diff --git a/vendor/lief/.circleci/config.yml b/vendor/lief/.circleci/config.yml deleted file mode 100644 index 48a9c0d..0000000 --- a/vendor/lief/.circleci/config.yml +++ /dev/null @@ -1,62 +0,0 @@ -version: 2.1 -jobs: - build: - macos: - xcode: 12.3.0 - steps: - - checkout: - path: ~/LIEF - - restore_cache: - keys: - - ccache-{{ arch }}-{{ .Branch }} - - ccache-{{ arch }}-master - - ccache-{{ arch }} - - pyenv - - run: - name: Install pyenv - command: | - brew install pyenv - pyenv root - pyenv install --list - - run: - name: Install ccache - command: brew install ccache - - run: - name: Install ninja - command: brew install ninja - - run: - name: CCache initialization - command: | - ccache --show-stats - ccache --zero-stats - ccache --max-size=10.0G - ccache --set-config=compiler_check=content - - run: - name: LIEF build setup - command: | - export PYTHON_CONFIGURE_OPTS="--enable-shared --enable-unicode=ucs2" - pyenv install --skip-existing 3.9.0 - export PYTHON_BINARY=$(pyenv root)/versions/3.9.0/bin/python3.9 - $PYTHON_BINARY -m pip install --upgrade pip setuptools wheel - $PYTHON_BINARY ./setup.py --ninja --lief-test build bdist_wheel - bash scripts/osx/package_sdk.sh - - run: - name: LIEF deploy - command: | - export PYTHON_BINARY=$(pyenv root)/versions/3.9.0/bin/python3.9 - $PYTHON_BINARY -m pip install --upgrade requests mako - $PYTHON_BINARY .github/deploy.py - - run: - name: ccache stats - when: always - command: | - ccache --show-stats - - save_cache: - key: 'ccache-{{ arch }}-{{ .Branch }}' - paths: [ "/home/circleci/.ccache" ] - - save_cache: - key: 'pyenv' - paths: [ "/home/circleci/.pyenv" ] - - - diff --git a/vendor/lief/.clang-format b/vendor/lief/.clang-format new file mode 100644 index 0000000..66f096a --- /dev/null +++ b/vendor/lief/.clang-format @@ -0,0 +1,118 @@ +--- +Language: Cpp +BasedOnStyle: LLVM +Standard: c++17 + +# Column limit +ColumnLimit: 83 + +# Indentation +IndentWidth: 2 +TabWidth: 2 +UseTab: Never +ContinuationIndentWidth: 4 +ConstructorInitializerIndentWidth: 2 +IndentCaseLabels: true +IndentCaseBlocks: false +IndentPPDirectives: BeforeHash +NamespaceIndentation: None +IndentWrappedFunctionNames: true +IndentAccessModifiers: false + +# Access modifiers at same level as class members +AccessModifierOffset: 0 + +# Constructor initializers: colon at end of line, each initializer on new line +BreakConstructorInitializers: AfterColon +PackConstructorInitializers: Never + +# Inheritance +BreakInheritanceList: BeforeColon + +# Pointer/Reference alignment: attached to type +PointerAlignment: Left +ReferenceAlignment: Pointer +DerivePointerAlignment: false + +# Spacing +SpaceBeforeParens: ControlStatements +SpaceBeforeCpp11BracedList: false +SpaceInEmptyBlock: false +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: false +SpaceBeforeAssignmentOperators: true +SpaceBeforeRangeBasedForLoopColon: true + +# Alignment +AlignAfterOpenBracket: Align +AlignOperands: Align +AlignTrailingComments: true +AlignConsecutiveAssignments: None +AlignConsecutiveDeclarations: false + +# Short forms +AllowShortFunctionsOnASingleLine: Empty +AllowShortIfStatementsOnASingleLine: Never +AllowShortLoopsOnASingleLine: false +AllowShortBlocksOnASingleLine: Never +AllowShortCaseLabelsOnASingleLine: true +AllowShortLambdasOnASingleLine: All +AllowShortEnumsOnASingleLine: true +AllowAllParametersOfDeclarationOnNextLine: true +AllowShortCaseExpressionOnASingleLine: true + +# Packing +BinPackArguments: true +BinPackParameters: true + +# Namespaces +CompactNamespaces: false +FixNamespaceComments: false + +# Empty lines +EmptyLineAfterAccessModifier: Never +EmptyLineBeforeAccessModifier: LogicalBlock +MaxEmptyLinesToKeep: 2 + +# Ternary operators stay at end of line +BreakBeforeTernaryOperators: false + +# Misc +Cpp11BracedListStyle: true +ReflowComments: true +InsertBraces: true +InsertNewlineAtEOF: true + +BreakTemplateDeclarations: Yes +BreakBeforeCloseBracketBracedList: true +BreakBeforeCloseBracketFunction: true +BreakBeforeTemplateCloser: true + +EnumTrailingComma: Insert +AlignConsecutiveMacros: + Enabled: true + AcrossEmptyLines: true + AcrossComments: true +BreakAfterReturnType: ExceptShortType +BreakBeforeBraces: Custom +BraceWrapping: + AfterCaseLabel: true + AfterControlStatement: MultiLine + +RemoveEmptyLinesInUnwrappedLines: true +RemoveSemicolon: true +QualifierAlignment: Left + + +# Includes - preserve existing order +SortIncludes: true +SortUsingDeclarations: LexicographicNumeric + +IncludeCategories: + - Regex: '^((<|")(spdlog|nanobind|catch2|utf8)/)' + Priority: 3 + - Regex: '<[[:alnum:].]+>' + Priority: 4 + - Regex: '.*' + Priority: 1 + SortPriority: 0 diff --git a/vendor/lief/.clang-format-ignore b/vendor/lief/.clang-format-ignore new file mode 100644 index 0000000..45c7af0 --- /dev/null +++ b/vendor/lief/.clang-format-ignore @@ -0,0 +1,4 @@ +api/python/** +third-party/** +src/runtime/osx/utils.h +tests/test_define_conflicts.cpp diff --git a/vendor/lief/.clang-tidy b/vendor/lief/.clang-tidy deleted file mode 100644 index ef58d54..0000000 --- a/vendor/lief/.clang-tidy +++ /dev/null @@ -1,35 +0,0 @@ -Checks: > - -*, - bugprone-*, - google-*, - misc-*, - modernize-*, - performance-*, - portability-*, - readability-*, - cppcoreguidelines-*, - -bugprone-easily-swappable-parameters, - -bugprone-narrowing-conversions, - -google-readability-namespace-comments, - -google-readability-todo, - -google-runtime-int, - -google-default-arguments - -google-runtime-references, - -misc-non-private-member-variables-in-classes, - -modernize-use-trailing-return-type, - -performance-noexcept-move-constructor, - -readability-function-cognitive-complexity, - -readability-inconsistent-declaration-parameter-name, - -readability-magic-numbers, - -readability-named-parameter, - -readability-redundant-string-cstr - -readability-uppercase-literal-suffix, - -# Turn all the warnings from the checks above into errors. -#WarningsAsErrors: "*" -UseColor: false - -CheckOptions: - - { key: readability-identifier-naming.PrivateMemberSuffix, value: _ } - - { key: readability-identifier-naming.ProtectedMemberSuffix, value: _ } - - { key: readability-identifier-naming.MacroDefinitionCase, value: UPPER_CASE } diff --git a/vendor/lief/.clang-tidy-core.yaml b/vendor/lief/.clang-tidy-core.yaml new file mode 100644 index 0000000..5d473ad --- /dev/null +++ b/vendor/lief/.clang-tidy-core.yaml @@ -0,0 +1,76 @@ +Checks: [ + -*, + bugprone-*, + performance-*, + portability-*, + cppcoreguidelines-*, + misc-*, + clang-taidy-*, + modernize-*, + + -clang-taidy-avoid-implicit-enum-to-integer-conversion, + -clang-taidy-avoid-high-cyclomatic-complexity, + + -modernize-use-trailing-return-type, + -modernize-use-nodiscard, + -modernize-avoid-c-arrays, + + # `modernize-avoid-c-style-cast` also rejects the functional-style suggested by + # `clang-taidy-avoid-static-integer-cast` (caught by -Wold-style-cast though) + -modernize-avoid-c-style-cast, + + -modernize-use-ranges, + -modernize-use-constraints, + -modernize-use-designated-initializers, + -modernize-use-integer-sign-comparison, + -modernize-use-string-view, + + -bugprone-derived-method-shadowing-base-method, + -bugprone-easily-swappable-parameters, + -bugprone-macro-parentheses, + -bugprone-narrowing-conversions, + -bugprone-reserved-identifier, + -bugprone-signed-bitwise, + -bugprone-signed-char-misuse, + -cppcoreguidelines-avoid-c-arrays, + -cppcoreguidelines-avoid-const-or-ref-data-members, + -cppcoreguidelines-avoid-do-while, + -cppcoreguidelines-avoid-magic-numbers, + -cppcoreguidelines-explicit-constructor, + -cppcoreguidelines-macro-to-enum, + -cppcoreguidelines-macro-usage, + -cppcoreguidelines-missing-std-forward, + -cppcoreguidelines-narrowing-conversions, + -cppcoreguidelines-non-private-member-variables-in-classes, + -cppcoreguidelines-owning-memory, + -cppcoreguidelines-pro-bounds-array-to-pointer-decay, + -cppcoreguidelines-pro-bounds-avoid-unchecked-container-access, + -cppcoreguidelines-pro-bounds-constant-array-index, + -cppcoreguidelines-pro-bounds-pointer-arithmetic, + -cppcoreguidelines-pro-type-const-cast, + -cppcoreguidelines-pro-type-reinterpret-cast, + -cppcoreguidelines-pro-type-static-cast-downcast, + -cppcoreguidelines-pro-type-union-access, + -cppcoreguidelines-special-member-functions, + -cppcoreguidelines-use-enum-class, + -misc-const-correctness, + -misc-explicit-constructor, + -misc-include-cleaner, + -misc-misplaced-const, + -misc-no-recursion, + -misc-non-private-member-variables-in-classes, + -misc-override-with-different-visibility, + -misc-static-assert, + -misc-use-anonymous-namespace, + -misc-use-internal-linkage, + -performance-enum-size, + -performance-no-int-to-ptr, + -portability-avoid-pragma-once, +] + +CheckOptions: + bugprone-unused-return-value.CheckedReturnTypes: '^::std::error_code$;^::std::error_condition$;^::std::errc$;^::std::expected$;^::LIEF::result$' + bugprone-unused-return-value.AllowCastToVoid: true + +HeaderFilterRegex: '.*' +ExcludeHeaderFilterRegex: '(builds|build|api/rust/include|utils/ordinals_lookup_tables_std|utils/ordinals_lookup_tables)/*' diff --git a/vendor/lief/.clangd b/vendor/lief/.clangd new file mode 100644 index 0000000..7533689 --- /dev/null +++ b/vendor/lief/.clangd @@ -0,0 +1,70 @@ +Documentation: + CommentFormat: Doxygen +Diagnostics: + Includes: + IgnoreHeader: + - spdlog/fmt/.* + - nanobind/stl/.* + - third-party/.* + ClangTidy: + FastCheckFilter: Strict + Add: [ + bugprone-*, + performance-*, + portability-*, + cppcoreguidelines-*, + modernize-*, + misc-*, + clang-taidy-*, + ] + Remove: [ + bugprone-easily-swappable-parameters, + bugprone-narrowing-conversions, + bugprone-reserved-identifier, + bugprone-signed-char-misuse, + cppcoreguidelines-avoid-c-arrays, + cppcoreguidelines-avoid-const-or-ref-data-members, + cppcoreguidelines-avoid-do-while, + cppcoreguidelines-avoid-magic-numbers, + cppcoreguidelines-explicit-constructor, + cppcoreguidelines-missing-std-forward, + cppcoreguidelines-narrowing-conversions, + cppcoreguidelines-non-private-member-variables-in-classes, + cppcoreguidelines-owning-memory, + cppcoreguidelines-pro-bounds-array-to-pointer-decay, + cppcoreguidelines-pro-bounds-constant-array-index, + cppcoreguidelines-pro-bounds-pointer-arithmetic, + cppcoreguidelines-pro-type-const-cast, + cppcoreguidelines-pro-type-reinterpret-cast, + cppcoreguidelines-pro-type-static-cast-downcast, + cppcoreguidelines-pro-type-union-access, + misc-explicit-constructor, + misc-misplaced-const, + misc-no-recursion, + misc-non-private-member-variables-in-classes, + misc-use-anonymous-namespace, + misc-use-internal-linkage, + misc-static-assert, + modernize-avoid-c-arrays, + modernize-concat-nested-namespaces, + modernize-make-unique, + modernize-use-nodiscard, + modernize-use-noexcept, + modernize-use-trailing-return-type, + performance-enum-size, + performance-no-int-to-ptr, + ] +--- +If: + PathMatch: + - api/rust/include/LIEF/.* +CompileFlags: + Remove: [-std=gnu++17] + Add: [-std=gnu++20] + +--- +If: + PathMatch: + - include/LIEF/.* + PathExclude: + - api/rust/.* diff --git a/vendor/lief/.coveragerc b/vendor/lief/.coveragerc new file mode 100644 index 0000000..828d7cd --- /dev/null +++ b/vendor/lief/.coveragerc @@ -0,0 +1,43 @@ +[paths] +source = + tests/ + +[run] +branch = True +relative_files = True +omit = + */api/python/* + */tests/utils.py + */tests/conftest.py + */tests/run_pytest.py + ; Require LIEF extended + */tests/coff/test_disassembler.py + */tests/api/test_demangle.py + */tests/dwarf/* + */tests/objc/* + */tests/assembly/* + */tests/pdb/* + */tests/dyld-shared-cache/* + +[report] +; Regexes for lines to exclude from consideration +exclude_also = + ; Don't complain about missing debug-only code: + def __repr__ + if self\.debug + + ; Don't complain if tests don't hit defensive assertion code: + raise AssertionError + raise NotImplementedError + raise RuntimeError + + ; Don't complain if non-runnable code isn't run: + if 0: + if __name__ == .__main__.: + if lief.__extended__: + if stderr: + if not file.exists(): + + ; Don't complain about these markers + @pytest\.mark\.lief_extended + @pytest\.mark\.slow diff --git a/vendor/lief/.dockerignore b/vendor/lief/.dockerignore deleted file mode 100644 index 378eac2..0000000 --- a/vendor/lief/.dockerignore +++ /dev/null @@ -1 +0,0 @@ -build diff --git a/vendor/lief/.github/FUNDING.yml b/vendor/lief/.github/FUNDING.yml new file mode 100644 index 0000000..2bd6368 --- /dev/null +++ b/vendor/lief/.github/FUNDING.yml @@ -0,0 +1 @@ +github: [lief-project] diff --git a/vendor/lief/.github/ISSUE_TEMPLATE/feature-request.md b/vendor/lief/.github/ISSUE_TEMPLATE/feature-request.md new file mode 100644 index 0000000..d092471 --- /dev/null +++ b/vendor/lief/.github/ISSUE_TEMPLATE/feature-request.md @@ -0,0 +1,12 @@ +--- +name: Feature Request +about: Suggest an idea for this project +title: '' +labels: '' +assignees: '' + +--- + +*Please describe what you would like to have in LIEF*. + +**Note: If the feature is not precise or if you want to have feedback first, you can open a [discussion](https://github.com/lief-project/LIEF/discussions).** diff --git a/vendor/lief/.github/ISSUE_TEMPLATE/premium-issue.md b/vendor/lief/.github/ISSUE_TEMPLATE/premium-issue.md new file mode 100644 index 0000000..a35a96b --- /dev/null +++ b/vendor/lief/.github/ISSUE_TEMPLATE/premium-issue.md @@ -0,0 +1,33 @@ +--- +name: Premium Issue +about: You need a fix for the issue with a high priority +title: '' +labels: Premium +assignees: romainthomas + +--- + +*Premium issues can be used to get a higher priority resolution for users and companies.* +*In return, you need to contribute to the project with an action:* + +- Writing a guest blog post here: https://lief-project.github.io/blog/ +- Fixing another issue +- Sponsoring the issue + +*Premium issues will be highlighted in the changelog and the release blog post with your name/logo* + +---------------------------------- + +**Description** + +*Please describe the issue/request that needs to be addressed* + +**Context** + +*Please provide the version of LIEF, the operating system as well as the binaries associated with the issue +(it can be sent by email as well)* + +---------------------------------- + + +**Reach out to `issue@lief.re` to discuss about the timeline/contribution.** diff --git a/vendor/lief/.github/ISSUE_TEMPLATE/regular-issue.md b/vendor/lief/.github/ISSUE_TEMPLATE/regular-issue.md new file mode 100644 index 0000000..df692a7 --- /dev/null +++ b/vendor/lief/.github/ISSUE_TEMPLATE/regular-issue.md @@ -0,0 +1,33 @@ +--- +name: Regular Issue +about: You identified a bug or a problem in LIEF +title: '' +labels: '' +assignees: romainthomas +--- + +**Describe the bug** +A clear and concise description of what the bug is. + +**To Reproduce** +Steps to reproduce the behavior: + +**Expected behavior** +A clear and concise description of what you expected to happen (if applicable) + +**Environment (please complete the following information):** + - System and Version : [e.g. Ubuntu 16.04] + - Target format (PE, ELF, Mach-O) + - LIEF commit version: ``python -c "import lief;print(lief.__version__)"`` or the one from ``LIEF/config.h`` + +**Additional context** +Add any other context about the problem here. + + +**NOTICE** + +If the issue does not contain enough information to be reproduced, +it will be flagged as [incomplete](https://github.com/lief-project/LIEF/issues?q=is%3Aissue+is%3Aclosed+label%3AIncomplete) +and closed. + +**/NOTICE** diff --git a/vendor/lief/.github/assets/index.j2 b/vendor/lief/.github/assets/index.j2 new file mode 100644 index 0000000..362bfcf --- /dev/null +++ b/vendor/lief/.github/assets/index.j2 @@ -0,0 +1,10 @@ + + +Links for lief + +

Links for lief

+% for path, filename in files: + ${filename}
+% endfor + + diff --git a/vendor/lief/.github/config/gh-ci.toml b/vendor/lief/.github/config/gh-ci.toml new file mode 100644 index 0000000..1416865 --- /dev/null +++ b/vendor/lief/.github/config/gh-ci.toml @@ -0,0 +1,9 @@ +[lief.s3] +region = "fr-par" +bucket = "lief" +endpoint = "https://s3.fr-par.scw.cloud" + +[lief.deploy] +branches = ["main", "master", "deploy", "devel"] +main-branches = ["main", "master"] +default-dir = "latest" diff --git a/vendor/lief/.github/deploy-key.enc b/vendor/lief/.github/deploy-key.enc new file mode 100644 index 0000000..761db54 Binary files /dev/null and b/vendor/lief/.github/deploy-key.enc differ diff --git a/vendor/lief/.github/deploy.py b/vendor/lief/.github/deploy.py new file mode 100644 index 0000000..44d3ed5 --- /dev/null +++ b/vendor/lief/.github/deploy.py @@ -0,0 +1,309 @@ +#!/usr/bin/env python3 +from botocore.exceptions import ClientError +from mako.template import Template +from pathlib import Path +from typing import Any, Optional + +import argparse +import boto3 +import functools +import logging +import os +import sys +import tempfile +import tomli +import re + +LOG_LEVEL = logging.INFO + +CURRENTDIR = Path(__file__).resolve().parent +REPODIR = CURRENTDIR.parent +ASSET_DIR = CURRENTDIR / "assets" +CONFIG_DIR = CURRENTDIR / "config" +LIEF_S3_KEY = os.getenv("LIEF_S3_KEY", None) +LIEF_S3_SECRET = os.getenv("LIEF_S3_SECRET", None) +OWNED_ORGS = ["lief-project/", "romainthomas/"] +RELEASE_KEYWORD = ["release-", "release/"] + +DEFAULT_CONFIG = CONFIG_DIR / "gh-ci.toml" +DEFAULT_TEMPLATE = (ASSET_DIR / "index.j2").read_text() + +logging.getLogger().addHandler(logging.StreamHandler(stream=sys.stdout)) +logging.getLogger().setLevel(LOG_LEVEL) +logger = logging.getLogger(__name__) + +if LIEF_S3_KEY is None or len(LIEF_S3_KEY) == 0: + logger.error("LIEF_S3_KEY is not set!") + +if LIEF_S3_SECRET is None or len(LIEF_S3_SECRET) == 0: + logger.error("LIEF_S3_SECRET is not set!") + +class S3Manager: + def __init__(self, dirname: str, bucket: str, + region: str, endpoint: str, + dry_run: bool = False): + self._s3_dirname: str = dirname + self._s3_bucket: str = bucket + self._s3_region: str = region + self._s3_endpoint: str = endpoint + self._dry_run: bool = dry_run + + logger.info("[S3] Bucket : %s", self._s3_bucket) + logger.info("[S3] Region : %s", self._s3_region) + logger.info("[S3] Endpoint: %s", self._s3_endpoint) + logger.info("[S3] Dir : %s", self._s3_dirname) + + def change_dir(self, dirname: str): + self._s3_dirname = dirname + + @property + def s3_lief_sdk(self) -> str: + return f"{self._s3_dirname}/sdk" + + @property + def s3_lief_wheel(self) -> str: + return f"{self._s3_dirname}/lief" + + @property + def url(self): + return f"https://{self._s3_bucket}.s3-website.{self._s3_region}.scw.cloud/{self._s3_dirname}" + + @functools.lru_cache(maxsize=1) + def s3(self) -> boto3.Session: + s3_res = boto3.resource( + 's3', + region_name=self._s3_region, + use_ssl=True, + endpoint_url=self._s3_endpoint, + aws_access_key_id=LIEF_S3_KEY, + aws_secret_access_key=LIEF_S3_SECRET + ) + return s3_res + + @classmethod + def from_config(cls, config): + pass + + def _s3_push(self, file: Path, dst: str): + logger.info("Uploading %s to %s", file, dst) + try: + obj = self.s3().Object(self._s3_bucket, dst) + if not self._dry_run: + obj.put(Body=file.read_bytes()) + else: + logger.info("[--] put: %s/%s - %s", self._s3_bucket, dst, file.as_posix()) + return 0 + except ClientError as e: + logger.error("S3 push failed: %s", e) + return 1 + + def push_wheel(self, file: str): + wheel_file = Path(file) + if not wheel_file.is_file(): + logger.error("'%s' is not a valid file!", wheel_file) + return + + dst = f"{self.s3_lief_wheel}/{wheel_file.name}" + self._s3_push(wheel_file, dst) + + def push_sdk(self, file: str): + sdk_path = Path(file) + if not sdk_path.is_file(): + logger.error("'%s' is not a valid file!", sdk_path) + return + + dst = f"{self.s3_lief_sdk}/{sdk_path.name}" + self._s3_push(sdk_path, dst) + + def push_content(self, content: str, dst: str): + with tempfile.TemporaryDirectory() as tmp: + tmp_path = Path(tmp) + index = tmp_path / "index.html" + index.write_text(content) + self._s3_push(index, dst) + + def process_sdk_wheels(self, directory: Path, maxdepth: int = 0, + depth: int = 0, recurse: bool = True, + skip_sdk: bool = False): + logger.info("Processing directory: %s", directory) + for item in directory.iterdir(): + if item.is_dir() and recurse: + if 0 < maxdepth < depth: + logger.debug("Maximum iteration depth reached") + else: + self.process_sdk_wheels(item, maxdepth, depth + 1, recurse) + elif item.is_file(): + extension = item.suffix + if extension in (".zip", ".gz") and not skip_sdk: + logger.info("[SDK ] Uploading '%s'", item.as_posix()) + self.push_sdk(item.as_posix()) + elif extension in (".whl", ): + logger.info("[WHEEL] Uploading '%s'", item.as_posix()) + self.push_wheel(item.as_posix()) + + + def upload_wheels_sdk(self, src_dir: Path, maxdepth: int, skip_sdk: bool): + logger.info("Looking for wheels and sdk from: %s", src_dir) + self.process_sdk_wheels(src_dir, maxdepth=maxdepth, recurse=True, + skip_sdk=skip_sdk) + + wheels_index = self.generate_index(self.s3_lief_wheel, + DEFAULT_TEMPLATE, + skiplist=("index.html", )) + + sdk_index = self.generate_index(self.s3_lief_sdk, DEFAULT_TEMPLATE, + skiplist=("index.html", )) + + self.push_content(wheels_index, f"{self.s3_lief_wheel}/index.html") + self.push_content(sdk_index, f"{self.s3_lief_sdk}/index.html") + + logger.info("Done!") + logger.info("URL: %s/%s", self.url, "sdk") + logger.info("URL: %s/%s", self.url, "lief") + + def s3_list(self, dirname: str) -> list[Any]: + if self._dry_run: + return [] + return self.s3().Bucket(self._s3_bucket).objects.filter(Prefix=dirname) + + def generate_index(self, dirname: str, template: str, skiplist=None): + files = self.s3_list(dirname) + selected_files = [] + for s3_object in files: + filename = Path(s3_object.key).name + if skiplist is not None and filename in skiplist: + continue + selected_files.append((s3_object.key, filename)) + return Template(template).render(files=selected_files) + +class GithubDeploy: + def __init__(self, branches: list[str], + main_branches: list[str], + default_dir: str, + s3_manager: S3Manager): + self.s3_manager: S3Manager = s3_manager + + self._branches: list[str] = branches + self._main_branches: list[str] = main_branches + self._default_dir: str = default_dir + + + @classmethod + def from_config(cls, config_file: Path): + with open(config_file, "rb") as f: + toml_config = tomli.load(f) + + if "lief" not in toml_config: + logger.warning("Missing lief entries in '%s'", config_file) + return None + lief_conf = toml_config["lief"] + + if "s3" not in lief_conf: + logger.warning("Missing lief.s3 entries in '%s'", config_file) + return None + + if "deploy" not in lief_conf: + logger.warning("Missing lief.deploy entries in '%s'", config_file) + return None + + branches = lief_conf["deploy"]["branches"] + main_branches = lief_conf["deploy"]["main-branches"] + default_dir = lief_conf["deploy"]["default-dir"] + s3_config = lief_conf["s3"] + s3_region = s3_config["region"] + s3_bucket = s3_config["bucket"] + s3_endpoint = s3_config["endpoint"] + + s3_manager = S3Manager(default_dir, s3_bucket, s3_region, s3_endpoint) + return cls(branches, main_branches, default_dir, s3_manager) + + @staticmethod + def branch() -> Optional[str]: + ref = os.getenv("GITHUB_REF") + if ref is None: + return None + return ref.replace("refs/heads/", "") + + @staticmethod + def is_pr() -> bool: + head_ref = os.getenv("GITHUB_HEAD_REF", "") + repo_path = os.getenv("GITHUB_REPOSITORY", "") + is_owned_repo = any(repo_path.startswith(org) for org in OWNED_ORGS) + return head_ref != "" or not is_owned_repo + + @staticmethod + def is_tagged() -> bool: + tag = GithubDeploy.tag_name() + return tag is not None and len(tag) > 0 + + @staticmethod + def tag_name() -> Optional[str]: + ref = os.getenv("GITHUB_REF", "") + logger.info("Github Action tag: %s", ref) + if ref.startswith("refs/tags/"): + return ref.replace("refs/tags/", "") + return "" + + @staticmethod + def workspace() -> str: + return os.getenv("GITHUB_WORKSPACE", "") + + def is_main_branch(self, name: str) -> bool: + return name in self._main_branches + + def should_be_deployed(self, branch: str) -> bool: + if any(re.match(s, branch) for s in self._branches): + return True + + return False + + def deploy(self, directories: list[str], skip_sdk: bool = False): + s3dir = None + + branch = GithubDeploy.branch() + + if branch is None: + logger.warning("Can't resolve the branch name") + sys.exit(1) + + s3dir = self._default_dir + + if not self.should_be_deployed(branch): + logger.info("Skipping deployment for branch: %s", branch) + return + + if s3dir is None: + logger.error("Target directory is not set") + sys.exit(1) + + logger.info("s3dir: %s", s3dir) + self.s3_manager.change_dir(s3dir) + for dirname in directories: + dirpath = Path(dirname).resolve().absolute().expanduser() + self.s3_manager.upload_wheels_sdk(dirpath, maxdepth=1, + skip_sdk=skip_sdk) + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("--config", "-c") + parser.add_argument("--dry-run", "-n", action="store_true", default=False) + parser.add_argument("--skip-sdk", action="store_true", default=False) + parser.add_argument("directories", nargs="+") + + args = parser.parse_args() + config_path = None + if args.config is not None: + config_path = Path(args.config) + else: + config_path = DEFAULT_CONFIG + + if not config_path.is_file(): + logger.error("'%s' is not a valid config path") + sys.exit(1) + + gh_deploy = GithubDeploy.from_config(config_path) + gh_deploy.deploy(args.directories, args.skip_sdk) + +if __name__ == "__main__": + main() + sys.exit(0) diff --git a/vendor/lief/.github/images/architecture.png b/vendor/lief/.github/images/architecture.png new file mode 100644 index 0000000..b842c06 Binary files /dev/null and b/vendor/lief/.github/images/architecture.png differ diff --git a/vendor/lief/.github/make_index.py b/vendor/lief/.github/make_index.py new file mode 100644 index 0000000..3867101 --- /dev/null +++ b/vendor/lief/.github/make_index.py @@ -0,0 +1,42 @@ +""" Build index from directory listing +From: https://stackoverflow.com/questions/39048654/how-to-enable-directory-indexing-on-github-pages + +make_index.py +""" + +INDEX_TEMPLATE = r""" + +Links for lief + +

Links for lief

+% for name in names: + ${name}
+% endfor + + +""" + +EXCLUDED = ['index.html', '.gitkeep'] +BASE_URL = "https://lief-project.github.io" + +import os +import argparse + +# May need to do "pip install mako" +from mako.template import Template + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("directory") + parser.add_argument("--base") + parser.add_argument("--output") + args = parser.parse_args() + fnames = [fname for fname in sorted(os.listdir(args.directory)) + if fname not in EXCLUDED] + html = Template(INDEX_TEMPLATE).render(names=fnames, base_url=BASE_URL, base=args.base) + with open(args.output, "w") as f: + f.write(html) + +if __name__ == '__main__': + main() diff --git a/vendor/lief/.github/requirements.txt b/vendor/lief/.github/requirements.txt new file mode 100644 index 0000000..00c8e8b --- /dev/null +++ b/vendor/lief/.github/requirements.txt @@ -0,0 +1,7 @@ +setuptools +boto3 +requests +twine +tomli +mako +wheel diff --git a/vendor/lief/.github/workflows/android.yml b/vendor/lief/.github/workflows/android.yml new file mode 100644 index 0000000..2274350 --- /dev/null +++ b/vendor/lief/.github/workflows/android.yml @@ -0,0 +1,84 @@ +name: 'Android' +on: + push: + branches: + - 'main' + tags-ignore: + - '**' + +jobs: + build-sdk: + runs-on: ubuntu-latest + strategy: + matrix: + arch: ['arm', 'arm64'] + fail-fast: false + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ~/.ccache + key: android-${{ runner.os }}-${{ matrix.arch }}-${{ steps.get-date.outputs.date }} + restore-keys: | + android-${{ runner.os }}-${{ matrix.arch }} + - name: Build SDK [${{ matrix.arch }}] + shell: bash + env: + ARCH: ${{ matrix.arch }} + run: | + docker run \ + -e CCACHE_COMPRESS=1 \ + -e CCACHE_MAXSIZE=10.0G \ + -e CCACHE_CPP2=1 \ + -e CCACHE_DIR=/ccache \ + -v $GITHUB_WORKSPACE:/work \ + -v $HOME/.ccache:/ccache \ + --rm liefproject/android-${ARCH} bash /work/scripts/docker/android-sdk-${ARCH} + - name: 'Upload Artifact' + uses: actions/upload-artifact@v7 + with: + name: android-sdk-${{ matrix.arch }} + path: build/*.tar.gz + retention-days: 3 + deploy: + if: ${{ always() }} + runs-on: ubuntu-latest + needs: build-sdk + steps: + - uses: actions/checkout@v5 + with: + fetch-depth: 0 + - name: Download artifacts + uses: actions/download-artifact@v8 + with: + path: ${{ runner.temp }}/artifacts + - name: Display artifacts + run: ls -R + working-directory: ${{ runner.temp }}/artifacts + - name: Deploy + env: + LIEF_S3_KEY: ${{ secrets.LIEF_S3_KEY }} + LIEF_S3_SECRET: ${{ secrets.LIEF_S3_SECRET }} + shell: bash + run: | + docker run --rm \ + -v $GITHUB_WORKSPACE:/src \ + -v $RUNNER_TEMP:/runner_tmp \ + -e GITHUB_ACTIONS="true" \ + -e GITHUB_WORKSPACE=$GITHUB_WORKSPACE \ + -e GITHUB_REF=$GITHUB_REF \ + -e GITHUB_REPOSITORY=$GITHUB_REPOSITORY \ + -e LIEF_S3_KEY=$LIEF_S3_KEY \ + -e LIEF_S3_SECRET=$LIEF_S3_SECRET \ + liefproject/deploy python3 /src/.github/deploy.py /runner_tmp/artifacts + + + diff --git a/vendor/lief/.github/workflows/linux-s390x.yml b/vendor/lief/.github/workflows/linux-s390x.yml new file mode 100644 index 0000000..16def51 --- /dev/null +++ b/vendor/lief/.github/workflows/linux-s390x.yml @@ -0,0 +1,252 @@ +name: 'Linux s390x' +on: + push: + branches: + - 'main' + tags-ignore: + - '**' + +jobs: + linux-sdk: + runs-on: [self-hosted, linux, s390x] + container: + image: liefproject/manylinux_2_28_s390x + env: + CCACHE_DIR: "/home/pylief/.ccache" + CXXFLAGS: "-ffunction-sections -fdata-sections -fvisibility-inlines-hidden -static-libstdc++ -static-libgcc" + CFLAGS: "-ffunction-sections -fdata-sections -static-libstdc++ -static-libgcc" + LDFLAGS: "-Wl,--gc-sections -Wl,--exclude-libs,ALL" + BUILD_DIR_STATIC: "/tmp/build/linux-s390x/static-release" + BUILD_DIR_SHARED: "/tmp/build/linux-s390x/shared-release" + CLICOLOR_FORCE: "1" + ACTIONS_RUNTIME_URL: "${{ env.ACTIONS_RUNTIME_URL }}" + ACTIONS_RUNTIME_TOKEN: "${{ env.ACTIONS_RUNTIME_TOKEN }}" + ACTIONS_CACHE_URL: "${{ env.ACTIONS_CACHE_URL }}" + options: --user 1001:1001 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Prepare ccache + shell: bash + run: | + mkdir -p /home/pylief/.ccache/tmp + - name: ccache cache files + uses: actions/cache@v5 + with: + path: /home/pylief/.ccache + key: linux-s390x-${{ runner.os }}-sdk-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-s390x-${{ runner.os }}-sdk + - name: CMake - Static + shell: bash + run: | + mkdir -p ${BUILD_DIR_STATIC} + cmake -S $GITHUB_WORKSPACE -B ${BUILD_DIR_STATIC} -GNinja \ + -DCMAKE_INSTALL_LIBDIR="lib" \ + -DCMAKE_LINK_WHAT_YOU_USE=on \ + -DBUILD_SHARED_LIBS=off \ + -DLIEF_INSTALL_COMPILED_EXAMPLES=on \ + -DCMAKE_INSTALL_PREFIX=/install \ + -DCMAKE_BUILD_TYPE=Release + - name: Compile - Static + shell: bash + run: | + cmake --build ${BUILD_DIR_STATIC} --target install + - name: CMake - Shared + shell: bash + run: | + mkdir -p ${BUILD_DIR_SHARED} + cmake -S $GITHUB_WORKSPACE -B ${BUILD_DIR_SHARED} -GNinja \ + -DCMAKE_INSTALL_LIBDIR="lib" \ + -DCMAKE_LINK_WHAT_YOU_USE=on \ + -DBUILD_SHARED_LIBS=on \ + -DLIEF_INSTALL_COMPILED_EXAMPLES=off \ + -DCMAKE_BUILD_TYPE=Release + - name: Compile - Shared + run: | + cmake --build ${BUILD_DIR_SHARED} --target all + - name: Package + run: | + cd /tmp/build/linux-s390x + cpack --config $GITHUB_WORKSPACE/cmake/cpack.config.cmake + - name: 'Upload SDK Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-s390x-sdk + path: /tmp/build/linux-s390x/*.tar.gz + retention-days: 3 + - name: 'Upload Install Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-s390x-install + path: /install + retention-days: 1 + + testing: + if: "!contains(github.event.commits[0].message, '[skip-test]')" + runs-on: [self-hosted, linux, s390x] + container: + image: liefproject/manylinux_2_28_s390x + env: + PYTHON_BINARY: "/opt/python/cp312-cp312/bin/python3.12" + LIEF_SAMPLES_DIR: "/tmp/samples" + LIEF_BUILD_DIR: "/tmp/lief-build" + LIEF_VENV: "/tmp/venv" + CLICOLOR_FORCE: "1" + PYTEST_ADDOPTS: "--color=yes" + options: --user 1001:1001 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ~/.ccache + key: linux-s390x-${{ runner.os }}-test-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-s390x-${{ runner.os }}-test + - name: Prepare Python virtual env + shell: bash + run: | + $PYTHON_BINARY -m venv ${LIEF_VENV} + source ${LIEF_VENV}/bin/activate + python -m pip install \ + -r tests/requirements.txt \ + -r api/python/build-requirements.txt + - name: Build & install LIEF + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + export PYLIEF_CONF="${GITHUB_WORKSPACE}/scripts/docker/config/pylinux-test-s390x.toml" + python -m pip -vvv install api/python + - name: Prepare test samples + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + mkdir -p ${LIEF_SAMPLES_DIR} + python tests/dl_samples.py ${LIEF_SAMPLES_DIR} + - name: Run tests + timeout-minutes: 5 + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + python tests/run_pytest.py + python tests/run_tools_check.py ${LIEF_BUILD_DIR}/ + ctest --output-on-failure --test-dir ${LIEF_BUILD_DIR}/ + + pywheels: + runs-on: [self-hosted, linux, s390x] + needs: linux-sdk + container: + image: liefproject/manylinux_2_28_s390x + env: + CCACHE_DIR: "/home/pylief/.ccache" + CXXFLAGS: "-ffunction-sections -fdata-sections -fvisibility-inlines-hidden -static-libgcc" + CFLAGS: "-ffunction-sections -fdata-sections -static-libgcc" + LDFLAGS: "-Wl,--gc-sections -Wl,--exclude-libs,ALL" + CLICOLOR_FORCE: "1" + FORCE_COLOR: "1" + LIEF_BUILD_DIR: "/tmp/lief-build" + ACTIONS_RUNTIME_URL: "${{ env.ACTIONS_RUNTIME_URL }}" + ACTIONS_RUNTIME_TOKEN: "${{ env.ACTIONS_RUNTIME_TOKEN }}" + ACTIONS_CACHE_URL: "${{ env.ACTIONS_CACHE_URL }}" + options: --user 1001:1001 + strategy: + matrix: + python-version: ['3.12', '3.13', '3.14'] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Prepare ccache + shell: bash + run: | + mkdir -p /home/pylief/.ccache/tmp + - name: ccache cache files + uses: actions/cache@v5 + with: + path: /home/pylief/.ccache + key: linux-s390x-${{ runner.os }}-${{ matrix.python-version }}-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-s390x-${{ runner.os }}-${{ matrix.python-version }} + - name: Download LIEF install dir + uses: actions/download-artifact@v8 + with: + name: linux-s390x-install + path: /install + - name: Generate wheel + env: + PYTHON_VERSION: ${{ matrix.python-version }} + shell: bash + run: | + export PYLIEF_CONF=$GITHUB_WORKSPACE/scripts/docker/config/pylinux-s390x.toml + PYTHON_VERSION_ALT=$(echo "${PYTHON_VERSION}" | sed 's/\.//') # Transform 3.12 -> 312 + PYTHON_BINARY=/opt/python/cp${PYTHON_VERSION_ALT}-cp${PYTHON_VERSION_ALT}/bin/python${PYTHON_VERSION} + $PYTHON_BINARY -m pip -vvv wheel --disable-pip-version-check \ + --wheel-dir=$GITHUB_WORKSPACE/wheel_stage \ + $GITHUB_WORKSPACE/api/python + - name: Run auditwheel + shell: bash + run: | + ls -alh $GITHUB_WORKSPACE/wheel_stage + find $GITHUB_WORKSPACE/wheel_stage -exec \ + auditwheel repair -w $GITHUB_WORKSPACE/dist {} \; + ls -alh $GITHUB_WORKSPACE/dist + - name: 'Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-s390x-python${{ matrix.python-version }}-wheel + path: dist/*.whl + retention-days: 3 + + deploy: + runs-on: ubuntu-latest + if: ${{ always() }} + needs: [pywheels] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Download artifacts + uses: actions/download-artifact@v8 + with: + pattern: linux-s390x-* + merge-multiple: true + path: ${{ runner.temp }}/artifacts + - name: Display artifacts + run: ls -R + working-directory: ${{ runner.temp }}/artifacts + - name: Deploy + env: + LIEF_S3_KEY: ${{ secrets.LIEF_S3_KEY }} + LIEF_S3_SECRET: ${{ secrets.LIEF_S3_SECRET }} + shell: bash + run: | + docker run --rm \ + -v $GITHUB_WORKSPACE:/src \ + -v $RUNNER_TEMP:/runner_tmp \ + -e GITHUB_ACTIONS="true" \ + -e GITHUB_WORKSPACE=$GITHUB_WORKSPACE \ + -e GITHUB_REF=$GITHUB_REF \ + -e GITHUB_REPOSITORY=$GITHUB_REPOSITORY \ + -e LIEF_S3_KEY=$LIEF_S3_KEY \ + -e LIEF_S3_SECRET=$LIEF_S3_SECRET \ + liefproject/deploy \ + python3 /src/.github/deploy.py --skip-sdk /runner_tmp/artifacts diff --git a/vendor/lief/.github/workflows/linux-x86-64.yml b/vendor/lief/.github/workflows/linux-x86-64.yml new file mode 100644 index 0000000..f353b65 --- /dev/null +++ b/vendor/lief/.github/workflows/linux-x86-64.yml @@ -0,0 +1,277 @@ +name: 'Linux x86-64' +on: + push: + branches: + - 'main' + tags-ignore: + - '**' + +jobs: + linux-sdk: + runs-on: ubuntu-latest + container: + image: liefproject/manylinux_2_28_x86_64 + env: + CCACHE_DIR: "/home/pylief/.ccache" + CXXFLAGS: "-ffunction-sections -fdata-sections -fvisibility-inlines-hidden -static-libstdc++ -static-libgcc" + CFLAGS: "-ffunction-sections -fdata-sections -static-libstdc++ -static-libgcc" + LDFLAGS: "-Wl,--gc-sections -Wl,--exclude-libs,ALL" + BUILD_DIR_STATIC: "/tmp/build/linux-x86-64/static-release" + BUILD_DIR_SHARED: "/tmp/build/linux-x86-64/shared-release" + CLICOLOR_FORCE: "1" + ACTIONS_RUNTIME_URL: "${{ env.ACTIONS_RUNTIME_URL }}" + ACTIONS_RUNTIME_TOKEN: "${{ env.ACTIONS_RUNTIME_TOKEN }}" + ACTIONS_CACHE_URL: "${{ env.ACTIONS_CACHE_URL }}" + options: --user 1001:1001 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Prepare ccache + shell: bash + run: | + mkdir -p /home/pylief/.ccache/tmp + - name: ccache cache files + uses: actions/cache@v5 + with: + path: /home/pylief/.ccache + key: linux-x86-64-${{ runner.os }}-sdk-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-x86-64-${{ runner.os }}-sdk + - name: CMake - Static + shell: bash + run: | + mkdir -p ${BUILD_DIR_STATIC} + cmake -S $GITHUB_WORKSPACE -B ${BUILD_DIR_STATIC} -GNinja \ + -DCMAKE_INSTALL_LIBDIR="lib" \ + -DCMAKE_LINK_WHAT_YOU_USE=on \ + -DBUILD_SHARED_LIBS=off \ + -DLIEF_INSTALL_COMPILED_EXAMPLES=on \ + -DCMAKE_INSTALL_PREFIX=/install \ + -DCMAKE_BUILD_TYPE=Release + - name: Compile - Static + shell: bash + run: | + cmake --build ${BUILD_DIR_STATIC} --target install + - name: CMake - Shared + shell: bash + run: | + mkdir -p ${BUILD_DIR_SHARED} + cmake -S $GITHUB_WORKSPACE -B ${BUILD_DIR_SHARED} -GNinja \ + -DCMAKE_INSTALL_LIBDIR="lib" \ + -DCMAKE_LINK_WHAT_YOU_USE=on \ + -DBUILD_SHARED_LIBS=on \ + -DLIEF_INSTALL_COMPILED_EXAMPLES=off \ + -DCMAKE_BUILD_TYPE=Release + - name: Compile - Shared + run: | + cmake --build ${BUILD_DIR_SHARED} --target all + - name: Package + run: | + cd /tmp/build/linux-x86-64 + cpack --config $GITHUB_WORKSPACE/cmake/cpack.config.cmake + - name: 'Upload SDK Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-x86-64-sdk + path: /tmp/build/linux-x86-64/*.tar.gz + retention-days: 3 + - name: 'Upload Install Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-x86-64-install + path: /install + retention-days: 1 + testing: + if: "!contains(github.event.commits[0].message, '[skip-test]')" + runs-on: ubuntu-latest + container: + image: liefproject/manylinux_2_28_x86_64 + env: + PYTHON_BINARY: "/opt/python/cp312-cp312/bin/python3.12" + LIEF_SAMPLES_DIR: "/tmp/samples" + LIEF_BUILD_DIR: "/tmp/lief-build" + LIEF_VENV: "/tmp/venv" + CLICOLOR_FORCE: "1" + PYTEST_ADDOPTS: "--color=yes" + options: --user 1001:1001 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ~/.ccache + key: linux-x86-64-${{ runner.os }}-test-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-x86-64-${{ runner.os }}-test + - name: Prepare Python virtual env + shell: bash + run: | + $PYTHON_BINARY -m venv ${LIEF_VENV} + source ${LIEF_VENV}/bin/activate + python -m pip install \ + -r tests/requirements.txt \ + -r api/python/build-requirements.txt + - name: Build & install LIEF + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + export PYLIEF_CONF="${GITHUB_WORKSPACE}/scripts/docker/config/pylinux-test-x64.toml" + python -m pip -vvv install api/python + - name: Prepare test samples + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + mkdir -p ${LIEF_SAMPLES_DIR} + python tests/dl_samples.py ${LIEF_SAMPLES_DIR} + - name: Run tests + timeout-minutes: 5 + shell: bash + run: | + source ${LIEF_VENV}/bin/activate + python tests/run_pytest.py + python tests/run_tools_check.py ${LIEF_BUILD_DIR}/ + ctest --output-on-failure --test-dir ${LIEF_BUILD_DIR}/ + - name: Fuzzing [ls x86-64] + shell: bash + timeout-minutes: 20 + run: | + source ${LIEF_VENV}/bin/activate + export PYTHONPATH="${GITHUB_WORKSPACE}/tests:$PYTHONPATH" + python tests/elf/fuzzing.py \ + ${LIEF_BUILD_DIR}/tests/Melkor/src/MELKOR/melkor \ + --input-seed ${LIEF_SAMPLES_DIR}/ELF/ELF64_x86-64_binary_ls.bin -n 100 + - name: Fuzzing [openssl x86-64] + shell: bash + timeout-minutes: 20 + run: | + source ${LIEF_VENV}/bin/activate + export PYTHONPATH="${GITHUB_WORKSPACE}/tests:$PYTHONPATH" + python tests/elf/fuzzing.py \ + ${LIEF_BUILD_DIR}/tests/Melkor/src/MELKOR/melkor \ + --input-seed ${LIEF_SAMPLES_DIR}/ELF/ELF64_x86-64_binary_openssl.bin -n 100 + - name: Fuzzing [nm x86-64] + shell: bash + timeout-minutes: 20 + run: | + source ${LIEF_VENV}/bin/activate + export PYTHONPATH="${GITHUB_WORKSPACE}/tests:$PYTHONPATH" + python tests/elf/fuzzing.py \ + ${LIEF_BUILD_DIR}/tests/Melkor/src/MELKOR/melkor \ + --input-seed ${LIEF_SAMPLES_DIR}/ELF/ELF64_x86-64_binary_nm.bin -n 100 + + pywheels: + runs-on: ubuntu-latest + needs: linux-sdk + container: + image: liefproject/manylinux_2_28_x86_64 + env: + CCACHE_DIR: "/home/pylief/.ccache" + CXXFLAGS: "-ffunction-sections -fdata-sections -fvisibility-inlines-hidden -static-libgcc" + CFLAGS: "-ffunction-sections -fdata-sections -static-libgcc" + LDFLAGS: "-Wl,--gc-sections -Wl,--exclude-libs,ALL" + CLICOLOR_FORCE: "1" + FORCE_COLOR: "1" + LIEF_BUILD_DIR: "/tmp/lief-build" + ACTIONS_RUNTIME_URL: "${{ env.ACTIONS_RUNTIME_URL }}" + ACTIONS_RUNTIME_TOKEN: "${{ env.ACTIONS_RUNTIME_TOKEN }}" + ACTIONS_CACHE_URL: "${{ env.ACTIONS_CACHE_URL }}" + options: --user 1001:1001 + strategy: + matrix: + python-version: ['3.12', '3.13', '3.14'] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Prepare ccache + shell: bash + run: | + mkdir -p /home/pylief/.ccache/tmp + - name: ccache cache files + uses: actions/cache@v5 + with: + path: /home/pylief/.ccache + key: linux-x86-64-${{ runner.os }}-${{ matrix.python-version }}-${{ steps.get-date.outputs.date }} + restore-keys: | + linux-x86-64-${{ runner.os }}-${{ matrix.python-version }} + - name: Download LIEF install dir + uses: actions/download-artifact@v8 + with: + name: linux-x86-64-install + path: /install + - name: Generate wheel + env: + PYTHON_VERSION: ${{ matrix.python-version }} + shell: bash + run: | + export PYLIEF_CONF=$GITHUB_WORKSPACE/scripts/docker/config/pylinux-x64.toml + PYTHON_VERSION_ALT=$(echo "${PYTHON_VERSION}" | sed 's/\.//') # Transform 3.8 -> 38 + PYTHON_BINARY=/opt/python/cp${PYTHON_VERSION_ALT}-cp${PYTHON_VERSION_ALT}/bin/python${PYTHON_VERSION} + $PYTHON_BINARY -m pip -vvv wheel --disable-pip-version-check \ + --wheel-dir=$GITHUB_WORKSPACE/wheel_stage \ + $GITHUB_WORKSPACE/api/python + - name: Run auditwheel + shell: bash + run: | + ls -alh $GITHUB_WORKSPACE/wheel_stage + find $GITHUB_WORKSPACE/wheel_stage -exec \ + auditwheel repair -w $GITHUB_WORKSPACE/dist {} \; + ls -alh $GITHUB_WORKSPACE/dist + - name: 'Artifact' + uses: actions/upload-artifact@v7 + with: + name: linux-x86-64-python${{ matrix.python-version }}-wheel + path: dist/*.whl + retention-days: 3 + deploy: + runs-on: ubuntu-latest + if: ${{ always() }} + needs: [pywheels] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Download artifacts + uses: actions/download-artifact@v8 + with: + pattern: linux-x86-64-* + merge-multiple: true + path: ${{ runner.temp }}/artifacts + - name: Display artifacts + run: ls -R + working-directory: ${{ runner.temp }}/artifacts + - name: Deploy + env: + LIEF_S3_KEY: ${{ secrets.LIEF_S3_KEY }} + LIEF_S3_SECRET: ${{ secrets.LIEF_S3_SECRET }} + shell: bash + run: | + docker run --rm \ + -v $GITHUB_WORKSPACE:/src \ + -v $RUNNER_TEMP:/runner_tmp \ + -e GITHUB_ACTIONS="true" \ + -e GITHUB_WORKSPACE=$GITHUB_WORKSPACE \ + -e GITHUB_REF=$GITHUB_REF \ + -e GITHUB_REPOSITORY=$GITHUB_REPOSITORY \ + -e LIEF_S3_KEY=$LIEF_S3_KEY \ + -e LIEF_S3_SECRET=$LIEF_S3_SECRET \ + liefproject/deploy \ + python3 /src/.github/deploy.py --skip-sdk /runner_tmp/artifacts diff --git a/vendor/lief/.github/workflows/osx.yml b/vendor/lief/.github/workflows/osx.yml new file mode 100644 index 0000000..6c7326d --- /dev/null +++ b/vendor/lief/.github/workflows/osx.yml @@ -0,0 +1,224 @@ +name: 'macOS' +on: + push: + branches: + - 'main' + tags-ignore: + - '**' + +env: + python-test-version: '3.13' + +jobs: + osx-sdk: + runs-on: macos-14 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Install system dependencies + run: | + brew install cmake ninja ccache + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Setup cache dir + shell: bash + run: | + mkdir -p $RUNNER_TEMP/.ccache + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ${{ runner.temp }}/.ccache + key: osx-${{ runner.os }}-sdk-${{ steps.get-date.outputs.date }} + restore-keys: | + osx-${{ runner.os }}-sdk + - name: Build SDK + shell: bash + env: + CLICOLOR_FORCE: "1" + MACOSX_DEPLOYMENT_TARGET: "11.0" + CCACHE_DIR: ${{ runner.temp }}/.ccache + CCACHE_MAXSIZE: 10.0G + CCACHE_CPP2: 1 + CCACHE_COMPRESS: 1 + run: | + bash scripts/osx/package_sdk.sh + - name: 'Upload SDK Artifact' + uses: actions/upload-artifact@v7 + with: + name: osx-sdk + path: build/*.tar.gz + retention-days: 3 + - name: 'Upload install artifact [arm64]' + uses: actions/upload-artifact@v7 + with: + name: osx-arm64-install + path: install/arm64 + retention-days: 1 + - name: 'Upload install artifact [x64]' + uses: actions/upload-artifact@v7 + with: + name: osx-x64-install + path: install/x64 + retention-days: 1 + osx-testing: + runs-on: macos-14 + if: "!contains(github.event.commits[0].message, '[skip-test]')" + steps: + - uses: actions/checkout@v5 + with: + fetch-depth: 0 + - name: Set up Python ${{ env.python-test-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ env.python-test-version }} + - name: Install system dependencies + run: | + brew install cmake ninja ccache + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Setup cache dir + shell: bash + run: | + mkdir -p $RUNNER_TEMP/.ccache + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ${{ runner.temp }}/.ccache + key: osx-${{ runner.os }}-test-${{ steps.get-date.outputs.date }} + restore-keys: | + osx-${{ runner.os }}-test + - name: Upgrade pip + shell: bash + run: | + python -m pip install --upgrade pip + - name: Build Python 3.13 with tests + shell: bash + env: + LIEF_SAMPLES_DIR: "/tmp/samples" + LIEF_BUILD_DIR: "/tmp/lief-build" + PYLIEF_CONF: "${{ github.workspace }}/scripts/osx/osx-testing-x64.toml" + CLICOLOR_FORCE: "1" + PYTEST_ADDOPTS: "--color=yes" + FORCE_COLOR: "1" + MACOSX_TARGET: "11.7" + MACOSX_DEPLOYMENT_TARGET: "11.0" + CCACHE_DIR: ${{ runner.temp }}/.ccache + CCACHE_MAXSIZE: 10.0G + CCACHE_CPP2: 1 + CCACHE_COMPRESS: 1 + run: | + python -m pip install -r tests/requirements.txt + python -m pip -vvv install api/python + python tests/dl_samples.py ${LIEF_SAMPLES_DIR} + - name: Run tests + shell: bash + timeout-minutes: 20 + env: + LIEF_SAMPLES_DIR: "/tmp/samples" + LIEF_BUILD_DIR: "/tmp/lief-build" + PYTEST_ADDOPTS: "--color=yes" + run: | + python tests/run_pytest.py + python tests/run_tools_check.py ${LIEF_BUILD_DIR}/ + ctest --output-on-failure --test-dir ${LIEF_BUILD_DIR}/ + wheels: + runs-on: macos-14 + needs: osx-sdk + strategy: + matrix: + python-version: ['3.12', '3.13', '3.14'] + arch: ['x64', 'arm64'] + fail-fast: false + steps: + - uses: actions/checkout@v5 + with: + fetch-depth: 0 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ matrix.python-version }} + - name: Install system dependencies + run: | + brew install cmake ninja ccache + python -m pip install --upgrade pip + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Setup cache dir + shell: bash + run: | + mkdir -p $RUNNER_TEMP/.ccache + - name: ccache cache files + uses: actions/cache@v5 + with: + path: ${{ runner.temp }}/.ccache + key: osx-${{ runner.os }}-${{ matrix.arch }}-${{ matrix.python-version }}-${{ steps.get-date.outputs.date }} + restore-keys: | + osx-${{ runner.os }}-${{ matrix.arch }}-${{ matrix.python-version }} + - name: Download LIEF install dir + uses: actions/download-artifact@v8 + with: + name: osx-${{ matrix.arch }}-install + path: ~/lief-${{ matrix.arch }}-install + - name: Build Python ${{ matrix.python-version }} [${{ matrix.arch }}] + shell: bash + env: + MACOSX_DEPLOYMENT_TARGET: "11.0" + FORCE_COLOR: "1" + CLICOLOR_FORCE: "1" + CCACHE_DIR: ${{ runner.temp }}/.ccache + CCACHE_MAXSIZE: 10.0G + CCACHE_CPP2: 1 + CCACHE_COMPRESS: 1 + PYLIEF_CONF: "${{ github.workspace }}/scripts/osx/py-${{ matrix.arch }}.toml" + run: | + python -m pip -vv wheel --wheel-dir=dist/ api/python + - name: 'Upload Python wheel artifact - ${{ matrix.python-version }}' + uses: actions/upload-artifact@v7 + with: + name: osx-wheel-${{ matrix.arch }}-${{ matrix.python-version }} + path: dist/*.whl + retention-days: 3 + deploy: + runs-on: ubuntu-latest + if: ${{ always() }} + needs: [wheels] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Download artifacts + uses: actions/download-artifact@v8 + with: + pattern: osx-* + merge-multiple: true + path: ${{ runner.temp }}/artifacts + - name: Display artifacts + run: ls -R + working-directory: ${{ runner.temp }}/artifacts + - name: Deploy + env: + LIEF_S3_KEY: ${{ secrets.LIEF_S3_KEY }} + LIEF_S3_SECRET: ${{ secrets.LIEF_S3_SECRET }} + shell: bash + run: | + docker run --rm \ + -v $GITHUB_WORKSPACE:/src \ + -v $RUNNER_TEMP:/runner_tmp \ + -e GITHUB_ACTIONS="true" \ + -e GITHUB_WORKSPACE=$GITHUB_WORKSPACE \ + -e GITHUB_REF=$GITHUB_REF \ + -e GITHUB_REPOSITORY=$GITHUB_REPOSITORY \ + -e LIEF_S3_KEY=$LIEF_S3_KEY \ + -e LIEF_S3_SECRET=$LIEF_S3_SECRET \ + liefproject/deploy \ + python3 /src/.github/deploy.py --skip-sdk /runner_tmp/artifacts diff --git a/vendor/lief/.github/workflows/pr.yml b/vendor/lief/.github/workflows/pr.yml new file mode 100644 index 0000000..6711597 --- /dev/null +++ b/vendor/lief/.github/workflows/pr.yml @@ -0,0 +1,92 @@ +name: LIEF PR +on: [pull_request, workflow_dispatch] + +env: + python-osx-version: '3.12' + python-win-version: '3.12' + +jobs: + osx: + runs-on: macos-14 + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ env.python-osx-version }} + - name: Install system dependencies + run: | + brew install cmake ninja ccache + python -m pip install --upgrade pip + - name: Build with Python ${{ env.python-osx-version }} & Test + shell: bash + env: + LIEF_SAMPLES_DIR: "/tmp/samples" + LIEF_BUILD_DIR: "/tmp/lief-build" + PYLIEF_CONF: "${{ github.workspace }}/scripts/osx/osx-testing-x64.toml" + run: | + python -m pip install -r tests/requirements.txt + python -m pip install -e api/python + python tests/dl_samples.py ${LIEF_SAMPLES_DIR} + python tests/run_pytest.py + python tests/run_tools_check.py ${LIEF_BUILD_DIR} + ctest --output-on-failure --test-dir ${LIEF_BUILD_DIR} + linux: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Build & Test + shell: bash + env: + PYTHON_VERSION: 312 + run: | + docker run --rm \ + -e PYTHON_VERSION=$PYTHON_VERSION \ + -e PYTHON_BINARY=/opt/python/cp312-cp312/bin/python3.12 \ + -v $GITHUB_WORKSPACE:/src \ + liefproject/manylinux_2_28_x86_64 \ + bash /src/scripts/docker/test-linux-x64 + windows: + runs-on: windows-latest + steps: + - uses: actions/checkout@v6 + - name: Set up Python ${{ env.python-win-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ env.python-win-version }} + architecture: x64 + - name: Install system dependencies + run: | + choco install ninja + python -m pip install --upgrade pip + - uses: ilammy/msvc-dev-cmd@v1 + with: + vsversion: "2022" + - name: Set env variables + run: | + chcp 65001 #set code page to utf-8 + echo ("LIEF_SAMPLES_DIR=" + $env:RUNNER_TEMP + "/samples") >> $env:GITHUB_ENV + echo ("LIEF_BUILD_DIR=" + $env:RUNNER_TEMP + "/lief-build") >> $env:GITHUB_ENV + echo ("PYLIEF_CONF=" + $env:GITHUB_WORKSPACE + "/scripts/windows/py-x64-test.toml") >> $env:GITHUB_ENV + - name: Build Python ${{ env.python-win-version }} + shell: pwsh + run: | + python -m pip install -r tests/requirements.txt + python -m pip install api/python + python tests/dl_samples.py $env:LIEF_SAMPLES_DIR + - name: Run tests - unittests + shell: pwsh + run: | + cd $env:GITHUB_WORKSPACE + ctest --output-on-failure --test-dir $env:LIEF_BUILD_DIR + Exit $LASTEXITCODE + - name: Run tests - python + shell: pwsh + run: | + cd $env:GITHUB_WORKSPACE + python tests/run_pytest.py + Exit $LASTEXITCODE diff --git a/vendor/lief/.github/workflows/windows-all.yml b/vendor/lief/.github/workflows/windows-all.yml new file mode 100644 index 0000000..a2759c5 --- /dev/null +++ b/vendor/lief/.github/workflows/windows-all.yml @@ -0,0 +1,268 @@ +name: LIEF Windows +on: + push: + branches: + - 'main' + tags-ignore: + - '**' + +env: + python-test-version: '3.13' + python-version: '3.13' + CLICOLOR_FORCE: "1" + FORCE_COLOR: "1" + GCC_COLORS: "yes" + COLORTERM: "truecolor" + TERM: "screen-256color" + CLICOLOR: "1" + +jobs: + build-sdk: + runs-on: windows-2022 + strategy: + matrix: + arch: ['x64', 'x86'] + fail-fast: false + env: + SCCACHE_CACHE_SIZE: 2G + SCCACHE_DIR: ${{ vars.SCCACHE_DIR }} + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Set up Python + uses: actions/setup-python@v6 + with: + python-version: ${{ env.python-version }} + architecture: ${{ matrix.arch }} + - run: python -m pip install setuptools + - name: Install system dependencies + run: | + choco install ninja + choco install sccache + - uses: ilammy/msvc-dev-cmd@v1 + with: + vsversion: "2022" + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Setup sccache + uses: actions/cache@v5 + continue-on-error: false + with: + path: ${{ vars.SCCACHE_DIR }} + key: ${{ runner.os }}-${{ matrix.arch }}-sccache-sdk-${{ steps.get-date.outputs.date }} + restore-keys: | + ${{ runner.os }}-${{ matrix.arch }}-sccache-sdk + - name: Start sccache server + run: sccache --start-server + - name: Build SDK + run: | + python ./scripts/windows/package_sdk.py + - name: 'Upload SDK artifact' + uses: actions/upload-artifact@v7 + with: + name: windows-${{ matrix.arch }}-sdk + path: build/*.zip + retention-days: 3 + - name: 'Upload install artifact' + uses: actions/upload-artifact@v7 + with: + name: windows-${{ matrix.arch }}-install + path: ${{ runner.temp }}/lief-install + retention-days: 1 + - name: sccache stats + run: sccache --show-stats + - name: stop sccache server + run: sccache --stop-server || true + tests: + runs-on: windows-2022 + if: "!contains(github.event.commits[0].message, '[skip-test]')" + strategy: + matrix: + arch: ['x64'] + fail-fast: false + env: + SCCACHE_CACHE_SIZE: 2G + SCCACHE_DIR: ${{ vars.SCCACHE_DIR }} + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Set up Python ${{ env.python-test-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ env.python-test-version }} + architecture: ${{ matrix.arch }} + - name: Install system dependencies + run: | + choco install ninja + choco install sccache + - uses: ilammy/msvc-dev-cmd@v1 + with: + vsversion: "2022" + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Setup sccache + uses: actions/cache@v5 + continue-on-error: false + with: + path: ${{ vars.SCCACHE_DIR }} + key: ${{ runner.os }}-${{ matrix.arch }}-sccache-test-${{ steps.get-date.outputs.date }} + restore-keys: | + ${{ runner.os }}-${{ matrix.arch }}-sccache-test + - name: Start sccache server + run: sccache --start-server + - name: Set arch specific env + if: matrix.arch == 'x64' + run: | + echo "ARCH=x64" >> $env:GITHUB_ENV + - name: Set arch specific env + if: matrix.arch == 'x86' + run: | + echo "ARCH=x86" >> $env:GITHUB_ENV + - name: Set Python config (${{ matrix.arch }}) + run: | + echo ("PYLIEF_CONF=" + $env:GITHUB_WORKSPACE + "/scripts/windows/py-" + $env:ARCH + "-test.toml") >> $env:GITHUB_ENV + - name: Set env variables + run: | + chcp 65001 #set code page to utf-8 + echo ("LIEF_SAMPLES_DIR=" + $env:RUNNER_TEMP + "/samples") >> $env:GITHUB_ENV + echo ("LIEF_BUILD_DIR=" + $env:RUNNER_TEMP + "/lief-build") >> $env:GITHUB_ENV + - name: Build Python ${{ env.python-test-version }} + shell: pwsh + run: | + python -m pip install -r tests/requirements.txt + python tests/dl_samples.py $env:LIEF_SAMPLES_DIR + python -m pip -vvv install --user api/python + Exit $LASTEXITCODE + - name: Download samples + shell: pwsh + run: | + python -m pip install -r tests/requirements.txt + python tests/dl_samples.py $env:LIEF_SAMPLES_DIR + - name: Run unittests + shell: pwsh + run: | + cd $env:GITHUB_WORKSPACE + ctest --output-on-failure --test-dir $env:LIEF_BUILD_DIR + Exit $LASTEXITCODE + - name: Run Python tests + timeout-minutes: 20 + shell: pwsh + run: | + cd $env:GITHUB_WORKSPACE + python tests/run_pytest.py + Exit $LASTEXITCODE + - name: sccache stats + run: sccache --show-stats + - name: stop sccache server + run: sccache --stop-server || true + wheels: + runs-on: windows-2022 + needs: build-sdk + strategy: + matrix: + python-version: ['3.12', '3.13', '3.14'] + arch: ['x86', 'x64'] + fail-fast: false + env: + SCCACHE_CACHE_SIZE: 2G + SCCACHE_DIR: ${{ vars.SCCACHE_DIR }} + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@v6 + with: + python-version: ${{ matrix.python-version }} + architecture: ${{ matrix.arch }} + - name: Install system dependencies + run: | + choco install ninja + choco install sccache + python -m pip install --upgrade pip + - uses: ilammy/msvc-dev-cmd@v1 + with: + vsversion: "2022" + - name: Get Date + id: get-date + run: | + echo "date=$(/bin/date -u "+%Y-%m-%d-%H;%M;%S")" >> $GITHUB_OUTPUT + shell: bash + - name: Save sccache + uses: actions/cache@v5 + continue-on-error: false + with: + path: ${{ vars.SCCACHE_DIR }} + key: ${{ runner.os }}-${{ matrix.arch }}-sccache-${{ matrix.python-version }}-${{ steps.get-date.outputs.date }} + restore-keys: | + ${{ runner.os }}-${{ matrix.arch }}-sccache-${{ matrix.python-version }} + - name: Download LIEF install dir + uses: actions/download-artifact@v8 + with: + name: windows-${{ matrix.arch }}-install + path: ~/lief-${{ matrix.arch }}-install + - name: Start sccache server + run: sccache --start-server + - name: Set arch specific env + if: matrix.arch == 'x64' + run: | + echo "ARCH=x64" >> $env:GITHUB_ENV + - name: Set arch specific env + if: matrix.arch == 'x86' + run: | + echo "ARCH=x86" >> $env:GITHUB_ENV + - name: Set Python config (${{ matrix.arch }}) + run: | + echo ("PYLIEF_CONF=" + $env:GITHUB_WORKSPACE + "/scripts/windows/py-" + $env:ARCH + ".toml") >> $env:GITHUB_ENV + - name: Set env variables + run: | + chcp 65001 #set code page to utf-8 + - name: Build Python ${{ matrix.python-version }} + shell: pwsh + run: | + python -m pip -vvv wheel --wheel-dir=dist/ ./api/python + - name: 'Upload Python artifacts [${{ matrix.python-version }}]' + uses: actions/upload-artifact@v7 + with: + name: windows-${{ matrix.arch }}-wheel-${{ matrix.python-version }} + path: dist/*.whl + retention-days: 3 + deploy: + if: ${{ always() }} + runs-on: ubuntu-latest + #needs: [build-sdk, wheels] + needs: [wheels] + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 0 + - name: Download artifacts + uses: actions/download-artifact@v8 + with: + pattern: windows-* + merge-multiple: true + path: ${{ runner.temp }}/artifacts + - name: Deploy + env: + LIEF_S3_KEY: ${{ secrets.LIEF_S3_KEY }} + LIEF_S3_SECRET: ${{ secrets.LIEF_S3_SECRET }} + shell: bash + run: | + docker run --rm \ + -v $GITHUB_WORKSPACE:/src \ + -v $RUNNER_TEMP:/runner_tmp \ + -e GITHUB_ACTIONS="true" \ + -e GITHUB_WORKSPACE=$GITHUB_WORKSPACE \ + -e GITHUB_REF=$GITHUB_REF \ + -e GITHUB_REPOSITORY=$GITHUB_REPOSITORY \ + -e LIEF_S3_KEY=$LIEF_S3_KEY \ + -e LIEF_S3_SECRET=$LIEF_S3_SECRET \ + liefproject/deploy python3 /src/.github/deploy.py --skip-sdk /runner_tmp/artifacts diff --git a/vendor/lief/.gitignore b/vendor/lief/.gitignore new file mode 100644 index 0000000..eb9ba92 --- /dev/null +++ b/vendor/lief/.gitignore @@ -0,0 +1,15 @@ +build/ +*.so +*.whl +*.dll +*.dylib +*.lib +lief.egg-info/ +dist/ +**/target/* +api/rust/cargo/target/* +api/rust/examples/target/* +tools/target/* +plugins/ghidra/bin/ +api/python/tests/lib/ +dev-scripts/ diff --git a/vendor/lief/.gitlab-ci.yml b/vendor/lief/.gitlab-ci.yml new file mode 100644 index 0000000..6b93cd1 --- /dev/null +++ b/vendor/lief/.gitlab-ci.yml @@ -0,0 +1,4 @@ +include: + - project: 'LIEF/ci' + ref: main + file: 'main.yml' diff --git a/vendor/lief/AUTHORS b/vendor/lief/AUTHORS index c5bf864..5909eb5 100644 --- a/vendor/lief/AUTHORS +++ b/vendor/lief/AUTHORS @@ -1,3 +1,3 @@ Authors: - Romain Thomas - Quarkslab + Romain Thomas diff --git a/vendor/lief/Acknowledgements b/vendor/lief/Acknowledgements index faed973..9c55299 100644 --- a/vendor/lief/Acknowledgements +++ b/vendor/lief/Acknowledgements @@ -4,13 +4,10 @@ Acknowledgements LIEF makes use of the following open source projects: - mbedTLS - https://tls.mbed.org/ - - pybind11 - https://github.com/pybind/pybind11 + - nanobind - https://github.com/wjakob/nanobind - json - https://nlohmann.github.io/json/ - - rang - https://agauniyal.github.io/rang/ - - easyloggingpp - https://github.com/muflihun/easyloggingpp - - Catch - https://github.com/philsquared/Catch - - yamlcpp - https://github.com/jbeder/yaml-cpp - - filesystem - https://github.com/wjakob/filesystem + - spdlog - https://github.com/gabime/spdlog + - Catch2 - https://github.com/catchorg/Catch2 - utf8-cpp - https://sourceforge.net/projects/utfcpp/ - llvm - http://llvm.org/ - For the formats enums and structures - virtualbox - https://www.virtualbox.org/ - For the PE 'LoadConfiguration' structures diff --git a/vendor/lief/CHANGELOG b/vendor/lief/CHANGELOG index 3598f2b..21202a7 100644 --- a/vendor/lief/CHANGELOG +++ b/vendor/lief/CHANGELOG @@ -1,5 +1,4 @@ Changelog ========= -see doc/sphinx/changelog.rst - +see doc/sphinx/changelog.md diff --git a/vendor/lief/CMakeLists.txt b/vendor/lief/CMakeLists.txt index 551e8f7..9598f3c 100644 --- a/vendor/lief/CMakeLists.txt +++ b/vendor/lief/CMakeLists.txt @@ -1,47 +1,45 @@ -cmake_minimum_required(VERSION 3.5) - -# Avoid warning about DOWNLOAD_EXTRACT_TIMESTAMP in CMake 3.24: -if (CMAKE_VERSION VERSION_GREATER_EQUAL "3.24.0") - cmake_policy(SET CMP0135 NEW) -endif() +cmake_minimum_required(VERSION 3.24) +project(LIEF LANGUAGES C CXX) set_property(GLOBAL PROPERTY USE_FOLDERS ON) # Modules list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake/") -set(IS_WIN_CROSS_COMPILE 0) -if(CMAKE_SYSTEM_NAME STREQUAL "Windows" AND CMAKE_CROSSCOMPILING) - set(IS_WIN_CROSS_COMPILE 1) -endif() - - -if(WIN32 OR ${IS_WIN_CROSS_COMPILE}) - include(ChooseMSVCCRT) -endif() include(CheckCXXCompilerFlag) include(CheckCCompilerFlag) -include(ExternalProject) include(CMakePackageConfigHelpers) -if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/.git" - AND IS_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/.git") - find_package(Git REQUIRED) - - # Information from git - # ==================== +find_package(Git) +if (DEFINED ENV{LIEF_VERSION_ENV}) + string(REGEX MATCHALL "([0-9]+)" VERSION_STRING "$ENV{LIEF_VERSION_ENV}") + if (NOT VERSION_STRING) + message(FATAL_ERROR "Invalid version") + endif() + list(GET VERSION_STRING 0 LIEF_VERSION_MAJOR) + list(GET VERSION_STRING 1 LIEF_VERSION_MINOR) + list(GET VERSION_STRING 2 LIEF_VERSION_PATCH) +elseif(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/.git" + AND IS_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/.git" AND Git_FOUND) include(LIEFGit) else() - set(LIEF_VERSION_MAJOR "0") - set(LIEF_VERSION_MINOR "13") - set(LIEF_VERSION_PATCH "0") + set(LIEF_VERSION_MAJOR 2) + set(LIEF_VERSION_MINOR 0) + set(LIEF_VERSION_PATCH 0) +endif() + +if (DEFINED ENV{LIEF_COMMIT}) + set(LIEF_COMMIT_HASH "$ENV{LIEF_COMMIT}") +endif() + +if (DEFINED ENV{LIEF_BRANCH}) + set(LIEF_GIT_BRANCH "$ENV{LIEF_BRANCH}") endif() # LIEF Project # ============ -project( - LIEF - VERSION ${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}) +project(LIEF VERSION + ${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}) message(STATUS "${PROJECT_NAME} ${PROJECT_VERSION}") # LIEF options @@ -57,8 +55,8 @@ message(STATUS "Caching: ${LIEF_USE_CCACHE}") if(LIEF_USE_CCACHE) find_program(CCACHE_FOUND ccache) if(CCACHE_FOUND) - set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ccache) - set_property(GLOBAL PROPERTY RULE_LAUNCH_LINK ccache) + set(CMAKE_C_COMPILER_LAUNCHER ${CCACHE_FOUND}) + set(CMAKE_CXX_COMPILER_LAUNCHER ${CCACHE_FOUND}) message(STATUS "Found ccache: ${CCACHE_FOUND}") else() find_program(SCCACHE_FOUND sccache) @@ -86,7 +84,12 @@ if(CMAKE_SYSTEM_NAME STREQUAL "iOS") set(CMAKE_XCODE_ATTRIBUTE_CODE_SIGN_IDENTITY "") endif() +set(LIEF_EXTRA_FLAGS) + +message(STATUS "LIEF_EXTRA_FLAGS: ${LIEF_EXTRA_FLAGS}") message(STATUS "CMAKE_CXX_FLAGS_RELEASE: ${CMAKE_CXX_FLAGS_RELEASE}") +message(STATUS "CMAKE_CXX_FLAGS_RELWITHDEBINFO: ${CMAKE_CXX_FLAGS_RELWITHDEBINFO}") +message(STATUS "CMAKE_CXX_FLAGS_DEBUG: ${CMAKE_CXX_FLAGS_DEBUG}") message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}") message(STATUS "CMAKE_CXX_LINK_EXECUTABLE: ${CMAKE_CXX_LINK_EXECUTABLE}") message(STATUS "CMAKE_CXX_LINK_FLAGS: ${CMAKE_CXX_LINK_FLAGS}") @@ -99,133 +102,77 @@ message(STATUS "CMAKE_LINK_LIBRARY_FILE_FLAG: ${CMAKE_LINK_LIBRARY_FILE_FLA message(STATUS "CMAKE_LINK_INTERFACE_LIBRARIES: ${CMAKE_LINK_INTERFACE_LIBRARIES}") message(STATUS "CMAKE_CXX_IMPLICIT_LINK_LIBRARIES: ${CMAKE_CXX_IMPLICIT_LINK_LIBRARIES}") message(STATUS "CMAKE_SYSTEM_PROCESSOR: ${CMAKE_SYSTEM_PROCESSOR}") +message(STATUS "CMAKE_MSVC_RUNTIME_LIBRARY: ${CMAKE_MSVC_RUNTIME_LIBRARY}") + +include(GNUInstallDirs) # LIEF Source definition # ====================== +add_library(LIB_LIEF src/Object.cpp) +add_subdirectory(src) -set(LIEF_PRIVATE_INCLUDE_DIR) -set(LIEF_PUBLIC_INCLUDE_DIR) - -set(LIEF_PUBLIC_INCLUDE_FILES) -set(LIEF_PRIVATE_INCLUDE_FILES) - -set(LIBLIEF_SOURCE_FILES - "${CMAKE_CURRENT_SOURCE_DIR}/src/errors.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/hash_stream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/logging.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/exception.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/iostream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/utils.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/internal_utils.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/Object.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/Object.tcc" - "${CMAKE_CURRENT_SOURCE_DIR}/src/Visitor.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/BinaryStream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/VectorStream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/FileStream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/MemoryStream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/SpanStream.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/BinaryStream/Convert.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/visitors/hash.cpp") - -# Grouping basic headers together -# =============================== -set(LIEF_INC_FILES - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/errors.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/span.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/ELF.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/Abstract.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/exception.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/iostream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/iterators.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/LIEF.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/logging.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/MachO.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/PE.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/types.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/utils.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/visibility.h" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/Object.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/Visitor.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/visitor_macros.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/BinaryStream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/VectorStream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/FileStream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/MemoryStream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/SpanStream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/BinaryStream/Convert.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/internal_utils.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/hash_stream.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/src/frozen.hpp" -) - -set(LIEF_VISITOR_INCLUDE_FILES - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/hash.hpp") - -set(LIEF_INCLUDE_FILES ${LIEF_INC_FILES} ${LIEF_VISITOR_INCLUDE_FILES}) - -set(LIEF_JSON_SRC "${CMAKE_CURRENT_SOURCE_DIR}/src/visitors/json.cpp") -set(LIEF_JSON_HDR "${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/json.hpp") - -list(APPEND LIEF_INC_FILES "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/json.hpp") -list(APPEND LIBLIEF_SOURCE_FILES "${CMAKE_CURRENT_SOURCE_DIR}/src/json_api.cpp") - -if(LIEF_ENABLE_JSON) - list(APPEND LIBLIEF_SOURCE_FILES "${LIEF_JSON_SRC}") - list(APPEND LIEF_INC_FILES "${LIEF_JSON_HDR}") +if (LIEF_EXTRA_FLAGS) + target_compile_options(LIB_LIEF PRIVATE ${LIEF_EXTRA_FLAGS}) endif() -source_group("Header Files" FILES ${LIEF_INC_FILES}) -source_group("Source Files" FILES ${LIBLIEF_SOURCE_FILES}) - -source_group("Header Files\\visitors" FILES ${LIEF_VISITOR_INCLUDE_FILES}) +if(LIEF_PRECOMPILED) + find_package(lief-extended QUIET) + if (NOT lief-extended_FOUND) + find_package(LIEF REQUIRED) + endif() +else() + add_library(LIEF::LIEF ALIAS LIB_LIEF) +endif() -add_library(LIB_LIEF ${LIBLIEF_SOURCE_FILES} ${LIEF_INCLUDE_FILES}) -add_library(LIEF::LIEF ALIAS LIB_LIEF) if(NOT LIEF_OPT_MBEDTLS_EXTERNAL) - set_source_files_properties(${mbedtls_src_crypto} PROPERTIES GENERATED TRUE) - set_source_files_properties(${mbedtls_src_x509} PROPERTIES GENERATED TRUE) - set_source_files_properties(${mbedtls_src_tls} PROPERTIES GENERATED TRUE) - target_sources(LIB_LIEF PRIVATE - "${mbedtls_src_crypto}" - "${mbedtls_src_x509}" - "${mbedtls_src_tls}") - - source_group("mbedtls\\crypto" FILES ${mbedtls_src_crypto}) - source_group("mbedtls\\x509" FILES ${mbedtls_src_x509}) - source_group("mbedtls\\tls" FILES ${mbedtls_src_tls}) - - target_include_directories( - LIB_LIEF SYSTEM PRIVATE - "${MBEDTLS_INCLUDE_DIRS}" - "${MBEDTLS_SOURCE_DIR}/library" + target_sources(LIB_LIEF PRIVATE ${mbedtls_src_files}) + + target_include_directories(LIB_LIEF SYSTEM PRIVATE + ${MBEDTLS_INCLUDE_DIRS} + "${MBEDTLS_SOURCE_DIR}/library" ) + if (LIEF_PYTHON_FREE_THREADED) + target_compile_definitions(LIB_LIEF PRIVATE + # these must be set at LIB_LIEF compile time to be forwarded to MbedTLS + -DMBEDTLS_THREADING_C + -DMBEDTLS_THREADING_ALT + ) + endif() - add_dependencies(LIB_LIEF lief_mbed_tls) + target_compile_definitions(LIB_LIEF PRIVATE + -DTF_PSA_CRYPTO_USER_CONFIG_FILE="${CMAKE_CURRENT_SOURCE_DIR}/config/mbedtls/psa_config.h" + ) else() - find_package(MbedTLS REQUIRED) + find_package(MbedTLS 4.0.0 EXACT REQUIRED) target_link_libraries(LIB_LIEF PRIVATE - MbedTLS::mbedcrypto - MbedTLS::mbedx509) + MbedTLS::tfpsacrypto MbedTLS::mbedx509) + if (LIEF_PYTHON_FREE_THREADED) + message(WARNING "Python free-threading requires the external MbedTLS to have \ + been built with threading support. LIEF cannot enforce this.") + endif() endif() -if(WINDOWS AND BUILD_SHARED_LIBS) - target_link_libraries(LIB_LIEF ws2_32) -endif() +target_compile_definitions(LIB_LIEF PRIVATE + -DMBEDTLS_CONFIG_FILE="${CMAKE_CURRENT_SOURCE_DIR}/config/mbedtls/config.h" + -DMBEDTLS_X509_USE_C + -DMBEDTLS_PK_PARSE_C +) -if(MSVC OR ${IS_WIN_CROSS_COMPILE}) - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} /bigobj") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} /bigobj") +if (WIN32) + target_link_libraries(LIB_LIEF PRIVATE bcrypt) endif() -if(CMAKE_BUILD_TYPE MATCHES Debug AND WINDOWS) - add_definitions(-D_ITERATOR_DEBUG_LEVEL=0 -D_SECURE_SCL=0 - -D_HAS_ITERATOR_DEBUGGING=0) +if(WIN32 AND BUILD_SHARED_LIBS) + target_link_libraries(LIB_LIEF PRIVATE ws2_32) + if (LIEF_IMPORT_SUFFIX) + set_target_properties(LIB_LIEF PROPERTIES IMPORT_SUFFIX "${LIEF_IMPORT_SUFFIX}") + endif() endif() -if(CMAKE_BUILD_TYPE MATCHES Debug AND UNIX) - target_compile_options(LIB_LIEF PRIVATE -g -O0) +if(MSVC) + target_compile_options(LIB_LIEF PRIVATE /bigobj) + target_compile_options(LIB_LIEF PUBLIC /Zc:__cplusplus) endif() if(BUILD_SHARED_LIBS OR LIEF_FORCE_API_EXPORTS) @@ -233,95 +180,31 @@ if(BUILD_SHARED_LIBS OR LIEF_FORCE_API_EXPORTS) else() target_compile_definitions(LIB_LIEF PRIVATE -DLIEF_STATIC) endif() -if(LIEF_SUPPORT_CXX14) - target_compile_features(LIB_LIEF PRIVATE cxx_std_14) -endif() -# Abstract part -include("${CMAKE_CURRENT_SOURCE_DIR}/src/Abstract/CMakeLists.txt") -# ELF Part -# ======== -include("${CMAKE_CURRENT_SOURCE_DIR}/src/ELF/CMakeLists.txt") -if(LIEF_ELF) - set(ENABLE_ELF_SUPPORT 1) -else() - set(ENABLE_ELF_SUPPORT 0) -endif() - -# PE Part -# ======= -include("${CMAKE_CURRENT_SOURCE_DIR}/src/PE/CMakeLists.txt") -if(LIEF_PE) - set(ENABLE_PE_SUPPORT 1) -else() - set(ENABLE_PE_SUPPORT 0) -endif() - -# MachO part -# ========== -include("${CMAKE_CURRENT_SOURCE_DIR}/src/MachO/CMakeLists.txt") -if(LIEF_MACHO) - set(ENABLE_MACHO_SUPPORT 1) -else() - set(ENABLE_MACHO_SUPPORT 0) +if(LIEF_ENABLE_JSON) + # Make nlohmann/json is only using C++11 API. + # Especially, MSVC[14.37.32822] is buggy with (no)rtti & std::any + # Ref: + # - https://github.com/nlohmann/json/issues/3900 + # - https://github.com/microsoft/STL/issues/4349#issuecomment-1920093172 + target_compile_definitions(LIB_LIEF PRIVATE JSON_HAS_CPP_11) endif() # Logging Configuration # ===================== - target_compile_definitions(LIB_LIEF PRIVATE SPDLOG_DISABLE_DEFAULT_LOGGER + SPDLOG_NO_EXCEPTIONS SPDLOG_FUNCTION=) -if(CMAKE_SYSTEM_NAME STREQUAL "iOS") - target_compile_definitions(LIB_LIEF PRIVATE SPDLOG_NO_EXCEPTIONS SPDLOG_NO_THREAD_ID) -endif() - -# Frozen Configuration -# ==================== -if(LIEF_FROZEN_ENABLED) -endif() - -# OAT part -# ======== -if(LIEF_OAT) - include(${CMAKE_CURRENT_SOURCE_DIR}/src/OAT/CMakeLists.txt) - set(ENABLE_OAT_SUPPORT 1) -else() - set(ENABLE_OAT_SUPPORT 0) -endif() - -# DEX part -# ======== -if(LIEF_DEX) - include(${CMAKE_CURRENT_SOURCE_DIR}/src/DEX/CMakeLists.txt) - set(ENABLE_DEX_SUPPORT 1) -else() - set(ENABLE_DEX_SUPPORT 0) +if (MSVC AND NOT CLANG_CL AND NOT LIEF_EXTERNAL_SPDLOG) + target_compile_definitions(LIB_LIEF PRIVATE FMT_UNICODE=0) endif() -# VDEX part -# ========= -if(LIEF_VDEX) - include(${CMAKE_CURRENT_SOURCE_DIR}/src/VDEX/CMakeLists.txt) - set(ENABLE_VDEX_SUPPORT 1) -else() - set(ENABLE_VDEX_SUPPORT 0) -endif() - -# ART part -# ======== -if(LIEF_ART) - include(${CMAKE_CURRENT_SOURCE_DIR}/src/ART/CMakeLists.txt) - set(ENABLE_ART_SUPPORT 1) -else() - set(ENABLE_ART_SUPPORT 0) +if(CMAKE_SYSTEM_NAME STREQUAL "iOS") + target_compile_definitions(LIB_LIEF PRIVATE SPDLOG_NO_THREAD_ID) endif() -# Platforms -# ========= -include(${CMAKE_CURRENT_SOURCE_DIR}/src/platforms/CMakeLists.txt) - # LIEF includes # ============= configure_file("${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/version.h.in" @@ -330,40 +213,39 @@ configure_file("${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/version.h.in" configure_file("${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/config.h.in" "${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/config.h" @ONLY) -list(APPEND LIEF_PUBLIC_INCLUDE_DIR - "${CMAKE_CURRENT_SOURCE_DIR}/include/" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/" - "${CMAKE_CURRENT_BINARY_DIR}/include/") +set(LIEF_PUBLIC_INCLUDE_DIR + ${CMAKE_CURRENT_SOURCE_DIR}/include/ + ${CMAKE_CURRENT_BINARY_DIR}/include/) -list(APPEND LIEF_PRIVATE_INCLUDE_DIR "${LIEF_PUBLIC_INCLUDE_DIR}" - "${CMAKE_CURRENT_SOURCE_DIR}/src" "${CMAKE_CURRENT_BINARY_DIR}") +set(LIEF_PRIVATE_INCLUDE_DIR + ${LIEF_PUBLIC_INCLUDE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/src + ${CMAKE_CURRENT_BINARY_DIR}) -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/LIEF.pc.in ${CMAKE_CURRENT_BINARY_DIR}/LIEF.pc - @ONLY) +configure_file(${CMAKE_CURRENT_SOURCE_DIR}/cmake/LIEF.pc.in + ${CMAKE_CURRENT_BINARY_DIR}/LIEF.pc @ONLY) target_include_directories(LIB_LIEF PUBLIC "$" PRIVATE "${LIEF_PRIVATE_INCLUDE_DIR}") +target_precompile_headers(LIB_LIEF PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/src/lief-pch.hpp +) + if(LIEF_ENABLE_JSON) if(LIEF_OPT_NLOHMANN_JSON_EXTERNAL) find_package(nlohmann_json REQUIRED) target_link_libraries(LIB_LIEF PRIVATE nlohmann_json::nlohmann_json) else() - add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann/json.hpp - COMMAND - ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann - COMMAND - ${CMAKE_COMMAND} -E copy_directory ${LIBJSON_SOURCE_DIR}/ - ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann/ - DEPENDS lief_libjson) - - target_sources(LIB_LIEF PRIVATE - ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann/json.hpp) + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann) + file(COPY ${LIBJSON_SOURCE_DIR}/ + DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/internal/nlohmann/) target_include_directories(LIB_LIEF PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/) endif() + target_compile_definitions(LIB_LIEF PRIVATE JSON_NOEXCEPTION) endif() if(LIEF_FROZEN_ENABLED) @@ -371,53 +253,36 @@ if(LIEF_FROZEN_ENABLED) find_package(frozen REQUIRED) target_link_libraries(LIB_LIEF PRIVATE frozen::frozen) else() - add_dependencies(LIB_LIEF lief_frozen) target_include_directories(LIB_LIEF PRIVATE "${FROZEN_INCLUDE_DIR}") endif() endif() + # ======================================= -# Leaf +# Expected # ======================================= -if(LIEF_EXTERNAL_LEAF) - message(STATUS "Using external LEAF version") - if(LIEF_EXTERNAL_LEAF_DIR) - message(STATUS "External LEAF include dir: ${LIEF_EXTERNAL_LEAF_DIR}") - target_include_directories(LIB_LIEF SYSTEM PUBLIC - "$") - endif() +if(LIEF_EXTERNAL_EXPECTED) + message(STATUS "Using external Expected version") + find_package(tl-expected REQUIRED) + target_link_libraries(LIB_LIEF PUBLIC tl::expected) else() - add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/leaf.hpp - COMMAND - ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/ - COMMAND - ${CMAKE_COMMAND} -E copy_directory ${LEAF_SRC_DIR}/ - ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/ - DEPENDS lief_leaf) - - target_sources(LIB_LIEF PRIVATE - ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/leaf.hpp) + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/) + file(COPY ${EXPECTED_SRC_DIR}/include/tl/ + DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/) endif() + # ======================================= # utfcpp # ======================================= - if(LIEF_OPT_UTFCPP_EXTERNAL) find_package(utf8cpp REQUIRED) - target_link_libraries(LIB_LIEF PRIVATE utf8cpp) + target_link_libraries(LIB_LIEF PRIVATE utf8cpp::utf8cpp) else() - add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/internal/utfcpp/utf8.h - COMMAND - ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/internal/ - COMMAND - ${CMAKE_COMMAND} -E copy_directory ${UTFCPP_INCLUDE_DIR}/ - ${CMAKE_CURRENT_BINARY_DIR}/internal/utfcpp - DEPENDS lief_utfcpp) - - target_sources(LIB_LIEF PRIVATE - ${CMAKE_CURRENT_BINARY_DIR}/internal/utfcpp/utf8.h) + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/internal/) + file(COPY ${UTFCPP_INCLUDE_DIR}/ + DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/internal/utfcpp) endif() # ======================================= @@ -431,40 +296,52 @@ if(LIEF_EXTERNAL_SPAN) "$") endif() else() - add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/span.hpp - COMMAND - ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/ - COMMAND - ${CMAKE_COMMAND} -E copy_directory ${TCB_SPAN_SRC_DIR}/ - ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/ - DEPENDS lief_span) - - target_sources(LIB_LIEF PRIVATE - ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/span.hpp) + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/) + file(COPY ${TCB_SPAN_SRC_DIR}/ + DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/third-party/internal/) endif() - - target_link_libraries(LIB_LIEF PRIVATE lief_spdlog) +if(ANDROID AND LIEF_LOGGING) + target_link_libraries(LIB_LIEF PUBLIC log) +endif() + # Flags definition # ---------------- - -# cmake-format: off -set_target_properties( - LIB_LIEF +set_target_properties(LIB_LIEF PROPERTIES POSITION_INDEPENDENT_CODE ON - CXX_STANDARD 11 + CXX_STANDARD 17 CXX_STANDARD_REQUIRED ON + VISIBILITY_INLINES_HIDDEN ON CXX_VISIBILITY_PRESET hidden C_VISIBILITY_PRESET hidden) -# cmake-format: on + +if (LIEF_CLANG_TIDY) + find_program(CLANG_TIDY_EXE NAMES "clang-tidy" REQUIRED) + cmake_path(GET CLANG_TIDY_EXE PARENT_PATH CLANG_TIDY_DIR) + + set(CLANG_TIDY_COMMAND + "${CLANG_TIDY_EXE}" + "--use-color" + "--load=${CLANG_TIDY_DIR}/clang-taidy.so" + "--config-file=${CMAKE_CURRENT_SOURCE_DIR}/.clang-tidy-core.yaml" + ) + if (LIEF_CLANG_TIDY_WARN_ERR) + list(APPEND CLANG_TIDY_COMMAND "--warnings-as-errors=*") + endif() + + set_target_properties(LIB_LIEF PROPERTIES CXX_CLANG_TIDY "${CLANG_TIDY_COMMAND}") + + if (TARGET LIB_LIEF_RUNTIME) + set_target_properties(LIB_LIEF_RUNTIME + PROPERTIES CXX_CLANG_TIDY "${CLANG_TIDY_COMMAND}") + endif() +endif() + if(UNIX AND NOT APPLE) - set_property( - TARGET LIB_LIEF - APPEND - PROPERTY LINK_FLAGS "-Wl,--gc-sections -Wl,--exclude-libs,ALL") + target_link_options(LIB_LIEF PRIVATE -Wl,--gc-sections -Wl,--exclude-libs,ALL) endif() target_compile_definitions(LIB_LIEF PUBLIC -D_GLIBCXX_USE_CXX11_ABI=1) @@ -474,19 +351,20 @@ target_compile_definitions(LIB_LIEF PUBLIC -D_GLIBCXX_USE_CXX11_ABI=1) set(SANITIZER_FLAGS -fno-omit-frame-pointer -g -O1) if(LIEF_ASAN) message(STATUS "Address sanitizer enabled") - list(APPEND SANITIZER_FLAGS -fsanitize=address) + list(APPEND SANITIZER_FLAGS + -fsanitize=address + -fsanitize-address-use-after-scope + -fsanitize-address-use-after-return=runtime + ) - set_property(TARGET LIB_LIEF - APPEND PROPERTY LINK_FLAGS -fsanitize=address) - target_link_libraries(LIB_LIEF INTERFACE asan) + target_link_options(LIB_LIEF PUBLIC -fsanitize=address) endif() if(LIEF_LSAN) message(STATUS "Leak sanitizer enabled") list(APPEND SANITIZER_FLAGS -fsanitize=leak) - set_property(TARGET LIB_LIEF - APPEND PROPERTY LINK_FLAGS -fsanitize=leak) + target_link_options(LIB_LIEF PUBLIC -fsanitize=leak) target_link_libraries(LIB_LIEF INTERFACE lsan) endif() @@ -495,21 +373,16 @@ if(LIEF_TSAN) message(STATUS "Thread sanitizer enabled") list(APPEND SANITIZER_FLAGS -fsanitize=thread) - set_property(TARGET LIB_LIEF - APPEND PROPERTY LINK_FLAGS -fsanitize=thread) - - target_link_libraries(LIB_LIEF INTERFACE tsan) + target_link_options(LIB_LIEF PUBLIC -fsanitize=thread) endif() if(LIEF_USAN) message(STATUS "Undefined sanitizer enabled") list(APPEND SANITIZER_FLAGS -fsanitize=undefined,null,alignment) - set_property(TARGET LIB_LIEF - APPEND PROPERTY LINK_FLAGS -fsanitize=undefined,null,alignment) target_link_options(LIB_LIEF PUBLIC -fsanitize=undefined,null,alignment) - target_link_libraries(LIB_LIEF PUBLIC ubsan -fsanitize=undefined,null,alignment) + target_link_libraries(LIB_LIEF PUBLIC ubsan) endif() set(LIEF_SANITIZER OFF) @@ -520,54 +393,37 @@ endif() if(LIEF_SANITIZER) message("LIEF Sanitizer enabled: ${SANITIZER_FLAGS}") target_compile_options(LIB_LIEF PUBLIC ${SANITIZER_FLAGS}) - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/tests/sanitizer") + add_subdirectory(tests/sanitizer) endif() -# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # Fuzzing options # ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ if(LIEF_FUZZING) - set(FUZZING_FLAGS -fno-omit-frame-pointer -g -O2 -fsanitize=address,fuzzer-no-link) - set(FUZZING_LINKER_FLAGS -fsanitize=address,fuzzer-no-link) - set_property(TARGET LIB_LIEF - APPEND PROPERTY LINK_FLAGS ${FUZZING_LINKER_FLAGS}) + set(FUZZING_FLAGS -fno-omit-frame-pointer -g -O2 -fsanitize=fuzzer-no-link) + target_link_options(LIB_LIEF PUBLIC -fsanitize=fuzzer-no-link) target_compile_options(LIB_LIEF PRIVATE ${FUZZING_FLAGS}) - target_link_libraries(LIB_LIEF PUBLIC asan pthread) - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/fuzzing") + target_link_libraries(LIB_LIEF PUBLIC pthread) + add_subdirectory(fuzzing) endif() -# Compile Flags -# ============= include(LIEFCompilerFlags) -# Profiling flags -# --------------- if(LIEF_PROFILING) - set(PROFILING_FLAGS - -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc - -fno-builtin-free -fno-omit-frame-pointer -g) - target_compile_options(LIB_LIEF PUBLIC ${PROFILING_FLAGS}) - - add_executable(elf_profiler profiling/elf_profiler.cpp) - target_compile_options(elf_profiler PUBLIC ${PROFILING_FLAGS}) - target_link_libraries(elf_profiler PRIVATE LIB_LIEF) - - add_executable(macho_profiler profiling/macho_profiler.cpp) - target_compile_options(macho_profiler PUBLIC ${PROFILING_FLAGS}) - target_link_libraries(macho_profiler PRIVATE LIB_LIEF) + add_subdirectory(profiling) endif() -# Coverage flags -# -------------- -if(LIEF_COVERAGE) - target_compile_options(LIB_LIEF PRIVATE -g -O0 --coverage -fprofile-arcs - -ftest-coverage) - target_link_libraries(LIB_LIEF gcov) -endif() - -set_target_properties(LIB_LIEF PROPERTIES OUTPUT_NAME LIEF EXPORT_NAME LIEF CLEAN_DIRECT_OUTPUT 1) +set_target_properties(LIB_LIEF PROPERTIES + OUTPUT_NAME LIEF + EXPORT_NAME LIEF + CLEAN_DIRECT_OUTPUT 1) +if (LIEF_SO_VERSION) + set_target_properties(LIB_LIEF PROPERTIES + VERSION "${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}" + SOVERSION "${LIEF_VERSION_MAJOR}" + ) +endif() # Set a default build type if none was specified if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) @@ -587,42 +443,21 @@ if(APPLE) set_target_properties(LIB_LIEF PROPERTIES MACOSX_RPATH ON) endif() -# API -# ====================== -include(LIEFApi) +add_subdirectory(api) -# Examples -# ====================== if(LIEF_EXAMPLES) - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/examples") + add_subdirectory(examples) endif() -# Tests -# ====================== - if(LIEF_TESTS) enable_testing() - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/tests") + add_subdirectory(tests) endif() -# Documentation -# ====================== -if(LIEF_DOC) - add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/doc) +if(LIEF_COMPILE_DOC_EXAMPLES) + add_subdirectory(doc/code/cpp) endif() -# Find Package Config -# ====================== -configure_file( - LIEFConfig.cmake.in - ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfig.cmake - @ONLY) - -write_basic_package_version_file( - ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfigVersion.cmake - VERSION ${PROJECT_VERSION} - COMPATIBILITY AnyNewerVersion) - # Post-build operations # ====================== if(BUILD_SHARED_LIBS AND CMAKE_BUILD_TYPE MATCHES "Release") @@ -645,84 +480,78 @@ if(BUILD_SHARED_LIBS AND CMAKE_BUILD_TYPE MATCHES "Release") endif() endif() -# Install Prefix -# ====================== -if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT AND UNIX) - if(UNIX AND NOT APPLE) - set(CMAKE_INSTALL_PREFIX - "/usr" - CACHE PATH "Install path prefix prepended on to install directories." - FORCE) - elseif(APPLE) - set(CMAKE_INSTALL_PREFIX - "/usr/local" - CACHE PATH "" FORCE) - endif() -endif() - -# Installation -# ====================== - -if(UNIX) - include(GNUInstallDirs) - set(CMAKE_INSTALL_LIBDIR "lib") -else() - if(WIN32) - set(CMAKE_INSTALL_LIBDIR "lib") - set(CMAKE_INSTALL_DATADIR "share") - set(CMAKE_INSTALL_INCLUDEDIR "include") - set(CMAKE_INSTALL_BINDIR "bin") - set(CMAKE_INSTALL_DATAROOTDIR "share") - message(STATUS "Setting installation destination on Windows to: ${CMAKE_INSTALL_PREFIX}") - else() - message(FATAL_ERROR "System not UNIX nor WIN32 - not implemented yet") +# Generate install target and package +# ======================================= +if(LIEF_INSTALL) + + # Find Package Config + # ====================== + configure_file(${CMAKE_CURRENT_SOURCE_DIR}/cmake/LIEFConfig.cmake.in + ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfig.cmake @ONLY) + + write_basic_package_version_file( + ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfigVersion.cmake + VERSION ${PROJECT_VERSION} + COMPATIBILITY AnyNewerVersion) + + # Install Prefix + # ====================== + if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT AND UNIX) + if(UNIX AND NOT APPLE) + set(CMAKE_INSTALL_PREFIX + "/usr" + CACHE PATH "Install path prefix prepended on to install directories." + FORCE) + elseif(APPLE) + set(CMAKE_INSTALL_PREFIX + "/usr/local" + CACHE PATH "" FORCE) endif() -endif() + endif() -install( - TARGETS LIB_LIEF lief_spdlog - EXPORT LIEFExport - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} - LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} - RUNTIME DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libraries - INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) - -install( - DIRECTORY ${LIEF_PUBLIC_INCLUDE_DIR} - DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} - COMPONENT headers - FILES_MATCHING - REGEX "(.*).(hpp|h|def|inc)$") - -install( - FILES ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfig.cmake - ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfigVersion.cmake - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/LIEF/cmake - COMPONENT config) - -install( - FILES ${CMAKE_CURRENT_BINARY_DIR}/LIEF.pc - DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig - COMPONENT libraries) - -if(BUILD_SHARED_LIBS) - set(lib_type shared) -else() - set(lib_type static) -endif() + install( + TARGETS LIB_LIEF lief_spdlog + EXPORT LIEFExport + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} + RUNTIME DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libraries + INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) + + install( + DIRECTORY ${LIEF_PUBLIC_INCLUDE_DIR} + DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} + COMPONENT headers + FILES_MATCHING + REGEX "(.*).(hpp|h|def|inc)$") + + install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfig.cmake + ${CMAKE_CURRENT_BINARY_DIR}/LIEFConfigVersion.cmake + DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/LIEF + COMPONENT config) + + install( + FILES ${CMAKE_CURRENT_BINARY_DIR}/LIEF.pc + DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig + COMPONENT libraries) + + if(BUILD_SHARED_LIBS) + set(lib_type shared) + else() + set(lib_type static) + endif() -install( - EXPORT LIEFExport - NAMESPACE LIEF:: - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/LIEF/cmake - FILE LIEFExport-${lib_type}.cmake - COMPONENT config) + install( + EXPORT LIEFExport + NAMESPACE LIEF:: + DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/LIEF + FILE LIEFExport-${lib_type}.cmake + COMPONENT config) -export( - EXPORT LIEFExport - NAMESPACE LIEF:: - FILE LIEFExport-${lib_type}.cmake) + export( + EXPORT LIEFExport + NAMESPACE LIEF:: + FILE LIEFExport-${lib_type}.cmake) -# Package -# ====================== -add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/package") + add_subdirectory(package) +endif() diff --git a/vendor/lief/Dockerfile b/vendor/lief/Dockerfile deleted file mode 100644 index aa72698..0000000 --- a/vendor/lief/Dockerfile +++ /dev/null @@ -1,21 +0,0 @@ -# Docker file used to compile LIEF on Linux x86-64 compliant with Python tag: manylinux1 -# docker build -t liefproject/manylinux1_x86_64:latest -f ./Dockerfile . -FROM quay.io/pypa/manylinux1_x86_64:2020-12-30-e2b3664 - -RUN yum update -y \ - && yum install -y ccache \ - && yum clean all - -RUN /opt/python/cp37-cp37m/bin/pip install cmake==3.13.3 ninja==1.10.0.post2 -ENV PATH=$PATH:/opt/python/cp37-cp37m/bin/ - -RUN curl --output /tmp/gcc-6.3.0-binutils-2.27-x86_64.tar.bz2 -L https://github.com/squeaky-pl/centos-devtools/releases/download/6.3/gcc-6.3.0-binutils-2.27-x86_64.tar.bz2 && \ - echo "ca3e9f92411507018c839c8cc2b496f14956a49fcf6df0cdcb356de7161bcbc5 /tmp/gcc-6.3.0-binutils-2.27-x86_64.tar.bz2" | sha256sum --check --status && \ - tar -C / -xj -f /tmp/gcc-6.3.0-binutils-2.27-x86_64.tar.bz2 && \ - rm -rf /tmp/gcc-6.3.0-binutils-2.27-x86_64.tar.bz2 - -ENV CC=/opt/devtools-6.3/bin/gcc -ENV CXX=/opt/devtools-6.3/bin/g++ -ENV CXXFLAGS="-static-libstdc++ -static-libgcc" - -WORKDIR /src diff --git a/vendor/lief/LICENSE b/vendor/lief/LICENSE index 0ee7c92..f0c1a1a 100644 --- a/vendor/lief/LICENSE +++ b/vendor/lief/LICENSE @@ -186,8 +186,8 @@ same "printed page" as the copyright notice for easier identification within third-party archives. - Copyright 2017 - 2022 R. Thomas - Copyright 2017 - 2022 Quarkslab + Copyright 2017 - 2026 R. Thomas + Copyright 2017 - 2026 Quarkslab Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/vendor/lief/LIEFConfig.cmake.in b/vendor/lief/LIEFConfig.cmake.in deleted file mode 100644 index 8c35eea..0000000 --- a/vendor/lief/LIEFConfig.cmake.in +++ /dev/null @@ -1,179 +0,0 @@ -#.rst: -# LIEFConfig -# -------- -# -# Populate the native LIEF targets. -# -# IMPORTED Targets -# ^^^^^^^^^^^^^^^^ -# -# This module defines :prop_tgt:`IMPORTED` target ``LIEF::LIEF`` -# -# Hints -# ^^^^^ -# -# A user may set ``LIEF_DIR`` to the directory where ``LIEFConfig.cmake`` file -# resides to tell CMake where to find this file. -# -# To choose between STATIC and SHARED version of LIEF library, one can use -# ``COMPONENTS STATIC`` of ``COMPONENTS SHARED``. If no components are -# specified, then a user may set ``LIEF_SHARED_LIBS`` to a true value to -# request shared libraries. By default, if no variables or components are set, -# the static library is preferred if present, else shared library will be used. -# -# .. code-block:: cmake -# -# find_package(LIEF 0.11.0 REQUIRED COMPONENTS STATIC) - - -# CMake component support for static and shared libraries based on -# https://alexreinking.com/blog/building-a-dual-shared-and-static-library-with-cmake.html - -# Process known components -set(LIEF_known_comps STATIC SHARED) -set(LIEF_comp_STATIC NO) -set(LIEF_comp_SHARED NO) -foreach(_comp ${LIEF_FIND_COMPONENTS}) - if(";${LIEF_known_comps};" MATCHES ";${_comp};") - set(LIEF_comp_${_comp} YES) - else() - set(LIEF_NOT_FOUND_MESSAGE - "LIEF does not recognize component `${_comp}`.") - set(LIEF_FOUND FALSE) - return() - endif() -endforeach() - - -# Validate component selection makes sense -if(LIEF_comp_STATIC AND LIEF_comp_SHARED) - set(LIEF_NOT_FOUND_MESSAGE - "LIEF `STATIC` and `SHARED` components are mutually exclusive.") - set(LIEF_FOUND FALSE) - return() -endif() - - -# These files are generated by CMake and hold the LIEF library target(s). -set(LIEF_static_export "${CMAKE_CURRENT_LIST_DIR}/LIEFExport-static.cmake") -set(LIEF_shared_export "${CMAKE_CURRENT_LIST_DIR}/LIEFExport-shared.cmake") - - -# Helper macro to load the requested targets, where `lib_type` is `static` or -# `shared` -macro(LIEF_load_targets lib_type) - if(NOT EXISTS "${LIEF_${lib_type}_export}") - set(LIEF_NOT_FOUND_MESSAGE - "LIEF `${lib_type}` libraries were requested but not found.") - set(LIEF_FOUND FALSE) - return() - endif () - - if("${lib_type}" STREQUAL "static") - # Need to find all dependencies even if they're private when LIEF is - # compiled statically - include(CMakeFindDependencyMacro) - - if(@LIEF_EXTERNAL_MBEDTLS@) - find_dependency(MbedTLS) - endif() - - if(@LIEF_EXTERNAL_UTF8CPP@) - find_dependency(utf8cpp) - endif() - - if(@LIEF_EXTERNAL_SPDLOG@) - find_dependency(spdlog) - endif() - - if(@LIEF_ENABLE_JSON@ AND @LIEF_NLOHMANN_JSON_EXTERNAL@) - find_dependency(nlohmann_json) - endif() - - if(NOT @LIEF_DISABLE_FROZEN@ AND @LIEF_OPT_FROZEN_EXTERNAL@) - find_dependency(frozen) - endif() - endif() - - # Include the respective targets file - include("${LIEF_${lib_type}_export}") -endmacro() - -# Run the logic to choose static or shared libraries -# 1. Check components -if(LIEF_comp_STATIC) - LIEF_load_targets("static") -elseif(LIEF_comp_SHARED) - LIEF_load_targets("shared") -# 2. Check LIEF-only library selection -elseif(DEFINED LIEF_SHARED_LIBS AND LIEF_SHARED_LIBS) - LIEF_load_targets("shared") -elseif(DEFINED LIEF_SHARED_LIBS AND NOT LIEF_SHARED_LIBS) - LIEF_load_targets("static") -# 3. Check CMake build type and choose what's available -elseif(BUILD_SHARED_LIBS) - if(EXISTS "${LIEF_shared_export}") - LIEF_load_targets("shared") - else() - LIEF_load_targets("static") - endif() -else() - if(EXISTS "${LIEF_static_export}") - LIEF_load_targets("static") - else() - LIEF_load_targets("shared") - endif() -endif() - - -# Attach location of public interface libraries that don't have -# their own CMake config that would otherwise be found using `find_dependency` - -# Header-only library can be found relatively easily -if(@LIEF_EXTERNAL_LEAF@) - find_path(BOOST_LEAF_INCLUDE_DIR boost/leaf.hpp) - if(NOT BOOST_LEAF_INCLUDE_DIR) - set(LIEF_NOT_FOUND_MESSAGE "Could not find include directory with 'boost/leaf.hpp'. Consider setting `BOOST_LEAF_INCLUDE_DIR` during CMake configuration") - set(LIEF_FOUND FALSE) - return() - endif() - set_property(TARGET LIEF::LIEF APPEND PROPERTY - INTERFACE_SYSTEM_INCLUDE_DIRECTORIES "${BOOST_LEAF_INCLUDE_DIR}" - ) -endif() - -# Header-only library can be found relatively easily -if(@LIEF_EXTERNAL_SPAN@) - find_path(TCB_SPAN_INCLUDE_DIR tcb/span.hpp) - if(NOT TCB_SPAN_INCLUDE_DIR) - set(LIEF_NOT_FOUND_MESSAGE "Could not find include directory with 'tcb/span.hpp'. Consider setting `TCB_SPAN_INCLUDE_DIR` during CMake configuration") - set(LIEF_FOUND FALSE) - return() - endif() - set_property(TARGET LIEF::LIEF APPEND PROPERTY - INTERFACE_SYSTEM_INCLUDE_DIRECTORIES "${TCB_SPAN_INCLUDE_DIR}" - ) -endif() - - -# Set this for backwards compatibility. This isn't quite the path to the -# actual library file, but using the target is strictly better because it -# includes all other information needed to correctly link and use LIEF -set(LIEF_LIBRARIES LIEF::LIEF) - -# Set this for backwards compatibility -get_target_property(LIEF_INCLUDE_DIRS LIEF::LIEF INTERFACE_INCLUDE_DIRECTORIES) - -# Set the following for backwards compatibility -if(LIEF_INCLUDE_DIR AND EXISTS "${LIEF_INCLUDE_DIR}/LIEF/version.h") - file(STRINGS "${LIEF_INCLUDE_DIR}/LIEF/version.h" LIEF_H REGEX "^#define LIEF_VERSION \"[^\"]*\"$") - - string(REGEX REPLACE "^.*LIEF_VERSION \"([0-9]+).*$" "\\1" LIEF_VERSION_MAJOR "${LIEF_H}") - string(REGEX REPLACE "^.*LIEF_VERSION \"[0-9]+\\.([0-9]+).*$" "\\1" LIEF_VERSION_MINOR "${LIEF_H}") - string(REGEX REPLACE "^.*LIEF_VERSION \"[0-9]+\\.[0-9]+\\.([0-9]+).*$" "\\1" LIEF_VERSION_PATCH "${LIEF_H}") - set(LIEF_VERSION_STRING "${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}") - - set(LIEF_MAJOR_VERSION "${LIEF_VERSION_MAJOR}") - set(LIEF_MINOR_VERSION "${LIEF_VERSION_MINOR}") - set(LIEF_PATCH_VERSION "${LIEF_VERSION_PATCH}") -endif() diff --git a/vendor/lief/MANIFEST.in b/vendor/lief/MANIFEST.in deleted file mode 100644 index 9105b32..0000000 --- a/vendor/lief/MANIFEST.in +++ /dev/null @@ -1,26 +0,0 @@ -include README.md LICENSE setup.cfg CMakeLists.txt LIEF.pc.in LIEFConfig.cmake.in - -# Examples -recursive-include examples * - -# LIEF Sources -recursive-include src * -recursive-include include * - -recursive-include third-party * -recursive-include cmake * -recursive-include scripts * - -# Bindings -recursive-include api * -prune api/python/build - -# Global exclude -recursive-exclude *.egg-info *.so - -# Install script -recursive-include package * - -# Documentation -recursive-include doc * - diff --git a/vendor/lief/README.md b/vendor/lief/README.md index 9e45399..b4fb91f 100644 --- a/vendor/lief/README.md +++ b/vendor/lief/README.md @@ -1,101 +1,106 @@

-
+

- -

- - - -   - - Linux x86-64 CI status - -   - - Linux AArch64 CI status - -   - - Android CI status - -   - - macOS CI status - -   - - iOS CI status - -   - - Windows CI status - -   - - - -   - - Twitter Follow - -

-
+

- Blog • - Documentation • - About + Blog • + Documentation • + About


# About -The purpose of this project is to provide a cross platform library which can parse, +The purpose of this project is to provide a cross-platform library to parse, modify and abstract ELF, PE and MachO formats. -Main features: +**Main features**: - * **Parsing**: LIEF can parse ELF, PE, MachO, OAT, DEX, VDEX, ART and provides an user-friendly API to access to format internals. - * **Modify**: LIEF enables to modify some parts of these formats + * **Parsing**: LIEF can parse [ELF](https://lief.re/doc/latest/formats/elf/index.html), [PE](https://lief.re/doc/latest/formats/pe/index.html), [MachO](https://lief.re/doc/latest/formats/macho/index.html), [COFF](https://lief.re/doc/latest/formats/coff/index.html), OAT, DEX, VDEX, ART and provides a user-friendly API to access their internals. + * **Modify**: LIEF can be used to modify some parts of these formats (adding a section, changing a symbol's name, ...) * **Abstract**: Three formats have common features like sections, symbols, entry point... LIEF factors them. - * **API**: LIEF can be used in C, C++ and Python + * **API**: You can use LIEF via [C++](https://lief.re/doc/latest/doxygen/), Python, [Rust](https://lief-rs.s3.fr-par.scw.cloud/doc/latest/lief/index.html), and + [Node.js](https://github.com/Piebald-AI/node-lief) (unofficial, AI-generated) + +**Extended features**: + + * [**Runtime**](https://lief.re/doc/latest/runtime/intro.html) + * [**DWARF/PDB** Support](https://lief.re/doc/latest/extended/debug_info/index.html) + * [**Objective-C** Metadata](https://lief.re/doc/latest/extended/objc/index.html) + * [**Dyld Shared Cache**](https://lief.re/doc/latest/extended/dsc/index.html) with support for extracting Dylib + * [**Disassembler**](https://lief.re/doc/latest/extended/disassembler/index.html): AArch64, x86/x86-64, ARM, RISC-V, Mips, PowerPC, eBPF + * [**Assembler**](https://lief.re/doc/latest/extended/assembler/index.html): AArch64, x86/x86-64, RISC-V + +**Plugins**: + + * [**Ghidra**](https://lief.re/doc/latest/plugins/ghidra/index.html) + * [**BinaryNinja**](https://lief.re/doc/latest/plugins/binaryninja/index.html) + +# Sponsors + +
+

+ +
+
+

# Content - [About](#about) -- [Download / Install](#downloads--install) +- [Downloads / Install](#downloads--install) - [Getting started](#getting-started) +- [Blog](https://lief.re/blog/) - [Documentation](#documentation) - - [Sphinx](https://lief-project.github.io/doc/stable/index.html) - - [Doxygen](https://lief-project.github.io/doc/latest/doxygen/index.html) + - [Rust](https://lief.re/doc/stable/rust/lief/) + - [Sphinx](https://lief.re/doc/latest/index.html) + - [Doxygen](https://lief.re/doc/latest/doxygen/index.html) - Tutorials: - - [Parse and manipulate formats](https://lief-project.github.io/doc/latest/tutorials/01_play_with_formats.html) - - [Create a PE from scratch](https://lief-project.github.io/doc/latest/tutorials/02_pe_from_scratch.html) - - [Play with ELF symbols](https://lief-project.github.io/doc/latest/tutorials/03_elf_change_symbols.html) - - [ELF Hooking](https://lief-project.github.io/doc/latest/tutorials/04_elf_hooking.html) - - [Infecting the plt/got](https://lief-project.github.io/doc/latest/tutorials/05_elf_infect_plt_got.html) - - [PE Hooking](https://lief-project.github.io/doc/latest/tutorials/06_pe_hooking.html) - - [PE Resources](https://lief-project.github.io/doc/latest/tutorials/07_pe_resource.html) - - [Transforming an ELF executable into a library](https://lief-project.github.io/doc/latest/tutorials/08_elf_bin2lib.html) - - [How to use frida on a non-rooted device](https://lief-project.github.io/doc/latest/tutorials/09_frida_lief.html) - - [Android formats](https://lief-project.github.io/doc/latest/tutorials/10_android_formats.html) - - [Mach-O modification](https://lief-project.github.io/doc/latest/tutorials/11_macho_modification.html) - - [ELF Coredump](https://lief-project.github.io/doc/latest/tutorials/12_elf_coredump.html) - - [PE Authenticode](https://lief-project.github.io/doc/latest/tutorials/13_pe_authenticode.html) + - [Parse and manipulate formats](https://lief.re/doc/latest/tutorials/01_play_with_formats.html) + - [Play with ELF symbols](https://lief.re/doc/latest/tutorials/03_elf_change_symbols.html) + - [PE Resources](https://lief.re/doc/latest/tutorials/07_pe_resource.html) + - [Transforming an ELF executable into a library](https://lief.re/doc/latest/tutorials/08_elf_bin2lib.html) + - [How to use frida on a non-rooted device](https://lief.re/doc/latest/tutorials/09_frida_lief.html) + - [Android formats](https://lief.re/doc/latest/tutorials/10_android_formats.html) + - [Mach-O modification](https://lief.re/doc/latest/tutorials/11_macho_modification.html) + - [ELF Coredump](https://lief.re/doc/latest/tutorials/12_elf_coredump.html) + - [PE Authenticode](https://lief.re/doc/latest/tutorials/13_pe_authenticode.html) - [Contact](#contact) -- [About](#about) +- [About](#about-1) - [Authors](#authors) - [License](#license) - - [Bibtex](#bibtex) + - [BibTeX](#bibtex) ## Downloads / Install -First, make sure to have an updated version of setuptools: +### C++ + +```cmake +find_package(LIEF REQUIRED) +target_link_libraries(my-project LIEF::LIEF) +``` + +### Rust + +```toml +[package] +name = "my-awesome-project" +version = "0.0.1" +edition = "2024" + +[dependencies] +lief = "1.0.0" +``` + +### Homebrew ```console -pip install setuptools --upgrade +brew install lief ``` +### Python + To install the latest **version** (release): ```console @@ -105,22 +110,23 @@ pip install lief To install nightly build: ```console -pip install [--user] --index-url https://lief.s3-website.fr-par.scw.cloud/latest lief==0.13.0.dev0 +pip install [--user] --force-reinstall --index-url https://lief.s3-website.fr-par.scw.cloud/latest lief==2.0.0.dev0 ``` ### Packages +- LIEF Extended: https://extended.lief.re (GitHub OAuth) - **Nightly**: * SDK: https://lief.s3-website.fr-par.scw.cloud/latest/sdk * Python Wheels: https://lief.s3-website.fr-par.scw.cloud/latest/lief -- **v0.12.1**: https://github.com/lief-project/LIEF/releases/tag/0.12.1 +- **v1.0.0**: https://github.com/lief-project/LIEF/releases/tag/1.0.0 Here are guides to install or integrate LIEF: - * [Python](https://lief-project.github.io/doc/latest/installation.html#python) - * [VisualStudio](https://lief-project.github.io/doc/latest/installation.html#visual-studio-integration) - * [XCode](https://lief-project.github.io/doc/latest/installation.html#xcode-integration) - * [CMake](https://lief-project.github.io/doc/latest/installation.html#cmake-integration) + * [Python](https://lief.re/doc/latest/installation.html#python) + * [Visual Studio](https://lief.re/doc/latest/installation.html#visual-studio-integration) + * [Xcode](https://lief.re/doc/latest/installation.html#xcode-integration) + * [CMake](https://lief.re/doc/latest/installation.html#cmake-integration) ## Getting started @@ -131,36 +137,63 @@ import lief # ELF binary = lief.parse("/usr/bin/ls") -print(binary) +for section in binary.sections: + print(section.name, section.virtual_address) # PE -binary = lief.parse("C:\\Windows\\explorer.exe") -print(binary) +binary = lief.parse(r"C:\Windows\explorer.exe") +if (rheader := binary.rich_header) is not None: + print(rheader.key) # Mach-O binary = lief.parse("/usr/bin/ls") -print(binary) +if (fixups := binary.dyld_chained_fixups) is not None: + print(fixups) +``` + +### Rust + +```rust +use lief::Binary; +use lief::pe::debug::Entries::CodeViewPDB; + +if let Some(Binary::PE(pe)) = Binary::parse(path.as_str()) { + for entry in pe.debug() { + if let CodeViewPDB(pdb_view) = entry { + println!("{}", pdb_view.filename()); + } + } +} ``` ### C++ ```cpp +#include #include int main(int argc, char** argv) { // ELF if (std::unique_ptr elf = LIEF::ELF::Parser::parse("/bin/ls")) { - std::cout << *elf << '\n'; + for (const LIEF::ELF::Section& section : elf->sections()) { + std::cout << section.name() << ' ' << section.virtual_address() << '\n'; + } } // PE if (std::unique_ptr pe = LIEF::PE::Parser::parse("C:\\Windows\\explorer.exe")) { - std::cout << *pe << '\n'; + if (const LIEF::PE::RichHeader* rheader = pe->rich_header()) { + std::cout << rheader->key() << '\n'; + } } // Mach-O if (std::unique_ptr macho = LIEF::MachO::Parser::parse("/bin/ls")) { - std::cout << *macho << '\n'; + for (const LIEF::MachO::Binary& bin : *macho) { + if (const LIEF::MachO::DyldChainedFixups* fixups = bin.dyld_chained_fixups()) { + std::cout << *fixups << '\n'; + } + } } return 0; @@ -168,48 +201,28 @@ int main(int argc, char** argv) { ``` -### C (Limited API) - -```cpp -#include - -int main(int argc, char** argv) { - Elf_Binary_t* elf = elf_parse("/usr/bin/ls"); - - Elf_Section_t** sections = elf->sections; - - for (size_t i = 0; sections[i] != NULL; ++i) { - printf("%s\n", sections[i]->name); - } - - elf_binary_destroy(elf); - return 0; -} -``` - ## Documentation -* [Main documentation](https://lief-project.github.io/doc/latest/index.html) -* [Tutorial](https://lief-project.github.io/doc/latest/tutorials/index.html) -* [API](https://lief-project.github.io/doc/latest/api/index.html) -* [Doxygen](https://lief-project.github.io/doc/latest/doxygen/index.html) +* [Main documentation](https://lief.re/doc/latest/index.html) +* [Doxygen](https://lief.re/doc/latest/doxygen/index.html) +* [Rust](https://lief.re/doc/stable/rust/lief/) ## Contact * **Mail**: contact at lief re -* **Gitter**: [lief-project](https://gitter.im/lief-project) +* **Discord**: [LIEF](https://discord.gg/7hRFGWYedu) ## About ### Authors -Romain Thomas ([@rh0main](https://twitter.com/rh0main)) - [Quarkslab](https://www.quarkslab.com) +Romain Thomas ([@rh0main](https://www.romainthomas.fr/)) - Formerly at [Quarkslab](https://www.quarkslab.com) ### License -LIEF is provided under the [Apache 2.0 license](https://github.com/lief-project/LIEF/blob/0.12.1/LICENSE). +[Apache 2.0](https://github.com/lief-project/LIEF/blob/1.0.0/LICENSE). -### Bibtex +### BibTeX ```bibtex @MISC {LIEF, @@ -220,5 +233,3 @@ LIEF is provided under the [Apache 2.0 license](https://github.com/lief-project/ year = "2017" } ``` - - diff --git a/vendor/lief/api/CMakeLists.txt b/vendor/lief/api/CMakeLists.txt new file mode 100644 index 0000000..6e1675d --- /dev/null +++ b/vendor/lief/api/CMakeLists.txt @@ -0,0 +1,8 @@ +if (LIEF_PYTHON_API) + add_subdirectory(python) +endif() + +if(LIEF_RUST_API) + add_subdirectory(rust) +endif() + diff --git a/vendor/lief/api/c/CMakeLists.txt b/vendor/lief/api/c/CMakeLists.txt deleted file mode 100644 index d0af70a..0000000 --- a/vendor/lief/api/c/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -include_directories( - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF" - "${CMAKE_CURRENT_SOURCE_DIR}/include" -) - -set(LIEF_C_INCLUDE_FILES - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/LIEF.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/logging.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/types.h" -) - -set(LIEF_C_SRC "${CMAKE_CURRENT_LIST_DIR}/logging.cpp") - -if (LIEF_ELF) - include("${CMAKE_CURRENT_LIST_DIR}/ELF/CMakeLists.txt") -endif() - -if (LIEF_PE) - include("${CMAKE_CURRENT_LIST_DIR}/PE/CMakeLists.txt") -endif() - -if (LIEF_MACHO) - include("${CMAKE_CURRENT_LIST_DIR}/MachO/CMakeLists.txt") -endif() - -source_group("Header Files\\C API" FILES ${LIEF_C_INCLUDE_FILES}) - -target_sources(LIB_LIEF PRIVATE "${LIEF_C_SRC}" ${LIEF_C_INCLUDE_FILES}) - diff --git a/vendor/lief/api/c/ELF/Binary.cpp b/vendor/lief/api/c/ELF/Binary.cpp deleted file mode 100644 index 953d58f..0000000 --- a/vendor/lief/api/c/ELF/Binary.cpp +++ /dev/null @@ -1,114 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Section.h" -#include "LIEF/ELF/Segment.h" -#include "LIEF/ELF/Header.h" -#include "LIEF/ELF/Symbol.h" - -#include "LIEF/ELF/Parser.hpp" -#include "LIEF/ELF/Binary.hpp" - -#include "Section.hpp" -#include "Segment.hpp" -#include "DynamicEntry.hpp" -#include "Symbol.hpp" -#include "Header.hpp" -#include "Binary.hpp" - -using namespace LIEF::ELF; - -namespace LIEF { -namespace ELF { -void init_c_binary(Elf_Binary_t* c_binary, Binary* binary) { - c_binary->handler = reinterpret_cast(binary); - c_binary->name = binary->name().c_str(); - c_binary->type = static_cast(binary->type()); - c_binary->interpreter = nullptr; - if (binary->has_interpreter()) { - const std::string& interp = binary->interpreter(); - c_binary->interpreter = static_cast(malloc((interp.size() + 1) * sizeof(char))); - std::memcpy( - reinterpret_cast(const_cast(c_binary->interpreter)), - reinterpret_cast(interp.data()), - interp.size()); - reinterpret_cast(const_cast(c_binary->interpreter))[interp.size()] = '\0'; - } - - - init_c_header(c_binary, binary); - init_c_sections(c_binary, binary); - init_c_segments(c_binary, binary); - init_c_dynamic_symbols(c_binary, binary); - init_c_static_symbols(c_binary, binary); - init_c_dynamic_entries(c_binary, binary); - - -} - -} -} - -Elf_Binary_t* elf_parse(const char *file) { - Binary* binary = Parser::parse(file).release(); - auto* c_binary = static_cast(malloc(sizeof(Elf_Binary_t))); - memset(c_binary, 0, sizeof(Elf_Binary_t)); - init_c_binary(c_binary, binary); - return c_binary; -} - -// Binary Methods -// ============== - -int elf_binary_save_header(Elf_Binary_t* binary) { - Header& hdr = reinterpret_cast(binary->handler)->header(); - - hdr.file_type(static_cast(binary->header.file_type)); - hdr.machine_type(static_cast(binary->header.machine_type)); - hdr.object_file_version(static_cast(binary->header.object_file_version)); - hdr.program_headers_offset(binary->header.program_headers_offset); - hdr.section_headers_offset(binary->header.section_headers_offset); - hdr.processor_flag(binary->header.processor_flags); - hdr.header_size(binary->header.header_size); - hdr.program_header_size(binary->header.program_header_size); - hdr.numberof_segments(binary->header.numberof_segments); - hdr.section_header_size(binary->header.section_header_size); - hdr.numberof_sections(binary->header.numberof_sections); - hdr.section_name_table_idx(binary->header.name_string_table_idx); - hdr.entrypoint(binary->header.entrypoint); - - //TODO: identity - return 1; -} - - -void elf_binary_destroy(Elf_Binary_t* binary) { - destroy_sections(binary); - destroy_segments(binary); - destroy_dynamic_symbols(binary); - destroy_static_symbols(binary); - destroy_dynamic_entries(binary); - - if (binary->interpreter != nullptr) { - free(const_cast(binary->interpreter)); - } - - delete reinterpret_cast(binary->handler); - free(binary); - -} -//} diff --git a/vendor/lief/api/c/ELF/Binary.hpp b/vendor/lief/api/c/ELF/Binary.hpp deleted file mode 100644 index 7d61a8d..0000000 --- a/vendor/lief/api/c/ELF/Binary.hpp +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_BINARY_CPP_C_API_ -#define LIEF_ELF_BINARY_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_binary(Elf_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/CMakeLists.txt b/vendor/lief/api/c/ELF/CMakeLists.txt deleted file mode 100644 index 61d8bf9..0000000 --- a/vendor/lief/api/c/ELF/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -include_directories( - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF" - "${CMAKE_CURRENT_SOURCE_DIR}/include" -) - -set(LIEF_C_ELF_SRC - "${CMAKE_CURRENT_LIST_DIR}/Symbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Segment.cpp" - "${CMAKE_CURRENT_LIST_DIR}/DynamicEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Header.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Binary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/EnumToString.cpp" - "${CMAKE_CURRENT_LIST_DIR}/utils.cpp" -) - - -set(LIEF_API_C_ELF_INCLUDE_FILES_CPP - "${CMAKE_CURRENT_LIST_DIR}/Binary.hpp" - "${CMAKE_CURRENT_LIST_DIR}/DynamicEntry.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Header.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Segment.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Symbol.hpp" -) - -set(LIEF_API_C_ELF_INCLUDE_FILES_C - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/Binary.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/DynamicEntry.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/EnumToString.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/Header.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/Section.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/Segment.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/Symbol.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/enums.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/ELF/utils.h" -) - -set(LIEF_C_ELF_INC "${LIEF_API_C_ELF_INCLUDE_FILES_C}" "${LIEF_API_C_ELF_INCLUDE_FILES_CPP}") - -source_group("Source Files\\C API\\ELF" FILES ${LIEF_API_C_ELF_SRC}) -source_group("Header Files\\C API\\ELF" FILES ${LIEF_C_ELF_INC}) - -target_sources(LIB_LIEF PRIVATE "${LIEF_C_ELF_SRC}" "${LIEF_C_ELF_INC}") diff --git a/vendor/lief/api/c/ELF/DynamicEntry.cpp b/vendor/lief/api/c/ELF/DynamicEntry.cpp deleted file mode 100644 index 51e6267..0000000 --- a/vendor/lief/api/c/ELF/DynamicEntry.cpp +++ /dev/null @@ -1,238 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "DynamicEntry.hpp" - -#include "LIEF/ELF/DynamicEntryFlags.hpp" -#include "LIEF/ELF/DynamicSharedObject.hpp" -#include "LIEF/ELF/DynamicEntryLibrary.hpp" -#include "LIEF/ELF/DynamicEntryRpath.hpp" -#include "LIEF/ELF/DynamicEntryRunPath.hpp" -#include "LIEF/ELF/DynamicEntryArray.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_dynamic_entries(Elf_Binary_t* c_binary, Binary* binary) { - - Binary::it_dynamic_entries dyn_entries = binary->dynamic_entries(); - c_binary->dynamic_entries = static_cast( - malloc((dyn_entries.size() + 1) * sizeof(Elf_DynamicEntry_t**))); - - for (size_t i = 0; i < dyn_entries.size(); ++i) { - DynamicEntry& entry = dyn_entries[i]; - switch(entry.tag()) { - case DYNAMIC_TAGS::DT_NEEDED: - { - - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_Library_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - e->name = reinterpret_cast(&entry)->name().c_str(); - - c_binary->dynamic_entries[i] = reinterpret_cast(e); - break; - } - - case DYNAMIC_TAGS::DT_SONAME: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_SharedObject_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - e->name = reinterpret_cast(&entry)->name().c_str(); - - c_binary->dynamic_entries[i] = reinterpret_cast(e); - break; - } - - case DYNAMIC_TAGS::DT_RPATH: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_Rpath_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - e->rpath = reinterpret_cast(&entry)->name().c_str(); - - c_binary->dynamic_entries[i] = reinterpret_cast(e); - - break; - } - - case DYNAMIC_TAGS::DT_RUNPATH: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_RunPath_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - e->runpath = reinterpret_cast(&entry)->name().c_str(); - - c_binary->dynamic_entries[i] = reinterpret_cast(e); - - break; - } - - case DYNAMIC_TAGS::DT_INIT_ARRAY: - case DYNAMIC_TAGS::DT_FINI_ARRAY: - case DYNAMIC_TAGS::DT_PREINIT_ARRAY: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_Array_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - const std::vector& array = reinterpret_cast(&entry)->array(); - e->array = static_cast(malloc((array.size() + 1) * sizeof(uint64_t))); - for (size_t i = 0; i < array.size(); ++i) { - e->array[i] = array[i]; - } - e->array[array.size()] = 0; - c_binary->dynamic_entries[i] = reinterpret_cast(e); - - break; - } - - case DYNAMIC_TAGS::DT_FLAGS: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_Flags_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - const DynamicEntryFlags::flags_list_t& flags = reinterpret_cast(&entry)->flags(); - e->flags = static_cast(malloc((flags.size() + 1) * sizeof(enum LIEF_ELF_DYNAMIC_FLAGS))); - e->flags_1 = nullptr; - - auto it = std::begin(flags); - - for (size_t i = 0; it != std::end(flags); ++i, ++it) { - e->flags[i] = static_cast(*it); - } - - e->flags[flags.size()] = static_cast(0); - c_binary->dynamic_entries[i] = reinterpret_cast(e); - - break; - } - - case DYNAMIC_TAGS::DT_FLAGS_1: - { - auto* e = static_cast( - malloc(sizeof(Elf_DynamicEntry_Flags_t))); - - e->tag = static_cast(entry.tag()); - e->value = entry.value(); - const DynamicEntryFlags::flags_list_t& flags = reinterpret_cast(&entry)->flags(); - e->flags_1 = static_cast(malloc((flags.size() + 1) * sizeof(enum LIEF_ELF_DYNAMIC_FLAGS_1))); - e->flags = nullptr; - - auto it = std::begin(flags); - - for (size_t i = 0; it != std::end(flags); ++i, ++it) { - e->flags_1[i] = static_cast(*it); - } - - e->flags_1[flags.size()] = static_cast(0); - c_binary->dynamic_entries[i] = reinterpret_cast(e); - - break; - } - - - - - default: - { - c_binary->dynamic_entries[i] = - static_cast(malloc(sizeof(Elf_DynamicEntry_t))); - c_binary->dynamic_entries[i]->tag = static_cast(entry.tag()); - c_binary->dynamic_entries[i]->value = entry.value(); - - } - } - } - - c_binary->dynamic_entries[dyn_entries.size()] = nullptr; - -} - - - -void destroy_dynamic_entries(Elf_Binary_t* c_binary) { - - Elf_DynamicEntry_t **dynamic_entries = c_binary->dynamic_entries; - for (size_t idx = 0; dynamic_entries[idx] != nullptr; ++idx) { - switch(static_cast(dynamic_entries[idx]->tag)) { - case DYNAMIC_TAGS::DT_NEEDED: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - case DYNAMIC_TAGS::DT_SONAME: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - case DYNAMIC_TAGS::DT_RPATH: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - case DYNAMIC_TAGS::DT_RUNPATH: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - case DYNAMIC_TAGS::DT_INIT_ARRAY: - case DYNAMIC_TAGS::DT_FINI_ARRAY: - case DYNAMIC_TAGS::DT_PREINIT_ARRAY: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - case DYNAMIC_TAGS::DT_FLAGS: - case DYNAMIC_TAGS::DT_FLAGS_1: - { - free(reinterpret_cast(dynamic_entries[idx])); - break; - } - - default: - { - - free(dynamic_entries[idx]); - } - - - } - } - free(c_binary->dynamic_entries); - -} - -} -} - - diff --git a/vendor/lief/api/c/ELF/DynamicEntry.hpp b/vendor/lief/api/c/ELF/DynamicEntry.hpp deleted file mode 100644 index 375e662..0000000 --- a/vendor/lief/api/c/ELF/DynamicEntry.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_DYNAMIC_ENTRY_CPP_C_API_ -#define LIEF_ELF_DYNAMIC_ENTRY_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -#include "LIEF/ELF/DynamicEntry.h" -#include "LIEF/ELF/DynamicEntry.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_dynamic_entries(Elf_Binary_t* c_binary, Binary* binary); -void destroy_dynamic_entries(Elf_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/EnumToString.cpp b/vendor/lief/api/c/ELF/EnumToString.cpp deleted file mode 100644 index cd4eeec..0000000 --- a/vendor/lief/api/c/ELF/EnumToString.cpp +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/ELF/EnumToString.h" -#include "LIEF/ELF/EnumToString.hpp" - -#include "LIEF/ELF/enums.h" -#include "LIEF/ELF/enums.hpp" - -extern "C" -{ - const char* E_TYPE_to_string(enum LIEF_ELF_E_TYPE e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* SYMBOL_BINDINGS_to_string(enum LIEF_ELF_SYMBOL_BINDINGS e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* VERSION_to_string(enum LIEF_ELF_VERSION e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ARCH_to_string(enum LIEF_ELF_ARCH e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* SEGMENT_TYPES_to_string(enum LIEF_ELF_SEGMENT_TYPES e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* DYNAMIC_TAGS_to_string(enum LIEF_ELF_DYNAMIC_TAGS e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ELF_SECTION_TYPES_to_string(enum LIEF_ELF_ELF_SECTION_TYPES e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ELF_SECTION_FLAGS_to_string(enum LIEF_ELF_ELF_SECTION_FLAGS e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ELF_SYMBOL_TYPES_to_string(enum LIEF_ELF_ELF_SYMBOL_TYPES e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ELF_CLASS_to_string(enum LIEF_ELF_ELF_CLASS e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* ELF_DATA_to_string(enum LIEF_ELF_ELF_DATA e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* OS_ABI_to_string(enum LIEF_ELF_OS_ABI e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* DYNAMIC_FLAGS_to_string(enum LIEF_ELF_DYNAMIC_FLAGS e) { - return LIEF::ELF::to_string(static_cast(e)); - } - - const char* DYNAMIC_FLAGS_1_to_string(enum LIEF_ELF_DYNAMIC_FLAGS_1 e) { - return LIEF::ELF::to_string(static_cast(e)); - } - -} diff --git a/vendor/lief/api/c/ELF/Header.cpp b/vendor/lief/api/c/ELF/Header.cpp deleted file mode 100644 index e579e20..0000000 --- a/vendor/lief/api/c/ELF/Header.cpp +++ /dev/null @@ -1,46 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Header.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_header(Elf_Binary_t* c_binary, Binary* binary) { - - const Header& hdr = binary->header(); - c_binary->header.file_type = static_cast(hdr.file_type()); - c_binary->header.machine_type = static_cast(hdr.machine_type()); - c_binary->header.object_file_version = static_cast(hdr.object_file_version()); - c_binary->header.program_headers_offset = hdr.program_headers_offset(); - c_binary->header.section_headers_offset = hdr.section_headers_offset(); - c_binary->header.processor_flags = hdr.processor_flag(); - c_binary->header.header_size = hdr.header_size(); - c_binary->header.program_header_size = hdr.program_header_size(); - c_binary->header.numberof_segments = hdr.numberof_segments(); - c_binary->header.section_header_size = hdr.section_header_size(); - c_binary->header.numberof_sections = hdr.numberof_sections(); - c_binary->header.name_string_table_idx = hdr.section_name_table_idx(); - c_binary->header.entrypoint = hdr.entrypoint(); - const Header::identity_t& ident = hdr.identity(); - std::copy( - std::begin(ident), - std::end(ident), - c_binary->header.identity); - -} - -} -} diff --git a/vendor/lief/api/c/ELF/Header.hpp b/vendor/lief/api/c/ELF/Header.hpp deleted file mode 100644 index 20190a7..0000000 --- a/vendor/lief/api/c/ELF/Header.hpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_HEADER_CPP_C_API_ -#define LIEF_ELF_HEADER_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -#include "LIEF/ELF/Header.h" -#include "LIEF/ELF/Header.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_header(Elf_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/Section.cpp b/vendor/lief/api/c/ELF/Section.cpp deleted file mode 100644 index 109d26e..0000000 --- a/vendor/lief/api/c/ELF/Section.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Section.hpp" - -namespace LIEF { -namespace ELF { -void init_c_sections(Elf_Binary_t* c_binary, Binary* binary) { - - Binary::it_sections sections = binary->sections(); - - c_binary->sections = static_cast( - malloc((sections.size() + 1) * sizeof(Elf_Section_t**))); - - for (size_t i = 0; i < sections.size(); ++i) { - Section& b_section = sections[i]; - c_binary->sections[i] = static_cast(malloc(sizeof(Elf_Section_t))); - span section_content = b_section.content(); - auto* content = static_cast(malloc(section_content.size() * sizeof(uint8_t))); - std::copy(std::begin(section_content), std::end(section_content), - content); - - c_binary->sections[i]->name = b_section.fullname().c_str(); - c_binary->sections[i]->flags = b_section.flags(); - c_binary->sections[i]->type = static_cast(b_section.type()); - c_binary->sections[i]->virtual_address = b_section.virtual_address(); - c_binary->sections[i]->offset = b_section.file_offset(); - c_binary->sections[i]->original_size = b_section.original_size(); - c_binary->sections[i]->link = b_section.link(); - c_binary->sections[i]->info = b_section.information(); - c_binary->sections[i]->alignment = b_section.alignment(); - c_binary->sections[i]->entry_size = b_section.entry_size(); - c_binary->sections[i]->content = content; - c_binary->sections[i]->size = section_content.size(); - c_binary->sections[i]->entropy = b_section.entropy(); - } - c_binary->sections[sections.size()] = nullptr; - -} - - - -void destroy_sections(Elf_Binary_t* c_binary) { - - Elf_Section_t **sections = c_binary->sections; - for (size_t idx = 0; sections[idx] != nullptr; ++idx) { - free(sections[idx]->content); - free(sections[idx]); - } - free(c_binary->sections); - -} - -} -} - - diff --git a/vendor/lief/api/c/ELF/Section.hpp b/vendor/lief/api/c/ELF/Section.hpp deleted file mode 100644 index 4404af3..0000000 --- a/vendor/lief/api/c/ELF/Section.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_SECTION_CPP_C_API_ -#define LIEF_ELF_SECTION_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -#include "LIEF/ELF/Section.h" -#include "LIEF/ELF/Section.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_sections(Elf_Binary_t* c_binary, Binary* binary); -void destroy_sections(Elf_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/Segment.cpp b/vendor/lief/api/c/ELF/Segment.cpp deleted file mode 100644 index decbbf2..0000000 --- a/vendor/lief/api/c/ELF/Segment.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Segment.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_segments(Elf_Binary_t* c_binary, Binary* binary) { - - Binary::it_segments segments = binary->segments(); - c_binary->segments = static_cast( - malloc((segments.size() + 1) * sizeof(Elf_Segment_t**))); - for (size_t i = 0; i < segments.size(); ++i) { - Segment& segment = segments[i]; - - span segment_content = segment.content(); - auto* content = static_cast(malloc(segment_content.size() * sizeof(uint8_t))); - std::copy( - std::begin(segment_content), - std::end(segment_content), - content); - - c_binary->segments[i] = static_cast(malloc(sizeof(Elf_Segment_t))); - c_binary->segments[i]->type = static_cast(segment.type()); - c_binary->segments[i]->flags = static_cast(segment.flags()); - c_binary->segments[i]->virtual_address = segment.virtual_address(); - c_binary->segments[i]->virtual_size = segment.virtual_size(); - c_binary->segments[i]->offset = segment.file_offset(); - c_binary->segments[i]->alignment = segment.alignment(); - c_binary->segments[i]->size = segment_content.size(); - c_binary->segments[i]->content = content; - } - - c_binary->segments[segments.size()] = nullptr; - -} - - - -void destroy_segments(Elf_Binary_t* c_binary) { - - Elf_Segment_t **segments = c_binary->segments; - for (size_t idx = 0; segments[idx] != nullptr; ++idx) { - free(segments[idx]->content); - free(segments[idx]); - } - free(c_binary->segments); - -} - -} -} - - diff --git a/vendor/lief/api/c/ELF/Segment.hpp b/vendor/lief/api/c/ELF/Segment.hpp deleted file mode 100644 index e2a50c9..0000000 --- a/vendor/lief/api/c/ELF/Segment.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_SEGMENT_CPP_C_API_ -#define LIEF_ELF_SEGMENT_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -#include "LIEF/ELF/Segment.h" -#include "LIEF/ELF/Segment.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_segments(Elf_Binary_t* c_binary, Binary* binary); -void destroy_segments(Elf_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/Symbol.cpp b/vendor/lief/api/c/ELF/Symbol.cpp deleted file mode 100644 index 2ca89b9..0000000 --- a/vendor/lief/api/c/ELF/Symbol.cpp +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Symbol.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_dynamic_symbols(Elf_Binary_t* c_binary, Binary* binary) { - Binary::it_dynamic_symbols dyn_symb = binary->dynamic_symbols(); - - c_binary->dynamic_symbols = static_cast( - malloc((dyn_symb.size() + 1) * sizeof(Elf_Symbol_t**))); - - for (size_t i = 0; i < dyn_symb.size(); ++i) { - Symbol& b_sym = dyn_symb[i]; - c_binary->dynamic_symbols[i] = static_cast(malloc(sizeof(Elf_Symbol_t))); - c_binary->dynamic_symbols[i]->name = b_sym.name().c_str(); - c_binary->dynamic_symbols[i]->type = static_cast(b_sym.type()); - c_binary->dynamic_symbols[i]->binding = static_cast(b_sym.binding()); - c_binary->dynamic_symbols[i]->other = b_sym.other(); - c_binary->dynamic_symbols[i]->shndx = b_sym.shndx(); - c_binary->dynamic_symbols[i]->value = b_sym.value(); - c_binary->dynamic_symbols[i]->size = b_sym.size(); - c_binary->dynamic_symbols[i]->information = b_sym.information(); - c_binary->dynamic_symbols[i]->is_exported = b_sym.is_exported(); - c_binary->dynamic_symbols[i]->is_imported = b_sym.is_imported(); - } - c_binary->dynamic_symbols[dyn_symb.size()] = nullptr; - - - -} - - -void init_c_static_symbols(Elf_Binary_t* c_binary, Binary* binary) { - Binary::it_static_symbols static_symb = binary->static_symbols(); - - c_binary->static_symbols = static_cast( - malloc((static_symb.size() + 1) * sizeof(Elf_Symbol_t**))); - - for (size_t i = 0; i < static_symb.size(); ++i) { - Symbol& b_sym = static_symb[i]; - c_binary->static_symbols[i] = static_cast(malloc(sizeof(Elf_Symbol_t))); - c_binary->static_symbols[i]->name = b_sym.name().c_str(); - c_binary->static_symbols[i]->type = static_cast(b_sym.type()); - c_binary->static_symbols[i]->binding = static_cast(b_sym.binding()); - c_binary->static_symbols[i]->other = b_sym.other(); - c_binary->static_symbols[i]->shndx = b_sym.shndx(); - c_binary->static_symbols[i]->value = b_sym.value(); - c_binary->static_symbols[i]->size = b_sym.size(); - c_binary->static_symbols[i]->information = b_sym.information(); - c_binary->static_symbols[i]->is_exported = b_sym.is_exported(); - c_binary->static_symbols[i]->is_imported = b_sym.is_imported(); - } - c_binary->static_symbols[static_symb.size()] = nullptr; - -} - - - -void destroy_dynamic_symbols(Elf_Binary_t* c_binary) { - Elf_Symbol_t **dynamic_symbols = c_binary->dynamic_symbols; - for (size_t idx = 0; dynamic_symbols[idx] != nullptr; ++idx) { - free(dynamic_symbols[idx]); - } - free(c_binary->dynamic_symbols); -} - - -void destroy_static_symbols(Elf_Binary_t* c_binary) { - Elf_Symbol_t **static_symbols = c_binary->static_symbols; - for (size_t idx = 0; static_symbols[idx] != nullptr; ++idx) { - free(static_symbols[idx]); - } - free(c_binary->static_symbols); -} - -} -} - - diff --git a/vendor/lief/api/c/ELF/Symbol.hpp b/vendor/lief/api/c/ELF/Symbol.hpp deleted file mode 100644 index eb34f4c..0000000 --- a/vendor/lief/api/c/ELF/Symbol.hpp +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ELF_SYMBOL_CPP_C_API_ -#define LIEF_ELF_SYMBOL_CPP_C_API_ - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Binary.hpp" - -#include "LIEF/ELF/Symbol.h" -#include "LIEF/ELF/Symbol.hpp" - -namespace LIEF { -namespace ELF { - -void init_c_dynamic_symbols(Elf_Binary_t* c_binary, Binary* binary); -void init_c_static_symbols(Elf_Binary_t* c_binary, Binary* binary); - -void destroy_dynamic_symbols(Elf_Binary_t* c_binary); -void destroy_static_symbols(Elf_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/ELF/utils.cpp b/vendor/lief/api/c/ELF/utils.cpp deleted file mode 100644 index df0d586..0000000 --- a/vendor/lief/api/c/ELF/utils.cpp +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/ELF/utils.hpp" -#include "LIEF/ELF/utils.h" - -bool is_elf(const char* file) { - return LIEF::ELF::is_elf(file); -} - diff --git a/vendor/lief/api/c/MachO/Binary.cpp b/vendor/lief/api/c/MachO/Binary.cpp deleted file mode 100644 index 0035a78..0000000 --- a/vendor/lief/api/c/MachO/Binary.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/MachO/Binary.h" - -#include "LIEF/MachO/Binary.hpp" - -#include "Binary.hpp" -#include "Section.hpp" -#include "Header.hpp" -#include "Symbol.hpp" -#include "Segment.hpp" -#include "LoadCommand.hpp" - - -using namespace LIEF::MachO; - -namespace LIEF { -namespace MachO { -void init_c_binary(Macho_Binary_t* c_binary, Binary* binary) { - - c_binary->handler = reinterpret_cast(binary); - c_binary->name = binary->name().c_str(); - c_binary->imagebase = binary->imagebase(); - init_c_header(c_binary, binary); - init_c_commands(c_binary, binary); - init_c_symbols(c_binary, binary); - init_c_sections(c_binary, binary); - init_c_segments(c_binary, binary); -} -} -} - -void macho_binaries_destroy(Macho_Binary_t** binaries) { - for (size_t i = 0; binaries[i] != nullptr; ++i) { - destroy_sections(binaries[i]); - destroy_commands(binaries[i]); - destroy_symbols(binaries[i]); - destroy_segments(binaries[i]); - - delete reinterpret_cast(binaries[i]->handler); - free(binaries[i]); - } - free(binaries); - -} diff --git a/vendor/lief/api/c/MachO/Binary.hpp b/vendor/lief/api/c/MachO/Binary.hpp deleted file mode 100644 index ab7c16d..0000000 --- a/vendor/lief/api/c/MachO/Binary.hpp +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_BINARY_CPP_C_API_ -#define LIEF_MACHO_BINARY_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_binary(Macho_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/MachO/CMakeLists.txt b/vendor/lief/api/c/MachO/CMakeLists.txt deleted file mode 100644 index 24bedde..0000000 --- a/vendor/lief/api/c/MachO/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -include_directories( - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF" - "${CMAKE_CURRENT_SOURCE_DIR}/include" -) - -set(LIEF_API_C_MACHO_SRC - "${CMAKE_CURRENT_LIST_DIR}/EnumToString.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Parser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/LoadCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Segment.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Symbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Header.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Binary.cpp" -) - - -set(LIEF_API_C_MACHO_INCLUDE_FILES_CPP - "${CMAKE_CURRENT_LIST_DIR}/Header.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Binary.hpp" - "${CMAKE_CURRENT_LIST_DIR}/LoadCommand.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Segment.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Symbol.hpp" -) - - -set(LIEF_API_C_MACHO_INCLUDE_FILES_C - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/enums.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/Binary.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/EnumToString.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/Header.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/LoadCommand.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/Section.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/Segment.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/MachO/Symbol.h" -) - - -set(LIEF_C_MACHO_INC "${LIEF_API_C_MACHO_INCLUDE_FILES_C}" "${LIEF_API_C_MACHO_INCLUDE_FILES_CPP}") - -source_group("Source Files\\C API\\MachO" FILES ${LIEF_API_C_MACHO_SRC}) -source_group("Header Files\\C API\\MachO" FILES ${LIEF_C_MACHO_INC}) - -target_sources(LIB_LIEF PRIVATE "${LIEF_API_C_MACHO_SRC}" ${LIEF_C_MACHO_INC}) diff --git a/vendor/lief/api/c/MachO/EnumToString.cpp b/vendor/lief/api/c/MachO/EnumToString.cpp deleted file mode 100644 index d8ab3a8..0000000 --- a/vendor/lief/api/c/MachO/EnumToString.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/MachO/EnumToString.h" -#include "LIEF/MachO/EnumToString.hpp" - -#include "LIEF/MachO/enums.hpp" -#include "LIEF/MachO/enums.h" - - -extern "C" -{ - -const char* LOAD_COMMAND_TYPES_to_string(enum LIEF_MACHO_LOAD_COMMAND_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* MACHO_TYPES_to_string(enum LIEF_MACHO_MACHO_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* FILE_TYPES_to_string(enum LIEF_MACHO_FILE_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* CPU_TYPES_to_string(enum LIEF_MACHO_CPU_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* HEADER_FLAGS_to_string(enum LIEF_MACHO_HEADER_FLAGS e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* MACHO_SECTION_TYPES_to_string(enum LIEF_MACHO_MACHO_SECTION_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* MACHO_SYMBOL_TYPES_to_string(enum LIEF_MACHO_MACHO_SYMBOL_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* N_LIST_TYPES_to_string(enum LIEF_MACHO_N_LIST_TYPES e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - -const char* SYMBOL_DESCRIPTIONS_to_string(enum LIEF_MACHO_SYMBOL_DESCRIPTIONS e) { - return LIEF::MachO::to_string(static_cast(e)); -} - - - - - - - -} diff --git a/vendor/lief/api/c/MachO/Header.cpp b/vendor/lief/api/c/MachO/Header.cpp deleted file mode 100644 index 82a33b7..0000000 --- a/vendor/lief/api/c/MachO/Header.cpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Header.hpp" - -namespace LIEF { -namespace MachO { -void init_c_header(Macho_Binary_t* c_binary, Binary* binary) { - Header& header = binary->header(); - c_binary->header.magic = static_cast(header.magic()); - c_binary->header.cpu_type = static_cast(header.cpu_type()); - c_binary->header.cpu_subtype = header.cpu_subtype(); - c_binary->header.file_type = static_cast(header.file_type()); - c_binary->header.nb_cmds = header.nb_cmds(); - c_binary->header.sizeof_cmds = header.sizeof_cmds(); - c_binary->header.flags = header.flags(); - c_binary->header.reserved = header.reserved(); -} - -} -} diff --git a/vendor/lief/api/c/MachO/Header.hpp b/vendor/lief/api/c/MachO/Header.hpp deleted file mode 100644 index 274a7d3..0000000 --- a/vendor/lief/api/c/MachO/Header.hpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_HEADER_CPP_C_API_ -#define LIEF_MACHO_HEADER_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -#include "LIEF/MachO/Header.h" -#include "LIEF/MachO/Header.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_header(Macho_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/MachO/LoadCommand.cpp b/vendor/lief/api/c/MachO/LoadCommand.cpp deleted file mode 100644 index b284bb9..0000000 --- a/vendor/lief/api/c/MachO/LoadCommand.cpp +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LoadCommand.hpp" - -namespace LIEF { -namespace MachO { -void init_c_commands(Macho_Binary_t* c_binary, Binary* binary) { - Binary::it_commands commands = binary->commands(); - - c_binary->commands = static_cast( - malloc((commands.size() + 1) * sizeof(Macho_Command_t**))); - - for (size_t i = 0; i < commands.size(); ++i) { - LoadCommand& cmd = commands[i]; - - c_binary->commands[i] = static_cast(malloc(sizeof(Macho_Command_t))); - const std::vector& cmd_content = cmd.data(); - auto* content = static_cast(malloc(cmd_content.size() * sizeof(uint8_t))); - std::copy( - std::begin(cmd_content), - std::end(cmd_content), - content); - - c_binary->commands[i]->command = static_cast(cmd.command()); - c_binary->commands[i]->size = cmd.size(); - c_binary->commands[i]->data = content; - c_binary->commands[i]->offset = cmd.command_offset(); - } - - c_binary->commands[commands.size()] = nullptr; - -} - - - -void destroy_commands(Macho_Binary_t* c_binary) { - Macho_Command_t **commands = c_binary->commands; - for (size_t idx = 0; commands[idx] != nullptr; ++idx) { - free(commands[idx]->data); - free(commands[idx]); - } - free(c_binary->commands); - -} - -} -} - - diff --git a/vendor/lief/api/c/MachO/LoadCommand.hpp b/vendor/lief/api/c/MachO/LoadCommand.hpp deleted file mode 100644 index 94cf63c..0000000 --- a/vendor/lief/api/c/MachO/LoadCommand.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_LOAD_COMMAND_CPP_C_API_ -#define LIEF_MACHO_LOAD_COMMAND_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -#include "LIEF/MachO/LoadCommand.h" -#include "LIEF/MachO/LoadCommand.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_commands(Macho_Binary_t* c_binary, Binary* binary); -void destroy_commands(Macho_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/MachO/Parser.cpp b/vendor/lief/api/c/MachO/Parser.cpp deleted file mode 100644 index 8f9efbf..0000000 --- a/vendor/lief/api/c/MachO/Parser.cpp +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Parser.hpp" -#include "LIEF/MachO/FatBinary.hpp" - -#include "Binary.hpp" - -using namespace LIEF::MachO; - -Macho_Binary_t** macho_parse(const char *file) { - FatBinary* fat = Parser::parse(file).release(); - if (fat == nullptr) { - return nullptr; - } - - size_t nb_bin = fat->size(); - - auto** c_macho_binaries = static_cast( - malloc((fat->size() + 1) * sizeof(Macho_Binary_t**))); - - for (size_t i = 0; i < nb_bin; ++i) { - Binary* binary = fat->at(i); - if (binary != nullptr) { - c_macho_binaries[i] = static_cast(malloc(sizeof(Macho_Binary_t))); - init_c_binary(c_macho_binaries[i], binary); - } - } - - fat->release_all_binaries(); - - c_macho_binaries[nb_bin] = nullptr; - delete fat; - - return c_macho_binaries; -} - diff --git a/vendor/lief/api/c/MachO/Section.cpp b/vendor/lief/api/c/MachO/Section.cpp deleted file mode 100644 index d88af35..0000000 --- a/vendor/lief/api/c/MachO/Section.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Section.hpp" - -namespace LIEF { -namespace MachO { -void init_c_sections(Macho_Binary_t* c_binary, Binary* binary) { - Binary::it_sections sections = binary->sections(); - - c_binary->sections = static_cast( - malloc((sections.size() + 1) * sizeof(Macho_Section_t**))); - - for (size_t i = 0; i < sections.size(); ++i) { - const Section& section = sections[i]; - - c_binary->sections[i] = static_cast(malloc(sizeof(Macho_Section_t))); - span section_content = section.content(); - auto* content = static_cast(malloc(section_content.size() * sizeof(uint8_t))); - std::copy(std::begin(section_content), std::end(section_content), - content); - - c_binary->sections[i]->name = section.fullname().c_str(); - c_binary->sections[i]->alignment = section.alignment(); - c_binary->sections[i]->relocation_offset = section.relocation_offset(); - c_binary->sections[i]->numberof_relocations = section.numberof_relocations(); - c_binary->sections[i]->flags = section.flags(); - c_binary->sections[i]->type = static_cast(section.type()); - c_binary->sections[i]->reserved1 = section.reserved1(); - c_binary->sections[i]->reserved2 = section.reserved2(); - c_binary->sections[i]->reserved3 = section.reserved3(); - c_binary->sections[i]->virtual_address = section.virtual_address(); - c_binary->sections[i]->offset = section.offset(); - c_binary->sections[i]->size = section_content.size(); - c_binary->sections[i]->content = content; - c_binary->sections[i]->entropy = section.entropy(); - } - - c_binary->sections[sections.size()] = nullptr; - -} - - - -void destroy_sections(Macho_Binary_t* c_binary) { - Macho_Section_t **sections = c_binary->sections; - for (size_t idx = 0; sections[idx] != nullptr; ++idx) { - free(sections[idx]->content); - free(sections[idx]); - } - free(c_binary->sections); - -} - -} -} - - diff --git a/vendor/lief/api/c/MachO/Section.hpp b/vendor/lief/api/c/MachO/Section.hpp deleted file mode 100644 index f91f5cb..0000000 --- a/vendor/lief/api/c/MachO/Section.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_SECTION_CPP_C_API_ -#define LIEF_MACHO_SECTION_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -#include "LIEF/MachO/Section.h" -#include "LIEF/MachO/Section.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_sections(Macho_Binary_t* c_binary, Binary* binary); -void destroy_sections(Macho_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/MachO/Segment.cpp b/vendor/lief/api/c/MachO/Segment.cpp deleted file mode 100644 index 24cbea2..0000000 --- a/vendor/lief/api/c/MachO/Segment.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Segment.hpp" - -namespace LIEF { -namespace MachO { -void init_c_segments(Macho_Binary_t* c_binary, Binary* binary) { - Binary::it_segments segments = binary->segments(); - - c_binary->segments = static_cast( - malloc((segments.size() + 1) * sizeof(Macho_Segment_t**))); - - for (size_t i = 0; i < segments.size(); ++i) { - SegmentCommand& segment = segments[i]; - - c_binary->segments[i] = static_cast(malloc(sizeof(Macho_Segment_t))); - span segment_content = segment.content(); - auto* content = static_cast(malloc(segment_content.size() * sizeof(uint8_t))); - std::copy( - std::begin(segment_content), - std::end(segment_content), - content); - - c_binary->segments[i]->name = segment.name().c_str(); - c_binary->segments[i]->virtual_address = segment.virtual_address(); - c_binary->segments[i]->virtual_size = segment.virtual_size(); - c_binary->segments[i]->file_size = segment.file_size(); - c_binary->segments[i]->file_offset = segment.file_offset(); - c_binary->segments[i]->max_protection = segment.max_protection(); - c_binary->segments[i]->init_protection = segment.init_protection(); - c_binary->segments[i]->numberof_sections = segment.numberof_sections(); - c_binary->segments[i]->flags = segment.flags(); - c_binary->segments[i]->content = content; - c_binary->segments[i]->size = segment_content.size(); - c_binary->segments[i]->sections = nullptr; //TODO - } - - c_binary->segments[segments.size()] = nullptr; - -} - - - -void destroy_segments(Macho_Binary_t* c_binary) { - Macho_Segment_t **segments = c_binary->segments; - for (size_t idx = 0; segments[idx] != nullptr; ++idx) { - free(segments[idx]->content); - free(segments[idx]); - } - free(c_binary->segments); - -} - -} -} - - diff --git a/vendor/lief/api/c/MachO/Segment.hpp b/vendor/lief/api/c/MachO/Segment.hpp deleted file mode 100644 index 4da6258..0000000 --- a/vendor/lief/api/c/MachO/Segment.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_SEGMENT_CPP_C_API_ -#define LIEF_MACHO_SEGMENT_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -#include "LIEF/MachO/Segment.h" -#include "LIEF/MachO/SegmentCommand.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_segments(Macho_Binary_t* c_binary, Binary* binary); -void destroy_segments(Macho_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/MachO/Symbol.cpp b/vendor/lief/api/c/MachO/Symbol.cpp deleted file mode 100644 index 9d2af10..0000000 --- a/vendor/lief/api/c/MachO/Symbol.cpp +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Symbol.hpp" - -namespace LIEF { -namespace MachO { -void init_c_symbols(Macho_Binary_t* c_binary, Binary* binary) { - Binary::it_symbols symbols = binary->symbols(); - - c_binary->symbols = static_cast( - malloc((symbols.size() + 1) * sizeof(Macho_Symbol_t**))); - - for (size_t i = 0; i < symbols.size(); ++i) { - const Symbol& symbol = symbols[i]; - - c_binary->symbols[i] = static_cast(malloc(sizeof(Macho_Symbol_t))); - - c_binary->symbols[i]->name = symbol.name().c_str(); - c_binary->symbols[i]->type = symbol.type(); - c_binary->symbols[i]->numberof_sections = symbol.numberof_sections(); - c_binary->symbols[i]->description = symbol.description(); - c_binary->symbols[i]->value = symbol.value(); - } - - c_binary->symbols[symbols.size()] = nullptr; - -} - - - -void destroy_symbols(Macho_Binary_t* c_binary) { - Macho_Symbol_t **symbols = c_binary->symbols; - for (size_t idx = 0; symbols[idx] != nullptr; ++idx) { - free(symbols[idx]); - } - free(c_binary->symbols); - -} - -} -} - - diff --git a/vendor/lief/api/c/MachO/Symbol.hpp b/vendor/lief/api/c/MachO/Symbol.hpp deleted file mode 100644 index 0eaf404..0000000 --- a/vendor/lief/api/c/MachO/Symbol.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_MACHO_SYMBOL_CPP_C_API_ -#define LIEF_MACHO_SYMBOL_CPP_C_API_ - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Binary.hpp" - -#include "LIEF/MachO/Symbol.h" -#include "LIEF/MachO/Symbol.hpp" - -namespace LIEF { -namespace MachO { - -void init_c_symbols(Macho_Binary_t* c_binary, Binary* binary); -void destroy_symbols(Macho_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/Binary.cpp b/vendor/lief/api/c/PE/Binary.cpp deleted file mode 100644 index 3ece8ff..0000000 --- a/vendor/lief/api/c/PE/Binary.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "LIEF/PE/Binary.h" - -#include "LIEF/PE/Parser.hpp" -#include "LIEF/PE/Binary.hpp" - -#include "Binary.hpp" -#include "DosHeader.hpp" -#include "Header.hpp" -#include "OptionalHeader.hpp" -#include "Section.hpp" -#include "DataDirectory.hpp" -#include "Import.hpp" - -using namespace LIEF::PE; - -namespace LIEF { -namespace PE { - -void init_c_binary(Pe_Binary_t* c_binary, Binary* binary) { - c_binary->name = binary->name().c_str(); - c_binary->handler = reinterpret_cast(binary); - - init_c_dos_header(c_binary, binary); - init_c_header(c_binary, binary); - init_c_optional_header(c_binary, binary); - init_c_sections(c_binary, binary); - init_c_data_directories(c_binary, binary); - init_c_imports(c_binary, binary); - -} - -} -} - -Pe_Binary_t* pe_parse(const char *file) { - Binary* binary = Parser::parse(file).release(); - auto* c_binary = static_cast(malloc(sizeof(Pe_Binary_t))); - std::memset(c_binary, 0, sizeof(Pe_Binary_t)); - init_c_binary(c_binary, binary); - - return c_binary; -} - -void pe_binary_destroy(Pe_Binary_t* binary) { - destroy_sections(binary); - destroy_data_directories(binary); - destroy_imports(binary); - delete reinterpret_cast(binary->handler); - free(binary); -} diff --git a/vendor/lief/api/c/PE/Binary.hpp b/vendor/lief/api/c/PE/Binary.hpp deleted file mode 100644 index 3369af7..0000000 --- a/vendor/lief/api/c/PE/Binary.hpp +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_BINARY_CPP_C_API_ -#define LIEF_PE_BINARY_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -namespace LIEF { -namespace PE { - -void init_c_binary(Pe_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/CMakeLists.txt b/vendor/lief/api/c/PE/CMakeLists.txt deleted file mode 100644 index 14e478e..0000000 --- a/vendor/lief/api/c/PE/CMakeLists.txt +++ /dev/null @@ -1,48 +0,0 @@ -include_directories( - "${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF" - "${CMAKE_CURRENT_SOURCE_DIR}/include" -) -set(LIEF_API_C_PE_SRC - "${CMAKE_CURRENT_LIST_DIR}/Binary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/DosHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Header.cpp" - "${CMAKE_CURRENT_LIST_DIR}/OptionalHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.cpp" - "${CMAKE_CURRENT_LIST_DIR}/DataDirectory.cpp" - "${CMAKE_CURRENT_LIST_DIR}/EnumToString.cpp" - "${CMAKE_CURRENT_LIST_DIR}/Import.cpp" - "${CMAKE_CURRENT_LIST_DIR}/ImportEntry.cpp" -) - - -set(LIEF_API_C_PE_INCLUDE_FILES_CPP - "${CMAKE_CURRENT_LIST_DIR}/Binary.hpp" - "${CMAKE_CURRENT_LIST_DIR}/DataDirectory.hpp" - "${CMAKE_CURRENT_LIST_DIR}/DosHeader.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Header.hpp" - "${CMAKE_CURRENT_LIST_DIR}/OptionalHeader.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Section.hpp" - "${CMAKE_CURRENT_LIST_DIR}/Import.hpp" - "${CMAKE_CURRENT_LIST_DIR}/ImportEntry.hpp" -) - -set(LIEF_API_C_PE_INCLUDE_FILES_C - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/enums.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/Binary.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/DataDirectory.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/DosHeader.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/EnumToString.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/Header.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/OptionalHeader.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/Section.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/Import.h" - "${CMAKE_CURRENT_SOURCE_DIR}/api/c/include/LIEF/PE/ImportEntry.h" -) - - -set(LIEF_C_PE_INC "${LIEF_API_C_PE_INCLUDE_FILES_C}" "${LIEF_API_C_PE_INCLUDE_FILES_CPP}") - -source_group("Source Files\\C API\\PE" FILES ${LIEF_API_C_PE_SRC}) -source_group("Header Files\\C API\\PE" FILES ${LIEF_C_PE_INC}) - -target_sources(LIB_LIEF PRIVATE "${LIEF_API_C_PE_SRC}" "${LIEF_C_PE_INC}") diff --git a/vendor/lief/api/c/PE/DataDirectory.cpp b/vendor/lief/api/c/PE/DataDirectory.cpp deleted file mode 100644 index b8dd912..0000000 --- a/vendor/lief/api/c/PE/DataDirectory.cpp +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "DataDirectory.hpp" - -namespace LIEF { -namespace PE { -void init_c_data_directories(Pe_Binary_t* c_binary, Binary* binary) { - - Binary::it_data_directories data_directories = binary->data_directories(); - - c_binary->data_directories = static_cast( - malloc((data_directories.size() + 1) * sizeof(Pe_DataDirectory_t**))); - - for (size_t i = 0; i < data_directories.size(); ++i) { - - c_binary->data_directories[i] = static_cast(malloc(sizeof(Pe_DataDirectory_t))); - c_binary->data_directories[i]->rva = data_directories[i].RVA(); - c_binary->data_directories[i]->size = data_directories[i].size(); - } - c_binary->data_directories[data_directories.size()] = nullptr; - - - -} - - - -void destroy_data_directories(Pe_Binary_t* c_binary) { - - Pe_DataDirectory_t **data_directories = c_binary->data_directories; - for (size_t idx = 0; data_directories[idx] != nullptr; ++idx) { - free(data_directories[idx]); - } - free(c_binary->data_directories); - -} - -} -} - - diff --git a/vendor/lief/api/c/PE/DataDirectory.hpp b/vendor/lief/api/c/PE/DataDirectory.hpp deleted file mode 100644 index cff19ec..0000000 --- a/vendor/lief/api/c/PE/DataDirectory.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_DATA_DIRECTORY_CPP_C_API_ -#define LIEF_PE_DATA_DIRECTORY_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/DataDirectory.h" -#include "LIEF/PE/DataDirectory.hpp" - -namespace LIEF { -namespace PE { - -void init_c_data_directories(Pe_Binary_t* c_binary, Binary* binary); -void destroy_data_directories(Pe_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/DosHeader.cpp b/vendor/lief/api/c/PE/DosHeader.cpp deleted file mode 100644 index 2fcd2cc..0000000 --- a/vendor/lief/api/c/PE/DosHeader.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "DosHeader.hpp" - -namespace LIEF { -namespace PE { -void init_c_dos_header(Pe_Binary_t* c_binary, Binary* binary) { - const DosHeader& dos_header = binary->dos_header(); - c_binary->dos_header.magic = dos_header.magic(); - c_binary->dos_header.used_bytes_in_the_last_page = dos_header.used_bytes_in_the_last_page(); - c_binary->dos_header.file_size_in_pages = dos_header.file_size_in_pages(); - c_binary->dos_header.numberof_relocation = dos_header.numberof_relocation(); - c_binary->dos_header.header_size_in_paragraphs = dos_header.header_size_in_paragraphs(); - c_binary->dos_header.minimum_extra_paragraphs = dos_header.minimum_extra_paragraphs(); - c_binary->dos_header.maximum_extra_paragraphs = dos_header.maximum_extra_paragraphs(); - c_binary->dos_header.initial_relative_ss = dos_header.initial_relative_ss(); - c_binary->dos_header.initial_sp = dos_header.initial_sp(); - c_binary->dos_header.checksum = dos_header.checksum(); - c_binary->dos_header.initial_ip = dos_header.initial_ip(); - c_binary->dos_header.initial_relative_cs = dos_header.initial_relative_cs(); - c_binary->dos_header.addressof_relocation_table = dos_header.addressof_relocation_table(); - c_binary->dos_header.overlay_number = dos_header.overlay_number(); - c_binary->dos_header.oem_id = dos_header.oem_id(); - c_binary->dos_header.oem_info = dos_header.oem_info(); - c_binary->dos_header.addressof_new_exeheader = dos_header.addressof_new_exeheader(); - - const DosHeader::reserved_t& reserved = dos_header.reserved(); - std::copy( - std::begin(reserved), - std::end(reserved), - c_binary->dos_header.reserved); - - - const DosHeader::reserved2_t& reserved2 = dos_header.reserved2(); - std::copy( - std::begin(reserved2), - std::end(reserved2), - c_binary->dos_header.reserved2); -} - -} -} diff --git a/vendor/lief/api/c/PE/DosHeader.hpp b/vendor/lief/api/c/PE/DosHeader.hpp deleted file mode 100644 index d5344c9..0000000 --- a/vendor/lief/api/c/PE/DosHeader.hpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_DOS_HEADER_CPP_C_API_ -#define LIEF_PE_DOS_HEADER_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/DosHeader.h" -#include "LIEF/PE/DosHeader.hpp" - -namespace LIEF { -namespace PE { - -void init_c_dos_header(Pe_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/EnumToString.cpp b/vendor/lief/api/c/PE/EnumToString.cpp deleted file mode 100644 index 39a36c8..0000000 --- a/vendor/lief/api/c/PE/EnumToString.cpp +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/PE/EnumToString.h" -#include "LIEF/PE/EnumToString.hpp" - -#include "LIEF/PE/enums.hpp" -#include "LIEF/PE/enums.h" - - -extern "C" -{ - -const char* PE_TYPES_to_string(enum LIEF_PE_PE_TYPES e) { - return LIEF::PE::to_string(static_cast(e)); -} - - -const char* MACHINE_TYPES_to_string(enum LIEF_PE_MACHINE_TYPES e) { - return LIEF::PE::to_string(static_cast(e)); -} - - -const char* SUBSYSTEM_to_string(enum LIEF_PE_SUBSYSTEM e) { - return LIEF::PE::to_string(static_cast(e)); -} - -} diff --git a/vendor/lief/api/c/PE/Header.cpp b/vendor/lief/api/c/PE/Header.cpp deleted file mode 100644 index 1953b17..0000000 --- a/vendor/lief/api/c/PE/Header.cpp +++ /dev/null @@ -1,42 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Header.hpp" - -namespace LIEF { -namespace PE { - -void init_c_header(Pe_Binary_t* c_binary, Binary* binary) { - - const Header& header = binary->header(); - - const Header::signature_t& signature = header.signature(); - - c_binary->header.machine = static_cast(header.machine()); - c_binary->header.numberof_sections = header.numberof_sections(); - c_binary->header.time_date_stamp = header.time_date_stamp(); - c_binary->header.pointerto_symbol_table = header.pointerto_symbol_table(); - c_binary->header.numberof_symbols = header.numberof_symbols(); - c_binary->header.sizeof_optional_header = header.sizeof_optional_header(); - c_binary->header.characteristics = static_cast(header.characteristics()); - - std::copy( - std::begin(signature), - std::end(signature), - c_binary->header.signature); -} - -} -} diff --git a/vendor/lief/api/c/PE/Header.hpp b/vendor/lief/api/c/PE/Header.hpp deleted file mode 100644 index a3ebba7..0000000 --- a/vendor/lief/api/c/PE/Header.hpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_HEADER_CPP_C_API_ -#define LIEF_PE_HEADER_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/Header.h" -#include "LIEF/PE/Header.hpp" - -namespace LIEF { -namespace PE { - -void init_c_header(Pe_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/Import.cpp b/vendor/lief/api/c/PE/Import.cpp deleted file mode 100644 index 3f491d9..0000000 --- a/vendor/lief/api/c/PE/Import.cpp +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Import.hpp" -#include "ImportEntry.hpp" - -namespace LIEF { -namespace PE { - -void init_c_imports(Pe_Binary_t* c_binary, Binary* binary) { - - if (!binary->has_imports()) { - c_binary->imports = nullptr; - } - - Binary::it_imports imports = binary->imports(); - - c_binary->imports = static_cast( - malloc((imports.size() + 1) * sizeof(Pe_Import_t**))); - - for (size_t i = 0; i < imports.size(); ++i) { - Import& imp = imports[i]; - c_binary->imports[i] = static_cast(malloc(sizeof(Pe_Import_t))); - - c_binary->imports[i]->name = imp.name().c_str(); - c_binary->imports[i]->forwarder_chain = imp.forwarder_chain(); - c_binary->imports[i]->timedatestamp = imp.forwarder_chain(); - c_binary->imports[i]->import_address_table_rva = imp.import_address_table_rva(); - c_binary->imports[i]->import_lookup_table_rva = imp.import_lookup_table_rva(); - c_binary->imports[i]->entries = nullptr; - init_c_import_entries(c_binary->imports[i], imp); - } - - c_binary->imports[imports.size()] = nullptr; -} - - -void destroy_imports(Pe_Binary_t* c_binary) { - if (c_binary->imports == nullptr) { - return; - } - - Pe_Import_t **imports = c_binary->imports; - for (size_t idx = 0; imports[idx] != nullptr; ++idx) { - destroy_import_entries(imports[idx]); - free(imports[idx]); - } - free(c_binary->imports); - -} - -} -} diff --git a/vendor/lief/api/c/PE/Import.hpp b/vendor/lief/api/c/PE/Import.hpp deleted file mode 100644 index a56aafa..0000000 --- a/vendor/lief/api/c/PE/Import.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_IMPORT_CPP_C_API_ -#define LIEF_PE_IMPORT_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/Import.h" -#include "LIEF/PE/Import.hpp" - -namespace LIEF { -namespace PE { - -void init_c_imports(Pe_Binary_t* c_binary, Binary* binary); -void destroy_imports(Pe_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/ImportEntry.cpp b/vendor/lief/api/c/PE/ImportEntry.cpp deleted file mode 100644 index 3a00c48..0000000 --- a/vendor/lief/api/c/PE/ImportEntry.cpp +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "ImportEntry.hpp" - -namespace LIEF { -namespace PE { - -void init_c_import_entries(Pe_Import_t* c_import, Import& imp) { - - Import::it_entries entries = imp.entries(); - - c_import->entries = static_cast( - malloc((entries.size() + 1) * sizeof(Pe_ImportEntry_t**))); - - for (size_t i = 0; i < entries.size(); ++i) { - ImportEntry& import_entry = entries[i]; - c_import->entries[i] = static_cast(malloc(sizeof(Pe_ImportEntry_t))); - - c_import->entries[i]->is_ordinal = import_entry.is_ordinal(); - c_import->entries[i]->name = import_entry.is_ordinal() ? nullptr : import_entry.name().c_str(); - c_import->entries[i]->ordinal = import_entry.is_ordinal() ? import_entry.ordinal() : 0; - c_import->entries[i]->hint_name_rva = import_entry.hint_name_rva(); - c_import->entries[i]->hint = import_entry.hint(); - c_import->entries[i]->iat_value = import_entry.iat_value(); - c_import->entries[i]->data = import_entry.data(); - c_import->entries[i]->iat_address = import_entry.iat_address(); - } - - c_import->entries[entries.size()] = nullptr; - -} - - -void destroy_import_entries(Pe_Import_t* c_import) { - Pe_ImportEntry_t **entries = c_import->entries; - for (size_t idx = 0; entries[idx] != nullptr; ++idx) { - free(entries[idx]); - } - free(c_import->entries); - -} - -} -} diff --git a/vendor/lief/api/c/PE/ImportEntry.hpp b/vendor/lief/api/c/PE/ImportEntry.hpp deleted file mode 100644 index 067e968..0000000 --- a/vendor/lief/api/c/PE/ImportEntry.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_IMPORT_ENTRY_CPP_C_API_ -#define LIEF_PE_IMPORT_ENTRY_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/ImportEntry.h" -#include "LIEF/PE/ImportEntry.hpp" - -namespace LIEF { -namespace PE { - -void init_c_import_entries(Pe_Import_t* c_import, Import& imp); -void destroy_import_entries(Pe_Import_t* c_import); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/OptionalHeader.cpp b/vendor/lief/api/c/PE/OptionalHeader.cpp deleted file mode 100644 index 1648f41..0000000 --- a/vendor/lief/api/c/PE/OptionalHeader.cpp +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "OptionalHeader.hpp" - -namespace LIEF { -namespace PE { - -void init_c_optional_header(Pe_Binary_t* c_binary, Binary* binary) { - - const OptionalHeader& optional_header = binary->optional_header(); - c_binary->optional_header.magic = static_cast(optional_header.magic()); - c_binary->optional_header.major_linker_version = optional_header.major_linker_version(); - c_binary->optional_header.minor_linker_version = optional_header.minor_linker_version(); - c_binary->optional_header.sizeof_code = optional_header.sizeof_code(); - c_binary->optional_header.sizeof_initialized_data = optional_header.sizeof_initialized_data(); - c_binary->optional_header.sizeof_uninitialized_data = optional_header.sizeof_uninitialized_data(); - c_binary->optional_header.addressof_entrypoint = optional_header.addressof_entrypoint(); - c_binary->optional_header.baseof_code = optional_header.baseof_code(); - if (optional_header.magic() == PE_TYPE::PE32) { - c_binary->optional_header.baseof_data = optional_header.baseof_data(); - } else { - c_binary->optional_header.baseof_data = 0; - } - c_binary->optional_header.imagebase = optional_header.imagebase(); - c_binary->optional_header.section_alignment = optional_header.section_alignment(); - c_binary->optional_header.file_alignment = optional_header.file_alignment(); - c_binary->optional_header.major_operating_system_version = optional_header.major_operating_system_version(); - c_binary->optional_header.minor_operating_system_version = optional_header.minor_operating_system_version(); - c_binary->optional_header.major_image_version = optional_header.major_image_version(); - c_binary->optional_header.minor_image_version = optional_header.minor_image_version(); - c_binary->optional_header.major_subsystem_version = optional_header.major_subsystem_version(); - c_binary->optional_header.minor_subsystem_version = optional_header.minor_subsystem_version(); - c_binary->optional_header.win32_version_value = optional_header.win32_version_value(); - c_binary->optional_header.sizeof_image = optional_header.sizeof_image(); - c_binary->optional_header.sizeof_headers = optional_header.sizeof_headers(); - c_binary->optional_header.checksum = optional_header.checksum(); - c_binary->optional_header.subsystem = static_cast(optional_header.subsystem()); - c_binary->optional_header.dll_characteristics = optional_header.dll_characteristics(); - c_binary->optional_header.sizeof_stack_reserve = optional_header.sizeof_stack_reserve(); - c_binary->optional_header.sizeof_stack_commit = optional_header.sizeof_stack_commit(); - c_binary->optional_header.sizeof_heap_reserve = optional_header.sizeof_heap_reserve(); - c_binary->optional_header.sizeof_heap_commit = optional_header.sizeof_heap_commit(); - c_binary->optional_header.loader_flags = optional_header.loader_flags(); - c_binary->optional_header.numberof_rva_and_size = optional_header.numberof_rva_and_size(); -} - -} -} diff --git a/vendor/lief/api/c/PE/OptionalHeader.hpp b/vendor/lief/api/c/PE/OptionalHeader.hpp deleted file mode 100644 index cc5b107..0000000 --- a/vendor/lief/api/c/PE/OptionalHeader.hpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_OPTIONAL_HEADER_CPP_C_API_ -#define LIEF_PE_OPTIONAL_HEADER_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/OptionalHeader.h" -#include "LIEF/PE/OptionalHeader.hpp" - -namespace LIEF { -namespace PE { - -void init_c_optional_header(Pe_Binary_t* c_binary, Binary* binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/PE/Section.cpp b/vendor/lief/api/c/PE/Section.cpp deleted file mode 100644 index ede9817..0000000 --- a/vendor/lief/api/c/PE/Section.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "Section.hpp" - -namespace LIEF { -namespace PE { -void init_c_sections(Pe_Binary_t* c_binary, Binary* binary) { - - Binary::it_sections sections = binary->sections(); - - c_binary->sections = static_cast( - malloc((sections.size() + 1) * sizeof(Pe_Section_t**))); - - for (size_t i = 0; i < sections.size(); ++i) { - Section& b_section = sections[i]; - c_binary->sections[i] = static_cast(malloc(sizeof(Pe_Section_t))); - span section_content = b_section.content(); - uint8_t* content = nullptr; - - if (!section_content.empty()) { - content = static_cast(malloc(section_content.size() * sizeof(uint8_t))); - std::copy(std::begin(section_content), std::end(section_content), - content); - } - - c_binary->sections[i]->name = b_section.fullname().c_str(); - c_binary->sections[i]->virtual_address = b_section.virtual_address(); - c_binary->sections[i]->size = b_section.size(); - c_binary->sections[i]->offset = b_section.offset(); - c_binary->sections[i]->virtual_size = b_section.virtual_size(); - c_binary->sections[i]->pointerto_relocation = b_section.pointerto_relocation(); - c_binary->sections[i]->pointerto_line_numbers = b_section.pointerto_line_numbers(); - c_binary->sections[i]->characteristics = b_section.characteristics(); - c_binary->sections[i]->content = content; - c_binary->sections[i]->content_size = section_content.size(); - c_binary->sections[i]->entropy = b_section.entropy(); - } - c_binary->sections[sections.size()] = nullptr; - -} - - - -void destroy_sections(Pe_Binary_t* c_binary) { - - Pe_Section_t **sections = c_binary->sections; - for (size_t idx = 0; sections[idx] != nullptr; ++idx) { - free(sections[idx]->content); - free(sections[idx]); - } - free(c_binary->sections); - -} - -} -} - - diff --git a/vendor/lief/api/c/PE/Section.hpp b/vendor/lief/api/c/PE/Section.hpp deleted file mode 100644 index 8353912..0000000 --- a/vendor/lief/api/c/PE/Section.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_PE_SECTION_CPP_C_API_ -#define LIEF_PE_SECTION_CPP_C_API_ - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/Binary.hpp" - -#include "LIEF/PE/Section.h" -#include "LIEF/PE/Section.hpp" - -namespace LIEF { -namespace PE { - -void init_c_sections(Pe_Binary_t* c_binary, Binary* binary); -void destroy_sections(Pe_Binary_t* c_binary); - -} -} - -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF.h b/vendor/lief/api/c/include/LIEF/ELF.h deleted file mode 100644 index 940d59d..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_H_ -#define C_LIEF_ELF_H_ - -//! @defgroup elf_c_api ELF C API - -#include "LIEF/ELF/Binary.h" -#include "LIEF/ELF/Symbol.h" -#include "LIEF/ELF/Section.h" -#include "LIEF/ELF/Header.h" -#include "LIEF/ELF/DynamicEntry.h" -#include "LIEF/ELF/EnumToString.h" -#include "LIEF/ELF/utils.h" -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/Binary.h b/vendor/lief/api/c/include/LIEF/ELF/Binary.h deleted file mode 100644 index cc4578e..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/Binary.h +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_BINARY_H_ -#define C_LIEF_ELF_BINARY_H_ - -/** @defgroup elf_binary_c_api Binary - * @ingroup elf_c_api - * @addtogroup elf_binary_c_api - * @brief Binary C API - * - * @{ - */ - -#include - -#include "LIEF/visibility.h" - -#include "LIEF/ELF/enums.h" - -#include "LIEF/ELF/Section.h" -#include "LIEF/ELF/Segment.h" -#include "LIEF/ELF/Header.h" -#include "LIEF/ELF/DynamicEntry.h" -#include "LIEF/ELF/Symbol.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief LIEF::ELF::Binary C Handler */ -struct Elf_Binary_t { - void* handler; - const char* name; - const char* interpreter; - enum LIEF_ELF_ELF_CLASS type; - Elf_Header_t header; - Elf_Section_t **sections; - Elf_Segment_t **segments; - Elf_DynamicEntry_t **dynamic_entries; - Elf_Symbol_t **dynamic_symbols; - Elf_Symbol_t **static_symbols; -}; - -typedef struct Elf_Binary_t Elf_Binary_t; - -/** @brief Wrapper for LIEF::ELF::Parser::parse */ -LIEF_API Elf_Binary_t* elf_parse(const char *file); - -LIEF_API void elf_binary_destroy(Elf_Binary_t* binary); - -/* ELF::Binary methods - * ================== - */ - -/** @brief Update LIEF::ELF::Header object */ -LIEF_API int elf_binary_save_header(Elf_Binary_t* binary); - - - -#ifdef __cplusplus -} -#endif - - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/DynamicEntry.h b/vendor/lief/api/c/include/LIEF/ELF/DynamicEntry.h deleted file mode 100644 index a4f05b2..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/DynamicEntry.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_DYNAMIC_ENTRY_H_ -#define C_LIEF_ELF_DYNAMIC_ENTRY_H_ - -#include - -#include "LIEF/ELF/enums.h" - -/** @defgroup elf_dynamic_entry_c_api Dynamic Entry - * @ingroup elf_c_api - * @addtogroup elf_dynamic_entry_c_api - * @brief Dynamic Entry C API - * - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -struct Elf_DynamicEntry_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; -}; - -struct Elf_DynamicEntry_Library_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - const char* name; -}; - -struct Elf_DynamicEntry_SharedObject_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - const char* name; -}; - -struct Elf_DynamicEntry_Array_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - uint64_t* array; -}; - -struct Elf_DynamicEntry_Rpath_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - const char* rpath; -}; - -struct Elf_DynamicEntry_RunPath_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - const char* runpath; -}; - - -struct Elf_DynamicEntry_Flags_t { - enum LIEF_ELF_DYNAMIC_TAGS tag; - uint64_t value; - enum LIEF_ELF_DYNAMIC_FLAGS *flags; - enum LIEF_ELF_DYNAMIC_FLAGS_1 *flags_1; -}; - -typedef struct Elf_DynamicEntry_t Elf_DynamicEntry_t; -typedef struct Elf_DynamicEntry_Library_t Elf_DynamicEntry_Library_t; -typedef struct Elf_DynamicEntry_SharedObject_t Elf_DynamicEntry_SharedObject_t; -typedef struct Elf_DynamicEntry_Array_t Elf_DynamicEntry_Array_t; -typedef struct Elf_DynamicEntry_Rpath_t Elf_DynamicEntry_Rpath_t; -typedef struct Elf_DynamicEntry_RunPath_t Elf_DynamicEntry_RunPath_t; -typedef struct Elf_DynamicEntry_Flags_t Elf_DynamicEntry_Flags_t; - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/EnumToString.h b/vendor/lief/api/c/include/LIEF/ELF/EnumToString.h deleted file mode 100644 index cfd388e..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/EnumToString.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_ENUM_TO_STRING_H_ -#define C_LIEF_ELF_ENUM_TO_STRING_H_ - -#include "LIEF/visibility.h" - -#include "LIEF/ELF/enums.h" - -#ifdef __cplusplus -extern "C" { -#endif - -LIEF_API const char* SYMBOL_BINDINGS_to_string(enum LIEF_ELF_SYMBOL_BINDINGS e); -LIEF_API const char* E_TYPE_to_string(enum LIEF_ELF_E_TYPE e); -LIEF_API const char* VERSION_to_string(enum LIEF_ELF_VERSION e); -LIEF_API const char* ARCH_to_string(enum LIEF_ELF_ARCH e); -LIEF_API const char* SEGMENT_TYPES_to_string(enum LIEF_ELF_SEGMENT_TYPES e); -LIEF_API const char* DYNAMIC_TAGS_to_string(enum LIEF_ELF_DYNAMIC_TAGS e); -LIEF_API const char* ELF_SECTION_TYPES_to_string(enum LIEF_ELF_ELF_SECTION_TYPES e); -LIEF_API const char* ELF_SECTION_FLAGS_to_string(enum LIEF_ELF_ELF_SECTION_FLAGS e); -LIEF_API const char* ELF_SYMBOL_TYPES_to_string(enum LIEF_ELF_ELF_SYMBOL_TYPES e); -LIEF_API const char* ELF_CLASS_to_string(enum LIEF_ELF_ELF_CLASS e); -LIEF_API const char* ELF_DATA_to_string(enum LIEF_ELF_ELF_DATA e); -LIEF_API const char* OS_ABI_to_string(enum LIEF_ELF_OS_ABI e); -LIEF_API const char* DYNAMIC_FLAGS_to_string(enum LIEF_ELF_DYNAMIC_FLAGS e); -LIEF_API const char* DYNAMIC_FLAGS_1_to_string(enum LIEF_ELF_DYNAMIC_FLAGS_1 e); - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/Header.h b/vendor/lief/api/c/include/LIEF/ELF/Header.h deleted file mode 100644 index 14a3e22..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/Header.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_HEADER_H_ -#define C_LIEF_ELF_HEADER_H_ -#include - -#include "LIEF/ELF/enums.h" -/** @defgroup elf_header_c_api Header - * @ingroup elf_c_api - * @addtogroup elf_header_c_api - * @brief Header C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Elf_Header_t { - uint8_t identity[LIEF_ELF_EI_NIDENT]; - enum LIEF_ELF_E_TYPE file_type; - enum LIEF_ELF_ARCH machine_type; - enum LIEF_ELF_VERSION object_file_version; - uint64_t entrypoint; - uint64_t program_headers_offset; - uint64_t section_headers_offset; - uint32_t processor_flags; - uint32_t header_size; - uint32_t program_header_size; - uint32_t numberof_segments; - uint32_t section_header_size; - uint32_t numberof_sections; - uint32_t name_string_table_idx; -}; - -typedef struct Elf_Header_t Elf_Header_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/Section.h b/vendor/lief/api/c/include/LIEF/ELF/Section.h deleted file mode 100644 index cc57d1e..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/Section.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_SECTION_H_ -#define C_LIEF_ELF_SECTION_H_ - -#include - -#include "LIEF/ELF/enums.h" - -/** @defgroup elf_section_c_api Section - * @ingroup elf_c_api - * @addtogroup elf_section_c_api - * @brief Section C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Elf_Section_t { - const char* name; - uint32_t flags; - enum LIEF_ELF_ELF_SECTION_TYPES type; - uint64_t virtual_address; - uint64_t offset; - uint64_t original_size; - uint32_t link; - uint32_t info; - uint64_t alignment; - uint64_t entry_size; - uint64_t size; - uint8_t* content; - double entropy; -}; - -typedef struct Elf_Section_t Elf_Section_t; - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/Segment.h b/vendor/lief/api/c/include/LIEF/ELF/Segment.h deleted file mode 100644 index d514d6d..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/Segment.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_SEGMENT_H_ -#define C_LIEF_ELF_SEGMENT_H_ - -#include -#include "LIEF/ELF/enums.h" - -/** @defgroup elf_segment_c_api Segment - * @ingroup elf_c_api - * @addtogroup elf_segment_c_api - * @brief Segment C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Elf_Segment_t { - enum LIEF_ELF_SEGMENT_TYPES type; - uint32_t flags; - uint64_t virtual_address; - uint64_t virtual_size; - uint64_t offset; - uint64_t alignment; - uint64_t size; - uint8_t* content; -}; - -typedef struct Elf_Segment_t Elf_Segment_t; - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/Symbol.h b/vendor/lief/api/c/include/LIEF/ELF/Symbol.h deleted file mode 100644 index 541caac..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/Symbol.h +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_SYMBOL_H_ -#define C_LIEF_ELF_SYMBOL_H_ - -#include - -#include "LIEF/ELF/enums.h" -#include "LIEF/types.h" -/** @defgroup elf_symbol_c_api Symbol - * @ingroup elf_c_api - * @addtogroup elf_symbol_c_api - * @brief Symbol C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Elf_Symbol_t { - const char* name; - enum LIEF_ELF_ELF_SYMBOL_TYPES type; - enum LIEF_ELF_SYMBOL_BINDINGS binding; - uint8_t information; - uint8_t other; - uint16_t shndx; - uint64_t value; - uint64_t size; - bool is_exported; /**< Whether or not the symbol is exported */ - bool is_imported; /**< Whether or not the symbol is imported */ -}; - -typedef struct Elf_Symbol_t Elf_Symbol_t; - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/enums.h b/vendor/lief/api/c/include/LIEF/ELF/enums.h deleted file mode 100644 index 986a85b..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/enums.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef LIEF_ELF_C_ENUMS_H_ -#define LIEF_ELF_C_ENUMS_H_ -#include "LIEF/ELF/undef.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _LIEF_EN(N) LIEF_ELF_##N // enum LIEF_N { -#define _LIEF_EN_2(N, TYPE) LIEF_ELF_##N // enum LIEF_N { -#define _LIEF_EI(X) LIEF_ELF_##X // LIEF_X - -#include "LIEF/ELF/enums.inc" - -#undef _LIEF_EN -#undef _LIEF_EN_2 -#undef _LIEF_EI - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/ELF/utils.h b/vendor/lief/api/c/include/LIEF/ELF/utils.h deleted file mode 100644 index cdb2b96..0000000 --- a/vendor/lief/api/c/include/LIEF/ELF/utils.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_ELF_UTILS_H_ -#define C_LIEF_ELF_UTILS_H_ - -/** @defgroup elf_utils_c_api Utils - * @ingroup elf_c_api - * @addtogroup elf_utils_c_api - * @brief Utils C API - * - * @{ - */ - -#include - -#include "LIEF/visibility.h" -#include "LIEF/types.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Check if the given file is an ELF one. */ -LIEF_API bool is_elf(const char* file); - -#ifdef __cplusplus -} -#endif - - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/LIEF.h b/vendor/lief/api/c/include/LIEF/LIEF.h deleted file mode 100644 index 4f0ea40..0000000 --- a/vendor/lief/api/c/include/LIEF/LIEF.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_H_ -#define C_LIEF_H_ - -#include -#include -#include -#include - -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO.h b/vendor/lief/api/c/include/LIEF/MachO.h deleted file mode 100644 index 6e949a4..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_H_ -#define C_LIEF_MACHO_H_ - -//! @defgroup macho_c_api MachO C API - -#include "LIEF/MachO/Binary.h" -#include "LIEF/MachO/Symbol.h" -#include "LIEF/MachO/Segment.h" -#include "LIEF/MachO/Section.h" -#include "LIEF/MachO/LoadCommand.h" -#include "LIEF/MachO/Header.h" -#include "LIEF/MachO/EnumToString.h" -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/Binary.h b/vendor/lief/api/c/include/LIEF/MachO/Binary.h deleted file mode 100644 index ba4b642..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/Binary.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_BINARY_H_ -#define C_LIEF_MACHO_BINARY_H_ - -/** @defgroup macho_binary_c_api Binary - * @ingroup macho_c_api - * @addtogroup macho_binary_c_api - * @brief Binary C API - * - * @{ - */ - -#include - -#include "LIEF/visibility.h" - -#include "LIEF/MachO/Header.h" -#include "LIEF/MachO/LoadCommand.h" -#include "LIEF/MachO/Symbol.h" -#include "LIEF/MachO/Section.h" -#include "LIEF/MachO/Segment.h" -#include "LIEF/MachO/enums.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief LIEF::MachO::Binary C Handler */ -struct Macho_Binary_t { - void* handler; - const char* name; - uint64_t imagebase; - Macho_Header_t header; - Macho_Command_t** commands; - Macho_Symbol_t** symbols; - Macho_Section_t** sections; - Macho_Segment_t** segments; - -}; - -typedef struct Macho_Binary_t Macho_Binary_t; - -/** @brief Wrapper on LIEF::MachO::Parser::parse */ -LIEF_API Macho_Binary_t** macho_parse(const char *file); - -LIEF_API void macho_binaries_destroy(Macho_Binary_t** binaries); - -#ifdef __cplusplus -} -#endif - - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/EnumToString.h b/vendor/lief/api/c/include/LIEF/MachO/EnumToString.h deleted file mode 100644 index 3b99074..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/EnumToString.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_ENUM_TO_STRING_H_ -#define C_LIEF_MACHO_ENUM_TO_STRING_H_ - -#include "LIEF/visibility.h" -#include "LIEF/MachO/enums.h" - -#ifdef __cplusplus -extern "C" { -#endif - -LIEF_API const char* LOAD_COMMAND_TYPES_to_string(enum LIEF_MACHO_LOAD_COMMAND_TYPES e); -LIEF_API const char* MACHO_TYPES_to_string(enum LIEF_MACHO_MACHO_TYPES e); -LIEF_API const char* FILE_TYPES_to_string(enum LIEF_MACHO_FILE_TYPES e); -LIEF_API const char* CPU_TYPES_to_string(enum LIEF_MACHO_CPU_TYPES e); -LIEF_API const char* HEADER_FLAGS_to_string(enum LIEF_MACHO_HEADER_FLAGS e); -LIEF_API const char* MACHO_SECTION_TYPES_to_string(enum LIEF_MACHO_MACHO_SECTION_TYPES e); -LIEF_API const char* MACHO_SYMBOL_TYPES_to_string(enum LIEF_MACHO_MACHO_SYMBOL_TYPES e); -LIEF_API const char* N_LIST_TYPES_to_string(enum LIEF_MACHO_N_LIST_TYPES e); -LIEF_API const char* SYMBOL_DESCRIPTIONS_to_string(enum LIEF_MACHO_SYMBOL_DESCRIPTIONS e); - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/Header.h b/vendor/lief/api/c/include/LIEF/MachO/Header.h deleted file mode 100644 index 99d853e..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/Header.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_HEADER_H_ -#define C_LIEF_MACHO_HEADER_H_ -#include - -#include "LIEF/MachO/enums.h" -/** @defgroup macho_header_c_api Header - * @ingroup macho_c_api - * @addtogroup macho_header_c_api - * @brief Header C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Macho_Header_t { - uint32_t magic; - enum LIEF_MACHO_CPU_TYPES cpu_type; - uint32_t cpu_subtype; - enum LIEF_MACHO_FILE_TYPES file_type; - uint32_t nb_cmds; - uint32_t sizeof_cmds; - uint32_t flags; - uint32_t reserved; -}; - -typedef struct Macho_Header_t Macho_Header_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/LoadCommand.h b/vendor/lief/api/c/include/LIEF/MachO/LoadCommand.h deleted file mode 100644 index 0cc933b..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/LoadCommand.h +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_LOAD_COMMAND_H_ -#define C_LIEF_MACHO_LOAD_COMMAND_H_ -#include - -#include "LIEF/MachO/enums.h" -/** @defgroup macho_load_command_c_api Header - * @ingroup macho_c_api - * @addtogroup macho_load_command_c_api - * @brief Load Command C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Macho_Command_t { - enum LIEF_MACHO_LOAD_COMMAND_TYPES command; - uint32_t size; - uint8_t* data; - uint32_t offset; -}; - -typedef struct Macho_Command_t Macho_Command_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/Section.h b/vendor/lief/api/c/include/LIEF/MachO/Section.h deleted file mode 100644 index 9423856..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/Section.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_SECTION_H_ -#define C_LIEF_MACHO_SECTION_H_ -#include - -#include "LIEF/MachO/enums.h" -/** @defgroup macho_section_c_api Header - * @ingroup macho_c_api - * @addtogroup macho_section_c_api - * @brief Section C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Macho_Section_t { - - const char* name; - uint32_t alignment; - uint32_t relocation_offset; - uint32_t numberof_relocations; - uint32_t flags; - enum LIEF_MACHO_MACHO_SECTION_TYPES type; - uint32_t reserved1; - uint32_t reserved2; - uint32_t reserved3; - uint64_t virtual_address; - uint64_t offset; - uint64_t size; - uint8_t* content; - double entropy; -}; - -typedef struct Macho_Section_t Macho_Section_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/Segment.h b/vendor/lief/api/c/include/LIEF/MachO/Segment.h deleted file mode 100644 index 79a5154..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/Segment.h +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_SEGMENT_H_ -#define C_LIEF_MACHO_SEGMENT_H_ -#include - -#include "LIEF/MachO/enums.h" -/** @defgroup macho_segment_c_api Header - * @ingroup macho_c_api - * @addtogroup macho_segment_c_api - * @brief Segment C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Macho_Segment_t { - const char* name; - uint64_t virtual_address; - uint64_t virtual_size; - uint64_t file_size; - uint64_t file_offset; - uint32_t max_protection; - uint32_t init_protection; - uint32_t numberof_sections; - uint32_t flags; - uint8_t* content; - uint64_t size; - Macho_Section_t** sections; -}; - -typedef struct Macho_Segment_t Macho_Segment_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/Symbol.h b/vendor/lief/api/c/include/LIEF/MachO/Symbol.h deleted file mode 100644 index f74e654..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/Symbol.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_MACHO_SYMBOL_H_ -#define C_LIEF_MACHO_SYMBOL_H_ -#include - -#include "LIEF/MachO/enums.h" -/** @defgroup macho_symbol_c_api Header - * @ingroup macho_c_api - * @addtogroup macho_symbol_c_api - * @brief Symbol C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Macho_Symbol_t { - const char* name; - uint8_t type; - uint8_t numberof_sections; - uint16_t description; - uint64_t value; -}; - -typedef struct Macho_Symbol_t Macho_Symbol_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/MachO/enums.h b/vendor/lief/api/c/include/LIEF/MachO/enums.h deleted file mode 100644 index 08c10c6..0000000 --- a/vendor/lief/api/c/include/LIEF/MachO/enums.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef LIEF_MACHO_C_ENUMS_H_ -#define LIEF_MACHO_C_ENUMS_H_ -#include "LIEF/MachO/undef.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef _LIEF_EN - #undef _LIEF_EN -#endif - -#ifdef _LIEF_EN_2 - #undef _LIEF_EN_2 -#endif - -#ifdef _LIEF_EI - #undef _LIEF_EI -#endif - -#define _LIEF_EN(N) LIEF_MACHO_##N // enum LIEF_N { -#define _LIEF_EN_2(N, TYPE) LIEF_MACHO_##N // enum LIEF_N { -#define _LIEF_EI(X) LIEF_MACHO_##X // LIEF_X - -#include "LIEF/MachO/enums.inc" - -#undef _LIEF_EN -#undef _LIEF_EN_2 -#undef _LIEF_EI - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE.h b/vendor/lief/api/c/include/LIEF/PE.h deleted file mode 100644 index ed0fcee..0000000 --- a/vendor/lief/api/c/include/LIEF/PE.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_H_ -#define C_LIEF_PE_H_ - -//! @defgroup pe_c_api PE C API - -#include "LIEF/PE/Binary.h" -#include "LIEF/PE/EnumToString.h" -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/Binary.h b/vendor/lief/api/c/include/LIEF/PE/Binary.h deleted file mode 100644 index 67d3309..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/Binary.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_BINARY_H_ -#define C_LIEF_PE_BINARY_H_ - -/** @defgroup pe_binary_c_api Binary - * @ingroup pe_c_api - * @addtogroup pe_binary_c_api - * @brief Binary C API - * - * @{ - */ - -#include - -#include "LIEF/visibility.h" - -#include "LIEF/PE/enums.h" - -#include "LIEF/PE/DosHeader.h" -#include "LIEF/PE/Header.h" -#include "LIEF/PE/OptionalHeader.h" -#include "LIEF/PE/DataDirectory.h" -#include "LIEF/PE/Section.h" -#include "LIEF/PE/Import.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief LIEF::PE::Binary C Handler */ -struct Pe_Binary_t { - void* handler; - const char* name; - Pe_DosHeader_t dos_header; - Pe_Header_t header; - Pe_OptionalHeader_t optional_header; - Pe_DataDirectory_t** data_directories; - Pe_Section_t** sections; - Pe_Import_t** imports; -}; - -typedef struct Pe_Binary_t Pe_Binary_t; - -/** Wrapper on LIEF::PE::Parser::parse */ -LIEF_API Pe_Binary_t* pe_parse(const char *file); - -LIEF_API void pe_binary_destroy(Pe_Binary_t* binary); - -#ifdef __cplusplus -} -#endif - - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/DataDirectory.h b/vendor/lief/api/c/include/LIEF/PE/DataDirectory.h deleted file mode 100644 index 4118484..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/DataDirectory.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_DATA_DIRECTORY_H_ -#define C_LIEF_PE_DATA_DIRECTORY_H_ - -#include - -#include "LIEF/PE/enums.h" -/** @defgroup pe_data_directory_c_api Section - * @ingroup pe_c_api - * @addtogroup pe_data_directory_c_api - * @brief Data directory C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_DataDirectory_t { - uint32_t rva; - uint32_t size; -}; - -typedef struct Pe_DataDirectory_t Pe_DataDirectory_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/DosHeader.h b/vendor/lief/api/c/include/LIEF/PE/DosHeader.h deleted file mode 100644 index 6df702f..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/DosHeader.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_DOS_HEADER_H_ -#define C_LIEF_PE_DOS_HEADER_H_ -#include - -#include "LIEF/ELF/enums.h" -/** @defgroup pe_dos_header_c_api DosHeader - * @ingroup pe_c_api - * @addtogroup pe_dos_header_c_api - * @brief Dos Header C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_DosHeader_t { - uint16_t magic ; - uint16_t used_bytes_in_the_last_page; - uint16_t file_size_in_pages; - uint16_t numberof_relocation; - uint16_t header_size_in_paragraphs; - uint16_t minimum_extra_paragraphs; - uint16_t maximum_extra_paragraphs; - uint16_t initial_relative_ss; - uint16_t initial_sp; - uint16_t checksum; - uint16_t initial_ip; - uint16_t initial_relative_cs; - uint16_t addressof_relocation_table; - uint16_t overlay_number; - uint16_t reserved[4]; - uint16_t oem_id; - uint16_t oem_info; - uint16_t reserved2[10]; - uint32_t addressof_new_exeheader; -}; - -typedef struct Pe_DosHeader_t Pe_DosHeader_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/EnumToString.h b/vendor/lief/api/c/include/LIEF/PE/EnumToString.h deleted file mode 100644 index f89db52..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/EnumToString.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_ENUM_TO_STRING_H_ -#define C_LIEF_PE_ENUM_TO_STRING_H_ - -#include "LIEF/visibility.h" - -#include "LIEF/PE/enums.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -LIEF_API const char* PE_TYPES_to_string(enum LIEF_PE_PE_TYPES e); -LIEF_API const char* MACHINE_TYPES_to_string(enum LIEF_PE_MACHINE_TYPES e); -LIEF_API const char* SUBSYSTEM_to_string(enum LIEF_PE_SUBSYSTEM e); - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/Header.h b/vendor/lief/api/c/include/LIEF/PE/Header.h deleted file mode 100644 index df310bb..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/Header.h +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_HEADER_H_ -#define C_LIEF_PE_HEADER_H_ - -#include - -#include "LIEF/PE/enums.h" -/** @defgroup pe_header_c_api Header - * @ingroup pe_c_api - * @addtogroup pe_header_c_api - * @brief Header C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_Header_t { - uint8_t signature[4]; - enum LIEF_PE_MACHINE_TYPES machine; - uint16_t numberof_sections; - uint32_t time_date_stamp; - uint32_t pointerto_symbol_table; - uint32_t numberof_symbols; - uint16_t sizeof_optional_header; - uint16_t characteristics; -}; - -typedef struct Pe_Header_t Pe_Header_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/Import.h b/vendor/lief/api/c/include/LIEF/PE/Import.h deleted file mode 100644 index 174b6b8..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/Import.h +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_IMPORT_H_ -#define C_LIEF_PE_IMPORT_H_ - -#include - -#include "LIEF/PE/enums.h" -#include "LIEF/PE/ImportEntry.h" - -/** @defgroup pe_import_c_api Import - * @ingroup pe_c_api - * @addtogroup pe_import_c_api - * @brief Import C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_Import_t { - const char* name; - uint32_t forwarder_chain; - uint32_t timedatestamp; - Pe_ImportEntry_t** entries; - uint32_t import_address_table_rva; - uint32_t import_lookup_table_rva; -}; - -typedef struct Pe_Import_t Pe_Import_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/ImportEntry.h b/vendor/lief/api/c/include/LIEF/PE/ImportEntry.h deleted file mode 100644 index 1efcdba..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/ImportEntry.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_IMPORT_ENTRY_H_ -#define C_LIEF_PE_IMPORT_ENTRY_H_ - -#include - -#include "LIEF/types.h" - -#include "LIEF/PE/enums.h" -#include "LIEF/PE/ImportEntry.h" - -/** @defgroup pe_import_entry_c_api Import Entry - * @ingroup pe_c_api - * @addtogroup pe_import_entry_c_api - * @brief Import Entry C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_ImportEntry_t { - bool is_ordinal; - const char* name; - uint16_t ordinal; - uint64_t hint_name_rva; - uint16_t hint; - uint64_t iat_value; - uint64_t data; - uint64_t iat_address; -}; - -typedef struct Pe_ImportEntry_t Pe_ImportEntry_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/OptionalHeader.h b/vendor/lief/api/c/include/LIEF/PE/OptionalHeader.h deleted file mode 100644 index f038e3b..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/OptionalHeader.h +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_OPTIONAL_HEADER_H_ -#define C_LIEF_PE_OPTIONAL_HEADER_H_ -#include - -#include "LIEF/PE/enums.h" -/** @defgroup pe_optional_header_c_api OptionalHeader - * @ingroup pe_c_api - * @addtogroup pe_optional_header_c_api - * @brief OptionalHeader C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_OptionalHeader_t { - enum LIEF_PE_PE_TYPES magic; - uint8_t major_linker_version; - uint8_t minor_linker_version; - uint32_t sizeof_code; - uint32_t sizeof_initialized_data; - uint32_t sizeof_uninitialized_data; - uint32_t addressof_entrypoint; - uint32_t baseof_code; - uint32_t baseof_data; - uint64_t imagebase; - uint32_t section_alignment; - uint32_t file_alignment; - uint16_t major_operating_system_version; - uint16_t minor_operating_system_version; - uint16_t major_image_version; - uint16_t minor_image_version; - uint16_t major_subsystem_version; - uint16_t minor_subsystem_version; - uint32_t win32_version_value; - uint32_t sizeof_image; - uint32_t sizeof_headers; - uint32_t checksum; - enum LIEF_PE_SUBSYSTEM subsystem; - uint32_t dll_characteristics; - uint64_t sizeof_stack_reserve; - uint64_t sizeof_stack_commit; - uint64_t sizeof_heap_reserve; - uint64_t sizeof_heap_commit; - uint32_t loader_flags; - uint32_t numberof_rva_and_size; -}; - -typedef struct Pe_OptionalHeader_t Pe_OptionalHeader_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/Section.h b/vendor/lief/api/c/include/LIEF/PE/Section.h deleted file mode 100644 index 3cb0341..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/Section.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef C_LIEF_PE_SECTION_H_ -#define C_LIEF_PE_SECTION_H_ - -#include - -#include "LIEF/PE/enums.h" -/** @defgroup pe_section_c_api Section - * @ingroup pe_c_api - * @addtogroup pe_section_c_api - * @brief Section C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -struct Pe_Section_t { - const char* name; - uint64_t virtual_address; - uint64_t size; - uint64_t offset; - - uint32_t virtual_size; - uint32_t pointerto_relocation; - uint32_t pointerto_line_numbers; - uint32_t characteristics; - - uint8_t* content; - uint64_t content_size; - double entropy; - -}; - -typedef struct Pe_Section_t Pe_Section_t; - - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif diff --git a/vendor/lief/api/c/include/LIEF/PE/enums.h b/vendor/lief/api/c/include/LIEF/PE/enums.h deleted file mode 100644 index 80c03be..0000000 --- a/vendor/lief/api/c/include/LIEF/PE/enums.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef LIEF_PE_C_ENUMS_H_ -#define LIEF_PE_C_ENUMS_H_ -#include "LIEF/PE/undef.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _LIEF_EN(N) LIEF_PE_##N // enum LIEF_N { -#define _LIEF_EN_2(N, TYPE) LIEF_PE_##N // enum LIEF_N { -#define _LIEF_EI(X) LIEF_PE_##X // LIEF_X - -#include "LIEF/PE/enums.inc" - -#undef _LIEF_EN -#undef _LIEF_EN_2 -#undef _LIEF_EI - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/vendor/lief/api/c/include/LIEF/logging.h b/vendor/lief/api/c/include/LIEF/logging.h deleted file mode 100644 index f3333ae..0000000 --- a/vendor/lief/api/c/include/LIEF/logging.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "LIEF/visibility.h" - -#ifndef C_LIEF_LOGGING_H_ -#define C_LIEF_LOGGING_H_ - -/** @defgroup logging_c_api Logging - * @brief Logging C API - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Disable the logging module */ -LIEF_API void lief_logging_disable(void); - -/** @brief Enable the logging module globally*/ -LIEF_API void lief_logging_enable(void); - -/** @brief Update logging level */ -LIEF_API void lief_logging_set_level(uint32_t level); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif - diff --git a/vendor/lief/api/c/include/LIEF/types.h b/vendor/lief/api/c/include/LIEF/types.h deleted file mode 100644 index e767ed7..0000000 --- a/vendor/lief/api/c/include/LIEF/types.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_C_TYPES_H_ -#define LIEF_C_TYPES_H_ -#include -#ifndef __cplusplus -#ifndef bool -typedef int bool; -#endif -#endif -#endif diff --git a/vendor/lief/api/c/logging.cpp b/vendor/lief/api/c/logging.cpp deleted file mode 100644 index 6f4b8d9..0000000 --- a/vendor/lief/api/c/logging.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/logging.hpp" -#include "LIEF/logging.h" - -using namespace LIEF::logging; - -void lief_logging_disable(void) { - disable(); -} - -void lief_logging_enable(void) { - enable(); -} - -void lief_logging_set_level(uint32_t level) { - set_level(static_cast(level)); -} diff --git a/vendor/lief/api/python/ART/CMakeLists.txt b/vendor/lief/api/python/ART/CMakeLists.txt deleted file mode 100644 index 422be7e..0000000 --- a/vendor/lief/api/python/ART/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -set(LIEF_PYTHON_ART_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyART.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFile.cpp" -) - -set(LIEF_PYTHON_ART_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyART.hpp") - -source_group("Source Files\\ART" FILES ${LIEF_PYTHON_ART_SRC}) -source_group("Header Files\\ART" FILES ${LIEF_PYTHON_ART_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ART_SRC}" "${LIEF_PYTHON_ART_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../") - - diff --git a/vendor/lief/api/python/ART/objects/pyFile.cpp b/vendor/lief/api/python/ART/objects/pyFile.cpp deleted file mode 100644 index ddd6a46..0000000 --- a/vendor/lief/api/python/ART/objects/pyFile.cpp +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/ART/File.hpp" -#include "LIEF/ART/hash.hpp" - -#include "pyART.hpp" - -namespace LIEF { -namespace ART { - -template -using no_const_getter = T (File::*)(void); - -template -using no_const_func = T (File::*)(P); - -template -using getter_t = T (File::*)(void) const; - -template -using setter_t = void (File::*)(T); - -template<> -void create(py::module& m) { - - // File object - py::class_(m, "File", "ART File representation") - - .def_property_readonly("header", - static_cast>(&File::header), - "Return the ART " RST_CLASS_REF(lief.ART.Header) "", - py::return_value_policy::reference) - - .def("__eq__", &File::operator==) - .def("__ne__", &File::operator!=) - .def("__hash__", - [] (const File& file) { - return Hash::hash(file); - }) - - .def("__str__", - [] (const File& file) - { - std::ostringstream stream; - stream << file; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ART/objects/pyHeader.cpp b/vendor/lief/api/python/ART/objects/pyHeader.cpp deleted file mode 100644 index 4aab5fc..0000000 --- a/vendor/lief/api/python/ART/objects/pyHeader.cpp +++ /dev/null @@ -1,114 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/ART/Header.hpp" -#include "LIEF/ART/hash.hpp" - -#include "pyART.hpp" - -namespace LIEF { -namespace ART { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - -template<> -void create
(py::module& m) { - - py::class_(m, "Header", "ART Header representation") - .def_property_readonly("magic", - static_cast>(&Header::magic) - ) - .def_property_readonly("version", - static_cast>(&Header::version) - ) - .def_property_readonly("image_begin", - static_cast>(&Header::image_begin) - ) - .def_property_readonly("image_size", - static_cast>(&Header::image_size) - ) - .def_property_readonly("oat_checksum", - static_cast>(&Header::oat_checksum) - ) - .def_property_readonly("oat_file_begin", - static_cast>(&Header::oat_file_begin) - ) - .def_property_readonly("oat_file_end", - static_cast>(&Header::oat_file_end) - ) - .def_property_readonly("oat_data_end", - static_cast>(&Header::oat_data_end) - ) - .def_property_readonly("patch_delta", - static_cast>(&Header::patch_delta) - ) - .def_property_readonly("image_roots", - static_cast>(&Header::image_roots) - ) - .def_property_readonly("pointer_size", - static_cast>(&Header::pointer_size) - ) - .def_property_readonly("compile_pic", - static_cast>(&Header::compile_pic) - ) - .def_property_readonly("nb_sections", - static_cast>(&Header::nb_sections) - ) - .def_property_readonly("nb_methods", - static_cast>(&Header::nb_methods) - ) - .def_property_readonly("boot_image_begin", - static_cast>(&Header::boot_image_begin) - ) - .def_property_readonly("boot_image_size", - static_cast>(&Header::boot_image_size) - ) - .def_property_readonly("boot_oat_begin", - static_cast>(&Header::boot_oat_begin) - ) - .def_property_readonly("boot_oat_size", - static_cast>(&Header::boot_oat_size) - ) - .def_property_readonly("storage_mode", - static_cast>(&Header::storage_mode) - ) - .def_property_readonly("data_size", - static_cast>(&Header::data_size) - ) - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - .def("__str__", - [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} -} -} - - diff --git a/vendor/lief/api/python/ART/objects/pyParser.cpp b/vendor/lief/api/python/ART/objects/pyParser.cpp deleted file mode 100644 index 2f06e5b..0000000 --- a/vendor/lief/api/python/ART/objects/pyParser.cpp +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyART.hpp" - -#include "LIEF/ART/Parser.hpp" - -#include - -namespace LIEF { -namespace ART { - -template<> -void create(py::module& m) { - - // Parser (Parser) - m.def("parse", - static_cast (*) (const std::string&)>(&Parser::parse), - "Parse the given filename and return an " RST_CLASS_REF(lief.ART.File) " object", - "filename"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast (*) (std::vector, const std::string&)>(&Parser::parse), - "Parse the given raw data and return an " RST_CLASS_REF(lief.ART.File) " object", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::ART::Parser::parse(std::move(raw), name); - }, - "io"_a, "name"_a = "", - py::return_value_policy::take_ownership); -} - -} -} diff --git a/vendor/lief/api/python/ART/pyART.cpp b/vendor/lief/api/python/ART/pyART.cpp deleted file mode 100644 index ba9ee17..0000000 --- a/vendor/lief/api/python/ART/pyART.cpp +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyART.hpp" - - -namespace LIEF { -namespace ART { -void init_python_module(py::module& m) { - py::module LIEF_ART_module = m.def_submodule("ART", "Python API for ART format"); - - init_enums(LIEF_ART_module); - init_objects(LIEF_ART_module); - init_utils(LIEF_ART_module); -} - - -void init_objects(py::module& m) { - CREATE(Parser, m); - CREATE(File, m); - CREATE(Header, m); -} - -} -} diff --git a/vendor/lief/api/python/ART/pyART.hpp b/vendor/lief/api/python/ART/pyART.hpp deleted file mode 100644 index f61510a..0000000 --- a/vendor/lief/api/python/ART/pyART.hpp +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ART_H_ -#define PY_LIEF_ART_H_ - -#include "LIEF/ART.hpp" - -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -namespace LIEF { -namespace ART { - -template -void create(py::module&); - -void init_python_module(py::module& m); - -void init_objects(py::module&); - -void init_enums(py::module&); - -void init_utils(py::module&); - - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(File); -SPECIALIZE_CREATE(Header); - -} -} - - -#endif diff --git a/vendor/lief/api/python/ART/pyEnums.cpp b/vendor/lief/api/python/ART/pyEnums.cpp deleted file mode 100644 index 205d667..0000000 --- a/vendor/lief/api/python/ART/pyEnums.cpp +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyART.hpp" -#include "LIEF/ART/enums.hpp" -#include "LIEF/ART/EnumToString.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace ART { -void init_enums(py::module& m) { - - py::enum_(m, "STORAGE_MODES") - .value(PY_ENUM(STORAGE_MODES::STORAGE_UNCOMPRESSED)) - .value(PY_ENUM(STORAGE_MODES::STORAGE_LZ4)) - .value(PY_ENUM(STORAGE_MODES::STORAGE_LZ4HC)); - -} -} -} diff --git a/vendor/lief/api/python/ART/pyUtils.cpp b/vendor/lief/api/python/ART/pyUtils.cpp deleted file mode 100644 index 69ff112..0000000 --- a/vendor/lief/api/python/ART/pyUtils.cpp +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyART.hpp" - -#include "LIEF/ART/utils.hpp" - -namespace LIEF { -namespace ART { - -void init_utils(py::module& m) { - - m.def("is_art", - static_cast(&is_art), - "Check if the **file** given in parameter is an ART", - "path"_a); - - m.def("is_art", - static_cast&)>(&is_art), - "Check if the **raw data** given in parameter is a ART", - "raw"_a); - - m.def("version", - static_cast(&version), - "Return the ART version of the **file** given in parameter", - "file"_a); - - m.def("version", - static_cast&)>(&version), - "Return the ART version of the **raw data** given in parameter", - "raw"_a); - - - m.def("android_version", - &android_version, - "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given ART version ", - "art_version"_a); -} - -} -} - diff --git a/vendor/lief/api/python/Abstract/CMakeLists.txt b/vendor/lief/api/python/Abstract/CMakeLists.txt deleted file mode 100644 index 6075ed8..0000000 --- a/vendor/lief/api/python/Abstract/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ - -set(LIEF_PYTHON_ABSTRACT_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyAbstract.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBinary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySection.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocation.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFunction.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" -) - - -set(LIEF_PYTHON_ABSTRACT_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyAbstract.hpp" -) - -source_group("Source Files\\Abstract" FILES ${LIEF_PYTHON_ABSTRACT_SRC}) -source_group("Header Files\\Abstract" FILES ${LIEF_PYTHON_ABSTRACT_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ABSTRACT_SRC}" "${LIEF_PYTHON_ABSTRACT_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") - - diff --git a/vendor/lief/api/python/Abstract/objects/pyBinary.cpp b/vendor/lief/api/python/Abstract/objects/pyBinary.cpp deleted file mode 100644 index 25c4ec7..0000000 --- a/vendor/lief/api/python/Abstract/objects/pyBinary.cpp +++ /dev/null @@ -1,248 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyAbstract.hpp" -#include "pyIterators.hpp" -#include "pyErr.hpp" -#include "LIEF/Abstract/Binary.hpp" - - -#define PY_ENUM(x) LIEF::to_string(x), x - -namespace LIEF { - -template -using getter_t = T (Binary::*)(void) const; - -template -using setter_t = void (Binary::*)(T); - -template -using it_t = T (Binary::*)(void); - -template -using no_const_func = T (Binary::*)(P); - -template<> -void create(py::module& m) { - py::class_ pybinary(m, "Binary", - R"delim( - File format abstract representation. - - This object represents the abstraction of an executable file format. - It enables to access common features (like the :attr:`~lief.Binary.entrypoint`) regardless - of the concrete format (e.g. :attr:`lief.ELF.Binary.entrypoint`) - )delim"); - - py::enum_(pybinary, "VA_TYPES") - .value(PY_ENUM(Binary::VA_TYPES::AUTO)) - .value(PY_ENUM(Binary::VA_TYPES::VA)) - .value(PY_ENUM(Binary::VA_TYPES::RVA)); - - init_ref_iterator(pybinary, "it_sections"); - init_ref_iterator(pybinary, "it_symbols"); - init_ref_iterator(pybinary, "it_relocations"); - - pybinary - .def_property_readonly("format", - &Binary::format, - "File format " RST_CLASS_REF(lief.EXE_FORMATS) " of the underlying binary.") - - .def_property_readonly("is_pie", - &Binary::is_pie, - "Check if the binary is position independent") - - .def_property_readonly("has_nx", - &Binary::has_nx, - "Check if the binary has ``NX`` protection (non executable stack)") - - .def_property("name", - static_cast>(&Binary::name), - static_cast>(&Binary::name), - "Binary's name") - - .def_property_readonly("header", - &Binary::header, - "Binary's abstract header (" RST_CLASS_REF(lief.Header) ")") - - .def_property_readonly("entrypoint", - &Binary::entrypoint, - "Binary's entrypoint") - - .def("remove_section", - static_cast(&Binary::remove_section), - "Remove the section with the given name", - "name"_a, "clear"_a = false) - - .def_property_readonly("sections", - static_cast>(&Binary::sections), - "Return an iterator over the binary's abstract sections (" RST_CLASS_REF(lief.Section) ")", - py::return_value_policy::reference_internal) - - .def_property_readonly("relocations", - static_cast>(&Binary::relocations), - "Return an iterator over abstract " RST_CLASS_REF(lief.Relocation) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("exported_functions", - &Binary::exported_functions, - "Return the binary's exported " RST_CLASS_REF(lief.Function) "") - - .def_property_readonly("imported_functions", - &Binary::imported_functions, - "Return the binary's imported " RST_CLASS_REF(lief.Function) " (name)") - - .def_property_readonly("libraries", - [] (const Binary& binary) { - const std::vector& imported_libraries = binary.imported_libraries(); - std::vector imported_libraries_encoded; - imported_libraries_encoded.reserve(imported_libraries.size()); - - std::transform( - std::begin(imported_libraries), std::end(imported_libraries), - std::back_inserter(imported_libraries_encoded), - &safe_string_converter); - return imported_libraries_encoded; - }, - "Return binary's imported libraries (name)") - - .def_property_readonly("symbols", - static_cast>(&Binary::symbols), - "Return an iterator over the binary's abstract " RST_CLASS_REF(lief.Symbol) "", - py::return_value_policy::reference_internal) - - .def("has_symbol", - &Binary::has_symbol, - "Check if a " RST_CLASS_REF(lief.Symbol) " with the given name exists", - "symbol_name"_a) - - .def("get_symbol", - static_cast>(&Binary::get_symbol), - R"delim( - Return the :class:`~lief.Symbol` from the given ``name``. - - If the symbol can't be found, it returns None. - )delim", - "symbol_name"_a, - py::return_value_policy::reference_internal) - - .def("get_function_address", - [] (const Binary& self, const std::string& name) { - return error_or(&Binary::get_function_address, self, name); - }, - "Return the address of the given function name", - "function_name"_a) - - .def("patch_address", - static_cast&, Binary::VA_TYPES)>(&Binary::patch_address), - R"delim( - Patch the address with the given list of bytes. - The virtual address is specified in the first argument and the content in the second (as a list of bytes). - - If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or - a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. - )delim", - "address"_a, "patch_value"_a, "va_type"_a = Binary::VA_TYPES::AUTO) - - .def("patch_address", - static_cast(&Binary::patch_address), - R"delim( - Patch the address with the given integer value. - The virtual address is specified in the first argument, the integer in the second and the integer's size of in third one. - - If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or - a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. - )delim", - "address"_a, "patch_value"_a, "size"_a = 8, "va_type"_a = Binary::VA_TYPES::AUTO) - - - .def("get_content_from_virtual_address", - &Binary::get_content_from_virtual_address, - R"delim( - Return the content located at the provided virtual address. - The virtual address is specified in the first argument and size to read (in bytes) in the second. - - If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or - a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. - )delim", - "virtual_address"_a, "size"_a, "va_type"_a = Binary::VA_TYPES::AUTO) - - .def_property_readonly("abstract", - [m] (py::object& self) { - self.attr("__class__") = m.attr("Binary"); - return self; - }, - R"delim( - Return the abstract representation of the current binary (:class:`lief.Binary`) - - .. warning:: - - Getting this property modifies the ``__class__`` attribute such as - the current binary looks like a :class:`lief.Binary`. - - To get back to the original binary, one needs to access :attr:`lief.Binary.concrete` - )delim", - py::return_value_policy::reference) - - - .def_property_readonly("concrete", - [m] (py::object& self) { - self.attr("__class__") = py::cast(self.cast()).attr("__class__"); - return self; - }, - R"delim( - The *concrete* representation of the binary. Basically, this property cast a :class:`lief.Binary` - into a :class:`lief.PE.Binary`, :class:`lief.ELF.Binary` or :class:`lief.MachO.Binary`. - - See also: :attr:`lief.Binary.abstract` - )delim", - py::return_value_policy::reference) - - .def_property_readonly("ctor_functions", - &Binary::ctor_functions, - "Constructor functions that are called prior to any other functions") - - .def("xref", - &Binary::xref, - "Return all **virtual addresses** that *use* the ``address`` given in parameter", - "virtual_address"_a) - - .def("offset_to_virtual_address", - [] (const Binary& self, uint64_t offset, uint64_t slide) { - return error_or(&Binary::offset_to_virtual_address, self, offset, slide); - }, - "Convert an offset into a virtual address.", - "offset"_a, "slide"_a = 0) - - .def_property_readonly("imagebase", - &Binary::imagebase, - "Default image base (i.e. if the ASLR is not enabled)") - - .def("__str__", - [] (const Binary& binary) - { - std::ostringstream stream; - stream << binary; - std::string str = stream.str(); - return str; - }); - -} - -} - diff --git a/vendor/lief/api/python/Abstract/objects/pyFunction.cpp b/vendor/lief/api/python/Abstract/objects/pyFunction.cpp deleted file mode 100644 index 7b7646a..0000000 --- a/vendor/lief/api/python/Abstract/objects/pyFunction.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAbstract.hpp" -#include "LIEF/Abstract/Symbol.hpp" - -#include -#include - -#define PY_ENUM(x) LIEF::to_string(x), x - -namespace LIEF { - -template -using getter_t = T (Function::*)(void) const; - -template -using setter_t = void (Function::*)(T); - -template<> -void create(py::module& m) { - - py::class_ pyfunction(m, "Function", - R"delim( - Class which represents a Function in an executable file format. - )delim"); - - py::enum_(pyfunction, "FLAGS") - .value(PY_ENUM(Function::FLAGS::IMPORTED)) - .value(PY_ENUM(Function::FLAGS::EXPORTED)) - .value(PY_ENUM(Function::FLAGS::CONSTRUCTOR)) - .value(PY_ENUM(Function::FLAGS::DESTRUCTOR)) - .value(PY_ENUM(Function::FLAGS::DEBUG)); - - pyfunction - .def(py::init()) - .def(py::init()) - .def(py::init()) - .def(py::init()) - - .def("add", - &Function::add, - "Add the given " RST_CLASS_REF(lief.Function.FLAGS) "", - "flag"_a) - - .def_property_readonly("flags", - &Function::flags, - "Function flags as a list of " RST_CLASS_REF(lief.Function.FLAGS) "") - - .def_property("address", - static_cast>(&Function::address), - static_cast>(&Function::address), - "Function's address") - - .def("__str__", - [] (const Function& f) { - std::ostringstream stream; - stream << f; - std::string str = stream.str(); - return str; - }); -} - -} diff --git a/vendor/lief/api/python/Abstract/objects/pyHeader.cpp b/vendor/lief/api/python/Abstract/objects/pyHeader.cpp deleted file mode 100644 index 932efd0..0000000 --- a/vendor/lief/api/python/Abstract/objects/pyHeader.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "pyAbstract.hpp" -#include "LIEF/Abstract/Header.hpp" - -namespace LIEF { -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - -template<> -void create
(py::module& m) { - py::class_(m, "Header") - .def(py::init()) - - .def_property("architecture", - static_cast>(&Header::architecture), - static_cast>(&Header::architecture), - "Target architecture (" RST_CLASS_REF(lief.ARCHITECTURES) ")") - - .def_property("modes", - static_cast&>>(&Header::modes), - static_cast&>>(&Header::modes), - "Target " RST_CLASS_REF(lief.MODES) " (32-bits, 64-bits...)") - - .def_property("entrypoint", - static_cast>(&Header::entrypoint), - static_cast>(&Header::entrypoint), - "Binary entrypoint") - - .def_property("object_type", - static_cast>(&Header::object_type), - static_cast>(&Header::object_type), - "Type of the binary (executable, library...)\n" - "See: " RST_CLASS_REF(lief.OBJECT_TYPES) "") - - .def_property("endianness", - static_cast>(&Header::endianness), - static_cast>(&Header::endianness), - "Binary endianness\n" - "See: " RST_CLASS_REF(lief.ENDIANNESS) "") - - .def_property_readonly("is_32", - &Header::is_32, - "``True`` if the binary targets a ``32-bits`` architecture") - - .def_property_readonly("is_64", - &Header::is_64, - "``True`` if the binary targets a ``64-bits`` architecture") - - - .def("__str__", - [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} -} diff --git a/vendor/lief/api/python/Abstract/objects/pyParser.cpp b/vendor/lief/api/python/Abstract/objects/pyParser.cpp deleted file mode 100644 index cc95b13..0000000 --- a/vendor/lief/api/python/Abstract/objects/pyParser.cpp +++ /dev/null @@ -1,168 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAbstract.hpp" - -#include "LIEF/Abstract/Parser.hpp" - -#include -#include - -namespace LIEF { -template<> -void create(py::module& m) { - - m.def("parse", - [] (py::bytes bytes, const std::string& name) { - std::string raw_str = bytes; - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str)) - }; - std::unique_ptr binary; - std::exception_ptr ep; - Py_BEGIN_ALLOW_THREADS - try { - binary = Parser::parse(std::move(raw), name); - } catch (...) { - ep = std::current_exception(); - } - Py_END_ALLOW_THREADS - if (ep) std::rethrow_exception(ep); - return binary; - }, - R"delim( - Parse a binary supported by LIEF from the given bytes and return either: - - - :class:`lief.ELF.Binary` - - :class:`lief.PE.Binary` - - :class:`lief.MachO.Binary` - - depending on the given binary format. - )delim", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - m.def("parse", - [] (const std::string& filepath) { - std::unique_ptr binary; - std::exception_ptr ep; - Py_BEGIN_ALLOW_THREADS - try { - binary = Parser::parse(filepath); - } catch (...) { - ep = std::current_exception(); - } - Py_END_ALLOW_THREADS - if (ep) std::rethrow_exception(ep); - return binary; - }, - R"delim( - Parse a binary from the given file path and return either: - - - :class:`lief.ELF.Binary` - - :class:`lief.PE.Binary` - - :class:`lief.MachO.Binary` - - depending on the given binary format. - )delim", - "filepath"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - [](const std::vector& raw, const std::string& name) { - std::unique_ptr binary; - std::exception_ptr ep; - Py_BEGIN_ALLOW_THREADS - try { - binary = Parser::parse(raw, name); - } catch (...) { - ep = std::current_exception(); - } - Py_END_ALLOW_THREADS - if (ep) std::rethrow_exception(ep); - return binary; - }, - R"delim( - Parse a binary supported by LIEF from the given list of bytes and return either: - - - :class:`lief.ELF.Binary` - - :class:`lief.PE.Binary` - - :class:`lief.MachO.Binary` - - depending on the given binary format. - )delim", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str)) - }; - - std::unique_ptr binary; - std::exception_ptr ep; - Py_BEGIN_ALLOW_THREADS - try { - binary = Parser::parse(std::move(raw), name); - } catch (...) { - ep = std::current_exception(); - } - Py_END_ALLOW_THREADS - if (ep) std::rethrow_exception(ep); - return binary; - }, - R"delim( - Parse a binary supported by LIEF from the given Python IO interface and return either: - - - :class:`lief.ELF.Binary` - - :class:`lief.PE.Binary` - - :class:`lief.MachO.Binary` - - depending on the given binary format. - )delim", - "io"_a, "name"_a = "", - py::return_value_policy::take_ownership); -} -} diff --git a/vendor/lief/api/python/Abstract/objects/pyRelocation.cpp b/vendor/lief/api/python/Abstract/objects/pyRelocation.cpp deleted file mode 100644 index 05d511d..0000000 --- a/vendor/lief/api/python/Abstract/objects/pyRelocation.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "pyAbstract.hpp" - -#include "LIEF/Abstract/hash.hpp" - -#include "LIEF/Abstract/Relocation.hpp" - -namespace LIEF { -template -using getter_t = T (Relocation::*)(void) const; - -template -using setter_t = void (Relocation::*)(T); - -template<> -void create(py::module& m) { - py::class_(m, "Relocation", - R"delim( - Class which represents an abstracted Relocation - )delim") - .def(py::init(), - "Default constructor") - - .def(py::init(), - "Constructor from an :attr:`~lief.Relocation.address` and a :attr:`~lief.Relocation.size`", - "address"_a, "size"_a) - - .def_property("address", - static_cast>(&Relocation::address), - static_cast>(&Relocation::address), - "Relocation's address") - - .def_property("size", - static_cast>(&Relocation::size), - static_cast>(&Relocation::size), - "Relocation's size (in **bits**)") - - .def("__eq__", &Relocation::operator==) - .def("__ne__", &Relocation::operator!=) - .def("__hash__", - [] (const Relocation& relocation) { - return AbstractHash::hash(relocation); - }) - - .def("__str__", - [] (const Relocation& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} -} diff --git a/vendor/lief/api/python/Abstract/objects/pySection.cpp b/vendor/lief/api/python/Abstract/objects/pySection.cpp deleted file mode 100644 index 92f0a4b..0000000 --- a/vendor/lief/api/python/Abstract/objects/pySection.cpp +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "pyAbstract.hpp" -#include "LIEF/Abstract/Section.hpp" - -namespace LIEF { -template -using getter_t = T (Section::*)(void) const; - -template -using setter_t = void (Section::*)(T); - -template<> -void create
(py::module& m) { - py::class_(m, "Section", - R"delim( - Class which represents an abstracted section - )delim") - .def(py::init(), - "Default constructor") - - .def(py::init(), - "Constructor from section name", - "name"_a) - - .def_property("name", - [] (const Section& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&Section::name), - "Section's name") - - .def_property_readonly("fullname", - &Section::fullname, - "Return the **fullname** of the section including the trailing bytes") - - .def_property("size", - static_cast>(&Section::size), - static_cast>(&Section::size), - "Section's size") - - .def_property("offset", - static_cast>(&Section::offset), - static_cast>(&Section::offset), - "Section's file offset") - - .def_property("virtual_address", - static_cast>(&Section::virtual_address), - static_cast>(&Section::virtual_address), - "Section's virtual address") - - .def_property("content", - [] (const Section& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast&>>(&Section::content), - "Section's content") - - .def_property_readonly("entropy", - &Section::entropy, - "Section's entropy") - - .def("search", - static_cast(&Section::search), - "Look for **integer** within the current section", - "number"_a, "pos"_a = 0, "size"_a = 0) - - .def("search", - static_cast(&Section::search), - "Look for **string** within the current section", - "str"_a, "pos"_a = 0) - - .def("search_all", - static_cast (Section::*)(uint64_t, size_t) const>(&Section::search_all), - "Look for **all** integers within the current section", - "number"_a, "size"_a = 0) - - .def("search_all", - static_cast (Section::*)(const std::string&) const>(&Section::search_all), - "Look for all **strings** within the current section", - "str"_a) - - .def("__str__", - [] (const Section& section) - { - std::ostringstream stream; - stream << section; - std::string str = stream.str(); - return str; - }); -} -} diff --git a/vendor/lief/api/python/Abstract/objects/pySymbol.cpp b/vendor/lief/api/python/Abstract/objects/pySymbol.cpp deleted file mode 100644 index 1a81c89..0000000 --- a/vendor/lief/api/python/Abstract/objects/pySymbol.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAbstract.hpp" -#include "LIEF/Abstract/Symbol.hpp" - -#include -#include - -namespace LIEF { - -template -using getter_t = T (Symbol::*)(void) const; - -template -using setter_t = void (Symbol::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "Symbol", - R"delim( - This class represents a symbol in an executable format. - )delim") - .def(py::init()) - - .def_property("name", - [] (const Symbol& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&Symbol::name), - "Symbol's name") - - .def_property("value", - static_cast>(&Symbol::value), - static_cast>(&Symbol::value), - "Symbol's value") - - .def_property("size", - static_cast>(&Symbol::size), - static_cast>(&Symbol::size), - "Symbol's size") - - .def("__str__", - [] (const Symbol& symbol) - { - std::ostringstream stream; - stream << symbol; - std::string str = stream.str(); - return str; - }); -} - -} diff --git a/vendor/lief/api/python/Abstract/pyAbstract.cpp b/vendor/lief/api/python/Abstract/pyAbstract.cpp deleted file mode 100644 index 7e177e9..0000000 --- a/vendor/lief/api/python/Abstract/pyAbstract.cpp +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyLIEF.hpp" -#include "pyAbstract.hpp" -namespace LIEF { - -void init_python_module(py::module& m) { - init_enums(m); - init_objects(m); -} - -void init_objects(py::module& m) { - CREATE(Header, m); - CREATE(Binary, m); - CREATE(Section, m); - CREATE(Symbol, m); - CREATE(Parser, m); - CREATE(Relocation, m); - CREATE(Function, m); -} - - -} - diff --git a/vendor/lief/api/python/Abstract/pyAbstract.hpp b/vendor/lief/api/python/Abstract/pyAbstract.hpp deleted file mode 100644 index 813530d..0000000 --- a/vendor/lief/api/python/Abstract/pyAbstract.hpp +++ /dev/null @@ -1,44 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ABSTRACT_H_ -#define PY_LIEF_ABSTRACT_H_ - -#include "pyLIEF.hpp" -#include "LIEF/Abstract.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - -namespace LIEF { -template -void create(py::module&); - -void init_python_module(py::module& m); -void init_objects(py::module&); -void init_enums(py::module&); - -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(Binary); -SPECIALIZE_CREATE(Section); -SPECIALIZE_CREATE(Symbol); -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(Relocation); -SPECIALIZE_CREATE(Function); -} -#endif diff --git a/vendor/lief/api/python/Abstract/pyEnums.cpp b/vendor/lief/api/python/Abstract/pyEnums.cpp deleted file mode 100644 index 40a1c6c..0000000 --- a/vendor/lief/api/python/Abstract/pyEnums.cpp +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAbstract.hpp" -#include "LIEF/Abstract/enums.hpp" -#include "LIEF/Abstract/EnumToString.hpp" - -#define PY_ENUM(x) LIEF::to_string(x), x -namespace LIEF { - -void init_enums(py::module& m) { - py::enum_(m, "EXE_FORMATS") - .value(PY_ENUM(EXE_FORMATS::FORMAT_UNKNOWN)) - .value(PY_ENUM(EXE_FORMATS::FORMAT_ELF)) - .value(PY_ENUM(EXE_FORMATS::FORMAT_PE)) - .value(PY_ENUM(EXE_FORMATS::FORMAT_MACHO)); - - py::enum_(m, "OBJECT_TYPES") - .value(PY_ENUM(OBJECT_TYPES::TYPE_NONE)) - .value(PY_ENUM(OBJECT_TYPES::TYPE_EXECUTABLE)) - .value(PY_ENUM(OBJECT_TYPES::TYPE_LIBRARY)) - .value(PY_ENUM(OBJECT_TYPES::TYPE_OBJECT)); - - py::enum_(m, "ARCHITECTURES") - .value(PY_ENUM(ARCHITECTURES::ARCH_NONE)) - .value(PY_ENUM(ARCHITECTURES::ARCH_ARM)) - .value(PY_ENUM(ARCHITECTURES::ARCH_ARM64)) - .value(PY_ENUM(ARCHITECTURES::ARCH_MIPS)) - .value(PY_ENUM(ARCHITECTURES::ARCH_X86)) - .value(PY_ENUM(ARCHITECTURES::ARCH_PPC)) - .value(PY_ENUM(ARCHITECTURES::ARCH_SPARC)) - .value(PY_ENUM(ARCHITECTURES::ARCH_SYSZ)) - .value(PY_ENUM(ARCHITECTURES::ARCH_XCORE)) - .value(PY_ENUM(ARCHITECTURES::ARCH_INTEL)) - .value(PY_ENUM(ARCHITECTURES::ARCH_RISCV)); - - py::enum_(m, "MODES") - .value(PY_ENUM(MODES::MODE_NONE)) - .value(PY_ENUM(MODES::MODE_16)) - .value(PY_ENUM(MODES::MODE_32)) - .value(PY_ENUM(MODES::MODE_64)) - .value(PY_ENUM(MODES::MODE_ARM)) - .value(PY_ENUM(MODES::MODE_THUMB)) - .value(PY_ENUM(MODES::MODE_MCLASS)) - .value(PY_ENUM(MODES::MODE_MICRO)) - .value(PY_ENUM(MODES::MODE_MIPS3)) - .value(PY_ENUM(MODES::MODE_MIPS32R6)) - .value(PY_ENUM(MODES::MODE_MIPSGP64)) - .value(PY_ENUM(MODES::MODE_V7)) - .value(PY_ENUM(MODES::MODE_V8)) - .value(PY_ENUM(MODES::MODE_V9)) - .value(PY_ENUM(MODES::MODE_MIPS32)) - .value(PY_ENUM(MODES::MODE_MIPS64)); - - py::enum_(m, "ENDIANNESS") - .value(PY_ENUM(ENDIANNESS::ENDIAN_NONE)) - .value(PY_ENUM(ENDIANNESS::ENDIAN_BIG)) - .value(PY_ENUM(ENDIANNESS::ENDIAN_LITTLE)); -} -} diff --git a/vendor/lief/api/python/CMakeLists.txt b/vendor/lief/api/python/CMakeLists.txt index 2e652c1..bc57754 100644 --- a/vendor/lief/api/python/CMakeLists.txt +++ b/vendor/lief/api/python/CMakeLists.txt @@ -1,214 +1,159 @@ -cmake_minimum_required(VERSION 3.1) - -# Avoid warning about DOWNLOAD_EXTRACT_TIMESTAMP in CMake 3.24: -if (CMAKE_VERSION VERSION_GREATER_EQUAL "3.24.0") - cmake_policy(SET CMP0135 NEW) -endif() - -include(ExternalProject) -include(CheckCXXCompilerFlag) -include(CheckCCompilerFlag) - - -macro(ADD_FLAG_IF_SUPPORTED flag name) - CHECK_C_COMPILER_FLAG("${flag}" "C_SUPPORTS_${name}") - CHECK_CXX_COMPILER_FLAG("${flag}" "CXX_SUPPORTS_${name}") - - if (C_SUPPORTS_${name}) - target_compile_options(pyLIEF PRIVATE ${flag}) +if (LIEF_PRECOMPILED) + if (LIEF_PY_LIEF_EXT_SHARED) + find_package(LIEF REQUIRED COMPONENTS SHARED) + else() + find_package(LIEF REQUIRED COMPONENTS STATIC) endif() - - if (CXX_SUPPORTS_${name}) - target_compile_options(pyLIEF PRIVATE ${flag}) - endif() -endmacro() - -add_library(lief_pybind11 INTERFACE) - -if (LIEF_EXTERNAL_PYBIND11) - find_package(pybind11 REQUIRED) - find_package(PythonLibsNew MODULE REQUIRED) - target_link_libraries(lief_pybind11 INTERFACE pybind11::module) - get_target_property(PYBIND_INC_DIR pybind11::module INTERFACE_INCLUDE_DIRECTORIES) - target_include_directories(lief_pybind11 SYSTEM INTERFACE ${PYBIND_INC_DIR} ${Python_INCLUDE_DIRS}) + message(STATUS "Using pre-installed version of LIEF") + set(LIEF_TARGET LIEF::LIEF) + set_target_properties(LIB_LIEF PROPERTIES EXCLUDE_FROM_ALL ON) else() - find_package(PythonLibsNew MODULE REQUIRED) - set(PYBIND11_VERSION 2.9.2) - set(PYBIND11_SHA256 SHA256=d1646e6f70d8a3acb2ddd85ce1ed543b5dd579c68b8fb8e9638282af20edead8) - set(PYBIND11_URL "${THIRD_PARTY_DIRECTORY}/pybind11-${PYBIND11_VERSION}.zip" CACHE STRING "URL to the Pybind11 repo") - ExternalProject_Add(lief_pybind11_project - URL ${PYBIND11_URL} - URL_HASH ${PYBIND11_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - INSTALL_COMMAND "") - add_dependencies(lief_pybind11 lief_pybind11_project) - ExternalProject_get_property(lief_pybind11_project SOURCE_DIR) - target_include_directories(lief_pybind11 SYSTEM INTERFACE "${SOURCE_DIR}/include") + set(LIEF_TARGET LIB_LIEF) endif() -message(STATUS "Python version: ${PYTHON_VERSION}") -message(STATUS "Python lib: ${PYTHON_LIBRARY}") -message(STATUS "Python include: ${PYTHON_INCLUDE_DIR}") -message(STATUS "Python interpreter: ${PYTHON_EXECUTABLE}") - - -# Define source files -set(LIEF_PYTHON_BASIC_SRC - "${CMAKE_CURRENT_SOURCE_DIR}/pyLIEF.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyUtils.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyExceptions.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyLogger.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyHash.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyObject.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyErr.cpp" - "${CMAKE_CURRENT_SOURCE_DIR}/encoding.cpp" -) - -list(APPEND LIEF_PYTHON_BASIC_SRC - "${CMAKE_CURRENT_SOURCE_DIR}/pyJson.cpp") +include(FetchContent) -set(LIEF_PYTHON_SRC - ${LIEF_PYTHON_BASIC_SRC} -) - -set(LIEF_PYTHON_BASIC_HDR - "${CMAKE_CURRENT_SOURCE_DIR}/pyErr.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyIterators.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/pyLIEF.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/enums_wrapper.hpp" - "${CMAKE_CURRENT_SOURCE_DIR}/encoding.hpp" -) - -set(LIEF_PYTHON_HDR - ${LIEF_PYTHON_BASIC_HDR} -) +if (LIEF_EXTERNAL_NANOBIND) + find_package(Python REQUIRED COMPONENTS Interpreter Development.Module) + find_package(nanobind REQUIRED) +else() + set(NANOBIND_VERSION 3.0.1) + set(NANOBIND_SHA256 SHA256=20111f42e0608e4e518bbe6095bdf64ef74d1d21bad22cb6f2aa3aff013e4443) + set(NANOBIND_URL "${THIRD_PARTY_DIRECTORY}/nanobind-${NANOBIND_VERSION}.zip" + CACHE STRING "URL to the Nanobind") + FetchContent_Declare(nanobind + URL ${NANOBIND_URL} + URL_HASH ${NANOBIND_SHA256} + ) + FetchContent_MakeAvailable(nanobind) + find_package(Python REQUIRED COMPONENTS Interpreter Development.Module) + find_package(nanobind REQUIRED PATHS ${nanobind_SOURCE_DIR}/cmake + NO_DEFAULT_PATH) +endif() -source_group("Header Files" FILES ${LIEF_PYTHON_BASIC_HDR}) -add_library(pyLIEF SHARED ${LIEF_PYTHON_SRC} ${LIEF_PYTHON_HDR}) +message(STATUS "Python version: ${Python_VERSION}") +message(STATUS "Python lib: ${Python_LIBRARIES}") +message(STATUS "Python include: ${Python_INCLUDE_DIRS}") +message(STATUS "Python interpreter: ${Python_EXECUTABLE}") -target_include_directories(pyLIEF PUBLIC - "${CMAKE_CURRENT_SOURCE_DIR}/" - "${CMAKE_CURRENT_SOURCE_DIR}/../../src" +set(NANOBIND_OPT + NB_STATIC + NOMINSIZE ) -target_include_directories(pyLIEF SYSTEM PRIVATE - "${PYTHON_INCLUDE_DIR}" - "${PYBIND11_SOURCE_DIR}/include") - -include("${CMAKE_CURRENT_SOURCE_DIR}/Abstract/CMakeLists.txt") - -if(LIEF_ELF) - include("${CMAKE_CURRENT_SOURCE_DIR}/ELF/CMakeLists.txt") +if (LIEF_PYTHON_STABLE_ABI) + message(STATUS "Stable ABI enabled") + list(APPEND NANOBIND_OPT STABLE_ABI) endif() -if(LIEF_PE) - include("${CMAKE_CURRENT_SOURCE_DIR}/PE/CMakeLists.txt") +if (LIEF_PYTHON_FREE_THREADED) + message(STATUS "Free threading enabled") + list(APPEND NANOBIND_OPT FREE_THREADED) endif() -if(LIEF_MACHO) - include("${CMAKE_CURRENT_SOURCE_DIR}/MachO/CMakeLists.txt") +if (LIEF_PYTHON_STATIC) + list(APPEND NANOBIND_OPT NB_EXT_STATIC ON) endif() -if(LIEF_OAT) - include("${CMAKE_CURRENT_SOURCE_DIR}/OAT/CMakeLists.txt") -endif() +nanobind_add_module( + pyLIEF + ${NANOBIND_OPT} -if(LIEF_DEX) - include("${CMAKE_CURRENT_SOURCE_DIR}/DEX/CMakeLists.txt") -endif() - -if(LIEF_VDEX) - include("${CMAKE_CURRENT_SOURCE_DIR}/VDEX/CMakeLists.txt") -endif() - -if(LIEF_ART) - include("${CMAKE_CURRENT_SOURCE_DIR}/ART/CMakeLists.txt") -endif() - -include("${CMAKE_CURRENT_SOURCE_DIR}/platforms/CMakeLists.txt") + NB_SUPPRESS_WARNINGS + src/pyLIEF.cpp +) -target_compile_features(pyLIEF PRIVATE cxx_attribute_deprecated) +add_subdirectory(src) set_target_properties(pyLIEF PROPERTIES POSITION_INDEPENDENT_CODE ON - CXX_STANDARD 14 + CXX_STANDARD 17 CXX_STANDARD_REQUIRED ON CXX_VISIBILITY_PRESET hidden C_VISIBILITY_PRESET hidden + PREFIX "" + OUTPUT_NAME "_lief" ) -if (MSVC) - set_property(TARGET pyLIEF PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) -endif() - -set_target_properties(pyLIEF PROPERTIES PYTHON_VERSION ${PYTHON_VERSION}) -set(PYLIEF_DEPS_LIBRARIES LIB_LIEF) -if(LIEF_COVERAGE) - target_compile_options(pyLIEF PRIVATE -g -O0 --coverage -fprofile-arcs -ftest-coverage) - set(PYLIEF_DEPS_LIBRARIES ${PYLIEF_DEPS_LIBRARIES} gcov) +if (LIEF_EXTRA_FLAGS) + target_compile_options(pyLIEF PRIVATE ${LIEF_EXTRA_FLAGS}) endif() +if (MSVC AND NOT CLANG_CL AND NOT LIEF_EXTERNAL_SPDLOG) + target_compile_definitions(pyLIEF PRIVATE FMT_UNICODE=0) +endif() -ADD_FLAG_IF_SUPPORTED("-Wno-macro-redefined" NO_MACRO_REDEFINED) -ADD_FLAG_IF_SUPPORTED("-Wno-deprecated-declarations" NO_DEPRECATED_DECLARATIONS) +target_link_libraries(pyLIEF PUBLIC ${LIEF_TARGET} lief_spdlog) -set_target_properties(pyLIEF PROPERTIES PREFIX "" OUTPUT_NAME "lief") -target_link_libraries(pyLIEF PRIVATE lief_pybind11) +target_precompile_headers(pyLIEF PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/src/pylief-pch.hpp +) if(APPLE) - set_target_properties(pyLIEF PROPERTIES - MACOSX_RPATH ON - LINK_FLAGS "-undefined dynamic_lookup " - ) + set_target_properties(pyLIEF PROPERTIES + MACOSX_RPATH ON + LINK_FLAGS "-undefined dynamic_lookup " + ) endif() -set_target_properties(pyLIEF PROPERTIES PREFIX "") -if (UNIX) - # Even on osx (c.f. EXT_SUFFIX from sysconfig) - set_target_properties(pyLIEF PROPERTIES SUFFIX ".so") + +if (UNIX OR MUSL) + if (LIEF_PYTHON_STATIC) + set_target_properties(pyLIEF PROPERTIES SUFFIX ".a") + else() + # Even on osx (c.f. EXT_SUFFIX from sysconfig) + set_target_properties(pyLIEF PROPERTIES SUFFIX ".so") + endif() elseif(WIN32) - set_target_properties(pyLIEF PROPERTIES SUFFIX ".pyd") + if (LIEF_PYTHON_STATIC) + set_target_properties(pyLIEF PROPERTIES SUFFIX ".lib") + else() + set_target_properties(pyLIEF PROPERTIES SUFFIX ".pyd") + endif() endif() -get_target_property(suffix pyLIEF SUFFIX) -set(LIEF_LIBRARY_NAME "lief${suffix}") if (WIN32) - set(PYLIEF_DEPS_LIBRARIES ${PYLIEF_DEPS_LIBRARIES} ${PYTHON_LIBRARIES}) + target_link_libraries(pyLIEF PUBLIC ${PYTHON_LIBRARIES} bcrypt) endif() -target_link_libraries(pyLIEF PUBLIC ${PYLIEF_DEPS_LIBRARIES}) +if (ANDROID) + target_link_libraries(pyLIEF PUBLIC Python::Module) +endif() +if(SKBUILD) + if(LIEF_PYTHON_EDITABLE) + install(TARGETS pyLIEF LIBRARY DESTINATION ${CMAKE_CURRENT_SOURCE_DIR}/lief) + else() + install(TARGETS pyLIEF LIBRARY DESTINATION ${SKBUILD_PLATLIB_DIR}/lief/) + endif() +endif() -if (CMAKE_BUILD_TYPE MATCHES Release AND UNIX AND NOT APPLE) - add_custom_command( - TARGET pyLIEF - COMMENT "Strip LIEF Python bindings" - POST_BUILD - COMMAND ${CMAKE_STRIP} --strip-all $ - ) +if (LIEF_ASAN) + target_link_libraries(pyLIEF INTERFACE libclang_rt.asan.so) endif() -if (CMAKE_BUILD_TYPE MATCHES Release AND APPLE) - add_custom_command( - TARGET pyLIEF - COMMENT "Strip LIEF Python bindings" - POST_BUILD - COMMAND ${CMAKE_STRIP} -x -S $ - ) +if (LIEF_TSAN) + target_link_libraries(pyLIEF INTERFACE libclang_rt.tsan.so) endif() -add_custom_command(TARGET pyLIEF POST_BUILD - COMMAND ${CMAKE_COMMAND} -E copy $ ${PROJECT_BINARY_DIR}/api/python/lief -) +if (LIEF_PYTHON_STATIC) + set(NANOBIND_TARGET nanobind-static) + if (LIEF_PYTHON_STABLE_ABI) + set(NANOBIND_TARGET nanobind-static-abi3) + endif() + install(TARGETS ${NANOBIND_TARGET} pyLIEF + DESTINATION lib/python-${Python_VERSION}) -if (MSVC) - add_custom_command(TARGET pyLIEF POST_BUILD - COMMAND ${CMAKE_COMMAND} -E copy $ ${CMAKE_CURRENT_BINARY_DIR} - ) -endif() + install( + DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/lief + DESTINATION lib/python/typing + FILES_MATCHING + REGEX "(.*).(pyi)$") + install(DIRECTORY ${NB_DIR}/include/ + DESTINATION include/) +endif() diff --git a/vendor/lief/api/python/DEX/CMakeLists.txt b/vendor/lief/api/python/DEX/CMakeLists.txt deleted file mode 100644 index 1b3a507..0000000 --- a/vendor/lief/api/python/DEX/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -set(LIEF_PYTHON_DEX_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyDEX.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFile.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyClass.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyField.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyMethod.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyMapList.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyMapItem.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyType.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyPrototype.cpp" -) - -set(LIEF_PYTHON_DEX_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyDEX.hpp") - -source_group("Source Files\\DEX" FILES ${LIEF_PYTHON_DEX_SRC}) -source_group("Header Files\\DEX" FILES ${LIEF_PYTHON_DEX_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_DEX_SRC}" "${LIEF_PYTHON_DEX_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../") - - diff --git a/vendor/lief/api/python/DEX/objects/pyClass.cpp b/vendor/lief/api/python/DEX/objects/pyClass.cpp deleted file mode 100644 index c736ecf..0000000 --- a/vendor/lief/api/python/DEX/objects/pyClass.cpp +++ /dev/null @@ -1,127 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/Class.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyIterators.hpp" -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Class::*)(void) const; - -template -using no_const_getter_t = T (Class::*)(void); - -template -using setter_t = void (Class::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ cls(m, "Class", "DEX Class representation"); - - init_ref_iterator(cls, "it_methods"); - init_ref_iterator(cls, "it_fields"); - - init_ref_iterator(cls, "it_named_methods"); - init_ref_iterator(cls, "it_named_fields"); - - cls - .def_property_readonly("fullname", - &Class::fullname, - "Mangled class name (e.g. ``Lcom/example/android/MyActivity;``)") - - .def_property_readonly("pretty_name", - &Class::pretty_name, - "Demangled class name (e.g. ``com.example.android.MyActivity``)") - - .def_property_readonly("name", - &Class::name, - "Class name (e.g. ``MyActivity``)") - - .def_property_readonly("source_filename", - &Class::source_filename, - "Original filename") - - .def_property_readonly("package_name", - &Class::package_name, - "Package Name (e.g. ``com.example.android``)") - - .def_property_readonly("has_parent", - &Class::has_parent, - "True if the current class extends another one") - - .def_property_readonly("parent", - static_cast>(&Class::parent), - "" RST_CLASS_REF(lief.DEX.Class) " parent class") - - .def_property_readonly("methods", - static_cast>(&Class::methods), - "Iterator over " RST_CLASS_REF(lief.DEX.Method) " implemented in this class") - - .def("get_method", - static_cast(&Class::methods), - "Iterator over " RST_CLASS_REF(lief.DEX.Method) " (s) having the given name", - "name"_a) - - .def_property_readonly("fields", - static_cast>(&Class::fields), - "Iterator over " RST_CLASS_REF(lief.DEX.Field) " in this class") - - .def("get_field", - static_cast(&Class::fields), - "Iterator over " RST_CLASS_REF(lief.DEX.Field) " (s) having the given name", - "name"_a) - - .def_property_readonly("access_flags", - static_cast>(&Class::access_flags), - "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) "") - - .def_property_readonly("dex2dex_info", - &Class::dex2dex_info, - "De-optimize information") - - .def_property_readonly("index", - &Class::index, - "Original index in the DEX class pool") - - .def("has", - static_cast(&Class::has), - "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present", - "flag"_a) - - - .def("__eq__", &Class::operator==) - .def("__ne__", &Class::operator!=) - .def("__hash__", - [] (const Class& cls) { - return Hash::hash(cls); - }) - - .def("__str__", - [] (const Class& cls) { - std::ostringstream stream; - stream << cls; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyCodeInfo.cpp b/vendor/lief/api/python/DEX/objects/pyCodeInfo.cpp deleted file mode 100644 index d5740e5..0000000 --- a/vendor/lief/api/python/DEX/objects/pyCodeInfo.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/CodeInfo.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (CodeInfo::*)(void) const; - -template -using no_const_getter_t = T (CodeInfo::*)(void); - -template -using setter_t = void (CodeInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "CodeInfo", "DEX CodeInfo representation") - - .def("__eq__", &CodeInfo::operator==) - .def("__ne__", &CodeInfo::operator!=) - .def("__hash__", - [] (const CodeInfo& cinfo) { - return Hash::hash(cinfo); - }) - - .def("__str__", - [] (const CodeInfo& cinfo) { - std::ostringstream stream; - stream << cinfo; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyField.cpp b/vendor/lief/api/python/DEX/objects/pyField.cpp deleted file mode 100644 index 6d64ece..0000000 --- a/vendor/lief/api/python/DEX/objects/pyField.cpp +++ /dev/null @@ -1,72 +0,0 @@ -#include "LIEF/DEX/Field.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Field::*)(void) const; - -template -using no_const_getter_t = T (Field::*)(void); - -template -using setter_t = void (Field::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "Field", "DEX Field representation") - .def_property_readonly("name", - &Field::name, - "Field's name") - - .def_property_readonly("index", - &Field::index, - "Original DEX file index of the field") - - .def_property_readonly("has_class", - &Field::has_class, - "True if a class is associated with this field") - - .def_property_readonly("cls", - static_cast>(&Field::cls), - "" RST_CLASS_REF(lief.DEX.Class) " associated with this field") - - .def_property_readonly("is_static", - &Field::is_static, - "True if the field is static") - - .def_property_readonly("type", - static_cast>(&Field::type), - "" RST_CLASS_REF(lief.DEX.Type) " of this field", py::return_value_policy::reference) - - .def_property_readonly("access_flags", - static_cast>(&Field::access_flags), - "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) "") - - .def("has", - static_cast(&Field::has), - "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present", - "flag"_a) - - .def("__eq__", &Field::operator==) - .def("__ne__", &Field::operator!=) - .def("__hash__", - [] (const Field& fld) { - return Hash::hash(fld); - }) - - .def("__str__", - [] (const Field& fld) { - std::ostringstream stream; - stream << fld; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyFile.cpp b/vendor/lief/api/python/DEX/objects/pyFile.cpp deleted file mode 100644 index 03cdb0a..0000000 --- a/vendor/lief/api/python/DEX/objects/pyFile.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/File.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyIterators.hpp" -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (File::*)(void) const; - -template -using no_const_getter_t = T (File::*)(void); - -template -using setter_t = void (File::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ file(m, "File", "DEX File representation"); - - init_ref_iterator(file, "it_classes"); - init_ref_iterator(file, "it_methods"); - init_ref_iterator(file, "it_strings"); - init_ref_iterator(file, "it_types"); - init_ref_iterator(file, "it_prototypes"); - init_ref_iterator(file, "it_fields"); - - file - .def_property_readonly("version", - &File::version, - "Dex version") - - .def_property_readonly("header", - static_cast>(&File::header), - "Dex File " RST_CLASS_REF(lief.DEX.Header) "", - py::return_value_policy::reference) - - .def_property_readonly("classes", - static_cast>(&File::classes), - "Iterator over Dex " RST_CLASS_REF(lief.DEX.Class) "") - - .def("has_class", - &File::has_class, - "Check if a class with a name given in parameter exists", - "classname"_a) - - .def("get_class", - static_cast(&File::get_class), - "classname"_a, - py::return_value_policy::reference) - - .def("get_class", - static_cast(&File::get_class), - "classname"_a, - py::return_value_policy::reference) - - .def_property_readonly("methods", - static_cast>(&File::methods), - "Iterator over Dex " RST_CLASS_REF(lief.DEX.Method) "") - - .def_property_readonly("fields", - static_cast>(&File::fields), - "Iterator over Dex " RST_CLASS_REF(lief.DEX.Field) "") - - .def_property_readonly("strings", - static_cast>(&File::strings), - "Iterator over Dex strings") - - .def_property_readonly("types", - static_cast>(&File::types), - "Iterator over Dex " RST_CLASS_REF(lief.DEX.Type) "") - - .def_property_readonly("prototypes", - static_cast>(&File::prototypes), - "Iterator over Dex " RST_CLASS_REF(lief.DEX.Prototype) "") - - .def_property_readonly("map", - static_cast>(&File::map), - "Dex " RST_CLASS_REF(lief.DEX.MapList) "") - - .def("raw", - &File::raw, - "Original raw file", - "deoptimize"_a = true) - - .def_property("name", - static_cast>(&File::name), - static_cast>(&File::name), - "Name of the dex file") - - .def_property("location", - static_cast>(&File::location), - static_cast>(&File::location), - "Original location of the dex file") - - //.def_property_readonly("dex2dex_info", - // &File::dex2dex_info) - - .def_property_readonly("dex2dex_json_info", - &File::dex2dex_json_info) - - .def("save", - &File::save, - "Save the **original** file into the file given in first parameter", - "output"_a = "", "deoptimize"_a = true) - - .def("__eq__", &File::operator==) - .def("__ne__", &File::operator!=) - .def("__hash__", - [] (const File& file) { - return Hash::hash(file); - }) - - .def("__str__", - [] (const File& file) { - std::ostringstream stream; - stream << file; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyHeader.cpp b/vendor/lief/api/python/DEX/objects/pyHeader.cpp deleted file mode 100644 index 9df26eb..0000000 --- a/vendor/lief/api/python/DEX/objects/pyHeader.cpp +++ /dev/null @@ -1,122 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/Header.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - -template<> -void create
(py::module& m) { - - py::class_(m, "Header", "DEX Header") - - .def_property_readonly("magic", - static_cast>(&Header::magic), - "Magic value") - - .def_property_readonly("checksum", - static_cast>(&Header::checksum), - "Checksum value of the rest of the file (without " RST_ATTR_REF(lief.DEX.Header.magic) ")") - - .def_property_readonly("signature", - static_cast>(&Header::signature), - "SHA-1 signature of the rest of the file (without " RST_ATTR_REF(lief.DEX.Header.magic) " and " RST_ATTR_REF(lief.DEX.Header.checksum) ")") - - .def_property_readonly("file_size", - static_cast>(&Header::file_size), - "Size of the current DEX file") - - .def_property_readonly("header_size", - static_cast>(&Header::header_size), - "Size of this header. Should be ``0x70``") - - .def_property_readonly("endian_tag", - static_cast>(&Header::endian_tag), - "Endianness tag. Should be ``ENDIAN_CONSTANT``") - - .def_property_readonly("map_offset", - static_cast>(&Header::map), - "Offset from the start of the file to the map item") - - .def_property_readonly("strings", - static_cast>(&Header::strings), - "String identifiers") - - .def_property_readonly("link", - static_cast>(&Header::link), - "Link (raw data)") - - .def_property_readonly("types", - static_cast>(&Header::types), - "Type identifiers") - - .def_property_readonly("prototypes", - static_cast>(&Header::prototypes), - "Prototypes identifiers") - - .def_property_readonly("fields", - static_cast>(&Header::fields), - "Fields identifiers") - - .def_property_readonly("methods", - static_cast>(&Header::methods), - "Methods identifiers") - - .def_property_readonly("classes", - static_cast>(&Header::classes), - "Classess identifiers") - - .def_property_readonly("data", - static_cast>(&Header::data), - "Raw data. Should be align on 32-bits") - - .def_property_readonly("nb_classes", - static_cast>(&Header::nb_classes), - "Number of classes in the current DEX") - - .def_property_readonly("nb_methods", - static_cast>(&Header::nb_methods), - "Number of methods in the current DEX") - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - .def("__str__", - [] (const Header& header) { - std::ostringstream stream; - stream << header; - return stream.str(); - }); - -} - -} -} - - diff --git a/vendor/lief/api/python/DEX/objects/pyMapItem.cpp b/vendor/lief/api/python/DEX/objects/pyMapItem.cpp deleted file mode 100644 index 0116a88..0000000 --- a/vendor/lief/api/python/DEX/objects/pyMapItem.cpp +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/MapItem.hpp" -#include "LIEF/DEX/hash.hpp" -#include "LIEF/DEX/EnumToString.hpp" - -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -#define PY_ENUM(x) to_string(x), x - -template -using getter_t = T (MapItem::*)(void) const; - -template -using no_const_getter_t = T (MapItem::*)(void); - -template -using setter_t = void (MapItem::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ mapitem(m, "MapItem", "DEX MapItem representation"); - - py::enum_(mapitem, "TYPES") - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::HEADER)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::STRING_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::TYPE_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::PROTO_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::FIELD_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::METHOD_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CLASS_DEF)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CALL_SITE_ID)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::METHOD_HANDLE)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::MAP_LIST)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::TYPE_LIST)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION_SET_REF_LIST)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION_SET)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CLASS_DATA)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CODE)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::STRING_DATA)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::DEBUG_INFO)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ENCODED_ARRAY)) - .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATIONS_DIRECTORY)); - - mapitem - .def_property_readonly("type", - static_cast>(&MapItem::type), - "" RST_CLASS_REF(lief.DEX.MapItem.TYPES) " of the item") - - .def_property_readonly("offset", - static_cast>(&MapItem::offset), - "Offset from the start of the file to the items in question") - - .def_property_readonly("size", - static_cast>(&MapItem::size), - "count of the number of items to be found at the indicated offset") - - .def("__eq__", &MapItem::operator==) - .def("__ne__", &MapItem::operator!=) - .def("__hash__", - [] (const MapItem& mlist) { - return Hash::hash(mlist); - }) - - .def("__str__", - [] (const MapItem& mlist) { - std::ostringstream stream; - stream << mlist; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyMapList.cpp b/vendor/lief/api/python/DEX/objects/pyMapList.cpp deleted file mode 100644 index 1dfc114..0000000 --- a/vendor/lief/api/python/DEX/objects/pyMapList.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/MapList.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (MapList::*)(void) const; - -template -using no_const_getter_t = T (MapList::*)(void); - -template -using setter_t = void (MapList::*)(T); - - -template<> -void create(py::module& m) { - - init_ref_iterator(m, "lief.DEX.MapList.it_items_t"); - - py::class_(m, "MapList", "DEX MapList representation") - .def_property_readonly("items", - static_cast>(&MapList::items), - "Iterator over " RST_CLASS_REF(lief.DEX.MapItem) "") - - .def("has", - &MapList::has, - "Check if the given " RST_CLASS_REF(lief.DEX.MapItem.TYPES) " is present", - "type"_a) - - .def("get", - static_cast(&MapList::get), - "Return the " RST_CLASS_REF(lief.DEX.MapItem.TYPES) " from " - "the given " RST_CLASS_REF(lief.DEX.MapItem.TYPES) "", - "type"_a, - py::return_value_policy::reference) - - .def("__getitem__", - static_cast(&MapList::get)) - - .def("__eq__", &MapList::operator==) - .def("__ne__", &MapList::operator!=) - .def("__hash__", - [] (const MapList& mlist) { - return Hash::hash(mlist); - }) - - .def("__str__", - [] (const MapList& mlist) { - std::ostringstream stream; - stream << mlist; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyMethod.cpp b/vendor/lief/api/python/DEX/objects/pyMethod.cpp deleted file mode 100644 index 2811747..0000000 --- a/vendor/lief/api/python/DEX/objects/pyMethod.cpp +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/Method.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Method::*)(void) const; - -template -using no_const_getter_t = T (Method::*)(void); - -template -using setter_t = void (Method::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "Method", "DEX Method representation") - .def_property_readonly("name", - &Method::name, - "Method's name") - - .def_property_readonly("index", - &Method::index, - "Original DEX file index of the method") - - .def_property_readonly("has_class", - &Method::has_class, - "True if a class is associated with this method") - - .def_property_readonly("cls", - static_cast>(&Method::cls), - "" RST_CLASS_REF(lief.DEX.Class) " associated with this method") - - .def_property_readonly("code_offset", - static_cast>(&Method::code_offset), - "Offset to the Dalvik Bytecode") - - .def_property_readonly("bytecode", - static_cast>(&Method::bytecode), - "Dalvik Bytecode as a list of bytes") - - .def_property_readonly("is_virtual", - &Method::is_virtual, - "True if the method is a virtual (not **private**, **static**, **final**, **constructor**)") - - .def_property_readonly("prototype", - static_cast>(&Method::prototype), - "" RST_CLASS_REF(lief.DEX.Prototype) " of this method") - - .def_property_readonly("access_flags", - static_cast>(&Method::access_flags), - "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) "") - - .def("has", - static_cast(&Method::has), - "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present", - "flag"_a) - - .def("insert_dex2dex_info", - &Method::insert_dex2dex_info, - "Insert de-optimization information", - "pc"_a, "index"_a) - - .def("__eq__", &Method::operator==) - .def("__ne__", &Method::operator!=) - .def("__hash__", - [] (const Method& cls) { - return Hash::hash(cls); - }) - - .def("__str__", - [] (const Method& cls) { - std::ostringstream stream; - stream << cls; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyParser.cpp b/vendor/lief/api/python/DEX/objects/pyParser.cpp deleted file mode 100644 index 7f360ce..0000000 --- a/vendor/lief/api/python/DEX/objects/pyParser.cpp +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyDEX.hpp" - -#include "LIEF/DEX/Parser.hpp" - -#include - -namespace LIEF { -namespace DEX { - -template<> -void create(py::module& m) { - - m.def("parse", - static_cast (*) (const std::string&)>(&Parser::parse), - "Parse the given filename and return a " RST_CLASS_REF(lief.DEX.File) " object", - "filename"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast(*)(std::vector, const std::string&)>(&Parser::parse), - "Parse the given raw data and return a " RST_CLASS_REF(lief.DEX.File) " object", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::DEX::Parser::parse(std::move(raw), name); - }, - "io"_a, "name"_a = "", - py::return_value_policy::take_ownership); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyPrototype.cpp b/vendor/lief/api/python/DEX/objects/pyPrototype.cpp deleted file mode 100644 index ca47d91..0000000 --- a/vendor/lief/api/python/DEX/objects/pyPrototype.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/Prototype.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "pyDEX.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Prototype::*)(void) const; - -template -using no_const_getter_t = T (Prototype::*)(void); - -template -using setter_t = void (Prototype::*)(T); - - -template<> -void create(py::module& m) { - - init_ref_iterator(m, "lief.DEX.Prototype.it_params"); - - py::class_(m, "Prototype", "DEX Prototype representation") - .def_property_readonly("return_type", - static_cast>(&Prototype::return_type), - "" RST_CLASS_REF(lief.DEX.Type) " returned", - py::return_value_policy::reference) - - .def_property_readonly("parameters_type", - static_cast>(&Prototype::parameters_type), - "Iterator over parameters " RST_CLASS_REF(lief.DEX.Type) "") - - .def("__eq__", &Prototype::operator==) - .def("__ne__", &Prototype::operator!=) - .def("__hash__", - [] (const Prototype& ptype) { - return Hash::hash(ptype); - }) - - .def("__str__", - [] (const Prototype& ptype) { - std::ostringstream stream; - stream << ptype; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/objects/pyType.cpp b/vendor/lief/api/python/DEX/objects/pyType.cpp deleted file mode 100644 index 1247c24..0000000 --- a/vendor/lief/api/python/DEX/objects/pyType.cpp +++ /dev/null @@ -1,125 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/DEX/Type.hpp" -#include "LIEF/DEX/hash.hpp" - -#include "LIEF/DEX/EnumToString.hpp" - -#include "pyDEX.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace DEX { - -template -using getter_t = T (Type::*)(void) const; - -template -using no_const_getter_t = T (Type::*)(void); - -template -using setter_t = void (Type::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ pytype(m, "Type", "DEX Type representation"); - - py::enum_(pytype, "TYPES") - .value(PY_ENUM(Type::TYPES::UNKNOWN)) - .value(PY_ENUM(Type::TYPES::ARRAY)) - .value(PY_ENUM(Type::TYPES::PRIMITIVE)) - .value(PY_ENUM(Type::TYPES::CLASS)); - - py::enum_(pytype, "PRIMITIVES") - .value(PY_ENUM(Type::PRIMITIVES::VOID_T)) - .value(PY_ENUM(Type::PRIMITIVES::BOOLEAN)) - .value(PY_ENUM(Type::PRIMITIVES::BYTE)) - .value(PY_ENUM(Type::PRIMITIVES::SHORT)) - .value(PY_ENUM(Type::PRIMITIVES::CHAR)) - .value(PY_ENUM(Type::PRIMITIVES::INT)) - .value(PY_ENUM(Type::PRIMITIVES::LONG)) - .value(PY_ENUM(Type::PRIMITIVES::FLOAT)) - .value(PY_ENUM(Type::PRIMITIVES::DOUBLE)); - - - pytype - .def_property_readonly("type", - &Type::type, - "" RST_CLASS_REF(lief.DEX.Type.TYPES) " of this object") - - .def_property_readonly("value", - [] (Type& type) -> py::object { - switch (type.type()) { - case Type::TYPES::ARRAY: - { - return py::cast(type.array()); - } - - case Type::TYPES::CLASS: - { - return py::cast(type.cls(), py::return_value_policy::reference); - } - - case Type::TYPES::PRIMITIVE: - { - return py::cast(type.primitive()); - } - - case Type::TYPES::UNKNOWN: - default: - { - return py::none{}; - } - } - }, - "Depending on the " RST_CLASS_REF(lief.DEX.Type.TYPES) ", return " - " " RST_CLASS_REF(lief.DEX.Class) " or " RST_CLASS_REF(lief.DEX.Type.PRIMITIVES) " or array", - py::return_value_policy::reference) - - .def_property_readonly("dim", - &Type::dim, - "If the current type is an array, return its dimension otherwise 0") - - .def_property_readonly("underlying_array_type", - static_cast>(&Type::underlying_array_type), - "Underlying type of the array", - py::return_value_policy::reference) - - .def_static("pretty_name", - &Type::pretty_name, - "Pretty name of primitives", - "primitive"_a) - - .def("__eq__", &Type::operator==) - .def("__ne__", &Type::operator!=) - .def("__hash__", - [] (const Type& type) { - return Hash::hash(type); - }) - - .def("__str__", - [] (const Type& type) { - std::ostringstream stream; - stream << type; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/DEX/pyDEX.cpp b/vendor/lief/api/python/DEX/pyDEX.cpp deleted file mode 100644 index 8016053..0000000 --- a/vendor/lief/api/python/DEX/pyDEX.cpp +++ /dev/null @@ -1,45 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyDEX.hpp" - - -namespace LIEF { -namespace DEX { -void init_python_module(py::module& m) { - py::module LIEF_DEX_module = m.def_submodule("DEX", "Python API for DEX format"); - - init_enums(LIEF_DEX_module); - init_objects(LIEF_DEX_module); - init_utils(LIEF_DEX_module); -} - - -void init_objects(py::module& m) { - CREATE(Parser, m); - CREATE(File, m); - CREATE(Header, m); - CREATE(Class, m); - CREATE(Method, m); - CREATE(Field, m); - CREATE(Prototype, m); - CREATE(Type, m); - CREATE(MapList, m); - CREATE(MapItem, m); - CREATE(CodeInfo, m); -} - -} -} diff --git a/vendor/lief/api/python/DEX/pyDEX.hpp b/vendor/lief/api/python/DEX/pyDEX.hpp deleted file mode 100644 index b742e97..0000000 --- a/vendor/lief/api/python/DEX/pyDEX.hpp +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_DEX_H_ -#define PY_LIEF_DEX_H_ - -#include "LIEF/DEX.hpp" - -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -namespace LIEF { -namespace DEX { - -template -void create(py::module&); - -void init_python_module(py::module& m); - -void init_objects(py::module&); - -void init_enums(py::module&); - -void init_utils(py::module&); - - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(File); -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(Class); -SPECIALIZE_CREATE(Method); -SPECIALIZE_CREATE(Field); -SPECIALIZE_CREATE(Prototype); -SPECIALIZE_CREATE(Type); -SPECIALIZE_CREATE(MapList); -SPECIALIZE_CREATE(MapItem); -SPECIALIZE_CREATE(CodeInfo); - -} -} - - -#endif diff --git a/vendor/lief/api/python/DEX/pyEnums.cpp b/vendor/lief/api/python/DEX/pyEnums.cpp deleted file mode 100644 index 30f332f..0000000 --- a/vendor/lief/api/python/DEX/pyEnums.cpp +++ /dev/null @@ -1,50 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyDEX.hpp" -#include "LIEF/DEX/enums.hpp" -#include "LIEF/DEX/EnumToString.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace DEX { -void init_enums(py::module& m) { - - py::enum_(m, "ACCESS_FLAGS") - .value(PY_ENUM(ACCESS_FLAGS::ACC_UNKNOWN)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_PUBLIC)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_PRIVATE)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_PROTECTED)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_STATIC)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_FINAL)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_SYNCHRONIZED)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_VOLATILE)) - .value("BRIDGE", ACCESS_FLAGS::ACC_BRIDGE) - .value("TRANSIENT", ACCESS_FLAGS::ACC_TRANSIENT) - .value(PY_ENUM(ACCESS_FLAGS::ACC_VARARGS)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_NATIVE)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_INTERFACE)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_ABSTRACT)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_STRICT)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_SYNTHETIC)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_ANNOTATION)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_ENUM)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_CONSTRUCTOR)) - .value(PY_ENUM(ACCESS_FLAGS::ACC_DECLARED_SYNCHRONIZED)); - -} -} -} diff --git a/vendor/lief/api/python/DEX/pyUtils.cpp b/vendor/lief/api/python/DEX/pyUtils.cpp deleted file mode 100644 index 997d75d..0000000 --- a/vendor/lief/api/python/DEX/pyUtils.cpp +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyDEX.hpp" - -#include "LIEF/DEX/utils.hpp" - -namespace LIEF { -namespace DEX { - -void init_utils(py::module& m) { - - m.def("is_dex", - static_cast(&is_dex), - "Check if the **file** given in parameter is a DEX", - "path"_a); - - m.def("is_dex", - static_cast&)>(&is_dex), - "Check if the **raw data** given in parameter is a DEX", - "raw"_a); - - m.def("version", - static_cast(&version), - "Return the DEX version of the **file** given in parameter", - "file"_a); - - m.def("version", - static_cast&)>(&version), - "Return the DEX version of the **raw data** given in parameter", - "raw"_a); - -} - -} -} - diff --git a/vendor/lief/api/python/ELF/CMakeLists.txt b/vendor/lief/api/python/ELF/CMakeLists.txt deleted file mode 100644 index bdf609c..0000000 --- a/vendor/lief/api/python/ELF/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -set(LIEF_PYTHON_ELF_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyELF.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolVersionAuxRequirement.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolVersion.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntryRunPath.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolVersionRequirement.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBinary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolVersionDefinition.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolVersionAux.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntryArray.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntryFlags.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySegment.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySection.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntryRpath.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocation.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicSharedObject.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicEntryLibrary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyGnuHash.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySysvHash.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBuilder.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pySizes.cpp" -) - -set(LIEF_PYTHON_ELF_NOTE - "${CMAKE_CURRENT_LIST_DIR}/objects/pyNote.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyNoteDetails.cpp" -) - -list(APPEND LIEF_PYTHON_ELF_SRC ${LIEF_PYTHON_ELF_NOTE}) - -include("${CMAKE_CURRENT_LIST_DIR}/objects/NoteDetails/CMakeLists.txt") - -set(LIEF_PYTHON_ELF_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyELF.hpp") - -source_group("Source Files\\ELF" FILES ${LIEF_PYTHON_ELF_SRC}) -source_group("Header Files\\ELF" FILES ${LIEF_PYTHON_ELF_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ELF_SRC}" "${LIEF_PYTHON_ELF_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") - - diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/CMakeLists.txt b/vendor/lief/api/python/ELF/objects/NoteDetails/CMakeLists.txt deleted file mode 100644 index 2f6b234..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -set(LIEF_PYTHON_ELF_NOTE_DETAILS_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyAndroidNote.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyNoteAbi.cpp" -) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ELF_NOTE_DETAILS_SRC}") - -include("${CMAKE_CURRENT_LIST_DIR}/core/CMakeLists.txt") - - - diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/CMakeLists.txt b/vendor/lief/api/python/ELF/objects/NoteDetails/core/CMakeLists.txt deleted file mode 100644 index 6040dae..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -set(LIEF_PYTHON_ELF_NOTE_DETAILS_CORE - "${CMAKE_CURRENT_LIST_DIR}/pyCorePrPsInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyCoreFile.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyCoreFileEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyCorePrStatus.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyCoreAuxv.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyCoreSigInfo.cpp" -) -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ELF_NOTE_DETAILS_CORE}") - - - diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp deleted file mode 100644 index a3a1bb6..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp +++ /dev/null @@ -1,141 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/core/CoreAuxv.hpp" - -#include "LIEF/ELF/EnumToString.hpp" - -#include "enums_wrapper.hpp" - -#define PY_ENUM(x) LIEF::ELF::to_string(x), x - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (CoreAuxv::*)(void) const; - -template -using setter_t = void (CoreAuxv::*)(T); - -template<> -void create(py::module& m) { - - py::class_ cls(m, "CoreAuxv"); - - cls - .def_property("values", - static_cast>(&CoreAuxv::values), - static_cast>(&CoreAuxv::values), - "Current values as a dictionarry for which keys are AUXV types") - - .def("get", - [] (const CoreAuxv& status, AUX_TYPE atype) -> py::object { - bool error; - uint64_t val = status.get(atype, &error); - if (error) { - return py::none(); - } - return py::int_(val); - }, - "Return the type value", - "type"_a) - - .def("set", - &CoreAuxv::set, - "Set type value", - "type"_a, "value"_a) - - .def("has", - &CoreAuxv::has, - "Check if a value is associated with the given type", - "type"_a) - - .def("__getitem__", - &CoreAuxv::operator[], - "", - py::return_value_policy::copy) - - .def("__setitem__", - [] (CoreAuxv& status, AUX_TYPE atype, uint64_t val) { - status.set(atype, val); - }, - "") - - .def("__contains__", - &CoreAuxv::has, - "") - - .def("__eq__", &CoreAuxv::operator==) - .def("__ne__", &CoreAuxv::operator!=) - .def("__hash__", - [] (const CoreAuxv& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const CoreAuxv& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); - - - LIEF::enum_(cls, "TYPES") - .value(PY_ENUM(AUX_TYPE::AT_NULL)) - .value(PY_ENUM(AUX_TYPE::AT_IGNORE)) - .value(PY_ENUM(AUX_TYPE::AT_EXECFD)) - .value(PY_ENUM(AUX_TYPE::AT_PHDR)) - .value(PY_ENUM(AUX_TYPE::AT_PHENT)) - .value(PY_ENUM(AUX_TYPE::AT_PHNUM)) - .value(PY_ENUM(AUX_TYPE::AT_PAGESZ)) - .value(PY_ENUM(AUX_TYPE::AT_BASE)) - .value(PY_ENUM(AUX_TYPE::AT_FLAGS)) - .value(PY_ENUM(AUX_TYPE::AT_ENTRY)) - .value(PY_ENUM(AUX_TYPE::AT_NOTELF)) - .value(PY_ENUM(AUX_TYPE::AT_UID)) - .value(PY_ENUM(AUX_TYPE::AT_EUID)) - .value(PY_ENUM(AUX_TYPE::AT_GID)) - .value(PY_ENUM(AUX_TYPE::AT_EGID)) - .value(PY_ENUM(AUX_TYPE::AT_CLKTCK)) - .value(PY_ENUM(AUX_TYPE::AT_PLATFORM)) - .value(PY_ENUM(AUX_TYPE::AT_HWCAP)) - .value(PY_ENUM(AUX_TYPE::AT_HWCAP2)) - .value(PY_ENUM(AUX_TYPE::AT_FPUCW)) - .value(PY_ENUM(AUX_TYPE::AT_DCACHEBSIZE)) - .value(PY_ENUM(AUX_TYPE::AT_ICACHEBSIZE)) - .value(PY_ENUM(AUX_TYPE::AT_UCACHEBSIZE)) - .value(PY_ENUM(AUX_TYPE::AT_IGNOREPPC)) - .value(PY_ENUM(AUX_TYPE::AT_SECURE)) - .value(PY_ENUM(AUX_TYPE::AT_BASE_PLATFORM)) - .value(PY_ENUM(AUX_TYPE::AT_RANDOM)) - .value(PY_ENUM(AUX_TYPE::AT_EXECFN)) - .value(PY_ENUM(AUX_TYPE::AT_SYSINFO)) - .value(PY_ENUM(AUX_TYPE::AT_SYSINFO_EHDR)) - .value(PY_ENUM(AUX_TYPE::AT_L1I_CACHESHAPE)) - .value(PY_ENUM(AUX_TYPE::AT_L1D_CACHESHAPE)); - - -} -} // namespace ELF -} // namespace LIEF diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFile.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFile.cpp deleted file mode 100644 index e0ac513..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFile.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (CoreFile::*)(void) const; - -template -using setter_t = void (CoreFile::*)(T); - -template<> -void create(py::module& m) { - - py::bind_vector(m, "CoreFile.files_t"); - - py::class_(m, "CoreFile") - - .def_property("files", - static_cast>(&CoreFile::files), - static_cast>(&CoreFile::files), - "List of files mapped in core. (list of " RST_CLASS_REF(lief.ELF.CoreFileEntry) ")") - - .def("__len__", - &CoreFile::count, - "Number of files mapped in core" - ) - - .def("__iter__", - [] (const CoreFile& f) { - return py::make_iterator(std::begin(f), std::end(f)); - }, - py::keep_alive<0, 1>()) - - .def("__eq__", &CoreFile::operator==) - .def("__ne__", &CoreFile::operator!=) - .def("__hash__", - [] (const CoreFile& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const CoreFile& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFileEntry.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFileEntry.cpp deleted file mode 100644 index 74d9d49..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreFileEntry.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include - -#include "pyELF.hpp" -#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" - -namespace LIEF { -namespace ELF { - -template<> -void create(py::module& m) { - - py::class_(m, "CoreFileEntry") - - .def_readwrite("start", &CoreFileEntry::start, - "Start address of mapped file") - - .def_readwrite("end", &CoreFileEntry::end, - "End address of mapped file") - - .def_readwrite("file_ofs", &CoreFileEntry::file_ofs, - "Offset (in core) of mapped file") - - .def_readwrite("path", &CoreFileEntry::path, - "Path of mapped file") - - - .def("__str__", - [] (const CoreFileEntry& entry) - { - std::ostringstream stream; - stream << entry; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp deleted file mode 100644 index bcd9bea..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp +++ /dev/null @@ -1,104 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/core/CorePrPsInfo.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (CorePrPsInfo::*)(void) const; - -template -using setter_t = void (CorePrPsInfo::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "CorePrPsInfo") - - .def_property("file_name", - static_cast>(&CorePrPsInfo::file_name), - static_cast>(&CorePrPsInfo::file_name), - "Process file name" - ) - - .def_property("flags", - static_cast>(&CorePrPsInfo::flags), - static_cast>(&CorePrPsInfo::flags), - "Process flags" - ) - - .def_property("uid", - static_cast>(&CorePrPsInfo::uid), - static_cast>(&CorePrPsInfo::uid), - "Process User ID" - ) - - .def_property("gid", - static_cast>(&CorePrPsInfo::gid), - static_cast>(&CorePrPsInfo::gid), - "Process Group ID" - ) - - .def_property("pid", - static_cast>(&CorePrPsInfo::pid), - static_cast>(&CorePrPsInfo::pid), - "Process ID" - ) - - .def_property("ppid", - static_cast>(&CorePrPsInfo::ppid), - static_cast>(&CorePrPsInfo::ppid), - "Process parent ID" - ) - - .def_property("pgrp", - static_cast>(&CorePrPsInfo::pgrp), - static_cast>(&CorePrPsInfo::pgrp), - "Process session group ID" - ) - - .def_property("sid", - static_cast>(&CorePrPsInfo::sid), - static_cast>(&CorePrPsInfo::sid), - "Process session ID" - ) - - .def("__eq__", &CorePrPsInfo::operator==) - .def("__ne__", &CorePrPsInfo::operator!=) - .def("__hash__", - [] (const CorePrPsInfo& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const CorePrPsInfo& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp deleted file mode 100644 index 703417e..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/core/CorePrStatus.hpp" - -#include "LIEF/ELF/EnumToString.hpp" - -#include "enums_wrapper.hpp" - -#define PY_ENUM(x) LIEF::ELF::to_string(x), x - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (CorePrStatus::*)(void) const; - -template -using setter_t = void (CorePrStatus::*)(T); - -template<> -void create(py::module& m) { - - py::class_ cls(m, "CorePrStatus"); - - py::class_(cls, "timeval") - .def_readwrite("sec", &CorePrStatus::timeval_t::sec) - .def_readwrite("usec", &CorePrStatus::timeval_t::usec); - - py::class_(cls, "siginfo") - .def_readwrite("sicode", &CorePrStatus::siginfo_t::si_code) - .def_readwrite("errno", &CorePrStatus::siginfo_t::si_errno) - .def_readwrite("signo", &CorePrStatus::siginfo_t::si_signo); - - cls - .def_property("siginfo", - static_cast>(&CorePrStatus::siginfo), - static_cast>(&CorePrStatus::siginfo), - "Info associated with the signal") - - .def_property("current_sig", - static_cast>(&CorePrStatus::current_sig), - static_cast>(&CorePrStatus::current_sig), - "Current Signal") - - .def_property("sigpend", - static_cast>(&CorePrStatus::sigpend), - static_cast>(&CorePrStatus::sigpend), - "Set of pending signals") - - .def_property("sighold", - static_cast>(&CorePrStatus::sighold), - static_cast>(&CorePrStatus::sighold), - "Set of held signals") - - .def_property("pid", - static_cast>(&CorePrStatus::pid), - static_cast>(&CorePrStatus::pid), - "Process ID") - - .def_property("ppid", - static_cast>(&CorePrStatus::ppid), - static_cast>(&CorePrStatus::ppid), - "Process parent ID") - - .def_property("pgrp", - static_cast>(&CorePrStatus::pgrp), - static_cast>(&CorePrStatus::pgrp), - "Process group ID") - - .def_property("sid", - static_cast>(&CorePrStatus::sid), - static_cast>(&CorePrStatus::sid), - "Process session ID") - - .def_property("utime", - static_cast>(&CorePrStatus::utime), - static_cast>(&CorePrStatus::utime), - "User time (" RST_CLASS_REF(lief.ELF.CorePrStatus.timeval) ")") - - .def_property("utime", - static_cast>(&CorePrStatus::utime), - static_cast>(&CorePrStatus::utime), - "User time (" RST_CLASS_REF(lief.ELF.CorePrStatus.timeval) ")") - - .def_property("stime", - static_cast>(&CorePrStatus::stime), - static_cast>(&CorePrStatus::stime), - "System time (" RST_CLASS_REF(lief.ELF.CorePrStatus.timeval) ")") - - .def_property("cutime", - static_cast>(&CorePrStatus::cutime), - static_cast>(&CorePrStatus::cutime), - "Cumulative user time (" RST_CLASS_REF(lief.ELF.CorePrStatus.timeval) ")") - - .def_property("cstime", - static_cast>(&CorePrStatus::cstime), - static_cast>(&CorePrStatus::cstime), - "Cumulative system time (" RST_CLASS_REF(lief.ELF.CorePrStatus.timeval) ")") - - .def_property("register_context", - static_cast>(&CorePrStatus::reg_context), - static_cast>(&CorePrStatus::reg_context), - "Current registers state as a dictionary where the keys are " - RST_CLASS_REF(lief.ELF.CorePrStatus.REGISTERS) " and the values the register's value") - - .def("get", - [] (const CorePrStatus& status, CorePrStatus::REGISTERS reg) -> py::object { - bool error; - uint64_t val = status.get(reg, &error); - if (error) { - return py::none(); - } - return py::int_(val); - }, - "Return the register value", - "register"_a) - - .def("set", - &CorePrStatus::set, - "Set register value", - "register"_a, "value"_a) - - .def("has", - &CorePrStatus::has, - "Check if a value is associated with the given register", - "register"_a) - - .def("__getitem__", - &CorePrStatus::operator[], - "", - py::return_value_policy::copy) - - .def("__setitem__", - [] (CorePrStatus& status, CorePrStatus::REGISTERS reg, uint64_t val) { - status.set(reg, val); - }, - "") - - .def("__contains__", - &CorePrStatus::has, - "") - - .def("__eq__", &CorePrStatus::operator==) - .def("__ne__", &CorePrStatus::operator!=) - .def("__hash__", - [] (const CorePrStatus& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const CorePrStatus& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); - - - LIEF::enum_(cls, "REGISTERS") - .value(PY_ENUM(CorePrStatus::REGISTERS::UNKNOWN)) - - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EBX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_ECX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EDX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_ESI)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EDI)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EBP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EAX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_DS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_ES)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_FS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_GS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86__)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EIP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_CS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_EFLAGS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_ESP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_SS)) - - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R15)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R14)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R13)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R12)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RBP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RBX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R11)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R10)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R9)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_R8)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RAX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RCX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RDX)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RSI)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RDI)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64__)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RIP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_CS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_EFLAGS)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_RSP)) - .value(PY_ENUM(CorePrStatus::REGISTERS::X86_64_SS)) - - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R0)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R1)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R2)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R3)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R4)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R5)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R6)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R7)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R8)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R9)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R10)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R11)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R12)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R13)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R14)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_R15)) - .value(PY_ENUM(CorePrStatus::REGISTERS::ARM_CPSR)) - - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X0)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X1)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X2)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X3)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X4)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X5)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X6)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X7)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X8)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X9)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X10)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X11)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X12)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X13)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X14)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X15)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X16)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X17)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X18)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X19)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X20)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X21)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X22)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X23)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X24)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X25)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X26)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X27)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X28)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X29)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X30)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_X31)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64_PC)) - .value(PY_ENUM(CorePrStatus::REGISTERS::AARCH64__)); - -} -} // namespace ELF -} // namespace LIEF diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp deleted file mode 100644 index fb19666..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/core/CoreSigInfo.hpp" - - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (CoreSigInfo::*)(void) const; - -template -using setter_t = void (CoreSigInfo::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "CoreSigInfo") - - .def_property("signo", - static_cast>(&CoreSigInfo::signo), - static_cast>(&CoreSigInfo::signo), - "Signal number") - - .def_property("sigcode", - static_cast>(&CoreSigInfo::sigcode), - static_cast>(&CoreSigInfo::sigcode), - "Signal code") - - .def_property("sigerrno", - static_cast>(&CoreSigInfo::sigerrno), - static_cast>(&CoreSigInfo::sigerrno), - "If non-zero, an errno value associated with this signal") - - .def("__eq__", &CoreSigInfo::operator==) - .def("__ne__", &CoreSigInfo::operator!=) - .def("__hash__", - [] (const CoreSigInfo& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const CoreSigInfo& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); - - -} -} // namespace ELF -} // namespace LIEF diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/pyAndroidNote.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/pyAndroidNote.cpp deleted file mode 100644 index 45838c8..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/pyAndroidNote.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/AndroidNote.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (AndroidNote::*)(void) const; - -template -using setter_t = void (AndroidNote::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "AndroidNote") - - .def_property("sdk_version", - static_cast>(&AndroidNote::sdk_version), - static_cast>(&AndroidNote::sdk_version), - "Target SDK platform" - ) - - .def_property("ndk_version", - static_cast>(&AndroidNote::ndk_version), - static_cast>(&AndroidNote::ndk_version), - "Android NDK version used to build the current binary" - ) - - .def_property("ndk_build_number", - static_cast>(&AndroidNote::ndk_build_number), - static_cast>(&AndroidNote::ndk_build_number), - "Android NDK build number" - ) - - .def("__eq__", &AndroidNote::operator==) - .def("__ne__", &AndroidNote::operator!=) - .def("__hash__", - [] (const AndroidNote& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const AndroidNote& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/NoteDetails/pyNoteAbi.cpp b/vendor/lief/api/python/ELF/objects/NoteDetails/pyNoteAbi.cpp deleted file mode 100644 index f7f8974..0000000 --- a/vendor/lief/api/python/ELF/objects/NoteDetails/pyNoteAbi.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails/NoteAbi.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (NoteAbi::*)(void) const; - -template -using setter_t = void (NoteAbi::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "NoteAbi") - - .def_property_readonly("abi", - static_cast>(&NoteAbi::abi), - "Return the target " RST_CLASS_REF(lief.ELF.NOTE_ABIS) "" - ) - - .def_property_readonly("version", - static_cast>(&NoteAbi::version), - "Return the target version as ``(Major, Minor, Patch)``" - ) - - .def("__eq__", &NoteAbi::operator==) - .def("__ne__", &NoteAbi::operator!=) - .def("__hash__", - [] (const NoteAbi& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const NoteAbi& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyBinary.cpp b/vendor/lief/api/python/ELF/objects/pyBinary.cpp deleted file mode 100644 index 9556b80..0000000 --- a/vendor/lief/api/python/ELF/objects/pyBinary.cpp +++ /dev/null @@ -1,711 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "pyIterators.hpp" -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/Binary.hpp" - -#include "pyErr.hpp" -#include "pyELF.hpp" - -namespace LIEF { -namespace ELF { - -template -using no_const_getter = T (Binary::*)(void); - -template -using no_const_func = T (Binary::*)(P); - -template -using getter_t = T (Binary::*)(void) const; - -template -using setter_t = void (Binary::*)(T); - - -template<> -void create(py::module& m) { - // Binary object - py::class_ bin(m, "Binary", R"delim( - Class which represents an ELF binary - )delim"); - - init_ref_iterator(bin, "it_notes"); - init_ref_iterator(bin, "it_symbols_version_requirement"); - init_ref_iterator(bin, "it_symbols_version_definition"); - init_ref_iterator(bin, "it_segments"); - init_ref_iterator(bin, "it_sections"); - init_ref_iterator(bin, "it_dynamic_entries"); - init_ref_iterator(bin, "it_symbols_version"); - // We don't need to register it_object_relocations, it_dynamic_relocations - // as it it the same underlying type - init_ref_iterator(bin, "it_filter_relocation"); - init_ref_iterator(bin, "it_relocations"); - - init_ref_iterator(bin, "it_dyn_static_symbols"); - init_ref_iterator(bin, "it_symbols"); // For it_dynamic_symbols / it_static_symbols - init_ref_iterator(bin, "it_filter_symbols"); // For it_imported_symbols - - - - - bin - .def_property_readonly("type", - &Binary::type, - "Return the binary's " RST_CLASS_REF(lief.ELF.ELF_CLASS) "") - - .def_property_readonly("header", - static_cast>(&Binary::header), - "Return " RST_CLASS_REF(lief.ELF.Header) " object", - py::return_value_policy::reference_internal) - - .def_property_readonly("sections", - static_cast>(&Binary::sections), - "Return an iterator over binary's " RST_CLASS_REF(lief.ELF.Section) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("segments", - static_cast>(&Binary::segments), - "Return an iterator to binary's " RST_CLASS_REF(lief.ELF.Segment) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("dynamic_entries", - static_cast>(&Binary::dynamic_entries), - "Return an iterator to " RST_CLASS_REF(lief.ELF.DynamicEntry) " entries as a list", - py::return_value_policy::reference_internal) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.ELF.DynamicEntry) " in the binary", - "dynamic_entry", - py::return_value_policy::reference) - - .def_property_readonly("static_symbols", - static_cast>(&Binary::static_symbols), - "Return an iterator to static " RST_CLASS_REF(lief.ELF.Symbol) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("dynamic_symbols", - static_cast>(&Binary::dynamic_symbols), - "Return an iterator to dynamic " RST_CLASS_REF(lief.ELF.Symbol) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("symbols", - static_cast>(&Binary::symbols), - "Return an iterator over both **static** and **dynamic** " RST_CLASS_REF(lief.ELF.Symbol) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("exported_symbols", - static_cast>(&Binary::exported_symbols), - "Return dynamic " RST_CLASS_REF(lief.ELF.Symbol) " which are exported", - py::return_value_policy::reference_internal) - - .def_property_readonly("imported_symbols", - static_cast>(&Binary::imported_symbols), - "Return dynamic " RST_CLASS_REF(lief.ELF.Symbol) " which are imported", - py::return_value_policy::reference_internal) - - .def_property_readonly("dynamic_relocations", - static_cast>(&Binary::dynamic_relocations), - "Return an iterator over dynamics " RST_CLASS_REF(lief.ELF.Relocation) "", - py::return_value_policy::reference_internal) - - .def("add_dynamic_relocation", - &Binary::add_dynamic_relocation, R"delim( - Add a new *dynamic* relocation. - - We consider a dynamic relocation as a relocation which is not plt-related. - - See: :meth:`lief.ELF.Binary.add_pltgot_relocation` - )delim", - "relocation"_a, - py::return_value_policy::reference) - - .def("add_pltgot_relocation", - &Binary::add_pltgot_relocation, R"delim( - Add a .plt.got relocation. This kind of relocation is usually - associated with a PLT stub that aims at resolving the underlying symbol. - - See: :meth:`lief.ELF.Binary.add_dynamic_relocation` - )delim", - "relocation"_a, - py::return_value_policy::reference) - - .def("add_object_relocation", - &Binary::add_object_relocation, - R"delim( - Add relocation for object file (.o) - - The first parameter is the section to add while the second parameter - is the :class:`~lief.ELF.Section` associated with the relocation. - - If there is an error, this function returns a nullptr. Otherwise, it returns - the relocation added.", - )delim", - "relocation"_a, "section"_a, - py::return_value_policy::reference) - - .def_property_readonly("pltgot_relocations", - static_cast>(&Binary::pltgot_relocations), - "Return an iterator over PLT/GOT " RST_CLASS_REF(lief.ELF.Relocation) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("object_relocations", - static_cast>(&Binary::object_relocations), - "Return an iterator over object " RST_CLASS_REF(lief.ELF.Relocation) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("relocations", - static_cast>(&Binary::relocations), - "Return an iterator over **all** " RST_CLASS_REF(lief.ELF.Relocation) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("symbols_version", - static_cast>(&Binary::symbols_version), - "Return an iterator " RST_CLASS_REF(lief.ELF.SymbolVersion) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("symbols_version_requirement", - static_cast>(&Binary::symbols_version_requirement), - "Return an iterator to " RST_CLASS_REF(lief.ELF.SymbolVersionRequirement) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("symbols_version_definition", - static_cast>(&Binary::symbols_version_definition), - "Return an iterator to " RST_CLASS_REF(lief.ELF.SymbolVersionDefinition) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("use_gnu_hash", - &Binary::use_gnu_hash, - "``True`` if GNU hash is used") - - .def_property_readonly("gnu_hash", - &Binary::gnu_hash, - "Return the " RST_CLASS_REF(lief.ELF.GnuHash) " object\n\n" - "Hash are used by the loader to speed up symbols resolution (GNU Version)", - py::return_value_policy::reference_internal) - - .def_property_readonly("use_sysv_hash", - &Binary::use_sysv_hash, - "``True`` if SYSV hash is used") - - .def_property_readonly("sysv_hash", - &Binary::sysv_hash, - "Return the " RST_CLASS_REF(lief.ELF.SysvHash) " object\n\n" - "Hash are used by the loader to speed up symbols resolution (SYSV version)", - py::return_value_policy::reference_internal) - - .def_property_readonly("imagebase", - &Binary::imagebase, - "Return the program image base. (e.g. ``0x400000``)") - - .def_property_readonly("virtual_size", - &Binary::virtual_size, - "Return the size of the mapped binary") - - .def_property_readonly("is_pie", - &Binary::is_pie, - R"delim( - Check if the binary has been compiled with `-fpie -pie` flags - - To do so we check if there is a `PT_INTERP` segment and if - the binary type is `ET_DYN` (Shared object) - )delim") - - .def_property_readonly("has_interpreter", - &Binary::has_interpreter, - "Check if the binary uses a loader (also named linker or interpreter)") - - .def_property_readonly("functions", - &Binary::functions, - "List of the functions found the in the binary") - - .def_property("interpreter", - static_cast>(&Binary::interpreter), - static_cast>(&Binary::interpreter), - "ELF interpreter (loader) if any. (e.g. ``/lib64/ld-linux-x86-64.so.2``)") - - .def("section_from_offset", - static_cast(&Binary::section_from_offset), - R"delim( - Return the :class:`~lief.ELF.Section` which encompasses the given offset. - It returns None if a section can't be found. - - If ``skip_nobits`` is set (which is the case by default), this function won't - consider sections for which the type is ``SHT_NOBITS`` (like ``.bss, .tbss, ...``) - )delim", - "offset"_a, "skip_nobits"_a = true, - py::return_value_policy::reference) - - .def("section_from_virtual_address", - static_cast(&Binary::section_from_virtual_address), - R"delim( - Return the :class:`~lief.ELF.Section` which encompasses the given virtual address. - It returns None if a section can't be found. - - If ``skip_nobits`` is set (which is the case by default), this function won't - consider sections for which the type is ``SHT_NOBITS`` (like ``.bss, .tbss, ...``) - )delim", - "address"_a, "skip_nobits"_a = true, - py::return_value_policy::reference) - - .def("segment_from_virtual_address", - static_cast>(&Binary::segment_from_virtual_address), - R"delim( - Return the :class:`~lief.ELF.Segment` which encompasses the given virtual address. - It returns None if a segment can't be found. - )delim", - "address"_a, - py::return_value_policy::reference) - - .def("segment_from_offset", - static_cast>(&Binary::segment_from_offset), - R"delim( - Return the :class:`~lief.ELF.Segment` which encompasses the given offset. - It returns None if a segment can't be found. - )delim", - "offset"_a, - py::return_value_policy::reference) - - .def("get", - static_cast>(&Binary::get), - R"delim( - Return the first binary's :class:`~lief.ELF.DynamicEntry` from the given - :class:`~lief.ELF.DYNAMIC_TAGS`. - - It returns None if the dynamic entry can't be found. - )delim", - "tag"_a, - py::return_value_policy::reference) - - .def("get", - static_cast>(&Binary::get), - R"delim( - Return the first binary's :class:`~lief.ELF.Segment` from the given - :class:`~lief.ELF.SEGMENT_TYPES` - - It returns None if the segment can't be found. - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("get", - static_cast>(&Binary::get), - R"delim( - Return the first binary's :class:`~lief.ELF.Note` from the given - :class:`~lief.ELF.NOTE_TYPES`. - - It returns None if the note can't be found. - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("get", - static_cast>(&Binary::get), - R"delim( - Return the first binary's :class:`~lief.ELF.Section` from the given - :class:`~lief.ELF.ELF_SECTION_TYPES` - - It returns None if the section can't be found. - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("has", - static_cast(&Binary::has), - R"delim( - Check if it exists a :class:`~lief.ELF.DynamicEntry` with the given - :class:`~lief.ELF.DYNAMIC_TAGS` - )delim", - "tag"_a) - - .def("has", - static_cast(&Binary::has), - "Check if a " RST_CLASS_REF(lief.ELF.Segment) " of *type* (" RST_CLASS_REF(lief.ELF.SEGMENT_TYPES) ") exists", - "type"_a) - - .def("has", - static_cast(&Binary::has), - "Check if a " RST_CLASS_REF(lief.ELF.Note) " of *type* (" RST_CLASS_REF(lief.ELF.NOTE_TYPES) ") exists", - "type"_a) - - .def("has", - static_cast(&Binary::has), - "Check if a " RST_CLASS_REF(lief.ELF.Section) " of *type* (" RST_CLASS_REF(lief.ELF.ECTION_TYPES) ") exists", - "type"_a) - - .def("patch_pltgot", - static_cast(&Binary::patch_pltgot), - "Patch the imported symbol's name with the ``address``", - "symbol_name"_a, "address"_a) - - .def("patch_pltgot", - static_cast(&Binary::patch_pltgot), - "Patch the imported " RST_CLASS_REF(lief.ELF.Symbol) " with the ``address``", - "symbol"_a, "address"_a) - - .def("has_section", - &Binary::has_section, - "Check if a " RST_CLASS_REF(lief.ELF.Section) " with the given name exists in the binary", - "section_name"_a) - - .def("has_section_with_offset", - &Binary::has_section_with_offset, - "Check if a " RST_CLASS_REF(lief.ELF.Section) " that encompasses the given offset exists", - "offset"_a) - - .def("has_section_with_va", - &Binary::has_section_with_va, - "Check if a " RST_CLASS_REF(lief.ELF.Section) " that encompasses the given virtual address exists", - "virtual_address"_a) - - .def("get_section", - static_cast>(&Binary::get_section), - R"delim( - Return the :class:`~lief.ELF.Section` with the given ``name`` - - It returns None if the section can't be found. - )delim", - "section_name"_a, - py::return_value_policy::reference) - - .def("add_static_symbol", - &Binary::add_static_symbol, - "Add a **static** " RST_CLASS_REF(lief.ELF.Symbol) " to the binary", - "symbol"_a, - py::return_value_policy::reference) - - .def("add_dynamic_symbol", - static_cast(&Binary::add_dynamic_symbol), - R"delim( - Add a **dynamic** :class:`~lief.ELF.Symbol` to the binary - - The function also takes an optional :class:`lief.ELF.SymbolVersion` - )delim", - "symbol"_a, "symbol_version"_a = nullptr, - py::return_value_policy::reference) - - .def("virtual_address_to_offset", - [] (const Binary& self, uint64_t address) { - return error_or(&Binary::virtual_address_to_offset, self, address); - }, - "Convert the virtual address to a file offset", - "virtual_address"_a) - - .def("add", - static_cast(&Binary::add), - R"delim( - Add the given :class:`~lief.ELF.Section` to the binary. - - If the section does not aim at being loaded in memory, - the ``loaded`` parameter has to be set to ``False`` (default: ``True``) - )delim", - "section"_a, "loaded"_a = true, - py::return_value_policy::reference) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.ELF.Segment) " in the binary" - "segment"_a, "base"_a = 0, - py::return_value_policy::reference) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.ELF.Note) " in the binary", - "note"_a, - py::return_value_policy::reference) - - .def("replace", - static_cast(&Binary::replace), - R"delim( - Replace the :class:`~lief.ELF.Segment` given in 2nd parameter with the - :class:`~lief.ELF.Segment` given in the first parameter and return the updated segment. - - .. warning:: - - The ``original_segment`` is no longer valid after this function - )delim", - "new_segment"_a, "original_segment"_a, "base"_a = 0, - py::return_value_policy::reference) - - .def("extend", - static_cast(&Binary::extend), - "Extend the given given " RST_CLASS_REF(lief.ELF.Segment) " by the given size", - "segment"_a, "size"_a, - py::return_value_policy::reference) - - .def("extend", - static_cast(&Binary::extend), - "Extend the given given " RST_CLASS_REF(lief.ELF.Section) " by the given size", - "segment"_a, "size"_a, - py::return_value_policy::reference) - - .def("remove", - static_cast(&Binary::remove), - "Remove the given " RST_CLASS_REF(lief.ELF.DynamicEntry) " from the dynamic table", - "dynamic_entry"_a) - - .def("remove", - static_cast(&Binary::remove), - "Remove **all** the " RST_CLASS_REF(lief.ELF.DynamicEntry) " with the given " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) "", - "tag"_a) - - .def("remove", - static_cast(&Binary::remove), - "Remove the given " RST_CLASS_REF(lief.ELF.Section) ". The ``clear`` parameter specifies whether or not " - "we must fill its content with ``0`` before removing", - "section"_a, "clear"_a = false) - - .def("remove", - static_cast(&Binary::remove), - "Remove the given " RST_CLASS_REF(lief.ELF.Note) "", - "note"_a) - - .def("remove", - static_cast(&Binary::remove), - "Remove **all** the " RST_CLASS_REF(lief.ELF.Note) " with the given " RST_CLASS_REF(lief.ELF.NOTE_TYPES) "", - "type"_a) - - .def_property_readonly("has_notes", - &Binary::has_notes, - "``True`` if the binary contains notes") - - .def_property_readonly("notes", - static_cast>(&Binary::notes), - "Return an iterator over the " RST_CLASS_REF(lief.ELF.Note) " entries", - py::return_value_policy::reference_internal) - - .def("strip", - &Binary::strip, - "Strip the binary") - - .def("permute_dynamic_symbols", - &Binary::permute_dynamic_symbols, - "Apply the given permutation on the dynamic symbols table", - "permutation"_a) - - .def("write", - static_cast(&Binary::write), - "Rebuild the binary and write it in a file", - "output"_a, - py::return_value_policy::reference_internal) - - .def_property_readonly("last_offset_section", - &Binary::last_offset_section, - "Return the last offset used in binary according to **sections table**") - - .def_property_readonly("last_offset_segment", - &Binary::last_offset_segment, - "Return the last offset used in binary according to **segments table**") - - .def_property_readonly("next_virtual_address", - &Binary::next_virtual_address, - "Return the next virtual address available") - - .def("add_library", - &Binary::add_library, - "Add a library with the given name as dependency", - "library_name"_a) - - .def("has_library", - &Binary::has_library, - "Check if the given library name exists in the current binary", - "library_name"_a) - - .def("remove_library", - &Binary::remove_library, - "Remove the given library", - "library_name"_a) - - .def("get_library", - static_cast>(&Binary::get_library), - R"delim( - Return the :class:`~lief.ELF.DynamicEntryLibrary` with the given ``name`` - - It returns None if the library can't be found. - )delim", - "library_name"_a, - py::return_value_policy::reference) - - .def("has_dynamic_symbol", - &Binary::has_dynamic_symbol, - "Check if the symbol with the given ``name`` exists in the **dynamic** symbol table", - "symbol_name"_a) - - .def("get_dynamic_symbol", - static_cast>(&Binary::get_dynamic_symbol), - R"delim( - Get the dynamic symbol from the given name. - - It returns None if it can't be found. - )delim", - "symbol_name"_a, - py::return_value_policy::reference) - - .def("has_static_symbol", - &Binary::has_static_symbol, - "Check if the symbol with the given ``name`` exists in the **static** symbol table", - "symbol_name"_a) - - .def("get_static_symbol", - static_cast>(&Binary::get_static_symbol), - R"delim( - Get the **static** symbol from the given ``name``. - - It returns None if it can't be found. - )delim", - "symbol_name"_a, - py::return_value_policy::reference) - - .def("get_strings", - static_cast(&Binary::strings), - "Return list of strings used in the current ELF file with a minimal size given in first parameter (Default: 5)\n" - "It looks for strings in the ``.roadata`` section", - "min_size"_a = 5, - py::return_value_policy::move) - - .def_property_readonly("strings", - [] (const Binary& bin) { - return bin.strings(); - }, - "Return list of strings used in the current ELF file.\n" - "Basically this function looks for strings in the ``.roadata`` section", - py::return_value_policy::move) - - .def("remove_static_symbol", - static_cast(&Binary::remove_static_symbol), - "Remove the given " RST_CLASS_REF(lief.ELF.Symbol) " from the ``.symtab`` section") - - .def("add_exported_function", - &Binary::add_exported_function, - "Create a symbol for the function at the given ``address`` and create an export", - "address"_a, "name"_a = "", - py::return_value_policy::reference) - - .def("export_symbol", - static_cast(&Binary::export_symbol), - "Export the given symbol and create an entry if it doesn't exist", - "symbol"_a, - py::return_value_policy::reference) - - .def("export_symbol", - static_cast(&Binary::export_symbol), - "Export the symbol with the given name and create an entry if it doesn't exist", - "symbol_name"_a, "value"_a = 0, - py::return_value_policy::reference) - - .def("get_relocation", - static_cast>(&Binary::get_relocation), - "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given symbol name", - "symbol_name"_a, - py::return_value_policy::reference) - - .def("get_relocation", - static_cast>(&Binary::get_relocation), - "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given " RST_CLASS_REF(lief.ELF.Symbol) "", - "symbol"_a, - py::return_value_policy::reference) - - .def("get_relocation", - static_cast>(&Binary::get_relocation), - "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given address", - "address"_a, - py::return_value_policy::reference) - - .def_property_readonly("dtor_functions", - &Binary::dtor_functions, - "List of the binary destructors (typically, the functions located in the ``.fini_array``)") - - .def_property_readonly("eof_offset", - &Binary::eof_offset, - "Return the last offset used by the ELF binary according to both: the sections table " - "and the segments table.") - - .def_property_readonly("has_overlay", - &Binary::has_overlay, - "True if data are appended to the end of the binary") - - .def_property("overlay", - static_cast>(&Binary::overlay), - static_cast>(&Binary::overlay), - "Overlay data that are not a part of the ELF format") - - .def(py::self += Segment()) - .def(py::self += Section()) - .def(py::self += DynamicEntry()) - .def(py::self += Note()) - - .def(py::self -= DynamicEntry()) - .def(py::self -= DYNAMIC_TAGS()) - - .def(py::self -= Note()) - .def(py::self -= NOTE_TYPES()) - - .def("__eq__", &Binary::operator==) - .def("__ne__", &Binary::operator!=) - .def("__hash__", - [] (const Binary& binary) { - return Hash::hash(binary); - }) - - .def("__getitem__", - static_cast(&Binary::operator[]), - "", - py::return_value_policy::reference) - - .def("__getitem__", - static_cast(&Binary::operator[]), - "", - py::return_value_policy::reference) - - .def("__getitem__", - static_cast(&Binary::operator[]), - "", - py::return_value_policy::reference) - - - .def("__getitem__", - static_cast(&Binary::operator[]), - "", - py::return_value_policy::reference) - - .def("__contains__", - static_cast(&Binary::has), - "Check if a " RST_CLASS_REF(lief.ELF.Segment) " of *type* (" RST_CLASS_REF(lief.ELF.SEGMENT_TYPES) ") exists") - - .def("__contains__", - static_cast(&Binary::has), - "Check if the " RST_CLASS_REF(lief.ELF.DynamicEntry) " associated with the given " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) " exists") - - .def("__contains__", - static_cast(&Binary::has), - "Check if the " RST_CLASS_REF(lief.ELF.Note) " associated with the given " RST_CLASS_REF(lief.ELF.NOTE_TYPES) " exists") - - .def("__contains__", - static_cast(&Binary::has), - "Check if the " RST_CLASS_REF(lief.ELF.Section) " associated with the given " RST_CLASS_REF(lief.ELF.SECTION_TYPES) " exists") - - .def("__str__", - [] (const Binary& binary) { - std::ostringstream stream; - stream << binary; - return stream.str(); - }); -} -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyBuilder.cpp b/vendor/lief/api/python/ELF/objects/pyBuilder.cpp deleted file mode 100644 index dd6f75e..0000000 --- a/vendor/lief/api/python/ELF/objects/pyBuilder.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "pyELF.hpp" - -#include "LIEF/ELF/Binary.hpp" -#include "LIEF/ELF/Builder.hpp" - -namespace LIEF { -namespace ELF { - -template<> -void create(py::module& m) { - py::class_ builder(m, "Builder", - R"delim( - Class which takes an :class:`lief.ELF.Binary` object and reconstructs a valid binary - )delim"); - - py::class_(builder, "config_t", - "Interface to tweak the " RST_CLASS_REF(lief.ELF.Builder) "") - .def(py::init<>()) - .def_readwrite("force_relocate", &Builder::config_t::force_relocate, - "Force to relocate all the ELF structures that can be relocated (mostly for testing)") - - .def_readwrite("dt_hash", &Builder::config_t::dt_hash) - .def_readwrite("dyn_str", &Builder::config_t::dyn_str) - .def_readwrite("dynamic_section", &Builder::config_t::dynamic_section) - .def_readwrite("fini_array", &Builder::config_t::fini_array) - .def_readwrite("init_array", &Builder::config_t::init_array) - .def_readwrite("interpreter", &Builder::config_t::interpreter) - .def_readwrite("jmprel", &Builder::config_t::jmprel) - .def_readwrite("notes", &Builder::config_t::notes) - .def_readwrite("preinit_array", &Builder::config_t::preinit_array) - .def_readwrite("rela", &Builder::config_t::rela) - .def_readwrite("static_symtab", &Builder::config_t::static_symtab) - .def_readwrite("sym_verdef", &Builder::config_t::sym_verdef) - .def_readwrite("sym_verneed", &Builder::config_t::sym_verneed) - .def_readwrite("sym_versym", &Builder::config_t::sym_versym) - .def_readwrite("symtab", &Builder::config_t::symtab); - - builder - .def(py::init(), - "Constructor that takes a " RST_CLASS_REF(lief.ELF.Binary) "", - "elf_binary"_a) - - .def("build", - static_cast(&Builder::build), - "Perform the build of the provided ELF binary") - - .def_property("config", - &Builder::config, - &Builder::set_config, - "Tweak the ELF builder with the provided config parameter", - py::return_value_policy::reference_internal) - - .def("write", - static_cast(&Builder::write), - "Write the build result into the ``output`` file", - "output"_a) - - .def("get_build", - &Builder::get_build, - "Return the build result as a ``list`` of bytes", - py::return_value_policy::reference_internal); - -} -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntry.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntry.cpp deleted file mode 100644 index 454ca81..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntry.cpp +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/DynamicEntry.hpp" -#include "LIEF/ELF/hash.hpp" - - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntry::*)(void) const; - -template -using setter_t = void (DynamicEntry::*)(T); - - -template<> -void create(py::module& m) { - - // DynamicEntry object - py::class_(m, "DynamicEntry", - R"delim( - Class which represents an entry in the dynamic table - These entries are located in the ``.dynamic`` section or the ``PT_DYNAMIC`` segment - )delim") - .def(py::init<>(), - "Default constructor") - - .def(py::init(), - "Constructor from a " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) " and value", - "tag"_a, "value"_a) - - .def_property("tag", - static_cast>(&DynamicEntry::tag), - static_cast>(&DynamicEntry::tag), - "Return the entry's " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) " which represent the entry type") - - .def_property("value", - static_cast>(&DynamicEntry::value), - static_cast>(&DynamicEntry::value), - R"delim( - Return the entry's value - - The meaning of the value strongly depends on the tag. - It can be an offset, an index, a flag, ... - )delim") - - .def("__eq__", &DynamicEntry::operator==) - .def("__ne__", &DynamicEntry::operator!=) - .def("__hash__", - [] (const DynamicEntry& entry) { - return Hash::hash(entry); - }) - - .def("__str__", - [] (const DynamicEntry& dynamicEntry) - { - std::ostringstream stream; - stream << dynamicEntry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntryArray.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntryArray.cpp deleted file mode 100644 index b759ca6..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntryArray.cpp +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -*/ - -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicEntryArray.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntryArray::*)(void) const; - -template -using setter_t = void (DynamicEntryArray::*)(T); - - -template<> -void create(py::module& m) { - - // Dynamic Entry Array object - py::class_(m, "DynamicEntryArray", - R"delim( - Class that represent an Array in the dynamic table. - This entry is associated with constructors: - - ``DT_PREINIT_ARRAY`` - - ``DT_INIT_ARRAY`` - - ``DT_FINI_ARRAY`` - - The underlying values are 64-bits integers to cover both: - ELF32 and ELF64 binaries. - )delim") - .def(py::init<>()) - - .def(py::init(), - "Constructor with " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) " and value", - "tag"_a, "value"_a) - - .def_property("array", - static_cast& (DynamicEntryArray::*)()>(&DynamicEntryArray::array), - static_cast&>>(&DynamicEntryArray::array), - "Return the array as a list of intergers", - py::return_value_policy::reference) - - .def("insert", - &DynamicEntryArray::insert, - "Insert the given ``function`` at ``pos``", - "pos"_a, "function"_a, - py::return_value_policy::reference) - - .def("append", - &DynamicEntryArray::append, - "Append the given ``function`` ", - "function"_a, - py::return_value_policy::reference) - - .def("remove", - &DynamicEntryArray::remove, - "Remove the given ``function`` ", - "function"_a, - py::return_value_policy::reference) - - - .def(py::self += uint64_t()) - .def(py::self -= uint64_t()) - - - .def("__getitem__", - static_cast(&DynamicEntryArray::operator[]), - py::return_value_policy::reference) - - .def("__len__", - &DynamicEntryArray::size) - - .def("__eq__", &DynamicEntryArray::operator==) - .def("__ne__", &DynamicEntryArray::operator!=) - .def("__hash__", - [] (const DynamicEntryArray& entry) { - return Hash::hash(entry); - }) - - - .def("__str__", - [] (const DynamicEntryArray& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntryFlags.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntryFlags.cpp deleted file mode 100644 index 9a16f53..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntryFlags.cpp +++ /dev/null @@ -1,116 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicEntryFlags.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntryFlags::*)(void) const; - -template -using setter_t = void (DynamicEntryFlags::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DynamicEntryFlags") - .def(py::init<>()) - - .def(py::init(), - "Constructor with " RST_CLASS_REF(lief.ELF.DYNAMIC_TAGS) " and value", - "tag"_a, "value"_a) - - .def_property_readonly("flags", - &DynamicEntryFlags::flags, - "Return list of " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS) " or " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS_1) " (integer)", - py::return_value_policy::move) - - .def("has", - static_cast(&DynamicEntryFlags::has), - "Check if this entry contains the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS) "", - "flag"_a) - - .def("has", - static_cast(&DynamicEntryFlags::has), - "Check if this entry contains the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS_1) "", - "flag"_a) - - .def("add", - static_cast(&DynamicEntryFlags::add), - "Add the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS) "", - "flag"_a) - - .def("add", - static_cast(&DynamicEntryFlags::add), - "Add the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS_1) "", - "flag"_a) - - .def("remove", - static_cast(&DynamicEntryFlags::remove), - "Remove the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS) "", - "flag"_a) - - .def("remove", - static_cast(&DynamicEntryFlags::remove), - "Remove the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS_1) "", - "flag"_a) - - - .def("__eq__", &DynamicEntryFlags::operator==) - .def("__ne__", &DynamicEntryFlags::operator!=) - .def("__hash__", - [] (const DynamicEntryFlags& entry) { - return Hash::hash(entry); - }) - - .def(py::self += DYNAMIC_FLAGS()) - .def(py::self += DYNAMIC_FLAGS_1()) - - - .def(py::self -= DYNAMIC_FLAGS()) - .def(py::self -= DYNAMIC_FLAGS_1()) - - .def("__contains__", - static_cast(&DynamicEntryFlags::has), - "Check if the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS) " is present") - - .def("__contains__", - static_cast(&DynamicEntryFlags::has), - "Check if the given " RST_CLASS_REF(lief.ELF.DYNAMIC_FLAGS_1) " is present") - - - .def("__str__", - [] (const DynamicEntryFlags& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntryLibrary.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntryLibrary.cpp deleted file mode 100644 index 051fb84..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntryLibrary.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicEntryLibrary.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntryLibrary::*)(void) const; - -template -using setter_t = void (DynamicEntryLibrary::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "DynamicEntryLibrary", - R"delim( - Class which represents a ``DT_NEEDED`` entry in the dynamic table. - - This kind of entry is usually used to create library dependency. - )delim") - - .def(py::init(), - "Constructor from a library name", - "library_name"_a) - - .def_property("name", - [] (const DynamicEntryLibrary& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DynamicEntryLibrary::name), - "Library associated with this entry (e.g. ``libc.so.6``)") - - .def("__eq__", &DynamicEntryLibrary::operator==) - .def("__ne__", &DynamicEntryLibrary::operator!=) - .def("__hash__", - [] (const DynamicEntryLibrary& entry) { - return Hash::hash(entry); - }) - - - .def("__str__", - [] (const DynamicEntryLibrary& dynamicEntryLibrary) - { - std::ostringstream stream; - stream << dynamicEntryLibrary; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntryRpath.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntryRpath.cpp deleted file mode 100644 index 17a4a7d..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntryRpath.cpp +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicEntryRpath.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntryRpath::*)(void) const; - -template -using setter_t = void (DynamicEntryRpath::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "DynamicEntryRpath", - R"delim( - Class which represents a ``DT_RPATH`` entry. This attribute is - deprecated (cf. ``man ld``) in favour of ``DT_RUNPATH`` (See :class:`~lief.ELF.DynamicRunPath`) - )delim") - - .def(py::init(), - "Constructor from (r)path", - "path"_a = "") - - .def(py::init &>(), - "Constructor from a list of paths", - "paths"_a) - - .def_property("name", - [] (const DynamicEntryRpath& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DynamicEntryRpath::name), - "The actual rpath as a string") - - .def_property("rpath", - [] (const DynamicEntryRpath& obj) { - return safe_string_converter(obj.rpath()); - }, - static_cast>(&DynamicEntryRpath::rpath), - "The actual rpath as a string") - - - .def_property("paths", - static_cast >>(&DynamicEntryRpath::paths), - static_cast&>>(&DynamicEntryRpath::paths), - "Paths as a list") - - .def("insert", - &DynamicEntryRpath::insert, - "Insert a ``path`` at the given ``position``", - "position"_a, "path"_a, - py::return_value_policy::reference) - - .def("append", - &DynamicEntryRpath::append, - "Append the given ``path`` ", - "path"_a, - py::return_value_policy::reference) - - - .def("remove", - &DynamicEntryRpath::remove, - "Remove the given ``path`` ", - "path"_a, - py::return_value_policy::reference) - - .def(py::self += std::string()) - .def(py::self -= std::string()) - - .def("__eq__", &DynamicEntryRpath::operator==) - .def("__ne__", &DynamicEntryRpath::operator!=) - .def("__hash__", - [] (const DynamicEntryRpath& entry) { - return Hash::hash(entry); - }) - - - .def("__str__", - [] (const DynamicEntryRpath& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicEntryRunPath.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicEntryRunPath.cpp deleted file mode 100644 index 8756fa1..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicEntryRunPath.cpp +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicEntryRunPath.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicEntryRunPath::*)(void) const; - -template -using setter_t = void (DynamicEntryRunPath::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DynamicEntryRunPath", - R"delim( - Class that represents a ``DT_RUNPATH`` wich is used by the loader - to resolve libraries (:class:`~lief.ELF.DynamicEntryLibrary`). - )delim") - - .def(py::init(), - "Constructor from a (run)path", - "path"_a = "") - - .def(py::init &>(), - "Constructor from a list of paths", - "paths"_a) - - .def_property("name", - [] (const DynamicEntryRunPath& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DynamicEntryRunPath::name), - "Runpath raw value") - - .def_property("runpath", - [] (const DynamicEntryRunPath& obj) { - return safe_string_converter(obj.runpath()); - }, - static_cast>(&DynamicEntryRunPath::runpath), - "Runpath raw value") - - .def_property("paths", - static_cast >>(&DynamicEntryRunPath::paths), - static_cast&>>(&DynamicEntryRunPath::paths), - "Paths as a list") - - .def("insert", - &DynamicEntryRunPath::insert, - "Insert a ``path`` at the given ``position``", - "position"_a, "path"_a, - py::return_value_policy::reference) - - .def("append", - &DynamicEntryRunPath::append, - "Append the given ``path`` ", - "path"_a, - py::return_value_policy::reference) - - - .def("remove", - &DynamicEntryRunPath::remove, - "Remove the given ``path`` ", - "path"_a, - py::return_value_policy::reference) - - - .def(py::self += std::string()) - .def(py::self -= std::string()) - - .def("__eq__", &DynamicEntryRunPath::operator==) - .def("__ne__", &DynamicEntryRunPath::operator!=) - .def("__hash__", - [] (const DynamicEntryRunPath& entry) { - return Hash::hash(entry); - }) - - .def("__str__", - [] (const DynamicEntryRunPath& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyDynamicSharedObject.cpp b/vendor/lief/api/python/ELF/objects/pyDynamicSharedObject.cpp deleted file mode 100644 index 84a8d91..0000000 --- a/vendor/lief/api/python/ELF/objects/pyDynamicSharedObject.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" - -#include "LIEF/ELF/DynamicSharedObject.hpp" -#include "LIEF/ELF/DynamicEntry.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (DynamicSharedObject::*)(void) const; - -template -using setter_t = void (DynamicSharedObject::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DynamicSharedObject", - R"delim( - Class which represents a ``DT_SONAME`` entry in the dynamic table - This kind of entry is usually used no name the original library. - - This entry is not present for executable. - )delim") - - .def(py::init(), - "Constructor from library name", - "library_name"_a) - - .def_property("name", - [] (const DynamicSharedObject& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DynamicSharedObject::name), - "Return the library name") - - .def("__eq__", &DynamicSharedObject::operator==) - .def("__ne__", &DynamicSharedObject::operator!=) - .def("__hash__", - [] (const DynamicSharedObject& entry) { - return Hash::hash(entry); - }) - - .def("__str__", - [] (const DynamicSharedObject& dynamicSharedObject) { - std::ostringstream stream; - stream << dynamicSharedObject; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyGnuHash.cpp b/vendor/lief/api/python/ELF/objects/pyGnuHash.cpp deleted file mode 100644 index c4e860e..0000000 --- a/vendor/lief/api/python/ELF/objects/pyGnuHash.cpp +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/GnuHash.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (GnuHash::*)(void) const; - -template -using setter_t = void (GnuHash::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "GnuHash", - R"delim( - Class which provides a view over the GNU Hash implementation. - Most of the fields are read-only since the values are re-computed by the :class:`lief.ELF.Builder`. - )delim") - .def(py::init<>()) - - .def_property_readonly("nb_buckets", - &GnuHash::nb_buckets, - "Return the number of buckets") - - .def_property_readonly("symbol_index", - &GnuHash::symbol_index, - "Index of the first symbol in the dynamic symbols table which is accessible with the hash table") - - .def_property_readonly("shift2", - &GnuHash::shift2, - "Shift count used in the bloom filter") - - .def_property_readonly("bloom_filters", - &GnuHash::bloom_filters, - "Bloom filters", - py::return_value_policy::reference_internal) - - .def_property_readonly("buckets", - &GnuHash::buckets, - "hash buckets", - py::return_value_policy::reference_internal) - - .def_property_readonly("hash_values", - &GnuHash::hash_values, - "Hash values", - py::return_value_policy::reference_internal) - - .def("check_bloom_filter", - &GnuHash::check_bloom_filter, - "Check if the given hash pass the bloom filter", - "hash"_a) - - .def("check_bucket", - &GnuHash::check_bucket, - "Check if the given hash pass the bucket filter", - "hash"_a) - - .def("check", - static_cast(&GnuHash::check), - "Check if the symbol *probably* exists. If " - "the returned value is ``false`` you can assume at ``100%`` that " - "the symbol with the given name doesn't exists. If ``true`` you can't " - "do any assumption ", - "symbol_name"_a) - - .def("check", - static_cast(&GnuHash::check), - "Check if the symbol associated with the given *probably* exists. If " - "the returned value is ``false`` you can assume at ``100%`` that " - "the symbol doesn't exists. If ``true`` you can't " - "do any assumption", - "hash_value"_a) - - .def("__eq__", &GnuHash::operator==) - .def("__ne__", &GnuHash::operator!=) - .def("__hash__", - [] (const GnuHash& gnuhash) { - return Hash::hash(gnuhash); - }) - - .def("__str__", - [] (const GnuHash& gnuhash) - { - std::ostringstream stream; - stream << gnuhash; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/ELF/objects/pyHeader.cpp b/vendor/lief/api/python/ELF/objects/pyHeader.cpp deleted file mode 100644 index bddfabf..0000000 --- a/vendor/lief/api/python/ELF/objects/pyHeader.cpp +++ /dev/null @@ -1,244 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/Header.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - - -template<> -void create
(py::module& m) { - - py::class_(m, "Header", - R"delim( - Class which represents the ELF's header. This is the ELF structure - that starts an ELF file. - )delim") - .def(py::init<>()) - - .def_property("identity_class", - static_cast>(&Header::identity_class), - static_cast>(&Header::identity_class), - "Header's " RST_CLASS_REF(lief.ELF.ELF_CLASS) "." - ) - - .def_property("identity_data", - static_cast>(&Header::identity_data), - static_cast>(&Header::identity_data), - "Specify the data encoding: " RST_CLASS_REF(lief.ELF.ELF_DATA) "." - ) - - .def_property("identity_version", - static_cast>(&Header::identity_version), - static_cast>(&Header::identity_version), - "Return header's " RST_CLASS_REF(lief.ELF.VERSION) "." - ) - - .def_property("identity_os_abi", - static_cast>(&Header::identity_os_abi), - static_cast>(&Header::identity_os_abi), - "Identifies the version of the ABI for which the object is prepared (" RST_CLASS_REF(lief.ELF.OS_ABI) ")." - ) - - .def_property("identity_abi_version", - static_cast>(&Header::identity_abi_version), - static_cast>(&Header::identity_abi_version), - "Return the ABI version (integer)." - ) - - .def_property("identity", - static_cast(&Header::identity), - [] (Header& header, const py::object& obj) { - if (py::isinstance(obj)) { - header.identity(obj.cast()); - return; - } - - if (py::isinstance(obj)) { - header.identity(obj.cast()); - return; - } - - if (py::isinstance(obj)) { - header.identity(obj.cast()); - return; - } - - std::string error_str = py::repr(obj).cast(); - error_str = error_str + " is not supported!"; - throw py::type_error(error_str.c_str()); - }, - "Header's identity.", - py::return_value_policy::reference_internal - ) - - .def_property("file_type", - static_cast>(&Header::file_type), - static_cast>(&Header::file_type), - "Return binary's " RST_CLASS_REF(lief.ELF.E_TYPE) ". This field determines if the binary \ - is a executable, a library..." - ) - - .def_property("machine_type", - static_cast>(&Header::machine_type), - static_cast>(&Header::machine_type), - "Return the target architecture (" RST_CLASS_REF(lief.ELF.ARCH) ")") - - .def_property("object_file_version", - static_cast>(&Header::object_file_version), - static_cast>(&Header::object_file_version), - "Return the " RST_CLASS_REF(lief.ELF.VERSION) "") - - .def_property("entrypoint", - static_cast>(&Header::entrypoint), - static_cast>(&Header::entrypoint), - "Return the binary entry point") - - .def_property("program_header_offset", - static_cast>(&Header::program_headers_offset), - static_cast>(&Header::program_headers_offset), - "Offset of program table (also known as segments table)") - - .def_property("section_header_offset", - static_cast>(&Header::section_headers_offset), - static_cast>(&Header::section_headers_offset), - "Offset of section table") - - .def_property("processor_flag", - static_cast>(&Header::processor_flag), - static_cast>(&Header::processor_flag), - "Processor-specific flags") - - .def_property_readonly("arm_flags_list", - &Header::arm_flags_list, - "Return a list of " RST_CLASS_REF(lief.ELF.ARM_EFLAGS) " present in " - ":attr:`~lief.ELF.Header.processor_flag`", - py::return_value_policy::reference_internal) - - .def_property_readonly("mips_flags_list", - &Header::mips_flags_list, - "Return a list of " RST_CLASS_REF(lief.ELF.MIPS_EFLAGS) " present in " - ":attr:`~lief.ELF.Header.processor_flag`", - py::return_value_policy::reference_internal) - - .def_property_readonly("ppc64_flags_list", - &Header::ppc64_flags_list, - "Return a list of " RST_CLASS_REF(lief.ELF.PPC64_EFLAGS) " present in " - ":attr:`~lief.ELF.Header.processor_flag`", - py::return_value_policy::reference_internal) - - .def_property_readonly("hexagon_flags_list", - &Header::hexagon_flags_list, - "Return a list of " RST_CLASS_REF(lief.ELF.HEXAGON_EFLAGS) " present in " - ":attr:`~lief.ELF.Header.processor_flag`", - py::return_value_policy::reference_internal) - - .def_property("header_size", - static_cast>(&Header::header_size), - static_cast>(&Header::header_size), - R"delim( - Return the size of the ELF header - - This size should be 64 for an ``ELF64`` binary and 52 for an ``ELF32``. - )delim") - - .def_property("program_header_size", - static_cast>(&Header::program_header_size), - static_cast>(&Header::program_header_size), - R"delim( - Return the size of a Segment header (:class:`lief.ELF.Segment`) - - This size should be 56 for a ``ELF64`` binary and 32 for an ``ELF32``. - )delim") - - .def_property("numberof_segments", - static_cast>(&Header::numberof_segments), - static_cast>(&Header::numberof_segments), - "Return the number of program headers (segments)") - - .def_property("section_header_size", - static_cast>(&Header::section_header_size), - static_cast>(&Header::section_header_size), - R"delim( - Return the size of a Section header (:class:`lief.ELF.Section`) - - This size should be 64 for a ``ELF64`` binary and 40 for an ``ELF32``. - )delim") - - .def_property("numberof_sections", - static_cast>(&Header::numberof_sections), - static_cast>(&Header::numberof_sections), - "Return the number of sections") - - .def_property("section_name_table_idx", - static_cast>(&Header::section_name_table_idx), - static_cast>(&Header::section_name_table_idx), - "Return the section index which contains sections' names") - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - .def("__contains__", - static_cast(&Header::has), - "Check if the given " RST_CLASS_REF(lief.ELF.ARM_EFLAGS) " is present in " - ":attr:`~lief.ELF.Header.processor_flag`") - - - .def("__contains__", - static_cast(&Header::has), - "Check if the given " RST_CLASS_REF(lief.ELF.MIPS_EFLAGS) " is present in " - ":attr:`~lief.ELF.Header.processor_flag`") - - - .def("__contains__", - static_cast(&Header::has), - "Check if the given " RST_CLASS_REF(lief.ELF.PPC64_EFLAGS) " is present in " - ":attr:`~lief.ELF.Header.processor_flag`") - - - .def("__contains__", - static_cast(&Header::has), - "Check if the given " RST_CLASS_REF(lief.ELF.HEXAGON_EFLAGS) " is present in " - ":attr:`~lief.ELF.Header.processor_flag`") - - .def("__str__", - [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyNote.cpp b/vendor/lief/api/python/ELF/objects/pyNote.cpp deleted file mode 100644 index 680a3f0..0000000 --- a/vendor/lief/api/python/ELF/objects/pyNote.cpp +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/Note.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Note::*)(void) const; - -template -using setter_t = void (Note::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "Note", - R"delim( - Class which represents an ELF note. - )delim") - - .def(py::init<>(), - "Default constructor") - - .def(py::init&>(), - "Constructor from a ``name``, ``type`` and ``description``", - "name"_a, "type"_a, "description"_a) - - .def_property_readonly("details", - static_cast(&Note::details), - "Parse the given note description and return a " RST_CLASS_REF(lief.ELF.NoteDetails) " object", - py::return_value_policy::reference_internal) - - .def_property("name", - static_cast>(&Note::name), - static_cast>(&Note::name), - "Return the *name* of the note (Usually the owner)." - ) - - .def_property("type", - static_cast>(&Note::type), - static_cast>(&Note::type), - "Return the type of the note. It can be one of the " RST_CLASS_REF(lief.ELF.NOTE_TYPES) " values" - ) - - .def_property("type_core", - static_cast>(&Note::type_core), - static_cast>(&Note::type_core), - "Return the type of the note for ELF Core (ET_CORE). It Can be one of the " RST_CLASS_REF(lief.ELF.NOTE_TYPES_CORE) " values" - ) - - .def_property("description", - static_cast>(&Note::description), - static_cast>(&Note::description), - "Return the description associated with the note" - ) - - .def_property_readonly("is_core", - &Note::is_core, - "True if the note is associated with a coredump") - - .def_property_readonly("is_android", - &Note::is_android, - R"delim( - True if the current note is specific to Android. - - If true, :attr:`lief.Note.details` returns a reference to the :class:`~lief.ELF.AndroidNote` object - )delim") - - .def_property_readonly("size", - &Note::size, - "Size of the **raw** note") - - .def("__eq__", &Note::operator==) - .def("__ne__", &Note::operator!=) - .def("__hash__", - [] (const Note& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const Note& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyNoteDetails.cpp b/vendor/lief/api/python/ELF/objects/pyNoteDetails.cpp deleted file mode 100644 index dbed310..0000000 --- a/vendor/lief/api/python/ELF/objects/pyNoteDetails.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/NoteDetails.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (NoteDetails::*)(void) const; - -template -using setter_t = void (NoteDetails::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "NoteDetails") - .def(py::init<>(), - "Default ctor") - - .def("__eq__", &NoteDetails::operator==) - .def("__ne__", &NoteDetails::operator!=) - .def("__hash__", - [] (const NoteDetails& note) { - return Hash::hash(note); - }) - - .def("__str__", - [] (const NoteDetails& note) - { - std::ostringstream stream; - stream << note; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyParser.cpp b/vendor/lief/api/python/ELF/objects/pyParser.cpp deleted file mode 100644 index 39f2ea4..0000000 --- a/vendor/lief/api/python/ELF/objects/pyParser.cpp +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/Parser.hpp" -#include "LIEF/ELF/Binary.hpp" - -#include - -namespace LIEF { -namespace ELF { - -template<> -void create(py::module& m) { - - // Parser (Parser) - m.def("parse", - static_cast (*) (const std::string&, DYNSYM_COUNT_METHODS)>(&Parser::parse), - R"delim( - Parse the ELF binary from the given **file path** and return a :class:`lief.ELF.Binary` object - - For *weird* binaries (e.g sectionless) you can choose the method to use to count dynamic symbols - (:class:`lief.ELF.DYNSYM_COUNT_METHODS`). By default, the value is set to - :attr:`lief.ELF.DYNSYM_COUNT_METHODS.COUNT_AUTO` - )delim", - "filename"_a, "dynsym_count_method"_a = DYNSYM_COUNT_METHODS::COUNT_AUTO, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast(*)(const std::vector&, const std::string&, DYNSYM_COUNT_METHODS)>(&Parser::parse), - R"delim( - Parse the ELF binary from the given **list of bytes** and return a :class:`lief.ELF.Binary` object - - For *weird* binaries (e.g sectionless) you can choose the method to use to count dynamic symbols - (:class:`lief.ELF.DYNSYM_COUNT_METHODS`). By default, the value is set to - :attr:`lief.ELF.DYNSYM_COUNT_METHODS.COUNT_AUTO` - )delim", - - "raw"_a, "name"_a = "", "dynsym_count_method"_a = DYNSYM_COUNT_METHODS::COUNT_AUTO, - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name, DYNSYM_COUNT_METHODS count) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::ELF::Parser::parse(std::move(raw), name, count); - }, - R"delim( - Parse the ELF binary from a Python IO stream and return a :class:`lief.ELF.Binary` object - - For *weird* binaries (e.g sectionless) you can choose the method to use to count dynamic symbols - (:class:`lief.ELF.lief.ELF.DYNSYM_COUNT_METHODS`). By default, the value is set to - :attr:`lief.ELF.lief.ELF.DYNSYM_COUNT_METHODS.COUNT_AUTO` - )delim", - "io"_a, "name"_a = "", "dynsym_count_method"_a = DYNSYM_COUNT_METHODS::COUNT_AUTO, - py::return_value_policy::take_ownership); -} -} -} diff --git a/vendor/lief/api/python/ELF/objects/pyRelocation.cpp b/vendor/lief/api/python/ELF/objects/pyRelocation.cpp deleted file mode 100644 index b3e02cf..0000000 --- a/vendor/lief/api/python/ELF/objects/pyRelocation.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/Relocation.hpp" -#include "LIEF/ELF/Symbol.hpp" -#include "LIEF/ELF/Section.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Relocation::*)(void) const; - -template -using setter_t = void (Relocation::*)(T); - - -template<> -void create(py::module& m) { - - // Relocation object - py::class_(m, "Relocation", - R"delim( - Class that represents an ELF relocation. - )delim") - .def(py::init<>()) - .def(py::init(), "arch"_a) - .def(py::init(), - "address"_a, "type"_a = 0, "addend"_a = 0, "is_rela"_a = false) - - .def_property("addend", - static_cast>(&Relocation::addend), - static_cast>(&Relocation::addend), - "Additional value") - - .def_property("info", - static_cast>(&Relocation::info), - static_cast>(&Relocation::info), - "Extra information like the symbol index") - - .def_property("purpose", - static_cast>(&Relocation::purpose), - static_cast>(&Relocation::purpose), - R"delim( - Purpose of the relocation (:class:`~lief.ELF.RELOCATION_PURPOSES`). - - This value provides the information about how the relocation is used (PLT/GOT resolution, ``.o`` file, ...) - )delim") - - .def_property("type", - static_cast>(&Relocation::type), - static_cast>(&Relocation::type), - R"delim( - Relocation type. This value depends on the underlying architecture. - - See: - * :class:`~lief.ELF.RELOCATION_X86_64` - * :class:`~lief.ELF.RELOCATION_i386` - * :class:`~lief.ELF.RELOCATION_AARCH64` - * :class:`~lief.ELF.RELOCATION_ARM` - )delim") - - .def_property_readonly("has_symbol", - &Relocation::has_symbol, - "``True`` if a " RST_CLASS_REF(lief.ELF.Symbol) " is associated with the relocation") - - .def_property("symbol", - static_cast(&Relocation::symbol), - static_cast(&Relocation::symbol), - R"delim( - :class:`~lief.ELF.Symbol` associated with the relocation or None - if no symbol are associated with this relocation. - )delim", - py::return_value_policy::reference) - - .def_property_readonly("has_section", - &Relocation::has_section, - R"delim( - ``True`` if this relocation has a :class:`lief.ELF.Section` associated with. - - This is usually the case for object files (``.o``) - )delim") - - .def_property_readonly("section", - static_cast(&Relocation::section), - R"delim( - :class:`~lief.ELF.Section` in which the relocation is applied or None if not relevant - )delim", - py::return_value_policy::reference) - - .def_property_readonly("is_rela", - static_cast>(&Relocation::is_rela), - "``True`` if the relocation **uses** the :attr:`~lief.ELF.Relocation.addend` proprety") - - .def_property_readonly("is_rel", - static_cast>(&Relocation::is_rel), - "``True`` if the relocation **doesn't use** the :attr:`~lief.ELF.Relocation.addend` proprety") - - .def("__eq__", &Relocation::operator==) - .def("__ne__", &Relocation::operator!=) - .def("__hash__", - [] (const Relocation& relocation) { - return Hash::hash(relocation); - }) - - .def("__str__", - [] (const Relocation& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySection.cpp b/vendor/lief/api/python/ELF/objects/pySection.cpp deleted file mode 100644 index 5073f08..0000000 --- a/vendor/lief/api/python/ELF/objects/pySection.cpp +++ /dev/null @@ -1,193 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" -#include "pyIterators.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/Abstract/Section.hpp" -#include "LIEF/ELF/Section.hpp" -#include "LIEF/ELF/Segment.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Section::*)(void) const; - -template -using setter_t = void (Section::*)(T); - -template -using no_const_getter = T (Section::*)(void); - - -template<> -void create
(py::module& m) { - - // Section object - py::class_ sec(m, "Section", - R"delim( - Class which represents an ELF section. - )delim"); - - init_ref_iterator(sec, "it_segments"); - - sec - .def(py::init<>(), - "Default constructor") - - .def("as_frame", - &Section::as_frame, - py::return_value_policy::reference_internal) - - .def_property_readonly("is_frame", - &Section::is_frame) - - .def(py::init(), - "Constructor from a name and a section type", - "name"_a, "type"_a = ELF_SECTION_TYPES::SHT_PROGBITS) - - .def(py::init([] (Section& section, std::vector& content, ELF_CLASS type) { - return new Section(content.data(), type); - })) - - .def_property("type", - static_cast>(&Section::type), - static_cast>(&Section::type), - "Return the " RST_CLASS_REF(lief.ELF.SECTION_TYPES) "") - - .def_property("flags", - static_cast>(&Section::flags), - static_cast>(&Section::flags), - "Return the section's flags as an integer") - - .def_property_readonly("flags_list", - &Section::flags_list, - "Return section's flags as a list of " RST_CLASS_REF(lief.ELF.SECTION_FLAGS) "") - - .def_property("file_offset", - static_cast>(&Section::file_offset), - static_cast>(&Section::file_offset), - "Offset of the section's content") - - .def_property_readonly("original_size", - static_cast>(&Section::original_size), - R"delim( - Original size of the section's data. - - This value is used by the :class:`~lief.ELF.Builder` to determine if it needs - to be relocated to avoid an override of the data - )delim") - - .def_property("alignment", - static_cast>(&Section::alignment), - static_cast>(&Section::alignment), - "Section alignment") - - .def_property("information", - static_cast>(&Section::information), - static_cast>(&Section::information), - "Section information (this value depends on the section)") - - .def_property("entry_size", - static_cast>(&Section::entry_size), - static_cast>(&Section::entry_size), - R"delim( - This property returns the size of an element in the case of a section that - contains an array. - - :Example: - - The `.dynamic` section contains an array of :class:`~lief.ELF.DynamicEntry`. As the - size of the raw C structure of this entry is 0x10 (``sizeof(Elf64_Dyn)``) - in a ELF64, the :attr:`~lief.ELF.Section.entry_size`, - is set to this value. - )delim") - - .def_property("link", - static_cast>(&Section::link), - static_cast>(&Section::link), - "Index to another section") - - .def_property_readonly("segments", - static_cast>(&Section::segments), - "Return segment(s) associated with the given section", - py::return_value_policy::reference_internal) - - .def("clear", - &Section::clear, - "Clear the content of the section with the given ``value``", - "value"_a = 0, - py::return_value_policy::reference) - - .def("add", - &Section::add, - "Add the given " RST_CLASS_REF(lief.ELF.SECTION_FLAGS) " to the list of " - ":attr:`~lief.ELF.Section.flags`", - "flag"_a) - - .def("remove", - &Section::remove, - "Remove the given " RST_CLASS_REF(lief.ELF.SECTION_FLAGS) " from the list of " - ":attr:`~lief.ELF.Section.flags`", - "flag"_a) - - .def("has", - static_cast(&Section::has), - "Check if the given " RST_CLASS_REF(lief.ELF.SECTION_FLAGS) " is present", - "flag"_a) - - .def("has", - static_cast(&Section::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Segment) " is present " - "in :attr:`~lief.ELF.Section.segments`", - "segment"_a) - - .def("__eq__", &Section::operator==) - .def("__ne__", &Section::operator!=) - .def("__hash__", - [] (const Section& section) { - return Hash::hash(section); - }) - - .def(py::self += ELF_SECTION_FLAGS()) - .def(py::self -= ELF_SECTION_FLAGS()) - - .def("__contains__", - static_cast(&Section::has), - "Check if the given " RST_CLASS_REF(lief.ELF.SECTION_FLAGS) " is present") - - - .def("__contains__", - static_cast(&Section::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Segment) " is present " - "in :attr:`~lief.ELF.Section.segments`") - - .def("__str__", - [] (const Section& section) - { - std::ostringstream stream; - stream << section; - return stream.str(); - }); -} - - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySegment.cpp b/vendor/lief/api/python/ELF/objects/pySegment.cpp deleted file mode 100644 index 7476259..0000000 --- a/vendor/lief/api/python/ELF/objects/pySegment.cpp +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include - - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/Segment.hpp" -#include "LIEF/ELF/Section.hpp" - -#include "pyIterators.hpp" -#include "pyELF.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Segment::*)(void) const; - -template -using setter_t = void (Segment::*)(T); - -template -using no_const_getter = T (Segment::*)(void); - - -template<> -void create(py::module& m) { - py::class_ seg(m, "Segment", - R"delim( - Class which represents the ELF segments - )delim"); - - init_ref_iterator(seg, "it_sections"); - - seg - .def(py::init<>()) - .def_static("from_raw", - [] (py::bytes raw) -> py::object { - const std::string& bytes_as_str = raw; - std::vector cpp_raw = {std::begin(bytes_as_str), std::end(bytes_as_str)}; - auto* f_ptr = static_cast(*)(const std::vector&)>(&Segment::from_raw); - return error_or(f_ptr, std::move(cpp_raw)); - }) - - .def_property("type", - static_cast>(&Segment::type), - static_cast>(&Segment::type), - "Segment's type: " RST_CLASS_REF(lief.ELF.SEGMENT_TYPES) "") - - .def_property("flags", - static_cast>(&Segment::flags), - static_cast>(&Segment::flags), - "The flag permissions associated with this segment") - - .def_property("file_offset", - static_cast>(&Segment::file_offset), - static_cast>(&Segment::file_offset), - "The file offset of the data associated with this segment") - - .def_property("virtual_address", - static_cast>(&Segment::virtual_address), - static_cast>(&Segment::virtual_address), - R"delim( - The virtual address of the segment. - - .. warning:: - The ELF format specifications require the following relationship: - - .. math:: - \text{virtual address} \equiv \text{file offset} \pmod{\text{page size}} - \text{virtual address} \equiv \text{file offset} \pmod{\text{alignment}} - )delim") - - .def_property("physical_address", - static_cast>(&Segment::physical_address), - static_cast>(&Segment::physical_address), - R"delim( - The physical address of the segment. - This value is not really relevant on systems like Linux or Android. On the other hand, - Qualcomm trustlets might use this value. - - Usually this value matches :attr:`~lief.ELF.Segment.virtual_address` - )delim") - - .def_property("physical_size", - static_cast>(&Segment::physical_size), - static_cast>(&Segment::physical_size), - "The **file** size of the data associated with this segment") - - .def_property("virtual_size", - static_cast>(&Segment::virtual_size), - static_cast>(&Segment::virtual_size), - R"delim( - The in-memory size of this segment. - - Usually, if the ``.bss`` segment is wrapped by this segment - then, virtual_size is larger than physical_size - )delim") - - .def_property("alignment", - static_cast>(&Segment::alignment), - static_cast>(&Segment::alignment), - "The offset alignment of the segment") - - .def_property("content", - [] (const Segment& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>>(&Segment::content), - "The raw data associated with this segment.") - - .def("add", - &Segment::add, - "Add the given " RST_CLASS_REF(lief.ELF.SEGMENT_FLAGS) " to the list of " - ":attr:`~lief.ELF.Segment.flags`", - "flag"_a) - - .def("remove", - &Segment::remove, - "Remove the given " RST_CLASS_REF(lief.ELF.SEGMENT_FLAGS) " from the list of " - ":attr:`~lief.ELF.Segment.flags`", - "flag"_a) - - .def("has", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.SEGMENT_FLAGS) " is present", - "flag"_a) - - .def("has", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Section) " is present " - "in :attr:`~lief.ELF.Segment.sections`", - "section"_a) - - .def("has", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Section) " 's name is present " - "in :attr:`~lief.ELF.Segment.sections`", - "section_name"_a) - - .def_property_readonly("sections", - static_cast>(&Segment::sections), - "Iterator over the " RST_CLASS_REF(lief.ELF.Section) " wrapped by this segment", - py::return_value_policy::reference_internal) - - .def("__eq__", &Segment::operator==) - .def("__ne__", &Segment::operator!=) - .def("__hash__", - [] (const Segment& segment) { - return Hash::hash(segment); - }) - - .def(py::self += ELF_SEGMENT_FLAGS()) - .def(py::self -= ELF_SEGMENT_FLAGS()) - - .def("__contains__", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.SEGMENT_FLAGS) " is present") - - .def("__contains__", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Section) " is present " - "in :attr:`~lief.ELF.Segment.sections`") - - .def("__contains__", - static_cast(&Segment::has), - "Check if the given " RST_CLASS_REF(lief.ELF.Section) " 's name is present " - "in :attr:`~lief.ELF.Segment.sections`") - - .def("__str__", - [] (const Segment& segment) - { - std::ostringstream stream; - stream << segment; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbol.cpp b/vendor/lief/api/python/ELF/objects/pySymbol.cpp deleted file mode 100644 index 7fed486..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbol.cpp +++ /dev/null @@ -1,157 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" -#include "pyIterators.hpp" - -#include "LIEF/ELF/Symbol.hpp" -#include "LIEF/ELF/SymbolVersion.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/Abstract/Symbol.hpp" - - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (Symbol::*)(void) const; - -template -using setter_t = void (Symbol::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "Symbol", - R"delim( - "Class which represents an ELF symbol" - )delim") - .def(py::init<>()) - .def_property_readonly("demangled_name", - &Symbol::demangled_name, - "Symbol's name demangled or an empty string if the demangling is not possible/failed") - - .def_property("type", - static_cast>(&Symbol::type), - static_cast>(&Symbol::type), - "The symbol's type provides a general classification for the associated entity. " - "See: " RST_CLASS_REF(lief.ELF.SYMBOL_TYPES) "") - - .def_property("binding", - static_cast>(&Symbol::binding), - static_cast>(&Symbol::binding), - "A symbol's binding determines the linkage visibility and behavior. " - "See " RST_CLASS_REF(lief.ELF.SYMBOL_BINDINGS) "") - - .def_property("information", - static_cast>(&Symbol::information), - static_cast>(&Symbol::information), - "This property specifies the symbol's type and binding attributes") - - .def_property("other", - static_cast>(&Symbol::other), - static_cast>(&Symbol::other), - "Alias for: " RST_ATTR_REF(lief.ELF.Symbol.visibility) "") - - .def_property("visibility", - static_cast>(&Symbol::visibility), - static_cast>(&Symbol::visibility), - R"delim( - Symbol :class:`~lief.ELF.SYMBOL_VISIBILITY`. - It's basically an alias on :attr:`~lief.ELF.Symbol.other` - )delim") - - .def_property("value", // Even though it is already defined in the base class (Abstract/Symbol) - // We keep the definition to provide a dedicated documentation - static_cast>(&Symbol::value), - static_cast>(&Symbol::value), - R"delim( - This member has different menaing depending on the symbol's type and the type of the ELF file (library, object, ...) - - - In relocatable files, this property contains the alignment constraints - of the symbol for which the section index is `SHN_COMMON`. - - In relocatable files, can also contain a section's offset for a defined symbol. - That is, `value` is an offset from the beginning of the section associated with this symbol. - - In executable and libraries, this property contains a virtual address. - )delim") - - .def_property("size", - static_cast>(&Symbol::size), - static_cast>(&Symbol::size), - "Many symbols have associated sizes. For example, a data object's size is the number of " - "bytes contained in the object. This member holds `0` if the symbol has no size or " - "an unknown size.") - - .def_property("shndx", - static_cast>(&Symbol::shndx), - static_cast>(&Symbol::shndx), - "Section index associated with the symbol") - - .def_property_readonly("has_version", - &Symbol::has_version, - "Check if this symbols has a " RST_CLASS_REF(lief.ELF.SymbolVersion) "") - - .def_property_readonly("symbol_version", - static_cast(&Symbol::symbol_version), - R"delim( - Return the :class:`~lief.ELF.SymbolVersion` associated with this symbol - - It returns None if no version is tied to this symbol. - )delim", - py::return_value_policy::reference_internal) - - .def_property_readonly("is_static", - &Symbol::is_static, - "True if the symbol is a static one (i.e. from the ``.symtab`` section") - - .def_property_readonly("is_function", - &Symbol::is_function, - "True if the symbol is a function") - - .def_property_readonly("is_variable", - &Symbol::is_variable, - "True if the symbol is a variable") - - .def_property("exported", - &Symbol::is_exported, &Symbol::set_exported, - "Whether the symbol is **exported**") - - .def_property("imported", - &Symbol::is_imported, &Symbol::set_imported, - "Whether the symbol is **imported**") - - .def("__eq__", &Symbol::operator==) - .def("__ne__", &Symbol::operator!=) - .def("__hash__", - [] (const Symbol& symbol) { - return Hash::hash(symbol); - }) - - - .def("__str__", - [] (const Symbol& symbol) { - std::ostringstream stream; - stream << symbol; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbolVersion.cpp b/vendor/lief/api/python/ELF/objects/pySymbolVersion.cpp deleted file mode 100644 index c34d1d0..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbolVersion.cpp +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/SymbolVersion.hpp" -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SymbolVersionAux.hpp" -#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SymbolVersion::*)(void) const; - -template -using setter_t = void (SymbolVersion::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "SymbolVersion") - .def(py::init<>(),"Default constructor") - .def(py::init(), "Constructor from :attr:`~lief.SymbolVersion.value`") - - .def_property_readonly_static("local", - [] (const py::object&) { - return SymbolVersion::local(); - }, - "Generate a *local* " RST_CLASS_REF(lief.ELF.SymbolVersion) "") - - .def_property_readonly_static("global_", - [] (const py::object&) { - return SymbolVersion::global(); - }, - "Generate a *global* " RST_CLASS_REF(lief.ELF.SymbolVersion) "") - - .def_property("value", - static_cast>(&SymbolVersion::value), - static_cast>(&SymbolVersion::value), - R"delim( - Value associated with the symbol. - - If the given SymbolVersion hasn't Auxiliary version: - - - `0` : The symbol is local - - `1` : The symbol is global - - All other values are used for versions in the own object or in any of - the dependencies. This is the version the symbol is tight to. - )delim") - - .def_property_readonly("has_auxiliary_version", - &SymbolVersion::has_auxiliary_version, - "Check if this symbols has a " RST_CLASS_REF(lief.ELF.SymbolVersionAux) "") - - .def_property( - "symbol_version_auxiliary", - static_cast(&SymbolVersion::symbol_version_auxiliary), - static_cast(&SymbolVersion::symbol_version_auxiliary), - R"delim( - Return the :class:`~lief.ELF.SymbolVersionAux` associated with this version or None if not present. - - The value can be changed by assigning a :class:`~lief.ELF.SymbolVersionAuxRequirement` which - must already exist in the :class:`~lief.ELF.SymbolVersionRequirement`. Once can use - :meth:`~lief.ELF.SymbolVersionAuxRequirement.add_aux_requirement` to add a new - :class:`~lief.ELF.SymbolVersionAuxRequirement`. - )delim", - py::return_value_policy::reference_internal) - - - .def("__eq__", &SymbolVersion::operator==) - .def("__ne__", &SymbolVersion::operator!=) - .def("__hash__", - [] (const SymbolVersion& sv) { - return Hash::hash(sv); - }) - - .def("__str__", - [] (const SymbolVersion& symbolVersion) - { - std::ostringstream stream; - stream << symbolVersion; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbolVersionAux.cpp b/vendor/lief/api/python/ELF/objects/pySymbolVersionAux.cpp deleted file mode 100644 index 85099b9..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbolVersionAux.cpp +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SymbolVersionAux.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SymbolVersionAux::*)(void) const; - -template -using setter_t = void (SymbolVersionAux::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "SymbolVersionAux", - "Class which represents an Auxiliary Symbol version") - - .def_property("name", - [] (const SymbolVersionAux& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&SymbolVersionAux::name), - "Symbol's name (e.g. ``GLIBC_2.2.5``)") - - .def("__eq__", &SymbolVersionAux::operator==) - .def("__ne__", &SymbolVersionAux::operator!=) - .def("__hash__", - [] (const SymbolVersionAux& sva) { - return Hash::hash(sva); - }) - - .def("__str__", - [] (const SymbolVersionAux& symbolVersionAux) - { - std::ostringstream stream; - stream << symbolVersionAux; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbolVersionAuxRequirement.cpp b/vendor/lief/api/python/ELF/objects/pySymbolVersionAuxRequirement.cpp deleted file mode 100644 index 4fdf655..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbolVersionAuxRequirement.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" - -#include -#include - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SymbolVersionAuxRequirement::*)(void) const; - -template -using setter_t = void (SymbolVersionAuxRequirement::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "SymbolVersionAuxRequirement") - .def(py::init<>(),"Default constructor") - - .def_property("hash", - static_cast>(&SymbolVersionAuxRequirement::hash), - static_cast>(&SymbolVersionAuxRequirement::hash), - "Hash value of the dependency name (use ELF hashing function)") - - .def_property("flags", - static_cast>(&SymbolVersionAuxRequirement::flags), - static_cast>(&SymbolVersionAuxRequirement::flags), - "Bitmask of flags") - - .def_property("other", - static_cast>(&SymbolVersionAuxRequirement::other), - static_cast>(&SymbolVersionAuxRequirement::other), - R"delim( - It returns the unique version index for the file which is used in the - version symbol table. If the highest bit (bit 15) is set this - is a hidden symbol which cannot be referenced from outside the - object. - )delim") - - - .def("__eq__", &SymbolVersionAuxRequirement::operator==) - .def("__ne__", &SymbolVersionAuxRequirement::operator!=) - .def("__hash__", - [] (const SymbolVersionAuxRequirement& svar) { - return Hash::hash(svar); - }) - - .def("__str__", - [] (const SymbolVersionAuxRequirement& symbolVersionAux) - { - std::ostringstream stream; - stream << symbolVersionAux; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbolVersionDefinition.cpp b/vendor/lief/api/python/ELF/objects/pySymbolVersionDefinition.cpp deleted file mode 100644 index a3bc017..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbolVersionDefinition.cpp +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyIterators.hpp" -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SymbolVersionDefinition.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SymbolVersionDefinition::*)(void) const; - -template -using setter_t = void (SymbolVersionDefinition::*)(T); - -template -using no_const_getter = T (SymbolVersionDefinition::*)(void); - - -template<> -void create(py::module& m) { - - py::class_ sym_ver_def(m, "SymbolVersionDefinition", - "Class which represents an entry defined in ``DT_VERDEF`` or ``.gnu.version_d``"); - - init_ref_iterator(sym_ver_def, "it_version_aux"); - sym_ver_def - .def_property("version", - static_cast>(&SymbolVersionDefinition::version), - static_cast>(&SymbolVersionDefinition::version), - R"delim( - Version revision. Should be 1 - - This field should always have the value ``1``. It will be changed - if the versioning implementation has to be changed in an incompatible way. - )delim") - - .def_property("flags", - static_cast>(&SymbolVersionDefinition::flags), - static_cast>(&SymbolVersionDefinition::flags), - "Version information") - - .def_property("hash", - static_cast>(&SymbolVersionDefinition::hash), - static_cast>(&SymbolVersionDefinition::hash), - "Hash value of the symbol's name (using ELF hash function)") - - .def_property_readonly("auxiliary_symbols", - static_cast>(&SymbolVersionDefinition::symbols_aux), - py::return_value_policy::reference_internal) - - .def("__eq__", &SymbolVersionDefinition::operator==) - .def("__ne__", &SymbolVersionDefinition::operator!=) - .def("__hash__", - [] (const SymbolVersionDefinition& svd) { - return Hash::hash(svd); - }) - - .def("__str__", - [] (const SymbolVersionDefinition& svd) - { - std::ostringstream stream; - stream << svd; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySymbolVersionRequirement.cpp b/vendor/lief/api/python/ELF/objects/pySymbolVersionRequirement.cpp deleted file mode 100644 index 25d38f0..0000000 --- a/vendor/lief/api/python/ELF/objects/pySymbolVersionRequirement.cpp +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SymbolVersionRequirement.hpp" - -#include "pyIterators.hpp" -#include "pyELF.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SymbolVersionRequirement::*)(void) const; - -template -using setter_t = void (SymbolVersionRequirement::*)(T); - -template -using no_const_getter = T (SymbolVersionRequirement::*)(void); - - -template<> -void create(py::module& m) { - - // Symbol Version Requirement object - py::class_ sym_ver_req(m, "SymbolVersionRequirement", - "Class which represents an entry in the ``DT_VERNEED`` or ``.gnu.version_r`` table"); - - init_ref_iterator(sym_ver_req, "it_aux_requirement"); - - sym_ver_req - .def_property("version", - static_cast>(&SymbolVersionRequirement::version), - static_cast>(&SymbolVersionRequirement::version), - "Version revision. Should be 1") - - .def_property("name", - static_cast>(&SymbolVersionRequirement::name), - static_cast>(&SymbolVersionRequirement::name), - "Library's name associated with this requirement (e.g. ``libc.so.6``)") - - .def("get_auxiliary_symbols", - static_cast>(&SymbolVersionRequirement::auxiliary_symbols), - "Auxiliary entries (iterator over " RST_CLASS_REF(lief.ELF.SymbolVersionAuxRequirement) ")", - py::return_value_policy::reference_internal) - - .def("add_auxiliary_requirement", - static_cast(&SymbolVersionRequirement::add_aux_requirement), - "Add an auxiliary version requirement to the existing entries") - - .def("__eq__", &SymbolVersionRequirement::operator==) - .def("__ne__", &SymbolVersionRequirement::operator!=) - .def("__hash__", - [] (const SymbolVersionRequirement& svr) { - return Hash::hash(svr); - }) - - .def("__str__", - [] (const SymbolVersionRequirement& symbolVersionRequirement) - { - std::ostringstream stream; - stream << symbolVersionRequirement; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/ELF/objects/pySysvHash.cpp b/vendor/lief/api/python/ELF/objects/pySysvHash.cpp deleted file mode 100644 index d495721..0000000 --- a/vendor/lief/api/python/ELF/objects/pySysvHash.cpp +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "pyELF.hpp" - -#include "LIEF/ELF/hash.hpp" -#include "LIEF/ELF/SysvHash.hpp" - -namespace LIEF { -namespace ELF { - -template -using getter_t = T (SysvHash::*)() const; - -template -using setter_t = void (SysvHash::*)(T); - -template<> -void create(py::module& m) { - - py::class_(m, "SysvHash", - R"delim( - Class which represents the SYSV hash for the symbols resolution - - References: - - * http://www.linker-aliens.org/blogs/ali/entry/gnu_hash_elf_sections/ - * https://docs.oracle.com/cd/E23824_01/html/819-0690/chapter6-48031.html - )delim") - .def(py::init<>()) - - .def_property_readonly("nbucket", - &SysvHash::nbucket, - "Return the number of buckets") - - .def_property("nchain", - static_cast>(&SysvHash::nchain), - static_cast>(&SysvHash::nchain), - "Return the number of *chains* (symbol table index)") - - .def_property_readonly("buckets", - &SysvHash::buckets, - "Buckets values", - py::return_value_policy::reference_internal) - - .def_property_readonly("chains", - &SysvHash::chains, - "Chains values", - py::return_value_policy::reference_internal) - - .def("__eq__", &SysvHash::operator==) - .def("__ne__", &SysvHash::operator!=) - .def("__hash__", - [] (const SysvHash& sysvhash) { - return Hash::hash(sysvhash); - }) - - - .def("__str__", - [] (const SysvHash& sysvhash) - { - std::ostringstream stream; - stream << sysvhash; - std::string str = stream.str(); - return str; - }); - - - -} - -} -} diff --git a/vendor/lief/api/python/ELF/pyELF.cpp b/vendor/lief/api/python/ELF/pyELF.cpp deleted file mode 100644 index 3525055..0000000 --- a/vendor/lief/api/python/ELF/pyELF.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" - - -namespace LIEF { -namespace ELF { -void init_python_module(py::module& m) { - py::module LIEF_ELF_module = m.def_submodule("ELF", "Python API for the ELF format"); - - init_enums(LIEF_ELF_module); - init_objects(LIEF_ELF_module); - - py::module LIEF_ELF32_module = LIEF_ELF_module.def_submodule("ELF32", ""); - init_ELF32_sizes(LIEF_ELF32_module); - - py::module LIEF_ELF64_module = LIEF_ELF_module.def_submodule("ELF64", ""); - init_ELF64_sizes(LIEF_ELF64_module); -} - -void init_objects(py::module& m) { - CREATE(Parser, m); - CREATE(SymbolVersion, m); - CREATE(Binary, m); - CREATE(Header, m); - CREATE(Section, m); - CREATE(Segment, m); - CREATE(Symbol, m); - CREATE(Relocation, m); - CREATE(SymbolVersionAux, m); - CREATE(SymbolVersionAuxRequirement, m); - CREATE(SymbolVersionDefinition,m ); - CREATE(SymbolVersionRequirement, m); - CREATE(DynamicEntry, m); - CREATE(DynamicEntryLibrary, m); - CREATE(DynamicSharedObject, m); - CREATE(DynamicEntryArray, m); - CREATE(DynamicEntryRpath, m); - CREATE(DynamicEntryRunPath, m); - CREATE(DynamicEntryFlags, m); - CREATE(GnuHash, m); - CREATE(SysvHash, m); - CREATE(Builder, m); - CREATE(Note, m); - CREATE(NoteDetails, m); - CREATE(AndroidNote, m); - CREATE(NoteAbi, m); - CREATE(CorePrPsInfo, m); - CREATE(CoreFile, m); - CREATE(CoreFileEntry, m); - CREATE(CorePrStatus, m); - CREATE(CoreAuxv, m); - CREATE(CoreSigInfo, m); -} - -} -} diff --git a/vendor/lief/api/python/ELF/pyELF.hpp b/vendor/lief/api/python/ELF/pyELF.hpp deleted file mode 100644 index 6781c65..0000000 --- a/vendor/lief/api/python/ELF/pyELF.hpp +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ELF_H_ -#define PY_LIEF_ELF_H_ - -#include -#include -#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -namespace LIEF { -namespace ELF { - -class Parser; -class Binary; -class Header; -class Section; -class Segment; -class Symbol; -class Relocation; -class SymbolVersion; -class SymbolVersionAux; -class SymbolVersionRequirement; -class SymbolVersionDefinition; -class SymbolVersionAuxRequirement; -class DynamicEntry; -class DynamicEntryLibrary; -class DynamicSharedObject; -class DynamicEntryArray; -class DynamicEntryRpath; -class DynamicEntryRunPath; -class DynamicEntryFlags; -class GnuHash; -class SysvHash; -class Builder; -class Note; -class NoteDetails; -class AndroidNote; -class NoteAbi; -class CorePrPsInfo; -class CoreFile; -class CoreFileEntry; -class CorePrStatus; -class CoreAuxv; -class CoreSigInfo; - -template -void create(py::module&); - -void init_python_module(py::module& m); -void init_objects(py::module&); -void init_enums(py::module&); - -void init_ELF32_sizes(py::module&); -void init_ELF64_sizes(py::module&); - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(Binary); -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(Section); -SPECIALIZE_CREATE(Segment); -SPECIALIZE_CREATE(Symbol); -SPECIALIZE_CREATE(Relocation); -SPECIALIZE_CREATE(SymbolVersion); -SPECIALIZE_CREATE(SymbolVersionAux); -SPECIALIZE_CREATE(SymbolVersionRequirement); -SPECIALIZE_CREATE(SymbolVersionDefinition); -SPECIALIZE_CREATE(SymbolVersionAuxRequirement); -SPECIALIZE_CREATE(DynamicEntry); -SPECIALIZE_CREATE(DynamicEntryLibrary); -SPECIALIZE_CREATE(DynamicSharedObject); -SPECIALIZE_CREATE(DynamicEntryArray); -SPECIALIZE_CREATE(DynamicEntryRpath); -SPECIALIZE_CREATE(DynamicEntryRunPath); -SPECIALIZE_CREATE(DynamicEntryFlags); -SPECIALIZE_CREATE(GnuHash); -SPECIALIZE_CREATE(SysvHash); -SPECIALIZE_CREATE(Builder); -SPECIALIZE_CREATE(Note); -SPECIALIZE_CREATE(NoteDetails); -SPECIALIZE_CREATE(AndroidNote); -SPECIALIZE_CREATE(NoteAbi); -SPECIALIZE_CREATE(CorePrPsInfo); -SPECIALIZE_CREATE(CoreFile); -SPECIALIZE_CREATE(CoreFileEntry); -SPECIALIZE_CREATE(CorePrStatus); -SPECIALIZE_CREATE(CoreAuxv); -SPECIALIZE_CREATE(CoreSigInfo); - -} -} - -PYBIND11_MAKE_OPAQUE(LIEF::ELF::CoreFile::files_t); - -#endif diff --git a/vendor/lief/api/python/ELF/pyEnums.cpp b/vendor/lief/api/python/ELF/pyEnums.cpp deleted file mode 100644 index b8fb943..0000000 --- a/vendor/lief/api/python/ELF/pyEnums.cpp +++ /dev/null @@ -1,1277 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyELF.hpp" -#include "enums_wrapper.hpp" - -#include "LIEF/ELF/enums.hpp" -#include "LIEF/ELF/EnumToString.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace ELF { - -void init_enums(py::module& m) { - - LIEF::enum_(m, "ELF_CLASS") - .value(PY_ENUM(ELF_CLASS::ELFCLASSNONE)) - .value(PY_ENUM(ELF_CLASS::ELFCLASS32)) - .value(PY_ENUM(ELF_CLASS::ELFCLASS64)); - - - LIEF::enum_(m, "ELF_DATA") - .value(PY_ENUM(ELF_DATA::ELFDATANONE)) - .value(PY_ENUM(ELF_DATA::ELFDATA2LSB)) - .value(PY_ENUM(ELF_DATA::ELFDATA2MSB)); - - LIEF::enum_(m, "OS_ABI") - .value(PY_ENUM(OS_ABI::ELFOSABI_SYSTEMV)) - .value(PY_ENUM(OS_ABI::ELFOSABI_HPUX)) - .value(PY_ENUM(OS_ABI::ELFOSABI_NETBSD)) - .value(PY_ENUM(OS_ABI::ELFOSABI_LINUX)) - .value("GNU", OS_ABI::ELFOSABI_GNU) - .value(PY_ENUM(OS_ABI::ELFOSABI_HURD)) - .value(PY_ENUM(OS_ABI::ELFOSABI_SOLARIS)) - .value(PY_ENUM(OS_ABI::ELFOSABI_AIX)) - .value(PY_ENUM(OS_ABI::ELFOSABI_IRIX)) - .value(PY_ENUM(OS_ABI::ELFOSABI_FREEBSD)) - .value(PY_ENUM(OS_ABI::ELFOSABI_TRU64)) - .value(PY_ENUM(OS_ABI::ELFOSABI_MODESTO)) - .value(PY_ENUM(OS_ABI::ELFOSABI_OPENBSD)) - .value(PY_ENUM(OS_ABI::ELFOSABI_OPENVMS)) - .value(PY_ENUM(OS_ABI::ELFOSABI_NSK)) - .value(PY_ENUM(OS_ABI::ELFOSABI_AROS)) - .value(PY_ENUM(OS_ABI::ELFOSABI_FENIXOS)) - .value(PY_ENUM(OS_ABI::ELFOSABI_CLOUDABI)) - .value(PY_ENUM(OS_ABI::ELFOSABI_AMDGPU_HSA)) - .value("C6000_ELFABI", OS_ABI::ELFOSABI_C6000_ELFABI) - .value(PY_ENUM(OS_ABI::ELFOSABI_C6000_LINUX)) - .value(PY_ENUM(OS_ABI::ELFOSABI_ARM)) - .value(PY_ENUM(OS_ABI::ELFOSABI_STANDALONE)); - - // Enum for the *e_type* of ElfXX_Ehdr - LIEF::enum_(m, "E_TYPE") - .value(PY_ENUM(E_TYPE::ET_NONE)) - .value(PY_ENUM(E_TYPE::ET_REL)) - .value(PY_ENUM(E_TYPE::ET_EXEC)) - .value(PY_ENUM(E_TYPE::ET_DYN)) - .value(PY_ENUM(E_TYPE::ET_CORE)) - .value(PY_ENUM(E_TYPE::ET_LOPROC)) - .value(PY_ENUM(E_TYPE::ET_HIPROC)); - - //! Enum for the *e_version* of ElfXX_Ehdr; - LIEF::enum_(m, "VERSION") - .value(PY_ENUM(VERSION::EV_NONE)) - .value(PY_ENUM(VERSION::EV_CURRENT)); - - // Enum for the *e_machine* of ElfXX_Ehdr - LIEF::enum_(m, "ARCH") - .value(PY_ENUM(ARCH::EM_NONE)) - .value(PY_ENUM(ARCH::EM_M32)) - .value(PY_ENUM(ARCH::EM_SPARC)) - .value(PY_ENUM(ARCH::EM_386)) - .value(PY_ENUM(ARCH::EM_68K)) - .value(PY_ENUM(ARCH::EM_88K)) - .value(PY_ENUM(ARCH::EM_IAMCU)) - .value(PY_ENUM(ARCH::EM_860)) - .value(PY_ENUM(ARCH::EM_MIPS)) - .value(PY_ENUM(ARCH::EM_S370)) - .value(PY_ENUM(ARCH::EM_MIPS_RS3_LE)) - .value(PY_ENUM(ARCH::EM_PARISC)) - .value(PY_ENUM(ARCH::EM_VPP500)) - .value(PY_ENUM(ARCH::EM_SPARC32PLUS)) - .value(PY_ENUM(ARCH::EM_960)) - .value(PY_ENUM(ARCH::EM_PPC)) - .value(PY_ENUM(ARCH::EM_PPC64)) - .value(PY_ENUM(ARCH::EM_S390)) - .value(PY_ENUM(ARCH::EM_SPU)) - .value(PY_ENUM(ARCH::EM_V800)) - .value(PY_ENUM(ARCH::EM_FR20)) - .value(PY_ENUM(ARCH::EM_RH32)) - .value(PY_ENUM(ARCH::EM_RCE)) - .value(PY_ENUM(ARCH::EM_ARM)) - .value(PY_ENUM(ARCH::EM_ALPHA)) - .value(PY_ENUM(ARCH::EM_SH)) - .value(PY_ENUM(ARCH::EM_SPARCV9)) - .value(PY_ENUM(ARCH::EM_TRICORE)) - .value(PY_ENUM(ARCH::EM_ARC)) - .value(PY_ENUM(ARCH::EM_H8_300)) - .value(PY_ENUM(ARCH::EM_H8_300H)) - .value(PY_ENUM(ARCH::EM_H8S)) - .value(PY_ENUM(ARCH::EM_H8_500)) - .value(PY_ENUM(ARCH::EM_IA_64)) - .value(PY_ENUM(ARCH::EM_MIPS_X)) - .value(PY_ENUM(ARCH::EM_COLDFIRE)) - .value(PY_ENUM(ARCH::EM_68HC12)) - .value(PY_ENUM(ARCH::EM_MMA)) - .value(PY_ENUM(ARCH::EM_PCP)) - .value(PY_ENUM(ARCH::EM_NCPU)) - .value(PY_ENUM(ARCH::EM_NDR1)) - .value(PY_ENUM(ARCH::EM_STARCORE)) - .value(PY_ENUM(ARCH::EM_ME16)) - .value(PY_ENUM(ARCH::EM_ST100)) - .value(PY_ENUM(ARCH::EM_TINYJ)) - .value(PY_ENUM(ARCH::EM_X86_64)) - .value(PY_ENUM(ARCH::EM_PDSP)) - .value(PY_ENUM(ARCH::EM_PDP10)) - .value(PY_ENUM(ARCH::EM_PDP11)) - .value(PY_ENUM(ARCH::EM_FX66)) - .value(PY_ENUM(ARCH::EM_ST9PLUS)) - .value(PY_ENUM(ARCH::EM_ST7)) - .value(PY_ENUM(ARCH::EM_68HC16)) - .value(PY_ENUM(ARCH::EM_68HC11)) - .value(PY_ENUM(ARCH::EM_68HC08)) - .value(PY_ENUM(ARCH::EM_68HC05)) - .value(PY_ENUM(ARCH::EM_SVX)) - .value(PY_ENUM(ARCH::EM_ST19)) - .value(PY_ENUM(ARCH::EM_VAX)) - .value(PY_ENUM(ARCH::EM_CRIS)) - .value(PY_ENUM(ARCH::EM_JAVELIN)) - .value(PY_ENUM(ARCH::EM_FIREPATH)) - .value(PY_ENUM(ARCH::EM_ZSP)) - .value(PY_ENUM(ARCH::EM_MMIX)) - .value(PY_ENUM(ARCH::EM_HUANY)) - .value(PY_ENUM(ARCH::EM_PRISM)) - .value(PY_ENUM(ARCH::EM_AVR)) - .value(PY_ENUM(ARCH::EM_FR30)) - .value(PY_ENUM(ARCH::EM_D10V)) - .value(PY_ENUM(ARCH::EM_D30V)) - .value(PY_ENUM(ARCH::EM_V850)) - .value(PY_ENUM(ARCH::EM_M32R)) - .value(PY_ENUM(ARCH::EM_MN10300)) - .value(PY_ENUM(ARCH::EM_MN10200)) - .value(PY_ENUM(ARCH::EM_PJ)) - .value(PY_ENUM(ARCH::EM_OPENRISC)) - .value(PY_ENUM(ARCH::EM_ARC_COMPACT)) - .value(PY_ENUM(ARCH::EM_XTENSA)) - .value(PY_ENUM(ARCH::EM_VIDEOCORE)) - .value(PY_ENUM(ARCH::EM_TMM_GPP)) - .value(PY_ENUM(ARCH::EM_NS32K)) - .value(PY_ENUM(ARCH::EM_TPC)) - .value(PY_ENUM(ARCH::EM_SNP1K)) - .value(PY_ENUM(ARCH::EM_ST200)) - .value(PY_ENUM(ARCH::EM_IP2K)) - .value(PY_ENUM(ARCH::EM_MAX)) - .value(PY_ENUM(ARCH::EM_CR)) - .value(PY_ENUM(ARCH::EM_F2MC16)) - .value(PY_ENUM(ARCH::EM_MSP430)) - .value(PY_ENUM(ARCH::EM_BLACKFIN)) - .value(PY_ENUM(ARCH::EM_SE_C33)) - .value(PY_ENUM(ARCH::EM_SEP)) - .value(PY_ENUM(ARCH::EM_ARCA)) - .value(PY_ENUM(ARCH::EM_UNICORE)) - .value(PY_ENUM(ARCH::EM_EXCESS)) - .value(PY_ENUM(ARCH::EM_DXP)) - .value(PY_ENUM(ARCH::EM_ALTERA_NIOS2)) - .value(PY_ENUM(ARCH::EM_CRX)) - .value(PY_ENUM(ARCH::EM_XGATE)) - .value(PY_ENUM(ARCH::EM_C166)) - .value(PY_ENUM(ARCH::EM_M16C)) - .value(PY_ENUM(ARCH::EM_DSPIC30F)) - .value(PY_ENUM(ARCH::EM_CE)) - .value(PY_ENUM(ARCH::EM_M32C)) - .value(PY_ENUM(ARCH::EM_TSK3000)) - .value(PY_ENUM(ARCH::EM_RS08)) - .value(PY_ENUM(ARCH::EM_SHARC)) - .value(PY_ENUM(ARCH::EM_ECOG2)) - .value(PY_ENUM(ARCH::EM_SCORE7)) - .value(PY_ENUM(ARCH::EM_DSP24)) - .value(PY_ENUM(ARCH::EM_VIDEOCORE3)) - .value(PY_ENUM(ARCH::EM_LATTICEMICO32)) - .value(PY_ENUM(ARCH::EM_SE_C17)) - .value(PY_ENUM(ARCH::EM_TI_C6000)) - .value(PY_ENUM(ARCH::EM_TI_C2000)) - .value(PY_ENUM(ARCH::EM_TI_C5500)) - .value(PY_ENUM(ARCH::EM_MMDSP_PLUS)) - .value(PY_ENUM(ARCH::EM_CYPRESS_M8C)) - .value(PY_ENUM(ARCH::EM_R32C)) - .value(PY_ENUM(ARCH::EM_TRIMEDIA)) - .value(PY_ENUM(ARCH::EM_HEXAGON)) - .value(PY_ENUM(ARCH::EM_8051)) - .value(PY_ENUM(ARCH::EM_STXP7X)) - .value(PY_ENUM(ARCH::EM_NDS32)) - .value("ECOG1", ARCH::EM_ECOG1) - .value("ECOG1X", ARCH::EM_ECOG1X) - .value(PY_ENUM(ARCH::EM_MAXQ30)) - .value(PY_ENUM(ARCH::EM_XIMO16)) - .value(PY_ENUM(ARCH::EM_MANIK)) - .value(PY_ENUM(ARCH::EM_CRAYNV2)) - .value(PY_ENUM(ARCH::EM_RX)) - .value(PY_ENUM(ARCH::EM_METAG)) - .value(PY_ENUM(ARCH::EM_MCST_ELBRUS)) - .value(PY_ENUM(ARCH::EM_ECOG16)) - .value(PY_ENUM(ARCH::EM_CR16)) - .value(PY_ENUM(ARCH::EM_ETPU)) - .value(PY_ENUM(ARCH::EM_SLE9X)) - .value(PY_ENUM(ARCH::EM_L10M)) - .value(PY_ENUM(ARCH::EM_K10M)) - .value(PY_ENUM(ARCH::EM_AARCH64)) - .value(PY_ENUM(ARCH::EM_AVR32)) - .value(PY_ENUM(ARCH::EM_STM8)) - .value(PY_ENUM(ARCH::EM_TILE64)) - .value(PY_ENUM(ARCH::EM_TILEPRO)) - .value(PY_ENUM(ARCH::EM_CUDA)) - .value(PY_ENUM(ARCH::EM_TILEGX)) - .value(PY_ENUM(ARCH::EM_CLOUDSHIELD)) - .value(PY_ENUM(ARCH::EM_COREA_1ST)) - .value(PY_ENUM(ARCH::EM_COREA_2ND)) - .value(PY_ENUM(ARCH::EM_ARC_COMPACT2)) - .value(PY_ENUM(ARCH::EM_OPEN8)) - .value(PY_ENUM(ARCH::EM_RL78)) - .value(PY_ENUM(ARCH::EM_VIDEOCORE5)) - .value(PY_ENUM(ARCH::EM_78KOR)) - .value(PY_ENUM(ARCH::EM_56800EX)) - .value(PY_ENUM(ARCH::EM_BA1)) - .value(PY_ENUM(ARCH::EM_BA2)) - .value(PY_ENUM(ARCH::EM_XCORE)) - .value(PY_ENUM(ARCH::EM_MCHP_PIC)) - .value(PY_ENUM(ARCH::EM_INTEL205)) - .value(PY_ENUM(ARCH::EM_INTEL206)) - .value(PY_ENUM(ARCH::EM_INTEL207)) - .value(PY_ENUM(ARCH::EM_INTEL208)) - .value(PY_ENUM(ARCH::EM_INTEL209)) - .value(PY_ENUM(ARCH::EM_KM32)) - .value(PY_ENUM(ARCH::EM_KMX32)) - .value(PY_ENUM(ARCH::EM_KMX16)) - .value(PY_ENUM(ARCH::EM_KMX8)) - .value(PY_ENUM(ARCH::EM_KVARC)) - .value(PY_ENUM(ARCH::EM_CDP)) - .value(PY_ENUM(ARCH::EM_COGE)) - .value(PY_ENUM(ARCH::EM_COOL)) - .value(PY_ENUM(ARCH::EM_NORC)) - .value(PY_ENUM(ARCH::EM_CSR_KALIMBA)) - .value(PY_ENUM(ARCH::EM_AMDGPU)) - .value(PY_ENUM(ARCH::EM_RISCV)) - .value(PY_ENUM(ARCH::EM_BPF)); - - - //! Enum for the *sh_type* of ElfXX_Shdr; - LIEF::enum_(m, "SECTION_TYPES") - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_NULL)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_PROGBITS)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_SYMTAB)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_STRTAB)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_RELA)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_HASH)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_DYNAMIC)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_NOTE)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_NOBITS)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_REL)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_SHLIB)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_DYNSYM)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_INIT_ARRAY)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_FINI_ARRAY)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_PREINIT_ARRAY)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GROUP)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_SYMTAB_SHNDX)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_LOOS)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GNU_ATTRIBUTES)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GNU_HASH)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GNU_verdef)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GNU_verneed)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_GNU_versym)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ANDROID_REL)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ANDROID_RELA)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_LLVM_ADDRSIG)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_RELR)) - - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ARM_EXIDX)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ARM_PREEMPTMAP)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ARM_ATTRIBUTES)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ARM_DEBUGOVERLAY)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_ARM_OVERLAYSECTION)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_HEX_ORDERED)) - .value("X86_64_UNWIND", ELF_SECTION_TYPES::SHT_X86_64_UNWIND) - //.value(PY_ENUM(ELF_SECTION_TYPES::SHT_MIPS_REGINFO)) - //.value(PY_ENUM(ELF_SECTION_TYPES::SHT_MIPS_OPTIONS)) - //.value(PY_ENUM(ELF_SECTION_TYPES::SHT_MIPS_ABIFLAGS)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_HIPROC)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_LOUSER)) - .value(PY_ENUM(ELF_SECTION_TYPES::SHT_HIUSER)); - - - //! Enum for the *sh_flags* field of ElfXX_Shdr; - LIEF::enum_(m, "SECTION_FLAGS", py::arithmetic()) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_NONE)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_WRITE)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_ALLOC)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_EXECINSTR)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_MERGE)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_STRINGS)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_INFO_LINK)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_LINK_ORDER)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_OS_NONCONFORMING)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_GROUP)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_TLS)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_EXCLUDE)) - .value("SHF_CP_SECTION", ELF_SECTION_FLAGS::XCORE_SHF_CP_SECTION) - .value(PY_ENUM(ELF_SECTION_FLAGS::XCORE_SHF_DP_SECTION)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_MASKOS)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_MASKPROC)) - .value(PY_ENUM(ELF_SECTION_FLAGS::SHF_HEX_GPREL)); - - //! Enum for the *p_type* field of ElfXX_Phdr - LIEF::enum_(m, "SEGMENT_TYPES") - .value(PY_ENUM(SEGMENT_TYPES::PT_NULL)) - .value(PY_ENUM(SEGMENT_TYPES::PT_LOAD)) - .value(PY_ENUM(SEGMENT_TYPES::PT_DYNAMIC)) - .value(PY_ENUM(SEGMENT_TYPES::PT_INTERP)) - .value(PY_ENUM(SEGMENT_TYPES::PT_NOTE)) - .value(PY_ENUM(SEGMENT_TYPES::PT_SHLIB)) - .value(PY_ENUM(SEGMENT_TYPES::PT_PHDR)) - .value(PY_ENUM(SEGMENT_TYPES::PT_TLS)) - .value(PY_ENUM(SEGMENT_TYPES::PT_GNU_EH_FRAME)) - .value(PY_ENUM(SEGMENT_TYPES::PT_GNU_PROPERTY)) - .value(PY_ENUM(SEGMENT_TYPES::PT_GNU_STACK)) - .value(PY_ENUM(SEGMENT_TYPES::PT_GNU_RELRO)) - .value(PY_ENUM(SEGMENT_TYPES::PT_ARM_ARCHEXT)) - .value(PY_ENUM(SEGMENT_TYPES::PT_ARM_EXIDX)) - .value("UNWIND", SEGMENT_TYPES::PT_ARM_UNWIND); - - //! Enum for the *p_flags* field of ElfXX_Phdr - LIEF::enum_(m, "SEGMENT_FLAGS", py::arithmetic()) - .value(PY_ENUM(ELF_SEGMENT_FLAGS::PF_NONE)) - .value(PY_ENUM(ELF_SEGMENT_FLAGS::PF_X)) - .value(PY_ENUM(ELF_SEGMENT_FLAGS::PF_W)) - .value(PY_ENUM(ELF_SEGMENT_FLAGS::PF_R)); - - LIEF::enum_(m, "DYNAMIC_TAGS") - .value(PY_ENUM(DYNAMIC_TAGS::DT_NULL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_NEEDED)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_PLTRELSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_PLTGOT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_HASH)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_STRTAB)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_SYMTAB)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELA)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELASZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELAENT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_STRSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_SYMENT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_INIT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_FINI)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_SONAME)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RPATH)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_SYMBOLIC)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_REL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELENT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_PLTREL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_DEBUG)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_TEXTREL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_JMPREL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_BIND_NOW)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_INIT_ARRAY)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_FINI_ARRAY)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_INIT_ARRAYSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_FINI_ARRAYSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RUNPATH)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_FLAGS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_PREINIT_ARRAY)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_PREINIT_ARRAYSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_GNU_HASH)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELACOUNT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELCOUNT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_FLAGS_1)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_VERSYM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_VERDEF)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_VERDEFNUM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_VERNEED)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_VERNEEDNUM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_RLD_VERSION)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_TIME_STAMP)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_ICHECKSUM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_IVERSION)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_FLAGS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_BASE_ADDRESS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_MSYM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_CONFLICT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_LIBLIST)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_LOCAL_GOTNO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_CONFLICTNO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_LIBLISTNO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_SYMTABNO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_UNREFEXTNO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_GOTSYM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_HIPAGENO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_RLD_MAP)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_CLASS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_CLASS_NO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_INSTANCE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_INSTANCE_NO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_RELOC)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_RELOC_NO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_SYM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_SYM_NO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_CLASSSYM)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DELTA_CLASSSYM_NO)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_CXX_FLAGS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_PIXIE_INIT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_SYMBOL_LIB)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_LOCALPAGE_GOTIDX)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_LOCAL_GOTIDX)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_HIDDEN_GOTIDX)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_PROTECTED_GOTIDX)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_OPTIONS)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_INTERFACE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_DYNSTR_ALIGN)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_INTERFACE_SIZE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_RLD_TEXT_RESOLVE_ADDR)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_PERF_SUFFIX)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_COMPACT_SIZE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_GP_VALUE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_AUX_DYNAMIC)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_PLTGOT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_MIPS_RWPLT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_REL_OFFSET)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_REL_SIZE)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_REL)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_RELSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_RELA)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_ANDROID_RELASZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELR)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELRSZ)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELRENT)) - .value(PY_ENUM(DYNAMIC_TAGS::DT_RELRCOUNT)); - - - LIEF::enum_(m, "SYMBOL_TYPES") - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_NOTYPE)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_OBJECT)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_FUNC)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_SECTION)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_FILE)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_COMMON)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_TLS)) - .value(PY_ENUM(ELF_SYMBOL_TYPES::STT_GNU_IFUNC)); - - - LIEF::enum_(m, "SYMBOL_BINDINGS") - .value(PY_ENUM(SYMBOL_BINDINGS::STB_LOCAL)) - .value(PY_ENUM(SYMBOL_BINDINGS::STB_GLOBAL)) - .value(PY_ENUM(SYMBOL_BINDINGS::STB_WEAK)) - .value(PY_ENUM(SYMBOL_BINDINGS::STB_GNU_UNIQUE)); - - - LIEF::enum_(m, "RELOCATION_X86_64") - .value(PY_ENUM(RELOC_x86_64::R_X86_64_NONE)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PC32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOT32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PLT32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_COPY)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GLOB_DAT)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_JUMP_SLOT)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_RELATIVE)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPCREL)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_32S)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_16)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PC16)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_8)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PC8)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_DTPMOD64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_DTPOFF64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TPOFF64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TLSGD)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TLSLD)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_DTPOFF32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTTPOFF)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TPOFF32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PC64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTOFF64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPC32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOT64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPCREL64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPC64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPLT64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PLTOFF64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_SIZE32)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_SIZE64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPC32_TLSDESC)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TLSDESC_CALL)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_TLSDESC)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_IRELATIVE)) - - .value(PY_ENUM(RELOC_x86_64::R_X86_64_RELATIVE64)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PC32_BND)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_PLT32_BND)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_GOTPCRELX)) - .value(PY_ENUM(RELOC_x86_64::R_X86_64_REX_GOTPCRELX)); - - - LIEF::enum_(m, "RELOCATION_ARM") - .value(PY_ENUM(RELOC_ARM::R_ARM_NONE)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PC24)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ABS32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_REL32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_PC_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ABS16)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ABS12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_ABS5)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ABS8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_SBREL32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_CALL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_PC8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_BREL_ADJ)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_DESC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_SWI8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_XPC25)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_XPC22)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_DTPMOD32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_DTPOFF32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_TPOFF32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_COPY)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GLOB_DAT)) - .value(PY_ENUM(RELOC_ARM::R_ARM_JUMP_SLOT)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RELATIVE)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOTOFF32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_BASE_PREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOT_BREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PLT32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_CALL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_JUMP24)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_JUMP24)) - .value(PY_ENUM(RELOC_ARM::R_ARM_BASE_ABS)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PCREL_7_0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PCREL_15_8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PCREL_23_15)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_SBREL_11_0_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SBREL_19_12_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SBREL_27_20_CK)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TARGET1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_SBREL31)) - .value(PY_ENUM(RELOC_ARM::R_ARM_V4BX)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TARGET2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PREL31)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVW_ABS_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVT_ABS)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVW_PREL_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVT_PREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVW_ABS_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVT_ABS)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVW_PREL_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVT_PREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_JUMP19)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_JUMP6)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_ALU_PREL_11_0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_PC12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ABS32_NOI)) - .value(PY_ENUM(RELOC_ARM::R_ARM_REL32_NOI)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PC_G0_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PC_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PC_G1_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PC_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_PC_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_PC_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_PC_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_PC_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_PC_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_PC_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_PC_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_PC_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_PC_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SB_G0_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SB_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SB_G1_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SB_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ALU_SB_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_SB_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_SB_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDR_SB_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_SB_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_SB_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDRS_SB_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_SB_G0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_SB_G1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_LDC_SB_G2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVW_BREL_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVT_BREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_MOVW_BREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVW_BREL_NC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVT_BREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_MOVW_BREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_GOTDESC)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_CALL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_DESCSEQ)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_TLS_CALL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PLT32_ABS)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOT_ABS)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOT_PREL)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOT_BREL12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOTOFF12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GOTRELAX)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GNU_VTENTRY)) - .value(PY_ENUM(RELOC_ARM::R_ARM_GNU_VTINHERIT)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_JUMP11)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_JUMP8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_GD32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_LDM32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_LDO32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_IE32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_LE32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_LDO12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_LE12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_TLS_IE12GP)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_0)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_1)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_2)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_3)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_4)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_5)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_6)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_7)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_8)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_9)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_10)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_11)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_12)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_13)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_14)) - .value(PY_ENUM(RELOC_ARM::R_ARM_PRIVATE_15)) - .value(PY_ENUM(RELOC_ARM::R_ARM_ME_TOO)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_TLS_DESCSEQ16)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_TLS_DESCSEQ32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_IRELATIVE)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RXPC25)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RSBREL32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_THM_RPC22)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RREL32)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RPC24)) - .value(PY_ENUM(RELOC_ARM::R_ARM_RBASE)); - - - LIEF::enum_(m, "RELOCATION_i386") - .value(PY_ENUM(RELOC_i386::R_386_NONE)) - .value(PY_ENUM(RELOC_i386::R_386_32)) - .value(PY_ENUM(RELOC_i386::R_386_PC32)) - .value(PY_ENUM(RELOC_i386::R_386_GOT32)) - .value(PY_ENUM(RELOC_i386::R_386_PLT32)) - .value(PY_ENUM(RELOC_i386::R_386_COPY)) - .value(PY_ENUM(RELOC_i386::R_386_GLOB_DAT)) - .value(PY_ENUM(RELOC_i386::R_386_JUMP_SLOT)) - .value(PY_ENUM(RELOC_i386::R_386_RELATIVE)) - .value(PY_ENUM(RELOC_i386::R_386_GOTOFF)) - .value(PY_ENUM(RELOC_i386::R_386_GOTPC)) - .value(PY_ENUM(RELOC_i386::R_386_32PLT)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_TPOFF)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_IE)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GOTIE)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LE)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GD)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDM)) - .value(PY_ENUM(RELOC_i386::R_386_16)) - .value(PY_ENUM(RELOC_i386::R_386_PC16)) - .value(PY_ENUM(RELOC_i386::R_386_8)) - .value(PY_ENUM(RELOC_i386::R_386_PC8)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GD_32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GD_PUSH)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GD_CALL)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GD_POP)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDM_32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDM_PUSH)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDM_CALL)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDM_POP)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LDO_32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_IE_32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_LE_32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_DTPMOD32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_DTPOFF32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_TPOFF32)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_GOTDESC)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_DESC_CALL)) - .value(PY_ENUM(RELOC_i386::R_386_TLS_DESC)) - .value(PY_ENUM(RELOC_i386::R_386_IRELATIVE)) - .value(PY_ENUM(RELOC_i386::R_386_NUM)); - - - LIEF::enum_(m, "RELOCATION_AARCH64") - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_NONE)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ABS64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ABS32)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ABS16)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_PREL64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_PREL32)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_PREL16)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G1_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G2_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_UABS_G3)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_SABS_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_SABS_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_SABS_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LD_PREL_LO19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ADR_PREL_LO21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ADR_PREL_PG_HI21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ADR_PREL_PG_HI21_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ADD_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LDST8_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TSTBR14)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_CONDBR19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_JUMP26)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_CALL26)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LDST16_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LDST32_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LDST64_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G1_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G2_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_PREL_G3)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LDST128_ABS_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G1_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G2_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_MOVW_GOTOFF_G3)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_GOTREL64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_GOTREL32)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_GOT_LD_PREL19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LD64_GOTOFF_LO15)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_ADR_GOT_PAGE)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LD64_GOT_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_LD64_GOTPAGE_LO15)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSGD_ADR_PREL21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSGD_ADR_PAGE21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSGD_ADD_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSGD_MOVW_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSGD_MOVW_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADR_PREL21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADR_PAGE21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADD_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LD_PREL19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_DTPREL_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_DTPREL_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_DTPREL_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADD_DTPREL_HI12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADD_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST8_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST16_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST32_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST64_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSIE_LD_GOTTPREL_PREL19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_MOVW_TPREL_G2)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_MOVW_TPREL_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_MOVW_TPREL_G0)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_ADD_TPREL_HI12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_ADD_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST8_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST16_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST32_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST64_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_LD_PREL19)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_ADR_PREL21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_ADR_PAGE21)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_LD64_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_ADD_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_OFF_G1)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_OFF_G0_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_LDR)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_ADD)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC_CALL)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST128_TPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST128_DTPREL_LO12)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_COPY)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_GLOB_DAT)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_JUMP_SLOT)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_RELATIVE)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLS_DTPREL64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLS_DTPMOD64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLS_TPREL64)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_TLSDESC)) - .value(PY_ENUM(RELOC_AARCH64::R_AARCH64_IRELATIVE)); - - LIEF::enum_(m, "RELOCATION_PPC") - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_NONE)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR32)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR24)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR14)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR14_BRTAKEN)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_ADDR14_BRNTAKEN)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL24)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL14)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL14_BRTAKEN)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL14_BRNTAKEN)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_PLTREL24)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_JMP_SLOT)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_RELATIVE)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_LOCAL24PC)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL32)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TLS)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPMOD32)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TPREL16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TPREL32)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPREL16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_DTPREL32)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSGD16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSGD16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSGD16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSGD16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSLD16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSLD16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSLD16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TLSLD16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TPREL16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_TPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_DTPREL16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_DTPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_DTPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_GOT_DTPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TLSGD)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_TLSLD)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL16)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL16_LO)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL16_HI)) - .value(PY_ENUM(RELOC_POWERPC32::R_PPC_REL16_HA)); - - LIEF::enum_(m, "RELOCATION_PPC64") - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_NONE)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR32)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR24)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR14)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR14_BRTAKEN)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR14_BRNTAKEN)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL24)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL14)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL14_BRTAKEN)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL14_BRNTAKEN)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_JMP_SLOT)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_RELATIVE)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL32)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR64)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HIGHER)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HIGHERA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HIGHEST)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_HIGHESTA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL64)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_ADDR16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TOC16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TLS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPMOD64)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL64)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL64)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSGD16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSGD16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSGD16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSGD16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSLD16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSLD16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSLD16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TLSLD16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TPREL16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TPREL16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_TPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_DTPREL16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_DTPREL16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_DTPREL16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_GOT_DTPREL16_HA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HIGHER)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HIGHERA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HIGHEST)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TPREL16_HIGHESTA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_LO_DS)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HIGHER)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HIGHERA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HIGHEST)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_DTPREL16_HIGHESTA)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TLSGD)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_TLSLD)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL16)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL16_LO)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL16_HI)) - .value(PY_ENUM(RELOC_POWERPC64::R_PPC64_REL16_HA)); - - LIEF::enum_(m, "RELOCATION_MIPS") - .value(PY_ENUM(RELOC_MIPS::R_MIPS_NONE)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_REL32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_26)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GPREL16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_LITERAL)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PC16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_CALL16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GPREL32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_UNUSED1)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_UNUSED2)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_UNUSED3)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_SHIFT5)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_SHIFT6)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_64)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT_DISP)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT_PAGE)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT_OFST)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GOT_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_SUB)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_INSERT_A)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_INSERT_B)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_DELETE)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_HIGHER)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_HIGHEST)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_CALL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_CALL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_SCN_DISP)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_REL16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_ADD_IMMEDIATE)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PJUMP)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_RELGOT)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_JALR)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPMOD32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPREL32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPMOD64)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPREL64)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_GD)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_LDM)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_DTPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_GOTTPREL)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_TPREL32)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_TPREL64)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_TPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_TLS_TPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_GLOB_DAT)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PC21_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PC26_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PC18_S3)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PC19_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PCHI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_PCLO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_26)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_GPREL)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_GOT16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_CALL16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_GD)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_LDM)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_DTPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_DTPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_GOTTPREL)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_TPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS16_TLS_TPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_COPY)) - .value(PY_ENUM(RELOC_MIPS::R_MIPS_JUMP_SLOT)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_26_S1)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GPREL16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_LITERAL)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC7_S1)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC10_S1)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC16_S1)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_CALL16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT_DISP)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT_PAGE)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT_OFST)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GOT_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_SUB)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_HIGHER)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_HIGHEST)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_CALL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_CALL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_SCN_DISP)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_JALR)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_HI0_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_GD)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_LDM)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_DTPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_DTPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_GOTTPREL)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_TPREL_HI16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_TLS_TPREL_LO16)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_GPREL7_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC23_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC21_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC26_S2)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC18_S3)) - .value(PY_ENUM(RELOC_MIPS::R_MICROMIPS_PC19_S2)); - - - LIEF::enum_(m, "DYNSYM_COUNT_METHODS") - .value(PY_ENUM(DYNSYM_COUNT_METHODS::COUNT_AUTO)) - .value(PY_ENUM(DYNSYM_COUNT_METHODS::COUNT_SECTION)) - .value(PY_ENUM(DYNSYM_COUNT_METHODS::COUNT_HASH)) - .value(PY_ENUM(DYNSYM_COUNT_METHODS::COUNT_RELOCATIONS)); - - - LIEF::enum_(m, "NOTE_TYPES") - .value(PY_ENUM(NOTE_TYPES::NT_UNKNOWN)) - .value(PY_ENUM(NOTE_TYPES::NT_GNU_ABI_TAG)) - .value(PY_ENUM(NOTE_TYPES::NT_GNU_HWCAP)) - .value(PY_ENUM(NOTE_TYPES::NT_GNU_BUILD_ID)) - .value(PY_ENUM(NOTE_TYPES::NT_GNU_GOLD_VERSION)) - .value(PY_ENUM(NOTE_TYPES::NT_GNU_PROPERTY_TYPE_0)) - .value(PY_ENUM(NOTE_TYPES::NT_CRASHPAD)); - - - LIEF::enum_(m, "NOTE_TYPES_CORE") - .value(PY_ENUM(NOTE_TYPES_CORE::NT_CORE_UNKNOWN)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_PRSTATUS)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_PRFPREG)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_PRPSINFO)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_TASKSTRUCT)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_AUXV)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_SIGINFO)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_FILE)) - - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_VFP)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_TLS)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_HW_BREAK)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_HW_WATCH)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_SYSTEM_CALL)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_ARM_SVE)) - - .value(PY_ENUM(NOTE_TYPES_CORE::NT_386_TLS)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_386_IOPERM)) - .value(PY_ENUM(NOTE_TYPES_CORE::NT_386_XSTATE)); - - - LIEF::enum_(m, "NOTE_ABIS") - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_UNKNOWN)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_LINUX)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_GNU)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_SOLARIS2)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_FREEBSD)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_NETBSD)) - .value(PY_ENUM(NOTE_ABIS::ELF_NOTE_OS_SYLLABLE)); - - - LIEF::enum_(m, "RELOCATION_PURPOSES") - .value(PY_ENUM(RELOCATION_PURPOSES::RELOC_PURPOSE_NONE)) - .value(PY_ENUM(RELOCATION_PURPOSES::RELOC_PURPOSE_PLTGOT)) - .value(PY_ENUM(RELOCATION_PURPOSES::RELOC_PURPOSE_DYNAMIC)) - .value(PY_ENUM(RELOCATION_PURPOSES::RELOC_PURPOSE_OBJECT)); - - - LIEF::enum_(m, "ARM_EFLAGS", py::arithmetic()) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_SOFT_FLOAT)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_VFP_FLOAT)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_UNKNOWN)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_VER1)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_VER2)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_VER3)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_VER4)) - .value(PY_ENUM(ARM_EFLAGS::EF_ARM_EABI_VER5)); - - - LIEF::enum_(m, "PPC64_EFLAGS", py::arithmetic()) - .value(PY_ENUM(PPC64_EFLAGS::EF_PPC64_ABI)); - - LIEF::enum_(m, "MIPS_EFLAGS", py::arithmetic()) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_NOREORDER)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_PIC)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_CPIC)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ABI2)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_32BITMODE)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_FP64)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_NAN2008)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ABI_O32)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ABI_O64)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ABI_EABI32)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ABI_EABI64)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_3900)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_4010)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_4100)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_4650)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_4120)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_4111)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_SB1)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_OCTEON)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_XLR)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_OCTEON2)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_OCTEON3)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_5400)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_5900)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_5500)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_9000)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_LS2E)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_LS2F)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MACH_LS3A)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_MICROMIPS)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_ASE_M16)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_ASE_MDMX)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_1)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_2)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_3)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_4)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_5)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_32)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_64)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_32R2)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_64R2)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_32R6)) - .value(PY_ENUM(MIPS_EFLAGS::EF_MIPS_ARCH_64R6)); - - LIEF::enum_(m, "HEXAGON_EFLAGS", py::arithmetic()) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_MACH_V2)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_MACH_V3)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_MACH_V4)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_MACH_V5)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_ISA_MACH)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_ISA_V2)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_ISA_V3)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_ISA_V4)) - .value(PY_ENUM(HEXAGON_EFLAGS::EF_HEXAGON_ISA_V5)); - - - LIEF::enum_(m, "IDENTITY") - .value(PY_ENUM(IDENTITY::EI_MAG0)) - .value(PY_ENUM(IDENTITY::EI_MAG1)) - .value(PY_ENUM(IDENTITY::EI_MAG2)) - .value(PY_ENUM(IDENTITY::EI_MAG3)) - .value(PY_ENUM(IDENTITY::EI_CLASS)) - .value(PY_ENUM(IDENTITY::EI_DATA)) - .value(PY_ENUM(IDENTITY::EI_VERSION)) - .value(PY_ENUM(IDENTITY::EI_OSABI)) - .value(PY_ENUM(IDENTITY::EI_ABIVERSION)) - .value(PY_ENUM(IDENTITY::EI_PAD)) - .value(PY_ENUM(IDENTITY::EI_NIDENT)); - - - LIEF::enum_(m, "SYMBOL_SECTION_INDEX") - .value(PY_ENUM(SYMBOL_SECTION_INDEX::SHN_UNDEF)) - .value(PY_ENUM(SYMBOL_SECTION_INDEX::SHN_ABS)) - .value(PY_ENUM(SYMBOL_SECTION_INDEX::SHN_COMMON)) - .value(PY_ENUM(SYMBOL_SECTION_INDEX::SHN_HIRESERVE)); - - - LIEF::enum_(m, "DYNAMIC_FLAGS", py::arithmetic()) - .value(PY_ENUM(DYNAMIC_FLAGS::DF_ORIGIN)) - .value(PY_ENUM(DYNAMIC_FLAGS::DF_SYMBOLIC)) - .value(PY_ENUM(DYNAMIC_FLAGS::DF_TEXTREL)) - .value(PY_ENUM(DYNAMIC_FLAGS::DF_BIND_NOW)) - .value(PY_ENUM(DYNAMIC_FLAGS::DF_STATIC_TLS)); - - LIEF::enum_(m, "DYNAMIC_FLAGS_1", py::arithmetic()) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NOW)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_GLOBAL)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_GROUP)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NODELETE)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_LOADFLTR)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_INITFIRST)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NOOPEN)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_ORIGIN)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_DIRECT)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_TRANS)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_INTERPOSE)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NODEFLIB)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NODUMP)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_CONFALT)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_ENDFILTEE)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_DISPRELDNE)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_DISPRELPND)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NODIRECT)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_IGNMULDEF)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NOKSYMS)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NOHDR)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_EDITED)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_NORELOC)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_SYMINTPOSE)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_GLOBAUDIT)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_SINGLETON)) - .value(PY_ENUM(DYNAMIC_FLAGS_1::DF_1_PIE)); - - - LIEF::enum_(m, "SYMBOL_VISIBILITY") - .value(PY_ENUM(ELF_SYMBOL_VISIBILITY::STV_DEFAULT)) - .value(PY_ENUM(ELF_SYMBOL_VISIBILITY::STV_HIDDEN)) - .value(PY_ENUM(ELF_SYMBOL_VISIBILITY::STV_INTERNAL)) - .value(PY_ENUM(ELF_SYMBOL_VISIBILITY::STV_PROTECTED)); - -} - -} -} diff --git a/vendor/lief/api/python/ELF/pySizes.cpp b/vendor/lief/api/python/ELF/pySizes.cpp deleted file mode 100644 index b156867..0000000 --- a/vendor/lief/api/python/ELF/pySizes.cpp +++ /dev/null @@ -1,54 +0,0 @@ -#include "pyELF.hpp" -#include "ELF/Structures.hpp" - -namespace LIEF { -namespace ELF { -void init_ELF32_sizes(py::module& m) { - enum SIZES : size_t {}; - py::enum_(m, "SIZES") - .value("ADDR", static_cast(sizeof(details::Elf32_Addr))) - .value("OFF", static_cast(sizeof(details::Elf32_Off))) - .value("HALF", static_cast(sizeof(details::Elf32_Half))) - .value("WORD", static_cast(sizeof(details::Elf32_Word))) - .value("SWORD", static_cast(sizeof(details::Elf32_Sword))) - .value("INT", static_cast(sizeof(uint32_t))) - .value("EHDR", static_cast(sizeof(details::Elf32_Ehdr))) - .value("SHDR", static_cast(sizeof(details::Elf32_Shdr))) - .value("PHDR", static_cast(sizeof(details::Elf32_Phdr))) - .value("SYM", static_cast(sizeof(details::Elf32_Sym))) - .value("REL", static_cast(sizeof(details::Elf32_Rel))) - .value("RELA", static_cast(sizeof(details::Elf32_Rela))) - .value("DYN", static_cast(sizeof(details::Elf32_Dyn))) - .value("VERNEED", static_cast(sizeof(details::Elf32_Verneed))) - .value("VERNAUX", static_cast(sizeof(details::Elf32_Vernaux))) - .value("AUXV", static_cast(sizeof(details::Elf32_Auxv))) - .value("VERDEF", static_cast(sizeof(details::Elf32_Verdef))) - .value("VERDAUX", static_cast(sizeof(details::Elf32_Verdaux))); -} - - -void init_ELF64_sizes(py::module& m) { - enum SIZES : size_t {}; - py::enum_(m, "SIZES") - .value("ADDR", static_cast(sizeof(details::Elf64_Addr))) - .value("OFF", static_cast(sizeof(details::Elf64_Off))) - .value("HALF", static_cast(sizeof(details::Elf64_Half))) - .value("WORD", static_cast(sizeof(details::Elf64_Word))) - .value("SWORD", static_cast(sizeof(details::Elf64_Sword))) - .value("INT", static_cast(sizeof(uint64_t))) - .value("EHDR", static_cast(sizeof(details::Elf64_Ehdr))) - .value("SHDR", static_cast(sizeof(details::Elf64_Shdr))) - .value("PHDR", static_cast(sizeof(details::Elf64_Phdr))) - .value("SYM", static_cast(sizeof(details::Elf64_Sym))) - .value("REL", static_cast(sizeof(details::Elf64_Rel))) - .value("RELA", static_cast(sizeof(details::Elf64_Rela))) - .value("DYN", static_cast(sizeof(details::Elf64_Dyn))) - .value("VERNEED", static_cast(sizeof(details::Elf64_Verneed))) - .value("VERNAUX", static_cast(sizeof(details::Elf64_Vernaux))) - .value("AUXV", static_cast(sizeof(details::Elf64_Auxv))) - .value("VERDEF", static_cast(sizeof(details::Elf64_Verdef))) - .value("VERDAUX", static_cast(sizeof(details::Elf64_Verdaux))); -} - -} -} diff --git a/vendor/lief/api/python/MachO/CMakeLists.txt b/vendor/lief/api/python/MachO/CMakeLists.txt deleted file mode 100644 index 61a8eba..0000000 --- a/vendor/lief/api/python/MachO/CMakeLists.txt +++ /dev/null @@ -1,61 +0,0 @@ -set(LIEF_PYTHON_MACHO_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyMachO.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDylibCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBinary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFatBinary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyLoadCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySegmentCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySection.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbolCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyUUID.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySourceVersion.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyVersionMin.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyMainCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDylinker.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDyldInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDyldChainedFixups.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyChainedBindingInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDyldBindingInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDyldExportsTrie.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocationFixup.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFunctionStarts.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocation.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocationObject.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocationDyld.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBindingInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyExportInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyThreadCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRPathCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParserConfig.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDynamicSymbolCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeSignature.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySegmentSplitInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDataInCode.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDataCodeEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySubFramework.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDyldEnvironment.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyEncryptionInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBuildVersion.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFilesetCommand.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeSignatureDir.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyTwoLevelHints.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyLinkerOptHint.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBuilder.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" -) - -set(LIEF_PYTHON_MACHO_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyMachO.hpp") - -source_group("Source Files\\MachO" FILES ${LIEF_PYTHON_MACHO_SRC}) -source_group("Header Files\\MachO" FILES ${LIEF_PYTHON_MACHO_HDR}) - -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_MACHO_SRC}" "${LIEF_PYTHON_MACHO_HDR}") - - - diff --git a/vendor/lief/api/python/MachO/objects/pyBinary.cpp b/vendor/lief/api/python/MachO/objects/pyBinary.cpp deleted file mode 100644 index f05b7f5..0000000 --- a/vendor/lief/api/python/MachO/objects/pyBinary.cpp +++ /dev/null @@ -1,640 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "LIEF/Abstract/Binary.hpp" -#include "LIEF/MachO/Binary.hpp" -#include "LIEF/MachO/Symbol.hpp" -#include "LIEF/MachO/Section.hpp" - -#include "LIEF/MachO/hash.hpp" - -#include "pyErr.hpp" -#include "pyMachO.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace MachO { - -template -using no_const_getter = T (Binary::*)(void); - -template -using no_const_func = T (Binary::*)(P); - - -template<> -void create(py::module& m) { - - - py::class_ bin(m, "Binary", - R"delim( - Class which represents a MachO binary - )delim"); - - init_ref_iterator(bin, "it_commands"); - - init_ref_iterator(bin, "it_symbols"); - init_ref_iterator(bin, "it_filter_symbols"); - init_ref_iterator(bin, "it_sections"); - init_ref_iterator(bin, "it_segments"); - init_ref_iterator(bin, "it_libraries"); - init_ref_iterator(bin, "it_relocations"); - - // --> Already registered with FatMachO (same container) - //init_ref_iterator(bin, "it_fileset_binaries"); - - bin - .def_property_readonly("header", - static_cast>(&Binary::header), - "Return binary's " RST_CLASS_REF(lief.MachO.Header) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("sections", - static_cast>(&Binary::sections), - "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Section) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("relocations", - static_cast>(&Binary::relocations), - "Return an iterator over binary's " RST_CLASS_REF(lief.MachO.Relocation) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("segments", - static_cast>(&Binary::segments), - "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.SegmentCommand) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("libraries", - static_cast>(&Binary::libraries), - "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.DylibCommand) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("symbols", - static_cast>(&Binary::symbols), - "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Symbol) "", - py::return_value_policy::reference_internal) - - .def("has_symbol", - &Binary::has_symbol, - "Check if a " RST_CLASS_REF(lief.MachO.Symbol) " with the given name exists", - "name"_a) - - .def("get_symbol", - static_cast>(&Binary::get_symbol), - "Return the " RST_CLASS_REF(lief.MachO.Symbol) " from the given name", - "name"_a, - py::return_value_policy::reference) - - .def_property_readonly("imported_symbols", - static_cast>(&Binary::imported_symbols), - "Return the binary's " RST_CLASS_REF(lief.MachO.Symbol) " which are imported", - py::return_value_policy::reference_internal) - - .def_property_readonly("exported_symbols", - static_cast>(&Binary::exported_symbols), - "Return the binary's " RST_CLASS_REF(lief.MachO.Symbol) " which are exported", - py::return_value_policy::reference_internal) - - .def_property_readonly("commands", - static_cast>(&Binary::commands), - "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Command) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("filesets", - static_cast>(&Binary::filesets), - "Return binary's " RST_CLASS_REF(lief.MachO.Filesets) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("has_filesets", - &Binary::has_filesets, - "Return ``True`` if the binary has filesets") - - .def_property_readonly("imagebase", - &Binary::imagebase, - R"delim( - Return the binary's ``imagebase`` which is the base address - where segments are mapped (without the ASLR). ``0`` if not relevant. - )delim") - - .def_property_readonly("virtual_size", - &Binary::virtual_size, - "Binary's memory size when mapped") - - .def_property_readonly("fat_offset", - &Binary::fat_offset, - "Return binary's *fat offset*. ``0`` if not relevant.", - py::return_value_policy::copy) - - .def("section_from_offset", - static_cast(&Binary::section_from_offset), - "Return the " RST_CLASS_REF(lief.MachO.Section) " which encompasses the offset", - py::return_value_policy::reference) - - .def("section_from_virtual_address", - static_cast(&Binary::section_from_virtual_address), - "Return the " RST_CLASS_REF(lief.MachO.Section) " which encompasses the virtual address", - py::return_value_policy::reference) - - .def("segment_from_offset", - static_cast(&Binary::segment_from_offset), - "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " which encompasses the offset", - py::return_value_policy::reference) - - .def("segment_from_virtual_address", - static_cast(&Binary::segment_from_virtual_address), - "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " which encompasses the virtual address", - py::return_value_policy::reference) - - .def_property_readonly("has_entrypoint", - &Binary::has_entrypoint, - R"delim( - ``True`` if the binary has an entrypoint. - - Basically for libraries it will return ``false`` - )delim") - - - .def_property_readonly("has_uuid", - &Binary::has_uuid, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.UUIDCommand) " command.") - - .def_property_readonly("uuid", - static_cast>(&Binary::uuid), - "Return the binary's " RST_CLASS_REF(lief.MachO.UUIDCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_main_command", - &Binary::has_main_command, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.MainCommand) " command.") - - .def_property_readonly("main_command", - static_cast>(&Binary::main_command), - "Return the binary's " RST_CLASS_REF(lief.MachO.MainCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dylinker", - &Binary::has_dylinker, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DylinkerCommand) " command.") - - .def_property_readonly("dylinker", - static_cast>(&Binary::dylinker), - "Return the binary's " RST_CLASS_REF(lief.MachO.DylinkerCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dyld_info", - &Binary::has_dyld_info, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldInfo) " command.") - - .def_property_readonly("dyld_info", - static_cast>(&Binary::dyld_info), - "Return the binary's " RST_CLASS_REF(lief.MachO.DyldInfo) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_function_starts", - &Binary::has_function_starts, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.FunctionStarts) " command.") - - .def_property_readonly("function_starts", - static_cast>(&Binary::function_starts), - "Return the binary's " RST_CLASS_REF(lief.MachO.FunctionStarts) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_source_version", - &Binary::has_source_version, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SourceVersion) " command.") - - .def_property_readonly("source_version", - static_cast>(&Binary::source_version), - "Return the binary's " RST_CLASS_REF(lief.MachO.SourceVersion) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_version_min", - &Binary::has_version_min, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.VersionMin) " command.") - - .def_property_readonly("version_min", - static_cast>(&Binary::version_min), - "Return the binary's " RST_CLASS_REF(lief.MachO.VersionMin) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_thread_command", - &Binary::has_thread_command, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.ThreadCommand) " command.") - - .def_property_readonly("thread_command", - static_cast>(&Binary::thread_command), - "Return the binary's " RST_CLASS_REF(lief.MachO.ThreadCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_rpath", - &Binary::has_rpath, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.RPathCommand) " command.") - - .def_property_readonly("rpath", - static_cast>(&Binary::rpath), - "Return the binary's " RST_CLASS_REF(lief.MachO.RPathCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_symbol_command", - &Binary::has_symbol_command, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SymbolCommand) " command.") - - .def_property_readonly("symbol_command", - static_cast>(&Binary::symbol_command), - "Return the binary's " RST_CLASS_REF(lief.MachO.SymbolCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dynamic_symbol_command", - &Binary::has_dynamic_symbol_command, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DynamicSymbolCommand) " command.") - - .def_property_readonly("dynamic_symbol_command", - static_cast>(&Binary::dynamic_symbol_command), - "Return the binary's " RST_CLASS_REF(lief.MachO.DynamicSymbolCommand) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_code_signature", - &Binary::has_code_signature, - "``True`` if the binary is signed (i.e. has a " RST_CLASS_REF(lief.MachO.CodeSignature) " command)") - - .def_property_readonly("code_signature", - static_cast>(&Binary::code_signature), - "Return the binary's " RST_CLASS_REF(lief.MachO.CodeSignature) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_code_signature_dir", - &Binary::has_code_signature_dir, - "``True`` if the binary is signed (i.e. has a " RST_CLASS_REF(lief.MachO.CodeSignatureDir) " command) " - "with the command LC_DYLIB_CODE_SIGN_DRS") - - .def_property_readonly("code_signature_dir", - static_cast>(&Binary::code_signature_dir), - "Return the binary's " RST_CLASS_REF(lief.MachO.CodeSignatureDir) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_data_in_code", - &Binary::has_data_in_code, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DataInCode) " command") - - .def_property_readonly("data_in_code", - static_cast>(&Binary::data_in_code), - "Return the binary's " RST_CLASS_REF(lief.MachO.DataInCode) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_segment_split_info", - &Binary::has_segment_split_info, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SegmentSplitInfo) " command") - - .def_property_readonly("segment_split_info", - static_cast>(&Binary::segment_split_info), - "Return the binary's " RST_CLASS_REF(lief.MachO.SegmentSplitInfo) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_sub_framework", - &Binary::has_sub_framework, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SubFramework) " command") - - .def_property_readonly("sub_framework", - static_cast>(&Binary::sub_framework), - "Return the binary's " RST_CLASS_REF(lief.MachO.SubFramework) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dyld_environment", - &Binary::has_dyld_environment, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldEnvironment) " command") - - .def_property_readonly("dyld_environment", - static_cast>(&Binary::dyld_environment), - "Return the binary's " RST_CLASS_REF(lief.MachO.DyldEnvironment) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_encryption_info", - &Binary::has_encryption_info, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.EncryptionInfo) " command") - - .def_property_readonly("encryption_info", - static_cast>(&Binary::encryption_info), - "Return the binary's " RST_CLASS_REF(lief.MachO.EncryptionInfo) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_build_version", - &Binary::has_build_version, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.BuildVersion) " command") - - .def_property_readonly("build_version", - static_cast>(&Binary::build_version), - "Return the binary's " RST_CLASS_REF(lief.MachO.BuildVersion) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dyld_chained_fixups", - &Binary::has_dyld_chained_fixups, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldChainedFixups) " command") - - .def_property_readonly("dyld_chained_fixups", - static_cast>(&Binary::dyld_chained_fixups), - "Return the binary's " RST_CLASS_REF(lief.MachO.DyldChainedFixups) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_dyld_exports_trie", - &Binary::has_dyld_exports_trie, - "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldExportsTrie) " command") - - .def_property_readonly("dyld_exports_trie", - static_cast>(&Binary::dyld_exports_trie), - "Return the binary's " RST_CLASS_REF(lief.MachO.DyldExportsTrie) " if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_two_level_hints", - &Binary::has_two_level_hints, - "``True`` if the binary embeds the Two Level Hint command (" RST_CLASS_REF(lief.MachO.TwoLevelHints) ")") - - .def_property_readonly("two_level_hints", - static_cast>(&Binary::two_level_hints), - "Return the binary's " RST_CLASS_REF(lief.MachO.TwoLevelHints) " if any, or None", - py::return_value_policy::reference) - - - .def_property_readonly("has_linker_opt_hint", - &Binary::has_linker_opt_hint, - "``True`` if the binary embeds the Linker optimization hint command (" RST_CLASS_REF(lief.MachO.LinkerOptHint) ")") - - .def_property_readonly("linker_opt_hint", - static_cast>(&Binary::linker_opt_hint), - "Return the binary's " RST_CLASS_REF(lief.MachO.LinkerOptHint) " if any, or None", - py::return_value_policy::reference) - - .def("virtual_address_to_offset", - [] (const Binary& self, uint64_t va) { - return error_or(&Binary::virtual_address_to_offset, self, va); - }, - "Convert the virtual address to an offset in the binary", - "virtual_address"_a) - - .def("has_section", - &Binary::has_section, - "Check if a section with the given name exists", - "name"_a) - - .def("get_section", - static_cast(&Binary::get_section), - "Return the section from the given name or None if the section does not exist", - "name"_a, - py::return_value_policy::reference) - - .def("has_segment", - &Binary::has_segment, - "Check if a " RST_CLASS_REF(lief.MachO.SegmentCommand) " with the given name exists", - "name"_a) - - .def("get_segment", - static_cast(&Binary::get_segment), - "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " from the given name", - "name"_a, - py::return_value_policy::reference) - - .def_property_readonly("va_ranges", - &Binary::va_ranges, - "Return the range of virtual addresses as a tuple ``(va_start, va_end)``") - - .def_property_readonly("off_ranges", - &Binary::off_ranges, - "Return the range of offsets as a tuple ``(off_start, off_end)``") - - .def("is_valid_addr", - &Binary::is_valid_addr, - R"delim( - Check if the given address is encompassed between the range of virtual addresses. - - See: :attr:`~lief.MachO.Binary.va_ranges` - )delim", - "address"_a) - - .def("write", - static_cast(&Binary::write), - "Rebuild the binary and write and write its content if the file given in parameter", - "output"_a, - py::return_value_policy::reference_internal) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.MachO.DylibCommand) "", - "dylib_command"_a, - py::return_value_policy::reference) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.MachO.SegmentCommand) "", - "segment"_a, - py::return_value_policy::reference) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.MachO.LoadCommand) "", - "load_command"_a, - py::return_value_policy::reference) - - .def("add", - static_cast(&Binary::add), - "Add a new " RST_CLASS_REF(lief.MachO.LoadCommand) " at ``index``", - "load_command"_a, "index"_a, - py::return_value_policy::reference) - - - .def("remove", - static_cast(&Binary::remove), - "Remove a " RST_CLASS_REF(lief.MachO.LoadCommand) "", - "load_command"_a) - - .def("remove", - static_cast(&Binary::remove), - "Remove **all** the " RST_CLASS_REF(lief.MachO.LoadCommand) " having the given " - "" RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES) "", - "type"_a) - - .def("remove", - static_cast(&Binary::remove), - "Remove the given " RST_CLASS_REF(lief.MachO.Symbol)"", - "symbol"_a) - - .def("remove_command", - static_cast(&Binary::remove_command), - "Remove the " RST_CLASS_REF(lief.MachO.LoadCommand) " at the given ``index``", - "index"_a) - - .def("remove_section", - static_cast(&Binary::remove_section), - "Remove the section with the given name", - "name"_a, "clear"_a = false) - - .def("remove_section", - py::overload_cast(&Binary::remove_section), - R"delim( - Remove the section from the segment with the name - given in the first parameter and with the section's name provided in the - second parameter.)delim", - "segname"_a, "secname"_a, "clear"_a = false) - - .def("remove_signature", - static_cast(&Binary::remove_signature), - "Remove the " RST_CLASS_REF(lief.MachO.CodeSignature) " (if any)") - - .def("remove_symbol", - static_cast(&Binary::remove_symbol), - "Remove all symbol(s) with the given name", - "name"_a) - - .def("can_remove", - static_cast(&Binary::can_remove), - "Check if the given symbol can be safely removed.", - "symbol"_a) - - .def("can_remove_symbol", - static_cast(&Binary::can_remove_symbol), - "Check if the given symbol name can be safely removed.", - "symbol_name"_a) - - .def("unexport", - static_cast(&Binary::unexport), - "Remove the symbol from the export table", - "name"_a) - - .def("unexport", - static_cast(&Binary::unexport), - "Remove the symbol from the export table", - "symbol"_a) - - .def("extend", - static_cast(&Binary::extend), - "Extend a " RST_CLASS_REF(lief.MachO.LoadCommand) " by ``size``", - "load_command"_a, "size"_a) - - .def("extend_segment", - static_cast(&Binary::extend_segment), - "Extend the **content** of the given " RST_CLASS_REF(lief.MachO.SegmentCommand) " by ``size``", - "segment_command"_a, "size"_a) - - .def("add_section", - static_cast(&Binary::add_section), - "Add a new " RST_CLASS_REF(lief.MachO.Section) " in the given " RST_CLASS_REF(lief.MachO.SegmentCommand) "", - "segment"_a, "section"_a, - py::return_value_policy::reference) - - .def("add_section", - static_cast(&Binary::add_section), - "Add a new " RST_CLASS_REF(lief.MachO.Section) " within the ``__TEXT`` segment", - "section"_a, - py::return_value_policy::reference) - - - .def("add_section", - static_cast(&Binary::add_section), - "Add a new " RST_CLASS_REF(lief.MachO.Section) " in the given " RST_CLASS_REF(lief.MachO.SegmentCommand) "", - "section"_a, "section"_a, - py::return_value_policy::reference) - - .def("add_library", - static_cast(&Binary::add_library), - "Add a new library dependency", - "library_name"_a, - py::return_value_policy::reference) - - .def("get", - static_cast(&Binary::get), - "Return the **first** " RST_CLASS_REF(lief.MachO.LoadCommand) " having the given " - "" RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES) " or None if it is not present.", - "type"_a, - py::return_value_policy::reference) - - .def("has", - static_cast(&Binary::has), - "Check if the current binary has a " RST_CLASS_REF(lief.MachO.LoadCommand) " with the given " - "" RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES) "", - "type"_a) - - .def_property_readonly("unwind_functions", - &Binary::unwind_functions, - "Return list of " RST_CLASS_REF(lief.Function) " found in the ``__unwind_info`` section") - - .def_property_readonly("functions", - &Binary::functions, - "Return list of **all** " RST_CLASS_REF(lief.Function) " found") - - .def("get_section", - py::overload_cast(&Binary::get_section), - R"delim( - Return the section from the segment with the name - given in the first parameter and with the section's name provided in the - second parameter. If the section cannot be found, it returns a nullptr - )delim", - "segname"_a, "secname"_a, - py::return_value_policy::reference_internal) - - .def("shift", - [] (Binary& self, size_t width) { - return error_or(&Binary::shift, self, width); - }, - R"delim( - Shift the content located right after the Load commands table. - This operation can be used to add a new command - )delim", - "value"_a) - - .def("shift_linkedit", - [] (Binary& self, size_t width) { - return error_or(&Binary::shift_linkedit, self, width); - }, - "Shift the position on the __LINKEDIT data by `width`", - "value"_a) - - .def("add_exported_function", - &Binary::add_exported_function, - "Add a new export in the binary", - "address"_a, "name"_a, - py::return_value_policy::reference) - - .def("add_local_symbol", - &Binary::add_local_symbol, - "Add a new a new symbol in the LC_SYMTAB", - "address"_a, "name"_a, - py::return_value_policy::reference) - - .def_property_readonly("page_size", - &Binary::page_size, - "Return the binary's page size") - - .def("__getitem__", - static_cast(&Binary::operator[]), - "", - py::return_value_policy::reference) - - .def("__contains__", - static_cast(&Binary::has)) - - - .def("__str__", - [] (const Binary& binary) - { - std::ostringstream stream; - stream << binary; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/MachO/objects/pyBindingInfo.cpp b/vendor/lief/api/python/MachO/objects/pyBindingInfo.cpp deleted file mode 100644 index 75d341e..0000000 --- a/vendor/lief/api/python/MachO/objects/pyBindingInfo.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/BindingInfo.hpp" -#include "LIEF/MachO/SegmentCommand.hpp" -#include "LIEF/MachO/Symbol.hpp" -#include "LIEF/MachO/DylibCommand.hpp" - -#include "pyMachO.hpp" - - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (BindingInfo::*)(void) const; - -template -using setter_t = void (BindingInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "BindingInfo", - R"delim( - Class that provides an interface over an entry in DyldInfo structure - - This class does not represent a structure that exists in the Mach-O format - specifications but it provides a *view* of a binding operation that is performed - by the Dyld binding bytecode (`LC_DYLD_INFO`) or the Dyld chained fixups (`DYLD_CHAINED_FIXUPS`) - - See: :class:`~lief.MachO.ChainedBindingInfo`, :class:`~lief.MachO.DyldBindingInfo` - )delim") - - - .def_property("address", - static_cast>(&BindingInfo::address), - static_cast>(&BindingInfo::address), - "Binding's address") - - - .def_property("library_ordinal", - static_cast>(&BindingInfo::library_ordinal), - static_cast>(&BindingInfo::library_ordinal)) - - .def_property("addend", - static_cast>(&BindingInfo::addend), - static_cast>(&BindingInfo::addend), - "Value added to the segment's virtual address when binding") - - .def_property("weak_import", - static_cast>(&BindingInfo::is_weak_import), - static_cast>(&BindingInfo::set_weak_import)) - - - .def_property_readonly("has_library", - &BindingInfo::has_library, - "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.DylibCommand) " associated with") - - .def_property_readonly("library", - static_cast(&BindingInfo::library), - "" RST_CLASS_REF(lief.MachO.DylibCommand) " associated with the binding if any, or None", - py::return_value_policy::reference) - - - .def_property_readonly("has_segment", - &BindingInfo::has_segment, - "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with") - - .def_property_readonly("segment", - static_cast(&BindingInfo::segment), - "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the binding if any, or None", - py::return_value_policy::reference) - - - .def_property_readonly("has_symbol", - &BindingInfo::has_symbol, - "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with") - - .def_property_readonly("symbol", - static_cast(&BindingInfo::symbol), - "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the binding if any, or None", - py::return_value_policy::reference) - - .def("__eq__", &BindingInfo::operator==) - .def("__ne__", &BindingInfo::operator!=) - .def("__hash__", - [] (const BindingInfo& binding_info) { - return Hash::hash(binding_info); - }) - - - .def("__str__", - [] (const BindingInfo& binding_info) - { - std::ostringstream stream; - stream << binding_info; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyBuildVersion.cpp b/vendor/lief/api/python/MachO/objects/pyBuildVersion.cpp deleted file mode 100644 index a398674..0000000 --- a/vendor/lief/api/python/MachO/objects/pyBuildVersion.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/BuildVersion.hpp" -#include "LIEF/MachO/EnumToString.hpp" - -#include "enums_wrapper.hpp" - -#include "pyMachO.hpp" - -#define PY_ENUM(x) LIEF::MachO::to_string(x), x - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (BuildVersion::*)(void) const; - -template -using setter_t = void (BuildVersion::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ cls(m, "BuildVersion"); - py::class_ tool_version_cls(m, "BuildToolVersion", - R"delim( - Class that represents a tool's version that was involved in the build of the binary - )delim"); - - - // Build Tool Version - // ================== - tool_version_cls - .def_property_readonly("tool", - &BuildToolVersion::tool, - "" RST_CLASS_REF(.BuildVersion.TOOLS) " type") - - .def_property_readonly("version", - &BuildToolVersion::version, - "Version of the tool") - - .def("__eq__", &BuildToolVersion::operator==) - .def("__ne__", &BuildToolVersion::operator!=) - .def("__hash__", - [] (const BuildToolVersion& version) { - return Hash::hash(version); - }) - - .def("__str__", - [] (const BuildToolVersion& version) - { - std::ostringstream stream; - stream << version; - return stream.str(); - }); - - - LIEF::enum_(tool_version_cls, "TOOLS") - .value(PY_ENUM(BuildToolVersion::TOOLS::UNKNOWN)) - .value(PY_ENUM(BuildToolVersion::TOOLS::CLANG)) - .value(PY_ENUM(BuildToolVersion::TOOLS::SWIFT)) - .value(PY_ENUM(BuildToolVersion::TOOLS::LD)); - - cls - - .def_property("platform", - static_cast>(&BuildVersion::platform), - static_cast>(&BuildVersion::platform), - "Target " RST_CLASS_REF(.BuildVersion.PLATFORMS) "") - - .def_property("minos", - static_cast>(&BuildVersion::minos), - static_cast>(&BuildVersion::minos), - "Minimal OS version on which this binary was built to run") - - .def_property("sdk", - static_cast>(&BuildVersion::sdk), - static_cast>(&BuildVersion::sdk), - "SDK Version") - - .def_property_readonly("tools", - static_cast>(&BuildVersion::tools), - "List of " RST_CLASS_REF(BuildToolVersion) " used when while this binary") - - .def("__eq__", &BuildVersion::operator==) - .def("__ne__", &BuildVersion::operator!=) - .def("__hash__", - [] (const BuildVersion& version) { - return Hash::hash(version); - }) - - .def("__str__", - [] (const BuildVersion& version) - { - std::ostringstream stream; - stream << version; - return stream.str(); - }); - - - LIEF::enum_(cls, "PLATFORMS") - .value(PY_ENUM(BuildVersion::PLATFORMS::UNKNOWN)) - .value(PY_ENUM(BuildVersion::PLATFORMS::MACOS)) - .value(PY_ENUM(BuildVersion::PLATFORMS::IOS)) - .value(PY_ENUM(BuildVersion::PLATFORMS::TVOS)) - .value(PY_ENUM(BuildVersion::PLATFORMS::WATCHOS)); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyBuilder.cpp b/vendor/lief/api/python/MachO/objects/pyBuilder.cpp deleted file mode 100644 index 77ecf32..0000000 --- a/vendor/lief/api/python/MachO/objects/pyBuilder.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "pyMachO.hpp" -#include "pyErr.hpp" - -#include "LIEF/MachO/Binary.hpp" -#include "LIEF/MachO/FatBinary.hpp" -#include "LIEF/MachO/Builder.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - py::class_ builder(m, "Builder", - R"delim( - Class used to reconstruct a Mach-O binary from its object representation - )delim"); - - py::class_(builder, "config_t", - "Interface to tweak the " RST_CLASS_REF(lief.MachO.Builder) "") - .def(py::init<>()) - .def_readwrite("linkedit", &Builder::config_t::linkedit); - - builder - .def_static("write", - [] (Binary& bin, const std::string& out) { - auto target = py::overload_cast(&Builder::write); - return error_or(target, bin, out); - }, - R"delim( - )delim", - "binary"_a, "output"_a) - .def_static("write", - [] (Binary& bin, const std::string& out, Builder::config_t config) { - auto target = py::overload_cast(&Builder::write); - return error_or(target, bin, out, config); - }, - R"delim( - )delim", - "binary"_a, "output"_a, "config"_a) - .def_static("write", - [] (FatBinary& fat, const std::string& out) { - auto target = py::overload_cast(&Builder::write); - return error_or(target, fat, out); - }, - R"delim( - )delim", - "fat_binary"_a, "output"_a) - .def_static("write", - [] (FatBinary& fat, const std::string& out, Builder::config_t config) { - auto target = py::overload_cast(&Builder::write); - return error_or(target, fat, out, config); - }, - R"delim( - )delim", - "fat_binary"_a, "output"_a, "config"_a); -} -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyChainedBindingInfo.cpp b/vendor/lief/api/python/MachO/objects/pyChainedBindingInfo.cpp deleted file mode 100644 index 3f78bc0..0000000 --- a/vendor/lief/api/python/MachO/objects/pyChainedBindingInfo.cpp +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/ChainedBindingInfo.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_(m, "ChainedBindingInfo", - R"delim( - This class represents a symbol binding operation associated with - the LC_DYLD_CHAINED_FIXUPS command. - - This class does not represent a structure that exists in the Mach-O format - specifications but it provides a *view* on an entry. - - See also: :class:`~lief.MachO.BindingInfo` - )delim") - - .def_property_readonly("format", - &ChainedBindingInfo::format, - R"delim( - :class:`~lief.MachO.DYLD_CHAINED_FORMAT` of the import - )delim") - - .def_property_readonly("ptr_format", - &ChainedBindingInfo::ptr_format, - R"delim( - :class:`~lief.MachO.DYLD_CHAINED_PTR_FORMAT` of the import - )delim") - - .def_property("offset", - py::overload_cast<>(&ChainedBindingInfo::offset, py::const_), - py::overload_cast(&ChainedBindingInfo::offset), - R"delim( - Offset of the entry in the chained fixups - )delim") - - .def_property_readonly("sign_extended_addend", &ChainedBindingInfo::sign_extended_addend) - - .def("__eq__", &ChainedBindingInfo::operator==) - .def("__ne__", &ChainedBindingInfo::operator!=) - .def("__hash__", - [] (const ChainedBindingInfo& info) { - return Hash::hash(info); - }) - - .def("__str__", - [] (const ChainedBindingInfo& info) { - std::ostringstream stream; - std::string str = stream.str(); - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyCodeSignature.cpp b/vendor/lief/api/python/MachO/objects/pyCodeSignature.cpp deleted file mode 100644 index 7c83418..0000000 --- a/vendor/lief/api/python/MachO/objects/pyCodeSignature.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/CodeSignature.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (CodeSignature::*)(void) const; - -template -using setter_t = void (CodeSignature::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "CodeSignature") - - .def_property("data_offset", - static_cast>(&CodeSignature::data_offset), - static_cast>(&CodeSignature::data_offset), - "Offset in the binary where the signature starts") - - .def_property("data_size", - static_cast>(&CodeSignature::data_size), - static_cast>(&CodeSignature::data_size), - "Size of the raw signature") - - .def_property_readonly("content", - [] (const CodeSignature& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The raw signature as a bytes stream") - - .def("__eq__", &CodeSignature::operator==) - .def("__ne__", &CodeSignature::operator!=) - .def("__hash__", - [] (const CodeSignature& func) { - return Hash::hash(func); - }) - - .def("__str__", - [] (const CodeSignature& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyCodeSignatureDir.cpp b/vendor/lief/api/python/MachO/objects/pyCodeSignatureDir.cpp deleted file mode 100644 index acada62..0000000 --- a/vendor/lief/api/python/MachO/objects/pyCodeSignatureDir.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/CodeSignatureDir.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_(m, "CodeSignatureDir") - - .def_property("data_offset", - py::overload_cast<>(&CodeSignatureDir::data_offset, py::const_), - py::overload_cast(&CodeSignatureDir::data_offset), - "Offset in the binary where the signature starts") - - .def_property("data_size", - py::overload_cast<>(&CodeSignatureDir::data_offset, py::const_), - py::overload_cast(&CodeSignatureDir::data_offset), - "Size of the raw signature") - - .def_property_readonly("content", - [] (const CodeSignatureDir& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The raw signature as a bytes stream") - - .def("__eq__", &CodeSignatureDir::operator==) - .def("__ne__", &CodeSignatureDir::operator!=) - .def("__hash__", - [] (const CodeSignatureDir& sig) { - return Hash::hash(sig); - }) - - .def("__str__", - [] (const CodeSignatureDir& dir) - { - std::ostringstream stream; - stream << dir; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDataCodeEntry.cpp b/vendor/lief/api/python/MachO/objects/pyDataCodeEntry.cpp deleted file mode 100644 index 4ef9c27..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDataCodeEntry.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DataCodeEntry.hpp" -#include "LIEF/MachO/EnumToString.hpp" - -#include "enums_wrapper.hpp" - -#include "pyMachO.hpp" - -#define PY_ENUM(x) LIEF::MachO::to_string(x), x - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DataCodeEntry::*)(void) const; - -template -using setter_t = void (DataCodeEntry::*)(T); - - -template<> -void create(py::module& m) { - - - py::class_ cls(m, "DataCodeEntry", - R"delim( - Interface over an entry in the :class:`~lief.MachO.DataInCode` command - )delim"); - - cls - .def(py::init()) - .def_property("offset", - static_cast>(&DataCodeEntry::offset), - static_cast>(&DataCodeEntry::offset), - "Offset of the data") - - .def_property("length", - static_cast>(&DataCodeEntry::length), - static_cast>(&DataCodeEntry::length), - "Length of the data") - - .def_property("type", - static_cast>(&DataCodeEntry::type), - static_cast>(&DataCodeEntry::type), - "Type of the data (" RST_CLASS_REF(lief.MachO.DataCodeEntry.TYPES) "") - - - .def("__eq__", &DataCodeEntry::operator==) - .def("__ne__", &DataCodeEntry::operator!=) - .def("__hash__", - [] (const DataCodeEntry& func) { - return Hash::hash(func); - }) - - - .def("__str__", - [] (const DataCodeEntry& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); - - - LIEF::enum_(cls, "TYPES") - .value(PY_ENUM(DataCodeEntry::TYPES::UNKNOWN)) - .value(PY_ENUM(DataCodeEntry::TYPES::DATA)) - .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_8)) - .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_16)) - .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_32)) - .value(PY_ENUM(DataCodeEntry::TYPES::ABS_JUMP_TABLE_32)); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDataInCode.cpp b/vendor/lief/api/python/MachO/objects/pyDataInCode.cpp deleted file mode 100644 index a07a4d1..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDataInCode.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DataInCode.hpp" - -#include "pyIterators.hpp" -#include "pyMachO.hpp" - - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DataInCode::*)(void) const; - -template -using setter_t = void (DataInCode::*)(T); - - -template<> -void create(py::module& m) { - - // Init Iterator - init_ref_iterator(m, "it_data_in_code_entries"); - - py::class_(m, "DataInCode", - R"delim( - Interface of the LC_DATA_IN_CODE command - - This command is used to list slices of code sections that contain data. The *slices* - information are stored as an array of :class:`~lief.MachO.DataCodeEntry` - )delim") - .def_property("data_offset", - static_cast>(&DataInCode::data_offset), - static_cast>(&DataInCode::data_offset), - "Start of the array of the DataCodeEntry entries") - - .def_property("data_size", - static_cast>(&DataInCode::data_size), - static_cast>(&DataInCode::data_size), - "Whole size of the array (``size = sizeof(DataCodeEntry) * nb_elements``)") - - .def_property_readonly("entries", - static_cast(&DataInCode::entries), - "Iterator over " RST_CLASS_REF(lief.MachO.DataCodeEntry) "", - py::return_value_policy::reference_internal) - - .def("add", - &DataInCode::add, - "Add an new " RST_CLASS_REF(lief.MachO.DataCodeEntry) "", - "entry"_a) - - .def_property_readonly("content", - [] (const DataInCode& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The original content as a bytes stream") - - - .def("__eq__", &DataInCode::operator==) - .def("__ne__", &DataInCode::operator!=) - .def("__hash__", - [] (const DataInCode& func) { - return Hash::hash(func); - }) - - - .def("__str__", - [] (const DataInCode& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); - -} -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDyldBindingInfo.cpp b/vendor/lief/api/python/MachO/objects/pyDyldBindingInfo.cpp deleted file mode 100644 index 4cc8f05..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDyldBindingInfo.cpp +++ /dev/null @@ -1,86 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DyldBindingInfo.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DyldBindingInfo::*)() const; - -template -using setter_t = void (DyldBindingInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DyldBindingInfo", - R"delim( - This class represents a symbol binding operation associated with - the LC_DYLD_INFO bytecode. - - This class does not represent a structure that exists in the Mach-O format - specifications but it provides a *view* on an entry of the Dyld binding opcodes. - - See also: :class:`~lief.MachO.BindingInfo` - )delim") - - .def_property("binding_class", - static_cast>(&DyldBindingInfo::binding_class), - static_cast>(&DyldBindingInfo::binding_class), - "" RST_CLASS_REF(lief.MachO.BINDING_CLASS) " of the binding") - - .def_property("binding_type", - static_cast>(&DyldBindingInfo::binding_type), - static_cast>(&DyldBindingInfo::binding_type), - R"delim( - :class:`~lief.MachO.BIND_TYPES` of the binding. - - Usually, it is :attr:`~lief.MachO.BIND_TYPES.POINTER`. - )delim") - - - .def_property_readonly("original_offset", - &DyldBindingInfo::original_offset, - "Original relative offset of the binding opcodes") - - .def("__eq__", &DyldBindingInfo::operator==) - .def("__ne__", &DyldBindingInfo::operator!=) - .def("__hash__", - [] (const DyldBindingInfo& info) { - return Hash::hash(info); - }) - - .def("__str__", - [] (const DyldBindingInfo& info) { - std::ostringstream stream; - std::string str = stream.str(); - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDyldChainedFixups.cpp b/vendor/lief/api/python/MachO/objects/pyDyldChainedFixups.cpp deleted file mode 100644 index a3dfb48..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDyldChainedFixups.cpp +++ /dev/null @@ -1,187 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "pyIterators.hpp" -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DyldChainedFixups.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_ chained(m, "DyldChainedFixups", - R"delim( - Class that represents the LC_DYLD_CHAINED_FIXUPS command - - This command aims at providing rebase and binding information like - the :class:`~lief.MachO.DyldInfo` 's bytecode. Compared to the :class:`~lief.MachO.DyldInfo` bytecode, - these chained fixups are taking less space. - )delim"); - - init_ref_iterator(chained, "it_binding_info"); - init_ref_iterator(chained, "it_chained_starts_in_segments_t"); - - py::class_(chained, "chained_starts_in_segment", - R"delim( - Structure that mirrors the raw dyld_chained_starts_in_segment - which aims at providing information about the chained rebase/bind fixups - - The relocations provided by this structure can be accessed through :attr:`~lief.MachO.SegmentCommand.relocations` - )delim") - .def_readonly("offset", &DyldChainedFixups::chained_starts_in_segment::offset, - "Original offset of the structure, relative to :attr:`~lief.MachO.DyldChainedFixups.starts_offset`") - .def_readonly("size", &DyldChainedFixups::chained_starts_in_segment::size, - "``sizeof(size) + sizeof(page_size) + ... + sizeof(pointer_format)``") - .def_readonly("page_size", &DyldChainedFixups::chained_starts_in_segment::page_size, - "Likely 0x1000 for x86/x86_64 architectures and 0x4000 for ARM64 architecture") - .def_readonly("segment_offset", &DyldChainedFixups::chained_starts_in_segment::segment_offset, - R"delim( - Offset of the segment's data from the beginning of the file. - (it should match :attr:`~lief.MachO.SegmentCommand.file_offset`) - )delim") - .def_readonly("page_start", &DyldChainedFixups::chained_starts_in_segment::page_start, - R"delim( - Offset in the :class:`~lief.MachO.SegmentCommand` of - the first element of the chain. - )delim") - .def_readonly("pointer_format", &DyldChainedFixups::chained_starts_in_segment::pointer_format, - R"delim( - How pointers are encoded - )delim") - .def_readonly("max_valid_pointer", &DyldChainedFixups::chained_starts_in_segment::max_valid_pointer, - R"delim( - for 32-bit OS, any value beyond this is not a pointer - )delim") - .def_property_readonly("page_count", - &DyldChainedFixups::chained_starts_in_segment::page_count, - "How many pages are in the :attr:`~lief.MachO.DyldChainedFixups.page_start` array") - - .def_property_readonly("segment", - [] (DyldChainedFixups::chained_starts_in_segment& self) -> SegmentCommand* { - return &self.segment; - }, - ":class:`~lief.MachO.SegmentCommand` in which the rebase/bind fixups take place", - py::return_value_policy::reference) - - .def("__str__", - [] (const DyldChainedFixups::chained_starts_in_segment& self) { - std::ostringstream stream; - stream << self; - return stream.str(); - }); - - chained - .def_property("data_offset", - py::overload_cast<>(&DyldChainedFixups::data_offset, py::const_), - py::overload_cast(&DyldChainedFixups::data_offset), - R"delim( - Offset of the LC_DYLD_CHAINED_FIXUPS chained payload. - This offset should point in the ``__LINKEDIT`` segment - )delim") - - .def_property("data_size", - py::overload_cast<>(&DyldChainedFixups::data_size, py::const_), - py::overload_cast(&DyldChainedFixups::data_size), - "Size of the LC_DYLD_CHAINED_FIXUPS payload") - - .def_property_readonly("bindings", - py::overload_cast<>(&DyldChainedFixups::bindings), - "Iterator over the bindings " RST_CLASS_REF(lief.MachO.ChainedBindingInfo) - " associated with this command") - - .def_property_readonly("chained_starts_in_segments", - py::overload_cast<>(&DyldChainedFixups::chained_starts_in_segments), - "Iterator over the chained fixup metadata: " RST_CLASS_REF(lief.MachO.DyldChainedFixups.chained_starts_in_segment) "") - - .def_property("fixups_version", - py::overload_cast<>(&DyldChainedFixups::fixups_version, py::const_), - py::overload_cast(&DyldChainedFixups::fixups_version), - R"delim( - Chained fixups version. The loader (as far of dyld v852.2) checks that this value is set to 0. - )delim") - - .def_property("starts_offset", - py::overload_cast<>(&DyldChainedFixups::starts_offset, py::const_), - py::overload_cast(&DyldChainedFixups::starts_offset), - R"delim( - offset of dyld_chained_starts_in_image in chain_data - )delim") - - .def_property("imports_offset", - py::overload_cast<>(&DyldChainedFixups::imports_offset, py::const_), - py::overload_cast(&DyldChainedFixups::imports_offset), - R"delim( - Offset of imports table in chain data - )delim") - - .def_property("symbols_offset", - py::overload_cast<>(&DyldChainedFixups::symbols_offset, py::const_), - py::overload_cast(&DyldChainedFixups::symbols_offset), - R"delim( - Offset of symbol strings in chain data - )delim") - - .def_property("imports_count", - py::overload_cast<>(&DyldChainedFixups::imports_count, py::const_), - py::overload_cast(&DyldChainedFixups::imports_count), - R"delim( - Number of imported symbol names - )delim") - - .def_property("symbols_format", - py::overload_cast<>(&DyldChainedFixups::symbols_format, py::const_), - py::overload_cast(&DyldChainedFixups::symbols_format), - R"delim( - The compression algorithm (if any) used to store the symbols - 0 means uncompressed while 1 means zlib compressed. - - As far of the version v852.2 of dyld loader, it only supports - **uncompressed** format - )delim") - - .def_property("imports_format", - py::overload_cast<>(&DyldChainedFixups::imports_format, py::const_), - py::overload_cast(&DyldChainedFixups::imports_format), - R"delim( - The format of the imports (:class:`~lief.MachO.ChainedBindingInfo`) - )delim") - - .def("__eq__", &DyldChainedFixups::operator==) - .def("__ne__", &DyldChainedFixups::operator!=) - .def("__hash__", - [] (const DyldChainedFixups& func) { - return Hash::hash(func); - }) - - .def("__str__", - [] (const DyldChainedFixups& fixups) { - std::ostringstream stream; - stream << fixups; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDyldEnvironment.cpp b/vendor/lief/api/python/MachO/objects/pyDyldEnvironment.cpp deleted file mode 100644 index 2dd4a05..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDyldEnvironment.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DyldEnvironment.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DyldEnvironment::*)(void) const; - -template -using setter_t = void (DyldEnvironment::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DyldEnvironment", - R"delim( - Class that represents a LC_DYLD_ENVIRONMENT which is - used by the Mach-O linker/loader to initialize an environment variable - )delim") - - .def_property("value", - static_cast>(&DyldEnvironment::value), - static_cast>(&DyldEnvironment::value), - "Environment variable as a string", - py::return_value_policy::reference_internal) - - .def("__eq__", &DyldEnvironment::operator==) - .def("__ne__", &DyldEnvironment::operator!=) - .def("__hash__", - [] (const DyldEnvironment& env) { - return Hash::hash(env); - }) - - - .def("__str__", - [] (const DyldEnvironment& env) - { - std::ostringstream stream; - stream << env; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDyldExportsTrie.cpp b/vendor/lief/api/python/MachO/objects/pyDyldExportsTrie.cpp deleted file mode 100644 index 20db632..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDyldExportsTrie.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "pyIterators.hpp" - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DyldExportsTrie.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_ exports_trie(m, "DyldExportsTrie", - R"delim( - Class that represents the LC_DYLD_EXPORTS_TRIE command - - In recent Mach-O binaries, this command replace the DyldInfo export trie buffer - )delim"); - - try { - init_ref_iterator(exports_trie, "it_export_info"); - } catch (const std::runtime_error&) { } - - exports_trie - .def_property("data_offset", - py::overload_cast<>(&DyldExportsTrie::data_offset, py::const_), - py::overload_cast(&DyldExportsTrie::data_offset), - "Offset of the trie in the binary. This offset should point in the __LINKEDIT") - - .def_property("data_size", - py::overload_cast<>(&DyldExportsTrie::data_size, py::const_), - py::overload_cast(&DyldExportsTrie::data_size), - "Raw size of the trie") - - .def_property_readonly("content", - [] (const DyldExportsTrie& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The raw export trie") - - .def_property_readonly("exports", - py::overload_cast<>(&DyldExportsTrie::exports), - R"delim( - Iterator over the :class:`~lief.MachO.ExportInfo` associated with - this trie. - )delim") - - .def("show_export_trie", - &DyldExportsTrie::show_export_trie, - "Show the trie in a humman-readable way") - - .def("__eq__", &DyldExportsTrie::operator==) - .def("__ne__", &DyldExportsTrie::operator!=) - .def("__hash__", - [] (const DyldExportsTrie& info) { - return Hash::hash(info); - }) - - .def("__str__", - [] (const DyldExportsTrie& info) { - std::ostringstream stream; - std::string str = stream.str(); - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDyldInfo.cpp b/vendor/lief/api/python/MachO/objects/pyDyldInfo.cpp deleted file mode 100644 index 3913334..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDyldInfo.cpp +++ /dev/null @@ -1,317 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DyldInfo.hpp" - -#include "pyIterators.hpp" -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DyldInfo::*)(void) const; - -template -using setter_t = void (DyldInfo::*)(T); - -template -using no_const_getter = T (DyldInfo::*)(void); - - -template<> -void create(py::module& m) { - - py::class_ dyld(m, "DyldInfo", - R"delim( - Class that represents the LC_DYLD_INFO and LC_DYLD_INFO_ONLY commands - )delim"); - - init_ref_iterator(dyld, "it_binding_info"); - - - try { - init_ref_iterator(dyld, "it_export_info"); - } catch (const std::runtime_error&) { } - - dyld - .def_property("rebase", - static_cast>(&DyldInfo::rebase), - static_cast>(&DyldInfo::rebase), - R"delim( - *Rebase* information as a tuple ``(offset, size)`` - - Dyld rebases an image whenever dyld loads it at an address different - from its preferred address. The rebase information is a stream - of byte sized opcodes for which symbolic names start with ``REBASE_OPCODE_``. - - Conceptually the rebase information is a table of tuples: ``(seg-index, seg-offset, type)`` - - The opcodes are a compressed way to encode the table by only - encoding when a column changes. In addition simple patterns - like "every n'th offset for m times" can be encoded in a few bytes - - .. seealso:: - - ``/usr/include/mach-o/loader.h`` - )delim") - - .def_property("rebase_opcodes", - [] (const DyldInfo& self) { - span content = self.rebase_opcodes(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&DyldInfo::rebase_opcodes), - "Return the rebase's opcodes as ``list`` of bytes") - - .def_property_readonly("show_rebases_opcodes", - &DyldInfo::show_rebases_opcodes, - "Return the rebase opcodes in a humman-readable way") - - .def_property("bind", - static_cast>(&DyldInfo::bind), - static_cast>(&DyldInfo::bind), - R"delim( - *Bind* information as a tuple ``(offset, size)`` - - Dyld binds an image during the loading process, if the image - requires any pointers to be initialized to symbols in other images. - The rebase information is a stream of byte sized opcodes for which symbolic names start with ``BIND_OPCODE_``. - - Conceptually the bind information is a table of tuples: - ``(seg-index, seg-offset, type, symbol-library-ordinal, symbol-name, addend)`` - The opcodes are a compressed way to encode the table by only encoding when a column changes. In addition simple patterns - like for runs of pointers initialzed to the same value can be encoded in a few bytes. - - .. seealso:: - - ``/usr/include/mach-o/loader.h`` - )delim") - - - .def_property("bind_opcodes", - [] (const DyldInfo& self) { - span content = self.bind_opcodes(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&DyldInfo::bind_opcodes), - "Return the binding's opcodes as ``list`` of bytes") - - .def_property_readonly("show_bind_opcodes", - &DyldInfo::show_bind_opcodes, - "Return the bind opcodes in a humman-readable way") - - - .def_property("weak_bind", - static_cast>(&DyldInfo::weak_bind), - static_cast>(&DyldInfo::weak_bind), - R"delim( - *Weak Bind* information as a tuple ``(offset, size)`` - - Some C++ programs require dyld to unique symbols so that all - images in the process use the same copy of some code/data. - - This step is done after binding. - The content of the weak_bind info is an opcode stream like the bind_info. - But it is sorted alphabetically by symbol name. This enables dyld to walk - all images with weak binding information in order and look for collisions. - If there are no collisions, dyld does no updating. - That means that some fixups are also encoded in the bind_info. - For instance, all calls to ``operator new`` are first bound to ``libstdc++.dylib`` - using the information in bind_info. - Then if some image overrides operator new that is detected when - the weak_bind information is processed and the call to operator new is then rebound. - - .. seealso:: - - ``/usr/include/mach-o/loader.h`` - )delim") - - - .def_property("weak_bind_opcodes", - [] (const DyldInfo& self) { - span content = self.weak_bind_opcodes(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&DyldInfo::weak_bind_opcodes), - "Return **Weak** binding's opcodes as ``list`` of bytes") - - .def_property_readonly("show_weak_bind_opcodes", - &DyldInfo::show_weak_bind_opcodes, - "Return the weak bind opcodes in a humman-readable way") - - .def_property("lazy_bind", - static_cast>(&DyldInfo::lazy_bind), - static_cast>(&DyldInfo::lazy_bind), - R"delim( - *Lazy Bind* information as a tuple ``(offset, size)`` - - Some uses of external symbols do not need to be bound immediately. - Instead they can be lazily bound on first use. - The lazy_bind are contains a stream of BIND opcodes to bind all lazy symbols. - Normal use is that dyld ignores the lazy_bind section when loading an image. - Instead the static linker arranged for the lazy pointer to initially point - to a helper function which pushes the offset into the lazy_bind area for the symbol - needing to be bound, then jumps to dyld which simply adds the offset to - lazy_bind_off to get the information on what to bind. - - .. seealso:: - - ``/usr/include/mach-o/loader.h`` - )delim") - - - .def_property("lazy_bind_opcodes", - [] (const DyldInfo& self) { - span content = self.lazy_bind_opcodes(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&DyldInfo::lazy_bind_opcodes), - "Return **lazy** binding's opcodes as ``list`` of bytes") - - .def_property_readonly("show_lazy_bind_opcodes", - &DyldInfo::show_lazy_bind_opcodes, - "Return the weak bind opcodes in a humman-readable way", - py::return_value_policy::reference_internal) - - .def_property_readonly("bindings", - static_cast>(&DyldInfo::bindings), - "Return an iterator over Dyld's " RST_CLASS_REF(lief.MachO.BindingInfo) "", - py::return_value_policy::reference_internal) - - .def_property("export_info", - static_cast>(&DyldInfo::export_info), - static_cast>(&DyldInfo::export_info), - R"delim( - *Export* information as a tuple ``(offset, size)`` - - The symbols exported by a dylib are encoded in a trie. - This is a compact representation that factors out common prefixes. - - It also reduces ``LINKEDIT`` pages in RAM because it encodes all - information (name, address, flags) in one small, contiguous range. - The export area is a stream of nodes. The first node sequentially - is the start node for the trie. - - Nodes for a symbol start with a byte that is the length of the exported - symbol information for the string so far. - If there is no exported symbol, the byte is zero. - If there is exported info, it follows the length byte. - The exported info normally consists of a flags and offset both encoded - in `uleb128 `_. - The offset is location of the content named by the symbol. - It is the offset from the mach_header for the image. - - After the initial byte and optional exported symbol information - is a byte of how many edges (0-255) that this node has leaving - it, followed by each edge. - Each edge is a zero terminated cstring of the addition chars - in the symbol, followed by a uleb128 offset for the node that - edge points to. - - .. seealso:: - - ``/usr/include/mach-o/loader.h`` - )delim") - - - .def_property("export_trie", - [] (const DyldInfo& self) { - span content = self.export_trie(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&DyldInfo::export_trie), - "Return Export's trie as ``list`` of bytes") - - .def_property_readonly("exports", - static_cast>(&DyldInfo::exports), - "Return an iterator over Dyld's " RST_CLASS_REF(lief.MachO.ExportInfo) "", - py::return_value_policy::reference_internal) - - .def_property_readonly("show_export_trie", - &DyldInfo::show_export_trie, - "Return the export trie in a humman-readable way", - py::return_value_policy::reference_internal) - - .def("set_rebase_offset", - &DyldInfo::set_rebase_offset, - "offset"_a) - - .def("set_rebase_size", - &DyldInfo::set_rebase_size, - "size"_a) - - - .def("set_bind_offset", - &DyldInfo::set_bind_offset, - "offset"_a) - - .def("set_bind_size", - &DyldInfo::set_bind_size, - "size"_a) - - - .def("set_weak_bind_offset", - &DyldInfo::set_weak_bind_offset, - "offset"_a) - - .def("set_weak_bind_size", - &DyldInfo::set_weak_bind_size, - "size"_a) - - - .def("set_lazy_bind_offset", - &DyldInfo::set_lazy_bind_offset, - "offset"_a) - - .def("set_lazy_bind_size", - &DyldInfo::set_lazy_bind_size, - "size"_a) - - - .def("set_export_offset", - &DyldInfo::set_export_offset, - "offset"_a) - - .def("set_export_size", - &DyldInfo::set_export_size, - "size"_a) - - .def("__eq__", &DyldInfo::operator==) - .def("__ne__", &DyldInfo::operator!=) - .def("__hash__", - [] (const DyldInfo& info) { - return Hash::hash(info); - }) - - - .def("__str__", - [] (const DyldInfo& info) { - std::ostringstream stream; - stream << info; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDylibCommand.cpp b/vendor/lief/api/python/MachO/objects/pyDylibCommand.cpp deleted file mode 100644 index 028f68c..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDylibCommand.cpp +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DylibCommand.hpp" - -#include "pyMachO.hpp" - - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DylibCommand::*)(void) const; - -template -using setter_t = void (DylibCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DylibCommand", - R"delim( - Class which represents a library dependency - )delim") - - .def_property("name", - static_cast>(&DylibCommand::name), - static_cast>(&DylibCommand::name), - "Library's name", - py::return_value_policy::reference_internal) - - .def_property("timestamp", - static_cast>(&DylibCommand::timestamp), - static_cast>(&DylibCommand::timestamp), - "Library's timestamp", - py::return_value_policy::reference_internal) - - .def_property("current_version", - static_cast>(&DylibCommand::current_version), - static_cast>(&DylibCommand::current_version), - "Library's current version", - py::return_value_policy::reference_internal) - - .def_property("compatibility_version", - static_cast>(&DylibCommand::compatibility_version), - static_cast>(&DylibCommand::compatibility_version), - "Library's compatibility version", - py::return_value_policy::reference_internal) - - .def_static("weak_lib", - &DylibCommand::weak_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.LOAD_WEAK_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def_static("id_dylib", - &DylibCommand::id_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.ID_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def_static("load_dylib", - &DylibCommand::load_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.LOAD_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def_static("reexport_dylib", - &DylibCommand::reexport_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.REEXPORT_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def_static("load_upward_dylib", - &DylibCommand::load_upward_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.LOAD_UPWARD_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def_static("lazy_load_dylib", - &DylibCommand::lazy_load_dylib, - "Factory function to generate a " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES.LAZY_LOAD_DYLIB) " library", - "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) - - .def("__eq__", &DylibCommand::operator==) - .def("__ne__", &DylibCommand::operator!=) - .def("__hash__", - [] (const DylibCommand& dylib_command) { - return Hash::hash(dylib_command); - }) - - - .def("__str__", - [] (const DylibCommand& command) - { - std::ostringstream stream; - stream << command; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDylinker.cpp b/vendor/lief/api/python/MachO/objects/pyDylinker.cpp deleted file mode 100644 index 8b9d959..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDylinker.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DylinkerCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DylinkerCommand::*)(void) const; - -template -using setter_t = void (DylinkerCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "DylinkerCommand", - R"delim( - Class that represents the Mach-O linker, also named loader - Most of the time, :attr:`~lief.MachO.DylinkerCommand.name` returns ``/usr/lib/dyld`` - )delim") - - .def_property("name", - static_cast>(&DylinkerCommand::name), - static_cast>(&DylinkerCommand::name), - "Path to the loader/linker", - py::return_value_policy::reference_internal) - - .def("__eq__", &DylinkerCommand::operator==) - .def("__ne__", &DylinkerCommand::operator!=) - .def("__hash__", - [] (const DylinkerCommand& dylinker) { - return Hash::hash(dylinker); - }) - - - .def("__str__", - [] (const DylinkerCommand& dylinker) - { - std::ostringstream stream; - stream << dylinker; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyDynamicSymbolCommand.cpp b/vendor/lief/api/python/MachO/objects/pyDynamicSymbolCommand.cpp deleted file mode 100644 index 6c88653..0000000 --- a/vendor/lief/api/python/MachO/objects/pyDynamicSymbolCommand.cpp +++ /dev/null @@ -1,204 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/DynamicSymbolCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (DynamicSymbolCommand::*)(void) const; - -template -using setter_t = void (DynamicSymbolCommand::*)(T); - -template -using no_const_getter = T (DynamicSymbolCommand::*)(void); - - -template<> -void create(py::module& m) { - - py::class_(m, "DynamicSymbolCommand", - R"delim( - Class that represents the LC_DYSYMTAB command. - This command completes the LC_SYMTAB (SymbolCommand) to provide - a better granularity over the symbols layout. - )delim") - - .def_property("idx_local_symbol", - static_cast>(&DynamicSymbolCommand::idx_local_symbol), - static_cast>(&DynamicSymbolCommand::idx_local_symbol), - "Index of the first symbol in the group of local symbols." - ) - - .def_property("nb_local_symbols", - static_cast>(&DynamicSymbolCommand::nb_local_symbols), - static_cast>(&DynamicSymbolCommand::nb_local_symbols), - "Number of symbols in the group of local symbols." - ) - - .def_property("idx_external_define_symbol", - static_cast>(&DynamicSymbolCommand::idx_external_define_symbol), - static_cast>(&DynamicSymbolCommand::idx_external_define_symbol), - "Index of the first symbol in the group of defined external symbols." - ) - - .def_property("nb_external_define_symbols", - static_cast>(&DynamicSymbolCommand::nb_external_define_symbols), - static_cast>(&DynamicSymbolCommand::nb_external_define_symbols), - "Number of symbols in the group of defined external symbols." - ) - - .def_property("idx_undefined_symbol", - static_cast>(&DynamicSymbolCommand::idx_undefined_symbol), - static_cast>(&DynamicSymbolCommand::idx_undefined_symbol), - "Index of the first symbol in the group of undefined external symbols." - ) - - .def_property("nb_undefined_symbols", - static_cast>(&DynamicSymbolCommand::nb_undefined_symbols), - static_cast>(&DynamicSymbolCommand::nb_undefined_symbols), - "Number of symbols in the group of undefined external symbols." - ) - - .def_property("toc_offset", - static_cast>(&DynamicSymbolCommand::toc_offset), - static_cast>(&DynamicSymbolCommand::toc_offset), - R"delim( - Byte offset from the start of the file to the table of contents data. - Table of content is used by legacy Mach-O loader and this field should be set to 0 - )delim") - - .def_property("nb_toc", - static_cast>(&DynamicSymbolCommand::nb_toc), - static_cast>(&DynamicSymbolCommand::nb_toc), - R"delim( - Number of entries in the table of contents - Should be set to 0 on recent Mach-O - )delim") - - .def_property("module_table_offset", - static_cast>(&DynamicSymbolCommand::module_table_offset), - static_cast>(&DynamicSymbolCommand::module_table_offset), - R"delim( - Byte offset from the start of the file to the module table data. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def_property("nb_module_table", - static_cast>(&DynamicSymbolCommand::nb_module_table), - static_cast>(&DynamicSymbolCommand::nb_module_table), - R"delim( - Number of entries in the module table. - This field seems unused by recent Mach-O loader and should be set to 0. - )delim") - - .def_property("external_reference_symbol_offset", - static_cast>(&DynamicSymbolCommand::external_reference_symbol_offset), - static_cast>(&DynamicSymbolCommand::external_reference_symbol_offset), - R"delim( - Byte offset from the start of the file to the external reference table data. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def_property("nb_external_reference_symbols", - static_cast>(&DynamicSymbolCommand::nb_external_reference_symbols), - static_cast>(&DynamicSymbolCommand::nb_external_reference_symbols), - R"delim( - Number of entries in the external reference table. - This field seems unused by recent Mach-O loader and should be set to 0. - )delim") - - .def_property("indirect_symbol_offset", - static_cast>(&DynamicSymbolCommand::indirect_symbol_offset), - static_cast>(&DynamicSymbolCommand::indirect_symbol_offset), - R"delim( - Byte offset from the start of the file to the indirect symbol table data. - - Indirect symbol table is used by the loader to speed-up symbol resolution during - the *lazy binding* process - - References: - - * ``dyld-519.2.1/src/ImageLoaderMachOCompressed.cpp`` - * ``dyld-519.2.1/src/ImageLoaderMachOClassic.cpp`` - )delim") - - .def_property("nb_indirect_symbols", - static_cast>(&DynamicSymbolCommand::nb_indirect_symbols), - static_cast>(&DynamicSymbolCommand::nb_indirect_symbols), - "Number of entries in the indirect symbol table.") - - .def_property("external_relocation_offset", - static_cast>(&DynamicSymbolCommand::external_relocation_offset), - static_cast>(&DynamicSymbolCommand::external_relocation_offset), - R"delim( - Byte offset from the start of the file to the module table data. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def_property("nb_external_relocations", - static_cast>(&DynamicSymbolCommand::nb_external_relocations), - static_cast>(&DynamicSymbolCommand::nb_external_relocations), - R"delim( - Number of entries in the external relocation table. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def_property("local_relocation_offset", - static_cast>(&DynamicSymbolCommand::local_relocation_offset), - static_cast>(&DynamicSymbolCommand::local_relocation_offset), - R"delim( - Byte offset from the start of the file to the local relocation table data. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def_property("nb_local_relocations", - static_cast>(&DynamicSymbolCommand::nb_local_relocations), - static_cast>(&DynamicSymbolCommand::nb_local_relocations), - R"delim( - Number of entries in the local relocation table. - This field seems unused by recent Mach-O loader and should be set to 0 - )delim") - - .def("__eq__", &DynamicSymbolCommand::operator==) - .def("__ne__", &DynamicSymbolCommand::operator!=) - .def("__hash__", - [] (const DynamicSymbolCommand& cmd) { - return Hash::hash(cmd); - }) - - - .def("__str__", - [] (const DynamicSymbolCommand& info) - { - std::ostringstream stream; - stream << info; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyEncryptionInfo.cpp b/vendor/lief/api/python/MachO/objects/pyEncryptionInfo.cpp deleted file mode 100644 index a936061..0000000 --- a/vendor/lief/api/python/MachO/objects/pyEncryptionInfo.cpp +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/EncryptionInfo.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (EncryptionInfo::*)(void) const; - -template -using setter_t = void (EncryptionInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "EncryptionInfo", - R"delim( - Class that represents the LC_ENCRYPTION_INFO / LC_ENCRYPTION_INFO_64 commands - - The encryption info is usually present in Mach-O executables that - target iOS to encrypt some sections of the binary - )delim") - - .def_property("crypt_offset", - static_cast>(&EncryptionInfo::crypt_offset), - static_cast>(&EncryptionInfo::crypt_offset), - "File offset of encrypted range") - - .def_property("crypt_size", - static_cast>(&EncryptionInfo::crypt_size), - static_cast>(&EncryptionInfo::crypt_size), - "File size of encrypted range") - - .def_property("crypt_id", - static_cast>(&EncryptionInfo::crypt_id), - static_cast>(&EncryptionInfo::crypt_id), - "The encryption system. 0 means no encrypted") - - - - .def("__eq__", &EncryptionInfo::operator==) - .def("__ne__", &EncryptionInfo::operator!=) - .def("__hash__", - [] (const EncryptionInfo& uuid) { - return Hash::hash(uuid); - }) - - - .def("__str__", - [] (const EncryptionInfo& uuid) - { - std::ostringstream stream; - stream << uuid; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyExportInfo.cpp b/vendor/lief/api/python/MachO/objects/pyExportInfo.cpp deleted file mode 100644 index 8b4731d..0000000 --- a/vendor/lief/api/python/MachO/objects/pyExportInfo.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/ExportInfo.hpp" -#include "LIEF/MachO/Symbol.hpp" -#include "LIEF/MachO/DylibCommand.hpp" - -#include "pyMachO.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (ExportInfo::*)(void) const; - -template -using no_const_getter_t = T (ExportInfo::*)(void); - -template -using setter_t = void (ExportInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "ExportInfo", - R"delim( - Class that provides an interface over the Dyld export info - - This class does not represent a structure that exists in the Mach-O format - specification but provides a *view* on an entry of the Dyld export trie. - )delim") - - .def_property_readonly("node_offset", - static_cast>(&ExportInfo::node_offset), - "Original offset in the export Trie") - - .def_property_readonly("kind", - static_cast>(&ExportInfo::kind), - "The export's kind: regular, thread local, absolute, ... (" RST_CLASS_REF(lief.MachO.EXPORT_SYMBOL_KINDS) ")") - - .def_property_readonly("flags_list", - static_cast>(&ExportInfo::flags_list), - "Return flags as a list of " RST_CLASS_REF(lief.MachO.EXPORT_SYMBOL_KINDS) "") - - .def_property("flags", - static_cast>(&ExportInfo::flags), - static_cast>(&ExportInfo::flags), - "Some information (" RST_CLASS_REF(lief.MachO.EXPORT_SYMBOL_FLAGS) ") about the export (like weak export, reexport, ...)") - - .def_property("address", - static_cast>(&ExportInfo::address), - static_cast>(&ExportInfo::address), - "The address of the export") - - .def_property_readonly("alias", - static_cast>(&ExportInfo::alias), - "" RST_CLASS_REF(lief.MachO.Symbol) " alias if the current symbol is re-exported", - py::return_value_policy::reference) - - .def_property_readonly("alias_library", - static_cast>(&ExportInfo::alias_library), - "If the current symbol has an alias, it returns the " RST_CLASS_REF(lief.MachO.DylibCommand) " " - " command associated with", - py::return_value_policy::reference) - - .def_property_readonly("has_symbol", - &ExportInfo::has_symbol, - "``True`` if the export info has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with") - - .def("has", - &ExportInfo::has, - "Check if the flag " RST_CLASS_REF(lief.MachO.EXPORT_SYMBOL_FLAGS) " given in first parameter is present" - "flag"_a) - - .def_property_readonly("symbol", - static_cast(&ExportInfo::symbol), - "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the export if any, or None ", - py::return_value_policy::reference) - - - .def("__eq__", &ExportInfo::operator==) - .def("__ne__", &ExportInfo::operator!=) - .def("__hash__", - [] (const ExportInfo& export_info) { - return Hash::hash(export_info); - }) - - - .def("__str__", - [] (const ExportInfo& export_info) - { - std::ostringstream stream; - stream << export_info; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyFatBinary.cpp b/vendor/lief/api/python/MachO/objects/pyFatBinary.cpp deleted file mode 100644 index 9bb1ecb..0000000 --- a/vendor/lief/api/python/MachO/objects/pyFatBinary.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "LIEF/MachO/FatBinary.hpp" - -#include "pyIterators.hpp" -#include "pyMachO.hpp" - - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - - py::class_ fat(m, "FatBinary", - R"delim( - Class which represent a Mach-O (fat) binary - This object is also used for representing Mach-O binaries that are **NOT FAT** - )delim"); - - init_ref_iterator(fat, "it_binaries"); - - fat - .def_property_readonly("size", - &FatBinary::size, - "Number of " RST_CLASS_REF(lief.MachO.Binary) " registred") - - .def("at", - static_cast(&FatBinary::at), - "Return the " RST_CLASS_REF(lief.MachO.Binary) " at the given index or None if it is not present", - "index"_a, - py::return_value_policy::reference_internal) - - .def("take", - static_cast(FatBinary::*)(CPU_TYPES)>(&FatBinary::take), - "Return the " RST_CLASS_REF(lief.MachO.Binary) " that matches the " - "given " RST_CLASS_REF(lief.MachO.CPU_TYPES) "", - "cpu"_a, - py::return_value_policy::take_ownership) - - .def("write", - &FatBinary::write, - "Build a Mach-O universal binary", - "filename"_a) - - .def("raw", - &FatBinary::raw, - "Build a Mach-O universal binary and return its bytes") - - .def("__len__", - &FatBinary::size) - - .def("__getitem__", - static_cast(&FatBinary::operator[]), - "", - py::return_value_policy::reference_internal) - - .def("__iter__", - static_cast(&FatBinary::begin), - py::return_value_policy::reference_internal) - - .def("__str__", - [] (const FatBinary& fat_binary) - { - std::ostringstream stream; - stream << fat_binary; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyFilesetCommand.cpp b/vendor/lief/api/python/MachO/objects/pyFilesetCommand.cpp deleted file mode 100644 index 7bb917d..0000000 --- a/vendor/lief/api/python/MachO/objects/pyFilesetCommand.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/FilesetCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (FilesetCommand::*)(void) const; - -template -using setter_t = void (FilesetCommand::*)(T); - -template -using no_const_getter_t = T (FilesetCommand::*)(); - - - -template<> -void create(py::module& m) { - - py::class_(m, "FilesetCommand", - "Class associated with the LC_FILESET_ENTRY commands") - .def_property("name", - static_cast>(&FilesetCommand::name), - static_cast>(&FilesetCommand::name), - "Name of the underlying MachO binary") - - .def_property("virtual_address", - static_cast>(&FilesetCommand::virtual_address), - static_cast>(&FilesetCommand::virtual_address), - "Memory address where the MachO file should be mapped") - - .def_property("file_offset", - static_cast>(&FilesetCommand::file_offset), - static_cast>(&FilesetCommand::file_offset), - "Original offset in the kernel cache") - - .def_property_readonly("binary", - static_cast>(&FilesetCommand::binary), - "Return the " RST_CLASS_REF(lief.MachO.Binary) " object associated with the entry", - py::return_value_policy::reference) - - .def("__eq__", &FilesetCommand::operator==) - .def("__ne__", &FilesetCommand::operator!=) - .def("__hash__", - [] (const FilesetCommand& main) { - return Hash::hash(main); - }) - - - .def("__str__", - [] (const FilesetCommand& main) - { - std::ostringstream stream; - stream << main; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyFunctionStarts.cpp b/vendor/lief/api/python/MachO/objects/pyFunctionStarts.cpp deleted file mode 100644 index 73a088b..0000000 --- a/vendor/lief/api/python/MachO/objects/pyFunctionStarts.cpp +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/FunctionStarts.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (FunctionStarts::*)(void) const; - -template -using setter_t = void (FunctionStarts::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "FunctionStarts", - R"delim( - Class which represents the LC_FUNCTION_STARTS command - - This command is an array of ULEB128 encoded values - )delim") - - .def_property("data_offset", - static_cast>(&FunctionStarts::data_offset), - static_cast>(&FunctionStarts::data_offset), - "Offset in the binary where *start functions* are located") - - .def_property("data_size", - static_cast>(&FunctionStarts::data_size), - static_cast>(&FunctionStarts::data_size), - "Size of the functions list in the binary") - - .def_property("functions", - static_cast&>>(&FunctionStarts::functions), - static_cast&>>(&FunctionStarts::functions), - R"delim( - Addresses of every function entry point in the executable - - This allows functions to exist for which there are no entries in the symbol table. - - .. warning:: - - The address is relative to the ``__TEXT`` segment - )delim", - py::return_value_policy::reference_internal) - - .def("add_function", - &FunctionStarts::add_function, - "Add a new function", - "address"_a) - - .def_property_readonly("content", - [] (const FunctionStarts& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The original content as a bytes stream") - - .def("__eq__", &FunctionStarts::operator==) - .def("__ne__", &FunctionStarts::operator!=) - .def("__hash__", - [] (const FunctionStarts& func) { - return Hash::hash(func); - }) - - - .def("__str__", - [] (const FunctionStarts& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyHeader.cpp b/vendor/lief/api/python/MachO/objects/pyHeader.cpp deleted file mode 100644 index fc024fb..0000000 --- a/vendor/lief/api/python/MachO/objects/pyHeader.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/Header.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - - -template<> -void create
(py::module& m) { - - py::class_(m, "Header", - "Class that represents the Mach-O header") - .def(py::init<>()) - - .def_property("magic", - static_cast>(&Header::magic), - static_cast>(&Header::magic), - R"delim( - The Mach-O magic bytes. These bytes determine whether it is - a 32 bits Mach-O, a 64 bits Mach-O files etc. - )delim") - - .def_property("cpu_type", - static_cast>(&Header::cpu_type), - static_cast>(&Header::cpu_type), - "Target CPU ( " RST_CLASS_REF(lief.MachO.CPU_TYPES) ")") - - .def_property("cpu_subtype", - static_cast>(&Header::cpu_subtype), - static_cast>(&Header::cpu_subtype), - R"delim( - Return the CPU subtype supported by the Mach-O binary. - For ARM architectures, this value could represent the minimum version - for which the Mach-O binary has been compiled for. - )delim") - - .def_property("file_type", - static_cast>(&Header::file_type), - static_cast>(&Header::file_type), - "Binary's type ( " RST_CLASS_REF(lief.MachO.FILE_TYPES) ")") - - .def_property("flags", - static_cast>(&Header::flags), - static_cast>(&Header::flags), - "Binary's flags ( " RST_CLASS_REF(lief.MachO.HEADER_FLAGS) ")") - - .def_property("nb_cmds", - static_cast>(&Header::nb_cmds), - static_cast>(&Header::nb_cmds), - "Number of " RST_CLASS_REF(lief.MachO.LoadCommand) "") - - .def_property("sizeof_cmds", - static_cast>(&Header::sizeof_cmds), - static_cast>(&Header::sizeof_cmds), - "Size of all " RST_CLASS_REF(lief.MachO.LoadCommand) "") - - .def_property("reserved", - static_cast>(&Header::reserved), - static_cast>(&Header::reserved), - "According to the official documentation, a reserved value") - - .def_property_readonly("flags_list", - &Header::flags_list, - "" RST_CLASS_REF(lief.PE.HEADER_FLAGS) " as a list") - - .def("add", - static_cast(&Header::add), - "Add the given " RST_CLASS_REF(lief.MachO.HEADER_FLAGS) "", - "flag"_a) - - .def("remove", - static_cast(&Header::remove), - "Remove the given " RST_CLASS_REF(lief.MachO.HEADER_FLAGS) "", - "flag"_a) - - .def("has", - static_cast(&Header::has), - "``True`` if the given " RST_CLASS_REF(lief.MachO.HEADER_FLAGS) " is in the " - ":attr:`~lief.MachO.Header.flags`", - "flag"_a) - - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - .def(py::self += HEADER_FLAGS()) - .def(py::self -= HEADER_FLAGS()) - - .def("__contains__", - static_cast(&Header::has), - "Check if the given " RST_CLASS_REF(lief.MachO.HEADER_FLAGS) " is present") - - - .def("__str__", - [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyLinkerOptHint.cpp b/vendor/lief/api/python/MachO/objects/pyLinkerOptHint.cpp deleted file mode 100644 index f46609a..0000000 --- a/vendor/lief/api/python/MachO/objects/pyLinkerOptHint.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/LinkerOptHint.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_(m, "LinkerOptHint", - R"delim( - Class which represents the `LC_LINKER_OPTIMIZATION_HINT` command - )delim") - - .def_property("data_offset", - py::overload_cast<>(&LinkerOptHint::data_offset, py::const_), - py::overload_cast(&LinkerOptHint::data_offset), - "Offset in the binary where the payload starts") - - .def_property("data_size", - py::overload_cast<>(&LinkerOptHint::data_offset, py::const_), - py::overload_cast(&LinkerOptHint::data_offset), - "Size of the raw payload") - - .def_property_readonly("content", - [] (const LinkerOptHint& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The raw payload") - - .def("__eq__", &LinkerOptHint::operator==) - .def("__ne__", &LinkerOptHint::operator!=) - .def("__hash__", - [] (const LinkerOptHint& opt) { - return Hash::hash(opt); - }) - - .def("__str__", - [] (const LinkerOptHint& opt) - { - std::ostringstream stream; - stream << opt; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyLoadCommand.cpp b/vendor/lief/api/python/MachO/objects/pyLoadCommand.cpp deleted file mode 100644 index fd9f3c2..0000000 --- a/vendor/lief/api/python/MachO/objects/pyLoadCommand.cpp +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/LoadCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (LoadCommand::*)(void) const; - -template -using setter_t = void (LoadCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "LoadCommand", - "Based class for the Mach-O load commands") - .def(py::init<>()) - - .def_property("command", - static_cast>(&LoadCommand::command), - static_cast>(&LoadCommand::command), - "Command type ( " RST_CLASS_REF(lief.MachO.LOAD_COMMAND_TYPES) ")" - ) - - .def_property("size", - static_cast>(&LoadCommand::size), - static_cast>(&LoadCommand::size), - "Size of the command (should be greather than ``sizeof(load_command)``)") - - .def_property("data", - static_cast>(&LoadCommand::data), - static_cast>(&LoadCommand::data), - "Command's data") - - .def_property("command_offset", - static_cast>(&LoadCommand::command_offset), - static_cast>(&LoadCommand::command_offset), - "Offset of the command within the *Load Command Table*") - - .def("__eq__", &LoadCommand::operator==) - .def("__ne__", &LoadCommand::operator!=) - .def("__hash__", - [] (const LoadCommand& load_command) { - return Hash::hash(load_command); - }) - - .def("__str__", - [] (const LoadCommand& command) - { - std::ostringstream stream; - stream << command; - std::string str = stream.str(); - return str; - }); -} - - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyMainCommand.cpp b/vendor/lief/api/python/MachO/objects/pyMainCommand.cpp deleted file mode 100644 index 76d5a60..0000000 --- a/vendor/lief/api/python/MachO/objects/pyMainCommand.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/MainCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (MainCommand::*)(void) const; - -template -using setter_t = void (MainCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "MainCommand", - R"delim( - Class that represent the LC_MAIN command. This kind - of command can be used to determine the entrypoint of an executable - )delim") - - .def_property("entrypoint", - static_cast>(&MainCommand::entrypoint), - static_cast>(&MainCommand::entrypoint), - "Offset of the *main* function relative to the ``__TEXT`` segment") - - .def_property("stack_size", - static_cast>(&MainCommand::stack_size), - static_cast>(&MainCommand::stack_size), - "The initial stack size (if not 0)") - - - .def("__eq__", &MainCommand::operator==) - .def("__ne__", &MainCommand::operator!=) - .def("__hash__", - [] (const MainCommand& main) { - return Hash::hash(main); - }) - - - .def("__str__", - [] (const MainCommand& main) - { - std::ostringstream stream; - stream << main; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyParser.cpp b/vendor/lief/api/python/MachO/objects/pyParser.cpp deleted file mode 100644 index b3f13c0..0000000 --- a/vendor/lief/api/python/MachO/objects/pyParser.cpp +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/Parser.hpp" -#include "LIEF/MachO/FatBinary.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - // Parser (Parser) - m.def("parse", - static_cast (*) (const std::string&, const ParserConfig&)>(&LIEF::MachO::Parser::parse), - R"delim( - Parse the given binary and return a :class:`~lief.MachO.FatBinary` object - - One can configure the parsing with the ``config`` parameter. See :class:`~lief.MachO.ParserConfig`, - )delim", - "filename"_a, - "config"_a = ParserConfig::deep(), - py::return_value_policy::take_ownership); - - - m.def("parse", - static_cast (*) (const std::vector&, const std::string&, const ParserConfig&)>(&LIEF::MachO::Parser::parse), - R"delim( - Parse the given binary (from raw bytes) and return a :class:`~lief.MachO.FatBinary` object - - One can configure the parsing with the ``config`` parameter. See :class:`~lief.MachO.ParserConfig` - )delim", - "raw"_a, - "name"_a = "", - "config"_a = ParserConfig::quick(), - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, std::string name, const ParserConfig& config) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::MachO::Parser::parse(std::move(raw), name, config); - }, - R"delim( - Parse the given binary from a Python IO interface and return a :class:`~lief.MachO.FatBinary` object - - One can configure the parsing with the ``config`` parameter. See :class:`~lief.MachO.ParserConfig` - )delim", - "io"_a, - "name"_a = "", - "config"_a = ParserConfig::quick(), - py::return_value_policy::take_ownership); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyParserConfig.cpp b/vendor/lief/api/python/MachO/objects/pyParserConfig.cpp deleted file mode 100644 index 5bee190..0000000 --- a/vendor/lief/api/python/MachO/objects/pyParserConfig.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "LIEF/MachO/ParserConfig.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_(m, "ParserConfig", - R"delim( - This class is used to tweak the MachO Parser (:class:`~lief.MachO.Parser`) - )delim") - - .def(py::init<>()) - .def_readwrite("parse_dyld_exports", &ParserConfig::parse_dyld_exports, - "Parse the Dyld export trie") - - .def_readwrite("parse_dyld_bindings", &ParserConfig::parse_dyld_bindings, - "Parse the Dyld binding opcodes") - - .def_readwrite("parse_dyld_rebases", &ParserConfig::parse_dyld_rebases, - "Parse the Dyld rebase opcodes") - - .def("full_dyldinfo", &ParserConfig::full_dyldinfo, - R"delim( - If ``flag`` is set to ``true``, Exports, Bindings and Rebases opcodes are parsed. - - .. warning:: - - Enabling this flag can slow down the parsing - )delim", - "flag"_a) - - .def_property_readonly_static("deep", - [] (py::object /* self */) { return ParserConfig::deep(); }, - R"delim( - Return a parser configuration such as all the objects supported by LIEF are parsed - )delim") - - .def_property_readonly_static("quick", - [] (py::object /* self */) { return ParserConfig::quick(); }, - R"delim( - Return a configuration to parse the most important MachO structures - )delim"); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyRPathCommand.cpp b/vendor/lief/api/python/MachO/objects/pyRPathCommand.cpp deleted file mode 100644 index 15c6833..0000000 --- a/vendor/lief/api/python/MachO/objects/pyRPathCommand.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 - 2021 J.Rieck (based on R. Thomas's work) - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/RPathCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (RPathCommand::*)(void) const; - -template -using setter_t = void (RPathCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "RPathCommand") - - .def_property("path", - static_cast>(&RPathCommand::path), - static_cast>(&RPathCommand::path), - "@rpath path", - py::return_value_policy::reference_internal) - - - .def("__eq__", &RPathCommand::operator==) - .def("__ne__", &RPathCommand::operator!=) - .def("__hash__", - [] (const RPathCommand& rpath_command) { - return Hash::hash(rpath_command); - }) - - - .def("__str__", - [] (const RPathCommand& rpath_command) - { - std::ostringstream stream; - stream << rpath_command; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyRelocation.cpp b/vendor/lief/api/python/MachO/objects/pyRelocation.cpp deleted file mode 100644 index 47d9ef8..0000000 --- a/vendor/lief/api/python/MachO/objects/pyRelocation.cpp +++ /dev/null @@ -1,155 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/Relocation.hpp" -#include "LIEF/MachO/Symbol.hpp" -#include "LIEF/MachO/Section.hpp" -#include "LIEF/MachO/SegmentCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (Relocation::*)(void) const; - -template -using setter_t = void (Relocation::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "Relocation", - R"delim( - It extends the LIEF :class:`lief.Relocation` abstract class and it is sub-classed by - - 1. :class:`~lief.MachO.RelocationObject` - 2. :class:`~lief.MachO.RelocationDyld` - )delim") - - .def_property("address", - static_cast>(&Relocation::address), - static_cast>(&Relocation::address), - R"delim( - For :attr:`~lief.MachO.FILE_TYPES.OBJECT` or (:attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.RELOCATION_ORIGINS.RELOC_TABLE`) this is an " - offset from the start of the :class:`~lief.MachO.Section` - to the item containing the address requiring relocation. - - For :attr:`~lief.MachO.FILE_TYPES.EXECUTE` / :attr:`~lief.MachO.FILE_TYPES.DYLIB` or - (:attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.RELOCATION_ORIGINS.DYLDINFO`) - this is a :attr:`~lief.MachO.SegmentCommand.virtual_address`. - )delim") - - .def_property("pc_relative", - static_cast>(&Relocation::is_pc_relative), - static_cast>(&Relocation::pc_relative), - R"delim( - Indicates whether the item containing the address to be - relocated is part of a CPU instruction that uses PC-relative addressing. - - For addresses contained in PC-relative instructions, the CPU adds the address of - the instruction to the address contained in the instruction. - )delim") - - .def_property("type", - static_cast>(&Relocation::type), - static_cast>(&Relocation::type), - R"delim( - Type of the relocation according to the :attr:`~lief.MachO.Relocation.architecture` and/or :attr:`~lief.MachO.Relocation.origin` - - If :attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.RELOCATION_ORIGINS.RELOC_TABLE`: - - See: - - * :class:`lief.MachO.X86_RELOCATION` - * :class:`lief.MachO.X86_64_RELOCATION` - * :class:`lief.MachO.PPC_RELOCATION` - * :class:`lief.MachO.ARM_RELOCATION` - * :class:`lief.MachO.ARM64_RELOCATION` - - If :attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.RELOCATION_ORIGINS.DYLDINFO`, - the value is associated with :class:`~lief.MachO.REBASE_TYPES`. - )delim") - - .def_property_readonly("architecture", - &Relocation::architecture, - "" RST_CLASS_REF(lief.MachO.CPU_TYPES) " of the relocation") - - .def_property_readonly("has_symbol", - &Relocation::has_symbol, - "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with") - - .def_property_readonly("symbol", - static_cast(&Relocation::symbol), - "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the relocation if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_section", - &Relocation::has_section, - "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.Section) " associated with") - - .def_property_readonly("section", - static_cast(&Relocation::section), - "" RST_CLASS_REF(lief.MachO.Section) " associated with the relocation if any, or None", - py::return_value_policy::reference) - - - .def_property_readonly("origin", - &Relocation::origin, - R"delim( - :class:`~lief.MachO.RELOCATION_ORIGINS` of the relocation - - * For :attr:`~lief.MachO.FILE_TYPES.OBJECT` file it should be :attr:`~lief.MachO.RELOCATION_ORIGINS.RELOC_TABLE` - * For :attr:`~lief.MachO.FILE_TYPES.EXECUTE` or :attr:`~lief.MachO.FILE_TYPES.DYLIB` it should be :attr:`~lief.MachO.RELOCATION_ORIGINS.DYLDINFO`") - )delim") - - .def_property_readonly("has_segment", - &Relocation::has_segment, - "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with") - - .def_property_readonly("segment", - static_cast(&Relocation::segment), - "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the relocation if any, or None", - py::return_value_policy::reference) - - .def("__eq__", &Relocation::operator==) - .def("__ne__", &Relocation::operator!=) - .def("__hash__", - [] (const Relocation& relocation) { - return Hash::hash(relocation); - }) - - - .def("__str__", - [] (const Relocation& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyRelocationDyld.cpp b/vendor/lief/api/python/MachO/objects/pyRelocationDyld.cpp deleted file mode 100644 index 0057b6a..0000000 --- a/vendor/lief/api/python/MachO/objects/pyRelocationDyld.cpp +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/RelocationDyld.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (RelocationDyld::*)(void) const; - -template -using setter_t = void (RelocationDyld::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "RelocationDyld", - R"delim( - Class that represents a relocation found in the :class:`~lief.MachO.DyldInfo` structure. - - While this class does not have an associated structure in the Mach-O format specification, - it provides a convenient interface for the :attr:`lief.MachO.DyldInfo.rebase` values - - See also: :class:`~lief.MachO.RelocationObject` - )delim") - - .def("__le__", &RelocationDyld::operator<=) - .def("__lt__", &RelocationDyld::operator<) - .def("__ge__", &RelocationDyld::operator>=) - .def("__gt__", &RelocationDyld::operator>) - .def("__eq__", &RelocationDyld::operator==) - .def("__ne__", &RelocationDyld::operator!=) - .def("__hash__", - [] (const RelocationDyld& relocation) { - return Hash::hash(relocation); - }) - - .def("__str__", - [] (const RelocationDyld& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyRelocationFixup.cpp b/vendor/lief/api/python/MachO/objects/pyRelocationFixup.cpp deleted file mode 100644 index 0b48544..0000000 --- a/vendor/lief/api/python/MachO/objects/pyRelocationFixup.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/RelocationFixup.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (RelocationFixup::*)() const; - -template -using setter_t = void (RelocationFixup::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "RelocationFixup", - R"delim( - Class that represents a rebase relocation found in the LC_DYLD_CHAINED_FIXUPS command. - - This class extends :class:`lief.Relocation` (and :class:`lief.MachO.Relocation`) in which - :attr:`~lief.Relocation.address` is set to the absolute virtual address - where the relocation must take place (e.g. `0x10000d270`). - - On the other hand, :attr:`~lief.MachO.RelocationFixup.target` contains the value - that should be set at :attr:`~lief.Relocation.address` if the - imagebase is :attr:`~lief.Binary.imagebase` (e.g. `0x1000073a8`). - - If the Mach-O loader chooses another base address (like 0x7ff100000), it must set - `0x10000d270` to `0x7ff1073a8`. - )delim") - - .def_property("target", - py::overload_cast<>(&RelocationFixup::target, py::const_), - py::overload_cast(&RelocationFixup::target)) - - .def("__eq__", &RelocationFixup::operator==) - .def("__ne__", &RelocationFixup::operator!=) - .def("__hash__", - [] (const RelocationFixup& relocation) { - return Hash::hash(relocation); - }) - - .def("__str__", - [] (const RelocationFixup& relocation) { - std::ostringstream stream; - std::string str = stream.str(); - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyRelocationObject.cpp b/vendor/lief/api/python/MachO/objects/pyRelocationObject.cpp deleted file mode 100644 index 7c8d4e8..0000000 --- a/vendor/lief/api/python/MachO/objects/pyRelocationObject.cpp +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/RelocationObject.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (RelocationObject::*)(void) const; - -template -using setter_t = void (RelocationObject::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "RelocationObject", - R"delim( - Class that represents a relocation presents in the MachO object - file (``.o``). Usually, this kind of relocation is found in the :class:`lief.MachO.Section`. - )delim") - - .def_property("value", - static_cast>(&RelocationObject::value), - static_cast>(&RelocationObject::value), - R"delim( - For **scattered** relocations, the address of the relocatable expression - for the item in the file that needs to be updated if the address is changed. - - For relocatable expressions with the difference of two section addresses, - the address from which to subtract (in mathematical terms, the minuend) - is contained in the first relocation entry and the address to subtract (the subtrahend) - is contained in the second relocation entry.", - )delim") - - - .def_property_readonly("is_scattered", - &RelocationObject::is_scattered, - "``True`` if the relocation is a scattered one") - - .def("__eq__", &RelocationObject::operator==) - .def("__ne__", &RelocationObject::operator!=) - .def("__hash__", - [] (const RelocationObject& relocation) { - return Hash::hash(relocation); - }) - - - .def("__str__", - [] (const RelocationObject& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pySection.cpp b/vendor/lief/api/python/MachO/objects/pySection.cpp deleted file mode 100644 index 1561dbb..0000000 --- a/vendor/lief/api/python/MachO/objects/pySection.cpp +++ /dev/null @@ -1,181 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/Section.hpp" -#include "LIEF/MachO/Relocation.hpp" -#include "LIEF/MachO/SegmentCommand.hpp" - -#include "pyMachO.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (Section::*)(void) const; - -template -using setter_t = void (Section::*)(T); - -template -using no_const_getter = T (Section::*)(void); - - -template<> -void create
(py::module& m) { - - py::class_ sec(m, "Section", - "Class that represents a Mach-O section"); - try { - /* - * it_relocations could be already registered by the SegmentCommand - */ - init_ref_iterator(sec, "it_relocations"); - } catch (const std::runtime_error&) { } - - sec - .def(py::init<>()) - - .def(py::init(), - "Constructor from a section's name", - "section_name"_a) - - .def(py::init(), - "Constructor from a section's name and its content", - "section_name"_a, "content"_a) - - .def_property("alignment", - static_cast>(&Section::alignment), - static_cast>(&Section::alignment), - "Section's alignment as a power of 2") - - .def_property("relocation_offset", - static_cast>(&Section::relocation_offset), - static_cast>(&Section::relocation_offset), - R"delim( - Offset of the relocation table. This value should be 0 - for executable and libraries as the relocations are managed by the :attr:`lief.MachO.DyldInfo.rebase` - - Other the other hand, for object files (``.o``) this value should not be 0 - )delim") - - .def_property("numberof_relocations", - static_cast>(&Section::numberof_relocations), - static_cast>(&Section::numberof_relocations), - "Number of relocations associated with this section") - - .def_property("type", - static_cast>(&Section::type), - static_cast>(&Section::type), - R"delim( - Type of the section. This value can help to determine - the purpose of the section (c.f. :class:`~lief.MachO.MACHO_SECTION_TYPES`) - )delim") - - .def_property_readonly("relocations", - static_cast>(&Section::relocations), - "Iterator over the " RST_CLASS_REF(lief.MachO.Relocation) " (if any)", - py::return_value_policy::reference_internal) - - .def_property("reserved1", - static_cast>(&Section::reserved1), - static_cast>(&Section::reserved1), - "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*") - - .def_property("reserved2", - static_cast>(&Section::reserved2), - static_cast>(&Section::reserved2), - "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*") - - .def_property("reserved3", - static_cast>(&Section::reserved3), - static_cast>(&Section::reserved3), - "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*") - - .def_property("flags", - static_cast>(&Section::flags), - static_cast>(&Section::flags), - "Section's flags masked with SECTION_FLAGS_MASK (see: :class:`~lief.MachO.MACHO_SECTION_FLAGS`)") - - .def_property_readonly("flags_list", - static_cast>(&Section::flags_list), - py::return_value_policy::reference_internal) - - .def_property_readonly("segment", - static_cast(&Section::segment), - "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the section or None if not present", - py::return_value_policy::reference) - - .def_property("segment_name", - static_cast>(&Section::segment_name), - static_cast>(&Section::segment_name), - R"delim( - The segment name associated with the section - )delim") - - .def_property_readonly("has_segment", - &Section::has_segment, - "True if the current section has a segment associated with") - - .def("has", - static_cast(&Section::has), - "Check if the section has the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) "", - "flag"_a) - - .def("add", - static_cast(&Section::add), - "Add the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) "", - "flag"_a) - - .def("remove", - static_cast(&Section::remove), - "Remove the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) "", - "flag"_a) - - .def(py::self += MACHO_SECTION_FLAGS()) - .def(py::self -= MACHO_SECTION_FLAGS()) - - .def("__contains__", - static_cast(&Section::has), - "Check if the given " RST_CLASS_REF(lief.MachO.MACHO_SECTION_FLAGS) " is present") - - - - .def("__eq__", &Section::operator==) - .def("__ne__", &Section::operator!=) - .def("__hash__", - [] (const Section& section) { - return Hash::hash(section); - }) - - - .def("__str__", - [] (const Section& section) - { - std::ostringstream stream; - stream << section; - std::string str = stream.str(); - return str; - }); - -} - -} -} - diff --git a/vendor/lief/api/python/MachO/objects/pySegmentCommand.cpp b/vendor/lief/api/python/MachO/objects/pySegmentCommand.cpp deleted file mode 100644 index 42ed1cf..0000000 --- a/vendor/lief/api/python/MachO/objects/pySegmentCommand.cpp +++ /dev/null @@ -1,173 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyMachO.hpp" -#include "pyIterators.hpp" - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/SegmentCommand.hpp" -#include "LIEF/MachO/Section.hpp" - -#include -#include - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (SegmentCommand::*)(void) const; - -template -using setter_t = void (SegmentCommand::*)(T); - -template -using no_const_getter = T (SegmentCommand::*)(void); - - -template<> -void create(py::module& m) { - - py::class_ seg_cmd(m, "SegmentCommand", - R"delim( - Class which represents a LOAD_COMMAND_TYPES::LC_SEGMENT / LOAD_COMMAND_TYPES::LC_SEGMENT_64 command - )delim"); - - init_ref_iterator(seg_cmd, "it_sections"); - - try { - /* - * it_relocations could be already registered by the Section - */ - init_ref_iterator(seg_cmd, "it_relocations"); - } catch (const std::runtime_error&) { } - - seg_cmd - .def(py::init<>()) - .def(py::init()) - .def(py::init()) - - .def_property("name", - [] (const SegmentCommand& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&SegmentCommand::name), - "Segment's name") - - .def_property("virtual_address", - static_cast>(&SegmentCommand::virtual_address), - static_cast>(&SegmentCommand::virtual_address), - "Segment's virtual address") - - .def_property("virtual_size", - static_cast>(&SegmentCommand::virtual_size), - static_cast>(&SegmentCommand::virtual_size), - "Segment's virtual size") - - .def_property("file_size", - static_cast>(&SegmentCommand::file_size), - static_cast>(&SegmentCommand::file_size), - "Segment's file size") - - .def_property("file_offset", - static_cast>(&SegmentCommand::file_offset), - static_cast>(&SegmentCommand::file_offset), - "Segment's file offset") - - .def_property("max_protection", - static_cast>(&SegmentCommand::max_protection), - static_cast>(&SegmentCommand::max_protection), - "Segment's max protection") - - .def_property("init_protection", - static_cast>(&SegmentCommand::init_protection), - static_cast>(&SegmentCommand::init_protection), - "Segment's initial protection") - - .def_property("numberof_sections", - static_cast>(&SegmentCommand::numberof_sections), - static_cast>(&SegmentCommand::numberof_sections), - "Number of sections in this segment") - - .def_property_readonly("sections", - static_cast>(&SegmentCommand::sections), - "Segment's sections") - - .def_property_readonly("relocations", - static_cast>(&SegmentCommand::relocations), - "Segment's relocations") - - .def_property_readonly("index", &SegmentCommand::index, - "Relative index of the segment in the segment table") - - .def_property("content", - [] (const SegmentCommand& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, - static_cast>(&SegmentCommand::content), - "Segment's content") - - .def_property("flags", - static_cast>(&SegmentCommand::flags), - static_cast>(&SegmentCommand::flags), - "Segment's flags") - - .def("has", - static_cast(&SegmentCommand::has), - "Check if the given " RST_CLASS_REF(lief.MachO.Section) " belongs to the current segment", - "section"_a) - - .def("has_section", - static_cast(&SegmentCommand::has_section), - "Check if the given section name belongs to the current segment", - "section_name"_a) - - .def("add_section", - static_cast(&SegmentCommand::add_section), - "", - "section"_a, - py::return_value_policy::reference) - - .def("get_section", - py::overload_cast(&SegmentCommand::get_section), - R"delim( - Get the :class:`~lief.MachO.Section` with the given name - )delim", - "name"_a, - py::return_value_policy::reference_internal) - - .def("__eq__", &SegmentCommand::operator==) - .def("__ne__", &SegmentCommand::operator!=) - .def("__hash__", - [] (const SegmentCommand& segment_command) { - return Hash::hash(segment_command); - }) - - - .def("__str__", - [] (const SegmentCommand& segment) - { - std::ostringstream stream; - stream << segment; - std::string str = stream.str(); - return str; - }); - -} - -} -} - - diff --git a/vendor/lief/api/python/MachO/objects/pySegmentSplitInfo.cpp b/vendor/lief/api/python/MachO/objects/pySegmentSplitInfo.cpp deleted file mode 100644 index 0567ecf..0000000 --- a/vendor/lief/api/python/MachO/objects/pySegmentSplitInfo.cpp +++ /dev/null @@ -1,77 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/SegmentSplitInfo.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (SegmentSplitInfo::*)(void) const; - -template -using setter_t = void (SegmentSplitInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "SegmentSplitInfo", - "Class that represents the LOAD_COMMAND_TYPES::LC_SEGMENT_SPLIT_INFO command") - - .def_property("data_offset", - static_cast>(&SegmentSplitInfo::data_offset), - static_cast>(&SegmentSplitInfo::data_offset), - "Offset in the binary where the data start") - - .def_property("data_size", - static_cast>(&SegmentSplitInfo::data_size), - static_cast>(&SegmentSplitInfo::data_size), - "Size of the raw data") - - .def_property_readonly("content", - [] (const SegmentSplitInfo& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The original content as a bytes stream") - - .def("__eq__", &SegmentSplitInfo::operator==) - .def("__ne__", &SegmentSplitInfo::operator!=) - .def("__hash__", - [] (const SegmentSplitInfo& func) { - return Hash::hash(func); - }) - - - .def("__str__", - [] (const SegmentSplitInfo& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pySourceVersion.cpp b/vendor/lief/api/python/MachO/objects/pySourceVersion.cpp deleted file mode 100644 index 16b6187..0000000 --- a/vendor/lief/api/python/MachO/objects/pySourceVersion.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/SourceVersion.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (SourceVersion::*)(void) const; - -template -using setter_t = void (SourceVersion::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "SourceVersion", - R"delim( - Class that represents the MachO LOAD_COMMAND_TYPES::LC_SOURCE_VERSION - This command is used to provide the *version* of the sources used to build the binary - )delim") - - .def_property("version", - static_cast>(&SourceVersion::version), - static_cast>(&SourceVersion::version), - "Version as a tuple of **5** integers", - py::return_value_policy::reference_internal) - - - .def("__eq__", &SourceVersion::operator==) - .def("__ne__", &SourceVersion::operator!=) - .def("__hash__", - [] (const SourceVersion& version) { - return Hash::hash(version); - }) - - - .def("__str__", - [] (const SourceVersion& version) - { - std::ostringstream stream; - stream << version; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pySubFramework.cpp b/vendor/lief/api/python/MachO/objects/pySubFramework.cpp deleted file mode 100644 index f836a63..0000000 --- a/vendor/lief/api/python/MachO/objects/pySubFramework.cpp +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/SubFramework.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (SubFramework::*)(void) const; - -template -using setter_t = void (SubFramework::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "SubFramework", - R"delim( - Class that represents the SubFramework command. - Accodring to the Mach-O ``loader.h`` documentation: - - - > A dynamically linked shared library may be a subframework of an umbrella - > framework. If so it will be linked with "-umbrella umbrella_name" where - > Where "umbrella_name" is the name of the umbrella framework. A subframework - > can only be linked against by its umbrella framework or other subframeworks - > that are part of the same umbrella framework. Otherwise the static link - > editor produces an error and states to link against the umbrella framework. - > The name of the umbrella framework for subframeworks is recorded in the - > following structure. - )delim") - - .def_property("umbrella", - static_cast>(&SubFramework::umbrella), - static_cast>(&SubFramework::umbrella), - "Name of the umbrella framework") - - .def("__eq__", &SubFramework::operator==) - .def("__ne__", &SubFramework::operator!=) - .def("__hash__", - [] (const SubFramework& func) { - return Hash::hash(func); - }) - - - .def("__str__", - [] (const SubFramework& func) - { - std::ostringstream stream; - stream << func; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pySymbol.cpp b/vendor/lief/api/python/MachO/objects/pySymbol.cpp deleted file mode 100644 index d3df007..0000000 --- a/vendor/lief/api/python/MachO/objects/pySymbol.cpp +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/Section.hpp" -#include "LIEF/MachO/Symbol.hpp" - -#include "pyIterators.hpp" -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (Symbol::*)(void) const; - -template -using setter_t = void (Symbol::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ symbol(m, "Symbol", - R"delim( - Class that represents a Symbol in a Mach-O file. - - A Mach-O symbol can come from: - - 1. The symbols command (LC_SYMTAB / SymbolCommand) - 2. The Dyld Export trie - 3. The Dyld Symbol bindings - )delim"); - - py::enum_(symbol, "TOOLS") - .value("NONE", Symbol::CATEGORY::NONE) - .value("LOCAL", Symbol::CATEGORY::LOCAL) - .value("EXTERNAL", Symbol::CATEGORY::EXTERNAL) - .value("UNDEFINED", Symbol::CATEGORY::UNDEFINED) - .value("INDIRECT_ABS", Symbol::CATEGORY::INDIRECT_ABS) - .value("INDIRECT_LOCAL", Symbol::CATEGORY::INDIRECT_LOCAL); - - symbol - .def(py::init<>()) - - .def_property_readonly("demangled_name", - &Symbol::demangled_name, - "Symbol's unmangled name") - - .def_property("type", - static_cast>(&Symbol::type), - static_cast>(&Symbol::type)) - - .def_property("numberof_sections", - static_cast>(&Symbol::numberof_sections), - static_cast>(&Symbol::numberof_sections), - R"delim( - It returns the number of sections in which this symbol can be found. - If the symbol can't be found in any section, it returns 0 (NO_SECT) - )delim") - - .def_property("description", - static_cast>(&Symbol::description), - static_cast>(&Symbol::description), - "Return information about the symbol (:class:`~lief.MachO.SYMBOL_DESCRIPTIONS`)") - - .def_property_readonly("has_export_info", - &Symbol::has_export_info, - "``True`` if the symbol has an " RST_CLASS_REF(lief.MachO.ExportInfo) " associated with") - - .def_property_readonly("origin", - &Symbol::origin, - "Return the " RST_CLASS_REF(lief.MachO.SYMBOL_ORIGINS) " of this symbol") - - .def_property_readonly("export_info", - static_cast(&Symbol::export_info), - "" RST_CLASS_REF(lief.MachO.ExportInfo) " associated with the symbol if any, or None", - py::return_value_policy::reference) - - .def_property_readonly("has_binding_info", - &Symbol::has_binding_info, - "``True`` if the symbol has an " RST_CLASS_REF(lief.MachO.BindingInfo) " associated with") - - .def_property_readonly("binding_info", - static_cast(&Symbol::binding_info), - "" RST_CLASS_REF(lief.MachO.BindingInfo) " associated with the symbol if any, or None", - py::return_value_policy::reference) - - .def("__eq__", &Symbol::operator==) - .def("__ne__", &Symbol::operator!=) - .def("__hash__", - [] (const Symbol& symbol) { - return Hash::hash(symbol); - }) - - - .def("__str__", - [] (const Symbol& symbol) { - std::ostringstream stream; - stream << symbol; - std::string str = stream.str(); - return str; - }); - -} - -} -} - - - diff --git a/vendor/lief/api/python/MachO/objects/pySymbolCommand.cpp b/vendor/lief/api/python/MachO/objects/pySymbolCommand.cpp deleted file mode 100644 index 4656840..0000000 --- a/vendor/lief/api/python/MachO/objects/pySymbolCommand.cpp +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/SymbolCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (SymbolCommand::*)(void) const; - -template -using setter_t = void (SymbolCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "SymbolCommand", - R"delim( - Class that represents the LC_SYMTAB command - )delim") - .def(py::init<>()) - - .def_property("symbol_offset", - static_cast>(&SymbolCommand::symbol_offset), - static_cast>(&SymbolCommand::symbol_offset), - "Offset from the start of the file to the n_list associated with the command") - - .def_property("numberof_symbols", - static_cast>(&SymbolCommand::numberof_symbols), - static_cast>(&SymbolCommand::numberof_symbols), - "Number of symbols registered") - - .def_property("strings_offset", - static_cast>(&SymbolCommand::strings_offset), - static_cast>(&SymbolCommand::strings_offset), - "Offset from the start of the file to the string table") - - .def_property("strings_size", - static_cast>(&SymbolCommand::strings_size), - static_cast>(&SymbolCommand::strings_size), - "Size of the size string table") - - - .def("__eq__", &SymbolCommand::operator==) - .def("__ne__", &SymbolCommand::operator!=) - .def("__hash__", - [] (const SymbolCommand& symbolcmd) { - return Hash::hash(symbolcmd); - }) - - .def("__str__", - [] (const SymbolCommand& symbolcmd) - { - std::ostringstream stream; - stream << symbolcmd; - std::string str = stream.str(); - return str; - }); - -} - -} -} - - diff --git a/vendor/lief/api/python/MachO/objects/pyThreadCommand.cpp b/vendor/lief/api/python/MachO/objects/pyThreadCommand.cpp deleted file mode 100644 index 3a49575..0000000 --- a/vendor/lief/api/python/MachO/objects/pyThreadCommand.cpp +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/ThreadCommand.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (ThreadCommand::*)(void) const; - -template -using setter_t = void (ThreadCommand::*)(T); - - - -template<> -void create(py::module& m) { - - py::class_(m, "ThreadCommand", - R"delim( - Class that represents the LC_THREAD / LC_UNIXTHREAD commands and that - can be used to get the binary entrypoint when the LC_MAIN (MainCommand) is not present - - Generally speaking, this command aims at defining the original state - of the main thread which includes the registers' values - )delim") - - .def_property("flavor", - static_cast>(&ThreadCommand::flavor), - static_cast>(&ThreadCommand::flavor), - R"delim( - Integer that defines a special *flavor* for the thread. - - The meaning of this value depends on the :attr:`~lief.MachO.ThreadCommand.architecture`. - The list of the values can be found in the XNU kernel files: - - - xnu/osfmk/mach/arm/thread_status.h for the ARM/AArch64 architectures - - xnu/osfmk/mach/i386/thread_status.h for the x86/x86-64 architectures - )delim") - - - .def_property("state", - static_cast&>>(&ThreadCommand::state), - static_cast&>>(&ThreadCommand::state), - R"delim( - The actual thread state as a vector of bytes. Depending on the architecture(), - these data can be casted into x86_thread_state_t, x86_thread_state64_t, ... - )delim") - - - .def_property("count", - static_cast>(&ThreadCommand::count), - static_cast>(&ThreadCommand::count), - R"delim( - Size of the thread state data with 32-bits alignment. - - This value should match len(:attr:`~lief.MachO.ThreadCommand.state`) - )delim") - - .def_property_readonly("pc", - static_cast>(&ThreadCommand::pc), - R"delim( - Return the initial Program Counter regardless of the underlying architecture. - This value, when non null, can be used to determine the binary's entrypoint. - - Underneath, it works by looking for the PC register value in the :attr:`~lief.MachO.ThreadCommand.state` data - )delim") - - .def_property("architecture", - static_cast>(&ThreadCommand::architecture), - static_cast>(&ThreadCommand::architecture), - "The CPU architecture that is targeted by this ThreadCommand") - - .def("__eq__", &ThreadCommand::operator==) - .def("__ne__", &ThreadCommand::operator!=) - .def("__hash__", - [] (const ThreadCommand& thread) { - return LIEF::Hash::hash(thread); - }) - - - .def("__str__", - [] (const ThreadCommand& thread) - { - std::ostringstream stream; - stream << thread; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyTwoLevelHints.cpp b/vendor/lief/api/python/MachO/objects/pyTwoLevelHints.cpp deleted file mode 100644 index 368acb0..0000000 --- a/vendor/lief/api/python/MachO/objects/pyTwoLevelHints.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/TwoLevelHints.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template<> -void create(py::module& m) { - - py::class_ cmd(m, "TwoLevelHints", - R"delim( - Class which represents the `LC_TWOLEVEL_HINTS` command - )delim"); - - cmd - .def_property_readonly("hints", - py::overload_cast<>(&TwoLevelHints::hints)) - .def_property_readonly("content", - [] (const TwoLevelHints& self) { - span content = self.content(); - return py::memoryview::from_memory(content.data(), content.size()); - }, "The original content as a bytes stream") - - .def("__eq__", &TwoLevelHints::operator==) - .def("__ne__", &TwoLevelHints::operator!=) - .def("__hash__", - [] (const TwoLevelHints& two) { - return Hash::hash(two); - }) - - .def("__str__", - [] (const TwoLevelHints& two) { - std::ostringstream stream; - stream << two; - return stream.str(); - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyUUID.cpp b/vendor/lief/api/python/MachO/objects/pyUUID.cpp deleted file mode 100644 index ebfec67..0000000 --- a/vendor/lief/api/python/MachO/objects/pyUUID.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/UUIDCommand.hpp" - -#include "pyMachO.hpp" - -#ifdef uuid_t -#pragma message("Windows #define uuid_t, undefine it for this file.") -#undef uuid_t -#endif - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (UUIDCommand::*)(void) const; - -template -using setter_t = void (UUIDCommand::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "UUIDCommand", - "Class that represents the UUID command") - - .def_property("uuid", - static_cast>(&UUIDCommand::uuid), - static_cast>(&UUIDCommand::uuid), - "UUID as a list", - py::return_value_policy::reference_internal) - - - .def("__eq__", &UUIDCommand::operator==) - .def("__ne__", &UUIDCommand::operator!=) - .def("__hash__", - [] (const UUIDCommand& uuid) { - return Hash::hash(uuid); - }) - - - .def("__str__", - [] (const UUIDCommand& uuid) - { - std::ostringstream stream; - stream << uuid; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/MachO/objects/pyVersionMin.cpp b/vendor/lief/api/python/MachO/objects/pyVersionMin.cpp deleted file mode 100644 index 6644eb5..0000000 --- a/vendor/lief/api/python/MachO/objects/pyVersionMin.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include -#include - -#include "LIEF/MachO/hash.hpp" -#include "LIEF/MachO/VersionMin.hpp" - -#include "pyMachO.hpp" - -namespace LIEF { -namespace MachO { - -template -using getter_t = T (VersionMin::*)(void) const; - -template -using setter_t = void (VersionMin::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "VersionMin", - "Class that wraps the LC_VERSION_MIN_MACOSX, LC_VERSION_MIN_IPHONEOS, ... commands") - - .def_property("version", - static_cast>(&VersionMin::version), - static_cast>(&VersionMin::version), - "Version as a tuple of **3** integers", - py::return_value_policy::reference_internal) - - - .def_property("sdk", - static_cast>(&VersionMin::sdk), - static_cast>(&VersionMin::sdk), - "SDK as a tuple of **3** integers", - py::return_value_policy::reference_internal) - - - .def("__eq__", &VersionMin::operator==) - .def("__ne__", &VersionMin::operator!=) - .def("__hash__", - [] (const VersionMin& version) { - return Hash::hash(version); - }) - - - .def("__str__", - [] (const VersionMin& version) - { - std::ostringstream stream; - stream << version; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/MachO/pyEnums.cpp b/vendor/lief/api/python/MachO/pyEnums.cpp deleted file mode 100644 index 9af1da5..0000000 --- a/vendor/lief/api/python/MachO/pyEnums.cpp +++ /dev/null @@ -1,354 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyMachO.hpp" -#include "LIEF/MachO/enums.hpp" -#include "LIEF/MachO/EnumToString.hpp" -#include "enums_wrapper.hpp" - -#define PY_ENUM(x) LIEF::MachO::to_string(x), x - -namespace LIEF { -namespace MachO { - -void init_enums(py::module& m) { - - LIEF::enum_(m, "CPU_TYPES") - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_ANY)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_X86)) - .value("I386", LIEF::MachO::CPU_TYPES::CPU_TYPE_I386) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_X86_64)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_MC98000)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_ARM)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_ARM64)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_SPARC)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_POWERPC)) - .value(PY_ENUM(LIEF::MachO::CPU_TYPES::CPU_TYPE_POWERPC64)); - - LIEF::enum_(m, "MACHO_TYPES") - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::MH_MAGIC)) - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::MH_CIGAM)) - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::MH_MAGIC_64)) - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::MH_CIGAM_64)) - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::FAT_MAGIC)) - .value(PY_ENUM(LIEF::MachO::MACHO_TYPES::FAT_CIGAM)); - - - LIEF::enum_(m, "FILE_TYPES") - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_OBJECT)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_EXECUTE)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_FVMLIB)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_CORE)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_PRELOAD)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_DYLIB)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_DYLINKER)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_BUNDLE)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_DYLIB_STUB)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_DSYM)) - .value(PY_ENUM(LIEF::MachO::FILE_TYPES::MH_KEXT_BUNDLE)); - - LIEF::enum_(m, "HEADER_FLAGS") - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_NOUNDEFS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_INCRLINK)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_DYLDLINK)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_BINDATLOAD)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_PREBOUND)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_SPLIT_SEGS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_LAZY_INIT)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_TWOLEVEL)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_FORCE_FLAT)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_NOMULTIDEFS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_NOFIXPREBINDING)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_PREBINDABLE)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_ALLMODSBOUND)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_SUBSECTIONS_VIA_SYMBOLS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_CANONICAL)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_WEAK_DEFINES)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_BINDS_TO_WEAK)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_ALLOW_STACK_EXECUTION)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_ROOT_SAFE)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_SETUID_SAFE)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_NO_REEXPORTED_DYLIBS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_PIE)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_DEAD_STRIPPABLE_DYLIB)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_HAS_TLV_DESCRIPTORS)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_NO_HEAP_EXECUTION)) - .value(PY_ENUM(LIEF::MachO::HEADER_FLAGS::MH_APP_EXTENSION_SAFE)); - - - - LIEF::enum_(m, "LOAD_COMMAND_TYPES") - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SEGMENT)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SYMTAB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SYMSEG)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_THREAD)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_UNIXTHREAD)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LOADFVMLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_IDFVMLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_IDENT)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_FVMFILE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_PREPAGE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYSYMTAB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LOAD_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ID_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LOAD_DYLINKER)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ID_DYLINKER)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_PREBOUND_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ROUTINES)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SUB_FRAMEWORK)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SUB_UMBRELLA)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SUB_CLIENT)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SUB_LIBRARY)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_TWOLEVEL_HINTS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_PREBIND_CKSUM)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LOAD_WEAK_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SEGMENT_64)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ROUTINES_64)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_UUID)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_RPATH)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_CODE_SIGNATURE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SEGMENT_SPLIT_INFO)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_REEXPORT_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LAZY_LOAD_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ENCRYPTION_INFO)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLD_INFO)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLD_INFO_ONLY)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LOAD_UPWARD_DYLIB)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_VERSION_MIN_MACOSX)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_VERSION_MIN_IPHONEOS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_FUNCTION_STARTS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLD_ENVIRONMENT)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_MAIN)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DATA_IN_CODE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_SOURCE_VERSION)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLIB_CODE_SIGN_DRS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_ENCRYPTION_INFO_64)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LINKER_OPTION)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_LINKER_OPTIMIZATION_HINT)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_VERSION_MIN_TVOS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_VERSION_MIN_WATCHOS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_NOTE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_BUILD_VERSION)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLD_EXPORTS_TRIE)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_DYLD_CHAINED_FIXUPS)) - .value(PY_ENUM(LIEF::MachO::LOAD_COMMAND_TYPES::LC_FILESET_ENTRY)); - - - LIEF::enum_(m, "SECTION_TYPES") - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_REGULAR)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_ZEROFILL)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_CSTRING_LITERALS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_4BYTE_LITERALS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_8BYTE_LITERALS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_LITERAL_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_NON_LAZY_SYMBOL_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_LAZY_SYMBOL_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_SYMBOL_STUBS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_MOD_INIT_FUNC_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_MOD_TERM_FUNC_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_COALESCED)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_GB_ZEROFILL)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_INTERPOSING)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_16BYTE_LITERALS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_DTRACE_DOF)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_LAZY_DYLIB_SYMBOL_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_THREAD_LOCAL_REGULAR)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_THREAD_LOCAL_ZEROFILL)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_THREAD_LOCAL_VARIABLES)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_THREAD_LOCAL_VARIABLE_POINTERS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_TYPES::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS)); - - - LIEF::enum_(m, "X86_RELOCATION") - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_VANILLA)) - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_PAIR)) - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_PB_LA_PTR)) - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_LOCAL_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::X86_RELOCATION::GENERIC_RELOC_TLV)); - - LIEF::enum_(m, "X86_64_RELOCATION") - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_UNSIGNED)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_SIGNED)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_BRANCH)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_GOT_LOAD)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_GOT)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_SUBTRACTOR)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_SIGNED_1)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_SIGNED_2)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_SIGNED_4)) - .value(PY_ENUM(LIEF::MachO::X86_64_RELOCATION::X86_64_RELOC_TLV)); - - LIEF::enum_(m, "PPC_RELOCATION") - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_VANILLA)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_PAIR)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_BR14)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_BR24)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_HI16)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_LO16)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_HA16)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_LO14)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_PB_LA_PTR)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_HI16_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_LO16_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_HA16_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_JBSR)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_LO14_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::PPC_RELOCATION::PPC_RELOC_LOCAL_SECTDIFF)); - - LIEF::enum_(m, "ARM_RELOCATION") - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_VANILLA)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_PAIR)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_LOCAL_SECTDIFF)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_PB_LA_PTR)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_BR24)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_THUMB_RELOC_BR22)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_THUMB_32BIT_BRANCH)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_HALF)) - .value(PY_ENUM(LIEF::MachO::ARM_RELOCATION::ARM_RELOC_HALF_SECTDIFF)); - - LIEF::enum_(m, "ARM64_RELOCATION") - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_UNSIGNED)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_SUBTRACTOR)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_BRANCH26)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_PAGE21)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_PAGEOFF12)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_GOT_LOAD_PAGE21)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_GOT_LOAD_PAGEOFF12)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_POINTER_TO_GOT)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_TLVP_LOAD_PAGE21)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_TLVP_LOAD_PAGEOFF12)) - .value(PY_ENUM(LIEF::MachO::ARM64_RELOCATION::ARM64_RELOC_ADDEND)); - - - LIEF::enum_(m, "RELOCATION_ORIGINS") - .value(PY_ENUM(LIEF::MachO::RELOCATION_ORIGINS::ORIGIN_UNKNOWN)) - .value(PY_ENUM(LIEF::MachO::RELOCATION_ORIGINS::ORIGIN_DYLDINFO)) - .value(PY_ENUM(LIEF::MachO::RELOCATION_ORIGINS::ORIGIN_RELOC_TABLE)) - .value(PY_ENUM(LIEF::MachO::RELOCATION_ORIGINS::ORIGIN_CHAINED_FIXUPS)); - - - LIEF::enum_(m, "REBASE_TYPES") - .value(PY_ENUM(LIEF::MachO::REBASE_TYPES::REBASE_TYPE_POINTER)) - .value(PY_ENUM(LIEF::MachO::REBASE_TYPES::REBASE_TYPE_TEXT_ABSOLUTE32)) - .value(PY_ENUM(LIEF::MachO::REBASE_TYPES::REBASE_TYPE_TEXT_PCREL32)); - - - LIEF::enum_(m, "BINDING_CLASS") - .value(PY_ENUM(LIEF::MachO::BINDING_CLASS::BIND_CLASS_WEAK)) - .value(PY_ENUM(LIEF::MachO::BINDING_CLASS::BIND_CLASS_LAZY)) - .value(PY_ENUM(LIEF::MachO::BINDING_CLASS::BIND_CLASS_STANDARD)) - .value(PY_ENUM(LIEF::MachO::BINDING_CLASS::BIND_CLASS_THREADED)); - - - LIEF::enum_(m, "REBASE_OPCODES") - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_DONE)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_SET_TYPE_IMM)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_ADD_ADDR_ULEB)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_ADD_ADDR_IMM_SCALED)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_DO_REBASE_IMM_TIMES)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_DO_REBASE_ULEB_TIMES)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB)) - .value(PY_ENUM(LIEF::MachO::REBASE_OPCODES::REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB)); - - - LIEF::enum_(m, "BIND_TYPES") - .value(PY_ENUM(LIEF::MachO::BIND_TYPES::BIND_TYPE_POINTER)) - .value(PY_ENUM(LIEF::MachO::BIND_TYPES::BIND_TYPE_TEXT_ABSOLUTE32)) - .value(PY_ENUM(LIEF::MachO::BIND_TYPES::BIND_TYPE_TEXT_PCREL32)); - - - LIEF::enum_(m, "BIND_SPECIAL_DYLIB") - .value(PY_ENUM(LIEF::MachO::BIND_SPECIAL_DYLIB::BIND_SPECIAL_DYLIB_SELF)) - .value(PY_ENUM(LIEF::MachO::BIND_SPECIAL_DYLIB::BIND_SPECIAL_DYLIB_MAIN_EXECUTABLE)) - .value(PY_ENUM(LIEF::MachO::BIND_SPECIAL_DYLIB::BIND_SPECIAL_DYLIB_FLAT_LOOKUP)); - - - LIEF::enum_(m, "BIND_OPCODES") - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_DONE)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_DYLIB_ORDINAL_IMM)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_DYLIB_SPECIAL_IMM)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_TYPE_IMM)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_ADDEND_SLEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_ADD_ADDR_ULEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_DO_BIND)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_DO_BIND_ADD_ADDR_IMM_SCALED)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB)) - .value(PY_ENUM(LIEF::MachO::BIND_OPCODES::BIND_OPCODE_THREADED)); - - - LIEF::enum_(m, "EXPORT_SYMBOL_KINDS") - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_KINDS::EXPORT_SYMBOL_FLAGS_KIND_REGULAR)) - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_KINDS::EXPORT_SYMBOL_FLAGS_KIND_THREAD_LOCAL)) - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_KINDS::EXPORT_SYMBOL_FLAGS_KIND_ABSOLUTE)); - - py::enum_(m, "EXPORT_SYMBOL_FLAGS") - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_FLAGS::EXPORT_SYMBOL_FLAGS_WEAK_DEFINITION)) - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_FLAGS::EXPORT_SYMBOL_FLAGS_REEXPORT)) - .value(PY_ENUM(LIEF::MachO::EXPORT_SYMBOL_FLAGS::EXPORT_SYMBOL_FLAGS_STUB_AND_RESOLVER)); - - - LIEF::enum_(m, "VM_PROTECTIONS") - .value(PY_ENUM(LIEF::MachO::VM_PROTECTIONS::VM_PROT_READ)) - .value(PY_ENUM(LIEF::MachO::VM_PROTECTIONS::VM_PROT_WRITE)) - .value(PY_ENUM(LIEF::MachO::VM_PROTECTIONS::VM_PROT_EXECUTE)); - - - LIEF::enum_(m, "SYMBOL_ORIGINS") - .value(PY_ENUM(LIEF::MachO::SYMBOL_ORIGINS::SYM_ORIGIN_UNKNOWN)) - .value(PY_ENUM(LIEF::MachO::SYMBOL_ORIGINS::SYM_ORIGIN_DYLD_EXPORT)) - .value(PY_ENUM(LIEF::MachO::SYMBOL_ORIGINS::SYM_ORIGIN_LC_SYMTAB)); - - LIEF::enum_(m, "SECTION_FLAGS") - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_PURE_INSTRUCTIONS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_NO_TOC)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_STRIP_STATIC_SYMS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_NO_DEAD_STRIP)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_LIVE_SUPPORT)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_SELF_MODIFYING_CODE)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_DEBUG)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_SOME_INSTRUCTIONS)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_EXT_RELOC)) - .value(PY_ENUM(LIEF::MachO::MACHO_SECTION_FLAGS::S_ATTR_LOC_RELOC)); - - LIEF::enum_(m, "DYLD_CHAINED_FORMAT") - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_FORMAT::IMPORT)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_FORMAT::IMPORT_ADDEND)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_FORMAT::IMPORT_ADDEND64)); - - LIEF::enum_(m, "DYLD_CHAINED_PTR_FORMAT") - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_64)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_32)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_32_CACHE)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_32_FIRMWARE)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_64_OFFSET)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_KERNEL)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_64_KERNEL_CACHE)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_USERLAND)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_FIRMWARE)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_X86_64_KERNEL_CACHE)) - .value(PY_ENUM(LIEF::MachO::DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_USERLAND24)); -} - -} -} diff --git a/vendor/lief/api/python/MachO/pyMachO.cpp b/vendor/lief/api/python/MachO/pyMachO.cpp deleted file mode 100644 index 1d36eea..0000000 --- a/vendor/lief/api/python/MachO/pyMachO.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "pyMachO.hpp" - - -namespace LIEF { -namespace MachO { - -void init_python_module(py::module& m) { - py::module LIEF_MachO_module = m.def_submodule("MachO", "Python API for the MachO format"); - - init_enums(LIEF_MachO_module); - init_objects(LIEF_MachO_module); - init_utils(LIEF_MachO_module); -} - -void init_objects(py::module& m) { - - CREATE(ParserConfig, m); - CREATE(Parser, m); - - CREATE(FatBinary, m); - CREATE(Binary, m); - CREATE(Header, m); - CREATE(LoadCommand, m); - CREATE(UUIDCommand, m); - CREATE(SymbolCommand, m); - CREATE(SegmentCommand, m); - CREATE(Section, m); - CREATE(MainCommand, m); - CREATE(DynamicSymbolCommand, m); - CREATE(DylinkerCommand, m); - CREATE(DyldInfo, m); - CREATE(DyldChainedFixups, m); - CREATE(DyldExportsTrie, m); - CREATE(DylibCommand, m); - CREATE(ThreadCommand, m); - CREATE(RPathCommand, m); - CREATE(Symbol, m); - CREATE(Relocation, m); - CREATE(RelocationObject, m); - CREATE(RelocationDyld, m); - CREATE(RelocationFixup, m); - CREATE(BindingInfo, m); - CREATE(DyldBindingInfo, m); - CREATE(ExportInfo, m); - CREATE(FunctionStarts, m); - CREATE(CodeSignature, m); - CREATE(CodeSignatureDir, m); - CREATE(DataInCode, m); - CREATE(DataCodeEntry, m); - CREATE(SourceVersion, m); - CREATE(VersionMin, m); - CREATE(SegmentSplitInfo, m); - CREATE(SubFramework, m); - CREATE(DyldEnvironment, m); - CREATE(EncryptionInfo, m); - CREATE(BuildVersion, m); - CREATE(FilesetCommand, m); - CREATE(ChainedBindingInfo, m); - CREATE(TwoLevelHints, m); - CREATE(LinkerOptHint, m); - CREATE(Builder, m); -} - -} -} diff --git a/vendor/lief/api/python/MachO/pyMachO.hpp b/vendor/lief/api/python/MachO/pyMachO.hpp deleted file mode 100644 index 6358ca7..0000000 --- a/vendor/lief/api/python/MachO/pyMachO.hpp +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_MACHO_H_ -#define PY_LIEF_MACHO_H_ - -#include "LIEF/MachO/Parser.hpp" -#include "LIEF/MachO/Binary.hpp" -#include "LIEF/MachO/Builder.hpp" - -#include -#include - -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -namespace LIEF { -namespace MachO { - -template -void create(py::module&); - -void init_python_module(py::module& m); -void init_objects(py::module&); -void init_enums(py::module&); -void init_utils(py::module&); - - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(ParserConfig); - -SPECIALIZE_CREATE(Binary); -SPECIALIZE_CREATE(BindingInfo); -SPECIALIZE_CREATE(BuildVersion); -SPECIALIZE_CREATE(ChainedBindingInfo); -SPECIALIZE_CREATE(CodeSignature); -SPECIALIZE_CREATE(CodeSignatureDir); -SPECIALIZE_CREATE(DataCodeEntry); -SPECIALIZE_CREATE(DataInCode); -SPECIALIZE_CREATE(DyldBindingInfo); -SPECIALIZE_CREATE(DyldChainedFixups); -SPECIALIZE_CREATE(DyldEnvironment); -SPECIALIZE_CREATE(DyldExportsTrie); -SPECIALIZE_CREATE(DyldInfo); -SPECIALIZE_CREATE(DylibCommand); -SPECIALIZE_CREATE(DylinkerCommand); -SPECIALIZE_CREATE(DynamicSymbolCommand); -SPECIALIZE_CREATE(EncryptionInfo); -SPECIALIZE_CREATE(ExportInfo); -SPECIALIZE_CREATE(FatBinary); -SPECIALIZE_CREATE(FilesetCommand); -SPECIALIZE_CREATE(FunctionStarts); -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(LinkerOptHint); -SPECIALIZE_CREATE(LoadCommand); -SPECIALIZE_CREATE(MainCommand); -SPECIALIZE_CREATE(RPathCommand); -SPECIALIZE_CREATE(Relocation); -SPECIALIZE_CREATE(RelocationDyld); -SPECIALIZE_CREATE(RelocationFixup); -SPECIALIZE_CREATE(RelocationObject); -SPECIALIZE_CREATE(Section); -SPECIALIZE_CREATE(SegmentCommand); -SPECIALIZE_CREATE(SegmentSplitInfo); -SPECIALIZE_CREATE(SourceVersion); -SPECIALIZE_CREATE(SubFramework); -SPECIALIZE_CREATE(Symbol); -SPECIALIZE_CREATE(SymbolCommand); -SPECIALIZE_CREATE(ThreadCommand); -SPECIALIZE_CREATE(TwoLevelHints); -SPECIALIZE_CREATE(UUIDCommand); -SPECIALIZE_CREATE(VersionMin); -SPECIALIZE_CREATE(Builder); - -} -} - - -// Opaque containers -PYBIND11_MAKE_OPAQUE(std::vector) - - -#endif diff --git a/vendor/lief/api/python/MachO/pyUtils.cpp b/vendor/lief/api/python/MachO/pyUtils.cpp deleted file mode 100644 index d2124ad..0000000 --- a/vendor/lief/api/python/MachO/pyUtils.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyMachO.hpp" - -#include "LIEF/MachO/utils.hpp" -#include "LIEF/MachO/FatBinary.hpp" - -namespace LIEF { -namespace MachO { - -void init_utils(py::module& m) { - - m.def("is_macho", - static_cast(&is_macho), - "Check if the given file is a ``MachO`` (from filename)", - "filename"_a); - - - m.def("is_macho", - static_cast&)>(&is_macho), - "Check if the given raw data is a ``MachO``", - "raw"_a); - - m.def("is_fat", - &is_fat, - "Check if the given Mach-O is fat", - "file"_a); - - m.def("is_64", - &is_64, - "Check if the given Mach-O is 64-bits", - "file"_a); - - m.def("check_layout", - [] (const Binary& bin) { - std::string on_error; - bool is_valid = check_layout(bin, &on_error); - return std::pair{is_valid, on_error}; - }, - "Check the layout of the given Mach-O binary. It checks if it can be signed " - "according to ``cctools-921/libstuff/checkout.c``", - "file"_a); - - m.def("check_layout", - [] (const FatBinary& bin) { - std::string on_error; - bool is_valid = check_layout(bin, &on_error); - return std::pair{is_valid, on_error}; - }, - R"delim( - Check the layout of the given FAT Mach-O by checking individually the layout - of the binaries embedded in the FAT. - )delim", - "file"_a); - - -} - -} // namespace Mach-O -} - diff --git a/vendor/lief/api/python/OAT/CMakeLists.txt b/vendor/lief/api/python/OAT/CMakeLists.txt deleted file mode 100644 index a4aaad9..0000000 --- a/vendor/lief/api/python/OAT/CMakeLists.txt +++ /dev/null @@ -1,30 +0,0 @@ -set(LIEF_PYTHON_OAT_OBJECTS_SRC - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDexFile.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyClass.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyMethod.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBinary.cpp" -) - -set(LIEF_PYTHON_OAT_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyOAT.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" -) - - -set(LIEF_PYTHON_OAT_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyOAT.hpp") - - -list(APPEND LIEF_PYTHON_OAT_SRC ${LIEF_PYTHON_OAT_OBJECTS_SRC}) - -source_group("Source Files\\OAT" FILES ${LIEF_PYTHON_OAT_SRC}) -source_group("Header Files\\OAT" FILES ${LIEF_PYTHON_OAT_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_OAT_SRC}" "${LIEF_PYTHON_OAT_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../") - - diff --git a/vendor/lief/api/python/OAT/objects/pyBinary.cpp b/vendor/lief/api/python/OAT/objects/pyBinary.cpp deleted file mode 100644 index 8d41818..0000000 --- a/vendor/lief/api/python/OAT/objects/pyBinary.cpp +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/OAT/Binary.hpp" -#include "LIEF/OAT/hash.hpp" -#include "LIEF/ELF/Binary.hpp" -#include "pyIterators.hpp" - -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -template -using no_const_getter = T (Binary::*)(); - -template -using no_const_func = T (Binary::*)(P); - -template -using getter_t = T (Binary::*)() const; - -template -using setter_t = void (Binary::*)(T); - -template<> -void create(py::module& m) { - - // Binary object - py::class_ bin(m, "Binary", "OAT binary representation"); - - init_ref_iterator(bin, "it_dex_files"); - init_ref_iterator(bin, "it_oat_dex_files"); - init_ref_iterator(bin, "it_classes"); - init_ref_iterator(bin, "it_methods"); - - bin - .def_property_readonly("header", - static_cast>(&Binary::header), - "Return the OAT " RST_CLASS_REF(lief.OAT.Header) "", - py::return_value_policy::reference) - - .def_property_readonly("dex_files", - static_cast>(&Binary::dex_files), - "Return an iterator over " RST_CLASS_REF(lief.DEX.File) "") - - .def_property_readonly("oat_dex_files", - static_cast>(&Binary::oat_dex_files), - "Return an iterator over " RST_CLASS_REF(lief.OAT.DexFile) "") - - .def_property_readonly("classes", - static_cast>(&Binary::classes), - "Return an iterator over " RST_CLASS_REF(lief.OAT.Class) "", - py::return_value_policy::reference) - - .def_property_readonly("methods", - static_cast>(&Binary::methods), - "Return an iterator over " RST_CLASS_REF(lief.OAT.Method) "", - py::return_value_policy::reference) - - .def_property_readonly("has_class", - &Binary::has_class, - "Check if the class if the given name is present in the current OAT binary") - - .def("get_class", - static_cast>(&Binary::get_class), - "Return the " RST_CLASS_REF(lief.OAT.Class) " from its name", - "class_name"_a, - py::return_value_policy::reference) - - .def("get_class", - static_cast>(&Binary::get_class), - "Return the " RST_CLASS_REF(lief.OAT.Class) " from its **index**", - "class_index"_a, - py::return_value_policy::reference) - - .def_property_readonly("dex2dex_json_info", - &Binary::dex2dex_json_info) - - .def("__eq__", &Binary::operator==) - .def("__ne__", &Binary::operator!=) - .def("__hash__", - [] (const Binary& bin) { - return Hash::hash(bin); - }) - - .def("__str__", - [] (const Binary& binary) - { - std::ostringstream stream; - stream << binary; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/OAT/objects/pyClass.cpp b/vendor/lief/api/python/OAT/objects/pyClass.cpp deleted file mode 100644 index e887b37..0000000 --- a/vendor/lief/api/python/OAT/objects/pyClass.cpp +++ /dev/null @@ -1,108 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/OAT/Class.hpp" -#include "LIEF/OAT/hash.hpp" - -#include "pyIterators.hpp" -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -template -using getter_t = T (Class::*)(void) const; - -template -using setter_t = void (Class::*)(T); - -template -using no_const_getter = T (Class::*)(void); - -template<> -void create(py::module& m) { - - py::class_ cls(m, "Class", "OAT Class representation"); - - init_ref_iterator(cls, "it_methods"); - - cls - .def(py::init<>()) - - .def("has_dex_class", - &Class::has_dex_class, - "True if a " RST_CLASS_REF_FULL(lief.DEX.Class) " object " - "is associated with this **OAT** Class") - - .def_property_readonly("status", - &Class::status, - "Class " RST_CLASS_REF(lief.OAT.OAT_CLASS_STATUS) "") - - .def_property_readonly("type", - &Class::type, - "Information (" RST_CLASS_REF(lief.OAT.OAT_CLASS_TYPES) ") about how methods " - "are optimized") - - .def_property_readonly("fullname", - &Class::fullname, - "Class mangled name (e.g. ``Lcom/android/MyActivity;``)") - - .def_property_readonly("index", - &Class::index, - "Index the **DEX** classes pool (" RST_ATTR_REF_FULL(lief.DEX.File.classes) ")") - - .def_property_readonly("methods", - static_cast>(&Class::methods), - "Iterator over " RST_CLASS_REF_FULL(lief.OAT.Method) "") - - .def_property_readonly("bitmap", - &Class::bitmap, - "Bitmap information used to quickly find which methods are " - "optimized") - - .def("is_quickened", - static_cast(&Class::is_quickened), - "Check if the given " RST_CLASS_REF_FULL(lief.DEX.Method) " is compiled into native code", - "dex_method"_a) - - .def("is_quickened", - static_cast(&Class::is_quickened), - "Check if the Method at the given index is compiled into native code", - "method_index"_a) - - .def("method_offsets_index", - static_cast(&Class::method_offsets_index)) - - .def("method_offsets_index", - static_cast(&Class::method_offsets_index)) - - .def("__eq__", &Class::operator==) - .def("__ne__", &Class::operator!=) - .def("__hash__", - [] (const Class& cls) { - return Hash::hash(cls); - }) - - .def("__str__", - [] (const Class& cls) { - std::ostringstream stream; - stream << cls; - return stream.str(); - }); -} - - -} -} diff --git a/vendor/lief/api/python/OAT/objects/pyDexFile.cpp b/vendor/lief/api/python/OAT/objects/pyDexFile.cpp deleted file mode 100644 index 20ac3a6..0000000 --- a/vendor/lief/api/python/OAT/objects/pyDexFile.cpp +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/OAT/DexFile.hpp" -#include "LIEF/OAT/hash.hpp" - -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -template -using getter_t = T (DexFile::*)(void) const; - -template -using setter_t = void (DexFile::*)(T); - -template -using no_const_getter = T (DexFile::*)(void); - -template<> -void create(py::module& m) { - - py::class_(m, "DexFile", "OAT DexFile representation") - .def(py::init<>()) - - .def_property("location", - static_cast>(&DexFile::location), - static_cast>(&DexFile::location), - "Original location of the DEX file") - - .def_property("checksum", - static_cast>(&DexFile::checksum), - static_cast>(&DexFile::checksum), - "Checksum of the underlying DEX file") - - .def_property("dex_offset", - static_cast>(&DexFile::dex_offset), - static_cast>(&DexFile::dex_offset), - "Offset to the raw " RST_CLASS_REF_FULL(lief.DEX.File) "") - - .def_property_readonly("has_dex_file", - &DexFile::has_dex_file, - "Check if the " RST_CLASS_REF_FULL(lief.DEX.File) " is present") - - .def_property_readonly("dex_file", - static_cast>(&DexFile::dex_file), - "Associated " RST_CLASS_REF_FULL(lief.DEX.File) "") - - .def("__eq__", &DexFile::operator==) - .def("__ne__", &DexFile::operator!=) - .def("__hash__", - [] (const DexFile& dex_file) { - return Hash::hash(dex_file); - }) - - .def("__str__", - [] (const DexFile& dexfile) { - std::ostringstream stream; - stream << dexfile; - return stream.str(); - }); -} - -} -} - diff --git a/vendor/lief/api/python/OAT/objects/pyHeader.cpp b/vendor/lief/api/python/OAT/objects/pyHeader.cpp deleted file mode 100644 index 8dd233c..0000000 --- a/vendor/lief/api/python/OAT/objects/pyHeader.cpp +++ /dev/null @@ -1,203 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/OAT/Header.hpp" -#include "LIEF/OAT/hash.hpp" - -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - -template -using no_const_getter = T (Header::*)(void); - -template<> -void create
(py::module& m) { - - py::class_ hdr(m, "Header", "OAT Header representation"); - py::class_ it_key_values_t(hdr, "it_key_values_t"); - - py::class_(it_key_values_t, "value_type") - .def_property_readonly("key", - [] (Header::it_key_values_t::reference p) { - return p.first; - }, py::return_value_policy::reference_internal) - - .def_property("value", - [] (Header::it_key_values_t::reference p) { - return p.second; - }, - [] (Header::it_key_values_t::reference p, const std::string& value) { - std::string& ref_value = p.second; - ref_value = value; - }, - py::return_value_policy::reference_internal); - - it_key_values_t - .def("__getitem__", - [] (Header::it_key_values_t& v, size_t i) -> Header::it_key_values_t::value_type { - if (i >= v.size()) - throw py::index_error(); - return v[i]; - }, - py::return_value_policy::reference_internal) - - .def("__len__", - [](Header::it_key_values_t& v) { - return v.size(); - }) - - .def("__iter__", - [](Header::it_key_values_t& v) -> Header::it_key_values_t { - return std::begin(v); - }, py::return_value_policy::reference_internal) - - .def("__next__", - [] (Header::it_key_values_t& v) -> Header::it_key_values_t::value_type { - if (v == std::end(v)) { - throw py::stop_iteration(); - } - return *(v++); - - }, py::return_value_policy::reference_internal); - - hdr - .def(py::init<>()) - - .def_property_readonly("key_values", - static_cast>(&Header::key_values), - "Configuration used for the ``dex2oat`` transformation", - py::return_value_policy::reference_internal) - - .def_property_readonly("keys", - &Header::keys, - "List of " RST_CLASS_REF(lief.OAT.HEADER_KEYS) " present", - py::return_value_policy::reference_internal) - - .def_property_readonly("values", - &Header::values, - "List of values associated with " RST_ATTR_REF(lief.OAT.Header.keys) "", - py::return_value_policy::move) - - .def_property_readonly("magic", - static_cast>(&Header::magic), - "Magic number: ``oat\\x0A``") - - .def_property_readonly("version", - static_cast>(&Header::version), - "Underlying version of the OAT file") - - .def_property_readonly("checksum", - static_cast>(&Header::checksum), - "Checksum of the OAT file") - - .def_property_readonly("instruction_set", - static_cast>(&Header::instruction_set), - "List of " RST_CLASS_REF(lief.OAT.INSTRUCTION_SETS) "") - - .def_property_readonly("nb_dex_files", - static_cast>(&Header::nb_dex_files), - "Number of " RST_CLASS_REF_FULL(lief.DEX.File) " registred in the current OAT") - - .def_property_readonly("oat_dex_files_offset", - static_cast>(&Header::oat_dex_files_offset), - "Offset to the raw " RST_CLASS_REF_FULL(lief.OAT.DexFile) "\n\n" - ".. warning::\n\n" - "\tThis attribute is only relevant for OAT for which the version is above 131") - - .def_property_readonly("executable_offset", - static_cast>(&Header::executable_offset)) - - .def_property_readonly("i2i_bridge_offset", - static_cast>(&Header::i2i_bridge_offset)) - - .def_property_readonly("i2c_code_bridge_offset", - static_cast>(&Header::i2c_code_bridge_offset)) - - .def_property_readonly("jni_dlsym_lookup_offset", - static_cast>(&Header::jni_dlsym_lookup_offset)) - - .def_property_readonly("quick_generic_jni_trampoline_offset", - static_cast>(&Header::quick_generic_jni_trampoline_offset)) - - .def_property_readonly("quick_imt_conflict_trampoline_offset", - static_cast>(&Header::quick_imt_conflict_trampoline_offset)) - - .def_property_readonly("quick_resolution_trampoline_offset", - static_cast>(&Header::quick_resolution_trampoline_offset)) - - .def_property_readonly("quick_to_interpreter_bridge_offset", - static_cast>(&Header::quick_to_interpreter_bridge_offset)) - - .def_property_readonly("image_patch_delta", - static_cast>(&Header::image_patch_delta)) - - .def_property_readonly("image_file_location_oat_checksum", - static_cast>(&Header::image_file_location_oat_checksum)) - - .def_property_readonly("image_file_location_oat_data_begin", - static_cast>(&Header::image_file_location_oat_data_begin)) - - .def_property_readonly("key_value_size", - static_cast>(&Header::key_value_size)) - - .def("get", - static_cast(&Header::get), - "key"_a, - py::return_value_policy::reference) - - - .def("set", - static_cast(&Header::set), - "key"_a, "value"_a, - py::return_value_policy::reference) - - .def("__getitem__", - static_cast(&Header::operator[]), - "", - py::return_value_policy::reference) - - .def("__setitem__", - static_cast(&Header::set), - "", - py::return_value_policy::reference) - - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - - - .def("__str__", - [] (const Header& header) { - std::ostringstream stream; - stream << header; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/OAT/objects/pyMethod.cpp b/vendor/lief/api/python/OAT/objects/pyMethod.cpp deleted file mode 100644 index 0f74c82..0000000 --- a/vendor/lief/api/python/OAT/objects/pyMethod.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/OAT/Method.hpp" -#include "LIEF/OAT/hash.hpp" - -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -template -using getter_t = T (Method::*)(void) const; - -template -using setter_t = void (Method::*)(T); - -template -using no_const_getter = T (Method::*)(void); - -template<> -void create(py::module& m) { - - py::class_(m, "Method", "OAT Method representation") - .def(py::init<>()) - - .def_property_readonly("name", - &Method::name, - "Method's name") - - .def_property_readonly("oat_class", - static_cast>(&Method::oat_class), - "" RST_CLASS_REF(lief.OAT.Class) " associated with the method (or None)", - py::return_value_policy::reference) - - .def_property_readonly("dex_method", - static_cast>(&Method::dex_method), - "Mirrored " RST_CLASS_REF(lief.DEX.Method) " associated with the OAT method (or None)", - py::return_value_policy::reference) - - .def_property_readonly("has_dex_method", - &Method::has_dex_method, - "Check if a " RST_CLASS_REF(lief.DEX.Method) " is associated with the OAT method", - py::return_value_policy::reference) - - .def_property_readonly("is_dex2dex_optimized", - &Method::is_dex2dex_optimized, - "True if the optimization is **DEX**") - - .def_property_readonly("is_compiled", - &Method::is_compiled, - "True if the optimization is **native**") - - .def_property("quick_code", - static_cast>(&Method::quick_code), - static_cast>(&Method::quick_code), - "Quick code associated with the method") - - .def("__eq__", &Method::operator==) - .def("__ne__", &Method::operator!=) - .def("__hash__", - [] (const Method& method) { - return Hash::hash(method); - }) - - .def("__str__", - [] (const Method& method) { - std::ostringstream stream; - stream << method; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/OAT/objects/pyParser.cpp b/vendor/lief/api/python/OAT/objects/pyParser.cpp deleted file mode 100644 index af26ef0..0000000 --- a/vendor/lief/api/python/OAT/objects/pyParser.cpp +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyOAT.hpp" - -#include "LIEF/OAT/Parser.hpp" - -#include - -namespace LIEF { -namespace OAT { - -template<> -void create(py::module& m) { - - // Parser (Parser) - m.def("parse", - static_cast (*) (const std::string&)>(&Parser::parse), - "Parse the given OAT file and return a " RST_CLASS_REF(lief.OAT.Binary) " object", - "oat_file"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast (*) (const std::string&, const std::string&)>(&Parser::parse), - "Parse the given OAT with its VDEX file and return a " RST_CLASS_REF(lief.OAT.Binary) " object", - "oat_file"_a, "vdex_file"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast (*) (std::vector, const std::string&)>(&Parser::parse), - "Parse the given raw data and return a " RST_CLASS_REF(lief.OAT.Binary) " object", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::OAT::Parser::parse(std::move(raw), name); - }, - "io"_a, "name"_a = "", - py::return_value_policy::take_ownership); -} -} -} diff --git a/vendor/lief/api/python/OAT/pyEnums.cpp b/vendor/lief/api/python/OAT/pyEnums.cpp deleted file mode 100644 index fa01588..0000000 --- a/vendor/lief/api/python/OAT/pyEnums.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyOAT.hpp" -#include "LIEF/OAT/enums.hpp" -#include "LIEF/OAT/EnumToString.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace OAT { - -void init_enums(py::module& m) { - - py::enum_(m, "OAT_CLASS_TYPES") - .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_ALL_COMPILED)) - .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_SOME_COMPILED)) - .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_NONE_COMPILED)); - - py::enum_(m, "OAT_CLASS_STATUS") - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RETIRED)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_ERROR)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_NOTREADY)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_IDX)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_LOADED)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RESOLVING)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RESOLVED)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFYING)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RETRY_VERIFICATION_AT_RUNTIME)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFYING_AT_RUNTIME)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFIED)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_INITIALIZING)) - .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_INITIALIZED)); - - py::enum_(m, "HEADER_KEYS") - .value(PY_ENUM(HEADER_KEYS::KEY_IMAGE_LOCATION)) - .value(PY_ENUM(HEADER_KEYS::KEY_DEX2OAT_CMD_LINE)) - .value(PY_ENUM(HEADER_KEYS::KEY_DEX2OAT_HOST)) - .value(PY_ENUM(HEADER_KEYS::KEY_PIC)) - .value(PY_ENUM(HEADER_KEYS::KEY_HAS_PATCH_INFO)) - .value(PY_ENUM(HEADER_KEYS::KEY_DEBUGGABLE)) - .value(PY_ENUM(HEADER_KEYS::KEY_NATIVE_DEBUGGABLE)) - .value(PY_ENUM(HEADER_KEYS::KEY_COMPILER_FILTER)) - .value(PY_ENUM(HEADER_KEYS::KEY_CLASS_PATH)) - .value(PY_ENUM(HEADER_KEYS::KEY_BOOT_CLASS_PATH)) - .value(PY_ENUM(HEADER_KEYS::KEY_CONCURRENT_COPYING)); - - - py::enum_(m, "INSTRUCTION_SETS") - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_NONE)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_ARM)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_ARM_64)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_THUMB2)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_X86)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_X86_64)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_MIPS)) - .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_MIPS_64)); - -} - -} -} diff --git a/vendor/lief/api/python/OAT/pyOAT.cpp b/vendor/lief/api/python/OAT/pyOAT.cpp deleted file mode 100644 index 0e0c9bf..0000000 --- a/vendor/lief/api/python/OAT/pyOAT.cpp +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyOAT.hpp" - -namespace LIEF { -namespace OAT { - -void init_python_module(py::module& m) { - py::module LIEF_OAT_module = m.def_submodule("OAT", "Python API for OAT format"); - - init_enums(LIEF_OAT_module); - init_utils(LIEF_OAT_module); - - init_objects(LIEF_OAT_module); -} - - -void init_objects(py::module& m) { - CREATE(Parser, m); - CREATE(Binary, m); - CREATE(Header, m); - CREATE(DexFile, m); - CREATE(Class, m); - CREATE(Method, m); -} -} -} diff --git a/vendor/lief/api/python/OAT/pyOAT.hpp b/vendor/lief/api/python/OAT/pyOAT.hpp deleted file mode 100644 index 65c3ead..0000000 --- a/vendor/lief/api/python/OAT/pyOAT.hpp +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_OAT_H_ -#define PY_LIEF_OAT_H_ - -#include "LIEF/OAT.hpp" -#include "pyLIEF.hpp" - -#include -#include - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -PYBIND11_MAKE_OPAQUE(LIEF::OAT::Header::it_key_values_t::value_type); // std::pair> - -namespace LIEF { -namespace OAT { - -template -void create(py::module&); - -void init_python_module(py::module& m); - -void init_objects(py::module&); - -void init_enums(py::module&); -void init_utils(py::module&); - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(Binary); -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(DexFile); -SPECIALIZE_CREATE(Class); -SPECIALIZE_CREATE(Method); -} -} - - -#endif diff --git a/vendor/lief/api/python/OAT/pyUtils.cpp b/vendor/lief/api/python/OAT/pyUtils.cpp deleted file mode 100644 index 734a340..0000000 --- a/vendor/lief/api/python/OAT/pyUtils.cpp +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyOAT.hpp" - -#include "LIEF/OAT/utils.hpp" - -namespace LIEF { -namespace OAT { - -void init_utils(py::module& m) { - - m.def("is_oat", - static_cast(&is_oat), - "Check if the " RST_CLASS_REF(lief.ELF.Binary) " given in parameter is a OAT one", - "binary"_a); - - m.def("is_oat", - static_cast(&is_oat), - "Check if the **file** given in parameter is a OAT one", - "path"_a); - - m.def("is_oat", - static_cast&)>(&is_oat), - "Check if the **raw data** given in parameter is a OAT one", - "raw"_a); - - - m.def("version", - static_cast(&version), - "Return the OAT version of the " RST_CLASS_REF(lief.ELF.Binary) " given in parameter", - "binary"_a); - - m.def("version", - static_cast(&version), - "Return the OAT version of the **file** given in parameter", - "file"_a); - - m.def("version", - static_cast&)>(&version), - "Return the OAT version of the **raw data** given in parameter", - "raw"_a); - - - m.def("android_version", - &android_version, - "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given OAT version"); -} - -} -} - diff --git a/vendor/lief/api/python/PE/CMakeLists.txt b/vendor/lief/api/python/PE/CMakeLists.txt deleted file mode 100644 index 15d8ee1..0000000 --- a/vendor/lief/api/python/PE/CMakeLists.txt +++ /dev/null @@ -1,63 +0,0 @@ -set(LIEF_PYTHON_PE_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" - - "${CMAKE_CURRENT_LIST_DIR}/objects/pyResourceNode.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyResourceData.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyResourceDirectory.cpp" - - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceIcon.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceVersion.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceVarFileInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceFixedFileInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceStringFileInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyLangCodeItem.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceDialog.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceDialogItem.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceStringTable.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/resources/pyResourceAccelerator.cpp" - - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeIntegrity.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDataDirectory.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDosHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRichHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRichEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBuilder.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyOptionalHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocationEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyBinary.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyResourcesManager.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDebug.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeView.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyCodeViewPDB.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyPogo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyPogoEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySection.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyExport.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyImport.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyExportEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyRelocation.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyImportEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDelayImport.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyDelayImportEntry.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pySymbol.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyTLS.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyEnums.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyPE.cpp" -) - -set(LIEF_PYTHON_PE_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyPE.hpp") - -source_group("Source Files\\PE" FILES ${LIEF_PYTHON_PE_SRC}) -source_group("Header Files\\PE" FILES ${LIEF_PYTHON_PE_HDR}) - -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_PE_SRC}" "${LIEF_PYTHON_PE_HDR}") - - -include("${CMAKE_CURRENT_LIST_DIR}/objects/LoadConfigurations/CMakeLists.txt") -include("${CMAKE_CURRENT_LIST_DIR}/objects/signature/CMakeLists.txt") - - diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/CMakeLists.txt b/vendor/lief/api/python/PE/objects/LoadConfigurations/CMakeLists.txt deleted file mode 100644 index e9870c0..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -set(LIEF_PYTHON_PE_LOAD_CONFIGURE_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfiguration.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV0.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV1.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV2.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV3.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV4.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV5.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV6.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyLoadConfigurationV7.cpp" -) - -source_group("Source Files\\PE\\Load Configuration" FILES ${LIEF_PYTHON_PE_LOAD_CONFIGURE_SRC}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_PE_LOAD_CONFIGURE_SRC}") - - - diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp deleted file mode 100644 index f5d2114..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp +++ /dev/null @@ -1,170 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfiguration::*)(void) const; - -template -using setter_t = void (LoadConfiguration::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfiguration", - R"delim( - Class that represents the default PE's ``LoadConfiguration`` - It's the base class for any future versions of the structure - )delim") - .def(py::init<>()) - - .def_property_readonly("version", - &LoadConfiguration::version, - "(SDK) Version of the structure. (" RST_CLASS_REF(lief.PE.WIN_VERSION) ")") - - .def_property("characteristics", - static_cast>(&LoadConfiguration::characteristics), - static_cast>(&LoadConfiguration::characteristics), - "Characteristics of the structure.") - - .def_property_readonly("size", - static_cast>(&LoadConfiguration::size), - "Size of the structure which is an alias for " RST_ATTR_REF(lief.PE.LoadConfiguration.characteristics) "") - - .def_property("timedatestamp", - static_cast>(&LoadConfiguration::timedatestamp), - static_cast>(&LoadConfiguration::timedatestamp), - "Date and time stamp value") - - .def_property("major_version", - static_cast>(&LoadConfiguration::major_version), - static_cast>(&LoadConfiguration::major_version), - "Major Version") - - .def_property("minor_version", - static_cast>(&LoadConfiguration::minor_version), - static_cast>(&LoadConfiguration::minor_version), - "Minor version") - - .def_property("global_flags_clear", - static_cast>(&LoadConfiguration::global_flags_clear), - static_cast>(&LoadConfiguration::global_flags_clear), - "The global loader flags to clear for this process as the loader start the process.") - - .def_property("global_flags_set", - static_cast>(&LoadConfiguration::global_flags_set), - static_cast>(&LoadConfiguration::global_flags_set), - "The global loader flags to set for this process as the loader starts the process.") - - .def_property("critical_section_default_timeout", - static_cast>(&LoadConfiguration::critical_section_default_timeout), - static_cast>(&LoadConfiguration::critical_section_default_timeout), - "The default timeout value to use for is process’s critical sections that are abandoned.") - - .def_property("decommit_free_block_threshold", - static_cast>(&LoadConfiguration::decommit_free_block_threshold), - static_cast>(&LoadConfiguration::decommit_free_block_threshold), - "Memory that must be freed before it is returned to the system, in bytes.") - - .def_property("decommit_total_free_threshold", - static_cast>(&LoadConfiguration::decommit_total_free_threshold), - static_cast>(&LoadConfiguration::decommit_total_free_threshold), - "Total amount of free memory, in bytes") - - .def_property("lock_prefix_table", - static_cast>(&LoadConfiguration::lock_prefix_table), - static_cast>(&LoadConfiguration::lock_prefix_table), - "The **VA** of a list of addresses where the ``LOCK`` prefix " - "is used so that they can be replaced with ``NOP`` on single processor machines.") - - .def_property("maximum_allocation_size", - static_cast>(&LoadConfiguration::maximum_allocation_size), - static_cast>(&LoadConfiguration::maximum_allocation_size), - "Maximum allocation size, in bytes.") - - .def_property("virtual_memory_threshold", - static_cast>(&LoadConfiguration::virtual_memory_threshold), - static_cast>(&LoadConfiguration::virtual_memory_threshold), - "Maximum virtual memory size, in bytes.") - - .def_property("process_affinity_mask", - static_cast>(&LoadConfiguration::process_affinity_mask), - static_cast>(&LoadConfiguration::process_affinity_mask), - "Setting this field to a non-zero value is equivalent to calling " - "``SetProcessAffinityMask`` with this value during process startup (.exe only)") - - .def_property("process_heap_flags", - static_cast>(&LoadConfiguration::process_heap_flags), - static_cast>(&LoadConfiguration::process_heap_flags), - R"delim( - Process heap flags that correspond to the first argument of the ``HeapCreate`` - function. These flags apply to the process heap that is created during process startup. - )delim") - - .def_property("csd_version", - static_cast>(&LoadConfiguration::csd_version), - static_cast>(&LoadConfiguration::csd_version), - "The service pack version identifier.") - - .def_property("reserved1", - static_cast>(&LoadConfiguration::reserved1), - static_cast>(&LoadConfiguration::reserved1), - "Must be zero.") - - .def_property("dependent_load_flags", - static_cast>(&LoadConfiguration::dependent_load_flags), - static_cast>(&LoadConfiguration::dependent_load_flags), - "On recent the version of the structure, Microsoft renamed reserved1 to DependentLoadFlags. " - "This is an alias for " RST_ATTR_REF(lief.PE.LoadConfiguration.reserved1) "") - - .def_property("editlist", - static_cast>(&LoadConfiguration::editlist), - static_cast>(&LoadConfiguration::editlist), - "Reserved for use by the system.") - - .def_property("security_cookie", - static_cast>(&LoadConfiguration::security_cookie), - static_cast>(&LoadConfiguration::security_cookie), - "A pointer to a cookie that is used by Visual C++ or GS implementation.") - - .def("__eq__", &LoadConfiguration::operator==) - .def("__ne__", &LoadConfiguration::operator!=) - .def("__hash__", - [] (const LoadConfiguration& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfiguration& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV0.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV0.cpp deleted file mode 100644 index 977f533..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV0.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV0::*)(void) const; - -template -using setter_t = void (LoadConfigurationV0::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV0", - R"delim( - :class:`~lief.PE.LoadConfiguration` enhanced with SEH. - It is associated with the :class:`~lief.PE.WIN_VERSION`: :attr:`~lief.PE.WIN_VERSION.SEH` - )delim") - - .def(py::init<>()) - - .def_property("se_handler_table", - static_cast>(&LoadConfigurationV0::se_handler_table), - static_cast>(&LoadConfigurationV0::se_handler_table), - "The VA of the sorted table of RVAs of each valid, unique " - "SE handler in the image.") - - .def_property("se_handler_count", - static_cast>(&LoadConfigurationV0::se_handler_count), - static_cast>(&LoadConfigurationV0::se_handler_count), - "The count of unique handlers in the table.") - - - .def("__eq__", &LoadConfigurationV0::operator==) - .def("__ne__", &LoadConfigurationV0::operator!=) - .def("__hash__", - [] (const LoadConfigurationV0& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV0& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV1.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV1.cpp deleted file mode 100644 index d2da0a4..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV1.cpp +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV1::*)(void) const; - -template -using setter_t = void (LoadConfigurationV1::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV1", - R"delim( - :class:`~lief.PE.LoadConfigurationV0` enhanced with *Control Flow Guard*. - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN_8_1` - )delim") - .def(py::init<>()) - - .def_property("guard_cf_check_function_pointer", - static_cast>(&LoadConfigurationV1::guard_cf_check_function_pointer), - static_cast>(&LoadConfigurationV1::guard_cf_check_function_pointer), - "The VA where Control Flow Guard check-function pointer is stored.") - - .def_property("guard_cf_dispatch_function_pointer", - static_cast>(&LoadConfigurationV1::guard_cf_dispatch_function_pointer), - static_cast>(&LoadConfigurationV1::guard_cf_dispatch_function_pointer), - "The VA where Control Flow Guard dispatch-function pointer is stored.") - - .def_property("guard_cf_function_table", - static_cast>(&LoadConfigurationV1::guard_cf_function_table), - static_cast>(&LoadConfigurationV1::guard_cf_function_table), - "The VA of the sorted table of RVAs of each Control Flow Guard function in the image.") - - .def_property("guard_cf_function_count", - static_cast>(&LoadConfigurationV1::guard_cf_function_count), - static_cast>(&LoadConfigurationV1::guard_cf_function_count), - "The count of unique RVAs in the :attr:`~lief.PE.LoadConfigurationV1.guard_cf_function_table`") - - .def_property("guard_flags", - static_cast>(&LoadConfigurationV1::guard_flags), - static_cast>(&LoadConfigurationV1::guard_flags), - "Control Flow Guard related flags.") - - .def("has", - static_cast(&LoadConfigurationV1::has), - "Check if the given " RST_CLASS_REF(lief.PE.GUARD_CF_FLAGS) " is present in " - ":attr:`~lief.PE.LoadConfigurationV1.guard_flags`", - "flag"_a) - - .def_property_readonly("guard_cf_flags_list", - &LoadConfigurationV1::guard_cf_flags_list, - "Return list of " RST_CLASS_REF(lief.PE.GUARD_CF_FLAGS) " present in " - ":attr:`~lief.PE.LoadConfigurationV1.guard_flags`", - py::return_value_policy::reference_internal) - - .def("__eq__", &LoadConfigurationV1::operator==) - .def("__ne__", &LoadConfigurationV1::operator!=) - .def("__hash__", - [] (const LoadConfigurationV1& config) { - return Hash::hash(config); - }) - - - .def("__contains__", - static_cast(&LoadConfigurationV1::has)) - - - .def("__str__", [] (const LoadConfigurationV1& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV2.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV2.cpp deleted file mode 100644 index d5dc472..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV2.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV2::*)(void) const; - -template -using setter_t = void (LoadConfigurationV2::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV2", - R"delim( - :class:`~lief.PE.LoadConfigurationV1` enhanced with *code integrity*. - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN10_0_9879` - )delim") - - .def(py::init<>()) - - .def_property_readonly("code_integrity", - static_cast(&LoadConfigurationV2::code_integrity), - "" RST_CLASS_REF(lief.PE.CodeIntegrity) " object", - py::return_value_policy::reference) - - - .def("__eq__", &LoadConfigurationV2::operator==) - .def("__ne__", &LoadConfigurationV2::operator!=) - .def("__hash__", - [] (const LoadConfigurationV2& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV2& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV3.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV3.cpp deleted file mode 100644 index dd96f8c..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV3.cpp +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV3::*)(void) const; - -template -using setter_t = void (LoadConfigurationV3::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV3", - R"delim( - :class:`~lief.PE.LoadConfigurationV2` with Control Flow Guard improved. - - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN10_0_14286` - )delim") - - .def(py::init<>()) - - .def_property("guard_address_taken_iat_entry_table", - static_cast>(&LoadConfigurationV3::guard_address_taken_iat_entry_table), - static_cast>(&LoadConfigurationV3::guard_address_taken_iat_entry_table), - "VA of a table associated with CFG's *IAT* checks") - - .def_property("guard_address_taken_iat_entry_count", - static_cast>(&LoadConfigurationV3::guard_address_taken_iat_entry_count), - static_cast>(&LoadConfigurationV3::guard_address_taken_iat_entry_count), - "Number of entries in the :attr:`~lief.PE.guard_address_taken_iat_entry_table`") - - .def_property("guard_long_jump_target_table", - static_cast>(&LoadConfigurationV3::guard_long_jump_target_table), - static_cast>(&LoadConfigurationV3::guard_long_jump_target_table), - "VA of a table associated with CFG's *long jump*") - - .def_property("guard_long_jump_target_count", - static_cast>(&LoadConfigurationV3::guard_long_jump_target_count), - static_cast>(&LoadConfigurationV3::guard_long_jump_target_count), - "Number of entries in the :attr:`~lief.PE.guard_address_taken_iat_entry_table`") - - .def("__eq__", &LoadConfigurationV3::operator==) - .def("__ne__", &LoadConfigurationV3::operator!=) - .def("__hash__", - [] (const LoadConfigurationV3& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV3& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV4.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV4.cpp deleted file mode 100644 index 0eb8bc0..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV4.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV4::*)(void) const; - -template -using setter_t = void (LoadConfigurationV4::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV4", - R"delim( - :class:`~lief.PE.LoadConfigurationV3` enhanced with: - - * Kind of dynamic relocations - * *Hybrid Metadata Pointer* - - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN10_0_14383` - )delim") - .def(py::init<>()) - - .def_property("dynamic_value_reloc_table", - static_cast>(&LoadConfigurationV4::dynamic_value_reloc_table), - static_cast>(&LoadConfigurationV4::dynamic_value_reloc_table), - "VA of pointing to a ``IMAGE_DYNAMIC_RELOCATION_TABLE``") - - .def_property("hybrid_metadata_pointer", - static_cast>(&LoadConfigurationV4::hybrid_metadata_pointer), - static_cast>(&LoadConfigurationV4::hybrid_metadata_pointer), - "") - - - .def("__eq__", &LoadConfigurationV4::operator==) - .def("__ne__", &LoadConfigurationV4::operator!=) - .def("__hash__", - [] (const LoadConfigurationV4& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV4& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV5.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV5.cpp deleted file mode 100644 index 7a7ac3b..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV5.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV5::*)(void) const; - -template -using setter_t = void (LoadConfigurationV5::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV5", - R"delim( - :class:`~lief.PE.LoadConfigurationV4` enhanced nhanced with Return Flow Guard. - - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN10_0_14901` - )delim") - - .def(py::init<>()) - - .def_property("guard_rf_failure_routine", - static_cast>(&LoadConfigurationV5::guard_rf_failure_routine), - static_cast>(&LoadConfigurationV5::guard_rf_failure_routine), - "VA of the failure routine") - - .def_property("guard_rf_failure_routine_function_pointer", - static_cast>(&LoadConfigurationV5::guard_rf_failure_routine_function_pointer), - static_cast>(&LoadConfigurationV5::guard_rf_failure_routine_function_pointer), - "VA of the failure routine ``fptr``") - - .def_property("dynamic_value_reloctable_offset", - static_cast>(&LoadConfigurationV5::dynamic_value_reloctable_offset), - static_cast>(&LoadConfigurationV5::dynamic_value_reloctable_offset), - "Offset of dynamic relocation table relative to the relocation table") - - .def_property("dynamic_value_reloctable_section", - static_cast>(&LoadConfigurationV5::dynamic_value_reloctable_section), - static_cast>(&LoadConfigurationV5::dynamic_value_reloctable_section), - "The section index of the dynamic value relocation table") - - .def_property("reserved2", - static_cast>(&LoadConfigurationV5::reserved2), - static_cast>(&LoadConfigurationV5::reserved2), - "Must be zero") - - - .def("__eq__", &LoadConfigurationV5::operator==) - .def("__ne__", &LoadConfigurationV5::operator!=) - .def("__hash__", - [] (const LoadConfigurationV5& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV5& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV6.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV6.cpp deleted file mode 100644 index 33fc9c9..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV6.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV6::*)(void) const; - -template -using setter_t = void (LoadConfigurationV6::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV6", - R"delim( - :class:`~lief.PE.LoadConfigurationV5` enhanced with Hotpatch and improved RFG. - - It is associated with the :class:`~lief.PE.WIN_VERSION` set to :attr:`~lief.PE.WIN_VERSION.WIN10_0_15002` - )delim") - - .def(py::init<>()) - - .def_property("guard_rf_verify_stackpointer_function_pointer", - static_cast>(&LoadConfigurationV6::guard_rf_verify_stackpointer_function_pointer), - static_cast>(&LoadConfigurationV6::guard_rf_verify_stackpointer_function_pointer), - "VA of the Function verifying the stack pointer") - - .def_property("hotpatch_table_offset", - static_cast>(&LoadConfigurationV6::hotpatch_table_offset), - static_cast>(&LoadConfigurationV6::hotpatch_table_offset), - "Offset to the *hotpatch* table") - - - .def("__eq__", &LoadConfigurationV6::operator==) - .def("__ne__", &LoadConfigurationV6::operator!=) - .def("__hash__", - [] (const LoadConfigurationV6& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV6& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV7.cpp b/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV7.cpp deleted file mode 100644 index caa9a28..0000000 --- a/vendor/lief/api/python/PE/objects/LoadConfigurations/pyLoadConfigurationV7.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/LoadConfigurations.hpp" - -#include -#include - - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LoadConfigurationV7::*)(void) const; - -template -using setter_t = void (LoadConfigurationV7::*)(T); - -template<> -void create(py::module& m) { - py::class_(m, "LoadConfigurationV7") - .def(py::init<>()) - - .def_property("reserved3", - static_cast>(&LoadConfigurationV7::reserved3), - static_cast>(&LoadConfigurationV7::reserved3), - "") - - .def_property("addressof_unicode_string", - static_cast>(&LoadConfigurationV7::addressof_unicode_string), - static_cast>(&LoadConfigurationV7::addressof_unicode_string), - "") - - - .def("__eq__", &LoadConfigurationV7::operator==) - .def("__ne__", &LoadConfigurationV7::operator!=) - .def("__hash__", - [] (const LoadConfigurationV7& config) { - return Hash::hash(config); - }) - - - .def("__str__", [] (const LoadConfigurationV7& config) - { - std::ostringstream stream; - stream << config; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyBinary.cpp b/vendor/lief/api/python/PE/objects/pyBinary.cpp deleted file mode 100644 index 1108b1d..0000000 --- a/vendor/lief/api/python/PE/objects/pyBinary.cpp +++ /dev/null @@ -1,424 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/PE/Parser.hpp" -#include "LIEF/PE/Builder.hpp" -#include "LIEF/PE/Binary.hpp" -#include "LIEF/Abstract/Binary.hpp" - -#include "pyPE.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace PE { - -template -using no_const_func = T (Binary::*)(P); - -template -using no_const_getter = T (Binary::*)(void); - -template -using getter_t = T (Binary::*)(void) const; - -template -using setter_t = void (Binary::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ bin(m, "Binary", - R"delim( - Class which represents a PE binary which is the main interface - to manage and modify a PE executable. - - This object can be instantiated through :func:`lief.parse` or :func:`lief.PE.parse` while - the constructor of this object can be used to craft a binary from scratch (see: :ref:`02-pe-from-scratch`) - )delim"); - - init_ref_iterator(bin, "it_section"); - init_ref_iterator(bin, "it_data_directories"); - init_ref_iterator(bin, "it_relocations"); - init_ref_iterator(bin, "it_imports"); - init_ref_iterator(bin, "it_delay_imports"); - init_ref_iterator(bin, "it_symbols"); - init_ref_iterator(bin, "it_const_signatures"); - - bin - .def(py::init(), - "name"_a, "type"_a) - - .def_property_readonly("sections", - static_cast>(&Binary::sections), - "Return binary's an iterator over the PE's " RST_CLASS_REF(lief.PE.Section) "", - py::return_value_policy::reference) - - .def_property_readonly("dos_header", - static_cast(&Binary::dos_header), - "Return the " RST_CLASS_REF(lief.PE.DosHeader) "", - py::return_value_policy::reference) - - .def_property_readonly("header", - static_cast(&Binary::header), - "Return the " RST_CLASS_REF(lief.PE.Header) "", - py::return_value_policy::reference) - - .def_property_readonly("optional_header", - static_cast(&Binary::optional_header), - "Return the " RST_CLASS_REF(lief.PE.OptionalHeader) "", - py::return_value_policy::reference) - - .def_property_readonly("virtual_size", - &Binary::virtual_size, - R"delim( - Return the binary's virtual size. - - This value should match :attr:`~lief.PE.OptionalHeader.sizeof_image` - )delim") - - .def_property_readonly("sizeof_headers", - &Binary::sizeof_headers, - "Size of all the PE headers") - - .def("rva_to_offset", - &Binary::rva_to_offset, - "rva_address"_a, - R"delim( - Convert a relative virtual address to an offset - - The conversion is performed by looking for the section that encompasses the provided RVA. - )delim") - - .def("va_to_offset", - &Binary::va_to_offset, - "va_address"_a, - R"delim( - Convert an **absolute** virtual address into an offset - - See: :meth:`~lief.PE.Binary.rva_to_offset` - )delim") - - .def("section_from_offset", - static_cast(&Binary::section_from_offset), - R"delim( - Return the :class:`~lief.PE.Section` which encompasses the provided offset. - It returns None if a section can't be found. - )delim", - "offset"_a, - py::return_value_policy::reference) - - .def("section_from_rva", - static_cast(&Binary::section_from_rva), - R"delim( - Return the :class:`~lief.PE.Section` which encompasses the provided **relative** virtual address. - If a section can't be found, it returns None. - )delim", - "rva"_a, - py::return_value_policy::reference) - - .def_property("tls", - static_cast(&Binary::tls), - static_cast(&Binary::tls), - "" RST_CLASS_REF(lief.PE.TLS) " object (if present)", - py::return_value_policy::reference) - - .def_property("rich_header", - static_cast(&Binary::rich_header), - static_cast(&Binary::rich_header), - "" RST_CLASS_REF(lief.PE.RichHeader) " object (if present)", - py::return_value_policy::reference) - - .def_property_readonly("has_rich_header", &Binary::has_rich_header, - "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.RichHeader) " object") - - .def_property_readonly("has_debug", &Binary::has_debug, - "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Debug) " object") - - .def_property_readonly("has_tls", &Binary::has_tls, - "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.TLS) " object") - - .def_property_readonly("has_imports", &Binary::has_imports, - "``True`` if the current binary has imports (" RST_CLASS_REF(lief.PE.Import) ")") - - .def_property_readonly("has_exports", &Binary::has_exports, - "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Export) " object") - - .def_property_readonly("has_resources", &Binary::has_resources, - "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Resources) " object") - - .def_property_readonly("has_exceptions", &Binary::has_exceptions, - "``True`` if the current binary uses ``Exceptions``") - - .def_property_readonly("has_relocations", &Binary::has_relocations, - "``True`` if the current binary uses " RST_CLASS_REF(lief.PE.Relocation) "") - - .def_property_readonly("has_configuration", &Binary::has_configuration, - "``True`` if the current binary has " RST_CLASS_REF(lief.PE.LoadConfiguration) "") - - .def_property_readonly("has_signatures", &Binary::has_signatures, - "``True`` if the binary is signed with the PE authenticode (" RST_CLASS_REF(lief.PE.Signature) ")") - - .def_property_readonly("is_reproducible_build", &Binary::is_reproducible_build, - "``True`` if the binary was compiled with a reproducible build directive (" RST_CLASS_REF(lief.PE.Debug) ")") - - .def_property_readonly("functions", - &Binary::functions, - "**All** " RST_CLASS_REF(lief.Function) " found in the binary") - - .def_property_readonly("exception_functions", - &Binary::exception_functions, - "" RST_CLASS_REF(lief.Function) " found in the Exception directory") - - .def("predict_function_rva", - static_cast(&Binary::predict_function_rva), - "Try to predict the RVA of the given function name in the given import library name", - "library"_a, "function"_a) - - .def_property_readonly("signatures", - static_cast(&Binary::signatures), - "Return an iterator over the " RST_CLASS_REF(lief.PE.Signature) " objects", - py::return_value_policy::reference) - - .def("authentihash", - [] (const Binary& bin, ALGORITHMS algo) { - const std::vector& data = bin.authentihash(algo); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Compute the authentihash according to the " RST_CLASS_REF(lief.PE.ALGORITHMS) " " - "given in the first parameter", - "algorithm"_a) - - .def("verify_signature", - static_cast(&Binary::verify_signature), - R"delim( - Verify the binary against the embedded signature(s) (if any) - - First off, it checks that the embedded signatures are correct (c.f. :meth:`lief.PE.Signature.check`) - and then it checks that the authentihash matches :attr:`lief.PE.ContentInfo.digest` - - One can tweak the verification process with the :class:`lief.PE.Signature.VERIFICATION_CHECKS` flags - - .. seealso:: - - :meth:`lief.PE.Signature.check` - )delim", - "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT) - - .def("verify_signature", - static_cast(&Binary::verify_signature), - R"delim( - Verify the binary with the Signature object provided in the first parameter - It can be used to verify a detached signature: - - .. code-block:: python - - detached = lief.PE.Signature.parse("sig.pkcs7") - binary.verify_signature(detached) - )delim", - "signature"_a, "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT) - - .def_property_readonly("authentihash_md5", - [] (const Binary& bin) { - const std::vector& data = bin.authentihash(ALGORITHMS::MD5); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Authentihash **MD5** value") - - .def_property_readonly("authentihash_sha1", - [] (const Binary& bin) { - const std::vector& data = bin.authentihash(ALGORITHMS::SHA_1); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Authentihash **SHA1** value") - - .def_property_readonly("authentihash_sha256", - [] (const Binary& bin) { - const std::vector& data = bin.authentihash(ALGORITHMS::SHA_256); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Authentihash **SHA-256** value") - - .def_property_readonly("authentihash_sha512", - [] (const Binary& bin) { - const std::vector& data = bin.authentihash(ALGORITHMS::SHA_512); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Authentihash **SHA-512** value") - - .def_property_readonly("debug", - static_cast(&Binary::debug), - "Return the " RST_CLASS_REF(lief.PE.Debug) "", - py::return_value_policy::reference) - - .def_property_readonly("load_configuration", - static_cast(&Binary::load_configuration), - "Return the " RST_CLASS_REF(lief.PE.LoadConfiguration) " object or None if not present", - py::return_value_policy::reference) - - .def("get_export", - static_cast(&Binary::get_export), - "Return the " RST_CLASS_REF(lief.PE.Export) " object", - py::return_value_policy::reference) - - .def_property_readonly("symbols", - static_cast& (Binary::*)(void)>(&Binary::symbols), - "Return binary's " RST_CLASS_REF(lief.PE.Symbol) "", - py::return_value_policy::reference) - - .def("get_section", - static_cast>(&Binary::get_section), - "Return the " RST_CLASS_REF(lief.PE.Section) " object from the given name or None if not not found", - "section_name"_a, - py::return_value_policy::reference) - - .def("add_section", - &Binary::add_section, - "Add a " RST_CLASS_REF(lief.PE.Section) " to the binary.", - "section"_a, py::arg("type") = PE_SECTION_TYPES::UNKNOWN, - py::return_value_policy::reference) - - .def_property_readonly("relocations", - static_cast>(&Binary::relocations), - "Return an iterator over the " RST_CLASS_REF(lief.PE.Relocation) "", - py::return_value_policy::reference) - - .def("add_relocation", - &Binary::add_relocation, - "Add a " RST_CLASS_REF(lief.PE.Relocation) " to the binary", - "relocation"_a) - - .def("remove_all_relocations", &Binary::remove_all_relocations) - - .def("remove", - static_cast(&Binary::remove), - "Remove the " RST_CLASS_REF(lief.PE.Section) " given in first parameter", - "section"_a, "clear"_a = false) - - .def_property_readonly("data_directories", - static_cast>(&Binary::data_directories), - "Return an iterator over the " RST_CLASS_REF(lief.PE.DataDirectory) "", - py::return_value_policy::reference) - - .def("data_directory", - static_cast(&Binary::data_directory), - "Return the " RST_CLASS_REF(lief.PE.DataDirectory) " object from the given " RST_CLASS_REF(lief.PE.DATA_DIRECTORY) " type", - "type"_a, - py::return_value_policy::reference) - - .def_property_readonly("imports", - static_cast>(&Binary::imports), - "Return an iterator over the " RST_CLASS_REF(lief.PE.Import) " libraries", - py::return_value_policy::reference) - - .def("has_import", - &Binary::has_import, - "``True`` if the binary imports the given library name", - "import_name"_a) - - .def("get_import", - static_cast>(&Binary::get_import), - "Return the " RST_CLASS_REF(lief.PE.Import) " from the given name or None if not not found", - "import_name"_a, - py::return_value_policy::reference) - - .def_property_readonly("delay_imports", - static_cast>(&Binary::delay_imports), - "Return an iterator over the " RST_CLASS_REF(lief.PE.DelayImport) " ") - - .def_property_readonly("has_delay_imports", &Binary::has_delay_imports, - "``True`` if the current binary has delay imports (" RST_CLASS_REF(lief.PE.DelayImport) ")") - - .def("has_delay_import", - &Binary::has_delay_import, - "``True`` if the binary imports the given library name", - "import_name"_a) - - .def("get_delay_import", - static_cast>(&Binary::get_delay_import), - "Return the " RST_CLASS_REF(lief.PE.DelayImport) " from the given name or None if not not found", - "import_name"_a, - py::return_value_policy::reference) - - .def_property_readonly("resources_manager", - [] (Binary& self) { - return error_or(&Binary::resources_manager, self); - }, - "Return the " RST_CLASS_REF(lief.PE.ResourcesManager) " to manage resources") - - .def_property_readonly("resources", - static_cast>(&Binary::resources), - "Return the " RST_CLASS_REF(lief.PE.ResourceNode) " tree or None if not not present", - py::return_value_policy::reference) - - .def_property_readonly("overlay", - static_cast&>>(&Binary::overlay), - "Return the overlay content as a ``list`` of bytes", - py::return_value_policy::reference) - - .def_property("dos_stub", - static_cast&>>(&Binary::dos_stub), - static_cast&>>(&Binary::dos_stub), - "DOS stub content as a ``list`` of bytes") - - .def("add_import_function", - &Binary::add_import_function, - "Add a function to the given " RST_CLASS_REF(lief.PE.Import) " name", - "import_name"_a, "function_name"_a, - py::return_value_policy::reference) - - .def("add_library", - &Binary::add_library, - "Add an " RST_CLASS_REF(lief.PE.Import) " by name", - "import_name"_a, - py::return_value_policy::reference) - - .def("remove_library", - &Binary::remove_library, - "Remove the " RST_CLASS_REF(lief.PE.Import) " from the given name", - "import_name"_a) - - .def("hook_function", - static_cast(&Binary::hook_function), - "**DEPRECATED**", - "function_name"_a, "hook_address"_a) - - .def("hook_function", - static_cast(&Binary::hook_function), - "**DEPRECATED**", - "library_name"_a, "function_name"_a, "hook_address"_a) - - .def("remove_all_libraries", - &Binary::remove_all_libraries, - "Remove all imported libraries") - - .def("write", - static_cast(&Binary::write), - "Build the binary and write the result to the given ``output`` file", - "output_path"_a) - - .def("__str__", - [] (const Binary& binary) - { - std::ostringstream stream; - stream << binary; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyBuilder.cpp b/vendor/lief/api/python/PE/objects/pyBuilder.cpp deleted file mode 100644 index 1f5602f..0000000 --- a/vendor/lief/api/python/PE/objects/pyBuilder.cpp +++ /dev/null @@ -1,118 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/Builder.hpp" - -#include -#include - -//template>{}, int> = 0 > -//constexpr decltype(auto) my_invoke(Fn&& f, Args&&... args) -// noexcept(noexcept(std::mem_fn(f)(std::forward(args)...))) -//{ -// return std::mem_fn(f)(std::forward(args)...); -//} - -namespace LIEF { -namespace PE { - -template<> -void create(py::module& m) { - - py::class_(m, "Builder", - R"delim( - Class that is used to rebuild a raw PE binary from a PE::Binary object - )delim") - - .def(py::init(), - "Constructor that takes a " RST_CLASS_REF(lief.PE.Binary) "", - "pe_binary"_a) - - .def("build", - [] (Builder& self) -> py::object { - return error_or(static_cast(&Builder::build), self); - }, - "Perform the build process") - - .def("build_imports", - &Builder::build_imports, - "Rebuild the import table into another section", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("patch_imports", - &Builder::patch_imports, - "Patch the original import table in order to redirect functions to " - "the new import table.\n\n" - "This setting should be used with ``build_imports`` set to ``True``", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("build_relocations", - &Builder::build_relocations, - "Rebuild the relocation table in another section", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("build_tls", - static_cast(&Builder::build_tls), - "Rebuild TLS object in another section", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("build_resources", - static_cast(&Builder::build_resources), - "Rebuid the resources in another section", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("build_overlay", - static_cast(&Builder::build_overlay), - "Rebuild the binary's overlay", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("build_dos_stub", - static_cast(&Builder::build_dos_stub), - "Rebuild the DOS stub", - py::arg("enable") = true, - py::return_value_policy::reference) - - .def("write", - static_cast(&Builder::write), - "Write the build result into the ``output`` file", - "output"_a) - - .def("get_build", - &Builder::get_build, - "Return the build result as a ``list`` of bytes", - py::return_value_policy::reference_internal) - - - .def("__str__", - [] (const Builder& builder) { - std::ostringstream stream; - stream << builder; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyCodeIntegrity.cpp b/vendor/lief/api/python/PE/objects/pyCodeIntegrity.cpp deleted file mode 100644 index b946a61..0000000 --- a/vendor/lief/api/python/PE/objects/pyCodeIntegrity.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/CodeIntegrity.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (CodeIntegrity::*)(void) const; - -template -using setter_t = void (CodeIntegrity::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "CodeIntegrity") - .def(py::init<>()) - - .def_property("flags", - static_cast>(&CodeIntegrity::flags), - static_cast>(&CodeIntegrity::flags), - "Flags to indicate if CI information is available, etc.") - - .def_property("catalog", - static_cast>(&CodeIntegrity::catalog), - static_cast>(&CodeIntegrity::catalog), - "``0xFFFF`` means not available") - - .def_property("catalog_offset", - static_cast>(&CodeIntegrity::catalog_offset), - static_cast>(&CodeIntegrity::catalog_offset), - "") - - .def_property("reserved", - static_cast>(&CodeIntegrity::reserved), - static_cast>(&CodeIntegrity::reserved), - "Additional bitmask to be defined later") - - - .def("__eq__", &CodeIntegrity::operator==) - .def("__ne__", &CodeIntegrity::operator!=) - .def("__hash__", - [] (const CodeIntegrity& code) { - return Hash::hash(code); - }) - - - .def("__str__", [] (const CodeIntegrity& code) - { - std::ostringstream stream; - stream << code; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyCodeView.cpp b/vendor/lief/api/python/PE/objects/pyCodeView.cpp deleted file mode 100644 index 1a53335..0000000 --- a/vendor/lief/api/python/PE/objects/pyCodeView.cpp +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/CodeView.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (CodeView::*)(void) const; - -template -using setter_t = void (CodeView::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "CodeView") - .def_property_readonly("cv_signature", - static_cast>(&CodeView::cv_signature), - "Type of the code view (" RST_CLASS_REF(lief.PE.CODE_VIEW_SIGNATURES) ")") - - .def("__eq__", &CodeView::operator==) - .def("__ne__", &CodeView::operator!=) - .def("__hash__", - [] (const CodeView& codeview) { - return Hash::hash(codeview); - }) - - .def("__str__", [] (const CodeView& cv) - { - std::ostringstream stream; - stream << cv; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyCodeViewPDB.cpp b/vendor/lief/api/python/PE/objects/pyCodeViewPDB.cpp deleted file mode 100644 index 49a5c49..0000000 --- a/vendor/lief/api/python/PE/objects/pyCodeViewPDB.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/CodeViewPDB.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (CodeViewPDB::*)(void) const; - -template -using setter_t = void (CodeViewPDB::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "CodeViewPDB") - .def(py::init<>()) - - .def_property("signature", - static_cast>(&CodeViewPDB::signature), - static_cast>(&CodeViewPDB::signature)) - - .def_property("age", - static_cast>(&CodeViewPDB::age), - static_cast>(&CodeViewPDB::age)) - - .def_property("filename", - static_cast>(&CodeViewPDB::filename), - static_cast>(&CodeViewPDB::filename)) - - .def("__eq__", &CodeViewPDB::operator==) - .def("__ne__", &CodeViewPDB::operator!=) - .def("__hash__", - [] (const CodeViewPDB& codeview) { - return Hash::hash(codeview); - }) - - .def("__str__", [] (const CodeViewPDB& cv) - { - std::ostringstream stream; - stream << cv; - return stream.str(); - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyDataDirectory.cpp b/vendor/lief/api/python/PE/objects/pyDataDirectory.cpp deleted file mode 100644 index 05a5d57..0000000 --- a/vendor/lief/api/python/PE/objects/pyDataDirectory.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/DataDirectory.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (DataDirectory::*)(void) const; - -template -using setter_t = void (DataDirectory::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "DataDirectory", - R"delim( - Class that represents a PE data directory entry - )delim") - .def(py::init<>()) - .def_property("rva", - static_cast>(&DataDirectory::RVA), - static_cast>(&DataDirectory::RVA), - "**Relative** virtual address of the content associated with the current data directory") - - .def_property("size", - static_cast>(&DataDirectory::size), - static_cast>(&DataDirectory::size), - "Size in bytes of the content associated with the current data directory") - - .def_property_readonly("section", - static_cast(&DataDirectory::section), - "" RST_CLASS_REF(lief.PE.Section) " associated with the current data directory or None if not linked", - py::return_value_policy::reference) - - .def_property_readonly("type", - &DataDirectory::type, - "Type (" RST_CLASS_REF(lief.PE.DATA_DIRECTORY) ") of the current data directory", - py::return_value_policy::reference_internal) - - .def_property_readonly("has_section", - &DataDirectory::has_section, - "``True`` if the current data directory is tied to a " RST_CLASS_REF(lief.PE.Section) "") - - .def("__eq__", &DataDirectory::operator==) - .def("__ne__", &DataDirectory::operator!=) - .def("__hash__", - [] (const DataDirectory& data_directory) { - return Hash::hash(data_directory); - }) - - .def("__str__", [] (const DataDirectory& datadir) - { - std::ostringstream stream; - stream << datadir; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyDebug.cpp b/vendor/lief/api/python/PE/objects/pyDebug.cpp deleted file mode 100644 index 33b6913..0000000 --- a/vendor/lief/api/python/PE/objects/pyDebug.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Debug.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Debug::*)(void) const; - -template -using setter_t = void (Debug::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "Debug") - .def(py::init<>()) - - .def_property("characteristics", - static_cast>(&Debug::characteristics), - static_cast>(&Debug::characteristics), - "Reserved should be 0") - - .def_property("timestamp", - static_cast>(&Debug::timestamp), - static_cast>(&Debug::timestamp), - "The time and date that the debug data was created.") - - .def_property("major_version", - static_cast>(&Debug::major_version), - static_cast>(&Debug::major_version), - "The major version number of the debug data format.") - - .def_property("minor_version", - static_cast>(&Debug::minor_version), - static_cast>(&Debug::minor_version), - "The minor version number of the debug data format.") - - .def_property("type", - static_cast>(&Debug::type), - static_cast>(&Debug::type), - "The format (" RST_CLASS_REF(lief.PE.DEBUG_TYPES) ") of the debugging information") - - .def_property("sizeof_data", - static_cast>(&Debug::sizeof_data), - static_cast>(&Debug::sizeof_data), - "Size of the debug data") - - .def_property("addressof_rawdata", - static_cast>(&Debug::addressof_rawdata), - static_cast>(&Debug::addressof_rawdata), - "Address of the debug data relative to the image base") - - .def_property("pointerto_rawdata", - static_cast>(&Debug::pointerto_rawdata), - static_cast>(&Debug::pointerto_rawdata), - "File offset of the debug data") - - .def_property_readonly("has_code_view", - &Debug::has_code_view, - "Whether or not a code view is present") - - .def_property_readonly("code_view", - static_cast(&Debug::code_view), - R"delim( - Return an object which subclass :class:`~lief.PE.CodeView` representing the code view" - The subclassed object can be one of: - - * :class:`~lief.PE.CodeViewPDB` - - If a code view is not present, it is set to None - )delim", - py::return_value_policy::reference) - - .def_property_readonly("has_pogo", - &Debug::has_pogo, - "Whether or not a pogo is present") - - .def_property_readonly("pogo", - static_cast(&Debug::pogo), - R"delim( - Return an object which subclasses :class:`~lief.PE.Pogo` representing the pogo entry. - It returns None if not present. - )delim", - py::return_value_policy::reference) - - .def("__eq__", &Debug::operator==) - .def("__ne__", &Debug::operator!=) - .def("__hash__", - [] (const Debug& debug) { - return Hash::hash(debug); - }) - - .def("__str__", [] (const Debug& debug) - { - std::ostringstream stream; - stream << debug; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyDelayImport.cpp b/vendor/lief/api/python/PE/objects/pyDelayImport.cpp deleted file mode 100644 index cb99b24..0000000 --- a/vendor/lief/api/python/PE/objects/pyDelayImport.cpp +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/DelayImport.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (DelayImport::*)() const; - -template -using setter_t = void (DelayImport::*)(T); - -template -using no_const_getter = T (DelayImport::*)(); - -template -using no_const_func = T (DelayImport::*)(P); - - -template<> -void create(py::module& m) { - py::class_ imp(m, "DelayImport", - R"delim( - Class that represents a PE delay import - )delim"); - - init_ref_iterator(imp, "it_entries"); - - imp - .def(py::init(), - "Constructor from a library name", - "library_name"_a) - - .def_property_readonly("entries", - static_cast>(&DelayImport::entries), - "Iterator over the " RST_CLASS_REF(lief.PE.DelayImportEntry) " (functions)", - py::return_value_policy::reference) - - .def_property("name", - [] (const DelayImport& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DelayImport::name), - "Library name (e.g. ``kernel32.dll``)", - py::return_value_policy::reference_internal) - - .def_property("attribute", - static_cast>(&DelayImport::attribute), - static_cast>(&DelayImport::attribute), - R"delim( - Reserved and **should** be zero according to the PE specifications - )delim") - - .def_property("handle", - static_cast>(&DelayImport::handle), - static_cast>(&DelayImport::handle), - R"delim( - The RVA of the module handle (in the ``.data`` section) - It is used for storage by the routine that is supplied to manage delay-loading. - )delim") - - .def_property("iat", - static_cast>(&DelayImport::iat), - static_cast>(&DelayImport::iat), - R"delim( - RVA of the delay-load import address table. - )delim") - - .def_property("names_table", - static_cast>(&DelayImport::names_table), - static_cast>(&DelayImport::names_table), - R"delim( - RVA of the delay-load import names table. - The content of this table has the layout as the Import lookup table - )delim") - - .def_property("biat", - static_cast>(&DelayImport::biat), - static_cast>(&DelayImport::biat), - R"delim( - RVA of the **bound** delay-load import address table or 0 - if the table does not exist. - )delim") - - - .def_property("uiat", - static_cast>(&DelayImport::uiat), - static_cast>(&DelayImport::uiat), - R"delim( - RVA of the **unload** delay-load import address table or 0 - if the table does not exist. - - According to the PE specifications, this table is an - exact copy of the delay import address table that can be - used to to restore the original IAT the case of unloading. - )delim") - - .def_property("timestamp", - static_cast>(&DelayImport::timestamp), - static_cast>(&DelayImport::timestamp), - R"delim( - The timestamp of the DLL to which this image has been bound. - )delim") - - .def("__eq__", &DelayImport::operator==) - .def("__ne__", &DelayImport::operator!=) - .def("__hash__", - [] (const DelayImport& import) { - return Hash::hash(import); - }) - - - .def("__str__", [] (const DelayImport& import) - { - std::ostringstream stream; - stream << import; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyDelayImportEntry.cpp b/vendor/lief/api/python/PE/objects/pyDelayImportEntry.cpp deleted file mode 100644 index 61e2175..0000000 --- a/vendor/lief/api/python/PE/objects/pyDelayImportEntry.cpp +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/DelayImportEntry.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (DelayImportEntry::*)() const; - -template -using setter_t = void (DelayImportEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "DelayImportEntry", - R"delim( - Class that represents an entry (i.e. a delay import) in the delay import table (:class:`~lief.PE.DelayImport`). - - It extends the :class:`lief.Symbol` generic class that provides the :attr:`lief.Symbol.name` - and :attr:`lief.Symbol.value` - - The meaning of :attr:`lief.Symbol.value` for this PE object is the address (as an RVA) in the IAT - where the resolution should take place - )delim") - .def(py::init<>()) - - .def_property("name", - [] (const DelayImportEntry& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&DelayImportEntry::name), - "Delay import name if not ordinal") - - .def_property("data", - static_cast>(&DelayImportEntry::data), - static_cast>(&DelayImportEntry::data), - "Raw value") - - .def_property_readonly("is_ordinal", - &DelayImportEntry::is_ordinal, - "``True`` if it is an import by ordinal") - - .def_property_readonly("ordinal", - &DelayImportEntry::ordinal, - "Ordinal value (if any). See: :attr:`~lief.PE.DelayImportEntry.is_ordinal`") - - .def_property_readonly("hint", - &DelayImportEntry::hint, - "Index into the :attr:`lief.PE.Export.entries` that is used to speed-up the symbol resolution") - - .def_property_readonly("iat_value", - &DelayImportEntry::iat_value, - R"delim( - Value of the current entry in the delay-loaded import address table. - See: :attr:`~DelayImportEntry.iat` - )delim") - - .def("__eq__", &DelayImportEntry::operator==) - .def("__ne__", &DelayImportEntry::operator!=) - .def("__hash__", - [] (const DelayImportEntry& import_entry) { - return Hash::hash(import_entry); - }) - - .def("__str__", [] (const DelayImportEntry& importEntry) { - std::ostringstream stream; - stream << importEntry; - return stream.str(); - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyDosHeader.cpp b/vendor/lief/api/python/PE/objects/pyDosHeader.cpp deleted file mode 100644 index eddf1c5..0000000 --- a/vendor/lief/api/python/PE/objects/pyDosHeader.cpp +++ /dev/null @@ -1,133 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/DosHeader.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_abs_t = T (DosHeader::*)(void) const; - -template -using setter_abs_t = void (DosHeader::*)(T); - -using getter_t = getter_abs_t; -using setter_t = setter_abs_t; - - -template<> -void create(py::module& m) { - py::class_(m, "DosHeader", - R"delim( - Class which represents the DosHeader, the **first** structure presents at the beginning of a PE file. - - Most of the attributes of this structures are not relevant, except :attr:`~lief.PE.DosHeader.addressof_new_exeheader` - )delim") - .def(py::init<>()) - .def_property("magic", - static_cast(&DosHeader::magic), - static_cast(&DosHeader::magic)) - - .def_property("used_bytes_in_the_last_page", - static_cast(&DosHeader::used_bytes_in_the_last_page), - static_cast(&DosHeader::used_bytes_in_the_last_page)) - - .def_property("file_size_in_pages", - static_cast(&DosHeader::file_size_in_pages), - static_cast(&DosHeader::file_size_in_pages)) - - .def_property("numberof_relocation", - static_cast(&DosHeader::numberof_relocation), - static_cast(&DosHeader::numberof_relocation)) - - .def_property("header_size_in_paragraphs", - static_cast(&DosHeader::header_size_in_paragraphs), - static_cast(&DosHeader::header_size_in_paragraphs)) - - .def_property("minimum_extra_paragraphs", - static_cast(&DosHeader::minimum_extra_paragraphs), - static_cast(&DosHeader::minimum_extra_paragraphs)) - - .def_property("maximum_extra_paragraphs", - static_cast(&DosHeader::maximum_extra_paragraphs), - static_cast(&DosHeader::maximum_extra_paragraphs)) - - .def_property("initial_relative_ss", - static_cast(&DosHeader::initial_relative_ss), - static_cast(&DosHeader::initial_relative_ss)) - - .def_property("initial_sp", - static_cast(&DosHeader::initial_sp), - static_cast(&DosHeader::initial_sp)) - - .def_property("checksum", - static_cast(&DosHeader::checksum), - static_cast(&DosHeader::checksum)) - - .def_property("initial_ip", - static_cast(&DosHeader::initial_ip), - static_cast(&DosHeader::initial_ip)) - - .def_property("initial_relative_cs", - static_cast(&DosHeader::initial_relative_cs), - static_cast(&DosHeader::initial_relative_cs)) - - .def_property("addressof_relocation_table", - static_cast(&DosHeader::addressof_relocation_table), - static_cast(&DosHeader::addressof_relocation_table)) - - .def_property("overlay_number", - static_cast(&DosHeader::overlay_number), - static_cast(&DosHeader::overlay_number)) - - .def_property("oem_id", - static_cast(&DosHeader::oem_id), - static_cast(&DosHeader::oem_id)) - - .def_property("oem_info", - static_cast(&DosHeader::oem_info), - static_cast(&DosHeader::oem_info)) - - .def_property("addressof_new_exeheader", - static_cast>(&DosHeader::addressof_new_exeheader), - static_cast>(&DosHeader::addressof_new_exeheader)) - - - .def("__eq__", &DosHeader::operator==) - .def("__ne__", &DosHeader::operator!=) - .def("__hash__", - [] (const DosHeader& dos_header) { - return Hash::hash(dos_header); - }) - - .def("__str__", [] (const DosHeader& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); - -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyExport.cpp b/vendor/lief/api/python/PE/objects/pyExport.cpp deleted file mode 100644 index 22397bd..0000000 --- a/vendor/lief/api/python/PE/objects/pyExport.cpp +++ /dev/null @@ -1,105 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Export.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Export::*)(void) const; - -template -using setter_t = void (Export::*)(T); - -template -using no_const_getter = T (Export::*)(void); - - -template<> -void create(py::module& m) { - py::class_ exp(m, "Export", - R"delim( - Class which represents a PE Export - )delim"); - - init_ref_iterator(exp, "it_entries"); - - exp - .def(py::init<>()) - - .def_property("name", - [] (const Export& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&Export::name), - "The name of the library exported (e.g. ``KERNEL32.dll``)") - - .def_property("export_flags", - static_cast>(&Export::export_flags), - static_cast>(&Export::export_flags), - "According to the PE specifications this value is reserved and should be set to 0") - - .def_property("timestamp", - static_cast>(&Export::timestamp), - static_cast>(&Export::timestamp), - "The time and date that the export data was created") - - .def_property("major_version", - static_cast>(&Export::major_version), - static_cast>(&Export::major_version), - "The major version number (can be user-defined)") - - .def_property("minor_version", - static_cast>(&Export::minor_version), - static_cast>(&Export::minor_version), - "The minor version number (can be user-defined)") - - .def_property("ordinal_base", - static_cast>(&Export::ordinal_base), - static_cast>(&Export::ordinal_base), - "The starting number for the exports. Usually this value is set to 1") - - .def_property_readonly("entries", - static_cast>(&Export::entries), - "Iterator over the " RST_CLASS_REF(lief.PE.ExportEntry) "", - py::return_value_policy::reference_internal) - - - .def("__eq__", &Export::operator==) - .def("__ne__", &Export::operator!=) - .def("__hash__", - [] (const Export& export_) { - return Hash::hash(export_); - }) - - .def("__str__", [] (const Export& export_) - { - std::ostringstream stream; - stream << export_; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyExportEntry.cpp b/vendor/lief/api/python/PE/objects/pyExportEntry.cpp deleted file mode 100644 index 6713ffe..0000000 --- a/vendor/lief/api/python/PE/objects/pyExportEntry.cpp +++ /dev/null @@ -1,98 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/ExportEntry.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ExportEntry::*)(void) const; - -template -using setter_t = void (ExportEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_ export_entry(m, "ExportEntry", - R"delim( - Class which represents a PE Export entry (cf. :class:`lief.PE.Export`) - )delim"); - - py::class_(export_entry, "forward_information_t") - .def_readwrite("library", &ExportEntry::forward_information_t::library) - .def_readwrite("function", &ExportEntry::forward_information_t::function) - - .def("__str__", [] (const ExportEntry::forward_information_t& info) - { - std::ostringstream stream; - stream << info; - return stream.str(); - }); - - export_entry - .def(py::init<>()) - - .def_property("name", - [] (const ExportEntry& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&ExportEntry::name)) - - .def_property("ordinal", - static_cast>(&ExportEntry::ordinal), - static_cast>(&ExportEntry::ordinal)) - - .def_property("address", - static_cast>(&ExportEntry::address), - static_cast>(&ExportEntry::address)) - - .def_property("is_extern", - static_cast>(&ExportEntry::is_extern), - static_cast>(&ExportEntry::is_extern)) - - .def_property_readonly("is_forwarded", - &ExportEntry::is_forwarded) - - .def_property_readonly("forward_information", - &ExportEntry::forward_information) - - .def_property_readonly("function_rva", - &ExportEntry::function_rva) - - .def("__eq__", &ExportEntry::operator==) - .def("__ne__", &ExportEntry::operator!=) - .def("__hash__", - [] (const ExportEntry& export_entry) { - return Hash::hash(export_entry); - }) - - .def("__str__", [] (const ExportEntry& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyHeader.cpp b/vendor/lief/api/python/PE/objects/pyHeader.cpp deleted file mode 100644 index bef9b4e..0000000 --- a/vendor/lief/api/python/PE/objects/pyHeader.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Header.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - - -template<> -void create
(py::module& m) { - py::class_(m, "Header", - R"delim( - Class that represents the PE header (which follows the :class:`lief.PE.DosHeader`) - )delim") - .def(py::init<>()) - - .def_property("signature", - static_cast>(&Header::signature), - static_cast>(&Header::signature), - "Signature (or magic byte) of the header. It must be: ``PE\\0\\0``") - - .def_property("machine", - static_cast>(&Header::machine), - static_cast>(&Header::machine), - "The target machine architecture: " RST_CLASS_REF(lief.PE.MACHINE_TYPES) "") - - .def_property("numberof_sections", - static_cast>(&Header::numberof_sections), - static_cast>(&Header::numberof_sections), - "Number of sections in the binary") - - .def_property("time_date_stamps", - static_cast>(&Header::time_date_stamp), - static_cast>(&Header::time_date_stamp), - "The low 32 bits of the number of seconds since 00:00 January 1, 1970 that indicates when the file was created.") - - .def_property("pointerto_symbol_table", - static_cast>(&Header::pointerto_symbol_table), - static_cast>(&Header::pointerto_symbol_table), - R"delim( - The file offset of the COFF symbol table, or zero if no COFF symbol table is present. - - This value should be zero for an image because COFF debugging information is deprecated. - )delim") - - .def_property("numberof_symbols", - static_cast>(&Header::numberof_symbols), - static_cast>(&Header::numberof_symbols), - R"delim( - The number of entries in the symbol table. This data can be used to locate the string table - which immediately follows the symbol table. - - This value should be zero for an image because COFF debugging information is deprecated. - )delim") - - .def_property("sizeof_optional_header", - static_cast>(&Header::sizeof_optional_header), - static_cast>(&Header::sizeof_optional_header), - R"delim( - Size of the :class:`~lief.PE.OptionalHeader` **AND** the data directories which follows this header. - - This value is equivalent to: ``sizeof(pe_optional_header) + NB_DATA_DIR * sizeof(data_directory)`` - - This size **should** be either: - - * 0xE0 (224) for a PE32 (32 bits) - * 0xF0 (240) for a PE32+ (64 bits) - )delim") - - .def_property("characteristics", - static_cast>(&Header::characteristics), - static_cast>(&Header::characteristics), - "The " RST_CLASS_REF(lief.PE.HEADER_CHARACTERISTICS) " that indicate the attributes of the file.") - - .def("has_characteristic", - &Header::has_characteristic, - "``True`` if the header has the given " RST_CLASS_REF(lief.PE.HEADER_CHARACTERISTICS) "", - "characteristic"_a) - - .def("add_characteristic", - &Header::add_characteristic, - "Add the given " RST_CLASS_REF(lief.PE.HEADER_CHARACTERISTICS) " to the header", - "characteristic"_a) - - .def("remove_characteristic", - &Header::remove_characteristic, - "Remove the given " RST_CLASS_REF(lief.PE.HEADER_CHARACTERISTICS) " from the header", - "characteristic"_a) - - .def_property_readonly("characteristics_list", - &Header::characteristics_list, - "Return the " RST_CLASS_REF(lief.PE.HEADER_CHARACTERISTICS) " as a ``list``") - - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - - .def("__str__", [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyImport.cpp b/vendor/lief/api/python/PE/objects/pyImport.cpp deleted file mode 100644 index b0cceab..0000000 --- a/vendor/lief/api/python/PE/objects/pyImport.cpp +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" -#include "pyErr.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Import.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Import::*)(void) const; - -template -using setter_t = void (Import::*)(T); - -template -using no_const_getter = T (Import::*)(void); - -template -using no_const_func = T (Import::*)(P); - - -template<> -void create(py::module& m) { - py::class_ imp(m, "Import", - R"delim( - Class that represents a PE import - )delim"); - - init_ref_iterator(imp, "it_entries"); - - imp - .def(py::init<>(), - "Default constructor") - - .def(py::init(), - "Constructor from a library name", - "library_name"_a) - - .def_property_readonly("forwarder_chain", - &Import::forwarder_chain, - "The index of the first forwarder reference") - - .def_property_readonly("timedatestamp", - &Import::timedatestamp, - R"delim( - The stamp that is set to zero until the image is bound. - - After the image is bound, this field is set to the time/data stamp of the DLL - )delim") - - .def_property_readonly("entries", - static_cast>(&Import::entries), - "Iterator over the " RST_CLASS_REF(lief.PE.ImportEntry) " (functions)", - py::return_value_policy::reference) - - .def_property("name", - [] (const Import& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&Import::name), - "Library name (e.g. ``kernel32.dll``)", - py::return_value_policy::reference) - - .def_property_readonly("directory", - static_cast>(&Import::directory), - R"delim( - Return the :class:`~lief.PE.DataDirectory` associated with this import. - - It should be the one at index :attr:`lief.PE.DATA_DIRECTORY.IMPORT_TABLE`. - It can return None if the Import directory can't be resolved. - )delim", - py::return_value_policy::reference) - - .def_property_readonly("iat_directory", - static_cast>(&Import::iat_directory), - R"delim( - Return the :class:`~lief.PE.DataDirectory` associated with the ``IAT`` table. - - It should be the one at index :attr:`lief.PE.DATA_DIRECTORY.IAT`. It can - return None if the IAT directory can't be resolved. - )delim", - py::return_value_policy::reference) - - .def_property("import_address_table_rva", - static_cast>(&Import::import_address_table_rva), - static_cast>(&Import::import_address_table_rva), - R"delim( - The RVA of the import address table (``IAT``). The content of this - table is **identical** to the content of the Import Lookup Table (``ILT``) - until the image is bound. - - .. warning:: - - This address could change when re-building the binary - )delim") - - .def_property("import_lookup_table_rva", - static_cast>(&Import::import_lookup_table_rva), - static_cast>(&Import::import_lookup_table_rva), - R"delim( - The RVA of the import lookup table. This table - contains the :attr:`~lief.PE.ImportEntry.name` or the :attr:`~lief.PE.ImportEntry.ordinal` - for all the imports. - )delim") - - .def("get_function_rva_from_iat", - [] (const Import& self, const std::string& name) { - return error_or(&Import::get_function_rva_from_iat, self, name); - }, - "Return the relative virtual address of the given function within the *Import Address Table*", - "function_name"_a) - - .def("add_entry", - static_cast(&Import::add_entry), - "Add an " RST_CLASS_REF(lief.PE.ImportEntry) " (function) to the current import", - "entry"_a, - py::return_value_policy::reference) - - .def("add_entry", - static_cast(&Import::add_entry), - "Add an " RST_CLASS_REF(lief.PE.ImportEntry) " (function) to the current import", - "function_name"_a, - py::return_value_policy::reference) - - .def("get_entry", - static_cast>(&Import::get_entry), - "Return the " RST_CLASS_REF(lief.PE.ImportEntry) " with the given name or None if not found", - "function_name"_a, - py::return_value_policy::reference) - - - .def("__eq__", &Import::operator==) - .def("__ne__", &Import::operator!=) - .def("__hash__", - [] (const Import& import) { - return Hash::hash(import); - }) - - - .def("__str__", [] (const Import& import) - { - std::ostringstream stream; - stream << import; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyImportEntry.cpp b/vendor/lief/api/python/PE/objects/pyImportEntry.cpp deleted file mode 100644 index 595c919..0000000 --- a/vendor/lief/api/python/PE/objects/pyImportEntry.cpp +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/ImportEntry.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ImportEntry::*)(void) const; - -template -using setter_t = void (ImportEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ImportEntry", - R"delim( - Class that represents an entry (i.e. an import) in the import table (:class:`~lief.PE.Import`). - - It extends the :class:`lief.Symbol` generic class that provides the :attr:`lief.Symbol.name` - and :attr:`lief.Symbol.value` - )delim") - .def(py::init<>()) - - .def(py::init(), - "Constructor from a :attr:`~lief.PE.ImportEntry.name`", - "import_name"_a) - - .def(py::init(), - "Constructor from a :attr:`~lief.PE.ImportEntry.data` and an optionally :attr:`~lief.PE.ImportEntry.name`", - "data"_a, "name"_a = "") - - .def_property("name", - [] (const ImportEntry& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&ImportEntry::name), - "Import name if not ordinal") - - .def_property("data", - static_cast>(&ImportEntry::data), - static_cast>(&ImportEntry::data), - "Raw value") - - .def_property_readonly("is_ordinal", - &ImportEntry::is_ordinal, - "``True`` if it is an import by ordinal") - - .def_property_readonly("ordinal", - &ImportEntry::ordinal, - "Ordinal value (if any). See: :attr:`~lief.PE.ImportEntry.is_ordinal`") - - .def_property_readonly("hint", - &ImportEntry::hint, - "Index into the :attr:`lief.PE.Export.entries` that is used to speed-up the symbol resolution") - - .def_property_readonly("iat_value", - &ImportEntry::iat_value, - "Value of the current entry in the Import Address Table. It should match the lookup table value.") - - .def_property_readonly("iat_address", - &ImportEntry::iat_address, - "**Original** address of the entry in the Import Address Table") - - - .def("__eq__", &ImportEntry::operator==) - .def("__ne__", &ImportEntry::operator!=) - .def("__hash__", - [] (const ImportEntry& import_entry) { - return Hash::hash(import_entry); - }) - - .def("__str__", [] (const ImportEntry& importEntry) - { - std::ostringstream stream; - stream << importEntry; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyOptionalHeader.cpp b/vendor/lief/api/python/PE/objects/pyOptionalHeader.cpp deleted file mode 100644 index 42fff1c..0000000 --- a/vendor/lief/api/python/PE/objects/pyOptionalHeader.cpp +++ /dev/null @@ -1,312 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/OptionalHeader.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (OptionalHeader::*)(void) const; - -template -using setter_t = void (OptionalHeader::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "OptionalHeader", - R"delim( - Class which represents the PE OptionalHeader structure.. - )delim") - .def(py::init<>()) - .def_property("magic", - static_cast>(&OptionalHeader::magic), - static_cast>(&OptionalHeader::magic), - "Magic value (" RST_CLASS_REF(lief.PE.PE_TYPE) ") that identifies a ``PE32`` from a ``PE64``") - - .def_property("major_linker_version", - static_cast>(&OptionalHeader::major_linker_version), - static_cast>(&OptionalHeader::major_linker_version), - "The linker major version number") - - .def_property("minor_linker_version", - static_cast>(&OptionalHeader::minor_linker_version), - static_cast>(&OptionalHeader::minor_linker_version), - "The linker minor version number") - - .def_property("sizeof_code", - static_cast>(&OptionalHeader::sizeof_code), - static_cast>(&OptionalHeader::sizeof_code), - R"delim( - The size of the code ``.text`` section or the sum of - all the sections that contain code (ie. :class:`~lief.PE.Section` with the flag :attr:`~lief.PE.SECTION_CHARACTERISTICS.CNT_CODE`) - )delim") - - .def_property("sizeof_initialized_data", - static_cast>(&OptionalHeader::sizeof_initialized_data), - static_cast>(&OptionalHeader::sizeof_initialized_data), - R"delim( - The size of the initialized data which are usually located in the ``.data`` section. - If the initialized data are split across multiple sections, it is the sum of the sections. - - The sections associated with the initialized data are usually identified with the - flag :attr:`~lief.PE.SECTION_CHARACTERISTICS.CNT_INITIALIZED_DATA` - )delim") - - .def_property("sizeof_uninitialized_data", - static_cast>(&OptionalHeader::sizeof_uninitialized_data), - static_cast>(&OptionalHeader::sizeof_uninitialized_data), - R"delim( - The size of the uninitialized data which are usually located in the ``.bss`` section. - If the uninitialized data are split across multiple sections, it is the sum of the sections. - - The sections associated with the uninitialized data are usually identified with the - flag :attr:`~lief.PE.SECTION_CHARACTERISTICS.CNT_UNINITIALIZED_DATA` - )delim") - - .def_property("addressof_entrypoint", - static_cast>(&OptionalHeader::addressof_entrypoint), - static_cast>(&OptionalHeader::addressof_entrypoint), - R"delim( - The address of the entry point relative to the image base when the executable file is - loaded into memory. For program images, this is the starting address. For device - drivers, this is the address of the initialization function. - - An entry point is optional for DLLs. When no entry point is present, this field must be zero. - )delim") - - .def_property("baseof_code", - static_cast>(&OptionalHeader::baseof_code), - static_cast>(&OptionalHeader::baseof_code), - "Address relative to the imagebase where the binary's code starts") - - .def_property("baseof_data", - static_cast>(&OptionalHeader::baseof_data), - static_cast>(&OptionalHeader::baseof_data), - R"delim( - Address relative to the imagebase where the binary's data starts. - - .. warning:: - - This value is not present for ``PE64`` files - - )delim") - - .def_property("imagebase", - static_cast>(&OptionalHeader::imagebase), - static_cast>(&OptionalHeader::imagebase), - "The preferred base address when mapping the binary in memory") - - .def_property("section_alignment", - static_cast>(&OptionalHeader::section_alignment), - static_cast>(&OptionalHeader::section_alignment), - R"delim( - The alignment (in bytes) of sections when they are loaded into memory. - It must be greater than or equal to :attr:`~lief.PE.OptionalHeader.file_alignment` and - the default is the page size for the architecture. - )delim") - - .def_property("file_alignment", - static_cast>(&OptionalHeader::file_alignment), - static_cast>(&OptionalHeader::file_alignment), - R"delim( - The alignment factor (in bytes) that is used to align the raw data of - sections in the image file. - The value should be a **power of 2** between 512 and 64K, inclusive. - The default value is 512. - If the :attr:`~lief.PE.OptionalHeader.section_alignment` is less than the architecture's page size, - then :attr:`~lief.PE.OptionalHeader.file_alignment` must match :attr:`~lief.PE.OptionalHeader.section_alignment`. - )delim") - - - .def_property("major_operating_system_version", - static_cast>(&OptionalHeader::major_operating_system_version), - static_cast>(&OptionalHeader::major_operating_system_version), - "The major version number of the required operating system.") - - .def_property("minor_operating_system_version", - static_cast>(&OptionalHeader::minor_operating_system_version), - static_cast>(&OptionalHeader::minor_operating_system_version), - "The minor version number of the required operating system.") - - .def_property("major_image_version", - static_cast>(&OptionalHeader::major_image_version), - static_cast>(&OptionalHeader::major_image_version), - "The major version number of the image.") - - .def_property("minor_image_version", - static_cast>(&OptionalHeader::minor_image_version), - static_cast>(&OptionalHeader::minor_image_version), - "The minor version number of the image.") - - .def_property("major_subsystem_version", - static_cast>(&OptionalHeader::major_subsystem_version), - static_cast>(&OptionalHeader::major_subsystem_version), - "The major version number of the subsystem.") - - .def_property("minor_subsystem_version", - static_cast>(&OptionalHeader::minor_subsystem_version), - static_cast>(&OptionalHeader::minor_subsystem_version), - "The minor version number of the subsystem") - - .def_property("win32_version_value", - static_cast>(&OptionalHeader::win32_version_value), - static_cast>(&OptionalHeader::win32_version_value), - "Reserved, must be zero.") - - .def_property("sizeof_image", - static_cast>(&OptionalHeader::sizeof_image), - static_cast>(&OptionalHeader::sizeof_image), - R"delim( - The size (in bytes) of the image, including all headers, as the image is loaded in memory. - It must be a multiple of :attr:`~lief.PE.OptionalHeader.section_alignment` and should match :attr:`~lief.PE.Binary.virtual_size`. - )delim") - - .def_property("sizeof_headers", - static_cast>(&OptionalHeader::sizeof_headers), - static_cast>(&OptionalHeader::sizeof_headers), - R"delim( - The combined size of an MS-DOS stub, PE header, and section headers rounded up - to a multiple of :attr:`~lief.PE.OptionalHeader.file_alignment`. - )delim") - - .def_property("checksum", - static_cast>(&OptionalHeader::checksum), - static_cast>(&OptionalHeader::checksum), - R"delim( - The image file checksum. The algorithm for computing the checksum is incorporated into ``IMAGHELP.DLL``. - The following are checked for validation at load time all **drivers**, any **DLL loaded at boot** - time, and any **DLL** that is loaded into a **critical** Windows process. - )delim") - - - .def_property_readonly("computed_checksum", - &OptionalHeader::computed_checksum, - R"delim( - The re-computed value of the :attr:`~lief.PE.OptionalHeader.checksum`. - If both values do not match, it could mean that the binary has been modified - after the compilation. - - This value is computed by LIEF when parsing the PE binary. - )delim") - - .def_property("subsystem", - static_cast>(&OptionalHeader::subsystem), - static_cast>(&OptionalHeader::subsystem), - R"delim( - Target subsystem (:class:`~lief.PE.SUBSYSTEM`) like Driver, XBox, Windows GUI, .. - )delim") - - .def_property("dll_characteristics", - static_cast>(&OptionalHeader::dll_characteristics), - static_cast>(&OptionalHeader::dll_characteristics), - R"delim( - Some characteristics (:class:`~lief.PE.DLL_CHARACTERISTICS`) of the underlying binary like the support of the PIE. - - The prefix ``dll`` comes from the official PE specifications but these characteristics - are also used for **executables** - )delim") - - .def("add", - static_cast(&OptionalHeader::add), - "Add the given " RST_CLASS_REF(lief.PE.DLL_CHARACTERISTICS) "", - "characteristic"_a) - - .def("remove", - static_cast(&OptionalHeader::remove), - "Remove the given " RST_CLASS_REF(lief.PE.DLL_CHARACTERISTICS) "", - "characteristic"_a) - - .def_property_readonly("dll_characteristics_lists", - &OptionalHeader::dll_characteristics_list, - ":attr:`~lief.PE.OptionalHeader.dll_characteristics` as a list of " RST_CLASS_REF(lief.PE.DLL_CHARACTERISTICS) "") - - .def("has", - static_cast(&OptionalHeader::has), - "``True`` if the given " RST_CLASS_REF(lief.PE.DLL_CHARACTERISTICS) " is in the " - ":attr:`~lief.PE.OptionalHeader.dll_characteristics`", - "characteristics"_a) - - .def_property("sizeof_stack_reserve", - static_cast>(&OptionalHeader::sizeof_stack_reserve), - static_cast>(&OptionalHeader::sizeof_stack_reserve), - R"delim( - The size of the stack to reserve. - - Only :attr:`~lief.PE.OptionalHeader.sizeof_stack_commit` is committed, the rest is made - available one page at a time until the reserve size is reached. - )delim") - - .def_property("sizeof_stack_commit", - static_cast>(&OptionalHeader::sizeof_stack_commit), - static_cast>(&OptionalHeader::sizeof_stack_commit), - "The size of the stack to commit.") - - .def_property("sizeof_heap_reserve", - static_cast>(&OptionalHeader::sizeof_heap_reserve), - static_cast>(&OptionalHeader::sizeof_heap_reserve), - R"delim( - The size of the local heap space to reserve. - - Only :attr:`~lief.PE.OptionalHeader.sizeof_heap_commit` is available one page at a time until - the reserve size is reached. - )delim") - - .def_property("sizeof_heap_commit", - static_cast>(&OptionalHeader::sizeof_heap_commit), - static_cast>(&OptionalHeader::sizeof_heap_commit), - "The size of the local heap space to commit.") - - .def_property("loader_flags", - static_cast>(&OptionalHeader::loader_flags), - static_cast>(&OptionalHeader::loader_flags), - "According to the PE specifications, this value is *reserved* and **should** be 0.") - - .def_property("numberof_rva_and_size", - static_cast>(&OptionalHeader::numberof_rva_and_size), - static_cast>(&OptionalHeader::numberof_rva_and_size), - "The number of " RST_CLASS_REF(lief.PE.DataDirectory) " that follow this header") - - .def("__eq__", &OptionalHeader::operator==) - .def("__ne__", &OptionalHeader::operator!=) - .def("__hash__", - [] (const OptionalHeader& optional_header) { - return Hash::hash(optional_header); - }) - - .def(py::self += DLL_CHARACTERISTICS()) - .def(py::self -= DLL_CHARACTERISTICS()) - - .def("__contains__", - static_cast(&OptionalHeader::has), - "Check if the given " RST_CLASS_REF(lief.PE.DLL_CHARACTERISTICS) " is present") - - .def("__str__", [] (const OptionalHeader& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyParser.cpp b/vendor/lief/api/python/PE/objects/pyParser.cpp deleted file mode 100644 index 424feec..0000000 --- a/vendor/lief/api/python/PE/objects/pyParser.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/Parser.hpp" - -#include - -namespace LIEF { -namespace PE { - -template<> -void create(py::module& m) { - - m.def("parse", - static_cast (*) (const std::string&)>(&Parser::parse), - "Parse the PE binary from the given **file path** and return a " RST_CLASS_REF(lief.PE.Binary) " object", - "filename"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast (*) (std::vector, const std::string&)>(&Parser::parse), - "Parse the PE binary from the given **list of bytes** and return a :class:`lief.PE.Binary` object", - "raw"_a, "name"_a = "", - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str)) - }; - - return LIEF::PE::Parser::parse(std::move(raw), name); - }, - "Parse the PE binary from the given Python IO interface and return a :class:`lief.PE.Binary` object", - "io"_a, "name"_a = "", - py::return_value_policy::take_ownership); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyPogo.cpp b/vendor/lief/api/python/PE/objects/pyPogo.cpp deleted file mode 100644 index 793575d..0000000 --- a/vendor/lief/api/python/PE/objects/pyPogo.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Pogo.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Pogo::*)(void) const; - -template -using setter_t = void (Pogo::*)(T); - -template -using no_const_getter = T (Pogo::*)(void); - -template<> -void create(py::module& m) { - py::class_ pogo(m, "Pogo"); - - init_ref_iterator(pogo, "it_entries"); - - pogo - .def(py::init<>()) - - .def_property_readonly("entries", - static_cast>(&Pogo::entries), - py::return_value_policy::reference_internal) - - .def_property_readonly("signature", - static_cast>(&Pogo::signature), - "Type of the pogo (" RST_CLASS_REF(lief.PE.POGO_SIGNATURES) ")") - - - .def("__eq__", &Pogo::operator==) - .def("__ne__", &Pogo::operator!=) - .def("__hash__", - [] (const Pogo& pogo_entry) { - return Hash::hash(pogo_entry); - }) - - .def("__str__", [] (const Pogo& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyPogoEntry.cpp b/vendor/lief/api/python/PE/objects/pyPogoEntry.cpp deleted file mode 100644 index c782e5f..0000000 --- a/vendor/lief/api/python/PE/objects/pyPogoEntry.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/PogoEntry.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (PogoEntry::*)(void) const; - -template -using setter_t = void (PogoEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "PogoEntry") - .def(py::init<>()) - - .def_property("name", - [] (const PogoEntry& obj) { - return safe_string_converter(obj.name()); - }, - static_cast>(&PogoEntry::name)) - - .def_property("start_rva", - static_cast>(&PogoEntry::start_rva), - static_cast>(&PogoEntry::start_rva)) - - .def_property("size", - static_cast>(&PogoEntry::size), - static_cast>(&PogoEntry::size)) - - - .def("__eq__", &PogoEntry::operator==) - .def("__ne__", &PogoEntry::operator!=) - .def("__hash__", - [] (const PogoEntry& pogo_entry) { - return Hash::hash(pogo_entry); - }) - - .def("__str__", [] (const PogoEntry& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyRelocation.cpp b/vendor/lief/api/python/PE/objects/pyRelocation.cpp deleted file mode 100644 index 7bb4f1f..0000000 --- a/vendor/lief/api/python/PE/objects/pyRelocation.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Relocation.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Relocation::*)(void) const; - -template -using setter_t = void (Relocation::*)(T); - -template -using it_t = T (Relocation::*)(void); - -template<> -void create(py::module& m) { - py::class_ reloc(m, "Relocation", - R"delim( - Class which represents the *Base Relocation Block* - Usually, we find this structure in the ``.reloc`` section - )delim"); - - init_ref_iterator(reloc, "it_entries"); - - reloc - .def(py::init<>()) - - .def_property("virtual_address", - static_cast>(&Relocation::virtual_address), - static_cast>(&Relocation::virtual_address), - "The RVA for which the offset of the relocation entries (RelocationEntry) is added") - - .def_property("block_size", - static_cast>(&Relocation::block_size), - static_cast>(&Relocation::block_size), - R"delim( - The total number of bytes in the base relocation block. - ``block_size = sizeof(BaseRelocationBlock) + nb_of_relocs * sizeof(uint16_t = RelocationEntry)`` - )delim") - - .def_property_readonly("entries", - static_cast>(&Relocation::entries), - "Iterator over the " RST_CLASS_REF(lief.PE.RelocationEntry) "") - - .def("add_entry", - &Relocation::add_entry, - "Add a new " RST_CLASS_REF(lief.PE.RelocationEntry) "", - "new_entry"_a) - - - .def("__eq__", &Relocation::operator==) - .def("__ne__", &Relocation::operator!=) - .def("__hash__", - [] (const Relocation& relocation) { - return Hash::hash(relocation); - }) - - .def("__str__", [] (const Relocation& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/pyRelocationEntry.cpp b/vendor/lief/api/python/PE/objects/pyRelocationEntry.cpp deleted file mode 100644 index 671b04b..0000000 --- a/vendor/lief/api/python/PE/objects/pyRelocationEntry.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/RelocationEntry.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (RelocationEntry::*)(void) const; - -template -using setter_t = void (RelocationEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "RelocationEntry", - R"delim( - Class which represents an entry of the PE relocation table. - - It extends the :class:`lief.Relocation` object to provide an uniform API across the file formats - )delim") - .def(py::init<>()) - - .def_property("data", - static_cast>(&RelocationEntry::data), - static_cast>(&RelocationEntry::data), - R"delim( - Raw data of the relocation: - - * The **high** 4 bits store the relocation :attr:`~lief.PE.RelocationEntry.type` - * The **low** 12 bits store the relocation offset (:attr:`~lief.PE.RelocationEntry.position`) - )delim") - - .def_property("position", - static_cast>(&RelocationEntry::position), - static_cast>(&RelocationEntry::position), - "Offset - relative to :attr:`~lief.PE.Relocation.virtual_address` - where the relocation occurs") - - .def_property("type", - static_cast>(&RelocationEntry::type), - static_cast>(&RelocationEntry::type), - "Type of the relocation (see: " RST_CLASS_REF(lief.PE.RELOCATIONS_BASE_TYPES) ")") - - - .def("__eq__", &RelocationEntry::operator==) - .def("__ne__", &RelocationEntry::operator!=) - .def("__hash__", - [] (const RelocationEntry& relocation_entry) { - return Hash::hash(relocation_entry); - }) - - .def("__str__", [] (const RelocationEntry& relocation) - { - std::ostringstream stream; - stream << relocation; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyResourceData.cpp b/vendor/lief/api/python/PE/objects/pyResourceData.cpp deleted file mode 100644 index cf6031c..0000000 --- a/vendor/lief/api/python/PE/objects/pyResourceData.cpp +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/ResourceData.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceData::*)(void) const; - -template -using setter_t = void (ResourceData::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceData", - R"delim( - Class which represents a Data Node in the PE resources tree - )delim") - .def(py::init<>(), - "Default constructor") - - .def(py::init&, uint32_t>(), - "content"_a, "code_page"_a) - - .def_property("code_page", - static_cast>(&ResourceData::code_page), - static_cast>(&ResourceData::code_page), - R"delim( - Return the code page that is used to decode code point - values within the resource data. Typically, the code page is the Unicode code page. - )delim") - - .def_property("content", - static_cast&>>(&ResourceData::content), - static_cast&>>(&ResourceData::content), - "Resource content") - - .def_property("reserved", - static_cast>(&ResourceData::reserved), - static_cast>(&ResourceData::reserved), - "Reserved value. Should be ``0``") - - .def_property_readonly("offset", - &ResourceData::offset, - R"delim( - Offset of the content within the resource - - .. warning:: - - This value can change when re-building the resource table - )delim") - - .def("__eq__", &ResourceData::operator==) - .def("__ne__", &ResourceData::operator!=) - - .def("__hash__", - [] (const ResourceData& node) { - return Hash::hash(node); - }) - - .def("__str__", - [] (const ResourceData& data) { - std::ostringstream stream; - stream << data; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyResourceDirectory.cpp b/vendor/lief/api/python/PE/objects/pyResourceDirectory.cpp deleted file mode 100644 index 648fd73..0000000 --- a/vendor/lief/api/python/PE/objects/pyResourceDirectory.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/ResourceDirectory.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceDirectory::*)(void) const; - -template -using setter_t = void (ResourceDirectory::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceDirectory") - .def(py::init<>(), - "Default constructor") - - .def_property("characteristics", - static_cast>(&ResourceDirectory::characteristics), - static_cast>(&ResourceDirectory::characteristics), - "Resource characteristics. This field is reserved for future use. " - "It is currently set to zero.") - - .def_property("time_date_stamp", - static_cast>(&ResourceDirectory::time_date_stamp), - static_cast>(&ResourceDirectory::time_date_stamp), - "The time that the resource data was created by the " - "resource compiler.") - - .def_property("major_version", - static_cast>(&ResourceDirectory::major_version), - static_cast>(&ResourceDirectory::major_version), - "The major version number, set by the user.") - - .def_property("minor_version", - static_cast>(&ResourceDirectory::minor_version), - static_cast>(&ResourceDirectory::minor_version), - "The minor version number, set by the user.") - - .def_property("numberof_name_entries", - static_cast>(&ResourceDirectory::numberof_name_entries), - static_cast>(&ResourceDirectory::numberof_name_entries), - "The number of directory entries immediately " - "following the table that use strings to identify Type, " - "Name, or Language entries (depending on the level " - "of the table") - - .def_property("numberof_id_entries", - static_cast>(&ResourceDirectory::numberof_id_entries), - static_cast>(&ResourceDirectory::numberof_id_entries), - "The number of directory entries immediately " - "following the Name entries that use numeric IDs for " - "Type, Name, or Language entries.") - - - .def("__eq__", &ResourceDirectory::operator==) - .def("__ne__", &ResourceDirectory::operator!=) - - .def("__hash__", - [] (const ResourceDirectory& node) { - return Hash::hash(node); - }) - - .def("__str__", - [] (const ResourceDirectory& directory) { - std::ostringstream stream; - stream << directory; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyResourceNode.cpp b/vendor/lief/api/python/PE/objects/pyResourceNode.cpp deleted file mode 100644 index be94d6d..0000000 --- a/vendor/lief/api/python/PE/objects/pyResourceNode.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/utils.hpp" -#include "LIEF/PE/ResourceNode.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceNode::*)(void) const; - -template -using setter_t = void (ResourceNode::*)(T); - - -template<> -void create(py::module& m) { - py::class_ res_node(m, "ResourceNode", - R"delim( - Class which represents a Node in the resource tree. - It is extended by :class:`lief.PE.ResourceData` and :class:`lief.PE.ResourceNode` - )delim"); - - init_ref_iterator(res_node, "it_childs"); - - res_node - .def_property("id", - static_cast>(&ResourceNode::id), - static_cast>(&ResourceNode::id), - "Integer that identifies the Type, Name, or " - "Language ID entry.") - - .def_property_readonly("is_directory", - &ResourceNode::is_directory, - "``True`` if the current resource is a " RST_CLASS_REF(lief.PE.ResourceDirectory) "") - - .def_property_readonly("is_data", - &ResourceNode::is_data, - "``True`` if the current resource is a " RST_CLASS_REF(lief.PE.ResourceData) "") - - .def_property_readonly("has_name", - &ResourceNode::has_name, - "``True`` if the current resource uses a name") - - .def_property("name", - [] (const ResourceNode& node) { - return safe_string_converter(LIEF::u16tou8(node.name())); - }, - static_cast(&ResourceNode::name), - "Resource's name") - - .def_property_readonly("childs", - static_cast(&ResourceNode::childs), - "Node's childs") - - .def("add_directory_node", - static_cast(&ResourceNode::add_child), - "Add a " RST_CLASS_REF(lief.PE.ResourceDirectory) " to the current node", - "resource_directory"_a, - py::return_value_policy::reference) - - .def("add_data_node", - static_cast(&ResourceNode::add_child), - "Add a " RST_CLASS_REF(lief.PE.ResourceData) " to the current node", - "resource_data"_a, - py::return_value_policy::reference) - - .def("delete_child", - static_cast(&ResourceNode::delete_child), - "Delete the given " RST_CLASS_REF(lief.PE.ResourceNode) " from childs", - "node"_a) - - .def("delete_child", - static_cast(&ResourceNode::delete_child), - "Delete the " RST_CLASS_REF(lief.PE.ResourceNode) " with the given :attr:`~lief.PE.ResourceNode.id` from childs", - "id"_a) - - .def_property_readonly("depth", - &ResourceNode::depth, - "Current depth of the entry in the resource tree") - - .def("__eq__", &ResourceNode::operator==) - .def("__ne__", &ResourceNode::operator!=) - - .def("__hash__", - [] (const ResourceNode& node) { - return Hash::hash(node); - }) - - .def("__str__", - [] (const ResourceNode& node) { - std::ostringstream stream; - stream << node; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyResourcesManager.cpp b/vendor/lief/api/python/PE/objects/pyResourcesManager.cpp deleted file mode 100644 index 4acc10f..0000000 --- a/vendor/lief/api/python/PE/objects/pyResourcesManager.cpp +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * Copyright 2017 - 2021 K. Nakagawa - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" -#include "pyErr.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/ResourcesManager.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourcesManager::*)(void) const; - -template -using setter_t = void (ResourcesManager::*)(T); - -template -using no_const_func = T (ResourcesManager::*)(P); - - -template<> -void create(py::module& m) { - py::class_ manager(m, "ResourcesManager", - "The Resource Manager provides an enhanced API to manipulate the resource tree"); - - init_ref_iterator(manager, "it_const_dialogs"); - init_ref_iterator(manager, "it_const_icons"); - init_ref_iterator(manager, "it_const_strings_table"); - init_ref_iterator(manager, "it_const_accelerators"); - - manager - .def_property_readonly("has_manifest", - &ResourcesManager::has_manifest, - "``True`` if the resources contain a Manifest element") - - .def_property("manifest", - [] (const ResourcesManager& obj) { - return safe_string_converter(obj.manifest()); - }, - static_cast>(&ResourcesManager::manifest), - "Manifest as a ``string``") - - - .def_property_readonly("has_version", - &ResourcesManager::has_version, - "``true`` if the resources contain a " RST_CLASS_REF(lief.PE.ResourceVersion) "") - - .def_property_readonly("version", - [] (ResourcesManager& self) { - return error_or(&ResourcesManager::version, self); - }, - "Return the " RST_CLASS_REF(lief.PE.ResourceVersion) "") - - .def_property_readonly("has_icons", - &ResourcesManager::has_icons, - "``true`` if the resources contain " RST_CLASS_REF(lief.PE.ResourceIcon) "") - - .def_property_readonly("icons", - &ResourcesManager::icons, - "Return the list of the " RST_CLASS_REF(lief.PE.ResourceIcon) " present in the resource") - - .def("change_icon", - &ResourcesManager::change_icon, - "Switch the given icons", - "old_one"_a, "new_one"_a) - - .def_property_readonly("has_dialogs", - &ResourcesManager::has_dialogs, - "``true`` if the resources contain " RST_CLASS_REF(lief.PE.ResourceDialog) "") - - .def_property_readonly("dialogs", - &ResourcesManager::dialogs, - "Return the list of the " RST_CLASS_REF(lief.PE.ResourceDialog) " present in the resource") - - .def_property_readonly("types_available", - &ResourcesManager::get_types_available, - "Return list of " RST_CLASS_REF(lief.PE.RESOURCE_TYPES) " present in the resources") - - .def_property_readonly("langs_available", - &ResourcesManager::get_langs_available, - "Return list of " RST_CLASS_REF(lief.PE.RESOURCE_LANGS) " present in the resources") - - .def_property_readonly("sublangs_available", - &ResourcesManager::get_sublangs_available, - "Return list of " RST_CLASS_REF(lief.PE.RESOURCE_SUBLANGS) " present in the resources") - - .def("add_icon", - &ResourcesManager::add_icon, - "Add an icon to the resources", - "icon"_a) - - .def("has_type", - &ResourcesManager::has_type, - "``True`` if the resource has the given " RST_CLASS_REF(lief.PE.RESOURCE_TYPES) "", - "type"_a) - - .def_property_readonly("has_string_table", - &ResourcesManager::has_string_table, - "``True`` if resources contain " RST_CLASS_REF(lief.PE.ResourceStringTable) "") - - .def_property_readonly("string_table", - &ResourcesManager::string_table, - "Return list of " RST_CLASS_REF(lief.PE.ResourceStringTable) " present in the resource") - - .def_property_readonly("has_html", - &ResourcesManager::has_html, - "``True`` if resources contain HTML resource") - - .def_property_readonly("html", - &ResourcesManager::html, - "HTML resource as the list of ``string``") - - .def_property_readonly("has_accelerator", - &ResourcesManager::has_accelerator, - "``True`` if resources contain " RST_CLASS_REF(lief.PE.ResourceAccelerator) "") - - .def_property_readonly("accelerator", - &ResourcesManager::accelerator, - "Return list of " RST_CLASS_REF(lief.PE.ResourceAccelerator) " present in the resource") - - .def("get_node_type", - static_cast>(&ResourcesManager::get_node_type), - R"delim( - Return :class:`~lief.PE.ResourceNode` with the given :class:`~lief.PE.RESOURCE_TYPES` - or None if not found. - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("__str__", - [] (const ResourcesManager& manager) { - std::ostringstream stream; - stream << manager; - std::string str = stream.str(); - return str; - }); -} -} -} - diff --git a/vendor/lief/api/python/PE/objects/pyRichEntry.cpp b/vendor/lief/api/python/PE/objects/pyRichEntry.cpp deleted file mode 100644 index cd0ad2c..0000000 --- a/vendor/lief/api/python/PE/objects/pyRichEntry.cpp +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/RichEntry.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (RichEntry::*)(void) const; - -template -using setter_t = void (RichEntry::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "RichEntry", - R"delim( - Class which represents an entry associated to the RichHeader - )delim") - .def(py::init<>()) - .def(py::init(), - "Contructor from " - ":attr:`~lief.PE.RichEntry.id`, " - ":attr:`~lief.PE.RichEntry.build_id` and " - ":attr:`~lief.PE.RichEntry.count`", - "id"_a, "build_id"_a, "count"_a) - - .def_property("id", - static_cast>(&RichEntry::id), - static_cast>(&RichEntry::id), - "Type of the entry") - - .def_property("build_id", - static_cast>(&RichEntry::build_id), - static_cast>(&RichEntry::build_id), - "Builder number of the tool (if any)") - - .def_property("count", - static_cast>(&RichEntry::count), - static_cast>(&RichEntry::count), - "*Occurrence* count") - - .def("__eq__", &RichEntry::operator==) - .def("__ne__", &RichEntry::operator!=) - .def("__hash__", - [] (const RichEntry& entry) { - return Hash::hash(entry); - }) - - .def("__str__", [] (const RichEntry& entry) - { - std::ostringstream stream; - stream << entry; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyRichHeader.cpp b/vendor/lief/api/python/PE/objects/pyRichHeader.cpp deleted file mode 100644 index c398a32..0000000 --- a/vendor/lief/api/python/PE/objects/pyRichHeader.cpp +++ /dev/null @@ -1,128 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/RichHeader.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (RichHeader::*)(void) const; - -template -using setter_t = void (RichHeader::*)(T); - -template -using no_const_getter = T (RichHeader::*)(void); - - -template<> -void create(py::module& m) { - py::class_ rich(m, "RichHeader", - R"delim( - Class which represents the not-so-documented rich header - - This structure is usually located at the end of the :attr:`~lief.PE.Binary.dos_stub` - and contains information about the build environment. - - It is generated by the Microsoft linker `link.exe` and there are no options to disable - or remove this information. - )delim"); - - init_ref_iterator(rich, "it_entries"); - - rich - .def(py::init<>()) - .def_property("key", - static_cast>(&RichHeader::key), - static_cast>(&RichHeader::key), - "Key used to encode the header (xor operation)") - - .def_property_readonly("entries", - static_cast>(&RichHeader::entries), - "Return an iterator over the " RST_CLASS_REF(lief.PE.RichEntry) " within the header", - py::return_value_policy::reference) - - .def("add_entry", - static_cast(&RichHeader::add_entry), - "Add a new " RST_CLASS_REF(lief.PE.RichEntry) "", - "entry"_a) - - .def("add_entry", - static_cast(&RichHeader::add_entry), - "Add a new " RST_CLASS_REF(lief.PE.RichEntry) " given its " - ":attr:`~lief.PE.RichEntry.id`, " - ":attr:`~lief.PE.RichEntry.build_id`, " - ":attr:`~lief.PE.RichEntry.count`", - "id"_a, "build_id"_a, "count"_a) - - .def("raw", - py::overload_cast<>(&RichHeader::raw, py::const_), - R"delim( - The raw structure of the Rich header without xor-encoding. - - This function is equivalent as calling the other raw function with a `xor_key` set to 0 - )delim") - - .def("raw", - py::overload_cast(&RichHeader::raw, py::const_), - R"delim( - Given this rich header, this function re-computes - the raw bytes of the structure with the provided xor-key. - - You can access the decoded data's structure with the `xor_key` set to 0 - )delim", - "xor_key"_a) - - .def("hash", - py::overload_cast(&RichHeader::hash, py::const_), - R"delim( - Compute the hash of the decoded rich header structure with the given hash :class:`~lief.PE.ALGORITHMS` - )delim", - "algo"_a) - - .def("hash", - py::overload_cast(&RichHeader::hash, py::const_), - R"delim( - Compute the hash of the rich header structure encoded with the provided key and the given hash - :class:`~lief.PE.ALGORITHMS` - )delim", - "algo"_a, "xor_key"_a) - - .def("__eq__", &RichHeader::operator==) - .def("__ne__", &RichHeader::operator!=) - .def("__hash__", - [] (const RichHeader& rich_header) { - return Hash::hash(rich_header); - }) - - .def("__str__", [] (const RichHeader& rich_header) - { - std::ostringstream stream; - stream << rich_header; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pySection.cpp b/vendor/lief/api/python/PE/objects/pySection.cpp deleted file mode 100644 index 446d354..0000000 --- a/vendor/lief/api/python/PE/objects/pySection.cpp +++ /dev/null @@ -1,154 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/Abstract/Section.hpp" -#include "LIEF/PE/Section.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Section::*)(void) const; - -template -using setter_t = void (Section::*)(T); - - -template<> -void create
(py::module& m) { - py::class_(m, "Section", - R"delim( - Class which represents a PE section. - - It extends the base class :class:`lief.Section` - )delim") - .def(py::init<>()) - .def(py::init&, const std::string&, uint32_t>(), - "Constructor from " - ":attr:`~lief.PE.Section.content`, " - ":attr:`~lief.PE.Section.name` and " - ":attr:`~lief.PE.Section.characteristics`", - "content"_a, py::arg("name") = "", py::arg("characteristics") = 0) - - .def(py::init(), - "Constructor from a " - ":attr:`~lief.PE.Section.name`", - "name"_a) - - .def_property("virtual_size", - static_cast>(&Section::virtual_size), - static_cast>(&Section::virtual_size), - R"delim( - The total size of the section when loaded into memory. - - If this value is greater than :attr:`~lief.PE.Section.sizeof_raw_data`, the section is zero-padded. - )delim") - - .def_property("sizeof_raw_data", - static_cast>(&Section::sizeof_raw_data), - static_cast>(&Section::sizeof_raw_data), - "Alias of :attr:`~lief.PE.Section.size` (size of the data in the section)") - - .def_property("pointerto_raw_data", - static_cast>(&Section::pointerto_raw_data), - static_cast>(&Section::pointerto_raw_data), - "The offset of the section data in the PE file. Alias of :attr:`~lief.PE.Section.offset`") - - .def_property("pointerto_relocation", - static_cast>(&Section::pointerto_relocation), - static_cast>(&Section::pointerto_relocation), - R"delim( - The file pointer to the beginning of the COFF relocation entries for the section. This is set to zero for - executable images or if there are no relocations. - - For modern PE binaries, this value is usually set to 0 as the relocations are managed by - :class:`~lief.PE.Relocation`. - )delim") - - .def_property("pointerto_line_numbers", - static_cast>(&Section::pointerto_line_numbers), - static_cast>(&Section::pointerto_line_numbers), - R"delim( - The file pointer to the beginning of line-number entries for the section. - This is set to zero if there are no COFF line numbers. This value should be zero for an image because COFF - debugging information is deprecated and modern debug information relies on the PDB files. - )delim") - - .def_property("numberof_relocations", - static_cast>(&Section::numberof_relocations), - static_cast>(&Section::numberof_relocations), - R"delim( - The number of relocation entries for the section. - - See: :attr:`~lief.PE.Section.pointerto_relocation` - )delim") - - .def_property("numberof_line_numbers", - static_cast>(&Section::numberof_line_numbers), - static_cast>(&Section::numberof_line_numbers), - R"delim( - The number of line-number entries for the section. - This value should be zero for an image because COFF debugging information is - deprecated. - - See: :attr:`~lief.PE.Section.pointerto_line_numbers` - )delim") - - - .def_property("characteristics", - static_cast>(&Section::characteristics), - static_cast>(&Section::characteristics), - "The " RST_CLASS_REF(lief.PE.SECTION_CHARACTERISTICS) " that describe the characteristics of the section") - - .def_property_readonly("characteristics_lists", - &Section::characteristics_list, - ":attr:`~lief.PE.Section.characteristics` as a ``list``") - - .def("has_characteristic", - &Section::has_characteristic, - "``True`` if the section has the given " RST_CLASS_REF(lief.PE.SECTION_CHARACTERISTICS) "", - "characteristic"_a) - - .def_property_readonly("padding", - [] (const Section& sec) { - const std::vector& data = sec.padding(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Section padding content as bytes") - - .def("__eq__", &Section::operator==) - .def("__ne__", &Section::operator!=) - .def("__hash__", - [] (const Section& section) { - return Hash::hash(section); - }) - - .def("__str__", - [] (const Section& section) { - std::ostringstream stream; - stream << section; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pySymbol.cpp b/vendor/lief/api/python/PE/objects/pySymbol.cpp deleted file mode 100644 index 2f4ef12..0000000 --- a/vendor/lief/api/python/PE/objects/pySymbol.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/Symbol.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Symbol::*)(void) const; - -template -using setter_t = void (Symbol::*)(T); - -template -using no_const_getter = T (Symbol::*)(void); - - -template<> -void create(py::module& m) { - py::class_(m, "Symbol") - .def(py::init<>()) - - .def_property("name", - static_cast> (&Symbol::wname), - static_cast>(&Symbol::name)) - - .def_property_readonly("section_number", - &Symbol::section_number) - - .def_property_readonly("type", - &Symbol::type) - - .def_property_readonly("base_type", - &Symbol::base_type) - - .def_property_readonly("complex_type", - &Symbol::complex_type) - - .def_property_readonly("storage_class", - &Symbol::storage_class) - - .def_property_readonly("numberof_aux_symbols", - &Symbol::numberof_aux_symbols) - - .def_property_readonly("section", - static_cast>(&Symbol::section), - py::return_value_policy::reference) - - .def_property_readonly("has_section", - &Symbol::has_section, - "``True`` if symbols are located in a section") - - .def("__eq__", &Symbol::operator==) - .def("__ne__", &Symbol::operator!=) - .def("__hash__", - [] (const Symbol& symbol) { - return Hash::hash(symbol); - }) - - - .def("__str__", [] (const Symbol& symbol) - { - std::ostringstream stream; - stream << symbol; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/pyTLS.cpp b/vendor/lief/api/python/PE/objects/pyTLS.cpp deleted file mode 100644 index 1cabb43..0000000 --- a/vendor/lief/api/python/PE/objects/pyTLS.cpp +++ /dev/null @@ -1,153 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/TLS.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (TLS::*)(void) const; - -template -using setter_t = void (TLS::*)(T); - -template -using no_const_getter = T (TLS::*)(void); - - -template<> -void create(py::module& m) { - py::class_(m, "TLS", - R"delim( - Class which represents the PE Thread Local Storage. - This PE structure is also used to implement binary/library constructors. - )delim") - .def(py::init<>(), - "Default constructor") - - .def_property("callbacks", - static_cast&>>(&TLS::callbacks), - static_cast&>>(&TLS::callbacks), - R"delim( - List of the callback associated with the current TLS. - - These functions are called before any other functions of the PE binary. - )delim") - - .def_property("addressof_index", - static_cast>(&TLS::addressof_index), - static_cast>(&TLS::addressof_index), - R"delim( - The location to receive the TLS index, which the loader assigns. - This location is in an ordinary data section, so it can be given a symbolic name that is accessible - to the program. - )delim") - - .def_property("addressof_callbacks", - static_cast>(&TLS::addressof_callbacks), - static_cast>(&TLS::addressof_callbacks), - R"delim( - The pointer to an array of TLS callback functions. - - The array is null-terminated, so if no callback function - is supported, this field points to 4 bytes set to zero. - - See: :attr:`~lief.PE.TLS.callbacks` - )delim") - - .def_property("sizeof_zero_fill", - static_cast>(&TLS::sizeof_zero_fill), - static_cast>(&TLS::sizeof_zero_fill), - R"delim( - The size in bytes of the template, beyond the initialized data delimited by - the :attr:`~lief.PE.TLS.addressof_raw_data` fields. - The total template size should be the same as the total size of TLS data in the image file. - The zero fill is the amount of data that comes after the initialized nonzero data. - )delim") - - - .def_property("characteristics", - static_cast>(&TLS::characteristics), - static_cast>(&TLS::characteristics), - R"delim( - The four bits [23:20] describe alignment info. - Possible values are those defined as IMAGE_SCN_ALIGN_*, which are also used to - describe alignment of section in object files. The other 28 bits are reserved for future use. - )delim") - - .def_property("addressof_raw_data", - static_cast>>(&TLS::addressof_raw_data), - static_cast>>(&TLS::addressof_raw_data), - R"delim( - Tuple ``(start address, end address)`` of the TLS template. - The template is a block of data that is used to initialize TLS data. - The system copies all of this data each time a thread is created, so it must not be - corrupted. - - .. note:: - - These addresses are not RVA. It is addresses for which there should be a base - relocation in the ``.reloc`` section. - )delim") - - .def_property("data_template", - static_cast&>>(&TLS::data_template), - static_cast&>>(&TLS::data_template), - "The data template content") - - .def_property_readonly("has_section", - &TLS::has_section, - "``True`` if there is a " RST_CLASS_REF(lief.PE.Section) " associated with the TLS object") - - .def_property_readonly("has_data_directory", - &TLS::has_data_directory, - "``True`` if there is a " RST_CLASS_REF(lief.PE.DataDirectory) " associated with the TLS object") - - .def_property_readonly("directory", - static_cast>(&TLS::directory), - "" RST_CLASS_REF(lief.PE.DataDirectory) " associated with the TLS object (or None if not linked)", - py::return_value_policy::reference) - - .def_property_readonly("section", - static_cast>(&TLS::section), - "" RST_CLASS_REF(lief.PE.Section) " associated with the TLS object (or None if not linked)", - py::return_value_policy::reference) - - - .def("__eq__", &TLS::operator==) - .def("__ne__", &TLS::operator!=) - .def("__hash__", - [] (const TLS& tls) { - return Hash::hash(tls); - }) - - .def("__str__", [] (const TLS& tls) - { - std::ostringstream stream; - stream << tls; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/resources/pyLangCodeItem.cpp b/vendor/lief/api/python/PE/objects/resources/pyLangCodeItem.cpp deleted file mode 100644 index 6e013f7..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyLangCodeItem.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/LangCodeItem.hpp" - -#include -#include - - -namespace LIEF { -namespace PE { - -template -using getter_t = T (LangCodeItem::*)(void) const; - -template -using setter_t = void (LangCodeItem::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "LangCodeItem", - R"delim( - Class which represents the childs of the :class:`~lief.PE.ResourceStringFileInfo` - - See: https://docs.microsoft.com/en-us/windows/win32/menurc/stringtable - )delim") - - .def_property("type", - static_cast>(&LangCodeItem::type), - static_cast>(&LangCodeItem::type), - R"delim( - The type of data in the version resource - - * ``1`` if it contains text data - * ``0`` if it contains binary data - )delim") - - .def_property("key", - static_cast>(&LangCodeItem::key), - static_cast>(&LangCodeItem::key), - R"delim( - A 8-digit hexadecimal number stored as an Unicode string - - * The four most significant digits represent the language identifier. - * The four least significant digits represent the code page for which the data is formatted. - - See: - - * :attr:`~lief.PE.LangCodeItem.code_page` - * :attr:`~lief.PE.LangCodeItem.lang` - * :attr:`~lief.PE.LangCodeItem.sublang` - - )delim") - - .def_property("lang", - static_cast>(&LangCodeItem::lang), - static_cast>(&LangCodeItem::lang), - "Lang (" RST_CLASS_REF(lief.PE.RESOURCE_LANGS) ") for which " - ":attr:`~lief.PE.LangCodeItem.items` are defined") - - .def_property("sublang", - static_cast>(&LangCodeItem::sublang), - static_cast>(&LangCodeItem::sublang), - "Sub-lang (" RST_CLASS_REF(lief.PE.RESOURCE_SUBLANGS) ") for which " - ":attr:`~lief.PE.LangCodeItem.items` are defined") - - .def_property("code_page", - static_cast>(&LangCodeItem::code_page), - static_cast>(&LangCodeItem::code_page), - R"delim( - :class:`~lief.PE.CODE_PAGES` for which :attr:`~lief.PE.LangCodeItem.items` are defined. - - See: https://docs.microsoft.com/en-us/windows/win32/intl/code-page-identifiers - )delim") - - .def_property("items", - [] (const LangCodeItem& item) -> py::dict { - py::dict output; - for (const auto& p : item.items()) { - output[u16tou8(p.first).c_str()] = py::bytes(u16tou8(p.second)); - } - return output; - }, - static_cast>(&LangCodeItem::items)) - - - .def("__eq__", &LangCodeItem::operator==) - .def("__ne__", &LangCodeItem::operator!=) - .def("__hash__", - [] (const LangCodeItem& item) { - return Hash::hash(item); - }) - - .def("__str__", - [] (const LangCodeItem& item) { - std::ostringstream stream; - stream << item; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceAccelerator.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceAccelerator.cpp deleted file mode 100644 index e396ecf..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceAccelerator.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * Copyright 2017 - 2021 K. Nakagawa - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceAccelerator.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceAccelerator::*)(void) const; - -template -using setter_t = void (ResourceAccelerator::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceAccelerator") - - .def_property_readonly("flags", - static_cast>(&ResourceAccelerator::flags), - "Describe the keyboard accelerator characteristics.") - - .def_property_readonly("ansi", - static_cast>(&ResourceAccelerator::ansi), - "An ANSI character value or a virtual-key code that identifies the accelerator key.") - - .def_property_readonly("id", - static_cast>(&ResourceAccelerator::id), - "An identifier for the keyboard accelerator.") - - .def_property_readonly("padding", - static_cast>(&ResourceAccelerator::padding), - "The number of bytes inserted to ensure that the structure is aligned on a DWORD boundary.") - - .def("__eq__", &ResourceAccelerator::operator==) - .def("__ne__", &ResourceAccelerator::operator!=) - .def("__hash__", - [] (const ResourceAccelerator& acc) { - return Hash::hash(acc); - }) - - .def("__str__", - [] (const ResourceAccelerator& acc) { - std::ostringstream stream; - stream << acc; - return stream.str(); - }); -} -} -} diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceDialog.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceDialog.cpp deleted file mode 100644 index 45922e7..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceDialog.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyIterators.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceDialog.hpp" - -#include -#include - - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceDialog::*)(void) const; - -template -using setter_t = void (ResourceDialog::*)(T); - - -template<> -void create(py::module& m) { - py::class_ dialog(m, "ResourceDialog", - R"delim( - Representation of a dialog box. - - Windows allows two kinds of dialog box: - - * Simple one - * Extended one - - :attr:`~lief.PE.ResourceDialog.is_extended` can be used to determine which one is implemented - )delim"); - - init_ref_iterator(dialog, "it_const_items"); - - dialog - .def_property_readonly("is_extended", - &ResourceDialog::is_extended, - "``True`` if the dialog is an extended one") - - .def_property_readonly("version", - &ResourceDialog::version, - "The version number of the extended dialog box template. This member must be set to 1.") - - .def_property_readonly("signature", - &ResourceDialog::signature, - R"delim( - Indicate whether a template is an extended dialog box template: - - * ``0xFFFF``: Extended dialog box template - * Other value: Standard dialog box template - )delim") - - .def_property_readonly("help_id", - &ResourceDialog::version, - "The help context identifier for the dialog box window") - - .def_property_readonly("x", - static_cast>(&ResourceDialog::x), - "The x-coordinate, in dialog box units, of the upper-left corner of the dialog box.") - - .def_property_readonly("y", - static_cast>(&ResourceDialog::y), - "The y-coordinate, in dialog box units, of the upper-left corner of the dialog box.") - - .def_property_readonly("cx", - static_cast>(&ResourceDialog::cx), - "The width, in dialog box units, of the dialog box.") - - .def_property_readonly("cy", - static_cast>(&ResourceDialog::cy), - "The height, in dialog box units, of the dialog box.") - - .def_property_readonly("title", - static_cast>(&ResourceDialog::title), - "The title of the dialog box") - - .def_property_readonly("typeface", - static_cast>(&ResourceDialog::typeface), - "The name of the typeface for the font") - - .def_property_readonly("weight", - static_cast>(&ResourceDialog::weight), - "The weight of the font") - - .def_property_readonly("point_size", - static_cast>(&ResourceDialog::point_size), - "The point size of the font to use for the text in the dialog box and its controls.") - - .def_property_readonly("charset", - static_cast>(&ResourceDialog::charset), - "The character set to be used") - - .def_property_readonly("style_list", - &ResourceDialog::style_list, - "Return list of " RST_CLASS_REF(lief.PE.WINDOW_STYLES) " associated with the " - ":attr:`~lief.PE.ResourceDialog.style` member") - - .def_property_readonly("dialogbox_style_list", - &ResourceDialog::dialogbox_style_list, - "Return list of " RST_CLASS_REF(lief.PE.DIALOG_BOX_STYLES) " associated with the " - ":attr:`~lief.PE.ResourceDialog.style` member") - - .def_property_readonly("extended_style_list", - &ResourceDialog::dialogbox_style_list, - "Return list of " RST_CLASS_REF(lief.PE.EXTENDED_WINDOW_STYLES) " associated with the " - ":attr:`~lief.PE.ResourceDialog.extended_style` member") - - .def_property_readonly("style", - &ResourceDialog::extended_style, - "The style of the dialog box. This member can be a combination of " - RST_CLASS_REF(lief.PE.WINDOW_STYLES) " and " RST_CLASS_REF(lief.PE.DIALOG_BOX_STYLES) "") - - .def_property_readonly("extended_style", - &ResourceDialog::extended_style, - "The extended windows styles (" RST_CLASS_REF(lief.PE.EXTENDED_WINDOW_STYLES) ")") - - .def_property_readonly("items", - &ResourceDialog::items, - "Iterator over the controls (" RST_CLASS_REF(lief.PE.ResourceDialogItem) ") that defines the Dialog (Button, Label...)") - - .def("has_style", - &ResourceDialog::has_style, - "Check if the :attr:`~lief.PE.ResourceDialog.style` member has the given " - "" RST_CLASS_REF(lief.PE.WINDOW_STYLES) "", - "style"_a) - - .def("has_dialogbox_style", - &ResourceDialog::has_dialogbox_style, - "Check if the :attr:`~lief.PE.ResourceDialog.style` member has the given " - "" RST_CLASS_REF(lief.PE.DIALOG_BOX_STYLES) "", - "style"_a) - - .def("has_extended_style", - &ResourceDialog::has_extended_style, - "Check if the :attr:`~lief.PE.ResourceDialog.extended_style` member has the given " - "" RST_CLASS_REF(lief.PE.EXTENDED_WINDOW_STYLES) "", - "style"_a) - - .def_property("lang", - static_cast>(&ResourceDialog::lang), - static_cast>(&ResourceDialog::lang), - "Primary " RST_CLASS_REF(lief.PE.RESOURCE_LANGS) " associated with the dialog") - - .def_property("sub_lang", - static_cast>(&ResourceDialog::sub_lang), - static_cast>(&ResourceDialog::sub_lang), - "Secondary " RST_CLASS_REF(lief.PE.RESOURCE_SUBLANGS) " associated with the dialog") - - .def("__eq__", &ResourceDialog::operator==) - .def("__ne__", &ResourceDialog::operator!=) - .def("__hash__", - [] (const ResourceDialog& dialog) { - return Hash::hash(dialog); - }) - - .def("__str__", - [] (const ResourceDialog& dialog) { - std::ostringstream stream; - stream << dialog; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceDialogItem.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceDialogItem.cpp deleted file mode 100644 index 23f58ca..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceDialogItem.cpp +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceDialogItem.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceDialogItem::*)(void) const; - -template -using setter_t = void (ResourceDialogItem::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceDialogItem", - R"delim( - This class represents an item in the :class:`lief.PE.ResourceDialog` - )delim") - - .def_property_readonly("is_extended", - &ResourceDialogItem::is_extended, - "``True`` if the control is an extended one") - - .def_property_readonly("help_id", - static_cast>(&ResourceDialogItem::help_id), - "The help context identifier for the control") - - .def_property_readonly("extended_style", - static_cast>(&ResourceDialogItem::extended_style), - "The extended styles for the window") - - .def_property_readonly("style", - static_cast>(&ResourceDialogItem::style), - "The style of the control. This member can be a combination of " - "" RST_CLASS_REF(lief.PE.WINDOW_STYLES) " values " - "and one or more of the control style values.") - - .def_property_readonly("x", - static_cast>(&ResourceDialogItem::x), - "The x-coordinate, in dialog box units, of the upper-left corner of the control") - - .def_property_readonly("y", - static_cast>(&ResourceDialogItem::y), - "The y-coordinate, in dialog box units, of the upper-left corner of the control") - - .def_property_readonly("cx", - static_cast>(&ResourceDialogItem::cx), - "The width, in dialog box units, of the control") - - .def_property_readonly("cy", - static_cast>(&ResourceDialogItem::cy), - "The height, in dialog box units, of the control") - - .def_property_readonly("id", - static_cast>(&ResourceDialogItem::id), - "The control identifier") - - .def_property_readonly("title", - static_cast>(&ResourceDialogItem::title), - "Initial text of the control") - - .def("__eq__", &ResourceDialogItem::operator==) - .def("__ne__", &ResourceDialogItem::operator!=) - .def("__hash__", - [] (const ResourceDialogItem& dialog) { - return Hash::hash(dialog); - }) - - .def("__str__", - [] (const ResourceDialogItem& dialog_item) { - std::ostringstream stream; - stream << dialog_item; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceFixedFileInfo.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceFixedFileInfo.cpp deleted file mode 100644 index 9f43094..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceFixedFileInfo.cpp +++ /dev/null @@ -1,155 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceFixedFileInfo.hpp" - -#include -#include - - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceFixedFileInfo::*)(void) const; - -template -using setter_t = void (ResourceFixedFileInfo::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceFixedFileInfo", - R"delim( - Representation of the `VS_FIXEDFILEINFO `_ - structure - )delim") - - .def_property("signature", - static_cast>(&ResourceFixedFileInfo::signature), - static_cast>(&ResourceFixedFileInfo::signature), - "Must be set to ``0xFEEF04BD``") - - .def_property("struct_version", - static_cast>(&ResourceFixedFileInfo::struct_version), - static_cast>(&ResourceFixedFileInfo::struct_version), - R"delim( - The binary version number of this structure. - - * The high-order word of this member contains the major version number. - * The low-order word contains the minor version number - )delim") - - .def_property("file_version_MS", - static_cast>(&ResourceFixedFileInfo::file_version_MS), - static_cast>(&ResourceFixedFileInfo::file_version_MS), - R"delim( - The **most** significant 32 bits of the file's binary version number - - This member is used with :attr:`~lief.PE.ResourceFixedFileInfo.file_version_LS` - to form a 64-bits value used for numeric comparisons. - )delim") - - .def_property("file_version_LS", - static_cast>(&ResourceFixedFileInfo::file_version_LS), - static_cast>(&ResourceFixedFileInfo::file_version_LS), - R"delim( - The **least** significant 32 bits of the file's binary version number - - This member is used with :attr:`~lief.PE.ResourceFixedFileInfo.file_version_MS` - to form a 64-bits value used for numeric comparisons. - )delim") - - .def_property("product_version_MS", - static_cast>(&ResourceFixedFileInfo::product_version_MS), - static_cast>(&ResourceFixedFileInfo::product_version_MS), - R"delim( - The **most** significant 32 bits of the product with which this file was distributed - - This member is used with :attr:`~lief.PE.ResourceFixedFileInfo.product_version_LS` - to form a 64-bits value used for numeric comparisons. - )delim") - - .def_property("product_version_LS", - static_cast>(&ResourceFixedFileInfo::product_version_LS), - static_cast>(&ResourceFixedFileInfo::product_version_LS), - R"delim( - The **least** significant 32 bits of the product with which this file was distributed - - This member is used with :attr:`~lief.PE.ResourceFixedFileInfo.product_version_MS` - to form a 64-bits value used for numeric comparisons. - )delim") - - .def_property("file_flags_mask", - static_cast>(&ResourceFixedFileInfo::file_flags_mask), - static_cast>(&ResourceFixedFileInfo::file_flags_mask), - R"delim( - Contains a bitmask that specifies the valid bits in :attr:`~lief.PE.ResourceFixedFileInfo.file_flags`. - A bit is valid only if it was defined when the file was created. - )delim") - - .def_property("file_flags", - static_cast>(&ResourceFixedFileInfo::file_flags), - static_cast>(&ResourceFixedFileInfo::file_flags), - "Contains a bitmask that specifies the Boolean attributes of the file (" RST_CLASS_REF(lief.PE.FIXED_VERSION_FILE_FLAGS) ")") - - .def_property("file_os", - static_cast>(&ResourceFixedFileInfo::file_os), - static_cast>(&ResourceFixedFileInfo::file_os), - "The operating system for which this file was designed (" RST_CLASS_REF(lief.PE.FIXED_VERSION_OS) ")") - - .def_property("file_type", - static_cast>(&ResourceFixedFileInfo::file_type), - static_cast>(&ResourceFixedFileInfo::file_type), - "The general type of file (" RST_CLASS_REF(lief.PE.FIXED_VERSION_FILE_TYPES) ")") - - .def_property("file_subtype", - static_cast>(&ResourceFixedFileInfo::file_subtype), - static_cast>(&ResourceFixedFileInfo::file_subtype), - "The function of the file (" RST_CLASS_REF(lief.PE.FIXED_VERSION_FILE_SUB_TYPES) ")") - - .def_property("file_date_MS", - static_cast>(&ResourceFixedFileInfo::file_date_MS), - static_cast>(&ResourceFixedFileInfo::file_date_MS), - "The **most** significant 32 bits of the file's 64-bit binary creation date and time stamp") - - .def_property("file_date_LS", - static_cast>(&ResourceFixedFileInfo::file_date_LS), - static_cast>(&ResourceFixedFileInfo::file_date_LS), - "The **least** significant 32 bits of the file's 64-bit binary creation date and time stamp") - - - .def("__eq__", &ResourceFixedFileInfo::operator==) - .def("__ne__", &ResourceFixedFileInfo::operator!=) - .def("__hash__", - [] (const ResourceFixedFileInfo& fixed_file_info) { - return Hash::hash(fixed_file_info); - }) - - .def("__str__", - [] (const ResourceFixedFileInfo& fixed_file_info) { - std::ostringstream stream; - stream << fixed_file_info; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceIcon.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceIcon.cpp deleted file mode 100644 index 3acec8c..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceIcon.cpp +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceIcon.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceIcon::*)(void) const; - -template -using setter_t = void (ResourceIcon::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceIcon") - .def_property("id", - static_cast>(&ResourceIcon::id), - static_cast>(&ResourceIcon::id), - "Id associated with the icon") - - .def_property("lang", - static_cast>(&ResourceIcon::lang), - static_cast>(&ResourceIcon::lang), - "Language (" RST_CLASS_REF(lief.PE.RESOURCE_LANGS) ") associated with the icon") - - .def_property("sublang", - static_cast>(&ResourceIcon::sublang), - static_cast>(&ResourceIcon::sublang), - "Sub language (" RST_CLASS_REF(lief.PE.RESOURCE_SUBLANGS) ") associated with the icon") - - .def_property("width", - static_cast>(&ResourceIcon::width), - static_cast>(&ResourceIcon::width), - "Width in pixels of the image") - - .def_property("height", - static_cast>(&ResourceIcon::height), - static_cast>(&ResourceIcon::height), - "Height in pixels of the image") - - .def_property("color_count", - static_cast>(&ResourceIcon::color_count), - static_cast>(&ResourceIcon::color_count), - "Number of colors in image (0 if >=8bpp)") - - .def_property("reserved", - static_cast>(&ResourceIcon::reserved), - static_cast>(&ResourceIcon::reserved), - "Reserved (must be 0)") - - .def_property("planes", - static_cast>(&ResourceIcon::planes), - static_cast>(&ResourceIcon::planes), - "Color Planes") - - .def_property("bit_count", - static_cast>(&ResourceIcon::bit_count), - static_cast>(&ResourceIcon::bit_count), - "Bits per pixel") - - .def_property("pixels", - static_cast&>>(&ResourceIcon::pixels), - static_cast&>>(&ResourceIcon::pixels)) - - .def("save", - &ResourceIcon::save, - "Save the icon to the given filepath", - "filepath"_a) - - .def("__eq__", &ResourceIcon::operator==) - .def("__ne__", &ResourceIcon::operator!=) - .def("__hash__", - [] (const ResourceIcon& icon) { - return Hash::hash(icon); - }) - - .def("__str__", - [] (const ResourceIcon& icon) { - std::ostringstream stream; - stream << icon; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceStringFileInfo.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceStringFileInfo.cpp deleted file mode 100644 index e8587cf..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceStringFileInfo.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceStringFileInfo.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceStringFileInfo::*)(void) const; - -template -using setter_t = void (ResourceStringFileInfo::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceStringFileInfo", - R"delim( - Representation of the ``StringFileInfo`` structure - - See: https://docs.microsoft.com/en-us/windows/win32/menurc/stringfileinfo - )delim") - - - .def_property("type", - static_cast>(&ResourceStringFileInfo::type), - static_cast>(&ResourceStringFileInfo::type), - R"delim( - The type of data in the version resource: - - * ``1`` if it contains text data - * ``0`` if it contains binary data - )delim") - - .def_property("key", - static_cast>(&ResourceStringFileInfo::key), - static_cast>(&ResourceStringFileInfo::key), - "Signature of the structure. Must be ``StringFileInfo``") - - .def_property("langcode_items", - static_cast& (ResourceStringFileInfo::*)(void)>(&ResourceStringFileInfo::langcode_items), - static_cast&>>(&ResourceStringFileInfo::langcode_items), - R"delim( - List of the LangCodeItem items - - Each :attr:`~lief.PE.LangCodeItem.key` indicates the appropriate language and code page - for displaying the ``key: value`` of :attr:`~lief.PE.LangCodeItem.items` - )delim") - - .def("__eq__", &ResourceStringFileInfo::operator==) - .def("__ne__", &ResourceStringFileInfo::operator!=) - .def("__hash__", - [] (const ResourceStringFileInfo& string_file_info) { - return Hash::hash(string_file_info); - }) - - .def("__str__", - [] (const ResourceStringFileInfo& string_file_info) { - std::ostringstream stream; - stream << string_file_info; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceStringTable.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceStringTable.cpp deleted file mode 100644 index 197bd8f..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceStringTable.cpp +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * Copyright 2017 - 2021 K. Nakagawa - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceStringTable.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceStringTable::*)(void) const; - -template -using setter_t = void (ResourceStringTable::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceStringTable") - - .def_property_readonly("length", - static_cast>(&ResourceStringTable::length), - "The size of the string, not including length field itself.") - - .def_property_readonly("name", - static_cast>(&ResourceStringTable::name), - "The variable-length Unicode string data, word-aligned." - ) - - .def("__eq__", &ResourceStringTable::operator==) - .def("__ne__", &ResourceStringTable::operator!=) - .def("__hash__", - [] (const ResourceStringTable& string_table) { - return Hash::hash(string_table); - }) - - .def("__str__", - [] (const ResourceStringTable& string_table) { - std::ostringstream stream; - stream << string_table; - std::string str = stream.str(); - return str; - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceVarFileInfo.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceVarFileInfo.cpp deleted file mode 100644 index 01b14be..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceVarFileInfo.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceVarFileInfo.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceVarFileInfo::*)(void) const; - -template -using setter_t = void (ResourceVarFileInfo::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceVarFileInfo", - "This object describes information about languages supported by the application") - - .def_property("type", - static_cast>(&ResourceVarFileInfo::type), - static_cast>(&ResourceVarFileInfo::type), - R"delim( - The type of data in the version resource - - * ``1`` if it contains text data - * ``0`` if it contains binary data - )delim") - - - .def_property("key", - static_cast>(&ResourceVarFileInfo::key), - static_cast>(&ResourceVarFileInfo::key), - "Signature of the structure. Must be ``VarFileInfo``") - - .def_property("translations", - static_cast& (ResourceVarFileInfo::*)(void)>(&ResourceVarFileInfo::translations), - static_cast&>>(&ResourceVarFileInfo::translations), - R"delim( - List of languages that the application supports - - The **least** significant 16-bits must contain a Microsoft language identifier, - and the **most** significant 16-bits must contain the :class:`~lief.PE.CODE_PAGES` - Either **most** or **least** 16-bits can be zero, indicating that the file is language or code page independent. - )delim") - - .def("__eq__", &ResourceVarFileInfo::operator==) - .def("__ne__", &ResourceVarFileInfo::operator!=) - .def("__hash__", - [] (const ResourceVarFileInfo& var_file_info) { - return Hash::hash(var_file_info); - }) - - .def("__str__", - [] (const ResourceVarFileInfo& var_file_info) { - std::ostringstream stream; - stream << var_file_info; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/resources/pyResourceVersion.cpp b/vendor/lief/api/python/PE/objects/resources/pyResourceVersion.cpp deleted file mode 100644 index 6596260..0000000 --- a/vendor/lief/api/python/PE/objects/resources/pyResourceVersion.cpp +++ /dev/null @@ -1,133 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/resources/ResourceVersion.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ResourceVersion::*)(void) const; - -template -using setter_t = void (ResourceVersion::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ResourceVersion", - R"delim( - Class that represents the data associated with the ``RT_VERSION`` entry - - See: `VS_VERSIONINFO `_ - )delim") - - .def_property("type", - static_cast>(&ResourceVersion::type), - static_cast>(&ResourceVersion::type), - R"delim( - The type of data in the version resource - * ``1`` if it contains text data - * ``0`` if it contains binary data - )delim") - - - .def_property("key", - static_cast>(&ResourceVersion::key), - static_cast>(&ResourceVersion::key), - "Signature of the structure. Must be ``VS_VERSION_INFO``") - - .def_property("fixed_file_info", - static_cast>(&ResourceVersion::fixed_file_info), - static_cast>(&ResourceVersion::fixed_file_info), - R"delim( - :class:`~lief.PE.ResourceFixedFileInfo` associated with the version (if any). - This object describes various information about the application's version. - - If not present, this property is set to None - )delim") - - .def_property("string_file_info", - static_cast>(&ResourceVersion::string_file_info), - static_cast>(&ResourceVersion::string_file_info), - R"delim( - :class:`~lief.PE.ResourceStringFileInfo` associated with the version (if any) - This object describes various information about the application's version. - The underlying structure is basically a dictionary (key/value) - - If the current :class:`~lief.PE.ResourceVersion` does not use :class:`~lief.PE.ResourceStringFileInfo`, - it returns None. - )delim") - - .def_property("var_file_info", - static_cast>(&ResourceVersion::var_file_info), - static_cast>(&ResourceVersion::var_file_info), - R"delim( - :class:`~lief.PE.ResourceVarFileInfo` associated with the version (if any) - This object describes information about languages supported by the application. - - If the current :class:`~lief.PE.ResourceVersion` does not use :class:`~lief.PE.ResourceVarFileInfo`, - it returns None. - )delim") - - .def_property_readonly("has_fixed_file_info", - &ResourceVersion::has_fixed_file_info, - "``True`` if the version contains a " RST_CLASS_REF(lief.PE.ResourceFixedFileInfo) "") - - .def_property_readonly("has_string_file_info", - &ResourceVersion::has_string_file_info, - "``True`` if the version contains a " RST_CLASS_REF(lief.PE.ResourceStringFileInfo) "") - - .def_property_readonly("has_var_file_info", - &ResourceVersion::has_var_file_info, - "``True`` if the version contains a " RST_CLASS_REF(lief.PE.ResourceVarFileInfo) "") - - .def("remove_fixed_file_info", - &ResourceVersion::remove_fixed_file_info, - "Remove the " RST_CLASS_REF(lief.PE.ResourceFixedFileInfo) " from the version") - - .def("remove_string_file_info", - &ResourceVersion::remove_string_file_info, - "Remove the " RST_CLASS_REF(lief.PE.ResourceStringFileInfo) " from the version") - - .def("remove_var_file_info", - &ResourceVersion::remove_var_file_info, - "Remove the " RST_CLASS_REF(lief.PE.ResourceVarFileInfo) " from the version") - - .def("__eq__", &ResourceVersion::operator==) - .def("__ne__", &ResourceVersion::operator!=) - .def("__hash__", - [] (const ResourceVersion& version) { - return Hash::hash(version); - }) - - .def("__str__", - [] (const ResourceVersion& version) { - std::ostringstream stream; - stream << version; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/CMakeLists.txt b/vendor/lief/api/python/PE/objects/signature/CMakeLists.txt deleted file mode 100644 index 1ff2c0e..0000000 --- a/vendor/lief/api/python/PE/objects/signature/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -set(LIEF_PYTHON_PE_SIG_SRC - "${CMAKE_CURRENT_LIST_DIR}/pySignerInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyAttribute.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyRsaInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyx509.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyContentInfo.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pySignature.cpp" -) - -source_group("Header Files\\PE\\signature" FILES ${LIEF_PYTHON_PE_SIG_SRC}) - -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") -target_sources(pyLIEF PRIVATE ${LIEF_PYTHON_PE_SIG_SRC}) - -include("${CMAKE_CURRENT_LIST_DIR}/attributes/CMakeLists.txt") diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/CMakeLists.txt b/vendor/lief/api/python/PE/objects/signature/attributes/CMakeLists.txt deleted file mode 100644 index e917910..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -set(LIEF_PYTHON_PE_SIG_ATTR_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyMsCounterSign.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyContentType.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyGenericType.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pySpcSpOpusInfo.cpp" - - "${CMAKE_CURRENT_LIST_DIR}/pyMsSpcStatementType.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyMsSpcNestedSignature.cpp" - - "${CMAKE_CURRENT_LIST_DIR}/pyPKCS9SigningTime.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyPKCS9MessageDigest.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyPKCS9AtSequenceNumber.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyPKCS9CounterSignature.cpp" -) - -source_group("Header Files\\PE\\signature\\attributes" FILES ${LIEF_PYTHON_PE_SIG_ATTR_SRC}) - -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}") -target_sources(pyLIEF PRIVATE ${LIEF_PYTHON_PE_SIG_ATTR_SRC}) diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyContentType.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyContentType.cpp deleted file mode 100644 index f45a595..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyContentType.cpp +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/ContentType.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ContentType::*)(void) const; - -template -using setter_t = void (ContentType::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "ContentType", - R"delim( - Interface over the structure described by the OID ``1.2.840.113549.1.9.3`` (PKCS #9) - The internal structure is described in the: - `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ - - .. code-block:: text - - ContentType ::= OBJECT IDENTIFIER - - )delim") - .def_property_readonly("oid", - &ContentType::oid, "OID as described in RFC #2985 (string object)") - - .def("__hash__", - [] (const ContentType& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &ContentType::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyGenericType.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyGenericType.cpp deleted file mode 100644 index 4ad0b50..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyGenericType.cpp +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/GenericType.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (GenericType::*)(void) const; - -template -using setter_t = void (GenericType::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "GenericType", - R"delim( - Interface over an attribute for which the internal structure is not supported by LIEF - )delim") - .def_property_readonly("oid", - &GenericType::oid, - "OID of the original attribute") - - .def_property_readonly("raw_content", - [] (const GenericType& type) -> py::bytes { - const std::vector& raw = type.raw_content(); - return py::bytes(reinterpret_cast(raw.data()), raw.size()); - }, - "Original DER blob of the attribute") - - .def("__hash__", - [] (const GenericType& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &GenericType::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsCounterSign.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyMsCounterSign.cpp deleted file mode 100644 index 56c6235..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsCounterSign.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/MsCounterSign.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp deleted file mode 100644 index 8f5e74e..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/MsSpcNestedSignature.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (MsSpcNestedSignature::*)(void) const; - -template -using setter_t = void (MsSpcNestedSignature::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "MsSpcNestedSignature", - R"delim( - Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.4.1`` - - The internal structure is not documented but we can infer the following structure: - - .. code-block:: text - - MsSpcNestedSignature ::= SET OF SignedData - - With ``SignedData``, the structure described in PKCS #7 RFC (See: :class:`lief.PE.Signature`) - )delim") - .def_property_readonly("signature", - &MsSpcNestedSignature::sig, - "Underlying " RST_CLASS_REF(lief.PE.Signature) " object", - py::return_value_policy::reference) - - .def("__hash__", - [] (const MsSpcNestedSignature& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &MsSpcNestedSignature::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcStatementType.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcStatementType.cpp deleted file mode 100644 index c5eb5e7..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyMsSpcStatementType.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/MsSpcStatementType.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (MsSpcStatementType::*)(void) const; - -template -using setter_t = void (MsSpcStatementType::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "MsSpcStatementType", - R"delim( - Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.1.11`` - - The internal structure is described in the official document: - `Windows Authenticode Portable Executable Signature Format `_ - - .. code-block:: text - - SpcStatementType ::= SEQUENCE of OBJECT IDENTIFIER - - )delim") - - .def_property_readonly("oid", - &MsSpcStatementType::oid, - R"delim( - According to the documentation: - - :: - - The SpcStatementType MUST contain one Object Identifier with either - the value ``1.3.6.1.4.1.311.2.1.21 (SPC_INDIVIDUAL_SP_KEY_PURPOSE_OBJID)`` or - ``1.3.6.1.4.1.311.2.1.22 (SPC_COMMERCIAL_SP_KEY_PURPOSE_OBJID)``. - )delim") - - .def("__hash__", - [] (const MsSpcStatementType& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &MsSpcStatementType::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp deleted file mode 100644 index 7c9e97c..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/PKCS9AtSequenceNumber.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (PKCS9AtSequenceNumber::*)(void) const; - -template -using setter_t = void (PKCS9AtSequenceNumber::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "PKCS9AtSequenceNumber", - R"delim( - Interface over the structure described by the OID ``1.2.840.113549.1.9.25.4`` (PKCS #9) - - The internal structure is described in the - `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ - - .. code-block:: text - - sequenceNumber ATTRIBUTE ::= { - WITH SYNTAX SequenceNumber - EQUALITY MATCHING RULE integerMat - SINGLE VALUE TRUE - ID pkcs-9-at-sequenceNumber - } - - SequenceNumber ::= INTEGER (1..MAX) - - )delim") - - .def_property_readonly("number", - &PKCS9AtSequenceNumber::number, - "Number as described in the RFC") - - .def("__hash__", - [] (const PKCS9AtSequenceNumber& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &PKCS9AtSequenceNumber::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp deleted file mode 100644 index 2c14515..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/PKCS9CounterSignature.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (PKCS9CounterSignature::*)(void) const; - -template -using setter_t = void (PKCS9CounterSignature::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "PKCS9CounterSignature", - R"delim( - Interface over the structure described by the OID ``1.2.840.113549.1.9.6`` (PKCS #9) - - The internal structure is described in the - `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ - - .. code-block:: text - - counterSignature ATTRIBUTE ::= { - WITH SYNTAX SignerInfo - ID pkcs-9-at-counterSignature - } - - )delim") - .def_property_readonly("signer", - &PKCS9CounterSignature::signer, - "Return the " RST_CLASS_REF(lief.PE.SignerInfo) " as described in the RFC #2985", - py::return_value_policy::reference) - - .def("__hash__", - [] (const PKCS9CounterSignature& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &PKCS9CounterSignature::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp deleted file mode 100644 index c240963..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/PKCS9MessageDigest.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (PKCS9MessageDigest::*)(void) const; - -template -using setter_t = void (PKCS9MessageDigest::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "PKCS9MessageDigest", - R"delim( - Interface over the structure described by the OID ``1.2.840.113549.1.9.4`` (PKCS #9) - - The internal structure is described in the - `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ - - .. code-block:: text - - messageDigest ATTRIBUTE ::= { - WITH SYNTAX MessageDigest - EQUALITY MATCHING RULE octet - SINGLE VALUE TRUE - ID pkcs-9-at-messageDigest - } - - MessageDigest ::= OCTET STRING - - )delim") - - .def_property_readonly("digest", - [] (const PKCS9MessageDigest& digest) -> py::object { - const std::vector& data = digest.digest(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Message digeset as a blob of bytes as described in the RFC") - - .def("__hash__", - [] (const PKCS9MessageDigest& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &PKCS9MessageDigest::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp deleted file mode 100644 index 682b73c..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/PKCS9SigningTime.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (PKCS9SigningTime::*)(void) const; - -template -using setter_t = void (PKCS9SigningTime::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "PKCS9SigningTime", - R"delim( - Interface over the structure described by the OID ``1.2.840.113549.1.9.5`` (PKCS #9) - - The internal structure is described in the - `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ - - .. code-block:: text - - signingTime ATTRIBUTE ::= { - WITH SYNTAX SigningTime - EQUALITY MATCHING RULE signingTimeMatch - SINGLE VALUE TRUE - ID pkcs-9-at-signingTime - } - - SigningTime ::= Time -- imported from ISO/IEC 9594-8 - - )delim") - - .def_property_readonly("time", - &PKCS9SigningTime::time, - "Time as a list [year, month, day, hour, min, sec]") - - .def("__hash__", - [] (const PKCS9SigningTime& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &PKCS9SigningTime::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp b/vendor/lief/api/python/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp deleted file mode 100644 index 50b23f7..0000000 --- a/vendor/lief/api/python/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" -#include "LIEF/PE/signature/attributes/SpcSpOpusInfo.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (SpcSpOpusInfo::*)(void) const; - -template -using setter_t = void (SpcSpOpusInfo::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "SpcSpOpusInfo", - R"delim( - Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.1.12`` - The internal structure is described in the official document: `Windows Authenticode Portable Executable Signature Format `_ - - .. code-block:: text - - SpcSpOpusInfo ::= SEQUENCE { - programName [0] EXPLICIT SpcString OPTIONAL, - moreInfo [1] EXPLICIT SpcLink OPTIONAL - } - )delim" - ) - .def_property_readonly("program_name", - [] (const SpcSpOpusInfo& info) { - return safe_string_converter(info.program_name()); - }, "Program description provided by the publisher") - - .def_property_readonly("more_info", - [] (const SpcSpOpusInfo& info) { - return safe_string_converter(info.more_info()); - }, "Other information such as an URL") - - .def("__hash__", - [] (const SpcSpOpusInfo& obj) { - return Hash::hash(obj); - }) - - .def("__str__", &SpcSpOpusInfo::print); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/pyAttribute.cpp b/vendor/lief/api/python/PE/objects/signature/pyAttribute.cpp deleted file mode 100644 index 3416952..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pyAttribute.cpp +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Attribute.hpp" - -#include -#include - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Attribute::*)(void) const; - -template -using setter_t = void (Attribute::*)(T); - - -template<> -void create(py::module& m) { - py::class_(m, "Attribute", "Interface over PKCS #7 attribute") - .def_property_readonly("type", - &Attribute::type, - "Concrete type (" RST_CLASS_REF(lief.PE.SIG_ATTRIBUTE_TYPES) ") of the attribute") - - .def("__str__", [] (const Attribute& attr) - { - return attr.print(); - }); -} - -} -} diff --git a/vendor/lief/api/python/PE/objects/signature/pyContentInfo.cpp b/vendor/lief/api/python/PE/objects/signature/pyContentInfo.cpp deleted file mode 100644 index 11925d5..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pyContentInfo.cpp +++ /dev/null @@ -1,116 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/ContentInfo.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (ContentInfo::*)(void) const; - -template -using setter_t = void (ContentInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "ContentInfo", - R"delim( - ContentInfo as described in the `RFC 2315 `_ - - .. code-block:: text - - ContentInfo ::= SEQUENCE { - contentType ContentType, - content [0] EXPLICIT ANY DEFINED BY contentType OPTIONAL - } - - ContentType ::= OBJECT IDENTIFIER - - In the case of PE signature, ContentType **must** be set to SPC_INDIRECT_DATA_OBJID - OID: ``1.3.6.1.4.1.311.2.1.4`` and content is defined by the structure: ``SpcIndirectDataContent`` - - .. code-block:: text - - SpcIndirectDataContent ::= SEQUENCE { - data SpcAttributeTypeAndOptionalValue, - messageDigest DigestInfo - } - - SpcAttributeTypeAndOptionalValue ::= SEQUENCE { - type ObjectID, - value [0] EXPLICIT ANY OPTIONAL - } - - For PE signature, ``SpcAttributeTypeAndOptionalValue.type`` - is set to ``SPC_PE_IMAGE_DATAOBJ`` (OID: ``1.3.6.1.4.1.311.2.1.15``) and the value is defined by - ``SpcPeImageData`` - - .. code-block:: text - - DigestInfo ::= SEQUENCE { - digestAlgorithm AlgorithmIdentifier, - digest OCTETSTRING - } - - AlgorithmIdentifier ::= SEQUENCE { - algorithm ObjectID, - parameters [0] EXPLICIT ANY OPTIONAL - } - )delim") - - .def_property_readonly("content_type", - &ContentInfo::content_type, - "OID of the content type. This value should match ``SPC_INDIRECT_DATA_OBJID``") - - .def_property_readonly("digest_algorithm", - &ContentInfo::digest_algorithm, - "Algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") used to hash the file. " - "This value should match " RST_ATTR_REF_FULL(SignerInfo.digest_algorithm) " and " - "" RST_ATTR_REF_FULL(Signature.digest_algorithm) "") - - .def_property_readonly("digest", - [] (const ContentInfo& info) -> py::bytes { - const std::vector& dg = info.digest(); - return py::bytes(reinterpret_cast(dg.data()), dg.size()); - }, - "The digest as ``bytes``. It should match the binary :meth:`~lief.PE.Binary.authentihash`") - - .def("__hash__", - [] (const ContentInfo& info) { - return Hash::hash(info); - }) - - .def("__str__", - [] (const ContentInfo& content_info) - { - std::ostringstream stream; - stream << content_info; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/pyRsaInfo.cpp b/vendor/lief/api/python/PE/objects/signature/pyRsaInfo.cpp deleted file mode 100644 index ce3f538..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pyRsaInfo.cpp +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/PE/signature/RsaInfo.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (RsaInfo::*)(void) const; - -template -using setter_t = void (RsaInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_(m, "RsaInfo", "Object representing a RSA key") - .def_property_readonly("has_public_key", - &RsaInfo::has_public_key, - "True if it embeds a public key") - - .def_property_readonly("has_private_key", - &RsaInfo::has_private_key, - "True if it embeds a private key") - - .def_property_readonly("N", - [] (const RsaInfo& info) { - const std::vector& data = info.N(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "RSA public modulus (in bytes)") - - .def_property_readonly("E", - [] (const RsaInfo& info) { - const std::vector& data = info.E(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, "RSA public exponent (in bytes)") - - .def_property_readonly("D", - [] (const RsaInfo& info) { - const std::vector& data = info.D(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, "RSA private exponent (in bytes)") - - .def_property_readonly("P", - [] (const RsaInfo& info) { - const std::vector& data = info.P(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, "First prime factor (in bytes)") - - .def_property_readonly("Q", - [] (const RsaInfo& info) { - const std::vector& data = info.Q(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, "Second prime factor (in bytes)") - - .def_property_readonly("key_size", - &RsaInfo::key_size, "Size of the public modulus in bits") - - .def_property_readonly("__len__", - &RsaInfo::key_size) - - .def("__str__", - [] (const RsaInfo& info) - { - std::ostringstream stream; - stream << info; - return safe_string_converter(stream.str()); - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/pySignature.cpp b/vendor/lief/api/python/PE/objects/signature/pySignature.cpp deleted file mode 100644 index 54f4283..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pySignature.cpp +++ /dev/null @@ -1,241 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "enums_wrapper.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/Signature.hpp" -#include "LIEF/PE/signature/SignatureParser.hpp" - -#define LIEF_PE_FORCE_UNDEF -#include "LIEF/PE/undef.h" -#include "pyPE.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (Signature::*)(void) const; - -template -using setter_t = void (Signature::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ signature(m, "Signature"); - LIEF::enum_ verif_flags_enums(signature, "VERIFICATION_FLAGS", py::arithmetic()); - verif_flags_enums - .value("OK", Signature::VERIFICATION_FLAGS::OK) - .value("INVALID_SIGNER", Signature::VERIFICATION_FLAGS::INVALID_SIGNER) - .value("UNSUPPORTED_ALGORITHM", Signature::VERIFICATION_FLAGS::UNSUPPORTED_ALGORITHM) - .value("INCONSISTENT_DIGEST_ALGORITHM", Signature::VERIFICATION_FLAGS::INCONSISTENT_DIGEST_ALGORITHM) - .value("CERT_NOT_FOUND", Signature::VERIFICATION_FLAGS::CERT_NOT_FOUND) - .value("CORRUPTED_CONTENT_INFO", Signature::VERIFICATION_FLAGS::CORRUPTED_CONTENT_INFO) - .value("CORRUPTED_AUTH_DATA", Signature::VERIFICATION_FLAGS::CORRUPTED_AUTH_DATA) - .value("MISSING_PKCS9_MESSAGE_DIGEST", Signature::VERIFICATION_FLAGS::MISSING_PKCS9_MESSAGE_DIGEST) - .value("BAD_DIGEST", Signature::VERIFICATION_FLAGS::BAD_DIGEST) - .value("BAD_SIGNATURE", Signature::VERIFICATION_FLAGS::BAD_SIGNATURE) - .value("NO_SIGNATURE", Signature::VERIFICATION_FLAGS::NO_SIGNATURE) - .value("CERT_EXPIRED", Signature::VERIFICATION_FLAGS::CERT_EXPIRED) - .value("CERT_FUTURE", Signature::VERIFICATION_FLAGS::CERT_FUTURE); - - py::dict verif_flags_entries = verif_flags_enums.attr("__entries"); - verif_flags_enums - .def("__str__", [verif_flags_entries] (const Signature::VERIFICATION_FLAGS& flags) { - if (flags == Signature::VERIFICATION_FLAGS::OK) { - return Signature::flag_to_string(flags); - } - std::string flags_str; - for (const auto& item : verif_flags_entries) { - Signature::VERIFICATION_FLAGS flag = item.second[py::int_(0)].cast(); - if ((flags & flag) == flag && flag != Signature::VERIFICATION_FLAGS::OK) { - if (!flags_str.empty()) { - flags_str += " | "; - } - flags_str += "VERIFICATION_FLAGS." + Signature::flag_to_string(flag); - } - } - return flags_str; - }, py::prepend{}); - - LIEF::enum_(signature, "VERIFICATION_CHECKS", py::arithmetic(), - R"delim( - Flags to tweak the verification process of the signature - See :meth:`lief.PE.Signature.check` and :meth:`lief.PE.Binary.verify_signature` - )delim") - .value("DEFAULT", Signature::VERIFICATION_CHECKS::DEFAULT, - "Default behavior that tries to follow the Microsoft verification process as close as possible") - - .value("HASH_ONLY", Signature::VERIFICATION_CHECKS::HASH_ONLY, - R"delim( - Only check that :meth:`lief.PE.Binary.authentihash` matches :attr:`lief.PE.ContentInfo.digest` - regardless of the signature's validity - )delim") - - .value("LIFETIME_SIGNING", Signature::VERIFICATION_CHECKS::LIFETIME_SIGNING, - R"delim( - Same semantic as `WTD_LIFETIME_SIGNING_FLAG `_ - )delim") - - .value("SKIP_CERT_TIME", Signature::VERIFICATION_CHECKS::SKIP_CERT_TIME, - R"delim( - Skip the verification of the certificates time validities so that even though - a certificate expired, it returns :attr:`lief.PE.Signature.VERIFICATION_FLAGS.OK` - )delim"); - - init_ref_iterator(signature, "it_const_crt"); - init_ref_iterator(signature, "it_const_signers_t"); - - signature - .def_static("parse", - [] (const std::string& path) -> py::object { - auto sig = SignatureParser::parse(path); - if (!sig) { - return py::none(); - } - return py::cast(sig.value()); - }, - "Parse the DER PKCS #7 signature from the file path given in the first parameter", - "path"_a) - - .def_static("parse", - [] (const std::vector& raw, bool skip_header) -> py::object { - auto sig = SignatureParser::parse(raw, skip_header); - if (!sig) { - return py::none(); - } - return py::cast(sig.value()); - }, - "Parse the raw (DER) PKCS #7 signature given in the first parameter", - "raw"_a, "skip_header"_a = false) - - .def_property_readonly("version", - &Signature::version, - "Version of the signature. It should be 1") - - .def_property_readonly("digest_algorithm", - &Signature::digest_algorithm, - "Return the algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") \ - used to sign the content of " RST_CLASS_REF(lief.PE.ContentInfo) "") - - .def_property_readonly("content_info", - &Signature::content_info, - "Return the " RST_CLASS_REF(lief.PE.ContentInfo) "", - py::return_value_policy::reference) - - .def_property_readonly("certificates", - &Signature::certificates, - "Return an iterator over " RST_CLASS_REF(lief.PE.x509) " certificates", - py::return_value_policy::reference) - - .def_property_readonly("signers", - &Signature::signers, - "Return an iterator over the signers: " RST_CLASS_REF(lief.PE.SignerInfo) "", - py::return_value_policy::reference) - - .def("find_crt", - static_cast&) const>(&Signature::find_crt), - "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its serial number", - py::return_value_policy::reference, - "serialno"_a) - - .def("find_crt_subject", - static_cast(&Signature::find_crt_subject), - "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its subject", - py::return_value_policy::reference, - "subject"_a) - - .def("find_crt_subject", - static_cast&) const>(&Signature::find_crt_subject), - "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its subject **AND** its serial number", - py::return_value_policy::reference, - "subject"_a, "serialno"_a) - - .def("find_crt_issuer", - static_cast(&Signature::find_crt_issuer), - "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its issuer", - py::return_value_policy::reference, - "issuer"_a) - - .def("find_crt_issuer", - static_cast&) const>(&Signature::find_crt_issuer), - "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its issuer **AND** its serial number", - py::return_value_policy::reference, - "issuer"_a, "serialno"_a) - - .def("check", - &Signature::check, - // Note: This documentation needs to be sync with LIEF::PE::Signature::check - R"delim( - Check the integrity of the signature and return a :class:`lief.PE.Signature.VERIFICATION_FLAGS` - - By default, it performs the following verifications: - - 1. It must contain only **one** signer info (:attr:`~lief.PE.Signature.signers`) - 2. :attr:`lief.PE.Signature.digest_algorithm` must match: - - * :attr:`lief.PE.ContentInfo.digest_algorithm` - * :attr:`lief.PE.SignerInfo.digest_algorithm` - - 3. The x509 certificate specified by :attr:`lief.PE.SignerInfo.serial_number` **and** :attr:`lief.PE.SignerInfo.issuer` - must exist within :attr:`lief.PE.Signature.certificates` - 4. Given the x509 certificate, compare :attr:`lief.PE.SignerInfo.encrypted_digest` against either: - - * hash of authenticated attributes (:attr:`~lief.PE.SignerInfo.authenticated_attributes`) if present - * hash of ContentInfo - - 5. If they are Authenticated attributes, check that a PKCS9_MESSAGE_DIGEST (:class:`lief.PE.PKCS9MessageDigest`) attribute exists - and that its value matches hash of ContentInfo - 6. Check the validity of the PKCS #9 counter signature if present - 7. If the signature doesn't embed a signing-time in the counter signature, check the certificate - validity. (See :attr:`lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING` and :attr:`lief.pe.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME`) - - See: :class:`lief.PE.Signature.VERIFICATION_CHECKS` to tweak the behavior - - )delim", - "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT - ) - - .def_property_readonly("raw_der", - [] (const Signature& sig) { - const std::vector& raw = sig.raw_der(); - return py::bytes(reinterpret_cast(raw.data()), raw.size()); - }, - "Return the raw original signature as a byte object", - py::return_value_policy::reference_internal) - - .def("__hash__", - [] (const Signature& obj) { - return Hash::hash(obj); - }) - - .def("__str__", - [] (const Signature& signature) - { - std::ostringstream stream; - stream << signature; - return stream.str(); - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/pySignerInfo.cpp b/vendor/lief/api/python/PE/objects/signature/pySignerInfo.cpp deleted file mode 100644 index ae3a7a8..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pySignerInfo.cpp +++ /dev/null @@ -1,165 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/SignerInfo.hpp" -#include "LIEF/PE/signature/Attribute.hpp" - -#include "pyPE.hpp" -#include "pyIterators.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (SignerInfo::*)(void) const; - -template -using setter_t = void (SignerInfo::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ signer(m, "SignerInfo", - R"delim( - SignerInfo as described in the `RFC 2315 #Section 9.2 `_ - - .. code-block:: text - - SignerInfo ::= SEQUENCE { - version Version, - issuerAndSerialNumber IssuerAndSerialNumber, - digestAlgorithm DigestAlgorithmIdentifier, - authenticatedAttributes [0] IMPLICIT Attributes OPTIONAL, - digestEncryptionAlgorithm DigestEncryptionAlgorithmIdentifier, - encryptedDigest EncryptedDigest, - unauthenticatedAttributes [1] IMPLICIT Attributes OPTIONAL - } - - EncryptedDigest ::= OCTET STRING - )delim"); - - - init_ref_iterator(signer, "it_const_attributes_t"); - - signer - .def_property_readonly("version", - &SignerInfo::version, - "Should be 1") - - .def_property_readonly("serial_number", - [] (const SignerInfo& info) -> py::bytes { - const std::vector& data = info.serial_number(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "The X509 serial number used to sign the signed-data (see: :attr:`lief.PE.x509.serial_number`)") - - .def_property_readonly("issuer", - [] (const SignerInfo& object) { - return safe_string_converter(object.issuer()); - }, - "The X509 issuer used to sign the signed-data (see: :attr:`lief.PE.x509.issuer`)", - py::return_value_policy::copy) - - .def_property_readonly("digest_algorithm", - &SignerInfo::digest_algorithm, - "Algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") used to hash the file. " - "This value should match " RST_ATTR_REF_FULL(ContentInfo.digest_algorithm) " " - "and " RST_ATTR_REF_FULL(Signature.digest_algorithm) "") - - .def_property_readonly("encryption_algorithm", - &SignerInfo::encryption_algorithm, - "Return algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") used to encrypt the digest") - - .def_property_readonly("encrypted_digest", - [] (const SignerInfo& info) { - const std::vector& data = info.encrypted_digest(); - return py::bytes(reinterpret_cast(data.data()), data.size()); - }, - "Return the signature created by the signing certificate's private key") - - .def_property_readonly("authenticated_attributes", - &SignerInfo::authenticated_attributes, - "Return an iterator over the authenticated attributes (" - "" RST_CLASS_REF(lief.PE.Attribute) ")", - py::return_value_policy::reference) - - .def_property_readonly("unauthenticated_attributes", - &SignerInfo::unauthenticated_attributes, - "Return an iterator over the unauthenticated attributes (" - "" RST_CLASS_REF(lief.PE.Attribute) ")", - py::return_value_policy::reference) - - .def("get_attribute", - &SignerInfo::get_attribute, - R"delim( - Return the authenticated or un-authenticated attribute matching the - given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` - It returns **the first** entry that matches the given type. If it can't be - found, it returns None - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("get_auth_attribute", - &SignerInfo::get_auth_attribute, - R"delim( - Return the authenticated attribute matching the - given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` - It returns **the first** entry that matches the given type. If it can't be - found, it returns None - )delim", - "type"_a, - py::return_value_policy::reference) - - .def("get_unauth_attribute", - &SignerInfo::get_unauth_attribute, - R"delim( - Return the un-authenticated attribute matching the - given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` - It returns **the first** entry that matches the given type. If it can't be - found, it returns a nullptr - )delim", - "type"_a, - py::return_value_policy::reference) - - .def_property_readonly("cert", - static_cast(&SignerInfo::cert), - "" RST_CLASS_REF(lief.PE.x509) " certificate used by this signer. If it can't be found, it returns None", - py::return_value_policy::reference) - - .def("__hash__", - [] (const SignerInfo& obj) { - return Hash::hash(obj); - }) - - .def("__str__", - [] (const SignerInfo& signer_info) - { - std::ostringstream stream; - stream << signer_info; - std::string str = stream.str(); - return str; - }); - -} - -} -} - diff --git a/vendor/lief/api/python/PE/objects/signature/pyx509.cpp b/vendor/lief/api/python/PE/objects/signature/pyx509.cpp deleted file mode 100644 index dcfbc8d..0000000 --- a/vendor/lief/api/python/PE/objects/signature/pyx509.cpp +++ /dev/null @@ -1,222 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "enums_wrapper.hpp" - -#include "LIEF/PE/hash.hpp" -#include "LIEF/PE/signature/x509.hpp" -#include "LIEF/PE/signature/RsaInfo.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -template -using getter_t = T (x509::*)(void) const; - -template -using setter_t = void (x509::*)(T); - - -template<> -void create(py::module& m) { - - py::class_ cls_x509(m, "x509", "Interface over a x509 certificate"); - - LIEF::enum_(cls_x509, "VERIFICATION_FLAGS", py::arithmetic(), - "Verification flags associated with " RST_METH_REF(lief.PE.x509.verify) "") - .value("OK", x509::VERIFICATION_FLAGS::OK, "The verification succeed") - .value("BADCERT_EXPIRED", x509::VERIFICATION_FLAGS::BADCERT_EXPIRED, "The certificate validity has expired") - .value("BADCERT_REVOKED", x509::VERIFICATION_FLAGS::BADCERT_REVOKED, "The certificate has been revoked (is on a CRL)") - .value("BADCERT_CN_MISMATCH", x509::VERIFICATION_FLAGS::BADCERT_CN_MISMATCH, "The certificate Common Name (CN) does not match with the expected CN.") - .value("BADCERT_NOT_TRUSTED", x509::VERIFICATION_FLAGS::BADCERT_NOT_TRUSTED, "The certificate is not correctly signed by the trusted CA.") - .value("BADCRL_NOT_TRUSTED", x509::VERIFICATION_FLAGS::BADCRL_NOT_TRUSTED, "The CRL is not correctly signed by the trusted CA.") - .value("BADCRL_EXPIRED", x509::VERIFICATION_FLAGS::BADCRL_EXPIRED, "The CRL is expired.") - .value("BADCERT_MISSING", x509::VERIFICATION_FLAGS::BADCERT_MISSING, "Certificate was missing.") - .value("BADCERT_SKIP_VERIFY", x509::VERIFICATION_FLAGS::BADCERT_SKIP_VERIFY, "Certificate verification was skipped.") - .value("BADCERT_OTHERNATURE", x509::VERIFICATION_FLAGS::BADCERT_OTHER, "Other reason") - .value("BADCERT_FUTURE", x509::VERIFICATION_FLAGS::BADCERT_FUTURE, "The certificate validity starts in the future.") - .value("BADCRL_FUTURE", x509::VERIFICATION_FLAGS::BADCRL_FUTURE, "The CRL is from the future") - .value("BADCERT_KEY_USAGE", x509::VERIFICATION_FLAGS::BADCERT_KEY_USAGE, "Usage does not match the keyUsage extension.") - .value("BADCERT_EXT_KEY_USAGE", x509::VERIFICATION_FLAGS::BADCERT_EXT_KEY_USAGE, "Usage does not match the extendedKeyUsage extension.") - .value("BADCERT_NS_CERT_TYPE", x509::VERIFICATION_FLAGS::BADCERT_NS_CERT_TYPE, "Usage does not match the nsCertType extension.") - .value("BADCERT_BAD_MD", x509::VERIFICATION_FLAGS::BADCERT_BAD_MD, "The certificate is signed with an unacceptable hash.") - .value("BADCERT_BAD_PK", x509::VERIFICATION_FLAGS::BADCERT_BAD_PK, "The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA).") - .value("BADCERT_BAD_KEY", x509::VERIFICATION_FLAGS::BADCERT_BAD_KEY, "The certificate is signed with an unacceptable key (eg bad curve, RSA too short).") - .value("BADCRL_BAD_MD", x509::VERIFICATION_FLAGS::BADCRL_BAD_MD, "The CRL is signed with an unacceptable hash.") - .value("BADCRL_BAD_PK", x509::VERIFICATION_FLAGS::BADCRL_BAD_PK, "The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA).") - .value("BADCRL_BAD_KEY", x509::VERIFICATION_FLAGS::BADCRL_BAD_KEY, "The CRL is signed with an unacceptable key (eg bad curve, RSA too short)."); - - LIEF::enum_(cls_x509, "KEY_TYPES", "Public key scheme used by the x509 certificate") - .value("NONE", x509::KEY_TYPES::NONE, "Unknown scheme") - .value("RSA", x509::KEY_TYPES::RSA, "RSA scheme") - .value("ECKEY", x509::KEY_TYPES::ECKEY, "Elliptic-curve scheme") - .value("ECKEY_DH", x509::KEY_TYPES::ECKEY_DH, "Elliptic-curve Diffie-Hellman") - .value("ECDSA", x509::KEY_TYPES::ECDSA, "Elliptic-curve Digital Signature Algorithm") - .value("RSA_ALT", x509::KEY_TYPES::RSA_ALT, "RSA scheme with an alternative implementation for signing and decrypting") - .value("RSASSA_PSS", x509::KEY_TYPES::RSASSA_PSS, "RSA Probabilistic signature scheme"); - - LIEF::enum_(cls_x509, "KEY_USAGE", "Key usage as defined in `RFC #5280 - section-4.2.1.3 `_") - .value("DIGITAL_SIGNATURE", x509::KEY_USAGE::DIGITAL_SIGNATURE, "The key is used for digital signature") - .value("NON_REPUDIATION", x509::KEY_USAGE::NON_REPUDIATION, "The key is used for digital signature AND to protects against falsely denying some action") - .value("KEY_ENCIPHERMENT", x509::KEY_USAGE::KEY_ENCIPHERMENT, "The key is used for enciphering private or secret keys") - .value("DATA_ENCIPHERMENT", x509::KEY_USAGE::DATA_ENCIPHERMENT, "The key is used for directly enciphering raw user data without the use of an intermediate symmetric cipher") - .value("KEY_AGREEMENT", x509::KEY_USAGE::KEY_AGREEMENT, "The Key is used for key agreement. (e.g. with Diffie-Hellman)") - .value("KEY_CERT_SIGN", x509::KEY_USAGE::KEY_CERT_SIGN, "The key is used for verifying signatures on public key certificates") - .value("CRL_SIGN", x509::KEY_USAGE::CRL_SIGN, "The key is used for verifying signatures on certificate revocation lists") - .value("ENCIPHER_ONLY", x509::KEY_USAGE::ENCIPHER_ONLY, "In **association with** KEY_AGREEMENT (otherwise the meaning is undefined), the key is only used for enciphering data while performing key agreement") - .value("DECIPHER_ONLY", x509::KEY_USAGE::DECIPHER_ONLY, "In **association with** KEY_AGREEMENT (otherwise the meaning is undefined), the key is only used for deciphering data while performing key agreement"); - - cls_x509 - .def_static("parse", - static_cast(&x509::parse), - "Parse " RST_CLASS_REF(lief.PE.x509) " certificate(s) from a file path given in the first parameter.\n" - "It returns a **list** of " RST_CLASS_REF(lief.PE.x509) " objects", - "path"_a) - - .def_static("parse", - static_cast&)>(&x509::parse), - "Parse " RST_CLASS_REF(lief.PE.x509) " certificate(s) from a raw blob given in the first parameter.\n" - "It returns a **list** of " RST_CLASS_REF(lief.PE.x509) " objects", - "raw"_a) - - .def_property_readonly("version", - &x509::version, - "X.509 version. (1=v1, 2=v2, 3=v3)") - - .def_property_readonly("serial_number", - [] (const x509& crt) -> py::bytes { - const std::vector& sn = crt.serial_number(); - return py::bytes(reinterpret_cast(sn.data()), sn.size()); - }, - "Unique id for certificate issued by a specific CA.") - - .def_property_readonly("signature_algorithm", - &x509::signature_algorithm, - "Signature algorithm (OID)") - - .def_property_readonly("valid_from", - &x509::valid_from, - "Start time of certificate validity") - - .def_property_readonly("valid_to", - &x509::valid_to, - "End time of certificate validity") - - .def_property_readonly("issuer", - [] (const x509& object) { - return safe_string_converter(object.issuer()); - }, - "Issuer of the certificate") - - .def_property_readonly("subject", - [] (const x509& object) { - return safe_string_converter(object.subject()); - }, - "Subject of the certificate") - - .def_property_readonly("raw", - [] (const x509& crt) -> py::bytes { - const std::vector& raw = crt.raw(); - return py::bytes(reinterpret_cast(raw.data()), raw.size()); - }, - "The raw bytes associated with this x509 cert (DER encoded)") - - .def_property_readonly("key_type", - &x509::key_type, - "Return the underlying public-key scheme (" RST_CLASS_REF(lief.PE.x509.KEY_TYPES) ")") - - .def_property_readonly("rsa_info", - &x509::rsa_info, - "If the underlying public-key scheme is RSA, return the " RST_CLASS_REF(lief.PE.RsaInfo) " associated with this certificate. " - "Otherwise, return None", - py::return_value_policy::take_ownership) - - .def_property_readonly("key_usage", - &x509::key_usage, - "Purpose of the key contained in the certificate (see " RST_CLASS_REF(lief.PE.x509.KEY_USAGE) ")") - - .def_property_readonly("ext_key_usage", - &x509::ext_key_usage, - "Indicates one or more purposes for which the certified public key may be used (list of OID)") - - .def_property_readonly("certificate_policies", - &x509::certificate_policies, - "Policy information terms as list of OID (see RFC #5280)") - - .def_property_readonly("is_ca", - &x509::is_ca) - - .def_property_readonly("signature", - [] (const x509& cert) -> py::bytes { - const std::vector& sig = cert.signature(); - return py::bytes(reinterpret_cast(sig.data()), sig.size()); - }, "The signature of the certificate") - - .def("verify", - static_cast(&x509::verify), - R"delim( - Verify that this certificate has been used **to trust** the given :class:`~lief.PE.x509` certificate - - It returns a set of flags defined by :class:`~lief.PE.x509.VERIFICATION_FLAGS` - - :Example: - - .. code-block:: python - - ca = lief.PE.x509.parse("ca.crt")[0] - signer = lief.PE.x509.parse("signer.crt")[0] - print(ca.verify(signer)) # lief.PE.x509.VERIFICATION_FLAGS.OK - - )delim", - "ca"_a) - - .def("is_trusted_by", - &x509::is_trusted_by, - R"delim( - Verify this certificate against a list of root CA (list of :class:`~lief.PE.x509` objects) - It returns a set of flags defined by :class:`~lief.PE.x509.VERIFICATION_FLAGS` - - :Example: - - .. code-block:: python - - signer = binary.signatures[0].signers[0] - microsoft_ca_bundle lief.PE.x509.parse("bundle.pem") - print(signer.cert.is_trusted_by(microsoft_ca_bundle)) - )delim", - "ca_list"_a) - - .def("__hash__", - [] (const x509& obj) { - return Hash::hash(obj); - }) - - .def("__str__", - [] (const x509& x509_crt) - { - std::ostringstream stream; - stream << x509_crt; - return safe_string_converter(stream.str()); - }); -} - -} -} - diff --git a/vendor/lief/api/python/PE/pyEnums.cpp b/vendor/lief/api/python/PE/pyEnums.cpp deleted file mode 100644 index 0769928..0000000 --- a/vendor/lief/api/python/PE/pyEnums.cpp +++ /dev/null @@ -1,1157 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "pyPE.hpp" -#define LIEF_PE_FORCE_UNDEF -#include "LIEF/PE/undef.h" -#include "LIEF/PE/enums.hpp" -#include "LIEF/PE/EnumToString.hpp" -#include "enums_wrapper.hpp" - -#define PY_ENUM(x) LIEF::PE::to_string(x), x - -namespace LIEF { -namespace PE { - - -void init_enums(py::module& m) { - - LIEF::enum_(m, "PE_TYPE") - .value(PY_ENUM(PE_TYPE::PE32)) - .value(PY_ENUM(PE_TYPE::PE32_PLUS)); - - LIEF::enum_(m, "MACHINE_TYPES") - .value(PY_ENUM(MACHINE_TYPES::MT_Invalid)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_UNKNOWN)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_AM33)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_AMD64)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_ARM)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_ARMNT)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_ARM64)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_EBC)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_I386)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_IA64)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_M32R)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_MIPS16)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_MIPSFPU)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_MIPSFPU16)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_POWERPC)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_POWERPCFP)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_R4000)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_SH3)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_SH3DSP)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_SH4)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_SH5)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_THUMB)) - .value(PY_ENUM(MACHINE_TYPES::IMAGE_FILE_MACHINE_WCEMIPSV2)); - - LIEF::enum_(m, "HEADER_CHARACTERISTICS", py::arithmetic()) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_RELOCS_STRIPPED)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_EXECUTABLE_IMAGE)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_LINE_NUMS_STRIPPED)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_LOCAL_SYMS_STRIPPED)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_AGGRESSIVE_WS_TRIM)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_LARGE_ADDRESS_AWARE)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_BYTES_REVERSED_LO)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_32BIT_MACHINE)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_DEBUG_STRIPPED)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_NET_RUN_FROM_SWAP)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_SYSTEM)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_DLL)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_UP_SYSTEM_ONLY)) - .value(PY_ENUM(HEADER_CHARACTERISTICS::IMAGE_FILE_BYTES_REVERSED_HI)); - - LIEF::enum_(m, "SUBSYSTEM") - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_UNKNOWN)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_NATIVE)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_WINDOWS_GUI)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_WINDOWS_CUI)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_OS2_CUI)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_POSIX_CUI)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_NATIVE_WINDOWS)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_WINDOWS_CE_GUI)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_EFI_APPLICATION)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_EFI_ROM)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_XBOX)) - .value(PY_ENUM(SUBSYSTEM::IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION)); - - LIEF::enum_(m, "DATA_DIRECTORY") - .value(PY_ENUM(DATA_DIRECTORY::EXPORT_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::IMPORT_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::RESOURCE_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::EXCEPTION_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::CERTIFICATE_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::BASE_RELOCATION_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::DEBUG)) - .value(PY_ENUM(DATA_DIRECTORY::ARCHITECTURE)) - .value(PY_ENUM(DATA_DIRECTORY::GLOBAL_PTR)) - .value(PY_ENUM(DATA_DIRECTORY::TLS_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::LOAD_CONFIG_TABLE)) - .value(PY_ENUM(DATA_DIRECTORY::BOUND_IMPORT)) - .value(PY_ENUM(DATA_DIRECTORY::IAT)) - .value(PY_ENUM(DATA_DIRECTORY::DELAY_IMPORT_DESCRIPTOR)) - .value(PY_ENUM(DATA_DIRECTORY::CLR_RUNTIME_HEADER)) - .value(PY_ENUM(DATA_DIRECTORY::RESERVED)); - - LIEF::enum_(m, "DLL_CHARACTERISTICS", py::arithmetic()) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_HIGH_ENTROPY_VA)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_NX_COMPAT)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_NO_ISOLATION)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_NO_SEH)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_NO_BIND)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_APPCONTAINER)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_WDM_DRIVER)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_GUARD_CF)) - .value(PY_ENUM(DLL_CHARACTERISTICS::IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE)); - - - LIEF::enum_(m, "SECTION_CHARACTERISTICS", py::arithmetic()) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_TYPE_NO_PAD)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_CNT_CODE)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_CNT_INITIALIZED_DATA)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_CNT_UNINITIALIZED_DATA)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_LNK_OTHER)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_LNK_INFO)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_LNK_REMOVE)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_LNK_COMDAT)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_GPREL)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_PURGEABLE)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_16BIT)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_LOCKED)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_PRELOAD)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_1BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_2BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_4BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_8BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_16BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_32BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_64BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_128BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_256BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_512BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_1024BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_2048BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_4096BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_ALIGN_8192BYTES)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_LNK_NRELOC_OVFL)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_DISCARDABLE)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_NOT_CACHED)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_NOT_PAGED)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_SHARED)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_EXECUTE)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_READ)) - .value(PY_ENUM(SECTION_CHARACTERISTICS::IMAGE_SCN_MEM_WRITE)); - - LIEF::enum_(m, "SECTION_TYPES") - .value(PY_ENUM(PE_SECTION_TYPES::TEXT)) - .value(PY_ENUM(PE_SECTION_TYPES::TLS)) - .value(PY_ENUM(PE_SECTION_TYPES::IMPORT)) - .value(PY_ENUM(PE_SECTION_TYPES::DATA)) - .value(PY_ENUM(PE_SECTION_TYPES::BSS)) - .value(PY_ENUM(PE_SECTION_TYPES::RESOURCE)) - .value(PY_ENUM(PE_SECTION_TYPES::RELOCATION)) - .value(PY_ENUM(PE_SECTION_TYPES::EXPORT)) - .value(PY_ENUM(PE_SECTION_TYPES::UNKNOWN)); - - - LIEF::enum_(m, "SYMBOL_BASE_TYPES") - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_NULL)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_VOID)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_CHAR)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_SHORT)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_INT)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_LONG)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_FLOAT)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_DOUBLE)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_STRUCT)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_UNION)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_ENUM)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_MOE)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_BYTE)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_WORD)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_UINT)) - .value(PY_ENUM(SYMBOL_BASE_TYPES::IMAGE_SYM_TYPE_DWORD)); - - - LIEF::enum_(m, "SYMBOL_COMPLEX_TYPES") - .value(PY_ENUM(SYMBOL_COMPLEX_TYPES::IMAGE_SYM_DTYPE_NULL)) - .value(PY_ENUM(SYMBOL_COMPLEX_TYPES::IMAGE_SYM_DTYPE_POINTER)) - .value(PY_ENUM(SYMBOL_COMPLEX_TYPES::IMAGE_SYM_DTYPE_FUNCTION)) - .value(PY_ENUM(SYMBOL_COMPLEX_TYPES::IMAGE_SYM_DTYPE_ARRAY)) - .value(PY_ENUM(SYMBOL_COMPLEX_TYPES::SCT_COMPLEX_TYPE_SHIFT)); - - - LIEF::enum_(m, "SYMBOL_SECTION_NUMBER") - .value(PY_ENUM(SYMBOL_SECTION_NUMBER::IMAGE_SYM_DEBUG)) - .value(PY_ENUM(SYMBOL_SECTION_NUMBER::IMAGE_SYM_ABSOLUTE)) - .value(PY_ENUM(SYMBOL_SECTION_NUMBER::IMAGE_SYM_UNDEFINED)); - - - LIEF::enum_(m, "SYMBOL_STORAGE_CLASS") - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_END_OF_FUNCTION)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_NULL)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_AUTOMATIC)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_EXTERNAL)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_STATIC)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_REGISTER)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_EXTERNAL_DEF)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_LABEL)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_UNDEFINED_LABEL)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_MEMBER_OF_STRUCT)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_UNION_TAG)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_TYPE_DEFINITION)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_UNDEFINED_STATIC)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_ENUM_TAG)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_MEMBER_OF_ENUM)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_REGISTER_PARAM)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_BIT_FIELD)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_BLOCK)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_FUNCTION)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_END_OF_STRUCT)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_FILE)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_SECTION)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_WEAK_EXTERNAL)) - .value(PY_ENUM(SYMBOL_STORAGE_CLASS::IMAGE_SYM_CLASS_CLR_TOKEN)); - - - LIEF::enum_(m, "RELOCATIONS_BASE_TYPES") - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_ABSOLUTE)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_HIGH)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_LOW)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_HIGHLOW)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_HIGHADJ)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_MIPS_JMPADDR)) - .value("ARM_MOV32A", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_ARM_MOV32A) - .value("ARM_MOV32", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_ARM_MOV32) - .value("RISCV_HI20", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_RISCV_HI20) - .value("ARM_MOV32T", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_ARM_MOV32T) - .value("THUMB_MOV32", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_THUMB_MOV32) - .value("RISCV_LOW12I", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_RISCV_LOW12I) - .value("RISCV_LOW12S", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_RISCV_LOW12S) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_SECTION)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_REL)) - .value("MIPS_JMPADDR16", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_MIPS_JMPADDR16) - .value("IA64_IMM64", RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_IA64_IMM64) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_DIR64)) - .value(PY_ENUM(RELOCATIONS_BASE_TYPES::IMAGE_REL_BASED_HIGH3ADJ)); - - - LIEF::enum_(m, "DEBUG_TYPES") - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_UNKNOWN)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_COFF)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_CODEVIEW)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_FPO)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_MISC)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_EXCEPTION)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_FIXUP)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_OMAP_TO_SRC)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_OMAP_FROM_SRC)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_BORLAND)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_CLSID)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_VC_FEATURE)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_POGO)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_ILTCG)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_MPX)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_REPRO)) - .value(PY_ENUM(DEBUG_TYPES::IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS)); - - - LIEF::enum_(m, "RESOURCE_TYPES") - .value(PY_ENUM(RESOURCE_TYPES::CURSOR)) - .value(PY_ENUM(RESOURCE_TYPES::BITMAP)) - .value(PY_ENUM(RESOURCE_TYPES::ICON)) - .value(PY_ENUM(RESOURCE_TYPES::MENU)) - .value(PY_ENUM(RESOURCE_TYPES::DIALOG)) - .value(PY_ENUM(RESOURCE_TYPES::STRING)) - .value(PY_ENUM(RESOURCE_TYPES::FONTDIR)) - .value(PY_ENUM(RESOURCE_TYPES::FONT)) - .value(PY_ENUM(RESOURCE_TYPES::ACCELERATOR)) - .value(PY_ENUM(RESOURCE_TYPES::RCDATA)) - .value(PY_ENUM(RESOURCE_TYPES::MESSAGETABLE)) - .value(PY_ENUM(RESOURCE_TYPES::GROUP_CURSOR)) - .value(PY_ENUM(RESOURCE_TYPES::GROUP_ICON)) - .value(PY_ENUM(RESOURCE_TYPES::VERSION)) - .value(PY_ENUM(RESOURCE_TYPES::DLGINCLUDE)) - .value(PY_ENUM(RESOURCE_TYPES::PLUGPLAY)) - .value(PY_ENUM(RESOURCE_TYPES::VXD)) - .value(PY_ENUM(RESOURCE_TYPES::ANICURSOR)) - .value(PY_ENUM(RESOURCE_TYPES::ANIICON)) - .value(PY_ENUM(RESOURCE_TYPES::HTML)) - .value(PY_ENUM(RESOURCE_TYPES::MANIFEST)); - - - LIEF::enum_(m, "RESOURCE_LANGS") - .value(PY_ENUM(RESOURCE_LANGS::LANG_NEUTRAL)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_INVARIANT)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_AFRIKAANS)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ALBANIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ARABIC)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ARMENIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ASSAMESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_AZERI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_BASQUE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_BELARUSIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_BANGLA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_BULGARIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_CATALAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_CHINESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_CROATIAN)) - .value("BOSNIAN", RESOURCE_LANGS::LANG_BOSNIAN) - .value(PY_ENUM(RESOURCE_LANGS::LANG_CZECH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_DANISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_DIVEHI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_DUTCH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ENGLISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ESTONIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_FAEROESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_FARSI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_FINNISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_FRENCH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_GALICIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_GEORGIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_GERMAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_GREEK)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_GUJARATI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_HEBREW)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_HINDI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_HUNGARIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ICELANDIC)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_INDONESIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ITALIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_JAPANESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KANNADA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KASHMIRI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KAZAK)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KONKANI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KOREAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_KYRGYZ)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_LATVIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_LITHUANIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MACEDONIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MALAY)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MALAYALAM)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MANIPURI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MARATHI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MONGOLIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_NEPALI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_NORWEGIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ORIYA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_POLISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_PORTUGUESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_PUNJABI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ROMANIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_RUSSIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SANSKRIT)) - .value("SERBIAN", RESOURCE_LANGS::LANG_SERBIAN) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SINDHI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SLOVAK)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SLOVENIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SPANISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SWAHILI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SWEDISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SYRIAC)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TAMIL)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TATAR)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TELUGU)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_THAI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TURKISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_UKRAINIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_URDU)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_UZBEK)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_VIETNAMESE)) - .value("GAELIC", RESOURCE_LANGS::LANG_GAELIC) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MALTESE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_MAORI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_RHAETO_ROMANCE)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SAMI)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SORBIAN)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_SUTU)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TSONGA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TSWANA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_VENDA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_XHOSA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ZULU)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_ESPERANTO)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_WALON)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_CORNISH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_WELSH)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_BRETON)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_INUKTITUT)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_IRISH)) - .value("LOWER_SORBIAN", RESOURCE_LANGS::LANG_LOWER_SORBIAN) - .value(PY_ENUM(RESOURCE_LANGS::LANG_PULAR)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_QUECHUA)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TAMAZIGHT)) - .value(PY_ENUM(RESOURCE_LANGS::LANG_TIGRINYA)) - .value("VALENCIAN", RESOURCE_LANGS::LANG_VALENCIAN); - - LIEF::enum_(m, "RESOURCE_SUBLANGS") - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_AFRIKAANS_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ALBANIAN_ALBANIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ALSATIAN_FRANCE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_AMHARIC_ETHIOPIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_ALGERIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_BAHRAIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_EGYPT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_IRAQ)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_JORDAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_KUWAIT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_LEBANON)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_LIBYA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_MOROCCO)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_OMAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_QATAR)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_SAUDI_ARABIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_SYRIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_TUNISIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_UAE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARABIC_YEMEN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ARMENIAN_ARMENIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ASSAMESE_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_AZERI_CYRILLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_AZERI_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BASHKIR_RUSSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BASQUE_BASQUE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BELARUSIAN_BELARUS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BANGLA_BANGLADESH)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BANGLA_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BOSNIAN_BOSNIA_HERZEGOVINA_CYRILLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BOSNIAN_BOSNIA_HERZEGOVINA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BRETON_FRANCE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_BULGARIAN_BULGARIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CATALAN_CATALAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CHINESE_HONGKONG)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CHINESE_MACAU)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CHINESE_SIMPLIFIED)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CHINESE_SINGAPORE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CHINESE_TRADITIONAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CORSICAN_FRANCE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CROATIAN_BOSNIA_HERZEGOVINA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CROATIAN_CROATIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CUSTOM_DEFAULT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CUSTOM_UNSPECIFIED)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_CZECH_CZECH_REPUBLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DANISH_DENMARK)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DARI_AFGHANISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DEFAULT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DIVEHI_MALDIVES)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DUTCH_BELGIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_DUTCH)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_AUS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_BELIZE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_CAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_CARIBBEAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_EIRE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_JAMAICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_MALAYSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_NZ)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_PHILIPPINES)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_SINGAPORE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_TRINIDAD)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_UK)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_US)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_ZIMBABWE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ENGLISH_IRELAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ESTONIAN_ESTONIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FAEROESE_FAROE_ISLANDS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FILIPINO_PHILIPPINES)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FINNISH_FINLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH_BELGIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH_CANADIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH_LUXEMBOURG)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH_MONACO)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH_SWISS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRENCH)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_FRISIAN_NETHERLANDS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GALICIAN_GALICIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GEORGIAN_GEORGIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GERMAN_AUSTRIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GERMAN_LIECHTENSTEIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GERMAN_LUXEMBOURG)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GERMAN_SWISS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GERMAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GREEK_GREECE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GREENLANDIC_GREENLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_GUJARATI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_HAUSA_NIGERIA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_HEBREW_ISRAEL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_HINDI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_HUNGARIAN_HUNGARY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ICELANDIC_ICELAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_IGBO_NIGERIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_INDONESIAN_INDONESIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_INUKTITUT_CANADA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_INUKTITUT_CANADA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_IRISH_IRELAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ITALIAN_SWISS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ITALIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_JAPANESE_JAPAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KANNADA_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KASHMIRI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KASHMIRI_SASIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KAZAK_KAZAKHSTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KHMER_CAMBODIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KICHE_GUATEMALA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KINYARWANDA_RWANDA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KONKANI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KOREAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_KYRGYZ_KYRGYZSTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LAO_LAO)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LATVIAN_LATVIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LITHUANIAN_CLASSIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LITHUANIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LOWER_SORBIAN_GERMANY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_LUXEMBOURGISH_LUXEMBOURG)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MACEDONIAN_MACEDONIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MALAY_BRUNEI_DARUSSALAM)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MALAY_MALAYSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MALAYALAM_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MALTESE_MALTA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MAORI_NEW_ZEALAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MAPUDUNGUN_CHILE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MARATHI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MOHAWK_MOHAWK)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MONGOLIAN_CYRILLIC_MONGOLIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_MONGOLIAN_PRC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_NEPALI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_NEPALI_NEPAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_NEUTRAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_NORWEGIAN_BOKMAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_NORWEGIAN_NYNORSK)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_OCCITAN_FRANCE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ORIYA_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PASHTO_AFGHANISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PERSIAN_IRAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_POLISH_POLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PORTUGUESE_BRAZILIAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PORTUGUESE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PUNJABI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_QUECHUA_BOLIVIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_QUECHUA_ECUADOR)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_QUECHUA_PERU)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ROMANIAN_ROMANIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ROMANSH_SWITZERLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_RUSSIAN_RUSSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_INARI_FINLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_LULE_NORWAY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_LULE_SWEDEN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_NORTHERN_FINLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_NORTHERN_NORWAY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_NORTHERN_SWEDEN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_SKOLT_FINLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_SOUTHERN_NORWAY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SAMI_SOUTHERN_SWEDEN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SANSKRIT_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SERBIAN_BOSNIA_HERZEGOVINA_CYRILLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SERBIAN_BOSNIA_HERZEGOVINA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SERBIAN_CROATIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SERBIAN_CYRILLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SERBIAN_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SINDHI_AFGHANISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SINDHI_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SINDHI_PAKISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SINHALESE_SRI_LANKA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SLOVAK_SLOVAKIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SLOVENIAN_SLOVENIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SOTHO_NORTHERN_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_ARGENTINA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_BOLIVIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_CHILE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_COLOMBIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_COSTA_RICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_DOMINICAN_REPUBLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_ECUADOR)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_EL_SALVADOR)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_GUATEMALA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_HONDURAS)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_MEXICAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_MODERN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_NICARAGUA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_PANAMA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_PARAGUAY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_PERU)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_PUERTO_RICO)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_URUGUAY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_US)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH_VENEZUELA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SPANISH)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SWAHILI_KENYA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SWEDISH_FINLAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SWEDISH)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SYRIAC_SYRIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_SYS_DEFAULT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TAJIK_TAJIKISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TAMAZIGHT_ALGERIA_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TAMIL_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TATAR_RUSSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TELUGU_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_THAI_THAILAND)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TIBETAN_PRC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TIGRIGNA_ERITREA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TSWANA_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TURKISH_TURKEY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TURKMEN_TURKMENISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UI_CUSTOM_DEFAULT)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UIGHUR_PRC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UKRAINIAN_UKRAINE)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UPPER_SORBIAN_GERMANY)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_URDU_INDIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_URDU_PAKISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UZBEK_CYRILLIC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_UZBEK_LATIN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_VIETNAMESE_VIETNAM)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_WELSH_UNITED_KINGDOM)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_WOLOF_SENEGAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_XHOSA_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_YAKUT_RUSSIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_YI_PRC)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_YORUBA_NIGERIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_ZULU_SOUTH_AFRICA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PULAR_SENEGAL)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_PUNJABI_PAKISTAN)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TSWANA_BOTSWANA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TAMIL_SRI_LANKA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TIGRINYA_ETHIOPIA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_TIGRINYA_ERITREA)) - .value(PY_ENUM(RESOURCE_SUBLANGS::SUBLANG_VALENCIAN_VALENCIA)); - - LIEF::enum_(m, "EXTENDED_WINDOW_STYLES") - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_DLGMODALFRAME)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_NOPARENTNOTIFY)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_TOPMOST)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_ACCEPTFILES)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_TRANSPARENT)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_MDICHILD)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_TOOLWINDOW)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_WINDOWEDGE)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_CLIENTEDGE)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_CONTEXTHELP)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_RIGHT)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_LEFT)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_RTLREADING)) - .value("LTRREADING", EXTENDED_WINDOW_STYLES::WS_EX_LTRREADING) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_LEFTSCROLLBAR)) - .value("RIGHTSCROLLBAR", EXTENDED_WINDOW_STYLES::WS_EX_RIGHTSCROLLBAR) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_CONTROLPARENT)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_STATICEDGE)) - .value(PY_ENUM(EXTENDED_WINDOW_STYLES::WS_EX_APPWINDOW)); - - - - LIEF::enum_(m, "WINDOW_STYLES") - .value(PY_ENUM(WINDOW_STYLES::WS_OVERLAPPED)) - .value(PY_ENUM(WINDOW_STYLES::WS_POPUP)) - .value(PY_ENUM(WINDOW_STYLES::WS_CHILD)) - .value(PY_ENUM(WINDOW_STYLES::WS_MINIMIZE)) - .value(PY_ENUM(WINDOW_STYLES::WS_VISIBLE)) - .value(PY_ENUM(WINDOW_STYLES::WS_DISABLED)) - .value(PY_ENUM(WINDOW_STYLES::WS_CLIPSIBLINGS)) - .value(PY_ENUM(WINDOW_STYLES::WS_CLIPCHILDREN)) - .value(PY_ENUM(WINDOW_STYLES::WS_MAXIMIZE)) - .value(PY_ENUM(WINDOW_STYLES::WS_CAPTION)) - .value(PY_ENUM(WINDOW_STYLES::WS_BORDER)) - .value(PY_ENUM(WINDOW_STYLES::WS_DLGFRAME)) - .value(PY_ENUM(WINDOW_STYLES::WS_VSCROLL)) - .value(PY_ENUM(WINDOW_STYLES::WS_HSCROLL)) - .value(PY_ENUM(WINDOW_STYLES::WS_SYSMENU)) - .value(PY_ENUM(WINDOW_STYLES::WS_THICKFRAME)) - .value("GROUP", WINDOW_STYLES::WS_GROUP) - .value("TABSTOP", WINDOW_STYLES::WS_TABSTOP) - .value(PY_ENUM(WINDOW_STYLES::WS_MINIMIZEBOX)) - .value(PY_ENUM(WINDOW_STYLES::WS_MAXIMIZEBOX)); - - - LIEF::enum_(m, "DIALOG_BOX_STYLES") - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_ABSALIGN)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_SYSMODAL)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_LOCALEDIT)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_SETFONT)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_MODALFRAME)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_NOIDLEMSG)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_SETFOREGROUND)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_3DLOOK)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_FIXEDSYS)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_NOFAILCREATE)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_CONTROL)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_CENTER)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_CENTERMOUSE)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_CONTEXTHELP)) - .value(PY_ENUM(DIALOG_BOX_STYLES::DS_SHELLFONT)); - - - LIEF::enum_(m, "FIXED_VERSION_OS") - .value(PY_ENUM(FIXED_VERSION_OS::VOS_UNKNOWN)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_DOS)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_NT)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS__WINDOWS16)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS__WINDOWS32)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_OS216)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_OS232)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS__PM16)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS__PM32)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_DOS_WINDOWS16)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_DOS_WINDOWS32)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_NT_WINDOWS32)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_OS216_PM16)) - .value(PY_ENUM(FIXED_VERSION_OS::VOS_OS232_PM32)); - - LIEF::enum_(m, "FIXED_VERSION_FILE_FLAGS") - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_DEBUG)) - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_INFOINFERRED)) - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_PATCHED)) - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_PRERELEASE)) - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_PRIVATEBUILD)) - .value(PY_ENUM(FIXED_VERSION_FILE_FLAGS::VS_FF_SPECIALBUILD)); - - - LIEF::enum_(m, "FIXED_VERSION_FILE_TYPES") - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_APP)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_DLL)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_DRV)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_FONT)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_STATIC_LIB)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_UNKNOWN)) - .value(PY_ENUM(FIXED_VERSION_FILE_TYPES::VFT_VXD)); - - - LIEF::enum_(m, "FIXED_VERSION_FILE_SUB_TYPES") - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_COMM)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_DISPLAY)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_INSTALLABLE)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_KEYBOARD)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_LANGUAGE)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_MOUSE)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_NETWORK)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_PRINTER)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_SOUND)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_SYSTEM)) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_DRV_VERSIONED_PRINTER)) - .value("FONT_RASTER", FIXED_VERSION_FILE_SUB_TYPES::VFT2_FONT_RASTER) - .value("FONT_TRUETYPE", FIXED_VERSION_FILE_SUB_TYPES::VFT2_FONT_TRUETYPE) - .value("FONT_VECTOR", FIXED_VERSION_FILE_SUB_TYPES::VFT2_FONT_VECTOR) - .value(PY_ENUM(FIXED_VERSION_FILE_SUB_TYPES::VFT2_UNKNOWN)); - - LIEF::enum_(m, "CODE_PAGES") - .value(PY_ENUM(CODE_PAGES::CP_IBM037)) - .value(PY_ENUM(CODE_PAGES::CP_IBM437)) - .value(PY_ENUM(CODE_PAGES::CP_IBM500)) - .value(PY_ENUM(CODE_PAGES::CP_ASMO_708)) - .value(PY_ENUM(CODE_PAGES::CP_DOS_720)) - .value(PY_ENUM(CODE_PAGES::CP_IBM737)) - .value(PY_ENUM(CODE_PAGES::CP_IBM775)) - .value(PY_ENUM(CODE_PAGES::CP_IBM850)) - .value(PY_ENUM(CODE_PAGES::CP_IBM852)) - .value(PY_ENUM(CODE_PAGES::CP_IBM855)) - .value(PY_ENUM(CODE_PAGES::CP_IBM857)) - .value(PY_ENUM(CODE_PAGES::CP_IBM00858)) - .value(PY_ENUM(CODE_PAGES::CP_IBM860)) - .value(PY_ENUM(CODE_PAGES::CP_IBM861)) - .value(PY_ENUM(CODE_PAGES::CP_DOS_862)) - .value(PY_ENUM(CODE_PAGES::CP_IBM863)) - .value(PY_ENUM(CODE_PAGES::CP_IBM864)) - .value(PY_ENUM(CODE_PAGES::CP_IBM865)) - .value(PY_ENUM(CODE_PAGES::CP_CP866)) - .value(PY_ENUM(CODE_PAGES::CP_IBM869)) - .value(PY_ENUM(CODE_PAGES::CP_IBM870)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_874)) - .value(PY_ENUM(CODE_PAGES::CP_CP875)) - .value(PY_ENUM(CODE_PAGES::CP_SHIFT_JIS)) - .value(PY_ENUM(CODE_PAGES::CP_GB2312)) - .value(PY_ENUM(CODE_PAGES::CP_KS_C_5601_1987)) - .value(PY_ENUM(CODE_PAGES::CP_BIG5)) - .value(PY_ENUM(CODE_PAGES::CP_IBM1026)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01047)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01140)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01141)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01142)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01143)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01144)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01145)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01146)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01147)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01148)) - .value(PY_ENUM(CODE_PAGES::CP_IBM01149)) - .value(PY_ENUM(CODE_PAGES::CP_UTF_16)) - .value(PY_ENUM(CODE_PAGES::CP_UNICODEFFFE)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1250)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1251)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1252)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1253)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1254)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1255)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1256)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1257)) - .value(PY_ENUM(CODE_PAGES::CP_WINDOWS_1258)) - .value(PY_ENUM(CODE_PAGES::CP_JOHAB)) - .value(PY_ENUM(CODE_PAGES::CP_MACINTOSH)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_JAPANESE)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_CHINESETRAD)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_KOREAN)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_ARABIC)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_HEBREW)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_GREEK)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_CYRILLIC)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_CHINESESIMP)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_ROMANIAN)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_UKRAINIAN)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_THAI)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_CE)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_ICELANDIC)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_TURKISH)) - .value(PY_ENUM(CODE_PAGES::CP_X_MAC_CROATIAN)) - .value(PY_ENUM(CODE_PAGES::CP_UTF_32)) - .value(PY_ENUM(CODE_PAGES::CP_UTF_32BE)) - .value(PY_ENUM(CODE_PAGES::CP_X_CHINESE_CNS)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20001)) - .value(PY_ENUM(CODE_PAGES::CP_X_CHINESE_ETEN)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20003)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20004)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20005)) - .value(PY_ENUM(CODE_PAGES::CP_X_IA5)) - .value(PY_ENUM(CODE_PAGES::CP_X_IA5_GERMAN)) - .value(PY_ENUM(CODE_PAGES::CP_X_IA5_SWEDISH)) - .value(PY_ENUM(CODE_PAGES::CP_X_IA5_NORWEGIAN)) - .value(PY_ENUM(CODE_PAGES::CP_US_ASCII)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20261)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20269)) - .value(PY_ENUM(CODE_PAGES::CP_IBM273)) - .value(PY_ENUM(CODE_PAGES::CP_IBM277)) - .value(PY_ENUM(CODE_PAGES::CP_IBM278)) - .value(PY_ENUM(CODE_PAGES::CP_IBM280)) - .value(PY_ENUM(CODE_PAGES::CP_IBM284)) - .value(PY_ENUM(CODE_PAGES::CP_IBM285)) - .value(PY_ENUM(CODE_PAGES::CP_IBM290)) - .value(PY_ENUM(CODE_PAGES::CP_IBM297)) - .value(PY_ENUM(CODE_PAGES::CP_IBM420)) - .value(PY_ENUM(CODE_PAGES::CP_IBM423)) - .value(PY_ENUM(CODE_PAGES::CP_IBM424)) - .value(PY_ENUM(CODE_PAGES::CP_X_EBCDIC_KOREANEXTENDED)) - .value(PY_ENUM(CODE_PAGES::CP_IBM_THAI)) - .value(PY_ENUM(CODE_PAGES::CP_KOI8_R)) - .value(PY_ENUM(CODE_PAGES::CP_IBM871)) - .value(PY_ENUM(CODE_PAGES::CP_IBM880)) - .value(PY_ENUM(CODE_PAGES::CP_IBM905)) - .value(PY_ENUM(CODE_PAGES::CP_IBM00924)) - .value(PY_ENUM(CODE_PAGES::CP_EUC_JP_JIS)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20936)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP20949)) - .value(PY_ENUM(CODE_PAGES::CP_CP1025)) - .value(PY_ENUM(CODE_PAGES::CP_KOI8_U)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_1)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_2)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_3)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_4)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_5)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_6)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_7)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_8)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_9)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_13)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_15)) - .value(PY_ENUM(CODE_PAGES::CP_X_EUROPA)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_8859_8_I)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_2022_JP)) - .value(PY_ENUM(CODE_PAGES::CP_CSISO2022JP)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_2022_JP_JIS)) - .value(PY_ENUM(CODE_PAGES::CP_ISO_2022_KR)) - .value(PY_ENUM(CODE_PAGES::CP_X_CP50227)) - .value(PY_ENUM(CODE_PAGES::CP_EUC_JP)) - .value(PY_ENUM(CODE_PAGES::CP_EUC_CN)) - .value(PY_ENUM(CODE_PAGES::CP_EUC_KR)) - .value(PY_ENUM(CODE_PAGES::CP_HZ_GB_2312)) - .value(PY_ENUM(CODE_PAGES::CP_GB18030)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_DE)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_BE)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_TA)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_TE)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_AS)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_OR)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_KA)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_MA)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_GU)) - .value(PY_ENUM(CODE_PAGES::CP_X_ISCII_PA)) - .value(PY_ENUM(CODE_PAGES::CP_UTF_7)) - .value(PY_ENUM(CODE_PAGES::CP_UTF_8)); - - LIEF::enum_(m, "WIN_VERSION") - .value(PY_ENUM(WIN_VERSION::WIN_UNKNOWN)) - .value(PY_ENUM(WIN_VERSION::WIN_SEH)) - .value(PY_ENUM(WIN_VERSION::WIN8_1)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_9879)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_14286)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_14383)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_14901)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_15002)) - .value(PY_ENUM(WIN_VERSION::WIN10_0_16237)); - - LIEF::enum_(m, "GUARD_CF_FLAGS", py::arithmetic()) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_NONE)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_INSTRUMENTED)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_W_INSTRUMENTED)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_FUNCTION_TABLE_PRESENT)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_EXPORT_SUPPRESSION_INFO_PRESENT)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_ENABLE_EXPORT_SUPPRESSION)) - .value(PY_ENUM(GUARD_CF_FLAGS::GCF_LONGJUMP_TABLE_PRESENT)) - .value(PY_ENUM(GUARD_CF_FLAGS::GRF_INSTRUMENTED)) - .value(PY_ENUM(GUARD_CF_FLAGS::GRF_ENABLE)) - .value(PY_ENUM(GUARD_CF_FLAGS::GRF_STRICT)); - - - LIEF::enum_(m, "CODE_VIEW_SIGNATURES") - .value(PY_ENUM(CODE_VIEW_SIGNATURES::CVS_UNKNOWN)) - .value(PY_ENUM(CODE_VIEW_SIGNATURES::CVS_PDB_70)) - .value(PY_ENUM(CODE_VIEW_SIGNATURES::CVS_PDB_20)) - .value(PY_ENUM(CODE_VIEW_SIGNATURES::CVS_CV_50)) - .value(PY_ENUM(CODE_VIEW_SIGNATURES::CVS_CV_41)); - - LIEF::enum_(m, "POGO_SIGNATURES") - .value(PY_ENUM(POGO_SIGNATURES::POGO_UNKNOWN)) - .value(PY_ENUM(POGO_SIGNATURES::POGO_LCTG)) - .value(PY_ENUM(POGO_SIGNATURES::POGO_PGI)); - - LIEF::enum_(m, "ACCELERATOR_FLAGS", py::arithmetic()) - .value(PY_ENUM(ACCELERATOR_FLAGS::FVIRTKEY)) - .value(PY_ENUM(ACCELERATOR_FLAGS::FNOINVERT)) - .value(PY_ENUM(ACCELERATOR_FLAGS::FSHIFT)) - .value(PY_ENUM(ACCELERATOR_FLAGS::FCONTROL)) - .value(PY_ENUM(ACCELERATOR_FLAGS::FALT)) - .value(PY_ENUM(ACCELERATOR_FLAGS::END)); - - LIEF::enum_(m, "ACCELERATOR_VK_CODES") - .value("VK_LBUTTON" , ACCELERATOR_VK_CODES::VK_LBUTTON) - .value("VK_RBUTTON" , ACCELERATOR_VK_CODES::VK_RBUTTON) - .value("VK_CANCEL" , ACCELERATOR_VK_CODES::VK_CANCEL) - .value("VK_MBUTTON" , ACCELERATOR_VK_CODES::VK_MBUTTON) - .value("VK_XBUTTON1" , ACCELERATOR_VK_CODES::VK_XBUTTON1) - .value("VK_XBUTTON2" , ACCELERATOR_VK_CODES::VK_XBUTTON2) - .value("VK_BACK" , ACCELERATOR_VK_CODES::VK_BACK) - .value("VK_TAB" , ACCELERATOR_VK_CODES::VK_TAB) - .value("VK_CLEAR" , ACCELERATOR_VK_CODES::VK_CLEAR) - .value("VK_RETURN" , ACCELERATOR_VK_CODES::VK_RETURN) - .value("VK_SHIFT" , ACCELERATOR_VK_CODES::VK_SHIFT) - .value("VK_CONTROL" , ACCELERATOR_VK_CODES::VK_CONTROL) - .value("VK_MENU" , ACCELERATOR_VK_CODES::VK_MENU) - .value("VK_PAUSE" , ACCELERATOR_VK_CODES::VK_PAUSE) - .value("VK_CAPITAL" , ACCELERATOR_VK_CODES::VK_CAPITAL) - .value("VK_KANA" , ACCELERATOR_VK_CODES::VK_KANA) - .value("VK_HANGUEL" , ACCELERATOR_VK_CODES::VK_HANGUEL) - .value("VK_HANGUL" , ACCELERATOR_VK_CODES::VK_HANGUL) - .value("VK_IME_ON" , ACCELERATOR_VK_CODES::VK_IME_ON) - .value("VK_JUNJA" , ACCELERATOR_VK_CODES::VK_JUNJA) - .value("VK_FINAL" , ACCELERATOR_VK_CODES::VK_FINAL) - .value("VK_HANJA" , ACCELERATOR_VK_CODES::VK_HANJA) - .value("VK_KANJI" , ACCELERATOR_VK_CODES::VK_KANJI) - .value("VK_IME_OFF" , ACCELERATOR_VK_CODES::VK_IME_OFF) - .value("VK_ESCAPE" , ACCELERATOR_VK_CODES::VK_ESCAPE) - .value("VK_CONVERT" , ACCELERATOR_VK_CODES::VK_CONVERT) - .value("VK_NONCONVERT" , ACCELERATOR_VK_CODES::VK_NONCONVERT) - .value("VK_ACCEPT" , ACCELERATOR_VK_CODES::VK_ACCEPT) - .value("VK_MODECHANGE" , ACCELERATOR_VK_CODES::VK_MODECHANGE) - .value("VK_SPACE" , ACCELERATOR_VK_CODES::VK_SPACE) - .value("VK_PRIOR" , ACCELERATOR_VK_CODES::VK_PRIOR) - .value("VK_NEXT" , ACCELERATOR_VK_CODES::VK_NEXT) - .value("VK_END" , ACCELERATOR_VK_CODES::VK_END) - .value("VK_HOME" , ACCELERATOR_VK_CODES::VK_HOME) - .value("VK_LEFT" , ACCELERATOR_VK_CODES::VK_LEFT) - .value("VK_UP" , ACCELERATOR_VK_CODES::VK_UP) - .value("VK_RIGHT" , ACCELERATOR_VK_CODES::VK_RIGHT) - .value("VK_DOWN" , ACCELERATOR_VK_CODES::VK_DOWN) - .value("VK_SELECT" , ACCELERATOR_VK_CODES::VK_SELECT) - .value("VK_PRINT" , ACCELERATOR_VK_CODES::VK_PRINT) - .value("VK_EXECUTE" , ACCELERATOR_VK_CODES::VK_EXECUTE) - .value("VK_SNAPSHOT" , ACCELERATOR_VK_CODES::VK_SNAPSHOT) - .value("VK_INSERT" , ACCELERATOR_VK_CODES::VK_INSERT) - .value("VK_DELETE" , ACCELERATOR_VK_CODES::VK_DELETE) - .value("VK_HELP" , ACCELERATOR_VK_CODES::VK_HELP) - .value("VK_0" , ACCELERATOR_VK_CODES::VK_0) - .value("VK_1" , ACCELERATOR_VK_CODES::VK_1) - .value("VK_2" , ACCELERATOR_VK_CODES::VK_2) - .value("VK_3" , ACCELERATOR_VK_CODES::VK_3) - .value("VK_4" , ACCELERATOR_VK_CODES::VK_4) - .value("VK_5" , ACCELERATOR_VK_CODES::VK_5) - .value("VK_6" , ACCELERATOR_VK_CODES::VK_6) - .value("VK_7" , ACCELERATOR_VK_CODES::VK_7) - .value("VK_8" , ACCELERATOR_VK_CODES::VK_8) - .value("VK_9" , ACCELERATOR_VK_CODES::VK_9) - .value("VK_A" , ACCELERATOR_VK_CODES::VK_A) - .value("VK_B" , ACCELERATOR_VK_CODES::VK_B) - .value("VK_C" , ACCELERATOR_VK_CODES::VK_C) - .value("VK_D" , ACCELERATOR_VK_CODES::VK_D) - .value("VK_E" , ACCELERATOR_VK_CODES::VK_E) - .value("VK_F" , ACCELERATOR_VK_CODES::VK_F) - .value("VK_G" , ACCELERATOR_VK_CODES::VK_G) - .value("VK_H" , ACCELERATOR_VK_CODES::VK_H) - .value("VK_I" , ACCELERATOR_VK_CODES::VK_I) - .value("VK_J" , ACCELERATOR_VK_CODES::VK_J) - .value("VK_K" , ACCELERATOR_VK_CODES::VK_K) - .value("VK_L" , ACCELERATOR_VK_CODES::VK_L) - .value("VK_M" , ACCELERATOR_VK_CODES::VK_M) - .value("VK_N" , ACCELERATOR_VK_CODES::VK_N) - .value("VK_O" , ACCELERATOR_VK_CODES::VK_O) - .value("VK_P" , ACCELERATOR_VK_CODES::VK_P) - .value("VK_Q" , ACCELERATOR_VK_CODES::VK_Q) - .value("VK_R" , ACCELERATOR_VK_CODES::VK_R) - .value("VK_S" , ACCELERATOR_VK_CODES::VK_S) - .value("VK_T" , ACCELERATOR_VK_CODES::VK_T) - .value("VK_U" , ACCELERATOR_VK_CODES::VK_U) - .value("VK_V" , ACCELERATOR_VK_CODES::VK_V) - .value("VK_W" , ACCELERATOR_VK_CODES::VK_W) - .value("VK_X" , ACCELERATOR_VK_CODES::VK_X) - .value("VK_Y" , ACCELERATOR_VK_CODES::VK_Y) - .value("VK_Z" , ACCELERATOR_VK_CODES::VK_Z) - .value("VK_LWIN" , ACCELERATOR_VK_CODES::VK_LWIN) - .value("VK_RWIN" , ACCELERATOR_VK_CODES::VK_RWIN) - .value("VK_APPS" , ACCELERATOR_VK_CODES::VK_APPS) - .value("VK_SLEEP" , ACCELERATOR_VK_CODES::VK_SLEEP) - .value("VK_NUMPAD0" , ACCELERATOR_VK_CODES::VK_NUMPAD0) - .value("VK_NUMPAD1" , ACCELERATOR_VK_CODES::VK_NUMPAD1) - .value("VK_NUMPAD2" , ACCELERATOR_VK_CODES::VK_NUMPAD2) - .value("VK_NUMPAD3" , ACCELERATOR_VK_CODES::VK_NUMPAD3) - .value("VK_NUMPAD4" , ACCELERATOR_VK_CODES::VK_NUMPAD4) - .value("VK_NUMPAD5" , ACCELERATOR_VK_CODES::VK_NUMPAD5) - .value("VK_NUMPAD6" , ACCELERATOR_VK_CODES::VK_NUMPAD6) - .value("VK_NUMPAD7" , ACCELERATOR_VK_CODES::VK_NUMPAD7) - .value("VK_NUMPAD8" , ACCELERATOR_VK_CODES::VK_NUMPAD8) - .value("VK_NUMPAD9" , ACCELERATOR_VK_CODES::VK_NUMPAD9) - .value("VK_MULTIPLY" , ACCELERATOR_VK_CODES::VK_MULTIPLY) - .value("VK_ADD" , ACCELERATOR_VK_CODES::VK_ADD) - .value("VK_SEPARATOR" , ACCELERATOR_VK_CODES::VK_SEPARATOR) - .value("VK_SUBTRACT" , ACCELERATOR_VK_CODES::VK_SUBTRACT) - .value("VK_DECIMAL" , ACCELERATOR_VK_CODES::VK_DECIMAL) - .value("VK_DIVIDE" , ACCELERATOR_VK_CODES::VK_DIVIDE) - .value("VK_F1" , ACCELERATOR_VK_CODES::VK_F1) - .value("VK_F2" , ACCELERATOR_VK_CODES::VK_F2) - .value("VK_F3" , ACCELERATOR_VK_CODES::VK_F3) - .value("VK_F4" , ACCELERATOR_VK_CODES::VK_F4) - .value("VK_F5" , ACCELERATOR_VK_CODES::VK_F5) - .value("VK_F6" , ACCELERATOR_VK_CODES::VK_F6) - .value("VK_F7" , ACCELERATOR_VK_CODES::VK_F7) - .value("VK_F8" , ACCELERATOR_VK_CODES::VK_F8) - .value("VK_F9" , ACCELERATOR_VK_CODES::VK_F9) - .value("VK_F10" , ACCELERATOR_VK_CODES::VK_F10) - .value("VK_F11" , ACCELERATOR_VK_CODES::VK_F11) - .value("VK_F12" , ACCELERATOR_VK_CODES::VK_F12) - .value("VK_F13" , ACCELERATOR_VK_CODES::VK_F13) - .value("VK_F14" , ACCELERATOR_VK_CODES::VK_F14) - .value("VK_F15" , ACCELERATOR_VK_CODES::VK_F15) - .value("VK_F16" , ACCELERATOR_VK_CODES::VK_F16) - .value("VK_F17" , ACCELERATOR_VK_CODES::VK_F17) - .value("VK_F18" , ACCELERATOR_VK_CODES::VK_F18) - .value("VK_F19" , ACCELERATOR_VK_CODES::VK_F19) - .value("VK_F20" , ACCELERATOR_VK_CODES::VK_F20) - .value("VK_F21" , ACCELERATOR_VK_CODES::VK_F21) - .value("VK_F22" , ACCELERATOR_VK_CODES::VK_F22) - .value("VK_F23" , ACCELERATOR_VK_CODES::VK_F23) - .value("VK_F24" , ACCELERATOR_VK_CODES::VK_F24) - .value("VK_NUMLOCK" , ACCELERATOR_VK_CODES::VK_NUMLOCK) - .value("VK_SCROLL" , ACCELERATOR_VK_CODES::VK_SCROLL) - .value("VK_LSHIFT" , ACCELERATOR_VK_CODES::VK_LSHIFT) - .value("VK_RSHIFT" , ACCELERATOR_VK_CODES::VK_RSHIFT) - .value("VK_LCONTROL" , ACCELERATOR_VK_CODES::VK_LCONTROL) - .value("VK_RCONTROL" , ACCELERATOR_VK_CODES::VK_RCONTROL) - .value("VK_LMENU" , ACCELERATOR_VK_CODES::VK_LMENU) - .value("VK_RMENU" , ACCELERATOR_VK_CODES::VK_RMENU) - .value("VK_BROWSER_BACK" , ACCELERATOR_VK_CODES::VK_BROWSER_BACK) - .value("VK_BROWSER_FORWARD" , ACCELERATOR_VK_CODES::VK_BROWSER_FORWARD) - .value("VK_BROWSER_REFRESH" , ACCELERATOR_VK_CODES::VK_BROWSER_REFRESH) - .value("VK_BROWSER_STOP" , ACCELERATOR_VK_CODES::VK_BROWSER_STOP) - .value("VK_BROWSER_SEARCH" , ACCELERATOR_VK_CODES::VK_BROWSER_SEARCH) - .value("VK_BROWSER_FAVORITES" , ACCELERATOR_VK_CODES::VK_BROWSER_FAVORITES) - .value("VK_BROWSER_HOME" , ACCELERATOR_VK_CODES::VK_BROWSER_HOME) - .value("VK_VOLUME_MUTE" , ACCELERATOR_VK_CODES::VK_VOLUME_MUTE) - .value("VK_VOLUME_DOWN" , ACCELERATOR_VK_CODES::VK_VOLUME_DOWN) - .value("VK_VOLUME_UP" , ACCELERATOR_VK_CODES::VK_VOLUME_UP) - .value("VK_MEDIA_NEXT_TRACK" , ACCELERATOR_VK_CODES::VK_MEDIA_NEXT_TRACK) - .value("VK_MEDIA_PREV_TRACK" , ACCELERATOR_VK_CODES::VK_MEDIA_PREV_TRACK) - .value("VK_MEDIA_STOP" , ACCELERATOR_VK_CODES::VK_MEDIA_STOP) - .value("VK_MEDIA_PLAY_PAUSE" , ACCELERATOR_VK_CODES::VK_MEDIA_PLAY_PAUSE) - .value("VK_LAUNCH_MAIL" , ACCELERATOR_VK_CODES::VK_LAUNCH_MAIL) - .value("VK_LAUNCH_MEDIA_SELECT" , ACCELERATOR_VK_CODES::VK_LAUNCH_MEDIA_SELECT) - .value("VK_LAUNCH_APP1" , ACCELERATOR_VK_CODES::VK_LAUNCH_APP1) - .value("VK_LAUNCH_APP2" , ACCELERATOR_VK_CODES::VK_LAUNCH_APP2) - .value("VK_OEM_1" , ACCELERATOR_VK_CODES::VK_OEM_1) - .value("VK_OEM_PLUS" , ACCELERATOR_VK_CODES::VK_OEM_PLUS) - .value("VK_OEM_COMMA" , ACCELERATOR_VK_CODES::VK_OEM_COMMA) - .value("VK_OEM_MINUS" , ACCELERATOR_VK_CODES::VK_OEM_MINUS) - .value("VK_OEM_PERIOD" , ACCELERATOR_VK_CODES::VK_OEM_PERIOD) - .value("VK_OEM_2" , ACCELERATOR_VK_CODES::VK_OEM_2) - .value("VK_OEM_4" , ACCELERATOR_VK_CODES::VK_OEM_4) - .value("VK_OEM_5" , ACCELERATOR_VK_CODES::VK_OEM_5) - .value("VK_OEM_6" , ACCELERATOR_VK_CODES::VK_OEM_6) - .value("VK_OEM_7" , ACCELERATOR_VK_CODES::VK_OEM_7) - .value("VK_OEM_8" , ACCELERATOR_VK_CODES::VK_OEM_8) - .value("VK_OEM_102" , ACCELERATOR_VK_CODES::VK_OEM_102) - .value("VK_PROCESSKEY" , ACCELERATOR_VK_CODES::VK_PROCESSKEY) - .value("VK_PACKET" , ACCELERATOR_VK_CODES::VK_PACKET) - .value("VK_ATTN" , ACCELERATOR_VK_CODES::VK_ATTN) - .value("VK_CRSEL" , ACCELERATOR_VK_CODES::VK_CRSEL) - .value("VK_EXSEL" , ACCELERATOR_VK_CODES::VK_EXSEL) - .value("VK_EREOF" , ACCELERATOR_VK_CODES::VK_EREOF) - .value("VK_PLAY" , ACCELERATOR_VK_CODES::VK_PLAY) - .value("VK_ZOOM" , ACCELERATOR_VK_CODES::VK_ZOOM) - .value("VK_NONAME" , ACCELERATOR_VK_CODES::VK_NONAME) - .value("VK_PA1" , ACCELERATOR_VK_CODES::VK_PA1) - .value("VK_OEM_CLEAR" , ACCELERATOR_VK_CODES::VK_OEM_CLEAR); - - LIEF::enum_(m, "ALGORITHMS") - .value(PY_ENUM(ALGORITHMS::UNKNOWN)) - .value(PY_ENUM(ALGORITHMS::SHA_512)) - .value(PY_ENUM(ALGORITHMS::SHA_384)) - .value(PY_ENUM(ALGORITHMS::SHA_256)) - .value(PY_ENUM(ALGORITHMS::SHA_1)) - .value(PY_ENUM(ALGORITHMS::MD5)) - .value(PY_ENUM(ALGORITHMS::MD4)) - .value(PY_ENUM(ALGORITHMS::MD2)) - .value(PY_ENUM(ALGORITHMS::RSA)) - .value(PY_ENUM(ALGORITHMS::EC)) - - .value(PY_ENUM(ALGORITHMS::MD5_RSA)) - .value(PY_ENUM(ALGORITHMS::SHA1_DSA)) - .value(PY_ENUM(ALGORITHMS::SHA1_RSA)) - - .value(PY_ENUM(ALGORITHMS::SHA_256_RSA)) - .value(PY_ENUM(ALGORITHMS::SHA_384_RSA)) - .value(PY_ENUM(ALGORITHMS::SHA_512_RSA)) - - .value(PY_ENUM(ALGORITHMS::SHA1_ECDSA)) - .value(PY_ENUM(ALGORITHMS::SHA_256_ECDSA)) - .value(PY_ENUM(ALGORITHMS::SHA_384_ECDSA)) - .value(PY_ENUM(ALGORITHMS::SHA_512_ECDSA)); - - - LIEF::enum_(m, "SIG_ATTRIBUTE_TYPES") - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::UNKNOWN)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::CONTENT_TYPE)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::GENERIC_TYPE)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::SPC_SP_OPUS_INFO)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::MS_COUNTER_SIGN)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::MS_SPC_NESTED_SIGN)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::MS_SPC_STATEMENT_TYPE)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::PKCS9_AT_SEQUENCE_NUMBER)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::PKCS9_COUNTER_SIGNATURE)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::PKCS9_MESSAGE_DIGEST)) - .value(PY_ENUM(SIG_ATTRIBUTE_TYPES::PKCS9_SIGNING_TIME)); -} - -} -} diff --git a/vendor/lief/api/python/PE/pyPE.cpp b/vendor/lief/api/python/PE/pyPE.cpp deleted file mode 100644 index 8ec6206..0000000 --- a/vendor/lief/api/python/PE/pyPE.cpp +++ /dev/null @@ -1,114 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * Copyright 2017 - 2021 K. Nakagawa - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/PE/signature/OIDToString.hpp" - -#include "pyPE.hpp" - -namespace LIEF { -namespace PE { - -void init_python_module(py::module& m) { - py::module LIEF_PE_module = m.def_submodule("PE", "Python API for the LIEF's PE format"); - - init_enums(LIEF_PE_module); - init_objects(LIEF_PE_module); - init_utils(LIEF_PE_module); - - LIEF_PE_module.def("oid_to_string", - &oid_to_string, - "Convert an OID to a human-readable string"); - - - // Opaque containers - py::bind_vector>(m, "ListLangCodeItem"); - py::bind_map(m, "DictStringVersion"); -} - -void init_objects(py::module& m) { - CREATE(Parser, m); - - CREATE(DosHeader, m); - CREATE(Header, m); - CREATE(OptionalHeader, m); - CREATE(RichHeader, m); - CREATE(RichEntry, m); - CREATE(DataDirectory, m); - CREATE(Section, m); - CREATE(Relocation, m); - CREATE(RelocationEntry, m); - CREATE(Export, m); - CREATE(ExportEntry, m); - CREATE(TLS, m); - CREATE(Symbol, m); - CREATE(Debug, m); - CREATE(CodeView, m); - CREATE(CodeViewPDB, m); - CREATE(Pogo, m); - CREATE(PogoEntry, m); - CREATE(Import, m); - CREATE(ImportEntry, m); - CREATE(DelayImport, m); - CREATE(DelayImportEntry, m); - CREATE(ResourcesManager, m); - CREATE(ResourceNode, m); - CREATE(ResourceData, m); - CREATE(ResourceDirectory, m); - CREATE(ResourceVersion, m); - CREATE(ResourceStringFileInfo, m); - CREATE(ResourceFixedFileInfo, m); - CREATE(ResourceVarFileInfo, m); - CREATE(LangCodeItem, m); - CREATE(ResourceIcon, m); - CREATE(ResourceDialog, m); - CREATE(ResourceDialogItem, m); - CREATE(ResourceStringTable, m); - CREATE(ResourceAccelerator, m); - CREATE(Signature, m); - CREATE(RsaInfo, m); - CREATE(x509, m); - CREATE(ContentInfo, m); - CREATE(SignerInfo, m); - CREATE(CodeIntegrity, m); - CREATE(Attribute, m); - CREATE(ContentType, m); - CREATE(GenericType, m); - CREATE(MsSpcNestedSignature, m); - CREATE(MsSpcStatementType, m); - CREATE(PKCS9AtSequenceNumber, m); - CREATE(PKCS9CounterSignature, m); - CREATE(PKCS9MessageDigest, m); - CREATE(PKCS9SigningTime, m); - CREATE(SpcSpOpusInfo, m); - - CREATE(LoadConfiguration, m); - CREATE(LoadConfigurationV0, m); - CREATE(LoadConfigurationV1, m); - CREATE(LoadConfigurationV2, m); - CREATE(LoadConfigurationV3, m); - CREATE(LoadConfigurationV4, m); - CREATE(LoadConfigurationV5, m); - CREATE(LoadConfigurationV6, m); - CREATE(LoadConfigurationV7, m); - - CREATE(Binary, m); - CREATE(Builder, m); - -} - - -} -} diff --git a/vendor/lief/api/python/PE/pyPE.hpp b/vendor/lief/api/python/PE/pyPE.hpp deleted file mode 100644 index ae4c328..0000000 --- a/vendor/lief/api/python/PE/pyPE.hpp +++ /dev/null @@ -1,127 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * Copyright 2017 - 2021 K. Nakagawa - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_PE_H_ -#define PY_LIEF_PE_H_ - -#include -#include - -#include -#include - -#include "LIEF/PE.hpp" - -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - -namespace LIEF { -namespace PE { - -template -void create(py::module&); - -void init_python_module(py::module& m); -void init_objects(py::module&); -void init_enums(py::module&); -void init_utils(py::module&); - -SPECIALIZE_CREATE(Parser); - -SPECIALIZE_CREATE(Binary); -SPECIALIZE_CREATE(DosHeader); -SPECIALIZE_CREATE(Header); -SPECIALIZE_CREATE(OptionalHeader); -SPECIALIZE_CREATE(RichHeader); -SPECIALIZE_CREATE(RichEntry); -SPECIALIZE_CREATE(DataDirectory); -SPECIALIZE_CREATE(Section); -SPECIALIZE_CREATE(Relocation); -SPECIALIZE_CREATE(RelocationEntry); -SPECIALIZE_CREATE(Export); -SPECIALIZE_CREATE(ExportEntry); -SPECIALIZE_CREATE(TLS); -SPECIALIZE_CREATE(Symbol); -SPECIALIZE_CREATE(Debug); -SPECIALIZE_CREATE(CodeView); -SPECIALIZE_CREATE(CodeViewPDB); -SPECIALIZE_CREATE(Pogo); -SPECIALIZE_CREATE(PogoEntry); -SPECIALIZE_CREATE(Import); -SPECIALIZE_CREATE(ImportEntry); -SPECIALIZE_CREATE(DelayImport); -SPECIALIZE_CREATE(DelayImportEntry); -SPECIALIZE_CREATE(ResourceNode); -SPECIALIZE_CREATE(ResourceData); -SPECIALIZE_CREATE(ResourceDirectory); -SPECIALIZE_CREATE(ResourcesManager); -SPECIALIZE_CREATE(ResourceVersion); -SPECIALIZE_CREATE(ResourceStringFileInfo); -SPECIALIZE_CREATE(ResourceFixedFileInfo); -SPECIALIZE_CREATE(ResourceVarFileInfo); -SPECIALIZE_CREATE(LangCodeItem); -SPECIALIZE_CREATE(ResourceIcon); -SPECIALIZE_CREATE(ResourceStringTable); -SPECIALIZE_CREATE(ResourceDialog); -SPECIALIZE_CREATE(ResourceDialogItem); -SPECIALIZE_CREATE(ResourceAccelerator); - -SPECIALIZE_CREATE(Signature); -SPECIALIZE_CREATE(RsaInfo); -SPECIALIZE_CREATE(x509); -SPECIALIZE_CREATE(SignerInfo); -SPECIALIZE_CREATE(Attribute); -SPECIALIZE_CREATE(ContentInfo); -SPECIALIZE_CREATE(ContentType); -SPECIALIZE_CREATE(GenericType); -SPECIALIZE_CREATE(MsSpcNestedSignature); -SPECIALIZE_CREATE(MsSpcStatementType); -SPECIALIZE_CREATE(PKCS9AtSequenceNumber); -SPECIALIZE_CREATE(PKCS9CounterSignature); -SPECIALIZE_CREATE(PKCS9MessageDigest); -SPECIALIZE_CREATE(PKCS9SigningTime); -SPECIALIZE_CREATE(SpcSpOpusInfo); - -SPECIALIZE_CREATE(CodeIntegrity); -SPECIALIZE_CREATE(LoadConfiguration); -SPECIALIZE_CREATE(LoadConfigurationV0); -SPECIALIZE_CREATE(LoadConfigurationV1); -SPECIALIZE_CREATE(LoadConfigurationV2); -SPECIALIZE_CREATE(LoadConfigurationV3); -SPECIALIZE_CREATE(LoadConfigurationV4); -SPECIALIZE_CREATE(LoadConfigurationV5); -SPECIALIZE_CREATE(LoadConfigurationV6); -SPECIALIZE_CREATE(LoadConfigurationV7); - -SPECIALIZE_CREATE(ResourcesManager); - -SPECIALIZE_CREATE(Builder); - -} -} - - -// Opaque containers -PYBIND11_MAKE_OPAQUE(std::vector) -using dict_langcode_item = std::map; -PYBIND11_MAKE_OPAQUE(dict_langcode_item) - -#endif diff --git a/vendor/lief/api/python/PE/pyUtils.cpp b/vendor/lief/api/python/PE/pyUtils.cpp deleted file mode 100644 index f376ef7..0000000 --- a/vendor/lief/api/python/PE/pyUtils.cpp +++ /dev/null @@ -1,96 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPE.hpp" -#include "pyErr.hpp" - -#include "LIEF/PE/utils.hpp" - -namespace LIEF { -namespace PE { - -void init_utils(py::module& m) { - py::enum_(m, "IMPHASH_MODE", - "Enum to define the behavior of :func:`~lief.PE.get_imphash`") - .value("DEFAULT", IMPHASH_MODE::DEFAULT, "Default implementation") - .value("LIEF", IMPHASH_MODE::LIEF, "Same as DEFAULT") - .value("PEFILE", IMPHASH_MODE::PEFILE, "Use pefile algorithm") - .value("VT", IMPHASH_MODE::VT, "Same as PEFILE since Virus Total is using pefile"); - - m.def("is_pe", - static_cast(&is_pe), - "Check if the given file is a ``PE``", - "file"_a); - - m.def("is_pe", - static_cast&)>(&is_pe), - "Check if the given raw data is a ``PE``", - "raw"_a); - - m.def("get_type", - [] (const std::string& file) { - return error_or(static_cast (*)(const std::string&)>(&get_type), file); - }, - "If the input file is a ``PE`` one, return the " RST_CLASS_REF(lief.PE.PE_TYPE) " \n" - "If the function fails to determine the type, it returns a " RST_CLASS_REF(lief.lief_errors) "", - "file"_a); - - - m.def("get_type", - [] (const std::vector& raw) { - return error_or(static_cast (*)(const std::vector&)>(&get_type), raw); - }, - "If the input *raw* data represent a ``PE`` file, return the " RST_CLASS_REF(lief.PE.PE_TYPE) " \n" - "If the function fails to determine the type, it returns a " RST_CLASS_REF(lief.lief_errors) "", - "raw"_a); - - m.def("get_imphash", - &get_imphash, - R"delim( - Compute the hash of imported functions - - Properties of the hash generated: - - * Order agnostic - * Casse agnostic - * Ordinal (**in some extent**) agnostic - * - - If one needs the same output as Virus Total (i.e. pefile), you can use :attr:`~lief.PE.IMPHASH_MODE.PEFILE` - as second parameter. - - .. warning:: - The algorithm used to compute the *imphash* value has some variations compared to Yara, pefile, - VT implementation - - .. seealso:: - https://www.fireeye.com/blog/threat-research/2014/01/tracking-malware-import-hashing.html - )delim", - "binary"_a, "mode"_a = IMPHASH_MODE::DEFAULT); - - m.def("resolve_ordinals", - [] (const Import& import, bool strict = false, bool use_std = false) { - return error_or(resolve_ordinals, import, strict, use_std); - }, - "Take an " RST_CLASS_REF(lief.PE.Import) " as entry and try to resolve its ordinal imports\n\n" - - "The ``strict`` boolean parameter enables to throw a " RST_CLASS_REF(lief.not_found) " exception " - "if the ordinal can't be resolved. Otherwise it skips the entry.", - "import"_a, "strict"_a = false, "use_std"_a = false, - py::return_value_policy::copy); -} - -} -} diff --git a/vendor/lief/api/python/README.md b/vendor/lief/api/python/README.md new file mode 100644 index 0000000..1040b68 --- /dev/null +++ b/vendor/lief/api/python/README.md @@ -0,0 +1,60 @@ +# About + +The purpose of this project is to provide a cross-platform library that can parse, modify and +abstract ELF, PE and MachO formats. + +Main features: + +> - **Parsing**: LIEF can parse ELF, PE, MachO, OAT, DEX, VDEX, ART and provides a user-friendly API to access format internals. +> - **Modify**: LIEF enables to modify some parts of these formats +> - **Abstract**: Three formats have common features like sections, symbols, entry point... LIEF factors them. +> - **API**: LIEF can be used in C++, Python and Rust + +LIEF Extended: + +> - DWARF/PDB Support +> - Objective-C Metadata +> - dyld shared cache + +Checkout: for the details + +# Getting Started + +```console +$ pip install lief +``` + +```python +import lief + +elf = lief.ELF.parse("/bin/ls") +for section in elf.sections: + print(section.name, len(section.content)) + +pe = lief.PE.parse("cmd.exe") +for imp in pe.imports: + print(imp.name) + +fat = lief.MachO.parse("/bin/dyld") +for macho in fat: + for sym in macho.symbols: + print(sym) +``` + +# Documentation + +- [Main documentation](https://lief.re/doc/latest/index.html) +- [API](https://lief.re/doc/latest/api/python/index.html) + +# Contact + +- **Mail**: contact at lief.re +- **Discord**: [LIEF](https://discord.gg/jGQtyAYChJ) + +# Authors + +Romain Thomas [@rh0main](https://x.com/rh0main) + +______________________________________________________________________ + +LIEF is provided under the [Apache 2.0 license](https://github.com/lief-project/LIEF/blob/0.15.1/LICENSE) diff --git a/vendor/lief/api/python/VDEX/CMakeLists.txt b/vendor/lief/api/python/VDEX/CMakeLists.txt deleted file mode 100644 index ffffd66..0000000 --- a/vendor/lief/api/python/VDEX/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -set(LIEF_PYTHON_VDEX_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyVDEX.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyUtils.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyHeader.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyParser.cpp" - "${CMAKE_CURRENT_LIST_DIR}/objects/pyFile.cpp" -) - -set(LIEF_PYTHON_VDEX_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyVDEX.hpp") - -source_group("Source Files\\VDEX" FILES ${LIEF_PYTHON_VDEX_SRC}) -source_group("Header Files\\VDEX" FILES ${LIEF_PYTHON_VDEX_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_VDEX_SRC}" "${LIEF_PYTHON_VDEX_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../") - - diff --git a/vendor/lief/api/python/VDEX/objects/pyFile.cpp b/vendor/lief/api/python/VDEX/objects/pyFile.cpp deleted file mode 100644 index d347c09..0000000 --- a/vendor/lief/api/python/VDEX/objects/pyFile.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/VDEX/File.hpp" -#include "LIEF/VDEX/hash.hpp" - -#include "pyIterators.hpp" -#include "pyVDEX.hpp" - -namespace LIEF { -namespace VDEX { - -template -using no_const_getter = T (File::*)(); - -template -using no_const_func = T (File::*)(P); - -template -using getter_t = T (File::*)() const; - -template -using setter_t = void (File::*)(T); - -template<> -void create(py::module& m) { - - // File object - py::class_ file(m, "File", "VDEX File representation"); - - /* - * it_dex_files is also registered by OAT/pyBinary.cpp and pybind11 - * seems not able to see their (limited) scope such as it raises - * generic_type: type "it_dex_files" is already registered! - * - * NOTE(romain): I tried to add py::local_module in pyIterator.hpp without - * success - */ - try { - init_ref_iterator(file, "it_dex_files"); - } catch (const std::runtime_error&) {} - - file - .def_property_readonly("header", - static_cast>(&File::header), - "Return the VDEX " RST_CLASS_REF(lief.VDEX.Header) "", - py::return_value_policy::reference) - - .def_property_readonly("dex_files", - static_cast>(&File::dex_files), - "Return an iterator over " RST_CLASS_REF(lief.DEX.File) "", - py::return_value_policy::reference) - - .def_property_readonly("dex2dex_json_info", - &File::dex2dex_json_info) - - .def("__eq__", &File::operator==) - .def("__ne__", &File::operator!=) - .def("__hash__", - [] (const File& file) { - return Hash::hash(file); - }) - - - .def("__str__", - [] (const File& file) - { - std::ostringstream stream; - stream << file; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/VDEX/objects/pyHeader.cpp b/vendor/lief/api/python/VDEX/objects/pyHeader.cpp deleted file mode 100644 index a0e81a8..0000000 --- a/vendor/lief/api/python/VDEX/objects/pyHeader.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/VDEX/Header.hpp" -#include "LIEF/VDEX/hash.hpp" - -#include "pyVDEX.hpp" - -namespace LIEF { -namespace VDEX { - -template -using getter_t = T (Header::*)(void) const; - -template -using setter_t = void (Header::*)(T); - -template<> -void create
(py::module& m) { - - py::class_(m, "Header", "VDEX Header representation") - - .def_property_readonly("magic", - static_cast>(&Header::magic), - "Magic value used to identify VDEX") - - .def_property_readonly("version", - static_cast>(&Header::version), - "VDEX version number") - - .def_property_readonly("nb_dex_files", - static_cast>(&Header::nb_dex_files), - "Number of " RST_CLASS_REF(lief.DEX.File) " files registered") - - .def_property_readonly("dex_size", - static_cast>(&Header::dex_size), - "Size of **all** " RST_CLASS_REF(lief.DEX.File) "") - - .def_property_readonly("verifier_deps_size", - static_cast>(&Header::verifier_deps_size), - "Size of verifier deps section") - - .def_property_readonly("quickening_info_size", - static_cast>(&Header::quickening_info_size), - "Size of quickening info section") - - .def("__eq__", &Header::operator==) - .def("__ne__", &Header::operator!=) - .def("__hash__", - [] (const Header& header) { - return Hash::hash(header); - }) - - .def("__str__", - [] (const Header& header) - { - std::ostringstream stream; - stream << header; - std::string str = stream.str(); - return str; - }); -} - -} -} - diff --git a/vendor/lief/api/python/VDEX/objects/pyParser.cpp b/vendor/lief/api/python/VDEX/objects/pyParser.cpp deleted file mode 100644 index e7d87e9..0000000 --- a/vendor/lief/api/python/VDEX/objects/pyParser.cpp +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyVDEX.hpp" - -#include "LIEF/VDEX/Parser.hpp" - -#include - -namespace LIEF { -namespace VDEX { - -template<> -void create(py::module& m) { - - // Parser (Parser) - m.def("parse", - static_cast (*) (const std::string&)>(&Parser::parse), - "Parse the given filename and return a " RST_CLASS_REF(lief.VDEX.File) " object", - "filename"_a, - py::return_value_policy::take_ownership); - - m.def("parse", - static_cast (*) (const std::vector&, const std::string&)>(&Parser::parse), - "Parse the given raw data and return a " RST_CLASS_REF(lief.VDEX.File) " object", - "raw"_a, py::arg("name") = "", - py::return_value_policy::take_ownership); - - - m.def("parse", - [] (py::object byteio, const std::string& name) { - const auto& io = py::module::import("io"); - const auto& RawIOBase = io.attr("RawIOBase"); - const auto& BufferedIOBase = io.attr("BufferedIOBase"); - const auto& TextIOBase = io.attr("TextIOBase"); - - py::object rawio; - - - if (py::isinstance(byteio, RawIOBase)) { - rawio = byteio; - } - - else if (py::isinstance(byteio, BufferedIOBase)) { - rawio = byteio.attr("raw"); - } - - else if (py::isinstance(byteio, TextIOBase)) { - rawio = byteio.attr("buffer").attr("raw"); - } - - else { - throw py::type_error(py::repr(byteio).cast().c_str()); - } - - std::string raw_str = static_cast(rawio.attr("readall")()); - std::vector raw = { - std::make_move_iterator(std::begin(raw_str)), - std::make_move_iterator(std::end(raw_str))}; - - return LIEF::VDEX::Parser::parse(std::move(raw), name); - }, - "io"_a, - "name"_a = "", - py::return_value_policy::take_ownership); -} -} -} diff --git a/vendor/lief/api/python/VDEX/pyUtils.cpp b/vendor/lief/api/python/VDEX/pyUtils.cpp deleted file mode 100644 index 5112f5b..0000000 --- a/vendor/lief/api/python/VDEX/pyUtils.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyVDEX.hpp" - -#include "LIEF/VDEX/utils.hpp" - -namespace LIEF { -namespace VDEX { - -void init_utils(py::module& m) { - - m.def("is_vdex", - static_cast(&is_vdex), - "Check if the **file** given in parameter is an VDEX", - "path"_a); - - m.def("is_vdex", - static_cast&)>(&is_vdex), - "Check if the **raw data** given in parameter is a VDEX", - "raw"_a); - - m.def("version", - static_cast(&version), - "Return the VDEX version of the **file** given in parameter", - "file"_a); - - m.def("version", - static_cast&)>(&version), - "Return the VDEX version of the **raw data** given in parameter", - "raw"_a); - - m.def("android_version", - &android_version, - "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given VDEX version ", - "vdex_version"_a); -} - -} -} - diff --git a/vendor/lief/api/python/VDEX/pyVDEX.cpp b/vendor/lief/api/python/VDEX/pyVDEX.cpp deleted file mode 100644 index 44ddc0e..0000000 --- a/vendor/lief/api/python/VDEX/pyVDEX.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyVDEX.hpp" - - -namespace LIEF { -namespace VDEX { -void init_python_module(py::module& m) { - py::module LIEF_VDEX_module = m.def_submodule("VDEX", "Python API for VDEX format"); - - init_objects(LIEF_VDEX_module); - init_utils(LIEF_VDEX_module); -} - - -void init_objects(py::module& m) { - CREATE(Parser, m); - CREATE(File, m); - CREATE(Header, m); -} - -} -} diff --git a/vendor/lief/api/python/VDEX/pyVDEX.hpp b/vendor/lief/api/python/VDEX/pyVDEX.hpp deleted file mode 100644 index 05da5f6..0000000 --- a/vendor/lief/api/python/VDEX/pyVDEX.hpp +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_VDEX_H_ -#define PY_LIEF_VDEX_H_ - -#include "LIEF/VDEX.hpp" - -#include "pyLIEF.hpp" - -#define SPECIALIZE_CREATE(X) \ - template<> \ - void create(py::module&) - -#define CREATE(X,Y) create(Y) - - -namespace LIEF { -namespace VDEX { - -template -void create(py::module&); - -void init_python_module(py::module& m); - -void init_objects(py::module&); - -void init_utils(py::module&); - - -SPECIALIZE_CREATE(Parser); -SPECIALIZE_CREATE(File); -SPECIALIZE_CREATE(Header); - -} -} - - -#endif diff --git a/vendor/lief/api/python/backend/__init__.py b/vendor/lief/api/python/backend/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/vendor/lief/api/python/backend/config.py b/vendor/lief/api/python/backend/config.py new file mode 100644 index 0000000..8901457 --- /dev/null +++ b/vendor/lief/api/python/backend/config.py @@ -0,0 +1,327 @@ +from __future__ import annotations + +import os +import platform +import sysconfig +from pathlib import Path +from typing import Annotated, Any, Literal + +import tomli +from pydantic import BaseModel, Field, GetCoreSchemaHandler, ValidationError +from pydantic_core import CoreSchema, ErrorDetails, core_schema +from scikit_build_core._logging import rich_print + + +def cmake_serialize(field: Any): + if isinstance(field, bool): + return "ON" if field else "OFF" + return field + + +class EnvStringValidator: + def _get_env_string(self, string: str) -> str: + winpy_architecture = os.getenv("LIEF_TARGET_ARCHITECTURE", "") + if winpy_architecture == "x86_64": + winpy_architecture = "amd64" + formatted = string.format( + python_version=os.getenv("LIEF_TARGET_PYTHON_VERSION", ""), + python_version_alt=os.getenv("LIEF_TARGET_PYTHON_VERSION", "").replace( + ".", "" + ), + architecture=os.getenv("LIEF_TARGET_ARCHITECTURE", ""), + winpy_architecture=winpy_architecture, + ci_project_dir=os.getenv("CI_PROJECT_DIR", ""), + stable_abi=os.getenv("LIEF_STABLE_ABI", ""), + free_threaded=os.getenv("LIEF_FREE_THREADED", ""), + runtime=os.getenv("LIEF_RUNTIME", "false"), + ) + return formatted + + def __get_pydantic_core_schema__( + self, source_type: Any, handler: GetCoreSchemaHandler + ) -> CoreSchema: + return core_schema.no_info_after_validator_function( + self._get_env_string, handler(source_type) + ) + + +EnvString = Annotated[str, EnvStringValidator()] + + +class BuildConfig(BaseModel): + build_type: EnvString = Field("Release", alias="type") + cache: bool = True + ninja: bool = False + stable_abi: bool | EnvString = Field(False, alias="stable-abi") + free_threaded: bool | EnvString | None = Field(None, alias="free-threaded") + default_target: str = Field("pyLIEF", alias="default-target") + parallel_jobs: int = Field(0, alias="parallel-jobs") + compilation_flags: list[str] = Field([], alias="compilation-flags") + lief_extra_compilation_flags: list[str] = Field( + [], alias="lief-extra-compilation-flags" + ) + build_dir: EnvString | None = Field(None, alias="build-dir") + extra_targets: list[EnvString] | EnvString = Field([], alias="extra-targets") + extra_cmake: list[EnvString] | EnvString = Field([], alias="extra-cmake-opt") + lief_install_dir: EnvString | None = Field(None, alias="lief-install-dir") + py_api: EnvString = Field("", alias="py-api") + c_compiler: EnvString | None = Field(None, alias="c-compiler") + cxx_compiler: EnvString | None = Field(None, alias="cxx-compiler") + + @property + def targets(self) -> list[str]: + default_targets: list[str] = [self.default_target] + if self.extra_targets is not None: + if isinstance(self.extra_targets, str): + default_targets.append(self.extra_targets) + else: + default_targets.extend(self.extra_targets) + + return default_targets + + def cmake_dump(self) -> list[str]: + out: list[str] = [f"-DLIEF_USE_CCACHE={cmake_serialize(self.cache)}"] + + if self.extra_cmake is not None: + if isinstance(self.extra_cmake, str): + out.append(self.extra_cmake) + elif isinstance(self.extra_cmake, list): + out.extend(self.extra_cmake) + + if self.lief_install_dir is not None: + lief_cmake_dir = Path(self.lief_install_dir) / "lib" / "cmake" / "LIEF" + lief_dir = lief_cmake_dir.expanduser().resolve() + + if not lief_dir.is_dir(): + raise RuntimeError(f"Invalid install dir: {lief_cmake_dir}") + + out.extend( + ( + "-DLIEF_PY_LIEF_EXT=on", + "-DLIEF_INSTALL=off", + f"-DLIEF_DIR={lief_dir.as_posix()}", + ) + ) + + if self.c_compiler is not None: + out.append(f"-DCMAKE_C_COMPILER={self.c_compiler}") + + if self.cxx_compiler is not None: + out.append(f"-DCMAKE_CXX_COMPILER={self.cxx_compiler}") + + if len(self.compilation_flags) > 0: + flags = " ".join(self.compilation_flags) + out.extend( + ( + f"-DCMAKE_CXX_FLAGS={flags}", + f"-DCMAKE_C_FLAGS={flags}", + ) + ) + + if len(self.lief_extra_compilation_flags) > 0: + flags = ";".join(self.lief_extra_compilation_flags) + out.extend((f"-DLIEF_EXTRA_FLAGS={flags}",)) + + free_threaded = self.free_threaded + if free_threaded is None: + free_threaded = bool(sysconfig.get_config_var("Py_GIL_DISABLED")) + + out.extend( + [ + f"-DLIEF_PYTHON_STABLE_ABI={cmake_serialize(self.stable_abi)}", + f"-DLIEF_PYTHON_FREE_THREADED={cmake_serialize(free_threaded)}", + ] + ) + + return out + + +class ThirdParty(BaseModel): + spdlog: EnvString | None = None + nanobind: EnvString | None = None + + def cmake_dump(self) -> list[str]: + out: list[str] = [] + if self.spdlog is not None: + out.extend(("-DLIEF_EXTERNAL_SPDLOG=ON", f"-Dspdlog_DIR={self.spdlog}")) + + if self.nanobind is not None: + out.extend( + ("-DLIEF_OPT_NANOBIND_EXTERNAL=ON", f"-Dnanobind_DIR={self.nanobind}") + ) + + return out + + +class CrossCompilation(BaseModel): + osx_arch: EnvString | None = Field(None, alias="osx-arch") + platform: EnvString | None = None + pyversion: EnvString | None = None + abi: EnvString | None = None + + def cmake_dump(self) -> list[str]: + out: list[str] = [] + if self.osx_arch is not None: + out.extend((f"-DCMAKE_OSX_ARCHITECTURES={self.osx_arch}",)) + return out + + +class Formats(BaseModel): + elf: bool = True + pe: bool = True + macho: bool = True + coff: bool = True + dex: bool = True + art: bool = True + oat: bool = True + vdex: bool = True + + def cmake_dump(self) -> list[str]: + return [ + f"-DLIEF_ELF={cmake_serialize(self.elf)}", + f"-DLIEF_PE={cmake_serialize(self.pe)}", + f"-DLIEF_MACHO={cmake_serialize(self.macho)}", + f"-DLIEF_COFF={cmake_serialize(self.coff)}", + f"-DLIEF_DEX={cmake_serialize(self.dex)}", + f"-DLIEF_OAT={cmake_serialize(self.oat)}", + f"-DLIEF_ART={cmake_serialize(self.art)}", + f"-DLIEF_VDEX={cmake_serialize(self.vdex)}", + ] + + +class Logging(BaseModel): + enabled: bool = True + debug: bool = False + + def cmake_dump(self) -> list[str]: + return [ + f"-DLIEF_LOGGING={cmake_serialize(self.enabled)}", + f"-DLIEF_LOGGING_DEBUG={cmake_serialize(self.debug)}", + ] + + +class Features(BaseModel): + # json is an attribute already defined in BaseModel + json_support: bool = Field(True, alias="json") + frozen: bool = True + runtime: bool | EnvString = Field(False) + + def cmake_dump(self) -> list[str]: + return [ + f"-DLIEF_RUNTIME={cmake_serialize(self.runtime)}", + f"-DLIEF_ENABLE_JSON={cmake_serialize(self.json_support)}", + f"-DLIEF_DISABLE_FROZEN={cmake_serialize(not self.frozen)}", + ] + + +class Runtime(BaseModel): + platform: Literal["linux", "windows", "android", "osx", "ios"] | None = None + architecture: EnvString | Literal["arm64", "x86_64"] | None = None + + def cmake_dump(self) -> list[str]: + out: list[str] = [] + + if self.platform is not None: + out.append(f"-DLIEF_RUNTIME_PLATFORM={self.platform}") + + if self.architecture is not None: + out.append(f"-DLIEF_RUNTIME_ARCH={self.architecture}") + + return out + + +class ConfigT(BaseModel): + build: BuildConfig = BuildConfig() + formats: Formats = Formats() + third_party: ThirdParty = Field(ThirdParty(), alias="third-party") + features: Features = Features() + logging: Logging = Logging() + runtime: Runtime = Runtime() + cross_compilation: CrossCompilation = Field( + CrossCompilation(), alias="cross-compilation" + ) + + def _cmake_base_args(self) -> list[str]: + return [ + "-DLIEF_PYTHON_API=on", + "-DLIEF_INSTALL=off", + "-DLIEF_INSTALL_COMPILED_EXAMPLES=off", + ] + + def cmake_dump(self) -> list[str]: + return [ + *self._cmake_base_args(), + *self.build.cmake_dump(), + *self.formats.cmake_dump(), + *self.third_party.cmake_dump(), + *self.features.cmake_dump(), + *self.logging.cmake_dump(), + *self.runtime.cmake_dump(), + *self.cross_compilation.cmake_dump(), + ] + + +def pretty_error(err: ErrorDetails, file: Path): + loc = ".".join([str(e) for e in err["loc"]]) + if err["type"] == "value_error.missing": + rich_print(f"[red]'{loc}' is missing in {file}") + else: + rich_print(f"[red]Error with '{loc}' in {file} ({err['msg']})") + + +class Config: + DEFAULT_EXCLUDE: list[str] = ["*.so", "*.pyd"] + + def __init__(self, config: ConfigT): + self._config: ConfigT = config + + @classmethod + def from_file(cls, file: Path): + with open(file, "rb") as f: + toml_config = tomli.load(f) + + try: + return cls(ConfigT.model_validate(toml_config["lief"])) + except ValidationError as e: + for err in e.errors(): + pretty_error(err, file) + return None + + @property + def strip(self) -> str: + return str(self._config.build.build_type.lower() == "release") + + @property + def build_dir(self) -> str: + if bdir := os.getenv("LIEF_BUILD_DIR", None): + return bdir + + if bdir := self._config.build.build_dir: + return bdir + + return "" + + def get_cmake_args(self, editable: bool = False) -> list[str]: + cmake_args = self._config.cmake_dump() + if editable: + cmake_args.append( + "-DLIEF_PYTHON_EDITABLE=ON", + ) + return cmake_args + + @property + def cmake_generator(self) -> list[str]: + if self._config.build.ninja: + return [ + "-GNinja", + ] + return [] + + @property + def osx_arch(self) -> str: + return self.cross_compilation.osx_arch or platform.machine() + + def __getattr__(self, name): + if value := getattr(self._config, name, None): + return value + return self.__getattribute__(name) diff --git a/vendor/lief/api/python/backend/dynamic_provider.py b/vendor/lief/api/python/backend/dynamic_provider.py new file mode 100644 index 0000000..f5f4ad6 --- /dev/null +++ b/vendor/lief/api/python/backend/dynamic_provider.py @@ -0,0 +1,20 @@ +from __future__ import annotations + +from collections.abc import Mapping +from typing import Any + +from scikit_build_core._logging import rich_print +from setup import BINDING_DIR +from versioning import Versioning + + +def dynamic_metadata( + _settings: Mapping[str, Any], + _project: Mapping[str, Any], +) -> dict[str, Any]: + version = Versioning().get_version() + rich_print("{green}LIEF Version: {version}", version=version) + return { + "version": version, + "readme": (BINDING_DIR / "README.md").as_posix(), + } diff --git a/vendor/lief/api/python/backend/setup.py b/vendor/lief/api/python/backend/setup.py new file mode 100644 index 0000000..c274591 --- /dev/null +++ b/vendor/lief/api/python/backend/setup.py @@ -0,0 +1,225 @@ +from __future__ import annotations + +import os +import platform +import sys +import sysconfig +from functools import lru_cache +from pathlib import Path + +CWD = Path(__file__).parent +ROOT_DIR = CWD / ".." / ".." / ".." +BINDING_DIR = ROOT_DIR / "api" / "python" +SRC_DIR = ROOT_DIR.resolve().absolute() + +DEFAULT_CONF = CWD / ".." / "config-default.toml" + +_WHEEL_TAG_COMPUTE_BEST = None + + +@lru_cache(maxsize=1) +def get_config(): + from config import Config + + if path := os.getenv("PYLIEF_CONF"): + config_path = Path(path).resolve().absolute() + return Config.from_file(config_path) + return Config.from_file(DEFAULT_CONF) + + +def _compute_best(cls, *arg, **kwargs): + from scikit_build_core.builder.wheel_tag import WheelTag + + assert _WHEEL_TAG_COMPUTE_BEST is not None + best_tag = _WHEEL_TAG_COMPUTE_BEST(cls, *arg, **kwargs) + config = get_config() + + pyvers = best_tag.pyvers + abis = best_tag.abis + archs = best_tag.archs + + if version := config.cross_compilation.pyversion: + pyvers = [version] + + if abi := config.cross_compilation.abi: + abis = [abi] + + if platform := config.cross_compilation.platform: + archs = [platform] + + return WheelTag(pyvers, abis, archs) + + +def _get_vc_env(vc_arch: str) -> dict[str, str]: + try: + from setuptools import distutils # type: ignore + + return distutils._msvccompiler._get_vc_env(vc_arch) # type: ignore + except AttributeError: + from setuptools._distutils import _msvccompiler # type: ignore + + return _msvccompiler._get_vc_env(vc_arch) # type: ignore + + +def _fix_env(): + config = get_config() + if sys.platform.startswith("win"): + if config.build.ninja: + is64 = sys.maxsize > 2**32 + arch = "x64" if is64 else "x86" + ninja_env = _get_vc_env(arch) + os.environ.update(ninja_env) + + if sys.platform.startswith("darwin"): + deployment_target = os.getenv( + "MACOSX_DEPLOYMENT_TARGET", None + ) or sysconfig.get_config_var("MACOSX_DEPLOYMENT_TARGET") + os.environ["_PYTHON_HOST_PLATFORM"] = ( + f"macosx-{deployment_target}-{config.osx_arch}" + ) + # scikit_build_core is aware of ARCHFLAGS for the wheel arch: + # builder/builder.py:get_archs() + os.environ["ARCHFLAGS"] = f"-arch {config.osx_arch}" + + if platform := config.cross_compilation.platform: + global _WHEEL_TAG_COMPUTE_BEST + from scikit_build_core.builder.wheel_tag import WheelTag + + _WHEEL_TAG_COMPUTE_BEST = WheelTag.compute_best + WheelTag.compute_best = _compute_best # type: ignore + + os.environ["_PYTHON_HOST_PLATFORM"] = platform + + if os.name == "nt" and platform == "win32": + os.environ["VSCMD_ARG_TGT_ARCH"] = "x86" + sys.version = sys.version.lower().replace("amd64", "") + sys.platform = "win32" + + +def _get_hooked_config(is_editable: bool) -> dict[str, str | list[str]] | None: + from config import Config + + config = get_config() + + if config is None: + raise RuntimeError("Can't get the configuration") + + if config.build.py_api.startswith("cp3"): + # https://github.com/scikit-build/scikit-build-core/blob/9ac2e35aa888b70e9f1999a75dfafb7a5d709f88/src/scikit_build_core/builder/wheel_tag.py#L83-L85 + # Make sure that this check is not silently warned since it could lead + # to a wrong .whl filename + minor = int(config.build.py_api[3:]) + if sys.implementation.name != "cpython" or minor > sys.version_info.minor: + msg = f"Ignoring py-api, not a CPython interpreter ({sys.implementation.name}) or version (3.{minor}) is too high" + raise RuntimeError(msg) + + config_settings = { + "logging.level": "DEBUG", + "build-dir": config.build_dir, + "build.targets": config.build.targets, + "install.strip": config.strip, + "backport.find-python": "0", + "wheel.py-api": config.build.py_api, + "cmake.source-dir": SRC_DIR.as_posix(), + "cmake.build-type": config.build.build_type, + "cmake.args": [ + *config.cmake_generator, + *config.get_cmake_args(is_editable), + ], + "sdist.exclude": Config.DEFAULT_EXCLUDE, + } + return config_settings + + +def _get_build_requirements(is_editable: bool) -> list[str]: + build_req_file = BINDING_DIR / "build-requirements.txt" + if not build_req_file.is_file() and not (BINDING_DIR / "src").is_dir(): + # By convention this is a mocked sdist + impl = sys.implementation.name + version = "{0.major}.{0.minor}.{0.micro}".format(sys.version_info) + free_threaded = bool(sysconfig.get_config_var("Py_GIL_DISABLED")) + ft_status = "free-threaded" if free_threaded else "GIL-enabled" + print( + f"LIEF does not provide precompiled wheels for " + f"'{sys.platform} - {platform.machine()}' " + f"(Python: {impl} {version} [{ft_status}])", + file=sys.stderr, + ) + sys.exit(1) + reqs = [ + line + for line in build_req_file.read_text().splitlines() + if not line.startswith("#") + ] + return reqs + + +def get_requires_for_build_wheel( + config_settings: dict[str, str | list[str]] | None = None, +) -> list[str]: + return _get_build_requirements(is_editable=False) + + +def prepare_metadata_for_build_wheel( + metadata_directory: str, + config_settings: dict[str, str | list[str]] | None = None, +) -> str: + from scikit_build_core.build import prepare_metadata_for_build_wheel as _impl + + _fix_env() + return _impl(metadata_directory, config_settings) + + +def build_wheel(wheel_directory, config_settings=None, metadata_directory=None): + from scikit_build_core.build import build_wheel as _impl + + config_settings = _get_hooked_config(is_editable=False) + _fix_env() + return _impl(wheel_directory, config_settings, metadata_directory) + + +def get_requires_for_build_editable( + config_settings: dict[str, str | list[str]] | None = None, +) -> list[str]: + return _get_build_requirements(is_editable=True) + + +def prepare_metadata_for_build_editable( + metadata_directory: str, + config_settings: dict[str, str | list[str]] | None = None, +) -> str: + from scikit_build_core.build import prepare_metadata_for_build_editable as _impl + + _fix_env() + return _impl(metadata_directory, config_settings) + + +def build_editable( + wheel_directory: str, + config_settings: dict[str, str | list[str]] | None = None, + metadata_directory: str | None = None, +) -> str: + from scikit_build_core.build import build_editable as _impl + + config_settings = _get_hooked_config(is_editable=True) + _fix_env() + return _impl(wheel_directory, config_settings, metadata_directory) + + +def build_sdist( + sdist_directory: str, + config_settings: dict[str, str | list[str]] | None = None, +) -> str: + from scikit_build_core.build.sdist import build_sdist as _impl + + config_settings = _get_hooked_config(is_editable=False) + assert config_settings is not None + config_settings["sdist.exclude"].extend(["*"]) # type: ignore + config_settings["sdist.include"] = [ + "pyproject.toml", + "backend/setup.py", + "backend/versioning.py", + "backend/config.py", + "backend/dynamic_provider.py", + ] + return _impl(sdist_directory, config_settings) diff --git a/vendor/lief/api/python/backend/versioning.py b/vendor/lief/api/python/backend/versioning.py new file mode 100644 index 0000000..8520565 --- /dev/null +++ b/vendor/lief/api/python/backend/versioning.py @@ -0,0 +1,139 @@ +from __future__ import annotations + +import os +import re +import shlex +import subprocess +import sys +from shutil import which + +from scikit_build_core._logging import rich_print as _rich_print +from setup import ROOT_DIR + + +def rich_print(*args): + if sys.platform.startswith("win"): + # Workaround for: + # KeyError: 'WinError' + # File "[...]\scikit_build_core\_logging.py", line 122, in + # lambda m: "".join(colors()[x] for x in m.group(1).split()), + return print(*args) + return _rich_print(*args) + + +class Versioning: + COMMAND = "{git} describe --tags --long --dirty" + GIT_BRANCH = "{git} rev-parse --abbrev-ref HEAD" + IS_TAGGED_CMD = "{git} tag --list --points-at=HEAD" + FMT_DEV = "{tag}.dev0" + FMT_TAGGED = "{tag}" + CMAKE_VERSION_R = r"set\(LIEF_VERSION_(MAJOR|MINOR|PATCH)\s(\d+)\)" + + def __init__(self): + self._git = which("git") + + def _exec_git_cmd(self, cmd: str, **kwargs) -> str: + args = dict(kwargs) + args["git"] = self._git + cmd_list = shlex.split(cmd.format(**args)) + return subprocess.check_output( + cmd_list, text=True, cwd=ROOT_DIR.as_posix() + ).strip() + + def has_git(self) -> bool: + return self._git is not None and (ROOT_DIR / ".git").is_dir() + + def get_branch(self) -> str | None: + if not self.has_git(): + return None + + try: + return self._exec_git_cmd(Versioning.GIT_BRANCH) + except subprocess.SubprocessError as e: + rich_print(f"[red]Error: {e}") + return None + + def format_version(self, version: str, fmt: str, is_dev: bool = False): + branch = self.get_branch() + if branch is not None and branch.startswith("release-"): + _, version = branch.split("release-") + return version + + if branch is not None and branch.startswith("release/"): + _, version = branch.split("release/") + major, minor, patch = version.split(".") + if patch == "x": + return f"{major}.{minor}" + return version + + parts = version.split("-") + assert len(parts) in (3, 4) + dirty = len(parts) == 4 + tag, count, sha = parts[:3] + MA, MI, PA = map(int, tag.split(".")) # 0.9.0 -> (0, 9, 0) + + if is_dev: + if MI == 17: + # Special case for the 0.17.0 which is the last version of + # the 0.X.Y series + tag = "1.0.0" + else: + tag = f"{MA + 1}.{MI}.{0}" + + if count == "0" and not dirty: + return tag + return fmt.format(tag=tag, gitsha=sha.lstrip("g")) + + def version_from_git(self) -> str | None: + if not self.has_git(): + return None + + try: + is_tagged = self._exec_git_cmd(Versioning.IS_TAGGED_CMD) != "" + git_version = self._exec_git_cmd(Versioning.COMMAND) + if is_tagged: + return self.format_version( + version=git_version, fmt=Versioning.FMT_TAGGED + ) + return self.format_version( + version=git_version, fmt=Versioning.FMT_DEV, is_dev=True + ) + except Exception as e: + rich_print(f"[red]Error: {e}") + return None + + def version_from_cmake(self) -> str | None: + main_cmake = ROOT_DIR / "CMakeLists.txt" + cmakefile = main_cmake.read_text() + major: int | None = None + minor: int | None = None + patch: int | None = None + + itre = re.finditer(Versioning.CMAKE_VERSION_R, cmakefile, flags=re.MULTILINE) + + for cmake_version in itre: + typ, value = cmake_version.groups() + typ = typ.lower() + if typ == "major": + major = int(value) + elif typ == "minor": + minor = int(value) + elif typ == "patch": + patch = int(value) + + if any(e is None for e in (major, minor, patch)): + return None + + return f"{major}.{minor}.{patch}" + + def get_version(self) -> str: + if version := os.getenv("LIEF_VERSION_ENV"): + return version + + if version := self.version_from_git(): + return version + + if version := self.version_from_cmake(): + return version + + raise RuntimeError("Can't determine version") diff --git a/vendor/lief/api/python/build-requirements.txt b/vendor/lief/api/python/build-requirements.txt new file mode 100644 index 0000000..4cda8b8 --- /dev/null +++ b/vendor/lief/api/python/build-requirements.txt @@ -0,0 +1,10 @@ +tomli==2.4.1 +scikit-build-core==1.0.3 +# For Ninja: msvc.msvc14_get_vc_env +setuptools==83.0.0 +# For the "env" feature +pydantic==2.13.4 +# Implicit from scikit-build-core +pathspec==1.1.1 +build==1.5.0 +wheel==0.47.0 diff --git a/vendor/lief/api/python/config-default.toml b/vendor/lief/api/python/config-default.toml new file mode 100644 index 0000000..aca7315 --- /dev/null +++ b/vendor/lief/api/python/config-default.toml @@ -0,0 +1,24 @@ +[lief.build] +type = "Release" +cache = true +ninja = true +parallel-jobs = 0 + +[lief.formats] +elf = true +pe = true +macho = true +android = true +art = true +vdex = true +oat = true +dex = true + +[lief.features] +json = true +frozen = true +runtime = false + +[lief.logging] +enabled = true +debug = false diff --git a/vendor/lief/api/python/encoding.cpp b/vendor/lief/api/python/encoding.cpp deleted file mode 100644 index eded042..0000000 --- a/vendor/lief/api/python/encoding.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "encoding.hpp" - -py::object safe_string_converter(const std::string& str) { - auto global = py::dict(py::module::import("__main__").attr("__dict__")); - auto local = py::dict(); - py::bytes name_bytes = py::bytes(str); - local["name_bytes"] = name_bytes; - -#if PY_MAJOR_VERSION >= 3 - py::eval(R"( -encodings = ["big5", "big5hkscs", "cp037", "cp424", "cp437", "cp500", "cp737", "cp775", "cp850", "cp852", "cp855", - "cp856", "cp857", "cp860", "cp861", "cp862", "cp863", "cp864", "cp865", "cp866", "cp869", "cp874", "cp875", "cp932", "cp949", - "cp950", "cp1006", "cp1026", "cp1140", "cp1250", "cp1251", "cp1252", "cp1253", "cp1254", "cp1255", "cp1256", "cp1257", "cp1258", - "euc_jp", "euc_jis_2004", "euc_jisx0213", "euc_kr", "gb2312", "gbk", "gb18030", "hz", "iso2022_jp", "iso2022_jp_1", "iso2022_jp_2", - "iso2022_jp_2004", "iso2022_jp_3", "iso2022_jp_ext", "iso2022_kr", "latin_1", "iso8859_2", "iso8859_3", "iso8859_4", "iso8859_5", - "iso8859_6", "iso8859_7", "iso8859_8", "iso8859_9", "iso8859_10", "iso8859_13", "iso8859_14", "iso8859_15", "johab", "koi8_r", "koi8_u", - "mac_cyrillic", "mac_greek", "mac_iceland", "mac_latin2", "mac_roman", "mac_turkish", "ptcp154", "shift_jis", "shift_jis_2004", - "shift_jisx0213", "utf_32", "utf_32_be", "utf_32_le", "utf_16", "utf_16_be", "utf_16_le", "utf_7", "utf_8_sig" ] -for e in encodings: - try: - name_str = name_bytes.decode(e) - break - except (UnicodeEncodeError, UnicodeDecodeError) as e: - continue -name_str = name_bytes.decode('ascii', 'backslashreplace') - )", global, local); -#else - py::eval(R"( -def handler(err): - start = err.start - end = err.end - return (u"".join([u"\\x{0:02x}".format(ord(err.object[i])) for i in range(start,end)]),end) -import codecs -codecs.register_error('backslashreplace_', handler) -name_str = name_bytes.decode('ascii', 'backslashreplace_') - )", global, local); -#endif - return local["name_str"]; -} diff --git a/vendor/lief/api/python/encoding.hpp b/vendor/lief/api/python/encoding.hpp deleted file mode 100644 index 1dac00c..0000000 --- a/vendor/lief/api/python/encoding.hpp +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ENCODING_H_ -#define PY_LIEF_ENCODING_H_ - - -#include -#include - -namespace py = pybind11; - -py::object safe_string_converter(const std::string& str); - -#endif diff --git a/vendor/lief/api/python/enums_wrapper.hpp b/vendor/lief/api/python/enums_wrapper.hpp deleted file mode 100644 index 68c5c17..0000000 --- a/vendor/lief/api/python/enums_wrapper.hpp +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ENUMS_WRAPPER_H_ -#define PY_LIEF_ENUMS_WRAPPER_H_ -#include -#include - -#include "LIEF/visibility.h" - -namespace py = pybind11; - -namespace LIEF { - -template -class LIEF_LOCAL enum_ : public pybind11::enum_ { - public: - using py::enum_::def; - using py::enum_::def_property_readonly_static; - using Scalar = typename py::enum_::Scalar; - - template - enum_(const py::handle &scope, const char *name, const Extra&... extra) : - py::enum_{scope, name, extra...} - { - constexpr bool is_arithmetic = py::detail::any_of...>::value; - def("__eq__", [](const Type &value, Scalar value2) { return (Scalar) value == value2; }); - def("__ne__", [](const Type &value, Scalar value2) { return (Scalar) value != value2; }); - if (is_arithmetic) { - def("__lt__", [](const Type &value, Scalar value2) { return (Scalar) value < value2; }); - def("__gt__", [](const Type &value, Scalar value2) { return (Scalar) value > value2; }); - def("__le__", [](const Type &value, Scalar value2) { return (Scalar) value <= value2; }); - def("__ge__", [](const Type &value, Scalar value2) { return (Scalar) value >= value2; }); - def("__invert__", [](const Type &value) { return ~((Scalar) value); }); - def("__and__", [](const Type &value, Scalar value2) { return (Scalar) value & value2; }); - def("__or__", [](const Type &value, Scalar value2) { return (Scalar) value | value2; }); - def("__xor__", [](const Type &value, Scalar value2) { return (Scalar) value ^ value2; }); - def("__rand__", [](const Type &value, Scalar value2) { return (Scalar) value & value2; }); - def("__ror__", [](const Type &value, Scalar value2) { return (Scalar) value | value2; }); - def("__rxor__", [](const Type &value, Scalar value2) { return (Scalar) value ^ value2; }); - def("__and__", [](const Type &value, const Type &value2) { return (Scalar) value & (Scalar) value2; }); - def("__or__", [](const Type &value, const Type &value2) { return (Scalar) value | (Scalar) value2; }); - def("__xor__", [](const Type &value, const Type &value2) { return (Scalar) value ^ (Scalar) value2; }); - } - } -}; - -} - -#endif diff --git a/vendor/lief/api/python/examples/abstract_json.py b/vendor/lief/api/python/examples/abstract_json.py new file mode 100755 index 0000000..2224a6e --- /dev/null +++ b/vendor/lief/api/python/examples/abstract_json.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +"""Dump the *abstract* view of a binary (ELF / PE / Mach-O) as JSON. + +The abstract layer exposes the subset of information shared by every +supported executable format (sections, symbols, relocations, ...). This +script parses the input file, converts its abstract representation to +JSON via ``lief.to_json`` and pretty-prints it. + +Example: + + $ python abstract_json.py /bin/ls +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to an ELF, PE or Mach-O binary") + args = parser.parse_args() + + binary = lief.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}'", file=sys.stderr) + return 1 + if isinstance(binary, lief.COFF.Binary): + print("COFF objects do not expose an abstract view", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(binary.abstract)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/abstract_reader.py b/vendor/lief/api/python/examples/abstract_reader.py new file mode 100755 index 0000000..9f55a92 --- /dev/null +++ b/vendor/lief/api/python/examples/abstract_reader.py @@ -0,0 +1,246 @@ +#!/usr/bin/env python +"""Format-agnostic binary reader. + +Uses the abstract layer of LIEF to render the common subset of +information (header, sections, relocations, symbols, imports, +exports, libraries) for an ELF, PE or Mach-O binary. + +Example: + + $ python abstract_reader.py -a /bin/ls +""" + +import argparse +import sys +import traceback + +import lief + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_header(binary): + header = binary.header + + print("== Header ==\n") + format_str = "{:<15} {:<30}" + format_hex = "{:<15} 0x{:<13x}" + + modes_str = " - ".join([str(m).split(".")[-1] for m in header.modes]) + bitness = "" + if header.is_32: + bitness = "32-bits" + + if header.is_64: + bitness = "64-bits" + + print(format_str.format("Architecture:", str(header.architecture).split(".")[-1])) + print(format_str.format("Modes:", modes_str)) + print(format_hex.format("Entrypoint:", header.entrypoint)) + print(format_str.format("Object type:", str(header.object_type).split(".")[-1])) + print(format_str.format("Endianness:", str(header.endianness).split(".")[-1])) + print(format_str.format("Bitness:", bitness)) + print() + + +@exceptions_handler(Exception) +def print_sections(binary): + print("== Sections ==") + f_title = "|{:<30} | {:<18}| {:<18}| {:<18}| {:<9}|" + f_value = "|{:<30} | 0x{:<16x}| 0x{:<16x}| 0x{:<16x}| {:<9.2f}|" + print(f_title.format("Name", "File offset", "Size", "Virtual Address", "Entropy")) + for section in binary.sections: + print( + f_value.format( + section.name, + section.offset, + section.size, + section.virtual_address, + section.entropy, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_relocations(binary): + print("== Relocations ==") + f_title = "|{:<18} | {:<6}|" + f_value = "|0x{:<16x} | {:<6d}|" + print(f_title.format("Address", "Size")) + for relocation in binary.relocations: + print(f_value.format(relocation.address, relocation.size)) + print() + + +@exceptions_handler(Exception) +def print_symbols(binary): + + print("== Symbols ==") + + f = "|{:<30} |" + + print(f.format("Name")) + + for symbol in binary.symbols: + print(f.format(symbol.name)) + print() + + +@exceptions_handler(Exception) +def print_exported_functions(binary): + + print("== Exported functions ==") + f = "|{:<30} |" + print(f.format("Name")) + for func in binary.exported_functions: + print(f.format(func)) + print() + + +@exceptions_handler(Exception) +def print_imported_functions(binary): + + print("== Imported functions ==") + f = "|{:<30} |" + print(f.format("Name")) + for func in binary.imported_functions: + print(f.format(func)) + print() + + +@exceptions_handler(Exception) +def print_imported_libraries(binary): + + print("== Imported Libraries ==") + f = "|{:<30} |" + print(f.format("Name")) + for library in binary.libraries: + print(f.format(library)) + print() + + +def main(): + parser = argparse.ArgumentParser(usage="%(prog)s [options] ") + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + + parser.add_argument( + "-H", "--header", action="store_true", dest="show_header", help="Display header" + ) + + parser.add_argument( + "-i", + "--imported", + action="store_true", + dest="show_imported_functions", + help="Display imported functions", + ) + + parser.add_argument( + "-L", + "--libraries", + action="store_true", + dest="show_libraries", + help="Display Imported Libraries", + ) + + parser.add_argument( + "-r", + "--relocations", + action="store_true", + dest="show_relocs", + help="Display the relocations (if present)", + ) + + parser.add_argument( + "-s", + "--symbols", + action="store_true", + dest="show_symbols", + help="Display Symbols", + ) + + parser.add_argument( + "-S", + "--sections", + action="store_true", + dest="show_sections", + help="Display Sections", + ) + + parser.add_argument( + "-x", + "--exported", + action="store_true", + dest="show_exported_functions", + help="Display exported functions", + ) + + parser.add_argument("binary", metavar="", help="Target File") + + args = parser.parse_args() + + binary = lief.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}'", file=sys.stderr) + return 1 + if isinstance(binary, lief.COFF.Binary): + print("COFF objects do not expose an abstract view", file=sys.stderr) + return 1 + + binary = binary.abstract + if args.show_header or args.show_all: + print_header(binary) + + if (args.show_imported_functions or args.show_all) and len( + binary.imported_functions + ) > 0: + print_imported_functions(binary) + + if (args.show_exported_functions or args.show_all) and len( + binary.exported_functions + ) > 0: + print_exported_functions(binary) + + if (args.show_libraries or args.show_all) and len(binary.libraries) > 0: + print_imported_libraries(binary) + + if (args.show_sections or args.show_all) and len(binary.sections) > 0: + print_sections(binary) + + if (args.show_symbols or args.show_all) and len(binary.symbols) > 0: + print_symbols(binary) + + if (args.show_relocs or args.show_all) and len(binary.relocations) > 0: + print_relocations(binary) + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/dex_json.py b/vendor/lief/api/python/examples/dex_json.py new file mode 100755 index 0000000..237d5f5 --- /dev/null +++ b/vendor/lief/api/python/examples/dex_json.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python +"""Dump a DEX file (Android Dalvik bytecode) as JSON. + +Parses a ``.dex`` file and writes a pretty-printed JSON dump of its +structure (header, classes, methods, strings, ...) using +``lief.to_json``. + +Example: + + $ python dex_json.py classes.dex +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Path to a DEX file") + args = parser.parse_args() + + if not lief.is_dex(args.file): + print(f"'{args.file}' is not a DEX file", file=sys.stderr) + return 1 + + dexfile = lief.DEX.parse(args.file) + if dexfile is None: + print(f"Error: failed to parse '{args.file}'", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(dexfile)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/dex_reader.py b/vendor/lief/api/python/examples/dex_reader.py new file mode 100755 index 0000000..2113f07 --- /dev/null +++ b/vendor/lief/api/python/examples/dex_reader.py @@ -0,0 +1,257 @@ +#!/usr/bin/env python +"""Pretty-print the structure of an Android DEX file. + +Parses a ``.dex`` file with ``lief.DEX.parse`` and renders header, +classes, methods, fields, strings, types, prototypes and the map +list, selected by command-line flags. + +Example: + + $ python dex_reader.py -a classes.dex +""" + +import argparse +import shutil +import sys +import traceback + +import lief +from lief import DEX + +EXIT_STATUS = 0 +_term_size = shutil.get_terminal_size((100, 100)) +terminal_columns = _term_size.columns +terminal_rows = _term_size.lines + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + global EXIT_STATUS + print(f"{self.func.__name__} raised: {e}") + EXIT_STATUS = 1 + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_information(dexfile): + print("== Information ==") + print(f"DEX File version: {dexfile.version}") + print() + + +@exceptions_handler(Exception) +def print_header(dexfile): + print("== Header ==") + print(dexfile.header) + + +@exceptions_handler(Exception) +def print_classes(dexfile): + print("== Classes ==") + for cls in dexfile.classes: + print(cls) + + +@exceptions_handler(Exception) +def print_fields(dexfile): + print("== Fields ==") + for f in dexfile.fields: + print(f) + + +@exceptions_handler(Exception) +def print_methods(dexfile): + print("== Methods ==") + for m in dexfile.methods: + print(m) + + +@exceptions_handler(Exception) +def print_strings(dexfile): + print("== Strings ==") + for s in dexfile.strings: + print(s) + + +@exceptions_handler(Exception) +def print_types(dexfile): + print("== Types ==") + for t in dexfile.types: + print(t) + + +@exceptions_handler(Exception) +def print_prototypes(dexfile): + print("== Prototypes ==") + for t in dexfile.prototypes: + print(t) + + +@exceptions_handler(Exception) +def print_map(dexfile): + print("== Map ==") + print(dexfile.map) + + +def main(): + parser = argparse.ArgumentParser(usage="%(prog)s [options] DEX files") + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + + parser.add_argument( + "-H", "--header", action="store_true", dest="show_header", help="Display header" + ) + + parser.add_argument( + "-c", + "--classes", + action="store_true", + dest="show_classes", + help="Display classes", + ) + + parser.add_argument( + "-f", "--fields", action="store_true", dest="show_fields", help="Display Fields" + ) + + parser.add_argument( + "-m", + "--methods", + action="store_true", + dest="show_methods", + help="Display Methods", + ) + + parser.add_argument( + "-s", + "--strings", + action="store_true", + dest="show_strings", + help="Display Strings", + ) + + parser.add_argument( + "-t", "--types", action="store_true", dest="show_types", help="Display Types" + ) + + parser.add_argument( + "-p", + "--prototypes", + action="store_true", + dest="show_prototypes", + help="Display Prototypes", + ) + + parser.add_argument( + "-M", "--map", action="store_true", dest="show_map", help="Display Map" + ) + + parser.add_argument("file", metavar="", help="Target DEX File") + + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + + lief.logging.set_level(args.main_verbosity) + + dexfile = DEX.parse(args.file) + if dexfile is None: + print(f"Error: failed to parse '{args.file}' as DEX", file=sys.stderr) + return 1 + + print_information(dexfile) + + if args.show_header or args.show_all: + print_header(dexfile) + + if (args.show_classes or args.show_all) and len(dexfile.classes) > 0: + print_classes(dexfile) + + if (args.show_fields or args.show_all) and len(dexfile.fields) > 0: + print_fields(dexfile) + + if (args.show_methods or args.show_all) and len(dexfile.methods) > 0: + print_methods(dexfile) + + if (args.show_strings or args.show_all) and len(dexfile.strings) > 0: + print_strings(dexfile) + + if (args.show_types or args.show_all) and len(dexfile.types) > 0: + print_types(dexfile) + + if (args.show_prototypes or args.show_all) and len(dexfile.prototypes) > 0: + print_prototypes(dexfile) + + if args.show_map or args.show_all: + print_map(dexfile) + + return EXIT_STATUS + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/disassembler.py b/vendor/lief/api/python/examples/disassembler.py new file mode 100755 index 0000000..edee888 --- /dev/null +++ b/vendor/lief/api/python/examples/disassembler.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python +"""Disassemble instructions at an address of an ELF/PE/Mach-O binary. + +Uses LIEF's extended disassembly API to iterate over the instructions +located at the given virtual address of the binary. + +Note: only available with the extended version of LIEF. + +Example: + + $ python disassembler.py /bin/ls 0x4000 +""" + +import argparse +import sys +from pathlib import Path + +import lief + + +def disassemble(target: lief.Binary, addr: int) -> None: + for inst in target.disassemble(addr): + print(inst) + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Target binary", type=Path) + parser.add_argument( + "address", help="Address to disassemble", type=lambda x: int(x, 0) + ) + args = parser.parse_args() + + target = lief.parse(args.file) + if target is None: + print(f"Can't load: {args.file}", file=sys.stderr) + return 1 + if isinstance(target, lief.COFF.Binary): + print("COFF binaries are not supported by the disassembler", file=sys.stderr) + return 1 + + disassemble(target, args.address) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/vendor/lief/api/python/examples/dwarf_editor.py b/vendor/lief/api/python/examples/dwarf_editor.py new file mode 100755 index 0000000..5d63f26 --- /dev/null +++ b/vendor/lief/api/python/examples/dwarf_editor.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python +"""Create a companion DWARF file from a PE binary. + +Demonstrates the DWARF editor API: loads a PE binary, synthesizes a +compilation unit with one function returning a pointer to a +structure and a stack variable, then writes the result to +``/tmp/out.debug``. + +Note: only available with the extended version of LIEF. + +Example: + + $ python dwarf_editor.py program.exe +""" + +import argparse +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Input PE binary") + parser.add_argument( + "--output", + default="/tmp/out.debug", + help="Output DWARF file (default: %(default)s)", + ) + args = parser.parse_args() + + if not lief.__extended__: + print("This example requires the extended version of LIEF", file=sys.stderr) + return 1 + + pe = lief.PE.parse(args.file) + if pe is None: + print(f"Error: failed to parse '{args.file}' as PE", file=sys.stderr) + return 1 + + editor = lief.dwarf.Editor.from_binary(pe) + if editor is None: + print("Failed to create a DWARF editor", file=sys.stderr) + return 1 + + unit = editor.create_compilation_unit() + unit.set_producer("LIEF") + + func = unit.create_function("hello") + func.set_address(0x123) + + pointer_type = unit.create_structure("my_struct_t").pointer_to() + if pointer_type is None: + print("Failed to create the pointer type", file=sys.stderr) + return 1 + func.set_return_type(pointer_type) + + var = func.create_stack_variable("local_var") + var.set_stack_offset(8) + + editor.write(args.output) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/dyld_shared_cache_reader.py b/vendor/lief/api/python/examples/dyld_shared_cache_reader.py new file mode 100755 index 0000000..0e72ffd --- /dev/null +++ b/vendor/lief/api/python/examples/dyld_shared_cache_reader.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python +"""List the contents of a dyld shared cache. + +Loads an Apple ``dyld`` shared cache (single file or multi-file +directory layout) and prints the embedded libraries, the mapping +information for each page range and the UUID of the sub-caches. + +Note: only available with the extended version of LIEF. + +Example: + + $ python dyld_shared_cache_reader.py /System/Library/dyld/dyld_shared_cache_arm64e +""" + +import argparse +import sys +from pathlib import Path + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument( + "target", type=Path, help="Target dyld shared cache file or directory" + ) + args = parser.parse_args() + + target: Path = args.target + if not target.exists(): + print(f"'{target}' does not exist", file=sys.stderr) + return 1 + + dyld_cache = lief.dsc.load(target) + if dyld_cache is None: + print(f"Can't parse '{target}'", file=sys.stderr) + return 1 + + for lib in dyld_cache.libraries: + print(f"{lib.address:#016x} {lib.path}") + + for idx, info in enumerate(dyld_cache.mapping_info): + print( + f"mapping_info[{idx:02d}]: " + f"[{info.address:#016x}, {info.end_address:#016x}] -> " + f"{info.file_offset:#016x}" + ) + + for idx, subcache in enumerate(dyld_cache.subcaches): + uuid_str = ":".join(f"{e:02x}" for e in subcache.uuid) + print(f"cache[{idx:02d}]: {uuid_str} {subcache.suffix}") + + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/vendor/lief/api/python/examples/elf_bin2lib.py b/vendor/lief/api/python/examples/elf_bin2lib.py new file mode 100755 index 0000000..1952883 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_bin2lib.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python +"""Promote a PIE executable to a shared library by exporting a function. + +Takes a PIE ELF executable, declares an exported function at the +given address, and rewrites the binary so that it can be ``dlopen``-ed +and the function invoked via ``dlsym``. + +Example: + + $ python elf_bin2lib.py -n compute -o libcompute.so ./prog 0x1200 +""" + +import argparse +import sys + +import lief + + +def bin2lib(binary: lief.ELF.Binary, address: int, output: str, name: str = "") -> int: + if not binary.is_pie: + print("It only works with PIE binaries", file=sys.stderr) + return 1 + + function = binary.add_exported_function(address, name) + print("Function created:", function) + binary.write(output) + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument( + "--name", "-n", default="", help="Name of the function to create" + ) + parser.add_argument( + "--output", "-o", default="libfoo.so", help="Output name (default: %(default)s)" + ) + parser.add_argument("binary", help="The target ELF binary") + parser.add_argument( + "address", type=lambda e: int(e, 0), help="Address of the function to export" + ) + + args = parser.parse_args() + binary = lief.ELF.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}' as ELF", file=sys.stderr) + return 1 + + return bin2lib(binary, args.address, args.output, name=args.name) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_change_interpreter.py b/vendor/lief/api/python/examples/elf_change_interpreter.py new file mode 100755 index 0000000..5d20be9 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_change_interpreter.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python +"""Change the program interpreter of an ELF executable. + +Replaces the ``PT_INTERP`` entry (the ``.interp`` section) of a +dynamically-linked ELF executable with the path of another ELF +interpreter, then writes the patched binary to disk with the execute +bit set. + +Example: + + $ python elf_change_interpreter.py \\ + --output /tmp/ls_musl /bin/ls /usr/lib/ld-musl-x86_64.so.1 +""" + +import argparse +import stat +import sys +from pathlib import Path + +import lief + + +def change_interpreter( + target: Path, interpreter: Path, output: Path | None = None +) -> int: + if not target.is_file() or not lief.is_elf(target): + print(f"Wrong target! ({target})", file=sys.stderr) + return 1 + + if not interpreter.is_file() or not lief.is_elf(interpreter): + print(f"Wrong interpreter! ({interpreter})", file=sys.stderr) + return 1 + + binary = lief.ELF.parse(target) + if binary is None: + print(f"Failed to parse '{target}' as ELF", file=sys.stderr) + return 1 + + if not binary.has_interpreter: + print("The given target doesn't have an interpreter!", file=sys.stderr) + return 1 + + binary.interpreter = str(interpreter) + + output_path = output or Path(f"{target.name}_updated") + + output_path.unlink(missing_ok=True) + + binary.write(output_path) + + # Restore the execute bit that LIEF doesn't propagate. + st = output_path.stat() + output_path.chmod(st.st_mode | stat.S_IEXEC) + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument( + "-o", "--output", help="Path to the rewritten binary", default=None, type=Path + ) + parser.add_argument("target", metavar="", help="Target ELF file", type=Path) + parser.add_argument( + "interpreter", + metavar="", + help="Path to the new interpreter", + type=Path, + ) + + args = parser.parse_args() + return change_interpreter(args.target, args.interpreter, args.output) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_deps.py b/vendor/lief/api/python/examples/elf_deps.py new file mode 100755 index 0000000..47b2085 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_deps.py @@ -0,0 +1,150 @@ +#!/usr/bin/env python3 +"""Analyze ELF shared library dependencies and symbol versioning. + +A cross-platform alternative to ldd that works without executing the binary. +Lists shared library dependencies, RPATH/RUNPATH search paths, and optionally +shows imported symbol versions (useful for checking glibc compatibility). + +Inspired by conda-build's liefldd.py and Bitcoin's symbol-check.py. + +Example: + + $ python elf_deps.py /usr/bin/ls + Dependencies: /usr/bin/ls + ======================================== + Interpreter: /lib64/ld-linux-x86-64.so.2 + Type: DYN (Position-Independent Executable) + + Shared Libraries: + libselinux.so.1 + libc.so.6 + ld-linux-x86-64.so.2 + + $ python elf_deps.py --versions /usr/bin/ls + ... + Symbol Versions: + GLIBC_2.2.5 (25 symbols) + GLIBC_2.3 (1 symbols) + GLIBC_2.17 (2 symbols) +""" + +import argparse +from collections import defaultdict + +import lief + +HEADER_TYPES = { + lief.ELF.Header.FILE_TYPE.EXEC: "EXEC (Executable)", + lief.ELF.Header.FILE_TYPE.DYN: "DYN (Shared Object / PIE)", + lief.ELF.Header.FILE_TYPE.REL: "REL (Relocatable)", + lief.ELF.Header.FILE_TYPE.CORE: "CORE (Core Dump)", +} + + +def analyze_deps(filename, show_versions=False): + """Analyze ELF dependencies and symbol version requirements.""" + binary = lief.ELF.parse(filename) + if binary is None: + print(f"Error: failed to parse '{filename}' as ELF") + return False + + file_type = HEADER_TYPES.get(binary.header.file_type, str(binary.header.file_type)) + interpreter = binary.interpreter or "(none — statically linked)" + + print(f"Dependencies: {filename}") + print("=" * 48) + print(f" Interpreter: {interpreter}") + print(f" Type: {file_type}") + print(f" Arch: {binary.header.machine_type.name}") + print() + + # Shared libraries (DT_NEEDED entries) + libraries = list(binary.libraries) + if libraries: + print(" Shared Libraries:") + for lib in libraries: + print(f" {lib}") + else: + print(" Shared Libraries: (none — statically linked)") + print() + + # RPATH and RUNPATH + rpath = None + runpath = None + for entry in binary.dynamic_entries: + if isinstance(entry, lief.ELF.DynamicEntryRpath): + rpath = entry.rpath + elif isinstance(entry, lief.ELF.DynamicEntryRunPath): + runpath = entry.runpath + + if rpath or runpath: + print(" Search Paths:") + if rpath: + print(f" RPATH: {rpath}") + if runpath: + print(f" RUNPATH: {runpath}") + print() + + # Symbol versions + if show_versions: + version_counts = defaultdict(int) + version_symbols = defaultdict(list) + + for sym in binary.imported_symbols: + if not sym.has_version: + continue + version = sym.symbol_version + if not version.has_auxiliary_version: + continue + ver_name = version.symbol_version_auxiliary.name + version_counts[ver_name] += 1 + version_symbols[ver_name].append(sym.name) + + if version_counts: + print(" Symbol Versions:") + for ver_name in sorted(version_counts): + count = version_counts[ver_name] + print(f" {ver_name:<24} ({count} symbol{'s' if count != 1 else ''})") + print() + + # Show highest required version per library prefix + lib_versions = defaultdict(list) + for ver_name in version_counts: + parts = ver_name.rsplit("_", 1) + if len(parts) == 2: + lib, ver_str = parts + try: + ver_tuple = tuple(int(x) for x in ver_str.split(".")) + lib_versions[lib].append((ver_tuple, ver_name)) + except ValueError: + pass + + if lib_versions: + print(" Minimum Required Versions:") + for lib in sorted(lib_versions): + max_ver = max(lib_versions[lib], key=lambda x: x[0]) + print(f" {lib}: {max_ver[1]}") + print() + + return True + + +def main(): + parser = argparse.ArgumentParser( + description="Analyze ELF shared library dependencies" + ) + parser.add_argument("binaries", nargs="+", help="ELF binaries to analyze") + parser.add_argument( + "-v", + "--versions", + action="store_true", + help="Show imported symbol version requirements", + ) + args = parser.parse_args() + + for path in args.binaries: + analyze_deps(path, show_versions=args.versions) + + +if __name__ == "__main__": + main() diff --git a/vendor/lief/api/python/examples/elf_json.py b/vendor/lief/api/python/examples/elf_json.py new file mode 100755 index 0000000..8a17d9c --- /dev/null +++ b/vendor/lief/api/python/examples/elf_json.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python +"""Dump an ELF binary as JSON. + +Parses an ELF file and writes a pretty-printed JSON dump of the full +structure (header, sections, segments, dynamic entries, symbols, ...) +using ``lief.to_json``. + +Example: + + $ python elf_json.py /bin/ls +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to an ELF binary") + args = parser.parse_args() + + binary = lief.ELF.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}' as ELF", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(binary)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_reader.py b/vendor/lief/api/python/examples/elf_reader.py new file mode 100755 index 0000000..86368e3 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_reader.py @@ -0,0 +1,808 @@ +#!/usr/bin/env python +"""Pretty-print the structure of an ELF binary. + +Equivalent to ``readelf`` with a selection of the most useful flags +(``-h``, ``-S``, ``-l``, ``-d``, ``-s``, ``-r``, ``-V`` ...). The +target file is parsed with ``lief.ELF.parse`` and the requested +sections are rendered as formatted tables. + +Example: + + $ python elf_reader.py -a /bin/ls +""" + +import argparse +import shutil +import sys +import textwrap +import traceback + +import lief +from lief import ELF + +_term_size = shutil.get_terminal_size((110, 100)) +terminal_columns = _term_size.columns - 10 +terminal_rows = _term_size.lines + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_header(binary): + header = binary.header + identity = header.identity + + print("== Header ==\n") + format_str = "{:<30} {:<30}" + format_hex = "{:<30} 0x{:<13x}" + format_dec = "{:<30} {:<30d}" + format_ide = "{:<30} {:<02x} {:<02x} {:<02x} {:<02x}" + + eflags_str = "" + if header.machine_type == lief.ELF.ARCH.ARM: + eflags_str = " - ".join([str(s).split(".")[-1] for s in header.arm_flags_list]) + + if header.machine_type in [ + lief.ELF.ARCH.MIPS, + lief.ELF.ARCH.MIPS_RS3_LE, + lief.ELF.ARCH.MIPS_X, + ]: + eflags_str = " - ".join([str(s).split(".")[-1] for s in header.mips_flags_list]) + + if header.machine_type == lief.ELF.ARCH.PPC64: + eflags_str = " - ".join( + [str(s).split(".")[-1] for s in header.ppc64_flags_list] + ) + + if header.machine_type == lief.ELF.ARCH.HEXAGON: + eflags_str = " - ".join( + [str(s).split(".")[-1] for s in header.hexagon_flags_list] + ) + + if header.machine_type == lief.ELF.ARCH.LOONGARCH: + eflags_str = " - ".join( + [str(s).split(".")[-1] for s in header.loongarch_flags_list] + ) + print(identity) + print( + format_ide.format("Magic:", identity[0], identity[1], identity[2], identity[3]) + ) + print(format_str.format("Class:", str(header.identity_class).split(".")[-1])) + print(format_str.format("Endianness:", str(header.identity_data).split(".")[-1])) + print(format_str.format("Version:", str(header.identity_version).split(".")[-1])) + print(format_str.format("OS/ABI:", str(header.identity_os_abi).split(".")[-1])) + print(format_dec.format("ABI Version:", header.identity_abi_version)) + print(format_str.format("File Type:", str(header.file_type).split(".")[-1])) + print(format_str.format("Machine Type:", str(header.machine_type).split(".")[-1])) + print( + format_str.format( + "Object File Version:", str(header.object_file_version).split(".")[-1] + ) + ) + print(format_hex.format("Entry Point:", header.entrypoint)) + print(format_hex.format("Program Header Offset:", header.program_header_offset)) + print(format_hex.format("Section Header Offset:", header.section_header_offset)) + print(format_hex.format("Processor flags:", header.processor_flag) + eflags_str) + print(format_dec.format("Header Size:", header.header_size)) + print(format_dec.format("Program Header Size:", header.program_header_size)) + print(format_dec.format("Section Header Size:", header.section_header_size)) + print(format_dec.format("Number of segments:", header.numberof_segments)) + print(format_dec.format("Number of sections:", header.numberof_sections)) + print() + + +@exceptions_handler(Exception) +def print_sections(binary): + sections = binary.sections + if len(sections) > 0: + print("== Sections ==\n") + f_title = "|{:<30} | {:<12}| {:<17}| {:<12}| {:<10}| {:<8}| {:<8}|" + f_value = "|{:<30} | {:<12}| 0x{:<14x} | 0x{:<10x}| 0x{:<8x}| {:<8.2f}| {:<10}" + print( + f_title.format( + "Name", + "Type", + "Virtual address", + "File offset", + "Size", + "Entropy", + "Segment(s)", + ) + ) + + for section in sections: + segments_str = " - ".join( + [str(s.type).split(".")[-1] for s in section.segments] + ) + print( + f_value.format( + section.name, + str(section.type).split(".")[-1], + section.virtual_address, + section.file_offset, + section.size, + abs(section.entropy), + segments_str, + ) + ) + print() + else: + print("No sections") + + +@exceptions_handler(Exception) +def print_segments(binary): + segments = binary.segments + # Segments + if len(segments) > 0: + print("== Segments ==\n") + f_title = "|{:<30} | {:<10}| {:<18}| {:<17}| {:<17}| {:<17}| {:<19}|" + f_value = "|{:<30} | {:<10}| 0x{:<16x}| 0x{:<15x}| 0x{:<15x}| 0x{:<15x}| {}" + print( + f_title.format( + "Type", + "Flags", + "File offset", + "Virtual Address", + "Virtual Size", + "Size", + "Sections", + ) + ) + + for segment in segments: + sections = segment.sections + s = ", ".join([section.name for section in sections]) + flags_str = ["-"] * 3 + if ELF.Segment.FLAGS.R in segment: + flags_str[0] = "r" + + if ELF.Segment.FLAGS.W in segment: + flags_str[1] = "w" + + if ELF.Segment.FLAGS.X in segment: + flags_str[2] = "x" + flags_str = "".join(flags_str) + + print( + f_value.format( + str(segment.type).split(".")[-1], + flags_str, + segment.file_offset, + segment.virtual_address, + segment.virtual_size, + segment.physical_size, + s, + ) + ) + print() + else: + print("No segments") + + +@exceptions_handler(Exception) +def print_dynamic_entries(binary): + dynamic_entries = binary.dynamic_entries + # Dynamic entries + if len(dynamic_entries) == 0: + return + + print("== Dynamic entries ==\n") + f_title = "|{:<16} | {:<10}| {:<20}|" + f_value = "|{:<16} | 0x{:<8x}| {:<20}|" + print(f_title.format("Tag", "Value", "Info")) + for entry in dynamic_entries: + if entry.tag == ELF.DynamicEntry.TAG.NULL: + continue + + if entry.tag in [ + ELF.DynamicEntry.TAG.SONAME, + ELF.DynamicEntry.TAG.NEEDED, + ELF.DynamicEntry.TAG.RUNPATH, + ELF.DynamicEntry.TAG.RPATH, + ]: + print( + f_value.format(str(entry.tag).split(".")[-1], entry.value, entry.name) + ) + elif ( + type(entry) is ELF.DynamicEntryArray + ): # [ELF.DynamicEntry.TAG.INIT_ARRAY,ELF.DynamicEntry.TAG.FINI_ARRAY]: + print( + f_value.format( + str(entry.tag).split(".")[-1], + entry.value, + ", ".join(map(hex, entry.array)), + ) + ) + elif ( + entry.tag == ELF.DynamicEntry.TAG.FLAGS + or entry.tag == ELF.DynamicEntry.TAG.FLAGS_1 + ): + flags_str = " - ".join( + [str(ELF.DynamicEntryFlags.FLAG(s)).split(".")[-1] for s in entry.flags] + ) + print(f_value.format(str(entry.tag).split(".")[-1], entry.value, flags_str)) + else: + print(f_value.format(str(entry.tag).split(".")[-1], entry.value, "")) + + print() + + +@exceptions_handler(Exception) +def print_symbols(symbols, no_trunc): + can_demangle = len(symbols) > 0 and len(symbols[0].demangled_name) > 0 + if can_demangle: + maxsize = max([len(symbol.demangled_name) for symbol in symbols]) + else: + maxsize = max([len(symbol.name) for symbol in symbols]) + + SIZE = 70 + maxsize = ( + min(maxsize, terminal_columns - SIZE) + if terminal_columns > SIZE + else terminal_columns + ) + + f_title = "|{:<" + str(maxsize) + "} | {:<7}| {:<8}| {:<10}| {:<8}| {:<4}| {:<14}|" + f_value = "|{:<" + str(maxsize) + "} | {:<7}| {:<8x}| {:<10}| {:<8}| {:<4}| {:<14}|" + + print( + f_title.format( + "Name", "Type", "Value", "Visibility", "Binding", "I/E", "Version" + ) + ) + + for symbol in symbols: + symbol_version = symbol.symbol_version if symbol.has_version else "" + + import_export = "" + if symbol.imported: + import_export = "I" + + if symbol.exported: + import_export = "E" + + symbol_name = symbol.demangled_name + if len(symbol_name) == 0: + symbol_name = symbol.name + + wrapped = textwrap.wrap(symbol_name, maxsize) + + if len(wrapped) > 1 and not no_trunc: + symbol_name = wrapped[0][:-3] + "..." + + print( + f_value.format( + symbol_name, + str(symbol.type).split(".")[-1], + symbol.value, + str(symbol.visibility).split(".")[-1], + str(symbol.binding).split(".")[-1], + import_export, + str(symbol_version), + ) + ) + + +@exceptions_handler(Exception) +def print_dynamic_symbols(binary, args): + print("== Dynamic symbols ==\n") + print_symbols(binary.dynamic_symbols, args.no_trunc) + + +@exceptions_handler(Exception) +def print_symtab_symbols(binary, args): + print("== Symtab symbols ==\n") + print_symbols(binary.symtab_symbols, args.no_trunc) + + +@exceptions_handler(Exception) +def print_relocations(binary, relocations): + f_title = "|{:<10} | {:<10}| {:<8}| {:<8}| {:<8}| {:<15}| {:<30} |" + f_value = "|0x{:<8x} | {:<10}| {:<8d}| {:<8d}| {:<8x}| {:<15}| {:<30} |" + + print( + f_title.format("Address", "Type", "Info", "Size", "Addend", "Purpose", "Symbol") + ) + + for relocation in relocations: + type = str(relocation.type) + if ( + binary.header.machine_type == ELF.ARCH.x86_64 + or binary.header.machine_type == ELF.ARCH.i386 + or binary.header.machine_type == ELF.ARCH.ARM + or binary.header.machine_type == ELF.ARCH.AARCH64 + ): + type = str(relocation.type) + + symbol_name = "" + if relocation.has_symbol: + symbol: lief.ELF.Symbol = relocation.symbol + if len(symbol.name) > 0: + symbol_name = symbol.name + elif symbol.type == lief.ELF.Symbol.TYPE.SECTION: + shndx = symbol.shndx + sections = binary.sections + if 0 < shndx < len(sections): + symbol_name = sections[shndx].name + " + " + hex(relocation.addend) + else: + symbol_name = f"
" + + print( + f_value.format( + relocation.address, + type.split(".")[-1], + relocation.info, + relocation.size, + relocation.addend, + str(relocation.purpose).split(".")[-1], + symbol_name, + ) + ) + + +@exceptions_handler(Exception) +def print_all_relocations(binary): + dynamicrelocations = binary.dynamic_relocations + pltgot_relocations = binary.pltgot_relocations + object_relocations = binary.object_relocations + + if len(dynamicrelocations) > 0: + print("== Dynamic Relocations ==\n") + print_relocations(binary, dynamicrelocations) + + if len(pltgot_relocations) > 0: + print("== PLT/GOT Relocations ==\n") + print_relocations(binary, pltgot_relocations) + + if len(object_relocations) > 0: + print("== Object Relocations ==\n") + print_relocations(binary, object_relocations) + + +@exceptions_handler(Exception) +def print_exported_symbols(binary, args): + symbols = binary.exported_symbols + + print("== Exported symbols ==\n") + if len(symbols) == 0: + print("No exports!") + return + print_symbols(symbols, args.no_trunc) + + +@exceptions_handler(Exception) +def print_imported_symbols(binary, args): + symbols = binary.imported_symbols + print("== Imported symbols ==\n") + + if len(symbols) == 0: + print("No imports!") + return + print_symbols(symbols, args.no_trunc) + + +@exceptions_handler(Exception) +def print_information(binary): + print("== Information ==\n") + format_str = "{:<30} {:<30}" + format_hex = "{:<30} 0x{:<28x}" + print(format_hex.format("Address base:", binary.imagebase)) + print(format_hex.format("Virtual size:", binary.virtual_size)) + print(format_str.format("PIE:", str(binary.is_pie))) + print(format_str.format("NX:", str(binary.has_nx))) + + +@exceptions_handler(Exception) +def print_gnu_hash(binary): + print("== GNU Hash ==\n") + + if not binary.use_gnu_hash: + return + + gnu_hash = binary.gnu_hash + + format_str = "{:<30} {}" + format_hex = "{:<30} 0x{:<28x}" + format_dec = "{:<30} {:<30d}" + + print(format_dec.format("Number of buckets:", gnu_hash.nb_buckets)) + print(format_dec.format("First symbol index:", gnu_hash.symbol_index)) + print(format_hex.format("Shift Count:", gnu_hash.shift2)) + print(format_str.format("Bloom filters:", gnu_hash.bloom_filters)) + print(format_str.format("Buckets:", gnu_hash.buckets)) + print(format_str.format("Hash values:", gnu_hash.hash_values)) + + +@exceptions_handler(Exception) +def print_sysv_hash(binary): + print("== SYSV Hash ==\n") + + if not binary.use_sysv_hash: + return + + sysv_hash = binary.sysv_hash + + format_str = "{:<30} {}" + format_dec = "{:<30} {:<30d}" + + print(format_dec.format("Number of buckets:", sysv_hash.nbucket)) + print(format_dec.format("Number of chains:", sysv_hash.nchain)) + print(format_str.format("Buckets:", sysv_hash.buckets)) + print(format_str.format("Chains:", sysv_hash.chains)) + + +@exceptions_handler(Exception) +def print_notes(binary): + print("== Notes ==\n") + + format_str = "{:<19} {}" + format_dec = "{:<19} {:<30d}" + + notes = binary.notes + for idx, note in enumerate(notes): + description = note.description + description_str = " ".join(f"{e:02x}" for e in description[:16]) + if len(description) > 16: + description_str += " ..." + + print(f"Note #{idx:d}") + + type_str = note.type_core if note.is_core else note.type + type_str = str(type_str).split(".")[-1] + + print(format_str.format("Name:", note.name)) + print(format_str.format("Type:", type_str)) + print(format_str.format("Description:", description_str)) + + note_details = note.details + + if isinstance(note_details, lief.ELF.AndroidIdent): + print(format_dec.format("SDK Version:", note_details.sdk_version)) + print(format_str.format("NDK Version:", note_details.ndk_version)) + print(format_str.format("NDK build number:", note_details.ndk_build_number)) + + if isinstance(note_details, lief.ELF.NoteAbi): + version = note_details.version + version_str = f"{version[0]:d}.{version[1]:d}.{version[2]:d}" + + print(format_str.format("ABI:", note_details.abi)) + print(format_str.format("Version:", version_str)) + + if note.type == ELF.Note.TYPE.GNU_GOLD_VERSION: + print(format_str.format("Version:", "".join(map(chr, note.description)))) + + if note.is_core: + print(note_details) + + print("\n") + + +@exceptions_handler(Exception) +def print_ctor(binary): + print("== Constructors ==\n") + + print(f"Functions: ({len(binary.ctor_functions):d})") + for idx, f in enumerate(binary.ctor_functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_strings(binary): + print("== Strings ==\n") + + strings = binary.strings + print(f"Strings: ({len(binary.strings):d})") + for s in strings: + print(f" {s}") + + +@exceptions_handler(Exception) +def print_functions(binary): + print("== Functions ==\n") + + functions = binary.functions + print(f"Functions: ({len(functions):d})") + for idx, f in enumerate(functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +def main(): + parser = argparse.ArgumentParser(add_help=False, prog=sys.argv[0]) + parser.add_argument("elf_file") + + parser.add_argument( + "-a", + "--all", + action="store_true", + dest="show_all", + help="Equivalent to: -h -l -S -s -r -d -V", + ) + + parser.add_argument( + "-d", + "--dynamic", + action="store_true", + dest="show_dynamic_tags", + help="Display the dynamic section", + ) + + parser.add_argument( + "-H", "--help", action="help", dest="help", help="Display this information" + ) + + parser.add_argument( + "-h", + "--file-header", + action="store_true", + dest="show_file_header", + help="Display the ELF file header", + ) + + parser.add_argument( + "-i", + "--imported", + action="store_true", + dest="show_imported_symbols", + help="Display imported symbols", + ) + + parser.add_argument( + "-l", + "--program-headers", + "--segments", + action="store_true", + dest="show_program_header", + help="Display the program headers", + ) + + parser.add_argument( + "-S", + "--section-headers", + "--sections", + action="store_true", + dest="show_section_header", + help="Display the sections' headers", + ) + + parser.add_argument( + "-e", + "--headers", + action="store_true", + dest="show_all_headers", + help="Equivalent to: -h -l -S", + ) + + parser.add_argument( + "-s", + "--symbols", + "--syms", + action="store_true", + dest="show_symbols", + help="Display the symbol table", + ) + + parser.add_argument( + "--dynamic-symbols", + "--dsyms", + action="store_true", + dest="show_dynamic_symbols", + help="Display the dynamic symbols", + ) + + parser.add_argument( + "--symtab-symbols", + "--ssyms", + action="store_true", + dest="show_symtab_symbols", + help="Display the symtab symbols", + ) + + parser.add_argument( + "-r", + "--relocs", + action="store_true", + dest="show_relocs", + help="Display the relocations (if present)", + ) + + parser.add_argument( + "-V", + "--version-info", + action="store_true", + dest="show_version_info", + help="Display the version sections (if present)", + ) + + parser.add_argument( + "-x", + "--exported", + action="store_true", + dest="show_exported_symbols", + help="Display exported symbols", + ) + + parser.add_argument( + "--gnu-hash", action="store_true", dest="show_gnu_hash", help="Display GNU Hash" + ) + + parser.add_argument( + "--sysv-hash", + action="store_true", + dest="show_sysv_hash", + help="Display SYSV Hash", + ) + + parser.add_argument( + "-n", "--notes", action="store_true", dest="show_notes", help="Display Notes" + ) + + parser.add_argument( + "--no-trunc", + action="store_true", + dest="no_trunc", + default=False, + help="Do not trunc symbol names ...", + ) + + parser.add_argument( + "--ctor", action="store_true", dest="show_ctor", help="Constructor functions" + ) + + parser.add_argument( + "--strings", + action="store_true", + dest="show_strings", + help="Strings present in the current ELF", + ) + + parser.add_argument( + "--functions", + action="store_true", + dest="show_functions", + help="List all function addresses found", + ) + + # Logging setup + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + + lief.logging.set_level(args.main_verbosity) + binary = ELF.parse(args.elf_file) + if binary is None: + print(f"Error: failed to parse '{args.elf_file}' as ELF", file=sys.stderr) + return 1 + + print_information(binary) + if args.show_all: + do_file_header = do_section_header = do_program_header = True + + if args.show_all_headers: + do_file_header = do_section_header = do_program_header = True + else: + do_file_header = args.show_file_header + do_section_header = args.show_section_header + do_program_header = args.show_program_header + + if do_file_header or args.show_all: + print_header(binary) + + if do_section_header or args.show_all: + print_sections(binary) + + if do_program_header or args.show_all: + print_segments(binary) + + if args.show_dynamic_tags or args.show_all: + print_dynamic_entries(binary) + + if (args.show_symbols or args.show_all or args.show_dynamic_symbols) and len( + binary.dynamic_symbols + ) > 0: + print_dynamic_symbols(binary, args) + + if (args.show_symbols or args.show_all or args.show_symtab_symbols) and len( + binary.symtab_symbols + ) > 0: + print_symtab_symbols(binary, args) + + if args.show_relocs or args.show_all: + print_all_relocations(binary) + + if args.show_imported_symbols or args.show_all: + print_imported_symbols(binary, args) + + if args.show_exported_symbols or args.show_all: + print_exported_symbols(binary, args) + + if (args.show_gnu_hash or args.show_all) and binary.use_gnu_hash: + print_gnu_hash(binary) + + if (args.show_sysv_hash or args.show_all) and binary.use_sysv_hash: + print_sysv_hash(binary) + + if args.show_notes or args.show_all: + print_notes(binary) + + if args.show_ctor or args.show_all: + print_ctor(binary) + + if args.show_strings or args.show_all: + print_strings(binary) + + if args.show_functions: + print_functions(binary) + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_remove_section_table.py b/vendor/lief/api/python/examples/elf_remove_section_table.py new file mode 100755 index 0000000..90c5d19 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_remove_section_table.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python +"""Strip the section table from an ELF binary. + +Zeros out the ``e_shoff`` and ``e_shnum`` fields of the ELF header so +that tools relying on the section table (notably ``gdb``, ``readelf +-S``) lose visibility into the binary while the program headers +remain intact and the file still runs. + +Example: + + $ python elf_remove_section_table.py /bin/ls ls_nosec + $ readelf -S ls_nosec + There are no sections in this file. + $ ./ls_nosec # still runs +""" + +import argparse +import sys + +import lief + + +def remove_section_table(filename: str, output: str) -> int: + binary = lief.ELF.parse(filename) + if binary is None: + print(f"Error: failed to parse '{filename}' as ELF", file=sys.stderr) + return 1 + + header = binary.header + header.section_header_offset = 0 + header.numberof_sections = 0 + binary.write(output) + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("input", metavar="", help="Input ELF binary") + parser.add_argument("output", metavar="", help="Path to the rewritten binary") + args = parser.parse_args() + return remove_section_table(args.input, args.output) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_symbol_obfuscation.py b/vendor/lief/api/python/examples/elf_symbol_obfuscation.py new file mode 100755 index 0000000..c85fb37 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_symbol_obfuscation.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python +"""Obfuscate ``.symtab`` entries by renaming them to random strings. + +Replaces every static (``.symtab``) symbol name with a random +lowercase string of the same length. Useful to hinder naive symbolic +analysis while preserving binary layout. + +Example: + + $ readelf -s ./hello_c | head -3 + 29: 0400420 0 FUNC LOCAL DEFAULT 12 deregister_tm_clones + $ python elf_symbol_obfuscation.py ./hello_c ./hello_c.obf + $ readelf -s ./hello_c.obf | head -3 + 29: 0400420 0 FUNC LOCAL DEFAULT 12 wsadqwrubbmdugrxzwiv +""" + +import argparse +import random +import string +import sys + +import lief + + +def randomword(length: int) -> str: + return "".join(random.choice(string.ascii_lowercase) for _ in range(length)) + + +def randomize(binary: lief.ELF.Binary, output: str) -> int: + symbols = binary.symtab_symbols + if len(symbols) == 0: + print("No symbols", file=sys.stderr) + return 1 + for symbol in symbols: + symbol.name = randomword(len(symbol.name)) + binary.write(output) + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("input", metavar="", help="Input ELF binary") + parser.add_argument("output", metavar="", help="Output obfuscated binary") + args = parser.parse_args() + + binary = lief.ELF.parse(args.input) + if binary is None: + print(f"Error: failed to parse '{args.input}' as ELF", file=sys.stderr) + return 1 + + return randomize(binary, args.output) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/elf_unstrip.py b/vendor/lief/api/python/examples/elf_unstrip.py new file mode 100755 index 0000000..c20ea16 --- /dev/null +++ b/vendor/lief/api/python/examples/elf_unstrip.py @@ -0,0 +1,85 @@ +#!/usr/bin/env python +"""Inject a ``.symtab`` entry into a stripped ELF binary. + +Adds a fresh ``SYMTAB``/``STRTAB`` section pair and records a single +``FUNC`` symbol (by default ``main`` at ``0x402A00``) so that +debuggers such as ``gdb`` can resolve a symbolic breakpoint on a +binary whose static symbol table was removed. + +Example: + + $ python elf_unstrip.py ./stripped ./unstripped + $ gdb ./unstripped + (gdb) break main + Breakpoint 1 at 0x402a00 +""" + +import argparse +import sys + +from lief import ELF + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("input", metavar="", help="Input (stripped) ELF binary") + parser.add_argument("output", metavar="", help="Output ELF binary") + parser.add_argument( + "--address", + type=lambda e: int(e, 0), + default=0x402A00, + help="Address of the added symbol (default: 0x402A00)", + ) + parser.add_argument( + "--name", default="main", help="Name of the added symbol (default: main)" + ) + args = parser.parse_args() + + binary = ELF.parse(args.input) + if binary is None: + print(f"Error: failed to parse '{args.input}' as ELF", file=sys.stderr) + return 1 + + symtab_section = ELF.Section() + symtab_section.name = "" + symtab_section.type = ELF.Section.TYPE.SYMTAB + symtab_section.entry_size = 0x18 + symtab_section.alignment = 8 + symtab_section.link = len(binary.sections) + 1 + symtab_section.content = [0] * 100 + + symstr_section = ELF.Section() + symstr_section.name = "" + symstr_section.type = ELF.Section.TYPE.STRTAB + symstr_section.entry_size = 1 + symstr_section.alignment = 1 + symstr_section.content = [0] * 100 + + binary.add(symtab_section, loaded=False) + binary.add(symstr_section, loaded=False) + + null_symbol = ELF.Symbol() + null_symbol.name = "" + null_symbol.type = ELF.Symbol.TYPE.NOTYPE + null_symbol.value = 0 + null_symbol.binding = ELF.Symbol.BINDING.LOCAL + null_symbol.size = 0 + null_symbol.shndx = 0 + binary.add_symtab_symbol(null_symbol) + + symbol = ELF.Symbol() + symbol.name = args.name + symbol.type = ELF.Symbol.TYPE.FUNC + symbol.value = args.address + symbol.binding = ELF.Symbol.BINDING.LOCAL + symbol.shndx = 14 + symbol = binary.add_symtab_symbol(symbol) + + print(symbol) + + binary.write(args.output) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/json_dump.py b/vendor/lief/api/python/examples/json_dump.py new file mode 100755 index 0000000..3e6faf1 --- /dev/null +++ b/vendor/lief/api/python/examples/json_dump.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python +"""Format-agnostic JSON dump. + +Dispatches to ``lief.parse`` and pretty-prints the full JSON +representation of the loaded binary (ELF, PE, Mach-O, COFF, OAT). Use +one of the format-specific ``*_json.py`` scripts when the target type +is known in advance. + +Example: + + $ python json_dump.py /bin/ls +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Path to a binary supported by LIEF") + args = parser.parse_args() + + binary = lief.parse(args.file) + if binary is None: + print(f"Error: failed to parse '{args.file}'", file=sys.stderr) + return 1 + if isinstance(binary, lief.COFF.Binary): + print("COFF objects are not supported by lief.to_json", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(binary)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/macho_parser_tweak.py b/vendor/lief/api/python/examples/macho_parser_tweak.py new file mode 100755 index 0000000..34b65af --- /dev/null +++ b/vendor/lief/api/python/examples/macho_parser_tweak.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python +"""Benchmark Mach-O parsing with and without dyld info. + +Illustrates how to tune ``lief.MachO.ParserConfig`` to skip the +(expensive) dyld bindings/exports/rebases parsing, then to re-parse +with ``full_dyldinfo`` enabled, printing the elapsed time for both +passes. + +Example: + + $ python macho_parser_tweak.py /usr/bin/ls +""" + +import argparse +import sys +import time + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Path to a Mach-O binary") + args = parser.parse_args() + + # Skip the dyld info parsing. + config = lief.MachO.ParserConfig() + config.parse_dyld_bindings = False + config.parse_dyld_exports = False + config.parse_dyld_rebases = False + + t1 = time.time() + lief.MachO.parse(args.file, config) + t2 = time.time() + print(f"Without dyld info: {t2 - t1:.3f}s") + + # Parse the dyld info. + config.full_dyldinfo(True) + t1 = time.time() + lief.MachO.parse(args.file, config) + t2 = time.time() + print(f"With dyld info: {t2 - t1:.3f}s") + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/macho_reader.py b/vendor/lief/api/python/examples/macho_reader.py new file mode 100755 index 0000000..2c646b3 --- /dev/null +++ b/vendor/lief/api/python/examples/macho_reader.py @@ -0,0 +1,1187 @@ +#!/usr/bin/env python +"""Pretty-print the structure of a Mach-O binary. + +Equivalent to ``otool``/``llvm-otool`` with a selection of the most +useful flags. The file is parsed with ``lief.MachO.parse`` and each +requested section (header, load commands, segments, symbols, imports, +...) is rendered as a formatted table. + +Example: + + $ python macho_reader.py -a /usr/bin/ls +""" + +import argparse +import shutil +import sys +import traceback + +import lief +from lief import MachO + +_term_size = shutil.get_terminal_size((100, 100)) +terminal_columns = _term_size.columns +terminal_rows = _term_size.lines +EXIT_STATUS = 0 + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + global EXIT_STATUS + print(f"{self.func.__name__} raised: {e}") + EXIT_STATUS = 1 + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_information(binary): + print("== Information ==") + format_str = "{:<30} {:<30}" + format_hex = "{:<30} 0x{:<28x}" + header: lief.MachO.Header = binary.header + cpu = str(header.cpu_type).split(".")[-1] + + print(format_hex.format("Address base:", binary.imagebase)) + print(format_str.format("PIE:", str(binary.is_pie))) + print(format_str.format("NX:", str(binary.has_nx))) + print(format_str.format("Arch:", cpu)) + print() + + +@exceptions_handler(Exception) +def print_header(binary): + format_str = "{:<33} {:<30}" + format_hex = "{:<33} 0x{:<28x}" + format_dec = "{:<33} {:<30d}" + + print("== Header ==") + header = binary.header + flags_str = " - ".join([str(s).split(".")[-1] for s in header.flags_list]) + + print(format_str.format("Magic:", str(header.magic).split(".")[-1])) + print(format_str.format("CPU Type:", str(header.cpu_type).split(".")[-1])) + print(format_hex.format("CPU sub-type:", header.cpu_subtype)) + print(format_str.format("File Type:", str(header.file_type).split(".")[-1])) + print(format_str.format("Flags:", flags_str)) + print(format_dec.format("Number of commands:", header.nb_cmds)) + print(format_hex.format("Size of commands:", header.sizeof_cmds)) + print(format_hex.format("Reserved:", header.reserved)) + + +@exceptions_handler(Exception) +def print_commands(binary): + + f_title = "|{:<20}|{:<11}|{:<11}|" + f_value = "|{:<20}|0x{:08x} |0x{:08x} |" + print("== Commands ==") + print(f_title.format("Command", "Offset", "Size")) + for command in binary.commands: + print( + f_value.format( + str(command.command).split(".")[-1], + command.command_offset, + command.size, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_libraries(binary): + + f_title = "|{:<30}|{:<10}|{:<16}|{:<22}|" + f_value = "|{:<30}|{:<10d}|{:<16}|{:<22}|" + print("== Libraries ==") + print( + f_title.format("Name", "Timestamp", "Current Version", "Compatibility Version") + ) + for library in binary.libraries: + current_version_str = "{:d}.{:d}.{:d}".format(*library.current_version) + compatibility_version_str = "{:d}.{:d}.{:d}".format( + *library.compatibility_version + ) + print( + f_value.format( + library.name, + library.timestamp, + current_version_str, + compatibility_version_str, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_segments(binary): + + f_title = "|{:<20}|{:<16}|{:<16}|{:<16}|{:16}|{:16}|{:16}|{}" + f_value = ( + "|{:<20}|0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |{}" + ) + print("== Segments ==") + print( + f_title.format( + "Name", + "Virtual Address", + "Virtual Size", + "Offset", + "Size", + "Max Protection", + "Init Protection", + "Sections", + ) + ) + for segment in binary.segments: + sections = ", ".join(s.name for s in segment.sections) + print( + f_value.format( + segment.name, + segment.virtual_address, + segment.virtual_size, + segment.file_offset, + segment.file_size, + segment.max_protection, + segment.init_protection, + sections, + ) + ) + + print() + + +@exceptions_handler(Exception) +def print_sections(binary): + + f_title = "|{:<20}|{:<16}|{:<16}|{:<16}|{:16}|{:22}|{:19}|{:25}|{:25}|" + f_value = "|{:<20}|0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<19x} |0x{:<16x} |{:<25}|{:<25}" + + print("== Sections ==") + + print( + f_title.format( + "Name", + "Virtual Address", + "Offset", + "Size", + "Alignement", + "Number of Relocations", + "Relocation offset", + "Type", + "Flags", + ) + ) + + for section in binary.sections: + flags_str = " - ".join([str(s).split(".")[-1] for s in section.flags_list]) + print( + f_value.format( + section.name, + section.virtual_address, + section.offset, + section.size, + section.alignment, + section.numberof_relocations, + section.relocation_offset, + str(section.type).split(".")[-1], + flags_str, + ) + ) + if len(section.relocations) > 0: + for idx, reloc in enumerate(section.relocations): + name = reloc.symbol.name if reloc.has_symbol else "" + secname = " - " + reloc.section.name if reloc.has_section else "" + type = str(reloc.type) + if reloc.architecture == MachO.Header.CPU_TYPE.X86: + type = str(MachO.X86_RELOCATION(reloc.type)) + + if reloc.architecture == MachO.Header.CPU_TYPE.x86_64: + type = str(MachO.X86_64_RELOCATION(reloc.type)) + + if reloc.architecture == MachO.Header.CPU_TYPE.ARM: + type = str(MachO.ARM_RELOCATION(reloc.type)) + + if reloc.architecture == MachO.Header.CPU_TYPE.ARM64: + type = str(MachO.ARM64_RELOCATION(reloc.type)) + + if reloc.architecture == MachO.Header.CPU_TYPE.POWERPC: + type = str(MachO.PPC_RELOCATION(reloc.type)) + + print( + " [Reloc #{:d} {section}] {name:<10} 0x{address:<6x} {type:<20} {size:d} {pcrel} {scat}".format( + idx, + section=secname, + name=name, + address=reloc.address, + type=type.split(".")[-1], + size=reloc.size, + pcrel=str(reloc.pc_relative), + scat=str(reloc.is_scattered), + ) + ) + print() + + print() + + +@exceptions_handler(Exception) +def print_symbols(binary): + symbols = binary.symbols + if len(symbols) == 0: + return + try: + maxsize = max([len(symbol.demangled_name) for symbol in symbols]) + except Exception: # noqa + maxsize = max([len(symbol.name) for symbol in symbols]) + maxsize = ( + min(maxsize, terminal_columns - 90) + if terminal_columns > 90 + else terminal_columns + ) + + f_title = "|{:<" + str(maxsize) + "} |{:<6}|{:<19}|{:<16}|{:16}| {:s}" + f_value = ( + "|{:<" + str(maxsize) + "} |0x{:<3x} |0x{:<16x} |0x{:<13x} |0x{:<13x} | {:s}" + ) + print("== Symbols ==") + print( + f_title.format( + "Name", "Type", "Number of Sections", "Description", "Value", "Library" + ) + ) + for symbol in binary.symbols: + libname = "" + if symbol.has_binding_info and symbol.binding_info.has_library: + libname = symbol.binding_info.library.name + + if symbol.has_export_info: + symbol_value = symbol.export_info.address + elif symbol.has_binding_info: + symbol_value = symbol.binding_info.address + else: + symbol_value = symbol.value + + try: + symbol_name = symbol.demangled_name + except Exception: # noqa + symbol_name = symbol.name + print( + f_value.format( + symbol_name, + symbol.type, + symbol.numberof_sections, + symbol.description, + symbol_value, + libname, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_symbol_command(binary): + print("== Symbol Command ==") + + scmd = binary.symbol_command + + format_hex = "{:<17} 0x{:<28x}" + format_dec = "{:<17} {:<30d}" + + print(format_hex.format("Symbol offset", scmd.symbol_offset)) + print(format_dec.format("Number of symbols", scmd.numberof_symbols)) + + print(format_hex.format("String offset", scmd.strings_offset)) + print(format_hex.format("String size", scmd.strings_size)) + + print() + + +@exceptions_handler(Exception) +def print_dynamic_symbol_command(binary): + print("== Dynamic Symbol Command ==") + + dyscmd = binary.dynamic_symbol_command + + format_hex = "{:<36} 0x{:<28x}" + format_dec = "{:<36} {:<30d}" + + print(format_dec.format("First local symbol index", dyscmd.idx_local_symbol)) + print(format_dec.format("Number of local symbols", dyscmd.nb_local_symbols)) + + print(format_dec.format("External symbol index", dyscmd.idx_external_define_symbol)) + print( + format_dec.format( + "Number of external symbols", dyscmd.nb_external_define_symbols + ) + ) + + print(format_dec.format("Undefined symbol index", dyscmd.idx_undefined_symbol)) + print(format_dec.format("Number of undefined symbols", dyscmd.nb_undefined_symbols)) + + print(format_dec.format("Table of content offset", dyscmd.toc_offset)) + print(format_dec.format("Number of entries in TOC", dyscmd.nb_toc)) + + print(format_hex.format("Module table offset", dyscmd.module_table_offset)) + print( + format_dec.format("Number of entries in module table", dyscmd.nb_module_table) + ) + + print( + format_hex.format( + "External reference table offset", dyscmd.external_reference_symbol_offset + ) + ) + print( + format_dec.format( + "Number of external reference", dyscmd.nb_external_reference_symbols + ) + ) + + print(format_hex.format("Indirect symbols offset", dyscmd.indirect_symbol_offset)) + print(format_dec.format("Number of indirect symbols", dyscmd.nb_indirect_symbols)) + + print( + format_hex.format( + "External relocation offset", dyscmd.external_relocation_offset + ) + ) + print( + format_dec.format( + "Number of external relocations", dyscmd.nb_external_relocations + ) + ) + + print(format_hex.format("Local relocation offset", dyscmd.local_relocation_offset)) + print(format_dec.format("Number of local relocations", dyscmd.nb_local_relocations)) + + print() + + +@exceptions_handler(Exception) +def print_uuid(binary): + print("== UUID ==") + cmd = binary.uuid + uuid_str = " ".join(f"{e:02x}" for e in cmd.uuid) + print(f"UUID: {uuid_str}") + + print() + + +@exceptions_handler(Exception) +def print_main_command(binary): + + format_hex = "{:<13} 0x{:<28x}" + + print("== Main Command ==") + cmd = binary.main_command + + print(format_hex.format("Entry point:", cmd.entrypoint)) + print(format_hex.format("Stack size:", cmd.stack_size)) + + print() + + +@exceptions_handler(Exception) +def print_thread_command(binary): + + format_hex = "{:<13} 0x{:<28x}" + + print("== Thread Command ==") + cmd = binary.thread_command + + print(format_hex.format("Flavor:", cmd.flavor)) + print(format_hex.format("Count:", cmd.count)) + print(format_hex.format("PC:", cmd.pc)) + + print() + + +@exceptions_handler(Exception) +def print_rpath_command(binary): + + print("== Rpath Command ==") + cmd = binary.rpath + print(f"Path: {cmd.path}") + + print() + + +@exceptions_handler(Exception) +def print_dylinker(binary): + print("== Dylinker ==") + print(f"Path: {binary.dylinker.name}") + + print() + + +@exceptions_handler(Exception) +def print_function_starts(binary): + format_hex = "{:<13} 0x{:<28x}" + + print("== Function Starts ==") + + fstarts = binary.function_starts + + print(format_hex.format("Offset:", fstarts.data_offset)) + print(format_hex.format("Size:", fstarts.data_size)) + print(f"Functions: ({len(fstarts.functions):d})") + for idx, address in enumerate(fstarts.functions): + print(f" [{idx:d}] __TEXT + 0x{address:x}") + + print() + + +@exceptions_handler(Exception) +def print_data_in_code(binary): + format_hex = "{:<13} 0x{:<28x}" + + print("== Data In Code ==") + + datacode = binary.data_in_code + + print(format_hex.format("Offset:", datacode.data_offset)) + print(format_hex.format("Size:", datacode.data_size)) + print() + for entry in datacode.entries: + type_str = str(entry.type).split(".")[-1] + print(f"- {type_str:<14}: 0x{entry.offset:x} ({entry.length:d} bytes)") + print() + + +@exceptions_handler(Exception) +def print_segment_split_info(binary): + format_hex = "{:<13} 0x{:<28x}" + + print("== Segment Split Info ==") + + sinfo = binary.segment_split_info + + print(format_hex.format("Offset:", sinfo.data_offset)) + print(format_hex.format("Size:", sinfo.data_size)) + + print() + + +@exceptions_handler(Exception) +def print_sub_framework(binary): + format_str = "{:<13} {:<30}" + + print("== Sub Framework ==") + + sinfo = binary.sub_framework + print(format_str.format("Umbrella:", sinfo.umbrella)) + + print() + + +@exceptions_handler(Exception) +def print_dyld_environment(binary): + format_str = "{:<13} {:<30}" + + print("== Dyld Environment ==") + + env = binary.dyld_environment + print(format_str.format("Value:", env.value)) + + print() + + +@exceptions_handler(Exception) +def print_dyld_info(binary): + print("== Dyld Info ==") + f_title = "|{:<12}|{:<11}|{:<11}|" + f_value = "|{:<12}|0x{:<8x} |0x{:<8x} |" + + dyld_info = binary.dyld_info + + print(f_title.format("Type", "Offset", "Size")) + print(f_value.format("Rebase", dyld_info.rebase[0], dyld_info.rebase[1])) + print(f_value.format("Bind", dyld_info.bind[0], dyld_info.bind[1])) + print(f_value.format("Weak Bind", dyld_info.weak_bind[0], dyld_info.weak_bind[1])) + print(f_value.format("Lazy Bind", dyld_info.lazy_bind[0], dyld_info.lazy_bind[1])) + print(f_value.format("Export", dyld_info.export_info[0], dyld_info.export_info[1])) + + print() + + print("Bindings") + print("--------") + for _idx, binfo in enumerate(dyld_info.bindings): + print("{:10}: {}".format("Class", str(binfo.binding_class).split(".")[-1])) + print("{:10}: {}".format("Type", str(binfo.binding_type).split(".")[-1])) + print("{:10}: {:x}".format("Address", binfo.address)) + + if binfo.has_symbol: + print("{:10}: {}".format("Symbol", binfo.symbol.name)) + + if binfo.has_segment: + print("{:10}: {}".format("Segment", binfo.segment.name)) + + if binfo.has_library: + print("{:10}: {}".format("Library", binfo.library.name)) + + if binfo.binding_class == lief.MachO.BINDING_CLASS.LAZY: + print("{:10}: {}".format("Offset", binfo.original_offset)) + + print() + + print() + + print("Exports") + print("-------") + for _idx, einfo in enumerate(dyld_info.exports): + output = f"0x{einfo.address:08x} - {einfo.symbol.name}" + if einfo.alias: + output += f" - {einfo.alias.name}" + if einfo.alias_library: + output += f" from {einfo.alias_library.name}" + print(output) + + # print("{:10}: {:<10x}".format("Address", einfo.address)) + # print("{:10}: {:<10x}".format("Flags", einfo.flags)) + + # if binfo.has_symbol: + # print("{:10}: {}".format("Symbol", einfo.symbol.name)) + + print() + + print() + + +@exceptions_handler(Exception) +def print_rebase_opcodes(binary): + print("== Rebase opcodes ==") + + print(binary.dyld_info.show_rebases_opcodes) + + print() + + +@exceptions_handler(Exception) +def print_bind_opcodes(binary): + print("== Bind opcodes ==") + + print(binary.dyld_info.show_bind_opcodes) + + print() + + +@exceptions_handler(Exception) +def print_weak_bind_opcodes(binary): + print("== Weak bind opcodes ==") + + print(binary.dyld_info.show_weak_bind_opcodes) + + print() + + +@exceptions_handler(Exception) +def print_lazy_bind_opcodes(binary): + print("== Lazy bind opcodes ==") + + print(binary.dyld_info.show_lazy_bind_opcodes) + + print() + + +@exceptions_handler(Exception) +def print_export_trie(binary): + print("== Export trie ==") + if binary.has_dyld_info: + print(binary.dyld_info.show_export_trie) + if binary.has_dyld_exports_trie: + trie: lief.MachO.DyldExportsTrie = binary.dyld_exports_trie + print(f"Linkedit position: 0x{trie.data_offset} (0x{trie.data_size:x} bytes)") + print(trie.show_export_trie()) + + print() + + +@exceptions_handler(Exception) +def print_source_version(binary): + print("== Source Version ==") + + version = binary.source_version.version + + print("Version: {:d}.{:d}.{:d}.{:d}.{:d}".format(*version)) + + print() + + +@exceptions_handler(Exception) +def print_version_min(binary): + print("== Version Min ==") + + version = binary.version_min.version + sdk = binary.version_min.sdk + + print("Version: {:d}.{:d}.{:d}".format(*version)) + print("SDK: {:d}.{:d}.{:d}".format(*sdk)) + + print() + + +@exceptions_handler(Exception) +def print_relocations(binary): + print("== Relocations ==") + + f_value = "|0x{address:<10x} | {size:<4d} | {type:<15} | {pcrel:<11} | {secseg:<23} | {symbol}" + f_title = "|{address:<12} | {size:<4} | {type:<15} | {pcrel:<11} | {secseg:<23} | {symbol}" + + print( + f_title.format( + address="Address", + size="Size", + type="Type", + pcrel="PC Relative", + secseg="Section/Section", + symbol="Symbol", + ) + ) + + for reloc in binary.relocations: + rtype = reloc.type + if isinstance(rtype, int): + type_str = str(rtype) + else: + type_str = str(rtype).split(".")[-1] + + symbol_name = "" + if reloc.has_symbol: + symbol_name = reloc.symbol.name + + secseg_name = "" + if reloc.has_segment and reloc.has_section: + secseg_name = f"{reloc.segment.name}.{reloc.section.name}" + else: + if reloc.has_segment: + secseg_name = reloc.segment.name + + if reloc.has_section: + secseg_name = reloc.section.name + + print( + f_value.format( + address=reloc.address, + size=reloc.size, + type=type_str, + pcrel=str(reloc.pc_relative), + secseg=secseg_name, + symbol=symbol_name, + ) + ) + + print() + + +@exceptions_handler(Exception) +def print_encryption_info(binary): + + format_hex = "{:<13} 0x{:<28x}" + format_dec = "{:<13} {:<30d}" + + print("== Encryption Info ==") + cmd = binary.encryption_info + + print(format_hex.format("Offset:", cmd.crypt_offset)) + print(format_hex.format("Size:", cmd.crypt_size)) + print(format_dec.format("ID:", cmd.crypt_id)) + + print() + + +@exceptions_handler(Exception) +def print_ctor(binary): + print("== Constructors ==\n") + + print(f"Functions: ({len(binary.ctor_functions):d})") + for idx, f in enumerate(binary.ctor_functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_unwind_functions(binary): + print("== Unwind functions ==\n") + + print(f"Functions: ({len(binary.unwind_functions):d})") + for idx, f in enumerate(binary.unwind_functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_functions(binary): + print("== Functions ==\n") + + print(f"Functions: ({len(binary.functions):d})") + for idx, f in enumerate(binary.functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_build_version(binary): + print("== Build Version ==\n") + + build_version = binary.build_version + + print("Platform: {}".format(str(build_version.platform).split(".")[-1])) + print("Min OS: {:d}.{:d}.{:d}".format(*build_version.minos)) + print("SDK: {:d}.{:d}.{:d}".format(*build_version.sdk)) + + tools = build_version.tools + if len(tools) > 0: + print(f"~~ Tools ({len(tools)}) ~~") + for tool in tools: + tool_str = str(tool.tool).split(".")[-1] + print(" {} - {}.{}.{}".format(tool_str, *tool.version)) + + +def print_chained_fixups(binary: lief.MachO.Binary): + fixups = binary.dyld_chained_fixups + if fixups is None: + return + print("== Dyld Chained Fixups ==") + print(fixups) + + +def main(): + parser = argparse.ArgumentParser(usage="%(prog)s [options] ") + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + + parser.add_argument( + "-c", + "--commands", + action="store_true", + dest="show_commands", + help="Display Commands", + ) + + parser.add_argument( + "-H", "--header", action="store_true", dest="show_header", help="Display header" + ) + + parser.add_argument( + "-L", + "--libraries", + action="store_true", + dest="show_libraries", + help="Display Imported Libraries", + ) + + parser.add_argument( + "-l", + "--segments", + action="store_true", + dest="show_segments", + help="Display Segments", + ) + + parser.add_argument( + "-r", + "--relocations", + action="store_true", + dest="show_relocs", + help="Display the relocations (if present)", + ) + + parser.add_argument( + "-s", + "--symbols", + action="store_true", + dest="show_symbols", + help="Display Symbols", + ) + + parser.add_argument( + "-S", + "--sections", + action="store_true", + dest="show_sections", + help="Display Sections", + ) + + parser.add_argument( + "--uuid", action="store_true", dest="show_uuid", help="Display the UUID command" + ) + + parser.add_argument( + "--main", action="store_true", dest="show_main", help="Display the Main command" + ) + + parser.add_argument( + "--dylinker", + action="store_true", + dest="show_dylinker", + help="Display the Dylinker command", + ) + + parser.add_argument( + "--dyldinfo", + action="store_true", + dest="show_dyldinfo", + help="Display the DyldInfo command", + ) + + parser.add_argument( + "--function-starts", + action="store_true", + dest="show_function_starts", + help="Display the FunctionStarts command", + ) + + parser.add_argument( + "--rebase-opcodes", + action="store_true", + dest="show_rebase_opcodes", + help='Display the "Rebase" opcodes', + ) + + parser.add_argument( + "--source-version", + action="store_true", + dest="show_source_version", + help="Display the 'Source Version' command", + ) + + parser.add_argument( + "--version-min", + action="store_true", + dest="show_version_min", + help="Display the 'Version Min' command", + ) + + parser.add_argument( + "--thread-command", + action="store_true", + dest="show_thread_command", + help="Display the 'Thread Command' command", + ) + + parser.add_argument( + "--rpath-command", + action="store_true", + dest="show_rpath_command", + help="Display the 'Rpath Command' command", + ) + + parser.add_argument( + "--symbol-command", + action="store_true", + dest="show_symbol_command", + help="Display the 'Symbol Command' command", + ) + + parser.add_argument( + "--dynamic-symbol-command", + action="store_true", + dest="show_dynamic_symbol_command", + help="Display the 'Symbol Command' command", + ) + + parser.add_argument( + "--data-in-code", + action="store_true", + dest="show_data_in_code", + help="Display the 'Data In Code' command", + ) + + parser.add_argument( + "--segment-split-info", + action="store_true", + dest="show_segment_split_info", + help="Display the 'Segment Split Info' command", + ) + + parser.add_argument( + "--sub-framework", + action="store_true", + dest="show_sub_framework", + help="Display the 'Sub Framework' command", + ) + + parser.add_argument( + "--dyld-environment", + action="store_true", + dest="show_dyld_env", + help="Display the 'Dyld Environment' command", + ) + + parser.add_argument( + "--encryption-info", + action="store_true", + dest="show_encrypt_info", + help="Display the 'Encryption Info' command", + ) + + parser.add_argument( + "--bind-opcodes", + action="store_true", + dest="show_bind_opcodes", + help='Display the "Bind" opcodes', + ) + + parser.add_argument( + "--weak-bind-opcodes", + action="store_true", + dest="show_weak_bind_opcodes", + help='Display the "Weak Bind" opcodes', + ) + + parser.add_argument( + "--lazy-bind-opcodes", + action="store_true", + dest="show_lazy_bind_opcodes", + help='Display the "Lazy Bind" opcodes', + ) + + parser.add_argument( + "--export-trie", + action="store_true", + dest="show_export_trie", + help="Display the export trie", + ) + + parser.add_argument( + "--opcodes", + action="store_true", + dest="show_opcodes", + help="Display the bind and rebase opcodes", + ) + + parser.add_argument( + "--ctor", action="store_true", dest="show_ctor", help="Constructor functions" + ) + + parser.add_argument( + "--unwind-functions", + action="store_true", + dest="show_ufunctions", + help="Functions from unwind info", + ) + + parser.add_argument( + "--functions", + action="store_true", + dest="show_functions", + help="All functions found in the binary", + ) + + parser.add_argument( + "--build-version", + action="store_true", + dest="show_build_version", + help="Show build version", + ) + + parser.add_argument( + "--chained-fixups", + action="store_true", + dest="show_chained_fixups", + help="Show Dyld Chained Fixups", + ) + + parser.add_argument( + "--check-layout", + action="store_true", + dest="check_layout", + help="Check the layout of the binary", + ) + + parser.add_argument("binary", metavar="", help="Target Mach-O File") + + # Logging setup + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + + lief.logging.set_level(args.main_verbosity) + + binaries = MachO.parse(args.binary) + if binaries is None: + print(f"Can't parse {args.binary}") + sys.exit(1) + + if len(binaries) > 1: + print(f"Fat Mach-O: {len(binaries):d} binaries") + + if args.check_layout: + isok, err = MachO.check_layout(binaries) + if not isok: + print(err) + + for binary in binaries: + print_information(binary) + + if args.show_header or args.show_all: + print_header(binary) + + if args.show_commands or args.show_all: + print_commands(binary) + + if args.show_libraries or args.show_all: + print_libraries(binary) + + if args.show_segments or args.show_all: + print_segments(binary) + + if args.show_sections or args.show_all: + print_sections(binary) + + if args.show_symbols or args.show_all: + print_symbols(binary) + + if (args.show_uuid or args.show_all) and binary.has_uuid: + print_uuid(binary) + + if (args.show_main or args.show_all) and binary.has_main_command: + print_main_command(binary) + + if (args.show_dylinker or args.show_all) and binary.has_dylinker: + print_dylinker(binary) + + if (args.show_dyldinfo or args.show_all) and binary.has_dyld_info: + print_dyld_info(binary) + + if (args.show_function_starts or args.show_all) and binary.has_function_starts: + print_function_starts(binary) + + if (args.show_source_version or args.show_all) and binary.has_source_version: + print_source_version(binary) + + if (args.show_version_min or args.show_all) and binary.has_version_min: + print_version_min(binary) + + if (args.show_relocs or args.show_all) and len(binary.relocations) > 0: + print_relocations(binary) + + if (args.show_thread_command or args.show_all) and binary.has_thread_command: + print_thread_command(binary) + + if (args.show_rpath_command or args.show_all) and binary.has_rpath: + print_rpath_command(binary) + + if (args.show_symbol_command or args.show_all) and binary.has_symbol_command: + print_symbol_command(binary) + + if ( + args.show_dynamic_symbol_command or args.show_all + ) and binary.has_dynamic_symbol_command: + print_dynamic_symbol_command(binary) + + if (args.show_data_in_code or args.show_all) and binary.has_data_in_code: + print_data_in_code(binary) + + if ( + args.show_segment_split_info or args.show_all + ) and binary.has_segment_split_info: + print_segment_split_info(binary) + + if (args.show_sub_framework or args.show_all) and binary.has_sub_framework: + print_sub_framework(binary) + + if (args.show_dyld_env or args.show_all) and binary.has_dyld_environment: + print_dyld_environment(binary) + + if (args.show_encrypt_info or args.show_all) and binary.has_encryption_info: + print_encryption_info(binary) + + if (args.show_rpath_command or args.show_all) and binary.has_rpath: + print_rpath_command(binary) + + if (args.show_rebase_opcodes or args.show_opcodes) and binary.has_dyld_info: + print_rebase_opcodes(binary) + + if (args.show_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: + print_bind_opcodes(binary) + + if (args.show_weak_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: + print_weak_bind_opcodes(binary) + + if (args.show_lazy_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: + print_lazy_bind_opcodes(binary) + + if args.show_export_trie or args.show_opcodes: + print_export_trie(binary) + + if args.show_ctor or args.show_all: + print_ctor(binary) + + if args.show_ufunctions or args.show_all: + print_unwind_functions(binary) + + if args.show_functions or args.show_all: + print_functions(binary) + + if (args.show_build_version or args.show_all) and binary.has_build_version: + print_build_version(binary) + + if args.show_chained_fixups or args.show_all: + print_chained_fixups(binary) + + +if __name__ == "__main__": + main() + sys.exit(EXIT_STATUS) diff --git a/vendor/lief/api/python/examples/nm.py b/vendor/lief/api/python/examples/nm.py new file mode 100755 index 0000000..de09476 --- /dev/null +++ b/vendor/lief/api/python/examples/nm.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python +"""Format-agnostic ``nm``-style symbol lister. + +Prints every symbol found in a binary. For PE files, it prints the +entries of the *symbol section*; for ELF files, both the static +(``.symtab``) and dynamic (``.dynsym``) symbols; for Mach-O the +global symbol table. + +Example: + + $ python nm.py /usr/bin/ls +""" + +import argparse +import sys + +import lief + + +def nm(filename: str) -> int: + binary = lief.parse(filename) + if binary is None: + print(f"Error: failed to parse '{filename}'", file=sys.stderr) + return 1 + + symbols = binary.symbols + if len(symbols) > 0: + for symbol in symbols: + print(symbol) + else: + print("No symbols found") + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to the binary to list") + args = parser.parse_args() + return nm(args.binary) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/oat_reader.py b/vendor/lief/api/python/examples/oat_reader.py new file mode 100755 index 0000000..b466416 --- /dev/null +++ b/vendor/lief/api/python/examples/oat_reader.py @@ -0,0 +1,211 @@ +#!/usr/bin/env python +"""Pretty-print the structure of an Android OAT file. + +Parses an ``.oat`` file with ``lief.OAT.parse`` and renders a summary +of the file (header, embedded DEX files, classes, methods) selected +by command-line flags. + +Example: + + $ python oat_reader.py -a boot.oat +""" + +import argparse +import shutil +import sys +import traceback + +import lief +from lief import OAT + +EXIT_STATUS = 0 +_term_size = shutil.get_terminal_size((100, 100)) +terminal_columns = _term_size.columns +terminal_rows = _term_size.lines + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + global EXIT_STATUS + print(f"{self.func.__name__} raised: {e}") + EXIT_STATUS = 1 + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_information(binary): + print("== Information ==") + + android_version = lief.OAT.android_version(binary.header.version) + code_name = lief.Android.code_name(android_version) + version = lief.Android.version_string(android_version) + + print(f"Version: {binary.header.version} - Android {version} {code_name}") + print(f"Number of dex files: {len(binary.oat_dex_files)}") + print(f"Number of classes: {len(binary.classes)}") + print(f"Number of methods: {len(binary.methods)}") + print() + + +@exceptions_handler(Exception) +def print_header(binary): + print("== Header ==") + print(binary.header) + + +@exceptions_handler(Exception) +def print_dex_files(binary): + print("== Dex files ==") + for oat_dex in binary.oat_dex_files: + print(oat_dex) + + +@exceptions_handler(Exception) +def print_classes(binary): + print("== Classes ==") + for cls in binary.classes: + print(cls) + + +@exceptions_handler(Exception) +def print_methods(binary): + print("== Methods ==") + for m in binary.methods: + print(m) + + +def main(): + parser = argparse.ArgumentParser(usage="%(prog)s [options] oat files") + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + + parser.add_argument( + "-H", "--header", action="store_true", dest="show_header", help="Display header" + ) + + parser.add_argument( + "-c", + "--classes", + action="store_true", + dest="show_classes", + help="Display classes", + ) + + parser.add_argument( + "-d", "--dex", action="store_true", dest="show_dex", help="Display Dex files" + ) + + parser.add_argument( + "-m", + "--methods", + action="store_true", + dest="show_methods", + help="Display Methods", + ) + + parser.add_argument( + "-x", + "--extract", + action="store_true", + dest="extract_dex", + help="Extract DEX files", + ) + + parser.add_argument("binary", metavar="", help="Target OAT File") + + # Logging setup + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + + lief.logging.set_level(args.main_verbosity) + + binary = OAT.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}' as OAT", file=sys.stderr) + return 1 + + print_information(binary) + + if args.show_header or args.show_all: + print_header(binary) + + if (args.show_dex or args.show_all) and len(binary.oat_dex_files) > 0: + print_dex_files(binary) + + if args.show_classes and len(binary.classes) > 0: + print_classes(binary) + + if args.show_methods and len(binary.methods) > 0: + print_methods(binary) + + return EXIT_STATUS + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/objc_dump.py b/vendor/lief/api/python/examples/objc_dump.py new file mode 100755 index 0000000..c3a35dd --- /dev/null +++ b/vendor/lief/api/python/examples/objc_dump.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python +"""Dump Objective-C metadata of a Mach-O binary. + +Parses the Objective-C runtime metadata stored in a Mach-O binary +and prints a header-like declaration of every class (and optionally +every protocol) found. + +Note: only available with the extended version of LIEF. + +Example: + + $ python objc_dump.py /System/Applications/Calculator.app/Contents/MacOS/Calculator +""" + +import argparse +import sys +from pathlib import Path + +import lief + + +def process(filepath: str, skip_protocols: bool = False, + output_path: str | None = None) -> int: + target = Path(filepath) + if not target.is_file(): + print(f"'{target}' is not a valid file", file=sys.stderr) + return 1 + + macho = lief.MachO.parse(target) + if macho is None: + print(f"Can't parse Mach-O file: {target}", file=sys.stderr) + return 1 + + metadata = macho.at(0).objc_metadata + if metadata is None: + print(f"Can't parse ObjC metadata in '{target}'", file=sys.stderr) + return 1 + + if skip_protocols: + output = "" + for cls in metadata.classes: + output += cls.to_decl() + else: + output = metadata.to_decl() + print(output) + + if output_path is not None: + out = Path(output_path) + if out.is_dir(): + out /= f"{target.name}_objc.h" + out.write_text(output) + print(f"Saved in {out}") + return 0 + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("-o", "--output", help="Output file or directory", default=None) + parser.add_argument("--skip-protocols", help="Skip ObjC protocols definition", + action="store_true") + parser.add_argument("file", help="Path to the Mach-O binary") + args = parser.parse_args() + + lief.logging.set_level(lief.logging.Level.Warn) + return process(args.file, args.skip_protocols, args.output) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/vendor/lief/api/python/examples/pdb_inspect.py b/vendor/lief/api/python/examples/pdb_inspect.py new file mode 100755 index 0000000..092b6e8 --- /dev/null +++ b/vendor/lief/api/python/examples/pdb_inspect.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python +"""Inspect a Microsoft PDB (Program Database) file. + +Loads a ``.pdb`` file and walks its contents: GUID/age metadata, +public symbols, user-defined types (classes) and per-compilation-unit +information (source files and functions). + +Note: only available with the extended version of LIEF. + +Example: + + $ python pdb_inspect.py ./program.pdb +""" + +import argparse +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Path to the PDB file") + args = parser.parse_args() + + pdb = lief.pdb.load(args.file) + if pdb is None: + print(f"Error: failed to load '{args.file}'", file=sys.stderr) + return 1 + + print(f"age={pdb.age}, guid={pdb.guid}") + + for sym in pdb.public_symbols: + print(f"name={sym.name}, section={sym.section_name}, RVA={sym.RVA}") + + for ty in pdb.types: + if isinstance(ty, lief.pdb.types.Class): + print(f"Class[name]={ty.name}") + + for cu in pdb.compilation_units: + print(f"module={cu.module_name}") + for src in cu.sources: + print(f" - {src}") + for func in cu.functions: + print( + f"name={func.name}, section={func.section_name}, " + f"RVA={func.RVA}, code_size={func.code_size}" + ) + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/pe_authenticode.py b/vendor/lief/api/python/examples/pe_authenticode.py new file mode 100755 index 0000000..ac3d455 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_authenticode.py @@ -0,0 +1,83 @@ +#!/usr/bin/env python +"""Verify Authenticode signatures and inspect certificates in PE binaries. + +Checks whether a PE binary has a valid Authenticode signature, computes +authentihash digests, and lists all certificates in the signature chain. + +Example: + + $ python pe_authenticode.py driver.sys + Authenticode Report: driver.sys + ================================================ + Signature Present: Yes + Verification: OK + Authentihash (MD5): a1:b2:c3:... + Authentihash (SHA-256): de:ad:be:... + + Certificate Chain: + [0] Subject: CN=Microsoft Windows, O=Microsoft Corporation + Issuer: CN=Microsoft Windows Verification PCA + Serial: 61:01:c6:c1:... + Valid: 2008-10-22 -> 2010-01-22 + ... +""" + +import sys + +import lief + + +def verify_authenticode(filename): + """Verify Authenticode signature and print certificate details.""" + binary = lief.PE.parse(filename) + if binary is None: + print(f"Error: failed to parse '{filename}' as PE") + return False + + print(f"Authenticode Report: {filename}") + print("=" * 48) + + if not binary.signatures: + print(" Signature Present: No") + print() + return True + + # Overall verification + result = binary.verify_signature() + is_valid = result == lief.PE.Signature.VERIFICATION_FLAGS.OK + print(f" {'Signature Present:':<30} Yes") + print(f" {'Verification:':<30} {'OK' if is_valid else str(result)}") + + # Authentihash digests + print(f" {'Authentihash (MD5):':<30} {binary.authentihash_md5.hex(':')}") + print(f" {'Authentihash (SHA-256):':<30} {binary.authentihash_sha256.hex(':')}") + print() + + # Certificate chain for each signature + for sig_idx, sig in enumerate(binary.signatures): + label = ( + f"Signature #{sig_idx}" + if len(binary.signatures) > 1 + else "Certificate Chain" + ) + print(f" {label}:") + print(f" Digest Algorithm: {sig.digest_algorithm}") + print() + + for idx, cert in enumerate(sig.certificates): + print(f" [{idx}] Subject: {cert.subject}") + print(f" Issuer: {cert.issuer}") + print(f" Serial: {cert.serial_number.hex(':')}") + print(f" Valid: {cert.valid_from} -> {cert.valid_to}") + print() + + return True + + +if __name__ == "__main__": + if len(sys.argv) < 2: + print(f"Usage: {sys.argv[0]} [pe_binary ...]") + sys.exit(1) + + for path in sys.argv[1:]: + verify_authenticode(path) diff --git a/vendor/lief/api/python/examples/pe_authenticode_api_example.py b/vendor/lief/api/python/examples/pe_authenticode_api_example.py new file mode 100755 index 0000000..53cfc42 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_authenticode_api_example.py @@ -0,0 +1,80 @@ +#!/usr/bin/env python +"""Walk-through of LIEF's Authenticode API. + +Exercises the most useful entry points of the Authenticode surface: +computing authentihashes, calling ``verify_signature``, iterating +over the certificate chain and verifying the chain against a trust +bundle pointed to by the ``LIEF_CA_BUNDLE`` environment variable. + +Example: + + $ LIEF_CA_BUNDLE=/path/to/authenticode-bundle.pem \\ + python api_example.py avast_free_antivirus_setup_online.exe +""" + +import argparse +import os +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to a PE binary") + parser.add_argument( + "--bundle", + default=os.getenv("LIEF_CA_BUNDLE"), + help="Path to a PEM bundle of trust anchors (default: $LIEF_CA_BUNDLE)", + ) + args = parser.parse_args() + + pe = lief.PE.parse(args.binary) + if pe is None: + print(f"Error: failed to parse '{args.binary}' as PE", file=sys.stderr) + return 1 + + # Authentihash digests. + print(pe.authentihash_md5.hex(":")) + print(pe.authentihash(lief.PE.ALGORITHMS.SHA_1).hex(":")) + + # PKCS #7 signature verification. + print(pe.verify_signature()) + + if not pe.signatures: + print("No signature embedded in the PE", file=sys.stderr) + return 1 + + signature = pe.signatures[0] + + # Look for a well-known DigiCert root CA in the embedded chain. + bin_ca = None + target_issuer = ( + "C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA" + ) + for crt in signature.certificates: + if crt.issuer == target_issuer: + bin_ca = crt + break + if bin_ca is None: + print("No DigiCert root CA found in the signature chain", file=sys.stderr) + return 1 + + # Verify the selected CA against an external trust bundle (e.g. the + # authenticode bundle shipped with signify). + if args.bundle is not None: + bundle = lief.PE.x509.parse(args.bundle) + print(bin_ca.is_trusted_by(bundle)) + + # Verify that the signer certificate was signed by the selected CA. + cert_signer = signature.signers[0].cert + print(cert_signer) + if cert_signer is None: + print("Signer certificate is missing", file=sys.stderr) + return 1 + print(bin_ca.verify(cert_signer)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/pe_authenticode_reader.py b/vendor/lief/api/python/examples/pe_authenticode_reader.py new file mode 100755 index 0000000..85681b6 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_authenticode_reader.py @@ -0,0 +1,416 @@ +#!/usr/bin/env python +"""Detailed dump of a PE Authenticode signature (or a standalone .p7b). + +Pretty-prints every attribute of an Authenticode signature: content +info, digest algorithms, certificates, signers, authenticated and +unauthenticated attributes (including PKCS9 counter-signatures and +MS-specific nested signatures). + +Can also verify the signature and extract the raw PKCS#7 blob. + +Example: + + $ python authenticode_reader.py --all driver.sys + $ python authenticode_reader.py --check --allow-expired driver.sys + $ python authenticode_reader.py --save out.p7b driver.sys +""" + +import argparse +import pathlib +import sys +import traceback + +import lief + +HAS_EXCEPTION = False + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + global HAS_EXCEPTION + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + HAS_EXCEPTION = True + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60, file=sys.stderr) + print(f"Exception in {self.func.__name__}: {e}") + traceback.print_exc() + print("-" * 60, file=sys.stderr) + + +@exceptions_handler(Exception) +def print_attr(indent: int, auth: lief.PE.Attribute): + if auth.type == lief.PE.Attribute.TYPE.CONTENT_TYPE: + print_content_type(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.PKCS9_SIGNING_TIME: + print_signing_time(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.MS_SPC_STATEMENT_TYPE: + print_ms_statement_type(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.PKCS9_MESSAGE_DIGEST: + print_pkcs_msg_dg(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.PKCS9_COUNTER_SIGNATURE: + print_pkcs_counter_sig(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.GENERIC_TYPE: + print_generic_type(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.SPC_SP_OPUS_INFO: + print_spc_sp_opus_info(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.MS_SPC_NESTED_SIGN: + print_ms_nested_sig(indent, auth) + elif auth.type == lief.PE.Attribute.TYPE.PKCS9_AT_SEQUENCE_NUMBER: + print_pkcs9_at_seq_number(indent, auth) + else: + print(" " * indent, type(auth), auth) + + +@exceptions_handler(Exception) +def print_pkcs9_at_seq_number(indent: int, auth: lief.PE.PKCS9AtSequenceNumber): + print("{} PKCS #9 sequence number: {}".format(" " * indent, auth.number)) + + +@exceptions_handler(Exception) +def print_ms_nested_sig(indent: int, auth: lief.PE.MsSpcNestedSignature): + print("{} MS Nested Signature:".format(" " * indent)) + print_all(auth.signature, indent + 2) + + +@exceptions_handler(Exception) +def print_spc_sp_opus_info(indent: int, auth: lief.PE.SpcSpOpusInfo): + if len(auth.program_name) > 0 and len(auth.more_info) > 0: + print("{} Info: {} {}".format(" " * indent, auth.program_name, auth.more_info)) + elif len(auth.program_name) > 0 and len(auth.more_info) == 0: + print("{} Info: {}".format(" " * indent, auth.program_name)) + elif len(auth.program_name) == 0 and len(auth.more_info) > 0: + print("{} Info: {}".format(" " * indent, auth.more_info)) + else: + print("{} Info: ".format(" " * indent)) + + +@exceptions_handler(Exception) +def print_generic_type(indent: int, auth: lief.PE.GenericType): + print( + "{} Generic Type {} ({})".format( + " " * indent, auth.oid, lief.PE.oid_to_string(auth.oid) + ) + ) + + +@exceptions_handler(Exception) +def print_content_type(indent: int, auth: lief.PE.ContentType): + print( + "{} Content Type OID: {} ({})".format( + " " * indent, auth.oid, lief.PE.oid_to_string(auth.oid) + ) + ) + + +@exceptions_handler(Exception) +def print_signing_time(indent: int, auth: lief.PE.PKCS9SigningTime): + print( + "{} Signing Time: {}/{:02}/{:02} - {:02}:{:02}:{:02}".format( + " " * indent, *auth.time + ) + ) + + +@exceptions_handler(Exception) +def print_ms_statement_type(indent: int, auth: lief.PE.MsSpcStatementType): + print( + "{} MS Statement type OID: {} ({})".format( + " " * indent, auth.oid, lief.PE.oid_to_string(auth.oid) + ) + ) + + +@exceptions_handler(Exception) +def print_pkcs_msg_dg(indent: int, auth: lief.PE.PKCS9MessageDigest): + print("{} PKCS9 Message Digest: {}".format(" " * indent, auth.digest.hex())) + + +@exceptions_handler(Exception) +def print_crt(indent: int, crt: lief.PE.x509): + print("{} Version : {:d}".format(" " * indent, crt.version)) + print("{} Issuer : {}".format(" " * indent, crt.issuer)) + print("{} Subject : {}".format(" " * indent, crt.subject)) + print("{} Serial Number : {}".format(" " * indent, crt.serial_number.hex())) + print( + "{} Signature Algorithm: {}".format( + " " * indent, lief.PE.oid_to_string(crt.signature_algorithm) + ) + ) + print( + "{} Valid from : {}/{:02d}/{:02d} - {:02d}:{:02d}:{:02d}".format( + " " * indent, *crt.valid_from + ) + ) + print( + "{} Valid to : {}/{:02d}/{:02d} - {:02d}:{:02d}:{:02d}".format( + " " * indent, *crt.valid_to + ) + ) + if len(crt.key_usage) > 0: + print( + "{} Key usage : {}".format( + " " * indent, " - ".join(str(e).split(".")[-1] for e in crt.key_usage) + ) + ) + if len(crt.ext_key_usage) > 0: + print( + "{} Ext key usage : {}".format( + " " * indent, + " - ".join(lief.PE.oid_to_string(e) for e in crt.ext_key_usage), + ) + ) + if crt.rsa_info is not None: + rsa_info = crt.rsa_info + print("{} RSA key size : {}".format(" " * indent, rsa_info.key_size)) + print("{} ===========================================".format(" " * indent)) + + +@exceptions_handler(Exception) +def print_pkcs_counter_sig(indent: int, auth: lief.PE.PKCS9CounterSignature): + print("{} PKCS9 counter signature".format(" " * indent)) + signer = auth.signer + print("{} Version : {:d}".format(" " * indent, signer.version)) + print( + "{} Serial Number : {}".format(" " * indent, signer.serial_number.hex()) + ) + print("{} Issuer : {}".format(" " * indent, signer.issuer)) + print("{} Digest Algorithm : {}".format(" " * indent, signer.digest_algorithm)) + print( + "{} Encryption Algorithm: {}".format( + " " * indent, signer.encryption_algorithm + ) + ) + print( + "{} Encrypted Digest : {} ...".format( + " " * indent, signer.encrypted_digest.hex()[:20] + ) + ) + + if len(signer.authenticated_attributes) > 0: + print("{} Authenticated attributes:".format(" " * indent)) + for sub_auth in signer.authenticated_attributes: + print_attr(indent + 4, sub_auth) + + if len(signer.unauthenticated_attributes) > 0: + print("{} Un-Authenticated attributes:".format(" " * indent)) + for sub_auth in signer.unauthenticated_attributes: + print_attr(indent + 4, sub_auth) + + +@exceptions_handler(Exception) +def print_all(sig: lief.PE.Signature, indent: int = 2): + ci: lief.PE.ContentInfo = sig.content_info + print("{}Signature version : {}".format(" " * indent, sig.version)) + print("{}Digest Algorithm : {!s}".format(" " * indent, sig.digest_algorithm)) + print("{}Content Info:".format(" " * indent)) + print( + "{} Content Type : {!s} ({})".format( + " " * indent, ci.content_type, lief.PE.oid_to_string(ci.content_type) + ) + ) + print("{} Digest Algorithm: {!s}".format(" " * indent, ci.digest_algorithm)) + print("{} Digest : {!s}".format(" " * indent, ci.digest.hex())) + print("{}Certificates".format(" " * indent)) + for crt in sig.certificates: + print_crt(indent, crt) + print("{}Signer(s)".format(" " * indent)) + for signer in sig.signers: + print("{} Version : {:d}".format(" " * indent, signer.version)) + print( + "{} Serial Number : {}".format( + " " * indent, signer.serial_number.hex() + ) + ) + print("{} Issuer : {}".format(" " * indent, signer.issuer)) + print( + "{} Digest Algorithm : {}".format(" " * indent, signer.digest_algorithm) + ) + print( + "{} Encryption Algorithm: {}".format( + " " * indent, signer.encryption_algorithm + ) + ) + print( + "{} Encrypted Digest : {} ...".format( + " " * indent, signer.encrypted_digest.hex()[:20] + ) + ) + if len(signer.authenticated_attributes) > 0: + print("{} Authenticated attributes:".format(" " * indent)) + for auth in signer.authenticated_attributes: + print_attr(indent + 4, auth) + + if len(signer.unauthenticated_attributes) > 0: + print("{} Un-authenticated attributes:".format(" " * indent)) + for auth in signer.unauthenticated_attributes: + print_attr(indent + 4, auth) + + +@exceptions_handler(Exception) +def show_crts(sig: lief.PE.Signature, args): + for crt in sig.certificates: + print_crt(0, crt) + + +@exceptions_handler(Exception) +def process_signature(sig: lief.PE.Signature, args): + if args.show_all: + print_all(sig) + + if args.show_crt: + show_crts(sig, args) + + if args.show_hash: + print(f"Authentihash: {sig.content_info.digest.hex()}") + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("file") + + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + + parser.add_argument( + "-c", + "--crt", + action="store_true", + dest="show_crt", + help="Show embedded x509 certificates", + ) + + parser.add_argument( + "-H", + "--hash", + action="store_true", + dest="show_hash", + help="Show the authentihash value", + ) + + parser.add_argument( + "-C", + "--check", + action="store_true", + dest="check_sig", + help="Check the signature", + ) + + parser.add_argument( + "-D", + "--allow-expired", + action="store_true", + dest="allow_expired", + help="Allow expired certificates", + ) + + parser.add_argument( + "-s", "--save", dest="ext_file_path", help="Extract and save the PKCS #7" + ) + + # Logging setup + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + lief.logging.set_level(args.main_verbosity) + + if lief.is_pe(args.file): + binary = lief.PE.parse(args.file) + if binary is None: + print(f"Error while parsing {args.file}") + sys.exit(1) + + if args.check_sig: + flags = lief.PE.Signature.VERIFICATION_CHECKS.DEFAULT + if args.allow_expired: + flags = lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME + res = binary.verify_signature(flags) + print(res) + + if args.show_hash: + print(f"Binary MD5 authentihash: {binary.authentihash_md5.hex()}") + print(f"Binary SHA-1 authentihash: {binary.authentihash_sha1.hex()}") + print(f"Binary SHA-256 authentihash: {binary.authentihash_sha256.hex()}") + + for idx, sig in enumerate(binary.signatures): + process_signature(sig, args) + if args.ext_file_path: + path = args.ext_file_path + if idx > 0: + path += str(idx) + if not path.endswith(".p7b"): + path += ".p7b" + outpath = pathlib.Path(path) + outpath.write_bytes(sig.raw_der) + print(f"Signature saved to {outpath}") + else: + # Try as a regular p7b signature + sig = lief.PE.Signature.parse(args.file) + if sig is None: + print("Fail to parse the signature") + sys.exit(1) + process_signature(sig, args) + + +if __name__ == "__main__": + main() + if HAS_EXCEPTION: + sys.exit(1) diff --git a/vendor/lief/api/python/examples/pe_extract_features.py b/vendor/lief/api/python/examples/pe_extract_features.py new file mode 100755 index 0000000..9d14738 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_extract_features.py @@ -0,0 +1,286 @@ +#!/usr/bin/env python +"""Extract PE binary features for analysis and machine learning. + +Extracts structural features from PE files suitable for malware detection, +binary classification, or general analysis. Outputs a JSON report of the +binary's characteristics. + +Example: + + $ python pe_extract_features.py malware.exe + { + "filename": "malware.exe", + "header": { ... }, + "sections": [ ... ], + "imports": { ... }, + "exports": { ... }, + "rich_header": { ... }, + ... + } + + $ python pe_extract_features.py --summary program.exe + Feature Summary: program.exe + ================================================ + File Size: 102400 bytes + Sections: 5 + Imports: 3 libraries, 47 functions + ... +""" + +import argparse +import json +import math +import sys +from collections import Counter + +import lief + + +def compute_entropy(data): + """Compute Shannon entropy of a byte sequence.""" + if not data: + return 0.0 + counter = Counter(data) + length = len(data) + entropy = 0.0 + for count in counter.values(): + p = count / length + if p > 0: + entropy -= p * math.log2(p) + return round(entropy, 4) + + +def extract_header_features(binary): + """Extract PE header features.""" + hdr = binary.header + opt = binary.optional_header + + return { + "machine": str(hdr.machine), + "number_of_sections": hdr.numberof_sections, + "timestamp": hdr.time_date_stamps, + "characteristics": [str(c) for c in hdr.characteristics_list], + "magic": str(opt.magic), + "major_linker_version": opt.major_linker_version, + "minor_linker_version": opt.minor_linker_version, + "sizeof_code": opt.sizeof_code, + "sizeof_initialized_data": opt.sizeof_initialized_data, + "sizeof_uninitialized_data": opt.sizeof_uninitialized_data, + "entrypoint": opt.addressof_entrypoint, + "imagebase": opt.imagebase, + "section_alignment": opt.section_alignment, + "file_alignment": opt.file_alignment, + "sizeof_image": opt.sizeof_image, + "sizeof_headers": opt.sizeof_headers, + "dll_characteristics": [str(c) for c in opt.dll_characteristics_list], + "subsystem": str(opt.subsystem), + } + + +def extract_section_features(binary): + """Extract features for each PE section.""" + sections = [] + for section in binary.sections: + raw = bytes(section.content) + sections.append( + { + "name": section.name, + "virtual_size": section.virtual_size, + "virtual_address": section.virtual_address, + "sizeof_raw_data": section.size, + "entropy": compute_entropy(raw), + "characteristics": [str(c) for c in section.characteristics_lists], + } + ) + return sections + + +def extract_import_features(binary): + """Extract import table features.""" + imports = {} + total_functions = 0 + + for imp in binary.imports: + functions = [ + entry.name if not entry.is_ordinal else f"ord({entry.ordinal})" + for entry in imp.entries + ] + imports[imp.name] = functions + total_functions += len(functions) + + return { + "libraries": list(imports.keys()), + "library_count": len(imports), + "function_count": total_functions, + "details": imports, + } + + +def extract_export_features(binary): + """Extract export table features.""" + export = binary.get_export() + if export is None: + return {"name": None, "count": 0, "entries": []} + + entries = [] + for entry in export.entries: + e = {"name": entry.name, "ordinal": entry.ordinal} + if entry.is_forwarded: + fwd = entry.forward_information + e["forwarded_to"] = f"{fwd.library}.{fwd.function}" + entries.append(e) + + return { + "name": export.name, + "count": len(entries), + "entries": entries, + } + + +def extract_rich_header_features(binary): + """Extract Rich header features (compiler toolchain info).""" + if binary.rich_header is None: + return None + + entries = [] + for entry in binary.rich_header.entries: + entries.append( + { + "build_id": entry.build_id, + "count": entry.count, + "id": entry.id, + } + ) + + return { + "entries": entries, + "key": binary.rich_header.key, + } + + +def extract_signature_features(binary): + """Extract Authenticode signature info.""" + if not binary.signatures: + return {"signed": False} + + sigs = [] + for sig in binary.signatures: + certs = [] + for cert in sig.certificates: + certs.append( + { + "subject": cert.subject, + "issuer": cert.issuer, + "serial_number": cert.serial_number.hex(), + "valid_from": str(cert.valid_from), + "valid_to": str(cert.valid_to), + } + ) + sigs.append( + { + "version": sig.version, + "digest_algorithm": str(sig.digest_algorithm), + "certificates": certs, + } + ) + + result = binary.verify_signature() + return { + "signed": True, + "valid": result == lief.PE.Signature.VERIFICATION_FLAGS.OK, + "verification": str(result), + "signatures": sigs, + } + + +def extract_all_features(filename): + """Extract all features from a PE binary.""" + binary = lief.PE.parse(filename) + if binary is None: + return None + + return { + "filename": filename, + "header": extract_header_features(binary), + "sections": extract_section_features(binary), + "imports": extract_import_features(binary), + "exports": extract_export_features(binary), + "rich_header": extract_rich_header_features(binary), + "signature": extract_signature_features(binary), + } + + +def print_summary(features): + """Print a human-readable summary of extracted features.""" + print(f"Feature Summary: {features['filename']}") + print("=" * 48) + + hdr = features["header"] + print(f" {'Machine:':<28} {hdr['machine']}") + print(f" {'Subsystem:':<28} {hdr['subsystem']}") + print(f" {'Entrypoint:':<28} 0x{hdr['entrypoint']:x}") + print(f" {'Image Size:':<28} {hdr['sizeof_image']} bytes") + print() + + sections = features["sections"] + print(f" Sections ({len(sections)}):") + for sec in sections: + flag = "" + if sec["entropy"] > 7.0: + flag = " [HIGH ENTROPY]" + elif sec["entropy"] < 0.5 and sec["sizeof_raw_data"] > 0: + flag = " [LOW ENTROPY]" + print( + f" {sec['name']:<12} size={sec['sizeof_raw_data']:<8} entropy={sec['entropy']:.2f}{flag}" + ) + print() + + imp = features["imports"] + print( + f" Imports: {imp['library_count']} libraries, {imp['function_count']} functions" + ) + for lib in imp["libraries"]: + print(f" {lib} ({len(imp['details'][lib])} functions)") + print() + + exp = features["exports"] + if exp["count"] > 0: + print(f" Exports: {exp['count']} functions (DLL name: {exp['name']})") + print() + + sig = features["signature"] + print(f" Signed: {'Yes' if sig['signed'] else 'No'}") + if sig["signed"]: + print(f" Signature Valid: {'Yes' if sig['valid'] else 'No'}") + print() + + +def main(): + parser = argparse.ArgumentParser( + description="Extract PE binary features for analysis" + ) + parser.add_argument("binaries", nargs="+", help="PE binaries to analyze") + parser.add_argument( + "--summary", + action="store_true", + help="Print human-readable summary instead of JSON", + ) + parser.add_argument( + "--indent", type=int, default=2, help="JSON indentation level (default: 2)" + ) + args = parser.parse_args() + + for path in args.binaries: + features = extract_all_features(path) + if features is None: + print(f"Error: failed to parse '{path}' as PE", file=sys.stderr) + continue + + if args.summary: + print_summary(features) + else: + print(json.dumps(features, indent=args.indent)) + + +if __name__ == "__main__": + main() diff --git a/vendor/lief/api/python/examples/pe_forwardinfo.py b/vendor/lief/api/python/examples/pe_forwardinfo.py new file mode 100755 index 0000000..a96ae30 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_forwardinfo.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python +"""List forwarded exports of a PE binary. + +Walks the export directory of a PE binary and prints every entry +that is a *forward* (an export whose implementation lives in another +DLL). + +Example: + + $ python pe_forwardinfo.py C:\\Windows\\System32\\kernel32.dll +""" + +import argparse +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to a PE binary") + args = parser.parse_args() + + pe = lief.PE.parse(args.binary) + if pe is None: + print(f"Error: failed to parse '{args.binary}' as PE", file=sys.stderr) + return 1 + + exports = pe.get_export() + if exports is None: + print("No export directory") + return 0 + + for e in filter(lambda e: e.is_forwarded, exports.entries): + fwd = e.forward_information + print(f"{e.name:<35} -> {fwd.library}.{fwd.function}") + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/pe_json.py b/vendor/lief/api/python/examples/pe_json.py new file mode 100755 index 0000000..248b59d --- /dev/null +++ b/vendor/lief/api/python/examples/pe_json.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python +"""Dump a PE binary as JSON. + +Parses a PE file and writes a pretty-printed JSON dump of the full +structure (DOS/optional header, sections, imports, exports, resources, +...) using ``lief.to_json``. + +Example: + + $ python pe_json.py C:\\\\Windows\\\\explorer.exe +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to a PE binary") + args = parser.parse_args() + + binary = lief.PE.parse(args.binary) + if binary is None: + print(f"Error: failed to parse '{args.binary}' as PE", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(binary)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/pe_reader.py b/vendor/lief/api/python/examples/pe_reader.py new file mode 100755 index 0000000..04ad566 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_reader.py @@ -0,0 +1,946 @@ +#!/usr/bin/env python +"""Pretty-print the structure of a PE binary. + +Equivalent to ``dumpbin``/``llvm-readobj`` with a selection of the +most useful flags. The file is parsed with ``lief.PE.parse`` and each +requested section (DOS/optional header, sections, imports, exports, +resources, TLS, debug, authenticode, ...) is rendered as a formatted +table. + +Example: + + $ python pe_reader.py -a program.exe +""" + +import argparse +import sys +import traceback + +import lief +from lief import PE + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + _exc_type, _exc_value, exc_traceback = sys.exc_info() + traceback.print_tb(exc_traceback) + print("-" * 60) + + +@exceptions_handler(Exception) +def print_information(binary): + print("== Information ==\n") + format_str = "{:<30} {:<30}" + format_hex = "{:<30} 0x{:<28x}" + print(format_hex.format("Virtual size:", binary.virtual_size)) + print(format_str.format("Imphash:", PE.get_imphash(binary))) + print(format_str.format("PIE:", str(binary.is_pie))) + print(format_str.format("NX:", str(binary.has_nx))) + + +@exceptions_handler(Exception) +def print_header(binary): + dos_header = binary.dos_header + header = binary.header + optional_header = binary.optional_header + + format_str = "{:<33} {:<30}" + format_hex = "{:<33} 0x{:<28x}" + format_dec = "{:<33} {:<30d}" + + print("== Dos Header ==") + print(format_str.format("Magic:", str(dos_header.magic))) + print( + format_dec.format( + "Used bytes in the last page:", dos_header.used_bytes_in_last_page + ) + ) + print(format_dec.format("File size in pages:", dos_header.file_size_in_pages)) + print(format_dec.format("Number of relocations:", dos_header.numberof_relocation)) + print( + format_dec.format( + "Header size in paragraphs:", dos_header.header_size_in_paragraphs + ) + ) + print( + format_dec.format( + "Minimum extra paragraphs:", dos_header.minimum_extra_paragraphs + ) + ) + print( + format_dec.format( + "Maximum extra paragraphs", dos_header.maximum_extra_paragraphs + ) + ) + print(format_dec.format("Initial relative SS", dos_header.initial_relative_ss)) + print(format_hex.format("Initial SP:", dos_header.initial_sp)) + print(format_hex.format("Checksum:", dos_header.checksum)) + print(format_dec.format("Initial IP:", dos_header.initial_ip)) + print(format_dec.format("Initial CS:", dos_header.initial_relative_cs)) + print( + format_hex.format( + "Address of relocation table:", dos_header.addressof_relocation_table + ) + ) + print(format_dec.format("Overlay number:", dos_header.overlay_number)) + print(format_dec.format("OEM ID:", dos_header.oem_id)) + print(format_dec.format("OEM information", dos_header.oem_info)) + print( + format_hex.format( + "Address of optional header:", dos_header.addressof_new_exeheader + ) + ) + print() + + print("== Header ==") + + char_str = " - ".join( + [str(chara).split(".")[-1] for chara in header.characteristics_list] + ) + + print(format_str.format("Signature:", "".join(map(chr, header.signature)))) + print(format_str.format("Machine:", str(header.machine))) + print(format_dec.format("Number of sections:", header.numberof_sections)) + print(format_dec.format("Time Date stamp:", header.time_date_stamps)) + print(format_dec.format("Pointer to symbols:", header.pointerto_symbol_table)) + print(format_dec.format("Number of symbols:", header.numberof_symbols)) + print(format_dec.format("Size of optional header:", header.sizeof_optional_header)) + print(format_str.format("Characteristics:", char_str)) + print() + + dll_char_str = " - ".join( + [ + str(chara).split(".")[-1] + for chara in optional_header.dll_characteristics_lists + ] + ) + subsystem_str = str(optional_header.subsystem).split(".")[-1] + print("== Optional Header ==") + magic = "PE32" if optional_header.magic == PE.PE_TYPE.PE32 else "PE64" + print(format_str.format("Magic:", magic)) + print( + format_dec.format("Major linker version:", optional_header.major_linker_version) + ) + print( + format_dec.format("Minor linker version:", optional_header.minor_linker_version) + ) + print(format_dec.format("Size of code:", optional_header.sizeof_code)) + print( + format_dec.format( + "Size of initialized data:", optional_header.sizeof_initialized_data + ) + ) + print( + format_dec.format( + "Size of uninitialized data:", optional_header.sizeof_uninitialized_data + ) + ) + print(format_hex.format("Entry point:", optional_header.addressof_entrypoint)) + print(format_hex.format("Base of code:", optional_header.baseof_code)) + if magic == "PE32": + print(format_hex.format("Base of data", optional_header.baseof_data)) + print(format_hex.format("Image base:", optional_header.imagebase)) + print(format_hex.format("Section alignment:", optional_header.section_alignment)) + print(format_hex.format("File alignment:", optional_header.file_alignment)) + print( + format_dec.format( + "Major operating system version:", + optional_header.major_operating_system_version, + ) + ) + print( + format_dec.format( + "Minor operating system version:", + optional_header.minor_operating_system_version, + ) + ) + print( + format_dec.format("Major image version:", optional_header.major_image_version) + ) + print( + format_dec.format("Minor image version:", optional_header.minor_image_version) + ) + print( + format_dec.format( + "Major subsystem version:", optional_header.major_subsystem_version + ) + ) + print( + format_dec.format( + "Minor subsystem version:", optional_header.minor_subsystem_version + ) + ) + print( + format_dec.format("WIN32 version value:", optional_header.win32_version_value) + ) + print(format_hex.format("Size of image:", optional_header.sizeof_image)) + print(format_hex.format("Size of headers:", optional_header.sizeof_headers)) + print(format_hex.format("Checksum:", optional_header.checksum)) + print(format_str.format("Subsystem:", subsystem_str)) + print(format_str.format("DLL Characteristics:", dll_char_str)) + print( + format_hex.format( + "Size of stack reserve:", optional_header.sizeof_stack_reserve + ) + ) + print( + format_hex.format("Size of stack commit:", optional_header.sizeof_stack_commit) + ) + print( + format_hex.format("Size of heap reserve:", optional_header.sizeof_heap_reserve) + ) + print(format_hex.format("Size of heap commit:", optional_header.sizeof_heap_commit)) + print(format_dec.format("Loader flags:", optional_header.loader_flags)) + print( + format_dec.format( + "Number of RVA and size:", optional_header.numberof_rva_and_size + ) + ) + print() + + +@exceptions_handler(Exception) +def print_data_directories(binary): + data_directories = binary.data_directories + + print("== Data Directories ==") + f_title = "|{:<24} | {:<10} | {:<10} | {:<8} |" + f_value = "|{:<24} | 0x{:<8x} | 0x{:<8x} | {:<8} |" + print(f_title.format("Type", "RVA", "Size", "Section")) + + for directory in data_directories: + section_name = directory.section.name if directory.has_section else "" + print( + f_value.format( + str(directory.type).split(".")[-1], + directory.rva, + directory.size, + section_name, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_sections(binary): + sections = binary.sections + + print("== Sections ==") + f_title = "|{:<10} | {:<16} | {:<16} | {:<18} | {:<16} | {:<9} | {:<9}" + f_value = ( + "|{:<10} | 0x{:<14x} | 0x{:<14x} | 0x{:<16x} | 0x{:<14x} | {:<9.2f} | {:<9}" + ) + print( + f_title.format( + "Name", + "Offset", + "Size", + "Virtual Address", + "Virtual size", + "Entropy", + "Flags", + ) + ) + + for section in sections: + flags = "" + for flag in section.characteristics_lists: + flags += str(flag).split(".")[-1] + " " + print( + f_value.format( + section.name, + section.offset, + section.size, + section.virtual_address, + section.virtual_size, + section.entropy, + flags, + ) + ) + print() + + +@exceptions_handler(Exception) +def print_symbols(binary): + symbols = binary.symbols + if len(symbols) > 0: + print("== Symbols ==") + f_title = "|{:<20} | {:<10} | {:<8} | {:<8} | {:<8} | {:<13} |" + f_value = "|{:<20} | 0x{:<8x} | {:<14} | {:<10} | {:<12} | {:<13} |" + + print( + f_title.format( + "Name", + "Value", + "Section number", + "Basic type", + "Complex type", + "Storage class", + ) + ) + for symbol in symbols: + if symbol.section_number <= 0: + section_nb_str = str( + PE.SYMBOL_SECTION_NUMBER(symbol.section_number) + ).split(".")[-1] + else: + try: + section_nb_str = symbol.section.name + except Exception: # noqa + section_nb_str = f"section<{symbol.section_number:d}>" + + print( + f_value.format( + symbol.name[:20], + symbol.value, + section_nb_str, + str(symbol.base_type).split(".")[-1], + str(symbol.complex_type).split(".")[-1], + str(symbol.storage_class).split(".")[-1], + ) + ) + + +@exceptions_handler(Exception) +def print_imports(binary, resolve=False): + print("== Imports ==") + imports = binary.imports + + for import_ in imports: + if resolve: + import_ = lief.PE.resolve_ordinals(import_) + + print(import_.name) + entries = import_.entries + f_value = " {:<33} 0x{:<14x} 0x{:<14x} 0x{:<16x}" + for entry in entries: + print(f_value.format(entry.name, entry.data, entry.iat_value, entry.hint)) + print() + + +@exceptions_handler(Exception) +def print_tls(binary): + format_str = "{:<33} {:<30}" + format_hex = "{:<33} 0x{:<28x}" + + print("== TLS ==") + tls = binary.tls + callbacks = tls.callbacks + print(format_hex.format("Address of callbacks:", tls.addressof_callbacks)) + if len(callbacks) > 0: + print("Callbacks:") + for callback in callbacks: + print(" " + hex(callback)) + + print(format_hex.format("Address of index:", tls.addressof_index)) + print(format_hex.format("Size of zero fill:", tls.sizeof_zero_fill)) + print( + "{:<33} 0x{:<10x} 0x{:<10x}".format( + "Address of raw data:", tls.addressof_raw_data[0], tls.addressof_raw_data[1] + ) + ) + print(format_hex.format("Size of raw data:", len(tls.data_template))) + print(format_hex.format("Characteristics:", tls.characteristics)) + print(format_str.format("Section:", tls.section.name)) + print(format_str.format("Data directory:", str(tls.directory.type))) + print() + + +@exceptions_handler(Exception) +def print_relocations(binary): + relocations = binary.relocations + print("== Relocations ==") + for relocation in relocations: + entries = relocation.entries + print(hex(relocation.virtual_address)) + for entry in entries: + print( + " 0x{:<8x} {:<8}".format( + entry.position, str(entry.type).split(".")[-1] + ) + ) + print() + + +@exceptions_handler(Exception) +def print_export(binary): + print("== Exports ==") + exports = binary.get_export() + entries = exports.entries + f_value = "{:<20} 0x{:<10x} 0x{:<10x} 0x{:<6x} 0x{:<6x} 0x{:<10x}" + print( + f_value.format( + exports.name, + exports.export_flags, + exports.timestamp, + exports.major_version, + exports.minor_version, + exports.ordinal_base, + ) + ) + entries = sorted(entries, key=lambda e: e.ordinal) + for entry in entries: + extern = "[EXTERN]" if entry.is_extern else "" + print( + f" {entry.name[:20]:<20} {entry.ordinal:d} 0x{entry.address:<10x} {extern:<13}" + ) + print() + + +@exceptions_handler(Exception) +def print_debug(binary): + format_str = "{:<33} {:<30}" + format_hex = "{:<33} 0x{:<28x}" + format_dec = "{:<33} {:<30d}" + + debugs = binary.debug + print(f"== Debug ({len(debugs)}) ==") + for debug in debugs: + print(format_hex.format("Characteristics:", debug.characteristics)) + print(format_hex.format("Timestamp:", debug.timestamp)) + print(format_dec.format("Major version:", debug.major_version)) + print(format_dec.format("Minor version:", debug.minor_version)) + print(format_str.format("type:", str(debug.type).split(".")[-1])) + print(format_hex.format("Size of data:", debug.sizeof_data)) + print(format_hex.format("Address of raw data:", debug.addressof_rawdata)) + print(format_hex.format("Pointer to raw data:", debug.pointerto_rawdata)) + + if isinstance(debug, lief.PE.CodeViewPDB): + code_view: lief.PE.CodeViewPDB = debug + cv_signature = code_view.cv_signature + sig_str = " ".join(f"{e:02x}" for e in code_view.signature) + print( + format_str.format( + "Code View Signature:", str(cv_signature).split(".")[-1] + ) + ) + print(format_str.format("Signature:", sig_str)) + print(format_dec.format("Age:", code_view.age)) + print(format_str.format("Filename:", code_view.filename)) + elif isinstance(debug, lief.PE.CodeView): + code_view: lief.PE.CodeView = debug + cv_signature = code_view.cv_signature + print( + format_str.format( + "Code View Signature:", str(cv_signature).split(".")[-1] + ) + ) + elif isinstance(debug, lief.PE.Pogo): + pogo: lief.PE.Pogo = debug + sig_str = str(pogo.signature).split(".")[-1] + print(format_str.format("Signature:", sig_str)) + print("Entries:") + for entry in pogo.entries: + print(f" {entry.name:<20} 0x{entry.start_rva:x} ({entry.size:d})") + + print("\n") + + +@exceptions_handler(Exception) +def print_signature(binary): + for signature in binary.signatures: + print(signature) + + +@exceptions_handler(Exception) +def print_rich_header(binary): + print("== Rich Header ==") + header = binary.rich_header + print(f"Key: 0x{header.key:08x}") + + for entry in header.entries: + print( + f" - ID: {entry.id:04x} Build ID: {entry.build_id:04x} Count: {entry.count:d}" + ) + print() + + +@exceptions_handler(Exception) +def print_resources(binary): + print("== Resources ==") + manager = binary.resources_manager + + print(manager) + + print() + + +@exceptions_handler(Exception) +def print_load_configuration(binary): + format_str = "{:<45} {:<30}" + format_hex = "{:<45} 0x{:<28x}" + format_dec = "{:<45} {:<30d}" + + print("== Load Configuration ==") + config = binary.load_configuration + + print(format_str.format("Version:", str(config.version).split(".")[-1])) + print(format_dec.format("Characteristics:", config.characteristics)) + print(format_dec.format("Timedatestamp:", config.timedatestamp)) + print(format_dec.format("Major version:", config.major_version)) + print(format_dec.format("Minor version:", config.minor_version)) + print(format_hex.format("Global flags clear:", config.global_flags_clear)) + print(format_hex.format("Global flags set:", config.global_flags_set)) + print( + format_dec.format( + "Critical section default timeout:", config.critical_section_default_timeout + ) + ) + print( + format_hex.format( + "Decommit free block threshold:", config.decommit_free_block_threshold + ) + ) + print( + format_hex.format( + "Decommit total free threshold:", config.decommit_total_free_threshold + ) + ) + print(format_hex.format("Lock prefix table:", config.lock_prefix_table)) + print(format_hex.format("Maximum allocation size:", config.maximum_allocation_size)) + print( + format_hex.format("Virtual memory threshold:", config.virtual_memory_threshold) + ) + print(format_hex.format("Process affinity mask:", config.process_affinity_mask)) + print(format_hex.format("Process heap flags:", config.process_heap_flags)) + print(format_hex.format("CSD Version:", config.csd_version)) + print(format_hex.format("Reserved 1:", config.reserved1)) + print(format_hex.format("Edit list:", config.editlist)) + print(format_hex.format("Security cookie:", config.security_cookie)) + + if isinstance(config, lief.PE.LoadConfigurationV0): + print(format_hex.format("SE handler table:", config.se_handler_table)) + print(format_dec.format("SE handler count:", config.se_handler_count)) + + if isinstance(config, lief.PE.LoadConfigurationV1): + flags_str = " - ".join( + str(e).split(".")[-1] for e in config.guard_cf_flags_list + ) + print( + format_hex.format( + "GCF check function pointer:", config.guard_cf_check_function_pointer + ) + ) + print( + format_hex.format( + "GCF dispatch function pointer:", + config.guard_cf_dispatch_function_pointer, + ) + ) + print(format_hex.format("GCF function table :", config.guard_cf_function_table)) + print(format_dec.format("GCF Function count :", config.guard_cf_function_count)) + print( + "{:<45} {} (0x{:x})".format( + "Guard flags:", flags_str, int(config.guard_flags) + ) + ) + + if isinstance(config, lief.PE.LoadConfigurationV2): + code_integrity = config.code_integrity + print("Code Integrity:") + print(format_dec.format(" " * 3 + "Flags:", code_integrity.flags)) + print(format_dec.format(" " * 3 + "Catalog:", code_integrity.catalog)) + print( + format_hex.format( + " " * 3 + "Catalog offset:", code_integrity.catalog_offset + ) + ) + print(format_dec.format(" " * 3 + "Reserved:", code_integrity.reserved)) + + if isinstance(config, lief.PE.LoadConfigurationV3): + print( + format_hex.format( + "Guard address taken iat entry table:", + config.guard_address_taken_iat_entry_table, + ) + ) + print( + format_hex.format( + "Guard address taken iat entry count:", + config.guard_address_taken_iat_entry_count, + ) + ) + print( + format_hex.format( + "Guard long jump target table:", config.guard_long_jump_target_table + ) + ) + print( + format_hex.format( + "Guard long jump target count:", config.guard_long_jump_target_count + ) + ) + + if isinstance(config, lief.PE.LoadConfigurationV4): + print( + format_hex.format( + "Dynamic value relocation table:", config.dynamic_value_reloc_table + ) + ) + print( + format_hex.format( + "Hybrid metadata pointer:", config.hybrid_metadata_pointer + ) + ) + + if isinstance(config, lief.PE.LoadConfigurationV5): + print( + format_hex.format("GRF failure routine:", config.guard_rf_failure_routine) + ) + print( + format_hex.format( + "GRF failure routine function pointer:", + config.guard_rf_failure_routine_function_pointer, + ) + ) + print( + format_hex.format( + "Dynamic value reloctable offset:", + config.dynamic_value_reloctable_offset, + ) + ) + print( + format_hex.format( + "Dynamic value reloctable section:", + config.dynamic_value_reloctable_section, + ) + ) + + if isinstance(config, lief.PE.LoadConfigurationV6): + print( + format_hex.format( + "GRF verify stackpointer function pointer:", + config.guard_rf_verify_stackpointer_function_pointer, + ) + ) + print(format_hex.format("Hotpatch table offset:", config.hotpatch_table_offset)) + + if isinstance(config, lief.PE.LoadConfigurationV7): + print(format_hex.format("Reserved 3:", config.reserved3)) + + print() + + +@exceptions_handler(Exception) +def print_ctor(binary): + print("== Constructors ==\n") + + print(f"Functions: ({len(binary.ctor_functions):d})") + for idx, f in enumerate(binary.ctor_functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_exception_functions(binary): + print("== Exception functions ==\n") + + print(f"Functions: ({len(binary.exception_functions):d})") + for idx, f in enumerate(binary.exception_functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x}") + + +@exceptions_handler(Exception) +def print_functions(binary): + print("== Functions ==\n") + + print(f"Functions: ({len(binary.functions):d})") + for idx, f in enumerate(binary.functions): + print(f" [{idx:d}] {f.name}: 0x{f.address:x} ({f.size:d} bytes)") + + +@exceptions_handler(Exception) +def print_delay_imports(binary): + delay_imports = binary.delay_imports + if len(delay_imports) == 0: + return + print("== Delay Imports ==\n") + for imp in delay_imports: + print(imp.name) + print(f" Attribute: {imp.attribute}") + print(f" Handle: 0x{imp.handle:x}") + print(f" IAT: 0x{imp.iat:x}") + print(f" Names Table: 0x{imp.names_table:x}") + print(f" Bound IAT: 0x{imp.biat:x}") + print(f" Unload IAT: 0x{imp.uiat:x}") + print(f" Timestamp: 0x{imp.timestamp:x}") + for entry in imp.entries: + print( + f" {entry.name:<25} 0x{entry.value:08x}: 0x{entry.iat_value:010x} - 0x{entry.hint:x}" + ) + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("pe_file") + + parser.add_argument( + "-a", + "--all", + action="store_true", + dest="show_all", + help="Show all informations", + ) + + parser.add_argument( + "-d", + "--data-directories", + action="store_true", + dest="show_data_directories", + help="Display data directories", + ) + + parser.add_argument( + "--dbg", action="store_true", dest="show_debug", help="Display debug directory" + ) + + parser.add_argument( + "-g", + "--signature", + action="store_true", + dest="show_signature", + help="Display the binary's signature if any", + ) + + parser.add_argument( + "-H", + "--header", + action="store_true", + dest="show_headers", + help="Display headers", + ) + + parser.add_argument( + "-i", + "--import", + action="store_true", + dest="show_imports", + help="Display imported functions and libraries", + ) + + parser.add_argument( + "--resolve-ordinals", + action="store_true", + dest="resolve_ordinals", + help="When used with --import, it attempts to resolve names of ordinal imports", + ) + + parser.add_argument( + "-r", + "--relocs", + action="store_true", + dest="show_relocs", + help="Display the relocations (if present)", + ) + + parser.add_argument( + "-R", + "--rich-header", + action="store_true", + dest="show_richheader", + help="Display the Rich Header", + ) + + parser.add_argument( + "--resources", + "--rsrc", + action="store_true", + dest="show_resources", + help="Display the resources (if present)", + ) + + parser.add_argument( + "-S", + "--section-headers", + "--sections", + action="store_true", + dest="show_section_header", + help="Display the sections' headers", + ) + + parser.add_argument( + "-s", + "--symbols", + "--syms", + action="store_true", + dest="show_symbols", + help="Display symbols", + ) + + parser.add_argument( + "-t", + "--tls", + action="store_true", + dest="show_tls", + help="Display TLS informations", + ) + + parser.add_argument( + "-x", + "--export", + action="store_true", + dest="show_export", + help="Display exported functions/libraries", + ) + + parser.add_argument( + "--load-config", + action="store_true", + dest="show_loadconfig", + help="Display load configuration", + ) + + parser.add_argument( + "--ctor", action="store_true", dest="show_ctor", help="Constructor functions" + ) + + parser.add_argument( + "-f", + "--functions", + action="store_true", + dest="show_functions", + help="Display all functions found in the binary", + ) + + parser.add_argument( + "--exception-functions", + action="store_true", + dest="show_pfunctions", + help="Display functions found in the exception directory", + ) + + parser.add_argument( + "--delay-imports", + action="store_true", + dest="show_delay_imports", + help="Display delay imports", + ) + + # Logging setup + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + lief.logging.set_level(args.main_verbosity) + + binary = PE.parse(args.pe_file) + + if binary is None: + sys.exit(1) + + print_information(binary) + + if args.show_data_directories or args.show_all: + print_data_directories(binary) + + if args.show_headers or args.show_all: + print_header(binary) + + if (args.show_imports or args.show_all) and binary.has_imports: + print_imports(binary, resolve=args.resolve_ordinals) + + if (args.show_relocs or args.show_all) and binary.has_relocations: + print_relocations(binary) + + if args.show_section_header or args.show_all: + print_sections(binary) + + if args.show_symbols or args.show_all: + print_symbols(binary) + + if (args.show_tls or args.show_all) and binary.has_tls: + print_tls(binary) + + if (args.show_export or args.show_all) and binary.has_exports: + print_export(binary) + + if (args.show_debug or args.show_all) and binary.has_debug: + print_debug(binary) + + if (args.show_signature or args.show_all) and binary.has_signatures: + print_signature(binary) + + if (args.show_richheader or args.show_all) and binary.has_rich_header: + print_rich_header(binary) + + if (args.show_resources or args.show_all) and binary.has_resources: + print_resources(binary) + + if (args.show_loadconfig or args.show_all) and binary.has_configuration: + print_load_configuration(binary) + + if args.show_ctor or args.show_all: + print_ctor(binary) + + if args.show_functions or args.show_all: + print_functions(binary) + + if args.show_pfunctions or args.show_all: + print_exception_functions(binary) + + if args.show_delay_imports or args.show_all: + print_delay_imports(binary) + + +if __name__ == "__main__": + main() diff --git a/vendor/lief/api/python/examples/pe_resources_manager.py b/vendor/lief/api/python/examples/pe_resources_manager.py new file mode 100755 index 0000000..a820179 --- /dev/null +++ b/vendor/lief/api/python/examples/pe_resources_manager.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python +"""Dump the resource tree and manifest of a PE binary. + +Uses ``lief.PE.ResourcesManager`` to render a friendly view of the +``.rsrc`` section followed by the XML manifest embedded in the +binary (when present). + +Example: + + $ python pe_resources_manager.py C:\\Windows\\explorer.exe +""" + +import argparse +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("binary", help="Path to a PE binary") + args = parser.parse_args() + + pe = lief.PE.parse(args.binary) + if pe is None: + print(f"Error: failed to parse '{args.binary}' as PE", file=sys.stderr) + return 1 + + manager = pe.resources_manager + if not isinstance(manager, lief.PE.ResourcesManager): + print("Error: failed to access the resource manager") + return 1 + + print(manager) + print(manager.manifest) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/runtime_android.py b/vendor/lief/api/python/examples/runtime_android.py new file mode 100755 index 0000000..687c16b --- /dev/null +++ b/vendor/lief/api/python/examples/runtime_android.py @@ -0,0 +1,195 @@ +#!/usr/bin/env python3 +import ctypes +import sys +from itertools import islice + +import lief + + +def host_info(): + print("Host") + # lief-doc: host-start + print(f" Hostname: {lief.runtime.Host.name}") + print(f" Home: {lief.runtime.Host.home_dir}") + print(f" cache: {lief.runtime.Host.cache_dir}") + print(f" temp: {lief.runtime.Host.tmp_dir}") + print(f" config: {lief.runtime.Host.config_dir}") + # lief-doc: host-end + + # lief-doc: host-android-start + if (sdk := lief.runtime.android.Host.sdk_version) is not None: + print(f" SDK: {sdk}") + # lief-doc: host-android-end + print() + + +def process_info(): + print("Process") + # lief-doc: process-start + print(f" PID: {lief.runtime.Process.pid}") + print(f" TID: {lief.runtime.Process.tid}") + print(f" Page size: {lief.runtime.Process.page_size:#06x}") + print(f" Arch: {lief.runtime.Process.arch}") + print(f" Platform: {lief.runtime.Process.platform}") + # lief-doc: process-end + + # lief-doc: process-android-start + # Access a named property + sdk = lief.runtime.android.Process.get_system_property("ro.build.version.sdk") + if sdk is not None: + print(f" {sdk.name}: {sdk.value} (serial: {sdk.serial})") + + # Iterate over all properties + for prop in lief.runtime.android.Process.properties: + print(f" {prop.name}: {prop.value} (serial: {prop.serial})") + # lief-doc: process-android-end + + +def modules_info(): + print("Module API") + libc: lief.runtime.android.Module | None = None + # lief-doc: modules-start + for mod in lief.runtime.modules(): + print(mod) + # Look for the Bionic libc + if mod.name.endswith("libc.so"): + print( + f"libc.so found: {mod.path} ([{mod.imagebase:#010x}, {mod.end:#010x}])" + ) + assert isinstance(mod, lief.runtime.android.Module) + libc = mod + # lief-doc: modules-end + + if libc is None: + return + + # lief-doc: modules-android-start + print(f"libc path: {libc.path}") + if __cxa_finalize := libc.dlsym("__cxa_finalize"): + __cxa_finalize_addr = lief.to_int(__cxa_finalize) + print(f"{libc.name}!__cxa_finalize: {__cxa_finalize_addr:#010x}") + + if malloc := libc.dlsym("malloc"): + malloc_addr = lief.to_int(malloc) + print(f"{libc.name}!malloc: {malloc_addr:#010x}") + + # With LIEF extended, we can disassemble the function from its + # absolute memory address: + if lief.__extended__: + for inst in islice(lief.runtime.disassemble(malloc_addr), 4): + print(" ", inst) + + if (elf_on_disk := libc.parse_from_path()) is not None and ( + __cxa_finalize := elf_on_disk.get_symbol("__cxa_finalize") + ) is not None: + print(f"__cxa_finalize: {__cxa_finalize.value:#010x}") + + if liblog := lief.runtime.android.dlopen("liblog.so"): + print( + f"liblog loaded: {liblog.path} " + f"(dlopen handler={lief.to_int(liblog.handle):#010x})" + ) + + if log_print := liblog.dlsym("__android_log_print"): + log_print_addr = lief.to_int(log_print) + print(f"{liblog.name}!__android_log_print: {log_print_addr:#010x}") + # lief-doc: modules-android-end + + +def memory_example(): + print("Memory") + # lief-doc: memory-start + chunk = lief.runtime.Memory.mmap( + lief.runtime.Process.page_size, + lief.runtime.Memory.ANONYMOUS | lief.runtime.Memory.PRIVATE, + lief.runtime.Memory.READ | lief.runtime.Memory.WRITE | lief.runtime.Memory.EXEC, + ) + + class Config(lief.assembly.AssemblerConfig): + def resolve_symbol(self, name: str) -> int | None: + libc = lief.runtime.android.dlopen("libc.so") + if libc is None: + print("Failed to dlopen libc.so", file=sys.stderr) + return None + + if name == "write": + return lief.to_int(libc.dlsym("write")) + return None + + config = Config() + + raw_inst = lief.runtime.assemble( + chunk.addr, + r""" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + ldr x8, =write + + mov x0, 1 // STDOUT_FILENO + adr x1, msg // buf = &msg + mov x2, 27 // len = len("LIEF Runtime Extended Demo\n") + blr x8 // write(STDOUT_FILENO, msg, 27) + + ldp x29, x30, [sp], 16 + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + """, + config, + ) + + # Disassemble the JITed stub from memory + for inst in islice(lief.runtime.disassemble(chunk.addr), 9): + print(inst) + + # Dump as raw bytes + raw_bytes = lief.runtime.Memory.read(chunk.addr, len(raw_inst)) + print(raw_bytes.hex(":")) + + # Flush the instruction cache before executing the freshly written code + # (this is required on AArch64). + chunk.cache_flush() + + # Change the permission to R-X + chunk.make_rx() + + VoidVoidFunc = ctypes.CFUNCTYPE(None) # void(*)() + hello_jit = VoidVoidFunc(chunk.addr) + hello_jit() + + # Change the message + pos = raw_bytes.find(b"LIEF Runtime") + chunk.make_rw() + lief.runtime.Memory.write(b"Hello Python ctypes World!\n", chunk.addr + pos) + chunk.make_rx() + chunk.cache_flush() + + # Print again + hello_jit() + + # Don't miss good practices! + chunk.deallocate() + # lief-doc: memory-end + + +def main() -> int: + if not lief.runtime.enabled: + print("Error: LIEF's runtime is not enabled", file=sys.stderr) + return 0 + + host_info() + process_info() + modules_info() + memory_example() + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/runtime_linux.py b/vendor/lief/api/python/examples/runtime_linux.py new file mode 100755 index 0000000..ae5ee71 --- /dev/null +++ b/vendor/lief/api/python/examples/runtime_linux.py @@ -0,0 +1,190 @@ +#!/usr/bin/env python3 +import ctypes +import sys +from itertools import islice + +import lief + + +def host_info(): + print("Host") + # lief-doc: host-start + print(f" Hostname: {lief.runtime.Host.name}") + print(f" Home: {lief.runtime.Host.home_dir}") + print(f" cache: {lief.runtime.Host.cache_dir}") + print(f" temp: {lief.runtime.Host.tmp_dir}") + print(f" config: {lief.runtime.Host.config_dir}") + # lief-doc: host-end + + # lief-doc: host-linux-start + print(f" sys_name: {lief.runtime.linux.Host.sys_name}") + print(f" sys_release: {lief.runtime.linux.Host.sys_release}") + print(f" sys_version: {lief.runtime.linux.Host.sys_version}") + print(f" hardware: {lief.runtime.linux.Host.hardware}") + # lief-doc: host-linux-end + print() + + +def process_info(): + print("Process") + # lief-doc: process-start + print(f" PID: {lief.runtime.Process.pid}") + print(f" TID: {lief.runtime.Process.tid}") + print(f" Page size: {lief.runtime.Process.page_size:#06x}") + print(f" Arch: {lief.runtime.Process.arch}") + print(f" Platform: {lief.runtime.Process.platform}") + print(f" TERM: {lief.runtime.Process.get_env('TERM')}") + # lief-doc: process-end + + # lief-doc: process-linux-start + print(f" glibc: {lief.runtime.linux.Process.glibc_version}") + # lief-doc: process-linux-end + + +def modules_info(): + print("Module API") + libc: lief.runtime.linux.Module | None = None + # lief-doc: modules-start + for mod in lief.runtime.modules(): + print(mod) + # Look for the libc + if mod.name.startswith("libc.so"): + print( + f"libc.so found: {mod.path} ([{mod.imagebase:#010x}, {mod.end:#010x}])" + ) + assert isinstance(mod, lief.runtime.linux.Module) + libc = mod + # lief-doc: modules-end + + if libc is None: + return + + # lief-doc: modules-linux-start + print(f"libc path: {libc.path}") + if __cxa_finalize := libc.dlsym("__cxa_finalize"): + __cxa_finalize_addr = lief.to_int(__cxa_finalize) + print(f"{libc.name}!__cxa_finalize: {__cxa_finalize_addr:#010x}") + + if malloc := libc.dlsym("malloc"): + malloc_addr = lief.to_int(malloc) + # lief.to_int is used to convert an opaque pointer (void*) into a + # regular Python int + print(f"{libc.name}!malloc: {malloc_addr:#010x}") + + # With LIEF extended, we can disassemble the function from its + # absolute memory address: + if lief.__extended__: + for inst in islice(lief.runtime.disassemble(malloc_addr), 4): + print(" ", inst) + + # This parses the ELF from its path on the disk + if (elf_on_disk := libc.parse_from_path()) is not None and ( + __cxa_finalize := elf_on_disk.get_symbol("__cxa_finalize") + ) is not None: + print(f"__cxa_finalize: {__cxa_finalize.value:#010x}") + + # This code loads 'librt.so' and wrap the dlopen handler in a Module. + if librt := lief.runtime.linux.dlopen("librt.so.1"): + print( + f"librt loaded: {librt.path} (dlopen handler={lief.to_int(librt.handle):#010x})" + ) + + # Parse the ELF directly from memory. + if librt_mem := librt.parse_from_memory(): + # This code looks for the relocation associated with the + # **imported** symbol `__cxa_finalize` that is defined in the libc. + # The relocation holds the address where the function is resolved. + # Therefore, by reading this relocation address we can access the + # resolved address of `__cxa_finalize`. This address should match + # the value previously returned by dlsym + __cxa_finalize_reloc = next( + ( + reloc + for reloc in librt_mem.relocations + if reloc.symbol is not None + and reloc.symbol.name == "__cxa_finalize" + ), + None, + ) + if __cxa_finalize_reloc is not None: + abs_reloc_addr = librt.imagebase + __cxa_finalize_reloc.address + # We assume a 64-bit architecture + __cxa_finalize_addr = lief.runtime.Memory.read_u64(abs_reloc_addr) + print( + f"{librt.name} -> {abs_reloc_addr:#010x} -> {__cxa_finalize_addr:#010x}" + ) + # lief-doc: modules-linux-end + + +def memory_example(): + # lief-doc: memory-start + chunk = lief.runtime.Memory.mmap( + lief.runtime.Process.page_size, + lief.runtime.Memory.ANONYMOUS | lief.runtime.Memory.PRIVATE, + lief.runtime.Memory.READ | lief.runtime.Memory.WRITE | lief.runtime.Memory.EXEC, + ) + + raw_inst = lief.runtime.assemble( + chunk.addr, + r""" + .global _start + + .text + _start: + push 1 + pop rax + mov edi, eax + lea rsi, [rip + msg] + mov rdx, 28 + syscall + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + """, + ) + + # Ensure the assembly is correctly JITed at the beginning of the allocated + # memory + for inst in islice(lief.runtime.disassemble(chunk.addr), 7): + print(inst) + + # Dump as raw bytes + raw_bytes = lief.runtime.Memory.read(chunk.addr, len(raw_inst)) + print(raw_bytes.hex(":")) + + # Change the permission to R-X + chunk.make_rx() + + VoidVoidFunc = ctypes.CFUNCTYPE(None) # void(*)() + hello_jit = VoidVoidFunc(chunk.addr) + hello_jit() + + # Change the message + pos = raw_bytes.find(b"LIEF Runtime") + chunk.make_rw() + lief.runtime.Memory.write(b"Hello Python ctypes World!\n", chunk.addr + pos) + chunk.make_rx() + + # Print again + hello_jit() + + # Don't miss good practices! + chunk.deallocate() + # lief-doc: memory-end + + +def main() -> int: + if not lief.runtime.enabled: + print("Error: LIEF's runtime is not enabled", file=sys.stderr) + return 0 + + host_info() + process_info() + modules_info() + memory_example() + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/runtime_osx.py b/vendor/lief/api/python/examples/runtime_osx.py new file mode 100755 index 0000000..2ab63b1 --- /dev/null +++ b/vendor/lief/api/python/examples/runtime_osx.py @@ -0,0 +1,202 @@ +#!/usr/bin/env python3 +import ctypes +import sys +from itertools import islice + +import lief + + +def host_info(): + print("Host") + # lief-doc: host-start + print(f" Hostname: {lief.runtime.Host.name}") + print(f" Home: {lief.runtime.Host.home_dir}") + print(f" Cache: {lief.runtime.Host.cache_dir}") + print(f" Temp: {lief.runtime.Host.tmp_dir}") + print(f" Config: {lief.runtime.Host.config_dir}") + # lief-doc: host-end + + # lief-doc: host-osx-start + print(f" Version: {lief.runtime.osx.Host.os_version_name}") + sip = "enabled" if lief.runtime.osx.Host.is_sip_enabled else "disabled" + print(f" SIP: {sip}") + # lief-doc: host-osx-end + print() + + +def process_info(): + print("Process") + # lief-doc: process-start + print(f" PID: {lief.runtime.Process.pid}") + print(f" TID: {lief.runtime.Process.tid}") + print(f" Page size: {lief.runtime.Process.page_size:#06x}") + print(f" Arch: {lief.runtime.Process.arch}") + print(f" Platform: {lief.runtime.Process.platform}") + # lief-doc: process-end + + # lief-doc: process-osx-start + print(f" dyld: {lief.runtime.osx.Process.dyld_version}") + # lief-doc: process-osx-end + + +def modules_info(): + print("Module API") + + # Module referencing libsystem_c.dylib in memory + libsystem: lief.runtime.osx.Module | None = None + + # lief-doc: modules-start + for mod in lief.runtime.modules(): + print(mod) + # Look for the C library + if mod.name.endswith("libsystem_c.dylib"): + print( + f"libsystem_c.dylib found: {mod.path} ([{mod.imagebase:#010x}, {mod.end:#010x}])" + ) + assert isinstance(mod, lief.runtime.osx.Module) + libsystem = mod + # lief-doc: modules-end + + if libsystem is None: + return + + # lief-doc: modules-osx-start + print(f"libsystem_c path: {libsystem.path}") + if arc4_init := libsystem.dlsym("arc4_init"): + # lief.to_int converts an opaque pointer (void*) into a regular Python int + arc4_init_addr = lief.to_int(arc4_init) + print(f"{libsystem.name}!arc4_init: {arc4_init_addr:#010x}") + + # With LIEF extended, we can disassemble the function directly from its + # absolute memory address: + if lief.__extended__: + for inst in islice(lief.runtime.disassemble(arc4_init_addr), 4): + print(" ", inst) + + # libsystem.path looks like a valid path but libsystem_c.dylib lives in the + # dyld-shared-cache. Therefore, it's pointless to try to parse the library + # from its filepath as the library does not exist on the disk. + macho_on_disk: lief.MachO.Binary | None = None + with lief.logging.level_scope(lief.logging.Level.Off): + macho_on_disk = libsystem.parse_from_path() + + if macho_on_disk is None: + print(f"As expected, {libsystem.path} is not present in the filesystem") + + # But we can parse it from memory: + if macho_memory := libsystem.parse_from_memory(): + print(f"in-memory imagebase: {macho_memory.imagebase:#010x}") + # List 'exported' symbols + for sym in macho_memory.exported_symbols: + print(f"{sym.name:10}: {sym.value:#010x}") + + # lief-doc: modules-osx-end + + +def memory_example(): + print("Memory") + # lief-doc: memory-start + # The JIT below allocates and executes RWX memory. On macOS this is only + # permitted when SIP is disabled, so we check it before. + if lief.runtime.osx.Host.is_sip_enabled: + print("SIP is enabled: skipping the JIT memory example", file=sys.stderr) + return + + # Note the `JIT` flag here that is used to switch the allocated chunk into + # R-X once the shellcode is committed. + chunk = lief.runtime.Memory.mmap( + lief.runtime.Process.page_size, + lief.runtime.Memory.ANONYMOUS + | lief.runtime.Memory.PRIVATE + | lief.runtime.Memory.JIT, + lief.runtime.Memory.READ | lief.runtime.Memory.WRITE, + ) + + # The message printed by the shellcode. It must stay alive while the JITed + # function runs, so we keep a reference for the whole function. + MSG = b"Hello World\n" + msg = ctypes.create_string_buffer(MSG) + + # libSystem re-exports the libc symbols (write, ...) + libsystem = lief.runtime.osx.dlopen("libSystem.B.dylib") + + # The assembler resolves the symbols referenced by the shellcode through + # this config, mirroring the C++ ``AssemblerConfig::resolve_symbol`` override. + class Config(lief.assembly.AssemblerConfig): + def resolve_symbol(self, name: str) -> int | None: + if libsystem is None: + print("Failed to dlopen libSystem.B.dylib", file=sys.stderr) + return None + + # Resolve the symbols that are used by the shellcode + if name == "write": + return lief.to_int(libsystem.dlsym("write")) + if name == "var_msg": + return ctypes.addressof(msg) + if name == "var_msg_len": + return len(MSG) + return None + + config = Config() + + # Shellcode dynamically compiled and whose referenced symbols are resolved + # at runtime by the provided config + lief.runtime.assemble( + chunk.addr, + r""" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x8, =write // write(2) libc wrapper + ldr x1, =var_msg // buffer + ldr w2, =var_msg_len // length + + // write(STDOUT_FILENO, msg, len) + mov x0, 1 + blr x8 + + mov x0, xzr + ldp x29, x30, [sp], 16 + ret + """, + config, + ) + + # Flush the instruction cache + chunk.cache_flush() + + # Change the permission to R-X and invoke the JITed function + chunk.make_rx() + + void_void_func = ctypes.CFUNCTYPE(None) # void(*)() + hello_jit = void_void_func(chunk.addr) + + # This call prints the message "Hello World" on the console + hello_jit() + + # Don't miss good practices! + chunk.deallocate() + # lief-doc: memory-end + + +def main() -> int: + if not lief.runtime.enabled: + print("Error: LIEF's runtime is not enabled", file=sys.stderr) + return 0 + + host_info() + process_info() + modules_info() + memory_example() + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/runtime_windows.py b/vendor/lief/api/python/examples/runtime_windows.py new file mode 100755 index 0000000..f1926e1 --- /dev/null +++ b/vendor/lief/api/python/examples/runtime_windows.py @@ -0,0 +1,249 @@ +#!/usr/bin/env python3 +import ctypes +import sys +from itertools import islice + +import lief + + +def host_info(): + print("Host") + # lief-doc: host-start + print(f" Hostname: {lief.runtime.Host.name}") + print(f" Home: {lief.runtime.Host.home_dir}") + print(f" Cache: {lief.runtime.Host.cache_dir}") + print(f" Temp: {lief.runtime.Host.tmp_dir}") + print(f" Config: {lief.runtime.Host.config_dir}") + # lief-doc: host-end + + # lief-doc: host-windows-start + print(f" Version: {lief.runtime.windows.Host.version}") + # lief-doc: host-windows-end + print() + + +def process_info(): + print("Process") + # lief-doc: process-start + print(f" PID: {lief.runtime.Process.pid}") + print(f" TID: {lief.runtime.Process.tid}") + print(f" Page size: {lief.runtime.Process.page_size:#06x}") + print(f" Arch: {lief.runtime.Process.arch}") + print(f" Platform: {lief.runtime.Process.platform}") + if (userdomain := lief.runtime.Process.get_env("USERDOMAIN")) is not None: + print(f" USERDOMAIN:{userdomain}") + # lief-doc: process-end + + # lief-doc: process-windows-start + if (peb := lief.runtime.windows.Process.peb) is not None: + print(f" PEB.BeingDebugged: {peb.being_debugged}") + print(f" PEB.Ldr: {peb.ldr:#06x}") + print(f" PEB.ProcessParameters: {peb.process_parameters:#06x}") + print(f" PEB.AtlThunkSListPtr: {peb.atl_thunk_slist_ptr:#06x}") + print(f" PEB.AtlThunkSListPtr32: {peb.atl_thunk_slist_ptr32:#06x}") + print(f" PEB.PostProcessInitRoutine: {peb.post_process_init_routine:#06x}") + print(f" PEB.SessionId: {peb.session_id:#06x}") + # lief-doc: process-windows-end + + # lief-doc: peb-modules-start + if (peb := lief.runtime.windows.Process.peb) is not None: + modules = list(peb.entries) + for i, entry in enumerate(modules[:3]): + print( + f" module[{i}]: {entry.base_dll_name} " + f"(base={entry.dll_base:#06x}, size={entry.size_of_image:#06x})" + ) + print(f" -> {len(modules)} modules in the load order list") + if modules: + print(f" last module: {modules[-1].base_dll_name}") + # lief-doc: peb-modules-end + + # lief-doc: peb-module-details-start + if (peb := lief.runtime.windows.Process.peb) is not None: + first = next(iter(peb.entries), None) + if first is not None: + print(f" {first.base_dll_name} extended LDR_DATA_TABLE_ENTRY fields:") + # Always available across the supported Windows versions: + print(f" Flags: {first.flags:#06x}") + print(f" ObsoleteLoadCount: {first.obsolete_load_count}") + print(f" TlsIndex: {first.tls_index:#06x}") + print(f" TimeDateStamp: {first.time_date_stamp:#06x}") + # Attributes that are available only from certain version: + if (v := first.ddag_node) is not None: # Windows 8+ + print(f" DdagNode: {v:#06x}") + if (v := first.original_base) is not None: # Windows 8+ + print(f" OriginalBase: {v:#06x}") + if (v := first.load_reason) is not None: # Windows 8+ + print(f" LoadReason: {v}") + if (v := first.signing_level) is not None: # Windows 10+ + print(f" SigningLevel: {v}") + if (v := first.check_sum) is not None: # Windows 10+ + print(f" CheckSum: {v:#06x}") + if (v := first.hot_patch_state) is not None: # Windows 11+ + print(f" HotPatchState: {v}") + # lief-doc: peb-module-details-end + + +def modules_info(): + print("Module API") + ntdll: lief.runtime.windows.Module | None = None + # lief-doc: modules-start + for mod in lief.runtime.modules(): + print(mod) + # Look for ntdll + if mod.name.endswith("ntdll.dll"): + print( + f"ntdll.dll found: {mod.path} ([{mod.imagebase:#010x}, {mod.end:#010x}])" + ) + assert isinstance(mod, lief.runtime.windows.Module) + ntdll = mod + # lief-doc: modules-end + + if ntdll is None: + return + + # lief-doc: modules-windows-start + print(f"ntdll path: {ntdll.path}") + if nt_query := ntdll.dlsym("NtQueryInformationProcess"): + # lief.to_int converts an opaque pointer (void*) into a regular Python int + nt_query_addr = lief.to_int(nt_query) + print(f"{ntdll.name}!NtQueryInformationProcess: {nt_query_addr:#010x}") + + # This parses the PE from its path on the disk + if pe_on_disk := ntdll.parse_from_path(): + print(f"on-disk imagebase: {pe_on_disk.optional_header.imagebase:#010x}") + if sym := pe_on_disk.get_symbol("NtQueryInformationProcess"): + print(f"NtQueryInformationProcess: {sym.value:#010x}") + + # This parses the PE directly from memory + if pe_memory := ntdll.parse_from_memory(): + imagebase = pe_memory.optional_header.imagebase + print(f"in-memory imagebase: {imagebase:#010x}") + if sym := pe_memory.get_symbol("RtlFreeHeap"): + print(f"RtlFreeHeap: {sym.value:#010x}") + + # With LIEF extended, we can disassemble the function directly from + # its absolute memory address: + if lief.__extended__: + for inst in islice(lief.runtime.disassemble(imagebase + sym.value), 4): + print(" ", inst) + # lief-doc: modules-windows-end + + +def memory_example(): + print("Memory") + # lief-doc: memory-start + chunk = lief.runtime.Memory.mmap( + lief.runtime.Process.page_size, + lief.runtime.Memory.ANONYMOUS | lief.runtime.Memory.PRIVATE, + lief.runtime.Memory.READ | lief.runtime.Memory.WRITE | lief.runtime.Memory.EXEC, + ) + + # The message printed by the shellcode. It must stay alive while the JITed + # function runs, so we keep a reference for the whole function. + MSG = b"Hello World\n" + msg = ctypes.create_string_buffer(MSG) + + # The assembler resolves the symbols referenced by the shellcode through + # this config, mirroring the C++ ``AssemblerConfig::resolve_symbol`` override. + class Config(lief.assembly.AssemblerConfig): + def resolve_symbol(self, name: str) -> int | None: + kernel32 = lief.runtime.windows.dlopen("kernel32.dll") + if kernel32 is None: + print("Failed to dlopen kernel32.dll", file=sys.stderr) + return None + + # Resolve the symbols that are used by the shellcode + if name == "GetStdHandle": + return lief.to_int(kernel32.dlsym("GetStdHandle")) + if name == "WriteFile": + return lief.to_int(kernel32.dlsym("WriteFile")) + if name == "var_msg": + return ctypes.addressof(msg) + if name == "var_msg_len": + return len(MSG) + return None + + config = Config() + + # Shellcode dynamically compiled and whose referenced symbols are resolved + # at runtime by the provided config + lief.runtime.assemble( + chunk.addr, + r""" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -64]! + mov x29, sp + stp x19, x20, [sp, 16] + stp x21, x22, [sp, 32] + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x19, =GetStdHandle + ldr x20, =WriteFile + ldr x21, =var_msg + ldr w22, =var_msg_len + + // Call GetStdHandle(STD_OUTPUT_HANDLE) + // STD_OUTPUT_HANDLE = -11 + // GetStdHandle is stored in x19 + mov w0, -11 + blr x19 + + // Call ---> bool WriteFile( + // HANDLE hConsoleOutput, // x0: from GetStdHandle (already set) + // const VOID *lpBuffer, // x1: pointer to string + // DWORD nNumberOfCharsToWrite, // w2: length of string + // LPDWORD lpNumberOfCharsWritten,// x3: pointer to written count + // LPVOID lpReserved // x4: NULL + // ); + mov x1, x21 + mov w2, w22 + add x3, sp, 48 + mov x4, xzr + blr x20 + + mov x0, xzr + ldp x21, x22, [sp, 32] + ldp x19, x20, [sp, 16] + ldp x29, x30, [sp], 64 + ret + """, + config, + ) + + # Flush the instruction cache + chunk.cache_flush() + + # Change the permission to R-X and invoke the JITed function + chunk.make_rx() + + void_void_func = ctypes.CFUNCTYPE(None) # void(*)() + hello_jit = void_void_func(chunk.addr) + + # This call prints the message "Hello World" on the console + hello_jit() + + # Don't miss good practices! + chunk.deallocate() + # lief-doc: memory-end + + +def main() -> int: + if not lief.runtime.enabled: + print("Error: LIEF's runtime is not enabled", file=sys.stderr) + return 0 + + host_info() + process_info() + modules_info() + memory_example() + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/ty.toml b/vendor/lief/api/python/examples/ty.toml new file mode 100644 index 0000000..04cf983 --- /dev/null +++ b/vendor/lief/api/python/examples/ty.toml @@ -0,0 +1,7 @@ +[environment] +extra-paths = [".."] + +[rules] +unused-type-ignore-comment = "ignore" +unused-ignore-comment = "ignore" +unresolved-attribute = "ignore" diff --git a/vendor/lief/api/python/examples/vdex_json.py b/vendor/lief/api/python/examples/vdex_json.py new file mode 100755 index 0000000..b915b44 --- /dev/null +++ b/vendor/lief/api/python/examples/vdex_json.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python +"""Dump a VDEX file (Android verified DEX container) as JSON. + +Parses a ``.vdex`` file and writes a pretty-printed JSON dump of its +structure using ``lief.to_json``. + +Example: + + $ python vdex_json.py primary.vdex +""" + +import argparse +import json +import sys + +import lief + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument("file", help="Path to a VDEX file") + args = parser.parse_args() + + if not lief.is_vdex(args.file): + print(f"'{args.file}' is not a VDEX file", file=sys.stderr) + return 1 + + vdexfile = lief.VDEX.parse(args.file) + if vdexfile is None: + print(f"Error: failed to parse '{args.file}'", file=sys.stderr) + return 1 + + json_data = json.loads(lief.to_json(vdexfile)) + print(json.dumps(json_data, sort_keys=True, indent=4)) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/examples/vdex_reader.py b/vendor/lief/api/python/examples/vdex_reader.py new file mode 100755 index 0000000..33dda16 --- /dev/null +++ b/vendor/lief/api/python/examples/vdex_reader.py @@ -0,0 +1,145 @@ +#!/usr/bin/env python +"""Pretty-print the structure of an Android VDEX file. + +Parses a ``.vdex`` container with ``lief.VDEX.parse`` and renders the +header and (optionally) the embedded DEX files. + +Example: + + $ python vdex_reader.py -a primary.vdex +""" + +import argparse +import sys +import traceback + +import lief +from lief import VDEX + +EXIT_STATUS = 0 + + +class exceptions_handler: + func = None + + def __init__(self, exceptions, on_except_callback=None): + self.exceptions = exceptions + self.on_except_callback = on_except_callback + + def __call__(self, *args, **kwargs): + if self.func is None: + self.func = args[0] + return self + try: + return self.func(*args, **kwargs) + except self.exceptions as e: + global EXIT_STATUS + print(f"{self.func.__name__} raised: {e}") + EXIT_STATUS = 1 + if self.on_except_callback is not None: + self.on_except_callback(e) + else: + print("-" * 60) + print(f"Exception in {self.func.__name__}: {e}") + traceback.print_exc() + print("-" * 60) + + +@exceptions_handler(Exception) +def print_information(vdexfile): + print("== Information ==") + print(f"VDEX File version: {vdexfile.header.version}") + print() + + +@exceptions_handler(Exception) +def print_header(vdexfile): + print("== Header ==") + print(vdexfile.header) + + +@exceptions_handler(Exception) +def print_dex_files(vdexfile): + print("== Embedded DEX files ==") + for dexfile in vdexfile.dex_files: + print(dexfile) + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__.splitlines()[0]) + parser.add_argument( + "-a", "--all", action="store_true", dest="show_all", help="Show all information" + ) + parser.add_argument( + "-H", "--header", action="store_true", dest="show_header", help="Display header" + ) + parser.add_argument( + "-d", + "--dex", + action="store_true", + dest="show_dex", + help="Display embedded DEX files", + ) + parser.add_argument("file", metavar="", help="Target VDEX file") + + logger_group = parser.add_argument_group("Logger") + verbosity = logger_group.add_mutually_exclusive_group() + verbosity.add_argument( + "--debug", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Debug, + ) + verbosity.add_argument( + "--trace", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Trace, + ) + verbosity.add_argument( + "--info", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Info, + ) + verbosity.add_argument( + "--warn", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Warn, + ) + verbosity.add_argument( + "--err", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Err, + ) + verbosity.add_argument( + "--critical", + dest="main_verbosity", + action="store_const", + const=lief.logging.Level.Critical, + ) + parser.set_defaults(main_verbosity=lief.logging.Level.Warn) + + args = parser.parse_args() + lief.logging.set_level(args.main_verbosity) + + vdexfile = VDEX.parse(args.file) + if vdexfile is None: + print(f"Error: failed to parse '{args.file}' as VDEX", file=sys.stderr) + return 1 + + print_information(vdexfile) + + if args.show_header or args.show_all: + print_header(vdexfile) + + if args.show_dex or args.show_all: + print_dex_files(vdexfile) + + return EXIT_STATUS + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/vendor/lief/api/python/lief/ART.pyi b/vendor/lief/api/python/lief/ART.pyi new file mode 100644 index 0000000..b7806cb --- /dev/null +++ b/vendor/lief/api/python/lief/ART.pyi @@ -0,0 +1,102 @@ +from collections.abc import Sequence +import enum +import io +import os +from typing import Optional, Union, overload + +import lief +import lief.Android + + +class STORAGE_MODES(enum.Enum): + UNCOMPRESSED = 0 + + LZ4 = 1 + + LZ4HC = 2 + +@overload +def parse(filename: str) -> Optional[File]: ... + +@overload +def parse(raw: Sequence[int], name: str = '') -> Optional[File]: ... + +@overload +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], name: str = '') -> Optional[File]: ... + +class File(lief.Object): + @property + def header(self) -> Header: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + @property + def magic(self) -> list[int]: ... + + @property + def version(self) -> int: ... + + @property + def image_begin(self) -> int: ... + + @property + def image_size(self) -> int: ... + + @property + def oat_checksum(self) -> int: ... + + @property + def oat_file_begin(self) -> int: ... + + @property + def oat_file_end(self) -> int: ... + + @property + def oat_data_end(self) -> int: ... + + @property + def patch_delta(self) -> int: ... + + @property + def image_roots(self) -> int: ... + + @property + def pointer_size(self) -> int: ... + + @property + def compile_pic(self) -> bool: ... + + @property + def nb_sections(self) -> int: ... + + @property + def nb_methods(self) -> int: ... + + @property + def boot_image_begin(self) -> int: ... + + @property + def boot_image_size(self) -> int: ... + + @property + def boot_oat_begin(self) -> int: ... + + @property + def boot_oat_size(self) -> int: ... + + @property + def storage_mode(self) -> STORAGE_MODES: ... + + @property + def data_size(self) -> int: ... + + def __str__(self) -> str: ... + +@overload +def version(file: str) -> int: ... + +@overload +def version(raw: Sequence[int]) -> int: ... + +def android_version(art_version: int) -> lief.Android.ANDROID_VERSIONS: ... diff --git a/vendor/lief/api/python/lief/Android.pyi b/vendor/lief/api/python/lief/Android.pyi new file mode 100644 index 0000000..cbf5d43 --- /dev/null +++ b/vendor/lief/api/python/lief/Android.pyi @@ -0,0 +1,32 @@ +import enum + + +class ANDROID_VERSIONS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ANDROID_VERSIONS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + VERSION_601 = 1 + + VERSION_700 = 2 + + VERSION_710 = 3 + + VERSION_712 = 4 + + VERSION_800 = 5 + + VERSION_810 = 6 + + VERSION_900 = 7 + +def code_name(version: ANDROID_VERSIONS) -> str: ... + +def version_string(version: ANDROID_VERSIONS) -> str: ... diff --git a/vendor/lief/api/python/lief/COFF.pyi b/vendor/lief/api/python/lief/COFF.pyi new file mode 100644 index 0000000..bbd470c --- /dev/null +++ b/vendor/lief/api/python/lief/COFF.pyi @@ -0,0 +1,714 @@ +from collections.abc import Iterator +import enum +import io +import os +from typing import Final, Optional, Union, overload + +import lief +import lief.PE +import lief.assembly + + +class Header: + class KIND(enum.Enum): + UNKNOWN = 0 + + REGULAR = 1 + + BIGOBJ = 2 + + @property + def kind(self) -> Header.KIND: ... + + machine: lief.PE.Header.MACHINE_TYPES + + nb_sections: int + + pointerto_symbol_table: int + + nb_symbols: int + + timedatestamp: int + + def __str__(self) -> str: ... + + def copy(self) -> Optional[Header]: ... + +class RegularHeader(Header): + sizeof_optionalheader: int + + characteristics: int + +class BigObjHeader(Header): + version: int + + @property + def uuid(self) -> memoryview: ... + + sizeof_data: int + + flags: int + + metadata_size: int + + metadata_offset: int + +class Binary: + class it_section: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_section: ... + + def __next__(self) -> Section: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_strings_table: + def __getitem__(self, arg: int, /) -> String: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_strings_table: ... + + def __next__(self) -> String: ... + + class it_functions: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_functions: ... + + def __next__(self) -> Symbol: ... + + @property + def header(self) -> Header: ... + + @property + def sections(self) -> Binary.it_section: ... + + def get_section(self, name: str) -> Section | None: ... + + @property + def relocations(self) -> Binary.it_relocations: ... + + @property + def symbols(self) -> lief.PE.Binary.it_symbols: ... + + @property + def functions(self) -> Binary.it_functions: ... + + @property + def string_table(self) -> lief.PE.Binary.it_strings_table: ... + + def find_string(self, offset: int) -> String | None: ... + + def find_function(self, name: str) -> Symbol | None: ... + + def find_demangled_function(self, name: str) -> Symbol | None: ... + + @overload + def disassemble(self, function: Symbol) -> Iterator[Optional[lief.assembly.Instruction]]: ... + + @overload + def disassemble(self, function_name: str) -> Iterator[Optional[lief.assembly.Instruction]]: ... + + def disassemble_from_bytes(self, buffer: bytes, address: int = 0) -> Iterator[Optional[lief.assembly.Instruction]]: ... + + def __str__(self) -> str: ... + +class ParserConfig: + def __init__(self) -> None: ... + + default_conf: Final[ParserConfig] = ... + + all: Final[ParserConfig] = ... + +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], config: ParserConfig = ...) -> Optional[Binary]: ... + +class String: + string: str + + offset: int + + def __str__(self) -> str: ... + +class Symbol(lief.Symbol): + class it_auxiliary_symbols_t: + def __getitem__(self, arg: int, /) -> AuxiliarySymbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Symbol.it_auxiliary_symbols_t: ... + + def __next__(self) -> AuxiliarySymbol: ... + + class STORAGE_CLASS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.STORAGE_CLASS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + END_OF_FUNCTION = -1 + + NONE = 0 + + AUTOMATIC = 1 + + EXTERNAL = 2 + + STATIC = 3 + + REGISTER = 4 + + EXTERNAL_DEF = 5 + + LABEL = 6 + + UNDEFINED_LABEL = 7 + + MEMBER_OF_STRUCT = 8 + + ARGUMENT = 9 + + STRUCT_TAG = 10 + + MEMBER_OF_UNION = 11 + + UNION_TAG = 12 + + TYPE_DEFINITION = 13 + + UNDEFINED_STATIC = 14 + + ENUM_TAG = 15 + + MEMBER_OF_ENUM = 16 + + REGISTER_PARAM = 17 + + BIT_FIELD = 18 + + BLOCK = 100 + + FUNCTION = 101 + + END_OF_STRUCT = 102 + + FILE = 103 + + SECTION = 104 + + WEAK_EXTERNAL = 105 + + CLR_TOKEN = 107 + + class BASE_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.BASE_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NULL = 0 + + VOID = 1 + + CHAR = 2 + + SHORT = 3 + + INT = 4 + + LONG = 5 + + FLOAT = 6 + + DOUBLE = 7 + + STRUCT = 8 + + UNION = 9 + + ENUM = 10 + + MOE = 11 + + BYTE = 12 + + WORD = 13 + + UINT = 14 + + DWORD = 15 + + class COMPLEX_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.COMPLEX_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NULL = 0 + + POINTER = 1 + + FUNCTION = 2 + + ARRAY = 3 + + type: int + + @property + def base_type(self) -> Symbol.BASE_TYPE: ... + + @property + def complex_type(self) -> Symbol.COMPLEX_TYPE: ... + + @property + def storage_class(self) -> Symbol.STORAGE_CLASS: ... + + section_idx: int + + @property + def section(self) -> Section | None: ... + + @property + def is_external(self) -> bool: ... + + @property + def is_absolute(self) -> bool: ... + + @property + def is_weak_external(self) -> bool: ... + + @property + def is_undefined(self) -> bool: ... + + @property + def is_function_line_info(self) -> bool: ... + + @property + def is_file_record(self) -> bool: ... + + @property + def is_function(self) -> bool: ... + + @property + def auxiliary_symbols(self) -> Symbol.it_auxiliary_symbols_t: ... + + @property + def coff_name(self) -> String | None: ... + + @property + def demangled_name(self) -> str: ... + + def __str__(self) -> str: ... + +class Section(lief.Section): + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Section.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Section.it_symbols: ... + + def __next__(self) -> Symbol: ... + + class ComdatInfo: + @property + def symbol(self) -> Symbol: ... + + @property + def kind(self) -> AuxiliarySectionDefinition.COMDAT_SELECTION: ... + + virtual_size: int + + sizeof_raw_data: int + + pointerto_raw_data: int + + pointerto_relocation: int + + pointerto_line_numbers: int + + numberof_relocations: int + + numberof_line_numbers: int + + characteristics: int + + @property + def characteristics_lists(self) -> list[lief.PE.Section.CHARACTERISTICS]: ... + + def has_characteristic(self, characteristic: lief.PE.Section.CHARACTERISTICS) -> bool: ... + + @property + def is_discardable(self) -> bool: ... + + @property + def relocations(self) -> Section.it_relocations: ... + + @property + def symbols(self) -> Section.it_symbols: ... + + @property + def has_extended_relocations(self) -> bool: ... + + @property + def comdat_info(self) -> Section.ComdatInfo | None: ... + + @property + def coff_string(self) -> String | None: ... + + def __str__(self) -> str: ... + +class Relocation(lief.Relocation): + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Relocation.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 4294967295 + + AMD64_ABSOLUTE = 262144 + + AMD64_ADDR32 = 262146 + + AMD64_ADDR32NB = 262147 + + AMD64_ADDR64 = 262145 + + AMD64_PAIR = 262159 + + AMD64_REL32 = 262148 + + AMD64_REL32_1 = 262149 + + AMD64_REL32_2 = 262150 + + AMD64_REL32_3 = 262151 + + AMD64_REL32_4 = 262152 + + AMD64_REL32_5 = 262153 + + AMD64_SECREL = 262155 + + AMD64_SECREL7 = 262156 + + AMD64_SECTION = 262154 + + AMD64_SREL32 = 262158 + + AMD64_SSPAN32 = 262160 + + AMD64_TOKEN = 262157 + + ARM64_ABSOLUTE = 1048576 + + ARM64_ADDR32 = 1048577 + + ARM64_ADDR32NB = 1048578 + + ARM64_ADDR64 = 1048590 + + ARM64_BRANCH14 = 1048592 + + ARM64_BRANCH19 = 1048591 + + ARM64_BRANCH26 = 1048579 + + ARM64_PAGEBASE_REL21 = 1048580 + + ARM64_PAGEOFFSET_12A = 1048582 + + ARM64_PAGEOFFSET_12L = 1048583 + + ARM64_REL21 = 1048581 + + ARM64_REL32 = 1048593 + + ARM64_SECREL = 1048584 + + ARM64_SECREL_HIGH12A = 1048586 + + ARM64_SECREL_LOW12A = 1048585 + + ARM64_SECREL_LOW12L = 1048587 + + ARM64_SECTION = 1048589 + + ARM64_TOKEN = 1048588 + + ARM_ABSOLUTE = 524288 + + ARM_ADDR32 = 524289 + + ARM_ADDR32NB = 524290 + + ARM_BLX11 = 524297 + + ARM_BLX23T = 524309 + + ARM_BLX24 = 524296 + + ARM_BRANCH11 = 524292 + + ARM_BRANCH20T = 524306 + + ARM_BRANCH24 = 524291 + + ARM_BRANCH24T = 524308 + + ARM_MOV32A = 524304 + + ARM_MOV32T = 524305 + + ARM_PAIR = 524310 + + ARM_REL32 = 524298 + + ARM_SECREL = 524303 + + ARM_SECTION = 524302 + + ARM_TOKEN = 524293 + + I386_ABSOLUTE = 131072 + + I386_DIR16 = 131073 + + I386_DIR32 = 131078 + + I386_DIR32NB = 131079 + + I386_REL16 = 131074 + + I386_REL32 = 131092 + + I386_SECREL = 131083 + + I386_SECREL7 = 131085 + + I386_SECTION = 131082 + + I386_SEG12 = 131081 + + I386_TOKEN = 131084 + + MIPS_ABSOLUTE = 2097152 + + MIPS_GPREL = 2097158 + + MIPS_JMPADDR = 2097155 + + MIPS_JMPADDR16 = 2097168 + + MIPS_LITERAL = 2097159 + + MIPS_PAIR = 2097189 + + MIPS_REFHALF = 2097153 + + MIPS_REFHI = 2097156 + + MIPS_REFLO = 2097157 + + MIPS_REFWORD = 2097154 + + MIPS_REFWORDNB = 2097186 + + MIPS_SECREL = 2097163 + + MIPS_SECRELHI = 2097165 + + MIPS_SECRELLO = 2097164 + + MIPS_SECTION = 2097162 + + @property + def symbol_idx(self) -> int: ... + + @property + def symbol(self) -> Symbol | None: ... + + @property + def type(self) -> Relocation.TYPE: ... + + @property + def section(self) -> Section | None: ... + + def __str__(self) -> str: ... + +class AuxiliarySymbol: + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> AuxiliarySymbol.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + CLR_TOKEN = 1 + + FUNC_DEF = 2 + + BF_AND_EF = 3 + + WEAK_EXTERNAL = 4 + + FILE = 5 + + SEC_DEF = 6 + + @property + def type(self) -> AuxiliarySymbol.TYPE: ... + + @property + def payload(self) -> memoryview: ... + + def __str__(self) -> str: ... + + def copy(self) -> Optional[AuxiliarySymbol]: ... + +class AuxiliaryCLRToken(AuxiliarySymbol): + @property + def aux_type(self) -> int: ... + + @property + def reserved(self) -> int: ... + + @property + def symbol_idx(self) -> int: ... + + @property + def symbol(self) -> Symbol | None: ... + + @property + def rgb_reserved(self) -> memoryview: ... + +class AuxiliaryFunctionDefinition(AuxiliarySymbol): + @property + def tag_index(self) -> int: ... + + @property + def total_size(self) -> int: ... + + @property + def ptr_to_line_number(self) -> int: ... + + @property + def ptr_to_next_func(self) -> int: ... + + @property + def padding(self) -> int: ... + +class AuxiliaryWeakExternal(AuxiliarySymbol): + class CHARACTERISTICS(enum.Enum): + SEARCH_NOLIBRARY = 1 + + SEARCH_LIBRARY = 2 + + SEARCH_ALIAS = 3 + + ANTI_DEPENDENCY = 4 + + @property + def sym_idx(self) -> int: ... + + @property + def characteristics(self) -> AuxiliaryWeakExternal.CHARACTERISTICS: ... + + @property + def padding(self) -> memoryview: ... + +class AuxiliarybfAndefSymbol(AuxiliarySymbol): + pass + +class AuxiliarySectionDefinition(AuxiliarySymbol): + class COMDAT_SELECTION(enum.Enum): + NONE = 0 + + NODUPLICATES = 1 + + ANY = 2 + + SAME_SIZE = 3 + + EXACT_MATCH = 4 + + ASSOCIATIVE = 5 + + LARGEST = 6 + + @property + def length(self) -> int: ... + + @property + def nb_relocs(self) -> int: ... + + @property + def nb_line_numbers(self) -> int: ... + + @property + def checksum(self) -> int: ... + + @property + def section_idx(self) -> int: ... + + @property + def selection(self) -> AuxiliarySectionDefinition.COMDAT_SELECTION: ... + + @property + def reserved(self) -> int: ... + +class AuxiliaryFile(AuxiliarySymbol): + @property + def filename(self) -> str: ... diff --git a/vendor/lief/api/python/lief/DEX.pyi b/vendor/lief/api/python/lief/DEX.pyi new file mode 100644 index 0000000..7421bbd --- /dev/null +++ b/vendor/lief/api/python/lief/DEX.pyi @@ -0,0 +1,518 @@ +from collections.abc import Sequence +import enum +import io +import os +from typing import Optional, Union, overload + +import lief + + +class ACCESS_FLAGS(enum.Enum): + UNKNOWN = 0 + + PUBLIC = 1 + + PRIVATE = 2 + + PROTECTED = 4 + + STATIC = 8 + + FINAL = 16 + + SYNCHRONIZED = 32 + + VOLATILE = 64 + + BRIDGE = 64 + + TRANSIENT = 128 + + VARARGS = 128 + + NATIVE = 256 + + INTERFACE = 512 + + ABSTRACT = 1024 + + STRICT = 2048 + + SYNTHETIC = 4096 + + ANNOTATION = 8192 + + ENUM = 16384 + + CONSTRUCTOR = 65536 + + DECLARED_SYNCHRONIZED = 131072 + +@overload +def parse(filename: str) -> Optional[File]: ... + +@overload +def parse(raw: Sequence[int], name: str = '') -> Optional[File]: ... + +@overload +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], name: str = '') -> Optional[File]: ... + +class File(lief.Object): + class it_classes: + def __getitem__(self, arg: int, /) -> Class: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_classes: ... + + def __next__(self) -> Class: ... + + class it_methods: + def __getitem__(self, arg: int, /) -> Method: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_methods: ... + + def __next__(self) -> Method: ... + + class it_strings: + def __getitem__(self, arg: int, /) -> str: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_strings: ... + + def __next__(self) -> str: ... + + class it_types: + def __getitem__(self, arg: int, /) -> Type: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_types: ... + + def __next__(self) -> Type: ... + + class it_prototypes: + def __getitem__(self, arg: int, /) -> Prototype: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_prototypes: ... + + def __next__(self) -> Prototype: ... + + class it_fields: + def __getitem__(self, arg: int, /) -> Field: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> File.it_fields: ... + + def __next__(self) -> Field: ... + + @property + def version(self) -> int: ... + + @property + def header(self) -> Header: ... + + @property + def classes(self) -> File.it_classes: ... + + def has_class(self, classname: str) -> bool: ... + + @overload + def get_class(self, classname: str) -> Class | None: ... + + @overload + def get_class(self, classname: int) -> Class | None: ... + + @property + def methods(self) -> File.it_methods: ... + + @property + def fields(self) -> File.it_fields: ... + + @property + def strings(self) -> File.it_strings: ... + + @property + def types(self) -> File.it_types: ... + + @property + def prototypes(self) -> File.it_prototypes: ... + + @property + def map(self) -> MapList: ... + + def raw(self, deoptimize: bool = True) -> list[int]: ... + + name: str + + location: str + + @property + def dex2dex_json_info(self) -> str: ... + + def save(self, output: str = '', deoptimize: bool = True) -> str: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + @property + def magic(self) -> list[int]: ... + + @property + def checksum(self) -> int: ... + + @property + def signature(self) -> list[int]: ... + + @property + def file_size(self) -> int: ... + + @property + def header_size(self) -> int: ... + + @property + def endian_tag(self) -> int: ... + + @property + def map_offset(self) -> int: ... + + @property + def strings(self) -> tuple[int, int]: ... + + @property + def link(self) -> tuple[int, int]: ... + + @property + def types(self) -> tuple[int, int]: ... + + @property + def prototypes(self) -> tuple[int, int]: ... + + @property + def fields(self) -> tuple[int, int]: ... + + @property + def methods(self) -> tuple[int, int]: ... + + @property + def classes(self) -> tuple[int, int]: ... + + @property + def data(self) -> tuple[int, int]: ... + + @property + def nb_classes(self) -> int: ... + + @property + def nb_methods(self) -> int: ... + + def __str__(self) -> str: ... + +class Class(lief.Object): + class it_methods: + def __getitem__(self, arg: int, /) -> Method: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Class.it_methods: ... + + def __next__(self) -> Method: ... + + class it_fields: + def __getitem__(self, arg: int, /) -> Field: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Class.it_fields: ... + + def __next__(self) -> Field: ... + + class it_named_methods: + def __getitem__(self, arg: int, /) -> Method: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Class.it_named_methods: ... + + def __next__(self) -> Method: ... + + class it_named_fields: + def __getitem__(self, arg: int, /) -> Field: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Class.it_named_fields: ... + + def __next__(self) -> Field: ... + + @property + def fullname(self) -> str: ... + + @property + def pretty_name(self) -> str: ... + + @property + def name(self) -> str: ... + + @property + def source_filename(self) -> str: ... + + @property + def package_name(self) -> str: ... + + @property + def has_parent(self) -> bool: ... + + @property + def parent(self) -> Class | None: ... + + @property + def methods(self) -> Class.it_methods: ... + + def get_method(self, name: str) -> Class.it_named_methods: ... + + @property + def fields(self) -> Class.it_fields: ... + + def get_field(self, name: str) -> Class.it_named_fields: ... + + @property + def access_flags(self) -> list[ACCESS_FLAGS]: ... + + @property + def dex2dex_info(self) -> dict[Method, dict[int, int]]: ... + + @property + def index(self) -> int: ... + + def has(self, flag: ACCESS_FLAGS) -> bool: ... + + def __str__(self) -> str: ... + +class Method(lief.Object): + @property + def name(self) -> str: ... + + @property + def index(self) -> int: ... + + @property + def has_class(self) -> bool: ... + + @property + def cls(self) -> Class | None: ... + + @property + def code_offset(self) -> int: ... + + @property + def bytecode(self) -> list[int]: ... + + @property + def is_virtual(self) -> bool: ... + + @property + def prototype(self) -> Prototype | None: ... + + @property + def access_flags(self) -> list[ACCESS_FLAGS]: ... + + def has(self, flag: ACCESS_FLAGS) -> bool: ... + + def insert_dex2dex_info(self, pc: int, index: int) -> None: ... + + @property + def code_info(self) -> CodeInfo: ... + + def __str__(self) -> str: ... + +class Field(lief.Object): + @property + def name(self) -> str: ... + + @property + def index(self) -> int: ... + + @property + def has_class(self) -> bool: ... + + @property + def cls(self) -> Class | None: ... + + @property + def is_static(self) -> bool: ... + + @property + def type(self) -> Type | None: ... + + @property + def access_flags(self) -> list[ACCESS_FLAGS]: ... + + def has(self, flag: ACCESS_FLAGS) -> bool: ... + + def __str__(self) -> str: ... + +class Prototype(lief.Object): + class it_params: + def __getitem__(self, arg: int, /) -> Type: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Prototype.it_params: ... + + def __next__(self) -> Type: ... + + @property + def return_type(self) -> Type | None: ... + + @property + def parameters_type(self) -> Prototype.it_params: ... + + def __str__(self) -> str: ... + +class Type(lief.Object): + class TYPES(enum.Enum): + UNKNOWN = 0 + + ARRAY = 3 + + PRIMITIVE = 1 + + CLASS = 2 + + class PRIMITIVES(enum.Enum): + VOID_T = 1 + + BOOLEAN = 2 + + BYTE = 3 + + SHORT = 4 + + CHAR = 5 + + INT = 6 + + LONG = 7 + + FLOAT = 8 + + DOUBLE = 9 + + @property + def type(self) -> Type.TYPES: ... + + @property + def value(self) -> object: ... + + @property + def dim(self) -> int: ... + + @property + def underlying_array_type(self) -> Type: ... + + @staticmethod + def pretty_name(primitive: Type.PRIMITIVES) -> str: ... + + def __str__(self) -> str: ... + +class MapList(lief.Object): + class it_items_t: + def __getitem__(self, arg: int, /) -> MapItem: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> MapList.it_items_t: ... + + def __next__(self) -> MapItem: ... + + @property + def items(self) -> MapList.it_items_t: ... + + def has(self, type: MapItem.TYPES) -> bool: ... + + def get(self, type: MapItem.TYPES) -> MapItem: ... + + def __getitem__(self, arg: MapItem.TYPES, /) -> MapItem: ... + + def __str__(self) -> str: ... + +class MapItem(lief.Object): + class TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> MapItem.TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + HEADER = 0 + + STRING_ID = 1 + + TYPE_ID = 2 + + PROTO_ID = 3 + + FIELD_ID = 4 + + METHOD_ID = 5 + + CLASS_DEF = 6 + + CALL_SITE_ID = 7 + + METHOD_HANDLE = 8 + + MAP_LIST = 4096 + + TYPE_LIST = 4097 + + ANNOTATION_SET_REF_LIST = 4098 + + ANNOTATION_SET = 4099 + + CLASS_DATA = 8192 + + CODE = 8193 + + STRING_DATA = 8194 + + DEBUG_INFO = 8195 + + ANNOTATION = 8196 + + ENCODED_ARRAY = 8197 + + ANNOTATIONS_DIRECTORY = 8198 + + @property + def type(self) -> MapItem.TYPES: ... + + @property + def offset(self) -> int: ... + + @property + def size(self) -> int: ... + + def __str__(self) -> str: ... + +class CodeInfo(lief.Object): + @property + def nb_registers(self) -> int: ... + + def __str__(self) -> str: ... + +@overload +def version(file: str) -> int: ... + +@overload +def version(raw: Sequence[int]) -> int: ... diff --git a/vendor/lief/api/python/lief/ELF.pyi b/vendor/lief/api/python/lief/ELF.pyi new file mode 100644 index 0000000..fde4605 --- /dev/null +++ b/vendor/lief/api/python/lief/ELF.pyi @@ -0,0 +1,5964 @@ +from collections.abc import Iterable, Iterator, Mapping, Sequence +import enum +import io +import os +from typing import Final, Optional, Union, overload + +import lief + + +def check_layout(binary: Binary) -> tuple[bool, str]: ... + +class ARCH(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ARCH: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + M32 = 1 + + SPARC = 2 + + I386 = 3 + + M68K = 4 + + M88K = 5 + + IAMCU = 6 + + I860 = 7 + + MIPS = 8 + + S370 = 9 + + MIPS_RS3_LE = 10 + + PARISC = 15 + + VPP500 = 17 + + SPARC32PLUS = 18 + + I60 = 19 + + PPC = 20 + + PPC64 = 21 + + S390 = 22 + + SPU = 23 + + V800 = 36 + + FR20 = 37 + + RH32 = 38 + + RCE = 39 + + ARM = 40 + + ALPHA = 41 + + SH = 42 + + SPARCV9 = 43 + + TRICORE = 44 + + ARC = 45 + + H8_300 = 46 + + H8_300H = 47 + + H8S = 48 + + H8_500 = 49 + + IA_64 = 50 + + MIPS_X = 51 + + COLDFIRE = 52 + + M68HC12 = 53 + + MMA = 54 + + PCP = 55 + + NCPU = 56 + + NDR1 = 57 + + STARCORE = 58 + + ME16 = 59 + + ST100 = 60 + + TINYJ = 61 + + X86_64 = 62 + + PDSP = 63 + + PDP10 = 64 + + PDP11 = 65 + + FX66 = 66 + + ST9PLUS = 67 + + ST7 = 68 + + M68HC16 = 69 + + M68HC11 = 70 + + M68HC08 = 71 + + M68HC05 = 72 + + SVX = 73 + + ST19 = 74 + + VAX = 75 + + CRIS = 76 + + JAVELIN = 77 + + FIREPATH = 78 + + ZSP = 79 + + MMIX = 80 + + HUANY = 81 + + PRISM = 82 + + AVR = 83 + + FR30 = 84 + + D10V = 85 + + D30V = 86 + + V850 = 87 + + M32R = 88 + + MN10300 = 89 + + MN10200 = 90 + + PJ = 91 + + OPENRISC = 92 + + ARC_COMPACT = 93 + + XTENSA = 94 + + VIDEOCORE = 95 + + TMM_GPP = 96 + + NS32K = 97 + + TPC = 98 + + SNP1K = 99 + + ST200 = 100 + + IP2K = 101 + + MAX = 102 + + CR = 103 + + F2MC16 = 104 + + MSP430 = 105 + + BLACKFIN = 106 + + SE_C33 = 107 + + SEP = 108 + + ARCA = 109 + + UNICORE = 110 + + EXCESS = 111 + + DXP = 112 + + ALTERA_NIOS2 = 113 + + CRX = 114 + + XGATE = 115 + + C166 = 116 + + M16C = 117 + + DSPIC30F = 118 + + CE = 119 + + M32C = 120 + + TSK3000 = 131 + + RS08 = 132 + + SHARC = 133 + + ECOG2 = 134 + + SCORE7 = 135 + + DSP24 = 136 + + VIDEOCORE3 = 137 + + LATTICEMICO32 = 138 + + SE_C17 = 139 + + TI_C6000 = 140 + + TI_C2000 = 141 + + TI_C5500 = 142 + + MMDSP_PLUS = 160 + + CYPRESS_M8C = 161 + + R32C = 162 + + TRIMEDIA = 163 + + HEXAGON = 164 + + M8051 = 165 + + STXP7X = 166 + + NDS32 = 167 + + ECOG1X = 168 + + MAXQ30 = 169 + + XIMO16 = 170 + + MANIK = 171 + + CRAYNV2 = 172 + + RX = 173 + + METAG = 174 + + MCST_ELBRUS = 175 + + ECOG16 = 176 + + CR16 = 177 + + ETPU = 178 + + SLE9X = 179 + + L10M = 180 + + K10M = 181 + + AARCH64 = 183 + + AVR32 = 185 + + STM8 = 186 + + TILE64 = 187 + + TILEPRO = 188 + + CUDA = 190 + + TILEGX = 191 + + CLOUDSHIELD = 192 + + COREA_1ST = 193 + + COREA_2ND = 194 + + ARC_COMPACT2 = 195 + + OPEN8 = 196 + + RL78 = 197 + + VIDEOCORE5 = 198 + + M78KOR = 199 + + M56800EX = 200 + + BA1 = 201 + + BA2 = 202 + + XCORE = 203 + + MCHP_PIC = 204 + + INTEL205 = 205 + + INTEL206 = 206 + + INTEL207 = 207 + + INTEL208 = 208 + + INTEL209 = 209 + + KM32 = 210 + + KMX32 = 211 + + KMX16 = 212 + + KMX8 = 213 + + KVARC = 214 + + CDP = 215 + + COGE = 216 + + COOL = 217 + + NORC = 218 + + CSR_KALIMBA = 219 + + AMDGPU = 224 + + RISCV = 243 + + BPF = 247 + + CSKY = 252 + + LOONGARCH = 258 + + ALPHA_ALT = 36902 + +class ParserConfig: + def __init__(self) -> None: ... + + class DYNSYM_COUNT(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ParserConfig.DYNSYM_COUNT: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + AUTO = 0 + + SECTION = 1 + + HASH = 2 + + RELOCATIONS = 3 + + parse_relocations: bool + + parse_dyn_symbols: bool + + parse_symtab_symbols: bool + + parse_symbol_versions: bool + + parse_notes: bool + + parse_overlay: bool + + count_mtd: ParserConfig.DYNSYM_COUNT + + page_size: int + + all: Final[ParserConfig] = ... + +@overload +def parse_from_memory(address: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +@overload +def parse_from_memory(address: int, size: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +def parse_from_dump(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], addr: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], config: ParserConfig = ...) -> Optional[Binary]: ... + +class SymbolVersion(lief.Object): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: int, /) -> None: ... + + local: Final[SymbolVersion] = ... + + global_: Final[SymbolVersion] = ... + + value: int + + @property + def has_auxiliary_version(self) -> bool: ... + + @property + def symbol_version_auxiliary(self) -> SymbolVersionAux | None: ... + + @symbol_version_auxiliary.setter + def symbol_version_auxiliary(self, arg: SymbolVersionAuxRequirement, /) -> None: ... + + def drop_version(self, value: int) -> None: ... + + def as_global(self) -> None: ... + + def as_local(self) -> None: ... + + def __str__(self) -> str: ... + +class Binary(lief.Binary): + class it_notes: + def __getitem__(self, arg: int, /) -> Note: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_notes: ... + + def __next__(self) -> Note: ... + + class it_symbols_version_requirement: + def __getitem__(self, arg: int, /) -> SymbolVersionRequirement: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols_version_requirement: ... + + def __next__(self) -> SymbolVersionRequirement: ... + + class it_symbols_version_definition: + def __getitem__(self, arg: int, /) -> SymbolVersionDefinition: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols_version_definition: ... + + def __next__(self) -> SymbolVersionDefinition: ... + + class it_segments: + def __getitem__(self, arg: int, /) -> Segment: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_segments: ... + + def __next__(self) -> Segment: ... + + class it_sections: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_sections: ... + + def __next__(self) -> Section: ... + + class it_dynamic_entries: + def __getitem__(self, arg: int, /) -> DynamicEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_dynamic_entries: ... + + def __next__(self) -> DynamicEntry: ... + + class it_symbols_version: + def __getitem__(self, arg: int, /) -> SymbolVersion: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols_version: ... + + def __next__(self) -> SymbolVersion: ... + + class it_filter_relocation: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_filter_relocation: ... + + def __next__(self) -> Relocation: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class it_dyn_symtab_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_dyn_symtab_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_filter_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_filter_symbols: ... + + def __next__(self) -> Symbol: ... + + class PHDR_RELOC(enum.Enum): + AUTO = 0 + + PIE_SHIFT = 1 + + BSS_END = 2 + + FILE_END = 3 + + SEGMENT_GAP = 4 + + class SEC_INSERT_POS(enum.Enum): + AUTO = 0 + + POST_SECTION = 2 + + POST_SEGMENT = 1 + + @property + def type(self) -> Header.CLASS: ... + + @property + def header(self) -> Header: ... # type: ignore + + @property + def sections(self) -> Binary.it_sections: ... # type: ignore + + @property + def segments(self) -> Binary.it_segments: ... + + @property + def dynamic_entries(self) -> Binary.it_dynamic_entries: ... + + @overload + def add(self, arg: DynamicEntry, /) -> DynamicEntry: ... + + @overload + def add(self, section: Section, loaded: bool = True, pos: Binary.SEC_INSERT_POS = Binary.SEC_INSERT_POS.AUTO) -> Section | None: ... + + @overload + def add(self, segment: Segment, base: int = 0) -> Segment | None: ... + + @overload + def add(self, note: Note) -> Note: ... + + @property + def symtab_symbols(self) -> Binary.it_symbols: ... + + @property + def dynamic_symbols(self) -> Binary.it_symbols: ... + + @property + def symbols(self) -> Binary.it_dyn_symtab_symbols: ... # type: ignore + + @property + def exported_symbols(self) -> Binary.it_filter_symbols: ... + + @property + def imported_symbols(self) -> Binary.it_filter_symbols: ... + + @property + def dynamic_relocations(self) -> Binary.it_filter_relocation: ... + + def add_dynamic_relocation(self, relocation: Relocation) -> Relocation: ... + + def add_pltgot_relocation(self, relocation: Relocation) -> Relocation: ... + + def add_object_relocation(self, relocation: Relocation, section: Section) -> Relocation | None: ... + + @property + def pltgot_relocations(self) -> Binary.it_filter_relocation: ... + + @property + def object_relocations(self) -> Binary.it_filter_relocation: ... + + @property + def relocations(self) -> Binary.it_relocations: ... # type: ignore + + @property + def symbols_version(self) -> Binary.it_symbols_version: ... + + @property + def symbols_version_requirement(self) -> Binary.it_symbols_version_requirement: ... + + @property + def symbols_version_definition(self) -> Binary.it_symbols_version_definition: ... + + @property + def use_gnu_hash(self) -> bool: ... + + @property + def gnu_hash(self) -> GnuHash | None: ... + + @property + def use_sysv_hash(self) -> bool: ... + + @property + def sysv_hash(self) -> SysvHash | None: ... + + @property + def imagebase(self) -> int: ... + + @property + def virtual_size(self) -> int: ... + + @property + def is_pie(self) -> bool: ... + + @property + def has_interpreter(self) -> bool: ... + + @property + def functions(self) -> list[lief.Function]: ... + + interpreter: str + + def section_from_offset(self, offset: int, skip_nobits: bool = True) -> Section | None: ... + + def section_from_virtual_address(self, address: int, skip_nobits: bool = True) -> Section | None: ... + + def segment_from_virtual_address(self, address: int) -> Segment | None: ... + + def segment_from_offset(self, offset: int) -> Segment | None: ... + + @overload + def get(self, tag: DynamicEntry.TAG) -> DynamicEntry | None: ... + + @overload + def get(self, type: Segment.TYPE) -> Segment | None: ... + + @overload + def get(self, type: Note.TYPE) -> Note | None: ... + + @overload + def get(self, type: Section.TYPE) -> Section | None: ... + + @overload + def has(self, tag: DynamicEntry.TAG) -> bool: ... + + @overload + def has(self, type: Segment.TYPE) -> bool: ... + + @overload + def has(self, type: Note.TYPE) -> bool: ... + + @overload + def has(self, type: Section.TYPE) -> bool: ... + + @overload + def patch_pltgot(self, symbol_name: str, address: int) -> None: ... + + @overload + def patch_pltgot(self, symbol: Symbol, address: int) -> None: ... + + @overload + def dynsym_idx(self, name: str) -> int: ... + + @overload + def dynsym_idx(self, symbol: Symbol) -> int: ... + + @overload + def symtab_idx(self, name: str) -> int: ... + + @overload + def symtab_idx(self, symbol: Symbol) -> int: ... + + def has_section(self, section_name: str) -> bool: ... + + def has_section_with_offset(self, offset: int) -> bool: ... + + def has_section_with_va(self, virtual_address: int) -> bool: ... + + def get_section(self, section_name: str) -> Section | None: ... + + def add_symtab_symbol(self, symbol: Symbol) -> Symbol: ... + + def add_dynamic_symbol(self, symbol: Symbol, symbol_version: SymbolVersion | None = None) -> Symbol: ... + + def virtual_address_to_offset(self, virtual_address: int) -> Union[int, lief.lief_errors]: ... + + def replace(self, new_segment: Segment, original_segment: Segment, base: int = 0) -> Segment | None: ... + + @overload + def extend(self, segment: Segment, size: int) -> Segment | None: ... + + @overload + def extend(self, segment: Section, size: int) -> Section | None: ... + + @overload + def remove(self, dynamic_entry: DynamicEntry) -> None: ... + + @overload + def remove(self, tag: DynamicEntry.TAG) -> None: ... + + @overload + def remove(self, section: Section, clear: bool = False) -> None: ... + + @overload + def remove(self, segment: Segment, clear: bool = False) -> None: ... + + @overload + def remove(self, type: Segment.TYPE, clear: bool = False) -> None: ... + + @overload + def remove(self, note: Note) -> None: ... + + @overload + def remove(self, type: Note.TYPE) -> None: ... + + @property + def has_notes(self) -> bool: ... + + @property + def notes(self) -> Binary.it_notes: ... + + def strip(self) -> None: ... + + def permute_dynamic_symbols(self, permutation: Sequence[int]) -> None: ... + + @overload + def write(self, output: Union[str | os.PathLike]) -> None: ... + + @overload + def write(self, output: Union[str | os.PathLike], config: Builder.config_t) -> None: ... + + @overload + def write_to_bytes(self, config: Builder.config_t) -> bytes: ... + + @overload + def write_to_bytes(self) -> bytes: ... + + @property + def last_offset_section(self) -> int: ... + + @property + def last_offset_segment(self) -> int: ... + + @property + def next_virtual_address(self) -> int: ... + + def add_library(self, library_name: str) -> DynamicEntryLibrary: ... + + def has_library(self, library_name: str) -> bool: ... + + def remove_library(self, library_name: str) -> None: ... + + def get_library(self, library_name: str) -> DynamicEntryLibrary | None: ... + + def has_dynamic_symbol(self, symbol_name: str) -> bool: ... + + def get_dynamic_symbol(self, symbol_name: str) -> Symbol | None: ... + + def has_symtab_symbol(self, symbol_name: str) -> bool: ... + + def get_symtab_symbol(self, symbol_name: str) -> Symbol | None: ... + + def get_strings(self, min_size: int = 5) -> list[str]: ... + + @property + def strings(self) -> list[Union[str, bytes]]: ... + + def remove_symtab_symbol(self, arg: Symbol, /) -> None: ... + + @overload + def remove_dynamic_symbol(self, arg: Symbol, /) -> None: ... + + @overload + def remove_dynamic_symbol(self, arg: str, /) -> None: ... + + def add_exported_function(self, address: int, name: str = '') -> Symbol: ... + + @overload + def export_symbol(self, symbol: Symbol) -> Symbol: ... + + @overload + def export_symbol(self, symbol_name: str, value: int = 0) -> Symbol: ... + + @overload + def get_relocation(self, symbol_name: str) -> Relocation | None: ... + + @overload + def get_relocation(self, symbol: Symbol) -> Relocation | None: ... + + @overload + def get_relocation(self, address: int) -> Relocation | None: ... + + @property + def dtor_functions(self) -> list[lief.Function]: ... + + @property + def eof_offset(self) -> int: ... + + @property + def has_overlay(self) -> bool: ... + + @property + def is_targeting_android(self) -> bool: ... + + @overload + def get_section_idx(self, arg: Section, /) -> Union[int, lief.lief_errors]: ... + + @overload + def get_section_idx(self, arg: str, /) -> Union[int, lief.lief_errors]: ... + + @property + def overlay(self) -> memoryview: ... + + @overlay.setter + def overlay(self, arg: bytes, /) -> None: ... + + def relocate_phdr_table(self, type: Binary.PHDR_RELOC = Binary.PHDR_RELOC.AUTO) -> int: ... + + def get_relocated_dynamic_array(self, array_tag: DynamicEntry.TAG) -> list[int]: ... + + def find_version_requirement(self, libname: str) -> SymbolVersionRequirement | None: ... + + def remove_version_requirement(self, libname: str) -> bool: ... + + @overload + def __iadd__(self, arg: Segment, /) -> Binary: ... + + @overload + def __iadd__(self, arg: Section, /) -> Binary: ... + + @overload + def __iadd__(self, arg: DynamicEntry, /) -> Binary: ... + + @overload + def __iadd__(self, arg: Note, /) -> Binary | None: ... + + @overload + def __isub__(self, arg: DynamicEntry, /) -> Binary: ... + + @overload + def __isub__(self, arg: DynamicEntry.TAG, /) -> Binary: ... + + @overload + def __isub__(self, arg: Note, /) -> Binary | None: ... + + @overload + def __isub__(self, arg: Note.TYPE, /) -> Binary: ... + + @overload + def __getitem__(self, arg: Segment.TYPE, /) -> Segment | None: ... + + @overload + def __getitem__(self, arg: Note.TYPE, /) -> Note | None: ... + + @overload + def __getitem__(self, arg: DynamicEntry.TAG, /) -> DynamicEntry | None: ... + + @overload + def __getitem__(self, arg: Section.TYPE, /) -> Section | None: ... + + @overload + def __contains__(self, arg: Segment.TYPE, /) -> bool: ... + + @overload + def __contains__(self, arg: DynamicEntry.TAG, /) -> bool: ... + + @overload + def __contains__(self, arg: Note.TYPE, /) -> bool: ... + + @overload + def __contains__(self, arg: Section.TYPE, /) -> bool: ... + + def __str__(self) -> str: ... + +class PROCESSOR_FLAGS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> PROCESSOR_FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + ARM_EABI_UNKNOWN = 8796093022208 + + ARM_SOFT_FLOAT = 8796093022720 + + ARM_VFP_FLOAT = 8796093023232 + + ARM_EABI_VER1 = 8796109799424 + + ARM_EABI_VER2 = 8796126576640 + + ARM_EABI_VER3 = 8796143353856 + + ARM_EABI_VER4 = 8796160131072 + + ARM_EABI_VER5 = 8796176908288 + + HEXAGON_MACH_V2 = 17592186044417 + + HEXAGON_MACH_V3 = 17592186044418 + + HEXAGON_MACH_V4 = 17592186044419 + + HEXAGON_MACH_V5 = 17592186044420 + + HEXAGON_ISA_V2 = 17592186044432 + + HEXAGON_ISA_V3 = 17592186044448 + + HEXAGON_ISA_V4 = 17592186044464 + + HEXAGON_ISA_V5 = 17592186044480 + + LOONGARCH_ABI_SOFT_FLOAT = 26388279066625 + + LOONGARCH_ABI_SINGLE_FLOAT = 26388279066626 + + LOONGARCH_ABI_DOUBLE_FLOAT = 26388279066627 + + MIPS_NOREORDER = 35184372088833 + + MIPS_PIC = 35184372088834 + + MIPS_CPIC = 35184372088836 + + MIPS_ABI2 = 35184372088864 + + MIPS_32BITMODE = 35184372089088 + + MIPS_FP64 = 35184372089344 + + MIPS_NAN2008 = 35184372089856 + + MIPS_ABI_O32 = 35184372092928 + + MIPS_ABI_O64 = 35184372097024 + + MIPS_ABI_EABI32 = 35184372101120 + + MIPS_ABI_EABI64 = 35184372105216 + + MIPS_MACH_3900 = 35184380542976 + + MIPS_MACH_4010 = 35184380608512 + + MIPS_MACH_4100 = 35184380674048 + + MIPS_MACH_4650 = 35184380805120 + + MIPS_MACH_4120 = 35184380936192 + + MIPS_MACH_4111 = 35184381001728 + + MIPS_MACH_SB1 = 35184381132800 + + MIPS_MACH_OCTEON = 35184381198336 + + MIPS_MACH_XLR = 35184381263872 + + MIPS_MACH_OCTEON2 = 35184381329408 + + MIPS_MACH_OCTEON3 = 35184381394944 + + MIPS_MACH_5400 = 35184381591552 + + MIPS_MACH_5900 = 35184381657088 + + MIPS_MACH_5500 = 35184382050304 + + MIPS_MACH_9000 = 35184382115840 + + MIPS_MACH_LS2E = 35184382574592 + + MIPS_MACH_LS2F = 35184382640128 + + MIPS_MACH_LS3A = 35184382705664 + + MIPS_MICROMIPS = 35184405643264 + + MIPS_ARCH_ASE_M16 = 35184439197696 + + MIPS_ARCH_ASE_MDMX = 35184506306560 + + MIPS_ARCH_1 = 35184372088832 + + MIPS_ARCH_2 = 35184640524288 + + MIPS_ARCH_3 = 35184908959744 + + MIPS_ARCH_4 = 35185177395200 + + MIPS_ARCH_5 = 35185445830656 + + MIPS_ARCH_32 = 35185714266112 + + MIPS_ARCH_64 = 35185982701568 + + MIPS_ARCH_32R2 = 35186251137024 + + MIPS_ARCH_64R2 = 35186519572480 + + MIPS_ARCH_32R6 = 35186788007936 + + MIPS_ARCH_64R6 = 35187056443392 + + RISCV_RVC = 43980465111041 + + RISCV_FLOAT_ABI_SOFT = 43980465111040 + + RISCV_FLOAT_ABI_SINGLE = 43980465111042 + + RISCV_FLOAT_ABI_DOUBLE = 43980465111044 + + RISCV_FLOAT_ABI_QUAD = 43980465111046 + + RISCV_FLOAT_ABI_RVE = 43980465111048 + + RISCV_FLOAT_ABI_TSO = 43980465111056 + +class Header(lief.Object): + def __init__(self) -> None: ... + + class FILE_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.FILE_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + REL = 1 + + EXEC = 2 + + DYN = 3 + + CORE = 4 + + class VERSION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.VERSION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + CURRENT = 1 + + class CLASS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.CLASS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + ELF32 = 1 + + ELF64 = 2 + + class OS_ABI(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.OS_ABI: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + SYSTEMV = 0 + + HPUX = 1 + + NETBSD = 2 + + LINUX = 3 + + HURD = 4 + + SOLARIS = 6 + + AIX = 7 + + IRIX = 8 + + FREEBSD = 9 + + TRU64 = 10 + + MODESTO = 11 + + OPENBSD = 12 + + OPENVMS = 13 + + NSK = 14 + + AROS = 15 + + FENIXOS = 16 + + CLOUDABI = 17 + + AMDGPU_HSA = 64 + + C6000_LINUX = 65 + + ARM = 97 + + STANDALONE = 255 + + class ELF_DATA(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.ELF_DATA: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + LSB = 1 + + MSB = 2 + + identity_class: Header.CLASS + + identity_data: Header.ELF_DATA + + identity_version: Header.VERSION + + identity_os_abi: Header.OS_ABI + + identity_abi_version: int + + @property + def identity(self) -> list[int]: ... + + @identity.setter + def identity(self, arg: object, /) -> None: ... + + file_type: Header.FILE_TYPE + + machine_type: ARCH + + @property + def is_mips_n64(self) -> bool: ... + + object_file_version: Header.VERSION + + entrypoint: int + + program_header_offset: int + + section_header_offset: int + + processor_flag: int + + def has(self, arg: PROCESSOR_FLAGS, /) -> bool: ... + + @property + def flags_list(self) -> list[PROCESSOR_FLAGS]: ... + + header_size: int + + program_header_size: int + + numberof_segments: int + + section_header_size: int + + numberof_sections: int + + section_name_table_idx: int + + def __str__(self) -> str: ... + +class Section(lief.Section): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, name: str, type: Section.TYPE = Section.TYPE.PROGBITS) -> None: ... + + class it_segments: + def __getitem__(self, arg: int, /) -> Segment: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Section.it_segments: ... + + def __next__(self) -> Segment: ... + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Section.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + WRITE = 1 + + ALLOC = 2 + + EXECINSTR = 4 + + MERGE = 16 + + STRINGS = 32 + + INFO_LINK = 64 + + LINK_ORDER = 128 + + OS_NONCONFORMING = 256 + + GROUP = 512 + + TLS = 1024 + + COMPRESSED = 2048 + + GNU_RETAIN = 2097152 + + EXCLUDE = 2147483648 + + XCORE_SHF_DP_SECTION = 4563402752 + + XCORE_SHF_CP_SECTION = 4831838208 + + X86_64_LARGE = 8858370048 + + HEX_GPREL = 13153337344 + + MIPS_NODUPES = 17196646400 + + MIPS_NAMES = 17213423616 + + MIPS_LOCAL = 17246978048 + + MIPS_NOSTRIP = 17314086912 + + MIPS_GPREL = 17448304640 + + MIPS_MERGE = 17716740096 + + MIPS_ADDR = 18253611008 + + MIPS_STRING = 19327352832 + + ARM_PURECODE = 22011707392 + + AARCH64_PURECODE = 26306674688 + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Section.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + SHT_NULL_ = 0 + + PROGBITS = 1 + + SYMTAB = 2 + + STRTAB = 3 + + RELA = 4 + + HASH = 5 + + DYNAMIC = 6 + + NOTE = 7 + + NOBITS = 8 + + REL = 9 + + SHLIB = 10 + + DYNSYM = 11 + + INIT_ARRAY = 14 + + FINI_ARRAY = 15 + + PREINIT_ARRAY = 16 + + GROUP = 17 + + SYMTAB_SHNDX = 18 + + RELR = 19 + + ANDROID_REL = 1610612737 + + ANDROID_RELA = 1610612738 + + LLVM_ADDRSIG = 1879002115 + + ANDROID_RELR = 1879047936 + + GNU_ATTRIBUTES = 1879048181 + + GNU_HASH = 1879048182 + + GNU_VERDEF = 1879048189 + + GNU_VERNEED = 1879048190 + + GNU_VERSYM = 1879048191 + + ARM_EXIDX = 6174015489 + + ARM_PREEMPTMAP = 6174015490 + + ARM_ATTRIBUTES = 6174015491 + + ARM_DEBUGOVERLAY = 6174015492 + + ARM_OVERLAYSECTION = 6174015493 + + HEX_ORDERED = 10468982784 + + X86_64_UNWIND = 10468982785 + + MIPS_LIBLIST = 14763950080 + + MIPS_MSYM = 14763950081 + + MIPS_CONFLICT = 14763950082 + + MIPS_GPTAB = 14763950083 + + MIPS_UCODE = 14763950084 + + MIPS_DEBUG = 14763950085 + + MIPS_REGINFO = 14763950086 + + MIPS_PACKAGE = 14763950087 + + MIPS_PACKSYM = 14763950088 + + MIPS_RELD = 14763950089 + + MIPS_IFACE = 14763950091 + + MIPS_CONTENT = 14763950092 + + MIPS_OPTIONS = 14763950093 + + MIPS_SHDR = 14763950096 + + MIPS_FDESC = 14763950097 + + MIPS_EXTSYM = 14763950098 + + MIPS_DENSE = 14763950099 + + MIPS_PDESC = 14763950100 + + MIPS_LOCSYM = 14763950101 + + MIPS_AUXSYM = 14763950102 + + MIPS_OPTSYM = 14763950103 + + MIPS_LOCSTR = 14763950104 + + MIPS_LINE = 14763950105 + + MIPS_RFDESC = 14763950106 + + MIPS_DELTASYM = 14763950107 + + MIPS_DELTAINST = 14763950108 + + MIPS_DELTACLASS = 14763950109 + + MIPS_DWARF = 14763950110 + + MIPS_DELTADECL = 14763950111 + + MIPS_SYMBOL_LIB = 14763950112 + + MIPS_EVENTS = 14763950113 + + MIPS_TRANSLATE = 14763950114 + + MIPS_PIXIE = 14763950115 + + MIPS_XLATE = 14763950116 + + MIPS_XLATE_DEBUG = 14763950117 + + MIPS_WHIRL = 14763950118 + + MIPS_EH_REGION = 14763950119 + + MIPS_XLATE_OLD = 14763950120 + + MIPS_PDR_EXCEPTION = 14763950121 + + MIPS_ABIFLAGS = 14763950122 + + MIPS_XHASH = 14763950123 + + RISCV_ATTRIBUTES = 19058917379 + + AARCH64_ATTRIBUTES = 23353884675 + + AARCH64_AUTH_RELR = 23353884676 + + AARCH64_MEMTAG_GLOBALS_STATIC = 23353884679 + + AARCH64_MEMTAG_GLOBALS_DYNAMIC = 23353884680 + + def as_frame(self) -> Section: ... + + @property + def is_frame(self) -> bool: ... + + type: Section.TYPE + + flags: int + + @property + def flags_list(self) -> list[Section.FLAGS]: ... + + file_offset: int + + @property + def original_size(self) -> int: ... + + alignment: int + + information: int + + entry_size: int + + link: int + + @property + def segments(self) -> Section.it_segments: ... + + def clear(self, value: int = 0) -> Section: ... + + def add(self, flag: Section.FLAGS) -> None: ... + + def remove(self, flag: Section.FLAGS) -> None: ... + + @overload + def has(self, flag: Section.FLAGS) -> bool: ... + + @overload + def has(self, segment: Segment) -> bool: ... + + def __iadd__(self, arg: Section.FLAGS, /) -> Section: ... + + def __isub__(self, arg: Section.FLAGS, /) -> Section: ... + + @overload + def __contains__(self, arg: Section.FLAGS, /) -> bool: ... + + @overload + def __contains__(self, arg: Segment, /) -> bool: ... + + def __str__(self) -> str: ... + +class Segment(lief.Object): + def __init__(self) -> None: ... + + class it_sections: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Segment.it_sections: ... + + def __next__(self) -> Section: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Segment.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + PT_NULL_ = 0 + + LOAD = 1 + + DYNAMIC = 2 + + INTERP = 3 + + NOTE = 4 + + SHLIB = 5 + + PHDR = 6 + + TLS = 7 + + GNU_EH_FRAME = 1685382480 + + GNU_STACK = 1685382481 + + GNU_PROPERTY = 1685382483 + + GNU_RELRO = 1685382482 + + PAX_FLAGS = 1694766464 + + ARM_ARCHEXT = 10468982784 + + ARM_EXIDX = 10468982785 + + AARCH64_MEMTAG_MTE = 19058917378 + + MIPS_REGINFO = 27648851968 + + MIPS_RTPROC = 27648851969 + + MIPS_OPTIONS = 27648851970 + + MIPS_ABIFLAGS = 27648851971 + + RISCV_ATTRIBUTES = 36238786563 + + IA_64_EXT = 44828721152 + + IA_64_UNWIND = 44828721153 + + HP_TLS = 9007200865353728 + + HP_CORE_NONE = 9007200865353729 + + HP_CORE_VERSION = 9007200865353730 + + HP_CORE_KERNEL = 9007200865353731 + + HP_CORE_COMM = 9007200865353732 + + HP_CORE_PROC = 9007200865353733 + + HP_CORE_LOADABLE = 9007200865353734 + + HP_CORE_STACK = 9007200865353735 + + HP_CORE_SHM = 9007200865353736 + + HP_CORE_MMF = 9007200865353737 + + HP_PARALLEL = 9007200865353744 + + HP_FASTBIND = 9007200865353745 + + HP_OPT_ANNOT = 9007200865353746 + + HP_HSL_ANNOT = 9007200865353747 + + HP_STACK = 9007200865353748 + + HP_CORE_UTSNAME = 9007200865353749 + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Segment.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + R = 4 + + W = 2 + + X = 1 + + NONE = 0 + + @staticmethod + def from_raw(arg: bytes, /) -> Union[Segment, lief.lief_errors]: ... + + type: Segment.TYPE + + flags: Segment.FLAGS + + raw_flags: int + + file_offset: int + + virtual_address: int + + physical_address: int + + physical_size: int + + virtual_size: int + + alignment: int + + @property + def content(self) -> memoryview: ... + + @content.setter + def content(self, arg: Sequence[int], /) -> None: ... + + def add(self, flag: Segment.FLAGS) -> None: ... + + def remove(self, flag: Segment.FLAGS) -> None: ... + + @overload + def has(self, flag: Segment.FLAGS) -> bool: ... + + @overload + def has(self, section: Section) -> bool: ... + + @overload + def has(self, section_name: str) -> bool: ... + + def clear(self) -> None: ... + + def fill(self, value: str) -> None: ... + + @property + def sections(self) -> Segment.it_sections: ... + + def __iadd__(self, arg: Segment.FLAGS, /) -> Segment: ... + + def __isub__(self, arg: Segment.FLAGS, /) -> Segment: ... + + @overload + def __contains__(self, arg: Segment.FLAGS, /) -> bool: ... + + @overload + def __contains__(self, arg: Section, /) -> bool: ... + + @overload + def __contains__(self, arg: str, /) -> bool: ... + + def __str__(self) -> str: ... + +class Symbol(lief.Symbol): + def __init__(self) -> None: ... + + class BINDING(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.BINDING: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + LOCAL = 0 + + GLOBAL = 1 + + WEAK = 2 + + GNU_UNIQUE = 10 + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NOTYPE = 0 + + OBJECT = 1 + + FUNC = 2 + + SECTION = 3 + + FILE = 4 + + COMMON = 5 + + TLS = 6 + + GNU_IFUNC = 10 + + class VISIBILITY(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.VISIBILITY: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DEFAULT = 0 + + INTERNAL = 1 + + HIDDEN = 2 + + PROTECTED = 3 + + @property + def demangled_name(self) -> str: ... + + type: Symbol.TYPE + + binding: Symbol.BINDING + + information: int + + other: int + + visibility: Symbol.VISIBILITY + + value: int + + size: int + + shndx: int + + @property + def has_version(self) -> bool: ... + + @property + def symbol_version(self) -> SymbolVersion | None: ... + + @property + def section(self) -> Section | None: ... + + @property + def is_static(self) -> bool: ... + + @property + def is_function(self) -> bool: ... + + @property + def is_variable(self) -> bool: ... + + exported: bool + + imported: bool + + def __str__(self) -> str: ... + +class Relocation(lief.Relocation): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arch: ARCH) -> None: ... + + @overload + def __init__(self, address: int, type: Relocation.TYPE, encoding: Relocation.ENCODING) -> None: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Relocation.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + X86_64_NONE = 134217728 + + X86_64_64 = 134217729 + + X86_64_PC32 = 134217730 + + X86_64_GOT32 = 134217731 + + X86_64_PLT32 = 134217732 + + X86_64_COPY = 134217733 + + X86_64_GLOB_DAT = 134217734 + + X86_64_JUMP_SLOT = 134217735 + + X86_64_RELATIVE = 134217736 + + X86_64_GOTPCREL = 134217737 + + X86_64_32 = 134217738 + + X86_64_32S = 134217739 + + X86_64_16 = 134217740 + + X86_64_PC16 = 134217741 + + X86_64_8 = 134217742 + + X86_64_PC8 = 134217743 + + X86_64_DTPMOD64 = 134217744 + + X86_64_DTPOFF64 = 134217745 + + X86_64_TPOFF64 = 134217746 + + X86_64_TLSGD = 134217747 + + X86_64_TLSLD = 134217748 + + X86_64_DTPOFF32 = 134217749 + + X86_64_GOTTPOFF = 134217750 + + X86_64_TPOFF32 = 134217751 + + X86_64_PC64 = 134217752 + + X86_64_GOTOFF64 = 134217753 + + X86_64_GOTPC32 = 134217754 + + X86_64_GOT64 = 134217755 + + X86_64_GOTPCREL64 = 134217756 + + X86_64_GOTPC64 = 134217757 + + X86_64_GOTPLT64 = 134217758 + + X86_64_PLTOFF64 = 134217759 + + X86_64_SIZE32 = 134217760 + + X86_64_SIZE64 = 134217761 + + X86_64_GOTPC32_TLSDESC = 134217762 + + X86_64_TLSDESC_CALL = 134217763 + + X86_64_TLSDESC = 134217764 + + X86_64_IRELATIVE = 134217765 + + X86_64_RELATIVE64 = 134217766 + + X86_64_PC32_BND = 134217767 + + X86_64_PLT32_BND = 134217768 + + X86_64_GOTPCRELX = 134217769 + + X86_64_REX_GOTPCRELX = 134217770 + + AARCH64_NONE = 268435456 + + AARCH64_ABS64 = 268435713 + + AARCH64_ABS32 = 268435714 + + AARCH64_ABS16 = 268435715 + + AARCH64_PREL64 = 268435716 + + AARCH64_PREL32 = 268435717 + + AARCH64_PREL16 = 268435718 + + AARCH64_MOVW_UABS_G0 = 268435719 + + AARCH64_MOVW_UABS_G0_NC = 268435720 + + AARCH64_MOVW_UABS_G1 = 268435721 + + AARCH64_MOVW_UABS_G1_NC = 268435722 + + AARCH64_MOVW_UABS_G2 = 268435723 + + AARCH64_MOVW_UABS_G2_NC = 268435724 + + AARCH64_MOVW_UABS_G3 = 268435725 + + AARCH64_MOVW_SABS_G0 = 268435726 + + AARCH64_MOVW_SABS_G1 = 268435727 + + AARCH64_MOVW_SABS_G2 = 268435728 + + AARCH64_LD_PREL_LO19 = 268435729 + + AARCH64_ADR_PREL_LO21 = 268435730 + + AARCH64_ADR_PREL_PG_HI21 = 268435731 + + AARCH64_ADR_PREL_PG_HI21_NC = 268435732 + + AARCH64_ADD_ABS_LO12_NC = 268435733 + + AARCH64_LDST8_ABS_LO12_NC = 268435734 + + AARCH64_TSTBR14 = 268435735 + + AARCH64_CONDBR19 = 268435736 + + AARCH64_JUMP26 = 268435738 + + AARCH64_CALL26 = 268435739 + + AARCH64_LDST16_ABS_LO12_NC = 268435740 + + AARCH64_LDST32_ABS_LO12_NC = 268435741 + + AARCH64_LDST64_ABS_LO12_NC = 268435742 + + AARCH64_MOVW_PREL_G0 = 268435743 + + AARCH64_MOVW_PREL_G0_NC = 268435744 + + AARCH64_MOVW_PREL_G1 = 268435745 + + AARCH64_MOVW_PREL_G1_NC = 268435746 + + AARCH64_MOVW_PREL_G2 = 268435747 + + AARCH64_MOVW_PREL_G2_NC = 268435748 + + AARCH64_MOVW_PREL_G3 = 268435749 + + AARCH64_LDST128_ABS_LO12_NC = 268435755 + + AARCH64_MOVW_GOTOFF_G0 = 268435756 + + AARCH64_MOVW_GOTOFF_G0_NC = 268435757 + + AARCH64_MOVW_GOTOFF_G1 = 268435758 + + AARCH64_MOVW_GOTOFF_G1_NC = 268435759 + + AARCH64_MOVW_GOTOFF_G2 = 268435760 + + AARCH64_MOVW_GOTOFF_G2_NC = 268435761 + + AARCH64_MOVW_GOTOFF_G3 = 268435762 + + AARCH64_GOTREL64 = 268435763 + + AARCH64_GOTREL32 = 268435764 + + AARCH64_GOT_LD_PREL19 = 268435765 + + AARCH64_LD64_GOTOFF_LO15 = 268435766 + + AARCH64_ADR_GOT_PAGE = 268435767 + + AARCH64_LD64_GOT_LO12_NC = 268435768 + + AARCH64_LD64_GOTPAGE_LO15 = 268435769 + + AARCH64_TLSGD_ADR_PREL21 = 268435968 + + AARCH64_TLSGD_ADR_PAGE21 = 268435969 + + AARCH64_TLSGD_ADD_LO12_NC = 268435970 + + AARCH64_TLSGD_MOVW_G1 = 268435971 + + AARCH64_TLSGD_MOVW_G0_NC = 268435972 + + AARCH64_TLSLD_ADR_PREL21 = 268435973 + + AARCH64_TLSLD_ADR_PAGE21 = 268435974 + + AARCH64_TLSLD_ADD_LO12_NC = 268435975 + + AARCH64_TLSLD_MOVW_G1 = 268435976 + + AARCH64_TLSLD_MOVW_G0_NC = 268435977 + + AARCH64_TLSLD_LD_PREL19 = 268435978 + + AARCH64_TLSLD_MOVW_DTPREL_G2 = 268435979 + + AARCH64_TLSLD_MOVW_DTPREL_G1 = 268435980 + + AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 268435981 + + AARCH64_TLSLD_MOVW_DTPREL_G0 = 268435982 + + AARCH64_TLSLD_MOVW_DTPREL_G0_NC = 268435983 + + AARCH64_TLSLD_ADD_DTPREL_HI12 = 268435984 + + AARCH64_TLSLD_ADD_DTPREL_LO12 = 268435985 + + AARCH64_TLSLD_ADD_DTPREL_LO12_NC = 268435986 + + AARCH64_TLSLD_LDST8_DTPREL_LO12 = 268435987 + + AARCH64_TLSLD_LDST8_DTPREL_LO12_NC = 268435988 + + AARCH64_TLSLD_LDST16_DTPREL_LO12 = 268435989 + + AARCH64_TLSLD_LDST16_DTPREL_LO12_NC = 268435990 + + AARCH64_TLSLD_LDST32_DTPREL_LO12 = 268435991 + + AARCH64_TLSLD_LDST32_DTPREL_LO12_NC = 268435992 + + AARCH64_TLSLD_LDST64_DTPREL_LO12 = 268435993 + + AARCH64_TLSLD_LDST64_DTPREL_LO12_NC = 268435994 + + AARCH64_TLSIE_MOVW_GOTTPREL_G1 = 268435995 + + AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC = 268435996 + + AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 268435997 + + AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 268435998 + + AARCH64_TLSIE_LD_GOTTPREL_PREL19 = 268435999 + + AARCH64_TLSLE_MOVW_TPREL_G2 = 268436000 + + AARCH64_TLSLE_MOVW_TPREL_G1 = 268436001 + + AARCH64_TLSLE_MOVW_TPREL_G1_NC = 268436002 + + AARCH64_TLSLE_MOVW_TPREL_G0 = 268436003 + + AARCH64_TLSLE_MOVW_TPREL_G0_NC = 268436004 + + AARCH64_TLSLE_ADD_TPREL_HI12 = 268436005 + + AARCH64_TLSLE_ADD_TPREL_LO12 = 268436006 + + AARCH64_TLSLE_ADD_TPREL_LO12_NC = 268436007 + + AARCH64_TLSLE_LDST8_TPREL_LO12 = 268436008 + + AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 268436009 + + AARCH64_TLSLE_LDST16_TPREL_LO12 = 268436010 + + AARCH64_TLSLE_LDST16_TPREL_LO12_NC = 268436011 + + AARCH64_TLSLE_LDST32_TPREL_LO12 = 268436012 + + AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 268436013 + + AARCH64_TLSLE_LDST64_TPREL_LO12 = 268436014 + + AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 268436015 + + AARCH64_TLSDESC_LD_PREL19 = 268436016 + + AARCH64_TLSDESC_ADR_PREL21 = 268436017 + + AARCH64_TLSDESC_ADR_PAGE21 = 268436018 + + AARCH64_TLSDESC_LD64_LO12_NC = 268436019 + + AARCH64_TLSDESC_ADD_LO12_NC = 268436020 + + AARCH64_TLSDESC_OFF_G1 = 268436021 + + AARCH64_TLSDESC_OFF_G0_NC = 268436022 + + AARCH64_TLSDESC_LDR = 268436023 + + AARCH64_TLSDESC_ADD = 268436024 + + AARCH64_TLSDESC_CALL = 268436025 + + AARCH64_TLSLE_LDST128_TPREL_LO12 = 268436026 + + AARCH64_TLSLE_LDST128_TPREL_LO12_NC = 268436027 + + AARCH64_TLSLD_LDST128_DTPREL_LO12 = 268436028 + + AARCH64_TLSLD_LDST128_DTPREL_LO12_NC = 268436029 + + AARCH64_COPY = 268436480 + + AARCH64_GLOB_DAT = 268436481 + + AARCH64_JUMP_SLOT = 268436482 + + AARCH64_RELATIVE = 268436483 + + AARCH64_TLS_DTPREL64 = 268436484 + + AARCH64_TLS_DTPMOD64 = 268436485 + + AARCH64_TLS_TPREL64 = 268436486 + + AARCH64_TLSDESC = 268436487 + + AARCH64_IRELATIVE = 268436488 + + ARM_NONE = 402653184 + + ARM_PC24 = 402653185 + + ARM_ABS32 = 402653186 + + ARM_REL32 = 402653187 + + ARM_LDR_PC_G0 = 402653188 + + ARM_ABS16 = 402653189 + + ARM_ABS12 = 402653190 + + ARM_THM_ABS5 = 402653191 + + ARM_ABS8 = 402653192 + + ARM_SBREL32 = 402653193 + + ARM_THM_CALL = 402653194 + + ARM_THM_PC8 = 402653195 + + ARM_BREL_ADJ = 402653196 + + ARM_TLS_DESC = 402653197 + + ARM_THM_SWI8 = 402653198 + + ARM_XPC25 = 402653199 + + ARM_THM_XPC22 = 402653200 + + ARM_TLS_DTPMOD32 = 402653201 + + ARM_TLS_DTPOFF32 = 402653202 + + ARM_TLS_TPOFF32 = 402653203 + + ARM_COPY = 402653204 + + ARM_GLOB_DAT = 402653205 + + ARM_JUMP_SLOT = 402653206 + + ARM_RELATIVE = 402653207 + + ARM_GOTOFF32 = 402653208 + + ARM_BASE_PREL = 402653209 + + ARM_GOT_BREL = 402653210 + + ARM_PLT32 = 402653211 + + ARM_CALL = 402653212 + + ARM_JUMP24 = 402653213 + + ARM_THM_JUMP24 = 402653214 + + ARM_BASE_ABS = 402653215 + + ARM_ALU_PCREL_7_0 = 402653216 + + ARM_ALU_PCREL_15_8 = 402653217 + + ARM_ALU_PCREL_23_15 = 402653218 + + ARM_LDR_SBREL_11_0_NC = 402653219 + + ARM_ALU_SBREL_19_12_NC = 402653220 + + ARM_ALU_SBREL_27_20_CK = 402653221 + + ARM_TARGET1 = 402653222 + + ARM_SBREL31 = 402653223 + + ARM_V4BX = 402653224 + + ARM_TARGET2 = 402653225 + + ARM_PREL31 = 402653226 + + ARM_MOVW_ABS_NC = 402653227 + + ARM_MOVT_ABS = 402653228 + + ARM_MOVW_PREL_NC = 402653229 + + ARM_MOVT_PREL = 402653230 + + ARM_THM_MOVW_ABS_NC = 402653231 + + ARM_THM_MOVT_ABS = 402653232 + + ARM_THM_MOVW_PREL_NC = 402653233 + + ARM_THM_MOVT_PREL = 402653234 + + ARM_THM_JUMP19 = 402653235 + + ARM_THM_JUMP6 = 402653236 + + ARM_THM_ALU_PREL_11_0 = 402653237 + + ARM_THM_PC12 = 402653238 + + ARM_ABS32_NOI = 402653239 + + ARM_REL32_NOI = 402653240 + + ARM_ALU_PC_G0_NC = 402653241 + + ARM_ALU_PC_G0 = 402653242 + + ARM_ALU_PC_G1_NC = 402653243 + + ARM_ALU_PC_G1 = 402653244 + + ARM_ALU_PC_G2 = 402653245 + + ARM_LDR_PC_G1 = 402653246 + + ARM_LDR_PC_G2 = 402653247 + + ARM_LDRS_PC_G0 = 402653248 + + ARM_LDRS_PC_G1 = 402653249 + + ARM_LDRS_PC_G2 = 402653250 + + ARM_LDC_PC_G0 = 402653251 + + ARM_LDC_PC_G1 = 402653252 + + ARM_LDC_PC_G2 = 402653253 + + ARM_ALU_SB_G0_NC = 402653254 + + ARM_ALU_SB_G0 = 402653255 + + ARM_ALU_SB_G1_NC = 402653256 + + ARM_ALU_SB_G1 = 402653257 + + ARM_ALU_SB_G2 = 402653258 + + ARM_LDR_SB_G0 = 402653259 + + ARM_LDR_SB_G1 = 402653260 + + ARM_LDR_SB_G2 = 402653261 + + ARM_LDRS_SB_G0 = 402653262 + + ARM_LDRS_SB_G1 = 402653263 + + ARM_LDRS_SB_G2 = 402653264 + + ARM_LDC_SB_G0 = 402653265 + + ARM_LDC_SB_G1 = 402653266 + + ARM_LDC_SB_G2 = 402653267 + + ARM_MOVW_BREL_NC = 402653268 + + ARM_MOVT_BREL = 402653269 + + ARM_MOVW_BREL = 402653270 + + ARM_THM_MOVW_BREL_NC = 402653271 + + ARM_THM_MOVT_BREL = 402653272 + + ARM_THM_MOVW_BREL = 402653273 + + ARM_TLS_GOTDESC = 402653274 + + ARM_TLS_CALL = 402653275 + + ARM_TLS_DESCSEQ = 402653276 + + ARM_THM_TLS_CALL = 402653277 + + ARM_PLT32_ABS = 402653278 + + ARM_GOT_ABS = 402653279 + + ARM_GOT_PREL = 402653280 + + ARM_GOT_BREL12 = 402653281 + + ARM_GOTOFF12 = 402653282 + + ARM_GOTRELAX = 402653283 + + ARM_GNU_VTENTRY = 402653284 + + ARM_GNU_VTINHERIT = 402653285 + + ARM_THM_JUMP11 = 402653286 + + ARM_THM_JUMP8 = 402653287 + + ARM_TLS_GD32 = 402653288 + + ARM_TLS_LDM32 = 402653289 + + ARM_TLS_LDO32 = 402653290 + + ARM_TLS_IE32 = 402653291 + + ARM_TLS_LE32 = 402653292 + + ARM_TLS_LDO12 = 402653293 + + ARM_TLS_LE12 = 402653294 + + ARM_TLS_IE12GP = 402653295 + + ARM_PRIVATE_0 = 402653296 + + ARM_PRIVATE_1 = 402653297 + + ARM_PRIVATE_2 = 402653298 + + ARM_PRIVATE_3 = 402653299 + + ARM_PRIVATE_4 = 402653300 + + ARM_PRIVATE_5 = 402653301 + + ARM_PRIVATE_6 = 402653302 + + ARM_PRIVATE_7 = 402653303 + + ARM_PRIVATE_8 = 402653304 + + ARM_PRIVATE_9 = 402653305 + + ARM_PRIVATE_10 = 402653306 + + ARM_PRIVATE_11 = 402653307 + + ARM_PRIVATE_12 = 402653308 + + ARM_PRIVATE_13 = 402653309 + + ARM_PRIVATE_14 = 402653310 + + ARM_PRIVATE_15 = 402653311 + + ARM_ME_TOO = 402653312 + + ARM_THM_TLS_DESCSEQ16 = 402653313 + + ARM_THM_TLS_DESCSEQ32 = 402653314 + + ARM_IRELATIVE = 402653344 + + ARM_RXPC25 = 402653433 + + ARM_RSBREL32 = 402653434 + + ARM_THM_RPC22 = 402653435 + + ARM_RREL32 = 402653436 + + ARM_RPC24 = 402653437 + + ARM_RBASE = 402653438 + + HEX_NONE = 536870912 + + HEX_B22_PCREL = 536870913 + + HEX_B15_PCREL = 536870914 + + HEX_B7_PCREL = 536870915 + + HEX_LO16 = 536870916 + + HEX_HI16 = 536870917 + + HEX_32 = 536870918 + + HEX_16 = 536870919 + + HEX_8 = 536870920 + + HEX_GPREL16_0 = 536870921 + + HEX_GPREL16_1 = 536870922 + + HEX_GPREL16_2 = 536870923 + + HEX_GPREL16_3 = 536870924 + + HEX_HL16 = 536870925 + + HEX_B13_PCREL = 536870926 + + HEX_B9_PCREL = 536870927 + + HEX_B32_PCREL_X = 536870928 + + HEX_32_6_X = 536870929 + + HEX_B22_PCREL_X = 536870930 + + HEX_B15_PCREL_X = 536870931 + + HEX_B13_PCREL_X = 536870932 + + HEX_B9_PCREL_X = 536870933 + + HEX_B7_PCREL_X = 536870934 + + HEX_16_X = 536870935 + + HEX_12_X = 536870936 + + HEX_11_X = 536870937 + + HEX_10_X = 536870938 + + HEX_9_X = 536870939 + + HEX_8_X = 536870940 + + HEX_7_X = 536870941 + + HEX_6_X = 536870942 + + HEX_32_PCREL = 536870943 + + HEX_COPY = 536870944 + + HEX_GLOB_DAT = 536870945 + + HEX_JMP_SLOT = 536870946 + + HEX_RELATIVE = 536870947 + + HEX_PLT_B22_PCREL = 536870948 + + HEX_GOTREL_LO16 = 536870949 + + HEX_GOTREL_HI16 = 536870950 + + HEX_GOTREL_32 = 536870951 + + HEX_GOT_LO16 = 536870952 + + HEX_GOT_HI16 = 536870953 + + HEX_GOT_32 = 536870954 + + HEX_GOT_16 = 536870955 + + HEX_DTPMOD_32 = 536870956 + + HEX_DTPREL_LO16 = 536870957 + + HEX_DTPREL_HI16 = 536870958 + + HEX_DTPREL_32 = 536870959 + + HEX_DTPREL_16 = 536870960 + + HEX_GD_PLT_B22_PCREL = 536870961 + + HEX_GD_GOT_LO16 = 536870962 + + HEX_GD_GOT_HI16 = 536870963 + + HEX_GD_GOT_32 = 536870964 + + HEX_GD_GOT_16 = 536870965 + + HEX_IE_LO16 = 536870966 + + HEX_IE_HI16 = 536870967 + + HEX_IE_32 = 536870968 + + HEX_IE_GOT_LO16 = 536870969 + + HEX_IE_GOT_HI16 = 536870970 + + HEX_IE_GOT_32 = 536870971 + + HEX_IE_GOT_16 = 536870972 + + HEX_TPREL_LO16 = 536870973 + + HEX_TPREL_HI16 = 536870974 + + HEX_TPREL_32 = 536870975 + + HEX_TPREL_16 = 536870976 + + HEX_6_PCREL_X = 536870977 + + HEX_GOTREL_32_6_X = 536870978 + + HEX_GOTREL_16_X = 536870979 + + HEX_GOTREL_11_X = 536870980 + + HEX_GOT_32_6_X = 536870981 + + HEX_GOT_16_X = 536870982 + + HEX_GOT_11_X = 536870983 + + HEX_DTPREL_32_6_X = 536870984 + + HEX_DTPREL_16_X = 536870985 + + HEX_DTPREL_11_X = 536870986 + + HEX_GD_GOT_32_6_X = 536870987 + + HEX_GD_GOT_16_X = 536870988 + + HEX_GD_GOT_11_X = 536870989 + + HEX_IE_32_6_X = 536870990 + + HEX_IE_16_X = 536870991 + + HEX_IE_GOT_32_6_X = 536870992 + + HEX_IE_GOT_16_X = 536870993 + + HEX_IE_GOT_11_X = 536870994 + + HEX_TPREL_32_6_X = 536870995 + + HEX_TPREL_16_X = 536870996 + + HEX_TPREL_11_X = 536870997 + + HEX_LD_PLT_B22_PCREL = 536870998 + + HEX_LD_GOT_LO16 = 536870999 + + HEX_LD_GOT_HI16 = 536871000 + + HEX_LD_GOT_32 = 536871001 + + HEX_LD_GOT_16 = 536871002 + + HEX_LD_GOT_32_6_X = 536871003 + + HEX_LD_GOT_16_X = 536871004 + + HEX_LD_GOT_11_X = 536871005 + + X86_NONE = 671088640 + + X86_32 = 671088641 + + X86_PC32 = 671088642 + + X86_GOT32 = 671088643 + + X86_PLT32 = 671088644 + + X86_COPY = 671088645 + + X86_GLOB_DAT = 671088646 + + X86_JUMP_SLOT = 671088647 + + X86_RELATIVE = 671088648 + + X86_GOTOFF = 671088649 + + X86_GOTPC = 671088650 + + X86_32PLT = 671088651 + + X86_TLS_TPOFF = 671088654 + + X86_TLS_IE = 671088655 + + X86_TLS_GOTIE = 671088656 + + X86_TLS_LE = 671088657 + + X86_TLS_GD = 671088658 + + X86_TLS_LDM = 671088659 + + X86_16 = 671088660 + + X86_PC16 = 671088661 + + X86_8 = 671088662 + + X86_PC8 = 671088663 + + X86_TLS_GD_32 = 671088664 + + X86_TLS_GD_PUSH = 671088665 + + X86_TLS_GD_CALL = 671088666 + + X86_TLS_GD_POP = 671088667 + + X86_TLS_LDM_32 = 671088668 + + X86_TLS_LDM_PUSH = 671088669 + + X86_TLS_LDM_CALL = 671088670 + + X86_TLS_LDM_POP = 671088671 + + X86_TLS_LDO_32 = 671088672 + + X86_TLS_IE_32 = 671088673 + + X86_TLS_LE_32 = 671088674 + + X86_TLS_DTPMOD32 = 671088675 + + X86_TLS_DTPOFF32 = 671088676 + + X86_TLS_TPOFF32 = 671088677 + + X86_TLS_GOTDESC = 671088679 + + X86_TLS_DESC_CALL = 671088680 + + X86_TLS_DESC = 671088681 + + X86_IRELATIVE = 671088682 + + LARCH_NONE = 805306368 + + LARCH_32 = 805306369 + + LARCH_64 = 805306370 + + LARCH_RELATIVE = 805306371 + + LARCH_COPY = 805306372 + + LARCH_JUMP_SLOT = 805306373 + + LARCH_TLS_DTPMOD32 = 805306374 + + LARCH_TLS_DTPMOD64 = 805306375 + + LARCH_TLS_DTPREL32 = 805306376 + + LARCH_TLS_DTPREL64 = 805306377 + + LARCH_TLS_TPREL32 = 805306378 + + LARCH_TLS_TPREL64 = 805306379 + + LARCH_IRELATIVE = 805306380 + + LARCH_MARK_LA = 805306388 + + LARCH_MARK_PCREL = 805306389 + + LARCH_SOP_PUSH_PCREL = 805306390 + + LARCH_SOP_PUSH_ABSOLUTE = 805306391 + + LARCH_SOP_PUSH_DUP = 805306392 + + LARCH_SOP_PUSH_GPREL = 805306393 + + LARCH_SOP_PUSH_TLS_TPREL = 805306394 + + LARCH_SOP_PUSH_TLS_GOT = 805306395 + + LARCH_SOP_PUSH_TLS_GD = 805306396 + + LARCH_SOP_PUSH_PLT_PCREL = 805306397 + + LARCH_SOP_ASSERT = 805306398 + + LARCH_SOP_NOT = 805306399 + + LARCH_SOP_SUB = 805306400 + + LARCH_SOP_SL = 805306401 + + LARCH_SOP_SR = 805306402 + + LARCH_SOP_ADD = 805306403 + + LARCH_SOP_AND = 805306404 + + LARCH_SOP_IF_ELSE = 805306405 + + LARCH_SOP_POP_32_S_10_5 = 805306406 + + LARCH_SOP_POP_32_U_10_12 = 805306407 + + LARCH_SOP_POP_32_S_10_12 = 805306408 + + LARCH_SOP_POP_32_S_10_16 = 805306409 + + LARCH_SOP_POP_32_S_10_16_S2 = 805306410 + + LARCH_SOP_POP_32_S_5_20 = 805306411 + + LARCH_SOP_POP_32_S_0_5_10_16_S2 = 805306412 + + LARCH_SOP_POP_32_S_0_10_10_16_S2 = 805306413 + + LARCH_SOP_POP_32_U = 805306414 + + LARCH_ADD8 = 805306415 + + LARCH_ADD16 = 805306416 + + LARCH_ADD24 = 805306417 + + LARCH_ADD32 = 805306418 + + LARCH_ADD64 = 805306419 + + LARCH_SUB8 = 805306420 + + LARCH_SUB16 = 805306421 + + LARCH_SUB24 = 805306422 + + LARCH_SUB32 = 805306423 + + LARCH_SUB64 = 805306424 + + LARCH_GNU_VTINHERIT = 805306425 + + LARCH_GNU_VTENTRY = 805306426 + + LARCH_B16 = 805306432 + + LARCH_B21 = 805306433 + + LARCH_B26 = 805306434 + + LARCH_ABS_HI20 = 805306435 + + LARCH_ABS_LO12 = 805306436 + + LARCH_ABS64_LO20 = 805306437 + + LARCH_ABS64_HI12 = 805306438 + + LARCH_PCALA_HI20 = 805306439 + + LARCH_PCALA_LO12 = 805306440 + + LARCH_PCALA64_LO20 = 805306441 + + LARCH_PCALA64_HI12 = 805306442 + + LARCH_GOT_PC_HI20 = 805306443 + + LARCH_GOT_PC_LO12 = 805306444 + + LARCH_GOT64_PC_LO20 = 805306445 + + LARCH_GOT64_PC_HI12 = 805306446 + + LARCH_GOT_HI20 = 805306447 + + LARCH_GOT_LO12 = 805306448 + + LARCH_GOT64_LO20 = 805306449 + + LARCH_GOT64_HI12 = 805306450 + + LARCH_TLS_LE_HI20 = 805306451 + + LARCH_TLS_LE_LO12 = 805306452 + + LARCH_TLS_LE64_LO20 = 805306453 + + LARCH_TLS_LE64_HI12 = 805306454 + + LARCH_TLS_IE_PC_HI20 = 805306455 + + LARCH_TLS_IE_PC_LO12 = 805306456 + + LARCH_TLS_IE64_PC_LO20 = 805306457 + + LARCH_TLS_IE64_PC_HI12 = 805306458 + + LARCH_TLS_IE_HI20 = 805306459 + + LARCH_TLS_IE_LO12 = 805306460 + + LARCH_TLS_IE64_LO20 = 805306461 + + LARCH_TLS_IE64_HI12 = 805306462 + + LARCH_TLS_LD_PC_HI20 = 805306463 + + LARCH_TLS_LD_HI20 = 805306464 + + LARCH_TLS_GD_PC_HI20 = 805306465 + + LARCH_TLS_GD_HI20 = 805306466 + + LARCH_32_PCREL = 805306467 + + LARCH_RELAX = 805306468 + + LARCH_ALIGN = 805306470 + + LARCH_PCREL20_S2 = 805306471 + + LARCH_ADD6 = 805306473 + + LARCH_SUB6 = 805306474 + + LARCH_ADD_ULEB128 = 805306475 + + LARCH_SUB_ULEB128 = 805306476 + + LARCH_64_PCREL = 805306477 + + LARCH_CALL36 = 805306478 + + LARCH_TLS_DESC32 = 805306381 + + LARCH_TLS_DESC64 = 805306382 + + LARCH_TLS_DESC_PC_HI20 = 805306479 + + LARCH_TLS_DESC_PC_LO12 = 805306480 + + LARCH_TLS_DESC64_PC_LO20 = 805306481 + + LARCH_TLS_DESC64_PC_HI12 = 805306482 + + LARCH_TLS_DESC_HI20 = 805306483 + + LARCH_TLS_DESC_LO12 = 805306484 + + LARCH_TLS_DESC64_LO20 = 805306485 + + LARCH_TLS_DESC64_HI12 = 805306486 + + LARCH_TLS_DESC_LD = 805306487 + + LARCH_TLS_DESC_CALL = 805306488 + + LARCH_TLS_LE_HI20_R = 805306489 + + LARCH_TLS_LE_ADD_R = 805306490 + + LARCH_TLS_LE_LO12_R = 805306491 + + LARCH_TLS_LD_PCREL20_S2 = 805306492 + + LARCH_TLS_GD_PCREL20_S2 = 805306493 + + LARCH_TLS_DESC_PCREL20_S2 = 805306494 + + MIPS_NONE = 939524096 + + MIPS_16 = 939524097 + + MIPS_32 = 939524098 + + MIPS_REL32 = 939524099 + + MIPS_26 = 939524100 + + MIPS_HI16 = 939524101 + + MIPS_LO16 = 939524102 + + MIPS_GPREL16 = 939524103 + + MIPS_LITERAL = 939524104 + + MIPS_GOT16 = 939524105 + + MIPS_PC16 = 939524106 + + MIPS_CALL16 = 939524107 + + MIPS_GPREL32 = 939524108 + + MIPS_UNUSED1 = 939524109 + + MIPS_UNUSED2 = 939524110 + + MIPS_UNUSED3 = 939524111 + + MIPS_SHIFT5 = 939524112 + + MIPS_SHIFT6 = 939524113 + + MIPS_64 = 939524114 + + MIPS_GOT_DISP = 939524115 + + MIPS_GOT_PAGE = 939524116 + + MIPS_GOT_OFST = 939524117 + + MIPS_GOT_HI16 = 939524118 + + MIPS_GOT_LO16 = 939524119 + + MIPS_SUB = 939524120 + + MIPS_INSERT_A = 939524121 + + MIPS_INSERT_B = 939524122 + + MIPS_DELETE = 939524123 + + MIPS_HIGHER = 939524124 + + MIPS_HIGHEST = 939524125 + + MIPS_CALL_HI16 = 939524126 + + MIPS_CALL_LO16 = 939524127 + + MIPS_SCN_DISP = 939524128 + + MIPS_REL16 = 939524129 + + MIPS_ADD_IMMEDIATE = 939524130 + + MIPS_PJUMP = 939524131 + + MIPS_RELGOT = 939524132 + + MIPS_JALR = 939524133 + + MIPS_TLS_DTPMOD32 = 939524134 + + MIPS_TLS_DTPREL32 = 939524135 + + MIPS_TLS_DTPMOD64 = 939524136 + + MIPS_TLS_DTPREL64 = 939524137 + + MIPS_TLS_GD = 939524138 + + MIPS_TLS_LDM = 939524139 + + MIPS_TLS_DTPREL_HI16 = 939524140 + + MIPS_TLS_DTPREL_LO16 = 939524141 + + MIPS_TLS_GOTTPREL = 939524142 + + MIPS_TLS_TPREL32 = 939524143 + + MIPS_TLS_TPREL64 = 939524144 + + MIPS_TLS_TPREL_HI16 = 939524145 + + MIPS_TLS_TPREL_LO16 = 939524146 + + MIPS_GLOB_DAT = 939524147 + + MIPS_PC21_S2 = 939524156 + + MIPS_PC26_S2 = 939524157 + + MIPS_PC18_S3 = 939524158 + + MIPS_PC19_S2 = 939524159 + + MIPS_PCHI16 = 939524160 + + MIPS_PCLO16 = 939524161 + + MIPS16_26 = 939524196 + + MIPS16_GPREL = 939524197 + + MIPS16_GOT16 = 939524198 + + MIPS16_CALL16 = 939524199 + + MIPS16_HI16 = 939524200 + + MIPS16_LO16 = 939524201 + + MIPS16_TLS_GD = 939524202 + + MIPS16_TLS_LDM = 939524203 + + MIPS16_TLS_DTPREL_HI16 = 939524204 + + MIPS16_TLS_DTPREL_LO16 = 939524205 + + MIPS16_TLS_GOTTPREL = 939524206 + + MIPS16_TLS_TPREL_HI16 = 939524207 + + MIPS16_TLS_TPREL_LO16 = 939524208 + + MIPS_COPY = 939524222 + + MIPS_JUMP_SLOT = 939524223 + + MICROMIPS_26_S1 = 939524229 + + MICROMIPS_HI16 = 939524230 + + MICROMIPS_LO16 = 939524231 + + MICROMIPS_GPREL16 = 939524232 + + MICROMIPS_LITERAL = 939524233 + + MICROMIPS_GOT16 = 939524234 + + MICROMIPS_PC7_S1 = 939524235 + + MICROMIPS_PC10_S1 = 939524236 + + MICROMIPS_PC16_S1 = 939524237 + + MICROMIPS_CALL16 = 939524238 + + MICROMIPS_GOT_DISP = 939524241 + + MICROMIPS_GOT_PAGE = 939524242 + + MICROMIPS_GOT_OFST = 939524243 + + MICROMIPS_GOT_HI16 = 939524244 + + MICROMIPS_GOT_LO16 = 939524245 + + MICROMIPS_SUB = 939524246 + + MICROMIPS_HIGHER = 939524247 + + MICROMIPS_HIGHEST = 939524248 + + MICROMIPS_CALL_HI16 = 939524249 + + MICROMIPS_CALL_LO16 = 939524250 + + MICROMIPS_SCN_DISP = 939524251 + + MICROMIPS_JALR = 939524252 + + MICROMIPS_HI0_LO16 = 939524253 + + MICROMIPS_TLS_GD = 939524258 + + MICROMIPS_TLS_LDM = 939524259 + + MICROMIPS_TLS_DTPREL_HI16 = 939524260 + + MICROMIPS_TLS_DTPREL_LO16 = 939524261 + + MICROMIPS_TLS_GOTTPREL = 939524262 + + MICROMIPS_TLS_TPREL_HI16 = 939524265 + + MICROMIPS_TLS_TPREL_LO16 = 939524266 + + MICROMIPS_GPREL7_S2 = 939524268 + + MICROMIPS_PC23_S2 = 939524269 + + MICROMIPS_PC21_S2 = 939524270 + + MICROMIPS_PC26_S2 = 939524271 + + MICROMIPS_PC18_S3 = 939524272 + + MICROMIPS_PC19_S2 = 939524273 + + MIPS_NUM = 939524314 + + MIPS_PC32 = 939524344 + + MIPS_EH = 939524345 + + PPC_NONE = 1073741824 + + PPC_ADDR32 = 1073741825 + + PPC_ADDR24 = 1073741826 + + PPC_ADDR16 = 1073741827 + + PPC_ADDR16_LO = 1073741828 + + PPC_ADDR16_HI = 1073741829 + + PPC_ADDR16_HA = 1073741830 + + PPC_ADDR14 = 1073741831 + + PPC_ADDR14_BRTAKEN = 1073741832 + + PPC_ADDR14_BRNTAKEN = 1073741833 + + PPC_REL24 = 1073741834 + + PPC_REL14 = 1073741835 + + PPC_REL14_BRTAKEN = 1073741836 + + PPC_REL14_BRNTAKEN = 1073741837 + + PPC_GOT16 = 1073741838 + + PPC_GOT16_LO = 1073741839 + + PPC_GOT16_HI = 1073741840 + + PPC_GOT16_HA = 1073741841 + + PPC_PLTREL24 = 1073741842 + + PPC_JMP_SLOT = 1073741845 + + PPC_RELATIVE = 1073741846 + + PPC_LOCAL24PC = 1073741847 + + PPC_REL32 = 1073741850 + + PPC_TLS = 1073741891 + + PPC_DTPMOD32 = 1073741892 + + PPC_TPREL16 = 1073741893 + + PPC_TPREL16_LO = 1073741894 + + PPC_TPREL16_HI = 1073741895 + + PPC_TPREL16_HA = 1073741896 + + PPC_TPREL32 = 1073741897 + + PPC_DTPREL16 = 1073741898 + + PPC_DTPREL16_LO = 1073741899 + + PPC_DTPREL16_HI = 1073741900 + + PPC_DTPREL16_HA = 1073741901 + + PPC_DTPREL32 = 1073741902 + + PPC_GOT_TLSGD16 = 1073741903 + + PPC_GOT_TLSGD16_LO = 1073741904 + + PPC_GOT_TLSGD16_HI = 1073741905 + + PPC_GOT_TLSGD16_HA = 1073741906 + + PPC_GOT_TLSLD16 = 1073741907 + + PPC_GOT_TLSLD16_LO = 1073741908 + + PPC_GOT_TLSLD16_HI = 1073741909 + + PPC_GOT_TLSLD16_HA = 1073741910 + + PPC_GOT_TPREL16 = 1073741911 + + PPC_GOT_TPREL16_LO = 1073741912 + + PPC_GOT_TPREL16_HI = 1073741913 + + PPC_GOT_TPREL16_HA = 1073741914 + + PPC_GOT_DTPREL16 = 1073741915 + + PPC_GOT_DTPREL16_LO = 1073741916 + + PPC_GOT_DTPREL16_HI = 1073741917 + + PPC_GOT_DTPREL16_HA = 1073741918 + + PPC_TLSGD = 1073741919 + + PPC_TLSLD = 1073741920 + + PPC_REL16 = 1073742073 + + PPC_REL16_LO = 1073742074 + + PPC_REL16_HI = 1073742075 + + PPC_REL16_HA = 1073742076 + + PPC64_NONE = 1207959552 + + PPC64_ADDR32 = 1207959553 + + PPC64_ADDR24 = 1207959554 + + PPC64_ADDR16 = 1207959555 + + PPC64_ADDR16_LO = 1207959556 + + PPC64_ADDR16_HI = 1207959557 + + PPC64_ADDR16_HA = 1207959558 + + PPC64_ADDR14 = 1207959559 + + PPC64_ADDR14_BRTAKEN = 1207959560 + + PPC64_ADDR14_BRNTAKEN = 1207959561 + + PPC64_REL24 = 1207959562 + + PPC64_REL14 = 1207959563 + + PPC64_REL14_BRTAKEN = 1207959564 + + PPC64_REL14_BRNTAKEN = 1207959565 + + PPC64_GOT16 = 1207959566 + + PPC64_GOT16_LO = 1207959567 + + PPC64_GOT16_HI = 1207959568 + + PPC64_GOT16_HA = 1207959569 + + PPC64_JMP_SLOT = 1207959573 + + PPC64_RELATIVE = 1207959574 + + PPC64_REL32 = 1207959578 + + PPC64_ADDR64 = 1207959590 + + PPC64_ADDR16_HIGHER = 1207959591 + + PPC64_ADDR16_HIGHERA = 1207959592 + + PPC64_ADDR16_HIGHEST = 1207959593 + + PPC64_ADDR16_HIGHESTA = 1207959594 + + PPC64_REL64 = 1207959596 + + PPC64_TOC16 = 1207959599 + + PPC64_TOC16_LO = 1207959600 + + PPC64_TOC16_HI = 1207959601 + + PPC64_TOC16_HA = 1207959602 + + PPC64_TOC = 1207959603 + + PPC64_ADDR16_DS = 1207959608 + + PPC64_ADDR16_LO_DS = 1207959609 + + PPC64_GOT16_DS = 1207959610 + + PPC64_GOT16_LO_DS = 1207959611 + + PPC64_TOC16_DS = 1207959615 + + PPC64_TOC16_LO_DS = 1207959616 + + PPC64_TLS = 1207959619 + + PPC64_DTPMOD64 = 1207959620 + + PPC64_TPREL16 = 1207959621 + + PPC64_TPREL16_LO = 1207959622 + + PPC64_TPREL16_HI = 1207959623 + + PPC64_TPREL16_HA = 1207959624 + + PPC64_TPREL64 = 1207959625 + + PPC64_DTPREL16 = 1207959626 + + PPC64_DTPREL16_LO = 1207959627 + + PPC64_DTPREL16_HI = 1207959628 + + PPC64_DTPREL16_HA = 1207959629 + + PPC64_DTPREL64 = 1207959630 + + PPC64_GOT_TLSGD16 = 1207959631 + + PPC64_GOT_TLSGD16_LO = 1207959632 + + PPC64_GOT_TLSGD16_HI = 1207959633 + + PPC64_GOT_TLSGD16_HA = 1207959634 + + PPC64_GOT_TLSLD16 = 1207959635 + + PPC64_GOT_TLSLD16_LO = 1207959636 + + PPC64_GOT_TLSLD16_HI = 1207959637 + + PPC64_GOT_TLSLD16_HA = 1207959638 + + PPC64_GOT_TPREL16_DS = 1207959639 + + PPC64_GOT_TPREL16_LO_DS = 1207959640 + + PPC64_GOT_TPREL16_HI = 1207959641 + + PPC64_GOT_TPREL16_HA = 1207959642 + + PPC64_GOT_DTPREL16_DS = 1207959643 + + PPC64_GOT_DTPREL16_LO_DS = 1207959644 + + PPC64_GOT_DTPREL16_HI = 1207959645 + + PPC64_GOT_DTPREL16_HA = 1207959646 + + PPC64_TPREL16_DS = 1207959647 + + PPC64_TPREL16_LO_DS = 1207959648 + + PPC64_TPREL16_HIGHER = 1207959649 + + PPC64_TPREL16_HIGHERA = 1207959650 + + PPC64_TPREL16_HIGHEST = 1207959651 + + PPC64_TPREL16_HIGHESTA = 1207959652 + + PPC64_DTPREL16_DS = 1207959653 + + PPC64_DTPREL16_LO_DS = 1207959654 + + PPC64_DTPREL16_HIGHER = 1207959655 + + PPC64_DTPREL16_HIGHERA = 1207959656 + + PPC64_DTPREL16_HIGHEST = 1207959657 + + PPC64_DTPREL16_HIGHESTA = 1207959658 + + PPC64_TLSGD = 1207959659 + + PPC64_TLSLD = 1207959660 + + PPC64_REL16 = 1207959801 + + PPC64_REL16_LO = 1207959802 + + PPC64_REL16_HI = 1207959803 + + PPC64_REL16_HA = 1207959804 + + SPARC_NONE = 1342177280 + + SPARC_8 = 1342177281 + + SPARC_16 = 1342177282 + + SPARC_32 = 1342177283 + + SPARC_DISP8 = 1342177284 + + SPARC_DISP16 = 1342177285 + + SPARC_DISP32 = 1342177286 + + SPARC_WDISP30 = 1342177287 + + SPARC_WDISP22 = 1342177288 + + SPARC_HI22 = 1342177289 + + SPARC_22 = 1342177290 + + SPARC_13 = 1342177291 + + SPARC_LO10 = 1342177292 + + SPARC_GOT10 = 1342177293 + + SPARC_GOT13 = 1342177294 + + SPARC_GOT22 = 1342177295 + + SPARC_PC10 = 1342177296 + + SPARC_PC22 = 1342177297 + + SPARC_WPLT30 = 1342177298 + + SPARC_COPY = 1342177299 + + SPARC_GLOB_DAT = 1342177300 + + SPARC_JMP_SLOT = 1342177301 + + SPARC_RELATIVE = 1342177302 + + SPARC_UA32 = 1342177303 + + SPARC_PLT32 = 1342177304 + + SPARC_HIPLT22 = 1342177305 + + SPARC_LOPLT10 = 1342177306 + + SPARC_PCPLT32 = 1342177307 + + SPARC_PCPLT22 = 1342177308 + + SPARC_PCPLT10 = 1342177309 + + SPARC_10 = 1342177310 + + SPARC_11 = 1342177311 + + SPARC_64 = 1342177312 + + SPARC_OLO10 = 1342177313 + + SPARC_HH22 = 1342177314 + + SPARC_HM10 = 1342177315 + + SPARC_LM22 = 1342177316 + + SPARC_PC_HH22 = 1342177317 + + SPARC_PC_HM10 = 1342177318 + + SPARC_PC_LM22 = 1342177319 + + SPARC_WDISP16 = 1342177320 + + SPARC_WDISP19 = 1342177321 + + SPARC_7 = 1342177323 + + SPARC_5 = 1342177324 + + SPARC_6 = 1342177325 + + SPARC_DISP64 = 1342177326 + + SPARC_PLT64 = 1342177327 + + SPARC_HIX22 = 1342177328 + + SPARC_LOX10 = 1342177329 + + SPARC_H44 = 1342177330 + + SPARC_M44 = 1342177331 + + SPARC_L44 = 1342177332 + + SPARC_REGISTER = 1342177333 + + SPARC_UA64 = 1342177334 + + SPARC_UA16 = 1342177335 + + SPARC_TLS_GD_HI22 = 1342177336 + + SPARC_TLS_GD_LO10 = 1342177337 + + SPARC_TLS_GD_ADD = 1342177338 + + SPARC_TLS_GD_CALL = 1342177339 + + SPARC_TLS_LDM_HI22 = 1342177340 + + SPARC_TLS_LDM_LO10 = 1342177341 + + SPARC_TLS_LDM_ADD = 1342177342 + + SPARC_TLS_LDM_CALL = 1342177343 + + SPARC_TLS_LDO_HIX22 = 1342177344 + + SPARC_TLS_LDO_LOX10 = 1342177345 + + SPARC_TLS_LDO_ADD = 1342177346 + + SPARC_TLS_IE_HI22 = 1342177347 + + SPARC_TLS_IE_LO10 = 1342177348 + + SPARC_TLS_IE_LD = 1342177349 + + SPARC_TLS_IE_LDX = 1342177350 + + SPARC_TLS_IE_ADD = 1342177351 + + SPARC_TLS_LE_HIX22 = 1342177352 + + SPARC_TLS_LE_LOX10 = 1342177353 + + SPARC_TLS_DTPMOD32 = 1342177354 + + SPARC_TLS_DTPMOD64 = 1342177355 + + SPARC_TLS_DTPOFF32 = 1342177356 + + SPARC_TLS_DTPOFF64 = 1342177357 + + SPARC_TLS_TPOFF32 = 1342177358 + + SPARC_TLS_TPOFF64 = 1342177359 + + SPARC_GOTDATA_HIX22 = 1342177360 + + SPARC_GOTDATA_LOX10 = 1342177361 + + SPARC_GOTDATA_OP_HIX22 = 1342177362 + + SPARC_GOTDATA_OP_LOX10 = 1342177363 + + SPARC_GOTDATA_OP = 1342177364 + + SYSZ_NONE = 1476395008 + + SYSZ_8 = 1476395009 + + SYSZ_12 = 1476395010 + + SYSZ_16 = 1476395011 + + SYSZ_32 = 1476395012 + + SYSZ_PC32 = 1476395013 + + SYSZ_GOT12 = 1476395014 + + SYSZ_GOT32 = 1476395015 + + SYSZ_PLT32 = 1476395016 + + SYSZ_COPY = 1476395017 + + SYSZ_GLOB_DAT = 1476395018 + + SYSZ_JMP_SLOT = 1476395019 + + SYSZ_RELATIVE = 1476395020 + + SYSZ_GOTOFF = 1476395021 + + SYSZ_GOTPC = 1476395022 + + SYSZ_GOT16 = 1476395023 + + SYSZ_PC16 = 1476395024 + + SYSZ_PC16DBL = 1476395025 + + SYSZ_PLT16DBL = 1476395026 + + SYSZ_PC32DBL = 1476395027 + + SYSZ_PLT32DBL = 1476395028 + + SYSZ_GOTPCDBL = 1476395029 + + SYSZ_64 = 1476395030 + + SYSZ_PC64 = 1476395031 + + SYSZ_GOT64 = 1476395032 + + SYSZ_PLT64 = 1476395033 + + SYSZ_GOTENT = 1476395034 + + SYSZ_GOTOFF16 = 1476395035 + + SYSZ_GOTOFF64 = 1476395036 + + SYSZ_GOTPLT12 = 1476395037 + + SYSZ_GOTPLT16 = 1476395038 + + SYSZ_GOTPLT32 = 1476395039 + + SYSZ_GOTPLT64 = 1476395040 + + SYSZ_GOTPLTENT = 1476395041 + + SYSZ_PLTOFF16 = 1476395042 + + SYSZ_PLTOFF32 = 1476395043 + + SYSZ_PLTOFF64 = 1476395044 + + SYSZ_TLS_LOAD = 1476395045 + + SYSZ_TLS_GDCALL = 1476395046 + + SYSZ_TLS_LDCALL = 1476395047 + + SYSZ_TLS_GD32 = 1476395048 + + SYSZ_TLS_GD64 = 1476395049 + + SYSZ_TLS_GOTIE12 = 1476395050 + + SYSZ_TLS_GOTIE32 = 1476395051 + + SYSZ_TLS_GOTIE64 = 1476395052 + + SYSZ_TLS_LDM32 = 1476395053 + + SYSZ_TLS_LDM64 = 1476395054 + + SYSZ_TLS_IE32 = 1476395055 + + SYSZ_TLS_IE64 = 1476395056 + + SYSZ_TLS_IEENT = 1476395057 + + SYSZ_TLS_LE32 = 1476395058 + + SYSZ_TLS_LE64 = 1476395059 + + SYSZ_TLS_LDO32 = 1476395060 + + SYSZ_TLS_LDO64 = 1476395061 + + SYSZ_TLS_DTPMOD = 1476395062 + + SYSZ_TLS_DTPOFF = 1476395063 + + SYSZ_TLS_TPOFF = 1476395064 + + SYSZ_20 = 1476395065 + + SYSZ_GOT20 = 1476395066 + + SYSZ_GOTPLT20 = 1476395067 + + SYSZ_TLS_GOTIE20 = 1476395068 + + SYSZ_IRELATIVE = 1476395069 + + SYSZ_PC12DBL = 1476395070 + + SYSZ_PLT12DBL = 1476395071 + + SYSZ_PC24DBL = 1476395072 + + SYSZ_PLT24DBL = 1476395073 + + RISCV_NONE = 1610612736 + + RISCV_32 = 1610612737 + + RISCV_64 = 1610612738 + + RISCV_RELATIVE = 1610612739 + + RISCV_COPY = 1610612740 + + RISCV_JUMP_SLOT = 1610612741 + + RISCV_TLS_DTPMOD32 = 1610612742 + + RISCV_TLS_DTPMOD64 = 1610612743 + + RISCV_TLS_DTPREL32 = 1610612744 + + RISCV_TLS_DTPREL64 = 1610612745 + + RISCV_TLS_TPREL32 = 1610612746 + + RISCV_TLS_TPREL64 = 1610612747 + + RISCV_TLSDESC = 1610612748 + + RISCV_BRANCH = 1610612752 + + RISCV_JAL = 1610612753 + + RISCV_CALL = 1610612754 + + RISCV_CALL_PLT = 1610612755 + + RISCV_GOT_HI20 = 1610612756 + + RISCV_TLS_GOT_HI20 = 1610612757 + + RISCV_TLS_GD_HI20 = 1610612758 + + RISCV_PCREL_HI20 = 1610612759 + + RISCV_PCREL_LO12_I = 1610612760 + + RISCV_PCREL_LO12_S = 1610612761 + + RISCV_HI20 = 1610612762 + + RISCV_LO12_I = 1610612763 + + RISCV_LO12_S = 1610612764 + + RISCV_TPREL_HI20 = 1610612765 + + RISCV_TPREL_LO12_I = 1610612766 + + RISCV_TPREL_LO12_S = 1610612767 + + RISCV_TPREL_ADD = 1610612768 + + RISCV_ADD8 = 1610612769 + + RISCV_ADD16 = 1610612770 + + RISCV_ADD32 = 1610612771 + + RISCV_ADD64 = 1610612772 + + RISCV_SUB8 = 1610612773 + + RISCV_SUB16 = 1610612774 + + RISCV_SUB32 = 1610612775 + + RISCV_SUB64 = 1610612776 + + RISCV_GOT32_PCREL = 1610612777 + + RISCV_ALIGN = 1610612779 + + RISCV_RVC_BRANCH = 1610612780 + + RISCV_RVC_JUMP = 1610612781 + + RISCV_RVC_LUI = 1610612782 + + RISCV_RELAX = 1610612787 + + RISCV_SUB6 = 1610612788 + + RISCV_SET6 = 1610612789 + + RISCV_SET8 = 1610612790 + + RISCV_SET16 = 1610612791 + + RISCV_SET32 = 1610612792 + + RISCV_32_PCREL = 1610612793 + + RISCV_IRELATIVE = 1610612794 + + RISCV_PLT32 = 1610612795 + + RISCV_SET_ULEB128 = 1610612796 + + RISCV_SUB_ULEB128 = 1610612797 + + RISCV_TLSDESC_HI20 = 1610612798 + + RISCV_TLSDESC_LOAD_LO12 = 1610612799 + + RISCV_TLSDESC_ADD_LO12 = 1610612800 + + RISCV_TLSDESC_CALL = 1610612801 + + BPF_NONE = 1744830464 + + BPF_64_64 = 1744830465 + + BPF_64_ABS64 = 1744830466 + + BPF_64_ABS32 = 1744830467 + + BPF_64_NODYLD32 = 1744830468 + + BPF_64_32 = 1744830474 + + SH_NONE = 1879048192 + + SH_DIR32 = 1879048193 + + SH_REL32 = 1879048194 + + SH_DIR8WPN = 1879048195 + + SH_IND12W = 1879048196 + + SH_DIR8WPL = 1879048197 + + SH_DIR8WPZ = 1879048198 + + SH_DIR8BP = 1879048199 + + SH_DIR8W = 1879048200 + + SH_DIR8L = 1879048201 + + SH_LOOP_START = 1879048202 + + SH_LOOP_END = 1879048203 + + SH_GNU_VTINHERIT = 1879048214 + + SH_GNU_VTENTRY = 1879048215 + + SH_SWITCH8 = 1879048216 + + SH_SWITCH16 = 1879048217 + + SH_SWITCH32 = 1879048218 + + SH_USES = 1879048219 + + SH_COUNT = 1879048220 + + SH_ALIGN = 1879048221 + + SH_CODE = 1879048222 + + SH_DATA = 1879048223 + + SH_LABEL = 1879048224 + + SH_DIR16 = 1879048225 + + SH_DIR8 = 1879048226 + + SH_DIR8UL = 1879048227 + + SH_DIR8UW = 1879048228 + + SH_DIR8U = 1879048229 + + SH_DIR8SW = 1879048230 + + SH_DIR8S = 1879048231 + + SH_DIR4UL = 1879048232 + + SH_DIR4UW = 1879048233 + + SH_DIR4U = 1879048234 + + SH_PSHA = 1879048235 + + SH_PSHL = 1879048236 + + SH_DIR5U = 1879048237 + + SH_DIR6U = 1879048238 + + SH_DIR6S = 1879048239 + + SH_DIR10S = 1879048240 + + SH_DIR10SW = 1879048241 + + SH_DIR10SL = 1879048242 + + SH_DIR10SQ = 1879048243 + + SH_DIR16S = 1879048245 + + SH_TLS_GD_32 = 1879048336 + + SH_TLS_LD_32 = 1879048337 + + SH_TLS_LDO_32 = 1879048338 + + SH_TLS_IE_32 = 1879048339 + + SH_TLS_LE_32 = 1879048340 + + SH_TLS_DTPMOD32 = 1879048341 + + SH_TLS_DTPOFF32 = 1879048342 + + SH_TLS_TPOFF32 = 1879048343 + + SH_GOT32 = 1879048352 + + SH_PLT32 = 1879048353 + + SH_COPY = 1879048354 + + SH_GLOB_DAT = 1879048355 + + SH_JMP_SLOT = 1879048356 + + SH_RELATIVE = 1879048357 + + SH_GOTOFF = 1879048358 + + SH_GOTPC = 1879048359 + + SH_GOTPLT32 = 1879048360 + + SH_GOT_LOW16 = 1879048361 + + SH_GOT_MEDLOW16 = 1879048362 + + SH_GOT_MEDHI16 = 1879048363 + + SH_GOT_HI16 = 1879048364 + + SH_GOTPLT_LOW16 = 1879048365 + + SH_GOTPLT_MEDLOW16 = 1879048366 + + SH_GOTPLT_MEDHI16 = 1879048367 + + SH_GOTPLT_HI16 = 1879048368 + + SH_PLT_LOW16 = 1879048369 + + SH_PLT_MEDLOW16 = 1879048370 + + SH_PLT_MEDHI16 = 1879048371 + + SH_PLT_HI16 = 1879048372 + + SH_GOTOFF_LOW16 = 1879048373 + + SH_GOTOFF_MEDLOW16 = 1879048374 + + SH_GOTOFF_MEDHI16 = 1879048375 + + SH_GOTOFF_HI16 = 1879048376 + + SH_GOTPC_LOW16 = 1879048377 + + SH_GOTPC_MEDLOW16 = 1879048378 + + SH_GOTPC_MEDHI16 = 1879048379 + + SH_GOTPC_HI16 = 1879048380 + + SH_GOT10BY4 = 1879048381 + + SH_GOTPLT10BY4 = 1879048382 + + SH_GOT10BY8 = 1879048383 + + SH_GOTPLT10BY8 = 1879048384 + + SH_COPY64 = 1879048385 + + SH_GLOB_DAT64 = 1879048386 + + SH_JMP_SLOT64 = 1879048387 + + SH_RELATIVE64 = 1879048388 + + SH_GOT20 = 1879048393 + + SH_GOTOFF20 = 1879048394 + + SH_GOTFUNCDESC = 1879048395 + + SH_GOTFUNCDESC20 = 1879048396 + + SH_GOTOFFFUNCDESC = 1879048397 + + SH_GOTOFFFUNCDESC20 = 1879048398 + + SH_FUNCDESC = 1879048399 + + SH_FUNCDESC_VALUE = 1879048400 + + SH_SHMEDIA_CODE = 1879048434 + + SH_PT_16 = 1879048435 + + SH_IMMS16 = 1879048436 + + SH_IMMU16 = 1879048437 + + SH_IMM_LOW16 = 1879048438 + + SH_IMM_LOW16_PCREL = 1879048439 + + SH_IMM_MEDLOW16 = 1879048440 + + SH_IMM_MEDLOW16_PCREL = 1879048441 + + SH_IMM_MEDHI16 = 1879048442 + + SH_IMM_MEDHI16_PCREL = 1879048443 + + SH_IMM_HI16 = 1879048444 + + SH_IMM_HI16_PCREL = 1879048445 + + SH_64 = 1879048446 + + SH_64_PCREL = 1879048447 + + class PURPOSE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Relocation.PURPOSE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + PLTGOT = 1 + + DYNAMIC = 2 + + OBJECT = 3 + + class ENCODING(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Relocation.ENCODING: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + ANDROID_SLEB = 4 + + REL = 1 + + RELR = 3 + + RELA = 2 + + addend: int + + info: int + + purpose: Relocation.PURPOSE + + type: Relocation.TYPE + + @property + def has_symbol(self) -> bool: ... + + @property + def symbol(self) -> Symbol | None: ... + + @symbol.setter + def symbol(self, arg: Symbol, /) -> None: ... + + @property + def has_section(self) -> bool: ... + + @property + def section(self) -> Section | None: ... + + @property + def symbol_table(self) -> Section | None: ... + + @property + def is_rela(self) -> bool: ... + + @property + def is_rel(self) -> bool: ... + + @overload + def r_info(self, clazz: Header.CLASS, data: Header.ELF_DATA) -> int: ... + + @overload + def r_info(self, header: Header) -> int: ... + + @property + def is_relatively_encoded(self) -> bool: ... + + @property + def is_android_packed(self) -> bool: ... + + @property + def encoding(self) -> Relocation.ENCODING: ... + + def resolve(self, base_address: int = 0) -> Union[int, lief.lief_errors]: ... + + def __str__(self) -> str: ... + +class SymbolVersionAux(lief.Object): + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class SymbolVersionAuxRequirement(SymbolVersionAux): + def __init__(self) -> None: ... + + hash: int + + flags: int + + other: int + + def __str__(self) -> str: ... + +class SymbolVersionDefinition(lief.Object): + class it_version_aux: + def __getitem__(self, arg: int, /) -> SymbolVersionAux: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> SymbolVersionDefinition.it_version_aux: ... + + def __next__(self) -> SymbolVersionAux: ... + + version: int + + flags: int + + hash: int + + @property + def ndx(self) -> int: ... + + @property + def auxiliary_symbols(self) -> SymbolVersionDefinition.it_version_aux: ... + + def __str__(self) -> str: ... + +class SymbolVersionRequirement(lief.Object): + class it_aux_requirement: + def __getitem__(self, arg: int, /) -> SymbolVersionAuxRequirement: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> SymbolVersionRequirement.it_aux_requirement: ... + + def __next__(self) -> SymbolVersionAuxRequirement: ... + + version: int + + name: str + + def get_auxiliary_symbols(self) -> SymbolVersionRequirement.it_aux_requirement: ... + + def add_auxiliary_requirement(self, arg: SymbolVersionAuxRequirement, /) -> SymbolVersionAuxRequirement: ... + + def find_aux(self, name: str) -> SymbolVersionAuxRequirement | None: ... + + @overload + def remove_aux_requirement(self, name: str) -> bool: ... + + @overload + def remove_aux_requirement(self, aux: SymbolVersionAuxRequirement) -> bool: ... + + def __str__(self) -> str: ... + +class DynamicEntry(lief.Object): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, tag: DynamicEntry.TAG, value: int) -> None: ... + + class TAG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DynamicEntry.TAG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 18446744073709551615 + + NULL = 0 + + NEEDED = 1 + + PLTRELSZ = 2 + + PLTGOT = 3 + + HASH = 4 + + STRTAB = 5 + + SYMTAB = 6 + + RELA = 7 + + RELASZ = 8 + + RELAENT = 9 + + STRSZ = 10 + + SYMENT = 11 + + INIT = 12 + + FINI = 13 + + SONAME = 14 + + RPATH = 15 + + SYMBOLIC = 16 + + REL = 17 + + RELSZ = 18 + + RELENT = 19 + + PLTREL = 20 + + DEBUG_TAG = 21 + + TEXTREL = 22 + + JMPREL = 23 + + BIND_NOW = 24 + + INIT_ARRAY = 25 + + FINI_ARRAY = 26 + + INIT_ARRAYSZ = 27 + + FINI_ARRAYSZ = 28 + + RUNPATH = 29 + + FLAGS = 30 + + PREINIT_ARRAY = 32 + + PREINIT_ARRAYSZ = 33 + + SYMTAB_SHNDX = 34 + + RELRSZ = 35 + + RELR = 36 + + RELRENT = 37 + + GNU_HASH = 1879047925 + + TLSDESC_PLT = 1879047926 + + TLSDESC_GOT = 1879047927 + + RELACOUNT = 1879048185 + + RELCOUNT = 1879048186 + + FLAGS_1 = 1879048187 + + VERSYM = 1879048176 + + VERDEF = 1879048188 + + VERDEFNUM = 1879048189 + + VERNEED = 1879048190 + + VERNEEDNUM = 1879048191 + + AUXILIARY = 2147483645 + + FILTER = 2147483647 + + ANDROID_REL_OFFSET = 1610612749 + + ANDROID_REL_SIZE = 1610612750 + + ANDROID_REL = 1610612751 + + ANDROID_RELSZ = 1610612752 + + ANDROID_RELA = 1610612753 + + ANDROID_RELASZ = 1610612754 + + ANDROID_RELR = 1879040000 + + ANDROID_RELRSZ = 1879040001 + + ANDROID_RELRENT = 1879040003 + + ANDROID_RELRCOUNT = 1879040005 + + MIPS_RLD_VERSION = 6174015489 + + MIPS_TIME_STAMP = 6174015490 + + MIPS_ICHECKSUM = 6174015491 + + MIPS_IVERSION = 6174015492 + + MIPS_FLAGS = 6174015493 + + MIPS_BASE_ADDRESS = 6174015494 + + MIPS_MSYM = 6174015495 + + MIPS_CONFLICT = 6174015496 + + MIPS_LIBLIST = 6174015497 + + MIPS_LOCAL_GOTNO = 6174015498 + + MIPS_CONFLICTNO = 6174015499 + + MIPS_LIBLISTNO = 6174015504 + + MIPS_SYMTABNO = 6174015505 + + MIPS_UNREFEXTNO = 6174015506 + + MIPS_GOTSYM = 6174015507 + + MIPS_HIPAGENO = 6174015508 + + MIPS_RLD_MAP = 6174015510 + + MIPS_DELTA_CLASS = 6174015511 + + MIPS_DELTA_CLASS_NO = 6174015512 + + MIPS_DELTA_INSTANCE = 6174015513 + + MIPS_DELTA_INSTANCE_NO = 6174015514 + + MIPS_DELTA_RELOC = 6174015515 + + MIPS_DELTA_RELOC_NO = 6174015516 + + MIPS_DELTA_SYM = 6174015517 + + MIPS_DELTA_SYM_NO = 6174015518 + + MIPS_DELTA_CLASSSYM = 6174015520 + + MIPS_DELTA_CLASSSYM_NO = 6174015521 + + MIPS_CXX_FLAGS = 6174015522 + + MIPS_PIXIE_INIT = 6174015523 + + MIPS_SYMBOL_LIB = 6174015524 + + MIPS_LOCALPAGE_GOTIDX = 6174015525 + + MIPS_LOCAL_GOTIDX = 6174015526 + + MIPS_HIDDEN_GOTIDX = 6174015527 + + MIPS_PROTECTED_GOTIDX = 6174015528 + + MIPS_OPTIONS = 6174015529 + + MIPS_INTERFACE = 6174015530 + + MIPS_DYNSTR_ALIGN = 6174015531 + + MIPS_INTERFACE_SIZE = 6174015532 + + MIPS_RLD_TEXT_RESOLVE_ADDR = 6174015533 + + MIPS_PERF_SUFFIX = 6174015534 + + MIPS_COMPACT_SIZE = 6174015535 + + MIPS_GP_VALUE = 6174015536 + + MIPS_AUX_DYNAMIC = 6174015537 + + MIPS_PLTGOT = 6174015538 + + MIPS_RWPLT = 6174015540 + + MIPS_RLD_MAP_REL = 6174015541 + + MIPS_XHASH = 6174015542 + + AARCH64_BTI_PLT = 10468982785 + + AARCH64_PAC_PLT = 10468982787 + + AARCH64_VARIANT_PCS = 10468982789 + + AARCH64_MEMTAG_MODE = 10468982793 + + AARCH64_MEMTAG_HEAP = 10468982795 + + AARCH64_MEMTAG_STACK = 10468982796 + + AARCH64_MEMTAG_GLOBALS = 10468982797 + + AARCH64_MEMTAG_GLOBALSSZ = 10468982799 + + HEXAGON_SYMSZ = 14763950080 + + HEXAGON_VER = 14763950081 + + HEXAGON_PLT = 14763950082 + + PPC_GOT = 19058917376 + + PPC_OPT = 19058917377 + + PPC64_GLINK = 23353884672 + + PPC64_OPT = 23353884675 + + RISCV_VARIANT_CC = 27648851971 + + X86_64_PLT = 31943819264 + + X86_64_PLTSZ = 31943819265 + + X86_64_PLTENT = 31943819267 + + IA_64_PLT_RESERVE = 36238786560 + + IA_64_VMS_SUBTYPE = 35970351104 + + IA_64_VMS_IMGIOCNT = 35970351106 + + IA_64_VMS_LNKFLAGS = 35970351112 + + IA_64_VMS_VIR_MEM_BLK_SIZ = 35970351114 + + IA_64_VMS_IDENT = 35970351116 + + IA_64_VMS_NEEDED_IDENT = 35970351120 + + IA_64_VMS_IMG_RELA_CNT = 35970351122 + + IA_64_VMS_SEG_RELA_CNT = 35970351124 + + IA_64_VMS_FIXUP_RELA_CNT = 35970351126 + + IA_64_VMS_FIXUP_NEEDED = 35970351128 + + IA_64_VMS_SYMVEC_CNT = 35970351130 + + IA_64_VMS_XLATED = 35970351134 + + IA_64_VMS_STACKSIZE = 35970351136 + + IA_64_VMS_UNWINDSZ = 35970351138 + + IA_64_VMS_UNWIND_CODSEG = 35970351140 + + IA_64_VMS_UNWIND_INFOSEG = 35970351142 + + IA_64_VMS_LINKTIME = 35970351144 + + IA_64_VMS_SEG_NO = 35970351146 + + IA_64_VMS_SYMVEC_OFFSET = 35970351148 + + IA_64_VMS_SYMVEC_SEG = 35970351150 + + IA_64_VMS_UNWIND_OFFSET = 35970351152 + + IA_64_VMS_UNWIND_SEG = 35970351154 + + IA_64_VMS_STRTAB_OFFSET = 35970351156 + + IA_64_VMS_SYSVER_OFFSET = 35970351158 + + IA_64_VMS_IMG_RELA_OFF = 35970351160 + + IA_64_VMS_SEG_RELA_OFF = 35970351162 + + IA_64_VMS_FIXUP_RELA_OFF = 35970351164 + + IA_64_VMS_PLTGOT_OFFSET = 35970351166 + + IA_64_VMS_PLTGOT_SEG = 35970351168 + + IA_64_VMS_FPMODE = 35970351170 + + tag: DynamicEntry.TAG + + value: int + + def __str__(self) -> str: ... + +class DynamicEntryLibrary(DynamicEntry): + def __init__(self, library_name: str) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class DynamicSharedObject(DynamicEntry): + def __init__(self, library_name: str) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class DynamicEntryAuxiliary(DynamicEntry): + def __init__(self, library_name: str) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class DynamicEntryFilter(DynamicEntry): + def __init__(self, library_name: str) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class DynamicEntryArray(DynamicEntry): + def __init__(self, tag: DynamicEntry.TAG, array: Sequence[int]) -> None: ... + + @property + def array(self) -> list[int]: ... + + @array.setter + def array(self, arg: Sequence[int], /) -> None: ... + + def insert(self, pos: int, function: int) -> DynamicEntryArray: ... + + def append(self, function: int) -> DynamicEntryArray: ... + + def remove(self, function: int) -> DynamicEntryArray: ... + + def __iadd__(self, arg: int, /) -> DynamicEntryArray: ... + + def __isub__(self, arg: int, /) -> DynamicEntryArray: ... + + def __getitem__(self, arg: int, /) -> int: ... + + def __len__(self) -> int: ... + + def __str__(self) -> str: ... + +class DynamicEntryRpath(DynamicEntry): + @overload + def __init__(self, path: str = '') -> None: ... + + @overload + def __init__(self, paths: Sequence[str]) -> None: ... + + @property + def rpath(self) -> Union[str, bytes]: ... + + @rpath.setter + def rpath(self, arg: str, /) -> None: ... + + @property + def paths(self) -> list[str]: ... + + @paths.setter + def paths(self, arg: Sequence[str], /) -> None: ... + + def insert(self, position: int, path: str) -> DynamicEntryRpath: ... + + def append(self, path: str) -> DynamicEntryRpath: ... + + def remove(self, path: str) -> DynamicEntryRpath: ... + + def __iadd__(self, arg: str, /) -> DynamicEntryRpath: ... + + def __isub__(self, arg: str, /) -> DynamicEntryRpath: ... + + def __str__(self) -> str: ... + +class DynamicEntryRunPath(DynamicEntry): + @overload + def __init__(self, path: str = '') -> None: ... + + @overload + def __init__(self, paths: Sequence[str]) -> None: ... + + @property + def runpath(self) -> Union[str, bytes]: ... + + @runpath.setter + def runpath(self, arg: str, /) -> None: ... + + @property + def paths(self) -> list[str]: ... + + @paths.setter + def paths(self, arg: Sequence[str], /) -> None: ... + + def insert(self, position: int, path: str) -> DynamicEntryRunPath: ... + + def append(self, path: str) -> DynamicEntryRunPath: ... + + def remove(self, path: str) -> DynamicEntryRunPath: ... + + def __iadd__(self, arg: str, /) -> DynamicEntryRunPath: ... + + def __isub__(self, arg: str, /) -> DynamicEntryRunPath: ... + + def __str__(self) -> str: ... + +class DynamicEntryFlags(DynamicEntry): + class FLAG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DynamicEntryFlags.FLAG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + ORIGIN = 1 + + SYMBOLIC = 2 + + TEXTREL = 4 + + BIND_NOW = 8 + + STATIC_TLS = 16 + + NOW = 4294967297 + + GLOBAL = 4294967298 + + GROUP = 4294967300 + + NODELETE = 4294967304 + + LOADFLTR = 4294967312 + + INITFIRST = 4294967328 + + NOOPEN = 4294967360 + + HANDLE_ORIGIN = 4294967424 + + DIRECT = 4294967552 + + TRANS = 4294967808 + + INTERPOSE = 4294968320 + + NODEFLIB = 4294969344 + + NODUMP = 4294971392 + + CONFALT = 4294975488 + + ENDFILTEE = 4294983680 + + DISPRELDNE = 4295000064 + + DISPRELPND = 4295032832 + + NODIRECT = 4295098368 + + IGNMULDEF = 4295229440 + + NOKSYMS = 4295491584 + + NOHDR = 4296015872 + + EDITED = 4297064448 + + NORELOC = 4299161600 + + SYMINTPOSE = 4303355904 + + GLOBAUDIT = 4311744512 + + SINGLETON = 4328521728 + + PIE = 4429185024 + + KMOD = 4563402752 + + WEAKFILTER = 4831838208 + + NOCOMMON = 5368709120 + + @property + def flags(self) -> list[DynamicEntryFlags.FLAG]: ... + + def has(self, flag: DynamicEntryFlags.FLAG) -> bool: ... + + def add(self, flag: DynamicEntryFlags.FLAG) -> None: ... + + def remove(self, flag: DynamicEntryFlags.FLAG) -> None: ... + + def __iadd__(self, arg: DynamicEntryFlags.FLAG, /) -> DynamicEntryFlags: ... + + def __isub__(self, arg: DynamicEntryFlags.FLAG, /) -> DynamicEntryFlags: ... + + def __contains__(self, arg: DynamicEntryFlags.FLAG, /) -> bool: ... + + def __str__(self) -> str: ... + +class GnuHash(lief.Object): + def __init__(self) -> None: ... + + @property + def nb_buckets(self) -> int: ... + + @property + def symbol_index(self) -> int: ... + + @property + def shift2(self) -> int: ... + + @property + def bloom_filters(self) -> list[int]: ... + + @property + def buckets(self) -> list[int]: ... + + @property + def hash_values(self) -> list[int]: ... + + def check_bloom_filter(self, hash: int) -> bool: ... + + def check_bucket(self, hash: int) -> bool: ... + + @overload + def check(self, symbol_name: str) -> bool: ... + + @overload + def check(self, hash_value: int) -> bool: ... + + def __str__(self) -> str: ... + +class SysvHash(lief.Object): + def __init__(self) -> None: ... + + @property + def nbucket(self) -> int: ... + + nchain: int + + @property + def buckets(self) -> list[int]: ... + + @property + def chains(self) -> list[int]: ... + + def __str__(self) -> str: ... + +class Builder: + @overload + def __init__(self, elf: Binary) -> None: ... + + @overload + def __init__(self, elf: Binary, config: Builder.config_t) -> None: ... + + class config_t: + def __init__(self) -> None: ... + + force_relocate: bool + + skip_dynamic: bool + + dt_hash: bool + + dyn_str: bool + + dynamic_section: bool + + fini_array: bool + + init_array: bool + + interpreter: bool + + jmprel: bool + + notes: bool + + preinit_array: bool + + relr: bool + + android_rela: bool + + rela: bool + + static_symtab: bool + + sym_verdef: bool + + sym_verneed: bool + + sym_versym: bool + + symtab: bool + + coredump_notes: bool + + keep_empty_version_requirement: bool + + def build(self) -> None: ... + + @property + def config(self) -> Builder.config_t: ... + + def write(self, output: str) -> None: ... + + def get_build(self) -> list[int]: ... + +class Note(lief.Object): + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Note.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + GNU_ABI_TAG = 1 + + GNU_HWCAP = 2 + + GNU_BUILD_ID = 3 + + GNU_GOLD_VERSION = 4 + + GNU_PROPERTY_TYPE_0 = 5 + + GNU_BUILD_ATTRIBUTE_OPEN = 6 + + GNU_BUILD_ATTRIBUTE_FUNC = 7 + + CRASHPAD = 8 + + CORE_PRSTATUS = 9 + + CORE_FPREGSET = 10 + + CORE_PRPSINFO = 11 + + CORE_TASKSTRUCT = 12 + + CORE_AUXV = 13 + + CORE_PSTATUS = 14 + + CORE_FPREGS = 15 + + CORE_PSINFO = 16 + + CORE_LWPSTATUS = 17 + + CORE_LWPSINFO = 18 + + CORE_WIN32PSTATUS = 19 + + CORE_FILE = 20 + + CORE_PRXFPREG = 21 + + CORE_SIGINFO = 22 + + CORE_ARM_VFP = 23 + + CORE_ARM_TLS = 24 + + CORE_ARM_HW_BREAK = 25 + + CORE_ARM_HW_WATCH = 26 + + CORE_ARM_SYSTEM_CALL = 27 + + CORE_ARM_SVE = 28 + + CORE_ARM_PAC_MASK = 29 + + CORE_ARM_PACA_KEYS = 30 + + CORE_ARM_PACG_KEYS = 31 + + CORE_TAGGED_ADDR_CTRL = 32 + + CORE_PAC_ENABLED_KEYS = 33 + + CORE_X86_TLS = 34 + + CORE_X86_IOPERM = 35 + + CORE_X86_XSTATE = 36 + + CORE_X86_CET = 37 + + ANDROID_MEMTAG = 39 + + ANDROID_KUSER = 40 + + ANDROID_IDENT = 38 + + GO_BUILDID = 41 + + STAPSDT = 42 + + QNX_STACK = 43 + + @overload + @staticmethod + def create(name: str, original_type: int, description: Sequence[int], section_name: str, file_type: Header.FILE_TYPE = Header.FILE_TYPE.NONE, arch: ARCH = ARCH.NONE, cls: Header.CLASS = Header.CLASS.NONE) -> Optional[Note]: ... + + @overload + @staticmethod + def create(raw: bytes, section_name: str = '', file_type: Header.FILE_TYPE = Header.FILE_TYPE.NONE, arch: ARCH = ARCH.NONE, cls: Header.CLASS = Header.CLASS.NONE) -> Optional[Note]: ... + + @overload + @staticmethod + def create(name: str, type: Note.TYPE, description: Sequence[int], section_name: str, arch: ARCH = ARCH.NONE, cls: Header.CLASS = Header.CLASS.NONE) -> Optional[Note]: ... + + name: str + + @property + def original_type(self) -> int: ... + + @property + def type(self) -> Note.TYPE: ... + + @property + def description(self) -> memoryview: ... + + @description.setter + def description(self, arg: Sequence[int], /) -> None: ... + + @property + def size(self) -> int: ... + + def copy(self) -> Optional[Note]: ... + + def __str__(self) -> str: ... + +class NoteGnuProperty(Note): + class Property: + @property + def type(self) -> NoteGnuProperty.Property.TYPE: ... + + def __str__(self) -> str: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> NoteGnuProperty.Property.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + GENERIC = 1 + + AARCH64_FEATURES = 2 + + AARCH64_PAUTH = 3 + + STACK_SIZE = 4 + + NO_COPY_ON_PROTECTED = 5 + + X86_ISA = 6 + + X86_FEATURE = 7 + + NEEDED = 8 + + @property + def properties(self) -> list[Optional[NoteGnuProperty.Property]]: ... + + def find(self, arg: NoteGnuProperty.Property.TYPE, /) -> Optional[NoteGnuProperty.Property]: ... + + def __str__(self) -> str: ... + +class AArch64Feature(NoteGnuProperty.Property): + @property + def features(self) -> list[AArch64Feature.FEATURE]: ... + + class FEATURE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> AArch64Feature.FEATURE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + BTI = 1 + + PAC = 2 + + GCS = 3 + +class AArch64PAuth(NoteGnuProperty.Property): + @property + def platform(self) -> int: ... + + @property + def version(self) -> int: ... + +class Needed(NoteGnuProperty.Property): + class NEED(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Needed.NEED: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NEED = 0 + + INDIRECT_EXTERN_ACCESS = 1 + + @property + def needs(self) -> list[Needed.NEED]: ... + +class X86Features(NoteGnuProperty.Property): + @property + def features(self) -> list[tuple[X86Features.FLAG, X86Features.FEATURE]]: ... + + class FLAG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86Features.FLAG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + NEEDED = 2 + + USED = 1 + + class FEATURE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86Features.FEATURE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + IBT = 1 + + SHSTK = 2 + + LAM_U48 = 3 + + LAM_U57 = 4 + + X86 = 5 + + X87 = 6 + + MMX = 7 + + XMM = 8 + + YMM = 9 + + ZMM = 10 + + FXSR = 11 + + XSAVE = 12 + + XSAVEOPT = 13 + + XSAVEC = 14 + + TMM = 15 + + MASK = 16 + +class X86ISA(NoteGnuProperty.Property): + @property + def values(self) -> list[tuple[X86ISA.FLAG, X86ISA.ISA]]: ... + + class FLAG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86ISA.FLAG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + NEEDED = 2 + + USED = 1 + + class ISA(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86ISA.ISA: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + BASELINE = 1 + + V2 = 2 + + V3 = 3 + + V4 = 4 + + CMOV = 5 + + FMA = 6 + + I486 = 7 + + I586 = 8 + + I686 = 9 + + SSE = 10 + + SSE2 = 11 + + SSE3 = 12 + + SSSE3 = 13 + + SSE4_1 = 14 + + SSE4_2 = 15 + + AVX = 16 + + AVX2 = 17 + + AVX512F = 18 + + AVX512CD = 19 + + AVX512ER = 20 + + AVX512PF = 21 + + AVX512VL = 22 + + AVX512DQ = 23 + + AVX512BW = 24 + + AVX512_4FMAPS = 25 + + AVX512_4VNNIW = 26 + + AVX512_BITALG = 27 + + AVX512_IFMA = 28 + + AVX512_VBMI = 29 + + AVX512_VBMI2 = 30 + + AVX512_VNNI = 31 + + AVX512_BF16 = 32 + +class StackSize(NoteGnuProperty.Property): + @property + def stack_size(self) -> int: ... + +class NoteNoCopyOnProtected(NoteGnuProperty.Property): + pass + +class Generic(NoteGnuProperty.Property): + @property + def raw_type(self) -> int: ... + +class AndroidIdent(Note): + sdk_version: int + + ndk_version: str + + ndk_build_number: str + + def __str__(self) -> str: ... + +class NoteAbi(Note): + class ABI(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> NoteAbi.ABI: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + LINUX = 0 + + GNU = 1 + + SOLARIS2 = 2 + + FREEBSD = 3 + + NETBSD = 4 + + SYLLABLE = 5 + + NACL = 6 + + @property + def abi(self) -> Optional[NoteAbi.ABI]: ... + + @property + def version(self) -> Optional[list[int]]: ... + + def __str__(self) -> str: ... + +class CoreAuxv(Note): + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CoreAuxv.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + END = 0 + + IGNORE_TY = 1 + + EXECFD = 2 + + PHDR = 3 + + PHENT = 4 + + PHNUM = 5 + + PAGESZ = 6 + + BASE = 7 + + FLAGS = 8 + + ENTRY = 9 + + NOTELF = 10 + + UID = 11 + + EUID = 12 + + GID = 13 + + EGID = 14 + + TGT_PLATFORM = 15 + + HWCAP = 16 + + CLKTCK = 17 + + FPUCW = 18 + + DCACHEBSIZE = 19 + + ICACHEBSIZE = 20 + + UCACHEBSIZE = 21 + + IGNOREPPC = 22 + + SECURE = 23 + + BASE_PLATFORM = 24 + + RANDOM = 25 + + HWCAP2 = 26 + + EXECFN = 31 + + SYSINFO = 32 + + SYSINFO_EHDR = 33 + + @property + def values(self) -> dict[CoreAuxv.TYPE, int]: ... + + def get(self, type: CoreAuxv.TYPE) -> Optional[int]: ... + + def __getitem__(self, arg: CoreAuxv.TYPE, /) -> Optional[int]: ... + + @overload + def set(self, type: CoreAuxv.TYPE, value: int) -> bool: ... + + @overload + def set(self, arg: Mapping[CoreAuxv.TYPE, int], /) -> bool: ... + + @overload + def __setitem__(self, arg0: CoreAuxv.TYPE, arg1: int, /) -> bool: ... + + @overload + def __setitem__(self, arg: Mapping[CoreAuxv.TYPE, int], /) -> bool: ... + + def __str__(self) -> str: ... + +class CoreFile(Note): + class files_t: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: CoreFile.files_t, /) -> None: ... + + @overload + def __init__(self, arg: Iterable[CoreFile.entry_t], /) -> None: ... + + def __len__(self) -> int: ... + + def __bool__(self) -> bool: ... + + def __repr__(self) -> str: ... + + def __iter__(self) -> Iterator[CoreFile.entry_t]: ... + + @overload + def __getitem__(self, arg: int, /) -> CoreFile.entry_t: ... + + @overload + def __getitem__(self, arg: slice, /) -> CoreFile.files_t | None: ... + + def clear(self) -> None: ... + + def append(self, arg: CoreFile.entry_t, /) -> None: ... + + def insert(self, arg0: int, arg1: CoreFile.entry_t, /) -> None: ... + + def pop(self, index: int = -1) -> CoreFile.entry_t: ... + + def extend(self, arg: CoreFile.files_t, /) -> None: ... + + @overload + def __setitem__(self, arg0: int, arg1: CoreFile.entry_t, /) -> None: ... + + @overload + def __setitem__(self, arg0: slice, arg1: CoreFile.files_t, /) -> None: ... + + @overload + def __delitem__(self, arg: int, /) -> None: ... + + @overload + def __delitem__(self, arg: slice, /) -> None: ... + + class entry_t: + start: int + + end: int + + file_ofs: int + + path: str + + def __str__(self) -> str: ... + + files: CoreFile.files_t + + def __len__(self) -> int: ... + + def __iter__(self) -> Iterator[CoreFile.entry_t]: ... + + def __str__(self) -> str: ... + +class CorePrPsInfo(Note): + class info_t: + state: int + + sname: str + + zombie: bool + + nice: int + + flag: int + + uid: int + + gid: int + + pid: int + + ppid: int + + pgrp: int + + sid: int + + filename: str + + args: str + + @property + def filename_stripped(self) -> str: ... + + @property + def args_stripped(self) -> str: ... + + @property + def info(self) -> Optional[CorePrPsInfo.info_t]: ... + + @info.setter + def info(self, arg: CorePrPsInfo.info_t, /) -> None: ... + + def __str__(self) -> str: ... + +class CoreSigInfo(Note): + @property + def signo(self) -> Optional[int]: ... + + @signo.setter + def signo(self, arg: int, /) -> None: ... + + @property + def sigcode(self) -> Optional[int]: ... + + @sigcode.setter + def sigcode(self, arg: int, /) -> None: ... + + @property + def sigerrno(self) -> Optional[int]: ... + + @sigerrno.setter + def sigerrno(self, arg: int, /) -> None: ... + + def __str__(self) -> str: ... + +class CorePrStatus(Note): + class timeval_t: + sec: int + + usec: int + + class siginfo_t: + sicode: int + + errno: int + + signo: int + + class pr_status_t: + info: CorePrStatus.siginfo_t + + cursig: int + + reserved: int + + sigpend: int + + sighold: int + + pid: int + + ppid: int + + pgrp: int + + sid: int + + utime: CorePrStatus.timeval_t + + stime: CorePrStatus.timeval_t + + cutime: CorePrStatus.timeval_t + + cstime: CorePrStatus.timeval_t + + class Registers: + class X86(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CorePrStatus.Registers.X86: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + EBX = 0 + + ECX = 1 + + EDX = 2 + + ESI = 3 + + EDI = 4 + + EBP = 5 + + EAX = 6 + + DS = 7 + + ES = 8 + + FS = 9 + + GS = 10 + + ORIG_EAX = 11 + + EIP = 12 + + CS = 13 + + EFLAGS = 14 + + ESP = 15 + + SS = 16 + + class X86_64(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CorePrStatus.Registers.X86_64: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + R15 = 0 + + R14 = 1 + + R13 = 2 + + R12 = 3 + + RBP = 4 + + RBX = 5 + + R11 = 6 + + R10 = 7 + + R9 = 8 + + R8 = 9 + + RAX = 10 + + RCX = 11 + + RDX = 12 + + RSI = 13 + + RDI = 14 + + ORIG_RAX = 15 + + RIP = 16 + + CS = 17 + + EFLAGS = 18 + + RSP = 19 + + SS = 20 + + FS_BASE = 21 + + GS_BASE = 22 + + DS = 23 + + ES = 24 + + class ARM(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CorePrStatus.Registers.ARM: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + R0 = 0 + + R1 = 1 + + R2 = 2 + + R3 = 3 + + R4 = 4 + + R5 = 5 + + R6 = 6 + + R7 = 7 + + R8 = 8 + + R9 = 9 + + R10 = 10 + + R11 = 11 + + R12 = 12 + + R13 = 13 + + R14 = 14 + + R15 = 15 + + CPSR = 16 + + class AARCH64(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CorePrStatus.Registers.AARCH64: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + X0 = 0 + + X1 = 1 + + X2 = 2 + + X3 = 3 + + X4 = 4 + + X5 = 5 + + X6 = 6 + + X7 = 7 + + X8 = 8 + + X9 = 9 + + X10 = 10 + + X11 = 11 + + X12 = 12 + + X13 = 13 + + X14 = 14 + + X15 = 15 + + X16 = 16 + + X17 = 17 + + X18 = 18 + + X19 = 19 + + X20 = 20 + + X21 = 21 + + X22 = 22 + + X23 = 23 + + X24 = 24 + + X25 = 25 + + X26 = 26 + + X27 = 27 + + X28 = 28 + + X29 = 29 + + X30 = 30 + + X31 = 31 + + PC = 32 + + PSTATE = 33 + + status: CorePrStatus.pr_status_t + + @property + def architecture(self) -> ARCH: ... + + @property + def pc(self) -> Optional[int]: ... + + @property + def sp(self) -> Optional[int]: ... + + @property + def return_value(self) -> Optional[int]: ... + + @property + def register_values(self) -> list[int]: ... + + @overload + def get(self, reg: CorePrStatus.Registers.X86) -> Optional[int]: ... + + @overload + def get(self, reg: CorePrStatus.Registers.X86_64) -> Optional[int]: ... + + @overload + def get(self, reg: CorePrStatus.Registers.ARM) -> Optional[int]: ... + + @overload + def get(self, reg: CorePrStatus.Registers.AARCH64) -> Optional[int]: ... + + @overload + def __getitem__(self, arg: CorePrStatus.Registers.X86, /) -> Optional[int]: ... + + @overload + def __getitem__(self, arg: CorePrStatus.Registers.X86_64, /) -> Optional[int]: ... + + @overload + def __getitem__(self, arg: CorePrStatus.Registers.ARM, /) -> Optional[int]: ... + + @overload + def __getitem__(self, arg: CorePrStatus.Registers.AARCH64, /) -> Optional[int]: ... + + @overload + def set(self, reg: CorePrStatus.Registers.X86, value: int) -> lief.ok_error_t: ... + + @overload + def set(self, reg: CorePrStatus.Registers.X86_64, value: int) -> lief.ok_error_t: ... + + @overload + def set(self, reg: CorePrStatus.Registers.ARM, value: int) -> lief.ok_error_t: ... + + @overload + def set(self, reg: CorePrStatus.Registers.AARCH64, value: int) -> lief.ok_error_t: ... + + @overload + def __setitem__(self, arg0: CorePrStatus.Registers.X86, arg1: int, /) -> lief.ok_error_t: ... + + @overload + def __setitem__(self, arg0: CorePrStatus.Registers.X86_64, arg1: int, /) -> lief.ok_error_t: ... + + @overload + def __setitem__(self, arg0: CorePrStatus.Registers.ARM, arg1: int, /) -> lief.ok_error_t: ... + + @overload + def __setitem__(self, arg0: CorePrStatus.Registers.AARCH64, arg1: int, /) -> lief.ok_error_t: ... + + def __str__(self) -> str: ... + +class QNXStack(Note): + stack_size: int + + stack_allocated: int + + is_executable: bool + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/MachO.pyi b/vendor/lief/api/python/lief/MachO.pyi new file mode 100644 index 0000000..427b2d5 --- /dev/null +++ b/vendor/lief/api/python/lief/MachO.pyi @@ -0,0 +1,3340 @@ +from collections.abc import Iterator, Sequence +import enum +import io +import os +from typing import Final, Optional, Union, overload + +import lief + +import lief +import lief.objc + + +class MACHO_TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> MACHO_TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + MAGIC = 4277009102 + + CIGAM = 3472551422 + + MAGIC_64 = 4277009103 + + CIGAM_64 = 3489328638 + + MAGIC_FAT = 3405691582 + + CIGAM_FAT = 3199925962 + + NEURAL_MODEL = 3203398350 + +class X86_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + VANILLA = 0 + + PAIR = 1 + + SECTDIFF = 2 + + PB_LA_PTR = 3 + + LOCAL_SECTDIFF = 4 + + TLV = 5 + +class X86_64_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> X86_64_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNSIGNED = 0 + + SIGNED = 1 + + BRANCH = 2 + + GOT_LOAD = 3 + + GOT = 4 + + SUBTRACTOR = 5 + + SIGNED_1 = 6 + + SIGNED_2 = 7 + + SIGNED_4 = 8 + + TLV = 9 + +class PPC_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> PPC_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + VANILLA = 0 + + PAIR = 1 + + BR14 = 2 + + BR24 = 3 + + HI16 = 4 + + LO16 = 5 + + HA16 = 6 + + LO14 = 7 + + SECTDIFF = 8 + + PB_LA_PTR = 9 + + HI16_SECTDIFF = 10 + + LO16_SECTDIFF = 11 + + HA16_SECTDIFF = 12 + + JBSR = 13 + + LO14_SECTDIFF = 14 + + LOCAL_SECTDIFF = 15 + +class ARM_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ARM_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + VANILLA = 0 + + PAIR = 1 + + SECTDIFF = 2 + + LOCAL_SECTDIFF = 3 + + PB_LA_PTR = 4 + + BR24 = 5 + + THUMB_RELOC_BR22 = 6 + + THUMB_32BIT_BRANCH = 7 + + HALF = 8 + + HALF_SECTDIFF = 9 + +class ARM64_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ARM64_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNSIGNED = 0 + + SUBTRACTOR = 1 + + BRANCH26 = 2 + + PAGE21 = 3 + + PAGEOFF12 = 4 + + GOT_LOAD_PAGE21 = 5 + + GOT_LOAD_PAGEOFF12 = 6 + + POINTER_TO_GOT = 7 + + TLVP_LOAD_PAGE21 = 8 + + TLVP_LOAD_PAGEOFF12 = 9 + + ADDEND = 10 + +class DYLD_CHAINED_FORMAT(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DYLD_CHAINED_FORMAT: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + IMPORT = 1 + + IMPORT_ADDEND = 2 + + IMPORT_ADDEND64 = 3 + +class DYLD_CHAINED_PTR_FORMAT(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DYLD_CHAINED_PTR_FORMAT: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + PTR_ARM64E = 1 + + PTR_64 = 2 + + PTR_32 = 3 + + PTR_32_CACHE = 4 + + PTR_32_FIRMWARE = 5 + + PTR_64_OFFSET = 6 + + PTR_ARM64E_KERNEL = 7 + + PTR_64_KERNEL_CACHE = 8 + + PTR_ARM64E_USERLAND = 9 + + PTR_ARM64E_FIRMWARE = 10 + + PTR_X86_64_KERNEL_CACHE = 11 + + PTR_ARM64E_USERLAND24 = 12 + + PTR_ARM64E_SHARED_CACHE = 13 + + PTR_ARM64E_SEGMENTED = 14 + +class ParserConfig: + def __init__(self) -> None: ... + + parse_dyld_exports: bool + + parse_dyld_bindings: bool + + parse_dyld_rebases: bool + + fix_from_memory: bool + + from_dyld_shared_cache: bool + + def full_dyldinfo(self, flag: bool) -> ParserConfig: ... + + deep: Final[ParserConfig] = ... + + quick: Final[ParserConfig] = ... + +def parse_from_memory(address: int, config: ParserConfig = ...) -> Optional[FatBinary]: ... + +def parse_from_dump(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], addr: int, config: ParserConfig = ...) -> Optional[FatBinary]: ... + +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], config: ParserConfig = ...) -> Optional[FatBinary]: ... + +class ChainedPointerAnalysis: + class dyld_chained_ptr_arm64e_rebase_t: + @property + def unpack_target(self) -> int: ... + + @property + def target(self) -> int: ... + + @property + def high8(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_bind_t: + @property + def ordinal(self) -> int: ... + + @property + def zero(self) -> int: ... + + @property + def addend(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_auth_rebase_t: + @property + def target(self) -> int: ... + + @property + def diversity(self) -> int: ... + + @property + def addr_div(self) -> int: ... + + @property + def key(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> int: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_auth_bind_t: + @property + def ordinal(self) -> int: ... + + @property + def zero(self) -> int: ... + + @property + def diversity(self) -> int: ... + + @property + def addr_div(self) -> int: ... + + @property + def key(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_64_rebase_t: + @property + def unpack_target(self) -> int: ... + + @property + def target(self) -> int: ... + + @property + def high8(self) -> int: ... + + @property + def reserved(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_bind24_t: + @property + def ordinal(self) -> int: ... + + @property + def zero(self) -> int: ... + + @property + def addend(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_auth_bind24_t: + @property + def ordinal(self) -> int: ... + + @property + def zero(self) -> int: ... + + @property + def diversity(self) -> int: ... + + @property + def addr_div(self) -> int: ... + + @property + def key(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_64_bind_t: + @property + def ordinal(self) -> int: ... + + @property + def addend(self) -> int: ... + + @property + def reserved(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_64_kernel_cache_rebase_t: + @property + def ordinal(self) -> int: ... + + @property + def cache_level(self) -> int: ... + + @property + def diversity(self) -> int: ... + + @property + def addr_div(self) -> int: ... + + @property + def key(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def is_auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_32_rebase_t: + @property + def target(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> int: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_32_bind_t: + @property + def ordinal(self) -> int: ... + + @property + def addend(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def bind(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_32_cache_rebase_t: + @property + def target(self) -> int: ... + + @property + def next(self) -> int: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_32_firmware_rebase_t: + @property + def target(self) -> int: ... + + @property + def next(self) -> int: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_segmented_rebase_t: + @property + def target_seg_offset(self) -> int: ... + + @property + def target_seg_index(self) -> int: ... + + @property + def padding(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class dyld_chained_ptr_arm64e_auth_segmented_rebase_t: + @property + def target_seg_offset(self) -> int: ... + + @property + def target_seg_index(self) -> int: ... + + @property + def diversity(self) -> int: ... + + @property + def addr_div(self) -> int: ... + + @property + def key(self) -> int: ... + + @property + def next(self) -> int: ... + + @property + def auth(self) -> bool: ... + + def __str__(self) -> str: ... + + @staticmethod + def stride(fmt: DYLD_CHAINED_PTR_FORMAT) -> int: ... + + @staticmethod + def from_value(ptr: int, size: int) -> Optional[ChainedPointerAnalysis]: ... + + @property + def value(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def dyld_chained_ptr_arm64e_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_rebase_t: ... + + @property + def dyld_chained_ptr_arm64e_bind(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind_t: ... + + @property + def dyld_chained_ptr_arm64e_auth_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_rebase_t: ... + + @property + def dyld_chained_ptr_arm64e_auth_bind(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind_t: ... + + @property + def dyld_chained_ptr_64_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_64_rebase_t: ... + + @property + def dyld_chained_ptr_arm64e_bind24(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind24_t: ... + + @property + def dyld_chained_ptr_arm64e_auth_bind24(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind24_t: ... + + @property + def dyld_chained_ptr_64_bind(self) -> ChainedPointerAnalysis.dyld_chained_ptr_64_bind_t: ... + + @property + def dyld_chained_ptr_64_kernel_cache_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_64_kernel_cache_rebase_t: ... + + @property + def dyld_chained_ptr_32_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_32_rebase_t: ... + + @property + def dyld_chained_ptr_32_bind(self) -> ChainedPointerAnalysis.dyld_chained_ptr_32_bind_t: ... + + @property + def dyld_chained_ptr_32_cache_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_32_cache_rebase_t: ... + + @property + def dyld_chained_ptr_32_firmware_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_32_firmware_rebase_t: ... + + @property + def dyld_chained_ptr_arm64e_segmented_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_segmented_rebase_t: ... + + @property + def dyld_chained_ptr_arm64e_auth_segmented_rebase(self) -> ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_segmented_rebase_t: ... + + def get_as(self, arg: DYLD_CHAINED_PTR_FORMAT, /) -> Union[lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind24_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind24_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_bind_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_kernel_cache_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_bind_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_cache_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_firmware_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_segmented_rebase_t, lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_segmented_rebase_t, int, None]: ... + +class FatBinary: + class it_binaries: + def __getitem__(self, arg: int, /) -> Binary: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FatBinary.it_binaries: ... + + def __next__(self) -> Binary: ... + + @staticmethod + def create(binaries: Sequence[Optional[Binary]]) -> Optional[FatBinary]: ... + + @property + def size(self) -> int: ... + + def at(self, index: int) -> Binary | None: ... + + def take(self, cpu: Header.CPU_TYPE) -> Optional[Binary]: ... + + def write(self, filename: Union[str | os.PathLike]) -> None: ... + + def raw(self) -> list[int]: ... + + def get(self, arg: Header.CPU_TYPE, /) -> Binary | None: ... + + def __len__(self) -> int: ... + + @overload + def __getitem__(self, arg: int, /) -> Binary | None: ... + + @overload + def __getitem__(self, arg: Header.CPU_TYPE, /) -> Binary | None: ... + + def __iter__(self) -> FatBinary.it_binaries: ... + + def __str__(self) -> str: ... + +class Binary(lief.Binary): + class it_commands: + def __getitem__(self, arg: int, /) -> LoadCommand: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_commands: ... + + def __next__(self) -> LoadCommand: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_filter_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_filter_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_sections: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_sections: ... + + def __next__(self) -> Section: ... + + class it_segments: + def __getitem__(self, arg: int, /) -> SegmentCommand: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_segments: ... + + def __next__(self) -> SegmentCommand: ... + + class it_libraries: + def __getitem__(self, arg: int, /) -> DylibCommand: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_libraries: ... + + def __next__(self) -> DylibCommand: ... + + class it_lazy_load_dylib_info: + def __getitem__(self, arg: int, /) -> LazyLoadDylibInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_lazy_load_dylib_info: ... + + def __next__(self) -> LazyLoadDylibInfo: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class it_rpaths: + def __getitem__(self, arg: int, /) -> RPathCommand: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_rpaths: ... + + def __next__(self) -> RPathCommand: ... + + class it_sub_clients: + def __getitem__(self, arg: int, /) -> SubClient: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_sub_clients: ... + + def __next__(self) -> SubClient: ... + + class it_notes: + def __getitem__(self, arg: int, /) -> NoteCommand: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_notes: ... + + def __next__(self) -> NoteCommand: ... + + class range_t: + start: int + + end: int + + @property + def header(self) -> Header: ... # type: ignore + + @property + def sections(self) -> Binary.it_sections: ... # type: ignore + + @property + def relocations(self) -> Binary.it_relocations: ... # type: ignore + + @property + def segments(self) -> Binary.it_segments: ... + + @property + def libraries(self) -> Binary.it_libraries: ... # type: ignore + + @property + def lazy_load_dylib_infos(self) -> Binary.it_lazy_load_dylib_info: ... + + @property + def symbols(self) -> Binary.it_symbols: ... # type: ignore + + def has_symbol(self, name: str) -> bool: ... # type: ignore + + def get_symbol(self, name: str) -> Symbol | None: ... # type: ignore + + @property + def imported_symbols(self) -> Binary.it_filter_symbols: ... + + @property + def exported_symbols(self) -> Binary.it_filter_symbols: ... + + @property + def commands(self) -> Binary.it_commands: ... + + @property + def filesets(self) -> FatBinary.it_binaries: ... + + @property + def has_filesets(self) -> bool: ... + + @property + def fileset_name(self) -> str: ... + + @property + def fileset_addr(self) -> int: ... + + @property + def imagebase(self) -> int: ... + + @property + def virtual_size(self) -> int: ... + + @property + def fat_offset(self) -> int: ... + + def section_from_offset(self, arg: int, /) -> Section | None: ... + + def section_from_virtual_address(self, arg: int, /) -> Section | None: ... + + def segment_from_offset(self, arg: int, /) -> SegmentCommand | None: ... + + def segment_from_virtual_address(self, arg: int, /) -> SegmentCommand | None: ... + + @property + def has_entrypoint(self) -> bool: ... + + @property + def has_uuid(self) -> bool: ... + + @property + def uuid(self) -> UUIDCommand | None: ... + + @property + def has_main_command(self) -> bool: ... + + @property + def main_command(self) -> MainCommand | None: ... + + @property + def has_dylinker(self) -> bool: ... + + @property + def dylinker(self) -> DylinkerCommand | None: ... + + @property + def has_dyld_info(self) -> bool: ... + + @property + def dyld_info(self) -> DyldInfo | None: ... + + @property + def has_function_starts(self) -> bool: ... + + @property + def function_starts(self) -> FunctionStarts | None: ... + + @property + def has_source_version(self) -> bool: ... + + @property + def source_version(self) -> SourceVersion | None: ... + + @property + def has_version_min(self) -> bool: ... + + @property + def version_min(self) -> VersionMin | None: ... + + @property + def has_routine_command(self) -> bool: ... + + @property + def routine_command(self) -> Routine | None: ... + + @property + def has_thread_command(self) -> bool: ... + + @property + def thread_command(self) -> ThreadCommand | None: ... + + @property + def has_rpath(self) -> bool: ... + + @property + def rpath(self) -> RPathCommand | None: ... + + @property + def rpaths(self) -> Binary.it_rpaths: ... + + @property + def has_symbol_command(self) -> bool: ... # type: ignore + + @property + def symbol_command(self) -> SymbolCommand | None: ... + + @property + def has_dynamic_symbol_command(self) -> bool: ... + + @property + def dynamic_symbol_command(self) -> DynamicSymbolCommand | None: ... + + @property + def has_code_signature(self) -> bool: ... + + @property + def code_signature(self) -> CodeSignature | None: ... + + @property + def has_code_signature_dir(self) -> bool: ... + + @property + def code_signature_dir(self) -> CodeSignatureDir | None: ... + + @property + def has_data_in_code(self) -> bool: ... + + @property + def data_in_code(self) -> DataInCode | None: ... + + @property + def has_segment_split_info(self) -> bool: ... + + @property + def segment_split_info(self) -> SegmentSplitInfo | None: ... + + @property + def subclients(self) -> Binary.it_sub_clients: ... + + @property + def has_subclients(self) -> bool: ... + + @property + def has_sub_framework(self) -> bool: ... + + @property + def sub_framework(self) -> SubFramework | None: ... + + @property + def has_dyld_environment(self) -> bool: ... + + @property + def dyld_environment(self) -> DyldEnvironment | None: ... + + @property + def has_encryption_info(self) -> bool: ... + + @property + def encryption_info(self) -> EncryptionInfo | None: ... + + @property + def has_build_version(self) -> bool: ... + + @property + def platform(self) -> BuildVersion.PLATFORMS: ... + + @property + def is_ios(self) -> bool: ... + + @property + def is_macos(self) -> bool: ... + + @property + def build_version(self) -> BuildVersion | None: ... + + @property + def has_dyld_chained_fixups(self) -> bool: ... + + @property + def dyld_chained_fixups(self) -> DyldChainedFixups | None: ... + + @property + def has_dyld_exports_trie(self) -> bool: ... + + @property + def dyld_exports_trie(self) -> DyldExportsTrie | None: ... + + @property + def has_two_level_hints(self) -> bool: ... + + @property + def two_level_hints(self) -> TwoLevelHints | None: ... + + @property + def has_linker_opt_hint(self) -> bool: ... + + @property + def linker_opt_hint(self) -> LinkerOptHint | None: ... + + @property + def has_atom_info(self) -> bool: ... + + @property + def atom_info(self) -> AtomInfo | None: ... + + @property + def has_function_variants(self) -> bool: ... + + @property + def function_variants(self) -> FunctionVariants | None: ... + + @property + def has_function_variant_fixups(self) -> bool: ... + + @property + def function_variant_fixups(self) -> FunctionVariantFixups | None: ... + + def virtual_address_to_offset(self, virtual_address: int) -> Union[int, lief.lief_errors]: ... + + def has_section(self, name: str) -> bool: ... + + @overload + def get_section(self, name: str) -> Section | None: ... + + @overload + def get_section(self, segname: str, secname: str) -> Section | None: ... + + def has_segment(self, name: str) -> bool: ... + + def get_segment(self, name: str) -> SegmentCommand | None: ... + + @property + def va_ranges(self) -> Binary.range_t: ... + + @property + def off_ranges(self) -> Binary.range_t: ... + + @property + def tlv_initial_content_range(self) -> Binary.range_t: ... + + def is_valid_addr(self, address: int) -> bool: ... + + @overload + def write(self, output: Union[str | os.PathLike]) -> None: ... + + @overload + def write(self, output: Union[str | os.PathLike], config: Builder.config_t) -> None: ... + + @overload + def write_to_bytes(self, config: Builder.config_t) -> bytes: ... + + @overload + def write_to_bytes(self) -> bytes: ... + + @overload + def add(self, dylib_command: DylibCommand) -> LoadCommand | None: ... + + @overload + def add(self, segment: SegmentCommand) -> LoadCommand | None: ... + + @overload + def add(self, load_command: LoadCommand) -> LoadCommand | None: ... + + @overload + def add(self, load_command: LoadCommand, index: int) -> LoadCommand | None: ... + + @overload + def remove(self, load_command: LoadCommand) -> bool: ... + + @overload + def remove(self, type: LoadCommand.TYPE) -> bool: ... + + @overload + def remove(self, symbol: Symbol) -> bool: ... + + def remove_command(self, index: int) -> bool: ... + + @overload + def remove_section(self, name: str, clear: bool = False) -> None: ... + + @overload + def remove_section(self, segname: str, secname: str, clear: bool = False) -> None: ... + + def remove_signature(self) -> bool: ... + + def remove_symbol(self, name: str) -> bool: ... + + def can_remove(self, symbol: Symbol) -> bool: ... + + def can_remove_symbol(self, symbol_name: str) -> bool: ... + + @overload + def unexport(self, name: str) -> bool: ... + + @overload + def unexport(self, symbol: Symbol) -> bool: ... + + def extend(self, load_command: LoadCommand, size: int) -> bool: ... + + def extend_segment(self, segment_command: SegmentCommand, size: int) -> bool: ... + + @overload + def add_section(self, segment: SegmentCommand, section: Section) -> Section | None: ... + + @overload + def add_section(self, section: Section) -> Section | None: ... + + def find_library(self, name: str) -> DylibCommand | None: ... + + def extend_section(self, section: Section, size: int) -> bool: ... + + def add_library(self, library_name: str) -> LoadCommand | None: ... + + def get(self, type: LoadCommand.TYPE) -> LoadCommand | None: ... + + def has(self, type: LoadCommand.TYPE) -> bool: ... + + @property + def unwind_functions(self) -> list[lief.Function]: ... + + @property + def functions(self) -> list[lief.Function]: ... + + def shift(self, value: int) -> Union[lief.ok_t, lief.lief_errors]: ... + + def shift_linkedit(self, value: int) -> Union[lief.ok_t, lief.lief_errors]: ... + + def add_exported_function(self, address: int, name: str) -> ExportInfo | None: ... + + def add_local_symbol(self, address: int, name: str) -> Symbol | None: ... + + @property + def bindings(self) -> Iterator[BindingInfo]: ... + + @property + def symbol_stubs(self) -> Sequence[Stub]: ... + + @property + def has_nx_heap(self) -> bool: ... + + @property + def has_nx_stack(self) -> bool: ... + + @property + def support_arm64_ptr_auth(self) -> bool: ... + + @property + def objc_metadata(self) -> Optional[lief.objc.Metadata]: ... + + @property + def notes(self) -> Binary.it_notes: ... + + @property + def has_notes(self) -> bool: ... + + def __getitem__(self, arg: LoadCommand.TYPE, /) -> LoadCommand | None: ... + + def __contains__(self, arg: LoadCommand.TYPE, /) -> bool: ... + + @property + def overlay(self) -> memoryview: ... + + @property + def available_command_space(self) -> int: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + def __init__(self) -> None: ... + + class CPU_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.CPU_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + ANY = -1 + + X86 = 7 + + X86_64 = 16777223 + + MIPS = 8 + + MC98000 = 10 + + HPPA = 11 + + ARM = 12 + + ARM64 = 16777228 + + MC88000 = 13 + + SPARC = 14 + + I860 = 15 + + ALPHA = 16 + + POWERPC = 18 + + POWERPC64 = 16777234 + + APPLE_GPU = 16777235 + + AMD_GPU = 16777236 + + INTEL_GPU = 16777237 + + AIR64 = 16777239 + + class FILE_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.FILE_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + OBJECT = 1 + + EXECUTE = 2 + + FVMLIB = 3 + + CORE = 4 + + PRELOAD = 5 + + DYLIB = 6 + + DYLINKER = 7 + + BUNDLE = 8 + + DYLIB_STUB = 9 + + DSYM = 10 + + KEXT_BUNDLE = 11 + + FILESET = 12 + + GPU_EXECUTE = 13 + + GPU_DYLIB = 14 + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Header.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NOUNDEFS = 1 + + INCRLINK = 2 + + DYLDLINK = 4 + + BINDATLOAD = 8 + + PREBOUND = 16 + + SPLIT_SEGS = 32 + + LAZY_INIT = 64 + + TWOLEVEL = 128 + + FORCE_FLAT = 256 + + NOMULTIDEFS = 512 + + NOFIXPREBINDING = 1024 + + PREBINDABLE = 2048 + + ALLMODSBOUND = 4096 + + SUBSECTIONS_VIA_SYMBOLS = 8192 + + CANONICAL = 16384 + + WEAK_DEFINES = 32768 + + BINDS_TO_WEAK = 65536 + + ALLOW_STACK_EXECUTION = 131072 + + ROOT_SAFE = 262144 + + SETUID_SAFE = 524288 + + NO_REEXPORTED_DYLIBS = 1048576 + + PIE = 2097152 + + DEAD_STRIPPABLE_DYLIB = 4194304 + + HAS_TLV_DESCRIPTORS = 8388608 + + NO_HEAP_EXECUTION = 16777216 + + APP_EXTENSION_SAFE = 33554432 + + NLIST_OUTOFSYNC_WITH_DYLDINFO = 67108864 + + SIM_SUPPORT = 134217728 + + IMPLICIT_PAGEZERO = 268435456 + + DYLIB_IN_CACHE = 2147483648 + + magic: MACHO_TYPES + + cpu_type: Header.CPU_TYPE + + cpu_subtype: int + + file_type: Header.FILE_TYPE + + flags: int + + nb_cmds: int + + sizeof_cmds: int + + reserved: int + + @property + def flags_list(self) -> list[Header.FLAGS]: ... + + @property + def is_32bit(self) -> bool: ... + + @property + def is_64bit(self) -> bool: ... + + def add(self, flag: Header.FLAGS) -> None: ... + + def remove(self, flag: Header.FLAGS) -> None: ... + + def has(self, flag: Header.FLAGS) -> bool: ... + + def __iadd__(self, arg: Header.FLAGS, /) -> Header: ... + + def __isub__(self, arg: Header.FLAGS, /) -> Header: ... + + def __contains__(self, arg: Header.FLAGS, /) -> bool: ... + + def __str__(self) -> str: ... + +class LoadCommand(lief.Object): + def __init__(self) -> None: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> LoadCommand.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + SEGMENT = 1 + + SYMTAB = 2 + + SYMSEG = 3 + + THREAD = 4 + + UNIXTHREAD = 5 + + LOADFVMLIB = 6 + + IDFVMLIB = 7 + + IDENT = 8 + + FVMFILE = 9 + + PREPAGE = 10 + + DYSYMTAB = 11 + + LOAD_DYLIB = 12 + + ID_DYLIB = 13 + + LOAD_DYLINKER = 14 + + ID_DYLINKER = 15 + + PREBOUND_DYLIB = 16 + + ROUTINES = 17 + + SUB_FRAMEWORK = 18 + + SUB_UMBRELLA = 19 + + SUB_CLIENT = 20 + + SUB_LIBRARY = 21 + + TWOLEVEL_HINTS = 22 + + PREBIND_CKSUM = 23 + + LOAD_WEAK_DYLIB = 2147483672 + + SEGMENT_64 = 25 + + ROUTINES_64 = 26 + + UUID = 27 + + RPATH = 2147483676 + + CODE_SIGNATURE = 29 + + SEGMENT_SPLIT_INFO = 30 + + REEXPORT_DYLIB = 2147483679 + + LAZY_LOAD_DYLIB = 32 + + ENCRYPTION_INFO = 33 + + DYLD_INFO = 34 + + DYLD_INFO_ONLY = 2147483682 + + LOAD_UPWARD_DYLIB = 2147483683 + + VERSION_MIN_MACOSX = 36 + + VERSION_MIN_IPHONEOS = 37 + + FUNCTION_STARTS = 38 + + DYLD_ENVIRONMENT = 39 + + MAIN = 2147483688 + + DATA_IN_CODE = 41 + + SOURCE_VERSION = 42 + + DYLIB_CODE_SIGN_DRS = 43 + + ENCRYPTION_INFO_64 = 44 + + LINKER_OPTION = 45 + + LINKER_OPTIMIZATION_HINT = 46 + + VERSION_MIN_TVOS = 47 + + VERSION_MIN_WATCHOS = 48 + + NOTE = 49 + + BUILD_VERSION = 50 + + DYLD_EXPORTS_TRIE = 2147483699 + + DYLD_CHAINED_FIXUPS = 2147483700 + + FILESET_ENTRY = 2147483701 + + ATOM_INFO = 54 + + FUNCTION_VARIANTS = 55 + + FUNCTION_VARIANT_FIXUPS = 56 + + TARGET_TRIPLE = 57 + + LAZY_LOAD_DYLIB_INFO = 58 + + LIEF_UNKNOWN = 4293787649 + + command: LoadCommand.TYPE + + size: int + + @property + def data(self) -> memoryview: ... + + @data.setter + def data(self, arg: Sequence[int], /) -> None: ... + + command_offset: int + + def __str__(self) -> str: ... + +class UUIDCommand(LoadCommand): + @property + def uuid(self) -> list[int]: ... + + @uuid.setter + def uuid(self, arg: Sequence[int], /) -> None: ... + + def __str__(self) -> str: ... + +class SymbolCommand(LoadCommand): + def __init__(self) -> None: ... + + symbol_offset: int + + numberof_symbols: int + + strings_offset: int + + strings_size: int + + def __str__(self) -> str: ... + +class SegmentCommand(LoadCommand): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: str, /) -> None: ... + + @overload + def __init__(self, arg0: str, arg1: Sequence[int], /) -> None: ... + + class it_sections: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> SegmentCommand.it_sections: ... + + def __next__(self) -> Section: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> SegmentCommand.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class VM_PROTECTIONS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> SegmentCommand.VM_PROTECTIONS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + R = 1 + + W = 2 + + X = 4 + + class FLAGS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> SegmentCommand.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + HIGHVM = 1 + + FVMLIB = 2 + + NORELOC = 4 + + PROTECTED_VERSION_1 = 8 + + READ_ONLY = 16 + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + virtual_address: int + + virtual_size: int + + file_size: int + + file_offset: int + + max_protection: int + + init_protection: int + + numberof_sections: int + + @property + def sections(self) -> SegmentCommand.it_sections: ... + + @property + def relocations(self) -> SegmentCommand.it_relocations: ... + + @property + def index(self) -> int: ... + + @property + def content(self) -> memoryview: ... + + @content.setter + def content(self, arg: Sequence[int], /) -> None: ... + + flags: int + + def has(self, section: Section) -> bool: ... + + def has_section(self, section_name: str) -> bool: ... + + def add_section(self, section: Section) -> Section: ... + + def get_section(self, name: str) -> Section | None: ... + + def __str__(self) -> str: ... + +class LinkEdit(SegmentCommand): + pass + +class Section(lief.Section): + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Section.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Section.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + REGULAR = 0 + + ZEROFILL = 1 + + CSTRING_LITERALS = 2 + + IS_4BYTE_LITERALS = 3 + + IS_8BYTE_LITERALS = 4 + + LITERAL_POINTERS = 5 + + NON_LAZY_SYMBOL_POINTERS = 6 + + LAZY_SYMBOL_POINTERS = 7 + + SYMBOL_STUBS = 8 + + MOD_INIT_FUNC_POINTERS = 9 + + MOD_TERM_FUNC_POINTERS = 10 + + COALESCED = 11 + + GB_ZEROFILL = 12 + + INTERPOSING = 13 + + IS_16BYTE_LITERALS = 14 + + DTRACE_DOF = 15 + + LAZY_DYLIB_SYMBOL_POINTERS = 16 + + THREAD_LOCAL_REGULAR = 17 + + THREAD_LOCAL_ZEROFILL = 18 + + THREAD_LOCAL_VARIABLES = 19 + + THREAD_LOCAL_VARIABLE_POINTERS = 20 + + THREAD_LOCAL_INIT_FUNCTION_POINTERS = 21 + + INIT_FUNC_OFFSETS = 22 + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Section.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + PURE_INSTRUCTIONS = 2147483648 + + NO_TOC = 1073741824 + + STRIP_STATIC_SYMS = 536870912 + + NO_DEAD_STRIP = 268435456 + + LIVE_SUPPORT = 134217728 + + SELF_MODIFYING_CODE = 67108864 + + DEBUG_INFO = 33554432 + + SOME_INSTRUCTIONS = 1024 + + EXT_RELOC = 512 + + LOC_RELOC = 256 + + @overload + @staticmethod + def create(name: str, content: Sequence[int], type: Section.TYPE = Section.TYPE.REGULAR) -> Optional[Section]: ... + + @overload + @staticmethod + def create(name: str, type: Section.TYPE = Section.TYPE.REGULAR) -> Optional[Section]: ... + + alignment: int + + relocation_offset: int + + numberof_relocations: int + + type: Section.TYPE + + @property + def relocations(self) -> SegmentCommand.it_relocations: ... + + reserved1: int + + reserved2: int + + reserved3: int + + @property + def flags(self) -> Section.FLAGS: ... + + @flags.setter + def flags(self, arg: int, /) -> None: ... + + @property + def flags_list(self) -> list[Section.FLAGS]: ... + + @property + def segment(self) -> SegmentCommand | None: ... + + segment_name: str + + @property + def has_segment(self) -> bool: ... + + def has(self, flag: Section.FLAGS) -> bool: ... + + def add(self, flag: Section.FLAGS) -> None: ... + + def remove(self, flag: Section.FLAGS) -> None: ... + + def __iadd__(self, arg: Section.FLAGS, /) -> Section: ... + + def __isub__(self, arg: Section.FLAGS, /) -> Section: ... + + def __contains__(self, arg: Section.FLAGS, /) -> bool: ... + + def __str__(self) -> str: ... + +class MainCommand(LoadCommand): + def __init__(self, arg0: int, arg1: int, /) -> None: ... + + entrypoint: int + + stack_size: int + + def __str__(self) -> str: ... + +class NoteCommand(LoadCommand): + note_offset: int + + note_size: int + + @property + def owner_str(self) -> str: ... + + @property + def owner(self) -> memoryview: ... + + @owner.setter + def owner(self, arg: bytes, /) -> None: ... + + def __str__(self) -> str: ... + +class DynamicSymbolCommand(LoadCommand): + class it_indirect_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicSymbolCommand.it_indirect_symbols: ... + + def __next__(self) -> Symbol: ... + + idx_local_symbol: int + + nb_local_symbols: int + + idx_external_define_symbol: int + + nb_external_define_symbols: int + + idx_undefined_symbol: int + + nb_undefined_symbols: int + + toc_offset: int + + nb_toc: int + + module_table_offset: int + + nb_module_table: int + + external_reference_symbol_offset: int + + nb_external_reference_symbols: int + + indirect_symbol_offset: int + + nb_indirect_symbols: int + + external_relocation_offset: int + + nb_external_relocations: int + + local_relocation_offset: int + + nb_local_relocations: int + + @property + def indirect_symbols(self) -> DynamicSymbolCommand.it_indirect_symbols: ... + + def __str__(self) -> str: ... + +class DylinkerCommand(LoadCommand): + def __init__(self, arg: str, /) -> None: ... + + name: str + + def __str__(self) -> str: ... + +class DyldInfo(LoadCommand): + class REBASE_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DyldInfo.REBASE_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + POINTER = 1 + + TEXT_ABSOLUTE32 = 2 + + TEXT_PCREL32 = 3 + + THREADED = 102 + + class REBASE_OPCODES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DyldInfo.REBASE_OPCODES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DONE = 0 + + SET_TYPE_IMM = 16 + + SET_SEGMENT_AND_OFFSET_ULEB = 32 + + ADD_ADDR_ULEB = 48 + + ADD_ADDR_IMM_SCALED = 64 + + DO_REBASE_IMM_TIMES = 80 + + DO_REBASE_ULEB_TIMES = 96 + + DO_REBASE_ADD_ADDR_ULEB = 112 + + DO_REBASE_ULEB_TIMES_SKIPPING_ULEB = 128 + + class BIND_OPCODES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DyldInfo.BIND_OPCODES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DONE = 0 + + SET_DYLIB_ORDINAL_IMM = 16 + + SET_DYLIB_ORDINAL_ULEB = 32 + + SET_DYLIB_SPECIAL_IMM = 48 + + SET_SYMBOL_TRAILING_FLAGS_IMM = 64 + + SET_TYPE_IMM = 80 + + SET_ADDEND_SLEB = 96 + + SET_SEGMENT_AND_OFFSET_ULEB = 112 + + ADD_ADDR_ULEB = 128 + + DO_BIND = 144 + + DO_BIND_ADD_ADDR_ULEB = 160 + + DO_BIND_ADD_ADDR_IMM_SCALED = 176 + + DO_BIND_ULEB_TIMES_SKIPPING_ULEB = 192 + + THREADED_APPLY = 209 + + THREADED = 208 + + class it_binding_info: + def __getitem__(self, arg: int, /) -> DyldBindingInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DyldInfo.it_binding_info: ... + + def __next__(self) -> DyldBindingInfo: ... + + class it_export_info: + def __getitem__(self, arg: int, /) -> ExportInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DyldInfo.it_export_info: ... + + def __next__(self) -> ExportInfo: ... + + rebase: tuple[int, int] + + @property + def rebase_opcodes(self) -> memoryview: ... + + @rebase_opcodes.setter + def rebase_opcodes(self, arg: Sequence[int], /) -> None: ... + + @property + def show_rebases_opcodes(self) -> str: ... + + bind: tuple[int, int] + + @property + def bind_opcodes(self) -> memoryview: ... + + @bind_opcodes.setter + def bind_opcodes(self, arg: Sequence[int], /) -> None: ... + + @property + def show_bind_opcodes(self) -> str: ... + + weak_bind: tuple[int, int] + + @property + def weak_bind_opcodes(self) -> memoryview: ... + + @weak_bind_opcodes.setter + def weak_bind_opcodes(self, arg: Sequence[int], /) -> None: ... + + @property + def show_weak_bind_opcodes(self) -> str: ... + + lazy_bind: tuple[int, int] + + @property + def lazy_bind_opcodes(self) -> memoryview: ... + + @lazy_bind_opcodes.setter + def lazy_bind_opcodes(self, arg: Sequence[int], /) -> None: ... + + @property + def show_lazy_bind_opcodes(self) -> str: ... + + @property + def bindings(self) -> DyldInfo.it_binding_info: ... + + export_info: tuple[int, int] + + @property + def export_trie(self) -> memoryview: ... + + @export_trie.setter + def export_trie(self, arg: Sequence[int], /) -> None: ... + + @property + def exports(self) -> DyldExportsTrie.it_export_info: ... + + @property + def show_export_trie(self) -> str: ... + + def set_rebase_offset(self, offset: int) -> None: ... + + def set_rebase_size(self, size: int) -> None: ... + + def set_bind_offset(self, offset: int) -> None: ... + + def set_bind_size(self, size: int) -> None: ... + + def set_weak_bind_offset(self, offset: int) -> None: ... + + def set_weak_bind_size(self, size: int) -> None: ... + + def set_lazy_bind_offset(self, offset: int) -> None: ... + + def set_lazy_bind_size(self, size: int) -> None: ... + + def set_export_offset(self, offset: int) -> None: ... + + def set_export_size(self, size: int) -> None: ... + + def __str__(self) -> str: ... + +class DyldChainedFixups(LoadCommand): + class it_binding_info: + def __getitem__(self, arg: int, /) -> ChainedBindingInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DyldChainedFixups.it_binding_info: ... + + def __next__(self) -> ChainedBindingInfo: ... + + class it_chained_starts_in_segments_t: + def __getitem__(self, arg: int, /) -> DyldChainedFixups.chained_starts_in_segment: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DyldChainedFixups.it_chained_starts_in_segments_t: ... + + def __next__(self) -> DyldChainedFixups.chained_starts_in_segment: ... + + class chained_starts_in_segment: + @property + def offset(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def page_size(self) -> int: ... + + @property + def segment_offset(self) -> int: ... + + @property + def page_start(self) -> list[int]: ... + + @property + def pointer_format(self) -> DYLD_CHAINED_PTR_FORMAT: ... + + @property + def max_valid_pointer(self) -> int: ... + + @property + def page_count(self) -> int: ... + + @property + def segment(self) -> SegmentCommand | None: ... + + def __str__(self) -> str: ... + + data_offset: int + + data_size: int + + @property + def payload(self) -> memoryview: ... + + @property + def bindings(self) -> DyldChainedFixups.it_binding_info: ... + + @property + def chained_starts_in_segments(self) -> DyldChainedFixups.it_chained_starts_in_segments_t: ... + + fixups_version: int + + starts_offset: int + + imports_offset: int + + symbols_offset: int + + imports_count: int + + symbols_format: int + + imports_format: DYLD_CHAINED_FORMAT + + def __str__(self) -> str: ... + +class DyldExportsTrie(LoadCommand): + class it_export_info: + def __getitem__(self, arg: int, /) -> ExportInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DyldExportsTrie.it_export_info: ... + + def __next__(self) -> ExportInfo: ... + + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + @property + def exports(self) -> DyldExportsTrie.it_export_info: ... + + def show_export_trie(self) -> str: ... + + def __str__(self) -> str: ... + +class DylibCommand(LoadCommand): + name: str + + @property + def name_offset(self) -> int: ... + + timestamp: int + + @property + def current_version(self) -> list[int]: ... + + @current_version.setter + def current_version(self, arg: Sequence[int], /) -> None: ... + + @property + def compatibility_version(self) -> list[int]: ... + + @compatibility_version.setter + def compatibility_version(self, arg: Sequence[int], /) -> None: ... + + @staticmethod + def weak_lib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + @staticmethod + def id_dylib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + @staticmethod + def load_dylib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + @staticmethod + def reexport_dylib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + @staticmethod + def load_upward_dylib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + @staticmethod + def lazy_load_dylib(name: str, timestamp: int = 0, current_version: int = 0, compat_version: int = 0) -> DylibCommand: ... + + def __str__(self) -> str: ... + +class ThreadCommand(LoadCommand): + def __init__(self, arg0: int, arg1: int, arg2: Header.CPU_TYPE, /) -> None: ... + + flavor: int + + @property + def state(self) -> memoryview: ... + + @state.setter + def state(self, arg: Sequence[int], /) -> None: ... + + count: int + + @property + def pc(self) -> int: ... + + architecture: Header.CPU_TYPE + + def __str__(self) -> str: ... + +class ThreadLocalVariables(Section): + class Thunk: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, func: int, key: int, offset: int) -> None: ... + + func: int + + key: int + + offset: int + + def __str__(self) -> str: ... + + @property + def thunks(self) -> Sequence[ThreadLocalVariables.Thunk]: ... + + @property + def nb_thunks(self) -> int: ... + + def get(self, idx: int) -> ThreadLocalVariables.Thunk | None: ... + + def set(self, idx: int, thunk: ThreadLocalVariables.Thunk) -> None: ... + + def __getitem__(self, idx: int) -> ThreadLocalVariables.Thunk | None: ... + + def __setitem__(self, idx: int, thunk: ThreadLocalVariables.Thunk) -> None: ... + +class RPathCommand(LoadCommand): + @staticmethod + def create(path: str) -> Optional[RPathCommand]: ... + + @property + def path_offset(self) -> int: ... + + path: str + + def __str__(self) -> str: ... + +class Symbol(lief.Symbol): + def __init__(self) -> None: ... + + class CATEGORY(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.CATEGORY: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + LOCAL = 1 + + EXTERNAL = 2 + + UNDEFINED = 3 + + INDIRECT_ABS = 4 + + INDIRECT_LOCAL = 5 + + INDIRECT_ABS_LOCAL = 6 + + class ORIGIN(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.ORIGIN: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + DYLD_EXPORT = 1 + + DYLD_BIND = 2 + + SYMTAB = 3 + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Symbol.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNDEFINED = 0 + + ABSOLUTE_SYM = 2 + + SECTION = 14 + + PREBOUND = 12 + + INDIRECT = 10 + + @property + def demangled_name(self) -> str: ... + + @property + def category(self) -> Symbol.CATEGORY: ... + + raw_type: int + + @property + def type(self) -> Symbol.TYPE: ... + + numberof_sections: int + + description: int + + @property + def has_export_info(self) -> bool: ... + + @property + def origin(self) -> Symbol.ORIGIN: ... + + @property + def export_info(self) -> ExportInfo | None: ... + + @property + def has_binding_info(self) -> bool: ... + + @property + def binding_info(self) -> BindingInfo | None: ... + + @property + def library(self) -> DylibCommand | None: ... + + @property + def is_external(self) -> bool: ... + + @property + def library_ordinal(self) -> int: ... + + def __str__(self) -> str: ... + +class Relocation(lief.Relocation): + class ORIGIN(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Relocation.ORIGIN: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + DYLDINFO = 1 + + RELOC_TABLE = 2 + + CHAINED_FIXUPS = 3 + + address: int + + pc_relative: bool + + @property + def type(self) -> Union[lief.MachO.X86_RELOCATION, lief.MachO.X86_64_RELOCATION, lief.MachO.PPC_RELOCATION, lief.MachO.ARM_RELOCATION, lief.MachO.ARM64_RELOCATION, lief.MachO.DyldInfo.REBASE_TYPE, ]: ... + + @type.setter + def type(self, arg: int, /) -> None: ... + + @property + def architecture(self) -> Header.CPU_TYPE: ... + + @property + def has_symbol(self) -> bool: ... + + @property + def symbol(self) -> Symbol | None: ... + + @property + def has_section(self) -> bool: ... + + @property + def section(self) -> Section | None: ... + + @property + def origin(self) -> Relocation.ORIGIN: ... + + @property + def has_segment(self) -> bool: ... + + @property + def segment(self) -> SegmentCommand | None: ... + + def __str__(self) -> str: ... + +class RelocationObject(Relocation): + value: int + + @property + def is_scattered(self) -> bool: ... + + def __str__(self) -> str: ... + +class RelocationDyld(Relocation): + def __le__(self, arg: RelocationDyld, /) -> bool: ... + + def __lt__(self, arg: RelocationDyld, /) -> bool: ... + + def __ge__(self, arg: RelocationDyld, /) -> bool: ... + + def __gt__(self, arg: RelocationDyld, /) -> bool: ... + + def __str__(self) -> str: ... + +class RelocationFixup(Relocation): + target: int + + next: int + + def __str__(self) -> str: ... + +class BindingInfo(lief.Object): + address: int + + library_ordinal: int + + addend: int + + weak_import: bool + + @property + def has_library(self) -> bool: ... + + @property + def library(self) -> DylibCommand | None: ... + + @property + def has_segment(self) -> bool: ... + + @property + def segment(self) -> SegmentCommand | None: ... + + @property + def has_symbol(self) -> bool: ... + + @property + def symbol(self) -> Symbol | None: ... + + def __str__(self) -> str: ... + +class DyldBindingInfo(BindingInfo): + class CLASS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DyldBindingInfo.CLASS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + WEAK = 1 + + LAZY = 2 + + STANDARD = 3 + + THREADED = 100 + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DyldBindingInfo.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + POINTER = 1 + + TEXT_ABSOLUTE32 = 2 + + TEXT_PCREL32 = 3 + + binding_class: DyldBindingInfo.CLASS + + binding_type: DyldBindingInfo.TYPE + + @property + def original_offset(self) -> int: ... + + def __str__(self) -> str: ... + +class ExportInfo(lief.Object): + class KIND(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ExportInfo.KIND: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + REGULAR = 0 + + THREAD_LOCAL_KIND = 1 + + ABSOLUTE_KIND = 2 + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ExportInfo.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + WEAK_DEFINITION = 4 + + REEXPORT = 8 + + STUB_AND_RESOLVER = 16 + + STATIC_RESOLVER = 32 + + @property + def node_offset(self) -> int: ... + + @property + def kind(self) -> ExportInfo.KIND: ... + + @property + def flags_list(self) -> list[ExportInfo.FLAGS]: ... + + flags: int + + address: int + + @property + def alias(self) -> Symbol | None: ... + + @property + def alias_library(self) -> DylibCommand | None: ... + + @property + def has_symbol(self) -> bool: ... + + def has(self, flag: ExportInfo.FLAGS) -> bool: ... + + @property + def symbol(self) -> Symbol | None: ... + + def __str__(self) -> str: ... + +class FunctionStarts(LoadCommand): + data_offset: int + + data_size: int + + @property + def functions(self) -> list[int]: ... + + @functions.setter + def functions(self, arg: Sequence[int], /) -> None: ... + + def add_function(self, address: int) -> None: ... + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class FunctionVariants(LoadCommand): + class RuntimeTableEntry: + class FLAGS(enum.Enum): + ARM64_DEFAULT = 3145728 + + ARM64_FLAGM = 3145729 + + ARM64_FLAGM2 = 3145730 + + ARM64_FHM = 3145731 + + ARM64_DOTPROD = 3145732 + + ARM64_SHA3 = 3145733 + + ARM64_RDM = 3145734 + + ARM64_LSE = 3145735 + + ARM64_SHA256 = 3145736 + + ARM64_SHA512 = 3145737 + + ARM64_SHA1 = 3145738 + + ARM64_AES = 3145739 + + ARM64_PMULL = 3145740 + + ARM64_SPECRES = 3145741 + + ARM64_SB = 3145742 + + ARM64_FRINTTS = 3145743 + + ARM64_LRCPC = 3145744 + + ARM64_LRCPC2 = 3145745 + + ARM64_FCMA = 3145746 + + ARM64_JSCVT = 3145747 + + ARM64_PAUTH = 3145748 + + ARM64_PAUTH2 = 3145749 + + ARM64_FPAC = 3145750 + + ARM64_DPB = 3145751 + + ARM64_DPB2 = 3145752 + + ARM64_BF16 = 3145753 + + ARM64_I8MM = 3145754 + + ARM64_WFXT = 3145755 + + ARM64_RPRES = 3145756 + + ARM64_ECV = 3145757 + + ARM64_AFP = 3145758 + + ARM64_LSE2 = 3145759 + + ARM64_CSV2 = 3145760 + + ARM64_CVS3 = 3145761 + + ARM64_DIT = 3145762 + + ARM64_FP16 = 3145763 + + ARM64_SSBS = 3145764 + + ARM64_BTI = 3145765 + + ARM64_SME = 3145772 + + ARM64_SME2 = 3145773 + + ARM64_SMEF64F64 = 3145774 + + ARM64_SMEI16I64 = 3145775 + + ARM64_SMEF32F32 = 3145776 + + ARM64_SMEBI32I32 = 3145777 + + ARM64_SMEB16F32 = 3145778 + + ARM64_SMEF16F32 = 3145779 + + ARM64_SMEI8I32 = 3145780 + + ARM64_SMEI16I32 = 3145781 + + ARM64_ADVSIMD = 3145782 + + ARM64_ADVSIMDHPFP = 3145783 + + ARM64_CRC32 = 3145784 + + PER_PROCESS_DEFAULT = 1048576 + + PER_PROCESS_TRANSLATED = 1048577 + + PER_PROCESS_MTE_ENABLED = 1048578 + + PER_PROCESS_NO_OVERREAD = 1048579 + + SYSTEM_WIDE_DEFAULT = 2097152 + + SYSTEM_WIDE_INTERNAL_INSTALL = 2097153 + + SYSTEM_WIDE_CUSTOMER_INSTALL = 2097154 + + SYSTEM_WIDE_LOCKDOWN = 2097155 + + X86_64_DEFAULT = 4194304 + + X86_64_SSE41 = 4194305 + + X86_64_FMA = 4194306 + + X86_64_AVX = 4194307 + + X86_64_AVX2 = 4194308 + + X86_64_AVX512F = 4194309 + + X86_64_AVX512BW = 4194310 + + X86_64_BMI1 = 4194311 + + X86_64_ROSETTA = 4194312 + + X86_64_HASWELL = 4194313 + + X86_64_IVYBRIDGE = 4194314 + + X86_64_NEHALEM = 4194315 + + UNKNOWN = 0 + + impl: int + + another_table: bool + + @property + def flag_bit_nums(self) -> memoryview: ... + + @property + def flags(self) -> list[FunctionVariants.RuntimeTableEntry.FLAGS]: ... + + def __str__(self) -> str: ... + + class RuntimeTable: + class KIND(enum.Enum): + UNKNOWN = 0 + + PER_PROCESS = 1 + + SYSTEM_WIDE = 2 + + ARM64 = 3 + + X86_64 = 4 + + class it_entries: + def __getitem__(self, arg: int, /) -> FunctionVariants.RuntimeTableEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FunctionVariants.RuntimeTable.it_entries: ... + + def __next__(self) -> FunctionVariants.RuntimeTableEntry: ... + + @property + def kind(self) -> FunctionVariants.RuntimeTable.KIND: ... + + @property + def offset(self) -> int: ... + + @property + def entries(self) -> FunctionVariants.RuntimeTable.it_entries: ... + + def __str__(self) -> str: ... + + class it_runtime_table: + def __getitem__(self, arg: int, /) -> FunctionVariants.RuntimeTable: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FunctionVariants.it_runtime_table: ... + + def __next__(self) -> FunctionVariants.RuntimeTable: ... + + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + @property + def runtime_table(self) -> FunctionVariants.it_runtime_table: ... + + def __str__(self) -> str: ... + +class FunctionVariantFixups(LoadCommand): + class Fixup: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, seg_offset: int, seg_index: int, variant_index: int, pac_auth: bool, pac_address: bool, pac_key: int, pac_diversity: int) -> None: ... + + seg_offset: int + + seg_index: int + + variant_index: int + + pac_auth: bool + + pac_address: bool + + pac_key: int + + pac_diversity: int + + @property + def segment(self) -> SegmentCommand | None: ... + + def __str__(self) -> str: ... + + class it_fixups: + def __getitem__(self, arg: int, /) -> FunctionVariantFixups.Fixup: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FunctionVariantFixups.it_fixups: ... + + def __next__(self) -> FunctionVariantFixups.Fixup: ... + + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + @property + def fixups(self) -> FunctionVariantFixups.it_fixups: ... + + def add(self, fixup: FunctionVariantFixups.Fixup) -> FunctionVariantFixups: ... + + def __str__(self) -> str: ... + +class LazyLoadDylibInfo(LoadCommand): + class Fixup: + address: int + + @property + def ordinal(self) -> int: ... + + @property + def symbol(self) -> str: ... + + @property + def is_auth(self) -> bool: ... + + def __str__(self) -> str: ... + + class it_fixups: + def __getitem__(self, arg: int, /) -> LazyLoadDylibInfo.Fixup: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> LazyLoadDylibInfo.it_fixups: ... + + def __next__(self) -> LazyLoadDylibInfo.Fixup: ... + + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + load_path: str + + flag_image_offset: int + + flags: int + + may_be_missing: bool + + pointer_format: int + + chain_start_image_offset: int + + @property + def symbols(self) -> list[str]: ... + + @symbols.setter + def symbols(self, arg: Sequence[str], /) -> LazyLoadDylibInfo: ... + + def add_symbol(self, symbol: str) -> LazyLoadDylibInfo: ... + + def clear_symbols(self) -> LazyLoadDylibInfo: ... + + @property + def fixups(self) -> LazyLoadDylibInfo.it_fixups: ... + + def __str__(self) -> str: ... + +class AtomInfo(LoadCommand): + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class CodeSignature(LoadCommand): + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class CodeSignatureDir(LoadCommand): + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class it_data_in_code_entries: + def __getitem__(self, arg: int, /) -> DataCodeEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> it_data_in_code_entries: ... + + def __next__(self) -> DataCodeEntry: ... + +class DataInCode(LoadCommand): + data_offset: int + + data_size: int + + @property + def entries(self) -> it_data_in_code_entries: ... + + def add(self, entry: DataCodeEntry) -> DataInCode: ... + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class DataCodeEntry(lief.Object): + class TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DataCodeEntry.TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + DATA = 1 + + JUMP_TABLE_8 = 2 + + JUMP_TABLE_16 = 3 + + JUMP_TABLE_32 = 4 + + ABS_JUMP_TABLE_32 = 5 + + offset: int + + length: int + + type: DataCodeEntry.TYPES + + def __str__(self) -> str: ... + +class SourceVersion(LoadCommand): + @property + def version(self) -> list[int]: ... + + @version.setter + def version(self, arg: Sequence[int], /) -> None: ... + + def __str__(self) -> str: ... + +class Routine(LoadCommand): + init_address: int + + init_module: int + + reserved1: int + + reserved2: int + + reserved3: int + + reserved4: int + + reserved5: int + + reserved6: int + + def __str__(self) -> str: ... + +class VersionMin(LoadCommand): + @property + def version(self) -> list[int]: ... + + @version.setter + def version(self, arg: Sequence[int], /) -> None: ... + + @property + def sdk(self) -> list[int]: ... + + @sdk.setter + def sdk(self, arg: Sequence[int], /) -> None: ... + + def __str__(self) -> str: ... + +class SegmentSplitInfo(LoadCommand): + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class SubFramework(LoadCommand): + umbrella: str + + def __str__(self) -> str: ... + +class SubClient(LoadCommand): + client: str + + def __str__(self) -> str: ... + +class DyldEnvironment(LoadCommand): + value: str + + def __str__(self) -> str: ... + +class EncryptionInfo(LoadCommand): + crypt_offset: int + + crypt_size: int + + crypt_id: int + + def __str__(self) -> str: ... + +class BuildVersion(LoadCommand): + class PLATFORMS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> BuildVersion.PLATFORMS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + MACOS = 1 + + IOS = 2 + + TVOS = 3 + + WATCHOS = 4 + + BRIDGEOS = 5 + + MAC_CATALYST = 6 + + IOS_SIMULATOR = 7 + + TVOS_SIMULATOR = 8 + + WATCHOS_SIMULATOR = 9 + + DRIVERKIT = 10 + + VISIONOS = 11 + + VISIONOS_SIMULATOR = 12 + + FIRMWARE = 13 + + SEPOS = 14 + + MACOS_EXCLAVE_CORE = 15 + + MACOS_EXCLAVE_KIT = 16 + + IOS_EXCLAVE_CORE = 17 + + IOS_EXCLAVE_KIT = 18 + + TVOS_EXCLAVE_CORE = 19 + + TVOS_EXCLAVE_KIT = 20 + + WATCHOS_EXCLAVE_CORE = 21 + + WATCHOS_EXCLAVE_KIT = 22 + + VISIONOS_EXCLAVE_CORE = 23 + + VISIONOS_EXCLAVE_KIT = 24 + + ANY = 4294967295 + + platform: BuildVersion.PLATFORMS + + @property + def minos(self) -> list[int]: ... + + @minos.setter + def minos(self, arg: Sequence[int], /) -> None: ... + + @property + def sdk(self) -> list[int]: ... + + @sdk.setter + def sdk(self, arg: Sequence[int], /) -> None: ... + + @property + def tools(self) -> list[BuildToolVersion]: ... + + def __str__(self) -> str: ... + +class BuildToolVersion(lief.Object): + @property + def tool(self) -> BuildToolVersion.TOOLS: ... + + @property + def version(self) -> list[int]: ... + + def __str__(self) -> str: ... + + class TOOLS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> BuildToolVersion.TOOLS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + CLANG = 1 + + SWIFT = 2 + + LD = 3 + + LLD = 4 + + METAL = 1024 + + AIRLLD = 1025 + + AIRNT = 1026 + + AIRNT_PLUGIN = 1027 + + AIRPACK = 1028 + + GPUARCHIVER = 1031 + + METAL_FRAMEWORK = 1032 + +class FilesetCommand(LoadCommand): + name: str + + virtual_address: int + + file_offset: int + + @property + def binary(self) -> Binary | None: ... + + def __str__(self) -> str: ... + +class ChainedBindingInfo(BindingInfo): + @property + def format(self) -> DYLD_CHAINED_FORMAT: ... + + @property + def ptr_format(self) -> DYLD_CHAINED_PTR_FORMAT: ... + + offset: int + + @property + def sign_extended_addend(self) -> int: ... + + def __str__(self) -> str: ... + +class TwoLevelHints(LoadCommand): + class it_hints_t: + def __getitem__(self, arg: int, /) -> int: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> TwoLevelHints.it_hints_t: ... + + def __next__(self) -> int: ... + + @property + def hints(self) -> TwoLevelHints.it_hints_t: ... + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class LinkerOptHint(LoadCommand): + data_offset: int + + data_size: int + + @property + def content(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class IndirectBindingInfo(BindingInfo): + pass + +class UnknownCommand(LoadCommand): + @property + def original_command(self) -> int: ... + + def __str__(self) -> str: ... + +class Stub: + def __init__(self, target_info: Stub.target_info_t, address: int, raw_stub: Sequence[int]) -> None: ... + + class target_info_t: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg0: Header.CPU_TYPE, arg1: int, /) -> None: ... + + arch: Header.CPU_TYPE + + subtype: int + + @property + def address(self) -> int: ... + + @property + def raw(self) -> memoryview: ... + + @property + def target(self) -> Union[int, lief.lief_errors]: ... + + def __str__(self) -> str: ... + +class Builder: + class config_t: + def __init__(self) -> None: ... + + linkedit: bool + + @overload + @staticmethod + def write(binary: Binary, output: str) -> Union[lief.ok_t, lief.lief_errors]: ... + + @overload + @staticmethod + def write(binary: Binary, output: str, config: Builder.config_t) -> Union[lief.ok_t, lief.lief_errors]: ... + + @overload + @staticmethod + def write(fat_binary: FatBinary, output: str) -> Union[lief.ok_t, lief.lief_errors]: ... + + @overload + @staticmethod + def write(fat_binary: FatBinary, output: str, config: Builder.config_t) -> Union[lief.ok_t, lief.lief_errors]: ... + +def is_fat(file: Union[str | os.PathLike]) -> bool: ... + +def is_64(file: Union[str | os.PathLike]) -> bool: ... + +@overload +def check_layout(file: Binary) -> tuple[bool, str]: ... + +@overload +def check_layout(file: FatBinary) -> tuple[bool, str]: ... diff --git a/vendor/lief/api/python/lief/OAT.pyi b/vendor/lief/api/python/lief/OAT.pyi new file mode 100644 index 0000000..f06f641 --- /dev/null +++ b/vendor/lief/api/python/lief/OAT.pyi @@ -0,0 +1,355 @@ +from collections.abc import Sequence +import enum +import io +import os +from typing import Optional, Union, overload + +import lief +import lief.Android +import lief.DEX +import lief.ELF + + +class OAT_CLASS_TYPES(enum.Enum): + ALL_COMPILED = 0 + + SOME_COMPILED = 1 + + NONE_COMPILED = 2 + +class OAT_CLASS_STATUS(enum.Enum): + RETIRED = -2 + + ERROR = -1 + + NOTREADY = 0 + + IDX = 1 + + LOADED = 2 + + RESOLVING = 3 + + RESOLVED = 4 + + VERIFYING = 5 + + VERIFICATION_AT_RUNTIME = 6 + + VERIFYING_AT_RUNTIME = 7 + + VERIFIED = 8 + + INITIALIZING = 9 + + INITIALIZED = 10 + +class HEADER_KEYS(enum.Enum): + IMAGE_LOCATION = 0 + + DEX2OAT_CMD_LINE = 1 + + DEX2OAT_HOST = 2 + + PIC = 3 + + HAS_PATCH_INFO = 4 + + DEBUGGABLE = 5 + + NATIVE_DEBUGGABLE = 6 + + COMPILER_FILTER = 7 + + CLASS_PATH = 8 + + BOOT_CLASS_PATH = 9 + + CONCURRENT_COPYING = 10 + +class INSTRUCTION_SETS(enum.Enum): + NONE = 0 + + ARM = 1 + + ARM_64 = 2 + + THUMB2 = 3 + + X86 = 4 + + X86_64 = 5 + + MIPS = 6 + + MIPS_64 = 7 + +@overload +def version(binary: lief.ELF.Binary) -> int: ... + +@overload +def version(file: str) -> int: ... + +@overload +def version(raw: Sequence[int]) -> int: ... + +def android_version(arg: int, /) -> lief.Android.ANDROID_VERSIONS: ... + +@overload +def parse(oat_file: str) -> Optional[Binary]: ... + +@overload +def parse(oat_file: str, vdex_file: str) -> Optional[Binary]: ... + +@overload +def parse(raw: Sequence[int]) -> Optional[Binary]: ... + +@overload +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]]) -> Optional[Binary]: ... + +class Binary(lief.ELF.Binary): + class it_dex_files: + def __getitem__(self, arg: int, /) -> lief.DEX.File: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_dex_files: ... + + def __next__(self) -> lief.DEX.File: ... + + class it_oat_dex_files: + def __getitem__(self, arg: int, /) -> DexFile: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_oat_dex_files: ... + + def __next__(self) -> DexFile: ... + + class it_classes: + def __getitem__(self, arg: int, /) -> Class: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_classes: ... + + def __next__(self) -> Class: ... + + class it_methods: + def __getitem__(self, arg: int, /) -> Method: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_methods: ... + + def __next__(self) -> Method: ... + + @property + def header(self) -> Header: ... # type: ignore + + @property + def dex_files(self) -> Binary.it_dex_files: ... + + @property + def oat_dex_files(self) -> Binary.it_oat_dex_files: ... + + @property + def classes(self) -> Binary.it_classes: ... + + @property + def methods(self) -> Binary.it_methods: ... + + def has_class(self, arg: str, /) -> bool: ... + + @overload + def get_class(self, class_name: str) -> Class | None: ... + + @overload + def get_class(self, class_index: int) -> Class | None: ... + + @property + def dex2dex_json_info(self) -> str: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + def __init__(self) -> None: ... + + class it_key_values_t: + def __getitem__(self, arg: int, /) -> Header.element_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Header.it_key_values_t: ... + + def __next__(self) -> Header.element_t: ... + + class element_t: + key: HEADER_KEYS + + value: str + + @property + def key_values(self) -> Header.it_key_values_t: ... + + @property + def keys(self) -> list[HEADER_KEYS]: ... + + @property + def values(self) -> list[str]: ... + + @property + def magic(self) -> list[int]: ... + + @property + def version(self) -> int: ... + + @property + def checksum(self) -> int: ... + + @property + def instruction_set(self) -> INSTRUCTION_SETS: ... + + @property + def nb_dex_files(self) -> int: ... + + @property + def oat_dex_files_offset(self) -> int: ... + + @property + def executable_offset(self) -> int: ... + + @property + def i2i_bridge_offset(self) -> int: ... + + @property + def i2c_code_bridge_offset(self) -> int: ... + + @property + def jni_dlsym_lookup_offset(self) -> int: ... + + @property + def quick_generic_jni_trampoline_offset(self) -> int: ... + + @property + def quick_imt_conflict_trampoline_offset(self) -> int: ... + + @property + def quick_resolution_trampoline_offset(self) -> int: ... + + @property + def quick_to_interpreter_bridge_offset(self) -> int: ... + + @property + def image_patch_delta(self) -> int: ... + + @property + def image_file_location_oat_checksum(self) -> int: ... + + @property + def image_file_location_oat_data_begin(self) -> int: ... + + @property + def key_value_size(self) -> int: ... + + def get(self, key: HEADER_KEYS) -> str: ... + + def set(self, key: HEADER_KEYS, value: str) -> Header: ... + + def __getitem__(self, arg: HEADER_KEYS, /) -> str: ... + + def __setitem__(self, arg0: HEADER_KEYS, arg1: str, /) -> Header: ... + + def __str__(self) -> str: ... + +class DexFile(lief.Object): + def __init__(self) -> None: ... + + location: str + + checksum: int + + dex_offset: int + + @property + def has_dex_file(self) -> bool: ... + + @property + def dex_file(self) -> lief.DEX.File | None: ... + + def __str__(self) -> str: ... + +class Class(lief.Object): + def __init__(self) -> None: ... + + class it_methods: + def __getitem__(self, arg: int, /) -> Method: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Class.it_methods: ... + + def __next__(self) -> Method: ... + + def has_dex_class(self) -> bool: ... + + @property + def status(self) -> OAT_CLASS_STATUS: ... + + @property + def type(self) -> OAT_CLASS_TYPES: ... + + @property + def fullname(self) -> str: ... + + @property + def index(self) -> int: ... + + @property + def methods(self) -> Class.it_methods: ... + + @property + def bitmap(self) -> list[int]: ... + + @overload + def is_quickened(self, dex_method: lief.DEX.Method) -> bool: ... + + @overload + def is_quickened(self, method_index: int) -> bool: ... + + @overload + def method_offsets_index(self, arg: lief.DEX.Method, /) -> int: ... + + @overload + def method_offsets_index(self, arg: int, /) -> int: ... + + def __str__(self) -> str: ... + +class Method(lief.Object): + def __init__(self) -> None: ... + + @property + def name(self) -> str: ... + + @property + def oat_class(self) -> Class | None: ... + + @property + def dex_method(self) -> lief.DEX.Method | None: ... + + @property + def has_dex_method(self) -> bool: ... + + @property + def is_dex2dex_optimized(self) -> bool: ... + + @property + def is_compiled(self) -> bool: ... + + @property + def quick_code(self) -> list[int]: ... + + @quick_code.setter + def quick_code(self, arg: Sequence[int], /) -> None: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/PE/__init__.pyi b/vendor/lief/api/python/lief/PE/__init__.pyi new file mode 100644 index 0000000..e42d5b8 --- /dev/null +++ b/vendor/lief/api/python/lief/PE/__init__.pyi @@ -0,0 +1,4981 @@ +from collections.abc import Callable, Sequence +import enum +import io +import os +from typing import Final, Optional, Union, overload + +import lief.PE + +import lief +import lief.COFF +from lief.PE import ( + unwind_aarch64 as unwind_aarch64, + unwind_x64 as unwind_x64 +) + + +class PE_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> PE_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + PE32 = 267 + + PE32_PLUS = 523 + +class ALGORITHMS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ALGORITHMS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + SHA_512 = 1 + + SHA_384 = 2 + + SHA_256 = 3 + + SHA_1 = 4 + + MD5 = 5 + + MD4 = 6 + + MD2 = 7 + + RSA = 8 + + EC = 9 + + MD5_RSA = 10 + + SHA1_DSA = 11 + + SHA1_RSA = 12 + + SHA_256_RSA = 13 + + SHA_384_RSA = 14 + + SHA_512_RSA = 15 + + SHA1_ECDSA = 16 + + SHA_256_ECDSA = 17 + + SHA_384_ECDSA = 18 + + SHA_512_ECDSA = 19 + +class ParserConfig: + def __init__(self) -> None: ... + + parse_signature: bool + + parse_exports: bool + + parse_imports: bool + + parse_rsrc: bool + + parse_reloc: bool + + parse_exceptions: bool + + parse_arm64x_binary: bool + + rebase: int | None + + default_conf: Final[ParserConfig] = ... + + all: Final[ParserConfig] = ... + + def __str__(self) -> str: ... + +@overload +def parse_from_memory(address: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +@overload +def parse_from_memory(address: int, size: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +def parse_from_dump(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], addr: int, config: ParserConfig = ...) -> Optional[Binary]: ... + +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], config: ParserConfig = ...) -> Optional[Binary]: ... + +class DosHeader(lief.Object): + @staticmethod + def create(arg: PE_TYPE, /) -> DosHeader: ... + + magic: int + + used_bytes_in_last_page: int + + file_size_in_pages: int + + numberof_relocation: int + + header_size_in_paragraphs: int + + minimum_extra_paragraphs: int + + maximum_extra_paragraphs: int + + initial_relative_ss: int + + initial_sp: int + + checksum: int + + initial_ip: int + + initial_relative_cs: int + + addressof_relocation_table: int + + overlay_number: int + + oem_id: int + + oem_info: int + + addressof_new_exeheader: int + + def copy(self) -> DosHeader: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + class MACHINE_TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.MACHINE_TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + ALPHA = 388 + + ALPHA64 = 644 + + AM33 = 467 + + AMD64 = 34404 + + ARM = 448 + + ARMNT = 452 + + ARM64 = 43620 + + EBC = 3772 + + I386 = 332 + + IA64 = 512 + + LOONGARCH32 = 25138 + + LOONGARCH64 = 25188 + + M32R = 36929 + + MIPS16 = 614 + + MIPSFPU = 870 + + MIPSFPU16 = 1126 + + POWERPC = 496 + + POWERPCFP = 497 + + POWERPCBE = 498 + + R4000 = 358 + + SH3 = 418 + + SH3DSP = 419 + + SH4 = 422 + + SH5 = 424 + + THUMB = 450 + + WCEMIPSV2 = 361 + + ARM64EC = 42561 + + ARM64X = 42574 + + CHPE_X86 = 14948 + + class CHARACTERISTICS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Header.CHARACTERISTICS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + RELOCS_STRIPPED = 1 + + EXECUTABLE_IMAGE = 2 + + LINE_NUMS_STRIPPED = 4 + + LOCAL_SYMS_STRIPPED = 8 + + AGGRESSIVE_WS_TRIM = 16 + + LARGE_ADDRESS_AWARE = 32 + + BYTES_REVERSED_LO = 128 + + NEED_32BIT_MACHINE = 256 + + DEBUG_STRIPPED = 512 + + REMOVABLE_RUN_FROM_SWAP = 1024 + + NET_RUN_FROM_SWAP = 2048 + + SYSTEM = 4096 + + DLL = 8192 + + UP_SYSTEM_ONLY = 16384 + + BYTES_REVERSED_HI = 32768 + + @staticmethod + def create(type: PE_TYPE) -> Header: ... + + @property + def signature(self) -> list[int]: ... + + @signature.setter + def signature(self, arg: Sequence[int], /) -> None: ... + + machine: Header.MACHINE_TYPES + + numberof_sections: int + + time_date_stamps: int + + pointerto_symbol_table: int + + numberof_symbols: int + + sizeof_optional_header: int + + characteristics: int + + def has_characteristic(self, characteristic: Header.CHARACTERISTICS) -> bool: ... + + def add_characteristic(self, characteristic: Header.CHARACTERISTICS) -> None: ... + + def remove_characteristic(self, characteristic: Header.CHARACTERISTICS) -> None: ... + + @property + def characteristics_list(self) -> list[Header.CHARACTERISTICS]: ... + + def copy(self) -> Header: ... + + def __str__(self) -> str: ... + +class OptionalHeader(lief.Object): + class SUBSYSTEM(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> OptionalHeader.SUBSYSTEM: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + NATIVE = 1 + + WINDOWS_GUI = 2 + + WINDOWS_CUI = 3 + + OS2_CUI = 5 + + POSIX_CUI = 7 + + NATIVE_WINDOWS = 8 + + WINDOWS_CE_GUI = 9 + + EFI_APPLICATION = 10 + + EFI_BOOT_SERVICE_DRIVER = 11 + + EFI_RUNTIME_DRIVER = 12 + + EFI_ROM = 13 + + XBOX = 14 + + WINDOWS_BOOT_APPLICATION = 16 + + XBOX_CODE_CATALOG = 17 + + class DLL_CHARACTERISTICS(enum.IntFlag): + def __repr__(self, /): ... + + @staticmethod + def from_value(arg: int, /) -> OptionalHeader.DLL_CHARACTERISTICS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + HIGH_ENTROPY_VA = 32 + + DYNAMIC_BASE = 64 + + FORCE_INTEGRITY = 128 + + NX_COMPAT = 256 + + NO_ISOLATION = 512 + + NO_SEH = 1024 + + NO_BIND = 2048 + + APPCONTAINER = 4096 + + WDM_DRIVER = 8192 + + GUARD_CF = 16384 + + TERMINAL_SERVER_AWARE = 32768 + + @staticmethod + def create(type: PE_TYPE) -> OptionalHeader: ... + + magic: PE_TYPE + + major_linker_version: int + + minor_linker_version: int + + sizeof_code: int + + sizeof_initialized_data: int + + sizeof_uninitialized_data: int + + addressof_entrypoint: int + + baseof_code: int + + baseof_data: int + + imagebase: int + + section_alignment: int + + file_alignment: int + + major_operating_system_version: int + + minor_operating_system_version: int + + major_image_version: int + + minor_image_version: int + + major_subsystem_version: int + + minor_subsystem_version: int + + win32_version_value: int + + sizeof_image: int + + sizeof_headers: int + + checksum: int + + subsystem: OptionalHeader.SUBSYSTEM + + dll_characteristics: int + + def add(self, characteristic: OptionalHeader.DLL_CHARACTERISTICS) -> None: ... + + def remove(self, characteristic: OptionalHeader.DLL_CHARACTERISTICS) -> None: ... + + @property + def dll_characteristics_lists(self) -> list[OptionalHeader.DLL_CHARACTERISTICS]: ... + + def has(self, characteristics: OptionalHeader.DLL_CHARACTERISTICS) -> bool: ... + + sizeof_stack_reserve: int + + sizeof_stack_commit: int + + sizeof_heap_reserve: int + + sizeof_heap_commit: int + + loader_flags: int + + numberof_rva_and_size: int + + def __iadd__(self, arg: OptionalHeader.DLL_CHARACTERISTICS, /) -> OptionalHeader: ... + + def __isub__(self, arg: OptionalHeader.DLL_CHARACTERISTICS, /) -> OptionalHeader: ... + + def __contains__(self, arg: OptionalHeader.DLL_CHARACTERISTICS, /) -> bool: ... + + def copy(self) -> OptionalHeader: ... + + def __str__(self) -> str: ... + +class RichHeader(lief.Object): + def __init__(self) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> RichEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> RichHeader.it_entries: ... + + def __next__(self) -> RichEntry: ... + + key: int + + @property + def entries(self) -> RichHeader.it_entries: ... + + @overload + def add_entry(self, entry: RichEntry) -> None: ... + + @overload + def add_entry(self, id: int, build_id: int, count: int) -> None: ... + + @overload + def raw(self) -> list[int]: ... + + @overload + def raw(self, xor_key: int) -> list[int]: ... + + @overload + def hash(self, algo: ALGORITHMS) -> list[int]: ... + + @overload + def hash(self, algo: ALGORITHMS, xor_key: int) -> list[int]: ... + + def copy(self) -> RichHeader: ... + + def __str__(self) -> str: ... + +class RichEntry(lief.Object): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, id: int, build_id: int, count: int) -> None: ... + + id: int + + build_id: int + + count: int + + def copy(self) -> RichEntry: ... + + def __str__(self) -> str: ... + +class DataDirectory(lief.Object): + def __init__(self) -> None: ... + + class TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DataDirectory.TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + EXPORT_TABLE = 0 + + IMPORT_TABLE = 1 + + RESOURCE_TABLE = 2 + + EXCEPTION_TABLE = 3 + + CERTIFICATE_TABLE = 4 + + BASE_RELOCATION_TABLE = 5 + + DEBUG_DIR = 6 + + ARCHITECTURE = 7 + + GLOBAL_PTR = 8 + + TLS_TABLE = 9 + + LOAD_CONFIG_TABLE = 10 + + BOUND_IMPORT = 11 + + IAT = 12 + + DELAY_IMPORT_DESCRIPTOR = 13 + + CLR_RUNTIME_HEADER = 14 + + RESERVED = 15 + + UNKNOWN = 16 + + rva: int + + size: int + + @property + def section(self) -> Section | None: ... + + @property + def content(self) -> memoryview: ... + + @property + def type(self) -> DataDirectory.TYPES: ... + + @property + def has_section(self) -> bool: ... + + def copy(self) -> DataDirectory: ... + + def __str__(self) -> str: ... + +class Section(lief.Section): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, name: str, content: Sequence[int]) -> None: ... + + @overload + def __init__(self, name: str) -> None: ... + + class CHARACTERISTICS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Section.CHARACTERISTICS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + TYPE_NO_PAD = 8 + + CNT_CODE = 32 + + CNT_INITIALIZED_DATA = 64 + + CNT_UNINITIALIZED_DATA = 128 + + LNK_OTHER = 256 + + LNK_INFO = 512 + + LNK_REMOVE = 2048 + + LNK_COMDAT = 4096 + + GPREL = 32768 + + MEM_PURGEABLE = 65536 + + MEM_16BIT = 131072 + + MEM_LOCKED = 262144 + + MEM_PRELOAD = 524288 + + ALIGN_1BYTES = 1048576 + + ALIGN_2BYTES = 2097152 + + ALIGN_4BYTES = 3145728 + + ALIGN_8BYTES = 4194304 + + ALIGN_16BYTES = 5242880 + + ALIGN_32BYTES = 6291456 + + ALIGN_64BYTES = 7340032 + + ALIGN_128BYTES = 8388608 + + ALIGN_256BYTES = 9437184 + + ALIGN_512BYTES = 10485760 + + ALIGN_1024BYTES = 11534336 + + ALIGN_2048BYTES = 12582912 + + ALIGN_4096BYTES = 13631488 + + ALIGN_8192BYTES = 14680064 + + LNK_NRELOC_OVFL = 16777216 + + MEM_DISCARDABLE = 33554432 + + MEM_NOT_CACHED = 67108864 + + MEM_NOT_PAGED = 134217728 + + MEM_SHARED = 268435456 + + MEM_EXECUTE = 536870912 + + MEM_READ = 1073741824 + + MEM_WRITE = 2147483648 + + virtual_size: int + + sizeof_raw_data: int + + pointerto_raw_data: int + + pointerto_relocation: int + + pointerto_line_numbers: int + + numberof_relocations: int + + numberof_line_numbers: int + + characteristics: int + + @property + def characteristics_lists(self) -> list[Section.CHARACTERISTICS]: ... + + def has_characteristic(self, characteristic: Section.CHARACTERISTICS) -> bool: ... + + @property + def is_discardable(self) -> bool: ... + + @property + def coff_string(self) -> lief.COFF.String | None: ... + + @property + def padding(self) -> bytes: ... + + def copy(self) -> Section: ... + + def __str__(self) -> str: ... + +class Relocation(lief.Object): + def __init__(self) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> RelocationEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Relocation.it_entries: ... + + def __next__(self) -> RelocationEntry: ... + + virtual_address: int + + block_size: int + + @property + def entries(self) -> Relocation.it_entries: ... + + def add_entry(self, new_entry: RelocationEntry) -> RelocationEntry: ... + + def copy(self) -> Relocation: ... + + def __str__(self) -> str: ... + +class RelocationEntry(lief.Relocation): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg0: int, arg1: RelocationEntry.BASE_TYPES, /) -> None: ... + + class BASE_TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> RelocationEntry.BASE_TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = -1 + + ABS = 0 + + HIGH = 1 + + LOW = 2 + + HIGHLOW = 3 + + HIGHADJ = 4 + + MIPS_JMPADDR = 261 + + ARM_MOV32 = 517 + + RISCV_HI20 = 1029 + + SECTION = 6 + + THUMB_MOV32 = 2055 + + RISCV_LOW12I = 4103 + + RISCV_LOW12S = 8200 + + MIPS_JMPADDR16 = 9 + + DIR64 = 10 + + HIGH3ADJ = 11 + + @property + def data(self) -> int: ... + + position: int + + type: RelocationEntry.BASE_TYPES + + def __str__(self) -> str: ... + +class Export(lief.Object): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, name: str, entries: Sequence[ExportEntry]) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> ExportEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Export.it_entries: ... + + def __next__(self) -> ExportEntry: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + export_flags: int + + timestamp: int + + major_version: int + + minor_version: int + + ordinal_base: int + + @property + def entries(self) -> Export.it_entries: ... + + @property + def name_rva(self) -> int: ... + + @property + def export_addr_table_rva(self) -> int: ... + + @property + def export_addr_table_cnt(self) -> int: ... + + @property + def names_addr_table_rva(self) -> int: ... + + @property + def names_addr_table_cnt(self) -> int: ... + + @property + def ord_addr_table_rva(self) -> int: ... + + @overload + def find_entry(self, name: str) -> ExportEntry | None: ... + + @overload + def find_entry(self, ordinal: int) -> ExportEntry | None: ... + + def find_entry_at(self, rva_addr: int) -> ExportEntry | None: ... + + @overload + def add_entry(self, exp: ExportEntry) -> ExportEntry: ... + + @overload + def add_entry(self, name: str, addr: int) -> ExportEntry: ... + + @overload + def remove_entry(self, entry: ExportEntry) -> bool: ... + + @overload + def remove_entry(self, name: str) -> bool: ... + + @overload + def remove_entry(self, rva: int) -> bool: ... + + def copy(self) -> Export: ... + + def __str__(self) -> str: ... + +class ExportEntry(lief.Symbol): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, name: str, addr: int) -> None: ... + + class forward_information_t: + library: str + + function: str + + def __str__(self) -> str: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + ordinal: int + + address: int + + is_extern: bool + + @property + def is_forwarded(self) -> bool: ... + + @property + def forward_information(self) -> ExportEntry.forward_information_t: ... + + @property + def function_rva(self) -> int: ... + + @property + def demangled_name(self) -> str: ... + + def set_forward_info(self, lib: str, function: str) -> None: ... + + def __str__(self) -> str: ... + +class TLS(lief.Object): + def __init__(self) -> None: ... + + @property + def callbacks(self) -> list[int]: ... + + @callbacks.setter + def callbacks(self, arg: Sequence[int], /) -> None: ... + + addressof_index: int + + addressof_callbacks: int + + sizeof_zero_fill: int + + characteristics: int + + addressof_raw_data: tuple[int, int] + + @property + def data_template(self) -> memoryview: ... + + @data_template.setter + def data_template(self, arg: Sequence[int], /) -> None: ... + + @property + def has_section(self) -> bool: ... + + @property + def has_data_directory(self) -> bool: ... + + @property + def directory(self) -> DataDirectory | None: ... + + @property + def section(self) -> Section | None: ... + + def add_callback(self, addr: int) -> TLS: ... + + def copy(self) -> TLS: ... + + def __str__(self) -> str: ... + +class Import(lief.Object): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, library_name: str) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> ImportEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Import.it_entries: ... + + def __next__(self) -> ImportEntry: ... + + @property + def forwarder_chain(self) -> int: ... + + @property + def timedatestamp(self) -> int: ... + + @property + def entries(self) -> Import.it_entries: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + @property + def directory(self) -> DataDirectory | None: ... + + @property + def iat_directory(self) -> DataDirectory | None: ... + + import_address_table_rva: int + + import_lookup_table_rva: int + + def get_function_rva_from_iat(self, function_name: str) -> Union[int, lief.lief_errors]: ... + + @overload + def add_entry(self, entry: ImportEntry) -> ImportEntry: ... + + @overload + def add_entry(self, function_name: str) -> ImportEntry: ... + + def get_entry(self, function_name: str) -> ImportEntry | None: ... + + @property + def name_rva(self) -> int: ... + + @overload + def remove_entry(self, name: str) -> bool: ... + + @overload + def remove_entry(self, ord: int) -> bool: ... + + def __str__(self) -> str: ... + +class ImportEntry(lief.Symbol): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, import_name: str) -> None: ... + + @overload + def __init__(self, data: int, type: PE_TYPE) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + data: int + + @property + def demangled_name(self) -> str: ... + + @property + def is_ordinal(self) -> bool: ... + + @property + def ordinal(self) -> int: ... + + @property + def hint(self) -> int: ... + + iat_value: int + + ilt_value: int + + @property + def iat_address(self) -> int: ... + + def copy(self) -> ImportEntry: ... + + def __str__(self) -> str: ... + +class DelayImport(lief.Object): + def __init__(self, library_name: str) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> DelayImportEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DelayImport.it_entries: ... + + def __next__(self) -> DelayImportEntry: ... + + @property + def entries(self) -> DelayImport.it_entries: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + attribute: int + + handle: int + + iat: int + + names_table: int + + biat: int + + uiat: int + + timestamp: int + + def copy(self) -> DelayImport: ... + + def __str__(self) -> str: ... + +class DelayImportEntry(lief.Symbol): + def __init__(self) -> None: ... + + @property + def demangled_name(self) -> str: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + data: int + + @property + def is_ordinal(self) -> bool: ... + + @property + def ordinal(self) -> int: ... + + @property + def hint(self) -> int: ... + + @property + def iat_value(self) -> int: ... + + def copy(self) -> DelayImportEntry: ... + + def __str__(self) -> str: ... + +class ExceptionInfo: + class ARCH(enum.Enum): + UNKNOWN = 0 + + ARM64 = 1 + + X86_64 = 2 + + @property + def arch(self) -> ExceptionInfo.ARCH: ... + + @property + def rva_start(self) -> int: ... + + @property + def offset(self) -> int: ... + + def copy(self) -> Optional[ExceptionInfo]: ... + + def __str__(self) -> str: ... + +class RuntimeFunctionX64(ExceptionInfo): + class UNWIND_FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> RuntimeFunctionX64.UNWIND_FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + EXCEPTION_HANDLER = 1 + + TERMINATE_HANDLER = 2 + + CHAIN_INFO = 4 + + class UNWIND_OPCODES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> RuntimeFunctionX64.UNWIND_OPCODES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + PUSH_NONVOL = 0 + + ALLOC_LARGE = 1 + + ALLOC_SMALL = 2 + + SET_FPREG = 3 + + SAVE_NONVOL = 4 + + SAVE_NONVOL_FAR = 5 + + SAVE_XMM128 = 8 + + SAVE_XMM128_FAR = 9 + + PUSH_MACHFRAME = 10 + + EPILOG = 6 + + SPARE = 7 + + class UNWIND_REG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> RuntimeFunctionX64.UNWIND_REG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + RAX = 0 + + RCX = 1 + + RDX = 2 + + RBX = 3 + + RSP = 4 + + RBP = 5 + + RSI = 6 + + RDI = 7 + + R8 = 8 + + R9 = 9 + + R10 = 10 + + R11 = 11 + + R12 = 12 + + R13 = 13 + + R14 = 14 + + R15 = 15 + + class unwind_info_t: + version: int + + flags: int + + sizeof_prologue: int + + count_opcodes: int + + frame_reg: int + + frame_reg_offset: int + + @property + def raw_opcodes(self) -> list[int]: ... + + @raw_opcodes.setter + def raw_opcodes(self, arg: Sequence[int], /) -> None: ... + + handler: int | None + + chained: RuntimeFunctionX64 + + def has(self, arg: RuntimeFunctionX64.UNWIND_FLAGS, /) -> bool: ... + + @property + def opcodes(self) -> list[Optional[unwind_x64.Code]]: ... + + def __str__(self) -> str: ... + + @property + def rva_end(self) -> int: ... + + @property + def unwind_rva(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def unwind_info(self) -> RuntimeFunctionX64.unwind_info_t | None: ... + +class RuntimeFunctionAArch64(ExceptionInfo): + class PACKED_FLAGS(enum.Enum): + UNPACKED = 0 + + PACKED = 1 + + PACKED_FRAGMENT = 2 + + RESERVED = 3 + + @property + def length(self) -> int: ... + + @property + def flag(self) -> RuntimeFunctionAArch64.PACKED_FLAGS: ... + + @property + def rva_end(self) -> int: ... + +class Debug(lief.Object): + def __init__(self) -> None: ... + + class TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Debug.TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + COFF = 1 + + CODEVIEW = 2 + + FPO = 3 + + MISC = 4 + + EXCEPTION = 5 + + FIXUP = 6 + + OMAP_TO_SRC = 7 + + OMAP_FROM_SRC = 8 + + BORLAND = 9 + + RESERVED10 = 10 + + CLSID = 11 + + VC_FEATURE = 12 + + POGO = 13 + + ILTCG = 14 + + MPX = 15 + + REPRO = 16 + + PDBCHECKSUM = 19 + + EX_DLLCHARACTERISTICS = 20 + + characteristics: int + + timestamp: int + + major_version: int + + minor_version: int + + @property + def type(self) -> Debug.TYPES: ... + + sizeof_data: int + + addressof_rawdata: int + + pointerto_rawdata: int + + @property + def section(self) -> Section | None: ... + + @property + def payload(self) -> memoryview: ... + + def copy(self) -> Optional[Debug]: ... + + def __str__(self) -> str: ... + +class CodeView(Debug): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: CodeView.SIGNATURES, /) -> None: ... + + class SIGNATURES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CodeView.SIGNATURES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + PDB_70 = 1396986706 + + PDB_20 = 808534606 + + CV_50 = 825311822 + + CV_41 = 959464014 + + @property + def cv_signature(self) -> CodeView.SIGNATURES: ... + + def __str__(self) -> str: ... + +class CodeViewPDB(CodeView): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, filename: str) -> None: ... + + @property + def parent(self) -> lief.PE.CodeView: ... + + @property + def guid(self) -> str: ... + + @property + def signature(self) -> list[int]: ... + + @signature.setter + def signature(self, arg: Sequence[int], /) -> None: ... + + age: int + + @property + def filename(self) -> Union[str, bytes]: ... + + @filename.setter + def filename(self, arg: str, /) -> None: ... + + def __str__(self) -> str: ... + +class Repro(Debug): + @property + def hash(self) -> memoryview: ... + + @hash.setter + def hash(self, arg: bytes, /) -> None: ... + + def __str__(self) -> str: ... + +class Pogo(Debug): + def __init__(self) -> None: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> PogoEntry: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Pogo.it_entries: ... + + def __next__(self) -> PogoEntry: ... + + class SIGNATURES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Pogo.SIGNATURES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 268435455 + + ZERO = 0 + + LCTG = 1280590663 + + PGI = 1346849024 + + PGO = 1346850560 + + PGU = 1346852096 + + SPGO = 1397770063 + + @property + def entries(self) -> Pogo.it_entries: ... + + @property + def signature(self) -> Pogo.SIGNATURES: ... + + def __str__(self) -> str: ... + +class PogoEntry(lief.Object): + def __init__(self) -> None: ... + + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + start_rva: int + + size: int + + def copy(self) -> PogoEntry: ... + + def __str__(self) -> str: ... + +class PDBChecksum(Debug): + def __init__(self, algo: PDBChecksum.HASH_ALGO, hash: Sequence[int]) -> None: ... + + class HASH_ALGO(enum.Enum): + UNKNOWN = 0 + + SHA256 = 1 + + @property + def hash(self) -> memoryview: ... + + @hash.setter + def hash(self, arg: Sequence[int], /) -> None: ... + + algorithm: PDBChecksum.HASH_ALGO + + def __str__(self) -> str: ... + +class VCFeature(Debug): + pre_vcpp: int + + c_cpp: int + + gs: int + + sdl: int + + guards: int + +class ExDllCharacteristics(Debug): + class CHARACTERISTICS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ExDllCharacteristics.CHARACTERISTICS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + CET_COMPAT = 1 + + CET_COMPAT_STRICT_MODE = 2 + + CET_SET_CONTEXT_IP_VALIDATION_RELAXED_MODE = 4 + + CET_DYNAMIC_APIS_ALLOW_IN_PROC = 8 + + CET_RESERVED_1 = 16 + + CET_RESERVED_2 = 32 + + FORWARD_CFI_COMPAT = 64 + + HOTPATCH_COMPATIBLE = 128 + + def has(self, characteristic: ExDllCharacteristics.CHARACTERISTICS) -> bool: ... + + @property + def ex_characteristics(self) -> ExDllCharacteristics.CHARACTERISTICS: ... + + @property + def ex_characteristics_list(self) -> list[ExDllCharacteristics.CHARACTERISTICS]: ... + +class FPO(Debug): + class FRAME_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> FPO.FRAME_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + FPO_ = 0 + + TRAP = 1 + + TSS = 2 + + NON_FPO = 3 + + class entry_t: + rva: int + + proc_size: int + + nb_locals: int + + parameters_size: int + + prolog_size: int + + nb_saved_regs: int + + use_seh: bool + + use_bp: bool + + reserved: int + + type: FPO.FRAME_TYPE + + def __str__(self) -> str: ... + + class it_entries: + def __getitem__(self, arg: int, /) -> FPO.entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FPO.it_entries: ... + + def __next__(self) -> FPO.entry_t: ... + + @property + def entries(self) -> FPO.it_entries: ... + +class ResourcesManager(lief.Object): + def __init__(self, node: ResourceNode) -> None: ... + + class it_const_dialogs: + def __getitem__(self, arg: int, /) -> ResourceDialog: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourcesManager.it_const_dialogs: ... + + def __next__(self) -> ResourceDialog: ... + + class it_const_icons: + def __getitem__(self, arg: int, /) -> ResourceIcon: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourcesManager.it_const_icons: ... + + def __next__(self) -> ResourceIcon: ... + + class it_const_accelerators: + def __getitem__(self, arg: int, /) -> ResourceAccelerator: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourcesManager.it_const_accelerators: ... + + def __next__(self) -> ResourceAccelerator: ... + + class string_entry_t: + string: str + + id: int + + def __str__(self) -> str: ... + + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ResourcesManager.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + CURSOR = 1 + + BITMAP = 2 + + ICON = 3 + + MENU = 4 + + DIALOG = 5 + + STRING = 6 + + FONTDIR = 7 + + FONT = 8 + + ACCELERATOR = 9 + + RCDATA = 10 + + MESSAGETABLE = 11 + + GROUP_CURSOR = 12 + + GROUP_ICON = 14 + + VERSION = 16 + + DLGINCLUDE = 17 + + PLUGPLAY = 19 + + VXD = 20 + + ANICURSOR = 21 + + ANIICON = 22 + + HTML = 23 + + MANIFEST = 24 + + @property + def has_manifest(self) -> bool: ... + + @property + def manifest(self) -> Union[str, bytes]: ... + + @manifest.setter + def manifest(self, arg: str, /) -> None: ... + + @property + def has_version(self) -> bool: ... + + @property + def version(self) -> list[ResourceVersion]: ... + + @property + def has_icons(self) -> bool: ... + + @property + def icons(self) -> ResourcesManager.it_const_icons: ... + + def change_icon(self, old_one: ResourceIcon, new_one: ResourceIcon) -> None: ... + + @property + def has_dialogs(self) -> bool: ... + + @property + def dialogs(self) -> ResourcesManager.it_const_dialogs: ... + + @property + def types(self) -> list[ResourcesManager.TYPE]: ... + + def add_icon(self, icon: ResourceIcon) -> None: ... + + def has_type(self, type: ResourcesManager.TYPE) -> bool: ... + + @property + def has_string_table(self) -> bool: ... + + @property + def string_table(self) -> list[ResourcesManager.string_entry_t]: ... + + @property + def has_html(self) -> bool: ... + + @property + def html(self) -> list[str]: ... + + @property + def has_accelerator(self) -> bool: ... + + @property + def accelerator(self) -> ResourcesManager.it_const_accelerators: ... + + def get_node_type(self, type: ResourcesManager.TYPE) -> ResourceNode | None: ... + + def print(self, max_depth: int = 0) -> str: ... + + def __str__(self) -> str: ... + +class ResourceNode(lief.Object): + class it_childs: + def __getitem__(self, arg: int, /) -> ResourceNode: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceNode.it_childs: ... + + def __next__(self) -> ResourceNode: ... + + @staticmethod + def parse(bytes: bytes, rva: int) -> Optional[ResourceNode]: ... + + id: int + + @property + def is_directory(self) -> bool: ... + + @property + def is_data(self) -> bool: ... + + @property + def has_name(self) -> bool: ... + + name: str + + @property + def childs(self) -> ResourceNode.it_childs: ... + + def add_child(self, node: ResourceNode) -> ResourceNode: ... + + @overload + def delete_child(self, node: ResourceNode) -> None: ... + + @overload + def delete_child(self, id: int) -> None: ... + + @property + def depth(self) -> int: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def copy(self) -> Optional[ResourceNode]: ... + + def __str__(self) -> str: ... + +class ResourceData(ResourceNode): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, content: Sequence[int], code_page: int = 0) -> None: ... + + code_page: int + + @property + def content(self) -> memoryview: ... + + @content.setter + def content(self, arg: bytes, /) -> None: ... + + reserved: int + + @property + def offset(self) -> int: ... + + def __str__(self) -> str: ... + +class ResourceDirectory(ResourceNode): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: int, /) -> None: ... + + characteristics: int + + time_date_stamp: int + + major_version: int + + minor_version: int + + numberof_name_entries: int + + numberof_id_entries: int + + def __str__(self) -> str: ... + +class ResourceVersion(lief.Object): + class fixed_file_info_t: + class VERSION_OS(enum.Enum): + DOS_WINDOWS16 = 65537 + + DOS_WINDOWS32 = 65540 + + NT = 262144 + + NT_WINDOWS32 = 262148 + + OS216 = 131072 + + OS216_PM16 = 131074 + + OS232 = 196608 + + OS232_PM32 = 196611 + + PM16 = 2 + + PM32 = 3 + + UNKNOWN = 0 + + WINCE = 327680 + + WINDOWS16 = 1 + + WINDOWS32 = 4 + + class FILE_TYPE(enum.Enum): + UNKNOWN = 0 + + APP = 1 + + DLL = 2 + + DRV = 3 + + FONT = 4 + + STATIC_LIB = 7 + + VXD = 5 + + class FILE_FLAGS(enum.Enum): + DEBUG = 1 + + INFO_INFERRED = 16 + + PATCHED = 4 + + PRERELEASE = 2 + + PRIVATEBUILD = 8 + + SPECIALBUILD = 32 + + class FILE_TYPE_DETAILS(enum.Enum): + DRV_COMM = 8589934602 + + DRV_DISPLAY = 8589934596 + + DRV_INPUTMETHOD = 8589934603 + + DRV_INSTALLABLE = 8589934600 + + DRV_KEYBOARD = 8589934594 + + DRV_LANGUAGE = 8589934595 + + DRV_MOUSE = 8589934597 + + DRV_NETWORK = 8589934598 + + DRV_PRINTER = 8589934593 + + DRV_SOUND = 8589934601 + + DRV_SYSTEM = 8589934599 + + DRV_VERSIONED_PRINTER = 12 + + FONT_RASTER = 17179869185 + + FONT_TRUETYPE = 17179869187 + + FONT_VECTOR = 17179869186 + + UNKNOWN = 0 + + signature: int + + struct_version: int + + file_version_ms: int + + file_version_ls: int + + product_version_ms: int + + product_version_ls: int + + file_flags_mask: int + + file_flags: int + + file_os: int + + file_type: int + + file_subtype: int + + file_date_ms: int + + file_date_ls: int + + def has(self, flag: ResourceVersion.fixed_file_info_t.FILE_FLAGS) -> bool: ... + + @property + def flags(self) -> list[ResourceVersion.fixed_file_info_t.FILE_FLAGS]: ... + + @property + def file_type_details(self) -> ResourceVersion.fixed_file_info_t.FILE_TYPE_DETAILS: ... + + def __str__(self) -> str: ... + + @property + def key(self) -> str: ... + + @property + def type(self) -> int: ... + + @property + def file_info(self) -> ResourceVersion.fixed_file_info_t: ... + + @property + def string_file_info(self) -> ResourceStringFileInfo | None: ... + + @property + def var_file_info(self) -> ResourceVarFileInfo | None: ... + + def __str__(self) -> str: ... + +class ResourceStringTable(lief.Object): + class it_entries: + def __getitem__(self, arg: int, /) -> ResourceStringTable.entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceStringTable.it_entries: ... + + def __next__(self) -> ResourceStringTable.entry_t: ... + + class entry_t: + key: str + + value: str + + def __bool__(self) -> bool: ... + + @property + def key(self) -> str: ... + + @property + def type(self) -> int: ... + + @property + def entries(self) -> ResourceStringTable.it_entries: ... + + def get(self, key: str) -> str | None: ... + + def __getitem__(self, arg: str, /) -> str | None: ... + +class ResourceStringFileInfo(lief.Object): + class it_elements: + def __getitem__(self, arg: int, /) -> ResourceStringTable: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceStringFileInfo.it_elements: ... + + def __next__(self) -> ResourceStringTable: ... + + @property + def type(self) -> int: ... + + @property + def key(self) -> str: ... + + @property + def children(self) -> ResourceStringFileInfo.it_elements: ... + + def __str__(self) -> str: ... + +class ResourceVar: + @property + def type(self) -> int: ... + + @property + def key(self) -> str: ... + + @property + def values(self) -> list[int]: ... + + def __str__(self) -> str: ... + +class ResourceVarFileInfo(lief.Object): + class it_vars: + def __getitem__(self, arg: int, /) -> ResourceVar: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceVarFileInfo.it_vars: ... + + def __next__(self) -> ResourceVar: ... + + @property + def type(self) -> int: ... + + @property + def key(self) -> str: ... + + @property + def vars(self) -> ResourceVarFileInfo.it_vars: ... + + def __str__(self) -> str: ... + +class ResourceIcon(lief.Object): + id: int + + lang: int + + sublang: int + + width: int + + height: int + + color_count: int + + reserved: int + + planes: int + + bit_count: int + + @property + def pixels(self) -> memoryview: ... + + @pixels.setter + def pixels(self, arg: Sequence[int], /) -> None: ... + + def save(self, filepath: str) -> None: ... + + def serialize(self) -> bytes: ... + + @staticmethod + def from_serialization(arg: bytes, /) -> Union[ResourceIcon, lief.lief_errors]: ... + + def __str__(self) -> str: ... + +class ResourceDialog(lief.Object): + class DIALOG_STYLES(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ResourceDialog.DIALOG_STYLES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + ABSALIGN = 1 + + SYSMODAL = 2 + + LOCALEDIT = 32 + + SETFONT = 64 + + MODALFRAME = 128 + + NOIDLEMSG = 256 + + SETFOREGROUND = 512 + + S3DLOOK = 4 + + FIXEDSYS = 8 + + NOFAILCREATE = 16 + + CONTROL = 1024 + + CENTER = 2048 + + CENTERMOUSE = 4096 + + CONTEXTHELP = 8192 + + SHELLFONT = 72 + + class WINDOW_STYLES(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ResourceDialog.WINDOW_STYLES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + OVERLAPPED = 0 + + POPUP = 2147483648 + + CHILD = 1073741824 + + MINIMIZE = 536870912 + + VISIBLE = 268435456 + + DISABLED = 134217728 + + CLIPSIBLINGS = 67108864 + + CLIPCHILDREN = 33554432 + + MAXIMIZE = 16777216 + + CAPTION = 12582912 + + BORDER = 8388608 + + DLGFRAME = 4194304 + + VSCROLL = 2097152 + + HSCROLL = 1048576 + + SYSMENU = 524288 + + THICKFRAME = 262144 + + GROUP = 131072 + + TABSTOP = 65536 + + class WINDOW_EXTENDED_STYLES(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ResourceDialog.WINDOW_EXTENDED_STYLES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DLGMODALFRAME = 1 + + NOPARENTNOTIFY = 4 + + TOPMOST = 8 + + ACCEPTFILES = 16 + + TRANSPARENT_STY = 32 + + MDICHILD = 64 + + TOOLWINDOW = 128 + + WINDOWEDGE = 256 + + CLIENTEDGE = 512 + + CONTEXTHELP = 1024 + + RIGHT = 4096 + + LEFT = 0 + + RTLREADING = 8192 + + LEFTSCROLLBAR = 16384 + + CONTROLPARENT = 65536 + + STATICEDGE = 131072 + + APPWINDOW = 262144 + + class CONTROL_STYLES(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ResourceDialog.CONTROL_STYLES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + TOP = 1 + + NOMOVEY = 2 + + BOTTOM = 3 + + NORESIZE = 4 + + NOPARENTALIGN = 8 + + ADJUSTABLE = 32 + + NODIVIDER = 64 + + VERT = 128 + + LEFT = 129 + + RIGHT = 131 + + NOMOVEX = 130 + + class TYPE(enum.Enum): + UNKNOWN = 0 + + REGULAR = 1 + + EXTENDED = 2 + + class Item: + style: int + + extended_style: int + + id: int + + x: int + + y: int + + cx: int + + cy: int + + @overload + def has(self, style: ResourceDialog.WINDOW_STYLES) -> bool: ... + + @overload + def has(self, style: ResourceDialog.CONTROL_STYLES) -> bool: ... + + @property + def window_styles(self) -> list[ResourceDialog.WINDOW_STYLES]: ... + + @property + def control_styles(self) -> list[ResourceDialog.CONTROL_STYLES]: ... + + @property + def clazz(self) -> Optional[Union[int, str]]: ... + + @property + def title(self) -> Optional[Union[int, str]]: ... + + @property + def creation_data(self) -> memoryview: ... + + def __str__(self) -> str: ... + + @property + def type(self) -> ResourceDialog.TYPE: ... + + style: int + + extended_style: int + + x: int + + y: int + + cx: int + + cy: int + + @overload + def has(self, arg: ResourceDialog.DIALOG_STYLES, /) -> bool: ... + + @overload + def has(self, arg: ResourceDialog.WINDOW_STYLES, /) -> bool: ... + + @overload + def has(self, arg: ResourceDialog.WINDOW_EXTENDED_STYLES, /) -> bool: ... + + @property + def styles_list(self) -> list[ResourceDialog.DIALOG_STYLES]: ... + + @property + def windows_styles_list(self) -> list[ResourceDialog.WINDOW_STYLES]: ... + + @property + def windows_ext_styles_list(self) -> list[ResourceDialog.WINDOW_EXTENDED_STYLES]: ... + + title: str + + @property + def menu(self) -> Optional[Union[int, str]]: ... + + @property + def window_class(self) -> Optional[Union[int, str]]: ... + + def copy(self) -> Optional[ResourceDialog]: ... + + def __str__(self) -> str: ... + +class ResourceDialogExtended(ResourceDialog): + def __init__(self) -> None: ... + + class it_items: + def __getitem__(self, arg: int, /) -> ResourceDialogExtended.Item: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceDialogExtended.it_items: ... + + def __next__(self) -> ResourceDialogExtended.Item: ... + + class font_t: + point_size: int + + weight: int + + italic: bool + + charset: int + + typeface: str + + def __bool__(self) -> bool: ... + + def __str__(self) -> str: ... + + class Item(ResourceDialog.Item): + def __init__(self) -> None: ... + + help_id: int + + def __str__(self) -> str: ... + + @property + def version(self) -> int: ... + + @property + def signature(self) -> int: ... + + @property + def help_id(self) -> int: ... + + @property + def items(self) -> ResourceDialogExtended.it_items: ... + + @property + def font(self) -> ResourceDialogExtended.font_t: ... + + def add_item(self, item: ResourceDialogExtended.Item) -> None: ... + + def __str__(self) -> str: ... + +class ResourceDialogRegular(ResourceDialog): + def __init__(self) -> None: ... + + class it_items: + def __getitem__(self, arg: int, /) -> ResourceDialogRegular.Item: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> ResourceDialogRegular.it_items: ... + + def __next__(self) -> ResourceDialogRegular.Item: ... + + class font_t: + point_size: int + + name: str + + def __bool__(self) -> bool: ... + + def __str__(self) -> str: ... + + class Item(ResourceDialog.Item): + def __init__(self) -> None: ... + + def __str__(self) -> str: ... + + @property + def nb_items(self) -> int: ... + + @property + def items(self) -> ResourceDialogRegular.it_items: ... + + @property + def font(self) -> ResourceDialogRegular.font_t: ... + + def add_item(self, item: ResourceDialogRegular.Item) -> None: ... + + def __str__(self) -> str: ... + +class ACCELERATOR_CODES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> ACCELERATOR_CODES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + LBUTTON = 1 + + RBUTTON = 2 + + CANCEL = 3 + + MBUTTON = 4 + + XBUTTON1_K = 5 + + XBUTTON2_K = 6 + + BACK = 8 + + TAB = 9 + + CLEAR = 12 + + RETURN = 13 + + SHIFT = 16 + + CONTROL = 17 + + MENU = 18 + + PAUSE = 19 + + CAPITAL = 20 + + KANA = 21 + + IME_ON = 22 + + JUNJA = 23 + + FINAL = 24 + + KANJI = 25 + + IME_OFF = 26 + + ESCAPE = 27 + + CONVERT = 28 + + NONCONVERT = 29 + + ACCEPT = 30 + + MODECHANGE = 31 + + SPACE = 32 + + PRIOR = 33 + + NEXT = 34 + + END = 35 + + HOME = 36 + + LEFT = 37 + + UP = 38 + + RIGHT = 39 + + DOWN = 40 + + SELECT = 41 + + PRINT = 42 + + EXECUTE = 43 + + SNAPSHOT = 44 + + INSERT = 45 + + DELETE_K = 46 + + HELP = 47 + + NUM_0 = 48 + + NUM_1 = 49 + + NUM_2 = 50 + + NUM_3 = 51 + + NUM_4 = 52 + + NUM_5 = 53 + + NUM_6 = 54 + + NUM_7 = 55 + + NUM_8 = 56 + + NUM_9 = 57 + + A = 65 + + B = 66 + + C = 67 + + D = 68 + + E = 69 + + F = 70 + + G = 71 + + H = 72 + + I = 73 + + J = 74 + + K = 75 + + L = 76 + + M = 77 + + N = 78 + + O = 79 + + P = 80 + + Q = 81 + + R = 82 + + S = 83 + + T = 84 + + U = 85 + + V = 86 + + W = 87 + + X = 88 + + Y = 89 + + Z = 90 + + LWIN = 91 + + RWIN = 92 + + APPS = 93 + + SLEEP = 95 + + NUMPAD0 = 96 + + NUMPAD1 = 97 + + NUMPAD2 = 98 + + NUMPAD3 = 99 + + NUMPAD4 = 100 + + NUMPAD5 = 101 + + NUMPAD6 = 102 + + NUMPAD7 = 103 + + NUMPAD8 = 104 + + NUMPAD9 = 105 + + MULTIPLY = 106 + + ADD = 107 + + SEPARATOR = 108 + + SUBTRACT = 109 + + DECIMAL = 110 + + DIVIDE = 111 + + F1 = 112 + + F2 = 113 + + F3 = 114 + + F4 = 115 + + F5 = 116 + + F6 = 117 + + F7 = 118 + + F8 = 119 + + F9 = 120 + + F10 = 121 + + F11 = 122 + + F12 = 123 + + F13 = 124 + + F14 = 125 + + F15 = 126 + + F16 = 127 + + F17 = 128 + + F18 = 129 + + F19 = 130 + + F20 = 131 + + F21 = 132 + + F22 = 133 + + F23 = 134 + + F24 = 135 + + NUMLOCK = 144 + + SCROLL = 145 + + LSHIFT = 160 + + RSHIFT = 161 + + LCONTROL = 162 + + RCONTROL = 163 + + LMENU = 164 + + RMENU = 165 + + BROWSER_BACK = 166 + + BROWSER_FORWARD = 167 + + BROWSER_REFRESH = 168 + + BROWSER_STOP = 169 + + BROWSER_SEARCH = 170 + + BROWSER_FAVORITES = 171 + + BROWSER_HOME = 172 + + VOLUME_MUTE = 173 + + VOLUME_DOWN = 174 + + VOLUME_UP = 175 + + MEDIA_NEXT_TRACK = 176 + + MEDIA_PREV_TRACK = 177 + + MEDIA_STOP = 178 + + MEDIA_PLAY_PAUSE = 179 + + LAUNCH_MAIL = 180 + + LAUNCH_MEDIA_SELECT = 181 + + LAUNCH_APP1 = 182 + + LAUNCH_APP2 = 183 + + OEM_1 = 186 + + OEM_PLUS = 187 + + OEM_COMMA = 188 + + OEM_MINUS = 189 + + OEM_PERIOD = 190 + + OEM_2 = 191 + + OEM_4 = 219 + + OEM_5 = 220 + + OEM_6 = 221 + + OEM_7 = 222 + + OEM_8 = 223 + + OEM_102 = 226 + + PROCESSKEY = 229 + + PACKET = 231 + + ATTN = 246 + + CRSEL = 247 + + EXSEL = 248 + + EREOF = 249 + + PLAY = 250 + + ZOOM = 251 + + NONAME = 252 + + PA1 = 253 + + OEM_CLEAR = 254 + +class ResourceAccelerator(lief.Object): + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> ResourceAccelerator.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + VIRTKEY = 1 + + NOINVERT = 2 + + SHIFT = 4 + + CONTROL = 8 + + ALT = 16 + + END = 128 + + @property + def flags(self) -> int: ... + + @property + def ansi(self) -> int: ... + + @property + def ansi_str(self) -> str: ... + + @property + def id(self) -> int: ... + + @property + def padding(self) -> int: ... + + def has(self, arg: ResourceAccelerator.FLAGS, /) -> bool: ... + + def add(self, arg: ResourceAccelerator.FLAGS, /) -> ResourceAccelerator: ... + + def remove(self, arg: ResourceAccelerator.FLAGS, /) -> ResourceAccelerator: ... + + def __str__(self) -> str: ... + +class RESOURCE_LANGS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> RESOURCE_LANGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NEUTRAL = 0 + + INVARIANT = 127 + + AFRIKAANS = 54 + + ALBANIAN = 28 + + ARABIC = 1 + + ARMENIAN = 43 + + ASSAMESE = 77 + + AZERI = 44 + + BASQUE = 45 + + BELARUSIAN = 35 + + BANGLA = 69 + + BULGARIAN = 2 + + CATALAN = 3 + + CHINESE = 4 + + CROATIAN = 26 + + BOSNIAN = 26 + + CZECH = 5 + + DANISH = 6 + + DIVEHI = 101 + + DUTCH = 19 + + ENGLISH = 9 + + ESTONIAN = 37 + + FAEROESE = 56 + + FARSI = 41 + + FINNISH = 11 + + FRENCH = 12 + + GALICIAN = 86 + + GEORGIAN = 55 + + GERMAN = 7 + + GREEK = 8 + + GUJARATI = 71 + + HEBREW = 13 + + HINDI = 57 + + HUNGARIAN = 14 + + ICELANDIC = 15 + + INDONESIAN = 33 + + ITALIAN = 16 + + JAPANESE = 17 + + KANNADA = 75 + + KASHMIRI = 96 + + KAZAK = 63 + + KONKANI = 87 + + KOREAN = 18 + + KYRGYZ = 64 + + LATVIAN = 38 + + LITHUANIAN = 39 + + MACEDONIAN = 47 + + MALAY = 62 + + MALAYALAM = 76 + + MANIPURI = 88 + + MARATHI = 78 + + MONGOLIAN = 80 + + NEPALI = 97 + + NORWEGIAN = 20 + + ORIYA = 72 + + POLISH = 21 + + PORTUGUESE = 22 + + PUNJABI = 70 + + ROMANIAN = 24 + + RUSSIAN = 25 + + SANSKRIT = 79 + + SERBIAN = 26 + + SINDHI = 89 + + SLOVAK = 27 + + SLOVENIAN = 36 + + SPANISH = 10 + + SWAHILI = 65 + + SWEDISH = 29 + + SYRIAC = 90 + + TAMIL = 73 + + TATAR = 68 + + TELUGU = 74 + + THAI = 30 + + TURKISH = 31 + + UKRAINIAN = 34 + + URDU = 32 + + UZBEK = 67 + + VIETNAMESE = 42 + + GAELIC = 60 + + MALTESE = 58 + + MAORI = 40 + + RHAETO_ROMANCE = 23 + + SAMI = 59 + + SORBIAN = 46 + + SUTU = 48 + + TSONGA = 49 + + TSWANA = 50 + + VENDA = 51 + + XHOSA = 52 + + ZULU = 53 + + ESPERANTO = 143 + + WALON = 144 + + CORNISH = 145 + + WELSH = 146 + + BRETON = 147 + + INUKTITUT = 93 + + IRISH = 60 + + LOWER_SORBIAN = 46 + + PULAR = 103 + + QUECHUA = 107 + + TAMAZIGHT = 95 + + TIGRINYA = 115 + + VALENCIAN = 3 + +class Signature(lief.Object): + class VERIFICATION_FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Signature.VERIFICATION_FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + OK = 0 + + INVALID_SIGNER = 1 + + UNSUPPORTED_ALGORITHM = 2 + + INCONSISTENT_DIGEST_ALGORITHM = 4 + + CERT_NOT_FOUND = 8 + + CORRUPTED_CONTENT_INFO = 16 + + CORRUPTED_AUTH_DATA = 32 + + MISSING_PKCS9_MESSAGE_DIGEST = 64 + + BAD_DIGEST = 128 + + BAD_SIGNATURE = 256 + + NO_SIGNATURE = 512 + + CERT_EXPIRED = 1024 + + CERT_FUTURE = 2048 + + class VERIFICATION_CHECKS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Signature.VERIFICATION_CHECKS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DEFAULT = 1 + + HASH_ONLY = 2 + + LIFETIME_SIGNING = 4 + + SKIP_CERT_TIME = 8 + + class it_const_crt: + def __getitem__(self, arg: int, /) -> x509: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Signature.it_const_crt: ... + + def __next__(self) -> x509: ... + + class it_const_signers_t: + def __getitem__(self, arg: int, /) -> SignerInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Signature.it_const_signers_t: ... + + def __next__(self) -> SignerInfo: ... + + @overload + @staticmethod + def parse(path: Union[str | os.PathLike]) -> Optional[Signature]: ... + + @overload + @staticmethod + def parse(raw: Sequence[int], skip_header: bool = False) -> Optional[Signature]: ... + + @property + def version(self) -> int: ... + + @property + def digest_algorithm(self) -> ALGORITHMS: ... + + @property + def content_info(self) -> ContentInfo: ... + + @property + def certificates(self) -> Signature.it_const_crt: ... + + @property + def signers(self) -> Signature.it_const_signers_t: ... + + def find_crt(self, serialno: Sequence[int]) -> x509 | None: ... + + @overload + def find_crt_subject(self, subject: str) -> x509 | None: ... + + @overload + def find_crt_subject(self, subject: str, serialno: Sequence[int]) -> x509 | None: ... + + @overload + def find_crt_issuer(self, issuer: str) -> x509 | None: ... + + @overload + def find_crt_issuer(self, issuer: str, serialno: Sequence[int]) -> x509 | None: ... + + def check(self, checks: Signature.VERIFICATION_CHECKS = Signature.VERIFICATION_CHECKS.DEFAULT) -> Signature.VERIFICATION_FLAGS: ... + + @property + def raw_der(self) -> memoryview: ... + + def __str__(self) -> str: ... + +class RsaInfo: + @property + def has_public_key(self) -> bool: ... + + @property + def has_private_key(self) -> bool: ... + + @property + def N(self) -> bytes: ... + + @property + def E(self) -> bytes: ... + + @property + def D(self) -> bytes: ... + + @property + def P(self) -> bytes: ... + + @property + def Q(self) -> bytes: ... + + @property + def key_size(self) -> int: ... + + @property + def __len__(self) -> int: ... + + def __str__(self) -> str: ... + +class x509(lief.Object): + class VERIFICATION_FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> x509.VERIFICATION_FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + OK = 0 + + BADCERT_EXPIRED = 1 + + BADCERT_REVOKED = 2 + + BADCERT_CN_MISMATCH = 4 + + BADCERT_NOT_TRUSTED = 8 + + BADCRL_NOT_TRUSTED = 16 + + BADCRL_EXPIRED = 32 + + BADCERT_MISSING = 64 + + BADCERT_SKIP_VERIFY = 128 + + BADCERT_OTHERNATURE = 256 + + BADCERT_FUTURE = 512 + + BADCRL_FUTURE = 1024 + + BADCERT_KEY_USAGE = 2048 + + BADCERT_EXT_KEY_USAGE = 4096 + + BADCERT_NS_CERT_TYPE = 8192 + + BADCERT_BAD_MD = 16384 + + BADCERT_BAD_PK = 32768 + + BADCERT_BAD_KEY = 65536 + + BADCRL_BAD_MD = 131072 + + BADCRL_BAD_PK = 262144 + + BADCRL_BAD_KEY = 524288 + + class KEY_TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> x509.KEY_TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + RSA = 1 + + ECKEY = 2 + + ECKEY_DH = 3 + + ECDSA = 4 + + RSA_ALT = 5 + + RSASSA_PSS = 6 + + class KEY_USAGE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> x509.KEY_USAGE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + DIGITAL_SIGNATURE = 0 + + NON_REPUDIATION = 1 + + KEY_ENCIPHERMENT = 2 + + DATA_ENCIPHERMENT = 3 + + KEY_AGREEMENT = 4 + + KEY_CERT_SIGN = 5 + + CRL_SIGN = 6 + + ENCIPHER_ONLY = 7 + + DECIPHER_ONLY = 8 + + @overload + @staticmethod + def parse(path: str) -> list[x509]: ... + + @overload + @staticmethod + def parse(raw: Sequence[int]) -> list[x509]: ... + + @property + def version(self) -> int: ... + + @property + def serial_number(self) -> bytes: ... + + @property + def signature_algorithm(self) -> str: ... + + @property + def valid_from(self) -> list[int]: ... + + @property + def valid_to(self) -> list[int]: ... + + @property + def issuer(self) -> Union[str, bytes]: ... + + @property + def subject(self) -> Union[str, bytes]: ... + + @property + def raw(self) -> bytes: ... + + @property + def key_type(self) -> x509.KEY_TYPES: ... + + @property + def rsa_info(self) -> Optional[RsaInfo]: ... + + @property + def key_usage(self) -> list[x509.KEY_USAGE]: ... + + @property + def ext_key_usage(self) -> list[str]: ... + + @property + def certificate_policies(self) -> list[str]: ... + + @property + def is_ca(self) -> bool: ... + + @property + def signature(self) -> bytes: ... + + def verify(self, ca: x509) -> x509.VERIFICATION_FLAGS: ... + + def is_trusted_by(self, ca_list: Sequence[x509]) -> x509.VERIFICATION_FLAGS: ... + + def __str__(self) -> str: ... + +class ContentInfo(lief.Object): + class Content(lief.Object): + @property + def content_type(self) -> str: ... + + def copy(self) -> Optional[ContentInfo.Content]: ... + + @property + def content_type(self) -> str: ... + + @property + def digest(self) -> bytes: ... + + @property + def digest_algorithm(self) -> ALGORITHMS: ... + + @property + def value(self) -> ContentInfo.Content: ... + + def copy(self) -> ContentInfo: ... + + def __str__(self) -> str: ... + +class GenericContent(ContentInfo.Content): + pass + +class SpcIndirectData(ContentInfo.Content): + @property + def digest_algorithm(self) -> ALGORITHMS: ... + + @property + def digest(self) -> memoryview: ... + + @property + def file(self) -> str: ... + + @property + def url(self) -> str: ... + + def __str__(self) -> str: ... + +class SignerInfo(lief.Object): + class it_const_attributes_t: + def __getitem__(self, arg: int, /) -> Attribute: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> SignerInfo.it_const_attributes_t: ... + + def __next__(self) -> Attribute: ... + + @property + def version(self) -> int: ... + + @property + def serial_number(self) -> bytes: ... + + @property + def issuer(self) -> Union[str, bytes]: ... + + @property + def digest_algorithm(self) -> ALGORITHMS: ... + + @property + def encryption_algorithm(self) -> ALGORITHMS: ... + + @property + def encrypted_digest(self) -> bytes: ... + + @property + def authenticated_attributes(self) -> SignerInfo.it_const_attributes_t: ... + + @property + def unauthenticated_attributes(self) -> SignerInfo.it_const_attributes_t: ... + + def get_attribute(self, type: Attribute.TYPE) -> Attribute | None: ... + + def get_auth_attribute(self, type: Attribute.TYPE) -> Attribute | None: ... + + def get_unauth_attribute(self, type: Attribute.TYPE) -> Attribute | None: ... + + @property + def cert(self) -> x509 | None: ... + + def __str__(self) -> str: ... + +class CodeIntegrity(lief.Object): + def __init__(self) -> None: ... + + flags: int + + catalog: int + + catalog_offset: int + + reserved: int + + def __str__(self) -> str: ... + +class Attribute(lief.Object): + class TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Attribute.TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + CONTENT_TYPE = 1 + + GENERIC_TYPE = 2 + + SPC_SP_OPUS_INFO = 4 + + MS_COUNTER_SIGN = 6 + + MS_SPC_NESTED_SIGN = 7 + + MS_SPC_STATEMENT_TYPE = 8 + + SPC_RELAXED_PE_MARKER_CHECK = 5 + + SIGNING_CERTIFICATE_V2 = 3 + + MS_PLATFORM_MANIFEST_BINARY_ID = 9 + + PKCS9_AT_SEQUENCE_NUMBER = 10 + + PKCS9_COUNTER_SIGNATURE = 11 + + PKCS9_MESSAGE_DIGEST = 12 + + PKCS9_SIGNING_TIME = 13 + + @property + def type(self) -> Attribute.TYPE: ... + + def __str__(self) -> str: ... + +class ContentType(Attribute): + @property + def oid(self) -> str: ... + +class GenericType(Attribute): + @property + def oid(self) -> str: ... + + @property + def raw_content(self) -> memoryview: ... + +class MsSpcNestedSignature(Attribute): + @property + def signature(self) -> Signature: ... + +class MsSpcStatementType(Attribute): + @property + def oid(self) -> str: ... + +class MsManifestBinaryID(Attribute): + manifest_id: str + + def __str__(self) -> str: ... + +class PKCS9AtSequenceNumber(Attribute): + @property + def number(self) -> int: ... + +class PKCS9CounterSignature(Attribute): + @property + def signer(self) -> SignerInfo: ... + +class PKCS9MessageDigest(Attribute): + @property + def digest(self) -> bytes: ... + +class PKCS9SigningTime(Attribute): + @property + def time(self) -> list[int]: ... + +class SpcSpOpusInfo(Attribute): + @property + def program_name(self) -> Union[str, bytes]: ... + + @property + def more_info(self) -> Union[str, bytes]: ... + +class MsCounterSign(Attribute): + class it_const_crt: + def __getitem__(self, arg: int, /) -> x509: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> MsCounterSign.it_const_crt: ... + + def __next__(self) -> x509: ... + + class it_const_signers_t: + def __getitem__(self, arg: int, /) -> SignerInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> MsCounterSign.it_const_signers_t: ... + + def __next__(self) -> SignerInfo: ... + + @property + def version(self) -> int: ... + + @property + def digest_algorithm(self) -> ALGORITHMS: ... + + @property + def content_info(self) -> ContentInfo: ... + + @property + def certificates(self) -> MsCounterSign.it_const_crt: ... + + @property + def signers(self) -> MsCounterSign.it_const_signers_t: ... + +class SpcRelaxedPeMarkerCheck(Attribute): + @property + def value(self) -> int: ... + +class SigningCertificateV2(Attribute): + pass + +class PKCS9TSTInfo(ContentInfo.Content): + pass + +class CHPEMetadata: + class KIND(enum.Enum): + UNKNOWN = 0 + + ARM64 = 1 + + X86 = 2 + + @property + def version(self) -> int: ... + + @property + def kind(self) -> CHPEMetadata.KIND: ... + + def copy(self) -> Optional[CHPEMetadata]: ... + + def __str__(self) -> str: ... + +class CHPEMetadataARM64(CHPEMetadata): + class it_range_entries: + def __getitem__(self, arg: int, /) -> CHPEMetadataARM64.range_entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> CHPEMetadataARM64.it_range_entries: ... + + def __next__(self) -> CHPEMetadataARM64.range_entry_t: ... + + class it_redirection_entries: + def __getitem__(self, arg: int, /) -> CHPEMetadataARM64.redirection_entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> CHPEMetadataARM64.it_redirection_entries: ... + + def __next__(self) -> CHPEMetadataARM64.redirection_entry_t: ... + + class it_code_range_entry_point: + def __getitem__(self, arg: int, /) -> CHPEMetadataARM64.code_range_entry_point_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> CHPEMetadataARM64.it_code_range_entry_point: ... + + def __next__(self) -> CHPEMetadataARM64.code_range_entry_point_t: ... + + class range_entry_t: + class TYPE(enum.Enum): + ARM64 = 0 + + ARM64EC = 1 + + AMD64 = 2 + + start_offset: int + + length: int + + @property + def type(self) -> CHPEMetadataARM64.range_entry_t.TYPE: ... + + @property + def start(self) -> int: ... + + @property + def end(self) -> int: ... + + class redirection_entry_t: + src: int + + dst: int + + class code_range_entry_point_t: + start_rva: int + + end_rva: int + + entrypoint: int + + code_map: int + + code_map_count: int + + code_ranges_to_entrypoints: int + + redirection_metadata: int + + os_arm64x_dispatch_call_no_redirect: int + + os_arm64x_dispatch_ret: int + + os_arm64x_dispatch_call: int + + os_arm64x_dispatch_icall: int + + os_arm64x_dispatch_icall_cfg: int + + alternate_entry_point: int + + auxiliary_iat: int + + code_ranges_to_entry_points_count: int + + redirection_metadata_count: int + + get_x64_information_function_pointer: int + + set_x64_information_function_pointer: int + + extra_rfe_table: int + + extra_rfe_table_size: int + + os_arm64x_dispatch_fptr: int + + auxiliary_iat_copy: int + + auxiliary_delay_import: int + + auxiliary_delay_import_copy: int + + bitfield_info: int + + @property + def code_ranges(self) -> CHPEMetadataARM64.it_range_entries: ... + + @property + def redirections(self) -> CHPEMetadataARM64.it_redirection_entries: ... + + @property + def code_range_entry_point(self) -> CHPEMetadataARM64.it_code_range_entry_point: ... + +class CHPEMetadataX86(CHPEMetadata): + chpe_code_address_range_offset: int + + chpe_code_address_range_count: int + + wowa64_exception_handler_function_pointer: int + + wowa64_dispatch_call_function_pointer: int + + wowa64_dispatch_indirect_call_function_pointer: int + + wowa64_dispatch_indirect_call_cfg_function_pointer: int + + wowa64_dispatch_ret_function_pointer: int + + wowa64_dispatch_ret_leaf_function_pointer: int + + wowa64_dispatch_jump_function_pointer: int + + @property + def compiler_iat_pointer(self) -> int | None: ... + + @compiler_iat_pointer.setter + def compiler_iat_pointer(self, arg: int, /) -> CHPEMetadataX86: ... + + @property + def wowa64_rdtsc_function_pointer(self) -> int | None: ... + + @wowa64_rdtsc_function_pointer.setter + def wowa64_rdtsc_function_pointer(self, arg: int, /) -> CHPEMetadataX86: ... + +class DynamicRelocation: + class IMAGE_DYNAMIC_RELOCATION(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DynamicRelocation.IMAGE_DYNAMIC_RELOCATION: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + RELOCATION_GUARD_RF_PROLOGUE = 1 + + RELOCATION_GUARD_RF_EPILOGUE = 2 + + RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER = 3 + + RELOCATION_GUARD_INDIR_CONTROL_TRANSFER = 4 + + RELOCATION_GUARD_SWITCHTABLE_BRANCH = 5 + + RELOCATION_ARM64X = 6 + + RELOCATION_FUNCTION_OVERRIDE = 7 + + RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER = 8 + + @property + def version(self) -> int: ... + + symbol: int + + @property + def fixups(self) -> DynamicFixup | None: ... + + def __str__(self) -> str: ... + + def copy(self) -> Optional[DynamicRelocation]: ... + +class DynamicRelocationV1(DynamicRelocation): + pass + +class DynamicRelocationV2(DynamicRelocation): + pass + +class DynamicFixup: + class KIND(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DynamicFixup.KIND: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + GENERIC = 1 + + ARM64X = 2 + + FUNCTION_OVERRIDE = 3 + + ARM64_KERNEL_IMPORT_CALL_TRANSFER = 4 + + @property + def kind(self) -> DynamicFixup.KIND: ... + + def __str__(self) -> str: ... + + def copy(self) -> Optional[DynamicFixup]: ... + +class DynamicFixupARM64X(DynamicFixup): + class FIXUP_TYPE(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DynamicFixupARM64X.FIXUP_TYPE: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + ZEROFILL = 0 + + VALUE = 1 + + DELTA = 2 + + class reloc_entry_t: + rva: int + + type: DynamicFixupARM64X.FIXUP_TYPE + + size: int + + @property + def raw_bytes(self) -> list[int]: ... + + @raw_bytes.setter + def raw_bytes(self, arg: Sequence[int], /) -> None: ... + + value: int + + def __str__(self) -> str: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> DynamicFixupARM64X.reloc_entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupARM64X.it_relocations: ... + + def __next__(self) -> DynamicFixupARM64X.reloc_entry_t: ... + + @property + def relocations(self) -> DynamicFixupARM64X.it_relocations: ... + +class DynamicFixupControlTransfer(DynamicFixup): + NO_IAT_INDEX: Final[int] = ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> DynamicFixupControlTransfer.reloc_entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupControlTransfer.it_relocations: ... + + def __next__(self) -> DynamicFixupControlTransfer.reloc_entry_t: ... + + class reloc_entry_t: + rva: int + + is_call: bool + + iat_index: int + + def __str__(self) -> str: ... + + @property + def relocations(self) -> DynamicFixupControlTransfer.it_relocations: ... + +class DynamicFixupARM64Kernel(DynamicFixup): + NO_IAT_INDEX: Final[int] = ... + + class IMPORT_TYPE(enum.Enum): + STATIC = 0 + + DELAYED = 1 + + class it_relocations: + def __getitem__(self, arg: int, /) -> DynamicFixupARM64Kernel.reloc_entry_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupARM64Kernel.it_relocations: ... + + def __next__(self) -> DynamicFixupARM64Kernel.reloc_entry_t: ... + + class reloc_entry_t: + rva: int + + indirect_call: bool + + register_index: int + + import_type: DynamicFixupARM64Kernel.IMPORT_TYPE + + iat_index: int + + def __str__(self) -> str: ... + + @property + def relocations(self) -> DynamicFixupARM64Kernel.it_relocations: ... + +class DynamicFixupGeneric(DynamicFixup): + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupGeneric.it_relocations: ... + + def __next__(self) -> Relocation: ... + + @property + def relocations(self) -> DynamicFixupGeneric.it_relocations: ... + +class DynamicFixupUnknown(DynamicFixup): + @property + def payload(self) -> memoryview: ... + +class FunctionOverrideInfo: + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupGeneric.it_relocations: ... + + def __next__(self) -> Relocation: ... + + original_rva: int + + bdd_offset: int + + @property + def rva_size(self) -> int: ... + + @property + def base_reloc_size(self) -> int: ... + + @property + def relocations(self) -> DynamicFixupGeneric.it_relocations: ... + + @property + def functions_rva(self) -> list[int]: ... + + def __str__(self) -> str: ... + +class FunctionOverride(DynamicFixup): + class image_bdd_dynamic_relocation_t: + left: int + + right: int + + value: int + + class image_bdd_info_t: + version: int + + original_size: int + + original_offset: int + + @property + def relocations(self) -> list[FunctionOverride.image_bdd_dynamic_relocation_t]: ... + + @relocations.setter + def relocations(self, arg: Sequence[FunctionOverride.image_bdd_dynamic_relocation_t], /) -> None: ... + + @property + def payload(self) -> list[int]: ... + + @payload.setter + def payload(self, arg: Sequence[int], /) -> None: ... + + class it_func_overriding_info: + def __getitem__(self, arg: int, /) -> FunctionOverrideInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FunctionOverride.it_func_overriding_info: ... + + def __next__(self) -> FunctionOverrideInfo: ... + + class it_bdd_info: + def __getitem__(self, arg: int, /) -> FunctionOverride.image_bdd_info_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> FunctionOverride.it_bdd_info: ... + + def __next__(self) -> FunctionOverride.image_bdd_info_t: ... + + @property + def func_overriding_info(self) -> FunctionOverride.it_func_overriding_info: ... + + @property + def bdd_info(self) -> FunctionOverride.it_bdd_info: ... + + @overload + def find_bdd_info(self, arg: int, /) -> FunctionOverride.image_bdd_info_t | None: ... + + @overload + def find_bdd_info(self, arg: FunctionOverrideInfo, /) -> FunctionOverride.image_bdd_info_t | None: ... + +class EnclaveImport: + class TYPE(enum.Enum): + NONE = 0 + + UNIQUE_ID = 1 + + AUTHOR_ID = 2 + + FAMILY_ID = 3 + + IMAGE_ID = 4 + + type: EnclaveImport.TYPE + + min_security_version: int + + @property + def id(self) -> list[int]: ... + + @id.setter + def id(self, arg: Sequence[int], /) -> EnclaveImport: ... + + @property + def family_id(self) -> list[int]: ... + + @family_id.setter + def family_id(self, arg: Sequence[int], /) -> EnclaveImport: ... + + @property + def image_id(self) -> list[int]: ... + + @image_id.setter + def image_id(self, arg: Sequence[int], /) -> EnclaveImport: ... + + import_name_rva: int + + import_name: str + + reserved: int + + def __str__(self) -> str: ... + +class EnclaveConfiguration: + class it_imports: + def __getitem__(self, arg: int, /) -> EnclaveImport: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> EnclaveConfiguration.it_imports: ... + + def __next__(self) -> EnclaveImport: ... + + size: int + + min_required_config_size: int + + policy_flags: int + + @property + def is_debuggable(self) -> bool: ... + + import_list_rva: int + + import_entry_size: int + + @property + def nb_imports(self) -> int: ... + + @property + def imports(self) -> EnclaveConfiguration.it_imports: ... + + @property + def family_id(self) -> list[int]: ... + + @family_id.setter + def family_id(self, arg: Sequence[int], /) -> EnclaveConfiguration: ... + + @property + def image_id(self) -> list[int]: ... + + @image_id.setter + def image_id(self, arg: Sequence[int], /) -> EnclaveConfiguration: ... + + image_version: int + + security_version: int + + enclave_size: int + + nb_threads: int + + enclave_flags: int + + def __str__(self) -> str: ... + +class VolatileMetadata: + class range_t: + start: int + + size: int + + @property + def end(self) -> int: ... + + class it_info_ranges_t: + def __getitem__(self, arg: int, /) -> VolatileMetadata.range_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> VolatileMetadata.it_info_ranges_t: ... + + def __next__(self) -> VolatileMetadata.range_t: ... + + size: int + + min_version: int + + max_version: int + + access_table_rva: int + + @property + def access_table(self) -> list[int]: ... + + @property + def access_table_size(self) -> int: ... + + info_range_rva: int + + @property + def info_ranges_size(self) -> int: ... + + @property + def info_ranges(self) -> VolatileMetadata.it_info_ranges_t: ... + + def __str__(self) -> str: ... + +class LoadConfiguration(lief.Object): + class guard_function_t: + rva: int + + extra: int + + class it_guard_functions: + def __getitem__(self, arg: int, /) -> LoadConfiguration.guard_function_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> LoadConfiguration.it_guard_functions: ... + + def __next__(self) -> LoadConfiguration.guard_function_t: ... + + class it_dynamic_relocations_t: + def __getitem__(self, arg: int, /) -> DynamicRelocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> LoadConfiguration.it_dynamic_relocations_t: ... + + def __next__(self) -> DynamicRelocation: ... + + class IMAGE_GUARD(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> LoadConfiguration.IMAGE_GUARD: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + CF_INSTRUMENTED = 256 + + CFW_INSTRUMENTED = 512 + + CF_FUNCTION_TABLE_PRESENT = 1024 + + SECURITY_COOKIE_UNUSED = 2048 + + PROTECT_DELAYLOAD_IAT = 4096 + + DELAYLOAD_IAT_IN_ITS_OWN_SECTION = 8192 + + CF_EXPORT_SUPPRESSION_INFO_PRESENT = 16384 + + CF_ENABLE_EXPORT_SUPPRESSION = 32768 + + CF_LONGJUMP_TABLE_PRESENT = 65536 + + RF_INSTRUMENTED = 131072 + + RF_ENABLE = 262144 + + RF_STRICT = 524288 + + RETPOLINE_PRESENT = 1048576 + + EH_CONTINUATION_TABLE_PRESENT = 4194304 + + XFG_ENABLED = 8388608 + + CASTGUARD_PRESENT = 16777216 + + MEMCPY_PRESENT = 33554432 + + characteristics: int + + size: int + + timedatestamp: int + + major_version: int + + minor_version: int + + global_flags_clear: int + + global_flags_set: int + + critical_section_default_timeout: int + + decommit_free_block_threshold: int + + decommit_total_free_threshold: int + + lock_prefix_table: int + + maximum_allocation_size: int + + virtual_memory_threshold: int + + process_affinity_mask: int + + process_heap_flags: int + + csd_version: int + + dependent_load_flags: int + + reserved1: int + + editlist: int + + security_cookie: int + + @property + def se_handler_table(self) -> int | None: ... + + @se_handler_table.setter + def se_handler_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def seh_functions(self) -> list[int]: ... + + @property + def se_handler_count(self) -> int | None: ... + + @se_handler_count.setter + def se_handler_count(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_cf_check_function_pointer(self) -> int | None: ... + + @guard_cf_check_function_pointer.setter + def guard_cf_check_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_cf_dispatch_function_pointer(self) -> int | None: ... + + @guard_cf_dispatch_function_pointer.setter + def guard_cf_dispatch_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_cf_function_table(self) -> int | None: ... + + @guard_cf_function_table.setter + def guard_cf_function_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_cf_function_count(self) -> int | None: ... + + @guard_cf_function_count.setter + def guard_cf_function_count(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_cf_functions(self) -> LoadConfiguration.it_guard_functions: ... + + @property + def guard_flags(self) -> int | None: ... + + @guard_flags.setter + def guard_flags(self, arg: int, /) -> LoadConfiguration: ... + + def has(self, arg: LoadConfiguration.IMAGE_GUARD, /) -> bool: ... + + @property + def guard_cf_flags_list(self) -> list[LoadConfiguration.IMAGE_GUARD]: ... + + @property + def code_integrity(self) -> CodeIntegrity | None: ... + + @code_integrity.setter + def code_integrity(self, arg: CodeIntegrity, /) -> LoadConfiguration: ... + + @property + def guard_address_taken_iat_entry_table(self) -> int | None: ... + + @guard_address_taken_iat_entry_table.setter + def guard_address_taken_iat_entry_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_address_taken_iat_entry_count(self) -> int | None: ... + + @guard_address_taken_iat_entry_count.setter + def guard_address_taken_iat_entry_count(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_address_taken_iat_entries(self) -> LoadConfiguration.it_guard_functions: ... + + @property + def guard_long_jump_target_table(self) -> int | None: ... + + @guard_long_jump_target_table.setter + def guard_long_jump_target_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_long_jump_target_count(self) -> int | None: ... + + @guard_long_jump_target_count.setter + def guard_long_jump_target_count(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_long_jump_targets(self) -> LoadConfiguration.it_guard_functions: ... + + @property + def dynamic_value_reloc_table(self) -> int | None: ... + + @dynamic_value_reloc_table.setter + def dynamic_value_reloc_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def hybrid_metadata_pointer(self) -> int | None: ... + + @hybrid_metadata_pointer.setter + def hybrid_metadata_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def chpe_metadata_pointer(self) -> int | None: ... + + @property + def chpe_metadata(self) -> CHPEMetadata | None: ... + + @property + def guard_rf_failure_routine(self) -> int | None: ... + + @guard_rf_failure_routine.setter + def guard_rf_failure_routine(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_rf_failure_routine_function_pointer(self) -> int | None: ... + + @guard_rf_failure_routine_function_pointer.setter + def guard_rf_failure_routine_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def dynamic_value_reloctable_offset(self) -> int | None: ... + + @dynamic_value_reloctable_offset.setter + def dynamic_value_reloctable_offset(self, arg: int, /) -> LoadConfiguration: ... + + @property + def dynamic_value_reloctable_section(self) -> int | None: ... + + @dynamic_value_reloctable_section.setter + def dynamic_value_reloctable_section(self, arg: int, /) -> LoadConfiguration: ... + + @property + def dynamic_relocations(self) -> LoadConfiguration.it_dynamic_relocations_t: ... + + @property + def reserved2(self) -> int | None: ... + + @reserved2.setter + def reserved2(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_rf_verify_stackpointer_function_pointer(self) -> int | None: ... + + @guard_rf_verify_stackpointer_function_pointer.setter + def guard_rf_verify_stackpointer_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def hotpatch_table_offset(self) -> int | None: ... + + @hotpatch_table_offset.setter + def hotpatch_table_offset(self, arg: int, /) -> LoadConfiguration: ... + + @property + def reserved3(self) -> int | None: ... + + @reserved3.setter + def reserved3(self, arg: int, /) -> LoadConfiguration: ... + + @property + def enclave_configuration_ptr(self) -> int | None: ... + + @enclave_configuration_ptr.setter + def enclave_configuration_ptr(self, arg: int, /) -> LoadConfiguration: ... + + @property + def enclave_config(self) -> EnclaveConfiguration | None: ... + + @property + def volatile_metadata_pointer(self) -> int | None: ... + + @volatile_metadata_pointer.setter + def volatile_metadata_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def volatile_metadata(self) -> VolatileMetadata | None: ... + + @property + def guard_eh_continuation_table(self) -> int | None: ... + + @guard_eh_continuation_table.setter + def guard_eh_continuation_table(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_eh_continuation_count(self) -> int | None: ... + + @guard_eh_continuation_count.setter + def guard_eh_continuation_count(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_eh_continuation_functions(self) -> LoadConfiguration.it_guard_functions: ... + + @property + def guard_xfg_check_function_pointer(self) -> int | None: ... + + @guard_xfg_check_function_pointer.setter + def guard_xfg_check_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_xfg_dispatch_function_pointer(self) -> int | None: ... + + @guard_xfg_dispatch_function_pointer.setter + def guard_xfg_dispatch_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_xfg_table_dispatch_function_pointer(self) -> int | None: ... + + @guard_xfg_table_dispatch_function_pointer.setter + def guard_xfg_table_dispatch_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def cast_guard_os_determined_failure_mode(self) -> int | None: ... + + @cast_guard_os_determined_failure_mode.setter + def cast_guard_os_determined_failure_mode(self, arg: int, /) -> LoadConfiguration: ... + + @property + def guard_memcpy_function_pointer(self) -> int | None: ... + + @guard_memcpy_function_pointer.setter + def guard_memcpy_function_pointer(self, arg: int, /) -> LoadConfiguration: ... + + @property + def uma_function_pointers(self) -> int | None: ... + + @uma_function_pointers.setter + def uma_function_pointers(self, arg: int, /) -> LoadConfiguration: ... + + def copy(self) -> LoadConfiguration: ... + + def __str__(self) -> str: ... + +class Binary(lief.Binary): + class it_section: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_section: ... + + def __next__(self) -> Section: ... + + class it_data_directories: + def __getitem__(self, arg: int, /) -> DataDirectory: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_data_directories: ... + + def __next__(self) -> DataDirectory: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> DynamicFixupGeneric.it_relocations: ... + + def __next__(self) -> Relocation: ... + + class it_imports: + def __getitem__(self, arg: int, /) -> Import: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_imports: ... + + def __next__(self) -> Import: ... + + class it_delay_imports: + def __getitem__(self, arg: int, /) -> DelayImport: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_delay_imports: ... + + def __next__(self) -> DelayImport: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> lief.COFF.Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols: ... + + def __next__(self) -> lief.COFF.Symbol: ... + + class it_const_signatures: + def __getitem__(self, arg: int, /) -> Signature: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_const_signatures: ... + + def __next__(self) -> Signature: ... + + class it_debug: + def __getitem__(self, arg: int, /) -> Debug: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_debug: ... + + def __next__(self) -> Debug: ... + + class it_strings_table: + def __getitem__(self, arg: int, /) -> lief.COFF.String: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_strings_table: ... + + def __next__(self) -> lief.COFF.String: ... + + class it_exceptions: + def __getitem__(self, arg: int, /) -> ExceptionInfo: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_exceptions: ... + + def __next__(self) -> ExceptionInfo: ... + + @property + def sections(self) -> Binary.it_section: ... # type: ignore + + @property + def dos_header(self) -> DosHeader: ... + + @property + def header(self) -> Header: ... # type: ignore + + @property + def optional_header(self) -> OptionalHeader: ... + + def compute_checksum(self) -> int: ... + + @property + def virtual_size(self) -> int: ... + + @property + def sizeof_headers(self) -> int: ... + + def rva_to_offset(self, rva_address: int) -> int: ... + + def va_to_offset(self, va_address: int) -> int: ... + + def offset_to_rva(self, offset: int) -> int: ... + + def section_from_offset(self, offset: int) -> Section | None: ... + + def section_from_rva(self, rva: int) -> Section | None: ... + + @property + def tls(self) -> TLS | None: ... + + @tls.setter + def tls(self, arg: TLS, /) -> TLS: ... + + def remove_tls(self) -> None: ... + + @property + def rich_header(self) -> RichHeader | None: ... + + @rich_header.setter + def rich_header(self, arg: RichHeader, /) -> None: ... + + @property + def has_rich_header(self) -> bool: ... + + @property + def has_debug(self) -> bool: ... + + @property + def has_tls(self) -> bool: ... + + @property + def has_imports(self) -> bool: ... + + @property + def has_exports(self) -> bool: ... + + @property + def has_resources(self) -> bool: ... + + @property + def has_exceptions(self) -> bool: ... + + @property + def has_relocations(self) -> bool: ... + + @property + def has_configuration(self) -> bool: ... + + @property + def has_signatures(self) -> bool: ... + + @property + def is_reproducible_build(self) -> bool: ... + + @property + def functions(self) -> list[lief.Function]: ... + + @property + def exception_functions(self) -> list[lief.Function]: ... + + @property + def signatures(self) -> Binary.it_const_signatures: ... + + def authentihash(self, algorithm: ALGORITHMS) -> bytes: ... + + @overload + def verify_signature(self, checks: Signature.VERIFICATION_CHECKS = Signature.VERIFICATION_CHECKS.DEFAULT) -> Signature.VERIFICATION_FLAGS: ... + + @overload + def verify_signature(self, signature: Signature, checks: Signature.VERIFICATION_CHECKS = Signature.VERIFICATION_CHECKS.DEFAULT) -> Signature.VERIFICATION_FLAGS: ... + + @property + def authentihash_md5(self) -> bytes: ... + + @property + def authentihash_sha1(self) -> bytes: ... + + @property + def authentihash_sha256(self) -> bytes: ... + + @property + def authentihash_sha512(self) -> bytes: ... + + @property + def debug(self) -> Binary.it_debug: ... + + def add_debug_info(self, entry: Debug) -> Debug | None: ... + + def remove_debug(self, entry: Debug) -> bool: ... + + def clear_debug(self) -> bool: ... + + @property + def codeview_pdb(self) -> CodeViewPDB | None: ... + + @property + def load_configuration(self) -> LoadConfiguration | None: ... + + def get_export(self) -> Export | None: ... + + def set_export(self, arg: Export, /) -> Export: ... + + @property + def symbols(self) -> Binary.it_symbols: ... # type: ignore + + def get_section(self, section_name: str) -> Section | None: ... + + def add_section(self, section: Section) -> Section | None: ... + + @property + def relocations(self) -> DynamicFixupGeneric.it_relocations: ... # type: ignore + + def add_relocation(self, relocation: Relocation) -> Relocation: ... + + def remove_all_relocations(self) -> None: ... + + def remove(self, section: Section, clear: bool = False) -> None: ... + + @property + def data_directories(self) -> Binary.it_data_directories: ... + + def data_directory(self, type: DataDirectory.TYPES) -> DataDirectory | None: ... + + @property + def imports(self) -> Binary.it_imports: ... + + def has_import(self, import_name: str) -> bool: ... + + def get_import(self, import_name: str) -> Import | None: ... + + @property + def delay_imports(self) -> Binary.it_delay_imports: ... + + @property + def has_delay_imports(self) -> bool: ... + + def has_delay_import(self, import_name: str) -> bool: ... + + def get_delay_import(self, import_name: str) -> DelayImport | None: ... + + @property + def resources_manager(self) -> Union[ResourcesManager, lief.lief_errors]: ... + + @property + def resources(self) -> ResourceNode | None: ... + + @property + def overlay(self) -> memoryview: ... + + @property + def overlay_offset(self) -> int: ... + + @property + def dos_stub(self) -> memoryview: ... + + @dos_stub.setter + def dos_stub(self, arg: Sequence[int], /) -> None: ... + + def add_import(self, import_name: str, pos: int = -1) -> Import: ... + + def remove_import(self, name: str) -> bool: ... + + def remove_all_imports(self) -> None: ... + + def set_resources(self, new_tree: ResourceNode) -> ResourceNode | None: ... + + @property + def exceptions(self) -> Binary.it_exceptions: ... + + @property + def export_dir(self) -> DataDirectory | None: ... + + @property + def import_dir(self) -> DataDirectory | None: ... + + @property + def rsrc_dir(self) -> DataDirectory | None: ... + + @property + def exceptions_dir(self) -> DataDirectory | None: ... + + @property + def cert_dir(self) -> DataDirectory | None: ... + + @property + def relocation_dir(self) -> DataDirectory | None: ... + + @property + def debug_dir(self) -> DataDirectory | None: ... + + @property + def tls_dir(self) -> DataDirectory | None: ... + + @property + def load_config_dir(self) -> DataDirectory | None: ... + + @property + def iat_dir(self) -> DataDirectory | None: ... + + @property + def delay_dir(self) -> DataDirectory | None: ... + + @property + def is_arm64ec(self) -> bool: ... + + @property + def is_arm64x(self) -> bool: ... + + @overload + def write(self, output_path: Union[str | os.PathLike]) -> None: ... + + @overload + def write(self, output_path: Union[str | os.PathLike], config: Builder.config_t) -> None: ... + + @overload + def write_to_bytes(self, config: Builder.config_t) -> bytes: ... + + @overload + def write_to_bytes(self) -> bytes: ... + + def fill_address(self, address: int, size: int, value: int = 0, addr_type: lief.Binary.VA_TYPES = lief.Binary.VA_TYPES.AUTO) -> None: ... + + @property + def coff_string_table(self) -> Binary.it_strings_table: ... + + def find_coff_string(self, offset: int) -> lief.COFF.String | None: ... + + def find_exception_at(self, rva: int) -> ExceptionInfo | None: ... + + @property + def nested_pe_binary(self) -> Binary | None: ... + + def __str__(self) -> str: ... + +class Builder: + def __init__(self, binary: Binary, config: Builder.config_t) -> None: ... + + class config_t: + def __init__(self) -> None: ... + + imports: bool + + exports: bool + + resources: bool + + relocations: bool + + load_configuration: bool + + tls: bool + + overlay: bool + + debug: bool + + dos_stub: bool + + rsrc_section: str + + idata_section: str + + tls_section: str + + reloc_section: str + + export_section: str + + debug_section: str + + resolved_iat_cbk: Callable[[Binary, Import, ImportEntry, int], None] + + force_relocating: bool + + @property + def rsrc_data(self) -> memoryview: ... + + def build(self) -> Union[lief.ok_t, lief.lief_errors]: ... + + def write(self, output: str) -> None: ... + + def raw_bytes(self) -> bytes: ... + +class Factory: + @staticmethod + def create(arg: PE_TYPE, /) -> Optional[Factory]: ... + + def add_section(self, arg: Section, /) -> Factory: ... + + def get(self) -> Optional[Binary]: ... + +class IMPHASH_MODE(enum.Enum): + DEFAULT = 0 + + LIEF = 0 + + PEFILE = 1 + + VT = 1 + +def oid_to_string(arg: str, /) -> str: ... + +@overload +def get_type(file: Union[str | os.PathLike]) -> Union[PE_TYPE, lief.lief_errors]: ... + +@overload +def get_type(raw: Sequence[int]) -> Union[PE_TYPE, lief.lief_errors]: ... + +def get_imphash(binary: Binary, mode: IMPHASH_MODE = IMPHASH_MODE.DEFAULT) -> str: ... + +def resolve_ordinals(imp: Import, strict: bool = False, use_std: bool = False) -> Union[Import, lief.lief_errors]: ... + +def check_layout(binary: Binary) -> tuple[bool, str]: ... diff --git a/vendor/lief/api/python/lief/PE/unwind_aarch64.pyi b/vendor/lief/api/python/lief/PE/unwind_aarch64.pyi new file mode 100644 index 0000000..633e6f0 --- /dev/null +++ b/vendor/lief/api/python/lief/PE/unwind_aarch64.pyi @@ -0,0 +1,62 @@ +from collections.abc import Sequence + +import lief.PE + + +class UnpackedFunction(lief.PE.RuntimeFunctionAArch64): + class epilog_scope_t: + start_offset: int + + start_index: int + + reserved: int + + class it_epilog_scopes: + def __getitem__(self, arg: int, /) -> UnpackedFunction.epilog_scope_t: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> UnpackedFunction.it_epilog_scopes: ... + + def __next__(self) -> UnpackedFunction.epilog_scope_t: ... + + xdata_rva: int + + version: int + + X: int + + E: int + + @property + def epilog_count(self) -> int: ... + + @property + def epilog_offset(self) -> int: ... + + code_words: int + + exception_handler: int + + @property + def unwind_code(self) -> memoryview: ... + + @unwind_code.setter + def unwind_code(self, arg: Sequence[int], /) -> UnpackedFunction: ... + + @property + def epilog_scopes(self) -> UnpackedFunction.it_epilog_scopes: ... + + @property + def is_extended(self) -> bool: ... + +class PackedFunction(lief.PE.RuntimeFunctionAArch64): + frame_size: int + + reg_I: int + + reg_F: int + + H: int + + CR: int diff --git a/vendor/lief/api/python/lief/PE/unwind_x64.pyi b/vendor/lief/api/python/lief/PE/unwind_x64.pyi new file mode 100644 index 0000000..b5ecf30 --- /dev/null +++ b/vendor/lief/api/python/lief/PE/unwind_x64.pyi @@ -0,0 +1,51 @@ +import lief.PE + + +class Code: + @property + def opcode(self) -> lief.PE.RuntimeFunctionX64.UNWIND_OPCODES: ... + + @property + def position(self) -> int: ... + + def __str__(self) -> str: ... + +class Alloc(Code): + @property + def size(self) -> int: ... + +class PushNonVol(Code): + @property + def reg(self) -> lief.PE.RuntimeFunctionX64.UNWIND_REG: ... + +class PushMachFrame(Code): + @property + def value(self) -> int: ... + +class SetFPReg(Code): + @property + def reg(self) -> lief.PE.RuntimeFunctionX64.UNWIND_REG: ... + +class SaveNonVolatile(Code): + @property + def reg(self) -> lief.PE.RuntimeFunctionX64.UNWIND_REG: ... + + @property + def offset(self) -> int: ... + +class SaveXMM128(Code): + @property + def num(self) -> int: ... + + @property + def offset(self) -> int: ... + +class Epilog(Code): + @property + def flags(self) -> int: ... + + @property + def size(self) -> int: ... + +class Spare(Code): + pass diff --git a/vendor/lief/api/python/lief/VDEX.pyi b/vendor/lief/api/python/lief/VDEX.pyi new file mode 100644 index 0000000..cae22e8 --- /dev/null +++ b/vendor/lief/api/python/lief/VDEX.pyi @@ -0,0 +1,56 @@ +from collections.abc import Sequence +import io +import os +from typing import Optional, Union, overload + +import lief +import lief.Android +import lief.OAT + + +@overload +def parse(filename: str) -> Optional[File]: ... + +@overload +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], name: str = '') -> Optional[File]: ... + +class File(lief.Object): + @property + def header(self) -> Header: ... + + @property + def dex_files(self) -> lief.OAT.Binary.it_dex_files: ... + + @property + def dex2dex_json_info(self) -> str: ... + + def __str__(self) -> str: ... + +class Header(lief.Object): + @property + def magic(self) -> list[int]: ... + + @property + def version(self) -> int: ... + + @property + def nb_dex_files(self) -> int: ... + + @property + def dex_size(self) -> int: ... + + @property + def verifier_deps_size(self) -> int: ... + + @property + def quickening_info_size(self) -> int: ... + + def __str__(self) -> str: ... + +@overload +def version(file: str) -> int: ... + +@overload +def version(raw: Sequence[int]) -> int: ... + +def android_version(vdex_version: int) -> lief.Android.ANDROID_VERSIONS: ... diff --git a/vendor/lief/api/python/lief/__init__.py b/vendor/lief/api/python/lief/__init__.py new file mode 100644 index 0000000..093c4dc --- /dev/null +++ b/vendor/lief/api/python/lief/__init__.py @@ -0,0 +1,28 @@ +import os +import sys +import traceback + +if len(__path__) > 0 and __path__[0] not in sys.path: + from . import _lief # type: ignore + from ._lief import * # type: ignore + from ._lief import ( # type: ignore + __commit__, + __extended__, + __free_threaded__, + __is_tagged__, + __tag__, + __version__, + ) + + if __extended__: + from ._lief_extended import ( # type: ignore + __LIEF_EXTENDED_VERSION_STR__, + __LIEF_MAIN_COMMIT__, + __extended_version__, + ) + + # cf. https://github.com/pytorch/pytorch/blob/60a3b7425dde97fe8b46183c154a9c3b24f0c733/torch/__init__.py#L467-L470 + for attr in dir(_lief): + candidate = getattr(_lief, attr) + if type(candidate) is type(_lief): + sys.modules.setdefault(f"lief.{attr}", candidate) diff --git a/vendor/lief/api/python/lief/__init__.pyi b/vendor/lief/api/python/lief/__init__.pyi new file mode 100644 index 0000000..8ef23d8 --- /dev/null +++ b/vendor/lief/api/python/lief/__init__.pyi @@ -0,0 +1,908 @@ +from collections.abc import Iterator, Mapping, Sequence +import enum +import io +import os +from typing import Any, Optional, Union, overload + +import lief +import lief.PE + +from lief import ( + ART as ART, + Android as Android, + COFF as COFF, + DEX as DEX, + ELF as ELF, + MachO as MachO, + OAT as OAT, + PE as PE, + VDEX as VDEX, + assembly as assembly, + dsc as dsc, + dwarf as dwarf, + logging as logging, + objc as objc, + pdb as pdb, + runtime as runtime +) + + +__tag__: str = ... + +__commit__: str = ... + +__is_tagged__: bool = ... + +__free_threaded__: bool = ... + +class lief_version_t: + major: int + + minor: int + + patch: int + + id: int + + def __repr__(self) -> str: ... + + def __str__(self) -> str: ... + +def disable_leak_warning() -> None: ... + +def demangle(mangled: str) -> Optional[str]: ... + +@overload +def dump(buffer: memoryview, title: str = '', prefix: str = '', limit: int = 0) -> str: ... + +@overload +def dump(buffer: bytes, title: str = '', prefix: str = '', limit: int = 0) -> str: ... + +def extended_version_info() -> str: ... + +def extended_version() -> lief_version_t: ... + +def to_int(ptr: Any) -> int: ... + +def to_ptr(ptr: int) -> Any: ... + +__extended__: bool = ... + +class range_t: + low: int + + high: int + + @property + def size(self) -> int: ... + + def __repr__(self) -> str: ... + + def __str__(self) -> str: ... + +class debug_location_t: + line: int + + file: str + + def __repr__(self) -> str: ... + +class PLATFORMS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> PLATFORMS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 3 + + LINUX = 1 + + ANDROID = 2 + + WINDOWS = 3 + + IOS = 4 + + OSX = 5 + +def current_platform() -> PLATFORMS: ... + +class Object: + def __hash__(self) -> int: ... + + def __eq__(self, arg, /) -> bool: ... + +class ok_t: + def __bool__(self) -> bool: ... + +class ok_error_t: + @property + def is_error(self) -> bool: ... + + @property + def is_value(self) -> bool: ... + + @property + def error(self) -> lief_errors: ... + + @property + def value(self) -> ok_t: ... + + def __bool__(self) -> bool: ... + +class lief_errors(enum.Enum): + read_error = 1 + + not_found = 2 + + not_implemented = 3 + + not_supported = 4 + + corrupted = 5 + + conversion_error = 6 + + read_out_of_bound = 7 + + asn1_bad_tag = 8 + + file_error = 9 + + file_format_error = 10 + + parsing_error = 11 + + build_error = 12 + + data_too_large = 13 + + require_extended_version = 14 + + inconsistent = 15 + + runtime_error = 16 + +@overload +def hash(arg: Object, /) -> int: ... # type: ignore + +@overload +def hash(arg: Sequence[int], /) -> int: ... # type: ignore + +@overload +def hash(arg: bytes, /) -> int: ... # type: ignore + +@overload +def hash(arg: str, /) -> int: ... # type: ignore + +def to_json(arg: Object, /) -> str: ... + +class BinaryStream: + @property + def size(self) -> int: ... + + def __bool__(self) -> bool: ... + + def __len__(self) -> int: ... + + @property + def is_memory_stream(self) -> bool: ... + + @property + def pos(self) -> int: ... + + def increment_pos(self, value: int) -> BinaryStream: ... + + def decrement_pos(self, value: int) -> None: ... + + def setpos(self, value: int) -> None: ... + + def read_uleb128(self) -> tuple[Union[int,lief.lief_errors], int]: ... + + def read_sleb128(self) -> tuple[Union[int,lief.lief_errors], int]: ... + + def read_dwarf_encoded(self, encoding: int) -> Union[int,lief.lief_errors]: ... + + def read_string(self, maxsize: int = 18446744073709551615) -> Union[str,lief.lief_errors]: ... + + def peek_string(self, maxsize: int = 18446744073709551615) -> Union[str,lief.lief_errors]: ... + + def peek_string_at(self, offset: int, maxsize: int = 18446744073709551615) -> Union[str,lief.lief_errors]: ... + + @overload + def read_u16string(self) -> Union[str,lief.lief_errors]: ... + + @overload + def read_u16string(self, length: int) -> Union[str,lief.lief_errors]: ... + + @overload + def peek_u16string(self) -> Union[str,lief.lief_errors]: ... + + @overload + def peek_u16string(self, length: int) -> Union[str,lief.lief_errors]: ... + + @overload + def peek_u16string(self, offset: int, length: int) -> Union[str,lief.lief_errors]: ... + + def read_mutf8(self, maxsize: int = 18446744073709551615) -> Union[str,lief.lief_errors]: ... + + def peek_data(self, offset: int, size: int, virtual_address: int = 0) -> bytes | None: ... + + @overload + def read_data(self, size: int) -> bytes | None: ... + + @overload + def read_data(self) -> bytes | None: ... + + def align(self, align_on: int) -> int: ... + + def set_endian_swap(self, swap: bool) -> None: ... + + def read_u8(self) -> Union[int,lief.lief_errors]: ... + + def read_i8(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u8(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u8(self, offset: int) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i8(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i8(self, offset: int) -> Union[int,lief.lief_errors]: ... + + def read_u16(self) -> Union[int,lief.lief_errors]: ... + + def read_i16(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u16(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u16(self, offset: int) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i16(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i16(self, offset: int) -> Union[int,lief.lief_errors]: ... + + def read_u32(self) -> Union[int,lief.lief_errors]: ... + + def read_i32(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u32(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u32(self, offset: int) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i32(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i32(self, offset: int) -> Union[int,lief.lief_errors]: ... + + def read_u64(self) -> Union[int,lief.lief_errors]: ... + + def read_i64(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u64(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_u64(self, offset: int) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i64(self) -> Union[int,lief.lief_errors]: ... + + @overload + def peek_i64(self, offset: int) -> Union[int,lief.lief_errors]: ... + + @property + def start(self) -> int: ... + + @property + def start_addr(self) -> int: ... + + @property + def end(self) -> int: ... + + @property + def end_addr(self) -> int: ... + + @property + def p(self) -> int: ... + + @property + def p_addr(self) -> int: ... + +class SpanStream(BinaryStream): + @overload + def slice(self, offset: int, size: int) -> Union[SpanStream,lief.lief_errors]: ... + + @overload + def slice(self, offset: int) -> Union[SpanStream,lief.lief_errors]: ... + + def to_vector(self) -> Optional[VectorStream]: ... + + @property + def content(self) -> bytes: ... + + @property + def __bytes__(self) -> bytes: ... + +class VectorStream(BinaryStream): + @staticmethod + def from_file(path: Union[str, os.PathLike]) -> Union[VectorStream,lief.lief_errors]: ... + + @staticmethod + def from_bytes(buffer: bytes) -> Optional[VectorStream]: ... + + @property + def content(self) -> memoryview: ... + + @overload + def slice(self, arg0: int, arg1: int, /) -> Optional[SpanStream]: ... + + @overload + def slice(self, arg: int, /) -> Optional[SpanStream]: ... + +class FileStream(BinaryStream): + @staticmethod + def from_file(arg: Union[str, os.PathLike], /) -> Union[FileStream,lief.lief_errors]: ... + + @property + def content(self) -> bytes: ... + +class WriteStream: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, endian_swap: bool) -> None: ... + + def reserve(self, size: int) -> WriteStream: ... + + def increase_capacity(self, size: int) -> WriteStream: ... + + def align(self, alignment: int, fill: int = 0) -> WriteStream: ... + + @property + def size(self) -> int: ... + + def __len__(self) -> int: ... + + @property + def tellp(self) -> int: ... + + def seekp(self, pos: int) -> WriteStream: ... + + def seek_end(self) -> WriteStream: ... + + def pad(self, size: int, value: int = 0) -> WriteStream: ... + + def set_endian_swap(self, swap: bool) -> None: ... + + @property + def endian_swap(self) -> bool: ... + + @property + def raw(self) -> memoryview: ... + + def __bytes__(self) -> bytes: ... + + def write_u8(self, arg: int, /) -> WriteStream: ... + + def write_i8(self, arg: int, /) -> WriteStream: ... + + def write_u16(self, arg: int, /) -> WriteStream: ... + + def write_i16(self, arg: int, /) -> WriteStream: ... + + def write_u32(self, arg: int, /) -> WriteStream: ... + + def write_i32(self, arg: int, /) -> WriteStream: ... + + def write_u64(self, arg: int, /) -> WriteStream: ... + + def write_i64(self, arg: int, /) -> WriteStream: ... + + def write_uleb128(self, value: int) -> WriteStream: ... + + def write_sleb128(self, value: int) -> WriteStream: ... + + @overload + def write(self, s: str) -> WriteStream: ... + + @overload + def write(self, buffer: bytes) -> WriteStream: ... + + @overload + def write(self, buffer: Sequence[int]) -> WriteStream: ... + + @overload + def write(self, other: WriteStream) -> WriteStream: ... + + def put(self, c: int) -> WriteStream: ... + +class Header(Object): + class ARCHITECTURES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.ARCHITECTURES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + ARM = 1 + + ARM64 = 2 + + MIPS = 3 + + X86 = 4 + + X86_64 = 5 + + PPC = 6 + + SPARC = 7 + + SYSZ = 8 + + XCORE = 9 + + RISCV = 10 + + LOONGARCH = 11 + + PPC64 = 12 + + class ENDIANNESS(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.ENDIANNESS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + BIG = 1 + + LITTLE = 2 + + class MODES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.MODES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + BITS_16 = 1 + + BITS_32 = 2 + + BITS_64 = 4 + + THUMB = 8 + + ARM64E = 16 + + class OBJECT_TYPES(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> Header.OBJECT_TYPES: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + EXECUTABLE = 1 + + LIBRARY = 2 + + OBJECT = 3 + + @property + def architecture(self) -> Header.ARCHITECTURES: ... + + @property + def modes(self) -> Header.MODES: ... + + @property + def modes_list(self) -> list[Header.MODES]: ... + + @property + def entrypoint(self) -> int: ... + + @property + def object_type(self) -> Header.OBJECT_TYPES: ... + + @property + def endianness(self) -> Header.ENDIANNESS: ... + + @property + def is_32(self) -> bool: ... + + @property + def is_64(self) -> bool: ... + + def __str__(self) -> str: ... + +class Binary(Object): + class VA_TYPES(enum.Enum): + AUTO = 0 + + RVA = 1 + + VA = 2 + + class FORMATS(enum.Enum): + UNKNOWN = 0 + + ELF = 1 + + PE = 2 + + MACHO = 3 + + OAT = 4 + + class it_sections: + def __getitem__(self, arg: int, /) -> Section: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_sections: ... + + def __next__(self) -> Section: ... + + class it_symbols: + def __getitem__(self, arg: int, /) -> Symbol: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_symbols: ... + + def __next__(self) -> Symbol: ... + + class it_relocations: + def __getitem__(self, arg: int, /) -> Relocation: ... + + def __len__(self) -> int: ... + + def __iter__(self) -> Binary.it_relocations: ... + + def __next__(self) -> Relocation: ... + + @property + def debug_info(self) -> DebugInfo | None: ... + + @property + def format(self) -> Binary.FORMATS: ... + + @property + def is_pie(self) -> bool: ... + + @property + def has_nx(self) -> bool: ... + + @property + def header(self) -> Header: ... + + @property + def entrypoint(self) -> int: ... + + def remove_section(self, name: str, clear: bool = False) -> None: ... + + @property + def sections(self) -> Binary.it_sections: ... + + @property + def relocations(self) -> Binary.it_relocations: ... + + @property + def exported_functions(self) -> list[Function]: ... + + @property + def imported_functions(self) -> list[Function]: ... + + @property + def libraries(self) -> list[Union[str,bytes]]: ... + + @property + def symbols(self) -> Binary.it_symbols: ... + + def has_symbol(self, symbol_name: str) -> bool: ... + + def get_symbol(self, symbol_name: str) -> Symbol | None: ... + + def get_function_address(self, function_name: str) -> Union[int, lief_errors]: ... + + @overload + def patch_address(self, address: int, patch_value: Sequence[int], va_type: Binary.VA_TYPES = Binary.VA_TYPES.AUTO) -> None: ... + + @overload + def patch_address(self, address: int, patch_value: int, size: int = 8, va_type: Binary.VA_TYPES = Binary.VA_TYPES.AUTO) -> None: ... + + def get_content_from_virtual_address(self, virtual_address: int, size: int, va_type: Binary.VA_TYPES = Binary.VA_TYPES.AUTO) -> memoryview: ... + + def get_int_from_virtual_address(self, address: int, interger_size: int, type: Binary.VA_TYPES = Binary.VA_TYPES.AUTO) -> Optional[int]: ... + + @property + def abstract(self) -> lief.Binary: ... + + @property + def concrete(self) -> lief.ELF.Binary | lief.PE.Binary | lief.MachO.Binary: ... + + @property + def ctor_functions(self) -> list[Function]: ... + + def xref(self, virtual_address: int) -> list[int]: ... + + def offset_to_virtual_address(self, offset: int, slide: int = 0) -> Union[int, lief_errors]: ... + + @property + def imagebase(self) -> int: ... + + @property + def original_size(self) -> int: ... + + @overload + def disassemble(self, address: int) -> Iterator[Optional[assembly.Instruction]]: ... + + @overload + def disassemble(self, address: int, size: int) -> Iterator[Optional[assembly.Instruction]]: ... + + @overload + def disassemble(self, function_name: str) -> Iterator[Optional[assembly.Instruction]]: ... + + def disassemble_from_bytes(self, buffer: bytes, address: int = 0) -> Iterator[Optional[assembly.Instruction]]: ... + + def assemble(self, address: int, assembly: str, config: assembly.AssemblerConfig = ...) -> bytes: ... + + @property + def page_size(self) -> int: ... + + def load_debug_info(self, path: Union[str | os.PathLike]) -> DebugInfo | None: ... + + @property + def virtual_size(self) -> int: ... + + def __str__(self) -> str: ... + +class Section(Object): + @property + def name(self) -> Union[str, bytes]: ... + + @name.setter + def name(self, arg: str, /) -> None: ... + + @property + def fullname(self) -> bytes: ... + + size: int + + offset: int + + virtual_address: int + + @property + def content(self) -> memoryview: ... + + @content.setter + def content(self, arg: Sequence[int], /) -> None: ... + + @property + def entropy(self) -> float: ... + + @overload + def search(self, number: int, pos: int = 0, size: int = 0) -> Optional[int]: ... + + @overload + def search(self, str: str, pos: int = 0) -> Optional[int]: ... + + @overload + def search(self, bytes: bytes, pos: int = 0) -> Optional[int]: ... + + @overload + def search_all(self, number: int, size: int = 0) -> list[int]: ... + + @overload + def search_all(self, str: str) -> list[int]: ... + + def __str__(self) -> str: ... + +class Symbol(Object): + @property + def name(self) -> Union[str, bytes]: ... # type: ignore + + @name.setter + def name(self, arg: str, /) -> None: ... # type: ignore + + value: int + + size: int + + def __str__(self) -> str: ... + +def parse(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]]) -> PE.Binary | OAT.Binary | ELF.Binary | MachO.Binary | COFF.Binary | None: ... + +def parse_from_dump(obj: Union[str | io.IOBase | os.PathLike | bytes | list[int]], addr: int) -> PE.Binary | OAT.Binary | ELF.Binary | MachO.Binary | COFF.Binary | None: ... + +class Relocation(Object): + address: int + + size: int + + def __str__(self) -> str: ... + +class Function(Symbol): + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, arg: str, /) -> None: ... + + @overload + def __init__(self, arg: int, /) -> None: ... + + @overload + def __init__(self, arg0: str, arg1: int, /) -> None: ... + + class FLAGS(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Function.FLAGS: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + IMPORTED = 16 + + EXPORTED = 8 + + CONSTRUCTOR = 1 + + DESTRUCTOR = 2 + + DEBUG_INFO = 4 + + def add(self, flag: Function.FLAGS) -> Function: ... + + def has(self, flag: Function.FLAGS) -> bool: ... + + @property + def flags(self) -> Function.FLAGS: ... + + @property + def flags_list(self) -> list[Function.FLAGS]: ... + + address: int + + def __str__(self) -> str: ... + +class DebugInfo: + class FORMAT(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> DebugInfo.FORMAT: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + DWARF = 1 + + PDB = 2 + + @property + def format(self) -> DebugInfo.FORMAT: ... + + def find_function_address(self, name: str) -> int | None: ... + +class DeclOpt: + def __init__(self) -> None: ... + + indentation: int + + is_cpp: bool + + show_extended_annotations: bool + + include_types: bool + + include_locals: bool + + desugar: bool + + show_field_offsets: bool + + @property + def type_aliases(self) -> dict[str, str]: ... + + @type_aliases.setter + def type_aliases(self, arg: Mapping[str, str], /) -> DeclOpt: ... + + def add_type_alias(self, name: str, alias: str) -> DeclOpt: ... + +def is_pdb(file: Union[str | os.PathLike]) -> bool: ... + +def is_shared_cache(file: Union[str | os.PathLike]) -> bool: ... + +@overload +def is_elf(filename: Union[str | os.PathLike]) -> bool: ... + +@overload +def is_elf(raw: Sequence[int]) -> bool: ... + +@overload +def is_pe(file: Union[str | os.PathLike]) -> bool: ... + +@overload +def is_pe(raw: Sequence[int]) -> bool: ... + +@overload +def is_macho(filename: Union[str | os.PathLike]) -> bool: ... + +@overload +def is_macho(raw: Sequence[int]) -> bool: ... + +@overload +def is_oat(binary: ELF.Binary) -> bool: ... + +@overload +def is_oat(path: str) -> bool: ... + +@overload +def is_oat(raw: Sequence[int]) -> bool: ... + +@overload +def is_dex(path: str) -> bool: ... + +@overload +def is_dex(raw: Sequence[int]) -> bool: ... + +@overload +def is_vdex(path: str) -> bool: ... + +@overload +def is_vdex(raw: Sequence[int]) -> bool: ... + +@overload +def is_art(path: str) -> bool: ... + +@overload +def is_art(raw: Sequence[int]) -> bool: ... + +def is_coff(file: Union[str | os.PathLike]) -> bool: ... diff --git a/vendor/lief/api/python/lief/assembly/__init__.pyi b/vendor/lief/api/python/lief/assembly/__init__.pyi new file mode 100644 index 0000000..c1d0a90 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/__init__.pyi @@ -0,0 +1,123 @@ +import enum +from typing import Union + +import lief +from lief.assembly import ( + aarch64 as aarch64, + arm as arm, + ebpf as ebpf, + mips as mips, + powerpc as powerpc, + riscv as riscv, + x86 as x86 +) + + +class Engine: + pass + +class Instruction: + __match_args__: tuple = ... + + class MemoryAccess(enum.Flag): + @staticmethod + def from_value(arg: int, /) -> Instruction.MemoryAccess: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + NONE = 0 + + READ = 1 + + WRITE = 2 + + @property + def address(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def mnemonic(self) -> str: ... + + def to_string(self, with_address: bool = True) -> str: ... + + @property + def raw(self) -> bytes: ... + + @property + def is_call(self) -> bool: ... + + @property + def is_terminator(self) -> bool: ... + + @property + def is_branch(self) -> bool: ... + + @property + def is_syscall(self) -> bool: ... + + @property + def is_memory_access(self) -> bool: ... + + @property + def is_move_reg(self) -> bool: ... + + @property + def is_add(self) -> bool: ... + + @property + def is_trap(self) -> bool: ... + + @property + def is_barrier(self) -> bool: ... + + @property + def is_return(self) -> bool: ... + + @property + def is_indirect_branch(self) -> bool: ... + + @property + def is_conditional_branch(self) -> bool: ... + + @property + def is_unconditional_branch(self) -> bool: ... + + @property + def is_compare(self) -> bool: ... + + @property + def is_move_immediate(self) -> bool: ... + + @property + def is_bitcast(self) -> bool: ... + + @property + def memory_access(self) -> Instruction.MemoryAccess: ... + + @property + def branch_target(self) -> Union[int, lief.lief_errors]: ... + + def __str__(self) -> str: ... + +class AssemblerConfig: + def __init__(self) -> None: ... + + class DIALECT(enum.Enum): + DEFAULT_DIALECT = 0 + + X86_INTEL = 1 + + X86_ATT = 2 + + @staticmethod + def default_config() -> AssemblerConfig: ... + + dialect: AssemblerConfig.DIALECT + + def resolve_symbol(self, name: str) -> int | None: ... diff --git a/vendor/lief/api/python/lief/assembly/aarch64/__init__.pyi b/vendor/lief/api/python/lief/assembly/aarch64/__init__.pyi new file mode 100644 index 0000000..838fcea --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/aarch64/__init__.pyi @@ -0,0 +1,23349 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.aarch64 import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ABS_ZPmZ_B_UNDEF = 322 + + ABS_ZPmZ_D_UNDEF = 323 + + ABS_ZPmZ_H_UNDEF = 324 + + ABS_ZPmZ_S_UNDEF = 325 + + ADDHA_MPPZ_D_PSEUDO_D = 326 + + ADDHA_MPPZ_S_PSEUDO_S = 327 + + ADDSWrr = 328 + + ADDSXrr = 329 + + ADDVA_MPPZ_D_PSEUDO_D = 330 + + ADDVA_MPPZ_S_PSEUDO_S = 331 + + ADDWrr = 332 + + ADDXrr = 333 + + ADD_VG2_M2Z2Z_D_PSEUDO = 334 + + ADD_VG2_M2Z2Z_S_PSEUDO = 335 + + ADD_VG2_M2ZZ_D_PSEUDO = 336 + + ADD_VG2_M2ZZ_S_PSEUDO = 337 + + ADD_VG2_M2Z_D_PSEUDO = 338 + + ADD_VG2_M2Z_S_PSEUDO = 339 + + ADD_VG4_M4Z4Z_D_PSEUDO = 340 + + ADD_VG4_M4Z4Z_S_PSEUDO = 341 + + ADD_VG4_M4ZZ_D_PSEUDO = 342 + + ADD_VG4_M4ZZ_S_PSEUDO = 343 + + ADD_VG4_M4Z_D_PSEUDO = 344 + + ADD_VG4_M4Z_S_PSEUDO = 345 + + ADD_ZPZZ_B_ZERO = 346 + + ADD_ZPZZ_D_ZERO = 347 + + ADD_ZPZZ_H_ZERO = 348 + + ADD_ZPZZ_S_ZERO = 349 + + ADDlowTLS = 350 + + ADJCALLSTACKDOWN = 351 + + ADJCALLSTACKUP = 352 + + AESIMCrrTied = 353 + + AESMCrrTied = 354 + + ANDSWrr = 355 + + ANDSXrr = 356 + + ANDWrr = 357 + + ANDXrr = 358 + + AND_ZPZZ_B_ZERO = 359 + + AND_ZPZZ_D_ZERO = 360 + + AND_ZPZZ_H_ZERO = 361 + + AND_ZPZZ_S_ZERO = 362 + + ASRD_ZPZI_B_ZERO = 363 + + ASRD_ZPZI_D_ZERO = 364 + + ASRD_ZPZI_H_ZERO = 365 + + ASRD_ZPZI_S_ZERO = 366 + + ASR_ZPZI_B_UNDEF = 367 + + ASR_ZPZI_B_ZERO = 368 + + ASR_ZPZI_D_UNDEF = 369 + + ASR_ZPZI_D_ZERO = 370 + + ASR_ZPZI_H_UNDEF = 371 + + ASR_ZPZI_H_ZERO = 372 + + ASR_ZPZI_S_UNDEF = 373 + + ASR_ZPZI_S_ZERO = 374 + + ASR_ZPZZ_B_UNDEF = 375 + + ASR_ZPZZ_B_ZERO = 376 + + ASR_ZPZZ_D_UNDEF = 377 + + ASR_ZPZZ_D_ZERO = 378 + + ASR_ZPZZ_H_UNDEF = 379 + + ASR_ZPZZ_H_ZERO = 380 + + ASR_ZPZZ_S_UNDEF = 381 + + ASR_ZPZZ_S_ZERO = 382 + + AUTH_TCRETURN = 383 + + AUTH_TCRETURN_BTI = 384 + + AUTPAC = 385 + + AUTx16x17 = 386 + + AUTxMxN = 387 + + AllocateSMESaveBuffer = 388 + + AllocateZABuffer = 389 + + BFADD_VG2_M2Z_H_PSEUDO = 390 + + BFADD_VG4_M4Z_H_PSEUDO = 391 + + BFADD_ZPZZ_UNDEF = 392 + + BFADD_ZPZZ_ZERO = 393 + + BFDOT_VG2_M2Z2Z_HtoS_PSEUDO = 394 + + BFDOT_VG2_M2ZZI_HtoS_PSEUDO = 395 + + BFDOT_VG2_M2ZZ_HtoS_PSEUDO = 396 + + BFDOT_VG4_M4Z4Z_HtoS_PSEUDO = 397 + + BFDOT_VG4_M4ZZI_HtoS_PSEUDO = 398 + + BFDOT_VG4_M4ZZ_HtoS_PSEUDO = 399 + + BFMAXNM_ZPZZ_UNDEF = 400 + + BFMAXNM_ZPZZ_ZERO = 401 + + BFMAX_ZPZZ_UNDEF = 402 + + BFMAX_ZPZZ_ZERO = 403 + + BFMINNM_ZPZZ_UNDEF = 404 + + BFMINNM_ZPZZ_ZERO = 405 + + BFMIN_ZPZZ_UNDEF = 406 + + BFMIN_ZPZZ_ZERO = 407 + + BFMLAL_MZZI_HtoS_PSEUDO = 408 + + BFMLAL_MZZ_HtoS_PSEUDO = 409 + + BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO = 410 + + BFMLAL_VG2_M2ZZI_HtoS_PSEUDO = 411 + + BFMLAL_VG2_M2ZZ_HtoS_PSEUDO = 412 + + BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO = 413 + + BFMLAL_VG4_M4ZZI_HtoS_PSEUDO = 414 + + BFMLAL_VG4_M4ZZ_HtoS_PSEUDO = 415 + + BFMLA_VG2_M2Z2Z_PSEUDO = 416 + + BFMLA_VG2_M2ZZI_PSEUDO = 417 + + BFMLA_VG2_M2ZZ_PSEUDO = 418 + + BFMLA_VG4_M4Z4Z_PSEUDO = 419 + + BFMLA_VG4_M4ZZI_PSEUDO = 420 + + BFMLA_VG4_M4ZZ_PSEUDO = 421 + + BFMLA_ZPZZZ_UNDEF = 422 + + BFMLSL_MZZI_HtoS_PSEUDO = 423 + + BFMLSL_MZZ_HtoS_PSEUDO = 424 + + BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO = 425 + + BFMLSL_VG2_M2ZZI_HtoS_PSEUDO = 426 + + BFMLSL_VG2_M2ZZ_HtoS_PSEUDO = 427 + + BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO = 428 + + BFMLSL_VG4_M4ZZI_HtoS_PSEUDO = 429 + + BFMLSL_VG4_M4ZZ_HtoS_PSEUDO = 430 + + BFMLS_VG2_M2Z2Z_PSEUDO = 431 + + BFMLS_VG2_M2ZZI_PSEUDO = 432 + + BFMLS_VG2_M2ZZ_PSEUDO = 433 + + BFMLS_VG4_M4Z4Z_PSEUDO = 434 + + BFMLS_VG4_M4ZZI_PSEUDO = 435 + + BFMLS_VG4_M4ZZ_PSEUDO = 436 + + BFMLS_ZPZZZ_UNDEF = 437 + + BFMOP4A_M2Z2Z_H_PSEUDO = 438 + + BFMOP4A_M2Z2Z_S_PSEUDO = 439 + + BFMOP4A_M2ZZ_H_PSEUDO = 440 + + BFMOP4A_M2ZZ_S_PSEUDO = 441 + + BFMOP4A_MZ2Z_H_PSEUDO = 442 + + BFMOP4A_MZ2Z_S_PSEUDO = 443 + + BFMOP4A_MZZ_H_PSEUDO = 444 + + BFMOP4A_MZZ_S_PSEUDO = 445 + + BFMOP4S_M2Z2Z_H_PSEUDO = 446 + + BFMOP4S_M2Z2Z_S_PSEUDO = 447 + + BFMOP4S_M2ZZ_H_PSEUDO = 448 + + BFMOP4S_M2ZZ_S_PSEUDO = 449 + + BFMOP4S_MZ2Z_H_PSEUDO = 450 + + BFMOP4S_MZ2Z_S_PSEUDO = 451 + + BFMOP4S_MZZ_H_PSEUDO = 452 + + BFMOP4S_MZZ_S_PSEUDO = 453 + + BFMOPA_MPPZZ_H_PSEUDO = 454 + + BFMOPA_MPPZZ_PSEUDO = 455 + + BFMOPS_MPPZZ_H_PSEUDO = 456 + + BFMOPS_MPPZZ_PSEUDO = 457 + + BFMUL_ZPZZ_UNDEF = 458 + + BFMUL_ZPZZ_ZERO = 459 + + BFSUB_VG2_M2Z_H_PSEUDO = 460 + + BFSUB_VG4_M4Z_H_PSEUDO = 461 + + BFSUB_ZPZZ_UNDEF = 462 + + BFSUB_ZPZZ_ZERO = 463 + + BFTMOPA_M2ZZZI_HtoH_PSEUDO = 464 + + BFTMOPA_M2ZZZI_HtoS_PSEUDO = 465 + + BFVDOT_VG2_M2ZZI_HtoS_PSEUDO = 466 + + BICSWrr = 467 + + BICSXrr = 468 + + BICWrr = 469 + + BICXrr = 470 + + BIC_ZPZZ_B_ZERO = 471 + + BIC_ZPZZ_D_ZERO = 472 + + BIC_ZPZZ_H_ZERO = 473 + + BIC_ZPZZ_S_ZERO = 474 + + BLRA = 475 + + BLRA_RVMARKER = 476 + + BLRNoIP = 477 + + BLR_BTI = 478 + + BLR_RVMARKER = 479 + + BLR_X16 = 480 + + BMOPA_MPPZZ_S_PSEUDO = 481 + + BMOPS_MPPZZ_S_PSEUDO = 482 + + BRA = 483 + + BR_JumpTable = 484 + + BSPv16i8 = 485 + + BSPv8i8 = 486 + + CATCHRET = 487 + + CBBAssertExt = 488 + + CBHAssertExt = 489 + + CBWPri = 490 + + CBWPrr = 491 + + CBXPri = 492 + + CBXPrr = 493 + + CHECK_MATCHING_VL_PSEUDO = 494 + + CLEANUPRET = 495 + + CLS_ZPmZ_B_UNDEF = 496 + + CLS_ZPmZ_D_UNDEF = 497 + + CLS_ZPmZ_H_UNDEF = 498 + + CLS_ZPmZ_S_UNDEF = 499 + + CLZ_ZPmZ_B_UNDEF = 500 + + CLZ_ZPmZ_D_UNDEF = 501 + + CLZ_ZPmZ_H_UNDEF = 502 + + CLZ_ZPmZ_S_UNDEF = 503 + + CMP_SWAP_128 = 504 + + CMP_SWAP_128_ACQUIRE = 505 + + CMP_SWAP_128_MONOTONIC = 506 + + CMP_SWAP_128_RELEASE = 507 + + CMP_SWAP_16 = 508 + + CMP_SWAP_32 = 509 + + CMP_SWAP_64 = 510 + + CMP_SWAP_8 = 511 + + CNOT_ZPmZ_B_UNDEF = 512 + + CNOT_ZPmZ_D_UNDEF = 513 + + CNOT_ZPmZ_H_UNDEF = 514 + + CNOT_ZPmZ_S_UNDEF = 515 + + CNT_ZPmZ_B_UNDEF = 516 + + CNT_ZPmZ_D_UNDEF = 517 + + CNT_ZPmZ_H_UNDEF = 518 + + CNT_ZPmZ_S_UNDEF = 519 + + COALESCER_BARRIER_FPR128 = 520 + + COALESCER_BARRIER_FPR16 = 521 + + COALESCER_BARRIER_FPR32 = 522 + + COALESCER_BARRIER_FPR64 = 523 + + CommitZASavePseudo = 524 + + EMITBKEY = 525 + + EMITMTETAGGED = 526 + + EONWrr = 527 + + EONXrr = 528 + + EORWrr = 529 + + EORXrr = 530 + + EOR_ZPZZ_B_ZERO = 531 + + EOR_ZPZZ_D_ZERO = 532 + + EOR_ZPZZ_H_ZERO = 533 + + EOR_ZPZZ_S_ZERO = 534 + + EXT_ZZI_CONSTRUCTIVE = 535 + + EntryPStateSM = 536 + + F128CSEL = 537 + + FABD_ZPZZ_D_UNDEF = 538 + + FABD_ZPZZ_D_ZERO = 539 + + FABD_ZPZZ_H_UNDEF = 540 + + FABD_ZPZZ_H_ZERO = 541 + + FABD_ZPZZ_S_UNDEF = 542 + + FABD_ZPZZ_S_ZERO = 543 + + FABS_ZPmZ_D_UNDEF = 544 + + FABS_ZPmZ_H_UNDEF = 545 + + FABS_ZPmZ_S_UNDEF = 546 + + FADD_VG2_M2Z_D_PSEUDO = 547 + + FADD_VG2_M2Z_H_PSEUDO = 548 + + FADD_VG2_M2Z_S_PSEUDO = 549 + + FADD_VG4_M4Z_D_PSEUDO = 550 + + FADD_VG4_M4Z_H_PSEUDO = 551 + + FADD_VG4_M4Z_S_PSEUDO = 552 + + FADD_ZPZI_D_UNDEF = 553 + + FADD_ZPZI_D_ZERO = 554 + + FADD_ZPZI_H_UNDEF = 555 + + FADD_ZPZI_H_ZERO = 556 + + FADD_ZPZI_S_UNDEF = 557 + + FADD_ZPZI_S_ZERO = 558 + + FADD_ZPZZ_D_UNDEF = 559 + + FADD_ZPZZ_D_ZERO = 560 + + FADD_ZPZZ_H_UNDEF = 561 + + FADD_ZPZZ_H_ZERO = 562 + + FADD_ZPZZ_S_UNDEF = 563 + + FADD_ZPZZ_S_ZERO = 564 + + FAMAX_ZPZZ_D_UNDEF = 565 + + FAMAX_ZPZZ_H_UNDEF = 566 + + FAMAX_ZPZZ_S_UNDEF = 567 + + FAMIN_ZPZZ_D_UNDEF = 568 + + FAMIN_ZPZZ_H_UNDEF = 569 + + FAMIN_ZPZZ_S_UNDEF = 570 + + FCVTZS_ZPmZ_DtoD_UNDEF = 571 + + FCVTZS_ZPmZ_DtoS_UNDEF = 572 + + FCVTZS_ZPmZ_HtoD_UNDEF = 573 + + FCVTZS_ZPmZ_HtoH_UNDEF = 574 + + FCVTZS_ZPmZ_HtoS_UNDEF = 575 + + FCVTZS_ZPmZ_StoD_UNDEF = 576 + + FCVTZS_ZPmZ_StoS_UNDEF = 577 + + FCVTZU_ZPmZ_DtoD_UNDEF = 578 + + FCVTZU_ZPmZ_DtoS_UNDEF = 579 + + FCVTZU_ZPmZ_HtoD_UNDEF = 580 + + FCVTZU_ZPmZ_HtoH_UNDEF = 581 + + FCVTZU_ZPmZ_HtoS_UNDEF = 582 + + FCVTZU_ZPmZ_StoD_UNDEF = 583 + + FCVTZU_ZPmZ_StoS_UNDEF = 584 + + FCVT_ZPmZ_DtoH_UNDEF = 585 + + FCVT_ZPmZ_DtoS_UNDEF = 586 + + FCVT_ZPmZ_HtoD_UNDEF = 587 + + FCVT_ZPmZ_HtoS_UNDEF = 588 + + FCVT_ZPmZ_StoD_UNDEF = 589 + + FCVT_ZPmZ_StoH_UNDEF = 590 + + FDIVR_ZPZZ_D_ZERO = 591 + + FDIVR_ZPZZ_H_ZERO = 592 + + FDIVR_ZPZZ_S_ZERO = 593 + + FDIV_ZPZZ_D_UNDEF = 594 + + FDIV_ZPZZ_D_ZERO = 595 + + FDIV_ZPZZ_H_UNDEF = 596 + + FDIV_ZPZZ_H_ZERO = 597 + + FDIV_ZPZZ_S_UNDEF = 598 + + FDIV_ZPZZ_S_ZERO = 599 + + FDOT_VG2_M2Z2Z_BtoH_PSEUDO = 600 + + FDOT_VG2_M2Z2Z_BtoS_PSEUDO = 601 + + FDOT_VG2_M2Z2Z_HtoS_PSEUDO = 602 + + FDOT_VG2_M2ZZI_BtoH_PSEUDO = 603 + + FDOT_VG2_M2ZZI_BtoS_PSEUDO = 604 + + FDOT_VG2_M2ZZI_HtoS_PSEUDO = 605 + + FDOT_VG2_M2ZZ_BtoH_PSEUDO = 606 + + FDOT_VG2_M2ZZ_BtoS_PSEUDO = 607 + + FDOT_VG2_M2ZZ_HtoS_PSEUDO = 608 + + FDOT_VG4_M4Z4Z_BtoH_PSEUDO = 609 + + FDOT_VG4_M4Z4Z_BtoS_PSEUDO = 610 + + FDOT_VG4_M4Z4Z_HtoS_PSEUDO = 611 + + FDOT_VG4_M4ZZI_BtoH_PSEUDO = 612 + + FDOT_VG4_M4ZZI_BtoS_PSEUDO = 613 + + FDOT_VG4_M4ZZI_HtoS_PSEUDO = 614 + + FDOT_VG4_M4ZZ_BtoH_PSEUDO = 615 + + FDOT_VG4_M4ZZ_BtoS_PSEUDO = 616 + + FDOT_VG4_M4ZZ_HtoS_PSEUDO = 617 + + FLOGB_ZPZZ_D_ZERO = 618 + + FLOGB_ZPZZ_H_ZERO = 619 + + FLOGB_ZPZZ_S_ZERO = 620 + + FMAXNM_ZPZI_D_UNDEF = 621 + + FMAXNM_ZPZI_D_ZERO = 622 + + FMAXNM_ZPZI_H_UNDEF = 623 + + FMAXNM_ZPZI_H_ZERO = 624 + + FMAXNM_ZPZI_S_UNDEF = 625 + + FMAXNM_ZPZI_S_ZERO = 626 + + FMAXNM_ZPZZ_D_UNDEF = 627 + + FMAXNM_ZPZZ_D_ZERO = 628 + + FMAXNM_ZPZZ_H_UNDEF = 629 + + FMAXNM_ZPZZ_H_ZERO = 630 + + FMAXNM_ZPZZ_S_UNDEF = 631 + + FMAXNM_ZPZZ_S_ZERO = 632 + + FMAX_ZPZI_D_UNDEF = 633 + + FMAX_ZPZI_D_ZERO = 634 + + FMAX_ZPZI_H_UNDEF = 635 + + FMAX_ZPZI_H_ZERO = 636 + + FMAX_ZPZI_S_UNDEF = 637 + + FMAX_ZPZI_S_ZERO = 638 + + FMAX_ZPZZ_D_UNDEF = 639 + + FMAX_ZPZZ_D_ZERO = 640 + + FMAX_ZPZZ_H_UNDEF = 641 + + FMAX_ZPZZ_H_ZERO = 642 + + FMAX_ZPZZ_S_UNDEF = 643 + + FMAX_ZPZZ_S_ZERO = 644 + + FMINNM_ZPZI_D_UNDEF = 645 + + FMINNM_ZPZI_D_ZERO = 646 + + FMINNM_ZPZI_H_UNDEF = 647 + + FMINNM_ZPZI_H_ZERO = 648 + + FMINNM_ZPZI_S_UNDEF = 649 + + FMINNM_ZPZI_S_ZERO = 650 + + FMINNM_ZPZZ_D_UNDEF = 651 + + FMINNM_ZPZZ_D_ZERO = 652 + + FMINNM_ZPZZ_H_UNDEF = 653 + + FMINNM_ZPZZ_H_ZERO = 654 + + FMINNM_ZPZZ_S_UNDEF = 655 + + FMINNM_ZPZZ_S_ZERO = 656 + + FMIN_ZPZI_D_UNDEF = 657 + + FMIN_ZPZI_D_ZERO = 658 + + FMIN_ZPZI_H_UNDEF = 659 + + FMIN_ZPZI_H_ZERO = 660 + + FMIN_ZPZI_S_UNDEF = 661 + + FMIN_ZPZI_S_ZERO = 662 + + FMIN_ZPZZ_D_UNDEF = 663 + + FMIN_ZPZZ_D_ZERO = 664 + + FMIN_ZPZZ_H_UNDEF = 665 + + FMIN_ZPZZ_H_ZERO = 666 + + FMIN_ZPZZ_S_UNDEF = 667 + + FMIN_ZPZZ_S_ZERO = 668 + + FMLALL_MZZI_BtoS_PSEUDO = 669 + + FMLALL_MZZ_BtoS_PSEUDO = 670 + + FMLALL_VG2_M2Z2Z_BtoS_PSEUDO = 671 + + FMLALL_VG2_M2ZZI_BtoS_PSEUDO = 672 + + FMLALL_VG2_M2ZZ_BtoS_PSEUDO = 673 + + FMLALL_VG4_M4Z4Z_BtoS_PSEUDO = 674 + + FMLALL_VG4_M4ZZI_BtoS_PSEUDO = 675 + + FMLALL_VG4_M4ZZ_BtoS_PSEUDO = 676 + + FMLAL_MZZI_BtoH_PSEUDO = 677 + + FMLAL_MZZI_HtoS_PSEUDO = 678 + + FMLAL_MZZ_HtoS_PSEUDO = 679 + + FMLAL_VG2_M2Z2Z_BtoH_PSEUDO = 680 + + FMLAL_VG2_M2Z2Z_HtoS_PSEUDO = 681 + + FMLAL_VG2_M2ZZI_BtoH_PSEUDO = 682 + + FMLAL_VG2_M2ZZI_HtoS_PSEUDO = 683 + + FMLAL_VG2_M2ZZ_BtoH_PSEUDO = 684 + + FMLAL_VG2_M2ZZ_HtoS_PSEUDO = 685 + + FMLAL_VG2_MZZ_BtoH_PSEUDO = 686 + + FMLAL_VG4_M4Z4Z_BtoH_PSEUDO = 687 + + FMLAL_VG4_M4Z4Z_HtoS_PSEUDO = 688 + + FMLAL_VG4_M4ZZI_BtoH_PSEUDO = 689 + + FMLAL_VG4_M4ZZI_HtoS_PSEUDO = 690 + + FMLAL_VG4_M4ZZ_BtoH_PSEUDO = 691 + + FMLAL_VG4_M4ZZ_HtoS_PSEUDO = 692 + + FMLA_VG2_M2Z2Z_D_PSEUDO = 693 + + FMLA_VG2_M2Z2Z_H_PSEUDO = 694 + + FMLA_VG2_M2Z2Z_S_PSEUDO = 695 + + FMLA_VG2_M2ZZI_D_PSEUDO = 696 + + FMLA_VG2_M2ZZI_H_PSEUDO = 697 + + FMLA_VG2_M2ZZI_S_PSEUDO = 698 + + FMLA_VG2_M2ZZ_D_PSEUDO = 699 + + FMLA_VG2_M2ZZ_H_PSEUDO = 700 + + FMLA_VG2_M2ZZ_S_PSEUDO = 701 + + FMLA_VG4_M4Z4Z_D_PSEUDO = 702 + + FMLA_VG4_M4Z4Z_H_PSEUDO = 703 + + FMLA_VG4_M4Z4Z_S_PSEUDO = 704 + + FMLA_VG4_M4ZZI_D_PSEUDO = 705 + + FMLA_VG4_M4ZZI_H_PSEUDO = 706 + + FMLA_VG4_M4ZZI_S_PSEUDO = 707 + + FMLA_VG4_M4ZZ_D_PSEUDO = 708 + + FMLA_VG4_M4ZZ_H_PSEUDO = 709 + + FMLA_VG4_M4ZZ_S_PSEUDO = 710 + + FMLA_ZPZZZ_D_UNDEF = 711 + + FMLA_ZPZZZ_H_UNDEF = 712 + + FMLA_ZPZZZ_S_UNDEF = 713 + + FMLSL_MZZI_HtoS_PSEUDO = 714 + + FMLSL_MZZ_HtoS_PSEUDO = 715 + + FMLSL_VG2_M2Z2Z_HtoS_PSEUDO = 716 + + FMLSL_VG2_M2ZZI_HtoS_PSEUDO = 717 + + FMLSL_VG2_M2ZZ_HtoS_PSEUDO = 718 + + FMLSL_VG4_M4Z4Z_HtoS_PSEUDO = 719 + + FMLSL_VG4_M4ZZI_HtoS_PSEUDO = 720 + + FMLSL_VG4_M4ZZ_HtoS_PSEUDO = 721 + + FMLS_VG2_M2Z2Z_D_PSEUDO = 722 + + FMLS_VG2_M2Z2Z_H_PSEUDO = 723 + + FMLS_VG2_M2Z2Z_S_PSEUDO = 724 + + FMLS_VG2_M2ZZI_D_PSEUDO = 725 + + FMLS_VG2_M2ZZI_H_PSEUDO = 726 + + FMLS_VG2_M2ZZI_S_PSEUDO = 727 + + FMLS_VG2_M2ZZ_D_PSEUDO = 728 + + FMLS_VG2_M2ZZ_H_PSEUDO = 729 + + FMLS_VG2_M2ZZ_S_PSEUDO = 730 + + FMLS_VG4_M4Z4Z_D_PSEUDO = 731 + + FMLS_VG4_M4Z4Z_H_PSEUDO = 732 + + FMLS_VG4_M4Z4Z_S_PSEUDO = 733 + + FMLS_VG4_M4ZZI_D_PSEUDO = 734 + + FMLS_VG4_M4ZZI_H_PSEUDO = 735 + + FMLS_VG4_M4ZZI_S_PSEUDO = 736 + + FMLS_VG4_M4ZZ_D_PSEUDO = 737 + + FMLS_VG4_M4ZZ_H_PSEUDO = 738 + + FMLS_VG4_M4ZZ_S_PSEUDO = 739 + + FMLS_ZPZZZ_D_UNDEF = 740 + + FMLS_ZPZZZ_H_UNDEF = 741 + + FMLS_ZPZZZ_S_UNDEF = 742 + + FMOP4A_M2Z2Z_BtoH_PSEUDO = 743 + + FMOP4A_M2Z2Z_BtoS_PSEUDO = 744 + + FMOP4A_M2Z2Z_D_PSEUDO = 745 + + FMOP4A_M2Z2Z_H_PSEUDO = 746 + + FMOP4A_M2Z2Z_HtoS_PSEUDO = 747 + + FMOP4A_M2Z2Z_S_PSEUDO = 748 + + FMOP4A_M2ZZ_BtoH_PSEUDO = 749 + + FMOP4A_M2ZZ_BtoS_PSEUDO = 750 + + FMOP4A_M2ZZ_D_PSEUDO = 751 + + FMOP4A_M2ZZ_H_PSEUDO = 752 + + FMOP4A_M2ZZ_HtoS_PSEUDO = 753 + + FMOP4A_M2ZZ_S_PSEUDO = 754 + + FMOP4A_MZ2Z_BtoH_PSEUDO = 755 + + FMOP4A_MZ2Z_BtoS_PSEUDO = 756 + + FMOP4A_MZ2Z_D_PSEUDO = 757 + + FMOP4A_MZ2Z_H_PSEUDO = 758 + + FMOP4A_MZ2Z_HtoS_PSEUDO = 759 + + FMOP4A_MZ2Z_S_PSEUDO = 760 + + FMOP4A_MZZ_BtoH_PSEUDO = 761 + + FMOP4A_MZZ_BtoS_PSEUDO = 762 + + FMOP4A_MZZ_D_PSEUDO = 763 + + FMOP4A_MZZ_H_PSEUDO = 764 + + FMOP4A_MZZ_HtoS_PSEUDO = 765 + + FMOP4A_MZZ_S_PSEUDO = 766 + + FMOP4S_M2Z2Z_D_PSEUDO = 767 + + FMOP4S_M2Z2Z_H_PSEUDO = 768 + + FMOP4S_M2Z2Z_HtoS_PSEUDO = 769 + + FMOP4S_M2Z2Z_S_PSEUDO = 770 + + FMOP4S_M2ZZ_D_PSEUDO = 771 + + FMOP4S_M2ZZ_H_PSEUDO = 772 + + FMOP4S_M2ZZ_HtoS_PSEUDO = 773 + + FMOP4S_M2ZZ_S_PSEUDO = 774 + + FMOP4S_MZ2Z_D_PSEUDO = 775 + + FMOP4S_MZ2Z_H_PSEUDO = 776 + + FMOP4S_MZ2Z_HtoS_PSEUDO = 777 + + FMOP4S_MZ2Z_S_PSEUDO = 778 + + FMOP4S_MZZ_D_PSEUDO = 779 + + FMOP4S_MZZ_H_PSEUDO = 780 + + FMOP4S_MZZ_HtoS_PSEUDO = 781 + + FMOP4S_MZZ_S_PSEUDO = 782 + + FMOPAL_MPPZZ_PSEUDO = 783 + + FMOPA_MPPZZ_BtoH_PSEUDO = 784 + + FMOPA_MPPZZ_BtoS_PSEUDO = 785 + + FMOPA_MPPZZ_D_PSEUDO = 786 + + FMOPA_MPPZZ_H_PSEUDO = 787 + + FMOPA_MPPZZ_S_PSEUDO = 788 + + FMOPSL_MPPZZ_PSEUDO = 789 + + FMOPS_MPPZZ_D_PSEUDO = 790 + + FMOPS_MPPZZ_H_PSEUDO = 791 + + FMOPS_MPPZZ_S_PSEUDO = 792 + + FMOVD0 = 793 + + FMOVH0 = 794 + + FMOVS0 = 795 + + FMULX_ZPZZ_D_UNDEF = 796 + + FMULX_ZPZZ_D_ZERO = 797 + + FMULX_ZPZZ_H_UNDEF = 798 + + FMULX_ZPZZ_H_ZERO = 799 + + FMULX_ZPZZ_S_UNDEF = 800 + + FMULX_ZPZZ_S_ZERO = 801 + + FMUL_ZPZI_D_UNDEF = 802 + + FMUL_ZPZI_D_ZERO = 803 + + FMUL_ZPZI_H_UNDEF = 804 + + FMUL_ZPZI_H_ZERO = 805 + + FMUL_ZPZI_S_UNDEF = 806 + + FMUL_ZPZI_S_ZERO = 807 + + FMUL_ZPZZ_D_UNDEF = 808 + + FMUL_ZPZZ_D_ZERO = 809 + + FMUL_ZPZZ_H_UNDEF = 810 + + FMUL_ZPZZ_H_ZERO = 811 + + FMUL_ZPZZ_S_UNDEF = 812 + + FMUL_ZPZZ_S_ZERO = 813 + + FNEG_ZPmZ_D_UNDEF = 814 + + FNEG_ZPmZ_H_UNDEF = 815 + + FNEG_ZPmZ_S_UNDEF = 816 + + FNMLA_ZPZZZ_D_UNDEF = 817 + + FNMLA_ZPZZZ_H_UNDEF = 818 + + FNMLA_ZPZZZ_S_UNDEF = 819 + + FNMLS_ZPZZZ_D_UNDEF = 820 + + FNMLS_ZPZZZ_H_UNDEF = 821 + + FNMLS_ZPZZZ_S_UNDEF = 822 + + FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO = 823 + + FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO = 824 + + FRECPX_ZPmZ_D_UNDEF = 825 + + FRECPX_ZPmZ_H_UNDEF = 826 + + FRECPX_ZPmZ_S_UNDEF = 827 + + FRINT32X_ZPmZ_D_UNDEF = 828 + + FRINT32X_ZPmZ_S_UNDEF = 829 + + FRINT32Z_ZPmZ_D_UNDEF = 830 + + FRINT32Z_ZPmZ_S_UNDEF = 831 + + FRINT64X_ZPmZ_D_UNDEF = 832 + + FRINT64X_ZPmZ_S_UNDEF = 833 + + FRINT64Z_ZPmZ_D_UNDEF = 834 + + FRINT64Z_ZPmZ_S_UNDEF = 835 + + FRINTA_ZPmZ_D_UNDEF = 836 + + FRINTA_ZPmZ_H_UNDEF = 837 + + FRINTA_ZPmZ_S_UNDEF = 838 + + FRINTI_ZPmZ_D_UNDEF = 839 + + FRINTI_ZPmZ_H_UNDEF = 840 + + FRINTI_ZPmZ_S_UNDEF = 841 + + FRINTM_ZPmZ_D_UNDEF = 842 + + FRINTM_ZPmZ_H_UNDEF = 843 + + FRINTM_ZPmZ_S_UNDEF = 844 + + FRINTN_ZPmZ_D_UNDEF = 845 + + FRINTN_ZPmZ_H_UNDEF = 846 + + FRINTN_ZPmZ_S_UNDEF = 847 + + FRINTP_ZPmZ_D_UNDEF = 848 + + FRINTP_ZPmZ_H_UNDEF = 849 + + FRINTP_ZPmZ_S_UNDEF = 850 + + FRINTX_ZPmZ_D_UNDEF = 851 + + FRINTX_ZPmZ_H_UNDEF = 852 + + FRINTX_ZPmZ_S_UNDEF = 853 + + FRINTZ_ZPmZ_D_UNDEF = 854 + + FRINTZ_ZPmZ_H_UNDEF = 855 + + FRINTZ_ZPmZ_S_UNDEF = 856 + + FSQRT_ZPmZ_D_UNDEF = 857 + + FSQRT_ZPmZ_H_UNDEF = 858 + + FSQRT_ZPmZ_S_UNDEF = 859 + + FSUBR_ZPZI_D_UNDEF = 860 + + FSUBR_ZPZI_D_ZERO = 861 + + FSUBR_ZPZI_H_UNDEF = 862 + + FSUBR_ZPZI_H_ZERO = 863 + + FSUBR_ZPZI_S_UNDEF = 864 + + FSUBR_ZPZI_S_ZERO = 865 + + FSUBR_ZPZZ_D_ZERO = 866 + + FSUBR_ZPZZ_H_ZERO = 867 + + FSUBR_ZPZZ_S_ZERO = 868 + + FSUB_VG2_M2Z_D_PSEUDO = 869 + + FSUB_VG2_M2Z_H_PSEUDO = 870 + + FSUB_VG2_M2Z_S_PSEUDO = 871 + + FSUB_VG4_M4Z_D_PSEUDO = 872 + + FSUB_VG4_M4Z_H_PSEUDO = 873 + + FSUB_VG4_M4Z_S_PSEUDO = 874 + + FSUB_ZPZI_D_UNDEF = 875 + + FSUB_ZPZI_D_ZERO = 876 + + FSUB_ZPZI_H_UNDEF = 877 + + FSUB_ZPZI_H_ZERO = 878 + + FSUB_ZPZI_S_UNDEF = 879 + + FSUB_ZPZI_S_ZERO = 880 + + FSUB_ZPZZ_D_UNDEF = 881 + + FSUB_ZPZZ_D_ZERO = 882 + + FSUB_ZPZZ_H_UNDEF = 883 + + FSUB_ZPZZ_H_ZERO = 884 + + FSUB_ZPZZ_S_UNDEF = 885 + + FSUB_ZPZZ_S_ZERO = 886 + + FTMOPA_M2ZZZI_BtoH_PSEUDO = 887 + + FTMOPA_M2ZZZI_BtoS_PSEUDO = 888 + + FTMOPA_M2ZZZI_HtoH_PSEUDO = 889 + + FTMOPA_M2ZZZI_HtoS_PSEUDO = 890 + + FTMOPA_M2ZZZI_StoS_PSEUDO = 891 + + FVDOTB_VG4_M2ZZI_BtoS_PSEUDO = 892 + + FVDOTT_VG4_M2ZZI_BtoS_PSEUDO = 893 + + FVDOT_VG2_M2ZZI_BtoH_PSEUDO = 894 + + FVDOT_VG2_M2ZZI_HtoS_PSEUDO = 895 + + G_AARCH64_PREFETCH = 896 + + G_AARCH64_RANGE_PREFETCH = 897 + + G_ADD_LOW = 898 + + G_BSP = 899 + + G_DUP = 900 + + G_DUPLANE16 = 901 + + G_DUPLANE32 = 902 + + G_DUPLANE64 = 903 + + G_DUPLANE8 = 904 + + G_EXT = 905 + + G_FCMEQ = 906 + + G_FCMGE = 907 + + G_FCMGT = 908 + + G_FPTRUNC_ODD = 909 + + G_PMULL = 910 + + G_REV16 = 911 + + G_REV32 = 912 + + G_REV64 = 913 + + G_SADDLP = 914 + + G_SADDLV = 915 + + G_SDOT = 916 + + G_SITOF = 917 + + G_SLI = 918 + + G_SMULL = 919 + + G_SQSHLU_I = 920 + + G_SRI = 921 + + G_SRSHR_I = 922 + + G_TRN1 = 923 + + G_TRN2 = 924 + + G_UADDLP = 925 + + G_UADDLV = 926 + + G_UDOT = 927 + + G_UITOF = 928 + + G_UMULL = 929 + + G_URSHR_I = 930 + + G_USDOT = 931 + + G_UZP1 = 932 + + G_UZP2 = 933 + + G_VASHR = 934 + + G_VLSHR = 935 + + G_ZIP1 = 936 + + G_ZIP2 = 937 + + GetSMESaveSize = 938 + + HOM_Epilog = 939 + + HOM_Prolog = 940 + + HWASAN_CHECK_MEMACCESS = 941 + + HWASAN_CHECK_MEMACCESS_FIXEDSHADOW = 942 + + HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 943 + + HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW = 944 + + INSERT_MXIPZ_H_PSEUDO_B = 945 + + INSERT_MXIPZ_H_PSEUDO_D = 946 + + INSERT_MXIPZ_H_PSEUDO_H = 947 + + INSERT_MXIPZ_H_PSEUDO_Q = 948 + + INSERT_MXIPZ_H_PSEUDO_S = 949 + + INSERT_MXIPZ_V_PSEUDO_B = 950 + + INSERT_MXIPZ_V_PSEUDO_D = 951 + + INSERT_MXIPZ_V_PSEUDO_H = 952 + + INSERT_MXIPZ_V_PSEUDO_Q = 953 + + INSERT_MXIPZ_V_PSEUDO_S = 954 + + IRGstack = 955 + + InOutZAUsePseudo = 956 + + InitTPIDR2Obj = 957 + + JumpTableDest16 = 958 + + JumpTableDest32 = 959 + + JumpTableDest8 = 960 + + KCFI_CHECK = 961 + + LD1B_2Z_IMM_PSEUDO = 962 + + LD1B_2Z_PSEUDO = 963 + + LD1B_4Z_IMM_PSEUDO = 964 + + LD1B_4Z_PSEUDO = 965 + + LD1D_2Z_IMM_PSEUDO = 966 + + LD1D_2Z_PSEUDO = 967 + + LD1D_4Z_IMM_PSEUDO = 968 + + LD1D_4Z_PSEUDO = 969 + + LD1H_2Z_IMM_PSEUDO = 970 + + LD1H_2Z_PSEUDO = 971 + + LD1H_4Z_IMM_PSEUDO = 972 + + LD1H_4Z_PSEUDO = 973 + + LD1W_2Z_IMM_PSEUDO = 974 + + LD1W_2Z_PSEUDO = 975 + + LD1W_4Z_IMM_PSEUDO = 976 + + LD1W_4Z_PSEUDO = 977 + + LD1_MXIPXX_H_PSEUDO_B = 978 + + LD1_MXIPXX_H_PSEUDO_D = 979 + + LD1_MXIPXX_H_PSEUDO_H = 980 + + LD1_MXIPXX_H_PSEUDO_Q = 981 + + LD1_MXIPXX_H_PSEUDO_S = 982 + + LD1_MXIPXX_V_PSEUDO_B = 983 + + LD1_MXIPXX_V_PSEUDO_D = 984 + + LD1_MXIPXX_V_PSEUDO_H = 985 + + LD1_MXIPXX_V_PSEUDO_Q = 986 + + LD1_MXIPXX_V_PSEUDO_S = 987 + + LDNT1B_2Z_IMM_PSEUDO = 988 + + LDNT1B_2Z_PSEUDO = 989 + + LDNT1B_4Z_IMM_PSEUDO = 990 + + LDNT1B_4Z_PSEUDO = 991 + + LDNT1D_2Z_IMM_PSEUDO = 992 + + LDNT1D_2Z_PSEUDO = 993 + + LDNT1D_4Z_IMM_PSEUDO = 994 + + LDNT1D_4Z_PSEUDO = 995 + + LDNT1H_2Z_IMM_PSEUDO = 996 + + LDNT1H_2Z_PSEUDO = 997 + + LDNT1H_4Z_IMM_PSEUDO = 998 + + LDNT1H_4Z_PSEUDO = 999 + + LDNT1W_2Z_IMM_PSEUDO = 1000 + + LDNT1W_2Z_PSEUDO = 1001 + + LDNT1W_4Z_IMM_PSEUDO = 1002 + + LDNT1W_4Z_PSEUDO = 1003 + + LDR_PPXI = 1004 + + LDR_TX_PSEUDO = 1005 + + LDR_ZA_PSEUDO = 1006 + + LDR_ZZXI = 1007 + + LDR_ZZXI_STRIDED_CONTIGUOUS = 1008 + + LDR_ZZZXI = 1009 + + LDR_ZZZZXI = 1010 + + LDR_ZZZZXI_STRIDED_CONTIGUOUS = 1011 + + LOADauthptrstatic = 1012 + + LOADgot = 1013 + + LOADgotAUTH = 1014 + + LOADgotPAC = 1015 + + LSL_ZPZI_B_UNDEF = 1016 + + LSL_ZPZI_B_ZERO = 1017 + + LSL_ZPZI_D_UNDEF = 1018 + + LSL_ZPZI_D_ZERO = 1019 + + LSL_ZPZI_H_UNDEF = 1020 + + LSL_ZPZI_H_ZERO = 1021 + + LSL_ZPZI_S_UNDEF = 1022 + + LSL_ZPZI_S_ZERO = 1023 + + LSL_ZPZZ_B_UNDEF = 1024 + + LSL_ZPZZ_B_ZERO = 1025 + + LSL_ZPZZ_D_UNDEF = 1026 + + LSL_ZPZZ_D_ZERO = 1027 + + LSL_ZPZZ_H_UNDEF = 1028 + + LSL_ZPZZ_H_ZERO = 1029 + + LSL_ZPZZ_S_UNDEF = 1030 + + LSL_ZPZZ_S_ZERO = 1031 + + LSR_ZPZI_B_UNDEF = 1032 + + LSR_ZPZI_B_ZERO = 1033 + + LSR_ZPZI_D_UNDEF = 1034 + + LSR_ZPZI_D_ZERO = 1035 + + LSR_ZPZI_H_UNDEF = 1036 + + LSR_ZPZI_H_ZERO = 1037 + + LSR_ZPZI_S_UNDEF = 1038 + + LSR_ZPZI_S_ZERO = 1039 + + LSR_ZPZZ_B_UNDEF = 1040 + + LSR_ZPZZ_B_ZERO = 1041 + + LSR_ZPZZ_D_UNDEF = 1042 + + LSR_ZPZZ_D_ZERO = 1043 + + LSR_ZPZZ_H_UNDEF = 1044 + + LSR_ZPZZ_H_ZERO = 1045 + + LSR_ZPZZ_S_UNDEF = 1046 + + LSR_ZPZZ_S_ZERO = 1047 + + MLA_ZPZZZ_B_UNDEF = 1048 + + MLA_ZPZZZ_D_UNDEF = 1049 + + MLA_ZPZZZ_H_UNDEF = 1050 + + MLA_ZPZZZ_S_UNDEF = 1051 + + MLS_ZPZZZ_B_UNDEF = 1052 + + MLS_ZPZZZ_D_UNDEF = 1053 + + MLS_ZPZZZ_H_UNDEF = 1054 + + MLS_ZPZZZ_S_UNDEF = 1055 + + MOPSMemoryCopyPseudo = 1056 + + MOPSMemoryMovePseudo = 1057 + + MOPSMemorySetPseudo = 1058 + + MOPSMemorySetTaggingPseudo = 1059 + + MOVAZ_2ZMI_H_B_PSEUDO = 1060 + + MOVAZ_2ZMI_H_D_PSEUDO = 1061 + + MOVAZ_2ZMI_H_H_PSEUDO = 1062 + + MOVAZ_2ZMI_H_S_PSEUDO = 1063 + + MOVAZ_2ZMI_V_B_PSEUDO = 1064 + + MOVAZ_2ZMI_V_D_PSEUDO = 1065 + + MOVAZ_2ZMI_V_H_PSEUDO = 1066 + + MOVAZ_2ZMI_V_S_PSEUDO = 1067 + + MOVAZ_4ZMI_H_B_PSEUDO = 1068 + + MOVAZ_4ZMI_H_D_PSEUDO = 1069 + + MOVAZ_4ZMI_H_H_PSEUDO = 1070 + + MOVAZ_4ZMI_H_S_PSEUDO = 1071 + + MOVAZ_4ZMI_V_B_PSEUDO = 1072 + + MOVAZ_4ZMI_V_D_PSEUDO = 1073 + + MOVAZ_4ZMI_V_H_PSEUDO = 1074 + + MOVAZ_4ZMI_V_S_PSEUDO = 1075 + + MOVAZ_VG2_2ZMXI_PSEUDO = 1076 + + MOVAZ_VG4_4ZMXI_PSEUDO = 1077 + + MOVAZ_ZMI_H_B_PSEUDO = 1078 + + MOVAZ_ZMI_H_D_PSEUDO = 1079 + + MOVAZ_ZMI_H_H_PSEUDO = 1080 + + MOVAZ_ZMI_H_Q_PSEUDO = 1081 + + MOVAZ_ZMI_H_S_PSEUDO = 1082 + + MOVAZ_ZMI_V_B_PSEUDO = 1083 + + MOVAZ_ZMI_V_D_PSEUDO = 1084 + + MOVAZ_ZMI_V_H_PSEUDO = 1085 + + MOVAZ_ZMI_V_Q_PSEUDO = 1086 + + MOVAZ_ZMI_V_S_PSEUDO = 1087 + + MOVA_MXI2Z_H_B_PSEUDO = 1088 + + MOVA_MXI2Z_H_D_PSEUDO = 1089 + + MOVA_MXI2Z_H_H_PSEUDO = 1090 + + MOVA_MXI2Z_H_S_PSEUDO = 1091 + + MOVA_MXI2Z_V_B_PSEUDO = 1092 + + MOVA_MXI2Z_V_D_PSEUDO = 1093 + + MOVA_MXI2Z_V_H_PSEUDO = 1094 + + MOVA_MXI2Z_V_S_PSEUDO = 1095 + + MOVA_MXI4Z_H_B_PSEUDO = 1096 + + MOVA_MXI4Z_H_D_PSEUDO = 1097 + + MOVA_MXI4Z_H_H_PSEUDO = 1098 + + MOVA_MXI4Z_H_S_PSEUDO = 1099 + + MOVA_MXI4Z_V_B_PSEUDO = 1100 + + MOVA_MXI4Z_V_D_PSEUDO = 1101 + + MOVA_MXI4Z_V_H_PSEUDO = 1102 + + MOVA_MXI4Z_V_S_PSEUDO = 1103 + + MOVA_VG2_MXI2Z_PSEUDO = 1104 + + MOVA_VG4_MXI4Z_PSEUDO = 1105 + + MOVMCSym = 1106 + + MOVT_TIZ_PSEUDO = 1107 + + MOVaddr = 1108 + + MOVaddrBA = 1109 + + MOVaddrCP = 1110 + + MOVaddrEXT = 1111 + + MOVaddrJT = 1112 + + MOVaddrPAC = 1113 + + MOVaddrTLS = 1114 + + MOVbaseTLS = 1115 + + MOVi32imm = 1116 + + MOVi64imm = 1117 + + MRS_FPCR = 1118 + + MRS_FPSR = 1119 + + MSR_FPCR = 1120 + + MSR_FPMR = 1121 + + MSR_FPSR = 1122 + + MSRpstatePseudo = 1123 + + MUL_ZPZZ_B_UNDEF = 1124 + + MUL_ZPZZ_D_UNDEF = 1125 + + MUL_ZPZZ_H_UNDEF = 1126 + + MUL_ZPZZ_S_UNDEF = 1127 + + NEG_ZPmZ_B_UNDEF = 1128 + + NEG_ZPmZ_D_UNDEF = 1129 + + NEG_ZPmZ_H_UNDEF = 1130 + + NEG_ZPmZ_S_UNDEF = 1131 + + NOT_ZPmZ_B_UNDEF = 1132 + + NOT_ZPmZ_D_UNDEF = 1133 + + NOT_ZPmZ_H_UNDEF = 1134 + + NOT_ZPmZ_S_UNDEF = 1135 + + ORNWrr = 1136 + + ORNXrr = 1137 + + ORRWrr = 1138 + + ORRXrr = 1139 + + ORR_ZPZZ_B_ZERO = 1140 + + ORR_ZPZZ_D_ZERO = 1141 + + ORR_ZPZZ_H_ZERO = 1142 + + ORR_ZPZZ_S_ZERO = 1143 + + PAC = 1144 + + PAUTH_EPILOGUE = 1145 + + PAUTH_PROLOGUE = 1146 + + PROBED_STACKALLOC = 1147 + + PROBED_STACKALLOC_DYN = 1148 + + PROBED_STACKALLOC_VAR = 1149 + + PTEST_PP_ANY = 1150 + + PTEST_PP_FIRST = 1151 + + RET_ReallyLR = 1152 + + RequiresZASavePseudo = 1153 + + RequiresZT0SavePseudo = 1154 + + RestoreZAPseudo = 1155 + + SABD_ZPZZ_B_UNDEF = 1156 + + SABD_ZPZZ_D_UNDEF = 1157 + + SABD_ZPZZ_H_UNDEF = 1158 + + SABD_ZPZZ_S_UNDEF = 1159 + + SCVTF_ZPmZ_DtoD_UNDEF = 1160 + + SCVTF_ZPmZ_DtoH_UNDEF = 1161 + + SCVTF_ZPmZ_DtoS_UNDEF = 1162 + + SCVTF_ZPmZ_HtoH_UNDEF = 1163 + + SCVTF_ZPmZ_StoD_UNDEF = 1164 + + SCVTF_ZPmZ_StoH_UNDEF = 1165 + + SCVTF_ZPmZ_StoS_UNDEF = 1166 + + SDIV_ZPZZ_D_UNDEF = 1167 + + SDIV_ZPZZ_S_UNDEF = 1168 + + SDOT_VG2_M2Z2Z_BtoS_PSEUDO = 1169 + + SDOT_VG2_M2Z2Z_HtoD_PSEUDO = 1170 + + SDOT_VG2_M2Z2Z_HtoS_PSEUDO = 1171 + + SDOT_VG2_M2ZZI_BToS_PSEUDO = 1172 + + SDOT_VG2_M2ZZI_HToS_PSEUDO = 1173 + + SDOT_VG2_M2ZZI_HtoD_PSEUDO = 1174 + + SDOT_VG2_M2ZZ_BtoS_PSEUDO = 1175 + + SDOT_VG2_M2ZZ_HtoD_PSEUDO = 1176 + + SDOT_VG2_M2ZZ_HtoS_PSEUDO = 1177 + + SDOT_VG4_M4Z4Z_BtoS_PSEUDO = 1178 + + SDOT_VG4_M4Z4Z_HtoD_PSEUDO = 1179 + + SDOT_VG4_M4Z4Z_HtoS_PSEUDO = 1180 + + SDOT_VG4_M4ZZI_BToS_PSEUDO = 1181 + + SDOT_VG4_M4ZZI_HToS_PSEUDO = 1182 + + SDOT_VG4_M4ZZI_HtoD_PSEUDO = 1183 + + SDOT_VG4_M4ZZ_BtoS_PSEUDO = 1184 + + SDOT_VG4_M4ZZ_HtoD_PSEUDO = 1185 + + SDOT_VG4_M4ZZ_HtoS_PSEUDO = 1186 + + SEH_AddFP = 1187 + + SEH_AllocZ = 1188 + + SEH_EpilogEnd = 1189 + + SEH_EpilogStart = 1190 + + SEH_Nop = 1191 + + SEH_PACSignLR = 1192 + + SEH_PrologEnd = 1193 + + SEH_SaveAnyRegI = 1194 + + SEH_SaveAnyRegIP = 1195 + + SEH_SaveAnyRegQP = 1196 + + SEH_SaveAnyRegQPX = 1197 + + SEH_SaveFPLR = 1198 + + SEH_SaveFPLR_X = 1199 + + SEH_SaveFReg = 1200 + + SEH_SaveFRegP = 1201 + + SEH_SaveFRegP_X = 1202 + + SEH_SaveFReg_X = 1203 + + SEH_SavePReg = 1204 + + SEH_SaveReg = 1205 + + SEH_SaveRegP = 1206 + + SEH_SaveRegP_X = 1207 + + SEH_SaveReg_X = 1208 + + SEH_SaveZReg = 1209 + + SEH_SetFP = 1210 + + SEH_StackAlloc = 1211 + + SHSUB_ZPZZ_B_UNDEF = 1212 + + SHSUB_ZPZZ_D_UNDEF = 1213 + + SHSUB_ZPZZ_H_UNDEF = 1214 + + SHSUB_ZPZZ_S_UNDEF = 1215 + + SMAX_ZPZZ_B_UNDEF = 1216 + + SMAX_ZPZZ_D_UNDEF = 1217 + + SMAX_ZPZZ_H_UNDEF = 1218 + + SMAX_ZPZZ_S_UNDEF = 1219 + + SMEStateAllocPseudo = 1220 + + SMIN_ZPZZ_B_UNDEF = 1221 + + SMIN_ZPZZ_D_UNDEF = 1222 + + SMIN_ZPZZ_H_UNDEF = 1223 + + SMIN_ZPZZ_S_UNDEF = 1224 + + SMLALL_MZZI_BtoS_PSEUDO = 1225 + + SMLALL_MZZI_HtoD_PSEUDO = 1226 + + SMLALL_MZZ_BtoS_PSEUDO = 1227 + + SMLALL_MZZ_HtoD_PSEUDO = 1228 + + SMLALL_VG2_M2Z2Z_BtoS_PSEUDO = 1229 + + SMLALL_VG2_M2Z2Z_HtoD_PSEUDO = 1230 + + SMLALL_VG2_M2ZZI_BtoS_PSEUDO = 1231 + + SMLALL_VG2_M2ZZI_HtoD_PSEUDO = 1232 + + SMLALL_VG2_M2ZZ_BtoS_PSEUDO = 1233 + + SMLALL_VG2_M2ZZ_HtoD_PSEUDO = 1234 + + SMLALL_VG4_M4Z4Z_BtoS_PSEUDO = 1235 + + SMLALL_VG4_M4Z4Z_HtoD_PSEUDO = 1236 + + SMLALL_VG4_M4ZZI_BtoS_PSEUDO = 1237 + + SMLALL_VG4_M4ZZI_HtoD_PSEUDO = 1238 + + SMLALL_VG4_M4ZZ_BtoS_PSEUDO = 1239 + + SMLALL_VG4_M4ZZ_HtoD_PSEUDO = 1240 + + SMLAL_MZZI_HtoS_PSEUDO = 1241 + + SMLAL_MZZ_HtoS_PSEUDO = 1242 + + SMLAL_VG2_M2Z2Z_HtoS_PSEUDO = 1243 + + SMLAL_VG2_M2ZZI_S_PSEUDO = 1244 + + SMLAL_VG2_M2ZZ_HtoS_PSEUDO = 1245 + + SMLAL_VG4_M4Z4Z_HtoS_PSEUDO = 1246 + + SMLAL_VG4_M4ZZI_HtoS_PSEUDO = 1247 + + SMLAL_VG4_M4ZZ_HtoS_PSEUDO = 1248 + + SMLSLL_MZZI_BtoS_PSEUDO = 1249 + + SMLSLL_MZZI_HtoD_PSEUDO = 1250 + + SMLSLL_MZZ_BtoS_PSEUDO = 1251 + + SMLSLL_MZZ_HtoD_PSEUDO = 1252 + + SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO = 1253 + + SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO = 1254 + + SMLSLL_VG2_M2ZZI_BtoS_PSEUDO = 1255 + + SMLSLL_VG2_M2ZZI_HtoD_PSEUDO = 1256 + + SMLSLL_VG2_M2ZZ_BtoS_PSEUDO = 1257 + + SMLSLL_VG2_M2ZZ_HtoD_PSEUDO = 1258 + + SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO = 1259 + + SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO = 1260 + + SMLSLL_VG4_M4ZZI_BtoS_PSEUDO = 1261 + + SMLSLL_VG4_M4ZZI_HtoD_PSEUDO = 1262 + + SMLSLL_VG4_M4ZZ_BtoS_PSEUDO = 1263 + + SMLSLL_VG4_M4ZZ_HtoD_PSEUDO = 1264 + + SMLSL_MZZI_HtoS_PSEUDO = 1265 + + SMLSL_MZZ_HtoS_PSEUDO = 1266 + + SMLSL_VG2_M2Z2Z_HtoS_PSEUDO = 1267 + + SMLSL_VG2_M2ZZI_S_PSEUDO = 1268 + + SMLSL_VG2_M2ZZ_HtoS_PSEUDO = 1269 + + SMLSL_VG4_M4Z4Z_HtoS_PSEUDO = 1270 + + SMLSL_VG4_M4ZZI_HtoS_PSEUDO = 1271 + + SMLSL_VG4_M4ZZ_HtoS_PSEUDO = 1272 + + SMOP4A_M2Z2Z_BToS_PSEUDO = 1273 + + SMOP4A_M2Z2Z_HToS_PSEUDO = 1274 + + SMOP4A_M2Z2Z_HtoD_PSEUDO = 1275 + + SMOP4A_M2ZZ_BToS_PSEUDO = 1276 + + SMOP4A_M2ZZ_HToS_PSEUDO = 1277 + + SMOP4A_M2ZZ_HtoD_PSEUDO = 1278 + + SMOP4A_MZ2Z_BToS_PSEUDO = 1279 + + SMOP4A_MZ2Z_HToS_PSEUDO = 1280 + + SMOP4A_MZ2Z_HtoD_PSEUDO = 1281 + + SMOP4A_MZZ_BToS_PSEUDO = 1282 + + SMOP4A_MZZ_HToS_PSEUDO = 1283 + + SMOP4A_MZZ_HtoD_PSEUDO = 1284 + + SMOP4S_M2Z2Z_BToS_PSEUDO = 1285 + + SMOP4S_M2Z2Z_HToS_PSEUDO = 1286 + + SMOP4S_M2Z2Z_HtoD_PSEUDO = 1287 + + SMOP4S_M2ZZ_BToS_PSEUDO = 1288 + + SMOP4S_M2ZZ_HToS_PSEUDO = 1289 + + SMOP4S_M2ZZ_HtoD_PSEUDO = 1290 + + SMOP4S_MZ2Z_BToS_PSEUDO = 1291 + + SMOP4S_MZ2Z_HToS_PSEUDO = 1292 + + SMOP4S_MZ2Z_HtoD_PSEUDO = 1293 + + SMOP4S_MZZ_BToS_PSEUDO = 1294 + + SMOP4S_MZZ_HToS_PSEUDO = 1295 + + SMOP4S_MZZ_HtoD_PSEUDO = 1296 + + SMOPA_MPPZZ_D_PSEUDO = 1297 + + SMOPA_MPPZZ_HtoS_PSEUDO = 1298 + + SMOPA_MPPZZ_S_PSEUDO = 1299 + + SMOPS_MPPZZ_D_PSEUDO = 1300 + + SMOPS_MPPZZ_HtoS_PSEUDO = 1301 + + SMOPS_MPPZZ_S_PSEUDO = 1302 + + SMULH_ZPZZ_B_UNDEF = 1303 + + SMULH_ZPZZ_D_UNDEF = 1304 + + SMULH_ZPZZ_H_UNDEF = 1305 + + SMULH_ZPZZ_S_UNDEF = 1306 + + SPACE = 1307 + + SQABS_ZPmZ_B_UNDEF = 1308 + + SQABS_ZPmZ_D_UNDEF = 1309 + + SQABS_ZPmZ_H_UNDEF = 1310 + + SQABS_ZPmZ_S_UNDEF = 1311 + + SQNEG_ZPmZ_B_UNDEF = 1312 + + SQNEG_ZPmZ_D_UNDEF = 1313 + + SQNEG_ZPmZ_H_UNDEF = 1314 + + SQNEG_ZPmZ_S_UNDEF = 1315 + + SQRSHL_ZPZZ_B_UNDEF = 1316 + + SQRSHL_ZPZZ_D_UNDEF = 1317 + + SQRSHL_ZPZZ_H_UNDEF = 1318 + + SQRSHL_ZPZZ_S_UNDEF = 1319 + + SQSHLU_ZPZI_B_ZERO = 1320 + + SQSHLU_ZPZI_D_ZERO = 1321 + + SQSHLU_ZPZI_H_ZERO = 1322 + + SQSHLU_ZPZI_S_ZERO = 1323 + + SQSHL_ZPZI_B_UNDEF = 1324 + + SQSHL_ZPZI_B_ZERO = 1325 + + SQSHL_ZPZI_D_UNDEF = 1326 + + SQSHL_ZPZI_D_ZERO = 1327 + + SQSHL_ZPZI_H_UNDEF = 1328 + + SQSHL_ZPZI_H_ZERO = 1329 + + SQSHL_ZPZI_S_UNDEF = 1330 + + SQSHL_ZPZI_S_ZERO = 1331 + + SQSHL_ZPZZ_B_UNDEF = 1332 + + SQSHL_ZPZZ_D_UNDEF = 1333 + + SQSHL_ZPZZ_H_UNDEF = 1334 + + SQSHL_ZPZZ_S_UNDEF = 1335 + + SRSHL_ZPZZ_B_UNDEF = 1336 + + SRSHL_ZPZZ_D_UNDEF = 1337 + + SRSHL_ZPZZ_H_UNDEF = 1338 + + SRSHL_ZPZZ_S_UNDEF = 1339 + + SRSHR_ZPZI_B_ZERO = 1340 + + SRSHR_ZPZI_D_ZERO = 1341 + + SRSHR_ZPZI_H_ZERO = 1342 + + SRSHR_ZPZI_S_ZERO = 1343 + + STGloop = 1344 + + STGloop_wback = 1345 + + STMOPA_M2ZZZI_BtoS_PSEUDO = 1346 + + STMOPA_M2ZZZI_HtoS_PSEUDO = 1347 + + STR_PPXI = 1348 + + STR_TX_PSEUDO = 1349 + + STR_ZZXI = 1350 + + STR_ZZXI_STRIDED_CONTIGUOUS = 1351 + + STR_ZZZXI = 1352 + + STR_ZZZZXI = 1353 + + STR_ZZZZXI_STRIDED_CONTIGUOUS = 1354 + + STZGloop = 1355 + + STZGloop_wback = 1356 + + SUBR_ZPZZ_B_ZERO = 1357 + + SUBR_ZPZZ_D_ZERO = 1358 + + SUBR_ZPZZ_H_ZERO = 1359 + + SUBR_ZPZZ_S_ZERO = 1360 + + SUBSWrr = 1361 + + SUBSXrr = 1362 + + SUBWrr = 1363 + + SUBXrr = 1364 + + SUB_VG2_M2Z2Z_D_PSEUDO = 1365 + + SUB_VG2_M2Z2Z_S_PSEUDO = 1366 + + SUB_VG2_M2ZZ_D_PSEUDO = 1367 + + SUB_VG2_M2ZZ_S_PSEUDO = 1368 + + SUB_VG2_M2Z_D_PSEUDO = 1369 + + SUB_VG2_M2Z_S_PSEUDO = 1370 + + SUB_VG4_M4Z4Z_D_PSEUDO = 1371 + + SUB_VG4_M4Z4Z_S_PSEUDO = 1372 + + SUB_VG4_M4ZZ_D_PSEUDO = 1373 + + SUB_VG4_M4ZZ_S_PSEUDO = 1374 + + SUB_VG4_M4Z_D_PSEUDO = 1375 + + SUB_VG4_M4Z_S_PSEUDO = 1376 + + SUB_ZPZZ_B_ZERO = 1377 + + SUB_ZPZZ_D_ZERO = 1378 + + SUB_ZPZZ_H_ZERO = 1379 + + SUB_ZPZZ_S_ZERO = 1380 + + SUDOT_VG2_M2ZZI_BToS_PSEUDO = 1381 + + SUDOT_VG2_M2ZZ_BToS_PSEUDO = 1382 + + SUDOT_VG4_M4ZZI_BToS_PSEUDO = 1383 + + SUDOT_VG4_M4ZZ_BToS_PSEUDO = 1384 + + SUMLALL_MZZI_BtoS_PSEUDO = 1385 + + SUMLALL_VG2_M2ZZI_BtoS_PSEUDO = 1386 + + SUMLALL_VG2_M2ZZ_BtoS_PSEUDO = 1387 + + SUMLALL_VG4_M4ZZI_BtoS_PSEUDO = 1388 + + SUMLALL_VG4_M4ZZ_BtoS_PSEUDO = 1389 + + SUMOP4A_M2Z2Z_BToS_PSEUDO = 1390 + + SUMOP4A_M2Z2Z_HtoD_PSEUDO = 1391 + + SUMOP4A_M2ZZ_BToS_PSEUDO = 1392 + + SUMOP4A_M2ZZ_HtoD_PSEUDO = 1393 + + SUMOP4A_MZ2Z_BToS_PSEUDO = 1394 + + SUMOP4A_MZ2Z_HtoD_PSEUDO = 1395 + + SUMOP4A_MZZ_BToS_PSEUDO = 1396 + + SUMOP4A_MZZ_HtoD_PSEUDO = 1397 + + SUMOP4S_M2Z2Z_BToS_PSEUDO = 1398 + + SUMOP4S_M2Z2Z_HtoD_PSEUDO = 1399 + + SUMOP4S_M2ZZ_BToS_PSEUDO = 1400 + + SUMOP4S_M2ZZ_HtoD_PSEUDO = 1401 + + SUMOP4S_MZ2Z_BToS_PSEUDO = 1402 + + SUMOP4S_MZ2Z_HtoD_PSEUDO = 1403 + + SUMOP4S_MZZ_BToS_PSEUDO = 1404 + + SUMOP4S_MZZ_HtoD_PSEUDO = 1405 + + SUMOPA_MPPZZ_D_PSEUDO = 1406 + + SUMOPA_MPPZZ_S_PSEUDO = 1407 + + SUMOPS_MPPZZ_D_PSEUDO = 1408 + + SUMOPS_MPPZZ_S_PSEUDO = 1409 + + SUTMOPA_M2ZZZI_BtoS_PSEUDO = 1410 + + SUVDOT_VG4_M4ZZI_BToS_PSEUDO = 1411 + + SVDOT_VG2_M2ZZI_HtoS_PSEUDO = 1412 + + SVDOT_VG4_M4ZZI_BtoS_PSEUDO = 1413 + + SVDOT_VG4_M4ZZI_HtoD_PSEUDO = 1414 + + SXTB_ZPmZ_D_UNDEF = 1415 + + SXTB_ZPmZ_H_UNDEF = 1416 + + SXTB_ZPmZ_S_UNDEF = 1417 + + SXTH_ZPmZ_D_UNDEF = 1418 + + SXTH_ZPmZ_S_UNDEF = 1419 + + SXTW_ZPmZ_D_UNDEF = 1420 + + SpeculationBarrierISBDSBEndBB = 1421 + + SpeculationBarrierSBEndBB = 1422 + + SpeculationSafeValueW = 1423 + + SpeculationSafeValueX = 1424 + + StoreSwiftAsyncContext = 1425 + + TAGPstack = 1426 + + TCRETURNdi = 1427 + + TCRETURNri = 1428 + + TCRETURNriALL = 1429 + + TCRETURNrinotx16 = 1430 + + TCRETURNrix16x17 = 1431 + + TCRETURNrix17 = 1432 + + TLSDESCCALL = 1433 + + TLSDESC_AUTH_CALLSEQ = 1434 + + TLSDESC_CALLSEQ = 1435 + + UABD_ZPZZ_B_UNDEF = 1436 + + UABD_ZPZZ_D_UNDEF = 1437 + + UABD_ZPZZ_H_UNDEF = 1438 + + UABD_ZPZZ_S_UNDEF = 1439 + + UCVTF_ZPmZ_DtoD_UNDEF = 1440 + + UCVTF_ZPmZ_DtoH_UNDEF = 1441 + + UCVTF_ZPmZ_DtoS_UNDEF = 1442 + + UCVTF_ZPmZ_HtoH_UNDEF = 1443 + + UCVTF_ZPmZ_StoD_UNDEF = 1444 + + UCVTF_ZPmZ_StoH_UNDEF = 1445 + + UCVTF_ZPmZ_StoS_UNDEF = 1446 + + UDIV_ZPZZ_D_UNDEF = 1447 + + UDIV_ZPZZ_S_UNDEF = 1448 + + UDOT_VG2_M2Z2Z_BtoS_PSEUDO = 1449 + + UDOT_VG2_M2Z2Z_HtoD_PSEUDO = 1450 + + UDOT_VG2_M2Z2Z_HtoS_PSEUDO = 1451 + + UDOT_VG2_M2ZZI_BToS_PSEUDO = 1452 + + UDOT_VG2_M2ZZI_HToS_PSEUDO = 1453 + + UDOT_VG2_M2ZZI_HtoD_PSEUDO = 1454 + + UDOT_VG2_M2ZZ_BtoS_PSEUDO = 1455 + + UDOT_VG2_M2ZZ_HtoD_PSEUDO = 1456 + + UDOT_VG2_M2ZZ_HtoS_PSEUDO = 1457 + + UDOT_VG4_M4Z4Z_BtoS_PSEUDO = 1458 + + UDOT_VG4_M4Z4Z_HtoD_PSEUDO = 1459 + + UDOT_VG4_M4Z4Z_HtoS_PSEUDO = 1460 + + UDOT_VG4_M4ZZI_BtoS_PSEUDO = 1461 + + UDOT_VG4_M4ZZI_HToS_PSEUDO = 1462 + + UDOT_VG4_M4ZZI_HtoD_PSEUDO = 1463 + + UDOT_VG4_M4ZZ_BtoS_PSEUDO = 1464 + + UDOT_VG4_M4ZZ_HtoD_PSEUDO = 1465 + + UDOT_VG4_M4ZZ_HtoS_PSEUDO = 1466 + + UHSUB_ZPZZ_B_UNDEF = 1467 + + UHSUB_ZPZZ_D_UNDEF = 1468 + + UHSUB_ZPZZ_H_UNDEF = 1469 + + UHSUB_ZPZZ_S_UNDEF = 1470 + + UMAX_ZPZZ_B_UNDEF = 1471 + + UMAX_ZPZZ_D_UNDEF = 1472 + + UMAX_ZPZZ_H_UNDEF = 1473 + + UMAX_ZPZZ_S_UNDEF = 1474 + + UMIN_ZPZZ_B_UNDEF = 1475 + + UMIN_ZPZZ_D_UNDEF = 1476 + + UMIN_ZPZZ_H_UNDEF = 1477 + + UMIN_ZPZZ_S_UNDEF = 1478 + + UMLALL_MZZI_BtoS_PSEUDO = 1479 + + UMLALL_MZZI_HtoD_PSEUDO = 1480 + + UMLALL_MZZ_BtoS_PSEUDO = 1481 + + UMLALL_MZZ_HtoD_PSEUDO = 1482 + + UMLALL_VG2_M2Z2Z_BtoS_PSEUDO = 1483 + + UMLALL_VG2_M2Z2Z_HtoD_PSEUDO = 1484 + + UMLALL_VG2_M2ZZI_BtoS_PSEUDO = 1485 + + UMLALL_VG2_M2ZZI_HtoD_PSEUDO = 1486 + + UMLALL_VG2_M2ZZ_BtoS_PSEUDO = 1487 + + UMLALL_VG2_M2ZZ_HtoD_PSEUDO = 1488 + + UMLALL_VG4_M4Z4Z_BtoS_PSEUDO = 1489 + + UMLALL_VG4_M4Z4Z_HtoD_PSEUDO = 1490 + + UMLALL_VG4_M4ZZI_BtoS_PSEUDO = 1491 + + UMLALL_VG4_M4ZZI_HtoD_PSEUDO = 1492 + + UMLALL_VG4_M4ZZ_BtoS_PSEUDO = 1493 + + UMLALL_VG4_M4ZZ_HtoD_PSEUDO = 1494 + + UMLAL_MZZI_HtoS_PSEUDO = 1495 + + UMLAL_MZZ_HtoS_PSEUDO = 1496 + + UMLAL_VG2_M2Z2Z_HtoS_PSEUDO = 1497 + + UMLAL_VG2_M2ZZI_S_PSEUDO = 1498 + + UMLAL_VG2_M2ZZ_HtoS_PSEUDO = 1499 + + UMLAL_VG4_M4Z4Z_HtoS_PSEUDO = 1500 + + UMLAL_VG4_M4ZZI_HtoS_PSEUDO = 1501 + + UMLAL_VG4_M4ZZ_HtoS_PSEUDO = 1502 + + UMLSLL_MZZI_BtoS_PSEUDO = 1503 + + UMLSLL_MZZI_HtoD_PSEUDO = 1504 + + UMLSLL_MZZ_BtoS_PSEUDO = 1505 + + UMLSLL_MZZ_HtoD_PSEUDO = 1506 + + UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO = 1507 + + UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO = 1508 + + UMLSLL_VG2_M2ZZI_BtoS_PSEUDO = 1509 + + UMLSLL_VG2_M2ZZI_HtoD_PSEUDO = 1510 + + UMLSLL_VG2_M2ZZ_BtoS_PSEUDO = 1511 + + UMLSLL_VG2_M2ZZ_HtoD_PSEUDO = 1512 + + UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO = 1513 + + UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO = 1514 + + UMLSLL_VG4_M4ZZI_BtoS_PSEUDO = 1515 + + UMLSLL_VG4_M4ZZI_HtoD_PSEUDO = 1516 + + UMLSLL_VG4_M4ZZ_BtoS_PSEUDO = 1517 + + UMLSLL_VG4_M4ZZ_HtoD_PSEUDO = 1518 + + UMLSL_MZZI_HtoS_PSEUDO = 1519 + + UMLSL_MZZ_HtoS_PSEUDO = 1520 + + UMLSL_VG2_M2Z2Z_HtoS_PSEUDO = 1521 + + UMLSL_VG2_M2ZZI_S_PSEUDO = 1522 + + UMLSL_VG2_M2ZZ_HtoS_PSEUDO = 1523 + + UMLSL_VG4_M4Z4Z_HtoS_PSEUDO = 1524 + + UMLSL_VG4_M4ZZI_HtoS_PSEUDO = 1525 + + UMLSL_VG4_M4ZZ_HtoS_PSEUDO = 1526 + + UMOP4A_M2Z2Z_BToS_PSEUDO = 1527 + + UMOP4A_M2Z2Z_HToS_PSEUDO = 1528 + + UMOP4A_M2Z2Z_HtoD_PSEUDO = 1529 + + UMOP4A_M2ZZ_BToS_PSEUDO = 1530 + + UMOP4A_M2ZZ_HToS_PSEUDO = 1531 + + UMOP4A_M2ZZ_HtoD_PSEUDO = 1532 + + UMOP4A_MZ2Z_BToS_PSEUDO = 1533 + + UMOP4A_MZ2Z_HToS_PSEUDO = 1534 + + UMOP4A_MZ2Z_HtoD_PSEUDO = 1535 + + UMOP4A_MZZ_BToS_PSEUDO = 1536 + + UMOP4A_MZZ_HToS_PSEUDO = 1537 + + UMOP4A_MZZ_HtoD_PSEUDO = 1538 + + UMOP4S_M2Z2Z_BToS_PSEUDO = 1539 + + UMOP4S_M2Z2Z_HToS_PSEUDO = 1540 + + UMOP4S_M2Z2Z_HtoD_PSEUDO = 1541 + + UMOP4S_M2ZZ_BToS_PSEUDO = 1542 + + UMOP4S_M2ZZ_HToS_PSEUDO = 1543 + + UMOP4S_M2ZZ_HtoD_PSEUDO = 1544 + + UMOP4S_MZ2Z_BToS_PSEUDO = 1545 + + UMOP4S_MZ2Z_HToS_PSEUDO = 1546 + + UMOP4S_MZ2Z_HtoD_PSEUDO = 1547 + + UMOP4S_MZZ_BToS_PSEUDO = 1548 + + UMOP4S_MZZ_HToS_PSEUDO = 1549 + + UMOP4S_MZZ_HtoD_PSEUDO = 1550 + + UMOPA_MPPZZ_D_PSEUDO = 1551 + + UMOPA_MPPZZ_HtoS_PSEUDO = 1552 + + UMOPA_MPPZZ_S_PSEUDO = 1553 + + UMOPS_MPPZZ_D_PSEUDO = 1554 + + UMOPS_MPPZZ_HtoS_PSEUDO = 1555 + + UMOPS_MPPZZ_S_PSEUDO = 1556 + + UMULH_ZPZZ_B_UNDEF = 1557 + + UMULH_ZPZZ_D_UNDEF = 1558 + + UMULH_ZPZZ_H_UNDEF = 1559 + + UMULH_ZPZZ_S_UNDEF = 1560 + + UQRSHL_ZPZZ_B_UNDEF = 1561 + + UQRSHL_ZPZZ_D_UNDEF = 1562 + + UQRSHL_ZPZZ_H_UNDEF = 1563 + + UQRSHL_ZPZZ_S_UNDEF = 1564 + + UQSHL_ZPZI_B_UNDEF = 1565 + + UQSHL_ZPZI_B_ZERO = 1566 + + UQSHL_ZPZI_D_UNDEF = 1567 + + UQSHL_ZPZI_D_ZERO = 1568 + + UQSHL_ZPZI_H_UNDEF = 1569 + + UQSHL_ZPZI_H_ZERO = 1570 + + UQSHL_ZPZI_S_UNDEF = 1571 + + UQSHL_ZPZI_S_ZERO = 1572 + + UQSHL_ZPZZ_B_UNDEF = 1573 + + UQSHL_ZPZZ_D_UNDEF = 1574 + + UQSHL_ZPZZ_H_UNDEF = 1575 + + UQSHL_ZPZZ_S_UNDEF = 1576 + + URECPE_ZPmZ_S_UNDEF = 1577 + + URSHL_ZPZZ_B_UNDEF = 1578 + + URSHL_ZPZZ_D_UNDEF = 1579 + + URSHL_ZPZZ_H_UNDEF = 1580 + + URSHL_ZPZZ_S_UNDEF = 1581 + + URSHR_ZPZI_B_ZERO = 1582 + + URSHR_ZPZI_D_ZERO = 1583 + + URSHR_ZPZI_H_ZERO = 1584 + + URSHR_ZPZI_S_ZERO = 1585 + + URSQRTE_ZPmZ_S_UNDEF = 1586 + + USDOT_VG2_M2Z2Z_BToS_PSEUDO = 1587 + + USDOT_VG2_M2ZZI_BToS_PSEUDO = 1588 + + USDOT_VG2_M2ZZ_BToS_PSEUDO = 1589 + + USDOT_VG4_M4Z4Z_BToS_PSEUDO = 1590 + + USDOT_VG4_M4ZZI_BToS_PSEUDO = 1591 + + USDOT_VG4_M4ZZ_BToS_PSEUDO = 1592 + + USMLALL_MZZI_BtoS_PSEUDO = 1593 + + USMLALL_MZZ_BtoS_PSEUDO = 1594 + + USMLALL_VG2_M2Z2Z_BtoS_PSEUDO = 1595 + + USMLALL_VG2_M2ZZI_BtoS_PSEUDO = 1596 + + USMLALL_VG2_M2ZZ_BtoS_PSEUDO = 1597 + + USMLALL_VG4_M4Z4Z_BtoS_PSEUDO = 1598 + + USMLALL_VG4_M4ZZI_BtoS_PSEUDO = 1599 + + USMLALL_VG4_M4ZZ_BtoS_PSEUDO = 1600 + + USMOP4A_M2Z2Z_BToS_PSEUDO = 1601 + + USMOP4A_M2Z2Z_HtoD_PSEUDO = 1602 + + USMOP4A_M2ZZ_BToS_PSEUDO = 1603 + + USMOP4A_M2ZZ_HtoD_PSEUDO = 1604 + + USMOP4A_MZ2Z_BToS_PSEUDO = 1605 + + USMOP4A_MZ2Z_HtoD_PSEUDO = 1606 + + USMOP4A_MZZ_BToS_PSEUDO = 1607 + + USMOP4A_MZZ_HtoD_PSEUDO = 1608 + + USMOP4S_M2Z2Z_BToS_PSEUDO = 1609 + + USMOP4S_M2Z2Z_HtoD_PSEUDO = 1610 + + USMOP4S_M2ZZ_BToS_PSEUDO = 1611 + + USMOP4S_M2ZZ_HtoD_PSEUDO = 1612 + + USMOP4S_MZ2Z_BToS_PSEUDO = 1613 + + USMOP4S_MZ2Z_HtoD_PSEUDO = 1614 + + USMOP4S_MZZ_BToS_PSEUDO = 1615 + + USMOP4S_MZZ_HtoD_PSEUDO = 1616 + + USMOPA_MPPZZ_D_PSEUDO = 1617 + + USMOPA_MPPZZ_S_PSEUDO = 1618 + + USMOPS_MPPZZ_D_PSEUDO = 1619 + + USMOPS_MPPZZ_S_PSEUDO = 1620 + + USTMOPA_M2ZZZI_BtoS_PSEUDO = 1621 + + USVDOT_VG4_M4ZZI_BToS_PSEUDO = 1622 + + UTMOPA_M2ZZZI_BtoS_PSEUDO = 1623 + + UTMOPA_M2ZZZI_HtoS_PSEUDO = 1624 + + UVDOT_VG2_M2ZZI_HtoS_PSEUDO = 1625 + + UVDOT_VG4_M4ZZI_BtoS_PSEUDO = 1626 + + UVDOT_VG4_M4ZZI_HtoD_PSEUDO = 1627 + + UXTB_ZPmZ_D_UNDEF = 1628 + + UXTB_ZPmZ_H_UNDEF = 1629 + + UXTB_ZPmZ_S_UNDEF = 1630 + + UXTH_ZPmZ_D_UNDEF = 1631 + + UXTH_ZPmZ_S_UNDEF = 1632 + + UXTW_ZPmZ_D_UNDEF = 1633 + + ZERO_MXI_2Z_PSEUDO = 1634 + + ZERO_MXI_4Z_PSEUDO = 1635 + + ZERO_MXI_VG2_2Z_PSEUDO = 1636 + + ZERO_MXI_VG2_4Z_PSEUDO = 1637 + + ZERO_MXI_VG2_Z_PSEUDO = 1638 + + ZERO_MXI_VG4_2Z_PSEUDO = 1639 + + ZERO_MXI_VG4_4Z_PSEUDO = 1640 + + ZERO_MXI_VG4_Z_PSEUDO = 1641 + + ZERO_M_PSEUDO = 1642 + + ZERO_T_PSEUDO = 1643 + + ABSWr = 1644 + + ABSXr = 1645 + + ABS_ZPmZ_B = 1646 + + ABS_ZPmZ_D = 1647 + + ABS_ZPmZ_H = 1648 + + ABS_ZPmZ_S = 1649 + + ABS_ZPzZ_B = 1650 + + ABS_ZPzZ_D = 1651 + + ABS_ZPzZ_H = 1652 + + ABS_ZPzZ_S = 1653 + + ABSv16i8 = 1654 + + ABSv1i64 = 1655 + + ABSv2i32 = 1656 + + ABSv2i64 = 1657 + + ABSv4i16 = 1658 + + ABSv4i32 = 1659 + + ABSv8i16 = 1660 + + ABSv8i8 = 1661 + + ADCLB_ZZZ_D = 1662 + + ADCLB_ZZZ_S = 1663 + + ADCLT_ZZZ_D = 1664 + + ADCLT_ZZZ_S = 1665 + + ADCSWr = 1666 + + ADCSXr = 1667 + + ADCWr = 1668 + + ADCXr = 1669 + + ADDG = 1670 + + ADDHA_MPPZ_D = 1671 + + ADDHA_MPPZ_S = 1672 + + ADDHNB_ZZZ_B = 1673 + + ADDHNB_ZZZ_H = 1674 + + ADDHNB_ZZZ_S = 1675 + + ADDHNT_ZZZ_B = 1676 + + ADDHNT_ZZZ_H = 1677 + + ADDHNT_ZZZ_S = 1678 + + ADDHNv2i64_v2i32 = 1679 + + ADDHNv2i64_v4i32 = 1680 + + ADDHNv4i32_v4i16 = 1681 + + ADDHNv4i32_v8i16 = 1682 + + ADDHNv8i16_v16i8 = 1683 + + ADDHNv8i16_v8i8 = 1684 + + ADDPL_XXI = 1685 + + ADDPT_shift = 1686 + + ADDP_ZPmZ_B = 1687 + + ADDP_ZPmZ_D = 1688 + + ADDP_ZPmZ_H = 1689 + + ADDP_ZPmZ_S = 1690 + + ADDPv16i8 = 1691 + + ADDPv2i32 = 1692 + + ADDPv2i64 = 1693 + + ADDPv2i64p = 1694 + + ADDPv4i16 = 1695 + + ADDPv4i32 = 1696 + + ADDPv8i16 = 1697 + + ADDPv8i8 = 1698 + + ADDQP_ZZZ_B = 1699 + + ADDQP_ZZZ_D = 1700 + + ADDQP_ZZZ_H = 1701 + + ADDQP_ZZZ_S = 1702 + + ADDQV_VPZ_B = 1703 + + ADDQV_VPZ_D = 1704 + + ADDQV_VPZ_H = 1705 + + ADDQV_VPZ_S = 1706 + + ADDSPL_XXI = 1707 + + ADDSUBP_ZZZ_B = 1708 + + ADDSUBP_ZZZ_D = 1709 + + ADDSUBP_ZZZ_H = 1710 + + ADDSUBP_ZZZ_S = 1711 + + ADDSVL_XXI = 1712 + + ADDSWri = 1713 + + ADDSWrs = 1714 + + ADDSWrx = 1715 + + ADDSXri = 1716 + + ADDSXrs = 1717 + + ADDSXrx = 1718 + + ADDSXrx64 = 1719 + + ADDVA_MPPZ_D = 1720 + + ADDVA_MPPZ_S = 1721 + + ADDVL_XXI = 1722 + + ADDVv16i8v = 1723 + + ADDVv4i16v = 1724 + + ADDVv4i32v = 1725 + + ADDVv8i16v = 1726 + + ADDVv8i8v = 1727 + + ADDWri = 1728 + + ADDWrs = 1729 + + ADDWrx = 1730 + + ADDXri = 1731 + + ADDXrs = 1732 + + ADDXrx = 1733 + + ADDXrx64 = 1734 + + ADD_VG2_2ZZ_B = 1735 + + ADD_VG2_2ZZ_D = 1736 + + ADD_VG2_2ZZ_H = 1737 + + ADD_VG2_2ZZ_S = 1738 + + ADD_VG2_M2Z2Z_D = 1739 + + ADD_VG2_M2Z2Z_S = 1740 + + ADD_VG2_M2ZZ_D = 1741 + + ADD_VG2_M2ZZ_S = 1742 + + ADD_VG2_M2Z_D = 1743 + + ADD_VG2_M2Z_S = 1744 + + ADD_VG4_4ZZ_B = 1745 + + ADD_VG4_4ZZ_D = 1746 + + ADD_VG4_4ZZ_H = 1747 + + ADD_VG4_4ZZ_S = 1748 + + ADD_VG4_M4Z4Z_D = 1749 + + ADD_VG4_M4Z4Z_S = 1750 + + ADD_VG4_M4ZZ_D = 1751 + + ADD_VG4_M4ZZ_S = 1752 + + ADD_VG4_M4Z_D = 1753 + + ADD_VG4_M4Z_S = 1754 + + ADD_ZI_B = 1755 + + ADD_ZI_D = 1756 + + ADD_ZI_H = 1757 + + ADD_ZI_S = 1758 + + ADD_ZPmZ_B = 1759 + + ADD_ZPmZ_CPA = 1760 + + ADD_ZPmZ_D = 1761 + + ADD_ZPmZ_H = 1762 + + ADD_ZPmZ_S = 1763 + + ADD_ZZZ_B = 1764 + + ADD_ZZZ_CPA = 1765 + + ADD_ZZZ_D = 1766 + + ADD_ZZZ_H = 1767 + + ADD_ZZZ_S = 1768 + + ADDv16i8 = 1769 + + ADDv1i64 = 1770 + + ADDv2i32 = 1771 + + ADDv2i64 = 1772 + + ADDv4i16 = 1773 + + ADDv4i32 = 1774 + + ADDv8i16 = 1775 + + ADDv8i8 = 1776 + + ADR = 1777 + + ADRP = 1778 + + ADR_LSL_ZZZ_D_0 = 1779 + + ADR_LSL_ZZZ_D_1 = 1780 + + ADR_LSL_ZZZ_D_2 = 1781 + + ADR_LSL_ZZZ_D_3 = 1782 + + ADR_LSL_ZZZ_S_0 = 1783 + + ADR_LSL_ZZZ_S_1 = 1784 + + ADR_LSL_ZZZ_S_2 = 1785 + + ADR_LSL_ZZZ_S_3 = 1786 + + ADR_SXTW_ZZZ_D_0 = 1787 + + ADR_SXTW_ZZZ_D_1 = 1788 + + ADR_SXTW_ZZZ_D_2 = 1789 + + ADR_SXTW_ZZZ_D_3 = 1790 + + ADR_UXTW_ZZZ_D_0 = 1791 + + ADR_UXTW_ZZZ_D_1 = 1792 + + ADR_UXTW_ZZZ_D_2 = 1793 + + ADR_UXTW_ZZZ_D_3 = 1794 + + AESDIMC_2ZZI_B = 1795 + + AESDIMC_4ZZI_B = 1796 + + AESD_2ZZI_B = 1797 + + AESD_4ZZI_B = 1798 + + AESD_ZZZ_B = 1799 + + AESDrr = 1800 + + AESEMC_2ZZI_B = 1801 + + AESEMC_4ZZI_B = 1802 + + AESE_2ZZI_B = 1803 + + AESE_4ZZI_B = 1804 + + AESE_ZZZ_B = 1805 + + AESErr = 1806 + + AESIMC_ZZ_B = 1807 + + AESIMCrr = 1808 + + AESMC_ZZ_B = 1809 + + AESMCrr = 1810 + + ANDQV_VPZ_B = 1811 + + ANDQV_VPZ_D = 1812 + + ANDQV_VPZ_H = 1813 + + ANDQV_VPZ_S = 1814 + + ANDSWri = 1815 + + ANDSWrs = 1816 + + ANDSXri = 1817 + + ANDSXrs = 1818 + + ANDS_PPzPP = 1819 + + ANDV_VPZ_B = 1820 + + ANDV_VPZ_D = 1821 + + ANDV_VPZ_H = 1822 + + ANDV_VPZ_S = 1823 + + ANDWri = 1824 + + ANDWrs = 1825 + + ANDXri = 1826 + + ANDXrs = 1827 + + AND_PPzPP = 1828 + + AND_ZI = 1829 + + AND_ZPmZ_B = 1830 + + AND_ZPmZ_D = 1831 + + AND_ZPmZ_H = 1832 + + AND_ZPmZ_S = 1833 + + AND_ZZZ = 1834 + + ANDv16i8 = 1835 + + ANDv8i8 = 1836 + + APAS = 1837 + + ASRD_ZPmI_B = 1838 + + ASRD_ZPmI_D = 1839 + + ASRD_ZPmI_H = 1840 + + ASRD_ZPmI_S = 1841 + + ASRR_ZPmZ_B = 1842 + + ASRR_ZPmZ_D = 1843 + + ASRR_ZPmZ_H = 1844 + + ASRR_ZPmZ_S = 1845 + + ASRVWr = 1846 + + ASRVXr = 1847 + + ASR_WIDE_ZPmZ_B = 1848 + + ASR_WIDE_ZPmZ_H = 1849 + + ASR_WIDE_ZPmZ_S = 1850 + + ASR_WIDE_ZZZ_B = 1851 + + ASR_WIDE_ZZZ_H = 1852 + + ASR_WIDE_ZZZ_S = 1853 + + ASR_ZPmI_B = 1854 + + ASR_ZPmI_D = 1855 + + ASR_ZPmI_H = 1856 + + ASR_ZPmI_S = 1857 + + ASR_ZPmZ_B = 1858 + + ASR_ZPmZ_D = 1859 + + ASR_ZPmZ_H = 1860 + + ASR_ZPmZ_S = 1861 + + ASR_ZZI_B = 1862 + + ASR_ZZI_D = 1863 + + ASR_ZZI_H = 1864 + + ASR_ZZI_S = 1865 + + AUTDA = 1866 + + AUTDB = 1867 + + AUTDZA = 1868 + + AUTDZB = 1869 + + AUTIA = 1870 + + AUTIA1716 = 1871 + + AUTIA171615 = 1872 + + AUTIASP = 1873 + + AUTIASPPCi = 1874 + + AUTIASPPCr = 1875 + + AUTIAZ = 1876 + + AUTIB = 1877 + + AUTIB1716 = 1878 + + AUTIB171615 = 1879 + + AUTIBSP = 1880 + + AUTIBSPPCi = 1881 + + AUTIBSPPCr = 1882 + + AUTIBZ = 1883 + + AUTIZA = 1884 + + AUTIZB = 1885 + + AXFLAG = 1886 + + B = 1887 + + BCAX = 1888 + + BCAX_ZZZZ = 1889 + + BCcc = 1890 + + BDEP_ZZZ_B = 1891 + + BDEP_ZZZ_D = 1892 + + BDEP_ZZZ_H = 1893 + + BDEP_ZZZ_S = 1894 + + BEXT_ZZZ_B = 1895 + + BEXT_ZZZ_D = 1896 + + BEXT_ZZZ_H = 1897 + + BEXT_ZZZ_S = 1898 + + BF16DOTlanev4bf16 = 1899 + + BF16DOTlanev8bf16 = 1900 + + BF1CVTL = 1901 + + BF1CVTL2 = 1902 + + BF1CVTLT_ZZ_BtoH = 1903 + + BF1CVTL_2ZZ_BtoH = 1904 + + BF1CVT_2ZZ_BtoH = 1905 + + BF1CVT_ZZ_BtoH = 1906 + + BF2CVTL = 1907 + + BF2CVTL2 = 1908 + + BF2CVTLT_ZZ_BtoH = 1909 + + BF2CVTL_2ZZ_BtoH = 1910 + + BF2CVT_2ZZ_BtoH = 1911 + + BF2CVT_ZZ_BtoH = 1912 + + BFADD_VG2_M2Z_H = 1913 + + BFADD_VG4_M4Z_H = 1914 + + BFADD_ZPmZZ = 1915 + + BFADD_ZZZ = 1916 + + BFCLAMP_VG2_2ZZZ_H = 1917 + + BFCLAMP_VG4_4ZZZ_H = 1918 + + BFCLAMP_ZZZ = 1919 + + BFCVT = 1920 + + BFCVTN = 1921 + + BFCVTN2 = 1922 + + BFCVTNT_ZPmZ = 1923 + + BFCVTNT_ZPzZ_StoH = 1924 + + BFCVTN_Z2Z_HtoB = 1925 + + BFCVTN_Z2Z_StoH = 1926 + + BFCVT_Z2Z_HtoB = 1927 + + BFCVT_Z2Z_StoH = 1928 + + BFCVT_ZPmZ = 1929 + + BFCVT_ZPzZ_StoH = 1930 + + BFDOT_VG2_M2Z2Z_HtoS = 1931 + + BFDOT_VG2_M2ZZI_HtoS = 1932 + + BFDOT_VG2_M2ZZ_HtoS = 1933 + + BFDOT_VG4_M4Z4Z_HtoS = 1934 + + BFDOT_VG4_M4ZZI_HtoS = 1935 + + BFDOT_VG4_M4ZZ_HtoS = 1936 + + BFDOT_ZZI = 1937 + + BFDOT_ZZZ = 1938 + + BFDOTv4bf16 = 1939 + + BFDOTv8bf16 = 1940 + + BFMAXNM_VG2_2Z2Z_H = 1941 + + BFMAXNM_VG2_2ZZ_H = 1942 + + BFMAXNM_VG4_4Z2Z_H = 1943 + + BFMAXNM_VG4_4ZZ_H = 1944 + + BFMAXNM_ZPmZZ = 1945 + + BFMAX_VG2_2Z2Z_H = 1946 + + BFMAX_VG2_2ZZ_H = 1947 + + BFMAX_VG4_4Z2Z_H = 1948 + + BFMAX_VG4_4ZZ_H = 1949 + + BFMAX_ZPmZZ = 1950 + + BFMINNM_VG2_2Z2Z_H = 1951 + + BFMINNM_VG2_2ZZ_H = 1952 + + BFMINNM_VG4_4Z2Z_H = 1953 + + BFMINNM_VG4_4ZZ_H = 1954 + + BFMINNM_ZPmZZ = 1955 + + BFMIN_VG2_2Z2Z_H = 1956 + + BFMIN_VG2_2ZZ_H = 1957 + + BFMIN_VG4_4Z2Z_H = 1958 + + BFMIN_VG4_4ZZ_H = 1959 + + BFMIN_ZPmZZ = 1960 + + BFMLALB = 1961 + + BFMLALBIdx = 1962 + + BFMLALB_ZZZ = 1963 + + BFMLALB_ZZZI = 1964 + + BFMLALT = 1965 + + BFMLALTIdx = 1966 + + BFMLALT_ZZZ = 1967 + + BFMLALT_ZZZI = 1968 + + BFMLAL_MZZI_HtoS = 1969 + + BFMLAL_MZZ_HtoS = 1970 + + BFMLAL_VG2_M2Z2Z_HtoS = 1971 + + BFMLAL_VG2_M2ZZI_HtoS = 1972 + + BFMLAL_VG2_M2ZZ_HtoS = 1973 + + BFMLAL_VG4_M4Z4Z_HtoS = 1974 + + BFMLAL_VG4_M4ZZI_HtoS = 1975 + + BFMLAL_VG4_M4ZZ_HtoS = 1976 + + BFMLA_VG2_M2Z2Z = 1977 + + BFMLA_VG2_M2ZZ = 1978 + + BFMLA_VG2_M2ZZI = 1979 + + BFMLA_VG4_M4Z4Z = 1980 + + BFMLA_VG4_M4ZZ = 1981 + + BFMLA_VG4_M4ZZI = 1982 + + BFMLA_ZPmZZ = 1983 + + BFMLA_ZZZI = 1984 + + BFMLSLB_ZZZI_S = 1985 + + BFMLSLB_ZZZ_S = 1986 + + BFMLSLT_ZZZI_S = 1987 + + BFMLSLT_ZZZ_S = 1988 + + BFMLSL_MZZI_HtoS = 1989 + + BFMLSL_MZZ_HtoS = 1990 + + BFMLSL_VG2_M2Z2Z_HtoS = 1991 + + BFMLSL_VG2_M2ZZI_HtoS = 1992 + + BFMLSL_VG2_M2ZZ_HtoS = 1993 + + BFMLSL_VG4_M4Z4Z_HtoS = 1994 + + BFMLSL_VG4_M4ZZI_HtoS = 1995 + + BFMLSL_VG4_M4ZZ_HtoS = 1996 + + BFMLS_VG2_M2Z2Z = 1997 + + BFMLS_VG2_M2ZZ = 1998 + + BFMLS_VG2_M2ZZI = 1999 + + BFMLS_VG4_M4Z4Z = 2000 + + BFMLS_VG4_M4ZZ = 2001 + + BFMLS_VG4_M4ZZI = 2002 + + BFMLS_ZPmZZ = 2003 + + BFMLS_ZZZI = 2004 + + BFMMLA = 2005 + + BFMMLA_ZZZ_H = 2006 + + BFMMLA_ZZZ_HtoS = 2007 + + BFMOP4A_M2Z2Z_H = 2008 + + BFMOP4A_M2Z2Z_S = 2009 + + BFMOP4A_M2ZZ_H = 2010 + + BFMOP4A_M2ZZ_S = 2011 + + BFMOP4A_MZ2Z_H = 2012 + + BFMOP4A_MZ2Z_S = 2013 + + BFMOP4A_MZZ_H = 2014 + + BFMOP4A_MZZ_S = 2015 + + BFMOP4S_M2Z2Z_H = 2016 + + BFMOP4S_M2Z2Z_S = 2017 + + BFMOP4S_M2ZZ_H = 2018 + + BFMOP4S_M2ZZ_S = 2019 + + BFMOP4S_MZ2Z_H = 2020 + + BFMOP4S_MZ2Z_S = 2021 + + BFMOP4S_MZZ_H = 2022 + + BFMOP4S_MZZ_S = 2023 + + BFMOPA_MPPZZ = 2024 + + BFMOPA_MPPZZ_H = 2025 + + BFMOPS_MPPZZ = 2026 + + BFMOPS_MPPZZ_H = 2027 + + BFMUL_2Z2Z = 2028 + + BFMUL_2ZZ = 2029 + + BFMUL_4Z4Z = 2030 + + BFMUL_4ZZ = 2031 + + BFMUL_ZPmZZ = 2032 + + BFMUL_ZZZ = 2033 + + BFMUL_ZZZI = 2034 + + BFMWri = 2035 + + BFMXri = 2036 + + BFSCALE_2Z2Z = 2037 + + BFSCALE_2ZZ = 2038 + + BFSCALE_4Z4Z = 2039 + + BFSCALE_4ZZ = 2040 + + BFSCALE_ZPZZ_H = 2041 + + BFSUB_VG2_M2Z_H = 2042 + + BFSUB_VG4_M4Z_H = 2043 + + BFSUB_ZPmZZ = 2044 + + BFSUB_ZZZ = 2045 + + BFTMOPA_M2ZZZI_HtoH = 2046 + + BFTMOPA_M2ZZZI_HtoS = 2047 + + BFVDOT_VG2_M2ZZI_HtoS = 2048 + + BGRP_ZZZ_B = 2049 + + BGRP_ZZZ_D = 2050 + + BGRP_ZZZ_H = 2051 + + BGRP_ZZZ_S = 2052 + + BICSWrs = 2053 + + BICSXrs = 2054 + + BICS_PPzPP = 2055 + + BICWrs = 2056 + + BICXrs = 2057 + + BIC_PPzPP = 2058 + + BIC_ZPmZ_B = 2059 + + BIC_ZPmZ_D = 2060 + + BIC_ZPmZ_H = 2061 + + BIC_ZPmZ_S = 2062 + + BIC_ZZZ = 2063 + + BICv16i8 = 2064 + + BICv2i32 = 2065 + + BICv4i16 = 2066 + + BICv4i32 = 2067 + + BICv8i16 = 2068 + + BICv8i8 = 2069 + + BIFv16i8 = 2070 + + BIFv8i8 = 2071 + + BITv16i8 = 2072 + + BITv8i8 = 2073 + + BL = 2074 + + BLR = 2075 + + BLRAA = 2076 + + BLRAAZ = 2077 + + BLRAB = 2078 + + BLRABZ = 2079 + + BMOPA_MPPZZ_S = 2080 + + BMOPS_MPPZZ_S = 2081 + + BR = 2082 + + BRAA = 2083 + + BRAAZ = 2084 + + BRAB = 2085 + + BRABZ = 2086 + + BRB_IALL = 2087 + + BRB_INJ = 2088 + + BRK = 2089 + + BRKAS_PPzP = 2090 + + BRKA_PPmP = 2091 + + BRKA_PPzP = 2092 + + BRKBS_PPzP = 2093 + + BRKB_PPmP = 2094 + + BRKB_PPzP = 2095 + + BRKNS_PPzP = 2096 + + BRKN_PPzP = 2097 + + BRKPAS_PPzPP = 2098 + + BRKPA_PPzPP = 2099 + + BRKPBS_PPzPP = 2100 + + BRKPB_PPzPP = 2101 + + BSL1N_ZZZZ = 2102 + + BSL2N_ZZZZ = 2103 + + BSL_ZZZZ = 2104 + + BSLv16i8 = 2105 + + BSLv8i8 = 2106 + + Bcc = 2107 + + CADD_ZZI_B = 2108 + + CADD_ZZI_D = 2109 + + CADD_ZZI_H = 2110 + + CADD_ZZI_S = 2111 + + CASAB = 2112 + + CASAH = 2113 + + CASALB = 2114 + + CASALH = 2115 + + CASALTX = 2116 + + CASALW = 2117 + + CASALX = 2118 + + CASATX = 2119 + + CASAW = 2120 + + CASAX = 2121 + + CASB = 2122 + + CASH = 2123 + + CASLB = 2124 + + CASLH = 2125 + + CASLTX = 2126 + + CASLW = 2127 + + CASLX = 2128 + + CASPALTX = 2129 + + CASPALW = 2130 + + CASPALX = 2131 + + CASPATX = 2132 + + CASPAW = 2133 + + CASPAX = 2134 + + CASPLTX = 2135 + + CASPLW = 2136 + + CASPLX = 2137 + + CASPTX = 2138 + + CASPW = 2139 + + CASPX = 2140 + + CASTX = 2141 + + CASW = 2142 + + CASX = 2143 + + CBBEQWrr = 2144 + + CBBGEWrr = 2145 + + CBBGTWrr = 2146 + + CBBHIWrr = 2147 + + CBBHSWrr = 2148 + + CBBNEWrr = 2149 + + CBEQWri = 2150 + + CBEQWrr = 2151 + + CBEQXri = 2152 + + CBEQXrr = 2153 + + CBGEWrr = 2154 + + CBGEXrr = 2155 + + CBGTWri = 2156 + + CBGTWrr = 2157 + + CBGTXri = 2158 + + CBGTXrr = 2159 + + CBHEQWrr = 2160 + + CBHGEWrr = 2161 + + CBHGTWrr = 2162 + + CBHHIWrr = 2163 + + CBHHSWrr = 2164 + + CBHIWri = 2165 + + CBHIWrr = 2166 + + CBHIXri = 2167 + + CBHIXrr = 2168 + + CBHNEWrr = 2169 + + CBHSWrr = 2170 + + CBHSXrr = 2171 + + CBLOWri = 2172 + + CBLOXri = 2173 + + CBLTWri = 2174 + + CBLTXri = 2175 + + CBNEWri = 2176 + + CBNEWrr = 2177 + + CBNEXri = 2178 + + CBNEXrr = 2179 + + CBNZW = 2180 + + CBNZX = 2181 + + CBZW = 2182 + + CBZX = 2183 + + CCMNWi = 2184 + + CCMNWr = 2185 + + CCMNXi = 2186 + + CCMNXr = 2187 + + CCMPWi = 2188 + + CCMPWr = 2189 + + CCMPXi = 2190 + + CCMPXr = 2191 + + CDOT_ZZZI_D = 2192 + + CDOT_ZZZI_S = 2193 + + CDOT_ZZZ_D = 2194 + + CDOT_ZZZ_S = 2195 + + CFINV = 2196 + + CHKFEAT = 2197 + + CLASTA_RPZ_B = 2198 + + CLASTA_RPZ_D = 2199 + + CLASTA_RPZ_H = 2200 + + CLASTA_RPZ_S = 2201 + + CLASTA_VPZ_B = 2202 + + CLASTA_VPZ_D = 2203 + + CLASTA_VPZ_H = 2204 + + CLASTA_VPZ_S = 2205 + + CLASTA_ZPZ_B = 2206 + + CLASTA_ZPZ_D = 2207 + + CLASTA_ZPZ_H = 2208 + + CLASTA_ZPZ_S = 2209 + + CLASTB_RPZ_B = 2210 + + CLASTB_RPZ_D = 2211 + + CLASTB_RPZ_H = 2212 + + CLASTB_RPZ_S = 2213 + + CLASTB_VPZ_B = 2214 + + CLASTB_VPZ_D = 2215 + + CLASTB_VPZ_H = 2216 + + CLASTB_VPZ_S = 2217 + + CLASTB_ZPZ_B = 2218 + + CLASTB_ZPZ_D = 2219 + + CLASTB_ZPZ_H = 2220 + + CLASTB_ZPZ_S = 2221 + + CLREX = 2222 + + CLSWr = 2223 + + CLSXr = 2224 + + CLS_ZPmZ_B = 2225 + + CLS_ZPmZ_D = 2226 + + CLS_ZPmZ_H = 2227 + + CLS_ZPmZ_S = 2228 + + CLS_ZPzZ_B = 2229 + + CLS_ZPzZ_D = 2230 + + CLS_ZPzZ_H = 2231 + + CLS_ZPzZ_S = 2232 + + CLSv16i8 = 2233 + + CLSv2i32 = 2234 + + CLSv4i16 = 2235 + + CLSv4i32 = 2236 + + CLSv8i16 = 2237 + + CLSv8i8 = 2238 + + CLZWr = 2239 + + CLZXr = 2240 + + CLZ_ZPmZ_B = 2241 + + CLZ_ZPmZ_D = 2242 + + CLZ_ZPmZ_H = 2243 + + CLZ_ZPmZ_S = 2244 + + CLZ_ZPzZ_B = 2245 + + CLZ_ZPzZ_D = 2246 + + CLZ_ZPzZ_H = 2247 + + CLZ_ZPzZ_S = 2248 + + CLZv16i8 = 2249 + + CLZv2i32 = 2250 + + CLZv4i16 = 2251 + + CLZv4i32 = 2252 + + CLZv8i16 = 2253 + + CLZv8i8 = 2254 + + CMEQv16i8 = 2255 + + CMEQv16i8rz = 2256 + + CMEQv1i64 = 2257 + + CMEQv1i64rz = 2258 + + CMEQv2i32 = 2259 + + CMEQv2i32rz = 2260 + + CMEQv2i64 = 2261 + + CMEQv2i64rz = 2262 + + CMEQv4i16 = 2263 + + CMEQv4i16rz = 2264 + + CMEQv4i32 = 2265 + + CMEQv4i32rz = 2266 + + CMEQv8i16 = 2267 + + CMEQv8i16rz = 2268 + + CMEQv8i8 = 2269 + + CMEQv8i8rz = 2270 + + CMGEv16i8 = 2271 + + CMGEv16i8rz = 2272 + + CMGEv1i64 = 2273 + + CMGEv1i64rz = 2274 + + CMGEv2i32 = 2275 + + CMGEv2i32rz = 2276 + + CMGEv2i64 = 2277 + + CMGEv2i64rz = 2278 + + CMGEv4i16 = 2279 + + CMGEv4i16rz = 2280 + + CMGEv4i32 = 2281 + + CMGEv4i32rz = 2282 + + CMGEv8i16 = 2283 + + CMGEv8i16rz = 2284 + + CMGEv8i8 = 2285 + + CMGEv8i8rz = 2286 + + CMGTv16i8 = 2287 + + CMGTv16i8rz = 2288 + + CMGTv1i64 = 2289 + + CMGTv1i64rz = 2290 + + CMGTv2i32 = 2291 + + CMGTv2i32rz = 2292 + + CMGTv2i64 = 2293 + + CMGTv2i64rz = 2294 + + CMGTv4i16 = 2295 + + CMGTv4i16rz = 2296 + + CMGTv4i32 = 2297 + + CMGTv4i32rz = 2298 + + CMGTv8i16 = 2299 + + CMGTv8i16rz = 2300 + + CMGTv8i8 = 2301 + + CMGTv8i8rz = 2302 + + CMHIv16i8 = 2303 + + CMHIv1i64 = 2304 + + CMHIv2i32 = 2305 + + CMHIv2i64 = 2306 + + CMHIv4i16 = 2307 + + CMHIv4i32 = 2308 + + CMHIv8i16 = 2309 + + CMHIv8i8 = 2310 + + CMHSv16i8 = 2311 + + CMHSv1i64 = 2312 + + CMHSv2i32 = 2313 + + CMHSv2i64 = 2314 + + CMHSv4i16 = 2315 + + CMHSv4i32 = 2316 + + CMHSv8i16 = 2317 + + CMHSv8i8 = 2318 + + CMLA_ZZZI_H = 2319 + + CMLA_ZZZI_S = 2320 + + CMLA_ZZZ_B = 2321 + + CMLA_ZZZ_D = 2322 + + CMLA_ZZZ_H = 2323 + + CMLA_ZZZ_S = 2324 + + CMLEv16i8rz = 2325 + + CMLEv1i64rz = 2326 + + CMLEv2i32rz = 2327 + + CMLEv2i64rz = 2328 + + CMLEv4i16rz = 2329 + + CMLEv4i32rz = 2330 + + CMLEv8i16rz = 2331 + + CMLEv8i8rz = 2332 + + CMLTv16i8rz = 2333 + + CMLTv1i64rz = 2334 + + CMLTv2i32rz = 2335 + + CMLTv2i64rz = 2336 + + CMLTv4i16rz = 2337 + + CMLTv4i32rz = 2338 + + CMLTv8i16rz = 2339 + + CMLTv8i8rz = 2340 + + CMPEQ_PPzZI_B = 2341 + + CMPEQ_PPzZI_D = 2342 + + CMPEQ_PPzZI_H = 2343 + + CMPEQ_PPzZI_S = 2344 + + CMPEQ_PPzZZ_B = 2345 + + CMPEQ_PPzZZ_D = 2346 + + CMPEQ_PPzZZ_H = 2347 + + CMPEQ_PPzZZ_S = 2348 + + CMPEQ_WIDE_PPzZZ_B = 2349 + + CMPEQ_WIDE_PPzZZ_H = 2350 + + CMPEQ_WIDE_PPzZZ_S = 2351 + + CMPGE_PPzZI_B = 2352 + + CMPGE_PPzZI_D = 2353 + + CMPGE_PPzZI_H = 2354 + + CMPGE_PPzZI_S = 2355 + + CMPGE_PPzZZ_B = 2356 + + CMPGE_PPzZZ_D = 2357 + + CMPGE_PPzZZ_H = 2358 + + CMPGE_PPzZZ_S = 2359 + + CMPGE_WIDE_PPzZZ_B = 2360 + + CMPGE_WIDE_PPzZZ_H = 2361 + + CMPGE_WIDE_PPzZZ_S = 2362 + + CMPGT_PPzZI_B = 2363 + + CMPGT_PPzZI_D = 2364 + + CMPGT_PPzZI_H = 2365 + + CMPGT_PPzZI_S = 2366 + + CMPGT_PPzZZ_B = 2367 + + CMPGT_PPzZZ_D = 2368 + + CMPGT_PPzZZ_H = 2369 + + CMPGT_PPzZZ_S = 2370 + + CMPGT_WIDE_PPzZZ_B = 2371 + + CMPGT_WIDE_PPzZZ_H = 2372 + + CMPGT_WIDE_PPzZZ_S = 2373 + + CMPHI_PPzZI_B = 2374 + + CMPHI_PPzZI_D = 2375 + + CMPHI_PPzZI_H = 2376 + + CMPHI_PPzZI_S = 2377 + + CMPHI_PPzZZ_B = 2378 + + CMPHI_PPzZZ_D = 2379 + + CMPHI_PPzZZ_H = 2380 + + CMPHI_PPzZZ_S = 2381 + + CMPHI_WIDE_PPzZZ_B = 2382 + + CMPHI_WIDE_PPzZZ_H = 2383 + + CMPHI_WIDE_PPzZZ_S = 2384 + + CMPHS_PPzZI_B = 2385 + + CMPHS_PPzZI_D = 2386 + + CMPHS_PPzZI_H = 2387 + + CMPHS_PPzZI_S = 2388 + + CMPHS_PPzZZ_B = 2389 + + CMPHS_PPzZZ_D = 2390 + + CMPHS_PPzZZ_H = 2391 + + CMPHS_PPzZZ_S = 2392 + + CMPHS_WIDE_PPzZZ_B = 2393 + + CMPHS_WIDE_PPzZZ_H = 2394 + + CMPHS_WIDE_PPzZZ_S = 2395 + + CMPLE_PPzZI_B = 2396 + + CMPLE_PPzZI_D = 2397 + + CMPLE_PPzZI_H = 2398 + + CMPLE_PPzZI_S = 2399 + + CMPLE_WIDE_PPzZZ_B = 2400 + + CMPLE_WIDE_PPzZZ_H = 2401 + + CMPLE_WIDE_PPzZZ_S = 2402 + + CMPLO_PPzZI_B = 2403 + + CMPLO_PPzZI_D = 2404 + + CMPLO_PPzZI_H = 2405 + + CMPLO_PPzZI_S = 2406 + + CMPLO_WIDE_PPzZZ_B = 2407 + + CMPLO_WIDE_PPzZZ_H = 2408 + + CMPLO_WIDE_PPzZZ_S = 2409 + + CMPLS_PPzZI_B = 2410 + + CMPLS_PPzZI_D = 2411 + + CMPLS_PPzZI_H = 2412 + + CMPLS_PPzZI_S = 2413 + + CMPLS_WIDE_PPzZZ_B = 2414 + + CMPLS_WIDE_PPzZZ_H = 2415 + + CMPLS_WIDE_PPzZZ_S = 2416 + + CMPLT_PPzZI_B = 2417 + + CMPLT_PPzZI_D = 2418 + + CMPLT_PPzZI_H = 2419 + + CMPLT_PPzZI_S = 2420 + + CMPLT_WIDE_PPzZZ_B = 2421 + + CMPLT_WIDE_PPzZZ_H = 2422 + + CMPLT_WIDE_PPzZZ_S = 2423 + + CMPNE_PPzZI_B = 2424 + + CMPNE_PPzZI_D = 2425 + + CMPNE_PPzZI_H = 2426 + + CMPNE_PPzZI_S = 2427 + + CMPNE_PPzZZ_B = 2428 + + CMPNE_PPzZZ_D = 2429 + + CMPNE_PPzZZ_H = 2430 + + CMPNE_PPzZZ_S = 2431 + + CMPNE_WIDE_PPzZZ_B = 2432 + + CMPNE_WIDE_PPzZZ_H = 2433 + + CMPNE_WIDE_PPzZZ_S = 2434 + + CMTSTv16i8 = 2435 + + CMTSTv1i64 = 2436 + + CMTSTv2i32 = 2437 + + CMTSTv2i64 = 2438 + + CMTSTv4i16 = 2439 + + CMTSTv4i32 = 2440 + + CMTSTv8i16 = 2441 + + CMTSTv8i8 = 2442 + + CNOT_ZPmZ_B = 2443 + + CNOT_ZPmZ_D = 2444 + + CNOT_ZPmZ_H = 2445 + + CNOT_ZPmZ_S = 2446 + + CNOT_ZPzZ_B = 2447 + + CNOT_ZPzZ_D = 2448 + + CNOT_ZPzZ_H = 2449 + + CNOT_ZPzZ_S = 2450 + + CNTB_XPiI = 2451 + + CNTD_XPiI = 2452 + + CNTH_XPiI = 2453 + + CNTP_XCI_B = 2454 + + CNTP_XCI_D = 2455 + + CNTP_XCI_H = 2456 + + CNTP_XCI_S = 2457 + + CNTP_XPP_B = 2458 + + CNTP_XPP_D = 2459 + + CNTP_XPP_H = 2460 + + CNTP_XPP_S = 2461 + + CNTW_XPiI = 2462 + + CNTWr = 2463 + + CNTXr = 2464 + + CNT_ZPmZ_B = 2465 + + CNT_ZPmZ_D = 2466 + + CNT_ZPmZ_H = 2467 + + CNT_ZPmZ_S = 2468 + + CNT_ZPzZ_B = 2469 + + CNT_ZPzZ_D = 2470 + + CNT_ZPzZ_H = 2471 + + CNT_ZPzZ_S = 2472 + + CNTv16i8 = 2473 + + CNTv8i8 = 2474 + + COMPACT_ZPZ_B = 2475 + + COMPACT_ZPZ_D = 2476 + + COMPACT_ZPZ_H = 2477 + + COMPACT_ZPZ_S = 2478 + + CPYE = 2479 + + CPYEN = 2480 + + CPYERN = 2481 + + CPYERT = 2482 + + CPYERTN = 2483 + + CPYERTRN = 2484 + + CPYERTWN = 2485 + + CPYET = 2486 + + CPYETN = 2487 + + CPYETRN = 2488 + + CPYETWN = 2489 + + CPYEWN = 2490 + + CPYEWT = 2491 + + CPYEWTN = 2492 + + CPYEWTRN = 2493 + + CPYEWTWN = 2494 + + CPYFE = 2495 + + CPYFEN = 2496 + + CPYFERN = 2497 + + CPYFERT = 2498 + + CPYFERTN = 2499 + + CPYFERTRN = 2500 + + CPYFERTWN = 2501 + + CPYFET = 2502 + + CPYFETN = 2503 + + CPYFETRN = 2504 + + CPYFETWN = 2505 + + CPYFEWN = 2506 + + CPYFEWT = 2507 + + CPYFEWTN = 2508 + + CPYFEWTRN = 2509 + + CPYFEWTWN = 2510 + + CPYFM = 2511 + + CPYFMN = 2512 + + CPYFMRN = 2513 + + CPYFMRT = 2514 + + CPYFMRTN = 2515 + + CPYFMRTRN = 2516 + + CPYFMRTWN = 2517 + + CPYFMT = 2518 + + CPYFMTN = 2519 + + CPYFMTRN = 2520 + + CPYFMTWN = 2521 + + CPYFMWN = 2522 + + CPYFMWT = 2523 + + CPYFMWTN = 2524 + + CPYFMWTRN = 2525 + + CPYFMWTWN = 2526 + + CPYFP = 2527 + + CPYFPN = 2528 + + CPYFPRN = 2529 + + CPYFPRT = 2530 + + CPYFPRTN = 2531 + + CPYFPRTRN = 2532 + + CPYFPRTWN = 2533 + + CPYFPT = 2534 + + CPYFPTN = 2535 + + CPYFPTRN = 2536 + + CPYFPTWN = 2537 + + CPYFPWN = 2538 + + CPYFPWT = 2539 + + CPYFPWTN = 2540 + + CPYFPWTRN = 2541 + + CPYFPWTWN = 2542 + + CPYM = 2543 + + CPYMN = 2544 + + CPYMRN = 2545 + + CPYMRT = 2546 + + CPYMRTN = 2547 + + CPYMRTRN = 2548 + + CPYMRTWN = 2549 + + CPYMT = 2550 + + CPYMTN = 2551 + + CPYMTRN = 2552 + + CPYMTWN = 2553 + + CPYMWN = 2554 + + CPYMWT = 2555 + + CPYMWTN = 2556 + + CPYMWTRN = 2557 + + CPYMWTWN = 2558 + + CPYP = 2559 + + CPYPN = 2560 + + CPYPRN = 2561 + + CPYPRT = 2562 + + CPYPRTN = 2563 + + CPYPRTRN = 2564 + + CPYPRTWN = 2565 + + CPYPT = 2566 + + CPYPTN = 2567 + + CPYPTRN = 2568 + + CPYPTWN = 2569 + + CPYPWN = 2570 + + CPYPWT = 2571 + + CPYPWTN = 2572 + + CPYPWTRN = 2573 + + CPYPWTWN = 2574 + + CPY_ZPmI_B = 2575 + + CPY_ZPmI_D = 2576 + + CPY_ZPmI_H = 2577 + + CPY_ZPmI_S = 2578 + + CPY_ZPmR_B = 2579 + + CPY_ZPmR_D = 2580 + + CPY_ZPmR_H = 2581 + + CPY_ZPmR_S = 2582 + + CPY_ZPmV_B = 2583 + + CPY_ZPmV_D = 2584 + + CPY_ZPmV_H = 2585 + + CPY_ZPmV_S = 2586 + + CPY_ZPzI_B = 2587 + + CPY_ZPzI_D = 2588 + + CPY_ZPzI_H = 2589 + + CPY_ZPzI_S = 2590 + + CRC32Brr = 2591 + + CRC32CBrr = 2592 + + CRC32CHrr = 2593 + + CRC32CWrr = 2594 + + CRC32CXrr = 2595 + + CRC32Hrr = 2596 + + CRC32Wrr = 2597 + + CRC32Xrr = 2598 + + CSELWr = 2599 + + CSELXr = 2600 + + CSINCWr = 2601 + + CSINCXr = 2602 + + CSINVWr = 2603 + + CSINVXr = 2604 + + CSNEGWr = 2605 + + CSNEGXr = 2606 + + CTERMEQ_WW = 2607 + + CTERMEQ_XX = 2608 + + CTERMNE_WW = 2609 + + CTERMNE_XX = 2610 + + CTZWr = 2611 + + CTZXr = 2612 + + DCPS1 = 2613 + + DCPS2 = 2614 + + DCPS3 = 2615 + + DECB_XPiI = 2616 + + DECD_XPiI = 2617 + + DECD_ZPiI = 2618 + + DECH_XPiI = 2619 + + DECH_ZPiI = 2620 + + DECP_XP_B = 2621 + + DECP_XP_D = 2622 + + DECP_XP_H = 2623 + + DECP_XP_S = 2624 + + DECP_ZP_D = 2625 + + DECP_ZP_H = 2626 + + DECP_ZP_S = 2627 + + DECW_XPiI = 2628 + + DECW_ZPiI = 2629 + + DMB = 2630 + + DRPS = 2631 + + DSB = 2632 + + DSBnXS = 2633 + + DUPM_ZI = 2634 + + DUPQ_ZZI_B = 2635 + + DUPQ_ZZI_D = 2636 + + DUPQ_ZZI_H = 2637 + + DUPQ_ZZI_S = 2638 + + DUP_ZI_B = 2639 + + DUP_ZI_D = 2640 + + DUP_ZI_H = 2641 + + DUP_ZI_S = 2642 + + DUP_ZR_B = 2643 + + DUP_ZR_D = 2644 + + DUP_ZR_H = 2645 + + DUP_ZR_S = 2646 + + DUP_ZZI_B = 2647 + + DUP_ZZI_D = 2648 + + DUP_ZZI_H = 2649 + + DUP_ZZI_Q = 2650 + + DUP_ZZI_S = 2651 + + DUPi16 = 2652 + + DUPi32 = 2653 + + DUPi64 = 2654 + + DUPi8 = 2655 + + DUPv16i8gpr = 2656 + + DUPv16i8lane = 2657 + + DUPv2i32gpr = 2658 + + DUPv2i32lane = 2659 + + DUPv2i64gpr = 2660 + + DUPv2i64lane = 2661 + + DUPv4i16gpr = 2662 + + DUPv4i16lane = 2663 + + DUPv4i32gpr = 2664 + + DUPv4i32lane = 2665 + + DUPv8i16gpr = 2666 + + DUPv8i16lane = 2667 + + DUPv8i8gpr = 2668 + + DUPv8i8lane = 2669 + + EONWrs = 2670 + + EONXrs = 2671 + + EOR3 = 2672 + + EOR3_ZZZZ = 2673 + + EORBT_ZZZ_B = 2674 + + EORBT_ZZZ_D = 2675 + + EORBT_ZZZ_H = 2676 + + EORBT_ZZZ_S = 2677 + + EORQV_VPZ_B = 2678 + + EORQV_VPZ_D = 2679 + + EORQV_VPZ_H = 2680 + + EORQV_VPZ_S = 2681 + + EORS_PPzPP = 2682 + + EORTB_ZZZ_B = 2683 + + EORTB_ZZZ_D = 2684 + + EORTB_ZZZ_H = 2685 + + EORTB_ZZZ_S = 2686 + + EORV_VPZ_B = 2687 + + EORV_VPZ_D = 2688 + + EORV_VPZ_H = 2689 + + EORV_VPZ_S = 2690 + + EORWri = 2691 + + EORWrs = 2692 + + EORXri = 2693 + + EORXrs = 2694 + + EOR_PPzPP = 2695 + + EOR_ZI = 2696 + + EOR_ZPmZ_B = 2697 + + EOR_ZPmZ_D = 2698 + + EOR_ZPmZ_H = 2699 + + EOR_ZPmZ_S = 2700 + + EOR_ZZZ = 2701 + + EORv16i8 = 2702 + + EORv8i8 = 2703 + + ERET = 2704 + + ERETAA = 2705 + + ERETAB = 2706 + + EXPAND_ZPZ_B = 2707 + + EXPAND_ZPZ_D = 2708 + + EXPAND_ZPZ_H = 2709 + + EXPAND_ZPZ_S = 2710 + + EXTQ_ZZI = 2711 + + EXTRACT_ZPMXI_H_B = 2712 + + EXTRACT_ZPMXI_H_D = 2713 + + EXTRACT_ZPMXI_H_H = 2714 + + EXTRACT_ZPMXI_H_Q = 2715 + + EXTRACT_ZPMXI_H_S = 2716 + + EXTRACT_ZPMXI_V_B = 2717 + + EXTRACT_ZPMXI_V_D = 2718 + + EXTRACT_ZPMXI_V_H = 2719 + + EXTRACT_ZPMXI_V_Q = 2720 + + EXTRACT_ZPMXI_V_S = 2721 + + EXTRWrri = 2722 + + EXTRXrri = 2723 + + EXT_ZZI = 2724 + + EXT_ZZI_B = 2725 + + EXTv16i8 = 2726 + + EXTv8i8 = 2727 + + F1CVTL = 2728 + + F1CVTL2 = 2729 + + F1CVTLT_ZZ_BtoH = 2730 + + F1CVTL_2ZZ_BtoH = 2731 + + F1CVT_2ZZ_BtoH = 2732 + + F1CVT_ZZ_BtoH = 2733 + + F2CVTL = 2734 + + F2CVTL2 = 2735 + + F2CVTLT_ZZ_BtoH = 2736 + + F2CVTL_2ZZ_BtoH = 2737 + + F2CVT_2ZZ_BtoH = 2738 + + F2CVT_ZZ_BtoH = 2739 + + FABD16 = 2740 + + FABD32 = 2741 + + FABD64 = 2742 + + FABD_ZPmZ_D = 2743 + + FABD_ZPmZ_H = 2744 + + FABD_ZPmZ_S = 2745 + + FABDv2f32 = 2746 + + FABDv2f64 = 2747 + + FABDv4f16 = 2748 + + FABDv4f32 = 2749 + + FABDv8f16 = 2750 + + FABSDr = 2751 + + FABSHr = 2752 + + FABSSr = 2753 + + FABS_ZPmZ_D = 2754 + + FABS_ZPmZ_H = 2755 + + FABS_ZPmZ_S = 2756 + + FABS_ZPzZ_D = 2757 + + FABS_ZPzZ_H = 2758 + + FABS_ZPzZ_S = 2759 + + FABSv2f32 = 2760 + + FABSv2f64 = 2761 + + FABSv4f16 = 2762 + + FABSv4f32 = 2763 + + FABSv8f16 = 2764 + + FACGE16 = 2765 + + FACGE32 = 2766 + + FACGE64 = 2767 + + FACGE_PPzZZ_D = 2768 + + FACGE_PPzZZ_H = 2769 + + FACGE_PPzZZ_S = 2770 + + FACGEv2f32 = 2771 + + FACGEv2f64 = 2772 + + FACGEv4f16 = 2773 + + FACGEv4f32 = 2774 + + FACGEv8f16 = 2775 + + FACGT16 = 2776 + + FACGT32 = 2777 + + FACGT64 = 2778 + + FACGT_PPzZZ_D = 2779 + + FACGT_PPzZZ_H = 2780 + + FACGT_PPzZZ_S = 2781 + + FACGTv2f32 = 2782 + + FACGTv2f64 = 2783 + + FACGTv4f16 = 2784 + + FACGTv4f32 = 2785 + + FACGTv8f16 = 2786 + + FADDA_VPZ_D = 2787 + + FADDA_VPZ_H = 2788 + + FADDA_VPZ_S = 2789 + + FADDDrr = 2790 + + FADDHrr = 2791 + + FADDP_ZPmZZ_D = 2792 + + FADDP_ZPmZZ_H = 2793 + + FADDP_ZPmZZ_S = 2794 + + FADDPv2f32 = 2795 + + FADDPv2f64 = 2796 + + FADDPv2i16p = 2797 + + FADDPv2i32p = 2798 + + FADDPv2i64p = 2799 + + FADDPv4f16 = 2800 + + FADDPv4f32 = 2801 + + FADDPv8f16 = 2802 + + FADDQV_D = 2803 + + FADDQV_H = 2804 + + FADDQV_S = 2805 + + FADDSrr = 2806 + + FADDV_VPZ_D = 2807 + + FADDV_VPZ_H = 2808 + + FADDV_VPZ_S = 2809 + + FADD_VG2_M2Z_D = 2810 + + FADD_VG2_M2Z_H = 2811 + + FADD_VG2_M2Z_S = 2812 + + FADD_VG4_M4Z_D = 2813 + + FADD_VG4_M4Z_H = 2814 + + FADD_VG4_M4Z_S = 2815 + + FADD_ZPmI_D = 2816 + + FADD_ZPmI_H = 2817 + + FADD_ZPmI_S = 2818 + + FADD_ZPmZ_D = 2819 + + FADD_ZPmZ_H = 2820 + + FADD_ZPmZ_S = 2821 + + FADD_ZZZ_D = 2822 + + FADD_ZZZ_H = 2823 + + FADD_ZZZ_S = 2824 + + FADDv2f32 = 2825 + + FADDv2f64 = 2826 + + FADDv4f16 = 2827 + + FADDv4f32 = 2828 + + FADDv8f16 = 2829 + + FAMAX_2Z2Z_D = 2830 + + FAMAX_2Z2Z_H = 2831 + + FAMAX_2Z2Z_S = 2832 + + FAMAX_4Z4Z_D = 2833 + + FAMAX_4Z4Z_H = 2834 + + FAMAX_4Z4Z_S = 2835 + + FAMAX_ZPmZ_D = 2836 + + FAMAX_ZPmZ_H = 2837 + + FAMAX_ZPmZ_S = 2838 + + FAMAXv2f32 = 2839 + + FAMAXv2f64 = 2840 + + FAMAXv4f16 = 2841 + + FAMAXv4f32 = 2842 + + FAMAXv8f16 = 2843 + + FAMIN_2Z2Z_D = 2844 + + FAMIN_2Z2Z_H = 2845 + + FAMIN_2Z2Z_S = 2846 + + FAMIN_4Z4Z_D = 2847 + + FAMIN_4Z4Z_H = 2848 + + FAMIN_4Z4Z_S = 2849 + + FAMIN_ZPmZ_D = 2850 + + FAMIN_ZPmZ_H = 2851 + + FAMIN_ZPmZ_S = 2852 + + FAMINv2f32 = 2853 + + FAMINv2f64 = 2854 + + FAMINv4f16 = 2855 + + FAMINv4f32 = 2856 + + FAMINv8f16 = 2857 + + FCADD_ZPmZ_D = 2858 + + FCADD_ZPmZ_H = 2859 + + FCADD_ZPmZ_S = 2860 + + FCADDv2f32 = 2861 + + FCADDv2f64 = 2862 + + FCADDv4f16 = 2863 + + FCADDv4f32 = 2864 + + FCADDv8f16 = 2865 + + FCCMPDrr = 2866 + + FCCMPEDrr = 2867 + + FCCMPEHrr = 2868 + + FCCMPESrr = 2869 + + FCCMPHrr = 2870 + + FCCMPSrr = 2871 + + FCLAMP_VG2_2Z2Z_D = 2872 + + FCLAMP_VG2_2Z2Z_H = 2873 + + FCLAMP_VG2_2Z2Z_S = 2874 + + FCLAMP_VG4_4Z4Z_D = 2875 + + FCLAMP_VG4_4Z4Z_H = 2876 + + FCLAMP_VG4_4Z4Z_S = 2877 + + FCLAMP_ZZZ_D = 2878 + + FCLAMP_ZZZ_H = 2879 + + FCLAMP_ZZZ_S = 2880 + + FCMEQ16 = 2881 + + FCMEQ32 = 2882 + + FCMEQ64 = 2883 + + FCMEQ_PPzZ0_D = 2884 + + FCMEQ_PPzZ0_H = 2885 + + FCMEQ_PPzZ0_S = 2886 + + FCMEQ_PPzZZ_D = 2887 + + FCMEQ_PPzZZ_H = 2888 + + FCMEQ_PPzZZ_S = 2889 + + FCMEQv1i16rz = 2890 + + FCMEQv1i32rz = 2891 + + FCMEQv1i64rz = 2892 + + FCMEQv2f32 = 2893 + + FCMEQv2f64 = 2894 + + FCMEQv2i32rz = 2895 + + FCMEQv2i64rz = 2896 + + FCMEQv4f16 = 2897 + + FCMEQv4f32 = 2898 + + FCMEQv4i16rz = 2899 + + FCMEQv4i32rz = 2900 + + FCMEQv8f16 = 2901 + + FCMEQv8i16rz = 2902 + + FCMGE16 = 2903 + + FCMGE32 = 2904 + + FCMGE64 = 2905 + + FCMGE_PPzZ0_D = 2906 + + FCMGE_PPzZ0_H = 2907 + + FCMGE_PPzZ0_S = 2908 + + FCMGE_PPzZZ_D = 2909 + + FCMGE_PPzZZ_H = 2910 + + FCMGE_PPzZZ_S = 2911 + + FCMGEv1i16rz = 2912 + + FCMGEv1i32rz = 2913 + + FCMGEv1i64rz = 2914 + + FCMGEv2f32 = 2915 + + FCMGEv2f64 = 2916 + + FCMGEv2i32rz = 2917 + + FCMGEv2i64rz = 2918 + + FCMGEv4f16 = 2919 + + FCMGEv4f32 = 2920 + + FCMGEv4i16rz = 2921 + + FCMGEv4i32rz = 2922 + + FCMGEv8f16 = 2923 + + FCMGEv8i16rz = 2924 + + FCMGT16 = 2925 + + FCMGT32 = 2926 + + FCMGT64 = 2927 + + FCMGT_PPzZ0_D = 2928 + + FCMGT_PPzZ0_H = 2929 + + FCMGT_PPzZ0_S = 2930 + + FCMGT_PPzZZ_D = 2931 + + FCMGT_PPzZZ_H = 2932 + + FCMGT_PPzZZ_S = 2933 + + FCMGTv1i16rz = 2934 + + FCMGTv1i32rz = 2935 + + FCMGTv1i64rz = 2936 + + FCMGTv2f32 = 2937 + + FCMGTv2f64 = 2938 + + FCMGTv2i32rz = 2939 + + FCMGTv2i64rz = 2940 + + FCMGTv4f16 = 2941 + + FCMGTv4f32 = 2942 + + FCMGTv4i16rz = 2943 + + FCMGTv4i32rz = 2944 + + FCMGTv8f16 = 2945 + + FCMGTv8i16rz = 2946 + + FCMLA_ZPmZZ_D = 2947 + + FCMLA_ZPmZZ_H = 2948 + + FCMLA_ZPmZZ_S = 2949 + + FCMLA_ZZZI_H = 2950 + + FCMLA_ZZZI_S = 2951 + + FCMLAv2f32 = 2952 + + FCMLAv2f64 = 2953 + + FCMLAv4f16 = 2954 + + FCMLAv4f16_indexed = 2955 + + FCMLAv4f32 = 2956 + + FCMLAv4f32_indexed = 2957 + + FCMLAv8f16 = 2958 + + FCMLAv8f16_indexed = 2959 + + FCMLE_PPzZ0_D = 2960 + + FCMLE_PPzZ0_H = 2961 + + FCMLE_PPzZ0_S = 2962 + + FCMLEv1i16rz = 2963 + + FCMLEv1i32rz = 2964 + + FCMLEv1i64rz = 2965 + + FCMLEv2i32rz = 2966 + + FCMLEv2i64rz = 2967 + + FCMLEv4i16rz = 2968 + + FCMLEv4i32rz = 2969 + + FCMLEv8i16rz = 2970 + + FCMLT_PPzZ0_D = 2971 + + FCMLT_PPzZ0_H = 2972 + + FCMLT_PPzZ0_S = 2973 + + FCMLTv1i16rz = 2974 + + FCMLTv1i32rz = 2975 + + FCMLTv1i64rz = 2976 + + FCMLTv2i32rz = 2977 + + FCMLTv2i64rz = 2978 + + FCMLTv4i16rz = 2979 + + FCMLTv4i32rz = 2980 + + FCMLTv8i16rz = 2981 + + FCMNE_PPzZ0_D = 2982 + + FCMNE_PPzZ0_H = 2983 + + FCMNE_PPzZ0_S = 2984 + + FCMNE_PPzZZ_D = 2985 + + FCMNE_PPzZZ_H = 2986 + + FCMNE_PPzZZ_S = 2987 + + FCMPDri = 2988 + + FCMPDrr = 2989 + + FCMPEDri = 2990 + + FCMPEDrr = 2991 + + FCMPEHri = 2992 + + FCMPEHrr = 2993 + + FCMPESri = 2994 + + FCMPESrr = 2995 + + FCMPHri = 2996 + + FCMPHrr = 2997 + + FCMPSri = 2998 + + FCMPSrr = 2999 + + FCMUO_PPzZZ_D = 3000 + + FCMUO_PPzZZ_H = 3001 + + FCMUO_PPzZZ_S = 3002 + + FCPY_ZPmI_D = 3003 + + FCPY_ZPmI_H = 3004 + + FCPY_ZPmI_S = 3005 + + FCSELDrrr = 3006 + + FCSELHrrr = 3007 + + FCSELSrrr = 3008 + + FCVTASDHr = 3009 + + FCVTASDSr = 3010 + + FCVTASSDr = 3011 + + FCVTASSHr = 3012 + + FCVTASUWDr = 3013 + + FCVTASUWHr = 3014 + + FCVTASUWSr = 3015 + + FCVTASUXDr = 3016 + + FCVTASUXHr = 3017 + + FCVTASUXSr = 3018 + + FCVTASv1f16 = 3019 + + FCVTASv1i32 = 3020 + + FCVTASv1i64 = 3021 + + FCVTASv2f32 = 3022 + + FCVTASv2f64 = 3023 + + FCVTASv4f16 = 3024 + + FCVTASv4f32 = 3025 + + FCVTASv8f16 = 3026 + + FCVTAUDHr = 3027 + + FCVTAUDSr = 3028 + + FCVTAUSDr = 3029 + + FCVTAUSHr = 3030 + + FCVTAUUWDr = 3031 + + FCVTAUUWHr = 3032 + + FCVTAUUWSr = 3033 + + FCVTAUUXDr = 3034 + + FCVTAUUXHr = 3035 + + FCVTAUUXSr = 3036 + + FCVTAUv1f16 = 3037 + + FCVTAUv1i32 = 3038 + + FCVTAUv1i64 = 3039 + + FCVTAUv2f32 = 3040 + + FCVTAUv2f64 = 3041 + + FCVTAUv4f16 = 3042 + + FCVTAUv4f32 = 3043 + + FCVTAUv8f16 = 3044 + + FCVTDHr = 3045 + + FCVTDSr = 3046 + + FCVTHDr = 3047 + + FCVTHSr = 3048 + + FCVTLT_ZPmZ_HtoS = 3049 + + FCVTLT_ZPmZ_StoD = 3050 + + FCVTLT_ZPzZ_HtoS = 3051 + + FCVTLT_ZPzZ_StoD = 3052 + + FCVTL_2ZZ_H_S = 3053 + + FCVTLv2i32 = 3054 + + FCVTLv4i16 = 3055 + + FCVTLv4i32 = 3056 + + FCVTLv8i16 = 3057 + + FCVTMSDHr = 3058 + + FCVTMSDSr = 3059 + + FCVTMSSDr = 3060 + + FCVTMSSHr = 3061 + + FCVTMSUWDr = 3062 + + FCVTMSUWHr = 3063 + + FCVTMSUWSr = 3064 + + FCVTMSUXDr = 3065 + + FCVTMSUXHr = 3066 + + FCVTMSUXSr = 3067 + + FCVTMSv1f16 = 3068 + + FCVTMSv1i32 = 3069 + + FCVTMSv1i64 = 3070 + + FCVTMSv2f32 = 3071 + + FCVTMSv2f64 = 3072 + + FCVTMSv4f16 = 3073 + + FCVTMSv4f32 = 3074 + + FCVTMSv8f16 = 3075 + + FCVTMUDHr = 3076 + + FCVTMUDSr = 3077 + + FCVTMUSDr = 3078 + + FCVTMUSHr = 3079 + + FCVTMUUWDr = 3080 + + FCVTMUUWHr = 3081 + + FCVTMUUWSr = 3082 + + FCVTMUUXDr = 3083 + + FCVTMUUXHr = 3084 + + FCVTMUUXSr = 3085 + + FCVTMUv1f16 = 3086 + + FCVTMUv1i32 = 3087 + + FCVTMUv1i64 = 3088 + + FCVTMUv2f32 = 3089 + + FCVTMUv2f64 = 3090 + + FCVTMUv4f16 = 3091 + + FCVTMUv4f32 = 3092 + + FCVTMUv8f16 = 3093 + + FCVTNB_Z2Z_StoB = 3094 + + FCVTNSDHr = 3095 + + FCVTNSDSr = 3096 + + FCVTNSSDr = 3097 + + FCVTNSSHr = 3098 + + FCVTNSUWDr = 3099 + + FCVTNSUWHr = 3100 + + FCVTNSUWSr = 3101 + + FCVTNSUXDr = 3102 + + FCVTNSUXHr = 3103 + + FCVTNSUXSr = 3104 + + FCVTNSv1f16 = 3105 + + FCVTNSv1i32 = 3106 + + FCVTNSv1i64 = 3107 + + FCVTNSv2f32 = 3108 + + FCVTNSv2f64 = 3109 + + FCVTNSv4f16 = 3110 + + FCVTNSv4f32 = 3111 + + FCVTNSv8f16 = 3112 + + FCVTNT_Z2Z_StoB = 3113 + + FCVTNT_ZPmZ_DtoS = 3114 + + FCVTNT_ZPmZ_StoH = 3115 + + FCVTNT_ZPzZ_DtoS = 3116 + + FCVTNT_ZPzZ_StoH = 3117 + + FCVTNUDHr = 3118 + + FCVTNUDSr = 3119 + + FCVTNUSDr = 3120 + + FCVTNUSHr = 3121 + + FCVTNUUWDr = 3122 + + FCVTNUUWHr = 3123 + + FCVTNUUWSr = 3124 + + FCVTNUUXDr = 3125 + + FCVTNUUXHr = 3126 + + FCVTNUUXSr = 3127 + + FCVTNUv1f16 = 3128 + + FCVTNUv1i32 = 3129 + + FCVTNUv1i64 = 3130 + + FCVTNUv2f32 = 3131 + + FCVTNUv2f64 = 3132 + + FCVTNUv4f16 = 3133 + + FCVTNUv4f32 = 3134 + + FCVTNUv8f16 = 3135 + + FCVTN_F16v16f8 = 3136 + + FCVTN_F16v8f8 = 3137 + + FCVTN_F322v16f8 = 3138 + + FCVTN_F32v8f8 = 3139 + + FCVTN_Z2Z_HtoB = 3140 + + FCVTN_Z2Z_StoH = 3141 + + FCVTN_Z4Z_StoB = 3142 + + FCVTNv2i32 = 3143 + + FCVTNv4i16 = 3144 + + FCVTNv4i32 = 3145 + + FCVTNv8i16 = 3146 + + FCVTPSDHr = 3147 + + FCVTPSDSr = 3148 + + FCVTPSSDr = 3149 + + FCVTPSSHr = 3150 + + FCVTPSUWDr = 3151 + + FCVTPSUWHr = 3152 + + FCVTPSUWSr = 3153 + + FCVTPSUXDr = 3154 + + FCVTPSUXHr = 3155 + + FCVTPSUXSr = 3156 + + FCVTPSv1f16 = 3157 + + FCVTPSv1i32 = 3158 + + FCVTPSv1i64 = 3159 + + FCVTPSv2f32 = 3160 + + FCVTPSv2f64 = 3161 + + FCVTPSv4f16 = 3162 + + FCVTPSv4f32 = 3163 + + FCVTPSv8f16 = 3164 + + FCVTPUDHr = 3165 + + FCVTPUDSr = 3166 + + FCVTPUSDr = 3167 + + FCVTPUSHr = 3168 + + FCVTPUUWDr = 3169 + + FCVTPUUWHr = 3170 + + FCVTPUUWSr = 3171 + + FCVTPUUXDr = 3172 + + FCVTPUUXHr = 3173 + + FCVTPUUXSr = 3174 + + FCVTPUv1f16 = 3175 + + FCVTPUv1i32 = 3176 + + FCVTPUv1i64 = 3177 + + FCVTPUv2f32 = 3178 + + FCVTPUv2f64 = 3179 + + FCVTPUv4f16 = 3180 + + FCVTPUv4f32 = 3181 + + FCVTPUv8f16 = 3182 + + FCVTSDr = 3183 + + FCVTSHr = 3184 + + FCVTXNT_ZPmZ_DtoS = 3185 + + FCVTXNT_ZPzZ_StoD = 3186 + + FCVTXNv1i64 = 3187 + + FCVTXNv2f32 = 3188 + + FCVTXNv4f32 = 3189 + + FCVTX_ZPmZ_DtoS = 3190 + + FCVTX_ZPzZ_DtoS = 3191 + + FCVTZSDHr = 3192 + + FCVTZSDSr = 3193 + + FCVTZSN_Z2Z_DtoS = 3194 + + FCVTZSN_Z2Z_HtoB = 3195 + + FCVTZSN_Z2Z_StoH = 3196 + + FCVTZSSDr = 3197 + + FCVTZSSHr = 3198 + + FCVTZSSWDri = 3199 + + FCVTZSSWHri = 3200 + + FCVTZSSWSri = 3201 + + FCVTZSSXDri = 3202 + + FCVTZSSXHri = 3203 + + FCVTZSSXSri = 3204 + + FCVTZSUWDr = 3205 + + FCVTZSUWHr = 3206 + + FCVTZSUWSr = 3207 + + FCVTZSUXDr = 3208 + + FCVTZSUXHr = 3209 + + FCVTZSUXSr = 3210 + + FCVTZS_2Z2Z_StoS = 3211 + + FCVTZS_4Z4Z_StoS = 3212 + + FCVTZS_ZPmZ_DtoD = 3213 + + FCVTZS_ZPmZ_DtoS = 3214 + + FCVTZS_ZPmZ_HtoD = 3215 + + FCVTZS_ZPmZ_HtoH = 3216 + + FCVTZS_ZPmZ_HtoS = 3217 + + FCVTZS_ZPmZ_StoD = 3218 + + FCVTZS_ZPmZ_StoS = 3219 + + FCVTZS_ZPzZ_DtoD = 3220 + + FCVTZS_ZPzZ_DtoS = 3221 + + FCVTZS_ZPzZ_HtoD = 3222 + + FCVTZS_ZPzZ_HtoH = 3223 + + FCVTZS_ZPzZ_HtoS = 3224 + + FCVTZS_ZPzZ_StoD = 3225 + + FCVTZS_ZPzZ_StoS = 3226 + + FCVTZSd = 3227 + + FCVTZSh = 3228 + + FCVTZSs = 3229 + + FCVTZSv1f16 = 3230 + + FCVTZSv1i32 = 3231 + + FCVTZSv1i64 = 3232 + + FCVTZSv2f32 = 3233 + + FCVTZSv2f64 = 3234 + + FCVTZSv2i32_shift = 3235 + + FCVTZSv2i64_shift = 3236 + + FCVTZSv4f16 = 3237 + + FCVTZSv4f32 = 3238 + + FCVTZSv4i16_shift = 3239 + + FCVTZSv4i32_shift = 3240 + + FCVTZSv8f16 = 3241 + + FCVTZSv8i16_shift = 3242 + + FCVTZUDHr = 3243 + + FCVTZUDSr = 3244 + + FCVTZUN_Z2Z_DtoS = 3245 + + FCVTZUN_Z2Z_HtoB = 3246 + + FCVTZUN_Z2Z_StoH = 3247 + + FCVTZUSDr = 3248 + + FCVTZUSHr = 3249 + + FCVTZUSWDri = 3250 + + FCVTZUSWHri = 3251 + + FCVTZUSWSri = 3252 + + FCVTZUSXDri = 3253 + + FCVTZUSXHri = 3254 + + FCVTZUSXSri = 3255 + + FCVTZUUWDr = 3256 + + FCVTZUUWHr = 3257 + + FCVTZUUWSr = 3258 + + FCVTZUUXDr = 3259 + + FCVTZUUXHr = 3260 + + FCVTZUUXSr = 3261 + + FCVTZU_2Z2Z_StoS = 3262 + + FCVTZU_4Z4Z_StoS = 3263 + + FCVTZU_ZPmZ_DtoD = 3264 + + FCVTZU_ZPmZ_DtoS = 3265 + + FCVTZU_ZPmZ_HtoD = 3266 + + FCVTZU_ZPmZ_HtoH = 3267 + + FCVTZU_ZPmZ_HtoS = 3268 + + FCVTZU_ZPmZ_StoD = 3269 + + FCVTZU_ZPmZ_StoS = 3270 + + FCVTZU_ZPzZ_DtoD = 3271 + + FCVTZU_ZPzZ_DtoS = 3272 + + FCVTZU_ZPzZ_HtoD = 3273 + + FCVTZU_ZPzZ_HtoH = 3274 + + FCVTZU_ZPzZ_HtoS = 3275 + + FCVTZU_ZPzZ_StoD = 3276 + + FCVTZU_ZPzZ_StoS = 3277 + + FCVTZUd = 3278 + + FCVTZUh = 3279 + + FCVTZUs = 3280 + + FCVTZUv1f16 = 3281 + + FCVTZUv1i32 = 3282 + + FCVTZUv1i64 = 3283 + + FCVTZUv2f32 = 3284 + + FCVTZUv2f64 = 3285 + + FCVTZUv2i32_shift = 3286 + + FCVTZUv2i64_shift = 3287 + + FCVTZUv4f16 = 3288 + + FCVTZUv4f32 = 3289 + + FCVTZUv4i16_shift = 3290 + + FCVTZUv4i32_shift = 3291 + + FCVTZUv8f16 = 3292 + + FCVTZUv8i16_shift = 3293 + + FCVT_2ZZ_H_S = 3294 + + FCVT_Z2Z_HtoB = 3295 + + FCVT_Z2Z_StoH = 3296 + + FCVT_Z4Z_StoB = 3297 + + FCVT_ZPmZ_DtoH = 3298 + + FCVT_ZPmZ_DtoS = 3299 + + FCVT_ZPmZ_HtoD = 3300 + + FCVT_ZPmZ_HtoS = 3301 + + FCVT_ZPmZ_StoD = 3302 + + FCVT_ZPmZ_StoH = 3303 + + FCVT_ZPzZ_DtoH = 3304 + + FCVT_ZPzZ_DtoS = 3305 + + FCVT_ZPzZ_HtoD = 3306 + + FCVT_ZPzZ_HtoS = 3307 + + FCVT_ZPzZ_StoD = 3308 + + FCVT_ZPzZ_StoH = 3309 + + FDIVDrr = 3310 + + FDIVHrr = 3311 + + FDIVR_ZPmZ_D = 3312 + + FDIVR_ZPmZ_H = 3313 + + FDIVR_ZPmZ_S = 3314 + + FDIVSrr = 3315 + + FDIV_ZPmZ_D = 3316 + + FDIV_ZPmZ_H = 3317 + + FDIV_ZPmZ_S = 3318 + + FDIVv2f32 = 3319 + + FDIVv2f64 = 3320 + + FDIVv4f16 = 3321 + + FDIVv4f32 = 3322 + + FDIVv8f16 = 3323 + + FDOT_VG2_M2Z2Z_BtoH = 3324 + + FDOT_VG2_M2Z2Z_BtoS = 3325 + + FDOT_VG2_M2Z2Z_HtoS = 3326 + + FDOT_VG2_M2ZZI_BtoH = 3327 + + FDOT_VG2_M2ZZI_BtoS = 3328 + + FDOT_VG2_M2ZZI_HtoS = 3329 + + FDOT_VG2_M2ZZ_BtoH = 3330 + + FDOT_VG2_M2ZZ_BtoS = 3331 + + FDOT_VG2_M2ZZ_HtoS = 3332 + + FDOT_VG4_M4Z4Z_BtoH = 3333 + + FDOT_VG4_M4Z4Z_BtoS = 3334 + + FDOT_VG4_M4Z4Z_HtoS = 3335 + + FDOT_VG4_M4ZZI_BtoH = 3336 + + FDOT_VG4_M4ZZI_BtoS = 3337 + + FDOT_VG4_M4ZZI_HtoS = 3338 + + FDOT_VG4_M4ZZ_BtoH = 3339 + + FDOT_VG4_M4ZZ_BtoS = 3340 + + FDOT_VG4_M4ZZ_HtoS = 3341 + + FDOT_ZZZI_BtoH = 3342 + + FDOT_ZZZI_BtoS = 3343 + + FDOT_ZZZI_S = 3344 + + FDOT_ZZZ_BtoH = 3345 + + FDOT_ZZZ_BtoS = 3346 + + FDOT_ZZZ_S = 3347 + + FDOTlanev2f32 = 3348 + + FDOTlanev4f16 = 3349 + + FDOTlanev4f16_v2f32 = 3350 + + FDOTlanev4f32 = 3351 + + FDOTlanev8f16 = 3352 + + FDOTlanev8f16_v4f32 = 3353 + + FDOTv2f32 = 3354 + + FDOTv4f16 = 3355 + + FDOTv4f16_v2f32 = 3356 + + FDOTv4f32 = 3357 + + FDOTv8f16 = 3358 + + FDOTv8f16_v4f32 = 3359 + + FDUP_ZI_D = 3360 + + FDUP_ZI_H = 3361 + + FDUP_ZI_S = 3362 + + FEXPA_ZZ_D = 3363 + + FEXPA_ZZ_H = 3364 + + FEXPA_ZZ_S = 3365 + + FIRSTP_XPP_B = 3366 + + FIRSTP_XPP_D = 3367 + + FIRSTP_XPP_H = 3368 + + FIRSTP_XPP_S = 3369 + + FJCVTZS = 3370 + + FLOGB_ZPmZ_D = 3371 + + FLOGB_ZPmZ_H = 3372 + + FLOGB_ZPmZ_S = 3373 + + FLOGB_ZPzZ_D = 3374 + + FLOGB_ZPzZ_H = 3375 + + FLOGB_ZPzZ_S = 3376 + + FMADDDrrr = 3377 + + FMADDHrrr = 3378 + + FMADDSrrr = 3379 + + FMAD_ZPmZZ_D = 3380 + + FMAD_ZPmZZ_H = 3381 + + FMAD_ZPmZZ_S = 3382 + + FMAXDrr = 3383 + + FMAXHrr = 3384 + + FMAXNMDrr = 3385 + + FMAXNMHrr = 3386 + + FMAXNMP_ZPmZZ_D = 3387 + + FMAXNMP_ZPmZZ_H = 3388 + + FMAXNMP_ZPmZZ_S = 3389 + + FMAXNMPv2f32 = 3390 + + FMAXNMPv2f64 = 3391 + + FMAXNMPv2i16p = 3392 + + FMAXNMPv2i32p = 3393 + + FMAXNMPv2i64p = 3394 + + FMAXNMPv4f16 = 3395 + + FMAXNMPv4f32 = 3396 + + FMAXNMPv8f16 = 3397 + + FMAXNMQV_D = 3398 + + FMAXNMQV_H = 3399 + + FMAXNMQV_S = 3400 + + FMAXNMSrr = 3401 + + FMAXNMV_VPZ_D = 3402 + + FMAXNMV_VPZ_H = 3403 + + FMAXNMV_VPZ_S = 3404 + + FMAXNMVv4i16v = 3405 + + FMAXNMVv4i32v = 3406 + + FMAXNMVv8i16v = 3407 + + FMAXNM_VG2_2Z2Z_D = 3408 + + FMAXNM_VG2_2Z2Z_H = 3409 + + FMAXNM_VG2_2Z2Z_S = 3410 + + FMAXNM_VG2_2ZZ_D = 3411 + + FMAXNM_VG2_2ZZ_H = 3412 + + FMAXNM_VG2_2ZZ_S = 3413 + + FMAXNM_VG4_4Z4Z_D = 3414 + + FMAXNM_VG4_4Z4Z_H = 3415 + + FMAXNM_VG4_4Z4Z_S = 3416 + + FMAXNM_VG4_4ZZ_D = 3417 + + FMAXNM_VG4_4ZZ_H = 3418 + + FMAXNM_VG4_4ZZ_S = 3419 + + FMAXNM_ZPmI_D = 3420 + + FMAXNM_ZPmI_H = 3421 + + FMAXNM_ZPmI_S = 3422 + + FMAXNM_ZPmZ_D = 3423 + + FMAXNM_ZPmZ_H = 3424 + + FMAXNM_ZPmZ_S = 3425 + + FMAXNMv2f32 = 3426 + + FMAXNMv2f64 = 3427 + + FMAXNMv4f16 = 3428 + + FMAXNMv4f32 = 3429 + + FMAXNMv8f16 = 3430 + + FMAXP_ZPmZZ_D = 3431 + + FMAXP_ZPmZZ_H = 3432 + + FMAXP_ZPmZZ_S = 3433 + + FMAXPv2f32 = 3434 + + FMAXPv2f64 = 3435 + + FMAXPv2i16p = 3436 + + FMAXPv2i32p = 3437 + + FMAXPv2i64p = 3438 + + FMAXPv4f16 = 3439 + + FMAXPv4f32 = 3440 + + FMAXPv8f16 = 3441 + + FMAXQV_D = 3442 + + FMAXQV_H = 3443 + + FMAXQV_S = 3444 + + FMAXSrr = 3445 + + FMAXV_VPZ_D = 3446 + + FMAXV_VPZ_H = 3447 + + FMAXV_VPZ_S = 3448 + + FMAXVv4i16v = 3449 + + FMAXVv4i32v = 3450 + + FMAXVv8i16v = 3451 + + FMAX_VG2_2Z2Z_D = 3452 + + FMAX_VG2_2Z2Z_H = 3453 + + FMAX_VG2_2Z2Z_S = 3454 + + FMAX_VG2_2ZZ_D = 3455 + + FMAX_VG2_2ZZ_H = 3456 + + FMAX_VG2_2ZZ_S = 3457 + + FMAX_VG4_4Z4Z_D = 3458 + + FMAX_VG4_4Z4Z_H = 3459 + + FMAX_VG4_4Z4Z_S = 3460 + + FMAX_VG4_4ZZ_D = 3461 + + FMAX_VG4_4ZZ_H = 3462 + + FMAX_VG4_4ZZ_S = 3463 + + FMAX_ZPmI_D = 3464 + + FMAX_ZPmI_H = 3465 + + FMAX_ZPmI_S = 3466 + + FMAX_ZPmZ_D = 3467 + + FMAX_ZPmZ_H = 3468 + + FMAX_ZPmZ_S = 3469 + + FMAXv2f32 = 3470 + + FMAXv2f64 = 3471 + + FMAXv4f16 = 3472 + + FMAXv4f32 = 3473 + + FMAXv8f16 = 3474 + + FMINDrr = 3475 + + FMINHrr = 3476 + + FMINNMDrr = 3477 + + FMINNMHrr = 3478 + + FMINNMP_ZPmZZ_D = 3479 + + FMINNMP_ZPmZZ_H = 3480 + + FMINNMP_ZPmZZ_S = 3481 + + FMINNMPv2f32 = 3482 + + FMINNMPv2f64 = 3483 + + FMINNMPv2i16p = 3484 + + FMINNMPv2i32p = 3485 + + FMINNMPv2i64p = 3486 + + FMINNMPv4f16 = 3487 + + FMINNMPv4f32 = 3488 + + FMINNMPv8f16 = 3489 + + FMINNMQV_D = 3490 + + FMINNMQV_H = 3491 + + FMINNMQV_S = 3492 + + FMINNMSrr = 3493 + + FMINNMV_VPZ_D = 3494 + + FMINNMV_VPZ_H = 3495 + + FMINNMV_VPZ_S = 3496 + + FMINNMVv4i16v = 3497 + + FMINNMVv4i32v = 3498 + + FMINNMVv8i16v = 3499 + + FMINNM_VG2_2Z2Z_D = 3500 + + FMINNM_VG2_2Z2Z_H = 3501 + + FMINNM_VG2_2Z2Z_S = 3502 + + FMINNM_VG2_2ZZ_D = 3503 + + FMINNM_VG2_2ZZ_H = 3504 + + FMINNM_VG2_2ZZ_S = 3505 + + FMINNM_VG4_4Z4Z_D = 3506 + + FMINNM_VG4_4Z4Z_H = 3507 + + FMINNM_VG4_4Z4Z_S = 3508 + + FMINNM_VG4_4ZZ_D = 3509 + + FMINNM_VG4_4ZZ_H = 3510 + + FMINNM_VG4_4ZZ_S = 3511 + + FMINNM_ZPmI_D = 3512 + + FMINNM_ZPmI_H = 3513 + + FMINNM_ZPmI_S = 3514 + + FMINNM_ZPmZ_D = 3515 + + FMINNM_ZPmZ_H = 3516 + + FMINNM_ZPmZ_S = 3517 + + FMINNMv2f32 = 3518 + + FMINNMv2f64 = 3519 + + FMINNMv4f16 = 3520 + + FMINNMv4f32 = 3521 + + FMINNMv8f16 = 3522 + + FMINP_ZPmZZ_D = 3523 + + FMINP_ZPmZZ_H = 3524 + + FMINP_ZPmZZ_S = 3525 + + FMINPv2f32 = 3526 + + FMINPv2f64 = 3527 + + FMINPv2i16p = 3528 + + FMINPv2i32p = 3529 + + FMINPv2i64p = 3530 + + FMINPv4f16 = 3531 + + FMINPv4f32 = 3532 + + FMINPv8f16 = 3533 + + FMINQV_D = 3534 + + FMINQV_H = 3535 + + FMINQV_S = 3536 + + FMINSrr = 3537 + + FMINV_VPZ_D = 3538 + + FMINV_VPZ_H = 3539 + + FMINV_VPZ_S = 3540 + + FMINVv4i16v = 3541 + + FMINVv4i32v = 3542 + + FMINVv8i16v = 3543 + + FMIN_VG2_2Z2Z_D = 3544 + + FMIN_VG2_2Z2Z_H = 3545 + + FMIN_VG2_2Z2Z_S = 3546 + + FMIN_VG2_2ZZ_D = 3547 + + FMIN_VG2_2ZZ_H = 3548 + + FMIN_VG2_2ZZ_S = 3549 + + FMIN_VG4_4Z4Z_D = 3550 + + FMIN_VG4_4Z4Z_H = 3551 + + FMIN_VG4_4Z4Z_S = 3552 + + FMIN_VG4_4ZZ_D = 3553 + + FMIN_VG4_4ZZ_H = 3554 + + FMIN_VG4_4ZZ_S = 3555 + + FMIN_ZPmI_D = 3556 + + FMIN_ZPmI_H = 3557 + + FMIN_ZPmI_S = 3558 + + FMIN_ZPmZ_D = 3559 + + FMIN_ZPmZ_H = 3560 + + FMIN_ZPmZ_S = 3561 + + FMINv2f32 = 3562 + + FMINv2f64 = 3563 + + FMINv4f16 = 3564 + + FMINv4f32 = 3565 + + FMINv8f16 = 3566 + + FMLAL2lanev4f16 = 3567 + + FMLAL2lanev8f16 = 3568 + + FMLAL2v4f16 = 3569 + + FMLAL2v8f16 = 3570 + + FMLALB_ZZZ = 3571 + + FMLALB_ZZZI = 3572 + + FMLALB_ZZZI_SHH = 3573 + + FMLALB_ZZZ_SHH = 3574 + + FMLALBlanev8f16 = 3575 + + FMLALBv16i8_v8f16 = 3576 + + FMLALLBB_ZZZ = 3577 + + FMLALLBB_ZZZI = 3578 + + FMLALLBBlanev4f32 = 3579 + + FMLALLBBv4f32 = 3580 + + FMLALLBT_ZZZ = 3581 + + FMLALLBT_ZZZI = 3582 + + FMLALLBTlanev4f32 = 3583 + + FMLALLBTv4f32 = 3584 + + FMLALLTB_ZZZ = 3585 + + FMLALLTB_ZZZI = 3586 + + FMLALLTBlanev4f32 = 3587 + + FMLALLTBv4f32 = 3588 + + FMLALLTT_ZZZ = 3589 + + FMLALLTT_ZZZI = 3590 + + FMLALLTTlanev4f32 = 3591 + + FMLALLTTv4f32 = 3592 + + FMLALL_MZZI_BtoS = 3593 + + FMLALL_MZZ_BtoS = 3594 + + FMLALL_VG2_M2Z2Z_BtoS = 3595 + + FMLALL_VG2_M2ZZI_BtoS = 3596 + + FMLALL_VG2_M2ZZ_BtoS = 3597 + + FMLALL_VG4_M4Z4Z_BtoS = 3598 + + FMLALL_VG4_M4ZZI_BtoS = 3599 + + FMLALL_VG4_M4ZZ_BtoS = 3600 + + FMLALT_ZZZ = 3601 + + FMLALT_ZZZI = 3602 + + FMLALT_ZZZI_SHH = 3603 + + FMLALT_ZZZ_SHH = 3604 + + FMLALTlanev8f16 = 3605 + + FMLALTv16i8_v8f16 = 3606 + + FMLAL_MZZI_BtoH = 3607 + + FMLAL_MZZI_HtoS = 3608 + + FMLAL_MZZ_HtoS = 3609 + + FMLAL_VG2_M2Z2Z_BtoH = 3610 + + FMLAL_VG2_M2Z2Z_HtoS = 3611 + + FMLAL_VG2_M2ZZI_BtoH = 3612 + + FMLAL_VG2_M2ZZI_HtoS = 3613 + + FMLAL_VG2_M2ZZ_BtoH = 3614 + + FMLAL_VG2_M2ZZ_HtoS = 3615 + + FMLAL_VG2_MZZ_BtoH = 3616 + + FMLAL_VG4_M4Z4Z_BtoH = 3617 + + FMLAL_VG4_M4Z4Z_HtoS = 3618 + + FMLAL_VG4_M4ZZI_BtoH = 3619 + + FMLAL_VG4_M4ZZI_HtoS = 3620 + + FMLAL_VG4_M4ZZ_BtoH = 3621 + + FMLAL_VG4_M4ZZ_HtoS = 3622 + + FMLALlanev4f16 = 3623 + + FMLALlanev8f16 = 3624 + + FMLALv4f16 = 3625 + + FMLALv8f16 = 3626 + + FMLA_VG2_M2Z2Z_D = 3627 + + FMLA_VG2_M2Z2Z_H = 3628 + + FMLA_VG2_M2Z2Z_S = 3629 + + FMLA_VG2_M2ZZI_D = 3630 + + FMLA_VG2_M2ZZI_H = 3631 + + FMLA_VG2_M2ZZI_S = 3632 + + FMLA_VG2_M2ZZ_D = 3633 + + FMLA_VG2_M2ZZ_H = 3634 + + FMLA_VG2_M2ZZ_S = 3635 + + FMLA_VG4_M4Z4Z_D = 3636 + + FMLA_VG4_M4Z4Z_H = 3637 + + FMLA_VG4_M4Z4Z_S = 3638 + + FMLA_VG4_M4ZZI_D = 3639 + + FMLA_VG4_M4ZZI_H = 3640 + + FMLA_VG4_M4ZZI_S = 3641 + + FMLA_VG4_M4ZZ_D = 3642 + + FMLA_VG4_M4ZZ_H = 3643 + + FMLA_VG4_M4ZZ_S = 3644 + + FMLA_ZPmZZ_D = 3645 + + FMLA_ZPmZZ_H = 3646 + + FMLA_ZPmZZ_S = 3647 + + FMLA_ZZZI_D = 3648 + + FMLA_ZZZI_H = 3649 + + FMLA_ZZZI_S = 3650 + + FMLAv1i16_indexed = 3651 + + FMLAv1i32_indexed = 3652 + + FMLAv1i64_indexed = 3653 + + FMLAv2f32 = 3654 + + FMLAv2f64 = 3655 + + FMLAv2i32_indexed = 3656 + + FMLAv2i64_indexed = 3657 + + FMLAv4f16 = 3658 + + FMLAv4f32 = 3659 + + FMLAv4i16_indexed = 3660 + + FMLAv4i32_indexed = 3661 + + FMLAv8f16 = 3662 + + FMLAv8i16_indexed = 3663 + + FMLLA_ZZZ_HtoS = 3664 + + FMLSL2lanev4f16 = 3665 + + FMLSL2lanev8f16 = 3666 + + FMLSL2v4f16 = 3667 + + FMLSL2v8f16 = 3668 + + FMLSLB_ZZZI_SHH = 3669 + + FMLSLB_ZZZ_SHH = 3670 + + FMLSLT_ZZZI_SHH = 3671 + + FMLSLT_ZZZ_SHH = 3672 + + FMLSL_MZZI_HtoS = 3673 + + FMLSL_MZZ_HtoS = 3674 + + FMLSL_VG2_M2Z2Z_HtoS = 3675 + + FMLSL_VG2_M2ZZI_HtoS = 3676 + + FMLSL_VG2_M2ZZ_HtoS = 3677 + + FMLSL_VG4_M4Z4Z_HtoS = 3678 + + FMLSL_VG4_M4ZZI_HtoS = 3679 + + FMLSL_VG4_M4ZZ_HtoS = 3680 + + FMLSLlanev4f16 = 3681 + + FMLSLlanev8f16 = 3682 + + FMLSLv4f16 = 3683 + + FMLSLv8f16 = 3684 + + FMLS_VG2_M2Z2Z_D = 3685 + + FMLS_VG2_M2Z2Z_H = 3686 + + FMLS_VG2_M2Z2Z_S = 3687 + + FMLS_VG2_M2ZZI_D = 3688 + + FMLS_VG2_M2ZZI_H = 3689 + + FMLS_VG2_M2ZZI_S = 3690 + + FMLS_VG2_M2ZZ_D = 3691 + + FMLS_VG2_M2ZZ_H = 3692 + + FMLS_VG2_M2ZZ_S = 3693 + + FMLS_VG4_M4Z4Z_D = 3694 + + FMLS_VG4_M4Z4Z_H = 3695 + + FMLS_VG4_M4Z4Z_S = 3696 + + FMLS_VG4_M4ZZI_D = 3697 + + FMLS_VG4_M4ZZI_H = 3698 + + FMLS_VG4_M4ZZI_S = 3699 + + FMLS_VG4_M4ZZ_D = 3700 + + FMLS_VG4_M4ZZ_H = 3701 + + FMLS_VG4_M4ZZ_S = 3702 + + FMLS_ZPmZZ_D = 3703 + + FMLS_ZPmZZ_H = 3704 + + FMLS_ZPmZZ_S = 3705 + + FMLS_ZZZI_D = 3706 + + FMLS_ZZZI_H = 3707 + + FMLS_ZZZI_S = 3708 + + FMLSv1i16_indexed = 3709 + + FMLSv1i32_indexed = 3710 + + FMLSv1i64_indexed = 3711 + + FMLSv2f32 = 3712 + + FMLSv2f64 = 3713 + + FMLSv2i32_indexed = 3714 + + FMLSv2i64_indexed = 3715 + + FMLSv4f16 = 3716 + + FMLSv4f32 = 3717 + + FMLSv4i16_indexed = 3718 + + FMLSv4i32_indexed = 3719 + + FMLSv8f16 = 3720 + + FMLSv8i16_indexed = 3721 + + FMMLA_ZZZ_BtoH = 3722 + + FMMLA_ZZZ_BtoS = 3723 + + FMMLA_ZZZ_D = 3724 + + FMMLA_ZZZ_H = 3725 + + FMMLA_ZZZ_S = 3726 + + FMMLAv4f32 = 3727 + + FMMLAv8f16 = 3728 + + FMMLAv8f16_v4f32 = 3729 + + FMMLAv8f16_v8f16 = 3730 + + FMOP4A_M2Z2Z_BtoH = 3731 + + FMOP4A_M2Z2Z_BtoS = 3732 + + FMOP4A_M2Z2Z_D = 3733 + + FMOP4A_M2Z2Z_H = 3734 + + FMOP4A_M2Z2Z_HtoS = 3735 + + FMOP4A_M2Z2Z_S = 3736 + + FMOP4A_M2ZZ_BtoH = 3737 + + FMOP4A_M2ZZ_BtoS = 3738 + + FMOP4A_M2ZZ_D = 3739 + + FMOP4A_M2ZZ_H = 3740 + + FMOP4A_M2ZZ_HtoS = 3741 + + FMOP4A_M2ZZ_S = 3742 + + FMOP4A_MZ2Z_BtoH = 3743 + + FMOP4A_MZ2Z_BtoS = 3744 + + FMOP4A_MZ2Z_D = 3745 + + FMOP4A_MZ2Z_H = 3746 + + FMOP4A_MZ2Z_HtoS = 3747 + + FMOP4A_MZ2Z_S = 3748 + + FMOP4A_MZZ_BtoH = 3749 + + FMOP4A_MZZ_BtoS = 3750 + + FMOP4A_MZZ_D = 3751 + + FMOP4A_MZZ_H = 3752 + + FMOP4A_MZZ_HtoS = 3753 + + FMOP4A_MZZ_S = 3754 + + FMOP4S_M2Z2Z_D = 3755 + + FMOP4S_M2Z2Z_H = 3756 + + FMOP4S_M2Z2Z_HtoS = 3757 + + FMOP4S_M2Z2Z_S = 3758 + + FMOP4S_M2ZZ_D = 3759 + + FMOP4S_M2ZZ_H = 3760 + + FMOP4S_M2ZZ_HtoS = 3761 + + FMOP4S_M2ZZ_S = 3762 + + FMOP4S_MZ2Z_D = 3763 + + FMOP4S_MZ2Z_H = 3764 + + FMOP4S_MZ2Z_HtoS = 3765 + + FMOP4S_MZ2Z_S = 3766 + + FMOP4S_MZZ_D = 3767 + + FMOP4S_MZZ_H = 3768 + + FMOP4S_MZZ_HtoS = 3769 + + FMOP4S_MZZ_S = 3770 + + FMOPAL_MPPZZ = 3771 + + FMOPA_MPPZZ_BtoH = 3772 + + FMOPA_MPPZZ_BtoS = 3773 + + FMOPA_MPPZZ_D = 3774 + + FMOPA_MPPZZ_H = 3775 + + FMOPA_MPPZZ_S = 3776 + + FMOPSL_MPPZZ = 3777 + + FMOPS_MPPZZ_D = 3778 + + FMOPS_MPPZZ_H = 3779 + + FMOPS_MPPZZ_S = 3780 + + FMOVDXHighr = 3781 + + FMOVDXr = 3782 + + FMOVDi = 3783 + + FMOVDr = 3784 + + FMOVHWr = 3785 + + FMOVHXr = 3786 + + FMOVHi = 3787 + + FMOVHr = 3788 + + FMOVSWr = 3789 + + FMOVSi = 3790 + + FMOVSr = 3791 + + FMOVWHr = 3792 + + FMOVWSr = 3793 + + FMOVXDHighr = 3794 + + FMOVXDr = 3795 + + FMOVXHr = 3796 + + FMOVv2f32_ns = 3797 + + FMOVv2f64_ns = 3798 + + FMOVv4f16_ns = 3799 + + FMOVv4f32_ns = 3800 + + FMOVv8f16_ns = 3801 + + FMSB_ZPmZZ_D = 3802 + + FMSB_ZPmZZ_H = 3803 + + FMSB_ZPmZZ_S = 3804 + + FMSUBDrrr = 3805 + + FMSUBHrrr = 3806 + + FMSUBSrrr = 3807 + + FMULDrr = 3808 + + FMULHrr = 3809 + + FMULSrr = 3810 + + FMULX16 = 3811 + + FMULX32 = 3812 + + FMULX64 = 3813 + + FMULX_ZPmZ_D = 3814 + + FMULX_ZPmZ_H = 3815 + + FMULX_ZPmZ_S = 3816 + + FMULXv1i16_indexed = 3817 + + FMULXv1i32_indexed = 3818 + + FMULXv1i64_indexed = 3819 + + FMULXv2f32 = 3820 + + FMULXv2f64 = 3821 + + FMULXv2i32_indexed = 3822 + + FMULXv2i64_indexed = 3823 + + FMULXv4f16 = 3824 + + FMULXv4f32 = 3825 + + FMULXv4i16_indexed = 3826 + + FMULXv4i32_indexed = 3827 + + FMULXv8f16 = 3828 + + FMULXv8i16_indexed = 3829 + + FMUL_2Z2Z_D = 3830 + + FMUL_2Z2Z_H = 3831 + + FMUL_2Z2Z_S = 3832 + + FMUL_2ZZ_D = 3833 + + FMUL_2ZZ_H = 3834 + + FMUL_2ZZ_S = 3835 + + FMUL_4Z4Z_D = 3836 + + FMUL_4Z4Z_H = 3837 + + FMUL_4Z4Z_S = 3838 + + FMUL_4ZZ_D = 3839 + + FMUL_4ZZ_H = 3840 + + FMUL_4ZZ_S = 3841 + + FMUL_ZPmI_D = 3842 + + FMUL_ZPmI_H = 3843 + + FMUL_ZPmI_S = 3844 + + FMUL_ZPmZ_D = 3845 + + FMUL_ZPmZ_H = 3846 + + FMUL_ZPmZ_S = 3847 + + FMUL_ZZZI_D = 3848 + + FMUL_ZZZI_H = 3849 + + FMUL_ZZZI_S = 3850 + + FMUL_ZZZ_D = 3851 + + FMUL_ZZZ_H = 3852 + + FMUL_ZZZ_S = 3853 + + FMULv1i16_indexed = 3854 + + FMULv1i32_indexed = 3855 + + FMULv1i64_indexed = 3856 + + FMULv2f32 = 3857 + + FMULv2f64 = 3858 + + FMULv2i32_indexed = 3859 + + FMULv2i64_indexed = 3860 + + FMULv4f16 = 3861 + + FMULv4f32 = 3862 + + FMULv4i16_indexed = 3863 + + FMULv4i32_indexed = 3864 + + FMULv8f16 = 3865 + + FMULv8i16_indexed = 3866 + + FNEGDr = 3867 + + FNEGHr = 3868 + + FNEGSr = 3869 + + FNEG_ZPmZ_D = 3870 + + FNEG_ZPmZ_H = 3871 + + FNEG_ZPmZ_S = 3872 + + FNEG_ZPzZ_D = 3873 + + FNEG_ZPzZ_H = 3874 + + FNEG_ZPzZ_S = 3875 + + FNEGv2f32 = 3876 + + FNEGv2f64 = 3877 + + FNEGv4f16 = 3878 + + FNEGv4f32 = 3879 + + FNEGv8f16 = 3880 + + FNMADDDrrr = 3881 + + FNMADDHrrr = 3882 + + FNMADDSrrr = 3883 + + FNMAD_ZPmZZ_D = 3884 + + FNMAD_ZPmZZ_H = 3885 + + FNMAD_ZPmZZ_S = 3886 + + FNMLA_ZPmZZ_D = 3887 + + FNMLA_ZPmZZ_H = 3888 + + FNMLA_ZPmZZ_S = 3889 + + FNMLS_ZPmZZ_D = 3890 + + FNMLS_ZPmZZ_H = 3891 + + FNMLS_ZPmZZ_S = 3892 + + FNMSB_ZPmZZ_D = 3893 + + FNMSB_ZPmZZ_H = 3894 + + FNMSB_ZPmZZ_S = 3895 + + FNMSUBDrrr = 3896 + + FNMSUBHrrr = 3897 + + FNMSUBSrrr = 3898 + + FNMULDrr = 3899 + + FNMULHrr = 3900 + + FNMULSrr = 3901 + + FRECPE_ZZ_D = 3902 + + FRECPE_ZZ_H = 3903 + + FRECPE_ZZ_S = 3904 + + FRECPEv1f16 = 3905 + + FRECPEv1i32 = 3906 + + FRECPEv1i64 = 3907 + + FRECPEv2f32 = 3908 + + FRECPEv2f64 = 3909 + + FRECPEv4f16 = 3910 + + FRECPEv4f32 = 3911 + + FRECPEv8f16 = 3912 + + FRECPS16 = 3913 + + FRECPS32 = 3914 + + FRECPS64 = 3915 + + FRECPS_ZZZ_D = 3916 + + FRECPS_ZZZ_H = 3917 + + FRECPS_ZZZ_S = 3918 + + FRECPSv2f32 = 3919 + + FRECPSv2f64 = 3920 + + FRECPSv4f16 = 3921 + + FRECPSv4f32 = 3922 + + FRECPSv8f16 = 3923 + + FRECPX_ZPmZ_D = 3924 + + FRECPX_ZPmZ_H = 3925 + + FRECPX_ZPmZ_S = 3926 + + FRECPX_ZPzZ_D = 3927 + + FRECPX_ZPzZ_H = 3928 + + FRECPX_ZPzZ_S = 3929 + + FRECPXv1f16 = 3930 + + FRECPXv1i32 = 3931 + + FRECPXv1i64 = 3932 + + FRINT32XDr = 3933 + + FRINT32XSr = 3934 + + FRINT32X_ZPmZ_D = 3935 + + FRINT32X_ZPmZ_S = 3936 + + FRINT32X_ZPzZ_D = 3937 + + FRINT32X_ZPzZ_S = 3938 + + FRINT32Xv2f32 = 3939 + + FRINT32Xv2f64 = 3940 + + FRINT32Xv4f32 = 3941 + + FRINT32ZDr = 3942 + + FRINT32ZSr = 3943 + + FRINT32Z_ZPmZ_D = 3944 + + FRINT32Z_ZPmZ_S = 3945 + + FRINT32Z_ZPzZ_D = 3946 + + FRINT32Z_ZPzZ_S = 3947 + + FRINT32Zv2f32 = 3948 + + FRINT32Zv2f64 = 3949 + + FRINT32Zv4f32 = 3950 + + FRINT64XDr = 3951 + + FRINT64XSr = 3952 + + FRINT64X_ZPmZ_D = 3953 + + FRINT64X_ZPmZ_S = 3954 + + FRINT64X_ZPzZ_D = 3955 + + FRINT64X_ZPzZ_S = 3956 + + FRINT64Xv2f32 = 3957 + + FRINT64Xv2f64 = 3958 + + FRINT64Xv4f32 = 3959 + + FRINT64ZDr = 3960 + + FRINT64ZSr = 3961 + + FRINT64Z_ZPmZ_D = 3962 + + FRINT64Z_ZPmZ_S = 3963 + + FRINT64Z_ZPzZ_D = 3964 + + FRINT64Z_ZPzZ_S = 3965 + + FRINT64Zv2f32 = 3966 + + FRINT64Zv2f64 = 3967 + + FRINT64Zv4f32 = 3968 + + FRINTADr = 3969 + + FRINTAHr = 3970 + + FRINTASr = 3971 + + FRINTA_2Z2Z_S = 3972 + + FRINTA_4Z4Z_S = 3973 + + FRINTA_ZPmZ_D = 3974 + + FRINTA_ZPmZ_H = 3975 + + FRINTA_ZPmZ_S = 3976 + + FRINTA_ZPzZ_D = 3977 + + FRINTA_ZPzZ_H = 3978 + + FRINTA_ZPzZ_S = 3979 + + FRINTAv2f32 = 3980 + + FRINTAv2f64 = 3981 + + FRINTAv4f16 = 3982 + + FRINTAv4f32 = 3983 + + FRINTAv8f16 = 3984 + + FRINTIDr = 3985 + + FRINTIHr = 3986 + + FRINTISr = 3987 + + FRINTI_ZPmZ_D = 3988 + + FRINTI_ZPmZ_H = 3989 + + FRINTI_ZPmZ_S = 3990 + + FRINTI_ZPzZ_D = 3991 + + FRINTI_ZPzZ_H = 3992 + + FRINTI_ZPzZ_S = 3993 + + FRINTIv2f32 = 3994 + + FRINTIv2f64 = 3995 + + FRINTIv4f16 = 3996 + + FRINTIv4f32 = 3997 + + FRINTIv8f16 = 3998 + + FRINTMDr = 3999 + + FRINTMHr = 4000 + + FRINTMSr = 4001 + + FRINTM_2Z2Z_S = 4002 + + FRINTM_4Z4Z_S = 4003 + + FRINTM_ZPmZ_D = 4004 + + FRINTM_ZPmZ_H = 4005 + + FRINTM_ZPmZ_S = 4006 + + FRINTM_ZPzZ_D = 4007 + + FRINTM_ZPzZ_H = 4008 + + FRINTM_ZPzZ_S = 4009 + + FRINTMv2f32 = 4010 + + FRINTMv2f64 = 4011 + + FRINTMv4f16 = 4012 + + FRINTMv4f32 = 4013 + + FRINTMv8f16 = 4014 + + FRINTNDr = 4015 + + FRINTNHr = 4016 + + FRINTNSr = 4017 + + FRINTN_2Z2Z_S = 4018 + + FRINTN_4Z4Z_S = 4019 + + FRINTN_ZPmZ_D = 4020 + + FRINTN_ZPmZ_H = 4021 + + FRINTN_ZPmZ_S = 4022 + + FRINTN_ZPzZ_D = 4023 + + FRINTN_ZPzZ_H = 4024 + + FRINTN_ZPzZ_S = 4025 + + FRINTNv2f32 = 4026 + + FRINTNv2f64 = 4027 + + FRINTNv4f16 = 4028 + + FRINTNv4f32 = 4029 + + FRINTNv8f16 = 4030 + + FRINTPDr = 4031 + + FRINTPHr = 4032 + + FRINTPSr = 4033 + + FRINTP_2Z2Z_S = 4034 + + FRINTP_4Z4Z_S = 4035 + + FRINTP_ZPmZ_D = 4036 + + FRINTP_ZPmZ_H = 4037 + + FRINTP_ZPmZ_S = 4038 + + FRINTP_ZPzZ_D = 4039 + + FRINTP_ZPzZ_H = 4040 + + FRINTP_ZPzZ_S = 4041 + + FRINTPv2f32 = 4042 + + FRINTPv2f64 = 4043 + + FRINTPv4f16 = 4044 + + FRINTPv4f32 = 4045 + + FRINTPv8f16 = 4046 + + FRINTXDr = 4047 + + FRINTXHr = 4048 + + FRINTXSr = 4049 + + FRINTX_ZPmZ_D = 4050 + + FRINTX_ZPmZ_H = 4051 + + FRINTX_ZPmZ_S = 4052 + + FRINTX_ZPzZ_D = 4053 + + FRINTX_ZPzZ_H = 4054 + + FRINTX_ZPzZ_S = 4055 + + FRINTXv2f32 = 4056 + + FRINTXv2f64 = 4057 + + FRINTXv4f16 = 4058 + + FRINTXv4f32 = 4059 + + FRINTXv8f16 = 4060 + + FRINTZDr = 4061 + + FRINTZHr = 4062 + + FRINTZSr = 4063 + + FRINTZ_ZPmZ_D = 4064 + + FRINTZ_ZPmZ_H = 4065 + + FRINTZ_ZPmZ_S = 4066 + + FRINTZ_ZPzZ_D = 4067 + + FRINTZ_ZPzZ_H = 4068 + + FRINTZ_ZPzZ_S = 4069 + + FRINTZv2f32 = 4070 + + FRINTZv2f64 = 4071 + + FRINTZv4f16 = 4072 + + FRINTZv4f32 = 4073 + + FRINTZv8f16 = 4074 + + FRSQRTE_ZZ_D = 4075 + + FRSQRTE_ZZ_H = 4076 + + FRSQRTE_ZZ_S = 4077 + + FRSQRTEv1f16 = 4078 + + FRSQRTEv1i32 = 4079 + + FRSQRTEv1i64 = 4080 + + FRSQRTEv2f32 = 4081 + + FRSQRTEv2f64 = 4082 + + FRSQRTEv4f16 = 4083 + + FRSQRTEv4f32 = 4084 + + FRSQRTEv8f16 = 4085 + + FRSQRTS16 = 4086 + + FRSQRTS32 = 4087 + + FRSQRTS64 = 4088 + + FRSQRTS_ZZZ_D = 4089 + + FRSQRTS_ZZZ_H = 4090 + + FRSQRTS_ZZZ_S = 4091 + + FRSQRTSv2f32 = 4092 + + FRSQRTSv2f64 = 4093 + + FRSQRTSv4f16 = 4094 + + FRSQRTSv4f32 = 4095 + + FRSQRTSv8f16 = 4096 + + FSCALE_2Z2Z_D = 4097 + + FSCALE_2Z2Z_H = 4098 + + FSCALE_2Z2Z_S = 4099 + + FSCALE_2ZZ_D = 4100 + + FSCALE_2ZZ_H = 4101 + + FSCALE_2ZZ_S = 4102 + + FSCALE_4Z4Z_D = 4103 + + FSCALE_4Z4Z_H = 4104 + + FSCALE_4Z4Z_S = 4105 + + FSCALE_4ZZ_D = 4106 + + FSCALE_4ZZ_H = 4107 + + FSCALE_4ZZ_S = 4108 + + FSCALE_ZPmZ_D = 4109 + + FSCALE_ZPmZ_H = 4110 + + FSCALE_ZPmZ_S = 4111 + + FSCALEv2f32 = 4112 + + FSCALEv2f64 = 4113 + + FSCALEv4f16 = 4114 + + FSCALEv4f32 = 4115 + + FSCALEv8f16 = 4116 + + FSQRTDr = 4117 + + FSQRTHr = 4118 + + FSQRTSr = 4119 + + FSQRT_ZPZz_D = 4120 + + FSQRT_ZPZz_H = 4121 + + FSQRT_ZPZz_S = 4122 + + FSQRT_ZPmZ_D = 4123 + + FSQRT_ZPmZ_H = 4124 + + FSQRT_ZPmZ_S = 4125 + + FSQRTv2f32 = 4126 + + FSQRTv2f64 = 4127 + + FSQRTv4f16 = 4128 + + FSQRTv4f32 = 4129 + + FSQRTv8f16 = 4130 + + FSUBDrr = 4131 + + FSUBHrr = 4132 + + FSUBR_ZPmI_D = 4133 + + FSUBR_ZPmI_H = 4134 + + FSUBR_ZPmI_S = 4135 + + FSUBR_ZPmZ_D = 4136 + + FSUBR_ZPmZ_H = 4137 + + FSUBR_ZPmZ_S = 4138 + + FSUBSrr = 4139 + + FSUB_VG2_M2Z_D = 4140 + + FSUB_VG2_M2Z_H = 4141 + + FSUB_VG2_M2Z_S = 4142 + + FSUB_VG4_M4Z_D = 4143 + + FSUB_VG4_M4Z_H = 4144 + + FSUB_VG4_M4Z_S = 4145 + + FSUB_ZPmI_D = 4146 + + FSUB_ZPmI_H = 4147 + + FSUB_ZPmI_S = 4148 + + FSUB_ZPmZ_D = 4149 + + FSUB_ZPmZ_H = 4150 + + FSUB_ZPmZ_S = 4151 + + FSUB_ZZZ_D = 4152 + + FSUB_ZZZ_H = 4153 + + FSUB_ZZZ_S = 4154 + + FSUBv2f32 = 4155 + + FSUBv2f64 = 4156 + + FSUBv4f16 = 4157 + + FSUBv4f32 = 4158 + + FSUBv8f16 = 4159 + + FTMAD_ZZI_D = 4160 + + FTMAD_ZZI_H = 4161 + + FTMAD_ZZI_S = 4162 + + FTMOPA_M2ZZZI_BtoH = 4163 + + FTMOPA_M2ZZZI_BtoS = 4164 + + FTMOPA_M2ZZZI_HtoH = 4165 + + FTMOPA_M2ZZZI_HtoS = 4166 + + FTMOPA_M2ZZZI_StoS = 4167 + + FTSMUL_ZZZ_D = 4168 + + FTSMUL_ZZZ_H = 4169 + + FTSMUL_ZZZ_S = 4170 + + FTSSEL_ZZZ_D = 4171 + + FTSSEL_ZZZ_H = 4172 + + FTSSEL_ZZZ_S = 4173 + + FVDOTB_VG4_M2ZZI_BtoS = 4174 + + FVDOTT_VG4_M2ZZI_BtoS = 4175 + + FVDOT_VG2_M2ZZI_BtoH = 4176 + + FVDOT_VG2_M2ZZI_HtoS = 4177 + + GCSPOPCX = 4178 + + GCSPOPM = 4179 + + GCSPOPX = 4180 + + GCSPUSHM = 4181 + + GCSPUSHX = 4182 + + GCSSS1 = 4183 + + GCSSS2 = 4184 + + GCSSTR = 4185 + + GCSSTTR = 4186 + + GLD1B_D = 4187 + + GLD1B_D_IMM = 4188 + + GLD1B_D_SXTW = 4189 + + GLD1B_D_UXTW = 4190 + + GLD1B_S_IMM = 4191 + + GLD1B_S_SXTW = 4192 + + GLD1B_S_UXTW = 4193 + + GLD1D = 4194 + + GLD1D_IMM = 4195 + + GLD1D_SCALED = 4196 + + GLD1D_SXTW = 4197 + + GLD1D_SXTW_SCALED = 4198 + + GLD1D_UXTW = 4199 + + GLD1D_UXTW_SCALED = 4200 + + GLD1H_D = 4201 + + GLD1H_D_IMM = 4202 + + GLD1H_D_SCALED = 4203 + + GLD1H_D_SXTW = 4204 + + GLD1H_D_SXTW_SCALED = 4205 + + GLD1H_D_UXTW = 4206 + + GLD1H_D_UXTW_SCALED = 4207 + + GLD1H_S_IMM = 4208 + + GLD1H_S_SXTW = 4209 + + GLD1H_S_SXTW_SCALED = 4210 + + GLD1H_S_UXTW = 4211 + + GLD1H_S_UXTW_SCALED = 4212 + + GLD1Q = 4213 + + GLD1SB_D = 4214 + + GLD1SB_D_IMM = 4215 + + GLD1SB_D_SXTW = 4216 + + GLD1SB_D_UXTW = 4217 + + GLD1SB_S_IMM = 4218 + + GLD1SB_S_SXTW = 4219 + + GLD1SB_S_UXTW = 4220 + + GLD1SH_D = 4221 + + GLD1SH_D_IMM = 4222 + + GLD1SH_D_SCALED = 4223 + + GLD1SH_D_SXTW = 4224 + + GLD1SH_D_SXTW_SCALED = 4225 + + GLD1SH_D_UXTW = 4226 + + GLD1SH_D_UXTW_SCALED = 4227 + + GLD1SH_S_IMM = 4228 + + GLD1SH_S_SXTW = 4229 + + GLD1SH_S_SXTW_SCALED = 4230 + + GLD1SH_S_UXTW = 4231 + + GLD1SH_S_UXTW_SCALED = 4232 + + GLD1SW_D = 4233 + + GLD1SW_D_IMM = 4234 + + GLD1SW_D_SCALED = 4235 + + GLD1SW_D_SXTW = 4236 + + GLD1SW_D_SXTW_SCALED = 4237 + + GLD1SW_D_UXTW = 4238 + + GLD1SW_D_UXTW_SCALED = 4239 + + GLD1W_D = 4240 + + GLD1W_D_IMM = 4241 + + GLD1W_D_SCALED = 4242 + + GLD1W_D_SXTW = 4243 + + GLD1W_D_SXTW_SCALED = 4244 + + GLD1W_D_UXTW = 4245 + + GLD1W_D_UXTW_SCALED = 4246 + + GLD1W_IMM = 4247 + + GLD1W_SXTW = 4248 + + GLD1W_SXTW_SCALED = 4249 + + GLD1W_UXTW = 4250 + + GLD1W_UXTW_SCALED = 4251 + + GLDFF1B_D = 4252 + + GLDFF1B_D_IMM = 4253 + + GLDFF1B_D_SXTW = 4254 + + GLDFF1B_D_UXTW = 4255 + + GLDFF1B_S_IMM = 4256 + + GLDFF1B_S_SXTW = 4257 + + GLDFF1B_S_UXTW = 4258 + + GLDFF1D = 4259 + + GLDFF1D_IMM = 4260 + + GLDFF1D_SCALED = 4261 + + GLDFF1D_SXTW = 4262 + + GLDFF1D_SXTW_SCALED = 4263 + + GLDFF1D_UXTW = 4264 + + GLDFF1D_UXTW_SCALED = 4265 + + GLDFF1H_D = 4266 + + GLDFF1H_D_IMM = 4267 + + GLDFF1H_D_SCALED = 4268 + + GLDFF1H_D_SXTW = 4269 + + GLDFF1H_D_SXTW_SCALED = 4270 + + GLDFF1H_D_UXTW = 4271 + + GLDFF1H_D_UXTW_SCALED = 4272 + + GLDFF1H_S_IMM = 4273 + + GLDFF1H_S_SXTW = 4274 + + GLDFF1H_S_SXTW_SCALED = 4275 + + GLDFF1H_S_UXTW = 4276 + + GLDFF1H_S_UXTW_SCALED = 4277 + + GLDFF1SB_D = 4278 + + GLDFF1SB_D_IMM = 4279 + + GLDFF1SB_D_SXTW = 4280 + + GLDFF1SB_D_UXTW = 4281 + + GLDFF1SB_S_IMM = 4282 + + GLDFF1SB_S_SXTW = 4283 + + GLDFF1SB_S_UXTW = 4284 + + GLDFF1SH_D = 4285 + + GLDFF1SH_D_IMM = 4286 + + GLDFF1SH_D_SCALED = 4287 + + GLDFF1SH_D_SXTW = 4288 + + GLDFF1SH_D_SXTW_SCALED = 4289 + + GLDFF1SH_D_UXTW = 4290 + + GLDFF1SH_D_UXTW_SCALED = 4291 + + GLDFF1SH_S_IMM = 4292 + + GLDFF1SH_S_SXTW = 4293 + + GLDFF1SH_S_SXTW_SCALED = 4294 + + GLDFF1SH_S_UXTW = 4295 + + GLDFF1SH_S_UXTW_SCALED = 4296 + + GLDFF1SW_D = 4297 + + GLDFF1SW_D_IMM = 4298 + + GLDFF1SW_D_SCALED = 4299 + + GLDFF1SW_D_SXTW = 4300 + + GLDFF1SW_D_SXTW_SCALED = 4301 + + GLDFF1SW_D_UXTW = 4302 + + GLDFF1SW_D_UXTW_SCALED = 4303 + + GLDFF1W_D = 4304 + + GLDFF1W_D_IMM = 4305 + + GLDFF1W_D_SCALED = 4306 + + GLDFF1W_D_SXTW = 4307 + + GLDFF1W_D_SXTW_SCALED = 4308 + + GLDFF1W_D_UXTW = 4309 + + GLDFF1W_D_UXTW_SCALED = 4310 + + GLDFF1W_IMM = 4311 + + GLDFF1W_SXTW = 4312 + + GLDFF1W_SXTW_SCALED = 4313 + + GLDFF1W_UXTW = 4314 + + GLDFF1W_UXTW_SCALED = 4315 + + GMI = 4316 + + HINT = 4317 + + HISTCNT_ZPzZZ_D = 4318 + + HISTCNT_ZPzZZ_S = 4319 + + HISTSEG_ZZZ = 4320 + + HLT = 4321 + + HVC = 4322 + + INCB_XPiI = 4323 + + INCD_XPiI = 4324 + + INCD_ZPiI = 4325 + + INCH_XPiI = 4326 + + INCH_ZPiI = 4327 + + INCP_XP_B = 4328 + + INCP_XP_D = 4329 + + INCP_XP_H = 4330 + + INCP_XP_S = 4331 + + INCP_ZP_D = 4332 + + INCP_ZP_H = 4333 + + INCP_ZP_S = 4334 + + INCW_XPiI = 4335 + + INCW_ZPiI = 4336 + + INDEX_II_B = 4337 + + INDEX_II_D = 4338 + + INDEX_II_H = 4339 + + INDEX_II_S = 4340 + + INDEX_IR_B = 4341 + + INDEX_IR_D = 4342 + + INDEX_IR_H = 4343 + + INDEX_IR_S = 4344 + + INDEX_RI_B = 4345 + + INDEX_RI_D = 4346 + + INDEX_RI_H = 4347 + + INDEX_RI_S = 4348 + + INDEX_RR_B = 4349 + + INDEX_RR_D = 4350 + + INDEX_RR_H = 4351 + + INDEX_RR_S = 4352 + + INSERT_MXIPZ_H_B = 4353 + + INSERT_MXIPZ_H_D = 4354 + + INSERT_MXIPZ_H_H = 4355 + + INSERT_MXIPZ_H_Q = 4356 + + INSERT_MXIPZ_H_S = 4357 + + INSERT_MXIPZ_V_B = 4358 + + INSERT_MXIPZ_V_D = 4359 + + INSERT_MXIPZ_V_H = 4360 + + INSERT_MXIPZ_V_Q = 4361 + + INSERT_MXIPZ_V_S = 4362 + + INSR_ZR_B = 4363 + + INSR_ZR_D = 4364 + + INSR_ZR_H = 4365 + + INSR_ZR_S = 4366 + + INSR_ZV_B = 4367 + + INSR_ZV_D = 4368 + + INSR_ZV_H = 4369 + + INSR_ZV_S = 4370 + + INSvi16gpr = 4371 + + INSvi16lane = 4372 + + INSvi32gpr = 4373 + + INSvi32lane = 4374 + + INSvi64gpr = 4375 + + INSvi64lane = 4376 + + INSvi8gpr = 4377 + + INSvi8lane = 4378 + + IRG = 4379 + + ISB = 4380 + + LASTA_RPZ_B = 4381 + + LASTA_RPZ_D = 4382 + + LASTA_RPZ_H = 4383 + + LASTA_RPZ_S = 4384 + + LASTA_VPZ_B = 4385 + + LASTA_VPZ_D = 4386 + + LASTA_VPZ_H = 4387 + + LASTA_VPZ_S = 4388 + + LASTB_RPZ_B = 4389 + + LASTB_RPZ_D = 4390 + + LASTB_RPZ_H = 4391 + + LASTB_RPZ_S = 4392 + + LASTB_VPZ_B = 4393 + + LASTB_VPZ_D = 4394 + + LASTB_VPZ_H = 4395 + + LASTB_VPZ_S = 4396 + + LASTP_XPP_B = 4397 + + LASTP_XPP_D = 4398 + + LASTP_XPP_H = 4399 + + LASTP_XPP_S = 4400 + + LD1B = 4401 + + LD1B_2Z = 4402 + + LD1B_2Z_IMM = 4403 + + LD1B_2Z_STRIDED = 4404 + + LD1B_2Z_STRIDED_IMM = 4405 + + LD1B_4Z = 4406 + + LD1B_4Z_IMM = 4407 + + LD1B_4Z_STRIDED = 4408 + + LD1B_4Z_STRIDED_IMM = 4409 + + LD1B_D = 4410 + + LD1B_D_IMM = 4411 + + LD1B_H = 4412 + + LD1B_H_IMM = 4413 + + LD1B_IMM = 4414 + + LD1B_S = 4415 + + LD1B_S_IMM = 4416 + + LD1D = 4417 + + LD1D_2Z = 4418 + + LD1D_2Z_IMM = 4419 + + LD1D_2Z_STRIDED = 4420 + + LD1D_2Z_STRIDED_IMM = 4421 + + LD1D_4Z = 4422 + + LD1D_4Z_IMM = 4423 + + LD1D_4Z_STRIDED = 4424 + + LD1D_4Z_STRIDED_IMM = 4425 + + LD1D_IMM = 4426 + + LD1D_Q = 4427 + + LD1D_Q_IMM = 4428 + + LD1Fourv16b = 4429 + + LD1Fourv16b_POST = 4430 + + LD1Fourv1d = 4431 + + LD1Fourv1d_POST = 4432 + + LD1Fourv2d = 4433 + + LD1Fourv2d_POST = 4434 + + LD1Fourv2s = 4435 + + LD1Fourv2s_POST = 4436 + + LD1Fourv4h = 4437 + + LD1Fourv4h_POST = 4438 + + LD1Fourv4s = 4439 + + LD1Fourv4s_POST = 4440 + + LD1Fourv8b = 4441 + + LD1Fourv8b_POST = 4442 + + LD1Fourv8h = 4443 + + LD1Fourv8h_POST = 4444 + + LD1H = 4445 + + LD1H_2Z = 4446 + + LD1H_2Z_IMM = 4447 + + LD1H_2Z_STRIDED = 4448 + + LD1H_2Z_STRIDED_IMM = 4449 + + LD1H_4Z = 4450 + + LD1H_4Z_IMM = 4451 + + LD1H_4Z_STRIDED = 4452 + + LD1H_4Z_STRIDED_IMM = 4453 + + LD1H_D = 4454 + + LD1H_D_IMM = 4455 + + LD1H_IMM = 4456 + + LD1H_S = 4457 + + LD1H_S_IMM = 4458 + + LD1Onev16b = 4459 + + LD1Onev16b_POST = 4460 + + LD1Onev1d = 4461 + + LD1Onev1d_POST = 4462 + + LD1Onev2d = 4463 + + LD1Onev2d_POST = 4464 + + LD1Onev2s = 4465 + + LD1Onev2s_POST = 4466 + + LD1Onev4h = 4467 + + LD1Onev4h_POST = 4468 + + LD1Onev4s = 4469 + + LD1Onev4s_POST = 4470 + + LD1Onev8b = 4471 + + LD1Onev8b_POST = 4472 + + LD1Onev8h = 4473 + + LD1Onev8h_POST = 4474 + + LD1RB_D_IMM = 4475 + + LD1RB_H_IMM = 4476 + + LD1RB_IMM = 4477 + + LD1RB_S_IMM = 4478 + + LD1RD_IMM = 4479 + + LD1RH_D_IMM = 4480 + + LD1RH_IMM = 4481 + + LD1RH_S_IMM = 4482 + + LD1RO_B = 4483 + + LD1RO_B_IMM = 4484 + + LD1RO_D = 4485 + + LD1RO_D_IMM = 4486 + + LD1RO_H = 4487 + + LD1RO_H_IMM = 4488 + + LD1RO_W = 4489 + + LD1RO_W_IMM = 4490 + + LD1RQ_B = 4491 + + LD1RQ_B_IMM = 4492 + + LD1RQ_D = 4493 + + LD1RQ_D_IMM = 4494 + + LD1RQ_H = 4495 + + LD1RQ_H_IMM = 4496 + + LD1RQ_W = 4497 + + LD1RQ_W_IMM = 4498 + + LD1RSB_D_IMM = 4499 + + LD1RSB_H_IMM = 4500 + + LD1RSB_S_IMM = 4501 + + LD1RSH_D_IMM = 4502 + + LD1RSH_S_IMM = 4503 + + LD1RSW_IMM = 4504 + + LD1RW_D_IMM = 4505 + + LD1RW_IMM = 4506 + + LD1Rv16b = 4507 + + LD1Rv16b_POST = 4508 + + LD1Rv1d = 4509 + + LD1Rv1d_POST = 4510 + + LD1Rv2d = 4511 + + LD1Rv2d_POST = 4512 + + LD1Rv2s = 4513 + + LD1Rv2s_POST = 4514 + + LD1Rv4h = 4515 + + LD1Rv4h_POST = 4516 + + LD1Rv4s = 4517 + + LD1Rv4s_POST = 4518 + + LD1Rv8b = 4519 + + LD1Rv8b_POST = 4520 + + LD1Rv8h = 4521 + + LD1Rv8h_POST = 4522 + + LD1SB_D = 4523 + + LD1SB_D_IMM = 4524 + + LD1SB_H = 4525 + + LD1SB_H_IMM = 4526 + + LD1SB_S = 4527 + + LD1SB_S_IMM = 4528 + + LD1SH_D = 4529 + + LD1SH_D_IMM = 4530 + + LD1SH_S = 4531 + + LD1SH_S_IMM = 4532 + + LD1SW_D = 4533 + + LD1SW_D_IMM = 4534 + + LD1Threev16b = 4535 + + LD1Threev16b_POST = 4536 + + LD1Threev1d = 4537 + + LD1Threev1d_POST = 4538 + + LD1Threev2d = 4539 + + LD1Threev2d_POST = 4540 + + LD1Threev2s = 4541 + + LD1Threev2s_POST = 4542 + + LD1Threev4h = 4543 + + LD1Threev4h_POST = 4544 + + LD1Threev4s = 4545 + + LD1Threev4s_POST = 4546 + + LD1Threev8b = 4547 + + LD1Threev8b_POST = 4548 + + LD1Threev8h = 4549 + + LD1Threev8h_POST = 4550 + + LD1Twov16b = 4551 + + LD1Twov16b_POST = 4552 + + LD1Twov1d = 4553 + + LD1Twov1d_POST = 4554 + + LD1Twov2d = 4555 + + LD1Twov2d_POST = 4556 + + LD1Twov2s = 4557 + + LD1Twov2s_POST = 4558 + + LD1Twov4h = 4559 + + LD1Twov4h_POST = 4560 + + LD1Twov4s = 4561 + + LD1Twov4s_POST = 4562 + + LD1Twov8b = 4563 + + LD1Twov8b_POST = 4564 + + LD1Twov8h = 4565 + + LD1Twov8h_POST = 4566 + + LD1W = 4567 + + LD1W_2Z = 4568 + + LD1W_2Z_IMM = 4569 + + LD1W_2Z_STRIDED = 4570 + + LD1W_2Z_STRIDED_IMM = 4571 + + LD1W_4Z = 4572 + + LD1W_4Z_IMM = 4573 + + LD1W_4Z_STRIDED = 4574 + + LD1W_4Z_STRIDED_IMM = 4575 + + LD1W_D = 4576 + + LD1W_D_IMM = 4577 + + LD1W_IMM = 4578 + + LD1W_Q = 4579 + + LD1W_Q_IMM = 4580 + + LD1_MXIPXX_H_B = 4581 + + LD1_MXIPXX_H_D = 4582 + + LD1_MXIPXX_H_H = 4583 + + LD1_MXIPXX_H_Q = 4584 + + LD1_MXIPXX_H_S = 4585 + + LD1_MXIPXX_V_B = 4586 + + LD1_MXIPXX_V_D = 4587 + + LD1_MXIPXX_V_H = 4588 + + LD1_MXIPXX_V_Q = 4589 + + LD1_MXIPXX_V_S = 4590 + + LD1i16 = 4591 + + LD1i16_POST = 4592 + + LD1i32 = 4593 + + LD1i32_POST = 4594 + + LD1i64 = 4595 + + LD1i64_POST = 4596 + + LD1i8 = 4597 + + LD1i8_POST = 4598 + + LD2B = 4599 + + LD2B_IMM = 4600 + + LD2D = 4601 + + LD2D_IMM = 4602 + + LD2H = 4603 + + LD2H_IMM = 4604 + + LD2Q = 4605 + + LD2Q_IMM = 4606 + + LD2Rv16b = 4607 + + LD2Rv16b_POST = 4608 + + LD2Rv1d = 4609 + + LD2Rv1d_POST = 4610 + + LD2Rv2d = 4611 + + LD2Rv2d_POST = 4612 + + LD2Rv2s = 4613 + + LD2Rv2s_POST = 4614 + + LD2Rv4h = 4615 + + LD2Rv4h_POST = 4616 + + LD2Rv4s = 4617 + + LD2Rv4s_POST = 4618 + + LD2Rv8b = 4619 + + LD2Rv8b_POST = 4620 + + LD2Rv8h = 4621 + + LD2Rv8h_POST = 4622 + + LD2Twov16b = 4623 + + LD2Twov16b_POST = 4624 + + LD2Twov2d = 4625 + + LD2Twov2d_POST = 4626 + + LD2Twov2s = 4627 + + LD2Twov2s_POST = 4628 + + LD2Twov4h = 4629 + + LD2Twov4h_POST = 4630 + + LD2Twov4s = 4631 + + LD2Twov4s_POST = 4632 + + LD2Twov8b = 4633 + + LD2Twov8b_POST = 4634 + + LD2Twov8h = 4635 + + LD2Twov8h_POST = 4636 + + LD2W = 4637 + + LD2W_IMM = 4638 + + LD2i16 = 4639 + + LD2i16_POST = 4640 + + LD2i32 = 4641 + + LD2i32_POST = 4642 + + LD2i64 = 4643 + + LD2i64_POST = 4644 + + LD2i8 = 4645 + + LD2i8_POST = 4646 + + LD3B = 4647 + + LD3B_IMM = 4648 + + LD3D = 4649 + + LD3D_IMM = 4650 + + LD3H = 4651 + + LD3H_IMM = 4652 + + LD3Q = 4653 + + LD3Q_IMM = 4654 + + LD3Rv16b = 4655 + + LD3Rv16b_POST = 4656 + + LD3Rv1d = 4657 + + LD3Rv1d_POST = 4658 + + LD3Rv2d = 4659 + + LD3Rv2d_POST = 4660 + + LD3Rv2s = 4661 + + LD3Rv2s_POST = 4662 + + LD3Rv4h = 4663 + + LD3Rv4h_POST = 4664 + + LD3Rv4s = 4665 + + LD3Rv4s_POST = 4666 + + LD3Rv8b = 4667 + + LD3Rv8b_POST = 4668 + + LD3Rv8h = 4669 + + LD3Rv8h_POST = 4670 + + LD3Threev16b = 4671 + + LD3Threev16b_POST = 4672 + + LD3Threev2d = 4673 + + LD3Threev2d_POST = 4674 + + LD3Threev2s = 4675 + + LD3Threev2s_POST = 4676 + + LD3Threev4h = 4677 + + LD3Threev4h_POST = 4678 + + LD3Threev4s = 4679 + + LD3Threev4s_POST = 4680 + + LD3Threev8b = 4681 + + LD3Threev8b_POST = 4682 + + LD3Threev8h = 4683 + + LD3Threev8h_POST = 4684 + + LD3W = 4685 + + LD3W_IMM = 4686 + + LD3i16 = 4687 + + LD3i16_POST = 4688 + + LD3i32 = 4689 + + LD3i32_POST = 4690 + + LD3i64 = 4691 + + LD3i64_POST = 4692 + + LD3i8 = 4693 + + LD3i8_POST = 4694 + + LD4B = 4695 + + LD4B_IMM = 4696 + + LD4D = 4697 + + LD4D_IMM = 4698 + + LD4Fourv16b = 4699 + + LD4Fourv16b_POST = 4700 + + LD4Fourv2d = 4701 + + LD4Fourv2d_POST = 4702 + + LD4Fourv2s = 4703 + + LD4Fourv2s_POST = 4704 + + LD4Fourv4h = 4705 + + LD4Fourv4h_POST = 4706 + + LD4Fourv4s = 4707 + + LD4Fourv4s_POST = 4708 + + LD4Fourv8b = 4709 + + LD4Fourv8b_POST = 4710 + + LD4Fourv8h = 4711 + + LD4Fourv8h_POST = 4712 + + LD4H = 4713 + + LD4H_IMM = 4714 + + LD4Q = 4715 + + LD4Q_IMM = 4716 + + LD4Rv16b = 4717 + + LD4Rv16b_POST = 4718 + + LD4Rv1d = 4719 + + LD4Rv1d_POST = 4720 + + LD4Rv2d = 4721 + + LD4Rv2d_POST = 4722 + + LD4Rv2s = 4723 + + LD4Rv2s_POST = 4724 + + LD4Rv4h = 4725 + + LD4Rv4h_POST = 4726 + + LD4Rv4s = 4727 + + LD4Rv4s_POST = 4728 + + LD4Rv8b = 4729 + + LD4Rv8b_POST = 4730 + + LD4Rv8h = 4731 + + LD4Rv8h_POST = 4732 + + LD4W = 4733 + + LD4W_IMM = 4734 + + LD4i16 = 4735 + + LD4i16_POST = 4736 + + LD4i32 = 4737 + + LD4i32_POST = 4738 + + LD4i64 = 4739 + + LD4i64_POST = 4740 + + LD4i8 = 4741 + + LD4i8_POST = 4742 + + LD64B = 4743 + + LDADDAB = 4744 + + LDADDAH = 4745 + + LDADDALB = 4746 + + LDADDALH = 4747 + + LDADDALW = 4748 + + LDADDALX = 4749 + + LDADDAW = 4750 + + LDADDAX = 4751 + + LDADDB = 4752 + + LDADDH = 4753 + + LDADDLB = 4754 + + LDADDLH = 4755 + + LDADDLW = 4756 + + LDADDLX = 4757 + + LDADDW = 4758 + + LDADDX = 4759 + + LDAP1 = 4760 + + LDAPPi = 4761 + + LDAPRB = 4762 + + LDAPRH = 4763 + + LDAPRW = 4764 + + LDAPRWpost = 4765 + + LDAPRX = 4766 + + LDAPRXpost = 4767 + + LDAPURBi = 4768 + + LDAPURHi = 4769 + + LDAPURSBWi = 4770 + + LDAPURSBXi = 4771 + + LDAPURSHWi = 4772 + + LDAPURSHXi = 4773 + + LDAPURSWi = 4774 + + LDAPURXi = 4775 + + LDAPURbi = 4776 + + LDAPURdi = 4777 + + LDAPURhi = 4778 + + LDAPURi = 4779 + + LDAPURqi = 4780 + + LDAPURsi = 4781 + + LDAPi = 4782 + + LDARB = 4783 + + LDARH = 4784 + + LDARW = 4785 + + LDARX = 4786 + + LDATXRW = 4787 + + LDATXRX = 4788 + + LDAXPW = 4789 + + LDAXPX = 4790 + + LDAXRB = 4791 + + LDAXRH = 4792 + + LDAXRW = 4793 + + LDAXRX = 4794 + + LDBFADD = 4795 + + LDBFADDA = 4796 + + LDBFADDAL = 4797 + + LDBFADDL = 4798 + + LDBFMAX = 4799 + + LDBFMAXA = 4800 + + LDBFMAXAL = 4801 + + LDBFMAXL = 4802 + + LDBFMAXNM = 4803 + + LDBFMAXNMA = 4804 + + LDBFMAXNMAL = 4805 + + LDBFMAXNML = 4806 + + LDBFMIN = 4807 + + LDBFMINA = 4808 + + LDBFMINAL = 4809 + + LDBFMINL = 4810 + + LDBFMINNM = 4811 + + LDBFMINNMA = 4812 + + LDBFMINNMAL = 4813 + + LDBFMINNML = 4814 + + LDCLRAB = 4815 + + LDCLRAH = 4816 + + LDCLRALB = 4817 + + LDCLRALH = 4818 + + LDCLRALW = 4819 + + LDCLRALX = 4820 + + LDCLRAW = 4821 + + LDCLRAX = 4822 + + LDCLRB = 4823 + + LDCLRH = 4824 + + LDCLRLB = 4825 + + LDCLRLH = 4826 + + LDCLRLW = 4827 + + LDCLRLX = 4828 + + LDCLRP = 4829 + + LDCLRPA = 4830 + + LDCLRPAL = 4831 + + LDCLRPL = 4832 + + LDCLRW = 4833 + + LDCLRX = 4834 + + LDEORAB = 4835 + + LDEORAH = 4836 + + LDEORALB = 4837 + + LDEORALH = 4838 + + LDEORALW = 4839 + + LDEORALX = 4840 + + LDEORAW = 4841 + + LDEORAX = 4842 + + LDEORB = 4843 + + LDEORH = 4844 + + LDEORLB = 4845 + + LDEORLH = 4846 + + LDEORLW = 4847 + + LDEORLX = 4848 + + LDEORW = 4849 + + LDEORX = 4850 + + LDFADDAD = 4851 + + LDFADDAH = 4852 + + LDFADDALD = 4853 + + LDFADDALH = 4854 + + LDFADDALS = 4855 + + LDFADDAS = 4856 + + LDFADDD = 4857 + + LDFADDH = 4858 + + LDFADDLD = 4859 + + LDFADDLH = 4860 + + LDFADDLS = 4861 + + LDFADDS = 4862 + + LDFF1B = 4863 + + LDFF1B_D = 4864 + + LDFF1B_H = 4865 + + LDFF1B_S = 4866 + + LDFF1D = 4867 + + LDFF1H = 4868 + + LDFF1H_D = 4869 + + LDFF1H_S = 4870 + + LDFF1SB_D = 4871 + + LDFF1SB_H = 4872 + + LDFF1SB_S = 4873 + + LDFF1SH_D = 4874 + + LDFF1SH_S = 4875 + + LDFF1SW_D = 4876 + + LDFF1W = 4877 + + LDFF1W_D = 4878 + + LDFMAXAD = 4879 + + LDFMAXAH = 4880 + + LDFMAXALD = 4881 + + LDFMAXALH = 4882 + + LDFMAXALS = 4883 + + LDFMAXAS = 4884 + + LDFMAXD = 4885 + + LDFMAXH = 4886 + + LDFMAXLD = 4887 + + LDFMAXLH = 4888 + + LDFMAXLS = 4889 + + LDFMAXNMAD = 4890 + + LDFMAXNMAH = 4891 + + LDFMAXNMALD = 4892 + + LDFMAXNMALH = 4893 + + LDFMAXNMALS = 4894 + + LDFMAXNMAS = 4895 + + LDFMAXNMD = 4896 + + LDFMAXNMH = 4897 + + LDFMAXNMLD = 4898 + + LDFMAXNMLH = 4899 + + LDFMAXNMLS = 4900 + + LDFMAXNMS = 4901 + + LDFMAXS = 4902 + + LDFMINAD = 4903 + + LDFMINAH = 4904 + + LDFMINALD = 4905 + + LDFMINALH = 4906 + + LDFMINALS = 4907 + + LDFMINAS = 4908 + + LDFMIND = 4909 + + LDFMINH = 4910 + + LDFMINLD = 4911 + + LDFMINLH = 4912 + + LDFMINLS = 4913 + + LDFMINNMAD = 4914 + + LDFMINNMAH = 4915 + + LDFMINNMALD = 4916 + + LDFMINNMALH = 4917 + + LDFMINNMALS = 4918 + + LDFMINNMAS = 4919 + + LDFMINNMD = 4920 + + LDFMINNMH = 4921 + + LDFMINNMLD = 4922 + + LDFMINNMLH = 4923 + + LDFMINNMLS = 4924 + + LDFMINNMS = 4925 + + LDFMINS = 4926 + + LDG = 4927 + + LDGM = 4928 + + LDIAPPW = 4929 + + LDIAPPWpost = 4930 + + LDIAPPX = 4931 + + LDIAPPXpost = 4932 + + LDLARB = 4933 + + LDLARH = 4934 + + LDLARW = 4935 + + LDLARX = 4936 + + LDNF1B_D_IMM = 4937 + + LDNF1B_H_IMM = 4938 + + LDNF1B_IMM = 4939 + + LDNF1B_S_IMM = 4940 + + LDNF1D_IMM = 4941 + + LDNF1H_D_IMM = 4942 + + LDNF1H_IMM = 4943 + + LDNF1H_S_IMM = 4944 + + LDNF1SB_D_IMM = 4945 + + LDNF1SB_H_IMM = 4946 + + LDNF1SB_S_IMM = 4947 + + LDNF1SH_D_IMM = 4948 + + LDNF1SH_S_IMM = 4949 + + LDNF1SW_D_IMM = 4950 + + LDNF1W_D_IMM = 4951 + + LDNF1W_IMM = 4952 + + LDNPDi = 4953 + + LDNPQi = 4954 + + LDNPSi = 4955 + + LDNPWi = 4956 + + LDNPXi = 4957 + + LDNT1B_2Z = 4958 + + LDNT1B_2Z_IMM = 4959 + + LDNT1B_2Z_STRIDED = 4960 + + LDNT1B_2Z_STRIDED_IMM = 4961 + + LDNT1B_4Z = 4962 + + LDNT1B_4Z_IMM = 4963 + + LDNT1B_4Z_STRIDED = 4964 + + LDNT1B_4Z_STRIDED_IMM = 4965 + + LDNT1B_ZRI = 4966 + + LDNT1B_ZRR = 4967 + + LDNT1B_ZZR_D = 4968 + + LDNT1B_ZZR_S = 4969 + + LDNT1D_2Z = 4970 + + LDNT1D_2Z_IMM = 4971 + + LDNT1D_2Z_STRIDED = 4972 + + LDNT1D_2Z_STRIDED_IMM = 4973 + + LDNT1D_4Z = 4974 + + LDNT1D_4Z_IMM = 4975 + + LDNT1D_4Z_STRIDED = 4976 + + LDNT1D_4Z_STRIDED_IMM = 4977 + + LDNT1D_ZRI = 4978 + + LDNT1D_ZRR = 4979 + + LDNT1D_ZZR_D = 4980 + + LDNT1H_2Z = 4981 + + LDNT1H_2Z_IMM = 4982 + + LDNT1H_2Z_STRIDED = 4983 + + LDNT1H_2Z_STRIDED_IMM = 4984 + + LDNT1H_4Z = 4985 + + LDNT1H_4Z_IMM = 4986 + + LDNT1H_4Z_STRIDED = 4987 + + LDNT1H_4Z_STRIDED_IMM = 4988 + + LDNT1H_ZRI = 4989 + + LDNT1H_ZRR = 4990 + + LDNT1H_ZZR_D = 4991 + + LDNT1H_ZZR_S = 4992 + + LDNT1SB_ZZR_D = 4993 + + LDNT1SB_ZZR_S = 4994 + + LDNT1SH_ZZR_D = 4995 + + LDNT1SH_ZZR_S = 4996 + + LDNT1SW_ZZR_D = 4997 + + LDNT1W_2Z = 4998 + + LDNT1W_2Z_IMM = 4999 + + LDNT1W_2Z_STRIDED = 5000 + + LDNT1W_2Z_STRIDED_IMM = 5001 + + LDNT1W_4Z = 5002 + + LDNT1W_4Z_IMM = 5003 + + LDNT1W_4Z_STRIDED = 5004 + + LDNT1W_4Z_STRIDED_IMM = 5005 + + LDNT1W_ZRI = 5006 + + LDNT1W_ZRR = 5007 + + LDNT1W_ZZR_D = 5008 + + LDNT1W_ZZR_S = 5009 + + LDPDi = 5010 + + LDPDpost = 5011 + + LDPDpre = 5012 + + LDPQi = 5013 + + LDPQpost = 5014 + + LDPQpre = 5015 + + LDPSWi = 5016 + + LDPSWpost = 5017 + + LDPSWpre = 5018 + + LDPSi = 5019 + + LDPSpost = 5020 + + LDPSpre = 5021 + + LDPWi = 5022 + + LDPWpost = 5023 + + LDPWpre = 5024 + + LDPXi = 5025 + + LDPXpost = 5026 + + LDPXpre = 5027 + + LDRAAindexed = 5028 + + LDRAAwriteback = 5029 + + LDRABindexed = 5030 + + LDRABwriteback = 5031 + + LDRBBpost = 5032 + + LDRBBpre = 5033 + + LDRBBroW = 5034 + + LDRBBroX = 5035 + + LDRBBui = 5036 + + LDRBpost = 5037 + + LDRBpre = 5038 + + LDRBroW = 5039 + + LDRBroX = 5040 + + LDRBui = 5041 + + LDRDl = 5042 + + LDRDpost = 5043 + + LDRDpre = 5044 + + LDRDroW = 5045 + + LDRDroX = 5046 + + LDRDui = 5047 + + LDRHHpost = 5048 + + LDRHHpre = 5049 + + LDRHHroW = 5050 + + LDRHHroX = 5051 + + LDRHHui = 5052 + + LDRHpost = 5053 + + LDRHpre = 5054 + + LDRHroW = 5055 + + LDRHroX = 5056 + + LDRHui = 5057 + + LDRQl = 5058 + + LDRQpost = 5059 + + LDRQpre = 5060 + + LDRQroW = 5061 + + LDRQroX = 5062 + + LDRQui = 5063 + + LDRSBWpost = 5064 + + LDRSBWpre = 5065 + + LDRSBWroW = 5066 + + LDRSBWroX = 5067 + + LDRSBWui = 5068 + + LDRSBXpost = 5069 + + LDRSBXpre = 5070 + + LDRSBXroW = 5071 + + LDRSBXroX = 5072 + + LDRSBXui = 5073 + + LDRSHWpost = 5074 + + LDRSHWpre = 5075 + + LDRSHWroW = 5076 + + LDRSHWroX = 5077 + + LDRSHWui = 5078 + + LDRSHXpost = 5079 + + LDRSHXpre = 5080 + + LDRSHXroW = 5081 + + LDRSHXroX = 5082 + + LDRSHXui = 5083 + + LDRSWl = 5084 + + LDRSWpost = 5085 + + LDRSWpre = 5086 + + LDRSWroW = 5087 + + LDRSWroX = 5088 + + LDRSWui = 5089 + + LDRSl = 5090 + + LDRSpost = 5091 + + LDRSpre = 5092 + + LDRSroW = 5093 + + LDRSroX = 5094 + + LDRSui = 5095 + + LDRWl = 5096 + + LDRWpost = 5097 + + LDRWpre = 5098 + + LDRWroW = 5099 + + LDRWroX = 5100 + + LDRWui = 5101 + + LDRXl = 5102 + + LDRXpost = 5103 + + LDRXpre = 5104 + + LDRXroW = 5105 + + LDRXroX = 5106 + + LDRXui = 5107 + + LDR_PXI = 5108 + + LDR_TX = 5109 + + LDR_ZA = 5110 + + LDR_ZXI = 5111 + + LDSETAB = 5112 + + LDSETAH = 5113 + + LDSETALB = 5114 + + LDSETALH = 5115 + + LDSETALW = 5116 + + LDSETALX = 5117 + + LDSETAW = 5118 + + LDSETAX = 5119 + + LDSETB = 5120 + + LDSETH = 5121 + + LDSETLB = 5122 + + LDSETLH = 5123 + + LDSETLW = 5124 + + LDSETLX = 5125 + + LDSETP = 5126 + + LDSETPA = 5127 + + LDSETPAL = 5128 + + LDSETPL = 5129 + + LDSETW = 5130 + + LDSETX = 5131 + + LDSMAXAB = 5132 + + LDSMAXAH = 5133 + + LDSMAXALB = 5134 + + LDSMAXALH = 5135 + + LDSMAXALW = 5136 + + LDSMAXALX = 5137 + + LDSMAXAW = 5138 + + LDSMAXAX = 5139 + + LDSMAXB = 5140 + + LDSMAXH = 5141 + + LDSMAXLB = 5142 + + LDSMAXLH = 5143 + + LDSMAXLW = 5144 + + LDSMAXLX = 5145 + + LDSMAXW = 5146 + + LDSMAXX = 5147 + + LDSMINAB = 5148 + + LDSMINAH = 5149 + + LDSMINALB = 5150 + + LDSMINALH = 5151 + + LDSMINALW = 5152 + + LDSMINALX = 5153 + + LDSMINAW = 5154 + + LDSMINAX = 5155 + + LDSMINB = 5156 + + LDSMINH = 5157 + + LDSMINLB = 5158 + + LDSMINLH = 5159 + + LDSMINLW = 5160 + + LDSMINLX = 5161 + + LDSMINW = 5162 + + LDSMINX = 5163 + + LDTADDALW = 5164 + + LDTADDALX = 5165 + + LDTADDAW = 5166 + + LDTADDAX = 5167 + + LDTADDLW = 5168 + + LDTADDLX = 5169 + + LDTADDW = 5170 + + LDTADDX = 5171 + + LDTCLRALW = 5172 + + LDTCLRALX = 5173 + + LDTCLRAW = 5174 + + LDTCLRAX = 5175 + + LDTCLRLW = 5176 + + LDTCLRLX = 5177 + + LDTCLRW = 5178 + + LDTCLRX = 5179 + + LDTNPQi = 5180 + + LDTNPXi = 5181 + + LDTPQi = 5182 + + LDTPQpost = 5183 + + LDTPQpre = 5184 + + LDTPi = 5185 + + LDTPpost = 5186 + + LDTPpre = 5187 + + LDTRBi = 5188 + + LDTRHi = 5189 + + LDTRSBWi = 5190 + + LDTRSBXi = 5191 + + LDTRSHWi = 5192 + + LDTRSHXi = 5193 + + LDTRSWi = 5194 + + LDTRWi = 5195 + + LDTRXi = 5196 + + LDTSETALW = 5197 + + LDTSETALX = 5198 + + LDTSETAW = 5199 + + LDTSETAX = 5200 + + LDTSETLW = 5201 + + LDTSETLX = 5202 + + LDTSETW = 5203 + + LDTSETX = 5204 + + LDTXRWr = 5205 + + LDTXRXr = 5206 + + LDUMAXAB = 5207 + + LDUMAXAH = 5208 + + LDUMAXALB = 5209 + + LDUMAXALH = 5210 + + LDUMAXALW = 5211 + + LDUMAXALX = 5212 + + LDUMAXAW = 5213 + + LDUMAXAX = 5214 + + LDUMAXB = 5215 + + LDUMAXH = 5216 + + LDUMAXLB = 5217 + + LDUMAXLH = 5218 + + LDUMAXLW = 5219 + + LDUMAXLX = 5220 + + LDUMAXW = 5221 + + LDUMAXX = 5222 + + LDUMINAB = 5223 + + LDUMINAH = 5224 + + LDUMINALB = 5225 + + LDUMINALH = 5226 + + LDUMINALW = 5227 + + LDUMINALX = 5228 + + LDUMINAW = 5229 + + LDUMINAX = 5230 + + LDUMINB = 5231 + + LDUMINH = 5232 + + LDUMINLB = 5233 + + LDUMINLH = 5234 + + LDUMINLW = 5235 + + LDUMINLX = 5236 + + LDUMINW = 5237 + + LDUMINX = 5238 + + LDURBBi = 5239 + + LDURBi = 5240 + + LDURDi = 5241 + + LDURHHi = 5242 + + LDURHi = 5243 + + LDURQi = 5244 + + LDURSBWi = 5245 + + LDURSBXi = 5246 + + LDURSHWi = 5247 + + LDURSHXi = 5248 + + LDURSWi = 5249 + + LDURSi = 5250 + + LDURWi = 5251 + + LDURXi = 5252 + + LDXPW = 5253 + + LDXPX = 5254 + + LDXRB = 5255 + + LDXRH = 5256 + + LDXRW = 5257 + + LDXRX = 5258 + + LSLR_ZPmZ_B = 5259 + + LSLR_ZPmZ_D = 5260 + + LSLR_ZPmZ_H = 5261 + + LSLR_ZPmZ_S = 5262 + + LSLVWr = 5263 + + LSLVXr = 5264 + + LSL_WIDE_ZPmZ_B = 5265 + + LSL_WIDE_ZPmZ_H = 5266 + + LSL_WIDE_ZPmZ_S = 5267 + + LSL_WIDE_ZZZ_B = 5268 + + LSL_WIDE_ZZZ_H = 5269 + + LSL_WIDE_ZZZ_S = 5270 + + LSL_ZPmI_B = 5271 + + LSL_ZPmI_D = 5272 + + LSL_ZPmI_H = 5273 + + LSL_ZPmI_S = 5274 + + LSL_ZPmZ_B = 5275 + + LSL_ZPmZ_D = 5276 + + LSL_ZPmZ_H = 5277 + + LSL_ZPmZ_S = 5278 + + LSL_ZZI_B = 5279 + + LSL_ZZI_D = 5280 + + LSL_ZZI_H = 5281 + + LSL_ZZI_S = 5282 + + LSRR_ZPmZ_B = 5283 + + LSRR_ZPmZ_D = 5284 + + LSRR_ZPmZ_H = 5285 + + LSRR_ZPmZ_S = 5286 + + LSRVWr = 5287 + + LSRVXr = 5288 + + LSR_WIDE_ZPmZ_B = 5289 + + LSR_WIDE_ZPmZ_H = 5290 + + LSR_WIDE_ZPmZ_S = 5291 + + LSR_WIDE_ZZZ_B = 5292 + + LSR_WIDE_ZZZ_H = 5293 + + LSR_WIDE_ZZZ_S = 5294 + + LSR_ZPmI_B = 5295 + + LSR_ZPmI_D = 5296 + + LSR_ZPmI_H = 5297 + + LSR_ZPmI_S = 5298 + + LSR_ZPmZ_B = 5299 + + LSR_ZPmZ_D = 5300 + + LSR_ZPmZ_H = 5301 + + LSR_ZPmZ_S = 5302 + + LSR_ZZI_B = 5303 + + LSR_ZZI_D = 5304 + + LSR_ZZI_H = 5305 + + LSR_ZZI_S = 5306 + + LUT2_B = 5307 + + LUT2_H = 5308 + + LUT4_B = 5309 + + LUT4_H = 5310 + + LUTI2_2ZTZI_B = 5311 + + LUTI2_2ZTZI_H = 5312 + + LUTI2_2ZTZI_S = 5313 + + LUTI2_4ZTZI_B = 5314 + + LUTI2_4ZTZI_H = 5315 + + LUTI2_4ZTZI_S = 5316 + + LUTI2_S_2ZTZI_B = 5317 + + LUTI2_S_2ZTZI_H = 5318 + + LUTI2_S_4ZTZI_B = 5319 + + LUTI2_S_4ZTZI_H = 5320 + + LUTI2_ZTZI_B = 5321 + + LUTI2_ZTZI_H = 5322 + + LUTI2_ZTZI_S = 5323 + + LUTI2_ZZZI_B = 5324 + + LUTI2_ZZZI_H = 5325 + + LUTI4_2ZTZI_B = 5326 + + LUTI4_2ZTZI_H = 5327 + + LUTI4_2ZTZI_S = 5328 + + LUTI4_4ZTZI_H = 5329 + + LUTI4_4ZTZI_S = 5330 + + LUTI4_4ZZT2Z = 5331 + + LUTI4_S_2ZTZI_B = 5332 + + LUTI4_S_2ZTZI_H = 5333 + + LUTI4_S_4ZTZI_H = 5334 + + LUTI4_S_4ZZT2Z = 5335 + + LUTI4_Z2ZZI = 5336 + + LUTI4_ZTZI_B = 5337 + + LUTI4_ZTZI_H = 5338 + + LUTI4_ZTZI_S = 5339 + + LUTI4_ZZZI_B = 5340 + + LUTI4_ZZZI_H = 5341 + + LUTI6_4Z2Z2ZI = 5342 + + LUTI6_4ZT3Z = 5343 + + LUTI6_S_4Z2Z2ZI = 5344 + + LUTI6_S_4ZT3Z = 5345 + + LUTI6_Z2ZZ = 5346 + + LUTI6_Z2ZZI_H = 5347 + + LUTI6_ZTZ = 5348 + + MADDPT = 5349 + + MADDWrrr = 5350 + + MADDXrrr = 5351 + + MAD_CPA = 5352 + + MAD_ZPmZZ_B = 5353 + + MAD_ZPmZZ_D = 5354 + + MAD_ZPmZZ_H = 5355 + + MAD_ZPmZZ_S = 5356 + + MATCH_PPzZZ_B = 5357 + + MATCH_PPzZZ_H = 5358 + + MLA_CPA = 5359 + + MLA_ZPmZZ_B = 5360 + + MLA_ZPmZZ_D = 5361 + + MLA_ZPmZZ_H = 5362 + + MLA_ZPmZZ_S = 5363 + + MLA_ZZZI_D = 5364 + + MLA_ZZZI_H = 5365 + + MLA_ZZZI_S = 5366 + + MLAv16i8 = 5367 + + MLAv2i32 = 5368 + + MLAv2i32_indexed = 5369 + + MLAv4i16 = 5370 + + MLAv4i16_indexed = 5371 + + MLAv4i32 = 5372 + + MLAv4i32_indexed = 5373 + + MLAv8i16 = 5374 + + MLAv8i16_indexed = 5375 + + MLAv8i8 = 5376 + + MLS_ZPmZZ_B = 5377 + + MLS_ZPmZZ_D = 5378 + + MLS_ZPmZZ_H = 5379 + + MLS_ZPmZZ_S = 5380 + + MLS_ZZZI_D = 5381 + + MLS_ZZZI_H = 5382 + + MLS_ZZZI_S = 5383 + + MLSv16i8 = 5384 + + MLSv2i32 = 5385 + + MLSv2i32_indexed = 5386 + + MLSv4i16 = 5387 + + MLSv4i16_indexed = 5388 + + MLSv4i32 = 5389 + + MLSv4i32_indexed = 5390 + + MLSv8i16 = 5391 + + MLSv8i16_indexed = 5392 + + MLSv8i8 = 5393 + + MOPSSETGE = 5394 + + MOPSSETGEN = 5395 + + MOPSSETGET = 5396 + + MOPSSETGETN = 5397 + + MOVAZ_2ZMI_H_B = 5398 + + MOVAZ_2ZMI_H_D = 5399 + + MOVAZ_2ZMI_H_H = 5400 + + MOVAZ_2ZMI_H_S = 5401 + + MOVAZ_2ZMI_V_B = 5402 + + MOVAZ_2ZMI_V_D = 5403 + + MOVAZ_2ZMI_V_H = 5404 + + MOVAZ_2ZMI_V_S = 5405 + + MOVAZ_4ZMI_H_B = 5406 + + MOVAZ_4ZMI_H_D = 5407 + + MOVAZ_4ZMI_H_H = 5408 + + MOVAZ_4ZMI_H_S = 5409 + + MOVAZ_4ZMI_V_B = 5410 + + MOVAZ_4ZMI_V_D = 5411 + + MOVAZ_4ZMI_V_H = 5412 + + MOVAZ_4ZMI_V_S = 5413 + + MOVAZ_VG2_2ZMXI = 5414 + + MOVAZ_VG4_4ZMXI = 5415 + + MOVAZ_ZMI_H_B = 5416 + + MOVAZ_ZMI_H_D = 5417 + + MOVAZ_ZMI_H_H = 5418 + + MOVAZ_ZMI_H_Q = 5419 + + MOVAZ_ZMI_H_S = 5420 + + MOVAZ_ZMI_V_B = 5421 + + MOVAZ_ZMI_V_D = 5422 + + MOVAZ_ZMI_V_H = 5423 + + MOVAZ_ZMI_V_Q = 5424 + + MOVAZ_ZMI_V_S = 5425 + + MOVA_2ZMXI_H_B = 5426 + + MOVA_2ZMXI_H_D = 5427 + + MOVA_2ZMXI_H_H = 5428 + + MOVA_2ZMXI_H_S = 5429 + + MOVA_2ZMXI_V_B = 5430 + + MOVA_2ZMXI_V_D = 5431 + + MOVA_2ZMXI_V_H = 5432 + + MOVA_2ZMXI_V_S = 5433 + + MOVA_4ZMXI_H_B = 5434 + + MOVA_4ZMXI_H_D = 5435 + + MOVA_4ZMXI_H_H = 5436 + + MOVA_4ZMXI_H_S = 5437 + + MOVA_4ZMXI_V_B = 5438 + + MOVA_4ZMXI_V_D = 5439 + + MOVA_4ZMXI_V_H = 5440 + + MOVA_4ZMXI_V_S = 5441 + + MOVA_MXI2Z_H_B = 5442 + + MOVA_MXI2Z_H_D = 5443 + + MOVA_MXI2Z_H_H = 5444 + + MOVA_MXI2Z_H_S = 5445 + + MOVA_MXI2Z_V_B = 5446 + + MOVA_MXI2Z_V_D = 5447 + + MOVA_MXI2Z_V_H = 5448 + + MOVA_MXI2Z_V_S = 5449 + + MOVA_MXI4Z_H_B = 5450 + + MOVA_MXI4Z_H_D = 5451 + + MOVA_MXI4Z_H_H = 5452 + + MOVA_MXI4Z_H_S = 5453 + + MOVA_MXI4Z_V_B = 5454 + + MOVA_MXI4Z_V_D = 5455 + + MOVA_MXI4Z_V_H = 5456 + + MOVA_MXI4Z_V_S = 5457 + + MOVA_VG2_2ZMXI = 5458 + + MOVA_VG2_MXI2Z = 5459 + + MOVA_VG4_4ZMXI = 5460 + + MOVA_VG4_MXI4Z = 5461 + + MOVID = 5462 + + MOVIv16b_ns = 5463 + + MOVIv2d_ns = 5464 + + MOVIv2i32 = 5465 + + MOVIv2s_msl = 5466 + + MOVIv4i16 = 5467 + + MOVIv4i32 = 5468 + + MOVIv4s_msl = 5469 + + MOVIv8b_ns = 5470 + + MOVIv8i16 = 5471 + + MOVKWi = 5472 + + MOVKXi = 5473 + + MOVNWi = 5474 + + MOVNXi = 5475 + + MOVPRFX_ZPmZ_B = 5476 + + MOVPRFX_ZPmZ_D = 5477 + + MOVPRFX_ZPmZ_H = 5478 + + MOVPRFX_ZPmZ_S = 5479 + + MOVPRFX_ZPzZ_B = 5480 + + MOVPRFX_ZPzZ_D = 5481 + + MOVPRFX_ZPzZ_H = 5482 + + MOVPRFX_ZPzZ_S = 5483 + + MOVPRFX_ZZ = 5484 + + MOVT_TIX = 5485 + + MOVT_TIZ = 5486 + + MOVT_XTI = 5487 + + MOVZWi = 5488 + + MOVZXi = 5489 + + MRRS = 5490 + + MRS = 5491 + + MSB_ZPmZZ_B = 5492 + + MSB_ZPmZZ_D = 5493 + + MSB_ZPmZZ_H = 5494 + + MSB_ZPmZZ_S = 5495 + + MSR = 5496 + + MSRR = 5497 + + MSRpstateImm1 = 5498 + + MSRpstateImm4 = 5499 + + MSRpstatesvcrImm1 = 5500 + + MSUBPT = 5501 + + MSUBWrrr = 5502 + + MSUBXrrr = 5503 + + MUL_ZI_B = 5504 + + MUL_ZI_D = 5505 + + MUL_ZI_H = 5506 + + MUL_ZI_S = 5507 + + MUL_ZPmZ_B = 5508 + + MUL_ZPmZ_D = 5509 + + MUL_ZPmZ_H = 5510 + + MUL_ZPmZ_S = 5511 + + MUL_ZZZI_D = 5512 + + MUL_ZZZI_H = 5513 + + MUL_ZZZI_S = 5514 + + MUL_ZZZ_B = 5515 + + MUL_ZZZ_D = 5516 + + MUL_ZZZ_H = 5517 + + MUL_ZZZ_S = 5518 + + MULv16i8 = 5519 + + MULv2i32 = 5520 + + MULv2i32_indexed = 5521 + + MULv4i16 = 5522 + + MULv4i16_indexed = 5523 + + MULv4i32 = 5524 + + MULv4i32_indexed = 5525 + + MULv8i16 = 5526 + + MULv8i16_indexed = 5527 + + MULv8i8 = 5528 + + MVNIv2i32 = 5529 + + MVNIv2s_msl = 5530 + + MVNIv4i16 = 5531 + + MVNIv4i32 = 5532 + + MVNIv4s_msl = 5533 + + MVNIv8i16 = 5534 + + NANDS_PPzPP = 5535 + + NAND_PPzPP = 5536 + + NBSL_ZZZZ = 5537 + + NEG_ZPmZ_B = 5538 + + NEG_ZPmZ_D = 5539 + + NEG_ZPmZ_H = 5540 + + NEG_ZPmZ_S = 5541 + + NEG_ZPzZ_B = 5542 + + NEG_ZPzZ_D = 5543 + + NEG_ZPzZ_H = 5544 + + NEG_ZPzZ_S = 5545 + + NEGv16i8 = 5546 + + NEGv1i64 = 5547 + + NEGv2i32 = 5548 + + NEGv2i64 = 5549 + + NEGv4i16 = 5550 + + NEGv4i32 = 5551 + + NEGv8i16 = 5552 + + NEGv8i8 = 5553 + + NMATCH_PPzZZ_B = 5554 + + NMATCH_PPzZZ_H = 5555 + + NOP = 5556 + + NORS_PPzPP = 5557 + + NOR_PPzPP = 5558 + + NOT_ZPmZ_B = 5559 + + NOT_ZPmZ_D = 5560 + + NOT_ZPmZ_H = 5561 + + NOT_ZPmZ_S = 5562 + + NOT_ZPzZ_B = 5563 + + NOT_ZPzZ_D = 5564 + + NOT_ZPzZ_H = 5565 + + NOT_ZPzZ_S = 5566 + + NOTv16i8 = 5567 + + NOTv8i8 = 5568 + + ORNS_PPzPP = 5569 + + ORNWrs = 5570 + + ORNXrs = 5571 + + ORN_PPzPP = 5572 + + ORNv16i8 = 5573 + + ORNv8i8 = 5574 + + ORQV_VPZ_B = 5575 + + ORQV_VPZ_D = 5576 + + ORQV_VPZ_H = 5577 + + ORQV_VPZ_S = 5578 + + ORRS_PPzPP = 5579 + + ORRWri = 5580 + + ORRWrs = 5581 + + ORRXri = 5582 + + ORRXrs = 5583 + + ORR_PPzPP = 5584 + + ORR_ZI = 5585 + + ORR_ZPmZ_B = 5586 + + ORR_ZPmZ_D = 5587 + + ORR_ZPmZ_H = 5588 + + ORR_ZPmZ_S = 5589 + + ORR_ZZZ = 5590 + + ORRv16i8 = 5591 + + ORRv2i32 = 5592 + + ORRv4i16 = 5593 + + ORRv4i32 = 5594 + + ORRv8i16 = 5595 + + ORRv8i8 = 5596 + + ORV_VPZ_B = 5597 + + ORV_VPZ_D = 5598 + + ORV_VPZ_H = 5599 + + ORV_VPZ_S = 5600 + + PACDA = 5601 + + PACDB = 5602 + + PACDZA = 5603 + + PACDZB = 5604 + + PACGA = 5605 + + PACIA = 5606 + + PACIA1716 = 5607 + + PACIA171615 = 5608 + + PACIASP = 5609 + + PACIASPPC = 5610 + + PACIAZ = 5611 + + PACIB = 5612 + + PACIB1716 = 5613 + + PACIB171615 = 5614 + + PACIBSP = 5615 + + PACIBSPPC = 5616 + + PACIBZ = 5617 + + PACIZA = 5618 + + PACIZB = 5619 + + PACM = 5620 + + PACNBIASPPC = 5621 + + PACNBIBSPPC = 5622 + + PEXT_2PCI_B = 5623 + + PEXT_2PCI_D = 5624 + + PEXT_2PCI_H = 5625 + + PEXT_2PCI_S = 5626 + + PEXT_PCI_B = 5627 + + PEXT_PCI_D = 5628 + + PEXT_PCI_H = 5629 + + PEXT_PCI_S = 5630 + + PFALSE = 5631 + + PFIRST_B = 5632 + + PMLAL_2ZZZ_Q = 5633 + + PMOV_PZI_B = 5634 + + PMOV_PZI_D = 5635 + + PMOV_PZI_H = 5636 + + PMOV_PZI_S = 5637 + + PMOV_ZIP_B = 5638 + + PMOV_ZIP_D = 5639 + + PMOV_ZIP_H = 5640 + + PMOV_ZIP_S = 5641 + + PMULLB_ZZZ_D = 5642 + + PMULLB_ZZZ_H = 5643 + + PMULLB_ZZZ_Q = 5644 + + PMULLT_ZZZ_D = 5645 + + PMULLT_ZZZ_H = 5646 + + PMULLT_ZZZ_Q = 5647 + + PMULL_2ZZZ_Q = 5648 + + PMULLv16i8 = 5649 + + PMULLv1i64 = 5650 + + PMULLv2i64 = 5651 + + PMULLv8i8 = 5652 + + PMUL_ZZZ_B = 5653 + + PMULv16i8 = 5654 + + PMULv8i8 = 5655 + + PNEXT_B = 5656 + + PNEXT_D = 5657 + + PNEXT_H = 5658 + + PNEXT_S = 5659 + + PRFB_D_PZI = 5660 + + PRFB_D_SCALED = 5661 + + PRFB_D_SXTW_SCALED = 5662 + + PRFB_D_UXTW_SCALED = 5663 + + PRFB_PRI = 5664 + + PRFB_PRR = 5665 + + PRFB_S_PZI = 5666 + + PRFB_S_SXTW_SCALED = 5667 + + PRFB_S_UXTW_SCALED = 5668 + + PRFD_D_PZI = 5669 + + PRFD_D_SCALED = 5670 + + PRFD_D_SXTW_SCALED = 5671 + + PRFD_D_UXTW_SCALED = 5672 + + PRFD_PRI = 5673 + + PRFD_PRR = 5674 + + PRFD_S_PZI = 5675 + + PRFD_S_SXTW_SCALED = 5676 + + PRFD_S_UXTW_SCALED = 5677 + + PRFH_D_PZI = 5678 + + PRFH_D_SCALED = 5679 + + PRFH_D_SXTW_SCALED = 5680 + + PRFH_D_UXTW_SCALED = 5681 + + PRFH_PRI = 5682 + + PRFH_PRR = 5683 + + PRFH_S_PZI = 5684 + + PRFH_S_SXTW_SCALED = 5685 + + PRFH_S_UXTW_SCALED = 5686 + + PRFMl = 5687 + + PRFMroW = 5688 + + PRFMroX = 5689 + + PRFMui = 5690 + + PRFUMi = 5691 + + PRFW_D_PZI = 5692 + + PRFW_D_SCALED = 5693 + + PRFW_D_SXTW_SCALED = 5694 + + PRFW_D_UXTW_SCALED = 5695 + + PRFW_PRI = 5696 + + PRFW_PRR = 5697 + + PRFW_S_PZI = 5698 + + PRFW_S_SXTW_SCALED = 5699 + + PRFW_S_UXTW_SCALED = 5700 + + PSEL_PPPRI_B = 5701 + + PSEL_PPPRI_D = 5702 + + PSEL_PPPRI_H = 5703 + + PSEL_PPPRI_S = 5704 + + PTEST_PP = 5705 + + PTRUES_B = 5706 + + PTRUES_D = 5707 + + PTRUES_H = 5708 + + PTRUES_S = 5709 + + PTRUE_B = 5710 + + PTRUE_C_B = 5711 + + PTRUE_C_D = 5712 + + PTRUE_C_H = 5713 + + PTRUE_C_S = 5714 + + PTRUE_D = 5715 + + PTRUE_H = 5716 + + PTRUE_S = 5717 + + PUNPKHI_PP = 5718 + + PUNPKLO_PP = 5719 + + RADDHNB_ZZZ_B = 5720 + + RADDHNB_ZZZ_H = 5721 + + RADDHNB_ZZZ_S = 5722 + + RADDHNT_ZZZ_B = 5723 + + RADDHNT_ZZZ_H = 5724 + + RADDHNT_ZZZ_S = 5725 + + RADDHNv2i64_v2i32 = 5726 + + RADDHNv2i64_v4i32 = 5727 + + RADDHNv4i32_v4i16 = 5728 + + RADDHNv4i32_v8i16 = 5729 + + RADDHNv8i16_v16i8 = 5730 + + RADDHNv8i16_v8i8 = 5731 + + RAX1 = 5732 + + RAX1_ZZZ_D = 5733 + + RBITWr = 5734 + + RBITXr = 5735 + + RBIT_ZPmZ_B = 5736 + + RBIT_ZPmZ_D = 5737 + + RBIT_ZPmZ_H = 5738 + + RBIT_ZPmZ_S = 5739 + + RBIT_ZPzZ_B = 5740 + + RBIT_ZPzZ_D = 5741 + + RBIT_ZPzZ_H = 5742 + + RBIT_ZPzZ_S = 5743 + + RBITv16i8 = 5744 + + RBITv8i8 = 5745 + + RCWCAS = 5746 + + RCWCASA = 5747 + + RCWCASAL = 5748 + + RCWCASL = 5749 + + RCWCASP = 5750 + + RCWCASPA = 5751 + + RCWCASPAL = 5752 + + RCWCASPL = 5753 + + RCWCLR = 5754 + + RCWCLRA = 5755 + + RCWCLRAL = 5756 + + RCWCLRL = 5757 + + RCWCLRP = 5758 + + RCWCLRPA = 5759 + + RCWCLRPAL = 5760 + + RCWCLRPL = 5761 + + RCWCLRS = 5762 + + RCWCLRSA = 5763 + + RCWCLRSAL = 5764 + + RCWCLRSL = 5765 + + RCWCLRSP = 5766 + + RCWCLRSPA = 5767 + + RCWCLRSPAL = 5768 + + RCWCLRSPL = 5769 + + RCWSCAS = 5770 + + RCWSCASA = 5771 + + RCWSCASAL = 5772 + + RCWSCASL = 5773 + + RCWSCASP = 5774 + + RCWSCASPA = 5775 + + RCWSCASPAL = 5776 + + RCWSCASPL = 5777 + + RCWSET = 5778 + + RCWSETA = 5779 + + RCWSETAL = 5780 + + RCWSETL = 5781 + + RCWSETP = 5782 + + RCWSETPA = 5783 + + RCWSETPAL = 5784 + + RCWSETPL = 5785 + + RCWSETS = 5786 + + RCWSETSA = 5787 + + RCWSETSAL = 5788 + + RCWSETSL = 5789 + + RCWSETSP = 5790 + + RCWSETSPA = 5791 + + RCWSETSPAL = 5792 + + RCWSETSPL = 5793 + + RCWSWP = 5794 + + RCWSWPA = 5795 + + RCWSWPAL = 5796 + + RCWSWPL = 5797 + + RCWSWPP = 5798 + + RCWSWPPA = 5799 + + RCWSWPPAL = 5800 + + RCWSWPPL = 5801 + + RCWSWPS = 5802 + + RCWSWPSA = 5803 + + RCWSWPSAL = 5804 + + RCWSWPSL = 5805 + + RCWSWPSP = 5806 + + RCWSWPSPA = 5807 + + RCWSWPSPAL = 5808 + + RCWSWPSPL = 5809 + + RDFFRS_PPz = 5810 + + RDFFR_P = 5811 + + RDFFR_PPz = 5812 + + RDSVLI_XI = 5813 + + RDVLI_XI = 5814 + + RET = 5815 + + RETAA = 5816 + + RETAASPPCi = 5817 + + RETAASPPCr = 5818 + + RETAB = 5819 + + RETABSPPCi = 5820 + + RETABSPPCr = 5821 + + REV16Wr = 5822 + + REV16Xr = 5823 + + REV16v16i8 = 5824 + + REV16v8i8 = 5825 + + REV32Xr = 5826 + + REV32v16i8 = 5827 + + REV32v4i16 = 5828 + + REV32v8i16 = 5829 + + REV32v8i8 = 5830 + + REV64v16i8 = 5831 + + REV64v2i32 = 5832 + + REV64v4i16 = 5833 + + REV64v4i32 = 5834 + + REV64v8i16 = 5835 + + REV64v8i8 = 5836 + + REVB_ZPmZ_D = 5837 + + REVB_ZPmZ_H = 5838 + + REVB_ZPmZ_S = 5839 + + REVB_ZPzZ_D = 5840 + + REVB_ZPzZ_H = 5841 + + REVB_ZPzZ_S = 5842 + + REVD_ZPmZ = 5843 + + REVD_ZPzZ = 5844 + + REVH_ZPmZ_D = 5845 + + REVH_ZPmZ_S = 5846 + + REVH_ZPzZ_D = 5847 + + REVH_ZPzZ_S = 5848 + + REVW_ZPmZ_D = 5849 + + REVW_ZPzZ_D = 5850 + + REVWr = 5851 + + REVXr = 5852 + + REV_PP_B = 5853 + + REV_PP_D = 5854 + + REV_PP_H = 5855 + + REV_PP_S = 5856 + + REV_ZZ_B = 5857 + + REV_ZZ_D = 5858 + + REV_ZZ_H = 5859 + + REV_ZZ_S = 5860 + + RMIF = 5861 + + RORVWr = 5862 + + RORVXr = 5863 + + RPRFM = 5864 + + RSHRNB_ZZI_B = 5865 + + RSHRNB_ZZI_H = 5866 + + RSHRNB_ZZI_S = 5867 + + RSHRNT_ZZI_B = 5868 + + RSHRNT_ZZI_H = 5869 + + RSHRNT_ZZI_S = 5870 + + RSHRNv16i8_shift = 5871 + + RSHRNv2i32_shift = 5872 + + RSHRNv4i16_shift = 5873 + + RSHRNv4i32_shift = 5874 + + RSHRNv8i16_shift = 5875 + + RSHRNv8i8_shift = 5876 + + RSUBHNB_ZZZ_B = 5877 + + RSUBHNB_ZZZ_H = 5878 + + RSUBHNB_ZZZ_S = 5879 + + RSUBHNT_ZZZ_B = 5880 + + RSUBHNT_ZZZ_H = 5881 + + RSUBHNT_ZZZ_S = 5882 + + RSUBHNv2i64_v2i32 = 5883 + + RSUBHNv2i64_v4i32 = 5884 + + RSUBHNv4i32_v4i16 = 5885 + + RSUBHNv4i32_v8i16 = 5886 + + RSUBHNv8i16_v16i8 = 5887 + + RSUBHNv8i16_v8i8 = 5888 + + SABALB_ZZZ_D = 5889 + + SABALB_ZZZ_H = 5890 + + SABALB_ZZZ_S = 5891 + + SABALT_ZZZ_D = 5892 + + SABALT_ZZZ_H = 5893 + + SABALT_ZZZ_S = 5894 + + SABAL_ZZZ_BtoH = 5895 + + SABAL_ZZZ_HtoS = 5896 + + SABAL_ZZZ_StoD = 5897 + + SABALv16i8_v8i16 = 5898 + + SABALv2i32_v2i64 = 5899 + + SABALv4i16_v4i32 = 5900 + + SABALv4i32_v2i64 = 5901 + + SABALv8i16_v4i32 = 5902 + + SABALv8i8_v8i16 = 5903 + + SABA_ZZZ_B = 5904 + + SABA_ZZZ_D = 5905 + + SABA_ZZZ_H = 5906 + + SABA_ZZZ_S = 5907 + + SABAv16i8 = 5908 + + SABAv2i32 = 5909 + + SABAv4i16 = 5910 + + SABAv4i32 = 5911 + + SABAv8i16 = 5912 + + SABAv8i8 = 5913 + + SABDLB_ZZZ_D = 5914 + + SABDLB_ZZZ_H = 5915 + + SABDLB_ZZZ_S = 5916 + + SABDLT_ZZZ_D = 5917 + + SABDLT_ZZZ_H = 5918 + + SABDLT_ZZZ_S = 5919 + + SABDLv16i8_v8i16 = 5920 + + SABDLv2i32_v2i64 = 5921 + + SABDLv4i16_v4i32 = 5922 + + SABDLv4i32_v2i64 = 5923 + + SABDLv8i16_v4i32 = 5924 + + SABDLv8i8_v8i16 = 5925 + + SABD_ZPmZ_B = 5926 + + SABD_ZPmZ_D = 5927 + + SABD_ZPmZ_H = 5928 + + SABD_ZPmZ_S = 5929 + + SABDv16i8 = 5930 + + SABDv2i32 = 5931 + + SABDv4i16 = 5932 + + SABDv4i32 = 5933 + + SABDv8i16 = 5934 + + SABDv8i8 = 5935 + + SADALP_ZPmZ_D = 5936 + + SADALP_ZPmZ_H = 5937 + + SADALP_ZPmZ_S = 5938 + + SADALPv16i8_v8i16 = 5939 + + SADALPv2i32_v1i64 = 5940 + + SADALPv4i16_v2i32 = 5941 + + SADALPv4i32_v2i64 = 5942 + + SADALPv8i16_v4i32 = 5943 + + SADALPv8i8_v4i16 = 5944 + + SADDLBT_ZZZ_D = 5945 + + SADDLBT_ZZZ_H = 5946 + + SADDLBT_ZZZ_S = 5947 + + SADDLB_ZZZ_D = 5948 + + SADDLB_ZZZ_H = 5949 + + SADDLB_ZZZ_S = 5950 + + SADDLPv16i8_v8i16 = 5951 + + SADDLPv2i32_v1i64 = 5952 + + SADDLPv4i16_v2i32 = 5953 + + SADDLPv4i32_v2i64 = 5954 + + SADDLPv8i16_v4i32 = 5955 + + SADDLPv8i8_v4i16 = 5956 + + SADDLT_ZZZ_D = 5957 + + SADDLT_ZZZ_H = 5958 + + SADDLT_ZZZ_S = 5959 + + SADDLVv16i8v = 5960 + + SADDLVv4i16v = 5961 + + SADDLVv4i32v = 5962 + + SADDLVv8i16v = 5963 + + SADDLVv8i8v = 5964 + + SADDLv16i8_v8i16 = 5965 + + SADDLv2i32_v2i64 = 5966 + + SADDLv4i16_v4i32 = 5967 + + SADDLv4i32_v2i64 = 5968 + + SADDLv8i16_v4i32 = 5969 + + SADDLv8i8_v8i16 = 5970 + + SADDV_VPZ_B = 5971 + + SADDV_VPZ_H = 5972 + + SADDV_VPZ_S = 5973 + + SADDWB_ZZZ_D = 5974 + + SADDWB_ZZZ_H = 5975 + + SADDWB_ZZZ_S = 5976 + + SADDWT_ZZZ_D = 5977 + + SADDWT_ZZZ_H = 5978 + + SADDWT_ZZZ_S = 5979 + + SADDWv16i8_v8i16 = 5980 + + SADDWv2i32_v2i64 = 5981 + + SADDWv4i16_v4i32 = 5982 + + SADDWv4i32_v2i64 = 5983 + + SADDWv8i16_v4i32 = 5984 + + SADDWv8i8_v8i16 = 5985 + + SB = 5986 + + SBCLB_ZZZ_D = 5987 + + SBCLB_ZZZ_S = 5988 + + SBCLT_ZZZ_D = 5989 + + SBCLT_ZZZ_S = 5990 + + SBCSWr = 5991 + + SBCSXr = 5992 + + SBCWr = 5993 + + SBCXr = 5994 + + SBFMWri = 5995 + + SBFMXri = 5996 + + SCLAMP_VG2_2Z2Z_B = 5997 + + SCLAMP_VG2_2Z2Z_D = 5998 + + SCLAMP_VG2_2Z2Z_H = 5999 + + SCLAMP_VG2_2Z2Z_S = 6000 + + SCLAMP_VG4_4Z4Z_B = 6001 + + SCLAMP_VG4_4Z4Z_D = 6002 + + SCLAMP_VG4_4Z4Z_H = 6003 + + SCLAMP_VG4_4Z4Z_S = 6004 + + SCLAMP_ZZZ_B = 6005 + + SCLAMP_ZZZ_D = 6006 + + SCLAMP_ZZZ_H = 6007 + + SCLAMP_ZZZ_S = 6008 + + SCVTFDSr = 6009 + + SCVTFHDr = 6010 + + SCVTFHSr = 6011 + + SCVTFLT_ZZ_BtoH = 6012 + + SCVTFLT_ZZ_HtoS = 6013 + + SCVTFLT_ZZ_StoD = 6014 + + SCVTFSDr = 6015 + + SCVTFSWDri = 6016 + + SCVTFSWHri = 6017 + + SCVTFSWSri = 6018 + + SCVTFSXDri = 6019 + + SCVTFSXHri = 6020 + + SCVTFSXSri = 6021 + + SCVTFUWDri = 6022 + + SCVTFUWHri = 6023 + + SCVTFUWSri = 6024 + + SCVTFUXDri = 6025 + + SCVTFUXHri = 6026 + + SCVTFUXSri = 6027 + + SCVTF_2Z2Z_StoS = 6028 + + SCVTF_4Z4Z_StoS = 6029 + + SCVTF_ZPmZ_DtoD = 6030 + + SCVTF_ZPmZ_DtoH = 6031 + + SCVTF_ZPmZ_DtoS = 6032 + + SCVTF_ZPmZ_HtoH = 6033 + + SCVTF_ZPmZ_StoD = 6034 + + SCVTF_ZPmZ_StoH = 6035 + + SCVTF_ZPmZ_StoS = 6036 + + SCVTF_ZPzZ_DtoD = 6037 + + SCVTF_ZPzZ_DtoH = 6038 + + SCVTF_ZPzZ_DtoS = 6039 + + SCVTF_ZPzZ_HtoH = 6040 + + SCVTF_ZPzZ_StoD = 6041 + + SCVTF_ZPzZ_StoH = 6042 + + SCVTF_ZPzZ_StoS = 6043 + + SCVTF_ZZ_BtoH = 6044 + + SCVTF_ZZ_HtoS = 6045 + + SCVTF_ZZ_StoD = 6046 + + SCVTFd = 6047 + + SCVTFh = 6048 + + SCVTFs = 6049 + + SCVTFv1i16 = 6050 + + SCVTFv1i32 = 6051 + + SCVTFv1i64 = 6052 + + SCVTFv2f32 = 6053 + + SCVTFv2f64 = 6054 + + SCVTFv2i32_shift = 6055 + + SCVTFv2i64_shift = 6056 + + SCVTFv4f16 = 6057 + + SCVTFv4f32 = 6058 + + SCVTFv4i16_shift = 6059 + + SCVTFv4i32_shift = 6060 + + SCVTFv8f16 = 6061 + + SCVTFv8i16_shift = 6062 + + SDIVR_ZPmZ_D = 6063 + + SDIVR_ZPmZ_S = 6064 + + SDIVWr = 6065 + + SDIVXr = 6066 + + SDIV_ZPmZ_D = 6067 + + SDIV_ZPmZ_S = 6068 + + SDOT_VG2_M2Z2Z_BtoS = 6069 + + SDOT_VG2_M2Z2Z_HtoD = 6070 + + SDOT_VG2_M2Z2Z_HtoS = 6071 + + SDOT_VG2_M2ZZI_BToS = 6072 + + SDOT_VG2_M2ZZI_HToS = 6073 + + SDOT_VG2_M2ZZI_HtoD = 6074 + + SDOT_VG2_M2ZZ_BtoS = 6075 + + SDOT_VG2_M2ZZ_HtoD = 6076 + + SDOT_VG2_M2ZZ_HtoS = 6077 + + SDOT_VG4_M4Z4Z_BtoS = 6078 + + SDOT_VG4_M4Z4Z_HtoD = 6079 + + SDOT_VG4_M4Z4Z_HtoS = 6080 + + SDOT_VG4_M4ZZI_BToS = 6081 + + SDOT_VG4_M4ZZI_HToS = 6082 + + SDOT_VG4_M4ZZI_HtoD = 6083 + + SDOT_VG4_M4ZZ_BtoS = 6084 + + SDOT_VG4_M4ZZ_HtoD = 6085 + + SDOT_VG4_M4ZZ_HtoS = 6086 + + SDOT_ZZZI_BtoH = 6087 + + SDOT_ZZZI_BtoS = 6088 + + SDOT_ZZZI_HtoD = 6089 + + SDOT_ZZZI_HtoS = 6090 + + SDOT_ZZZ_BtoH = 6091 + + SDOT_ZZZ_BtoS = 6092 + + SDOT_ZZZ_HtoD = 6093 + + SDOT_ZZZ_HtoS = 6094 + + SDOTlanev16i8 = 6095 + + SDOTlanev8i8 = 6096 + + SDOTv16i8 = 6097 + + SDOTv8i8 = 6098 + + SEL_PPPP = 6099 + + SEL_VG2_2ZC2Z2Z_B = 6100 + + SEL_VG2_2ZC2Z2Z_D = 6101 + + SEL_VG2_2ZC2Z2Z_H = 6102 + + SEL_VG2_2ZC2Z2Z_S = 6103 + + SEL_VG4_4ZC4Z4Z_B = 6104 + + SEL_VG4_4ZC4Z4Z_D = 6105 + + SEL_VG4_4ZC4Z4Z_H = 6106 + + SEL_VG4_4ZC4Z4Z_S = 6107 + + SEL_ZPZZ_B = 6108 + + SEL_ZPZZ_D = 6109 + + SEL_ZPZZ_H = 6110 + + SEL_ZPZZ_S = 6111 + + SETE = 6112 + + SETEN = 6113 + + SETET = 6114 + + SETETN = 6115 + + SETF16 = 6116 + + SETF8 = 6117 + + SETFFR = 6118 + + SETGM = 6119 + + SETGMN = 6120 + + SETGMT = 6121 + + SETGMTN = 6122 + + SETGOE = 6123 + + SETGOEN = 6124 + + SETGOET = 6125 + + SETGOETN = 6126 + + SETGOM = 6127 + + SETGOMN = 6128 + + SETGOMT = 6129 + + SETGOMTN = 6130 + + SETGOP = 6131 + + SETGOPN = 6132 + + SETGOPT = 6133 + + SETGOPTN = 6134 + + SETGP = 6135 + + SETGPN = 6136 + + SETGPT = 6137 + + SETGPTN = 6138 + + SETM = 6139 + + SETMN = 6140 + + SETMT = 6141 + + SETMTN = 6142 + + SETP = 6143 + + SETPN = 6144 + + SETPT = 6145 + + SETPTN = 6146 + + SHA1Crrr = 6147 + + SHA1Hrr = 6148 + + SHA1Mrrr = 6149 + + SHA1Prrr = 6150 + + SHA1SU0rrr = 6151 + + SHA1SU1rr = 6152 + + SHA256H2rrr = 6153 + + SHA256Hrrr = 6154 + + SHA256SU0rr = 6155 + + SHA256SU1rrr = 6156 + + SHA512H = 6157 + + SHA512H2 = 6158 + + SHA512SU0 = 6159 + + SHA512SU1 = 6160 + + SHADD_ZPmZ_B = 6161 + + SHADD_ZPmZ_D = 6162 + + SHADD_ZPmZ_H = 6163 + + SHADD_ZPmZ_S = 6164 + + SHADDv16i8 = 6165 + + SHADDv2i32 = 6166 + + SHADDv4i16 = 6167 + + SHADDv4i32 = 6168 + + SHADDv8i16 = 6169 + + SHADDv8i8 = 6170 + + SHLLv16i8 = 6171 + + SHLLv2i32 = 6172 + + SHLLv4i16 = 6173 + + SHLLv4i32 = 6174 + + SHLLv8i16 = 6175 + + SHLLv8i8 = 6176 + + SHLd = 6177 + + SHLv16i8_shift = 6178 + + SHLv2i32_shift = 6179 + + SHLv2i64_shift = 6180 + + SHLv4i16_shift = 6181 + + SHLv4i32_shift = 6182 + + SHLv8i16_shift = 6183 + + SHLv8i8_shift = 6184 + + SHRNB_ZZI_B = 6185 + + SHRNB_ZZI_H = 6186 + + SHRNB_ZZI_S = 6187 + + SHRNT_ZZI_B = 6188 + + SHRNT_ZZI_H = 6189 + + SHRNT_ZZI_S = 6190 + + SHRNv16i8_shift = 6191 + + SHRNv2i32_shift = 6192 + + SHRNv4i16_shift = 6193 + + SHRNv4i32_shift = 6194 + + SHRNv8i16_shift = 6195 + + SHRNv8i8_shift = 6196 + + SHSUBR_ZPmZ_B = 6197 + + SHSUBR_ZPmZ_D = 6198 + + SHSUBR_ZPmZ_H = 6199 + + SHSUBR_ZPmZ_S = 6200 + + SHSUB_ZPmZ_B = 6201 + + SHSUB_ZPmZ_D = 6202 + + SHSUB_ZPmZ_H = 6203 + + SHSUB_ZPmZ_S = 6204 + + SHSUBv16i8 = 6205 + + SHSUBv2i32 = 6206 + + SHSUBv4i16 = 6207 + + SHSUBv4i32 = 6208 + + SHSUBv8i16 = 6209 + + SHSUBv8i8 = 6210 + + SHUH = 6211 + + SLI_ZZI_B = 6212 + + SLI_ZZI_D = 6213 + + SLI_ZZI_H = 6214 + + SLI_ZZI_S = 6215 + + SLId = 6216 + + SLIv16i8_shift = 6217 + + SLIv2i32_shift = 6218 + + SLIv2i64_shift = 6219 + + SLIv4i16_shift = 6220 + + SLIv4i32_shift = 6221 + + SLIv8i16_shift = 6222 + + SLIv8i8_shift = 6223 + + SM3PARTW1 = 6224 + + SM3PARTW2 = 6225 + + SM3SS1 = 6226 + + SM3TT1A = 6227 + + SM3TT1B = 6228 + + SM3TT2A = 6229 + + SM3TT2B = 6230 + + SM4E = 6231 + + SM4EKEY_ZZZ_S = 6232 + + SM4ENCKEY = 6233 + + SM4E_ZZZ_S = 6234 + + SMADDLrrr = 6235 + + SMAXP_ZPmZ_B = 6236 + + SMAXP_ZPmZ_D = 6237 + + SMAXP_ZPmZ_H = 6238 + + SMAXP_ZPmZ_S = 6239 + + SMAXPv16i8 = 6240 + + SMAXPv2i32 = 6241 + + SMAXPv4i16 = 6242 + + SMAXPv4i32 = 6243 + + SMAXPv8i16 = 6244 + + SMAXPv8i8 = 6245 + + SMAXQV_VPZ_B = 6246 + + SMAXQV_VPZ_D = 6247 + + SMAXQV_VPZ_H = 6248 + + SMAXQV_VPZ_S = 6249 + + SMAXV_VPZ_B = 6250 + + SMAXV_VPZ_D = 6251 + + SMAXV_VPZ_H = 6252 + + SMAXV_VPZ_S = 6253 + + SMAXVv16i8v = 6254 + + SMAXVv4i16v = 6255 + + SMAXVv4i32v = 6256 + + SMAXVv8i16v = 6257 + + SMAXVv8i8v = 6258 + + SMAXWri = 6259 + + SMAXWrr = 6260 + + SMAXXri = 6261 + + SMAXXrr = 6262 + + SMAX_VG2_2Z2Z_B = 6263 + + SMAX_VG2_2Z2Z_D = 6264 + + SMAX_VG2_2Z2Z_H = 6265 + + SMAX_VG2_2Z2Z_S = 6266 + + SMAX_VG2_2ZZ_B = 6267 + + SMAX_VG2_2ZZ_D = 6268 + + SMAX_VG2_2ZZ_H = 6269 + + SMAX_VG2_2ZZ_S = 6270 + + SMAX_VG4_4Z4Z_B = 6271 + + SMAX_VG4_4Z4Z_D = 6272 + + SMAX_VG4_4Z4Z_H = 6273 + + SMAX_VG4_4Z4Z_S = 6274 + + SMAX_VG4_4ZZ_B = 6275 + + SMAX_VG4_4ZZ_D = 6276 + + SMAX_VG4_4ZZ_H = 6277 + + SMAX_VG4_4ZZ_S = 6278 + + SMAX_ZI_B = 6279 + + SMAX_ZI_D = 6280 + + SMAX_ZI_H = 6281 + + SMAX_ZI_S = 6282 + + SMAX_ZPmZ_B = 6283 + + SMAX_ZPmZ_D = 6284 + + SMAX_ZPmZ_H = 6285 + + SMAX_ZPmZ_S = 6286 + + SMAXv16i8 = 6287 + + SMAXv2i32 = 6288 + + SMAXv4i16 = 6289 + + SMAXv4i32 = 6290 + + SMAXv8i16 = 6291 + + SMAXv8i8 = 6292 + + SMC = 6293 + + SMINP_ZPmZ_B = 6294 + + SMINP_ZPmZ_D = 6295 + + SMINP_ZPmZ_H = 6296 + + SMINP_ZPmZ_S = 6297 + + SMINPv16i8 = 6298 + + SMINPv2i32 = 6299 + + SMINPv4i16 = 6300 + + SMINPv4i32 = 6301 + + SMINPv8i16 = 6302 + + SMINPv8i8 = 6303 + + SMINQV_VPZ_B = 6304 + + SMINQV_VPZ_D = 6305 + + SMINQV_VPZ_H = 6306 + + SMINQV_VPZ_S = 6307 + + SMINV_VPZ_B = 6308 + + SMINV_VPZ_D = 6309 + + SMINV_VPZ_H = 6310 + + SMINV_VPZ_S = 6311 + + SMINVv16i8v = 6312 + + SMINVv4i16v = 6313 + + SMINVv4i32v = 6314 + + SMINVv8i16v = 6315 + + SMINVv8i8v = 6316 + + SMINWri = 6317 + + SMINWrr = 6318 + + SMINXri = 6319 + + SMINXrr = 6320 + + SMIN_VG2_2Z2Z_B = 6321 + + SMIN_VG2_2Z2Z_D = 6322 + + SMIN_VG2_2Z2Z_H = 6323 + + SMIN_VG2_2Z2Z_S = 6324 + + SMIN_VG2_2ZZ_B = 6325 + + SMIN_VG2_2ZZ_D = 6326 + + SMIN_VG2_2ZZ_H = 6327 + + SMIN_VG2_2ZZ_S = 6328 + + SMIN_VG4_4Z4Z_B = 6329 + + SMIN_VG4_4Z4Z_D = 6330 + + SMIN_VG4_4Z4Z_H = 6331 + + SMIN_VG4_4Z4Z_S = 6332 + + SMIN_VG4_4ZZ_B = 6333 + + SMIN_VG4_4ZZ_D = 6334 + + SMIN_VG4_4ZZ_H = 6335 + + SMIN_VG4_4ZZ_S = 6336 + + SMIN_ZI_B = 6337 + + SMIN_ZI_D = 6338 + + SMIN_ZI_H = 6339 + + SMIN_ZI_S = 6340 + + SMIN_ZPmZ_B = 6341 + + SMIN_ZPmZ_D = 6342 + + SMIN_ZPmZ_H = 6343 + + SMIN_ZPmZ_S = 6344 + + SMINv16i8 = 6345 + + SMINv2i32 = 6346 + + SMINv4i16 = 6347 + + SMINv4i32 = 6348 + + SMINv8i16 = 6349 + + SMINv8i8 = 6350 + + SMLALB_ZZZI_D = 6351 + + SMLALB_ZZZI_S = 6352 + + SMLALB_ZZZ_D = 6353 + + SMLALB_ZZZ_H = 6354 + + SMLALB_ZZZ_S = 6355 + + SMLALL_MZZI_BtoS = 6356 + + SMLALL_MZZI_HtoD = 6357 + + SMLALL_MZZ_BtoS = 6358 + + SMLALL_MZZ_HtoD = 6359 + + SMLALL_VG2_M2Z2Z_BtoS = 6360 + + SMLALL_VG2_M2Z2Z_HtoD = 6361 + + SMLALL_VG2_M2ZZI_BtoS = 6362 + + SMLALL_VG2_M2ZZI_HtoD = 6363 + + SMLALL_VG2_M2ZZ_BtoS = 6364 + + SMLALL_VG2_M2ZZ_HtoD = 6365 + + SMLALL_VG4_M4Z4Z_BtoS = 6366 + + SMLALL_VG4_M4Z4Z_HtoD = 6367 + + SMLALL_VG4_M4ZZI_BtoS = 6368 + + SMLALL_VG4_M4ZZI_HtoD = 6369 + + SMLALL_VG4_M4ZZ_BtoS = 6370 + + SMLALL_VG4_M4ZZ_HtoD = 6371 + + SMLALT_ZZZI_D = 6372 + + SMLALT_ZZZI_S = 6373 + + SMLALT_ZZZ_D = 6374 + + SMLALT_ZZZ_H = 6375 + + SMLALT_ZZZ_S = 6376 + + SMLAL_MZZI_HtoS = 6377 + + SMLAL_MZZ_HtoS = 6378 + + SMLAL_VG2_M2Z2Z_HtoS = 6379 + + SMLAL_VG2_M2ZZI_S = 6380 + + SMLAL_VG2_M2ZZ_HtoS = 6381 + + SMLAL_VG4_M4Z4Z_HtoS = 6382 + + SMLAL_VG4_M4ZZI_HtoS = 6383 + + SMLAL_VG4_M4ZZ_HtoS = 6384 + + SMLALv16i8_v8i16 = 6385 + + SMLALv2i32_indexed = 6386 + + SMLALv2i32_v2i64 = 6387 + + SMLALv4i16_indexed = 6388 + + SMLALv4i16_v4i32 = 6389 + + SMLALv4i32_indexed = 6390 + + SMLALv4i32_v2i64 = 6391 + + SMLALv8i16_indexed = 6392 + + SMLALv8i16_v4i32 = 6393 + + SMLALv8i8_v8i16 = 6394 + + SMLSLB_ZZZI_D = 6395 + + SMLSLB_ZZZI_S = 6396 + + SMLSLB_ZZZ_D = 6397 + + SMLSLB_ZZZ_H = 6398 + + SMLSLB_ZZZ_S = 6399 + + SMLSLL_MZZI_BtoS = 6400 + + SMLSLL_MZZI_HtoD = 6401 + + SMLSLL_MZZ_BtoS = 6402 + + SMLSLL_MZZ_HtoD = 6403 + + SMLSLL_VG2_M2Z2Z_BtoS = 6404 + + SMLSLL_VG2_M2Z2Z_HtoD = 6405 + + SMLSLL_VG2_M2ZZI_BtoS = 6406 + + SMLSLL_VG2_M2ZZI_HtoD = 6407 + + SMLSLL_VG2_M2ZZ_BtoS = 6408 + + SMLSLL_VG2_M2ZZ_HtoD = 6409 + + SMLSLL_VG4_M4Z4Z_BtoS = 6410 + + SMLSLL_VG4_M4Z4Z_HtoD = 6411 + + SMLSLL_VG4_M4ZZI_BtoS = 6412 + + SMLSLL_VG4_M4ZZI_HtoD = 6413 + + SMLSLL_VG4_M4ZZ_BtoS = 6414 + + SMLSLL_VG4_M4ZZ_HtoD = 6415 + + SMLSLT_ZZZI_D = 6416 + + SMLSLT_ZZZI_S = 6417 + + SMLSLT_ZZZ_D = 6418 + + SMLSLT_ZZZ_H = 6419 + + SMLSLT_ZZZ_S = 6420 + + SMLSL_MZZI_HtoS = 6421 + + SMLSL_MZZ_HtoS = 6422 + + SMLSL_VG2_M2Z2Z_HtoS = 6423 + + SMLSL_VG2_M2ZZI_S = 6424 + + SMLSL_VG2_M2ZZ_HtoS = 6425 + + SMLSL_VG4_M4Z4Z_HtoS = 6426 + + SMLSL_VG4_M4ZZI_HtoS = 6427 + + SMLSL_VG4_M4ZZ_HtoS = 6428 + + SMLSLv16i8_v8i16 = 6429 + + SMLSLv2i32_indexed = 6430 + + SMLSLv2i32_v2i64 = 6431 + + SMLSLv4i16_indexed = 6432 + + SMLSLv4i16_v4i32 = 6433 + + SMLSLv4i32_indexed = 6434 + + SMLSLv4i32_v2i64 = 6435 + + SMLSLv8i16_indexed = 6436 + + SMLSLv8i16_v4i32 = 6437 + + SMLSLv8i8_v8i16 = 6438 + + SMMLA = 6439 + + SMMLA_ZZZ = 6440 + + SMOP4A_M2Z2Z_BToS = 6441 + + SMOP4A_M2Z2Z_HToS = 6442 + + SMOP4A_M2Z2Z_HtoD = 6443 + + SMOP4A_M2ZZ_BToS = 6444 + + SMOP4A_M2ZZ_HToS = 6445 + + SMOP4A_M2ZZ_HtoD = 6446 + + SMOP4A_MZ2Z_BToS = 6447 + + SMOP4A_MZ2Z_HToS = 6448 + + SMOP4A_MZ2Z_HtoD = 6449 + + SMOP4A_MZZ_BToS = 6450 + + SMOP4A_MZZ_HToS = 6451 + + SMOP4A_MZZ_HtoD = 6452 + + SMOP4S_M2Z2Z_BToS = 6453 + + SMOP4S_M2Z2Z_HToS = 6454 + + SMOP4S_M2Z2Z_HtoD = 6455 + + SMOP4S_M2ZZ_BToS = 6456 + + SMOP4S_M2ZZ_HToS = 6457 + + SMOP4S_M2ZZ_HtoD = 6458 + + SMOP4S_MZ2Z_BToS = 6459 + + SMOP4S_MZ2Z_HToS = 6460 + + SMOP4S_MZ2Z_HtoD = 6461 + + SMOP4S_MZZ_BToS = 6462 + + SMOP4S_MZZ_HToS = 6463 + + SMOP4S_MZZ_HtoD = 6464 + + SMOPA_MPPZZ_D = 6465 + + SMOPA_MPPZZ_HtoS = 6466 + + SMOPA_MPPZZ_S = 6467 + + SMOPS_MPPZZ_D = 6468 + + SMOPS_MPPZZ_HtoS = 6469 + + SMOPS_MPPZZ_S = 6470 + + SMOVvi16to32 = 6471 + + SMOVvi16to32_idx0 = 6472 + + SMOVvi16to64 = 6473 + + SMOVvi16to64_idx0 = 6474 + + SMOVvi32to64 = 6475 + + SMOVvi32to64_idx0 = 6476 + + SMOVvi8to32 = 6477 + + SMOVvi8to32_idx0 = 6478 + + SMOVvi8to64 = 6479 + + SMOVvi8to64_idx0 = 6480 + + SMSUBLrrr = 6481 + + SMULH_ZPmZ_B = 6482 + + SMULH_ZPmZ_D = 6483 + + SMULH_ZPmZ_H = 6484 + + SMULH_ZPmZ_S = 6485 + + SMULH_ZZZ_B = 6486 + + SMULH_ZZZ_D = 6487 + + SMULH_ZZZ_H = 6488 + + SMULH_ZZZ_S = 6489 + + SMULHrr = 6490 + + SMULLB_ZZZI_D = 6491 + + SMULLB_ZZZI_S = 6492 + + SMULLB_ZZZ_D = 6493 + + SMULLB_ZZZ_H = 6494 + + SMULLB_ZZZ_S = 6495 + + SMULLT_ZZZI_D = 6496 + + SMULLT_ZZZI_S = 6497 + + SMULLT_ZZZ_D = 6498 + + SMULLT_ZZZ_H = 6499 + + SMULLT_ZZZ_S = 6500 + + SMULLv16i8_v8i16 = 6501 + + SMULLv2i32_indexed = 6502 + + SMULLv2i32_v2i64 = 6503 + + SMULLv4i16_indexed = 6504 + + SMULLv4i16_v4i32 = 6505 + + SMULLv4i32_indexed = 6506 + + SMULLv4i32_v2i64 = 6507 + + SMULLv8i16_indexed = 6508 + + SMULLv8i16_v4i32 = 6509 + + SMULLv8i8_v8i16 = 6510 + + SPLICE_ZPZZ_B = 6511 + + SPLICE_ZPZZ_D = 6512 + + SPLICE_ZPZZ_H = 6513 + + SPLICE_ZPZZ_S = 6514 + + SPLICE_ZPZ_B = 6515 + + SPLICE_ZPZ_D = 6516 + + SPLICE_ZPZ_H = 6517 + + SPLICE_ZPZ_S = 6518 + + SQABS_ZPmZ_B = 6519 + + SQABS_ZPmZ_D = 6520 + + SQABS_ZPmZ_H = 6521 + + SQABS_ZPmZ_S = 6522 + + SQABS_ZPzZ_B = 6523 + + SQABS_ZPzZ_D = 6524 + + SQABS_ZPzZ_H = 6525 + + SQABS_ZPzZ_S = 6526 + + SQABSv16i8 = 6527 + + SQABSv1i16 = 6528 + + SQABSv1i32 = 6529 + + SQABSv1i64 = 6530 + + SQABSv1i8 = 6531 + + SQABSv2i32 = 6532 + + SQABSv2i64 = 6533 + + SQABSv4i16 = 6534 + + SQABSv4i32 = 6535 + + SQABSv8i16 = 6536 + + SQABSv8i8 = 6537 + + SQADD_ZI_B = 6538 + + SQADD_ZI_D = 6539 + + SQADD_ZI_H = 6540 + + SQADD_ZI_S = 6541 + + SQADD_ZPmZ_B = 6542 + + SQADD_ZPmZ_D = 6543 + + SQADD_ZPmZ_H = 6544 + + SQADD_ZPmZ_S = 6545 + + SQADD_ZZZ_B = 6546 + + SQADD_ZZZ_D = 6547 + + SQADD_ZZZ_H = 6548 + + SQADD_ZZZ_S = 6549 + + SQADDv16i8 = 6550 + + SQADDv1i16 = 6551 + + SQADDv1i32 = 6552 + + SQADDv1i64 = 6553 + + SQADDv1i8 = 6554 + + SQADDv2i32 = 6555 + + SQADDv2i64 = 6556 + + SQADDv4i16 = 6557 + + SQADDv4i32 = 6558 + + SQADDv8i16 = 6559 + + SQADDv8i8 = 6560 + + SQCADD_ZZI_B = 6561 + + SQCADD_ZZI_D = 6562 + + SQCADD_ZZI_H = 6563 + + SQCADD_ZZI_S = 6564 + + SQCVTN_Z2Z_StoH = 6565 + + SQCVTN_Z4Z_DtoH = 6566 + + SQCVTN_Z4Z_StoB = 6567 + + SQCVTUN_Z2Z_StoH = 6568 + + SQCVTUN_Z4Z_DtoH = 6569 + + SQCVTUN_Z4Z_StoB = 6570 + + SQCVTU_Z2Z_StoH = 6571 + + SQCVTU_Z4Z_DtoH = 6572 + + SQCVTU_Z4Z_StoB = 6573 + + SQCVT_Z2Z_StoH = 6574 + + SQCVT_Z4Z_DtoH = 6575 + + SQCVT_Z4Z_StoB = 6576 + + SQDECB_XPiI = 6577 + + SQDECB_XPiWdI = 6578 + + SQDECD_XPiI = 6579 + + SQDECD_XPiWdI = 6580 + + SQDECD_ZPiI = 6581 + + SQDECH_XPiI = 6582 + + SQDECH_XPiWdI = 6583 + + SQDECH_ZPiI = 6584 + + SQDECP_XPWd_B = 6585 + + SQDECP_XPWd_D = 6586 + + SQDECP_XPWd_H = 6587 + + SQDECP_XPWd_S = 6588 + + SQDECP_XP_B = 6589 + + SQDECP_XP_D = 6590 + + SQDECP_XP_H = 6591 + + SQDECP_XP_S = 6592 + + SQDECP_ZP_D = 6593 + + SQDECP_ZP_H = 6594 + + SQDECP_ZP_S = 6595 + + SQDECW_XPiI = 6596 + + SQDECW_XPiWdI = 6597 + + SQDECW_ZPiI = 6598 + + SQDMLALBT_ZZZ_D = 6599 + + SQDMLALBT_ZZZ_H = 6600 + + SQDMLALBT_ZZZ_S = 6601 + + SQDMLALB_ZZZI_D = 6602 + + SQDMLALB_ZZZI_S = 6603 + + SQDMLALB_ZZZ_D = 6604 + + SQDMLALB_ZZZ_H = 6605 + + SQDMLALB_ZZZ_S = 6606 + + SQDMLALT_ZZZI_D = 6607 + + SQDMLALT_ZZZI_S = 6608 + + SQDMLALT_ZZZ_D = 6609 + + SQDMLALT_ZZZ_H = 6610 + + SQDMLALT_ZZZ_S = 6611 + + SQDMLALi16 = 6612 + + SQDMLALi32 = 6613 + + SQDMLALv1i32_indexed = 6614 + + SQDMLALv1i64_indexed = 6615 + + SQDMLALv2i32_indexed = 6616 + + SQDMLALv2i32_v2i64 = 6617 + + SQDMLALv4i16_indexed = 6618 + + SQDMLALv4i16_v4i32 = 6619 + + SQDMLALv4i32_indexed = 6620 + + SQDMLALv4i32_v2i64 = 6621 + + SQDMLALv8i16_indexed = 6622 + + SQDMLALv8i16_v4i32 = 6623 + + SQDMLSLBT_ZZZ_D = 6624 + + SQDMLSLBT_ZZZ_H = 6625 + + SQDMLSLBT_ZZZ_S = 6626 + + SQDMLSLB_ZZZI_D = 6627 + + SQDMLSLB_ZZZI_S = 6628 + + SQDMLSLB_ZZZ_D = 6629 + + SQDMLSLB_ZZZ_H = 6630 + + SQDMLSLB_ZZZ_S = 6631 + + SQDMLSLT_ZZZI_D = 6632 + + SQDMLSLT_ZZZI_S = 6633 + + SQDMLSLT_ZZZ_D = 6634 + + SQDMLSLT_ZZZ_H = 6635 + + SQDMLSLT_ZZZ_S = 6636 + + SQDMLSLi16 = 6637 + + SQDMLSLi32 = 6638 + + SQDMLSLv1i32_indexed = 6639 + + SQDMLSLv1i64_indexed = 6640 + + SQDMLSLv2i32_indexed = 6641 + + SQDMLSLv2i32_v2i64 = 6642 + + SQDMLSLv4i16_indexed = 6643 + + SQDMLSLv4i16_v4i32 = 6644 + + SQDMLSLv4i32_indexed = 6645 + + SQDMLSLv4i32_v2i64 = 6646 + + SQDMLSLv8i16_indexed = 6647 + + SQDMLSLv8i16_v4i32 = 6648 + + SQDMULH_VG2_2Z2Z_B = 6649 + + SQDMULH_VG2_2Z2Z_D = 6650 + + SQDMULH_VG2_2Z2Z_H = 6651 + + SQDMULH_VG2_2Z2Z_S = 6652 + + SQDMULH_VG2_2ZZ_B = 6653 + + SQDMULH_VG2_2ZZ_D = 6654 + + SQDMULH_VG2_2ZZ_H = 6655 + + SQDMULH_VG2_2ZZ_S = 6656 + + SQDMULH_VG4_4Z4Z_B = 6657 + + SQDMULH_VG4_4Z4Z_D = 6658 + + SQDMULH_VG4_4Z4Z_H = 6659 + + SQDMULH_VG4_4Z4Z_S = 6660 + + SQDMULH_VG4_4ZZ_B = 6661 + + SQDMULH_VG4_4ZZ_D = 6662 + + SQDMULH_VG4_4ZZ_H = 6663 + + SQDMULH_VG4_4ZZ_S = 6664 + + SQDMULH_ZZZI_D = 6665 + + SQDMULH_ZZZI_H = 6666 + + SQDMULH_ZZZI_S = 6667 + + SQDMULH_ZZZ_B = 6668 + + SQDMULH_ZZZ_D = 6669 + + SQDMULH_ZZZ_H = 6670 + + SQDMULH_ZZZ_S = 6671 + + SQDMULHv1i16 = 6672 + + SQDMULHv1i16_indexed = 6673 + + SQDMULHv1i32 = 6674 + + SQDMULHv1i32_indexed = 6675 + + SQDMULHv2i32 = 6676 + + SQDMULHv2i32_indexed = 6677 + + SQDMULHv4i16 = 6678 + + SQDMULHv4i16_indexed = 6679 + + SQDMULHv4i32 = 6680 + + SQDMULHv4i32_indexed = 6681 + + SQDMULHv8i16 = 6682 + + SQDMULHv8i16_indexed = 6683 + + SQDMULLB_ZZZI_D = 6684 + + SQDMULLB_ZZZI_S = 6685 + + SQDMULLB_ZZZ_D = 6686 + + SQDMULLB_ZZZ_H = 6687 + + SQDMULLB_ZZZ_S = 6688 + + SQDMULLT_ZZZI_D = 6689 + + SQDMULLT_ZZZI_S = 6690 + + SQDMULLT_ZZZ_D = 6691 + + SQDMULLT_ZZZ_H = 6692 + + SQDMULLT_ZZZ_S = 6693 + + SQDMULLi16 = 6694 + + SQDMULLi32 = 6695 + + SQDMULLv1i32_indexed = 6696 + + SQDMULLv1i64_indexed = 6697 + + SQDMULLv2i32_indexed = 6698 + + SQDMULLv2i32_v2i64 = 6699 + + SQDMULLv4i16_indexed = 6700 + + SQDMULLv4i16_v4i32 = 6701 + + SQDMULLv4i32_indexed = 6702 + + SQDMULLv4i32_v2i64 = 6703 + + SQDMULLv8i16_indexed = 6704 + + SQDMULLv8i16_v4i32 = 6705 + + SQINCB_XPiI = 6706 + + SQINCB_XPiWdI = 6707 + + SQINCD_XPiI = 6708 + + SQINCD_XPiWdI = 6709 + + SQINCD_ZPiI = 6710 + + SQINCH_XPiI = 6711 + + SQINCH_XPiWdI = 6712 + + SQINCH_ZPiI = 6713 + + SQINCP_XPWd_B = 6714 + + SQINCP_XPWd_D = 6715 + + SQINCP_XPWd_H = 6716 + + SQINCP_XPWd_S = 6717 + + SQINCP_XP_B = 6718 + + SQINCP_XP_D = 6719 + + SQINCP_XP_H = 6720 + + SQINCP_XP_S = 6721 + + SQINCP_ZP_D = 6722 + + SQINCP_ZP_H = 6723 + + SQINCP_ZP_S = 6724 + + SQINCW_XPiI = 6725 + + SQINCW_XPiWdI = 6726 + + SQINCW_ZPiI = 6727 + + SQNEG_ZPmZ_B = 6728 + + SQNEG_ZPmZ_D = 6729 + + SQNEG_ZPmZ_H = 6730 + + SQNEG_ZPmZ_S = 6731 + + SQNEG_ZPzZ_B = 6732 + + SQNEG_ZPzZ_D = 6733 + + SQNEG_ZPzZ_H = 6734 + + SQNEG_ZPzZ_S = 6735 + + SQNEGv16i8 = 6736 + + SQNEGv1i16 = 6737 + + SQNEGv1i32 = 6738 + + SQNEGv1i64 = 6739 + + SQNEGv1i8 = 6740 + + SQNEGv2i32 = 6741 + + SQNEGv2i64 = 6742 + + SQNEGv4i16 = 6743 + + SQNEGv4i32 = 6744 + + SQNEGv8i16 = 6745 + + SQNEGv8i8 = 6746 + + SQRDCMLAH_ZZZI_H = 6747 + + SQRDCMLAH_ZZZI_S = 6748 + + SQRDCMLAH_ZZZ_B = 6749 + + SQRDCMLAH_ZZZ_D = 6750 + + SQRDCMLAH_ZZZ_H = 6751 + + SQRDCMLAH_ZZZ_S = 6752 + + SQRDMLAH_ZZZI_D = 6753 + + SQRDMLAH_ZZZI_H = 6754 + + SQRDMLAH_ZZZI_S = 6755 + + SQRDMLAH_ZZZ_B = 6756 + + SQRDMLAH_ZZZ_D = 6757 + + SQRDMLAH_ZZZ_H = 6758 + + SQRDMLAH_ZZZ_S = 6759 + + SQRDMLAHv1i16 = 6760 + + SQRDMLAHv1i16_indexed = 6761 + + SQRDMLAHv1i32 = 6762 + + SQRDMLAHv1i32_indexed = 6763 + + SQRDMLAHv2i32 = 6764 + + SQRDMLAHv2i32_indexed = 6765 + + SQRDMLAHv4i16 = 6766 + + SQRDMLAHv4i16_indexed = 6767 + + SQRDMLAHv4i32 = 6768 + + SQRDMLAHv4i32_indexed = 6769 + + SQRDMLAHv8i16 = 6770 + + SQRDMLAHv8i16_indexed = 6771 + + SQRDMLSH_ZZZI_D = 6772 + + SQRDMLSH_ZZZI_H = 6773 + + SQRDMLSH_ZZZI_S = 6774 + + SQRDMLSH_ZZZ_B = 6775 + + SQRDMLSH_ZZZ_D = 6776 + + SQRDMLSH_ZZZ_H = 6777 + + SQRDMLSH_ZZZ_S = 6778 + + SQRDMLSHv1i16 = 6779 + + SQRDMLSHv1i16_indexed = 6780 + + SQRDMLSHv1i32 = 6781 + + SQRDMLSHv1i32_indexed = 6782 + + SQRDMLSHv2i32 = 6783 + + SQRDMLSHv2i32_indexed = 6784 + + SQRDMLSHv4i16 = 6785 + + SQRDMLSHv4i16_indexed = 6786 + + SQRDMLSHv4i32 = 6787 + + SQRDMLSHv4i32_indexed = 6788 + + SQRDMLSHv8i16 = 6789 + + SQRDMLSHv8i16_indexed = 6790 + + SQRDMULH_ZZZI_D = 6791 + + SQRDMULH_ZZZI_H = 6792 + + SQRDMULH_ZZZI_S = 6793 + + SQRDMULH_ZZZ_B = 6794 + + SQRDMULH_ZZZ_D = 6795 + + SQRDMULH_ZZZ_H = 6796 + + SQRDMULH_ZZZ_S = 6797 + + SQRDMULHv1i16 = 6798 + + SQRDMULHv1i16_indexed = 6799 + + SQRDMULHv1i32 = 6800 + + SQRDMULHv1i32_indexed = 6801 + + SQRDMULHv2i32 = 6802 + + SQRDMULHv2i32_indexed = 6803 + + SQRDMULHv4i16 = 6804 + + SQRDMULHv4i16_indexed = 6805 + + SQRDMULHv4i32 = 6806 + + SQRDMULHv4i32_indexed = 6807 + + SQRDMULHv8i16 = 6808 + + SQRDMULHv8i16_indexed = 6809 + + SQRSHLR_ZPmZ_B = 6810 + + SQRSHLR_ZPmZ_D = 6811 + + SQRSHLR_ZPmZ_H = 6812 + + SQRSHLR_ZPmZ_S = 6813 + + SQRSHL_ZPmZ_B = 6814 + + SQRSHL_ZPmZ_D = 6815 + + SQRSHL_ZPmZ_H = 6816 + + SQRSHL_ZPmZ_S = 6817 + + SQRSHLv16i8 = 6818 + + SQRSHLv1i16 = 6819 + + SQRSHLv1i32 = 6820 + + SQRSHLv1i64 = 6821 + + SQRSHLv1i8 = 6822 + + SQRSHLv2i32 = 6823 + + SQRSHLv2i64 = 6824 + + SQRSHLv4i16 = 6825 + + SQRSHLv4i32 = 6826 + + SQRSHLv8i16 = 6827 + + SQRSHLv8i8 = 6828 + + SQRSHRNB_ZZI_B = 6829 + + SQRSHRNB_ZZI_H = 6830 + + SQRSHRNB_ZZI_S = 6831 + + SQRSHRNT_ZZI_B = 6832 + + SQRSHRNT_ZZI_H = 6833 + + SQRSHRNT_ZZI_S = 6834 + + SQRSHRN_VG4_Z4ZI_B = 6835 + + SQRSHRN_VG4_Z4ZI_H = 6836 + + SQRSHRN_Z2ZI_HtoB = 6837 + + SQRSHRN_Z2ZI_StoH = 6838 + + SQRSHRNb = 6839 + + SQRSHRNh = 6840 + + SQRSHRNs = 6841 + + SQRSHRNv16i8_shift = 6842 + + SQRSHRNv2i32_shift = 6843 + + SQRSHRNv4i16_shift = 6844 + + SQRSHRNv4i32_shift = 6845 + + SQRSHRNv8i16_shift = 6846 + + SQRSHRNv8i8_shift = 6847 + + SQRSHRUNB_ZZI_B = 6848 + + SQRSHRUNB_ZZI_H = 6849 + + SQRSHRUNB_ZZI_S = 6850 + + SQRSHRUNT_ZZI_B = 6851 + + SQRSHRUNT_ZZI_H = 6852 + + SQRSHRUNT_ZZI_S = 6853 + + SQRSHRUN_VG4_Z4ZI_B = 6854 + + SQRSHRUN_VG4_Z4ZI_H = 6855 + + SQRSHRUN_Z2ZI_HtoB = 6856 + + SQRSHRUN_Z2ZI_StoH = 6857 + + SQRSHRUNb = 6858 + + SQRSHRUNh = 6859 + + SQRSHRUNs = 6860 + + SQRSHRUNv16i8_shift = 6861 + + SQRSHRUNv2i32_shift = 6862 + + SQRSHRUNv4i16_shift = 6863 + + SQRSHRUNv4i32_shift = 6864 + + SQRSHRUNv8i16_shift = 6865 + + SQRSHRUNv8i8_shift = 6866 + + SQRSHRU_VG2_Z2ZI_H = 6867 + + SQRSHRU_VG4_Z4ZI_B = 6868 + + SQRSHRU_VG4_Z4ZI_H = 6869 + + SQRSHR_VG2_Z2ZI_H = 6870 + + SQRSHR_VG4_Z4ZI_B = 6871 + + SQRSHR_VG4_Z4ZI_H = 6872 + + SQSHLR_ZPmZ_B = 6873 + + SQSHLR_ZPmZ_D = 6874 + + SQSHLR_ZPmZ_H = 6875 + + SQSHLR_ZPmZ_S = 6876 + + SQSHLU_ZPmI_B = 6877 + + SQSHLU_ZPmI_D = 6878 + + SQSHLU_ZPmI_H = 6879 + + SQSHLU_ZPmI_S = 6880 + + SQSHLUb = 6881 + + SQSHLUd = 6882 + + SQSHLUh = 6883 + + SQSHLUs = 6884 + + SQSHLUv16i8_shift = 6885 + + SQSHLUv2i32_shift = 6886 + + SQSHLUv2i64_shift = 6887 + + SQSHLUv4i16_shift = 6888 + + SQSHLUv4i32_shift = 6889 + + SQSHLUv8i16_shift = 6890 + + SQSHLUv8i8_shift = 6891 + + SQSHL_ZPmI_B = 6892 + + SQSHL_ZPmI_D = 6893 + + SQSHL_ZPmI_H = 6894 + + SQSHL_ZPmI_S = 6895 + + SQSHL_ZPmZ_B = 6896 + + SQSHL_ZPmZ_D = 6897 + + SQSHL_ZPmZ_H = 6898 + + SQSHL_ZPmZ_S = 6899 + + SQSHLb = 6900 + + SQSHLd = 6901 + + SQSHLh = 6902 + + SQSHLs = 6903 + + SQSHLv16i8 = 6904 + + SQSHLv16i8_shift = 6905 + + SQSHLv1i16 = 6906 + + SQSHLv1i32 = 6907 + + SQSHLv1i64 = 6908 + + SQSHLv1i8 = 6909 + + SQSHLv2i32 = 6910 + + SQSHLv2i32_shift = 6911 + + SQSHLv2i64 = 6912 + + SQSHLv2i64_shift = 6913 + + SQSHLv4i16 = 6914 + + SQSHLv4i16_shift = 6915 + + SQSHLv4i32 = 6916 + + SQSHLv4i32_shift = 6917 + + SQSHLv8i16 = 6918 + + SQSHLv8i16_shift = 6919 + + SQSHLv8i8 = 6920 + + SQSHLv8i8_shift = 6921 + + SQSHRNB_ZZI_B = 6922 + + SQSHRNB_ZZI_H = 6923 + + SQSHRNB_ZZI_S = 6924 + + SQSHRNT_ZZI_B = 6925 + + SQSHRNT_ZZI_H = 6926 + + SQSHRNT_ZZI_S = 6927 + + SQSHRN_Z2ZI_HtoB = 6928 + + SQSHRN_Z2ZI_StoH = 6929 + + SQSHRNb = 6930 + + SQSHRNh = 6931 + + SQSHRNs = 6932 + + SQSHRNv16i8_shift = 6933 + + SQSHRNv2i32_shift = 6934 + + SQSHRNv4i16_shift = 6935 + + SQSHRNv4i32_shift = 6936 + + SQSHRNv8i16_shift = 6937 + + SQSHRNv8i8_shift = 6938 + + SQSHRUNB_ZZI_B = 6939 + + SQSHRUNB_ZZI_H = 6940 + + SQSHRUNB_ZZI_S = 6941 + + SQSHRUNT_ZZI_B = 6942 + + SQSHRUNT_ZZI_H = 6943 + + SQSHRUNT_ZZI_S = 6944 + + SQSHRUN_Z2ZI_HtoB = 6945 + + SQSHRUN_Z2ZI_StoH = 6946 + + SQSHRUNb = 6947 + + SQSHRUNh = 6948 + + SQSHRUNs = 6949 + + SQSHRUNv16i8_shift = 6950 + + SQSHRUNv2i32_shift = 6951 + + SQSHRUNv4i16_shift = 6952 + + SQSHRUNv4i32_shift = 6953 + + SQSHRUNv8i16_shift = 6954 + + SQSHRUNv8i8_shift = 6955 + + SQSUBR_ZPmZ_B = 6956 + + SQSUBR_ZPmZ_D = 6957 + + SQSUBR_ZPmZ_H = 6958 + + SQSUBR_ZPmZ_S = 6959 + + SQSUB_ZI_B = 6960 + + SQSUB_ZI_D = 6961 + + SQSUB_ZI_H = 6962 + + SQSUB_ZI_S = 6963 + + SQSUB_ZPmZ_B = 6964 + + SQSUB_ZPmZ_D = 6965 + + SQSUB_ZPmZ_H = 6966 + + SQSUB_ZPmZ_S = 6967 + + SQSUB_ZZZ_B = 6968 + + SQSUB_ZZZ_D = 6969 + + SQSUB_ZZZ_H = 6970 + + SQSUB_ZZZ_S = 6971 + + SQSUBv16i8 = 6972 + + SQSUBv1i16 = 6973 + + SQSUBv1i32 = 6974 + + SQSUBv1i64 = 6975 + + SQSUBv1i8 = 6976 + + SQSUBv2i32 = 6977 + + SQSUBv2i64 = 6978 + + SQSUBv4i16 = 6979 + + SQSUBv4i32 = 6980 + + SQSUBv8i16 = 6981 + + SQSUBv8i8 = 6982 + + SQXTNB_ZZ_B = 6983 + + SQXTNB_ZZ_H = 6984 + + SQXTNB_ZZ_S = 6985 + + SQXTNT_ZZ_B = 6986 + + SQXTNT_ZZ_H = 6987 + + SQXTNT_ZZ_S = 6988 + + SQXTNv16i8 = 6989 + + SQXTNv1i16 = 6990 + + SQXTNv1i32 = 6991 + + SQXTNv1i8 = 6992 + + SQXTNv2i32 = 6993 + + SQXTNv4i16 = 6994 + + SQXTNv4i32 = 6995 + + SQXTNv8i16 = 6996 + + SQXTNv8i8 = 6997 + + SQXTUNB_ZZ_B = 6998 + + SQXTUNB_ZZ_H = 6999 + + SQXTUNB_ZZ_S = 7000 + + SQXTUNT_ZZ_B = 7001 + + SQXTUNT_ZZ_H = 7002 + + SQXTUNT_ZZ_S = 7003 + + SQXTUNv16i8 = 7004 + + SQXTUNv1i16 = 7005 + + SQXTUNv1i32 = 7006 + + SQXTUNv1i8 = 7007 + + SQXTUNv2i32 = 7008 + + SQXTUNv4i16 = 7009 + + SQXTUNv4i32 = 7010 + + SQXTUNv8i16 = 7011 + + SQXTUNv8i8 = 7012 + + SRHADD_ZPmZ_B = 7013 + + SRHADD_ZPmZ_D = 7014 + + SRHADD_ZPmZ_H = 7015 + + SRHADD_ZPmZ_S = 7016 + + SRHADDv16i8 = 7017 + + SRHADDv2i32 = 7018 + + SRHADDv4i16 = 7019 + + SRHADDv4i32 = 7020 + + SRHADDv8i16 = 7021 + + SRHADDv8i8 = 7022 + + SRI_ZZI_B = 7023 + + SRI_ZZI_D = 7024 + + SRI_ZZI_H = 7025 + + SRI_ZZI_S = 7026 + + SRId = 7027 + + SRIv16i8_shift = 7028 + + SRIv2i32_shift = 7029 + + SRIv2i64_shift = 7030 + + SRIv4i16_shift = 7031 + + SRIv4i32_shift = 7032 + + SRIv8i16_shift = 7033 + + SRIv8i8_shift = 7034 + + SRSHLR_ZPmZ_B = 7035 + + SRSHLR_ZPmZ_D = 7036 + + SRSHLR_ZPmZ_H = 7037 + + SRSHLR_ZPmZ_S = 7038 + + SRSHL_VG2_2Z2Z_B = 7039 + + SRSHL_VG2_2Z2Z_D = 7040 + + SRSHL_VG2_2Z2Z_H = 7041 + + SRSHL_VG2_2Z2Z_S = 7042 + + SRSHL_VG2_2ZZ_B = 7043 + + SRSHL_VG2_2ZZ_D = 7044 + + SRSHL_VG2_2ZZ_H = 7045 + + SRSHL_VG2_2ZZ_S = 7046 + + SRSHL_VG4_4Z4Z_B = 7047 + + SRSHL_VG4_4Z4Z_D = 7048 + + SRSHL_VG4_4Z4Z_H = 7049 + + SRSHL_VG4_4Z4Z_S = 7050 + + SRSHL_VG4_4ZZ_B = 7051 + + SRSHL_VG4_4ZZ_D = 7052 + + SRSHL_VG4_4ZZ_H = 7053 + + SRSHL_VG4_4ZZ_S = 7054 + + SRSHL_ZPmZ_B = 7055 + + SRSHL_ZPmZ_D = 7056 + + SRSHL_ZPmZ_H = 7057 + + SRSHL_ZPmZ_S = 7058 + + SRSHLv16i8 = 7059 + + SRSHLv1i64 = 7060 + + SRSHLv2i32 = 7061 + + SRSHLv2i64 = 7062 + + SRSHLv4i16 = 7063 + + SRSHLv4i32 = 7064 + + SRSHLv8i16 = 7065 + + SRSHLv8i8 = 7066 + + SRSHR_ZPmI_B = 7067 + + SRSHR_ZPmI_D = 7068 + + SRSHR_ZPmI_H = 7069 + + SRSHR_ZPmI_S = 7070 + + SRSHRd = 7071 + + SRSHRv16i8_shift = 7072 + + SRSHRv2i32_shift = 7073 + + SRSHRv2i64_shift = 7074 + + SRSHRv4i16_shift = 7075 + + SRSHRv4i32_shift = 7076 + + SRSHRv8i16_shift = 7077 + + SRSHRv8i8_shift = 7078 + + SRSRA_ZZI_B = 7079 + + SRSRA_ZZI_D = 7080 + + SRSRA_ZZI_H = 7081 + + SRSRA_ZZI_S = 7082 + + SRSRAd = 7083 + + SRSRAv16i8_shift = 7084 + + SRSRAv2i32_shift = 7085 + + SRSRAv2i64_shift = 7086 + + SRSRAv4i16_shift = 7087 + + SRSRAv4i32_shift = 7088 + + SRSRAv8i16_shift = 7089 + + SRSRAv8i8_shift = 7090 + + SSHLLB_ZZI_D = 7091 + + SSHLLB_ZZI_H = 7092 + + SSHLLB_ZZI_S = 7093 + + SSHLLT_ZZI_D = 7094 + + SSHLLT_ZZI_H = 7095 + + SSHLLT_ZZI_S = 7096 + + SSHLLv16i8_shift = 7097 + + SSHLLv2i32_shift = 7098 + + SSHLLv4i16_shift = 7099 + + SSHLLv4i32_shift = 7100 + + SSHLLv8i16_shift = 7101 + + SSHLLv8i8_shift = 7102 + + SSHLv16i8 = 7103 + + SSHLv1i64 = 7104 + + SSHLv2i32 = 7105 + + SSHLv2i64 = 7106 + + SSHLv4i16 = 7107 + + SSHLv4i32 = 7108 + + SSHLv8i16 = 7109 + + SSHLv8i8 = 7110 + + SSHRd = 7111 + + SSHRv16i8_shift = 7112 + + SSHRv2i32_shift = 7113 + + SSHRv2i64_shift = 7114 + + SSHRv4i16_shift = 7115 + + SSHRv4i32_shift = 7116 + + SSHRv8i16_shift = 7117 + + SSHRv8i8_shift = 7118 + + SSRA_ZZI_B = 7119 + + SSRA_ZZI_D = 7120 + + SSRA_ZZI_H = 7121 + + SSRA_ZZI_S = 7122 + + SSRAd = 7123 + + SSRAv16i8_shift = 7124 + + SSRAv2i32_shift = 7125 + + SSRAv2i64_shift = 7126 + + SSRAv4i16_shift = 7127 + + SSRAv4i32_shift = 7128 + + SSRAv8i16_shift = 7129 + + SSRAv8i8_shift = 7130 + + SST1B_D = 7131 + + SST1B_D_IMM = 7132 + + SST1B_D_SXTW = 7133 + + SST1B_D_UXTW = 7134 + + SST1B_S_IMM = 7135 + + SST1B_S_SXTW = 7136 + + SST1B_S_UXTW = 7137 + + SST1D = 7138 + + SST1D_IMM = 7139 + + SST1D_SCALED = 7140 + + SST1D_SXTW = 7141 + + SST1D_SXTW_SCALED = 7142 + + SST1D_UXTW = 7143 + + SST1D_UXTW_SCALED = 7144 + + SST1H_D = 7145 + + SST1H_D_IMM = 7146 + + SST1H_D_SCALED = 7147 + + SST1H_D_SXTW = 7148 + + SST1H_D_SXTW_SCALED = 7149 + + SST1H_D_UXTW = 7150 + + SST1H_D_UXTW_SCALED = 7151 + + SST1H_S_IMM = 7152 + + SST1H_S_SXTW = 7153 + + SST1H_S_SXTW_SCALED = 7154 + + SST1H_S_UXTW = 7155 + + SST1H_S_UXTW_SCALED = 7156 + + SST1Q = 7157 + + SST1W_D = 7158 + + SST1W_D_IMM = 7159 + + SST1W_D_SCALED = 7160 + + SST1W_D_SXTW = 7161 + + SST1W_D_SXTW_SCALED = 7162 + + SST1W_D_UXTW = 7163 + + SST1W_D_UXTW_SCALED = 7164 + + SST1W_IMM = 7165 + + SST1W_SXTW = 7166 + + SST1W_SXTW_SCALED = 7167 + + SST1W_UXTW = 7168 + + SST1W_UXTW_SCALED = 7169 + + SSUBLBT_ZZZ_D = 7170 + + SSUBLBT_ZZZ_H = 7171 + + SSUBLBT_ZZZ_S = 7172 + + SSUBLB_ZZZ_D = 7173 + + SSUBLB_ZZZ_H = 7174 + + SSUBLB_ZZZ_S = 7175 + + SSUBLTB_ZZZ_D = 7176 + + SSUBLTB_ZZZ_H = 7177 + + SSUBLTB_ZZZ_S = 7178 + + SSUBLT_ZZZ_D = 7179 + + SSUBLT_ZZZ_H = 7180 + + SSUBLT_ZZZ_S = 7181 + + SSUBLv16i8_v8i16 = 7182 + + SSUBLv2i32_v2i64 = 7183 + + SSUBLv4i16_v4i32 = 7184 + + SSUBLv4i32_v2i64 = 7185 + + SSUBLv8i16_v4i32 = 7186 + + SSUBLv8i8_v8i16 = 7187 + + SSUBWB_ZZZ_D = 7188 + + SSUBWB_ZZZ_H = 7189 + + SSUBWB_ZZZ_S = 7190 + + SSUBWT_ZZZ_D = 7191 + + SSUBWT_ZZZ_H = 7192 + + SSUBWT_ZZZ_S = 7193 + + SSUBWv16i8_v8i16 = 7194 + + SSUBWv2i32_v2i64 = 7195 + + SSUBWv4i16_v4i32 = 7196 + + SSUBWv4i32_v2i64 = 7197 + + SSUBWv8i16_v4i32 = 7198 + + SSUBWv8i8_v8i16 = 7199 + + ST1B = 7200 + + ST1B_2Z = 7201 + + ST1B_2Z_IMM = 7202 + + ST1B_2Z_STRIDED = 7203 + + ST1B_2Z_STRIDED_IMM = 7204 + + ST1B_4Z = 7205 + + ST1B_4Z_IMM = 7206 + + ST1B_4Z_STRIDED = 7207 + + ST1B_4Z_STRIDED_IMM = 7208 + + ST1B_D = 7209 + + ST1B_D_IMM = 7210 + + ST1B_H = 7211 + + ST1B_H_IMM = 7212 + + ST1B_IMM = 7213 + + ST1B_S = 7214 + + ST1B_S_IMM = 7215 + + ST1D = 7216 + + ST1D_2Z = 7217 + + ST1D_2Z_IMM = 7218 + + ST1D_2Z_STRIDED = 7219 + + ST1D_2Z_STRIDED_IMM = 7220 + + ST1D_4Z = 7221 + + ST1D_4Z_IMM = 7222 + + ST1D_4Z_STRIDED = 7223 + + ST1D_4Z_STRIDED_IMM = 7224 + + ST1D_IMM = 7225 + + ST1D_Q = 7226 + + ST1D_Q_IMM = 7227 + + ST1Fourv16b = 7228 + + ST1Fourv16b_POST = 7229 + + ST1Fourv1d = 7230 + + ST1Fourv1d_POST = 7231 + + ST1Fourv2d = 7232 + + ST1Fourv2d_POST = 7233 + + ST1Fourv2s = 7234 + + ST1Fourv2s_POST = 7235 + + ST1Fourv4h = 7236 + + ST1Fourv4h_POST = 7237 + + ST1Fourv4s = 7238 + + ST1Fourv4s_POST = 7239 + + ST1Fourv8b = 7240 + + ST1Fourv8b_POST = 7241 + + ST1Fourv8h = 7242 + + ST1Fourv8h_POST = 7243 + + ST1H = 7244 + + ST1H_2Z = 7245 + + ST1H_2Z_IMM = 7246 + + ST1H_2Z_STRIDED = 7247 + + ST1H_2Z_STRIDED_IMM = 7248 + + ST1H_4Z = 7249 + + ST1H_4Z_IMM = 7250 + + ST1H_4Z_STRIDED = 7251 + + ST1H_4Z_STRIDED_IMM = 7252 + + ST1H_D = 7253 + + ST1H_D_IMM = 7254 + + ST1H_IMM = 7255 + + ST1H_S = 7256 + + ST1H_S_IMM = 7257 + + ST1Onev16b = 7258 + + ST1Onev16b_POST = 7259 + + ST1Onev1d = 7260 + + ST1Onev1d_POST = 7261 + + ST1Onev2d = 7262 + + ST1Onev2d_POST = 7263 + + ST1Onev2s = 7264 + + ST1Onev2s_POST = 7265 + + ST1Onev4h = 7266 + + ST1Onev4h_POST = 7267 + + ST1Onev4s = 7268 + + ST1Onev4s_POST = 7269 + + ST1Onev8b = 7270 + + ST1Onev8b_POST = 7271 + + ST1Onev8h = 7272 + + ST1Onev8h_POST = 7273 + + ST1Threev16b = 7274 + + ST1Threev16b_POST = 7275 + + ST1Threev1d = 7276 + + ST1Threev1d_POST = 7277 + + ST1Threev2d = 7278 + + ST1Threev2d_POST = 7279 + + ST1Threev2s = 7280 + + ST1Threev2s_POST = 7281 + + ST1Threev4h = 7282 + + ST1Threev4h_POST = 7283 + + ST1Threev4s = 7284 + + ST1Threev4s_POST = 7285 + + ST1Threev8b = 7286 + + ST1Threev8b_POST = 7287 + + ST1Threev8h = 7288 + + ST1Threev8h_POST = 7289 + + ST1Twov16b = 7290 + + ST1Twov16b_POST = 7291 + + ST1Twov1d = 7292 + + ST1Twov1d_POST = 7293 + + ST1Twov2d = 7294 + + ST1Twov2d_POST = 7295 + + ST1Twov2s = 7296 + + ST1Twov2s_POST = 7297 + + ST1Twov4h = 7298 + + ST1Twov4h_POST = 7299 + + ST1Twov4s = 7300 + + ST1Twov4s_POST = 7301 + + ST1Twov8b = 7302 + + ST1Twov8b_POST = 7303 + + ST1Twov8h = 7304 + + ST1Twov8h_POST = 7305 + + ST1W = 7306 + + ST1W_2Z = 7307 + + ST1W_2Z_IMM = 7308 + + ST1W_2Z_STRIDED = 7309 + + ST1W_2Z_STRIDED_IMM = 7310 + + ST1W_4Z = 7311 + + ST1W_4Z_IMM = 7312 + + ST1W_4Z_STRIDED = 7313 + + ST1W_4Z_STRIDED_IMM = 7314 + + ST1W_D = 7315 + + ST1W_D_IMM = 7316 + + ST1W_IMM = 7317 + + ST1W_Q = 7318 + + ST1W_Q_IMM = 7319 + + ST1_MXIPXX_H_B = 7320 + + ST1_MXIPXX_H_D = 7321 + + ST1_MXIPXX_H_H = 7322 + + ST1_MXIPXX_H_Q = 7323 + + ST1_MXIPXX_H_S = 7324 + + ST1_MXIPXX_V_B = 7325 + + ST1_MXIPXX_V_D = 7326 + + ST1_MXIPXX_V_H = 7327 + + ST1_MXIPXX_V_Q = 7328 + + ST1_MXIPXX_V_S = 7329 + + ST1i16 = 7330 + + ST1i16_POST = 7331 + + ST1i32 = 7332 + + ST1i32_POST = 7333 + + ST1i64 = 7334 + + ST1i64_POST = 7335 + + ST1i8 = 7336 + + ST1i8_POST = 7337 + + ST2B = 7338 + + ST2B_IMM = 7339 + + ST2D = 7340 + + ST2D_IMM = 7341 + + ST2GPostIndex = 7342 + + ST2GPreIndex = 7343 + + ST2Gi = 7344 + + ST2H = 7345 + + ST2H_IMM = 7346 + + ST2Q = 7347 + + ST2Q_IMM = 7348 + + ST2Twov16b = 7349 + + ST2Twov16b_POST = 7350 + + ST2Twov2d = 7351 + + ST2Twov2d_POST = 7352 + + ST2Twov2s = 7353 + + ST2Twov2s_POST = 7354 + + ST2Twov4h = 7355 + + ST2Twov4h_POST = 7356 + + ST2Twov4s = 7357 + + ST2Twov4s_POST = 7358 + + ST2Twov8b = 7359 + + ST2Twov8b_POST = 7360 + + ST2Twov8h = 7361 + + ST2Twov8h_POST = 7362 + + ST2W = 7363 + + ST2W_IMM = 7364 + + ST2i16 = 7365 + + ST2i16_POST = 7366 + + ST2i32 = 7367 + + ST2i32_POST = 7368 + + ST2i64 = 7369 + + ST2i64_POST = 7370 + + ST2i8 = 7371 + + ST2i8_POST = 7372 + + ST3B = 7373 + + ST3B_IMM = 7374 + + ST3D = 7375 + + ST3D_IMM = 7376 + + ST3H = 7377 + + ST3H_IMM = 7378 + + ST3Q = 7379 + + ST3Q_IMM = 7380 + + ST3Threev16b = 7381 + + ST3Threev16b_POST = 7382 + + ST3Threev2d = 7383 + + ST3Threev2d_POST = 7384 + + ST3Threev2s = 7385 + + ST3Threev2s_POST = 7386 + + ST3Threev4h = 7387 + + ST3Threev4h_POST = 7388 + + ST3Threev4s = 7389 + + ST3Threev4s_POST = 7390 + + ST3Threev8b = 7391 + + ST3Threev8b_POST = 7392 + + ST3Threev8h = 7393 + + ST3Threev8h_POST = 7394 + + ST3W = 7395 + + ST3W_IMM = 7396 + + ST3i16 = 7397 + + ST3i16_POST = 7398 + + ST3i32 = 7399 + + ST3i32_POST = 7400 + + ST3i64 = 7401 + + ST3i64_POST = 7402 + + ST3i8 = 7403 + + ST3i8_POST = 7404 + + ST4B = 7405 + + ST4B_IMM = 7406 + + ST4D = 7407 + + ST4D_IMM = 7408 + + ST4Fourv16b = 7409 + + ST4Fourv16b_POST = 7410 + + ST4Fourv2d = 7411 + + ST4Fourv2d_POST = 7412 + + ST4Fourv2s = 7413 + + ST4Fourv2s_POST = 7414 + + ST4Fourv4h = 7415 + + ST4Fourv4h_POST = 7416 + + ST4Fourv4s = 7417 + + ST4Fourv4s_POST = 7418 + + ST4Fourv8b = 7419 + + ST4Fourv8b_POST = 7420 + + ST4Fourv8h = 7421 + + ST4Fourv8h_POST = 7422 + + ST4H = 7423 + + ST4H_IMM = 7424 + + ST4Q = 7425 + + ST4Q_IMM = 7426 + + ST4W = 7427 + + ST4W_IMM = 7428 + + ST4i16 = 7429 + + ST4i16_POST = 7430 + + ST4i32 = 7431 + + ST4i32_POST = 7432 + + ST4i64 = 7433 + + ST4i64_POST = 7434 + + ST4i8 = 7435 + + ST4i8_POST = 7436 + + ST64B = 7437 + + ST64BV = 7438 + + ST64BV0 = 7439 + + STBFADD = 7440 + + STBFADDL = 7441 + + STBFMAX = 7442 + + STBFMAXL = 7443 + + STBFMAXNM = 7444 + + STBFMAXNML = 7445 + + STBFMIN = 7446 + + STBFMINL = 7447 + + STBFMINNM = 7448 + + STBFMINNML = 7449 + + STCPH = 7450 + + STFADDD = 7451 + + STFADDH = 7452 + + STFADDLD = 7453 + + STFADDLH = 7454 + + STFADDLS = 7455 + + STFADDS = 7456 + + STFMAXD = 7457 + + STFMAXH = 7458 + + STFMAXLD = 7459 + + STFMAXLH = 7460 + + STFMAXLS = 7461 + + STFMAXNMD = 7462 + + STFMAXNMH = 7463 + + STFMAXNMLD = 7464 + + STFMAXNMLH = 7465 + + STFMAXNMLS = 7466 + + STFMAXNMS = 7467 + + STFMAXS = 7468 + + STFMIND = 7469 + + STFMINH = 7470 + + STFMINLD = 7471 + + STFMINLH = 7472 + + STFMINLS = 7473 + + STFMINNMD = 7474 + + STFMINNMH = 7475 + + STFMINNMLD = 7476 + + STFMINNMLH = 7477 + + STFMINNMLS = 7478 + + STFMINNMS = 7479 + + STFMINS = 7480 + + STGM = 7481 + + STGPi = 7482 + + STGPostIndex = 7483 + + STGPpost = 7484 + + STGPpre = 7485 + + STGPreIndex = 7486 + + STGi = 7487 + + STILPW = 7488 + + STILPWpre = 7489 + + STILPX = 7490 + + STILPXpre = 7491 + + STL1 = 7492 + + STLLRB = 7493 + + STLLRH = 7494 + + STLLRW = 7495 + + STLLRX = 7496 + + STLPi = 7497 + + STLRB = 7498 + + STLRH = 7499 + + STLRW = 7500 + + STLRWpre = 7501 + + STLRX = 7502 + + STLRXpre = 7503 + + STLTXRW = 7504 + + STLTXRX = 7505 + + STLURBi = 7506 + + STLURHi = 7507 + + STLURWi = 7508 + + STLURXi = 7509 + + STLURbi = 7510 + + STLURdi = 7511 + + STLURhi = 7512 + + STLURqi = 7513 + + STLURsi = 7514 + + STLXPW = 7515 + + STLXPX = 7516 + + STLXRB = 7517 + + STLXRH = 7518 + + STLXRW = 7519 + + STLXRX = 7520 + + STMOPA_M2ZZZI_BtoS = 7521 + + STMOPA_M2ZZZI_HtoS = 7522 + + STNPDi = 7523 + + STNPQi = 7524 + + STNPSi = 7525 + + STNPWi = 7526 + + STNPXi = 7527 + + STNT1B_2Z = 7528 + + STNT1B_2Z_IMM = 7529 + + STNT1B_2Z_STRIDED = 7530 + + STNT1B_2Z_STRIDED_IMM = 7531 + + STNT1B_4Z = 7532 + + STNT1B_4Z_IMM = 7533 + + STNT1B_4Z_STRIDED = 7534 + + STNT1B_4Z_STRIDED_IMM = 7535 + + STNT1B_ZRI = 7536 + + STNT1B_ZRR = 7537 + + STNT1B_ZZR_D = 7538 + + STNT1B_ZZR_S = 7539 + + STNT1D_2Z = 7540 + + STNT1D_2Z_IMM = 7541 + + STNT1D_2Z_STRIDED = 7542 + + STNT1D_2Z_STRIDED_IMM = 7543 + + STNT1D_4Z = 7544 + + STNT1D_4Z_IMM = 7545 + + STNT1D_4Z_STRIDED = 7546 + + STNT1D_4Z_STRIDED_IMM = 7547 + + STNT1D_ZRI = 7548 + + STNT1D_ZRR = 7549 + + STNT1D_ZZR_D = 7550 + + STNT1H_2Z = 7551 + + STNT1H_2Z_IMM = 7552 + + STNT1H_2Z_STRIDED = 7553 + + STNT1H_2Z_STRIDED_IMM = 7554 + + STNT1H_4Z = 7555 + + STNT1H_4Z_IMM = 7556 + + STNT1H_4Z_STRIDED = 7557 + + STNT1H_4Z_STRIDED_IMM = 7558 + + STNT1H_ZRI = 7559 + + STNT1H_ZRR = 7560 + + STNT1H_ZZR_D = 7561 + + STNT1H_ZZR_S = 7562 + + STNT1W_2Z = 7563 + + STNT1W_2Z_IMM = 7564 + + STNT1W_2Z_STRIDED = 7565 + + STNT1W_2Z_STRIDED_IMM = 7566 + + STNT1W_4Z = 7567 + + STNT1W_4Z_IMM = 7568 + + STNT1W_4Z_STRIDED = 7569 + + STNT1W_4Z_STRIDED_IMM = 7570 + + STNT1W_ZRI = 7571 + + STNT1W_ZRR = 7572 + + STNT1W_ZZR_D = 7573 + + STNT1W_ZZR_S = 7574 + + STPDi = 7575 + + STPDpost = 7576 + + STPDpre = 7577 + + STPQi = 7578 + + STPQpost = 7579 + + STPQpre = 7580 + + STPSi = 7581 + + STPSpost = 7582 + + STPSpre = 7583 + + STPWi = 7584 + + STPWpost = 7585 + + STPWpre = 7586 + + STPXi = 7587 + + STPXpost = 7588 + + STPXpre = 7589 + + STRBBpost = 7590 + + STRBBpre = 7591 + + STRBBroW = 7592 + + STRBBroX = 7593 + + STRBBui = 7594 + + STRBpost = 7595 + + STRBpre = 7596 + + STRBroW = 7597 + + STRBroX = 7598 + + STRBui = 7599 + + STRDpost = 7600 + + STRDpre = 7601 + + STRDroW = 7602 + + STRDroX = 7603 + + STRDui = 7604 + + STRHHpost = 7605 + + STRHHpre = 7606 + + STRHHroW = 7607 + + STRHHroX = 7608 + + STRHHui = 7609 + + STRHpost = 7610 + + STRHpre = 7611 + + STRHroW = 7612 + + STRHroX = 7613 + + STRHui = 7614 + + STRQpost = 7615 + + STRQpre = 7616 + + STRQroW = 7617 + + STRQroX = 7618 + + STRQui = 7619 + + STRSpost = 7620 + + STRSpre = 7621 + + STRSroW = 7622 + + STRSroX = 7623 + + STRSui = 7624 + + STRWpost = 7625 + + STRWpre = 7626 + + STRWroW = 7627 + + STRWroX = 7628 + + STRWui = 7629 + + STRXpost = 7630 + + STRXpre = 7631 + + STRXroW = 7632 + + STRXroX = 7633 + + STRXui = 7634 + + STR_PXI = 7635 + + STR_TX = 7636 + + STR_ZA = 7637 + + STR_ZXI = 7638 + + STSHH = 7639 + + STTNPQi = 7640 + + STTNPXi = 7641 + + STTPQi = 7642 + + STTPQpost = 7643 + + STTPQpre = 7644 + + STTPi = 7645 + + STTPpost = 7646 + + STTPpre = 7647 + + STTRBi = 7648 + + STTRHi = 7649 + + STTRWi = 7650 + + STTRXi = 7651 + + STTXRWr = 7652 + + STTXRXr = 7653 + + STURBBi = 7654 + + STURBi = 7655 + + STURDi = 7656 + + STURHHi = 7657 + + STURHi = 7658 + + STURQi = 7659 + + STURSi = 7660 + + STURWi = 7661 + + STURXi = 7662 + + STXPW = 7663 + + STXPX = 7664 + + STXRB = 7665 + + STXRH = 7666 + + STXRW = 7667 + + STXRX = 7668 + + STZ2GPostIndex = 7669 + + STZ2GPreIndex = 7670 + + STZ2Gi = 7671 + + STZGM = 7672 + + STZGPostIndex = 7673 + + STZGPreIndex = 7674 + + STZGi = 7675 + + SUBG = 7676 + + SUBHNB_ZZZ_B = 7677 + + SUBHNB_ZZZ_H = 7678 + + SUBHNB_ZZZ_S = 7679 + + SUBHNT_ZZZ_B = 7680 + + SUBHNT_ZZZ_H = 7681 + + SUBHNT_ZZZ_S = 7682 + + SUBHNv2i64_v2i32 = 7683 + + SUBHNv2i64_v4i32 = 7684 + + SUBHNv4i32_v4i16 = 7685 + + SUBHNv4i32_v8i16 = 7686 + + SUBHNv8i16_v16i8 = 7687 + + SUBHNv8i16_v8i8 = 7688 + + SUBP = 7689 + + SUBPS = 7690 + + SUBPT_shift = 7691 + + SUBP_ZPmZZ_B = 7692 + + SUBP_ZPmZZ_D = 7693 + + SUBP_ZPmZZ_H = 7694 + + SUBP_ZPmZZ_S = 7695 + + SUBR_ZI_B = 7696 + + SUBR_ZI_D = 7697 + + SUBR_ZI_H = 7698 + + SUBR_ZI_S = 7699 + + SUBR_ZPmZ_B = 7700 + + SUBR_ZPmZ_D = 7701 + + SUBR_ZPmZ_H = 7702 + + SUBR_ZPmZ_S = 7703 + + SUBSWri = 7704 + + SUBSWrs = 7705 + + SUBSWrx = 7706 + + SUBSXri = 7707 + + SUBSXrs = 7708 + + SUBSXrx = 7709 + + SUBSXrx64 = 7710 + + SUBWri = 7711 + + SUBWrs = 7712 + + SUBWrx = 7713 + + SUBXri = 7714 + + SUBXrs = 7715 + + SUBXrx = 7716 + + SUBXrx64 = 7717 + + SUB_VG2_M2Z2Z_D = 7718 + + SUB_VG2_M2Z2Z_S = 7719 + + SUB_VG2_M2ZZ_D = 7720 + + SUB_VG2_M2ZZ_S = 7721 + + SUB_VG2_M2Z_D = 7722 + + SUB_VG2_M2Z_S = 7723 + + SUB_VG4_M4Z4Z_D = 7724 + + SUB_VG4_M4Z4Z_S = 7725 + + SUB_VG4_M4ZZ_D = 7726 + + SUB_VG4_M4ZZ_S = 7727 + + SUB_VG4_M4Z_D = 7728 + + SUB_VG4_M4Z_S = 7729 + + SUB_ZI_B = 7730 + + SUB_ZI_D = 7731 + + SUB_ZI_H = 7732 + + SUB_ZI_S = 7733 + + SUB_ZPmZ_B = 7734 + + SUB_ZPmZ_CPA = 7735 + + SUB_ZPmZ_D = 7736 + + SUB_ZPmZ_H = 7737 + + SUB_ZPmZ_S = 7738 + + SUB_ZZZ_B = 7739 + + SUB_ZZZ_CPA = 7740 + + SUB_ZZZ_D = 7741 + + SUB_ZZZ_H = 7742 + + SUB_ZZZ_S = 7743 + + SUBv16i8 = 7744 + + SUBv1i64 = 7745 + + SUBv2i32 = 7746 + + SUBv2i64 = 7747 + + SUBv4i16 = 7748 + + SUBv4i32 = 7749 + + SUBv8i16 = 7750 + + SUBv8i8 = 7751 + + SUDOT_VG2_M2ZZI_BToS = 7752 + + SUDOT_VG2_M2ZZ_BToS = 7753 + + SUDOT_VG4_M4ZZI_BToS = 7754 + + SUDOT_VG4_M4ZZ_BToS = 7755 + + SUDOT_ZZZI = 7756 + + SUDOTlanev16i8 = 7757 + + SUDOTlanev8i8 = 7758 + + SUMLALL_MZZI_BtoS = 7759 + + SUMLALL_VG2_M2ZZI_BtoS = 7760 + + SUMLALL_VG2_M2ZZ_BtoS = 7761 + + SUMLALL_VG4_M4ZZI_BtoS = 7762 + + SUMLALL_VG4_M4ZZ_BtoS = 7763 + + SUMOP4A_M2Z2Z_BToS = 7764 + + SUMOP4A_M2Z2Z_HtoD = 7765 + + SUMOP4A_M2ZZ_BToS = 7766 + + SUMOP4A_M2ZZ_HtoD = 7767 + + SUMOP4A_MZ2Z_BToS = 7768 + + SUMOP4A_MZ2Z_HtoD = 7769 + + SUMOP4A_MZZ_BToS = 7770 + + SUMOP4A_MZZ_HtoD = 7771 + + SUMOP4S_M2Z2Z_BToS = 7772 + + SUMOP4S_M2Z2Z_HtoD = 7773 + + SUMOP4S_M2ZZ_BToS = 7774 + + SUMOP4S_M2ZZ_HtoD = 7775 + + SUMOP4S_MZ2Z_BToS = 7776 + + SUMOP4S_MZ2Z_HtoD = 7777 + + SUMOP4S_MZZ_BToS = 7778 + + SUMOP4S_MZZ_HtoD = 7779 + + SUMOPA_MPPZZ_D = 7780 + + SUMOPA_MPPZZ_S = 7781 + + SUMOPS_MPPZZ_D = 7782 + + SUMOPS_MPPZZ_S = 7783 + + SUNPKHI_ZZ_D = 7784 + + SUNPKHI_ZZ_H = 7785 + + SUNPKHI_ZZ_S = 7786 + + SUNPKLO_ZZ_D = 7787 + + SUNPKLO_ZZ_H = 7788 + + SUNPKLO_ZZ_S = 7789 + + SUNPK_VG2_2ZZ_D = 7790 + + SUNPK_VG2_2ZZ_H = 7791 + + SUNPK_VG2_2ZZ_S = 7792 + + SUNPK_VG4_4Z2Z_D = 7793 + + SUNPK_VG4_4Z2Z_H = 7794 + + SUNPK_VG4_4Z2Z_S = 7795 + + SUQADD_ZPmZ_B = 7796 + + SUQADD_ZPmZ_D = 7797 + + SUQADD_ZPmZ_H = 7798 + + SUQADD_ZPmZ_S = 7799 + + SUQADDv16i8 = 7800 + + SUQADDv1i16 = 7801 + + SUQADDv1i32 = 7802 + + SUQADDv1i64 = 7803 + + SUQADDv1i8 = 7804 + + SUQADDv2i32 = 7805 + + SUQADDv2i64 = 7806 + + SUQADDv4i16 = 7807 + + SUQADDv4i32 = 7808 + + SUQADDv8i16 = 7809 + + SUQADDv8i8 = 7810 + + SUTMOPA_M2ZZZI_BtoS = 7811 + + SUVDOT_VG4_M4ZZI_BToS = 7812 + + SVC = 7813 + + SVDOT_VG2_M2ZZI_HtoS = 7814 + + SVDOT_VG4_M4ZZI_BtoS = 7815 + + SVDOT_VG4_M4ZZI_HtoD = 7816 + + SWPAB = 7817 + + SWPAH = 7818 + + SWPALB = 7819 + + SWPALH = 7820 + + SWPALW = 7821 + + SWPALX = 7822 + + SWPAW = 7823 + + SWPAX = 7824 + + SWPB = 7825 + + SWPH = 7826 + + SWPLB = 7827 + + SWPLH = 7828 + + SWPLW = 7829 + + SWPLX = 7830 + + SWPP = 7831 + + SWPPA = 7832 + + SWPPAL = 7833 + + SWPPL = 7834 + + SWPTALW = 7835 + + SWPTALX = 7836 + + SWPTAW = 7837 + + SWPTAX = 7838 + + SWPTLW = 7839 + + SWPTLX = 7840 + + SWPTW = 7841 + + SWPTX = 7842 + + SWPW = 7843 + + SWPX = 7844 + + SXTB_ZPmZ_D = 7845 + + SXTB_ZPmZ_H = 7846 + + SXTB_ZPmZ_S = 7847 + + SXTB_ZPzZ_D = 7848 + + SXTB_ZPzZ_H = 7849 + + SXTB_ZPzZ_S = 7850 + + SXTH_ZPmZ_D = 7851 + + SXTH_ZPmZ_S = 7852 + + SXTH_ZPzZ_D = 7853 + + SXTH_ZPzZ_S = 7854 + + SXTW_ZPmZ_D = 7855 + + SXTW_ZPzZ_D = 7856 + + SYSLxt = 7857 + + SYSPxt = 7858 + + SYSPxt_XZR = 7859 + + SYSxt = 7860 + + TBLQ_ZZZ_B = 7861 + + TBLQ_ZZZ_D = 7862 + + TBLQ_ZZZ_H = 7863 + + TBLQ_ZZZ_S = 7864 + + TBL_ZZZZ_B = 7865 + + TBL_ZZZZ_D = 7866 + + TBL_ZZZZ_H = 7867 + + TBL_ZZZZ_S = 7868 + + TBL_ZZZ_B = 7869 + + TBL_ZZZ_D = 7870 + + TBL_ZZZ_H = 7871 + + TBL_ZZZ_S = 7872 + + TBLv16i8Four = 7873 + + TBLv16i8One = 7874 + + TBLv16i8Three = 7875 + + TBLv16i8Two = 7876 + + TBLv8i8Four = 7877 + + TBLv8i8One = 7878 + + TBLv8i8Three = 7879 + + TBLv8i8Two = 7880 + + TBNZW = 7881 + + TBNZX = 7882 + + TBXQ_ZZZ_B = 7883 + + TBXQ_ZZZ_D = 7884 + + TBXQ_ZZZ_H = 7885 + + TBXQ_ZZZ_S = 7886 + + TBX_ZZZ_B = 7887 + + TBX_ZZZ_D = 7888 + + TBX_ZZZ_H = 7889 + + TBX_ZZZ_S = 7890 + + TBXv16i8Four = 7891 + + TBXv16i8One = 7892 + + TBXv16i8Three = 7893 + + TBXv16i8Two = 7894 + + TBXv8i8Four = 7895 + + TBXv8i8One = 7896 + + TBXv8i8Three = 7897 + + TBXv8i8Two = 7898 + + TBZW = 7899 + + TBZX = 7900 + + TCHANGEBri = 7901 + + TCHANGEBrr = 7902 + + TCHANGEFri = 7903 + + TCHANGEFrr = 7904 + + TENTER = 7905 + + TEXIT = 7906 + + TRCIT = 7907 + + TRN1_PPP_B = 7908 + + TRN1_PPP_D = 7909 + + TRN1_PPP_H = 7910 + + TRN1_PPP_S = 7911 + + TRN1_ZZZ_B = 7912 + + TRN1_ZZZ_D = 7913 + + TRN1_ZZZ_H = 7914 + + TRN1_ZZZ_Q = 7915 + + TRN1_ZZZ_S = 7916 + + TRN1v16i8 = 7917 + + TRN1v2i32 = 7918 + + TRN1v2i64 = 7919 + + TRN1v4i16 = 7920 + + TRN1v4i32 = 7921 + + TRN1v8i16 = 7922 + + TRN1v8i8 = 7923 + + TRN2_PPP_B = 7924 + + TRN2_PPP_D = 7925 + + TRN2_PPP_H = 7926 + + TRN2_PPP_S = 7927 + + TRN2_ZZZ_B = 7928 + + TRN2_ZZZ_D = 7929 + + TRN2_ZZZ_H = 7930 + + TRN2_ZZZ_Q = 7931 + + TRN2_ZZZ_S = 7932 + + TRN2v16i8 = 7933 + + TRN2v2i32 = 7934 + + TRN2v2i64 = 7935 + + TRN2v4i16 = 7936 + + TRN2v4i32 = 7937 + + TRN2v8i16 = 7938 + + TRN2v8i8 = 7939 + + TSB = 7940 + + UABALB_ZZZ_D = 7941 + + UABALB_ZZZ_H = 7942 + + UABALB_ZZZ_S = 7943 + + UABALT_ZZZ_D = 7944 + + UABALT_ZZZ_H = 7945 + + UABALT_ZZZ_S = 7946 + + UABAL_ZZZ_BtoH = 7947 + + UABAL_ZZZ_HtoS = 7948 + + UABAL_ZZZ_StoD = 7949 + + UABALv16i8_v8i16 = 7950 + + UABALv2i32_v2i64 = 7951 + + UABALv4i16_v4i32 = 7952 + + UABALv4i32_v2i64 = 7953 + + UABALv8i16_v4i32 = 7954 + + UABALv8i8_v8i16 = 7955 + + UABA_ZZZ_B = 7956 + + UABA_ZZZ_D = 7957 + + UABA_ZZZ_H = 7958 + + UABA_ZZZ_S = 7959 + + UABAv16i8 = 7960 + + UABAv2i32 = 7961 + + UABAv4i16 = 7962 + + UABAv4i32 = 7963 + + UABAv8i16 = 7964 + + UABAv8i8 = 7965 + + UABDLB_ZZZ_D = 7966 + + UABDLB_ZZZ_H = 7967 + + UABDLB_ZZZ_S = 7968 + + UABDLT_ZZZ_D = 7969 + + UABDLT_ZZZ_H = 7970 + + UABDLT_ZZZ_S = 7971 + + UABDLv16i8_v8i16 = 7972 + + UABDLv2i32_v2i64 = 7973 + + UABDLv4i16_v4i32 = 7974 + + UABDLv4i32_v2i64 = 7975 + + UABDLv8i16_v4i32 = 7976 + + UABDLv8i8_v8i16 = 7977 + + UABD_ZPmZ_B = 7978 + + UABD_ZPmZ_D = 7979 + + UABD_ZPmZ_H = 7980 + + UABD_ZPmZ_S = 7981 + + UABDv16i8 = 7982 + + UABDv2i32 = 7983 + + UABDv4i16 = 7984 + + UABDv4i32 = 7985 + + UABDv8i16 = 7986 + + UABDv8i8 = 7987 + + UADALP_ZPmZ_D = 7988 + + UADALP_ZPmZ_H = 7989 + + UADALP_ZPmZ_S = 7990 + + UADALPv16i8_v8i16 = 7991 + + UADALPv2i32_v1i64 = 7992 + + UADALPv4i16_v2i32 = 7993 + + UADALPv4i32_v2i64 = 7994 + + UADALPv8i16_v4i32 = 7995 + + UADALPv8i8_v4i16 = 7996 + + UADDLB_ZZZ_D = 7997 + + UADDLB_ZZZ_H = 7998 + + UADDLB_ZZZ_S = 7999 + + UADDLPv16i8_v8i16 = 8000 + + UADDLPv2i32_v1i64 = 8001 + + UADDLPv4i16_v2i32 = 8002 + + UADDLPv4i32_v2i64 = 8003 + + UADDLPv8i16_v4i32 = 8004 + + UADDLPv8i8_v4i16 = 8005 + + UADDLT_ZZZ_D = 8006 + + UADDLT_ZZZ_H = 8007 + + UADDLT_ZZZ_S = 8008 + + UADDLVv16i8v = 8009 + + UADDLVv4i16v = 8010 + + UADDLVv4i32v = 8011 + + UADDLVv8i16v = 8012 + + UADDLVv8i8v = 8013 + + UADDLv16i8_v8i16 = 8014 + + UADDLv2i32_v2i64 = 8015 + + UADDLv4i16_v4i32 = 8016 + + UADDLv4i32_v2i64 = 8017 + + UADDLv8i16_v4i32 = 8018 + + UADDLv8i8_v8i16 = 8019 + + UADDV_VPZ_B = 8020 + + UADDV_VPZ_D = 8021 + + UADDV_VPZ_H = 8022 + + UADDV_VPZ_S = 8023 + + UADDWB_ZZZ_D = 8024 + + UADDWB_ZZZ_H = 8025 + + UADDWB_ZZZ_S = 8026 + + UADDWT_ZZZ_D = 8027 + + UADDWT_ZZZ_H = 8028 + + UADDWT_ZZZ_S = 8029 + + UADDWv16i8_v8i16 = 8030 + + UADDWv2i32_v2i64 = 8031 + + UADDWv4i16_v4i32 = 8032 + + UADDWv4i32_v2i64 = 8033 + + UADDWv8i16_v4i32 = 8034 + + UADDWv8i8_v8i16 = 8035 + + UBFMWri = 8036 + + UBFMXri = 8037 + + UCLAMP_VG2_2Z2Z_B = 8038 + + UCLAMP_VG2_2Z2Z_D = 8039 + + UCLAMP_VG2_2Z2Z_H = 8040 + + UCLAMP_VG2_2Z2Z_S = 8041 + + UCLAMP_VG4_4Z4Z_B = 8042 + + UCLAMP_VG4_4Z4Z_D = 8043 + + UCLAMP_VG4_4Z4Z_H = 8044 + + UCLAMP_VG4_4Z4Z_S = 8045 + + UCLAMP_ZZZ_B = 8046 + + UCLAMP_ZZZ_D = 8047 + + UCLAMP_ZZZ_H = 8048 + + UCLAMP_ZZZ_S = 8049 + + UCVTFDSr = 8050 + + UCVTFHDr = 8051 + + UCVTFHSr = 8052 + + UCVTFLT_ZZ_BtoH = 8053 + + UCVTFLT_ZZ_HtoS = 8054 + + UCVTFLT_ZZ_StoD = 8055 + + UCVTFSDr = 8056 + + UCVTFSWDri = 8057 + + UCVTFSWHri = 8058 + + UCVTFSWSri = 8059 + + UCVTFSXDri = 8060 + + UCVTFSXHri = 8061 + + UCVTFSXSri = 8062 + + UCVTFUWDri = 8063 + + UCVTFUWHri = 8064 + + UCVTFUWSri = 8065 + + UCVTFUXDri = 8066 + + UCVTFUXHri = 8067 + + UCVTFUXSri = 8068 + + UCVTF_2Z2Z_StoS = 8069 + + UCVTF_4Z4Z_StoS = 8070 + + UCVTF_ZPmZ_DtoD = 8071 + + UCVTF_ZPmZ_DtoH = 8072 + + UCVTF_ZPmZ_DtoS = 8073 + + UCVTF_ZPmZ_HtoH = 8074 + + UCVTF_ZPmZ_StoD = 8075 + + UCVTF_ZPmZ_StoH = 8076 + + UCVTF_ZPmZ_StoS = 8077 + + UCVTF_ZPzZ_DtoD = 8078 + + UCVTF_ZPzZ_DtoH = 8079 + + UCVTF_ZPzZ_DtoS = 8080 + + UCVTF_ZPzZ_HtoH = 8081 + + UCVTF_ZPzZ_StoD = 8082 + + UCVTF_ZPzZ_StoH = 8083 + + UCVTF_ZPzZ_StoS = 8084 + + UCVTF_ZZ_BtoH = 8085 + + UCVTF_ZZ_HtoS = 8086 + + UCVTF_ZZ_StoD = 8087 + + UCVTFd = 8088 + + UCVTFh = 8089 + + UCVTFs = 8090 + + UCVTFv1i16 = 8091 + + UCVTFv1i32 = 8092 + + UCVTFv1i64 = 8093 + + UCVTFv2f32 = 8094 + + UCVTFv2f64 = 8095 + + UCVTFv2i32_shift = 8096 + + UCVTFv2i64_shift = 8097 + + UCVTFv4f16 = 8098 + + UCVTFv4f32 = 8099 + + UCVTFv4i16_shift = 8100 + + UCVTFv4i32_shift = 8101 + + UCVTFv8f16 = 8102 + + UCVTFv8i16_shift = 8103 + + UDF = 8104 + + UDIVR_ZPmZ_D = 8105 + + UDIVR_ZPmZ_S = 8106 + + UDIVWr = 8107 + + UDIVXr = 8108 + + UDIV_ZPmZ_D = 8109 + + UDIV_ZPmZ_S = 8110 + + UDOT_VG2_M2Z2Z_BtoS = 8111 + + UDOT_VG2_M2Z2Z_HtoD = 8112 + + UDOT_VG2_M2Z2Z_HtoS = 8113 + + UDOT_VG2_M2ZZI_BToS = 8114 + + UDOT_VG2_M2ZZI_HToS = 8115 + + UDOT_VG2_M2ZZI_HtoD = 8116 + + UDOT_VG2_M2ZZ_BtoS = 8117 + + UDOT_VG2_M2ZZ_HtoD = 8118 + + UDOT_VG2_M2ZZ_HtoS = 8119 + + UDOT_VG4_M4Z4Z_BtoS = 8120 + + UDOT_VG4_M4Z4Z_HtoD = 8121 + + UDOT_VG4_M4Z4Z_HtoS = 8122 + + UDOT_VG4_M4ZZI_BtoS = 8123 + + UDOT_VG4_M4ZZI_HToS = 8124 + + UDOT_VG4_M4ZZI_HtoD = 8125 + + UDOT_VG4_M4ZZ_BtoS = 8126 + + UDOT_VG4_M4ZZ_HtoD = 8127 + + UDOT_VG4_M4ZZ_HtoS = 8128 + + UDOT_ZZZI_BtoH = 8129 + + UDOT_ZZZI_BtoS = 8130 + + UDOT_ZZZI_HtoD = 8131 + + UDOT_ZZZI_HtoS = 8132 + + UDOT_ZZZ_BtoH = 8133 + + UDOT_ZZZ_BtoS = 8134 + + UDOT_ZZZ_HtoD = 8135 + + UDOT_ZZZ_HtoS = 8136 + + UDOTlanev16i8 = 8137 + + UDOTlanev8i8 = 8138 + + UDOTv16i8 = 8139 + + UDOTv8i8 = 8140 + + UHADD_ZPmZ_B = 8141 + + UHADD_ZPmZ_D = 8142 + + UHADD_ZPmZ_H = 8143 + + UHADD_ZPmZ_S = 8144 + + UHADDv16i8 = 8145 + + UHADDv2i32 = 8146 + + UHADDv4i16 = 8147 + + UHADDv4i32 = 8148 + + UHADDv8i16 = 8149 + + UHADDv8i8 = 8150 + + UHSUBR_ZPmZ_B = 8151 + + UHSUBR_ZPmZ_D = 8152 + + UHSUBR_ZPmZ_H = 8153 + + UHSUBR_ZPmZ_S = 8154 + + UHSUB_ZPmZ_B = 8155 + + UHSUB_ZPmZ_D = 8156 + + UHSUB_ZPmZ_H = 8157 + + UHSUB_ZPmZ_S = 8158 + + UHSUBv16i8 = 8159 + + UHSUBv2i32 = 8160 + + UHSUBv4i16 = 8161 + + UHSUBv4i32 = 8162 + + UHSUBv8i16 = 8163 + + UHSUBv8i8 = 8164 + + UMADDLrrr = 8165 + + UMAXP_ZPmZ_B = 8166 + + UMAXP_ZPmZ_D = 8167 + + UMAXP_ZPmZ_H = 8168 + + UMAXP_ZPmZ_S = 8169 + + UMAXPv16i8 = 8170 + + UMAXPv2i32 = 8171 + + UMAXPv4i16 = 8172 + + UMAXPv4i32 = 8173 + + UMAXPv8i16 = 8174 + + UMAXPv8i8 = 8175 + + UMAXQV_VPZ_B = 8176 + + UMAXQV_VPZ_D = 8177 + + UMAXQV_VPZ_H = 8178 + + UMAXQV_VPZ_S = 8179 + + UMAXV_VPZ_B = 8180 + + UMAXV_VPZ_D = 8181 + + UMAXV_VPZ_H = 8182 + + UMAXV_VPZ_S = 8183 + + UMAXVv16i8v = 8184 + + UMAXVv4i16v = 8185 + + UMAXVv4i32v = 8186 + + UMAXVv8i16v = 8187 + + UMAXVv8i8v = 8188 + + UMAXWri = 8189 + + UMAXWrr = 8190 + + UMAXXri = 8191 + + UMAXXrr = 8192 + + UMAX_VG2_2Z2Z_B = 8193 + + UMAX_VG2_2Z2Z_D = 8194 + + UMAX_VG2_2Z2Z_H = 8195 + + UMAX_VG2_2Z2Z_S = 8196 + + UMAX_VG2_2ZZ_B = 8197 + + UMAX_VG2_2ZZ_D = 8198 + + UMAX_VG2_2ZZ_H = 8199 + + UMAX_VG2_2ZZ_S = 8200 + + UMAX_VG4_4Z4Z_B = 8201 + + UMAX_VG4_4Z4Z_D = 8202 + + UMAX_VG4_4Z4Z_H = 8203 + + UMAX_VG4_4Z4Z_S = 8204 + + UMAX_VG4_4ZZ_B = 8205 + + UMAX_VG4_4ZZ_D = 8206 + + UMAX_VG4_4ZZ_H = 8207 + + UMAX_VG4_4ZZ_S = 8208 + + UMAX_ZI_B = 8209 + + UMAX_ZI_D = 8210 + + UMAX_ZI_H = 8211 + + UMAX_ZI_S = 8212 + + UMAX_ZPmZ_B = 8213 + + UMAX_ZPmZ_D = 8214 + + UMAX_ZPmZ_H = 8215 + + UMAX_ZPmZ_S = 8216 + + UMAXv16i8 = 8217 + + UMAXv2i32 = 8218 + + UMAXv4i16 = 8219 + + UMAXv4i32 = 8220 + + UMAXv8i16 = 8221 + + UMAXv8i8 = 8222 + + UMINP_ZPmZ_B = 8223 + + UMINP_ZPmZ_D = 8224 + + UMINP_ZPmZ_H = 8225 + + UMINP_ZPmZ_S = 8226 + + UMINPv16i8 = 8227 + + UMINPv2i32 = 8228 + + UMINPv4i16 = 8229 + + UMINPv4i32 = 8230 + + UMINPv8i16 = 8231 + + UMINPv8i8 = 8232 + + UMINQV_VPZ_B = 8233 + + UMINQV_VPZ_D = 8234 + + UMINQV_VPZ_H = 8235 + + UMINQV_VPZ_S = 8236 + + UMINV_VPZ_B = 8237 + + UMINV_VPZ_D = 8238 + + UMINV_VPZ_H = 8239 + + UMINV_VPZ_S = 8240 + + UMINVv16i8v = 8241 + + UMINVv4i16v = 8242 + + UMINVv4i32v = 8243 + + UMINVv8i16v = 8244 + + UMINVv8i8v = 8245 + + UMINWri = 8246 + + UMINWrr = 8247 + + UMINXri = 8248 + + UMINXrr = 8249 + + UMIN_VG2_2Z2Z_B = 8250 + + UMIN_VG2_2Z2Z_D = 8251 + + UMIN_VG2_2Z2Z_H = 8252 + + UMIN_VG2_2Z2Z_S = 8253 + + UMIN_VG2_2ZZ_B = 8254 + + UMIN_VG2_2ZZ_D = 8255 + + UMIN_VG2_2ZZ_H = 8256 + + UMIN_VG2_2ZZ_S = 8257 + + UMIN_VG4_4Z4Z_B = 8258 + + UMIN_VG4_4Z4Z_D = 8259 + + UMIN_VG4_4Z4Z_H = 8260 + + UMIN_VG4_4Z4Z_S = 8261 + + UMIN_VG4_4ZZ_B = 8262 + + UMIN_VG4_4ZZ_D = 8263 + + UMIN_VG4_4ZZ_H = 8264 + + UMIN_VG4_4ZZ_S = 8265 + + UMIN_ZI_B = 8266 + + UMIN_ZI_D = 8267 + + UMIN_ZI_H = 8268 + + UMIN_ZI_S = 8269 + + UMIN_ZPmZ_B = 8270 + + UMIN_ZPmZ_D = 8271 + + UMIN_ZPmZ_H = 8272 + + UMIN_ZPmZ_S = 8273 + + UMINv16i8 = 8274 + + UMINv2i32 = 8275 + + UMINv4i16 = 8276 + + UMINv4i32 = 8277 + + UMINv8i16 = 8278 + + UMINv8i8 = 8279 + + UMLALB_ZZZI_D = 8280 + + UMLALB_ZZZI_S = 8281 + + UMLALB_ZZZ_D = 8282 + + UMLALB_ZZZ_H = 8283 + + UMLALB_ZZZ_S = 8284 + + UMLALL_MZZI_BtoS = 8285 + + UMLALL_MZZI_HtoD = 8286 + + UMLALL_MZZ_BtoS = 8287 + + UMLALL_MZZ_HtoD = 8288 + + UMLALL_VG2_M2Z2Z_BtoS = 8289 + + UMLALL_VG2_M2Z2Z_HtoD = 8290 + + UMLALL_VG2_M2ZZI_BtoS = 8291 + + UMLALL_VG2_M2ZZI_HtoD = 8292 + + UMLALL_VG2_M2ZZ_BtoS = 8293 + + UMLALL_VG2_M2ZZ_HtoD = 8294 + + UMLALL_VG4_M4Z4Z_BtoS = 8295 + + UMLALL_VG4_M4Z4Z_HtoD = 8296 + + UMLALL_VG4_M4ZZI_BtoS = 8297 + + UMLALL_VG4_M4ZZI_HtoD = 8298 + + UMLALL_VG4_M4ZZ_BtoS = 8299 + + UMLALL_VG4_M4ZZ_HtoD = 8300 + + UMLALT_ZZZI_D = 8301 + + UMLALT_ZZZI_S = 8302 + + UMLALT_ZZZ_D = 8303 + + UMLALT_ZZZ_H = 8304 + + UMLALT_ZZZ_S = 8305 + + UMLAL_MZZI_HtoS = 8306 + + UMLAL_MZZ_HtoS = 8307 + + UMLAL_VG2_M2Z2Z_HtoS = 8308 + + UMLAL_VG2_M2ZZI_S = 8309 + + UMLAL_VG2_M2ZZ_HtoS = 8310 + + UMLAL_VG4_M4Z4Z_HtoS = 8311 + + UMLAL_VG4_M4ZZI_HtoS = 8312 + + UMLAL_VG4_M4ZZ_HtoS = 8313 + + UMLALv16i8_v8i16 = 8314 + + UMLALv2i32_indexed = 8315 + + UMLALv2i32_v2i64 = 8316 + + UMLALv4i16_indexed = 8317 + + UMLALv4i16_v4i32 = 8318 + + UMLALv4i32_indexed = 8319 + + UMLALv4i32_v2i64 = 8320 + + UMLALv8i16_indexed = 8321 + + UMLALv8i16_v4i32 = 8322 + + UMLALv8i8_v8i16 = 8323 + + UMLSLB_ZZZI_D = 8324 + + UMLSLB_ZZZI_S = 8325 + + UMLSLB_ZZZ_D = 8326 + + UMLSLB_ZZZ_H = 8327 + + UMLSLB_ZZZ_S = 8328 + + UMLSLL_MZZI_BtoS = 8329 + + UMLSLL_MZZI_HtoD = 8330 + + UMLSLL_MZZ_BtoS = 8331 + + UMLSLL_MZZ_HtoD = 8332 + + UMLSLL_VG2_M2Z2Z_BtoS = 8333 + + UMLSLL_VG2_M2Z2Z_HtoD = 8334 + + UMLSLL_VG2_M2ZZI_BtoS = 8335 + + UMLSLL_VG2_M2ZZI_HtoD = 8336 + + UMLSLL_VG2_M2ZZ_BtoS = 8337 + + UMLSLL_VG2_M2ZZ_HtoD = 8338 + + UMLSLL_VG4_M4Z4Z_BtoS = 8339 + + UMLSLL_VG4_M4Z4Z_HtoD = 8340 + + UMLSLL_VG4_M4ZZI_BtoS = 8341 + + UMLSLL_VG4_M4ZZI_HtoD = 8342 + + UMLSLL_VG4_M4ZZ_BtoS = 8343 + + UMLSLL_VG4_M4ZZ_HtoD = 8344 + + UMLSLT_ZZZI_D = 8345 + + UMLSLT_ZZZI_S = 8346 + + UMLSLT_ZZZ_D = 8347 + + UMLSLT_ZZZ_H = 8348 + + UMLSLT_ZZZ_S = 8349 + + UMLSL_MZZI_HtoS = 8350 + + UMLSL_MZZ_HtoS = 8351 + + UMLSL_VG2_M2Z2Z_HtoS = 8352 + + UMLSL_VG2_M2ZZI_S = 8353 + + UMLSL_VG2_M2ZZ_HtoS = 8354 + + UMLSL_VG4_M4Z4Z_HtoS = 8355 + + UMLSL_VG4_M4ZZI_HtoS = 8356 + + UMLSL_VG4_M4ZZ_HtoS = 8357 + + UMLSLv16i8_v8i16 = 8358 + + UMLSLv2i32_indexed = 8359 + + UMLSLv2i32_v2i64 = 8360 + + UMLSLv4i16_indexed = 8361 + + UMLSLv4i16_v4i32 = 8362 + + UMLSLv4i32_indexed = 8363 + + UMLSLv4i32_v2i64 = 8364 + + UMLSLv8i16_indexed = 8365 + + UMLSLv8i16_v4i32 = 8366 + + UMLSLv8i8_v8i16 = 8367 + + UMMLA = 8368 + + UMMLA_ZZZ = 8369 + + UMOP4A_M2Z2Z_BToS = 8370 + + UMOP4A_M2Z2Z_HToS = 8371 + + UMOP4A_M2Z2Z_HtoD = 8372 + + UMOP4A_M2ZZ_BToS = 8373 + + UMOP4A_M2ZZ_HToS = 8374 + + UMOP4A_M2ZZ_HtoD = 8375 + + UMOP4A_MZ2Z_BToS = 8376 + + UMOP4A_MZ2Z_HToS = 8377 + + UMOP4A_MZ2Z_HtoD = 8378 + + UMOP4A_MZZ_BToS = 8379 + + UMOP4A_MZZ_HToS = 8380 + + UMOP4A_MZZ_HtoD = 8381 + + UMOP4S_M2Z2Z_BToS = 8382 + + UMOP4S_M2Z2Z_HToS = 8383 + + UMOP4S_M2Z2Z_HtoD = 8384 + + UMOP4S_M2ZZ_BToS = 8385 + + UMOP4S_M2ZZ_HToS = 8386 + + UMOP4S_M2ZZ_HtoD = 8387 + + UMOP4S_MZ2Z_BToS = 8388 + + UMOP4S_MZ2Z_HToS = 8389 + + UMOP4S_MZ2Z_HtoD = 8390 + + UMOP4S_MZZ_BToS = 8391 + + UMOP4S_MZZ_HToS = 8392 + + UMOP4S_MZZ_HtoD = 8393 + + UMOPA_MPPZZ_D = 8394 + + UMOPA_MPPZZ_HtoS = 8395 + + UMOPA_MPPZZ_S = 8396 + + UMOPS_MPPZZ_D = 8397 + + UMOPS_MPPZZ_HtoS = 8398 + + UMOPS_MPPZZ_S = 8399 + + UMOVvi16 = 8400 + + UMOVvi16_idx0 = 8401 + + UMOVvi32 = 8402 + + UMOVvi32_idx0 = 8403 + + UMOVvi64 = 8404 + + UMOVvi64_idx0 = 8405 + + UMOVvi8 = 8406 + + UMOVvi8_idx0 = 8407 + + UMSUBLrrr = 8408 + + UMULH_ZPmZ_B = 8409 + + UMULH_ZPmZ_D = 8410 + + UMULH_ZPmZ_H = 8411 + + UMULH_ZPmZ_S = 8412 + + UMULH_ZZZ_B = 8413 + + UMULH_ZZZ_D = 8414 + + UMULH_ZZZ_H = 8415 + + UMULH_ZZZ_S = 8416 + + UMULHrr = 8417 + + UMULLB_ZZZI_D = 8418 + + UMULLB_ZZZI_S = 8419 + + UMULLB_ZZZ_D = 8420 + + UMULLB_ZZZ_H = 8421 + + UMULLB_ZZZ_S = 8422 + + UMULLT_ZZZI_D = 8423 + + UMULLT_ZZZI_S = 8424 + + UMULLT_ZZZ_D = 8425 + + UMULLT_ZZZ_H = 8426 + + UMULLT_ZZZ_S = 8427 + + UMULLv16i8_v8i16 = 8428 + + UMULLv2i32_indexed = 8429 + + UMULLv2i32_v2i64 = 8430 + + UMULLv4i16_indexed = 8431 + + UMULLv4i16_v4i32 = 8432 + + UMULLv4i32_indexed = 8433 + + UMULLv4i32_v2i64 = 8434 + + UMULLv8i16_indexed = 8435 + + UMULLv8i16_v4i32 = 8436 + + UMULLv8i8_v8i16 = 8437 + + UQADD_ZI_B = 8438 + + UQADD_ZI_D = 8439 + + UQADD_ZI_H = 8440 + + UQADD_ZI_S = 8441 + + UQADD_ZPmZ_B = 8442 + + UQADD_ZPmZ_D = 8443 + + UQADD_ZPmZ_H = 8444 + + UQADD_ZPmZ_S = 8445 + + UQADD_ZZZ_B = 8446 + + UQADD_ZZZ_D = 8447 + + UQADD_ZZZ_H = 8448 + + UQADD_ZZZ_S = 8449 + + UQADDv16i8 = 8450 + + UQADDv1i16 = 8451 + + UQADDv1i32 = 8452 + + UQADDv1i64 = 8453 + + UQADDv1i8 = 8454 + + UQADDv2i32 = 8455 + + UQADDv2i64 = 8456 + + UQADDv4i16 = 8457 + + UQADDv4i32 = 8458 + + UQADDv8i16 = 8459 + + UQADDv8i8 = 8460 + + UQCVTN_Z2Z_StoH = 8461 + + UQCVTN_Z4Z_DtoH = 8462 + + UQCVTN_Z4Z_StoB = 8463 + + UQCVT_Z2Z_StoH = 8464 + + UQCVT_Z4Z_DtoH = 8465 + + UQCVT_Z4Z_StoB = 8466 + + UQDECB_WPiI = 8467 + + UQDECB_XPiI = 8468 + + UQDECD_WPiI = 8469 + + UQDECD_XPiI = 8470 + + UQDECD_ZPiI = 8471 + + UQDECH_WPiI = 8472 + + UQDECH_XPiI = 8473 + + UQDECH_ZPiI = 8474 + + UQDECP_WP_B = 8475 + + UQDECP_WP_D = 8476 + + UQDECP_WP_H = 8477 + + UQDECP_WP_S = 8478 + + UQDECP_XP_B = 8479 + + UQDECP_XP_D = 8480 + + UQDECP_XP_H = 8481 + + UQDECP_XP_S = 8482 + + UQDECP_ZP_D = 8483 + + UQDECP_ZP_H = 8484 + + UQDECP_ZP_S = 8485 + + UQDECW_WPiI = 8486 + + UQDECW_XPiI = 8487 + + UQDECW_ZPiI = 8488 + + UQINCB_WPiI = 8489 + + UQINCB_XPiI = 8490 + + UQINCD_WPiI = 8491 + + UQINCD_XPiI = 8492 + + UQINCD_ZPiI = 8493 + + UQINCH_WPiI = 8494 + + UQINCH_XPiI = 8495 + + UQINCH_ZPiI = 8496 + + UQINCP_WP_B = 8497 + + UQINCP_WP_D = 8498 + + UQINCP_WP_H = 8499 + + UQINCP_WP_S = 8500 + + UQINCP_XP_B = 8501 + + UQINCP_XP_D = 8502 + + UQINCP_XP_H = 8503 + + UQINCP_XP_S = 8504 + + UQINCP_ZP_D = 8505 + + UQINCP_ZP_H = 8506 + + UQINCP_ZP_S = 8507 + + UQINCW_WPiI = 8508 + + UQINCW_XPiI = 8509 + + UQINCW_ZPiI = 8510 + + UQRSHLR_ZPmZ_B = 8511 + + UQRSHLR_ZPmZ_D = 8512 + + UQRSHLR_ZPmZ_H = 8513 + + UQRSHLR_ZPmZ_S = 8514 + + UQRSHL_ZPmZ_B = 8515 + + UQRSHL_ZPmZ_D = 8516 + + UQRSHL_ZPmZ_H = 8517 + + UQRSHL_ZPmZ_S = 8518 + + UQRSHLv16i8 = 8519 + + UQRSHLv1i16 = 8520 + + UQRSHLv1i32 = 8521 + + UQRSHLv1i64 = 8522 + + UQRSHLv1i8 = 8523 + + UQRSHLv2i32 = 8524 + + UQRSHLv2i64 = 8525 + + UQRSHLv4i16 = 8526 + + UQRSHLv4i32 = 8527 + + UQRSHLv8i16 = 8528 + + UQRSHLv8i8 = 8529 + + UQRSHRNB_ZZI_B = 8530 + + UQRSHRNB_ZZI_H = 8531 + + UQRSHRNB_ZZI_S = 8532 + + UQRSHRNT_ZZI_B = 8533 + + UQRSHRNT_ZZI_H = 8534 + + UQRSHRNT_ZZI_S = 8535 + + UQRSHRN_VG4_Z4ZI_B = 8536 + + UQRSHRN_VG4_Z4ZI_H = 8537 + + UQRSHRN_Z2ZI_HtoB = 8538 + + UQRSHRN_Z2ZI_StoH = 8539 + + UQRSHRNb = 8540 + + UQRSHRNh = 8541 + + UQRSHRNs = 8542 + + UQRSHRNv16i8_shift = 8543 + + UQRSHRNv2i32_shift = 8544 + + UQRSHRNv4i16_shift = 8545 + + UQRSHRNv4i32_shift = 8546 + + UQRSHRNv8i16_shift = 8547 + + UQRSHRNv8i8_shift = 8548 + + UQRSHR_VG2_Z2ZI_H = 8549 + + UQRSHR_VG4_Z4ZI_B = 8550 + + UQRSHR_VG4_Z4ZI_H = 8551 + + UQSHLR_ZPmZ_B = 8552 + + UQSHLR_ZPmZ_D = 8553 + + UQSHLR_ZPmZ_H = 8554 + + UQSHLR_ZPmZ_S = 8555 + + UQSHL_ZPmI_B = 8556 + + UQSHL_ZPmI_D = 8557 + + UQSHL_ZPmI_H = 8558 + + UQSHL_ZPmI_S = 8559 + + UQSHL_ZPmZ_B = 8560 + + UQSHL_ZPmZ_D = 8561 + + UQSHL_ZPmZ_H = 8562 + + UQSHL_ZPmZ_S = 8563 + + UQSHLb = 8564 + + UQSHLd = 8565 + + UQSHLh = 8566 + + UQSHLs = 8567 + + UQSHLv16i8 = 8568 + + UQSHLv16i8_shift = 8569 + + UQSHLv1i16 = 8570 + + UQSHLv1i32 = 8571 + + UQSHLv1i64 = 8572 + + UQSHLv1i8 = 8573 + + UQSHLv2i32 = 8574 + + UQSHLv2i32_shift = 8575 + + UQSHLv2i64 = 8576 + + UQSHLv2i64_shift = 8577 + + UQSHLv4i16 = 8578 + + UQSHLv4i16_shift = 8579 + + UQSHLv4i32 = 8580 + + UQSHLv4i32_shift = 8581 + + UQSHLv8i16 = 8582 + + UQSHLv8i16_shift = 8583 + + UQSHLv8i8 = 8584 + + UQSHLv8i8_shift = 8585 + + UQSHRNB_ZZI_B = 8586 + + UQSHRNB_ZZI_H = 8587 + + UQSHRNB_ZZI_S = 8588 + + UQSHRNT_ZZI_B = 8589 + + UQSHRNT_ZZI_H = 8590 + + UQSHRNT_ZZI_S = 8591 + + UQSHRN_Z2ZI_HtoB = 8592 + + UQSHRN_Z2ZI_StoH = 8593 + + UQSHRNb = 8594 + + UQSHRNh = 8595 + + UQSHRNs = 8596 + + UQSHRNv16i8_shift = 8597 + + UQSHRNv2i32_shift = 8598 + + UQSHRNv4i16_shift = 8599 + + UQSHRNv4i32_shift = 8600 + + UQSHRNv8i16_shift = 8601 + + UQSHRNv8i8_shift = 8602 + + UQSUBR_ZPmZ_B = 8603 + + UQSUBR_ZPmZ_D = 8604 + + UQSUBR_ZPmZ_H = 8605 + + UQSUBR_ZPmZ_S = 8606 + + UQSUB_ZI_B = 8607 + + UQSUB_ZI_D = 8608 + + UQSUB_ZI_H = 8609 + + UQSUB_ZI_S = 8610 + + UQSUB_ZPmZ_B = 8611 + + UQSUB_ZPmZ_D = 8612 + + UQSUB_ZPmZ_H = 8613 + + UQSUB_ZPmZ_S = 8614 + + UQSUB_ZZZ_B = 8615 + + UQSUB_ZZZ_D = 8616 + + UQSUB_ZZZ_H = 8617 + + UQSUB_ZZZ_S = 8618 + + UQSUBv16i8 = 8619 + + UQSUBv1i16 = 8620 + + UQSUBv1i32 = 8621 + + UQSUBv1i64 = 8622 + + UQSUBv1i8 = 8623 + + UQSUBv2i32 = 8624 + + UQSUBv2i64 = 8625 + + UQSUBv4i16 = 8626 + + UQSUBv4i32 = 8627 + + UQSUBv8i16 = 8628 + + UQSUBv8i8 = 8629 + + UQXTNB_ZZ_B = 8630 + + UQXTNB_ZZ_H = 8631 + + UQXTNB_ZZ_S = 8632 + + UQXTNT_ZZ_B = 8633 + + UQXTNT_ZZ_H = 8634 + + UQXTNT_ZZ_S = 8635 + + UQXTNv16i8 = 8636 + + UQXTNv1i16 = 8637 + + UQXTNv1i32 = 8638 + + UQXTNv1i8 = 8639 + + UQXTNv2i32 = 8640 + + UQXTNv4i16 = 8641 + + UQXTNv4i32 = 8642 + + UQXTNv8i16 = 8643 + + UQXTNv8i8 = 8644 + + URECPE_ZPmZ_S = 8645 + + URECPE_ZPzZ_S = 8646 + + URECPEv2i32 = 8647 + + URECPEv4i32 = 8648 + + URHADD_ZPmZ_B = 8649 + + URHADD_ZPmZ_D = 8650 + + URHADD_ZPmZ_H = 8651 + + URHADD_ZPmZ_S = 8652 + + URHADDv16i8 = 8653 + + URHADDv2i32 = 8654 + + URHADDv4i16 = 8655 + + URHADDv4i32 = 8656 + + URHADDv8i16 = 8657 + + URHADDv8i8 = 8658 + + URSHLR_ZPmZ_B = 8659 + + URSHLR_ZPmZ_D = 8660 + + URSHLR_ZPmZ_H = 8661 + + URSHLR_ZPmZ_S = 8662 + + URSHL_VG2_2Z2Z_B = 8663 + + URSHL_VG2_2Z2Z_D = 8664 + + URSHL_VG2_2Z2Z_H = 8665 + + URSHL_VG2_2Z2Z_S = 8666 + + URSHL_VG2_2ZZ_B = 8667 + + URSHL_VG2_2ZZ_D = 8668 + + URSHL_VG2_2ZZ_H = 8669 + + URSHL_VG2_2ZZ_S = 8670 + + URSHL_VG4_4Z4Z_B = 8671 + + URSHL_VG4_4Z4Z_D = 8672 + + URSHL_VG4_4Z4Z_H = 8673 + + URSHL_VG4_4Z4Z_S = 8674 + + URSHL_VG4_4ZZ_B = 8675 + + URSHL_VG4_4ZZ_D = 8676 + + URSHL_VG4_4ZZ_H = 8677 + + URSHL_VG4_4ZZ_S = 8678 + + URSHL_ZPmZ_B = 8679 + + URSHL_ZPmZ_D = 8680 + + URSHL_ZPmZ_H = 8681 + + URSHL_ZPmZ_S = 8682 + + URSHLv16i8 = 8683 + + URSHLv1i64 = 8684 + + URSHLv2i32 = 8685 + + URSHLv2i64 = 8686 + + URSHLv4i16 = 8687 + + URSHLv4i32 = 8688 + + URSHLv8i16 = 8689 + + URSHLv8i8 = 8690 + + URSHR_ZPmI_B = 8691 + + URSHR_ZPmI_D = 8692 + + URSHR_ZPmI_H = 8693 + + URSHR_ZPmI_S = 8694 + + URSHRd = 8695 + + URSHRv16i8_shift = 8696 + + URSHRv2i32_shift = 8697 + + URSHRv2i64_shift = 8698 + + URSHRv4i16_shift = 8699 + + URSHRv4i32_shift = 8700 + + URSHRv8i16_shift = 8701 + + URSHRv8i8_shift = 8702 + + URSQRTE_ZPmZ_S = 8703 + + URSQRTE_ZPzZ_S = 8704 + + URSQRTEv2i32 = 8705 + + URSQRTEv4i32 = 8706 + + URSRA_ZZI_B = 8707 + + URSRA_ZZI_D = 8708 + + URSRA_ZZI_H = 8709 + + URSRA_ZZI_S = 8710 + + URSRAd = 8711 + + URSRAv16i8_shift = 8712 + + URSRAv2i32_shift = 8713 + + URSRAv2i64_shift = 8714 + + URSRAv4i16_shift = 8715 + + URSRAv4i32_shift = 8716 + + URSRAv8i16_shift = 8717 + + URSRAv8i8_shift = 8718 + + USDOT_VG2_M2Z2Z_BToS = 8719 + + USDOT_VG2_M2ZZI_BToS = 8720 + + USDOT_VG2_M2ZZ_BToS = 8721 + + USDOT_VG4_M4Z4Z_BToS = 8722 + + USDOT_VG4_M4ZZI_BToS = 8723 + + USDOT_VG4_M4ZZ_BToS = 8724 + + USDOT_ZZZ = 8725 + + USDOT_ZZZI = 8726 + + USDOTlanev16i8 = 8727 + + USDOTlanev8i8 = 8728 + + USDOTv16i8 = 8729 + + USDOTv8i8 = 8730 + + USHLLB_ZZI_D = 8731 + + USHLLB_ZZI_H = 8732 + + USHLLB_ZZI_S = 8733 + + USHLLT_ZZI_D = 8734 + + USHLLT_ZZI_H = 8735 + + USHLLT_ZZI_S = 8736 + + USHLLv16i8_shift = 8737 + + USHLLv2i32_shift = 8738 + + USHLLv4i16_shift = 8739 + + USHLLv4i32_shift = 8740 + + USHLLv8i16_shift = 8741 + + USHLLv8i8_shift = 8742 + + USHLv16i8 = 8743 + + USHLv1i64 = 8744 + + USHLv2i32 = 8745 + + USHLv2i64 = 8746 + + USHLv4i16 = 8747 + + USHLv4i32 = 8748 + + USHLv8i16 = 8749 + + USHLv8i8 = 8750 + + USHRd = 8751 + + USHRv16i8_shift = 8752 + + USHRv2i32_shift = 8753 + + USHRv2i64_shift = 8754 + + USHRv4i16_shift = 8755 + + USHRv4i32_shift = 8756 + + USHRv8i16_shift = 8757 + + USHRv8i8_shift = 8758 + + USMLALL_MZZI_BtoS = 8759 + + USMLALL_MZZ_BtoS = 8760 + + USMLALL_VG2_M2Z2Z_BtoS = 8761 + + USMLALL_VG2_M2ZZI_BtoS = 8762 + + USMLALL_VG2_M2ZZ_BtoS = 8763 + + USMLALL_VG4_M4Z4Z_BtoS = 8764 + + USMLALL_VG4_M4ZZI_BtoS = 8765 + + USMLALL_VG4_M4ZZ_BtoS = 8766 + + USMMLA = 8767 + + USMMLA_ZZZ = 8768 + + USMOP4A_M2Z2Z_BToS = 8769 + + USMOP4A_M2Z2Z_HtoD = 8770 + + USMOP4A_M2ZZ_BToS = 8771 + + USMOP4A_M2ZZ_HtoD = 8772 + + USMOP4A_MZ2Z_BToS = 8773 + + USMOP4A_MZ2Z_HtoD = 8774 + + USMOP4A_MZZ_BToS = 8775 + + USMOP4A_MZZ_HtoD = 8776 + + USMOP4S_M2Z2Z_BToS = 8777 + + USMOP4S_M2Z2Z_HtoD = 8778 + + USMOP4S_M2ZZ_BToS = 8779 + + USMOP4S_M2ZZ_HtoD = 8780 + + USMOP4S_MZ2Z_BToS = 8781 + + USMOP4S_MZ2Z_HtoD = 8782 + + USMOP4S_MZZ_BToS = 8783 + + USMOP4S_MZZ_HtoD = 8784 + + USMOPA_MPPZZ_D = 8785 + + USMOPA_MPPZZ_S = 8786 + + USMOPS_MPPZZ_D = 8787 + + USMOPS_MPPZZ_S = 8788 + + USQADD_ZPmZ_B = 8789 + + USQADD_ZPmZ_D = 8790 + + USQADD_ZPmZ_H = 8791 + + USQADD_ZPmZ_S = 8792 + + USQADDv16i8 = 8793 + + USQADDv1i16 = 8794 + + USQADDv1i32 = 8795 + + USQADDv1i64 = 8796 + + USQADDv1i8 = 8797 + + USQADDv2i32 = 8798 + + USQADDv2i64 = 8799 + + USQADDv4i16 = 8800 + + USQADDv4i32 = 8801 + + USQADDv8i16 = 8802 + + USQADDv8i8 = 8803 + + USRA_ZZI_B = 8804 + + USRA_ZZI_D = 8805 + + USRA_ZZI_H = 8806 + + USRA_ZZI_S = 8807 + + USRAd = 8808 + + USRAv16i8_shift = 8809 + + USRAv2i32_shift = 8810 + + USRAv2i64_shift = 8811 + + USRAv4i16_shift = 8812 + + USRAv4i32_shift = 8813 + + USRAv8i16_shift = 8814 + + USRAv8i8_shift = 8815 + + USTMOPA_M2ZZZI_BtoS = 8816 + + USUBLB_ZZZ_D = 8817 + + USUBLB_ZZZ_H = 8818 + + USUBLB_ZZZ_S = 8819 + + USUBLT_ZZZ_D = 8820 + + USUBLT_ZZZ_H = 8821 + + USUBLT_ZZZ_S = 8822 + + USUBLv16i8_v8i16 = 8823 + + USUBLv2i32_v2i64 = 8824 + + USUBLv4i16_v4i32 = 8825 + + USUBLv4i32_v2i64 = 8826 + + USUBLv8i16_v4i32 = 8827 + + USUBLv8i8_v8i16 = 8828 + + USUBWB_ZZZ_D = 8829 + + USUBWB_ZZZ_H = 8830 + + USUBWB_ZZZ_S = 8831 + + USUBWT_ZZZ_D = 8832 + + USUBWT_ZZZ_H = 8833 + + USUBWT_ZZZ_S = 8834 + + USUBWv16i8_v8i16 = 8835 + + USUBWv2i32_v2i64 = 8836 + + USUBWv4i16_v4i32 = 8837 + + USUBWv4i32_v2i64 = 8838 + + USUBWv8i16_v4i32 = 8839 + + USUBWv8i8_v8i16 = 8840 + + USVDOT_VG4_M4ZZI_BToS = 8841 + + UTMOPA_M2ZZZI_BtoS = 8842 + + UTMOPA_M2ZZZI_HtoS = 8843 + + UUNPKHI_ZZ_D = 8844 + + UUNPKHI_ZZ_H = 8845 + + UUNPKHI_ZZ_S = 8846 + + UUNPKLO_ZZ_D = 8847 + + UUNPKLO_ZZ_H = 8848 + + UUNPKLO_ZZ_S = 8849 + + UUNPK_VG2_2ZZ_D = 8850 + + UUNPK_VG2_2ZZ_H = 8851 + + UUNPK_VG2_2ZZ_S = 8852 + + UUNPK_VG4_4Z2Z_D = 8853 + + UUNPK_VG4_4Z2Z_H = 8854 + + UUNPK_VG4_4Z2Z_S = 8855 + + UVDOT_VG2_M2ZZI_HtoS = 8856 + + UVDOT_VG4_M4ZZI_BtoS = 8857 + + UVDOT_VG4_M4ZZI_HtoD = 8858 + + UXTB_ZPmZ_D = 8859 + + UXTB_ZPmZ_H = 8860 + + UXTB_ZPmZ_S = 8861 + + UXTB_ZPzZ_D = 8862 + + UXTB_ZPzZ_H = 8863 + + UXTB_ZPzZ_S = 8864 + + UXTH_ZPmZ_D = 8865 + + UXTH_ZPmZ_S = 8866 + + UXTH_ZPzZ_D = 8867 + + UXTH_ZPzZ_S = 8868 + + UXTW_ZPmZ_D = 8869 + + UXTW_ZPzZ_D = 8870 + + UZP1_PPP_B = 8871 + + UZP1_PPP_D = 8872 + + UZP1_PPP_H = 8873 + + UZP1_PPP_S = 8874 + + UZP1_ZZZ_B = 8875 + + UZP1_ZZZ_D = 8876 + + UZP1_ZZZ_H = 8877 + + UZP1_ZZZ_Q = 8878 + + UZP1_ZZZ_S = 8879 + + UZP1v16i8 = 8880 + + UZP1v2i32 = 8881 + + UZP1v2i64 = 8882 + + UZP1v4i16 = 8883 + + UZP1v4i32 = 8884 + + UZP1v8i16 = 8885 + + UZP1v8i8 = 8886 + + UZP2_PPP_B = 8887 + + UZP2_PPP_D = 8888 + + UZP2_PPP_H = 8889 + + UZP2_PPP_S = 8890 + + UZP2_ZZZ_B = 8891 + + UZP2_ZZZ_D = 8892 + + UZP2_ZZZ_H = 8893 + + UZP2_ZZZ_Q = 8894 + + UZP2_ZZZ_S = 8895 + + UZP2v16i8 = 8896 + + UZP2v2i32 = 8897 + + UZP2v2i64 = 8898 + + UZP2v4i16 = 8899 + + UZP2v4i32 = 8900 + + UZP2v8i16 = 8901 + + UZP2v8i8 = 8902 + + UZPQ1_ZZZ_B = 8903 + + UZPQ1_ZZZ_D = 8904 + + UZPQ1_ZZZ_H = 8905 + + UZPQ1_ZZZ_S = 8906 + + UZPQ2_ZZZ_B = 8907 + + UZPQ2_ZZZ_D = 8908 + + UZPQ2_ZZZ_H = 8909 + + UZPQ2_ZZZ_S = 8910 + + UZP_VG2_2ZZZ_B = 8911 + + UZP_VG2_2ZZZ_D = 8912 + + UZP_VG2_2ZZZ_H = 8913 + + UZP_VG2_2ZZZ_Q = 8914 + + UZP_VG2_2ZZZ_S = 8915 + + UZP_VG4_4Z4Z_B = 8916 + + UZP_VG4_4Z4Z_D = 8917 + + UZP_VG4_4Z4Z_H = 8918 + + UZP_VG4_4Z4Z_Q = 8919 + + UZP_VG4_4Z4Z_S = 8920 + + WFET = 8921 + + WFIT = 8922 + + WHILEGE_2PXX_B = 8923 + + WHILEGE_2PXX_D = 8924 + + WHILEGE_2PXX_H = 8925 + + WHILEGE_2PXX_S = 8926 + + WHILEGE_CXX_B = 8927 + + WHILEGE_CXX_D = 8928 + + WHILEGE_CXX_H = 8929 + + WHILEGE_CXX_S = 8930 + + WHILEGE_PWW_B = 8931 + + WHILEGE_PWW_D = 8932 + + WHILEGE_PWW_H = 8933 + + WHILEGE_PWW_S = 8934 + + WHILEGE_PXX_B = 8935 + + WHILEGE_PXX_D = 8936 + + WHILEGE_PXX_H = 8937 + + WHILEGE_PXX_S = 8938 + + WHILEGT_2PXX_B = 8939 + + WHILEGT_2PXX_D = 8940 + + WHILEGT_2PXX_H = 8941 + + WHILEGT_2PXX_S = 8942 + + WHILEGT_CXX_B = 8943 + + WHILEGT_CXX_D = 8944 + + WHILEGT_CXX_H = 8945 + + WHILEGT_CXX_S = 8946 + + WHILEGT_PWW_B = 8947 + + WHILEGT_PWW_D = 8948 + + WHILEGT_PWW_H = 8949 + + WHILEGT_PWW_S = 8950 + + WHILEGT_PXX_B = 8951 + + WHILEGT_PXX_D = 8952 + + WHILEGT_PXX_H = 8953 + + WHILEGT_PXX_S = 8954 + + WHILEHI_2PXX_B = 8955 + + WHILEHI_2PXX_D = 8956 + + WHILEHI_2PXX_H = 8957 + + WHILEHI_2PXX_S = 8958 + + WHILEHI_CXX_B = 8959 + + WHILEHI_CXX_D = 8960 + + WHILEHI_CXX_H = 8961 + + WHILEHI_CXX_S = 8962 + + WHILEHI_PWW_B = 8963 + + WHILEHI_PWW_D = 8964 + + WHILEHI_PWW_H = 8965 + + WHILEHI_PWW_S = 8966 + + WHILEHI_PXX_B = 8967 + + WHILEHI_PXX_D = 8968 + + WHILEHI_PXX_H = 8969 + + WHILEHI_PXX_S = 8970 + + WHILEHS_2PXX_B = 8971 + + WHILEHS_2PXX_D = 8972 + + WHILEHS_2PXX_H = 8973 + + WHILEHS_2PXX_S = 8974 + + WHILEHS_CXX_B = 8975 + + WHILEHS_CXX_D = 8976 + + WHILEHS_CXX_H = 8977 + + WHILEHS_CXX_S = 8978 + + WHILEHS_PWW_B = 8979 + + WHILEHS_PWW_D = 8980 + + WHILEHS_PWW_H = 8981 + + WHILEHS_PWW_S = 8982 + + WHILEHS_PXX_B = 8983 + + WHILEHS_PXX_D = 8984 + + WHILEHS_PXX_H = 8985 + + WHILEHS_PXX_S = 8986 + + WHILELE_2PXX_B = 8987 + + WHILELE_2PXX_D = 8988 + + WHILELE_2PXX_H = 8989 + + WHILELE_2PXX_S = 8990 + + WHILELE_CXX_B = 8991 + + WHILELE_CXX_D = 8992 + + WHILELE_CXX_H = 8993 + + WHILELE_CXX_S = 8994 + + WHILELE_PWW_B = 8995 + + WHILELE_PWW_D = 8996 + + WHILELE_PWW_H = 8997 + + WHILELE_PWW_S = 8998 + + WHILELE_PXX_B = 8999 + + WHILELE_PXX_D = 9000 + + WHILELE_PXX_H = 9001 + + WHILELE_PXX_S = 9002 + + WHILELO_2PXX_B = 9003 + + WHILELO_2PXX_D = 9004 + + WHILELO_2PXX_H = 9005 + + WHILELO_2PXX_S = 9006 + + WHILELO_CXX_B = 9007 + + WHILELO_CXX_D = 9008 + + WHILELO_CXX_H = 9009 + + WHILELO_CXX_S = 9010 + + WHILELO_PWW_B = 9011 + + WHILELO_PWW_D = 9012 + + WHILELO_PWW_H = 9013 + + WHILELO_PWW_S = 9014 + + WHILELO_PXX_B = 9015 + + WHILELO_PXX_D = 9016 + + WHILELO_PXX_H = 9017 + + WHILELO_PXX_S = 9018 + + WHILELS_2PXX_B = 9019 + + WHILELS_2PXX_D = 9020 + + WHILELS_2PXX_H = 9021 + + WHILELS_2PXX_S = 9022 + + WHILELS_CXX_B = 9023 + + WHILELS_CXX_D = 9024 + + WHILELS_CXX_H = 9025 + + WHILELS_CXX_S = 9026 + + WHILELS_PWW_B = 9027 + + WHILELS_PWW_D = 9028 + + WHILELS_PWW_H = 9029 + + WHILELS_PWW_S = 9030 + + WHILELS_PXX_B = 9031 + + WHILELS_PXX_D = 9032 + + WHILELS_PXX_H = 9033 + + WHILELS_PXX_S = 9034 + + WHILELT_2PXX_B = 9035 + + WHILELT_2PXX_D = 9036 + + WHILELT_2PXX_H = 9037 + + WHILELT_2PXX_S = 9038 + + WHILELT_CXX_B = 9039 + + WHILELT_CXX_D = 9040 + + WHILELT_CXX_H = 9041 + + WHILELT_CXX_S = 9042 + + WHILELT_PWW_B = 9043 + + WHILELT_PWW_D = 9044 + + WHILELT_PWW_H = 9045 + + WHILELT_PWW_S = 9046 + + WHILELT_PXX_B = 9047 + + WHILELT_PXX_D = 9048 + + WHILELT_PXX_H = 9049 + + WHILELT_PXX_S = 9050 + + WHILERW_PXX_B = 9051 + + WHILERW_PXX_D = 9052 + + WHILERW_PXX_H = 9053 + + WHILERW_PXX_S = 9054 + + WHILEWR_PXX_B = 9055 + + WHILEWR_PXX_D = 9056 + + WHILEWR_PXX_H = 9057 + + WHILEWR_PXX_S = 9058 + + WRFFR = 9059 + + XAFLAG = 9060 + + XAR = 9061 + + XAR_ZZZI_B = 9062 + + XAR_ZZZI_D = 9063 + + XAR_ZZZI_H = 9064 + + XAR_ZZZI_S = 9065 + + XPACD = 9066 + + XPACI = 9067 + + XPACLRI = 9068 + + XTNv16i8 = 9069 + + XTNv2i32 = 9070 + + XTNv4i16 = 9071 + + XTNv4i32 = 9072 + + XTNv8i16 = 9073 + + XTNv8i8 = 9074 + + ZERO_M = 9075 + + ZERO_MXI_2Z = 9076 + + ZERO_MXI_4Z = 9077 + + ZERO_MXI_VG2_2Z = 9078 + + ZERO_MXI_VG2_4Z = 9079 + + ZERO_MXI_VG2_Z = 9080 + + ZERO_MXI_VG4_2Z = 9081 + + ZERO_MXI_VG4_4Z = 9082 + + ZERO_MXI_VG4_Z = 9083 + + ZERO_T = 9084 + + ZIP1_PPP_B = 9085 + + ZIP1_PPP_D = 9086 + + ZIP1_PPP_H = 9087 + + ZIP1_PPP_S = 9088 + + ZIP1_ZZZ_B = 9089 + + ZIP1_ZZZ_D = 9090 + + ZIP1_ZZZ_H = 9091 + + ZIP1_ZZZ_Q = 9092 + + ZIP1_ZZZ_S = 9093 + + ZIP1v16i8 = 9094 + + ZIP1v2i32 = 9095 + + ZIP1v2i64 = 9096 + + ZIP1v4i16 = 9097 + + ZIP1v4i32 = 9098 + + ZIP1v8i16 = 9099 + + ZIP1v8i8 = 9100 + + ZIP2_PPP_B = 9101 + + ZIP2_PPP_D = 9102 + + ZIP2_PPP_H = 9103 + + ZIP2_PPP_S = 9104 + + ZIP2_ZZZ_B = 9105 + + ZIP2_ZZZ_D = 9106 + + ZIP2_ZZZ_H = 9107 + + ZIP2_ZZZ_Q = 9108 + + ZIP2_ZZZ_S = 9109 + + ZIP2v16i8 = 9110 + + ZIP2v2i32 = 9111 + + ZIP2v2i64 = 9112 + + ZIP2v4i16 = 9113 + + ZIP2v4i32 = 9114 + + ZIP2v8i16 = 9115 + + ZIP2v8i8 = 9116 + + ZIPQ1_ZZZ_B = 9117 + + ZIPQ1_ZZZ_D = 9118 + + ZIPQ1_ZZZ_H = 9119 + + ZIPQ1_ZZZ_S = 9120 + + ZIPQ2_ZZZ_B = 9121 + + ZIPQ2_ZZZ_D = 9122 + + ZIPQ2_ZZZ_H = 9123 + + ZIPQ2_ZZZ_S = 9124 + + ZIP_VG2_2ZZZ_B = 9125 + + ZIP_VG2_2ZZZ_D = 9126 + + ZIP_VG2_2ZZZ_H = 9127 + + ZIP_VG2_2ZZZ_Q = 9128 + + ZIP_VG2_2ZZZ_S = 9129 + + ZIP_VG4_4Z4Z_B = 9130 + + ZIP_VG4_4Z4Z_D = 9131 + + ZIP_VG4_4Z4Z_H = 9132 + + ZIP_VG4_4Z4Z_Q = 9133 + + ZIP_VG4_4Z4Z_S = 9134 + + INSTRUCTION_LIST_END = 9135 + +class REG(enum.Enum): + NoRegister = 0 + + FFR = 1 + + FP = 2 + + FPCR = 3 + + FPMR = 4 + + FPSR = 5 + + LR = 6 + + NZCV = 7 + + SP = 8 + + VG = 9 + + WSP = 10 + + WSP_HI = 11 + + WZR = 12 + + WZR_HI = 13 + + XZR = 14 + + ZA = 15 + + B0 = 16 + + B1 = 17 + + B2 = 18 + + B3 = 19 + + B4 = 20 + + B5 = 21 + + B6 = 22 + + B7 = 23 + + B8 = 24 + + B9 = 25 + + B10 = 26 + + B11 = 27 + + B12 = 28 + + B13 = 29 + + B14 = 30 + + B15 = 31 + + B16 = 32 + + B17 = 33 + + B18 = 34 + + B19 = 35 + + B20 = 36 + + B21 = 37 + + B22 = 38 + + B23 = 39 + + B24 = 40 + + B25 = 41 + + B26 = 42 + + B27 = 43 + + B28 = 44 + + B29 = 45 + + B30 = 46 + + B31 = 47 + + D0 = 48 + + D1 = 49 + + D2 = 50 + + D3 = 51 + + D4 = 52 + + D5 = 53 + + D6 = 54 + + D7 = 55 + + D8 = 56 + + D9 = 57 + + D10 = 58 + + D11 = 59 + + D12 = 60 + + D13 = 61 + + D14 = 62 + + D15 = 63 + + D16 = 64 + + D17 = 65 + + D18 = 66 + + D19 = 67 + + D20 = 68 + + D21 = 69 + + D22 = 70 + + D23 = 71 + + D24 = 72 + + D25 = 73 + + D26 = 74 + + D27 = 75 + + D28 = 76 + + D29 = 77 + + D30 = 78 + + D31 = 79 + + H0 = 80 + + H1 = 81 + + H2 = 82 + + H3 = 83 + + H4 = 84 + + H5 = 85 + + H6 = 86 + + H7 = 87 + + H8 = 88 + + H9 = 89 + + H10 = 90 + + H11 = 91 + + H12 = 92 + + H13 = 93 + + H14 = 94 + + H15 = 95 + + H16 = 96 + + H17 = 97 + + H18 = 98 + + H19 = 99 + + H20 = 100 + + H21 = 101 + + H22 = 102 + + H23 = 103 + + H24 = 104 + + H25 = 105 + + H26 = 106 + + H27 = 107 + + H28 = 108 + + H29 = 109 + + H30 = 110 + + H31 = 111 + + P0 = 112 + + P1 = 113 + + P2 = 114 + + P3 = 115 + + P4 = 116 + + P5 = 117 + + P6 = 118 + + P7 = 119 + + P8 = 120 + + P9 = 121 + + P10 = 122 + + P11 = 123 + + P12 = 124 + + P13 = 125 + + P14 = 126 + + P15 = 127 + + PN0 = 128 + + PN1 = 129 + + PN2 = 130 + + PN3 = 131 + + PN4 = 132 + + PN5 = 133 + + PN6 = 134 + + PN7 = 135 + + PN8 = 136 + + PN9 = 137 + + PN10 = 138 + + PN11 = 139 + + PN12 = 140 + + PN13 = 141 + + PN14 = 142 + + PN15 = 143 + + Q0 = 144 + + Q1 = 145 + + Q2 = 146 + + Q3 = 147 + + Q4 = 148 + + Q5 = 149 + + Q6 = 150 + + Q7 = 151 + + Q8 = 152 + + Q9 = 153 + + Q10 = 154 + + Q11 = 155 + + Q12 = 156 + + Q13 = 157 + + Q14 = 158 + + Q15 = 159 + + Q16 = 160 + + Q17 = 161 + + Q18 = 162 + + Q19 = 163 + + Q20 = 164 + + Q21 = 165 + + Q22 = 166 + + Q23 = 167 + + Q24 = 168 + + Q25 = 169 + + Q26 = 170 + + Q27 = 171 + + Q28 = 172 + + Q29 = 173 + + Q30 = 174 + + Q31 = 175 + + S0 = 176 + + S1 = 177 + + S2 = 178 + + S3 = 179 + + S4 = 180 + + S5 = 181 + + S6 = 182 + + S7 = 183 + + S8 = 184 + + S9 = 185 + + S10 = 186 + + S11 = 187 + + S12 = 188 + + S13 = 189 + + S14 = 190 + + S15 = 191 + + S16 = 192 + + S17 = 193 + + S18 = 194 + + S19 = 195 + + S20 = 196 + + S21 = 197 + + S22 = 198 + + S23 = 199 + + S24 = 200 + + S25 = 201 + + S26 = 202 + + S27 = 203 + + S28 = 204 + + S29 = 205 + + S30 = 206 + + S31 = 207 + + W0 = 208 + + W1 = 209 + + W2 = 210 + + W3 = 211 + + W4 = 212 + + W5 = 213 + + W6 = 214 + + W7 = 215 + + W8 = 216 + + W9 = 217 + + W10 = 218 + + W11 = 219 + + W12 = 220 + + W13 = 221 + + W14 = 222 + + W15 = 223 + + W16 = 224 + + W17 = 225 + + W18 = 226 + + W19 = 227 + + W20 = 228 + + W21 = 229 + + W22 = 230 + + W23 = 231 + + W24 = 232 + + W25 = 233 + + W26 = 234 + + W27 = 235 + + W28 = 236 + + W29 = 237 + + W30 = 238 + + X0 = 239 + + X1 = 240 + + X2 = 241 + + X3 = 242 + + X4 = 243 + + X5 = 244 + + X6 = 245 + + X7 = 246 + + X8 = 247 + + X9 = 248 + + X10 = 249 + + X11 = 250 + + X12 = 251 + + X13 = 252 + + X14 = 253 + + X15 = 254 + + X16 = 255 + + X17 = 256 + + X18 = 257 + + X19 = 258 + + X20 = 259 + + X21 = 260 + + X22 = 261 + + X23 = 262 + + X24 = 263 + + X25 = 264 + + X26 = 265 + + X27 = 266 + + X28 = 267 + + Z0 = 268 + + Z1 = 269 + + Z2 = 270 + + Z3 = 271 + + Z4 = 272 + + Z5 = 273 + + Z6 = 274 + + Z7 = 275 + + Z8 = 276 + + Z9 = 277 + + Z10 = 278 + + Z11 = 279 + + Z12 = 280 + + Z13 = 281 + + Z14 = 282 + + Z15 = 283 + + Z16 = 284 + + Z17 = 285 + + Z18 = 286 + + Z19 = 287 + + Z20 = 288 + + Z21 = 289 + + Z22 = 290 + + Z23 = 291 + + Z24 = 292 + + Z25 = 293 + + Z26 = 294 + + Z27 = 295 + + Z28 = 296 + + Z29 = 297 + + Z30 = 298 + + Z31 = 299 + + ZAB0 = 300 + + ZAD0 = 301 + + ZAD1 = 302 + + ZAD2 = 303 + + ZAD3 = 304 + + ZAD4 = 305 + + ZAD5 = 306 + + ZAD6 = 307 + + ZAD7 = 308 + + ZAH0 = 309 + + ZAH1 = 310 + + ZAQ0 = 311 + + ZAQ1 = 312 + + ZAQ2 = 313 + + ZAQ3 = 314 + + ZAQ4 = 315 + + ZAQ5 = 316 + + ZAQ6 = 317 + + ZAQ7 = 318 + + ZAQ8 = 319 + + ZAQ9 = 320 + + ZAQ10 = 321 + + ZAQ11 = 322 + + ZAQ12 = 323 + + ZAQ13 = 324 + + ZAQ14 = 325 + + ZAQ15 = 326 + + ZAS0 = 327 + + ZAS1 = 328 + + ZAS2 = 329 + + ZAS3 = 330 + + ZT0 = 331 + + B0_HI = 332 + + B1_HI = 333 + + B2_HI = 334 + + B3_HI = 335 + + B4_HI = 336 + + B5_HI = 337 + + B6_HI = 338 + + B7_HI = 339 + + B8_HI = 340 + + B9_HI = 341 + + B10_HI = 342 + + B11_HI = 343 + + B12_HI = 344 + + B13_HI = 345 + + B14_HI = 346 + + B15_HI = 347 + + B16_HI = 348 + + B17_HI = 349 + + B18_HI = 350 + + B19_HI = 351 + + B20_HI = 352 + + B21_HI = 353 + + B22_HI = 354 + + B23_HI = 355 + + B24_HI = 356 + + B25_HI = 357 + + B26_HI = 358 + + B27_HI = 359 + + B28_HI = 360 + + B29_HI = 361 + + B30_HI = 362 + + B31_HI = 363 + + D0_HI = 364 + + D1_HI = 365 + + D2_HI = 366 + + D3_HI = 367 + + D4_HI = 368 + + D5_HI = 369 + + D6_HI = 370 + + D7_HI = 371 + + D8_HI = 372 + + D9_HI = 373 + + D10_HI = 374 + + D11_HI = 375 + + D12_HI = 376 + + D13_HI = 377 + + D14_HI = 378 + + D15_HI = 379 + + D16_HI = 380 + + D17_HI = 381 + + D18_HI = 382 + + D19_HI = 383 + + D20_HI = 384 + + D21_HI = 385 + + D22_HI = 386 + + D23_HI = 387 + + D24_HI = 388 + + D25_HI = 389 + + D26_HI = 390 + + D27_HI = 391 + + D28_HI = 392 + + D29_HI = 393 + + D30_HI = 394 + + D31_HI = 395 + + H0_HI = 396 + + H1_HI = 397 + + H2_HI = 398 + + H3_HI = 399 + + H4_HI = 400 + + H5_HI = 401 + + H6_HI = 402 + + H7_HI = 403 + + H8_HI = 404 + + H9_HI = 405 + + H10_HI = 406 + + H11_HI = 407 + + H12_HI = 408 + + H13_HI = 409 + + H14_HI = 410 + + H15_HI = 411 + + H16_HI = 412 + + H17_HI = 413 + + H18_HI = 414 + + H19_HI = 415 + + H20_HI = 416 + + H21_HI = 417 + + H22_HI = 418 + + H23_HI = 419 + + H24_HI = 420 + + H25_HI = 421 + + H26_HI = 422 + + H27_HI = 423 + + H28_HI = 424 + + H29_HI = 425 + + H30_HI = 426 + + H31_HI = 427 + + Q0_HI = 428 + + Q1_HI = 429 + + Q2_HI = 430 + + Q3_HI = 431 + + Q4_HI = 432 + + Q5_HI = 433 + + Q6_HI = 434 + + Q7_HI = 435 + + Q8_HI = 436 + + Q9_HI = 437 + + Q10_HI = 438 + + Q11_HI = 439 + + Q12_HI = 440 + + Q13_HI = 441 + + Q14_HI = 442 + + Q15_HI = 443 + + Q16_HI = 444 + + Q17_HI = 445 + + Q18_HI = 446 + + Q19_HI = 447 + + Q20_HI = 448 + + Q21_HI = 449 + + Q22_HI = 450 + + Q23_HI = 451 + + Q24_HI = 452 + + Q25_HI = 453 + + Q26_HI = 454 + + Q27_HI = 455 + + Q28_HI = 456 + + Q29_HI = 457 + + Q30_HI = 458 + + Q31_HI = 459 + + S0_HI = 460 + + S1_HI = 461 + + S2_HI = 462 + + S3_HI = 463 + + S4_HI = 464 + + S5_HI = 465 + + S6_HI = 466 + + S7_HI = 467 + + S8_HI = 468 + + S9_HI = 469 + + S10_HI = 470 + + S11_HI = 471 + + S12_HI = 472 + + S13_HI = 473 + + S14_HI = 474 + + S15_HI = 475 + + S16_HI = 476 + + S17_HI = 477 + + S18_HI = 478 + + S19_HI = 479 + + S20_HI = 480 + + S21_HI = 481 + + S22_HI = 482 + + S23_HI = 483 + + S24_HI = 484 + + S25_HI = 485 + + S26_HI = 486 + + S27_HI = 487 + + S28_HI = 488 + + S29_HI = 489 + + S30_HI = 490 + + S31_HI = 491 + + W0_HI = 492 + + W1_HI = 493 + + W2_HI = 494 + + W3_HI = 495 + + W4_HI = 496 + + W5_HI = 497 + + W6_HI = 498 + + W7_HI = 499 + + W8_HI = 500 + + W9_HI = 501 + + W10_HI = 502 + + W11_HI = 503 + + W12_HI = 504 + + W13_HI = 505 + + W14_HI = 506 + + W15_HI = 507 + + W16_HI = 508 + + W17_HI = 509 + + W18_HI = 510 + + W19_HI = 511 + + W20_HI = 512 + + W21_HI = 513 + + W22_HI = 514 + + W23_HI = 515 + + W24_HI = 516 + + W25_HI = 517 + + W26_HI = 518 + + W27_HI = 519 + + W28_HI = 520 + + W29_HI = 521 + + W30_HI = 522 + + D0_D1 = 523 + + D1_D2 = 524 + + D2_D3 = 525 + + D3_D4 = 526 + + D4_D5 = 527 + + D5_D6 = 528 + + D6_D7 = 529 + + D7_D8 = 530 + + D8_D9 = 531 + + D9_D10 = 532 + + D10_D11 = 533 + + D11_D12 = 534 + + D12_D13 = 535 + + D13_D14 = 536 + + D14_D15 = 537 + + D15_D16 = 538 + + D16_D17 = 539 + + D17_D18 = 540 + + D18_D19 = 541 + + D19_D20 = 542 + + D20_D21 = 543 + + D21_D22 = 544 + + D22_D23 = 545 + + D23_D24 = 546 + + D24_D25 = 547 + + D25_D26 = 548 + + D26_D27 = 549 + + D27_D28 = 550 + + D28_D29 = 551 + + D29_D30 = 552 + + D30_D31 = 553 + + D31_D0 = 554 + + D0_D1_D2_D3 = 555 + + D1_D2_D3_D4 = 556 + + D2_D3_D4_D5 = 557 + + D3_D4_D5_D6 = 558 + + D4_D5_D6_D7 = 559 + + D5_D6_D7_D8 = 560 + + D6_D7_D8_D9 = 561 + + D7_D8_D9_D10 = 562 + + D8_D9_D10_D11 = 563 + + D9_D10_D11_D12 = 564 + + D10_D11_D12_D13 = 565 + + D11_D12_D13_D14 = 566 + + D12_D13_D14_D15 = 567 + + D13_D14_D15_D16 = 568 + + D14_D15_D16_D17 = 569 + + D15_D16_D17_D18 = 570 + + D16_D17_D18_D19 = 571 + + D17_D18_D19_D20 = 572 + + D18_D19_D20_D21 = 573 + + D19_D20_D21_D22 = 574 + + D20_D21_D22_D23 = 575 + + D21_D22_D23_D24 = 576 + + D22_D23_D24_D25 = 577 + + D23_D24_D25_D26 = 578 + + D24_D25_D26_D27 = 579 + + D25_D26_D27_D28 = 580 + + D26_D27_D28_D29 = 581 + + D27_D28_D29_D30 = 582 + + D28_D29_D30_D31 = 583 + + D29_D30_D31_D0 = 584 + + D30_D31_D0_D1 = 585 + + D31_D0_D1_D2 = 586 + + D0_D1_D2 = 587 + + D1_D2_D3 = 588 + + D2_D3_D4 = 589 + + D3_D4_D5 = 590 + + D4_D5_D6 = 591 + + D5_D6_D7 = 592 + + D6_D7_D8 = 593 + + D7_D8_D9 = 594 + + D8_D9_D10 = 595 + + D9_D10_D11 = 596 + + D10_D11_D12 = 597 + + D11_D12_D13 = 598 + + D12_D13_D14 = 599 + + D13_D14_D15 = 600 + + D14_D15_D16 = 601 + + D15_D16_D17 = 602 + + D16_D17_D18 = 603 + + D17_D18_D19 = 604 + + D18_D19_D20 = 605 + + D19_D20_D21 = 606 + + D20_D21_D22 = 607 + + D21_D22_D23 = 608 + + D22_D23_D24 = 609 + + D23_D24_D25 = 610 + + D24_D25_D26 = 611 + + D25_D26_D27 = 612 + + D26_D27_D28 = 613 + + D27_D28_D29 = 614 + + D28_D29_D30 = 615 + + D29_D30_D31 = 616 + + D30_D31_D0 = 617 + + D31_D0_D1 = 618 + + P0_P1 = 619 + + P1_P2 = 620 + + P2_P3 = 621 + + P3_P4 = 622 + + P4_P5 = 623 + + P5_P6 = 624 + + P6_P7 = 625 + + P7_P8 = 626 + + P8_P9 = 627 + + P9_P10 = 628 + + P10_P11 = 629 + + P11_P12 = 630 + + P12_P13 = 631 + + P13_P14 = 632 + + P14_P15 = 633 + + P15_P0 = 634 + + Q0_Q1 = 635 + + Q1_Q2 = 636 + + Q2_Q3 = 637 + + Q3_Q4 = 638 + + Q4_Q5 = 639 + + Q5_Q6 = 640 + + Q6_Q7 = 641 + + Q7_Q8 = 642 + + Q8_Q9 = 643 + + Q9_Q10 = 644 + + Q10_Q11 = 645 + + Q11_Q12 = 646 + + Q12_Q13 = 647 + + Q13_Q14 = 648 + + Q14_Q15 = 649 + + Q15_Q16 = 650 + + Q16_Q17 = 651 + + Q17_Q18 = 652 + + Q18_Q19 = 653 + + Q19_Q20 = 654 + + Q20_Q21 = 655 + + Q21_Q22 = 656 + + Q22_Q23 = 657 + + Q23_Q24 = 658 + + Q24_Q25 = 659 + + Q25_Q26 = 660 + + Q26_Q27 = 661 + + Q27_Q28 = 662 + + Q28_Q29 = 663 + + Q29_Q30 = 664 + + Q30_Q31 = 665 + + Q31_Q0 = 666 + + Q0_Q1_Q2_Q3 = 667 + + Q1_Q2_Q3_Q4 = 668 + + Q2_Q3_Q4_Q5 = 669 + + Q3_Q4_Q5_Q6 = 670 + + Q4_Q5_Q6_Q7 = 671 + + Q5_Q6_Q7_Q8 = 672 + + Q6_Q7_Q8_Q9 = 673 + + Q7_Q8_Q9_Q10 = 674 + + Q8_Q9_Q10_Q11 = 675 + + Q9_Q10_Q11_Q12 = 676 + + Q10_Q11_Q12_Q13 = 677 + + Q11_Q12_Q13_Q14 = 678 + + Q12_Q13_Q14_Q15 = 679 + + Q13_Q14_Q15_Q16 = 680 + + Q14_Q15_Q16_Q17 = 681 + + Q15_Q16_Q17_Q18 = 682 + + Q16_Q17_Q18_Q19 = 683 + + Q17_Q18_Q19_Q20 = 684 + + Q18_Q19_Q20_Q21 = 685 + + Q19_Q20_Q21_Q22 = 686 + + Q20_Q21_Q22_Q23 = 687 + + Q21_Q22_Q23_Q24 = 688 + + Q22_Q23_Q24_Q25 = 689 + + Q23_Q24_Q25_Q26 = 690 + + Q24_Q25_Q26_Q27 = 691 + + Q25_Q26_Q27_Q28 = 692 + + Q26_Q27_Q28_Q29 = 693 + + Q27_Q28_Q29_Q30 = 694 + + Q28_Q29_Q30_Q31 = 695 + + Q29_Q30_Q31_Q0 = 696 + + Q30_Q31_Q0_Q1 = 697 + + Q31_Q0_Q1_Q2 = 698 + + Q0_Q1_Q2 = 699 + + Q1_Q2_Q3 = 700 + + Q2_Q3_Q4 = 701 + + Q3_Q4_Q5 = 702 + + Q4_Q5_Q6 = 703 + + Q5_Q6_Q7 = 704 + + Q6_Q7_Q8 = 705 + + Q7_Q8_Q9 = 706 + + Q8_Q9_Q10 = 707 + + Q9_Q10_Q11 = 708 + + Q10_Q11_Q12 = 709 + + Q11_Q12_Q13 = 710 + + Q12_Q13_Q14 = 711 + + Q13_Q14_Q15 = 712 + + Q14_Q15_Q16 = 713 + + Q15_Q16_Q17 = 714 + + Q16_Q17_Q18 = 715 + + Q17_Q18_Q19 = 716 + + Q18_Q19_Q20 = 717 + + Q19_Q20_Q21 = 718 + + Q20_Q21_Q22 = 719 + + Q21_Q22_Q23 = 720 + + Q22_Q23_Q24 = 721 + + Q23_Q24_Q25 = 722 + + Q24_Q25_Q26 = 723 + + Q25_Q26_Q27 = 724 + + Q26_Q27_Q28 = 725 + + Q27_Q28_Q29 = 726 + + Q28_Q29_Q30 = 727 + + Q29_Q30_Q31 = 728 + + Q30_Q31_Q0 = 729 + + Q31_Q0_Q1 = 730 + + X22_X23_X24_X25_X26_X27_X28_FP = 731 + + X0_X1_X2_X3_X4_X5_X6_X7 = 732 + + X2_X3_X4_X5_X6_X7_X8_X9 = 733 + + X4_X5_X6_X7_X8_X9_X10_X11 = 734 + + X6_X7_X8_X9_X10_X11_X12_X13 = 735 + + X8_X9_X10_X11_X12_X13_X14_X15 = 736 + + X10_X11_X12_X13_X14_X15_X16_X17 = 737 + + X12_X13_X14_X15_X16_X17_X18_X19 = 738 + + X14_X15_X16_X17_X18_X19_X20_X21 = 739 + + X16_X17_X18_X19_X20_X21_X22_X23 = 740 + + X18_X19_X20_X21_X22_X23_X24_X25 = 741 + + X20_X21_X22_X23_X24_X25_X26_X27 = 742 + + W30_WZR = 743 + + W0_W1 = 744 + + W2_W3 = 745 + + W4_W5 = 746 + + W6_W7 = 747 + + W8_W9 = 748 + + W10_W11 = 749 + + W12_W13 = 750 + + W14_W15 = 751 + + W16_W17 = 752 + + W18_W19 = 753 + + W20_W21 = 754 + + W22_W23 = 755 + + W24_W25 = 756 + + W26_W27 = 757 + + W28_W29 = 758 + + LR_XZR = 759 + + X28_FP = 760 + + X0_X1 = 761 + + X2_X3 = 762 + + X4_X5 = 763 + + X6_X7 = 764 + + X8_X9 = 765 + + X10_X11 = 766 + + X12_X13 = 767 + + X14_X15 = 768 + + X16_X17 = 769 + + X18_X19 = 770 + + X20_X21 = 771 + + X22_X23 = 772 + + X24_X25 = 773 + + X26_X27 = 774 + + Z0_Z1 = 775 + + Z1_Z2 = 776 + + Z2_Z3 = 777 + + Z3_Z4 = 778 + + Z4_Z5 = 779 + + Z5_Z6 = 780 + + Z6_Z7 = 781 + + Z7_Z8 = 782 + + Z8_Z9 = 783 + + Z9_Z10 = 784 + + Z10_Z11 = 785 + + Z11_Z12 = 786 + + Z12_Z13 = 787 + + Z13_Z14 = 788 + + Z14_Z15 = 789 + + Z15_Z16 = 790 + + Z16_Z17 = 791 + + Z17_Z18 = 792 + + Z18_Z19 = 793 + + Z19_Z20 = 794 + + Z20_Z21 = 795 + + Z21_Z22 = 796 + + Z22_Z23 = 797 + + Z23_Z24 = 798 + + Z24_Z25 = 799 + + Z25_Z26 = 800 + + Z26_Z27 = 801 + + Z27_Z28 = 802 + + Z28_Z29 = 803 + + Z29_Z30 = 804 + + Z30_Z31 = 805 + + Z31_Z0 = 806 + + Z0_Z1_Z2_Z3 = 807 + + Z1_Z2_Z3_Z4 = 808 + + Z2_Z3_Z4_Z5 = 809 + + Z3_Z4_Z5_Z6 = 810 + + Z4_Z5_Z6_Z7 = 811 + + Z5_Z6_Z7_Z8 = 812 + + Z6_Z7_Z8_Z9 = 813 + + Z7_Z8_Z9_Z10 = 814 + + Z8_Z9_Z10_Z11 = 815 + + Z9_Z10_Z11_Z12 = 816 + + Z10_Z11_Z12_Z13 = 817 + + Z11_Z12_Z13_Z14 = 818 + + Z12_Z13_Z14_Z15 = 819 + + Z13_Z14_Z15_Z16 = 820 + + Z14_Z15_Z16_Z17 = 821 + + Z15_Z16_Z17_Z18 = 822 + + Z16_Z17_Z18_Z19 = 823 + + Z17_Z18_Z19_Z20 = 824 + + Z18_Z19_Z20_Z21 = 825 + + Z19_Z20_Z21_Z22 = 826 + + Z20_Z21_Z22_Z23 = 827 + + Z21_Z22_Z23_Z24 = 828 + + Z22_Z23_Z24_Z25 = 829 + + Z23_Z24_Z25_Z26 = 830 + + Z24_Z25_Z26_Z27 = 831 + + Z25_Z26_Z27_Z28 = 832 + + Z26_Z27_Z28_Z29 = 833 + + Z27_Z28_Z29_Z30 = 834 + + Z28_Z29_Z30_Z31 = 835 + + Z29_Z30_Z31_Z0 = 836 + + Z30_Z31_Z0_Z1 = 837 + + Z31_Z0_Z1_Z2 = 838 + + Z0_Z1_Z2 = 839 + + Z1_Z2_Z3 = 840 + + Z2_Z3_Z4 = 841 + + Z3_Z4_Z5 = 842 + + Z4_Z5_Z6 = 843 + + Z5_Z6_Z7 = 844 + + Z6_Z7_Z8 = 845 + + Z7_Z8_Z9 = 846 + + Z8_Z9_Z10 = 847 + + Z9_Z10_Z11 = 848 + + Z10_Z11_Z12 = 849 + + Z11_Z12_Z13 = 850 + + Z12_Z13_Z14 = 851 + + Z13_Z14_Z15 = 852 + + Z14_Z15_Z16 = 853 + + Z15_Z16_Z17 = 854 + + Z16_Z17_Z18 = 855 + + Z17_Z18_Z19 = 856 + + Z18_Z19_Z20 = 857 + + Z19_Z20_Z21 = 858 + + Z20_Z21_Z22 = 859 + + Z21_Z22_Z23 = 860 + + Z22_Z23_Z24 = 861 + + Z23_Z24_Z25 = 862 + + Z24_Z25_Z26 = 863 + + Z25_Z26_Z27 = 864 + + Z26_Z27_Z28 = 865 + + Z27_Z28_Z29 = 866 + + Z28_Z29_Z30 = 867 + + Z29_Z30_Z31 = 868 + + Z30_Z31_Z0 = 869 + + Z31_Z0_Z1 = 870 + + Z16_Z24 = 871 + + Z17_Z25 = 872 + + Z18_Z26 = 873 + + Z19_Z27 = 874 + + Z20_Z28 = 875 + + Z21_Z29 = 876 + + Z22_Z30 = 877 + + Z23_Z31 = 878 + + Z0_Z8 = 879 + + Z1_Z9 = 880 + + Z2_Z10 = 881 + + Z3_Z11 = 882 + + Z4_Z12 = 883 + + Z5_Z13 = 884 + + Z6_Z14 = 885 + + Z7_Z15 = 886 + + Z16_Z20_Z24_Z28 = 887 + + Z17_Z21_Z25_Z29 = 888 + + Z18_Z22_Z26_Z30 = 889 + + Z19_Z23_Z27_Z31 = 890 + + Z0_Z4_Z8_Z12 = 891 + + Z1_Z5_Z9_Z13 = 892 + + Z2_Z6_Z10_Z14 = 893 + + Z3_Z7_Z11_Z15 = 894 + + NUM_TARGET_REGS = 895 + +class SYSREG(enum.Enum): + OSDTRRX_EL1 = 32770 + + DBGBVR0_EL1 = 32772 + + DBGBCR0_EL1 = 32773 + + DBGWVR0_EL1 = 32774 + + DBGWCR0_EL1 = 32775 + + DBGBVR1_EL1 = 32780 + + DBGBCR1_EL1 = 32781 + + DBGWVR1_EL1 = 32782 + + DBGWCR1_EL1 = 32783 + + MDCCINT_EL1 = 32784 + + MDSCR_EL1 = 32786 + + DBGBVR2_EL1 = 32788 + + DBGBCR2_EL1 = 32789 + + DBGWVR2_EL1 = 32790 + + DBGWCR2_EL1 = 32791 + + OSDTRTX_EL1 = 32794 + + DBGBVR3_EL1 = 32796 + + DBGBCR3_EL1 = 32797 + + DBGWVR3_EL1 = 32798 + + DBGWCR3_EL1 = 32799 + + MDSELR_EL1 = 32802 + + DBGBVR4_EL1 = 32804 + + DBGBCR4_EL1 = 32805 + + DBGWVR4_EL1 = 32806 + + DBGWCR4_EL1 = 32807 + + MDSTEPOP_EL1 = 32810 + + DBGBVR5_EL1 = 32812 + + DBGBCR5_EL1 = 32813 + + DBGWVR5_EL1 = 32814 + + DBGWCR5_EL1 = 32815 + + OSECCR_EL1 = 32818 + + DBGBVR6_EL1 = 32820 + + DBGBCR6_EL1 = 32821 + + DBGWVR6_EL1 = 32822 + + DBGWCR6_EL1 = 32823 + + DBGBVR7_EL1 = 32828 + + DBGBCR7_EL1 = 32829 + + DBGWVR7_EL1 = 32830 + + DBGWCR7_EL1 = 32831 + + DBGBVR8_EL1 = 32836 + + DBGBCR8_EL1 = 32837 + + DBGWVR8_EL1 = 32838 + + DBGWCR8_EL1 = 32839 + + DBGBVR9_EL1 = 32844 + + DBGBCR9_EL1 = 32845 + + DBGWVR9_EL1 = 32846 + + DBGWCR9_EL1 = 32847 + + DBGBVR10_EL1 = 32852 + + DBGBCR10_EL1 = 32853 + + DBGWVR10_EL1 = 32854 + + DBGWCR10_EL1 = 32855 + + DBGBVR11_EL1 = 32860 + + DBGBCR11_EL1 = 32861 + + DBGWVR11_EL1 = 32862 + + DBGWCR11_EL1 = 32863 + + DBGBVR12_EL1 = 32868 + + DBGBCR12_EL1 = 32869 + + DBGWVR12_EL1 = 32870 + + DBGWCR12_EL1 = 32871 + + DBGBVR13_EL1 = 32876 + + DBGBCR13_EL1 = 32877 + + DBGWVR13_EL1 = 32878 + + DBGWCR13_EL1 = 32879 + + DBGBVR14_EL1 = 32884 + + DBGBCR14_EL1 = 32885 + + DBGWVR14_EL1 = 32886 + + DBGWCR14_EL1 = 32887 + + DBGBVR15_EL1 = 32892 + + DBGBCR15_EL1 = 32893 + + DBGWVR15_EL1 = 32894 + + DBGWCR15_EL1 = 32895 + + MDRAR_EL1 = 32896 + + OSLAR_EL1 = 32900 + + OSLSR_EL1 = 32908 + + OSDLR_EL1 = 32924 + + DBGPRCR_EL1 = 32932 + + DBGCLAIMSET_EL1 = 33734 + + DBGCLAIMCLR_EL1 = 33742 + + DBGAUTHSTATUS_EL1 = 33782 + + SPMCGCR0_EL1 = 34024 + + SPMCGCR1_EL1 = 34025 + + SPMACCESSR_EL1 = 34027 + + SPMIIDR_EL1 = 34028 + + SPMDEVARCH_EL1 = 34029 + + SPMDEVAFF_EL1 = 34030 + + SPMCFGR_EL1 = 34031 + + SPMINTENSET_EL1 = 34033 + + SPMINTENCLR_EL1 = 34034 + + PMEVCNTSVR0_EL1 = 34624 + + PMEVCNTSVR1_EL1 = 34625 + + PMEVCNTSVR2_EL1 = 34626 + + PMEVCNTSVR3_EL1 = 34627 + + PMEVCNTSVR4_EL1 = 34628 + + PMEVCNTSVR5_EL1 = 34629 + + PMEVCNTSVR6_EL1 = 34630 + + PMEVCNTSVR7_EL1 = 34631 + + PMEVCNTSVR8_EL1 = 34632 + + PMEVCNTSVR9_EL1 = 34633 + + PMEVCNTSVR10_EL1 = 34634 + + PMEVCNTSVR11_EL1 = 34635 + + PMEVCNTSVR12_EL1 = 34636 + + PMEVCNTSVR13_EL1 = 34637 + + PMEVCNTSVR14_EL1 = 34638 + + PMEVCNTSVR15_EL1 = 34639 + + PMEVCNTSVR16_EL1 = 34640 + + PMEVCNTSVR17_EL1 = 34641 + + PMEVCNTSVR18_EL1 = 34642 + + PMEVCNTSVR19_EL1 = 34643 + + PMEVCNTSVR20_EL1 = 34644 + + PMEVCNTSVR21_EL1 = 34645 + + PMEVCNTSVR22_EL1 = 34646 + + PMEVCNTSVR23_EL1 = 34647 + + PMEVCNTSVR24_EL1 = 34648 + + PMEVCNTSVR25_EL1 = 34649 + + PMEVCNTSVR26_EL1 = 34650 + + PMEVCNTSVR27_EL1 = 34651 + + PMEVCNTSVR28_EL1 = 34652 + + PMEVCNTSVR29_EL1 = 34653 + + PMEVCNTSVR30_EL1 = 34654 + + PMCCNTSVR_EL1 = 34655 + + PMICNTSVR_EL1 = 34656 + + TRCTRACEIDR = 34817 + + TRCVICTLR = 34818 + + TRCSEQEVR0 = 34820 + + TRCCNTRLDVR0 = 34821 + + TRCIDR8 = 34822 + + TRCIMSPEC0 = 34823 + + TRCPRGCTLR = 34824 + + TRCQCTLR = 34825 + + TRCVIIECTLR = 34826 + + TRCSEQEVR1 = 34828 + + TRCCNTRLDVR1 = 34829 + + TRCIDR9 = 34830 + + TRCIMSPEC1 = 34831 + + TRCPROCSELR = 34832 + + TRCITEEDCR = 34833 + + TRCVISSCTLR = 34834 + + TRCSEQEVR2 = 34836 + + TRCCNTRLDVR2 = 34837 + + TRCIDR10 = 34838 + + TRCIMSPEC2 = 34839 + + TRCSTATR = 34840 + + TRCVIPCSSCTLR = 34842 + + TRCCNTRLDVR3 = 34845 + + TRCIDR11 = 34846 + + TRCIMSPEC3 = 34847 + + TRCCONFIGR = 34848 + + TRCCNTCTLR0 = 34853 + + TRCIDR12 = 34854 + + TRCIMSPEC4 = 34855 + + TRCCNTCTLR1 = 34861 + + TRCIDR13 = 34862 + + TRCIMSPEC5 = 34863 + + TRCAUXCTLR = 34864 + + TRCSEQRSTEVR = 34868 + + TRCCNTCTLR2 = 34869 + + TRCIMSPEC6 = 34871 + + TRCSEQSTR = 34876 + + TRCCNTCTLR3 = 34877 + + TRCIMSPEC7 = 34879 + + TRCEVENTCTL0R = 34880 + + TRCVDCTLR = 34882 + + TRCEXTINSELR = 34884 + + TRCCNTVR0 = 34885 + + TRCIDR0 = 34887 + + TRCEVENTCTL1R = 34888 + + TRCVDSACCTLR = 34890 + + TRCEXTINSELR1 = 34892 + + TRCCNTVR1 = 34893 + + TRCIDR1 = 34895 + + TRCRSR = 34896 + + TRCVDARCCTLR = 34898 + + TRCEXTINSELR2 = 34900 + + TRCCNTVR2 = 34901 + + TRCIDR2 = 34903 + + TRCSTALLCTLR = 34904 + + TRCEXTINSELR3 = 34908 + + TRCCNTVR3 = 34909 + + TRCIDR3 = 34911 + + TRCTSCTLR = 34912 + + TRCIDR4 = 34919 + + TRCSYNCPR = 34920 + + TRCIDR5 = 34927 + + TRCCCCTLR = 34928 + + TRCIDR6 = 34935 + + TRCBBCTLR = 34936 + + TRCIDR7 = 34943 + + TRCRSCTLR16 = 34945 + + TRCSSCCR0 = 34946 + + TRCSSPCICR0 = 34947 + + TRCOSLAR = 34948 + + TRCRSCTLR17 = 34953 + + TRCSSCCR1 = 34954 + + TRCSSPCICR1 = 34955 + + TRCOSLSR = 34956 + + TRCRSCTLR2 = 34960 + + TRCRSCTLR18 = 34961 + + TRCSSCCR2 = 34962 + + TRCSSPCICR2 = 34963 + + TRCRSCTLR3 = 34968 + + TRCRSCTLR19 = 34969 + + TRCSSCCR3 = 34970 + + TRCSSPCICR3 = 34971 + + TRCRSCTLR4 = 34976 + + TRCRSCTLR20 = 34977 + + TRCSSCCR4 = 34978 + + TRCSSPCICR4 = 34979 + + TRCPDCR = 34980 + + TRCRSCTLR5 = 34984 + + TRCRSCTLR21 = 34985 + + TRCSSCCR5 = 34986 + + TRCSSPCICR5 = 34987 + + TRCPDSR = 34988 + + TRCRSCTLR6 = 34992 + + TRCRSCTLR22 = 34993 + + TRCSSCCR6 = 34994 + + TRCSSPCICR6 = 34995 + + TRCRSCTLR7 = 35000 + + TRCRSCTLR23 = 35001 + + TRCSSCCR7 = 35002 + + TRCSSPCICR7 = 35003 + + TRCRSCTLR8 = 35008 + + TRCRSCTLR24 = 35009 + + TRCSSCSR0 = 35010 + + TRCRSCTLR9 = 35016 + + TRCRSCTLR25 = 35017 + + TRCSSCSR1 = 35018 + + TRCRSCTLR10 = 35024 + + TRCRSCTLR26 = 35025 + + TRCSSCSR2 = 35026 + + TRCRSCTLR11 = 35032 + + TRCRSCTLR27 = 35033 + + TRCSSCSR3 = 35034 + + TRCRSCTLR12 = 35040 + + TRCRSCTLR28 = 35041 + + TRCSSCSR4 = 35042 + + TRCRSCTLR13 = 35048 + + TRCRSCTLR29 = 35049 + + TRCSSCSR5 = 35050 + + TRCRSCTLR14 = 35056 + + TRCRSCTLR30 = 35057 + + TRCSSCSR6 = 35058 + + TRCRSCTLR15 = 35064 + + TRCRSCTLR31 = 35065 + + TRCSSCSR7 = 35066 + + TRCACVR0 = 35072 + + TRCACVR8 = 35073 + + TRCACATR0 = 35074 + + TRCACATR8 = 35075 + + TRCDVCVR0 = 35076 + + TRCDVCVR4 = 35077 + + TRCDVCMR0 = 35078 + + TRCDVCMR4 = 35079 + + TRCACVR1 = 35088 + + TRCACVR9 = 35089 + + TRCACATR1 = 35090 + + TRCACATR9 = 35091 + + TRCACVR2 = 35104 + + TRCACVR10 = 35105 + + TRCACATR2 = 35106 + + TRCACATR10 = 35107 + + TRCDVCVR1 = 35108 + + TRCDVCVR5 = 35109 + + TRCDVCMR1 = 35110 + + TRCDVCMR5 = 35111 + + TRCACVR3 = 35120 + + TRCACVR11 = 35121 + + TRCACATR3 = 35122 + + TRCACATR11 = 35123 + + TRCACVR4 = 35136 + + TRCACVR12 = 35137 + + TRCACATR4 = 35138 + + TRCACATR12 = 35139 + + TRCDVCVR2 = 35140 + + TRCDVCVR6 = 35141 + + TRCDVCMR2 = 35142 + + TRCDVCMR6 = 35143 + + TRCACVR5 = 35152 + + TRCACVR13 = 35153 + + TRCACATR5 = 35154 + + TRCACATR13 = 35155 + + TRCACVR6 = 35168 + + TRCACVR14 = 35169 + + TRCACATR6 = 35170 + + TRCACATR14 = 35171 + + TRCDVCVR3 = 35172 + + TRCDVCVR7 = 35173 + + TRCDVCMR3 = 35174 + + TRCDVCMR7 = 35175 + + TRCACVR7 = 35184 + + TRCACVR15 = 35185 + + TRCACATR7 = 35186 + + TRCACATR15 = 35187 + + TRCCIDCVR0 = 35200 + + TRCVMIDCVR0 = 35201 + + TRCCIDCCTLR0 = 35202 + + TRCCIDCCTLR1 = 35210 + + TRCCIDCVR1 = 35216 + + TRCVMIDCVR1 = 35217 + + TRCVMIDCCTLR0 = 35218 + + TRCVMIDCCTLR1 = 35226 + + TRCCIDCVR2 = 35232 + + TRCVMIDCVR2 = 35233 + + TRCCIDCVR3 = 35248 + + TRCVMIDCVR3 = 35249 + + TRCCIDCVR4 = 35264 + + TRCVMIDCVR4 = 35265 + + TRCCIDCVR5 = 35280 + + TRCVMIDCVR5 = 35281 + + TRCCIDCVR6 = 35296 + + TRCVMIDCVR6 = 35297 + + TRCCIDCVR7 = 35312 + + TRCVMIDCVR7 = 35313 + + TRCITCTRL = 35716 + + TRCDEVID = 35735 + + TRCDEVTYPE = 35743 + + TRCPIDR4 = 35751 + + TRCPIDR5 = 35759 + + TRCPIDR6 = 35767 + + TRCPIDR7 = 35775 + + TRCCLAIMSET = 35782 + + TRCPIDR0 = 35783 + + TRCCLAIMCLR = 35790 + + TRCPIDR1 = 35791 + + TRCDEVAFF0 = 35798 + + TRCPIDR2 = 35799 + + TRCDEVAFF1 = 35806 + + TRCPIDR3 = 35807 + + TRCLAR = 35814 + + TRCCIDR0 = 35815 + + TRCLSR = 35822 + + TRCCIDR1 = 35823 + + TRCAUTHSTATUS = 35830 + + TRCCIDR2 = 35831 + + TRCDEVARCH = 35838 + + TRCCIDR3 = 35839 + + BRBINF0_EL1 = 35840 + + BRBSRC0_EL1 = 35841 + + BRBTGT0_EL1 = 35842 + + BRBINF16_EL1 = 35844 + + BRBSRC16_EL1 = 35845 + + BRBTGT16_EL1 = 35846 + + BRBINF1_EL1 = 35848 + + BRBSRC1_EL1 = 35849 + + BRBTGT1_EL1 = 35850 + + BRBINF17_EL1 = 35852 + + BRBSRC17_EL1 = 35853 + + BRBTGT17_EL1 = 35854 + + BRBINF2_EL1 = 35856 + + BRBSRC2_EL1 = 35857 + + BRBTGT2_EL1 = 35858 + + BRBINF18_EL1 = 35860 + + BRBSRC18_EL1 = 35861 + + BRBTGT18_EL1 = 35862 + + BRBINF3_EL1 = 35864 + + BRBSRC3_EL1 = 35865 + + BRBTGT3_EL1 = 35866 + + BRBINF19_EL1 = 35868 + + BRBSRC19_EL1 = 35869 + + BRBTGT19_EL1 = 35870 + + BRBINF4_EL1 = 35872 + + BRBSRC4_EL1 = 35873 + + BRBTGT4_EL1 = 35874 + + BRBINF20_EL1 = 35876 + + BRBSRC20_EL1 = 35877 + + BRBTGT20_EL1 = 35878 + + BRBINF5_EL1 = 35880 + + BRBSRC5_EL1 = 35881 + + BRBTGT5_EL1 = 35882 + + BRBINF21_EL1 = 35884 + + BRBSRC21_EL1 = 35885 + + BRBTGT21_EL1 = 35886 + + BRBINF6_EL1 = 35888 + + BRBSRC6_EL1 = 35889 + + BRBTGT6_EL1 = 35890 + + BRBINF22_EL1 = 35892 + + BRBSRC22_EL1 = 35893 + + BRBTGT22_EL1 = 35894 + + BRBINF7_EL1 = 35896 + + BRBSRC7_EL1 = 35897 + + BRBTGT7_EL1 = 35898 + + BRBINF23_EL1 = 35900 + + BRBSRC23_EL1 = 35901 + + BRBTGT23_EL1 = 35902 + + BRBINF8_EL1 = 35904 + + BRBSRC8_EL1 = 35905 + + BRBTGT8_EL1 = 35906 + + BRBINF24_EL1 = 35908 + + BRBSRC24_EL1 = 35909 + + BRBTGT24_EL1 = 35910 + + BRBINF9_EL1 = 35912 + + BRBSRC9_EL1 = 35913 + + BRBTGT9_EL1 = 35914 + + BRBINF25_EL1 = 35916 + + BRBSRC25_EL1 = 35917 + + BRBTGT25_EL1 = 35918 + + BRBINF10_EL1 = 35920 + + BRBSRC10_EL1 = 35921 + + BRBTGT10_EL1 = 35922 + + BRBINF26_EL1 = 35924 + + BRBSRC26_EL1 = 35925 + + BRBTGT26_EL1 = 35926 + + BRBINF11_EL1 = 35928 + + BRBSRC11_EL1 = 35929 + + BRBTGT11_EL1 = 35930 + + BRBINF27_EL1 = 35932 + + BRBSRC27_EL1 = 35933 + + BRBTGT27_EL1 = 35934 + + BRBINF12_EL1 = 35936 + + BRBSRC12_EL1 = 35937 + + BRBTGT12_EL1 = 35938 + + BRBINF28_EL1 = 35940 + + BRBSRC28_EL1 = 35941 + + BRBTGT28_EL1 = 35942 + + BRBINF13_EL1 = 35944 + + BRBSRC13_EL1 = 35945 + + BRBTGT13_EL1 = 35946 + + BRBINF29_EL1 = 35948 + + BRBSRC29_EL1 = 35949 + + BRBTGT29_EL1 = 35950 + + BRBINF14_EL1 = 35952 + + BRBSRC14_EL1 = 35953 + + BRBTGT14_EL1 = 35954 + + BRBINF30_EL1 = 35956 + + BRBSRC30_EL1 = 35957 + + BRBTGT30_EL1 = 35958 + + BRBINF15_EL1 = 35960 + + BRBSRC15_EL1 = 35961 + + BRBTGT15_EL1 = 35962 + + BRBINF31_EL1 = 35964 + + BRBSRC31_EL1 = 35965 + + BRBTGT31_EL1 = 35966 + + BRBCR_EL1 = 35968 + + BRBFCR_EL1 = 35969 + + BRBTS_EL1 = 35970 + + BRBINFINJ_EL1 = 35976 + + BRBSRCINJ_EL1 = 35977 + + BRBTGTINJ_EL1 = 35978 + + BRBIDR0_EL1 = 35984 + + TEECR32_EL1 = 36864 + + TEEHBR32_EL1 = 36992 + + MDCCSR_EL0 = 38920 + + DBGDTR_EL0 = 38944 + + DBGDTRRX_EL0 = 38952 + + SPMCR_EL0 = 40160 + + SPMCNTENSET_EL0 = 40161 + + SPMCNTENCLR_EL0 = 40162 + + SPMOVSCLR_EL0 = 40163 + + SPMZR_EL0 = 40164 + + SPMSELR_EL0 = 40165 + + SPMOVSSET_EL0 = 40179 + + SPMEVCNTR0_EL0 = 40704 + + SPMEVCNTR1_EL0 = 40705 + + SPMEVCNTR2_EL0 = 40706 + + SPMEVCNTR3_EL0 = 40707 + + SPMEVCNTR4_EL0 = 40708 + + SPMEVCNTR5_EL0 = 40709 + + SPMEVCNTR6_EL0 = 40710 + + SPMEVCNTR7_EL0 = 40711 + + SPMEVCNTR8_EL0 = 40712 + + SPMEVCNTR9_EL0 = 40713 + + SPMEVCNTR10_EL0 = 40714 + + SPMEVCNTR11_EL0 = 40715 + + SPMEVCNTR12_EL0 = 40716 + + SPMEVCNTR13_EL0 = 40717 + + SPMEVCNTR14_EL0 = 40718 + + SPMEVCNTR15_EL0 = 40719 + + SPMEVTYPER0_EL0 = 40720 + + SPMEVTYPER1_EL0 = 40721 + + SPMEVTYPER2_EL0 = 40722 + + SPMEVTYPER3_EL0 = 40723 + + SPMEVTYPER4_EL0 = 40724 + + SPMEVTYPER5_EL0 = 40725 + + SPMEVTYPER6_EL0 = 40726 + + SPMEVTYPER7_EL0 = 40727 + + SPMEVTYPER8_EL0 = 40728 + + SPMEVTYPER9_EL0 = 40729 + + SPMEVTYPER10_EL0 = 40730 + + SPMEVTYPER11_EL0 = 40731 + + SPMEVTYPER12_EL0 = 40732 + + SPMEVTYPER13_EL0 = 40733 + + SPMEVTYPER14_EL0 = 40734 + + SPMEVTYPER15_EL0 = 40735 + + SPMEVFILTR0_EL0 = 40736 + + SPMEVFILTR1_EL0 = 40737 + + SPMEVFILTR2_EL0 = 40738 + + SPMEVFILTR3_EL0 = 40739 + + SPMEVFILTR4_EL0 = 40740 + + SPMEVFILTR5_EL0 = 40741 + + SPMEVFILTR6_EL0 = 40742 + + SPMEVFILTR7_EL0 = 40743 + + SPMEVFILTR8_EL0 = 40744 + + SPMEVFILTR9_EL0 = 40745 + + SPMEVFILTR10_EL0 = 40746 + + SPMEVFILTR11_EL0 = 40747 + + SPMEVFILTR12_EL0 = 40748 + + SPMEVFILTR13_EL0 = 40749 + + SPMEVFILTR14_EL0 = 40750 + + SPMEVFILTR15_EL0 = 40751 + + SPMEVFILT2R0_EL0 = 40752 + + SPMEVFILT2R1_EL0 = 40753 + + SPMEVFILT2R2_EL0 = 40754 + + SPMEVFILT2R3_EL0 = 40755 + + SPMEVFILT2R4_EL0 = 40756 + + SPMEVFILT2R5_EL0 = 40757 + + SPMEVFILT2R6_EL0 = 40758 + + SPMEVFILT2R7_EL0 = 40759 + + SPMEVFILT2R8_EL0 = 40760 + + SPMEVFILT2R9_EL0 = 40761 + + SPMEVFILT2R10_EL0 = 40762 + + SPMEVFILT2R11_EL0 = 40763 + + SPMEVFILT2R12_EL0 = 40764 + + SPMEVFILT2R13_EL0 = 40765 + + SPMEVFILT2R14_EL0 = 40766 + + SPMEVFILT2R15_EL0 = 40767 + + DBGVCR32_EL2 = 41016 + + BRBCR_EL2 = 42112 + + SPMACCESSR_EL2 = 42219 + + BRBCR_EL12 = 44160 + + SPMACCESSR_EL12 = 44267 + + SPMACCESSR_EL3 = 46315 + + SPMROOTCR_EL3 = 46327 + + SPMSCR_EL1 = 48375 + + MIDR_EL1 = 49152 + + MPUIR_EL1 = 49156 + + MPIDR_EL1 = 49157 + + REVIDR_EL1 = 49158 + + ID_PFR0_EL1 = 49160 + + ID_PFR1_EL1 = 49161 + + ID_DFR0_EL1 = 49162 + + ID_AFR0_EL1 = 49163 + + ID_MMFR0_EL1 = 49164 + + ID_MMFR1_EL1 = 49165 + + ID_MMFR2_EL1 = 49166 + + ID_MMFR3_EL1 = 49167 + + ID_ISAR0_EL1 = 49168 + + ID_ISAR1_EL1 = 49169 + + ID_ISAR2_EL1 = 49170 + + ID_ISAR3_EL1 = 49171 + + ID_ISAR4_EL1 = 49172 + + ID_ISAR5_EL1 = 49173 + + ID_MMFR4_EL1 = 49174 + + ID_ISAR6_EL1 = 49175 + + MVFR0_EL1 = 49176 + + MVFR1_EL1 = 49177 + + MVFR2_EL1 = 49178 + + ID_PFR2_EL1 = 49180 + + ID_DFR1_EL1 = 49181 + + ID_MMFR5_EL1 = 49182 + + ID_AA64PFR0_EL1 = 49184 + + ID_AA64PFR1_EL1 = 49185 + + ID_AA64PFR2_EL1 = 49186 + + ID_AA64ZFR0_EL1 = 49188 + + ID_AA64SMFR0_EL1 = 49189 + + ID_AA64FPFR0_EL1 = 49191 + + ID_AA64DFR0_EL1 = 49192 + + ID_AA64DFR1_EL1 = 49193 + + ID_AA64DFR2_EL1 = 49194 + + ID_AA64AFR0_EL1 = 49196 + + ID_AA64AFR1_EL1 = 49197 + + ID_AA64ISAR0_EL1 = 49200 + + ID_AA64ISAR1_EL1 = 49201 + + ID_AA64ISAR2_EL1 = 49202 + + ID_AA64ISAR3_EL1 = 49203 + + ID_AA64MMFR0_EL1 = 49208 + + ID_AA64MMFR1_EL1 = 49209 + + ID_AA64MMFR2_EL1 = 49210 + + ID_AA64MMFR3_EL1 = 49211 + + ID_AA64MMFR4_EL1 = 49212 + + SCTLR_EL1 = 49280 + + ACTLR_EL1 = 49281 + + CPACR_EL1 = 49282 + + SCTLR2_EL1 = 49283 + + RGSR_EL1 = 49285 + + GCR_EL1 = 49286 + + ZCR_EL1 = 49296 + + TRFCR_EL1 = 49297 + + TRCITECR_EL1 = 49299 + + SMPRI_EL1 = 49300 + + SMCR_EL1 = 49302 + + SCTLRMASK_EL1 = 49312 + + ACTLRMASK_EL1 = 49313 + + CPACRMASK_EL1 = 49314 + + SCTLR2MASK_EL1 = 49315 + + CPACRALIAS_EL1 = 49316 + + ACTLRALIAS_EL1 = 49317 + + SCTLRALIAS_EL1 = 49318 + + SCTLR2ALIAS_EL1 = 49319 + + TTBR0_EL1 = 49408 + + TTBR1_EL1 = 49409 + + TCR_EL1 = 49410 + + TCR2_EL1 = 49411 + + IRTBRU_EL1 = 49412 + + IRTBRP_EL1 = 49413 + + DPOTBR0_EL1 = 49414 + + DPOTBR1_EL1 = 49415 + + APIAKeyLo_EL1 = 49416 + + APIAKeyHi_EL1 = 49417 + + APIBKeyLo_EL1 = 49418 + + APIBKeyHi_EL1 = 49419 + + LDSTT_EL1 = 49423 + + APDAKeyLo_EL1 = 49424 + + APDAKeyHi_EL1 = 49425 + + APDBKeyLo_EL1 = 49426 + + APDBKeyHi_EL1 = 49427 + + TPMIN0_EL1 = 49428 + + TPMAX0_EL1 = 49429 + + TPMIN1_EL1 = 49430 + + TPMAX1_EL1 = 49431 + + APGAKeyLo_EL1 = 49432 + + APGAKeyHi_EL1 = 49433 + + GCSCR_EL1 = 49448 + + GCSPR_EL1 = 49449 + + GCSCRE0_EL1 = 49450 + + TCRMASK_EL1 = 49466 + + TCR2MASK_EL1 = 49467 + + TCRALIAS_EL1 = 49470 + + TCR2ALIAS_EL1 = 49471 + + FGDTP0_EL1 = 49552 + + FGDTP1_EL1 = 49553 + + FGDTP2_EL1 = 49554 + + FGDTP3_EL1 = 49555 + + FGDTP4_EL1 = 49556 + + FGDTP5_EL1 = 49557 + + FGDTP6_EL1 = 49558 + + FGDTP7_EL1 = 49559 + + FGDTP8_EL1 = 49560 + + FGDTP9_EL1 = 49561 + + FGDTP10_EL1 = 49562 + + FGDTP11_EL1 = 49563 + + FGDTP12_EL1 = 49564 + + FGDTP13_EL1 = 49565 + + FGDTP14_EL1 = 49566 + + FGDTP15_EL1 = 49567 + + FGDTU0_EL1 = 49568 + + FGDTU1_EL1 = 49569 + + FGDTU2_EL1 = 49570 + + FGDTU3_EL1 = 49571 + + FGDTU4_EL1 = 49572 + + FGDTU5_EL1 = 49573 + + FGDTU6_EL1 = 49574 + + FGDTU7_EL1 = 49575 + + FGDTU8_EL1 = 49576 + + FGDTU9_EL1 = 49577 + + FGDTU10_EL1 = 49578 + + FGDTU11_EL1 = 49579 + + FGDTU12_EL1 = 49580 + + FGDTU13_EL1 = 49581 + + FGDTU14_EL1 = 49582 + + FGDTU15_EL1 = 49583 + + AFGDTP0_EL1 = 49584 + + AFGDTP1_EL1 = 49585 + + AFGDTP2_EL1 = 49586 + + AFGDTP3_EL1 = 49587 + + AFGDTP4_EL1 = 49588 + + AFGDTP5_EL1 = 49589 + + AFGDTP6_EL1 = 49590 + + AFGDTP7_EL1 = 49591 + + AFGDTP8_EL1 = 49592 + + AFGDTP9_EL1 = 49593 + + AFGDTP10_EL1 = 49594 + + AFGDTP11_EL1 = 49595 + + AFGDTP12_EL1 = 49596 + + AFGDTP13_EL1 = 49597 + + AFGDTP14_EL1 = 49598 + + AFGDTP15_EL1 = 49599 + + AFGDTU0_EL1 = 49600 + + AFGDTU1_EL1 = 49601 + + AFGDTU2_EL1 = 49602 + + AFGDTU3_EL1 = 49603 + + AFGDTU4_EL1 = 49604 + + AFGDTU5_EL1 = 49605 + + AFGDTU6_EL1 = 49606 + + AFGDTU7_EL1 = 49607 + + AFGDTU8_EL1 = 49608 + + AFGDTU9_EL1 = 49609 + + AFGDTU10_EL1 = 49610 + + AFGDTU11_EL1 = 49611 + + AFGDTU12_EL1 = 49612 + + AFGDTU13_EL1 = 49613 + + AFGDTU14_EL1 = 49614 + + AFGDTU15_EL1 = 49615 + + SPSR_EL1 = 49664 + + ELR_EL1 = 49665 + + STINDEX_EL1 = 49666 + + TINDEX_EL1 = 49667 + + SP_EL0 = 49672 + + SPSel = 49680 + + CurrentEL = 49682 + + PAN = 49683 + + UAO = 49684 + + ALLINT = 49688 + + PM = 49689 + + ICC_PMR_EL1 = 49712 + + AFSR0_EL1 = 49800 + + AFSR1_EL1 = 49801 + + ESR_EL1 = 49808 + + ERRIDR_EL1 = 49816 + + ERRSELR_EL1 = 49817 + + ERXGSR_EL1 = 49818 + + ERXFR_EL1 = 49824 + + ERXCTLR_EL1 = 49825 + + ERXSTATUS_EL1 = 49826 + + ERXADDR_EL1 = 49827 + + ERXPFGF_EL1 = 49828 + + ERXPFGCTL_EL1 = 49829 + + ERXPFGCDN_EL1 = 49830 + + ERXMISC0_EL1 = 49832 + + ERXMISC1_EL1 = 49833 + + ERXMISC2_EL1 = 49834 + + ERXMISC3_EL1 = 49835 + + TFSR_EL1 = 49840 + + TFSRE0_EL1 = 49841 + + FAR_EL1 = 49920 + + PFAR_EL1 = 49925 + + PRENR_EL1 = 49929 + + PRSELR_EL1 = 49937 + + PRBAR_EL1 = 49984 + + PRLAR_EL1 = 49985 + + PRBAR1_EL1 = 49988 + + PRLAR1_EL1 = 49989 + + PRBAR2_EL1 = 49992 + + PRLAR2_EL1 = 49993 + + PRBAR3_EL1 = 49996 + + PRLAR3_EL1 = 49997 + + PRBAR4_EL1 = 50000 + + PRLAR4_EL1 = 50001 + + PRBAR5_EL1 = 50004 + + PRLAR5_EL1 = 50005 + + PRBAR6_EL1 = 50008 + + PRLAR6_EL1 = 50009 + + PRBAR7_EL1 = 50012 + + PRLAR7_EL1 = 50013 + + PRBAR8_EL1 = 50016 + + PRLAR8_EL1 = 50017 + + PRBAR9_EL1 = 50020 + + PRLAR9_EL1 = 50021 + + PRBAR10_EL1 = 50024 + + PRLAR10_EL1 = 50025 + + PRBAR11_EL1 = 50028 + + PRLAR11_EL1 = 50029 + + PRBAR12_EL1 = 50032 + + PRLAR12_EL1 = 50033 + + PRBAR13_EL1 = 50036 + + PRLAR13_EL1 = 50037 + + PRBAR14_EL1 = 50040 + + PRLAR14_EL1 = 50041 + + PRBAR15_EL1 = 50044 + + PRLAR15_EL1 = 50045 + + PAR_EL1 = 50080 + + PMSCR_EL1 = 50376 + + PMSNEVFR_EL1 = 50377 + + PMSICR_EL1 = 50378 + + PMSIRR_EL1 = 50379 + + PMSFCR_EL1 = 50380 + + PMSEVFR_EL1 = 50381 + + PMSLATFR_EL1 = 50382 + + PMSIDR_EL1 = 50383 + + PMBLIMITR_EL1 = 50384 + + PMBPTR_EL1 = 50385 + + PMBSR_EL1 = 50387 + + PMSDSFR_EL1 = 50388 + + PMBMAR_EL1 = 50389 + + PMBIDR_EL1 = 50391 + + TRBLIMITR_EL1 = 50392 + + TRBPTR_EL1 = 50393 + + TRBBASER_EL1 = 50394 + + TRBSR_EL1 = 50395 + + TRBMAR_EL1 = 50396 + + TRBMPAM_EL1 = 50397 + + TRBTRG_EL1 = 50398 + + TRBIDR_EL1 = 50399 + + PMSSCR_EL1 = 50411 + + PMINTENSET_EL1 = 50417 + + PMINTENCLR_EL1 = 50418 + + PMUACR_EL1 = 50420 + + PMECR_EL1 = 50421 + + PMMIR_EL1 = 50422 + + PMIAR_EL1 = 50423 + + MAIR_EL1 = 50448 + + MAIR2_EL1 = 50449 + + PIRE0_EL1 = 50450 + + PIR_EL1 = 50451 + + POR_EL1 = 50452 + + S2POR_EL1 = 50453 + + TTTBRU_EL1 = 50454 + + TTTBRP_EL1 = 50455 + + AMAIR_EL1 = 50456 + + AMAIR2_EL1 = 50457 + + LORSA_EL1 = 50464 + + LOREA_EL1 = 50465 + + LORN_EL1 = 50466 + + LORC_EL1 = 50467 + + MPAMIDR_EL1 = 50468 + + MPAMBWIDR_EL1 = 50469 + + TLBIDIDR_EL1 = 50470 + + LORID_EL1 = 50471 + + MPAM1_EL1 = 50472 + + MPAM0_EL1 = 50473 + + MPAMCTL_EL1 = 50474 + + MPAMSM_EL1 = 50475 + + MPAMBW1_EL1 = 50476 + + MPAMBW0_EL1 = 50477 + + MPAMBWSM_EL1 = 50479 + + VBAR_EL1 = 50688 + + RVBAR_EL1 = 50689 + + RMR_EL1 = 50690 + + ISR_EL1 = 50696 + + DISR_EL1 = 50697 + + ICC_IAR0_EL1 = 50752 + + ICC_EOIR0_EL1 = 50753 + + ICC_HPPIR0_EL1 = 50754 + + ICC_BPR0_EL1 = 50755 + + ICC_AP0R0_EL1 = 50756 + + ICC_AP0R1_EL1 = 50757 + + ICC_AP0R2_EL1 = 50758 + + ICC_AP0R3_EL1 = 50759 + + ICC_AP1R0_EL1 = 50760 + + ICC_AP1R1_EL1 = 50761 + + ICC_AP1R2_EL1 = 50762 + + ICC_AP1R3_EL1 = 50763 + + ICC_NMIAR1_EL1 = 50765 + + ICC_PPI_HMR0_EL1 = 50768 + + ICC_PPI_HMR1_EL1 = 50769 + + ICC_IDR0_EL1 = 50770 + + ICC_HPPIR_EL1 = 50771 + + ICC_ICSR_EL1 = 50772 + + ICC_IAFFIDR_EL1 = 50773 + + ICC_PPI_ENABLER0_EL1 = 50774 + + ICC_PPI_ENABLER1_EL1 = 50775 + + ICC_DIR_EL1 = 50777 + + ICC_RPR_EL1 = 50779 + + ICC_SGI1R_EL1 = 50781 + + ICC_ASGI1R_EL1 = 50782 + + ICC_SGI0R_EL1 = 50783 + + ICC_IAR1_EL1 = 50784 + + ICC_EOIR1_EL1 = 50785 + + ICC_HPPIR1_EL1 = 50786 + + ICC_BPR1_EL1 = 50787 + + ICC_CTLR_EL1 = 50788 + + ICC_SRE_EL1 = 50789 + + ICC_IGRPEN0_EL1 = 50790 + + ICC_IGRPEN1_EL1 = 50791 + + ICC_PPI_CACTIVER0_EL1 = 50792 + + ICC_PPI_CACTIVER1_EL1 = 50793 + + ICC_PPI_SACTIVER0_EL1 = 50794 + + ICC_PPI_SACTIVER1_EL1 = 50795 + + ICC_PPI_CPENDR0_EL1 = 50796 + + ICC_PPI_CPENDR1_EL1 = 50797 + + ICC_PPI_SPENDR0_EL1 = 50798 + + ICC_PPI_SPENDR1_EL1 = 50799 + + ICC_PPI_PRIORITYR0_EL1 = 50800 + + ICC_PPI_PRIORITYR1_EL1 = 50801 + + ICC_PPI_PRIORITYR2_EL1 = 50802 + + ICC_PPI_PRIORITYR3_EL1 = 50803 + + ICC_PPI_PRIORITYR4_EL1 = 50804 + + ICC_PPI_PRIORITYR5_EL1 = 50805 + + ICC_PPI_PRIORITYR6_EL1 = 50806 + + ICC_PPI_PRIORITYR7_EL1 = 50807 + + ICC_PPI_PRIORITYR8_EL1 = 50808 + + ICC_PPI_PRIORITYR9_EL1 = 50809 + + ICC_PPI_PRIORITYR10_EL1 = 50810 + + ICC_PPI_PRIORITYR11_EL1 = 50811 + + ICC_PPI_PRIORITYR12_EL1 = 50812 + + ICC_PPI_PRIORITYR13_EL1 = 50813 + + ICC_PPI_PRIORITYR14_EL1 = 50814 + + ICC_PPI_PRIORITYR15_EL1 = 50815 + + TPIDR3_EL1 = 50816 + + CONTEXTIDR_EL1 = 50817 + + RCWSMASK_EL1 = 50819 + + TPIDR_EL1 = 50820 + + ACCDATA_EL1 = 50821 + + RCWMASK_EL1 = 50822 + + SCXTNUM_EL1 = 50823 + + CNTKCTL_EL1 = 50952 + + CCSIDR_EL1 = 51200 + + CLIDR_EL1 = 51201 + + CCSIDR2_EL1 = 51202 + + GMID_EL1 = 51204 + + SMIDR_EL1 = 51206 + + AIDR_EL1 = 51207 + + ICC_APR_EL1 = 52736 + + ICC_CR0_EL1 = 52737 + + ICC_PCR_EL1 = 52738 + + ICC_HAPR_EL1 = 52739 + + CSSELR_EL1 = 53248 + + CTR_EL0 = 55297 + + DCZID_EL0 = 55303 + + TPMIN0_EL0 = 55572 + + TPMAX0_EL0 = 55573 + + TPMIN1_EL0 = 55574 + + TPMAX1_EL0 = 55575 + + RNDR = 55584 + + RNDRRS = 55585 + + GCSPR_EL0 = 55593 + + TINDEX_EL0 = 55811 + + NZCV = 55824 + + DAIF = 55825 + + SVCR = 55826 + + DIT = 55829 + + SSBS = 55830 + + TCO = 55831 + + FPCR = 55840 + + FPSR = 55841 + + FPMR = 55842 + + DSPSR_EL0 = 55848 + + DLR_EL0 = 55849 + + DPOCR_EL0 = 55850 + + PMICNTR_EL0 = 56480 + + PMICFILTR_EL0 = 56496 + + PMCR_EL0 = 56544 + + PMCNTENSET_EL0 = 56545 + + PMCNTENCLR_EL0 = 56546 + + PMOVSCLR_EL0 = 56547 + + PMSWINC_EL0 = 56548 + + PMSELR_EL0 = 56549 + + PMCEID0_EL0 = 56550 + + PMCEID1_EL0 = 56551 + + PMCCNTR_EL0 = 56552 + + PMXEVTYPER_EL0 = 56553 + + PMXEVCNTR_EL0 = 56554 + + PMZR_EL0 = 56556 + + PMUSERENR_EL0 = 56560 + + PMOVSSET_EL0 = 56563 + + POR_EL0 = 56596 + + TPIDR3_EL0 = 56960 + + TPIDR_EL0 = 56962 + + TPIDRRO_EL0 = 56963 + + TPIDR2_EL0 = 56965 + + SCXTNUM_EL0 = 56967 + + AMCR_EL0 = 56976 + + AMCFGR_EL0 = 56977 + + AMCGCR_EL0 = 56978 + + AMUSERENR_EL0 = 56979 + + AMCNTENCLR0_EL0 = 56980 + + AMCNTENSET0_EL0 = 56981 + + AMCG1IDR_EL0 = 56982 + + AMCNTENCLR1_EL0 = 56984 + + AMCNTENSET1_EL0 = 56985 + + AMEVCNTR00_EL0 = 56992 + + AMEVCNTR01_EL0 = 56993 + + AMEVCNTR02_EL0 = 56994 + + AMEVCNTR03_EL0 = 56995 + + AMEVTYPER00_EL0 = 57008 + + AMEVTYPER01_EL0 = 57009 + + AMEVTYPER02_EL0 = 57010 + + AMEVTYPER03_EL0 = 57011 + + AMEVCNTR10_EL0 = 57056 + + AMEVCNTR11_EL0 = 57057 + + AMEVCNTR12_EL0 = 57058 + + AMEVCNTR13_EL0 = 57059 + + AMEVCNTR14_EL0 = 57060 + + AMEVCNTR15_EL0 = 57061 + + AMEVCNTR16_EL0 = 57062 + + AMEVCNTR17_EL0 = 57063 + + AMEVCNTR18_EL0 = 57064 + + AMEVCNTR19_EL0 = 57065 + + AMEVCNTR110_EL0 = 57066 + + AMEVCNTR111_EL0 = 57067 + + AMEVCNTR112_EL0 = 57068 + + AMEVCNTR113_EL0 = 57069 + + AMEVCNTR114_EL0 = 57070 + + AMEVCNTR115_EL0 = 57071 + + AMEVTYPER10_EL0 = 57072 + + AMEVTYPER11_EL0 = 57073 + + AMEVTYPER12_EL0 = 57074 + + AMEVTYPER13_EL0 = 57075 + + AMEVTYPER14_EL0 = 57076 + + AMEVTYPER15_EL0 = 57077 + + AMEVTYPER16_EL0 = 57078 + + AMEVTYPER17_EL0 = 57079 + + AMEVTYPER18_EL0 = 57080 + + AMEVTYPER19_EL0 = 57081 + + AMEVTYPER110_EL0 = 57082 + + AMEVTYPER111_EL0 = 57083 + + AMEVTYPER112_EL0 = 57084 + + AMEVTYPER113_EL0 = 57085 + + AMEVTYPER114_EL0 = 57086 + + AMEVTYPER115_EL0 = 57087 + + CNTFRQ_EL0 = 57088 + + CNTPCT_EL0 = 57089 + + CNTVCT_EL0 = 57090 + + CNTPCTSS_EL0 = 57093 + + CNTVCTSS_EL0 = 57094 + + CNTP_TVAL_EL0 = 57104 + + CNTP_CTL_EL0 = 57105 + + CNTP_CVAL_EL0 = 57106 + + CNTV_TVAL_EL0 = 57112 + + CNTV_CTL_EL0 = 57113 + + CNTV_CVAL_EL0 = 57114 + + PMEVCNTR0_EL0 = 57152 + + PMEVCNTR1_EL0 = 57153 + + PMEVCNTR2_EL0 = 57154 + + PMEVCNTR3_EL0 = 57155 + + PMEVCNTR4_EL0 = 57156 + + PMEVCNTR5_EL0 = 57157 + + PMEVCNTR6_EL0 = 57158 + + PMEVCNTR7_EL0 = 57159 + + PMEVCNTR8_EL0 = 57160 + + PMEVCNTR9_EL0 = 57161 + + PMEVCNTR10_EL0 = 57162 + + PMEVCNTR11_EL0 = 57163 + + PMEVCNTR12_EL0 = 57164 + + PMEVCNTR13_EL0 = 57165 + + PMEVCNTR14_EL0 = 57166 + + PMEVCNTR15_EL0 = 57167 + + PMEVCNTR16_EL0 = 57168 + + PMEVCNTR17_EL0 = 57169 + + PMEVCNTR18_EL0 = 57170 + + PMEVCNTR19_EL0 = 57171 + + PMEVCNTR20_EL0 = 57172 + + PMEVCNTR21_EL0 = 57173 + + PMEVCNTR22_EL0 = 57174 + + PMEVCNTR23_EL0 = 57175 + + PMEVCNTR24_EL0 = 57176 + + PMEVCNTR25_EL0 = 57177 + + PMEVCNTR26_EL0 = 57178 + + PMEVCNTR27_EL0 = 57179 + + PMEVCNTR28_EL0 = 57180 + + PMEVCNTR29_EL0 = 57181 + + PMEVCNTR30_EL0 = 57182 + + PMEVTYPER0_EL0 = 57184 + + PMEVTYPER1_EL0 = 57185 + + PMEVTYPER2_EL0 = 57186 + + PMEVTYPER3_EL0 = 57187 + + PMEVTYPER4_EL0 = 57188 + + PMEVTYPER5_EL0 = 57189 + + PMEVTYPER6_EL0 = 57190 + + PMEVTYPER7_EL0 = 57191 + + PMEVTYPER8_EL0 = 57192 + + PMEVTYPER9_EL0 = 57193 + + PMEVTYPER10_EL0 = 57194 + + PMEVTYPER11_EL0 = 57195 + + PMEVTYPER12_EL0 = 57196 + + PMEVTYPER13_EL0 = 57197 + + PMEVTYPER14_EL0 = 57198 + + PMEVTYPER15_EL0 = 57199 + + PMEVTYPER16_EL0 = 57200 + + PMEVTYPER17_EL0 = 57201 + + PMEVTYPER18_EL0 = 57202 + + PMEVTYPER19_EL0 = 57203 + + PMEVTYPER20_EL0 = 57204 + + PMEVTYPER21_EL0 = 57205 + + PMEVTYPER22_EL0 = 57206 + + PMEVTYPER23_EL0 = 57207 + + PMEVTYPER24_EL0 = 57208 + + PMEVTYPER25_EL0 = 57209 + + PMEVTYPER26_EL0 = 57210 + + PMEVTYPER27_EL0 = 57211 + + PMEVTYPER28_EL0 = 57212 + + PMEVTYPER29_EL0 = 57213 + + PMEVTYPER30_EL0 = 57214 + + PMCCFILTR_EL0 = 57215 + + VPIDR_EL2 = 57344 + + MPUIR_EL2 = 57348 + + VMPIDR_EL2 = 57349 + + SCTLR_EL2 = 57472 + + ACTLR_EL2 = 57473 + + SCTLR2_EL2 = 57475 + + HCR_EL2 = 57480 + + MDCR_EL2 = 57481 + + CPTR_EL2 = 57482 + + HSTR_EL2 = 57483 + + HFGRTR_EL2 = 57484 + + HFGWTR_EL2 = 57485 + + HFGITR_EL2 = 57486 + + HACR_EL2 = 57487 + + ZCR_EL2 = 57488 + + TRFCR_EL2 = 57489 + + HCRX_EL2 = 57490 + + TRCITECR_EL2 = 57491 + + SMPRIMAP_EL2 = 57493 + + SMCR_EL2 = 57494 + + SDER32_EL2 = 57497 + + SCTLRMASK_EL2 = 57504 + + ACTLRMASK_EL2 = 57505 + + CPTRMASK_EL2 = 57506 + + SCTLR2MASK_EL2 = 57507 + + NVHCR_EL2 = 57512 + + NVHCRX_EL2 = 57513 + + NVHCRMASK_EL2 = 57516 + + NVHCRXMASK_EL2 = 57517 + + HCRMASK_EL2 = 57518 + + HCRXMASK_EL2 = 57519 + + TTBR0_EL2 = 57600 + + TTBR1_EL2 = 57601 + + TCR_EL2 = 57602 + + TCR2_EL2 = 57603 + + IRTBRU_EL2 = 57604 + + IRTBRP_EL2 = 57605 + + DPOTBR0_EL2 = 57606 + + DPOTBR1_EL2 = 57607 + + VTTBR_EL2 = 57608 + + VTCR_EL2 = 57610 + + LDSTT_EL2 = 57615 + + VNCR_EL2 = 57616 + + VNCCR_EL2 = 57617 + + TPMIN0_EL2 = 57620 + + TPMAX0_EL2 = 57621 + + TPMIN1_EL2 = 57622 + + TPMAX1_EL2 = 57623 + + HDBSSBR_EL2 = 57626 + + HDBSSPROD_EL2 = 57627 + + HACDBSBR_EL2 = 57628 + + HACDBSCONS_EL2 = 57629 + + GCSCR_EL2 = 57640 + + GCSPR_EL2 = 57641 + + VSTTBR_EL2 = 57648 + + VSTCR_EL2 = 57650 + + TCRMASK_EL2 = 57658 + + TCR2MASK_EL2 = 57659 + + VTLBID0_EL2 = 57664 + + VTLBID1_EL2 = 57665 + + VTLBID2_EL2 = 57666 + + VTLBID3_EL2 = 57667 + + VTLBIDOS0_EL2 = 57672 + + VTLBIDOS1_EL2 = 57673 + + VTLBIDOS2_EL2 = 57674 + + VTLBIDOS3_EL2 = 57675 + + DACR32_EL2 = 57728 + + HDFGRTR2_EL2 = 57736 + + HDFGWTR2_EL2 = 57737 + + HFGRTR2_EL2 = 57738 + + HFGWTR2_EL2 = 57739 + + HDFGRTR_EL2 = 57740 + + HDFGWTR_EL2 = 57741 + + HAFGRTR_EL2 = 57742 + + HFGITR2_EL2 = 57743 + + FGDTP0_EL2 = 57744 + + FGDTP1_EL2 = 57745 + + FGDTP2_EL2 = 57746 + + FGDTP3_EL2 = 57747 + + FGDTP4_EL2 = 57748 + + FGDTP5_EL2 = 57749 + + FGDTP6_EL2 = 57750 + + FGDTP7_EL2 = 57751 + + FGDTP8_EL2 = 57752 + + FGDTP9_EL2 = 57753 + + FGDTP10_EL2 = 57754 + + FGDTP11_EL2 = 57755 + + FGDTP12_EL2 = 57756 + + FGDTP13_EL2 = 57757 + + FGDTP14_EL2 = 57758 + + FGDTP15_EL2 = 57759 + + FGDTU0_EL2 = 57760 + + FGDTU1_EL2 = 57761 + + FGDTU2_EL2 = 57762 + + FGDTU3_EL2 = 57763 + + FGDTU4_EL2 = 57764 + + FGDTU5_EL2 = 57765 + + FGDTU6_EL2 = 57766 + + FGDTU7_EL2 = 57767 + + FGDTU8_EL2 = 57768 + + FGDTU9_EL2 = 57769 + + FGDTU10_EL2 = 57770 + + FGDTU11_EL2 = 57771 + + FGDTU12_EL2 = 57772 + + FGDTU13_EL2 = 57773 + + FGDTU14_EL2 = 57774 + + FGDTU15_EL2 = 57775 + + AFGDTP0_EL2 = 57776 + + AFGDTP1_EL2 = 57777 + + AFGDTP2_EL2 = 57778 + + AFGDTP3_EL2 = 57779 + + AFGDTP4_EL2 = 57780 + + AFGDTP5_EL2 = 57781 + + AFGDTP6_EL2 = 57782 + + AFGDTP7_EL2 = 57783 + + AFGDTP8_EL2 = 57784 + + AFGDTP9_EL2 = 57785 + + AFGDTP10_EL2 = 57786 + + AFGDTP11_EL2 = 57787 + + AFGDTP12_EL2 = 57788 + + AFGDTP13_EL2 = 57789 + + AFGDTP14_EL2 = 57790 + + AFGDTP15_EL2 = 57791 + + AFGDTU0_EL2 = 57792 + + AFGDTU1_EL2 = 57793 + + AFGDTU2_EL2 = 57794 + + AFGDTU3_EL2 = 57795 + + AFGDTU4_EL2 = 57796 + + AFGDTU5_EL2 = 57797 + + AFGDTU6_EL2 = 57798 + + AFGDTU7_EL2 = 57799 + + AFGDTU8_EL2 = 57800 + + AFGDTU9_EL2 = 57801 + + AFGDTU10_EL2 = 57802 + + AFGDTU11_EL2 = 57803 + + AFGDTU12_EL2 = 57804 + + AFGDTU13_EL2 = 57805 + + AFGDTU14_EL2 = 57806 + + AFGDTU15_EL2 = 57807 + + SPSR_EL2 = 57856 + + ELR_EL2 = 57857 + + STINDEX_EL2 = 57858 + + TINDEX_EL2 = 57859 + + SP_EL1 = 57864 + + SPSR_irq = 57880 + + SPSR_abt = 57881 + + SPSR_und = 57882 + + SPSR_fiq = 57883 + + IFSR32_EL2 = 57985 + + AFSR0_EL2 = 57992 + + AFSR1_EL2 = 57993 + + ESR_EL2 = 58000 + + VSESR_EL2 = 58003 + + FPEXC32_EL2 = 58008 + + TFSR_EL2 = 58032 + + FAR_EL2 = 58112 + + HPFAR_EL2 = 58116 + + PFAR_EL2 = 58117 + + PRENR_EL2 = 58121 + + PRSELR_EL2 = 58129 + + PRBAR_EL2 = 58176 + + PRLAR_EL2 = 58177 + + PRBAR1_EL2 = 58180 + + PRLAR1_EL2 = 58181 + + PRBAR2_EL2 = 58184 + + PRLAR2_EL2 = 58185 + + PRBAR3_EL2 = 58188 + + PRLAR3_EL2 = 58189 + + PRBAR4_EL2 = 58192 + + PRLAR4_EL2 = 58193 + + PRBAR5_EL2 = 58196 + + PRLAR5_EL2 = 58197 + + PRBAR6_EL2 = 58200 + + PRLAR6_EL2 = 58201 + + PRBAR7_EL2 = 58204 + + PRLAR7_EL2 = 58205 + + PRBAR8_EL2 = 58208 + + PRLAR8_EL2 = 58209 + + PRBAR9_EL2 = 58212 + + PRLAR9_EL2 = 58213 + + PRBAR10_EL2 = 58216 + + PRLAR10_EL2 = 58217 + + PRBAR11_EL2 = 58220 + + PRLAR11_EL2 = 58221 + + PRBAR12_EL2 = 58224 + + PRLAR12_EL2 = 58225 + + PRBAR13_EL2 = 58228 + + PRLAR13_EL2 = 58229 + + PRBAR14_EL2 = 58232 + + PRLAR14_EL2 = 58233 + + PRBAR15_EL2 = 58236 + + PRLAR15_EL2 = 58237 + + PMSCR_EL2 = 58568 + + PMBSR_EL2 = 58579 + + TRBSR_EL2 = 58587 + + MAIR2_EL2 = 58633 + + MAIR_EL2 = 58640 + + PIRE0_EL2 = 58642 + + PIR_EL2 = 58643 + + POR_EL2 = 58644 + + S2PIR_EL2 = 58645 + + TTTBRU_EL2 = 58646 + + TTTBRP_EL2 = 58647 + + AMAIR_EL2 = 58648 + + AMAIR2_EL2 = 58649 + + MPAMHCR_EL2 = 58656 + + MPAMVPMV_EL2 = 58657 + + MPAM2_EL2 = 58664 + + MPAMCTL_EL2 = 58666 + + MPAMBW2_EL2 = 58668 + + MPAMBWCAP_EL2 = 58670 + + MPAMVPM0_EL2 = 58672 + + MPAMVPM1_EL2 = 58673 + + MPAMVPM2_EL2 = 58674 + + MPAMVPM3_EL2 = 58675 + + MPAMVPM4_EL2 = 58676 + + MPAMVPM5_EL2 = 58677 + + MPAMVPM6_EL2 = 58678 + + MPAMVPM7_EL2 = 58679 + + MPAMVIDCR_EL2 = 58680 + + MPAMVIDSR_EL2 = 58681 + + MECID_P0_EL2 = 58688 + + MECID_A0_EL2 = 58689 + + MECID_P1_EL2 = 58690 + + MECID_A1_EL2 = 58691 + + MECIDR_EL2 = 58695 + + VMECID_P_EL2 = 58696 + + VMECID_A_EL2 = 58697 + + VBAR_EL2 = 58880 + + RVBAR_EL2 = 58881 + + RMR_EL2 = 58882 + + VDISR_EL2 = 58889 + + ICH_AP0R0_EL2 = 58944 + + ICH_AP0R1_EL2 = 58945 + + ICH_AP0R2_EL2 = 58946 + + ICH_AP0R3_EL2 = 58947 + + ICH_APR_EL2 = 58948 + + ICH_HPPIR_EL2 = 58949 + + ICH_AP1R0_EL2 = 58952 + + ICH_AP1R1_EL2 = 58953 + + ICH_AP1R2_EL2 = 58954 + + ICH_AP1R3_EL2 = 58955 + + ICH_HFGRTR_EL2 = 58956 + + ICC_SRE_EL2 = 58957 + + ICH_HFGWTR_EL2 = 58958 + + ICH_HFGITR_EL2 = 58959 + + ICH_PPI_DVIR0_EL2 = 58960 + + ICH_PPI_DVIR1_EL2 = 58961 + + ICH_PPI_ENABLER0_EL2 = 58962 + + ICH_PPI_ENABLER1_EL2 = 58963 + + ICH_PPI_PENDR0_EL2 = 58964 + + ICH_PPI_PENDR1_EL2 = 58965 + + ICH_PPI_ACTIVER0_EL2 = 58966 + + ICH_PPI_ACTIVER1_EL2 = 58967 + + ICH_HCR_EL2 = 58968 + + ICH_VTR_EL2 = 58969 + + ICH_MISR_EL2 = 58970 + + ICH_EISR_EL2 = 58971 + + ICH_VCTLR_EL2 = 58972 + + ICH_ELRSR_EL2 = 58973 + + ICH_CONTEXTR_EL2 = 58974 + + ICH_VMCR_EL2 = 58975 + + ICH_LR0_EL2 = 58976 + + ICH_LR1_EL2 = 58977 + + ICH_LR2_EL2 = 58978 + + ICH_LR3_EL2 = 58979 + + ICH_LR4_EL2 = 58980 + + ICH_LR5_EL2 = 58981 + + ICH_LR6_EL2 = 58982 + + ICH_LR7_EL2 = 58983 + + ICH_LR8_EL2 = 58984 + + ICH_LR9_EL2 = 58985 + + ICH_LR10_EL2 = 58986 + + ICH_LR11_EL2 = 58987 + + ICH_LR12_EL2 = 58988 + + ICH_LR13_EL2 = 58989 + + ICH_LR14_EL2 = 58990 + + ICH_LR15_EL2 = 58991 + + ICH_PPI_PRIORITYR0_EL2 = 58992 + + ICH_PPI_PRIORITYR1_EL2 = 58993 + + ICH_PPI_PRIORITYR2_EL2 = 58994 + + ICH_PPI_PRIORITYR3_EL2 = 58995 + + ICH_PPI_PRIORITYR4_EL2 = 58996 + + ICH_PPI_PRIORITYR5_EL2 = 58997 + + ICH_PPI_PRIORITYR6_EL2 = 58998 + + ICH_PPI_PRIORITYR7_EL2 = 58999 + + ICH_PPI_PRIORITYR8_EL2 = 59000 + + ICH_PPI_PRIORITYR9_EL2 = 59001 + + ICH_PPI_PRIORITYR10_EL2 = 59002 + + ICH_PPI_PRIORITYR11_EL2 = 59003 + + ICH_PPI_PRIORITYR12_EL2 = 59004 + + ICH_PPI_PRIORITYR13_EL2 = 59005 + + ICH_PPI_PRIORITYR14_EL2 = 59006 + + ICH_PPI_PRIORITYR15_EL2 = 59007 + + TPIDR3_EL2 = 59008 + + CONTEXTIDR_EL2 = 59009 + + TPIDR_EL2 = 59010 + + SCXTNUM_EL2 = 59015 + + AMEVCNTVOFF00_EL2 = 59072 + + AMEVCNTVOFF01_EL2 = 59073 + + AMEVCNTVOFF02_EL2 = 59074 + + AMEVCNTVOFF03_EL2 = 59075 + + AMEVCNTVOFF04_EL2 = 59076 + + AMEVCNTVOFF05_EL2 = 59077 + + AMEVCNTVOFF06_EL2 = 59078 + + AMEVCNTVOFF07_EL2 = 59079 + + AMEVCNTVOFF08_EL2 = 59080 + + AMEVCNTVOFF09_EL2 = 59081 + + AMEVCNTVOFF010_EL2 = 59082 + + AMEVCNTVOFF011_EL2 = 59083 + + AMEVCNTVOFF012_EL2 = 59084 + + AMEVCNTVOFF013_EL2 = 59085 + + AMEVCNTVOFF014_EL2 = 59086 + + AMEVCNTVOFF015_EL2 = 59087 + + AMEVCNTVOFF10_EL2 = 59088 + + AMEVCNTVOFF11_EL2 = 59089 + + AMEVCNTVOFF12_EL2 = 59090 + + AMEVCNTVOFF13_EL2 = 59091 + + AMEVCNTVOFF14_EL2 = 59092 + + AMEVCNTVOFF15_EL2 = 59093 + + AMEVCNTVOFF16_EL2 = 59094 + + AMEVCNTVOFF17_EL2 = 59095 + + AMEVCNTVOFF18_EL2 = 59096 + + AMEVCNTVOFF19_EL2 = 59097 + + AMEVCNTVOFF110_EL2 = 59098 + + AMEVCNTVOFF111_EL2 = 59099 + + AMEVCNTVOFF112_EL2 = 59100 + + AMEVCNTVOFF113_EL2 = 59101 + + AMEVCNTVOFF114_EL2 = 59102 + + AMEVCNTVOFF115_EL2 = 59103 + + CNTVOFF_EL2 = 59139 + + CNTSCALE_EL2 = 59140 + + CNTISCALE_EL2 = 59141 + + CNTPOFF_EL2 = 59142 + + CNTVFRQ_EL2 = 59143 + + CNTHCTL_EL2 = 59144 + + CNTHP_TVAL_EL2 = 59152 + + CNTHP_CTL_EL2 = 59153 + + CNTHP_CVAL_EL2 = 59154 + + CNTHV_TVAL_EL2 = 59160 + + CNTHV_CTL_EL2 = 59161 + + CNTHV_CVAL_EL2 = 59162 + + CNTHVS_TVAL_EL2 = 59168 + + CNTHVS_CTL_EL2 = 59169 + + CNTHVS_CVAL_EL2 = 59170 + + CNTHPS_TVAL_EL2 = 59176 + + CNTHPS_CTL_EL2 = 59177 + + CNTHPS_CVAL_EL2 = 59178 + + SCTLR_EL12 = 59520 + + ACTLR_EL12 = 59521 + + CPACR_EL12 = 59522 + + SCTLR2_EL12 = 59523 + + ZCR_EL12 = 59536 + + TRFCR_EL12 = 59537 + + TRCITECR_EL12 = 59539 + + SMCR_EL12 = 59542 + + SCTLRMASK_EL12 = 59552 + + ACTLRMASK_EL12 = 59553 + + CPACRMASK_EL12 = 59554 + + SCTLR2MASK_EL12 = 59555 + + TTBR0_EL12 = 59648 + + TTBR1_EL12 = 59649 + + TCR_EL12 = 59650 + + TCR2_EL12 = 59651 + + IRTBRU_EL12 = 59652 + + IRTBRP_EL12 = 59653 + + DPOTBR0_EL12 = 59654 + + DPOTBR1_EL12 = 59655 + + LDSTT_EL12 = 59663 + + TPMIN0_EL12 = 59668 + + TPMAX0_EL12 = 59669 + + TPMIN1_EL12 = 59670 + + TPMAX1_EL12 = 59671 + + GCSCR_EL12 = 59688 + + GCSPR_EL12 = 59689 + + TCRMASK_EL12 = 59706 + + TCR2MASK_EL12 = 59707 + + FGDTP0_EL12 = 59792 + + FGDTP1_EL12 = 59793 + + FGDTP2_EL12 = 59794 + + FGDTP3_EL12 = 59795 + + FGDTP4_EL12 = 59796 + + FGDTP5_EL12 = 59797 + + FGDTP6_EL12 = 59798 + + FGDTP7_EL12 = 59799 + + FGDTP8_EL12 = 59800 + + FGDTP9_EL12 = 59801 + + FGDTP10_EL12 = 59802 + + FGDTP11_EL12 = 59803 + + FGDTP12_EL12 = 59804 + + FGDTP13_EL12 = 59805 + + FGDTP14_EL12 = 59806 + + FGDTP15_EL12 = 59807 + + FGDTU0_EL12 = 59808 + + FGDTU1_EL12 = 59809 + + FGDTU2_EL12 = 59810 + + FGDTU3_EL12 = 59811 + + FGDTU4_EL12 = 59812 + + FGDTU5_EL12 = 59813 + + FGDTU6_EL12 = 59814 + + FGDTU7_EL12 = 59815 + + FGDTU8_EL12 = 59816 + + FGDTU9_EL12 = 59817 + + FGDTU10_EL12 = 59818 + + FGDTU11_EL12 = 59819 + + FGDTU12_EL12 = 59820 + + FGDTU13_EL12 = 59821 + + FGDTU14_EL12 = 59822 + + FGDTU15_EL12 = 59823 + + AFGDTP0_EL12 = 59824 + + AFGDTP1_EL12 = 59825 + + AFGDTP2_EL12 = 59826 + + AFGDTP3_EL12 = 59827 + + AFGDTP4_EL12 = 59828 + + AFGDTP5_EL12 = 59829 + + AFGDTP6_EL12 = 59830 + + AFGDTP7_EL12 = 59831 + + AFGDTP8_EL12 = 59832 + + AFGDTP9_EL12 = 59833 + + AFGDTP10_EL12 = 59834 + + AFGDTP11_EL12 = 59835 + + AFGDTP12_EL12 = 59836 + + AFGDTP13_EL12 = 59837 + + AFGDTP14_EL12 = 59838 + + AFGDTP15_EL12 = 59839 + + AFGDTU0_EL12 = 59840 + + AFGDTU1_EL12 = 59841 + + AFGDTU2_EL12 = 59842 + + AFGDTU3_EL12 = 59843 + + AFGDTU4_EL12 = 59844 + + AFGDTU5_EL12 = 59845 + + AFGDTU6_EL12 = 59846 + + AFGDTU7_EL12 = 59847 + + AFGDTU8_EL12 = 59848 + + AFGDTU9_EL12 = 59849 + + AFGDTU10_EL12 = 59850 + + AFGDTU11_EL12 = 59851 + + AFGDTU12_EL12 = 59852 + + AFGDTU13_EL12 = 59853 + + AFGDTU14_EL12 = 59854 + + AFGDTU15_EL12 = 59855 + + SPSR_EL12 = 59904 + + ELR_EL12 = 59905 + + STINDEX_EL12 = 59906 + + TINDEX_EL12 = 59907 + + AFSR0_EL12 = 60040 + + AFSR1_EL12 = 60041 + + ESR_EL12 = 60048 + + TFSR_EL12 = 60080 + + FAR_EL12 = 60160 + + PFAR_EL12 = 60165 + + PMSCR_EL12 = 60616 + + PMBSR_EL12 = 60627 + + TRBSR_EL12 = 60635 + + MAIR_EL12 = 60688 + + MAIR2_EL12 = 60689 + + PIRE0_EL12 = 60690 + + PIR_EL12 = 60691 + + POR_EL12 = 60692 + + TTTBRU_EL12 = 60694 + + TTTBRP_EL12 = 60695 + + AMAIR_EL12 = 60696 + + AMAIR2_EL12 = 60697 + + MPAM1_EL12 = 60712 + + MPAMCTL_EL12 = 60714 + + MPAMBW1_EL12 = 60716 + + VBAR_EL12 = 60928 + + TPIDR3_EL12 = 61056 + + CONTEXTIDR_EL12 = 61057 + + SCXTNUM_EL12 = 61063 + + CNTKCTL_EL12 = 61192 + + CNTP_TVAL_EL02 = 61200 + + CNTP_CTL_EL02 = 61201 + + CNTP_CVAL_EL02 = 61202 + + CNTV_TVAL_EL02 = 61208 + + CNTV_CTL_EL02 = 61209 + + CNTV_CVAL_EL02 = 61210 + + SCTLR_EL3 = 61568 + + ACTLR_EL3 = 61569 + + SCTLR2_EL3 = 61571 + + SCR_EL3 = 61576 + + SDER32_EL3 = 61577 + + CPTR_EL3 = 61578 + + FGWTE3_EL3 = 61581 + + ZCR_EL3 = 61584 + + SMCR_EL3 = 61590 + + MDCR_EL3 = 61593 + + TTBR0_EL3 = 61696 + + TCR_EL3 = 61698 + + IRTBRP_EL3 = 61701 + + DPOTBR0_EL3 = 61702 + + GPTBR_EL3 = 61708 + + GPCBW_EL3 = 61709 + + GPCCR_EL3 = 61710 + + GCSCR_EL3 = 61736 + + GCSPR_EL3 = 61737 + + FGDTP0_EL3 = 61840 + + FGDTP1_EL3 = 61841 + + FGDTP2_EL3 = 61842 + + FGDTP3_EL3 = 61843 + + FGDTP4_EL3 = 61844 + + FGDTP5_EL3 = 61845 + + FGDTP6_EL3 = 61846 + + FGDTP7_EL3 = 61847 + + FGDTP8_EL3 = 61848 + + FGDTP9_EL3 = 61849 + + FGDTP10_EL3 = 61850 + + FGDTP11_EL3 = 61851 + + FGDTP12_EL3 = 61852 + + FGDTP13_EL3 = 61853 + + FGDTP14_EL3 = 61854 + + FGDTP15_EL3 = 61855 + + AFGDTP0_EL3 = 61872 + + AFGDTP1_EL3 = 61873 + + AFGDTP2_EL3 = 61874 + + AFGDTP3_EL3 = 61875 + + AFGDTP4_EL3 = 61876 + + AFGDTP5_EL3 = 61877 + + AFGDTP6_EL3 = 61878 + + AFGDTP7_EL3 = 61879 + + AFGDTP8_EL3 = 61880 + + AFGDTP9_EL3 = 61881 + + AFGDTP10_EL3 = 61882 + + AFGDTP11_EL3 = 61883 + + AFGDTP12_EL3 = 61884 + + AFGDTP13_EL3 = 61885 + + AFGDTP14_EL3 = 61886 + + AFGDTP15_EL3 = 61887 + + SPSR_EL3 = 61952 + + ELR_EL3 = 61953 + + STINDEX_EL3 = 61954 + + TINDEX_EL3 = 61955 + + SP_EL2 = 61960 + + AFSR0_EL3 = 62088 + + AFSR1_EL3 = 62089 + + ESR_EL3 = 62096 + + VSESR_EL3 = 62099 + + TFSR_EL3 = 62128 + + FAR_EL3 = 62208 + + MFAR_EL3 = 62213 + + PMBSR_EL3 = 62675 + + TRBSR_EL3 = 62683 + + MAIR2_EL3 = 62729 + + MAIR_EL3 = 62736 + + PIR_EL3 = 62739 + + POR_EL3 = 62740 + + TTTBRP_EL3 = 62743 + + AMAIR_EL3 = 62744 + + AMAIR2_EL3 = 62745 + + MPAM3_EL3 = 62760 + + MPAMCTL_EL3 = 62762 + + MPAMBW3_EL3 = 62764 + + MPAMVIDSR_EL3 = 62777 + + MECID_RL_A_EL3 = 62801 + + VBAR_EL3 = 62976 + + RVBAR_EL3 = 62977 + + RMR_EL3 = 62978 + + VDISR_EL3 = 62985 + + ICC_APR_EL3 = 63040 + + ICC_PCR_EL3 = 63041 + + ICC_DOMHPPIR_EL3 = 63042 + + ICC_PPI_DOMAINR0_EL3 = 63044 + + ICC_PPI_DOMAINR1_EL3 = 63045 + + ICC_PPI_DOMAINR2_EL3 = 63046 + + ICC_PPI_DOMAINR3_EL3 = 63047 + + ICC_CR0_EL3 = 63048 + + ICC_HPPIR_EL3 = 63049 + + ICC_CTLR_EL3 = 63076 + + ICC_SRE_EL3 = 63077 + + ICC_IGRPEN1_EL3 = 63079 + + TPIDR3_EL3 = 63104 + + TPIDR_EL3 = 63106 + + SCXTNUM_EL3 = 63111 + + CNTPS_TVAL_EL1 = 65296 + + CNTPS_CTL_EL1 = 65297 + + CNTPS_CVAL_EL1 = 65298 + + NUM_TARGET_SYSREGS = 1665 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/aarch64/operands.pyi b/vendor/lief/api/python/lief/assembly/aarch64/operands.pyi new file mode 100644 index 0000000..3b32bd0 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/aarch64/operands.pyi @@ -0,0 +1,57 @@ +import enum +from typing import Optional, Union + +import lief.assembly.aarch64 + +import lief.assembly.aarch64 + + +class Immediate(lief.assembly.aarch64.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.aarch64.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> Optional[Union[lief.assembly.aarch64.REG, lief.assembly.aarch64.SYSREG]]: ... + +class Memory(lief.assembly.aarch64.Operand): + class SHIFT(enum.Enum): + UNKNOWN = 0 + + LSL = 1 + + UXTX = 2 + + UXTW = 3 + + SXTX = 4 + + SXTW = 5 + + class shift_info_t: + @property + def type(self) -> Memory.SHIFT: ... + + @property + def value(self) -> int: ... + + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.aarch64.REG: ... + + @property + def offset(self) -> Optional[Union[lief.assembly.aarch64.REG, int]]: ... + + @property + def shift(self) -> Memory.shift_info_t: ... + +class PCRelative(lief.assembly.aarch64.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/assembly/arm.pyi b/vendor/lief/api/python/lief/assembly/arm.pyi new file mode 100644 index 0000000..d4ce07c --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/arm.pyi @@ -0,0 +1,9051 @@ +import enum + +import lief.assembly + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ADDSri = 322 + + ADDSrr = 323 + + ADDSrsi = 324 + + ADDSrsr = 325 + + ADJCALLSTACKDOWN = 326 + + ADJCALLSTACKUP = 327 + + ASRi = 328 + + ASRr = 329 + + ASRs1 = 330 + + B = 331 + + BCCZi64 = 332 + + BCCi64 = 333 + + BLX_noip = 334 + + BLX_pred_noip = 335 + + BL_PUSHLR = 336 + + BMOVPCB_CALL = 337 + + BMOVPCRX_CALL = 338 + + BR_JTadd = 339 + + BR_JTm_i12 = 340 + + BR_JTm_rs = 341 + + BR_JTr = 342 + + BX_CALL = 343 + + CMP_SWAP_16 = 344 + + CMP_SWAP_32 = 345 + + CMP_SWAP_64 = 346 + + CMP_SWAP_8 = 347 + + CONSTPOOL_ENTRY = 348 + + COPY_STRUCT_BYVAL_I32 = 349 + + ITasm = 350 + + Int_eh_sjlj_dispatchsetup = 351 + + Int_eh_sjlj_longjmp = 352 + + Int_eh_sjlj_setjmp = 353 + + Int_eh_sjlj_setjmp_nofp = 354 + + Int_eh_sjlj_setup_dispatch = 355 + + JUMPTABLE_ADDRS = 356 + + JUMPTABLE_INSTS = 357 + + JUMPTABLE_TBB = 358 + + JUMPTABLE_TBH = 359 + + KCFI_CHECK_ARM = 360 + + KCFI_CHECK_Thumb1 = 361 + + KCFI_CHECK_Thumb2 = 362 + + LDMIA_RET = 363 + + LDRBT_POST = 364 + + LDRConstPool = 365 + + LDRHTii = 366 + + LDRLIT_ga_abs = 367 + + LDRLIT_ga_pcrel = 368 + + LDRLIT_ga_pcrel_ldr = 369 + + LDRSBTii = 370 + + LDRSHTii = 371 + + LDRT_POST = 372 + + LEApcrel = 373 + + LEApcrelJT = 374 + + LOADDUAL = 375 + + LSLi = 376 + + LSLr = 377 + + LSRi = 378 + + LSRr = 379 + + LSRs1 = 380 + + MEMCPY = 381 + + MLAv5 = 382 + + MOVCCi = 383 + + MOVCCi16 = 384 + + MOVCCi32imm = 385 + + MOVCCr = 386 + + MOVCCsi = 387 + + MOVCCsr = 388 + + MOVPCRX = 389 + + MOVTi16_ga_pcrel = 390 + + MOV_ga_pcrel = 391 + + MOV_ga_pcrel_ldr = 392 + + MOVi16_ga_pcrel = 393 + + MOVi32imm = 394 + + MQPRCopy = 395 + + MQQPRLoad = 396 + + MQQPRStore = 397 + + MQQQQPRLoad = 398 + + MQQQQPRStore = 399 + + MULv5 = 400 + + MVE_MEMCPYLOOPINST = 401 + + MVE_MEMSETLOOPINST = 402 + + MVNCCi = 403 + + PICADD = 404 + + PICLDR = 405 + + PICLDRB = 406 + + PICLDRH = 407 + + PICLDRSB = 408 + + PICLDRSH = 409 + + PICSTR = 410 + + PICSTRB = 411 + + PICSTRH = 412 + + RORi = 413 + + RORr = 414 + + RRX = 415 + + RRXi = 416 + + RSBSri = 417 + + RSBSrsi = 418 + + RSBSrsr = 419 + + SEH_EpilogEnd = 420 + + SEH_EpilogStart = 421 + + SEH_Nop = 422 + + SEH_Nop_Ret = 423 + + SEH_PrologEnd = 424 + + SEH_SaveFRegs = 425 + + SEH_SaveLR = 426 + + SEH_SaveRegs = 427 + + SEH_SaveRegs_Ret = 428 + + SEH_SaveSP = 429 + + SEH_StackAlloc = 430 + + SMLALv5 = 431 + + SMULLv5 = 432 + + SPACE = 433 + + STOREDUAL = 434 + + STRBT_POST = 435 + + STRBi_preidx = 436 + + STRBr_preidx = 437 + + STRH_preidx = 438 + + STRT_POST = 439 + + STRi_preidx = 440 + + STRr_preidx = 441 + + SUBS_PC_LR = 442 + + SUBSri = 443 + + SUBSrr = 444 + + SUBSrsi = 445 + + SUBSrsr = 446 + + SpeculationBarrierISBDSBEndBB = 447 + + SpeculationBarrierSBEndBB = 448 + + TAILJMPd = 449 + + TAILJMPr = 450 + + TAILJMPr4 = 451 + + TCRETURNdi = 452 + + TCRETURNri = 453 + + TCRETURNrinotr12 = 454 + + TPsoft = 455 + + UMLALv5 = 456 + + UMULLv5 = 457 + + VLD1LNdAsm_16 = 458 + + VLD1LNdAsm_32 = 459 + + VLD1LNdAsm_8 = 460 + + VLD1LNdWB_fixed_Asm_16 = 461 + + VLD1LNdWB_fixed_Asm_32 = 462 + + VLD1LNdWB_fixed_Asm_8 = 463 + + VLD1LNdWB_register_Asm_16 = 464 + + VLD1LNdWB_register_Asm_32 = 465 + + VLD1LNdWB_register_Asm_8 = 466 + + VLD2LNdAsm_16 = 467 + + VLD2LNdAsm_32 = 468 + + VLD2LNdAsm_8 = 469 + + VLD2LNdWB_fixed_Asm_16 = 470 + + VLD2LNdWB_fixed_Asm_32 = 471 + + VLD2LNdWB_fixed_Asm_8 = 472 + + VLD2LNdWB_register_Asm_16 = 473 + + VLD2LNdWB_register_Asm_32 = 474 + + VLD2LNdWB_register_Asm_8 = 475 + + VLD2LNqAsm_16 = 476 + + VLD2LNqAsm_32 = 477 + + VLD2LNqWB_fixed_Asm_16 = 478 + + VLD2LNqWB_fixed_Asm_32 = 479 + + VLD2LNqWB_register_Asm_16 = 480 + + VLD2LNqWB_register_Asm_32 = 481 + + VLD3DUPdAsm_16 = 482 + + VLD3DUPdAsm_32 = 483 + + VLD3DUPdAsm_8 = 484 + + VLD3DUPdWB_fixed_Asm_16 = 485 + + VLD3DUPdWB_fixed_Asm_32 = 486 + + VLD3DUPdWB_fixed_Asm_8 = 487 + + VLD3DUPdWB_register_Asm_16 = 488 + + VLD3DUPdWB_register_Asm_32 = 489 + + VLD3DUPdWB_register_Asm_8 = 490 + + VLD3DUPqAsm_16 = 491 + + VLD3DUPqAsm_32 = 492 + + VLD3DUPqAsm_8 = 493 + + VLD3DUPqWB_fixed_Asm_16 = 494 + + VLD3DUPqWB_fixed_Asm_32 = 495 + + VLD3DUPqWB_fixed_Asm_8 = 496 + + VLD3DUPqWB_register_Asm_16 = 497 + + VLD3DUPqWB_register_Asm_32 = 498 + + VLD3DUPqWB_register_Asm_8 = 499 + + VLD3LNdAsm_16 = 500 + + VLD3LNdAsm_32 = 501 + + VLD3LNdAsm_8 = 502 + + VLD3LNdWB_fixed_Asm_16 = 503 + + VLD3LNdWB_fixed_Asm_32 = 504 + + VLD3LNdWB_fixed_Asm_8 = 505 + + VLD3LNdWB_register_Asm_16 = 506 + + VLD3LNdWB_register_Asm_32 = 507 + + VLD3LNdWB_register_Asm_8 = 508 + + VLD3LNqAsm_16 = 509 + + VLD3LNqAsm_32 = 510 + + VLD3LNqWB_fixed_Asm_16 = 511 + + VLD3LNqWB_fixed_Asm_32 = 512 + + VLD3LNqWB_register_Asm_16 = 513 + + VLD3LNqWB_register_Asm_32 = 514 + + VLD3dAsm_16 = 515 + + VLD3dAsm_32 = 516 + + VLD3dAsm_8 = 517 + + VLD3dWB_fixed_Asm_16 = 518 + + VLD3dWB_fixed_Asm_32 = 519 + + VLD3dWB_fixed_Asm_8 = 520 + + VLD3dWB_register_Asm_16 = 521 + + VLD3dWB_register_Asm_32 = 522 + + VLD3dWB_register_Asm_8 = 523 + + VLD3qAsm_16 = 524 + + VLD3qAsm_32 = 525 + + VLD3qAsm_8 = 526 + + VLD3qWB_fixed_Asm_16 = 527 + + VLD3qWB_fixed_Asm_32 = 528 + + VLD3qWB_fixed_Asm_8 = 529 + + VLD3qWB_register_Asm_16 = 530 + + VLD3qWB_register_Asm_32 = 531 + + VLD3qWB_register_Asm_8 = 532 + + VLD4DUPdAsm_16 = 533 + + VLD4DUPdAsm_32 = 534 + + VLD4DUPdAsm_8 = 535 + + VLD4DUPdWB_fixed_Asm_16 = 536 + + VLD4DUPdWB_fixed_Asm_32 = 537 + + VLD4DUPdWB_fixed_Asm_8 = 538 + + VLD4DUPdWB_register_Asm_16 = 539 + + VLD4DUPdWB_register_Asm_32 = 540 + + VLD4DUPdWB_register_Asm_8 = 541 + + VLD4DUPqAsm_16 = 542 + + VLD4DUPqAsm_32 = 543 + + VLD4DUPqAsm_8 = 544 + + VLD4DUPqWB_fixed_Asm_16 = 545 + + VLD4DUPqWB_fixed_Asm_32 = 546 + + VLD4DUPqWB_fixed_Asm_8 = 547 + + VLD4DUPqWB_register_Asm_16 = 548 + + VLD4DUPqWB_register_Asm_32 = 549 + + VLD4DUPqWB_register_Asm_8 = 550 + + VLD4LNdAsm_16 = 551 + + VLD4LNdAsm_32 = 552 + + VLD4LNdAsm_8 = 553 + + VLD4LNdWB_fixed_Asm_16 = 554 + + VLD4LNdWB_fixed_Asm_32 = 555 + + VLD4LNdWB_fixed_Asm_8 = 556 + + VLD4LNdWB_register_Asm_16 = 557 + + VLD4LNdWB_register_Asm_32 = 558 + + VLD4LNdWB_register_Asm_8 = 559 + + VLD4LNqAsm_16 = 560 + + VLD4LNqAsm_32 = 561 + + VLD4LNqWB_fixed_Asm_16 = 562 + + VLD4LNqWB_fixed_Asm_32 = 563 + + VLD4LNqWB_register_Asm_16 = 564 + + VLD4LNqWB_register_Asm_32 = 565 + + VLD4dAsm_16 = 566 + + VLD4dAsm_32 = 567 + + VLD4dAsm_8 = 568 + + VLD4dWB_fixed_Asm_16 = 569 + + VLD4dWB_fixed_Asm_32 = 570 + + VLD4dWB_fixed_Asm_8 = 571 + + VLD4dWB_register_Asm_16 = 572 + + VLD4dWB_register_Asm_32 = 573 + + VLD4dWB_register_Asm_8 = 574 + + VLD4qAsm_16 = 575 + + VLD4qAsm_32 = 576 + + VLD4qAsm_8 = 577 + + VLD4qWB_fixed_Asm_16 = 578 + + VLD4qWB_fixed_Asm_32 = 579 + + VLD4qWB_fixed_Asm_8 = 580 + + VLD4qWB_register_Asm_16 = 581 + + VLD4qWB_register_Asm_32 = 582 + + VLD4qWB_register_Asm_8 = 583 + + VMOVD0 = 584 + + VMOVDcc = 585 + + VMOVHcc = 586 + + VMOVQ0 = 587 + + VMOVScc = 588 + + VST1LNdAsm_16 = 589 + + VST1LNdAsm_32 = 590 + + VST1LNdAsm_8 = 591 + + VST1LNdWB_fixed_Asm_16 = 592 + + VST1LNdWB_fixed_Asm_32 = 593 + + VST1LNdWB_fixed_Asm_8 = 594 + + VST1LNdWB_register_Asm_16 = 595 + + VST1LNdWB_register_Asm_32 = 596 + + VST1LNdWB_register_Asm_8 = 597 + + VST2LNdAsm_16 = 598 + + VST2LNdAsm_32 = 599 + + VST2LNdAsm_8 = 600 + + VST2LNdWB_fixed_Asm_16 = 601 + + VST2LNdWB_fixed_Asm_32 = 602 + + VST2LNdWB_fixed_Asm_8 = 603 + + VST2LNdWB_register_Asm_16 = 604 + + VST2LNdWB_register_Asm_32 = 605 + + VST2LNdWB_register_Asm_8 = 606 + + VST2LNqAsm_16 = 607 + + VST2LNqAsm_32 = 608 + + VST2LNqWB_fixed_Asm_16 = 609 + + VST2LNqWB_fixed_Asm_32 = 610 + + VST2LNqWB_register_Asm_16 = 611 + + VST2LNqWB_register_Asm_32 = 612 + + VST3LNdAsm_16 = 613 + + VST3LNdAsm_32 = 614 + + VST3LNdAsm_8 = 615 + + VST3LNdWB_fixed_Asm_16 = 616 + + VST3LNdWB_fixed_Asm_32 = 617 + + VST3LNdWB_fixed_Asm_8 = 618 + + VST3LNdWB_register_Asm_16 = 619 + + VST3LNdWB_register_Asm_32 = 620 + + VST3LNdWB_register_Asm_8 = 621 + + VST3LNqAsm_16 = 622 + + VST3LNqAsm_32 = 623 + + VST3LNqWB_fixed_Asm_16 = 624 + + VST3LNqWB_fixed_Asm_32 = 625 + + VST3LNqWB_register_Asm_16 = 626 + + VST3LNqWB_register_Asm_32 = 627 + + VST3dAsm_16 = 628 + + VST3dAsm_32 = 629 + + VST3dAsm_8 = 630 + + VST3dWB_fixed_Asm_16 = 631 + + VST3dWB_fixed_Asm_32 = 632 + + VST3dWB_fixed_Asm_8 = 633 + + VST3dWB_register_Asm_16 = 634 + + VST3dWB_register_Asm_32 = 635 + + VST3dWB_register_Asm_8 = 636 + + VST3qAsm_16 = 637 + + VST3qAsm_32 = 638 + + VST3qAsm_8 = 639 + + VST3qWB_fixed_Asm_16 = 640 + + VST3qWB_fixed_Asm_32 = 641 + + VST3qWB_fixed_Asm_8 = 642 + + VST3qWB_register_Asm_16 = 643 + + VST3qWB_register_Asm_32 = 644 + + VST3qWB_register_Asm_8 = 645 + + VST4LNdAsm_16 = 646 + + VST4LNdAsm_32 = 647 + + VST4LNdAsm_8 = 648 + + VST4LNdWB_fixed_Asm_16 = 649 + + VST4LNdWB_fixed_Asm_32 = 650 + + VST4LNdWB_fixed_Asm_8 = 651 + + VST4LNdWB_register_Asm_16 = 652 + + VST4LNdWB_register_Asm_32 = 653 + + VST4LNdWB_register_Asm_8 = 654 + + VST4LNqAsm_16 = 655 + + VST4LNqAsm_32 = 656 + + VST4LNqWB_fixed_Asm_16 = 657 + + VST4LNqWB_fixed_Asm_32 = 658 + + VST4LNqWB_register_Asm_16 = 659 + + VST4LNqWB_register_Asm_32 = 660 + + VST4dAsm_16 = 661 + + VST4dAsm_32 = 662 + + VST4dAsm_8 = 663 + + VST4dWB_fixed_Asm_16 = 664 + + VST4dWB_fixed_Asm_32 = 665 + + VST4dWB_fixed_Asm_8 = 666 + + VST4dWB_register_Asm_16 = 667 + + VST4dWB_register_Asm_32 = 668 + + VST4dWB_register_Asm_8 = 669 + + VST4qAsm_16 = 670 + + VST4qAsm_32 = 671 + + VST4qAsm_8 = 672 + + VST4qWB_fixed_Asm_16 = 673 + + VST4qWB_fixed_Asm_32 = 674 + + VST4qWB_fixed_Asm_8 = 675 + + VST4qWB_register_Asm_16 = 676 + + VST4qWB_register_Asm_32 = 677 + + VST4qWB_register_Asm_8 = 678 + + WIN__CHKSTK = 679 + + WIN__DBZCHK = 680 + + t2ADDSri = 681 + + t2ADDSrr = 682 + + t2ADDSrs = 683 + + t2BF_LabelPseudo = 684 + + t2BR_JT = 685 + + t2CALL_BTI = 686 + + t2DoLoopStart = 687 + + t2DoLoopStartTP = 688 + + t2LDMIA_RET = 689 + + t2LDRB_OFFSET_imm = 690 + + t2LDRB_POST_imm = 691 + + t2LDRB_PRE_imm = 692 + + t2LDRBpcrel = 693 + + t2LDRConstPool = 694 + + t2LDRH_OFFSET_imm = 695 + + t2LDRH_POST_imm = 696 + + t2LDRH_PRE_imm = 697 + + t2LDRHpcrel = 698 + + t2LDRLIT_ga_pcrel = 699 + + t2LDRSB_OFFSET_imm = 700 + + t2LDRSB_POST_imm = 701 + + t2LDRSB_PRE_imm = 702 + + t2LDRSBpcrel = 703 + + t2LDRSH_OFFSET_imm = 704 + + t2LDRSH_POST_imm = 705 + + t2LDRSH_PRE_imm = 706 + + t2LDRSHpcrel = 707 + + t2LDR_POST_imm = 708 + + t2LDR_PRE_imm = 709 + + t2LDRpci_pic = 710 + + t2LDRpcrel = 711 + + t2LEApcrel = 712 + + t2LEApcrelJT = 713 + + t2LoopDec = 714 + + t2LoopEnd = 715 + + t2LoopEndDec = 716 + + t2MOVCCasr = 717 + + t2MOVCCi = 718 + + t2MOVCCi16 = 719 + + t2MOVCCi32imm = 720 + + t2MOVCClsl = 721 + + t2MOVCClsr = 722 + + t2MOVCCr = 723 + + t2MOVCCror = 724 + + t2MOVSsi = 725 + + t2MOVSsr = 726 + + t2MOVTi16_ga_pcrel = 727 + + t2MOV_ga_pcrel = 728 + + t2MOVi16_ga_pcrel = 729 + + t2MOVi32imm = 730 + + t2MOVsi = 731 + + t2MOVsr = 732 + + t2MVNCCi = 733 + + t2RSBSri = 734 + + t2RSBSrs = 735 + + t2STRB_OFFSET_imm = 736 + + t2STRB_POST_imm = 737 + + t2STRB_PRE_imm = 738 + + t2STRB_preidx = 739 + + t2STRH_OFFSET_imm = 740 + + t2STRH_POST_imm = 741 + + t2STRH_PRE_imm = 742 + + t2STRH_preidx = 743 + + t2STR_POST_imm = 744 + + t2STR_PRE_imm = 745 + + t2STR_preidx = 746 + + t2SUBSri = 747 + + t2SUBSrr = 748 + + t2SUBSrs = 749 + + t2SpeculationBarrierISBDSBEndBB = 750 + + t2SpeculationBarrierSBEndBB = 751 + + t2TBB_JT = 752 + + t2TBH_JT = 753 + + t2WhileLoopSetup = 754 + + t2WhileLoopStart = 755 + + t2WhileLoopStartLR = 756 + + t2WhileLoopStartTP = 757 + + tADCS = 758 + + tADDSi3 = 759 + + tADDSi8 = 760 + + tADDSrr = 761 + + tADDframe = 762 + + tADJCALLSTACKDOWN = 763 + + tADJCALLSTACKUP = 764 + + tBLXNS_CALL = 765 + + tBLXr_noip = 766 + + tBL_PUSHLR = 767 + + tBRIND = 768 + + tBR_JTr = 769 + + tBXNS_RET = 770 + + tBX_CALL = 771 + + tBX_RET = 772 + + tBX_RET_vararg = 773 + + tBfar = 774 + + tCMP_SWAP_16 = 775 + + tCMP_SWAP_32 = 776 + + tCMP_SWAP_8 = 777 + + tLDMIA_UPD = 778 + + tLDRConstPool = 779 + + tLDRLIT_ga_abs = 780 + + tLDRLIT_ga_pcrel = 781 + + tLDR_postidx = 782 + + tLDRpci_pic = 783 + + tLEApcrel = 784 + + tLEApcrelJT = 785 + + tLSLSri = 786 + + tMOVCCr_pseudo = 787 + + tMOVi32imm = 788 + + tPOP_RET = 789 + + tRSBS = 790 + + tSBCS = 791 + + tSUBSi3 = 792 + + tSUBSi8 = 793 + + tSUBSrr = 794 + + tTAILJMPd = 795 + + tTAILJMPdND = 796 + + tTAILJMPr = 797 + + tTBB_JT = 798 + + tTBH_JT = 799 + + tTPsoft = 800 + + ADCri = 801 + + ADCrr = 802 + + ADCrsi = 803 + + ADCrsr = 804 + + ADDri = 805 + + ADDrr = 806 + + ADDrsi = 807 + + ADDrsr = 808 + + ADR = 809 + + AESD = 810 + + AESE = 811 + + AESIMC = 812 + + AESMC = 813 + + ANDri = 814 + + ANDrr = 815 + + ANDrsi = 816 + + ANDrsr = 817 + + BF16VDOTI_VDOTD = 818 + + BF16VDOTI_VDOTQ = 819 + + BF16VDOTS_VDOTD = 820 + + BF16VDOTS_VDOTQ = 821 + + BF16_VCVT = 822 + + BF16_VCVTB = 823 + + BF16_VCVTT = 824 + + BFC = 825 + + BFI = 826 + + BICri = 827 + + BICrr = 828 + + BICrsi = 829 + + BICrsr = 830 + + BKPT = 831 + + BL = 832 + + BLX = 833 + + BLX_pred = 834 + + BLXi = 835 + + BL_pred = 836 + + BX = 837 + + BXJ = 838 + + BX_RET = 839 + + BX_pred = 840 + + Bcc = 841 + + CDE_CX1 = 842 + + CDE_CX1A = 843 + + CDE_CX1D = 844 + + CDE_CX1DA = 845 + + CDE_CX2 = 846 + + CDE_CX2A = 847 + + CDE_CX2D = 848 + + CDE_CX2DA = 849 + + CDE_CX3 = 850 + + CDE_CX3A = 851 + + CDE_CX3D = 852 + + CDE_CX3DA = 853 + + CDE_VCX1A_fpdp = 854 + + CDE_VCX1A_fpsp = 855 + + CDE_VCX1A_vec = 856 + + CDE_VCX1_fpdp = 857 + + CDE_VCX1_fpsp = 858 + + CDE_VCX1_vec = 859 + + CDE_VCX2A_fpdp = 860 + + CDE_VCX2A_fpsp = 861 + + CDE_VCX2A_vec = 862 + + CDE_VCX2_fpdp = 863 + + CDE_VCX2_fpsp = 864 + + CDE_VCX2_vec = 865 + + CDE_VCX3A_fpdp = 866 + + CDE_VCX3A_fpsp = 867 + + CDE_VCX3A_vec = 868 + + CDE_VCX3_fpdp = 869 + + CDE_VCX3_fpsp = 870 + + CDE_VCX3_vec = 871 + + CDP = 872 + + CDP2 = 873 + + CLREX = 874 + + CLZ = 875 + + CMNri = 876 + + CMNzrr = 877 + + CMNzrsi = 878 + + CMNzrsr = 879 + + CMPri = 880 + + CMPrr = 881 + + CMPrsi = 882 + + CMPrsr = 883 + + CPS1p = 884 + + CPS2p = 885 + + CPS3p = 886 + + CRC32B = 887 + + CRC32CB = 888 + + CRC32CH = 889 + + CRC32CW = 890 + + CRC32H = 891 + + CRC32W = 892 + + DBG = 893 + + DMB = 894 + + DSB = 895 + + EORri = 896 + + EORrr = 897 + + EORrsi = 898 + + EORrsr = 899 + + ERET = 900 + + FCONSTD = 901 + + FCONSTH = 902 + + FCONSTS = 903 + + FLDMXDB_UPD = 904 + + FLDMXIA = 905 + + FLDMXIA_UPD = 906 + + FMSTAT = 907 + + FSTMXDB_UPD = 908 + + FSTMXIA = 909 + + FSTMXIA_UPD = 910 + + HINT = 911 + + HLT = 912 + + HVC = 913 + + ISB = 914 + + LDA = 915 + + LDAB = 916 + + LDAEX = 917 + + LDAEXB = 918 + + LDAEXD = 919 + + LDAEXH = 920 + + LDAH = 921 + + LDC2L_OFFSET = 922 + + LDC2L_OPTION = 923 + + LDC2L_POST = 924 + + LDC2L_PRE = 925 + + LDC2_OFFSET = 926 + + LDC2_OPTION = 927 + + LDC2_POST = 928 + + LDC2_PRE = 929 + + LDCL_OFFSET = 930 + + LDCL_OPTION = 931 + + LDCL_POST = 932 + + LDCL_PRE = 933 + + LDC_OFFSET = 934 + + LDC_OPTION = 935 + + LDC_POST = 936 + + LDC_PRE = 937 + + LDMDA = 938 + + LDMDA_UPD = 939 + + LDMDB = 940 + + LDMDB_UPD = 941 + + LDMIA = 942 + + LDMIA_UPD = 943 + + LDMIB = 944 + + LDMIB_UPD = 945 + + LDRBT_POST_IMM = 946 + + LDRBT_POST_REG = 947 + + LDRB_POST_IMM = 948 + + LDRB_POST_REG = 949 + + LDRB_PRE_IMM = 950 + + LDRB_PRE_REG = 951 + + LDRBi12 = 952 + + LDRBrs = 953 + + LDRD = 954 + + LDRD_POST = 955 + + LDRD_PRE = 956 + + LDREX = 957 + + LDREXB = 958 + + LDREXD = 959 + + LDREXH = 960 + + LDRH = 961 + + LDRHTi = 962 + + LDRHTr = 963 + + LDRH_POST = 964 + + LDRH_PRE = 965 + + LDRSB = 966 + + LDRSBTi = 967 + + LDRSBTr = 968 + + LDRSB_POST = 969 + + LDRSB_PRE = 970 + + LDRSH = 971 + + LDRSHTi = 972 + + LDRSHTr = 973 + + LDRSH_POST = 974 + + LDRSH_PRE = 975 + + LDRT_POST_IMM = 976 + + LDRT_POST_REG = 977 + + LDR_POST_IMM = 978 + + LDR_POST_REG = 979 + + LDR_PRE_IMM = 980 + + LDR_PRE_REG = 981 + + LDRcp = 982 + + LDRi12 = 983 + + LDRrs = 984 + + MCR = 985 + + MCR2 = 986 + + MCRR = 987 + + MCRR2 = 988 + + MLA = 989 + + MLS = 990 + + MOVPCLR = 991 + + MOVTi16 = 992 + + MOVi = 993 + + MOVi16 = 994 + + MOVr = 995 + + MOVr_TC = 996 + + MOVsi = 997 + + MOVsr = 998 + + MRC = 999 + + MRC2 = 1000 + + MRRC = 1001 + + MRRC2 = 1002 + + MRS = 1003 + + MRSbanked = 1004 + + MRSsys = 1005 + + MSR = 1006 + + MSRbanked = 1007 + + MSRi = 1008 + + MUL = 1009 + + MVE_ASRLi = 1010 + + MVE_ASRLr = 1011 + + MVE_DLSTP_16 = 1012 + + MVE_DLSTP_32 = 1013 + + MVE_DLSTP_64 = 1014 + + MVE_DLSTP_8 = 1015 + + MVE_LCTP = 1016 + + MVE_LETP = 1017 + + MVE_LSLLi = 1018 + + MVE_LSLLr = 1019 + + MVE_LSRL = 1020 + + MVE_SQRSHR = 1021 + + MVE_SQRSHRL = 1022 + + MVE_SQSHL = 1023 + + MVE_SQSHLL = 1024 + + MVE_SRSHR = 1025 + + MVE_SRSHRL = 1026 + + MVE_UQRSHL = 1027 + + MVE_UQRSHLL = 1028 + + MVE_UQSHL = 1029 + + MVE_UQSHLL = 1030 + + MVE_URSHR = 1031 + + MVE_URSHRL = 1032 + + MVE_VABAVs16 = 1033 + + MVE_VABAVs32 = 1034 + + MVE_VABAVs8 = 1035 + + MVE_VABAVu16 = 1036 + + MVE_VABAVu32 = 1037 + + MVE_VABAVu8 = 1038 + + MVE_VABDf16 = 1039 + + MVE_VABDf32 = 1040 + + MVE_VABDs16 = 1041 + + MVE_VABDs32 = 1042 + + MVE_VABDs8 = 1043 + + MVE_VABDu16 = 1044 + + MVE_VABDu32 = 1045 + + MVE_VABDu8 = 1046 + + MVE_VABSf16 = 1047 + + MVE_VABSf32 = 1048 + + MVE_VABSs16 = 1049 + + MVE_VABSs32 = 1050 + + MVE_VABSs8 = 1051 + + MVE_VADC = 1052 + + MVE_VADCI = 1053 + + MVE_VADDLVs32acc = 1054 + + MVE_VADDLVs32no_acc = 1055 + + MVE_VADDLVu32acc = 1056 + + MVE_VADDLVu32no_acc = 1057 + + MVE_VADDVs16acc = 1058 + + MVE_VADDVs16no_acc = 1059 + + MVE_VADDVs32acc = 1060 + + MVE_VADDVs32no_acc = 1061 + + MVE_VADDVs8acc = 1062 + + MVE_VADDVs8no_acc = 1063 + + MVE_VADDVu16acc = 1064 + + MVE_VADDVu16no_acc = 1065 + + MVE_VADDVu32acc = 1066 + + MVE_VADDVu32no_acc = 1067 + + MVE_VADDVu8acc = 1068 + + MVE_VADDVu8no_acc = 1069 + + MVE_VADD_qr_f16 = 1070 + + MVE_VADD_qr_f32 = 1071 + + MVE_VADD_qr_i16 = 1072 + + MVE_VADD_qr_i32 = 1073 + + MVE_VADD_qr_i8 = 1074 + + MVE_VADDf16 = 1075 + + MVE_VADDf32 = 1076 + + MVE_VADDi16 = 1077 + + MVE_VADDi32 = 1078 + + MVE_VADDi8 = 1079 + + MVE_VAND = 1080 + + MVE_VBIC = 1081 + + MVE_VBICimmi16 = 1082 + + MVE_VBICimmi32 = 1083 + + MVE_VBRSR16 = 1084 + + MVE_VBRSR32 = 1085 + + MVE_VBRSR8 = 1086 + + MVE_VCADDf16 = 1087 + + MVE_VCADDf32 = 1088 + + MVE_VCADDi16 = 1089 + + MVE_VCADDi32 = 1090 + + MVE_VCADDi8 = 1091 + + MVE_VCLSs16 = 1092 + + MVE_VCLSs32 = 1093 + + MVE_VCLSs8 = 1094 + + MVE_VCLZs16 = 1095 + + MVE_VCLZs32 = 1096 + + MVE_VCLZs8 = 1097 + + MVE_VCMLAf16 = 1098 + + MVE_VCMLAf32 = 1099 + + MVE_VCMPf16 = 1100 + + MVE_VCMPf16r = 1101 + + MVE_VCMPf32 = 1102 + + MVE_VCMPf32r = 1103 + + MVE_VCMPi16 = 1104 + + MVE_VCMPi16r = 1105 + + MVE_VCMPi32 = 1106 + + MVE_VCMPi32r = 1107 + + MVE_VCMPi8 = 1108 + + MVE_VCMPi8r = 1109 + + MVE_VCMPs16 = 1110 + + MVE_VCMPs16r = 1111 + + MVE_VCMPs32 = 1112 + + MVE_VCMPs32r = 1113 + + MVE_VCMPs8 = 1114 + + MVE_VCMPs8r = 1115 + + MVE_VCMPu16 = 1116 + + MVE_VCMPu16r = 1117 + + MVE_VCMPu32 = 1118 + + MVE_VCMPu32r = 1119 + + MVE_VCMPu8 = 1120 + + MVE_VCMPu8r = 1121 + + MVE_VCMULf16 = 1122 + + MVE_VCMULf32 = 1123 + + MVE_VCTP16 = 1124 + + MVE_VCTP32 = 1125 + + MVE_VCTP64 = 1126 + + MVE_VCTP8 = 1127 + + MVE_VCVTf16f32bh = 1128 + + MVE_VCVTf16f32th = 1129 + + MVE_VCVTf16s16_fix = 1130 + + MVE_VCVTf16s16n = 1131 + + MVE_VCVTf16u16_fix = 1132 + + MVE_VCVTf16u16n = 1133 + + MVE_VCVTf32f16bh = 1134 + + MVE_VCVTf32f16th = 1135 + + MVE_VCVTf32s32_fix = 1136 + + MVE_VCVTf32s32n = 1137 + + MVE_VCVTf32u32_fix = 1138 + + MVE_VCVTf32u32n = 1139 + + MVE_VCVTs16f16_fix = 1140 + + MVE_VCVTs16f16a = 1141 + + MVE_VCVTs16f16m = 1142 + + MVE_VCVTs16f16n = 1143 + + MVE_VCVTs16f16p = 1144 + + MVE_VCVTs16f16z = 1145 + + MVE_VCVTs32f32_fix = 1146 + + MVE_VCVTs32f32a = 1147 + + MVE_VCVTs32f32m = 1148 + + MVE_VCVTs32f32n = 1149 + + MVE_VCVTs32f32p = 1150 + + MVE_VCVTs32f32z = 1151 + + MVE_VCVTu16f16_fix = 1152 + + MVE_VCVTu16f16a = 1153 + + MVE_VCVTu16f16m = 1154 + + MVE_VCVTu16f16n = 1155 + + MVE_VCVTu16f16p = 1156 + + MVE_VCVTu16f16z = 1157 + + MVE_VCVTu32f32_fix = 1158 + + MVE_VCVTu32f32a = 1159 + + MVE_VCVTu32f32m = 1160 + + MVE_VCVTu32f32n = 1161 + + MVE_VCVTu32f32p = 1162 + + MVE_VCVTu32f32z = 1163 + + MVE_VDDUPu16 = 1164 + + MVE_VDDUPu32 = 1165 + + MVE_VDDUPu8 = 1166 + + MVE_VDUP16 = 1167 + + MVE_VDUP32 = 1168 + + MVE_VDUP8 = 1169 + + MVE_VDWDUPu16 = 1170 + + MVE_VDWDUPu32 = 1171 + + MVE_VDWDUPu8 = 1172 + + MVE_VEOR = 1173 + + MVE_VFMA_qr_Sf16 = 1174 + + MVE_VFMA_qr_Sf32 = 1175 + + MVE_VFMA_qr_f16 = 1176 + + MVE_VFMA_qr_f32 = 1177 + + MVE_VFMAf16 = 1178 + + MVE_VFMAf32 = 1179 + + MVE_VFMSf16 = 1180 + + MVE_VFMSf32 = 1181 + + MVE_VHADD_qr_s16 = 1182 + + MVE_VHADD_qr_s32 = 1183 + + MVE_VHADD_qr_s8 = 1184 + + MVE_VHADD_qr_u16 = 1185 + + MVE_VHADD_qr_u32 = 1186 + + MVE_VHADD_qr_u8 = 1187 + + MVE_VHADDs16 = 1188 + + MVE_VHADDs32 = 1189 + + MVE_VHADDs8 = 1190 + + MVE_VHADDu16 = 1191 + + MVE_VHADDu32 = 1192 + + MVE_VHADDu8 = 1193 + + MVE_VHCADDs16 = 1194 + + MVE_VHCADDs32 = 1195 + + MVE_VHCADDs8 = 1196 + + MVE_VHSUB_qr_s16 = 1197 + + MVE_VHSUB_qr_s32 = 1198 + + MVE_VHSUB_qr_s8 = 1199 + + MVE_VHSUB_qr_u16 = 1200 + + MVE_VHSUB_qr_u32 = 1201 + + MVE_VHSUB_qr_u8 = 1202 + + MVE_VHSUBs16 = 1203 + + MVE_VHSUBs32 = 1204 + + MVE_VHSUBs8 = 1205 + + MVE_VHSUBu16 = 1206 + + MVE_VHSUBu32 = 1207 + + MVE_VHSUBu8 = 1208 + + MVE_VIDUPu16 = 1209 + + MVE_VIDUPu32 = 1210 + + MVE_VIDUPu8 = 1211 + + MVE_VIWDUPu16 = 1212 + + MVE_VIWDUPu32 = 1213 + + MVE_VIWDUPu8 = 1214 + + MVE_VLD20_16 = 1215 + + MVE_VLD20_16_wb = 1216 + + MVE_VLD20_32 = 1217 + + MVE_VLD20_32_wb = 1218 + + MVE_VLD20_8 = 1219 + + MVE_VLD20_8_wb = 1220 + + MVE_VLD21_16 = 1221 + + MVE_VLD21_16_wb = 1222 + + MVE_VLD21_32 = 1223 + + MVE_VLD21_32_wb = 1224 + + MVE_VLD21_8 = 1225 + + MVE_VLD21_8_wb = 1226 + + MVE_VLD40_16 = 1227 + + MVE_VLD40_16_wb = 1228 + + MVE_VLD40_32 = 1229 + + MVE_VLD40_32_wb = 1230 + + MVE_VLD40_8 = 1231 + + MVE_VLD40_8_wb = 1232 + + MVE_VLD41_16 = 1233 + + MVE_VLD41_16_wb = 1234 + + MVE_VLD41_32 = 1235 + + MVE_VLD41_32_wb = 1236 + + MVE_VLD41_8 = 1237 + + MVE_VLD41_8_wb = 1238 + + MVE_VLD42_16 = 1239 + + MVE_VLD42_16_wb = 1240 + + MVE_VLD42_32 = 1241 + + MVE_VLD42_32_wb = 1242 + + MVE_VLD42_8 = 1243 + + MVE_VLD42_8_wb = 1244 + + MVE_VLD43_16 = 1245 + + MVE_VLD43_16_wb = 1246 + + MVE_VLD43_32 = 1247 + + MVE_VLD43_32_wb = 1248 + + MVE_VLD43_8 = 1249 + + MVE_VLD43_8_wb = 1250 + + MVE_VLDRBS16 = 1251 + + MVE_VLDRBS16_post = 1252 + + MVE_VLDRBS16_pre = 1253 + + MVE_VLDRBS16_rq = 1254 + + MVE_VLDRBS32 = 1255 + + MVE_VLDRBS32_post = 1256 + + MVE_VLDRBS32_pre = 1257 + + MVE_VLDRBS32_rq = 1258 + + MVE_VLDRBU16 = 1259 + + MVE_VLDRBU16_post = 1260 + + MVE_VLDRBU16_pre = 1261 + + MVE_VLDRBU16_rq = 1262 + + MVE_VLDRBU32 = 1263 + + MVE_VLDRBU32_post = 1264 + + MVE_VLDRBU32_pre = 1265 + + MVE_VLDRBU32_rq = 1266 + + MVE_VLDRBU8 = 1267 + + MVE_VLDRBU8_post = 1268 + + MVE_VLDRBU8_pre = 1269 + + MVE_VLDRBU8_rq = 1270 + + MVE_VLDRDU64_qi = 1271 + + MVE_VLDRDU64_qi_pre = 1272 + + MVE_VLDRDU64_rq = 1273 + + MVE_VLDRDU64_rq_u = 1274 + + MVE_VLDRHS32 = 1275 + + MVE_VLDRHS32_post = 1276 + + MVE_VLDRHS32_pre = 1277 + + MVE_VLDRHS32_rq = 1278 + + MVE_VLDRHS32_rq_u = 1279 + + MVE_VLDRHU16 = 1280 + + MVE_VLDRHU16_post = 1281 + + MVE_VLDRHU16_pre = 1282 + + MVE_VLDRHU16_rq = 1283 + + MVE_VLDRHU16_rq_u = 1284 + + MVE_VLDRHU32 = 1285 + + MVE_VLDRHU32_post = 1286 + + MVE_VLDRHU32_pre = 1287 + + MVE_VLDRHU32_rq = 1288 + + MVE_VLDRHU32_rq_u = 1289 + + MVE_VLDRWU32 = 1290 + + MVE_VLDRWU32_post = 1291 + + MVE_VLDRWU32_pre = 1292 + + MVE_VLDRWU32_qi = 1293 + + MVE_VLDRWU32_qi_pre = 1294 + + MVE_VLDRWU32_rq = 1295 + + MVE_VLDRWU32_rq_u = 1296 + + MVE_VMAXAVs16 = 1297 + + MVE_VMAXAVs32 = 1298 + + MVE_VMAXAVs8 = 1299 + + MVE_VMAXAs16 = 1300 + + MVE_VMAXAs32 = 1301 + + MVE_VMAXAs8 = 1302 + + MVE_VMAXNMAVf16 = 1303 + + MVE_VMAXNMAVf32 = 1304 + + MVE_VMAXNMAf16 = 1305 + + MVE_VMAXNMAf32 = 1306 + + MVE_VMAXNMVf16 = 1307 + + MVE_VMAXNMVf32 = 1308 + + MVE_VMAXNMf16 = 1309 + + MVE_VMAXNMf32 = 1310 + + MVE_VMAXVs16 = 1311 + + MVE_VMAXVs32 = 1312 + + MVE_VMAXVs8 = 1313 + + MVE_VMAXVu16 = 1314 + + MVE_VMAXVu32 = 1315 + + MVE_VMAXVu8 = 1316 + + MVE_VMAXs16 = 1317 + + MVE_VMAXs32 = 1318 + + MVE_VMAXs8 = 1319 + + MVE_VMAXu16 = 1320 + + MVE_VMAXu32 = 1321 + + MVE_VMAXu8 = 1322 + + MVE_VMINAVs16 = 1323 + + MVE_VMINAVs32 = 1324 + + MVE_VMINAVs8 = 1325 + + MVE_VMINAs16 = 1326 + + MVE_VMINAs32 = 1327 + + MVE_VMINAs8 = 1328 + + MVE_VMINNMAVf16 = 1329 + + MVE_VMINNMAVf32 = 1330 + + MVE_VMINNMAf16 = 1331 + + MVE_VMINNMAf32 = 1332 + + MVE_VMINNMVf16 = 1333 + + MVE_VMINNMVf32 = 1334 + + MVE_VMINNMf16 = 1335 + + MVE_VMINNMf32 = 1336 + + MVE_VMINVs16 = 1337 + + MVE_VMINVs32 = 1338 + + MVE_VMINVs8 = 1339 + + MVE_VMINVu16 = 1340 + + MVE_VMINVu32 = 1341 + + MVE_VMINVu8 = 1342 + + MVE_VMINs16 = 1343 + + MVE_VMINs32 = 1344 + + MVE_VMINs8 = 1345 + + MVE_VMINu16 = 1346 + + MVE_VMINu32 = 1347 + + MVE_VMINu8 = 1348 + + MVE_VMLADAVas16 = 1349 + + MVE_VMLADAVas32 = 1350 + + MVE_VMLADAVas8 = 1351 + + MVE_VMLADAVau16 = 1352 + + MVE_VMLADAVau32 = 1353 + + MVE_VMLADAVau8 = 1354 + + MVE_VMLADAVaxs16 = 1355 + + MVE_VMLADAVaxs32 = 1356 + + MVE_VMLADAVaxs8 = 1357 + + MVE_VMLADAVs16 = 1358 + + MVE_VMLADAVs32 = 1359 + + MVE_VMLADAVs8 = 1360 + + MVE_VMLADAVu16 = 1361 + + MVE_VMLADAVu32 = 1362 + + MVE_VMLADAVu8 = 1363 + + MVE_VMLADAVxs16 = 1364 + + MVE_VMLADAVxs32 = 1365 + + MVE_VMLADAVxs8 = 1366 + + MVE_VMLALDAVas16 = 1367 + + MVE_VMLALDAVas32 = 1368 + + MVE_VMLALDAVau16 = 1369 + + MVE_VMLALDAVau32 = 1370 + + MVE_VMLALDAVaxs16 = 1371 + + MVE_VMLALDAVaxs32 = 1372 + + MVE_VMLALDAVs16 = 1373 + + MVE_VMLALDAVs32 = 1374 + + MVE_VMLALDAVu16 = 1375 + + MVE_VMLALDAVu32 = 1376 + + MVE_VMLALDAVxs16 = 1377 + + MVE_VMLALDAVxs32 = 1378 + + MVE_VMLAS_qr_i16 = 1379 + + MVE_VMLAS_qr_i32 = 1380 + + MVE_VMLAS_qr_i8 = 1381 + + MVE_VMLA_qr_i16 = 1382 + + MVE_VMLA_qr_i32 = 1383 + + MVE_VMLA_qr_i8 = 1384 + + MVE_VMLSDAVas16 = 1385 + + MVE_VMLSDAVas32 = 1386 + + MVE_VMLSDAVas8 = 1387 + + MVE_VMLSDAVaxs16 = 1388 + + MVE_VMLSDAVaxs32 = 1389 + + MVE_VMLSDAVaxs8 = 1390 + + MVE_VMLSDAVs16 = 1391 + + MVE_VMLSDAVs32 = 1392 + + MVE_VMLSDAVs8 = 1393 + + MVE_VMLSDAVxs16 = 1394 + + MVE_VMLSDAVxs32 = 1395 + + MVE_VMLSDAVxs8 = 1396 + + MVE_VMLSLDAVas16 = 1397 + + MVE_VMLSLDAVas32 = 1398 + + MVE_VMLSLDAVaxs16 = 1399 + + MVE_VMLSLDAVaxs32 = 1400 + + MVE_VMLSLDAVs16 = 1401 + + MVE_VMLSLDAVs32 = 1402 + + MVE_VMLSLDAVxs16 = 1403 + + MVE_VMLSLDAVxs32 = 1404 + + MVE_VMOVLs16bh = 1405 + + MVE_VMOVLs16th = 1406 + + MVE_VMOVLs8bh = 1407 + + MVE_VMOVLs8th = 1408 + + MVE_VMOVLu16bh = 1409 + + MVE_VMOVLu16th = 1410 + + MVE_VMOVLu8bh = 1411 + + MVE_VMOVLu8th = 1412 + + MVE_VMOVNi16bh = 1413 + + MVE_VMOVNi16th = 1414 + + MVE_VMOVNi32bh = 1415 + + MVE_VMOVNi32th = 1416 + + MVE_VMOV_from_lane_32 = 1417 + + MVE_VMOV_from_lane_s16 = 1418 + + MVE_VMOV_from_lane_s8 = 1419 + + MVE_VMOV_from_lane_u16 = 1420 + + MVE_VMOV_from_lane_u8 = 1421 + + MVE_VMOV_q_rr = 1422 + + MVE_VMOV_rr_q = 1423 + + MVE_VMOV_to_lane_16 = 1424 + + MVE_VMOV_to_lane_32 = 1425 + + MVE_VMOV_to_lane_8 = 1426 + + MVE_VMOVimmf32 = 1427 + + MVE_VMOVimmi16 = 1428 + + MVE_VMOVimmi32 = 1429 + + MVE_VMOVimmi64 = 1430 + + MVE_VMOVimmi8 = 1431 + + MVE_VMULHs16 = 1432 + + MVE_VMULHs32 = 1433 + + MVE_VMULHs8 = 1434 + + MVE_VMULHu16 = 1435 + + MVE_VMULHu32 = 1436 + + MVE_VMULHu8 = 1437 + + MVE_VMULLBp16 = 1438 + + MVE_VMULLBp8 = 1439 + + MVE_VMULLBs16 = 1440 + + MVE_VMULLBs32 = 1441 + + MVE_VMULLBs8 = 1442 + + MVE_VMULLBu16 = 1443 + + MVE_VMULLBu32 = 1444 + + MVE_VMULLBu8 = 1445 + + MVE_VMULLTp16 = 1446 + + MVE_VMULLTp8 = 1447 + + MVE_VMULLTs16 = 1448 + + MVE_VMULLTs32 = 1449 + + MVE_VMULLTs8 = 1450 + + MVE_VMULLTu16 = 1451 + + MVE_VMULLTu32 = 1452 + + MVE_VMULLTu8 = 1453 + + MVE_VMUL_qr_f16 = 1454 + + MVE_VMUL_qr_f32 = 1455 + + MVE_VMUL_qr_i16 = 1456 + + MVE_VMUL_qr_i32 = 1457 + + MVE_VMUL_qr_i8 = 1458 + + MVE_VMULf16 = 1459 + + MVE_VMULf32 = 1460 + + MVE_VMULi16 = 1461 + + MVE_VMULi32 = 1462 + + MVE_VMULi8 = 1463 + + MVE_VMVN = 1464 + + MVE_VMVNimmi16 = 1465 + + MVE_VMVNimmi32 = 1466 + + MVE_VNEGf16 = 1467 + + MVE_VNEGf32 = 1468 + + MVE_VNEGs16 = 1469 + + MVE_VNEGs32 = 1470 + + MVE_VNEGs8 = 1471 + + MVE_VORN = 1472 + + MVE_VORR = 1473 + + MVE_VORRimmi16 = 1474 + + MVE_VORRimmi32 = 1475 + + MVE_VPNOT = 1476 + + MVE_VPSEL = 1477 + + MVE_VPST = 1478 + + MVE_VPTv16i8 = 1479 + + MVE_VPTv16i8r = 1480 + + MVE_VPTv16s8 = 1481 + + MVE_VPTv16s8r = 1482 + + MVE_VPTv16u8 = 1483 + + MVE_VPTv16u8r = 1484 + + MVE_VPTv4f32 = 1485 + + MVE_VPTv4f32r = 1486 + + MVE_VPTv4i32 = 1487 + + MVE_VPTv4i32r = 1488 + + MVE_VPTv4s32 = 1489 + + MVE_VPTv4s32r = 1490 + + MVE_VPTv4u32 = 1491 + + MVE_VPTv4u32r = 1492 + + MVE_VPTv8f16 = 1493 + + MVE_VPTv8f16r = 1494 + + MVE_VPTv8i16 = 1495 + + MVE_VPTv8i16r = 1496 + + MVE_VPTv8s16 = 1497 + + MVE_VPTv8s16r = 1498 + + MVE_VPTv8u16 = 1499 + + MVE_VPTv8u16r = 1500 + + MVE_VQABSs16 = 1501 + + MVE_VQABSs32 = 1502 + + MVE_VQABSs8 = 1503 + + MVE_VQADD_qr_s16 = 1504 + + MVE_VQADD_qr_s32 = 1505 + + MVE_VQADD_qr_s8 = 1506 + + MVE_VQADD_qr_u16 = 1507 + + MVE_VQADD_qr_u32 = 1508 + + MVE_VQADD_qr_u8 = 1509 + + MVE_VQADDs16 = 1510 + + MVE_VQADDs32 = 1511 + + MVE_VQADDs8 = 1512 + + MVE_VQADDu16 = 1513 + + MVE_VQADDu32 = 1514 + + MVE_VQADDu8 = 1515 + + MVE_VQDMLADHXs16 = 1516 + + MVE_VQDMLADHXs32 = 1517 + + MVE_VQDMLADHXs8 = 1518 + + MVE_VQDMLADHs16 = 1519 + + MVE_VQDMLADHs32 = 1520 + + MVE_VQDMLADHs8 = 1521 + + MVE_VQDMLAH_qrs16 = 1522 + + MVE_VQDMLAH_qrs32 = 1523 + + MVE_VQDMLAH_qrs8 = 1524 + + MVE_VQDMLASH_qrs16 = 1525 + + MVE_VQDMLASH_qrs32 = 1526 + + MVE_VQDMLASH_qrs8 = 1527 + + MVE_VQDMLSDHXs16 = 1528 + + MVE_VQDMLSDHXs32 = 1529 + + MVE_VQDMLSDHXs8 = 1530 + + MVE_VQDMLSDHs16 = 1531 + + MVE_VQDMLSDHs32 = 1532 + + MVE_VQDMLSDHs8 = 1533 + + MVE_VQDMULH_qr_s16 = 1534 + + MVE_VQDMULH_qr_s32 = 1535 + + MVE_VQDMULH_qr_s8 = 1536 + + MVE_VQDMULHi16 = 1537 + + MVE_VQDMULHi32 = 1538 + + MVE_VQDMULHi8 = 1539 + + MVE_VQDMULL_qr_s16bh = 1540 + + MVE_VQDMULL_qr_s16th = 1541 + + MVE_VQDMULL_qr_s32bh = 1542 + + MVE_VQDMULL_qr_s32th = 1543 + + MVE_VQDMULLs16bh = 1544 + + MVE_VQDMULLs16th = 1545 + + MVE_VQDMULLs32bh = 1546 + + MVE_VQDMULLs32th = 1547 + + MVE_VQMOVNs16bh = 1548 + + MVE_VQMOVNs16th = 1549 + + MVE_VQMOVNs32bh = 1550 + + MVE_VQMOVNs32th = 1551 + + MVE_VQMOVNu16bh = 1552 + + MVE_VQMOVNu16th = 1553 + + MVE_VQMOVNu32bh = 1554 + + MVE_VQMOVNu32th = 1555 + + MVE_VQMOVUNs16bh = 1556 + + MVE_VQMOVUNs16th = 1557 + + MVE_VQMOVUNs32bh = 1558 + + MVE_VQMOVUNs32th = 1559 + + MVE_VQNEGs16 = 1560 + + MVE_VQNEGs32 = 1561 + + MVE_VQNEGs8 = 1562 + + MVE_VQRDMLADHXs16 = 1563 + + MVE_VQRDMLADHXs32 = 1564 + + MVE_VQRDMLADHXs8 = 1565 + + MVE_VQRDMLADHs16 = 1566 + + MVE_VQRDMLADHs32 = 1567 + + MVE_VQRDMLADHs8 = 1568 + + MVE_VQRDMLAH_qrs16 = 1569 + + MVE_VQRDMLAH_qrs32 = 1570 + + MVE_VQRDMLAH_qrs8 = 1571 + + MVE_VQRDMLASH_qrs16 = 1572 + + MVE_VQRDMLASH_qrs32 = 1573 + + MVE_VQRDMLASH_qrs8 = 1574 + + MVE_VQRDMLSDHXs16 = 1575 + + MVE_VQRDMLSDHXs32 = 1576 + + MVE_VQRDMLSDHXs8 = 1577 + + MVE_VQRDMLSDHs16 = 1578 + + MVE_VQRDMLSDHs32 = 1579 + + MVE_VQRDMLSDHs8 = 1580 + + MVE_VQRDMULH_qr_s16 = 1581 + + MVE_VQRDMULH_qr_s32 = 1582 + + MVE_VQRDMULH_qr_s8 = 1583 + + MVE_VQRDMULHi16 = 1584 + + MVE_VQRDMULHi32 = 1585 + + MVE_VQRDMULHi8 = 1586 + + MVE_VQRSHL_by_vecs16 = 1587 + + MVE_VQRSHL_by_vecs32 = 1588 + + MVE_VQRSHL_by_vecs8 = 1589 + + MVE_VQRSHL_by_vecu16 = 1590 + + MVE_VQRSHL_by_vecu32 = 1591 + + MVE_VQRSHL_by_vecu8 = 1592 + + MVE_VQRSHL_qrs16 = 1593 + + MVE_VQRSHL_qrs32 = 1594 + + MVE_VQRSHL_qrs8 = 1595 + + MVE_VQRSHL_qru16 = 1596 + + MVE_VQRSHL_qru32 = 1597 + + MVE_VQRSHL_qru8 = 1598 + + MVE_VQRSHRNbhs16 = 1599 + + MVE_VQRSHRNbhs32 = 1600 + + MVE_VQRSHRNbhu16 = 1601 + + MVE_VQRSHRNbhu32 = 1602 + + MVE_VQRSHRNths16 = 1603 + + MVE_VQRSHRNths32 = 1604 + + MVE_VQRSHRNthu16 = 1605 + + MVE_VQRSHRNthu32 = 1606 + + MVE_VQRSHRUNs16bh = 1607 + + MVE_VQRSHRUNs16th = 1608 + + MVE_VQRSHRUNs32bh = 1609 + + MVE_VQRSHRUNs32th = 1610 + + MVE_VQSHLU_imms16 = 1611 + + MVE_VQSHLU_imms32 = 1612 + + MVE_VQSHLU_imms8 = 1613 + + MVE_VQSHL_by_vecs16 = 1614 + + MVE_VQSHL_by_vecs32 = 1615 + + MVE_VQSHL_by_vecs8 = 1616 + + MVE_VQSHL_by_vecu16 = 1617 + + MVE_VQSHL_by_vecu32 = 1618 + + MVE_VQSHL_by_vecu8 = 1619 + + MVE_VQSHL_qrs16 = 1620 + + MVE_VQSHL_qrs32 = 1621 + + MVE_VQSHL_qrs8 = 1622 + + MVE_VQSHL_qru16 = 1623 + + MVE_VQSHL_qru32 = 1624 + + MVE_VQSHL_qru8 = 1625 + + MVE_VQSHLimms16 = 1626 + + MVE_VQSHLimms32 = 1627 + + MVE_VQSHLimms8 = 1628 + + MVE_VQSHLimmu16 = 1629 + + MVE_VQSHLimmu32 = 1630 + + MVE_VQSHLimmu8 = 1631 + + MVE_VQSHRNbhs16 = 1632 + + MVE_VQSHRNbhs32 = 1633 + + MVE_VQSHRNbhu16 = 1634 + + MVE_VQSHRNbhu32 = 1635 + + MVE_VQSHRNths16 = 1636 + + MVE_VQSHRNths32 = 1637 + + MVE_VQSHRNthu16 = 1638 + + MVE_VQSHRNthu32 = 1639 + + MVE_VQSHRUNs16bh = 1640 + + MVE_VQSHRUNs16th = 1641 + + MVE_VQSHRUNs32bh = 1642 + + MVE_VQSHRUNs32th = 1643 + + MVE_VQSUB_qr_s16 = 1644 + + MVE_VQSUB_qr_s32 = 1645 + + MVE_VQSUB_qr_s8 = 1646 + + MVE_VQSUB_qr_u16 = 1647 + + MVE_VQSUB_qr_u32 = 1648 + + MVE_VQSUB_qr_u8 = 1649 + + MVE_VQSUBs16 = 1650 + + MVE_VQSUBs32 = 1651 + + MVE_VQSUBs8 = 1652 + + MVE_VQSUBu16 = 1653 + + MVE_VQSUBu32 = 1654 + + MVE_VQSUBu8 = 1655 + + MVE_VREV16_8 = 1656 + + MVE_VREV32_16 = 1657 + + MVE_VREV32_8 = 1658 + + MVE_VREV64_16 = 1659 + + MVE_VREV64_32 = 1660 + + MVE_VREV64_8 = 1661 + + MVE_VRHADDs16 = 1662 + + MVE_VRHADDs32 = 1663 + + MVE_VRHADDs8 = 1664 + + MVE_VRHADDu16 = 1665 + + MVE_VRHADDu32 = 1666 + + MVE_VRHADDu8 = 1667 + + MVE_VRINTf16A = 1668 + + MVE_VRINTf16M = 1669 + + MVE_VRINTf16N = 1670 + + MVE_VRINTf16P = 1671 + + MVE_VRINTf16X = 1672 + + MVE_VRINTf16Z = 1673 + + MVE_VRINTf32A = 1674 + + MVE_VRINTf32M = 1675 + + MVE_VRINTf32N = 1676 + + MVE_VRINTf32P = 1677 + + MVE_VRINTf32X = 1678 + + MVE_VRINTf32Z = 1679 + + MVE_VRMLALDAVHas32 = 1680 + + MVE_VRMLALDAVHau32 = 1681 + + MVE_VRMLALDAVHaxs32 = 1682 + + MVE_VRMLALDAVHs32 = 1683 + + MVE_VRMLALDAVHu32 = 1684 + + MVE_VRMLALDAVHxs32 = 1685 + + MVE_VRMLSLDAVHas32 = 1686 + + MVE_VRMLSLDAVHaxs32 = 1687 + + MVE_VRMLSLDAVHs32 = 1688 + + MVE_VRMLSLDAVHxs32 = 1689 + + MVE_VRMULHs16 = 1690 + + MVE_VRMULHs32 = 1691 + + MVE_VRMULHs8 = 1692 + + MVE_VRMULHu16 = 1693 + + MVE_VRMULHu32 = 1694 + + MVE_VRMULHu8 = 1695 + + MVE_VRSHL_by_vecs16 = 1696 + + MVE_VRSHL_by_vecs32 = 1697 + + MVE_VRSHL_by_vecs8 = 1698 + + MVE_VRSHL_by_vecu16 = 1699 + + MVE_VRSHL_by_vecu32 = 1700 + + MVE_VRSHL_by_vecu8 = 1701 + + MVE_VRSHL_qrs16 = 1702 + + MVE_VRSHL_qrs32 = 1703 + + MVE_VRSHL_qrs8 = 1704 + + MVE_VRSHL_qru16 = 1705 + + MVE_VRSHL_qru32 = 1706 + + MVE_VRSHL_qru8 = 1707 + + MVE_VRSHRNi16bh = 1708 + + MVE_VRSHRNi16th = 1709 + + MVE_VRSHRNi32bh = 1710 + + MVE_VRSHRNi32th = 1711 + + MVE_VRSHR_imms16 = 1712 + + MVE_VRSHR_imms32 = 1713 + + MVE_VRSHR_imms8 = 1714 + + MVE_VRSHR_immu16 = 1715 + + MVE_VRSHR_immu32 = 1716 + + MVE_VRSHR_immu8 = 1717 + + MVE_VSBC = 1718 + + MVE_VSBCI = 1719 + + MVE_VSHLC = 1720 + + MVE_VSHLL_imms16bh = 1721 + + MVE_VSHLL_imms16th = 1722 + + MVE_VSHLL_imms8bh = 1723 + + MVE_VSHLL_imms8th = 1724 + + MVE_VSHLL_immu16bh = 1725 + + MVE_VSHLL_immu16th = 1726 + + MVE_VSHLL_immu8bh = 1727 + + MVE_VSHLL_immu8th = 1728 + + MVE_VSHLL_lws16bh = 1729 + + MVE_VSHLL_lws16th = 1730 + + MVE_VSHLL_lws8bh = 1731 + + MVE_VSHLL_lws8th = 1732 + + MVE_VSHLL_lwu16bh = 1733 + + MVE_VSHLL_lwu16th = 1734 + + MVE_VSHLL_lwu8bh = 1735 + + MVE_VSHLL_lwu8th = 1736 + + MVE_VSHL_by_vecs16 = 1737 + + MVE_VSHL_by_vecs32 = 1738 + + MVE_VSHL_by_vecs8 = 1739 + + MVE_VSHL_by_vecu16 = 1740 + + MVE_VSHL_by_vecu32 = 1741 + + MVE_VSHL_by_vecu8 = 1742 + + MVE_VSHL_immi16 = 1743 + + MVE_VSHL_immi32 = 1744 + + MVE_VSHL_immi8 = 1745 + + MVE_VSHL_qrs16 = 1746 + + MVE_VSHL_qrs32 = 1747 + + MVE_VSHL_qrs8 = 1748 + + MVE_VSHL_qru16 = 1749 + + MVE_VSHL_qru32 = 1750 + + MVE_VSHL_qru8 = 1751 + + MVE_VSHRNi16bh = 1752 + + MVE_VSHRNi16th = 1753 + + MVE_VSHRNi32bh = 1754 + + MVE_VSHRNi32th = 1755 + + MVE_VSHR_imms16 = 1756 + + MVE_VSHR_imms32 = 1757 + + MVE_VSHR_imms8 = 1758 + + MVE_VSHR_immu16 = 1759 + + MVE_VSHR_immu32 = 1760 + + MVE_VSHR_immu8 = 1761 + + MVE_VSLIimm16 = 1762 + + MVE_VSLIimm32 = 1763 + + MVE_VSLIimm8 = 1764 + + MVE_VSRIimm16 = 1765 + + MVE_VSRIimm32 = 1766 + + MVE_VSRIimm8 = 1767 + + MVE_VST20_16 = 1768 + + MVE_VST20_16_wb = 1769 + + MVE_VST20_32 = 1770 + + MVE_VST20_32_wb = 1771 + + MVE_VST20_8 = 1772 + + MVE_VST20_8_wb = 1773 + + MVE_VST21_16 = 1774 + + MVE_VST21_16_wb = 1775 + + MVE_VST21_32 = 1776 + + MVE_VST21_32_wb = 1777 + + MVE_VST21_8 = 1778 + + MVE_VST21_8_wb = 1779 + + MVE_VST40_16 = 1780 + + MVE_VST40_16_wb = 1781 + + MVE_VST40_32 = 1782 + + MVE_VST40_32_wb = 1783 + + MVE_VST40_8 = 1784 + + MVE_VST40_8_wb = 1785 + + MVE_VST41_16 = 1786 + + MVE_VST41_16_wb = 1787 + + MVE_VST41_32 = 1788 + + MVE_VST41_32_wb = 1789 + + MVE_VST41_8 = 1790 + + MVE_VST41_8_wb = 1791 + + MVE_VST42_16 = 1792 + + MVE_VST42_16_wb = 1793 + + MVE_VST42_32 = 1794 + + MVE_VST42_32_wb = 1795 + + MVE_VST42_8 = 1796 + + MVE_VST42_8_wb = 1797 + + MVE_VST43_16 = 1798 + + MVE_VST43_16_wb = 1799 + + MVE_VST43_32 = 1800 + + MVE_VST43_32_wb = 1801 + + MVE_VST43_8 = 1802 + + MVE_VST43_8_wb = 1803 + + MVE_VSTRB16 = 1804 + + MVE_VSTRB16_post = 1805 + + MVE_VSTRB16_pre = 1806 + + MVE_VSTRB16_rq = 1807 + + MVE_VSTRB32 = 1808 + + MVE_VSTRB32_post = 1809 + + MVE_VSTRB32_pre = 1810 + + MVE_VSTRB32_rq = 1811 + + MVE_VSTRB8_rq = 1812 + + MVE_VSTRBU8 = 1813 + + MVE_VSTRBU8_post = 1814 + + MVE_VSTRBU8_pre = 1815 + + MVE_VSTRD64_qi = 1816 + + MVE_VSTRD64_qi_pre = 1817 + + MVE_VSTRD64_rq = 1818 + + MVE_VSTRD64_rq_u = 1819 + + MVE_VSTRH16_rq = 1820 + + MVE_VSTRH16_rq_u = 1821 + + MVE_VSTRH32 = 1822 + + MVE_VSTRH32_post = 1823 + + MVE_VSTRH32_pre = 1824 + + MVE_VSTRH32_rq = 1825 + + MVE_VSTRH32_rq_u = 1826 + + MVE_VSTRHU16 = 1827 + + MVE_VSTRHU16_post = 1828 + + MVE_VSTRHU16_pre = 1829 + + MVE_VSTRW32_qi = 1830 + + MVE_VSTRW32_qi_pre = 1831 + + MVE_VSTRW32_rq = 1832 + + MVE_VSTRW32_rq_u = 1833 + + MVE_VSTRWU32 = 1834 + + MVE_VSTRWU32_post = 1835 + + MVE_VSTRWU32_pre = 1836 + + MVE_VSUB_qr_f16 = 1837 + + MVE_VSUB_qr_f32 = 1838 + + MVE_VSUB_qr_i16 = 1839 + + MVE_VSUB_qr_i32 = 1840 + + MVE_VSUB_qr_i8 = 1841 + + MVE_VSUBf16 = 1842 + + MVE_VSUBf32 = 1843 + + MVE_VSUBi16 = 1844 + + MVE_VSUBi32 = 1845 + + MVE_VSUBi8 = 1846 + + MVE_WLSTP_16 = 1847 + + MVE_WLSTP_32 = 1848 + + MVE_WLSTP_64 = 1849 + + MVE_WLSTP_8 = 1850 + + MVNi = 1851 + + MVNr = 1852 + + MVNsi = 1853 + + MVNsr = 1854 + + NEON_VMAXNMNDf = 1855 + + NEON_VMAXNMNDh = 1856 + + NEON_VMAXNMNQf = 1857 + + NEON_VMAXNMNQh = 1858 + + NEON_VMINNMNDf = 1859 + + NEON_VMINNMNDh = 1860 + + NEON_VMINNMNQf = 1861 + + NEON_VMINNMNQh = 1862 + + ORRri = 1863 + + ORRrr = 1864 + + ORRrsi = 1865 + + ORRrsr = 1866 + + PKHBT = 1867 + + PKHTB = 1868 + + PLDWi12 = 1869 + + PLDWrs = 1870 + + PLDi12 = 1871 + + PLDrs = 1872 + + PLIi12 = 1873 + + PLIrs = 1874 + + QADD = 1875 + + QADD16 = 1876 + + QADD8 = 1877 + + QASX = 1878 + + QDADD = 1879 + + QDSUB = 1880 + + QSAX = 1881 + + QSUB = 1882 + + QSUB16 = 1883 + + QSUB8 = 1884 + + RBIT = 1885 + + REV = 1886 + + REV16 = 1887 + + REVSH = 1888 + + RFEDA = 1889 + + RFEDA_UPD = 1890 + + RFEDB = 1891 + + RFEDB_UPD = 1892 + + RFEIA = 1893 + + RFEIA_UPD = 1894 + + RFEIB = 1895 + + RFEIB_UPD = 1896 + + RSBri = 1897 + + RSBrr = 1898 + + RSBrsi = 1899 + + RSBrsr = 1900 + + RSCri = 1901 + + RSCrr = 1902 + + RSCrsi = 1903 + + RSCrsr = 1904 + + SADD16 = 1905 + + SADD8 = 1906 + + SASX = 1907 + + SB = 1908 + + SBCri = 1909 + + SBCrr = 1910 + + SBCrsi = 1911 + + SBCrsr = 1912 + + SBFX = 1913 + + SDIV = 1914 + + SEL = 1915 + + SETEND = 1916 + + SETPAN = 1917 + + SHA1C = 1918 + + SHA1H = 1919 + + SHA1M = 1920 + + SHA1P = 1921 + + SHA1SU0 = 1922 + + SHA1SU1 = 1923 + + SHA256H = 1924 + + SHA256H2 = 1925 + + SHA256SU0 = 1926 + + SHA256SU1 = 1927 + + SHADD16 = 1928 + + SHADD8 = 1929 + + SHASX = 1930 + + SHSAX = 1931 + + SHSUB16 = 1932 + + SHSUB8 = 1933 + + SMC = 1934 + + SMLABB = 1935 + + SMLABT = 1936 + + SMLAD = 1937 + + SMLADX = 1938 + + SMLAL = 1939 + + SMLALBB = 1940 + + SMLALBT = 1941 + + SMLALD = 1942 + + SMLALDX = 1943 + + SMLALTB = 1944 + + SMLALTT = 1945 + + SMLATB = 1946 + + SMLATT = 1947 + + SMLAWB = 1948 + + SMLAWT = 1949 + + SMLSD = 1950 + + SMLSDX = 1951 + + SMLSLD = 1952 + + SMLSLDX = 1953 + + SMMLA = 1954 + + SMMLAR = 1955 + + SMMLS = 1956 + + SMMLSR = 1957 + + SMMUL = 1958 + + SMMULR = 1959 + + SMUAD = 1960 + + SMUADX = 1961 + + SMULBB = 1962 + + SMULBT = 1963 + + SMULL = 1964 + + SMULTB = 1965 + + SMULTT = 1966 + + SMULWB = 1967 + + SMULWT = 1968 + + SMUSD = 1969 + + SMUSDX = 1970 + + SRSDA = 1971 + + SRSDA_UPD = 1972 + + SRSDB = 1973 + + SRSDB_UPD = 1974 + + SRSIA = 1975 + + SRSIA_UPD = 1976 + + SRSIB = 1977 + + SRSIB_UPD = 1978 + + SSAT = 1979 + + SSAT16 = 1980 + + SSAX = 1981 + + SSUB16 = 1982 + + SSUB8 = 1983 + + STC2L_OFFSET = 1984 + + STC2L_OPTION = 1985 + + STC2L_POST = 1986 + + STC2L_PRE = 1987 + + STC2_OFFSET = 1988 + + STC2_OPTION = 1989 + + STC2_POST = 1990 + + STC2_PRE = 1991 + + STCL_OFFSET = 1992 + + STCL_OPTION = 1993 + + STCL_POST = 1994 + + STCL_PRE = 1995 + + STC_OFFSET = 1996 + + STC_OPTION = 1997 + + STC_POST = 1998 + + STC_PRE = 1999 + + STL = 2000 + + STLB = 2001 + + STLEX = 2002 + + STLEXB = 2003 + + STLEXD = 2004 + + STLEXH = 2005 + + STLH = 2006 + + STMDA = 2007 + + STMDA_UPD = 2008 + + STMDB = 2009 + + STMDB_UPD = 2010 + + STMIA = 2011 + + STMIA_UPD = 2012 + + STMIB = 2013 + + STMIB_UPD = 2014 + + STRBT_POST_IMM = 2015 + + STRBT_POST_REG = 2016 + + STRB_POST_IMM = 2017 + + STRB_POST_REG = 2018 + + STRB_PRE_IMM = 2019 + + STRB_PRE_REG = 2020 + + STRBi12 = 2021 + + STRBrs = 2022 + + STRD = 2023 + + STRD_POST = 2024 + + STRD_PRE = 2025 + + STREX = 2026 + + STREXB = 2027 + + STREXD = 2028 + + STREXH = 2029 + + STRH = 2030 + + STRHTi = 2031 + + STRHTr = 2032 + + STRH_POST = 2033 + + STRH_PRE = 2034 + + STRT_POST_IMM = 2035 + + STRT_POST_REG = 2036 + + STR_POST_IMM = 2037 + + STR_POST_REG = 2038 + + STR_PRE_IMM = 2039 + + STR_PRE_REG = 2040 + + STRi12 = 2041 + + STRrs = 2042 + + SUBri = 2043 + + SUBrr = 2044 + + SUBrsi = 2045 + + SUBrsr = 2046 + + SVC = 2047 + + SWP = 2048 + + SWPB = 2049 + + SXTAB = 2050 + + SXTAB16 = 2051 + + SXTAH = 2052 + + SXTB = 2053 + + SXTB16 = 2054 + + SXTH = 2055 + + TEQri = 2056 + + TEQrr = 2057 + + TEQrsi = 2058 + + TEQrsr = 2059 + + TRAP = 2060 + + TSB = 2061 + + TSTri = 2062 + + TSTrr = 2063 + + TSTrsi = 2064 + + TSTrsr = 2065 + + UADD16 = 2066 + + UADD8 = 2067 + + UASX = 2068 + + UBFX = 2069 + + UDF = 2070 + + UDIV = 2071 + + UHADD16 = 2072 + + UHADD8 = 2073 + + UHASX = 2074 + + UHSAX = 2075 + + UHSUB16 = 2076 + + UHSUB8 = 2077 + + UMAAL = 2078 + + UMLAL = 2079 + + UMULL = 2080 + + UQADD16 = 2081 + + UQADD8 = 2082 + + UQASX = 2083 + + UQSAX = 2084 + + UQSUB16 = 2085 + + UQSUB8 = 2086 + + USAD8 = 2087 + + USADA8 = 2088 + + USAT = 2089 + + USAT16 = 2090 + + USAX = 2091 + + USUB16 = 2092 + + USUB8 = 2093 + + UXTAB = 2094 + + UXTAB16 = 2095 + + UXTAH = 2096 + + UXTB = 2097 + + UXTB16 = 2098 + + UXTH = 2099 + + VABALsv2i64 = 2100 + + VABALsv4i32 = 2101 + + VABALsv8i16 = 2102 + + VABALuv2i64 = 2103 + + VABALuv4i32 = 2104 + + VABALuv8i16 = 2105 + + VABAsv16i8 = 2106 + + VABAsv2i32 = 2107 + + VABAsv4i16 = 2108 + + VABAsv4i32 = 2109 + + VABAsv8i16 = 2110 + + VABAsv8i8 = 2111 + + VABAuv16i8 = 2112 + + VABAuv2i32 = 2113 + + VABAuv4i16 = 2114 + + VABAuv4i32 = 2115 + + VABAuv8i16 = 2116 + + VABAuv8i8 = 2117 + + VABDLsv2i64 = 2118 + + VABDLsv4i32 = 2119 + + VABDLsv8i16 = 2120 + + VABDLuv2i64 = 2121 + + VABDLuv4i32 = 2122 + + VABDLuv8i16 = 2123 + + VABDfd = 2124 + + VABDfq = 2125 + + VABDhd = 2126 + + VABDhq = 2127 + + VABDsv16i8 = 2128 + + VABDsv2i32 = 2129 + + VABDsv4i16 = 2130 + + VABDsv4i32 = 2131 + + VABDsv8i16 = 2132 + + VABDsv8i8 = 2133 + + VABDuv16i8 = 2134 + + VABDuv2i32 = 2135 + + VABDuv4i16 = 2136 + + VABDuv4i32 = 2137 + + VABDuv8i16 = 2138 + + VABDuv8i8 = 2139 + + VABSD = 2140 + + VABSH = 2141 + + VABSS = 2142 + + VABSfd = 2143 + + VABSfq = 2144 + + VABShd = 2145 + + VABShq = 2146 + + VABSv16i8 = 2147 + + VABSv2i32 = 2148 + + VABSv4i16 = 2149 + + VABSv4i32 = 2150 + + VABSv8i16 = 2151 + + VABSv8i8 = 2152 + + VACGEfd = 2153 + + VACGEfq = 2154 + + VACGEhd = 2155 + + VACGEhq = 2156 + + VACGTfd = 2157 + + VACGTfq = 2158 + + VACGThd = 2159 + + VACGThq = 2160 + + VADDD = 2161 + + VADDH = 2162 + + VADDHNv2i32 = 2163 + + VADDHNv4i16 = 2164 + + VADDHNv8i8 = 2165 + + VADDLsv2i64 = 2166 + + VADDLsv4i32 = 2167 + + VADDLsv8i16 = 2168 + + VADDLuv2i64 = 2169 + + VADDLuv4i32 = 2170 + + VADDLuv8i16 = 2171 + + VADDS = 2172 + + VADDWsv2i64 = 2173 + + VADDWsv4i32 = 2174 + + VADDWsv8i16 = 2175 + + VADDWuv2i64 = 2176 + + VADDWuv4i32 = 2177 + + VADDWuv8i16 = 2178 + + VADDfd = 2179 + + VADDfq = 2180 + + VADDhd = 2181 + + VADDhq = 2182 + + VADDv16i8 = 2183 + + VADDv1i64 = 2184 + + VADDv2i32 = 2185 + + VADDv2i64 = 2186 + + VADDv4i16 = 2187 + + VADDv4i32 = 2188 + + VADDv8i16 = 2189 + + VADDv8i8 = 2190 + + VANDd = 2191 + + VANDq = 2192 + + VBF16MALBQ = 2193 + + VBF16MALBQI = 2194 + + VBF16MALTQ = 2195 + + VBF16MALTQI = 2196 + + VBICd = 2197 + + VBICiv2i32 = 2198 + + VBICiv4i16 = 2199 + + VBICiv4i32 = 2200 + + VBICiv8i16 = 2201 + + VBICq = 2202 + + VBIFd = 2203 + + VBIFq = 2204 + + VBITd = 2205 + + VBITq = 2206 + + VBSLd = 2207 + + VBSLq = 2208 + + VBSPd = 2209 + + VBSPq = 2210 + + VCADDv2f32 = 2211 + + VCADDv4f16 = 2212 + + VCADDv4f32 = 2213 + + VCADDv8f16 = 2214 + + VCEQfd = 2215 + + VCEQfq = 2216 + + VCEQhd = 2217 + + VCEQhq = 2218 + + VCEQv16i8 = 2219 + + VCEQv2i32 = 2220 + + VCEQv4i16 = 2221 + + VCEQv4i32 = 2222 + + VCEQv8i16 = 2223 + + VCEQv8i8 = 2224 + + VCEQzv16i8 = 2225 + + VCEQzv2f32 = 2226 + + VCEQzv2i32 = 2227 + + VCEQzv4f16 = 2228 + + VCEQzv4f32 = 2229 + + VCEQzv4i16 = 2230 + + VCEQzv4i32 = 2231 + + VCEQzv8f16 = 2232 + + VCEQzv8i16 = 2233 + + VCEQzv8i8 = 2234 + + VCGEfd = 2235 + + VCGEfq = 2236 + + VCGEhd = 2237 + + VCGEhq = 2238 + + VCGEsv16i8 = 2239 + + VCGEsv2i32 = 2240 + + VCGEsv4i16 = 2241 + + VCGEsv4i32 = 2242 + + VCGEsv8i16 = 2243 + + VCGEsv8i8 = 2244 + + VCGEuv16i8 = 2245 + + VCGEuv2i32 = 2246 + + VCGEuv4i16 = 2247 + + VCGEuv4i32 = 2248 + + VCGEuv8i16 = 2249 + + VCGEuv8i8 = 2250 + + VCGEzv16i8 = 2251 + + VCGEzv2f32 = 2252 + + VCGEzv2i32 = 2253 + + VCGEzv4f16 = 2254 + + VCGEzv4f32 = 2255 + + VCGEzv4i16 = 2256 + + VCGEzv4i32 = 2257 + + VCGEzv8f16 = 2258 + + VCGEzv8i16 = 2259 + + VCGEzv8i8 = 2260 + + VCGTfd = 2261 + + VCGTfq = 2262 + + VCGThd = 2263 + + VCGThq = 2264 + + VCGTsv16i8 = 2265 + + VCGTsv2i32 = 2266 + + VCGTsv4i16 = 2267 + + VCGTsv4i32 = 2268 + + VCGTsv8i16 = 2269 + + VCGTsv8i8 = 2270 + + VCGTuv16i8 = 2271 + + VCGTuv2i32 = 2272 + + VCGTuv4i16 = 2273 + + VCGTuv4i32 = 2274 + + VCGTuv8i16 = 2275 + + VCGTuv8i8 = 2276 + + VCGTzv16i8 = 2277 + + VCGTzv2f32 = 2278 + + VCGTzv2i32 = 2279 + + VCGTzv4f16 = 2280 + + VCGTzv4f32 = 2281 + + VCGTzv4i16 = 2282 + + VCGTzv4i32 = 2283 + + VCGTzv8f16 = 2284 + + VCGTzv8i16 = 2285 + + VCGTzv8i8 = 2286 + + VCLEzv16i8 = 2287 + + VCLEzv2f32 = 2288 + + VCLEzv2i32 = 2289 + + VCLEzv4f16 = 2290 + + VCLEzv4f32 = 2291 + + VCLEzv4i16 = 2292 + + VCLEzv4i32 = 2293 + + VCLEzv8f16 = 2294 + + VCLEzv8i16 = 2295 + + VCLEzv8i8 = 2296 + + VCLSv16i8 = 2297 + + VCLSv2i32 = 2298 + + VCLSv4i16 = 2299 + + VCLSv4i32 = 2300 + + VCLSv8i16 = 2301 + + VCLSv8i8 = 2302 + + VCLTzv16i8 = 2303 + + VCLTzv2f32 = 2304 + + VCLTzv2i32 = 2305 + + VCLTzv4f16 = 2306 + + VCLTzv4f32 = 2307 + + VCLTzv4i16 = 2308 + + VCLTzv4i32 = 2309 + + VCLTzv8f16 = 2310 + + VCLTzv8i16 = 2311 + + VCLTzv8i8 = 2312 + + VCLZv16i8 = 2313 + + VCLZv2i32 = 2314 + + VCLZv4i16 = 2315 + + VCLZv4i32 = 2316 + + VCLZv8i16 = 2317 + + VCLZv8i8 = 2318 + + VCMLAv2f32 = 2319 + + VCMLAv2f32_indexed = 2320 + + VCMLAv4f16 = 2321 + + VCMLAv4f16_indexed = 2322 + + VCMLAv4f32 = 2323 + + VCMLAv4f32_indexed = 2324 + + VCMLAv8f16 = 2325 + + VCMLAv8f16_indexed = 2326 + + VCMPD = 2327 + + VCMPED = 2328 + + VCMPEH = 2329 + + VCMPES = 2330 + + VCMPEZD = 2331 + + VCMPEZH = 2332 + + VCMPEZS = 2333 + + VCMPH = 2334 + + VCMPS = 2335 + + VCMPZD = 2336 + + VCMPZH = 2337 + + VCMPZS = 2338 + + VCNTd = 2339 + + VCNTq = 2340 + + VCVTANSDf = 2341 + + VCVTANSDh = 2342 + + VCVTANSQf = 2343 + + VCVTANSQh = 2344 + + VCVTANUDf = 2345 + + VCVTANUDh = 2346 + + VCVTANUQf = 2347 + + VCVTANUQh = 2348 + + VCVTASD = 2349 + + VCVTASH = 2350 + + VCVTASS = 2351 + + VCVTAUD = 2352 + + VCVTAUH = 2353 + + VCVTAUS = 2354 + + VCVTBDH = 2355 + + VCVTBHD = 2356 + + VCVTBHS = 2357 + + VCVTBSH = 2358 + + VCVTDS = 2359 + + VCVTMNSDf = 2360 + + VCVTMNSDh = 2361 + + VCVTMNSQf = 2362 + + VCVTMNSQh = 2363 + + VCVTMNUDf = 2364 + + VCVTMNUDh = 2365 + + VCVTMNUQf = 2366 + + VCVTMNUQh = 2367 + + VCVTMSD = 2368 + + VCVTMSH = 2369 + + VCVTMSS = 2370 + + VCVTMUD = 2371 + + VCVTMUH = 2372 + + VCVTMUS = 2373 + + VCVTNNSDf = 2374 + + VCVTNNSDh = 2375 + + VCVTNNSQf = 2376 + + VCVTNNSQh = 2377 + + VCVTNNUDf = 2378 + + VCVTNNUDh = 2379 + + VCVTNNUQf = 2380 + + VCVTNNUQh = 2381 + + VCVTNSD = 2382 + + VCVTNSH = 2383 + + VCVTNSS = 2384 + + VCVTNUD = 2385 + + VCVTNUH = 2386 + + VCVTNUS = 2387 + + VCVTPNSDf = 2388 + + VCVTPNSDh = 2389 + + VCVTPNSQf = 2390 + + VCVTPNSQh = 2391 + + VCVTPNUDf = 2392 + + VCVTPNUDh = 2393 + + VCVTPNUQf = 2394 + + VCVTPNUQh = 2395 + + VCVTPSD = 2396 + + VCVTPSH = 2397 + + VCVTPSS = 2398 + + VCVTPUD = 2399 + + VCVTPUH = 2400 + + VCVTPUS = 2401 + + VCVTSD = 2402 + + VCVTTDH = 2403 + + VCVTTHD = 2404 + + VCVTTHS = 2405 + + VCVTTSH = 2406 + + VCVTf2h = 2407 + + VCVTf2sd = 2408 + + VCVTf2sq = 2409 + + VCVTf2ud = 2410 + + VCVTf2uq = 2411 + + VCVTf2xsd = 2412 + + VCVTf2xsq = 2413 + + VCVTf2xud = 2414 + + VCVTf2xuq = 2415 + + VCVTh2f = 2416 + + VCVTh2sd = 2417 + + VCVTh2sq = 2418 + + VCVTh2ud = 2419 + + VCVTh2uq = 2420 + + VCVTh2xsd = 2421 + + VCVTh2xsq = 2422 + + VCVTh2xud = 2423 + + VCVTh2xuq = 2424 + + VCVTs2fd = 2425 + + VCVTs2fq = 2426 + + VCVTs2hd = 2427 + + VCVTs2hq = 2428 + + VCVTu2fd = 2429 + + VCVTu2fq = 2430 + + VCVTu2hd = 2431 + + VCVTu2hq = 2432 + + VCVTxs2fd = 2433 + + VCVTxs2fq = 2434 + + VCVTxs2hd = 2435 + + VCVTxs2hq = 2436 + + VCVTxu2fd = 2437 + + VCVTxu2fq = 2438 + + VCVTxu2hd = 2439 + + VCVTxu2hq = 2440 + + VDIVD = 2441 + + VDIVH = 2442 + + VDIVS = 2443 + + VDUP16d = 2444 + + VDUP16q = 2445 + + VDUP32d = 2446 + + VDUP32q = 2447 + + VDUP8d = 2448 + + VDUP8q = 2449 + + VDUPLN16d = 2450 + + VDUPLN16q = 2451 + + VDUPLN32d = 2452 + + VDUPLN32q = 2453 + + VDUPLN8d = 2454 + + VDUPLN8q = 2455 + + VEORd = 2456 + + VEORq = 2457 + + VEXTd16 = 2458 + + VEXTd32 = 2459 + + VEXTd8 = 2460 + + VEXTq16 = 2461 + + VEXTq32 = 2462 + + VEXTq64 = 2463 + + VEXTq8 = 2464 + + VFMAD = 2465 + + VFMAH = 2466 + + VFMALD = 2467 + + VFMALDI = 2468 + + VFMALQ = 2469 + + VFMALQI = 2470 + + VFMAS = 2471 + + VFMAfd = 2472 + + VFMAfq = 2473 + + VFMAhd = 2474 + + VFMAhq = 2475 + + VFMSD = 2476 + + VFMSH = 2477 + + VFMSLD = 2478 + + VFMSLDI = 2479 + + VFMSLQ = 2480 + + VFMSLQI = 2481 + + VFMSS = 2482 + + VFMSfd = 2483 + + VFMSfq = 2484 + + VFMShd = 2485 + + VFMShq = 2486 + + VFNMAD = 2487 + + VFNMAH = 2488 + + VFNMAS = 2489 + + VFNMSD = 2490 + + VFNMSH = 2491 + + VFNMSS = 2492 + + VFP_VMAXNMD = 2493 + + VFP_VMAXNMH = 2494 + + VFP_VMAXNMS = 2495 + + VFP_VMINNMD = 2496 + + VFP_VMINNMH = 2497 + + VFP_VMINNMS = 2498 + + VGETLNi32 = 2499 + + VGETLNs16 = 2500 + + VGETLNs8 = 2501 + + VGETLNu16 = 2502 + + VGETLNu8 = 2503 + + VHADDsv16i8 = 2504 + + VHADDsv2i32 = 2505 + + VHADDsv4i16 = 2506 + + VHADDsv4i32 = 2507 + + VHADDsv8i16 = 2508 + + VHADDsv8i8 = 2509 + + VHADDuv16i8 = 2510 + + VHADDuv2i32 = 2511 + + VHADDuv4i16 = 2512 + + VHADDuv4i32 = 2513 + + VHADDuv8i16 = 2514 + + VHADDuv8i8 = 2515 + + VHSUBsv16i8 = 2516 + + VHSUBsv2i32 = 2517 + + VHSUBsv4i16 = 2518 + + VHSUBsv4i32 = 2519 + + VHSUBsv8i16 = 2520 + + VHSUBsv8i8 = 2521 + + VHSUBuv16i8 = 2522 + + VHSUBuv2i32 = 2523 + + VHSUBuv4i16 = 2524 + + VHSUBuv4i32 = 2525 + + VHSUBuv8i16 = 2526 + + VHSUBuv8i8 = 2527 + + VINSH = 2528 + + VJCVT = 2529 + + VLD1DUPd16 = 2530 + + VLD1DUPd16wb_fixed = 2531 + + VLD1DUPd16wb_register = 2532 + + VLD1DUPd32 = 2533 + + VLD1DUPd32wb_fixed = 2534 + + VLD1DUPd32wb_register = 2535 + + VLD1DUPd8 = 2536 + + VLD1DUPd8wb_fixed = 2537 + + VLD1DUPd8wb_register = 2538 + + VLD1DUPq16 = 2539 + + VLD1DUPq16wb_fixed = 2540 + + VLD1DUPq16wb_register = 2541 + + VLD1DUPq32 = 2542 + + VLD1DUPq32wb_fixed = 2543 + + VLD1DUPq32wb_register = 2544 + + VLD1DUPq8 = 2545 + + VLD1DUPq8wb_fixed = 2546 + + VLD1DUPq8wb_register = 2547 + + VLD1LNd16 = 2548 + + VLD1LNd16_UPD = 2549 + + VLD1LNd32 = 2550 + + VLD1LNd32_UPD = 2551 + + VLD1LNd8 = 2552 + + VLD1LNd8_UPD = 2553 + + VLD1LNq16Pseudo = 2554 + + VLD1LNq16Pseudo_UPD = 2555 + + VLD1LNq32Pseudo = 2556 + + VLD1LNq32Pseudo_UPD = 2557 + + VLD1LNq8Pseudo = 2558 + + VLD1LNq8Pseudo_UPD = 2559 + + VLD1d16 = 2560 + + VLD1d16Q = 2561 + + VLD1d16QPseudo = 2562 + + VLD1d16QPseudoWB_fixed = 2563 + + VLD1d16QPseudoWB_register = 2564 + + VLD1d16Qwb_fixed = 2565 + + VLD1d16Qwb_register = 2566 + + VLD1d16T = 2567 + + VLD1d16TPseudo = 2568 + + VLD1d16TPseudoWB_fixed = 2569 + + VLD1d16TPseudoWB_register = 2570 + + VLD1d16Twb_fixed = 2571 + + VLD1d16Twb_register = 2572 + + VLD1d16wb_fixed = 2573 + + VLD1d16wb_register = 2574 + + VLD1d32 = 2575 + + VLD1d32Q = 2576 + + VLD1d32QPseudo = 2577 + + VLD1d32QPseudoWB_fixed = 2578 + + VLD1d32QPseudoWB_register = 2579 + + VLD1d32Qwb_fixed = 2580 + + VLD1d32Qwb_register = 2581 + + VLD1d32T = 2582 + + VLD1d32TPseudo = 2583 + + VLD1d32TPseudoWB_fixed = 2584 + + VLD1d32TPseudoWB_register = 2585 + + VLD1d32Twb_fixed = 2586 + + VLD1d32Twb_register = 2587 + + VLD1d32wb_fixed = 2588 + + VLD1d32wb_register = 2589 + + VLD1d64 = 2590 + + VLD1d64Q = 2591 + + VLD1d64QPseudo = 2592 + + VLD1d64QPseudoWB_fixed = 2593 + + VLD1d64QPseudoWB_register = 2594 + + VLD1d64Qwb_fixed = 2595 + + VLD1d64Qwb_register = 2596 + + VLD1d64T = 2597 + + VLD1d64TPseudo = 2598 + + VLD1d64TPseudoWB_fixed = 2599 + + VLD1d64TPseudoWB_register = 2600 + + VLD1d64Twb_fixed = 2601 + + VLD1d64Twb_register = 2602 + + VLD1d64wb_fixed = 2603 + + VLD1d64wb_register = 2604 + + VLD1d8 = 2605 + + VLD1d8Q = 2606 + + VLD1d8QPseudo = 2607 + + VLD1d8QPseudoWB_fixed = 2608 + + VLD1d8QPseudoWB_register = 2609 + + VLD1d8Qwb_fixed = 2610 + + VLD1d8Qwb_register = 2611 + + VLD1d8T = 2612 + + VLD1d8TPseudo = 2613 + + VLD1d8TPseudoWB_fixed = 2614 + + VLD1d8TPseudoWB_register = 2615 + + VLD1d8Twb_fixed = 2616 + + VLD1d8Twb_register = 2617 + + VLD1d8wb_fixed = 2618 + + VLD1d8wb_register = 2619 + + VLD1q16 = 2620 + + VLD1q16HighQPseudo = 2621 + + VLD1q16HighQPseudo_UPD = 2622 + + VLD1q16HighTPseudo = 2623 + + VLD1q16HighTPseudo_UPD = 2624 + + VLD1q16LowQPseudo_UPD = 2625 + + VLD1q16LowTPseudo_UPD = 2626 + + VLD1q16wb_fixed = 2627 + + VLD1q16wb_register = 2628 + + VLD1q32 = 2629 + + VLD1q32HighQPseudo = 2630 + + VLD1q32HighQPseudo_UPD = 2631 + + VLD1q32HighTPseudo = 2632 + + VLD1q32HighTPseudo_UPD = 2633 + + VLD1q32LowQPseudo_UPD = 2634 + + VLD1q32LowTPseudo_UPD = 2635 + + VLD1q32wb_fixed = 2636 + + VLD1q32wb_register = 2637 + + VLD1q64 = 2638 + + VLD1q64HighQPseudo = 2639 + + VLD1q64HighQPseudo_UPD = 2640 + + VLD1q64HighTPseudo = 2641 + + VLD1q64HighTPseudo_UPD = 2642 + + VLD1q64LowQPseudo_UPD = 2643 + + VLD1q64LowTPseudo_UPD = 2644 + + VLD1q64wb_fixed = 2645 + + VLD1q64wb_register = 2646 + + VLD1q8 = 2647 + + VLD1q8HighQPseudo = 2648 + + VLD1q8HighQPseudo_UPD = 2649 + + VLD1q8HighTPseudo = 2650 + + VLD1q8HighTPseudo_UPD = 2651 + + VLD1q8LowQPseudo_UPD = 2652 + + VLD1q8LowTPseudo_UPD = 2653 + + VLD1q8wb_fixed = 2654 + + VLD1q8wb_register = 2655 + + VLD2DUPd16 = 2656 + + VLD2DUPd16wb_fixed = 2657 + + VLD2DUPd16wb_register = 2658 + + VLD2DUPd16x2 = 2659 + + VLD2DUPd16x2wb_fixed = 2660 + + VLD2DUPd16x2wb_register = 2661 + + VLD2DUPd32 = 2662 + + VLD2DUPd32wb_fixed = 2663 + + VLD2DUPd32wb_register = 2664 + + VLD2DUPd32x2 = 2665 + + VLD2DUPd32x2wb_fixed = 2666 + + VLD2DUPd32x2wb_register = 2667 + + VLD2DUPd8 = 2668 + + VLD2DUPd8wb_fixed = 2669 + + VLD2DUPd8wb_register = 2670 + + VLD2DUPd8x2 = 2671 + + VLD2DUPd8x2wb_fixed = 2672 + + VLD2DUPd8x2wb_register = 2673 + + VLD2DUPq16EvenPseudo = 2674 + + VLD2DUPq16OddPseudo = 2675 + + VLD2DUPq16OddPseudoWB_fixed = 2676 + + VLD2DUPq16OddPseudoWB_register = 2677 + + VLD2DUPq32EvenPseudo = 2678 + + VLD2DUPq32OddPseudo = 2679 + + VLD2DUPq32OddPseudoWB_fixed = 2680 + + VLD2DUPq32OddPseudoWB_register = 2681 + + VLD2DUPq8EvenPseudo = 2682 + + VLD2DUPq8OddPseudo = 2683 + + VLD2DUPq8OddPseudoWB_fixed = 2684 + + VLD2DUPq8OddPseudoWB_register = 2685 + + VLD2LNd16 = 2686 + + VLD2LNd16Pseudo = 2687 + + VLD2LNd16Pseudo_UPD = 2688 + + VLD2LNd16_UPD = 2689 + + VLD2LNd32 = 2690 + + VLD2LNd32Pseudo = 2691 + + VLD2LNd32Pseudo_UPD = 2692 + + VLD2LNd32_UPD = 2693 + + VLD2LNd8 = 2694 + + VLD2LNd8Pseudo = 2695 + + VLD2LNd8Pseudo_UPD = 2696 + + VLD2LNd8_UPD = 2697 + + VLD2LNq16 = 2698 + + VLD2LNq16Pseudo = 2699 + + VLD2LNq16Pseudo_UPD = 2700 + + VLD2LNq16_UPD = 2701 + + VLD2LNq32 = 2702 + + VLD2LNq32Pseudo = 2703 + + VLD2LNq32Pseudo_UPD = 2704 + + VLD2LNq32_UPD = 2705 + + VLD2b16 = 2706 + + VLD2b16wb_fixed = 2707 + + VLD2b16wb_register = 2708 + + VLD2b32 = 2709 + + VLD2b32wb_fixed = 2710 + + VLD2b32wb_register = 2711 + + VLD2b8 = 2712 + + VLD2b8wb_fixed = 2713 + + VLD2b8wb_register = 2714 + + VLD2d16 = 2715 + + VLD2d16wb_fixed = 2716 + + VLD2d16wb_register = 2717 + + VLD2d32 = 2718 + + VLD2d32wb_fixed = 2719 + + VLD2d32wb_register = 2720 + + VLD2d8 = 2721 + + VLD2d8wb_fixed = 2722 + + VLD2d8wb_register = 2723 + + VLD2q16 = 2724 + + VLD2q16Pseudo = 2725 + + VLD2q16PseudoWB_fixed = 2726 + + VLD2q16PseudoWB_register = 2727 + + VLD2q16wb_fixed = 2728 + + VLD2q16wb_register = 2729 + + VLD2q32 = 2730 + + VLD2q32Pseudo = 2731 + + VLD2q32PseudoWB_fixed = 2732 + + VLD2q32PseudoWB_register = 2733 + + VLD2q32wb_fixed = 2734 + + VLD2q32wb_register = 2735 + + VLD2q8 = 2736 + + VLD2q8Pseudo = 2737 + + VLD2q8PseudoWB_fixed = 2738 + + VLD2q8PseudoWB_register = 2739 + + VLD2q8wb_fixed = 2740 + + VLD2q8wb_register = 2741 + + VLD3DUPd16 = 2742 + + VLD3DUPd16Pseudo = 2743 + + VLD3DUPd16Pseudo_UPD = 2744 + + VLD3DUPd16_UPD = 2745 + + VLD3DUPd32 = 2746 + + VLD3DUPd32Pseudo = 2747 + + VLD3DUPd32Pseudo_UPD = 2748 + + VLD3DUPd32_UPD = 2749 + + VLD3DUPd8 = 2750 + + VLD3DUPd8Pseudo = 2751 + + VLD3DUPd8Pseudo_UPD = 2752 + + VLD3DUPd8_UPD = 2753 + + VLD3DUPq16 = 2754 + + VLD3DUPq16EvenPseudo = 2755 + + VLD3DUPq16OddPseudo = 2756 + + VLD3DUPq16OddPseudo_UPD = 2757 + + VLD3DUPq16_UPD = 2758 + + VLD3DUPq32 = 2759 + + VLD3DUPq32EvenPseudo = 2760 + + VLD3DUPq32OddPseudo = 2761 + + VLD3DUPq32OddPseudo_UPD = 2762 + + VLD3DUPq32_UPD = 2763 + + VLD3DUPq8 = 2764 + + VLD3DUPq8EvenPseudo = 2765 + + VLD3DUPq8OddPseudo = 2766 + + VLD3DUPq8OddPseudo_UPD = 2767 + + VLD3DUPq8_UPD = 2768 + + VLD3LNd16 = 2769 + + VLD3LNd16Pseudo = 2770 + + VLD3LNd16Pseudo_UPD = 2771 + + VLD3LNd16_UPD = 2772 + + VLD3LNd32 = 2773 + + VLD3LNd32Pseudo = 2774 + + VLD3LNd32Pseudo_UPD = 2775 + + VLD3LNd32_UPD = 2776 + + VLD3LNd8 = 2777 + + VLD3LNd8Pseudo = 2778 + + VLD3LNd8Pseudo_UPD = 2779 + + VLD3LNd8_UPD = 2780 + + VLD3LNq16 = 2781 + + VLD3LNq16Pseudo = 2782 + + VLD3LNq16Pseudo_UPD = 2783 + + VLD3LNq16_UPD = 2784 + + VLD3LNq32 = 2785 + + VLD3LNq32Pseudo = 2786 + + VLD3LNq32Pseudo_UPD = 2787 + + VLD3LNq32_UPD = 2788 + + VLD3d16 = 2789 + + VLD3d16Pseudo = 2790 + + VLD3d16Pseudo_UPD = 2791 + + VLD3d16_UPD = 2792 + + VLD3d32 = 2793 + + VLD3d32Pseudo = 2794 + + VLD3d32Pseudo_UPD = 2795 + + VLD3d32_UPD = 2796 + + VLD3d8 = 2797 + + VLD3d8Pseudo = 2798 + + VLD3d8Pseudo_UPD = 2799 + + VLD3d8_UPD = 2800 + + VLD3q16 = 2801 + + VLD3q16Pseudo_UPD = 2802 + + VLD3q16_UPD = 2803 + + VLD3q16oddPseudo = 2804 + + VLD3q16oddPseudo_UPD = 2805 + + VLD3q32 = 2806 + + VLD3q32Pseudo_UPD = 2807 + + VLD3q32_UPD = 2808 + + VLD3q32oddPseudo = 2809 + + VLD3q32oddPseudo_UPD = 2810 + + VLD3q8 = 2811 + + VLD3q8Pseudo_UPD = 2812 + + VLD3q8_UPD = 2813 + + VLD3q8oddPseudo = 2814 + + VLD3q8oddPseudo_UPD = 2815 + + VLD4DUPd16 = 2816 + + VLD4DUPd16Pseudo = 2817 + + VLD4DUPd16Pseudo_UPD = 2818 + + VLD4DUPd16_UPD = 2819 + + VLD4DUPd32 = 2820 + + VLD4DUPd32Pseudo = 2821 + + VLD4DUPd32Pseudo_UPD = 2822 + + VLD4DUPd32_UPD = 2823 + + VLD4DUPd8 = 2824 + + VLD4DUPd8Pseudo = 2825 + + VLD4DUPd8Pseudo_UPD = 2826 + + VLD4DUPd8_UPD = 2827 + + VLD4DUPq16 = 2828 + + VLD4DUPq16EvenPseudo = 2829 + + VLD4DUPq16OddPseudo = 2830 + + VLD4DUPq16OddPseudo_UPD = 2831 + + VLD4DUPq16_UPD = 2832 + + VLD4DUPq32 = 2833 + + VLD4DUPq32EvenPseudo = 2834 + + VLD4DUPq32OddPseudo = 2835 + + VLD4DUPq32OddPseudo_UPD = 2836 + + VLD4DUPq32_UPD = 2837 + + VLD4DUPq8 = 2838 + + VLD4DUPq8EvenPseudo = 2839 + + VLD4DUPq8OddPseudo = 2840 + + VLD4DUPq8OddPseudo_UPD = 2841 + + VLD4DUPq8_UPD = 2842 + + VLD4LNd16 = 2843 + + VLD4LNd16Pseudo = 2844 + + VLD4LNd16Pseudo_UPD = 2845 + + VLD4LNd16_UPD = 2846 + + VLD4LNd32 = 2847 + + VLD4LNd32Pseudo = 2848 + + VLD4LNd32Pseudo_UPD = 2849 + + VLD4LNd32_UPD = 2850 + + VLD4LNd8 = 2851 + + VLD4LNd8Pseudo = 2852 + + VLD4LNd8Pseudo_UPD = 2853 + + VLD4LNd8_UPD = 2854 + + VLD4LNq16 = 2855 + + VLD4LNq16Pseudo = 2856 + + VLD4LNq16Pseudo_UPD = 2857 + + VLD4LNq16_UPD = 2858 + + VLD4LNq32 = 2859 + + VLD4LNq32Pseudo = 2860 + + VLD4LNq32Pseudo_UPD = 2861 + + VLD4LNq32_UPD = 2862 + + VLD4d16 = 2863 + + VLD4d16Pseudo = 2864 + + VLD4d16Pseudo_UPD = 2865 + + VLD4d16_UPD = 2866 + + VLD4d32 = 2867 + + VLD4d32Pseudo = 2868 + + VLD4d32Pseudo_UPD = 2869 + + VLD4d32_UPD = 2870 + + VLD4d8 = 2871 + + VLD4d8Pseudo = 2872 + + VLD4d8Pseudo_UPD = 2873 + + VLD4d8_UPD = 2874 + + VLD4q16 = 2875 + + VLD4q16Pseudo_UPD = 2876 + + VLD4q16_UPD = 2877 + + VLD4q16oddPseudo = 2878 + + VLD4q16oddPseudo_UPD = 2879 + + VLD4q32 = 2880 + + VLD4q32Pseudo_UPD = 2881 + + VLD4q32_UPD = 2882 + + VLD4q32oddPseudo = 2883 + + VLD4q32oddPseudo_UPD = 2884 + + VLD4q8 = 2885 + + VLD4q8Pseudo_UPD = 2886 + + VLD4q8_UPD = 2887 + + VLD4q8oddPseudo = 2888 + + VLD4q8oddPseudo_UPD = 2889 + + VLDMDDB_UPD = 2890 + + VLDMDIA = 2891 + + VLDMDIA_UPD = 2892 + + VLDMQIA = 2893 + + VLDMSDB_UPD = 2894 + + VLDMSIA = 2895 + + VLDMSIA_UPD = 2896 + + VLDRD = 2897 + + VLDRH = 2898 + + VLDRS = 2899 + + VLDR_FPCXTNS_off = 2900 + + VLDR_FPCXTNS_post = 2901 + + VLDR_FPCXTNS_pre = 2902 + + VLDR_FPCXTS_off = 2903 + + VLDR_FPCXTS_post = 2904 + + VLDR_FPCXTS_pre = 2905 + + VLDR_FPSCR_NZCVQC_off = 2906 + + VLDR_FPSCR_NZCVQC_post = 2907 + + VLDR_FPSCR_NZCVQC_pre = 2908 + + VLDR_FPSCR_off = 2909 + + VLDR_FPSCR_post = 2910 + + VLDR_FPSCR_pre = 2911 + + VLDR_P0_off = 2912 + + VLDR_P0_post = 2913 + + VLDR_P0_pre = 2914 + + VLDR_VPR_off = 2915 + + VLDR_VPR_post = 2916 + + VLDR_VPR_pre = 2917 + + VLLDM = 2918 + + VLLDM_T2 = 2919 + + VLSTM = 2920 + + VLSTM_T2 = 2921 + + VMAXfd = 2922 + + VMAXfq = 2923 + + VMAXhd = 2924 + + VMAXhq = 2925 + + VMAXsv16i8 = 2926 + + VMAXsv2i32 = 2927 + + VMAXsv4i16 = 2928 + + VMAXsv4i32 = 2929 + + VMAXsv8i16 = 2930 + + VMAXsv8i8 = 2931 + + VMAXuv16i8 = 2932 + + VMAXuv2i32 = 2933 + + VMAXuv4i16 = 2934 + + VMAXuv4i32 = 2935 + + VMAXuv8i16 = 2936 + + VMAXuv8i8 = 2937 + + VMINfd = 2938 + + VMINfq = 2939 + + VMINhd = 2940 + + VMINhq = 2941 + + VMINsv16i8 = 2942 + + VMINsv2i32 = 2943 + + VMINsv4i16 = 2944 + + VMINsv4i32 = 2945 + + VMINsv8i16 = 2946 + + VMINsv8i8 = 2947 + + VMINuv16i8 = 2948 + + VMINuv2i32 = 2949 + + VMINuv4i16 = 2950 + + VMINuv4i32 = 2951 + + VMINuv8i16 = 2952 + + VMINuv8i8 = 2953 + + VMLAD = 2954 + + VMLAH = 2955 + + VMLALslsv2i32 = 2956 + + VMLALslsv4i16 = 2957 + + VMLALsluv2i32 = 2958 + + VMLALsluv4i16 = 2959 + + VMLALsv2i64 = 2960 + + VMLALsv4i32 = 2961 + + VMLALsv8i16 = 2962 + + VMLALuv2i64 = 2963 + + VMLALuv4i32 = 2964 + + VMLALuv8i16 = 2965 + + VMLAS = 2966 + + VMLAfd = 2967 + + VMLAfq = 2968 + + VMLAhd = 2969 + + VMLAhq = 2970 + + VMLAslfd = 2971 + + VMLAslfq = 2972 + + VMLAslhd = 2973 + + VMLAslhq = 2974 + + VMLAslv2i32 = 2975 + + VMLAslv4i16 = 2976 + + VMLAslv4i32 = 2977 + + VMLAslv8i16 = 2978 + + VMLAv16i8 = 2979 + + VMLAv2i32 = 2980 + + VMLAv4i16 = 2981 + + VMLAv4i32 = 2982 + + VMLAv8i16 = 2983 + + VMLAv8i8 = 2984 + + VMLSD = 2985 + + VMLSH = 2986 + + VMLSLslsv2i32 = 2987 + + VMLSLslsv4i16 = 2988 + + VMLSLsluv2i32 = 2989 + + VMLSLsluv4i16 = 2990 + + VMLSLsv2i64 = 2991 + + VMLSLsv4i32 = 2992 + + VMLSLsv8i16 = 2993 + + VMLSLuv2i64 = 2994 + + VMLSLuv4i32 = 2995 + + VMLSLuv8i16 = 2996 + + VMLSS = 2997 + + VMLSfd = 2998 + + VMLSfq = 2999 + + VMLShd = 3000 + + VMLShq = 3001 + + VMLSslfd = 3002 + + VMLSslfq = 3003 + + VMLSslhd = 3004 + + VMLSslhq = 3005 + + VMLSslv2i32 = 3006 + + VMLSslv4i16 = 3007 + + VMLSslv4i32 = 3008 + + VMLSslv8i16 = 3009 + + VMLSv16i8 = 3010 + + VMLSv2i32 = 3011 + + VMLSv4i16 = 3012 + + VMLSv4i32 = 3013 + + VMLSv8i16 = 3014 + + VMLSv8i8 = 3015 + + VMMLA = 3016 + + VMOVD = 3017 + + VMOVDRR = 3018 + + VMOVH = 3019 + + VMOVHR = 3020 + + VMOVLsv2i64 = 3021 + + VMOVLsv4i32 = 3022 + + VMOVLsv8i16 = 3023 + + VMOVLuv2i64 = 3024 + + VMOVLuv4i32 = 3025 + + VMOVLuv8i16 = 3026 + + VMOVNv2i32 = 3027 + + VMOVNv4i16 = 3028 + + VMOVNv8i8 = 3029 + + VMOVRH = 3030 + + VMOVRRD = 3031 + + VMOVRRS = 3032 + + VMOVRS = 3033 + + VMOVS = 3034 + + VMOVSR = 3035 + + VMOVSRR = 3036 + + VMOVv16i8 = 3037 + + VMOVv1i64 = 3038 + + VMOVv2f32 = 3039 + + VMOVv2i32 = 3040 + + VMOVv2i64 = 3041 + + VMOVv4f32 = 3042 + + VMOVv4i16 = 3043 + + VMOVv4i32 = 3044 + + VMOVv8i16 = 3045 + + VMOVv8i8 = 3046 + + VMRS = 3047 + + VMRS_FPCXTNS = 3048 + + VMRS_FPCXTS = 3049 + + VMRS_FPEXC = 3050 + + VMRS_FPINST = 3051 + + VMRS_FPINST2 = 3052 + + VMRS_FPSCR_NZCVQC = 3053 + + VMRS_FPSID = 3054 + + VMRS_MVFR0 = 3055 + + VMRS_MVFR1 = 3056 + + VMRS_MVFR2 = 3057 + + VMRS_P0 = 3058 + + VMRS_VPR = 3059 + + VMSR = 3060 + + VMSR_FPCXTNS = 3061 + + VMSR_FPCXTS = 3062 + + VMSR_FPEXC = 3063 + + VMSR_FPINST = 3064 + + VMSR_FPINST2 = 3065 + + VMSR_FPSCR_NZCVQC = 3066 + + VMSR_FPSID = 3067 + + VMSR_P0 = 3068 + + VMSR_VPR = 3069 + + VMULD = 3070 + + VMULH = 3071 + + VMULLp64 = 3072 + + VMULLp8 = 3073 + + VMULLslsv2i32 = 3074 + + VMULLslsv4i16 = 3075 + + VMULLsluv2i32 = 3076 + + VMULLsluv4i16 = 3077 + + VMULLsv2i64 = 3078 + + VMULLsv4i32 = 3079 + + VMULLsv8i16 = 3080 + + VMULLuv2i64 = 3081 + + VMULLuv4i32 = 3082 + + VMULLuv8i16 = 3083 + + VMULS = 3084 + + VMULfd = 3085 + + VMULfq = 3086 + + VMULhd = 3087 + + VMULhq = 3088 + + VMULpd = 3089 + + VMULpq = 3090 + + VMULslfd = 3091 + + VMULslfq = 3092 + + VMULslhd = 3093 + + VMULslhq = 3094 + + VMULslv2i32 = 3095 + + VMULslv4i16 = 3096 + + VMULslv4i32 = 3097 + + VMULslv8i16 = 3098 + + VMULv16i8 = 3099 + + VMULv2i32 = 3100 + + VMULv4i16 = 3101 + + VMULv4i32 = 3102 + + VMULv8i16 = 3103 + + VMULv8i8 = 3104 + + VMVNd = 3105 + + VMVNq = 3106 + + VMVNv2i32 = 3107 + + VMVNv4i16 = 3108 + + VMVNv4i32 = 3109 + + VMVNv8i16 = 3110 + + VNEGD = 3111 + + VNEGH = 3112 + + VNEGS = 3113 + + VNEGf32q = 3114 + + VNEGfd = 3115 + + VNEGhd = 3116 + + VNEGhq = 3117 + + VNEGs16d = 3118 + + VNEGs16q = 3119 + + VNEGs32d = 3120 + + VNEGs32q = 3121 + + VNEGs8d = 3122 + + VNEGs8q = 3123 + + VNMLAD = 3124 + + VNMLAH = 3125 + + VNMLAS = 3126 + + VNMLSD = 3127 + + VNMLSH = 3128 + + VNMLSS = 3129 + + VNMULD = 3130 + + VNMULH = 3131 + + VNMULS = 3132 + + VORNd = 3133 + + VORNq = 3134 + + VORRd = 3135 + + VORRiv2i32 = 3136 + + VORRiv4i16 = 3137 + + VORRiv4i32 = 3138 + + VORRiv8i16 = 3139 + + VORRq = 3140 + + VPADALsv16i8 = 3141 + + VPADALsv2i32 = 3142 + + VPADALsv4i16 = 3143 + + VPADALsv4i32 = 3144 + + VPADALsv8i16 = 3145 + + VPADALsv8i8 = 3146 + + VPADALuv16i8 = 3147 + + VPADALuv2i32 = 3148 + + VPADALuv4i16 = 3149 + + VPADALuv4i32 = 3150 + + VPADALuv8i16 = 3151 + + VPADALuv8i8 = 3152 + + VPADDLsv16i8 = 3153 + + VPADDLsv2i32 = 3154 + + VPADDLsv4i16 = 3155 + + VPADDLsv4i32 = 3156 + + VPADDLsv8i16 = 3157 + + VPADDLsv8i8 = 3158 + + VPADDLuv16i8 = 3159 + + VPADDLuv2i32 = 3160 + + VPADDLuv4i16 = 3161 + + VPADDLuv4i32 = 3162 + + VPADDLuv8i16 = 3163 + + VPADDLuv8i8 = 3164 + + VPADDf = 3165 + + VPADDh = 3166 + + VPADDi16 = 3167 + + VPADDi32 = 3168 + + VPADDi8 = 3169 + + VPMAXf = 3170 + + VPMAXh = 3171 + + VPMAXs16 = 3172 + + VPMAXs32 = 3173 + + VPMAXs8 = 3174 + + VPMAXu16 = 3175 + + VPMAXu32 = 3176 + + VPMAXu8 = 3177 + + VPMINf = 3178 + + VPMINh = 3179 + + VPMINs16 = 3180 + + VPMINs32 = 3181 + + VPMINs8 = 3182 + + VPMINu16 = 3183 + + VPMINu32 = 3184 + + VPMINu8 = 3185 + + VQABSv16i8 = 3186 + + VQABSv2i32 = 3187 + + VQABSv4i16 = 3188 + + VQABSv4i32 = 3189 + + VQABSv8i16 = 3190 + + VQABSv8i8 = 3191 + + VQADDsv16i8 = 3192 + + VQADDsv1i64 = 3193 + + VQADDsv2i32 = 3194 + + VQADDsv2i64 = 3195 + + VQADDsv4i16 = 3196 + + VQADDsv4i32 = 3197 + + VQADDsv8i16 = 3198 + + VQADDsv8i8 = 3199 + + VQADDuv16i8 = 3200 + + VQADDuv1i64 = 3201 + + VQADDuv2i32 = 3202 + + VQADDuv2i64 = 3203 + + VQADDuv4i16 = 3204 + + VQADDuv4i32 = 3205 + + VQADDuv8i16 = 3206 + + VQADDuv8i8 = 3207 + + VQDMLALslv2i32 = 3208 + + VQDMLALslv4i16 = 3209 + + VQDMLALv2i64 = 3210 + + VQDMLALv4i32 = 3211 + + VQDMLSLslv2i32 = 3212 + + VQDMLSLslv4i16 = 3213 + + VQDMLSLv2i64 = 3214 + + VQDMLSLv4i32 = 3215 + + VQDMULHslv2i32 = 3216 + + VQDMULHslv4i16 = 3217 + + VQDMULHslv4i32 = 3218 + + VQDMULHslv8i16 = 3219 + + VQDMULHv2i32 = 3220 + + VQDMULHv4i16 = 3221 + + VQDMULHv4i32 = 3222 + + VQDMULHv8i16 = 3223 + + VQDMULLslv2i32 = 3224 + + VQDMULLslv4i16 = 3225 + + VQDMULLv2i64 = 3226 + + VQDMULLv4i32 = 3227 + + VQMOVNsuv2i32 = 3228 + + VQMOVNsuv4i16 = 3229 + + VQMOVNsuv8i8 = 3230 + + VQMOVNsv2i32 = 3231 + + VQMOVNsv4i16 = 3232 + + VQMOVNsv8i8 = 3233 + + VQMOVNuv2i32 = 3234 + + VQMOVNuv4i16 = 3235 + + VQMOVNuv8i8 = 3236 + + VQNEGv16i8 = 3237 + + VQNEGv2i32 = 3238 + + VQNEGv4i16 = 3239 + + VQNEGv4i32 = 3240 + + VQNEGv8i16 = 3241 + + VQNEGv8i8 = 3242 + + VQRDMLAHslv2i32 = 3243 + + VQRDMLAHslv4i16 = 3244 + + VQRDMLAHslv4i32 = 3245 + + VQRDMLAHslv8i16 = 3246 + + VQRDMLAHv2i32 = 3247 + + VQRDMLAHv4i16 = 3248 + + VQRDMLAHv4i32 = 3249 + + VQRDMLAHv8i16 = 3250 + + VQRDMLSHslv2i32 = 3251 + + VQRDMLSHslv4i16 = 3252 + + VQRDMLSHslv4i32 = 3253 + + VQRDMLSHslv8i16 = 3254 + + VQRDMLSHv2i32 = 3255 + + VQRDMLSHv4i16 = 3256 + + VQRDMLSHv4i32 = 3257 + + VQRDMLSHv8i16 = 3258 + + VQRDMULHslv2i32 = 3259 + + VQRDMULHslv4i16 = 3260 + + VQRDMULHslv4i32 = 3261 + + VQRDMULHslv8i16 = 3262 + + VQRDMULHv2i32 = 3263 + + VQRDMULHv4i16 = 3264 + + VQRDMULHv4i32 = 3265 + + VQRDMULHv8i16 = 3266 + + VQRSHLsv16i8 = 3267 + + VQRSHLsv1i64 = 3268 + + VQRSHLsv2i32 = 3269 + + VQRSHLsv2i64 = 3270 + + VQRSHLsv4i16 = 3271 + + VQRSHLsv4i32 = 3272 + + VQRSHLsv8i16 = 3273 + + VQRSHLsv8i8 = 3274 + + VQRSHLuv16i8 = 3275 + + VQRSHLuv1i64 = 3276 + + VQRSHLuv2i32 = 3277 + + VQRSHLuv2i64 = 3278 + + VQRSHLuv4i16 = 3279 + + VQRSHLuv4i32 = 3280 + + VQRSHLuv8i16 = 3281 + + VQRSHLuv8i8 = 3282 + + VQRSHRNsv2i32 = 3283 + + VQRSHRNsv4i16 = 3284 + + VQRSHRNsv8i8 = 3285 + + VQRSHRNuv2i32 = 3286 + + VQRSHRNuv4i16 = 3287 + + VQRSHRNuv8i8 = 3288 + + VQRSHRUNv2i32 = 3289 + + VQRSHRUNv4i16 = 3290 + + VQRSHRUNv8i8 = 3291 + + VQSHLsiv16i8 = 3292 + + VQSHLsiv1i64 = 3293 + + VQSHLsiv2i32 = 3294 + + VQSHLsiv2i64 = 3295 + + VQSHLsiv4i16 = 3296 + + VQSHLsiv4i32 = 3297 + + VQSHLsiv8i16 = 3298 + + VQSHLsiv8i8 = 3299 + + VQSHLsuv16i8 = 3300 + + VQSHLsuv1i64 = 3301 + + VQSHLsuv2i32 = 3302 + + VQSHLsuv2i64 = 3303 + + VQSHLsuv4i16 = 3304 + + VQSHLsuv4i32 = 3305 + + VQSHLsuv8i16 = 3306 + + VQSHLsuv8i8 = 3307 + + VQSHLsv16i8 = 3308 + + VQSHLsv1i64 = 3309 + + VQSHLsv2i32 = 3310 + + VQSHLsv2i64 = 3311 + + VQSHLsv4i16 = 3312 + + VQSHLsv4i32 = 3313 + + VQSHLsv8i16 = 3314 + + VQSHLsv8i8 = 3315 + + VQSHLuiv16i8 = 3316 + + VQSHLuiv1i64 = 3317 + + VQSHLuiv2i32 = 3318 + + VQSHLuiv2i64 = 3319 + + VQSHLuiv4i16 = 3320 + + VQSHLuiv4i32 = 3321 + + VQSHLuiv8i16 = 3322 + + VQSHLuiv8i8 = 3323 + + VQSHLuv16i8 = 3324 + + VQSHLuv1i64 = 3325 + + VQSHLuv2i32 = 3326 + + VQSHLuv2i64 = 3327 + + VQSHLuv4i16 = 3328 + + VQSHLuv4i32 = 3329 + + VQSHLuv8i16 = 3330 + + VQSHLuv8i8 = 3331 + + VQSHRNsv2i32 = 3332 + + VQSHRNsv4i16 = 3333 + + VQSHRNsv8i8 = 3334 + + VQSHRNuv2i32 = 3335 + + VQSHRNuv4i16 = 3336 + + VQSHRNuv8i8 = 3337 + + VQSHRUNv2i32 = 3338 + + VQSHRUNv4i16 = 3339 + + VQSHRUNv8i8 = 3340 + + VQSUBsv16i8 = 3341 + + VQSUBsv1i64 = 3342 + + VQSUBsv2i32 = 3343 + + VQSUBsv2i64 = 3344 + + VQSUBsv4i16 = 3345 + + VQSUBsv4i32 = 3346 + + VQSUBsv8i16 = 3347 + + VQSUBsv8i8 = 3348 + + VQSUBuv16i8 = 3349 + + VQSUBuv1i64 = 3350 + + VQSUBuv2i32 = 3351 + + VQSUBuv2i64 = 3352 + + VQSUBuv4i16 = 3353 + + VQSUBuv4i32 = 3354 + + VQSUBuv8i16 = 3355 + + VQSUBuv8i8 = 3356 + + VRADDHNv2i32 = 3357 + + VRADDHNv4i16 = 3358 + + VRADDHNv8i8 = 3359 + + VRECPEd = 3360 + + VRECPEfd = 3361 + + VRECPEfq = 3362 + + VRECPEhd = 3363 + + VRECPEhq = 3364 + + VRECPEq = 3365 + + VRECPSfd = 3366 + + VRECPSfq = 3367 + + VRECPShd = 3368 + + VRECPShq = 3369 + + VREV16d8 = 3370 + + VREV16q8 = 3371 + + VREV32d16 = 3372 + + VREV32d8 = 3373 + + VREV32q16 = 3374 + + VREV32q8 = 3375 + + VREV64d16 = 3376 + + VREV64d32 = 3377 + + VREV64d8 = 3378 + + VREV64q16 = 3379 + + VREV64q32 = 3380 + + VREV64q8 = 3381 + + VRHADDsv16i8 = 3382 + + VRHADDsv2i32 = 3383 + + VRHADDsv4i16 = 3384 + + VRHADDsv4i32 = 3385 + + VRHADDsv8i16 = 3386 + + VRHADDsv8i8 = 3387 + + VRHADDuv16i8 = 3388 + + VRHADDuv2i32 = 3389 + + VRHADDuv4i16 = 3390 + + VRHADDuv4i32 = 3391 + + VRHADDuv8i16 = 3392 + + VRHADDuv8i8 = 3393 + + VRINTAD = 3394 + + VRINTAH = 3395 + + VRINTANDf = 3396 + + VRINTANDh = 3397 + + VRINTANQf = 3398 + + VRINTANQh = 3399 + + VRINTAS = 3400 + + VRINTMD = 3401 + + VRINTMH = 3402 + + VRINTMNDf = 3403 + + VRINTMNDh = 3404 + + VRINTMNQf = 3405 + + VRINTMNQh = 3406 + + VRINTMS = 3407 + + VRINTND = 3408 + + VRINTNH = 3409 + + VRINTNNDf = 3410 + + VRINTNNDh = 3411 + + VRINTNNQf = 3412 + + VRINTNNQh = 3413 + + VRINTNS = 3414 + + VRINTPD = 3415 + + VRINTPH = 3416 + + VRINTPNDf = 3417 + + VRINTPNDh = 3418 + + VRINTPNQf = 3419 + + VRINTPNQh = 3420 + + VRINTPS = 3421 + + VRINTRD = 3422 + + VRINTRH = 3423 + + VRINTRS = 3424 + + VRINTXD = 3425 + + VRINTXH = 3426 + + VRINTXNDf = 3427 + + VRINTXNDh = 3428 + + VRINTXNQf = 3429 + + VRINTXNQh = 3430 + + VRINTXS = 3431 + + VRINTZD = 3432 + + VRINTZH = 3433 + + VRINTZNDf = 3434 + + VRINTZNDh = 3435 + + VRINTZNQf = 3436 + + VRINTZNQh = 3437 + + VRINTZS = 3438 + + VRSHLsv16i8 = 3439 + + VRSHLsv1i64 = 3440 + + VRSHLsv2i32 = 3441 + + VRSHLsv2i64 = 3442 + + VRSHLsv4i16 = 3443 + + VRSHLsv4i32 = 3444 + + VRSHLsv8i16 = 3445 + + VRSHLsv8i8 = 3446 + + VRSHLuv16i8 = 3447 + + VRSHLuv1i64 = 3448 + + VRSHLuv2i32 = 3449 + + VRSHLuv2i64 = 3450 + + VRSHLuv4i16 = 3451 + + VRSHLuv4i32 = 3452 + + VRSHLuv8i16 = 3453 + + VRSHLuv8i8 = 3454 + + VRSHRNv2i32 = 3455 + + VRSHRNv4i16 = 3456 + + VRSHRNv8i8 = 3457 + + VRSHRsv16i8 = 3458 + + VRSHRsv1i64 = 3459 + + VRSHRsv2i32 = 3460 + + VRSHRsv2i64 = 3461 + + VRSHRsv4i16 = 3462 + + VRSHRsv4i32 = 3463 + + VRSHRsv8i16 = 3464 + + VRSHRsv8i8 = 3465 + + VRSHRuv16i8 = 3466 + + VRSHRuv1i64 = 3467 + + VRSHRuv2i32 = 3468 + + VRSHRuv2i64 = 3469 + + VRSHRuv4i16 = 3470 + + VRSHRuv4i32 = 3471 + + VRSHRuv8i16 = 3472 + + VRSHRuv8i8 = 3473 + + VRSQRTEd = 3474 + + VRSQRTEfd = 3475 + + VRSQRTEfq = 3476 + + VRSQRTEhd = 3477 + + VRSQRTEhq = 3478 + + VRSQRTEq = 3479 + + VRSQRTSfd = 3480 + + VRSQRTSfq = 3481 + + VRSQRTShd = 3482 + + VRSQRTShq = 3483 + + VRSRAsv16i8 = 3484 + + VRSRAsv1i64 = 3485 + + VRSRAsv2i32 = 3486 + + VRSRAsv2i64 = 3487 + + VRSRAsv4i16 = 3488 + + VRSRAsv4i32 = 3489 + + VRSRAsv8i16 = 3490 + + VRSRAsv8i8 = 3491 + + VRSRAuv16i8 = 3492 + + VRSRAuv1i64 = 3493 + + VRSRAuv2i32 = 3494 + + VRSRAuv2i64 = 3495 + + VRSRAuv4i16 = 3496 + + VRSRAuv4i32 = 3497 + + VRSRAuv8i16 = 3498 + + VRSRAuv8i8 = 3499 + + VRSUBHNv2i32 = 3500 + + VRSUBHNv4i16 = 3501 + + VRSUBHNv8i8 = 3502 + + VSCCLRMD = 3503 + + VSCCLRMS = 3504 + + VSDOTD = 3505 + + VSDOTDI = 3506 + + VSDOTQ = 3507 + + VSDOTQI = 3508 + + VSELEQD = 3509 + + VSELEQH = 3510 + + VSELEQS = 3511 + + VSELGED = 3512 + + VSELGEH = 3513 + + VSELGES = 3514 + + VSELGTD = 3515 + + VSELGTH = 3516 + + VSELGTS = 3517 + + VSELVSD = 3518 + + VSELVSH = 3519 + + VSELVSS = 3520 + + VSETLNi16 = 3521 + + VSETLNi32 = 3522 + + VSETLNi8 = 3523 + + VSHLLi16 = 3524 + + VSHLLi32 = 3525 + + VSHLLi8 = 3526 + + VSHLLsv2i64 = 3527 + + VSHLLsv4i32 = 3528 + + VSHLLsv8i16 = 3529 + + VSHLLuv2i64 = 3530 + + VSHLLuv4i32 = 3531 + + VSHLLuv8i16 = 3532 + + VSHLiv16i8 = 3533 + + VSHLiv1i64 = 3534 + + VSHLiv2i32 = 3535 + + VSHLiv2i64 = 3536 + + VSHLiv4i16 = 3537 + + VSHLiv4i32 = 3538 + + VSHLiv8i16 = 3539 + + VSHLiv8i8 = 3540 + + VSHLsv16i8 = 3541 + + VSHLsv1i64 = 3542 + + VSHLsv2i32 = 3543 + + VSHLsv2i64 = 3544 + + VSHLsv4i16 = 3545 + + VSHLsv4i32 = 3546 + + VSHLsv8i16 = 3547 + + VSHLsv8i8 = 3548 + + VSHLuv16i8 = 3549 + + VSHLuv1i64 = 3550 + + VSHLuv2i32 = 3551 + + VSHLuv2i64 = 3552 + + VSHLuv4i16 = 3553 + + VSHLuv4i32 = 3554 + + VSHLuv8i16 = 3555 + + VSHLuv8i8 = 3556 + + VSHRNv2i32 = 3557 + + VSHRNv4i16 = 3558 + + VSHRNv8i8 = 3559 + + VSHRsv16i8 = 3560 + + VSHRsv1i64 = 3561 + + VSHRsv2i32 = 3562 + + VSHRsv2i64 = 3563 + + VSHRsv4i16 = 3564 + + VSHRsv4i32 = 3565 + + VSHRsv8i16 = 3566 + + VSHRsv8i8 = 3567 + + VSHRuv16i8 = 3568 + + VSHRuv1i64 = 3569 + + VSHRuv2i32 = 3570 + + VSHRuv2i64 = 3571 + + VSHRuv4i16 = 3572 + + VSHRuv4i32 = 3573 + + VSHRuv8i16 = 3574 + + VSHRuv8i8 = 3575 + + VSHTOD = 3576 + + VSHTOH = 3577 + + VSHTOS = 3578 + + VSITOD = 3579 + + VSITOH = 3580 + + VSITOS = 3581 + + VSLIv16i8 = 3582 + + VSLIv1i64 = 3583 + + VSLIv2i32 = 3584 + + VSLIv2i64 = 3585 + + VSLIv4i16 = 3586 + + VSLIv4i32 = 3587 + + VSLIv8i16 = 3588 + + VSLIv8i8 = 3589 + + VSLTOD = 3590 + + VSLTOH = 3591 + + VSLTOS = 3592 + + VSMMLA = 3593 + + VSQRTD = 3594 + + VSQRTH = 3595 + + VSQRTS = 3596 + + VSRAsv16i8 = 3597 + + VSRAsv1i64 = 3598 + + VSRAsv2i32 = 3599 + + VSRAsv2i64 = 3600 + + VSRAsv4i16 = 3601 + + VSRAsv4i32 = 3602 + + VSRAsv8i16 = 3603 + + VSRAsv8i8 = 3604 + + VSRAuv16i8 = 3605 + + VSRAuv1i64 = 3606 + + VSRAuv2i32 = 3607 + + VSRAuv2i64 = 3608 + + VSRAuv4i16 = 3609 + + VSRAuv4i32 = 3610 + + VSRAuv8i16 = 3611 + + VSRAuv8i8 = 3612 + + VSRIv16i8 = 3613 + + VSRIv1i64 = 3614 + + VSRIv2i32 = 3615 + + VSRIv2i64 = 3616 + + VSRIv4i16 = 3617 + + VSRIv4i32 = 3618 + + VSRIv8i16 = 3619 + + VSRIv8i8 = 3620 + + VST1LNd16 = 3621 + + VST1LNd16_UPD = 3622 + + VST1LNd32 = 3623 + + VST1LNd32_UPD = 3624 + + VST1LNd8 = 3625 + + VST1LNd8_UPD = 3626 + + VST1LNq16Pseudo = 3627 + + VST1LNq16Pseudo_UPD = 3628 + + VST1LNq32Pseudo = 3629 + + VST1LNq32Pseudo_UPD = 3630 + + VST1LNq8Pseudo = 3631 + + VST1LNq8Pseudo_UPD = 3632 + + VST1d16 = 3633 + + VST1d16Q = 3634 + + VST1d16QPseudo = 3635 + + VST1d16QPseudoWB_fixed = 3636 + + VST1d16QPseudoWB_register = 3637 + + VST1d16Qwb_fixed = 3638 + + VST1d16Qwb_register = 3639 + + VST1d16T = 3640 + + VST1d16TPseudo = 3641 + + VST1d16TPseudoWB_fixed = 3642 + + VST1d16TPseudoWB_register = 3643 + + VST1d16Twb_fixed = 3644 + + VST1d16Twb_register = 3645 + + VST1d16wb_fixed = 3646 + + VST1d16wb_register = 3647 + + VST1d32 = 3648 + + VST1d32Q = 3649 + + VST1d32QPseudo = 3650 + + VST1d32QPseudoWB_fixed = 3651 + + VST1d32QPseudoWB_register = 3652 + + VST1d32Qwb_fixed = 3653 + + VST1d32Qwb_register = 3654 + + VST1d32T = 3655 + + VST1d32TPseudo = 3656 + + VST1d32TPseudoWB_fixed = 3657 + + VST1d32TPseudoWB_register = 3658 + + VST1d32Twb_fixed = 3659 + + VST1d32Twb_register = 3660 + + VST1d32wb_fixed = 3661 + + VST1d32wb_register = 3662 + + VST1d64 = 3663 + + VST1d64Q = 3664 + + VST1d64QPseudo = 3665 + + VST1d64QPseudoWB_fixed = 3666 + + VST1d64QPseudoWB_register = 3667 + + VST1d64Qwb_fixed = 3668 + + VST1d64Qwb_register = 3669 + + VST1d64T = 3670 + + VST1d64TPseudo = 3671 + + VST1d64TPseudoWB_fixed = 3672 + + VST1d64TPseudoWB_register = 3673 + + VST1d64Twb_fixed = 3674 + + VST1d64Twb_register = 3675 + + VST1d64wb_fixed = 3676 + + VST1d64wb_register = 3677 + + VST1d8 = 3678 + + VST1d8Q = 3679 + + VST1d8QPseudo = 3680 + + VST1d8QPseudoWB_fixed = 3681 + + VST1d8QPseudoWB_register = 3682 + + VST1d8Qwb_fixed = 3683 + + VST1d8Qwb_register = 3684 + + VST1d8T = 3685 + + VST1d8TPseudo = 3686 + + VST1d8TPseudoWB_fixed = 3687 + + VST1d8TPseudoWB_register = 3688 + + VST1d8Twb_fixed = 3689 + + VST1d8Twb_register = 3690 + + VST1d8wb_fixed = 3691 + + VST1d8wb_register = 3692 + + VST1q16 = 3693 + + VST1q16HighQPseudo = 3694 + + VST1q16HighQPseudo_UPD = 3695 + + VST1q16HighTPseudo = 3696 + + VST1q16HighTPseudo_UPD = 3697 + + VST1q16LowQPseudo_UPD = 3698 + + VST1q16LowTPseudo_UPD = 3699 + + VST1q16wb_fixed = 3700 + + VST1q16wb_register = 3701 + + VST1q32 = 3702 + + VST1q32HighQPseudo = 3703 + + VST1q32HighQPseudo_UPD = 3704 + + VST1q32HighTPseudo = 3705 + + VST1q32HighTPseudo_UPD = 3706 + + VST1q32LowQPseudo_UPD = 3707 + + VST1q32LowTPseudo_UPD = 3708 + + VST1q32wb_fixed = 3709 + + VST1q32wb_register = 3710 + + VST1q64 = 3711 + + VST1q64HighQPseudo = 3712 + + VST1q64HighQPseudo_UPD = 3713 + + VST1q64HighTPseudo = 3714 + + VST1q64HighTPseudo_UPD = 3715 + + VST1q64LowQPseudo_UPD = 3716 + + VST1q64LowTPseudo_UPD = 3717 + + VST1q64wb_fixed = 3718 + + VST1q64wb_register = 3719 + + VST1q8 = 3720 + + VST1q8HighQPseudo = 3721 + + VST1q8HighQPseudo_UPD = 3722 + + VST1q8HighTPseudo = 3723 + + VST1q8HighTPseudo_UPD = 3724 + + VST1q8LowQPseudo_UPD = 3725 + + VST1q8LowTPseudo_UPD = 3726 + + VST1q8wb_fixed = 3727 + + VST1q8wb_register = 3728 + + VST2LNd16 = 3729 + + VST2LNd16Pseudo = 3730 + + VST2LNd16Pseudo_UPD = 3731 + + VST2LNd16_UPD = 3732 + + VST2LNd32 = 3733 + + VST2LNd32Pseudo = 3734 + + VST2LNd32Pseudo_UPD = 3735 + + VST2LNd32_UPD = 3736 + + VST2LNd8 = 3737 + + VST2LNd8Pseudo = 3738 + + VST2LNd8Pseudo_UPD = 3739 + + VST2LNd8_UPD = 3740 + + VST2LNq16 = 3741 + + VST2LNq16Pseudo = 3742 + + VST2LNq16Pseudo_UPD = 3743 + + VST2LNq16_UPD = 3744 + + VST2LNq32 = 3745 + + VST2LNq32Pseudo = 3746 + + VST2LNq32Pseudo_UPD = 3747 + + VST2LNq32_UPD = 3748 + + VST2b16 = 3749 + + VST2b16wb_fixed = 3750 + + VST2b16wb_register = 3751 + + VST2b32 = 3752 + + VST2b32wb_fixed = 3753 + + VST2b32wb_register = 3754 + + VST2b8 = 3755 + + VST2b8wb_fixed = 3756 + + VST2b8wb_register = 3757 + + VST2d16 = 3758 + + VST2d16wb_fixed = 3759 + + VST2d16wb_register = 3760 + + VST2d32 = 3761 + + VST2d32wb_fixed = 3762 + + VST2d32wb_register = 3763 + + VST2d8 = 3764 + + VST2d8wb_fixed = 3765 + + VST2d8wb_register = 3766 + + VST2q16 = 3767 + + VST2q16Pseudo = 3768 + + VST2q16PseudoWB_fixed = 3769 + + VST2q16PseudoWB_register = 3770 + + VST2q16wb_fixed = 3771 + + VST2q16wb_register = 3772 + + VST2q32 = 3773 + + VST2q32Pseudo = 3774 + + VST2q32PseudoWB_fixed = 3775 + + VST2q32PseudoWB_register = 3776 + + VST2q32wb_fixed = 3777 + + VST2q32wb_register = 3778 + + VST2q8 = 3779 + + VST2q8Pseudo = 3780 + + VST2q8PseudoWB_fixed = 3781 + + VST2q8PseudoWB_register = 3782 + + VST2q8wb_fixed = 3783 + + VST2q8wb_register = 3784 + + VST3LNd16 = 3785 + + VST3LNd16Pseudo = 3786 + + VST3LNd16Pseudo_UPD = 3787 + + VST3LNd16_UPD = 3788 + + VST3LNd32 = 3789 + + VST3LNd32Pseudo = 3790 + + VST3LNd32Pseudo_UPD = 3791 + + VST3LNd32_UPD = 3792 + + VST3LNd8 = 3793 + + VST3LNd8Pseudo = 3794 + + VST3LNd8Pseudo_UPD = 3795 + + VST3LNd8_UPD = 3796 + + VST3LNq16 = 3797 + + VST3LNq16Pseudo = 3798 + + VST3LNq16Pseudo_UPD = 3799 + + VST3LNq16_UPD = 3800 + + VST3LNq32 = 3801 + + VST3LNq32Pseudo = 3802 + + VST3LNq32Pseudo_UPD = 3803 + + VST3LNq32_UPD = 3804 + + VST3d16 = 3805 + + VST3d16Pseudo = 3806 + + VST3d16Pseudo_UPD = 3807 + + VST3d16_UPD = 3808 + + VST3d32 = 3809 + + VST3d32Pseudo = 3810 + + VST3d32Pseudo_UPD = 3811 + + VST3d32_UPD = 3812 + + VST3d8 = 3813 + + VST3d8Pseudo = 3814 + + VST3d8Pseudo_UPD = 3815 + + VST3d8_UPD = 3816 + + VST3q16 = 3817 + + VST3q16Pseudo_UPD = 3818 + + VST3q16_UPD = 3819 + + VST3q16oddPseudo = 3820 + + VST3q16oddPseudo_UPD = 3821 + + VST3q32 = 3822 + + VST3q32Pseudo_UPD = 3823 + + VST3q32_UPD = 3824 + + VST3q32oddPseudo = 3825 + + VST3q32oddPseudo_UPD = 3826 + + VST3q8 = 3827 + + VST3q8Pseudo_UPD = 3828 + + VST3q8_UPD = 3829 + + VST3q8oddPseudo = 3830 + + VST3q8oddPseudo_UPD = 3831 + + VST4LNd16 = 3832 + + VST4LNd16Pseudo = 3833 + + VST4LNd16Pseudo_UPD = 3834 + + VST4LNd16_UPD = 3835 + + VST4LNd32 = 3836 + + VST4LNd32Pseudo = 3837 + + VST4LNd32Pseudo_UPD = 3838 + + VST4LNd32_UPD = 3839 + + VST4LNd8 = 3840 + + VST4LNd8Pseudo = 3841 + + VST4LNd8Pseudo_UPD = 3842 + + VST4LNd8_UPD = 3843 + + VST4LNq16 = 3844 + + VST4LNq16Pseudo = 3845 + + VST4LNq16Pseudo_UPD = 3846 + + VST4LNq16_UPD = 3847 + + VST4LNq32 = 3848 + + VST4LNq32Pseudo = 3849 + + VST4LNq32Pseudo_UPD = 3850 + + VST4LNq32_UPD = 3851 + + VST4d16 = 3852 + + VST4d16Pseudo = 3853 + + VST4d16Pseudo_UPD = 3854 + + VST4d16_UPD = 3855 + + VST4d32 = 3856 + + VST4d32Pseudo = 3857 + + VST4d32Pseudo_UPD = 3858 + + VST4d32_UPD = 3859 + + VST4d8 = 3860 + + VST4d8Pseudo = 3861 + + VST4d8Pseudo_UPD = 3862 + + VST4d8_UPD = 3863 + + VST4q16 = 3864 + + VST4q16Pseudo_UPD = 3865 + + VST4q16_UPD = 3866 + + VST4q16oddPseudo = 3867 + + VST4q16oddPseudo_UPD = 3868 + + VST4q32 = 3869 + + VST4q32Pseudo_UPD = 3870 + + VST4q32_UPD = 3871 + + VST4q32oddPseudo = 3872 + + VST4q32oddPseudo_UPD = 3873 + + VST4q8 = 3874 + + VST4q8Pseudo_UPD = 3875 + + VST4q8_UPD = 3876 + + VST4q8oddPseudo = 3877 + + VST4q8oddPseudo_UPD = 3878 + + VSTMDDB_UPD = 3879 + + VSTMDIA = 3880 + + VSTMDIA_UPD = 3881 + + VSTMQIA = 3882 + + VSTMSDB_UPD = 3883 + + VSTMSIA = 3884 + + VSTMSIA_UPD = 3885 + + VSTRD = 3886 + + VSTRH = 3887 + + VSTRS = 3888 + + VSTR_FPCXTNS_off = 3889 + + VSTR_FPCXTNS_post = 3890 + + VSTR_FPCXTNS_pre = 3891 + + VSTR_FPCXTS_off = 3892 + + VSTR_FPCXTS_post = 3893 + + VSTR_FPCXTS_pre = 3894 + + VSTR_FPSCR_NZCVQC_off = 3895 + + VSTR_FPSCR_NZCVQC_post = 3896 + + VSTR_FPSCR_NZCVQC_pre = 3897 + + VSTR_FPSCR_off = 3898 + + VSTR_FPSCR_post = 3899 + + VSTR_FPSCR_pre = 3900 + + VSTR_P0_off = 3901 + + VSTR_P0_post = 3902 + + VSTR_P0_pre = 3903 + + VSTR_VPR_off = 3904 + + VSTR_VPR_post = 3905 + + VSTR_VPR_pre = 3906 + + VSUBD = 3907 + + VSUBH = 3908 + + VSUBHNv2i32 = 3909 + + VSUBHNv4i16 = 3910 + + VSUBHNv8i8 = 3911 + + VSUBLsv2i64 = 3912 + + VSUBLsv4i32 = 3913 + + VSUBLsv8i16 = 3914 + + VSUBLuv2i64 = 3915 + + VSUBLuv4i32 = 3916 + + VSUBLuv8i16 = 3917 + + VSUBS = 3918 + + VSUBWsv2i64 = 3919 + + VSUBWsv4i32 = 3920 + + VSUBWsv8i16 = 3921 + + VSUBWuv2i64 = 3922 + + VSUBWuv4i32 = 3923 + + VSUBWuv8i16 = 3924 + + VSUBfd = 3925 + + VSUBfq = 3926 + + VSUBhd = 3927 + + VSUBhq = 3928 + + VSUBv16i8 = 3929 + + VSUBv1i64 = 3930 + + VSUBv2i32 = 3931 + + VSUBv2i64 = 3932 + + VSUBv4i16 = 3933 + + VSUBv4i32 = 3934 + + VSUBv8i16 = 3935 + + VSUBv8i8 = 3936 + + VSUDOTDI = 3937 + + VSUDOTQI = 3938 + + VSWPd = 3939 + + VSWPq = 3940 + + VTBL1 = 3941 + + VTBL2 = 3942 + + VTBL3 = 3943 + + VTBL3Pseudo = 3944 + + VTBL4 = 3945 + + VTBL4Pseudo = 3946 + + VTBX1 = 3947 + + VTBX2 = 3948 + + VTBX3 = 3949 + + VTBX3Pseudo = 3950 + + VTBX4 = 3951 + + VTBX4Pseudo = 3952 + + VTOSHD = 3953 + + VTOSHH = 3954 + + VTOSHS = 3955 + + VTOSIRD = 3956 + + VTOSIRH = 3957 + + VTOSIRS = 3958 + + VTOSIZD = 3959 + + VTOSIZH = 3960 + + VTOSIZS = 3961 + + VTOSLD = 3962 + + VTOSLH = 3963 + + VTOSLS = 3964 + + VTOUHD = 3965 + + VTOUHH = 3966 + + VTOUHS = 3967 + + VTOUIRD = 3968 + + VTOUIRH = 3969 + + VTOUIRS = 3970 + + VTOUIZD = 3971 + + VTOUIZH = 3972 + + VTOUIZS = 3973 + + VTOULD = 3974 + + VTOULH = 3975 + + VTOULS = 3976 + + VTRNd16 = 3977 + + VTRNd32 = 3978 + + VTRNd8 = 3979 + + VTRNq16 = 3980 + + VTRNq32 = 3981 + + VTRNq8 = 3982 + + VTSTv16i8 = 3983 + + VTSTv2i32 = 3984 + + VTSTv4i16 = 3985 + + VTSTv4i32 = 3986 + + VTSTv8i16 = 3987 + + VTSTv8i8 = 3988 + + VUDOTD = 3989 + + VUDOTDI = 3990 + + VUDOTQ = 3991 + + VUDOTQI = 3992 + + VUHTOD = 3993 + + VUHTOH = 3994 + + VUHTOS = 3995 + + VUITOD = 3996 + + VUITOH = 3997 + + VUITOS = 3998 + + VULTOD = 3999 + + VULTOH = 4000 + + VULTOS = 4001 + + VUMMLA = 4002 + + VUSDOTD = 4003 + + VUSDOTDI = 4004 + + VUSDOTQ = 4005 + + VUSDOTQI = 4006 + + VUSMMLA = 4007 + + VUZPd16 = 4008 + + VUZPd8 = 4009 + + VUZPq16 = 4010 + + VUZPq32 = 4011 + + VUZPq8 = 4012 + + VZIPd16 = 4013 + + VZIPd8 = 4014 + + VZIPq16 = 4015 + + VZIPq32 = 4016 + + VZIPq8 = 4017 + + sysLDMDA = 4018 + + sysLDMDA_UPD = 4019 + + sysLDMDB = 4020 + + sysLDMDB_UPD = 4021 + + sysLDMIA = 4022 + + sysLDMIA_UPD = 4023 + + sysLDMIB = 4024 + + sysLDMIB_UPD = 4025 + + sysSTMDA = 4026 + + sysSTMDA_UPD = 4027 + + sysSTMDB = 4028 + + sysSTMDB_UPD = 4029 + + sysSTMIA = 4030 + + sysSTMIA_UPD = 4031 + + sysSTMIB = 4032 + + sysSTMIB_UPD = 4033 + + t2ADCri = 4034 + + t2ADCrr = 4035 + + t2ADCrs = 4036 + + t2ADDri = 4037 + + t2ADDri12 = 4038 + + t2ADDrr = 4039 + + t2ADDrs = 4040 + + t2ADDspImm = 4041 + + t2ADDspImm12 = 4042 + + t2ADR = 4043 + + t2ANDri = 4044 + + t2ANDrr = 4045 + + t2ANDrs = 4046 + + t2ASRri = 4047 + + t2ASRrr = 4048 + + t2ASRs1 = 4049 + + t2AUT = 4050 + + t2AUTG = 4051 + + t2B = 4052 + + t2BFC = 4053 + + t2BFI = 4054 + + t2BFLi = 4055 + + t2BFLr = 4056 + + t2BFi = 4057 + + t2BFic = 4058 + + t2BFr = 4059 + + t2BICri = 4060 + + t2BICrr = 4061 + + t2BICrs = 4062 + + t2BTI = 4063 + + t2BXAUT = 4064 + + t2BXJ = 4065 + + t2Bcc = 4066 + + t2CDP = 4067 + + t2CDP2 = 4068 + + t2CLREX = 4069 + + t2CLRM = 4070 + + t2CLZ = 4071 + + t2CMNri = 4072 + + t2CMNzrr = 4073 + + t2CMNzrs = 4074 + + t2CMPri = 4075 + + t2CMPrr = 4076 + + t2CMPrs = 4077 + + t2CPS1p = 4078 + + t2CPS2p = 4079 + + t2CPS3p = 4080 + + t2CRC32B = 4081 + + t2CRC32CB = 4082 + + t2CRC32CH = 4083 + + t2CRC32CW = 4084 + + t2CRC32H = 4085 + + t2CRC32W = 4086 + + t2CSEL = 4087 + + t2CSINC = 4088 + + t2CSINV = 4089 + + t2CSNEG = 4090 + + t2DBG = 4091 + + t2DCPS1 = 4092 + + t2DCPS2 = 4093 + + t2DCPS3 = 4094 + + t2DLS = 4095 + + t2DMB = 4096 + + t2DSB = 4097 + + t2EORri = 4098 + + t2EORrr = 4099 + + t2EORrs = 4100 + + t2HINT = 4101 + + t2HVC = 4102 + + t2ISB = 4103 + + t2IT = 4104 + + t2Int_eh_sjlj_setjmp = 4105 + + t2Int_eh_sjlj_setjmp_nofp = 4106 + + t2LDA = 4107 + + t2LDAB = 4108 + + t2LDAEX = 4109 + + t2LDAEXB = 4110 + + t2LDAEXD = 4111 + + t2LDAEXH = 4112 + + t2LDAH = 4113 + + t2LDC2L_OFFSET = 4114 + + t2LDC2L_OPTION = 4115 + + t2LDC2L_POST = 4116 + + t2LDC2L_PRE = 4117 + + t2LDC2_OFFSET = 4118 + + t2LDC2_OPTION = 4119 + + t2LDC2_POST = 4120 + + t2LDC2_PRE = 4121 + + t2LDCL_OFFSET = 4122 + + t2LDCL_OPTION = 4123 + + t2LDCL_POST = 4124 + + t2LDCL_PRE = 4125 + + t2LDC_OFFSET = 4126 + + t2LDC_OPTION = 4127 + + t2LDC_POST = 4128 + + t2LDC_PRE = 4129 + + t2LDMDB = 4130 + + t2LDMDB_UPD = 4131 + + t2LDMIA = 4132 + + t2LDMIA_UPD = 4133 + + t2LDRBT = 4134 + + t2LDRB_POST = 4135 + + t2LDRB_PRE = 4136 + + t2LDRBi12 = 4137 + + t2LDRBi8 = 4138 + + t2LDRBpci = 4139 + + t2LDRBs = 4140 + + t2LDRD_POST = 4141 + + t2LDRD_PRE = 4142 + + t2LDRDi8 = 4143 + + t2LDREX = 4144 + + t2LDREXB = 4145 + + t2LDREXD = 4146 + + t2LDREXH = 4147 + + t2LDRHT = 4148 + + t2LDRH_POST = 4149 + + t2LDRH_PRE = 4150 + + t2LDRHi12 = 4151 + + t2LDRHi8 = 4152 + + t2LDRHpci = 4153 + + t2LDRHs = 4154 + + t2LDRSBT = 4155 + + t2LDRSB_POST = 4156 + + t2LDRSB_PRE = 4157 + + t2LDRSBi12 = 4158 + + t2LDRSBi8 = 4159 + + t2LDRSBpci = 4160 + + t2LDRSBs = 4161 + + t2LDRSHT = 4162 + + t2LDRSH_POST = 4163 + + t2LDRSH_PRE = 4164 + + t2LDRSHi12 = 4165 + + t2LDRSHi8 = 4166 + + t2LDRSHpci = 4167 + + t2LDRSHs = 4168 + + t2LDRT = 4169 + + t2LDR_POST = 4170 + + t2LDR_PRE = 4171 + + t2LDRi12 = 4172 + + t2LDRi8 = 4173 + + t2LDRpci = 4174 + + t2LDRs = 4175 + + t2LE = 4176 + + t2LEUpdate = 4177 + + t2LSLri = 4178 + + t2LSLrr = 4179 + + t2LSRri = 4180 + + t2LSRrr = 4181 + + t2LSRs1 = 4182 + + t2MCR = 4183 + + t2MCR2 = 4184 + + t2MCRR = 4185 + + t2MCRR2 = 4186 + + t2MLA = 4187 + + t2MLS = 4188 + + t2MOVTi16 = 4189 + + t2MOVi = 4190 + + t2MOVi16 = 4191 + + t2MOVr = 4192 + + t2MRC = 4193 + + t2MRC2 = 4194 + + t2MRRC = 4195 + + t2MRRC2 = 4196 + + t2MRS_AR = 4197 + + t2MRS_M = 4198 + + t2MRSbanked = 4199 + + t2MRSsys_AR = 4200 + + t2MSR_AR = 4201 + + t2MSR_M = 4202 + + t2MSRbanked = 4203 + + t2MUL = 4204 + + t2MVNi = 4205 + + t2MVNr = 4206 + + t2MVNs = 4207 + + t2ORNri = 4208 + + t2ORNrr = 4209 + + t2ORNrs = 4210 + + t2ORRri = 4211 + + t2ORRrr = 4212 + + t2ORRrs = 4213 + + t2PAC = 4214 + + t2PACBTI = 4215 + + t2PACG = 4216 + + t2PKHBT = 4217 + + t2PKHTB = 4218 + + t2PLDWi12 = 4219 + + t2PLDWi8 = 4220 + + t2PLDWs = 4221 + + t2PLDi12 = 4222 + + t2PLDi8 = 4223 + + t2PLDpci = 4224 + + t2PLDs = 4225 + + t2PLIi12 = 4226 + + t2PLIi8 = 4227 + + t2PLIpci = 4228 + + t2PLIs = 4229 + + t2QADD = 4230 + + t2QADD16 = 4231 + + t2QADD8 = 4232 + + t2QASX = 4233 + + t2QDADD = 4234 + + t2QDSUB = 4235 + + t2QSAX = 4236 + + t2QSUB = 4237 + + t2QSUB16 = 4238 + + t2QSUB8 = 4239 + + t2RBIT = 4240 + + t2REV = 4241 + + t2REV16 = 4242 + + t2REVSH = 4243 + + t2RFEDB = 4244 + + t2RFEDBW = 4245 + + t2RFEIA = 4246 + + t2RFEIAW = 4247 + + t2RORri = 4248 + + t2RORrr = 4249 + + t2RRX = 4250 + + t2RSBri = 4251 + + t2RSBrr = 4252 + + t2RSBrs = 4253 + + t2SADD16 = 4254 + + t2SADD8 = 4255 + + t2SASX = 4256 + + t2SB = 4257 + + t2SBCri = 4258 + + t2SBCrr = 4259 + + t2SBCrs = 4260 + + t2SBFX = 4261 + + t2SDIV = 4262 + + t2SEL = 4263 + + t2SETPAN = 4264 + + t2SG = 4265 + + t2SHADD16 = 4266 + + t2SHADD8 = 4267 + + t2SHASX = 4268 + + t2SHSAX = 4269 + + t2SHSUB16 = 4270 + + t2SHSUB8 = 4271 + + t2SMC = 4272 + + t2SMLABB = 4273 + + t2SMLABT = 4274 + + t2SMLAD = 4275 + + t2SMLADX = 4276 + + t2SMLAL = 4277 + + t2SMLALBB = 4278 + + t2SMLALBT = 4279 + + t2SMLALD = 4280 + + t2SMLALDX = 4281 + + t2SMLALTB = 4282 + + t2SMLALTT = 4283 + + t2SMLATB = 4284 + + t2SMLATT = 4285 + + t2SMLAWB = 4286 + + t2SMLAWT = 4287 + + t2SMLSD = 4288 + + t2SMLSDX = 4289 + + t2SMLSLD = 4290 + + t2SMLSLDX = 4291 + + t2SMMLA = 4292 + + t2SMMLAR = 4293 + + t2SMMLS = 4294 + + t2SMMLSR = 4295 + + t2SMMUL = 4296 + + t2SMMULR = 4297 + + t2SMUAD = 4298 + + t2SMUADX = 4299 + + t2SMULBB = 4300 + + t2SMULBT = 4301 + + t2SMULL = 4302 + + t2SMULTB = 4303 + + t2SMULTT = 4304 + + t2SMULWB = 4305 + + t2SMULWT = 4306 + + t2SMUSD = 4307 + + t2SMUSDX = 4308 + + t2SRSDB = 4309 + + t2SRSDB_UPD = 4310 + + t2SRSIA = 4311 + + t2SRSIA_UPD = 4312 + + t2SSAT = 4313 + + t2SSAT16 = 4314 + + t2SSAX = 4315 + + t2SSUB16 = 4316 + + t2SSUB8 = 4317 + + t2STC2L_OFFSET = 4318 + + t2STC2L_OPTION = 4319 + + t2STC2L_POST = 4320 + + t2STC2L_PRE = 4321 + + t2STC2_OFFSET = 4322 + + t2STC2_OPTION = 4323 + + t2STC2_POST = 4324 + + t2STC2_PRE = 4325 + + t2STCL_OFFSET = 4326 + + t2STCL_OPTION = 4327 + + t2STCL_POST = 4328 + + t2STCL_PRE = 4329 + + t2STC_OFFSET = 4330 + + t2STC_OPTION = 4331 + + t2STC_POST = 4332 + + t2STC_PRE = 4333 + + t2STL = 4334 + + t2STLB = 4335 + + t2STLEX = 4336 + + t2STLEXB = 4337 + + t2STLEXD = 4338 + + t2STLEXH = 4339 + + t2STLH = 4340 + + t2STMDB = 4341 + + t2STMDB_UPD = 4342 + + t2STMIA = 4343 + + t2STMIA_UPD = 4344 + + t2STRBT = 4345 + + t2STRB_POST = 4346 + + t2STRB_PRE = 4347 + + t2STRBi12 = 4348 + + t2STRBi8 = 4349 + + t2STRBs = 4350 + + t2STRD_POST = 4351 + + t2STRD_PRE = 4352 + + t2STRDi8 = 4353 + + t2STREX = 4354 + + t2STREXB = 4355 + + t2STREXD = 4356 + + t2STREXH = 4357 + + t2STRHT = 4358 + + t2STRH_POST = 4359 + + t2STRH_PRE = 4360 + + t2STRHi12 = 4361 + + t2STRHi8 = 4362 + + t2STRHs = 4363 + + t2STRT = 4364 + + t2STR_POST = 4365 + + t2STR_PRE = 4366 + + t2STRi12 = 4367 + + t2STRi8 = 4368 + + t2STRs = 4369 + + t2SUBS_PC_LR = 4370 + + t2SUBri = 4371 + + t2SUBri12 = 4372 + + t2SUBrr = 4373 + + t2SUBrs = 4374 + + t2SUBspImm = 4375 + + t2SUBspImm12 = 4376 + + t2SXTAB = 4377 + + t2SXTAB16 = 4378 + + t2SXTAH = 4379 + + t2SXTB = 4380 + + t2SXTB16 = 4381 + + t2SXTH = 4382 + + t2TBB = 4383 + + t2TBH = 4384 + + t2TEQri = 4385 + + t2TEQrr = 4386 + + t2TEQrs = 4387 + + t2TSB = 4388 + + t2TSTri = 4389 + + t2TSTrr = 4390 + + t2TSTrs = 4391 + + t2TT = 4392 + + t2TTA = 4393 + + t2TTAT = 4394 + + t2TTT = 4395 + + t2UADD16 = 4396 + + t2UADD8 = 4397 + + t2UASX = 4398 + + t2UBFX = 4399 + + t2UDF = 4400 + + t2UDIV = 4401 + + t2UHADD16 = 4402 + + t2UHADD8 = 4403 + + t2UHASX = 4404 + + t2UHSAX = 4405 + + t2UHSUB16 = 4406 + + t2UHSUB8 = 4407 + + t2UMAAL = 4408 + + t2UMLAL = 4409 + + t2UMULL = 4410 + + t2UQADD16 = 4411 + + t2UQADD8 = 4412 + + t2UQASX = 4413 + + t2UQSAX = 4414 + + t2UQSUB16 = 4415 + + t2UQSUB8 = 4416 + + t2USAD8 = 4417 + + t2USADA8 = 4418 + + t2USAT = 4419 + + t2USAT16 = 4420 + + t2USAX = 4421 + + t2USUB16 = 4422 + + t2USUB8 = 4423 + + t2UXTAB = 4424 + + t2UXTAB16 = 4425 + + t2UXTAH = 4426 + + t2UXTB = 4427 + + t2UXTB16 = 4428 + + t2UXTH = 4429 + + t2WLS = 4430 + + tADC = 4431 + + tADDhirr = 4432 + + tADDi3 = 4433 + + tADDi8 = 4434 + + tADDrSP = 4435 + + tADDrSPi = 4436 + + tADDrr = 4437 + + tADDspi = 4438 + + tADDspr = 4439 + + tADR = 4440 + + tAND = 4441 + + tASRri = 4442 + + tASRrr = 4443 + + tB = 4444 + + tBIC = 4445 + + tBKPT = 4446 + + tBL = 4447 + + tBLXNSr = 4448 + + tBLXi = 4449 + + tBLXr = 4450 + + tBX = 4451 + + tBXNS = 4452 + + tBcc = 4453 + + tCBNZ = 4454 + + tCBZ = 4455 + + tCMNz = 4456 + + tCMPhir = 4457 + + tCMPi8 = 4458 + + tCMPr = 4459 + + tCPS = 4460 + + tEOR = 4461 + + tHINT = 4462 + + tHLT = 4463 + + tInt_WIN_eh_sjlj_longjmp = 4464 + + tInt_eh_sjlj_longjmp = 4465 + + tInt_eh_sjlj_setjmp = 4466 + + tLDMIA = 4467 + + tLDRBi = 4468 + + tLDRBr = 4469 + + tLDRHi = 4470 + + tLDRHr = 4471 + + tLDRSB = 4472 + + tLDRSH = 4473 + + tLDRi = 4474 + + tLDRpci = 4475 + + tLDRr = 4476 + + tLDRspi = 4477 + + tLSLri = 4478 + + tLSLrr = 4479 + + tLSRri = 4480 + + tLSRrr = 4481 + + tMOVSr = 4482 + + tMOVi8 = 4483 + + tMOVr = 4484 + + tMUL = 4485 + + tMVN = 4486 + + tORR = 4487 + + tPICADD = 4488 + + tPOP = 4489 + + tPUSH = 4490 + + tREV = 4491 + + tREV16 = 4492 + + tREVSH = 4493 + + tROR = 4494 + + tRSB = 4495 + + tSBC = 4496 + + tSETEND = 4497 + + tSTMIA_UPD = 4498 + + tSTRBi = 4499 + + tSTRBr = 4500 + + tSTRHi = 4501 + + tSTRHr = 4502 + + tSTRi = 4503 + + tSTRr = 4504 + + tSTRspi = 4505 + + tSUBi3 = 4506 + + tSUBi8 = 4507 + + tSUBrr = 4508 + + tSUBspi = 4509 + + tSVC = 4510 + + tSXTB = 4511 + + tSXTH = 4512 + + tTRAP = 4513 + + tTST = 4514 + + tUDF = 4515 + + tUXTB = 4516 + + tUXTH = 4517 + + t__brkdiv0 = 4518 + + INSTRUCTION_LIST_END = 4519 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... diff --git a/vendor/lief/api/python/lief/assembly/ebpf/__init__.pyi b/vendor/lief/api/python/lief/assembly/ebpf/__init__.pyi new file mode 100644 index 0000000..e80d863 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/ebpf/__init__.pyi @@ -0,0 +1,1124 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.ebpf import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ADJCALLSTACKDOWN = 322 + + ADJCALLSTACKUP = 323 + + FI_ri = 324 + + LDIMM64 = 325 + + MEMCPY = 326 + + Select = 327 + + Select_32 = 328 + + Select_32_64 = 329 + + Select_64_32 = 330 + + Select_Ri = 331 + + Select_Ri_32 = 332 + + Select_Ri_32_64 = 333 + + Select_Ri_64_32 = 334 + + ADDR_SPACE_CAST = 335 + + ADD_ri = 336 + + ADD_ri_32 = 337 + + ADD_rr = 338 + + ADD_rr_32 = 339 + + AND_ri = 340 + + AND_ri_32 = 341 + + AND_rr = 342 + + AND_rr_32 = 343 + + BE16 = 344 + + BE32 = 345 + + BE64 = 346 + + BSWAP16 = 347 + + BSWAP32 = 348 + + BSWAP64 = 349 + + CMPXCHGD = 350 + + CMPXCHGW32 = 351 + + CORE_LD32 = 352 + + CORE_LD64 = 353 + + CORE_SHIFT = 354 + + CORE_ST = 355 + + DIV_ri = 356 + + DIV_ri_32 = 357 + + DIV_rr = 358 + + DIV_rr_32 = 359 + + JAL = 360 + + JALX = 361 + + JCOND = 362 + + JEQ_ri = 363 + + JEQ_ri_32 = 364 + + JEQ_rr = 365 + + JEQ_rr_32 = 366 + + JMP = 367 + + JMPL = 368 + + JNE_ri = 369 + + JNE_ri_32 = 370 + + JNE_rr = 371 + + JNE_rr_32 = 372 + + JSET_ri = 373 + + JSET_ri_32 = 374 + + JSET_rr = 375 + + JSET_rr_32 = 376 + + JSGE_ri = 377 + + JSGE_ri_32 = 378 + + JSGE_rr = 379 + + JSGE_rr_32 = 380 + + JSGT_ri = 381 + + JSGT_ri_32 = 382 + + JSGT_rr = 383 + + JSGT_rr_32 = 384 + + JSLE_ri = 385 + + JSLE_ri_32 = 386 + + JSLE_rr = 387 + + JSLE_rr_32 = 388 + + JSLT_ri = 389 + + JSLT_ri_32 = 390 + + JSLT_rr = 391 + + JSLT_rr_32 = 392 + + JUGE_ri = 393 + + JUGE_ri_32 = 394 + + JUGE_rr = 395 + + JUGE_rr_32 = 396 + + JUGT_ri = 397 + + JUGT_ri_32 = 398 + + JUGT_rr = 399 + + JUGT_rr_32 = 400 + + JULE_ri = 401 + + JULE_ri_32 = 402 + + JULE_rr = 403 + + JULE_rr_32 = 404 + + JULT_ri = 405 + + JULT_ri_32 = 406 + + JULT_rr = 407 + + JULT_rr_32 = 408 + + JX = 409 + + LDB = 410 + + LDB32 = 411 + + LDBACQ32 = 412 + + LDBSX = 413 + + LDD = 414 + + LDDACQ = 415 + + LDH = 416 + + LDH32 = 417 + + LDHACQ32 = 418 + + LDHSX = 419 + + LDW = 420 + + LDW32 = 421 + + LDWACQ32 = 422 + + LDWSX = 423 + + LD_ABS_B = 424 + + LD_ABS_H = 425 + + LD_ABS_W = 426 + + LD_IND_B = 427 + + LD_IND_H = 428 + + LD_IND_W = 429 + + LD_imm64 = 430 + + LD_pseudo = 431 + + LE16 = 432 + + LE32 = 433 + + LE64 = 434 + + MOD_ri = 435 + + MOD_ri_32 = 436 + + MOD_rr = 437 + + MOD_rr_32 = 438 + + MOVSX_rr_16 = 439 + + MOVSX_rr_32 = 440 + + MOVSX_rr_32_16 = 441 + + MOVSX_rr_32_8 = 442 + + MOVSX_rr_8 = 443 + + MOV_32_64 = 444 + + MOV_ri = 445 + + MOV_ri_32 = 446 + + MOV_rr = 447 + + MOV_rr_32 = 448 + + MUL_ri = 449 + + MUL_ri_32 = 450 + + MUL_rr = 451 + + MUL_rr_32 = 452 + + NEG_32 = 453 + + NEG_64 = 454 + + NOP = 455 + + OR_ri = 456 + + OR_ri_32 = 457 + + OR_rr = 458 + + OR_rr_32 = 459 + + RET = 460 + + SDIV_ri = 461 + + SDIV_ri_32 = 462 + + SDIV_rr = 463 + + SDIV_rr_32 = 464 + + SLL_ri = 465 + + SLL_ri_32 = 466 + + SLL_rr = 467 + + SLL_rr_32 = 468 + + SMOD_ri = 469 + + SMOD_ri_32 = 470 + + SMOD_rr = 471 + + SMOD_rr_32 = 472 + + SRA_ri = 473 + + SRA_ri_32 = 474 + + SRA_rr = 475 + + SRA_rr_32 = 476 + + SRL_ri = 477 + + SRL_ri_32 = 478 + + SRL_rr = 479 + + SRL_rr_32 = 480 + + STB = 481 + + STB32 = 482 + + STBREL32 = 483 + + STB_imm = 484 + + STD = 485 + + STDREL = 486 + + STD_imm = 487 + + STH = 488 + + STH32 = 489 + + STHREL32 = 490 + + STH_imm = 491 + + STW = 492 + + STW32 = 493 + + STWREL32 = 494 + + STW_imm = 495 + + SUB_ri = 496 + + SUB_ri_32 = 497 + + SUB_rr = 498 + + SUB_rr_32 = 499 + + XADDD = 500 + + XADDW = 501 + + XADDW32 = 502 + + XANDD = 503 + + XANDW32 = 504 + + XCHGD = 505 + + XCHGW32 = 506 + + XFADDD = 507 + + XFADDW32 = 508 + + XFANDD = 509 + + XFANDW32 = 510 + + XFORD = 511 + + XFORW32 = 512 + + XFXORD = 513 + + XFXORW32 = 514 + + XORD = 515 + + XORW32 = 516 + + XOR_ri = 517 + + XOR_ri_32 = 518 + + XOR_rr = 519 + + XOR_rr_32 = 520 + + XXORD = 521 + + XXORW32 = 522 + + INSTRUCTION_LIST_END = 523 + +class REG(enum.Enum): + NoRegister = 0 + + R0 = 1 + + R1 = 2 + + R2 = 3 + + R3 = 4 + + R4 = 5 + + R5 = 6 + + R6 = 7 + + R7 = 8 + + R8 = 9 + + R9 = 10 + + R10 = 11 + + R11 = 12 + + W0 = 13 + + W1 = 14 + + W2 = 15 + + W3 = 16 + + W4 = 17 + + W5 = 18 + + W6 = 19 + + W7 = 20 + + W8 = 21 + + W9 = 22 + + W10 = 23 + + W11 = 24 + + NUM_TARGET_REGS = 25 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/ebpf/operands.pyi b/vendor/lief/api/python/lief/assembly/ebpf/operands.pyi new file mode 100644 index 0000000..3fc459d --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/ebpf/operands.pyi @@ -0,0 +1,29 @@ +import lief.assembly.ebpf + + +class Immediate(lief.assembly.ebpf.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.ebpf.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> lief.assembly.ebpf.REG: ... + +class Memory(lief.assembly.ebpf.Operand): + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.ebpf.REG: ... + + @property + def displacement(self) -> int: ... + +class PCRelative(lief.assembly.ebpf.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/assembly/mips/__init__.pyi b/vendor/lief/api/python/lief/assembly/mips/__init__.pyi new file mode 100644 index 0000000..22b264a --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/mips/__init__.pyi @@ -0,0 +1,6752 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.mips import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ABSMacro = 322 + + ADJCALLSTACKDOWN = 323 + + ADJCALLSTACKUP = 324 + + AND_V_D_PSEUDO = 325 + + AND_V_H_PSEUDO = 326 + + AND_V_W_PSEUDO = 327 + + ATOMIC_CMP_SWAP_I16 = 328 + + ATOMIC_CMP_SWAP_I16_POSTRA = 329 + + ATOMIC_CMP_SWAP_I32 = 330 + + ATOMIC_CMP_SWAP_I32_POSTRA = 331 + + ATOMIC_CMP_SWAP_I64 = 332 + + ATOMIC_CMP_SWAP_I64_POSTRA = 333 + + ATOMIC_CMP_SWAP_I8 = 334 + + ATOMIC_CMP_SWAP_I8_POSTRA = 335 + + ATOMIC_LOAD_ADD_I16 = 336 + + ATOMIC_LOAD_ADD_I16_POSTRA = 337 + + ATOMIC_LOAD_ADD_I32 = 338 + + ATOMIC_LOAD_ADD_I32_POSTRA = 339 + + ATOMIC_LOAD_ADD_I64 = 340 + + ATOMIC_LOAD_ADD_I64_POSTRA = 341 + + ATOMIC_LOAD_ADD_I8 = 342 + + ATOMIC_LOAD_ADD_I8_POSTRA = 343 + + ATOMIC_LOAD_AND_I16 = 344 + + ATOMIC_LOAD_AND_I16_POSTRA = 345 + + ATOMIC_LOAD_AND_I32 = 346 + + ATOMIC_LOAD_AND_I32_POSTRA = 347 + + ATOMIC_LOAD_AND_I64 = 348 + + ATOMIC_LOAD_AND_I64_POSTRA = 349 + + ATOMIC_LOAD_AND_I8 = 350 + + ATOMIC_LOAD_AND_I8_POSTRA = 351 + + ATOMIC_LOAD_MAX_I16 = 352 + + ATOMIC_LOAD_MAX_I16_POSTRA = 353 + + ATOMIC_LOAD_MAX_I32 = 354 + + ATOMIC_LOAD_MAX_I32_POSTRA = 355 + + ATOMIC_LOAD_MAX_I64 = 356 + + ATOMIC_LOAD_MAX_I64_POSTRA = 357 + + ATOMIC_LOAD_MAX_I8 = 358 + + ATOMIC_LOAD_MAX_I8_POSTRA = 359 + + ATOMIC_LOAD_MIN_I16 = 360 + + ATOMIC_LOAD_MIN_I16_POSTRA = 361 + + ATOMIC_LOAD_MIN_I32 = 362 + + ATOMIC_LOAD_MIN_I32_POSTRA = 363 + + ATOMIC_LOAD_MIN_I64 = 364 + + ATOMIC_LOAD_MIN_I64_POSTRA = 365 + + ATOMIC_LOAD_MIN_I8 = 366 + + ATOMIC_LOAD_MIN_I8_POSTRA = 367 + + ATOMIC_LOAD_NAND_I16 = 368 + + ATOMIC_LOAD_NAND_I16_POSTRA = 369 + + ATOMIC_LOAD_NAND_I32 = 370 + + ATOMIC_LOAD_NAND_I32_POSTRA = 371 + + ATOMIC_LOAD_NAND_I64 = 372 + + ATOMIC_LOAD_NAND_I64_POSTRA = 373 + + ATOMIC_LOAD_NAND_I8 = 374 + + ATOMIC_LOAD_NAND_I8_POSTRA = 375 + + ATOMIC_LOAD_OR_I16 = 376 + + ATOMIC_LOAD_OR_I16_POSTRA = 377 + + ATOMIC_LOAD_OR_I32 = 378 + + ATOMIC_LOAD_OR_I32_POSTRA = 379 + + ATOMIC_LOAD_OR_I64 = 380 + + ATOMIC_LOAD_OR_I64_POSTRA = 381 + + ATOMIC_LOAD_OR_I8 = 382 + + ATOMIC_LOAD_OR_I8_POSTRA = 383 + + ATOMIC_LOAD_SUB_I16 = 384 + + ATOMIC_LOAD_SUB_I16_POSTRA = 385 + + ATOMIC_LOAD_SUB_I32 = 386 + + ATOMIC_LOAD_SUB_I32_POSTRA = 387 + + ATOMIC_LOAD_SUB_I64 = 388 + + ATOMIC_LOAD_SUB_I64_POSTRA = 389 + + ATOMIC_LOAD_SUB_I8 = 390 + + ATOMIC_LOAD_SUB_I8_POSTRA = 391 + + ATOMIC_LOAD_UMAX_I16 = 392 + + ATOMIC_LOAD_UMAX_I16_POSTRA = 393 + + ATOMIC_LOAD_UMAX_I32 = 394 + + ATOMIC_LOAD_UMAX_I32_POSTRA = 395 + + ATOMIC_LOAD_UMAX_I64 = 396 + + ATOMIC_LOAD_UMAX_I64_POSTRA = 397 + + ATOMIC_LOAD_UMAX_I8 = 398 + + ATOMIC_LOAD_UMAX_I8_POSTRA = 399 + + ATOMIC_LOAD_UMIN_I16 = 400 + + ATOMIC_LOAD_UMIN_I16_POSTRA = 401 + + ATOMIC_LOAD_UMIN_I32 = 402 + + ATOMIC_LOAD_UMIN_I32_POSTRA = 403 + + ATOMIC_LOAD_UMIN_I64 = 404 + + ATOMIC_LOAD_UMIN_I64_POSTRA = 405 + + ATOMIC_LOAD_UMIN_I8 = 406 + + ATOMIC_LOAD_UMIN_I8_POSTRA = 407 + + ATOMIC_LOAD_XOR_I16 = 408 + + ATOMIC_LOAD_XOR_I16_POSTRA = 409 + + ATOMIC_LOAD_XOR_I32 = 410 + + ATOMIC_LOAD_XOR_I32_POSTRA = 411 + + ATOMIC_LOAD_XOR_I64 = 412 + + ATOMIC_LOAD_XOR_I64_POSTRA = 413 + + ATOMIC_LOAD_XOR_I8 = 414 + + ATOMIC_LOAD_XOR_I8_POSTRA = 415 + + ATOMIC_SWAP_I16 = 416 + + ATOMIC_SWAP_I16_POSTRA = 417 + + ATOMIC_SWAP_I32 = 418 + + ATOMIC_SWAP_I32_POSTRA = 419 + + ATOMIC_SWAP_I64 = 420 + + ATOMIC_SWAP_I64_POSTRA = 421 + + ATOMIC_SWAP_I8 = 422 + + ATOMIC_SWAP_I8_POSTRA = 423 + + B = 424 + + BAL_BR = 425 + + BAL_BR_MM = 426 + + BEQLImmMacro = 427 + + BGE = 428 + + BGEImmMacro = 429 + + BGEL = 430 + + BGELImmMacro = 431 + + BGEU = 432 + + BGEUImmMacro = 433 + + BGEUL = 434 + + BGEULImmMacro = 435 + + BGT = 436 + + BGTImmMacro = 437 + + BGTL = 438 + + BGTLImmMacro = 439 + + BGTU = 440 + + BGTUImmMacro = 441 + + BGTUL = 442 + + BGTULImmMacro = 443 + + BLE = 444 + + BLEImmMacro = 445 + + BLEL = 446 + + BLELImmMacro = 447 + + BLEU = 448 + + BLEUImmMacro = 449 + + BLEUL = 450 + + BLEULImmMacro = 451 + + BLT = 452 + + BLTImmMacro = 453 + + BLTL = 454 + + BLTLImmMacro = 455 + + BLTU = 456 + + BLTUImmMacro = 457 + + BLTUL = 458 + + BLTULImmMacro = 459 + + BNELImmMacro = 460 + + BPOSGE32_PSEUDO = 461 + + BSEL_D_PSEUDO = 462 + + BSEL_FD_PSEUDO = 463 + + BSEL_FW_PSEUDO = 464 + + BSEL_H_PSEUDO = 465 + + BSEL_W_PSEUDO = 466 + + B_MM = 467 + + B_MMR6_Pseudo = 468 + + B_MM_Pseudo = 469 + + BeqImm = 470 + + BneImm = 471 + + BteqzT8CmpX16 = 472 + + BteqzT8CmpiX16 = 473 + + BteqzT8SltX16 = 474 + + BteqzT8SltiX16 = 475 + + BteqzT8SltiuX16 = 476 + + BteqzT8SltuX16 = 477 + + BtnezT8CmpX16 = 478 + + BtnezT8CmpiX16 = 479 + + BtnezT8SltX16 = 480 + + BtnezT8SltiX16 = 481 + + BtnezT8SltiuX16 = 482 + + BtnezT8SltuX16 = 483 + + BuildPairF64 = 484 + + BuildPairF64_64 = 485 + + CFTC1 = 486 + + CONSTPOOL_ENTRY = 487 + + COPY_FD_PSEUDO = 488 + + COPY_FW_PSEUDO = 489 + + CTTC1 = 490 + + Constant32 = 491 + + DMULImmMacro = 492 + + DMULMacro = 493 + + DMULOMacro = 494 + + DMULOUMacro = 495 + + DROL = 496 + + DROLImm = 497 + + DROR = 498 + + DRORImm = 499 + + DSDivIMacro = 500 + + DSDivMacro = 501 + + DSRemIMacro = 502 + + DSRemMacro = 503 + + DUDivIMacro = 504 + + DUDivMacro = 505 + + DURemIMacro = 506 + + DURemMacro = 507 + + ERet = 508 + + ExtractElementF64 = 509 + + ExtractElementF64_64 = 510 + + FABS_D = 511 + + FABS_W = 512 + + FEXP2_D_1_PSEUDO = 513 + + FEXP2_W_1_PSEUDO = 514 + + FILL_FD_PSEUDO = 515 + + FILL_FW_PSEUDO = 516 + + GotPrologue16 = 517 + + INSERT_B_VIDX64_PSEUDO = 518 + + INSERT_B_VIDX_PSEUDO = 519 + + INSERT_D_VIDX64_PSEUDO = 520 + + INSERT_D_VIDX_PSEUDO = 521 + + INSERT_FD_PSEUDO = 522 + + INSERT_FD_VIDX64_PSEUDO = 523 + + INSERT_FD_VIDX_PSEUDO = 524 + + INSERT_FW_PSEUDO = 525 + + INSERT_FW_VIDX64_PSEUDO = 526 + + INSERT_FW_VIDX_PSEUDO = 527 + + INSERT_H_VIDX64_PSEUDO = 528 + + INSERT_H_VIDX_PSEUDO = 529 + + INSERT_W_VIDX64_PSEUDO = 530 + + INSERT_W_VIDX_PSEUDO = 531 + + JALR64Pseudo = 532 + + JALRHB64Pseudo = 533 + + JALRHBPseudo = 534 + + JALRPseudo = 535 + + JAL_MMR6 = 536 + + JalOneReg = 537 + + JalTwoReg = 538 + + LDMacro = 539 + + LDR_D = 540 + + LDR_W = 541 + + LD_F16 = 542 + + LOAD_ACC128 = 543 + + LOAD_ACC64 = 544 + + LOAD_ACC64DSP = 545 + + LOAD_CCOND_DSP = 546 + + LONG_BRANCH_ADDiu = 547 + + LONG_BRANCH_ADDiu2Op = 548 + + LONG_BRANCH_DADDiu = 549 + + LONG_BRANCH_DADDiu2Op = 550 + + LONG_BRANCH_LUi = 551 + + LONG_BRANCH_LUi2Op = 552 + + LONG_BRANCH_LUi2Op_64 = 553 + + LWM_MM = 554 + + LoadAddrImm32 = 555 + + LoadAddrImm64 = 556 + + LoadAddrReg32 = 557 + + LoadAddrReg64 = 558 + + LoadImm32 = 559 + + LoadImm64 = 560 + + LoadImmDoubleFGR = 561 + + LoadImmDoubleFGR_32 = 562 + + LoadImmDoubleGPR = 563 + + LoadImmSingleFGR = 564 + + LoadImmSingleGPR = 565 + + LwConstant32 = 566 + + MFTACX = 567 + + MFTC0 = 568 + + MFTC1 = 569 + + MFTDSP = 570 + + MFTGPR = 571 + + MFTHC1 = 572 + + MFTHI = 573 + + MFTLO = 574 + + MIPSeh_return32 = 575 + + MIPSeh_return64 = 576 + + MSA_FP_EXTEND_D_PSEUDO = 577 + + MSA_FP_EXTEND_W_PSEUDO = 578 + + MSA_FP_ROUND_D_PSEUDO = 579 + + MSA_FP_ROUND_W_PSEUDO = 580 + + MTTACX = 581 + + MTTC0 = 582 + + MTTC1 = 583 + + MTTDSP = 584 + + MTTGPR = 585 + + MTTHC1 = 586 + + MTTHI = 587 + + MTTLO = 588 + + MULImmMacro = 589 + + MULOMacro = 590 + + MULOUMacro = 591 + + MultRxRy16 = 592 + + MultRxRyRz16 = 593 + + MultuRxRy16 = 594 + + MultuRxRyRz16 = 595 + + NOP = 596 + + NORImm = 597 + + NORImm64 = 598 + + NOR_V_D_PSEUDO = 599 + + NOR_V_H_PSEUDO = 600 + + NOR_V_W_PSEUDO = 601 + + OR_V_D_PSEUDO = 602 + + OR_V_H_PSEUDO = 603 + + OR_V_W_PSEUDO = 604 + + PseudoCMPU_EQ_QB = 605 + + PseudoCMPU_LE_QB = 606 + + PseudoCMPU_LT_QB = 607 + + PseudoCMP_EQ_PH = 608 + + PseudoCMP_LE_PH = 609 + + PseudoCMP_LT_PH = 610 + + PseudoCVT_D32_W = 611 + + PseudoCVT_D64_L = 612 + + PseudoCVT_D64_W = 613 + + PseudoCVT_S_L = 614 + + PseudoCVT_S_W = 615 + + PseudoDMULT = 616 + + PseudoDMULTu = 617 + + PseudoDSDIV = 618 + + PseudoDUDIV = 619 + + PseudoD_SELECT_I = 620 + + PseudoD_SELECT_I64 = 621 + + PseudoIndirectBranch = 622 + + PseudoIndirectBranch64 = 623 + + PseudoIndirectBranch64R6 = 624 + + PseudoIndirectBranchR6 = 625 + + PseudoIndirectBranch_MM = 626 + + PseudoIndirectBranch_MMR6 = 627 + + PseudoIndirectHazardBranch = 628 + + PseudoIndirectHazardBranch64 = 629 + + PseudoIndrectHazardBranch64R6 = 630 + + PseudoIndrectHazardBranchR6 = 631 + + PseudoMADD = 632 + + PseudoMADDU = 633 + + PseudoMADDU_MM = 634 + + PseudoMADD_MM = 635 + + PseudoMFHI = 636 + + PseudoMFHI64 = 637 + + PseudoMFHI_MM = 638 + + PseudoMFLO = 639 + + PseudoMFLO64 = 640 + + PseudoMFLO_MM = 641 + + PseudoMSUB = 642 + + PseudoMSUBU = 643 + + PseudoMSUBU_MM = 644 + + PseudoMSUB_MM = 645 + + PseudoMTLOHI = 646 + + PseudoMTLOHI64 = 647 + + PseudoMTLOHI_DSP = 648 + + PseudoMTLOHI_MM = 649 + + PseudoMULT = 650 + + PseudoMULT_MM = 651 + + PseudoMULTu = 652 + + PseudoMULTu_MM = 653 + + PseudoPICK_PH = 654 + + PseudoPICK_QB = 655 + + PseudoReturn = 656 + + PseudoReturn64 = 657 + + PseudoSDIV = 658 + + PseudoSELECTFP_F_D32 = 659 + + PseudoSELECTFP_F_D64 = 660 + + PseudoSELECTFP_F_I = 661 + + PseudoSELECTFP_F_I64 = 662 + + PseudoSELECTFP_F_S = 663 + + PseudoSELECTFP_T_D32 = 664 + + PseudoSELECTFP_T_D64 = 665 + + PseudoSELECTFP_T_I = 666 + + PseudoSELECTFP_T_I64 = 667 + + PseudoSELECTFP_T_S = 668 + + PseudoSELECT_D32 = 669 + + PseudoSELECT_D64 = 670 + + PseudoSELECT_I = 671 + + PseudoSELECT_I64 = 672 + + PseudoSELECT_S = 673 + + PseudoTRUNC_W_D = 674 + + PseudoTRUNC_W_D32 = 675 + + PseudoTRUNC_W_S = 676 + + PseudoUDIV = 677 + + ROL = 678 + + ROLImm = 679 + + ROR = 680 + + RORImm = 681 + + RetRA = 682 + + RetRA16 = 683 + + SDC1_M1 = 684 + + SDIV_MM_Pseudo = 685 + + SDMacro = 686 + + SDivIMacro = 687 + + SDivMacro = 688 + + SEQIMacro = 689 + + SEQMacro = 690 + + SGE = 691 + + SGEImm = 692 + + SGEImm64 = 693 + + SGEU = 694 + + SGEUImm = 695 + + SGEUImm64 = 696 + + SGTImm = 697 + + SGTImm64 = 698 + + SGTUImm = 699 + + SGTUImm64 = 700 + + SLE = 701 + + SLEImm = 702 + + SLEImm64 = 703 + + SLEU = 704 + + SLEUImm = 705 + + SLEUImm64 = 706 + + SLTImm64 = 707 + + SLTUImm64 = 708 + + SNEIMacro = 709 + + SNEMacro = 710 + + SNZ_B_PSEUDO = 711 + + SNZ_D_PSEUDO = 712 + + SNZ_H_PSEUDO = 713 + + SNZ_V_PSEUDO = 714 + + SNZ_W_PSEUDO = 715 + + SRemIMacro = 716 + + SRemMacro = 717 + + STORE_ACC128 = 718 + + STORE_ACC64 = 719 + + STORE_ACC64DSP = 720 + + STORE_CCOND_DSP = 721 + + STR_D = 722 + + STR_W = 723 + + ST_F16 = 724 + + SWM_MM = 725 + + SZ_B_PSEUDO = 726 + + SZ_D_PSEUDO = 727 + + SZ_H_PSEUDO = 728 + + SZ_V_PSEUDO = 729 + + SZ_W_PSEUDO = 730 + + SaaAddr = 731 + + SaadAddr = 732 + + SelBeqZ = 733 + + SelBneZ = 734 + + SelTBteqZCmp = 735 + + SelTBteqZCmpi = 736 + + SelTBteqZSlt = 737 + + SelTBteqZSlti = 738 + + SelTBteqZSltiu = 739 + + SelTBteqZSltu = 740 + + SelTBtneZCmp = 741 + + SelTBtneZCmpi = 742 + + SelTBtneZSlt = 743 + + SelTBtneZSlti = 744 + + SelTBtneZSltiu = 745 + + SelTBtneZSltu = 746 + + SltCCRxRy16 = 747 + + SltiCCRxImmX16 = 748 + + SltiuCCRxImmX16 = 749 + + SltuCCRxRy16 = 750 + + SltuRxRyRz16 = 751 + + TAILCALL = 752 + + TAILCALL64R6REG = 753 + + TAILCALLHB64R6REG = 754 + + TAILCALLHBR6REG = 755 + + TAILCALLR6REG = 756 + + TAILCALLREG = 757 + + TAILCALLREG64 = 758 + + TAILCALLREGHB = 759 + + TAILCALLREGHB64 = 760 + + TAILCALLREG_MM = 761 + + TAILCALLREG_MMR6 = 762 + + TAILCALL_MM = 763 + + TAILCALL_MMR6 = 764 + + TRAP = 765 + + TRAP_MM = 766 + + UDIV_MM_Pseudo = 767 + + UDivIMacro = 768 + + UDivMacro = 769 + + URemIMacro = 770 + + URemMacro = 771 + + Ulh = 772 + + Ulhu = 773 + + Ulw = 774 + + Ush = 775 + + Usw = 776 + + XOR_V_D_PSEUDO = 777 + + XOR_V_H_PSEUDO = 778 + + XOR_V_W_PSEUDO = 779 + + ABSQ_S_PH = 780 + + ABSQ_S_PH_MM = 781 + + ABSQ_S_QB = 782 + + ABSQ_S_QB_MMR2 = 783 + + ABSQ_S_W = 784 + + ABSQ_S_W_MM = 785 + + ADD = 786 + + ADDIUPC = 787 + + ADDIUPC_MM = 788 + + ADDIUPC_MMR6 = 789 + + ADDIUR1SP_MM = 790 + + ADDIUR2_MM = 791 + + ADDIUS5_MM = 792 + + ADDIUSP_MM = 793 + + ADDIU_MMR6 = 794 + + ADDQH_PH = 795 + + ADDQH_PH_MMR2 = 796 + + ADDQH_R_PH = 797 + + ADDQH_R_PH_MMR2 = 798 + + ADDQH_R_W = 799 + + ADDQH_R_W_MMR2 = 800 + + ADDQH_W = 801 + + ADDQH_W_MMR2 = 802 + + ADDQ_PH = 803 + + ADDQ_PH_MM = 804 + + ADDQ_S_PH = 805 + + ADDQ_S_PH_MM = 806 + + ADDQ_S_W = 807 + + ADDQ_S_W_MM = 808 + + ADDR_PS64 = 809 + + ADDSC = 810 + + ADDSC_MM = 811 + + ADDS_A_B = 812 + + ADDS_A_D = 813 + + ADDS_A_H = 814 + + ADDS_A_W = 815 + + ADDS_S_B = 816 + + ADDS_S_D = 817 + + ADDS_S_H = 818 + + ADDS_S_W = 819 + + ADDS_U_B = 820 + + ADDS_U_D = 821 + + ADDS_U_H = 822 + + ADDS_U_W = 823 + + ADDU16_MM = 824 + + ADDU16_MMR6 = 825 + + ADDUH_QB = 826 + + ADDUH_QB_MMR2 = 827 + + ADDUH_R_QB = 828 + + ADDUH_R_QB_MMR2 = 829 + + ADDU_MMR6 = 830 + + ADDU_PH = 831 + + ADDU_PH_MMR2 = 832 + + ADDU_QB = 833 + + ADDU_QB_MM = 834 + + ADDU_S_PH = 835 + + ADDU_S_PH_MMR2 = 836 + + ADDU_S_QB = 837 + + ADDU_S_QB_MM = 838 + + ADDVI_B = 839 + + ADDVI_D = 840 + + ADDVI_H = 841 + + ADDVI_W = 842 + + ADDV_B = 843 + + ADDV_D = 844 + + ADDV_H = 845 + + ADDV_W = 846 + + ADDWC = 847 + + ADDWC_MM = 848 + + ADD_A_B = 849 + + ADD_A_D = 850 + + ADD_A_H = 851 + + ADD_A_W = 852 + + ADD_MM = 853 + + ADD_MMR6 = 854 + + ADDi = 855 + + ADDi_MM = 856 + + ADDiu = 857 + + ADDiu_MM = 858 + + ADDu = 859 + + ADDu_MM = 860 + + ALIGN = 861 + + ALIGN_MMR6 = 862 + + ALUIPC = 863 + + ALUIPC_MMR6 = 864 + + AND = 865 + + AND16_MM = 866 + + AND16_MMR6 = 867 + + AND64 = 868 + + ANDI16_MM = 869 + + ANDI16_MMR6 = 870 + + ANDI_B = 871 + + ANDI_MMR6 = 872 + + AND_MM = 873 + + AND_MMR6 = 874 + + AND_V = 875 + + ANDi = 876 + + ANDi64 = 877 + + ANDi_MM = 878 + + APPEND = 879 + + APPEND_MMR2 = 880 + + ASUB_S_B = 881 + + ASUB_S_D = 882 + + ASUB_S_H = 883 + + ASUB_S_W = 884 + + ASUB_U_B = 885 + + ASUB_U_D = 886 + + ASUB_U_H = 887 + + ASUB_U_W = 888 + + AUI = 889 + + AUIPC = 890 + + AUIPC_MMR6 = 891 + + AUI_MMR6 = 892 + + AVER_S_B = 893 + + AVER_S_D = 894 + + AVER_S_H = 895 + + AVER_S_W = 896 + + AVER_U_B = 897 + + AVER_U_D = 898 + + AVER_U_H = 899 + + AVER_U_W = 900 + + AVE_S_B = 901 + + AVE_S_D = 902 + + AVE_S_H = 903 + + AVE_S_W = 904 + + AVE_U_B = 905 + + AVE_U_D = 906 + + AVE_U_H = 907 + + AVE_U_W = 908 + + AddiuRxImmX16 = 909 + + AddiuRxPcImmX16 = 910 + + AddiuRxRxImm16 = 911 + + AddiuRxRxImmX16 = 912 + + AddiuRxRyOffMemX16 = 913 + + AddiuSpImm16 = 914 + + AddiuSpImmX16 = 915 + + AdduRxRyRz16 = 916 + + AndRxRxRy16 = 917 + + B16_MM = 918 + + BADDu = 919 + + BAL = 920 + + BALC = 921 + + BALC_MMR6 = 922 + + BALIGN = 923 + + BALIGN_MMR2 = 924 + + BBIT0 = 925 + + BBIT032 = 926 + + BBIT1 = 927 + + BBIT132 = 928 + + BC = 929 + + BC16_MMR6 = 930 + + BC1EQZ = 931 + + BC1EQZC_MMR6 = 932 + + BC1F = 933 + + BC1FL = 934 + + BC1F_MM = 935 + + BC1NEZ = 936 + + BC1NEZC_MMR6 = 937 + + BC1T = 938 + + BC1TL = 939 + + BC1T_MM = 940 + + BC2EQZ = 941 + + BC2EQZC_MMR6 = 942 + + BC2NEZ = 943 + + BC2NEZC_MMR6 = 944 + + BCLRI_B = 945 + + BCLRI_D = 946 + + BCLRI_H = 947 + + BCLRI_W = 948 + + BCLR_B = 949 + + BCLR_D = 950 + + BCLR_H = 951 + + BCLR_W = 952 + + BC_MMR6 = 953 + + BEQ = 954 + + BEQ64 = 955 + + BEQC = 956 + + BEQC64 = 957 + + BEQC_MMR6 = 958 + + BEQL = 959 + + BEQZ16_MM = 960 + + BEQZALC = 961 + + BEQZALC_MMR6 = 962 + + BEQZC = 963 + + BEQZC16_MMR6 = 964 + + BEQZC64 = 965 + + BEQZC_MM = 966 + + BEQZC_MMR6 = 967 + + BEQ_MM = 968 + + BGEC = 969 + + BGEC64 = 970 + + BGEC_MMR6 = 971 + + BGEUC = 972 + + BGEUC64 = 973 + + BGEUC_MMR6 = 974 + + BGEZ = 975 + + BGEZ64 = 976 + + BGEZAL = 977 + + BGEZALC = 978 + + BGEZALC_MMR6 = 979 + + BGEZALL = 980 + + BGEZALS_MM = 981 + + BGEZAL_MM = 982 + + BGEZC = 983 + + BGEZC64 = 984 + + BGEZC_MMR6 = 985 + + BGEZL = 986 + + BGEZ_MM = 987 + + BGTZ = 988 + + BGTZ64 = 989 + + BGTZALC = 990 + + BGTZALC_MMR6 = 991 + + BGTZC = 992 + + BGTZC64 = 993 + + BGTZC_MMR6 = 994 + + BGTZL = 995 + + BGTZ_MM = 996 + + BINSLI_B = 997 + + BINSLI_D = 998 + + BINSLI_H = 999 + + BINSLI_W = 1000 + + BINSL_B = 1001 + + BINSL_D = 1002 + + BINSL_H = 1003 + + BINSL_W = 1004 + + BINSRI_B = 1005 + + BINSRI_D = 1006 + + BINSRI_H = 1007 + + BINSRI_W = 1008 + + BINSR_B = 1009 + + BINSR_D = 1010 + + BINSR_H = 1011 + + BINSR_W = 1012 + + BITREV = 1013 + + BITREV_MM = 1014 + + BITSWAP = 1015 + + BITSWAP_MMR6 = 1016 + + BLEZ = 1017 + + BLEZ64 = 1018 + + BLEZALC = 1019 + + BLEZALC_MMR6 = 1020 + + BLEZC = 1021 + + BLEZC64 = 1022 + + BLEZC_MMR6 = 1023 + + BLEZL = 1024 + + BLEZ_MM = 1025 + + BLTC = 1026 + + BLTC64 = 1027 + + BLTC_MMR6 = 1028 + + BLTUC = 1029 + + BLTUC64 = 1030 + + BLTUC_MMR6 = 1031 + + BLTZ = 1032 + + BLTZ64 = 1033 + + BLTZAL = 1034 + + BLTZALC = 1035 + + BLTZALC_MMR6 = 1036 + + BLTZALL = 1037 + + BLTZALS_MM = 1038 + + BLTZAL_MM = 1039 + + BLTZC = 1040 + + BLTZC64 = 1041 + + BLTZC_MMR6 = 1042 + + BLTZL = 1043 + + BLTZ_MM = 1044 + + BMNZI_B = 1045 + + BMNZ_V = 1046 + + BMZI_B = 1047 + + BMZ_V = 1048 + + BNE = 1049 + + BNE64 = 1050 + + BNEC = 1051 + + BNEC64 = 1052 + + BNEC_MMR6 = 1053 + + BNEGI_B = 1054 + + BNEGI_D = 1055 + + BNEGI_H = 1056 + + BNEGI_W = 1057 + + BNEG_B = 1058 + + BNEG_D = 1059 + + BNEG_H = 1060 + + BNEG_W = 1061 + + BNEL = 1062 + + BNEZ16_MM = 1063 + + BNEZALC = 1064 + + BNEZALC_MMR6 = 1065 + + BNEZC = 1066 + + BNEZC16_MMR6 = 1067 + + BNEZC64 = 1068 + + BNEZC_MM = 1069 + + BNEZC_MMR6 = 1070 + + BNE_MM = 1071 + + BNVC = 1072 + + BNVC_MMR6 = 1073 + + BNZ_B = 1074 + + BNZ_D = 1075 + + BNZ_H = 1076 + + BNZ_V = 1077 + + BNZ_W = 1078 + + BOVC = 1079 + + BOVC_MMR6 = 1080 + + BPOSGE32 = 1081 + + BPOSGE32C_MMR3 = 1082 + + BPOSGE32_MM = 1083 + + BREAK = 1084 + + BREAK16_MM = 1085 + + BREAK16_MMR6 = 1086 + + BREAK_MM = 1087 + + BREAK_MMR6 = 1088 + + BSELI_B = 1089 + + BSEL_V = 1090 + + BSETI_B = 1091 + + BSETI_D = 1092 + + BSETI_H = 1093 + + BSETI_W = 1094 + + BSET_B = 1095 + + BSET_D = 1096 + + BSET_H = 1097 + + BSET_W = 1098 + + BZ_B = 1099 + + BZ_D = 1100 + + BZ_H = 1101 + + BZ_V = 1102 + + BZ_W = 1103 + + BeqzRxImm16 = 1104 + + BeqzRxImmX16 = 1105 + + Bimm16 = 1106 + + BimmX16 = 1107 + + BnezRxImm16 = 1108 + + BnezRxImmX16 = 1109 + + Break16 = 1110 + + Bteqz16 = 1111 + + BteqzX16 = 1112 + + Btnez16 = 1113 + + BtnezX16 = 1114 + + CACHE = 1115 + + CACHEE = 1116 + + CACHEE_MM = 1117 + + CACHE_MM = 1118 + + CACHE_MMR6 = 1119 + + CACHE_R6 = 1120 + + CEIL_L_D64 = 1121 + + CEIL_L_D_MMR6 = 1122 + + CEIL_L_S = 1123 + + CEIL_L_S_MMR6 = 1124 + + CEIL_W_D32 = 1125 + + CEIL_W_D64 = 1126 + + CEIL_W_D_MMR6 = 1127 + + CEIL_W_MM = 1128 + + CEIL_W_S = 1129 + + CEIL_W_S_MM = 1130 + + CEIL_W_S_MMR6 = 1131 + + CEQI_B = 1132 + + CEQI_D = 1133 + + CEQI_H = 1134 + + CEQI_W = 1135 + + CEQ_B = 1136 + + CEQ_D = 1137 + + CEQ_H = 1138 + + CEQ_W = 1139 + + CFC1 = 1140 + + CFC1_MM = 1141 + + CFC2_MM = 1142 + + CFCMSA = 1143 + + CINS = 1144 + + CINS32 = 1145 + + CINS64_32 = 1146 + + CINS_i32 = 1147 + + CLASS_D = 1148 + + CLASS_D_MMR6 = 1149 + + CLASS_S = 1150 + + CLASS_S_MMR6 = 1151 + + CLEI_S_B = 1152 + + CLEI_S_D = 1153 + + CLEI_S_H = 1154 + + CLEI_S_W = 1155 + + CLEI_U_B = 1156 + + CLEI_U_D = 1157 + + CLEI_U_H = 1158 + + CLEI_U_W = 1159 + + CLE_S_B = 1160 + + CLE_S_D = 1161 + + CLE_S_H = 1162 + + CLE_S_W = 1163 + + CLE_U_B = 1164 + + CLE_U_D = 1165 + + CLE_U_H = 1166 + + CLE_U_W = 1167 + + CLO = 1168 + + CLO_MM = 1169 + + CLO_MMR6 = 1170 + + CLO_R6 = 1171 + + CLTI_S_B = 1172 + + CLTI_S_D = 1173 + + CLTI_S_H = 1174 + + CLTI_S_W = 1175 + + CLTI_U_B = 1176 + + CLTI_U_D = 1177 + + CLTI_U_H = 1178 + + CLTI_U_W = 1179 + + CLT_S_B = 1180 + + CLT_S_D = 1181 + + CLT_S_H = 1182 + + CLT_S_W = 1183 + + CLT_U_B = 1184 + + CLT_U_D = 1185 + + CLT_U_H = 1186 + + CLT_U_W = 1187 + + CLZ = 1188 + + CLZ_MM = 1189 + + CLZ_MMR6 = 1190 + + CLZ_R6 = 1191 + + CMPGDU_EQ_QB = 1192 + + CMPGDU_EQ_QB_MMR2 = 1193 + + CMPGDU_LE_QB = 1194 + + CMPGDU_LE_QB_MMR2 = 1195 + + CMPGDU_LT_QB = 1196 + + CMPGDU_LT_QB_MMR2 = 1197 + + CMPGU_EQ_QB = 1198 + + CMPGU_EQ_QB_MM = 1199 + + CMPGU_LE_QB = 1200 + + CMPGU_LE_QB_MM = 1201 + + CMPGU_LT_QB = 1202 + + CMPGU_LT_QB_MM = 1203 + + CMPU_EQ_QB = 1204 + + CMPU_EQ_QB_MM = 1205 + + CMPU_LE_QB = 1206 + + CMPU_LE_QB_MM = 1207 + + CMPU_LT_QB = 1208 + + CMPU_LT_QB_MM = 1209 + + CMP_AF_D_MMR6 = 1210 + + CMP_AF_S_MMR6 = 1211 + + CMP_EQ_D = 1212 + + CMP_EQ_D_MMR6 = 1213 + + CMP_EQ_PH = 1214 + + CMP_EQ_PH_MM = 1215 + + CMP_EQ_S = 1216 + + CMP_EQ_S_MMR6 = 1217 + + CMP_F_D = 1218 + + CMP_F_S = 1219 + + CMP_LE_D = 1220 + + CMP_LE_D_MMR6 = 1221 + + CMP_LE_PH = 1222 + + CMP_LE_PH_MM = 1223 + + CMP_LE_S = 1224 + + CMP_LE_S_MMR6 = 1225 + + CMP_LT_D = 1226 + + CMP_LT_D_MMR6 = 1227 + + CMP_LT_PH = 1228 + + CMP_LT_PH_MM = 1229 + + CMP_LT_S = 1230 + + CMP_LT_S_MMR6 = 1231 + + CMP_SAF_D = 1232 + + CMP_SAF_D_MMR6 = 1233 + + CMP_SAF_S = 1234 + + CMP_SAF_S_MMR6 = 1235 + + CMP_SEQ_D = 1236 + + CMP_SEQ_D_MMR6 = 1237 + + CMP_SEQ_S = 1238 + + CMP_SEQ_S_MMR6 = 1239 + + CMP_SLE_D = 1240 + + CMP_SLE_D_MMR6 = 1241 + + CMP_SLE_S = 1242 + + CMP_SLE_S_MMR6 = 1243 + + CMP_SLT_D = 1244 + + CMP_SLT_D_MMR6 = 1245 + + CMP_SLT_S = 1246 + + CMP_SLT_S_MMR6 = 1247 + + CMP_SUEQ_D = 1248 + + CMP_SUEQ_D_MMR6 = 1249 + + CMP_SUEQ_S = 1250 + + CMP_SUEQ_S_MMR6 = 1251 + + CMP_SULE_D = 1252 + + CMP_SULE_D_MMR6 = 1253 + + CMP_SULE_S = 1254 + + CMP_SULE_S_MMR6 = 1255 + + CMP_SULT_D = 1256 + + CMP_SULT_D_MMR6 = 1257 + + CMP_SULT_S = 1258 + + CMP_SULT_S_MMR6 = 1259 + + CMP_SUN_D = 1260 + + CMP_SUN_D_MMR6 = 1261 + + CMP_SUN_S = 1262 + + CMP_SUN_S_MMR6 = 1263 + + CMP_UEQ_D = 1264 + + CMP_UEQ_D_MMR6 = 1265 + + CMP_UEQ_S = 1266 + + CMP_UEQ_S_MMR6 = 1267 + + CMP_ULE_D = 1268 + + CMP_ULE_D_MMR6 = 1269 + + CMP_ULE_S = 1270 + + CMP_ULE_S_MMR6 = 1271 + + CMP_ULT_D = 1272 + + CMP_ULT_D_MMR6 = 1273 + + CMP_ULT_S = 1274 + + CMP_ULT_S_MMR6 = 1275 + + CMP_UN_D = 1276 + + CMP_UN_D_MMR6 = 1277 + + CMP_UN_S = 1278 + + CMP_UN_S_MMR6 = 1279 + + COPY_S_B = 1280 + + COPY_S_D = 1281 + + COPY_S_H = 1282 + + COPY_S_W = 1283 + + COPY_U_B = 1284 + + COPY_U_H = 1285 + + COPY_U_W = 1286 + + CRC32B = 1287 + + CRC32CB = 1288 + + CRC32CD = 1289 + + CRC32CH = 1290 + + CRC32CW = 1291 + + CRC32D = 1292 + + CRC32H = 1293 + + CRC32W = 1294 + + CTC1 = 1295 + + CTC1_MM = 1296 + + CTC2_MM = 1297 + + CTCMSA = 1298 + + CVT_D32_S = 1299 + + CVT_D32_S_MM = 1300 + + CVT_D32_W = 1301 + + CVT_D32_W_MM = 1302 + + CVT_D64_L = 1303 + + CVT_D64_S = 1304 + + CVT_D64_S_MM = 1305 + + CVT_D64_W = 1306 + + CVT_D64_W_MM = 1307 + + CVT_D_L_MMR6 = 1308 + + CVT_L_D64 = 1309 + + CVT_L_D64_MM = 1310 + + CVT_L_D_MMR6 = 1311 + + CVT_L_S = 1312 + + CVT_L_S_MM = 1313 + + CVT_L_S_MMR6 = 1314 + + CVT_PS_PW64 = 1315 + + CVT_PS_S64 = 1316 + + CVT_PW_PS64 = 1317 + + CVT_S_D32 = 1318 + + CVT_S_D32_MM = 1319 + + CVT_S_D64 = 1320 + + CVT_S_D64_MM = 1321 + + CVT_S_L = 1322 + + CVT_S_L_MMR6 = 1323 + + CVT_S_PL64 = 1324 + + CVT_S_PU64 = 1325 + + CVT_S_W = 1326 + + CVT_S_W_MM = 1327 + + CVT_S_W_MMR6 = 1328 + + CVT_W_D32 = 1329 + + CVT_W_D32_MM = 1330 + + CVT_W_D64 = 1331 + + CVT_W_D64_MM = 1332 + + CVT_W_S = 1333 + + CVT_W_S_MM = 1334 + + CVT_W_S_MMR6 = 1335 + + C_EQ_D32 = 1336 + + C_EQ_D32_MM = 1337 + + C_EQ_D64 = 1338 + + C_EQ_D64_MM = 1339 + + C_EQ_S = 1340 + + C_EQ_S_MM = 1341 + + C_F_D32 = 1342 + + C_F_D32_MM = 1343 + + C_F_D64 = 1344 + + C_F_D64_MM = 1345 + + C_F_S = 1346 + + C_F_S_MM = 1347 + + C_LE_D32 = 1348 + + C_LE_D32_MM = 1349 + + C_LE_D64 = 1350 + + C_LE_D64_MM = 1351 + + C_LE_S = 1352 + + C_LE_S_MM = 1353 + + C_LT_D32 = 1354 + + C_LT_D32_MM = 1355 + + C_LT_D64 = 1356 + + C_LT_D64_MM = 1357 + + C_LT_S = 1358 + + C_LT_S_MM = 1359 + + C_NGE_D32 = 1360 + + C_NGE_D32_MM = 1361 + + C_NGE_D64 = 1362 + + C_NGE_D64_MM = 1363 + + C_NGE_S = 1364 + + C_NGE_S_MM = 1365 + + C_NGLE_D32 = 1366 + + C_NGLE_D32_MM = 1367 + + C_NGLE_D64 = 1368 + + C_NGLE_D64_MM = 1369 + + C_NGLE_S = 1370 + + C_NGLE_S_MM = 1371 + + C_NGL_D32 = 1372 + + C_NGL_D32_MM = 1373 + + C_NGL_D64 = 1374 + + C_NGL_D64_MM = 1375 + + C_NGL_S = 1376 + + C_NGL_S_MM = 1377 + + C_NGT_D32 = 1378 + + C_NGT_D32_MM = 1379 + + C_NGT_D64 = 1380 + + C_NGT_D64_MM = 1381 + + C_NGT_S = 1382 + + C_NGT_S_MM = 1383 + + C_OLE_D32 = 1384 + + C_OLE_D32_MM = 1385 + + C_OLE_D64 = 1386 + + C_OLE_D64_MM = 1387 + + C_OLE_S = 1388 + + C_OLE_S_MM = 1389 + + C_OLT_D32 = 1390 + + C_OLT_D32_MM = 1391 + + C_OLT_D64 = 1392 + + C_OLT_D64_MM = 1393 + + C_OLT_S = 1394 + + C_OLT_S_MM = 1395 + + C_SEQ_D32 = 1396 + + C_SEQ_D32_MM = 1397 + + C_SEQ_D64 = 1398 + + C_SEQ_D64_MM = 1399 + + C_SEQ_S = 1400 + + C_SEQ_S_MM = 1401 + + C_SF_D32 = 1402 + + C_SF_D32_MM = 1403 + + C_SF_D64 = 1404 + + C_SF_D64_MM = 1405 + + C_SF_S = 1406 + + C_SF_S_MM = 1407 + + C_UEQ_D32 = 1408 + + C_UEQ_D32_MM = 1409 + + C_UEQ_D64 = 1410 + + C_UEQ_D64_MM = 1411 + + C_UEQ_S = 1412 + + C_UEQ_S_MM = 1413 + + C_ULE_D32 = 1414 + + C_ULE_D32_MM = 1415 + + C_ULE_D64 = 1416 + + C_ULE_D64_MM = 1417 + + C_ULE_S = 1418 + + C_ULE_S_MM = 1419 + + C_ULT_D32 = 1420 + + C_ULT_D32_MM = 1421 + + C_ULT_D64 = 1422 + + C_ULT_D64_MM = 1423 + + C_ULT_S = 1424 + + C_ULT_S_MM = 1425 + + C_UN_D32 = 1426 + + C_UN_D32_MM = 1427 + + C_UN_D64 = 1428 + + C_UN_D64_MM = 1429 + + C_UN_S = 1430 + + C_UN_S_MM = 1431 + + CmpRxRy16 = 1432 + + CmpiRxImm16 = 1433 + + CmpiRxImmX16 = 1434 + + DADD = 1435 + + DADDi = 1436 + + DADDiu = 1437 + + DADDu = 1438 + + DAHI = 1439 + + DALIGN = 1440 + + DATI = 1441 + + DAUI = 1442 + + DBITSWAP = 1443 + + DCLO = 1444 + + DCLO_R6 = 1445 + + DCLZ = 1446 + + DCLZ_R6 = 1447 + + DDIV = 1448 + + DDIVU = 1449 + + DERET = 1450 + + DERET_MM = 1451 + + DERET_MMR6 = 1452 + + DEXT = 1453 + + DEXT64_32 = 1454 + + DEXTM = 1455 + + DEXTU = 1456 + + DI = 1457 + + DINS = 1458 + + DINSM = 1459 + + DINSU = 1460 + + DIV = 1461 + + DIVU = 1462 + + DIVU_MMR6 = 1463 + + DIV_MMR6 = 1464 + + DIV_S_B = 1465 + + DIV_S_D = 1466 + + DIV_S_H = 1467 + + DIV_S_W = 1468 + + DIV_U_B = 1469 + + DIV_U_D = 1470 + + DIV_U_H = 1471 + + DIV_U_W = 1472 + + DI_MM = 1473 + + DI_MMR6 = 1474 + + DLSA = 1475 + + DLSA_R6 = 1476 + + DMFC0 = 1477 + + DMFC1 = 1478 + + DMFC2 = 1479 + + DMFC2_OCTEON = 1480 + + DMFGC0 = 1481 + + DMOD = 1482 + + DMODU = 1483 + + DMT = 1484 + + DMTC0 = 1485 + + DMTC1 = 1486 + + DMTC2 = 1487 + + DMTC2_OCTEON = 1488 + + DMTGC0 = 1489 + + DMUH = 1490 + + DMUHU = 1491 + + DMUL = 1492 + + DMULT = 1493 + + DMULTu = 1494 + + DMULU = 1495 + + DMUL_R6 = 1496 + + DOTP_S_D = 1497 + + DOTP_S_H = 1498 + + DOTP_S_W = 1499 + + DOTP_U_D = 1500 + + DOTP_U_H = 1501 + + DOTP_U_W = 1502 + + DPADD_S_D = 1503 + + DPADD_S_H = 1504 + + DPADD_S_W = 1505 + + DPADD_U_D = 1506 + + DPADD_U_H = 1507 + + DPADD_U_W = 1508 + + DPAQX_SA_W_PH = 1509 + + DPAQX_SA_W_PH_MMR2 = 1510 + + DPAQX_S_W_PH = 1511 + + DPAQX_S_W_PH_MMR2 = 1512 + + DPAQ_SA_L_W = 1513 + + DPAQ_SA_L_W_MM = 1514 + + DPAQ_S_W_PH = 1515 + + DPAQ_S_W_PH_MM = 1516 + + DPAU_H_QBL = 1517 + + DPAU_H_QBL_MM = 1518 + + DPAU_H_QBR = 1519 + + DPAU_H_QBR_MM = 1520 + + DPAX_W_PH = 1521 + + DPAX_W_PH_MMR2 = 1522 + + DPA_W_PH = 1523 + + DPA_W_PH_MMR2 = 1524 + + DPOP = 1525 + + DPSQX_SA_W_PH = 1526 + + DPSQX_SA_W_PH_MMR2 = 1527 + + DPSQX_S_W_PH = 1528 + + DPSQX_S_W_PH_MMR2 = 1529 + + DPSQ_SA_L_W = 1530 + + DPSQ_SA_L_W_MM = 1531 + + DPSQ_S_W_PH = 1532 + + DPSQ_S_W_PH_MM = 1533 + + DPSUB_S_D = 1534 + + DPSUB_S_H = 1535 + + DPSUB_S_W = 1536 + + DPSUB_U_D = 1537 + + DPSUB_U_H = 1538 + + DPSUB_U_W = 1539 + + DPSU_H_QBL = 1540 + + DPSU_H_QBL_MM = 1541 + + DPSU_H_QBR = 1542 + + DPSU_H_QBR_MM = 1543 + + DPSX_W_PH = 1544 + + DPSX_W_PH_MMR2 = 1545 + + DPS_W_PH = 1546 + + DPS_W_PH_MMR2 = 1547 + + DROTR = 1548 + + DROTR32 = 1549 + + DROTRV = 1550 + + DSBH = 1551 + + DSDIV = 1552 + + DSHD = 1553 + + DSLL = 1554 + + DSLL32 = 1555 + + DSLL64_32 = 1556 + + DSLLV = 1557 + + DSRA = 1558 + + DSRA32 = 1559 + + DSRAV = 1560 + + DSRL = 1561 + + DSRL32 = 1562 + + DSRLV = 1563 + + DSUB = 1564 + + DSUBu = 1565 + + DUDIV = 1566 + + DVP = 1567 + + DVPE = 1568 + + DVP_MMR6 = 1569 + + DivRxRy16 = 1570 + + DivuRxRy16 = 1571 + + EHB = 1572 + + EHB_MM = 1573 + + EHB_MMR6 = 1574 + + EI = 1575 + + EI_MM = 1576 + + EI_MMR6 = 1577 + + EMT = 1578 + + ERET = 1579 + + ERETNC = 1580 + + ERETNC_MMR6 = 1581 + + ERET_MM = 1582 + + ERET_MMR6 = 1583 + + EVP = 1584 + + EVPE = 1585 + + EVP_MMR6 = 1586 + + EXT = 1587 + + EXTP = 1588 + + EXTPDP = 1589 + + EXTPDPV = 1590 + + EXTPDPV_MM = 1591 + + EXTPDP_MM = 1592 + + EXTPV = 1593 + + EXTPV_MM = 1594 + + EXTP_MM = 1595 + + EXTRV_RS_W = 1596 + + EXTRV_RS_W_MM = 1597 + + EXTRV_R_W = 1598 + + EXTRV_R_W_MM = 1599 + + EXTRV_S_H = 1600 + + EXTRV_S_H_MM = 1601 + + EXTRV_W = 1602 + + EXTRV_W_MM = 1603 + + EXTR_RS_W = 1604 + + EXTR_RS_W_MM = 1605 + + EXTR_R_W = 1606 + + EXTR_R_W_MM = 1607 + + EXTR_S_H = 1608 + + EXTR_S_H_MM = 1609 + + EXTR_W = 1610 + + EXTR_W_MM = 1611 + + EXTS = 1612 + + EXTS32 = 1613 + + EXT_MM = 1614 + + EXT_MMR6 = 1615 + + FABS_D32 = 1616 + + FABS_D32_MM = 1617 + + FABS_D64 = 1618 + + FABS_D64_MM = 1619 + + FABS_S = 1620 + + FABS_S_MM = 1621 + + FADD_D = 1622 + + FADD_D32 = 1623 + + FADD_D32_MM = 1624 + + FADD_D64 = 1625 + + FADD_D64_MM = 1626 + + FADD_PS64 = 1627 + + FADD_S = 1628 + + FADD_S_MM = 1629 + + FADD_S_MMR6 = 1630 + + FADD_W = 1631 + + FCAF_D = 1632 + + FCAF_W = 1633 + + FCEQ_D = 1634 + + FCEQ_W = 1635 + + FCLASS_D = 1636 + + FCLASS_W = 1637 + + FCLE_D = 1638 + + FCLE_W = 1639 + + FCLT_D = 1640 + + FCLT_W = 1641 + + FCMP_D32 = 1642 + + FCMP_D32_MM = 1643 + + FCMP_D64 = 1644 + + FCMP_S32 = 1645 + + FCMP_S32_MM = 1646 + + FCNE_D = 1647 + + FCNE_W = 1648 + + FCOR_D = 1649 + + FCOR_W = 1650 + + FCUEQ_D = 1651 + + FCUEQ_W = 1652 + + FCULE_D = 1653 + + FCULE_W = 1654 + + FCULT_D = 1655 + + FCULT_W = 1656 + + FCUNE_D = 1657 + + FCUNE_W = 1658 + + FCUN_D = 1659 + + FCUN_W = 1660 + + FDIV_D = 1661 + + FDIV_D32 = 1662 + + FDIV_D32_MM = 1663 + + FDIV_D64 = 1664 + + FDIV_D64_MM = 1665 + + FDIV_S = 1666 + + FDIV_S_MM = 1667 + + FDIV_S_MMR6 = 1668 + + FDIV_W = 1669 + + FEXDO_H = 1670 + + FEXDO_W = 1671 + + FEXP2_D = 1672 + + FEXP2_W = 1673 + + FEXUPL_D = 1674 + + FEXUPL_W = 1675 + + FEXUPR_D = 1676 + + FEXUPR_W = 1677 + + FFINT_S_D = 1678 + + FFINT_S_W = 1679 + + FFINT_U_D = 1680 + + FFINT_U_W = 1681 + + FFQL_D = 1682 + + FFQL_W = 1683 + + FFQR_D = 1684 + + FFQR_W = 1685 + + FILL_B = 1686 + + FILL_D = 1687 + + FILL_H = 1688 + + FILL_W = 1689 + + FLOG2_D = 1690 + + FLOG2_W = 1691 + + FLOOR_L_D64 = 1692 + + FLOOR_L_D_MMR6 = 1693 + + FLOOR_L_S = 1694 + + FLOOR_L_S_MMR6 = 1695 + + FLOOR_W_D32 = 1696 + + FLOOR_W_D64 = 1697 + + FLOOR_W_D_MMR6 = 1698 + + FLOOR_W_MM = 1699 + + FLOOR_W_S = 1700 + + FLOOR_W_S_MM = 1701 + + FLOOR_W_S_MMR6 = 1702 + + FMADD_D = 1703 + + FMADD_W = 1704 + + FMAX_A_D = 1705 + + FMAX_A_W = 1706 + + FMAX_D = 1707 + + FMAX_W = 1708 + + FMIN_A_D = 1709 + + FMIN_A_W = 1710 + + FMIN_D = 1711 + + FMIN_W = 1712 + + FMOV_D32 = 1713 + + FMOV_D32_MM = 1714 + + FMOV_D64 = 1715 + + FMOV_D64_MM = 1716 + + FMOV_D_MMR6 = 1717 + + FMOV_S = 1718 + + FMOV_S_MM = 1719 + + FMOV_S_MMR6 = 1720 + + FMSUB_D = 1721 + + FMSUB_W = 1722 + + FMUL_D = 1723 + + FMUL_D32 = 1724 + + FMUL_D32_MM = 1725 + + FMUL_D64 = 1726 + + FMUL_D64_MM = 1727 + + FMUL_PS64 = 1728 + + FMUL_S = 1729 + + FMUL_S_MM = 1730 + + FMUL_S_MMR6 = 1731 + + FMUL_W = 1732 + + FNEG_D32 = 1733 + + FNEG_D32_MM = 1734 + + FNEG_D64 = 1735 + + FNEG_D64_MM = 1736 + + FNEG_S = 1737 + + FNEG_S_MM = 1738 + + FNEG_S_MMR6 = 1739 + + FORK = 1740 + + FRCP_D = 1741 + + FRCP_W = 1742 + + FRINT_D = 1743 + + FRINT_W = 1744 + + FRSQRT_D = 1745 + + FRSQRT_W = 1746 + + FSAF_D = 1747 + + FSAF_W = 1748 + + FSEQ_D = 1749 + + FSEQ_W = 1750 + + FSLE_D = 1751 + + FSLE_W = 1752 + + FSLT_D = 1753 + + FSLT_W = 1754 + + FSNE_D = 1755 + + FSNE_W = 1756 + + FSOR_D = 1757 + + FSOR_W = 1758 + + FSQRT_D = 1759 + + FSQRT_D32 = 1760 + + FSQRT_D32_MM = 1761 + + FSQRT_D64 = 1762 + + FSQRT_D64_MM = 1763 + + FSQRT_S = 1764 + + FSQRT_S_MM = 1765 + + FSQRT_W = 1766 + + FSUB_D = 1767 + + FSUB_D32 = 1768 + + FSUB_D32_MM = 1769 + + FSUB_D64 = 1770 + + FSUB_D64_MM = 1771 + + FSUB_PS64 = 1772 + + FSUB_S = 1773 + + FSUB_S_MM = 1774 + + FSUB_S_MMR6 = 1775 + + FSUB_W = 1776 + + FSUEQ_D = 1777 + + FSUEQ_W = 1778 + + FSULE_D = 1779 + + FSULE_W = 1780 + + FSULT_D = 1781 + + FSULT_W = 1782 + + FSUNE_D = 1783 + + FSUNE_W = 1784 + + FSUN_D = 1785 + + FSUN_W = 1786 + + FTINT_S_D = 1787 + + FTINT_S_W = 1788 + + FTINT_U_D = 1789 + + FTINT_U_W = 1790 + + FTQ_H = 1791 + + FTQ_W = 1792 + + FTRUNC_S_D = 1793 + + FTRUNC_S_W = 1794 + + FTRUNC_U_D = 1795 + + FTRUNC_U_W = 1796 + + GINVI = 1797 + + GINVI_MMR6 = 1798 + + GINVT = 1799 + + GINVT_MMR6 = 1800 + + HADD_S_D = 1801 + + HADD_S_H = 1802 + + HADD_S_W = 1803 + + HADD_U_D = 1804 + + HADD_U_H = 1805 + + HADD_U_W = 1806 + + HSUB_S_D = 1807 + + HSUB_S_H = 1808 + + HSUB_S_W = 1809 + + HSUB_U_D = 1810 + + HSUB_U_H = 1811 + + HSUB_U_W = 1812 + + HYPCALL = 1813 + + HYPCALL_MM = 1814 + + ILVEV_B = 1815 + + ILVEV_D = 1816 + + ILVEV_H = 1817 + + ILVEV_W = 1818 + + ILVL_B = 1819 + + ILVL_D = 1820 + + ILVL_H = 1821 + + ILVL_W = 1822 + + ILVOD_B = 1823 + + ILVOD_D = 1824 + + ILVOD_H = 1825 + + ILVOD_W = 1826 + + ILVR_B = 1827 + + ILVR_D = 1828 + + ILVR_H = 1829 + + ILVR_W = 1830 + + INS = 1831 + + INSERT_B = 1832 + + INSERT_D = 1833 + + INSERT_H = 1834 + + INSERT_W = 1835 + + INSV = 1836 + + INSVE_B = 1837 + + INSVE_D = 1838 + + INSVE_H = 1839 + + INSVE_W = 1840 + + INSV_MM = 1841 + + INS_MM = 1842 + + INS_MMR6 = 1843 + + J = 1844 + + JAL = 1845 + + JALR = 1846 + + JALR16_MM = 1847 + + JALR64 = 1848 + + JALRC16_MMR6 = 1849 + + JALRC_HB_MMR6 = 1850 + + JALRC_MMR6 = 1851 + + JALRS16_MM = 1852 + + JALRS_MM = 1853 + + JALR_HB = 1854 + + JALR_HB64 = 1855 + + JALR_MM = 1856 + + JALS_MM = 1857 + + JALX = 1858 + + JALX_MM = 1859 + + JAL_MM = 1860 + + JIALC = 1861 + + JIALC64 = 1862 + + JIALC_MMR6 = 1863 + + JIC = 1864 + + JIC64 = 1865 + + JIC_MMR6 = 1866 + + JR = 1867 + + JR16_MM = 1868 + + JR64 = 1869 + + JRADDIUSP = 1870 + + JRC16_MM = 1871 + + JRC16_MMR6 = 1872 + + JRCADDIUSP_MMR6 = 1873 + + JR_HB = 1874 + + JR_HB64 = 1875 + + JR_HB64_R6 = 1876 + + JR_HB_R6 = 1877 + + JR_MM = 1878 + + J_MM = 1879 + + Jal16 = 1880 + + JalB16 = 1881 + + JrRa16 = 1882 + + JrcRa16 = 1883 + + JrcRx16 = 1884 + + JumpLinkReg16 = 1885 + + LB = 1886 + + LB64 = 1887 + + LBE = 1888 + + LBE_MM = 1889 + + LBU16_MM = 1890 + + LBUX = 1891 + + LBUX_MM = 1892 + + LBU_MMR6 = 1893 + + LB_MM = 1894 + + LB_MMR6 = 1895 + + LBu = 1896 + + LBu64 = 1897 + + LBuE = 1898 + + LBuE_MM = 1899 + + LBu_MM = 1900 + + LD = 1901 + + LDC1 = 1902 + + LDC164 = 1903 + + LDC1_D64_MMR6 = 1904 + + LDC1_MM_D32 = 1905 + + LDC1_MM_D64 = 1906 + + LDC2 = 1907 + + LDC2_MMR6 = 1908 + + LDC2_R6 = 1909 + + LDC3 = 1910 + + LDI_B = 1911 + + LDI_D = 1912 + + LDI_H = 1913 + + LDI_W = 1914 + + LDL = 1915 + + LDPC = 1916 + + LDR = 1917 + + LDXC1 = 1918 + + LDXC164 = 1919 + + LD_B = 1920 + + LD_D = 1921 + + LD_H = 1922 + + LD_W = 1923 + + LEA_ADDiu = 1924 + + LEA_ADDiu64 = 1925 + + LEA_ADDiu_MM = 1926 + + LH = 1927 + + LH64 = 1928 + + LHE = 1929 + + LHE_MM = 1930 + + LHU16_MM = 1931 + + LHX = 1932 + + LHX_MM = 1933 + + LH_MM = 1934 + + LHu = 1935 + + LHu64 = 1936 + + LHuE = 1937 + + LHuE_MM = 1938 + + LHu_MM = 1939 + + LI16_MM = 1940 + + LI16_MMR6 = 1941 + + LL = 1942 + + LL64 = 1943 + + LL64_R6 = 1944 + + LLD = 1945 + + LLD_R6 = 1946 + + LLE = 1947 + + LLE_MM = 1948 + + LL_MM = 1949 + + LL_MMR6 = 1950 + + LL_R6 = 1951 + + LSA = 1952 + + LSA_MMR6 = 1953 + + LSA_R6 = 1954 + + LUI_MMR6 = 1955 + + LUXC1 = 1956 + + LUXC164 = 1957 + + LUXC1_MM = 1958 + + LUi = 1959 + + LUi64 = 1960 + + LUi_MM = 1961 + + LW = 1962 + + LW16_MM = 1963 + + LW64 = 1964 + + LWC1 = 1965 + + LWC1_MM = 1966 + + LWC2 = 1967 + + LWC2_MMR6 = 1968 + + LWC2_R6 = 1969 + + LWC3 = 1970 + + LWDSP = 1971 + + LWDSP_MM = 1972 + + LWE = 1973 + + LWE_MM = 1974 + + LWGP_MM = 1975 + + LWL = 1976 + + LWL64 = 1977 + + LWLE = 1978 + + LWLE_MM = 1979 + + LWL_MM = 1980 + + LWM16_MM = 1981 + + LWM16_MMR6 = 1982 + + LWM32_MM = 1983 + + LWPC = 1984 + + LWPC_MMR6 = 1985 + + LWP_MM = 1986 + + LWR = 1987 + + LWR64 = 1988 + + LWRE = 1989 + + LWRE_MM = 1990 + + LWR_MM = 1991 + + LWSP_MM = 1992 + + LWUPC = 1993 + + LWU_MM = 1994 + + LWX = 1995 + + LWXC1 = 1996 + + LWXC1_MM = 1997 + + LWXS_MM = 1998 + + LWX_MM = 1999 + + LW_MM = 2000 + + LW_MMR6 = 2001 + + LWu = 2002 + + LbRxRyOffMemX16 = 2003 + + LbuRxRyOffMemX16 = 2004 + + LhRxRyOffMemX16 = 2005 + + LhuRxRyOffMemX16 = 2006 + + LiRxImm16 = 2007 + + LiRxImmAlignX16 = 2008 + + LiRxImmX16 = 2009 + + LwRxPcTcp16 = 2010 + + LwRxPcTcpX16 = 2011 + + LwRxRyOffMemX16 = 2012 + + LwRxSpImmX16 = 2013 + + MADD = 2014 + + MADDF_D = 2015 + + MADDF_D_MMR6 = 2016 + + MADDF_S = 2017 + + MADDF_S_MMR6 = 2018 + + MADDR_Q_H = 2019 + + MADDR_Q_W = 2020 + + MADDU = 2021 + + MADDU_DSP = 2022 + + MADDU_DSP_MM = 2023 + + MADDU_MM = 2024 + + MADDV_B = 2025 + + MADDV_D = 2026 + + MADDV_H = 2027 + + MADDV_W = 2028 + + MADD_D32 = 2029 + + MADD_D32_MM = 2030 + + MADD_D64 = 2031 + + MADD_DSP = 2032 + + MADD_DSP_MM = 2033 + + MADD_MM = 2034 + + MADD_Q_H = 2035 + + MADD_Q_W = 2036 + + MADD_S = 2037 + + MADD_S_MM = 2038 + + MAQ_SA_W_PHL = 2039 + + MAQ_SA_W_PHL_MM = 2040 + + MAQ_SA_W_PHR = 2041 + + MAQ_SA_W_PHR_MM = 2042 + + MAQ_S_W_PHL = 2043 + + MAQ_S_W_PHL_MM = 2044 + + MAQ_S_W_PHR = 2045 + + MAQ_S_W_PHR_MM = 2046 + + MAXA_D = 2047 + + MAXA_D_MMR6 = 2048 + + MAXA_S = 2049 + + MAXA_S_MMR6 = 2050 + + MAXI_S_B = 2051 + + MAXI_S_D = 2052 + + MAXI_S_H = 2053 + + MAXI_S_W = 2054 + + MAXI_U_B = 2055 + + MAXI_U_D = 2056 + + MAXI_U_H = 2057 + + MAXI_U_W = 2058 + + MAX_A_B = 2059 + + MAX_A_D = 2060 + + MAX_A_H = 2061 + + MAX_A_W = 2062 + + MAX_D = 2063 + + MAX_D_MMR6 = 2064 + + MAX_S = 2065 + + MAX_S_B = 2066 + + MAX_S_D = 2067 + + MAX_S_H = 2068 + + MAX_S_MMR6 = 2069 + + MAX_S_W = 2070 + + MAX_U_B = 2071 + + MAX_U_D = 2072 + + MAX_U_H = 2073 + + MAX_U_W = 2074 + + MFC0 = 2075 + + MFC0_MMR6 = 2076 + + MFC1 = 2077 + + MFC1_D64 = 2078 + + MFC1_MM = 2079 + + MFC1_MMR6 = 2080 + + MFC2 = 2081 + + MFC2_MMR6 = 2082 + + MFGC0 = 2083 + + MFGC0_MM = 2084 + + MFHC0_MMR6 = 2085 + + MFHC1_D32 = 2086 + + MFHC1_D32_MM = 2087 + + MFHC1_D64 = 2088 + + MFHC1_D64_MM = 2089 + + MFHC2_MMR6 = 2090 + + MFHGC0 = 2091 + + MFHGC0_MM = 2092 + + MFHI = 2093 + + MFHI16_MM = 2094 + + MFHI64 = 2095 + + MFHI_DSP = 2096 + + MFHI_DSP_MM = 2097 + + MFHI_MM = 2098 + + MFLO = 2099 + + MFLO16_MM = 2100 + + MFLO64 = 2101 + + MFLO_DSP = 2102 + + MFLO_DSP_MM = 2103 + + MFLO_MM = 2104 + + MFTR = 2105 + + MINA_D = 2106 + + MINA_D_MMR6 = 2107 + + MINA_S = 2108 + + MINA_S_MMR6 = 2109 + + MINI_S_B = 2110 + + MINI_S_D = 2111 + + MINI_S_H = 2112 + + MINI_S_W = 2113 + + MINI_U_B = 2114 + + MINI_U_D = 2115 + + MINI_U_H = 2116 + + MINI_U_W = 2117 + + MIN_A_B = 2118 + + MIN_A_D = 2119 + + MIN_A_H = 2120 + + MIN_A_W = 2121 + + MIN_D = 2122 + + MIN_D_MMR6 = 2123 + + MIN_S = 2124 + + MIN_S_B = 2125 + + MIN_S_D = 2126 + + MIN_S_H = 2127 + + MIN_S_MMR6 = 2128 + + MIN_S_W = 2129 + + MIN_U_B = 2130 + + MIN_U_D = 2131 + + MIN_U_H = 2132 + + MIN_U_W = 2133 + + MOD = 2134 + + MODSUB = 2135 + + MODSUB_MM = 2136 + + MODU = 2137 + + MODU_MMR6 = 2138 + + MOD_MMR6 = 2139 + + MOD_S_B = 2140 + + MOD_S_D = 2141 + + MOD_S_H = 2142 + + MOD_S_W = 2143 + + MOD_U_B = 2144 + + MOD_U_D = 2145 + + MOD_U_H = 2146 + + MOD_U_W = 2147 + + MOVE16_MM = 2148 + + MOVE16_MMR6 = 2149 + + MOVEP_MM = 2150 + + MOVEP_MMR6 = 2151 + + MOVE_V = 2152 + + MOVF_D32 = 2153 + + MOVF_D32_MM = 2154 + + MOVF_D64 = 2155 + + MOVF_I = 2156 + + MOVF_I64 = 2157 + + MOVF_I_MM = 2158 + + MOVF_S = 2159 + + MOVF_S_MM = 2160 + + MOVN_I64_D64 = 2161 + + MOVN_I64_I = 2162 + + MOVN_I64_I64 = 2163 + + MOVN_I64_S = 2164 + + MOVN_I_D32 = 2165 + + MOVN_I_D32_MM = 2166 + + MOVN_I_D64 = 2167 + + MOVN_I_I = 2168 + + MOVN_I_I64 = 2169 + + MOVN_I_MM = 2170 + + MOVN_I_S = 2171 + + MOVN_I_S_MM = 2172 + + MOVT_D32 = 2173 + + MOVT_D32_MM = 2174 + + MOVT_D64 = 2175 + + MOVT_I = 2176 + + MOVT_I64 = 2177 + + MOVT_I_MM = 2178 + + MOVT_S = 2179 + + MOVT_S_MM = 2180 + + MOVZ_I64_D64 = 2181 + + MOVZ_I64_I = 2182 + + MOVZ_I64_I64 = 2183 + + MOVZ_I64_S = 2184 + + MOVZ_I_D32 = 2185 + + MOVZ_I_D32_MM = 2186 + + MOVZ_I_D64 = 2187 + + MOVZ_I_I = 2188 + + MOVZ_I_I64 = 2189 + + MOVZ_I_MM = 2190 + + MOVZ_I_S = 2191 + + MOVZ_I_S_MM = 2192 + + MSUB = 2193 + + MSUBF_D = 2194 + + MSUBF_D_MMR6 = 2195 + + MSUBF_S = 2196 + + MSUBF_S_MMR6 = 2197 + + MSUBR_Q_H = 2198 + + MSUBR_Q_W = 2199 + + MSUBU = 2200 + + MSUBU_DSP = 2201 + + MSUBU_DSP_MM = 2202 + + MSUBU_MM = 2203 + + MSUBV_B = 2204 + + MSUBV_D = 2205 + + MSUBV_H = 2206 + + MSUBV_W = 2207 + + MSUB_D32 = 2208 + + MSUB_D32_MM = 2209 + + MSUB_D64 = 2210 + + MSUB_DSP = 2211 + + MSUB_DSP_MM = 2212 + + MSUB_MM = 2213 + + MSUB_Q_H = 2214 + + MSUB_Q_W = 2215 + + MSUB_S = 2216 + + MSUB_S_MM = 2217 + + MTC0 = 2218 + + MTC0_MMR6 = 2219 + + MTC1 = 2220 + + MTC1_D64 = 2221 + + MTC1_D64_MM = 2222 + + MTC1_MM = 2223 + + MTC1_MMR6 = 2224 + + MTC2 = 2225 + + MTC2_MMR6 = 2226 + + MTGC0 = 2227 + + MTGC0_MM = 2228 + + MTHC0_MMR6 = 2229 + + MTHC1_D32 = 2230 + + MTHC1_D32_MM = 2231 + + MTHC1_D64 = 2232 + + MTHC1_D64_MM = 2233 + + MTHC2_MMR6 = 2234 + + MTHGC0 = 2235 + + MTHGC0_MM = 2236 + + MTHI = 2237 + + MTHI64 = 2238 + + MTHI_DSP = 2239 + + MTHI_DSP_MM = 2240 + + MTHI_MM = 2241 + + MTHLIP = 2242 + + MTHLIP_MM = 2243 + + MTLO = 2244 + + MTLO64 = 2245 + + MTLO_DSP = 2246 + + MTLO_DSP_MM = 2247 + + MTLO_MM = 2248 + + MTM0 = 2249 + + MTM1 = 2250 + + MTM2 = 2251 + + MTP0 = 2252 + + MTP1 = 2253 + + MTP2 = 2254 + + MTTR = 2255 + + MUH = 2256 + + MUHU = 2257 + + MUHU_MMR6 = 2258 + + MUH_MMR6 = 2259 + + MUL = 2260 + + MULEQ_S_W_PHL = 2261 + + MULEQ_S_W_PHL_MM = 2262 + + MULEQ_S_W_PHR = 2263 + + MULEQ_S_W_PHR_MM = 2264 + + MULEU_S_PH_QBL = 2265 + + MULEU_S_PH_QBL_MM = 2266 + + MULEU_S_PH_QBR = 2267 + + MULEU_S_PH_QBR_MM = 2268 + + MULQ_RS_PH = 2269 + + MULQ_RS_PH_MM = 2270 + + MULQ_RS_W = 2271 + + MULQ_RS_W_MMR2 = 2272 + + MULQ_S_PH = 2273 + + MULQ_S_PH_MMR2 = 2274 + + MULQ_S_W = 2275 + + MULQ_S_W_MMR2 = 2276 + + MULR_PS64 = 2277 + + MULR_Q_H = 2278 + + MULR_Q_W = 2279 + + MULSAQ_S_W_PH = 2280 + + MULSAQ_S_W_PH_MM = 2281 + + MULSA_W_PH = 2282 + + MULSA_W_PH_MMR2 = 2283 + + MULT = 2284 + + MULTU_DSP = 2285 + + MULTU_DSP_MM = 2286 + + MULT_DSP = 2287 + + MULT_DSP_MM = 2288 + + MULT_MM = 2289 + + MULTu = 2290 + + MULTu_MM = 2291 + + MULU = 2292 + + MULU_MMR6 = 2293 + + MULV_B = 2294 + + MULV_D = 2295 + + MULV_H = 2296 + + MULV_W = 2297 + + MUL_MM = 2298 + + MUL_MMR6 = 2299 + + MUL_PH = 2300 + + MUL_PH_MMR2 = 2301 + + MUL_Q_H = 2302 + + MUL_Q_W = 2303 + + MUL_R6 = 2304 + + MUL_S_PH = 2305 + + MUL_S_PH_MMR2 = 2306 + + Mfhi16 = 2307 + + Mflo16 = 2308 + + Move32R16 = 2309 + + MoveR3216 = 2310 + + NAL = 2311 + + NLOC_B = 2312 + + NLOC_D = 2313 + + NLOC_H = 2314 + + NLOC_W = 2315 + + NLZC_B = 2316 + + NLZC_D = 2317 + + NLZC_H = 2318 + + NLZC_W = 2319 + + NMADD_D32 = 2320 + + NMADD_D32_MM = 2321 + + NMADD_D64 = 2322 + + NMADD_S = 2323 + + NMADD_S_MM = 2324 + + NMSUB_D32 = 2325 + + NMSUB_D32_MM = 2326 + + NMSUB_D64 = 2327 + + NMSUB_S = 2328 + + NMSUB_S_MM = 2329 + + NOR = 2330 + + NOR64 = 2331 + + NORI_B = 2332 + + NOR_MM = 2333 + + NOR_MMR6 = 2334 + + NOR_V = 2335 + + NOT16_MM = 2336 + + NOT16_MMR6 = 2337 + + NegRxRy16 = 2338 + + NotRxRy16 = 2339 + + OR = 2340 + + OR16_MM = 2341 + + OR16_MMR6 = 2342 + + OR64 = 2343 + + ORI_B = 2344 + + ORI_MMR6 = 2345 + + OR_MM = 2346 + + OR_MMR6 = 2347 + + OR_V = 2348 + + ORi = 2349 + + ORi64 = 2350 + + ORi_MM = 2351 + + OrRxRxRy16 = 2352 + + PACKRL_PH = 2353 + + PACKRL_PH_MM = 2354 + + PAUSE = 2355 + + PAUSE_MM = 2356 + + PAUSE_MMR6 = 2357 + + PCKEV_B = 2358 + + PCKEV_D = 2359 + + PCKEV_H = 2360 + + PCKEV_W = 2361 + + PCKOD_B = 2362 + + PCKOD_D = 2363 + + PCKOD_H = 2364 + + PCKOD_W = 2365 + + PCNT_B = 2366 + + PCNT_D = 2367 + + PCNT_H = 2368 + + PCNT_W = 2369 + + PICK_PH = 2370 + + PICK_PH_MM = 2371 + + PICK_QB = 2372 + + PICK_QB_MM = 2373 + + PLL_PS64 = 2374 + + PLU_PS64 = 2375 + + POP = 2376 + + PRECEQU_PH_QBL = 2377 + + PRECEQU_PH_QBLA = 2378 + + PRECEQU_PH_QBLA_MM = 2379 + + PRECEQU_PH_QBL_MM = 2380 + + PRECEQU_PH_QBR = 2381 + + PRECEQU_PH_QBRA = 2382 + + PRECEQU_PH_QBRA_MM = 2383 + + PRECEQU_PH_QBR_MM = 2384 + + PRECEQ_W_PHL = 2385 + + PRECEQ_W_PHL_MM = 2386 + + PRECEQ_W_PHR = 2387 + + PRECEQ_W_PHR_MM = 2388 + + PRECEU_PH_QBL = 2389 + + PRECEU_PH_QBLA = 2390 + + PRECEU_PH_QBLA_MM = 2391 + + PRECEU_PH_QBL_MM = 2392 + + PRECEU_PH_QBR = 2393 + + PRECEU_PH_QBRA = 2394 + + PRECEU_PH_QBRA_MM = 2395 + + PRECEU_PH_QBR_MM = 2396 + + PRECRQU_S_QB_PH = 2397 + + PRECRQU_S_QB_PH_MM = 2398 + + PRECRQ_PH_W = 2399 + + PRECRQ_PH_W_MM = 2400 + + PRECRQ_QB_PH = 2401 + + PRECRQ_QB_PH_MM = 2402 + + PRECRQ_RS_PH_W = 2403 + + PRECRQ_RS_PH_W_MM = 2404 + + PRECR_QB_PH = 2405 + + PRECR_QB_PH_MMR2 = 2406 + + PRECR_SRA_PH_W = 2407 + + PRECR_SRA_PH_W_MMR2 = 2408 + + PRECR_SRA_R_PH_W = 2409 + + PRECR_SRA_R_PH_W_MMR2 = 2410 + + PREF = 2411 + + PREFE = 2412 + + PREFE_MM = 2413 + + PREFX_MM = 2414 + + PREF_MM = 2415 + + PREF_MMR6 = 2416 + + PREF_R6 = 2417 + + PREPEND = 2418 + + PREPEND_MMR2 = 2419 + + PUL_PS64 = 2420 + + PUU_PS64 = 2421 + + RADDU_W_QB = 2422 + + RADDU_W_QB_MM = 2423 + + RDDSP = 2424 + + RDDSP_MM = 2425 + + RDHWR = 2426 + + RDHWR64 = 2427 + + RDHWR_MM = 2428 + + RDHWR_MMR6 = 2429 + + RDPGPR_MMR6 = 2430 + + RECIP_D32 = 2431 + + RECIP_D32_MM = 2432 + + RECIP_D64 = 2433 + + RECIP_D64_MM = 2434 + + RECIP_S = 2435 + + RECIP_S_MM = 2436 + + REPLV_PH = 2437 + + REPLV_PH_MM = 2438 + + REPLV_QB = 2439 + + REPLV_QB_MM = 2440 + + REPL_PH = 2441 + + REPL_PH_MM = 2442 + + REPL_QB = 2443 + + REPL_QB_MM = 2444 + + RINT_D = 2445 + + RINT_D_MMR6 = 2446 + + RINT_S = 2447 + + RINT_S_MMR6 = 2448 + + ROTR = 2449 + + ROTRV = 2450 + + ROTRV_MM = 2451 + + ROTR_MM = 2452 + + ROUND_L_D64 = 2453 + + ROUND_L_D_MMR6 = 2454 + + ROUND_L_S = 2455 + + ROUND_L_S_MMR6 = 2456 + + ROUND_W_D32 = 2457 + + ROUND_W_D64 = 2458 + + ROUND_W_D_MMR6 = 2459 + + ROUND_W_MM = 2460 + + ROUND_W_S = 2461 + + ROUND_W_S_MM = 2462 + + ROUND_W_S_MMR6 = 2463 + + RSQRT_D32 = 2464 + + RSQRT_D32_MM = 2465 + + RSQRT_D64 = 2466 + + RSQRT_D64_MM = 2467 + + RSQRT_S = 2468 + + RSQRT_S_MM = 2469 + + Restore16 = 2470 + + RestoreX16 = 2471 + + SAA = 2472 + + SAAD = 2473 + + SAT_S_B = 2474 + + SAT_S_D = 2475 + + SAT_S_H = 2476 + + SAT_S_W = 2477 + + SAT_U_B = 2478 + + SAT_U_D = 2479 + + SAT_U_H = 2480 + + SAT_U_W = 2481 + + SB = 2482 + + SB16_MM = 2483 + + SB16_MMR6 = 2484 + + SB64 = 2485 + + SBE = 2486 + + SBE_MM = 2487 + + SB_MM = 2488 + + SB_MMR6 = 2489 + + SC = 2490 + + SC64 = 2491 + + SC64_R6 = 2492 + + SCD = 2493 + + SCD_R6 = 2494 + + SCE = 2495 + + SCE_MM = 2496 + + SC_MM = 2497 + + SC_MMR6 = 2498 + + SC_R6 = 2499 + + SD = 2500 + + SDBBP = 2501 + + SDBBP16_MM = 2502 + + SDBBP16_MMR6 = 2503 + + SDBBP_MM = 2504 + + SDBBP_MMR6 = 2505 + + SDBBP_R6 = 2506 + + SDC1 = 2507 + + SDC164 = 2508 + + SDC1_D64_MMR6 = 2509 + + SDC1_MM_D32 = 2510 + + SDC1_MM_D64 = 2511 + + SDC2 = 2512 + + SDC2_MMR6 = 2513 + + SDC2_R6 = 2514 + + SDC3 = 2515 + + SDIV = 2516 + + SDIV_MM = 2517 + + SDL = 2518 + + SDR = 2519 + + SDXC1 = 2520 + + SDXC164 = 2521 + + SEB = 2522 + + SEB64 = 2523 + + SEB_MM = 2524 + + SEH = 2525 + + SEH64 = 2526 + + SEH_MM = 2527 + + SELEQZ = 2528 + + SELEQZ64 = 2529 + + SELEQZ_D = 2530 + + SELEQZ_D_MMR6 = 2531 + + SELEQZ_MMR6 = 2532 + + SELEQZ_S = 2533 + + SELEQZ_S_MMR6 = 2534 + + SELNEZ = 2535 + + SELNEZ64 = 2536 + + SELNEZ_D = 2537 + + SELNEZ_D_MMR6 = 2538 + + SELNEZ_MMR6 = 2539 + + SELNEZ_S = 2540 + + SELNEZ_S_MMR6 = 2541 + + SEL_D = 2542 + + SEL_D_MMR6 = 2543 + + SEL_S = 2544 + + SEL_S_MMR6 = 2545 + + SEQ = 2546 + + SEQi = 2547 + + SH = 2548 + + SH16_MM = 2549 + + SH16_MMR6 = 2550 + + SH64 = 2551 + + SHE = 2552 + + SHE_MM = 2553 + + SHF_B = 2554 + + SHF_H = 2555 + + SHF_W = 2556 + + SHILO = 2557 + + SHILOV = 2558 + + SHILOV_MM = 2559 + + SHILO_MM = 2560 + + SHLLV_PH = 2561 + + SHLLV_PH_MM = 2562 + + SHLLV_QB = 2563 + + SHLLV_QB_MM = 2564 + + SHLLV_S_PH = 2565 + + SHLLV_S_PH_MM = 2566 + + SHLLV_S_W = 2567 + + SHLLV_S_W_MM = 2568 + + SHLL_PH = 2569 + + SHLL_PH_MM = 2570 + + SHLL_QB = 2571 + + SHLL_QB_MM = 2572 + + SHLL_S_PH = 2573 + + SHLL_S_PH_MM = 2574 + + SHLL_S_W = 2575 + + SHLL_S_W_MM = 2576 + + SHRAV_PH = 2577 + + SHRAV_PH_MM = 2578 + + SHRAV_QB = 2579 + + SHRAV_QB_MMR2 = 2580 + + SHRAV_R_PH = 2581 + + SHRAV_R_PH_MM = 2582 + + SHRAV_R_QB = 2583 + + SHRAV_R_QB_MMR2 = 2584 + + SHRAV_R_W = 2585 + + SHRAV_R_W_MM = 2586 + + SHRA_PH = 2587 + + SHRA_PH_MM = 2588 + + SHRA_QB = 2589 + + SHRA_QB_MMR2 = 2590 + + SHRA_R_PH = 2591 + + SHRA_R_PH_MM = 2592 + + SHRA_R_QB = 2593 + + SHRA_R_QB_MMR2 = 2594 + + SHRA_R_W = 2595 + + SHRA_R_W_MM = 2596 + + SHRLV_PH = 2597 + + SHRLV_PH_MMR2 = 2598 + + SHRLV_QB = 2599 + + SHRLV_QB_MM = 2600 + + SHRL_PH = 2601 + + SHRL_PH_MMR2 = 2602 + + SHRL_QB = 2603 + + SHRL_QB_MM = 2604 + + SH_MM = 2605 + + SH_MMR6 = 2606 + + SIGRIE = 2607 + + SIGRIE_MMR6 = 2608 + + SLDI_B = 2609 + + SLDI_D = 2610 + + SLDI_H = 2611 + + SLDI_W = 2612 + + SLD_B = 2613 + + SLD_D = 2614 + + SLD_H = 2615 + + SLD_W = 2616 + + SLL = 2617 + + SLL16_MM = 2618 + + SLL16_MMR6 = 2619 + + SLL64_32 = 2620 + + SLL64_64 = 2621 + + SLLI_B = 2622 + + SLLI_D = 2623 + + SLLI_H = 2624 + + SLLI_W = 2625 + + SLLV = 2626 + + SLLV_MM = 2627 + + SLL_B = 2628 + + SLL_D = 2629 + + SLL_H = 2630 + + SLL_MM = 2631 + + SLL_MMR6 = 2632 + + SLL_W = 2633 + + SLT = 2634 + + SLT64 = 2635 + + SLT_MM = 2636 + + SLTi = 2637 + + SLTi64 = 2638 + + SLTi_MM = 2639 + + SLTiu = 2640 + + SLTiu64 = 2641 + + SLTiu_MM = 2642 + + SLTu = 2643 + + SLTu64 = 2644 + + SLTu_MM = 2645 + + SNE = 2646 + + SNEi = 2647 + + SPLATI_B = 2648 + + SPLATI_D = 2649 + + SPLATI_H = 2650 + + SPLATI_W = 2651 + + SPLAT_B = 2652 + + SPLAT_D = 2653 + + SPLAT_H = 2654 + + SPLAT_W = 2655 + + SRA = 2656 + + SRAI_B = 2657 + + SRAI_D = 2658 + + SRAI_H = 2659 + + SRAI_W = 2660 + + SRARI_B = 2661 + + SRARI_D = 2662 + + SRARI_H = 2663 + + SRARI_W = 2664 + + SRAR_B = 2665 + + SRAR_D = 2666 + + SRAR_H = 2667 + + SRAR_W = 2668 + + SRAV = 2669 + + SRAV_MM = 2670 + + SRA_B = 2671 + + SRA_D = 2672 + + SRA_H = 2673 + + SRA_MM = 2674 + + SRA_W = 2675 + + SRL = 2676 + + SRL16_MM = 2677 + + SRL16_MMR6 = 2678 + + SRLI_B = 2679 + + SRLI_D = 2680 + + SRLI_H = 2681 + + SRLI_W = 2682 + + SRLRI_B = 2683 + + SRLRI_D = 2684 + + SRLRI_H = 2685 + + SRLRI_W = 2686 + + SRLR_B = 2687 + + SRLR_D = 2688 + + SRLR_H = 2689 + + SRLR_W = 2690 + + SRLV = 2691 + + SRLV_MM = 2692 + + SRL_B = 2693 + + SRL_D = 2694 + + SRL_H = 2695 + + SRL_MM = 2696 + + SRL_W = 2697 + + SSNOP = 2698 + + SSNOP_MM = 2699 + + SSNOP_MMR6 = 2700 + + ST_B = 2701 + + ST_D = 2702 + + ST_H = 2703 + + ST_W = 2704 + + SUB = 2705 + + SUBQH_PH = 2706 + + SUBQH_PH_MMR2 = 2707 + + SUBQH_R_PH = 2708 + + SUBQH_R_PH_MMR2 = 2709 + + SUBQH_R_W = 2710 + + SUBQH_R_W_MMR2 = 2711 + + SUBQH_W = 2712 + + SUBQH_W_MMR2 = 2713 + + SUBQ_PH = 2714 + + SUBQ_PH_MM = 2715 + + SUBQ_S_PH = 2716 + + SUBQ_S_PH_MM = 2717 + + SUBQ_S_W = 2718 + + SUBQ_S_W_MM = 2719 + + SUBSUS_U_B = 2720 + + SUBSUS_U_D = 2721 + + SUBSUS_U_H = 2722 + + SUBSUS_U_W = 2723 + + SUBSUU_S_B = 2724 + + SUBSUU_S_D = 2725 + + SUBSUU_S_H = 2726 + + SUBSUU_S_W = 2727 + + SUBS_S_B = 2728 + + SUBS_S_D = 2729 + + SUBS_S_H = 2730 + + SUBS_S_W = 2731 + + SUBS_U_B = 2732 + + SUBS_U_D = 2733 + + SUBS_U_H = 2734 + + SUBS_U_W = 2735 + + SUBU16_MM = 2736 + + SUBU16_MMR6 = 2737 + + SUBUH_QB = 2738 + + SUBUH_QB_MMR2 = 2739 + + SUBUH_R_QB = 2740 + + SUBUH_R_QB_MMR2 = 2741 + + SUBU_MMR6 = 2742 + + SUBU_PH = 2743 + + SUBU_PH_MMR2 = 2744 + + SUBU_QB = 2745 + + SUBU_QB_MM = 2746 + + SUBU_S_PH = 2747 + + SUBU_S_PH_MMR2 = 2748 + + SUBU_S_QB = 2749 + + SUBU_S_QB_MM = 2750 + + SUBVI_B = 2751 + + SUBVI_D = 2752 + + SUBVI_H = 2753 + + SUBVI_W = 2754 + + SUBV_B = 2755 + + SUBV_D = 2756 + + SUBV_H = 2757 + + SUBV_W = 2758 + + SUB_MM = 2759 + + SUB_MMR6 = 2760 + + SUBu = 2761 + + SUBu_MM = 2762 + + SUXC1 = 2763 + + SUXC164 = 2764 + + SUXC1_MM = 2765 + + SW = 2766 + + SW16_MM = 2767 + + SW16_MMR6 = 2768 + + SW64 = 2769 + + SWC1 = 2770 + + SWC1_MM = 2771 + + SWC2 = 2772 + + SWC2_MMR6 = 2773 + + SWC2_R6 = 2774 + + SWC3 = 2775 + + SWDSP = 2776 + + SWDSP_MM = 2777 + + SWE = 2778 + + SWE_MM = 2779 + + SWL = 2780 + + SWL64 = 2781 + + SWLE = 2782 + + SWLE_MM = 2783 + + SWL_MM = 2784 + + SWM16_MM = 2785 + + SWM16_MMR6 = 2786 + + SWM32_MM = 2787 + + SWP_MM = 2788 + + SWR = 2789 + + SWR64 = 2790 + + SWRE = 2791 + + SWRE_MM = 2792 + + SWR_MM = 2793 + + SWSP_MM = 2794 + + SWSP_MMR6 = 2795 + + SWXC1 = 2796 + + SWXC1_MM = 2797 + + SW_MM = 2798 + + SW_MMR6 = 2799 + + SYNC = 2800 + + SYNCI = 2801 + + SYNCI_MM = 2802 + + SYNCI_MMR6 = 2803 + + SYNC_MM = 2804 + + SYNC_MMR6 = 2805 + + SYSCALL = 2806 + + SYSCALL_MM = 2807 + + Save16 = 2808 + + SaveX16 = 2809 + + SbRxRyOffMemX16 = 2810 + + SebRx16 = 2811 + + SehRx16 = 2812 + + ShRxRyOffMemX16 = 2813 + + SllX16 = 2814 + + SllvRxRy16 = 2815 + + SltRxRy16 = 2816 + + SltiRxImm16 = 2817 + + SltiRxImmX16 = 2818 + + SltiuRxImm16 = 2819 + + SltiuRxImmX16 = 2820 + + SltuRxRy16 = 2821 + + SraX16 = 2822 + + SravRxRy16 = 2823 + + SrlX16 = 2824 + + SrlvRxRy16 = 2825 + + SubuRxRyRz16 = 2826 + + SwRxRyOffMemX16 = 2827 + + SwRxSpImmX16 = 2828 + + TEQ = 2829 + + TEQI = 2830 + + TEQI_MM = 2831 + + TEQ_MM = 2832 + + TGE = 2833 + + TGEI = 2834 + + TGEIU = 2835 + + TGEIU_MM = 2836 + + TGEI_MM = 2837 + + TGEU = 2838 + + TGEU_MM = 2839 + + TGE_MM = 2840 + + TLBGINV = 2841 + + TLBGINVF = 2842 + + TLBGINVF_MM = 2843 + + TLBGINV_MM = 2844 + + TLBGP = 2845 + + TLBGP_MM = 2846 + + TLBGR = 2847 + + TLBGR_MM = 2848 + + TLBGWI = 2849 + + TLBGWI_MM = 2850 + + TLBGWR = 2851 + + TLBGWR_MM = 2852 + + TLBINV = 2853 + + TLBINVF = 2854 + + TLBINVF_MMR6 = 2855 + + TLBINV_MMR6 = 2856 + + TLBP = 2857 + + TLBP_MM = 2858 + + TLBR = 2859 + + TLBR_MM = 2860 + + TLBWI = 2861 + + TLBWI_MM = 2862 + + TLBWR = 2863 + + TLBWR_MM = 2864 + + TLT = 2865 + + TLTI = 2866 + + TLTIU_MM = 2867 + + TLTI_MM = 2868 + + TLTU = 2869 + + TLTU_MM = 2870 + + TLT_MM = 2871 + + TNE = 2872 + + TNEI = 2873 + + TNEI_MM = 2874 + + TNE_MM = 2875 + + TRUNC_L_D64 = 2876 + + TRUNC_L_D_MMR6 = 2877 + + TRUNC_L_S = 2878 + + TRUNC_L_S_MMR6 = 2879 + + TRUNC_W_D32 = 2880 + + TRUNC_W_D64 = 2881 + + TRUNC_W_D_MMR6 = 2882 + + TRUNC_W_MM = 2883 + + TRUNC_W_S = 2884 + + TRUNC_W_S_MM = 2885 + + TRUNC_W_S_MMR6 = 2886 + + TTLTIU = 2887 + + UDIV = 2888 + + UDIV_MM = 2889 + + V3MULU = 2890 + + VMM0 = 2891 + + VMULU = 2892 + + VSHF_B = 2893 + + VSHF_D = 2894 + + VSHF_H = 2895 + + VSHF_W = 2896 + + WAIT = 2897 + + WAIT_MM = 2898 + + WAIT_MMR6 = 2899 + + WRDSP = 2900 + + WRDSP_MM = 2901 + + WRPGPR_MMR6 = 2902 + + WSBH = 2903 + + WSBH_MM = 2904 + + WSBH_MMR6 = 2905 + + XOR = 2906 + + XOR16_MM = 2907 + + XOR16_MMR6 = 2908 + + XOR64 = 2909 + + XORI_B = 2910 + + XORI_MMR6 = 2911 + + XOR_MM = 2912 + + XOR_MMR6 = 2913 + + XOR_V = 2914 + + XORi = 2915 + + XORi64 = 2916 + + XORi_MM = 2917 + + XorRxRxRy16 = 2918 + + YIELD = 2919 + + INSTRUCTION_LIST_END = 2920 + +class REG(enum.Enum): + NoRegister = 0 + + AT = 1 + + DSPCCond = 2 + + DSPCarry = 3 + + DSPEFI = 4 + + DSPOutFlag = 5 + + DSPPos = 6 + + DSPSCount = 7 + + FP = 8 + + GP = 9 + + MSAAccess = 10 + + MSACSR = 11 + + MSAIR = 12 + + MSAMap = 13 + + MSAModify = 14 + + MSARequest = 15 + + MSASave = 16 + + MSAUnmap = 17 + + PC = 18 + + RA = 19 + + SP = 20 + + ZERO = 21 + + A0 = 22 + + A1 = 23 + + A2 = 24 + + A3 = 25 + + AC0 = 26 + + AC1 = 27 + + AC2 = 28 + + AC3 = 29 + + AT_64 = 30 + + COP00 = 31 + + COP01 = 32 + + COP02 = 33 + + COP03 = 34 + + COP04 = 35 + + COP05 = 36 + + COP06 = 37 + + COP07 = 38 + + COP08 = 39 + + COP09 = 40 + + COP20 = 41 + + COP21 = 42 + + COP22 = 43 + + COP23 = 44 + + COP24 = 45 + + COP25 = 46 + + COP26 = 47 + + COP27 = 48 + + COP28 = 49 + + COP29 = 50 + + COP30 = 51 + + COP31 = 52 + + COP32 = 53 + + COP33 = 54 + + COP34 = 55 + + COP35 = 56 + + COP36 = 57 + + COP37 = 58 + + COP38 = 59 + + COP39 = 60 + + COP010 = 61 + + COP011 = 62 + + COP012 = 63 + + COP013 = 64 + + COP014 = 65 + + COP015 = 66 + + COP016 = 67 + + COP017 = 68 + + COP018 = 69 + + COP019 = 70 + + COP020 = 71 + + COP021 = 72 + + COP022 = 73 + + COP023 = 74 + + COP024 = 75 + + COP025 = 76 + + COP026 = 77 + + COP027 = 78 + + COP028 = 79 + + COP029 = 80 + + COP030 = 81 + + COP031 = 82 + + COP210 = 83 + + COP211 = 84 + + COP212 = 85 + + COP213 = 86 + + COP214 = 87 + + COP215 = 88 + + COP216 = 89 + + COP217 = 90 + + COP218 = 91 + + COP219 = 92 + + COP220 = 93 + + COP221 = 94 + + COP222 = 95 + + COP223 = 96 + + COP224 = 97 + + COP225 = 98 + + COP226 = 99 + + COP227 = 100 + + COP228 = 101 + + COP229 = 102 + + COP230 = 103 + + COP231 = 104 + + COP310 = 105 + + COP311 = 106 + + COP312 = 107 + + COP313 = 108 + + COP314 = 109 + + COP315 = 110 + + COP316 = 111 + + COP317 = 112 + + COP318 = 113 + + COP319 = 114 + + COP320 = 115 + + COP321 = 116 + + COP322 = 117 + + COP323 = 118 + + COP324 = 119 + + COP325 = 120 + + COP326 = 121 + + COP327 = 122 + + COP328 = 123 + + COP329 = 124 + + COP330 = 125 + + COP331 = 126 + + D0 = 127 + + D1 = 128 + + D2 = 129 + + D3 = 130 + + D4 = 131 + + D5 = 132 + + D6 = 133 + + D7 = 134 + + D8 = 135 + + D9 = 136 + + D10 = 137 + + D11 = 138 + + D12 = 139 + + D13 = 140 + + D14 = 141 + + D15 = 142 + + DSPOutFlag20 = 143 + + DSPOutFlag21 = 144 + + DSPOutFlag22 = 145 + + DSPOutFlag23 = 146 + + F0 = 147 + + F1 = 148 + + F2 = 149 + + F3 = 150 + + F4 = 151 + + F5 = 152 + + F6 = 153 + + F7 = 154 + + F8 = 155 + + F9 = 156 + + F10 = 157 + + F11 = 158 + + F12 = 159 + + F13 = 160 + + F14 = 161 + + F15 = 162 + + F16 = 163 + + F17 = 164 + + F18 = 165 + + F19 = 166 + + F20 = 167 + + F21 = 168 + + F22 = 169 + + F23 = 170 + + F24 = 171 + + F25 = 172 + + F26 = 173 + + F27 = 174 + + F28 = 175 + + F29 = 176 + + F30 = 177 + + F31 = 178 + + FCC0 = 179 + + FCC1 = 180 + + FCC2 = 181 + + FCC3 = 182 + + FCC4 = 183 + + FCC5 = 184 + + FCC6 = 185 + + FCC7 = 186 + + FCR0 = 187 + + FCR1 = 188 + + FCR2 = 189 + + FCR3 = 190 + + FCR4 = 191 + + FCR5 = 192 + + FCR6 = 193 + + FCR7 = 194 + + FCR8 = 195 + + FCR9 = 196 + + FCR10 = 197 + + FCR11 = 198 + + FCR12 = 199 + + FCR13 = 200 + + FCR14 = 201 + + FCR15 = 202 + + FCR16 = 203 + + FCR17 = 204 + + FCR18 = 205 + + FCR19 = 206 + + FCR20 = 207 + + FCR21 = 208 + + FCR22 = 209 + + FCR23 = 210 + + FCR24 = 211 + + FCR25 = 212 + + FCR26 = 213 + + FCR27 = 214 + + FCR28 = 215 + + FCR29 = 216 + + FCR30 = 217 + + FCR31 = 218 + + FP_64 = 219 + + F_HI0 = 220 + + F_HI1 = 221 + + F_HI2 = 222 + + F_HI3 = 223 + + F_HI4 = 224 + + F_HI5 = 225 + + F_HI6 = 226 + + F_HI7 = 227 + + F_HI8 = 228 + + F_HI9 = 229 + + F_HI10 = 230 + + F_HI11 = 231 + + F_HI12 = 232 + + F_HI13 = 233 + + F_HI14 = 234 + + F_HI15 = 235 + + F_HI16 = 236 + + F_HI17 = 237 + + F_HI18 = 238 + + F_HI19 = 239 + + F_HI20 = 240 + + F_HI21 = 241 + + F_HI22 = 242 + + F_HI23 = 243 + + F_HI24 = 244 + + F_HI25 = 245 + + F_HI26 = 246 + + F_HI27 = 247 + + F_HI28 = 248 + + F_HI29 = 249 + + F_HI30 = 250 + + F_HI31 = 251 + + GP_64 = 252 + + HI0 = 253 + + HI1 = 254 + + HI2 = 255 + + HI3 = 256 + + HWR0 = 257 + + HWR1 = 258 + + HWR2 = 259 + + HWR3 = 260 + + HWR4 = 261 + + HWR5 = 262 + + HWR6 = 263 + + HWR7 = 264 + + HWR8 = 265 + + HWR9 = 266 + + HWR10 = 267 + + HWR11 = 268 + + HWR12 = 269 + + HWR13 = 270 + + HWR14 = 271 + + HWR15 = 272 + + HWR16 = 273 + + HWR17 = 274 + + HWR18 = 275 + + HWR19 = 276 + + HWR20 = 277 + + HWR21 = 278 + + HWR22 = 279 + + HWR23 = 280 + + HWR24 = 281 + + HWR25 = 282 + + HWR26 = 283 + + HWR27 = 284 + + HWR28 = 285 + + HWR29 = 286 + + HWR30 = 287 + + HWR31 = 288 + + K0 = 289 + + K1 = 290 + + LO0 = 291 + + LO1 = 292 + + LO2 = 293 + + LO3 = 294 + + MPL0 = 295 + + MPL1 = 296 + + MPL2 = 297 + + MSA8 = 298 + + MSA9 = 299 + + MSA10 = 300 + + MSA11 = 301 + + MSA12 = 302 + + MSA13 = 303 + + MSA14 = 304 + + MSA15 = 305 + + MSA16 = 306 + + MSA17 = 307 + + MSA18 = 308 + + MSA19 = 309 + + MSA20 = 310 + + MSA21 = 311 + + MSA22 = 312 + + MSA23 = 313 + + MSA24 = 314 + + MSA25 = 315 + + MSA26 = 316 + + MSA27 = 317 + + MSA28 = 318 + + MSA29 = 319 + + MSA30 = 320 + + MSA31 = 321 + + P0 = 322 + + P1 = 323 + + P2 = 324 + + RA_64 = 325 + + S0 = 326 + + S1 = 327 + + S2 = 328 + + S3 = 329 + + S4 = 330 + + S5 = 331 + + S6 = 332 + + S7 = 333 + + SP_64 = 334 + + T0 = 335 + + T1 = 336 + + T2 = 337 + + T3 = 338 + + T4 = 339 + + T5 = 340 + + T6 = 341 + + T7 = 342 + + T8 = 343 + + T9 = 344 + + V0 = 345 + + V1 = 346 + + W0 = 347 + + W1 = 348 + + W2 = 349 + + W3 = 350 + + W4 = 351 + + W5 = 352 + + W6 = 353 + + W7 = 354 + + W8 = 355 + + W9 = 356 + + W10 = 357 + + W11 = 358 + + W12 = 359 + + W13 = 360 + + W14 = 361 + + W15 = 362 + + W16 = 363 + + W17 = 364 + + W18 = 365 + + W19 = 366 + + W20 = 367 + + W21 = 368 + + W22 = 369 + + W23 = 370 + + W24 = 371 + + W25 = 372 + + W26 = 373 + + W27 = 374 + + W28 = 375 + + W29 = 376 + + W30 = 377 + + W31 = 378 + + ZERO_64 = 379 + + A0_64 = 380 + + A1_64 = 381 + + A2_64 = 382 + + A3_64 = 383 + + AC0_64 = 384 + + D0_64 = 385 + + D1_64 = 386 + + D2_64 = 387 + + D3_64 = 388 + + D4_64 = 389 + + D5_64 = 390 + + D6_64 = 391 + + D7_64 = 392 + + D8_64 = 393 + + D9_64 = 394 + + D10_64 = 395 + + D11_64 = 396 + + D12_64 = 397 + + D13_64 = 398 + + D14_64 = 399 + + D15_64 = 400 + + D16_64 = 401 + + D17_64 = 402 + + D18_64 = 403 + + D19_64 = 404 + + D20_64 = 405 + + D21_64 = 406 + + D22_64 = 407 + + D23_64 = 408 + + D24_64 = 409 + + D25_64 = 410 + + D26_64 = 411 + + D27_64 = 412 + + D28_64 = 413 + + D29_64 = 414 + + D30_64 = 415 + + D31_64 = 416 + + DSPOutFlag16_19 = 417 + + HI0_64 = 418 + + K0_64 = 419 + + K1_64 = 420 + + LO0_64 = 421 + + S0_64 = 422 + + S1_64 = 423 + + S2_64 = 424 + + S3_64 = 425 + + S4_64 = 426 + + S5_64 = 427 + + S6_64 = 428 + + S7_64 = 429 + + T0_64 = 430 + + T1_64 = 431 + + T2_64 = 432 + + T3_64 = 433 + + T4_64 = 434 + + T5_64 = 435 + + T6_64 = 436 + + T7_64 = 437 + + T8_64 = 438 + + T9_64 = 439 + + V0_64 = 440 + + V1_64 = 441 + + NUM_TARGET_REGS = 442 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/mips/operands.pyi b/vendor/lief/api/python/lief/assembly/mips/operands.pyi new file mode 100644 index 0000000..8762fc3 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/mips/operands.pyi @@ -0,0 +1,33 @@ +from typing import Optional, Union + +import lief.assembly.mips + +import lief.assembly.mips + + +class Immediate(lief.assembly.mips.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.mips.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> lief.assembly.mips.REG: ... + +class Memory(lief.assembly.mips.Operand): + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.mips.REG: ... + + @property + def offset(self) -> Optional[Union[lief.assembly.mips.REG, int]]: ... + +class PCRelative(lief.assembly.mips.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/assembly/powerpc/__init__.pyi b/vendor/lief/api/python/lief/assembly/powerpc/__init__.pyi new file mode 100644 index 0000000..ce18a7d --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/powerpc/__init__.pyi @@ -0,0 +1,7244 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.powerpc import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ATOMIC_CMP_SWAP_I128 = 322 + + ATOMIC_LOAD_ADD_I128 = 323 + + ATOMIC_LOAD_AND_I128 = 324 + + ATOMIC_LOAD_NAND_I128 = 325 + + ATOMIC_LOAD_OR_I128 = 326 + + ATOMIC_LOAD_SUB_I128 = 327 + + ATOMIC_LOAD_XOR_I128 = 328 + + ATOMIC_SWAP_I128 = 329 + + BUILD_QUADWORD = 330 + + BUILD_UACC = 331 + + CFENCE = 332 + + CFENCE8 = 333 + + CLRLSLDI = 334 + + CLRLSLDI_rec = 335 + + CLRLSLWI = 336 + + CLRLSLWI_rec = 337 + + CLRRDI = 338 + + CLRRDI_rec = 339 + + CLRRWI = 340 + + CLRRWI_rec = 341 + + DCBFL = 342 + + DCBFLP = 343 + + DCBFPS = 344 + + DCBFx = 345 + + DCBSTPS = 346 + + DCBTCT = 347 + + DCBTDS = 348 + + DCBTSTCT = 349 + + DCBTSTDS = 350 + + DCBTSTT = 351 + + DCBTSTx = 352 + + DCBTT = 353 + + DCBTx = 354 + + DFLOADf32 = 355 + + DFLOADf64 = 356 + + DFSTOREf32 = 357 + + DFSTOREf64 = 358 + + EXTLDI = 359 + + EXTLDI_rec = 360 + + EXTLWI = 361 + + EXTLWI_rec = 362 + + EXTRDI = 363 + + EXTRDI_rec = 364 + + EXTRWI = 365 + + EXTRWI_rec = 366 + + INSLWI = 367 + + INSLWI_rec = 368 + + INSRDI = 369 + + INSRDI_rec = 370 + + INSRWI = 371 + + INSRWI_rec = 372 + + KILL_PAIR = 373 + + LAx = 374 + + LIWAX = 375 + + LIWZX = 376 + + PPCLdFixedAddr = 377 + + PSUBI = 378 + + RLWIMIbm = 379 + + RLWIMIbm_rec = 380 + + RLWINMbm = 381 + + RLWINMbm_rec = 382 + + RLWNMbm = 383 + + RLWNMbm_rec = 384 + + ROTRDI = 385 + + ROTRDI_rec = 386 + + ROTRWI = 387 + + ROTRWI_rec = 388 + + SLDI = 389 + + SLDI_rec = 390 + + SLWI = 391 + + SLWI_rec = 392 + + SPILLTOVSR_LD = 393 + + SPILLTOVSR_LDX = 394 + + SPILLTOVSR_ST = 395 + + SPILLTOVSR_STX = 396 + + SRDI = 397 + + SRDI_rec = 398 + + SRWI = 399 + + SRWI_rec = 400 + + STIWX = 401 + + SUBI = 402 + + SUBIC = 403 + + SUBIC_rec = 404 + + SUBIS = 405 + + SUBPCIS = 406 + + XFLOADf32 = 407 + + XFLOADf64 = 408 + + XFSTOREf32 = 409 + + XFSTOREf64 = 410 + + ADD4 = 411 + + ADD4O = 412 + + ADD4O_rec = 413 + + ADD4TLS = 414 + + ADD4_rec = 415 + + ADD8 = 416 + + ADD8O = 417 + + ADD8O_rec = 418 + + ADD8TLS = 419 + + ADD8TLS_ = 420 + + ADD8_rec = 421 + + ADDC = 422 + + ADDC8 = 423 + + ADDC8O = 424 + + ADDC8O_rec = 425 + + ADDC8_rec = 426 + + ADDCO = 427 + + ADDCO_rec = 428 + + ADDC_rec = 429 + + ADDE = 430 + + ADDE8 = 431 + + ADDE8O = 432 + + ADDE8O_rec = 433 + + ADDE8_rec = 434 + + ADDEO = 435 + + ADDEO_rec = 436 + + ADDEX = 437 + + ADDEX8 = 438 + + ADDE_rec = 439 + + ADDG6S = 440 + + ADDG6S8 = 441 + + ADDI = 442 + + ADDI8 = 443 + + ADDIC = 444 + + ADDIC8 = 445 + + ADDIC_rec = 446 + + ADDIS = 447 + + ADDIS8 = 448 + + ADDISdtprelHA = 449 + + ADDISdtprelHA32 = 450 + + ADDISgotTprelHA = 451 + + ADDIStlsgdHA = 452 + + ADDIStlsldHA = 453 + + ADDIStocHA = 454 + + ADDIStocHA8 = 455 + + ADDIdtprelL = 456 + + ADDIdtprelL32 = 457 + + ADDItlsgdL = 458 + + ADDItlsgdL32 = 459 + + ADDItlsgdLADDR = 460 + + ADDItlsgdLADDR32 = 461 + + ADDItlsldL = 462 + + ADDItlsldL32 = 463 + + ADDItlsldLADDR = 464 + + ADDItlsldLADDR32 = 465 + + ADDItoc = 466 + + ADDItoc8 = 467 + + ADDItocL = 468 + + ADDItocL8 = 469 + + ADDME = 470 + + ADDME8 = 471 + + ADDME8O = 472 + + ADDME8O_rec = 473 + + ADDME8_rec = 474 + + ADDMEO = 475 + + ADDMEO_rec = 476 + + ADDME_rec = 477 + + ADDPCIS = 478 + + ADDZE = 479 + + ADDZE8 = 480 + + ADDZE8O = 481 + + ADDZE8O_rec = 482 + + ADDZE8_rec = 483 + + ADDZEO = 484 + + ADDZEO_rec = 485 + + ADDZE_rec = 486 + + ADJCALLSTACKDOWN = 487 + + ADJCALLSTACKUP = 488 + + AND = 489 + + AND8 = 490 + + AND8_rec = 491 + + ANDC = 492 + + ANDC8 = 493 + + ANDC8_rec = 494 + + ANDC_rec = 495 + + ANDI8_rec = 496 + + ANDIS8_rec = 497 + + ANDIS_rec = 498 + + ANDI_rec = 499 + + ANDI_rec_1_EQ_BIT = 500 + + ANDI_rec_1_EQ_BIT8 = 501 + + ANDI_rec_1_GT_BIT = 502 + + ANDI_rec_1_GT_BIT8 = 503 + + AND_rec = 504 + + ATOMIC_CMP_SWAP_I16 = 505 + + ATOMIC_CMP_SWAP_I32 = 506 + + ATOMIC_CMP_SWAP_I64 = 507 + + ATOMIC_CMP_SWAP_I8 = 508 + + ATOMIC_LOAD_ADD_I16 = 509 + + ATOMIC_LOAD_ADD_I32 = 510 + + ATOMIC_LOAD_ADD_I64 = 511 + + ATOMIC_LOAD_ADD_I8 = 512 + + ATOMIC_LOAD_AND_I16 = 513 + + ATOMIC_LOAD_AND_I32 = 514 + + ATOMIC_LOAD_AND_I64 = 515 + + ATOMIC_LOAD_AND_I8 = 516 + + ATOMIC_LOAD_MAX_I16 = 517 + + ATOMIC_LOAD_MAX_I32 = 518 + + ATOMIC_LOAD_MAX_I64 = 519 + + ATOMIC_LOAD_MAX_I8 = 520 + + ATOMIC_LOAD_MIN_I16 = 521 + + ATOMIC_LOAD_MIN_I32 = 522 + + ATOMIC_LOAD_MIN_I64 = 523 + + ATOMIC_LOAD_MIN_I8 = 524 + + ATOMIC_LOAD_NAND_I16 = 525 + + ATOMIC_LOAD_NAND_I32 = 526 + + ATOMIC_LOAD_NAND_I64 = 527 + + ATOMIC_LOAD_NAND_I8 = 528 + + ATOMIC_LOAD_OR_I16 = 529 + + ATOMIC_LOAD_OR_I32 = 530 + + ATOMIC_LOAD_OR_I64 = 531 + + ATOMIC_LOAD_OR_I8 = 532 + + ATOMIC_LOAD_SUB_I16 = 533 + + ATOMIC_LOAD_SUB_I32 = 534 + + ATOMIC_LOAD_SUB_I64 = 535 + + ATOMIC_LOAD_SUB_I8 = 536 + + ATOMIC_LOAD_UMAX_I16 = 537 + + ATOMIC_LOAD_UMAX_I32 = 538 + + ATOMIC_LOAD_UMAX_I64 = 539 + + ATOMIC_LOAD_UMAX_I8 = 540 + + ATOMIC_LOAD_UMIN_I16 = 541 + + ATOMIC_LOAD_UMIN_I32 = 542 + + ATOMIC_LOAD_UMIN_I64 = 543 + + ATOMIC_LOAD_UMIN_I8 = 544 + + ATOMIC_LOAD_XOR_I16 = 545 + + ATOMIC_LOAD_XOR_I32 = 546 + + ATOMIC_LOAD_XOR_I64 = 547 + + ATOMIC_LOAD_XOR_I8 = 548 + + ATOMIC_SWAP_I16 = 549 + + ATOMIC_SWAP_I32 = 550 + + ATOMIC_SWAP_I64 = 551 + + ATOMIC_SWAP_I8 = 552 + + ATTN = 553 + + B = 554 + + BA = 555 + + BC = 556 + + BCC = 557 + + BCCA = 558 + + BCCCTR = 559 + + BCCCTR8 = 560 + + BCCCTRL = 561 + + BCCCTRL8 = 562 + + BCCL = 563 + + BCCLA = 564 + + BCCLR = 565 + + BCCLRL = 566 + + BCCTR = 567 + + BCCTR8 = 568 + + BCCTR8n = 569 + + BCCTRL = 570 + + BCCTRL8 = 571 + + BCCTRL8n = 572 + + BCCTRLn = 573 + + BCCTRn = 574 + + BCDADD_rec = 575 + + BCDCFN_rec = 576 + + BCDCFSQ_rec = 577 + + BCDCFZ_rec = 578 + + BCDCPSGN_rec = 579 + + BCDCTN_rec = 580 + + BCDCTSQ_rec = 581 + + BCDCTZ_rec = 582 + + BCDSETSGN_rec = 583 + + BCDSR_rec = 584 + + BCDSUB_rec = 585 + + BCDS_rec = 586 + + BCDTRUNC_rec = 587 + + BCDUS_rec = 588 + + BCDUTRUNC_rec = 589 + + BCL = 590 + + BCLR = 591 + + BCLRL = 592 + + BCLRLn = 593 + + BCLRn = 594 + + BCLalways = 595 + + BCLn = 596 + + BCTR = 597 + + BCTR8 = 598 + + BCTRL = 599 + + BCTRL8 = 600 + + BCTRL8_LDinto_toc = 601 + + BCTRL8_LDinto_toc_RM = 602 + + BCTRL8_RM = 603 + + BCTRL_LWZinto_toc = 604 + + BCTRL_LWZinto_toc_RM = 605 + + BCTRL_RM = 606 + + BCn = 607 + + BDNZ = 608 + + BDNZ8 = 609 + + BDNZA = 610 + + BDNZAm = 611 + + BDNZAp = 612 + + BDNZL = 613 + + BDNZLA = 614 + + BDNZLAm = 615 + + BDNZLAp = 616 + + BDNZLR = 617 + + BDNZLR8 = 618 + + BDNZLRL = 619 + + BDNZLRLm = 620 + + BDNZLRLp = 621 + + BDNZLRm = 622 + + BDNZLRp = 623 + + BDNZLm = 624 + + BDNZLp = 625 + + BDNZm = 626 + + BDNZp = 627 + + BDZ = 628 + + BDZ8 = 629 + + BDZA = 630 + + BDZAm = 631 + + BDZAp = 632 + + BDZL = 633 + + BDZLA = 634 + + BDZLAm = 635 + + BDZLAp = 636 + + BDZLR = 637 + + BDZLR8 = 638 + + BDZLRL = 639 + + BDZLRLm = 640 + + BDZLRLp = 641 + + BDZLRm = 642 + + BDZLRp = 643 + + BDZLm = 644 + + BDZLp = 645 + + BDZm = 646 + + BDZp = 647 + + BL = 648 + + BL8 = 649 + + BL8_NOP = 650 + + BL8_NOP_RM = 651 + + BL8_NOP_TLS = 652 + + BL8_NOTOC = 653 + + BL8_NOTOC_RM = 654 + + BL8_NOTOC_TLS = 655 + + BL8_RM = 656 + + BL8_TLS = 657 + + BL8_TLS_ = 658 + + BLA = 659 + + BLA8 = 660 + + BLA8_NOP = 661 + + BLA8_NOP_RM = 662 + + BLA8_RM = 663 + + BLA_RM = 664 + + BLR = 665 + + BLR8 = 666 + + BLRL = 667 + + BL_NOP = 668 + + BL_NOP_RM = 669 + + BL_RM = 670 + + BL_TLS = 671 + + BPERMD = 672 + + BRD = 673 + + BRH = 674 + + BRH8 = 675 + + BRINC = 676 + + BRW = 677 + + BRW8 = 678 + + CBCDTD = 679 + + CBCDTD8 = 680 + + CDTBCD = 681 + + CDTBCD8 = 682 + + CFUGED = 683 + + CLRBHRB = 684 + + CMPB = 685 + + CMPB8 = 686 + + CMPD = 687 + + CMPDI = 688 + + CMPEQB = 689 + + CMPLD = 690 + + CMPLDI = 691 + + CMPLW = 692 + + CMPLWI = 693 + + CMPRB = 694 + + CMPRB8 = 695 + + CMPW = 696 + + CMPWI = 697 + + CNTLZD = 698 + + CNTLZDM = 699 + + CNTLZD_rec = 700 + + CNTLZW = 701 + + CNTLZW8 = 702 + + CNTLZW8_rec = 703 + + CNTLZW_rec = 704 + + CNTTZD = 705 + + CNTTZDM = 706 + + CNTTZD_rec = 707 + + CNTTZW = 708 + + CNTTZW8 = 709 + + CNTTZW8_rec = 710 + + CNTTZW_rec = 711 + + CP_ABORT = 712 + + CP_COPY = 713 + + CP_COPY8 = 714 + + CP_PASTE8_rec = 715 + + CP_PASTE_rec = 716 + + CR6SET = 717 + + CR6UNSET = 718 + + CRAND = 719 + + CRANDC = 720 + + CREQV = 721 + + CRNAND = 722 + + CRNOR = 723 + + CRNOT = 724 + + CROR = 725 + + CRORC = 726 + + CRSET = 727 + + CRUNSET = 728 + + CRXOR = 729 + + CTRL_DEP = 730 + + DADD = 731 + + DADDQ = 732 + + DADDQ_rec = 733 + + DADD_rec = 734 + + DARN = 735 + + DCBA = 736 + + DCBF = 737 + + DCBFEP = 738 + + DCBI = 739 + + DCBST = 740 + + DCBSTEP = 741 + + DCBT = 742 + + DCBTEP = 743 + + DCBTST = 744 + + DCBTSTEP = 745 + + DCBZ = 746 + + DCBZEP = 747 + + DCBZL = 748 + + DCBZLEP = 749 + + DCCCI = 750 + + DCFFIX = 751 + + DCFFIXQ = 752 + + DCFFIXQQ = 753 + + DCFFIXQ_rec = 754 + + DCFFIX_rec = 755 + + DCMPO = 756 + + DCMPOQ = 757 + + DCMPU = 758 + + DCMPUQ = 759 + + DCTDP = 760 + + DCTDP_rec = 761 + + DCTFIX = 762 + + DCTFIXQ = 763 + + DCTFIXQQ = 764 + + DCTFIXQ_rec = 765 + + DCTFIX_rec = 766 + + DCTQPQ = 767 + + DCTQPQ_rec = 768 + + DDEDPD = 769 + + DDEDPDQ = 770 + + DDEDPDQ_rec = 771 + + DDEDPD_rec = 772 + + DDIV = 773 + + DDIVQ = 774 + + DDIVQ_rec = 775 + + DDIV_rec = 776 + + DENBCD = 777 + + DENBCDQ = 778 + + DENBCDQ_rec = 779 + + DENBCD_rec = 780 + + DIEX = 781 + + DIEXQ = 782 + + DIEXQ_rec = 783 + + DIEX_rec = 784 + + DIVD = 785 + + DIVDE = 786 + + DIVDEO = 787 + + DIVDEO_rec = 788 + + DIVDEU = 789 + + DIVDEUO = 790 + + DIVDEUO_rec = 791 + + DIVDEU_rec = 792 + + DIVDE_rec = 793 + + DIVDO = 794 + + DIVDO_rec = 795 + + DIVDU = 796 + + DIVDUO = 797 + + DIVDUO_rec = 798 + + DIVDU_rec = 799 + + DIVD_rec = 800 + + DIVW = 801 + + DIVWE = 802 + + DIVWEO = 803 + + DIVWEO_rec = 804 + + DIVWEU = 805 + + DIVWEUO = 806 + + DIVWEUO_rec = 807 + + DIVWEU_rec = 808 + + DIVWE_rec = 809 + + DIVWO = 810 + + DIVWO_rec = 811 + + DIVWU = 812 + + DIVWUO = 813 + + DIVWUO_rec = 814 + + DIVWU_rec = 815 + + DIVW_rec = 816 + + DMMR = 817 + + DMSETDMRZ = 818 + + DMSHA2HASH = 819 + + DMSHA3HASH = 820 + + DMUL = 821 + + DMULQ = 822 + + DMULQ_rec = 823 + + DMUL_rec = 824 + + DMXOR = 825 + + DMXVBF16GERX2 = 826 + + DMXVBF16GERX2NN = 827 + + DMXVBF16GERX2NP = 828 + + DMXVBF16GERX2PN = 829 + + DMXVBF16GERX2PP = 830 + + DMXVF16GERX2 = 831 + + DMXVF16GERX2NN = 832 + + DMXVF16GERX2NP = 833 + + DMXVF16GERX2PN = 834 + + DMXVF16GERX2PP = 835 + + DMXVI8GERX4 = 836 + + DMXVI8GERX4PP = 837 + + DMXVI8GERX4SPP = 838 + + DMXXEXTFDMR256 = 839 + + DMXXEXTFDMR512 = 840 + + DMXXEXTFDMR512_HI = 841 + + DMXXINSTDMR256 = 842 + + DMXXINSTDMR512 = 843 + + DMXXINSTDMR512_HI = 844 + + DMXXSETACCZ = 845 + + DMXXSHAPAD = 846 + + DQUA = 847 + + DQUAI = 848 + + DQUAIQ = 849 + + DQUAIQ_rec = 850 + + DQUAI_rec = 851 + + DQUAQ = 852 + + DQUAQ_rec = 853 + + DQUA_rec = 854 + + DRDPQ = 855 + + DRDPQ_rec = 856 + + DRINTN = 857 + + DRINTNQ = 858 + + DRINTNQ_rec = 859 + + DRINTN_rec = 860 + + DRINTX = 861 + + DRINTXQ = 862 + + DRINTXQ_rec = 863 + + DRINTX_rec = 864 + + DRRND = 865 + + DRRNDQ = 866 + + DRRNDQ_rec = 867 + + DRRND_rec = 868 + + DRSP = 869 + + DRSP_rec = 870 + + DSCLI = 871 + + DSCLIQ = 872 + + DSCLIQ_rec = 873 + + DSCLI_rec = 874 + + DSCRI = 875 + + DSCRIQ = 876 + + DSCRIQ_rec = 877 + + DSCRI_rec = 878 + + DSS = 879 + + DSSALL = 880 + + DST = 881 + + DST64 = 882 + + DSTST = 883 + + DSTST64 = 884 + + DSTSTT = 885 + + DSTSTT64 = 886 + + DSTT = 887 + + DSTT64 = 888 + + DSUB = 889 + + DSUBQ = 890 + + DSUBQ_rec = 891 + + DSUB_rec = 892 + + DTSTDC = 893 + + DTSTDCQ = 894 + + DTSTDG = 895 + + DTSTDGQ = 896 + + DTSTEX = 897 + + DTSTEXQ = 898 + + DTSTSF = 899 + + DTSTSFI = 900 + + DTSTSFIQ = 901 + + DTSTSFQ = 902 + + DXEX = 903 + + DXEXQ = 904 + + DXEXQ_rec = 905 + + DXEX_rec = 906 + + DYNALLOC = 907 + + DYNALLOC8 = 908 + + DYNAREAOFFSET = 909 + + DYNAREAOFFSET8 = 910 + + DecreaseCTR8loop = 911 + + DecreaseCTRloop = 912 + + EFDABS = 913 + + EFDADD = 914 + + EFDCFS = 915 + + EFDCFSF = 916 + + EFDCFSI = 917 + + EFDCFSID = 918 + + EFDCFUF = 919 + + EFDCFUI = 920 + + EFDCFUID = 921 + + EFDCMPEQ = 922 + + EFDCMPGT = 923 + + EFDCMPLT = 924 + + EFDCTSF = 925 + + EFDCTSI = 926 + + EFDCTSIDZ = 927 + + EFDCTSIZ = 928 + + EFDCTUF = 929 + + EFDCTUI = 930 + + EFDCTUIDZ = 931 + + EFDCTUIZ = 932 + + EFDDIV = 933 + + EFDMUL = 934 + + EFDNABS = 935 + + EFDNEG = 936 + + EFDSUB = 937 + + EFDTSTEQ = 938 + + EFDTSTGT = 939 + + EFDTSTLT = 940 + + EFSABS = 941 + + EFSADD = 942 + + EFSCFD = 943 + + EFSCFSF = 944 + + EFSCFSI = 945 + + EFSCFUF = 946 + + EFSCFUI = 947 + + EFSCMPEQ = 948 + + EFSCMPGT = 949 + + EFSCMPLT = 950 + + EFSCTSF = 951 + + EFSCTSI = 952 + + EFSCTSIZ = 953 + + EFSCTUF = 954 + + EFSCTUI = 955 + + EFSCTUIZ = 956 + + EFSDIV = 957 + + EFSMUL = 958 + + EFSNABS = 959 + + EFSNEG = 960 + + EFSSUB = 961 + + EFSTSTEQ = 962 + + EFSTSTGT = 963 + + EFSTSTLT = 964 + + EH_SjLj_LongJmp32 = 965 + + EH_SjLj_LongJmp64 = 966 + + EH_SjLj_SetJmp32 = 967 + + EH_SjLj_SetJmp64 = 968 + + EH_SjLj_Setup = 969 + + EQV = 970 + + EQV8 = 971 + + EQV8_rec = 972 + + EQV_rec = 973 + + EVABS = 974 + + EVADDIW = 975 + + EVADDSMIAAW = 976 + + EVADDSSIAAW = 977 + + EVADDUMIAAW = 978 + + EVADDUSIAAW = 979 + + EVADDW = 980 + + EVAND = 981 + + EVANDC = 982 + + EVCMPEQ = 983 + + EVCMPGTS = 984 + + EVCMPGTU = 985 + + EVCMPLTS = 986 + + EVCMPLTU = 987 + + EVCNTLSW = 988 + + EVCNTLZW = 989 + + EVDIVWS = 990 + + EVDIVWU = 991 + + EVEQV = 992 + + EVEXTSB = 993 + + EVEXTSH = 994 + + EVFSABS = 995 + + EVFSADD = 996 + + EVFSCFSF = 997 + + EVFSCFSI = 998 + + EVFSCFUF = 999 + + EVFSCFUI = 1000 + + EVFSCMPEQ = 1001 + + EVFSCMPGT = 1002 + + EVFSCMPLT = 1003 + + EVFSCTSF = 1004 + + EVFSCTSI = 1005 + + EVFSCTSIZ = 1006 + + EVFSCTUF = 1007 + + EVFSCTUI = 1008 + + EVFSCTUIZ = 1009 + + EVFSDIV = 1010 + + EVFSMUL = 1011 + + EVFSNABS = 1012 + + EVFSNEG = 1013 + + EVFSSUB = 1014 + + EVFSTSTEQ = 1015 + + EVFSTSTGT = 1016 + + EVFSTSTLT = 1017 + + EVLDD = 1018 + + EVLDDX = 1019 + + EVLDH = 1020 + + EVLDHX = 1021 + + EVLDW = 1022 + + EVLDWX = 1023 + + EVLHHESPLAT = 1024 + + EVLHHESPLATX = 1025 + + EVLHHOSSPLAT = 1026 + + EVLHHOSSPLATX = 1027 + + EVLHHOUSPLAT = 1028 + + EVLHHOUSPLATX = 1029 + + EVLWHE = 1030 + + EVLWHEX = 1031 + + EVLWHOS = 1032 + + EVLWHOSX = 1033 + + EVLWHOU = 1034 + + EVLWHOUX = 1035 + + EVLWHSPLAT = 1036 + + EVLWHSPLATX = 1037 + + EVLWWSPLAT = 1038 + + EVLWWSPLATX = 1039 + + EVMERGEHI = 1040 + + EVMERGEHILO = 1041 + + EVMERGELO = 1042 + + EVMERGELOHI = 1043 + + EVMHEGSMFAA = 1044 + + EVMHEGSMFAN = 1045 + + EVMHEGSMIAA = 1046 + + EVMHEGSMIAN = 1047 + + EVMHEGUMIAA = 1048 + + EVMHEGUMIAN = 1049 + + EVMHESMF = 1050 + + EVMHESMFA = 1051 + + EVMHESMFAAW = 1052 + + EVMHESMFANW = 1053 + + EVMHESMI = 1054 + + EVMHESMIA = 1055 + + EVMHESMIAAW = 1056 + + EVMHESMIANW = 1057 + + EVMHESSF = 1058 + + EVMHESSFA = 1059 + + EVMHESSFAAW = 1060 + + EVMHESSFANW = 1061 + + EVMHESSIAAW = 1062 + + EVMHESSIANW = 1063 + + EVMHEUMI = 1064 + + EVMHEUMIA = 1065 + + EVMHEUMIAAW = 1066 + + EVMHEUMIANW = 1067 + + EVMHEUSIAAW = 1068 + + EVMHEUSIANW = 1069 + + EVMHOGSMFAA = 1070 + + EVMHOGSMFAN = 1071 + + EVMHOGSMIAA = 1072 + + EVMHOGSMIAN = 1073 + + EVMHOGUMIAA = 1074 + + EVMHOGUMIAN = 1075 + + EVMHOSMF = 1076 + + EVMHOSMFA = 1077 + + EVMHOSMFAAW = 1078 + + EVMHOSMFANW = 1079 + + EVMHOSMI = 1080 + + EVMHOSMIA = 1081 + + EVMHOSMIAAW = 1082 + + EVMHOSMIANW = 1083 + + EVMHOSSF = 1084 + + EVMHOSSFA = 1085 + + EVMHOSSFAAW = 1086 + + EVMHOSSFANW = 1087 + + EVMHOSSIAAW = 1088 + + EVMHOSSIANW = 1089 + + EVMHOUMI = 1090 + + EVMHOUMIA = 1091 + + EVMHOUMIAAW = 1092 + + EVMHOUMIANW = 1093 + + EVMHOUSIAAW = 1094 + + EVMHOUSIANW = 1095 + + EVMRA = 1096 + + EVMWHSMF = 1097 + + EVMWHSMFA = 1098 + + EVMWHSMI = 1099 + + EVMWHSMIA = 1100 + + EVMWHSSF = 1101 + + EVMWHSSFA = 1102 + + EVMWHUMI = 1103 + + EVMWHUMIA = 1104 + + EVMWLSMIAAW = 1105 + + EVMWLSMIANW = 1106 + + EVMWLSSIAAW = 1107 + + EVMWLSSIANW = 1108 + + EVMWLUMI = 1109 + + EVMWLUMIA = 1110 + + EVMWLUMIAAW = 1111 + + EVMWLUMIANW = 1112 + + EVMWLUSIAAW = 1113 + + EVMWLUSIANW = 1114 + + EVMWSMF = 1115 + + EVMWSMFA = 1116 + + EVMWSMFAA = 1117 + + EVMWSMFAN = 1118 + + EVMWSMI = 1119 + + EVMWSMIA = 1120 + + EVMWSMIAA = 1121 + + EVMWSMIAN = 1122 + + EVMWSSF = 1123 + + EVMWSSFA = 1124 + + EVMWSSFAA = 1125 + + EVMWSSFAN = 1126 + + EVMWUMI = 1127 + + EVMWUMIA = 1128 + + EVMWUMIAA = 1129 + + EVMWUMIAN = 1130 + + EVNAND = 1131 + + EVNEG = 1132 + + EVNOR = 1133 + + EVOR = 1134 + + EVORC = 1135 + + EVRLW = 1136 + + EVRLWI = 1137 + + EVRNDW = 1138 + + EVSEL = 1139 + + EVSLW = 1140 + + EVSLWI = 1141 + + EVSPLATFI = 1142 + + EVSPLATI = 1143 + + EVSRWIS = 1144 + + EVSRWIU = 1145 + + EVSRWS = 1146 + + EVSRWU = 1147 + + EVSTDD = 1148 + + EVSTDDX = 1149 + + EVSTDH = 1150 + + EVSTDHX = 1151 + + EVSTDW = 1152 + + EVSTDWX = 1153 + + EVSTWHE = 1154 + + EVSTWHEX = 1155 + + EVSTWHO = 1156 + + EVSTWHOX = 1157 + + EVSTWWE = 1158 + + EVSTWWEX = 1159 + + EVSTWWO = 1160 + + EVSTWWOX = 1161 + + EVSUBFSMIAAW = 1162 + + EVSUBFSSIAAW = 1163 + + EVSUBFUMIAAW = 1164 + + EVSUBFUSIAAW = 1165 + + EVSUBFW = 1166 + + EVSUBIFW = 1167 + + EVXOR = 1168 + + EXTSB = 1169 + + EXTSB8 = 1170 + + EXTSB8_32_64 = 1171 + + EXTSB8_rec = 1172 + + EXTSB_rec = 1173 + + EXTSH = 1174 + + EXTSH8 = 1175 + + EXTSH8_32_64 = 1176 + + EXTSH8_rec = 1177 + + EXTSH_rec = 1178 + + EXTSW = 1179 + + EXTSWSLI = 1180 + + EXTSWSLI_32_64 = 1181 + + EXTSWSLI_32_64_rec = 1182 + + EXTSWSLI_rec = 1183 + + EXTSW_32 = 1184 + + EXTSW_32_64 = 1185 + + EXTSW_32_64_rec = 1186 + + EXTSW_rec = 1187 + + EnforceIEIO = 1188 + + FABSD = 1189 + + FABSD_rec = 1190 + + FABSS = 1191 + + FABSS_rec = 1192 + + FADD = 1193 + + FADDS = 1194 + + FADDS_rec = 1195 + + FADD_rec = 1196 + + FADDrtz = 1197 + + FCFID = 1198 + + FCFIDS = 1199 + + FCFIDS_rec = 1200 + + FCFIDU = 1201 + + FCFIDUS = 1202 + + FCFIDUS_rec = 1203 + + FCFIDU_rec = 1204 + + FCFID_rec = 1205 + + FCMPOD = 1206 + + FCMPOS = 1207 + + FCMPUD = 1208 + + FCMPUS = 1209 + + FCPSGND = 1210 + + FCPSGND_rec = 1211 + + FCPSGNS = 1212 + + FCPSGNS_rec = 1213 + + FCTID = 1214 + + FCTIDU = 1215 + + FCTIDUZ = 1216 + + FCTIDUZ_rec = 1217 + + FCTIDU_rec = 1218 + + FCTIDZ = 1219 + + FCTIDZ_rec = 1220 + + FCTID_rec = 1221 + + FCTIW = 1222 + + FCTIWU = 1223 + + FCTIWUZ = 1224 + + FCTIWUZ_rec = 1225 + + FCTIWU_rec = 1226 + + FCTIWZ = 1227 + + FCTIWZ_rec = 1228 + + FCTIW_rec = 1229 + + FDIV = 1230 + + FDIVS = 1231 + + FDIVS_rec = 1232 + + FDIV_rec = 1233 + + FENCE = 1234 + + FMADD = 1235 + + FMADDS = 1236 + + FMADDS_rec = 1237 + + FMADD_rec = 1238 + + FMR = 1239 + + FMR_rec = 1240 + + FMSUB = 1241 + + FMSUBS = 1242 + + FMSUBS_rec = 1243 + + FMSUB_rec = 1244 + + FMUL = 1245 + + FMULS = 1246 + + FMULS_rec = 1247 + + FMUL_rec = 1248 + + FNABSD = 1249 + + FNABSD_rec = 1250 + + FNABSS = 1251 + + FNABSS_rec = 1252 + + FNEGD = 1253 + + FNEGD_rec = 1254 + + FNEGS = 1255 + + FNEGS_rec = 1256 + + FNMADD = 1257 + + FNMADDS = 1258 + + FNMADDS_rec = 1259 + + FNMADD_rec = 1260 + + FNMSUB = 1261 + + FNMSUBS = 1262 + + FNMSUBS_rec = 1263 + + FNMSUB_rec = 1264 + + FRE = 1265 + + FRES = 1266 + + FRES_rec = 1267 + + FRE_rec = 1268 + + FRIMD = 1269 + + FRIMD_rec = 1270 + + FRIMS = 1271 + + FRIMS_rec = 1272 + + FRIND = 1273 + + FRIND_rec = 1274 + + FRINS = 1275 + + FRINS_rec = 1276 + + FRIPD = 1277 + + FRIPD_rec = 1278 + + FRIPS = 1279 + + FRIPS_rec = 1280 + + FRIZD = 1281 + + FRIZD_rec = 1282 + + FRIZS = 1283 + + FRIZS_rec = 1284 + + FRSP = 1285 + + FRSP_rec = 1286 + + FRSQRTE = 1287 + + FRSQRTES = 1288 + + FRSQRTES_rec = 1289 + + FRSQRTE_rec = 1290 + + FSELD = 1291 + + FSELD_rec = 1292 + + FSELS = 1293 + + FSELS_rec = 1294 + + FSQRT = 1295 + + FSQRTS = 1296 + + FSQRTS_rec = 1297 + + FSQRT_rec = 1298 + + FSUB = 1299 + + FSUBS = 1300 + + FSUBS_rec = 1301 + + FSUB_rec = 1302 + + FTDIV = 1303 + + FTSQRT = 1304 + + GETtlsADDR = 1305 + + GETtlsADDR32 = 1306 + + GETtlsADDR32AIX = 1307 + + GETtlsADDR64AIX = 1308 + + GETtlsADDRPCREL = 1309 + + GETtlsMOD32AIX = 1310 + + GETtlsMOD64AIX = 1311 + + GETtlsTpointer32AIX = 1312 + + GETtlsldADDR = 1313 + + GETtlsldADDR32 = 1314 + + GETtlsldADDRPCREL = 1315 + + HASHCHK = 1316 + + HASHCHK8 = 1317 + + HASHCHKP = 1318 + + HASHCHKP8 = 1319 + + HASHST = 1320 + + HASHST8 = 1321 + + HASHSTP = 1322 + + HASHSTP8 = 1323 + + HRFID = 1324 + + ICBI = 1325 + + ICBIEP = 1326 + + ICBLC = 1327 + + ICBLQ = 1328 + + ICBT = 1329 + + ICBTLS = 1330 + + ICCCI = 1331 + + ISEL = 1332 + + ISEL8 = 1333 + + ISYNC = 1334 + + LA = 1335 + + LA8 = 1336 + + LBARX = 1337 + + LBARXL = 1338 + + LBEPX = 1339 + + LBZ = 1340 + + LBZ8 = 1341 + + LBZCIX = 1342 + + LBZU = 1343 + + LBZU8 = 1344 + + LBZUX = 1345 + + LBZUX8 = 1346 + + LBZX = 1347 + + LBZX8 = 1348 + + LBZXTLS = 1349 + + LBZXTLS_ = 1350 + + LBZXTLS_32 = 1351 + + LD = 1352 + + LDARX = 1353 + + LDARXL = 1354 + + LDAT = 1355 + + LDAT_PSEUDO = 1356 + + LDBRX = 1357 + + LDCIX = 1358 + + LDU = 1359 + + LDUX = 1360 + + LDX = 1361 + + LDXTLS = 1362 + + LDXTLS_ = 1363 + + LDgotTprelL = 1364 + + LDgotTprelL32 = 1365 + + LDtoc = 1366 + + LDtocBA = 1367 + + LDtocCPT = 1368 + + LDtocJTI = 1369 + + LDtocL = 1370 + + LFD = 1371 + + LFDEPX = 1372 + + LFDU = 1373 + + LFDUX = 1374 + + LFDX = 1375 + + LFDXTLS = 1376 + + LFDXTLS_ = 1377 + + LFIWAX = 1378 + + LFIWZX = 1379 + + LFS = 1380 + + LFSU = 1381 + + LFSUX = 1382 + + LFSX = 1383 + + LFSXTLS = 1384 + + LFSXTLS_ = 1385 + + LHA = 1386 + + LHA8 = 1387 + + LHARX = 1388 + + LHARXL = 1389 + + LHAU = 1390 + + LHAU8 = 1391 + + LHAUX = 1392 + + LHAUX8 = 1393 + + LHAX = 1394 + + LHAX8 = 1395 + + LHAXTLS = 1396 + + LHAXTLS_ = 1397 + + LHAXTLS_32 = 1398 + + LHBRX = 1399 + + LHBRX8 = 1400 + + LHEPX = 1401 + + LHZ = 1402 + + LHZ8 = 1403 + + LHZCIX = 1404 + + LHZU = 1405 + + LHZU8 = 1406 + + LHZUX = 1407 + + LHZUX8 = 1408 + + LHZX = 1409 + + LHZX8 = 1410 + + LHZXTLS = 1411 + + LHZXTLS_ = 1412 + + LHZXTLS_32 = 1413 + + LI = 1414 + + LI8 = 1415 + + LIS = 1416 + + LIS8 = 1417 + + LMW = 1418 + + LQ = 1419 + + LQARX = 1420 + + LQARXL = 1421 + + LQX_PSEUDO = 1422 + + LSWI = 1423 + + LVEBX = 1424 + + LVEHX = 1425 + + LVEWX = 1426 + + LVSL = 1427 + + LVSR = 1428 + + LVX = 1429 + + LVXL = 1430 + + LWA = 1431 + + LWARX = 1432 + + LWARXL = 1433 + + LWAT = 1434 + + LWAT_PSEUDO = 1435 + + LWAUX = 1436 + + LWAX = 1437 + + LWAXTLS = 1438 + + LWAXTLS_ = 1439 + + LWAXTLS_32 = 1440 + + LWAX_32 = 1441 + + LWA_32 = 1442 + + LWBRX = 1443 + + LWBRX8 = 1444 + + LWEPX = 1445 + + LWZ = 1446 + + LWZ8 = 1447 + + LWZCIX = 1448 + + LWZU = 1449 + + LWZU8 = 1450 + + LWZUX = 1451 + + LWZUX8 = 1452 + + LWZX = 1453 + + LWZX8 = 1454 + + LWZXTLS = 1455 + + LWZXTLS_ = 1456 + + LWZXTLS_32 = 1457 + + LWZtoc = 1458 + + LWZtocL = 1459 + + LXSD = 1460 + + LXSDX = 1461 + + LXSIBZX = 1462 + + LXSIHZX = 1463 + + LXSIWAX = 1464 + + LXSIWZX = 1465 + + LXSSP = 1466 + + LXSSPX = 1467 + + LXV = 1468 + + LXVB16X = 1469 + + LXVD2X = 1470 + + LXVDSX = 1471 + + LXVH8X = 1472 + + LXVKQ = 1473 + + LXVL = 1474 + + LXVLL = 1475 + + LXVP = 1476 + + LXVPB32X = 1477 + + LXVPRL = 1478 + + LXVPRLL = 1479 + + LXVPX = 1480 + + LXVRBX = 1481 + + LXVRDX = 1482 + + LXVRHX = 1483 + + LXVRL = 1484 + + LXVRLL = 1485 + + LXVRWX = 1486 + + LXVW4X = 1487 + + LXVWSX = 1488 + + LXVX = 1489 + + MADDHD = 1490 + + MADDHDU = 1491 + + MADDLD = 1492 + + MADDLD8 = 1493 + + MBAR = 1494 + + MCRF = 1495 + + MCRFS = 1496 + + MCRXRX = 1497 + + MFBHRBE = 1498 + + MFCR = 1499 + + MFCR8 = 1500 + + MFCTR = 1501 + + MFCTR8 = 1502 + + MFDCR = 1503 + + MFFS = 1504 + + MFFSCDRN = 1505 + + MFFSCDRNI = 1506 + + MFFSCE = 1507 + + MFFSCRN = 1508 + + MFFSCRNI = 1509 + + MFFSL = 1510 + + MFFS_rec = 1511 + + MFLR = 1512 + + MFLR8 = 1513 + + MFMSR = 1514 + + MFOCRF = 1515 + + MFOCRF8 = 1516 + + MFPMR = 1517 + + MFSPR = 1518 + + MFSPR8 = 1519 + + MFSR = 1520 + + MFSRIN = 1521 + + MFTB = 1522 + + MFTB8 = 1523 + + MFUDSCR = 1524 + + MFVRD = 1525 + + MFVRSAVE = 1526 + + MFVRSAVEv = 1527 + + MFVRWZ = 1528 + + MFVSCR = 1529 + + MFVSRD = 1530 + + MFVSRLD = 1531 + + MFVSRWZ = 1532 + + MODSD = 1533 + + MODSW = 1534 + + MODUD = 1535 + + MODUW = 1536 + + MSGSYNC = 1537 + + MSYNC = 1538 + + MTCRF = 1539 + + MTCRF8 = 1540 + + MTCTR = 1541 + + MTCTR8 = 1542 + + MTCTR8loop = 1543 + + MTCTRloop = 1544 + + MTDCR = 1545 + + MTFSB0 = 1546 + + MTFSB1 = 1547 + + MTFSF = 1548 + + MTFSFI = 1549 + + MTFSFI_rec = 1550 + + MTFSFIb = 1551 + + MTFSF_rec = 1552 + + MTFSFb = 1553 + + MTLPL = 1554 + + MTLPL8 = 1555 + + MTLR = 1556 + + MTLR8 = 1557 + + MTMSR = 1558 + + MTMSRD = 1559 + + MTOCRF = 1560 + + MTOCRF8 = 1561 + + MTPMR = 1562 + + MTSPR = 1563 + + MTSPR8 = 1564 + + MTSR = 1565 + + MTSRIN = 1566 + + MTUDSCR = 1567 + + MTVRD = 1568 + + MTVRSAVE = 1569 + + MTVRSAVEv = 1570 + + MTVRWA = 1571 + + MTVRWZ = 1572 + + MTVSCR = 1573 + + MTVSRBM = 1574 + + MTVSRBMI = 1575 + + MTVSRD = 1576 + + MTVSRDD = 1577 + + MTVSRDM = 1578 + + MTVSRHM = 1579 + + MTVSRQM = 1580 + + MTVSRWA = 1581 + + MTVSRWM = 1582 + + MTVSRWS = 1583 + + MTVSRWZ = 1584 + + MULHD = 1585 + + MULHDU = 1586 + + MULHDU_rec = 1587 + + MULHD_rec = 1588 + + MULHW = 1589 + + MULHWU = 1590 + + MULHWU_rec = 1591 + + MULHW_rec = 1592 + + MULLD = 1593 + + MULLDO = 1594 + + MULLDO_rec = 1595 + + MULLD_rec = 1596 + + MULLI = 1597 + + MULLI8 = 1598 + + MULLW = 1599 + + MULLWO = 1600 + + MULLWO_rec = 1601 + + MULLW_rec = 1602 + + MoveGOTtoLR = 1603 + + MovePCtoLR = 1604 + + MovePCtoLR8 = 1605 + + NAND = 1606 + + NAND8 = 1607 + + NAND8_rec = 1608 + + NAND_rec = 1609 + + NAP = 1610 + + NEG = 1611 + + NEG8 = 1612 + + NEG8O = 1613 + + NEG8O_rec = 1614 + + NEG8_rec = 1615 + + NEGO = 1616 + + NEGO_rec = 1617 + + NEG_rec = 1618 + + NOP = 1619 + + NOP_GT_PWR6 = 1620 + + NOP_GT_PWR7 = 1621 + + NOR = 1622 + + NOR8 = 1623 + + NOR8_rec = 1624 + + NOR_rec = 1625 + + OR = 1626 + + OR8 = 1627 + + OR8_rec = 1628 + + ORC = 1629 + + ORC8 = 1630 + + ORC8_rec = 1631 + + ORC_rec = 1632 + + ORI = 1633 + + ORI8 = 1634 + + ORIS = 1635 + + ORIS8 = 1636 + + OR_rec = 1637 + + PADDI = 1638 + + PADDI8 = 1639 + + PADDI8pc = 1640 + + PADDIS = 1641 + + PADDIS8 = 1642 + + PADDIS8pc = 1643 + + PADDISpc = 1644 + + PADDIdtprel = 1645 + + PADDIpc = 1646 + + PDEPD = 1647 + + PEXTD = 1648 + + PLA = 1649 + + PLA8 = 1650 + + PLA8pc = 1651 + + PLApc = 1652 + + PLBZ = 1653 + + PLBZ8 = 1654 + + PLBZ8nopc = 1655 + + PLBZ8onlypc = 1656 + + PLBZ8pc = 1657 + + PLBZnopc = 1658 + + PLBZonlypc = 1659 + + PLBZpc = 1660 + + PLD = 1661 + + PLDnopc = 1662 + + PLDonlypc = 1663 + + PLDpc = 1664 + + PLFD = 1665 + + PLFDnopc = 1666 + + PLFDonlypc = 1667 + + PLFDpc = 1668 + + PLFS = 1669 + + PLFSnopc = 1670 + + PLFSonlypc = 1671 + + PLFSpc = 1672 + + PLHA = 1673 + + PLHA8 = 1674 + + PLHA8nopc = 1675 + + PLHA8onlypc = 1676 + + PLHA8pc = 1677 + + PLHAnopc = 1678 + + PLHAonlypc = 1679 + + PLHApc = 1680 + + PLHZ = 1681 + + PLHZ8 = 1682 + + PLHZ8nopc = 1683 + + PLHZ8onlypc = 1684 + + PLHZ8pc = 1685 + + PLHZnopc = 1686 + + PLHZonlypc = 1687 + + PLHZpc = 1688 + + PLI = 1689 + + PLI8 = 1690 + + PLWA = 1691 + + PLWA8 = 1692 + + PLWA8nopc = 1693 + + PLWA8onlypc = 1694 + + PLWA8pc = 1695 + + PLWAnopc = 1696 + + PLWAonlypc = 1697 + + PLWApc = 1698 + + PLWZ = 1699 + + PLWZ8 = 1700 + + PLWZ8nopc = 1701 + + PLWZ8onlypc = 1702 + + PLWZ8pc = 1703 + + PLWZnopc = 1704 + + PLWZonlypc = 1705 + + PLWZpc = 1706 + + PLXSD = 1707 + + PLXSDnopc = 1708 + + PLXSDonlypc = 1709 + + PLXSDpc = 1710 + + PLXSSP = 1711 + + PLXSSPnopc = 1712 + + PLXSSPonlypc = 1713 + + PLXSSPpc = 1714 + + PLXV = 1715 + + PLXVP = 1716 + + PLXVPnopc = 1717 + + PLXVPonlypc = 1718 + + PLXVPpc = 1719 + + PLXVnopc = 1720 + + PLXVonlypc = 1721 + + PLXVpc = 1722 + + PMDMXVBF16GERX2 = 1723 + + PMDMXVBF16GERX2NN = 1724 + + PMDMXVBF16GERX2NP = 1725 + + PMDMXVBF16GERX2PN = 1726 + + PMDMXVBF16GERX2PP = 1727 + + PMDMXVF16GERX2 = 1728 + + PMDMXVF16GERX2NN = 1729 + + PMDMXVF16GERX2NP = 1730 + + PMDMXVF16GERX2PN = 1731 + + PMDMXVF16GERX2PP = 1732 + + PMDMXVI8GERX4 = 1733 + + PMDMXVI8GERX4PP = 1734 + + PMDMXVI8GERX4SPP = 1735 + + PMXVBF16GER2 = 1736 + + PMXVBF16GER2NN = 1737 + + PMXVBF16GER2NP = 1738 + + PMXVBF16GER2PN = 1739 + + PMXVBF16GER2PP = 1740 + + PMXVBF16GER2W = 1741 + + PMXVBF16GER2WNN = 1742 + + PMXVBF16GER2WNP = 1743 + + PMXVBF16GER2WPN = 1744 + + PMXVBF16GER2WPP = 1745 + + PMXVF16GER2 = 1746 + + PMXVF16GER2NN = 1747 + + PMXVF16GER2NP = 1748 + + PMXVF16GER2PN = 1749 + + PMXVF16GER2PP = 1750 + + PMXVF16GER2W = 1751 + + PMXVF16GER2WNN = 1752 + + PMXVF16GER2WNP = 1753 + + PMXVF16GER2WPN = 1754 + + PMXVF16GER2WPP = 1755 + + PMXVF32GER = 1756 + + PMXVF32GERNN = 1757 + + PMXVF32GERNP = 1758 + + PMXVF32GERPN = 1759 + + PMXVF32GERPP = 1760 + + PMXVF32GERW = 1761 + + PMXVF32GERWNN = 1762 + + PMXVF32GERWNP = 1763 + + PMXVF32GERWPN = 1764 + + PMXVF32GERWPP = 1765 + + PMXVF64GER = 1766 + + PMXVF64GERNN = 1767 + + PMXVF64GERNP = 1768 + + PMXVF64GERPN = 1769 + + PMXVF64GERPP = 1770 + + PMXVF64GERW = 1771 + + PMXVF64GERWNN = 1772 + + PMXVF64GERWNP = 1773 + + PMXVF64GERWPN = 1774 + + PMXVF64GERWPP = 1775 + + PMXVI16GER2 = 1776 + + PMXVI16GER2PP = 1777 + + PMXVI16GER2S = 1778 + + PMXVI16GER2SPP = 1779 + + PMXVI16GER2SW = 1780 + + PMXVI16GER2SWPP = 1781 + + PMXVI16GER2W = 1782 + + PMXVI16GER2WPP = 1783 + + PMXVI4GER8 = 1784 + + PMXVI4GER8PP = 1785 + + PMXVI4GER8W = 1786 + + PMXVI4GER8WPP = 1787 + + PMXVI8GER4 = 1788 + + PMXVI8GER4PP = 1789 + + PMXVI8GER4SPP = 1790 + + PMXVI8GER4W = 1791 + + PMXVI8GER4WPP = 1792 + + PMXVI8GER4WSPP = 1793 + + POPCNTB = 1794 + + POPCNTB8 = 1795 + + POPCNTD = 1796 + + POPCNTW = 1797 + + PPC32GOT = 1798 + + PPC32PICGOT = 1799 + + PREPARE_PROBED_ALLOCA_32 = 1800 + + PREPARE_PROBED_ALLOCA_64 = 1801 + + PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 = 1802 + + PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 = 1803 + + PROBED_ALLOCA_32 = 1804 + + PROBED_ALLOCA_64 = 1805 + + PROBED_STACKALLOC_32 = 1806 + + PROBED_STACKALLOC_64 = 1807 + + PSTB = 1808 + + PSTB8 = 1809 + + PSTB8nopc = 1810 + + PSTB8onlypc = 1811 + + PSTB8pc = 1812 + + PSTBnopc = 1813 + + PSTBonlypc = 1814 + + PSTBpc = 1815 + + PSTD = 1816 + + PSTDnopc = 1817 + + PSTDonlypc = 1818 + + PSTDpc = 1819 + + PSTFD = 1820 + + PSTFDnopc = 1821 + + PSTFDonlypc = 1822 + + PSTFDpc = 1823 + + PSTFS = 1824 + + PSTFSnopc = 1825 + + PSTFSonlypc = 1826 + + PSTFSpc = 1827 + + PSTH = 1828 + + PSTH8 = 1829 + + PSTH8nopc = 1830 + + PSTH8onlypc = 1831 + + PSTH8pc = 1832 + + PSTHnopc = 1833 + + PSTHonlypc = 1834 + + PSTHpc = 1835 + + PSTW = 1836 + + PSTW8 = 1837 + + PSTW8nopc = 1838 + + PSTW8onlypc = 1839 + + PSTW8pc = 1840 + + PSTWnopc = 1841 + + PSTWonlypc = 1842 + + PSTWpc = 1843 + + PSTXSD = 1844 + + PSTXSDnopc = 1845 + + PSTXSDonlypc = 1846 + + PSTXSDpc = 1847 + + PSTXSSP = 1848 + + PSTXSSPnopc = 1849 + + PSTXSSPonlypc = 1850 + + PSTXSSPpc = 1851 + + PSTXV = 1852 + + PSTXVP = 1853 + + PSTXVPnopc = 1854 + + PSTXVPonlypc = 1855 + + PSTXVPpc = 1856 + + PSTXVnopc = 1857 + + PSTXVonlypc = 1858 + + PSTXVpc = 1859 + + PTESYNCIO = 1860 + + PseudoEIEIO = 1861 + + RESTORE_ACC = 1862 + + RESTORE_CR = 1863 + + RESTORE_CRBIT = 1864 + + RESTORE_DMR = 1865 + + RESTORE_DMRP = 1866 + + RESTORE_QUADWORD = 1867 + + RESTORE_UACC = 1868 + + RESTORE_WACC = 1869 + + RFCI = 1870 + + RFDI = 1871 + + RFEBB = 1872 + + RFI = 1873 + + RFID = 1874 + + RFMCI = 1875 + + RLDCL = 1876 + + RLDCL_rec = 1877 + + RLDCR = 1878 + + RLDCR_rec = 1879 + + RLDIC = 1880 + + RLDICL = 1881 + + RLDICL_32 = 1882 + + RLDICL_32_64 = 1883 + + RLDICL_32_rec = 1884 + + RLDICL_rec = 1885 + + RLDICR = 1886 + + RLDICR_32 = 1887 + + RLDICR_rec = 1888 + + RLDIC_rec = 1889 + + RLDIMI = 1890 + + RLDIMI_rec = 1891 + + RLWIMI = 1892 + + RLWIMI8 = 1893 + + RLWIMI8_rec = 1894 + + RLWIMI_rec = 1895 + + RLWINM = 1896 + + RLWINM8 = 1897 + + RLWINM8_rec = 1898 + + RLWINM_rec = 1899 + + RLWNM = 1900 + + RLWNM8 = 1901 + + RLWNM8_rec = 1902 + + RLWNM_rec = 1903 + + ReadTB = 1904 + + SC = 1905 + + SCV = 1906 + + SELECT_CC_F16 = 1907 + + SELECT_CC_F4 = 1908 + + SELECT_CC_F8 = 1909 + + SELECT_CC_I4 = 1910 + + SELECT_CC_I8 = 1911 + + SELECT_CC_SPE = 1912 + + SELECT_CC_SPE4 = 1913 + + SELECT_CC_VRRC = 1914 + + SELECT_CC_VSFRC = 1915 + + SELECT_CC_VSRC = 1916 + + SELECT_CC_VSSRC = 1917 + + SELECT_F16 = 1918 + + SELECT_F4 = 1919 + + SELECT_F8 = 1920 + + SELECT_I4 = 1921 + + SELECT_I8 = 1922 + + SELECT_SPE = 1923 + + SELECT_SPE4 = 1924 + + SELECT_VRRC = 1925 + + SELECT_VSFRC = 1926 + + SELECT_VSRC = 1927 + + SELECT_VSSRC = 1928 + + SETB = 1929 + + SETB8 = 1930 + + SETBC = 1931 + + SETBC8 = 1932 + + SETBCR = 1933 + + SETBCR8 = 1934 + + SETFLM = 1935 + + SETNBC = 1936 + + SETNBC8 = 1937 + + SETNBCR = 1938 + + SETNBCR8 = 1939 + + SETRND = 1940 + + SETRNDi = 1941 + + SLBFEE_rec = 1942 + + SLBIA = 1943 + + SLBIE = 1944 + + SLBIEG = 1945 + + SLBMFEE = 1946 + + SLBMFEV = 1947 + + SLBMTE = 1948 + + SLBSYNC = 1949 + + SLD = 1950 + + SLD_rec = 1951 + + SLW = 1952 + + SLW8 = 1953 + + SLW8_rec = 1954 + + SLW_rec = 1955 + + SPELWZ = 1956 + + SPELWZX = 1957 + + SPESTW = 1958 + + SPESTWX = 1959 + + SPILL_ACC = 1960 + + SPILL_CR = 1961 + + SPILL_CRBIT = 1962 + + SPILL_DMR = 1963 + + SPILL_DMRP = 1964 + + SPILL_QUADWORD = 1965 + + SPILL_UACC = 1966 + + SPILL_WACC = 1967 + + SPLIT_QUADWORD = 1968 + + SRAD = 1969 + + SRADI = 1970 + + SRADI_32 = 1971 + + SRADI_rec = 1972 + + SRAD_rec = 1973 + + SRAW = 1974 + + SRAW8 = 1975 + + SRAW8_rec = 1976 + + SRAWI = 1977 + + SRAWI8 = 1978 + + SRAWI8_rec = 1979 + + SRAWI_rec = 1980 + + SRAW_rec = 1981 + + SRD = 1982 + + SRD_rec = 1983 + + SRW = 1984 + + SRW8 = 1985 + + SRW8_rec = 1986 + + SRW_rec = 1987 + + STB = 1988 + + STB8 = 1989 + + STBCIX = 1990 + + STBCX = 1991 + + STBEPX = 1992 + + STBU = 1993 + + STBU8 = 1994 + + STBUX = 1995 + + STBUX8 = 1996 + + STBX = 1997 + + STBX8 = 1998 + + STBXTLS = 1999 + + STBXTLS_ = 2000 + + STBXTLS_32 = 2001 + + STD = 2002 + + STDAT = 2003 + + STDBRX = 2004 + + STDCIX = 2005 + + STDCX = 2006 + + STDU = 2007 + + STDUX = 2008 + + STDX = 2009 + + STDXTLS = 2010 + + STDXTLS_ = 2011 + + STFD = 2012 + + STFDEPX = 2013 + + STFDU = 2014 + + STFDUX = 2015 + + STFDX = 2016 + + STFDXTLS = 2017 + + STFDXTLS_ = 2018 + + STFIWX = 2019 + + STFS = 2020 + + STFSU = 2021 + + STFSUX = 2022 + + STFSX = 2023 + + STFSXTLS = 2024 + + STFSXTLS_ = 2025 + + STH = 2026 + + STH8 = 2027 + + STHBRX = 2028 + + STHCIX = 2029 + + STHCX = 2030 + + STHEPX = 2031 + + STHU = 2032 + + STHU8 = 2033 + + STHUX = 2034 + + STHUX8 = 2035 + + STHX = 2036 + + STHX8 = 2037 + + STHXTLS = 2038 + + STHXTLS_ = 2039 + + STHXTLS_32 = 2040 + + STMW = 2041 + + STOP = 2042 + + STQ = 2043 + + STQCX = 2044 + + STQX_PSEUDO = 2045 + + STSWI = 2046 + + STVEBX = 2047 + + STVEHX = 2048 + + STVEWX = 2049 + + STVX = 2050 + + STVXL = 2051 + + STW = 2052 + + STW8 = 2053 + + STWAT = 2054 + + STWBRX = 2055 + + STWCIX = 2056 + + STWCX = 2057 + + STWEPX = 2058 + + STWU = 2059 + + STWU8 = 2060 + + STWUX = 2061 + + STWUX8 = 2062 + + STWX = 2063 + + STWX8 = 2064 + + STWXTLS = 2065 + + STWXTLS_ = 2066 + + STWXTLS_32 = 2067 + + STXSD = 2068 + + STXSDX = 2069 + + STXSIBX = 2070 + + STXSIBXv = 2071 + + STXSIHX = 2072 + + STXSIHXv = 2073 + + STXSIWX = 2074 + + STXSSP = 2075 + + STXSSPX = 2076 + + STXV = 2077 + + STXVB16X = 2078 + + STXVD2X = 2079 + + STXVH8X = 2080 + + STXVL = 2081 + + STXVLL = 2082 + + STXVP = 2083 + + STXVPB32X = 2084 + + STXVPRL = 2085 + + STXVPRLL = 2086 + + STXVPX = 2087 + + STXVRBX = 2088 + + STXVRDX = 2089 + + STXVRHX = 2090 + + STXVRL = 2091 + + STXVRLL = 2092 + + STXVRWX = 2093 + + STXVW4X = 2094 + + STXVX = 2095 + + SUBF = 2096 + + SUBF8 = 2097 + + SUBF8O = 2098 + + SUBF8O_rec = 2099 + + SUBF8_rec = 2100 + + SUBFC = 2101 + + SUBFC8 = 2102 + + SUBFC8O = 2103 + + SUBFC8O_rec = 2104 + + SUBFC8_rec = 2105 + + SUBFCO = 2106 + + SUBFCO_rec = 2107 + + SUBFC_rec = 2108 + + SUBFE = 2109 + + SUBFE8 = 2110 + + SUBFE8O = 2111 + + SUBFE8O_rec = 2112 + + SUBFE8_rec = 2113 + + SUBFEO = 2114 + + SUBFEO_rec = 2115 + + SUBFE_rec = 2116 + + SUBFIC = 2117 + + SUBFIC8 = 2118 + + SUBFME = 2119 + + SUBFME8 = 2120 + + SUBFME8O = 2121 + + SUBFME8O_rec = 2122 + + SUBFME8_rec = 2123 + + SUBFMEO = 2124 + + SUBFMEO_rec = 2125 + + SUBFME_rec = 2126 + + SUBFO = 2127 + + SUBFO_rec = 2128 + + SUBFUS = 2129 + + SUBFUS_rec = 2130 + + SUBFZE = 2131 + + SUBFZE8 = 2132 + + SUBFZE8O = 2133 + + SUBFZE8O_rec = 2134 + + SUBFZE8_rec = 2135 + + SUBFZEO = 2136 + + SUBFZEO_rec = 2137 + + SUBFZE_rec = 2138 + + SUBF_rec = 2139 + + SYNC = 2140 + + SYNCP10 = 2141 + + TABORT = 2142 + + TABORTDC = 2143 + + TABORTDCI = 2144 + + TABORTWC = 2145 + + TABORTWCI = 2146 + + TAILB = 2147 + + TAILB8 = 2148 + + TAILBA = 2149 + + TAILBA8 = 2150 + + TAILBCTR = 2151 + + TAILBCTR8 = 2152 + + TBEGIN = 2153 + + TBEGIN_RET = 2154 + + TCHECK = 2155 + + TCHECK_RET = 2156 + + TCRETURNai = 2157 + + TCRETURNai8 = 2158 + + TCRETURNdi = 2159 + + TCRETURNdi8 = 2160 + + TCRETURNri = 2161 + + TCRETURNri8 = 2162 + + TD = 2163 + + TDI = 2164 + + TEND = 2165 + + TLBIA = 2166 + + TLBIE = 2167 + + TLBIE8P9 = 2168 + + TLBIEIO = 2169 + + TLBIEL = 2170 + + TLBIEP = 2171 + + TLBIEP8 = 2172 + + TLBIEP9 = 2173 + + TLBILX = 2174 + + TLBIVAX = 2175 + + TLBLD = 2176 + + TLBLI = 2177 + + TLBRE = 2178 + + TLBRE2 = 2179 + + TLBSX = 2180 + + TLBSX2 = 2181 + + TLBSX2D = 2182 + + TLBSYNC = 2183 + + TLBSYNCIO = 2184 + + TLBWE = 2185 + + TLBWE2 = 2186 + + TLSGDAIX = 2187 + + TLSGDAIX8 = 2188 + + TLSLDAIX = 2189 + + TLSLDAIX8 = 2190 + + TRAP = 2191 + + TRECHKPT = 2192 + + TRECLAIM = 2193 + + TSR = 2194 + + TW = 2195 + + TWI = 2196 + + UNENCODED_NOP = 2197 + + UpdateGBR = 2198 + + VABSDUB = 2199 + + VABSDUH = 2200 + + VABSDUW = 2201 + + VADDCUQ = 2202 + + VADDCUW = 2203 + + VADDECUQ = 2204 + + VADDEUQM = 2205 + + VADDFP = 2206 + + VADDSBS = 2207 + + VADDSHS = 2208 + + VADDSWS = 2209 + + VADDUBM = 2210 + + VADDUBS = 2211 + + VADDUDM = 2212 + + VADDUHM = 2213 + + VADDUHS = 2214 + + VADDUQM = 2215 + + VADDUWM = 2216 + + VADDUWS = 2217 + + VAND = 2218 + + VANDC = 2219 + + VAVGSB = 2220 + + VAVGSH = 2221 + + VAVGSW = 2222 + + VAVGUB = 2223 + + VAVGUH = 2224 + + VAVGUW = 2225 + + VBPERMD = 2226 + + VBPERMQ = 2227 + + VCFSX = 2228 + + VCFSX_0 = 2229 + + VCFUGED = 2230 + + VCFUX = 2231 + + VCFUX_0 = 2232 + + VCIPHER = 2233 + + VCIPHERLAST = 2234 + + VCLRLB = 2235 + + VCLRRB = 2236 + + VCLZB = 2237 + + VCLZD = 2238 + + VCLZDM = 2239 + + VCLZH = 2240 + + VCLZLSBB = 2241 + + VCLZW = 2242 + + VCMPBFP = 2243 + + VCMPBFP_rec = 2244 + + VCMPEQFP = 2245 + + VCMPEQFP_rec = 2246 + + VCMPEQUB = 2247 + + VCMPEQUB_rec = 2248 + + VCMPEQUD = 2249 + + VCMPEQUD_rec = 2250 + + VCMPEQUH = 2251 + + VCMPEQUH_rec = 2252 + + VCMPEQUQ = 2253 + + VCMPEQUQ_rec = 2254 + + VCMPEQUW = 2255 + + VCMPEQUW_rec = 2256 + + VCMPGEFP = 2257 + + VCMPGEFP_rec = 2258 + + VCMPGTFP = 2259 + + VCMPGTFP_rec = 2260 + + VCMPGTSB = 2261 + + VCMPGTSB_rec = 2262 + + VCMPGTSD = 2263 + + VCMPGTSD_rec = 2264 + + VCMPGTSH = 2265 + + VCMPGTSH_rec = 2266 + + VCMPGTSQ = 2267 + + VCMPGTSQ_rec = 2268 + + VCMPGTSW = 2269 + + VCMPGTSW_rec = 2270 + + VCMPGTUB = 2271 + + VCMPGTUB_rec = 2272 + + VCMPGTUD = 2273 + + VCMPGTUD_rec = 2274 + + VCMPGTUH = 2275 + + VCMPGTUH_rec = 2276 + + VCMPGTUQ = 2277 + + VCMPGTUQ_rec = 2278 + + VCMPGTUW = 2279 + + VCMPGTUW_rec = 2280 + + VCMPNEB = 2281 + + VCMPNEB_rec = 2282 + + VCMPNEH = 2283 + + VCMPNEH_rec = 2284 + + VCMPNEW = 2285 + + VCMPNEW_rec = 2286 + + VCMPNEZB = 2287 + + VCMPNEZB_rec = 2288 + + VCMPNEZH = 2289 + + VCMPNEZH_rec = 2290 + + VCMPNEZW = 2291 + + VCMPNEZW_rec = 2292 + + VCMPSQ = 2293 + + VCMPUQ = 2294 + + VCNTMBB = 2295 + + VCNTMBD = 2296 + + VCNTMBH = 2297 + + VCNTMBW = 2298 + + VCTSXS = 2299 + + VCTSXS_0 = 2300 + + VCTUXS = 2301 + + VCTUXS_0 = 2302 + + VCTZB = 2303 + + VCTZD = 2304 + + VCTZDM = 2305 + + VCTZH = 2306 + + VCTZLSBB = 2307 + + VCTZW = 2308 + + VDIVESD = 2309 + + VDIVESQ = 2310 + + VDIVESW = 2311 + + VDIVEUD = 2312 + + VDIVEUQ = 2313 + + VDIVEUW = 2314 + + VDIVSD = 2315 + + VDIVSQ = 2316 + + VDIVSW = 2317 + + VDIVUD = 2318 + + VDIVUQ = 2319 + + VDIVUW = 2320 + + VEQV = 2321 + + VEXPANDBM = 2322 + + VEXPANDDM = 2323 + + VEXPANDHM = 2324 + + VEXPANDQM = 2325 + + VEXPANDWM = 2326 + + VEXPTEFP = 2327 + + VEXTDDVLX = 2328 + + VEXTDDVRX = 2329 + + VEXTDUBVLX = 2330 + + VEXTDUBVRX = 2331 + + VEXTDUHVLX = 2332 + + VEXTDUHVRX = 2333 + + VEXTDUWVLX = 2334 + + VEXTDUWVRX = 2335 + + VEXTRACTBM = 2336 + + VEXTRACTD = 2337 + + VEXTRACTDM = 2338 + + VEXTRACTHM = 2339 + + VEXTRACTQM = 2340 + + VEXTRACTUB = 2341 + + VEXTRACTUH = 2342 + + VEXTRACTUW = 2343 + + VEXTRACTWM = 2344 + + VEXTSB2D = 2345 + + VEXTSB2Ds = 2346 + + VEXTSB2W = 2347 + + VEXTSB2Ws = 2348 + + VEXTSD2Q = 2349 + + VEXTSH2D = 2350 + + VEXTSH2Ds = 2351 + + VEXTSH2W = 2352 + + VEXTSH2Ws = 2353 + + VEXTSW2D = 2354 + + VEXTSW2Ds = 2355 + + VEXTUBLX = 2356 + + VEXTUBRX = 2357 + + VEXTUHLX = 2358 + + VEXTUHRX = 2359 + + VEXTUWLX = 2360 + + VEXTUWRX = 2361 + + VGBBD = 2362 + + VGNB = 2363 + + VINSBLX = 2364 + + VINSBRX = 2365 + + VINSBVLX = 2366 + + VINSBVRX = 2367 + + VINSD = 2368 + + VINSDLX = 2369 + + VINSDRX = 2370 + + VINSERTB = 2371 + + VINSERTD = 2372 + + VINSERTH = 2373 + + VINSERTW = 2374 + + VINSHLX = 2375 + + VINSHRX = 2376 + + VINSHVLX = 2377 + + VINSHVRX = 2378 + + VINSW = 2379 + + VINSWLX = 2380 + + VINSWRX = 2381 + + VINSWVLX = 2382 + + VINSWVRX = 2383 + + VLOGEFP = 2384 + + VMADDFP = 2385 + + VMAXFP = 2386 + + VMAXSB = 2387 + + VMAXSD = 2388 + + VMAXSH = 2389 + + VMAXSW = 2390 + + VMAXUB = 2391 + + VMAXUD = 2392 + + VMAXUH = 2393 + + VMAXUW = 2394 + + VMHADDSHS = 2395 + + VMHRADDSHS = 2396 + + VMINFP = 2397 + + VMINSB = 2398 + + VMINSD = 2399 + + VMINSH = 2400 + + VMINSW = 2401 + + VMINUB = 2402 + + VMINUD = 2403 + + VMINUH = 2404 + + VMINUW = 2405 + + VMLADDUHM = 2406 + + VMODSD = 2407 + + VMODSQ = 2408 + + VMODSW = 2409 + + VMODUD = 2410 + + VMODUQ = 2411 + + VMODUW = 2412 + + VMRGEW = 2413 + + VMRGHB = 2414 + + VMRGHH = 2415 + + VMRGHW = 2416 + + VMRGLB = 2417 + + VMRGLH = 2418 + + VMRGLW = 2419 + + VMRGOW = 2420 + + VMSUMCUD = 2421 + + VMSUMMBM = 2422 + + VMSUMSHM = 2423 + + VMSUMSHS = 2424 + + VMSUMUBM = 2425 + + VMSUMUDM = 2426 + + VMSUMUHM = 2427 + + VMSUMUHS = 2428 + + VMUL10CUQ = 2429 + + VMUL10ECUQ = 2430 + + VMUL10EUQ = 2431 + + VMUL10UQ = 2432 + + VMULESB = 2433 + + VMULESD = 2434 + + VMULESH = 2435 + + VMULESW = 2436 + + VMULEUB = 2437 + + VMULEUD = 2438 + + VMULEUH = 2439 + + VMULEUW = 2440 + + VMULHSD = 2441 + + VMULHSW = 2442 + + VMULHUD = 2443 + + VMULHUW = 2444 + + VMULLD = 2445 + + VMULOSB = 2446 + + VMULOSD = 2447 + + VMULOSH = 2448 + + VMULOSW = 2449 + + VMULOUB = 2450 + + VMULOUD = 2451 + + VMULOUH = 2452 + + VMULOUW = 2453 + + VMULUWM = 2454 + + VNAND = 2455 + + VNCIPHER = 2456 + + VNCIPHERLAST = 2457 + + VNEGD = 2458 + + VNEGW = 2459 + + VNMSUBFP = 2460 + + VNOR = 2461 + + VOR = 2462 + + VORC = 2463 + + VPDEPD = 2464 + + VPERM = 2465 + + VPERMR = 2466 + + VPERMXOR = 2467 + + VPEXTD = 2468 + + VPKPX = 2469 + + VPKSDSS = 2470 + + VPKSDUS = 2471 + + VPKSHSS = 2472 + + VPKSHUS = 2473 + + VPKSWSS = 2474 + + VPKSWUS = 2475 + + VPKUDUM = 2476 + + VPKUDUS = 2477 + + VPKUHUM = 2478 + + VPKUHUS = 2479 + + VPKUWUM = 2480 + + VPKUWUS = 2481 + + VPMSUMB = 2482 + + VPMSUMD = 2483 + + VPMSUMH = 2484 + + VPMSUMW = 2485 + + VPOPCNTB = 2486 + + VPOPCNTD = 2487 + + VPOPCNTH = 2488 + + VPOPCNTW = 2489 + + VPRTYBD = 2490 + + VPRTYBQ = 2491 + + VPRTYBW = 2492 + + VREFP = 2493 + + VRFIM = 2494 + + VRFIN = 2495 + + VRFIP = 2496 + + VRFIZ = 2497 + + VRLB = 2498 + + VRLD = 2499 + + VRLDMI = 2500 + + VRLDNM = 2501 + + VRLH = 2502 + + VRLQ = 2503 + + VRLQMI = 2504 + + VRLQNM = 2505 + + VRLW = 2506 + + VRLWMI = 2507 + + VRLWNM = 2508 + + VRSQRTEFP = 2509 + + VSBOX = 2510 + + VSEL = 2511 + + VSHASIGMAD = 2512 + + VSHASIGMAW = 2513 + + VSL = 2514 + + VSLB = 2515 + + VSLD = 2516 + + VSLDBI = 2517 + + VSLDOI = 2518 + + VSLH = 2519 + + VSLO = 2520 + + VSLQ = 2521 + + VSLV = 2522 + + VSLW = 2523 + + VSPLTB = 2524 + + VSPLTBs = 2525 + + VSPLTH = 2526 + + VSPLTHs = 2527 + + VSPLTISB = 2528 + + VSPLTISH = 2529 + + VSPLTISW = 2530 + + VSPLTW = 2531 + + VSR = 2532 + + VSRAB = 2533 + + VSRAD = 2534 + + VSRAH = 2535 + + VSRAQ = 2536 + + VSRAW = 2537 + + VSRB = 2538 + + VSRD = 2539 + + VSRDBI = 2540 + + VSRH = 2541 + + VSRO = 2542 + + VSRQ = 2543 + + VSRV = 2544 + + VSRW = 2545 + + VSTRIBL = 2546 + + VSTRIBL_rec = 2547 + + VSTRIBR = 2548 + + VSTRIBR_rec = 2549 + + VSTRIHL = 2550 + + VSTRIHL_rec = 2551 + + VSTRIHR = 2552 + + VSTRIHR_rec = 2553 + + VSUBCUQ = 2554 + + VSUBCUW = 2555 + + VSUBECUQ = 2556 + + VSUBEUQM = 2557 + + VSUBFP = 2558 + + VSUBSBS = 2559 + + VSUBSHS = 2560 + + VSUBSWS = 2561 + + VSUBUBM = 2562 + + VSUBUBS = 2563 + + VSUBUDM = 2564 + + VSUBUHM = 2565 + + VSUBUHS = 2566 + + VSUBUQM = 2567 + + VSUBUWM = 2568 + + VSUBUWS = 2569 + + VSUM2SWS = 2570 + + VSUM4SBS = 2571 + + VSUM4SHS = 2572 + + VSUM4UBS = 2573 + + VSUMSWS = 2574 + + VUCMPRHB = 2575 + + VUCMPRHH = 2576 + + VUCMPRHN = 2577 + + VUCMPRLB = 2578 + + VUCMPRLH = 2579 + + VUCMPRLN = 2580 + + VUPKHPX = 2581 + + VUPKHSB = 2582 + + VUPKHSH = 2583 + + VUPKHSNTOB = 2584 + + VUPKHSW = 2585 + + VUPKINT4TOBF16 = 2586 + + VUPKINT4TOFP32 = 2587 + + VUPKINT8TOBF16 = 2588 + + VUPKINT8TOFP32 = 2589 + + VUPKLPX = 2590 + + VUPKLSB = 2591 + + VUPKLSH = 2592 + + VUPKLSNTOB = 2593 + + VUPKLSW = 2594 + + VXOR = 2595 + + V_SET0 = 2596 + + V_SET0B = 2597 + + V_SET0H = 2598 + + V_SETALLONES = 2599 + + V_SETALLONESB = 2600 + + V_SETALLONESH = 2601 + + WAIT = 2602 + + WAITP10 = 2603 + + WRTEE = 2604 + + WRTEEI = 2605 + + XOR = 2606 + + XOR8 = 2607 + + XOR8_rec = 2608 + + XORI = 2609 + + XORI8 = 2610 + + XORIS = 2611 + + XORIS8 = 2612 + + XOR_rec = 2613 + + XSABSDP = 2614 + + XSABSQP = 2615 + + XSADDADDSUQM = 2616 + + XSADDADDUQM = 2617 + + XSADDDP = 2618 + + XSADDQP = 2619 + + XSADDQPO = 2620 + + XSADDSP = 2621 + + XSADDSUBSUQM = 2622 + + XSADDSUBUQM = 2623 + + XSCMPEQDP = 2624 + + XSCMPEQQP = 2625 + + XSCMPEXPDP = 2626 + + XSCMPEXPQP = 2627 + + XSCMPGEDP = 2628 + + XSCMPGEQP = 2629 + + XSCMPGTDP = 2630 + + XSCMPGTQP = 2631 + + XSCMPODP = 2632 + + XSCMPOQP = 2633 + + XSCMPUDP = 2634 + + XSCMPUQP = 2635 + + XSCPSGNDP = 2636 + + XSCPSGNQP = 2637 + + XSCVDPHP = 2638 + + XSCVDPQP = 2639 + + XSCVDPSP = 2640 + + XSCVDPSPN = 2641 + + XSCVDPSXDS = 2642 + + XSCVDPSXDSs = 2643 + + XSCVDPSXWS = 2644 + + XSCVDPSXWSs = 2645 + + XSCVDPUXDS = 2646 + + XSCVDPUXDSs = 2647 + + XSCVDPUXWS = 2648 + + XSCVDPUXWSs = 2649 + + XSCVHPDP = 2650 + + XSCVQPDP = 2651 + + XSCVQPDPO = 2652 + + XSCVQPSDZ = 2653 + + XSCVQPSQZ = 2654 + + XSCVQPSWZ = 2655 + + XSCVQPUDZ = 2656 + + XSCVQPUQZ = 2657 + + XSCVQPUWZ = 2658 + + XSCVSDQP = 2659 + + XSCVSPDP = 2660 + + XSCVSPDPN = 2661 + + XSCVSQQP = 2662 + + XSCVSXDDP = 2663 + + XSCVSXDSP = 2664 + + XSCVUDQP = 2665 + + XSCVUQQP = 2666 + + XSCVUXDDP = 2667 + + XSCVUXDSP = 2668 + + XSDIVDP = 2669 + + XSDIVQP = 2670 + + XSDIVQPO = 2671 + + XSDIVSP = 2672 + + XSIEXPDP = 2673 + + XSIEXPQP = 2674 + + XSMADDADP = 2675 + + XSMADDASP = 2676 + + XSMADDMDP = 2677 + + XSMADDMSP = 2678 + + XSMADDQP = 2679 + + XSMADDQPO = 2680 + + XSMAXCDP = 2681 + + XSMAXCQP = 2682 + + XSMAXDP = 2683 + + XSMAXJDP = 2684 + + XSMERGE2T1UQM = 2685 + + XSMERGE2T2UQM = 2686 + + XSMERGE2T3UQM = 2687 + + XSMERGE3T1UQM = 2688 + + XSMINCDP = 2689 + + XSMINCQP = 2690 + + XSMINDP = 2691 + + XSMINJDP = 2692 + + XSMSUBADP = 2693 + + XSMSUBASP = 2694 + + XSMSUBMDP = 2695 + + XSMSUBMSP = 2696 + + XSMSUBQP = 2697 + + XSMSUBQPO = 2698 + + XSMULDP = 2699 + + XSMULQP = 2700 + + XSMULQPO = 2701 + + XSMULSP = 2702 + + XSNABSDP = 2703 + + XSNABSDPs = 2704 + + XSNABSQP = 2705 + + XSNEGDP = 2706 + + XSNEGQP = 2707 + + XSNMADDADP = 2708 + + XSNMADDASP = 2709 + + XSNMADDMDP = 2710 + + XSNMADDMSP = 2711 + + XSNMADDQP = 2712 + + XSNMADDQPO = 2713 + + XSNMSUBADP = 2714 + + XSNMSUBASP = 2715 + + XSNMSUBMDP = 2716 + + XSNMSUBMSP = 2717 + + XSNMSUBQP = 2718 + + XSNMSUBQPO = 2719 + + XSRDPI = 2720 + + XSRDPIC = 2721 + + XSRDPIM = 2722 + + XSRDPIP = 2723 + + XSRDPIZ = 2724 + + XSREBASE2T1UQM = 2725 + + XSREBASE2T2UQM = 2726 + + XSREBASE2T3UQM = 2727 + + XSREBASE2T4UQM = 2728 + + XSREBASE3T1UQM = 2729 + + XSREBASE3T2UQM = 2730 + + XSREBASE3T3UQM = 2731 + + XSREDP = 2732 + + XSRESP = 2733 + + XSRQPI = 2734 + + XSRQPIX = 2735 + + XSRQPXP = 2736 + + XSRSP = 2737 + + XSRSQRTEDP = 2738 + + XSRSQRTESP = 2739 + + XSSQRTDP = 2740 + + XSSQRTQP = 2741 + + XSSQRTQPO = 2742 + + XSSQRTSP = 2743 + + XSSUBDP = 2744 + + XSSUBQP = 2745 + + XSSUBQPO = 2746 + + XSSUBSP = 2747 + + XSTDIVDP = 2748 + + XSTSQRTDP = 2749 + + XSTSTDCDP = 2750 + + XSTSTDCQP = 2751 + + XSTSTDCSP = 2752 + + XSXEXPDP = 2753 + + XSXEXPQP = 2754 + + XSXSIGDP = 2755 + + XSXSIGQP = 2756 + + XVABSDP = 2757 + + XVABSSP = 2758 + + XVADDDP = 2759 + + XVADDSP = 2760 + + XVADDUHM = 2761 + + XVADDUWM = 2762 + + XVBF16GER2 = 2763 + + XVBF16GER2NN = 2764 + + XVBF16GER2NP = 2765 + + XVBF16GER2PN = 2766 + + XVBF16GER2PP = 2767 + + XVBF16GER2W = 2768 + + XVBF16GER2WNN = 2769 + + XVBF16GER2WNP = 2770 + + XVBF16GER2WPN = 2771 + + XVBF16GER2WPP = 2772 + + XVCMPEQDP = 2773 + + XVCMPEQDP_rec = 2774 + + XVCMPEQSP = 2775 + + XVCMPEQSP_rec = 2776 + + XVCMPGEDP = 2777 + + XVCMPGEDP_rec = 2778 + + XVCMPGESP = 2779 + + XVCMPGESP_rec = 2780 + + XVCMPGTDP = 2781 + + XVCMPGTDP_rec = 2782 + + XVCMPGTSP = 2783 + + XVCMPGTSP_rec = 2784 + + XVCPSGNDP = 2785 + + XVCPSGNSP = 2786 + + XVCVBF16SPN = 2787 + + XVCVDPSP = 2788 + + XVCVDPSXDS = 2789 + + XVCVDPSXWS = 2790 + + XVCVDPUXDS = 2791 + + XVCVDPUXWS = 2792 + + XVCVHPSP = 2793 + + XVCVSPBF16 = 2794 + + XVCVSPDP = 2795 + + XVCVSPHP = 2796 + + XVCVSPSXDS = 2797 + + XVCVSPSXWS = 2798 + + XVCVSPUXDS = 2799 + + XVCVSPUXWS = 2800 + + XVCVSXDDP = 2801 + + XVCVSXDSP = 2802 + + XVCVSXWDP = 2803 + + XVCVSXWSP = 2804 + + XVCVUXDDP = 2805 + + XVCVUXDSP = 2806 + + XVCVUXWDP = 2807 + + XVCVUXWSP = 2808 + + XVDIVDP = 2809 + + XVDIVSP = 2810 + + XVF16GER2 = 2811 + + XVF16GER2NN = 2812 + + XVF16GER2NP = 2813 + + XVF16GER2PN = 2814 + + XVF16GER2PP = 2815 + + XVF16GER2W = 2816 + + XVF16GER2WNN = 2817 + + XVF16GER2WNP = 2818 + + XVF16GER2WPN = 2819 + + XVF16GER2WPP = 2820 + + XVF32GER = 2821 + + XVF32GERNN = 2822 + + XVF32GERNP = 2823 + + XVF32GERPN = 2824 + + XVF32GERPP = 2825 + + XVF32GERW = 2826 + + XVF32GERWNN = 2827 + + XVF32GERWNP = 2828 + + XVF32GERWPN = 2829 + + XVF32GERWPP = 2830 + + XVF64GER = 2831 + + XVF64GERNN = 2832 + + XVF64GERNP = 2833 + + XVF64GERPN = 2834 + + XVF64GERPP = 2835 + + XVF64GERW = 2836 + + XVF64GERWNN = 2837 + + XVF64GERWNP = 2838 + + XVF64GERWPN = 2839 + + XVF64GERWPP = 2840 + + XVI16GER2 = 2841 + + XVI16GER2PP = 2842 + + XVI16GER2S = 2843 + + XVI16GER2SPP = 2844 + + XVI16GER2SW = 2845 + + XVI16GER2SWPP = 2846 + + XVI16GER2W = 2847 + + XVI16GER2WPP = 2848 + + XVI4GER8 = 2849 + + XVI4GER8PP = 2850 + + XVI4GER8W = 2851 + + XVI4GER8WPP = 2852 + + XVI8GER4 = 2853 + + XVI8GER4PP = 2854 + + XVI8GER4SPP = 2855 + + XVI8GER4W = 2856 + + XVI8GER4WPP = 2857 + + XVI8GER4WSPP = 2858 + + XVIEXPDP = 2859 + + XVIEXPSP = 2860 + + XVMADDADP = 2861 + + XVMADDASP = 2862 + + XVMADDMDP = 2863 + + XVMADDMSP = 2864 + + XVMAXDP = 2865 + + XVMAXSP = 2866 + + XVMINDP = 2867 + + XVMINSP = 2868 + + XVMSUBADP = 2869 + + XVMSUBASP = 2870 + + XVMSUBMDP = 2871 + + XVMSUBMSP = 2872 + + XVMULDP = 2873 + + XVMULHSH = 2874 + + XVMULHSW = 2875 + + XVMULHUH = 2876 + + XVMULHUW = 2877 + + XVMULSP = 2878 + + XVMULUHM = 2879 + + XVMULUWM = 2880 + + XVNABSDP = 2881 + + XVNABSSP = 2882 + + XVNEGDP = 2883 + + XVNEGSP = 2884 + + XVNMADDADP = 2885 + + XVNMADDASP = 2886 + + XVNMADDMDP = 2887 + + XVNMADDMSP = 2888 + + XVNMSUBADP = 2889 + + XVNMSUBASP = 2890 + + XVNMSUBMDP = 2891 + + XVNMSUBMSP = 2892 + + XVRDPI = 2893 + + XVRDPIC = 2894 + + XVRDPIM = 2895 + + XVRDPIP = 2896 + + XVRDPIZ = 2897 + + XVREDP = 2898 + + XVRESP = 2899 + + XVRLW = 2900 + + XVRSPI = 2901 + + XVRSPIC = 2902 + + XVRSPIM = 2903 + + XVRSPIP = 2904 + + XVRSPIZ = 2905 + + XVRSQRTEDP = 2906 + + XVRSQRTESP = 2907 + + XVSQRTDP = 2908 + + XVSQRTSP = 2909 + + XVSUBDP = 2910 + + XVSUBSP = 2911 + + XVSUBUHM = 2912 + + XVSUBUWM = 2913 + + XVTDIVDP = 2914 + + XVTDIVSP = 2915 + + XVTLSBB = 2916 + + XVTSQRTDP = 2917 + + XVTSQRTSP = 2918 + + XVTSTDCDP = 2919 + + XVTSTDCSP = 2920 + + XVXEXPDP = 2921 + + XVXEXPSP = 2922 + + XVXSIGDP = 2923 + + XVXSIGSP = 2924 + + XXAESDECP = 2925 + + XXAESENCP = 2926 + + XXAESGENLKP = 2927 + + XXBLENDVB = 2928 + + XXBLENDVD = 2929 + + XXBLENDVH = 2930 + + XXBLENDVW = 2931 + + XXBRD = 2932 + + XXBRH = 2933 + + XXBRQ = 2934 + + XXBRW = 2935 + + XXEVAL = 2936 + + XXEXTRACTUW = 2937 + + XXGENPCVBM = 2938 + + XXGENPCVDM = 2939 + + XXGENPCVHM = 2940 + + XXGENPCVWM = 2941 + + XXGFMUL128 = 2942 + + XXINSERTW = 2943 + + XXLAND = 2944 + + XXLANDC = 2945 + + XXLEQV = 2946 + + XXLEQVOnes = 2947 + + XXLNAND = 2948 + + XXLNOR = 2949 + + XXLOR = 2950 + + XXLORC = 2951 + + XXLORf = 2952 + + XXLXOR = 2953 + + XXLXORdpz = 2954 + + XXLXORspz = 2955 + + XXLXORz = 2956 + + XXMFACC = 2957 + + XXMFACCW = 2958 + + XXMRGHW = 2959 + + XXMRGLW = 2960 + + XXMTACC = 2961 + + XXMTACCW = 2962 + + XXMULMUL = 2963 + + XXMULMULHIADD = 2964 + + XXMULMULLOADD = 2965 + + XXPERM = 2966 + + XXPERMDI = 2967 + + XXPERMDIs = 2968 + + XXPERMR = 2969 + + XXPERMX = 2970 + + XXSEL = 2971 + + XXSETACCZ = 2972 + + XXSLDWI = 2973 + + XXSLDWIs = 2974 + + XXSPLTI32DX = 2975 + + XXSPLTIB = 2976 + + XXSPLTIDP = 2977 + + XXSPLTIW = 2978 + + XXSPLTW = 2979 + + XXSPLTWs = 2980 + + XXSSUMUDM = 2981 + + XXSSUMUDMC = 2982 + + XXSSUMUDMCEXT = 2983 + + gBC = 2984 + + gBCA = 2985 + + gBCAat = 2986 + + gBCCTR = 2987 + + gBCCTRL = 2988 + + gBCL = 2989 + + gBCLA = 2990 + + gBCLAat = 2991 + + gBCLR = 2992 + + gBCLRL = 2993 + + gBCLat = 2994 + + gBCat = 2995 + + INSTRUCTION_LIST_END = 2996 + +class REG(enum.Enum): + NoRegister = 0 + + BP = 1 + + CARRY = 2 + + CTR = 3 + + FP = 4 + + LR = 5 + + RM = 6 + + SPEFSCR = 7 + + VRSAVE = 8 + + XER = 9 + + ZERO = 10 + + ACC0 = 11 + + ACC1 = 12 + + ACC2 = 13 + + ACC3 = 14 + + ACC4 = 15 + + ACC5 = 16 + + ACC6 = 17 + + ACC7 = 18 + + BP8 = 19 + + CR0 = 20 + + CR1 = 21 + + CR2 = 22 + + CR3 = 23 + + CR4 = 24 + + CR5 = 25 + + CR6 = 26 + + CR7 = 27 + + CTR8 = 28 + + DMR0 = 29 + + DMR1 = 30 + + DMR2 = 31 + + DMR3 = 32 + + DMR4 = 33 + + DMR5 = 34 + + DMR6 = 35 + + DMR7 = 36 + + DMRROW0 = 37 + + DMRROW1 = 38 + + DMRROW2 = 39 + + DMRROW3 = 40 + + DMRROW4 = 41 + + DMRROW5 = 42 + + DMRROW6 = 43 + + DMRROW7 = 44 + + DMRROW8 = 45 + + DMRROW9 = 46 + + DMRROW10 = 47 + + DMRROW11 = 48 + + DMRROW12 = 49 + + DMRROW13 = 50 + + DMRROW14 = 51 + + DMRROW15 = 52 + + DMRROW16 = 53 + + DMRROW17 = 54 + + DMRROW18 = 55 + + DMRROW19 = 56 + + DMRROW20 = 57 + + DMRROW21 = 58 + + DMRROW22 = 59 + + DMRROW23 = 60 + + DMRROW24 = 61 + + DMRROW25 = 62 + + DMRROW26 = 63 + + DMRROW27 = 64 + + DMRROW28 = 65 + + DMRROW29 = 66 + + DMRROW30 = 67 + + DMRROW31 = 68 + + DMRROW32 = 69 + + DMRROW33 = 70 + + DMRROW34 = 71 + + DMRROW35 = 72 + + DMRROW36 = 73 + + DMRROW37 = 74 + + DMRROW38 = 75 + + DMRROW39 = 76 + + DMRROW40 = 77 + + DMRROW41 = 78 + + DMRROW42 = 79 + + DMRROW43 = 80 + + DMRROW44 = 81 + + DMRROW45 = 82 + + DMRROW46 = 83 + + DMRROW47 = 84 + + DMRROW48 = 85 + + DMRROW49 = 86 + + DMRROW50 = 87 + + DMRROW51 = 88 + + DMRROW52 = 89 + + DMRROW53 = 90 + + DMRROW54 = 91 + + DMRROW55 = 92 + + DMRROW56 = 93 + + DMRROW57 = 94 + + DMRROW58 = 95 + + DMRROW59 = 96 + + DMRROW60 = 97 + + DMRROW61 = 98 + + DMRROW62 = 99 + + DMRROW63 = 100 + + DMRROWp0 = 101 + + DMRROWp1 = 102 + + DMRROWp2 = 103 + + DMRROWp3 = 104 + + DMRROWp4 = 105 + + DMRROWp5 = 106 + + DMRROWp6 = 107 + + DMRROWp7 = 108 + + DMRROWp8 = 109 + + DMRROWp9 = 110 + + DMRROWp10 = 111 + + DMRROWp11 = 112 + + DMRROWp12 = 113 + + DMRROWp13 = 114 + + DMRROWp14 = 115 + + DMRROWp15 = 116 + + DMRROWp16 = 117 + + DMRROWp17 = 118 + + DMRROWp18 = 119 + + DMRROWp19 = 120 + + DMRROWp20 = 121 + + DMRROWp21 = 122 + + DMRROWp22 = 123 + + DMRROWp23 = 124 + + DMRROWp24 = 125 + + DMRROWp25 = 126 + + DMRROWp26 = 127 + + DMRROWp27 = 128 + + DMRROWp28 = 129 + + DMRROWp29 = 130 + + DMRROWp30 = 131 + + DMRROWp31 = 132 + + DMRp0 = 133 + + DMRp1 = 134 + + DMRp2 = 135 + + DMRp3 = 136 + + F0 = 137 + + F1 = 138 + + F2 = 139 + + F3 = 140 + + F4 = 141 + + F5 = 142 + + F6 = 143 + + F7 = 144 + + F8 = 145 + + F9 = 146 + + F10 = 147 + + F11 = 148 + + F12 = 149 + + F13 = 150 + + F14 = 151 + + F15 = 152 + + F16 = 153 + + F17 = 154 + + F18 = 155 + + F19 = 156 + + F20 = 157 + + F21 = 158 + + F22 = 159 + + F23 = 160 + + F24 = 161 + + F25 = 162 + + F26 = 163 + + F27 = 164 + + F28 = 165 + + F29 = 166 + + F30 = 167 + + F31 = 168 + + FH0 = 169 + + FH1 = 170 + + FH2 = 171 + + FH3 = 172 + + FH4 = 173 + + FH5 = 174 + + FH6 = 175 + + FH7 = 176 + + FH8 = 177 + + FH9 = 178 + + FH10 = 179 + + FH11 = 180 + + FH12 = 181 + + FH13 = 182 + + FH14 = 183 + + FH15 = 184 + + FH16 = 185 + + FH17 = 186 + + FH18 = 187 + + FH19 = 188 + + FH20 = 189 + + FH21 = 190 + + FH22 = 191 + + FH23 = 192 + + FH24 = 193 + + FH25 = 194 + + FH26 = 195 + + FH27 = 196 + + FH28 = 197 + + FH29 = 198 + + FH30 = 199 + + FH31 = 200 + + FP8 = 201 + + Fpair0 = 202 + + Fpair2 = 203 + + Fpair4 = 204 + + Fpair6 = 205 + + Fpair8 = 206 + + Fpair10 = 207 + + Fpair12 = 208 + + Fpair14 = 209 + + Fpair16 = 210 + + Fpair18 = 211 + + Fpair20 = 212 + + Fpair22 = 213 + + Fpair24 = 214 + + Fpair26 = 215 + + Fpair28 = 216 + + Fpair30 = 217 + + H0 = 218 + + H1 = 219 + + H2 = 220 + + H3 = 221 + + H4 = 222 + + H5 = 223 + + H6 = 224 + + H7 = 225 + + H8 = 226 + + H9 = 227 + + H10 = 228 + + H11 = 229 + + H12 = 230 + + H13 = 231 + + H14 = 232 + + H15 = 233 + + H16 = 234 + + H17 = 235 + + H18 = 236 + + H19 = 237 + + H20 = 238 + + H21 = 239 + + H22 = 240 + + H23 = 241 + + H24 = 242 + + H25 = 243 + + H26 = 244 + + H27 = 245 + + H28 = 246 + + H29 = 247 + + H30 = 248 + + H31 = 249 + + LR8 = 250 + + R0 = 251 + + R1 = 252 + + R2 = 253 + + R3 = 254 + + R4 = 255 + + R5 = 256 + + R6 = 257 + + R7 = 258 + + R8 = 259 + + R9 = 260 + + R10 = 261 + + R11 = 262 + + R12 = 263 + + R13 = 264 + + R14 = 265 + + R15 = 266 + + R16 = 267 + + R17 = 268 + + R18 = 269 + + R19 = 270 + + R20 = 271 + + R21 = 272 + + R22 = 273 + + R23 = 274 + + R24 = 275 + + R25 = 276 + + R26 = 277 + + R27 = 278 + + R28 = 279 + + R29 = 280 + + R30 = 281 + + R31 = 282 + + S0 = 283 + + S1 = 284 + + S2 = 285 + + S3 = 286 + + S4 = 287 + + S5 = 288 + + S6 = 289 + + S7 = 290 + + S8 = 291 + + S9 = 292 + + S10 = 293 + + S11 = 294 + + S12 = 295 + + S13 = 296 + + S14 = 297 + + S15 = 298 + + S16 = 299 + + S17 = 300 + + S18 = 301 + + S19 = 302 + + S20 = 303 + + S21 = 304 + + S22 = 305 + + S23 = 306 + + S24 = 307 + + S25 = 308 + + S26 = 309 + + S27 = 310 + + S28 = 311 + + S29 = 312 + + S30 = 313 + + S31 = 314 + + UACC0 = 315 + + UACC1 = 316 + + UACC2 = 317 + + UACC3 = 318 + + UACC4 = 319 + + UACC5 = 320 + + UACC6 = 321 + + UACC7 = 322 + + V0 = 323 + + V1 = 324 + + V2 = 325 + + V3 = 326 + + V4 = 327 + + V5 = 328 + + V6 = 329 + + V7 = 330 + + V8 = 331 + + V9 = 332 + + V10 = 333 + + V11 = 334 + + V12 = 335 + + V13 = 336 + + V14 = 337 + + V15 = 338 + + V16 = 339 + + V17 = 340 + + V18 = 341 + + V19 = 342 + + V20 = 343 + + V21 = 344 + + V22 = 345 + + V23 = 346 + + V24 = 347 + + V25 = 348 + + V26 = 349 + + V27 = 350 + + V28 = 351 + + V29 = 352 + + V30 = 353 + + V31 = 354 + + VF0 = 355 + + VF1 = 356 + + VF2 = 357 + + VF3 = 358 + + VF4 = 359 + + VF5 = 360 + + VF6 = 361 + + VF7 = 362 + + VF8 = 363 + + VF9 = 364 + + VF10 = 365 + + VF11 = 366 + + VF12 = 367 + + VF13 = 368 + + VF14 = 369 + + VF15 = 370 + + VF16 = 371 + + VF17 = 372 + + VF18 = 373 + + VF19 = 374 + + VF20 = 375 + + VF21 = 376 + + VF22 = 377 + + VF23 = 378 + + VF24 = 379 + + VF25 = 380 + + VF26 = 381 + + VF27 = 382 + + VF28 = 383 + + VF29 = 384 + + VF30 = 385 + + VF31 = 386 + + VFH0 = 387 + + VFH1 = 388 + + VFH2 = 389 + + VFH3 = 390 + + VFH4 = 391 + + VFH5 = 392 + + VFH6 = 393 + + VFH7 = 394 + + VFH8 = 395 + + VFH9 = 396 + + VFH10 = 397 + + VFH11 = 398 + + VFH12 = 399 + + VFH13 = 400 + + VFH14 = 401 + + VFH15 = 402 + + VFH16 = 403 + + VFH17 = 404 + + VFH18 = 405 + + VFH19 = 406 + + VFH20 = 407 + + VFH21 = 408 + + VFH22 = 409 + + VFH23 = 410 + + VFH24 = 411 + + VFH25 = 412 + + VFH26 = 413 + + VFH27 = 414 + + VFH28 = 415 + + VFH29 = 416 + + VFH30 = 417 + + VFH31 = 418 + + VSL0 = 419 + + VSL1 = 420 + + VSL2 = 421 + + VSL3 = 422 + + VSL4 = 423 + + VSL5 = 424 + + VSL6 = 425 + + VSL7 = 426 + + VSL8 = 427 + + VSL9 = 428 + + VSL10 = 429 + + VSL11 = 430 + + VSL12 = 431 + + VSL13 = 432 + + VSL14 = 433 + + VSL15 = 434 + + VSL16 = 435 + + VSL17 = 436 + + VSL18 = 437 + + VSL19 = 438 + + VSL20 = 439 + + VSL21 = 440 + + VSL22 = 441 + + VSL23 = 442 + + VSL24 = 443 + + VSL25 = 444 + + VSL26 = 445 + + VSL27 = 446 + + VSL28 = 447 + + VSL29 = 448 + + VSL30 = 449 + + VSL31 = 450 + + VSRp0 = 451 + + VSRp1 = 452 + + VSRp2 = 453 + + VSRp3 = 454 + + VSRp4 = 455 + + VSRp5 = 456 + + VSRp6 = 457 + + VSRp7 = 458 + + VSRp8 = 459 + + VSRp9 = 460 + + VSRp10 = 461 + + VSRp11 = 462 + + VSRp12 = 463 + + VSRp13 = 464 + + VSRp14 = 465 + + VSRp15 = 466 + + VSRp16 = 467 + + VSRp17 = 468 + + VSRp18 = 469 + + VSRp19 = 470 + + VSRp20 = 471 + + VSRp21 = 472 + + VSRp22 = 473 + + VSRp23 = 474 + + VSRp24 = 475 + + VSRp25 = 476 + + VSRp26 = 477 + + VSRp27 = 478 + + VSRp28 = 479 + + VSRp29 = 480 + + VSRp30 = 481 + + VSRp31 = 482 + + VSX32 = 483 + + VSX33 = 484 + + VSX34 = 485 + + VSX35 = 486 + + VSX36 = 487 + + VSX37 = 488 + + VSX38 = 489 + + VSX39 = 490 + + VSX40 = 491 + + VSX41 = 492 + + VSX42 = 493 + + VSX43 = 494 + + VSX44 = 495 + + VSX45 = 496 + + VSX46 = 497 + + VSX47 = 498 + + VSX48 = 499 + + VSX49 = 500 + + VSX50 = 501 + + VSX51 = 502 + + VSX52 = 503 + + VSX53 = 504 + + VSX54 = 505 + + VSX55 = 506 + + VSX56 = 507 + + VSX57 = 508 + + VSX58 = 509 + + VSX59 = 510 + + VSX60 = 511 + + VSX61 = 512 + + VSX62 = 513 + + VSX63 = 514 + + WACC0 = 515 + + WACC1 = 516 + + WACC2 = 517 + + WACC3 = 518 + + WACC4 = 519 + + WACC5 = 520 + + WACC6 = 521 + + WACC7 = 522 + + WACC_HI0 = 523 + + WACC_HI1 = 524 + + WACC_HI2 = 525 + + WACC_HI3 = 526 + + WACC_HI4 = 527 + + WACC_HI5 = 528 + + WACC_HI6 = 529 + + WACC_HI7 = 530 + + X0 = 531 + + X1 = 532 + + X2 = 533 + + X3 = 534 + + X4 = 535 + + X5 = 536 + + X6 = 537 + + X7 = 538 + + X8 = 539 + + X9 = 540 + + X10 = 541 + + X11 = 542 + + X12 = 543 + + X13 = 544 + + X14 = 545 + + X15 = 546 + + X16 = 547 + + X17 = 548 + + X18 = 549 + + X19 = 550 + + X20 = 551 + + X21 = 552 + + X22 = 553 + + X23 = 554 + + X24 = 555 + + X25 = 556 + + X26 = 557 + + X27 = 558 + + X28 = 559 + + X29 = 560 + + X30 = 561 + + X31 = 562 + + ZERO8 = 563 + + CR0EQ = 564 + + CR1EQ = 565 + + CR2EQ = 566 + + CR3EQ = 567 + + CR4EQ = 568 + + CR5EQ = 569 + + CR6EQ = 570 + + CR7EQ = 571 + + CR0GT = 572 + + CR1GT = 573 + + CR2GT = 574 + + CR3GT = 575 + + CR4GT = 576 + + CR5GT = 577 + + CR6GT = 578 + + CR7GT = 579 + + CR0LT = 580 + + CR1LT = 581 + + CR2LT = 582 + + CR3LT = 583 + + CR4LT = 584 + + CR5LT = 585 + + CR6LT = 586 + + CR7LT = 587 + + CR0UN = 588 + + CR1UN = 589 + + CR2UN = 590 + + CR3UN = 591 + + CR4UN = 592 + + CR5UN = 593 + + CR6UN = 594 + + CR7UN = 595 + + G8p0 = 596 + + G8p1 = 597 + + G8p2 = 598 + + G8p3 = 599 + + G8p4 = 600 + + G8p5 = 601 + + G8p6 = 602 + + G8p7 = 603 + + G8p8 = 604 + + G8p9 = 605 + + G8p10 = 606 + + G8p11 = 607 + + G8p12 = 608 + + G8p13 = 609 + + G8p14 = 610 + + G8p15 = 611 + + NUM_TARGET_REGS = 612 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/powerpc/operands.pyi b/vendor/lief/api/python/lief/assembly/powerpc/operands.pyi new file mode 100644 index 0000000..1bded32 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/powerpc/operands.pyi @@ -0,0 +1,33 @@ +from typing import Optional, Union + +import lief.assembly.powerpc + +import lief.assembly.powerpc + + +class Immediate(lief.assembly.powerpc.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.powerpc.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> lief.assembly.powerpc.REG: ... + +class Memory(lief.assembly.powerpc.Operand): + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.powerpc.REG: ... + + @property + def offset(self) -> Optional[Union[lief.assembly.powerpc.REG, int]]: ... + +class PCRelative(lief.assembly.powerpc.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/assembly/riscv/__init__.pyi b/vendor/lief/api/python/lief/assembly/riscv/__init__.pyi new file mode 100644 index 0000000..797e8ce --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/riscv/__init__.pyi @@ -0,0 +1,34645 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.riscv import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ADJCALLSTACKDOWN = 322 + + ADJCALLSTACKUP = 323 + + BuildPairF64Pseudo = 324 + + ClearFCSR = 325 + + ClearFCSRImm = 326 + + G_CLZW = 327 + + G_CTZW = 328 + + G_DIVUW = 329 + + G_DIVW = 330 + + G_FCLASS = 331 + + G_FCVT_WU_RV64 = 332 + + G_FCVT_W_RV64 = 333 + + G_READ_VLENB = 334 + + G_REMUW = 335 + + G_ROLW = 336 + + G_RORW = 337 + + G_SLLW = 338 + + G_SPLAT_VECTOR_SPLIT_I64_VL = 339 + + G_SRAW = 340 + + G_SRLW = 341 + + G_VMCLR_VL = 342 + + G_VMSET_VL = 343 + + G_VMV_V_V_VL = 344 + + G_VSLIDEDOWN_VL = 345 + + G_VSLIDEUP_VL = 346 + + HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 347 + + KCFI_CHECK = 348 + + PROBED_STACKALLOC = 349 + + PROBED_STACKALLOC_DYN = 350 + + PROBED_STACKALLOC_RVV = 351 + + PseudoAddTPRel = 352 + + PseudoAtomicLoadAdd32 = 353 + + PseudoAtomicLoadAdd64 = 354 + + PseudoAtomicLoadAnd32 = 355 + + PseudoAtomicLoadAnd64 = 356 + + PseudoAtomicLoadMax32 = 357 + + PseudoAtomicLoadMax64 = 358 + + PseudoAtomicLoadMin32 = 359 + + PseudoAtomicLoadMin64 = 360 + + PseudoAtomicLoadNand32 = 361 + + PseudoAtomicLoadNand64 = 362 + + PseudoAtomicLoadOr32 = 363 + + PseudoAtomicLoadOr64 = 364 + + PseudoAtomicLoadSub32 = 365 + + PseudoAtomicLoadSub64 = 366 + + PseudoAtomicLoadUMax32 = 367 + + PseudoAtomicLoadUMax64 = 368 + + PseudoAtomicLoadUMin32 = 369 + + PseudoAtomicLoadUMin64 = 370 + + PseudoAtomicLoadXor32 = 371 + + PseudoAtomicLoadXor64 = 372 + + PseudoAtomicSwap32 = 373 + + PseudoAtomicSwap64 = 374 + + PseudoBR = 375 + + PseudoBRIND = 376 + + PseudoBRINDNonX7 = 377 + + PseudoBRINDX7 = 378 + + PseudoCALL = 379 + + PseudoCALLIndirect = 380 + + PseudoCALLIndirectNonX7 = 381 + + PseudoCALLIndirectX7 = 382 + + PseudoCALLReg = 383 + + PseudoCCADD = 384 + + PseudoCCADDI = 385 + + PseudoCCADDIW = 386 + + PseudoCCADDW = 387 + + PseudoCCAND = 388 + + PseudoCCANDI = 389 + + PseudoCCANDN = 390 + + PseudoCCLB = 391 + + PseudoCCLBU = 392 + + PseudoCCLD = 393 + + PseudoCCLH = 394 + + PseudoCCLHU = 395 + + PseudoCCLUI = 396 + + PseudoCCLW = 397 + + PseudoCCLWU = 398 + + PseudoCCMAX = 399 + + PseudoCCMAXU = 400 + + PseudoCCMIN = 401 + + PseudoCCMINU = 402 + + PseudoCCMOVGPR = 403 + + PseudoCCMOVGPRNoX0 = 404 + + PseudoCCMUL = 405 + + PseudoCCNDS_BFOS = 406 + + PseudoCCNDS_BFOZ = 407 + + PseudoCCOR = 408 + + PseudoCCORI = 409 + + PseudoCCORN = 410 + + PseudoCCQC_E_LB = 411 + + PseudoCCQC_E_LBU = 412 + + PseudoCCQC_E_LH = 413 + + PseudoCCQC_E_LHU = 414 + + PseudoCCQC_E_LI = 415 + + PseudoCCQC_E_LW = 416 + + PseudoCCQC_LI = 417 + + PseudoCCSLL = 418 + + PseudoCCSLLI = 419 + + PseudoCCSLLIW = 420 + + PseudoCCSLLW = 421 + + PseudoCCSRA = 422 + + PseudoCCSRAI = 423 + + PseudoCCSRAIW = 424 + + PseudoCCSRAW = 425 + + PseudoCCSRL = 426 + + PseudoCCSRLI = 427 + + PseudoCCSRLIW = 428 + + PseudoCCSRLW = 429 + + PseudoCCSUB = 430 + + PseudoCCSUBW = 431 + + PseudoCCXNOR = 432 + + PseudoCCXOR = 433 + + PseudoCCXORI = 434 + + PseudoCV_ELW = 435 + + PseudoC_ADDI_NOP = 436 + + PseudoCmpXchg32 = 437 + + PseudoCmpXchg64 = 438 + + PseudoFLD = 439 + + PseudoFLH = 440 + + PseudoFLQ = 441 + + PseudoFLW = 442 + + PseudoFROUND_D = 443 + + PseudoFROUND_D_IN32X = 444 + + PseudoFROUND_D_INX = 445 + + PseudoFROUND_H = 446 + + PseudoFROUND_H_INX = 447 + + PseudoFROUND_S = 448 + + PseudoFROUND_S_INX = 449 + + PseudoFSD = 450 + + PseudoFSH = 451 + + PseudoFSQ = 452 + + PseudoFSW = 453 + + PseudoJump = 454 + + PseudoLA = 455 + + PseudoLAImm = 456 + + PseudoLA_TLSDESC = 457 + + PseudoLA_TLS_GD = 458 + + PseudoLA_TLS_IE = 459 + + PseudoLB = 460 + + PseudoLBU = 461 + + PseudoLD = 462 + + PseudoLD_RV32 = 463 + + PseudoLD_RV32_OPT = 464 + + PseudoLGA = 465 + + PseudoLH = 466 + + PseudoLHU = 467 + + PseudoLI = 468 + + PseudoLLA = 469 + + PseudoLLAImm = 470 + + PseudoLW = 471 + + PseudoLWU = 472 + + PseudoLongBEQ = 473 + + PseudoLongBEQI = 474 + + PseudoLongBGE = 475 + + PseudoLongBGEU = 476 + + PseudoLongBLT = 477 + + PseudoLongBLTU = 478 + + PseudoLongBNE = 479 + + PseudoLongBNEI = 480 + + PseudoLongQC_BEQI = 481 + + PseudoLongQC_BGEI = 482 + + PseudoLongQC_BGEUI = 483 + + PseudoLongQC_BLTI = 484 + + PseudoLongQC_BLTUI = 485 + + PseudoLongQC_BNEI = 486 + + PseudoLongQC_E_BEQI = 487 + + PseudoLongQC_E_BGEI = 488 + + PseudoLongQC_E_BGEUI = 489 + + PseudoLongQC_E_BLTI = 490 + + PseudoLongQC_E_BLTUI = 491 + + PseudoLongQC_E_BNEI = 492 + + PseudoMOP_C_SSPUSH = 493 + + PseudoMOP_SSPOPCHK = 494 + + PseudoMOP_SSPUSH = 495 + + PseudoMV_FPR16INX = 496 + + PseudoMV_FPR32INX = 497 + + PseudoMaskedAtomicLoadAdd32 = 498 + + PseudoMaskedAtomicLoadMax32 = 499 + + PseudoMaskedAtomicLoadMin32 = 500 + + PseudoMaskedAtomicLoadNand32 = 501 + + PseudoMaskedAtomicLoadSub32 = 502 + + PseudoMaskedAtomicLoadUMax32 = 503 + + PseudoMaskedAtomicLoadUMin32 = 504 + + PseudoMaskedAtomicSwap32 = 505 + + PseudoMaskedCmpXchg32 = 506 + + PseudoMovAddr = 507 + + PseudoMovImm = 508 + + PseudoNDS_VD4DOTSU_VV_M1 = 509 + + PseudoNDS_VD4DOTSU_VV_M1_MASK = 510 + + PseudoNDS_VD4DOTSU_VV_M2 = 511 + + PseudoNDS_VD4DOTSU_VV_M2_MASK = 512 + + PseudoNDS_VD4DOTSU_VV_M4 = 513 + + PseudoNDS_VD4DOTSU_VV_M4_MASK = 514 + + PseudoNDS_VD4DOTSU_VV_M8 = 515 + + PseudoNDS_VD4DOTSU_VV_M8_MASK = 516 + + PseudoNDS_VD4DOTSU_VV_MF2 = 517 + + PseudoNDS_VD4DOTSU_VV_MF2_MASK = 518 + + PseudoNDS_VD4DOTS_VV_M1 = 519 + + PseudoNDS_VD4DOTS_VV_M1_MASK = 520 + + PseudoNDS_VD4DOTS_VV_M2 = 521 + + PseudoNDS_VD4DOTS_VV_M2_MASK = 522 + + PseudoNDS_VD4DOTS_VV_M4 = 523 + + PseudoNDS_VD4DOTS_VV_M4_MASK = 524 + + PseudoNDS_VD4DOTS_VV_M8 = 525 + + PseudoNDS_VD4DOTS_VV_M8_MASK = 526 + + PseudoNDS_VD4DOTS_VV_MF2 = 527 + + PseudoNDS_VD4DOTS_VV_MF2_MASK = 528 + + PseudoNDS_VD4DOTU_VV_M1 = 529 + + PseudoNDS_VD4DOTU_VV_M1_MASK = 530 + + PseudoNDS_VD4DOTU_VV_M2 = 531 + + PseudoNDS_VD4DOTU_VV_M2_MASK = 532 + + PseudoNDS_VD4DOTU_VV_M4 = 533 + + PseudoNDS_VD4DOTU_VV_M4_MASK = 534 + + PseudoNDS_VD4DOTU_VV_M8 = 535 + + PseudoNDS_VD4DOTU_VV_M8_MASK = 536 + + PseudoNDS_VD4DOTU_VV_MF2 = 537 + + PseudoNDS_VD4DOTU_VV_MF2_MASK = 538 + + PseudoNDS_VFNCVT_BF16_S_M1 = 539 + + PseudoNDS_VFNCVT_BF16_S_M2 = 540 + + PseudoNDS_VFNCVT_BF16_S_M4 = 541 + + PseudoNDS_VFNCVT_BF16_S_MF2 = 542 + + PseudoNDS_VFNCVT_BF16_S_MF4 = 543 + + PseudoNDS_VFPMADB_VFPR16_M1 = 544 + + PseudoNDS_VFPMADB_VFPR16_M1_MASK = 545 + + PseudoNDS_VFPMADB_VFPR16_M2 = 546 + + PseudoNDS_VFPMADB_VFPR16_M2_MASK = 547 + + PseudoNDS_VFPMADB_VFPR16_M4 = 548 + + PseudoNDS_VFPMADB_VFPR16_M4_MASK = 549 + + PseudoNDS_VFPMADB_VFPR16_M8 = 550 + + PseudoNDS_VFPMADB_VFPR16_M8_MASK = 551 + + PseudoNDS_VFPMADB_VFPR16_MF2 = 552 + + PseudoNDS_VFPMADB_VFPR16_MF2_MASK = 553 + + PseudoNDS_VFPMADB_VFPR16_MF4 = 554 + + PseudoNDS_VFPMADB_VFPR16_MF4_MASK = 555 + + PseudoNDS_VFPMADT_VFPR16_M1 = 556 + + PseudoNDS_VFPMADT_VFPR16_M1_MASK = 557 + + PseudoNDS_VFPMADT_VFPR16_M2 = 558 + + PseudoNDS_VFPMADT_VFPR16_M2_MASK = 559 + + PseudoNDS_VFPMADT_VFPR16_M4 = 560 + + PseudoNDS_VFPMADT_VFPR16_M4_MASK = 561 + + PseudoNDS_VFPMADT_VFPR16_M8 = 562 + + PseudoNDS_VFPMADT_VFPR16_M8_MASK = 563 + + PseudoNDS_VFPMADT_VFPR16_MF2 = 564 + + PseudoNDS_VFPMADT_VFPR16_MF2_MASK = 565 + + PseudoNDS_VFPMADT_VFPR16_MF4 = 566 + + PseudoNDS_VFPMADT_VFPR16_MF4_MASK = 567 + + PseudoNDS_VFWCVT_S_BF16_M1 = 568 + + PseudoNDS_VFWCVT_S_BF16_M2 = 569 + + PseudoNDS_VFWCVT_S_BF16_M4 = 570 + + PseudoNDS_VFWCVT_S_BF16_MF2 = 571 + + PseudoNDS_VFWCVT_S_BF16_MF4 = 572 + + PseudoNDS_VLN8_V_M1 = 573 + + PseudoNDS_VLN8_V_M1_MASK = 574 + + PseudoNDS_VLN8_V_M2 = 575 + + PseudoNDS_VLN8_V_M2_MASK = 576 + + PseudoNDS_VLN8_V_M4 = 577 + + PseudoNDS_VLN8_V_M4_MASK = 578 + + PseudoNDS_VLN8_V_M8 = 579 + + PseudoNDS_VLN8_V_M8_MASK = 580 + + PseudoNDS_VLN8_V_MF2 = 581 + + PseudoNDS_VLN8_V_MF2_MASK = 582 + + PseudoNDS_VLN8_V_MF4 = 583 + + PseudoNDS_VLN8_V_MF4_MASK = 584 + + PseudoNDS_VLN8_V_MF8 = 585 + + PseudoNDS_VLN8_V_MF8_MASK = 586 + + PseudoNDS_VLNU8_V_M1 = 587 + + PseudoNDS_VLNU8_V_M1_MASK = 588 + + PseudoNDS_VLNU8_V_M2 = 589 + + PseudoNDS_VLNU8_V_M2_MASK = 590 + + PseudoNDS_VLNU8_V_M4 = 591 + + PseudoNDS_VLNU8_V_M4_MASK = 592 + + PseudoNDS_VLNU8_V_M8 = 593 + + PseudoNDS_VLNU8_V_M8_MASK = 594 + + PseudoNDS_VLNU8_V_MF2 = 595 + + PseudoNDS_VLNU8_V_MF2_MASK = 596 + + PseudoNDS_VLNU8_V_MF4 = 597 + + PseudoNDS_VLNU8_V_MF4_MASK = 598 + + PseudoNDS_VLNU8_V_MF8 = 599 + + PseudoNDS_VLNU8_V_MF8_MASK = 600 + + PseudoQC_E_LB = 601 + + PseudoQC_E_LBU = 602 + + PseudoQC_E_LH = 603 + + PseudoQC_E_LHU = 604 + + PseudoQC_E_LW = 605 + + PseudoQC_E_SB = 606 + + PseudoQC_E_SH = 607 + + PseudoQC_E_SW = 608 + + PseudoQuietFLE_D = 609 + + PseudoQuietFLE_D_IN32X = 610 + + PseudoQuietFLE_D_INX = 611 + + PseudoQuietFLE_H = 612 + + PseudoQuietFLE_H_INX = 613 + + PseudoQuietFLE_S = 614 + + PseudoQuietFLE_S_INX = 615 + + PseudoQuietFLT_D = 616 + + PseudoQuietFLT_D_IN32X = 617 + + PseudoQuietFLT_D_INX = 618 + + PseudoQuietFLT_H = 619 + + PseudoQuietFLT_H_INX = 620 + + PseudoQuietFLT_S = 621 + + PseudoQuietFLT_S_INX = 622 + + PseudoRET = 623 + + PseudoRI_VEXTRACT_M1 = 624 + + PseudoRI_VEXTRACT_M2 = 625 + + PseudoRI_VEXTRACT_M4 = 626 + + PseudoRI_VEXTRACT_M8 = 627 + + PseudoRI_VEXTRACT_MF2 = 628 + + PseudoRI_VEXTRACT_MF4 = 629 + + PseudoRI_VEXTRACT_MF8 = 630 + + PseudoRI_VINSERT_M1 = 631 + + PseudoRI_VINSERT_M2 = 632 + + PseudoRI_VINSERT_M4 = 633 + + PseudoRI_VINSERT_M8 = 634 + + PseudoRI_VINSERT_MF2 = 635 + + PseudoRI_VINSERT_MF4 = 636 + + PseudoRI_VINSERT_MF8 = 637 + + PseudoRI_VUNZIP2A_VV_M1 = 638 + + PseudoRI_VUNZIP2A_VV_M1_MASK = 639 + + PseudoRI_VUNZIP2A_VV_M2 = 640 + + PseudoRI_VUNZIP2A_VV_M2_MASK = 641 + + PseudoRI_VUNZIP2A_VV_M4 = 642 + + PseudoRI_VUNZIP2A_VV_M4_MASK = 643 + + PseudoRI_VUNZIP2A_VV_M8 = 644 + + PseudoRI_VUNZIP2A_VV_M8_MASK = 645 + + PseudoRI_VUNZIP2A_VV_MF2 = 646 + + PseudoRI_VUNZIP2A_VV_MF2_MASK = 647 + + PseudoRI_VUNZIP2A_VV_MF4 = 648 + + PseudoRI_VUNZIP2A_VV_MF4_MASK = 649 + + PseudoRI_VUNZIP2A_VV_MF8 = 650 + + PseudoRI_VUNZIP2A_VV_MF8_MASK = 651 + + PseudoRI_VUNZIP2B_VV_M1 = 652 + + PseudoRI_VUNZIP2B_VV_M1_MASK = 653 + + PseudoRI_VUNZIP2B_VV_M2 = 654 + + PseudoRI_VUNZIP2B_VV_M2_MASK = 655 + + PseudoRI_VUNZIP2B_VV_M4 = 656 + + PseudoRI_VUNZIP2B_VV_M4_MASK = 657 + + PseudoRI_VUNZIP2B_VV_M8 = 658 + + PseudoRI_VUNZIP2B_VV_M8_MASK = 659 + + PseudoRI_VUNZIP2B_VV_MF2 = 660 + + PseudoRI_VUNZIP2B_VV_MF2_MASK = 661 + + PseudoRI_VUNZIP2B_VV_MF4 = 662 + + PseudoRI_VUNZIP2B_VV_MF4_MASK = 663 + + PseudoRI_VUNZIP2B_VV_MF8 = 664 + + PseudoRI_VUNZIP2B_VV_MF8_MASK = 665 + + PseudoRI_VZIP2A_VV_M1 = 666 + + PseudoRI_VZIP2A_VV_M1_MASK = 667 + + PseudoRI_VZIP2A_VV_M2 = 668 + + PseudoRI_VZIP2A_VV_M2_MASK = 669 + + PseudoRI_VZIP2A_VV_M4 = 670 + + PseudoRI_VZIP2A_VV_M4_MASK = 671 + + PseudoRI_VZIP2A_VV_M8 = 672 + + PseudoRI_VZIP2A_VV_M8_MASK = 673 + + PseudoRI_VZIP2A_VV_MF2 = 674 + + PseudoRI_VZIP2A_VV_MF2_MASK = 675 + + PseudoRI_VZIP2A_VV_MF4 = 676 + + PseudoRI_VZIP2A_VV_MF4_MASK = 677 + + PseudoRI_VZIP2A_VV_MF8 = 678 + + PseudoRI_VZIP2A_VV_MF8_MASK = 679 + + PseudoRI_VZIP2B_VV_M1 = 680 + + PseudoRI_VZIP2B_VV_M1_MASK = 681 + + PseudoRI_VZIP2B_VV_M2 = 682 + + PseudoRI_VZIP2B_VV_M2_MASK = 683 + + PseudoRI_VZIP2B_VV_M4 = 684 + + PseudoRI_VZIP2B_VV_M4_MASK = 685 + + PseudoRI_VZIP2B_VV_M8 = 686 + + PseudoRI_VZIP2B_VV_M8_MASK = 687 + + PseudoRI_VZIP2B_VV_MF2 = 688 + + PseudoRI_VZIP2B_VV_MF2_MASK = 689 + + PseudoRI_VZIP2B_VV_MF4 = 690 + + PseudoRI_VZIP2B_VV_MF4_MASK = 691 + + PseudoRI_VZIP2B_VV_MF8 = 692 + + PseudoRI_VZIP2B_VV_MF8_MASK = 693 + + PseudoRI_VZIPEVEN_VV_M1 = 694 + + PseudoRI_VZIPEVEN_VV_M1_MASK = 695 + + PseudoRI_VZIPEVEN_VV_M2 = 696 + + PseudoRI_VZIPEVEN_VV_M2_MASK = 697 + + PseudoRI_VZIPEVEN_VV_M4 = 698 + + PseudoRI_VZIPEVEN_VV_M4_MASK = 699 + + PseudoRI_VZIPEVEN_VV_M8 = 700 + + PseudoRI_VZIPEVEN_VV_M8_MASK = 701 + + PseudoRI_VZIPEVEN_VV_MF2 = 702 + + PseudoRI_VZIPEVEN_VV_MF2_MASK = 703 + + PseudoRI_VZIPEVEN_VV_MF4 = 704 + + PseudoRI_VZIPEVEN_VV_MF4_MASK = 705 + + PseudoRI_VZIPEVEN_VV_MF8 = 706 + + PseudoRI_VZIPEVEN_VV_MF8_MASK = 707 + + PseudoRI_VZIPODD_VV_M1 = 708 + + PseudoRI_VZIPODD_VV_M1_MASK = 709 + + PseudoRI_VZIPODD_VV_M2 = 710 + + PseudoRI_VZIPODD_VV_M2_MASK = 711 + + PseudoRI_VZIPODD_VV_M4 = 712 + + PseudoRI_VZIPODD_VV_M4_MASK = 713 + + PseudoRI_VZIPODD_VV_M8 = 714 + + PseudoRI_VZIPODD_VV_M8_MASK = 715 + + PseudoRI_VZIPODD_VV_MF2 = 716 + + PseudoRI_VZIPODD_VV_MF2_MASK = 717 + + PseudoRI_VZIPODD_VV_MF4 = 718 + + PseudoRI_VZIPODD_VV_MF4_MASK = 719 + + PseudoRI_VZIPODD_VV_MF8 = 720 + + PseudoRI_VZIPODD_VV_MF8_MASK = 721 + + PseudoRV32ZdinxLD = 722 + + PseudoRV32ZdinxSD = 723 + + PseudoReadVL = 724 + + PseudoReadVLENB = 725 + + PseudoReadVLENBViaVSETVLIX0 = 726 + + PseudoSB = 727 + + PseudoSD = 728 + + PseudoSD_RV32 = 729 + + PseudoSD_RV32_OPT = 730 + + PseudoSEXT_B = 731 + + PseudoSEXT_H = 732 + + PseudoSF_MM_E4M3_E4M3 = 733 + + PseudoSF_MM_E4M3_E5M2 = 734 + + PseudoSF_MM_E5M2_E4M3 = 735 + + PseudoSF_MM_E5M2_E5M2 = 736 + + PseudoSF_MM_F_F = 737 + + PseudoSF_MM_F_F_ALT = 738 + + PseudoSF_MM_S_S = 739 + + PseudoSF_MM_S_U = 740 + + PseudoSF_MM_U_S = 741 + + PseudoSF_MM_U_U = 742 + + PseudoSF_VC_FPR16VV_SE_M1 = 743 + + PseudoSF_VC_FPR16VV_SE_M2 = 744 + + PseudoSF_VC_FPR16VV_SE_M4 = 745 + + PseudoSF_VC_FPR16VV_SE_M8 = 746 + + PseudoSF_VC_FPR16VV_SE_MF2 = 747 + + PseudoSF_VC_FPR16VV_SE_MF4 = 748 + + PseudoSF_VC_FPR16VW_SE_M1 = 749 + + PseudoSF_VC_FPR16VW_SE_M2 = 750 + + PseudoSF_VC_FPR16VW_SE_M4 = 751 + + PseudoSF_VC_FPR16VW_SE_M8 = 752 + + PseudoSF_VC_FPR16VW_SE_MF2 = 753 + + PseudoSF_VC_FPR16VW_SE_MF4 = 754 + + PseudoSF_VC_FPR16V_SE_M1 = 755 + + PseudoSF_VC_FPR16V_SE_M2 = 756 + + PseudoSF_VC_FPR16V_SE_M4 = 757 + + PseudoSF_VC_FPR16V_SE_M8 = 758 + + PseudoSF_VC_FPR16V_SE_MF2 = 759 + + PseudoSF_VC_FPR16V_SE_MF4 = 760 + + PseudoSF_VC_FPR32VV_SE_M1 = 761 + + PseudoSF_VC_FPR32VV_SE_M2 = 762 + + PseudoSF_VC_FPR32VV_SE_M4 = 763 + + PseudoSF_VC_FPR32VV_SE_M8 = 764 + + PseudoSF_VC_FPR32VV_SE_MF2 = 765 + + PseudoSF_VC_FPR32VW_SE_M1 = 766 + + PseudoSF_VC_FPR32VW_SE_M2 = 767 + + PseudoSF_VC_FPR32VW_SE_M4 = 768 + + PseudoSF_VC_FPR32VW_SE_M8 = 769 + + PseudoSF_VC_FPR32VW_SE_MF2 = 770 + + PseudoSF_VC_FPR32V_SE_M1 = 771 + + PseudoSF_VC_FPR32V_SE_M2 = 772 + + PseudoSF_VC_FPR32V_SE_M4 = 773 + + PseudoSF_VC_FPR32V_SE_M8 = 774 + + PseudoSF_VC_FPR32V_SE_MF2 = 775 + + PseudoSF_VC_FPR64VV_SE_M1 = 776 + + PseudoSF_VC_FPR64VV_SE_M2 = 777 + + PseudoSF_VC_FPR64VV_SE_M4 = 778 + + PseudoSF_VC_FPR64VV_SE_M8 = 779 + + PseudoSF_VC_FPR64V_SE_M1 = 780 + + PseudoSF_VC_FPR64V_SE_M2 = 781 + + PseudoSF_VC_FPR64V_SE_M4 = 782 + + PseudoSF_VC_FPR64V_SE_M8 = 783 + + PseudoSF_VC_IVV_SE_M1 = 784 + + PseudoSF_VC_IVV_SE_M2 = 785 + + PseudoSF_VC_IVV_SE_M4 = 786 + + PseudoSF_VC_IVV_SE_M8 = 787 + + PseudoSF_VC_IVV_SE_MF2 = 788 + + PseudoSF_VC_IVV_SE_MF4 = 789 + + PseudoSF_VC_IVV_SE_MF8 = 790 + + PseudoSF_VC_IVW_SE_M1 = 791 + + PseudoSF_VC_IVW_SE_M2 = 792 + + PseudoSF_VC_IVW_SE_M4 = 793 + + PseudoSF_VC_IVW_SE_MF2 = 794 + + PseudoSF_VC_IVW_SE_MF4 = 795 + + PseudoSF_VC_IVW_SE_MF8 = 796 + + PseudoSF_VC_IV_SE_M1 = 797 + + PseudoSF_VC_IV_SE_M2 = 798 + + PseudoSF_VC_IV_SE_M4 = 799 + + PseudoSF_VC_IV_SE_M8 = 800 + + PseudoSF_VC_IV_SE_MF2 = 801 + + PseudoSF_VC_IV_SE_MF4 = 802 + + PseudoSF_VC_IV_SE_MF8 = 803 + + PseudoSF_VC_I_SE_M1 = 804 + + PseudoSF_VC_I_SE_M2 = 805 + + PseudoSF_VC_I_SE_M4 = 806 + + PseudoSF_VC_I_SE_M8 = 807 + + PseudoSF_VC_I_SE_MF2 = 808 + + PseudoSF_VC_I_SE_MF4 = 809 + + PseudoSF_VC_I_SE_MF8 = 810 + + PseudoSF_VC_VVV_SE_M1 = 811 + + PseudoSF_VC_VVV_SE_M2 = 812 + + PseudoSF_VC_VVV_SE_M4 = 813 + + PseudoSF_VC_VVV_SE_M8 = 814 + + PseudoSF_VC_VVV_SE_MF2 = 815 + + PseudoSF_VC_VVV_SE_MF4 = 816 + + PseudoSF_VC_VVV_SE_MF8 = 817 + + PseudoSF_VC_VVW_SE_M1 = 818 + + PseudoSF_VC_VVW_SE_M2 = 819 + + PseudoSF_VC_VVW_SE_M4 = 820 + + PseudoSF_VC_VVW_SE_MF2 = 821 + + PseudoSF_VC_VVW_SE_MF4 = 822 + + PseudoSF_VC_VVW_SE_MF8 = 823 + + PseudoSF_VC_VV_SE_M1 = 824 + + PseudoSF_VC_VV_SE_M2 = 825 + + PseudoSF_VC_VV_SE_M4 = 826 + + PseudoSF_VC_VV_SE_M8 = 827 + + PseudoSF_VC_VV_SE_MF2 = 828 + + PseudoSF_VC_VV_SE_MF4 = 829 + + PseudoSF_VC_VV_SE_MF8 = 830 + + PseudoSF_VC_V_FPR16VV_M1 = 831 + + PseudoSF_VC_V_FPR16VV_M2 = 832 + + PseudoSF_VC_V_FPR16VV_M4 = 833 + + PseudoSF_VC_V_FPR16VV_M8 = 834 + + PseudoSF_VC_V_FPR16VV_MF2 = 835 + + PseudoSF_VC_V_FPR16VV_MF4 = 836 + + PseudoSF_VC_V_FPR16VV_SE_M1 = 837 + + PseudoSF_VC_V_FPR16VV_SE_M2 = 838 + + PseudoSF_VC_V_FPR16VV_SE_M4 = 839 + + PseudoSF_VC_V_FPR16VV_SE_M8 = 840 + + PseudoSF_VC_V_FPR16VV_SE_MF2 = 841 + + PseudoSF_VC_V_FPR16VV_SE_MF4 = 842 + + PseudoSF_VC_V_FPR16VW_M1 = 843 + + PseudoSF_VC_V_FPR16VW_M2 = 844 + + PseudoSF_VC_V_FPR16VW_M4 = 845 + + PseudoSF_VC_V_FPR16VW_M8 = 846 + + PseudoSF_VC_V_FPR16VW_MF2 = 847 + + PseudoSF_VC_V_FPR16VW_MF4 = 848 + + PseudoSF_VC_V_FPR16VW_SE_M1 = 849 + + PseudoSF_VC_V_FPR16VW_SE_M2 = 850 + + PseudoSF_VC_V_FPR16VW_SE_M4 = 851 + + PseudoSF_VC_V_FPR16VW_SE_M8 = 852 + + PseudoSF_VC_V_FPR16VW_SE_MF2 = 853 + + PseudoSF_VC_V_FPR16VW_SE_MF4 = 854 + + PseudoSF_VC_V_FPR16V_M1 = 855 + + PseudoSF_VC_V_FPR16V_M2 = 856 + + PseudoSF_VC_V_FPR16V_M4 = 857 + + PseudoSF_VC_V_FPR16V_M8 = 858 + + PseudoSF_VC_V_FPR16V_MF2 = 859 + + PseudoSF_VC_V_FPR16V_MF4 = 860 + + PseudoSF_VC_V_FPR16V_SE_M1 = 861 + + PseudoSF_VC_V_FPR16V_SE_M2 = 862 + + PseudoSF_VC_V_FPR16V_SE_M4 = 863 + + PseudoSF_VC_V_FPR16V_SE_M8 = 864 + + PseudoSF_VC_V_FPR16V_SE_MF2 = 865 + + PseudoSF_VC_V_FPR16V_SE_MF4 = 866 + + PseudoSF_VC_V_FPR32VV_M1 = 867 + + PseudoSF_VC_V_FPR32VV_M2 = 868 + + PseudoSF_VC_V_FPR32VV_M4 = 869 + + PseudoSF_VC_V_FPR32VV_M8 = 870 + + PseudoSF_VC_V_FPR32VV_MF2 = 871 + + PseudoSF_VC_V_FPR32VV_SE_M1 = 872 + + PseudoSF_VC_V_FPR32VV_SE_M2 = 873 + + PseudoSF_VC_V_FPR32VV_SE_M4 = 874 + + PseudoSF_VC_V_FPR32VV_SE_M8 = 875 + + PseudoSF_VC_V_FPR32VV_SE_MF2 = 876 + + PseudoSF_VC_V_FPR32VW_M1 = 877 + + PseudoSF_VC_V_FPR32VW_M2 = 878 + + PseudoSF_VC_V_FPR32VW_M4 = 879 + + PseudoSF_VC_V_FPR32VW_M8 = 880 + + PseudoSF_VC_V_FPR32VW_MF2 = 881 + + PseudoSF_VC_V_FPR32VW_SE_M1 = 882 + + PseudoSF_VC_V_FPR32VW_SE_M2 = 883 + + PseudoSF_VC_V_FPR32VW_SE_M4 = 884 + + PseudoSF_VC_V_FPR32VW_SE_M8 = 885 + + PseudoSF_VC_V_FPR32VW_SE_MF2 = 886 + + PseudoSF_VC_V_FPR32V_M1 = 887 + + PseudoSF_VC_V_FPR32V_M2 = 888 + + PseudoSF_VC_V_FPR32V_M4 = 889 + + PseudoSF_VC_V_FPR32V_M8 = 890 + + PseudoSF_VC_V_FPR32V_MF2 = 891 + + PseudoSF_VC_V_FPR32V_SE_M1 = 892 + + PseudoSF_VC_V_FPR32V_SE_M2 = 893 + + PseudoSF_VC_V_FPR32V_SE_M4 = 894 + + PseudoSF_VC_V_FPR32V_SE_M8 = 895 + + PseudoSF_VC_V_FPR32V_SE_MF2 = 896 + + PseudoSF_VC_V_FPR64VV_M1 = 897 + + PseudoSF_VC_V_FPR64VV_M2 = 898 + + PseudoSF_VC_V_FPR64VV_M4 = 899 + + PseudoSF_VC_V_FPR64VV_M8 = 900 + + PseudoSF_VC_V_FPR64VV_SE_M1 = 901 + + PseudoSF_VC_V_FPR64VV_SE_M2 = 902 + + PseudoSF_VC_V_FPR64VV_SE_M4 = 903 + + PseudoSF_VC_V_FPR64VV_SE_M8 = 904 + + PseudoSF_VC_V_FPR64V_M1 = 905 + + PseudoSF_VC_V_FPR64V_M2 = 906 + + PseudoSF_VC_V_FPR64V_M4 = 907 + + PseudoSF_VC_V_FPR64V_M8 = 908 + + PseudoSF_VC_V_FPR64V_SE_M1 = 909 + + PseudoSF_VC_V_FPR64V_SE_M2 = 910 + + PseudoSF_VC_V_FPR64V_SE_M4 = 911 + + PseudoSF_VC_V_FPR64V_SE_M8 = 912 + + PseudoSF_VC_V_IVV_M1 = 913 + + PseudoSF_VC_V_IVV_M2 = 914 + + PseudoSF_VC_V_IVV_M4 = 915 + + PseudoSF_VC_V_IVV_M8 = 916 + + PseudoSF_VC_V_IVV_MF2 = 917 + + PseudoSF_VC_V_IVV_MF4 = 918 + + PseudoSF_VC_V_IVV_MF8 = 919 + + PseudoSF_VC_V_IVV_SE_M1 = 920 + + PseudoSF_VC_V_IVV_SE_M2 = 921 + + PseudoSF_VC_V_IVV_SE_M4 = 922 + + PseudoSF_VC_V_IVV_SE_M8 = 923 + + PseudoSF_VC_V_IVV_SE_MF2 = 924 + + PseudoSF_VC_V_IVV_SE_MF4 = 925 + + PseudoSF_VC_V_IVV_SE_MF8 = 926 + + PseudoSF_VC_V_IVW_M1 = 927 + + PseudoSF_VC_V_IVW_M2 = 928 + + PseudoSF_VC_V_IVW_M4 = 929 + + PseudoSF_VC_V_IVW_MF2 = 930 + + PseudoSF_VC_V_IVW_MF4 = 931 + + PseudoSF_VC_V_IVW_MF8 = 932 + + PseudoSF_VC_V_IVW_SE_M1 = 933 + + PseudoSF_VC_V_IVW_SE_M2 = 934 + + PseudoSF_VC_V_IVW_SE_M4 = 935 + + PseudoSF_VC_V_IVW_SE_MF2 = 936 + + PseudoSF_VC_V_IVW_SE_MF4 = 937 + + PseudoSF_VC_V_IVW_SE_MF8 = 938 + + PseudoSF_VC_V_IV_M1 = 939 + + PseudoSF_VC_V_IV_M2 = 940 + + PseudoSF_VC_V_IV_M4 = 941 + + PseudoSF_VC_V_IV_M8 = 942 + + PseudoSF_VC_V_IV_MF2 = 943 + + PseudoSF_VC_V_IV_MF4 = 944 + + PseudoSF_VC_V_IV_MF8 = 945 + + PseudoSF_VC_V_IV_SE_M1 = 946 + + PseudoSF_VC_V_IV_SE_M2 = 947 + + PseudoSF_VC_V_IV_SE_M4 = 948 + + PseudoSF_VC_V_IV_SE_M8 = 949 + + PseudoSF_VC_V_IV_SE_MF2 = 950 + + PseudoSF_VC_V_IV_SE_MF4 = 951 + + PseudoSF_VC_V_IV_SE_MF8 = 952 + + PseudoSF_VC_V_I_M1 = 953 + + PseudoSF_VC_V_I_M2 = 954 + + PseudoSF_VC_V_I_M4 = 955 + + PseudoSF_VC_V_I_M8 = 956 + + PseudoSF_VC_V_I_MF2 = 957 + + PseudoSF_VC_V_I_MF4 = 958 + + PseudoSF_VC_V_I_MF8 = 959 + + PseudoSF_VC_V_I_SE_M1 = 960 + + PseudoSF_VC_V_I_SE_M2 = 961 + + PseudoSF_VC_V_I_SE_M4 = 962 + + PseudoSF_VC_V_I_SE_M8 = 963 + + PseudoSF_VC_V_I_SE_MF2 = 964 + + PseudoSF_VC_V_I_SE_MF4 = 965 + + PseudoSF_VC_V_I_SE_MF8 = 966 + + PseudoSF_VC_V_VVV_M1 = 967 + + PseudoSF_VC_V_VVV_M2 = 968 + + PseudoSF_VC_V_VVV_M4 = 969 + + PseudoSF_VC_V_VVV_M8 = 970 + + PseudoSF_VC_V_VVV_MF2 = 971 + + PseudoSF_VC_V_VVV_MF4 = 972 + + PseudoSF_VC_V_VVV_MF8 = 973 + + PseudoSF_VC_V_VVV_SE_M1 = 974 + + PseudoSF_VC_V_VVV_SE_M2 = 975 + + PseudoSF_VC_V_VVV_SE_M4 = 976 + + PseudoSF_VC_V_VVV_SE_M8 = 977 + + PseudoSF_VC_V_VVV_SE_MF2 = 978 + + PseudoSF_VC_V_VVV_SE_MF4 = 979 + + PseudoSF_VC_V_VVV_SE_MF8 = 980 + + PseudoSF_VC_V_VVW_M1 = 981 + + PseudoSF_VC_V_VVW_M2 = 982 + + PseudoSF_VC_V_VVW_M4 = 983 + + PseudoSF_VC_V_VVW_MF2 = 984 + + PseudoSF_VC_V_VVW_MF4 = 985 + + PseudoSF_VC_V_VVW_MF8 = 986 + + PseudoSF_VC_V_VVW_SE_M1 = 987 + + PseudoSF_VC_V_VVW_SE_M2 = 988 + + PseudoSF_VC_V_VVW_SE_M4 = 989 + + PseudoSF_VC_V_VVW_SE_MF2 = 990 + + PseudoSF_VC_V_VVW_SE_MF4 = 991 + + PseudoSF_VC_V_VVW_SE_MF8 = 992 + + PseudoSF_VC_V_VV_M1 = 993 + + PseudoSF_VC_V_VV_M2 = 994 + + PseudoSF_VC_V_VV_M4 = 995 + + PseudoSF_VC_V_VV_M8 = 996 + + PseudoSF_VC_V_VV_MF2 = 997 + + PseudoSF_VC_V_VV_MF4 = 998 + + PseudoSF_VC_V_VV_MF8 = 999 + + PseudoSF_VC_V_VV_SE_M1 = 1000 + + PseudoSF_VC_V_VV_SE_M2 = 1001 + + PseudoSF_VC_V_VV_SE_M4 = 1002 + + PseudoSF_VC_V_VV_SE_M8 = 1003 + + PseudoSF_VC_V_VV_SE_MF2 = 1004 + + PseudoSF_VC_V_VV_SE_MF4 = 1005 + + PseudoSF_VC_V_VV_SE_MF8 = 1006 + + PseudoSF_VC_V_XVV_M1 = 1007 + + PseudoSF_VC_V_XVV_M2 = 1008 + + PseudoSF_VC_V_XVV_M4 = 1009 + + PseudoSF_VC_V_XVV_M8 = 1010 + + PseudoSF_VC_V_XVV_MF2 = 1011 + + PseudoSF_VC_V_XVV_MF4 = 1012 + + PseudoSF_VC_V_XVV_MF8 = 1013 + + PseudoSF_VC_V_XVV_SE_M1 = 1014 + + PseudoSF_VC_V_XVV_SE_M2 = 1015 + + PseudoSF_VC_V_XVV_SE_M4 = 1016 + + PseudoSF_VC_V_XVV_SE_M8 = 1017 + + PseudoSF_VC_V_XVV_SE_MF2 = 1018 + + PseudoSF_VC_V_XVV_SE_MF4 = 1019 + + PseudoSF_VC_V_XVV_SE_MF8 = 1020 + + PseudoSF_VC_V_XVW_M1 = 1021 + + PseudoSF_VC_V_XVW_M2 = 1022 + + PseudoSF_VC_V_XVW_M4 = 1023 + + PseudoSF_VC_V_XVW_MF2 = 1024 + + PseudoSF_VC_V_XVW_MF4 = 1025 + + PseudoSF_VC_V_XVW_MF8 = 1026 + + PseudoSF_VC_V_XVW_SE_M1 = 1027 + + PseudoSF_VC_V_XVW_SE_M2 = 1028 + + PseudoSF_VC_V_XVW_SE_M4 = 1029 + + PseudoSF_VC_V_XVW_SE_MF2 = 1030 + + PseudoSF_VC_V_XVW_SE_MF4 = 1031 + + PseudoSF_VC_V_XVW_SE_MF8 = 1032 + + PseudoSF_VC_V_XV_M1 = 1033 + + PseudoSF_VC_V_XV_M2 = 1034 + + PseudoSF_VC_V_XV_M4 = 1035 + + PseudoSF_VC_V_XV_M8 = 1036 + + PseudoSF_VC_V_XV_MF2 = 1037 + + PseudoSF_VC_V_XV_MF4 = 1038 + + PseudoSF_VC_V_XV_MF8 = 1039 + + PseudoSF_VC_V_XV_SE_M1 = 1040 + + PseudoSF_VC_V_XV_SE_M2 = 1041 + + PseudoSF_VC_V_XV_SE_M4 = 1042 + + PseudoSF_VC_V_XV_SE_M8 = 1043 + + PseudoSF_VC_V_XV_SE_MF2 = 1044 + + PseudoSF_VC_V_XV_SE_MF4 = 1045 + + PseudoSF_VC_V_XV_SE_MF8 = 1046 + + PseudoSF_VC_V_X_M1 = 1047 + + PseudoSF_VC_V_X_M2 = 1048 + + PseudoSF_VC_V_X_M4 = 1049 + + PseudoSF_VC_V_X_M8 = 1050 + + PseudoSF_VC_V_X_MF2 = 1051 + + PseudoSF_VC_V_X_MF4 = 1052 + + PseudoSF_VC_V_X_MF8 = 1053 + + PseudoSF_VC_V_X_SE_M1 = 1054 + + PseudoSF_VC_V_X_SE_M2 = 1055 + + PseudoSF_VC_V_X_SE_M4 = 1056 + + PseudoSF_VC_V_X_SE_M8 = 1057 + + PseudoSF_VC_V_X_SE_MF2 = 1058 + + PseudoSF_VC_V_X_SE_MF4 = 1059 + + PseudoSF_VC_V_X_SE_MF8 = 1060 + + PseudoSF_VC_XVV_SE_M1 = 1061 + + PseudoSF_VC_XVV_SE_M2 = 1062 + + PseudoSF_VC_XVV_SE_M4 = 1063 + + PseudoSF_VC_XVV_SE_M8 = 1064 + + PseudoSF_VC_XVV_SE_MF2 = 1065 + + PseudoSF_VC_XVV_SE_MF4 = 1066 + + PseudoSF_VC_XVV_SE_MF8 = 1067 + + PseudoSF_VC_XVW_SE_M1 = 1068 + + PseudoSF_VC_XVW_SE_M2 = 1069 + + PseudoSF_VC_XVW_SE_M4 = 1070 + + PseudoSF_VC_XVW_SE_MF2 = 1071 + + PseudoSF_VC_XVW_SE_MF4 = 1072 + + PseudoSF_VC_XVW_SE_MF8 = 1073 + + PseudoSF_VC_XV_SE_M1 = 1074 + + PseudoSF_VC_XV_SE_M2 = 1075 + + PseudoSF_VC_XV_SE_M4 = 1076 + + PseudoSF_VC_XV_SE_M8 = 1077 + + PseudoSF_VC_XV_SE_MF2 = 1078 + + PseudoSF_VC_XV_SE_MF4 = 1079 + + PseudoSF_VC_XV_SE_MF8 = 1080 + + PseudoSF_VC_X_SE_M1 = 1081 + + PseudoSF_VC_X_SE_M2 = 1082 + + PseudoSF_VC_X_SE_M4 = 1083 + + PseudoSF_VC_X_SE_M8 = 1084 + + PseudoSF_VC_X_SE_MF2 = 1085 + + PseudoSF_VC_X_SE_MF4 = 1086 + + PseudoSF_VC_X_SE_MF8 = 1087 + + PseudoSF_VFEXPA_V_M1_E16 = 1088 + + PseudoSF_VFEXPA_V_M1_E16_MASK = 1089 + + PseudoSF_VFEXPA_V_M1_E32 = 1090 + + PseudoSF_VFEXPA_V_M1_E32_MASK = 1091 + + PseudoSF_VFEXPA_V_M1_E64 = 1092 + + PseudoSF_VFEXPA_V_M1_E64_MASK = 1093 + + PseudoSF_VFEXPA_V_M2_E16 = 1094 + + PseudoSF_VFEXPA_V_M2_E16_MASK = 1095 + + PseudoSF_VFEXPA_V_M2_E32 = 1096 + + PseudoSF_VFEXPA_V_M2_E32_MASK = 1097 + + PseudoSF_VFEXPA_V_M2_E64 = 1098 + + PseudoSF_VFEXPA_V_M2_E64_MASK = 1099 + + PseudoSF_VFEXPA_V_M4_E16 = 1100 + + PseudoSF_VFEXPA_V_M4_E16_MASK = 1101 + + PseudoSF_VFEXPA_V_M4_E32 = 1102 + + PseudoSF_VFEXPA_V_M4_E32_MASK = 1103 + + PseudoSF_VFEXPA_V_M4_E64 = 1104 + + PseudoSF_VFEXPA_V_M4_E64_MASK = 1105 + + PseudoSF_VFEXPA_V_M8_E16 = 1106 + + PseudoSF_VFEXPA_V_M8_E16_MASK = 1107 + + PseudoSF_VFEXPA_V_M8_E32 = 1108 + + PseudoSF_VFEXPA_V_M8_E32_MASK = 1109 + + PseudoSF_VFEXPA_V_M8_E64 = 1110 + + PseudoSF_VFEXPA_V_M8_E64_MASK = 1111 + + PseudoSF_VFEXPA_V_MF2_E16 = 1112 + + PseudoSF_VFEXPA_V_MF2_E16_MASK = 1113 + + PseudoSF_VFEXPA_V_MF2_E32 = 1114 + + PseudoSF_VFEXPA_V_MF2_E32_MASK = 1115 + + PseudoSF_VFEXPA_V_MF4_E16 = 1116 + + PseudoSF_VFEXPA_V_MF4_E16_MASK = 1117 + + PseudoSF_VFEXP_ALT_V_M1_E16 = 1118 + + PseudoSF_VFEXP_ALT_V_M1_E16_MASK = 1119 + + PseudoSF_VFEXP_ALT_V_M2_E16 = 1120 + + PseudoSF_VFEXP_ALT_V_M2_E16_MASK = 1121 + + PseudoSF_VFEXP_ALT_V_M4_E16 = 1122 + + PseudoSF_VFEXP_ALT_V_M4_E16_MASK = 1123 + + PseudoSF_VFEXP_ALT_V_M8_E16 = 1124 + + PseudoSF_VFEXP_ALT_V_M8_E16_MASK = 1125 + + PseudoSF_VFEXP_ALT_V_MF2_E16 = 1126 + + PseudoSF_VFEXP_ALT_V_MF2_E16_MASK = 1127 + + PseudoSF_VFEXP_ALT_V_MF4_E16 = 1128 + + PseudoSF_VFEXP_ALT_V_MF4_E16_MASK = 1129 + + PseudoSF_VFEXP_V_M1_E16 = 1130 + + PseudoSF_VFEXP_V_M1_E16_MASK = 1131 + + PseudoSF_VFEXP_V_M1_E32 = 1132 + + PseudoSF_VFEXP_V_M1_E32_MASK = 1133 + + PseudoSF_VFEXP_V_M2_E16 = 1134 + + PseudoSF_VFEXP_V_M2_E16_MASK = 1135 + + PseudoSF_VFEXP_V_M2_E32 = 1136 + + PseudoSF_VFEXP_V_M2_E32_MASK = 1137 + + PseudoSF_VFEXP_V_M4_E16 = 1138 + + PseudoSF_VFEXP_V_M4_E16_MASK = 1139 + + PseudoSF_VFEXP_V_M4_E32 = 1140 + + PseudoSF_VFEXP_V_M4_E32_MASK = 1141 + + PseudoSF_VFEXP_V_M8_E16 = 1142 + + PseudoSF_VFEXP_V_M8_E16_MASK = 1143 + + PseudoSF_VFEXP_V_M8_E32 = 1144 + + PseudoSF_VFEXP_V_M8_E32_MASK = 1145 + + PseudoSF_VFEXP_V_MF2_E16 = 1146 + + PseudoSF_VFEXP_V_MF2_E16_MASK = 1147 + + PseudoSF_VFEXP_V_MF2_E32 = 1148 + + PseudoSF_VFEXP_V_MF2_E32_MASK = 1149 + + PseudoSF_VFEXP_V_MF4_E16 = 1150 + + PseudoSF_VFEXP_V_MF4_E16_MASK = 1151 + + PseudoSF_VFNRCLIP_XU_F_QF_M1 = 1152 + + PseudoSF_VFNRCLIP_XU_F_QF_M1_MASK = 1153 + + PseudoSF_VFNRCLIP_XU_F_QF_M2 = 1154 + + PseudoSF_VFNRCLIP_XU_F_QF_M2_MASK = 1155 + + PseudoSF_VFNRCLIP_XU_F_QF_MF2 = 1156 + + PseudoSF_VFNRCLIP_XU_F_QF_MF2_MASK = 1157 + + PseudoSF_VFNRCLIP_XU_F_QF_MF4 = 1158 + + PseudoSF_VFNRCLIP_XU_F_QF_MF4_MASK = 1159 + + PseudoSF_VFNRCLIP_XU_F_QF_MF8 = 1160 + + PseudoSF_VFNRCLIP_XU_F_QF_MF8_MASK = 1161 + + PseudoSF_VFNRCLIP_X_F_QF_M1 = 1162 + + PseudoSF_VFNRCLIP_X_F_QF_M1_MASK = 1163 + + PseudoSF_VFNRCLIP_X_F_QF_M2 = 1164 + + PseudoSF_VFNRCLIP_X_F_QF_M2_MASK = 1165 + + PseudoSF_VFNRCLIP_X_F_QF_MF2 = 1166 + + PseudoSF_VFNRCLIP_X_F_QF_MF2_MASK = 1167 + + PseudoSF_VFNRCLIP_X_F_QF_MF4 = 1168 + + PseudoSF_VFNRCLIP_X_F_QF_MF4_MASK = 1169 + + PseudoSF_VFNRCLIP_X_F_QF_MF8 = 1170 + + PseudoSF_VFNRCLIP_X_F_QF_MF8_MASK = 1171 + + PseudoSF_VFWMACC_4x4x4_M1 = 1172 + + PseudoSF_VFWMACC_4x4x4_M2 = 1173 + + PseudoSF_VFWMACC_4x4x4_M4 = 1174 + + PseudoSF_VFWMACC_4x4x4_MF2 = 1175 + + PseudoSF_VFWMACC_4x4x4_MF4 = 1176 + + PseudoSF_VLTE16 = 1177 + + PseudoSF_VLTE32 = 1178 + + PseudoSF_VLTE64 = 1179 + + PseudoSF_VLTE8 = 1180 + + PseudoSF_VQMACCSU_2x8x2_M1 = 1181 + + PseudoSF_VQMACCSU_2x8x2_M2 = 1182 + + PseudoSF_VQMACCSU_2x8x2_M4 = 1183 + + PseudoSF_VQMACCSU_2x8x2_M8 = 1184 + + PseudoSF_VQMACCSU_4x8x4_M1 = 1185 + + PseudoSF_VQMACCSU_4x8x4_M2 = 1186 + + PseudoSF_VQMACCSU_4x8x4_M4 = 1187 + + PseudoSF_VQMACCSU_4x8x4_MF2 = 1188 + + PseudoSF_VQMACCUS_2x8x2_M1 = 1189 + + PseudoSF_VQMACCUS_2x8x2_M2 = 1190 + + PseudoSF_VQMACCUS_2x8x2_M4 = 1191 + + PseudoSF_VQMACCUS_2x8x2_M8 = 1192 + + PseudoSF_VQMACCUS_4x8x4_M1 = 1193 + + PseudoSF_VQMACCUS_4x8x4_M2 = 1194 + + PseudoSF_VQMACCUS_4x8x4_M4 = 1195 + + PseudoSF_VQMACCUS_4x8x4_MF2 = 1196 + + PseudoSF_VQMACCU_2x8x2_M1 = 1197 + + PseudoSF_VQMACCU_2x8x2_M2 = 1198 + + PseudoSF_VQMACCU_2x8x2_M4 = 1199 + + PseudoSF_VQMACCU_2x8x2_M8 = 1200 + + PseudoSF_VQMACCU_4x8x4_M1 = 1201 + + PseudoSF_VQMACCU_4x8x4_M2 = 1202 + + PseudoSF_VQMACCU_4x8x4_M4 = 1203 + + PseudoSF_VQMACCU_4x8x4_MF2 = 1204 + + PseudoSF_VQMACC_2x8x2_M1 = 1205 + + PseudoSF_VQMACC_2x8x2_M2 = 1206 + + PseudoSF_VQMACC_2x8x2_M4 = 1207 + + PseudoSF_VQMACC_2x8x2_M8 = 1208 + + PseudoSF_VQMACC_4x8x4_M1 = 1209 + + PseudoSF_VQMACC_4x8x4_M2 = 1210 + + PseudoSF_VQMACC_4x8x4_M4 = 1211 + + PseudoSF_VQMACC_4x8x4_MF2 = 1212 + + PseudoSF_VSETTK = 1213 + + PseudoSF_VSETTM = 1214 + + PseudoSF_VSETTNT = 1215 + + PseudoSF_VSETTNTX0 = 1216 + + PseudoSF_VSETTNTX0X0 = 1217 + + PseudoSF_VSTE16 = 1218 + + PseudoSF_VSTE32 = 1219 + + PseudoSF_VSTE64 = 1220 + + PseudoSF_VSTE8 = 1221 + + PseudoSF_VTDISCARD = 1222 + + PseudoSF_VTMV_T_V = 1223 + + PseudoSF_VTMV_V_T = 1224 + + PseudoSF_VTZERO_T = 1225 + + PseudoSH = 1226 + + PseudoSW = 1227 + + PseudoTAIL = 1228 + + PseudoTAILIndirect = 1229 + + PseudoTAILIndirectNonX7 = 1230 + + PseudoTAILIndirectX7 = 1231 + + PseudoTH_VMAQASU_VV_M1 = 1232 + + PseudoTH_VMAQASU_VV_M1_MASK = 1233 + + PseudoTH_VMAQASU_VV_M2 = 1234 + + PseudoTH_VMAQASU_VV_M2_MASK = 1235 + + PseudoTH_VMAQASU_VV_M4 = 1236 + + PseudoTH_VMAQASU_VV_M4_MASK = 1237 + + PseudoTH_VMAQASU_VV_M8 = 1238 + + PseudoTH_VMAQASU_VV_M8_MASK = 1239 + + PseudoTH_VMAQASU_VV_MF2 = 1240 + + PseudoTH_VMAQASU_VV_MF2_MASK = 1241 + + PseudoTH_VMAQASU_VX_M1 = 1242 + + PseudoTH_VMAQASU_VX_M1_MASK = 1243 + + PseudoTH_VMAQASU_VX_M2 = 1244 + + PseudoTH_VMAQASU_VX_M2_MASK = 1245 + + PseudoTH_VMAQASU_VX_M4 = 1246 + + PseudoTH_VMAQASU_VX_M4_MASK = 1247 + + PseudoTH_VMAQASU_VX_M8 = 1248 + + PseudoTH_VMAQASU_VX_M8_MASK = 1249 + + PseudoTH_VMAQASU_VX_MF2 = 1250 + + PseudoTH_VMAQASU_VX_MF2_MASK = 1251 + + PseudoTH_VMAQAUS_VX_M1 = 1252 + + PseudoTH_VMAQAUS_VX_M1_MASK = 1253 + + PseudoTH_VMAQAUS_VX_M2 = 1254 + + PseudoTH_VMAQAUS_VX_M2_MASK = 1255 + + PseudoTH_VMAQAUS_VX_M4 = 1256 + + PseudoTH_VMAQAUS_VX_M4_MASK = 1257 + + PseudoTH_VMAQAUS_VX_M8 = 1258 + + PseudoTH_VMAQAUS_VX_M8_MASK = 1259 + + PseudoTH_VMAQAUS_VX_MF2 = 1260 + + PseudoTH_VMAQAUS_VX_MF2_MASK = 1261 + + PseudoTH_VMAQAU_VV_M1 = 1262 + + PseudoTH_VMAQAU_VV_M1_MASK = 1263 + + PseudoTH_VMAQAU_VV_M2 = 1264 + + PseudoTH_VMAQAU_VV_M2_MASK = 1265 + + PseudoTH_VMAQAU_VV_M4 = 1266 + + PseudoTH_VMAQAU_VV_M4_MASK = 1267 + + PseudoTH_VMAQAU_VV_M8 = 1268 + + PseudoTH_VMAQAU_VV_M8_MASK = 1269 + + PseudoTH_VMAQAU_VV_MF2 = 1270 + + PseudoTH_VMAQAU_VV_MF2_MASK = 1271 + + PseudoTH_VMAQAU_VX_M1 = 1272 + + PseudoTH_VMAQAU_VX_M1_MASK = 1273 + + PseudoTH_VMAQAU_VX_M2 = 1274 + + PseudoTH_VMAQAU_VX_M2_MASK = 1275 + + PseudoTH_VMAQAU_VX_M4 = 1276 + + PseudoTH_VMAQAU_VX_M4_MASK = 1277 + + PseudoTH_VMAQAU_VX_M8 = 1278 + + PseudoTH_VMAQAU_VX_M8_MASK = 1279 + + PseudoTH_VMAQAU_VX_MF2 = 1280 + + PseudoTH_VMAQAU_VX_MF2_MASK = 1281 + + PseudoTH_VMAQA_VV_M1 = 1282 + + PseudoTH_VMAQA_VV_M1_MASK = 1283 + + PseudoTH_VMAQA_VV_M2 = 1284 + + PseudoTH_VMAQA_VV_M2_MASK = 1285 + + PseudoTH_VMAQA_VV_M4 = 1286 + + PseudoTH_VMAQA_VV_M4_MASK = 1287 + + PseudoTH_VMAQA_VV_M8 = 1288 + + PseudoTH_VMAQA_VV_M8_MASK = 1289 + + PseudoTH_VMAQA_VV_MF2 = 1290 + + PseudoTH_VMAQA_VV_MF2_MASK = 1291 + + PseudoTH_VMAQA_VX_M1 = 1292 + + PseudoTH_VMAQA_VX_M1_MASK = 1293 + + PseudoTH_VMAQA_VX_M2 = 1294 + + PseudoTH_VMAQA_VX_M2_MASK = 1295 + + PseudoTH_VMAQA_VX_M4 = 1296 + + PseudoTH_VMAQA_VX_M4_MASK = 1297 + + PseudoTH_VMAQA_VX_M8 = 1298 + + PseudoTH_VMAQA_VX_M8_MASK = 1299 + + PseudoTH_VMAQA_VX_MF2 = 1300 + + PseudoTH_VMAQA_VX_MF2_MASK = 1301 + + PseudoTLSDESCCall = 1302 + + PseudoVAADDU_VV_M1 = 1303 + + PseudoVAADDU_VV_M1_MASK = 1304 + + PseudoVAADDU_VV_M2 = 1305 + + PseudoVAADDU_VV_M2_MASK = 1306 + + PseudoVAADDU_VV_M4 = 1307 + + PseudoVAADDU_VV_M4_MASK = 1308 + + PseudoVAADDU_VV_M8 = 1309 + + PseudoVAADDU_VV_M8_MASK = 1310 + + PseudoVAADDU_VV_MF2 = 1311 + + PseudoVAADDU_VV_MF2_MASK = 1312 + + PseudoVAADDU_VV_MF4 = 1313 + + PseudoVAADDU_VV_MF4_MASK = 1314 + + PseudoVAADDU_VV_MF8 = 1315 + + PseudoVAADDU_VV_MF8_MASK = 1316 + + PseudoVAADDU_VX_M1 = 1317 + + PseudoVAADDU_VX_M1_MASK = 1318 + + PseudoVAADDU_VX_M2 = 1319 + + PseudoVAADDU_VX_M2_MASK = 1320 + + PseudoVAADDU_VX_M4 = 1321 + + PseudoVAADDU_VX_M4_MASK = 1322 + + PseudoVAADDU_VX_M8 = 1323 + + PseudoVAADDU_VX_M8_MASK = 1324 + + PseudoVAADDU_VX_MF2 = 1325 + + PseudoVAADDU_VX_MF2_MASK = 1326 + + PseudoVAADDU_VX_MF4 = 1327 + + PseudoVAADDU_VX_MF4_MASK = 1328 + + PseudoVAADDU_VX_MF8 = 1329 + + PseudoVAADDU_VX_MF8_MASK = 1330 + + PseudoVAADD_VV_M1 = 1331 + + PseudoVAADD_VV_M1_MASK = 1332 + + PseudoVAADD_VV_M2 = 1333 + + PseudoVAADD_VV_M2_MASK = 1334 + + PseudoVAADD_VV_M4 = 1335 + + PseudoVAADD_VV_M4_MASK = 1336 + + PseudoVAADD_VV_M8 = 1337 + + PseudoVAADD_VV_M8_MASK = 1338 + + PseudoVAADD_VV_MF2 = 1339 + + PseudoVAADD_VV_MF2_MASK = 1340 + + PseudoVAADD_VV_MF4 = 1341 + + PseudoVAADD_VV_MF4_MASK = 1342 + + PseudoVAADD_VV_MF8 = 1343 + + PseudoVAADD_VV_MF8_MASK = 1344 + + PseudoVAADD_VX_M1 = 1345 + + PseudoVAADD_VX_M1_MASK = 1346 + + PseudoVAADD_VX_M2 = 1347 + + PseudoVAADD_VX_M2_MASK = 1348 + + PseudoVAADD_VX_M4 = 1349 + + PseudoVAADD_VX_M4_MASK = 1350 + + PseudoVAADD_VX_M8 = 1351 + + PseudoVAADD_VX_M8_MASK = 1352 + + PseudoVAADD_VX_MF2 = 1353 + + PseudoVAADD_VX_MF2_MASK = 1354 + + PseudoVAADD_VX_MF4 = 1355 + + PseudoVAADD_VX_MF4_MASK = 1356 + + PseudoVAADD_VX_MF8 = 1357 + + PseudoVAADD_VX_MF8_MASK = 1358 + + PseudoVADC_VIM_M1 = 1359 + + PseudoVADC_VIM_M2 = 1360 + + PseudoVADC_VIM_M4 = 1361 + + PseudoVADC_VIM_M8 = 1362 + + PseudoVADC_VIM_MF2 = 1363 + + PseudoVADC_VIM_MF4 = 1364 + + PseudoVADC_VIM_MF8 = 1365 + + PseudoVADC_VVM_M1 = 1366 + + PseudoVADC_VVM_M2 = 1367 + + PseudoVADC_VVM_M4 = 1368 + + PseudoVADC_VVM_M8 = 1369 + + PseudoVADC_VVM_MF2 = 1370 + + PseudoVADC_VVM_MF4 = 1371 + + PseudoVADC_VVM_MF8 = 1372 + + PseudoVADC_VXM_M1 = 1373 + + PseudoVADC_VXM_M2 = 1374 + + PseudoVADC_VXM_M4 = 1375 + + PseudoVADC_VXM_M8 = 1376 + + PseudoVADC_VXM_MF2 = 1377 + + PseudoVADC_VXM_MF4 = 1378 + + PseudoVADC_VXM_MF8 = 1379 + + PseudoVADD_VI_M1 = 1380 + + PseudoVADD_VI_M1_MASK = 1381 + + PseudoVADD_VI_M2 = 1382 + + PseudoVADD_VI_M2_MASK = 1383 + + PseudoVADD_VI_M4 = 1384 + + PseudoVADD_VI_M4_MASK = 1385 + + PseudoVADD_VI_M8 = 1386 + + PseudoVADD_VI_M8_MASK = 1387 + + PseudoVADD_VI_MF2 = 1388 + + PseudoVADD_VI_MF2_MASK = 1389 + + PseudoVADD_VI_MF4 = 1390 + + PseudoVADD_VI_MF4_MASK = 1391 + + PseudoVADD_VI_MF8 = 1392 + + PseudoVADD_VI_MF8_MASK = 1393 + + PseudoVADD_VV_M1 = 1394 + + PseudoVADD_VV_M1_MASK = 1395 + + PseudoVADD_VV_M2 = 1396 + + PseudoVADD_VV_M2_MASK = 1397 + + PseudoVADD_VV_M4 = 1398 + + PseudoVADD_VV_M4_MASK = 1399 + + PseudoVADD_VV_M8 = 1400 + + PseudoVADD_VV_M8_MASK = 1401 + + PseudoVADD_VV_MF2 = 1402 + + PseudoVADD_VV_MF2_MASK = 1403 + + PseudoVADD_VV_MF4 = 1404 + + PseudoVADD_VV_MF4_MASK = 1405 + + PseudoVADD_VV_MF8 = 1406 + + PseudoVADD_VV_MF8_MASK = 1407 + + PseudoVADD_VX_M1 = 1408 + + PseudoVADD_VX_M1_MASK = 1409 + + PseudoVADD_VX_M2 = 1410 + + PseudoVADD_VX_M2_MASK = 1411 + + PseudoVADD_VX_M4 = 1412 + + PseudoVADD_VX_M4_MASK = 1413 + + PseudoVADD_VX_M8 = 1414 + + PseudoVADD_VX_M8_MASK = 1415 + + PseudoVADD_VX_MF2 = 1416 + + PseudoVADD_VX_MF2_MASK = 1417 + + PseudoVADD_VX_MF4 = 1418 + + PseudoVADD_VX_MF4_MASK = 1419 + + PseudoVADD_VX_MF8 = 1420 + + PseudoVADD_VX_MF8_MASK = 1421 + + PseudoVAESDF_VS_M1_M1 = 1422 + + PseudoVAESDF_VS_M1_MF2 = 1423 + + PseudoVAESDF_VS_M1_MF4 = 1424 + + PseudoVAESDF_VS_M1_MF8 = 1425 + + PseudoVAESDF_VS_M2_M1 = 1426 + + PseudoVAESDF_VS_M2_M2 = 1427 + + PseudoVAESDF_VS_M2_MF2 = 1428 + + PseudoVAESDF_VS_M2_MF4 = 1429 + + PseudoVAESDF_VS_M2_MF8 = 1430 + + PseudoVAESDF_VS_M4_M1 = 1431 + + PseudoVAESDF_VS_M4_M2 = 1432 + + PseudoVAESDF_VS_M4_M4 = 1433 + + PseudoVAESDF_VS_M4_MF2 = 1434 + + PseudoVAESDF_VS_M4_MF4 = 1435 + + PseudoVAESDF_VS_M4_MF8 = 1436 + + PseudoVAESDF_VS_M8_M1 = 1437 + + PseudoVAESDF_VS_M8_M2 = 1438 + + PseudoVAESDF_VS_M8_M4 = 1439 + + PseudoVAESDF_VS_M8_MF2 = 1440 + + PseudoVAESDF_VS_M8_MF4 = 1441 + + PseudoVAESDF_VS_M8_MF8 = 1442 + + PseudoVAESDF_VS_MF2_MF2 = 1443 + + PseudoVAESDF_VS_MF2_MF4 = 1444 + + PseudoVAESDF_VS_MF2_MF8 = 1445 + + PseudoVAESDF_VV_M1 = 1446 + + PseudoVAESDF_VV_M2 = 1447 + + PseudoVAESDF_VV_M4 = 1448 + + PseudoVAESDF_VV_M8 = 1449 + + PseudoVAESDF_VV_MF2 = 1450 + + PseudoVAESDM_VS_M1_M1 = 1451 + + PseudoVAESDM_VS_M1_MF2 = 1452 + + PseudoVAESDM_VS_M1_MF4 = 1453 + + PseudoVAESDM_VS_M1_MF8 = 1454 + + PseudoVAESDM_VS_M2_M1 = 1455 + + PseudoVAESDM_VS_M2_M2 = 1456 + + PseudoVAESDM_VS_M2_MF2 = 1457 + + PseudoVAESDM_VS_M2_MF4 = 1458 + + PseudoVAESDM_VS_M2_MF8 = 1459 + + PseudoVAESDM_VS_M4_M1 = 1460 + + PseudoVAESDM_VS_M4_M2 = 1461 + + PseudoVAESDM_VS_M4_M4 = 1462 + + PseudoVAESDM_VS_M4_MF2 = 1463 + + PseudoVAESDM_VS_M4_MF4 = 1464 + + PseudoVAESDM_VS_M4_MF8 = 1465 + + PseudoVAESDM_VS_M8_M1 = 1466 + + PseudoVAESDM_VS_M8_M2 = 1467 + + PseudoVAESDM_VS_M8_M4 = 1468 + + PseudoVAESDM_VS_M8_MF2 = 1469 + + PseudoVAESDM_VS_M8_MF4 = 1470 + + PseudoVAESDM_VS_M8_MF8 = 1471 + + PseudoVAESDM_VS_MF2_MF2 = 1472 + + PseudoVAESDM_VS_MF2_MF4 = 1473 + + PseudoVAESDM_VS_MF2_MF8 = 1474 + + PseudoVAESDM_VV_M1 = 1475 + + PseudoVAESDM_VV_M2 = 1476 + + PseudoVAESDM_VV_M4 = 1477 + + PseudoVAESDM_VV_M8 = 1478 + + PseudoVAESDM_VV_MF2 = 1479 + + PseudoVAESEF_VS_M1_M1 = 1480 + + PseudoVAESEF_VS_M1_MF2 = 1481 + + PseudoVAESEF_VS_M1_MF4 = 1482 + + PseudoVAESEF_VS_M1_MF8 = 1483 + + PseudoVAESEF_VS_M2_M1 = 1484 + + PseudoVAESEF_VS_M2_M2 = 1485 + + PseudoVAESEF_VS_M2_MF2 = 1486 + + PseudoVAESEF_VS_M2_MF4 = 1487 + + PseudoVAESEF_VS_M2_MF8 = 1488 + + PseudoVAESEF_VS_M4_M1 = 1489 + + PseudoVAESEF_VS_M4_M2 = 1490 + + PseudoVAESEF_VS_M4_M4 = 1491 + + PseudoVAESEF_VS_M4_MF2 = 1492 + + PseudoVAESEF_VS_M4_MF4 = 1493 + + PseudoVAESEF_VS_M4_MF8 = 1494 + + PseudoVAESEF_VS_M8_M1 = 1495 + + PseudoVAESEF_VS_M8_M2 = 1496 + + PseudoVAESEF_VS_M8_M4 = 1497 + + PseudoVAESEF_VS_M8_MF2 = 1498 + + PseudoVAESEF_VS_M8_MF4 = 1499 + + PseudoVAESEF_VS_M8_MF8 = 1500 + + PseudoVAESEF_VS_MF2_MF2 = 1501 + + PseudoVAESEF_VS_MF2_MF4 = 1502 + + PseudoVAESEF_VS_MF2_MF8 = 1503 + + PseudoVAESEF_VV_M1 = 1504 + + PseudoVAESEF_VV_M2 = 1505 + + PseudoVAESEF_VV_M4 = 1506 + + PseudoVAESEF_VV_M8 = 1507 + + PseudoVAESEF_VV_MF2 = 1508 + + PseudoVAESEM_VS_M1_M1 = 1509 + + PseudoVAESEM_VS_M1_MF2 = 1510 + + PseudoVAESEM_VS_M1_MF4 = 1511 + + PseudoVAESEM_VS_M1_MF8 = 1512 + + PseudoVAESEM_VS_M2_M1 = 1513 + + PseudoVAESEM_VS_M2_M2 = 1514 + + PseudoVAESEM_VS_M2_MF2 = 1515 + + PseudoVAESEM_VS_M2_MF4 = 1516 + + PseudoVAESEM_VS_M2_MF8 = 1517 + + PseudoVAESEM_VS_M4_M1 = 1518 + + PseudoVAESEM_VS_M4_M2 = 1519 + + PseudoVAESEM_VS_M4_M4 = 1520 + + PseudoVAESEM_VS_M4_MF2 = 1521 + + PseudoVAESEM_VS_M4_MF4 = 1522 + + PseudoVAESEM_VS_M4_MF8 = 1523 + + PseudoVAESEM_VS_M8_M1 = 1524 + + PseudoVAESEM_VS_M8_M2 = 1525 + + PseudoVAESEM_VS_M8_M4 = 1526 + + PseudoVAESEM_VS_M8_MF2 = 1527 + + PseudoVAESEM_VS_M8_MF4 = 1528 + + PseudoVAESEM_VS_M8_MF8 = 1529 + + PseudoVAESEM_VS_MF2_MF2 = 1530 + + PseudoVAESEM_VS_MF2_MF4 = 1531 + + PseudoVAESEM_VS_MF2_MF8 = 1532 + + PseudoVAESEM_VV_M1 = 1533 + + PseudoVAESEM_VV_M2 = 1534 + + PseudoVAESEM_VV_M4 = 1535 + + PseudoVAESEM_VV_M8 = 1536 + + PseudoVAESEM_VV_MF2 = 1537 + + PseudoVAESKF1_VI_M1 = 1538 + + PseudoVAESKF1_VI_M2 = 1539 + + PseudoVAESKF1_VI_M4 = 1540 + + PseudoVAESKF1_VI_M8 = 1541 + + PseudoVAESKF1_VI_MF2 = 1542 + + PseudoVAESKF2_VI_M1 = 1543 + + PseudoVAESKF2_VI_M2 = 1544 + + PseudoVAESKF2_VI_M4 = 1545 + + PseudoVAESKF2_VI_M8 = 1546 + + PseudoVAESKF2_VI_MF2 = 1547 + + PseudoVAESZ_VS_M1_M1 = 1548 + + PseudoVAESZ_VS_M1_MF2 = 1549 + + PseudoVAESZ_VS_M1_MF4 = 1550 + + PseudoVAESZ_VS_M1_MF8 = 1551 + + PseudoVAESZ_VS_M2_M1 = 1552 + + PseudoVAESZ_VS_M2_M2 = 1553 + + PseudoVAESZ_VS_M2_MF2 = 1554 + + PseudoVAESZ_VS_M2_MF4 = 1555 + + PseudoVAESZ_VS_M2_MF8 = 1556 + + PseudoVAESZ_VS_M4_M1 = 1557 + + PseudoVAESZ_VS_M4_M2 = 1558 + + PseudoVAESZ_VS_M4_M4 = 1559 + + PseudoVAESZ_VS_M4_MF2 = 1560 + + PseudoVAESZ_VS_M4_MF4 = 1561 + + PseudoVAESZ_VS_M4_MF8 = 1562 + + PseudoVAESZ_VS_M8_M1 = 1563 + + PseudoVAESZ_VS_M8_M2 = 1564 + + PseudoVAESZ_VS_M8_M4 = 1565 + + PseudoVAESZ_VS_M8_MF2 = 1566 + + PseudoVAESZ_VS_M8_MF4 = 1567 + + PseudoVAESZ_VS_M8_MF8 = 1568 + + PseudoVAESZ_VS_MF2_MF2 = 1569 + + PseudoVAESZ_VS_MF2_MF4 = 1570 + + PseudoVAESZ_VS_MF2_MF8 = 1571 + + PseudoVANDN_VV_M1 = 1572 + + PseudoVANDN_VV_M1_MASK = 1573 + + PseudoVANDN_VV_M2 = 1574 + + PseudoVANDN_VV_M2_MASK = 1575 + + PseudoVANDN_VV_M4 = 1576 + + PseudoVANDN_VV_M4_MASK = 1577 + + PseudoVANDN_VV_M8 = 1578 + + PseudoVANDN_VV_M8_MASK = 1579 + + PseudoVANDN_VV_MF2 = 1580 + + PseudoVANDN_VV_MF2_MASK = 1581 + + PseudoVANDN_VV_MF4 = 1582 + + PseudoVANDN_VV_MF4_MASK = 1583 + + PseudoVANDN_VV_MF8 = 1584 + + PseudoVANDN_VV_MF8_MASK = 1585 + + PseudoVANDN_VX_M1 = 1586 + + PseudoVANDN_VX_M1_MASK = 1587 + + PseudoVANDN_VX_M2 = 1588 + + PseudoVANDN_VX_M2_MASK = 1589 + + PseudoVANDN_VX_M4 = 1590 + + PseudoVANDN_VX_M4_MASK = 1591 + + PseudoVANDN_VX_M8 = 1592 + + PseudoVANDN_VX_M8_MASK = 1593 + + PseudoVANDN_VX_MF2 = 1594 + + PseudoVANDN_VX_MF2_MASK = 1595 + + PseudoVANDN_VX_MF4 = 1596 + + PseudoVANDN_VX_MF4_MASK = 1597 + + PseudoVANDN_VX_MF8 = 1598 + + PseudoVANDN_VX_MF8_MASK = 1599 + + PseudoVAND_VI_M1 = 1600 + + PseudoVAND_VI_M1_MASK = 1601 + + PseudoVAND_VI_M2 = 1602 + + PseudoVAND_VI_M2_MASK = 1603 + + PseudoVAND_VI_M4 = 1604 + + PseudoVAND_VI_M4_MASK = 1605 + + PseudoVAND_VI_M8 = 1606 + + PseudoVAND_VI_M8_MASK = 1607 + + PseudoVAND_VI_MF2 = 1608 + + PseudoVAND_VI_MF2_MASK = 1609 + + PseudoVAND_VI_MF4 = 1610 + + PseudoVAND_VI_MF4_MASK = 1611 + + PseudoVAND_VI_MF8 = 1612 + + PseudoVAND_VI_MF8_MASK = 1613 + + PseudoVAND_VV_M1 = 1614 + + PseudoVAND_VV_M1_MASK = 1615 + + PseudoVAND_VV_M2 = 1616 + + PseudoVAND_VV_M2_MASK = 1617 + + PseudoVAND_VV_M4 = 1618 + + PseudoVAND_VV_M4_MASK = 1619 + + PseudoVAND_VV_M8 = 1620 + + PseudoVAND_VV_M8_MASK = 1621 + + PseudoVAND_VV_MF2 = 1622 + + PseudoVAND_VV_MF2_MASK = 1623 + + PseudoVAND_VV_MF4 = 1624 + + PseudoVAND_VV_MF4_MASK = 1625 + + PseudoVAND_VV_MF8 = 1626 + + PseudoVAND_VV_MF8_MASK = 1627 + + PseudoVAND_VX_M1 = 1628 + + PseudoVAND_VX_M1_MASK = 1629 + + PseudoVAND_VX_M2 = 1630 + + PseudoVAND_VX_M2_MASK = 1631 + + PseudoVAND_VX_M4 = 1632 + + PseudoVAND_VX_M4_MASK = 1633 + + PseudoVAND_VX_M8 = 1634 + + PseudoVAND_VX_M8_MASK = 1635 + + PseudoVAND_VX_MF2 = 1636 + + PseudoVAND_VX_MF2_MASK = 1637 + + PseudoVAND_VX_MF4 = 1638 + + PseudoVAND_VX_MF4_MASK = 1639 + + PseudoVAND_VX_MF8 = 1640 + + PseudoVAND_VX_MF8_MASK = 1641 + + PseudoVASUBU_VV_M1 = 1642 + + PseudoVASUBU_VV_M1_MASK = 1643 + + PseudoVASUBU_VV_M2 = 1644 + + PseudoVASUBU_VV_M2_MASK = 1645 + + PseudoVASUBU_VV_M4 = 1646 + + PseudoVASUBU_VV_M4_MASK = 1647 + + PseudoVASUBU_VV_M8 = 1648 + + PseudoVASUBU_VV_M8_MASK = 1649 + + PseudoVASUBU_VV_MF2 = 1650 + + PseudoVASUBU_VV_MF2_MASK = 1651 + + PseudoVASUBU_VV_MF4 = 1652 + + PseudoVASUBU_VV_MF4_MASK = 1653 + + PseudoVASUBU_VV_MF8 = 1654 + + PseudoVASUBU_VV_MF8_MASK = 1655 + + PseudoVASUBU_VX_M1 = 1656 + + PseudoVASUBU_VX_M1_MASK = 1657 + + PseudoVASUBU_VX_M2 = 1658 + + PseudoVASUBU_VX_M2_MASK = 1659 + + PseudoVASUBU_VX_M4 = 1660 + + PseudoVASUBU_VX_M4_MASK = 1661 + + PseudoVASUBU_VX_M8 = 1662 + + PseudoVASUBU_VX_M8_MASK = 1663 + + PseudoVASUBU_VX_MF2 = 1664 + + PseudoVASUBU_VX_MF2_MASK = 1665 + + PseudoVASUBU_VX_MF4 = 1666 + + PseudoVASUBU_VX_MF4_MASK = 1667 + + PseudoVASUBU_VX_MF8 = 1668 + + PseudoVASUBU_VX_MF8_MASK = 1669 + + PseudoVASUB_VV_M1 = 1670 + + PseudoVASUB_VV_M1_MASK = 1671 + + PseudoVASUB_VV_M2 = 1672 + + PseudoVASUB_VV_M2_MASK = 1673 + + PseudoVASUB_VV_M4 = 1674 + + PseudoVASUB_VV_M4_MASK = 1675 + + PseudoVASUB_VV_M8 = 1676 + + PseudoVASUB_VV_M8_MASK = 1677 + + PseudoVASUB_VV_MF2 = 1678 + + PseudoVASUB_VV_MF2_MASK = 1679 + + PseudoVASUB_VV_MF4 = 1680 + + PseudoVASUB_VV_MF4_MASK = 1681 + + PseudoVASUB_VV_MF8 = 1682 + + PseudoVASUB_VV_MF8_MASK = 1683 + + PseudoVASUB_VX_M1 = 1684 + + PseudoVASUB_VX_M1_MASK = 1685 + + PseudoVASUB_VX_M2 = 1686 + + PseudoVASUB_VX_M2_MASK = 1687 + + PseudoVASUB_VX_M4 = 1688 + + PseudoVASUB_VX_M4_MASK = 1689 + + PseudoVASUB_VX_M8 = 1690 + + PseudoVASUB_VX_M8_MASK = 1691 + + PseudoVASUB_VX_MF2 = 1692 + + PseudoVASUB_VX_MF2_MASK = 1693 + + PseudoVASUB_VX_MF4 = 1694 + + PseudoVASUB_VX_MF4_MASK = 1695 + + PseudoVASUB_VX_MF8 = 1696 + + PseudoVASUB_VX_MF8_MASK = 1697 + + PseudoVBREV8_V_M1 = 1698 + + PseudoVBREV8_V_M1_MASK = 1699 + + PseudoVBREV8_V_M2 = 1700 + + PseudoVBREV8_V_M2_MASK = 1701 + + PseudoVBREV8_V_M4 = 1702 + + PseudoVBREV8_V_M4_MASK = 1703 + + PseudoVBREV8_V_M8 = 1704 + + PseudoVBREV8_V_M8_MASK = 1705 + + PseudoVBREV8_V_MF2 = 1706 + + PseudoVBREV8_V_MF2_MASK = 1707 + + PseudoVBREV8_V_MF4 = 1708 + + PseudoVBREV8_V_MF4_MASK = 1709 + + PseudoVBREV8_V_MF8 = 1710 + + PseudoVBREV8_V_MF8_MASK = 1711 + + PseudoVBREV_V_M1 = 1712 + + PseudoVBREV_V_M1_MASK = 1713 + + PseudoVBREV_V_M2 = 1714 + + PseudoVBREV_V_M2_MASK = 1715 + + PseudoVBREV_V_M4 = 1716 + + PseudoVBREV_V_M4_MASK = 1717 + + PseudoVBREV_V_M8 = 1718 + + PseudoVBREV_V_M8_MASK = 1719 + + PseudoVBREV_V_MF2 = 1720 + + PseudoVBREV_V_MF2_MASK = 1721 + + PseudoVBREV_V_MF4 = 1722 + + PseudoVBREV_V_MF4_MASK = 1723 + + PseudoVBREV_V_MF8 = 1724 + + PseudoVBREV_V_MF8_MASK = 1725 + + PseudoVCLMULH_VV_M1 = 1726 + + PseudoVCLMULH_VV_M1_MASK = 1727 + + PseudoVCLMULH_VV_M2 = 1728 + + PseudoVCLMULH_VV_M2_MASK = 1729 + + PseudoVCLMULH_VV_M4 = 1730 + + PseudoVCLMULH_VV_M4_MASK = 1731 + + PseudoVCLMULH_VV_M8 = 1732 + + PseudoVCLMULH_VV_M8_MASK = 1733 + + PseudoVCLMULH_VV_MF2 = 1734 + + PseudoVCLMULH_VV_MF2_MASK = 1735 + + PseudoVCLMULH_VV_MF4 = 1736 + + PseudoVCLMULH_VV_MF4_MASK = 1737 + + PseudoVCLMULH_VV_MF8 = 1738 + + PseudoVCLMULH_VV_MF8_MASK = 1739 + + PseudoVCLMULH_VX_M1 = 1740 + + PseudoVCLMULH_VX_M1_MASK = 1741 + + PseudoVCLMULH_VX_M2 = 1742 + + PseudoVCLMULH_VX_M2_MASK = 1743 + + PseudoVCLMULH_VX_M4 = 1744 + + PseudoVCLMULH_VX_M4_MASK = 1745 + + PseudoVCLMULH_VX_M8 = 1746 + + PseudoVCLMULH_VX_M8_MASK = 1747 + + PseudoVCLMULH_VX_MF2 = 1748 + + PseudoVCLMULH_VX_MF2_MASK = 1749 + + PseudoVCLMULH_VX_MF4 = 1750 + + PseudoVCLMULH_VX_MF4_MASK = 1751 + + PseudoVCLMULH_VX_MF8 = 1752 + + PseudoVCLMULH_VX_MF8_MASK = 1753 + + PseudoVCLMUL_VV_M1 = 1754 + + PseudoVCLMUL_VV_M1_MASK = 1755 + + PseudoVCLMUL_VV_M2 = 1756 + + PseudoVCLMUL_VV_M2_MASK = 1757 + + PseudoVCLMUL_VV_M4 = 1758 + + PseudoVCLMUL_VV_M4_MASK = 1759 + + PseudoVCLMUL_VV_M8 = 1760 + + PseudoVCLMUL_VV_M8_MASK = 1761 + + PseudoVCLMUL_VV_MF2 = 1762 + + PseudoVCLMUL_VV_MF2_MASK = 1763 + + PseudoVCLMUL_VV_MF4 = 1764 + + PseudoVCLMUL_VV_MF4_MASK = 1765 + + PseudoVCLMUL_VV_MF8 = 1766 + + PseudoVCLMUL_VV_MF8_MASK = 1767 + + PseudoVCLMUL_VX_M1 = 1768 + + PseudoVCLMUL_VX_M1_MASK = 1769 + + PseudoVCLMUL_VX_M2 = 1770 + + PseudoVCLMUL_VX_M2_MASK = 1771 + + PseudoVCLMUL_VX_M4 = 1772 + + PseudoVCLMUL_VX_M4_MASK = 1773 + + PseudoVCLMUL_VX_M8 = 1774 + + PseudoVCLMUL_VX_M8_MASK = 1775 + + PseudoVCLMUL_VX_MF2 = 1776 + + PseudoVCLMUL_VX_MF2_MASK = 1777 + + PseudoVCLMUL_VX_MF4 = 1778 + + PseudoVCLMUL_VX_MF4_MASK = 1779 + + PseudoVCLMUL_VX_MF8 = 1780 + + PseudoVCLMUL_VX_MF8_MASK = 1781 + + PseudoVCLZ_V_M1 = 1782 + + PseudoVCLZ_V_M1_MASK = 1783 + + PseudoVCLZ_V_M2 = 1784 + + PseudoVCLZ_V_M2_MASK = 1785 + + PseudoVCLZ_V_M4 = 1786 + + PseudoVCLZ_V_M4_MASK = 1787 + + PseudoVCLZ_V_M8 = 1788 + + PseudoVCLZ_V_M8_MASK = 1789 + + PseudoVCLZ_V_MF2 = 1790 + + PseudoVCLZ_V_MF2_MASK = 1791 + + PseudoVCLZ_V_MF4 = 1792 + + PseudoVCLZ_V_MF4_MASK = 1793 + + PseudoVCLZ_V_MF8 = 1794 + + PseudoVCLZ_V_MF8_MASK = 1795 + + PseudoVCOMPRESS_VM_M1_E16 = 1796 + + PseudoVCOMPRESS_VM_M1_E32 = 1797 + + PseudoVCOMPRESS_VM_M1_E64 = 1798 + + PseudoVCOMPRESS_VM_M1_E8 = 1799 + + PseudoVCOMPRESS_VM_M2_E16 = 1800 + + PseudoVCOMPRESS_VM_M2_E32 = 1801 + + PseudoVCOMPRESS_VM_M2_E64 = 1802 + + PseudoVCOMPRESS_VM_M2_E8 = 1803 + + PseudoVCOMPRESS_VM_M4_E16 = 1804 + + PseudoVCOMPRESS_VM_M4_E32 = 1805 + + PseudoVCOMPRESS_VM_M4_E64 = 1806 + + PseudoVCOMPRESS_VM_M4_E8 = 1807 + + PseudoVCOMPRESS_VM_M8_E16 = 1808 + + PseudoVCOMPRESS_VM_M8_E32 = 1809 + + PseudoVCOMPRESS_VM_M8_E64 = 1810 + + PseudoVCOMPRESS_VM_M8_E8 = 1811 + + PseudoVCOMPRESS_VM_MF2_E16 = 1812 + + PseudoVCOMPRESS_VM_MF2_E32 = 1813 + + PseudoVCOMPRESS_VM_MF2_E8 = 1814 + + PseudoVCOMPRESS_VM_MF4_E16 = 1815 + + PseudoVCOMPRESS_VM_MF4_E8 = 1816 + + PseudoVCOMPRESS_VM_MF8_E8 = 1817 + + PseudoVCPOP_M_B1 = 1818 + + PseudoVCPOP_M_B16 = 1819 + + PseudoVCPOP_M_B16_MASK = 1820 + + PseudoVCPOP_M_B1_MASK = 1821 + + PseudoVCPOP_M_B2 = 1822 + + PseudoVCPOP_M_B2_MASK = 1823 + + PseudoVCPOP_M_B32 = 1824 + + PseudoVCPOP_M_B32_MASK = 1825 + + PseudoVCPOP_M_B4 = 1826 + + PseudoVCPOP_M_B4_MASK = 1827 + + PseudoVCPOP_M_B64 = 1828 + + PseudoVCPOP_M_B64_MASK = 1829 + + PseudoVCPOP_M_B8 = 1830 + + PseudoVCPOP_M_B8_MASK = 1831 + + PseudoVCPOP_V_M1 = 1832 + + PseudoVCPOP_V_M1_MASK = 1833 + + PseudoVCPOP_V_M2 = 1834 + + PseudoVCPOP_V_M2_MASK = 1835 + + PseudoVCPOP_V_M4 = 1836 + + PseudoVCPOP_V_M4_MASK = 1837 + + PseudoVCPOP_V_M8 = 1838 + + PseudoVCPOP_V_M8_MASK = 1839 + + PseudoVCPOP_V_MF2 = 1840 + + PseudoVCPOP_V_MF2_MASK = 1841 + + PseudoVCPOP_V_MF4 = 1842 + + PseudoVCPOP_V_MF4_MASK = 1843 + + PseudoVCPOP_V_MF8 = 1844 + + PseudoVCPOP_V_MF8_MASK = 1845 + + PseudoVCTZ_V_M1 = 1846 + + PseudoVCTZ_V_M1_MASK = 1847 + + PseudoVCTZ_V_M2 = 1848 + + PseudoVCTZ_V_M2_MASK = 1849 + + PseudoVCTZ_V_M4 = 1850 + + PseudoVCTZ_V_M4_MASK = 1851 + + PseudoVCTZ_V_M8 = 1852 + + PseudoVCTZ_V_M8_MASK = 1853 + + PseudoVCTZ_V_MF2 = 1854 + + PseudoVCTZ_V_MF2_MASK = 1855 + + PseudoVCTZ_V_MF4 = 1856 + + PseudoVCTZ_V_MF4_MASK = 1857 + + PseudoVCTZ_V_MF8 = 1858 + + PseudoVCTZ_V_MF8_MASK = 1859 + + PseudoVDIVU_VV_M1_E16 = 1860 + + PseudoVDIVU_VV_M1_E16_MASK = 1861 + + PseudoVDIVU_VV_M1_E32 = 1862 + + PseudoVDIVU_VV_M1_E32_MASK = 1863 + + PseudoVDIVU_VV_M1_E64 = 1864 + + PseudoVDIVU_VV_M1_E64_MASK = 1865 + + PseudoVDIVU_VV_M1_E8 = 1866 + + PseudoVDIVU_VV_M1_E8_MASK = 1867 + + PseudoVDIVU_VV_M2_E16 = 1868 + + PseudoVDIVU_VV_M2_E16_MASK = 1869 + + PseudoVDIVU_VV_M2_E32 = 1870 + + PseudoVDIVU_VV_M2_E32_MASK = 1871 + + PseudoVDIVU_VV_M2_E64 = 1872 + + PseudoVDIVU_VV_M2_E64_MASK = 1873 + + PseudoVDIVU_VV_M2_E8 = 1874 + + PseudoVDIVU_VV_M2_E8_MASK = 1875 + + PseudoVDIVU_VV_M4_E16 = 1876 + + PseudoVDIVU_VV_M4_E16_MASK = 1877 + + PseudoVDIVU_VV_M4_E32 = 1878 + + PseudoVDIVU_VV_M4_E32_MASK = 1879 + + PseudoVDIVU_VV_M4_E64 = 1880 + + PseudoVDIVU_VV_M4_E64_MASK = 1881 + + PseudoVDIVU_VV_M4_E8 = 1882 + + PseudoVDIVU_VV_M4_E8_MASK = 1883 + + PseudoVDIVU_VV_M8_E16 = 1884 + + PseudoVDIVU_VV_M8_E16_MASK = 1885 + + PseudoVDIVU_VV_M8_E32 = 1886 + + PseudoVDIVU_VV_M8_E32_MASK = 1887 + + PseudoVDIVU_VV_M8_E64 = 1888 + + PseudoVDIVU_VV_M8_E64_MASK = 1889 + + PseudoVDIVU_VV_M8_E8 = 1890 + + PseudoVDIVU_VV_M8_E8_MASK = 1891 + + PseudoVDIVU_VV_MF2_E16 = 1892 + + PseudoVDIVU_VV_MF2_E16_MASK = 1893 + + PseudoVDIVU_VV_MF2_E32 = 1894 + + PseudoVDIVU_VV_MF2_E32_MASK = 1895 + + PseudoVDIVU_VV_MF2_E8 = 1896 + + PseudoVDIVU_VV_MF2_E8_MASK = 1897 + + PseudoVDIVU_VV_MF4_E16 = 1898 + + PseudoVDIVU_VV_MF4_E16_MASK = 1899 + + PseudoVDIVU_VV_MF4_E8 = 1900 + + PseudoVDIVU_VV_MF4_E8_MASK = 1901 + + PseudoVDIVU_VV_MF8_E8 = 1902 + + PseudoVDIVU_VV_MF8_E8_MASK = 1903 + + PseudoVDIVU_VX_M1_E16 = 1904 + + PseudoVDIVU_VX_M1_E16_MASK = 1905 + + PseudoVDIVU_VX_M1_E32 = 1906 + + PseudoVDIVU_VX_M1_E32_MASK = 1907 + + PseudoVDIVU_VX_M1_E64 = 1908 + + PseudoVDIVU_VX_M1_E64_MASK = 1909 + + PseudoVDIVU_VX_M1_E8 = 1910 + + PseudoVDIVU_VX_M1_E8_MASK = 1911 + + PseudoVDIVU_VX_M2_E16 = 1912 + + PseudoVDIVU_VX_M2_E16_MASK = 1913 + + PseudoVDIVU_VX_M2_E32 = 1914 + + PseudoVDIVU_VX_M2_E32_MASK = 1915 + + PseudoVDIVU_VX_M2_E64 = 1916 + + PseudoVDIVU_VX_M2_E64_MASK = 1917 + + PseudoVDIVU_VX_M2_E8 = 1918 + + PseudoVDIVU_VX_M2_E8_MASK = 1919 + + PseudoVDIVU_VX_M4_E16 = 1920 + + PseudoVDIVU_VX_M4_E16_MASK = 1921 + + PseudoVDIVU_VX_M4_E32 = 1922 + + PseudoVDIVU_VX_M4_E32_MASK = 1923 + + PseudoVDIVU_VX_M4_E64 = 1924 + + PseudoVDIVU_VX_M4_E64_MASK = 1925 + + PseudoVDIVU_VX_M4_E8 = 1926 + + PseudoVDIVU_VX_M4_E8_MASK = 1927 + + PseudoVDIVU_VX_M8_E16 = 1928 + + PseudoVDIVU_VX_M8_E16_MASK = 1929 + + PseudoVDIVU_VX_M8_E32 = 1930 + + PseudoVDIVU_VX_M8_E32_MASK = 1931 + + PseudoVDIVU_VX_M8_E64 = 1932 + + PseudoVDIVU_VX_M8_E64_MASK = 1933 + + PseudoVDIVU_VX_M8_E8 = 1934 + + PseudoVDIVU_VX_M8_E8_MASK = 1935 + + PseudoVDIVU_VX_MF2_E16 = 1936 + + PseudoVDIVU_VX_MF2_E16_MASK = 1937 + + PseudoVDIVU_VX_MF2_E32 = 1938 + + PseudoVDIVU_VX_MF2_E32_MASK = 1939 + + PseudoVDIVU_VX_MF2_E8 = 1940 + + PseudoVDIVU_VX_MF2_E8_MASK = 1941 + + PseudoVDIVU_VX_MF4_E16 = 1942 + + PseudoVDIVU_VX_MF4_E16_MASK = 1943 + + PseudoVDIVU_VX_MF4_E8 = 1944 + + PseudoVDIVU_VX_MF4_E8_MASK = 1945 + + PseudoVDIVU_VX_MF8_E8 = 1946 + + PseudoVDIVU_VX_MF8_E8_MASK = 1947 + + PseudoVDIV_VV_M1_E16 = 1948 + + PseudoVDIV_VV_M1_E16_MASK = 1949 + + PseudoVDIV_VV_M1_E32 = 1950 + + PseudoVDIV_VV_M1_E32_MASK = 1951 + + PseudoVDIV_VV_M1_E64 = 1952 + + PseudoVDIV_VV_M1_E64_MASK = 1953 + + PseudoVDIV_VV_M1_E8 = 1954 + + PseudoVDIV_VV_M1_E8_MASK = 1955 + + PseudoVDIV_VV_M2_E16 = 1956 + + PseudoVDIV_VV_M2_E16_MASK = 1957 + + PseudoVDIV_VV_M2_E32 = 1958 + + PseudoVDIV_VV_M2_E32_MASK = 1959 + + PseudoVDIV_VV_M2_E64 = 1960 + + PseudoVDIV_VV_M2_E64_MASK = 1961 + + PseudoVDIV_VV_M2_E8 = 1962 + + PseudoVDIV_VV_M2_E8_MASK = 1963 + + PseudoVDIV_VV_M4_E16 = 1964 + + PseudoVDIV_VV_M4_E16_MASK = 1965 + + PseudoVDIV_VV_M4_E32 = 1966 + + PseudoVDIV_VV_M4_E32_MASK = 1967 + + PseudoVDIV_VV_M4_E64 = 1968 + + PseudoVDIV_VV_M4_E64_MASK = 1969 + + PseudoVDIV_VV_M4_E8 = 1970 + + PseudoVDIV_VV_M4_E8_MASK = 1971 + + PseudoVDIV_VV_M8_E16 = 1972 + + PseudoVDIV_VV_M8_E16_MASK = 1973 + + PseudoVDIV_VV_M8_E32 = 1974 + + PseudoVDIV_VV_M8_E32_MASK = 1975 + + PseudoVDIV_VV_M8_E64 = 1976 + + PseudoVDIV_VV_M8_E64_MASK = 1977 + + PseudoVDIV_VV_M8_E8 = 1978 + + PseudoVDIV_VV_M8_E8_MASK = 1979 + + PseudoVDIV_VV_MF2_E16 = 1980 + + PseudoVDIV_VV_MF2_E16_MASK = 1981 + + PseudoVDIV_VV_MF2_E32 = 1982 + + PseudoVDIV_VV_MF2_E32_MASK = 1983 + + PseudoVDIV_VV_MF2_E8 = 1984 + + PseudoVDIV_VV_MF2_E8_MASK = 1985 + + PseudoVDIV_VV_MF4_E16 = 1986 + + PseudoVDIV_VV_MF4_E16_MASK = 1987 + + PseudoVDIV_VV_MF4_E8 = 1988 + + PseudoVDIV_VV_MF4_E8_MASK = 1989 + + PseudoVDIV_VV_MF8_E8 = 1990 + + PseudoVDIV_VV_MF8_E8_MASK = 1991 + + PseudoVDIV_VX_M1_E16 = 1992 + + PseudoVDIV_VX_M1_E16_MASK = 1993 + + PseudoVDIV_VX_M1_E32 = 1994 + + PseudoVDIV_VX_M1_E32_MASK = 1995 + + PseudoVDIV_VX_M1_E64 = 1996 + + PseudoVDIV_VX_M1_E64_MASK = 1997 + + PseudoVDIV_VX_M1_E8 = 1998 + + PseudoVDIV_VX_M1_E8_MASK = 1999 + + PseudoVDIV_VX_M2_E16 = 2000 + + PseudoVDIV_VX_M2_E16_MASK = 2001 + + PseudoVDIV_VX_M2_E32 = 2002 + + PseudoVDIV_VX_M2_E32_MASK = 2003 + + PseudoVDIV_VX_M2_E64 = 2004 + + PseudoVDIV_VX_M2_E64_MASK = 2005 + + PseudoVDIV_VX_M2_E8 = 2006 + + PseudoVDIV_VX_M2_E8_MASK = 2007 + + PseudoVDIV_VX_M4_E16 = 2008 + + PseudoVDIV_VX_M4_E16_MASK = 2009 + + PseudoVDIV_VX_M4_E32 = 2010 + + PseudoVDIV_VX_M4_E32_MASK = 2011 + + PseudoVDIV_VX_M4_E64 = 2012 + + PseudoVDIV_VX_M4_E64_MASK = 2013 + + PseudoVDIV_VX_M4_E8 = 2014 + + PseudoVDIV_VX_M4_E8_MASK = 2015 + + PseudoVDIV_VX_M8_E16 = 2016 + + PseudoVDIV_VX_M8_E16_MASK = 2017 + + PseudoVDIV_VX_M8_E32 = 2018 + + PseudoVDIV_VX_M8_E32_MASK = 2019 + + PseudoVDIV_VX_M8_E64 = 2020 + + PseudoVDIV_VX_M8_E64_MASK = 2021 + + PseudoVDIV_VX_M8_E8 = 2022 + + PseudoVDIV_VX_M8_E8_MASK = 2023 + + PseudoVDIV_VX_MF2_E16 = 2024 + + PseudoVDIV_VX_MF2_E16_MASK = 2025 + + PseudoVDIV_VX_MF2_E32 = 2026 + + PseudoVDIV_VX_MF2_E32_MASK = 2027 + + PseudoVDIV_VX_MF2_E8 = 2028 + + PseudoVDIV_VX_MF2_E8_MASK = 2029 + + PseudoVDIV_VX_MF4_E16 = 2030 + + PseudoVDIV_VX_MF4_E16_MASK = 2031 + + PseudoVDIV_VX_MF4_E8 = 2032 + + PseudoVDIV_VX_MF4_E8_MASK = 2033 + + PseudoVDIV_VX_MF8_E8 = 2034 + + PseudoVDIV_VX_MF8_E8_MASK = 2035 + + PseudoVFADD_ALT_VFPR16_M1_E16 = 2036 + + PseudoVFADD_ALT_VFPR16_M1_E16_MASK = 2037 + + PseudoVFADD_ALT_VFPR16_M2_E16 = 2038 + + PseudoVFADD_ALT_VFPR16_M2_E16_MASK = 2039 + + PseudoVFADD_ALT_VFPR16_M4_E16 = 2040 + + PseudoVFADD_ALT_VFPR16_M4_E16_MASK = 2041 + + PseudoVFADD_ALT_VFPR16_M8_E16 = 2042 + + PseudoVFADD_ALT_VFPR16_M8_E16_MASK = 2043 + + PseudoVFADD_ALT_VFPR16_MF2_E16 = 2044 + + PseudoVFADD_ALT_VFPR16_MF2_E16_MASK = 2045 + + PseudoVFADD_ALT_VFPR16_MF4_E16 = 2046 + + PseudoVFADD_ALT_VFPR16_MF4_E16_MASK = 2047 + + PseudoVFADD_ALT_VV_M1_E16 = 2048 + + PseudoVFADD_ALT_VV_M1_E16_MASK = 2049 + + PseudoVFADD_ALT_VV_M2_E16 = 2050 + + PseudoVFADD_ALT_VV_M2_E16_MASK = 2051 + + PseudoVFADD_ALT_VV_M4_E16 = 2052 + + PseudoVFADD_ALT_VV_M4_E16_MASK = 2053 + + PseudoVFADD_ALT_VV_M8_E16 = 2054 + + PseudoVFADD_ALT_VV_M8_E16_MASK = 2055 + + PseudoVFADD_ALT_VV_MF2_E16 = 2056 + + PseudoVFADD_ALT_VV_MF2_E16_MASK = 2057 + + PseudoVFADD_ALT_VV_MF4_E16 = 2058 + + PseudoVFADD_ALT_VV_MF4_E16_MASK = 2059 + + PseudoVFADD_VFPR16_M1_E16 = 2060 + + PseudoVFADD_VFPR16_M1_E16_MASK = 2061 + + PseudoVFADD_VFPR16_M2_E16 = 2062 + + PseudoVFADD_VFPR16_M2_E16_MASK = 2063 + + PseudoVFADD_VFPR16_M4_E16 = 2064 + + PseudoVFADD_VFPR16_M4_E16_MASK = 2065 + + PseudoVFADD_VFPR16_M8_E16 = 2066 + + PseudoVFADD_VFPR16_M8_E16_MASK = 2067 + + PseudoVFADD_VFPR16_MF2_E16 = 2068 + + PseudoVFADD_VFPR16_MF2_E16_MASK = 2069 + + PseudoVFADD_VFPR16_MF4_E16 = 2070 + + PseudoVFADD_VFPR16_MF4_E16_MASK = 2071 + + PseudoVFADD_VFPR32_M1_E32 = 2072 + + PseudoVFADD_VFPR32_M1_E32_MASK = 2073 + + PseudoVFADD_VFPR32_M2_E32 = 2074 + + PseudoVFADD_VFPR32_M2_E32_MASK = 2075 + + PseudoVFADD_VFPR32_M4_E32 = 2076 + + PseudoVFADD_VFPR32_M4_E32_MASK = 2077 + + PseudoVFADD_VFPR32_M8_E32 = 2078 + + PseudoVFADD_VFPR32_M8_E32_MASK = 2079 + + PseudoVFADD_VFPR32_MF2_E32 = 2080 + + PseudoVFADD_VFPR32_MF2_E32_MASK = 2081 + + PseudoVFADD_VFPR64_M1_E64 = 2082 + + PseudoVFADD_VFPR64_M1_E64_MASK = 2083 + + PseudoVFADD_VFPR64_M2_E64 = 2084 + + PseudoVFADD_VFPR64_M2_E64_MASK = 2085 + + PseudoVFADD_VFPR64_M4_E64 = 2086 + + PseudoVFADD_VFPR64_M4_E64_MASK = 2087 + + PseudoVFADD_VFPR64_M8_E64 = 2088 + + PseudoVFADD_VFPR64_M8_E64_MASK = 2089 + + PseudoVFADD_VV_M1_E16 = 2090 + + PseudoVFADD_VV_M1_E16_MASK = 2091 + + PseudoVFADD_VV_M1_E32 = 2092 + + PseudoVFADD_VV_M1_E32_MASK = 2093 + + PseudoVFADD_VV_M1_E64 = 2094 + + PseudoVFADD_VV_M1_E64_MASK = 2095 + + PseudoVFADD_VV_M2_E16 = 2096 + + PseudoVFADD_VV_M2_E16_MASK = 2097 + + PseudoVFADD_VV_M2_E32 = 2098 + + PseudoVFADD_VV_M2_E32_MASK = 2099 + + PseudoVFADD_VV_M2_E64 = 2100 + + PseudoVFADD_VV_M2_E64_MASK = 2101 + + PseudoVFADD_VV_M4_E16 = 2102 + + PseudoVFADD_VV_M4_E16_MASK = 2103 + + PseudoVFADD_VV_M4_E32 = 2104 + + PseudoVFADD_VV_M4_E32_MASK = 2105 + + PseudoVFADD_VV_M4_E64 = 2106 + + PseudoVFADD_VV_M4_E64_MASK = 2107 + + PseudoVFADD_VV_M8_E16 = 2108 + + PseudoVFADD_VV_M8_E16_MASK = 2109 + + PseudoVFADD_VV_M8_E32 = 2110 + + PseudoVFADD_VV_M8_E32_MASK = 2111 + + PseudoVFADD_VV_M8_E64 = 2112 + + PseudoVFADD_VV_M8_E64_MASK = 2113 + + PseudoVFADD_VV_MF2_E16 = 2114 + + PseudoVFADD_VV_MF2_E16_MASK = 2115 + + PseudoVFADD_VV_MF2_E32 = 2116 + + PseudoVFADD_VV_MF2_E32_MASK = 2117 + + PseudoVFADD_VV_MF4_E16 = 2118 + + PseudoVFADD_VV_MF4_E16_MASK = 2119 + + PseudoVFCLASS_ALT_V_M1 = 2120 + + PseudoVFCLASS_ALT_V_M1_MASK = 2121 + + PseudoVFCLASS_ALT_V_M2 = 2122 + + PseudoVFCLASS_ALT_V_M2_MASK = 2123 + + PseudoVFCLASS_ALT_V_M4 = 2124 + + PseudoVFCLASS_ALT_V_M4_MASK = 2125 + + PseudoVFCLASS_ALT_V_M8 = 2126 + + PseudoVFCLASS_ALT_V_M8_MASK = 2127 + + PseudoVFCLASS_ALT_V_MF2 = 2128 + + PseudoVFCLASS_ALT_V_MF2_MASK = 2129 + + PseudoVFCLASS_ALT_V_MF4 = 2130 + + PseudoVFCLASS_ALT_V_MF4_MASK = 2131 + + PseudoVFCLASS_V_M1 = 2132 + + PseudoVFCLASS_V_M1_MASK = 2133 + + PseudoVFCLASS_V_M2 = 2134 + + PseudoVFCLASS_V_M2_MASK = 2135 + + PseudoVFCLASS_V_M4 = 2136 + + PseudoVFCLASS_V_M4_MASK = 2137 + + PseudoVFCLASS_V_M8 = 2138 + + PseudoVFCLASS_V_M8_MASK = 2139 + + PseudoVFCLASS_V_MF2 = 2140 + + PseudoVFCLASS_V_MF2_MASK = 2141 + + PseudoVFCLASS_V_MF4 = 2142 + + PseudoVFCLASS_V_MF4_MASK = 2143 + + PseudoVFCVT_F_XU_V_M1_E16 = 2144 + + PseudoVFCVT_F_XU_V_M1_E16_MASK = 2145 + + PseudoVFCVT_F_XU_V_M1_E32 = 2146 + + PseudoVFCVT_F_XU_V_M1_E32_MASK = 2147 + + PseudoVFCVT_F_XU_V_M1_E64 = 2148 + + PseudoVFCVT_F_XU_V_M1_E64_MASK = 2149 + + PseudoVFCVT_F_XU_V_M2_E16 = 2150 + + PseudoVFCVT_F_XU_V_M2_E16_MASK = 2151 + + PseudoVFCVT_F_XU_V_M2_E32 = 2152 + + PseudoVFCVT_F_XU_V_M2_E32_MASK = 2153 + + PseudoVFCVT_F_XU_V_M2_E64 = 2154 + + PseudoVFCVT_F_XU_V_M2_E64_MASK = 2155 + + PseudoVFCVT_F_XU_V_M4_E16 = 2156 + + PseudoVFCVT_F_XU_V_M4_E16_MASK = 2157 + + PseudoVFCVT_F_XU_V_M4_E32 = 2158 + + PseudoVFCVT_F_XU_V_M4_E32_MASK = 2159 + + PseudoVFCVT_F_XU_V_M4_E64 = 2160 + + PseudoVFCVT_F_XU_V_M4_E64_MASK = 2161 + + PseudoVFCVT_F_XU_V_M8_E16 = 2162 + + PseudoVFCVT_F_XU_V_M8_E16_MASK = 2163 + + PseudoVFCVT_F_XU_V_M8_E32 = 2164 + + PseudoVFCVT_F_XU_V_M8_E32_MASK = 2165 + + PseudoVFCVT_F_XU_V_M8_E64 = 2166 + + PseudoVFCVT_F_XU_V_M8_E64_MASK = 2167 + + PseudoVFCVT_F_XU_V_MF2_E16 = 2168 + + PseudoVFCVT_F_XU_V_MF2_E16_MASK = 2169 + + PseudoVFCVT_F_XU_V_MF2_E32 = 2170 + + PseudoVFCVT_F_XU_V_MF2_E32_MASK = 2171 + + PseudoVFCVT_F_XU_V_MF4_E16 = 2172 + + PseudoVFCVT_F_XU_V_MF4_E16_MASK = 2173 + + PseudoVFCVT_F_X_V_M1_E16 = 2174 + + PseudoVFCVT_F_X_V_M1_E16_MASK = 2175 + + PseudoVFCVT_F_X_V_M1_E32 = 2176 + + PseudoVFCVT_F_X_V_M1_E32_MASK = 2177 + + PseudoVFCVT_F_X_V_M1_E64 = 2178 + + PseudoVFCVT_F_X_V_M1_E64_MASK = 2179 + + PseudoVFCVT_F_X_V_M2_E16 = 2180 + + PseudoVFCVT_F_X_V_M2_E16_MASK = 2181 + + PseudoVFCVT_F_X_V_M2_E32 = 2182 + + PseudoVFCVT_F_X_V_M2_E32_MASK = 2183 + + PseudoVFCVT_F_X_V_M2_E64 = 2184 + + PseudoVFCVT_F_X_V_M2_E64_MASK = 2185 + + PseudoVFCVT_F_X_V_M4_E16 = 2186 + + PseudoVFCVT_F_X_V_M4_E16_MASK = 2187 + + PseudoVFCVT_F_X_V_M4_E32 = 2188 + + PseudoVFCVT_F_X_V_M4_E32_MASK = 2189 + + PseudoVFCVT_F_X_V_M4_E64 = 2190 + + PseudoVFCVT_F_X_V_M4_E64_MASK = 2191 + + PseudoVFCVT_F_X_V_M8_E16 = 2192 + + PseudoVFCVT_F_X_V_M8_E16_MASK = 2193 + + PseudoVFCVT_F_X_V_M8_E32 = 2194 + + PseudoVFCVT_F_X_V_M8_E32_MASK = 2195 + + PseudoVFCVT_F_X_V_M8_E64 = 2196 + + PseudoVFCVT_F_X_V_M8_E64_MASK = 2197 + + PseudoVFCVT_F_X_V_MF2_E16 = 2198 + + PseudoVFCVT_F_X_V_MF2_E16_MASK = 2199 + + PseudoVFCVT_F_X_V_MF2_E32 = 2200 + + PseudoVFCVT_F_X_V_MF2_E32_MASK = 2201 + + PseudoVFCVT_F_X_V_MF4_E16 = 2202 + + PseudoVFCVT_F_X_V_MF4_E16_MASK = 2203 + + PseudoVFCVT_RTZ_XU_F_V_M1 = 2204 + + PseudoVFCVT_RTZ_XU_F_V_M1_MASK = 2205 + + PseudoVFCVT_RTZ_XU_F_V_M2 = 2206 + + PseudoVFCVT_RTZ_XU_F_V_M2_MASK = 2207 + + PseudoVFCVT_RTZ_XU_F_V_M4 = 2208 + + PseudoVFCVT_RTZ_XU_F_V_M4_MASK = 2209 + + PseudoVFCVT_RTZ_XU_F_V_M8 = 2210 + + PseudoVFCVT_RTZ_XU_F_V_M8_MASK = 2211 + + PseudoVFCVT_RTZ_XU_F_V_MF2 = 2212 + + PseudoVFCVT_RTZ_XU_F_V_MF2_MASK = 2213 + + PseudoVFCVT_RTZ_XU_F_V_MF4 = 2214 + + PseudoVFCVT_RTZ_XU_F_V_MF4_MASK = 2215 + + PseudoVFCVT_RTZ_X_F_V_M1 = 2216 + + PseudoVFCVT_RTZ_X_F_V_M1_MASK = 2217 + + PseudoVFCVT_RTZ_X_F_V_M2 = 2218 + + PseudoVFCVT_RTZ_X_F_V_M2_MASK = 2219 + + PseudoVFCVT_RTZ_X_F_V_M4 = 2220 + + PseudoVFCVT_RTZ_X_F_V_M4_MASK = 2221 + + PseudoVFCVT_RTZ_X_F_V_M8 = 2222 + + PseudoVFCVT_RTZ_X_F_V_M8_MASK = 2223 + + PseudoVFCVT_RTZ_X_F_V_MF2 = 2224 + + PseudoVFCVT_RTZ_X_F_V_MF2_MASK = 2225 + + PseudoVFCVT_RTZ_X_F_V_MF4 = 2226 + + PseudoVFCVT_RTZ_X_F_V_MF4_MASK = 2227 + + PseudoVFCVT_XU_F_V_M1 = 2228 + + PseudoVFCVT_XU_F_V_M1_MASK = 2229 + + PseudoVFCVT_XU_F_V_M2 = 2230 + + PseudoVFCVT_XU_F_V_M2_MASK = 2231 + + PseudoVFCVT_XU_F_V_M4 = 2232 + + PseudoVFCVT_XU_F_V_M4_MASK = 2233 + + PseudoVFCVT_XU_F_V_M8 = 2234 + + PseudoVFCVT_XU_F_V_M8_MASK = 2235 + + PseudoVFCVT_XU_F_V_MF2 = 2236 + + PseudoVFCVT_XU_F_V_MF2_MASK = 2237 + + PseudoVFCVT_XU_F_V_MF4 = 2238 + + PseudoVFCVT_XU_F_V_MF4_MASK = 2239 + + PseudoVFCVT_X_F_V_M1 = 2240 + + PseudoVFCVT_X_F_V_M1_MASK = 2241 + + PseudoVFCVT_X_F_V_M2 = 2242 + + PseudoVFCVT_X_F_V_M2_MASK = 2243 + + PseudoVFCVT_X_F_V_M4 = 2244 + + PseudoVFCVT_X_F_V_M4_MASK = 2245 + + PseudoVFCVT_X_F_V_M8 = 2246 + + PseudoVFCVT_X_F_V_M8_MASK = 2247 + + PseudoVFCVT_X_F_V_MF2 = 2248 + + PseudoVFCVT_X_F_V_MF2_MASK = 2249 + + PseudoVFCVT_X_F_V_MF4 = 2250 + + PseudoVFCVT_X_F_V_MF4_MASK = 2251 + + PseudoVFDIV_VFPR16_M1_E16 = 2252 + + PseudoVFDIV_VFPR16_M1_E16_MASK = 2253 + + PseudoVFDIV_VFPR16_M2_E16 = 2254 + + PseudoVFDIV_VFPR16_M2_E16_MASK = 2255 + + PseudoVFDIV_VFPR16_M4_E16 = 2256 + + PseudoVFDIV_VFPR16_M4_E16_MASK = 2257 + + PseudoVFDIV_VFPR16_M8_E16 = 2258 + + PseudoVFDIV_VFPR16_M8_E16_MASK = 2259 + + PseudoVFDIV_VFPR16_MF2_E16 = 2260 + + PseudoVFDIV_VFPR16_MF2_E16_MASK = 2261 + + PseudoVFDIV_VFPR16_MF4_E16 = 2262 + + PseudoVFDIV_VFPR16_MF4_E16_MASK = 2263 + + PseudoVFDIV_VFPR32_M1_E32 = 2264 + + PseudoVFDIV_VFPR32_M1_E32_MASK = 2265 + + PseudoVFDIV_VFPR32_M2_E32 = 2266 + + PseudoVFDIV_VFPR32_M2_E32_MASK = 2267 + + PseudoVFDIV_VFPR32_M4_E32 = 2268 + + PseudoVFDIV_VFPR32_M4_E32_MASK = 2269 + + PseudoVFDIV_VFPR32_M8_E32 = 2270 + + PseudoVFDIV_VFPR32_M8_E32_MASK = 2271 + + PseudoVFDIV_VFPR32_MF2_E32 = 2272 + + PseudoVFDIV_VFPR32_MF2_E32_MASK = 2273 + + PseudoVFDIV_VFPR64_M1_E64 = 2274 + + PseudoVFDIV_VFPR64_M1_E64_MASK = 2275 + + PseudoVFDIV_VFPR64_M2_E64 = 2276 + + PseudoVFDIV_VFPR64_M2_E64_MASK = 2277 + + PseudoVFDIV_VFPR64_M4_E64 = 2278 + + PseudoVFDIV_VFPR64_M4_E64_MASK = 2279 + + PseudoVFDIV_VFPR64_M8_E64 = 2280 + + PseudoVFDIV_VFPR64_M8_E64_MASK = 2281 + + PseudoVFDIV_VV_M1_E16 = 2282 + + PseudoVFDIV_VV_M1_E16_MASK = 2283 + + PseudoVFDIV_VV_M1_E32 = 2284 + + PseudoVFDIV_VV_M1_E32_MASK = 2285 + + PseudoVFDIV_VV_M1_E64 = 2286 + + PseudoVFDIV_VV_M1_E64_MASK = 2287 + + PseudoVFDIV_VV_M2_E16 = 2288 + + PseudoVFDIV_VV_M2_E16_MASK = 2289 + + PseudoVFDIV_VV_M2_E32 = 2290 + + PseudoVFDIV_VV_M2_E32_MASK = 2291 + + PseudoVFDIV_VV_M2_E64 = 2292 + + PseudoVFDIV_VV_M2_E64_MASK = 2293 + + PseudoVFDIV_VV_M4_E16 = 2294 + + PseudoVFDIV_VV_M4_E16_MASK = 2295 + + PseudoVFDIV_VV_M4_E32 = 2296 + + PseudoVFDIV_VV_M4_E32_MASK = 2297 + + PseudoVFDIV_VV_M4_E64 = 2298 + + PseudoVFDIV_VV_M4_E64_MASK = 2299 + + PseudoVFDIV_VV_M8_E16 = 2300 + + PseudoVFDIV_VV_M8_E16_MASK = 2301 + + PseudoVFDIV_VV_M8_E32 = 2302 + + PseudoVFDIV_VV_M8_E32_MASK = 2303 + + PseudoVFDIV_VV_M8_E64 = 2304 + + PseudoVFDIV_VV_M8_E64_MASK = 2305 + + PseudoVFDIV_VV_MF2_E16 = 2306 + + PseudoVFDIV_VV_MF2_E16_MASK = 2307 + + PseudoVFDIV_VV_MF2_E32 = 2308 + + PseudoVFDIV_VV_MF2_E32_MASK = 2309 + + PseudoVFDIV_VV_MF4_E16 = 2310 + + PseudoVFDIV_VV_MF4_E16_MASK = 2311 + + PseudoVFIRST_M_B1 = 2312 + + PseudoVFIRST_M_B16 = 2313 + + PseudoVFIRST_M_B16_MASK = 2314 + + PseudoVFIRST_M_B1_MASK = 2315 + + PseudoVFIRST_M_B2 = 2316 + + PseudoVFIRST_M_B2_MASK = 2317 + + PseudoVFIRST_M_B32 = 2318 + + PseudoVFIRST_M_B32_MASK = 2319 + + PseudoVFIRST_M_B4 = 2320 + + PseudoVFIRST_M_B4_MASK = 2321 + + PseudoVFIRST_M_B64 = 2322 + + PseudoVFIRST_M_B64_MASK = 2323 + + PseudoVFIRST_M_B8 = 2324 + + PseudoVFIRST_M_B8_MASK = 2325 + + PseudoVFMACC_ALT_VFPR16_M1_E16 = 2326 + + PseudoVFMACC_ALT_VFPR16_M1_E16_MASK = 2327 + + PseudoVFMACC_ALT_VFPR16_M2_E16 = 2328 + + PseudoVFMACC_ALT_VFPR16_M2_E16_MASK = 2329 + + PseudoVFMACC_ALT_VFPR16_M4_E16 = 2330 + + PseudoVFMACC_ALT_VFPR16_M4_E16_MASK = 2331 + + PseudoVFMACC_ALT_VFPR16_M8_E16 = 2332 + + PseudoVFMACC_ALT_VFPR16_M8_E16_MASK = 2333 + + PseudoVFMACC_ALT_VFPR16_MF2_E16 = 2334 + + PseudoVFMACC_ALT_VFPR16_MF2_E16_MASK = 2335 + + PseudoVFMACC_ALT_VFPR16_MF4_E16 = 2336 + + PseudoVFMACC_ALT_VFPR16_MF4_E16_MASK = 2337 + + PseudoVFMACC_ALT_VV_M1_E16 = 2338 + + PseudoVFMACC_ALT_VV_M1_E16_MASK = 2339 + + PseudoVFMACC_ALT_VV_M2_E16 = 2340 + + PseudoVFMACC_ALT_VV_M2_E16_MASK = 2341 + + PseudoVFMACC_ALT_VV_M4_E16 = 2342 + + PseudoVFMACC_ALT_VV_M4_E16_MASK = 2343 + + PseudoVFMACC_ALT_VV_M8_E16 = 2344 + + PseudoVFMACC_ALT_VV_M8_E16_MASK = 2345 + + PseudoVFMACC_ALT_VV_MF2_E16 = 2346 + + PseudoVFMACC_ALT_VV_MF2_E16_MASK = 2347 + + PseudoVFMACC_ALT_VV_MF4_E16 = 2348 + + PseudoVFMACC_ALT_VV_MF4_E16_MASK = 2349 + + PseudoVFMACC_VFPR16_M1_E16 = 2350 + + PseudoVFMACC_VFPR16_M1_E16_MASK = 2351 + + PseudoVFMACC_VFPR16_M2_E16 = 2352 + + PseudoVFMACC_VFPR16_M2_E16_MASK = 2353 + + PseudoVFMACC_VFPR16_M4_E16 = 2354 + + PseudoVFMACC_VFPR16_M4_E16_MASK = 2355 + + PseudoVFMACC_VFPR16_M8_E16 = 2356 + + PseudoVFMACC_VFPR16_M8_E16_MASK = 2357 + + PseudoVFMACC_VFPR16_MF2_E16 = 2358 + + PseudoVFMACC_VFPR16_MF2_E16_MASK = 2359 + + PseudoVFMACC_VFPR16_MF4_E16 = 2360 + + PseudoVFMACC_VFPR16_MF4_E16_MASK = 2361 + + PseudoVFMACC_VFPR32_M1_E32 = 2362 + + PseudoVFMACC_VFPR32_M1_E32_MASK = 2363 + + PseudoVFMACC_VFPR32_M2_E32 = 2364 + + PseudoVFMACC_VFPR32_M2_E32_MASK = 2365 + + PseudoVFMACC_VFPR32_M4_E32 = 2366 + + PseudoVFMACC_VFPR32_M4_E32_MASK = 2367 + + PseudoVFMACC_VFPR32_M8_E32 = 2368 + + PseudoVFMACC_VFPR32_M8_E32_MASK = 2369 + + PseudoVFMACC_VFPR32_MF2_E32 = 2370 + + PseudoVFMACC_VFPR32_MF2_E32_MASK = 2371 + + PseudoVFMACC_VFPR64_M1_E64 = 2372 + + PseudoVFMACC_VFPR64_M1_E64_MASK = 2373 + + PseudoVFMACC_VFPR64_M2_E64 = 2374 + + PseudoVFMACC_VFPR64_M2_E64_MASK = 2375 + + PseudoVFMACC_VFPR64_M4_E64 = 2376 + + PseudoVFMACC_VFPR64_M4_E64_MASK = 2377 + + PseudoVFMACC_VFPR64_M8_E64 = 2378 + + PseudoVFMACC_VFPR64_M8_E64_MASK = 2379 + + PseudoVFMACC_VV_M1_E16 = 2380 + + PseudoVFMACC_VV_M1_E16_MASK = 2381 + + PseudoVFMACC_VV_M1_E32 = 2382 + + PseudoVFMACC_VV_M1_E32_MASK = 2383 + + PseudoVFMACC_VV_M1_E64 = 2384 + + PseudoVFMACC_VV_M1_E64_MASK = 2385 + + PseudoVFMACC_VV_M2_E16 = 2386 + + PseudoVFMACC_VV_M2_E16_MASK = 2387 + + PseudoVFMACC_VV_M2_E32 = 2388 + + PseudoVFMACC_VV_M2_E32_MASK = 2389 + + PseudoVFMACC_VV_M2_E64 = 2390 + + PseudoVFMACC_VV_M2_E64_MASK = 2391 + + PseudoVFMACC_VV_M4_E16 = 2392 + + PseudoVFMACC_VV_M4_E16_MASK = 2393 + + PseudoVFMACC_VV_M4_E32 = 2394 + + PseudoVFMACC_VV_M4_E32_MASK = 2395 + + PseudoVFMACC_VV_M4_E64 = 2396 + + PseudoVFMACC_VV_M4_E64_MASK = 2397 + + PseudoVFMACC_VV_M8_E16 = 2398 + + PseudoVFMACC_VV_M8_E16_MASK = 2399 + + PseudoVFMACC_VV_M8_E32 = 2400 + + PseudoVFMACC_VV_M8_E32_MASK = 2401 + + PseudoVFMACC_VV_M8_E64 = 2402 + + PseudoVFMACC_VV_M8_E64_MASK = 2403 + + PseudoVFMACC_VV_MF2_E16 = 2404 + + PseudoVFMACC_VV_MF2_E16_MASK = 2405 + + PseudoVFMACC_VV_MF2_E32 = 2406 + + PseudoVFMACC_VV_MF2_E32_MASK = 2407 + + PseudoVFMACC_VV_MF4_E16 = 2408 + + PseudoVFMACC_VV_MF4_E16_MASK = 2409 + + PseudoVFMADD_ALT_VFPR16_M1_E16 = 2410 + + PseudoVFMADD_ALT_VFPR16_M1_E16_MASK = 2411 + + PseudoVFMADD_ALT_VFPR16_M2_E16 = 2412 + + PseudoVFMADD_ALT_VFPR16_M2_E16_MASK = 2413 + + PseudoVFMADD_ALT_VFPR16_M4_E16 = 2414 + + PseudoVFMADD_ALT_VFPR16_M4_E16_MASK = 2415 + + PseudoVFMADD_ALT_VFPR16_M8_E16 = 2416 + + PseudoVFMADD_ALT_VFPR16_M8_E16_MASK = 2417 + + PseudoVFMADD_ALT_VFPR16_MF2_E16 = 2418 + + PseudoVFMADD_ALT_VFPR16_MF2_E16_MASK = 2419 + + PseudoVFMADD_ALT_VFPR16_MF4_E16 = 2420 + + PseudoVFMADD_ALT_VFPR16_MF4_E16_MASK = 2421 + + PseudoVFMADD_ALT_VV_M1_E16 = 2422 + + PseudoVFMADD_ALT_VV_M1_E16_MASK = 2423 + + PseudoVFMADD_ALT_VV_M2_E16 = 2424 + + PseudoVFMADD_ALT_VV_M2_E16_MASK = 2425 + + PseudoVFMADD_ALT_VV_M4_E16 = 2426 + + PseudoVFMADD_ALT_VV_M4_E16_MASK = 2427 + + PseudoVFMADD_ALT_VV_M8_E16 = 2428 + + PseudoVFMADD_ALT_VV_M8_E16_MASK = 2429 + + PseudoVFMADD_ALT_VV_MF2_E16 = 2430 + + PseudoVFMADD_ALT_VV_MF2_E16_MASK = 2431 + + PseudoVFMADD_ALT_VV_MF4_E16 = 2432 + + PseudoVFMADD_ALT_VV_MF4_E16_MASK = 2433 + + PseudoVFMADD_VFPR16_M1_E16 = 2434 + + PseudoVFMADD_VFPR16_M1_E16_MASK = 2435 + + PseudoVFMADD_VFPR16_M2_E16 = 2436 + + PseudoVFMADD_VFPR16_M2_E16_MASK = 2437 + + PseudoVFMADD_VFPR16_M4_E16 = 2438 + + PseudoVFMADD_VFPR16_M4_E16_MASK = 2439 + + PseudoVFMADD_VFPR16_M8_E16 = 2440 + + PseudoVFMADD_VFPR16_M8_E16_MASK = 2441 + + PseudoVFMADD_VFPR16_MF2_E16 = 2442 + + PseudoVFMADD_VFPR16_MF2_E16_MASK = 2443 + + PseudoVFMADD_VFPR16_MF4_E16 = 2444 + + PseudoVFMADD_VFPR16_MF4_E16_MASK = 2445 + + PseudoVFMADD_VFPR32_M1_E32 = 2446 + + PseudoVFMADD_VFPR32_M1_E32_MASK = 2447 + + PseudoVFMADD_VFPR32_M2_E32 = 2448 + + PseudoVFMADD_VFPR32_M2_E32_MASK = 2449 + + PseudoVFMADD_VFPR32_M4_E32 = 2450 + + PseudoVFMADD_VFPR32_M4_E32_MASK = 2451 + + PseudoVFMADD_VFPR32_M8_E32 = 2452 + + PseudoVFMADD_VFPR32_M8_E32_MASK = 2453 + + PseudoVFMADD_VFPR32_MF2_E32 = 2454 + + PseudoVFMADD_VFPR32_MF2_E32_MASK = 2455 + + PseudoVFMADD_VFPR64_M1_E64 = 2456 + + PseudoVFMADD_VFPR64_M1_E64_MASK = 2457 + + PseudoVFMADD_VFPR64_M2_E64 = 2458 + + PseudoVFMADD_VFPR64_M2_E64_MASK = 2459 + + PseudoVFMADD_VFPR64_M4_E64 = 2460 + + PseudoVFMADD_VFPR64_M4_E64_MASK = 2461 + + PseudoVFMADD_VFPR64_M8_E64 = 2462 + + PseudoVFMADD_VFPR64_M8_E64_MASK = 2463 + + PseudoVFMADD_VV_M1_E16 = 2464 + + PseudoVFMADD_VV_M1_E16_MASK = 2465 + + PseudoVFMADD_VV_M1_E32 = 2466 + + PseudoVFMADD_VV_M1_E32_MASK = 2467 + + PseudoVFMADD_VV_M1_E64 = 2468 + + PseudoVFMADD_VV_M1_E64_MASK = 2469 + + PseudoVFMADD_VV_M2_E16 = 2470 + + PseudoVFMADD_VV_M2_E16_MASK = 2471 + + PseudoVFMADD_VV_M2_E32 = 2472 + + PseudoVFMADD_VV_M2_E32_MASK = 2473 + + PseudoVFMADD_VV_M2_E64 = 2474 + + PseudoVFMADD_VV_M2_E64_MASK = 2475 + + PseudoVFMADD_VV_M4_E16 = 2476 + + PseudoVFMADD_VV_M4_E16_MASK = 2477 + + PseudoVFMADD_VV_M4_E32 = 2478 + + PseudoVFMADD_VV_M4_E32_MASK = 2479 + + PseudoVFMADD_VV_M4_E64 = 2480 + + PseudoVFMADD_VV_M4_E64_MASK = 2481 + + PseudoVFMADD_VV_M8_E16 = 2482 + + PseudoVFMADD_VV_M8_E16_MASK = 2483 + + PseudoVFMADD_VV_M8_E32 = 2484 + + PseudoVFMADD_VV_M8_E32_MASK = 2485 + + PseudoVFMADD_VV_M8_E64 = 2486 + + PseudoVFMADD_VV_M8_E64_MASK = 2487 + + PseudoVFMADD_VV_MF2_E16 = 2488 + + PseudoVFMADD_VV_MF2_E16_MASK = 2489 + + PseudoVFMADD_VV_MF2_E32 = 2490 + + PseudoVFMADD_VV_MF2_E32_MASK = 2491 + + PseudoVFMADD_VV_MF4_E16 = 2492 + + PseudoVFMADD_VV_MF4_E16_MASK = 2493 + + PseudoVFMAX_ALT_VFPR16_M1_E16 = 2494 + + PseudoVFMAX_ALT_VFPR16_M1_E16_MASK = 2495 + + PseudoVFMAX_ALT_VFPR16_M2_E16 = 2496 + + PseudoVFMAX_ALT_VFPR16_M2_E16_MASK = 2497 + + PseudoVFMAX_ALT_VFPR16_M4_E16 = 2498 + + PseudoVFMAX_ALT_VFPR16_M4_E16_MASK = 2499 + + PseudoVFMAX_ALT_VFPR16_M8_E16 = 2500 + + PseudoVFMAX_ALT_VFPR16_M8_E16_MASK = 2501 + + PseudoVFMAX_ALT_VFPR16_MF2_E16 = 2502 + + PseudoVFMAX_ALT_VFPR16_MF2_E16_MASK = 2503 + + PseudoVFMAX_ALT_VFPR16_MF4_E16 = 2504 + + PseudoVFMAX_ALT_VFPR16_MF4_E16_MASK = 2505 + + PseudoVFMAX_ALT_VV_M1_E16 = 2506 + + PseudoVFMAX_ALT_VV_M1_E16_MASK = 2507 + + PseudoVFMAX_ALT_VV_M2_E16 = 2508 + + PseudoVFMAX_ALT_VV_M2_E16_MASK = 2509 + + PseudoVFMAX_ALT_VV_M4_E16 = 2510 + + PseudoVFMAX_ALT_VV_M4_E16_MASK = 2511 + + PseudoVFMAX_ALT_VV_M8_E16 = 2512 + + PseudoVFMAX_ALT_VV_M8_E16_MASK = 2513 + + PseudoVFMAX_ALT_VV_MF2_E16 = 2514 + + PseudoVFMAX_ALT_VV_MF2_E16_MASK = 2515 + + PseudoVFMAX_ALT_VV_MF4_E16 = 2516 + + PseudoVFMAX_ALT_VV_MF4_E16_MASK = 2517 + + PseudoVFMAX_VFPR16_M1_E16 = 2518 + + PseudoVFMAX_VFPR16_M1_E16_MASK = 2519 + + PseudoVFMAX_VFPR16_M2_E16 = 2520 + + PseudoVFMAX_VFPR16_M2_E16_MASK = 2521 + + PseudoVFMAX_VFPR16_M4_E16 = 2522 + + PseudoVFMAX_VFPR16_M4_E16_MASK = 2523 + + PseudoVFMAX_VFPR16_M8_E16 = 2524 + + PseudoVFMAX_VFPR16_M8_E16_MASK = 2525 + + PseudoVFMAX_VFPR16_MF2_E16 = 2526 + + PseudoVFMAX_VFPR16_MF2_E16_MASK = 2527 + + PseudoVFMAX_VFPR16_MF4_E16 = 2528 + + PseudoVFMAX_VFPR16_MF4_E16_MASK = 2529 + + PseudoVFMAX_VFPR32_M1_E32 = 2530 + + PseudoVFMAX_VFPR32_M1_E32_MASK = 2531 + + PseudoVFMAX_VFPR32_M2_E32 = 2532 + + PseudoVFMAX_VFPR32_M2_E32_MASK = 2533 + + PseudoVFMAX_VFPR32_M4_E32 = 2534 + + PseudoVFMAX_VFPR32_M4_E32_MASK = 2535 + + PseudoVFMAX_VFPR32_M8_E32 = 2536 + + PseudoVFMAX_VFPR32_M8_E32_MASK = 2537 + + PseudoVFMAX_VFPR32_MF2_E32 = 2538 + + PseudoVFMAX_VFPR32_MF2_E32_MASK = 2539 + + PseudoVFMAX_VFPR64_M1_E64 = 2540 + + PseudoVFMAX_VFPR64_M1_E64_MASK = 2541 + + PseudoVFMAX_VFPR64_M2_E64 = 2542 + + PseudoVFMAX_VFPR64_M2_E64_MASK = 2543 + + PseudoVFMAX_VFPR64_M4_E64 = 2544 + + PseudoVFMAX_VFPR64_M4_E64_MASK = 2545 + + PseudoVFMAX_VFPR64_M8_E64 = 2546 + + PseudoVFMAX_VFPR64_M8_E64_MASK = 2547 + + PseudoVFMAX_VV_M1_E16 = 2548 + + PseudoVFMAX_VV_M1_E16_MASK = 2549 + + PseudoVFMAX_VV_M1_E32 = 2550 + + PseudoVFMAX_VV_M1_E32_MASK = 2551 + + PseudoVFMAX_VV_M1_E64 = 2552 + + PseudoVFMAX_VV_M1_E64_MASK = 2553 + + PseudoVFMAX_VV_M2_E16 = 2554 + + PseudoVFMAX_VV_M2_E16_MASK = 2555 + + PseudoVFMAX_VV_M2_E32 = 2556 + + PseudoVFMAX_VV_M2_E32_MASK = 2557 + + PseudoVFMAX_VV_M2_E64 = 2558 + + PseudoVFMAX_VV_M2_E64_MASK = 2559 + + PseudoVFMAX_VV_M4_E16 = 2560 + + PseudoVFMAX_VV_M4_E16_MASK = 2561 + + PseudoVFMAX_VV_M4_E32 = 2562 + + PseudoVFMAX_VV_M4_E32_MASK = 2563 + + PseudoVFMAX_VV_M4_E64 = 2564 + + PseudoVFMAX_VV_M4_E64_MASK = 2565 + + PseudoVFMAX_VV_M8_E16 = 2566 + + PseudoVFMAX_VV_M8_E16_MASK = 2567 + + PseudoVFMAX_VV_M8_E32 = 2568 + + PseudoVFMAX_VV_M8_E32_MASK = 2569 + + PseudoVFMAX_VV_M8_E64 = 2570 + + PseudoVFMAX_VV_M8_E64_MASK = 2571 + + PseudoVFMAX_VV_MF2_E16 = 2572 + + PseudoVFMAX_VV_MF2_E16_MASK = 2573 + + PseudoVFMAX_VV_MF2_E32 = 2574 + + PseudoVFMAX_VV_MF2_E32_MASK = 2575 + + PseudoVFMAX_VV_MF4_E16 = 2576 + + PseudoVFMAX_VV_MF4_E16_MASK = 2577 + + PseudoVFMERGE_ALT_VFPR16M_M1 = 2578 + + PseudoVFMERGE_ALT_VFPR16M_M2 = 2579 + + PseudoVFMERGE_ALT_VFPR16M_M4 = 2580 + + PseudoVFMERGE_ALT_VFPR16M_M8 = 2581 + + PseudoVFMERGE_ALT_VFPR16M_MF2 = 2582 + + PseudoVFMERGE_ALT_VFPR16M_MF4 = 2583 + + PseudoVFMERGE_ALT_VFPR32M_M1 = 2584 + + PseudoVFMERGE_ALT_VFPR32M_M2 = 2585 + + PseudoVFMERGE_ALT_VFPR32M_M4 = 2586 + + PseudoVFMERGE_ALT_VFPR32M_M8 = 2587 + + PseudoVFMERGE_ALT_VFPR32M_MF2 = 2588 + + PseudoVFMERGE_ALT_VFPR64M_M1 = 2589 + + PseudoVFMERGE_ALT_VFPR64M_M2 = 2590 + + PseudoVFMERGE_ALT_VFPR64M_M4 = 2591 + + PseudoVFMERGE_ALT_VFPR64M_M8 = 2592 + + PseudoVFMERGE_VFPR16M_M1 = 2593 + + PseudoVFMERGE_VFPR16M_M2 = 2594 + + PseudoVFMERGE_VFPR16M_M4 = 2595 + + PseudoVFMERGE_VFPR16M_M8 = 2596 + + PseudoVFMERGE_VFPR16M_MF2 = 2597 + + PseudoVFMERGE_VFPR16M_MF4 = 2598 + + PseudoVFMERGE_VFPR32M_M1 = 2599 + + PseudoVFMERGE_VFPR32M_M2 = 2600 + + PseudoVFMERGE_VFPR32M_M4 = 2601 + + PseudoVFMERGE_VFPR32M_M8 = 2602 + + PseudoVFMERGE_VFPR32M_MF2 = 2603 + + PseudoVFMERGE_VFPR64M_M1 = 2604 + + PseudoVFMERGE_VFPR64M_M2 = 2605 + + PseudoVFMERGE_VFPR64M_M4 = 2606 + + PseudoVFMERGE_VFPR64M_M8 = 2607 + + PseudoVFMIN_ALT_VFPR16_M1_E16 = 2608 + + PseudoVFMIN_ALT_VFPR16_M1_E16_MASK = 2609 + + PseudoVFMIN_ALT_VFPR16_M2_E16 = 2610 + + PseudoVFMIN_ALT_VFPR16_M2_E16_MASK = 2611 + + PseudoVFMIN_ALT_VFPR16_M4_E16 = 2612 + + PseudoVFMIN_ALT_VFPR16_M4_E16_MASK = 2613 + + PseudoVFMIN_ALT_VFPR16_M8_E16 = 2614 + + PseudoVFMIN_ALT_VFPR16_M8_E16_MASK = 2615 + + PseudoVFMIN_ALT_VFPR16_MF2_E16 = 2616 + + PseudoVFMIN_ALT_VFPR16_MF2_E16_MASK = 2617 + + PseudoVFMIN_ALT_VFPR16_MF4_E16 = 2618 + + PseudoVFMIN_ALT_VFPR16_MF4_E16_MASK = 2619 + + PseudoVFMIN_ALT_VV_M1_E16 = 2620 + + PseudoVFMIN_ALT_VV_M1_E16_MASK = 2621 + + PseudoVFMIN_ALT_VV_M2_E16 = 2622 + + PseudoVFMIN_ALT_VV_M2_E16_MASK = 2623 + + PseudoVFMIN_ALT_VV_M4_E16 = 2624 + + PseudoVFMIN_ALT_VV_M4_E16_MASK = 2625 + + PseudoVFMIN_ALT_VV_M8_E16 = 2626 + + PseudoVFMIN_ALT_VV_M8_E16_MASK = 2627 + + PseudoVFMIN_ALT_VV_MF2_E16 = 2628 + + PseudoVFMIN_ALT_VV_MF2_E16_MASK = 2629 + + PseudoVFMIN_ALT_VV_MF4_E16 = 2630 + + PseudoVFMIN_ALT_VV_MF4_E16_MASK = 2631 + + PseudoVFMIN_VFPR16_M1_E16 = 2632 + + PseudoVFMIN_VFPR16_M1_E16_MASK = 2633 + + PseudoVFMIN_VFPR16_M2_E16 = 2634 + + PseudoVFMIN_VFPR16_M2_E16_MASK = 2635 + + PseudoVFMIN_VFPR16_M4_E16 = 2636 + + PseudoVFMIN_VFPR16_M4_E16_MASK = 2637 + + PseudoVFMIN_VFPR16_M8_E16 = 2638 + + PseudoVFMIN_VFPR16_M8_E16_MASK = 2639 + + PseudoVFMIN_VFPR16_MF2_E16 = 2640 + + PseudoVFMIN_VFPR16_MF2_E16_MASK = 2641 + + PseudoVFMIN_VFPR16_MF4_E16 = 2642 + + PseudoVFMIN_VFPR16_MF4_E16_MASK = 2643 + + PseudoVFMIN_VFPR32_M1_E32 = 2644 + + PseudoVFMIN_VFPR32_M1_E32_MASK = 2645 + + PseudoVFMIN_VFPR32_M2_E32 = 2646 + + PseudoVFMIN_VFPR32_M2_E32_MASK = 2647 + + PseudoVFMIN_VFPR32_M4_E32 = 2648 + + PseudoVFMIN_VFPR32_M4_E32_MASK = 2649 + + PseudoVFMIN_VFPR32_M8_E32 = 2650 + + PseudoVFMIN_VFPR32_M8_E32_MASK = 2651 + + PseudoVFMIN_VFPR32_MF2_E32 = 2652 + + PseudoVFMIN_VFPR32_MF2_E32_MASK = 2653 + + PseudoVFMIN_VFPR64_M1_E64 = 2654 + + PseudoVFMIN_VFPR64_M1_E64_MASK = 2655 + + PseudoVFMIN_VFPR64_M2_E64 = 2656 + + PseudoVFMIN_VFPR64_M2_E64_MASK = 2657 + + PseudoVFMIN_VFPR64_M4_E64 = 2658 + + PseudoVFMIN_VFPR64_M4_E64_MASK = 2659 + + PseudoVFMIN_VFPR64_M8_E64 = 2660 + + PseudoVFMIN_VFPR64_M8_E64_MASK = 2661 + + PseudoVFMIN_VV_M1_E16 = 2662 + + PseudoVFMIN_VV_M1_E16_MASK = 2663 + + PseudoVFMIN_VV_M1_E32 = 2664 + + PseudoVFMIN_VV_M1_E32_MASK = 2665 + + PseudoVFMIN_VV_M1_E64 = 2666 + + PseudoVFMIN_VV_M1_E64_MASK = 2667 + + PseudoVFMIN_VV_M2_E16 = 2668 + + PseudoVFMIN_VV_M2_E16_MASK = 2669 + + PseudoVFMIN_VV_M2_E32 = 2670 + + PseudoVFMIN_VV_M2_E32_MASK = 2671 + + PseudoVFMIN_VV_M2_E64 = 2672 + + PseudoVFMIN_VV_M2_E64_MASK = 2673 + + PseudoVFMIN_VV_M4_E16 = 2674 + + PseudoVFMIN_VV_M4_E16_MASK = 2675 + + PseudoVFMIN_VV_M4_E32 = 2676 + + PseudoVFMIN_VV_M4_E32_MASK = 2677 + + PseudoVFMIN_VV_M4_E64 = 2678 + + PseudoVFMIN_VV_M4_E64_MASK = 2679 + + PseudoVFMIN_VV_M8_E16 = 2680 + + PseudoVFMIN_VV_M8_E16_MASK = 2681 + + PseudoVFMIN_VV_M8_E32 = 2682 + + PseudoVFMIN_VV_M8_E32_MASK = 2683 + + PseudoVFMIN_VV_M8_E64 = 2684 + + PseudoVFMIN_VV_M8_E64_MASK = 2685 + + PseudoVFMIN_VV_MF2_E16 = 2686 + + PseudoVFMIN_VV_MF2_E16_MASK = 2687 + + PseudoVFMIN_VV_MF2_E32 = 2688 + + PseudoVFMIN_VV_MF2_E32_MASK = 2689 + + PseudoVFMIN_VV_MF4_E16 = 2690 + + PseudoVFMIN_VV_MF4_E16_MASK = 2691 + + PseudoVFMSAC_ALT_VFPR16_M1_E16 = 2692 + + PseudoVFMSAC_ALT_VFPR16_M1_E16_MASK = 2693 + + PseudoVFMSAC_ALT_VFPR16_M2_E16 = 2694 + + PseudoVFMSAC_ALT_VFPR16_M2_E16_MASK = 2695 + + PseudoVFMSAC_ALT_VFPR16_M4_E16 = 2696 + + PseudoVFMSAC_ALT_VFPR16_M4_E16_MASK = 2697 + + PseudoVFMSAC_ALT_VFPR16_M8_E16 = 2698 + + PseudoVFMSAC_ALT_VFPR16_M8_E16_MASK = 2699 + + PseudoVFMSAC_ALT_VFPR16_MF2_E16 = 2700 + + PseudoVFMSAC_ALT_VFPR16_MF2_E16_MASK = 2701 + + PseudoVFMSAC_ALT_VFPR16_MF4_E16 = 2702 + + PseudoVFMSAC_ALT_VFPR16_MF4_E16_MASK = 2703 + + PseudoVFMSAC_ALT_VV_M1_E16 = 2704 + + PseudoVFMSAC_ALT_VV_M1_E16_MASK = 2705 + + PseudoVFMSAC_ALT_VV_M2_E16 = 2706 + + PseudoVFMSAC_ALT_VV_M2_E16_MASK = 2707 + + PseudoVFMSAC_ALT_VV_M4_E16 = 2708 + + PseudoVFMSAC_ALT_VV_M4_E16_MASK = 2709 + + PseudoVFMSAC_ALT_VV_M8_E16 = 2710 + + PseudoVFMSAC_ALT_VV_M8_E16_MASK = 2711 + + PseudoVFMSAC_ALT_VV_MF2_E16 = 2712 + + PseudoVFMSAC_ALT_VV_MF2_E16_MASK = 2713 + + PseudoVFMSAC_ALT_VV_MF4_E16 = 2714 + + PseudoVFMSAC_ALT_VV_MF4_E16_MASK = 2715 + + PseudoVFMSAC_VFPR16_M1_E16 = 2716 + + PseudoVFMSAC_VFPR16_M1_E16_MASK = 2717 + + PseudoVFMSAC_VFPR16_M2_E16 = 2718 + + PseudoVFMSAC_VFPR16_M2_E16_MASK = 2719 + + PseudoVFMSAC_VFPR16_M4_E16 = 2720 + + PseudoVFMSAC_VFPR16_M4_E16_MASK = 2721 + + PseudoVFMSAC_VFPR16_M8_E16 = 2722 + + PseudoVFMSAC_VFPR16_M8_E16_MASK = 2723 + + PseudoVFMSAC_VFPR16_MF2_E16 = 2724 + + PseudoVFMSAC_VFPR16_MF2_E16_MASK = 2725 + + PseudoVFMSAC_VFPR16_MF4_E16 = 2726 + + PseudoVFMSAC_VFPR16_MF4_E16_MASK = 2727 + + PseudoVFMSAC_VFPR32_M1_E32 = 2728 + + PseudoVFMSAC_VFPR32_M1_E32_MASK = 2729 + + PseudoVFMSAC_VFPR32_M2_E32 = 2730 + + PseudoVFMSAC_VFPR32_M2_E32_MASK = 2731 + + PseudoVFMSAC_VFPR32_M4_E32 = 2732 + + PseudoVFMSAC_VFPR32_M4_E32_MASK = 2733 + + PseudoVFMSAC_VFPR32_M8_E32 = 2734 + + PseudoVFMSAC_VFPR32_M8_E32_MASK = 2735 + + PseudoVFMSAC_VFPR32_MF2_E32 = 2736 + + PseudoVFMSAC_VFPR32_MF2_E32_MASK = 2737 + + PseudoVFMSAC_VFPR64_M1_E64 = 2738 + + PseudoVFMSAC_VFPR64_M1_E64_MASK = 2739 + + PseudoVFMSAC_VFPR64_M2_E64 = 2740 + + PseudoVFMSAC_VFPR64_M2_E64_MASK = 2741 + + PseudoVFMSAC_VFPR64_M4_E64 = 2742 + + PseudoVFMSAC_VFPR64_M4_E64_MASK = 2743 + + PseudoVFMSAC_VFPR64_M8_E64 = 2744 + + PseudoVFMSAC_VFPR64_M8_E64_MASK = 2745 + + PseudoVFMSAC_VV_M1_E16 = 2746 + + PseudoVFMSAC_VV_M1_E16_MASK = 2747 + + PseudoVFMSAC_VV_M1_E32 = 2748 + + PseudoVFMSAC_VV_M1_E32_MASK = 2749 + + PseudoVFMSAC_VV_M1_E64 = 2750 + + PseudoVFMSAC_VV_M1_E64_MASK = 2751 + + PseudoVFMSAC_VV_M2_E16 = 2752 + + PseudoVFMSAC_VV_M2_E16_MASK = 2753 + + PseudoVFMSAC_VV_M2_E32 = 2754 + + PseudoVFMSAC_VV_M2_E32_MASK = 2755 + + PseudoVFMSAC_VV_M2_E64 = 2756 + + PseudoVFMSAC_VV_M2_E64_MASK = 2757 + + PseudoVFMSAC_VV_M4_E16 = 2758 + + PseudoVFMSAC_VV_M4_E16_MASK = 2759 + + PseudoVFMSAC_VV_M4_E32 = 2760 + + PseudoVFMSAC_VV_M4_E32_MASK = 2761 + + PseudoVFMSAC_VV_M4_E64 = 2762 + + PseudoVFMSAC_VV_M4_E64_MASK = 2763 + + PseudoVFMSAC_VV_M8_E16 = 2764 + + PseudoVFMSAC_VV_M8_E16_MASK = 2765 + + PseudoVFMSAC_VV_M8_E32 = 2766 + + PseudoVFMSAC_VV_M8_E32_MASK = 2767 + + PseudoVFMSAC_VV_M8_E64 = 2768 + + PseudoVFMSAC_VV_M8_E64_MASK = 2769 + + PseudoVFMSAC_VV_MF2_E16 = 2770 + + PseudoVFMSAC_VV_MF2_E16_MASK = 2771 + + PseudoVFMSAC_VV_MF2_E32 = 2772 + + PseudoVFMSAC_VV_MF2_E32_MASK = 2773 + + PseudoVFMSAC_VV_MF4_E16 = 2774 + + PseudoVFMSAC_VV_MF4_E16_MASK = 2775 + + PseudoVFMSUB_ALT_VFPR16_M1_E16 = 2776 + + PseudoVFMSUB_ALT_VFPR16_M1_E16_MASK = 2777 + + PseudoVFMSUB_ALT_VFPR16_M2_E16 = 2778 + + PseudoVFMSUB_ALT_VFPR16_M2_E16_MASK = 2779 + + PseudoVFMSUB_ALT_VFPR16_M4_E16 = 2780 + + PseudoVFMSUB_ALT_VFPR16_M4_E16_MASK = 2781 + + PseudoVFMSUB_ALT_VFPR16_M8_E16 = 2782 + + PseudoVFMSUB_ALT_VFPR16_M8_E16_MASK = 2783 + + PseudoVFMSUB_ALT_VFPR16_MF2_E16 = 2784 + + PseudoVFMSUB_ALT_VFPR16_MF2_E16_MASK = 2785 + + PseudoVFMSUB_ALT_VFPR16_MF4_E16 = 2786 + + PseudoVFMSUB_ALT_VFPR16_MF4_E16_MASK = 2787 + + PseudoVFMSUB_ALT_VV_M1_E16 = 2788 + + PseudoVFMSUB_ALT_VV_M1_E16_MASK = 2789 + + PseudoVFMSUB_ALT_VV_M2_E16 = 2790 + + PseudoVFMSUB_ALT_VV_M2_E16_MASK = 2791 + + PseudoVFMSUB_ALT_VV_M4_E16 = 2792 + + PseudoVFMSUB_ALT_VV_M4_E16_MASK = 2793 + + PseudoVFMSUB_ALT_VV_M8_E16 = 2794 + + PseudoVFMSUB_ALT_VV_M8_E16_MASK = 2795 + + PseudoVFMSUB_ALT_VV_MF2_E16 = 2796 + + PseudoVFMSUB_ALT_VV_MF2_E16_MASK = 2797 + + PseudoVFMSUB_ALT_VV_MF4_E16 = 2798 + + PseudoVFMSUB_ALT_VV_MF4_E16_MASK = 2799 + + PseudoVFMSUB_VFPR16_M1_E16 = 2800 + + PseudoVFMSUB_VFPR16_M1_E16_MASK = 2801 + + PseudoVFMSUB_VFPR16_M2_E16 = 2802 + + PseudoVFMSUB_VFPR16_M2_E16_MASK = 2803 + + PseudoVFMSUB_VFPR16_M4_E16 = 2804 + + PseudoVFMSUB_VFPR16_M4_E16_MASK = 2805 + + PseudoVFMSUB_VFPR16_M8_E16 = 2806 + + PseudoVFMSUB_VFPR16_M8_E16_MASK = 2807 + + PseudoVFMSUB_VFPR16_MF2_E16 = 2808 + + PseudoVFMSUB_VFPR16_MF2_E16_MASK = 2809 + + PseudoVFMSUB_VFPR16_MF4_E16 = 2810 + + PseudoVFMSUB_VFPR16_MF4_E16_MASK = 2811 + + PseudoVFMSUB_VFPR32_M1_E32 = 2812 + + PseudoVFMSUB_VFPR32_M1_E32_MASK = 2813 + + PseudoVFMSUB_VFPR32_M2_E32 = 2814 + + PseudoVFMSUB_VFPR32_M2_E32_MASK = 2815 + + PseudoVFMSUB_VFPR32_M4_E32 = 2816 + + PseudoVFMSUB_VFPR32_M4_E32_MASK = 2817 + + PseudoVFMSUB_VFPR32_M8_E32 = 2818 + + PseudoVFMSUB_VFPR32_M8_E32_MASK = 2819 + + PseudoVFMSUB_VFPR32_MF2_E32 = 2820 + + PseudoVFMSUB_VFPR32_MF2_E32_MASK = 2821 + + PseudoVFMSUB_VFPR64_M1_E64 = 2822 + + PseudoVFMSUB_VFPR64_M1_E64_MASK = 2823 + + PseudoVFMSUB_VFPR64_M2_E64 = 2824 + + PseudoVFMSUB_VFPR64_M2_E64_MASK = 2825 + + PseudoVFMSUB_VFPR64_M4_E64 = 2826 + + PseudoVFMSUB_VFPR64_M4_E64_MASK = 2827 + + PseudoVFMSUB_VFPR64_M8_E64 = 2828 + + PseudoVFMSUB_VFPR64_M8_E64_MASK = 2829 + + PseudoVFMSUB_VV_M1_E16 = 2830 + + PseudoVFMSUB_VV_M1_E16_MASK = 2831 + + PseudoVFMSUB_VV_M1_E32 = 2832 + + PseudoVFMSUB_VV_M1_E32_MASK = 2833 + + PseudoVFMSUB_VV_M1_E64 = 2834 + + PseudoVFMSUB_VV_M1_E64_MASK = 2835 + + PseudoVFMSUB_VV_M2_E16 = 2836 + + PseudoVFMSUB_VV_M2_E16_MASK = 2837 + + PseudoVFMSUB_VV_M2_E32 = 2838 + + PseudoVFMSUB_VV_M2_E32_MASK = 2839 + + PseudoVFMSUB_VV_M2_E64 = 2840 + + PseudoVFMSUB_VV_M2_E64_MASK = 2841 + + PseudoVFMSUB_VV_M4_E16 = 2842 + + PseudoVFMSUB_VV_M4_E16_MASK = 2843 + + PseudoVFMSUB_VV_M4_E32 = 2844 + + PseudoVFMSUB_VV_M4_E32_MASK = 2845 + + PseudoVFMSUB_VV_M4_E64 = 2846 + + PseudoVFMSUB_VV_M4_E64_MASK = 2847 + + PseudoVFMSUB_VV_M8_E16 = 2848 + + PseudoVFMSUB_VV_M8_E16_MASK = 2849 + + PseudoVFMSUB_VV_M8_E32 = 2850 + + PseudoVFMSUB_VV_M8_E32_MASK = 2851 + + PseudoVFMSUB_VV_M8_E64 = 2852 + + PseudoVFMSUB_VV_M8_E64_MASK = 2853 + + PseudoVFMSUB_VV_MF2_E16 = 2854 + + PseudoVFMSUB_VV_MF2_E16_MASK = 2855 + + PseudoVFMSUB_VV_MF2_E32 = 2856 + + PseudoVFMSUB_VV_MF2_E32_MASK = 2857 + + PseudoVFMSUB_VV_MF4_E16 = 2858 + + PseudoVFMSUB_VV_MF4_E16_MASK = 2859 + + PseudoVFMUL_ALT_VFPR16_M1_E16 = 2860 + + PseudoVFMUL_ALT_VFPR16_M1_E16_MASK = 2861 + + PseudoVFMUL_ALT_VFPR16_M2_E16 = 2862 + + PseudoVFMUL_ALT_VFPR16_M2_E16_MASK = 2863 + + PseudoVFMUL_ALT_VFPR16_M4_E16 = 2864 + + PseudoVFMUL_ALT_VFPR16_M4_E16_MASK = 2865 + + PseudoVFMUL_ALT_VFPR16_M8_E16 = 2866 + + PseudoVFMUL_ALT_VFPR16_M8_E16_MASK = 2867 + + PseudoVFMUL_ALT_VFPR16_MF2_E16 = 2868 + + PseudoVFMUL_ALT_VFPR16_MF2_E16_MASK = 2869 + + PseudoVFMUL_ALT_VFPR16_MF4_E16 = 2870 + + PseudoVFMUL_ALT_VFPR16_MF4_E16_MASK = 2871 + + PseudoVFMUL_ALT_VV_M1_E16 = 2872 + + PseudoVFMUL_ALT_VV_M1_E16_MASK = 2873 + + PseudoVFMUL_ALT_VV_M2_E16 = 2874 + + PseudoVFMUL_ALT_VV_M2_E16_MASK = 2875 + + PseudoVFMUL_ALT_VV_M4_E16 = 2876 + + PseudoVFMUL_ALT_VV_M4_E16_MASK = 2877 + + PseudoVFMUL_ALT_VV_M8_E16 = 2878 + + PseudoVFMUL_ALT_VV_M8_E16_MASK = 2879 + + PseudoVFMUL_ALT_VV_MF2_E16 = 2880 + + PseudoVFMUL_ALT_VV_MF2_E16_MASK = 2881 + + PseudoVFMUL_ALT_VV_MF4_E16 = 2882 + + PseudoVFMUL_ALT_VV_MF4_E16_MASK = 2883 + + PseudoVFMUL_VFPR16_M1_E16 = 2884 + + PseudoVFMUL_VFPR16_M1_E16_MASK = 2885 + + PseudoVFMUL_VFPR16_M2_E16 = 2886 + + PseudoVFMUL_VFPR16_M2_E16_MASK = 2887 + + PseudoVFMUL_VFPR16_M4_E16 = 2888 + + PseudoVFMUL_VFPR16_M4_E16_MASK = 2889 + + PseudoVFMUL_VFPR16_M8_E16 = 2890 + + PseudoVFMUL_VFPR16_M8_E16_MASK = 2891 + + PseudoVFMUL_VFPR16_MF2_E16 = 2892 + + PseudoVFMUL_VFPR16_MF2_E16_MASK = 2893 + + PseudoVFMUL_VFPR16_MF4_E16 = 2894 + + PseudoVFMUL_VFPR16_MF4_E16_MASK = 2895 + + PseudoVFMUL_VFPR32_M1_E32 = 2896 + + PseudoVFMUL_VFPR32_M1_E32_MASK = 2897 + + PseudoVFMUL_VFPR32_M2_E32 = 2898 + + PseudoVFMUL_VFPR32_M2_E32_MASK = 2899 + + PseudoVFMUL_VFPR32_M4_E32 = 2900 + + PseudoVFMUL_VFPR32_M4_E32_MASK = 2901 + + PseudoVFMUL_VFPR32_M8_E32 = 2902 + + PseudoVFMUL_VFPR32_M8_E32_MASK = 2903 + + PseudoVFMUL_VFPR32_MF2_E32 = 2904 + + PseudoVFMUL_VFPR32_MF2_E32_MASK = 2905 + + PseudoVFMUL_VFPR64_M1_E64 = 2906 + + PseudoVFMUL_VFPR64_M1_E64_MASK = 2907 + + PseudoVFMUL_VFPR64_M2_E64 = 2908 + + PseudoVFMUL_VFPR64_M2_E64_MASK = 2909 + + PseudoVFMUL_VFPR64_M4_E64 = 2910 + + PseudoVFMUL_VFPR64_M4_E64_MASK = 2911 + + PseudoVFMUL_VFPR64_M8_E64 = 2912 + + PseudoVFMUL_VFPR64_M8_E64_MASK = 2913 + + PseudoVFMUL_VV_M1_E16 = 2914 + + PseudoVFMUL_VV_M1_E16_MASK = 2915 + + PseudoVFMUL_VV_M1_E32 = 2916 + + PseudoVFMUL_VV_M1_E32_MASK = 2917 + + PseudoVFMUL_VV_M1_E64 = 2918 + + PseudoVFMUL_VV_M1_E64_MASK = 2919 + + PseudoVFMUL_VV_M2_E16 = 2920 + + PseudoVFMUL_VV_M2_E16_MASK = 2921 + + PseudoVFMUL_VV_M2_E32 = 2922 + + PseudoVFMUL_VV_M2_E32_MASK = 2923 + + PseudoVFMUL_VV_M2_E64 = 2924 + + PseudoVFMUL_VV_M2_E64_MASK = 2925 + + PseudoVFMUL_VV_M4_E16 = 2926 + + PseudoVFMUL_VV_M4_E16_MASK = 2927 + + PseudoVFMUL_VV_M4_E32 = 2928 + + PseudoVFMUL_VV_M4_E32_MASK = 2929 + + PseudoVFMUL_VV_M4_E64 = 2930 + + PseudoVFMUL_VV_M4_E64_MASK = 2931 + + PseudoVFMUL_VV_M8_E16 = 2932 + + PseudoVFMUL_VV_M8_E16_MASK = 2933 + + PseudoVFMUL_VV_M8_E32 = 2934 + + PseudoVFMUL_VV_M8_E32_MASK = 2935 + + PseudoVFMUL_VV_M8_E64 = 2936 + + PseudoVFMUL_VV_M8_E64_MASK = 2937 + + PseudoVFMUL_VV_MF2_E16 = 2938 + + PseudoVFMUL_VV_MF2_E16_MASK = 2939 + + PseudoVFMUL_VV_MF2_E32 = 2940 + + PseudoVFMUL_VV_MF2_E32_MASK = 2941 + + PseudoVFMUL_VV_MF4_E16 = 2942 + + PseudoVFMUL_VV_MF4_E16_MASK = 2943 + + PseudoVFMV_FPR16_S = 2944 + + PseudoVFMV_FPR16_S_ALT = 2945 + + PseudoVFMV_FPR32_S = 2946 + + PseudoVFMV_FPR64_S = 2947 + + PseudoVFMV_S_FPR16 = 2948 + + PseudoVFMV_S_FPR16_ALT = 2949 + + PseudoVFMV_S_FPR32 = 2950 + + PseudoVFMV_S_FPR64 = 2951 + + PseudoVFMV_V_ALT_FPR16_M1 = 2952 + + PseudoVFMV_V_ALT_FPR16_M2 = 2953 + + PseudoVFMV_V_ALT_FPR16_M4 = 2954 + + PseudoVFMV_V_ALT_FPR16_M8 = 2955 + + PseudoVFMV_V_ALT_FPR16_MF2 = 2956 + + PseudoVFMV_V_ALT_FPR16_MF4 = 2957 + + PseudoVFMV_V_ALT_FPR32_M1 = 2958 + + PseudoVFMV_V_ALT_FPR32_M2 = 2959 + + PseudoVFMV_V_ALT_FPR32_M4 = 2960 + + PseudoVFMV_V_ALT_FPR32_M8 = 2961 + + PseudoVFMV_V_ALT_FPR32_MF2 = 2962 + + PseudoVFMV_V_ALT_FPR64_M1 = 2963 + + PseudoVFMV_V_ALT_FPR64_M2 = 2964 + + PseudoVFMV_V_ALT_FPR64_M4 = 2965 + + PseudoVFMV_V_ALT_FPR64_M8 = 2966 + + PseudoVFMV_V_FPR16_M1 = 2967 + + PseudoVFMV_V_FPR16_M2 = 2968 + + PseudoVFMV_V_FPR16_M4 = 2969 + + PseudoVFMV_V_FPR16_M8 = 2970 + + PseudoVFMV_V_FPR16_MF2 = 2971 + + PseudoVFMV_V_FPR16_MF4 = 2972 + + PseudoVFMV_V_FPR32_M1 = 2973 + + PseudoVFMV_V_FPR32_M2 = 2974 + + PseudoVFMV_V_FPR32_M4 = 2975 + + PseudoVFMV_V_FPR32_M8 = 2976 + + PseudoVFMV_V_FPR32_MF2 = 2977 + + PseudoVFMV_V_FPR64_M1 = 2978 + + PseudoVFMV_V_FPR64_M2 = 2979 + + PseudoVFMV_V_FPR64_M4 = 2980 + + PseudoVFMV_V_FPR64_M8 = 2981 + + PseudoVFNCVTBF16_F_F_ALT_W_M1_E8 = 2982 + + PseudoVFNCVTBF16_F_F_ALT_W_M1_E8_MASK = 2983 + + PseudoVFNCVTBF16_F_F_ALT_W_M2_E8 = 2984 + + PseudoVFNCVTBF16_F_F_ALT_W_M2_E8_MASK = 2985 + + PseudoVFNCVTBF16_F_F_ALT_W_M4_E8 = 2986 + + PseudoVFNCVTBF16_F_F_ALT_W_M4_E8_MASK = 2987 + + PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8 = 2988 + + PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8_MASK = 2989 + + PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8 = 2990 + + PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8_MASK = 2991 + + PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8 = 2992 + + PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8_MASK = 2993 + + PseudoVFNCVTBF16_F_F_W_M1_E16 = 2994 + + PseudoVFNCVTBF16_F_F_W_M1_E16_MASK = 2995 + + PseudoVFNCVTBF16_F_F_W_M1_E32 = 2996 + + PseudoVFNCVTBF16_F_F_W_M1_E32_MASK = 2997 + + PseudoVFNCVTBF16_F_F_W_M1_E8 = 2998 + + PseudoVFNCVTBF16_F_F_W_M1_E8_MASK = 2999 + + PseudoVFNCVTBF16_F_F_W_M2_E16 = 3000 + + PseudoVFNCVTBF16_F_F_W_M2_E16_MASK = 3001 + + PseudoVFNCVTBF16_F_F_W_M2_E32 = 3002 + + PseudoVFNCVTBF16_F_F_W_M2_E32_MASK = 3003 + + PseudoVFNCVTBF16_F_F_W_M2_E8 = 3004 + + PseudoVFNCVTBF16_F_F_W_M2_E8_MASK = 3005 + + PseudoVFNCVTBF16_F_F_W_M4_E16 = 3006 + + PseudoVFNCVTBF16_F_F_W_M4_E16_MASK = 3007 + + PseudoVFNCVTBF16_F_F_W_M4_E32 = 3008 + + PseudoVFNCVTBF16_F_F_W_M4_E32_MASK = 3009 + + PseudoVFNCVTBF16_F_F_W_M4_E8 = 3010 + + PseudoVFNCVTBF16_F_F_W_M4_E8_MASK = 3011 + + PseudoVFNCVTBF16_F_F_W_MF2_E16 = 3012 + + PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK = 3013 + + PseudoVFNCVTBF16_F_F_W_MF2_E32 = 3014 + + PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK = 3015 + + PseudoVFNCVTBF16_F_F_W_MF2_E8 = 3016 + + PseudoVFNCVTBF16_F_F_W_MF2_E8_MASK = 3017 + + PseudoVFNCVTBF16_F_F_W_MF4_E16 = 3018 + + PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK = 3019 + + PseudoVFNCVTBF16_F_F_W_MF4_E8 = 3020 + + PseudoVFNCVTBF16_F_F_W_MF4_E8_MASK = 3021 + + PseudoVFNCVTBF16_F_F_W_MF8_E8 = 3022 + + PseudoVFNCVTBF16_F_F_W_MF8_E8_MASK = 3023 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8 = 3024 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8_MASK = 3025 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8 = 3026 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8_MASK = 3027 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8 = 3028 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8_MASK = 3029 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8 = 3030 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8_MASK = 3031 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8 = 3032 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8_MASK = 3033 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8 = 3034 + + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8_MASK = 3035 + + PseudoVFNCVTBF16_SAT_F_F_W_M1_E8 = 3036 + + PseudoVFNCVTBF16_SAT_F_F_W_M1_E8_MASK = 3037 + + PseudoVFNCVTBF16_SAT_F_F_W_M2_E8 = 3038 + + PseudoVFNCVTBF16_SAT_F_F_W_M2_E8_MASK = 3039 + + PseudoVFNCVTBF16_SAT_F_F_W_M4_E8 = 3040 + + PseudoVFNCVTBF16_SAT_F_F_W_M4_E8_MASK = 3041 + + PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8 = 3042 + + PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8_MASK = 3043 + + PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8 = 3044 + + PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8_MASK = 3045 + + PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8 = 3046 + + PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8_MASK = 3047 + + PseudoVFNCVT_F_F_ALT_Q_M1_E8 = 3048 + + PseudoVFNCVT_F_F_ALT_Q_M1_E8_MASK = 3049 + + PseudoVFNCVT_F_F_ALT_Q_M2_E8 = 3050 + + PseudoVFNCVT_F_F_ALT_Q_M2_E8_MASK = 3051 + + PseudoVFNCVT_F_F_ALT_Q_MF2_E8 = 3052 + + PseudoVFNCVT_F_F_ALT_Q_MF2_E8_MASK = 3053 + + PseudoVFNCVT_F_F_ALT_Q_MF4_E8 = 3054 + + PseudoVFNCVT_F_F_ALT_Q_MF4_E8_MASK = 3055 + + PseudoVFNCVT_F_F_ALT_Q_MF8_E8 = 3056 + + PseudoVFNCVT_F_F_ALT_Q_MF8_E8_MASK = 3057 + + PseudoVFNCVT_F_F_ALT_W_M1_E16 = 3058 + + PseudoVFNCVT_F_F_ALT_W_M1_E16_MASK = 3059 + + PseudoVFNCVT_F_F_ALT_W_M2_E16 = 3060 + + PseudoVFNCVT_F_F_ALT_W_M2_E16_MASK = 3061 + + PseudoVFNCVT_F_F_ALT_W_M4_E16 = 3062 + + PseudoVFNCVT_F_F_ALT_W_M4_E16_MASK = 3063 + + PseudoVFNCVT_F_F_ALT_W_MF2_E16 = 3064 + + PseudoVFNCVT_F_F_ALT_W_MF2_E16_MASK = 3065 + + PseudoVFNCVT_F_F_ALT_W_MF4_E16 = 3066 + + PseudoVFNCVT_F_F_ALT_W_MF4_E16_MASK = 3067 + + PseudoVFNCVT_F_F_Q_M1_E8 = 3068 + + PseudoVFNCVT_F_F_Q_M1_E8_MASK = 3069 + + PseudoVFNCVT_F_F_Q_M2_E8 = 3070 + + PseudoVFNCVT_F_F_Q_M2_E8_MASK = 3071 + + PseudoVFNCVT_F_F_Q_MF2_E8 = 3072 + + PseudoVFNCVT_F_F_Q_MF2_E8_MASK = 3073 + + PseudoVFNCVT_F_F_Q_MF4_E8 = 3074 + + PseudoVFNCVT_F_F_Q_MF4_E8_MASK = 3075 + + PseudoVFNCVT_F_F_Q_MF8_E8 = 3076 + + PseudoVFNCVT_F_F_Q_MF8_E8_MASK = 3077 + + PseudoVFNCVT_F_F_W_M1_E16 = 3078 + + PseudoVFNCVT_F_F_W_M1_E16_MASK = 3079 + + PseudoVFNCVT_F_F_W_M1_E32 = 3080 + + PseudoVFNCVT_F_F_W_M1_E32_MASK = 3081 + + PseudoVFNCVT_F_F_W_M2_E16 = 3082 + + PseudoVFNCVT_F_F_W_M2_E16_MASK = 3083 + + PseudoVFNCVT_F_F_W_M2_E32 = 3084 + + PseudoVFNCVT_F_F_W_M2_E32_MASK = 3085 + + PseudoVFNCVT_F_F_W_M4_E16 = 3086 + + PseudoVFNCVT_F_F_W_M4_E16_MASK = 3087 + + PseudoVFNCVT_F_F_W_M4_E32 = 3088 + + PseudoVFNCVT_F_F_W_M4_E32_MASK = 3089 + + PseudoVFNCVT_F_F_W_MF2_E16 = 3090 + + PseudoVFNCVT_F_F_W_MF2_E16_MASK = 3091 + + PseudoVFNCVT_F_F_W_MF2_E32 = 3092 + + PseudoVFNCVT_F_F_W_MF2_E32_MASK = 3093 + + PseudoVFNCVT_F_F_W_MF4_E16 = 3094 + + PseudoVFNCVT_F_F_W_MF4_E16_MASK = 3095 + + PseudoVFNCVT_F_XU_W_M1_E16 = 3096 + + PseudoVFNCVT_F_XU_W_M1_E16_MASK = 3097 + + PseudoVFNCVT_F_XU_W_M1_E32 = 3098 + + PseudoVFNCVT_F_XU_W_M1_E32_MASK = 3099 + + PseudoVFNCVT_F_XU_W_M2_E16 = 3100 + + PseudoVFNCVT_F_XU_W_M2_E16_MASK = 3101 + + PseudoVFNCVT_F_XU_W_M2_E32 = 3102 + + PseudoVFNCVT_F_XU_W_M2_E32_MASK = 3103 + + PseudoVFNCVT_F_XU_W_M4_E16 = 3104 + + PseudoVFNCVT_F_XU_W_M4_E16_MASK = 3105 + + PseudoVFNCVT_F_XU_W_M4_E32 = 3106 + + PseudoVFNCVT_F_XU_W_M4_E32_MASK = 3107 + + PseudoVFNCVT_F_XU_W_MF2_E16 = 3108 + + PseudoVFNCVT_F_XU_W_MF2_E16_MASK = 3109 + + PseudoVFNCVT_F_XU_W_MF2_E32 = 3110 + + PseudoVFNCVT_F_XU_W_MF2_E32_MASK = 3111 + + PseudoVFNCVT_F_XU_W_MF4_E16 = 3112 + + PseudoVFNCVT_F_XU_W_MF4_E16_MASK = 3113 + + PseudoVFNCVT_F_X_W_M1_E16 = 3114 + + PseudoVFNCVT_F_X_W_M1_E16_MASK = 3115 + + PseudoVFNCVT_F_X_W_M1_E32 = 3116 + + PseudoVFNCVT_F_X_W_M1_E32_MASK = 3117 + + PseudoVFNCVT_F_X_W_M2_E16 = 3118 + + PseudoVFNCVT_F_X_W_M2_E16_MASK = 3119 + + PseudoVFNCVT_F_X_W_M2_E32 = 3120 + + PseudoVFNCVT_F_X_W_M2_E32_MASK = 3121 + + PseudoVFNCVT_F_X_W_M4_E16 = 3122 + + PseudoVFNCVT_F_X_W_M4_E16_MASK = 3123 + + PseudoVFNCVT_F_X_W_M4_E32 = 3124 + + PseudoVFNCVT_F_X_W_M4_E32_MASK = 3125 + + PseudoVFNCVT_F_X_W_MF2_E16 = 3126 + + PseudoVFNCVT_F_X_W_MF2_E16_MASK = 3127 + + PseudoVFNCVT_F_X_W_MF2_E32 = 3128 + + PseudoVFNCVT_F_X_W_MF2_E32_MASK = 3129 + + PseudoVFNCVT_F_X_W_MF4_E16 = 3130 + + PseudoVFNCVT_F_X_W_MF4_E16_MASK = 3131 + + PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16 = 3132 + + PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16_MASK = 3133 + + PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16 = 3134 + + PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16_MASK = 3135 + + PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16 = 3136 + + PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16_MASK = 3137 + + PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16 = 3138 + + PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16_MASK = 3139 + + PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16 = 3140 + + PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16_MASK = 3141 + + PseudoVFNCVT_ROD_F_F_W_M1_E16 = 3142 + + PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK = 3143 + + PseudoVFNCVT_ROD_F_F_W_M1_E32 = 3144 + + PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK = 3145 + + PseudoVFNCVT_ROD_F_F_W_M2_E16 = 3146 + + PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK = 3147 + + PseudoVFNCVT_ROD_F_F_W_M2_E32 = 3148 + + PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK = 3149 + + PseudoVFNCVT_ROD_F_F_W_M4_E16 = 3150 + + PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK = 3151 + + PseudoVFNCVT_ROD_F_F_W_M4_E32 = 3152 + + PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK = 3153 + + PseudoVFNCVT_ROD_F_F_W_MF2_E16 = 3154 + + PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK = 3155 + + PseudoVFNCVT_ROD_F_F_W_MF2_E32 = 3156 + + PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK = 3157 + + PseudoVFNCVT_ROD_F_F_W_MF4_E16 = 3158 + + PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK = 3159 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M1 = 3160 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M1_MASK = 3161 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M2 = 3162 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M2_MASK = 3163 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M4 = 3164 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_M4_MASK = 3165 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2 = 3166 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2_MASK = 3167 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4 = 3168 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4_MASK = 3169 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8 = 3170 + + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8_MASK = 3171 + + PseudoVFNCVT_RTZ_XU_F_W_M1 = 3172 + + PseudoVFNCVT_RTZ_XU_F_W_M1_MASK = 3173 + + PseudoVFNCVT_RTZ_XU_F_W_M2 = 3174 + + PseudoVFNCVT_RTZ_XU_F_W_M2_MASK = 3175 + + PseudoVFNCVT_RTZ_XU_F_W_M4 = 3176 + + PseudoVFNCVT_RTZ_XU_F_W_M4_MASK = 3177 + + PseudoVFNCVT_RTZ_XU_F_W_MF2 = 3178 + + PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK = 3179 + + PseudoVFNCVT_RTZ_XU_F_W_MF4 = 3180 + + PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK = 3181 + + PseudoVFNCVT_RTZ_XU_F_W_MF8 = 3182 + + PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK = 3183 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M1 = 3184 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M1_MASK = 3185 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M2 = 3186 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M2_MASK = 3187 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M4 = 3188 + + PseudoVFNCVT_RTZ_X_F_ALT_W_M4_MASK = 3189 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF2 = 3190 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF2_MASK = 3191 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF4 = 3192 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF4_MASK = 3193 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF8 = 3194 + + PseudoVFNCVT_RTZ_X_F_ALT_W_MF8_MASK = 3195 + + PseudoVFNCVT_RTZ_X_F_W_M1 = 3196 + + PseudoVFNCVT_RTZ_X_F_W_M1_MASK = 3197 + + PseudoVFNCVT_RTZ_X_F_W_M2 = 3198 + + PseudoVFNCVT_RTZ_X_F_W_M2_MASK = 3199 + + PseudoVFNCVT_RTZ_X_F_W_M4 = 3200 + + PseudoVFNCVT_RTZ_X_F_W_M4_MASK = 3201 + + PseudoVFNCVT_RTZ_X_F_W_MF2 = 3202 + + PseudoVFNCVT_RTZ_X_F_W_MF2_MASK = 3203 + + PseudoVFNCVT_RTZ_X_F_W_MF4 = 3204 + + PseudoVFNCVT_RTZ_X_F_W_MF4_MASK = 3205 + + PseudoVFNCVT_RTZ_X_F_W_MF8 = 3206 + + PseudoVFNCVT_RTZ_X_F_W_MF8_MASK = 3207 + + PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8 = 3208 + + PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8_MASK = 3209 + + PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8 = 3210 + + PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8_MASK = 3211 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8 = 3212 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8_MASK = 3213 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8 = 3214 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8_MASK = 3215 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8 = 3216 + + PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8_MASK = 3217 + + PseudoVFNCVT_SAT_F_F_Q_M1_E8 = 3218 + + PseudoVFNCVT_SAT_F_F_Q_M1_E8_MASK = 3219 + + PseudoVFNCVT_SAT_F_F_Q_M2_E8 = 3220 + + PseudoVFNCVT_SAT_F_F_Q_M2_E8_MASK = 3221 + + PseudoVFNCVT_SAT_F_F_Q_MF2_E8 = 3222 + + PseudoVFNCVT_SAT_F_F_Q_MF2_E8_MASK = 3223 + + PseudoVFNCVT_SAT_F_F_Q_MF4_E8 = 3224 + + PseudoVFNCVT_SAT_F_F_Q_MF4_E8_MASK = 3225 + + PseudoVFNCVT_SAT_F_F_Q_MF8_E8 = 3226 + + PseudoVFNCVT_SAT_F_F_Q_MF8_E8_MASK = 3227 + + PseudoVFNCVT_XU_F_ALT_W_M1 = 3228 + + PseudoVFNCVT_XU_F_ALT_W_M1_MASK = 3229 + + PseudoVFNCVT_XU_F_ALT_W_M2 = 3230 + + PseudoVFNCVT_XU_F_ALT_W_M2_MASK = 3231 + + PseudoVFNCVT_XU_F_ALT_W_M4 = 3232 + + PseudoVFNCVT_XU_F_ALT_W_M4_MASK = 3233 + + PseudoVFNCVT_XU_F_ALT_W_MF2 = 3234 + + PseudoVFNCVT_XU_F_ALT_W_MF2_MASK = 3235 + + PseudoVFNCVT_XU_F_ALT_W_MF4 = 3236 + + PseudoVFNCVT_XU_F_ALT_W_MF4_MASK = 3237 + + PseudoVFNCVT_XU_F_ALT_W_MF8 = 3238 + + PseudoVFNCVT_XU_F_ALT_W_MF8_MASK = 3239 + + PseudoVFNCVT_XU_F_W_M1 = 3240 + + PseudoVFNCVT_XU_F_W_M1_MASK = 3241 + + PseudoVFNCVT_XU_F_W_M2 = 3242 + + PseudoVFNCVT_XU_F_W_M2_MASK = 3243 + + PseudoVFNCVT_XU_F_W_M4 = 3244 + + PseudoVFNCVT_XU_F_W_M4_MASK = 3245 + + PseudoVFNCVT_XU_F_W_MF2 = 3246 + + PseudoVFNCVT_XU_F_W_MF2_MASK = 3247 + + PseudoVFNCVT_XU_F_W_MF4 = 3248 + + PseudoVFNCVT_XU_F_W_MF4_MASK = 3249 + + PseudoVFNCVT_XU_F_W_MF8 = 3250 + + PseudoVFNCVT_XU_F_W_MF8_MASK = 3251 + + PseudoVFNCVT_X_F_ALT_W_M1 = 3252 + + PseudoVFNCVT_X_F_ALT_W_M1_MASK = 3253 + + PseudoVFNCVT_X_F_ALT_W_M2 = 3254 + + PseudoVFNCVT_X_F_ALT_W_M2_MASK = 3255 + + PseudoVFNCVT_X_F_ALT_W_M4 = 3256 + + PseudoVFNCVT_X_F_ALT_W_M4_MASK = 3257 + + PseudoVFNCVT_X_F_ALT_W_MF2 = 3258 + + PseudoVFNCVT_X_F_ALT_W_MF2_MASK = 3259 + + PseudoVFNCVT_X_F_ALT_W_MF4 = 3260 + + PseudoVFNCVT_X_F_ALT_W_MF4_MASK = 3261 + + PseudoVFNCVT_X_F_ALT_W_MF8 = 3262 + + PseudoVFNCVT_X_F_ALT_W_MF8_MASK = 3263 + + PseudoVFNCVT_X_F_W_M1 = 3264 + + PseudoVFNCVT_X_F_W_M1_MASK = 3265 + + PseudoVFNCVT_X_F_W_M2 = 3266 + + PseudoVFNCVT_X_F_W_M2_MASK = 3267 + + PseudoVFNCVT_X_F_W_M4 = 3268 + + PseudoVFNCVT_X_F_W_M4_MASK = 3269 + + PseudoVFNCVT_X_F_W_MF2 = 3270 + + PseudoVFNCVT_X_F_W_MF2_MASK = 3271 + + PseudoVFNCVT_X_F_W_MF4 = 3272 + + PseudoVFNCVT_X_F_W_MF4_MASK = 3273 + + PseudoVFNCVT_X_F_W_MF8 = 3274 + + PseudoVFNCVT_X_F_W_MF8_MASK = 3275 + + PseudoVFNMACC_ALT_VFPR16_M1_E16 = 3276 + + PseudoVFNMACC_ALT_VFPR16_M1_E16_MASK = 3277 + + PseudoVFNMACC_ALT_VFPR16_M2_E16 = 3278 + + PseudoVFNMACC_ALT_VFPR16_M2_E16_MASK = 3279 + + PseudoVFNMACC_ALT_VFPR16_M4_E16 = 3280 + + PseudoVFNMACC_ALT_VFPR16_M4_E16_MASK = 3281 + + PseudoVFNMACC_ALT_VFPR16_M8_E16 = 3282 + + PseudoVFNMACC_ALT_VFPR16_M8_E16_MASK = 3283 + + PseudoVFNMACC_ALT_VFPR16_MF2_E16 = 3284 + + PseudoVFNMACC_ALT_VFPR16_MF2_E16_MASK = 3285 + + PseudoVFNMACC_ALT_VFPR16_MF4_E16 = 3286 + + PseudoVFNMACC_ALT_VFPR16_MF4_E16_MASK = 3287 + + PseudoVFNMACC_ALT_VV_M1_E16 = 3288 + + PseudoVFNMACC_ALT_VV_M1_E16_MASK = 3289 + + PseudoVFNMACC_ALT_VV_M2_E16 = 3290 + + PseudoVFNMACC_ALT_VV_M2_E16_MASK = 3291 + + PseudoVFNMACC_ALT_VV_M4_E16 = 3292 + + PseudoVFNMACC_ALT_VV_M4_E16_MASK = 3293 + + PseudoVFNMACC_ALT_VV_M8_E16 = 3294 + + PseudoVFNMACC_ALT_VV_M8_E16_MASK = 3295 + + PseudoVFNMACC_ALT_VV_MF2_E16 = 3296 + + PseudoVFNMACC_ALT_VV_MF2_E16_MASK = 3297 + + PseudoVFNMACC_ALT_VV_MF4_E16 = 3298 + + PseudoVFNMACC_ALT_VV_MF4_E16_MASK = 3299 + + PseudoVFNMACC_VFPR16_M1_E16 = 3300 + + PseudoVFNMACC_VFPR16_M1_E16_MASK = 3301 + + PseudoVFNMACC_VFPR16_M2_E16 = 3302 + + PseudoVFNMACC_VFPR16_M2_E16_MASK = 3303 + + PseudoVFNMACC_VFPR16_M4_E16 = 3304 + + PseudoVFNMACC_VFPR16_M4_E16_MASK = 3305 + + PseudoVFNMACC_VFPR16_M8_E16 = 3306 + + PseudoVFNMACC_VFPR16_M8_E16_MASK = 3307 + + PseudoVFNMACC_VFPR16_MF2_E16 = 3308 + + PseudoVFNMACC_VFPR16_MF2_E16_MASK = 3309 + + PseudoVFNMACC_VFPR16_MF4_E16 = 3310 + + PseudoVFNMACC_VFPR16_MF4_E16_MASK = 3311 + + PseudoVFNMACC_VFPR32_M1_E32 = 3312 + + PseudoVFNMACC_VFPR32_M1_E32_MASK = 3313 + + PseudoVFNMACC_VFPR32_M2_E32 = 3314 + + PseudoVFNMACC_VFPR32_M2_E32_MASK = 3315 + + PseudoVFNMACC_VFPR32_M4_E32 = 3316 + + PseudoVFNMACC_VFPR32_M4_E32_MASK = 3317 + + PseudoVFNMACC_VFPR32_M8_E32 = 3318 + + PseudoVFNMACC_VFPR32_M8_E32_MASK = 3319 + + PseudoVFNMACC_VFPR32_MF2_E32 = 3320 + + PseudoVFNMACC_VFPR32_MF2_E32_MASK = 3321 + + PseudoVFNMACC_VFPR64_M1_E64 = 3322 + + PseudoVFNMACC_VFPR64_M1_E64_MASK = 3323 + + PseudoVFNMACC_VFPR64_M2_E64 = 3324 + + PseudoVFNMACC_VFPR64_M2_E64_MASK = 3325 + + PseudoVFNMACC_VFPR64_M4_E64 = 3326 + + PseudoVFNMACC_VFPR64_M4_E64_MASK = 3327 + + PseudoVFNMACC_VFPR64_M8_E64 = 3328 + + PseudoVFNMACC_VFPR64_M8_E64_MASK = 3329 + + PseudoVFNMACC_VV_M1_E16 = 3330 + + PseudoVFNMACC_VV_M1_E16_MASK = 3331 + + PseudoVFNMACC_VV_M1_E32 = 3332 + + PseudoVFNMACC_VV_M1_E32_MASK = 3333 + + PseudoVFNMACC_VV_M1_E64 = 3334 + + PseudoVFNMACC_VV_M1_E64_MASK = 3335 + + PseudoVFNMACC_VV_M2_E16 = 3336 + + PseudoVFNMACC_VV_M2_E16_MASK = 3337 + + PseudoVFNMACC_VV_M2_E32 = 3338 + + PseudoVFNMACC_VV_M2_E32_MASK = 3339 + + PseudoVFNMACC_VV_M2_E64 = 3340 + + PseudoVFNMACC_VV_M2_E64_MASK = 3341 + + PseudoVFNMACC_VV_M4_E16 = 3342 + + PseudoVFNMACC_VV_M4_E16_MASK = 3343 + + PseudoVFNMACC_VV_M4_E32 = 3344 + + PseudoVFNMACC_VV_M4_E32_MASK = 3345 + + PseudoVFNMACC_VV_M4_E64 = 3346 + + PseudoVFNMACC_VV_M4_E64_MASK = 3347 + + PseudoVFNMACC_VV_M8_E16 = 3348 + + PseudoVFNMACC_VV_M8_E16_MASK = 3349 + + PseudoVFNMACC_VV_M8_E32 = 3350 + + PseudoVFNMACC_VV_M8_E32_MASK = 3351 + + PseudoVFNMACC_VV_M8_E64 = 3352 + + PseudoVFNMACC_VV_M8_E64_MASK = 3353 + + PseudoVFNMACC_VV_MF2_E16 = 3354 + + PseudoVFNMACC_VV_MF2_E16_MASK = 3355 + + PseudoVFNMACC_VV_MF2_E32 = 3356 + + PseudoVFNMACC_VV_MF2_E32_MASK = 3357 + + PseudoVFNMACC_VV_MF4_E16 = 3358 + + PseudoVFNMACC_VV_MF4_E16_MASK = 3359 + + PseudoVFNMADD_ALT_VFPR16_M1_E16 = 3360 + + PseudoVFNMADD_ALT_VFPR16_M1_E16_MASK = 3361 + + PseudoVFNMADD_ALT_VFPR16_M2_E16 = 3362 + + PseudoVFNMADD_ALT_VFPR16_M2_E16_MASK = 3363 + + PseudoVFNMADD_ALT_VFPR16_M4_E16 = 3364 + + PseudoVFNMADD_ALT_VFPR16_M4_E16_MASK = 3365 + + PseudoVFNMADD_ALT_VFPR16_M8_E16 = 3366 + + PseudoVFNMADD_ALT_VFPR16_M8_E16_MASK = 3367 + + PseudoVFNMADD_ALT_VFPR16_MF2_E16 = 3368 + + PseudoVFNMADD_ALT_VFPR16_MF2_E16_MASK = 3369 + + PseudoVFNMADD_ALT_VFPR16_MF4_E16 = 3370 + + PseudoVFNMADD_ALT_VFPR16_MF4_E16_MASK = 3371 + + PseudoVFNMADD_ALT_VV_M1_E16 = 3372 + + PseudoVFNMADD_ALT_VV_M1_E16_MASK = 3373 + + PseudoVFNMADD_ALT_VV_M2_E16 = 3374 + + PseudoVFNMADD_ALT_VV_M2_E16_MASK = 3375 + + PseudoVFNMADD_ALT_VV_M4_E16 = 3376 + + PseudoVFNMADD_ALT_VV_M4_E16_MASK = 3377 + + PseudoVFNMADD_ALT_VV_M8_E16 = 3378 + + PseudoVFNMADD_ALT_VV_M8_E16_MASK = 3379 + + PseudoVFNMADD_ALT_VV_MF2_E16 = 3380 + + PseudoVFNMADD_ALT_VV_MF2_E16_MASK = 3381 + + PseudoVFNMADD_ALT_VV_MF4_E16 = 3382 + + PseudoVFNMADD_ALT_VV_MF4_E16_MASK = 3383 + + PseudoVFNMADD_VFPR16_M1_E16 = 3384 + + PseudoVFNMADD_VFPR16_M1_E16_MASK = 3385 + + PseudoVFNMADD_VFPR16_M2_E16 = 3386 + + PseudoVFNMADD_VFPR16_M2_E16_MASK = 3387 + + PseudoVFNMADD_VFPR16_M4_E16 = 3388 + + PseudoVFNMADD_VFPR16_M4_E16_MASK = 3389 + + PseudoVFNMADD_VFPR16_M8_E16 = 3390 + + PseudoVFNMADD_VFPR16_M8_E16_MASK = 3391 + + PseudoVFNMADD_VFPR16_MF2_E16 = 3392 + + PseudoVFNMADD_VFPR16_MF2_E16_MASK = 3393 + + PseudoVFNMADD_VFPR16_MF4_E16 = 3394 + + PseudoVFNMADD_VFPR16_MF4_E16_MASK = 3395 + + PseudoVFNMADD_VFPR32_M1_E32 = 3396 + + PseudoVFNMADD_VFPR32_M1_E32_MASK = 3397 + + PseudoVFNMADD_VFPR32_M2_E32 = 3398 + + PseudoVFNMADD_VFPR32_M2_E32_MASK = 3399 + + PseudoVFNMADD_VFPR32_M4_E32 = 3400 + + PseudoVFNMADD_VFPR32_M4_E32_MASK = 3401 + + PseudoVFNMADD_VFPR32_M8_E32 = 3402 + + PseudoVFNMADD_VFPR32_M8_E32_MASK = 3403 + + PseudoVFNMADD_VFPR32_MF2_E32 = 3404 + + PseudoVFNMADD_VFPR32_MF2_E32_MASK = 3405 + + PseudoVFNMADD_VFPR64_M1_E64 = 3406 + + PseudoVFNMADD_VFPR64_M1_E64_MASK = 3407 + + PseudoVFNMADD_VFPR64_M2_E64 = 3408 + + PseudoVFNMADD_VFPR64_M2_E64_MASK = 3409 + + PseudoVFNMADD_VFPR64_M4_E64 = 3410 + + PseudoVFNMADD_VFPR64_M4_E64_MASK = 3411 + + PseudoVFNMADD_VFPR64_M8_E64 = 3412 + + PseudoVFNMADD_VFPR64_M8_E64_MASK = 3413 + + PseudoVFNMADD_VV_M1_E16 = 3414 + + PseudoVFNMADD_VV_M1_E16_MASK = 3415 + + PseudoVFNMADD_VV_M1_E32 = 3416 + + PseudoVFNMADD_VV_M1_E32_MASK = 3417 + + PseudoVFNMADD_VV_M1_E64 = 3418 + + PseudoVFNMADD_VV_M1_E64_MASK = 3419 + + PseudoVFNMADD_VV_M2_E16 = 3420 + + PseudoVFNMADD_VV_M2_E16_MASK = 3421 + + PseudoVFNMADD_VV_M2_E32 = 3422 + + PseudoVFNMADD_VV_M2_E32_MASK = 3423 + + PseudoVFNMADD_VV_M2_E64 = 3424 + + PseudoVFNMADD_VV_M2_E64_MASK = 3425 + + PseudoVFNMADD_VV_M4_E16 = 3426 + + PseudoVFNMADD_VV_M4_E16_MASK = 3427 + + PseudoVFNMADD_VV_M4_E32 = 3428 + + PseudoVFNMADD_VV_M4_E32_MASK = 3429 + + PseudoVFNMADD_VV_M4_E64 = 3430 + + PseudoVFNMADD_VV_M4_E64_MASK = 3431 + + PseudoVFNMADD_VV_M8_E16 = 3432 + + PseudoVFNMADD_VV_M8_E16_MASK = 3433 + + PseudoVFNMADD_VV_M8_E32 = 3434 + + PseudoVFNMADD_VV_M8_E32_MASK = 3435 + + PseudoVFNMADD_VV_M8_E64 = 3436 + + PseudoVFNMADD_VV_M8_E64_MASK = 3437 + + PseudoVFNMADD_VV_MF2_E16 = 3438 + + PseudoVFNMADD_VV_MF2_E16_MASK = 3439 + + PseudoVFNMADD_VV_MF2_E32 = 3440 + + PseudoVFNMADD_VV_MF2_E32_MASK = 3441 + + PseudoVFNMADD_VV_MF4_E16 = 3442 + + PseudoVFNMADD_VV_MF4_E16_MASK = 3443 + + PseudoVFNMSAC_ALT_VFPR16_M1_E16 = 3444 + + PseudoVFNMSAC_ALT_VFPR16_M1_E16_MASK = 3445 + + PseudoVFNMSAC_ALT_VFPR16_M2_E16 = 3446 + + PseudoVFNMSAC_ALT_VFPR16_M2_E16_MASK = 3447 + + PseudoVFNMSAC_ALT_VFPR16_M4_E16 = 3448 + + PseudoVFNMSAC_ALT_VFPR16_M4_E16_MASK = 3449 + + PseudoVFNMSAC_ALT_VFPR16_M8_E16 = 3450 + + PseudoVFNMSAC_ALT_VFPR16_M8_E16_MASK = 3451 + + PseudoVFNMSAC_ALT_VFPR16_MF2_E16 = 3452 + + PseudoVFNMSAC_ALT_VFPR16_MF2_E16_MASK = 3453 + + PseudoVFNMSAC_ALT_VFPR16_MF4_E16 = 3454 + + PseudoVFNMSAC_ALT_VFPR16_MF4_E16_MASK = 3455 + + PseudoVFNMSAC_ALT_VV_M1_E16 = 3456 + + PseudoVFNMSAC_ALT_VV_M1_E16_MASK = 3457 + + PseudoVFNMSAC_ALT_VV_M2_E16 = 3458 + + PseudoVFNMSAC_ALT_VV_M2_E16_MASK = 3459 + + PseudoVFNMSAC_ALT_VV_M4_E16 = 3460 + + PseudoVFNMSAC_ALT_VV_M4_E16_MASK = 3461 + + PseudoVFNMSAC_ALT_VV_M8_E16 = 3462 + + PseudoVFNMSAC_ALT_VV_M8_E16_MASK = 3463 + + PseudoVFNMSAC_ALT_VV_MF2_E16 = 3464 + + PseudoVFNMSAC_ALT_VV_MF2_E16_MASK = 3465 + + PseudoVFNMSAC_ALT_VV_MF4_E16 = 3466 + + PseudoVFNMSAC_ALT_VV_MF4_E16_MASK = 3467 + + PseudoVFNMSAC_VFPR16_M1_E16 = 3468 + + PseudoVFNMSAC_VFPR16_M1_E16_MASK = 3469 + + PseudoVFNMSAC_VFPR16_M2_E16 = 3470 + + PseudoVFNMSAC_VFPR16_M2_E16_MASK = 3471 + + PseudoVFNMSAC_VFPR16_M4_E16 = 3472 + + PseudoVFNMSAC_VFPR16_M4_E16_MASK = 3473 + + PseudoVFNMSAC_VFPR16_M8_E16 = 3474 + + PseudoVFNMSAC_VFPR16_M8_E16_MASK = 3475 + + PseudoVFNMSAC_VFPR16_MF2_E16 = 3476 + + PseudoVFNMSAC_VFPR16_MF2_E16_MASK = 3477 + + PseudoVFNMSAC_VFPR16_MF4_E16 = 3478 + + PseudoVFNMSAC_VFPR16_MF4_E16_MASK = 3479 + + PseudoVFNMSAC_VFPR32_M1_E32 = 3480 + + PseudoVFNMSAC_VFPR32_M1_E32_MASK = 3481 + + PseudoVFNMSAC_VFPR32_M2_E32 = 3482 + + PseudoVFNMSAC_VFPR32_M2_E32_MASK = 3483 + + PseudoVFNMSAC_VFPR32_M4_E32 = 3484 + + PseudoVFNMSAC_VFPR32_M4_E32_MASK = 3485 + + PseudoVFNMSAC_VFPR32_M8_E32 = 3486 + + PseudoVFNMSAC_VFPR32_M8_E32_MASK = 3487 + + PseudoVFNMSAC_VFPR32_MF2_E32 = 3488 + + PseudoVFNMSAC_VFPR32_MF2_E32_MASK = 3489 + + PseudoVFNMSAC_VFPR64_M1_E64 = 3490 + + PseudoVFNMSAC_VFPR64_M1_E64_MASK = 3491 + + PseudoVFNMSAC_VFPR64_M2_E64 = 3492 + + PseudoVFNMSAC_VFPR64_M2_E64_MASK = 3493 + + PseudoVFNMSAC_VFPR64_M4_E64 = 3494 + + PseudoVFNMSAC_VFPR64_M4_E64_MASK = 3495 + + PseudoVFNMSAC_VFPR64_M8_E64 = 3496 + + PseudoVFNMSAC_VFPR64_M8_E64_MASK = 3497 + + PseudoVFNMSAC_VV_M1_E16 = 3498 + + PseudoVFNMSAC_VV_M1_E16_MASK = 3499 + + PseudoVFNMSAC_VV_M1_E32 = 3500 + + PseudoVFNMSAC_VV_M1_E32_MASK = 3501 + + PseudoVFNMSAC_VV_M1_E64 = 3502 + + PseudoVFNMSAC_VV_M1_E64_MASK = 3503 + + PseudoVFNMSAC_VV_M2_E16 = 3504 + + PseudoVFNMSAC_VV_M2_E16_MASK = 3505 + + PseudoVFNMSAC_VV_M2_E32 = 3506 + + PseudoVFNMSAC_VV_M2_E32_MASK = 3507 + + PseudoVFNMSAC_VV_M2_E64 = 3508 + + PseudoVFNMSAC_VV_M2_E64_MASK = 3509 + + PseudoVFNMSAC_VV_M4_E16 = 3510 + + PseudoVFNMSAC_VV_M4_E16_MASK = 3511 + + PseudoVFNMSAC_VV_M4_E32 = 3512 + + PseudoVFNMSAC_VV_M4_E32_MASK = 3513 + + PseudoVFNMSAC_VV_M4_E64 = 3514 + + PseudoVFNMSAC_VV_M4_E64_MASK = 3515 + + PseudoVFNMSAC_VV_M8_E16 = 3516 + + PseudoVFNMSAC_VV_M8_E16_MASK = 3517 + + PseudoVFNMSAC_VV_M8_E32 = 3518 + + PseudoVFNMSAC_VV_M8_E32_MASK = 3519 + + PseudoVFNMSAC_VV_M8_E64 = 3520 + + PseudoVFNMSAC_VV_M8_E64_MASK = 3521 + + PseudoVFNMSAC_VV_MF2_E16 = 3522 + + PseudoVFNMSAC_VV_MF2_E16_MASK = 3523 + + PseudoVFNMSAC_VV_MF2_E32 = 3524 + + PseudoVFNMSAC_VV_MF2_E32_MASK = 3525 + + PseudoVFNMSAC_VV_MF4_E16 = 3526 + + PseudoVFNMSAC_VV_MF4_E16_MASK = 3527 + + PseudoVFNMSUB_ALT_VFPR16_M1_E16 = 3528 + + PseudoVFNMSUB_ALT_VFPR16_M1_E16_MASK = 3529 + + PseudoVFNMSUB_ALT_VFPR16_M2_E16 = 3530 + + PseudoVFNMSUB_ALT_VFPR16_M2_E16_MASK = 3531 + + PseudoVFNMSUB_ALT_VFPR16_M4_E16 = 3532 + + PseudoVFNMSUB_ALT_VFPR16_M4_E16_MASK = 3533 + + PseudoVFNMSUB_ALT_VFPR16_M8_E16 = 3534 + + PseudoVFNMSUB_ALT_VFPR16_M8_E16_MASK = 3535 + + PseudoVFNMSUB_ALT_VFPR16_MF2_E16 = 3536 + + PseudoVFNMSUB_ALT_VFPR16_MF2_E16_MASK = 3537 + + PseudoVFNMSUB_ALT_VFPR16_MF4_E16 = 3538 + + PseudoVFNMSUB_ALT_VFPR16_MF4_E16_MASK = 3539 + + PseudoVFNMSUB_ALT_VV_M1_E16 = 3540 + + PseudoVFNMSUB_ALT_VV_M1_E16_MASK = 3541 + + PseudoVFNMSUB_ALT_VV_M2_E16 = 3542 + + PseudoVFNMSUB_ALT_VV_M2_E16_MASK = 3543 + + PseudoVFNMSUB_ALT_VV_M4_E16 = 3544 + + PseudoVFNMSUB_ALT_VV_M4_E16_MASK = 3545 + + PseudoVFNMSUB_ALT_VV_M8_E16 = 3546 + + PseudoVFNMSUB_ALT_VV_M8_E16_MASK = 3547 + + PseudoVFNMSUB_ALT_VV_MF2_E16 = 3548 + + PseudoVFNMSUB_ALT_VV_MF2_E16_MASK = 3549 + + PseudoVFNMSUB_ALT_VV_MF4_E16 = 3550 + + PseudoVFNMSUB_ALT_VV_MF4_E16_MASK = 3551 + + PseudoVFNMSUB_VFPR16_M1_E16 = 3552 + + PseudoVFNMSUB_VFPR16_M1_E16_MASK = 3553 + + PseudoVFNMSUB_VFPR16_M2_E16 = 3554 + + PseudoVFNMSUB_VFPR16_M2_E16_MASK = 3555 + + PseudoVFNMSUB_VFPR16_M4_E16 = 3556 + + PseudoVFNMSUB_VFPR16_M4_E16_MASK = 3557 + + PseudoVFNMSUB_VFPR16_M8_E16 = 3558 + + PseudoVFNMSUB_VFPR16_M8_E16_MASK = 3559 + + PseudoVFNMSUB_VFPR16_MF2_E16 = 3560 + + PseudoVFNMSUB_VFPR16_MF2_E16_MASK = 3561 + + PseudoVFNMSUB_VFPR16_MF4_E16 = 3562 + + PseudoVFNMSUB_VFPR16_MF4_E16_MASK = 3563 + + PseudoVFNMSUB_VFPR32_M1_E32 = 3564 + + PseudoVFNMSUB_VFPR32_M1_E32_MASK = 3565 + + PseudoVFNMSUB_VFPR32_M2_E32 = 3566 + + PseudoVFNMSUB_VFPR32_M2_E32_MASK = 3567 + + PseudoVFNMSUB_VFPR32_M4_E32 = 3568 + + PseudoVFNMSUB_VFPR32_M4_E32_MASK = 3569 + + PseudoVFNMSUB_VFPR32_M8_E32 = 3570 + + PseudoVFNMSUB_VFPR32_M8_E32_MASK = 3571 + + PseudoVFNMSUB_VFPR32_MF2_E32 = 3572 + + PseudoVFNMSUB_VFPR32_MF2_E32_MASK = 3573 + + PseudoVFNMSUB_VFPR64_M1_E64 = 3574 + + PseudoVFNMSUB_VFPR64_M1_E64_MASK = 3575 + + PseudoVFNMSUB_VFPR64_M2_E64 = 3576 + + PseudoVFNMSUB_VFPR64_M2_E64_MASK = 3577 + + PseudoVFNMSUB_VFPR64_M4_E64 = 3578 + + PseudoVFNMSUB_VFPR64_M4_E64_MASK = 3579 + + PseudoVFNMSUB_VFPR64_M8_E64 = 3580 + + PseudoVFNMSUB_VFPR64_M8_E64_MASK = 3581 + + PseudoVFNMSUB_VV_M1_E16 = 3582 + + PseudoVFNMSUB_VV_M1_E16_MASK = 3583 + + PseudoVFNMSUB_VV_M1_E32 = 3584 + + PseudoVFNMSUB_VV_M1_E32_MASK = 3585 + + PseudoVFNMSUB_VV_M1_E64 = 3586 + + PseudoVFNMSUB_VV_M1_E64_MASK = 3587 + + PseudoVFNMSUB_VV_M2_E16 = 3588 + + PseudoVFNMSUB_VV_M2_E16_MASK = 3589 + + PseudoVFNMSUB_VV_M2_E32 = 3590 + + PseudoVFNMSUB_VV_M2_E32_MASK = 3591 + + PseudoVFNMSUB_VV_M2_E64 = 3592 + + PseudoVFNMSUB_VV_M2_E64_MASK = 3593 + + PseudoVFNMSUB_VV_M4_E16 = 3594 + + PseudoVFNMSUB_VV_M4_E16_MASK = 3595 + + PseudoVFNMSUB_VV_M4_E32 = 3596 + + PseudoVFNMSUB_VV_M4_E32_MASK = 3597 + + PseudoVFNMSUB_VV_M4_E64 = 3598 + + PseudoVFNMSUB_VV_M4_E64_MASK = 3599 + + PseudoVFNMSUB_VV_M8_E16 = 3600 + + PseudoVFNMSUB_VV_M8_E16_MASK = 3601 + + PseudoVFNMSUB_VV_M8_E32 = 3602 + + PseudoVFNMSUB_VV_M8_E32_MASK = 3603 + + PseudoVFNMSUB_VV_M8_E64 = 3604 + + PseudoVFNMSUB_VV_M8_E64_MASK = 3605 + + PseudoVFNMSUB_VV_MF2_E16 = 3606 + + PseudoVFNMSUB_VV_MF2_E16_MASK = 3607 + + PseudoVFNMSUB_VV_MF2_E32 = 3608 + + PseudoVFNMSUB_VV_MF2_E32_MASK = 3609 + + PseudoVFNMSUB_VV_MF4_E16 = 3610 + + PseudoVFNMSUB_VV_MF4_E16_MASK = 3611 + + PseudoVFRDIV_VFPR16_M1_E16 = 3612 + + PseudoVFRDIV_VFPR16_M1_E16_MASK = 3613 + + PseudoVFRDIV_VFPR16_M2_E16 = 3614 + + PseudoVFRDIV_VFPR16_M2_E16_MASK = 3615 + + PseudoVFRDIV_VFPR16_M4_E16 = 3616 + + PseudoVFRDIV_VFPR16_M4_E16_MASK = 3617 + + PseudoVFRDIV_VFPR16_M8_E16 = 3618 + + PseudoVFRDIV_VFPR16_M8_E16_MASK = 3619 + + PseudoVFRDIV_VFPR16_MF2_E16 = 3620 + + PseudoVFRDIV_VFPR16_MF2_E16_MASK = 3621 + + PseudoVFRDIV_VFPR16_MF4_E16 = 3622 + + PseudoVFRDIV_VFPR16_MF4_E16_MASK = 3623 + + PseudoVFRDIV_VFPR32_M1_E32 = 3624 + + PseudoVFRDIV_VFPR32_M1_E32_MASK = 3625 + + PseudoVFRDIV_VFPR32_M2_E32 = 3626 + + PseudoVFRDIV_VFPR32_M2_E32_MASK = 3627 + + PseudoVFRDIV_VFPR32_M4_E32 = 3628 + + PseudoVFRDIV_VFPR32_M4_E32_MASK = 3629 + + PseudoVFRDIV_VFPR32_M8_E32 = 3630 + + PseudoVFRDIV_VFPR32_M8_E32_MASK = 3631 + + PseudoVFRDIV_VFPR32_MF2_E32 = 3632 + + PseudoVFRDIV_VFPR32_MF2_E32_MASK = 3633 + + PseudoVFRDIV_VFPR64_M1_E64 = 3634 + + PseudoVFRDIV_VFPR64_M1_E64_MASK = 3635 + + PseudoVFRDIV_VFPR64_M2_E64 = 3636 + + PseudoVFRDIV_VFPR64_M2_E64_MASK = 3637 + + PseudoVFRDIV_VFPR64_M4_E64 = 3638 + + PseudoVFRDIV_VFPR64_M4_E64_MASK = 3639 + + PseudoVFRDIV_VFPR64_M8_E64 = 3640 + + PseudoVFRDIV_VFPR64_M8_E64_MASK = 3641 + + PseudoVFREC7_ALT_V_M1_E16 = 3642 + + PseudoVFREC7_ALT_V_M1_E16_MASK = 3643 + + PseudoVFREC7_ALT_V_M2_E16 = 3644 + + PseudoVFREC7_ALT_V_M2_E16_MASK = 3645 + + PseudoVFREC7_ALT_V_M4_E16 = 3646 + + PseudoVFREC7_ALT_V_M4_E16_MASK = 3647 + + PseudoVFREC7_ALT_V_M8_E16 = 3648 + + PseudoVFREC7_ALT_V_M8_E16_MASK = 3649 + + PseudoVFREC7_ALT_V_MF2_E16 = 3650 + + PseudoVFREC7_ALT_V_MF2_E16_MASK = 3651 + + PseudoVFREC7_ALT_V_MF4_E16 = 3652 + + PseudoVFREC7_ALT_V_MF4_E16_MASK = 3653 + + PseudoVFREC7_V_M1_E16 = 3654 + + PseudoVFREC7_V_M1_E16_MASK = 3655 + + PseudoVFREC7_V_M1_E32 = 3656 + + PseudoVFREC7_V_M1_E32_MASK = 3657 + + PseudoVFREC7_V_M1_E64 = 3658 + + PseudoVFREC7_V_M1_E64_MASK = 3659 + + PseudoVFREC7_V_M2_E16 = 3660 + + PseudoVFREC7_V_M2_E16_MASK = 3661 + + PseudoVFREC7_V_M2_E32 = 3662 + + PseudoVFREC7_V_M2_E32_MASK = 3663 + + PseudoVFREC7_V_M2_E64 = 3664 + + PseudoVFREC7_V_M2_E64_MASK = 3665 + + PseudoVFREC7_V_M4_E16 = 3666 + + PseudoVFREC7_V_M4_E16_MASK = 3667 + + PseudoVFREC7_V_M4_E32 = 3668 + + PseudoVFREC7_V_M4_E32_MASK = 3669 + + PseudoVFREC7_V_M4_E64 = 3670 + + PseudoVFREC7_V_M4_E64_MASK = 3671 + + PseudoVFREC7_V_M8_E16 = 3672 + + PseudoVFREC7_V_M8_E16_MASK = 3673 + + PseudoVFREC7_V_M8_E32 = 3674 + + PseudoVFREC7_V_M8_E32_MASK = 3675 + + PseudoVFREC7_V_M8_E64 = 3676 + + PseudoVFREC7_V_M8_E64_MASK = 3677 + + PseudoVFREC7_V_MF2_E16 = 3678 + + PseudoVFREC7_V_MF2_E16_MASK = 3679 + + PseudoVFREC7_V_MF2_E32 = 3680 + + PseudoVFREC7_V_MF2_E32_MASK = 3681 + + PseudoVFREC7_V_MF4_E16 = 3682 + + PseudoVFREC7_V_MF4_E16_MASK = 3683 + + PseudoVFREDMAX_VS_M1_E16 = 3684 + + PseudoVFREDMAX_VS_M1_E16_MASK = 3685 + + PseudoVFREDMAX_VS_M1_E32 = 3686 + + PseudoVFREDMAX_VS_M1_E32_MASK = 3687 + + PseudoVFREDMAX_VS_M1_E64 = 3688 + + PseudoVFREDMAX_VS_M1_E64_MASK = 3689 + + PseudoVFREDMAX_VS_M2_E16 = 3690 + + PseudoVFREDMAX_VS_M2_E16_MASK = 3691 + + PseudoVFREDMAX_VS_M2_E32 = 3692 + + PseudoVFREDMAX_VS_M2_E32_MASK = 3693 + + PseudoVFREDMAX_VS_M2_E64 = 3694 + + PseudoVFREDMAX_VS_M2_E64_MASK = 3695 + + PseudoVFREDMAX_VS_M4_E16 = 3696 + + PseudoVFREDMAX_VS_M4_E16_MASK = 3697 + + PseudoVFREDMAX_VS_M4_E32 = 3698 + + PseudoVFREDMAX_VS_M4_E32_MASK = 3699 + + PseudoVFREDMAX_VS_M4_E64 = 3700 + + PseudoVFREDMAX_VS_M4_E64_MASK = 3701 + + PseudoVFREDMAX_VS_M8_E16 = 3702 + + PseudoVFREDMAX_VS_M8_E16_MASK = 3703 + + PseudoVFREDMAX_VS_M8_E32 = 3704 + + PseudoVFREDMAX_VS_M8_E32_MASK = 3705 + + PseudoVFREDMAX_VS_M8_E64 = 3706 + + PseudoVFREDMAX_VS_M8_E64_MASK = 3707 + + PseudoVFREDMAX_VS_MF2_E16 = 3708 + + PseudoVFREDMAX_VS_MF2_E16_MASK = 3709 + + PseudoVFREDMAX_VS_MF2_E32 = 3710 + + PseudoVFREDMAX_VS_MF2_E32_MASK = 3711 + + PseudoVFREDMAX_VS_MF4_E16 = 3712 + + PseudoVFREDMAX_VS_MF4_E16_MASK = 3713 + + PseudoVFREDMIN_VS_M1_E16 = 3714 + + PseudoVFREDMIN_VS_M1_E16_MASK = 3715 + + PseudoVFREDMIN_VS_M1_E32 = 3716 + + PseudoVFREDMIN_VS_M1_E32_MASK = 3717 + + PseudoVFREDMIN_VS_M1_E64 = 3718 + + PseudoVFREDMIN_VS_M1_E64_MASK = 3719 + + PseudoVFREDMIN_VS_M2_E16 = 3720 + + PseudoVFREDMIN_VS_M2_E16_MASK = 3721 + + PseudoVFREDMIN_VS_M2_E32 = 3722 + + PseudoVFREDMIN_VS_M2_E32_MASK = 3723 + + PseudoVFREDMIN_VS_M2_E64 = 3724 + + PseudoVFREDMIN_VS_M2_E64_MASK = 3725 + + PseudoVFREDMIN_VS_M4_E16 = 3726 + + PseudoVFREDMIN_VS_M4_E16_MASK = 3727 + + PseudoVFREDMIN_VS_M4_E32 = 3728 + + PseudoVFREDMIN_VS_M4_E32_MASK = 3729 + + PseudoVFREDMIN_VS_M4_E64 = 3730 + + PseudoVFREDMIN_VS_M4_E64_MASK = 3731 + + PseudoVFREDMIN_VS_M8_E16 = 3732 + + PseudoVFREDMIN_VS_M8_E16_MASK = 3733 + + PseudoVFREDMIN_VS_M8_E32 = 3734 + + PseudoVFREDMIN_VS_M8_E32_MASK = 3735 + + PseudoVFREDMIN_VS_M8_E64 = 3736 + + PseudoVFREDMIN_VS_M8_E64_MASK = 3737 + + PseudoVFREDMIN_VS_MF2_E16 = 3738 + + PseudoVFREDMIN_VS_MF2_E16_MASK = 3739 + + PseudoVFREDMIN_VS_MF2_E32 = 3740 + + PseudoVFREDMIN_VS_MF2_E32_MASK = 3741 + + PseudoVFREDMIN_VS_MF4_E16 = 3742 + + PseudoVFREDMIN_VS_MF4_E16_MASK = 3743 + + PseudoVFREDOSUM_VS_M1_E16 = 3744 + + PseudoVFREDOSUM_VS_M1_E16_MASK = 3745 + + PseudoVFREDOSUM_VS_M1_E32 = 3746 + + PseudoVFREDOSUM_VS_M1_E32_MASK = 3747 + + PseudoVFREDOSUM_VS_M1_E64 = 3748 + + PseudoVFREDOSUM_VS_M1_E64_MASK = 3749 + + PseudoVFREDOSUM_VS_M2_E16 = 3750 + + PseudoVFREDOSUM_VS_M2_E16_MASK = 3751 + + PseudoVFREDOSUM_VS_M2_E32 = 3752 + + PseudoVFREDOSUM_VS_M2_E32_MASK = 3753 + + PseudoVFREDOSUM_VS_M2_E64 = 3754 + + PseudoVFREDOSUM_VS_M2_E64_MASK = 3755 + + PseudoVFREDOSUM_VS_M4_E16 = 3756 + + PseudoVFREDOSUM_VS_M4_E16_MASK = 3757 + + PseudoVFREDOSUM_VS_M4_E32 = 3758 + + PseudoVFREDOSUM_VS_M4_E32_MASK = 3759 + + PseudoVFREDOSUM_VS_M4_E64 = 3760 + + PseudoVFREDOSUM_VS_M4_E64_MASK = 3761 + + PseudoVFREDOSUM_VS_M8_E16 = 3762 + + PseudoVFREDOSUM_VS_M8_E16_MASK = 3763 + + PseudoVFREDOSUM_VS_M8_E32 = 3764 + + PseudoVFREDOSUM_VS_M8_E32_MASK = 3765 + + PseudoVFREDOSUM_VS_M8_E64 = 3766 + + PseudoVFREDOSUM_VS_M8_E64_MASK = 3767 + + PseudoVFREDOSUM_VS_MF2_E16 = 3768 + + PseudoVFREDOSUM_VS_MF2_E16_MASK = 3769 + + PseudoVFREDOSUM_VS_MF2_E32 = 3770 + + PseudoVFREDOSUM_VS_MF2_E32_MASK = 3771 + + PseudoVFREDOSUM_VS_MF4_E16 = 3772 + + PseudoVFREDOSUM_VS_MF4_E16_MASK = 3773 + + PseudoVFREDUSUM_VS_M1_E16 = 3774 + + PseudoVFREDUSUM_VS_M1_E16_MASK = 3775 + + PseudoVFREDUSUM_VS_M1_E32 = 3776 + + PseudoVFREDUSUM_VS_M1_E32_MASK = 3777 + + PseudoVFREDUSUM_VS_M1_E64 = 3778 + + PseudoVFREDUSUM_VS_M1_E64_MASK = 3779 + + PseudoVFREDUSUM_VS_M2_E16 = 3780 + + PseudoVFREDUSUM_VS_M2_E16_MASK = 3781 + + PseudoVFREDUSUM_VS_M2_E32 = 3782 + + PseudoVFREDUSUM_VS_M2_E32_MASK = 3783 + + PseudoVFREDUSUM_VS_M2_E64 = 3784 + + PseudoVFREDUSUM_VS_M2_E64_MASK = 3785 + + PseudoVFREDUSUM_VS_M4_E16 = 3786 + + PseudoVFREDUSUM_VS_M4_E16_MASK = 3787 + + PseudoVFREDUSUM_VS_M4_E32 = 3788 + + PseudoVFREDUSUM_VS_M4_E32_MASK = 3789 + + PseudoVFREDUSUM_VS_M4_E64 = 3790 + + PseudoVFREDUSUM_VS_M4_E64_MASK = 3791 + + PseudoVFREDUSUM_VS_M8_E16 = 3792 + + PseudoVFREDUSUM_VS_M8_E16_MASK = 3793 + + PseudoVFREDUSUM_VS_M8_E32 = 3794 + + PseudoVFREDUSUM_VS_M8_E32_MASK = 3795 + + PseudoVFREDUSUM_VS_M8_E64 = 3796 + + PseudoVFREDUSUM_VS_M8_E64_MASK = 3797 + + PseudoVFREDUSUM_VS_MF2_E16 = 3798 + + PseudoVFREDUSUM_VS_MF2_E16_MASK = 3799 + + PseudoVFREDUSUM_VS_MF2_E32 = 3800 + + PseudoVFREDUSUM_VS_MF2_E32_MASK = 3801 + + PseudoVFREDUSUM_VS_MF4_E16 = 3802 + + PseudoVFREDUSUM_VS_MF4_E16_MASK = 3803 + + PseudoVFROUND_NOEXCEPT_V_M1_MASK = 3804 + + PseudoVFROUND_NOEXCEPT_V_M2_MASK = 3805 + + PseudoVFROUND_NOEXCEPT_V_M4_MASK = 3806 + + PseudoVFROUND_NOEXCEPT_V_M8_MASK = 3807 + + PseudoVFROUND_NOEXCEPT_V_MF2_MASK = 3808 + + PseudoVFROUND_NOEXCEPT_V_MF4_MASK = 3809 + + PseudoVFRSQRT7_ALT_V_M1_E16 = 3810 + + PseudoVFRSQRT7_ALT_V_M1_E16_MASK = 3811 + + PseudoVFRSQRT7_ALT_V_M2_E16 = 3812 + + PseudoVFRSQRT7_ALT_V_M2_E16_MASK = 3813 + + PseudoVFRSQRT7_ALT_V_M4_E16 = 3814 + + PseudoVFRSQRT7_ALT_V_M4_E16_MASK = 3815 + + PseudoVFRSQRT7_ALT_V_M8_E16 = 3816 + + PseudoVFRSQRT7_ALT_V_M8_E16_MASK = 3817 + + PseudoVFRSQRT7_ALT_V_MF2_E16 = 3818 + + PseudoVFRSQRT7_ALT_V_MF2_E16_MASK = 3819 + + PseudoVFRSQRT7_ALT_V_MF4_E16 = 3820 + + PseudoVFRSQRT7_ALT_V_MF4_E16_MASK = 3821 + + PseudoVFRSQRT7_V_M1_E16 = 3822 + + PseudoVFRSQRT7_V_M1_E16_MASK = 3823 + + PseudoVFRSQRT7_V_M1_E32 = 3824 + + PseudoVFRSQRT7_V_M1_E32_MASK = 3825 + + PseudoVFRSQRT7_V_M1_E64 = 3826 + + PseudoVFRSQRT7_V_M1_E64_MASK = 3827 + + PseudoVFRSQRT7_V_M2_E16 = 3828 + + PseudoVFRSQRT7_V_M2_E16_MASK = 3829 + + PseudoVFRSQRT7_V_M2_E32 = 3830 + + PseudoVFRSQRT7_V_M2_E32_MASK = 3831 + + PseudoVFRSQRT7_V_M2_E64 = 3832 + + PseudoVFRSQRT7_V_M2_E64_MASK = 3833 + + PseudoVFRSQRT7_V_M4_E16 = 3834 + + PseudoVFRSQRT7_V_M4_E16_MASK = 3835 + + PseudoVFRSQRT7_V_M4_E32 = 3836 + + PseudoVFRSQRT7_V_M4_E32_MASK = 3837 + + PseudoVFRSQRT7_V_M4_E64 = 3838 + + PseudoVFRSQRT7_V_M4_E64_MASK = 3839 + + PseudoVFRSQRT7_V_M8_E16 = 3840 + + PseudoVFRSQRT7_V_M8_E16_MASK = 3841 + + PseudoVFRSQRT7_V_M8_E32 = 3842 + + PseudoVFRSQRT7_V_M8_E32_MASK = 3843 + + PseudoVFRSQRT7_V_M8_E64 = 3844 + + PseudoVFRSQRT7_V_M8_E64_MASK = 3845 + + PseudoVFRSQRT7_V_MF2_E16 = 3846 + + PseudoVFRSQRT7_V_MF2_E16_MASK = 3847 + + PseudoVFRSQRT7_V_MF2_E32 = 3848 + + PseudoVFRSQRT7_V_MF2_E32_MASK = 3849 + + PseudoVFRSQRT7_V_MF4_E16 = 3850 + + PseudoVFRSQRT7_V_MF4_E16_MASK = 3851 + + PseudoVFRSUB_ALT_VFPR16_M1_E16 = 3852 + + PseudoVFRSUB_ALT_VFPR16_M1_E16_MASK = 3853 + + PseudoVFRSUB_ALT_VFPR16_M2_E16 = 3854 + + PseudoVFRSUB_ALT_VFPR16_M2_E16_MASK = 3855 + + PseudoVFRSUB_ALT_VFPR16_M4_E16 = 3856 + + PseudoVFRSUB_ALT_VFPR16_M4_E16_MASK = 3857 + + PseudoVFRSUB_ALT_VFPR16_M8_E16 = 3858 + + PseudoVFRSUB_ALT_VFPR16_M8_E16_MASK = 3859 + + PseudoVFRSUB_ALT_VFPR16_MF2_E16 = 3860 + + PseudoVFRSUB_ALT_VFPR16_MF2_E16_MASK = 3861 + + PseudoVFRSUB_ALT_VFPR16_MF4_E16 = 3862 + + PseudoVFRSUB_ALT_VFPR16_MF4_E16_MASK = 3863 + + PseudoVFRSUB_VFPR16_M1_E16 = 3864 + + PseudoVFRSUB_VFPR16_M1_E16_MASK = 3865 + + PseudoVFRSUB_VFPR16_M2_E16 = 3866 + + PseudoVFRSUB_VFPR16_M2_E16_MASK = 3867 + + PseudoVFRSUB_VFPR16_M4_E16 = 3868 + + PseudoVFRSUB_VFPR16_M4_E16_MASK = 3869 + + PseudoVFRSUB_VFPR16_M8_E16 = 3870 + + PseudoVFRSUB_VFPR16_M8_E16_MASK = 3871 + + PseudoVFRSUB_VFPR16_MF2_E16 = 3872 + + PseudoVFRSUB_VFPR16_MF2_E16_MASK = 3873 + + PseudoVFRSUB_VFPR16_MF4_E16 = 3874 + + PseudoVFRSUB_VFPR16_MF4_E16_MASK = 3875 + + PseudoVFRSUB_VFPR32_M1_E32 = 3876 + + PseudoVFRSUB_VFPR32_M1_E32_MASK = 3877 + + PseudoVFRSUB_VFPR32_M2_E32 = 3878 + + PseudoVFRSUB_VFPR32_M2_E32_MASK = 3879 + + PseudoVFRSUB_VFPR32_M4_E32 = 3880 + + PseudoVFRSUB_VFPR32_M4_E32_MASK = 3881 + + PseudoVFRSUB_VFPR32_M8_E32 = 3882 + + PseudoVFRSUB_VFPR32_M8_E32_MASK = 3883 + + PseudoVFRSUB_VFPR32_MF2_E32 = 3884 + + PseudoVFRSUB_VFPR32_MF2_E32_MASK = 3885 + + PseudoVFRSUB_VFPR64_M1_E64 = 3886 + + PseudoVFRSUB_VFPR64_M1_E64_MASK = 3887 + + PseudoVFRSUB_VFPR64_M2_E64 = 3888 + + PseudoVFRSUB_VFPR64_M2_E64_MASK = 3889 + + PseudoVFRSUB_VFPR64_M4_E64 = 3890 + + PseudoVFRSUB_VFPR64_M4_E64_MASK = 3891 + + PseudoVFRSUB_VFPR64_M8_E64 = 3892 + + PseudoVFRSUB_VFPR64_M8_E64_MASK = 3893 + + PseudoVFSGNJN_ALT_VFPR16_M1_E16 = 3894 + + PseudoVFSGNJN_ALT_VFPR16_M1_E16_MASK = 3895 + + PseudoVFSGNJN_ALT_VFPR16_M2_E16 = 3896 + + PseudoVFSGNJN_ALT_VFPR16_M2_E16_MASK = 3897 + + PseudoVFSGNJN_ALT_VFPR16_M4_E16 = 3898 + + PseudoVFSGNJN_ALT_VFPR16_M4_E16_MASK = 3899 + + PseudoVFSGNJN_ALT_VFPR16_M8_E16 = 3900 + + PseudoVFSGNJN_ALT_VFPR16_M8_E16_MASK = 3901 + + PseudoVFSGNJN_ALT_VFPR16_MF2_E16 = 3902 + + PseudoVFSGNJN_ALT_VFPR16_MF2_E16_MASK = 3903 + + PseudoVFSGNJN_ALT_VFPR16_MF4_E16 = 3904 + + PseudoVFSGNJN_ALT_VFPR16_MF4_E16_MASK = 3905 + + PseudoVFSGNJN_ALT_VV_M1_E16 = 3906 + + PseudoVFSGNJN_ALT_VV_M1_E16_MASK = 3907 + + PseudoVFSGNJN_ALT_VV_M2_E16 = 3908 + + PseudoVFSGNJN_ALT_VV_M2_E16_MASK = 3909 + + PseudoVFSGNJN_ALT_VV_M4_E16 = 3910 + + PseudoVFSGNJN_ALT_VV_M4_E16_MASK = 3911 + + PseudoVFSGNJN_ALT_VV_M8_E16 = 3912 + + PseudoVFSGNJN_ALT_VV_M8_E16_MASK = 3913 + + PseudoVFSGNJN_ALT_VV_MF2_E16 = 3914 + + PseudoVFSGNJN_ALT_VV_MF2_E16_MASK = 3915 + + PseudoVFSGNJN_ALT_VV_MF4_E16 = 3916 + + PseudoVFSGNJN_ALT_VV_MF4_E16_MASK = 3917 + + PseudoVFSGNJN_VFPR16_M1_E16 = 3918 + + PseudoVFSGNJN_VFPR16_M1_E16_MASK = 3919 + + PseudoVFSGNJN_VFPR16_M2_E16 = 3920 + + PseudoVFSGNJN_VFPR16_M2_E16_MASK = 3921 + + PseudoVFSGNJN_VFPR16_M4_E16 = 3922 + + PseudoVFSGNJN_VFPR16_M4_E16_MASK = 3923 + + PseudoVFSGNJN_VFPR16_M8_E16 = 3924 + + PseudoVFSGNJN_VFPR16_M8_E16_MASK = 3925 + + PseudoVFSGNJN_VFPR16_MF2_E16 = 3926 + + PseudoVFSGNJN_VFPR16_MF2_E16_MASK = 3927 + + PseudoVFSGNJN_VFPR16_MF4_E16 = 3928 + + PseudoVFSGNJN_VFPR16_MF4_E16_MASK = 3929 + + PseudoVFSGNJN_VFPR32_M1_E32 = 3930 + + PseudoVFSGNJN_VFPR32_M1_E32_MASK = 3931 + + PseudoVFSGNJN_VFPR32_M2_E32 = 3932 + + PseudoVFSGNJN_VFPR32_M2_E32_MASK = 3933 + + PseudoVFSGNJN_VFPR32_M4_E32 = 3934 + + PseudoVFSGNJN_VFPR32_M4_E32_MASK = 3935 + + PseudoVFSGNJN_VFPR32_M8_E32 = 3936 + + PseudoVFSGNJN_VFPR32_M8_E32_MASK = 3937 + + PseudoVFSGNJN_VFPR32_MF2_E32 = 3938 + + PseudoVFSGNJN_VFPR32_MF2_E32_MASK = 3939 + + PseudoVFSGNJN_VFPR64_M1_E64 = 3940 + + PseudoVFSGNJN_VFPR64_M1_E64_MASK = 3941 + + PseudoVFSGNJN_VFPR64_M2_E64 = 3942 + + PseudoVFSGNJN_VFPR64_M2_E64_MASK = 3943 + + PseudoVFSGNJN_VFPR64_M4_E64 = 3944 + + PseudoVFSGNJN_VFPR64_M4_E64_MASK = 3945 + + PseudoVFSGNJN_VFPR64_M8_E64 = 3946 + + PseudoVFSGNJN_VFPR64_M8_E64_MASK = 3947 + + PseudoVFSGNJN_VV_M1_E16 = 3948 + + PseudoVFSGNJN_VV_M1_E16_MASK = 3949 + + PseudoVFSGNJN_VV_M1_E32 = 3950 + + PseudoVFSGNJN_VV_M1_E32_MASK = 3951 + + PseudoVFSGNJN_VV_M1_E64 = 3952 + + PseudoVFSGNJN_VV_M1_E64_MASK = 3953 + + PseudoVFSGNJN_VV_M2_E16 = 3954 + + PseudoVFSGNJN_VV_M2_E16_MASK = 3955 + + PseudoVFSGNJN_VV_M2_E32 = 3956 + + PseudoVFSGNJN_VV_M2_E32_MASK = 3957 + + PseudoVFSGNJN_VV_M2_E64 = 3958 + + PseudoVFSGNJN_VV_M2_E64_MASK = 3959 + + PseudoVFSGNJN_VV_M4_E16 = 3960 + + PseudoVFSGNJN_VV_M4_E16_MASK = 3961 + + PseudoVFSGNJN_VV_M4_E32 = 3962 + + PseudoVFSGNJN_VV_M4_E32_MASK = 3963 + + PseudoVFSGNJN_VV_M4_E64 = 3964 + + PseudoVFSGNJN_VV_M4_E64_MASK = 3965 + + PseudoVFSGNJN_VV_M8_E16 = 3966 + + PseudoVFSGNJN_VV_M8_E16_MASK = 3967 + + PseudoVFSGNJN_VV_M8_E32 = 3968 + + PseudoVFSGNJN_VV_M8_E32_MASK = 3969 + + PseudoVFSGNJN_VV_M8_E64 = 3970 + + PseudoVFSGNJN_VV_M8_E64_MASK = 3971 + + PseudoVFSGNJN_VV_MF2_E16 = 3972 + + PseudoVFSGNJN_VV_MF2_E16_MASK = 3973 + + PseudoVFSGNJN_VV_MF2_E32 = 3974 + + PseudoVFSGNJN_VV_MF2_E32_MASK = 3975 + + PseudoVFSGNJN_VV_MF4_E16 = 3976 + + PseudoVFSGNJN_VV_MF4_E16_MASK = 3977 + + PseudoVFSGNJX_ALT_VFPR16_M1_E16 = 3978 + + PseudoVFSGNJX_ALT_VFPR16_M1_E16_MASK = 3979 + + PseudoVFSGNJX_ALT_VFPR16_M2_E16 = 3980 + + PseudoVFSGNJX_ALT_VFPR16_M2_E16_MASK = 3981 + + PseudoVFSGNJX_ALT_VFPR16_M4_E16 = 3982 + + PseudoVFSGNJX_ALT_VFPR16_M4_E16_MASK = 3983 + + PseudoVFSGNJX_ALT_VFPR16_M8_E16 = 3984 + + PseudoVFSGNJX_ALT_VFPR16_M8_E16_MASK = 3985 + + PseudoVFSGNJX_ALT_VFPR16_MF2_E16 = 3986 + + PseudoVFSGNJX_ALT_VFPR16_MF2_E16_MASK = 3987 + + PseudoVFSGNJX_ALT_VFPR16_MF4_E16 = 3988 + + PseudoVFSGNJX_ALT_VFPR16_MF4_E16_MASK = 3989 + + PseudoVFSGNJX_ALT_VV_M1_E16 = 3990 + + PseudoVFSGNJX_ALT_VV_M1_E16_MASK = 3991 + + PseudoVFSGNJX_ALT_VV_M2_E16 = 3992 + + PseudoVFSGNJX_ALT_VV_M2_E16_MASK = 3993 + + PseudoVFSGNJX_ALT_VV_M4_E16 = 3994 + + PseudoVFSGNJX_ALT_VV_M4_E16_MASK = 3995 + + PseudoVFSGNJX_ALT_VV_M8_E16 = 3996 + + PseudoVFSGNJX_ALT_VV_M8_E16_MASK = 3997 + + PseudoVFSGNJX_ALT_VV_MF2_E16 = 3998 + + PseudoVFSGNJX_ALT_VV_MF2_E16_MASK = 3999 + + PseudoVFSGNJX_ALT_VV_MF4_E16 = 4000 + + PseudoVFSGNJX_ALT_VV_MF4_E16_MASK = 4001 + + PseudoVFSGNJX_VFPR16_M1_E16 = 4002 + + PseudoVFSGNJX_VFPR16_M1_E16_MASK = 4003 + + PseudoVFSGNJX_VFPR16_M2_E16 = 4004 + + PseudoVFSGNJX_VFPR16_M2_E16_MASK = 4005 + + PseudoVFSGNJX_VFPR16_M4_E16 = 4006 + + PseudoVFSGNJX_VFPR16_M4_E16_MASK = 4007 + + PseudoVFSGNJX_VFPR16_M8_E16 = 4008 + + PseudoVFSGNJX_VFPR16_M8_E16_MASK = 4009 + + PseudoVFSGNJX_VFPR16_MF2_E16 = 4010 + + PseudoVFSGNJX_VFPR16_MF2_E16_MASK = 4011 + + PseudoVFSGNJX_VFPR16_MF4_E16 = 4012 + + PseudoVFSGNJX_VFPR16_MF4_E16_MASK = 4013 + + PseudoVFSGNJX_VFPR32_M1_E32 = 4014 + + PseudoVFSGNJX_VFPR32_M1_E32_MASK = 4015 + + PseudoVFSGNJX_VFPR32_M2_E32 = 4016 + + PseudoVFSGNJX_VFPR32_M2_E32_MASK = 4017 + + PseudoVFSGNJX_VFPR32_M4_E32 = 4018 + + PseudoVFSGNJX_VFPR32_M4_E32_MASK = 4019 + + PseudoVFSGNJX_VFPR32_M8_E32 = 4020 + + PseudoVFSGNJX_VFPR32_M8_E32_MASK = 4021 + + PseudoVFSGNJX_VFPR32_MF2_E32 = 4022 + + PseudoVFSGNJX_VFPR32_MF2_E32_MASK = 4023 + + PseudoVFSGNJX_VFPR64_M1_E64 = 4024 + + PseudoVFSGNJX_VFPR64_M1_E64_MASK = 4025 + + PseudoVFSGNJX_VFPR64_M2_E64 = 4026 + + PseudoVFSGNJX_VFPR64_M2_E64_MASK = 4027 + + PseudoVFSGNJX_VFPR64_M4_E64 = 4028 + + PseudoVFSGNJX_VFPR64_M4_E64_MASK = 4029 + + PseudoVFSGNJX_VFPR64_M8_E64 = 4030 + + PseudoVFSGNJX_VFPR64_M8_E64_MASK = 4031 + + PseudoVFSGNJX_VV_M1_E16 = 4032 + + PseudoVFSGNJX_VV_M1_E16_MASK = 4033 + + PseudoVFSGNJX_VV_M1_E32 = 4034 + + PseudoVFSGNJX_VV_M1_E32_MASK = 4035 + + PseudoVFSGNJX_VV_M1_E64 = 4036 + + PseudoVFSGNJX_VV_M1_E64_MASK = 4037 + + PseudoVFSGNJX_VV_M2_E16 = 4038 + + PseudoVFSGNJX_VV_M2_E16_MASK = 4039 + + PseudoVFSGNJX_VV_M2_E32 = 4040 + + PseudoVFSGNJX_VV_M2_E32_MASK = 4041 + + PseudoVFSGNJX_VV_M2_E64 = 4042 + + PseudoVFSGNJX_VV_M2_E64_MASK = 4043 + + PseudoVFSGNJX_VV_M4_E16 = 4044 + + PseudoVFSGNJX_VV_M4_E16_MASK = 4045 + + PseudoVFSGNJX_VV_M4_E32 = 4046 + + PseudoVFSGNJX_VV_M4_E32_MASK = 4047 + + PseudoVFSGNJX_VV_M4_E64 = 4048 + + PseudoVFSGNJX_VV_M4_E64_MASK = 4049 + + PseudoVFSGNJX_VV_M8_E16 = 4050 + + PseudoVFSGNJX_VV_M8_E16_MASK = 4051 + + PseudoVFSGNJX_VV_M8_E32 = 4052 + + PseudoVFSGNJX_VV_M8_E32_MASK = 4053 + + PseudoVFSGNJX_VV_M8_E64 = 4054 + + PseudoVFSGNJX_VV_M8_E64_MASK = 4055 + + PseudoVFSGNJX_VV_MF2_E16 = 4056 + + PseudoVFSGNJX_VV_MF2_E16_MASK = 4057 + + PseudoVFSGNJX_VV_MF2_E32 = 4058 + + PseudoVFSGNJX_VV_MF2_E32_MASK = 4059 + + PseudoVFSGNJX_VV_MF4_E16 = 4060 + + PseudoVFSGNJX_VV_MF4_E16_MASK = 4061 + + PseudoVFSGNJ_ALT_VFPR16_M1_E16 = 4062 + + PseudoVFSGNJ_ALT_VFPR16_M1_E16_MASK = 4063 + + PseudoVFSGNJ_ALT_VFPR16_M2_E16 = 4064 + + PseudoVFSGNJ_ALT_VFPR16_M2_E16_MASK = 4065 + + PseudoVFSGNJ_ALT_VFPR16_M4_E16 = 4066 + + PseudoVFSGNJ_ALT_VFPR16_M4_E16_MASK = 4067 + + PseudoVFSGNJ_ALT_VFPR16_M8_E16 = 4068 + + PseudoVFSGNJ_ALT_VFPR16_M8_E16_MASK = 4069 + + PseudoVFSGNJ_ALT_VFPR16_MF2_E16 = 4070 + + PseudoVFSGNJ_ALT_VFPR16_MF2_E16_MASK = 4071 + + PseudoVFSGNJ_ALT_VFPR16_MF4_E16 = 4072 + + PseudoVFSGNJ_ALT_VFPR16_MF4_E16_MASK = 4073 + + PseudoVFSGNJ_ALT_VV_M1_E16 = 4074 + + PseudoVFSGNJ_ALT_VV_M1_E16_MASK = 4075 + + PseudoVFSGNJ_ALT_VV_M2_E16 = 4076 + + PseudoVFSGNJ_ALT_VV_M2_E16_MASK = 4077 + + PseudoVFSGNJ_ALT_VV_M4_E16 = 4078 + + PseudoVFSGNJ_ALT_VV_M4_E16_MASK = 4079 + + PseudoVFSGNJ_ALT_VV_M8_E16 = 4080 + + PseudoVFSGNJ_ALT_VV_M8_E16_MASK = 4081 + + PseudoVFSGNJ_ALT_VV_MF2_E16 = 4082 + + PseudoVFSGNJ_ALT_VV_MF2_E16_MASK = 4083 + + PseudoVFSGNJ_ALT_VV_MF4_E16 = 4084 + + PseudoVFSGNJ_ALT_VV_MF4_E16_MASK = 4085 + + PseudoVFSGNJ_VFPR16_M1_E16 = 4086 + + PseudoVFSGNJ_VFPR16_M1_E16_MASK = 4087 + + PseudoVFSGNJ_VFPR16_M2_E16 = 4088 + + PseudoVFSGNJ_VFPR16_M2_E16_MASK = 4089 + + PseudoVFSGNJ_VFPR16_M4_E16 = 4090 + + PseudoVFSGNJ_VFPR16_M4_E16_MASK = 4091 + + PseudoVFSGNJ_VFPR16_M8_E16 = 4092 + + PseudoVFSGNJ_VFPR16_M8_E16_MASK = 4093 + + PseudoVFSGNJ_VFPR16_MF2_E16 = 4094 + + PseudoVFSGNJ_VFPR16_MF2_E16_MASK = 4095 + + PseudoVFSGNJ_VFPR16_MF4_E16 = 4096 + + PseudoVFSGNJ_VFPR16_MF4_E16_MASK = 4097 + + PseudoVFSGNJ_VFPR32_M1_E32 = 4098 + + PseudoVFSGNJ_VFPR32_M1_E32_MASK = 4099 + + PseudoVFSGNJ_VFPR32_M2_E32 = 4100 + + PseudoVFSGNJ_VFPR32_M2_E32_MASK = 4101 + + PseudoVFSGNJ_VFPR32_M4_E32 = 4102 + + PseudoVFSGNJ_VFPR32_M4_E32_MASK = 4103 + + PseudoVFSGNJ_VFPR32_M8_E32 = 4104 + + PseudoVFSGNJ_VFPR32_M8_E32_MASK = 4105 + + PseudoVFSGNJ_VFPR32_MF2_E32 = 4106 + + PseudoVFSGNJ_VFPR32_MF2_E32_MASK = 4107 + + PseudoVFSGNJ_VFPR64_M1_E64 = 4108 + + PseudoVFSGNJ_VFPR64_M1_E64_MASK = 4109 + + PseudoVFSGNJ_VFPR64_M2_E64 = 4110 + + PseudoVFSGNJ_VFPR64_M2_E64_MASK = 4111 + + PseudoVFSGNJ_VFPR64_M4_E64 = 4112 + + PseudoVFSGNJ_VFPR64_M4_E64_MASK = 4113 + + PseudoVFSGNJ_VFPR64_M8_E64 = 4114 + + PseudoVFSGNJ_VFPR64_M8_E64_MASK = 4115 + + PseudoVFSGNJ_VV_M1_E16 = 4116 + + PseudoVFSGNJ_VV_M1_E16_MASK = 4117 + + PseudoVFSGNJ_VV_M1_E32 = 4118 + + PseudoVFSGNJ_VV_M1_E32_MASK = 4119 + + PseudoVFSGNJ_VV_M1_E64 = 4120 + + PseudoVFSGNJ_VV_M1_E64_MASK = 4121 + + PseudoVFSGNJ_VV_M2_E16 = 4122 + + PseudoVFSGNJ_VV_M2_E16_MASK = 4123 + + PseudoVFSGNJ_VV_M2_E32 = 4124 + + PseudoVFSGNJ_VV_M2_E32_MASK = 4125 + + PseudoVFSGNJ_VV_M2_E64 = 4126 + + PseudoVFSGNJ_VV_M2_E64_MASK = 4127 + + PseudoVFSGNJ_VV_M4_E16 = 4128 + + PseudoVFSGNJ_VV_M4_E16_MASK = 4129 + + PseudoVFSGNJ_VV_M4_E32 = 4130 + + PseudoVFSGNJ_VV_M4_E32_MASK = 4131 + + PseudoVFSGNJ_VV_M4_E64 = 4132 + + PseudoVFSGNJ_VV_M4_E64_MASK = 4133 + + PseudoVFSGNJ_VV_M8_E16 = 4134 + + PseudoVFSGNJ_VV_M8_E16_MASK = 4135 + + PseudoVFSGNJ_VV_M8_E32 = 4136 + + PseudoVFSGNJ_VV_M8_E32_MASK = 4137 + + PseudoVFSGNJ_VV_M8_E64 = 4138 + + PseudoVFSGNJ_VV_M8_E64_MASK = 4139 + + PseudoVFSGNJ_VV_MF2_E16 = 4140 + + PseudoVFSGNJ_VV_MF2_E16_MASK = 4141 + + PseudoVFSGNJ_VV_MF2_E32 = 4142 + + PseudoVFSGNJ_VV_MF2_E32_MASK = 4143 + + PseudoVFSGNJ_VV_MF4_E16 = 4144 + + PseudoVFSGNJ_VV_MF4_E16_MASK = 4145 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M1 = 4146 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M1_MASK = 4147 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M2 = 4148 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M2_MASK = 4149 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M4 = 4150 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M4_MASK = 4151 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M8 = 4152 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_M8_MASK = 4153 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2 = 4154 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2_MASK = 4155 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4 = 4156 + + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4_MASK = 4157 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M1 = 4158 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M1_MASK = 4159 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M2 = 4160 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M2_MASK = 4161 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M4 = 4162 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M4_MASK = 4163 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M8 = 4164 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_M8_MASK = 4165 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2 = 4166 + + PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2_MASK = 4167 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M1 = 4168 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M1_MASK = 4169 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M2 = 4170 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M2_MASK = 4171 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M4 = 4172 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M4_MASK = 4173 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M8 = 4174 + + PseudoVFSLIDE1DOWN_ALT_VFPR64_M8_MASK = 4175 + + PseudoVFSLIDE1DOWN_VFPR16_M1 = 4176 + + PseudoVFSLIDE1DOWN_VFPR16_M1_MASK = 4177 + + PseudoVFSLIDE1DOWN_VFPR16_M2 = 4178 + + PseudoVFSLIDE1DOWN_VFPR16_M2_MASK = 4179 + + PseudoVFSLIDE1DOWN_VFPR16_M4 = 4180 + + PseudoVFSLIDE1DOWN_VFPR16_M4_MASK = 4181 + + PseudoVFSLIDE1DOWN_VFPR16_M8 = 4182 + + PseudoVFSLIDE1DOWN_VFPR16_M8_MASK = 4183 + + PseudoVFSLIDE1DOWN_VFPR16_MF2 = 4184 + + PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK = 4185 + + PseudoVFSLIDE1DOWN_VFPR16_MF4 = 4186 + + PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK = 4187 + + PseudoVFSLIDE1DOWN_VFPR32_M1 = 4188 + + PseudoVFSLIDE1DOWN_VFPR32_M1_MASK = 4189 + + PseudoVFSLIDE1DOWN_VFPR32_M2 = 4190 + + PseudoVFSLIDE1DOWN_VFPR32_M2_MASK = 4191 + + PseudoVFSLIDE1DOWN_VFPR32_M4 = 4192 + + PseudoVFSLIDE1DOWN_VFPR32_M4_MASK = 4193 + + PseudoVFSLIDE1DOWN_VFPR32_M8 = 4194 + + PseudoVFSLIDE1DOWN_VFPR32_M8_MASK = 4195 + + PseudoVFSLIDE1DOWN_VFPR32_MF2 = 4196 + + PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK = 4197 + + PseudoVFSLIDE1DOWN_VFPR64_M1 = 4198 + + PseudoVFSLIDE1DOWN_VFPR64_M1_MASK = 4199 + + PseudoVFSLIDE1DOWN_VFPR64_M2 = 4200 + + PseudoVFSLIDE1DOWN_VFPR64_M2_MASK = 4201 + + PseudoVFSLIDE1DOWN_VFPR64_M4 = 4202 + + PseudoVFSLIDE1DOWN_VFPR64_M4_MASK = 4203 + + PseudoVFSLIDE1DOWN_VFPR64_M8 = 4204 + + PseudoVFSLIDE1DOWN_VFPR64_M8_MASK = 4205 + + PseudoVFSLIDE1UP_ALT_VFPR16_M1 = 4206 + + PseudoVFSLIDE1UP_ALT_VFPR16_M1_MASK = 4207 + + PseudoVFSLIDE1UP_ALT_VFPR16_M2 = 4208 + + PseudoVFSLIDE1UP_ALT_VFPR16_M2_MASK = 4209 + + PseudoVFSLIDE1UP_ALT_VFPR16_M4 = 4210 + + PseudoVFSLIDE1UP_ALT_VFPR16_M4_MASK = 4211 + + PseudoVFSLIDE1UP_ALT_VFPR16_M8 = 4212 + + PseudoVFSLIDE1UP_ALT_VFPR16_M8_MASK = 4213 + + PseudoVFSLIDE1UP_ALT_VFPR16_MF2 = 4214 + + PseudoVFSLIDE1UP_ALT_VFPR16_MF2_MASK = 4215 + + PseudoVFSLIDE1UP_ALT_VFPR16_MF4 = 4216 + + PseudoVFSLIDE1UP_ALT_VFPR16_MF4_MASK = 4217 + + PseudoVFSLIDE1UP_ALT_VFPR32_M1 = 4218 + + PseudoVFSLIDE1UP_ALT_VFPR32_M1_MASK = 4219 + + PseudoVFSLIDE1UP_ALT_VFPR32_M2 = 4220 + + PseudoVFSLIDE1UP_ALT_VFPR32_M2_MASK = 4221 + + PseudoVFSLIDE1UP_ALT_VFPR32_M4 = 4222 + + PseudoVFSLIDE1UP_ALT_VFPR32_M4_MASK = 4223 + + PseudoVFSLIDE1UP_ALT_VFPR32_M8 = 4224 + + PseudoVFSLIDE1UP_ALT_VFPR32_M8_MASK = 4225 + + PseudoVFSLIDE1UP_ALT_VFPR32_MF2 = 4226 + + PseudoVFSLIDE1UP_ALT_VFPR32_MF2_MASK = 4227 + + PseudoVFSLIDE1UP_ALT_VFPR64_M1 = 4228 + + PseudoVFSLIDE1UP_ALT_VFPR64_M1_MASK = 4229 + + PseudoVFSLIDE1UP_ALT_VFPR64_M2 = 4230 + + PseudoVFSLIDE1UP_ALT_VFPR64_M2_MASK = 4231 + + PseudoVFSLIDE1UP_ALT_VFPR64_M4 = 4232 + + PseudoVFSLIDE1UP_ALT_VFPR64_M4_MASK = 4233 + + PseudoVFSLIDE1UP_ALT_VFPR64_M8 = 4234 + + PseudoVFSLIDE1UP_ALT_VFPR64_M8_MASK = 4235 + + PseudoVFSLIDE1UP_VFPR16_M1 = 4236 + + PseudoVFSLIDE1UP_VFPR16_M1_MASK = 4237 + + PseudoVFSLIDE1UP_VFPR16_M2 = 4238 + + PseudoVFSLIDE1UP_VFPR16_M2_MASK = 4239 + + PseudoVFSLIDE1UP_VFPR16_M4 = 4240 + + PseudoVFSLIDE1UP_VFPR16_M4_MASK = 4241 + + PseudoVFSLIDE1UP_VFPR16_M8 = 4242 + + PseudoVFSLIDE1UP_VFPR16_M8_MASK = 4243 + + PseudoVFSLIDE1UP_VFPR16_MF2 = 4244 + + PseudoVFSLIDE1UP_VFPR16_MF2_MASK = 4245 + + PseudoVFSLIDE1UP_VFPR16_MF4 = 4246 + + PseudoVFSLIDE1UP_VFPR16_MF4_MASK = 4247 + + PseudoVFSLIDE1UP_VFPR32_M1 = 4248 + + PseudoVFSLIDE1UP_VFPR32_M1_MASK = 4249 + + PseudoVFSLIDE1UP_VFPR32_M2 = 4250 + + PseudoVFSLIDE1UP_VFPR32_M2_MASK = 4251 + + PseudoVFSLIDE1UP_VFPR32_M4 = 4252 + + PseudoVFSLIDE1UP_VFPR32_M4_MASK = 4253 + + PseudoVFSLIDE1UP_VFPR32_M8 = 4254 + + PseudoVFSLIDE1UP_VFPR32_M8_MASK = 4255 + + PseudoVFSLIDE1UP_VFPR32_MF2 = 4256 + + PseudoVFSLIDE1UP_VFPR32_MF2_MASK = 4257 + + PseudoVFSLIDE1UP_VFPR64_M1 = 4258 + + PseudoVFSLIDE1UP_VFPR64_M1_MASK = 4259 + + PseudoVFSLIDE1UP_VFPR64_M2 = 4260 + + PseudoVFSLIDE1UP_VFPR64_M2_MASK = 4261 + + PseudoVFSLIDE1UP_VFPR64_M4 = 4262 + + PseudoVFSLIDE1UP_VFPR64_M4_MASK = 4263 + + PseudoVFSLIDE1UP_VFPR64_M8 = 4264 + + PseudoVFSLIDE1UP_VFPR64_M8_MASK = 4265 + + PseudoVFSQRT_V_M1_E16 = 4266 + + PseudoVFSQRT_V_M1_E16_MASK = 4267 + + PseudoVFSQRT_V_M1_E32 = 4268 + + PseudoVFSQRT_V_M1_E32_MASK = 4269 + + PseudoVFSQRT_V_M1_E64 = 4270 + + PseudoVFSQRT_V_M1_E64_MASK = 4271 + + PseudoVFSQRT_V_M2_E16 = 4272 + + PseudoVFSQRT_V_M2_E16_MASK = 4273 + + PseudoVFSQRT_V_M2_E32 = 4274 + + PseudoVFSQRT_V_M2_E32_MASK = 4275 + + PseudoVFSQRT_V_M2_E64 = 4276 + + PseudoVFSQRT_V_M2_E64_MASK = 4277 + + PseudoVFSQRT_V_M4_E16 = 4278 + + PseudoVFSQRT_V_M4_E16_MASK = 4279 + + PseudoVFSQRT_V_M4_E32 = 4280 + + PseudoVFSQRT_V_M4_E32_MASK = 4281 + + PseudoVFSQRT_V_M4_E64 = 4282 + + PseudoVFSQRT_V_M4_E64_MASK = 4283 + + PseudoVFSQRT_V_M8_E16 = 4284 + + PseudoVFSQRT_V_M8_E16_MASK = 4285 + + PseudoVFSQRT_V_M8_E32 = 4286 + + PseudoVFSQRT_V_M8_E32_MASK = 4287 + + PseudoVFSQRT_V_M8_E64 = 4288 + + PseudoVFSQRT_V_M8_E64_MASK = 4289 + + PseudoVFSQRT_V_MF2_E16 = 4290 + + PseudoVFSQRT_V_MF2_E16_MASK = 4291 + + PseudoVFSQRT_V_MF2_E32 = 4292 + + PseudoVFSQRT_V_MF2_E32_MASK = 4293 + + PseudoVFSQRT_V_MF4_E16 = 4294 + + PseudoVFSQRT_V_MF4_E16_MASK = 4295 + + PseudoVFSUB_ALT_VFPR16_M1_E16 = 4296 + + PseudoVFSUB_ALT_VFPR16_M1_E16_MASK = 4297 + + PseudoVFSUB_ALT_VFPR16_M2_E16 = 4298 + + PseudoVFSUB_ALT_VFPR16_M2_E16_MASK = 4299 + + PseudoVFSUB_ALT_VFPR16_M4_E16 = 4300 + + PseudoVFSUB_ALT_VFPR16_M4_E16_MASK = 4301 + + PseudoVFSUB_ALT_VFPR16_M8_E16 = 4302 + + PseudoVFSUB_ALT_VFPR16_M8_E16_MASK = 4303 + + PseudoVFSUB_ALT_VFPR16_MF2_E16 = 4304 + + PseudoVFSUB_ALT_VFPR16_MF2_E16_MASK = 4305 + + PseudoVFSUB_ALT_VFPR16_MF4_E16 = 4306 + + PseudoVFSUB_ALT_VFPR16_MF4_E16_MASK = 4307 + + PseudoVFSUB_ALT_VV_M1_E16 = 4308 + + PseudoVFSUB_ALT_VV_M1_E16_MASK = 4309 + + PseudoVFSUB_ALT_VV_M2_E16 = 4310 + + PseudoVFSUB_ALT_VV_M2_E16_MASK = 4311 + + PseudoVFSUB_ALT_VV_M4_E16 = 4312 + + PseudoVFSUB_ALT_VV_M4_E16_MASK = 4313 + + PseudoVFSUB_ALT_VV_M8_E16 = 4314 + + PseudoVFSUB_ALT_VV_M8_E16_MASK = 4315 + + PseudoVFSUB_ALT_VV_MF2_E16 = 4316 + + PseudoVFSUB_ALT_VV_MF2_E16_MASK = 4317 + + PseudoVFSUB_ALT_VV_MF4_E16 = 4318 + + PseudoVFSUB_ALT_VV_MF4_E16_MASK = 4319 + + PseudoVFSUB_VFPR16_M1_E16 = 4320 + + PseudoVFSUB_VFPR16_M1_E16_MASK = 4321 + + PseudoVFSUB_VFPR16_M2_E16 = 4322 + + PseudoVFSUB_VFPR16_M2_E16_MASK = 4323 + + PseudoVFSUB_VFPR16_M4_E16 = 4324 + + PseudoVFSUB_VFPR16_M4_E16_MASK = 4325 + + PseudoVFSUB_VFPR16_M8_E16 = 4326 + + PseudoVFSUB_VFPR16_M8_E16_MASK = 4327 + + PseudoVFSUB_VFPR16_MF2_E16 = 4328 + + PseudoVFSUB_VFPR16_MF2_E16_MASK = 4329 + + PseudoVFSUB_VFPR16_MF4_E16 = 4330 + + PseudoVFSUB_VFPR16_MF4_E16_MASK = 4331 + + PseudoVFSUB_VFPR32_M1_E32 = 4332 + + PseudoVFSUB_VFPR32_M1_E32_MASK = 4333 + + PseudoVFSUB_VFPR32_M2_E32 = 4334 + + PseudoVFSUB_VFPR32_M2_E32_MASK = 4335 + + PseudoVFSUB_VFPR32_M4_E32 = 4336 + + PseudoVFSUB_VFPR32_M4_E32_MASK = 4337 + + PseudoVFSUB_VFPR32_M8_E32 = 4338 + + PseudoVFSUB_VFPR32_M8_E32_MASK = 4339 + + PseudoVFSUB_VFPR32_MF2_E32 = 4340 + + PseudoVFSUB_VFPR32_MF2_E32_MASK = 4341 + + PseudoVFSUB_VFPR64_M1_E64 = 4342 + + PseudoVFSUB_VFPR64_M1_E64_MASK = 4343 + + PseudoVFSUB_VFPR64_M2_E64 = 4344 + + PseudoVFSUB_VFPR64_M2_E64_MASK = 4345 + + PseudoVFSUB_VFPR64_M4_E64 = 4346 + + PseudoVFSUB_VFPR64_M4_E64_MASK = 4347 + + PseudoVFSUB_VFPR64_M8_E64 = 4348 + + PseudoVFSUB_VFPR64_M8_E64_MASK = 4349 + + PseudoVFSUB_VV_M1_E16 = 4350 + + PseudoVFSUB_VV_M1_E16_MASK = 4351 + + PseudoVFSUB_VV_M1_E32 = 4352 + + PseudoVFSUB_VV_M1_E32_MASK = 4353 + + PseudoVFSUB_VV_M1_E64 = 4354 + + PseudoVFSUB_VV_M1_E64_MASK = 4355 + + PseudoVFSUB_VV_M2_E16 = 4356 + + PseudoVFSUB_VV_M2_E16_MASK = 4357 + + PseudoVFSUB_VV_M2_E32 = 4358 + + PseudoVFSUB_VV_M2_E32_MASK = 4359 + + PseudoVFSUB_VV_M2_E64 = 4360 + + PseudoVFSUB_VV_M2_E64_MASK = 4361 + + PseudoVFSUB_VV_M4_E16 = 4362 + + PseudoVFSUB_VV_M4_E16_MASK = 4363 + + PseudoVFSUB_VV_M4_E32 = 4364 + + PseudoVFSUB_VV_M4_E32_MASK = 4365 + + PseudoVFSUB_VV_M4_E64 = 4366 + + PseudoVFSUB_VV_M4_E64_MASK = 4367 + + PseudoVFSUB_VV_M8_E16 = 4368 + + PseudoVFSUB_VV_M8_E16_MASK = 4369 + + PseudoVFSUB_VV_M8_E32 = 4370 + + PseudoVFSUB_VV_M8_E32_MASK = 4371 + + PseudoVFSUB_VV_M8_E64 = 4372 + + PseudoVFSUB_VV_M8_E64_MASK = 4373 + + PseudoVFSUB_VV_MF2_E16 = 4374 + + PseudoVFSUB_VV_MF2_E16_MASK = 4375 + + PseudoVFSUB_VV_MF2_E32 = 4376 + + PseudoVFSUB_VV_MF2_E32_MASK = 4377 + + PseudoVFSUB_VV_MF4_E16 = 4378 + + PseudoVFSUB_VV_MF4_E16_MASK = 4379 + + PseudoVFWADD_ALT_VFPR16_M1_E16 = 4380 + + PseudoVFWADD_ALT_VFPR16_M1_E16_MASK = 4381 + + PseudoVFWADD_ALT_VFPR16_M2_E16 = 4382 + + PseudoVFWADD_ALT_VFPR16_M2_E16_MASK = 4383 + + PseudoVFWADD_ALT_VFPR16_M4_E16 = 4384 + + PseudoVFWADD_ALT_VFPR16_M4_E16_MASK = 4385 + + PseudoVFWADD_ALT_VFPR16_MF2_E16 = 4386 + + PseudoVFWADD_ALT_VFPR16_MF2_E16_MASK = 4387 + + PseudoVFWADD_ALT_VFPR16_MF4_E16 = 4388 + + PseudoVFWADD_ALT_VFPR16_MF4_E16_MASK = 4389 + + PseudoVFWADD_ALT_VV_M1_E16 = 4390 + + PseudoVFWADD_ALT_VV_M1_E16_MASK = 4391 + + PseudoVFWADD_ALT_VV_M2_E16 = 4392 + + PseudoVFWADD_ALT_VV_M2_E16_MASK = 4393 + + PseudoVFWADD_ALT_VV_M4_E16 = 4394 + + PseudoVFWADD_ALT_VV_M4_E16_MASK = 4395 + + PseudoVFWADD_ALT_VV_MF2_E16 = 4396 + + PseudoVFWADD_ALT_VV_MF2_E16_MASK = 4397 + + PseudoVFWADD_ALT_VV_MF4_E16 = 4398 + + PseudoVFWADD_ALT_VV_MF4_E16_MASK = 4399 + + PseudoVFWADD_ALT_WFPR16_M1_E16 = 4400 + + PseudoVFWADD_ALT_WFPR16_M1_E16_MASK = 4401 + + PseudoVFWADD_ALT_WFPR16_M2_E16 = 4402 + + PseudoVFWADD_ALT_WFPR16_M2_E16_MASK = 4403 + + PseudoVFWADD_ALT_WFPR16_M4_E16 = 4404 + + PseudoVFWADD_ALT_WFPR16_M4_E16_MASK = 4405 + + PseudoVFWADD_ALT_WFPR16_MF2_E16 = 4406 + + PseudoVFWADD_ALT_WFPR16_MF2_E16_MASK = 4407 + + PseudoVFWADD_ALT_WFPR16_MF4_E16 = 4408 + + PseudoVFWADD_ALT_WFPR16_MF4_E16_MASK = 4409 + + PseudoVFWADD_ALT_WV_M1_E16 = 4410 + + PseudoVFWADD_ALT_WV_M1_E16_MASK = 4411 + + PseudoVFWADD_ALT_WV_M1_E16_MASK_TIED = 4412 + + PseudoVFWADD_ALT_WV_M1_E16_TIED = 4413 + + PseudoVFWADD_ALT_WV_M2_E16 = 4414 + + PseudoVFWADD_ALT_WV_M2_E16_MASK = 4415 + + PseudoVFWADD_ALT_WV_M2_E16_MASK_TIED = 4416 + + PseudoVFWADD_ALT_WV_M2_E16_TIED = 4417 + + PseudoVFWADD_ALT_WV_M4_E16 = 4418 + + PseudoVFWADD_ALT_WV_M4_E16_MASK = 4419 + + PseudoVFWADD_ALT_WV_M4_E16_MASK_TIED = 4420 + + PseudoVFWADD_ALT_WV_M4_E16_TIED = 4421 + + PseudoVFWADD_ALT_WV_MF2_E16 = 4422 + + PseudoVFWADD_ALT_WV_MF2_E16_MASK = 4423 + + PseudoVFWADD_ALT_WV_MF2_E16_MASK_TIED = 4424 + + PseudoVFWADD_ALT_WV_MF2_E16_TIED = 4425 + + PseudoVFWADD_ALT_WV_MF4_E16 = 4426 + + PseudoVFWADD_ALT_WV_MF4_E16_MASK = 4427 + + PseudoVFWADD_ALT_WV_MF4_E16_MASK_TIED = 4428 + + PseudoVFWADD_ALT_WV_MF4_E16_TIED = 4429 + + PseudoVFWADD_VFPR16_M1_E16 = 4430 + + PseudoVFWADD_VFPR16_M1_E16_MASK = 4431 + + PseudoVFWADD_VFPR16_M2_E16 = 4432 + + PseudoVFWADD_VFPR16_M2_E16_MASK = 4433 + + PseudoVFWADD_VFPR16_M4_E16 = 4434 + + PseudoVFWADD_VFPR16_M4_E16_MASK = 4435 + + PseudoVFWADD_VFPR16_MF2_E16 = 4436 + + PseudoVFWADD_VFPR16_MF2_E16_MASK = 4437 + + PseudoVFWADD_VFPR16_MF4_E16 = 4438 + + PseudoVFWADD_VFPR16_MF4_E16_MASK = 4439 + + PseudoVFWADD_VFPR32_M1_E32 = 4440 + + PseudoVFWADD_VFPR32_M1_E32_MASK = 4441 + + PseudoVFWADD_VFPR32_M2_E32 = 4442 + + PseudoVFWADD_VFPR32_M2_E32_MASK = 4443 + + PseudoVFWADD_VFPR32_M4_E32 = 4444 + + PseudoVFWADD_VFPR32_M4_E32_MASK = 4445 + + PseudoVFWADD_VFPR32_MF2_E32 = 4446 + + PseudoVFWADD_VFPR32_MF2_E32_MASK = 4447 + + PseudoVFWADD_VV_M1_E16 = 4448 + + PseudoVFWADD_VV_M1_E16_MASK = 4449 + + PseudoVFWADD_VV_M1_E32 = 4450 + + PseudoVFWADD_VV_M1_E32_MASK = 4451 + + PseudoVFWADD_VV_M2_E16 = 4452 + + PseudoVFWADD_VV_M2_E16_MASK = 4453 + + PseudoVFWADD_VV_M2_E32 = 4454 + + PseudoVFWADD_VV_M2_E32_MASK = 4455 + + PseudoVFWADD_VV_M4_E16 = 4456 + + PseudoVFWADD_VV_M4_E16_MASK = 4457 + + PseudoVFWADD_VV_M4_E32 = 4458 + + PseudoVFWADD_VV_M4_E32_MASK = 4459 + + PseudoVFWADD_VV_MF2_E16 = 4460 + + PseudoVFWADD_VV_MF2_E16_MASK = 4461 + + PseudoVFWADD_VV_MF2_E32 = 4462 + + PseudoVFWADD_VV_MF2_E32_MASK = 4463 + + PseudoVFWADD_VV_MF4_E16 = 4464 + + PseudoVFWADD_VV_MF4_E16_MASK = 4465 + + PseudoVFWADD_WFPR16_M1_E16 = 4466 + + PseudoVFWADD_WFPR16_M1_E16_MASK = 4467 + + PseudoVFWADD_WFPR16_M2_E16 = 4468 + + PseudoVFWADD_WFPR16_M2_E16_MASK = 4469 + + PseudoVFWADD_WFPR16_M4_E16 = 4470 + + PseudoVFWADD_WFPR16_M4_E16_MASK = 4471 + + PseudoVFWADD_WFPR16_MF2_E16 = 4472 + + PseudoVFWADD_WFPR16_MF2_E16_MASK = 4473 + + PseudoVFWADD_WFPR16_MF4_E16 = 4474 + + PseudoVFWADD_WFPR16_MF4_E16_MASK = 4475 + + PseudoVFWADD_WFPR32_M1_E32 = 4476 + + PseudoVFWADD_WFPR32_M1_E32_MASK = 4477 + + PseudoVFWADD_WFPR32_M2_E32 = 4478 + + PseudoVFWADD_WFPR32_M2_E32_MASK = 4479 + + PseudoVFWADD_WFPR32_M4_E32 = 4480 + + PseudoVFWADD_WFPR32_M4_E32_MASK = 4481 + + PseudoVFWADD_WFPR32_MF2_E32 = 4482 + + PseudoVFWADD_WFPR32_MF2_E32_MASK = 4483 + + PseudoVFWADD_WV_M1_E16 = 4484 + + PseudoVFWADD_WV_M1_E16_MASK = 4485 + + PseudoVFWADD_WV_M1_E16_MASK_TIED = 4486 + + PseudoVFWADD_WV_M1_E16_TIED = 4487 + + PseudoVFWADD_WV_M1_E32 = 4488 + + PseudoVFWADD_WV_M1_E32_MASK = 4489 + + PseudoVFWADD_WV_M1_E32_MASK_TIED = 4490 + + PseudoVFWADD_WV_M1_E32_TIED = 4491 + + PseudoVFWADD_WV_M2_E16 = 4492 + + PseudoVFWADD_WV_M2_E16_MASK = 4493 + + PseudoVFWADD_WV_M2_E16_MASK_TIED = 4494 + + PseudoVFWADD_WV_M2_E16_TIED = 4495 + + PseudoVFWADD_WV_M2_E32 = 4496 + + PseudoVFWADD_WV_M2_E32_MASK = 4497 + + PseudoVFWADD_WV_M2_E32_MASK_TIED = 4498 + + PseudoVFWADD_WV_M2_E32_TIED = 4499 + + PseudoVFWADD_WV_M4_E16 = 4500 + + PseudoVFWADD_WV_M4_E16_MASK = 4501 + + PseudoVFWADD_WV_M4_E16_MASK_TIED = 4502 + + PseudoVFWADD_WV_M4_E16_TIED = 4503 + + PseudoVFWADD_WV_M4_E32 = 4504 + + PseudoVFWADD_WV_M4_E32_MASK = 4505 + + PseudoVFWADD_WV_M4_E32_MASK_TIED = 4506 + + PseudoVFWADD_WV_M4_E32_TIED = 4507 + + PseudoVFWADD_WV_MF2_E16 = 4508 + + PseudoVFWADD_WV_MF2_E16_MASK = 4509 + + PseudoVFWADD_WV_MF2_E16_MASK_TIED = 4510 + + PseudoVFWADD_WV_MF2_E16_TIED = 4511 + + PseudoVFWADD_WV_MF2_E32 = 4512 + + PseudoVFWADD_WV_MF2_E32_MASK = 4513 + + PseudoVFWADD_WV_MF2_E32_MASK_TIED = 4514 + + PseudoVFWADD_WV_MF2_E32_TIED = 4515 + + PseudoVFWADD_WV_MF4_E16 = 4516 + + PseudoVFWADD_WV_MF4_E16_MASK = 4517 + + PseudoVFWADD_WV_MF4_E16_MASK_TIED = 4518 + + PseudoVFWADD_WV_MF4_E16_TIED = 4519 + + PseudoVFWCVTBF16_F_F_ALT_V_M1_E8 = 4520 + + PseudoVFWCVTBF16_F_F_ALT_V_M1_E8_MASK = 4521 + + PseudoVFWCVTBF16_F_F_ALT_V_M2_E8 = 4522 + + PseudoVFWCVTBF16_F_F_ALT_V_M2_E8_MASK = 4523 + + PseudoVFWCVTBF16_F_F_ALT_V_M4_E8 = 4524 + + PseudoVFWCVTBF16_F_F_ALT_V_M4_E8_MASK = 4525 + + PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8 = 4526 + + PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8_MASK = 4527 + + PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8 = 4528 + + PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8_MASK = 4529 + + PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8 = 4530 + + PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8_MASK = 4531 + + PseudoVFWCVTBF16_F_F_V_M1_E16 = 4532 + + PseudoVFWCVTBF16_F_F_V_M1_E16_MASK = 4533 + + PseudoVFWCVTBF16_F_F_V_M1_E32 = 4534 + + PseudoVFWCVTBF16_F_F_V_M1_E32_MASK = 4535 + + PseudoVFWCVTBF16_F_F_V_M1_E8 = 4536 + + PseudoVFWCVTBF16_F_F_V_M1_E8_MASK = 4537 + + PseudoVFWCVTBF16_F_F_V_M2_E16 = 4538 + + PseudoVFWCVTBF16_F_F_V_M2_E16_MASK = 4539 + + PseudoVFWCVTBF16_F_F_V_M2_E32 = 4540 + + PseudoVFWCVTBF16_F_F_V_M2_E32_MASK = 4541 + + PseudoVFWCVTBF16_F_F_V_M2_E8 = 4542 + + PseudoVFWCVTBF16_F_F_V_M2_E8_MASK = 4543 + + PseudoVFWCVTBF16_F_F_V_M4_E16 = 4544 + + PseudoVFWCVTBF16_F_F_V_M4_E16_MASK = 4545 + + PseudoVFWCVTBF16_F_F_V_M4_E32 = 4546 + + PseudoVFWCVTBF16_F_F_V_M4_E32_MASK = 4547 + + PseudoVFWCVTBF16_F_F_V_M4_E8 = 4548 + + PseudoVFWCVTBF16_F_F_V_M4_E8_MASK = 4549 + + PseudoVFWCVTBF16_F_F_V_MF2_E16 = 4550 + + PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK = 4551 + + PseudoVFWCVTBF16_F_F_V_MF2_E32 = 4552 + + PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK = 4553 + + PseudoVFWCVTBF16_F_F_V_MF2_E8 = 4554 + + PseudoVFWCVTBF16_F_F_V_MF2_E8_MASK = 4555 + + PseudoVFWCVTBF16_F_F_V_MF4_E16 = 4556 + + PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK = 4557 + + PseudoVFWCVTBF16_F_F_V_MF4_E8 = 4558 + + PseudoVFWCVTBF16_F_F_V_MF4_E8_MASK = 4559 + + PseudoVFWCVTBF16_F_F_V_MF8_E8 = 4560 + + PseudoVFWCVTBF16_F_F_V_MF8_E8_MASK = 4561 + + PseudoVFWCVT_F_F_ALT_V_M1_E16 = 4562 + + PseudoVFWCVT_F_F_ALT_V_M1_E16_MASK = 4563 + + PseudoVFWCVT_F_F_ALT_V_M2_E16 = 4564 + + PseudoVFWCVT_F_F_ALT_V_M2_E16_MASK = 4565 + + PseudoVFWCVT_F_F_ALT_V_M4_E16 = 4566 + + PseudoVFWCVT_F_F_ALT_V_M4_E16_MASK = 4567 + + PseudoVFWCVT_F_F_ALT_V_MF2_E16 = 4568 + + PseudoVFWCVT_F_F_ALT_V_MF2_E16_MASK = 4569 + + PseudoVFWCVT_F_F_ALT_V_MF4_E16 = 4570 + + PseudoVFWCVT_F_F_ALT_V_MF4_E16_MASK = 4571 + + PseudoVFWCVT_F_F_V_M1_E16 = 4572 + + PseudoVFWCVT_F_F_V_M1_E16_MASK = 4573 + + PseudoVFWCVT_F_F_V_M1_E32 = 4574 + + PseudoVFWCVT_F_F_V_M1_E32_MASK = 4575 + + PseudoVFWCVT_F_F_V_M2_E16 = 4576 + + PseudoVFWCVT_F_F_V_M2_E16_MASK = 4577 + + PseudoVFWCVT_F_F_V_M2_E32 = 4578 + + PseudoVFWCVT_F_F_V_M2_E32_MASK = 4579 + + PseudoVFWCVT_F_F_V_M4_E16 = 4580 + + PseudoVFWCVT_F_F_V_M4_E16_MASK = 4581 + + PseudoVFWCVT_F_F_V_M4_E32 = 4582 + + PseudoVFWCVT_F_F_V_M4_E32_MASK = 4583 + + PseudoVFWCVT_F_F_V_MF2_E16 = 4584 + + PseudoVFWCVT_F_F_V_MF2_E16_MASK = 4585 + + PseudoVFWCVT_F_F_V_MF2_E32 = 4586 + + PseudoVFWCVT_F_F_V_MF2_E32_MASK = 4587 + + PseudoVFWCVT_F_F_V_MF4_E16 = 4588 + + PseudoVFWCVT_F_F_V_MF4_E16_MASK = 4589 + + PseudoVFWCVT_F_XU_ALT_V_M1_E8 = 4590 + + PseudoVFWCVT_F_XU_ALT_V_M1_E8_MASK = 4591 + + PseudoVFWCVT_F_XU_ALT_V_M2_E8 = 4592 + + PseudoVFWCVT_F_XU_ALT_V_M2_E8_MASK = 4593 + + PseudoVFWCVT_F_XU_ALT_V_M4_E8 = 4594 + + PseudoVFWCVT_F_XU_ALT_V_M4_E8_MASK = 4595 + + PseudoVFWCVT_F_XU_ALT_V_MF2_E8 = 4596 + + PseudoVFWCVT_F_XU_ALT_V_MF2_E8_MASK = 4597 + + PseudoVFWCVT_F_XU_ALT_V_MF4_E8 = 4598 + + PseudoVFWCVT_F_XU_ALT_V_MF4_E8_MASK = 4599 + + PseudoVFWCVT_F_XU_ALT_V_MF8_E8 = 4600 + + PseudoVFWCVT_F_XU_ALT_V_MF8_E8_MASK = 4601 + + PseudoVFWCVT_F_XU_V_M1_E16 = 4602 + + PseudoVFWCVT_F_XU_V_M1_E16_MASK = 4603 + + PseudoVFWCVT_F_XU_V_M1_E32 = 4604 + + PseudoVFWCVT_F_XU_V_M1_E32_MASK = 4605 + + PseudoVFWCVT_F_XU_V_M1_E8 = 4606 + + PseudoVFWCVT_F_XU_V_M1_E8_MASK = 4607 + + PseudoVFWCVT_F_XU_V_M2_E16 = 4608 + + PseudoVFWCVT_F_XU_V_M2_E16_MASK = 4609 + + PseudoVFWCVT_F_XU_V_M2_E32 = 4610 + + PseudoVFWCVT_F_XU_V_M2_E32_MASK = 4611 + + PseudoVFWCVT_F_XU_V_M2_E8 = 4612 + + PseudoVFWCVT_F_XU_V_M2_E8_MASK = 4613 + + PseudoVFWCVT_F_XU_V_M4_E16 = 4614 + + PseudoVFWCVT_F_XU_V_M4_E16_MASK = 4615 + + PseudoVFWCVT_F_XU_V_M4_E32 = 4616 + + PseudoVFWCVT_F_XU_V_M4_E32_MASK = 4617 + + PseudoVFWCVT_F_XU_V_M4_E8 = 4618 + + PseudoVFWCVT_F_XU_V_M4_E8_MASK = 4619 + + PseudoVFWCVT_F_XU_V_MF2_E16 = 4620 + + PseudoVFWCVT_F_XU_V_MF2_E16_MASK = 4621 + + PseudoVFWCVT_F_XU_V_MF2_E32 = 4622 + + PseudoVFWCVT_F_XU_V_MF2_E32_MASK = 4623 + + PseudoVFWCVT_F_XU_V_MF2_E8 = 4624 + + PseudoVFWCVT_F_XU_V_MF2_E8_MASK = 4625 + + PseudoVFWCVT_F_XU_V_MF4_E16 = 4626 + + PseudoVFWCVT_F_XU_V_MF4_E16_MASK = 4627 + + PseudoVFWCVT_F_XU_V_MF4_E8 = 4628 + + PseudoVFWCVT_F_XU_V_MF4_E8_MASK = 4629 + + PseudoVFWCVT_F_XU_V_MF8_E8 = 4630 + + PseudoVFWCVT_F_XU_V_MF8_E8_MASK = 4631 + + PseudoVFWCVT_F_X_ALT_V_M1_E8 = 4632 + + PseudoVFWCVT_F_X_ALT_V_M1_E8_MASK = 4633 + + PseudoVFWCVT_F_X_ALT_V_M2_E8 = 4634 + + PseudoVFWCVT_F_X_ALT_V_M2_E8_MASK = 4635 + + PseudoVFWCVT_F_X_ALT_V_M4_E8 = 4636 + + PseudoVFWCVT_F_X_ALT_V_M4_E8_MASK = 4637 + + PseudoVFWCVT_F_X_ALT_V_MF2_E8 = 4638 + + PseudoVFWCVT_F_X_ALT_V_MF2_E8_MASK = 4639 + + PseudoVFWCVT_F_X_ALT_V_MF4_E8 = 4640 + + PseudoVFWCVT_F_X_ALT_V_MF4_E8_MASK = 4641 + + PseudoVFWCVT_F_X_ALT_V_MF8_E8 = 4642 + + PseudoVFWCVT_F_X_ALT_V_MF8_E8_MASK = 4643 + + PseudoVFWCVT_F_X_V_M1_E16 = 4644 + + PseudoVFWCVT_F_X_V_M1_E16_MASK = 4645 + + PseudoVFWCVT_F_X_V_M1_E32 = 4646 + + PseudoVFWCVT_F_X_V_M1_E32_MASK = 4647 + + PseudoVFWCVT_F_X_V_M1_E8 = 4648 + + PseudoVFWCVT_F_X_V_M1_E8_MASK = 4649 + + PseudoVFWCVT_F_X_V_M2_E16 = 4650 + + PseudoVFWCVT_F_X_V_M2_E16_MASK = 4651 + + PseudoVFWCVT_F_X_V_M2_E32 = 4652 + + PseudoVFWCVT_F_X_V_M2_E32_MASK = 4653 + + PseudoVFWCVT_F_X_V_M2_E8 = 4654 + + PseudoVFWCVT_F_X_V_M2_E8_MASK = 4655 + + PseudoVFWCVT_F_X_V_M4_E16 = 4656 + + PseudoVFWCVT_F_X_V_M4_E16_MASK = 4657 + + PseudoVFWCVT_F_X_V_M4_E32 = 4658 + + PseudoVFWCVT_F_X_V_M4_E32_MASK = 4659 + + PseudoVFWCVT_F_X_V_M4_E8 = 4660 + + PseudoVFWCVT_F_X_V_M4_E8_MASK = 4661 + + PseudoVFWCVT_F_X_V_MF2_E16 = 4662 + + PseudoVFWCVT_F_X_V_MF2_E16_MASK = 4663 + + PseudoVFWCVT_F_X_V_MF2_E32 = 4664 + + PseudoVFWCVT_F_X_V_MF2_E32_MASK = 4665 + + PseudoVFWCVT_F_X_V_MF2_E8 = 4666 + + PseudoVFWCVT_F_X_V_MF2_E8_MASK = 4667 + + PseudoVFWCVT_F_X_V_MF4_E16 = 4668 + + PseudoVFWCVT_F_X_V_MF4_E16_MASK = 4669 + + PseudoVFWCVT_F_X_V_MF4_E8 = 4670 + + PseudoVFWCVT_F_X_V_MF4_E8_MASK = 4671 + + PseudoVFWCVT_F_X_V_MF8_E8 = 4672 + + PseudoVFWCVT_F_X_V_MF8_E8_MASK = 4673 + + PseudoVFWCVT_RTZ_XU_F_V_M1 = 4674 + + PseudoVFWCVT_RTZ_XU_F_V_M1_MASK = 4675 + + PseudoVFWCVT_RTZ_XU_F_V_M2 = 4676 + + PseudoVFWCVT_RTZ_XU_F_V_M2_MASK = 4677 + + PseudoVFWCVT_RTZ_XU_F_V_M4 = 4678 + + PseudoVFWCVT_RTZ_XU_F_V_M4_MASK = 4679 + + PseudoVFWCVT_RTZ_XU_F_V_MF2 = 4680 + + PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK = 4681 + + PseudoVFWCVT_RTZ_XU_F_V_MF4 = 4682 + + PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK = 4683 + + PseudoVFWCVT_RTZ_X_F_V_M1 = 4684 + + PseudoVFWCVT_RTZ_X_F_V_M1_MASK = 4685 + + PseudoVFWCVT_RTZ_X_F_V_M2 = 4686 + + PseudoVFWCVT_RTZ_X_F_V_M2_MASK = 4687 + + PseudoVFWCVT_RTZ_X_F_V_M4 = 4688 + + PseudoVFWCVT_RTZ_X_F_V_M4_MASK = 4689 + + PseudoVFWCVT_RTZ_X_F_V_MF2 = 4690 + + PseudoVFWCVT_RTZ_X_F_V_MF2_MASK = 4691 + + PseudoVFWCVT_RTZ_X_F_V_MF4 = 4692 + + PseudoVFWCVT_RTZ_X_F_V_MF4_MASK = 4693 + + PseudoVFWCVT_XU_F_V_M1 = 4694 + + PseudoVFWCVT_XU_F_V_M1_MASK = 4695 + + PseudoVFWCVT_XU_F_V_M2 = 4696 + + PseudoVFWCVT_XU_F_V_M2_MASK = 4697 + + PseudoVFWCVT_XU_F_V_M4 = 4698 + + PseudoVFWCVT_XU_F_V_M4_MASK = 4699 + + PseudoVFWCVT_XU_F_V_MF2 = 4700 + + PseudoVFWCVT_XU_F_V_MF2_MASK = 4701 + + PseudoVFWCVT_XU_F_V_MF4 = 4702 + + PseudoVFWCVT_XU_F_V_MF4_MASK = 4703 + + PseudoVFWCVT_X_F_V_M1 = 4704 + + PseudoVFWCVT_X_F_V_M1_MASK = 4705 + + PseudoVFWCVT_X_F_V_M2 = 4706 + + PseudoVFWCVT_X_F_V_M2_MASK = 4707 + + PseudoVFWCVT_X_F_V_M4 = 4708 + + PseudoVFWCVT_X_F_V_M4_MASK = 4709 + + PseudoVFWCVT_X_F_V_MF2 = 4710 + + PseudoVFWCVT_X_F_V_MF2_MASK = 4711 + + PseudoVFWCVT_X_F_V_MF4 = 4712 + + PseudoVFWCVT_X_F_V_MF4_MASK = 4713 + + PseudoVFWMACCBF16_VFPR16_M1_E16 = 4714 + + PseudoVFWMACCBF16_VFPR16_M1_E16_MASK = 4715 + + PseudoVFWMACCBF16_VFPR16_M2_E16 = 4716 + + PseudoVFWMACCBF16_VFPR16_M2_E16_MASK = 4717 + + PseudoVFWMACCBF16_VFPR16_M4_E16 = 4718 + + PseudoVFWMACCBF16_VFPR16_M4_E16_MASK = 4719 + + PseudoVFWMACCBF16_VFPR16_MF2_E16 = 4720 + + PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK = 4721 + + PseudoVFWMACCBF16_VFPR16_MF4_E16 = 4722 + + PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK = 4723 + + PseudoVFWMACCBF16_VV_M1_E16 = 4724 + + PseudoVFWMACCBF16_VV_M1_E16_MASK = 4725 + + PseudoVFWMACCBF16_VV_M1_E32 = 4726 + + PseudoVFWMACCBF16_VV_M1_E32_MASK = 4727 + + PseudoVFWMACCBF16_VV_M2_E16 = 4728 + + PseudoVFWMACCBF16_VV_M2_E16_MASK = 4729 + + PseudoVFWMACCBF16_VV_M2_E32 = 4730 + + PseudoVFWMACCBF16_VV_M2_E32_MASK = 4731 + + PseudoVFWMACCBF16_VV_M4_E16 = 4732 + + PseudoVFWMACCBF16_VV_M4_E16_MASK = 4733 + + PseudoVFWMACCBF16_VV_M4_E32 = 4734 + + PseudoVFWMACCBF16_VV_M4_E32_MASK = 4735 + + PseudoVFWMACCBF16_VV_MF2_E16 = 4736 + + PseudoVFWMACCBF16_VV_MF2_E16_MASK = 4737 + + PseudoVFWMACCBF16_VV_MF2_E32 = 4738 + + PseudoVFWMACCBF16_VV_MF2_E32_MASK = 4739 + + PseudoVFWMACCBF16_VV_MF4_E16 = 4740 + + PseudoVFWMACCBF16_VV_MF4_E16_MASK = 4741 + + PseudoVFWMACC_ALT_VFPR16_M1_E16 = 4742 + + PseudoVFWMACC_ALT_VFPR16_M1_E16_MASK = 4743 + + PseudoVFWMACC_ALT_VFPR16_M2_E16 = 4744 + + PseudoVFWMACC_ALT_VFPR16_M2_E16_MASK = 4745 + + PseudoVFWMACC_ALT_VFPR16_M4_E16 = 4746 + + PseudoVFWMACC_ALT_VFPR16_M4_E16_MASK = 4747 + + PseudoVFWMACC_ALT_VFPR16_MF2_E16 = 4748 + + PseudoVFWMACC_ALT_VFPR16_MF2_E16_MASK = 4749 + + PseudoVFWMACC_ALT_VFPR16_MF4_E16 = 4750 + + PseudoVFWMACC_ALT_VFPR16_MF4_E16_MASK = 4751 + + PseudoVFWMACC_ALT_VV_M1_E16 = 4752 + + PseudoVFWMACC_ALT_VV_M1_E16_MASK = 4753 + + PseudoVFWMACC_ALT_VV_M2_E16 = 4754 + + PseudoVFWMACC_ALT_VV_M2_E16_MASK = 4755 + + PseudoVFWMACC_ALT_VV_M4_E16 = 4756 + + PseudoVFWMACC_ALT_VV_M4_E16_MASK = 4757 + + PseudoVFWMACC_ALT_VV_MF2_E16 = 4758 + + PseudoVFWMACC_ALT_VV_MF2_E16_MASK = 4759 + + PseudoVFWMACC_ALT_VV_MF4_E16 = 4760 + + PseudoVFWMACC_ALT_VV_MF4_E16_MASK = 4761 + + PseudoVFWMACC_VFPR16_M1_E16 = 4762 + + PseudoVFWMACC_VFPR16_M1_E16_MASK = 4763 + + PseudoVFWMACC_VFPR16_M2_E16 = 4764 + + PseudoVFWMACC_VFPR16_M2_E16_MASK = 4765 + + PseudoVFWMACC_VFPR16_M4_E16 = 4766 + + PseudoVFWMACC_VFPR16_M4_E16_MASK = 4767 + + PseudoVFWMACC_VFPR16_MF2_E16 = 4768 + + PseudoVFWMACC_VFPR16_MF2_E16_MASK = 4769 + + PseudoVFWMACC_VFPR16_MF4_E16 = 4770 + + PseudoVFWMACC_VFPR16_MF4_E16_MASK = 4771 + + PseudoVFWMACC_VFPR32_M1_E32 = 4772 + + PseudoVFWMACC_VFPR32_M1_E32_MASK = 4773 + + PseudoVFWMACC_VFPR32_M2_E32 = 4774 + + PseudoVFWMACC_VFPR32_M2_E32_MASK = 4775 + + PseudoVFWMACC_VFPR32_M4_E32 = 4776 + + PseudoVFWMACC_VFPR32_M4_E32_MASK = 4777 + + PseudoVFWMACC_VFPR32_MF2_E32 = 4778 + + PseudoVFWMACC_VFPR32_MF2_E32_MASK = 4779 + + PseudoVFWMACC_VV_M1_E16 = 4780 + + PseudoVFWMACC_VV_M1_E16_MASK = 4781 + + PseudoVFWMACC_VV_M1_E32 = 4782 + + PseudoVFWMACC_VV_M1_E32_MASK = 4783 + + PseudoVFWMACC_VV_M2_E16 = 4784 + + PseudoVFWMACC_VV_M2_E16_MASK = 4785 + + PseudoVFWMACC_VV_M2_E32 = 4786 + + PseudoVFWMACC_VV_M2_E32_MASK = 4787 + + PseudoVFWMACC_VV_M4_E16 = 4788 + + PseudoVFWMACC_VV_M4_E16_MASK = 4789 + + PseudoVFWMACC_VV_M4_E32 = 4790 + + PseudoVFWMACC_VV_M4_E32_MASK = 4791 + + PseudoVFWMACC_VV_MF2_E16 = 4792 + + PseudoVFWMACC_VV_MF2_E16_MASK = 4793 + + PseudoVFWMACC_VV_MF2_E32 = 4794 + + PseudoVFWMACC_VV_MF2_E32_MASK = 4795 + + PseudoVFWMACC_VV_MF4_E16 = 4796 + + PseudoVFWMACC_VV_MF4_E16_MASK = 4797 + + PseudoVFWMSAC_ALT_VFPR16_M1_E16 = 4798 + + PseudoVFWMSAC_ALT_VFPR16_M1_E16_MASK = 4799 + + PseudoVFWMSAC_ALT_VFPR16_M2_E16 = 4800 + + PseudoVFWMSAC_ALT_VFPR16_M2_E16_MASK = 4801 + + PseudoVFWMSAC_ALT_VFPR16_M4_E16 = 4802 + + PseudoVFWMSAC_ALT_VFPR16_M4_E16_MASK = 4803 + + PseudoVFWMSAC_ALT_VFPR16_MF2_E16 = 4804 + + PseudoVFWMSAC_ALT_VFPR16_MF2_E16_MASK = 4805 + + PseudoVFWMSAC_ALT_VFPR16_MF4_E16 = 4806 + + PseudoVFWMSAC_ALT_VFPR16_MF4_E16_MASK = 4807 + + PseudoVFWMSAC_ALT_VV_M1_E16 = 4808 + + PseudoVFWMSAC_ALT_VV_M1_E16_MASK = 4809 + + PseudoVFWMSAC_ALT_VV_M2_E16 = 4810 + + PseudoVFWMSAC_ALT_VV_M2_E16_MASK = 4811 + + PseudoVFWMSAC_ALT_VV_M4_E16 = 4812 + + PseudoVFWMSAC_ALT_VV_M4_E16_MASK = 4813 + + PseudoVFWMSAC_ALT_VV_MF2_E16 = 4814 + + PseudoVFWMSAC_ALT_VV_MF2_E16_MASK = 4815 + + PseudoVFWMSAC_ALT_VV_MF4_E16 = 4816 + + PseudoVFWMSAC_ALT_VV_MF4_E16_MASK = 4817 + + PseudoVFWMSAC_VFPR16_M1_E16 = 4818 + + PseudoVFWMSAC_VFPR16_M1_E16_MASK = 4819 + + PseudoVFWMSAC_VFPR16_M2_E16 = 4820 + + PseudoVFWMSAC_VFPR16_M2_E16_MASK = 4821 + + PseudoVFWMSAC_VFPR16_M4_E16 = 4822 + + PseudoVFWMSAC_VFPR16_M4_E16_MASK = 4823 + + PseudoVFWMSAC_VFPR16_MF2_E16 = 4824 + + PseudoVFWMSAC_VFPR16_MF2_E16_MASK = 4825 + + PseudoVFWMSAC_VFPR16_MF4_E16 = 4826 + + PseudoVFWMSAC_VFPR16_MF4_E16_MASK = 4827 + + PseudoVFWMSAC_VFPR32_M1_E32 = 4828 + + PseudoVFWMSAC_VFPR32_M1_E32_MASK = 4829 + + PseudoVFWMSAC_VFPR32_M2_E32 = 4830 + + PseudoVFWMSAC_VFPR32_M2_E32_MASK = 4831 + + PseudoVFWMSAC_VFPR32_M4_E32 = 4832 + + PseudoVFWMSAC_VFPR32_M4_E32_MASK = 4833 + + PseudoVFWMSAC_VFPR32_MF2_E32 = 4834 + + PseudoVFWMSAC_VFPR32_MF2_E32_MASK = 4835 + + PseudoVFWMSAC_VV_M1_E16 = 4836 + + PseudoVFWMSAC_VV_M1_E16_MASK = 4837 + + PseudoVFWMSAC_VV_M1_E32 = 4838 + + PseudoVFWMSAC_VV_M1_E32_MASK = 4839 + + PseudoVFWMSAC_VV_M2_E16 = 4840 + + PseudoVFWMSAC_VV_M2_E16_MASK = 4841 + + PseudoVFWMSAC_VV_M2_E32 = 4842 + + PseudoVFWMSAC_VV_M2_E32_MASK = 4843 + + PseudoVFWMSAC_VV_M4_E16 = 4844 + + PseudoVFWMSAC_VV_M4_E16_MASK = 4845 + + PseudoVFWMSAC_VV_M4_E32 = 4846 + + PseudoVFWMSAC_VV_M4_E32_MASK = 4847 + + PseudoVFWMSAC_VV_MF2_E16 = 4848 + + PseudoVFWMSAC_VV_MF2_E16_MASK = 4849 + + PseudoVFWMSAC_VV_MF2_E32 = 4850 + + PseudoVFWMSAC_VV_MF2_E32_MASK = 4851 + + PseudoVFWMSAC_VV_MF4_E16 = 4852 + + PseudoVFWMSAC_VV_MF4_E16_MASK = 4853 + + PseudoVFWMUL_ALT_VFPR16_M1_E16 = 4854 + + PseudoVFWMUL_ALT_VFPR16_M1_E16_MASK = 4855 + + PseudoVFWMUL_ALT_VFPR16_M2_E16 = 4856 + + PseudoVFWMUL_ALT_VFPR16_M2_E16_MASK = 4857 + + PseudoVFWMUL_ALT_VFPR16_M4_E16 = 4858 + + PseudoVFWMUL_ALT_VFPR16_M4_E16_MASK = 4859 + + PseudoVFWMUL_ALT_VFPR16_MF2_E16 = 4860 + + PseudoVFWMUL_ALT_VFPR16_MF2_E16_MASK = 4861 + + PseudoVFWMUL_ALT_VFPR16_MF4_E16 = 4862 + + PseudoVFWMUL_ALT_VFPR16_MF4_E16_MASK = 4863 + + PseudoVFWMUL_ALT_VV_M1_E16 = 4864 + + PseudoVFWMUL_ALT_VV_M1_E16_MASK = 4865 + + PseudoVFWMUL_ALT_VV_M2_E16 = 4866 + + PseudoVFWMUL_ALT_VV_M2_E16_MASK = 4867 + + PseudoVFWMUL_ALT_VV_M4_E16 = 4868 + + PseudoVFWMUL_ALT_VV_M4_E16_MASK = 4869 + + PseudoVFWMUL_ALT_VV_MF2_E16 = 4870 + + PseudoVFWMUL_ALT_VV_MF2_E16_MASK = 4871 + + PseudoVFWMUL_ALT_VV_MF4_E16 = 4872 + + PseudoVFWMUL_ALT_VV_MF4_E16_MASK = 4873 + + PseudoVFWMUL_VFPR16_M1_E16 = 4874 + + PseudoVFWMUL_VFPR16_M1_E16_MASK = 4875 + + PseudoVFWMUL_VFPR16_M2_E16 = 4876 + + PseudoVFWMUL_VFPR16_M2_E16_MASK = 4877 + + PseudoVFWMUL_VFPR16_M4_E16 = 4878 + + PseudoVFWMUL_VFPR16_M4_E16_MASK = 4879 + + PseudoVFWMUL_VFPR16_MF2_E16 = 4880 + + PseudoVFWMUL_VFPR16_MF2_E16_MASK = 4881 + + PseudoVFWMUL_VFPR16_MF4_E16 = 4882 + + PseudoVFWMUL_VFPR16_MF4_E16_MASK = 4883 + + PseudoVFWMUL_VFPR32_M1_E32 = 4884 + + PseudoVFWMUL_VFPR32_M1_E32_MASK = 4885 + + PseudoVFWMUL_VFPR32_M2_E32 = 4886 + + PseudoVFWMUL_VFPR32_M2_E32_MASK = 4887 + + PseudoVFWMUL_VFPR32_M4_E32 = 4888 + + PseudoVFWMUL_VFPR32_M4_E32_MASK = 4889 + + PseudoVFWMUL_VFPR32_MF2_E32 = 4890 + + PseudoVFWMUL_VFPR32_MF2_E32_MASK = 4891 + + PseudoVFWMUL_VV_M1_E16 = 4892 + + PseudoVFWMUL_VV_M1_E16_MASK = 4893 + + PseudoVFWMUL_VV_M1_E32 = 4894 + + PseudoVFWMUL_VV_M1_E32_MASK = 4895 + + PseudoVFWMUL_VV_M2_E16 = 4896 + + PseudoVFWMUL_VV_M2_E16_MASK = 4897 + + PseudoVFWMUL_VV_M2_E32 = 4898 + + PseudoVFWMUL_VV_M2_E32_MASK = 4899 + + PseudoVFWMUL_VV_M4_E16 = 4900 + + PseudoVFWMUL_VV_M4_E16_MASK = 4901 + + PseudoVFWMUL_VV_M4_E32 = 4902 + + PseudoVFWMUL_VV_M4_E32_MASK = 4903 + + PseudoVFWMUL_VV_MF2_E16 = 4904 + + PseudoVFWMUL_VV_MF2_E16_MASK = 4905 + + PseudoVFWMUL_VV_MF2_E32 = 4906 + + PseudoVFWMUL_VV_MF2_E32_MASK = 4907 + + PseudoVFWMUL_VV_MF4_E16 = 4908 + + PseudoVFWMUL_VV_MF4_E16_MASK = 4909 + + PseudoVFWNMACC_ALT_VFPR16_M1_E16 = 4910 + + PseudoVFWNMACC_ALT_VFPR16_M1_E16_MASK = 4911 + + PseudoVFWNMACC_ALT_VFPR16_M2_E16 = 4912 + + PseudoVFWNMACC_ALT_VFPR16_M2_E16_MASK = 4913 + + PseudoVFWNMACC_ALT_VFPR16_M4_E16 = 4914 + + PseudoVFWNMACC_ALT_VFPR16_M4_E16_MASK = 4915 + + PseudoVFWNMACC_ALT_VFPR16_MF2_E16 = 4916 + + PseudoVFWNMACC_ALT_VFPR16_MF2_E16_MASK = 4917 + + PseudoVFWNMACC_ALT_VFPR16_MF4_E16 = 4918 + + PseudoVFWNMACC_ALT_VFPR16_MF4_E16_MASK = 4919 + + PseudoVFWNMACC_ALT_VV_M1_E16 = 4920 + + PseudoVFWNMACC_ALT_VV_M1_E16_MASK = 4921 + + PseudoVFWNMACC_ALT_VV_M2_E16 = 4922 + + PseudoVFWNMACC_ALT_VV_M2_E16_MASK = 4923 + + PseudoVFWNMACC_ALT_VV_M4_E16 = 4924 + + PseudoVFWNMACC_ALT_VV_M4_E16_MASK = 4925 + + PseudoVFWNMACC_ALT_VV_MF2_E16 = 4926 + + PseudoVFWNMACC_ALT_VV_MF2_E16_MASK = 4927 + + PseudoVFWNMACC_ALT_VV_MF4_E16 = 4928 + + PseudoVFWNMACC_ALT_VV_MF4_E16_MASK = 4929 + + PseudoVFWNMACC_VFPR16_M1_E16 = 4930 + + PseudoVFWNMACC_VFPR16_M1_E16_MASK = 4931 + + PseudoVFWNMACC_VFPR16_M2_E16 = 4932 + + PseudoVFWNMACC_VFPR16_M2_E16_MASK = 4933 + + PseudoVFWNMACC_VFPR16_M4_E16 = 4934 + + PseudoVFWNMACC_VFPR16_M4_E16_MASK = 4935 + + PseudoVFWNMACC_VFPR16_MF2_E16 = 4936 + + PseudoVFWNMACC_VFPR16_MF2_E16_MASK = 4937 + + PseudoVFWNMACC_VFPR16_MF4_E16 = 4938 + + PseudoVFWNMACC_VFPR16_MF4_E16_MASK = 4939 + + PseudoVFWNMACC_VFPR32_M1_E32 = 4940 + + PseudoVFWNMACC_VFPR32_M1_E32_MASK = 4941 + + PseudoVFWNMACC_VFPR32_M2_E32 = 4942 + + PseudoVFWNMACC_VFPR32_M2_E32_MASK = 4943 + + PseudoVFWNMACC_VFPR32_M4_E32 = 4944 + + PseudoVFWNMACC_VFPR32_M4_E32_MASK = 4945 + + PseudoVFWNMACC_VFPR32_MF2_E32 = 4946 + + PseudoVFWNMACC_VFPR32_MF2_E32_MASK = 4947 + + PseudoVFWNMACC_VV_M1_E16 = 4948 + + PseudoVFWNMACC_VV_M1_E16_MASK = 4949 + + PseudoVFWNMACC_VV_M1_E32 = 4950 + + PseudoVFWNMACC_VV_M1_E32_MASK = 4951 + + PseudoVFWNMACC_VV_M2_E16 = 4952 + + PseudoVFWNMACC_VV_M2_E16_MASK = 4953 + + PseudoVFWNMACC_VV_M2_E32 = 4954 + + PseudoVFWNMACC_VV_M2_E32_MASK = 4955 + + PseudoVFWNMACC_VV_M4_E16 = 4956 + + PseudoVFWNMACC_VV_M4_E16_MASK = 4957 + + PseudoVFWNMACC_VV_M4_E32 = 4958 + + PseudoVFWNMACC_VV_M4_E32_MASK = 4959 + + PseudoVFWNMACC_VV_MF2_E16 = 4960 + + PseudoVFWNMACC_VV_MF2_E16_MASK = 4961 + + PseudoVFWNMACC_VV_MF2_E32 = 4962 + + PseudoVFWNMACC_VV_MF2_E32_MASK = 4963 + + PseudoVFWNMACC_VV_MF4_E16 = 4964 + + PseudoVFWNMACC_VV_MF4_E16_MASK = 4965 + + PseudoVFWNMSAC_ALT_VFPR16_M1_E16 = 4966 + + PseudoVFWNMSAC_ALT_VFPR16_M1_E16_MASK = 4967 + + PseudoVFWNMSAC_ALT_VFPR16_M2_E16 = 4968 + + PseudoVFWNMSAC_ALT_VFPR16_M2_E16_MASK = 4969 + + PseudoVFWNMSAC_ALT_VFPR16_M4_E16 = 4970 + + PseudoVFWNMSAC_ALT_VFPR16_M4_E16_MASK = 4971 + + PseudoVFWNMSAC_ALT_VFPR16_MF2_E16 = 4972 + + PseudoVFWNMSAC_ALT_VFPR16_MF2_E16_MASK = 4973 + + PseudoVFWNMSAC_ALT_VFPR16_MF4_E16 = 4974 + + PseudoVFWNMSAC_ALT_VFPR16_MF4_E16_MASK = 4975 + + PseudoVFWNMSAC_ALT_VV_M1_E16 = 4976 + + PseudoVFWNMSAC_ALT_VV_M1_E16_MASK = 4977 + + PseudoVFWNMSAC_ALT_VV_M2_E16 = 4978 + + PseudoVFWNMSAC_ALT_VV_M2_E16_MASK = 4979 + + PseudoVFWNMSAC_ALT_VV_M4_E16 = 4980 + + PseudoVFWNMSAC_ALT_VV_M4_E16_MASK = 4981 + + PseudoVFWNMSAC_ALT_VV_MF2_E16 = 4982 + + PseudoVFWNMSAC_ALT_VV_MF2_E16_MASK = 4983 + + PseudoVFWNMSAC_ALT_VV_MF4_E16 = 4984 + + PseudoVFWNMSAC_ALT_VV_MF4_E16_MASK = 4985 + + PseudoVFWNMSAC_VFPR16_M1_E16 = 4986 + + PseudoVFWNMSAC_VFPR16_M1_E16_MASK = 4987 + + PseudoVFWNMSAC_VFPR16_M2_E16 = 4988 + + PseudoVFWNMSAC_VFPR16_M2_E16_MASK = 4989 + + PseudoVFWNMSAC_VFPR16_M4_E16 = 4990 + + PseudoVFWNMSAC_VFPR16_M4_E16_MASK = 4991 + + PseudoVFWNMSAC_VFPR16_MF2_E16 = 4992 + + PseudoVFWNMSAC_VFPR16_MF2_E16_MASK = 4993 + + PseudoVFWNMSAC_VFPR16_MF4_E16 = 4994 + + PseudoVFWNMSAC_VFPR16_MF4_E16_MASK = 4995 + + PseudoVFWNMSAC_VFPR32_M1_E32 = 4996 + + PseudoVFWNMSAC_VFPR32_M1_E32_MASK = 4997 + + PseudoVFWNMSAC_VFPR32_M2_E32 = 4998 + + PseudoVFWNMSAC_VFPR32_M2_E32_MASK = 4999 + + PseudoVFWNMSAC_VFPR32_M4_E32 = 5000 + + PseudoVFWNMSAC_VFPR32_M4_E32_MASK = 5001 + + PseudoVFWNMSAC_VFPR32_MF2_E32 = 5002 + + PseudoVFWNMSAC_VFPR32_MF2_E32_MASK = 5003 + + PseudoVFWNMSAC_VV_M1_E16 = 5004 + + PseudoVFWNMSAC_VV_M1_E16_MASK = 5005 + + PseudoVFWNMSAC_VV_M1_E32 = 5006 + + PseudoVFWNMSAC_VV_M1_E32_MASK = 5007 + + PseudoVFWNMSAC_VV_M2_E16 = 5008 + + PseudoVFWNMSAC_VV_M2_E16_MASK = 5009 + + PseudoVFWNMSAC_VV_M2_E32 = 5010 + + PseudoVFWNMSAC_VV_M2_E32_MASK = 5011 + + PseudoVFWNMSAC_VV_M4_E16 = 5012 + + PseudoVFWNMSAC_VV_M4_E16_MASK = 5013 + + PseudoVFWNMSAC_VV_M4_E32 = 5014 + + PseudoVFWNMSAC_VV_M4_E32_MASK = 5015 + + PseudoVFWNMSAC_VV_MF2_E16 = 5016 + + PseudoVFWNMSAC_VV_MF2_E16_MASK = 5017 + + PseudoVFWNMSAC_VV_MF2_E32 = 5018 + + PseudoVFWNMSAC_VV_MF2_E32_MASK = 5019 + + PseudoVFWNMSAC_VV_MF4_E16 = 5020 + + PseudoVFWNMSAC_VV_MF4_E16_MASK = 5021 + + PseudoVFWREDOSUM_VS_M1_E16 = 5022 + + PseudoVFWREDOSUM_VS_M1_E16_MASK = 5023 + + PseudoVFWREDOSUM_VS_M1_E32 = 5024 + + PseudoVFWREDOSUM_VS_M1_E32_MASK = 5025 + + PseudoVFWREDOSUM_VS_M2_E16 = 5026 + + PseudoVFWREDOSUM_VS_M2_E16_MASK = 5027 + + PseudoVFWREDOSUM_VS_M2_E32 = 5028 + + PseudoVFWREDOSUM_VS_M2_E32_MASK = 5029 + + PseudoVFWREDOSUM_VS_M4_E16 = 5030 + + PseudoVFWREDOSUM_VS_M4_E16_MASK = 5031 + + PseudoVFWREDOSUM_VS_M4_E32 = 5032 + + PseudoVFWREDOSUM_VS_M4_E32_MASK = 5033 + + PseudoVFWREDOSUM_VS_M8_E16 = 5034 + + PseudoVFWREDOSUM_VS_M8_E16_MASK = 5035 + + PseudoVFWREDOSUM_VS_M8_E32 = 5036 + + PseudoVFWREDOSUM_VS_M8_E32_MASK = 5037 + + PseudoVFWREDOSUM_VS_MF2_E16 = 5038 + + PseudoVFWREDOSUM_VS_MF2_E16_MASK = 5039 + + PseudoVFWREDOSUM_VS_MF2_E32 = 5040 + + PseudoVFWREDOSUM_VS_MF2_E32_MASK = 5041 + + PseudoVFWREDOSUM_VS_MF4_E16 = 5042 + + PseudoVFWREDOSUM_VS_MF4_E16_MASK = 5043 + + PseudoVFWREDUSUM_VS_M1_E16 = 5044 + + PseudoVFWREDUSUM_VS_M1_E16_MASK = 5045 + + PseudoVFWREDUSUM_VS_M1_E32 = 5046 + + PseudoVFWREDUSUM_VS_M1_E32_MASK = 5047 + + PseudoVFWREDUSUM_VS_M2_E16 = 5048 + + PseudoVFWREDUSUM_VS_M2_E16_MASK = 5049 + + PseudoVFWREDUSUM_VS_M2_E32 = 5050 + + PseudoVFWREDUSUM_VS_M2_E32_MASK = 5051 + + PseudoVFWREDUSUM_VS_M4_E16 = 5052 + + PseudoVFWREDUSUM_VS_M4_E16_MASK = 5053 + + PseudoVFWREDUSUM_VS_M4_E32 = 5054 + + PseudoVFWREDUSUM_VS_M4_E32_MASK = 5055 + + PseudoVFWREDUSUM_VS_M8_E16 = 5056 + + PseudoVFWREDUSUM_VS_M8_E16_MASK = 5057 + + PseudoVFWREDUSUM_VS_M8_E32 = 5058 + + PseudoVFWREDUSUM_VS_M8_E32_MASK = 5059 + + PseudoVFWREDUSUM_VS_MF2_E16 = 5060 + + PseudoVFWREDUSUM_VS_MF2_E16_MASK = 5061 + + PseudoVFWREDUSUM_VS_MF2_E32 = 5062 + + PseudoVFWREDUSUM_VS_MF2_E32_MASK = 5063 + + PseudoVFWREDUSUM_VS_MF4_E16 = 5064 + + PseudoVFWREDUSUM_VS_MF4_E16_MASK = 5065 + + PseudoVFWSUB_ALT_VFPR16_M1_E16 = 5066 + + PseudoVFWSUB_ALT_VFPR16_M1_E16_MASK = 5067 + + PseudoVFWSUB_ALT_VFPR16_M2_E16 = 5068 + + PseudoVFWSUB_ALT_VFPR16_M2_E16_MASK = 5069 + + PseudoVFWSUB_ALT_VFPR16_M4_E16 = 5070 + + PseudoVFWSUB_ALT_VFPR16_M4_E16_MASK = 5071 + + PseudoVFWSUB_ALT_VFPR16_MF2_E16 = 5072 + + PseudoVFWSUB_ALT_VFPR16_MF2_E16_MASK = 5073 + + PseudoVFWSUB_ALT_VFPR16_MF4_E16 = 5074 + + PseudoVFWSUB_ALT_VFPR16_MF4_E16_MASK = 5075 + + PseudoVFWSUB_ALT_VV_M1_E16 = 5076 + + PseudoVFWSUB_ALT_VV_M1_E16_MASK = 5077 + + PseudoVFWSUB_ALT_VV_M2_E16 = 5078 + + PseudoVFWSUB_ALT_VV_M2_E16_MASK = 5079 + + PseudoVFWSUB_ALT_VV_M4_E16 = 5080 + + PseudoVFWSUB_ALT_VV_M4_E16_MASK = 5081 + + PseudoVFWSUB_ALT_VV_MF2_E16 = 5082 + + PseudoVFWSUB_ALT_VV_MF2_E16_MASK = 5083 + + PseudoVFWSUB_ALT_VV_MF4_E16 = 5084 + + PseudoVFWSUB_ALT_VV_MF4_E16_MASK = 5085 + + PseudoVFWSUB_ALT_WFPR16_M1_E16 = 5086 + + PseudoVFWSUB_ALT_WFPR16_M1_E16_MASK = 5087 + + PseudoVFWSUB_ALT_WFPR16_M2_E16 = 5088 + + PseudoVFWSUB_ALT_WFPR16_M2_E16_MASK = 5089 + + PseudoVFWSUB_ALT_WFPR16_M4_E16 = 5090 + + PseudoVFWSUB_ALT_WFPR16_M4_E16_MASK = 5091 + + PseudoVFWSUB_ALT_WFPR16_MF2_E16 = 5092 + + PseudoVFWSUB_ALT_WFPR16_MF2_E16_MASK = 5093 + + PseudoVFWSUB_ALT_WFPR16_MF4_E16 = 5094 + + PseudoVFWSUB_ALT_WFPR16_MF4_E16_MASK = 5095 + + PseudoVFWSUB_ALT_WV_M1_E16 = 5096 + + PseudoVFWSUB_ALT_WV_M1_E16_MASK = 5097 + + PseudoVFWSUB_ALT_WV_M1_E16_MASK_TIED = 5098 + + PseudoVFWSUB_ALT_WV_M1_E16_TIED = 5099 + + PseudoVFWSUB_ALT_WV_M2_E16 = 5100 + + PseudoVFWSUB_ALT_WV_M2_E16_MASK = 5101 + + PseudoVFWSUB_ALT_WV_M2_E16_MASK_TIED = 5102 + + PseudoVFWSUB_ALT_WV_M2_E16_TIED = 5103 + + PseudoVFWSUB_ALT_WV_M4_E16 = 5104 + + PseudoVFWSUB_ALT_WV_M4_E16_MASK = 5105 + + PseudoVFWSUB_ALT_WV_M4_E16_MASK_TIED = 5106 + + PseudoVFWSUB_ALT_WV_M4_E16_TIED = 5107 + + PseudoVFWSUB_ALT_WV_MF2_E16 = 5108 + + PseudoVFWSUB_ALT_WV_MF2_E16_MASK = 5109 + + PseudoVFWSUB_ALT_WV_MF2_E16_MASK_TIED = 5110 + + PseudoVFWSUB_ALT_WV_MF2_E16_TIED = 5111 + + PseudoVFWSUB_ALT_WV_MF4_E16 = 5112 + + PseudoVFWSUB_ALT_WV_MF4_E16_MASK = 5113 + + PseudoVFWSUB_ALT_WV_MF4_E16_MASK_TIED = 5114 + + PseudoVFWSUB_ALT_WV_MF4_E16_TIED = 5115 + + PseudoVFWSUB_VFPR16_M1_E16 = 5116 + + PseudoVFWSUB_VFPR16_M1_E16_MASK = 5117 + + PseudoVFWSUB_VFPR16_M2_E16 = 5118 + + PseudoVFWSUB_VFPR16_M2_E16_MASK = 5119 + + PseudoVFWSUB_VFPR16_M4_E16 = 5120 + + PseudoVFWSUB_VFPR16_M4_E16_MASK = 5121 + + PseudoVFWSUB_VFPR16_MF2_E16 = 5122 + + PseudoVFWSUB_VFPR16_MF2_E16_MASK = 5123 + + PseudoVFWSUB_VFPR16_MF4_E16 = 5124 + + PseudoVFWSUB_VFPR16_MF4_E16_MASK = 5125 + + PseudoVFWSUB_VFPR32_M1_E32 = 5126 + + PseudoVFWSUB_VFPR32_M1_E32_MASK = 5127 + + PseudoVFWSUB_VFPR32_M2_E32 = 5128 + + PseudoVFWSUB_VFPR32_M2_E32_MASK = 5129 + + PseudoVFWSUB_VFPR32_M4_E32 = 5130 + + PseudoVFWSUB_VFPR32_M4_E32_MASK = 5131 + + PseudoVFWSUB_VFPR32_MF2_E32 = 5132 + + PseudoVFWSUB_VFPR32_MF2_E32_MASK = 5133 + + PseudoVFWSUB_VV_M1_E16 = 5134 + + PseudoVFWSUB_VV_M1_E16_MASK = 5135 + + PseudoVFWSUB_VV_M1_E32 = 5136 + + PseudoVFWSUB_VV_M1_E32_MASK = 5137 + + PseudoVFWSUB_VV_M2_E16 = 5138 + + PseudoVFWSUB_VV_M2_E16_MASK = 5139 + + PseudoVFWSUB_VV_M2_E32 = 5140 + + PseudoVFWSUB_VV_M2_E32_MASK = 5141 + + PseudoVFWSUB_VV_M4_E16 = 5142 + + PseudoVFWSUB_VV_M4_E16_MASK = 5143 + + PseudoVFWSUB_VV_M4_E32 = 5144 + + PseudoVFWSUB_VV_M4_E32_MASK = 5145 + + PseudoVFWSUB_VV_MF2_E16 = 5146 + + PseudoVFWSUB_VV_MF2_E16_MASK = 5147 + + PseudoVFWSUB_VV_MF2_E32 = 5148 + + PseudoVFWSUB_VV_MF2_E32_MASK = 5149 + + PseudoVFWSUB_VV_MF4_E16 = 5150 + + PseudoVFWSUB_VV_MF4_E16_MASK = 5151 + + PseudoVFWSUB_WFPR16_M1_E16 = 5152 + + PseudoVFWSUB_WFPR16_M1_E16_MASK = 5153 + + PseudoVFWSUB_WFPR16_M2_E16 = 5154 + + PseudoVFWSUB_WFPR16_M2_E16_MASK = 5155 + + PseudoVFWSUB_WFPR16_M4_E16 = 5156 + + PseudoVFWSUB_WFPR16_M4_E16_MASK = 5157 + + PseudoVFWSUB_WFPR16_MF2_E16 = 5158 + + PseudoVFWSUB_WFPR16_MF2_E16_MASK = 5159 + + PseudoVFWSUB_WFPR16_MF4_E16 = 5160 + + PseudoVFWSUB_WFPR16_MF4_E16_MASK = 5161 + + PseudoVFWSUB_WFPR32_M1_E32 = 5162 + + PseudoVFWSUB_WFPR32_M1_E32_MASK = 5163 + + PseudoVFWSUB_WFPR32_M2_E32 = 5164 + + PseudoVFWSUB_WFPR32_M2_E32_MASK = 5165 + + PseudoVFWSUB_WFPR32_M4_E32 = 5166 + + PseudoVFWSUB_WFPR32_M4_E32_MASK = 5167 + + PseudoVFWSUB_WFPR32_MF2_E32 = 5168 + + PseudoVFWSUB_WFPR32_MF2_E32_MASK = 5169 + + PseudoVFWSUB_WV_M1_E16 = 5170 + + PseudoVFWSUB_WV_M1_E16_MASK = 5171 + + PseudoVFWSUB_WV_M1_E16_MASK_TIED = 5172 + + PseudoVFWSUB_WV_M1_E16_TIED = 5173 + + PseudoVFWSUB_WV_M1_E32 = 5174 + + PseudoVFWSUB_WV_M1_E32_MASK = 5175 + + PseudoVFWSUB_WV_M1_E32_MASK_TIED = 5176 + + PseudoVFWSUB_WV_M1_E32_TIED = 5177 + + PseudoVFWSUB_WV_M2_E16 = 5178 + + PseudoVFWSUB_WV_M2_E16_MASK = 5179 + + PseudoVFWSUB_WV_M2_E16_MASK_TIED = 5180 + + PseudoVFWSUB_WV_M2_E16_TIED = 5181 + + PseudoVFWSUB_WV_M2_E32 = 5182 + + PseudoVFWSUB_WV_M2_E32_MASK = 5183 + + PseudoVFWSUB_WV_M2_E32_MASK_TIED = 5184 + + PseudoVFWSUB_WV_M2_E32_TIED = 5185 + + PseudoVFWSUB_WV_M4_E16 = 5186 + + PseudoVFWSUB_WV_M4_E16_MASK = 5187 + + PseudoVFWSUB_WV_M4_E16_MASK_TIED = 5188 + + PseudoVFWSUB_WV_M4_E16_TIED = 5189 + + PseudoVFWSUB_WV_M4_E32 = 5190 + + PseudoVFWSUB_WV_M4_E32_MASK = 5191 + + PseudoVFWSUB_WV_M4_E32_MASK_TIED = 5192 + + PseudoVFWSUB_WV_M4_E32_TIED = 5193 + + PseudoVFWSUB_WV_MF2_E16 = 5194 + + PseudoVFWSUB_WV_MF2_E16_MASK = 5195 + + PseudoVFWSUB_WV_MF2_E16_MASK_TIED = 5196 + + PseudoVFWSUB_WV_MF2_E16_TIED = 5197 + + PseudoVFWSUB_WV_MF2_E32 = 5198 + + PseudoVFWSUB_WV_MF2_E32_MASK = 5199 + + PseudoVFWSUB_WV_MF2_E32_MASK_TIED = 5200 + + PseudoVFWSUB_WV_MF2_E32_TIED = 5201 + + PseudoVFWSUB_WV_MF4_E16 = 5202 + + PseudoVFWSUB_WV_MF4_E16_MASK = 5203 + + PseudoVFWSUB_WV_MF4_E16_MASK_TIED = 5204 + + PseudoVFWSUB_WV_MF4_E16_TIED = 5205 + + PseudoVGHSH_VV_M1 = 5206 + + PseudoVGHSH_VV_M2 = 5207 + + PseudoVGHSH_VV_M4 = 5208 + + PseudoVGHSH_VV_M8 = 5209 + + PseudoVGHSH_VV_MF2 = 5210 + + PseudoVGMUL_VV_M1 = 5211 + + PseudoVGMUL_VV_M2 = 5212 + + PseudoVGMUL_VV_M4 = 5213 + + PseudoVGMUL_VV_M8 = 5214 + + PseudoVGMUL_VV_MF2 = 5215 + + PseudoVID_V_M1 = 5216 + + PseudoVID_V_M1_MASK = 5217 + + PseudoVID_V_M2 = 5218 + + PseudoVID_V_M2_MASK = 5219 + + PseudoVID_V_M4 = 5220 + + PseudoVID_V_M4_MASK = 5221 + + PseudoVID_V_M8 = 5222 + + PseudoVID_V_M8_MASK = 5223 + + PseudoVID_V_MF2 = 5224 + + PseudoVID_V_MF2_MASK = 5225 + + PseudoVID_V_MF4 = 5226 + + PseudoVID_V_MF4_MASK = 5227 + + PseudoVID_V_MF8 = 5228 + + PseudoVID_V_MF8_MASK = 5229 + + PseudoVIOTA_M_M1 = 5230 + + PseudoVIOTA_M_M1_MASK = 5231 + + PseudoVIOTA_M_M2 = 5232 + + PseudoVIOTA_M_M2_MASK = 5233 + + PseudoVIOTA_M_M4 = 5234 + + PseudoVIOTA_M_M4_MASK = 5235 + + PseudoVIOTA_M_M8 = 5236 + + PseudoVIOTA_M_M8_MASK = 5237 + + PseudoVIOTA_M_MF2 = 5238 + + PseudoVIOTA_M_MF2_MASK = 5239 + + PseudoVIOTA_M_MF4 = 5240 + + PseudoVIOTA_M_MF4_MASK = 5241 + + PseudoVIOTA_M_MF8 = 5242 + + PseudoVIOTA_M_MF8_MASK = 5243 + + PseudoVLE16FF_V_M1 = 5244 + + PseudoVLE16FF_V_M1_MASK = 5245 + + PseudoVLE16FF_V_M2 = 5246 + + PseudoVLE16FF_V_M2_MASK = 5247 + + PseudoVLE16FF_V_M4 = 5248 + + PseudoVLE16FF_V_M4_MASK = 5249 + + PseudoVLE16FF_V_M8 = 5250 + + PseudoVLE16FF_V_M8_MASK = 5251 + + PseudoVLE16FF_V_MF2 = 5252 + + PseudoVLE16FF_V_MF2_MASK = 5253 + + PseudoVLE16FF_V_MF4 = 5254 + + PseudoVLE16FF_V_MF4_MASK = 5255 + + PseudoVLE16_V_M1 = 5256 + + PseudoVLE16_V_M1_MASK = 5257 + + PseudoVLE16_V_M2 = 5258 + + PseudoVLE16_V_M2_MASK = 5259 + + PseudoVLE16_V_M4 = 5260 + + PseudoVLE16_V_M4_MASK = 5261 + + PseudoVLE16_V_M8 = 5262 + + PseudoVLE16_V_M8_MASK = 5263 + + PseudoVLE16_V_MF2 = 5264 + + PseudoVLE16_V_MF2_MASK = 5265 + + PseudoVLE16_V_MF4 = 5266 + + PseudoVLE16_V_MF4_MASK = 5267 + + PseudoVLE32FF_V_M1 = 5268 + + PseudoVLE32FF_V_M1_MASK = 5269 + + PseudoVLE32FF_V_M2 = 5270 + + PseudoVLE32FF_V_M2_MASK = 5271 + + PseudoVLE32FF_V_M4 = 5272 + + PseudoVLE32FF_V_M4_MASK = 5273 + + PseudoVLE32FF_V_M8 = 5274 + + PseudoVLE32FF_V_M8_MASK = 5275 + + PseudoVLE32FF_V_MF2 = 5276 + + PseudoVLE32FF_V_MF2_MASK = 5277 + + PseudoVLE32_V_M1 = 5278 + + PseudoVLE32_V_M1_MASK = 5279 + + PseudoVLE32_V_M2 = 5280 + + PseudoVLE32_V_M2_MASK = 5281 + + PseudoVLE32_V_M4 = 5282 + + PseudoVLE32_V_M4_MASK = 5283 + + PseudoVLE32_V_M8 = 5284 + + PseudoVLE32_V_M8_MASK = 5285 + + PseudoVLE32_V_MF2 = 5286 + + PseudoVLE32_V_MF2_MASK = 5287 + + PseudoVLE64FF_V_M1 = 5288 + + PseudoVLE64FF_V_M1_MASK = 5289 + + PseudoVLE64FF_V_M2 = 5290 + + PseudoVLE64FF_V_M2_MASK = 5291 + + PseudoVLE64FF_V_M4 = 5292 + + PseudoVLE64FF_V_M4_MASK = 5293 + + PseudoVLE64FF_V_M8 = 5294 + + PseudoVLE64FF_V_M8_MASK = 5295 + + PseudoVLE64_V_M1 = 5296 + + PseudoVLE64_V_M1_MASK = 5297 + + PseudoVLE64_V_M2 = 5298 + + PseudoVLE64_V_M2_MASK = 5299 + + PseudoVLE64_V_M4 = 5300 + + PseudoVLE64_V_M4_MASK = 5301 + + PseudoVLE64_V_M8 = 5302 + + PseudoVLE64_V_M8_MASK = 5303 + + PseudoVLE8FF_V_M1 = 5304 + + PseudoVLE8FF_V_M1_MASK = 5305 + + PseudoVLE8FF_V_M2 = 5306 + + PseudoVLE8FF_V_M2_MASK = 5307 + + PseudoVLE8FF_V_M4 = 5308 + + PseudoVLE8FF_V_M4_MASK = 5309 + + PseudoVLE8FF_V_M8 = 5310 + + PseudoVLE8FF_V_M8_MASK = 5311 + + PseudoVLE8FF_V_MF2 = 5312 + + PseudoVLE8FF_V_MF2_MASK = 5313 + + PseudoVLE8FF_V_MF4 = 5314 + + PseudoVLE8FF_V_MF4_MASK = 5315 + + PseudoVLE8FF_V_MF8 = 5316 + + PseudoVLE8FF_V_MF8_MASK = 5317 + + PseudoVLE8_V_M1 = 5318 + + PseudoVLE8_V_M1_MASK = 5319 + + PseudoVLE8_V_M2 = 5320 + + PseudoVLE8_V_M2_MASK = 5321 + + PseudoVLE8_V_M4 = 5322 + + PseudoVLE8_V_M4_MASK = 5323 + + PseudoVLE8_V_M8 = 5324 + + PseudoVLE8_V_M8_MASK = 5325 + + PseudoVLE8_V_MF2 = 5326 + + PseudoVLE8_V_MF2_MASK = 5327 + + PseudoVLE8_V_MF4 = 5328 + + PseudoVLE8_V_MF4_MASK = 5329 + + PseudoVLE8_V_MF8 = 5330 + + PseudoVLE8_V_MF8_MASK = 5331 + + PseudoVLM_V_B1 = 5332 + + PseudoVLM_V_B16 = 5333 + + PseudoVLM_V_B2 = 5334 + + PseudoVLM_V_B32 = 5335 + + PseudoVLM_V_B4 = 5336 + + PseudoVLM_V_B64 = 5337 + + PseudoVLM_V_B8 = 5338 + + PseudoVLOXEI16_V_M1_M1 = 5339 + + PseudoVLOXEI16_V_M1_M1_MASK = 5340 + + PseudoVLOXEI16_V_M1_M2 = 5341 + + PseudoVLOXEI16_V_M1_M2_MASK = 5342 + + PseudoVLOXEI16_V_M1_M4 = 5343 + + PseudoVLOXEI16_V_M1_M4_MASK = 5344 + + PseudoVLOXEI16_V_M1_MF2 = 5345 + + PseudoVLOXEI16_V_M1_MF2_MASK = 5346 + + PseudoVLOXEI16_V_M2_M1 = 5347 + + PseudoVLOXEI16_V_M2_M1_MASK = 5348 + + PseudoVLOXEI16_V_M2_M2 = 5349 + + PseudoVLOXEI16_V_M2_M2_MASK = 5350 + + PseudoVLOXEI16_V_M2_M4 = 5351 + + PseudoVLOXEI16_V_M2_M4_MASK = 5352 + + PseudoVLOXEI16_V_M2_M8 = 5353 + + PseudoVLOXEI16_V_M2_M8_MASK = 5354 + + PseudoVLOXEI16_V_M4_M2 = 5355 + + PseudoVLOXEI16_V_M4_M2_MASK = 5356 + + PseudoVLOXEI16_V_M4_M4 = 5357 + + PseudoVLOXEI16_V_M4_M4_MASK = 5358 + + PseudoVLOXEI16_V_M4_M8 = 5359 + + PseudoVLOXEI16_V_M4_M8_MASK = 5360 + + PseudoVLOXEI16_V_M8_M4 = 5361 + + PseudoVLOXEI16_V_M8_M4_MASK = 5362 + + PseudoVLOXEI16_V_M8_M8 = 5363 + + PseudoVLOXEI16_V_M8_M8_MASK = 5364 + + PseudoVLOXEI16_V_MF2_M1 = 5365 + + PseudoVLOXEI16_V_MF2_M1_MASK = 5366 + + PseudoVLOXEI16_V_MF2_M2 = 5367 + + PseudoVLOXEI16_V_MF2_M2_MASK = 5368 + + PseudoVLOXEI16_V_MF2_MF2 = 5369 + + PseudoVLOXEI16_V_MF2_MF2_MASK = 5370 + + PseudoVLOXEI16_V_MF2_MF4 = 5371 + + PseudoVLOXEI16_V_MF2_MF4_MASK = 5372 + + PseudoVLOXEI16_V_MF4_M1 = 5373 + + PseudoVLOXEI16_V_MF4_M1_MASK = 5374 + + PseudoVLOXEI16_V_MF4_MF2 = 5375 + + PseudoVLOXEI16_V_MF4_MF2_MASK = 5376 + + PseudoVLOXEI16_V_MF4_MF4 = 5377 + + PseudoVLOXEI16_V_MF4_MF4_MASK = 5378 + + PseudoVLOXEI16_V_MF4_MF8 = 5379 + + PseudoVLOXEI16_V_MF4_MF8_MASK = 5380 + + PseudoVLOXEI32_V_M1_M1 = 5381 + + PseudoVLOXEI32_V_M1_M1_MASK = 5382 + + PseudoVLOXEI32_V_M1_M2 = 5383 + + PseudoVLOXEI32_V_M1_M2_MASK = 5384 + + PseudoVLOXEI32_V_M1_MF2 = 5385 + + PseudoVLOXEI32_V_M1_MF2_MASK = 5386 + + PseudoVLOXEI32_V_M1_MF4 = 5387 + + PseudoVLOXEI32_V_M1_MF4_MASK = 5388 + + PseudoVLOXEI32_V_M2_M1 = 5389 + + PseudoVLOXEI32_V_M2_M1_MASK = 5390 + + PseudoVLOXEI32_V_M2_M2 = 5391 + + PseudoVLOXEI32_V_M2_M2_MASK = 5392 + + PseudoVLOXEI32_V_M2_M4 = 5393 + + PseudoVLOXEI32_V_M2_M4_MASK = 5394 + + PseudoVLOXEI32_V_M2_MF2 = 5395 + + PseudoVLOXEI32_V_M2_MF2_MASK = 5396 + + PseudoVLOXEI32_V_M4_M1 = 5397 + + PseudoVLOXEI32_V_M4_M1_MASK = 5398 + + PseudoVLOXEI32_V_M4_M2 = 5399 + + PseudoVLOXEI32_V_M4_M2_MASK = 5400 + + PseudoVLOXEI32_V_M4_M4 = 5401 + + PseudoVLOXEI32_V_M4_M4_MASK = 5402 + + PseudoVLOXEI32_V_M4_M8 = 5403 + + PseudoVLOXEI32_V_M4_M8_MASK = 5404 + + PseudoVLOXEI32_V_M8_M2 = 5405 + + PseudoVLOXEI32_V_M8_M2_MASK = 5406 + + PseudoVLOXEI32_V_M8_M4 = 5407 + + PseudoVLOXEI32_V_M8_M4_MASK = 5408 + + PseudoVLOXEI32_V_M8_M8 = 5409 + + PseudoVLOXEI32_V_M8_M8_MASK = 5410 + + PseudoVLOXEI32_V_MF2_M1 = 5411 + + PseudoVLOXEI32_V_MF2_M1_MASK = 5412 + + PseudoVLOXEI32_V_MF2_MF2 = 5413 + + PseudoVLOXEI32_V_MF2_MF2_MASK = 5414 + + PseudoVLOXEI32_V_MF2_MF4 = 5415 + + PseudoVLOXEI32_V_MF2_MF4_MASK = 5416 + + PseudoVLOXEI32_V_MF2_MF8 = 5417 + + PseudoVLOXEI32_V_MF2_MF8_MASK = 5418 + + PseudoVLOXEI64_V_M1_M1 = 5419 + + PseudoVLOXEI64_V_M1_M1_MASK = 5420 + + PseudoVLOXEI64_V_M1_MF2 = 5421 + + PseudoVLOXEI64_V_M1_MF2_MASK = 5422 + + PseudoVLOXEI64_V_M1_MF4 = 5423 + + PseudoVLOXEI64_V_M1_MF4_MASK = 5424 + + PseudoVLOXEI64_V_M1_MF8 = 5425 + + PseudoVLOXEI64_V_M1_MF8_MASK = 5426 + + PseudoVLOXEI64_V_M2_M1 = 5427 + + PseudoVLOXEI64_V_M2_M1_MASK = 5428 + + PseudoVLOXEI64_V_M2_M2 = 5429 + + PseudoVLOXEI64_V_M2_M2_MASK = 5430 + + PseudoVLOXEI64_V_M2_MF2 = 5431 + + PseudoVLOXEI64_V_M2_MF2_MASK = 5432 + + PseudoVLOXEI64_V_M2_MF4 = 5433 + + PseudoVLOXEI64_V_M2_MF4_MASK = 5434 + + PseudoVLOXEI64_V_M4_M1 = 5435 + + PseudoVLOXEI64_V_M4_M1_MASK = 5436 + + PseudoVLOXEI64_V_M4_M2 = 5437 + + PseudoVLOXEI64_V_M4_M2_MASK = 5438 + + PseudoVLOXEI64_V_M4_M4 = 5439 + + PseudoVLOXEI64_V_M4_M4_MASK = 5440 + + PseudoVLOXEI64_V_M4_MF2 = 5441 + + PseudoVLOXEI64_V_M4_MF2_MASK = 5442 + + PseudoVLOXEI64_V_M8_M1 = 5443 + + PseudoVLOXEI64_V_M8_M1_MASK = 5444 + + PseudoVLOXEI64_V_M8_M2 = 5445 + + PseudoVLOXEI64_V_M8_M2_MASK = 5446 + + PseudoVLOXEI64_V_M8_M4 = 5447 + + PseudoVLOXEI64_V_M8_M4_MASK = 5448 + + PseudoVLOXEI64_V_M8_M8 = 5449 + + PseudoVLOXEI64_V_M8_M8_MASK = 5450 + + PseudoVLOXEI8_V_M1_M1 = 5451 + + PseudoVLOXEI8_V_M1_M1_MASK = 5452 + + PseudoVLOXEI8_V_M1_M2 = 5453 + + PseudoVLOXEI8_V_M1_M2_MASK = 5454 + + PseudoVLOXEI8_V_M1_M4 = 5455 + + PseudoVLOXEI8_V_M1_M4_MASK = 5456 + + PseudoVLOXEI8_V_M1_M8 = 5457 + + PseudoVLOXEI8_V_M1_M8_MASK = 5458 + + PseudoVLOXEI8_V_M2_M2 = 5459 + + PseudoVLOXEI8_V_M2_M2_MASK = 5460 + + PseudoVLOXEI8_V_M2_M4 = 5461 + + PseudoVLOXEI8_V_M2_M4_MASK = 5462 + + PseudoVLOXEI8_V_M2_M8 = 5463 + + PseudoVLOXEI8_V_M2_M8_MASK = 5464 + + PseudoVLOXEI8_V_M4_M4 = 5465 + + PseudoVLOXEI8_V_M4_M4_MASK = 5466 + + PseudoVLOXEI8_V_M4_M8 = 5467 + + PseudoVLOXEI8_V_M4_M8_MASK = 5468 + + PseudoVLOXEI8_V_M8_M8 = 5469 + + PseudoVLOXEI8_V_M8_M8_MASK = 5470 + + PseudoVLOXEI8_V_MF2_M1 = 5471 + + PseudoVLOXEI8_V_MF2_M1_MASK = 5472 + + PseudoVLOXEI8_V_MF2_M2 = 5473 + + PseudoVLOXEI8_V_MF2_M2_MASK = 5474 + + PseudoVLOXEI8_V_MF2_M4 = 5475 + + PseudoVLOXEI8_V_MF2_M4_MASK = 5476 + + PseudoVLOXEI8_V_MF2_MF2 = 5477 + + PseudoVLOXEI8_V_MF2_MF2_MASK = 5478 + + PseudoVLOXEI8_V_MF4_M1 = 5479 + + PseudoVLOXEI8_V_MF4_M1_MASK = 5480 + + PseudoVLOXEI8_V_MF4_M2 = 5481 + + PseudoVLOXEI8_V_MF4_M2_MASK = 5482 + + PseudoVLOXEI8_V_MF4_MF2 = 5483 + + PseudoVLOXEI8_V_MF4_MF2_MASK = 5484 + + PseudoVLOXEI8_V_MF4_MF4 = 5485 + + PseudoVLOXEI8_V_MF4_MF4_MASK = 5486 + + PseudoVLOXEI8_V_MF8_M1 = 5487 + + PseudoVLOXEI8_V_MF8_M1_MASK = 5488 + + PseudoVLOXEI8_V_MF8_MF2 = 5489 + + PseudoVLOXEI8_V_MF8_MF2_MASK = 5490 + + PseudoVLOXEI8_V_MF8_MF4 = 5491 + + PseudoVLOXEI8_V_MF8_MF4_MASK = 5492 + + PseudoVLOXEI8_V_MF8_MF8 = 5493 + + PseudoVLOXEI8_V_MF8_MF8_MASK = 5494 + + PseudoVLOXSEG2EI16_V_M1_M1 = 5495 + + PseudoVLOXSEG2EI16_V_M1_M1_MASK = 5496 + + PseudoVLOXSEG2EI16_V_M1_M2 = 5497 + + PseudoVLOXSEG2EI16_V_M1_M2_MASK = 5498 + + PseudoVLOXSEG2EI16_V_M1_M4 = 5499 + + PseudoVLOXSEG2EI16_V_M1_M4_MASK = 5500 + + PseudoVLOXSEG2EI16_V_M1_MF2 = 5501 + + PseudoVLOXSEG2EI16_V_M1_MF2_MASK = 5502 + + PseudoVLOXSEG2EI16_V_M2_M1 = 5503 + + PseudoVLOXSEG2EI16_V_M2_M1_MASK = 5504 + + PseudoVLOXSEG2EI16_V_M2_M2 = 5505 + + PseudoVLOXSEG2EI16_V_M2_M2_MASK = 5506 + + PseudoVLOXSEG2EI16_V_M2_M4 = 5507 + + PseudoVLOXSEG2EI16_V_M2_M4_MASK = 5508 + + PseudoVLOXSEG2EI16_V_M4_M2 = 5509 + + PseudoVLOXSEG2EI16_V_M4_M2_MASK = 5510 + + PseudoVLOXSEG2EI16_V_M4_M4 = 5511 + + PseudoVLOXSEG2EI16_V_M4_M4_MASK = 5512 + + PseudoVLOXSEG2EI16_V_M8_M4 = 5513 + + PseudoVLOXSEG2EI16_V_M8_M4_MASK = 5514 + + PseudoVLOXSEG2EI16_V_MF2_M1 = 5515 + + PseudoVLOXSEG2EI16_V_MF2_M1_MASK = 5516 + + PseudoVLOXSEG2EI16_V_MF2_M2 = 5517 + + PseudoVLOXSEG2EI16_V_MF2_M2_MASK = 5518 + + PseudoVLOXSEG2EI16_V_MF2_MF2 = 5519 + + PseudoVLOXSEG2EI16_V_MF2_MF2_MASK = 5520 + + PseudoVLOXSEG2EI16_V_MF2_MF4 = 5521 + + PseudoVLOXSEG2EI16_V_MF2_MF4_MASK = 5522 + + PseudoVLOXSEG2EI16_V_MF4_M1 = 5523 + + PseudoVLOXSEG2EI16_V_MF4_M1_MASK = 5524 + + PseudoVLOXSEG2EI16_V_MF4_MF2 = 5525 + + PseudoVLOXSEG2EI16_V_MF4_MF2_MASK = 5526 + + PseudoVLOXSEG2EI16_V_MF4_MF4 = 5527 + + PseudoVLOXSEG2EI16_V_MF4_MF4_MASK = 5528 + + PseudoVLOXSEG2EI16_V_MF4_MF8 = 5529 + + PseudoVLOXSEG2EI16_V_MF4_MF8_MASK = 5530 + + PseudoVLOXSEG2EI32_V_M1_M1 = 5531 + + PseudoVLOXSEG2EI32_V_M1_M1_MASK = 5532 + + PseudoVLOXSEG2EI32_V_M1_M2 = 5533 + + PseudoVLOXSEG2EI32_V_M1_M2_MASK = 5534 + + PseudoVLOXSEG2EI32_V_M1_MF2 = 5535 + + PseudoVLOXSEG2EI32_V_M1_MF2_MASK = 5536 + + PseudoVLOXSEG2EI32_V_M1_MF4 = 5537 + + PseudoVLOXSEG2EI32_V_M1_MF4_MASK = 5538 + + PseudoVLOXSEG2EI32_V_M2_M1 = 5539 + + PseudoVLOXSEG2EI32_V_M2_M1_MASK = 5540 + + PseudoVLOXSEG2EI32_V_M2_M2 = 5541 + + PseudoVLOXSEG2EI32_V_M2_M2_MASK = 5542 + + PseudoVLOXSEG2EI32_V_M2_M4 = 5543 + + PseudoVLOXSEG2EI32_V_M2_M4_MASK = 5544 + + PseudoVLOXSEG2EI32_V_M2_MF2 = 5545 + + PseudoVLOXSEG2EI32_V_M2_MF2_MASK = 5546 + + PseudoVLOXSEG2EI32_V_M4_M1 = 5547 + + PseudoVLOXSEG2EI32_V_M4_M1_MASK = 5548 + + PseudoVLOXSEG2EI32_V_M4_M2 = 5549 + + PseudoVLOXSEG2EI32_V_M4_M2_MASK = 5550 + + PseudoVLOXSEG2EI32_V_M4_M4 = 5551 + + PseudoVLOXSEG2EI32_V_M4_M4_MASK = 5552 + + PseudoVLOXSEG2EI32_V_M8_M2 = 5553 + + PseudoVLOXSEG2EI32_V_M8_M2_MASK = 5554 + + PseudoVLOXSEG2EI32_V_M8_M4 = 5555 + + PseudoVLOXSEG2EI32_V_M8_M4_MASK = 5556 + + PseudoVLOXSEG2EI32_V_MF2_M1 = 5557 + + PseudoVLOXSEG2EI32_V_MF2_M1_MASK = 5558 + + PseudoVLOXSEG2EI32_V_MF2_MF2 = 5559 + + PseudoVLOXSEG2EI32_V_MF2_MF2_MASK = 5560 + + PseudoVLOXSEG2EI32_V_MF2_MF4 = 5561 + + PseudoVLOXSEG2EI32_V_MF2_MF4_MASK = 5562 + + PseudoVLOXSEG2EI32_V_MF2_MF8 = 5563 + + PseudoVLOXSEG2EI32_V_MF2_MF8_MASK = 5564 + + PseudoVLOXSEG2EI64_V_M1_M1 = 5565 + + PseudoVLOXSEG2EI64_V_M1_M1_MASK = 5566 + + PseudoVLOXSEG2EI64_V_M1_MF2 = 5567 + + PseudoVLOXSEG2EI64_V_M1_MF2_MASK = 5568 + + PseudoVLOXSEG2EI64_V_M1_MF4 = 5569 + + PseudoVLOXSEG2EI64_V_M1_MF4_MASK = 5570 + + PseudoVLOXSEG2EI64_V_M1_MF8 = 5571 + + PseudoVLOXSEG2EI64_V_M1_MF8_MASK = 5572 + + PseudoVLOXSEG2EI64_V_M2_M1 = 5573 + + PseudoVLOXSEG2EI64_V_M2_M1_MASK = 5574 + + PseudoVLOXSEG2EI64_V_M2_M2 = 5575 + + PseudoVLOXSEG2EI64_V_M2_M2_MASK = 5576 + + PseudoVLOXSEG2EI64_V_M2_MF2 = 5577 + + PseudoVLOXSEG2EI64_V_M2_MF2_MASK = 5578 + + PseudoVLOXSEG2EI64_V_M2_MF4 = 5579 + + PseudoVLOXSEG2EI64_V_M2_MF4_MASK = 5580 + + PseudoVLOXSEG2EI64_V_M4_M1 = 5581 + + PseudoVLOXSEG2EI64_V_M4_M1_MASK = 5582 + + PseudoVLOXSEG2EI64_V_M4_M2 = 5583 + + PseudoVLOXSEG2EI64_V_M4_M2_MASK = 5584 + + PseudoVLOXSEG2EI64_V_M4_M4 = 5585 + + PseudoVLOXSEG2EI64_V_M4_M4_MASK = 5586 + + PseudoVLOXSEG2EI64_V_M4_MF2 = 5587 + + PseudoVLOXSEG2EI64_V_M4_MF2_MASK = 5588 + + PseudoVLOXSEG2EI64_V_M8_M1 = 5589 + + PseudoVLOXSEG2EI64_V_M8_M1_MASK = 5590 + + PseudoVLOXSEG2EI64_V_M8_M2 = 5591 + + PseudoVLOXSEG2EI64_V_M8_M2_MASK = 5592 + + PseudoVLOXSEG2EI64_V_M8_M4 = 5593 + + PseudoVLOXSEG2EI64_V_M8_M4_MASK = 5594 + + PseudoVLOXSEG2EI8_V_M1_M1 = 5595 + + PseudoVLOXSEG2EI8_V_M1_M1_MASK = 5596 + + PseudoVLOXSEG2EI8_V_M1_M2 = 5597 + + PseudoVLOXSEG2EI8_V_M1_M2_MASK = 5598 + + PseudoVLOXSEG2EI8_V_M1_M4 = 5599 + + PseudoVLOXSEG2EI8_V_M1_M4_MASK = 5600 + + PseudoVLOXSEG2EI8_V_M2_M2 = 5601 + + PseudoVLOXSEG2EI8_V_M2_M2_MASK = 5602 + + PseudoVLOXSEG2EI8_V_M2_M4 = 5603 + + PseudoVLOXSEG2EI8_V_M2_M4_MASK = 5604 + + PseudoVLOXSEG2EI8_V_M4_M4 = 5605 + + PseudoVLOXSEG2EI8_V_M4_M4_MASK = 5606 + + PseudoVLOXSEG2EI8_V_MF2_M1 = 5607 + + PseudoVLOXSEG2EI8_V_MF2_M1_MASK = 5608 + + PseudoVLOXSEG2EI8_V_MF2_M2 = 5609 + + PseudoVLOXSEG2EI8_V_MF2_M2_MASK = 5610 + + PseudoVLOXSEG2EI8_V_MF2_M4 = 5611 + + PseudoVLOXSEG2EI8_V_MF2_M4_MASK = 5612 + + PseudoVLOXSEG2EI8_V_MF2_MF2 = 5613 + + PseudoVLOXSEG2EI8_V_MF2_MF2_MASK = 5614 + + PseudoVLOXSEG2EI8_V_MF4_M1 = 5615 + + PseudoVLOXSEG2EI8_V_MF4_M1_MASK = 5616 + + PseudoVLOXSEG2EI8_V_MF4_M2 = 5617 + + PseudoVLOXSEG2EI8_V_MF4_M2_MASK = 5618 + + PseudoVLOXSEG2EI8_V_MF4_MF2 = 5619 + + PseudoVLOXSEG2EI8_V_MF4_MF2_MASK = 5620 + + PseudoVLOXSEG2EI8_V_MF4_MF4 = 5621 + + PseudoVLOXSEG2EI8_V_MF4_MF4_MASK = 5622 + + PseudoVLOXSEG2EI8_V_MF8_M1 = 5623 + + PseudoVLOXSEG2EI8_V_MF8_M1_MASK = 5624 + + PseudoVLOXSEG2EI8_V_MF8_MF2 = 5625 + + PseudoVLOXSEG2EI8_V_MF8_MF2_MASK = 5626 + + PseudoVLOXSEG2EI8_V_MF8_MF4 = 5627 + + PseudoVLOXSEG2EI8_V_MF8_MF4_MASK = 5628 + + PseudoVLOXSEG2EI8_V_MF8_MF8 = 5629 + + PseudoVLOXSEG2EI8_V_MF8_MF8_MASK = 5630 + + PseudoVLOXSEG3EI16_V_M1_M1 = 5631 + + PseudoVLOXSEG3EI16_V_M1_M1_MASK = 5632 + + PseudoVLOXSEG3EI16_V_M1_M2 = 5633 + + PseudoVLOXSEG3EI16_V_M1_M2_MASK = 5634 + + PseudoVLOXSEG3EI16_V_M1_MF2 = 5635 + + PseudoVLOXSEG3EI16_V_M1_MF2_MASK = 5636 + + PseudoVLOXSEG3EI16_V_M2_M1 = 5637 + + PseudoVLOXSEG3EI16_V_M2_M1_MASK = 5638 + + PseudoVLOXSEG3EI16_V_M2_M2 = 5639 + + PseudoVLOXSEG3EI16_V_M2_M2_MASK = 5640 + + PseudoVLOXSEG3EI16_V_M4_M2 = 5641 + + PseudoVLOXSEG3EI16_V_M4_M2_MASK = 5642 + + PseudoVLOXSEG3EI16_V_MF2_M1 = 5643 + + PseudoVLOXSEG3EI16_V_MF2_M1_MASK = 5644 + + PseudoVLOXSEG3EI16_V_MF2_M2 = 5645 + + PseudoVLOXSEG3EI16_V_MF2_M2_MASK = 5646 + + PseudoVLOXSEG3EI16_V_MF2_MF2 = 5647 + + PseudoVLOXSEG3EI16_V_MF2_MF2_MASK = 5648 + + PseudoVLOXSEG3EI16_V_MF2_MF4 = 5649 + + PseudoVLOXSEG3EI16_V_MF2_MF4_MASK = 5650 + + PseudoVLOXSEG3EI16_V_MF4_M1 = 5651 + + PseudoVLOXSEG3EI16_V_MF4_M1_MASK = 5652 + + PseudoVLOXSEG3EI16_V_MF4_MF2 = 5653 + + PseudoVLOXSEG3EI16_V_MF4_MF2_MASK = 5654 + + PseudoVLOXSEG3EI16_V_MF4_MF4 = 5655 + + PseudoVLOXSEG3EI16_V_MF4_MF4_MASK = 5656 + + PseudoVLOXSEG3EI16_V_MF4_MF8 = 5657 + + PseudoVLOXSEG3EI16_V_MF4_MF8_MASK = 5658 + + PseudoVLOXSEG3EI32_V_M1_M1 = 5659 + + PseudoVLOXSEG3EI32_V_M1_M1_MASK = 5660 + + PseudoVLOXSEG3EI32_V_M1_M2 = 5661 + + PseudoVLOXSEG3EI32_V_M1_M2_MASK = 5662 + + PseudoVLOXSEG3EI32_V_M1_MF2 = 5663 + + PseudoVLOXSEG3EI32_V_M1_MF2_MASK = 5664 + + PseudoVLOXSEG3EI32_V_M1_MF4 = 5665 + + PseudoVLOXSEG3EI32_V_M1_MF4_MASK = 5666 + + PseudoVLOXSEG3EI32_V_M2_M1 = 5667 + + PseudoVLOXSEG3EI32_V_M2_M1_MASK = 5668 + + PseudoVLOXSEG3EI32_V_M2_M2 = 5669 + + PseudoVLOXSEG3EI32_V_M2_M2_MASK = 5670 + + PseudoVLOXSEG3EI32_V_M2_MF2 = 5671 + + PseudoVLOXSEG3EI32_V_M2_MF2_MASK = 5672 + + PseudoVLOXSEG3EI32_V_M4_M1 = 5673 + + PseudoVLOXSEG3EI32_V_M4_M1_MASK = 5674 + + PseudoVLOXSEG3EI32_V_M4_M2 = 5675 + + PseudoVLOXSEG3EI32_V_M4_M2_MASK = 5676 + + PseudoVLOXSEG3EI32_V_M8_M2 = 5677 + + PseudoVLOXSEG3EI32_V_M8_M2_MASK = 5678 + + PseudoVLOXSEG3EI32_V_MF2_M1 = 5679 + + PseudoVLOXSEG3EI32_V_MF2_M1_MASK = 5680 + + PseudoVLOXSEG3EI32_V_MF2_MF2 = 5681 + + PseudoVLOXSEG3EI32_V_MF2_MF2_MASK = 5682 + + PseudoVLOXSEG3EI32_V_MF2_MF4 = 5683 + + PseudoVLOXSEG3EI32_V_MF2_MF4_MASK = 5684 + + PseudoVLOXSEG3EI32_V_MF2_MF8 = 5685 + + PseudoVLOXSEG3EI32_V_MF2_MF8_MASK = 5686 + + PseudoVLOXSEG3EI64_V_M1_M1 = 5687 + + PseudoVLOXSEG3EI64_V_M1_M1_MASK = 5688 + + PseudoVLOXSEG3EI64_V_M1_MF2 = 5689 + + PseudoVLOXSEG3EI64_V_M1_MF2_MASK = 5690 + + PseudoVLOXSEG3EI64_V_M1_MF4 = 5691 + + PseudoVLOXSEG3EI64_V_M1_MF4_MASK = 5692 + + PseudoVLOXSEG3EI64_V_M1_MF8 = 5693 + + PseudoVLOXSEG3EI64_V_M1_MF8_MASK = 5694 + + PseudoVLOXSEG3EI64_V_M2_M1 = 5695 + + PseudoVLOXSEG3EI64_V_M2_M1_MASK = 5696 + + PseudoVLOXSEG3EI64_V_M2_M2 = 5697 + + PseudoVLOXSEG3EI64_V_M2_M2_MASK = 5698 + + PseudoVLOXSEG3EI64_V_M2_MF2 = 5699 + + PseudoVLOXSEG3EI64_V_M2_MF2_MASK = 5700 + + PseudoVLOXSEG3EI64_V_M2_MF4 = 5701 + + PseudoVLOXSEG3EI64_V_M2_MF4_MASK = 5702 + + PseudoVLOXSEG3EI64_V_M4_M1 = 5703 + + PseudoVLOXSEG3EI64_V_M4_M1_MASK = 5704 + + PseudoVLOXSEG3EI64_V_M4_M2 = 5705 + + PseudoVLOXSEG3EI64_V_M4_M2_MASK = 5706 + + PseudoVLOXSEG3EI64_V_M4_MF2 = 5707 + + PseudoVLOXSEG3EI64_V_M4_MF2_MASK = 5708 + + PseudoVLOXSEG3EI64_V_M8_M1 = 5709 + + PseudoVLOXSEG3EI64_V_M8_M1_MASK = 5710 + + PseudoVLOXSEG3EI64_V_M8_M2 = 5711 + + PseudoVLOXSEG3EI64_V_M8_M2_MASK = 5712 + + PseudoVLOXSEG3EI8_V_M1_M1 = 5713 + + PseudoVLOXSEG3EI8_V_M1_M1_MASK = 5714 + + PseudoVLOXSEG3EI8_V_M1_M2 = 5715 + + PseudoVLOXSEG3EI8_V_M1_M2_MASK = 5716 + + PseudoVLOXSEG3EI8_V_M2_M2 = 5717 + + PseudoVLOXSEG3EI8_V_M2_M2_MASK = 5718 + + PseudoVLOXSEG3EI8_V_MF2_M1 = 5719 + + PseudoVLOXSEG3EI8_V_MF2_M1_MASK = 5720 + + PseudoVLOXSEG3EI8_V_MF2_M2 = 5721 + + PseudoVLOXSEG3EI8_V_MF2_M2_MASK = 5722 + + PseudoVLOXSEG3EI8_V_MF2_MF2 = 5723 + + PseudoVLOXSEG3EI8_V_MF2_MF2_MASK = 5724 + + PseudoVLOXSEG3EI8_V_MF4_M1 = 5725 + + PseudoVLOXSEG3EI8_V_MF4_M1_MASK = 5726 + + PseudoVLOXSEG3EI8_V_MF4_M2 = 5727 + + PseudoVLOXSEG3EI8_V_MF4_M2_MASK = 5728 + + PseudoVLOXSEG3EI8_V_MF4_MF2 = 5729 + + PseudoVLOXSEG3EI8_V_MF4_MF2_MASK = 5730 + + PseudoVLOXSEG3EI8_V_MF4_MF4 = 5731 + + PseudoVLOXSEG3EI8_V_MF4_MF4_MASK = 5732 + + PseudoVLOXSEG3EI8_V_MF8_M1 = 5733 + + PseudoVLOXSEG3EI8_V_MF8_M1_MASK = 5734 + + PseudoVLOXSEG3EI8_V_MF8_MF2 = 5735 + + PseudoVLOXSEG3EI8_V_MF8_MF2_MASK = 5736 + + PseudoVLOXSEG3EI8_V_MF8_MF4 = 5737 + + PseudoVLOXSEG3EI8_V_MF8_MF4_MASK = 5738 + + PseudoVLOXSEG3EI8_V_MF8_MF8 = 5739 + + PseudoVLOXSEG3EI8_V_MF8_MF8_MASK = 5740 + + PseudoVLOXSEG4EI16_V_M1_M1 = 5741 + + PseudoVLOXSEG4EI16_V_M1_M1_MASK = 5742 + + PseudoVLOXSEG4EI16_V_M1_M2 = 5743 + + PseudoVLOXSEG4EI16_V_M1_M2_MASK = 5744 + + PseudoVLOXSEG4EI16_V_M1_MF2 = 5745 + + PseudoVLOXSEG4EI16_V_M1_MF2_MASK = 5746 + + PseudoVLOXSEG4EI16_V_M2_M1 = 5747 + + PseudoVLOXSEG4EI16_V_M2_M1_MASK = 5748 + + PseudoVLOXSEG4EI16_V_M2_M2 = 5749 + + PseudoVLOXSEG4EI16_V_M2_M2_MASK = 5750 + + PseudoVLOXSEG4EI16_V_M4_M2 = 5751 + + PseudoVLOXSEG4EI16_V_M4_M2_MASK = 5752 + + PseudoVLOXSEG4EI16_V_MF2_M1 = 5753 + + PseudoVLOXSEG4EI16_V_MF2_M1_MASK = 5754 + + PseudoVLOXSEG4EI16_V_MF2_M2 = 5755 + + PseudoVLOXSEG4EI16_V_MF2_M2_MASK = 5756 + + PseudoVLOXSEG4EI16_V_MF2_MF2 = 5757 + + PseudoVLOXSEG4EI16_V_MF2_MF2_MASK = 5758 + + PseudoVLOXSEG4EI16_V_MF2_MF4 = 5759 + + PseudoVLOXSEG4EI16_V_MF2_MF4_MASK = 5760 + + PseudoVLOXSEG4EI16_V_MF4_M1 = 5761 + + PseudoVLOXSEG4EI16_V_MF4_M1_MASK = 5762 + + PseudoVLOXSEG4EI16_V_MF4_MF2 = 5763 + + PseudoVLOXSEG4EI16_V_MF4_MF2_MASK = 5764 + + PseudoVLOXSEG4EI16_V_MF4_MF4 = 5765 + + PseudoVLOXSEG4EI16_V_MF4_MF4_MASK = 5766 + + PseudoVLOXSEG4EI16_V_MF4_MF8 = 5767 + + PseudoVLOXSEG4EI16_V_MF4_MF8_MASK = 5768 + + PseudoVLOXSEG4EI32_V_M1_M1 = 5769 + + PseudoVLOXSEG4EI32_V_M1_M1_MASK = 5770 + + PseudoVLOXSEG4EI32_V_M1_M2 = 5771 + + PseudoVLOXSEG4EI32_V_M1_M2_MASK = 5772 + + PseudoVLOXSEG4EI32_V_M1_MF2 = 5773 + + PseudoVLOXSEG4EI32_V_M1_MF2_MASK = 5774 + + PseudoVLOXSEG4EI32_V_M1_MF4 = 5775 + + PseudoVLOXSEG4EI32_V_M1_MF4_MASK = 5776 + + PseudoVLOXSEG4EI32_V_M2_M1 = 5777 + + PseudoVLOXSEG4EI32_V_M2_M1_MASK = 5778 + + PseudoVLOXSEG4EI32_V_M2_M2 = 5779 + + PseudoVLOXSEG4EI32_V_M2_M2_MASK = 5780 + + PseudoVLOXSEG4EI32_V_M2_MF2 = 5781 + + PseudoVLOXSEG4EI32_V_M2_MF2_MASK = 5782 + + PseudoVLOXSEG4EI32_V_M4_M1 = 5783 + + PseudoVLOXSEG4EI32_V_M4_M1_MASK = 5784 + + PseudoVLOXSEG4EI32_V_M4_M2 = 5785 + + PseudoVLOXSEG4EI32_V_M4_M2_MASK = 5786 + + PseudoVLOXSEG4EI32_V_M8_M2 = 5787 + + PseudoVLOXSEG4EI32_V_M8_M2_MASK = 5788 + + PseudoVLOXSEG4EI32_V_MF2_M1 = 5789 + + PseudoVLOXSEG4EI32_V_MF2_M1_MASK = 5790 + + PseudoVLOXSEG4EI32_V_MF2_MF2 = 5791 + + PseudoVLOXSEG4EI32_V_MF2_MF2_MASK = 5792 + + PseudoVLOXSEG4EI32_V_MF2_MF4 = 5793 + + PseudoVLOXSEG4EI32_V_MF2_MF4_MASK = 5794 + + PseudoVLOXSEG4EI32_V_MF2_MF8 = 5795 + + PseudoVLOXSEG4EI32_V_MF2_MF8_MASK = 5796 + + PseudoVLOXSEG4EI64_V_M1_M1 = 5797 + + PseudoVLOXSEG4EI64_V_M1_M1_MASK = 5798 + + PseudoVLOXSEG4EI64_V_M1_MF2 = 5799 + + PseudoVLOXSEG4EI64_V_M1_MF2_MASK = 5800 + + PseudoVLOXSEG4EI64_V_M1_MF4 = 5801 + + PseudoVLOXSEG4EI64_V_M1_MF4_MASK = 5802 + + PseudoVLOXSEG4EI64_V_M1_MF8 = 5803 + + PseudoVLOXSEG4EI64_V_M1_MF8_MASK = 5804 + + PseudoVLOXSEG4EI64_V_M2_M1 = 5805 + + PseudoVLOXSEG4EI64_V_M2_M1_MASK = 5806 + + PseudoVLOXSEG4EI64_V_M2_M2 = 5807 + + PseudoVLOXSEG4EI64_V_M2_M2_MASK = 5808 + + PseudoVLOXSEG4EI64_V_M2_MF2 = 5809 + + PseudoVLOXSEG4EI64_V_M2_MF2_MASK = 5810 + + PseudoVLOXSEG4EI64_V_M2_MF4 = 5811 + + PseudoVLOXSEG4EI64_V_M2_MF4_MASK = 5812 + + PseudoVLOXSEG4EI64_V_M4_M1 = 5813 + + PseudoVLOXSEG4EI64_V_M4_M1_MASK = 5814 + + PseudoVLOXSEG4EI64_V_M4_M2 = 5815 + + PseudoVLOXSEG4EI64_V_M4_M2_MASK = 5816 + + PseudoVLOXSEG4EI64_V_M4_MF2 = 5817 + + PseudoVLOXSEG4EI64_V_M4_MF2_MASK = 5818 + + PseudoVLOXSEG4EI64_V_M8_M1 = 5819 + + PseudoVLOXSEG4EI64_V_M8_M1_MASK = 5820 + + PseudoVLOXSEG4EI64_V_M8_M2 = 5821 + + PseudoVLOXSEG4EI64_V_M8_M2_MASK = 5822 + + PseudoVLOXSEG4EI8_V_M1_M1 = 5823 + + PseudoVLOXSEG4EI8_V_M1_M1_MASK = 5824 + + PseudoVLOXSEG4EI8_V_M1_M2 = 5825 + + PseudoVLOXSEG4EI8_V_M1_M2_MASK = 5826 + + PseudoVLOXSEG4EI8_V_M2_M2 = 5827 + + PseudoVLOXSEG4EI8_V_M2_M2_MASK = 5828 + + PseudoVLOXSEG4EI8_V_MF2_M1 = 5829 + + PseudoVLOXSEG4EI8_V_MF2_M1_MASK = 5830 + + PseudoVLOXSEG4EI8_V_MF2_M2 = 5831 + + PseudoVLOXSEG4EI8_V_MF2_M2_MASK = 5832 + + PseudoVLOXSEG4EI8_V_MF2_MF2 = 5833 + + PseudoVLOXSEG4EI8_V_MF2_MF2_MASK = 5834 + + PseudoVLOXSEG4EI8_V_MF4_M1 = 5835 + + PseudoVLOXSEG4EI8_V_MF4_M1_MASK = 5836 + + PseudoVLOXSEG4EI8_V_MF4_M2 = 5837 + + PseudoVLOXSEG4EI8_V_MF4_M2_MASK = 5838 + + PseudoVLOXSEG4EI8_V_MF4_MF2 = 5839 + + PseudoVLOXSEG4EI8_V_MF4_MF2_MASK = 5840 + + PseudoVLOXSEG4EI8_V_MF4_MF4 = 5841 + + PseudoVLOXSEG4EI8_V_MF4_MF4_MASK = 5842 + + PseudoVLOXSEG4EI8_V_MF8_M1 = 5843 + + PseudoVLOXSEG4EI8_V_MF8_M1_MASK = 5844 + + PseudoVLOXSEG4EI8_V_MF8_MF2 = 5845 + + PseudoVLOXSEG4EI8_V_MF8_MF2_MASK = 5846 + + PseudoVLOXSEG4EI8_V_MF8_MF4 = 5847 + + PseudoVLOXSEG4EI8_V_MF8_MF4_MASK = 5848 + + PseudoVLOXSEG4EI8_V_MF8_MF8 = 5849 + + PseudoVLOXSEG4EI8_V_MF8_MF8_MASK = 5850 + + PseudoVLOXSEG5EI16_V_M1_M1 = 5851 + + PseudoVLOXSEG5EI16_V_M1_M1_MASK = 5852 + + PseudoVLOXSEG5EI16_V_M1_MF2 = 5853 + + PseudoVLOXSEG5EI16_V_M1_MF2_MASK = 5854 + + PseudoVLOXSEG5EI16_V_M2_M1 = 5855 + + PseudoVLOXSEG5EI16_V_M2_M1_MASK = 5856 + + PseudoVLOXSEG5EI16_V_MF2_M1 = 5857 + + PseudoVLOXSEG5EI16_V_MF2_M1_MASK = 5858 + + PseudoVLOXSEG5EI16_V_MF2_MF2 = 5859 + + PseudoVLOXSEG5EI16_V_MF2_MF2_MASK = 5860 + + PseudoVLOXSEG5EI16_V_MF2_MF4 = 5861 + + PseudoVLOXSEG5EI16_V_MF2_MF4_MASK = 5862 + + PseudoVLOXSEG5EI16_V_MF4_M1 = 5863 + + PseudoVLOXSEG5EI16_V_MF4_M1_MASK = 5864 + + PseudoVLOXSEG5EI16_V_MF4_MF2 = 5865 + + PseudoVLOXSEG5EI16_V_MF4_MF2_MASK = 5866 + + PseudoVLOXSEG5EI16_V_MF4_MF4 = 5867 + + PseudoVLOXSEG5EI16_V_MF4_MF4_MASK = 5868 + + PseudoVLOXSEG5EI16_V_MF4_MF8 = 5869 + + PseudoVLOXSEG5EI16_V_MF4_MF8_MASK = 5870 + + PseudoVLOXSEG5EI32_V_M1_M1 = 5871 + + PseudoVLOXSEG5EI32_V_M1_M1_MASK = 5872 + + PseudoVLOXSEG5EI32_V_M1_MF2 = 5873 + + PseudoVLOXSEG5EI32_V_M1_MF2_MASK = 5874 + + PseudoVLOXSEG5EI32_V_M1_MF4 = 5875 + + PseudoVLOXSEG5EI32_V_M1_MF4_MASK = 5876 + + PseudoVLOXSEG5EI32_V_M2_M1 = 5877 + + PseudoVLOXSEG5EI32_V_M2_M1_MASK = 5878 + + PseudoVLOXSEG5EI32_V_M2_MF2 = 5879 + + PseudoVLOXSEG5EI32_V_M2_MF2_MASK = 5880 + + PseudoVLOXSEG5EI32_V_M4_M1 = 5881 + + PseudoVLOXSEG5EI32_V_M4_M1_MASK = 5882 + + PseudoVLOXSEG5EI32_V_MF2_M1 = 5883 + + PseudoVLOXSEG5EI32_V_MF2_M1_MASK = 5884 + + PseudoVLOXSEG5EI32_V_MF2_MF2 = 5885 + + PseudoVLOXSEG5EI32_V_MF2_MF2_MASK = 5886 + + PseudoVLOXSEG5EI32_V_MF2_MF4 = 5887 + + PseudoVLOXSEG5EI32_V_MF2_MF4_MASK = 5888 + + PseudoVLOXSEG5EI32_V_MF2_MF8 = 5889 + + PseudoVLOXSEG5EI32_V_MF2_MF8_MASK = 5890 + + PseudoVLOXSEG5EI64_V_M1_M1 = 5891 + + PseudoVLOXSEG5EI64_V_M1_M1_MASK = 5892 + + PseudoVLOXSEG5EI64_V_M1_MF2 = 5893 + + PseudoVLOXSEG5EI64_V_M1_MF2_MASK = 5894 + + PseudoVLOXSEG5EI64_V_M1_MF4 = 5895 + + PseudoVLOXSEG5EI64_V_M1_MF4_MASK = 5896 + + PseudoVLOXSEG5EI64_V_M1_MF8 = 5897 + + PseudoVLOXSEG5EI64_V_M1_MF8_MASK = 5898 + + PseudoVLOXSEG5EI64_V_M2_M1 = 5899 + + PseudoVLOXSEG5EI64_V_M2_M1_MASK = 5900 + + PseudoVLOXSEG5EI64_V_M2_MF2 = 5901 + + PseudoVLOXSEG5EI64_V_M2_MF2_MASK = 5902 + + PseudoVLOXSEG5EI64_V_M2_MF4 = 5903 + + PseudoVLOXSEG5EI64_V_M2_MF4_MASK = 5904 + + PseudoVLOXSEG5EI64_V_M4_M1 = 5905 + + PseudoVLOXSEG5EI64_V_M4_M1_MASK = 5906 + + PseudoVLOXSEG5EI64_V_M4_MF2 = 5907 + + PseudoVLOXSEG5EI64_V_M4_MF2_MASK = 5908 + + PseudoVLOXSEG5EI64_V_M8_M1 = 5909 + + PseudoVLOXSEG5EI64_V_M8_M1_MASK = 5910 + + PseudoVLOXSEG5EI8_V_M1_M1 = 5911 + + PseudoVLOXSEG5EI8_V_M1_M1_MASK = 5912 + + PseudoVLOXSEG5EI8_V_MF2_M1 = 5913 + + PseudoVLOXSEG5EI8_V_MF2_M1_MASK = 5914 + + PseudoVLOXSEG5EI8_V_MF2_MF2 = 5915 + + PseudoVLOXSEG5EI8_V_MF2_MF2_MASK = 5916 + + PseudoVLOXSEG5EI8_V_MF4_M1 = 5917 + + PseudoVLOXSEG5EI8_V_MF4_M1_MASK = 5918 + + PseudoVLOXSEG5EI8_V_MF4_MF2 = 5919 + + PseudoVLOXSEG5EI8_V_MF4_MF2_MASK = 5920 + + PseudoVLOXSEG5EI8_V_MF4_MF4 = 5921 + + PseudoVLOXSEG5EI8_V_MF4_MF4_MASK = 5922 + + PseudoVLOXSEG5EI8_V_MF8_M1 = 5923 + + PseudoVLOXSEG5EI8_V_MF8_M1_MASK = 5924 + + PseudoVLOXSEG5EI8_V_MF8_MF2 = 5925 + + PseudoVLOXSEG5EI8_V_MF8_MF2_MASK = 5926 + + PseudoVLOXSEG5EI8_V_MF8_MF4 = 5927 + + PseudoVLOXSEG5EI8_V_MF8_MF4_MASK = 5928 + + PseudoVLOXSEG5EI8_V_MF8_MF8 = 5929 + + PseudoVLOXSEG5EI8_V_MF8_MF8_MASK = 5930 + + PseudoVLOXSEG6EI16_V_M1_M1 = 5931 + + PseudoVLOXSEG6EI16_V_M1_M1_MASK = 5932 + + PseudoVLOXSEG6EI16_V_M1_MF2 = 5933 + + PseudoVLOXSEG6EI16_V_M1_MF2_MASK = 5934 + + PseudoVLOXSEG6EI16_V_M2_M1 = 5935 + + PseudoVLOXSEG6EI16_V_M2_M1_MASK = 5936 + + PseudoVLOXSEG6EI16_V_MF2_M1 = 5937 + + PseudoVLOXSEG6EI16_V_MF2_M1_MASK = 5938 + + PseudoVLOXSEG6EI16_V_MF2_MF2 = 5939 + + PseudoVLOXSEG6EI16_V_MF2_MF2_MASK = 5940 + + PseudoVLOXSEG6EI16_V_MF2_MF4 = 5941 + + PseudoVLOXSEG6EI16_V_MF2_MF4_MASK = 5942 + + PseudoVLOXSEG6EI16_V_MF4_M1 = 5943 + + PseudoVLOXSEG6EI16_V_MF4_M1_MASK = 5944 + + PseudoVLOXSEG6EI16_V_MF4_MF2 = 5945 + + PseudoVLOXSEG6EI16_V_MF4_MF2_MASK = 5946 + + PseudoVLOXSEG6EI16_V_MF4_MF4 = 5947 + + PseudoVLOXSEG6EI16_V_MF4_MF4_MASK = 5948 + + PseudoVLOXSEG6EI16_V_MF4_MF8 = 5949 + + PseudoVLOXSEG6EI16_V_MF4_MF8_MASK = 5950 + + PseudoVLOXSEG6EI32_V_M1_M1 = 5951 + + PseudoVLOXSEG6EI32_V_M1_M1_MASK = 5952 + + PseudoVLOXSEG6EI32_V_M1_MF2 = 5953 + + PseudoVLOXSEG6EI32_V_M1_MF2_MASK = 5954 + + PseudoVLOXSEG6EI32_V_M1_MF4 = 5955 + + PseudoVLOXSEG6EI32_V_M1_MF4_MASK = 5956 + + PseudoVLOXSEG6EI32_V_M2_M1 = 5957 + + PseudoVLOXSEG6EI32_V_M2_M1_MASK = 5958 + + PseudoVLOXSEG6EI32_V_M2_MF2 = 5959 + + PseudoVLOXSEG6EI32_V_M2_MF2_MASK = 5960 + + PseudoVLOXSEG6EI32_V_M4_M1 = 5961 + + PseudoVLOXSEG6EI32_V_M4_M1_MASK = 5962 + + PseudoVLOXSEG6EI32_V_MF2_M1 = 5963 + + PseudoVLOXSEG6EI32_V_MF2_M1_MASK = 5964 + + PseudoVLOXSEG6EI32_V_MF2_MF2 = 5965 + + PseudoVLOXSEG6EI32_V_MF2_MF2_MASK = 5966 + + PseudoVLOXSEG6EI32_V_MF2_MF4 = 5967 + + PseudoVLOXSEG6EI32_V_MF2_MF4_MASK = 5968 + + PseudoVLOXSEG6EI32_V_MF2_MF8 = 5969 + + PseudoVLOXSEG6EI32_V_MF2_MF8_MASK = 5970 + + PseudoVLOXSEG6EI64_V_M1_M1 = 5971 + + PseudoVLOXSEG6EI64_V_M1_M1_MASK = 5972 + + PseudoVLOXSEG6EI64_V_M1_MF2 = 5973 + + PseudoVLOXSEG6EI64_V_M1_MF2_MASK = 5974 + + PseudoVLOXSEG6EI64_V_M1_MF4 = 5975 + + PseudoVLOXSEG6EI64_V_M1_MF4_MASK = 5976 + + PseudoVLOXSEG6EI64_V_M1_MF8 = 5977 + + PseudoVLOXSEG6EI64_V_M1_MF8_MASK = 5978 + + PseudoVLOXSEG6EI64_V_M2_M1 = 5979 + + PseudoVLOXSEG6EI64_V_M2_M1_MASK = 5980 + + PseudoVLOXSEG6EI64_V_M2_MF2 = 5981 + + PseudoVLOXSEG6EI64_V_M2_MF2_MASK = 5982 + + PseudoVLOXSEG6EI64_V_M2_MF4 = 5983 + + PseudoVLOXSEG6EI64_V_M2_MF4_MASK = 5984 + + PseudoVLOXSEG6EI64_V_M4_M1 = 5985 + + PseudoVLOXSEG6EI64_V_M4_M1_MASK = 5986 + + PseudoVLOXSEG6EI64_V_M4_MF2 = 5987 + + PseudoVLOXSEG6EI64_V_M4_MF2_MASK = 5988 + + PseudoVLOXSEG6EI64_V_M8_M1 = 5989 + + PseudoVLOXSEG6EI64_V_M8_M1_MASK = 5990 + + PseudoVLOXSEG6EI8_V_M1_M1 = 5991 + + PseudoVLOXSEG6EI8_V_M1_M1_MASK = 5992 + + PseudoVLOXSEG6EI8_V_MF2_M1 = 5993 + + PseudoVLOXSEG6EI8_V_MF2_M1_MASK = 5994 + + PseudoVLOXSEG6EI8_V_MF2_MF2 = 5995 + + PseudoVLOXSEG6EI8_V_MF2_MF2_MASK = 5996 + + PseudoVLOXSEG6EI8_V_MF4_M1 = 5997 + + PseudoVLOXSEG6EI8_V_MF4_M1_MASK = 5998 + + PseudoVLOXSEG6EI8_V_MF4_MF2 = 5999 + + PseudoVLOXSEG6EI8_V_MF4_MF2_MASK = 6000 + + PseudoVLOXSEG6EI8_V_MF4_MF4 = 6001 + + PseudoVLOXSEG6EI8_V_MF4_MF4_MASK = 6002 + + PseudoVLOXSEG6EI8_V_MF8_M1 = 6003 + + PseudoVLOXSEG6EI8_V_MF8_M1_MASK = 6004 + + PseudoVLOXSEG6EI8_V_MF8_MF2 = 6005 + + PseudoVLOXSEG6EI8_V_MF8_MF2_MASK = 6006 + + PseudoVLOXSEG6EI8_V_MF8_MF4 = 6007 + + PseudoVLOXSEG6EI8_V_MF8_MF4_MASK = 6008 + + PseudoVLOXSEG6EI8_V_MF8_MF8 = 6009 + + PseudoVLOXSEG6EI8_V_MF8_MF8_MASK = 6010 + + PseudoVLOXSEG7EI16_V_M1_M1 = 6011 + + PseudoVLOXSEG7EI16_V_M1_M1_MASK = 6012 + + PseudoVLOXSEG7EI16_V_M1_MF2 = 6013 + + PseudoVLOXSEG7EI16_V_M1_MF2_MASK = 6014 + + PseudoVLOXSEG7EI16_V_M2_M1 = 6015 + + PseudoVLOXSEG7EI16_V_M2_M1_MASK = 6016 + + PseudoVLOXSEG7EI16_V_MF2_M1 = 6017 + + PseudoVLOXSEG7EI16_V_MF2_M1_MASK = 6018 + + PseudoVLOXSEG7EI16_V_MF2_MF2 = 6019 + + PseudoVLOXSEG7EI16_V_MF2_MF2_MASK = 6020 + + PseudoVLOXSEG7EI16_V_MF2_MF4 = 6021 + + PseudoVLOXSEG7EI16_V_MF2_MF4_MASK = 6022 + + PseudoVLOXSEG7EI16_V_MF4_M1 = 6023 + + PseudoVLOXSEG7EI16_V_MF4_M1_MASK = 6024 + + PseudoVLOXSEG7EI16_V_MF4_MF2 = 6025 + + PseudoVLOXSEG7EI16_V_MF4_MF2_MASK = 6026 + + PseudoVLOXSEG7EI16_V_MF4_MF4 = 6027 + + PseudoVLOXSEG7EI16_V_MF4_MF4_MASK = 6028 + + PseudoVLOXSEG7EI16_V_MF4_MF8 = 6029 + + PseudoVLOXSEG7EI16_V_MF4_MF8_MASK = 6030 + + PseudoVLOXSEG7EI32_V_M1_M1 = 6031 + + PseudoVLOXSEG7EI32_V_M1_M1_MASK = 6032 + + PseudoVLOXSEG7EI32_V_M1_MF2 = 6033 + + PseudoVLOXSEG7EI32_V_M1_MF2_MASK = 6034 + + PseudoVLOXSEG7EI32_V_M1_MF4 = 6035 + + PseudoVLOXSEG7EI32_V_M1_MF4_MASK = 6036 + + PseudoVLOXSEG7EI32_V_M2_M1 = 6037 + + PseudoVLOXSEG7EI32_V_M2_M1_MASK = 6038 + + PseudoVLOXSEG7EI32_V_M2_MF2 = 6039 + + PseudoVLOXSEG7EI32_V_M2_MF2_MASK = 6040 + + PseudoVLOXSEG7EI32_V_M4_M1 = 6041 + + PseudoVLOXSEG7EI32_V_M4_M1_MASK = 6042 + + PseudoVLOXSEG7EI32_V_MF2_M1 = 6043 + + PseudoVLOXSEG7EI32_V_MF2_M1_MASK = 6044 + + PseudoVLOXSEG7EI32_V_MF2_MF2 = 6045 + + PseudoVLOXSEG7EI32_V_MF2_MF2_MASK = 6046 + + PseudoVLOXSEG7EI32_V_MF2_MF4 = 6047 + + PseudoVLOXSEG7EI32_V_MF2_MF4_MASK = 6048 + + PseudoVLOXSEG7EI32_V_MF2_MF8 = 6049 + + PseudoVLOXSEG7EI32_V_MF2_MF8_MASK = 6050 + + PseudoVLOXSEG7EI64_V_M1_M1 = 6051 + + PseudoVLOXSEG7EI64_V_M1_M1_MASK = 6052 + + PseudoVLOXSEG7EI64_V_M1_MF2 = 6053 + + PseudoVLOXSEG7EI64_V_M1_MF2_MASK = 6054 + + PseudoVLOXSEG7EI64_V_M1_MF4 = 6055 + + PseudoVLOXSEG7EI64_V_M1_MF4_MASK = 6056 + + PseudoVLOXSEG7EI64_V_M1_MF8 = 6057 + + PseudoVLOXSEG7EI64_V_M1_MF8_MASK = 6058 + + PseudoVLOXSEG7EI64_V_M2_M1 = 6059 + + PseudoVLOXSEG7EI64_V_M2_M1_MASK = 6060 + + PseudoVLOXSEG7EI64_V_M2_MF2 = 6061 + + PseudoVLOXSEG7EI64_V_M2_MF2_MASK = 6062 + + PseudoVLOXSEG7EI64_V_M2_MF4 = 6063 + + PseudoVLOXSEG7EI64_V_M2_MF4_MASK = 6064 + + PseudoVLOXSEG7EI64_V_M4_M1 = 6065 + + PseudoVLOXSEG7EI64_V_M4_M1_MASK = 6066 + + PseudoVLOXSEG7EI64_V_M4_MF2 = 6067 + + PseudoVLOXSEG7EI64_V_M4_MF2_MASK = 6068 + + PseudoVLOXSEG7EI64_V_M8_M1 = 6069 + + PseudoVLOXSEG7EI64_V_M8_M1_MASK = 6070 + + PseudoVLOXSEG7EI8_V_M1_M1 = 6071 + + PseudoVLOXSEG7EI8_V_M1_M1_MASK = 6072 + + PseudoVLOXSEG7EI8_V_MF2_M1 = 6073 + + PseudoVLOXSEG7EI8_V_MF2_M1_MASK = 6074 + + PseudoVLOXSEG7EI8_V_MF2_MF2 = 6075 + + PseudoVLOXSEG7EI8_V_MF2_MF2_MASK = 6076 + + PseudoVLOXSEG7EI8_V_MF4_M1 = 6077 + + PseudoVLOXSEG7EI8_V_MF4_M1_MASK = 6078 + + PseudoVLOXSEG7EI8_V_MF4_MF2 = 6079 + + PseudoVLOXSEG7EI8_V_MF4_MF2_MASK = 6080 + + PseudoVLOXSEG7EI8_V_MF4_MF4 = 6081 + + PseudoVLOXSEG7EI8_V_MF4_MF4_MASK = 6082 + + PseudoVLOXSEG7EI8_V_MF8_M1 = 6083 + + PseudoVLOXSEG7EI8_V_MF8_M1_MASK = 6084 + + PseudoVLOXSEG7EI8_V_MF8_MF2 = 6085 + + PseudoVLOXSEG7EI8_V_MF8_MF2_MASK = 6086 + + PseudoVLOXSEG7EI8_V_MF8_MF4 = 6087 + + PseudoVLOXSEG7EI8_V_MF8_MF4_MASK = 6088 + + PseudoVLOXSEG7EI8_V_MF8_MF8 = 6089 + + PseudoVLOXSEG7EI8_V_MF8_MF8_MASK = 6090 + + PseudoVLOXSEG8EI16_V_M1_M1 = 6091 + + PseudoVLOXSEG8EI16_V_M1_M1_MASK = 6092 + + PseudoVLOXSEG8EI16_V_M1_MF2 = 6093 + + PseudoVLOXSEG8EI16_V_M1_MF2_MASK = 6094 + + PseudoVLOXSEG8EI16_V_M2_M1 = 6095 + + PseudoVLOXSEG8EI16_V_M2_M1_MASK = 6096 + + PseudoVLOXSEG8EI16_V_MF2_M1 = 6097 + + PseudoVLOXSEG8EI16_V_MF2_M1_MASK = 6098 + + PseudoVLOXSEG8EI16_V_MF2_MF2 = 6099 + + PseudoVLOXSEG8EI16_V_MF2_MF2_MASK = 6100 + + PseudoVLOXSEG8EI16_V_MF2_MF4 = 6101 + + PseudoVLOXSEG8EI16_V_MF2_MF4_MASK = 6102 + + PseudoVLOXSEG8EI16_V_MF4_M1 = 6103 + + PseudoVLOXSEG8EI16_V_MF4_M1_MASK = 6104 + + PseudoVLOXSEG8EI16_V_MF4_MF2 = 6105 + + PseudoVLOXSEG8EI16_V_MF4_MF2_MASK = 6106 + + PseudoVLOXSEG8EI16_V_MF4_MF4 = 6107 + + PseudoVLOXSEG8EI16_V_MF4_MF4_MASK = 6108 + + PseudoVLOXSEG8EI16_V_MF4_MF8 = 6109 + + PseudoVLOXSEG8EI16_V_MF4_MF8_MASK = 6110 + + PseudoVLOXSEG8EI32_V_M1_M1 = 6111 + + PseudoVLOXSEG8EI32_V_M1_M1_MASK = 6112 + + PseudoVLOXSEG8EI32_V_M1_MF2 = 6113 + + PseudoVLOXSEG8EI32_V_M1_MF2_MASK = 6114 + + PseudoVLOXSEG8EI32_V_M1_MF4 = 6115 + + PseudoVLOXSEG8EI32_V_M1_MF4_MASK = 6116 + + PseudoVLOXSEG8EI32_V_M2_M1 = 6117 + + PseudoVLOXSEG8EI32_V_M2_M1_MASK = 6118 + + PseudoVLOXSEG8EI32_V_M2_MF2 = 6119 + + PseudoVLOXSEG8EI32_V_M2_MF2_MASK = 6120 + + PseudoVLOXSEG8EI32_V_M4_M1 = 6121 + + PseudoVLOXSEG8EI32_V_M4_M1_MASK = 6122 + + PseudoVLOXSEG8EI32_V_MF2_M1 = 6123 + + PseudoVLOXSEG8EI32_V_MF2_M1_MASK = 6124 + + PseudoVLOXSEG8EI32_V_MF2_MF2 = 6125 + + PseudoVLOXSEG8EI32_V_MF2_MF2_MASK = 6126 + + PseudoVLOXSEG8EI32_V_MF2_MF4 = 6127 + + PseudoVLOXSEG8EI32_V_MF2_MF4_MASK = 6128 + + PseudoVLOXSEG8EI32_V_MF2_MF8 = 6129 + + PseudoVLOXSEG8EI32_V_MF2_MF8_MASK = 6130 + + PseudoVLOXSEG8EI64_V_M1_M1 = 6131 + + PseudoVLOXSEG8EI64_V_M1_M1_MASK = 6132 + + PseudoVLOXSEG8EI64_V_M1_MF2 = 6133 + + PseudoVLOXSEG8EI64_V_M1_MF2_MASK = 6134 + + PseudoVLOXSEG8EI64_V_M1_MF4 = 6135 + + PseudoVLOXSEG8EI64_V_M1_MF4_MASK = 6136 + + PseudoVLOXSEG8EI64_V_M1_MF8 = 6137 + + PseudoVLOXSEG8EI64_V_M1_MF8_MASK = 6138 + + PseudoVLOXSEG8EI64_V_M2_M1 = 6139 + + PseudoVLOXSEG8EI64_V_M2_M1_MASK = 6140 + + PseudoVLOXSEG8EI64_V_M2_MF2 = 6141 + + PseudoVLOXSEG8EI64_V_M2_MF2_MASK = 6142 + + PseudoVLOXSEG8EI64_V_M2_MF4 = 6143 + + PseudoVLOXSEG8EI64_V_M2_MF4_MASK = 6144 + + PseudoVLOXSEG8EI64_V_M4_M1 = 6145 + + PseudoVLOXSEG8EI64_V_M4_M1_MASK = 6146 + + PseudoVLOXSEG8EI64_V_M4_MF2 = 6147 + + PseudoVLOXSEG8EI64_V_M4_MF2_MASK = 6148 + + PseudoVLOXSEG8EI64_V_M8_M1 = 6149 + + PseudoVLOXSEG8EI64_V_M8_M1_MASK = 6150 + + PseudoVLOXSEG8EI8_V_M1_M1 = 6151 + + PseudoVLOXSEG8EI8_V_M1_M1_MASK = 6152 + + PseudoVLOXSEG8EI8_V_MF2_M1 = 6153 + + PseudoVLOXSEG8EI8_V_MF2_M1_MASK = 6154 + + PseudoVLOXSEG8EI8_V_MF2_MF2 = 6155 + + PseudoVLOXSEG8EI8_V_MF2_MF2_MASK = 6156 + + PseudoVLOXSEG8EI8_V_MF4_M1 = 6157 + + PseudoVLOXSEG8EI8_V_MF4_M1_MASK = 6158 + + PseudoVLOXSEG8EI8_V_MF4_MF2 = 6159 + + PseudoVLOXSEG8EI8_V_MF4_MF2_MASK = 6160 + + PseudoVLOXSEG8EI8_V_MF4_MF4 = 6161 + + PseudoVLOXSEG8EI8_V_MF4_MF4_MASK = 6162 + + PseudoVLOXSEG8EI8_V_MF8_M1 = 6163 + + PseudoVLOXSEG8EI8_V_MF8_M1_MASK = 6164 + + PseudoVLOXSEG8EI8_V_MF8_MF2 = 6165 + + PseudoVLOXSEG8EI8_V_MF8_MF2_MASK = 6166 + + PseudoVLOXSEG8EI8_V_MF8_MF4 = 6167 + + PseudoVLOXSEG8EI8_V_MF8_MF4_MASK = 6168 + + PseudoVLOXSEG8EI8_V_MF8_MF8 = 6169 + + PseudoVLOXSEG8EI8_V_MF8_MF8_MASK = 6170 + + PseudoVLSE16_V_M1 = 6171 + + PseudoVLSE16_V_M1_MASK = 6172 + + PseudoVLSE16_V_M2 = 6173 + + PseudoVLSE16_V_M2_MASK = 6174 + + PseudoVLSE16_V_M4 = 6175 + + PseudoVLSE16_V_M4_MASK = 6176 + + PseudoVLSE16_V_M8 = 6177 + + PseudoVLSE16_V_M8_MASK = 6178 + + PseudoVLSE16_V_MF2 = 6179 + + PseudoVLSE16_V_MF2_MASK = 6180 + + PseudoVLSE16_V_MF4 = 6181 + + PseudoVLSE16_V_MF4_MASK = 6182 + + PseudoVLSE32_V_M1 = 6183 + + PseudoVLSE32_V_M1_MASK = 6184 + + PseudoVLSE32_V_M2 = 6185 + + PseudoVLSE32_V_M2_MASK = 6186 + + PseudoVLSE32_V_M4 = 6187 + + PseudoVLSE32_V_M4_MASK = 6188 + + PseudoVLSE32_V_M8 = 6189 + + PseudoVLSE32_V_M8_MASK = 6190 + + PseudoVLSE32_V_MF2 = 6191 + + PseudoVLSE32_V_MF2_MASK = 6192 + + PseudoVLSE64_V_M1 = 6193 + + PseudoVLSE64_V_M1_MASK = 6194 + + PseudoVLSE64_V_M2 = 6195 + + PseudoVLSE64_V_M2_MASK = 6196 + + PseudoVLSE64_V_M4 = 6197 + + PseudoVLSE64_V_M4_MASK = 6198 + + PseudoVLSE64_V_M8 = 6199 + + PseudoVLSE64_V_M8_MASK = 6200 + + PseudoVLSE8_V_M1 = 6201 + + PseudoVLSE8_V_M1_MASK = 6202 + + PseudoVLSE8_V_M2 = 6203 + + PseudoVLSE8_V_M2_MASK = 6204 + + PseudoVLSE8_V_M4 = 6205 + + PseudoVLSE8_V_M4_MASK = 6206 + + PseudoVLSE8_V_M8 = 6207 + + PseudoVLSE8_V_M8_MASK = 6208 + + PseudoVLSE8_V_MF2 = 6209 + + PseudoVLSE8_V_MF2_MASK = 6210 + + PseudoVLSE8_V_MF4 = 6211 + + PseudoVLSE8_V_MF4_MASK = 6212 + + PseudoVLSE8_V_MF8 = 6213 + + PseudoVLSE8_V_MF8_MASK = 6214 + + PseudoVLSEG2E16FF_V_M1 = 6215 + + PseudoVLSEG2E16FF_V_M1_MASK = 6216 + + PseudoVLSEG2E16FF_V_M2 = 6217 + + PseudoVLSEG2E16FF_V_M2_MASK = 6218 + + PseudoVLSEG2E16FF_V_M4 = 6219 + + PseudoVLSEG2E16FF_V_M4_MASK = 6220 + + PseudoVLSEG2E16FF_V_MF2 = 6221 + + PseudoVLSEG2E16FF_V_MF2_MASK = 6222 + + PseudoVLSEG2E16FF_V_MF4 = 6223 + + PseudoVLSEG2E16FF_V_MF4_MASK = 6224 + + PseudoVLSEG2E16_V_M1 = 6225 + + PseudoVLSEG2E16_V_M1_MASK = 6226 + + PseudoVLSEG2E16_V_M2 = 6227 + + PseudoVLSEG2E16_V_M2_MASK = 6228 + + PseudoVLSEG2E16_V_M4 = 6229 + + PseudoVLSEG2E16_V_M4_MASK = 6230 + + PseudoVLSEG2E16_V_MF2 = 6231 + + PseudoVLSEG2E16_V_MF2_MASK = 6232 + + PseudoVLSEG2E16_V_MF4 = 6233 + + PseudoVLSEG2E16_V_MF4_MASK = 6234 + + PseudoVLSEG2E32FF_V_M1 = 6235 + + PseudoVLSEG2E32FF_V_M1_MASK = 6236 + + PseudoVLSEG2E32FF_V_M2 = 6237 + + PseudoVLSEG2E32FF_V_M2_MASK = 6238 + + PseudoVLSEG2E32FF_V_M4 = 6239 + + PseudoVLSEG2E32FF_V_M4_MASK = 6240 + + PseudoVLSEG2E32FF_V_MF2 = 6241 + + PseudoVLSEG2E32FF_V_MF2_MASK = 6242 + + PseudoVLSEG2E32_V_M1 = 6243 + + PseudoVLSEG2E32_V_M1_MASK = 6244 + + PseudoVLSEG2E32_V_M2 = 6245 + + PseudoVLSEG2E32_V_M2_MASK = 6246 + + PseudoVLSEG2E32_V_M4 = 6247 + + PseudoVLSEG2E32_V_M4_MASK = 6248 + + PseudoVLSEG2E32_V_MF2 = 6249 + + PseudoVLSEG2E32_V_MF2_MASK = 6250 + + PseudoVLSEG2E64FF_V_M1 = 6251 + + PseudoVLSEG2E64FF_V_M1_MASK = 6252 + + PseudoVLSEG2E64FF_V_M2 = 6253 + + PseudoVLSEG2E64FF_V_M2_MASK = 6254 + + PseudoVLSEG2E64FF_V_M4 = 6255 + + PseudoVLSEG2E64FF_V_M4_MASK = 6256 + + PseudoVLSEG2E64_V_M1 = 6257 + + PseudoVLSEG2E64_V_M1_MASK = 6258 + + PseudoVLSEG2E64_V_M2 = 6259 + + PseudoVLSEG2E64_V_M2_MASK = 6260 + + PseudoVLSEG2E64_V_M4 = 6261 + + PseudoVLSEG2E64_V_M4_MASK = 6262 + + PseudoVLSEG2E8FF_V_M1 = 6263 + + PseudoVLSEG2E8FF_V_M1_MASK = 6264 + + PseudoVLSEG2E8FF_V_M2 = 6265 + + PseudoVLSEG2E8FF_V_M2_MASK = 6266 + + PseudoVLSEG2E8FF_V_M4 = 6267 + + PseudoVLSEG2E8FF_V_M4_MASK = 6268 + + PseudoVLSEG2E8FF_V_MF2 = 6269 + + PseudoVLSEG2E8FF_V_MF2_MASK = 6270 + + PseudoVLSEG2E8FF_V_MF4 = 6271 + + PseudoVLSEG2E8FF_V_MF4_MASK = 6272 + + PseudoVLSEG2E8FF_V_MF8 = 6273 + + PseudoVLSEG2E8FF_V_MF8_MASK = 6274 + + PseudoVLSEG2E8_V_M1 = 6275 + + PseudoVLSEG2E8_V_M1_MASK = 6276 + + PseudoVLSEG2E8_V_M2 = 6277 + + PseudoVLSEG2E8_V_M2_MASK = 6278 + + PseudoVLSEG2E8_V_M4 = 6279 + + PseudoVLSEG2E8_V_M4_MASK = 6280 + + PseudoVLSEG2E8_V_MF2 = 6281 + + PseudoVLSEG2E8_V_MF2_MASK = 6282 + + PseudoVLSEG2E8_V_MF4 = 6283 + + PseudoVLSEG2E8_V_MF4_MASK = 6284 + + PseudoVLSEG2E8_V_MF8 = 6285 + + PseudoVLSEG2E8_V_MF8_MASK = 6286 + + PseudoVLSEG3E16FF_V_M1 = 6287 + + PseudoVLSEG3E16FF_V_M1_MASK = 6288 + + PseudoVLSEG3E16FF_V_M2 = 6289 + + PseudoVLSEG3E16FF_V_M2_MASK = 6290 + + PseudoVLSEG3E16FF_V_MF2 = 6291 + + PseudoVLSEG3E16FF_V_MF2_MASK = 6292 + + PseudoVLSEG3E16FF_V_MF4 = 6293 + + PseudoVLSEG3E16FF_V_MF4_MASK = 6294 + + PseudoVLSEG3E16_V_M1 = 6295 + + PseudoVLSEG3E16_V_M1_MASK = 6296 + + PseudoVLSEG3E16_V_M2 = 6297 + + PseudoVLSEG3E16_V_M2_MASK = 6298 + + PseudoVLSEG3E16_V_MF2 = 6299 + + PseudoVLSEG3E16_V_MF2_MASK = 6300 + + PseudoVLSEG3E16_V_MF4 = 6301 + + PseudoVLSEG3E16_V_MF4_MASK = 6302 + + PseudoVLSEG3E32FF_V_M1 = 6303 + + PseudoVLSEG3E32FF_V_M1_MASK = 6304 + + PseudoVLSEG3E32FF_V_M2 = 6305 + + PseudoVLSEG3E32FF_V_M2_MASK = 6306 + + PseudoVLSEG3E32FF_V_MF2 = 6307 + + PseudoVLSEG3E32FF_V_MF2_MASK = 6308 + + PseudoVLSEG3E32_V_M1 = 6309 + + PseudoVLSEG3E32_V_M1_MASK = 6310 + + PseudoVLSEG3E32_V_M2 = 6311 + + PseudoVLSEG3E32_V_M2_MASK = 6312 + + PseudoVLSEG3E32_V_MF2 = 6313 + + PseudoVLSEG3E32_V_MF2_MASK = 6314 + + PseudoVLSEG3E64FF_V_M1 = 6315 + + PseudoVLSEG3E64FF_V_M1_MASK = 6316 + + PseudoVLSEG3E64FF_V_M2 = 6317 + + PseudoVLSEG3E64FF_V_M2_MASK = 6318 + + PseudoVLSEG3E64_V_M1 = 6319 + + PseudoVLSEG3E64_V_M1_MASK = 6320 + + PseudoVLSEG3E64_V_M2 = 6321 + + PseudoVLSEG3E64_V_M2_MASK = 6322 + + PseudoVLSEG3E8FF_V_M1 = 6323 + + PseudoVLSEG3E8FF_V_M1_MASK = 6324 + + PseudoVLSEG3E8FF_V_M2 = 6325 + + PseudoVLSEG3E8FF_V_M2_MASK = 6326 + + PseudoVLSEG3E8FF_V_MF2 = 6327 + + PseudoVLSEG3E8FF_V_MF2_MASK = 6328 + + PseudoVLSEG3E8FF_V_MF4 = 6329 + + PseudoVLSEG3E8FF_V_MF4_MASK = 6330 + + PseudoVLSEG3E8FF_V_MF8 = 6331 + + PseudoVLSEG3E8FF_V_MF8_MASK = 6332 + + PseudoVLSEG3E8_V_M1 = 6333 + + PseudoVLSEG3E8_V_M1_MASK = 6334 + + PseudoVLSEG3E8_V_M2 = 6335 + + PseudoVLSEG3E8_V_M2_MASK = 6336 + + PseudoVLSEG3E8_V_MF2 = 6337 + + PseudoVLSEG3E8_V_MF2_MASK = 6338 + + PseudoVLSEG3E8_V_MF4 = 6339 + + PseudoVLSEG3E8_V_MF4_MASK = 6340 + + PseudoVLSEG3E8_V_MF8 = 6341 + + PseudoVLSEG3E8_V_MF8_MASK = 6342 + + PseudoVLSEG4E16FF_V_M1 = 6343 + + PseudoVLSEG4E16FF_V_M1_MASK = 6344 + + PseudoVLSEG4E16FF_V_M2 = 6345 + + PseudoVLSEG4E16FF_V_M2_MASK = 6346 + + PseudoVLSEG4E16FF_V_MF2 = 6347 + + PseudoVLSEG4E16FF_V_MF2_MASK = 6348 + + PseudoVLSEG4E16FF_V_MF4 = 6349 + + PseudoVLSEG4E16FF_V_MF4_MASK = 6350 + + PseudoVLSEG4E16_V_M1 = 6351 + + PseudoVLSEG4E16_V_M1_MASK = 6352 + + PseudoVLSEG4E16_V_M2 = 6353 + + PseudoVLSEG4E16_V_M2_MASK = 6354 + + PseudoVLSEG4E16_V_MF2 = 6355 + + PseudoVLSEG4E16_V_MF2_MASK = 6356 + + PseudoVLSEG4E16_V_MF4 = 6357 + + PseudoVLSEG4E16_V_MF4_MASK = 6358 + + PseudoVLSEG4E32FF_V_M1 = 6359 + + PseudoVLSEG4E32FF_V_M1_MASK = 6360 + + PseudoVLSEG4E32FF_V_M2 = 6361 + + PseudoVLSEG4E32FF_V_M2_MASK = 6362 + + PseudoVLSEG4E32FF_V_MF2 = 6363 + + PseudoVLSEG4E32FF_V_MF2_MASK = 6364 + + PseudoVLSEG4E32_V_M1 = 6365 + + PseudoVLSEG4E32_V_M1_MASK = 6366 + + PseudoVLSEG4E32_V_M2 = 6367 + + PseudoVLSEG4E32_V_M2_MASK = 6368 + + PseudoVLSEG4E32_V_MF2 = 6369 + + PseudoVLSEG4E32_V_MF2_MASK = 6370 + + PseudoVLSEG4E64FF_V_M1 = 6371 + + PseudoVLSEG4E64FF_V_M1_MASK = 6372 + + PseudoVLSEG4E64FF_V_M2 = 6373 + + PseudoVLSEG4E64FF_V_M2_MASK = 6374 + + PseudoVLSEG4E64_V_M1 = 6375 + + PseudoVLSEG4E64_V_M1_MASK = 6376 + + PseudoVLSEG4E64_V_M2 = 6377 + + PseudoVLSEG4E64_V_M2_MASK = 6378 + + PseudoVLSEG4E8FF_V_M1 = 6379 + + PseudoVLSEG4E8FF_V_M1_MASK = 6380 + + PseudoVLSEG4E8FF_V_M2 = 6381 + + PseudoVLSEG4E8FF_V_M2_MASK = 6382 + + PseudoVLSEG4E8FF_V_MF2 = 6383 + + PseudoVLSEG4E8FF_V_MF2_MASK = 6384 + + PseudoVLSEG4E8FF_V_MF4 = 6385 + + PseudoVLSEG4E8FF_V_MF4_MASK = 6386 + + PseudoVLSEG4E8FF_V_MF8 = 6387 + + PseudoVLSEG4E8FF_V_MF8_MASK = 6388 + + PseudoVLSEG4E8_V_M1 = 6389 + + PseudoVLSEG4E8_V_M1_MASK = 6390 + + PseudoVLSEG4E8_V_M2 = 6391 + + PseudoVLSEG4E8_V_M2_MASK = 6392 + + PseudoVLSEG4E8_V_MF2 = 6393 + + PseudoVLSEG4E8_V_MF2_MASK = 6394 + + PseudoVLSEG4E8_V_MF4 = 6395 + + PseudoVLSEG4E8_V_MF4_MASK = 6396 + + PseudoVLSEG4E8_V_MF8 = 6397 + + PseudoVLSEG4E8_V_MF8_MASK = 6398 + + PseudoVLSEG5E16FF_V_M1 = 6399 + + PseudoVLSEG5E16FF_V_M1_MASK = 6400 + + PseudoVLSEG5E16FF_V_MF2 = 6401 + + PseudoVLSEG5E16FF_V_MF2_MASK = 6402 + + PseudoVLSEG5E16FF_V_MF4 = 6403 + + PseudoVLSEG5E16FF_V_MF4_MASK = 6404 + + PseudoVLSEG5E16_V_M1 = 6405 + + PseudoVLSEG5E16_V_M1_MASK = 6406 + + PseudoVLSEG5E16_V_MF2 = 6407 + + PseudoVLSEG5E16_V_MF2_MASK = 6408 + + PseudoVLSEG5E16_V_MF4 = 6409 + + PseudoVLSEG5E16_V_MF4_MASK = 6410 + + PseudoVLSEG5E32FF_V_M1 = 6411 + + PseudoVLSEG5E32FF_V_M1_MASK = 6412 + + PseudoVLSEG5E32FF_V_MF2 = 6413 + + PseudoVLSEG5E32FF_V_MF2_MASK = 6414 + + PseudoVLSEG5E32_V_M1 = 6415 + + PseudoVLSEG5E32_V_M1_MASK = 6416 + + PseudoVLSEG5E32_V_MF2 = 6417 + + PseudoVLSEG5E32_V_MF2_MASK = 6418 + + PseudoVLSEG5E64FF_V_M1 = 6419 + + PseudoVLSEG5E64FF_V_M1_MASK = 6420 + + PseudoVLSEG5E64_V_M1 = 6421 + + PseudoVLSEG5E64_V_M1_MASK = 6422 + + PseudoVLSEG5E8FF_V_M1 = 6423 + + PseudoVLSEG5E8FF_V_M1_MASK = 6424 + + PseudoVLSEG5E8FF_V_MF2 = 6425 + + PseudoVLSEG5E8FF_V_MF2_MASK = 6426 + + PseudoVLSEG5E8FF_V_MF4 = 6427 + + PseudoVLSEG5E8FF_V_MF4_MASK = 6428 + + PseudoVLSEG5E8FF_V_MF8 = 6429 + + PseudoVLSEG5E8FF_V_MF8_MASK = 6430 + + PseudoVLSEG5E8_V_M1 = 6431 + + PseudoVLSEG5E8_V_M1_MASK = 6432 + + PseudoVLSEG5E8_V_MF2 = 6433 + + PseudoVLSEG5E8_V_MF2_MASK = 6434 + + PseudoVLSEG5E8_V_MF4 = 6435 + + PseudoVLSEG5E8_V_MF4_MASK = 6436 + + PseudoVLSEG5E8_V_MF8 = 6437 + + PseudoVLSEG5E8_V_MF8_MASK = 6438 + + PseudoVLSEG6E16FF_V_M1 = 6439 + + PseudoVLSEG6E16FF_V_M1_MASK = 6440 + + PseudoVLSEG6E16FF_V_MF2 = 6441 + + PseudoVLSEG6E16FF_V_MF2_MASK = 6442 + + PseudoVLSEG6E16FF_V_MF4 = 6443 + + PseudoVLSEG6E16FF_V_MF4_MASK = 6444 + + PseudoVLSEG6E16_V_M1 = 6445 + + PseudoVLSEG6E16_V_M1_MASK = 6446 + + PseudoVLSEG6E16_V_MF2 = 6447 + + PseudoVLSEG6E16_V_MF2_MASK = 6448 + + PseudoVLSEG6E16_V_MF4 = 6449 + + PseudoVLSEG6E16_V_MF4_MASK = 6450 + + PseudoVLSEG6E32FF_V_M1 = 6451 + + PseudoVLSEG6E32FF_V_M1_MASK = 6452 + + PseudoVLSEG6E32FF_V_MF2 = 6453 + + PseudoVLSEG6E32FF_V_MF2_MASK = 6454 + + PseudoVLSEG6E32_V_M1 = 6455 + + PseudoVLSEG6E32_V_M1_MASK = 6456 + + PseudoVLSEG6E32_V_MF2 = 6457 + + PseudoVLSEG6E32_V_MF2_MASK = 6458 + + PseudoVLSEG6E64FF_V_M1 = 6459 + + PseudoVLSEG6E64FF_V_M1_MASK = 6460 + + PseudoVLSEG6E64_V_M1 = 6461 + + PseudoVLSEG6E64_V_M1_MASK = 6462 + + PseudoVLSEG6E8FF_V_M1 = 6463 + + PseudoVLSEG6E8FF_V_M1_MASK = 6464 + + PseudoVLSEG6E8FF_V_MF2 = 6465 + + PseudoVLSEG6E8FF_V_MF2_MASK = 6466 + + PseudoVLSEG6E8FF_V_MF4 = 6467 + + PseudoVLSEG6E8FF_V_MF4_MASK = 6468 + + PseudoVLSEG6E8FF_V_MF8 = 6469 + + PseudoVLSEG6E8FF_V_MF8_MASK = 6470 + + PseudoVLSEG6E8_V_M1 = 6471 + + PseudoVLSEG6E8_V_M1_MASK = 6472 + + PseudoVLSEG6E8_V_MF2 = 6473 + + PseudoVLSEG6E8_V_MF2_MASK = 6474 + + PseudoVLSEG6E8_V_MF4 = 6475 + + PseudoVLSEG6E8_V_MF4_MASK = 6476 + + PseudoVLSEG6E8_V_MF8 = 6477 + + PseudoVLSEG6E8_V_MF8_MASK = 6478 + + PseudoVLSEG7E16FF_V_M1 = 6479 + + PseudoVLSEG7E16FF_V_M1_MASK = 6480 + + PseudoVLSEG7E16FF_V_MF2 = 6481 + + PseudoVLSEG7E16FF_V_MF2_MASK = 6482 + + PseudoVLSEG7E16FF_V_MF4 = 6483 + + PseudoVLSEG7E16FF_V_MF4_MASK = 6484 + + PseudoVLSEG7E16_V_M1 = 6485 + + PseudoVLSEG7E16_V_M1_MASK = 6486 + + PseudoVLSEG7E16_V_MF2 = 6487 + + PseudoVLSEG7E16_V_MF2_MASK = 6488 + + PseudoVLSEG7E16_V_MF4 = 6489 + + PseudoVLSEG7E16_V_MF4_MASK = 6490 + + PseudoVLSEG7E32FF_V_M1 = 6491 + + PseudoVLSEG7E32FF_V_M1_MASK = 6492 + + PseudoVLSEG7E32FF_V_MF2 = 6493 + + PseudoVLSEG7E32FF_V_MF2_MASK = 6494 + + PseudoVLSEG7E32_V_M1 = 6495 + + PseudoVLSEG7E32_V_M1_MASK = 6496 + + PseudoVLSEG7E32_V_MF2 = 6497 + + PseudoVLSEG7E32_V_MF2_MASK = 6498 + + PseudoVLSEG7E64FF_V_M1 = 6499 + + PseudoVLSEG7E64FF_V_M1_MASK = 6500 + + PseudoVLSEG7E64_V_M1 = 6501 + + PseudoVLSEG7E64_V_M1_MASK = 6502 + + PseudoVLSEG7E8FF_V_M1 = 6503 + + PseudoVLSEG7E8FF_V_M1_MASK = 6504 + + PseudoVLSEG7E8FF_V_MF2 = 6505 + + PseudoVLSEG7E8FF_V_MF2_MASK = 6506 + + PseudoVLSEG7E8FF_V_MF4 = 6507 + + PseudoVLSEG7E8FF_V_MF4_MASK = 6508 + + PseudoVLSEG7E8FF_V_MF8 = 6509 + + PseudoVLSEG7E8FF_V_MF8_MASK = 6510 + + PseudoVLSEG7E8_V_M1 = 6511 + + PseudoVLSEG7E8_V_M1_MASK = 6512 + + PseudoVLSEG7E8_V_MF2 = 6513 + + PseudoVLSEG7E8_V_MF2_MASK = 6514 + + PseudoVLSEG7E8_V_MF4 = 6515 + + PseudoVLSEG7E8_V_MF4_MASK = 6516 + + PseudoVLSEG7E8_V_MF8 = 6517 + + PseudoVLSEG7E8_V_MF8_MASK = 6518 + + PseudoVLSEG8E16FF_V_M1 = 6519 + + PseudoVLSEG8E16FF_V_M1_MASK = 6520 + + PseudoVLSEG8E16FF_V_MF2 = 6521 + + PseudoVLSEG8E16FF_V_MF2_MASK = 6522 + + PseudoVLSEG8E16FF_V_MF4 = 6523 + + PseudoVLSEG8E16FF_V_MF4_MASK = 6524 + + PseudoVLSEG8E16_V_M1 = 6525 + + PseudoVLSEG8E16_V_M1_MASK = 6526 + + PseudoVLSEG8E16_V_MF2 = 6527 + + PseudoVLSEG8E16_V_MF2_MASK = 6528 + + PseudoVLSEG8E16_V_MF4 = 6529 + + PseudoVLSEG8E16_V_MF4_MASK = 6530 + + PseudoVLSEG8E32FF_V_M1 = 6531 + + PseudoVLSEG8E32FF_V_M1_MASK = 6532 + + PseudoVLSEG8E32FF_V_MF2 = 6533 + + PseudoVLSEG8E32FF_V_MF2_MASK = 6534 + + PseudoVLSEG8E32_V_M1 = 6535 + + PseudoVLSEG8E32_V_M1_MASK = 6536 + + PseudoVLSEG8E32_V_MF2 = 6537 + + PseudoVLSEG8E32_V_MF2_MASK = 6538 + + PseudoVLSEG8E64FF_V_M1 = 6539 + + PseudoVLSEG8E64FF_V_M1_MASK = 6540 + + PseudoVLSEG8E64_V_M1 = 6541 + + PseudoVLSEG8E64_V_M1_MASK = 6542 + + PseudoVLSEG8E8FF_V_M1 = 6543 + + PseudoVLSEG8E8FF_V_M1_MASK = 6544 + + PseudoVLSEG8E8FF_V_MF2 = 6545 + + PseudoVLSEG8E8FF_V_MF2_MASK = 6546 + + PseudoVLSEG8E8FF_V_MF4 = 6547 + + PseudoVLSEG8E8FF_V_MF4_MASK = 6548 + + PseudoVLSEG8E8FF_V_MF8 = 6549 + + PseudoVLSEG8E8FF_V_MF8_MASK = 6550 + + PseudoVLSEG8E8_V_M1 = 6551 + + PseudoVLSEG8E8_V_M1_MASK = 6552 + + PseudoVLSEG8E8_V_MF2 = 6553 + + PseudoVLSEG8E8_V_MF2_MASK = 6554 + + PseudoVLSEG8E8_V_MF4 = 6555 + + PseudoVLSEG8E8_V_MF4_MASK = 6556 + + PseudoVLSEG8E8_V_MF8 = 6557 + + PseudoVLSEG8E8_V_MF8_MASK = 6558 + + PseudoVLSSEG2E16_V_M1 = 6559 + + PseudoVLSSEG2E16_V_M1_MASK = 6560 + + PseudoVLSSEG2E16_V_M2 = 6561 + + PseudoVLSSEG2E16_V_M2_MASK = 6562 + + PseudoVLSSEG2E16_V_M4 = 6563 + + PseudoVLSSEG2E16_V_M4_MASK = 6564 + + PseudoVLSSEG2E16_V_MF2 = 6565 + + PseudoVLSSEG2E16_V_MF2_MASK = 6566 + + PseudoVLSSEG2E16_V_MF4 = 6567 + + PseudoVLSSEG2E16_V_MF4_MASK = 6568 + + PseudoVLSSEG2E32_V_M1 = 6569 + + PseudoVLSSEG2E32_V_M1_MASK = 6570 + + PseudoVLSSEG2E32_V_M2 = 6571 + + PseudoVLSSEG2E32_V_M2_MASK = 6572 + + PseudoVLSSEG2E32_V_M4 = 6573 + + PseudoVLSSEG2E32_V_M4_MASK = 6574 + + PseudoVLSSEG2E32_V_MF2 = 6575 + + PseudoVLSSEG2E32_V_MF2_MASK = 6576 + + PseudoVLSSEG2E64_V_M1 = 6577 + + PseudoVLSSEG2E64_V_M1_MASK = 6578 + + PseudoVLSSEG2E64_V_M2 = 6579 + + PseudoVLSSEG2E64_V_M2_MASK = 6580 + + PseudoVLSSEG2E64_V_M4 = 6581 + + PseudoVLSSEG2E64_V_M4_MASK = 6582 + + PseudoVLSSEG2E8_V_M1 = 6583 + + PseudoVLSSEG2E8_V_M1_MASK = 6584 + + PseudoVLSSEG2E8_V_M2 = 6585 + + PseudoVLSSEG2E8_V_M2_MASK = 6586 + + PseudoVLSSEG2E8_V_M4 = 6587 + + PseudoVLSSEG2E8_V_M4_MASK = 6588 + + PseudoVLSSEG2E8_V_MF2 = 6589 + + PseudoVLSSEG2E8_V_MF2_MASK = 6590 + + PseudoVLSSEG2E8_V_MF4 = 6591 + + PseudoVLSSEG2E8_V_MF4_MASK = 6592 + + PseudoVLSSEG2E8_V_MF8 = 6593 + + PseudoVLSSEG2E8_V_MF8_MASK = 6594 + + PseudoVLSSEG3E16_V_M1 = 6595 + + PseudoVLSSEG3E16_V_M1_MASK = 6596 + + PseudoVLSSEG3E16_V_M2 = 6597 + + PseudoVLSSEG3E16_V_M2_MASK = 6598 + + PseudoVLSSEG3E16_V_MF2 = 6599 + + PseudoVLSSEG3E16_V_MF2_MASK = 6600 + + PseudoVLSSEG3E16_V_MF4 = 6601 + + PseudoVLSSEG3E16_V_MF4_MASK = 6602 + + PseudoVLSSEG3E32_V_M1 = 6603 + + PseudoVLSSEG3E32_V_M1_MASK = 6604 + + PseudoVLSSEG3E32_V_M2 = 6605 + + PseudoVLSSEG3E32_V_M2_MASK = 6606 + + PseudoVLSSEG3E32_V_MF2 = 6607 + + PseudoVLSSEG3E32_V_MF2_MASK = 6608 + + PseudoVLSSEG3E64_V_M1 = 6609 + + PseudoVLSSEG3E64_V_M1_MASK = 6610 + + PseudoVLSSEG3E64_V_M2 = 6611 + + PseudoVLSSEG3E64_V_M2_MASK = 6612 + + PseudoVLSSEG3E8_V_M1 = 6613 + + PseudoVLSSEG3E8_V_M1_MASK = 6614 + + PseudoVLSSEG3E8_V_M2 = 6615 + + PseudoVLSSEG3E8_V_M2_MASK = 6616 + + PseudoVLSSEG3E8_V_MF2 = 6617 + + PseudoVLSSEG3E8_V_MF2_MASK = 6618 + + PseudoVLSSEG3E8_V_MF4 = 6619 + + PseudoVLSSEG3E8_V_MF4_MASK = 6620 + + PseudoVLSSEG3E8_V_MF8 = 6621 + + PseudoVLSSEG3E8_V_MF8_MASK = 6622 + + PseudoVLSSEG4E16_V_M1 = 6623 + + PseudoVLSSEG4E16_V_M1_MASK = 6624 + + PseudoVLSSEG4E16_V_M2 = 6625 + + PseudoVLSSEG4E16_V_M2_MASK = 6626 + + PseudoVLSSEG4E16_V_MF2 = 6627 + + PseudoVLSSEG4E16_V_MF2_MASK = 6628 + + PseudoVLSSEG4E16_V_MF4 = 6629 + + PseudoVLSSEG4E16_V_MF4_MASK = 6630 + + PseudoVLSSEG4E32_V_M1 = 6631 + + PseudoVLSSEG4E32_V_M1_MASK = 6632 + + PseudoVLSSEG4E32_V_M2 = 6633 + + PseudoVLSSEG4E32_V_M2_MASK = 6634 + + PseudoVLSSEG4E32_V_MF2 = 6635 + + PseudoVLSSEG4E32_V_MF2_MASK = 6636 + + PseudoVLSSEG4E64_V_M1 = 6637 + + PseudoVLSSEG4E64_V_M1_MASK = 6638 + + PseudoVLSSEG4E64_V_M2 = 6639 + + PseudoVLSSEG4E64_V_M2_MASK = 6640 + + PseudoVLSSEG4E8_V_M1 = 6641 + + PseudoVLSSEG4E8_V_M1_MASK = 6642 + + PseudoVLSSEG4E8_V_M2 = 6643 + + PseudoVLSSEG4E8_V_M2_MASK = 6644 + + PseudoVLSSEG4E8_V_MF2 = 6645 + + PseudoVLSSEG4E8_V_MF2_MASK = 6646 + + PseudoVLSSEG4E8_V_MF4 = 6647 + + PseudoVLSSEG4E8_V_MF4_MASK = 6648 + + PseudoVLSSEG4E8_V_MF8 = 6649 + + PseudoVLSSEG4E8_V_MF8_MASK = 6650 + + PseudoVLSSEG5E16_V_M1 = 6651 + + PseudoVLSSEG5E16_V_M1_MASK = 6652 + + PseudoVLSSEG5E16_V_MF2 = 6653 + + PseudoVLSSEG5E16_V_MF2_MASK = 6654 + + PseudoVLSSEG5E16_V_MF4 = 6655 + + PseudoVLSSEG5E16_V_MF4_MASK = 6656 + + PseudoVLSSEG5E32_V_M1 = 6657 + + PseudoVLSSEG5E32_V_M1_MASK = 6658 + + PseudoVLSSEG5E32_V_MF2 = 6659 + + PseudoVLSSEG5E32_V_MF2_MASK = 6660 + + PseudoVLSSEG5E64_V_M1 = 6661 + + PseudoVLSSEG5E64_V_M1_MASK = 6662 + + PseudoVLSSEG5E8_V_M1 = 6663 + + PseudoVLSSEG5E8_V_M1_MASK = 6664 + + PseudoVLSSEG5E8_V_MF2 = 6665 + + PseudoVLSSEG5E8_V_MF2_MASK = 6666 + + PseudoVLSSEG5E8_V_MF4 = 6667 + + PseudoVLSSEG5E8_V_MF4_MASK = 6668 + + PseudoVLSSEG5E8_V_MF8 = 6669 + + PseudoVLSSEG5E8_V_MF8_MASK = 6670 + + PseudoVLSSEG6E16_V_M1 = 6671 + + PseudoVLSSEG6E16_V_M1_MASK = 6672 + + PseudoVLSSEG6E16_V_MF2 = 6673 + + PseudoVLSSEG6E16_V_MF2_MASK = 6674 + + PseudoVLSSEG6E16_V_MF4 = 6675 + + PseudoVLSSEG6E16_V_MF4_MASK = 6676 + + PseudoVLSSEG6E32_V_M1 = 6677 + + PseudoVLSSEG6E32_V_M1_MASK = 6678 + + PseudoVLSSEG6E32_V_MF2 = 6679 + + PseudoVLSSEG6E32_V_MF2_MASK = 6680 + + PseudoVLSSEG6E64_V_M1 = 6681 + + PseudoVLSSEG6E64_V_M1_MASK = 6682 + + PseudoVLSSEG6E8_V_M1 = 6683 + + PseudoVLSSEG6E8_V_M1_MASK = 6684 + + PseudoVLSSEG6E8_V_MF2 = 6685 + + PseudoVLSSEG6E8_V_MF2_MASK = 6686 + + PseudoVLSSEG6E8_V_MF4 = 6687 + + PseudoVLSSEG6E8_V_MF4_MASK = 6688 + + PseudoVLSSEG6E8_V_MF8 = 6689 + + PseudoVLSSEG6E8_V_MF8_MASK = 6690 + + PseudoVLSSEG7E16_V_M1 = 6691 + + PseudoVLSSEG7E16_V_M1_MASK = 6692 + + PseudoVLSSEG7E16_V_MF2 = 6693 + + PseudoVLSSEG7E16_V_MF2_MASK = 6694 + + PseudoVLSSEG7E16_V_MF4 = 6695 + + PseudoVLSSEG7E16_V_MF4_MASK = 6696 + + PseudoVLSSEG7E32_V_M1 = 6697 + + PseudoVLSSEG7E32_V_M1_MASK = 6698 + + PseudoVLSSEG7E32_V_MF2 = 6699 + + PseudoVLSSEG7E32_V_MF2_MASK = 6700 + + PseudoVLSSEG7E64_V_M1 = 6701 + + PseudoVLSSEG7E64_V_M1_MASK = 6702 + + PseudoVLSSEG7E8_V_M1 = 6703 + + PseudoVLSSEG7E8_V_M1_MASK = 6704 + + PseudoVLSSEG7E8_V_MF2 = 6705 + + PseudoVLSSEG7E8_V_MF2_MASK = 6706 + + PseudoVLSSEG7E8_V_MF4 = 6707 + + PseudoVLSSEG7E8_V_MF4_MASK = 6708 + + PseudoVLSSEG7E8_V_MF8 = 6709 + + PseudoVLSSEG7E8_V_MF8_MASK = 6710 + + PseudoVLSSEG8E16_V_M1 = 6711 + + PseudoVLSSEG8E16_V_M1_MASK = 6712 + + PseudoVLSSEG8E16_V_MF2 = 6713 + + PseudoVLSSEG8E16_V_MF2_MASK = 6714 + + PseudoVLSSEG8E16_V_MF4 = 6715 + + PseudoVLSSEG8E16_V_MF4_MASK = 6716 + + PseudoVLSSEG8E32_V_M1 = 6717 + + PseudoVLSSEG8E32_V_M1_MASK = 6718 + + PseudoVLSSEG8E32_V_MF2 = 6719 + + PseudoVLSSEG8E32_V_MF2_MASK = 6720 + + PseudoVLSSEG8E64_V_M1 = 6721 + + PseudoVLSSEG8E64_V_M1_MASK = 6722 + + PseudoVLSSEG8E8_V_M1 = 6723 + + PseudoVLSSEG8E8_V_M1_MASK = 6724 + + PseudoVLSSEG8E8_V_MF2 = 6725 + + PseudoVLSSEG8E8_V_MF2_MASK = 6726 + + PseudoVLSSEG8E8_V_MF4 = 6727 + + PseudoVLSSEG8E8_V_MF4_MASK = 6728 + + PseudoVLSSEG8E8_V_MF8 = 6729 + + PseudoVLSSEG8E8_V_MF8_MASK = 6730 + + PseudoVLUXEI16_V_M1_M1 = 6731 + + PseudoVLUXEI16_V_M1_M1_MASK = 6732 + + PseudoVLUXEI16_V_M1_M2 = 6733 + + PseudoVLUXEI16_V_M1_M2_MASK = 6734 + + PseudoVLUXEI16_V_M1_M4 = 6735 + + PseudoVLUXEI16_V_M1_M4_MASK = 6736 + + PseudoVLUXEI16_V_M1_MF2 = 6737 + + PseudoVLUXEI16_V_M1_MF2_MASK = 6738 + + PseudoVLUXEI16_V_M2_M1 = 6739 + + PseudoVLUXEI16_V_M2_M1_MASK = 6740 + + PseudoVLUXEI16_V_M2_M2 = 6741 + + PseudoVLUXEI16_V_M2_M2_MASK = 6742 + + PseudoVLUXEI16_V_M2_M4 = 6743 + + PseudoVLUXEI16_V_M2_M4_MASK = 6744 + + PseudoVLUXEI16_V_M2_M8 = 6745 + + PseudoVLUXEI16_V_M2_M8_MASK = 6746 + + PseudoVLUXEI16_V_M4_M2 = 6747 + + PseudoVLUXEI16_V_M4_M2_MASK = 6748 + + PseudoVLUXEI16_V_M4_M4 = 6749 + + PseudoVLUXEI16_V_M4_M4_MASK = 6750 + + PseudoVLUXEI16_V_M4_M8 = 6751 + + PseudoVLUXEI16_V_M4_M8_MASK = 6752 + + PseudoVLUXEI16_V_M8_M4 = 6753 + + PseudoVLUXEI16_V_M8_M4_MASK = 6754 + + PseudoVLUXEI16_V_M8_M8 = 6755 + + PseudoVLUXEI16_V_M8_M8_MASK = 6756 + + PseudoVLUXEI16_V_MF2_M1 = 6757 + + PseudoVLUXEI16_V_MF2_M1_MASK = 6758 + + PseudoVLUXEI16_V_MF2_M2 = 6759 + + PseudoVLUXEI16_V_MF2_M2_MASK = 6760 + + PseudoVLUXEI16_V_MF2_MF2 = 6761 + + PseudoVLUXEI16_V_MF2_MF2_MASK = 6762 + + PseudoVLUXEI16_V_MF2_MF4 = 6763 + + PseudoVLUXEI16_V_MF2_MF4_MASK = 6764 + + PseudoVLUXEI16_V_MF4_M1 = 6765 + + PseudoVLUXEI16_V_MF4_M1_MASK = 6766 + + PseudoVLUXEI16_V_MF4_MF2 = 6767 + + PseudoVLUXEI16_V_MF4_MF2_MASK = 6768 + + PseudoVLUXEI16_V_MF4_MF4 = 6769 + + PseudoVLUXEI16_V_MF4_MF4_MASK = 6770 + + PseudoVLUXEI16_V_MF4_MF8 = 6771 + + PseudoVLUXEI16_V_MF4_MF8_MASK = 6772 + + PseudoVLUXEI32_V_M1_M1 = 6773 + + PseudoVLUXEI32_V_M1_M1_MASK = 6774 + + PseudoVLUXEI32_V_M1_M2 = 6775 + + PseudoVLUXEI32_V_M1_M2_MASK = 6776 + + PseudoVLUXEI32_V_M1_MF2 = 6777 + + PseudoVLUXEI32_V_M1_MF2_MASK = 6778 + + PseudoVLUXEI32_V_M1_MF4 = 6779 + + PseudoVLUXEI32_V_M1_MF4_MASK = 6780 + + PseudoVLUXEI32_V_M2_M1 = 6781 + + PseudoVLUXEI32_V_M2_M1_MASK = 6782 + + PseudoVLUXEI32_V_M2_M2 = 6783 + + PseudoVLUXEI32_V_M2_M2_MASK = 6784 + + PseudoVLUXEI32_V_M2_M4 = 6785 + + PseudoVLUXEI32_V_M2_M4_MASK = 6786 + + PseudoVLUXEI32_V_M2_MF2 = 6787 + + PseudoVLUXEI32_V_M2_MF2_MASK = 6788 + + PseudoVLUXEI32_V_M4_M1 = 6789 + + PseudoVLUXEI32_V_M4_M1_MASK = 6790 + + PseudoVLUXEI32_V_M4_M2 = 6791 + + PseudoVLUXEI32_V_M4_M2_MASK = 6792 + + PseudoVLUXEI32_V_M4_M4 = 6793 + + PseudoVLUXEI32_V_M4_M4_MASK = 6794 + + PseudoVLUXEI32_V_M4_M8 = 6795 + + PseudoVLUXEI32_V_M4_M8_MASK = 6796 + + PseudoVLUXEI32_V_M8_M2 = 6797 + + PseudoVLUXEI32_V_M8_M2_MASK = 6798 + + PseudoVLUXEI32_V_M8_M4 = 6799 + + PseudoVLUXEI32_V_M8_M4_MASK = 6800 + + PseudoVLUXEI32_V_M8_M8 = 6801 + + PseudoVLUXEI32_V_M8_M8_MASK = 6802 + + PseudoVLUXEI32_V_MF2_M1 = 6803 + + PseudoVLUXEI32_V_MF2_M1_MASK = 6804 + + PseudoVLUXEI32_V_MF2_MF2 = 6805 + + PseudoVLUXEI32_V_MF2_MF2_MASK = 6806 + + PseudoVLUXEI32_V_MF2_MF4 = 6807 + + PseudoVLUXEI32_V_MF2_MF4_MASK = 6808 + + PseudoVLUXEI32_V_MF2_MF8 = 6809 + + PseudoVLUXEI32_V_MF2_MF8_MASK = 6810 + + PseudoVLUXEI64_V_M1_M1 = 6811 + + PseudoVLUXEI64_V_M1_M1_MASK = 6812 + + PseudoVLUXEI64_V_M1_MF2 = 6813 + + PseudoVLUXEI64_V_M1_MF2_MASK = 6814 + + PseudoVLUXEI64_V_M1_MF4 = 6815 + + PseudoVLUXEI64_V_M1_MF4_MASK = 6816 + + PseudoVLUXEI64_V_M1_MF8 = 6817 + + PseudoVLUXEI64_V_M1_MF8_MASK = 6818 + + PseudoVLUXEI64_V_M2_M1 = 6819 + + PseudoVLUXEI64_V_M2_M1_MASK = 6820 + + PseudoVLUXEI64_V_M2_M2 = 6821 + + PseudoVLUXEI64_V_M2_M2_MASK = 6822 + + PseudoVLUXEI64_V_M2_MF2 = 6823 + + PseudoVLUXEI64_V_M2_MF2_MASK = 6824 + + PseudoVLUXEI64_V_M2_MF4 = 6825 + + PseudoVLUXEI64_V_M2_MF4_MASK = 6826 + + PseudoVLUXEI64_V_M4_M1 = 6827 + + PseudoVLUXEI64_V_M4_M1_MASK = 6828 + + PseudoVLUXEI64_V_M4_M2 = 6829 + + PseudoVLUXEI64_V_M4_M2_MASK = 6830 + + PseudoVLUXEI64_V_M4_M4 = 6831 + + PseudoVLUXEI64_V_M4_M4_MASK = 6832 + + PseudoVLUXEI64_V_M4_MF2 = 6833 + + PseudoVLUXEI64_V_M4_MF2_MASK = 6834 + + PseudoVLUXEI64_V_M8_M1 = 6835 + + PseudoVLUXEI64_V_M8_M1_MASK = 6836 + + PseudoVLUXEI64_V_M8_M2 = 6837 + + PseudoVLUXEI64_V_M8_M2_MASK = 6838 + + PseudoVLUXEI64_V_M8_M4 = 6839 + + PseudoVLUXEI64_V_M8_M4_MASK = 6840 + + PseudoVLUXEI64_V_M8_M8 = 6841 + + PseudoVLUXEI64_V_M8_M8_MASK = 6842 + + PseudoVLUXEI8_V_M1_M1 = 6843 + + PseudoVLUXEI8_V_M1_M1_MASK = 6844 + + PseudoVLUXEI8_V_M1_M2 = 6845 + + PseudoVLUXEI8_V_M1_M2_MASK = 6846 + + PseudoVLUXEI8_V_M1_M4 = 6847 + + PseudoVLUXEI8_V_M1_M4_MASK = 6848 + + PseudoVLUXEI8_V_M1_M8 = 6849 + + PseudoVLUXEI8_V_M1_M8_MASK = 6850 + + PseudoVLUXEI8_V_M2_M2 = 6851 + + PseudoVLUXEI8_V_M2_M2_MASK = 6852 + + PseudoVLUXEI8_V_M2_M4 = 6853 + + PseudoVLUXEI8_V_M2_M4_MASK = 6854 + + PseudoVLUXEI8_V_M2_M8 = 6855 + + PseudoVLUXEI8_V_M2_M8_MASK = 6856 + + PseudoVLUXEI8_V_M4_M4 = 6857 + + PseudoVLUXEI8_V_M4_M4_MASK = 6858 + + PseudoVLUXEI8_V_M4_M8 = 6859 + + PseudoVLUXEI8_V_M4_M8_MASK = 6860 + + PseudoVLUXEI8_V_M8_M8 = 6861 + + PseudoVLUXEI8_V_M8_M8_MASK = 6862 + + PseudoVLUXEI8_V_MF2_M1 = 6863 + + PseudoVLUXEI8_V_MF2_M1_MASK = 6864 + + PseudoVLUXEI8_V_MF2_M2 = 6865 + + PseudoVLUXEI8_V_MF2_M2_MASK = 6866 + + PseudoVLUXEI8_V_MF2_M4 = 6867 + + PseudoVLUXEI8_V_MF2_M4_MASK = 6868 + + PseudoVLUXEI8_V_MF2_MF2 = 6869 + + PseudoVLUXEI8_V_MF2_MF2_MASK = 6870 + + PseudoVLUXEI8_V_MF4_M1 = 6871 + + PseudoVLUXEI8_V_MF4_M1_MASK = 6872 + + PseudoVLUXEI8_V_MF4_M2 = 6873 + + PseudoVLUXEI8_V_MF4_M2_MASK = 6874 + + PseudoVLUXEI8_V_MF4_MF2 = 6875 + + PseudoVLUXEI8_V_MF4_MF2_MASK = 6876 + + PseudoVLUXEI8_V_MF4_MF4 = 6877 + + PseudoVLUXEI8_V_MF4_MF4_MASK = 6878 + + PseudoVLUXEI8_V_MF8_M1 = 6879 + + PseudoVLUXEI8_V_MF8_M1_MASK = 6880 + + PseudoVLUXEI8_V_MF8_MF2 = 6881 + + PseudoVLUXEI8_V_MF8_MF2_MASK = 6882 + + PseudoVLUXEI8_V_MF8_MF4 = 6883 + + PseudoVLUXEI8_V_MF8_MF4_MASK = 6884 + + PseudoVLUXEI8_V_MF8_MF8 = 6885 + + PseudoVLUXEI8_V_MF8_MF8_MASK = 6886 + + PseudoVLUXSEG2EI16_V_M1_M1 = 6887 + + PseudoVLUXSEG2EI16_V_M1_M1_MASK = 6888 + + PseudoVLUXSEG2EI16_V_M1_M2 = 6889 + + PseudoVLUXSEG2EI16_V_M1_M2_MASK = 6890 + + PseudoVLUXSEG2EI16_V_M1_M4 = 6891 + + PseudoVLUXSEG2EI16_V_M1_M4_MASK = 6892 + + PseudoVLUXSEG2EI16_V_M1_MF2 = 6893 + + PseudoVLUXSEG2EI16_V_M1_MF2_MASK = 6894 + + PseudoVLUXSEG2EI16_V_M2_M1 = 6895 + + PseudoVLUXSEG2EI16_V_M2_M1_MASK = 6896 + + PseudoVLUXSEG2EI16_V_M2_M2 = 6897 + + PseudoVLUXSEG2EI16_V_M2_M2_MASK = 6898 + + PseudoVLUXSEG2EI16_V_M2_M4 = 6899 + + PseudoVLUXSEG2EI16_V_M2_M4_MASK = 6900 + + PseudoVLUXSEG2EI16_V_M4_M2 = 6901 + + PseudoVLUXSEG2EI16_V_M4_M2_MASK = 6902 + + PseudoVLUXSEG2EI16_V_M4_M4 = 6903 + + PseudoVLUXSEG2EI16_V_M4_M4_MASK = 6904 + + PseudoVLUXSEG2EI16_V_M8_M4 = 6905 + + PseudoVLUXSEG2EI16_V_M8_M4_MASK = 6906 + + PseudoVLUXSEG2EI16_V_MF2_M1 = 6907 + + PseudoVLUXSEG2EI16_V_MF2_M1_MASK = 6908 + + PseudoVLUXSEG2EI16_V_MF2_M2 = 6909 + + PseudoVLUXSEG2EI16_V_MF2_M2_MASK = 6910 + + PseudoVLUXSEG2EI16_V_MF2_MF2 = 6911 + + PseudoVLUXSEG2EI16_V_MF2_MF2_MASK = 6912 + + PseudoVLUXSEG2EI16_V_MF2_MF4 = 6913 + + PseudoVLUXSEG2EI16_V_MF2_MF4_MASK = 6914 + + PseudoVLUXSEG2EI16_V_MF4_M1 = 6915 + + PseudoVLUXSEG2EI16_V_MF4_M1_MASK = 6916 + + PseudoVLUXSEG2EI16_V_MF4_MF2 = 6917 + + PseudoVLUXSEG2EI16_V_MF4_MF2_MASK = 6918 + + PseudoVLUXSEG2EI16_V_MF4_MF4 = 6919 + + PseudoVLUXSEG2EI16_V_MF4_MF4_MASK = 6920 + + PseudoVLUXSEG2EI16_V_MF4_MF8 = 6921 + + PseudoVLUXSEG2EI16_V_MF4_MF8_MASK = 6922 + + PseudoVLUXSEG2EI32_V_M1_M1 = 6923 + + PseudoVLUXSEG2EI32_V_M1_M1_MASK = 6924 + + PseudoVLUXSEG2EI32_V_M1_M2 = 6925 + + PseudoVLUXSEG2EI32_V_M1_M2_MASK = 6926 + + PseudoVLUXSEG2EI32_V_M1_MF2 = 6927 + + PseudoVLUXSEG2EI32_V_M1_MF2_MASK = 6928 + + PseudoVLUXSEG2EI32_V_M1_MF4 = 6929 + + PseudoVLUXSEG2EI32_V_M1_MF4_MASK = 6930 + + PseudoVLUXSEG2EI32_V_M2_M1 = 6931 + + PseudoVLUXSEG2EI32_V_M2_M1_MASK = 6932 + + PseudoVLUXSEG2EI32_V_M2_M2 = 6933 + + PseudoVLUXSEG2EI32_V_M2_M2_MASK = 6934 + + PseudoVLUXSEG2EI32_V_M2_M4 = 6935 + + PseudoVLUXSEG2EI32_V_M2_M4_MASK = 6936 + + PseudoVLUXSEG2EI32_V_M2_MF2 = 6937 + + PseudoVLUXSEG2EI32_V_M2_MF2_MASK = 6938 + + PseudoVLUXSEG2EI32_V_M4_M1 = 6939 + + PseudoVLUXSEG2EI32_V_M4_M1_MASK = 6940 + + PseudoVLUXSEG2EI32_V_M4_M2 = 6941 + + PseudoVLUXSEG2EI32_V_M4_M2_MASK = 6942 + + PseudoVLUXSEG2EI32_V_M4_M4 = 6943 + + PseudoVLUXSEG2EI32_V_M4_M4_MASK = 6944 + + PseudoVLUXSEG2EI32_V_M8_M2 = 6945 + + PseudoVLUXSEG2EI32_V_M8_M2_MASK = 6946 + + PseudoVLUXSEG2EI32_V_M8_M4 = 6947 + + PseudoVLUXSEG2EI32_V_M8_M4_MASK = 6948 + + PseudoVLUXSEG2EI32_V_MF2_M1 = 6949 + + PseudoVLUXSEG2EI32_V_MF2_M1_MASK = 6950 + + PseudoVLUXSEG2EI32_V_MF2_MF2 = 6951 + + PseudoVLUXSEG2EI32_V_MF2_MF2_MASK = 6952 + + PseudoVLUXSEG2EI32_V_MF2_MF4 = 6953 + + PseudoVLUXSEG2EI32_V_MF2_MF4_MASK = 6954 + + PseudoVLUXSEG2EI32_V_MF2_MF8 = 6955 + + PseudoVLUXSEG2EI32_V_MF2_MF8_MASK = 6956 + + PseudoVLUXSEG2EI64_V_M1_M1 = 6957 + + PseudoVLUXSEG2EI64_V_M1_M1_MASK = 6958 + + PseudoVLUXSEG2EI64_V_M1_MF2 = 6959 + + PseudoVLUXSEG2EI64_V_M1_MF2_MASK = 6960 + + PseudoVLUXSEG2EI64_V_M1_MF4 = 6961 + + PseudoVLUXSEG2EI64_V_M1_MF4_MASK = 6962 + + PseudoVLUXSEG2EI64_V_M1_MF8 = 6963 + + PseudoVLUXSEG2EI64_V_M1_MF8_MASK = 6964 + + PseudoVLUXSEG2EI64_V_M2_M1 = 6965 + + PseudoVLUXSEG2EI64_V_M2_M1_MASK = 6966 + + PseudoVLUXSEG2EI64_V_M2_M2 = 6967 + + PseudoVLUXSEG2EI64_V_M2_M2_MASK = 6968 + + PseudoVLUXSEG2EI64_V_M2_MF2 = 6969 + + PseudoVLUXSEG2EI64_V_M2_MF2_MASK = 6970 + + PseudoVLUXSEG2EI64_V_M2_MF4 = 6971 + + PseudoVLUXSEG2EI64_V_M2_MF4_MASK = 6972 + + PseudoVLUXSEG2EI64_V_M4_M1 = 6973 + + PseudoVLUXSEG2EI64_V_M4_M1_MASK = 6974 + + PseudoVLUXSEG2EI64_V_M4_M2 = 6975 + + PseudoVLUXSEG2EI64_V_M4_M2_MASK = 6976 + + PseudoVLUXSEG2EI64_V_M4_M4 = 6977 + + PseudoVLUXSEG2EI64_V_M4_M4_MASK = 6978 + + PseudoVLUXSEG2EI64_V_M4_MF2 = 6979 + + PseudoVLUXSEG2EI64_V_M4_MF2_MASK = 6980 + + PseudoVLUXSEG2EI64_V_M8_M1 = 6981 + + PseudoVLUXSEG2EI64_V_M8_M1_MASK = 6982 + + PseudoVLUXSEG2EI64_V_M8_M2 = 6983 + + PseudoVLUXSEG2EI64_V_M8_M2_MASK = 6984 + + PseudoVLUXSEG2EI64_V_M8_M4 = 6985 + + PseudoVLUXSEG2EI64_V_M8_M4_MASK = 6986 + + PseudoVLUXSEG2EI8_V_M1_M1 = 6987 + + PseudoVLUXSEG2EI8_V_M1_M1_MASK = 6988 + + PseudoVLUXSEG2EI8_V_M1_M2 = 6989 + + PseudoVLUXSEG2EI8_V_M1_M2_MASK = 6990 + + PseudoVLUXSEG2EI8_V_M1_M4 = 6991 + + PseudoVLUXSEG2EI8_V_M1_M4_MASK = 6992 + + PseudoVLUXSEG2EI8_V_M2_M2 = 6993 + + PseudoVLUXSEG2EI8_V_M2_M2_MASK = 6994 + + PseudoVLUXSEG2EI8_V_M2_M4 = 6995 + + PseudoVLUXSEG2EI8_V_M2_M4_MASK = 6996 + + PseudoVLUXSEG2EI8_V_M4_M4 = 6997 + + PseudoVLUXSEG2EI8_V_M4_M4_MASK = 6998 + + PseudoVLUXSEG2EI8_V_MF2_M1 = 6999 + + PseudoVLUXSEG2EI8_V_MF2_M1_MASK = 7000 + + PseudoVLUXSEG2EI8_V_MF2_M2 = 7001 + + PseudoVLUXSEG2EI8_V_MF2_M2_MASK = 7002 + + PseudoVLUXSEG2EI8_V_MF2_M4 = 7003 + + PseudoVLUXSEG2EI8_V_MF2_M4_MASK = 7004 + + PseudoVLUXSEG2EI8_V_MF2_MF2 = 7005 + + PseudoVLUXSEG2EI8_V_MF2_MF2_MASK = 7006 + + PseudoVLUXSEG2EI8_V_MF4_M1 = 7007 + + PseudoVLUXSEG2EI8_V_MF4_M1_MASK = 7008 + + PseudoVLUXSEG2EI8_V_MF4_M2 = 7009 + + PseudoVLUXSEG2EI8_V_MF4_M2_MASK = 7010 + + PseudoVLUXSEG2EI8_V_MF4_MF2 = 7011 + + PseudoVLUXSEG2EI8_V_MF4_MF2_MASK = 7012 + + PseudoVLUXSEG2EI8_V_MF4_MF4 = 7013 + + PseudoVLUXSEG2EI8_V_MF4_MF4_MASK = 7014 + + PseudoVLUXSEG2EI8_V_MF8_M1 = 7015 + + PseudoVLUXSEG2EI8_V_MF8_M1_MASK = 7016 + + PseudoVLUXSEG2EI8_V_MF8_MF2 = 7017 + + PseudoVLUXSEG2EI8_V_MF8_MF2_MASK = 7018 + + PseudoVLUXSEG2EI8_V_MF8_MF4 = 7019 + + PseudoVLUXSEG2EI8_V_MF8_MF4_MASK = 7020 + + PseudoVLUXSEG2EI8_V_MF8_MF8 = 7021 + + PseudoVLUXSEG2EI8_V_MF8_MF8_MASK = 7022 + + PseudoVLUXSEG3EI16_V_M1_M1 = 7023 + + PseudoVLUXSEG3EI16_V_M1_M1_MASK = 7024 + + PseudoVLUXSEG3EI16_V_M1_M2 = 7025 + + PseudoVLUXSEG3EI16_V_M1_M2_MASK = 7026 + + PseudoVLUXSEG3EI16_V_M1_MF2 = 7027 + + PseudoVLUXSEG3EI16_V_M1_MF2_MASK = 7028 + + PseudoVLUXSEG3EI16_V_M2_M1 = 7029 + + PseudoVLUXSEG3EI16_V_M2_M1_MASK = 7030 + + PseudoVLUXSEG3EI16_V_M2_M2 = 7031 + + PseudoVLUXSEG3EI16_V_M2_M2_MASK = 7032 + + PseudoVLUXSEG3EI16_V_M4_M2 = 7033 + + PseudoVLUXSEG3EI16_V_M4_M2_MASK = 7034 + + PseudoVLUXSEG3EI16_V_MF2_M1 = 7035 + + PseudoVLUXSEG3EI16_V_MF2_M1_MASK = 7036 + + PseudoVLUXSEG3EI16_V_MF2_M2 = 7037 + + PseudoVLUXSEG3EI16_V_MF2_M2_MASK = 7038 + + PseudoVLUXSEG3EI16_V_MF2_MF2 = 7039 + + PseudoVLUXSEG3EI16_V_MF2_MF2_MASK = 7040 + + PseudoVLUXSEG3EI16_V_MF2_MF4 = 7041 + + PseudoVLUXSEG3EI16_V_MF2_MF4_MASK = 7042 + + PseudoVLUXSEG3EI16_V_MF4_M1 = 7043 + + PseudoVLUXSEG3EI16_V_MF4_M1_MASK = 7044 + + PseudoVLUXSEG3EI16_V_MF4_MF2 = 7045 + + PseudoVLUXSEG3EI16_V_MF4_MF2_MASK = 7046 + + PseudoVLUXSEG3EI16_V_MF4_MF4 = 7047 + + PseudoVLUXSEG3EI16_V_MF4_MF4_MASK = 7048 + + PseudoVLUXSEG3EI16_V_MF4_MF8 = 7049 + + PseudoVLUXSEG3EI16_V_MF4_MF8_MASK = 7050 + + PseudoVLUXSEG3EI32_V_M1_M1 = 7051 + + PseudoVLUXSEG3EI32_V_M1_M1_MASK = 7052 + + PseudoVLUXSEG3EI32_V_M1_M2 = 7053 + + PseudoVLUXSEG3EI32_V_M1_M2_MASK = 7054 + + PseudoVLUXSEG3EI32_V_M1_MF2 = 7055 + + PseudoVLUXSEG3EI32_V_M1_MF2_MASK = 7056 + + PseudoVLUXSEG3EI32_V_M1_MF4 = 7057 + + PseudoVLUXSEG3EI32_V_M1_MF4_MASK = 7058 + + PseudoVLUXSEG3EI32_V_M2_M1 = 7059 + + PseudoVLUXSEG3EI32_V_M2_M1_MASK = 7060 + + PseudoVLUXSEG3EI32_V_M2_M2 = 7061 + + PseudoVLUXSEG3EI32_V_M2_M2_MASK = 7062 + + PseudoVLUXSEG3EI32_V_M2_MF2 = 7063 + + PseudoVLUXSEG3EI32_V_M2_MF2_MASK = 7064 + + PseudoVLUXSEG3EI32_V_M4_M1 = 7065 + + PseudoVLUXSEG3EI32_V_M4_M1_MASK = 7066 + + PseudoVLUXSEG3EI32_V_M4_M2 = 7067 + + PseudoVLUXSEG3EI32_V_M4_M2_MASK = 7068 + + PseudoVLUXSEG3EI32_V_M8_M2 = 7069 + + PseudoVLUXSEG3EI32_V_M8_M2_MASK = 7070 + + PseudoVLUXSEG3EI32_V_MF2_M1 = 7071 + + PseudoVLUXSEG3EI32_V_MF2_M1_MASK = 7072 + + PseudoVLUXSEG3EI32_V_MF2_MF2 = 7073 + + PseudoVLUXSEG3EI32_V_MF2_MF2_MASK = 7074 + + PseudoVLUXSEG3EI32_V_MF2_MF4 = 7075 + + PseudoVLUXSEG3EI32_V_MF2_MF4_MASK = 7076 + + PseudoVLUXSEG3EI32_V_MF2_MF8 = 7077 + + PseudoVLUXSEG3EI32_V_MF2_MF8_MASK = 7078 + + PseudoVLUXSEG3EI64_V_M1_M1 = 7079 + + PseudoVLUXSEG3EI64_V_M1_M1_MASK = 7080 + + PseudoVLUXSEG3EI64_V_M1_MF2 = 7081 + + PseudoVLUXSEG3EI64_V_M1_MF2_MASK = 7082 + + PseudoVLUXSEG3EI64_V_M1_MF4 = 7083 + + PseudoVLUXSEG3EI64_V_M1_MF4_MASK = 7084 + + PseudoVLUXSEG3EI64_V_M1_MF8 = 7085 + + PseudoVLUXSEG3EI64_V_M1_MF8_MASK = 7086 + + PseudoVLUXSEG3EI64_V_M2_M1 = 7087 + + PseudoVLUXSEG3EI64_V_M2_M1_MASK = 7088 + + PseudoVLUXSEG3EI64_V_M2_M2 = 7089 + + PseudoVLUXSEG3EI64_V_M2_M2_MASK = 7090 + + PseudoVLUXSEG3EI64_V_M2_MF2 = 7091 + + PseudoVLUXSEG3EI64_V_M2_MF2_MASK = 7092 + + PseudoVLUXSEG3EI64_V_M2_MF4 = 7093 + + PseudoVLUXSEG3EI64_V_M2_MF4_MASK = 7094 + + PseudoVLUXSEG3EI64_V_M4_M1 = 7095 + + PseudoVLUXSEG3EI64_V_M4_M1_MASK = 7096 + + PseudoVLUXSEG3EI64_V_M4_M2 = 7097 + + PseudoVLUXSEG3EI64_V_M4_M2_MASK = 7098 + + PseudoVLUXSEG3EI64_V_M4_MF2 = 7099 + + PseudoVLUXSEG3EI64_V_M4_MF2_MASK = 7100 + + PseudoVLUXSEG3EI64_V_M8_M1 = 7101 + + PseudoVLUXSEG3EI64_V_M8_M1_MASK = 7102 + + PseudoVLUXSEG3EI64_V_M8_M2 = 7103 + + PseudoVLUXSEG3EI64_V_M8_M2_MASK = 7104 + + PseudoVLUXSEG3EI8_V_M1_M1 = 7105 + + PseudoVLUXSEG3EI8_V_M1_M1_MASK = 7106 + + PseudoVLUXSEG3EI8_V_M1_M2 = 7107 + + PseudoVLUXSEG3EI8_V_M1_M2_MASK = 7108 + + PseudoVLUXSEG3EI8_V_M2_M2 = 7109 + + PseudoVLUXSEG3EI8_V_M2_M2_MASK = 7110 + + PseudoVLUXSEG3EI8_V_MF2_M1 = 7111 + + PseudoVLUXSEG3EI8_V_MF2_M1_MASK = 7112 + + PseudoVLUXSEG3EI8_V_MF2_M2 = 7113 + + PseudoVLUXSEG3EI8_V_MF2_M2_MASK = 7114 + + PseudoVLUXSEG3EI8_V_MF2_MF2 = 7115 + + PseudoVLUXSEG3EI8_V_MF2_MF2_MASK = 7116 + + PseudoVLUXSEG3EI8_V_MF4_M1 = 7117 + + PseudoVLUXSEG3EI8_V_MF4_M1_MASK = 7118 + + PseudoVLUXSEG3EI8_V_MF4_M2 = 7119 + + PseudoVLUXSEG3EI8_V_MF4_M2_MASK = 7120 + + PseudoVLUXSEG3EI8_V_MF4_MF2 = 7121 + + PseudoVLUXSEG3EI8_V_MF4_MF2_MASK = 7122 + + PseudoVLUXSEG3EI8_V_MF4_MF4 = 7123 + + PseudoVLUXSEG3EI8_V_MF4_MF4_MASK = 7124 + + PseudoVLUXSEG3EI8_V_MF8_M1 = 7125 + + PseudoVLUXSEG3EI8_V_MF8_M1_MASK = 7126 + + PseudoVLUXSEG3EI8_V_MF8_MF2 = 7127 + + PseudoVLUXSEG3EI8_V_MF8_MF2_MASK = 7128 + + PseudoVLUXSEG3EI8_V_MF8_MF4 = 7129 + + PseudoVLUXSEG3EI8_V_MF8_MF4_MASK = 7130 + + PseudoVLUXSEG3EI8_V_MF8_MF8 = 7131 + + PseudoVLUXSEG3EI8_V_MF8_MF8_MASK = 7132 + + PseudoVLUXSEG4EI16_V_M1_M1 = 7133 + + PseudoVLUXSEG4EI16_V_M1_M1_MASK = 7134 + + PseudoVLUXSEG4EI16_V_M1_M2 = 7135 + + PseudoVLUXSEG4EI16_V_M1_M2_MASK = 7136 + + PseudoVLUXSEG4EI16_V_M1_MF2 = 7137 + + PseudoVLUXSEG4EI16_V_M1_MF2_MASK = 7138 + + PseudoVLUXSEG4EI16_V_M2_M1 = 7139 + + PseudoVLUXSEG4EI16_V_M2_M1_MASK = 7140 + + PseudoVLUXSEG4EI16_V_M2_M2 = 7141 + + PseudoVLUXSEG4EI16_V_M2_M2_MASK = 7142 + + PseudoVLUXSEG4EI16_V_M4_M2 = 7143 + + PseudoVLUXSEG4EI16_V_M4_M2_MASK = 7144 + + PseudoVLUXSEG4EI16_V_MF2_M1 = 7145 + + PseudoVLUXSEG4EI16_V_MF2_M1_MASK = 7146 + + PseudoVLUXSEG4EI16_V_MF2_M2 = 7147 + + PseudoVLUXSEG4EI16_V_MF2_M2_MASK = 7148 + + PseudoVLUXSEG4EI16_V_MF2_MF2 = 7149 + + PseudoVLUXSEG4EI16_V_MF2_MF2_MASK = 7150 + + PseudoVLUXSEG4EI16_V_MF2_MF4 = 7151 + + PseudoVLUXSEG4EI16_V_MF2_MF4_MASK = 7152 + + PseudoVLUXSEG4EI16_V_MF4_M1 = 7153 + + PseudoVLUXSEG4EI16_V_MF4_M1_MASK = 7154 + + PseudoVLUXSEG4EI16_V_MF4_MF2 = 7155 + + PseudoVLUXSEG4EI16_V_MF4_MF2_MASK = 7156 + + PseudoVLUXSEG4EI16_V_MF4_MF4 = 7157 + + PseudoVLUXSEG4EI16_V_MF4_MF4_MASK = 7158 + + PseudoVLUXSEG4EI16_V_MF4_MF8 = 7159 + + PseudoVLUXSEG4EI16_V_MF4_MF8_MASK = 7160 + + PseudoVLUXSEG4EI32_V_M1_M1 = 7161 + + PseudoVLUXSEG4EI32_V_M1_M1_MASK = 7162 + + PseudoVLUXSEG4EI32_V_M1_M2 = 7163 + + PseudoVLUXSEG4EI32_V_M1_M2_MASK = 7164 + + PseudoVLUXSEG4EI32_V_M1_MF2 = 7165 + + PseudoVLUXSEG4EI32_V_M1_MF2_MASK = 7166 + + PseudoVLUXSEG4EI32_V_M1_MF4 = 7167 + + PseudoVLUXSEG4EI32_V_M1_MF4_MASK = 7168 + + PseudoVLUXSEG4EI32_V_M2_M1 = 7169 + + PseudoVLUXSEG4EI32_V_M2_M1_MASK = 7170 + + PseudoVLUXSEG4EI32_V_M2_M2 = 7171 + + PseudoVLUXSEG4EI32_V_M2_M2_MASK = 7172 + + PseudoVLUXSEG4EI32_V_M2_MF2 = 7173 + + PseudoVLUXSEG4EI32_V_M2_MF2_MASK = 7174 + + PseudoVLUXSEG4EI32_V_M4_M1 = 7175 + + PseudoVLUXSEG4EI32_V_M4_M1_MASK = 7176 + + PseudoVLUXSEG4EI32_V_M4_M2 = 7177 + + PseudoVLUXSEG4EI32_V_M4_M2_MASK = 7178 + + PseudoVLUXSEG4EI32_V_M8_M2 = 7179 + + PseudoVLUXSEG4EI32_V_M8_M2_MASK = 7180 + + PseudoVLUXSEG4EI32_V_MF2_M1 = 7181 + + PseudoVLUXSEG4EI32_V_MF2_M1_MASK = 7182 + + PseudoVLUXSEG4EI32_V_MF2_MF2 = 7183 + + PseudoVLUXSEG4EI32_V_MF2_MF2_MASK = 7184 + + PseudoVLUXSEG4EI32_V_MF2_MF4 = 7185 + + PseudoVLUXSEG4EI32_V_MF2_MF4_MASK = 7186 + + PseudoVLUXSEG4EI32_V_MF2_MF8 = 7187 + + PseudoVLUXSEG4EI32_V_MF2_MF8_MASK = 7188 + + PseudoVLUXSEG4EI64_V_M1_M1 = 7189 + + PseudoVLUXSEG4EI64_V_M1_M1_MASK = 7190 + + PseudoVLUXSEG4EI64_V_M1_MF2 = 7191 + + PseudoVLUXSEG4EI64_V_M1_MF2_MASK = 7192 + + PseudoVLUXSEG4EI64_V_M1_MF4 = 7193 + + PseudoVLUXSEG4EI64_V_M1_MF4_MASK = 7194 + + PseudoVLUXSEG4EI64_V_M1_MF8 = 7195 + + PseudoVLUXSEG4EI64_V_M1_MF8_MASK = 7196 + + PseudoVLUXSEG4EI64_V_M2_M1 = 7197 + + PseudoVLUXSEG4EI64_V_M2_M1_MASK = 7198 + + PseudoVLUXSEG4EI64_V_M2_M2 = 7199 + + PseudoVLUXSEG4EI64_V_M2_M2_MASK = 7200 + + PseudoVLUXSEG4EI64_V_M2_MF2 = 7201 + + PseudoVLUXSEG4EI64_V_M2_MF2_MASK = 7202 + + PseudoVLUXSEG4EI64_V_M2_MF4 = 7203 + + PseudoVLUXSEG4EI64_V_M2_MF4_MASK = 7204 + + PseudoVLUXSEG4EI64_V_M4_M1 = 7205 + + PseudoVLUXSEG4EI64_V_M4_M1_MASK = 7206 + + PseudoVLUXSEG4EI64_V_M4_M2 = 7207 + + PseudoVLUXSEG4EI64_V_M4_M2_MASK = 7208 + + PseudoVLUXSEG4EI64_V_M4_MF2 = 7209 + + PseudoVLUXSEG4EI64_V_M4_MF2_MASK = 7210 + + PseudoVLUXSEG4EI64_V_M8_M1 = 7211 + + PseudoVLUXSEG4EI64_V_M8_M1_MASK = 7212 + + PseudoVLUXSEG4EI64_V_M8_M2 = 7213 + + PseudoVLUXSEG4EI64_V_M8_M2_MASK = 7214 + + PseudoVLUXSEG4EI8_V_M1_M1 = 7215 + + PseudoVLUXSEG4EI8_V_M1_M1_MASK = 7216 + + PseudoVLUXSEG4EI8_V_M1_M2 = 7217 + + PseudoVLUXSEG4EI8_V_M1_M2_MASK = 7218 + + PseudoVLUXSEG4EI8_V_M2_M2 = 7219 + + PseudoVLUXSEG4EI8_V_M2_M2_MASK = 7220 + + PseudoVLUXSEG4EI8_V_MF2_M1 = 7221 + + PseudoVLUXSEG4EI8_V_MF2_M1_MASK = 7222 + + PseudoVLUXSEG4EI8_V_MF2_M2 = 7223 + + PseudoVLUXSEG4EI8_V_MF2_M2_MASK = 7224 + + PseudoVLUXSEG4EI8_V_MF2_MF2 = 7225 + + PseudoVLUXSEG4EI8_V_MF2_MF2_MASK = 7226 + + PseudoVLUXSEG4EI8_V_MF4_M1 = 7227 + + PseudoVLUXSEG4EI8_V_MF4_M1_MASK = 7228 + + PseudoVLUXSEG4EI8_V_MF4_M2 = 7229 + + PseudoVLUXSEG4EI8_V_MF4_M2_MASK = 7230 + + PseudoVLUXSEG4EI8_V_MF4_MF2 = 7231 + + PseudoVLUXSEG4EI8_V_MF4_MF2_MASK = 7232 + + PseudoVLUXSEG4EI8_V_MF4_MF4 = 7233 + + PseudoVLUXSEG4EI8_V_MF4_MF4_MASK = 7234 + + PseudoVLUXSEG4EI8_V_MF8_M1 = 7235 + + PseudoVLUXSEG4EI8_V_MF8_M1_MASK = 7236 + + PseudoVLUXSEG4EI8_V_MF8_MF2 = 7237 + + PseudoVLUXSEG4EI8_V_MF8_MF2_MASK = 7238 + + PseudoVLUXSEG4EI8_V_MF8_MF4 = 7239 + + PseudoVLUXSEG4EI8_V_MF8_MF4_MASK = 7240 + + PseudoVLUXSEG4EI8_V_MF8_MF8 = 7241 + + PseudoVLUXSEG4EI8_V_MF8_MF8_MASK = 7242 + + PseudoVLUXSEG5EI16_V_M1_M1 = 7243 + + PseudoVLUXSEG5EI16_V_M1_M1_MASK = 7244 + + PseudoVLUXSEG5EI16_V_M1_MF2 = 7245 + + PseudoVLUXSEG5EI16_V_M1_MF2_MASK = 7246 + + PseudoVLUXSEG5EI16_V_M2_M1 = 7247 + + PseudoVLUXSEG5EI16_V_M2_M1_MASK = 7248 + + PseudoVLUXSEG5EI16_V_MF2_M1 = 7249 + + PseudoVLUXSEG5EI16_V_MF2_M1_MASK = 7250 + + PseudoVLUXSEG5EI16_V_MF2_MF2 = 7251 + + PseudoVLUXSEG5EI16_V_MF2_MF2_MASK = 7252 + + PseudoVLUXSEG5EI16_V_MF2_MF4 = 7253 + + PseudoVLUXSEG5EI16_V_MF2_MF4_MASK = 7254 + + PseudoVLUXSEG5EI16_V_MF4_M1 = 7255 + + PseudoVLUXSEG5EI16_V_MF4_M1_MASK = 7256 + + PseudoVLUXSEG5EI16_V_MF4_MF2 = 7257 + + PseudoVLUXSEG5EI16_V_MF4_MF2_MASK = 7258 + + PseudoVLUXSEG5EI16_V_MF4_MF4 = 7259 + + PseudoVLUXSEG5EI16_V_MF4_MF4_MASK = 7260 + + PseudoVLUXSEG5EI16_V_MF4_MF8 = 7261 + + PseudoVLUXSEG5EI16_V_MF4_MF8_MASK = 7262 + + PseudoVLUXSEG5EI32_V_M1_M1 = 7263 + + PseudoVLUXSEG5EI32_V_M1_M1_MASK = 7264 + + PseudoVLUXSEG5EI32_V_M1_MF2 = 7265 + + PseudoVLUXSEG5EI32_V_M1_MF2_MASK = 7266 + + PseudoVLUXSEG5EI32_V_M1_MF4 = 7267 + + PseudoVLUXSEG5EI32_V_M1_MF4_MASK = 7268 + + PseudoVLUXSEG5EI32_V_M2_M1 = 7269 + + PseudoVLUXSEG5EI32_V_M2_M1_MASK = 7270 + + PseudoVLUXSEG5EI32_V_M2_MF2 = 7271 + + PseudoVLUXSEG5EI32_V_M2_MF2_MASK = 7272 + + PseudoVLUXSEG5EI32_V_M4_M1 = 7273 + + PseudoVLUXSEG5EI32_V_M4_M1_MASK = 7274 + + PseudoVLUXSEG5EI32_V_MF2_M1 = 7275 + + PseudoVLUXSEG5EI32_V_MF2_M1_MASK = 7276 + + PseudoVLUXSEG5EI32_V_MF2_MF2 = 7277 + + PseudoVLUXSEG5EI32_V_MF2_MF2_MASK = 7278 + + PseudoVLUXSEG5EI32_V_MF2_MF4 = 7279 + + PseudoVLUXSEG5EI32_V_MF2_MF4_MASK = 7280 + + PseudoVLUXSEG5EI32_V_MF2_MF8 = 7281 + + PseudoVLUXSEG5EI32_V_MF2_MF8_MASK = 7282 + + PseudoVLUXSEG5EI64_V_M1_M1 = 7283 + + PseudoVLUXSEG5EI64_V_M1_M1_MASK = 7284 + + PseudoVLUXSEG5EI64_V_M1_MF2 = 7285 + + PseudoVLUXSEG5EI64_V_M1_MF2_MASK = 7286 + + PseudoVLUXSEG5EI64_V_M1_MF4 = 7287 + + PseudoVLUXSEG5EI64_V_M1_MF4_MASK = 7288 + + PseudoVLUXSEG5EI64_V_M1_MF8 = 7289 + + PseudoVLUXSEG5EI64_V_M1_MF8_MASK = 7290 + + PseudoVLUXSEG5EI64_V_M2_M1 = 7291 + + PseudoVLUXSEG5EI64_V_M2_M1_MASK = 7292 + + PseudoVLUXSEG5EI64_V_M2_MF2 = 7293 + + PseudoVLUXSEG5EI64_V_M2_MF2_MASK = 7294 + + PseudoVLUXSEG5EI64_V_M2_MF4 = 7295 + + PseudoVLUXSEG5EI64_V_M2_MF4_MASK = 7296 + + PseudoVLUXSEG5EI64_V_M4_M1 = 7297 + + PseudoVLUXSEG5EI64_V_M4_M1_MASK = 7298 + + PseudoVLUXSEG5EI64_V_M4_MF2 = 7299 + + PseudoVLUXSEG5EI64_V_M4_MF2_MASK = 7300 + + PseudoVLUXSEG5EI64_V_M8_M1 = 7301 + + PseudoVLUXSEG5EI64_V_M8_M1_MASK = 7302 + + PseudoVLUXSEG5EI8_V_M1_M1 = 7303 + + PseudoVLUXSEG5EI8_V_M1_M1_MASK = 7304 + + PseudoVLUXSEG5EI8_V_MF2_M1 = 7305 + + PseudoVLUXSEG5EI8_V_MF2_M1_MASK = 7306 + + PseudoVLUXSEG5EI8_V_MF2_MF2 = 7307 + + PseudoVLUXSEG5EI8_V_MF2_MF2_MASK = 7308 + + PseudoVLUXSEG5EI8_V_MF4_M1 = 7309 + + PseudoVLUXSEG5EI8_V_MF4_M1_MASK = 7310 + + PseudoVLUXSEG5EI8_V_MF4_MF2 = 7311 + + PseudoVLUXSEG5EI8_V_MF4_MF2_MASK = 7312 + + PseudoVLUXSEG5EI8_V_MF4_MF4 = 7313 + + PseudoVLUXSEG5EI8_V_MF4_MF4_MASK = 7314 + + PseudoVLUXSEG5EI8_V_MF8_M1 = 7315 + + PseudoVLUXSEG5EI8_V_MF8_M1_MASK = 7316 + + PseudoVLUXSEG5EI8_V_MF8_MF2 = 7317 + + PseudoVLUXSEG5EI8_V_MF8_MF2_MASK = 7318 + + PseudoVLUXSEG5EI8_V_MF8_MF4 = 7319 + + PseudoVLUXSEG5EI8_V_MF8_MF4_MASK = 7320 + + PseudoVLUXSEG5EI8_V_MF8_MF8 = 7321 + + PseudoVLUXSEG5EI8_V_MF8_MF8_MASK = 7322 + + PseudoVLUXSEG6EI16_V_M1_M1 = 7323 + + PseudoVLUXSEG6EI16_V_M1_M1_MASK = 7324 + + PseudoVLUXSEG6EI16_V_M1_MF2 = 7325 + + PseudoVLUXSEG6EI16_V_M1_MF2_MASK = 7326 + + PseudoVLUXSEG6EI16_V_M2_M1 = 7327 + + PseudoVLUXSEG6EI16_V_M2_M1_MASK = 7328 + + PseudoVLUXSEG6EI16_V_MF2_M1 = 7329 + + PseudoVLUXSEG6EI16_V_MF2_M1_MASK = 7330 + + PseudoVLUXSEG6EI16_V_MF2_MF2 = 7331 + + PseudoVLUXSEG6EI16_V_MF2_MF2_MASK = 7332 + + PseudoVLUXSEG6EI16_V_MF2_MF4 = 7333 + + PseudoVLUXSEG6EI16_V_MF2_MF4_MASK = 7334 + + PseudoVLUXSEG6EI16_V_MF4_M1 = 7335 + + PseudoVLUXSEG6EI16_V_MF4_M1_MASK = 7336 + + PseudoVLUXSEG6EI16_V_MF4_MF2 = 7337 + + PseudoVLUXSEG6EI16_V_MF4_MF2_MASK = 7338 + + PseudoVLUXSEG6EI16_V_MF4_MF4 = 7339 + + PseudoVLUXSEG6EI16_V_MF4_MF4_MASK = 7340 + + PseudoVLUXSEG6EI16_V_MF4_MF8 = 7341 + + PseudoVLUXSEG6EI16_V_MF4_MF8_MASK = 7342 + + PseudoVLUXSEG6EI32_V_M1_M1 = 7343 + + PseudoVLUXSEG6EI32_V_M1_M1_MASK = 7344 + + PseudoVLUXSEG6EI32_V_M1_MF2 = 7345 + + PseudoVLUXSEG6EI32_V_M1_MF2_MASK = 7346 + + PseudoVLUXSEG6EI32_V_M1_MF4 = 7347 + + PseudoVLUXSEG6EI32_V_M1_MF4_MASK = 7348 + + PseudoVLUXSEG6EI32_V_M2_M1 = 7349 + + PseudoVLUXSEG6EI32_V_M2_M1_MASK = 7350 + + PseudoVLUXSEG6EI32_V_M2_MF2 = 7351 + + PseudoVLUXSEG6EI32_V_M2_MF2_MASK = 7352 + + PseudoVLUXSEG6EI32_V_M4_M1 = 7353 + + PseudoVLUXSEG6EI32_V_M4_M1_MASK = 7354 + + PseudoVLUXSEG6EI32_V_MF2_M1 = 7355 + + PseudoVLUXSEG6EI32_V_MF2_M1_MASK = 7356 + + PseudoVLUXSEG6EI32_V_MF2_MF2 = 7357 + + PseudoVLUXSEG6EI32_V_MF2_MF2_MASK = 7358 + + PseudoVLUXSEG6EI32_V_MF2_MF4 = 7359 + + PseudoVLUXSEG6EI32_V_MF2_MF4_MASK = 7360 + + PseudoVLUXSEG6EI32_V_MF2_MF8 = 7361 + + PseudoVLUXSEG6EI32_V_MF2_MF8_MASK = 7362 + + PseudoVLUXSEG6EI64_V_M1_M1 = 7363 + + PseudoVLUXSEG6EI64_V_M1_M1_MASK = 7364 + + PseudoVLUXSEG6EI64_V_M1_MF2 = 7365 + + PseudoVLUXSEG6EI64_V_M1_MF2_MASK = 7366 + + PseudoVLUXSEG6EI64_V_M1_MF4 = 7367 + + PseudoVLUXSEG6EI64_V_M1_MF4_MASK = 7368 + + PseudoVLUXSEG6EI64_V_M1_MF8 = 7369 + + PseudoVLUXSEG6EI64_V_M1_MF8_MASK = 7370 + + PseudoVLUXSEG6EI64_V_M2_M1 = 7371 + + PseudoVLUXSEG6EI64_V_M2_M1_MASK = 7372 + + PseudoVLUXSEG6EI64_V_M2_MF2 = 7373 + + PseudoVLUXSEG6EI64_V_M2_MF2_MASK = 7374 + + PseudoVLUXSEG6EI64_V_M2_MF4 = 7375 + + PseudoVLUXSEG6EI64_V_M2_MF4_MASK = 7376 + + PseudoVLUXSEG6EI64_V_M4_M1 = 7377 + + PseudoVLUXSEG6EI64_V_M4_M1_MASK = 7378 + + PseudoVLUXSEG6EI64_V_M4_MF2 = 7379 + + PseudoVLUXSEG6EI64_V_M4_MF2_MASK = 7380 + + PseudoVLUXSEG6EI64_V_M8_M1 = 7381 + + PseudoVLUXSEG6EI64_V_M8_M1_MASK = 7382 + + PseudoVLUXSEG6EI8_V_M1_M1 = 7383 + + PseudoVLUXSEG6EI8_V_M1_M1_MASK = 7384 + + PseudoVLUXSEG6EI8_V_MF2_M1 = 7385 + + PseudoVLUXSEG6EI8_V_MF2_M1_MASK = 7386 + + PseudoVLUXSEG6EI8_V_MF2_MF2 = 7387 + + PseudoVLUXSEG6EI8_V_MF2_MF2_MASK = 7388 + + PseudoVLUXSEG6EI8_V_MF4_M1 = 7389 + + PseudoVLUXSEG6EI8_V_MF4_M1_MASK = 7390 + + PseudoVLUXSEG6EI8_V_MF4_MF2 = 7391 + + PseudoVLUXSEG6EI8_V_MF4_MF2_MASK = 7392 + + PseudoVLUXSEG6EI8_V_MF4_MF4 = 7393 + + PseudoVLUXSEG6EI8_V_MF4_MF4_MASK = 7394 + + PseudoVLUXSEG6EI8_V_MF8_M1 = 7395 + + PseudoVLUXSEG6EI8_V_MF8_M1_MASK = 7396 + + PseudoVLUXSEG6EI8_V_MF8_MF2 = 7397 + + PseudoVLUXSEG6EI8_V_MF8_MF2_MASK = 7398 + + PseudoVLUXSEG6EI8_V_MF8_MF4 = 7399 + + PseudoVLUXSEG6EI8_V_MF8_MF4_MASK = 7400 + + PseudoVLUXSEG6EI8_V_MF8_MF8 = 7401 + + PseudoVLUXSEG6EI8_V_MF8_MF8_MASK = 7402 + + PseudoVLUXSEG7EI16_V_M1_M1 = 7403 + + PseudoVLUXSEG7EI16_V_M1_M1_MASK = 7404 + + PseudoVLUXSEG7EI16_V_M1_MF2 = 7405 + + PseudoVLUXSEG7EI16_V_M1_MF2_MASK = 7406 + + PseudoVLUXSEG7EI16_V_M2_M1 = 7407 + + PseudoVLUXSEG7EI16_V_M2_M1_MASK = 7408 + + PseudoVLUXSEG7EI16_V_MF2_M1 = 7409 + + PseudoVLUXSEG7EI16_V_MF2_M1_MASK = 7410 + + PseudoVLUXSEG7EI16_V_MF2_MF2 = 7411 + + PseudoVLUXSEG7EI16_V_MF2_MF2_MASK = 7412 + + PseudoVLUXSEG7EI16_V_MF2_MF4 = 7413 + + PseudoVLUXSEG7EI16_V_MF2_MF4_MASK = 7414 + + PseudoVLUXSEG7EI16_V_MF4_M1 = 7415 + + PseudoVLUXSEG7EI16_V_MF4_M1_MASK = 7416 + + PseudoVLUXSEG7EI16_V_MF4_MF2 = 7417 + + PseudoVLUXSEG7EI16_V_MF4_MF2_MASK = 7418 + + PseudoVLUXSEG7EI16_V_MF4_MF4 = 7419 + + PseudoVLUXSEG7EI16_V_MF4_MF4_MASK = 7420 + + PseudoVLUXSEG7EI16_V_MF4_MF8 = 7421 + + PseudoVLUXSEG7EI16_V_MF4_MF8_MASK = 7422 + + PseudoVLUXSEG7EI32_V_M1_M1 = 7423 + + PseudoVLUXSEG7EI32_V_M1_M1_MASK = 7424 + + PseudoVLUXSEG7EI32_V_M1_MF2 = 7425 + + PseudoVLUXSEG7EI32_V_M1_MF2_MASK = 7426 + + PseudoVLUXSEG7EI32_V_M1_MF4 = 7427 + + PseudoVLUXSEG7EI32_V_M1_MF4_MASK = 7428 + + PseudoVLUXSEG7EI32_V_M2_M1 = 7429 + + PseudoVLUXSEG7EI32_V_M2_M1_MASK = 7430 + + PseudoVLUXSEG7EI32_V_M2_MF2 = 7431 + + PseudoVLUXSEG7EI32_V_M2_MF2_MASK = 7432 + + PseudoVLUXSEG7EI32_V_M4_M1 = 7433 + + PseudoVLUXSEG7EI32_V_M4_M1_MASK = 7434 + + PseudoVLUXSEG7EI32_V_MF2_M1 = 7435 + + PseudoVLUXSEG7EI32_V_MF2_M1_MASK = 7436 + + PseudoVLUXSEG7EI32_V_MF2_MF2 = 7437 + + PseudoVLUXSEG7EI32_V_MF2_MF2_MASK = 7438 + + PseudoVLUXSEG7EI32_V_MF2_MF4 = 7439 + + PseudoVLUXSEG7EI32_V_MF2_MF4_MASK = 7440 + + PseudoVLUXSEG7EI32_V_MF2_MF8 = 7441 + + PseudoVLUXSEG7EI32_V_MF2_MF8_MASK = 7442 + + PseudoVLUXSEG7EI64_V_M1_M1 = 7443 + + PseudoVLUXSEG7EI64_V_M1_M1_MASK = 7444 + + PseudoVLUXSEG7EI64_V_M1_MF2 = 7445 + + PseudoVLUXSEG7EI64_V_M1_MF2_MASK = 7446 + + PseudoVLUXSEG7EI64_V_M1_MF4 = 7447 + + PseudoVLUXSEG7EI64_V_M1_MF4_MASK = 7448 + + PseudoVLUXSEG7EI64_V_M1_MF8 = 7449 + + PseudoVLUXSEG7EI64_V_M1_MF8_MASK = 7450 + + PseudoVLUXSEG7EI64_V_M2_M1 = 7451 + + PseudoVLUXSEG7EI64_V_M2_M1_MASK = 7452 + + PseudoVLUXSEG7EI64_V_M2_MF2 = 7453 + + PseudoVLUXSEG7EI64_V_M2_MF2_MASK = 7454 + + PseudoVLUXSEG7EI64_V_M2_MF4 = 7455 + + PseudoVLUXSEG7EI64_V_M2_MF4_MASK = 7456 + + PseudoVLUXSEG7EI64_V_M4_M1 = 7457 + + PseudoVLUXSEG7EI64_V_M4_M1_MASK = 7458 + + PseudoVLUXSEG7EI64_V_M4_MF2 = 7459 + + PseudoVLUXSEG7EI64_V_M4_MF2_MASK = 7460 + + PseudoVLUXSEG7EI64_V_M8_M1 = 7461 + + PseudoVLUXSEG7EI64_V_M8_M1_MASK = 7462 + + PseudoVLUXSEG7EI8_V_M1_M1 = 7463 + + PseudoVLUXSEG7EI8_V_M1_M1_MASK = 7464 + + PseudoVLUXSEG7EI8_V_MF2_M1 = 7465 + + PseudoVLUXSEG7EI8_V_MF2_M1_MASK = 7466 + + PseudoVLUXSEG7EI8_V_MF2_MF2 = 7467 + + PseudoVLUXSEG7EI8_V_MF2_MF2_MASK = 7468 + + PseudoVLUXSEG7EI8_V_MF4_M1 = 7469 + + PseudoVLUXSEG7EI8_V_MF4_M1_MASK = 7470 + + PseudoVLUXSEG7EI8_V_MF4_MF2 = 7471 + + PseudoVLUXSEG7EI8_V_MF4_MF2_MASK = 7472 + + PseudoVLUXSEG7EI8_V_MF4_MF4 = 7473 + + PseudoVLUXSEG7EI8_V_MF4_MF4_MASK = 7474 + + PseudoVLUXSEG7EI8_V_MF8_M1 = 7475 + + PseudoVLUXSEG7EI8_V_MF8_M1_MASK = 7476 + + PseudoVLUXSEG7EI8_V_MF8_MF2 = 7477 + + PseudoVLUXSEG7EI8_V_MF8_MF2_MASK = 7478 + + PseudoVLUXSEG7EI8_V_MF8_MF4 = 7479 + + PseudoVLUXSEG7EI8_V_MF8_MF4_MASK = 7480 + + PseudoVLUXSEG7EI8_V_MF8_MF8 = 7481 + + PseudoVLUXSEG7EI8_V_MF8_MF8_MASK = 7482 + + PseudoVLUXSEG8EI16_V_M1_M1 = 7483 + + PseudoVLUXSEG8EI16_V_M1_M1_MASK = 7484 + + PseudoVLUXSEG8EI16_V_M1_MF2 = 7485 + + PseudoVLUXSEG8EI16_V_M1_MF2_MASK = 7486 + + PseudoVLUXSEG8EI16_V_M2_M1 = 7487 + + PseudoVLUXSEG8EI16_V_M2_M1_MASK = 7488 + + PseudoVLUXSEG8EI16_V_MF2_M1 = 7489 + + PseudoVLUXSEG8EI16_V_MF2_M1_MASK = 7490 + + PseudoVLUXSEG8EI16_V_MF2_MF2 = 7491 + + PseudoVLUXSEG8EI16_V_MF2_MF2_MASK = 7492 + + PseudoVLUXSEG8EI16_V_MF2_MF4 = 7493 + + PseudoVLUXSEG8EI16_V_MF2_MF4_MASK = 7494 + + PseudoVLUXSEG8EI16_V_MF4_M1 = 7495 + + PseudoVLUXSEG8EI16_V_MF4_M1_MASK = 7496 + + PseudoVLUXSEG8EI16_V_MF4_MF2 = 7497 + + PseudoVLUXSEG8EI16_V_MF4_MF2_MASK = 7498 + + PseudoVLUXSEG8EI16_V_MF4_MF4 = 7499 + + PseudoVLUXSEG8EI16_V_MF4_MF4_MASK = 7500 + + PseudoVLUXSEG8EI16_V_MF4_MF8 = 7501 + + PseudoVLUXSEG8EI16_V_MF4_MF8_MASK = 7502 + + PseudoVLUXSEG8EI32_V_M1_M1 = 7503 + + PseudoVLUXSEG8EI32_V_M1_M1_MASK = 7504 + + PseudoVLUXSEG8EI32_V_M1_MF2 = 7505 + + PseudoVLUXSEG8EI32_V_M1_MF2_MASK = 7506 + + PseudoVLUXSEG8EI32_V_M1_MF4 = 7507 + + PseudoVLUXSEG8EI32_V_M1_MF4_MASK = 7508 + + PseudoVLUXSEG8EI32_V_M2_M1 = 7509 + + PseudoVLUXSEG8EI32_V_M2_M1_MASK = 7510 + + PseudoVLUXSEG8EI32_V_M2_MF2 = 7511 + + PseudoVLUXSEG8EI32_V_M2_MF2_MASK = 7512 + + PseudoVLUXSEG8EI32_V_M4_M1 = 7513 + + PseudoVLUXSEG8EI32_V_M4_M1_MASK = 7514 + + PseudoVLUXSEG8EI32_V_MF2_M1 = 7515 + + PseudoVLUXSEG8EI32_V_MF2_M1_MASK = 7516 + + PseudoVLUXSEG8EI32_V_MF2_MF2 = 7517 + + PseudoVLUXSEG8EI32_V_MF2_MF2_MASK = 7518 + + PseudoVLUXSEG8EI32_V_MF2_MF4 = 7519 + + PseudoVLUXSEG8EI32_V_MF2_MF4_MASK = 7520 + + PseudoVLUXSEG8EI32_V_MF2_MF8 = 7521 + + PseudoVLUXSEG8EI32_V_MF2_MF8_MASK = 7522 + + PseudoVLUXSEG8EI64_V_M1_M1 = 7523 + + PseudoVLUXSEG8EI64_V_M1_M1_MASK = 7524 + + PseudoVLUXSEG8EI64_V_M1_MF2 = 7525 + + PseudoVLUXSEG8EI64_V_M1_MF2_MASK = 7526 + + PseudoVLUXSEG8EI64_V_M1_MF4 = 7527 + + PseudoVLUXSEG8EI64_V_M1_MF4_MASK = 7528 + + PseudoVLUXSEG8EI64_V_M1_MF8 = 7529 + + PseudoVLUXSEG8EI64_V_M1_MF8_MASK = 7530 + + PseudoVLUXSEG8EI64_V_M2_M1 = 7531 + + PseudoVLUXSEG8EI64_V_M2_M1_MASK = 7532 + + PseudoVLUXSEG8EI64_V_M2_MF2 = 7533 + + PseudoVLUXSEG8EI64_V_M2_MF2_MASK = 7534 + + PseudoVLUXSEG8EI64_V_M2_MF4 = 7535 + + PseudoVLUXSEG8EI64_V_M2_MF4_MASK = 7536 + + PseudoVLUXSEG8EI64_V_M4_M1 = 7537 + + PseudoVLUXSEG8EI64_V_M4_M1_MASK = 7538 + + PseudoVLUXSEG8EI64_V_M4_MF2 = 7539 + + PseudoVLUXSEG8EI64_V_M4_MF2_MASK = 7540 + + PseudoVLUXSEG8EI64_V_M8_M1 = 7541 + + PseudoVLUXSEG8EI64_V_M8_M1_MASK = 7542 + + PseudoVLUXSEG8EI8_V_M1_M1 = 7543 + + PseudoVLUXSEG8EI8_V_M1_M1_MASK = 7544 + + PseudoVLUXSEG8EI8_V_MF2_M1 = 7545 + + PseudoVLUXSEG8EI8_V_MF2_M1_MASK = 7546 + + PseudoVLUXSEG8EI8_V_MF2_MF2 = 7547 + + PseudoVLUXSEG8EI8_V_MF2_MF2_MASK = 7548 + + PseudoVLUXSEG8EI8_V_MF4_M1 = 7549 + + PseudoVLUXSEG8EI8_V_MF4_M1_MASK = 7550 + + PseudoVLUXSEG8EI8_V_MF4_MF2 = 7551 + + PseudoVLUXSEG8EI8_V_MF4_MF2_MASK = 7552 + + PseudoVLUXSEG8EI8_V_MF4_MF4 = 7553 + + PseudoVLUXSEG8EI8_V_MF4_MF4_MASK = 7554 + + PseudoVLUXSEG8EI8_V_MF8_M1 = 7555 + + PseudoVLUXSEG8EI8_V_MF8_M1_MASK = 7556 + + PseudoVLUXSEG8EI8_V_MF8_MF2 = 7557 + + PseudoVLUXSEG8EI8_V_MF8_MF2_MASK = 7558 + + PseudoVLUXSEG8EI8_V_MF8_MF4 = 7559 + + PseudoVLUXSEG8EI8_V_MF8_MF4_MASK = 7560 + + PseudoVLUXSEG8EI8_V_MF8_MF8 = 7561 + + PseudoVLUXSEG8EI8_V_MF8_MF8_MASK = 7562 + + PseudoVMACC_VV_M1 = 7563 + + PseudoVMACC_VV_M1_MASK = 7564 + + PseudoVMACC_VV_M2 = 7565 + + PseudoVMACC_VV_M2_MASK = 7566 + + PseudoVMACC_VV_M4 = 7567 + + PseudoVMACC_VV_M4_MASK = 7568 + + PseudoVMACC_VV_M8 = 7569 + + PseudoVMACC_VV_M8_MASK = 7570 + + PseudoVMACC_VV_MF2 = 7571 + + PseudoVMACC_VV_MF2_MASK = 7572 + + PseudoVMACC_VV_MF4 = 7573 + + PseudoVMACC_VV_MF4_MASK = 7574 + + PseudoVMACC_VV_MF8 = 7575 + + PseudoVMACC_VV_MF8_MASK = 7576 + + PseudoVMACC_VX_M1 = 7577 + + PseudoVMACC_VX_M1_MASK = 7578 + + PseudoVMACC_VX_M2 = 7579 + + PseudoVMACC_VX_M2_MASK = 7580 + + PseudoVMACC_VX_M4 = 7581 + + PseudoVMACC_VX_M4_MASK = 7582 + + PseudoVMACC_VX_M8 = 7583 + + PseudoVMACC_VX_M8_MASK = 7584 + + PseudoVMACC_VX_MF2 = 7585 + + PseudoVMACC_VX_MF2_MASK = 7586 + + PseudoVMACC_VX_MF4 = 7587 + + PseudoVMACC_VX_MF4_MASK = 7588 + + PseudoVMACC_VX_MF8 = 7589 + + PseudoVMACC_VX_MF8_MASK = 7590 + + PseudoVMADC_VIM_M1 = 7591 + + PseudoVMADC_VIM_M2 = 7592 + + PseudoVMADC_VIM_M4 = 7593 + + PseudoVMADC_VIM_M8 = 7594 + + PseudoVMADC_VIM_MF2 = 7595 + + PseudoVMADC_VIM_MF4 = 7596 + + PseudoVMADC_VIM_MF8 = 7597 + + PseudoVMADC_VI_M1 = 7598 + + PseudoVMADC_VI_M2 = 7599 + + PseudoVMADC_VI_M4 = 7600 + + PseudoVMADC_VI_M8 = 7601 + + PseudoVMADC_VI_MF2 = 7602 + + PseudoVMADC_VI_MF4 = 7603 + + PseudoVMADC_VI_MF8 = 7604 + + PseudoVMADC_VVM_M1 = 7605 + + PseudoVMADC_VVM_M2 = 7606 + + PseudoVMADC_VVM_M4 = 7607 + + PseudoVMADC_VVM_M8 = 7608 + + PseudoVMADC_VVM_MF2 = 7609 + + PseudoVMADC_VVM_MF4 = 7610 + + PseudoVMADC_VVM_MF8 = 7611 + + PseudoVMADC_VV_M1 = 7612 + + PseudoVMADC_VV_M2 = 7613 + + PseudoVMADC_VV_M4 = 7614 + + PseudoVMADC_VV_M8 = 7615 + + PseudoVMADC_VV_MF2 = 7616 + + PseudoVMADC_VV_MF4 = 7617 + + PseudoVMADC_VV_MF8 = 7618 + + PseudoVMADC_VXM_M1 = 7619 + + PseudoVMADC_VXM_M2 = 7620 + + PseudoVMADC_VXM_M4 = 7621 + + PseudoVMADC_VXM_M8 = 7622 + + PseudoVMADC_VXM_MF2 = 7623 + + PseudoVMADC_VXM_MF4 = 7624 + + PseudoVMADC_VXM_MF8 = 7625 + + PseudoVMADC_VX_M1 = 7626 + + PseudoVMADC_VX_M2 = 7627 + + PseudoVMADC_VX_M4 = 7628 + + PseudoVMADC_VX_M8 = 7629 + + PseudoVMADC_VX_MF2 = 7630 + + PseudoVMADC_VX_MF4 = 7631 + + PseudoVMADC_VX_MF8 = 7632 + + PseudoVMADD_VV_M1 = 7633 + + PseudoVMADD_VV_M1_MASK = 7634 + + PseudoVMADD_VV_M2 = 7635 + + PseudoVMADD_VV_M2_MASK = 7636 + + PseudoVMADD_VV_M4 = 7637 + + PseudoVMADD_VV_M4_MASK = 7638 + + PseudoVMADD_VV_M8 = 7639 + + PseudoVMADD_VV_M8_MASK = 7640 + + PseudoVMADD_VV_MF2 = 7641 + + PseudoVMADD_VV_MF2_MASK = 7642 + + PseudoVMADD_VV_MF4 = 7643 + + PseudoVMADD_VV_MF4_MASK = 7644 + + PseudoVMADD_VV_MF8 = 7645 + + PseudoVMADD_VV_MF8_MASK = 7646 + + PseudoVMADD_VX_M1 = 7647 + + PseudoVMADD_VX_M1_MASK = 7648 + + PseudoVMADD_VX_M2 = 7649 + + PseudoVMADD_VX_M2_MASK = 7650 + + PseudoVMADD_VX_M4 = 7651 + + PseudoVMADD_VX_M4_MASK = 7652 + + PseudoVMADD_VX_M8 = 7653 + + PseudoVMADD_VX_M8_MASK = 7654 + + PseudoVMADD_VX_MF2 = 7655 + + PseudoVMADD_VX_MF2_MASK = 7656 + + PseudoVMADD_VX_MF4 = 7657 + + PseudoVMADD_VX_MF4_MASK = 7658 + + PseudoVMADD_VX_MF8 = 7659 + + PseudoVMADD_VX_MF8_MASK = 7660 + + PseudoVMANDN_MM_B1 = 7661 + + PseudoVMANDN_MM_B16 = 7662 + + PseudoVMANDN_MM_B2 = 7663 + + PseudoVMANDN_MM_B32 = 7664 + + PseudoVMANDN_MM_B4 = 7665 + + PseudoVMANDN_MM_B64 = 7666 + + PseudoVMANDN_MM_B8 = 7667 + + PseudoVMAND_MM_B1 = 7668 + + PseudoVMAND_MM_B16 = 7669 + + PseudoVMAND_MM_B2 = 7670 + + PseudoVMAND_MM_B32 = 7671 + + PseudoVMAND_MM_B4 = 7672 + + PseudoVMAND_MM_B64 = 7673 + + PseudoVMAND_MM_B8 = 7674 + + PseudoVMAXU_VV_M1 = 7675 + + PseudoVMAXU_VV_M1_MASK = 7676 + + PseudoVMAXU_VV_M2 = 7677 + + PseudoVMAXU_VV_M2_MASK = 7678 + + PseudoVMAXU_VV_M4 = 7679 + + PseudoVMAXU_VV_M4_MASK = 7680 + + PseudoVMAXU_VV_M8 = 7681 + + PseudoVMAXU_VV_M8_MASK = 7682 + + PseudoVMAXU_VV_MF2 = 7683 + + PseudoVMAXU_VV_MF2_MASK = 7684 + + PseudoVMAXU_VV_MF4 = 7685 + + PseudoVMAXU_VV_MF4_MASK = 7686 + + PseudoVMAXU_VV_MF8 = 7687 + + PseudoVMAXU_VV_MF8_MASK = 7688 + + PseudoVMAXU_VX_M1 = 7689 + + PseudoVMAXU_VX_M1_MASK = 7690 + + PseudoVMAXU_VX_M2 = 7691 + + PseudoVMAXU_VX_M2_MASK = 7692 + + PseudoVMAXU_VX_M4 = 7693 + + PseudoVMAXU_VX_M4_MASK = 7694 + + PseudoVMAXU_VX_M8 = 7695 + + PseudoVMAXU_VX_M8_MASK = 7696 + + PseudoVMAXU_VX_MF2 = 7697 + + PseudoVMAXU_VX_MF2_MASK = 7698 + + PseudoVMAXU_VX_MF4 = 7699 + + PseudoVMAXU_VX_MF4_MASK = 7700 + + PseudoVMAXU_VX_MF8 = 7701 + + PseudoVMAXU_VX_MF8_MASK = 7702 + + PseudoVMAX_VV_M1 = 7703 + + PseudoVMAX_VV_M1_MASK = 7704 + + PseudoVMAX_VV_M2 = 7705 + + PseudoVMAX_VV_M2_MASK = 7706 + + PseudoVMAX_VV_M4 = 7707 + + PseudoVMAX_VV_M4_MASK = 7708 + + PseudoVMAX_VV_M8 = 7709 + + PseudoVMAX_VV_M8_MASK = 7710 + + PseudoVMAX_VV_MF2 = 7711 + + PseudoVMAX_VV_MF2_MASK = 7712 + + PseudoVMAX_VV_MF4 = 7713 + + PseudoVMAX_VV_MF4_MASK = 7714 + + PseudoVMAX_VV_MF8 = 7715 + + PseudoVMAX_VV_MF8_MASK = 7716 + + PseudoVMAX_VX_M1 = 7717 + + PseudoVMAX_VX_M1_MASK = 7718 + + PseudoVMAX_VX_M2 = 7719 + + PseudoVMAX_VX_M2_MASK = 7720 + + PseudoVMAX_VX_M4 = 7721 + + PseudoVMAX_VX_M4_MASK = 7722 + + PseudoVMAX_VX_M8 = 7723 + + PseudoVMAX_VX_M8_MASK = 7724 + + PseudoVMAX_VX_MF2 = 7725 + + PseudoVMAX_VX_MF2_MASK = 7726 + + PseudoVMAX_VX_MF4 = 7727 + + PseudoVMAX_VX_MF4_MASK = 7728 + + PseudoVMAX_VX_MF8 = 7729 + + PseudoVMAX_VX_MF8_MASK = 7730 + + PseudoVMCLR_M_B1 = 7731 + + PseudoVMCLR_M_B16 = 7732 + + PseudoVMCLR_M_B2 = 7733 + + PseudoVMCLR_M_B32 = 7734 + + PseudoVMCLR_M_B4 = 7735 + + PseudoVMCLR_M_B64 = 7736 + + PseudoVMCLR_M_B8 = 7737 + + PseudoVMERGE_VIM_M1 = 7738 + + PseudoVMERGE_VIM_M2 = 7739 + + PseudoVMERGE_VIM_M4 = 7740 + + PseudoVMERGE_VIM_M8 = 7741 + + PseudoVMERGE_VIM_MF2 = 7742 + + PseudoVMERGE_VIM_MF4 = 7743 + + PseudoVMERGE_VIM_MF8 = 7744 + + PseudoVMERGE_VVM_M1 = 7745 + + PseudoVMERGE_VVM_M2 = 7746 + + PseudoVMERGE_VVM_M4 = 7747 + + PseudoVMERGE_VVM_M8 = 7748 + + PseudoVMERGE_VVM_MF2 = 7749 + + PseudoVMERGE_VVM_MF4 = 7750 + + PseudoVMERGE_VVM_MF8 = 7751 + + PseudoVMERGE_VXM_M1 = 7752 + + PseudoVMERGE_VXM_M2 = 7753 + + PseudoVMERGE_VXM_M4 = 7754 + + PseudoVMERGE_VXM_M8 = 7755 + + PseudoVMERGE_VXM_MF2 = 7756 + + PseudoVMERGE_VXM_MF4 = 7757 + + PseudoVMERGE_VXM_MF8 = 7758 + + PseudoVMFEQ_ALT_VFPR16_M1 = 7759 + + PseudoVMFEQ_ALT_VFPR16_M1_MASK = 7760 + + PseudoVMFEQ_ALT_VFPR16_M2 = 7761 + + PseudoVMFEQ_ALT_VFPR16_M2_MASK = 7762 + + PseudoVMFEQ_ALT_VFPR16_M4 = 7763 + + PseudoVMFEQ_ALT_VFPR16_M4_MASK = 7764 + + PseudoVMFEQ_ALT_VFPR16_M8 = 7765 + + PseudoVMFEQ_ALT_VFPR16_M8_MASK = 7766 + + PseudoVMFEQ_ALT_VFPR16_MF2 = 7767 + + PseudoVMFEQ_ALT_VFPR16_MF2_MASK = 7768 + + PseudoVMFEQ_ALT_VFPR16_MF4 = 7769 + + PseudoVMFEQ_ALT_VFPR16_MF4_MASK = 7770 + + PseudoVMFEQ_ALT_VFPR32_M1 = 7771 + + PseudoVMFEQ_ALT_VFPR32_M1_MASK = 7772 + + PseudoVMFEQ_ALT_VFPR32_M2 = 7773 + + PseudoVMFEQ_ALT_VFPR32_M2_MASK = 7774 + + PseudoVMFEQ_ALT_VFPR32_M4 = 7775 + + PseudoVMFEQ_ALT_VFPR32_M4_MASK = 7776 + + PseudoVMFEQ_ALT_VFPR32_M8 = 7777 + + PseudoVMFEQ_ALT_VFPR32_M8_MASK = 7778 + + PseudoVMFEQ_ALT_VFPR32_MF2 = 7779 + + PseudoVMFEQ_ALT_VFPR32_MF2_MASK = 7780 + + PseudoVMFEQ_ALT_VFPR64_M1 = 7781 + + PseudoVMFEQ_ALT_VFPR64_M1_MASK = 7782 + + PseudoVMFEQ_ALT_VFPR64_M2 = 7783 + + PseudoVMFEQ_ALT_VFPR64_M2_MASK = 7784 + + PseudoVMFEQ_ALT_VFPR64_M4 = 7785 + + PseudoVMFEQ_ALT_VFPR64_M4_MASK = 7786 + + PseudoVMFEQ_ALT_VFPR64_M8 = 7787 + + PseudoVMFEQ_ALT_VFPR64_M8_MASK = 7788 + + PseudoVMFEQ_ALT_VV_M1 = 7789 + + PseudoVMFEQ_ALT_VV_M1_MASK = 7790 + + PseudoVMFEQ_ALT_VV_M2 = 7791 + + PseudoVMFEQ_ALT_VV_M2_MASK = 7792 + + PseudoVMFEQ_ALT_VV_M4 = 7793 + + PseudoVMFEQ_ALT_VV_M4_MASK = 7794 + + PseudoVMFEQ_ALT_VV_M8 = 7795 + + PseudoVMFEQ_ALT_VV_M8_MASK = 7796 + + PseudoVMFEQ_ALT_VV_MF2 = 7797 + + PseudoVMFEQ_ALT_VV_MF2_MASK = 7798 + + PseudoVMFEQ_ALT_VV_MF4 = 7799 + + PseudoVMFEQ_ALT_VV_MF4_MASK = 7800 + + PseudoVMFEQ_VFPR16_M1 = 7801 + + PseudoVMFEQ_VFPR16_M1_MASK = 7802 + + PseudoVMFEQ_VFPR16_M2 = 7803 + + PseudoVMFEQ_VFPR16_M2_MASK = 7804 + + PseudoVMFEQ_VFPR16_M4 = 7805 + + PseudoVMFEQ_VFPR16_M4_MASK = 7806 + + PseudoVMFEQ_VFPR16_M8 = 7807 + + PseudoVMFEQ_VFPR16_M8_MASK = 7808 + + PseudoVMFEQ_VFPR16_MF2 = 7809 + + PseudoVMFEQ_VFPR16_MF2_MASK = 7810 + + PseudoVMFEQ_VFPR16_MF4 = 7811 + + PseudoVMFEQ_VFPR16_MF4_MASK = 7812 + + PseudoVMFEQ_VFPR32_M1 = 7813 + + PseudoVMFEQ_VFPR32_M1_MASK = 7814 + + PseudoVMFEQ_VFPR32_M2 = 7815 + + PseudoVMFEQ_VFPR32_M2_MASK = 7816 + + PseudoVMFEQ_VFPR32_M4 = 7817 + + PseudoVMFEQ_VFPR32_M4_MASK = 7818 + + PseudoVMFEQ_VFPR32_M8 = 7819 + + PseudoVMFEQ_VFPR32_M8_MASK = 7820 + + PseudoVMFEQ_VFPR32_MF2 = 7821 + + PseudoVMFEQ_VFPR32_MF2_MASK = 7822 + + PseudoVMFEQ_VFPR64_M1 = 7823 + + PseudoVMFEQ_VFPR64_M1_MASK = 7824 + + PseudoVMFEQ_VFPR64_M2 = 7825 + + PseudoVMFEQ_VFPR64_M2_MASK = 7826 + + PseudoVMFEQ_VFPR64_M4 = 7827 + + PseudoVMFEQ_VFPR64_M4_MASK = 7828 + + PseudoVMFEQ_VFPR64_M8 = 7829 + + PseudoVMFEQ_VFPR64_M8_MASK = 7830 + + PseudoVMFEQ_VV_M1 = 7831 + + PseudoVMFEQ_VV_M1_MASK = 7832 + + PseudoVMFEQ_VV_M2 = 7833 + + PseudoVMFEQ_VV_M2_MASK = 7834 + + PseudoVMFEQ_VV_M4 = 7835 + + PseudoVMFEQ_VV_M4_MASK = 7836 + + PseudoVMFEQ_VV_M8 = 7837 + + PseudoVMFEQ_VV_M8_MASK = 7838 + + PseudoVMFEQ_VV_MF2 = 7839 + + PseudoVMFEQ_VV_MF2_MASK = 7840 + + PseudoVMFEQ_VV_MF4 = 7841 + + PseudoVMFEQ_VV_MF4_MASK = 7842 + + PseudoVMFGE_ALT_VFPR16_M1 = 7843 + + PseudoVMFGE_ALT_VFPR16_M1_MASK = 7844 + + PseudoVMFGE_ALT_VFPR16_M2 = 7845 + + PseudoVMFGE_ALT_VFPR16_M2_MASK = 7846 + + PseudoVMFGE_ALT_VFPR16_M4 = 7847 + + PseudoVMFGE_ALT_VFPR16_M4_MASK = 7848 + + PseudoVMFGE_ALT_VFPR16_M8 = 7849 + + PseudoVMFGE_ALT_VFPR16_M8_MASK = 7850 + + PseudoVMFGE_ALT_VFPR16_MF2 = 7851 + + PseudoVMFGE_ALT_VFPR16_MF2_MASK = 7852 + + PseudoVMFGE_ALT_VFPR16_MF4 = 7853 + + PseudoVMFGE_ALT_VFPR16_MF4_MASK = 7854 + + PseudoVMFGE_ALT_VFPR32_M1 = 7855 + + PseudoVMFGE_ALT_VFPR32_M1_MASK = 7856 + + PseudoVMFGE_ALT_VFPR32_M2 = 7857 + + PseudoVMFGE_ALT_VFPR32_M2_MASK = 7858 + + PseudoVMFGE_ALT_VFPR32_M4 = 7859 + + PseudoVMFGE_ALT_VFPR32_M4_MASK = 7860 + + PseudoVMFGE_ALT_VFPR32_M8 = 7861 + + PseudoVMFGE_ALT_VFPR32_M8_MASK = 7862 + + PseudoVMFGE_ALT_VFPR32_MF2 = 7863 + + PseudoVMFGE_ALT_VFPR32_MF2_MASK = 7864 + + PseudoVMFGE_ALT_VFPR64_M1 = 7865 + + PseudoVMFGE_ALT_VFPR64_M1_MASK = 7866 + + PseudoVMFGE_ALT_VFPR64_M2 = 7867 + + PseudoVMFGE_ALT_VFPR64_M2_MASK = 7868 + + PseudoVMFGE_ALT_VFPR64_M4 = 7869 + + PseudoVMFGE_ALT_VFPR64_M4_MASK = 7870 + + PseudoVMFGE_ALT_VFPR64_M8 = 7871 + + PseudoVMFGE_ALT_VFPR64_M8_MASK = 7872 + + PseudoVMFGE_VFPR16_M1 = 7873 + + PseudoVMFGE_VFPR16_M1_MASK = 7874 + + PseudoVMFGE_VFPR16_M2 = 7875 + + PseudoVMFGE_VFPR16_M2_MASK = 7876 + + PseudoVMFGE_VFPR16_M4 = 7877 + + PseudoVMFGE_VFPR16_M4_MASK = 7878 + + PseudoVMFGE_VFPR16_M8 = 7879 + + PseudoVMFGE_VFPR16_M8_MASK = 7880 + + PseudoVMFGE_VFPR16_MF2 = 7881 + + PseudoVMFGE_VFPR16_MF2_MASK = 7882 + + PseudoVMFGE_VFPR16_MF4 = 7883 + + PseudoVMFGE_VFPR16_MF4_MASK = 7884 + + PseudoVMFGE_VFPR32_M1 = 7885 + + PseudoVMFGE_VFPR32_M1_MASK = 7886 + + PseudoVMFGE_VFPR32_M2 = 7887 + + PseudoVMFGE_VFPR32_M2_MASK = 7888 + + PseudoVMFGE_VFPR32_M4 = 7889 + + PseudoVMFGE_VFPR32_M4_MASK = 7890 + + PseudoVMFGE_VFPR32_M8 = 7891 + + PseudoVMFGE_VFPR32_M8_MASK = 7892 + + PseudoVMFGE_VFPR32_MF2 = 7893 + + PseudoVMFGE_VFPR32_MF2_MASK = 7894 + + PseudoVMFGE_VFPR64_M1 = 7895 + + PseudoVMFGE_VFPR64_M1_MASK = 7896 + + PseudoVMFGE_VFPR64_M2 = 7897 + + PseudoVMFGE_VFPR64_M2_MASK = 7898 + + PseudoVMFGE_VFPR64_M4 = 7899 + + PseudoVMFGE_VFPR64_M4_MASK = 7900 + + PseudoVMFGE_VFPR64_M8 = 7901 + + PseudoVMFGE_VFPR64_M8_MASK = 7902 + + PseudoVMFGT_ALT_VFPR16_M1 = 7903 + + PseudoVMFGT_ALT_VFPR16_M1_MASK = 7904 + + PseudoVMFGT_ALT_VFPR16_M2 = 7905 + + PseudoVMFGT_ALT_VFPR16_M2_MASK = 7906 + + PseudoVMFGT_ALT_VFPR16_M4 = 7907 + + PseudoVMFGT_ALT_VFPR16_M4_MASK = 7908 + + PseudoVMFGT_ALT_VFPR16_M8 = 7909 + + PseudoVMFGT_ALT_VFPR16_M8_MASK = 7910 + + PseudoVMFGT_ALT_VFPR16_MF2 = 7911 + + PseudoVMFGT_ALT_VFPR16_MF2_MASK = 7912 + + PseudoVMFGT_ALT_VFPR16_MF4 = 7913 + + PseudoVMFGT_ALT_VFPR16_MF4_MASK = 7914 + + PseudoVMFGT_ALT_VFPR32_M1 = 7915 + + PseudoVMFGT_ALT_VFPR32_M1_MASK = 7916 + + PseudoVMFGT_ALT_VFPR32_M2 = 7917 + + PseudoVMFGT_ALT_VFPR32_M2_MASK = 7918 + + PseudoVMFGT_ALT_VFPR32_M4 = 7919 + + PseudoVMFGT_ALT_VFPR32_M4_MASK = 7920 + + PseudoVMFGT_ALT_VFPR32_M8 = 7921 + + PseudoVMFGT_ALT_VFPR32_M8_MASK = 7922 + + PseudoVMFGT_ALT_VFPR32_MF2 = 7923 + + PseudoVMFGT_ALT_VFPR32_MF2_MASK = 7924 + + PseudoVMFGT_ALT_VFPR64_M1 = 7925 + + PseudoVMFGT_ALT_VFPR64_M1_MASK = 7926 + + PseudoVMFGT_ALT_VFPR64_M2 = 7927 + + PseudoVMFGT_ALT_VFPR64_M2_MASK = 7928 + + PseudoVMFGT_ALT_VFPR64_M4 = 7929 + + PseudoVMFGT_ALT_VFPR64_M4_MASK = 7930 + + PseudoVMFGT_ALT_VFPR64_M8 = 7931 + + PseudoVMFGT_ALT_VFPR64_M8_MASK = 7932 + + PseudoVMFGT_VFPR16_M1 = 7933 + + PseudoVMFGT_VFPR16_M1_MASK = 7934 + + PseudoVMFGT_VFPR16_M2 = 7935 + + PseudoVMFGT_VFPR16_M2_MASK = 7936 + + PseudoVMFGT_VFPR16_M4 = 7937 + + PseudoVMFGT_VFPR16_M4_MASK = 7938 + + PseudoVMFGT_VFPR16_M8 = 7939 + + PseudoVMFGT_VFPR16_M8_MASK = 7940 + + PseudoVMFGT_VFPR16_MF2 = 7941 + + PseudoVMFGT_VFPR16_MF2_MASK = 7942 + + PseudoVMFGT_VFPR16_MF4 = 7943 + + PseudoVMFGT_VFPR16_MF4_MASK = 7944 + + PseudoVMFGT_VFPR32_M1 = 7945 + + PseudoVMFGT_VFPR32_M1_MASK = 7946 + + PseudoVMFGT_VFPR32_M2 = 7947 + + PseudoVMFGT_VFPR32_M2_MASK = 7948 + + PseudoVMFGT_VFPR32_M4 = 7949 + + PseudoVMFGT_VFPR32_M4_MASK = 7950 + + PseudoVMFGT_VFPR32_M8 = 7951 + + PseudoVMFGT_VFPR32_M8_MASK = 7952 + + PseudoVMFGT_VFPR32_MF2 = 7953 + + PseudoVMFGT_VFPR32_MF2_MASK = 7954 + + PseudoVMFGT_VFPR64_M1 = 7955 + + PseudoVMFGT_VFPR64_M1_MASK = 7956 + + PseudoVMFGT_VFPR64_M2 = 7957 + + PseudoVMFGT_VFPR64_M2_MASK = 7958 + + PseudoVMFGT_VFPR64_M4 = 7959 + + PseudoVMFGT_VFPR64_M4_MASK = 7960 + + PseudoVMFGT_VFPR64_M8 = 7961 + + PseudoVMFGT_VFPR64_M8_MASK = 7962 + + PseudoVMFLE_ALT_VFPR16_M1 = 7963 + + PseudoVMFLE_ALT_VFPR16_M1_MASK = 7964 + + PseudoVMFLE_ALT_VFPR16_M2 = 7965 + + PseudoVMFLE_ALT_VFPR16_M2_MASK = 7966 + + PseudoVMFLE_ALT_VFPR16_M4 = 7967 + + PseudoVMFLE_ALT_VFPR16_M4_MASK = 7968 + + PseudoVMFLE_ALT_VFPR16_M8 = 7969 + + PseudoVMFLE_ALT_VFPR16_M8_MASK = 7970 + + PseudoVMFLE_ALT_VFPR16_MF2 = 7971 + + PseudoVMFLE_ALT_VFPR16_MF2_MASK = 7972 + + PseudoVMFLE_ALT_VFPR16_MF4 = 7973 + + PseudoVMFLE_ALT_VFPR16_MF4_MASK = 7974 + + PseudoVMFLE_ALT_VFPR32_M1 = 7975 + + PseudoVMFLE_ALT_VFPR32_M1_MASK = 7976 + + PseudoVMFLE_ALT_VFPR32_M2 = 7977 + + PseudoVMFLE_ALT_VFPR32_M2_MASK = 7978 + + PseudoVMFLE_ALT_VFPR32_M4 = 7979 + + PseudoVMFLE_ALT_VFPR32_M4_MASK = 7980 + + PseudoVMFLE_ALT_VFPR32_M8 = 7981 + + PseudoVMFLE_ALT_VFPR32_M8_MASK = 7982 + + PseudoVMFLE_ALT_VFPR32_MF2 = 7983 + + PseudoVMFLE_ALT_VFPR32_MF2_MASK = 7984 + + PseudoVMFLE_ALT_VFPR64_M1 = 7985 + + PseudoVMFLE_ALT_VFPR64_M1_MASK = 7986 + + PseudoVMFLE_ALT_VFPR64_M2 = 7987 + + PseudoVMFLE_ALT_VFPR64_M2_MASK = 7988 + + PseudoVMFLE_ALT_VFPR64_M4 = 7989 + + PseudoVMFLE_ALT_VFPR64_M4_MASK = 7990 + + PseudoVMFLE_ALT_VFPR64_M8 = 7991 + + PseudoVMFLE_ALT_VFPR64_M8_MASK = 7992 + + PseudoVMFLE_ALT_VV_M1 = 7993 + + PseudoVMFLE_ALT_VV_M1_MASK = 7994 + + PseudoVMFLE_ALT_VV_M2 = 7995 + + PseudoVMFLE_ALT_VV_M2_MASK = 7996 + + PseudoVMFLE_ALT_VV_M4 = 7997 + + PseudoVMFLE_ALT_VV_M4_MASK = 7998 + + PseudoVMFLE_ALT_VV_M8 = 7999 + + PseudoVMFLE_ALT_VV_M8_MASK = 8000 + + PseudoVMFLE_ALT_VV_MF2 = 8001 + + PseudoVMFLE_ALT_VV_MF2_MASK = 8002 + + PseudoVMFLE_ALT_VV_MF4 = 8003 + + PseudoVMFLE_ALT_VV_MF4_MASK = 8004 + + PseudoVMFLE_VFPR16_M1 = 8005 + + PseudoVMFLE_VFPR16_M1_MASK = 8006 + + PseudoVMFLE_VFPR16_M2 = 8007 + + PseudoVMFLE_VFPR16_M2_MASK = 8008 + + PseudoVMFLE_VFPR16_M4 = 8009 + + PseudoVMFLE_VFPR16_M4_MASK = 8010 + + PseudoVMFLE_VFPR16_M8 = 8011 + + PseudoVMFLE_VFPR16_M8_MASK = 8012 + + PseudoVMFLE_VFPR16_MF2 = 8013 + + PseudoVMFLE_VFPR16_MF2_MASK = 8014 + + PseudoVMFLE_VFPR16_MF4 = 8015 + + PseudoVMFLE_VFPR16_MF4_MASK = 8016 + + PseudoVMFLE_VFPR32_M1 = 8017 + + PseudoVMFLE_VFPR32_M1_MASK = 8018 + + PseudoVMFLE_VFPR32_M2 = 8019 + + PseudoVMFLE_VFPR32_M2_MASK = 8020 + + PseudoVMFLE_VFPR32_M4 = 8021 + + PseudoVMFLE_VFPR32_M4_MASK = 8022 + + PseudoVMFLE_VFPR32_M8 = 8023 + + PseudoVMFLE_VFPR32_M8_MASK = 8024 + + PseudoVMFLE_VFPR32_MF2 = 8025 + + PseudoVMFLE_VFPR32_MF2_MASK = 8026 + + PseudoVMFLE_VFPR64_M1 = 8027 + + PseudoVMFLE_VFPR64_M1_MASK = 8028 + + PseudoVMFLE_VFPR64_M2 = 8029 + + PseudoVMFLE_VFPR64_M2_MASK = 8030 + + PseudoVMFLE_VFPR64_M4 = 8031 + + PseudoVMFLE_VFPR64_M4_MASK = 8032 + + PseudoVMFLE_VFPR64_M8 = 8033 + + PseudoVMFLE_VFPR64_M8_MASK = 8034 + + PseudoVMFLE_VV_M1 = 8035 + + PseudoVMFLE_VV_M1_MASK = 8036 + + PseudoVMFLE_VV_M2 = 8037 + + PseudoVMFLE_VV_M2_MASK = 8038 + + PseudoVMFLE_VV_M4 = 8039 + + PseudoVMFLE_VV_M4_MASK = 8040 + + PseudoVMFLE_VV_M8 = 8041 + + PseudoVMFLE_VV_M8_MASK = 8042 + + PseudoVMFLE_VV_MF2 = 8043 + + PseudoVMFLE_VV_MF2_MASK = 8044 + + PseudoVMFLE_VV_MF4 = 8045 + + PseudoVMFLE_VV_MF4_MASK = 8046 + + PseudoVMFLT_ALT_VFPR16_M1 = 8047 + + PseudoVMFLT_ALT_VFPR16_M1_MASK = 8048 + + PseudoVMFLT_ALT_VFPR16_M2 = 8049 + + PseudoVMFLT_ALT_VFPR16_M2_MASK = 8050 + + PseudoVMFLT_ALT_VFPR16_M4 = 8051 + + PseudoVMFLT_ALT_VFPR16_M4_MASK = 8052 + + PseudoVMFLT_ALT_VFPR16_M8 = 8053 + + PseudoVMFLT_ALT_VFPR16_M8_MASK = 8054 + + PseudoVMFLT_ALT_VFPR16_MF2 = 8055 + + PseudoVMFLT_ALT_VFPR16_MF2_MASK = 8056 + + PseudoVMFLT_ALT_VFPR16_MF4 = 8057 + + PseudoVMFLT_ALT_VFPR16_MF4_MASK = 8058 + + PseudoVMFLT_ALT_VFPR32_M1 = 8059 + + PseudoVMFLT_ALT_VFPR32_M1_MASK = 8060 + + PseudoVMFLT_ALT_VFPR32_M2 = 8061 + + PseudoVMFLT_ALT_VFPR32_M2_MASK = 8062 + + PseudoVMFLT_ALT_VFPR32_M4 = 8063 + + PseudoVMFLT_ALT_VFPR32_M4_MASK = 8064 + + PseudoVMFLT_ALT_VFPR32_M8 = 8065 + + PseudoVMFLT_ALT_VFPR32_M8_MASK = 8066 + + PseudoVMFLT_ALT_VFPR32_MF2 = 8067 + + PseudoVMFLT_ALT_VFPR32_MF2_MASK = 8068 + + PseudoVMFLT_ALT_VFPR64_M1 = 8069 + + PseudoVMFLT_ALT_VFPR64_M1_MASK = 8070 + + PseudoVMFLT_ALT_VFPR64_M2 = 8071 + + PseudoVMFLT_ALT_VFPR64_M2_MASK = 8072 + + PseudoVMFLT_ALT_VFPR64_M4 = 8073 + + PseudoVMFLT_ALT_VFPR64_M4_MASK = 8074 + + PseudoVMFLT_ALT_VFPR64_M8 = 8075 + + PseudoVMFLT_ALT_VFPR64_M8_MASK = 8076 + + PseudoVMFLT_ALT_VV_M1 = 8077 + + PseudoVMFLT_ALT_VV_M1_MASK = 8078 + + PseudoVMFLT_ALT_VV_M2 = 8079 + + PseudoVMFLT_ALT_VV_M2_MASK = 8080 + + PseudoVMFLT_ALT_VV_M4 = 8081 + + PseudoVMFLT_ALT_VV_M4_MASK = 8082 + + PseudoVMFLT_ALT_VV_M8 = 8083 + + PseudoVMFLT_ALT_VV_M8_MASK = 8084 + + PseudoVMFLT_ALT_VV_MF2 = 8085 + + PseudoVMFLT_ALT_VV_MF2_MASK = 8086 + + PseudoVMFLT_ALT_VV_MF4 = 8087 + + PseudoVMFLT_ALT_VV_MF4_MASK = 8088 + + PseudoVMFLT_VFPR16_M1 = 8089 + + PseudoVMFLT_VFPR16_M1_MASK = 8090 + + PseudoVMFLT_VFPR16_M2 = 8091 + + PseudoVMFLT_VFPR16_M2_MASK = 8092 + + PseudoVMFLT_VFPR16_M4 = 8093 + + PseudoVMFLT_VFPR16_M4_MASK = 8094 + + PseudoVMFLT_VFPR16_M8 = 8095 + + PseudoVMFLT_VFPR16_M8_MASK = 8096 + + PseudoVMFLT_VFPR16_MF2 = 8097 + + PseudoVMFLT_VFPR16_MF2_MASK = 8098 + + PseudoVMFLT_VFPR16_MF4 = 8099 + + PseudoVMFLT_VFPR16_MF4_MASK = 8100 + + PseudoVMFLT_VFPR32_M1 = 8101 + + PseudoVMFLT_VFPR32_M1_MASK = 8102 + + PseudoVMFLT_VFPR32_M2 = 8103 + + PseudoVMFLT_VFPR32_M2_MASK = 8104 + + PseudoVMFLT_VFPR32_M4 = 8105 + + PseudoVMFLT_VFPR32_M4_MASK = 8106 + + PseudoVMFLT_VFPR32_M8 = 8107 + + PseudoVMFLT_VFPR32_M8_MASK = 8108 + + PseudoVMFLT_VFPR32_MF2 = 8109 + + PseudoVMFLT_VFPR32_MF2_MASK = 8110 + + PseudoVMFLT_VFPR64_M1 = 8111 + + PseudoVMFLT_VFPR64_M1_MASK = 8112 + + PseudoVMFLT_VFPR64_M2 = 8113 + + PseudoVMFLT_VFPR64_M2_MASK = 8114 + + PseudoVMFLT_VFPR64_M4 = 8115 + + PseudoVMFLT_VFPR64_M4_MASK = 8116 + + PseudoVMFLT_VFPR64_M8 = 8117 + + PseudoVMFLT_VFPR64_M8_MASK = 8118 + + PseudoVMFLT_VV_M1 = 8119 + + PseudoVMFLT_VV_M1_MASK = 8120 + + PseudoVMFLT_VV_M2 = 8121 + + PseudoVMFLT_VV_M2_MASK = 8122 + + PseudoVMFLT_VV_M4 = 8123 + + PseudoVMFLT_VV_M4_MASK = 8124 + + PseudoVMFLT_VV_M8 = 8125 + + PseudoVMFLT_VV_M8_MASK = 8126 + + PseudoVMFLT_VV_MF2 = 8127 + + PseudoVMFLT_VV_MF2_MASK = 8128 + + PseudoVMFLT_VV_MF4 = 8129 + + PseudoVMFLT_VV_MF4_MASK = 8130 + + PseudoVMFNE_ALT_VFPR16_M1 = 8131 + + PseudoVMFNE_ALT_VFPR16_M1_MASK = 8132 + + PseudoVMFNE_ALT_VFPR16_M2 = 8133 + + PseudoVMFNE_ALT_VFPR16_M2_MASK = 8134 + + PseudoVMFNE_ALT_VFPR16_M4 = 8135 + + PseudoVMFNE_ALT_VFPR16_M4_MASK = 8136 + + PseudoVMFNE_ALT_VFPR16_M8 = 8137 + + PseudoVMFNE_ALT_VFPR16_M8_MASK = 8138 + + PseudoVMFNE_ALT_VFPR16_MF2 = 8139 + + PseudoVMFNE_ALT_VFPR16_MF2_MASK = 8140 + + PseudoVMFNE_ALT_VFPR16_MF4 = 8141 + + PseudoVMFNE_ALT_VFPR16_MF4_MASK = 8142 + + PseudoVMFNE_ALT_VFPR32_M1 = 8143 + + PseudoVMFNE_ALT_VFPR32_M1_MASK = 8144 + + PseudoVMFNE_ALT_VFPR32_M2 = 8145 + + PseudoVMFNE_ALT_VFPR32_M2_MASK = 8146 + + PseudoVMFNE_ALT_VFPR32_M4 = 8147 + + PseudoVMFNE_ALT_VFPR32_M4_MASK = 8148 + + PseudoVMFNE_ALT_VFPR32_M8 = 8149 + + PseudoVMFNE_ALT_VFPR32_M8_MASK = 8150 + + PseudoVMFNE_ALT_VFPR32_MF2 = 8151 + + PseudoVMFNE_ALT_VFPR32_MF2_MASK = 8152 + + PseudoVMFNE_ALT_VFPR64_M1 = 8153 + + PseudoVMFNE_ALT_VFPR64_M1_MASK = 8154 + + PseudoVMFNE_ALT_VFPR64_M2 = 8155 + + PseudoVMFNE_ALT_VFPR64_M2_MASK = 8156 + + PseudoVMFNE_ALT_VFPR64_M4 = 8157 + + PseudoVMFNE_ALT_VFPR64_M4_MASK = 8158 + + PseudoVMFNE_ALT_VFPR64_M8 = 8159 + + PseudoVMFNE_ALT_VFPR64_M8_MASK = 8160 + + PseudoVMFNE_ALT_VV_M1 = 8161 + + PseudoVMFNE_ALT_VV_M1_MASK = 8162 + + PseudoVMFNE_ALT_VV_M2 = 8163 + + PseudoVMFNE_ALT_VV_M2_MASK = 8164 + + PseudoVMFNE_ALT_VV_M4 = 8165 + + PseudoVMFNE_ALT_VV_M4_MASK = 8166 + + PseudoVMFNE_ALT_VV_M8 = 8167 + + PseudoVMFNE_ALT_VV_M8_MASK = 8168 + + PseudoVMFNE_ALT_VV_MF2 = 8169 + + PseudoVMFNE_ALT_VV_MF2_MASK = 8170 + + PseudoVMFNE_ALT_VV_MF4 = 8171 + + PseudoVMFNE_ALT_VV_MF4_MASK = 8172 + + PseudoVMFNE_VFPR16_M1 = 8173 + + PseudoVMFNE_VFPR16_M1_MASK = 8174 + + PseudoVMFNE_VFPR16_M2 = 8175 + + PseudoVMFNE_VFPR16_M2_MASK = 8176 + + PseudoVMFNE_VFPR16_M4 = 8177 + + PseudoVMFNE_VFPR16_M4_MASK = 8178 + + PseudoVMFNE_VFPR16_M8 = 8179 + + PseudoVMFNE_VFPR16_M8_MASK = 8180 + + PseudoVMFNE_VFPR16_MF2 = 8181 + + PseudoVMFNE_VFPR16_MF2_MASK = 8182 + + PseudoVMFNE_VFPR16_MF4 = 8183 + + PseudoVMFNE_VFPR16_MF4_MASK = 8184 + + PseudoVMFNE_VFPR32_M1 = 8185 + + PseudoVMFNE_VFPR32_M1_MASK = 8186 + + PseudoVMFNE_VFPR32_M2 = 8187 + + PseudoVMFNE_VFPR32_M2_MASK = 8188 + + PseudoVMFNE_VFPR32_M4 = 8189 + + PseudoVMFNE_VFPR32_M4_MASK = 8190 + + PseudoVMFNE_VFPR32_M8 = 8191 + + PseudoVMFNE_VFPR32_M8_MASK = 8192 + + PseudoVMFNE_VFPR32_MF2 = 8193 + + PseudoVMFNE_VFPR32_MF2_MASK = 8194 + + PseudoVMFNE_VFPR64_M1 = 8195 + + PseudoVMFNE_VFPR64_M1_MASK = 8196 + + PseudoVMFNE_VFPR64_M2 = 8197 + + PseudoVMFNE_VFPR64_M2_MASK = 8198 + + PseudoVMFNE_VFPR64_M4 = 8199 + + PseudoVMFNE_VFPR64_M4_MASK = 8200 + + PseudoVMFNE_VFPR64_M8 = 8201 + + PseudoVMFNE_VFPR64_M8_MASK = 8202 + + PseudoVMFNE_VV_M1 = 8203 + + PseudoVMFNE_VV_M1_MASK = 8204 + + PseudoVMFNE_VV_M2 = 8205 + + PseudoVMFNE_VV_M2_MASK = 8206 + + PseudoVMFNE_VV_M4 = 8207 + + PseudoVMFNE_VV_M4_MASK = 8208 + + PseudoVMFNE_VV_M8 = 8209 + + PseudoVMFNE_VV_M8_MASK = 8210 + + PseudoVMFNE_VV_MF2 = 8211 + + PseudoVMFNE_VV_MF2_MASK = 8212 + + PseudoVMFNE_VV_MF4 = 8213 + + PseudoVMFNE_VV_MF4_MASK = 8214 + + PseudoVMINU_VV_M1 = 8215 + + PseudoVMINU_VV_M1_MASK = 8216 + + PseudoVMINU_VV_M2 = 8217 + + PseudoVMINU_VV_M2_MASK = 8218 + + PseudoVMINU_VV_M4 = 8219 + + PseudoVMINU_VV_M4_MASK = 8220 + + PseudoVMINU_VV_M8 = 8221 + + PseudoVMINU_VV_M8_MASK = 8222 + + PseudoVMINU_VV_MF2 = 8223 + + PseudoVMINU_VV_MF2_MASK = 8224 + + PseudoVMINU_VV_MF4 = 8225 + + PseudoVMINU_VV_MF4_MASK = 8226 + + PseudoVMINU_VV_MF8 = 8227 + + PseudoVMINU_VV_MF8_MASK = 8228 + + PseudoVMINU_VX_M1 = 8229 + + PseudoVMINU_VX_M1_MASK = 8230 + + PseudoVMINU_VX_M2 = 8231 + + PseudoVMINU_VX_M2_MASK = 8232 + + PseudoVMINU_VX_M4 = 8233 + + PseudoVMINU_VX_M4_MASK = 8234 + + PseudoVMINU_VX_M8 = 8235 + + PseudoVMINU_VX_M8_MASK = 8236 + + PseudoVMINU_VX_MF2 = 8237 + + PseudoVMINU_VX_MF2_MASK = 8238 + + PseudoVMINU_VX_MF4 = 8239 + + PseudoVMINU_VX_MF4_MASK = 8240 + + PseudoVMINU_VX_MF8 = 8241 + + PseudoVMINU_VX_MF8_MASK = 8242 + + PseudoVMIN_VV_M1 = 8243 + + PseudoVMIN_VV_M1_MASK = 8244 + + PseudoVMIN_VV_M2 = 8245 + + PseudoVMIN_VV_M2_MASK = 8246 + + PseudoVMIN_VV_M4 = 8247 + + PseudoVMIN_VV_M4_MASK = 8248 + + PseudoVMIN_VV_M8 = 8249 + + PseudoVMIN_VV_M8_MASK = 8250 + + PseudoVMIN_VV_MF2 = 8251 + + PseudoVMIN_VV_MF2_MASK = 8252 + + PseudoVMIN_VV_MF4 = 8253 + + PseudoVMIN_VV_MF4_MASK = 8254 + + PseudoVMIN_VV_MF8 = 8255 + + PseudoVMIN_VV_MF8_MASK = 8256 + + PseudoVMIN_VX_M1 = 8257 + + PseudoVMIN_VX_M1_MASK = 8258 + + PseudoVMIN_VX_M2 = 8259 + + PseudoVMIN_VX_M2_MASK = 8260 + + PseudoVMIN_VX_M4 = 8261 + + PseudoVMIN_VX_M4_MASK = 8262 + + PseudoVMIN_VX_M8 = 8263 + + PseudoVMIN_VX_M8_MASK = 8264 + + PseudoVMIN_VX_MF2 = 8265 + + PseudoVMIN_VX_MF2_MASK = 8266 + + PseudoVMIN_VX_MF4 = 8267 + + PseudoVMIN_VX_MF4_MASK = 8268 + + PseudoVMIN_VX_MF8 = 8269 + + PseudoVMIN_VX_MF8_MASK = 8270 + + PseudoVMNAND_MM_B1 = 8271 + + PseudoVMNAND_MM_B16 = 8272 + + PseudoVMNAND_MM_B2 = 8273 + + PseudoVMNAND_MM_B32 = 8274 + + PseudoVMNAND_MM_B4 = 8275 + + PseudoVMNAND_MM_B64 = 8276 + + PseudoVMNAND_MM_B8 = 8277 + + PseudoVMNOR_MM_B1 = 8278 + + PseudoVMNOR_MM_B16 = 8279 + + PseudoVMNOR_MM_B2 = 8280 + + PseudoVMNOR_MM_B32 = 8281 + + PseudoVMNOR_MM_B4 = 8282 + + PseudoVMNOR_MM_B64 = 8283 + + PseudoVMNOR_MM_B8 = 8284 + + PseudoVMORN_MM_B1 = 8285 + + PseudoVMORN_MM_B16 = 8286 + + PseudoVMORN_MM_B2 = 8287 + + PseudoVMORN_MM_B32 = 8288 + + PseudoVMORN_MM_B4 = 8289 + + PseudoVMORN_MM_B64 = 8290 + + PseudoVMORN_MM_B8 = 8291 + + PseudoVMOR_MM_B1 = 8292 + + PseudoVMOR_MM_B16 = 8293 + + PseudoVMOR_MM_B2 = 8294 + + PseudoVMOR_MM_B32 = 8295 + + PseudoVMOR_MM_B4 = 8296 + + PseudoVMOR_MM_B64 = 8297 + + PseudoVMOR_MM_B8 = 8298 + + PseudoVMSBC_VVM_M1 = 8299 + + PseudoVMSBC_VVM_M2 = 8300 + + PseudoVMSBC_VVM_M4 = 8301 + + PseudoVMSBC_VVM_M8 = 8302 + + PseudoVMSBC_VVM_MF2 = 8303 + + PseudoVMSBC_VVM_MF4 = 8304 + + PseudoVMSBC_VVM_MF8 = 8305 + + PseudoVMSBC_VV_M1 = 8306 + + PseudoVMSBC_VV_M2 = 8307 + + PseudoVMSBC_VV_M4 = 8308 + + PseudoVMSBC_VV_M8 = 8309 + + PseudoVMSBC_VV_MF2 = 8310 + + PseudoVMSBC_VV_MF4 = 8311 + + PseudoVMSBC_VV_MF8 = 8312 + + PseudoVMSBC_VXM_M1 = 8313 + + PseudoVMSBC_VXM_M2 = 8314 + + PseudoVMSBC_VXM_M4 = 8315 + + PseudoVMSBC_VXM_M8 = 8316 + + PseudoVMSBC_VXM_MF2 = 8317 + + PseudoVMSBC_VXM_MF4 = 8318 + + PseudoVMSBC_VXM_MF8 = 8319 + + PseudoVMSBC_VX_M1 = 8320 + + PseudoVMSBC_VX_M2 = 8321 + + PseudoVMSBC_VX_M4 = 8322 + + PseudoVMSBC_VX_M8 = 8323 + + PseudoVMSBC_VX_MF2 = 8324 + + PseudoVMSBC_VX_MF4 = 8325 + + PseudoVMSBC_VX_MF8 = 8326 + + PseudoVMSBF_M_B1 = 8327 + + PseudoVMSBF_M_B16 = 8328 + + PseudoVMSBF_M_B16_MASK = 8329 + + PseudoVMSBF_M_B1_MASK = 8330 + + PseudoVMSBF_M_B2 = 8331 + + PseudoVMSBF_M_B2_MASK = 8332 + + PseudoVMSBF_M_B32 = 8333 + + PseudoVMSBF_M_B32_MASK = 8334 + + PseudoVMSBF_M_B4 = 8335 + + PseudoVMSBF_M_B4_MASK = 8336 + + PseudoVMSBF_M_B64 = 8337 + + PseudoVMSBF_M_B64_MASK = 8338 + + PseudoVMSBF_M_B8 = 8339 + + PseudoVMSBF_M_B8_MASK = 8340 + + PseudoVMSEQ_VI_M1 = 8341 + + PseudoVMSEQ_VI_M1_MASK = 8342 + + PseudoVMSEQ_VI_M2 = 8343 + + PseudoVMSEQ_VI_M2_MASK = 8344 + + PseudoVMSEQ_VI_M4 = 8345 + + PseudoVMSEQ_VI_M4_MASK = 8346 + + PseudoVMSEQ_VI_M8 = 8347 + + PseudoVMSEQ_VI_M8_MASK = 8348 + + PseudoVMSEQ_VI_MF2 = 8349 + + PseudoVMSEQ_VI_MF2_MASK = 8350 + + PseudoVMSEQ_VI_MF4 = 8351 + + PseudoVMSEQ_VI_MF4_MASK = 8352 + + PseudoVMSEQ_VI_MF8 = 8353 + + PseudoVMSEQ_VI_MF8_MASK = 8354 + + PseudoVMSEQ_VV_M1 = 8355 + + PseudoVMSEQ_VV_M1_MASK = 8356 + + PseudoVMSEQ_VV_M2 = 8357 + + PseudoVMSEQ_VV_M2_MASK = 8358 + + PseudoVMSEQ_VV_M4 = 8359 + + PseudoVMSEQ_VV_M4_MASK = 8360 + + PseudoVMSEQ_VV_M8 = 8361 + + PseudoVMSEQ_VV_M8_MASK = 8362 + + PseudoVMSEQ_VV_MF2 = 8363 + + PseudoVMSEQ_VV_MF2_MASK = 8364 + + PseudoVMSEQ_VV_MF4 = 8365 + + PseudoVMSEQ_VV_MF4_MASK = 8366 + + PseudoVMSEQ_VV_MF8 = 8367 + + PseudoVMSEQ_VV_MF8_MASK = 8368 + + PseudoVMSEQ_VX_M1 = 8369 + + PseudoVMSEQ_VX_M1_MASK = 8370 + + PseudoVMSEQ_VX_M2 = 8371 + + PseudoVMSEQ_VX_M2_MASK = 8372 + + PseudoVMSEQ_VX_M4 = 8373 + + PseudoVMSEQ_VX_M4_MASK = 8374 + + PseudoVMSEQ_VX_M8 = 8375 + + PseudoVMSEQ_VX_M8_MASK = 8376 + + PseudoVMSEQ_VX_MF2 = 8377 + + PseudoVMSEQ_VX_MF2_MASK = 8378 + + PseudoVMSEQ_VX_MF4 = 8379 + + PseudoVMSEQ_VX_MF4_MASK = 8380 + + PseudoVMSEQ_VX_MF8 = 8381 + + PseudoVMSEQ_VX_MF8_MASK = 8382 + + PseudoVMSET_M_B1 = 8383 + + PseudoVMSET_M_B16 = 8384 + + PseudoVMSET_M_B2 = 8385 + + PseudoVMSET_M_B32 = 8386 + + PseudoVMSET_M_B4 = 8387 + + PseudoVMSET_M_B64 = 8388 + + PseudoVMSET_M_B8 = 8389 + + PseudoVMSGEU_VI = 8390 + + PseudoVMSGEU_VX = 8391 + + PseudoVMSGEU_VX_M = 8392 + + PseudoVMSGEU_VX_M_T = 8393 + + PseudoVMSGE_VI = 8394 + + PseudoVMSGE_VX = 8395 + + PseudoVMSGE_VX_M = 8396 + + PseudoVMSGE_VX_M_T = 8397 + + PseudoVMSGTU_VI_M1 = 8398 + + PseudoVMSGTU_VI_M1_MASK = 8399 + + PseudoVMSGTU_VI_M2 = 8400 + + PseudoVMSGTU_VI_M2_MASK = 8401 + + PseudoVMSGTU_VI_M4 = 8402 + + PseudoVMSGTU_VI_M4_MASK = 8403 + + PseudoVMSGTU_VI_M8 = 8404 + + PseudoVMSGTU_VI_M8_MASK = 8405 + + PseudoVMSGTU_VI_MF2 = 8406 + + PseudoVMSGTU_VI_MF2_MASK = 8407 + + PseudoVMSGTU_VI_MF4 = 8408 + + PseudoVMSGTU_VI_MF4_MASK = 8409 + + PseudoVMSGTU_VI_MF8 = 8410 + + PseudoVMSGTU_VI_MF8_MASK = 8411 + + PseudoVMSGTU_VX_M1 = 8412 + + PseudoVMSGTU_VX_M1_MASK = 8413 + + PseudoVMSGTU_VX_M2 = 8414 + + PseudoVMSGTU_VX_M2_MASK = 8415 + + PseudoVMSGTU_VX_M4 = 8416 + + PseudoVMSGTU_VX_M4_MASK = 8417 + + PseudoVMSGTU_VX_M8 = 8418 + + PseudoVMSGTU_VX_M8_MASK = 8419 + + PseudoVMSGTU_VX_MF2 = 8420 + + PseudoVMSGTU_VX_MF2_MASK = 8421 + + PseudoVMSGTU_VX_MF4 = 8422 + + PseudoVMSGTU_VX_MF4_MASK = 8423 + + PseudoVMSGTU_VX_MF8 = 8424 + + PseudoVMSGTU_VX_MF8_MASK = 8425 + + PseudoVMSGT_VI_M1 = 8426 + + PseudoVMSGT_VI_M1_MASK = 8427 + + PseudoVMSGT_VI_M2 = 8428 + + PseudoVMSGT_VI_M2_MASK = 8429 + + PseudoVMSGT_VI_M4 = 8430 + + PseudoVMSGT_VI_M4_MASK = 8431 + + PseudoVMSGT_VI_M8 = 8432 + + PseudoVMSGT_VI_M8_MASK = 8433 + + PseudoVMSGT_VI_MF2 = 8434 + + PseudoVMSGT_VI_MF2_MASK = 8435 + + PseudoVMSGT_VI_MF4 = 8436 + + PseudoVMSGT_VI_MF4_MASK = 8437 + + PseudoVMSGT_VI_MF8 = 8438 + + PseudoVMSGT_VI_MF8_MASK = 8439 + + PseudoVMSGT_VX_M1 = 8440 + + PseudoVMSGT_VX_M1_MASK = 8441 + + PseudoVMSGT_VX_M2 = 8442 + + PseudoVMSGT_VX_M2_MASK = 8443 + + PseudoVMSGT_VX_M4 = 8444 + + PseudoVMSGT_VX_M4_MASK = 8445 + + PseudoVMSGT_VX_M8 = 8446 + + PseudoVMSGT_VX_M8_MASK = 8447 + + PseudoVMSGT_VX_MF2 = 8448 + + PseudoVMSGT_VX_MF2_MASK = 8449 + + PseudoVMSGT_VX_MF4 = 8450 + + PseudoVMSGT_VX_MF4_MASK = 8451 + + PseudoVMSGT_VX_MF8 = 8452 + + PseudoVMSGT_VX_MF8_MASK = 8453 + + PseudoVMSIF_M_B1 = 8454 + + PseudoVMSIF_M_B16 = 8455 + + PseudoVMSIF_M_B16_MASK = 8456 + + PseudoVMSIF_M_B1_MASK = 8457 + + PseudoVMSIF_M_B2 = 8458 + + PseudoVMSIF_M_B2_MASK = 8459 + + PseudoVMSIF_M_B32 = 8460 + + PseudoVMSIF_M_B32_MASK = 8461 + + PseudoVMSIF_M_B4 = 8462 + + PseudoVMSIF_M_B4_MASK = 8463 + + PseudoVMSIF_M_B64 = 8464 + + PseudoVMSIF_M_B64_MASK = 8465 + + PseudoVMSIF_M_B8 = 8466 + + PseudoVMSIF_M_B8_MASK = 8467 + + PseudoVMSLEU_VI_M1 = 8468 + + PseudoVMSLEU_VI_M1_MASK = 8469 + + PseudoVMSLEU_VI_M2 = 8470 + + PseudoVMSLEU_VI_M2_MASK = 8471 + + PseudoVMSLEU_VI_M4 = 8472 + + PseudoVMSLEU_VI_M4_MASK = 8473 + + PseudoVMSLEU_VI_M8 = 8474 + + PseudoVMSLEU_VI_M8_MASK = 8475 + + PseudoVMSLEU_VI_MF2 = 8476 + + PseudoVMSLEU_VI_MF2_MASK = 8477 + + PseudoVMSLEU_VI_MF4 = 8478 + + PseudoVMSLEU_VI_MF4_MASK = 8479 + + PseudoVMSLEU_VI_MF8 = 8480 + + PseudoVMSLEU_VI_MF8_MASK = 8481 + + PseudoVMSLEU_VV_M1 = 8482 + + PseudoVMSLEU_VV_M1_MASK = 8483 + + PseudoVMSLEU_VV_M2 = 8484 + + PseudoVMSLEU_VV_M2_MASK = 8485 + + PseudoVMSLEU_VV_M4 = 8486 + + PseudoVMSLEU_VV_M4_MASK = 8487 + + PseudoVMSLEU_VV_M8 = 8488 + + PseudoVMSLEU_VV_M8_MASK = 8489 + + PseudoVMSLEU_VV_MF2 = 8490 + + PseudoVMSLEU_VV_MF2_MASK = 8491 + + PseudoVMSLEU_VV_MF4 = 8492 + + PseudoVMSLEU_VV_MF4_MASK = 8493 + + PseudoVMSLEU_VV_MF8 = 8494 + + PseudoVMSLEU_VV_MF8_MASK = 8495 + + PseudoVMSLEU_VX_M1 = 8496 + + PseudoVMSLEU_VX_M1_MASK = 8497 + + PseudoVMSLEU_VX_M2 = 8498 + + PseudoVMSLEU_VX_M2_MASK = 8499 + + PseudoVMSLEU_VX_M4 = 8500 + + PseudoVMSLEU_VX_M4_MASK = 8501 + + PseudoVMSLEU_VX_M8 = 8502 + + PseudoVMSLEU_VX_M8_MASK = 8503 + + PseudoVMSLEU_VX_MF2 = 8504 + + PseudoVMSLEU_VX_MF2_MASK = 8505 + + PseudoVMSLEU_VX_MF4 = 8506 + + PseudoVMSLEU_VX_MF4_MASK = 8507 + + PseudoVMSLEU_VX_MF8 = 8508 + + PseudoVMSLEU_VX_MF8_MASK = 8509 + + PseudoVMSLE_VI_M1 = 8510 + + PseudoVMSLE_VI_M1_MASK = 8511 + + PseudoVMSLE_VI_M2 = 8512 + + PseudoVMSLE_VI_M2_MASK = 8513 + + PseudoVMSLE_VI_M4 = 8514 + + PseudoVMSLE_VI_M4_MASK = 8515 + + PseudoVMSLE_VI_M8 = 8516 + + PseudoVMSLE_VI_M8_MASK = 8517 + + PseudoVMSLE_VI_MF2 = 8518 + + PseudoVMSLE_VI_MF2_MASK = 8519 + + PseudoVMSLE_VI_MF4 = 8520 + + PseudoVMSLE_VI_MF4_MASK = 8521 + + PseudoVMSLE_VI_MF8 = 8522 + + PseudoVMSLE_VI_MF8_MASK = 8523 + + PseudoVMSLE_VV_M1 = 8524 + + PseudoVMSLE_VV_M1_MASK = 8525 + + PseudoVMSLE_VV_M2 = 8526 + + PseudoVMSLE_VV_M2_MASK = 8527 + + PseudoVMSLE_VV_M4 = 8528 + + PseudoVMSLE_VV_M4_MASK = 8529 + + PseudoVMSLE_VV_M8 = 8530 + + PseudoVMSLE_VV_M8_MASK = 8531 + + PseudoVMSLE_VV_MF2 = 8532 + + PseudoVMSLE_VV_MF2_MASK = 8533 + + PseudoVMSLE_VV_MF4 = 8534 + + PseudoVMSLE_VV_MF4_MASK = 8535 + + PseudoVMSLE_VV_MF8 = 8536 + + PseudoVMSLE_VV_MF8_MASK = 8537 + + PseudoVMSLE_VX_M1 = 8538 + + PseudoVMSLE_VX_M1_MASK = 8539 + + PseudoVMSLE_VX_M2 = 8540 + + PseudoVMSLE_VX_M2_MASK = 8541 + + PseudoVMSLE_VX_M4 = 8542 + + PseudoVMSLE_VX_M4_MASK = 8543 + + PseudoVMSLE_VX_M8 = 8544 + + PseudoVMSLE_VX_M8_MASK = 8545 + + PseudoVMSLE_VX_MF2 = 8546 + + PseudoVMSLE_VX_MF2_MASK = 8547 + + PseudoVMSLE_VX_MF4 = 8548 + + PseudoVMSLE_VX_MF4_MASK = 8549 + + PseudoVMSLE_VX_MF8 = 8550 + + PseudoVMSLE_VX_MF8_MASK = 8551 + + PseudoVMSLTU_VI = 8552 + + PseudoVMSLTU_VV_M1 = 8553 + + PseudoVMSLTU_VV_M1_MASK = 8554 + + PseudoVMSLTU_VV_M2 = 8555 + + PseudoVMSLTU_VV_M2_MASK = 8556 + + PseudoVMSLTU_VV_M4 = 8557 + + PseudoVMSLTU_VV_M4_MASK = 8558 + + PseudoVMSLTU_VV_M8 = 8559 + + PseudoVMSLTU_VV_M8_MASK = 8560 + + PseudoVMSLTU_VV_MF2 = 8561 + + PseudoVMSLTU_VV_MF2_MASK = 8562 + + PseudoVMSLTU_VV_MF4 = 8563 + + PseudoVMSLTU_VV_MF4_MASK = 8564 + + PseudoVMSLTU_VV_MF8 = 8565 + + PseudoVMSLTU_VV_MF8_MASK = 8566 + + PseudoVMSLTU_VX_M1 = 8567 + + PseudoVMSLTU_VX_M1_MASK = 8568 + + PseudoVMSLTU_VX_M2 = 8569 + + PseudoVMSLTU_VX_M2_MASK = 8570 + + PseudoVMSLTU_VX_M4 = 8571 + + PseudoVMSLTU_VX_M4_MASK = 8572 + + PseudoVMSLTU_VX_M8 = 8573 + + PseudoVMSLTU_VX_M8_MASK = 8574 + + PseudoVMSLTU_VX_MF2 = 8575 + + PseudoVMSLTU_VX_MF2_MASK = 8576 + + PseudoVMSLTU_VX_MF4 = 8577 + + PseudoVMSLTU_VX_MF4_MASK = 8578 + + PseudoVMSLTU_VX_MF8 = 8579 + + PseudoVMSLTU_VX_MF8_MASK = 8580 + + PseudoVMSLT_VI = 8581 + + PseudoVMSLT_VV_M1 = 8582 + + PseudoVMSLT_VV_M1_MASK = 8583 + + PseudoVMSLT_VV_M2 = 8584 + + PseudoVMSLT_VV_M2_MASK = 8585 + + PseudoVMSLT_VV_M4 = 8586 + + PseudoVMSLT_VV_M4_MASK = 8587 + + PseudoVMSLT_VV_M8 = 8588 + + PseudoVMSLT_VV_M8_MASK = 8589 + + PseudoVMSLT_VV_MF2 = 8590 + + PseudoVMSLT_VV_MF2_MASK = 8591 + + PseudoVMSLT_VV_MF4 = 8592 + + PseudoVMSLT_VV_MF4_MASK = 8593 + + PseudoVMSLT_VV_MF8 = 8594 + + PseudoVMSLT_VV_MF8_MASK = 8595 + + PseudoVMSLT_VX_M1 = 8596 + + PseudoVMSLT_VX_M1_MASK = 8597 + + PseudoVMSLT_VX_M2 = 8598 + + PseudoVMSLT_VX_M2_MASK = 8599 + + PseudoVMSLT_VX_M4 = 8600 + + PseudoVMSLT_VX_M4_MASK = 8601 + + PseudoVMSLT_VX_M8 = 8602 + + PseudoVMSLT_VX_M8_MASK = 8603 + + PseudoVMSLT_VX_MF2 = 8604 + + PseudoVMSLT_VX_MF2_MASK = 8605 + + PseudoVMSLT_VX_MF4 = 8606 + + PseudoVMSLT_VX_MF4_MASK = 8607 + + PseudoVMSLT_VX_MF8 = 8608 + + PseudoVMSLT_VX_MF8_MASK = 8609 + + PseudoVMSNE_VI_M1 = 8610 + + PseudoVMSNE_VI_M1_MASK = 8611 + + PseudoVMSNE_VI_M2 = 8612 + + PseudoVMSNE_VI_M2_MASK = 8613 + + PseudoVMSNE_VI_M4 = 8614 + + PseudoVMSNE_VI_M4_MASK = 8615 + + PseudoVMSNE_VI_M8 = 8616 + + PseudoVMSNE_VI_M8_MASK = 8617 + + PseudoVMSNE_VI_MF2 = 8618 + + PseudoVMSNE_VI_MF2_MASK = 8619 + + PseudoVMSNE_VI_MF4 = 8620 + + PseudoVMSNE_VI_MF4_MASK = 8621 + + PseudoVMSNE_VI_MF8 = 8622 + + PseudoVMSNE_VI_MF8_MASK = 8623 + + PseudoVMSNE_VV_M1 = 8624 + + PseudoVMSNE_VV_M1_MASK = 8625 + + PseudoVMSNE_VV_M2 = 8626 + + PseudoVMSNE_VV_M2_MASK = 8627 + + PseudoVMSNE_VV_M4 = 8628 + + PseudoVMSNE_VV_M4_MASK = 8629 + + PseudoVMSNE_VV_M8 = 8630 + + PseudoVMSNE_VV_M8_MASK = 8631 + + PseudoVMSNE_VV_MF2 = 8632 + + PseudoVMSNE_VV_MF2_MASK = 8633 + + PseudoVMSNE_VV_MF4 = 8634 + + PseudoVMSNE_VV_MF4_MASK = 8635 + + PseudoVMSNE_VV_MF8 = 8636 + + PseudoVMSNE_VV_MF8_MASK = 8637 + + PseudoVMSNE_VX_M1 = 8638 + + PseudoVMSNE_VX_M1_MASK = 8639 + + PseudoVMSNE_VX_M2 = 8640 + + PseudoVMSNE_VX_M2_MASK = 8641 + + PseudoVMSNE_VX_M4 = 8642 + + PseudoVMSNE_VX_M4_MASK = 8643 + + PseudoVMSNE_VX_M8 = 8644 + + PseudoVMSNE_VX_M8_MASK = 8645 + + PseudoVMSNE_VX_MF2 = 8646 + + PseudoVMSNE_VX_MF2_MASK = 8647 + + PseudoVMSNE_VX_MF4 = 8648 + + PseudoVMSNE_VX_MF4_MASK = 8649 + + PseudoVMSNE_VX_MF8 = 8650 + + PseudoVMSNE_VX_MF8_MASK = 8651 + + PseudoVMSOF_M_B1 = 8652 + + PseudoVMSOF_M_B16 = 8653 + + PseudoVMSOF_M_B16_MASK = 8654 + + PseudoVMSOF_M_B1_MASK = 8655 + + PseudoVMSOF_M_B2 = 8656 + + PseudoVMSOF_M_B2_MASK = 8657 + + PseudoVMSOF_M_B32 = 8658 + + PseudoVMSOF_M_B32_MASK = 8659 + + PseudoVMSOF_M_B4 = 8660 + + PseudoVMSOF_M_B4_MASK = 8661 + + PseudoVMSOF_M_B64 = 8662 + + PseudoVMSOF_M_B64_MASK = 8663 + + PseudoVMSOF_M_B8 = 8664 + + PseudoVMSOF_M_B8_MASK = 8665 + + PseudoVMULHSU_VV_M1 = 8666 + + PseudoVMULHSU_VV_M1_MASK = 8667 + + PseudoVMULHSU_VV_M2 = 8668 + + PseudoVMULHSU_VV_M2_MASK = 8669 + + PseudoVMULHSU_VV_M4 = 8670 + + PseudoVMULHSU_VV_M4_MASK = 8671 + + PseudoVMULHSU_VV_M8 = 8672 + + PseudoVMULHSU_VV_M8_MASK = 8673 + + PseudoVMULHSU_VV_MF2 = 8674 + + PseudoVMULHSU_VV_MF2_MASK = 8675 + + PseudoVMULHSU_VV_MF4 = 8676 + + PseudoVMULHSU_VV_MF4_MASK = 8677 + + PseudoVMULHSU_VV_MF8 = 8678 + + PseudoVMULHSU_VV_MF8_MASK = 8679 + + PseudoVMULHSU_VX_M1 = 8680 + + PseudoVMULHSU_VX_M1_MASK = 8681 + + PseudoVMULHSU_VX_M2 = 8682 + + PseudoVMULHSU_VX_M2_MASK = 8683 + + PseudoVMULHSU_VX_M4 = 8684 + + PseudoVMULHSU_VX_M4_MASK = 8685 + + PseudoVMULHSU_VX_M8 = 8686 + + PseudoVMULHSU_VX_M8_MASK = 8687 + + PseudoVMULHSU_VX_MF2 = 8688 + + PseudoVMULHSU_VX_MF2_MASK = 8689 + + PseudoVMULHSU_VX_MF4 = 8690 + + PseudoVMULHSU_VX_MF4_MASK = 8691 + + PseudoVMULHSU_VX_MF8 = 8692 + + PseudoVMULHSU_VX_MF8_MASK = 8693 + + PseudoVMULHU_VV_M1 = 8694 + + PseudoVMULHU_VV_M1_MASK = 8695 + + PseudoVMULHU_VV_M2 = 8696 + + PseudoVMULHU_VV_M2_MASK = 8697 + + PseudoVMULHU_VV_M4 = 8698 + + PseudoVMULHU_VV_M4_MASK = 8699 + + PseudoVMULHU_VV_M8 = 8700 + + PseudoVMULHU_VV_M8_MASK = 8701 + + PseudoVMULHU_VV_MF2 = 8702 + + PseudoVMULHU_VV_MF2_MASK = 8703 + + PseudoVMULHU_VV_MF4 = 8704 + + PseudoVMULHU_VV_MF4_MASK = 8705 + + PseudoVMULHU_VV_MF8 = 8706 + + PseudoVMULHU_VV_MF8_MASK = 8707 + + PseudoVMULHU_VX_M1 = 8708 + + PseudoVMULHU_VX_M1_MASK = 8709 + + PseudoVMULHU_VX_M2 = 8710 + + PseudoVMULHU_VX_M2_MASK = 8711 + + PseudoVMULHU_VX_M4 = 8712 + + PseudoVMULHU_VX_M4_MASK = 8713 + + PseudoVMULHU_VX_M8 = 8714 + + PseudoVMULHU_VX_M8_MASK = 8715 + + PseudoVMULHU_VX_MF2 = 8716 + + PseudoVMULHU_VX_MF2_MASK = 8717 + + PseudoVMULHU_VX_MF4 = 8718 + + PseudoVMULHU_VX_MF4_MASK = 8719 + + PseudoVMULHU_VX_MF8 = 8720 + + PseudoVMULHU_VX_MF8_MASK = 8721 + + PseudoVMULH_VV_M1 = 8722 + + PseudoVMULH_VV_M1_MASK = 8723 + + PseudoVMULH_VV_M2 = 8724 + + PseudoVMULH_VV_M2_MASK = 8725 + + PseudoVMULH_VV_M4 = 8726 + + PseudoVMULH_VV_M4_MASK = 8727 + + PseudoVMULH_VV_M8 = 8728 + + PseudoVMULH_VV_M8_MASK = 8729 + + PseudoVMULH_VV_MF2 = 8730 + + PseudoVMULH_VV_MF2_MASK = 8731 + + PseudoVMULH_VV_MF4 = 8732 + + PseudoVMULH_VV_MF4_MASK = 8733 + + PseudoVMULH_VV_MF8 = 8734 + + PseudoVMULH_VV_MF8_MASK = 8735 + + PseudoVMULH_VX_M1 = 8736 + + PseudoVMULH_VX_M1_MASK = 8737 + + PseudoVMULH_VX_M2 = 8738 + + PseudoVMULH_VX_M2_MASK = 8739 + + PseudoVMULH_VX_M4 = 8740 + + PseudoVMULH_VX_M4_MASK = 8741 + + PseudoVMULH_VX_M8 = 8742 + + PseudoVMULH_VX_M8_MASK = 8743 + + PseudoVMULH_VX_MF2 = 8744 + + PseudoVMULH_VX_MF2_MASK = 8745 + + PseudoVMULH_VX_MF4 = 8746 + + PseudoVMULH_VX_MF4_MASK = 8747 + + PseudoVMULH_VX_MF8 = 8748 + + PseudoVMULH_VX_MF8_MASK = 8749 + + PseudoVMUL_VV_M1 = 8750 + + PseudoVMUL_VV_M1_MASK = 8751 + + PseudoVMUL_VV_M2 = 8752 + + PseudoVMUL_VV_M2_MASK = 8753 + + PseudoVMUL_VV_M4 = 8754 + + PseudoVMUL_VV_M4_MASK = 8755 + + PseudoVMUL_VV_M8 = 8756 + + PseudoVMUL_VV_M8_MASK = 8757 + + PseudoVMUL_VV_MF2 = 8758 + + PseudoVMUL_VV_MF2_MASK = 8759 + + PseudoVMUL_VV_MF4 = 8760 + + PseudoVMUL_VV_MF4_MASK = 8761 + + PseudoVMUL_VV_MF8 = 8762 + + PseudoVMUL_VV_MF8_MASK = 8763 + + PseudoVMUL_VX_M1 = 8764 + + PseudoVMUL_VX_M1_MASK = 8765 + + PseudoVMUL_VX_M2 = 8766 + + PseudoVMUL_VX_M2_MASK = 8767 + + PseudoVMUL_VX_M4 = 8768 + + PseudoVMUL_VX_M4_MASK = 8769 + + PseudoVMUL_VX_M8 = 8770 + + PseudoVMUL_VX_M8_MASK = 8771 + + PseudoVMUL_VX_MF2 = 8772 + + PseudoVMUL_VX_MF2_MASK = 8773 + + PseudoVMUL_VX_MF4 = 8774 + + PseudoVMUL_VX_MF4_MASK = 8775 + + PseudoVMUL_VX_MF8 = 8776 + + PseudoVMUL_VX_MF8_MASK = 8777 + + PseudoVMV_S_X = 8778 + + PseudoVMV_V_I_M1 = 8779 + + PseudoVMV_V_I_M2 = 8780 + + PseudoVMV_V_I_M4 = 8781 + + PseudoVMV_V_I_M8 = 8782 + + PseudoVMV_V_I_MF2 = 8783 + + PseudoVMV_V_I_MF4 = 8784 + + PseudoVMV_V_I_MF8 = 8785 + + PseudoVMV_V_V_M1 = 8786 + + PseudoVMV_V_V_M2 = 8787 + + PseudoVMV_V_V_M4 = 8788 + + PseudoVMV_V_V_M8 = 8789 + + PseudoVMV_V_V_MF2 = 8790 + + PseudoVMV_V_V_MF4 = 8791 + + PseudoVMV_V_V_MF8 = 8792 + + PseudoVMV_V_X_M1 = 8793 + + PseudoVMV_V_X_M2 = 8794 + + PseudoVMV_V_X_M4 = 8795 + + PseudoVMV_V_X_M8 = 8796 + + PseudoVMV_V_X_MF2 = 8797 + + PseudoVMV_V_X_MF4 = 8798 + + PseudoVMV_V_X_MF8 = 8799 + + PseudoVMV_X_S = 8800 + + PseudoVMXNOR_MM_B1 = 8801 + + PseudoVMXNOR_MM_B16 = 8802 + + PseudoVMXNOR_MM_B2 = 8803 + + PseudoVMXNOR_MM_B32 = 8804 + + PseudoVMXNOR_MM_B4 = 8805 + + PseudoVMXNOR_MM_B64 = 8806 + + PseudoVMXNOR_MM_B8 = 8807 + + PseudoVMXOR_MM_B1 = 8808 + + PseudoVMXOR_MM_B16 = 8809 + + PseudoVMXOR_MM_B2 = 8810 + + PseudoVMXOR_MM_B32 = 8811 + + PseudoVMXOR_MM_B4 = 8812 + + PseudoVMXOR_MM_B64 = 8813 + + PseudoVMXOR_MM_B8 = 8814 + + PseudoVNCLIPU_WI_M1 = 8815 + + PseudoVNCLIPU_WI_M1_MASK = 8816 + + PseudoVNCLIPU_WI_M2 = 8817 + + PseudoVNCLIPU_WI_M2_MASK = 8818 + + PseudoVNCLIPU_WI_M4 = 8819 + + PseudoVNCLIPU_WI_M4_MASK = 8820 + + PseudoVNCLIPU_WI_MF2 = 8821 + + PseudoVNCLIPU_WI_MF2_MASK = 8822 + + PseudoVNCLIPU_WI_MF4 = 8823 + + PseudoVNCLIPU_WI_MF4_MASK = 8824 + + PseudoVNCLIPU_WI_MF8 = 8825 + + PseudoVNCLIPU_WI_MF8_MASK = 8826 + + PseudoVNCLIPU_WV_M1 = 8827 + + PseudoVNCLIPU_WV_M1_MASK = 8828 + + PseudoVNCLIPU_WV_M2 = 8829 + + PseudoVNCLIPU_WV_M2_MASK = 8830 + + PseudoVNCLIPU_WV_M4 = 8831 + + PseudoVNCLIPU_WV_M4_MASK = 8832 + + PseudoVNCLIPU_WV_MF2 = 8833 + + PseudoVNCLIPU_WV_MF2_MASK = 8834 + + PseudoVNCLIPU_WV_MF4 = 8835 + + PseudoVNCLIPU_WV_MF4_MASK = 8836 + + PseudoVNCLIPU_WV_MF8 = 8837 + + PseudoVNCLIPU_WV_MF8_MASK = 8838 + + PseudoVNCLIPU_WX_M1 = 8839 + + PseudoVNCLIPU_WX_M1_MASK = 8840 + + PseudoVNCLIPU_WX_M2 = 8841 + + PseudoVNCLIPU_WX_M2_MASK = 8842 + + PseudoVNCLIPU_WX_M4 = 8843 + + PseudoVNCLIPU_WX_M4_MASK = 8844 + + PseudoVNCLIPU_WX_MF2 = 8845 + + PseudoVNCLIPU_WX_MF2_MASK = 8846 + + PseudoVNCLIPU_WX_MF4 = 8847 + + PseudoVNCLIPU_WX_MF4_MASK = 8848 + + PseudoVNCLIPU_WX_MF8 = 8849 + + PseudoVNCLIPU_WX_MF8_MASK = 8850 + + PseudoVNCLIP_WI_M1 = 8851 + + PseudoVNCLIP_WI_M1_MASK = 8852 + + PseudoVNCLIP_WI_M2 = 8853 + + PseudoVNCLIP_WI_M2_MASK = 8854 + + PseudoVNCLIP_WI_M4 = 8855 + + PseudoVNCLIP_WI_M4_MASK = 8856 + + PseudoVNCLIP_WI_MF2 = 8857 + + PseudoVNCLIP_WI_MF2_MASK = 8858 + + PseudoVNCLIP_WI_MF4 = 8859 + + PseudoVNCLIP_WI_MF4_MASK = 8860 + + PseudoVNCLIP_WI_MF8 = 8861 + + PseudoVNCLIP_WI_MF8_MASK = 8862 + + PseudoVNCLIP_WV_M1 = 8863 + + PseudoVNCLIP_WV_M1_MASK = 8864 + + PseudoVNCLIP_WV_M2 = 8865 + + PseudoVNCLIP_WV_M2_MASK = 8866 + + PseudoVNCLIP_WV_M4 = 8867 + + PseudoVNCLIP_WV_M4_MASK = 8868 + + PseudoVNCLIP_WV_MF2 = 8869 + + PseudoVNCLIP_WV_MF2_MASK = 8870 + + PseudoVNCLIP_WV_MF4 = 8871 + + PseudoVNCLIP_WV_MF4_MASK = 8872 + + PseudoVNCLIP_WV_MF8 = 8873 + + PseudoVNCLIP_WV_MF8_MASK = 8874 + + PseudoVNCLIP_WX_M1 = 8875 + + PseudoVNCLIP_WX_M1_MASK = 8876 + + PseudoVNCLIP_WX_M2 = 8877 + + PseudoVNCLIP_WX_M2_MASK = 8878 + + PseudoVNCLIP_WX_M4 = 8879 + + PseudoVNCLIP_WX_M4_MASK = 8880 + + PseudoVNCLIP_WX_MF2 = 8881 + + PseudoVNCLIP_WX_MF2_MASK = 8882 + + PseudoVNCLIP_WX_MF4 = 8883 + + PseudoVNCLIP_WX_MF4_MASK = 8884 + + PseudoVNCLIP_WX_MF8 = 8885 + + PseudoVNCLIP_WX_MF8_MASK = 8886 + + PseudoVNMSAC_VV_M1 = 8887 + + PseudoVNMSAC_VV_M1_MASK = 8888 + + PseudoVNMSAC_VV_M2 = 8889 + + PseudoVNMSAC_VV_M2_MASK = 8890 + + PseudoVNMSAC_VV_M4 = 8891 + + PseudoVNMSAC_VV_M4_MASK = 8892 + + PseudoVNMSAC_VV_M8 = 8893 + + PseudoVNMSAC_VV_M8_MASK = 8894 + + PseudoVNMSAC_VV_MF2 = 8895 + + PseudoVNMSAC_VV_MF2_MASK = 8896 + + PseudoVNMSAC_VV_MF4 = 8897 + + PseudoVNMSAC_VV_MF4_MASK = 8898 + + PseudoVNMSAC_VV_MF8 = 8899 + + PseudoVNMSAC_VV_MF8_MASK = 8900 + + PseudoVNMSAC_VX_M1 = 8901 + + PseudoVNMSAC_VX_M1_MASK = 8902 + + PseudoVNMSAC_VX_M2 = 8903 + + PseudoVNMSAC_VX_M2_MASK = 8904 + + PseudoVNMSAC_VX_M4 = 8905 + + PseudoVNMSAC_VX_M4_MASK = 8906 + + PseudoVNMSAC_VX_M8 = 8907 + + PseudoVNMSAC_VX_M8_MASK = 8908 + + PseudoVNMSAC_VX_MF2 = 8909 + + PseudoVNMSAC_VX_MF2_MASK = 8910 + + PseudoVNMSAC_VX_MF4 = 8911 + + PseudoVNMSAC_VX_MF4_MASK = 8912 + + PseudoVNMSAC_VX_MF8 = 8913 + + PseudoVNMSAC_VX_MF8_MASK = 8914 + + PseudoVNMSUB_VV_M1 = 8915 + + PseudoVNMSUB_VV_M1_MASK = 8916 + + PseudoVNMSUB_VV_M2 = 8917 + + PseudoVNMSUB_VV_M2_MASK = 8918 + + PseudoVNMSUB_VV_M4 = 8919 + + PseudoVNMSUB_VV_M4_MASK = 8920 + + PseudoVNMSUB_VV_M8 = 8921 + + PseudoVNMSUB_VV_M8_MASK = 8922 + + PseudoVNMSUB_VV_MF2 = 8923 + + PseudoVNMSUB_VV_MF2_MASK = 8924 + + PseudoVNMSUB_VV_MF4 = 8925 + + PseudoVNMSUB_VV_MF4_MASK = 8926 + + PseudoVNMSUB_VV_MF8 = 8927 + + PseudoVNMSUB_VV_MF8_MASK = 8928 + + PseudoVNMSUB_VX_M1 = 8929 + + PseudoVNMSUB_VX_M1_MASK = 8930 + + PseudoVNMSUB_VX_M2 = 8931 + + PseudoVNMSUB_VX_M2_MASK = 8932 + + PseudoVNMSUB_VX_M4 = 8933 + + PseudoVNMSUB_VX_M4_MASK = 8934 + + PseudoVNMSUB_VX_M8 = 8935 + + PseudoVNMSUB_VX_M8_MASK = 8936 + + PseudoVNMSUB_VX_MF2 = 8937 + + PseudoVNMSUB_VX_MF2_MASK = 8938 + + PseudoVNMSUB_VX_MF4 = 8939 + + PseudoVNMSUB_VX_MF4_MASK = 8940 + + PseudoVNMSUB_VX_MF8 = 8941 + + PseudoVNMSUB_VX_MF8_MASK = 8942 + + PseudoVNSRA_WI_M1 = 8943 + + PseudoVNSRA_WI_M1_MASK = 8944 + + PseudoVNSRA_WI_M2 = 8945 + + PseudoVNSRA_WI_M2_MASK = 8946 + + PseudoVNSRA_WI_M4 = 8947 + + PseudoVNSRA_WI_M4_MASK = 8948 + + PseudoVNSRA_WI_MF2 = 8949 + + PseudoVNSRA_WI_MF2_MASK = 8950 + + PseudoVNSRA_WI_MF4 = 8951 + + PseudoVNSRA_WI_MF4_MASK = 8952 + + PseudoVNSRA_WI_MF8 = 8953 + + PseudoVNSRA_WI_MF8_MASK = 8954 + + PseudoVNSRA_WV_M1 = 8955 + + PseudoVNSRA_WV_M1_MASK = 8956 + + PseudoVNSRA_WV_M2 = 8957 + + PseudoVNSRA_WV_M2_MASK = 8958 + + PseudoVNSRA_WV_M4 = 8959 + + PseudoVNSRA_WV_M4_MASK = 8960 + + PseudoVNSRA_WV_MF2 = 8961 + + PseudoVNSRA_WV_MF2_MASK = 8962 + + PseudoVNSRA_WV_MF4 = 8963 + + PseudoVNSRA_WV_MF4_MASK = 8964 + + PseudoVNSRA_WV_MF8 = 8965 + + PseudoVNSRA_WV_MF8_MASK = 8966 + + PseudoVNSRA_WX_M1 = 8967 + + PseudoVNSRA_WX_M1_MASK = 8968 + + PseudoVNSRA_WX_M2 = 8969 + + PseudoVNSRA_WX_M2_MASK = 8970 + + PseudoVNSRA_WX_M4 = 8971 + + PseudoVNSRA_WX_M4_MASK = 8972 + + PseudoVNSRA_WX_MF2 = 8973 + + PseudoVNSRA_WX_MF2_MASK = 8974 + + PseudoVNSRA_WX_MF4 = 8975 + + PseudoVNSRA_WX_MF4_MASK = 8976 + + PseudoVNSRA_WX_MF8 = 8977 + + PseudoVNSRA_WX_MF8_MASK = 8978 + + PseudoVNSRL_WI_M1 = 8979 + + PseudoVNSRL_WI_M1_MASK = 8980 + + PseudoVNSRL_WI_M2 = 8981 + + PseudoVNSRL_WI_M2_MASK = 8982 + + PseudoVNSRL_WI_M4 = 8983 + + PseudoVNSRL_WI_M4_MASK = 8984 + + PseudoVNSRL_WI_MF2 = 8985 + + PseudoVNSRL_WI_MF2_MASK = 8986 + + PseudoVNSRL_WI_MF4 = 8987 + + PseudoVNSRL_WI_MF4_MASK = 8988 + + PseudoVNSRL_WI_MF8 = 8989 + + PseudoVNSRL_WI_MF8_MASK = 8990 + + PseudoVNSRL_WV_M1 = 8991 + + PseudoVNSRL_WV_M1_MASK = 8992 + + PseudoVNSRL_WV_M2 = 8993 + + PseudoVNSRL_WV_M2_MASK = 8994 + + PseudoVNSRL_WV_M4 = 8995 + + PseudoVNSRL_WV_M4_MASK = 8996 + + PseudoVNSRL_WV_MF2 = 8997 + + PseudoVNSRL_WV_MF2_MASK = 8998 + + PseudoVNSRL_WV_MF4 = 8999 + + PseudoVNSRL_WV_MF4_MASK = 9000 + + PseudoVNSRL_WV_MF8 = 9001 + + PseudoVNSRL_WV_MF8_MASK = 9002 + + PseudoVNSRL_WX_M1 = 9003 + + PseudoVNSRL_WX_M1_MASK = 9004 + + PseudoVNSRL_WX_M2 = 9005 + + PseudoVNSRL_WX_M2_MASK = 9006 + + PseudoVNSRL_WX_M4 = 9007 + + PseudoVNSRL_WX_M4_MASK = 9008 + + PseudoVNSRL_WX_MF2 = 9009 + + PseudoVNSRL_WX_MF2_MASK = 9010 + + PseudoVNSRL_WX_MF4 = 9011 + + PseudoVNSRL_WX_MF4_MASK = 9012 + + PseudoVNSRL_WX_MF8 = 9013 + + PseudoVNSRL_WX_MF8_MASK = 9014 + + PseudoVOR_VI_M1 = 9015 + + PseudoVOR_VI_M1_MASK = 9016 + + PseudoVOR_VI_M2 = 9017 + + PseudoVOR_VI_M2_MASK = 9018 + + PseudoVOR_VI_M4 = 9019 + + PseudoVOR_VI_M4_MASK = 9020 + + PseudoVOR_VI_M8 = 9021 + + PseudoVOR_VI_M8_MASK = 9022 + + PseudoVOR_VI_MF2 = 9023 + + PseudoVOR_VI_MF2_MASK = 9024 + + PseudoVOR_VI_MF4 = 9025 + + PseudoVOR_VI_MF4_MASK = 9026 + + PseudoVOR_VI_MF8 = 9027 + + PseudoVOR_VI_MF8_MASK = 9028 + + PseudoVOR_VV_M1 = 9029 + + PseudoVOR_VV_M1_MASK = 9030 + + PseudoVOR_VV_M2 = 9031 + + PseudoVOR_VV_M2_MASK = 9032 + + PseudoVOR_VV_M4 = 9033 + + PseudoVOR_VV_M4_MASK = 9034 + + PseudoVOR_VV_M8 = 9035 + + PseudoVOR_VV_M8_MASK = 9036 + + PseudoVOR_VV_MF2 = 9037 + + PseudoVOR_VV_MF2_MASK = 9038 + + PseudoVOR_VV_MF4 = 9039 + + PseudoVOR_VV_MF4_MASK = 9040 + + PseudoVOR_VV_MF8 = 9041 + + PseudoVOR_VV_MF8_MASK = 9042 + + PseudoVOR_VX_M1 = 9043 + + PseudoVOR_VX_M1_MASK = 9044 + + PseudoVOR_VX_M2 = 9045 + + PseudoVOR_VX_M2_MASK = 9046 + + PseudoVOR_VX_M4 = 9047 + + PseudoVOR_VX_M4_MASK = 9048 + + PseudoVOR_VX_M8 = 9049 + + PseudoVOR_VX_M8_MASK = 9050 + + PseudoVOR_VX_MF2 = 9051 + + PseudoVOR_VX_MF2_MASK = 9052 + + PseudoVOR_VX_MF4 = 9053 + + PseudoVOR_VX_MF4_MASK = 9054 + + PseudoVOR_VX_MF8 = 9055 + + PseudoVOR_VX_MF8_MASK = 9056 + + PseudoVQDOTSU_VV_M1 = 9057 + + PseudoVQDOTSU_VV_M1_MASK = 9058 + + PseudoVQDOTSU_VV_M2 = 9059 + + PseudoVQDOTSU_VV_M2_MASK = 9060 + + PseudoVQDOTSU_VV_M4 = 9061 + + PseudoVQDOTSU_VV_M4_MASK = 9062 + + PseudoVQDOTSU_VV_M8 = 9063 + + PseudoVQDOTSU_VV_M8_MASK = 9064 + + PseudoVQDOTSU_VV_MF2 = 9065 + + PseudoVQDOTSU_VV_MF2_MASK = 9066 + + PseudoVQDOTSU_VX_M1 = 9067 + + PseudoVQDOTSU_VX_M1_MASK = 9068 + + PseudoVQDOTSU_VX_M2 = 9069 + + PseudoVQDOTSU_VX_M2_MASK = 9070 + + PseudoVQDOTSU_VX_M4 = 9071 + + PseudoVQDOTSU_VX_M4_MASK = 9072 + + PseudoVQDOTSU_VX_M8 = 9073 + + PseudoVQDOTSU_VX_M8_MASK = 9074 + + PseudoVQDOTSU_VX_MF2 = 9075 + + PseudoVQDOTSU_VX_MF2_MASK = 9076 + + PseudoVQDOTUS_VX_M1 = 9077 + + PseudoVQDOTUS_VX_M1_MASK = 9078 + + PseudoVQDOTUS_VX_M2 = 9079 + + PseudoVQDOTUS_VX_M2_MASK = 9080 + + PseudoVQDOTUS_VX_M4 = 9081 + + PseudoVQDOTUS_VX_M4_MASK = 9082 + + PseudoVQDOTUS_VX_M8 = 9083 + + PseudoVQDOTUS_VX_M8_MASK = 9084 + + PseudoVQDOTUS_VX_MF2 = 9085 + + PseudoVQDOTUS_VX_MF2_MASK = 9086 + + PseudoVQDOTU_VV_M1 = 9087 + + PseudoVQDOTU_VV_M1_MASK = 9088 + + PseudoVQDOTU_VV_M2 = 9089 + + PseudoVQDOTU_VV_M2_MASK = 9090 + + PseudoVQDOTU_VV_M4 = 9091 + + PseudoVQDOTU_VV_M4_MASK = 9092 + + PseudoVQDOTU_VV_M8 = 9093 + + PseudoVQDOTU_VV_M8_MASK = 9094 + + PseudoVQDOTU_VV_MF2 = 9095 + + PseudoVQDOTU_VV_MF2_MASK = 9096 + + PseudoVQDOTU_VX_M1 = 9097 + + PseudoVQDOTU_VX_M1_MASK = 9098 + + PseudoVQDOTU_VX_M2 = 9099 + + PseudoVQDOTU_VX_M2_MASK = 9100 + + PseudoVQDOTU_VX_M4 = 9101 + + PseudoVQDOTU_VX_M4_MASK = 9102 + + PseudoVQDOTU_VX_M8 = 9103 + + PseudoVQDOTU_VX_M8_MASK = 9104 + + PseudoVQDOTU_VX_MF2 = 9105 + + PseudoVQDOTU_VX_MF2_MASK = 9106 + + PseudoVQDOT_VV_M1 = 9107 + + PseudoVQDOT_VV_M1_MASK = 9108 + + PseudoVQDOT_VV_M2 = 9109 + + PseudoVQDOT_VV_M2_MASK = 9110 + + PseudoVQDOT_VV_M4 = 9111 + + PseudoVQDOT_VV_M4_MASK = 9112 + + PseudoVQDOT_VV_M8 = 9113 + + PseudoVQDOT_VV_M8_MASK = 9114 + + PseudoVQDOT_VV_MF2 = 9115 + + PseudoVQDOT_VV_MF2_MASK = 9116 + + PseudoVQDOT_VX_M1 = 9117 + + PseudoVQDOT_VX_M1_MASK = 9118 + + PseudoVQDOT_VX_M2 = 9119 + + PseudoVQDOT_VX_M2_MASK = 9120 + + PseudoVQDOT_VX_M4 = 9121 + + PseudoVQDOT_VX_M4_MASK = 9122 + + PseudoVQDOT_VX_M8 = 9123 + + PseudoVQDOT_VX_M8_MASK = 9124 + + PseudoVQDOT_VX_MF2 = 9125 + + PseudoVQDOT_VX_MF2_MASK = 9126 + + PseudoVREDAND_VS_M1_E16 = 9127 + + PseudoVREDAND_VS_M1_E16_MASK = 9128 + + PseudoVREDAND_VS_M1_E32 = 9129 + + PseudoVREDAND_VS_M1_E32_MASK = 9130 + + PseudoVREDAND_VS_M1_E64 = 9131 + + PseudoVREDAND_VS_M1_E64_MASK = 9132 + + PseudoVREDAND_VS_M1_E8 = 9133 + + PseudoVREDAND_VS_M1_E8_MASK = 9134 + + PseudoVREDAND_VS_M2_E16 = 9135 + + PseudoVREDAND_VS_M2_E16_MASK = 9136 + + PseudoVREDAND_VS_M2_E32 = 9137 + + PseudoVREDAND_VS_M2_E32_MASK = 9138 + + PseudoVREDAND_VS_M2_E64 = 9139 + + PseudoVREDAND_VS_M2_E64_MASK = 9140 + + PseudoVREDAND_VS_M2_E8 = 9141 + + PseudoVREDAND_VS_M2_E8_MASK = 9142 + + PseudoVREDAND_VS_M4_E16 = 9143 + + PseudoVREDAND_VS_M4_E16_MASK = 9144 + + PseudoVREDAND_VS_M4_E32 = 9145 + + PseudoVREDAND_VS_M4_E32_MASK = 9146 + + PseudoVREDAND_VS_M4_E64 = 9147 + + PseudoVREDAND_VS_M4_E64_MASK = 9148 + + PseudoVREDAND_VS_M4_E8 = 9149 + + PseudoVREDAND_VS_M4_E8_MASK = 9150 + + PseudoVREDAND_VS_M8_E16 = 9151 + + PseudoVREDAND_VS_M8_E16_MASK = 9152 + + PseudoVREDAND_VS_M8_E32 = 9153 + + PseudoVREDAND_VS_M8_E32_MASK = 9154 + + PseudoVREDAND_VS_M8_E64 = 9155 + + PseudoVREDAND_VS_M8_E64_MASK = 9156 + + PseudoVREDAND_VS_M8_E8 = 9157 + + PseudoVREDAND_VS_M8_E8_MASK = 9158 + + PseudoVREDAND_VS_MF2_E16 = 9159 + + PseudoVREDAND_VS_MF2_E16_MASK = 9160 + + PseudoVREDAND_VS_MF2_E32 = 9161 + + PseudoVREDAND_VS_MF2_E32_MASK = 9162 + + PseudoVREDAND_VS_MF2_E8 = 9163 + + PseudoVREDAND_VS_MF2_E8_MASK = 9164 + + PseudoVREDAND_VS_MF4_E16 = 9165 + + PseudoVREDAND_VS_MF4_E16_MASK = 9166 + + PseudoVREDAND_VS_MF4_E8 = 9167 + + PseudoVREDAND_VS_MF4_E8_MASK = 9168 + + PseudoVREDAND_VS_MF8_E8 = 9169 + + PseudoVREDAND_VS_MF8_E8_MASK = 9170 + + PseudoVREDMAXU_VS_M1_E16 = 9171 + + PseudoVREDMAXU_VS_M1_E16_MASK = 9172 + + PseudoVREDMAXU_VS_M1_E32 = 9173 + + PseudoVREDMAXU_VS_M1_E32_MASK = 9174 + + PseudoVREDMAXU_VS_M1_E64 = 9175 + + PseudoVREDMAXU_VS_M1_E64_MASK = 9176 + + PseudoVREDMAXU_VS_M1_E8 = 9177 + + PseudoVREDMAXU_VS_M1_E8_MASK = 9178 + + PseudoVREDMAXU_VS_M2_E16 = 9179 + + PseudoVREDMAXU_VS_M2_E16_MASK = 9180 + + PseudoVREDMAXU_VS_M2_E32 = 9181 + + PseudoVREDMAXU_VS_M2_E32_MASK = 9182 + + PseudoVREDMAXU_VS_M2_E64 = 9183 + + PseudoVREDMAXU_VS_M2_E64_MASK = 9184 + + PseudoVREDMAXU_VS_M2_E8 = 9185 + + PseudoVREDMAXU_VS_M2_E8_MASK = 9186 + + PseudoVREDMAXU_VS_M4_E16 = 9187 + + PseudoVREDMAXU_VS_M4_E16_MASK = 9188 + + PseudoVREDMAXU_VS_M4_E32 = 9189 + + PseudoVREDMAXU_VS_M4_E32_MASK = 9190 + + PseudoVREDMAXU_VS_M4_E64 = 9191 + + PseudoVREDMAXU_VS_M4_E64_MASK = 9192 + + PseudoVREDMAXU_VS_M4_E8 = 9193 + + PseudoVREDMAXU_VS_M4_E8_MASK = 9194 + + PseudoVREDMAXU_VS_M8_E16 = 9195 + + PseudoVREDMAXU_VS_M8_E16_MASK = 9196 + + PseudoVREDMAXU_VS_M8_E32 = 9197 + + PseudoVREDMAXU_VS_M8_E32_MASK = 9198 + + PseudoVREDMAXU_VS_M8_E64 = 9199 + + PseudoVREDMAXU_VS_M8_E64_MASK = 9200 + + PseudoVREDMAXU_VS_M8_E8 = 9201 + + PseudoVREDMAXU_VS_M8_E8_MASK = 9202 + + PseudoVREDMAXU_VS_MF2_E16 = 9203 + + PseudoVREDMAXU_VS_MF2_E16_MASK = 9204 + + PseudoVREDMAXU_VS_MF2_E32 = 9205 + + PseudoVREDMAXU_VS_MF2_E32_MASK = 9206 + + PseudoVREDMAXU_VS_MF2_E8 = 9207 + + PseudoVREDMAXU_VS_MF2_E8_MASK = 9208 + + PseudoVREDMAXU_VS_MF4_E16 = 9209 + + PseudoVREDMAXU_VS_MF4_E16_MASK = 9210 + + PseudoVREDMAXU_VS_MF4_E8 = 9211 + + PseudoVREDMAXU_VS_MF4_E8_MASK = 9212 + + PseudoVREDMAXU_VS_MF8_E8 = 9213 + + PseudoVREDMAXU_VS_MF8_E8_MASK = 9214 + + PseudoVREDMAX_VS_M1_E16 = 9215 + + PseudoVREDMAX_VS_M1_E16_MASK = 9216 + + PseudoVREDMAX_VS_M1_E32 = 9217 + + PseudoVREDMAX_VS_M1_E32_MASK = 9218 + + PseudoVREDMAX_VS_M1_E64 = 9219 + + PseudoVREDMAX_VS_M1_E64_MASK = 9220 + + PseudoVREDMAX_VS_M1_E8 = 9221 + + PseudoVREDMAX_VS_M1_E8_MASK = 9222 + + PseudoVREDMAX_VS_M2_E16 = 9223 + + PseudoVREDMAX_VS_M2_E16_MASK = 9224 + + PseudoVREDMAX_VS_M2_E32 = 9225 + + PseudoVREDMAX_VS_M2_E32_MASK = 9226 + + PseudoVREDMAX_VS_M2_E64 = 9227 + + PseudoVREDMAX_VS_M2_E64_MASK = 9228 + + PseudoVREDMAX_VS_M2_E8 = 9229 + + PseudoVREDMAX_VS_M2_E8_MASK = 9230 + + PseudoVREDMAX_VS_M4_E16 = 9231 + + PseudoVREDMAX_VS_M4_E16_MASK = 9232 + + PseudoVREDMAX_VS_M4_E32 = 9233 + + PseudoVREDMAX_VS_M4_E32_MASK = 9234 + + PseudoVREDMAX_VS_M4_E64 = 9235 + + PseudoVREDMAX_VS_M4_E64_MASK = 9236 + + PseudoVREDMAX_VS_M4_E8 = 9237 + + PseudoVREDMAX_VS_M4_E8_MASK = 9238 + + PseudoVREDMAX_VS_M8_E16 = 9239 + + PseudoVREDMAX_VS_M8_E16_MASK = 9240 + + PseudoVREDMAX_VS_M8_E32 = 9241 + + PseudoVREDMAX_VS_M8_E32_MASK = 9242 + + PseudoVREDMAX_VS_M8_E64 = 9243 + + PseudoVREDMAX_VS_M8_E64_MASK = 9244 + + PseudoVREDMAX_VS_M8_E8 = 9245 + + PseudoVREDMAX_VS_M8_E8_MASK = 9246 + + PseudoVREDMAX_VS_MF2_E16 = 9247 + + PseudoVREDMAX_VS_MF2_E16_MASK = 9248 + + PseudoVREDMAX_VS_MF2_E32 = 9249 + + PseudoVREDMAX_VS_MF2_E32_MASK = 9250 + + PseudoVREDMAX_VS_MF2_E8 = 9251 + + PseudoVREDMAX_VS_MF2_E8_MASK = 9252 + + PseudoVREDMAX_VS_MF4_E16 = 9253 + + PseudoVREDMAX_VS_MF4_E16_MASK = 9254 + + PseudoVREDMAX_VS_MF4_E8 = 9255 + + PseudoVREDMAX_VS_MF4_E8_MASK = 9256 + + PseudoVREDMAX_VS_MF8_E8 = 9257 + + PseudoVREDMAX_VS_MF8_E8_MASK = 9258 + + PseudoVREDMINU_VS_M1_E16 = 9259 + + PseudoVREDMINU_VS_M1_E16_MASK = 9260 + + PseudoVREDMINU_VS_M1_E32 = 9261 + + PseudoVREDMINU_VS_M1_E32_MASK = 9262 + + PseudoVREDMINU_VS_M1_E64 = 9263 + + PseudoVREDMINU_VS_M1_E64_MASK = 9264 + + PseudoVREDMINU_VS_M1_E8 = 9265 + + PseudoVREDMINU_VS_M1_E8_MASK = 9266 + + PseudoVREDMINU_VS_M2_E16 = 9267 + + PseudoVREDMINU_VS_M2_E16_MASK = 9268 + + PseudoVREDMINU_VS_M2_E32 = 9269 + + PseudoVREDMINU_VS_M2_E32_MASK = 9270 + + PseudoVREDMINU_VS_M2_E64 = 9271 + + PseudoVREDMINU_VS_M2_E64_MASK = 9272 + + PseudoVREDMINU_VS_M2_E8 = 9273 + + PseudoVREDMINU_VS_M2_E8_MASK = 9274 + + PseudoVREDMINU_VS_M4_E16 = 9275 + + PseudoVREDMINU_VS_M4_E16_MASK = 9276 + + PseudoVREDMINU_VS_M4_E32 = 9277 + + PseudoVREDMINU_VS_M4_E32_MASK = 9278 + + PseudoVREDMINU_VS_M4_E64 = 9279 + + PseudoVREDMINU_VS_M4_E64_MASK = 9280 + + PseudoVREDMINU_VS_M4_E8 = 9281 + + PseudoVREDMINU_VS_M4_E8_MASK = 9282 + + PseudoVREDMINU_VS_M8_E16 = 9283 + + PseudoVREDMINU_VS_M8_E16_MASK = 9284 + + PseudoVREDMINU_VS_M8_E32 = 9285 + + PseudoVREDMINU_VS_M8_E32_MASK = 9286 + + PseudoVREDMINU_VS_M8_E64 = 9287 + + PseudoVREDMINU_VS_M8_E64_MASK = 9288 + + PseudoVREDMINU_VS_M8_E8 = 9289 + + PseudoVREDMINU_VS_M8_E8_MASK = 9290 + + PseudoVREDMINU_VS_MF2_E16 = 9291 + + PseudoVREDMINU_VS_MF2_E16_MASK = 9292 + + PseudoVREDMINU_VS_MF2_E32 = 9293 + + PseudoVREDMINU_VS_MF2_E32_MASK = 9294 + + PseudoVREDMINU_VS_MF2_E8 = 9295 + + PseudoVREDMINU_VS_MF2_E8_MASK = 9296 + + PseudoVREDMINU_VS_MF4_E16 = 9297 + + PseudoVREDMINU_VS_MF4_E16_MASK = 9298 + + PseudoVREDMINU_VS_MF4_E8 = 9299 + + PseudoVREDMINU_VS_MF4_E8_MASK = 9300 + + PseudoVREDMINU_VS_MF8_E8 = 9301 + + PseudoVREDMINU_VS_MF8_E8_MASK = 9302 + + PseudoVREDMIN_VS_M1_E16 = 9303 + + PseudoVREDMIN_VS_M1_E16_MASK = 9304 + + PseudoVREDMIN_VS_M1_E32 = 9305 + + PseudoVREDMIN_VS_M1_E32_MASK = 9306 + + PseudoVREDMIN_VS_M1_E64 = 9307 + + PseudoVREDMIN_VS_M1_E64_MASK = 9308 + + PseudoVREDMIN_VS_M1_E8 = 9309 + + PseudoVREDMIN_VS_M1_E8_MASK = 9310 + + PseudoVREDMIN_VS_M2_E16 = 9311 + + PseudoVREDMIN_VS_M2_E16_MASK = 9312 + + PseudoVREDMIN_VS_M2_E32 = 9313 + + PseudoVREDMIN_VS_M2_E32_MASK = 9314 + + PseudoVREDMIN_VS_M2_E64 = 9315 + + PseudoVREDMIN_VS_M2_E64_MASK = 9316 + + PseudoVREDMIN_VS_M2_E8 = 9317 + + PseudoVREDMIN_VS_M2_E8_MASK = 9318 + + PseudoVREDMIN_VS_M4_E16 = 9319 + + PseudoVREDMIN_VS_M4_E16_MASK = 9320 + + PseudoVREDMIN_VS_M4_E32 = 9321 + + PseudoVREDMIN_VS_M4_E32_MASK = 9322 + + PseudoVREDMIN_VS_M4_E64 = 9323 + + PseudoVREDMIN_VS_M4_E64_MASK = 9324 + + PseudoVREDMIN_VS_M4_E8 = 9325 + + PseudoVREDMIN_VS_M4_E8_MASK = 9326 + + PseudoVREDMIN_VS_M8_E16 = 9327 + + PseudoVREDMIN_VS_M8_E16_MASK = 9328 + + PseudoVREDMIN_VS_M8_E32 = 9329 + + PseudoVREDMIN_VS_M8_E32_MASK = 9330 + + PseudoVREDMIN_VS_M8_E64 = 9331 + + PseudoVREDMIN_VS_M8_E64_MASK = 9332 + + PseudoVREDMIN_VS_M8_E8 = 9333 + + PseudoVREDMIN_VS_M8_E8_MASK = 9334 + + PseudoVREDMIN_VS_MF2_E16 = 9335 + + PseudoVREDMIN_VS_MF2_E16_MASK = 9336 + + PseudoVREDMIN_VS_MF2_E32 = 9337 + + PseudoVREDMIN_VS_MF2_E32_MASK = 9338 + + PseudoVREDMIN_VS_MF2_E8 = 9339 + + PseudoVREDMIN_VS_MF2_E8_MASK = 9340 + + PseudoVREDMIN_VS_MF4_E16 = 9341 + + PseudoVREDMIN_VS_MF4_E16_MASK = 9342 + + PseudoVREDMIN_VS_MF4_E8 = 9343 + + PseudoVREDMIN_VS_MF4_E8_MASK = 9344 + + PseudoVREDMIN_VS_MF8_E8 = 9345 + + PseudoVREDMIN_VS_MF8_E8_MASK = 9346 + + PseudoVREDOR_VS_M1_E16 = 9347 + + PseudoVREDOR_VS_M1_E16_MASK = 9348 + + PseudoVREDOR_VS_M1_E32 = 9349 + + PseudoVREDOR_VS_M1_E32_MASK = 9350 + + PseudoVREDOR_VS_M1_E64 = 9351 + + PseudoVREDOR_VS_M1_E64_MASK = 9352 + + PseudoVREDOR_VS_M1_E8 = 9353 + + PseudoVREDOR_VS_M1_E8_MASK = 9354 + + PseudoVREDOR_VS_M2_E16 = 9355 + + PseudoVREDOR_VS_M2_E16_MASK = 9356 + + PseudoVREDOR_VS_M2_E32 = 9357 + + PseudoVREDOR_VS_M2_E32_MASK = 9358 + + PseudoVREDOR_VS_M2_E64 = 9359 + + PseudoVREDOR_VS_M2_E64_MASK = 9360 + + PseudoVREDOR_VS_M2_E8 = 9361 + + PseudoVREDOR_VS_M2_E8_MASK = 9362 + + PseudoVREDOR_VS_M4_E16 = 9363 + + PseudoVREDOR_VS_M4_E16_MASK = 9364 + + PseudoVREDOR_VS_M4_E32 = 9365 + + PseudoVREDOR_VS_M4_E32_MASK = 9366 + + PseudoVREDOR_VS_M4_E64 = 9367 + + PseudoVREDOR_VS_M4_E64_MASK = 9368 + + PseudoVREDOR_VS_M4_E8 = 9369 + + PseudoVREDOR_VS_M4_E8_MASK = 9370 + + PseudoVREDOR_VS_M8_E16 = 9371 + + PseudoVREDOR_VS_M8_E16_MASK = 9372 + + PseudoVREDOR_VS_M8_E32 = 9373 + + PseudoVREDOR_VS_M8_E32_MASK = 9374 + + PseudoVREDOR_VS_M8_E64 = 9375 + + PseudoVREDOR_VS_M8_E64_MASK = 9376 + + PseudoVREDOR_VS_M8_E8 = 9377 + + PseudoVREDOR_VS_M8_E8_MASK = 9378 + + PseudoVREDOR_VS_MF2_E16 = 9379 + + PseudoVREDOR_VS_MF2_E16_MASK = 9380 + + PseudoVREDOR_VS_MF2_E32 = 9381 + + PseudoVREDOR_VS_MF2_E32_MASK = 9382 + + PseudoVREDOR_VS_MF2_E8 = 9383 + + PseudoVREDOR_VS_MF2_E8_MASK = 9384 + + PseudoVREDOR_VS_MF4_E16 = 9385 + + PseudoVREDOR_VS_MF4_E16_MASK = 9386 + + PseudoVREDOR_VS_MF4_E8 = 9387 + + PseudoVREDOR_VS_MF4_E8_MASK = 9388 + + PseudoVREDOR_VS_MF8_E8 = 9389 + + PseudoVREDOR_VS_MF8_E8_MASK = 9390 + + PseudoVREDSUM_VS_M1_E16 = 9391 + + PseudoVREDSUM_VS_M1_E16_MASK = 9392 + + PseudoVREDSUM_VS_M1_E32 = 9393 + + PseudoVREDSUM_VS_M1_E32_MASK = 9394 + + PseudoVREDSUM_VS_M1_E64 = 9395 + + PseudoVREDSUM_VS_M1_E64_MASK = 9396 + + PseudoVREDSUM_VS_M1_E8 = 9397 + + PseudoVREDSUM_VS_M1_E8_MASK = 9398 + + PseudoVREDSUM_VS_M2_E16 = 9399 + + PseudoVREDSUM_VS_M2_E16_MASK = 9400 + + PseudoVREDSUM_VS_M2_E32 = 9401 + + PseudoVREDSUM_VS_M2_E32_MASK = 9402 + + PseudoVREDSUM_VS_M2_E64 = 9403 + + PseudoVREDSUM_VS_M2_E64_MASK = 9404 + + PseudoVREDSUM_VS_M2_E8 = 9405 + + PseudoVREDSUM_VS_M2_E8_MASK = 9406 + + PseudoVREDSUM_VS_M4_E16 = 9407 + + PseudoVREDSUM_VS_M4_E16_MASK = 9408 + + PseudoVREDSUM_VS_M4_E32 = 9409 + + PseudoVREDSUM_VS_M4_E32_MASK = 9410 + + PseudoVREDSUM_VS_M4_E64 = 9411 + + PseudoVREDSUM_VS_M4_E64_MASK = 9412 + + PseudoVREDSUM_VS_M4_E8 = 9413 + + PseudoVREDSUM_VS_M4_E8_MASK = 9414 + + PseudoVREDSUM_VS_M8_E16 = 9415 + + PseudoVREDSUM_VS_M8_E16_MASK = 9416 + + PseudoVREDSUM_VS_M8_E32 = 9417 + + PseudoVREDSUM_VS_M8_E32_MASK = 9418 + + PseudoVREDSUM_VS_M8_E64 = 9419 + + PseudoVREDSUM_VS_M8_E64_MASK = 9420 + + PseudoVREDSUM_VS_M8_E8 = 9421 + + PseudoVREDSUM_VS_M8_E8_MASK = 9422 + + PseudoVREDSUM_VS_MF2_E16 = 9423 + + PseudoVREDSUM_VS_MF2_E16_MASK = 9424 + + PseudoVREDSUM_VS_MF2_E32 = 9425 + + PseudoVREDSUM_VS_MF2_E32_MASK = 9426 + + PseudoVREDSUM_VS_MF2_E8 = 9427 + + PseudoVREDSUM_VS_MF2_E8_MASK = 9428 + + PseudoVREDSUM_VS_MF4_E16 = 9429 + + PseudoVREDSUM_VS_MF4_E16_MASK = 9430 + + PseudoVREDSUM_VS_MF4_E8 = 9431 + + PseudoVREDSUM_VS_MF4_E8_MASK = 9432 + + PseudoVREDSUM_VS_MF8_E8 = 9433 + + PseudoVREDSUM_VS_MF8_E8_MASK = 9434 + + PseudoVREDXOR_VS_M1_E16 = 9435 + + PseudoVREDXOR_VS_M1_E16_MASK = 9436 + + PseudoVREDXOR_VS_M1_E32 = 9437 + + PseudoVREDXOR_VS_M1_E32_MASK = 9438 + + PseudoVREDXOR_VS_M1_E64 = 9439 + + PseudoVREDXOR_VS_M1_E64_MASK = 9440 + + PseudoVREDXOR_VS_M1_E8 = 9441 + + PseudoVREDXOR_VS_M1_E8_MASK = 9442 + + PseudoVREDXOR_VS_M2_E16 = 9443 + + PseudoVREDXOR_VS_M2_E16_MASK = 9444 + + PseudoVREDXOR_VS_M2_E32 = 9445 + + PseudoVREDXOR_VS_M2_E32_MASK = 9446 + + PseudoVREDXOR_VS_M2_E64 = 9447 + + PseudoVREDXOR_VS_M2_E64_MASK = 9448 + + PseudoVREDXOR_VS_M2_E8 = 9449 + + PseudoVREDXOR_VS_M2_E8_MASK = 9450 + + PseudoVREDXOR_VS_M4_E16 = 9451 + + PseudoVREDXOR_VS_M4_E16_MASK = 9452 + + PseudoVREDXOR_VS_M4_E32 = 9453 + + PseudoVREDXOR_VS_M4_E32_MASK = 9454 + + PseudoVREDXOR_VS_M4_E64 = 9455 + + PseudoVREDXOR_VS_M4_E64_MASK = 9456 + + PseudoVREDXOR_VS_M4_E8 = 9457 + + PseudoVREDXOR_VS_M4_E8_MASK = 9458 + + PseudoVREDXOR_VS_M8_E16 = 9459 + + PseudoVREDXOR_VS_M8_E16_MASK = 9460 + + PseudoVREDXOR_VS_M8_E32 = 9461 + + PseudoVREDXOR_VS_M8_E32_MASK = 9462 + + PseudoVREDXOR_VS_M8_E64 = 9463 + + PseudoVREDXOR_VS_M8_E64_MASK = 9464 + + PseudoVREDXOR_VS_M8_E8 = 9465 + + PseudoVREDXOR_VS_M8_E8_MASK = 9466 + + PseudoVREDXOR_VS_MF2_E16 = 9467 + + PseudoVREDXOR_VS_MF2_E16_MASK = 9468 + + PseudoVREDXOR_VS_MF2_E32 = 9469 + + PseudoVREDXOR_VS_MF2_E32_MASK = 9470 + + PseudoVREDXOR_VS_MF2_E8 = 9471 + + PseudoVREDXOR_VS_MF2_E8_MASK = 9472 + + PseudoVREDXOR_VS_MF4_E16 = 9473 + + PseudoVREDXOR_VS_MF4_E16_MASK = 9474 + + PseudoVREDXOR_VS_MF4_E8 = 9475 + + PseudoVREDXOR_VS_MF4_E8_MASK = 9476 + + PseudoVREDXOR_VS_MF8_E8 = 9477 + + PseudoVREDXOR_VS_MF8_E8_MASK = 9478 + + PseudoVRELOAD2_M1 = 9479 + + PseudoVRELOAD2_M2 = 9480 + + PseudoVRELOAD2_M4 = 9481 + + PseudoVRELOAD2_MF2 = 9482 + + PseudoVRELOAD2_MF4 = 9483 + + PseudoVRELOAD2_MF8 = 9484 + + PseudoVRELOAD3_M1 = 9485 + + PseudoVRELOAD3_M2 = 9486 + + PseudoVRELOAD3_MF2 = 9487 + + PseudoVRELOAD3_MF4 = 9488 + + PseudoVRELOAD3_MF8 = 9489 + + PseudoVRELOAD4_M1 = 9490 + + PseudoVRELOAD4_M2 = 9491 + + PseudoVRELOAD4_MF2 = 9492 + + PseudoVRELOAD4_MF4 = 9493 + + PseudoVRELOAD4_MF8 = 9494 + + PseudoVRELOAD5_M1 = 9495 + + PseudoVRELOAD5_MF2 = 9496 + + PseudoVRELOAD5_MF4 = 9497 + + PseudoVRELOAD5_MF8 = 9498 + + PseudoVRELOAD6_M1 = 9499 + + PseudoVRELOAD6_MF2 = 9500 + + PseudoVRELOAD6_MF4 = 9501 + + PseudoVRELOAD6_MF8 = 9502 + + PseudoVRELOAD7_M1 = 9503 + + PseudoVRELOAD7_MF2 = 9504 + + PseudoVRELOAD7_MF4 = 9505 + + PseudoVRELOAD7_MF8 = 9506 + + PseudoVRELOAD8_M1 = 9507 + + PseudoVRELOAD8_MF2 = 9508 + + PseudoVRELOAD8_MF4 = 9509 + + PseudoVRELOAD8_MF8 = 9510 + + PseudoVREMU_VV_M1_E16 = 9511 + + PseudoVREMU_VV_M1_E16_MASK = 9512 + + PseudoVREMU_VV_M1_E32 = 9513 + + PseudoVREMU_VV_M1_E32_MASK = 9514 + + PseudoVREMU_VV_M1_E64 = 9515 + + PseudoVREMU_VV_M1_E64_MASK = 9516 + + PseudoVREMU_VV_M1_E8 = 9517 + + PseudoVREMU_VV_M1_E8_MASK = 9518 + + PseudoVREMU_VV_M2_E16 = 9519 + + PseudoVREMU_VV_M2_E16_MASK = 9520 + + PseudoVREMU_VV_M2_E32 = 9521 + + PseudoVREMU_VV_M2_E32_MASK = 9522 + + PseudoVREMU_VV_M2_E64 = 9523 + + PseudoVREMU_VV_M2_E64_MASK = 9524 + + PseudoVREMU_VV_M2_E8 = 9525 + + PseudoVREMU_VV_M2_E8_MASK = 9526 + + PseudoVREMU_VV_M4_E16 = 9527 + + PseudoVREMU_VV_M4_E16_MASK = 9528 + + PseudoVREMU_VV_M4_E32 = 9529 + + PseudoVREMU_VV_M4_E32_MASK = 9530 + + PseudoVREMU_VV_M4_E64 = 9531 + + PseudoVREMU_VV_M4_E64_MASK = 9532 + + PseudoVREMU_VV_M4_E8 = 9533 + + PseudoVREMU_VV_M4_E8_MASK = 9534 + + PseudoVREMU_VV_M8_E16 = 9535 + + PseudoVREMU_VV_M8_E16_MASK = 9536 + + PseudoVREMU_VV_M8_E32 = 9537 + + PseudoVREMU_VV_M8_E32_MASK = 9538 + + PseudoVREMU_VV_M8_E64 = 9539 + + PseudoVREMU_VV_M8_E64_MASK = 9540 + + PseudoVREMU_VV_M8_E8 = 9541 + + PseudoVREMU_VV_M8_E8_MASK = 9542 + + PseudoVREMU_VV_MF2_E16 = 9543 + + PseudoVREMU_VV_MF2_E16_MASK = 9544 + + PseudoVREMU_VV_MF2_E32 = 9545 + + PseudoVREMU_VV_MF2_E32_MASK = 9546 + + PseudoVREMU_VV_MF2_E8 = 9547 + + PseudoVREMU_VV_MF2_E8_MASK = 9548 + + PseudoVREMU_VV_MF4_E16 = 9549 + + PseudoVREMU_VV_MF4_E16_MASK = 9550 + + PseudoVREMU_VV_MF4_E8 = 9551 + + PseudoVREMU_VV_MF4_E8_MASK = 9552 + + PseudoVREMU_VV_MF8_E8 = 9553 + + PseudoVREMU_VV_MF8_E8_MASK = 9554 + + PseudoVREMU_VX_M1_E16 = 9555 + + PseudoVREMU_VX_M1_E16_MASK = 9556 + + PseudoVREMU_VX_M1_E32 = 9557 + + PseudoVREMU_VX_M1_E32_MASK = 9558 + + PseudoVREMU_VX_M1_E64 = 9559 + + PseudoVREMU_VX_M1_E64_MASK = 9560 + + PseudoVREMU_VX_M1_E8 = 9561 + + PseudoVREMU_VX_M1_E8_MASK = 9562 + + PseudoVREMU_VX_M2_E16 = 9563 + + PseudoVREMU_VX_M2_E16_MASK = 9564 + + PseudoVREMU_VX_M2_E32 = 9565 + + PseudoVREMU_VX_M2_E32_MASK = 9566 + + PseudoVREMU_VX_M2_E64 = 9567 + + PseudoVREMU_VX_M2_E64_MASK = 9568 + + PseudoVREMU_VX_M2_E8 = 9569 + + PseudoVREMU_VX_M2_E8_MASK = 9570 + + PseudoVREMU_VX_M4_E16 = 9571 + + PseudoVREMU_VX_M4_E16_MASK = 9572 + + PseudoVREMU_VX_M4_E32 = 9573 + + PseudoVREMU_VX_M4_E32_MASK = 9574 + + PseudoVREMU_VX_M4_E64 = 9575 + + PseudoVREMU_VX_M4_E64_MASK = 9576 + + PseudoVREMU_VX_M4_E8 = 9577 + + PseudoVREMU_VX_M4_E8_MASK = 9578 + + PseudoVREMU_VX_M8_E16 = 9579 + + PseudoVREMU_VX_M8_E16_MASK = 9580 + + PseudoVREMU_VX_M8_E32 = 9581 + + PseudoVREMU_VX_M8_E32_MASK = 9582 + + PseudoVREMU_VX_M8_E64 = 9583 + + PseudoVREMU_VX_M8_E64_MASK = 9584 + + PseudoVREMU_VX_M8_E8 = 9585 + + PseudoVREMU_VX_M8_E8_MASK = 9586 + + PseudoVREMU_VX_MF2_E16 = 9587 + + PseudoVREMU_VX_MF2_E16_MASK = 9588 + + PseudoVREMU_VX_MF2_E32 = 9589 + + PseudoVREMU_VX_MF2_E32_MASK = 9590 + + PseudoVREMU_VX_MF2_E8 = 9591 + + PseudoVREMU_VX_MF2_E8_MASK = 9592 + + PseudoVREMU_VX_MF4_E16 = 9593 + + PseudoVREMU_VX_MF4_E16_MASK = 9594 + + PseudoVREMU_VX_MF4_E8 = 9595 + + PseudoVREMU_VX_MF4_E8_MASK = 9596 + + PseudoVREMU_VX_MF8_E8 = 9597 + + PseudoVREMU_VX_MF8_E8_MASK = 9598 + + PseudoVREM_VV_M1_E16 = 9599 + + PseudoVREM_VV_M1_E16_MASK = 9600 + + PseudoVREM_VV_M1_E32 = 9601 + + PseudoVREM_VV_M1_E32_MASK = 9602 + + PseudoVREM_VV_M1_E64 = 9603 + + PseudoVREM_VV_M1_E64_MASK = 9604 + + PseudoVREM_VV_M1_E8 = 9605 + + PseudoVREM_VV_M1_E8_MASK = 9606 + + PseudoVREM_VV_M2_E16 = 9607 + + PseudoVREM_VV_M2_E16_MASK = 9608 + + PseudoVREM_VV_M2_E32 = 9609 + + PseudoVREM_VV_M2_E32_MASK = 9610 + + PseudoVREM_VV_M2_E64 = 9611 + + PseudoVREM_VV_M2_E64_MASK = 9612 + + PseudoVREM_VV_M2_E8 = 9613 + + PseudoVREM_VV_M2_E8_MASK = 9614 + + PseudoVREM_VV_M4_E16 = 9615 + + PseudoVREM_VV_M4_E16_MASK = 9616 + + PseudoVREM_VV_M4_E32 = 9617 + + PseudoVREM_VV_M4_E32_MASK = 9618 + + PseudoVREM_VV_M4_E64 = 9619 + + PseudoVREM_VV_M4_E64_MASK = 9620 + + PseudoVREM_VV_M4_E8 = 9621 + + PseudoVREM_VV_M4_E8_MASK = 9622 + + PseudoVREM_VV_M8_E16 = 9623 + + PseudoVREM_VV_M8_E16_MASK = 9624 + + PseudoVREM_VV_M8_E32 = 9625 + + PseudoVREM_VV_M8_E32_MASK = 9626 + + PseudoVREM_VV_M8_E64 = 9627 + + PseudoVREM_VV_M8_E64_MASK = 9628 + + PseudoVREM_VV_M8_E8 = 9629 + + PseudoVREM_VV_M8_E8_MASK = 9630 + + PseudoVREM_VV_MF2_E16 = 9631 + + PseudoVREM_VV_MF2_E16_MASK = 9632 + + PseudoVREM_VV_MF2_E32 = 9633 + + PseudoVREM_VV_MF2_E32_MASK = 9634 + + PseudoVREM_VV_MF2_E8 = 9635 + + PseudoVREM_VV_MF2_E8_MASK = 9636 + + PseudoVREM_VV_MF4_E16 = 9637 + + PseudoVREM_VV_MF4_E16_MASK = 9638 + + PseudoVREM_VV_MF4_E8 = 9639 + + PseudoVREM_VV_MF4_E8_MASK = 9640 + + PseudoVREM_VV_MF8_E8 = 9641 + + PseudoVREM_VV_MF8_E8_MASK = 9642 + + PseudoVREM_VX_M1_E16 = 9643 + + PseudoVREM_VX_M1_E16_MASK = 9644 + + PseudoVREM_VX_M1_E32 = 9645 + + PseudoVREM_VX_M1_E32_MASK = 9646 + + PseudoVREM_VX_M1_E64 = 9647 + + PseudoVREM_VX_M1_E64_MASK = 9648 + + PseudoVREM_VX_M1_E8 = 9649 + + PseudoVREM_VX_M1_E8_MASK = 9650 + + PseudoVREM_VX_M2_E16 = 9651 + + PseudoVREM_VX_M2_E16_MASK = 9652 + + PseudoVREM_VX_M2_E32 = 9653 + + PseudoVREM_VX_M2_E32_MASK = 9654 + + PseudoVREM_VX_M2_E64 = 9655 + + PseudoVREM_VX_M2_E64_MASK = 9656 + + PseudoVREM_VX_M2_E8 = 9657 + + PseudoVREM_VX_M2_E8_MASK = 9658 + + PseudoVREM_VX_M4_E16 = 9659 + + PseudoVREM_VX_M4_E16_MASK = 9660 + + PseudoVREM_VX_M4_E32 = 9661 + + PseudoVREM_VX_M4_E32_MASK = 9662 + + PseudoVREM_VX_M4_E64 = 9663 + + PseudoVREM_VX_M4_E64_MASK = 9664 + + PseudoVREM_VX_M4_E8 = 9665 + + PseudoVREM_VX_M4_E8_MASK = 9666 + + PseudoVREM_VX_M8_E16 = 9667 + + PseudoVREM_VX_M8_E16_MASK = 9668 + + PseudoVREM_VX_M8_E32 = 9669 + + PseudoVREM_VX_M8_E32_MASK = 9670 + + PseudoVREM_VX_M8_E64 = 9671 + + PseudoVREM_VX_M8_E64_MASK = 9672 + + PseudoVREM_VX_M8_E8 = 9673 + + PseudoVREM_VX_M8_E8_MASK = 9674 + + PseudoVREM_VX_MF2_E16 = 9675 + + PseudoVREM_VX_MF2_E16_MASK = 9676 + + PseudoVREM_VX_MF2_E32 = 9677 + + PseudoVREM_VX_MF2_E32_MASK = 9678 + + PseudoVREM_VX_MF2_E8 = 9679 + + PseudoVREM_VX_MF2_E8_MASK = 9680 + + PseudoVREM_VX_MF4_E16 = 9681 + + PseudoVREM_VX_MF4_E16_MASK = 9682 + + PseudoVREM_VX_MF4_E8 = 9683 + + PseudoVREM_VX_MF4_E8_MASK = 9684 + + PseudoVREM_VX_MF8_E8 = 9685 + + PseudoVREM_VX_MF8_E8_MASK = 9686 + + PseudoVREV8_V_M1 = 9687 + + PseudoVREV8_V_M1_MASK = 9688 + + PseudoVREV8_V_M2 = 9689 + + PseudoVREV8_V_M2_MASK = 9690 + + PseudoVREV8_V_M4 = 9691 + + PseudoVREV8_V_M4_MASK = 9692 + + PseudoVREV8_V_M8 = 9693 + + PseudoVREV8_V_M8_MASK = 9694 + + PseudoVREV8_V_MF2 = 9695 + + PseudoVREV8_V_MF2_MASK = 9696 + + PseudoVREV8_V_MF4 = 9697 + + PseudoVREV8_V_MF4_MASK = 9698 + + PseudoVREV8_V_MF8 = 9699 + + PseudoVREV8_V_MF8_MASK = 9700 + + PseudoVRGATHEREI16_VV_M1_E16_M1 = 9701 + + PseudoVRGATHEREI16_VV_M1_E16_M1_MASK = 9702 + + PseudoVRGATHEREI16_VV_M1_E16_M2 = 9703 + + PseudoVRGATHEREI16_VV_M1_E16_M2_MASK = 9704 + + PseudoVRGATHEREI16_VV_M1_E16_MF2 = 9705 + + PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK = 9706 + + PseudoVRGATHEREI16_VV_M1_E16_MF4 = 9707 + + PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK = 9708 + + PseudoVRGATHEREI16_VV_M1_E32_M1 = 9709 + + PseudoVRGATHEREI16_VV_M1_E32_M1_MASK = 9710 + + PseudoVRGATHEREI16_VV_M1_E32_M2 = 9711 + + PseudoVRGATHEREI16_VV_M1_E32_M2_MASK = 9712 + + PseudoVRGATHEREI16_VV_M1_E32_MF2 = 9713 + + PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK = 9714 + + PseudoVRGATHEREI16_VV_M1_E32_MF4 = 9715 + + PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK = 9716 + + PseudoVRGATHEREI16_VV_M1_E64_M1 = 9717 + + PseudoVRGATHEREI16_VV_M1_E64_M1_MASK = 9718 + + PseudoVRGATHEREI16_VV_M1_E64_M2 = 9719 + + PseudoVRGATHEREI16_VV_M1_E64_M2_MASK = 9720 + + PseudoVRGATHEREI16_VV_M1_E64_MF2 = 9721 + + PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK = 9722 + + PseudoVRGATHEREI16_VV_M1_E64_MF4 = 9723 + + PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK = 9724 + + PseudoVRGATHEREI16_VV_M1_E8_M1 = 9725 + + PseudoVRGATHEREI16_VV_M1_E8_M1_MASK = 9726 + + PseudoVRGATHEREI16_VV_M1_E8_M2 = 9727 + + PseudoVRGATHEREI16_VV_M1_E8_M2_MASK = 9728 + + PseudoVRGATHEREI16_VV_M1_E8_MF2 = 9729 + + PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK = 9730 + + PseudoVRGATHEREI16_VV_M1_E8_MF4 = 9731 + + PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK = 9732 + + PseudoVRGATHEREI16_VV_M2_E16_M1 = 9733 + + PseudoVRGATHEREI16_VV_M2_E16_M1_MASK = 9734 + + PseudoVRGATHEREI16_VV_M2_E16_M2 = 9735 + + PseudoVRGATHEREI16_VV_M2_E16_M2_MASK = 9736 + + PseudoVRGATHEREI16_VV_M2_E16_M4 = 9737 + + PseudoVRGATHEREI16_VV_M2_E16_M4_MASK = 9738 + + PseudoVRGATHEREI16_VV_M2_E16_MF2 = 9739 + + PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK = 9740 + + PseudoVRGATHEREI16_VV_M2_E32_M1 = 9741 + + PseudoVRGATHEREI16_VV_M2_E32_M1_MASK = 9742 + + PseudoVRGATHEREI16_VV_M2_E32_M2 = 9743 + + PseudoVRGATHEREI16_VV_M2_E32_M2_MASK = 9744 + + PseudoVRGATHEREI16_VV_M2_E32_M4 = 9745 + + PseudoVRGATHEREI16_VV_M2_E32_M4_MASK = 9746 + + PseudoVRGATHEREI16_VV_M2_E32_MF2 = 9747 + + PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK = 9748 + + PseudoVRGATHEREI16_VV_M2_E64_M1 = 9749 + + PseudoVRGATHEREI16_VV_M2_E64_M1_MASK = 9750 + + PseudoVRGATHEREI16_VV_M2_E64_M2 = 9751 + + PseudoVRGATHEREI16_VV_M2_E64_M2_MASK = 9752 + + PseudoVRGATHEREI16_VV_M2_E64_M4 = 9753 + + PseudoVRGATHEREI16_VV_M2_E64_M4_MASK = 9754 + + PseudoVRGATHEREI16_VV_M2_E64_MF2 = 9755 + + PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK = 9756 + + PseudoVRGATHEREI16_VV_M2_E8_M1 = 9757 + + PseudoVRGATHEREI16_VV_M2_E8_M1_MASK = 9758 + + PseudoVRGATHEREI16_VV_M2_E8_M2 = 9759 + + PseudoVRGATHEREI16_VV_M2_E8_M2_MASK = 9760 + + PseudoVRGATHEREI16_VV_M2_E8_M4 = 9761 + + PseudoVRGATHEREI16_VV_M2_E8_M4_MASK = 9762 + + PseudoVRGATHEREI16_VV_M2_E8_MF2 = 9763 + + PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK = 9764 + + PseudoVRGATHEREI16_VV_M4_E16_M1 = 9765 + + PseudoVRGATHEREI16_VV_M4_E16_M1_MASK = 9766 + + PseudoVRGATHEREI16_VV_M4_E16_M2 = 9767 + + PseudoVRGATHEREI16_VV_M4_E16_M2_MASK = 9768 + + PseudoVRGATHEREI16_VV_M4_E16_M4 = 9769 + + PseudoVRGATHEREI16_VV_M4_E16_M4_MASK = 9770 + + PseudoVRGATHEREI16_VV_M4_E16_M8 = 9771 + + PseudoVRGATHEREI16_VV_M4_E16_M8_MASK = 9772 + + PseudoVRGATHEREI16_VV_M4_E32_M1 = 9773 + + PseudoVRGATHEREI16_VV_M4_E32_M1_MASK = 9774 + + PseudoVRGATHEREI16_VV_M4_E32_M2 = 9775 + + PseudoVRGATHEREI16_VV_M4_E32_M2_MASK = 9776 + + PseudoVRGATHEREI16_VV_M4_E32_M4 = 9777 + + PseudoVRGATHEREI16_VV_M4_E32_M4_MASK = 9778 + + PseudoVRGATHEREI16_VV_M4_E32_M8 = 9779 + + PseudoVRGATHEREI16_VV_M4_E32_M8_MASK = 9780 + + PseudoVRGATHEREI16_VV_M4_E64_M1 = 9781 + + PseudoVRGATHEREI16_VV_M4_E64_M1_MASK = 9782 + + PseudoVRGATHEREI16_VV_M4_E64_M2 = 9783 + + PseudoVRGATHEREI16_VV_M4_E64_M2_MASK = 9784 + + PseudoVRGATHEREI16_VV_M4_E64_M4 = 9785 + + PseudoVRGATHEREI16_VV_M4_E64_M4_MASK = 9786 + + PseudoVRGATHEREI16_VV_M4_E64_M8 = 9787 + + PseudoVRGATHEREI16_VV_M4_E64_M8_MASK = 9788 + + PseudoVRGATHEREI16_VV_M4_E8_M1 = 9789 + + PseudoVRGATHEREI16_VV_M4_E8_M1_MASK = 9790 + + PseudoVRGATHEREI16_VV_M4_E8_M2 = 9791 + + PseudoVRGATHEREI16_VV_M4_E8_M2_MASK = 9792 + + PseudoVRGATHEREI16_VV_M4_E8_M4 = 9793 + + PseudoVRGATHEREI16_VV_M4_E8_M4_MASK = 9794 + + PseudoVRGATHEREI16_VV_M4_E8_M8 = 9795 + + PseudoVRGATHEREI16_VV_M4_E8_M8_MASK = 9796 + + PseudoVRGATHEREI16_VV_M8_E16_M2 = 9797 + + PseudoVRGATHEREI16_VV_M8_E16_M2_MASK = 9798 + + PseudoVRGATHEREI16_VV_M8_E16_M4 = 9799 + + PseudoVRGATHEREI16_VV_M8_E16_M4_MASK = 9800 + + PseudoVRGATHEREI16_VV_M8_E16_M8 = 9801 + + PseudoVRGATHEREI16_VV_M8_E16_M8_MASK = 9802 + + PseudoVRGATHEREI16_VV_M8_E32_M2 = 9803 + + PseudoVRGATHEREI16_VV_M8_E32_M2_MASK = 9804 + + PseudoVRGATHEREI16_VV_M8_E32_M4 = 9805 + + PseudoVRGATHEREI16_VV_M8_E32_M4_MASK = 9806 + + PseudoVRGATHEREI16_VV_M8_E32_M8 = 9807 + + PseudoVRGATHEREI16_VV_M8_E32_M8_MASK = 9808 + + PseudoVRGATHEREI16_VV_M8_E64_M2 = 9809 + + PseudoVRGATHEREI16_VV_M8_E64_M2_MASK = 9810 + + PseudoVRGATHEREI16_VV_M8_E64_M4 = 9811 + + PseudoVRGATHEREI16_VV_M8_E64_M4_MASK = 9812 + + PseudoVRGATHEREI16_VV_M8_E64_M8 = 9813 + + PseudoVRGATHEREI16_VV_M8_E64_M8_MASK = 9814 + + PseudoVRGATHEREI16_VV_M8_E8_M2 = 9815 + + PseudoVRGATHEREI16_VV_M8_E8_M2_MASK = 9816 + + PseudoVRGATHEREI16_VV_M8_E8_M4 = 9817 + + PseudoVRGATHEREI16_VV_M8_E8_M4_MASK = 9818 + + PseudoVRGATHEREI16_VV_M8_E8_M8 = 9819 + + PseudoVRGATHEREI16_VV_M8_E8_M8_MASK = 9820 + + PseudoVRGATHEREI16_VV_MF2_E16_M1 = 9821 + + PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK = 9822 + + PseudoVRGATHEREI16_VV_MF2_E16_MF2 = 9823 + + PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK = 9824 + + PseudoVRGATHEREI16_VV_MF2_E16_MF4 = 9825 + + PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK = 9826 + + PseudoVRGATHEREI16_VV_MF2_E16_MF8 = 9827 + + PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK = 9828 + + PseudoVRGATHEREI16_VV_MF2_E32_M1 = 9829 + + PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK = 9830 + + PseudoVRGATHEREI16_VV_MF2_E32_MF2 = 9831 + + PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK = 9832 + + PseudoVRGATHEREI16_VV_MF2_E32_MF4 = 9833 + + PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK = 9834 + + PseudoVRGATHEREI16_VV_MF2_E32_MF8 = 9835 + + PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK = 9836 + + PseudoVRGATHEREI16_VV_MF2_E8_M1 = 9837 + + PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK = 9838 + + PseudoVRGATHEREI16_VV_MF2_E8_MF2 = 9839 + + PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK = 9840 + + PseudoVRGATHEREI16_VV_MF2_E8_MF4 = 9841 + + PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK = 9842 + + PseudoVRGATHEREI16_VV_MF2_E8_MF8 = 9843 + + PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK = 9844 + + PseudoVRGATHEREI16_VV_MF4_E16_MF2 = 9845 + + PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK = 9846 + + PseudoVRGATHEREI16_VV_MF4_E16_MF4 = 9847 + + PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK = 9848 + + PseudoVRGATHEREI16_VV_MF4_E16_MF8 = 9849 + + PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK = 9850 + + PseudoVRGATHEREI16_VV_MF4_E8_MF2 = 9851 + + PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK = 9852 + + PseudoVRGATHEREI16_VV_MF4_E8_MF4 = 9853 + + PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK = 9854 + + PseudoVRGATHEREI16_VV_MF4_E8_MF8 = 9855 + + PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK = 9856 + + PseudoVRGATHEREI16_VV_MF8_E8_MF4 = 9857 + + PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK = 9858 + + PseudoVRGATHEREI16_VV_MF8_E8_MF8 = 9859 + + PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK = 9860 + + PseudoVRGATHER_VI_M1 = 9861 + + PseudoVRGATHER_VI_M1_MASK = 9862 + + PseudoVRGATHER_VI_M2 = 9863 + + PseudoVRGATHER_VI_M2_MASK = 9864 + + PseudoVRGATHER_VI_M4 = 9865 + + PseudoVRGATHER_VI_M4_MASK = 9866 + + PseudoVRGATHER_VI_M8 = 9867 + + PseudoVRGATHER_VI_M8_MASK = 9868 + + PseudoVRGATHER_VI_MF2 = 9869 + + PseudoVRGATHER_VI_MF2_MASK = 9870 + + PseudoVRGATHER_VI_MF4 = 9871 + + PseudoVRGATHER_VI_MF4_MASK = 9872 + + PseudoVRGATHER_VI_MF8 = 9873 + + PseudoVRGATHER_VI_MF8_MASK = 9874 + + PseudoVRGATHER_VV_M1_E16 = 9875 + + PseudoVRGATHER_VV_M1_E16_MASK = 9876 + + PseudoVRGATHER_VV_M1_E32 = 9877 + + PseudoVRGATHER_VV_M1_E32_MASK = 9878 + + PseudoVRGATHER_VV_M1_E64 = 9879 + + PseudoVRGATHER_VV_M1_E64_MASK = 9880 + + PseudoVRGATHER_VV_M1_E8 = 9881 + + PseudoVRGATHER_VV_M1_E8_MASK = 9882 + + PseudoVRGATHER_VV_M2_E16 = 9883 + + PseudoVRGATHER_VV_M2_E16_MASK = 9884 + + PseudoVRGATHER_VV_M2_E32 = 9885 + + PseudoVRGATHER_VV_M2_E32_MASK = 9886 + + PseudoVRGATHER_VV_M2_E64 = 9887 + + PseudoVRGATHER_VV_M2_E64_MASK = 9888 + + PseudoVRGATHER_VV_M2_E8 = 9889 + + PseudoVRGATHER_VV_M2_E8_MASK = 9890 + + PseudoVRGATHER_VV_M4_E16 = 9891 + + PseudoVRGATHER_VV_M4_E16_MASK = 9892 + + PseudoVRGATHER_VV_M4_E32 = 9893 + + PseudoVRGATHER_VV_M4_E32_MASK = 9894 + + PseudoVRGATHER_VV_M4_E64 = 9895 + + PseudoVRGATHER_VV_M4_E64_MASK = 9896 + + PseudoVRGATHER_VV_M4_E8 = 9897 + + PseudoVRGATHER_VV_M4_E8_MASK = 9898 + + PseudoVRGATHER_VV_M8_E16 = 9899 + + PseudoVRGATHER_VV_M8_E16_MASK = 9900 + + PseudoVRGATHER_VV_M8_E32 = 9901 + + PseudoVRGATHER_VV_M8_E32_MASK = 9902 + + PseudoVRGATHER_VV_M8_E64 = 9903 + + PseudoVRGATHER_VV_M8_E64_MASK = 9904 + + PseudoVRGATHER_VV_M8_E8 = 9905 + + PseudoVRGATHER_VV_M8_E8_MASK = 9906 + + PseudoVRGATHER_VV_MF2_E16 = 9907 + + PseudoVRGATHER_VV_MF2_E16_MASK = 9908 + + PseudoVRGATHER_VV_MF2_E32 = 9909 + + PseudoVRGATHER_VV_MF2_E32_MASK = 9910 + + PseudoVRGATHER_VV_MF2_E8 = 9911 + + PseudoVRGATHER_VV_MF2_E8_MASK = 9912 + + PseudoVRGATHER_VV_MF4_E16 = 9913 + + PseudoVRGATHER_VV_MF4_E16_MASK = 9914 + + PseudoVRGATHER_VV_MF4_E8 = 9915 + + PseudoVRGATHER_VV_MF4_E8_MASK = 9916 + + PseudoVRGATHER_VV_MF8_E8 = 9917 + + PseudoVRGATHER_VV_MF8_E8_MASK = 9918 + + PseudoVRGATHER_VX_M1 = 9919 + + PseudoVRGATHER_VX_M1_MASK = 9920 + + PseudoVRGATHER_VX_M2 = 9921 + + PseudoVRGATHER_VX_M2_MASK = 9922 + + PseudoVRGATHER_VX_M4 = 9923 + + PseudoVRGATHER_VX_M4_MASK = 9924 + + PseudoVRGATHER_VX_M8 = 9925 + + PseudoVRGATHER_VX_M8_MASK = 9926 + + PseudoVRGATHER_VX_MF2 = 9927 + + PseudoVRGATHER_VX_MF2_MASK = 9928 + + PseudoVRGATHER_VX_MF4 = 9929 + + PseudoVRGATHER_VX_MF4_MASK = 9930 + + PseudoVRGATHER_VX_MF8 = 9931 + + PseudoVRGATHER_VX_MF8_MASK = 9932 + + PseudoVROL_VV_M1 = 9933 + + PseudoVROL_VV_M1_MASK = 9934 + + PseudoVROL_VV_M2 = 9935 + + PseudoVROL_VV_M2_MASK = 9936 + + PseudoVROL_VV_M4 = 9937 + + PseudoVROL_VV_M4_MASK = 9938 + + PseudoVROL_VV_M8 = 9939 + + PseudoVROL_VV_M8_MASK = 9940 + + PseudoVROL_VV_MF2 = 9941 + + PseudoVROL_VV_MF2_MASK = 9942 + + PseudoVROL_VV_MF4 = 9943 + + PseudoVROL_VV_MF4_MASK = 9944 + + PseudoVROL_VV_MF8 = 9945 + + PseudoVROL_VV_MF8_MASK = 9946 + + PseudoVROL_VX_M1 = 9947 + + PseudoVROL_VX_M1_MASK = 9948 + + PseudoVROL_VX_M2 = 9949 + + PseudoVROL_VX_M2_MASK = 9950 + + PseudoVROL_VX_M4 = 9951 + + PseudoVROL_VX_M4_MASK = 9952 + + PseudoVROL_VX_M8 = 9953 + + PseudoVROL_VX_M8_MASK = 9954 + + PseudoVROL_VX_MF2 = 9955 + + PseudoVROL_VX_MF2_MASK = 9956 + + PseudoVROL_VX_MF4 = 9957 + + PseudoVROL_VX_MF4_MASK = 9958 + + PseudoVROL_VX_MF8 = 9959 + + PseudoVROL_VX_MF8_MASK = 9960 + + PseudoVROR_VI_M1 = 9961 + + PseudoVROR_VI_M1_MASK = 9962 + + PseudoVROR_VI_M2 = 9963 + + PseudoVROR_VI_M2_MASK = 9964 + + PseudoVROR_VI_M4 = 9965 + + PseudoVROR_VI_M4_MASK = 9966 + + PseudoVROR_VI_M8 = 9967 + + PseudoVROR_VI_M8_MASK = 9968 + + PseudoVROR_VI_MF2 = 9969 + + PseudoVROR_VI_MF2_MASK = 9970 + + PseudoVROR_VI_MF4 = 9971 + + PseudoVROR_VI_MF4_MASK = 9972 + + PseudoVROR_VI_MF8 = 9973 + + PseudoVROR_VI_MF8_MASK = 9974 + + PseudoVROR_VV_M1 = 9975 + + PseudoVROR_VV_M1_MASK = 9976 + + PseudoVROR_VV_M2 = 9977 + + PseudoVROR_VV_M2_MASK = 9978 + + PseudoVROR_VV_M4 = 9979 + + PseudoVROR_VV_M4_MASK = 9980 + + PseudoVROR_VV_M8 = 9981 + + PseudoVROR_VV_M8_MASK = 9982 + + PseudoVROR_VV_MF2 = 9983 + + PseudoVROR_VV_MF2_MASK = 9984 + + PseudoVROR_VV_MF4 = 9985 + + PseudoVROR_VV_MF4_MASK = 9986 + + PseudoVROR_VV_MF8 = 9987 + + PseudoVROR_VV_MF8_MASK = 9988 + + PseudoVROR_VX_M1 = 9989 + + PseudoVROR_VX_M1_MASK = 9990 + + PseudoVROR_VX_M2 = 9991 + + PseudoVROR_VX_M2_MASK = 9992 + + PseudoVROR_VX_M4 = 9993 + + PseudoVROR_VX_M4_MASK = 9994 + + PseudoVROR_VX_M8 = 9995 + + PseudoVROR_VX_M8_MASK = 9996 + + PseudoVROR_VX_MF2 = 9997 + + PseudoVROR_VX_MF2_MASK = 9998 + + PseudoVROR_VX_MF4 = 9999 + + PseudoVROR_VX_MF4_MASK = 10000 + + PseudoVROR_VX_MF8 = 10001 + + PseudoVROR_VX_MF8_MASK = 10002 + + PseudoVRSUB_VI_M1 = 10003 + + PseudoVRSUB_VI_M1_MASK = 10004 + + PseudoVRSUB_VI_M2 = 10005 + + PseudoVRSUB_VI_M2_MASK = 10006 + + PseudoVRSUB_VI_M4 = 10007 + + PseudoVRSUB_VI_M4_MASK = 10008 + + PseudoVRSUB_VI_M8 = 10009 + + PseudoVRSUB_VI_M8_MASK = 10010 + + PseudoVRSUB_VI_MF2 = 10011 + + PseudoVRSUB_VI_MF2_MASK = 10012 + + PseudoVRSUB_VI_MF4 = 10013 + + PseudoVRSUB_VI_MF4_MASK = 10014 + + PseudoVRSUB_VI_MF8 = 10015 + + PseudoVRSUB_VI_MF8_MASK = 10016 + + PseudoVRSUB_VX_M1 = 10017 + + PseudoVRSUB_VX_M1_MASK = 10018 + + PseudoVRSUB_VX_M2 = 10019 + + PseudoVRSUB_VX_M2_MASK = 10020 + + PseudoVRSUB_VX_M4 = 10021 + + PseudoVRSUB_VX_M4_MASK = 10022 + + PseudoVRSUB_VX_M8 = 10023 + + PseudoVRSUB_VX_M8_MASK = 10024 + + PseudoVRSUB_VX_MF2 = 10025 + + PseudoVRSUB_VX_MF2_MASK = 10026 + + PseudoVRSUB_VX_MF4 = 10027 + + PseudoVRSUB_VX_MF4_MASK = 10028 + + PseudoVRSUB_VX_MF8 = 10029 + + PseudoVRSUB_VX_MF8_MASK = 10030 + + PseudoVSADDU_VI_M1 = 10031 + + PseudoVSADDU_VI_M1_MASK = 10032 + + PseudoVSADDU_VI_M2 = 10033 + + PseudoVSADDU_VI_M2_MASK = 10034 + + PseudoVSADDU_VI_M4 = 10035 + + PseudoVSADDU_VI_M4_MASK = 10036 + + PseudoVSADDU_VI_M8 = 10037 + + PseudoVSADDU_VI_M8_MASK = 10038 + + PseudoVSADDU_VI_MF2 = 10039 + + PseudoVSADDU_VI_MF2_MASK = 10040 + + PseudoVSADDU_VI_MF4 = 10041 + + PseudoVSADDU_VI_MF4_MASK = 10042 + + PseudoVSADDU_VI_MF8 = 10043 + + PseudoVSADDU_VI_MF8_MASK = 10044 + + PseudoVSADDU_VV_M1 = 10045 + + PseudoVSADDU_VV_M1_MASK = 10046 + + PseudoVSADDU_VV_M2 = 10047 + + PseudoVSADDU_VV_M2_MASK = 10048 + + PseudoVSADDU_VV_M4 = 10049 + + PseudoVSADDU_VV_M4_MASK = 10050 + + PseudoVSADDU_VV_M8 = 10051 + + PseudoVSADDU_VV_M8_MASK = 10052 + + PseudoVSADDU_VV_MF2 = 10053 + + PseudoVSADDU_VV_MF2_MASK = 10054 + + PseudoVSADDU_VV_MF4 = 10055 + + PseudoVSADDU_VV_MF4_MASK = 10056 + + PseudoVSADDU_VV_MF8 = 10057 + + PseudoVSADDU_VV_MF8_MASK = 10058 + + PseudoVSADDU_VX_M1 = 10059 + + PseudoVSADDU_VX_M1_MASK = 10060 + + PseudoVSADDU_VX_M2 = 10061 + + PseudoVSADDU_VX_M2_MASK = 10062 + + PseudoVSADDU_VX_M4 = 10063 + + PseudoVSADDU_VX_M4_MASK = 10064 + + PseudoVSADDU_VX_M8 = 10065 + + PseudoVSADDU_VX_M8_MASK = 10066 + + PseudoVSADDU_VX_MF2 = 10067 + + PseudoVSADDU_VX_MF2_MASK = 10068 + + PseudoVSADDU_VX_MF4 = 10069 + + PseudoVSADDU_VX_MF4_MASK = 10070 + + PseudoVSADDU_VX_MF8 = 10071 + + PseudoVSADDU_VX_MF8_MASK = 10072 + + PseudoVSADD_VI_M1 = 10073 + + PseudoVSADD_VI_M1_MASK = 10074 + + PseudoVSADD_VI_M2 = 10075 + + PseudoVSADD_VI_M2_MASK = 10076 + + PseudoVSADD_VI_M4 = 10077 + + PseudoVSADD_VI_M4_MASK = 10078 + + PseudoVSADD_VI_M8 = 10079 + + PseudoVSADD_VI_M8_MASK = 10080 + + PseudoVSADD_VI_MF2 = 10081 + + PseudoVSADD_VI_MF2_MASK = 10082 + + PseudoVSADD_VI_MF4 = 10083 + + PseudoVSADD_VI_MF4_MASK = 10084 + + PseudoVSADD_VI_MF8 = 10085 + + PseudoVSADD_VI_MF8_MASK = 10086 + + PseudoVSADD_VV_M1 = 10087 + + PseudoVSADD_VV_M1_MASK = 10088 + + PseudoVSADD_VV_M2 = 10089 + + PseudoVSADD_VV_M2_MASK = 10090 + + PseudoVSADD_VV_M4 = 10091 + + PseudoVSADD_VV_M4_MASK = 10092 + + PseudoVSADD_VV_M8 = 10093 + + PseudoVSADD_VV_M8_MASK = 10094 + + PseudoVSADD_VV_MF2 = 10095 + + PseudoVSADD_VV_MF2_MASK = 10096 + + PseudoVSADD_VV_MF4 = 10097 + + PseudoVSADD_VV_MF4_MASK = 10098 + + PseudoVSADD_VV_MF8 = 10099 + + PseudoVSADD_VV_MF8_MASK = 10100 + + PseudoVSADD_VX_M1 = 10101 + + PseudoVSADD_VX_M1_MASK = 10102 + + PseudoVSADD_VX_M2 = 10103 + + PseudoVSADD_VX_M2_MASK = 10104 + + PseudoVSADD_VX_M4 = 10105 + + PseudoVSADD_VX_M4_MASK = 10106 + + PseudoVSADD_VX_M8 = 10107 + + PseudoVSADD_VX_M8_MASK = 10108 + + PseudoVSADD_VX_MF2 = 10109 + + PseudoVSADD_VX_MF2_MASK = 10110 + + PseudoVSADD_VX_MF4 = 10111 + + PseudoVSADD_VX_MF4_MASK = 10112 + + PseudoVSADD_VX_MF8 = 10113 + + PseudoVSADD_VX_MF8_MASK = 10114 + + PseudoVSBC_VVM_M1 = 10115 + + PseudoVSBC_VVM_M2 = 10116 + + PseudoVSBC_VVM_M4 = 10117 + + PseudoVSBC_VVM_M8 = 10118 + + PseudoVSBC_VVM_MF2 = 10119 + + PseudoVSBC_VVM_MF4 = 10120 + + PseudoVSBC_VVM_MF8 = 10121 + + PseudoVSBC_VXM_M1 = 10122 + + PseudoVSBC_VXM_M2 = 10123 + + PseudoVSBC_VXM_M4 = 10124 + + PseudoVSBC_VXM_M8 = 10125 + + PseudoVSBC_VXM_MF2 = 10126 + + PseudoVSBC_VXM_MF4 = 10127 + + PseudoVSBC_VXM_MF8 = 10128 + + PseudoVSE16_V_M1 = 10129 + + PseudoVSE16_V_M1_MASK = 10130 + + PseudoVSE16_V_M2 = 10131 + + PseudoVSE16_V_M2_MASK = 10132 + + PseudoVSE16_V_M4 = 10133 + + PseudoVSE16_V_M4_MASK = 10134 + + PseudoVSE16_V_M8 = 10135 + + PseudoVSE16_V_M8_MASK = 10136 + + PseudoVSE16_V_MF2 = 10137 + + PseudoVSE16_V_MF2_MASK = 10138 + + PseudoVSE16_V_MF4 = 10139 + + PseudoVSE16_V_MF4_MASK = 10140 + + PseudoVSE32_V_M1 = 10141 + + PseudoVSE32_V_M1_MASK = 10142 + + PseudoVSE32_V_M2 = 10143 + + PseudoVSE32_V_M2_MASK = 10144 + + PseudoVSE32_V_M4 = 10145 + + PseudoVSE32_V_M4_MASK = 10146 + + PseudoVSE32_V_M8 = 10147 + + PseudoVSE32_V_M8_MASK = 10148 + + PseudoVSE32_V_MF2 = 10149 + + PseudoVSE32_V_MF2_MASK = 10150 + + PseudoVSE64_V_M1 = 10151 + + PseudoVSE64_V_M1_MASK = 10152 + + PseudoVSE64_V_M2 = 10153 + + PseudoVSE64_V_M2_MASK = 10154 + + PseudoVSE64_V_M4 = 10155 + + PseudoVSE64_V_M4_MASK = 10156 + + PseudoVSE64_V_M8 = 10157 + + PseudoVSE64_V_M8_MASK = 10158 + + PseudoVSE8_V_M1 = 10159 + + PseudoVSE8_V_M1_MASK = 10160 + + PseudoVSE8_V_M2 = 10161 + + PseudoVSE8_V_M2_MASK = 10162 + + PseudoVSE8_V_M4 = 10163 + + PseudoVSE8_V_M4_MASK = 10164 + + PseudoVSE8_V_M8 = 10165 + + PseudoVSE8_V_M8_MASK = 10166 + + PseudoVSE8_V_MF2 = 10167 + + PseudoVSE8_V_MF2_MASK = 10168 + + PseudoVSE8_V_MF4 = 10169 + + PseudoVSE8_V_MF4_MASK = 10170 + + PseudoVSE8_V_MF8 = 10171 + + PseudoVSE8_V_MF8_MASK = 10172 + + PseudoVSETIVLI = 10173 + + PseudoVSETVLI = 10174 + + PseudoVSETVLIX0 = 10175 + + PseudoVSETVLIX0X0 = 10176 + + PseudoVSEXT_VF2_M1 = 10177 + + PseudoVSEXT_VF2_M1_MASK = 10178 + + PseudoVSEXT_VF2_M2 = 10179 + + PseudoVSEXT_VF2_M2_MASK = 10180 + + PseudoVSEXT_VF2_M4 = 10181 + + PseudoVSEXT_VF2_M4_MASK = 10182 + + PseudoVSEXT_VF2_M8 = 10183 + + PseudoVSEXT_VF2_M8_MASK = 10184 + + PseudoVSEXT_VF2_MF2 = 10185 + + PseudoVSEXT_VF2_MF2_MASK = 10186 + + PseudoVSEXT_VF2_MF4 = 10187 + + PseudoVSEXT_VF2_MF4_MASK = 10188 + + PseudoVSEXT_VF4_M1 = 10189 + + PseudoVSEXT_VF4_M1_MASK = 10190 + + PseudoVSEXT_VF4_M2 = 10191 + + PseudoVSEXT_VF4_M2_MASK = 10192 + + PseudoVSEXT_VF4_M4 = 10193 + + PseudoVSEXT_VF4_M4_MASK = 10194 + + PseudoVSEXT_VF4_M8 = 10195 + + PseudoVSEXT_VF4_M8_MASK = 10196 + + PseudoVSEXT_VF4_MF2 = 10197 + + PseudoVSEXT_VF4_MF2_MASK = 10198 + + PseudoVSEXT_VF8_M1 = 10199 + + PseudoVSEXT_VF8_M1_MASK = 10200 + + PseudoVSEXT_VF8_M2 = 10201 + + PseudoVSEXT_VF8_M2_MASK = 10202 + + PseudoVSEXT_VF8_M4 = 10203 + + PseudoVSEXT_VF8_M4_MASK = 10204 + + PseudoVSEXT_VF8_M8 = 10205 + + PseudoVSEXT_VF8_M8_MASK = 10206 + + PseudoVSHA2CH_VV_M1 = 10207 + + PseudoVSHA2CH_VV_M2 = 10208 + + PseudoVSHA2CH_VV_M4 = 10209 + + PseudoVSHA2CH_VV_M8 = 10210 + + PseudoVSHA2CH_VV_MF2 = 10211 + + PseudoVSHA2CL_VV_M1 = 10212 + + PseudoVSHA2CL_VV_M2 = 10213 + + PseudoVSHA2CL_VV_M4 = 10214 + + PseudoVSHA2CL_VV_M8 = 10215 + + PseudoVSHA2CL_VV_MF2 = 10216 + + PseudoVSHA2MS_VV_M1_E32 = 10217 + + PseudoVSHA2MS_VV_M1_E64 = 10218 + + PseudoVSHA2MS_VV_M2_E32 = 10219 + + PseudoVSHA2MS_VV_M2_E64 = 10220 + + PseudoVSHA2MS_VV_M4_E32 = 10221 + + PseudoVSHA2MS_VV_M4_E64 = 10222 + + PseudoVSHA2MS_VV_M8_E32 = 10223 + + PseudoVSHA2MS_VV_M8_E64 = 10224 + + PseudoVSHA2MS_VV_MF2_E32 = 10225 + + PseudoVSLIDE1DOWN_VX_M1 = 10226 + + PseudoVSLIDE1DOWN_VX_M1_MASK = 10227 + + PseudoVSLIDE1DOWN_VX_M2 = 10228 + + PseudoVSLIDE1DOWN_VX_M2_MASK = 10229 + + PseudoVSLIDE1DOWN_VX_M4 = 10230 + + PseudoVSLIDE1DOWN_VX_M4_MASK = 10231 + + PseudoVSLIDE1DOWN_VX_M8 = 10232 + + PseudoVSLIDE1DOWN_VX_M8_MASK = 10233 + + PseudoVSLIDE1DOWN_VX_MF2 = 10234 + + PseudoVSLIDE1DOWN_VX_MF2_MASK = 10235 + + PseudoVSLIDE1DOWN_VX_MF4 = 10236 + + PseudoVSLIDE1DOWN_VX_MF4_MASK = 10237 + + PseudoVSLIDE1DOWN_VX_MF8 = 10238 + + PseudoVSLIDE1DOWN_VX_MF8_MASK = 10239 + + PseudoVSLIDE1UP_VX_M1 = 10240 + + PseudoVSLIDE1UP_VX_M1_MASK = 10241 + + PseudoVSLIDE1UP_VX_M2 = 10242 + + PseudoVSLIDE1UP_VX_M2_MASK = 10243 + + PseudoVSLIDE1UP_VX_M4 = 10244 + + PseudoVSLIDE1UP_VX_M4_MASK = 10245 + + PseudoVSLIDE1UP_VX_M8 = 10246 + + PseudoVSLIDE1UP_VX_M8_MASK = 10247 + + PseudoVSLIDE1UP_VX_MF2 = 10248 + + PseudoVSLIDE1UP_VX_MF2_MASK = 10249 + + PseudoVSLIDE1UP_VX_MF4 = 10250 + + PseudoVSLIDE1UP_VX_MF4_MASK = 10251 + + PseudoVSLIDE1UP_VX_MF8 = 10252 + + PseudoVSLIDE1UP_VX_MF8_MASK = 10253 + + PseudoVSLIDEDOWN_VI_M1 = 10254 + + PseudoVSLIDEDOWN_VI_M1_MASK = 10255 + + PseudoVSLIDEDOWN_VI_M2 = 10256 + + PseudoVSLIDEDOWN_VI_M2_MASK = 10257 + + PseudoVSLIDEDOWN_VI_M4 = 10258 + + PseudoVSLIDEDOWN_VI_M4_MASK = 10259 + + PseudoVSLIDEDOWN_VI_M8 = 10260 + + PseudoVSLIDEDOWN_VI_M8_MASK = 10261 + + PseudoVSLIDEDOWN_VI_MF2 = 10262 + + PseudoVSLIDEDOWN_VI_MF2_MASK = 10263 + + PseudoVSLIDEDOWN_VI_MF4 = 10264 + + PseudoVSLIDEDOWN_VI_MF4_MASK = 10265 + + PseudoVSLIDEDOWN_VI_MF8 = 10266 + + PseudoVSLIDEDOWN_VI_MF8_MASK = 10267 + + PseudoVSLIDEDOWN_VX_M1 = 10268 + + PseudoVSLIDEDOWN_VX_M1_MASK = 10269 + + PseudoVSLIDEDOWN_VX_M2 = 10270 + + PseudoVSLIDEDOWN_VX_M2_MASK = 10271 + + PseudoVSLIDEDOWN_VX_M4 = 10272 + + PseudoVSLIDEDOWN_VX_M4_MASK = 10273 + + PseudoVSLIDEDOWN_VX_M8 = 10274 + + PseudoVSLIDEDOWN_VX_M8_MASK = 10275 + + PseudoVSLIDEDOWN_VX_MF2 = 10276 + + PseudoVSLIDEDOWN_VX_MF2_MASK = 10277 + + PseudoVSLIDEDOWN_VX_MF4 = 10278 + + PseudoVSLIDEDOWN_VX_MF4_MASK = 10279 + + PseudoVSLIDEDOWN_VX_MF8 = 10280 + + PseudoVSLIDEDOWN_VX_MF8_MASK = 10281 + + PseudoVSLIDEUP_VI_M1 = 10282 + + PseudoVSLIDEUP_VI_M1_MASK = 10283 + + PseudoVSLIDEUP_VI_M2 = 10284 + + PseudoVSLIDEUP_VI_M2_MASK = 10285 + + PseudoVSLIDEUP_VI_M4 = 10286 + + PseudoVSLIDEUP_VI_M4_MASK = 10287 + + PseudoVSLIDEUP_VI_M8 = 10288 + + PseudoVSLIDEUP_VI_M8_MASK = 10289 + + PseudoVSLIDEUP_VI_MF2 = 10290 + + PseudoVSLIDEUP_VI_MF2_MASK = 10291 + + PseudoVSLIDEUP_VI_MF4 = 10292 + + PseudoVSLIDEUP_VI_MF4_MASK = 10293 + + PseudoVSLIDEUP_VI_MF8 = 10294 + + PseudoVSLIDEUP_VI_MF8_MASK = 10295 + + PseudoVSLIDEUP_VX_M1 = 10296 + + PseudoVSLIDEUP_VX_M1_MASK = 10297 + + PseudoVSLIDEUP_VX_M2 = 10298 + + PseudoVSLIDEUP_VX_M2_MASK = 10299 + + PseudoVSLIDEUP_VX_M4 = 10300 + + PseudoVSLIDEUP_VX_M4_MASK = 10301 + + PseudoVSLIDEUP_VX_M8 = 10302 + + PseudoVSLIDEUP_VX_M8_MASK = 10303 + + PseudoVSLIDEUP_VX_MF2 = 10304 + + PseudoVSLIDEUP_VX_MF2_MASK = 10305 + + PseudoVSLIDEUP_VX_MF4 = 10306 + + PseudoVSLIDEUP_VX_MF4_MASK = 10307 + + PseudoVSLIDEUP_VX_MF8 = 10308 + + PseudoVSLIDEUP_VX_MF8_MASK = 10309 + + PseudoVSLL_VI_M1 = 10310 + + PseudoVSLL_VI_M1_MASK = 10311 + + PseudoVSLL_VI_M2 = 10312 + + PseudoVSLL_VI_M2_MASK = 10313 + + PseudoVSLL_VI_M4 = 10314 + + PseudoVSLL_VI_M4_MASK = 10315 + + PseudoVSLL_VI_M8 = 10316 + + PseudoVSLL_VI_M8_MASK = 10317 + + PseudoVSLL_VI_MF2 = 10318 + + PseudoVSLL_VI_MF2_MASK = 10319 + + PseudoVSLL_VI_MF4 = 10320 + + PseudoVSLL_VI_MF4_MASK = 10321 + + PseudoVSLL_VI_MF8 = 10322 + + PseudoVSLL_VI_MF8_MASK = 10323 + + PseudoVSLL_VV_M1 = 10324 + + PseudoVSLL_VV_M1_MASK = 10325 + + PseudoVSLL_VV_M2 = 10326 + + PseudoVSLL_VV_M2_MASK = 10327 + + PseudoVSLL_VV_M4 = 10328 + + PseudoVSLL_VV_M4_MASK = 10329 + + PseudoVSLL_VV_M8 = 10330 + + PseudoVSLL_VV_M8_MASK = 10331 + + PseudoVSLL_VV_MF2 = 10332 + + PseudoVSLL_VV_MF2_MASK = 10333 + + PseudoVSLL_VV_MF4 = 10334 + + PseudoVSLL_VV_MF4_MASK = 10335 + + PseudoVSLL_VV_MF8 = 10336 + + PseudoVSLL_VV_MF8_MASK = 10337 + + PseudoVSLL_VX_M1 = 10338 + + PseudoVSLL_VX_M1_MASK = 10339 + + PseudoVSLL_VX_M2 = 10340 + + PseudoVSLL_VX_M2_MASK = 10341 + + PseudoVSLL_VX_M4 = 10342 + + PseudoVSLL_VX_M4_MASK = 10343 + + PseudoVSLL_VX_M8 = 10344 + + PseudoVSLL_VX_M8_MASK = 10345 + + PseudoVSLL_VX_MF2 = 10346 + + PseudoVSLL_VX_MF2_MASK = 10347 + + PseudoVSLL_VX_MF4 = 10348 + + PseudoVSLL_VX_MF4_MASK = 10349 + + PseudoVSLL_VX_MF8 = 10350 + + PseudoVSLL_VX_MF8_MASK = 10351 + + PseudoVSM3C_VI_M1 = 10352 + + PseudoVSM3C_VI_M2 = 10353 + + PseudoVSM3C_VI_M4 = 10354 + + PseudoVSM3C_VI_M8 = 10355 + + PseudoVSM3C_VI_MF2 = 10356 + + PseudoVSM3ME_VV_M1 = 10357 + + PseudoVSM3ME_VV_M2 = 10358 + + PseudoVSM3ME_VV_M4 = 10359 + + PseudoVSM3ME_VV_M8 = 10360 + + PseudoVSM3ME_VV_MF2 = 10361 + + PseudoVSM4K_VI_M1 = 10362 + + PseudoVSM4K_VI_M2 = 10363 + + PseudoVSM4K_VI_M4 = 10364 + + PseudoVSM4K_VI_M8 = 10365 + + PseudoVSM4K_VI_MF2 = 10366 + + PseudoVSM4R_VS_M1_M1 = 10367 + + PseudoVSM4R_VS_M1_MF2 = 10368 + + PseudoVSM4R_VS_M1_MF4 = 10369 + + PseudoVSM4R_VS_M1_MF8 = 10370 + + PseudoVSM4R_VS_M2_M1 = 10371 + + PseudoVSM4R_VS_M2_M2 = 10372 + + PseudoVSM4R_VS_M2_MF2 = 10373 + + PseudoVSM4R_VS_M2_MF4 = 10374 + + PseudoVSM4R_VS_M2_MF8 = 10375 + + PseudoVSM4R_VS_M4_M1 = 10376 + + PseudoVSM4R_VS_M4_M2 = 10377 + + PseudoVSM4R_VS_M4_M4 = 10378 + + PseudoVSM4R_VS_M4_MF2 = 10379 + + PseudoVSM4R_VS_M4_MF4 = 10380 + + PseudoVSM4R_VS_M4_MF8 = 10381 + + PseudoVSM4R_VS_M8_M1 = 10382 + + PseudoVSM4R_VS_M8_M2 = 10383 + + PseudoVSM4R_VS_M8_M4 = 10384 + + PseudoVSM4R_VS_M8_MF2 = 10385 + + PseudoVSM4R_VS_M8_MF4 = 10386 + + PseudoVSM4R_VS_M8_MF8 = 10387 + + PseudoVSM4R_VS_MF2_MF2 = 10388 + + PseudoVSM4R_VS_MF2_MF4 = 10389 + + PseudoVSM4R_VS_MF2_MF8 = 10390 + + PseudoVSM4R_VV_M1 = 10391 + + PseudoVSM4R_VV_M2 = 10392 + + PseudoVSM4R_VV_M4 = 10393 + + PseudoVSM4R_VV_M8 = 10394 + + PseudoVSM4R_VV_MF2 = 10395 + + PseudoVSMUL_VV_M1 = 10396 + + PseudoVSMUL_VV_M1_MASK = 10397 + + PseudoVSMUL_VV_M2 = 10398 + + PseudoVSMUL_VV_M2_MASK = 10399 + + PseudoVSMUL_VV_M4 = 10400 + + PseudoVSMUL_VV_M4_MASK = 10401 + + PseudoVSMUL_VV_M8 = 10402 + + PseudoVSMUL_VV_M8_MASK = 10403 + + PseudoVSMUL_VV_MF2 = 10404 + + PseudoVSMUL_VV_MF2_MASK = 10405 + + PseudoVSMUL_VV_MF4 = 10406 + + PseudoVSMUL_VV_MF4_MASK = 10407 + + PseudoVSMUL_VV_MF8 = 10408 + + PseudoVSMUL_VV_MF8_MASK = 10409 + + PseudoVSMUL_VX_M1 = 10410 + + PseudoVSMUL_VX_M1_MASK = 10411 + + PseudoVSMUL_VX_M2 = 10412 + + PseudoVSMUL_VX_M2_MASK = 10413 + + PseudoVSMUL_VX_M4 = 10414 + + PseudoVSMUL_VX_M4_MASK = 10415 + + PseudoVSMUL_VX_M8 = 10416 + + PseudoVSMUL_VX_M8_MASK = 10417 + + PseudoVSMUL_VX_MF2 = 10418 + + PseudoVSMUL_VX_MF2_MASK = 10419 + + PseudoVSMUL_VX_MF4 = 10420 + + PseudoVSMUL_VX_MF4_MASK = 10421 + + PseudoVSMUL_VX_MF8 = 10422 + + PseudoVSMUL_VX_MF8_MASK = 10423 + + PseudoVSM_V_B1 = 10424 + + PseudoVSM_V_B16 = 10425 + + PseudoVSM_V_B2 = 10426 + + PseudoVSM_V_B32 = 10427 + + PseudoVSM_V_B4 = 10428 + + PseudoVSM_V_B64 = 10429 + + PseudoVSM_V_B8 = 10430 + + PseudoVSOXEI16_V_M1_M1 = 10431 + + PseudoVSOXEI16_V_M1_M1_MASK = 10432 + + PseudoVSOXEI16_V_M1_M2 = 10433 + + PseudoVSOXEI16_V_M1_M2_MASK = 10434 + + PseudoVSOXEI16_V_M1_M4 = 10435 + + PseudoVSOXEI16_V_M1_M4_MASK = 10436 + + PseudoVSOXEI16_V_M1_MF2 = 10437 + + PseudoVSOXEI16_V_M1_MF2_MASK = 10438 + + PseudoVSOXEI16_V_M2_M1 = 10439 + + PseudoVSOXEI16_V_M2_M1_MASK = 10440 + + PseudoVSOXEI16_V_M2_M2 = 10441 + + PseudoVSOXEI16_V_M2_M2_MASK = 10442 + + PseudoVSOXEI16_V_M2_M4 = 10443 + + PseudoVSOXEI16_V_M2_M4_MASK = 10444 + + PseudoVSOXEI16_V_M2_M8 = 10445 + + PseudoVSOXEI16_V_M2_M8_MASK = 10446 + + PseudoVSOXEI16_V_M4_M2 = 10447 + + PseudoVSOXEI16_V_M4_M2_MASK = 10448 + + PseudoVSOXEI16_V_M4_M4 = 10449 + + PseudoVSOXEI16_V_M4_M4_MASK = 10450 + + PseudoVSOXEI16_V_M4_M8 = 10451 + + PseudoVSOXEI16_V_M4_M8_MASK = 10452 + + PseudoVSOXEI16_V_M8_M4 = 10453 + + PseudoVSOXEI16_V_M8_M4_MASK = 10454 + + PseudoVSOXEI16_V_M8_M8 = 10455 + + PseudoVSOXEI16_V_M8_M8_MASK = 10456 + + PseudoVSOXEI16_V_MF2_M1 = 10457 + + PseudoVSOXEI16_V_MF2_M1_MASK = 10458 + + PseudoVSOXEI16_V_MF2_M2 = 10459 + + PseudoVSOXEI16_V_MF2_M2_MASK = 10460 + + PseudoVSOXEI16_V_MF2_MF2 = 10461 + + PseudoVSOXEI16_V_MF2_MF2_MASK = 10462 + + PseudoVSOXEI16_V_MF2_MF4 = 10463 + + PseudoVSOXEI16_V_MF2_MF4_MASK = 10464 + + PseudoVSOXEI16_V_MF4_M1 = 10465 + + PseudoVSOXEI16_V_MF4_M1_MASK = 10466 + + PseudoVSOXEI16_V_MF4_MF2 = 10467 + + PseudoVSOXEI16_V_MF4_MF2_MASK = 10468 + + PseudoVSOXEI16_V_MF4_MF4 = 10469 + + PseudoVSOXEI16_V_MF4_MF4_MASK = 10470 + + PseudoVSOXEI16_V_MF4_MF8 = 10471 + + PseudoVSOXEI16_V_MF4_MF8_MASK = 10472 + + PseudoVSOXEI32_V_M1_M1 = 10473 + + PseudoVSOXEI32_V_M1_M1_MASK = 10474 + + PseudoVSOXEI32_V_M1_M2 = 10475 + + PseudoVSOXEI32_V_M1_M2_MASK = 10476 + + PseudoVSOXEI32_V_M1_MF2 = 10477 + + PseudoVSOXEI32_V_M1_MF2_MASK = 10478 + + PseudoVSOXEI32_V_M1_MF4 = 10479 + + PseudoVSOXEI32_V_M1_MF4_MASK = 10480 + + PseudoVSOXEI32_V_M2_M1 = 10481 + + PseudoVSOXEI32_V_M2_M1_MASK = 10482 + + PseudoVSOXEI32_V_M2_M2 = 10483 + + PseudoVSOXEI32_V_M2_M2_MASK = 10484 + + PseudoVSOXEI32_V_M2_M4 = 10485 + + PseudoVSOXEI32_V_M2_M4_MASK = 10486 + + PseudoVSOXEI32_V_M2_MF2 = 10487 + + PseudoVSOXEI32_V_M2_MF2_MASK = 10488 + + PseudoVSOXEI32_V_M4_M1 = 10489 + + PseudoVSOXEI32_V_M4_M1_MASK = 10490 + + PseudoVSOXEI32_V_M4_M2 = 10491 + + PseudoVSOXEI32_V_M4_M2_MASK = 10492 + + PseudoVSOXEI32_V_M4_M4 = 10493 + + PseudoVSOXEI32_V_M4_M4_MASK = 10494 + + PseudoVSOXEI32_V_M4_M8 = 10495 + + PseudoVSOXEI32_V_M4_M8_MASK = 10496 + + PseudoVSOXEI32_V_M8_M2 = 10497 + + PseudoVSOXEI32_V_M8_M2_MASK = 10498 + + PseudoVSOXEI32_V_M8_M4 = 10499 + + PseudoVSOXEI32_V_M8_M4_MASK = 10500 + + PseudoVSOXEI32_V_M8_M8 = 10501 + + PseudoVSOXEI32_V_M8_M8_MASK = 10502 + + PseudoVSOXEI32_V_MF2_M1 = 10503 + + PseudoVSOXEI32_V_MF2_M1_MASK = 10504 + + PseudoVSOXEI32_V_MF2_MF2 = 10505 + + PseudoVSOXEI32_V_MF2_MF2_MASK = 10506 + + PseudoVSOXEI32_V_MF2_MF4 = 10507 + + PseudoVSOXEI32_V_MF2_MF4_MASK = 10508 + + PseudoVSOXEI32_V_MF2_MF8 = 10509 + + PseudoVSOXEI32_V_MF2_MF8_MASK = 10510 + + PseudoVSOXEI64_V_M1_M1 = 10511 + + PseudoVSOXEI64_V_M1_M1_MASK = 10512 + + PseudoVSOXEI64_V_M1_MF2 = 10513 + + PseudoVSOXEI64_V_M1_MF2_MASK = 10514 + + PseudoVSOXEI64_V_M1_MF4 = 10515 + + PseudoVSOXEI64_V_M1_MF4_MASK = 10516 + + PseudoVSOXEI64_V_M1_MF8 = 10517 + + PseudoVSOXEI64_V_M1_MF8_MASK = 10518 + + PseudoVSOXEI64_V_M2_M1 = 10519 + + PseudoVSOXEI64_V_M2_M1_MASK = 10520 + + PseudoVSOXEI64_V_M2_M2 = 10521 + + PseudoVSOXEI64_V_M2_M2_MASK = 10522 + + PseudoVSOXEI64_V_M2_MF2 = 10523 + + PseudoVSOXEI64_V_M2_MF2_MASK = 10524 + + PseudoVSOXEI64_V_M2_MF4 = 10525 + + PseudoVSOXEI64_V_M2_MF4_MASK = 10526 + + PseudoVSOXEI64_V_M4_M1 = 10527 + + PseudoVSOXEI64_V_M4_M1_MASK = 10528 + + PseudoVSOXEI64_V_M4_M2 = 10529 + + PseudoVSOXEI64_V_M4_M2_MASK = 10530 + + PseudoVSOXEI64_V_M4_M4 = 10531 + + PseudoVSOXEI64_V_M4_M4_MASK = 10532 + + PseudoVSOXEI64_V_M4_MF2 = 10533 + + PseudoVSOXEI64_V_M4_MF2_MASK = 10534 + + PseudoVSOXEI64_V_M8_M1 = 10535 + + PseudoVSOXEI64_V_M8_M1_MASK = 10536 + + PseudoVSOXEI64_V_M8_M2 = 10537 + + PseudoVSOXEI64_V_M8_M2_MASK = 10538 + + PseudoVSOXEI64_V_M8_M4 = 10539 + + PseudoVSOXEI64_V_M8_M4_MASK = 10540 + + PseudoVSOXEI64_V_M8_M8 = 10541 + + PseudoVSOXEI64_V_M8_M8_MASK = 10542 + + PseudoVSOXEI8_V_M1_M1 = 10543 + + PseudoVSOXEI8_V_M1_M1_MASK = 10544 + + PseudoVSOXEI8_V_M1_M2 = 10545 + + PseudoVSOXEI8_V_M1_M2_MASK = 10546 + + PseudoVSOXEI8_V_M1_M4 = 10547 + + PseudoVSOXEI8_V_M1_M4_MASK = 10548 + + PseudoVSOXEI8_V_M1_M8 = 10549 + + PseudoVSOXEI8_V_M1_M8_MASK = 10550 + + PseudoVSOXEI8_V_M2_M2 = 10551 + + PseudoVSOXEI8_V_M2_M2_MASK = 10552 + + PseudoVSOXEI8_V_M2_M4 = 10553 + + PseudoVSOXEI8_V_M2_M4_MASK = 10554 + + PseudoVSOXEI8_V_M2_M8 = 10555 + + PseudoVSOXEI8_V_M2_M8_MASK = 10556 + + PseudoVSOXEI8_V_M4_M4 = 10557 + + PseudoVSOXEI8_V_M4_M4_MASK = 10558 + + PseudoVSOXEI8_V_M4_M8 = 10559 + + PseudoVSOXEI8_V_M4_M8_MASK = 10560 + + PseudoVSOXEI8_V_M8_M8 = 10561 + + PseudoVSOXEI8_V_M8_M8_MASK = 10562 + + PseudoVSOXEI8_V_MF2_M1 = 10563 + + PseudoVSOXEI8_V_MF2_M1_MASK = 10564 + + PseudoVSOXEI8_V_MF2_M2 = 10565 + + PseudoVSOXEI8_V_MF2_M2_MASK = 10566 + + PseudoVSOXEI8_V_MF2_M4 = 10567 + + PseudoVSOXEI8_V_MF2_M4_MASK = 10568 + + PseudoVSOXEI8_V_MF2_MF2 = 10569 + + PseudoVSOXEI8_V_MF2_MF2_MASK = 10570 + + PseudoVSOXEI8_V_MF4_M1 = 10571 + + PseudoVSOXEI8_V_MF4_M1_MASK = 10572 + + PseudoVSOXEI8_V_MF4_M2 = 10573 + + PseudoVSOXEI8_V_MF4_M2_MASK = 10574 + + PseudoVSOXEI8_V_MF4_MF2 = 10575 + + PseudoVSOXEI8_V_MF4_MF2_MASK = 10576 + + PseudoVSOXEI8_V_MF4_MF4 = 10577 + + PseudoVSOXEI8_V_MF4_MF4_MASK = 10578 + + PseudoVSOXEI8_V_MF8_M1 = 10579 + + PseudoVSOXEI8_V_MF8_M1_MASK = 10580 + + PseudoVSOXEI8_V_MF8_MF2 = 10581 + + PseudoVSOXEI8_V_MF8_MF2_MASK = 10582 + + PseudoVSOXEI8_V_MF8_MF4 = 10583 + + PseudoVSOXEI8_V_MF8_MF4_MASK = 10584 + + PseudoVSOXEI8_V_MF8_MF8 = 10585 + + PseudoVSOXEI8_V_MF8_MF8_MASK = 10586 + + PseudoVSOXSEG2EI16_V_M1_M1 = 10587 + + PseudoVSOXSEG2EI16_V_M1_M1_MASK = 10588 + + PseudoVSOXSEG2EI16_V_M1_M2 = 10589 + + PseudoVSOXSEG2EI16_V_M1_M2_MASK = 10590 + + PseudoVSOXSEG2EI16_V_M1_M4 = 10591 + + PseudoVSOXSEG2EI16_V_M1_M4_MASK = 10592 + + PseudoVSOXSEG2EI16_V_M1_MF2 = 10593 + + PseudoVSOXSEG2EI16_V_M1_MF2_MASK = 10594 + + PseudoVSOXSEG2EI16_V_M2_M1 = 10595 + + PseudoVSOXSEG2EI16_V_M2_M1_MASK = 10596 + + PseudoVSOXSEG2EI16_V_M2_M2 = 10597 + + PseudoVSOXSEG2EI16_V_M2_M2_MASK = 10598 + + PseudoVSOXSEG2EI16_V_M2_M4 = 10599 + + PseudoVSOXSEG2EI16_V_M2_M4_MASK = 10600 + + PseudoVSOXSEG2EI16_V_M4_M2 = 10601 + + PseudoVSOXSEG2EI16_V_M4_M2_MASK = 10602 + + PseudoVSOXSEG2EI16_V_M4_M4 = 10603 + + PseudoVSOXSEG2EI16_V_M4_M4_MASK = 10604 + + PseudoVSOXSEG2EI16_V_M8_M4 = 10605 + + PseudoVSOXSEG2EI16_V_M8_M4_MASK = 10606 + + PseudoVSOXSEG2EI16_V_MF2_M1 = 10607 + + PseudoVSOXSEG2EI16_V_MF2_M1_MASK = 10608 + + PseudoVSOXSEG2EI16_V_MF2_M2 = 10609 + + PseudoVSOXSEG2EI16_V_MF2_M2_MASK = 10610 + + PseudoVSOXSEG2EI16_V_MF2_MF2 = 10611 + + PseudoVSOXSEG2EI16_V_MF2_MF2_MASK = 10612 + + PseudoVSOXSEG2EI16_V_MF2_MF4 = 10613 + + PseudoVSOXSEG2EI16_V_MF2_MF4_MASK = 10614 + + PseudoVSOXSEG2EI16_V_MF4_M1 = 10615 + + PseudoVSOXSEG2EI16_V_MF4_M1_MASK = 10616 + + PseudoVSOXSEG2EI16_V_MF4_MF2 = 10617 + + PseudoVSOXSEG2EI16_V_MF4_MF2_MASK = 10618 + + PseudoVSOXSEG2EI16_V_MF4_MF4 = 10619 + + PseudoVSOXSEG2EI16_V_MF4_MF4_MASK = 10620 + + PseudoVSOXSEG2EI16_V_MF4_MF8 = 10621 + + PseudoVSOXSEG2EI16_V_MF4_MF8_MASK = 10622 + + PseudoVSOXSEG2EI32_V_M1_M1 = 10623 + + PseudoVSOXSEG2EI32_V_M1_M1_MASK = 10624 + + PseudoVSOXSEG2EI32_V_M1_M2 = 10625 + + PseudoVSOXSEG2EI32_V_M1_M2_MASK = 10626 + + PseudoVSOXSEG2EI32_V_M1_MF2 = 10627 + + PseudoVSOXSEG2EI32_V_M1_MF2_MASK = 10628 + + PseudoVSOXSEG2EI32_V_M1_MF4 = 10629 + + PseudoVSOXSEG2EI32_V_M1_MF4_MASK = 10630 + + PseudoVSOXSEG2EI32_V_M2_M1 = 10631 + + PseudoVSOXSEG2EI32_V_M2_M1_MASK = 10632 + + PseudoVSOXSEG2EI32_V_M2_M2 = 10633 + + PseudoVSOXSEG2EI32_V_M2_M2_MASK = 10634 + + PseudoVSOXSEG2EI32_V_M2_M4 = 10635 + + PseudoVSOXSEG2EI32_V_M2_M4_MASK = 10636 + + PseudoVSOXSEG2EI32_V_M2_MF2 = 10637 + + PseudoVSOXSEG2EI32_V_M2_MF2_MASK = 10638 + + PseudoVSOXSEG2EI32_V_M4_M1 = 10639 + + PseudoVSOXSEG2EI32_V_M4_M1_MASK = 10640 + + PseudoVSOXSEG2EI32_V_M4_M2 = 10641 + + PseudoVSOXSEG2EI32_V_M4_M2_MASK = 10642 + + PseudoVSOXSEG2EI32_V_M4_M4 = 10643 + + PseudoVSOXSEG2EI32_V_M4_M4_MASK = 10644 + + PseudoVSOXSEG2EI32_V_M8_M2 = 10645 + + PseudoVSOXSEG2EI32_V_M8_M2_MASK = 10646 + + PseudoVSOXSEG2EI32_V_M8_M4 = 10647 + + PseudoVSOXSEG2EI32_V_M8_M4_MASK = 10648 + + PseudoVSOXSEG2EI32_V_MF2_M1 = 10649 + + PseudoVSOXSEG2EI32_V_MF2_M1_MASK = 10650 + + PseudoVSOXSEG2EI32_V_MF2_MF2 = 10651 + + PseudoVSOXSEG2EI32_V_MF2_MF2_MASK = 10652 + + PseudoVSOXSEG2EI32_V_MF2_MF4 = 10653 + + PseudoVSOXSEG2EI32_V_MF2_MF4_MASK = 10654 + + PseudoVSOXSEG2EI32_V_MF2_MF8 = 10655 + + PseudoVSOXSEG2EI32_V_MF2_MF8_MASK = 10656 + + PseudoVSOXSEG2EI64_V_M1_M1 = 10657 + + PseudoVSOXSEG2EI64_V_M1_M1_MASK = 10658 + + PseudoVSOXSEG2EI64_V_M1_MF2 = 10659 + + PseudoVSOXSEG2EI64_V_M1_MF2_MASK = 10660 + + PseudoVSOXSEG2EI64_V_M1_MF4 = 10661 + + PseudoVSOXSEG2EI64_V_M1_MF4_MASK = 10662 + + PseudoVSOXSEG2EI64_V_M1_MF8 = 10663 + + PseudoVSOXSEG2EI64_V_M1_MF8_MASK = 10664 + + PseudoVSOXSEG2EI64_V_M2_M1 = 10665 + + PseudoVSOXSEG2EI64_V_M2_M1_MASK = 10666 + + PseudoVSOXSEG2EI64_V_M2_M2 = 10667 + + PseudoVSOXSEG2EI64_V_M2_M2_MASK = 10668 + + PseudoVSOXSEG2EI64_V_M2_MF2 = 10669 + + PseudoVSOXSEG2EI64_V_M2_MF2_MASK = 10670 + + PseudoVSOXSEG2EI64_V_M2_MF4 = 10671 + + PseudoVSOXSEG2EI64_V_M2_MF4_MASK = 10672 + + PseudoVSOXSEG2EI64_V_M4_M1 = 10673 + + PseudoVSOXSEG2EI64_V_M4_M1_MASK = 10674 + + PseudoVSOXSEG2EI64_V_M4_M2 = 10675 + + PseudoVSOXSEG2EI64_V_M4_M2_MASK = 10676 + + PseudoVSOXSEG2EI64_V_M4_M4 = 10677 + + PseudoVSOXSEG2EI64_V_M4_M4_MASK = 10678 + + PseudoVSOXSEG2EI64_V_M4_MF2 = 10679 + + PseudoVSOXSEG2EI64_V_M4_MF2_MASK = 10680 + + PseudoVSOXSEG2EI64_V_M8_M1 = 10681 + + PseudoVSOXSEG2EI64_V_M8_M1_MASK = 10682 + + PseudoVSOXSEG2EI64_V_M8_M2 = 10683 + + PseudoVSOXSEG2EI64_V_M8_M2_MASK = 10684 + + PseudoVSOXSEG2EI64_V_M8_M4 = 10685 + + PseudoVSOXSEG2EI64_V_M8_M4_MASK = 10686 + + PseudoVSOXSEG2EI8_V_M1_M1 = 10687 + + PseudoVSOXSEG2EI8_V_M1_M1_MASK = 10688 + + PseudoVSOXSEG2EI8_V_M1_M2 = 10689 + + PseudoVSOXSEG2EI8_V_M1_M2_MASK = 10690 + + PseudoVSOXSEG2EI8_V_M1_M4 = 10691 + + PseudoVSOXSEG2EI8_V_M1_M4_MASK = 10692 + + PseudoVSOXSEG2EI8_V_M2_M2 = 10693 + + PseudoVSOXSEG2EI8_V_M2_M2_MASK = 10694 + + PseudoVSOXSEG2EI8_V_M2_M4 = 10695 + + PseudoVSOXSEG2EI8_V_M2_M4_MASK = 10696 + + PseudoVSOXSEG2EI8_V_M4_M4 = 10697 + + PseudoVSOXSEG2EI8_V_M4_M4_MASK = 10698 + + PseudoVSOXSEG2EI8_V_MF2_M1 = 10699 + + PseudoVSOXSEG2EI8_V_MF2_M1_MASK = 10700 + + PseudoVSOXSEG2EI8_V_MF2_M2 = 10701 + + PseudoVSOXSEG2EI8_V_MF2_M2_MASK = 10702 + + PseudoVSOXSEG2EI8_V_MF2_M4 = 10703 + + PseudoVSOXSEG2EI8_V_MF2_M4_MASK = 10704 + + PseudoVSOXSEG2EI8_V_MF2_MF2 = 10705 + + PseudoVSOXSEG2EI8_V_MF2_MF2_MASK = 10706 + + PseudoVSOXSEG2EI8_V_MF4_M1 = 10707 + + PseudoVSOXSEG2EI8_V_MF4_M1_MASK = 10708 + + PseudoVSOXSEG2EI8_V_MF4_M2 = 10709 + + PseudoVSOXSEG2EI8_V_MF4_M2_MASK = 10710 + + PseudoVSOXSEG2EI8_V_MF4_MF2 = 10711 + + PseudoVSOXSEG2EI8_V_MF4_MF2_MASK = 10712 + + PseudoVSOXSEG2EI8_V_MF4_MF4 = 10713 + + PseudoVSOXSEG2EI8_V_MF4_MF4_MASK = 10714 + + PseudoVSOXSEG2EI8_V_MF8_M1 = 10715 + + PseudoVSOXSEG2EI8_V_MF8_M1_MASK = 10716 + + PseudoVSOXSEG2EI8_V_MF8_MF2 = 10717 + + PseudoVSOXSEG2EI8_V_MF8_MF2_MASK = 10718 + + PseudoVSOXSEG2EI8_V_MF8_MF4 = 10719 + + PseudoVSOXSEG2EI8_V_MF8_MF4_MASK = 10720 + + PseudoVSOXSEG2EI8_V_MF8_MF8 = 10721 + + PseudoVSOXSEG2EI8_V_MF8_MF8_MASK = 10722 + + PseudoVSOXSEG3EI16_V_M1_M1 = 10723 + + PseudoVSOXSEG3EI16_V_M1_M1_MASK = 10724 + + PseudoVSOXSEG3EI16_V_M1_M2 = 10725 + + PseudoVSOXSEG3EI16_V_M1_M2_MASK = 10726 + + PseudoVSOXSEG3EI16_V_M1_MF2 = 10727 + + PseudoVSOXSEG3EI16_V_M1_MF2_MASK = 10728 + + PseudoVSOXSEG3EI16_V_M2_M1 = 10729 + + PseudoVSOXSEG3EI16_V_M2_M1_MASK = 10730 + + PseudoVSOXSEG3EI16_V_M2_M2 = 10731 + + PseudoVSOXSEG3EI16_V_M2_M2_MASK = 10732 + + PseudoVSOXSEG3EI16_V_M4_M2 = 10733 + + PseudoVSOXSEG3EI16_V_M4_M2_MASK = 10734 + + PseudoVSOXSEG3EI16_V_MF2_M1 = 10735 + + PseudoVSOXSEG3EI16_V_MF2_M1_MASK = 10736 + + PseudoVSOXSEG3EI16_V_MF2_M2 = 10737 + + PseudoVSOXSEG3EI16_V_MF2_M2_MASK = 10738 + + PseudoVSOXSEG3EI16_V_MF2_MF2 = 10739 + + PseudoVSOXSEG3EI16_V_MF2_MF2_MASK = 10740 + + PseudoVSOXSEG3EI16_V_MF2_MF4 = 10741 + + PseudoVSOXSEG3EI16_V_MF2_MF4_MASK = 10742 + + PseudoVSOXSEG3EI16_V_MF4_M1 = 10743 + + PseudoVSOXSEG3EI16_V_MF4_M1_MASK = 10744 + + PseudoVSOXSEG3EI16_V_MF4_MF2 = 10745 + + PseudoVSOXSEG3EI16_V_MF4_MF2_MASK = 10746 + + PseudoVSOXSEG3EI16_V_MF4_MF4 = 10747 + + PseudoVSOXSEG3EI16_V_MF4_MF4_MASK = 10748 + + PseudoVSOXSEG3EI16_V_MF4_MF8 = 10749 + + PseudoVSOXSEG3EI16_V_MF4_MF8_MASK = 10750 + + PseudoVSOXSEG3EI32_V_M1_M1 = 10751 + + PseudoVSOXSEG3EI32_V_M1_M1_MASK = 10752 + + PseudoVSOXSEG3EI32_V_M1_M2 = 10753 + + PseudoVSOXSEG3EI32_V_M1_M2_MASK = 10754 + + PseudoVSOXSEG3EI32_V_M1_MF2 = 10755 + + PseudoVSOXSEG3EI32_V_M1_MF2_MASK = 10756 + + PseudoVSOXSEG3EI32_V_M1_MF4 = 10757 + + PseudoVSOXSEG3EI32_V_M1_MF4_MASK = 10758 + + PseudoVSOXSEG3EI32_V_M2_M1 = 10759 + + PseudoVSOXSEG3EI32_V_M2_M1_MASK = 10760 + + PseudoVSOXSEG3EI32_V_M2_M2 = 10761 + + PseudoVSOXSEG3EI32_V_M2_M2_MASK = 10762 + + PseudoVSOXSEG3EI32_V_M2_MF2 = 10763 + + PseudoVSOXSEG3EI32_V_M2_MF2_MASK = 10764 + + PseudoVSOXSEG3EI32_V_M4_M1 = 10765 + + PseudoVSOXSEG3EI32_V_M4_M1_MASK = 10766 + + PseudoVSOXSEG3EI32_V_M4_M2 = 10767 + + PseudoVSOXSEG3EI32_V_M4_M2_MASK = 10768 + + PseudoVSOXSEG3EI32_V_M8_M2 = 10769 + + PseudoVSOXSEG3EI32_V_M8_M2_MASK = 10770 + + PseudoVSOXSEG3EI32_V_MF2_M1 = 10771 + + PseudoVSOXSEG3EI32_V_MF2_M1_MASK = 10772 + + PseudoVSOXSEG3EI32_V_MF2_MF2 = 10773 + + PseudoVSOXSEG3EI32_V_MF2_MF2_MASK = 10774 + + PseudoVSOXSEG3EI32_V_MF2_MF4 = 10775 + + PseudoVSOXSEG3EI32_V_MF2_MF4_MASK = 10776 + + PseudoVSOXSEG3EI32_V_MF2_MF8 = 10777 + + PseudoVSOXSEG3EI32_V_MF2_MF8_MASK = 10778 + + PseudoVSOXSEG3EI64_V_M1_M1 = 10779 + + PseudoVSOXSEG3EI64_V_M1_M1_MASK = 10780 + + PseudoVSOXSEG3EI64_V_M1_MF2 = 10781 + + PseudoVSOXSEG3EI64_V_M1_MF2_MASK = 10782 + + PseudoVSOXSEG3EI64_V_M1_MF4 = 10783 + + PseudoVSOXSEG3EI64_V_M1_MF4_MASK = 10784 + + PseudoVSOXSEG3EI64_V_M1_MF8 = 10785 + + PseudoVSOXSEG3EI64_V_M1_MF8_MASK = 10786 + + PseudoVSOXSEG3EI64_V_M2_M1 = 10787 + + PseudoVSOXSEG3EI64_V_M2_M1_MASK = 10788 + + PseudoVSOXSEG3EI64_V_M2_M2 = 10789 + + PseudoVSOXSEG3EI64_V_M2_M2_MASK = 10790 + + PseudoVSOXSEG3EI64_V_M2_MF2 = 10791 + + PseudoVSOXSEG3EI64_V_M2_MF2_MASK = 10792 + + PseudoVSOXSEG3EI64_V_M2_MF4 = 10793 + + PseudoVSOXSEG3EI64_V_M2_MF4_MASK = 10794 + + PseudoVSOXSEG3EI64_V_M4_M1 = 10795 + + PseudoVSOXSEG3EI64_V_M4_M1_MASK = 10796 + + PseudoVSOXSEG3EI64_V_M4_M2 = 10797 + + PseudoVSOXSEG3EI64_V_M4_M2_MASK = 10798 + + PseudoVSOXSEG3EI64_V_M4_MF2 = 10799 + + PseudoVSOXSEG3EI64_V_M4_MF2_MASK = 10800 + + PseudoVSOXSEG3EI64_V_M8_M1 = 10801 + + PseudoVSOXSEG3EI64_V_M8_M1_MASK = 10802 + + PseudoVSOXSEG3EI64_V_M8_M2 = 10803 + + PseudoVSOXSEG3EI64_V_M8_M2_MASK = 10804 + + PseudoVSOXSEG3EI8_V_M1_M1 = 10805 + + PseudoVSOXSEG3EI8_V_M1_M1_MASK = 10806 + + PseudoVSOXSEG3EI8_V_M1_M2 = 10807 + + PseudoVSOXSEG3EI8_V_M1_M2_MASK = 10808 + + PseudoVSOXSEG3EI8_V_M2_M2 = 10809 + + PseudoVSOXSEG3EI8_V_M2_M2_MASK = 10810 + + PseudoVSOXSEG3EI8_V_MF2_M1 = 10811 + + PseudoVSOXSEG3EI8_V_MF2_M1_MASK = 10812 + + PseudoVSOXSEG3EI8_V_MF2_M2 = 10813 + + PseudoVSOXSEG3EI8_V_MF2_M2_MASK = 10814 + + PseudoVSOXSEG3EI8_V_MF2_MF2 = 10815 + + PseudoVSOXSEG3EI8_V_MF2_MF2_MASK = 10816 + + PseudoVSOXSEG3EI8_V_MF4_M1 = 10817 + + PseudoVSOXSEG3EI8_V_MF4_M1_MASK = 10818 + + PseudoVSOXSEG3EI8_V_MF4_M2 = 10819 + + PseudoVSOXSEG3EI8_V_MF4_M2_MASK = 10820 + + PseudoVSOXSEG3EI8_V_MF4_MF2 = 10821 + + PseudoVSOXSEG3EI8_V_MF4_MF2_MASK = 10822 + + PseudoVSOXSEG3EI8_V_MF4_MF4 = 10823 + + PseudoVSOXSEG3EI8_V_MF4_MF4_MASK = 10824 + + PseudoVSOXSEG3EI8_V_MF8_M1 = 10825 + + PseudoVSOXSEG3EI8_V_MF8_M1_MASK = 10826 + + PseudoVSOXSEG3EI8_V_MF8_MF2 = 10827 + + PseudoVSOXSEG3EI8_V_MF8_MF2_MASK = 10828 + + PseudoVSOXSEG3EI8_V_MF8_MF4 = 10829 + + PseudoVSOXSEG3EI8_V_MF8_MF4_MASK = 10830 + + PseudoVSOXSEG3EI8_V_MF8_MF8 = 10831 + + PseudoVSOXSEG3EI8_V_MF8_MF8_MASK = 10832 + + PseudoVSOXSEG4EI16_V_M1_M1 = 10833 + + PseudoVSOXSEG4EI16_V_M1_M1_MASK = 10834 + + PseudoVSOXSEG4EI16_V_M1_M2 = 10835 + + PseudoVSOXSEG4EI16_V_M1_M2_MASK = 10836 + + PseudoVSOXSEG4EI16_V_M1_MF2 = 10837 + + PseudoVSOXSEG4EI16_V_M1_MF2_MASK = 10838 + + PseudoVSOXSEG4EI16_V_M2_M1 = 10839 + + PseudoVSOXSEG4EI16_V_M2_M1_MASK = 10840 + + PseudoVSOXSEG4EI16_V_M2_M2 = 10841 + + PseudoVSOXSEG4EI16_V_M2_M2_MASK = 10842 + + PseudoVSOXSEG4EI16_V_M4_M2 = 10843 + + PseudoVSOXSEG4EI16_V_M4_M2_MASK = 10844 + + PseudoVSOXSEG4EI16_V_MF2_M1 = 10845 + + PseudoVSOXSEG4EI16_V_MF2_M1_MASK = 10846 + + PseudoVSOXSEG4EI16_V_MF2_M2 = 10847 + + PseudoVSOXSEG4EI16_V_MF2_M2_MASK = 10848 + + PseudoVSOXSEG4EI16_V_MF2_MF2 = 10849 + + PseudoVSOXSEG4EI16_V_MF2_MF2_MASK = 10850 + + PseudoVSOXSEG4EI16_V_MF2_MF4 = 10851 + + PseudoVSOXSEG4EI16_V_MF2_MF4_MASK = 10852 + + PseudoVSOXSEG4EI16_V_MF4_M1 = 10853 + + PseudoVSOXSEG4EI16_V_MF4_M1_MASK = 10854 + + PseudoVSOXSEG4EI16_V_MF4_MF2 = 10855 + + PseudoVSOXSEG4EI16_V_MF4_MF2_MASK = 10856 + + PseudoVSOXSEG4EI16_V_MF4_MF4 = 10857 + + PseudoVSOXSEG4EI16_V_MF4_MF4_MASK = 10858 + + PseudoVSOXSEG4EI16_V_MF4_MF8 = 10859 + + PseudoVSOXSEG4EI16_V_MF4_MF8_MASK = 10860 + + PseudoVSOXSEG4EI32_V_M1_M1 = 10861 + + PseudoVSOXSEG4EI32_V_M1_M1_MASK = 10862 + + PseudoVSOXSEG4EI32_V_M1_M2 = 10863 + + PseudoVSOXSEG4EI32_V_M1_M2_MASK = 10864 + + PseudoVSOXSEG4EI32_V_M1_MF2 = 10865 + + PseudoVSOXSEG4EI32_V_M1_MF2_MASK = 10866 + + PseudoVSOXSEG4EI32_V_M1_MF4 = 10867 + + PseudoVSOXSEG4EI32_V_M1_MF4_MASK = 10868 + + PseudoVSOXSEG4EI32_V_M2_M1 = 10869 + + PseudoVSOXSEG4EI32_V_M2_M1_MASK = 10870 + + PseudoVSOXSEG4EI32_V_M2_M2 = 10871 + + PseudoVSOXSEG4EI32_V_M2_M2_MASK = 10872 + + PseudoVSOXSEG4EI32_V_M2_MF2 = 10873 + + PseudoVSOXSEG4EI32_V_M2_MF2_MASK = 10874 + + PseudoVSOXSEG4EI32_V_M4_M1 = 10875 + + PseudoVSOXSEG4EI32_V_M4_M1_MASK = 10876 + + PseudoVSOXSEG4EI32_V_M4_M2 = 10877 + + PseudoVSOXSEG4EI32_V_M4_M2_MASK = 10878 + + PseudoVSOXSEG4EI32_V_M8_M2 = 10879 + + PseudoVSOXSEG4EI32_V_M8_M2_MASK = 10880 + + PseudoVSOXSEG4EI32_V_MF2_M1 = 10881 + + PseudoVSOXSEG4EI32_V_MF2_M1_MASK = 10882 + + PseudoVSOXSEG4EI32_V_MF2_MF2 = 10883 + + PseudoVSOXSEG4EI32_V_MF2_MF2_MASK = 10884 + + PseudoVSOXSEG4EI32_V_MF2_MF4 = 10885 + + PseudoVSOXSEG4EI32_V_MF2_MF4_MASK = 10886 + + PseudoVSOXSEG4EI32_V_MF2_MF8 = 10887 + + PseudoVSOXSEG4EI32_V_MF2_MF8_MASK = 10888 + + PseudoVSOXSEG4EI64_V_M1_M1 = 10889 + + PseudoVSOXSEG4EI64_V_M1_M1_MASK = 10890 + + PseudoVSOXSEG4EI64_V_M1_MF2 = 10891 + + PseudoVSOXSEG4EI64_V_M1_MF2_MASK = 10892 + + PseudoVSOXSEG4EI64_V_M1_MF4 = 10893 + + PseudoVSOXSEG4EI64_V_M1_MF4_MASK = 10894 + + PseudoVSOXSEG4EI64_V_M1_MF8 = 10895 + + PseudoVSOXSEG4EI64_V_M1_MF8_MASK = 10896 + + PseudoVSOXSEG4EI64_V_M2_M1 = 10897 + + PseudoVSOXSEG4EI64_V_M2_M1_MASK = 10898 + + PseudoVSOXSEG4EI64_V_M2_M2 = 10899 + + PseudoVSOXSEG4EI64_V_M2_M2_MASK = 10900 + + PseudoVSOXSEG4EI64_V_M2_MF2 = 10901 + + PseudoVSOXSEG4EI64_V_M2_MF2_MASK = 10902 + + PseudoVSOXSEG4EI64_V_M2_MF4 = 10903 + + PseudoVSOXSEG4EI64_V_M2_MF4_MASK = 10904 + + PseudoVSOXSEG4EI64_V_M4_M1 = 10905 + + PseudoVSOXSEG4EI64_V_M4_M1_MASK = 10906 + + PseudoVSOXSEG4EI64_V_M4_M2 = 10907 + + PseudoVSOXSEG4EI64_V_M4_M2_MASK = 10908 + + PseudoVSOXSEG4EI64_V_M4_MF2 = 10909 + + PseudoVSOXSEG4EI64_V_M4_MF2_MASK = 10910 + + PseudoVSOXSEG4EI64_V_M8_M1 = 10911 + + PseudoVSOXSEG4EI64_V_M8_M1_MASK = 10912 + + PseudoVSOXSEG4EI64_V_M8_M2 = 10913 + + PseudoVSOXSEG4EI64_V_M8_M2_MASK = 10914 + + PseudoVSOXSEG4EI8_V_M1_M1 = 10915 + + PseudoVSOXSEG4EI8_V_M1_M1_MASK = 10916 + + PseudoVSOXSEG4EI8_V_M1_M2 = 10917 + + PseudoVSOXSEG4EI8_V_M1_M2_MASK = 10918 + + PseudoVSOXSEG4EI8_V_M2_M2 = 10919 + + PseudoVSOXSEG4EI8_V_M2_M2_MASK = 10920 + + PseudoVSOXSEG4EI8_V_MF2_M1 = 10921 + + PseudoVSOXSEG4EI8_V_MF2_M1_MASK = 10922 + + PseudoVSOXSEG4EI8_V_MF2_M2 = 10923 + + PseudoVSOXSEG4EI8_V_MF2_M2_MASK = 10924 + + PseudoVSOXSEG4EI8_V_MF2_MF2 = 10925 + + PseudoVSOXSEG4EI8_V_MF2_MF2_MASK = 10926 + + PseudoVSOXSEG4EI8_V_MF4_M1 = 10927 + + PseudoVSOXSEG4EI8_V_MF4_M1_MASK = 10928 + + PseudoVSOXSEG4EI8_V_MF4_M2 = 10929 + + PseudoVSOXSEG4EI8_V_MF4_M2_MASK = 10930 + + PseudoVSOXSEG4EI8_V_MF4_MF2 = 10931 + + PseudoVSOXSEG4EI8_V_MF4_MF2_MASK = 10932 + + PseudoVSOXSEG4EI8_V_MF4_MF4 = 10933 + + PseudoVSOXSEG4EI8_V_MF4_MF4_MASK = 10934 + + PseudoVSOXSEG4EI8_V_MF8_M1 = 10935 + + PseudoVSOXSEG4EI8_V_MF8_M1_MASK = 10936 + + PseudoVSOXSEG4EI8_V_MF8_MF2 = 10937 + + PseudoVSOXSEG4EI8_V_MF8_MF2_MASK = 10938 + + PseudoVSOXSEG4EI8_V_MF8_MF4 = 10939 + + PseudoVSOXSEG4EI8_V_MF8_MF4_MASK = 10940 + + PseudoVSOXSEG4EI8_V_MF8_MF8 = 10941 + + PseudoVSOXSEG4EI8_V_MF8_MF8_MASK = 10942 + + PseudoVSOXSEG5EI16_V_M1_M1 = 10943 + + PseudoVSOXSEG5EI16_V_M1_M1_MASK = 10944 + + PseudoVSOXSEG5EI16_V_M1_MF2 = 10945 + + PseudoVSOXSEG5EI16_V_M1_MF2_MASK = 10946 + + PseudoVSOXSEG5EI16_V_M2_M1 = 10947 + + PseudoVSOXSEG5EI16_V_M2_M1_MASK = 10948 + + PseudoVSOXSEG5EI16_V_MF2_M1 = 10949 + + PseudoVSOXSEG5EI16_V_MF2_M1_MASK = 10950 + + PseudoVSOXSEG5EI16_V_MF2_MF2 = 10951 + + PseudoVSOXSEG5EI16_V_MF2_MF2_MASK = 10952 + + PseudoVSOXSEG5EI16_V_MF2_MF4 = 10953 + + PseudoVSOXSEG5EI16_V_MF2_MF4_MASK = 10954 + + PseudoVSOXSEG5EI16_V_MF4_M1 = 10955 + + PseudoVSOXSEG5EI16_V_MF4_M1_MASK = 10956 + + PseudoVSOXSEG5EI16_V_MF4_MF2 = 10957 + + PseudoVSOXSEG5EI16_V_MF4_MF2_MASK = 10958 + + PseudoVSOXSEG5EI16_V_MF4_MF4 = 10959 + + PseudoVSOXSEG5EI16_V_MF4_MF4_MASK = 10960 + + PseudoVSOXSEG5EI16_V_MF4_MF8 = 10961 + + PseudoVSOXSEG5EI16_V_MF4_MF8_MASK = 10962 + + PseudoVSOXSEG5EI32_V_M1_M1 = 10963 + + PseudoVSOXSEG5EI32_V_M1_M1_MASK = 10964 + + PseudoVSOXSEG5EI32_V_M1_MF2 = 10965 + + PseudoVSOXSEG5EI32_V_M1_MF2_MASK = 10966 + + PseudoVSOXSEG5EI32_V_M1_MF4 = 10967 + + PseudoVSOXSEG5EI32_V_M1_MF4_MASK = 10968 + + PseudoVSOXSEG5EI32_V_M2_M1 = 10969 + + PseudoVSOXSEG5EI32_V_M2_M1_MASK = 10970 + + PseudoVSOXSEG5EI32_V_M2_MF2 = 10971 + + PseudoVSOXSEG5EI32_V_M2_MF2_MASK = 10972 + + PseudoVSOXSEG5EI32_V_M4_M1 = 10973 + + PseudoVSOXSEG5EI32_V_M4_M1_MASK = 10974 + + PseudoVSOXSEG5EI32_V_MF2_M1 = 10975 + + PseudoVSOXSEG5EI32_V_MF2_M1_MASK = 10976 + + PseudoVSOXSEG5EI32_V_MF2_MF2 = 10977 + + PseudoVSOXSEG5EI32_V_MF2_MF2_MASK = 10978 + + PseudoVSOXSEG5EI32_V_MF2_MF4 = 10979 + + PseudoVSOXSEG5EI32_V_MF2_MF4_MASK = 10980 + + PseudoVSOXSEG5EI32_V_MF2_MF8 = 10981 + + PseudoVSOXSEG5EI32_V_MF2_MF8_MASK = 10982 + + PseudoVSOXSEG5EI64_V_M1_M1 = 10983 + + PseudoVSOXSEG5EI64_V_M1_M1_MASK = 10984 + + PseudoVSOXSEG5EI64_V_M1_MF2 = 10985 + + PseudoVSOXSEG5EI64_V_M1_MF2_MASK = 10986 + + PseudoVSOXSEG5EI64_V_M1_MF4 = 10987 + + PseudoVSOXSEG5EI64_V_M1_MF4_MASK = 10988 + + PseudoVSOXSEG5EI64_V_M1_MF8 = 10989 + + PseudoVSOXSEG5EI64_V_M1_MF8_MASK = 10990 + + PseudoVSOXSEG5EI64_V_M2_M1 = 10991 + + PseudoVSOXSEG5EI64_V_M2_M1_MASK = 10992 + + PseudoVSOXSEG5EI64_V_M2_MF2 = 10993 + + PseudoVSOXSEG5EI64_V_M2_MF2_MASK = 10994 + + PseudoVSOXSEG5EI64_V_M2_MF4 = 10995 + + PseudoVSOXSEG5EI64_V_M2_MF4_MASK = 10996 + + PseudoVSOXSEG5EI64_V_M4_M1 = 10997 + + PseudoVSOXSEG5EI64_V_M4_M1_MASK = 10998 + + PseudoVSOXSEG5EI64_V_M4_MF2 = 10999 + + PseudoVSOXSEG5EI64_V_M4_MF2_MASK = 11000 + + PseudoVSOXSEG5EI64_V_M8_M1 = 11001 + + PseudoVSOXSEG5EI64_V_M8_M1_MASK = 11002 + + PseudoVSOXSEG5EI8_V_M1_M1 = 11003 + + PseudoVSOXSEG5EI8_V_M1_M1_MASK = 11004 + + PseudoVSOXSEG5EI8_V_MF2_M1 = 11005 + + PseudoVSOXSEG5EI8_V_MF2_M1_MASK = 11006 + + PseudoVSOXSEG5EI8_V_MF2_MF2 = 11007 + + PseudoVSOXSEG5EI8_V_MF2_MF2_MASK = 11008 + + PseudoVSOXSEG5EI8_V_MF4_M1 = 11009 + + PseudoVSOXSEG5EI8_V_MF4_M1_MASK = 11010 + + PseudoVSOXSEG5EI8_V_MF4_MF2 = 11011 + + PseudoVSOXSEG5EI8_V_MF4_MF2_MASK = 11012 + + PseudoVSOXSEG5EI8_V_MF4_MF4 = 11013 + + PseudoVSOXSEG5EI8_V_MF4_MF4_MASK = 11014 + + PseudoVSOXSEG5EI8_V_MF8_M1 = 11015 + + PseudoVSOXSEG5EI8_V_MF8_M1_MASK = 11016 + + PseudoVSOXSEG5EI8_V_MF8_MF2 = 11017 + + PseudoVSOXSEG5EI8_V_MF8_MF2_MASK = 11018 + + PseudoVSOXSEG5EI8_V_MF8_MF4 = 11019 + + PseudoVSOXSEG5EI8_V_MF8_MF4_MASK = 11020 + + PseudoVSOXSEG5EI8_V_MF8_MF8 = 11021 + + PseudoVSOXSEG5EI8_V_MF8_MF8_MASK = 11022 + + PseudoVSOXSEG6EI16_V_M1_M1 = 11023 + + PseudoVSOXSEG6EI16_V_M1_M1_MASK = 11024 + + PseudoVSOXSEG6EI16_V_M1_MF2 = 11025 + + PseudoVSOXSEG6EI16_V_M1_MF2_MASK = 11026 + + PseudoVSOXSEG6EI16_V_M2_M1 = 11027 + + PseudoVSOXSEG6EI16_V_M2_M1_MASK = 11028 + + PseudoVSOXSEG6EI16_V_MF2_M1 = 11029 + + PseudoVSOXSEG6EI16_V_MF2_M1_MASK = 11030 + + PseudoVSOXSEG6EI16_V_MF2_MF2 = 11031 + + PseudoVSOXSEG6EI16_V_MF2_MF2_MASK = 11032 + + PseudoVSOXSEG6EI16_V_MF2_MF4 = 11033 + + PseudoVSOXSEG6EI16_V_MF2_MF4_MASK = 11034 + + PseudoVSOXSEG6EI16_V_MF4_M1 = 11035 + + PseudoVSOXSEG6EI16_V_MF4_M1_MASK = 11036 + + PseudoVSOXSEG6EI16_V_MF4_MF2 = 11037 + + PseudoVSOXSEG6EI16_V_MF4_MF2_MASK = 11038 + + PseudoVSOXSEG6EI16_V_MF4_MF4 = 11039 + + PseudoVSOXSEG6EI16_V_MF4_MF4_MASK = 11040 + + PseudoVSOXSEG6EI16_V_MF4_MF8 = 11041 + + PseudoVSOXSEG6EI16_V_MF4_MF8_MASK = 11042 + + PseudoVSOXSEG6EI32_V_M1_M1 = 11043 + + PseudoVSOXSEG6EI32_V_M1_M1_MASK = 11044 + + PseudoVSOXSEG6EI32_V_M1_MF2 = 11045 + + PseudoVSOXSEG6EI32_V_M1_MF2_MASK = 11046 + + PseudoVSOXSEG6EI32_V_M1_MF4 = 11047 + + PseudoVSOXSEG6EI32_V_M1_MF4_MASK = 11048 + + PseudoVSOXSEG6EI32_V_M2_M1 = 11049 + + PseudoVSOXSEG6EI32_V_M2_M1_MASK = 11050 + + PseudoVSOXSEG6EI32_V_M2_MF2 = 11051 + + PseudoVSOXSEG6EI32_V_M2_MF2_MASK = 11052 + + PseudoVSOXSEG6EI32_V_M4_M1 = 11053 + + PseudoVSOXSEG6EI32_V_M4_M1_MASK = 11054 + + PseudoVSOXSEG6EI32_V_MF2_M1 = 11055 + + PseudoVSOXSEG6EI32_V_MF2_M1_MASK = 11056 + + PseudoVSOXSEG6EI32_V_MF2_MF2 = 11057 + + PseudoVSOXSEG6EI32_V_MF2_MF2_MASK = 11058 + + PseudoVSOXSEG6EI32_V_MF2_MF4 = 11059 + + PseudoVSOXSEG6EI32_V_MF2_MF4_MASK = 11060 + + PseudoVSOXSEG6EI32_V_MF2_MF8 = 11061 + + PseudoVSOXSEG6EI32_V_MF2_MF8_MASK = 11062 + + PseudoVSOXSEG6EI64_V_M1_M1 = 11063 + + PseudoVSOXSEG6EI64_V_M1_M1_MASK = 11064 + + PseudoVSOXSEG6EI64_V_M1_MF2 = 11065 + + PseudoVSOXSEG6EI64_V_M1_MF2_MASK = 11066 + + PseudoVSOXSEG6EI64_V_M1_MF4 = 11067 + + PseudoVSOXSEG6EI64_V_M1_MF4_MASK = 11068 + + PseudoVSOXSEG6EI64_V_M1_MF8 = 11069 + + PseudoVSOXSEG6EI64_V_M1_MF8_MASK = 11070 + + PseudoVSOXSEG6EI64_V_M2_M1 = 11071 + + PseudoVSOXSEG6EI64_V_M2_M1_MASK = 11072 + + PseudoVSOXSEG6EI64_V_M2_MF2 = 11073 + + PseudoVSOXSEG6EI64_V_M2_MF2_MASK = 11074 + + PseudoVSOXSEG6EI64_V_M2_MF4 = 11075 + + PseudoVSOXSEG6EI64_V_M2_MF4_MASK = 11076 + + PseudoVSOXSEG6EI64_V_M4_M1 = 11077 + + PseudoVSOXSEG6EI64_V_M4_M1_MASK = 11078 + + PseudoVSOXSEG6EI64_V_M4_MF2 = 11079 + + PseudoVSOXSEG6EI64_V_M4_MF2_MASK = 11080 + + PseudoVSOXSEG6EI64_V_M8_M1 = 11081 + + PseudoVSOXSEG6EI64_V_M8_M1_MASK = 11082 + + PseudoVSOXSEG6EI8_V_M1_M1 = 11083 + + PseudoVSOXSEG6EI8_V_M1_M1_MASK = 11084 + + PseudoVSOXSEG6EI8_V_MF2_M1 = 11085 + + PseudoVSOXSEG6EI8_V_MF2_M1_MASK = 11086 + + PseudoVSOXSEG6EI8_V_MF2_MF2 = 11087 + + PseudoVSOXSEG6EI8_V_MF2_MF2_MASK = 11088 + + PseudoVSOXSEG6EI8_V_MF4_M1 = 11089 + + PseudoVSOXSEG6EI8_V_MF4_M1_MASK = 11090 + + PseudoVSOXSEG6EI8_V_MF4_MF2 = 11091 + + PseudoVSOXSEG6EI8_V_MF4_MF2_MASK = 11092 + + PseudoVSOXSEG6EI8_V_MF4_MF4 = 11093 + + PseudoVSOXSEG6EI8_V_MF4_MF4_MASK = 11094 + + PseudoVSOXSEG6EI8_V_MF8_M1 = 11095 + + PseudoVSOXSEG6EI8_V_MF8_M1_MASK = 11096 + + PseudoVSOXSEG6EI8_V_MF8_MF2 = 11097 + + PseudoVSOXSEG6EI8_V_MF8_MF2_MASK = 11098 + + PseudoVSOXSEG6EI8_V_MF8_MF4 = 11099 + + PseudoVSOXSEG6EI8_V_MF8_MF4_MASK = 11100 + + PseudoVSOXSEG6EI8_V_MF8_MF8 = 11101 + + PseudoVSOXSEG6EI8_V_MF8_MF8_MASK = 11102 + + PseudoVSOXSEG7EI16_V_M1_M1 = 11103 + + PseudoVSOXSEG7EI16_V_M1_M1_MASK = 11104 + + PseudoVSOXSEG7EI16_V_M1_MF2 = 11105 + + PseudoVSOXSEG7EI16_V_M1_MF2_MASK = 11106 + + PseudoVSOXSEG7EI16_V_M2_M1 = 11107 + + PseudoVSOXSEG7EI16_V_M2_M1_MASK = 11108 + + PseudoVSOXSEG7EI16_V_MF2_M1 = 11109 + + PseudoVSOXSEG7EI16_V_MF2_M1_MASK = 11110 + + PseudoVSOXSEG7EI16_V_MF2_MF2 = 11111 + + PseudoVSOXSEG7EI16_V_MF2_MF2_MASK = 11112 + + PseudoVSOXSEG7EI16_V_MF2_MF4 = 11113 + + PseudoVSOXSEG7EI16_V_MF2_MF4_MASK = 11114 + + PseudoVSOXSEG7EI16_V_MF4_M1 = 11115 + + PseudoVSOXSEG7EI16_V_MF4_M1_MASK = 11116 + + PseudoVSOXSEG7EI16_V_MF4_MF2 = 11117 + + PseudoVSOXSEG7EI16_V_MF4_MF2_MASK = 11118 + + PseudoVSOXSEG7EI16_V_MF4_MF4 = 11119 + + PseudoVSOXSEG7EI16_V_MF4_MF4_MASK = 11120 + + PseudoVSOXSEG7EI16_V_MF4_MF8 = 11121 + + PseudoVSOXSEG7EI16_V_MF4_MF8_MASK = 11122 + + PseudoVSOXSEG7EI32_V_M1_M1 = 11123 + + PseudoVSOXSEG7EI32_V_M1_M1_MASK = 11124 + + PseudoVSOXSEG7EI32_V_M1_MF2 = 11125 + + PseudoVSOXSEG7EI32_V_M1_MF2_MASK = 11126 + + PseudoVSOXSEG7EI32_V_M1_MF4 = 11127 + + PseudoVSOXSEG7EI32_V_M1_MF4_MASK = 11128 + + PseudoVSOXSEG7EI32_V_M2_M1 = 11129 + + PseudoVSOXSEG7EI32_V_M2_M1_MASK = 11130 + + PseudoVSOXSEG7EI32_V_M2_MF2 = 11131 + + PseudoVSOXSEG7EI32_V_M2_MF2_MASK = 11132 + + PseudoVSOXSEG7EI32_V_M4_M1 = 11133 + + PseudoVSOXSEG7EI32_V_M4_M1_MASK = 11134 + + PseudoVSOXSEG7EI32_V_MF2_M1 = 11135 + + PseudoVSOXSEG7EI32_V_MF2_M1_MASK = 11136 + + PseudoVSOXSEG7EI32_V_MF2_MF2 = 11137 + + PseudoVSOXSEG7EI32_V_MF2_MF2_MASK = 11138 + + PseudoVSOXSEG7EI32_V_MF2_MF4 = 11139 + + PseudoVSOXSEG7EI32_V_MF2_MF4_MASK = 11140 + + PseudoVSOXSEG7EI32_V_MF2_MF8 = 11141 + + PseudoVSOXSEG7EI32_V_MF2_MF8_MASK = 11142 + + PseudoVSOXSEG7EI64_V_M1_M1 = 11143 + + PseudoVSOXSEG7EI64_V_M1_M1_MASK = 11144 + + PseudoVSOXSEG7EI64_V_M1_MF2 = 11145 + + PseudoVSOXSEG7EI64_V_M1_MF2_MASK = 11146 + + PseudoVSOXSEG7EI64_V_M1_MF4 = 11147 + + PseudoVSOXSEG7EI64_V_M1_MF4_MASK = 11148 + + PseudoVSOXSEG7EI64_V_M1_MF8 = 11149 + + PseudoVSOXSEG7EI64_V_M1_MF8_MASK = 11150 + + PseudoVSOXSEG7EI64_V_M2_M1 = 11151 + + PseudoVSOXSEG7EI64_V_M2_M1_MASK = 11152 + + PseudoVSOXSEG7EI64_V_M2_MF2 = 11153 + + PseudoVSOXSEG7EI64_V_M2_MF2_MASK = 11154 + + PseudoVSOXSEG7EI64_V_M2_MF4 = 11155 + + PseudoVSOXSEG7EI64_V_M2_MF4_MASK = 11156 + + PseudoVSOXSEG7EI64_V_M4_M1 = 11157 + + PseudoVSOXSEG7EI64_V_M4_M1_MASK = 11158 + + PseudoVSOXSEG7EI64_V_M4_MF2 = 11159 + + PseudoVSOXSEG7EI64_V_M4_MF2_MASK = 11160 + + PseudoVSOXSEG7EI64_V_M8_M1 = 11161 + + PseudoVSOXSEG7EI64_V_M8_M1_MASK = 11162 + + PseudoVSOXSEG7EI8_V_M1_M1 = 11163 + + PseudoVSOXSEG7EI8_V_M1_M1_MASK = 11164 + + PseudoVSOXSEG7EI8_V_MF2_M1 = 11165 + + PseudoVSOXSEG7EI8_V_MF2_M1_MASK = 11166 + + PseudoVSOXSEG7EI8_V_MF2_MF2 = 11167 + + PseudoVSOXSEG7EI8_V_MF2_MF2_MASK = 11168 + + PseudoVSOXSEG7EI8_V_MF4_M1 = 11169 + + PseudoVSOXSEG7EI8_V_MF4_M1_MASK = 11170 + + PseudoVSOXSEG7EI8_V_MF4_MF2 = 11171 + + PseudoVSOXSEG7EI8_V_MF4_MF2_MASK = 11172 + + PseudoVSOXSEG7EI8_V_MF4_MF4 = 11173 + + PseudoVSOXSEG7EI8_V_MF4_MF4_MASK = 11174 + + PseudoVSOXSEG7EI8_V_MF8_M1 = 11175 + + PseudoVSOXSEG7EI8_V_MF8_M1_MASK = 11176 + + PseudoVSOXSEG7EI8_V_MF8_MF2 = 11177 + + PseudoVSOXSEG7EI8_V_MF8_MF2_MASK = 11178 + + PseudoVSOXSEG7EI8_V_MF8_MF4 = 11179 + + PseudoVSOXSEG7EI8_V_MF8_MF4_MASK = 11180 + + PseudoVSOXSEG7EI8_V_MF8_MF8 = 11181 + + PseudoVSOXSEG7EI8_V_MF8_MF8_MASK = 11182 + + PseudoVSOXSEG8EI16_V_M1_M1 = 11183 + + PseudoVSOXSEG8EI16_V_M1_M1_MASK = 11184 + + PseudoVSOXSEG8EI16_V_M1_MF2 = 11185 + + PseudoVSOXSEG8EI16_V_M1_MF2_MASK = 11186 + + PseudoVSOXSEG8EI16_V_M2_M1 = 11187 + + PseudoVSOXSEG8EI16_V_M2_M1_MASK = 11188 + + PseudoVSOXSEG8EI16_V_MF2_M1 = 11189 + + PseudoVSOXSEG8EI16_V_MF2_M1_MASK = 11190 + + PseudoVSOXSEG8EI16_V_MF2_MF2 = 11191 + + PseudoVSOXSEG8EI16_V_MF2_MF2_MASK = 11192 + + PseudoVSOXSEG8EI16_V_MF2_MF4 = 11193 + + PseudoVSOXSEG8EI16_V_MF2_MF4_MASK = 11194 + + PseudoVSOXSEG8EI16_V_MF4_M1 = 11195 + + PseudoVSOXSEG8EI16_V_MF4_M1_MASK = 11196 + + PseudoVSOXSEG8EI16_V_MF4_MF2 = 11197 + + PseudoVSOXSEG8EI16_V_MF4_MF2_MASK = 11198 + + PseudoVSOXSEG8EI16_V_MF4_MF4 = 11199 + + PseudoVSOXSEG8EI16_V_MF4_MF4_MASK = 11200 + + PseudoVSOXSEG8EI16_V_MF4_MF8 = 11201 + + PseudoVSOXSEG8EI16_V_MF4_MF8_MASK = 11202 + + PseudoVSOXSEG8EI32_V_M1_M1 = 11203 + + PseudoVSOXSEG8EI32_V_M1_M1_MASK = 11204 + + PseudoVSOXSEG8EI32_V_M1_MF2 = 11205 + + PseudoVSOXSEG8EI32_V_M1_MF2_MASK = 11206 + + PseudoVSOXSEG8EI32_V_M1_MF4 = 11207 + + PseudoVSOXSEG8EI32_V_M1_MF4_MASK = 11208 + + PseudoVSOXSEG8EI32_V_M2_M1 = 11209 + + PseudoVSOXSEG8EI32_V_M2_M1_MASK = 11210 + + PseudoVSOXSEG8EI32_V_M2_MF2 = 11211 + + PseudoVSOXSEG8EI32_V_M2_MF2_MASK = 11212 + + PseudoVSOXSEG8EI32_V_M4_M1 = 11213 + + PseudoVSOXSEG8EI32_V_M4_M1_MASK = 11214 + + PseudoVSOXSEG8EI32_V_MF2_M1 = 11215 + + PseudoVSOXSEG8EI32_V_MF2_M1_MASK = 11216 + + PseudoVSOXSEG8EI32_V_MF2_MF2 = 11217 + + PseudoVSOXSEG8EI32_V_MF2_MF2_MASK = 11218 + + PseudoVSOXSEG8EI32_V_MF2_MF4 = 11219 + + PseudoVSOXSEG8EI32_V_MF2_MF4_MASK = 11220 + + PseudoVSOXSEG8EI32_V_MF2_MF8 = 11221 + + PseudoVSOXSEG8EI32_V_MF2_MF8_MASK = 11222 + + PseudoVSOXSEG8EI64_V_M1_M1 = 11223 + + PseudoVSOXSEG8EI64_V_M1_M1_MASK = 11224 + + PseudoVSOXSEG8EI64_V_M1_MF2 = 11225 + + PseudoVSOXSEG8EI64_V_M1_MF2_MASK = 11226 + + PseudoVSOXSEG8EI64_V_M1_MF4 = 11227 + + PseudoVSOXSEG8EI64_V_M1_MF4_MASK = 11228 + + PseudoVSOXSEG8EI64_V_M1_MF8 = 11229 + + PseudoVSOXSEG8EI64_V_M1_MF8_MASK = 11230 + + PseudoVSOXSEG8EI64_V_M2_M1 = 11231 + + PseudoVSOXSEG8EI64_V_M2_M1_MASK = 11232 + + PseudoVSOXSEG8EI64_V_M2_MF2 = 11233 + + PseudoVSOXSEG8EI64_V_M2_MF2_MASK = 11234 + + PseudoVSOXSEG8EI64_V_M2_MF4 = 11235 + + PseudoVSOXSEG8EI64_V_M2_MF4_MASK = 11236 + + PseudoVSOXSEG8EI64_V_M4_M1 = 11237 + + PseudoVSOXSEG8EI64_V_M4_M1_MASK = 11238 + + PseudoVSOXSEG8EI64_V_M4_MF2 = 11239 + + PseudoVSOXSEG8EI64_V_M4_MF2_MASK = 11240 + + PseudoVSOXSEG8EI64_V_M8_M1 = 11241 + + PseudoVSOXSEG8EI64_V_M8_M1_MASK = 11242 + + PseudoVSOXSEG8EI8_V_M1_M1 = 11243 + + PseudoVSOXSEG8EI8_V_M1_M1_MASK = 11244 + + PseudoVSOXSEG8EI8_V_MF2_M1 = 11245 + + PseudoVSOXSEG8EI8_V_MF2_M1_MASK = 11246 + + PseudoVSOXSEG8EI8_V_MF2_MF2 = 11247 + + PseudoVSOXSEG8EI8_V_MF2_MF2_MASK = 11248 + + PseudoVSOXSEG8EI8_V_MF4_M1 = 11249 + + PseudoVSOXSEG8EI8_V_MF4_M1_MASK = 11250 + + PseudoVSOXSEG8EI8_V_MF4_MF2 = 11251 + + PseudoVSOXSEG8EI8_V_MF4_MF2_MASK = 11252 + + PseudoVSOXSEG8EI8_V_MF4_MF4 = 11253 + + PseudoVSOXSEG8EI8_V_MF4_MF4_MASK = 11254 + + PseudoVSOXSEG8EI8_V_MF8_M1 = 11255 + + PseudoVSOXSEG8EI8_V_MF8_M1_MASK = 11256 + + PseudoVSOXSEG8EI8_V_MF8_MF2 = 11257 + + PseudoVSOXSEG8EI8_V_MF8_MF2_MASK = 11258 + + PseudoVSOXSEG8EI8_V_MF8_MF4 = 11259 + + PseudoVSOXSEG8EI8_V_MF8_MF4_MASK = 11260 + + PseudoVSOXSEG8EI8_V_MF8_MF8 = 11261 + + PseudoVSOXSEG8EI8_V_MF8_MF8_MASK = 11262 + + PseudoVSPILL2_M1 = 11263 + + PseudoVSPILL2_M2 = 11264 + + PseudoVSPILL2_M4 = 11265 + + PseudoVSPILL2_MF2 = 11266 + + PseudoVSPILL2_MF4 = 11267 + + PseudoVSPILL2_MF8 = 11268 + + PseudoVSPILL3_M1 = 11269 + + PseudoVSPILL3_M2 = 11270 + + PseudoVSPILL3_MF2 = 11271 + + PseudoVSPILL3_MF4 = 11272 + + PseudoVSPILL3_MF8 = 11273 + + PseudoVSPILL4_M1 = 11274 + + PseudoVSPILL4_M2 = 11275 + + PseudoVSPILL4_MF2 = 11276 + + PseudoVSPILL4_MF4 = 11277 + + PseudoVSPILL4_MF8 = 11278 + + PseudoVSPILL5_M1 = 11279 + + PseudoVSPILL5_MF2 = 11280 + + PseudoVSPILL5_MF4 = 11281 + + PseudoVSPILL5_MF8 = 11282 + + PseudoVSPILL6_M1 = 11283 + + PseudoVSPILL6_MF2 = 11284 + + PseudoVSPILL6_MF4 = 11285 + + PseudoVSPILL6_MF8 = 11286 + + PseudoVSPILL7_M1 = 11287 + + PseudoVSPILL7_MF2 = 11288 + + PseudoVSPILL7_MF4 = 11289 + + PseudoVSPILL7_MF8 = 11290 + + PseudoVSPILL8_M1 = 11291 + + PseudoVSPILL8_MF2 = 11292 + + PseudoVSPILL8_MF4 = 11293 + + PseudoVSPILL8_MF8 = 11294 + + PseudoVSRA_VI_M1 = 11295 + + PseudoVSRA_VI_M1_MASK = 11296 + + PseudoVSRA_VI_M2 = 11297 + + PseudoVSRA_VI_M2_MASK = 11298 + + PseudoVSRA_VI_M4 = 11299 + + PseudoVSRA_VI_M4_MASK = 11300 + + PseudoVSRA_VI_M8 = 11301 + + PseudoVSRA_VI_M8_MASK = 11302 + + PseudoVSRA_VI_MF2 = 11303 + + PseudoVSRA_VI_MF2_MASK = 11304 + + PseudoVSRA_VI_MF4 = 11305 + + PseudoVSRA_VI_MF4_MASK = 11306 + + PseudoVSRA_VI_MF8 = 11307 + + PseudoVSRA_VI_MF8_MASK = 11308 + + PseudoVSRA_VV_M1 = 11309 + + PseudoVSRA_VV_M1_MASK = 11310 + + PseudoVSRA_VV_M2 = 11311 + + PseudoVSRA_VV_M2_MASK = 11312 + + PseudoVSRA_VV_M4 = 11313 + + PseudoVSRA_VV_M4_MASK = 11314 + + PseudoVSRA_VV_M8 = 11315 + + PseudoVSRA_VV_M8_MASK = 11316 + + PseudoVSRA_VV_MF2 = 11317 + + PseudoVSRA_VV_MF2_MASK = 11318 + + PseudoVSRA_VV_MF4 = 11319 + + PseudoVSRA_VV_MF4_MASK = 11320 + + PseudoVSRA_VV_MF8 = 11321 + + PseudoVSRA_VV_MF8_MASK = 11322 + + PseudoVSRA_VX_M1 = 11323 + + PseudoVSRA_VX_M1_MASK = 11324 + + PseudoVSRA_VX_M2 = 11325 + + PseudoVSRA_VX_M2_MASK = 11326 + + PseudoVSRA_VX_M4 = 11327 + + PseudoVSRA_VX_M4_MASK = 11328 + + PseudoVSRA_VX_M8 = 11329 + + PseudoVSRA_VX_M8_MASK = 11330 + + PseudoVSRA_VX_MF2 = 11331 + + PseudoVSRA_VX_MF2_MASK = 11332 + + PseudoVSRA_VX_MF4 = 11333 + + PseudoVSRA_VX_MF4_MASK = 11334 + + PseudoVSRA_VX_MF8 = 11335 + + PseudoVSRA_VX_MF8_MASK = 11336 + + PseudoVSRL_VI_M1 = 11337 + + PseudoVSRL_VI_M1_MASK = 11338 + + PseudoVSRL_VI_M2 = 11339 + + PseudoVSRL_VI_M2_MASK = 11340 + + PseudoVSRL_VI_M4 = 11341 + + PseudoVSRL_VI_M4_MASK = 11342 + + PseudoVSRL_VI_M8 = 11343 + + PseudoVSRL_VI_M8_MASK = 11344 + + PseudoVSRL_VI_MF2 = 11345 + + PseudoVSRL_VI_MF2_MASK = 11346 + + PseudoVSRL_VI_MF4 = 11347 + + PseudoVSRL_VI_MF4_MASK = 11348 + + PseudoVSRL_VI_MF8 = 11349 + + PseudoVSRL_VI_MF8_MASK = 11350 + + PseudoVSRL_VV_M1 = 11351 + + PseudoVSRL_VV_M1_MASK = 11352 + + PseudoVSRL_VV_M2 = 11353 + + PseudoVSRL_VV_M2_MASK = 11354 + + PseudoVSRL_VV_M4 = 11355 + + PseudoVSRL_VV_M4_MASK = 11356 + + PseudoVSRL_VV_M8 = 11357 + + PseudoVSRL_VV_M8_MASK = 11358 + + PseudoVSRL_VV_MF2 = 11359 + + PseudoVSRL_VV_MF2_MASK = 11360 + + PseudoVSRL_VV_MF4 = 11361 + + PseudoVSRL_VV_MF4_MASK = 11362 + + PseudoVSRL_VV_MF8 = 11363 + + PseudoVSRL_VV_MF8_MASK = 11364 + + PseudoVSRL_VX_M1 = 11365 + + PseudoVSRL_VX_M1_MASK = 11366 + + PseudoVSRL_VX_M2 = 11367 + + PseudoVSRL_VX_M2_MASK = 11368 + + PseudoVSRL_VX_M4 = 11369 + + PseudoVSRL_VX_M4_MASK = 11370 + + PseudoVSRL_VX_M8 = 11371 + + PseudoVSRL_VX_M8_MASK = 11372 + + PseudoVSRL_VX_MF2 = 11373 + + PseudoVSRL_VX_MF2_MASK = 11374 + + PseudoVSRL_VX_MF4 = 11375 + + PseudoVSRL_VX_MF4_MASK = 11376 + + PseudoVSRL_VX_MF8 = 11377 + + PseudoVSRL_VX_MF8_MASK = 11378 + + PseudoVSSE16_V_M1 = 11379 + + PseudoVSSE16_V_M1_MASK = 11380 + + PseudoVSSE16_V_M2 = 11381 + + PseudoVSSE16_V_M2_MASK = 11382 + + PseudoVSSE16_V_M4 = 11383 + + PseudoVSSE16_V_M4_MASK = 11384 + + PseudoVSSE16_V_M8 = 11385 + + PseudoVSSE16_V_M8_MASK = 11386 + + PseudoVSSE16_V_MF2 = 11387 + + PseudoVSSE16_V_MF2_MASK = 11388 + + PseudoVSSE16_V_MF4 = 11389 + + PseudoVSSE16_V_MF4_MASK = 11390 + + PseudoVSSE32_V_M1 = 11391 + + PseudoVSSE32_V_M1_MASK = 11392 + + PseudoVSSE32_V_M2 = 11393 + + PseudoVSSE32_V_M2_MASK = 11394 + + PseudoVSSE32_V_M4 = 11395 + + PseudoVSSE32_V_M4_MASK = 11396 + + PseudoVSSE32_V_M8 = 11397 + + PseudoVSSE32_V_M8_MASK = 11398 + + PseudoVSSE32_V_MF2 = 11399 + + PseudoVSSE32_V_MF2_MASK = 11400 + + PseudoVSSE64_V_M1 = 11401 + + PseudoVSSE64_V_M1_MASK = 11402 + + PseudoVSSE64_V_M2 = 11403 + + PseudoVSSE64_V_M2_MASK = 11404 + + PseudoVSSE64_V_M4 = 11405 + + PseudoVSSE64_V_M4_MASK = 11406 + + PseudoVSSE64_V_M8 = 11407 + + PseudoVSSE64_V_M8_MASK = 11408 + + PseudoVSSE8_V_M1 = 11409 + + PseudoVSSE8_V_M1_MASK = 11410 + + PseudoVSSE8_V_M2 = 11411 + + PseudoVSSE8_V_M2_MASK = 11412 + + PseudoVSSE8_V_M4 = 11413 + + PseudoVSSE8_V_M4_MASK = 11414 + + PseudoVSSE8_V_M8 = 11415 + + PseudoVSSE8_V_M8_MASK = 11416 + + PseudoVSSE8_V_MF2 = 11417 + + PseudoVSSE8_V_MF2_MASK = 11418 + + PseudoVSSE8_V_MF4 = 11419 + + PseudoVSSE8_V_MF4_MASK = 11420 + + PseudoVSSE8_V_MF8 = 11421 + + PseudoVSSE8_V_MF8_MASK = 11422 + + PseudoVSSEG2E16_V_M1 = 11423 + + PseudoVSSEG2E16_V_M1_MASK = 11424 + + PseudoVSSEG2E16_V_M2 = 11425 + + PseudoVSSEG2E16_V_M2_MASK = 11426 + + PseudoVSSEG2E16_V_M4 = 11427 + + PseudoVSSEG2E16_V_M4_MASK = 11428 + + PseudoVSSEG2E16_V_MF2 = 11429 + + PseudoVSSEG2E16_V_MF2_MASK = 11430 + + PseudoVSSEG2E16_V_MF4 = 11431 + + PseudoVSSEG2E16_V_MF4_MASK = 11432 + + PseudoVSSEG2E32_V_M1 = 11433 + + PseudoVSSEG2E32_V_M1_MASK = 11434 + + PseudoVSSEG2E32_V_M2 = 11435 + + PseudoVSSEG2E32_V_M2_MASK = 11436 + + PseudoVSSEG2E32_V_M4 = 11437 + + PseudoVSSEG2E32_V_M4_MASK = 11438 + + PseudoVSSEG2E32_V_MF2 = 11439 + + PseudoVSSEG2E32_V_MF2_MASK = 11440 + + PseudoVSSEG2E64_V_M1 = 11441 + + PseudoVSSEG2E64_V_M1_MASK = 11442 + + PseudoVSSEG2E64_V_M2 = 11443 + + PseudoVSSEG2E64_V_M2_MASK = 11444 + + PseudoVSSEG2E64_V_M4 = 11445 + + PseudoVSSEG2E64_V_M4_MASK = 11446 + + PseudoVSSEG2E8_V_M1 = 11447 + + PseudoVSSEG2E8_V_M1_MASK = 11448 + + PseudoVSSEG2E8_V_M2 = 11449 + + PseudoVSSEG2E8_V_M2_MASK = 11450 + + PseudoVSSEG2E8_V_M4 = 11451 + + PseudoVSSEG2E8_V_M4_MASK = 11452 + + PseudoVSSEG2E8_V_MF2 = 11453 + + PseudoVSSEG2E8_V_MF2_MASK = 11454 + + PseudoVSSEG2E8_V_MF4 = 11455 + + PseudoVSSEG2E8_V_MF4_MASK = 11456 + + PseudoVSSEG2E8_V_MF8 = 11457 + + PseudoVSSEG2E8_V_MF8_MASK = 11458 + + PseudoVSSEG3E16_V_M1 = 11459 + + PseudoVSSEG3E16_V_M1_MASK = 11460 + + PseudoVSSEG3E16_V_M2 = 11461 + + PseudoVSSEG3E16_V_M2_MASK = 11462 + + PseudoVSSEG3E16_V_MF2 = 11463 + + PseudoVSSEG3E16_V_MF2_MASK = 11464 + + PseudoVSSEG3E16_V_MF4 = 11465 + + PseudoVSSEG3E16_V_MF4_MASK = 11466 + + PseudoVSSEG3E32_V_M1 = 11467 + + PseudoVSSEG3E32_V_M1_MASK = 11468 + + PseudoVSSEG3E32_V_M2 = 11469 + + PseudoVSSEG3E32_V_M2_MASK = 11470 + + PseudoVSSEG3E32_V_MF2 = 11471 + + PseudoVSSEG3E32_V_MF2_MASK = 11472 + + PseudoVSSEG3E64_V_M1 = 11473 + + PseudoVSSEG3E64_V_M1_MASK = 11474 + + PseudoVSSEG3E64_V_M2 = 11475 + + PseudoVSSEG3E64_V_M2_MASK = 11476 + + PseudoVSSEG3E8_V_M1 = 11477 + + PseudoVSSEG3E8_V_M1_MASK = 11478 + + PseudoVSSEG3E8_V_M2 = 11479 + + PseudoVSSEG3E8_V_M2_MASK = 11480 + + PseudoVSSEG3E8_V_MF2 = 11481 + + PseudoVSSEG3E8_V_MF2_MASK = 11482 + + PseudoVSSEG3E8_V_MF4 = 11483 + + PseudoVSSEG3E8_V_MF4_MASK = 11484 + + PseudoVSSEG3E8_V_MF8 = 11485 + + PseudoVSSEG3E8_V_MF8_MASK = 11486 + + PseudoVSSEG4E16_V_M1 = 11487 + + PseudoVSSEG4E16_V_M1_MASK = 11488 + + PseudoVSSEG4E16_V_M2 = 11489 + + PseudoVSSEG4E16_V_M2_MASK = 11490 + + PseudoVSSEG4E16_V_MF2 = 11491 + + PseudoVSSEG4E16_V_MF2_MASK = 11492 + + PseudoVSSEG4E16_V_MF4 = 11493 + + PseudoVSSEG4E16_V_MF4_MASK = 11494 + + PseudoVSSEG4E32_V_M1 = 11495 + + PseudoVSSEG4E32_V_M1_MASK = 11496 + + PseudoVSSEG4E32_V_M2 = 11497 + + PseudoVSSEG4E32_V_M2_MASK = 11498 + + PseudoVSSEG4E32_V_MF2 = 11499 + + PseudoVSSEG4E32_V_MF2_MASK = 11500 + + PseudoVSSEG4E64_V_M1 = 11501 + + PseudoVSSEG4E64_V_M1_MASK = 11502 + + PseudoVSSEG4E64_V_M2 = 11503 + + PseudoVSSEG4E64_V_M2_MASK = 11504 + + PseudoVSSEG4E8_V_M1 = 11505 + + PseudoVSSEG4E8_V_M1_MASK = 11506 + + PseudoVSSEG4E8_V_M2 = 11507 + + PseudoVSSEG4E8_V_M2_MASK = 11508 + + PseudoVSSEG4E8_V_MF2 = 11509 + + PseudoVSSEG4E8_V_MF2_MASK = 11510 + + PseudoVSSEG4E8_V_MF4 = 11511 + + PseudoVSSEG4E8_V_MF4_MASK = 11512 + + PseudoVSSEG4E8_V_MF8 = 11513 + + PseudoVSSEG4E8_V_MF8_MASK = 11514 + + PseudoVSSEG5E16_V_M1 = 11515 + + PseudoVSSEG5E16_V_M1_MASK = 11516 + + PseudoVSSEG5E16_V_MF2 = 11517 + + PseudoVSSEG5E16_V_MF2_MASK = 11518 + + PseudoVSSEG5E16_V_MF4 = 11519 + + PseudoVSSEG5E16_V_MF4_MASK = 11520 + + PseudoVSSEG5E32_V_M1 = 11521 + + PseudoVSSEG5E32_V_M1_MASK = 11522 + + PseudoVSSEG5E32_V_MF2 = 11523 + + PseudoVSSEG5E32_V_MF2_MASK = 11524 + + PseudoVSSEG5E64_V_M1 = 11525 + + PseudoVSSEG5E64_V_M1_MASK = 11526 + + PseudoVSSEG5E8_V_M1 = 11527 + + PseudoVSSEG5E8_V_M1_MASK = 11528 + + PseudoVSSEG5E8_V_MF2 = 11529 + + PseudoVSSEG5E8_V_MF2_MASK = 11530 + + PseudoVSSEG5E8_V_MF4 = 11531 + + PseudoVSSEG5E8_V_MF4_MASK = 11532 + + PseudoVSSEG5E8_V_MF8 = 11533 + + PseudoVSSEG5E8_V_MF8_MASK = 11534 + + PseudoVSSEG6E16_V_M1 = 11535 + + PseudoVSSEG6E16_V_M1_MASK = 11536 + + PseudoVSSEG6E16_V_MF2 = 11537 + + PseudoVSSEG6E16_V_MF2_MASK = 11538 + + PseudoVSSEG6E16_V_MF4 = 11539 + + PseudoVSSEG6E16_V_MF4_MASK = 11540 + + PseudoVSSEG6E32_V_M1 = 11541 + + PseudoVSSEG6E32_V_M1_MASK = 11542 + + PseudoVSSEG6E32_V_MF2 = 11543 + + PseudoVSSEG6E32_V_MF2_MASK = 11544 + + PseudoVSSEG6E64_V_M1 = 11545 + + PseudoVSSEG6E64_V_M1_MASK = 11546 + + PseudoVSSEG6E8_V_M1 = 11547 + + PseudoVSSEG6E8_V_M1_MASK = 11548 + + PseudoVSSEG6E8_V_MF2 = 11549 + + PseudoVSSEG6E8_V_MF2_MASK = 11550 + + PseudoVSSEG6E8_V_MF4 = 11551 + + PseudoVSSEG6E8_V_MF4_MASK = 11552 + + PseudoVSSEG6E8_V_MF8 = 11553 + + PseudoVSSEG6E8_V_MF8_MASK = 11554 + + PseudoVSSEG7E16_V_M1 = 11555 + + PseudoVSSEG7E16_V_M1_MASK = 11556 + + PseudoVSSEG7E16_V_MF2 = 11557 + + PseudoVSSEG7E16_V_MF2_MASK = 11558 + + PseudoVSSEG7E16_V_MF4 = 11559 + + PseudoVSSEG7E16_V_MF4_MASK = 11560 + + PseudoVSSEG7E32_V_M1 = 11561 + + PseudoVSSEG7E32_V_M1_MASK = 11562 + + PseudoVSSEG7E32_V_MF2 = 11563 + + PseudoVSSEG7E32_V_MF2_MASK = 11564 + + PseudoVSSEG7E64_V_M1 = 11565 + + PseudoVSSEG7E64_V_M1_MASK = 11566 + + PseudoVSSEG7E8_V_M1 = 11567 + + PseudoVSSEG7E8_V_M1_MASK = 11568 + + PseudoVSSEG7E8_V_MF2 = 11569 + + PseudoVSSEG7E8_V_MF2_MASK = 11570 + + PseudoVSSEG7E8_V_MF4 = 11571 + + PseudoVSSEG7E8_V_MF4_MASK = 11572 + + PseudoVSSEG7E8_V_MF8 = 11573 + + PseudoVSSEG7E8_V_MF8_MASK = 11574 + + PseudoVSSEG8E16_V_M1 = 11575 + + PseudoVSSEG8E16_V_M1_MASK = 11576 + + PseudoVSSEG8E16_V_MF2 = 11577 + + PseudoVSSEG8E16_V_MF2_MASK = 11578 + + PseudoVSSEG8E16_V_MF4 = 11579 + + PseudoVSSEG8E16_V_MF4_MASK = 11580 + + PseudoVSSEG8E32_V_M1 = 11581 + + PseudoVSSEG8E32_V_M1_MASK = 11582 + + PseudoVSSEG8E32_V_MF2 = 11583 + + PseudoVSSEG8E32_V_MF2_MASK = 11584 + + PseudoVSSEG8E64_V_M1 = 11585 + + PseudoVSSEG8E64_V_M1_MASK = 11586 + + PseudoVSSEG8E8_V_M1 = 11587 + + PseudoVSSEG8E8_V_M1_MASK = 11588 + + PseudoVSSEG8E8_V_MF2 = 11589 + + PseudoVSSEG8E8_V_MF2_MASK = 11590 + + PseudoVSSEG8E8_V_MF4 = 11591 + + PseudoVSSEG8E8_V_MF4_MASK = 11592 + + PseudoVSSEG8E8_V_MF8 = 11593 + + PseudoVSSEG8E8_V_MF8_MASK = 11594 + + PseudoVSSRA_VI_M1 = 11595 + + PseudoVSSRA_VI_M1_MASK = 11596 + + PseudoVSSRA_VI_M2 = 11597 + + PseudoVSSRA_VI_M2_MASK = 11598 + + PseudoVSSRA_VI_M4 = 11599 + + PseudoVSSRA_VI_M4_MASK = 11600 + + PseudoVSSRA_VI_M8 = 11601 + + PseudoVSSRA_VI_M8_MASK = 11602 + + PseudoVSSRA_VI_MF2 = 11603 + + PseudoVSSRA_VI_MF2_MASK = 11604 + + PseudoVSSRA_VI_MF4 = 11605 + + PseudoVSSRA_VI_MF4_MASK = 11606 + + PseudoVSSRA_VI_MF8 = 11607 + + PseudoVSSRA_VI_MF8_MASK = 11608 + + PseudoVSSRA_VV_M1 = 11609 + + PseudoVSSRA_VV_M1_MASK = 11610 + + PseudoVSSRA_VV_M2 = 11611 + + PseudoVSSRA_VV_M2_MASK = 11612 + + PseudoVSSRA_VV_M4 = 11613 + + PseudoVSSRA_VV_M4_MASK = 11614 + + PseudoVSSRA_VV_M8 = 11615 + + PseudoVSSRA_VV_M8_MASK = 11616 + + PseudoVSSRA_VV_MF2 = 11617 + + PseudoVSSRA_VV_MF2_MASK = 11618 + + PseudoVSSRA_VV_MF4 = 11619 + + PseudoVSSRA_VV_MF4_MASK = 11620 + + PseudoVSSRA_VV_MF8 = 11621 + + PseudoVSSRA_VV_MF8_MASK = 11622 + + PseudoVSSRA_VX_M1 = 11623 + + PseudoVSSRA_VX_M1_MASK = 11624 + + PseudoVSSRA_VX_M2 = 11625 + + PseudoVSSRA_VX_M2_MASK = 11626 + + PseudoVSSRA_VX_M4 = 11627 + + PseudoVSSRA_VX_M4_MASK = 11628 + + PseudoVSSRA_VX_M8 = 11629 + + PseudoVSSRA_VX_M8_MASK = 11630 + + PseudoVSSRA_VX_MF2 = 11631 + + PseudoVSSRA_VX_MF2_MASK = 11632 + + PseudoVSSRA_VX_MF4 = 11633 + + PseudoVSSRA_VX_MF4_MASK = 11634 + + PseudoVSSRA_VX_MF8 = 11635 + + PseudoVSSRA_VX_MF8_MASK = 11636 + + PseudoVSSRL_VI_M1 = 11637 + + PseudoVSSRL_VI_M1_MASK = 11638 + + PseudoVSSRL_VI_M2 = 11639 + + PseudoVSSRL_VI_M2_MASK = 11640 + + PseudoVSSRL_VI_M4 = 11641 + + PseudoVSSRL_VI_M4_MASK = 11642 + + PseudoVSSRL_VI_M8 = 11643 + + PseudoVSSRL_VI_M8_MASK = 11644 + + PseudoVSSRL_VI_MF2 = 11645 + + PseudoVSSRL_VI_MF2_MASK = 11646 + + PseudoVSSRL_VI_MF4 = 11647 + + PseudoVSSRL_VI_MF4_MASK = 11648 + + PseudoVSSRL_VI_MF8 = 11649 + + PseudoVSSRL_VI_MF8_MASK = 11650 + + PseudoVSSRL_VV_M1 = 11651 + + PseudoVSSRL_VV_M1_MASK = 11652 + + PseudoVSSRL_VV_M2 = 11653 + + PseudoVSSRL_VV_M2_MASK = 11654 + + PseudoVSSRL_VV_M4 = 11655 + + PseudoVSSRL_VV_M4_MASK = 11656 + + PseudoVSSRL_VV_M8 = 11657 + + PseudoVSSRL_VV_M8_MASK = 11658 + + PseudoVSSRL_VV_MF2 = 11659 + + PseudoVSSRL_VV_MF2_MASK = 11660 + + PseudoVSSRL_VV_MF4 = 11661 + + PseudoVSSRL_VV_MF4_MASK = 11662 + + PseudoVSSRL_VV_MF8 = 11663 + + PseudoVSSRL_VV_MF8_MASK = 11664 + + PseudoVSSRL_VX_M1 = 11665 + + PseudoVSSRL_VX_M1_MASK = 11666 + + PseudoVSSRL_VX_M2 = 11667 + + PseudoVSSRL_VX_M2_MASK = 11668 + + PseudoVSSRL_VX_M4 = 11669 + + PseudoVSSRL_VX_M4_MASK = 11670 + + PseudoVSSRL_VX_M8 = 11671 + + PseudoVSSRL_VX_M8_MASK = 11672 + + PseudoVSSRL_VX_MF2 = 11673 + + PseudoVSSRL_VX_MF2_MASK = 11674 + + PseudoVSSRL_VX_MF4 = 11675 + + PseudoVSSRL_VX_MF4_MASK = 11676 + + PseudoVSSRL_VX_MF8 = 11677 + + PseudoVSSRL_VX_MF8_MASK = 11678 + + PseudoVSSSEG2E16_V_M1 = 11679 + + PseudoVSSSEG2E16_V_M1_MASK = 11680 + + PseudoVSSSEG2E16_V_M2 = 11681 + + PseudoVSSSEG2E16_V_M2_MASK = 11682 + + PseudoVSSSEG2E16_V_M4 = 11683 + + PseudoVSSSEG2E16_V_M4_MASK = 11684 + + PseudoVSSSEG2E16_V_MF2 = 11685 + + PseudoVSSSEG2E16_V_MF2_MASK = 11686 + + PseudoVSSSEG2E16_V_MF4 = 11687 + + PseudoVSSSEG2E16_V_MF4_MASK = 11688 + + PseudoVSSSEG2E32_V_M1 = 11689 + + PseudoVSSSEG2E32_V_M1_MASK = 11690 + + PseudoVSSSEG2E32_V_M2 = 11691 + + PseudoVSSSEG2E32_V_M2_MASK = 11692 + + PseudoVSSSEG2E32_V_M4 = 11693 + + PseudoVSSSEG2E32_V_M4_MASK = 11694 + + PseudoVSSSEG2E32_V_MF2 = 11695 + + PseudoVSSSEG2E32_V_MF2_MASK = 11696 + + PseudoVSSSEG2E64_V_M1 = 11697 + + PseudoVSSSEG2E64_V_M1_MASK = 11698 + + PseudoVSSSEG2E64_V_M2 = 11699 + + PseudoVSSSEG2E64_V_M2_MASK = 11700 + + PseudoVSSSEG2E64_V_M4 = 11701 + + PseudoVSSSEG2E64_V_M4_MASK = 11702 + + PseudoVSSSEG2E8_V_M1 = 11703 + + PseudoVSSSEG2E8_V_M1_MASK = 11704 + + PseudoVSSSEG2E8_V_M2 = 11705 + + PseudoVSSSEG2E8_V_M2_MASK = 11706 + + PseudoVSSSEG2E8_V_M4 = 11707 + + PseudoVSSSEG2E8_V_M4_MASK = 11708 + + PseudoVSSSEG2E8_V_MF2 = 11709 + + PseudoVSSSEG2E8_V_MF2_MASK = 11710 + + PseudoVSSSEG2E8_V_MF4 = 11711 + + PseudoVSSSEG2E8_V_MF4_MASK = 11712 + + PseudoVSSSEG2E8_V_MF8 = 11713 + + PseudoVSSSEG2E8_V_MF8_MASK = 11714 + + PseudoVSSSEG3E16_V_M1 = 11715 + + PseudoVSSSEG3E16_V_M1_MASK = 11716 + + PseudoVSSSEG3E16_V_M2 = 11717 + + PseudoVSSSEG3E16_V_M2_MASK = 11718 + + PseudoVSSSEG3E16_V_MF2 = 11719 + + PseudoVSSSEG3E16_V_MF2_MASK = 11720 + + PseudoVSSSEG3E16_V_MF4 = 11721 + + PseudoVSSSEG3E16_V_MF4_MASK = 11722 + + PseudoVSSSEG3E32_V_M1 = 11723 + + PseudoVSSSEG3E32_V_M1_MASK = 11724 + + PseudoVSSSEG3E32_V_M2 = 11725 + + PseudoVSSSEG3E32_V_M2_MASK = 11726 + + PseudoVSSSEG3E32_V_MF2 = 11727 + + PseudoVSSSEG3E32_V_MF2_MASK = 11728 + + PseudoVSSSEG3E64_V_M1 = 11729 + + PseudoVSSSEG3E64_V_M1_MASK = 11730 + + PseudoVSSSEG3E64_V_M2 = 11731 + + PseudoVSSSEG3E64_V_M2_MASK = 11732 + + PseudoVSSSEG3E8_V_M1 = 11733 + + PseudoVSSSEG3E8_V_M1_MASK = 11734 + + PseudoVSSSEG3E8_V_M2 = 11735 + + PseudoVSSSEG3E8_V_M2_MASK = 11736 + + PseudoVSSSEG3E8_V_MF2 = 11737 + + PseudoVSSSEG3E8_V_MF2_MASK = 11738 + + PseudoVSSSEG3E8_V_MF4 = 11739 + + PseudoVSSSEG3E8_V_MF4_MASK = 11740 + + PseudoVSSSEG3E8_V_MF8 = 11741 + + PseudoVSSSEG3E8_V_MF8_MASK = 11742 + + PseudoVSSSEG4E16_V_M1 = 11743 + + PseudoVSSSEG4E16_V_M1_MASK = 11744 + + PseudoVSSSEG4E16_V_M2 = 11745 + + PseudoVSSSEG4E16_V_M2_MASK = 11746 + + PseudoVSSSEG4E16_V_MF2 = 11747 + + PseudoVSSSEG4E16_V_MF2_MASK = 11748 + + PseudoVSSSEG4E16_V_MF4 = 11749 + + PseudoVSSSEG4E16_V_MF4_MASK = 11750 + + PseudoVSSSEG4E32_V_M1 = 11751 + + PseudoVSSSEG4E32_V_M1_MASK = 11752 + + PseudoVSSSEG4E32_V_M2 = 11753 + + PseudoVSSSEG4E32_V_M2_MASK = 11754 + + PseudoVSSSEG4E32_V_MF2 = 11755 + + PseudoVSSSEG4E32_V_MF2_MASK = 11756 + + PseudoVSSSEG4E64_V_M1 = 11757 + + PseudoVSSSEG4E64_V_M1_MASK = 11758 + + PseudoVSSSEG4E64_V_M2 = 11759 + + PseudoVSSSEG4E64_V_M2_MASK = 11760 + + PseudoVSSSEG4E8_V_M1 = 11761 + + PseudoVSSSEG4E8_V_M1_MASK = 11762 + + PseudoVSSSEG4E8_V_M2 = 11763 + + PseudoVSSSEG4E8_V_M2_MASK = 11764 + + PseudoVSSSEG4E8_V_MF2 = 11765 + + PseudoVSSSEG4E8_V_MF2_MASK = 11766 + + PseudoVSSSEG4E8_V_MF4 = 11767 + + PseudoVSSSEG4E8_V_MF4_MASK = 11768 + + PseudoVSSSEG4E8_V_MF8 = 11769 + + PseudoVSSSEG4E8_V_MF8_MASK = 11770 + + PseudoVSSSEG5E16_V_M1 = 11771 + + PseudoVSSSEG5E16_V_M1_MASK = 11772 + + PseudoVSSSEG5E16_V_MF2 = 11773 + + PseudoVSSSEG5E16_V_MF2_MASK = 11774 + + PseudoVSSSEG5E16_V_MF4 = 11775 + + PseudoVSSSEG5E16_V_MF4_MASK = 11776 + + PseudoVSSSEG5E32_V_M1 = 11777 + + PseudoVSSSEG5E32_V_M1_MASK = 11778 + + PseudoVSSSEG5E32_V_MF2 = 11779 + + PseudoVSSSEG5E32_V_MF2_MASK = 11780 + + PseudoVSSSEG5E64_V_M1 = 11781 + + PseudoVSSSEG5E64_V_M1_MASK = 11782 + + PseudoVSSSEG5E8_V_M1 = 11783 + + PseudoVSSSEG5E8_V_M1_MASK = 11784 + + PseudoVSSSEG5E8_V_MF2 = 11785 + + PseudoVSSSEG5E8_V_MF2_MASK = 11786 + + PseudoVSSSEG5E8_V_MF4 = 11787 + + PseudoVSSSEG5E8_V_MF4_MASK = 11788 + + PseudoVSSSEG5E8_V_MF8 = 11789 + + PseudoVSSSEG5E8_V_MF8_MASK = 11790 + + PseudoVSSSEG6E16_V_M1 = 11791 + + PseudoVSSSEG6E16_V_M1_MASK = 11792 + + PseudoVSSSEG6E16_V_MF2 = 11793 + + PseudoVSSSEG6E16_V_MF2_MASK = 11794 + + PseudoVSSSEG6E16_V_MF4 = 11795 + + PseudoVSSSEG6E16_V_MF4_MASK = 11796 + + PseudoVSSSEG6E32_V_M1 = 11797 + + PseudoVSSSEG6E32_V_M1_MASK = 11798 + + PseudoVSSSEG6E32_V_MF2 = 11799 + + PseudoVSSSEG6E32_V_MF2_MASK = 11800 + + PseudoVSSSEG6E64_V_M1 = 11801 + + PseudoVSSSEG6E64_V_M1_MASK = 11802 + + PseudoVSSSEG6E8_V_M1 = 11803 + + PseudoVSSSEG6E8_V_M1_MASK = 11804 + + PseudoVSSSEG6E8_V_MF2 = 11805 + + PseudoVSSSEG6E8_V_MF2_MASK = 11806 + + PseudoVSSSEG6E8_V_MF4 = 11807 + + PseudoVSSSEG6E8_V_MF4_MASK = 11808 + + PseudoVSSSEG6E8_V_MF8 = 11809 + + PseudoVSSSEG6E8_V_MF8_MASK = 11810 + + PseudoVSSSEG7E16_V_M1 = 11811 + + PseudoVSSSEG7E16_V_M1_MASK = 11812 + + PseudoVSSSEG7E16_V_MF2 = 11813 + + PseudoVSSSEG7E16_V_MF2_MASK = 11814 + + PseudoVSSSEG7E16_V_MF4 = 11815 + + PseudoVSSSEG7E16_V_MF4_MASK = 11816 + + PseudoVSSSEG7E32_V_M1 = 11817 + + PseudoVSSSEG7E32_V_M1_MASK = 11818 + + PseudoVSSSEG7E32_V_MF2 = 11819 + + PseudoVSSSEG7E32_V_MF2_MASK = 11820 + + PseudoVSSSEG7E64_V_M1 = 11821 + + PseudoVSSSEG7E64_V_M1_MASK = 11822 + + PseudoVSSSEG7E8_V_M1 = 11823 + + PseudoVSSSEG7E8_V_M1_MASK = 11824 + + PseudoVSSSEG7E8_V_MF2 = 11825 + + PseudoVSSSEG7E8_V_MF2_MASK = 11826 + + PseudoVSSSEG7E8_V_MF4 = 11827 + + PseudoVSSSEG7E8_V_MF4_MASK = 11828 + + PseudoVSSSEG7E8_V_MF8 = 11829 + + PseudoVSSSEG7E8_V_MF8_MASK = 11830 + + PseudoVSSSEG8E16_V_M1 = 11831 + + PseudoVSSSEG8E16_V_M1_MASK = 11832 + + PseudoVSSSEG8E16_V_MF2 = 11833 + + PseudoVSSSEG8E16_V_MF2_MASK = 11834 + + PseudoVSSSEG8E16_V_MF4 = 11835 + + PseudoVSSSEG8E16_V_MF4_MASK = 11836 + + PseudoVSSSEG8E32_V_M1 = 11837 + + PseudoVSSSEG8E32_V_M1_MASK = 11838 + + PseudoVSSSEG8E32_V_MF2 = 11839 + + PseudoVSSSEG8E32_V_MF2_MASK = 11840 + + PseudoVSSSEG8E64_V_M1 = 11841 + + PseudoVSSSEG8E64_V_M1_MASK = 11842 + + PseudoVSSSEG8E8_V_M1 = 11843 + + PseudoVSSSEG8E8_V_M1_MASK = 11844 + + PseudoVSSSEG8E8_V_MF2 = 11845 + + PseudoVSSSEG8E8_V_MF2_MASK = 11846 + + PseudoVSSSEG8E8_V_MF4 = 11847 + + PseudoVSSSEG8E8_V_MF4_MASK = 11848 + + PseudoVSSSEG8E8_V_MF8 = 11849 + + PseudoVSSSEG8E8_V_MF8_MASK = 11850 + + PseudoVSSUBU_VV_M1 = 11851 + + PseudoVSSUBU_VV_M1_MASK = 11852 + + PseudoVSSUBU_VV_M2 = 11853 + + PseudoVSSUBU_VV_M2_MASK = 11854 + + PseudoVSSUBU_VV_M4 = 11855 + + PseudoVSSUBU_VV_M4_MASK = 11856 + + PseudoVSSUBU_VV_M8 = 11857 + + PseudoVSSUBU_VV_M8_MASK = 11858 + + PseudoVSSUBU_VV_MF2 = 11859 + + PseudoVSSUBU_VV_MF2_MASK = 11860 + + PseudoVSSUBU_VV_MF4 = 11861 + + PseudoVSSUBU_VV_MF4_MASK = 11862 + + PseudoVSSUBU_VV_MF8 = 11863 + + PseudoVSSUBU_VV_MF8_MASK = 11864 + + PseudoVSSUBU_VX_M1 = 11865 + + PseudoVSSUBU_VX_M1_MASK = 11866 + + PseudoVSSUBU_VX_M2 = 11867 + + PseudoVSSUBU_VX_M2_MASK = 11868 + + PseudoVSSUBU_VX_M4 = 11869 + + PseudoVSSUBU_VX_M4_MASK = 11870 + + PseudoVSSUBU_VX_M8 = 11871 + + PseudoVSSUBU_VX_M8_MASK = 11872 + + PseudoVSSUBU_VX_MF2 = 11873 + + PseudoVSSUBU_VX_MF2_MASK = 11874 + + PseudoVSSUBU_VX_MF4 = 11875 + + PseudoVSSUBU_VX_MF4_MASK = 11876 + + PseudoVSSUBU_VX_MF8 = 11877 + + PseudoVSSUBU_VX_MF8_MASK = 11878 + + PseudoVSSUB_VV_M1 = 11879 + + PseudoVSSUB_VV_M1_MASK = 11880 + + PseudoVSSUB_VV_M2 = 11881 + + PseudoVSSUB_VV_M2_MASK = 11882 + + PseudoVSSUB_VV_M4 = 11883 + + PseudoVSSUB_VV_M4_MASK = 11884 + + PseudoVSSUB_VV_M8 = 11885 + + PseudoVSSUB_VV_M8_MASK = 11886 + + PseudoVSSUB_VV_MF2 = 11887 + + PseudoVSSUB_VV_MF2_MASK = 11888 + + PseudoVSSUB_VV_MF4 = 11889 + + PseudoVSSUB_VV_MF4_MASK = 11890 + + PseudoVSSUB_VV_MF8 = 11891 + + PseudoVSSUB_VV_MF8_MASK = 11892 + + PseudoVSSUB_VX_M1 = 11893 + + PseudoVSSUB_VX_M1_MASK = 11894 + + PseudoVSSUB_VX_M2 = 11895 + + PseudoVSSUB_VX_M2_MASK = 11896 + + PseudoVSSUB_VX_M4 = 11897 + + PseudoVSSUB_VX_M4_MASK = 11898 + + PseudoVSSUB_VX_M8 = 11899 + + PseudoVSSUB_VX_M8_MASK = 11900 + + PseudoVSSUB_VX_MF2 = 11901 + + PseudoVSSUB_VX_MF2_MASK = 11902 + + PseudoVSSUB_VX_MF4 = 11903 + + PseudoVSSUB_VX_MF4_MASK = 11904 + + PseudoVSSUB_VX_MF8 = 11905 + + PseudoVSSUB_VX_MF8_MASK = 11906 + + PseudoVSUB_VV_M1 = 11907 + + PseudoVSUB_VV_M1_MASK = 11908 + + PseudoVSUB_VV_M2 = 11909 + + PseudoVSUB_VV_M2_MASK = 11910 + + PseudoVSUB_VV_M4 = 11911 + + PseudoVSUB_VV_M4_MASK = 11912 + + PseudoVSUB_VV_M8 = 11913 + + PseudoVSUB_VV_M8_MASK = 11914 + + PseudoVSUB_VV_MF2 = 11915 + + PseudoVSUB_VV_MF2_MASK = 11916 + + PseudoVSUB_VV_MF4 = 11917 + + PseudoVSUB_VV_MF4_MASK = 11918 + + PseudoVSUB_VV_MF8 = 11919 + + PseudoVSUB_VV_MF8_MASK = 11920 + + PseudoVSUB_VX_M1 = 11921 + + PseudoVSUB_VX_M1_MASK = 11922 + + PseudoVSUB_VX_M2 = 11923 + + PseudoVSUB_VX_M2_MASK = 11924 + + PseudoVSUB_VX_M4 = 11925 + + PseudoVSUB_VX_M4_MASK = 11926 + + PseudoVSUB_VX_M8 = 11927 + + PseudoVSUB_VX_M8_MASK = 11928 + + PseudoVSUB_VX_MF2 = 11929 + + PseudoVSUB_VX_MF2_MASK = 11930 + + PseudoVSUB_VX_MF4 = 11931 + + PseudoVSUB_VX_MF4_MASK = 11932 + + PseudoVSUB_VX_MF8 = 11933 + + PseudoVSUB_VX_MF8_MASK = 11934 + + PseudoVSUXEI16_V_M1_M1 = 11935 + + PseudoVSUXEI16_V_M1_M1_MASK = 11936 + + PseudoVSUXEI16_V_M1_M2 = 11937 + + PseudoVSUXEI16_V_M1_M2_MASK = 11938 + + PseudoVSUXEI16_V_M1_M4 = 11939 + + PseudoVSUXEI16_V_M1_M4_MASK = 11940 + + PseudoVSUXEI16_V_M1_MF2 = 11941 + + PseudoVSUXEI16_V_M1_MF2_MASK = 11942 + + PseudoVSUXEI16_V_M2_M1 = 11943 + + PseudoVSUXEI16_V_M2_M1_MASK = 11944 + + PseudoVSUXEI16_V_M2_M2 = 11945 + + PseudoVSUXEI16_V_M2_M2_MASK = 11946 + + PseudoVSUXEI16_V_M2_M4 = 11947 + + PseudoVSUXEI16_V_M2_M4_MASK = 11948 + + PseudoVSUXEI16_V_M2_M8 = 11949 + + PseudoVSUXEI16_V_M2_M8_MASK = 11950 + + PseudoVSUXEI16_V_M4_M2 = 11951 + + PseudoVSUXEI16_V_M4_M2_MASK = 11952 + + PseudoVSUXEI16_V_M4_M4 = 11953 + + PseudoVSUXEI16_V_M4_M4_MASK = 11954 + + PseudoVSUXEI16_V_M4_M8 = 11955 + + PseudoVSUXEI16_V_M4_M8_MASK = 11956 + + PseudoVSUXEI16_V_M8_M4 = 11957 + + PseudoVSUXEI16_V_M8_M4_MASK = 11958 + + PseudoVSUXEI16_V_M8_M8 = 11959 + + PseudoVSUXEI16_V_M8_M8_MASK = 11960 + + PseudoVSUXEI16_V_MF2_M1 = 11961 + + PseudoVSUXEI16_V_MF2_M1_MASK = 11962 + + PseudoVSUXEI16_V_MF2_M2 = 11963 + + PseudoVSUXEI16_V_MF2_M2_MASK = 11964 + + PseudoVSUXEI16_V_MF2_MF2 = 11965 + + PseudoVSUXEI16_V_MF2_MF2_MASK = 11966 + + PseudoVSUXEI16_V_MF2_MF4 = 11967 + + PseudoVSUXEI16_V_MF2_MF4_MASK = 11968 + + PseudoVSUXEI16_V_MF4_M1 = 11969 + + PseudoVSUXEI16_V_MF4_M1_MASK = 11970 + + PseudoVSUXEI16_V_MF4_MF2 = 11971 + + PseudoVSUXEI16_V_MF4_MF2_MASK = 11972 + + PseudoVSUXEI16_V_MF4_MF4 = 11973 + + PseudoVSUXEI16_V_MF4_MF4_MASK = 11974 + + PseudoVSUXEI16_V_MF4_MF8 = 11975 + + PseudoVSUXEI16_V_MF4_MF8_MASK = 11976 + + PseudoVSUXEI32_V_M1_M1 = 11977 + + PseudoVSUXEI32_V_M1_M1_MASK = 11978 + + PseudoVSUXEI32_V_M1_M2 = 11979 + + PseudoVSUXEI32_V_M1_M2_MASK = 11980 + + PseudoVSUXEI32_V_M1_MF2 = 11981 + + PseudoVSUXEI32_V_M1_MF2_MASK = 11982 + + PseudoVSUXEI32_V_M1_MF4 = 11983 + + PseudoVSUXEI32_V_M1_MF4_MASK = 11984 + + PseudoVSUXEI32_V_M2_M1 = 11985 + + PseudoVSUXEI32_V_M2_M1_MASK = 11986 + + PseudoVSUXEI32_V_M2_M2 = 11987 + + PseudoVSUXEI32_V_M2_M2_MASK = 11988 + + PseudoVSUXEI32_V_M2_M4 = 11989 + + PseudoVSUXEI32_V_M2_M4_MASK = 11990 + + PseudoVSUXEI32_V_M2_MF2 = 11991 + + PseudoVSUXEI32_V_M2_MF2_MASK = 11992 + + PseudoVSUXEI32_V_M4_M1 = 11993 + + PseudoVSUXEI32_V_M4_M1_MASK = 11994 + + PseudoVSUXEI32_V_M4_M2 = 11995 + + PseudoVSUXEI32_V_M4_M2_MASK = 11996 + + PseudoVSUXEI32_V_M4_M4 = 11997 + + PseudoVSUXEI32_V_M4_M4_MASK = 11998 + + PseudoVSUXEI32_V_M4_M8 = 11999 + + PseudoVSUXEI32_V_M4_M8_MASK = 12000 + + PseudoVSUXEI32_V_M8_M2 = 12001 + + PseudoVSUXEI32_V_M8_M2_MASK = 12002 + + PseudoVSUXEI32_V_M8_M4 = 12003 + + PseudoVSUXEI32_V_M8_M4_MASK = 12004 + + PseudoVSUXEI32_V_M8_M8 = 12005 + + PseudoVSUXEI32_V_M8_M8_MASK = 12006 + + PseudoVSUXEI32_V_MF2_M1 = 12007 + + PseudoVSUXEI32_V_MF2_M1_MASK = 12008 + + PseudoVSUXEI32_V_MF2_MF2 = 12009 + + PseudoVSUXEI32_V_MF2_MF2_MASK = 12010 + + PseudoVSUXEI32_V_MF2_MF4 = 12011 + + PseudoVSUXEI32_V_MF2_MF4_MASK = 12012 + + PseudoVSUXEI32_V_MF2_MF8 = 12013 + + PseudoVSUXEI32_V_MF2_MF8_MASK = 12014 + + PseudoVSUXEI64_V_M1_M1 = 12015 + + PseudoVSUXEI64_V_M1_M1_MASK = 12016 + + PseudoVSUXEI64_V_M1_MF2 = 12017 + + PseudoVSUXEI64_V_M1_MF2_MASK = 12018 + + PseudoVSUXEI64_V_M1_MF4 = 12019 + + PseudoVSUXEI64_V_M1_MF4_MASK = 12020 + + PseudoVSUXEI64_V_M1_MF8 = 12021 + + PseudoVSUXEI64_V_M1_MF8_MASK = 12022 + + PseudoVSUXEI64_V_M2_M1 = 12023 + + PseudoVSUXEI64_V_M2_M1_MASK = 12024 + + PseudoVSUXEI64_V_M2_M2 = 12025 + + PseudoVSUXEI64_V_M2_M2_MASK = 12026 + + PseudoVSUXEI64_V_M2_MF2 = 12027 + + PseudoVSUXEI64_V_M2_MF2_MASK = 12028 + + PseudoVSUXEI64_V_M2_MF4 = 12029 + + PseudoVSUXEI64_V_M2_MF4_MASK = 12030 + + PseudoVSUXEI64_V_M4_M1 = 12031 + + PseudoVSUXEI64_V_M4_M1_MASK = 12032 + + PseudoVSUXEI64_V_M4_M2 = 12033 + + PseudoVSUXEI64_V_M4_M2_MASK = 12034 + + PseudoVSUXEI64_V_M4_M4 = 12035 + + PseudoVSUXEI64_V_M4_M4_MASK = 12036 + + PseudoVSUXEI64_V_M4_MF2 = 12037 + + PseudoVSUXEI64_V_M4_MF2_MASK = 12038 + + PseudoVSUXEI64_V_M8_M1 = 12039 + + PseudoVSUXEI64_V_M8_M1_MASK = 12040 + + PseudoVSUXEI64_V_M8_M2 = 12041 + + PseudoVSUXEI64_V_M8_M2_MASK = 12042 + + PseudoVSUXEI64_V_M8_M4 = 12043 + + PseudoVSUXEI64_V_M8_M4_MASK = 12044 + + PseudoVSUXEI64_V_M8_M8 = 12045 + + PseudoVSUXEI64_V_M8_M8_MASK = 12046 + + PseudoVSUXEI8_V_M1_M1 = 12047 + + PseudoVSUXEI8_V_M1_M1_MASK = 12048 + + PseudoVSUXEI8_V_M1_M2 = 12049 + + PseudoVSUXEI8_V_M1_M2_MASK = 12050 + + PseudoVSUXEI8_V_M1_M4 = 12051 + + PseudoVSUXEI8_V_M1_M4_MASK = 12052 + + PseudoVSUXEI8_V_M1_M8 = 12053 + + PseudoVSUXEI8_V_M1_M8_MASK = 12054 + + PseudoVSUXEI8_V_M2_M2 = 12055 + + PseudoVSUXEI8_V_M2_M2_MASK = 12056 + + PseudoVSUXEI8_V_M2_M4 = 12057 + + PseudoVSUXEI8_V_M2_M4_MASK = 12058 + + PseudoVSUXEI8_V_M2_M8 = 12059 + + PseudoVSUXEI8_V_M2_M8_MASK = 12060 + + PseudoVSUXEI8_V_M4_M4 = 12061 + + PseudoVSUXEI8_V_M4_M4_MASK = 12062 + + PseudoVSUXEI8_V_M4_M8 = 12063 + + PseudoVSUXEI8_V_M4_M8_MASK = 12064 + + PseudoVSUXEI8_V_M8_M8 = 12065 + + PseudoVSUXEI8_V_M8_M8_MASK = 12066 + + PseudoVSUXEI8_V_MF2_M1 = 12067 + + PseudoVSUXEI8_V_MF2_M1_MASK = 12068 + + PseudoVSUXEI8_V_MF2_M2 = 12069 + + PseudoVSUXEI8_V_MF2_M2_MASK = 12070 + + PseudoVSUXEI8_V_MF2_M4 = 12071 + + PseudoVSUXEI8_V_MF2_M4_MASK = 12072 + + PseudoVSUXEI8_V_MF2_MF2 = 12073 + + PseudoVSUXEI8_V_MF2_MF2_MASK = 12074 + + PseudoVSUXEI8_V_MF4_M1 = 12075 + + PseudoVSUXEI8_V_MF4_M1_MASK = 12076 + + PseudoVSUXEI8_V_MF4_M2 = 12077 + + PseudoVSUXEI8_V_MF4_M2_MASK = 12078 + + PseudoVSUXEI8_V_MF4_MF2 = 12079 + + PseudoVSUXEI8_V_MF4_MF2_MASK = 12080 + + PseudoVSUXEI8_V_MF4_MF4 = 12081 + + PseudoVSUXEI8_V_MF4_MF4_MASK = 12082 + + PseudoVSUXEI8_V_MF8_M1 = 12083 + + PseudoVSUXEI8_V_MF8_M1_MASK = 12084 + + PseudoVSUXEI8_V_MF8_MF2 = 12085 + + PseudoVSUXEI8_V_MF8_MF2_MASK = 12086 + + PseudoVSUXEI8_V_MF8_MF4 = 12087 + + PseudoVSUXEI8_V_MF8_MF4_MASK = 12088 + + PseudoVSUXEI8_V_MF8_MF8 = 12089 + + PseudoVSUXEI8_V_MF8_MF8_MASK = 12090 + + PseudoVSUXSEG2EI16_V_M1_M1 = 12091 + + PseudoVSUXSEG2EI16_V_M1_M1_MASK = 12092 + + PseudoVSUXSEG2EI16_V_M1_M2 = 12093 + + PseudoVSUXSEG2EI16_V_M1_M2_MASK = 12094 + + PseudoVSUXSEG2EI16_V_M1_M4 = 12095 + + PseudoVSUXSEG2EI16_V_M1_M4_MASK = 12096 + + PseudoVSUXSEG2EI16_V_M1_MF2 = 12097 + + PseudoVSUXSEG2EI16_V_M1_MF2_MASK = 12098 + + PseudoVSUXSEG2EI16_V_M2_M1 = 12099 + + PseudoVSUXSEG2EI16_V_M2_M1_MASK = 12100 + + PseudoVSUXSEG2EI16_V_M2_M2 = 12101 + + PseudoVSUXSEG2EI16_V_M2_M2_MASK = 12102 + + PseudoVSUXSEG2EI16_V_M2_M4 = 12103 + + PseudoVSUXSEG2EI16_V_M2_M4_MASK = 12104 + + PseudoVSUXSEG2EI16_V_M4_M2 = 12105 + + PseudoVSUXSEG2EI16_V_M4_M2_MASK = 12106 + + PseudoVSUXSEG2EI16_V_M4_M4 = 12107 + + PseudoVSUXSEG2EI16_V_M4_M4_MASK = 12108 + + PseudoVSUXSEG2EI16_V_M8_M4 = 12109 + + PseudoVSUXSEG2EI16_V_M8_M4_MASK = 12110 + + PseudoVSUXSEG2EI16_V_MF2_M1 = 12111 + + PseudoVSUXSEG2EI16_V_MF2_M1_MASK = 12112 + + PseudoVSUXSEG2EI16_V_MF2_M2 = 12113 + + PseudoVSUXSEG2EI16_V_MF2_M2_MASK = 12114 + + PseudoVSUXSEG2EI16_V_MF2_MF2 = 12115 + + PseudoVSUXSEG2EI16_V_MF2_MF2_MASK = 12116 + + PseudoVSUXSEG2EI16_V_MF2_MF4 = 12117 + + PseudoVSUXSEG2EI16_V_MF2_MF4_MASK = 12118 + + PseudoVSUXSEG2EI16_V_MF4_M1 = 12119 + + PseudoVSUXSEG2EI16_V_MF4_M1_MASK = 12120 + + PseudoVSUXSEG2EI16_V_MF4_MF2 = 12121 + + PseudoVSUXSEG2EI16_V_MF4_MF2_MASK = 12122 + + PseudoVSUXSEG2EI16_V_MF4_MF4 = 12123 + + PseudoVSUXSEG2EI16_V_MF4_MF4_MASK = 12124 + + PseudoVSUXSEG2EI16_V_MF4_MF8 = 12125 + + PseudoVSUXSEG2EI16_V_MF4_MF8_MASK = 12126 + + PseudoVSUXSEG2EI32_V_M1_M1 = 12127 + + PseudoVSUXSEG2EI32_V_M1_M1_MASK = 12128 + + PseudoVSUXSEG2EI32_V_M1_M2 = 12129 + + PseudoVSUXSEG2EI32_V_M1_M2_MASK = 12130 + + PseudoVSUXSEG2EI32_V_M1_MF2 = 12131 + + PseudoVSUXSEG2EI32_V_M1_MF2_MASK = 12132 + + PseudoVSUXSEG2EI32_V_M1_MF4 = 12133 + + PseudoVSUXSEG2EI32_V_M1_MF4_MASK = 12134 + + PseudoVSUXSEG2EI32_V_M2_M1 = 12135 + + PseudoVSUXSEG2EI32_V_M2_M1_MASK = 12136 + + PseudoVSUXSEG2EI32_V_M2_M2 = 12137 + + PseudoVSUXSEG2EI32_V_M2_M2_MASK = 12138 + + PseudoVSUXSEG2EI32_V_M2_M4 = 12139 + + PseudoVSUXSEG2EI32_V_M2_M4_MASK = 12140 + + PseudoVSUXSEG2EI32_V_M2_MF2 = 12141 + + PseudoVSUXSEG2EI32_V_M2_MF2_MASK = 12142 + + PseudoVSUXSEG2EI32_V_M4_M1 = 12143 + + PseudoVSUXSEG2EI32_V_M4_M1_MASK = 12144 + + PseudoVSUXSEG2EI32_V_M4_M2 = 12145 + + PseudoVSUXSEG2EI32_V_M4_M2_MASK = 12146 + + PseudoVSUXSEG2EI32_V_M4_M4 = 12147 + + PseudoVSUXSEG2EI32_V_M4_M4_MASK = 12148 + + PseudoVSUXSEG2EI32_V_M8_M2 = 12149 + + PseudoVSUXSEG2EI32_V_M8_M2_MASK = 12150 + + PseudoVSUXSEG2EI32_V_M8_M4 = 12151 + + PseudoVSUXSEG2EI32_V_M8_M4_MASK = 12152 + + PseudoVSUXSEG2EI32_V_MF2_M1 = 12153 + + PseudoVSUXSEG2EI32_V_MF2_M1_MASK = 12154 + + PseudoVSUXSEG2EI32_V_MF2_MF2 = 12155 + + PseudoVSUXSEG2EI32_V_MF2_MF2_MASK = 12156 + + PseudoVSUXSEG2EI32_V_MF2_MF4 = 12157 + + PseudoVSUXSEG2EI32_V_MF2_MF4_MASK = 12158 + + PseudoVSUXSEG2EI32_V_MF2_MF8 = 12159 + + PseudoVSUXSEG2EI32_V_MF2_MF8_MASK = 12160 + + PseudoVSUXSEG2EI64_V_M1_M1 = 12161 + + PseudoVSUXSEG2EI64_V_M1_M1_MASK = 12162 + + PseudoVSUXSEG2EI64_V_M1_MF2 = 12163 + + PseudoVSUXSEG2EI64_V_M1_MF2_MASK = 12164 + + PseudoVSUXSEG2EI64_V_M1_MF4 = 12165 + + PseudoVSUXSEG2EI64_V_M1_MF4_MASK = 12166 + + PseudoVSUXSEG2EI64_V_M1_MF8 = 12167 + + PseudoVSUXSEG2EI64_V_M1_MF8_MASK = 12168 + + PseudoVSUXSEG2EI64_V_M2_M1 = 12169 + + PseudoVSUXSEG2EI64_V_M2_M1_MASK = 12170 + + PseudoVSUXSEG2EI64_V_M2_M2 = 12171 + + PseudoVSUXSEG2EI64_V_M2_M2_MASK = 12172 + + PseudoVSUXSEG2EI64_V_M2_MF2 = 12173 + + PseudoVSUXSEG2EI64_V_M2_MF2_MASK = 12174 + + PseudoVSUXSEG2EI64_V_M2_MF4 = 12175 + + PseudoVSUXSEG2EI64_V_M2_MF4_MASK = 12176 + + PseudoVSUXSEG2EI64_V_M4_M1 = 12177 + + PseudoVSUXSEG2EI64_V_M4_M1_MASK = 12178 + + PseudoVSUXSEG2EI64_V_M4_M2 = 12179 + + PseudoVSUXSEG2EI64_V_M4_M2_MASK = 12180 + + PseudoVSUXSEG2EI64_V_M4_M4 = 12181 + + PseudoVSUXSEG2EI64_V_M4_M4_MASK = 12182 + + PseudoVSUXSEG2EI64_V_M4_MF2 = 12183 + + PseudoVSUXSEG2EI64_V_M4_MF2_MASK = 12184 + + PseudoVSUXSEG2EI64_V_M8_M1 = 12185 + + PseudoVSUXSEG2EI64_V_M8_M1_MASK = 12186 + + PseudoVSUXSEG2EI64_V_M8_M2 = 12187 + + PseudoVSUXSEG2EI64_V_M8_M2_MASK = 12188 + + PseudoVSUXSEG2EI64_V_M8_M4 = 12189 + + PseudoVSUXSEG2EI64_V_M8_M4_MASK = 12190 + + PseudoVSUXSEG2EI8_V_M1_M1 = 12191 + + PseudoVSUXSEG2EI8_V_M1_M1_MASK = 12192 + + PseudoVSUXSEG2EI8_V_M1_M2 = 12193 + + PseudoVSUXSEG2EI8_V_M1_M2_MASK = 12194 + + PseudoVSUXSEG2EI8_V_M1_M4 = 12195 + + PseudoVSUXSEG2EI8_V_M1_M4_MASK = 12196 + + PseudoVSUXSEG2EI8_V_M2_M2 = 12197 + + PseudoVSUXSEG2EI8_V_M2_M2_MASK = 12198 + + PseudoVSUXSEG2EI8_V_M2_M4 = 12199 + + PseudoVSUXSEG2EI8_V_M2_M4_MASK = 12200 + + PseudoVSUXSEG2EI8_V_M4_M4 = 12201 + + PseudoVSUXSEG2EI8_V_M4_M4_MASK = 12202 + + PseudoVSUXSEG2EI8_V_MF2_M1 = 12203 + + PseudoVSUXSEG2EI8_V_MF2_M1_MASK = 12204 + + PseudoVSUXSEG2EI8_V_MF2_M2 = 12205 + + PseudoVSUXSEG2EI8_V_MF2_M2_MASK = 12206 + + PseudoVSUXSEG2EI8_V_MF2_M4 = 12207 + + PseudoVSUXSEG2EI8_V_MF2_M4_MASK = 12208 + + PseudoVSUXSEG2EI8_V_MF2_MF2 = 12209 + + PseudoVSUXSEG2EI8_V_MF2_MF2_MASK = 12210 + + PseudoVSUXSEG2EI8_V_MF4_M1 = 12211 + + PseudoVSUXSEG2EI8_V_MF4_M1_MASK = 12212 + + PseudoVSUXSEG2EI8_V_MF4_M2 = 12213 + + PseudoVSUXSEG2EI8_V_MF4_M2_MASK = 12214 + + PseudoVSUXSEG2EI8_V_MF4_MF2 = 12215 + + PseudoVSUXSEG2EI8_V_MF4_MF2_MASK = 12216 + + PseudoVSUXSEG2EI8_V_MF4_MF4 = 12217 + + PseudoVSUXSEG2EI8_V_MF4_MF4_MASK = 12218 + + PseudoVSUXSEG2EI8_V_MF8_M1 = 12219 + + PseudoVSUXSEG2EI8_V_MF8_M1_MASK = 12220 + + PseudoVSUXSEG2EI8_V_MF8_MF2 = 12221 + + PseudoVSUXSEG2EI8_V_MF8_MF2_MASK = 12222 + + PseudoVSUXSEG2EI8_V_MF8_MF4 = 12223 + + PseudoVSUXSEG2EI8_V_MF8_MF4_MASK = 12224 + + PseudoVSUXSEG2EI8_V_MF8_MF8 = 12225 + + PseudoVSUXSEG2EI8_V_MF8_MF8_MASK = 12226 + + PseudoVSUXSEG3EI16_V_M1_M1 = 12227 + + PseudoVSUXSEG3EI16_V_M1_M1_MASK = 12228 + + PseudoVSUXSEG3EI16_V_M1_M2 = 12229 + + PseudoVSUXSEG3EI16_V_M1_M2_MASK = 12230 + + PseudoVSUXSEG3EI16_V_M1_MF2 = 12231 + + PseudoVSUXSEG3EI16_V_M1_MF2_MASK = 12232 + + PseudoVSUXSEG3EI16_V_M2_M1 = 12233 + + PseudoVSUXSEG3EI16_V_M2_M1_MASK = 12234 + + PseudoVSUXSEG3EI16_V_M2_M2 = 12235 + + PseudoVSUXSEG3EI16_V_M2_M2_MASK = 12236 + + PseudoVSUXSEG3EI16_V_M4_M2 = 12237 + + PseudoVSUXSEG3EI16_V_M4_M2_MASK = 12238 + + PseudoVSUXSEG3EI16_V_MF2_M1 = 12239 + + PseudoVSUXSEG3EI16_V_MF2_M1_MASK = 12240 + + PseudoVSUXSEG3EI16_V_MF2_M2 = 12241 + + PseudoVSUXSEG3EI16_V_MF2_M2_MASK = 12242 + + PseudoVSUXSEG3EI16_V_MF2_MF2 = 12243 + + PseudoVSUXSEG3EI16_V_MF2_MF2_MASK = 12244 + + PseudoVSUXSEG3EI16_V_MF2_MF4 = 12245 + + PseudoVSUXSEG3EI16_V_MF2_MF4_MASK = 12246 + + PseudoVSUXSEG3EI16_V_MF4_M1 = 12247 + + PseudoVSUXSEG3EI16_V_MF4_M1_MASK = 12248 + + PseudoVSUXSEG3EI16_V_MF4_MF2 = 12249 + + PseudoVSUXSEG3EI16_V_MF4_MF2_MASK = 12250 + + PseudoVSUXSEG3EI16_V_MF4_MF4 = 12251 + + PseudoVSUXSEG3EI16_V_MF4_MF4_MASK = 12252 + + PseudoVSUXSEG3EI16_V_MF4_MF8 = 12253 + + PseudoVSUXSEG3EI16_V_MF4_MF8_MASK = 12254 + + PseudoVSUXSEG3EI32_V_M1_M1 = 12255 + + PseudoVSUXSEG3EI32_V_M1_M1_MASK = 12256 + + PseudoVSUXSEG3EI32_V_M1_M2 = 12257 + + PseudoVSUXSEG3EI32_V_M1_M2_MASK = 12258 + + PseudoVSUXSEG3EI32_V_M1_MF2 = 12259 + + PseudoVSUXSEG3EI32_V_M1_MF2_MASK = 12260 + + PseudoVSUXSEG3EI32_V_M1_MF4 = 12261 + + PseudoVSUXSEG3EI32_V_M1_MF4_MASK = 12262 + + PseudoVSUXSEG3EI32_V_M2_M1 = 12263 + + PseudoVSUXSEG3EI32_V_M2_M1_MASK = 12264 + + PseudoVSUXSEG3EI32_V_M2_M2 = 12265 + + PseudoVSUXSEG3EI32_V_M2_M2_MASK = 12266 + + PseudoVSUXSEG3EI32_V_M2_MF2 = 12267 + + PseudoVSUXSEG3EI32_V_M2_MF2_MASK = 12268 + + PseudoVSUXSEG3EI32_V_M4_M1 = 12269 + + PseudoVSUXSEG3EI32_V_M4_M1_MASK = 12270 + + PseudoVSUXSEG3EI32_V_M4_M2 = 12271 + + PseudoVSUXSEG3EI32_V_M4_M2_MASK = 12272 + + PseudoVSUXSEG3EI32_V_M8_M2 = 12273 + + PseudoVSUXSEG3EI32_V_M8_M2_MASK = 12274 + + PseudoVSUXSEG3EI32_V_MF2_M1 = 12275 + + PseudoVSUXSEG3EI32_V_MF2_M1_MASK = 12276 + + PseudoVSUXSEG3EI32_V_MF2_MF2 = 12277 + + PseudoVSUXSEG3EI32_V_MF2_MF2_MASK = 12278 + + PseudoVSUXSEG3EI32_V_MF2_MF4 = 12279 + + PseudoVSUXSEG3EI32_V_MF2_MF4_MASK = 12280 + + PseudoVSUXSEG3EI32_V_MF2_MF8 = 12281 + + PseudoVSUXSEG3EI32_V_MF2_MF8_MASK = 12282 + + PseudoVSUXSEG3EI64_V_M1_M1 = 12283 + + PseudoVSUXSEG3EI64_V_M1_M1_MASK = 12284 + + PseudoVSUXSEG3EI64_V_M1_MF2 = 12285 + + PseudoVSUXSEG3EI64_V_M1_MF2_MASK = 12286 + + PseudoVSUXSEG3EI64_V_M1_MF4 = 12287 + + PseudoVSUXSEG3EI64_V_M1_MF4_MASK = 12288 + + PseudoVSUXSEG3EI64_V_M1_MF8 = 12289 + + PseudoVSUXSEG3EI64_V_M1_MF8_MASK = 12290 + + PseudoVSUXSEG3EI64_V_M2_M1 = 12291 + + PseudoVSUXSEG3EI64_V_M2_M1_MASK = 12292 + + PseudoVSUXSEG3EI64_V_M2_M2 = 12293 + + PseudoVSUXSEG3EI64_V_M2_M2_MASK = 12294 + + PseudoVSUXSEG3EI64_V_M2_MF2 = 12295 + + PseudoVSUXSEG3EI64_V_M2_MF2_MASK = 12296 + + PseudoVSUXSEG3EI64_V_M2_MF4 = 12297 + + PseudoVSUXSEG3EI64_V_M2_MF4_MASK = 12298 + + PseudoVSUXSEG3EI64_V_M4_M1 = 12299 + + PseudoVSUXSEG3EI64_V_M4_M1_MASK = 12300 + + PseudoVSUXSEG3EI64_V_M4_M2 = 12301 + + PseudoVSUXSEG3EI64_V_M4_M2_MASK = 12302 + + PseudoVSUXSEG3EI64_V_M4_MF2 = 12303 + + PseudoVSUXSEG3EI64_V_M4_MF2_MASK = 12304 + + PseudoVSUXSEG3EI64_V_M8_M1 = 12305 + + PseudoVSUXSEG3EI64_V_M8_M1_MASK = 12306 + + PseudoVSUXSEG3EI64_V_M8_M2 = 12307 + + PseudoVSUXSEG3EI64_V_M8_M2_MASK = 12308 + + PseudoVSUXSEG3EI8_V_M1_M1 = 12309 + + PseudoVSUXSEG3EI8_V_M1_M1_MASK = 12310 + + PseudoVSUXSEG3EI8_V_M1_M2 = 12311 + + PseudoVSUXSEG3EI8_V_M1_M2_MASK = 12312 + + PseudoVSUXSEG3EI8_V_M2_M2 = 12313 + + PseudoVSUXSEG3EI8_V_M2_M2_MASK = 12314 + + PseudoVSUXSEG3EI8_V_MF2_M1 = 12315 + + PseudoVSUXSEG3EI8_V_MF2_M1_MASK = 12316 + + PseudoVSUXSEG3EI8_V_MF2_M2 = 12317 + + PseudoVSUXSEG3EI8_V_MF2_M2_MASK = 12318 + + PseudoVSUXSEG3EI8_V_MF2_MF2 = 12319 + + PseudoVSUXSEG3EI8_V_MF2_MF2_MASK = 12320 + + PseudoVSUXSEG3EI8_V_MF4_M1 = 12321 + + PseudoVSUXSEG3EI8_V_MF4_M1_MASK = 12322 + + PseudoVSUXSEG3EI8_V_MF4_M2 = 12323 + + PseudoVSUXSEG3EI8_V_MF4_M2_MASK = 12324 + + PseudoVSUXSEG3EI8_V_MF4_MF2 = 12325 + + PseudoVSUXSEG3EI8_V_MF4_MF2_MASK = 12326 + + PseudoVSUXSEG3EI8_V_MF4_MF4 = 12327 + + PseudoVSUXSEG3EI8_V_MF4_MF4_MASK = 12328 + + PseudoVSUXSEG3EI8_V_MF8_M1 = 12329 + + PseudoVSUXSEG3EI8_V_MF8_M1_MASK = 12330 + + PseudoVSUXSEG3EI8_V_MF8_MF2 = 12331 + + PseudoVSUXSEG3EI8_V_MF8_MF2_MASK = 12332 + + PseudoVSUXSEG3EI8_V_MF8_MF4 = 12333 + + PseudoVSUXSEG3EI8_V_MF8_MF4_MASK = 12334 + + PseudoVSUXSEG3EI8_V_MF8_MF8 = 12335 + + PseudoVSUXSEG3EI8_V_MF8_MF8_MASK = 12336 + + PseudoVSUXSEG4EI16_V_M1_M1 = 12337 + + PseudoVSUXSEG4EI16_V_M1_M1_MASK = 12338 + + PseudoVSUXSEG4EI16_V_M1_M2 = 12339 + + PseudoVSUXSEG4EI16_V_M1_M2_MASK = 12340 + + PseudoVSUXSEG4EI16_V_M1_MF2 = 12341 + + PseudoVSUXSEG4EI16_V_M1_MF2_MASK = 12342 + + PseudoVSUXSEG4EI16_V_M2_M1 = 12343 + + PseudoVSUXSEG4EI16_V_M2_M1_MASK = 12344 + + PseudoVSUXSEG4EI16_V_M2_M2 = 12345 + + PseudoVSUXSEG4EI16_V_M2_M2_MASK = 12346 + + PseudoVSUXSEG4EI16_V_M4_M2 = 12347 + + PseudoVSUXSEG4EI16_V_M4_M2_MASK = 12348 + + PseudoVSUXSEG4EI16_V_MF2_M1 = 12349 + + PseudoVSUXSEG4EI16_V_MF2_M1_MASK = 12350 + + PseudoVSUXSEG4EI16_V_MF2_M2 = 12351 + + PseudoVSUXSEG4EI16_V_MF2_M2_MASK = 12352 + + PseudoVSUXSEG4EI16_V_MF2_MF2 = 12353 + + PseudoVSUXSEG4EI16_V_MF2_MF2_MASK = 12354 + + PseudoVSUXSEG4EI16_V_MF2_MF4 = 12355 + + PseudoVSUXSEG4EI16_V_MF2_MF4_MASK = 12356 + + PseudoVSUXSEG4EI16_V_MF4_M1 = 12357 + + PseudoVSUXSEG4EI16_V_MF4_M1_MASK = 12358 + + PseudoVSUXSEG4EI16_V_MF4_MF2 = 12359 + + PseudoVSUXSEG4EI16_V_MF4_MF2_MASK = 12360 + + PseudoVSUXSEG4EI16_V_MF4_MF4 = 12361 + + PseudoVSUXSEG4EI16_V_MF4_MF4_MASK = 12362 + + PseudoVSUXSEG4EI16_V_MF4_MF8 = 12363 + + PseudoVSUXSEG4EI16_V_MF4_MF8_MASK = 12364 + + PseudoVSUXSEG4EI32_V_M1_M1 = 12365 + + PseudoVSUXSEG4EI32_V_M1_M1_MASK = 12366 + + PseudoVSUXSEG4EI32_V_M1_M2 = 12367 + + PseudoVSUXSEG4EI32_V_M1_M2_MASK = 12368 + + PseudoVSUXSEG4EI32_V_M1_MF2 = 12369 + + PseudoVSUXSEG4EI32_V_M1_MF2_MASK = 12370 + + PseudoVSUXSEG4EI32_V_M1_MF4 = 12371 + + PseudoVSUXSEG4EI32_V_M1_MF4_MASK = 12372 + + PseudoVSUXSEG4EI32_V_M2_M1 = 12373 + + PseudoVSUXSEG4EI32_V_M2_M1_MASK = 12374 + + PseudoVSUXSEG4EI32_V_M2_M2 = 12375 + + PseudoVSUXSEG4EI32_V_M2_M2_MASK = 12376 + + PseudoVSUXSEG4EI32_V_M2_MF2 = 12377 + + PseudoVSUXSEG4EI32_V_M2_MF2_MASK = 12378 + + PseudoVSUXSEG4EI32_V_M4_M1 = 12379 + + PseudoVSUXSEG4EI32_V_M4_M1_MASK = 12380 + + PseudoVSUXSEG4EI32_V_M4_M2 = 12381 + + PseudoVSUXSEG4EI32_V_M4_M2_MASK = 12382 + + PseudoVSUXSEG4EI32_V_M8_M2 = 12383 + + PseudoVSUXSEG4EI32_V_M8_M2_MASK = 12384 + + PseudoVSUXSEG4EI32_V_MF2_M1 = 12385 + + PseudoVSUXSEG4EI32_V_MF2_M1_MASK = 12386 + + PseudoVSUXSEG4EI32_V_MF2_MF2 = 12387 + + PseudoVSUXSEG4EI32_V_MF2_MF2_MASK = 12388 + + PseudoVSUXSEG4EI32_V_MF2_MF4 = 12389 + + PseudoVSUXSEG4EI32_V_MF2_MF4_MASK = 12390 + + PseudoVSUXSEG4EI32_V_MF2_MF8 = 12391 + + PseudoVSUXSEG4EI32_V_MF2_MF8_MASK = 12392 + + PseudoVSUXSEG4EI64_V_M1_M1 = 12393 + + PseudoVSUXSEG4EI64_V_M1_M1_MASK = 12394 + + PseudoVSUXSEG4EI64_V_M1_MF2 = 12395 + + PseudoVSUXSEG4EI64_V_M1_MF2_MASK = 12396 + + PseudoVSUXSEG4EI64_V_M1_MF4 = 12397 + + PseudoVSUXSEG4EI64_V_M1_MF4_MASK = 12398 + + PseudoVSUXSEG4EI64_V_M1_MF8 = 12399 + + PseudoVSUXSEG4EI64_V_M1_MF8_MASK = 12400 + + PseudoVSUXSEG4EI64_V_M2_M1 = 12401 + + PseudoVSUXSEG4EI64_V_M2_M1_MASK = 12402 + + PseudoVSUXSEG4EI64_V_M2_M2 = 12403 + + PseudoVSUXSEG4EI64_V_M2_M2_MASK = 12404 + + PseudoVSUXSEG4EI64_V_M2_MF2 = 12405 + + PseudoVSUXSEG4EI64_V_M2_MF2_MASK = 12406 + + PseudoVSUXSEG4EI64_V_M2_MF4 = 12407 + + PseudoVSUXSEG4EI64_V_M2_MF4_MASK = 12408 + + PseudoVSUXSEG4EI64_V_M4_M1 = 12409 + + PseudoVSUXSEG4EI64_V_M4_M1_MASK = 12410 + + PseudoVSUXSEG4EI64_V_M4_M2 = 12411 + + PseudoVSUXSEG4EI64_V_M4_M2_MASK = 12412 + + PseudoVSUXSEG4EI64_V_M4_MF2 = 12413 + + PseudoVSUXSEG4EI64_V_M4_MF2_MASK = 12414 + + PseudoVSUXSEG4EI64_V_M8_M1 = 12415 + + PseudoVSUXSEG4EI64_V_M8_M1_MASK = 12416 + + PseudoVSUXSEG4EI64_V_M8_M2 = 12417 + + PseudoVSUXSEG4EI64_V_M8_M2_MASK = 12418 + + PseudoVSUXSEG4EI8_V_M1_M1 = 12419 + + PseudoVSUXSEG4EI8_V_M1_M1_MASK = 12420 + + PseudoVSUXSEG4EI8_V_M1_M2 = 12421 + + PseudoVSUXSEG4EI8_V_M1_M2_MASK = 12422 + + PseudoVSUXSEG4EI8_V_M2_M2 = 12423 + + PseudoVSUXSEG4EI8_V_M2_M2_MASK = 12424 + + PseudoVSUXSEG4EI8_V_MF2_M1 = 12425 + + PseudoVSUXSEG4EI8_V_MF2_M1_MASK = 12426 + + PseudoVSUXSEG4EI8_V_MF2_M2 = 12427 + + PseudoVSUXSEG4EI8_V_MF2_M2_MASK = 12428 + + PseudoVSUXSEG4EI8_V_MF2_MF2 = 12429 + + PseudoVSUXSEG4EI8_V_MF2_MF2_MASK = 12430 + + PseudoVSUXSEG4EI8_V_MF4_M1 = 12431 + + PseudoVSUXSEG4EI8_V_MF4_M1_MASK = 12432 + + PseudoVSUXSEG4EI8_V_MF4_M2 = 12433 + + PseudoVSUXSEG4EI8_V_MF4_M2_MASK = 12434 + + PseudoVSUXSEG4EI8_V_MF4_MF2 = 12435 + + PseudoVSUXSEG4EI8_V_MF4_MF2_MASK = 12436 + + PseudoVSUXSEG4EI8_V_MF4_MF4 = 12437 + + PseudoVSUXSEG4EI8_V_MF4_MF4_MASK = 12438 + + PseudoVSUXSEG4EI8_V_MF8_M1 = 12439 + + PseudoVSUXSEG4EI8_V_MF8_M1_MASK = 12440 + + PseudoVSUXSEG4EI8_V_MF8_MF2 = 12441 + + PseudoVSUXSEG4EI8_V_MF8_MF2_MASK = 12442 + + PseudoVSUXSEG4EI8_V_MF8_MF4 = 12443 + + PseudoVSUXSEG4EI8_V_MF8_MF4_MASK = 12444 + + PseudoVSUXSEG4EI8_V_MF8_MF8 = 12445 + + PseudoVSUXSEG4EI8_V_MF8_MF8_MASK = 12446 + + PseudoVSUXSEG5EI16_V_M1_M1 = 12447 + + PseudoVSUXSEG5EI16_V_M1_M1_MASK = 12448 + + PseudoVSUXSEG5EI16_V_M1_MF2 = 12449 + + PseudoVSUXSEG5EI16_V_M1_MF2_MASK = 12450 + + PseudoVSUXSEG5EI16_V_M2_M1 = 12451 + + PseudoVSUXSEG5EI16_V_M2_M1_MASK = 12452 + + PseudoVSUXSEG5EI16_V_MF2_M1 = 12453 + + PseudoVSUXSEG5EI16_V_MF2_M1_MASK = 12454 + + PseudoVSUXSEG5EI16_V_MF2_MF2 = 12455 + + PseudoVSUXSEG5EI16_V_MF2_MF2_MASK = 12456 + + PseudoVSUXSEG5EI16_V_MF2_MF4 = 12457 + + PseudoVSUXSEG5EI16_V_MF2_MF4_MASK = 12458 + + PseudoVSUXSEG5EI16_V_MF4_M1 = 12459 + + PseudoVSUXSEG5EI16_V_MF4_M1_MASK = 12460 + + PseudoVSUXSEG5EI16_V_MF4_MF2 = 12461 + + PseudoVSUXSEG5EI16_V_MF4_MF2_MASK = 12462 + + PseudoVSUXSEG5EI16_V_MF4_MF4 = 12463 + + PseudoVSUXSEG5EI16_V_MF4_MF4_MASK = 12464 + + PseudoVSUXSEG5EI16_V_MF4_MF8 = 12465 + + PseudoVSUXSEG5EI16_V_MF4_MF8_MASK = 12466 + + PseudoVSUXSEG5EI32_V_M1_M1 = 12467 + + PseudoVSUXSEG5EI32_V_M1_M1_MASK = 12468 + + PseudoVSUXSEG5EI32_V_M1_MF2 = 12469 + + PseudoVSUXSEG5EI32_V_M1_MF2_MASK = 12470 + + PseudoVSUXSEG5EI32_V_M1_MF4 = 12471 + + PseudoVSUXSEG5EI32_V_M1_MF4_MASK = 12472 + + PseudoVSUXSEG5EI32_V_M2_M1 = 12473 + + PseudoVSUXSEG5EI32_V_M2_M1_MASK = 12474 + + PseudoVSUXSEG5EI32_V_M2_MF2 = 12475 + + PseudoVSUXSEG5EI32_V_M2_MF2_MASK = 12476 + + PseudoVSUXSEG5EI32_V_M4_M1 = 12477 + + PseudoVSUXSEG5EI32_V_M4_M1_MASK = 12478 + + PseudoVSUXSEG5EI32_V_MF2_M1 = 12479 + + PseudoVSUXSEG5EI32_V_MF2_M1_MASK = 12480 + + PseudoVSUXSEG5EI32_V_MF2_MF2 = 12481 + + PseudoVSUXSEG5EI32_V_MF2_MF2_MASK = 12482 + + PseudoVSUXSEG5EI32_V_MF2_MF4 = 12483 + + PseudoVSUXSEG5EI32_V_MF2_MF4_MASK = 12484 + + PseudoVSUXSEG5EI32_V_MF2_MF8 = 12485 + + PseudoVSUXSEG5EI32_V_MF2_MF8_MASK = 12486 + + PseudoVSUXSEG5EI64_V_M1_M1 = 12487 + + PseudoVSUXSEG5EI64_V_M1_M1_MASK = 12488 + + PseudoVSUXSEG5EI64_V_M1_MF2 = 12489 + + PseudoVSUXSEG5EI64_V_M1_MF2_MASK = 12490 + + PseudoVSUXSEG5EI64_V_M1_MF4 = 12491 + + PseudoVSUXSEG5EI64_V_M1_MF4_MASK = 12492 + + PseudoVSUXSEG5EI64_V_M1_MF8 = 12493 + + PseudoVSUXSEG5EI64_V_M1_MF8_MASK = 12494 + + PseudoVSUXSEG5EI64_V_M2_M1 = 12495 + + PseudoVSUXSEG5EI64_V_M2_M1_MASK = 12496 + + PseudoVSUXSEG5EI64_V_M2_MF2 = 12497 + + PseudoVSUXSEG5EI64_V_M2_MF2_MASK = 12498 + + PseudoVSUXSEG5EI64_V_M2_MF4 = 12499 + + PseudoVSUXSEG5EI64_V_M2_MF4_MASK = 12500 + + PseudoVSUXSEG5EI64_V_M4_M1 = 12501 + + PseudoVSUXSEG5EI64_V_M4_M1_MASK = 12502 + + PseudoVSUXSEG5EI64_V_M4_MF2 = 12503 + + PseudoVSUXSEG5EI64_V_M4_MF2_MASK = 12504 + + PseudoVSUXSEG5EI64_V_M8_M1 = 12505 + + PseudoVSUXSEG5EI64_V_M8_M1_MASK = 12506 + + PseudoVSUXSEG5EI8_V_M1_M1 = 12507 + + PseudoVSUXSEG5EI8_V_M1_M1_MASK = 12508 + + PseudoVSUXSEG5EI8_V_MF2_M1 = 12509 + + PseudoVSUXSEG5EI8_V_MF2_M1_MASK = 12510 + + PseudoVSUXSEG5EI8_V_MF2_MF2 = 12511 + + PseudoVSUXSEG5EI8_V_MF2_MF2_MASK = 12512 + + PseudoVSUXSEG5EI8_V_MF4_M1 = 12513 + + PseudoVSUXSEG5EI8_V_MF4_M1_MASK = 12514 + + PseudoVSUXSEG5EI8_V_MF4_MF2 = 12515 + + PseudoVSUXSEG5EI8_V_MF4_MF2_MASK = 12516 + + PseudoVSUXSEG5EI8_V_MF4_MF4 = 12517 + + PseudoVSUXSEG5EI8_V_MF4_MF4_MASK = 12518 + + PseudoVSUXSEG5EI8_V_MF8_M1 = 12519 + + PseudoVSUXSEG5EI8_V_MF8_M1_MASK = 12520 + + PseudoVSUXSEG5EI8_V_MF8_MF2 = 12521 + + PseudoVSUXSEG5EI8_V_MF8_MF2_MASK = 12522 + + PseudoVSUXSEG5EI8_V_MF8_MF4 = 12523 + + PseudoVSUXSEG5EI8_V_MF8_MF4_MASK = 12524 + + PseudoVSUXSEG5EI8_V_MF8_MF8 = 12525 + + PseudoVSUXSEG5EI8_V_MF8_MF8_MASK = 12526 + + PseudoVSUXSEG6EI16_V_M1_M1 = 12527 + + PseudoVSUXSEG6EI16_V_M1_M1_MASK = 12528 + + PseudoVSUXSEG6EI16_V_M1_MF2 = 12529 + + PseudoVSUXSEG6EI16_V_M1_MF2_MASK = 12530 + + PseudoVSUXSEG6EI16_V_M2_M1 = 12531 + + PseudoVSUXSEG6EI16_V_M2_M1_MASK = 12532 + + PseudoVSUXSEG6EI16_V_MF2_M1 = 12533 + + PseudoVSUXSEG6EI16_V_MF2_M1_MASK = 12534 + + PseudoVSUXSEG6EI16_V_MF2_MF2 = 12535 + + PseudoVSUXSEG6EI16_V_MF2_MF2_MASK = 12536 + + PseudoVSUXSEG6EI16_V_MF2_MF4 = 12537 + + PseudoVSUXSEG6EI16_V_MF2_MF4_MASK = 12538 + + PseudoVSUXSEG6EI16_V_MF4_M1 = 12539 + + PseudoVSUXSEG6EI16_V_MF4_M1_MASK = 12540 + + PseudoVSUXSEG6EI16_V_MF4_MF2 = 12541 + + PseudoVSUXSEG6EI16_V_MF4_MF2_MASK = 12542 + + PseudoVSUXSEG6EI16_V_MF4_MF4 = 12543 + + PseudoVSUXSEG6EI16_V_MF4_MF4_MASK = 12544 + + PseudoVSUXSEG6EI16_V_MF4_MF8 = 12545 + + PseudoVSUXSEG6EI16_V_MF4_MF8_MASK = 12546 + + PseudoVSUXSEG6EI32_V_M1_M1 = 12547 + + PseudoVSUXSEG6EI32_V_M1_M1_MASK = 12548 + + PseudoVSUXSEG6EI32_V_M1_MF2 = 12549 + + PseudoVSUXSEG6EI32_V_M1_MF2_MASK = 12550 + + PseudoVSUXSEG6EI32_V_M1_MF4 = 12551 + + PseudoVSUXSEG6EI32_V_M1_MF4_MASK = 12552 + + PseudoVSUXSEG6EI32_V_M2_M1 = 12553 + + PseudoVSUXSEG6EI32_V_M2_M1_MASK = 12554 + + PseudoVSUXSEG6EI32_V_M2_MF2 = 12555 + + PseudoVSUXSEG6EI32_V_M2_MF2_MASK = 12556 + + PseudoVSUXSEG6EI32_V_M4_M1 = 12557 + + PseudoVSUXSEG6EI32_V_M4_M1_MASK = 12558 + + PseudoVSUXSEG6EI32_V_MF2_M1 = 12559 + + PseudoVSUXSEG6EI32_V_MF2_M1_MASK = 12560 + + PseudoVSUXSEG6EI32_V_MF2_MF2 = 12561 + + PseudoVSUXSEG6EI32_V_MF2_MF2_MASK = 12562 + + PseudoVSUXSEG6EI32_V_MF2_MF4 = 12563 + + PseudoVSUXSEG6EI32_V_MF2_MF4_MASK = 12564 + + PseudoVSUXSEG6EI32_V_MF2_MF8 = 12565 + + PseudoVSUXSEG6EI32_V_MF2_MF8_MASK = 12566 + + PseudoVSUXSEG6EI64_V_M1_M1 = 12567 + + PseudoVSUXSEG6EI64_V_M1_M1_MASK = 12568 + + PseudoVSUXSEG6EI64_V_M1_MF2 = 12569 + + PseudoVSUXSEG6EI64_V_M1_MF2_MASK = 12570 + + PseudoVSUXSEG6EI64_V_M1_MF4 = 12571 + + PseudoVSUXSEG6EI64_V_M1_MF4_MASK = 12572 + + PseudoVSUXSEG6EI64_V_M1_MF8 = 12573 + + PseudoVSUXSEG6EI64_V_M1_MF8_MASK = 12574 + + PseudoVSUXSEG6EI64_V_M2_M1 = 12575 + + PseudoVSUXSEG6EI64_V_M2_M1_MASK = 12576 + + PseudoVSUXSEG6EI64_V_M2_MF2 = 12577 + + PseudoVSUXSEG6EI64_V_M2_MF2_MASK = 12578 + + PseudoVSUXSEG6EI64_V_M2_MF4 = 12579 + + PseudoVSUXSEG6EI64_V_M2_MF4_MASK = 12580 + + PseudoVSUXSEG6EI64_V_M4_M1 = 12581 + + PseudoVSUXSEG6EI64_V_M4_M1_MASK = 12582 + + PseudoVSUXSEG6EI64_V_M4_MF2 = 12583 + + PseudoVSUXSEG6EI64_V_M4_MF2_MASK = 12584 + + PseudoVSUXSEG6EI64_V_M8_M1 = 12585 + + PseudoVSUXSEG6EI64_V_M8_M1_MASK = 12586 + + PseudoVSUXSEG6EI8_V_M1_M1 = 12587 + + PseudoVSUXSEG6EI8_V_M1_M1_MASK = 12588 + + PseudoVSUXSEG6EI8_V_MF2_M1 = 12589 + + PseudoVSUXSEG6EI8_V_MF2_M1_MASK = 12590 + + PseudoVSUXSEG6EI8_V_MF2_MF2 = 12591 + + PseudoVSUXSEG6EI8_V_MF2_MF2_MASK = 12592 + + PseudoVSUXSEG6EI8_V_MF4_M1 = 12593 + + PseudoVSUXSEG6EI8_V_MF4_M1_MASK = 12594 + + PseudoVSUXSEG6EI8_V_MF4_MF2 = 12595 + + PseudoVSUXSEG6EI8_V_MF4_MF2_MASK = 12596 + + PseudoVSUXSEG6EI8_V_MF4_MF4 = 12597 + + PseudoVSUXSEG6EI8_V_MF4_MF4_MASK = 12598 + + PseudoVSUXSEG6EI8_V_MF8_M1 = 12599 + + PseudoVSUXSEG6EI8_V_MF8_M1_MASK = 12600 + + PseudoVSUXSEG6EI8_V_MF8_MF2 = 12601 + + PseudoVSUXSEG6EI8_V_MF8_MF2_MASK = 12602 + + PseudoVSUXSEG6EI8_V_MF8_MF4 = 12603 + + PseudoVSUXSEG6EI8_V_MF8_MF4_MASK = 12604 + + PseudoVSUXSEG6EI8_V_MF8_MF8 = 12605 + + PseudoVSUXSEG6EI8_V_MF8_MF8_MASK = 12606 + + PseudoVSUXSEG7EI16_V_M1_M1 = 12607 + + PseudoVSUXSEG7EI16_V_M1_M1_MASK = 12608 + + PseudoVSUXSEG7EI16_V_M1_MF2 = 12609 + + PseudoVSUXSEG7EI16_V_M1_MF2_MASK = 12610 + + PseudoVSUXSEG7EI16_V_M2_M1 = 12611 + + PseudoVSUXSEG7EI16_V_M2_M1_MASK = 12612 + + PseudoVSUXSEG7EI16_V_MF2_M1 = 12613 + + PseudoVSUXSEG7EI16_V_MF2_M1_MASK = 12614 + + PseudoVSUXSEG7EI16_V_MF2_MF2 = 12615 + + PseudoVSUXSEG7EI16_V_MF2_MF2_MASK = 12616 + + PseudoVSUXSEG7EI16_V_MF2_MF4 = 12617 + + PseudoVSUXSEG7EI16_V_MF2_MF4_MASK = 12618 + + PseudoVSUXSEG7EI16_V_MF4_M1 = 12619 + + PseudoVSUXSEG7EI16_V_MF4_M1_MASK = 12620 + + PseudoVSUXSEG7EI16_V_MF4_MF2 = 12621 + + PseudoVSUXSEG7EI16_V_MF4_MF2_MASK = 12622 + + PseudoVSUXSEG7EI16_V_MF4_MF4 = 12623 + + PseudoVSUXSEG7EI16_V_MF4_MF4_MASK = 12624 + + PseudoVSUXSEG7EI16_V_MF4_MF8 = 12625 + + PseudoVSUXSEG7EI16_V_MF4_MF8_MASK = 12626 + + PseudoVSUXSEG7EI32_V_M1_M1 = 12627 + + PseudoVSUXSEG7EI32_V_M1_M1_MASK = 12628 + + PseudoVSUXSEG7EI32_V_M1_MF2 = 12629 + + PseudoVSUXSEG7EI32_V_M1_MF2_MASK = 12630 + + PseudoVSUXSEG7EI32_V_M1_MF4 = 12631 + + PseudoVSUXSEG7EI32_V_M1_MF4_MASK = 12632 + + PseudoVSUXSEG7EI32_V_M2_M1 = 12633 + + PseudoVSUXSEG7EI32_V_M2_M1_MASK = 12634 + + PseudoVSUXSEG7EI32_V_M2_MF2 = 12635 + + PseudoVSUXSEG7EI32_V_M2_MF2_MASK = 12636 + + PseudoVSUXSEG7EI32_V_M4_M1 = 12637 + + PseudoVSUXSEG7EI32_V_M4_M1_MASK = 12638 + + PseudoVSUXSEG7EI32_V_MF2_M1 = 12639 + + PseudoVSUXSEG7EI32_V_MF2_M1_MASK = 12640 + + PseudoVSUXSEG7EI32_V_MF2_MF2 = 12641 + + PseudoVSUXSEG7EI32_V_MF2_MF2_MASK = 12642 + + PseudoVSUXSEG7EI32_V_MF2_MF4 = 12643 + + PseudoVSUXSEG7EI32_V_MF2_MF4_MASK = 12644 + + PseudoVSUXSEG7EI32_V_MF2_MF8 = 12645 + + PseudoVSUXSEG7EI32_V_MF2_MF8_MASK = 12646 + + PseudoVSUXSEG7EI64_V_M1_M1 = 12647 + + PseudoVSUXSEG7EI64_V_M1_M1_MASK = 12648 + + PseudoVSUXSEG7EI64_V_M1_MF2 = 12649 + + PseudoVSUXSEG7EI64_V_M1_MF2_MASK = 12650 + + PseudoVSUXSEG7EI64_V_M1_MF4 = 12651 + + PseudoVSUXSEG7EI64_V_M1_MF4_MASK = 12652 + + PseudoVSUXSEG7EI64_V_M1_MF8 = 12653 + + PseudoVSUXSEG7EI64_V_M1_MF8_MASK = 12654 + + PseudoVSUXSEG7EI64_V_M2_M1 = 12655 + + PseudoVSUXSEG7EI64_V_M2_M1_MASK = 12656 + + PseudoVSUXSEG7EI64_V_M2_MF2 = 12657 + + PseudoVSUXSEG7EI64_V_M2_MF2_MASK = 12658 + + PseudoVSUXSEG7EI64_V_M2_MF4 = 12659 + + PseudoVSUXSEG7EI64_V_M2_MF4_MASK = 12660 + + PseudoVSUXSEG7EI64_V_M4_M1 = 12661 + + PseudoVSUXSEG7EI64_V_M4_M1_MASK = 12662 + + PseudoVSUXSEG7EI64_V_M4_MF2 = 12663 + + PseudoVSUXSEG7EI64_V_M4_MF2_MASK = 12664 + + PseudoVSUXSEG7EI64_V_M8_M1 = 12665 + + PseudoVSUXSEG7EI64_V_M8_M1_MASK = 12666 + + PseudoVSUXSEG7EI8_V_M1_M1 = 12667 + + PseudoVSUXSEG7EI8_V_M1_M1_MASK = 12668 + + PseudoVSUXSEG7EI8_V_MF2_M1 = 12669 + + PseudoVSUXSEG7EI8_V_MF2_M1_MASK = 12670 + + PseudoVSUXSEG7EI8_V_MF2_MF2 = 12671 + + PseudoVSUXSEG7EI8_V_MF2_MF2_MASK = 12672 + + PseudoVSUXSEG7EI8_V_MF4_M1 = 12673 + + PseudoVSUXSEG7EI8_V_MF4_M1_MASK = 12674 + + PseudoVSUXSEG7EI8_V_MF4_MF2 = 12675 + + PseudoVSUXSEG7EI8_V_MF4_MF2_MASK = 12676 + + PseudoVSUXSEG7EI8_V_MF4_MF4 = 12677 + + PseudoVSUXSEG7EI8_V_MF4_MF4_MASK = 12678 + + PseudoVSUXSEG7EI8_V_MF8_M1 = 12679 + + PseudoVSUXSEG7EI8_V_MF8_M1_MASK = 12680 + + PseudoVSUXSEG7EI8_V_MF8_MF2 = 12681 + + PseudoVSUXSEG7EI8_V_MF8_MF2_MASK = 12682 + + PseudoVSUXSEG7EI8_V_MF8_MF4 = 12683 + + PseudoVSUXSEG7EI8_V_MF8_MF4_MASK = 12684 + + PseudoVSUXSEG7EI8_V_MF8_MF8 = 12685 + + PseudoVSUXSEG7EI8_V_MF8_MF8_MASK = 12686 + + PseudoVSUXSEG8EI16_V_M1_M1 = 12687 + + PseudoVSUXSEG8EI16_V_M1_M1_MASK = 12688 + + PseudoVSUXSEG8EI16_V_M1_MF2 = 12689 + + PseudoVSUXSEG8EI16_V_M1_MF2_MASK = 12690 + + PseudoVSUXSEG8EI16_V_M2_M1 = 12691 + + PseudoVSUXSEG8EI16_V_M2_M1_MASK = 12692 + + PseudoVSUXSEG8EI16_V_MF2_M1 = 12693 + + PseudoVSUXSEG8EI16_V_MF2_M1_MASK = 12694 + + PseudoVSUXSEG8EI16_V_MF2_MF2 = 12695 + + PseudoVSUXSEG8EI16_V_MF2_MF2_MASK = 12696 + + PseudoVSUXSEG8EI16_V_MF2_MF4 = 12697 + + PseudoVSUXSEG8EI16_V_MF2_MF4_MASK = 12698 + + PseudoVSUXSEG8EI16_V_MF4_M1 = 12699 + + PseudoVSUXSEG8EI16_V_MF4_M1_MASK = 12700 + + PseudoVSUXSEG8EI16_V_MF4_MF2 = 12701 + + PseudoVSUXSEG8EI16_V_MF4_MF2_MASK = 12702 + + PseudoVSUXSEG8EI16_V_MF4_MF4 = 12703 + + PseudoVSUXSEG8EI16_V_MF4_MF4_MASK = 12704 + + PseudoVSUXSEG8EI16_V_MF4_MF8 = 12705 + + PseudoVSUXSEG8EI16_V_MF4_MF8_MASK = 12706 + + PseudoVSUXSEG8EI32_V_M1_M1 = 12707 + + PseudoVSUXSEG8EI32_V_M1_M1_MASK = 12708 + + PseudoVSUXSEG8EI32_V_M1_MF2 = 12709 + + PseudoVSUXSEG8EI32_V_M1_MF2_MASK = 12710 + + PseudoVSUXSEG8EI32_V_M1_MF4 = 12711 + + PseudoVSUXSEG8EI32_V_M1_MF4_MASK = 12712 + + PseudoVSUXSEG8EI32_V_M2_M1 = 12713 + + PseudoVSUXSEG8EI32_V_M2_M1_MASK = 12714 + + PseudoVSUXSEG8EI32_V_M2_MF2 = 12715 + + PseudoVSUXSEG8EI32_V_M2_MF2_MASK = 12716 + + PseudoVSUXSEG8EI32_V_M4_M1 = 12717 + + PseudoVSUXSEG8EI32_V_M4_M1_MASK = 12718 + + PseudoVSUXSEG8EI32_V_MF2_M1 = 12719 + + PseudoVSUXSEG8EI32_V_MF2_M1_MASK = 12720 + + PseudoVSUXSEG8EI32_V_MF2_MF2 = 12721 + + PseudoVSUXSEG8EI32_V_MF2_MF2_MASK = 12722 + + PseudoVSUXSEG8EI32_V_MF2_MF4 = 12723 + + PseudoVSUXSEG8EI32_V_MF2_MF4_MASK = 12724 + + PseudoVSUXSEG8EI32_V_MF2_MF8 = 12725 + + PseudoVSUXSEG8EI32_V_MF2_MF8_MASK = 12726 + + PseudoVSUXSEG8EI64_V_M1_M1 = 12727 + + PseudoVSUXSEG8EI64_V_M1_M1_MASK = 12728 + + PseudoVSUXSEG8EI64_V_M1_MF2 = 12729 + + PseudoVSUXSEG8EI64_V_M1_MF2_MASK = 12730 + + PseudoVSUXSEG8EI64_V_M1_MF4 = 12731 + + PseudoVSUXSEG8EI64_V_M1_MF4_MASK = 12732 + + PseudoVSUXSEG8EI64_V_M1_MF8 = 12733 + + PseudoVSUXSEG8EI64_V_M1_MF8_MASK = 12734 + + PseudoVSUXSEG8EI64_V_M2_M1 = 12735 + + PseudoVSUXSEG8EI64_V_M2_M1_MASK = 12736 + + PseudoVSUXSEG8EI64_V_M2_MF2 = 12737 + + PseudoVSUXSEG8EI64_V_M2_MF2_MASK = 12738 + + PseudoVSUXSEG8EI64_V_M2_MF4 = 12739 + + PseudoVSUXSEG8EI64_V_M2_MF4_MASK = 12740 + + PseudoVSUXSEG8EI64_V_M4_M1 = 12741 + + PseudoVSUXSEG8EI64_V_M4_M1_MASK = 12742 + + PseudoVSUXSEG8EI64_V_M4_MF2 = 12743 + + PseudoVSUXSEG8EI64_V_M4_MF2_MASK = 12744 + + PseudoVSUXSEG8EI64_V_M8_M1 = 12745 + + PseudoVSUXSEG8EI64_V_M8_M1_MASK = 12746 + + PseudoVSUXSEG8EI8_V_M1_M1 = 12747 + + PseudoVSUXSEG8EI8_V_M1_M1_MASK = 12748 + + PseudoVSUXSEG8EI8_V_MF2_M1 = 12749 + + PseudoVSUXSEG8EI8_V_MF2_M1_MASK = 12750 + + PseudoVSUXSEG8EI8_V_MF2_MF2 = 12751 + + PseudoVSUXSEG8EI8_V_MF2_MF2_MASK = 12752 + + PseudoVSUXSEG8EI8_V_MF4_M1 = 12753 + + PseudoVSUXSEG8EI8_V_MF4_M1_MASK = 12754 + + PseudoVSUXSEG8EI8_V_MF4_MF2 = 12755 + + PseudoVSUXSEG8EI8_V_MF4_MF2_MASK = 12756 + + PseudoVSUXSEG8EI8_V_MF4_MF4 = 12757 + + PseudoVSUXSEG8EI8_V_MF4_MF4_MASK = 12758 + + PseudoVSUXSEG8EI8_V_MF8_M1 = 12759 + + PseudoVSUXSEG8EI8_V_MF8_M1_MASK = 12760 + + PseudoVSUXSEG8EI8_V_MF8_MF2 = 12761 + + PseudoVSUXSEG8EI8_V_MF8_MF2_MASK = 12762 + + PseudoVSUXSEG8EI8_V_MF8_MF4 = 12763 + + PseudoVSUXSEG8EI8_V_MF8_MF4_MASK = 12764 + + PseudoVSUXSEG8EI8_V_MF8_MF8 = 12765 + + PseudoVSUXSEG8EI8_V_MF8_MF8_MASK = 12766 + + PseudoVWADDU_VV_M1 = 12767 + + PseudoVWADDU_VV_M1_MASK = 12768 + + PseudoVWADDU_VV_M2 = 12769 + + PseudoVWADDU_VV_M2_MASK = 12770 + + PseudoVWADDU_VV_M4 = 12771 + + PseudoVWADDU_VV_M4_MASK = 12772 + + PseudoVWADDU_VV_MF2 = 12773 + + PseudoVWADDU_VV_MF2_MASK = 12774 + + PseudoVWADDU_VV_MF4 = 12775 + + PseudoVWADDU_VV_MF4_MASK = 12776 + + PseudoVWADDU_VV_MF8 = 12777 + + PseudoVWADDU_VV_MF8_MASK = 12778 + + PseudoVWADDU_VX_M1 = 12779 + + PseudoVWADDU_VX_M1_MASK = 12780 + + PseudoVWADDU_VX_M2 = 12781 + + PseudoVWADDU_VX_M2_MASK = 12782 + + PseudoVWADDU_VX_M4 = 12783 + + PseudoVWADDU_VX_M4_MASK = 12784 + + PseudoVWADDU_VX_MF2 = 12785 + + PseudoVWADDU_VX_MF2_MASK = 12786 + + PseudoVWADDU_VX_MF4 = 12787 + + PseudoVWADDU_VX_MF4_MASK = 12788 + + PseudoVWADDU_VX_MF8 = 12789 + + PseudoVWADDU_VX_MF8_MASK = 12790 + + PseudoVWADDU_WV_M1 = 12791 + + PseudoVWADDU_WV_M1_MASK = 12792 + + PseudoVWADDU_WV_M1_MASK_TIED = 12793 + + PseudoVWADDU_WV_M1_TIED = 12794 + + PseudoVWADDU_WV_M2 = 12795 + + PseudoVWADDU_WV_M2_MASK = 12796 + + PseudoVWADDU_WV_M2_MASK_TIED = 12797 + + PseudoVWADDU_WV_M2_TIED = 12798 + + PseudoVWADDU_WV_M4 = 12799 + + PseudoVWADDU_WV_M4_MASK = 12800 + + PseudoVWADDU_WV_M4_MASK_TIED = 12801 + + PseudoVWADDU_WV_M4_TIED = 12802 + + PseudoVWADDU_WV_MF2 = 12803 + + PseudoVWADDU_WV_MF2_MASK = 12804 + + PseudoVWADDU_WV_MF2_MASK_TIED = 12805 + + PseudoVWADDU_WV_MF2_TIED = 12806 + + PseudoVWADDU_WV_MF4 = 12807 + + PseudoVWADDU_WV_MF4_MASK = 12808 + + PseudoVWADDU_WV_MF4_MASK_TIED = 12809 + + PseudoVWADDU_WV_MF4_TIED = 12810 + + PseudoVWADDU_WV_MF8 = 12811 + + PseudoVWADDU_WV_MF8_MASK = 12812 + + PseudoVWADDU_WV_MF8_MASK_TIED = 12813 + + PseudoVWADDU_WV_MF8_TIED = 12814 + + PseudoVWADDU_WX_M1 = 12815 + + PseudoVWADDU_WX_M1_MASK = 12816 + + PseudoVWADDU_WX_M2 = 12817 + + PseudoVWADDU_WX_M2_MASK = 12818 + + PseudoVWADDU_WX_M4 = 12819 + + PseudoVWADDU_WX_M4_MASK = 12820 + + PseudoVWADDU_WX_MF2 = 12821 + + PseudoVWADDU_WX_MF2_MASK = 12822 + + PseudoVWADDU_WX_MF4 = 12823 + + PseudoVWADDU_WX_MF4_MASK = 12824 + + PseudoVWADDU_WX_MF8 = 12825 + + PseudoVWADDU_WX_MF8_MASK = 12826 + + PseudoVWADD_VV_M1 = 12827 + + PseudoVWADD_VV_M1_MASK = 12828 + + PseudoVWADD_VV_M2 = 12829 + + PseudoVWADD_VV_M2_MASK = 12830 + + PseudoVWADD_VV_M4 = 12831 + + PseudoVWADD_VV_M4_MASK = 12832 + + PseudoVWADD_VV_MF2 = 12833 + + PseudoVWADD_VV_MF2_MASK = 12834 + + PseudoVWADD_VV_MF4 = 12835 + + PseudoVWADD_VV_MF4_MASK = 12836 + + PseudoVWADD_VV_MF8 = 12837 + + PseudoVWADD_VV_MF8_MASK = 12838 + + PseudoVWADD_VX_M1 = 12839 + + PseudoVWADD_VX_M1_MASK = 12840 + + PseudoVWADD_VX_M2 = 12841 + + PseudoVWADD_VX_M2_MASK = 12842 + + PseudoVWADD_VX_M4 = 12843 + + PseudoVWADD_VX_M4_MASK = 12844 + + PseudoVWADD_VX_MF2 = 12845 + + PseudoVWADD_VX_MF2_MASK = 12846 + + PseudoVWADD_VX_MF4 = 12847 + + PseudoVWADD_VX_MF4_MASK = 12848 + + PseudoVWADD_VX_MF8 = 12849 + + PseudoVWADD_VX_MF8_MASK = 12850 + + PseudoVWADD_WV_M1 = 12851 + + PseudoVWADD_WV_M1_MASK = 12852 + + PseudoVWADD_WV_M1_MASK_TIED = 12853 + + PseudoVWADD_WV_M1_TIED = 12854 + + PseudoVWADD_WV_M2 = 12855 + + PseudoVWADD_WV_M2_MASK = 12856 + + PseudoVWADD_WV_M2_MASK_TIED = 12857 + + PseudoVWADD_WV_M2_TIED = 12858 + + PseudoVWADD_WV_M4 = 12859 + + PseudoVWADD_WV_M4_MASK = 12860 + + PseudoVWADD_WV_M4_MASK_TIED = 12861 + + PseudoVWADD_WV_M4_TIED = 12862 + + PseudoVWADD_WV_MF2 = 12863 + + PseudoVWADD_WV_MF2_MASK = 12864 + + PseudoVWADD_WV_MF2_MASK_TIED = 12865 + + PseudoVWADD_WV_MF2_TIED = 12866 + + PseudoVWADD_WV_MF4 = 12867 + + PseudoVWADD_WV_MF4_MASK = 12868 + + PseudoVWADD_WV_MF4_MASK_TIED = 12869 + + PseudoVWADD_WV_MF4_TIED = 12870 + + PseudoVWADD_WV_MF8 = 12871 + + PseudoVWADD_WV_MF8_MASK = 12872 + + PseudoVWADD_WV_MF8_MASK_TIED = 12873 + + PseudoVWADD_WV_MF8_TIED = 12874 + + PseudoVWADD_WX_M1 = 12875 + + PseudoVWADD_WX_M1_MASK = 12876 + + PseudoVWADD_WX_M2 = 12877 + + PseudoVWADD_WX_M2_MASK = 12878 + + PseudoVWADD_WX_M4 = 12879 + + PseudoVWADD_WX_M4_MASK = 12880 + + PseudoVWADD_WX_MF2 = 12881 + + PseudoVWADD_WX_MF2_MASK = 12882 + + PseudoVWADD_WX_MF4 = 12883 + + PseudoVWADD_WX_MF4_MASK = 12884 + + PseudoVWADD_WX_MF8 = 12885 + + PseudoVWADD_WX_MF8_MASK = 12886 + + PseudoVWMACCSU_VV_M1 = 12887 + + PseudoVWMACCSU_VV_M1_MASK = 12888 + + PseudoVWMACCSU_VV_M2 = 12889 + + PseudoVWMACCSU_VV_M2_MASK = 12890 + + PseudoVWMACCSU_VV_M4 = 12891 + + PseudoVWMACCSU_VV_M4_MASK = 12892 + + PseudoVWMACCSU_VV_MF2 = 12893 + + PseudoVWMACCSU_VV_MF2_MASK = 12894 + + PseudoVWMACCSU_VV_MF4 = 12895 + + PseudoVWMACCSU_VV_MF4_MASK = 12896 + + PseudoVWMACCSU_VV_MF8 = 12897 + + PseudoVWMACCSU_VV_MF8_MASK = 12898 + + PseudoVWMACCSU_VX_M1 = 12899 + + PseudoVWMACCSU_VX_M1_MASK = 12900 + + PseudoVWMACCSU_VX_M2 = 12901 + + PseudoVWMACCSU_VX_M2_MASK = 12902 + + PseudoVWMACCSU_VX_M4 = 12903 + + PseudoVWMACCSU_VX_M4_MASK = 12904 + + PseudoVWMACCSU_VX_MF2 = 12905 + + PseudoVWMACCSU_VX_MF2_MASK = 12906 + + PseudoVWMACCSU_VX_MF4 = 12907 + + PseudoVWMACCSU_VX_MF4_MASK = 12908 + + PseudoVWMACCSU_VX_MF8 = 12909 + + PseudoVWMACCSU_VX_MF8_MASK = 12910 + + PseudoVWMACCUS_VX_M1 = 12911 + + PseudoVWMACCUS_VX_M1_MASK = 12912 + + PseudoVWMACCUS_VX_M2 = 12913 + + PseudoVWMACCUS_VX_M2_MASK = 12914 + + PseudoVWMACCUS_VX_M4 = 12915 + + PseudoVWMACCUS_VX_M4_MASK = 12916 + + PseudoVWMACCUS_VX_MF2 = 12917 + + PseudoVWMACCUS_VX_MF2_MASK = 12918 + + PseudoVWMACCUS_VX_MF4 = 12919 + + PseudoVWMACCUS_VX_MF4_MASK = 12920 + + PseudoVWMACCUS_VX_MF8 = 12921 + + PseudoVWMACCUS_VX_MF8_MASK = 12922 + + PseudoVWMACCU_VV_M1 = 12923 + + PseudoVWMACCU_VV_M1_MASK = 12924 + + PseudoVWMACCU_VV_M2 = 12925 + + PseudoVWMACCU_VV_M2_MASK = 12926 + + PseudoVWMACCU_VV_M4 = 12927 + + PseudoVWMACCU_VV_M4_MASK = 12928 + + PseudoVWMACCU_VV_MF2 = 12929 + + PseudoVWMACCU_VV_MF2_MASK = 12930 + + PseudoVWMACCU_VV_MF4 = 12931 + + PseudoVWMACCU_VV_MF4_MASK = 12932 + + PseudoVWMACCU_VV_MF8 = 12933 + + PseudoVWMACCU_VV_MF8_MASK = 12934 + + PseudoVWMACCU_VX_M1 = 12935 + + PseudoVWMACCU_VX_M1_MASK = 12936 + + PseudoVWMACCU_VX_M2 = 12937 + + PseudoVWMACCU_VX_M2_MASK = 12938 + + PseudoVWMACCU_VX_M4 = 12939 + + PseudoVWMACCU_VX_M4_MASK = 12940 + + PseudoVWMACCU_VX_MF2 = 12941 + + PseudoVWMACCU_VX_MF2_MASK = 12942 + + PseudoVWMACCU_VX_MF4 = 12943 + + PseudoVWMACCU_VX_MF4_MASK = 12944 + + PseudoVWMACCU_VX_MF8 = 12945 + + PseudoVWMACCU_VX_MF8_MASK = 12946 + + PseudoVWMACC_VV_M1 = 12947 + + PseudoVWMACC_VV_M1_MASK = 12948 + + PseudoVWMACC_VV_M2 = 12949 + + PseudoVWMACC_VV_M2_MASK = 12950 + + PseudoVWMACC_VV_M4 = 12951 + + PseudoVWMACC_VV_M4_MASK = 12952 + + PseudoVWMACC_VV_MF2 = 12953 + + PseudoVWMACC_VV_MF2_MASK = 12954 + + PseudoVWMACC_VV_MF4 = 12955 + + PseudoVWMACC_VV_MF4_MASK = 12956 + + PseudoVWMACC_VV_MF8 = 12957 + + PseudoVWMACC_VV_MF8_MASK = 12958 + + PseudoVWMACC_VX_M1 = 12959 + + PseudoVWMACC_VX_M1_MASK = 12960 + + PseudoVWMACC_VX_M2 = 12961 + + PseudoVWMACC_VX_M2_MASK = 12962 + + PseudoVWMACC_VX_M4 = 12963 + + PseudoVWMACC_VX_M4_MASK = 12964 + + PseudoVWMACC_VX_MF2 = 12965 + + PseudoVWMACC_VX_MF2_MASK = 12966 + + PseudoVWMACC_VX_MF4 = 12967 + + PseudoVWMACC_VX_MF4_MASK = 12968 + + PseudoVWMACC_VX_MF8 = 12969 + + PseudoVWMACC_VX_MF8_MASK = 12970 + + PseudoVWMULSU_VV_M1 = 12971 + + PseudoVWMULSU_VV_M1_MASK = 12972 + + PseudoVWMULSU_VV_M2 = 12973 + + PseudoVWMULSU_VV_M2_MASK = 12974 + + PseudoVWMULSU_VV_M4 = 12975 + + PseudoVWMULSU_VV_M4_MASK = 12976 + + PseudoVWMULSU_VV_MF2 = 12977 + + PseudoVWMULSU_VV_MF2_MASK = 12978 + + PseudoVWMULSU_VV_MF4 = 12979 + + PseudoVWMULSU_VV_MF4_MASK = 12980 + + PseudoVWMULSU_VV_MF8 = 12981 + + PseudoVWMULSU_VV_MF8_MASK = 12982 + + PseudoVWMULSU_VX_M1 = 12983 + + PseudoVWMULSU_VX_M1_MASK = 12984 + + PseudoVWMULSU_VX_M2 = 12985 + + PseudoVWMULSU_VX_M2_MASK = 12986 + + PseudoVWMULSU_VX_M4 = 12987 + + PseudoVWMULSU_VX_M4_MASK = 12988 + + PseudoVWMULSU_VX_MF2 = 12989 + + PseudoVWMULSU_VX_MF2_MASK = 12990 + + PseudoVWMULSU_VX_MF4 = 12991 + + PseudoVWMULSU_VX_MF4_MASK = 12992 + + PseudoVWMULSU_VX_MF8 = 12993 + + PseudoVWMULSU_VX_MF8_MASK = 12994 + + PseudoVWMULU_VV_M1 = 12995 + + PseudoVWMULU_VV_M1_MASK = 12996 + + PseudoVWMULU_VV_M2 = 12997 + + PseudoVWMULU_VV_M2_MASK = 12998 + + PseudoVWMULU_VV_M4 = 12999 + + PseudoVWMULU_VV_M4_MASK = 13000 + + PseudoVWMULU_VV_MF2 = 13001 + + PseudoVWMULU_VV_MF2_MASK = 13002 + + PseudoVWMULU_VV_MF4 = 13003 + + PseudoVWMULU_VV_MF4_MASK = 13004 + + PseudoVWMULU_VV_MF8 = 13005 + + PseudoVWMULU_VV_MF8_MASK = 13006 + + PseudoVWMULU_VX_M1 = 13007 + + PseudoVWMULU_VX_M1_MASK = 13008 + + PseudoVWMULU_VX_M2 = 13009 + + PseudoVWMULU_VX_M2_MASK = 13010 + + PseudoVWMULU_VX_M4 = 13011 + + PseudoVWMULU_VX_M4_MASK = 13012 + + PseudoVWMULU_VX_MF2 = 13013 + + PseudoVWMULU_VX_MF2_MASK = 13014 + + PseudoVWMULU_VX_MF4 = 13015 + + PseudoVWMULU_VX_MF4_MASK = 13016 + + PseudoVWMULU_VX_MF8 = 13017 + + PseudoVWMULU_VX_MF8_MASK = 13018 + + PseudoVWMUL_VV_M1 = 13019 + + PseudoVWMUL_VV_M1_MASK = 13020 + + PseudoVWMUL_VV_M2 = 13021 + + PseudoVWMUL_VV_M2_MASK = 13022 + + PseudoVWMUL_VV_M4 = 13023 + + PseudoVWMUL_VV_M4_MASK = 13024 + + PseudoVWMUL_VV_MF2 = 13025 + + PseudoVWMUL_VV_MF2_MASK = 13026 + + PseudoVWMUL_VV_MF4 = 13027 + + PseudoVWMUL_VV_MF4_MASK = 13028 + + PseudoVWMUL_VV_MF8 = 13029 + + PseudoVWMUL_VV_MF8_MASK = 13030 + + PseudoVWMUL_VX_M1 = 13031 + + PseudoVWMUL_VX_M1_MASK = 13032 + + PseudoVWMUL_VX_M2 = 13033 + + PseudoVWMUL_VX_M2_MASK = 13034 + + PseudoVWMUL_VX_M4 = 13035 + + PseudoVWMUL_VX_M4_MASK = 13036 + + PseudoVWMUL_VX_MF2 = 13037 + + PseudoVWMUL_VX_MF2_MASK = 13038 + + PseudoVWMUL_VX_MF4 = 13039 + + PseudoVWMUL_VX_MF4_MASK = 13040 + + PseudoVWMUL_VX_MF8 = 13041 + + PseudoVWMUL_VX_MF8_MASK = 13042 + + PseudoVWREDSUMU_VS_M1_E16 = 13043 + + PseudoVWREDSUMU_VS_M1_E16_MASK = 13044 + + PseudoVWREDSUMU_VS_M1_E32 = 13045 + + PseudoVWREDSUMU_VS_M1_E32_MASK = 13046 + + PseudoVWREDSUMU_VS_M1_E8 = 13047 + + PseudoVWREDSUMU_VS_M1_E8_MASK = 13048 + + PseudoVWREDSUMU_VS_M2_E16 = 13049 + + PseudoVWREDSUMU_VS_M2_E16_MASK = 13050 + + PseudoVWREDSUMU_VS_M2_E32 = 13051 + + PseudoVWREDSUMU_VS_M2_E32_MASK = 13052 + + PseudoVWREDSUMU_VS_M2_E8 = 13053 + + PseudoVWREDSUMU_VS_M2_E8_MASK = 13054 + + PseudoVWREDSUMU_VS_M4_E16 = 13055 + + PseudoVWREDSUMU_VS_M4_E16_MASK = 13056 + + PseudoVWREDSUMU_VS_M4_E32 = 13057 + + PseudoVWREDSUMU_VS_M4_E32_MASK = 13058 + + PseudoVWREDSUMU_VS_M4_E8 = 13059 + + PseudoVWREDSUMU_VS_M4_E8_MASK = 13060 + + PseudoVWREDSUMU_VS_M8_E16 = 13061 + + PseudoVWREDSUMU_VS_M8_E16_MASK = 13062 + + PseudoVWREDSUMU_VS_M8_E32 = 13063 + + PseudoVWREDSUMU_VS_M8_E32_MASK = 13064 + + PseudoVWREDSUMU_VS_M8_E8 = 13065 + + PseudoVWREDSUMU_VS_M8_E8_MASK = 13066 + + PseudoVWREDSUMU_VS_MF2_E16 = 13067 + + PseudoVWREDSUMU_VS_MF2_E16_MASK = 13068 + + PseudoVWREDSUMU_VS_MF2_E32 = 13069 + + PseudoVWREDSUMU_VS_MF2_E32_MASK = 13070 + + PseudoVWREDSUMU_VS_MF2_E8 = 13071 + + PseudoVWREDSUMU_VS_MF2_E8_MASK = 13072 + + PseudoVWREDSUMU_VS_MF4_E16 = 13073 + + PseudoVWREDSUMU_VS_MF4_E16_MASK = 13074 + + PseudoVWREDSUMU_VS_MF4_E8 = 13075 + + PseudoVWREDSUMU_VS_MF4_E8_MASK = 13076 + + PseudoVWREDSUMU_VS_MF8_E8 = 13077 + + PseudoVWREDSUMU_VS_MF8_E8_MASK = 13078 + + PseudoVWREDSUM_VS_M1_E16 = 13079 + + PseudoVWREDSUM_VS_M1_E16_MASK = 13080 + + PseudoVWREDSUM_VS_M1_E32 = 13081 + + PseudoVWREDSUM_VS_M1_E32_MASK = 13082 + + PseudoVWREDSUM_VS_M1_E8 = 13083 + + PseudoVWREDSUM_VS_M1_E8_MASK = 13084 + + PseudoVWREDSUM_VS_M2_E16 = 13085 + + PseudoVWREDSUM_VS_M2_E16_MASK = 13086 + + PseudoVWREDSUM_VS_M2_E32 = 13087 + + PseudoVWREDSUM_VS_M2_E32_MASK = 13088 + + PseudoVWREDSUM_VS_M2_E8 = 13089 + + PseudoVWREDSUM_VS_M2_E8_MASK = 13090 + + PseudoVWREDSUM_VS_M4_E16 = 13091 + + PseudoVWREDSUM_VS_M4_E16_MASK = 13092 + + PseudoVWREDSUM_VS_M4_E32 = 13093 + + PseudoVWREDSUM_VS_M4_E32_MASK = 13094 + + PseudoVWREDSUM_VS_M4_E8 = 13095 + + PseudoVWREDSUM_VS_M4_E8_MASK = 13096 + + PseudoVWREDSUM_VS_M8_E16 = 13097 + + PseudoVWREDSUM_VS_M8_E16_MASK = 13098 + + PseudoVWREDSUM_VS_M8_E32 = 13099 + + PseudoVWREDSUM_VS_M8_E32_MASK = 13100 + + PseudoVWREDSUM_VS_M8_E8 = 13101 + + PseudoVWREDSUM_VS_M8_E8_MASK = 13102 + + PseudoVWREDSUM_VS_MF2_E16 = 13103 + + PseudoVWREDSUM_VS_MF2_E16_MASK = 13104 + + PseudoVWREDSUM_VS_MF2_E32 = 13105 + + PseudoVWREDSUM_VS_MF2_E32_MASK = 13106 + + PseudoVWREDSUM_VS_MF2_E8 = 13107 + + PseudoVWREDSUM_VS_MF2_E8_MASK = 13108 + + PseudoVWREDSUM_VS_MF4_E16 = 13109 + + PseudoVWREDSUM_VS_MF4_E16_MASK = 13110 + + PseudoVWREDSUM_VS_MF4_E8 = 13111 + + PseudoVWREDSUM_VS_MF4_E8_MASK = 13112 + + PseudoVWREDSUM_VS_MF8_E8 = 13113 + + PseudoVWREDSUM_VS_MF8_E8_MASK = 13114 + + PseudoVWSLL_VI_M1 = 13115 + + PseudoVWSLL_VI_M1_MASK = 13116 + + PseudoVWSLL_VI_M2 = 13117 + + PseudoVWSLL_VI_M2_MASK = 13118 + + PseudoVWSLL_VI_M4 = 13119 + + PseudoVWSLL_VI_M4_MASK = 13120 + + PseudoVWSLL_VI_MF2 = 13121 + + PseudoVWSLL_VI_MF2_MASK = 13122 + + PseudoVWSLL_VI_MF4 = 13123 + + PseudoVWSLL_VI_MF4_MASK = 13124 + + PseudoVWSLL_VI_MF8 = 13125 + + PseudoVWSLL_VI_MF8_MASK = 13126 + + PseudoVWSLL_VV_M1 = 13127 + + PseudoVWSLL_VV_M1_MASK = 13128 + + PseudoVWSLL_VV_M2 = 13129 + + PseudoVWSLL_VV_M2_MASK = 13130 + + PseudoVWSLL_VV_M4 = 13131 + + PseudoVWSLL_VV_M4_MASK = 13132 + + PseudoVWSLL_VV_MF2 = 13133 + + PseudoVWSLL_VV_MF2_MASK = 13134 + + PseudoVWSLL_VV_MF4 = 13135 + + PseudoVWSLL_VV_MF4_MASK = 13136 + + PseudoVWSLL_VV_MF8 = 13137 + + PseudoVWSLL_VV_MF8_MASK = 13138 + + PseudoVWSLL_VX_M1 = 13139 + + PseudoVWSLL_VX_M1_MASK = 13140 + + PseudoVWSLL_VX_M2 = 13141 + + PseudoVWSLL_VX_M2_MASK = 13142 + + PseudoVWSLL_VX_M4 = 13143 + + PseudoVWSLL_VX_M4_MASK = 13144 + + PseudoVWSLL_VX_MF2 = 13145 + + PseudoVWSLL_VX_MF2_MASK = 13146 + + PseudoVWSLL_VX_MF4 = 13147 + + PseudoVWSLL_VX_MF4_MASK = 13148 + + PseudoVWSLL_VX_MF8 = 13149 + + PseudoVWSLL_VX_MF8_MASK = 13150 + + PseudoVWSUBU_VV_M1 = 13151 + + PseudoVWSUBU_VV_M1_MASK = 13152 + + PseudoVWSUBU_VV_M2 = 13153 + + PseudoVWSUBU_VV_M2_MASK = 13154 + + PseudoVWSUBU_VV_M4 = 13155 + + PseudoVWSUBU_VV_M4_MASK = 13156 + + PseudoVWSUBU_VV_MF2 = 13157 + + PseudoVWSUBU_VV_MF2_MASK = 13158 + + PseudoVWSUBU_VV_MF4 = 13159 + + PseudoVWSUBU_VV_MF4_MASK = 13160 + + PseudoVWSUBU_VV_MF8 = 13161 + + PseudoVWSUBU_VV_MF8_MASK = 13162 + + PseudoVWSUBU_VX_M1 = 13163 + + PseudoVWSUBU_VX_M1_MASK = 13164 + + PseudoVWSUBU_VX_M2 = 13165 + + PseudoVWSUBU_VX_M2_MASK = 13166 + + PseudoVWSUBU_VX_M4 = 13167 + + PseudoVWSUBU_VX_M4_MASK = 13168 + + PseudoVWSUBU_VX_MF2 = 13169 + + PseudoVWSUBU_VX_MF2_MASK = 13170 + + PseudoVWSUBU_VX_MF4 = 13171 + + PseudoVWSUBU_VX_MF4_MASK = 13172 + + PseudoVWSUBU_VX_MF8 = 13173 + + PseudoVWSUBU_VX_MF8_MASK = 13174 + + PseudoVWSUBU_WV_M1 = 13175 + + PseudoVWSUBU_WV_M1_MASK = 13176 + + PseudoVWSUBU_WV_M1_MASK_TIED = 13177 + + PseudoVWSUBU_WV_M1_TIED = 13178 + + PseudoVWSUBU_WV_M2 = 13179 + + PseudoVWSUBU_WV_M2_MASK = 13180 + + PseudoVWSUBU_WV_M2_MASK_TIED = 13181 + + PseudoVWSUBU_WV_M2_TIED = 13182 + + PseudoVWSUBU_WV_M4 = 13183 + + PseudoVWSUBU_WV_M4_MASK = 13184 + + PseudoVWSUBU_WV_M4_MASK_TIED = 13185 + + PseudoVWSUBU_WV_M4_TIED = 13186 + + PseudoVWSUBU_WV_MF2 = 13187 + + PseudoVWSUBU_WV_MF2_MASK = 13188 + + PseudoVWSUBU_WV_MF2_MASK_TIED = 13189 + + PseudoVWSUBU_WV_MF2_TIED = 13190 + + PseudoVWSUBU_WV_MF4 = 13191 + + PseudoVWSUBU_WV_MF4_MASK = 13192 + + PseudoVWSUBU_WV_MF4_MASK_TIED = 13193 + + PseudoVWSUBU_WV_MF4_TIED = 13194 + + PseudoVWSUBU_WV_MF8 = 13195 + + PseudoVWSUBU_WV_MF8_MASK = 13196 + + PseudoVWSUBU_WV_MF8_MASK_TIED = 13197 + + PseudoVWSUBU_WV_MF8_TIED = 13198 + + PseudoVWSUBU_WX_M1 = 13199 + + PseudoVWSUBU_WX_M1_MASK = 13200 + + PseudoVWSUBU_WX_M2 = 13201 + + PseudoVWSUBU_WX_M2_MASK = 13202 + + PseudoVWSUBU_WX_M4 = 13203 + + PseudoVWSUBU_WX_M4_MASK = 13204 + + PseudoVWSUBU_WX_MF2 = 13205 + + PseudoVWSUBU_WX_MF2_MASK = 13206 + + PseudoVWSUBU_WX_MF4 = 13207 + + PseudoVWSUBU_WX_MF4_MASK = 13208 + + PseudoVWSUBU_WX_MF8 = 13209 + + PseudoVWSUBU_WX_MF8_MASK = 13210 + + PseudoVWSUB_VV_M1 = 13211 + + PseudoVWSUB_VV_M1_MASK = 13212 + + PseudoVWSUB_VV_M2 = 13213 + + PseudoVWSUB_VV_M2_MASK = 13214 + + PseudoVWSUB_VV_M4 = 13215 + + PseudoVWSUB_VV_M4_MASK = 13216 + + PseudoVWSUB_VV_MF2 = 13217 + + PseudoVWSUB_VV_MF2_MASK = 13218 + + PseudoVWSUB_VV_MF4 = 13219 + + PseudoVWSUB_VV_MF4_MASK = 13220 + + PseudoVWSUB_VV_MF8 = 13221 + + PseudoVWSUB_VV_MF8_MASK = 13222 + + PseudoVWSUB_VX_M1 = 13223 + + PseudoVWSUB_VX_M1_MASK = 13224 + + PseudoVWSUB_VX_M2 = 13225 + + PseudoVWSUB_VX_M2_MASK = 13226 + + PseudoVWSUB_VX_M4 = 13227 + + PseudoVWSUB_VX_M4_MASK = 13228 + + PseudoVWSUB_VX_MF2 = 13229 + + PseudoVWSUB_VX_MF2_MASK = 13230 + + PseudoVWSUB_VX_MF4 = 13231 + + PseudoVWSUB_VX_MF4_MASK = 13232 + + PseudoVWSUB_VX_MF8 = 13233 + + PseudoVWSUB_VX_MF8_MASK = 13234 + + PseudoVWSUB_WV_M1 = 13235 + + PseudoVWSUB_WV_M1_MASK = 13236 + + PseudoVWSUB_WV_M1_MASK_TIED = 13237 + + PseudoVWSUB_WV_M1_TIED = 13238 + + PseudoVWSUB_WV_M2 = 13239 + + PseudoVWSUB_WV_M2_MASK = 13240 + + PseudoVWSUB_WV_M2_MASK_TIED = 13241 + + PseudoVWSUB_WV_M2_TIED = 13242 + + PseudoVWSUB_WV_M4 = 13243 + + PseudoVWSUB_WV_M4_MASK = 13244 + + PseudoVWSUB_WV_M4_MASK_TIED = 13245 + + PseudoVWSUB_WV_M4_TIED = 13246 + + PseudoVWSUB_WV_MF2 = 13247 + + PseudoVWSUB_WV_MF2_MASK = 13248 + + PseudoVWSUB_WV_MF2_MASK_TIED = 13249 + + PseudoVWSUB_WV_MF2_TIED = 13250 + + PseudoVWSUB_WV_MF4 = 13251 + + PseudoVWSUB_WV_MF4_MASK = 13252 + + PseudoVWSUB_WV_MF4_MASK_TIED = 13253 + + PseudoVWSUB_WV_MF4_TIED = 13254 + + PseudoVWSUB_WV_MF8 = 13255 + + PseudoVWSUB_WV_MF8_MASK = 13256 + + PseudoVWSUB_WV_MF8_MASK_TIED = 13257 + + PseudoVWSUB_WV_MF8_TIED = 13258 + + PseudoVWSUB_WX_M1 = 13259 + + PseudoVWSUB_WX_M1_MASK = 13260 + + PseudoVWSUB_WX_M2 = 13261 + + PseudoVWSUB_WX_M2_MASK = 13262 + + PseudoVWSUB_WX_M4 = 13263 + + PseudoVWSUB_WX_M4_MASK = 13264 + + PseudoVWSUB_WX_MF2 = 13265 + + PseudoVWSUB_WX_MF2_MASK = 13266 + + PseudoVWSUB_WX_MF4 = 13267 + + PseudoVWSUB_WX_MF4_MASK = 13268 + + PseudoVWSUB_WX_MF8 = 13269 + + PseudoVWSUB_WX_MF8_MASK = 13270 + + PseudoVXOR_VI_M1 = 13271 + + PseudoVXOR_VI_M1_MASK = 13272 + + PseudoVXOR_VI_M2 = 13273 + + PseudoVXOR_VI_M2_MASK = 13274 + + PseudoVXOR_VI_M4 = 13275 + + PseudoVXOR_VI_M4_MASK = 13276 + + PseudoVXOR_VI_M8 = 13277 + + PseudoVXOR_VI_M8_MASK = 13278 + + PseudoVXOR_VI_MF2 = 13279 + + PseudoVXOR_VI_MF2_MASK = 13280 + + PseudoVXOR_VI_MF4 = 13281 + + PseudoVXOR_VI_MF4_MASK = 13282 + + PseudoVXOR_VI_MF8 = 13283 + + PseudoVXOR_VI_MF8_MASK = 13284 + + PseudoVXOR_VV_M1 = 13285 + + PseudoVXOR_VV_M1_MASK = 13286 + + PseudoVXOR_VV_M2 = 13287 + + PseudoVXOR_VV_M2_MASK = 13288 + + PseudoVXOR_VV_M4 = 13289 + + PseudoVXOR_VV_M4_MASK = 13290 + + PseudoVXOR_VV_M8 = 13291 + + PseudoVXOR_VV_M8_MASK = 13292 + + PseudoVXOR_VV_MF2 = 13293 + + PseudoVXOR_VV_MF2_MASK = 13294 + + PseudoVXOR_VV_MF4 = 13295 + + PseudoVXOR_VV_MF4_MASK = 13296 + + PseudoVXOR_VV_MF8 = 13297 + + PseudoVXOR_VV_MF8_MASK = 13298 + + PseudoVXOR_VX_M1 = 13299 + + PseudoVXOR_VX_M1_MASK = 13300 + + PseudoVXOR_VX_M2 = 13301 + + PseudoVXOR_VX_M2_MASK = 13302 + + PseudoVXOR_VX_M4 = 13303 + + PseudoVXOR_VX_M4_MASK = 13304 + + PseudoVXOR_VX_M8 = 13305 + + PseudoVXOR_VX_M8_MASK = 13306 + + PseudoVXOR_VX_MF2 = 13307 + + PseudoVXOR_VX_MF2_MASK = 13308 + + PseudoVXOR_VX_MF4 = 13309 + + PseudoVXOR_VX_MF4_MASK = 13310 + + PseudoVXOR_VX_MF8 = 13311 + + PseudoVXOR_VX_MF8_MASK = 13312 + + PseudoVZEXT_VF2_M1 = 13313 + + PseudoVZEXT_VF2_M1_MASK = 13314 + + PseudoVZEXT_VF2_M2 = 13315 + + PseudoVZEXT_VF2_M2_MASK = 13316 + + PseudoVZEXT_VF2_M4 = 13317 + + PseudoVZEXT_VF2_M4_MASK = 13318 + + PseudoVZEXT_VF2_M8 = 13319 + + PseudoVZEXT_VF2_M8_MASK = 13320 + + PseudoVZEXT_VF2_MF2 = 13321 + + PseudoVZEXT_VF2_MF2_MASK = 13322 + + PseudoVZEXT_VF2_MF4 = 13323 + + PseudoVZEXT_VF2_MF4_MASK = 13324 + + PseudoVZEXT_VF4_M1 = 13325 + + PseudoVZEXT_VF4_M1_MASK = 13326 + + PseudoVZEXT_VF4_M2 = 13327 + + PseudoVZEXT_VF4_M2_MASK = 13328 + + PseudoVZEXT_VF4_M4 = 13329 + + PseudoVZEXT_VF4_M4_MASK = 13330 + + PseudoVZEXT_VF4_M8 = 13331 + + PseudoVZEXT_VF4_M8_MASK = 13332 + + PseudoVZEXT_VF4_MF2 = 13333 + + PseudoVZEXT_VF4_MF2_MASK = 13334 + + PseudoVZEXT_VF8_M1 = 13335 + + PseudoVZEXT_VF8_M1_MASK = 13336 + + PseudoVZEXT_VF8_M2 = 13337 + + PseudoVZEXT_VF8_M2_MASK = 13338 + + PseudoVZEXT_VF8_M4 = 13339 + + PseudoVZEXT_VF8_M4_MASK = 13340 + + PseudoVZEXT_VF8_M8 = 13341 + + PseudoVZEXT_VF8_M8_MASK = 13342 + + PseudoZEXT_H = 13343 + + PseudoZEXT_W = 13344 + + ReadCounterWide = 13345 + + ReadFCSR = 13346 + + ReadFFLAGS = 13347 + + ReadFRM = 13348 + + Select_FPR16INX_Using_CC_GPR = 13349 + + Select_FPR16_Using_CC_GPR = 13350 + + Select_FPR32INX_Using_CC_GPR = 13351 + + Select_FPR32_Using_CC_GPR = 13352 + + Select_FPR64IN32X_Using_CC_GPR = 13353 + + Select_FPR64INX_Using_CC_GPR = 13354 + + Select_FPR64_Using_CC_GPR = 13355 + + Select_GPRNoX0_Using_CC_SImm16NonZero_QC = 13356 + + Select_GPRNoX0_Using_CC_SImm5NonZero_QC = 13357 + + Select_GPRNoX0_Using_CC_UImm16NonZero_QC = 13358 + + Select_GPRNoX0_Using_CC_UImm5NonZero_QC = 13359 + + Select_GPR_Using_CC_GPR = 13360 + + Select_GPR_Using_CC_Imm5_Zibi = 13361 + + Select_GPR_Using_CC_SImm5_CV = 13362 + + Select_GPR_Using_CC_UImm7_NDS = 13363 + + Select_GPR_Using_CC_UImmLog2XLen_NDS = 13364 + + SetFCSR = 13365 + + SetFCSRImm = 13366 + + SplitF64Pseudo = 13367 + + SwapFRMImm = 13368 + + WriteFCSR = 13369 + + WriteFCSRImm = 13370 + + WriteFFLAGS = 13371 + + WriteFRM = 13372 + + WriteFRMImm = 13373 + + WriteVXRMImm = 13374 + + AADD = 13375 + + AADDU = 13376 + + ABS = 13377 + + ABSW = 13378 + + ADD = 13379 + + ADDD = 13380 + + ADDI = 13381 + + ADDIW = 13382 + + ADDW = 13383 + + ADD_UW = 13384 + + AES32DSI = 13385 + + AES32DSMI = 13386 + + AES32ESI = 13387 + + AES32ESMI = 13388 + + AES64DS = 13389 + + AES64DSM = 13390 + + AES64ES = 13391 + + AES64ESM = 13392 + + AES64IM = 13393 + + AES64KS1I = 13394 + + AES64KS2 = 13395 + + AMOADD_B = 13396 + + AMOADD_B_AQ = 13397 + + AMOADD_B_AQRL = 13398 + + AMOADD_B_RL = 13399 + + AMOADD_D = 13400 + + AMOADD_D_AQ = 13401 + + AMOADD_D_AQRL = 13402 + + AMOADD_D_RL = 13403 + + AMOADD_H = 13404 + + AMOADD_H_AQ = 13405 + + AMOADD_H_AQRL = 13406 + + AMOADD_H_RL = 13407 + + AMOADD_W = 13408 + + AMOADD_W_AQ = 13409 + + AMOADD_W_AQRL = 13410 + + AMOADD_W_RL = 13411 + + AMOAND_B = 13412 + + AMOAND_B_AQ = 13413 + + AMOAND_B_AQRL = 13414 + + AMOAND_B_RL = 13415 + + AMOAND_D = 13416 + + AMOAND_D_AQ = 13417 + + AMOAND_D_AQRL = 13418 + + AMOAND_D_RL = 13419 + + AMOAND_H = 13420 + + AMOAND_H_AQ = 13421 + + AMOAND_H_AQRL = 13422 + + AMOAND_H_RL = 13423 + + AMOAND_W = 13424 + + AMOAND_W_AQ = 13425 + + AMOAND_W_AQRL = 13426 + + AMOAND_W_RL = 13427 + + AMOCAS_B = 13428 + + AMOCAS_B_AQ = 13429 + + AMOCAS_B_AQRL = 13430 + + AMOCAS_B_RL = 13431 + + AMOCAS_D_RV32 = 13432 + + AMOCAS_D_RV32_AQ = 13433 + + AMOCAS_D_RV32_AQRL = 13434 + + AMOCAS_D_RV32_RL = 13435 + + AMOCAS_D_RV64 = 13436 + + AMOCAS_D_RV64_AQ = 13437 + + AMOCAS_D_RV64_AQRL = 13438 + + AMOCAS_D_RV64_RL = 13439 + + AMOCAS_H = 13440 + + AMOCAS_H_AQ = 13441 + + AMOCAS_H_AQRL = 13442 + + AMOCAS_H_RL = 13443 + + AMOCAS_Q = 13444 + + AMOCAS_Q_AQ = 13445 + + AMOCAS_Q_AQRL = 13446 + + AMOCAS_Q_RL = 13447 + + AMOCAS_W = 13448 + + AMOCAS_W_AQ = 13449 + + AMOCAS_W_AQRL = 13450 + + AMOCAS_W_RL = 13451 + + AMOMAXU_B = 13452 + + AMOMAXU_B_AQ = 13453 + + AMOMAXU_B_AQRL = 13454 + + AMOMAXU_B_RL = 13455 + + AMOMAXU_D = 13456 + + AMOMAXU_D_AQ = 13457 + + AMOMAXU_D_AQRL = 13458 + + AMOMAXU_D_RL = 13459 + + AMOMAXU_H = 13460 + + AMOMAXU_H_AQ = 13461 + + AMOMAXU_H_AQRL = 13462 + + AMOMAXU_H_RL = 13463 + + AMOMAXU_W = 13464 + + AMOMAXU_W_AQ = 13465 + + AMOMAXU_W_AQRL = 13466 + + AMOMAXU_W_RL = 13467 + + AMOMAX_B = 13468 + + AMOMAX_B_AQ = 13469 + + AMOMAX_B_AQRL = 13470 + + AMOMAX_B_RL = 13471 + + AMOMAX_D = 13472 + + AMOMAX_D_AQ = 13473 + + AMOMAX_D_AQRL = 13474 + + AMOMAX_D_RL = 13475 + + AMOMAX_H = 13476 + + AMOMAX_H_AQ = 13477 + + AMOMAX_H_AQRL = 13478 + + AMOMAX_H_RL = 13479 + + AMOMAX_W = 13480 + + AMOMAX_W_AQ = 13481 + + AMOMAX_W_AQRL = 13482 + + AMOMAX_W_RL = 13483 + + AMOMINU_B = 13484 + + AMOMINU_B_AQ = 13485 + + AMOMINU_B_AQRL = 13486 + + AMOMINU_B_RL = 13487 + + AMOMINU_D = 13488 + + AMOMINU_D_AQ = 13489 + + AMOMINU_D_AQRL = 13490 + + AMOMINU_D_RL = 13491 + + AMOMINU_H = 13492 + + AMOMINU_H_AQ = 13493 + + AMOMINU_H_AQRL = 13494 + + AMOMINU_H_RL = 13495 + + AMOMINU_W = 13496 + + AMOMINU_W_AQ = 13497 + + AMOMINU_W_AQRL = 13498 + + AMOMINU_W_RL = 13499 + + AMOMIN_B = 13500 + + AMOMIN_B_AQ = 13501 + + AMOMIN_B_AQRL = 13502 + + AMOMIN_B_RL = 13503 + + AMOMIN_D = 13504 + + AMOMIN_D_AQ = 13505 + + AMOMIN_D_AQRL = 13506 + + AMOMIN_D_RL = 13507 + + AMOMIN_H = 13508 + + AMOMIN_H_AQ = 13509 + + AMOMIN_H_AQRL = 13510 + + AMOMIN_H_RL = 13511 + + AMOMIN_W = 13512 + + AMOMIN_W_AQ = 13513 + + AMOMIN_W_AQRL = 13514 + + AMOMIN_W_RL = 13515 + + AMOOR_B = 13516 + + AMOOR_B_AQ = 13517 + + AMOOR_B_AQRL = 13518 + + AMOOR_B_RL = 13519 + + AMOOR_D = 13520 + + AMOOR_D_AQ = 13521 + + AMOOR_D_AQRL = 13522 + + AMOOR_D_RL = 13523 + + AMOOR_H = 13524 + + AMOOR_H_AQ = 13525 + + AMOOR_H_AQRL = 13526 + + AMOOR_H_RL = 13527 + + AMOOR_W = 13528 + + AMOOR_W_AQ = 13529 + + AMOOR_W_AQRL = 13530 + + AMOOR_W_RL = 13531 + + AMOSWAP_B = 13532 + + AMOSWAP_B_AQ = 13533 + + AMOSWAP_B_AQRL = 13534 + + AMOSWAP_B_RL = 13535 + + AMOSWAP_D = 13536 + + AMOSWAP_D_AQ = 13537 + + AMOSWAP_D_AQRL = 13538 + + AMOSWAP_D_RL = 13539 + + AMOSWAP_H = 13540 + + AMOSWAP_H_AQ = 13541 + + AMOSWAP_H_AQRL = 13542 + + AMOSWAP_H_RL = 13543 + + AMOSWAP_W = 13544 + + AMOSWAP_W_AQ = 13545 + + AMOSWAP_W_AQRL = 13546 + + AMOSWAP_W_RL = 13547 + + AMOXOR_B = 13548 + + AMOXOR_B_AQ = 13549 + + AMOXOR_B_AQRL = 13550 + + AMOXOR_B_RL = 13551 + + AMOXOR_D = 13552 + + AMOXOR_D_AQ = 13553 + + AMOXOR_D_AQRL = 13554 + + AMOXOR_D_RL = 13555 + + AMOXOR_H = 13556 + + AMOXOR_H_AQ = 13557 + + AMOXOR_H_AQRL = 13558 + + AMOXOR_H_RL = 13559 + + AMOXOR_W = 13560 + + AMOXOR_W_AQ = 13561 + + AMOXOR_W_AQRL = 13562 + + AMOXOR_W_RL = 13563 + + AND = 13564 + + ANDI = 13565 + + ANDN = 13566 + + ASUB = 13567 + + ASUBU = 13568 + + AUIPC = 13569 + + BCLR = 13570 + + BCLRI = 13571 + + BEQ = 13572 + + BEQI = 13573 + + BEXT = 13574 + + BEXTI = 13575 + + BGE = 13576 + + BGEU = 13577 + + BINV = 13578 + + BINVI = 13579 + + BLT = 13580 + + BLTU = 13581 + + BNE = 13582 + + BNEI = 13583 + + BREV8 = 13584 + + BSET = 13585 + + BSETI = 13586 + + CBO_CLEAN = 13587 + + CBO_FLUSH = 13588 + + CBO_INVAL = 13589 + + CBO_ZERO = 13590 + + CLMUL = 13591 + + CLMULH = 13592 + + CLMULR = 13593 + + CLS = 13594 + + CLSW = 13595 + + CLZ = 13596 + + CLZW = 13597 + + CM_JALT = 13598 + + CM_JT = 13599 + + CM_MVA01S = 13600 + + CM_MVSA01 = 13601 + + CM_POP = 13602 + + CM_POPRET = 13603 + + CM_POPRETZ = 13604 + + CM_PUSH = 13605 + + CPOP = 13606 + + CPOPW = 13607 + + CSRRC = 13608 + + CSRRCI = 13609 + + CSRRS = 13610 + + CSRRSI = 13611 + + CSRRW = 13612 + + CSRRWI = 13613 + + CTZ = 13614 + + CTZW = 13615 + + CV_ABS = 13616 + + CV_ABS_B = 13617 + + CV_ABS_H = 13618 + + CV_ADDN = 13619 + + CV_ADDNR = 13620 + + CV_ADDRN = 13621 + + CV_ADDRNR = 13622 + + CV_ADDUN = 13623 + + CV_ADDUNR = 13624 + + CV_ADDURN = 13625 + + CV_ADDURNR = 13626 + + CV_ADD_B = 13627 + + CV_ADD_DIV2 = 13628 + + CV_ADD_DIV4 = 13629 + + CV_ADD_DIV8 = 13630 + + CV_ADD_H = 13631 + + CV_ADD_SCI_B = 13632 + + CV_ADD_SCI_H = 13633 + + CV_ADD_SC_B = 13634 + + CV_ADD_SC_H = 13635 + + CV_AND_B = 13636 + + CV_AND_H = 13637 + + CV_AND_SCI_B = 13638 + + CV_AND_SCI_H = 13639 + + CV_AND_SC_B = 13640 + + CV_AND_SC_H = 13641 + + CV_AVGU_B = 13642 + + CV_AVGU_H = 13643 + + CV_AVGU_SCI_B = 13644 + + CV_AVGU_SCI_H = 13645 + + CV_AVGU_SC_B = 13646 + + CV_AVGU_SC_H = 13647 + + CV_AVG_B = 13648 + + CV_AVG_H = 13649 + + CV_AVG_SCI_B = 13650 + + CV_AVG_SCI_H = 13651 + + CV_AVG_SC_B = 13652 + + CV_AVG_SC_H = 13653 + + CV_BCLR = 13654 + + CV_BCLRR = 13655 + + CV_BEQIMM = 13656 + + CV_BITREV = 13657 + + CV_BNEIMM = 13658 + + CV_BSET = 13659 + + CV_BSETR = 13660 + + CV_CLB = 13661 + + CV_CLIP = 13662 + + CV_CLIPR = 13663 + + CV_CLIPU = 13664 + + CV_CLIPUR = 13665 + + CV_CMPEQ_B = 13666 + + CV_CMPEQ_H = 13667 + + CV_CMPEQ_SCI_B = 13668 + + CV_CMPEQ_SCI_H = 13669 + + CV_CMPEQ_SC_B = 13670 + + CV_CMPEQ_SC_H = 13671 + + CV_CMPGEU_B = 13672 + + CV_CMPGEU_H = 13673 + + CV_CMPGEU_SCI_B = 13674 + + CV_CMPGEU_SCI_H = 13675 + + CV_CMPGEU_SC_B = 13676 + + CV_CMPGEU_SC_H = 13677 + + CV_CMPGE_B = 13678 + + CV_CMPGE_H = 13679 + + CV_CMPGE_SCI_B = 13680 + + CV_CMPGE_SCI_H = 13681 + + CV_CMPGE_SC_B = 13682 + + CV_CMPGE_SC_H = 13683 + + CV_CMPGTU_B = 13684 + + CV_CMPGTU_H = 13685 + + CV_CMPGTU_SCI_B = 13686 + + CV_CMPGTU_SCI_H = 13687 + + CV_CMPGTU_SC_B = 13688 + + CV_CMPGTU_SC_H = 13689 + + CV_CMPGT_B = 13690 + + CV_CMPGT_H = 13691 + + CV_CMPGT_SCI_B = 13692 + + CV_CMPGT_SCI_H = 13693 + + CV_CMPGT_SC_B = 13694 + + CV_CMPGT_SC_H = 13695 + + CV_CMPLEU_B = 13696 + + CV_CMPLEU_H = 13697 + + CV_CMPLEU_SCI_B = 13698 + + CV_CMPLEU_SCI_H = 13699 + + CV_CMPLEU_SC_B = 13700 + + CV_CMPLEU_SC_H = 13701 + + CV_CMPLE_B = 13702 + + CV_CMPLE_H = 13703 + + CV_CMPLE_SCI_B = 13704 + + CV_CMPLE_SCI_H = 13705 + + CV_CMPLE_SC_B = 13706 + + CV_CMPLE_SC_H = 13707 + + CV_CMPLTU_B = 13708 + + CV_CMPLTU_H = 13709 + + CV_CMPLTU_SCI_B = 13710 + + CV_CMPLTU_SCI_H = 13711 + + CV_CMPLTU_SC_B = 13712 + + CV_CMPLTU_SC_H = 13713 + + CV_CMPLT_B = 13714 + + CV_CMPLT_H = 13715 + + CV_CMPLT_SCI_B = 13716 + + CV_CMPLT_SCI_H = 13717 + + CV_CMPLT_SC_B = 13718 + + CV_CMPLT_SC_H = 13719 + + CV_CMPNE_B = 13720 + + CV_CMPNE_H = 13721 + + CV_CMPNE_SCI_B = 13722 + + CV_CMPNE_SCI_H = 13723 + + CV_CMPNE_SC_B = 13724 + + CV_CMPNE_SC_H = 13725 + + CV_CNT = 13726 + + CV_CPLXCONJ = 13727 + + CV_CPLXMUL_I = 13728 + + CV_CPLXMUL_I_DIV2 = 13729 + + CV_CPLXMUL_I_DIV4 = 13730 + + CV_CPLXMUL_I_DIV8 = 13731 + + CV_CPLXMUL_R = 13732 + + CV_CPLXMUL_R_DIV2 = 13733 + + CV_CPLXMUL_R_DIV4 = 13734 + + CV_CPLXMUL_R_DIV8 = 13735 + + CV_DOTSP_B = 13736 + + CV_DOTSP_H = 13737 + + CV_DOTSP_SCI_B = 13738 + + CV_DOTSP_SCI_H = 13739 + + CV_DOTSP_SC_B = 13740 + + CV_DOTSP_SC_H = 13741 + + CV_DOTUP_B = 13742 + + CV_DOTUP_H = 13743 + + CV_DOTUP_SCI_B = 13744 + + CV_DOTUP_SCI_H = 13745 + + CV_DOTUP_SC_B = 13746 + + CV_DOTUP_SC_H = 13747 + + CV_DOTUSP_B = 13748 + + CV_DOTUSP_H = 13749 + + CV_DOTUSP_SCI_B = 13750 + + CV_DOTUSP_SCI_H = 13751 + + CV_DOTUSP_SC_B = 13752 + + CV_DOTUSP_SC_H = 13753 + + CV_ELW = 13754 + + CV_EXTBS = 13755 + + CV_EXTBZ = 13756 + + CV_EXTHS = 13757 + + CV_EXTHZ = 13758 + + CV_EXTRACT = 13759 + + CV_EXTRACTR = 13760 + + CV_EXTRACTU = 13761 + + CV_EXTRACTUR = 13762 + + CV_EXTRACTU_B = 13763 + + CV_EXTRACTU_H = 13764 + + CV_EXTRACT_B = 13765 + + CV_EXTRACT_H = 13766 + + CV_FF1 = 13767 + + CV_FL1 = 13768 + + CV_INSERT = 13769 + + CV_INSERTR = 13770 + + CV_INSERT_B = 13771 + + CV_INSERT_H = 13772 + + CV_LBU_ri_inc = 13773 + + CV_LBU_rr = 13774 + + CV_LBU_rr_inc = 13775 + + CV_LB_ri_inc = 13776 + + CV_LB_rr = 13777 + + CV_LB_rr_inc = 13778 + + CV_LHU_ri_inc = 13779 + + CV_LHU_rr = 13780 + + CV_LHU_rr_inc = 13781 + + CV_LH_ri_inc = 13782 + + CV_LH_rr = 13783 + + CV_LH_rr_inc = 13784 + + CV_LW_ri_inc = 13785 + + CV_LW_rr = 13786 + + CV_LW_rr_inc = 13787 + + CV_MAC = 13788 + + CV_MACHHSN = 13789 + + CV_MACHHSRN = 13790 + + CV_MACHHUN = 13791 + + CV_MACHHURN = 13792 + + CV_MACSN = 13793 + + CV_MACSRN = 13794 + + CV_MACUN = 13795 + + CV_MACURN = 13796 + + CV_MAX = 13797 + + CV_MAXU = 13798 + + CV_MAXU_B = 13799 + + CV_MAXU_H = 13800 + + CV_MAXU_SCI_B = 13801 + + CV_MAXU_SCI_H = 13802 + + CV_MAXU_SC_B = 13803 + + CV_MAXU_SC_H = 13804 + + CV_MAX_B = 13805 + + CV_MAX_H = 13806 + + CV_MAX_SCI_B = 13807 + + CV_MAX_SCI_H = 13808 + + CV_MAX_SC_B = 13809 + + CV_MAX_SC_H = 13810 + + CV_MIN = 13811 + + CV_MINU = 13812 + + CV_MINU_B = 13813 + + CV_MINU_H = 13814 + + CV_MINU_SCI_B = 13815 + + CV_MINU_SCI_H = 13816 + + CV_MINU_SC_B = 13817 + + CV_MINU_SC_H = 13818 + + CV_MIN_B = 13819 + + CV_MIN_H = 13820 + + CV_MIN_SCI_B = 13821 + + CV_MIN_SCI_H = 13822 + + CV_MIN_SC_B = 13823 + + CV_MIN_SC_H = 13824 + + CV_MSU = 13825 + + CV_MULHHSN = 13826 + + CV_MULHHSRN = 13827 + + CV_MULHHUN = 13828 + + CV_MULHHURN = 13829 + + CV_MULSN = 13830 + + CV_MULSRN = 13831 + + CV_MULUN = 13832 + + CV_MULURN = 13833 + + CV_OR_B = 13834 + + CV_OR_H = 13835 + + CV_OR_SCI_B = 13836 + + CV_OR_SCI_H = 13837 + + CV_OR_SC_B = 13838 + + CV_OR_SC_H = 13839 + + CV_PACK = 13840 + + CV_PACKHI_B = 13841 + + CV_PACKLO_B = 13842 + + CV_PACK_H = 13843 + + CV_ROR = 13844 + + CV_SB_ri_inc = 13845 + + CV_SB_rr = 13846 + + CV_SB_rr_inc = 13847 + + CV_SDOTSP_B = 13848 + + CV_SDOTSP_H = 13849 + + CV_SDOTSP_SCI_B = 13850 + + CV_SDOTSP_SCI_H = 13851 + + CV_SDOTSP_SC_B = 13852 + + CV_SDOTSP_SC_H = 13853 + + CV_SDOTUP_B = 13854 + + CV_SDOTUP_H = 13855 + + CV_SDOTUP_SCI_B = 13856 + + CV_SDOTUP_SCI_H = 13857 + + CV_SDOTUP_SC_B = 13858 + + CV_SDOTUP_SC_H = 13859 + + CV_SDOTUSP_B = 13860 + + CV_SDOTUSP_H = 13861 + + CV_SDOTUSP_SCI_B = 13862 + + CV_SDOTUSP_SCI_H = 13863 + + CV_SDOTUSP_SC_B = 13864 + + CV_SDOTUSP_SC_H = 13865 + + CV_SHUFFLE2_B = 13866 + + CV_SHUFFLE2_H = 13867 + + CV_SHUFFLEI0_SCI_B = 13868 + + CV_SHUFFLEI1_SCI_B = 13869 + + CV_SHUFFLEI2_SCI_B = 13870 + + CV_SHUFFLEI3_SCI_B = 13871 + + CV_SHUFFLE_B = 13872 + + CV_SHUFFLE_H = 13873 + + CV_SHUFFLE_SCI_H = 13874 + + CV_SH_ri_inc = 13875 + + CV_SH_rr = 13876 + + CV_SH_rr_inc = 13877 + + CV_SLE = 13878 + + CV_SLEU = 13879 + + CV_SLL_B = 13880 + + CV_SLL_H = 13881 + + CV_SLL_SCI_B = 13882 + + CV_SLL_SCI_H = 13883 + + CV_SLL_SC_B = 13884 + + CV_SLL_SC_H = 13885 + + CV_SRA_B = 13886 + + CV_SRA_H = 13887 + + CV_SRA_SCI_B = 13888 + + CV_SRA_SCI_H = 13889 + + CV_SRA_SC_B = 13890 + + CV_SRA_SC_H = 13891 + + CV_SRL_B = 13892 + + CV_SRL_H = 13893 + + CV_SRL_SCI_B = 13894 + + CV_SRL_SCI_H = 13895 + + CV_SRL_SC_B = 13896 + + CV_SRL_SC_H = 13897 + + CV_SUBN = 13898 + + CV_SUBNR = 13899 + + CV_SUBRN = 13900 + + CV_SUBRNR = 13901 + + CV_SUBROTMJ = 13902 + + CV_SUBROTMJ_DIV2 = 13903 + + CV_SUBROTMJ_DIV4 = 13904 + + CV_SUBROTMJ_DIV8 = 13905 + + CV_SUBUN = 13906 + + CV_SUBUNR = 13907 + + CV_SUBURN = 13908 + + CV_SUBURNR = 13909 + + CV_SUB_B = 13910 + + CV_SUB_DIV2 = 13911 + + CV_SUB_DIV4 = 13912 + + CV_SUB_DIV8 = 13913 + + CV_SUB_H = 13914 + + CV_SUB_SCI_B = 13915 + + CV_SUB_SCI_H = 13916 + + CV_SUB_SC_B = 13917 + + CV_SUB_SC_H = 13918 + + CV_SW_ri_inc = 13919 + + CV_SW_rr = 13920 + + CV_SW_rr_inc = 13921 + + CV_XOR_B = 13922 + + CV_XOR_H = 13923 + + CV_XOR_SCI_B = 13924 + + CV_XOR_SCI_H = 13925 + + CV_XOR_SC_B = 13926 + + CV_XOR_SC_H = 13927 + + CZERO_EQZ = 13928 + + CZERO_NEZ = 13929 + + C_ADD = 13930 + + C_ADDI = 13931 + + C_ADDI16SP = 13932 + + C_ADDI4SPN = 13933 + + C_ADDIW = 13934 + + C_ADDW = 13935 + + C_AND = 13936 + + C_ANDI = 13937 + + C_BEQZ = 13938 + + C_BNEZ = 13939 + + C_EBREAK = 13940 + + C_FLD = 13941 + + C_FLDSP = 13942 + + C_FLW = 13943 + + C_FLWSP = 13944 + + C_FSD = 13945 + + C_FSDSP = 13946 + + C_FSW = 13947 + + C_FSWSP = 13948 + + C_J = 13949 + + C_JAL = 13950 + + C_JALR = 13951 + + C_JR = 13952 + + C_LBU = 13953 + + C_LD = 13954 + + C_LDSP = 13955 + + C_LDSP_RV32 = 13956 + + C_LD_RV32 = 13957 + + C_LH = 13958 + + C_LHU = 13959 + + C_LH_INX = 13960 + + C_LI = 13961 + + C_LUI = 13962 + + C_LW = 13963 + + C_LWSP = 13964 + + C_LWSP_INX = 13965 + + C_LW_INX = 13966 + + C_MOP_1 = 13967 + + C_MOP_11 = 13968 + + C_MOP_13 = 13969 + + C_MOP_15 = 13970 + + C_MOP_3 = 13971 + + C_MOP_5 = 13972 + + C_MOP_7 = 13973 + + C_MOP_9 = 13974 + + C_MUL = 13975 + + C_MV = 13976 + + C_NOP = 13977 + + C_NOP_HINT = 13978 + + C_NOT = 13979 + + C_OR = 13980 + + C_SB = 13981 + + C_SD = 13982 + + C_SDSP = 13983 + + C_SDSP_RV32 = 13984 + + C_SD_RV32 = 13985 + + C_SEXT_B = 13986 + + C_SEXT_H = 13987 + + C_SH = 13988 + + C_SH_INX = 13989 + + C_SLLI = 13990 + + C_SRAI = 13991 + + C_SRLI = 13992 + + C_SSPOPCHK = 13993 + + C_SSPUSH = 13994 + + C_SUB = 13995 + + C_SUBW = 13996 + + C_SW = 13997 + + C_SWSP = 13998 + + C_SWSP_INX = 13999 + + C_SW_INX = 14000 + + C_UNIMP = 14001 + + C_XOR = 14002 + + C_ZEXT_B = 14003 + + C_ZEXT_H = 14004 + + C_ZEXT_W = 14005 + + DIV = 14006 + + DIVU = 14007 + + DIVUW = 14008 + + DIVW = 14009 + + DRET = 14010 + + EBREAK = 14011 + + ECALL = 14012 + + FADD_D = 14013 + + FADD_D_IN32X = 14014 + + FADD_D_INX = 14015 + + FADD_H = 14016 + + FADD_H_INX = 14017 + + FADD_Q = 14018 + + FADD_S = 14019 + + FADD_S_INX = 14020 + + FCLASS_D = 14021 + + FCLASS_D_IN32X = 14022 + + FCLASS_D_INX = 14023 + + FCLASS_H = 14024 + + FCLASS_H_INX = 14025 + + FCLASS_Q = 14026 + + FCLASS_S = 14027 + + FCLASS_S_INX = 14028 + + FCVTMOD_W_D = 14029 + + FCVT_BF16_S = 14030 + + FCVT_D_H = 14031 + + FCVT_D_H_IN32X = 14032 + + FCVT_D_H_INX = 14033 + + FCVT_D_L = 14034 + + FCVT_D_LU = 14035 + + FCVT_D_LU_INX = 14036 + + FCVT_D_L_INX = 14037 + + FCVT_D_Q = 14038 + + FCVT_D_S = 14039 + + FCVT_D_S_IN32X = 14040 + + FCVT_D_S_INX = 14041 + + FCVT_D_W = 14042 + + FCVT_D_WU = 14043 + + FCVT_D_WU_IN32X = 14044 + + FCVT_D_WU_INX = 14045 + + FCVT_D_W_IN32X = 14046 + + FCVT_D_W_INX = 14047 + + FCVT_H_D = 14048 + + FCVT_H_D_IN32X = 14049 + + FCVT_H_D_INX = 14050 + + FCVT_H_L = 14051 + + FCVT_H_LU = 14052 + + FCVT_H_LU_INX = 14053 + + FCVT_H_L_INX = 14054 + + FCVT_H_S = 14055 + + FCVT_H_S_INX = 14056 + + FCVT_H_W = 14057 + + FCVT_H_WU = 14058 + + FCVT_H_WU_INX = 14059 + + FCVT_H_W_INX = 14060 + + FCVT_LU_D = 14061 + + FCVT_LU_D_INX = 14062 + + FCVT_LU_H = 14063 + + FCVT_LU_H_INX = 14064 + + FCVT_LU_Q = 14065 + + FCVT_LU_S = 14066 + + FCVT_LU_S_INX = 14067 + + FCVT_L_D = 14068 + + FCVT_L_D_INX = 14069 + + FCVT_L_H = 14070 + + FCVT_L_H_INX = 14071 + + FCVT_L_Q = 14072 + + FCVT_L_S = 14073 + + FCVT_L_S_INX = 14074 + + FCVT_Q_D = 14075 + + FCVT_Q_L = 14076 + + FCVT_Q_LU = 14077 + + FCVT_Q_S = 14078 + + FCVT_Q_W = 14079 + + FCVT_Q_WU = 14080 + + FCVT_S_BF16 = 14081 + + FCVT_S_D = 14082 + + FCVT_S_D_IN32X = 14083 + + FCVT_S_D_INX = 14084 + + FCVT_S_H = 14085 + + FCVT_S_H_INX = 14086 + + FCVT_S_L = 14087 + + FCVT_S_LU = 14088 + + FCVT_S_LU_INX = 14089 + + FCVT_S_L_INX = 14090 + + FCVT_S_Q = 14091 + + FCVT_S_W = 14092 + + FCVT_S_WU = 14093 + + FCVT_S_WU_INX = 14094 + + FCVT_S_W_INX = 14095 + + FCVT_WU_D = 14096 + + FCVT_WU_D_IN32X = 14097 + + FCVT_WU_D_INX = 14098 + + FCVT_WU_H = 14099 + + FCVT_WU_H_INX = 14100 + + FCVT_WU_Q = 14101 + + FCVT_WU_S = 14102 + + FCVT_WU_S_INX = 14103 + + FCVT_W_D = 14104 + + FCVT_W_D_IN32X = 14105 + + FCVT_W_D_INX = 14106 + + FCVT_W_H = 14107 + + FCVT_W_H_INX = 14108 + + FCVT_W_Q = 14109 + + FCVT_W_S = 14110 + + FCVT_W_S_INX = 14111 + + FDIV_D = 14112 + + FDIV_D_IN32X = 14113 + + FDIV_D_INX = 14114 + + FDIV_H = 14115 + + FDIV_H_INX = 14116 + + FDIV_Q = 14117 + + FDIV_S = 14118 + + FDIV_S_INX = 14119 + + FENCE = 14120 + + FENCE_I = 14121 + + FENCE_TSO = 14122 + + FEQ_D = 14123 + + FEQ_D_IN32X = 14124 + + FEQ_D_INX = 14125 + + FEQ_H = 14126 + + FEQ_H_INX = 14127 + + FEQ_Q = 14128 + + FEQ_S = 14129 + + FEQ_S_INX = 14130 + + FLD = 14131 + + FLEQ_D = 14132 + + FLEQ_H = 14133 + + FLEQ_Q = 14134 + + FLEQ_S = 14135 + + FLE_D = 14136 + + FLE_D_IN32X = 14137 + + FLE_D_INX = 14138 + + FLE_H = 14139 + + FLE_H_INX = 14140 + + FLE_Q = 14141 + + FLE_S = 14142 + + FLE_S_INX = 14143 + + FLH = 14144 + + FLI_D = 14145 + + FLI_H = 14146 + + FLI_Q = 14147 + + FLI_S = 14148 + + FLQ = 14149 + + FLTQ_D = 14150 + + FLTQ_H = 14151 + + FLTQ_Q = 14152 + + FLTQ_S = 14153 + + FLT_D = 14154 + + FLT_D_IN32X = 14155 + + FLT_D_INX = 14156 + + FLT_H = 14157 + + FLT_H_INX = 14158 + + FLT_Q = 14159 + + FLT_S = 14160 + + FLT_S_INX = 14161 + + FLW = 14162 + + FMADD_D = 14163 + + FMADD_D_IN32X = 14164 + + FMADD_D_INX = 14165 + + FMADD_H = 14166 + + FMADD_H_INX = 14167 + + FMADD_Q = 14168 + + FMADD_S = 14169 + + FMADD_S_INX = 14170 + + FMAXM_D = 14171 + + FMAXM_H = 14172 + + FMAXM_Q = 14173 + + FMAXM_S = 14174 + + FMAX_D = 14175 + + FMAX_D_IN32X = 14176 + + FMAX_D_INX = 14177 + + FMAX_H = 14178 + + FMAX_H_INX = 14179 + + FMAX_Q = 14180 + + FMAX_S = 14181 + + FMAX_S_INX = 14182 + + FMINM_D = 14183 + + FMINM_H = 14184 + + FMINM_Q = 14185 + + FMINM_S = 14186 + + FMIN_D = 14187 + + FMIN_D_IN32X = 14188 + + FMIN_D_INX = 14189 + + FMIN_H = 14190 + + FMIN_H_INX = 14191 + + FMIN_Q = 14192 + + FMIN_S = 14193 + + FMIN_S_INX = 14194 + + FMSUB_D = 14195 + + FMSUB_D_IN32X = 14196 + + FMSUB_D_INX = 14197 + + FMSUB_H = 14198 + + FMSUB_H_INX = 14199 + + FMSUB_Q = 14200 + + FMSUB_S = 14201 + + FMSUB_S_INX = 14202 + + FMUL_D = 14203 + + FMUL_D_IN32X = 14204 + + FMUL_D_INX = 14205 + + FMUL_H = 14206 + + FMUL_H_INX = 14207 + + FMUL_Q = 14208 + + FMUL_S = 14209 + + FMUL_S_INX = 14210 + + FMVH_X_D = 14211 + + FMVH_X_Q = 14212 + + FMVP_D_X = 14213 + + FMVP_Q_X = 14214 + + FMV_D_X = 14215 + + FMV_H_X = 14216 + + FMV_W_X = 14217 + + FMV_X_D = 14218 + + FMV_X_H = 14219 + + FMV_X_W = 14220 + + FMV_X_W_FPR64 = 14221 + + FNMADD_D = 14222 + + FNMADD_D_IN32X = 14223 + + FNMADD_D_INX = 14224 + + FNMADD_H = 14225 + + FNMADD_H_INX = 14226 + + FNMADD_Q = 14227 + + FNMADD_S = 14228 + + FNMADD_S_INX = 14229 + + FNMSUB_D = 14230 + + FNMSUB_D_IN32X = 14231 + + FNMSUB_D_INX = 14232 + + FNMSUB_H = 14233 + + FNMSUB_H_INX = 14234 + + FNMSUB_Q = 14235 + + FNMSUB_S = 14236 + + FNMSUB_S_INX = 14237 + + FROUNDNX_D = 14238 + + FROUNDNX_H = 14239 + + FROUNDNX_Q = 14240 + + FROUNDNX_S = 14241 + + FROUND_D = 14242 + + FROUND_H = 14243 + + FROUND_Q = 14244 + + FROUND_S = 14245 + + FSD = 14246 + + FSGNJN_D = 14247 + + FSGNJN_D_IN32X = 14248 + + FSGNJN_D_INX = 14249 + + FSGNJN_H = 14250 + + FSGNJN_H_INX = 14251 + + FSGNJN_Q = 14252 + + FSGNJN_S = 14253 + + FSGNJN_S_INX = 14254 + + FSGNJX_D = 14255 + + FSGNJX_D_IN32X = 14256 + + FSGNJX_D_INX = 14257 + + FSGNJX_H = 14258 + + FSGNJX_H_INX = 14259 + + FSGNJX_Q = 14260 + + FSGNJX_S = 14261 + + FSGNJX_S_INX = 14262 + + FSGNJ_D = 14263 + + FSGNJ_D_IN32X = 14264 + + FSGNJ_D_INX = 14265 + + FSGNJ_H = 14266 + + FSGNJ_H_INX = 14267 + + FSGNJ_Q = 14268 + + FSGNJ_S = 14269 + + FSGNJ_S_INX = 14270 + + FSH = 14271 + + FSQ = 14272 + + FSQRT_D = 14273 + + FSQRT_D_IN32X = 14274 + + FSQRT_D_INX = 14275 + + FSQRT_H = 14276 + + FSQRT_H_INX = 14277 + + FSQRT_Q = 14278 + + FSQRT_S = 14279 + + FSQRT_S_INX = 14280 + + FSUB_D = 14281 + + FSUB_D_IN32X = 14282 + + FSUB_D_INX = 14283 + + FSUB_H = 14284 + + FSUB_H_INX = 14285 + + FSUB_Q = 14286 + + FSUB_S = 14287 + + FSUB_S_INX = 14288 + + FSW = 14289 + + HFENCE_GVMA = 14290 + + HFENCE_VVMA = 14291 + + HINVAL_GVMA = 14292 + + HINVAL_VVMA = 14293 + + HLVX_HU = 14294 + + HLVX_WU = 14295 + + HLV_B = 14296 + + HLV_BU = 14297 + + HLV_D = 14298 + + HLV_H = 14299 + + HLV_HU = 14300 + + HLV_W = 14301 + + HLV_WU = 14302 + + HSV_B = 14303 + + HSV_D = 14304 + + HSV_H = 14305 + + HSV_W = 14306 + + Insn16 = 14307 + + Insn32 = 14308 + + Insn48 = 14309 + + Insn64 = 14310 + + InsnB = 14311 + + InsnCA = 14312 + + InsnCB = 14313 + + InsnCI = 14314 + + InsnCIW = 14315 + + InsnCJ = 14316 + + InsnCL = 14317 + + InsnCR = 14318 + + InsnCS = 14319 + + InsnCSS = 14320 + + InsnI = 14321 + + InsnI_Mem = 14322 + + InsnJ = 14323 + + InsnQC_EAI = 14324 + + InsnQC_EB = 14325 + + InsnQC_EI = 14326 + + InsnQC_EI_Mem = 14327 + + InsnQC_EJ = 14328 + + InsnQC_ES = 14329 + + InsnR = 14330 + + InsnR4 = 14331 + + InsnS = 14332 + + InsnU = 14333 + + JAL = 14334 + + JALR = 14335 + + LB = 14336 + + LBU = 14337 + + LB_AQ = 14338 + + LB_AQRL = 14339 + + LD = 14340 + + LD_AQ = 14341 + + LD_AQRL = 14342 + + LD_RV32 = 14343 + + LH = 14344 + + LHU = 14345 + + LH_AQ = 14346 + + LH_AQRL = 14347 + + LH_INX = 14348 + + LR_D = 14349 + + LR_D_AQ = 14350 + + LR_D_AQRL = 14351 + + LR_D_RL = 14352 + + LR_W = 14353 + + LR_W_AQ = 14354 + + LR_W_AQRL = 14355 + + LR_W_RL = 14356 + + LUI = 14357 + + LW = 14358 + + LWU = 14359 + + LW_AQ = 14360 + + LW_AQRL = 14361 + + LW_INX = 14362 + + MACCSU_H00 = 14363 + + MACCSU_H11 = 14364 + + MACCSU_W00 = 14365 + + MACCSU_W11 = 14366 + + MACCU_H00 = 14367 + + MACCU_H01 = 14368 + + MACCU_H11 = 14369 + + MACCU_W00 = 14370 + + MACCU_W01 = 14371 + + MACCU_W11 = 14372 + + MACC_H00 = 14373 + + MACC_H01 = 14374 + + MACC_H11 = 14375 + + MACC_W00 = 14376 + + MACC_W01 = 14377 + + MACC_W11 = 14378 + + MAX = 14379 + + MAXU = 14380 + + MERGE = 14381 + + MHACC = 14382 + + MHACCSU = 14383 + + MHACCSU_H0 = 14384 + + MHACCSU_H1 = 14385 + + MHACCU = 14386 + + MHACC_H0 = 14387 + + MHACC_H1 = 14388 + + MHRACC = 14389 + + MHRACCSU = 14390 + + MHRACCU = 14391 + + MIN = 14392 + + MINU = 14393 + + MIPS_CCMOV = 14394 + + MIPS_EHB = 14395 + + MIPS_IHB = 14396 + + MIPS_LDP = 14397 + + MIPS_LWP = 14398 + + MIPS_PAUSE = 14399 + + MIPS_PREF = 14400 + + MIPS_SDP = 14401 + + MIPS_SWP = 14402 + + MNRET = 14403 + + MOP_RR_0 = 14404 + + MOP_RR_1 = 14405 + + MOP_RR_2 = 14406 + + MOP_RR_3 = 14407 + + MOP_RR_4 = 14408 + + MOP_RR_5 = 14409 + + MOP_RR_6 = 14410 + + MOP_RR_7 = 14411 + + MOP_R_0 = 14412 + + MOP_R_1 = 14413 + + MOP_R_10 = 14414 + + MOP_R_11 = 14415 + + MOP_R_12 = 14416 + + MOP_R_13 = 14417 + + MOP_R_14 = 14418 + + MOP_R_15 = 14419 + + MOP_R_16 = 14420 + + MOP_R_17 = 14421 + + MOP_R_18 = 14422 + + MOP_R_19 = 14423 + + MOP_R_2 = 14424 + + MOP_R_20 = 14425 + + MOP_R_21 = 14426 + + MOP_R_22 = 14427 + + MOP_R_23 = 14428 + + MOP_R_24 = 14429 + + MOP_R_25 = 14430 + + MOP_R_26 = 14431 + + MOP_R_27 = 14432 + + MOP_R_28 = 14433 + + MOP_R_29 = 14434 + + MOP_R_3 = 14435 + + MOP_R_30 = 14436 + + MOP_R_31 = 14437 + + MOP_R_4 = 14438 + + MOP_R_5 = 14439 + + MOP_R_6 = 14440 + + MOP_R_7 = 14441 + + MOP_R_8 = 14442 + + MOP_R_9 = 14443 + + MQACC_H00 = 14444 + + MQACC_H01 = 14445 + + MQACC_H11 = 14446 + + MQACC_W00 = 14447 + + MQACC_W01 = 14448 + + MQACC_W11 = 14449 + + MQRACC_H00 = 14450 + + MQRACC_H01 = 14451 + + MQRACC_H11 = 14452 + + MQRACC_W00 = 14453 + + MQRACC_W01 = 14454 + + MQRACC_W11 = 14455 + + MRET = 14456 + + MSEQ = 14457 + + MSLT = 14458 + + MSLTU = 14459 + + MUL = 14460 + + MULH = 14461 + + MULHR = 14462 + + MULHRSU = 14463 + + MULHRU = 14464 + + MULHSU = 14465 + + MULHSU_H0 = 14466 + + MULHSU_H1 = 14467 + + MULHU = 14468 + + MULH_H0 = 14469 + + MULH_H1 = 14470 + + MULQ = 14471 + + MULQR = 14472 + + MULSU_H00 = 14473 + + MULSU_H11 = 14474 + + MULSU_W00 = 14475 + + MULSU_W11 = 14476 + + MULU_H00 = 14477 + + MULU_H01 = 14478 + + MULU_H11 = 14479 + + MULU_W00 = 14480 + + MULU_W01 = 14481 + + MULU_W11 = 14482 + + MULW = 14483 + + MUL_H00 = 14484 + + MUL_H01 = 14485 + + MUL_H11 = 14486 + + MUL_W00 = 14487 + + MUL_W01 = 14488 + + MUL_W11 = 14489 + + MVM = 14490 + + MVMN = 14491 + + NCLIP = 14492 + + NCLIPI = 14493 + + NCLIPIU = 14494 + + NCLIPR = 14495 + + NCLIPRI = 14496 + + NCLIPRIU = 14497 + + NCLIPRU = 14498 + + NCLIPU = 14499 + + NDS_ADDIGP = 14500 + + NDS_BBC = 14501 + + NDS_BBS = 14502 + + NDS_BEQC = 14503 + + NDS_BFOS = 14504 + + NDS_BFOZ = 14505 + + NDS_BNEC = 14506 + + NDS_FCVT_BF16_S = 14507 + + NDS_FCVT_S_BF16 = 14508 + + NDS_FFB = 14509 + + NDS_FFMISM = 14510 + + NDS_FFZMISM = 14511 + + NDS_FLMISM = 14512 + + NDS_FMV_BF16_X = 14513 + + NDS_FMV_X_BF16 = 14514 + + NDS_LBGP = 14515 + + NDS_LBUGP = 14516 + + NDS_LDGP = 14517 + + NDS_LEA_B_ZE = 14518 + + NDS_LEA_D = 14519 + + NDS_LEA_D_ZE = 14520 + + NDS_LEA_H = 14521 + + NDS_LEA_H_ZE = 14522 + + NDS_LEA_W = 14523 + + NDS_LEA_W_ZE = 14524 + + NDS_LHGP = 14525 + + NDS_LHUGP = 14526 + + NDS_LWGP = 14527 + + NDS_LWUGP = 14528 + + NDS_SBGP = 14529 + + NDS_SDGP = 14530 + + NDS_SHGP = 14531 + + NDS_SWGP = 14532 + + NDS_VD4DOTSU_VV = 14533 + + NDS_VD4DOTS_VV = 14534 + + NDS_VD4DOTU_VV = 14535 + + NDS_VFNCVT_BF16_S = 14536 + + NDS_VFPMADB_VF = 14537 + + NDS_VFPMADT_VF = 14538 + + NDS_VFWCVT_F_B = 14539 + + NDS_VFWCVT_F_BU = 14540 + + NDS_VFWCVT_F_N = 14541 + + NDS_VFWCVT_F_NU = 14542 + + NDS_VFWCVT_S_BF16 = 14543 + + NDS_VLE4_V = 14544 + + NDS_VLN8_V = 14545 + + NDS_VLNU8_V = 14546 + + NSARI = 14547 + + NSRA = 14548 + + NSRAI = 14549 + + NSRAR = 14550 + + NSRL = 14551 + + NSRLI = 14552 + + OR = 14553 + + ORC_B = 14554 + + ORI = 14555 + + ORN = 14556 + + PAADDU_B = 14557 + + PAADDU_DB = 14558 + + PAADDU_DH = 14559 + + PAADDU_DW = 14560 + + PAADDU_H = 14561 + + PAADDU_W = 14562 + + PAADD_B = 14563 + + PAADD_DB = 14564 + + PAADD_DH = 14565 + + PAADD_DW = 14566 + + PAADD_H = 14567 + + PAADD_W = 14568 + + PAAS_HX = 14569 + + PAAS_WX = 14570 + + PAAX_DHX = 14571 + + PABDSUMAU_B = 14572 + + PABDSUMU_B = 14573 + + PABDU_B = 14574 + + PABDU_DB = 14575 + + PABDU_DH = 14576 + + PABDU_H = 14577 + + PABD_B = 14578 + + PABD_DB = 14579 + + PABD_DH = 14580 + + PABD_H = 14581 + + PACK = 14582 + + PACKH = 14583 + + PACKW = 14584 + + PADD_B = 14585 + + PADD_BS = 14586 + + PADD_DB = 14587 + + PADD_DBS = 14588 + + PADD_DH = 14589 + + PADD_DHS = 14590 + + PADD_DW = 14591 + + PADD_DWS = 14592 + + PADD_H = 14593 + + PADD_HS = 14594 + + PADD_W = 14595 + + PADD_WS = 14596 + + PASA_DHX = 14597 + + PASA_HX = 14598 + + PASA_WX = 14599 + + PASUBU_B = 14600 + + PASUBU_DB = 14601 + + PASUBU_DH = 14602 + + PASUBU_DW = 14603 + + PASUBU_H = 14604 + + PASUBU_W = 14605 + + PASUB_B = 14606 + + PASUB_DB = 14607 + + PASUB_DH = 14608 + + PASUB_DW = 14609 + + PASUB_H = 14610 + + PASUB_W = 14611 + + PAS_DHX = 14612 + + PAS_HX = 14613 + + PAS_WX = 14614 + + PLI_B = 14615 + + PLI_DB = 14616 + + PLI_DH = 14617 + + PLI_H = 14618 + + PLI_W = 14619 + + PLUI_DH = 14620 + + PLUI_H = 14621 + + PLUI_W = 14622 + + PM2ADDASU_H = 14623 + + PM2ADDASU_W = 14624 + + PM2ADDAU_H = 14625 + + PM2ADDAU_W = 14626 + + PM2ADDA_H = 14627 + + PM2ADDA_HX = 14628 + + PM2ADDA_W = 14629 + + PM2ADDA_WX = 14630 + + PM2ADDSU_H = 14631 + + PM2ADDSU_W = 14632 + + PM2ADDU_H = 14633 + + PM2ADDU_W = 14634 + + PM2ADD_H = 14635 + + PM2ADD_HX = 14636 + + PM2ADD_W = 14637 + + PM2ADD_WX = 14638 + + PM2SADD_H = 14639 + + PM2SADD_HX = 14640 + + PM2SUBA_H = 14641 + + PM2SUBA_HX = 14642 + + PM2SUBA_W = 14643 + + PM2SUBA_WX = 14644 + + PM2SUB_H = 14645 + + PM2SUB_HX = 14646 + + PM2SUB_W = 14647 + + PM2SUB_WX = 14648 + + PM2WADDASU_H = 14649 + + PM2WADDAU_H = 14650 + + PM2WADDA_H = 14651 + + PM2WADDA_HX = 14652 + + PM2WADDSU_H = 14653 + + PM2WADDU_H = 14654 + + PM2WADD_H = 14655 + + PM2WADD_HX = 14656 + + PM2WSUBA_H = 14657 + + PM2WSUBA_HX = 14658 + + PM2WSUB_H = 14659 + + PM2WSUB_HX = 14660 + + PM4ADDASU_B = 14661 + + PM4ADDASU_H = 14662 + + PM4ADDAU_B = 14663 + + PM4ADDAU_H = 14664 + + PM4ADDA_B = 14665 + + PM4ADDA_H = 14666 + + PM4ADDSU_B = 14667 + + PM4ADDSU_H = 14668 + + PM4ADDU_B = 14669 + + PM4ADDU_H = 14670 + + PM4ADD_B = 14671 + + PM4ADD_H = 14672 + + PMACCSU_W_H00 = 14673 + + PMACCSU_W_H11 = 14674 + + PMACCU_W_H00 = 14675 + + PMACCU_W_H01 = 14676 + + PMACCU_W_H11 = 14677 + + PMACC_W_H00 = 14678 + + PMACC_W_H01 = 14679 + + PMACC_W_H11 = 14680 + + PMAXU_B = 14681 + + PMAXU_DB = 14682 + + PMAXU_DH = 14683 + + PMAXU_DW = 14684 + + PMAXU_H = 14685 + + PMAXU_W = 14686 + + PMAX_B = 14687 + + PMAX_DB = 14688 + + PMAX_DH = 14689 + + PMAX_DW = 14690 + + PMAX_H = 14691 + + PMAX_W = 14692 + + PMHACCSU_H = 14693 + + PMHACCSU_H_B0 = 14694 + + PMHACCSU_H_B1 = 14695 + + PMHACCSU_W = 14696 + + PMHACCSU_W_H0 = 14697 + + PMHACCSU_W_H1 = 14698 + + PMHACCU_H = 14699 + + PMHACCU_W = 14700 + + PMHACC_H = 14701 + + PMHACC_H_B0 = 14702 + + PMHACC_H_B1 = 14703 + + PMHACC_W = 14704 + + PMHACC_W_H0 = 14705 + + PMHACC_W_H1 = 14706 + + PMHRACCSU_H = 14707 + + PMHRACCSU_W = 14708 + + PMHRACCU_H = 14709 + + PMHRACCU_W = 14710 + + PMHRACC_H = 14711 + + PMHRACC_W = 14712 + + PMINU_B = 14713 + + PMINU_DB = 14714 + + PMINU_DH = 14715 + + PMINU_DW = 14716 + + PMINU_H = 14717 + + PMINU_W = 14718 + + PMIN_B = 14719 + + PMIN_DB = 14720 + + PMIN_DH = 14721 + + PMIN_DW = 14722 + + PMIN_H = 14723 + + PMIN_W = 14724 + + PMQ2ADDA_H = 14725 + + PMQ2ADDA_W = 14726 + + PMQ2ADD_H = 14727 + + PMQ2ADD_W = 14728 + + PMQACC_W_H00 = 14729 + + PMQACC_W_H01 = 14730 + + PMQACC_W_H11 = 14731 + + PMQR2ADDA_H = 14732 + + PMQR2ADDA_W = 14733 + + PMQR2ADD_H = 14734 + + PMQR2ADD_W = 14735 + + PMQRACC_W_H00 = 14736 + + PMQRACC_W_H01 = 14737 + + PMQRACC_W_H11 = 14738 + + PMQRWACC = 14739 + + PMQRWACC_H = 14740 + + PMQWACC = 14741 + + PMQWACC_H = 14742 + + PMSEQ_B = 14743 + + PMSEQ_DB = 14744 + + PMSEQ_DH = 14745 + + PMSEQ_DW = 14746 + + PMSEQ_H = 14747 + + PMSEQ_W = 14748 + + PMSLTU_B = 14749 + + PMSLTU_DB = 14750 + + PMSLTU_DH = 14751 + + PMSLTU_DW = 14752 + + PMSLTU_H = 14753 + + PMSLTU_W = 14754 + + PMSLT_B = 14755 + + PMSLT_DB = 14756 + + PMSLT_DH = 14757 + + PMSLT_DW = 14758 + + PMSLT_H = 14759 + + PMSLT_W = 14760 + + PMULHRSU_H = 14761 + + PMULHRSU_W = 14762 + + PMULHRU_H = 14763 + + PMULHRU_W = 14764 + + PMULHR_H = 14765 + + PMULHR_W = 14766 + + PMULHSU_H = 14767 + + PMULHSU_H_B0 = 14768 + + PMULHSU_H_B1 = 14769 + + PMULHSU_W = 14770 + + PMULHSU_W_H0 = 14771 + + PMULHSU_W_H1 = 14772 + + PMULHU_H = 14773 + + PMULHU_W = 14774 + + PMULH_H = 14775 + + PMULH_H_B0 = 14776 + + PMULH_H_B1 = 14777 + + PMULH_W = 14778 + + PMULH_W_H0 = 14779 + + PMULH_W_H1 = 14780 + + PMULQR_H = 14781 + + PMULQR_W = 14782 + + PMULQ_H = 14783 + + PMULQ_W = 14784 + + PMULSU_H_B00 = 14785 + + PMULSU_H_B11 = 14786 + + PMULSU_W_H00 = 14787 + + PMULSU_W_H11 = 14788 + + PMULU_H_B00 = 14789 + + PMULU_H_B01 = 14790 + + PMULU_H_B11 = 14791 + + PMULU_W_H00 = 14792 + + PMULU_W_H01 = 14793 + + PMULU_W_H11 = 14794 + + PMUL_H_B00 = 14795 + + PMUL_H_B01 = 14796 + + PMUL_H_B11 = 14797 + + PMUL_W_H00 = 14798 + + PMUL_W_H01 = 14799 + + PMUL_W_H11 = 14800 + + PNCLIPIU_B = 14801 + + PNCLIPIU_H = 14802 + + PNCLIPI_B = 14803 + + PNCLIPI_H = 14804 + + PNCLIPRIU_B = 14805 + + PNCLIPRIU_H = 14806 + + PNCLIPRI_B = 14807 + + PNCLIPRI_H = 14808 + + PNCLIPRU_BS = 14809 + + PNCLIPRU_HS = 14810 + + PNCLIPR_BS = 14811 + + PNCLIPR_HS = 14812 + + PNCLIPU_BS = 14813 + + PNCLIPU_HS = 14814 + + PNCLIP_BS = 14815 + + PNCLIP_HS = 14816 + + PNSARI_B = 14817 + + PNSARI_H = 14818 + + PNSRAI_B = 14819 + + PNSRAI_H = 14820 + + PNSRAR_BS = 14821 + + PNSRAR_HS = 14822 + + PNSRA_BS = 14823 + + PNSRA_HS = 14824 + + PNSRLI_B = 14825 + + PNSRLI_H = 14826 + + PNSRL_BS = 14827 + + PNSRL_HS = 14828 + + PPAIREO_B = 14829 + + PPAIREO_DB = 14830 + + PPAIREO_DH = 14831 + + PPAIREO_H = 14832 + + PPAIREO_W = 14833 + + PPAIRE_B = 14834 + + PPAIRE_DB = 14835 + + PPAIRE_DH = 14836 + + PPAIRE_H = 14837 + + PPAIROE_B = 14838 + + PPAIROE_DB = 14839 + + PPAIROE_DH = 14840 + + PPAIROE_H = 14841 + + PPAIROE_W = 14842 + + PPAIRO_B = 14843 + + PPAIRO_DB = 14844 + + PPAIRO_DH = 14845 + + PPAIRO_H = 14846 + + PPAIRO_W = 14847 + + PREDSUMU_BS = 14848 + + PREDSUMU_DBS = 14849 + + PREDSUMU_DHS = 14850 + + PREDSUMU_HS = 14851 + + PREDSUMU_WS = 14852 + + PREDSUM_BS = 14853 + + PREDSUM_DBS = 14854 + + PREDSUM_DHS = 14855 + + PREDSUM_HS = 14856 + + PREDSUM_WS = 14857 + + PREFETCH_I = 14858 + + PREFETCH_R = 14859 + + PREFETCH_W = 14860 + + PSABS_B = 14861 + + PSABS_DB = 14862 + + PSABS_DH = 14863 + + PSABS_H = 14864 + + PSADDU_B = 14865 + + PSADDU_DB = 14866 + + PSADDU_DH = 14867 + + PSADDU_DW = 14868 + + PSADDU_H = 14869 + + PSADDU_W = 14870 + + PSADD_B = 14871 + + PSADD_DB = 14872 + + PSADD_DH = 14873 + + PSADD_DW = 14874 + + PSADD_H = 14875 + + PSADD_W = 14876 + + PSAS_DHX = 14877 + + PSAS_HX = 14878 + + PSAS_WX = 14879 + + PSATI_DH = 14880 + + PSATI_DW = 14881 + + PSATI_H = 14882 + + PSATI_W = 14883 + + PSA_DHX = 14884 + + PSA_HX = 14885 + + PSA_WX = 14886 + + PSEXT_DH_B = 14887 + + PSEXT_DW_B = 14888 + + PSEXT_DW_H = 14889 + + PSEXT_H_B = 14890 + + PSEXT_W_B = 14891 + + PSEXT_W_H = 14892 + + PSH1ADD_DH = 14893 + + PSH1ADD_DW = 14894 + + PSH1ADD_H = 14895 + + PSH1ADD_W = 14896 + + PSLLI_B = 14897 + + PSLLI_DB = 14898 + + PSLLI_DH = 14899 + + PSLLI_DW = 14900 + + PSLLI_H = 14901 + + PSLLI_W = 14902 + + PSLL_BS = 14903 + + PSLL_DBS = 14904 + + PSLL_DHS = 14905 + + PSLL_DWS = 14906 + + PSLL_HS = 14907 + + PSLL_WS = 14908 + + PSRAI_B = 14909 + + PSRAI_DB = 14910 + + PSRAI_DH = 14911 + + PSRAI_DW = 14912 + + PSRAI_H = 14913 + + PSRAI_W = 14914 + + PSRARI_DH = 14915 + + PSRARI_DW = 14916 + + PSRARI_H = 14917 + + PSRARI_W = 14918 + + PSRA_BS = 14919 + + PSRA_DBS = 14920 + + PSRA_DHS = 14921 + + PSRA_DWS = 14922 + + PSRA_HS = 14923 + + PSRA_WS = 14924 + + PSRLI_B = 14925 + + PSRLI_DB = 14926 + + PSRLI_DH = 14927 + + PSRLI_DW = 14928 + + PSRLI_H = 14929 + + PSRLI_W = 14930 + + PSRL_BS = 14931 + + PSRL_DBS = 14932 + + PSRL_DHS = 14933 + + PSRL_DWS = 14934 + + PSRL_HS = 14935 + + PSRL_WS = 14936 + + PSSA_DHX = 14937 + + PSSA_HX = 14938 + + PSSA_WX = 14939 + + PSSH1SADD_DH = 14940 + + PSSH1SADD_DW = 14941 + + PSSH1SADD_H = 14942 + + PSSH1SADD_W = 14943 + + PSSHAR_DHS = 14944 + + PSSHAR_DWS = 14945 + + PSSHAR_HS = 14946 + + PSSHAR_WS = 14947 + + PSSHA_DHS = 14948 + + PSSHA_DWS = 14949 + + PSSHA_HS = 14950 + + PSSHA_WS = 14951 + + PSSLAI_DH = 14952 + + PSSLAI_DW = 14953 + + PSSLAI_H = 14954 + + PSSLAI_W = 14955 + + PSSUBU_B = 14956 + + PSSUBU_DB = 14957 + + PSSUBU_DH = 14958 + + PSSUBU_DW = 14959 + + PSSUBU_H = 14960 + + PSSUBU_W = 14961 + + PSSUB_B = 14962 + + PSSUB_DB = 14963 + + PSSUB_DH = 14964 + + PSSUB_DW = 14965 + + PSSUB_H = 14966 + + PSSUB_W = 14967 + + PSUB_B = 14968 + + PSUB_DB = 14969 + + PSUB_DH = 14970 + + PSUB_DW = 14971 + + PSUB_H = 14972 + + PSUB_W = 14973 + + PUSATI_DH = 14974 + + PUSATI_DW = 14975 + + PUSATI_H = 14976 + + PUSATI_W = 14977 + + PWADDAU_B = 14978 + + PWADDAU_H = 14979 + + PWADDA_B = 14980 + + PWADDA_H = 14981 + + PWADDU_B = 14982 + + PWADDU_H = 14983 + + PWADD_B = 14984 + + PWADD_H = 14985 + + PWMACCSU_H = 14986 + + PWMACCU_H = 14987 + + PWMACC_H = 14988 + + PWMULSU_B = 14989 + + PWMULSU_H = 14990 + + PWMULU_B = 14991 + + PWMULU_H = 14992 + + PWMUL_B = 14993 + + PWMUL_H = 14994 + + PWSLAI_B = 14995 + + PWSLAI_H = 14996 + + PWSLA_BS = 14997 + + PWSLA_HS = 14998 + + PWSLLI_B = 14999 + + PWSLLI_H = 15000 + + PWSLL_BS = 15001 + + PWSLL_HS = 15002 + + PWSUBAU_B = 15003 + + PWSUBAU_H = 15004 + + PWSUBA_B = 15005 + + PWSUBA_H = 15006 + + PWSUBU_B = 15007 + + PWSUBU_H = 15008 + + PWSUB_B = 15009 + + PWSUB_H = 15010 + + QC_ADDSAT = 15011 + + QC_ADDUSAT = 15012 + + QC_BEQI = 15013 + + QC_BGEI = 15014 + + QC_BGEUI = 15015 + + QC_BLTI = 15016 + + QC_BLTUI = 15017 + + QC_BNEI = 15018 + + QC_BREV32 = 15019 + + QC_CLO = 15020 + + QC_CLRINTI = 15021 + + QC_CM_MVA01S = 15022 + + QC_CM_MVSA01 = 15023 + + QC_CM_POP = 15024 + + QC_CM_POPRET = 15025 + + QC_CM_POPRETZ = 15026 + + QC_CM_PUSH = 15027 + + QC_CM_PUSHFP = 15028 + + QC_COMPRESS2 = 15029 + + QC_COMPRESS3 = 15030 + + QC_CSRRWR = 15031 + + QC_CSRRWRI = 15032 + + QC_CTO = 15033 + + QC_C_BEXTI = 15034 + + QC_C_BSETI = 15035 + + QC_C_CLRINT = 15036 + + QC_C_DI = 15037 + + QC_C_DIR = 15038 + + QC_C_EI = 15039 + + QC_C_EIR = 15040 + + QC_C_EXTU = 15041 + + QC_C_MIENTER = 15042 + + QC_C_MIENTER_NEST = 15043 + + QC_C_MILEAVERET = 15044 + + QC_C_MNRET = 15045 + + QC_C_MRET = 15046 + + QC_C_MULIADD = 15047 + + QC_C_MVEQZ = 15048 + + QC_C_SETINT = 15049 + + QC_C_SYNC = 15050 + + QC_C_SYNCR = 15051 + + QC_C_SYNCWF = 15052 + + QC_C_SYNCWL = 15053 + + QC_EXPAND2 = 15054 + + QC_EXPAND3 = 15055 + + QC_EXT = 15056 + + QC_EXTD = 15057 + + QC_EXTDPR = 15058 + + QC_EXTDPRH = 15059 + + QC_EXTDR = 15060 + + QC_EXTDU = 15061 + + QC_EXTDUPR = 15062 + + QC_EXTDUPRH = 15063 + + QC_EXTDUR = 15064 + + QC_EXTU = 15065 + + QC_E_ADDAI = 15066 + + QC_E_ADDI = 15067 + + QC_E_ANDAI = 15068 + + QC_E_ANDI = 15069 + + QC_E_BEQI = 15070 + + QC_E_BGEI = 15071 + + QC_E_BGEUI = 15072 + + QC_E_BLTI = 15073 + + QC_E_BLTUI = 15074 + + QC_E_BNEI = 15075 + + QC_E_J = 15076 + + QC_E_JAL = 15077 + + QC_E_LB = 15078 + + QC_E_LBU = 15079 + + QC_E_LH = 15080 + + QC_E_LHU = 15081 + + QC_E_LI = 15082 + + QC_E_LW = 15083 + + QC_E_ORAI = 15084 + + QC_E_ORI = 15085 + + QC_E_SB = 15086 + + QC_E_SH = 15087 + + QC_E_SW = 15088 + + QC_E_XORAI = 15089 + + QC_E_XORI = 15090 + + QC_INSB = 15091 + + QC_INSBH = 15092 + + QC_INSBHR = 15093 + + QC_INSBI = 15094 + + QC_INSBPR = 15095 + + QC_INSBPRH = 15096 + + QC_INSBR = 15097 + + QC_INSBRI = 15098 + + QC_INW = 15099 + + QC_LI = 15100 + + QC_LIEQ = 15101 + + QC_LIEQI = 15102 + + QC_LIGE = 15103 + + QC_LIGEI = 15104 + + QC_LIGEU = 15105 + + QC_LIGEUI = 15106 + + QC_LILT = 15107 + + QC_LILTI = 15108 + + QC_LILTU = 15109 + + QC_LILTUI = 15110 + + QC_LINE = 15111 + + QC_LINEI = 15112 + + QC_LRB = 15113 + + QC_LRBU = 15114 + + QC_LRH = 15115 + + QC_LRHU = 15116 + + QC_LRW = 15117 + + QC_LWM = 15118 + + QC_LWMI = 15119 + + QC_MULIADD = 15120 + + QC_MVEQ = 15121 + + QC_MVEQI = 15122 + + QC_MVGE = 15123 + + QC_MVGEI = 15124 + + QC_MVGEU = 15125 + + QC_MVGEUI = 15126 + + QC_MVLT = 15127 + + QC_MVLTI = 15128 + + QC_MVLTU = 15129 + + QC_MVLTUI = 15130 + + QC_MVNE = 15131 + + QC_MVNEI = 15132 + + QC_NORM = 15133 + + QC_NORMEU = 15134 + + QC_NORMU = 15135 + + QC_OUTW = 15136 + + QC_PPUTCI = 15137 + + QC_SELECTEQI = 15138 + + QC_SELECTIEQ = 15139 + + QC_SELECTIEQI = 15140 + + QC_SELECTIIEQ = 15141 + + QC_SELECTIINE = 15142 + + QC_SELECTINE = 15143 + + QC_SELECTINEI = 15144 + + QC_SELECTNEI = 15145 + + QC_SETINTI = 15146 + + QC_SETWM = 15147 + + QC_SETWMI = 15148 + + QC_SHLADD = 15149 + + QC_SHLSAT = 15150 + + QC_SHLUSAT = 15151 + + QC_SRB = 15152 + + QC_SRH = 15153 + + QC_SRW = 15154 + + QC_SUBSAT = 15155 + + QC_SUBUSAT = 15156 + + QC_SWM = 15157 + + QC_SWMI = 15158 + + QC_SYNC = 15159 + + QC_SYNCR = 15160 + + QC_SYNCWF = 15161 + + QC_SYNCWL = 15162 + + QC_WRAP = 15163 + + QC_WRAPI = 15164 + + QK_C_LBU = 15165 + + QK_C_LBUSP = 15166 + + QK_C_LHU = 15167 + + QK_C_LHUSP = 15168 + + QK_C_SB = 15169 + + QK_C_SBSP = 15170 + + QK_C_SH = 15171 + + QK_C_SHSP = 15172 + + REM = 15173 + + REMU = 15174 + + REMUW = 15175 + + REMW = 15176 + + REV16 = 15177 + + REV8_RV32 = 15178 + + REV8_RV64 = 15179 + + REV_RV32 = 15180 + + REV_RV64 = 15181 + + RI_VEXTRACT = 15182 + + RI_VINSERT = 15183 + + RI_VUNZIP2A_VV = 15184 + + RI_VUNZIP2B_VV = 15185 + + RI_VZERO = 15186 + + RI_VZIP2A_VV = 15187 + + RI_VZIP2B_VV = 15188 + + RI_VZIPEVEN_VV = 15189 + + RI_VZIPODD_VV = 15190 + + ROL = 15191 + + ROLW = 15192 + + ROR = 15193 + + RORI = 15194 + + RORIW = 15195 + + RORW = 15196 + + SADD = 15197 + + SADDU = 15198 + + SATI_RV32 = 15199 + + SATI_RV64 = 15200 + + SB = 15201 + + SB_AQRL = 15202 + + SB_RL = 15203 + + SCTRCLR = 15204 + + SC_D = 15205 + + SC_D_AQ = 15206 + + SC_D_AQRL = 15207 + + SC_D_RL = 15208 + + SC_W = 15209 + + SC_W_AQ = 15210 + + SC_W_AQRL = 15211 + + SC_W_RL = 15212 + + SD = 15213 + + SD_AQRL = 15214 + + SD_RL = 15215 + + SD_RV32 = 15216 + + SEXT_B = 15217 + + SEXT_H = 15218 + + SFENCE_INVAL_IR = 15219 + + SFENCE_VMA = 15220 + + SFENCE_W_INVAL = 15221 + + SF_CDISCARD_D_L1 = 15222 + + SF_CEASE = 15223 + + SF_CFLUSH_D_L1 = 15224 + + SF_MM_E4M3_E4M3 = 15225 + + SF_MM_E4M3_E5M2 = 15226 + + SF_MM_E5M2_E4M3 = 15227 + + SF_MM_E5M2_E5M2 = 15228 + + SF_MM_F_F = 15229 + + SF_MM_S_S = 15230 + + SF_MM_S_U = 15231 + + SF_MM_U_S = 15232 + + SF_MM_U_U = 15233 + + SF_VC_FV = 15234 + + SF_VC_FVV = 15235 + + SF_VC_FVW = 15236 + + SF_VC_I = 15237 + + SF_VC_IV = 15238 + + SF_VC_IVV = 15239 + + SF_VC_IVW = 15240 + + SF_VC_VV = 15241 + + SF_VC_VVV = 15242 + + SF_VC_VVW = 15243 + + SF_VC_V_FV = 15244 + + SF_VC_V_FVV = 15245 + + SF_VC_V_FVW = 15246 + + SF_VC_V_I = 15247 + + SF_VC_V_IV = 15248 + + SF_VC_V_IVV = 15249 + + SF_VC_V_IVW = 15250 + + SF_VC_V_VV = 15251 + + SF_VC_V_VVV = 15252 + + SF_VC_V_VVW = 15253 + + SF_VC_V_X = 15254 + + SF_VC_V_XV = 15255 + + SF_VC_V_XVV = 15256 + + SF_VC_V_XVW = 15257 + + SF_VC_X = 15258 + + SF_VC_XV = 15259 + + SF_VC_XVV = 15260 + + SF_VC_XVW = 15261 + + SF_VFEXPA_V = 15262 + + SF_VFEXP_V = 15263 + + SF_VFNRCLIP_XU_F_QF = 15264 + + SF_VFNRCLIP_X_F_QF = 15265 + + SF_VFWMACC_4x4x4 = 15266 + + SF_VLTE16 = 15267 + + SF_VLTE32 = 15268 + + SF_VLTE64 = 15269 + + SF_VLTE8 = 15270 + + SF_VQMACCSU_2x8x2 = 15271 + + SF_VQMACCSU_4x8x4 = 15272 + + SF_VQMACCUS_2x8x2 = 15273 + + SF_VQMACCUS_4x8x4 = 15274 + + SF_VQMACCU_2x8x2 = 15275 + + SF_VQMACCU_4x8x4 = 15276 + + SF_VQMACC_2x8x2 = 15277 + + SF_VQMACC_4x8x4 = 15278 + + SF_VSETTK = 15279 + + SF_VSETTM = 15280 + + SF_VSETTN = 15281 + + SF_VSTE16 = 15282 + + SF_VSTE32 = 15283 + + SF_VSTE64 = 15284 + + SF_VSTE8 = 15285 + + SF_VTDISCARD = 15286 + + SF_VTMV_T_V = 15287 + + SF_VTMV_V_T = 15288 + + SF_VTZERO_T = 15289 + + SH = 15290 + + SH1ADD = 15291 + + SH1ADD_UW = 15292 + + SH2ADD = 15293 + + SH2ADD_UW = 15294 + + SH3ADD = 15295 + + SH3ADD_UW = 15296 + + SHA = 15297 + + SHA256SIG0 = 15298 + + SHA256SIG1 = 15299 + + SHA256SUM0 = 15300 + + SHA256SUM1 = 15301 + + SHA512SIG0 = 15302 + + SHA512SIG0H = 15303 + + SHA512SIG0L = 15304 + + SHA512SIG1 = 15305 + + SHA512SIG1H = 15306 + + SHA512SIG1L = 15307 + + SHA512SUM0 = 15308 + + SHA512SUM0R = 15309 + + SHA512SUM1 = 15310 + + SHA512SUM1R = 15311 + + SHAR = 15312 + + SH_AQRL = 15313 + + SH_INX = 15314 + + SH_RL = 15315 + + SINVAL_VMA = 15316 + + SLL = 15317 + + SLLI = 15318 + + SLLIW = 15319 + + SLLI_UW = 15320 + + SLLW = 15321 + + SLT = 15322 + + SLTI = 15323 + + SLTIU = 15324 + + SLTU = 15325 + + SLX = 15326 + + SM3P0 = 15327 + + SM3P1 = 15328 + + SM4ED = 15329 + + SM4KS = 15330 + + SMT_VMADOT = 15331 + + SMT_VMADOT1 = 15332 + + SMT_VMADOT1SU = 15333 + + SMT_VMADOT1U = 15334 + + SMT_VMADOT1US = 15335 + + SMT_VMADOT2 = 15336 + + SMT_VMADOT2SU = 15337 + + SMT_VMADOT2U = 15338 + + SMT_VMADOT2US = 15339 + + SMT_VMADOT3 = 15340 + + SMT_VMADOT3SU = 15341 + + SMT_VMADOT3U = 15342 + + SMT_VMADOT3US = 15343 + + SMT_VMADOTSU = 15344 + + SMT_VMADOTU = 15345 + + SMT_VMADOTUS = 15346 + + SRA = 15347 + + SRAI = 15348 + + SRAIW = 15349 + + SRARI_RV32 = 15350 + + SRARI_RV64 = 15351 + + SRAW = 15352 + + SRET = 15353 + + SRL = 15354 + + SRLI = 15355 + + SRLIW = 15356 + + SRLW = 15357 + + SRX = 15358 + + SSAMOSWAP_D = 15359 + + SSAMOSWAP_D_AQ = 15360 + + SSAMOSWAP_D_AQRL = 15361 + + SSAMOSWAP_D_RL = 15362 + + SSAMOSWAP_W = 15363 + + SSAMOSWAP_W_AQ = 15364 + + SSAMOSWAP_W_AQRL = 15365 + + SSAMOSWAP_W_RL = 15366 + + SSH1SADD = 15367 + + SSHA = 15368 + + SSHAR = 15369 + + SSLAI = 15370 + + SSPOPCHK = 15371 + + SSPUSH = 15372 + + SSRDP = 15373 + + SSUB = 15374 + + SSUBU = 15375 + + SUB = 15376 + + SUBD = 15377 + + SUBW = 15378 + + SW = 15379 + + SW_AQRL = 15380 + + SW_INX = 15381 + + SW_RL = 15382 + + TH_ADDSL = 15383 + + TH_DCACHE_CALL = 15384 + + TH_DCACHE_CIALL = 15385 + + TH_DCACHE_CIPA = 15386 + + TH_DCACHE_CISW = 15387 + + TH_DCACHE_CIVA = 15388 + + TH_DCACHE_CPA = 15389 + + TH_DCACHE_CPAL1 = 15390 + + TH_DCACHE_CSW = 15391 + + TH_DCACHE_CVA = 15392 + + TH_DCACHE_CVAL1 = 15393 + + TH_DCACHE_IALL = 15394 + + TH_DCACHE_IPA = 15395 + + TH_DCACHE_ISW = 15396 + + TH_DCACHE_IVA = 15397 + + TH_EXT = 15398 + + TH_EXTU = 15399 + + TH_FF0 = 15400 + + TH_FF1 = 15401 + + TH_FLRD = 15402 + + TH_FLRW = 15403 + + TH_FLURD = 15404 + + TH_FLURW = 15405 + + TH_FSRD = 15406 + + TH_FSRW = 15407 + + TH_FSURD = 15408 + + TH_FSURW = 15409 + + TH_ICACHE_IALL = 15410 + + TH_ICACHE_IALLS = 15411 + + TH_ICACHE_IPA = 15412 + + TH_ICACHE_IVA = 15413 + + TH_L2CACHE_CALL = 15414 + + TH_L2CACHE_CIALL = 15415 + + TH_L2CACHE_IALL = 15416 + + TH_LBIA = 15417 + + TH_LBIB = 15418 + + TH_LBUIA = 15419 + + TH_LBUIB = 15420 + + TH_LDD = 15421 + + TH_LDIA = 15422 + + TH_LDIB = 15423 + + TH_LHIA = 15424 + + TH_LHIB = 15425 + + TH_LHUIA = 15426 + + TH_LHUIB = 15427 + + TH_LRB = 15428 + + TH_LRBU = 15429 + + TH_LRD = 15430 + + TH_LRH = 15431 + + TH_LRHU = 15432 + + TH_LRW = 15433 + + TH_LRWU = 15434 + + TH_LURB = 15435 + + TH_LURBU = 15436 + + TH_LURD = 15437 + + TH_LURH = 15438 + + TH_LURHU = 15439 + + TH_LURW = 15440 + + TH_LURWU = 15441 + + TH_LWD = 15442 + + TH_LWIA = 15443 + + TH_LWIB = 15444 + + TH_LWUD = 15445 + + TH_LWUIA = 15446 + + TH_LWUIB = 15447 + + TH_MULA = 15448 + + TH_MULAH = 15449 + + TH_MULAW = 15450 + + TH_MULS = 15451 + + TH_MULSH = 15452 + + TH_MULSW = 15453 + + TH_MVEQZ = 15454 + + TH_MVNEZ = 15455 + + TH_REV = 15456 + + TH_REVW = 15457 + + TH_SBIA = 15458 + + TH_SBIB = 15459 + + TH_SDD = 15460 + + TH_SDIA = 15461 + + TH_SDIB = 15462 + + TH_SFENCE_VMAS = 15463 + + TH_SHIA = 15464 + + TH_SHIB = 15465 + + TH_SRB = 15466 + + TH_SRD = 15467 + + TH_SRH = 15468 + + TH_SRRI = 15469 + + TH_SRRIW = 15470 + + TH_SRW = 15471 + + TH_SURB = 15472 + + TH_SURD = 15473 + + TH_SURH = 15474 + + TH_SURW = 15475 + + TH_SWD = 15476 + + TH_SWIA = 15477 + + TH_SWIB = 15478 + + TH_SYNC = 15479 + + TH_SYNC_I = 15480 + + TH_SYNC_IS = 15481 + + TH_SYNC_S = 15482 + + TH_TST = 15483 + + TH_TSTNBZ = 15484 + + TH_VMAQASU_VV = 15485 + + TH_VMAQASU_VX = 15486 + + TH_VMAQAUS_VX = 15487 + + TH_VMAQAU_VV = 15488 + + TH_VMAQAU_VX = 15489 + + TH_VMAQA_VV = 15490 + + TH_VMAQA_VX = 15491 + + UNIMP = 15492 + + UNZIP16HP = 15493 + + UNZIP16P = 15494 + + UNZIP8HP = 15495 + + UNZIP8P = 15496 + + UNZIP_RV32 = 15497 + + USATI_RV32 = 15498 + + USATI_RV64 = 15499 + + VAADDU_VV = 15500 + + VAADDU_VX = 15501 + + VAADD_VV = 15502 + + VAADD_VX = 15503 + + VADC_VIM = 15504 + + VADC_VVM = 15505 + + VADC_VXM = 15506 + + VADD_VI = 15507 + + VADD_VV = 15508 + + VADD_VX = 15509 + + VAESDF_VS = 15510 + + VAESDF_VV = 15511 + + VAESDM_VS = 15512 + + VAESDM_VV = 15513 + + VAESEF_VS = 15514 + + VAESEF_VV = 15515 + + VAESEM_VS = 15516 + + VAESEM_VV = 15517 + + VAESKF1_VI = 15518 + + VAESKF2_VI = 15519 + + VAESZ_VS = 15520 + + VANDN_VV = 15521 + + VANDN_VX = 15522 + + VAND_VI = 15523 + + VAND_VV = 15524 + + VAND_VX = 15525 + + VASUBU_VV = 15526 + + VASUBU_VX = 15527 + + VASUB_VV = 15528 + + VASUB_VX = 15529 + + VBREV8_V = 15530 + + VBREV_V = 15531 + + VCLMULH_VV = 15532 + + VCLMULH_VX = 15533 + + VCLMUL_VV = 15534 + + VCLMUL_VX = 15535 + + VCLZ_V = 15536 + + VCOMPRESS_VM = 15537 + + VCPOP_M = 15538 + + VCPOP_V = 15539 + + VCTZ_V = 15540 + + VDIVU_VV = 15541 + + VDIVU_VX = 15542 + + VDIV_VV = 15543 + + VDIV_VX = 15544 + + VFADD_VF = 15545 + + VFADD_VV = 15546 + + VFCLASS_V = 15547 + + VFCVT_F_XU_V = 15548 + + VFCVT_F_X_V = 15549 + + VFCVT_RTZ_XU_F_V = 15550 + + VFCVT_RTZ_X_F_V = 15551 + + VFCVT_XU_F_V = 15552 + + VFCVT_X_F_V = 15553 + + VFDIV_VF = 15554 + + VFDIV_VV = 15555 + + VFIRST_M = 15556 + + VFMACC_VF = 15557 + + VFMACC_VV = 15558 + + VFMADD_VF = 15559 + + VFMADD_VV = 15560 + + VFMAX_VF = 15561 + + VFMAX_VV = 15562 + + VFMERGE_VFM = 15563 + + VFMIN_VF = 15564 + + VFMIN_VV = 15565 + + VFMSAC_VF = 15566 + + VFMSAC_VV = 15567 + + VFMSUB_VF = 15568 + + VFMSUB_VV = 15569 + + VFMUL_VF = 15570 + + VFMUL_VV = 15571 + + VFMV_F_S = 15572 + + VFMV_S_F = 15573 + + VFMV_V_F = 15574 + + VFNCVTBF16_F_F_W = 15575 + + VFNCVTBF16_SAT_F_F_W = 15576 + + VFNCVT_F_F_Q = 15577 + + VFNCVT_F_F_W = 15578 + + VFNCVT_F_XU_W = 15579 + + VFNCVT_F_X_W = 15580 + + VFNCVT_ROD_F_F_W = 15581 + + VFNCVT_RTZ_XU_F_W = 15582 + + VFNCVT_RTZ_X_F_W = 15583 + + VFNCVT_SAT_F_F_Q = 15584 + + VFNCVT_XU_F_W = 15585 + + VFNCVT_X_F_W = 15586 + + VFNMACC_VF = 15587 + + VFNMACC_VV = 15588 + + VFNMADD_VF = 15589 + + VFNMADD_VV = 15590 + + VFNMSAC_VF = 15591 + + VFNMSAC_VV = 15592 + + VFNMSUB_VF = 15593 + + VFNMSUB_VV = 15594 + + VFRDIV_VF = 15595 + + VFREC7_V = 15596 + + VFREDMAX_VS = 15597 + + VFREDMIN_VS = 15598 + + VFREDOSUM_VS = 15599 + + VFREDUSUM_VS = 15600 + + VFRSQRT7_V = 15601 + + VFRSUB_VF = 15602 + + VFSGNJN_VF = 15603 + + VFSGNJN_VV = 15604 + + VFSGNJX_VF = 15605 + + VFSGNJX_VV = 15606 + + VFSGNJ_VF = 15607 + + VFSGNJ_VV = 15608 + + VFSLIDE1DOWN_VF = 15609 + + VFSLIDE1UP_VF = 15610 + + VFSQRT_V = 15611 + + VFSUB_VF = 15612 + + VFSUB_VV = 15613 + + VFWADD_VF = 15614 + + VFWADD_VV = 15615 + + VFWADD_WF = 15616 + + VFWADD_WV = 15617 + + VFWCVTBF16_F_F_V = 15618 + + VFWCVT_F_F_V = 15619 + + VFWCVT_F_XU_V = 15620 + + VFWCVT_F_X_V = 15621 + + VFWCVT_RTZ_XU_F_V = 15622 + + VFWCVT_RTZ_X_F_V = 15623 + + VFWCVT_XU_F_V = 15624 + + VFWCVT_X_F_V = 15625 + + VFWMACCBF16_VF = 15626 + + VFWMACCBF16_VV = 15627 + + VFWMACC_VF = 15628 + + VFWMACC_VV = 15629 + + VFWMSAC_VF = 15630 + + VFWMSAC_VV = 15631 + + VFWMUL_VF = 15632 + + VFWMUL_VV = 15633 + + VFWNMACC_VF = 15634 + + VFWNMACC_VV = 15635 + + VFWNMSAC_VF = 15636 + + VFWNMSAC_VV = 15637 + + VFWREDOSUM_VS = 15638 + + VFWREDUSUM_VS = 15639 + + VFWSUB_VF = 15640 + + VFWSUB_VV = 15641 + + VFWSUB_WF = 15642 + + VFWSUB_WV = 15643 + + VGHSH_VS = 15644 + + VGHSH_VV = 15645 + + VGMUL_VS = 15646 + + VGMUL_VV = 15647 + + VID_V = 15648 + + VIOTA_M = 15649 + + VL1RE16_V = 15650 + + VL1RE32_V = 15651 + + VL1RE64_V = 15652 + + VL1RE8_V = 15653 + + VL2RE16_V = 15654 + + VL2RE32_V = 15655 + + VL2RE64_V = 15656 + + VL2RE8_V = 15657 + + VL4RE16_V = 15658 + + VL4RE32_V = 15659 + + VL4RE64_V = 15660 + + VL4RE8_V = 15661 + + VL8RE16_V = 15662 + + VL8RE32_V = 15663 + + VL8RE64_V = 15664 + + VL8RE8_V = 15665 + + VLE16FF_V = 15666 + + VLE16_V = 15667 + + VLE32FF_V = 15668 + + VLE32_V = 15669 + + VLE64FF_V = 15670 + + VLE64_V = 15671 + + VLE8FF_V = 15672 + + VLE8_V = 15673 + + VLM_V = 15674 + + VLOXEI16_V = 15675 + + VLOXEI32_V = 15676 + + VLOXEI64_V = 15677 + + VLOXEI8_V = 15678 + + VLOXSEG2EI16_V = 15679 + + VLOXSEG2EI32_V = 15680 + + VLOXSEG2EI64_V = 15681 + + VLOXSEG2EI8_V = 15682 + + VLOXSEG3EI16_V = 15683 + + VLOXSEG3EI32_V = 15684 + + VLOXSEG3EI64_V = 15685 + + VLOXSEG3EI8_V = 15686 + + VLOXSEG4EI16_V = 15687 + + VLOXSEG4EI32_V = 15688 + + VLOXSEG4EI64_V = 15689 + + VLOXSEG4EI8_V = 15690 + + VLOXSEG5EI16_V = 15691 + + VLOXSEG5EI32_V = 15692 + + VLOXSEG5EI64_V = 15693 + + VLOXSEG5EI8_V = 15694 + + VLOXSEG6EI16_V = 15695 + + VLOXSEG6EI32_V = 15696 + + VLOXSEG6EI64_V = 15697 + + VLOXSEG6EI8_V = 15698 + + VLOXSEG7EI16_V = 15699 + + VLOXSEG7EI32_V = 15700 + + VLOXSEG7EI64_V = 15701 + + VLOXSEG7EI8_V = 15702 + + VLOXSEG8EI16_V = 15703 + + VLOXSEG8EI32_V = 15704 + + VLOXSEG8EI64_V = 15705 + + VLOXSEG8EI8_V = 15706 + + VLSE16_V = 15707 + + VLSE32_V = 15708 + + VLSE64_V = 15709 + + VLSE8_V = 15710 + + VLSEG2E16FF_V = 15711 + + VLSEG2E16_V = 15712 + + VLSEG2E32FF_V = 15713 + + VLSEG2E32_V = 15714 + + VLSEG2E64FF_V = 15715 + + VLSEG2E64_V = 15716 + + VLSEG2E8FF_V = 15717 + + VLSEG2E8_V = 15718 + + VLSEG3E16FF_V = 15719 + + VLSEG3E16_V = 15720 + + VLSEG3E32FF_V = 15721 + + VLSEG3E32_V = 15722 + + VLSEG3E64FF_V = 15723 + + VLSEG3E64_V = 15724 + + VLSEG3E8FF_V = 15725 + + VLSEG3E8_V = 15726 + + VLSEG4E16FF_V = 15727 + + VLSEG4E16_V = 15728 + + VLSEG4E32FF_V = 15729 + + VLSEG4E32_V = 15730 + + VLSEG4E64FF_V = 15731 + + VLSEG4E64_V = 15732 + + VLSEG4E8FF_V = 15733 + + VLSEG4E8_V = 15734 + + VLSEG5E16FF_V = 15735 + + VLSEG5E16_V = 15736 + + VLSEG5E32FF_V = 15737 + + VLSEG5E32_V = 15738 + + VLSEG5E64FF_V = 15739 + + VLSEG5E64_V = 15740 + + VLSEG5E8FF_V = 15741 + + VLSEG5E8_V = 15742 + + VLSEG6E16FF_V = 15743 + + VLSEG6E16_V = 15744 + + VLSEG6E32FF_V = 15745 + + VLSEG6E32_V = 15746 + + VLSEG6E64FF_V = 15747 + + VLSEG6E64_V = 15748 + + VLSEG6E8FF_V = 15749 + + VLSEG6E8_V = 15750 + + VLSEG7E16FF_V = 15751 + + VLSEG7E16_V = 15752 + + VLSEG7E32FF_V = 15753 + + VLSEG7E32_V = 15754 + + VLSEG7E64FF_V = 15755 + + VLSEG7E64_V = 15756 + + VLSEG7E8FF_V = 15757 + + VLSEG7E8_V = 15758 + + VLSEG8E16FF_V = 15759 + + VLSEG8E16_V = 15760 + + VLSEG8E32FF_V = 15761 + + VLSEG8E32_V = 15762 + + VLSEG8E64FF_V = 15763 + + VLSEG8E64_V = 15764 + + VLSEG8E8FF_V = 15765 + + VLSEG8E8_V = 15766 + + VLSSEG2E16_V = 15767 + + VLSSEG2E32_V = 15768 + + VLSSEG2E64_V = 15769 + + VLSSEG2E8_V = 15770 + + VLSSEG3E16_V = 15771 + + VLSSEG3E32_V = 15772 + + VLSSEG3E64_V = 15773 + + VLSSEG3E8_V = 15774 + + VLSSEG4E16_V = 15775 + + VLSSEG4E32_V = 15776 + + VLSSEG4E64_V = 15777 + + VLSSEG4E8_V = 15778 + + VLSSEG5E16_V = 15779 + + VLSSEG5E32_V = 15780 + + VLSSEG5E64_V = 15781 + + VLSSEG5E8_V = 15782 + + VLSSEG6E16_V = 15783 + + VLSSEG6E32_V = 15784 + + VLSSEG6E64_V = 15785 + + VLSSEG6E8_V = 15786 + + VLSSEG7E16_V = 15787 + + VLSSEG7E32_V = 15788 + + VLSSEG7E64_V = 15789 + + VLSSEG7E8_V = 15790 + + VLSSEG8E16_V = 15791 + + VLSSEG8E32_V = 15792 + + VLSSEG8E64_V = 15793 + + VLSSEG8E8_V = 15794 + + VLUXEI16_V = 15795 + + VLUXEI32_V = 15796 + + VLUXEI64_V = 15797 + + VLUXEI8_V = 15798 + + VLUXSEG2EI16_V = 15799 + + VLUXSEG2EI32_V = 15800 + + VLUXSEG2EI64_V = 15801 + + VLUXSEG2EI8_V = 15802 + + VLUXSEG3EI16_V = 15803 + + VLUXSEG3EI32_V = 15804 + + VLUXSEG3EI64_V = 15805 + + VLUXSEG3EI8_V = 15806 + + VLUXSEG4EI16_V = 15807 + + VLUXSEG4EI32_V = 15808 + + VLUXSEG4EI64_V = 15809 + + VLUXSEG4EI8_V = 15810 + + VLUXSEG5EI16_V = 15811 + + VLUXSEG5EI32_V = 15812 + + VLUXSEG5EI64_V = 15813 + + VLUXSEG5EI8_V = 15814 + + VLUXSEG6EI16_V = 15815 + + VLUXSEG6EI32_V = 15816 + + VLUXSEG6EI64_V = 15817 + + VLUXSEG6EI8_V = 15818 + + VLUXSEG7EI16_V = 15819 + + VLUXSEG7EI32_V = 15820 + + VLUXSEG7EI64_V = 15821 + + VLUXSEG7EI8_V = 15822 + + VLUXSEG8EI16_V = 15823 + + VLUXSEG8EI32_V = 15824 + + VLUXSEG8EI64_V = 15825 + + VLUXSEG8EI8_V = 15826 + + VMACC_VV = 15827 + + VMACC_VX = 15828 + + VMADC_VI = 15829 + + VMADC_VIM = 15830 + + VMADC_VV = 15831 + + VMADC_VVM = 15832 + + VMADC_VX = 15833 + + VMADC_VXM = 15834 + + VMADD_VV = 15835 + + VMADD_VX = 15836 + + VMANDN_MM = 15837 + + VMAND_MM = 15838 + + VMAXU_VV = 15839 + + VMAXU_VX = 15840 + + VMAX_VV = 15841 + + VMAX_VX = 15842 + + VMERGE_VIM = 15843 + + VMERGE_VVM = 15844 + + VMERGE_VXM = 15845 + + VMFEQ_VF = 15846 + + VMFEQ_VV = 15847 + + VMFGE_VF = 15848 + + VMFGT_VF = 15849 + + VMFLE_VF = 15850 + + VMFLE_VV = 15851 + + VMFLT_VF = 15852 + + VMFLT_VV = 15853 + + VMFNE_VF = 15854 + + VMFNE_VV = 15855 + + VMINU_VV = 15856 + + VMINU_VX = 15857 + + VMIN_VV = 15858 + + VMIN_VX = 15859 + + VMNAND_MM = 15860 + + VMNOR_MM = 15861 + + VMORN_MM = 15862 + + VMOR_MM = 15863 + + VMSBC_VV = 15864 + + VMSBC_VVM = 15865 + + VMSBC_VX = 15866 + + VMSBC_VXM = 15867 + + VMSBF_M = 15868 + + VMSEQ_VI = 15869 + + VMSEQ_VV = 15870 + + VMSEQ_VX = 15871 + + VMSGTU_VI = 15872 + + VMSGTU_VX = 15873 + + VMSGT_VI = 15874 + + VMSGT_VX = 15875 + + VMSIF_M = 15876 + + VMSLEU_VI = 15877 + + VMSLEU_VV = 15878 + + VMSLEU_VX = 15879 + + VMSLE_VI = 15880 + + VMSLE_VV = 15881 + + VMSLE_VX = 15882 + + VMSLTU_VV = 15883 + + VMSLTU_VX = 15884 + + VMSLT_VV = 15885 + + VMSLT_VX = 15886 + + VMSNE_VI = 15887 + + VMSNE_VV = 15888 + + VMSNE_VX = 15889 + + VMSOF_M = 15890 + + VMULHSU_VV = 15891 + + VMULHSU_VX = 15892 + + VMULHU_VV = 15893 + + VMULHU_VX = 15894 + + VMULH_VV = 15895 + + VMULH_VX = 15896 + + VMUL_VV = 15897 + + VMUL_VX = 15898 + + VMV1R_V = 15899 + + VMV2R_V = 15900 + + VMV4R_V = 15901 + + VMV8R_V = 15902 + + VMV_S_X = 15903 + + VMV_V_I = 15904 + + VMV_V_V = 15905 + + VMV_V_X = 15906 + + VMV_X_S = 15907 + + VMXNOR_MM = 15908 + + VMXOR_MM = 15909 + + VNCLIPU_WI = 15910 + + VNCLIPU_WV = 15911 + + VNCLIPU_WX = 15912 + + VNCLIP_WI = 15913 + + VNCLIP_WV = 15914 + + VNCLIP_WX = 15915 + + VNMSAC_VV = 15916 + + VNMSAC_VX = 15917 + + VNMSUB_VV = 15918 + + VNMSUB_VX = 15919 + + VNSRA_WI = 15920 + + VNSRA_WV = 15921 + + VNSRA_WX = 15922 + + VNSRL_WI = 15923 + + VNSRL_WV = 15924 + + VNSRL_WX = 15925 + + VOR_VI = 15926 + + VOR_VV = 15927 + + VOR_VX = 15928 + + VQDOTSU_VV = 15929 + + VQDOTSU_VX = 15930 + + VQDOTUS_VX = 15931 + + VQDOTU_VV = 15932 + + VQDOTU_VX = 15933 + + VQDOT_VV = 15934 + + VQDOT_VX = 15935 + + VREDAND_VS = 15936 + + VREDMAXU_VS = 15937 + + VREDMAX_VS = 15938 + + VREDMINU_VS = 15939 + + VREDMIN_VS = 15940 + + VREDOR_VS = 15941 + + VREDSUM_VS = 15942 + + VREDXOR_VS = 15943 + + VREMU_VV = 15944 + + VREMU_VX = 15945 + + VREM_VV = 15946 + + VREM_VX = 15947 + + VREV8_V = 15948 + + VRGATHEREI16_VV = 15949 + + VRGATHER_VI = 15950 + + VRGATHER_VV = 15951 + + VRGATHER_VX = 15952 + + VROL_VV = 15953 + + VROL_VX = 15954 + + VROR_VI = 15955 + + VROR_VV = 15956 + + VROR_VX = 15957 + + VRSUB_VI = 15958 + + VRSUB_VX = 15959 + + VS1R_V = 15960 + + VS2R_V = 15961 + + VS4R_V = 15962 + + VS8R_V = 15963 + + VSADDU_VI = 15964 + + VSADDU_VV = 15965 + + VSADDU_VX = 15966 + + VSADD_VI = 15967 + + VSADD_VV = 15968 + + VSADD_VX = 15969 + + VSBC_VVM = 15970 + + VSBC_VXM = 15971 + + VSE16_V = 15972 + + VSE32_V = 15973 + + VSE64_V = 15974 + + VSE8_V = 15975 + + VSETIVLI = 15976 + + VSETVL = 15977 + + VSETVLI = 15978 + + VSEXT_VF2 = 15979 + + VSEXT_VF4 = 15980 + + VSEXT_VF8 = 15981 + + VSHA2CH_VV = 15982 + + VSHA2CL_VV = 15983 + + VSHA2MS_VV = 15984 + + VSLIDE1DOWN_VX = 15985 + + VSLIDE1UP_VX = 15986 + + VSLIDEDOWN_VI = 15987 + + VSLIDEDOWN_VX = 15988 + + VSLIDEUP_VI = 15989 + + VSLIDEUP_VX = 15990 + + VSLL_VI = 15991 + + VSLL_VV = 15992 + + VSLL_VX = 15993 + + VSM3C_VI = 15994 + + VSM3ME_VV = 15995 + + VSM4K_VI = 15996 + + VSM4R_VS = 15997 + + VSM4R_VV = 15998 + + VSMUL_VV = 15999 + + VSMUL_VX = 16000 + + VSM_V = 16001 + + VSOXEI16_V = 16002 + + VSOXEI32_V = 16003 + + VSOXEI64_V = 16004 + + VSOXEI8_V = 16005 + + VSOXSEG2EI16_V = 16006 + + VSOXSEG2EI32_V = 16007 + + VSOXSEG2EI64_V = 16008 + + VSOXSEG2EI8_V = 16009 + + VSOXSEG3EI16_V = 16010 + + VSOXSEG3EI32_V = 16011 + + VSOXSEG3EI64_V = 16012 + + VSOXSEG3EI8_V = 16013 + + VSOXSEG4EI16_V = 16014 + + VSOXSEG4EI32_V = 16015 + + VSOXSEG4EI64_V = 16016 + + VSOXSEG4EI8_V = 16017 + + VSOXSEG5EI16_V = 16018 + + VSOXSEG5EI32_V = 16019 + + VSOXSEG5EI64_V = 16020 + + VSOXSEG5EI8_V = 16021 + + VSOXSEG6EI16_V = 16022 + + VSOXSEG6EI32_V = 16023 + + VSOXSEG6EI64_V = 16024 + + VSOXSEG6EI8_V = 16025 + + VSOXSEG7EI16_V = 16026 + + VSOXSEG7EI32_V = 16027 + + VSOXSEG7EI64_V = 16028 + + VSOXSEG7EI8_V = 16029 + + VSOXSEG8EI16_V = 16030 + + VSOXSEG8EI32_V = 16031 + + VSOXSEG8EI64_V = 16032 + + VSOXSEG8EI8_V = 16033 + + VSRA_VI = 16034 + + VSRA_VV = 16035 + + VSRA_VX = 16036 + + VSRL_VI = 16037 + + VSRL_VV = 16038 + + VSRL_VX = 16039 + + VSSE16_V = 16040 + + VSSE32_V = 16041 + + VSSE64_V = 16042 + + VSSE8_V = 16043 + + VSSEG2E16_V = 16044 + + VSSEG2E32_V = 16045 + + VSSEG2E64_V = 16046 + + VSSEG2E8_V = 16047 + + VSSEG3E16_V = 16048 + + VSSEG3E32_V = 16049 + + VSSEG3E64_V = 16050 + + VSSEG3E8_V = 16051 + + VSSEG4E16_V = 16052 + + VSSEG4E32_V = 16053 + + VSSEG4E64_V = 16054 + + VSSEG4E8_V = 16055 + + VSSEG5E16_V = 16056 + + VSSEG5E32_V = 16057 + + VSSEG5E64_V = 16058 + + VSSEG5E8_V = 16059 + + VSSEG6E16_V = 16060 + + VSSEG6E32_V = 16061 + + VSSEG6E64_V = 16062 + + VSSEG6E8_V = 16063 + + VSSEG7E16_V = 16064 + + VSSEG7E32_V = 16065 + + VSSEG7E64_V = 16066 + + VSSEG7E8_V = 16067 + + VSSEG8E16_V = 16068 + + VSSEG8E32_V = 16069 + + VSSEG8E64_V = 16070 + + VSSEG8E8_V = 16071 + + VSSRA_VI = 16072 + + VSSRA_VV = 16073 + + VSSRA_VX = 16074 + + VSSRL_VI = 16075 + + VSSRL_VV = 16076 + + VSSRL_VX = 16077 + + VSSSEG2E16_V = 16078 + + VSSSEG2E32_V = 16079 + + VSSSEG2E64_V = 16080 + + VSSSEG2E8_V = 16081 + + VSSSEG3E16_V = 16082 + + VSSSEG3E32_V = 16083 + + VSSSEG3E64_V = 16084 + + VSSSEG3E8_V = 16085 + + VSSSEG4E16_V = 16086 + + VSSSEG4E32_V = 16087 + + VSSSEG4E64_V = 16088 + + VSSSEG4E8_V = 16089 + + VSSSEG5E16_V = 16090 + + VSSSEG5E32_V = 16091 + + VSSSEG5E64_V = 16092 + + VSSSEG5E8_V = 16093 + + VSSSEG6E16_V = 16094 + + VSSSEG6E32_V = 16095 + + VSSSEG6E64_V = 16096 + + VSSSEG6E8_V = 16097 + + VSSSEG7E16_V = 16098 + + VSSSEG7E32_V = 16099 + + VSSSEG7E64_V = 16100 + + VSSSEG7E8_V = 16101 + + VSSSEG8E16_V = 16102 + + VSSSEG8E32_V = 16103 + + VSSSEG8E64_V = 16104 + + VSSSEG8E8_V = 16105 + + VSSUBU_VV = 16106 + + VSSUBU_VX = 16107 + + VSSUB_VV = 16108 + + VSSUB_VX = 16109 + + VSUB_VV = 16110 + + VSUB_VX = 16111 + + VSUXEI16_V = 16112 + + VSUXEI32_V = 16113 + + VSUXEI64_V = 16114 + + VSUXEI8_V = 16115 + + VSUXSEG2EI16_V = 16116 + + VSUXSEG2EI32_V = 16117 + + VSUXSEG2EI64_V = 16118 + + VSUXSEG2EI8_V = 16119 + + VSUXSEG3EI16_V = 16120 + + VSUXSEG3EI32_V = 16121 + + VSUXSEG3EI64_V = 16122 + + VSUXSEG3EI8_V = 16123 + + VSUXSEG4EI16_V = 16124 + + VSUXSEG4EI32_V = 16125 + + VSUXSEG4EI64_V = 16126 + + VSUXSEG4EI8_V = 16127 + + VSUXSEG5EI16_V = 16128 + + VSUXSEG5EI32_V = 16129 + + VSUXSEG5EI64_V = 16130 + + VSUXSEG5EI8_V = 16131 + + VSUXSEG6EI16_V = 16132 + + VSUXSEG6EI32_V = 16133 + + VSUXSEG6EI64_V = 16134 + + VSUXSEG6EI8_V = 16135 + + VSUXSEG7EI16_V = 16136 + + VSUXSEG7EI32_V = 16137 + + VSUXSEG7EI64_V = 16138 + + VSUXSEG7EI8_V = 16139 + + VSUXSEG8EI16_V = 16140 + + VSUXSEG8EI32_V = 16141 + + VSUXSEG8EI64_V = 16142 + + VSUXSEG8EI8_V = 16143 + + VT_MASKC = 16144 + + VT_MASKCN = 16145 + + VWADDU_VV = 16146 + + VWADDU_VX = 16147 + + VWADDU_WV = 16148 + + VWADDU_WX = 16149 + + VWADD_VV = 16150 + + VWADD_VX = 16151 + + VWADD_WV = 16152 + + VWADD_WX = 16153 + + VWMACCSU_VV = 16154 + + VWMACCSU_VX = 16155 + + VWMACCUS_VX = 16156 + + VWMACCU_VV = 16157 + + VWMACCU_VX = 16158 + + VWMACC_VV = 16159 + + VWMACC_VX = 16160 + + VWMULSU_VV = 16161 + + VWMULSU_VX = 16162 + + VWMULU_VV = 16163 + + VWMULU_VX = 16164 + + VWMUL_VV = 16165 + + VWMUL_VX = 16166 + + VWREDSUMU_VS = 16167 + + VWREDSUM_VS = 16168 + + VWSLL_VI = 16169 + + VWSLL_VV = 16170 + + VWSLL_VX = 16171 + + VWSUBU_VV = 16172 + + VWSUBU_VX = 16173 + + VWSUBU_WV = 16174 + + VWSUBU_WX = 16175 + + VWSUB_VV = 16176 + + VWSUB_VX = 16177 + + VWSUB_WV = 16178 + + VWSUB_WX = 16179 + + VXOR_VI = 16180 + + VXOR_VV = 16181 + + VXOR_VX = 16182 + + VZEXT_VF2 = 16183 + + VZEXT_VF4 = 16184 + + VZEXT_VF8 = 16185 + + WADD = 16186 + + WADDA = 16187 + + WADDAU = 16188 + + WADDU = 16189 + + WFI = 16190 + + WMACC = 16191 + + WMACCSU = 16192 + + WMACCU = 16193 + + WMUL = 16194 + + WMULSU = 16195 + + WMULU = 16196 + + WRS_NTO = 16197 + + WRS_STO = 16198 + + WSLA = 16199 + + WSLAI = 16200 + + WSLL = 16201 + + WSLLI = 16202 + + WSUB = 16203 + + WSUBA = 16204 + + WSUBAU = 16205 + + WSUBU = 16206 + + WZIP16P = 16207 + + WZIP8P = 16208 + + XNOR = 16209 + + XOR = 16210 + + XORI = 16211 + + XPERM4 = 16212 + + XPERM8 = 16213 + + ZEXT_H_RV32 = 16214 + + ZEXT_H_RV64 = 16215 + + ZIP16HP = 16216 + + ZIP16P = 16217 + + ZIP8HP = 16218 + + ZIP8P = 16219 + + ZIP_RV32 = 16220 + + INSTRUCTION_LIST_END = 16221 + +class REG(enum.Enum): + NoRegister = 0 + + FCSR = 1 + + FFLAGS = 2 + + FRM = 3 + + SF_VCIX_STATE = 4 + + SSP = 5 + + VL = 6 + + VLENB = 7 + + VTYPE = 8 + + VXRM = 9 + + VXSAT = 10 + + DUMMY_REG_PAIR_WITH_X0 = 11 + + T0 = 12 + + T1 = 13 + + T2 = 14 + + T3 = 15 + + T4 = 16 + + T5 = 17 + + T6 = 18 + + T7 = 19 + + T8 = 20 + + T9 = 21 + + T10 = 22 + + T11 = 23 + + T12 = 24 + + T13 = 25 + + T14 = 26 + + T15 = 27 + + V0 = 28 + + V1 = 29 + + V2 = 30 + + V3 = 31 + + V4 = 32 + + V5 = 33 + + V6 = 34 + + V7 = 35 + + V8 = 36 + + V9 = 37 + + V10 = 38 + + V11 = 39 + + V12 = 40 + + V13 = 41 + + V14 = 42 + + V15 = 43 + + V16 = 44 + + V17 = 45 + + V18 = 46 + + V19 = 47 + + V20 = 48 + + V21 = 49 + + V22 = 50 + + V23 = 51 + + V24 = 52 + + V25 = 53 + + V26 = 54 + + V27 = 55 + + V28 = 56 + + V29 = 57 + + V30 = 58 + + V31 = 59 + + X0 = 60 + + X1 = 61 + + X2 = 62 + + X3 = 63 + + X4 = 64 + + X5 = 65 + + X6 = 66 + + X7 = 67 + + X8 = 68 + + X9 = 69 + + X10 = 70 + + X11 = 71 + + X12 = 72 + + X13 = 73 + + X14 = 74 + + X15 = 75 + + X16 = 76 + + X17 = 77 + + X18 = 78 + + X19 = 79 + + X20 = 80 + + X21 = 81 + + X22 = 82 + + X23 = 83 + + X24 = 84 + + X25 = 85 + + X26 = 86 + + X27 = 87 + + X28 = 88 + + X29 = 89 + + X30 = 90 + + X31 = 91 + + F0_D = 92 + + F1_D = 93 + + F2_D = 94 + + F3_D = 95 + + F4_D = 96 + + F5_D = 97 + + F6_D = 98 + + F7_D = 99 + + F8_D = 100 + + F9_D = 101 + + F10_D = 102 + + F11_D = 103 + + F12_D = 104 + + F13_D = 105 + + F14_D = 106 + + F15_D = 107 + + F16_D = 108 + + F17_D = 109 + + F18_D = 110 + + F19_D = 111 + + F20_D = 112 + + F21_D = 113 + + F22_D = 114 + + F23_D = 115 + + F24_D = 116 + + F25_D = 117 + + F26_D = 118 + + F27_D = 119 + + F28_D = 120 + + F29_D = 121 + + F30_D = 122 + + F31_D = 123 + + F0_F = 124 + + F1_F = 125 + + F2_F = 126 + + F3_F = 127 + + F4_F = 128 + + F5_F = 129 + + F6_F = 130 + + F7_F = 131 + + F8_F = 132 + + F9_F = 133 + + F10_F = 134 + + F11_F = 135 + + F12_F = 136 + + F13_F = 137 + + F14_F = 138 + + F15_F = 139 + + F16_F = 140 + + F17_F = 141 + + F18_F = 142 + + F19_F = 143 + + F20_F = 144 + + F21_F = 145 + + F22_F = 146 + + F23_F = 147 + + F24_F = 148 + + F25_F = 149 + + F26_F = 150 + + F27_F = 151 + + F28_F = 152 + + F29_F = 153 + + F30_F = 154 + + F31_F = 155 + + F0_H = 156 + + F1_H = 157 + + F2_H = 158 + + F3_H = 159 + + F4_H = 160 + + F5_H = 161 + + F6_H = 162 + + F7_H = 163 + + F8_H = 164 + + F9_H = 165 + + F10_H = 166 + + F11_H = 167 + + F12_H = 168 + + F13_H = 169 + + F14_H = 170 + + F15_H = 171 + + F16_H = 172 + + F17_H = 173 + + F18_H = 174 + + F19_H = 175 + + F20_H = 176 + + F21_H = 177 + + F22_H = 178 + + F23_H = 179 + + F24_H = 180 + + F25_H = 181 + + F26_H = 182 + + F27_H = 183 + + F28_H = 184 + + F29_H = 185 + + F30_H = 186 + + F31_H = 187 + + F0_Q = 188 + + F1_Q = 189 + + F2_Q = 190 + + F3_Q = 191 + + F4_Q = 192 + + F5_Q = 193 + + F6_Q = 194 + + F7_Q = 195 + + F8_Q = 196 + + F9_Q = 197 + + F10_Q = 198 + + F11_Q = 199 + + F12_Q = 200 + + F13_Q = 201 + + F14_Q = 202 + + F15_Q = 203 + + F16_Q = 204 + + F17_Q = 205 + + F18_Q = 206 + + F19_Q = 207 + + F20_Q = 208 + + F21_Q = 209 + + F22_Q = 210 + + F23_Q = 211 + + F24_Q = 212 + + F25_Q = 213 + + F26_Q = 214 + + F27_Q = 215 + + F28_Q = 216 + + F29_Q = 217 + + F30_Q = 218 + + F31_Q = 219 + + X0_H = 220 + + X1_H = 221 + + X2_H = 222 + + X3_H = 223 + + X4_H = 224 + + X5_H = 225 + + X6_H = 226 + + X7_H = 227 + + X8_H = 228 + + X9_H = 229 + + X10_H = 230 + + X11_H = 231 + + X12_H = 232 + + X13_H = 233 + + X14_H = 234 + + X15_H = 235 + + X16_H = 236 + + X17_H = 237 + + X18_H = 238 + + X19_H = 239 + + X20_H = 240 + + X21_H = 241 + + X22_H = 242 + + X23_H = 243 + + X24_H = 244 + + X25_H = 245 + + X26_H = 246 + + X27_H = 247 + + X28_H = 248 + + X29_H = 249 + + X30_H = 250 + + X31_H = 251 + + X0_Pair = 252 + + X0_W = 253 + + X1_W = 254 + + X2_W = 255 + + X3_W = 256 + + X4_W = 257 + + X5_W = 258 + + X6_W = 259 + + X7_W = 260 + + X8_W = 261 + + X9_W = 262 + + X10_W = 263 + + X11_W = 264 + + X12_W = 265 + + X13_W = 266 + + X14_W = 267 + + X15_W = 268 + + X16_W = 269 + + X17_W = 270 + + X18_W = 271 + + X19_W = 272 + + X20_W = 273 + + X21_W = 274 + + X22_W = 275 + + X23_W = 276 + + X24_W = 277 + + X25_W = 278 + + X26_W = 279 + + X27_W = 280 + + X28_W = 281 + + X29_W = 282 + + X30_W = 283 + + X31_W = 284 + + V0M2 = 285 + + V0M4 = 286 + + V0M8 = 287 + + V2M2 = 288 + + V4M2 = 289 + + V4M4 = 290 + + V6M2 = 291 + + V8M2 = 292 + + V8M4 = 293 + + V8M8 = 294 + + V10M2 = 295 + + V12M2 = 296 + + V12M4 = 297 + + V14M2 = 298 + + V16M2 = 299 + + V16M4 = 300 + + V16M8 = 301 + + V18M2 = 302 + + V20M2 = 303 + + V20M4 = 304 + + V22M2 = 305 + + V24M2 = 306 + + V24M4 = 307 + + V24M8 = 308 + + V26M2 = 309 + + V28M2 = 310 + + V28M4 = 311 + + V30M2 = 312 + + X2_X3 = 313 + + X4_X5 = 314 + + X6_X7 = 315 + + X8_X9 = 316 + + X10_X11 = 317 + + X12_X13 = 318 + + X14_X15 = 319 + + X16_X17 = 320 + + X18_X19 = 321 + + X20_X21 = 322 + + X22_X23 = 323 + + X24_X25 = 324 + + X26_X27 = 325 + + X28_X29 = 326 + + X30_X31 = 327 + + V1_V2 = 328 + + V2_V3 = 329 + + V3_V4 = 330 + + V4_V5 = 331 + + V5_V6 = 332 + + V6_V7 = 333 + + V7_V8 = 334 + + V8_V9 = 335 + + V9_V10 = 336 + + V10_V11 = 337 + + V11_V12 = 338 + + V12_V13 = 339 + + V13_V14 = 340 + + V14_V15 = 341 + + V15_V16 = 342 + + V16_V17 = 343 + + V17_V18 = 344 + + V18_V19 = 345 + + V19_V20 = 346 + + V20_V21 = 347 + + V21_V22 = 348 + + V22_V23 = 349 + + V23_V24 = 350 + + V24_V25 = 351 + + V25_V26 = 352 + + V26_V27 = 353 + + V27_V28 = 354 + + V28_V29 = 355 + + V29_V30 = 356 + + V30_V31 = 357 + + V0_V1 = 358 + + V2M2_V4M2 = 359 + + V4M2_V6M2 = 360 + + V6M2_V8M2 = 361 + + V8M2_V10M2 = 362 + + V10M2_V12M2 = 363 + + V12M2_V14M2 = 364 + + V14M2_V16M2 = 365 + + V16M2_V18M2 = 366 + + V18M2_V20M2 = 367 + + V20M2_V22M2 = 368 + + V22M2_V24M2 = 369 + + V24M2_V26M2 = 370 + + V26M2_V28M2 = 371 + + V28M2_V30M2 = 372 + + V0M2_V2M2 = 373 + + V4M4_V8M4 = 374 + + V8M4_V12M4 = 375 + + V12M4_V16M4 = 376 + + V16M4_V20M4 = 377 + + V20M4_V24M4 = 378 + + V24M4_V28M4 = 379 + + V0M4_V4M4 = 380 + + V1_V2_V3 = 381 + + V2_V3_V4 = 382 + + V3_V4_V5 = 383 + + V4_V5_V6 = 384 + + V5_V6_V7 = 385 + + V6_V7_V8 = 386 + + V7_V8_V9 = 387 + + V8_V9_V10 = 388 + + V9_V10_V11 = 389 + + V10_V11_V12 = 390 + + V11_V12_V13 = 391 + + V12_V13_V14 = 392 + + V13_V14_V15 = 393 + + V14_V15_V16 = 394 + + V15_V16_V17 = 395 + + V16_V17_V18 = 396 + + V17_V18_V19 = 397 + + V18_V19_V20 = 398 + + V19_V20_V21 = 399 + + V20_V21_V22 = 400 + + V21_V22_V23 = 401 + + V22_V23_V24 = 402 + + V23_V24_V25 = 403 + + V24_V25_V26 = 404 + + V25_V26_V27 = 405 + + V26_V27_V28 = 406 + + V27_V28_V29 = 407 + + V28_V29_V30 = 408 + + V29_V30_V31 = 409 + + V0_V1_V2 = 410 + + V2M2_V4M2_V6M2 = 411 + + V4M2_V6M2_V8M2 = 412 + + V6M2_V8M2_V10M2 = 413 + + V8M2_V10M2_V12M2 = 414 + + V10M2_V12M2_V14M2 = 415 + + V12M2_V14M2_V16M2 = 416 + + V14M2_V16M2_V18M2 = 417 + + V16M2_V18M2_V20M2 = 418 + + V18M2_V20M2_V22M2 = 419 + + V20M2_V22M2_V24M2 = 420 + + V22M2_V24M2_V26M2 = 421 + + V24M2_V26M2_V28M2 = 422 + + V26M2_V28M2_V30M2 = 423 + + V0M2_V2M2_V4M2 = 424 + + V1_V2_V3_V4 = 425 + + V2_V3_V4_V5 = 426 + + V3_V4_V5_V6 = 427 + + V4_V5_V6_V7 = 428 + + V5_V6_V7_V8 = 429 + + V6_V7_V8_V9 = 430 + + V7_V8_V9_V10 = 431 + + V8_V9_V10_V11 = 432 + + V9_V10_V11_V12 = 433 + + V10_V11_V12_V13 = 434 + + V11_V12_V13_V14 = 435 + + V12_V13_V14_V15 = 436 + + V13_V14_V15_V16 = 437 + + V14_V15_V16_V17 = 438 + + V15_V16_V17_V18 = 439 + + V16_V17_V18_V19 = 440 + + V17_V18_V19_V20 = 441 + + V18_V19_V20_V21 = 442 + + V19_V20_V21_V22 = 443 + + V20_V21_V22_V23 = 444 + + V21_V22_V23_V24 = 445 + + V22_V23_V24_V25 = 446 + + V23_V24_V25_V26 = 447 + + V24_V25_V26_V27 = 448 + + V25_V26_V27_V28 = 449 + + V26_V27_V28_V29 = 450 + + V27_V28_V29_V30 = 451 + + V28_V29_V30_V31 = 452 + + V0_V1_V2_V3 = 453 + + V2M2_V4M2_V6M2_V8M2 = 454 + + V4M2_V6M2_V8M2_V10M2 = 455 + + V6M2_V8M2_V10M2_V12M2 = 456 + + V8M2_V10M2_V12M2_V14M2 = 457 + + V10M2_V12M2_V14M2_V16M2 = 458 + + V12M2_V14M2_V16M2_V18M2 = 459 + + V14M2_V16M2_V18M2_V20M2 = 460 + + V16M2_V18M2_V20M2_V22M2 = 461 + + V18M2_V20M2_V22M2_V24M2 = 462 + + V20M2_V22M2_V24M2_V26M2 = 463 + + V22M2_V24M2_V26M2_V28M2 = 464 + + V24M2_V26M2_V28M2_V30M2 = 465 + + V0M2_V2M2_V4M2_V6M2 = 466 + + V1_V2_V3_V4_V5 = 467 + + V2_V3_V4_V5_V6 = 468 + + V3_V4_V5_V6_V7 = 469 + + V4_V5_V6_V7_V8 = 470 + + V5_V6_V7_V8_V9 = 471 + + V6_V7_V8_V9_V10 = 472 + + V7_V8_V9_V10_V11 = 473 + + V8_V9_V10_V11_V12 = 474 + + V9_V10_V11_V12_V13 = 475 + + V10_V11_V12_V13_V14 = 476 + + V11_V12_V13_V14_V15 = 477 + + V12_V13_V14_V15_V16 = 478 + + V13_V14_V15_V16_V17 = 479 + + V14_V15_V16_V17_V18 = 480 + + V15_V16_V17_V18_V19 = 481 + + V16_V17_V18_V19_V20 = 482 + + V17_V18_V19_V20_V21 = 483 + + V18_V19_V20_V21_V22 = 484 + + V19_V20_V21_V22_V23 = 485 + + V20_V21_V22_V23_V24 = 486 + + V21_V22_V23_V24_V25 = 487 + + V22_V23_V24_V25_V26 = 488 + + V23_V24_V25_V26_V27 = 489 + + V24_V25_V26_V27_V28 = 490 + + V25_V26_V27_V28_V29 = 491 + + V26_V27_V28_V29_V30 = 492 + + V27_V28_V29_V30_V31 = 493 + + V0_V1_V2_V3_V4 = 494 + + V1_V2_V3_V4_V5_V6 = 495 + + V2_V3_V4_V5_V6_V7 = 496 + + V3_V4_V5_V6_V7_V8 = 497 + + V4_V5_V6_V7_V8_V9 = 498 + + V5_V6_V7_V8_V9_V10 = 499 + + V6_V7_V8_V9_V10_V11 = 500 + + V7_V8_V9_V10_V11_V12 = 501 + + V8_V9_V10_V11_V12_V13 = 502 + + V9_V10_V11_V12_V13_V14 = 503 + + V10_V11_V12_V13_V14_V15 = 504 + + V11_V12_V13_V14_V15_V16 = 505 + + V12_V13_V14_V15_V16_V17 = 506 + + V13_V14_V15_V16_V17_V18 = 507 + + V14_V15_V16_V17_V18_V19 = 508 + + V15_V16_V17_V18_V19_V20 = 509 + + V16_V17_V18_V19_V20_V21 = 510 + + V17_V18_V19_V20_V21_V22 = 511 + + V18_V19_V20_V21_V22_V23 = 512 + + V19_V20_V21_V22_V23_V24 = 513 + + V20_V21_V22_V23_V24_V25 = 514 + + V21_V22_V23_V24_V25_V26 = 515 + + V22_V23_V24_V25_V26_V27 = 516 + + V23_V24_V25_V26_V27_V28 = 517 + + V24_V25_V26_V27_V28_V29 = 518 + + V25_V26_V27_V28_V29_V30 = 519 + + V26_V27_V28_V29_V30_V31 = 520 + + V0_V1_V2_V3_V4_V5 = 521 + + V1_V2_V3_V4_V5_V6_V7 = 522 + + V2_V3_V4_V5_V6_V7_V8 = 523 + + V3_V4_V5_V6_V7_V8_V9 = 524 + + V4_V5_V6_V7_V8_V9_V10 = 525 + + V5_V6_V7_V8_V9_V10_V11 = 526 + + V6_V7_V8_V9_V10_V11_V12 = 527 + + V7_V8_V9_V10_V11_V12_V13 = 528 + + V8_V9_V10_V11_V12_V13_V14 = 529 + + V9_V10_V11_V12_V13_V14_V15 = 530 + + V10_V11_V12_V13_V14_V15_V16 = 531 + + V11_V12_V13_V14_V15_V16_V17 = 532 + + V12_V13_V14_V15_V16_V17_V18 = 533 + + V13_V14_V15_V16_V17_V18_V19 = 534 + + V14_V15_V16_V17_V18_V19_V20 = 535 + + V15_V16_V17_V18_V19_V20_V21 = 536 + + V16_V17_V18_V19_V20_V21_V22 = 537 + + V17_V18_V19_V20_V21_V22_V23 = 538 + + V18_V19_V20_V21_V22_V23_V24 = 539 + + V19_V20_V21_V22_V23_V24_V25 = 540 + + V20_V21_V22_V23_V24_V25_V26 = 541 + + V21_V22_V23_V24_V25_V26_V27 = 542 + + V22_V23_V24_V25_V26_V27_V28 = 543 + + V23_V24_V25_V26_V27_V28_V29 = 544 + + V24_V25_V26_V27_V28_V29_V30 = 545 + + V25_V26_V27_V28_V29_V30_V31 = 546 + + V0_V1_V2_V3_V4_V5_V6 = 547 + + V1_V2_V3_V4_V5_V6_V7_V8 = 548 + + V2_V3_V4_V5_V6_V7_V8_V9 = 549 + + V3_V4_V5_V6_V7_V8_V9_V10 = 550 + + V4_V5_V6_V7_V8_V9_V10_V11 = 551 + + V5_V6_V7_V8_V9_V10_V11_V12 = 552 + + V6_V7_V8_V9_V10_V11_V12_V13 = 553 + + V7_V8_V9_V10_V11_V12_V13_V14 = 554 + + V8_V9_V10_V11_V12_V13_V14_V15 = 555 + + V9_V10_V11_V12_V13_V14_V15_V16 = 556 + + V10_V11_V12_V13_V14_V15_V16_V17 = 557 + + V11_V12_V13_V14_V15_V16_V17_V18 = 558 + + V12_V13_V14_V15_V16_V17_V18_V19 = 559 + + V13_V14_V15_V16_V17_V18_V19_V20 = 560 + + V14_V15_V16_V17_V18_V19_V20_V21 = 561 + + V15_V16_V17_V18_V19_V20_V21_V22 = 562 + + V16_V17_V18_V19_V20_V21_V22_V23 = 563 + + V17_V18_V19_V20_V21_V22_V23_V24 = 564 + + V18_V19_V20_V21_V22_V23_V24_V25 = 565 + + V19_V20_V21_V22_V23_V24_V25_V26 = 566 + + V20_V21_V22_V23_V24_V25_V26_V27 = 567 + + V21_V22_V23_V24_V25_V26_V27_V28 = 568 + + V22_V23_V24_V25_V26_V27_V28_V29 = 569 + + V23_V24_V25_V26_V27_V28_V29_V30 = 570 + + V24_V25_V26_V27_V28_V29_V30_V31 = 571 + + V0_V1_V2_V3_V4_V5_V6_V7 = 572 + + NUM_TARGET_REGS = 573 + +class SYSREG(enum.Enum): + fflags = 1 + + frm = 2 + + fcsr = 3 + + vstart = 8 + + vxsat = 9 + + vxrm = 10 + + vcsr = 15 + + ssp = 17 + + seed = 21 + + jvt = 23 + + sstatus = 256 + + sie = 260 + + stvec = 261 + + scounteren = 262 + + sf_stvt = 263 + + senvcfg = 266 + + sstateen0 = 268 + + sstateen1 = 269 + + sstateen2 = 270 + + sstateen3 = 271 + + sieh = 276 + + scountinhibit = 288 + + sscratch = 320 + + sepc = 321 + + scause = 322 + + sbadaddr = 323 + + sip = 324 + + sf_snxti = 325 + + sf_sintstatus = 326 + + sf_sscratchcsw = 328 + + sf_sscratchcswl = 329 + + stimecmp = 333 + + sctrctl = 334 + + sctrstatus = 335 + + siselect = 336 + + sireg = 337 + + sireg2 = 338 + + sireg3 = 339 + + siph = 340 + + sireg4 = 341 + + sireg5 = 342 + + sireg6 = 343 + + stopei = 348 + + stimecmph = 349 + + sctrdepth = 351 + + satp = 384 + + srmcfg = 385 + + vsstatus = 512 + + vsie = 516 + + vstvec = 517 + + vsieh = 532 + + vsscratch = 576 + + vsepc = 577 + + vscause = 578 + + vstval = 579 + + vsip = 580 + + vstimecmp = 589 + + vsctrctl = 590 + + vsiselect = 592 + + vsireg = 593 + + vsireg2 = 594 + + vsireg3 = 595 + + vsiph = 596 + + vsireg4 = 597 + + vsireg5 = 598 + + vsireg6 = 599 + + vstopei = 604 + + vstimecmph = 605 + + vsatp = 640 + + mstatus = 768 + + misa = 769 + + medeleg = 770 + + mideleg = 771 + + mie = 772 + + mtvec = 773 + + mcounteren = 774 + + sf_mtvt = 775 + + mvien = 776 + + mvip = 777 + + menvcfg = 778 + + mstateen0 = 780 + + mstateen1 = 781 + + mstateen2 = 782 + + mstateen3 = 783 + + mstatush = 784 + + medelegh = 786 + + midelegh = 787 + + mieh = 788 + + mvienh = 792 + + mviph = 793 + + menvcfgh = 794 + + mstateen0h = 796 + + mstateen1h = 797 + + mstateen2h = 798 + + mstateen3h = 799 + + mcountinhibit = 800 + + mcyclecfg = 801 + + minstretcfg = 802 + + mhpmevent3 = 803 + + mhpmevent4 = 804 + + mhpmevent5 = 805 + + mhpmevent6 = 806 + + mhpmevent7 = 807 + + mhpmevent8 = 808 + + mhpmevent9 = 809 + + mhpmevent10 = 810 + + mhpmevent11 = 811 + + mhpmevent12 = 812 + + mhpmevent13 = 813 + + mhpmevent14 = 814 + + mhpmevent15 = 815 + + mhpmevent16 = 816 + + mhpmevent17 = 817 + + mhpmevent18 = 818 + + mhpmevent19 = 819 + + mhpmevent20 = 820 + + mhpmevent21 = 821 + + mhpmevent22 = 822 + + mhpmevent23 = 823 + + mhpmevent24 = 824 + + mhpmevent25 = 825 + + mhpmevent26 = 826 + + mhpmevent27 = 827 + + mhpmevent28 = 828 + + mhpmevent29 = 829 + + mhpmevent30 = 830 + + mhpmevent31 = 831 + + mscratch = 832 + + mepc = 833 + + mcause = 834 + + mbadaddr = 835 + + mip = 836 + + sf_mnxti = 837 + + sf_mintstatus = 838 + + sf_mscratchcsw = 840 + + sf_mscratchcswl = 841 + + mtinst = 842 + + mtval2 = 843 + + mctrctl = 846 + + miselect = 848 + + mireg = 849 + + mireg2 = 850 + + mireg3 = 851 + + miph = 852 + + mireg4 = 853 + + mireg5 = 854 + + mireg6 = 855 + + mtopei = 860 + + pmpcfg0 = 928 + + pmpcfg1 = 929 + + pmpcfg2 = 930 + + pmpcfg3 = 931 + + pmpcfg4 = 932 + + pmpcfg5 = 933 + + pmpcfg6 = 934 + + pmpcfg7 = 935 + + pmpcfg8 = 936 + + pmpcfg9 = 937 + + pmpcfg10 = 938 + + pmpcfg11 = 939 + + pmpcfg12 = 940 + + pmpcfg13 = 941 + + pmpcfg14 = 942 + + pmpcfg15 = 943 + + pmpaddr0 = 944 + + pmpaddr1 = 945 + + pmpaddr2 = 946 + + pmpaddr3 = 947 + + pmpaddr4 = 948 + + pmpaddr5 = 949 + + pmpaddr6 = 950 + + pmpaddr7 = 951 + + pmpaddr8 = 952 + + pmpaddr9 = 953 + + pmpaddr10 = 954 + + pmpaddr11 = 955 + + pmpaddr12 = 956 + + pmpaddr13 = 957 + + pmpaddr14 = 958 + + pmpaddr15 = 959 + + pmpaddr16 = 960 + + pmpaddr17 = 961 + + pmpaddr18 = 962 + + pmpaddr19 = 963 + + pmpaddr20 = 964 + + pmpaddr21 = 965 + + pmpaddr22 = 966 + + pmpaddr23 = 967 + + pmpaddr24 = 968 + + pmpaddr25 = 969 + + pmpaddr26 = 970 + + pmpaddr27 = 971 + + pmpaddr28 = 972 + + pmpaddr29 = 973 + + pmpaddr30 = 974 + + pmpaddr31 = 975 + + pmpaddr32 = 976 + + pmpaddr33 = 977 + + pmpaddr34 = 978 + + pmpaddr35 = 979 + + pmpaddr36 = 980 + + pmpaddr37 = 981 + + pmpaddr38 = 982 + + pmpaddr39 = 983 + + pmpaddr40 = 984 + + pmpaddr41 = 985 + + pmpaddr42 = 986 + + pmpaddr43 = 987 + + pmpaddr44 = 988 + + pmpaddr45 = 989 + + pmpaddr46 = 990 + + pmpaddr47 = 991 + + pmpaddr48 = 992 + + pmpaddr49 = 993 + + pmpaddr50 = 994 + + pmpaddr51 = 995 + + pmpaddr52 = 996 + + pmpaddr53 = 997 + + pmpaddr54 = 998 + + pmpaddr55 = 999 + + pmpaddr56 = 1000 + + pmpaddr57 = 1001 + + pmpaddr58 = 1002 + + pmpaddr59 = 1003 + + pmpaddr60 = 1004 + + pmpaddr61 = 1005 + + pmpaddr62 = 1006 + + pmpaddr63 = 1007 + + scontext = 1448 + + hstatus = 1536 + + hedeleg = 1538 + + hideleg = 1539 + + hie = 1540 + + htimedelta = 1541 + + hcounteren = 1542 + + hgeie = 1543 + + hvien = 1544 + + hvictl = 1545 + + henvcfg = 1546 + + hstateen0 = 1548 + + hstateen1 = 1549 + + hstateen2 = 1550 + + hstateen3 = 1551 + + hedelegh = 1554 + + hidelegh = 1555 + + htimedeltah = 1557 + + hvienh = 1560 + + henvcfgh = 1562 + + hstateen0h = 1564 + + hstateen1h = 1565 + + hstateen2h = 1566 + + hstateen3h = 1567 + + htval = 1603 + + hip = 1604 + + hvip = 1605 + + hviprio1 = 1606 + + hviprio2 = 1607 + + htinst = 1610 + + hviph = 1621 + + hviprio1h = 1622 + + hviprio2h = 1623 + + hgatp = 1664 + + hcontext = 1704 + + mcyclecfgh = 1825 + + minstretcfgh = 1826 + + mhpmevent3h = 1827 + + mhpmevent4h = 1828 + + mhpmevent5h = 1829 + + mhpmevent6h = 1830 + + mhpmevent7h = 1831 + + mhpmevent8h = 1832 + + mhpmevent9h = 1833 + + mhpmevent10h = 1834 + + mhpmevent11h = 1835 + + mhpmevent12h = 1836 + + mhpmevent13h = 1837 + + mhpmevent14h = 1838 + + mhpmevent15h = 1839 + + mhpmevent16h = 1840 + + mhpmevent17h = 1841 + + mhpmevent18h = 1842 + + mhpmevent19h = 1843 + + mhpmevent20h = 1844 + + mhpmevent21h = 1845 + + mhpmevent22h = 1846 + + mhpmevent23h = 1847 + + mhpmevent24h = 1848 + + mhpmevent25h = 1849 + + mhpmevent26h = 1850 + + mhpmevent27h = 1851 + + mhpmevent28h = 1852 + + mhpmevent29h = 1853 + + mhpmevent30h = 1854 + + mhpmevent31h = 1855 + + mnscratch = 1856 + + mnepc = 1857 + + mncause = 1858 + + mnstatus = 1860 + + mseccfg = 1863 + + mseccfgh = 1879 + + tselect = 1952 + + etrigger = 1953 + + tdata2 = 1954 + + tdata3 = 1955 + + tinfo = 1956 + + tcontrol = 1957 + + mcontext = 1960 + + mscontext = 1962 + + dcsr = 1968 + + dpc = 1969 + + dscratch = 1970 + + dscratch1 = 1971 + + qc_mmcr = 1984 + + qc_mntvec = 1987 + + qc_mstktopaddr = 1988 + + qc_mstkbottomaddr = 1989 + + qc_mthreadptr = 1992 + + qc_mcause = 1993 + + qc_mwpstartaddr0 = 2000 + + qc_mwpstartaddr1 = 2001 + + qc_mwpstartaddr2 = 2002 + + qc_mwpstartaddr3 = 2003 + + qc_mwpendaddr0 = 2004 + + qc_mwpendaddr1 = 2005 + + qc_mwpendaddr2 = 2006 + + qc_mwpendaddr3 = 2007 + + qc_mclicip0 = 2032 + + qc_mclicip1 = 2033 + + qc_mclicip2 = 2034 + + qc_mclicip3 = 2035 + + qc_mclicip4 = 2036 + + qc_mclicip5 = 2037 + + qc_mclicip6 = 2038 + + qc_mclicip7 = 2039 + + qc_mclicie0 = 2040 + + qc_mclicie1 = 2041 + + qc_mclicie2 = 2042 + + qc_mclicie3 = 2043 + + qc_mclicie4 = 2044 + + qc_mclicie5 = 2045 + + qc_mclicie6 = 2046 + + qc_mclicie7 = 2047 + + mcycle = 2816 + + minstret = 2818 + + mhpmcounter3 = 2819 + + mhpmcounter4 = 2820 + + mhpmcounter5 = 2821 + + mhpmcounter6 = 2822 + + mhpmcounter7 = 2823 + + mhpmcounter8 = 2824 + + mhpmcounter9 = 2825 + + mhpmcounter10 = 2826 + + mhpmcounter11 = 2827 + + mhpmcounter12 = 2828 + + mhpmcounter13 = 2829 + + mhpmcounter14 = 2830 + + mhpmcounter15 = 2831 + + mhpmcounter16 = 2832 + + mhpmcounter17 = 2833 + + mhpmcounter18 = 2834 + + mhpmcounter19 = 2835 + + mhpmcounter20 = 2836 + + mhpmcounter21 = 2837 + + mhpmcounter22 = 2838 + + mhpmcounter23 = 2839 + + mhpmcounter24 = 2840 + + mhpmcounter25 = 2841 + + mhpmcounter26 = 2842 + + mhpmcounter27 = 2843 + + mhpmcounter28 = 2844 + + mhpmcounter29 = 2845 + + mhpmcounter30 = 2846 + + mhpmcounter31 = 2847 + + mcycleh = 2944 + + minstreth = 2946 + + mhpmcounter3h = 2947 + + mhpmcounter4h = 2948 + + mhpmcounter5h = 2949 + + mhpmcounter6h = 2950 + + mhpmcounter7h = 2951 + + mhpmcounter8h = 2952 + + mhpmcounter9h = 2953 + + mhpmcounter10h = 2954 + + mhpmcounter11h = 2955 + + mhpmcounter12h = 2956 + + mhpmcounter13h = 2957 + + mhpmcounter14h = 2958 + + mhpmcounter15h = 2959 + + mhpmcounter16h = 2960 + + mhpmcounter17h = 2961 + + mhpmcounter18h = 2962 + + mhpmcounter19h = 2963 + + mhpmcounter20h = 2964 + + mhpmcounter21h = 2965 + + mhpmcounter22h = 2966 + + mhpmcounter23h = 2967 + + mhpmcounter24h = 2968 + + mhpmcounter25h = 2969 + + mhpmcounter26h = 2970 + + mhpmcounter27h = 2971 + + mhpmcounter28h = 2972 + + mhpmcounter29h = 2973 + + mhpmcounter30h = 2974 + + mhpmcounter31h = 2975 + + qc_mclicilvl00 = 3008 + + qc_mclicilvl01 = 3009 + + qc_mclicilvl02 = 3010 + + qc_mclicilvl03 = 3011 + + qc_mclicilvl04 = 3012 + + qc_mclicilvl05 = 3013 + + qc_mclicilvl06 = 3014 + + qc_mclicilvl07 = 3015 + + qc_mclicilvl08 = 3016 + + qc_mclicilvl09 = 3017 + + qc_mclicilvl10 = 3018 + + qc_mclicilvl11 = 3019 + + qc_mclicilvl12 = 3020 + + qc_mclicilvl13 = 3021 + + qc_mclicilvl14 = 3022 + + qc_mclicilvl15 = 3023 + + qc_mclicilvl16 = 3024 + + qc_mclicilvl17 = 3025 + + qc_mclicilvl18 = 3026 + + qc_mclicilvl19 = 3027 + + qc_mclicilvl20 = 3028 + + qc_mclicilvl21 = 3029 + + qc_mclicilvl22 = 3030 + + qc_mclicilvl23 = 3031 + + qc_mclicilvl24 = 3032 + + qc_mclicilvl25 = 3033 + + qc_mclicilvl26 = 3034 + + qc_mclicilvl27 = 3035 + + qc_mclicilvl28 = 3036 + + qc_mclicilvl29 = 3037 + + qc_mclicilvl30 = 3038 + + qc_mclicilvl31 = 3039 + + cycle = 3072 + + time = 3073 + + instret = 3074 + + hpmcounter3 = 3075 + + hpmcounter4 = 3076 + + hpmcounter5 = 3077 + + hpmcounter6 = 3078 + + hpmcounter7 = 3079 + + hpmcounter8 = 3080 + + hpmcounter9 = 3081 + + hpmcounter10 = 3082 + + hpmcounter11 = 3083 + + hpmcounter12 = 3084 + + hpmcounter13 = 3085 + + hpmcounter14 = 3086 + + hpmcounter15 = 3087 + + hpmcounter16 = 3088 + + hpmcounter17 = 3089 + + hpmcounter18 = 3090 + + hpmcounter19 = 3091 + + hpmcounter20 = 3092 + + hpmcounter21 = 3093 + + hpmcounter22 = 3094 + + hpmcounter23 = 3095 + + hpmcounter24 = 3096 + + hpmcounter25 = 3097 + + hpmcounter26 = 3098 + + hpmcounter27 = 3099 + + hpmcounter28 = 3100 + + hpmcounter29 = 3101 + + hpmcounter30 = 3102 + + hpmcounter31 = 3103 + + vl = 3104 + + vtype = 3105 + + vlenb = 3106 + + cycleh = 3200 + + timeh = 3201 + + instreth = 3202 + + hpmcounter3h = 3203 + + hpmcounter4h = 3204 + + hpmcounter5h = 3205 + + hpmcounter6h = 3206 + + hpmcounter7h = 3207 + + hpmcounter8h = 3208 + + hpmcounter9h = 3209 + + hpmcounter10h = 3210 + + hpmcounter11h = 3211 + + hpmcounter12h = 3212 + + hpmcounter13h = 3213 + + hpmcounter14h = 3214 + + hpmcounter15h = 3215 + + hpmcounter16h = 3216 + + hpmcounter17h = 3217 + + hpmcounter18h = 3218 + + hpmcounter19h = 3219 + + hpmcounter20h = 3220 + + hpmcounter21h = 3221 + + hpmcounter22h = 3222 + + hpmcounter23h = 3223 + + hpmcounter24h = 3224 + + hpmcounter25h = 3225 + + hpmcounter26h = 3226 + + hpmcounter27h = 3227 + + hpmcounter28h = 3228 + + hpmcounter29h = 3229 + + hpmcounter30h = 3230 + + hpmcounter31h = 3231 + + scountovf = 3488 + + stopi = 3504 + + hgeip = 3602 + + vstopi = 3760 + + mvendorid = 3857 + + marchid = 3858 + + mimpid = 3859 + + mhartid = 3860 + + mconfigptr = 3861 + + mtopi = 4016 + + NUM_TARGET_SYSREGS = 513 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/riscv/operands.pyi b/vendor/lief/api/python/lief/assembly/riscv/operands.pyi new file mode 100644 index 0000000..8803172 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/riscv/operands.pyi @@ -0,0 +1,33 @@ +from typing import Optional, Union + +import lief.assembly.riscv + +import lief.assembly.riscv + + +class Immediate(lief.assembly.riscv.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.riscv.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> Optional[Union[lief.assembly.riscv.REG, lief.assembly.riscv.SYSREG]]: ... + +class Memory(lief.assembly.riscv.Operand): + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.riscv.REG: ... + + @property + def displacement(self) -> int: ... + +class PCRelative(lief.assembly.riscv.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/assembly/x86/__init__.pyi b/vendor/lief/api/python/lief/assembly/x86/__init__.pyi new file mode 100644 index 0000000..870c704 --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/x86/__init__.pyi @@ -0,0 +1,45407 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.assembly +from lief.assembly.x86 import operands as operands + + +class OPCODE(enum.Enum): + PHI = 0 + + INLINEASM = 1 + + INLINEASM_BR = 2 + + CFI_INSTRUCTION = 3 + + EH_LABEL = 4 + + GC_LABEL = 5 + + ANNOTATION_LABEL = 6 + + KILL = 7 + + EXTRACT_SUBREG = 8 + + INSERT_SUBREG = 9 + + IMPLICIT_DEF = 10 + + INIT_UNDEF = 11 + + SUBREG_TO_REG = 12 + + COPY_TO_REGCLASS = 13 + + DBG_VALUE = 14 + + DBG_VALUE_LIST = 15 + + DBG_INSTR_REF = 16 + + DBG_PHI = 17 + + DBG_LABEL = 18 + + REG_SEQUENCE = 19 + + COPY = 20 + + COPY_LANEMASK = 21 + + BUNDLE = 22 + + LIFETIME_START = 23 + + LIFETIME_END = 24 + + PSEUDO_PROBE = 25 + + ARITH_FENCE = 26 + + STACKMAP = 27 + + FENTRY_CALL = 28 + + PATCHPOINT = 29 + + LOAD_STACK_GUARD = 30 + + PREALLOCATED_SETUP = 31 + + PREALLOCATED_ARG = 32 + + STATEPOINT = 33 + + LOCAL_ESCAPE = 34 + + FAULTING_OP = 35 + + PATCHABLE_OP = 36 + + PATCHABLE_FUNCTION_ENTER = 37 + + PATCHABLE_RET = 38 + + PATCHABLE_FUNCTION_EXIT = 39 + + PATCHABLE_TAIL_CALL = 40 + + PATCHABLE_EVENT_CALL = 41 + + PATCHABLE_TYPED_EVENT_CALL = 42 + + ICALL_BRANCH_FUNNEL = 43 + + FAKE_USE = 44 + + MEMBARRIER = 45 + + JUMP_TABLE_DEBUG_INFO = 46 + + RELOC_NONE = 47 + + CONVERGENCECTRL_ENTRY = 48 + + CONVERGENCECTRL_ANCHOR = 49 + + CONVERGENCECTRL_LOOP = 50 + + CONVERGENCECTRL_GLUE = 51 + + G_ASSERT_SEXT = 52 + + G_ASSERT_ZEXT = 53 + + G_ASSERT_ALIGN = 54 + + G_ADD = 55 + + G_SUB = 56 + + G_MUL = 57 + + G_SDIV = 58 + + G_UDIV = 59 + + G_SREM = 60 + + G_UREM = 61 + + G_SDIVREM = 62 + + G_UDIVREM = 63 + + G_AND = 64 + + G_OR = 65 + + G_XOR = 66 + + G_ABDS = 67 + + G_ABDU = 68 + + G_UAVGFLOOR = 69 + + G_UAVGCEIL = 70 + + G_SAVGFLOOR = 71 + + G_SAVGCEIL = 72 + + G_IMPLICIT_DEF = 73 + + G_PHI = 74 + + G_FRAME_INDEX = 75 + + G_GLOBAL_VALUE = 76 + + G_PTRAUTH_GLOBAL_VALUE = 77 + + G_CONSTANT_POOL = 78 + + G_EXTRACT = 79 + + G_UNMERGE_VALUES = 80 + + G_INSERT = 81 + + G_MERGE_VALUES = 82 + + G_BUILD_VECTOR = 83 + + G_BUILD_VECTOR_TRUNC = 84 + + G_CONCAT_VECTORS = 85 + + G_PTRTOINT = 86 + + G_INTTOPTR = 87 + + G_BITCAST = 88 + + G_FREEZE = 89 + + G_CONSTANT_FOLD_BARRIER = 90 + + G_INTRINSIC_FPTRUNC_ROUND = 91 + + G_INTRINSIC_TRUNC = 92 + + G_INTRINSIC_ROUND = 93 + + G_INTRINSIC_LRINT = 94 + + G_INTRINSIC_LLRINT = 95 + + G_INTRINSIC_ROUNDEVEN = 96 + + G_READCYCLECOUNTER = 97 + + G_READSTEADYCOUNTER = 98 + + G_LOAD = 99 + + G_SEXTLOAD = 100 + + G_ZEXTLOAD = 101 + + G_INDEXED_LOAD = 102 + + G_INDEXED_SEXTLOAD = 103 + + G_INDEXED_ZEXTLOAD = 104 + + G_STORE = 105 + + G_INDEXED_STORE = 106 + + G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107 + + G_ATOMIC_CMPXCHG = 108 + + G_ATOMICRMW_XCHG = 109 + + G_ATOMICRMW_ADD = 110 + + G_ATOMICRMW_SUB = 111 + + G_ATOMICRMW_AND = 112 + + G_ATOMICRMW_NAND = 113 + + G_ATOMICRMW_OR = 114 + + G_ATOMICRMW_XOR = 115 + + G_ATOMICRMW_MAX = 116 + + G_ATOMICRMW_MIN = 117 + + G_ATOMICRMW_UMAX = 118 + + G_ATOMICRMW_UMIN = 119 + + G_ATOMICRMW_FADD = 120 + + G_ATOMICRMW_FSUB = 121 + + G_ATOMICRMW_FMAX = 122 + + G_ATOMICRMW_FMIN = 123 + + G_ATOMICRMW_FMAXIMUM = 124 + + G_ATOMICRMW_FMINIMUM = 125 + + G_ATOMICRMW_UINC_WRAP = 126 + + G_ATOMICRMW_UDEC_WRAP = 127 + + G_ATOMICRMW_USUB_COND = 128 + + G_ATOMICRMW_USUB_SAT = 129 + + G_FENCE = 130 + + G_PREFETCH = 131 + + G_BRCOND = 132 + + G_BRINDIRECT = 133 + + G_INVOKE_REGION_START = 134 + + G_INTRINSIC = 135 + + G_INTRINSIC_W_SIDE_EFFECTS = 136 + + G_INTRINSIC_CONVERGENT = 137 + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138 + + G_ANYEXT = 139 + + G_TRUNC = 140 + + G_TRUNC_SSAT_S = 141 + + G_TRUNC_SSAT_U = 142 + + G_TRUNC_USAT_U = 143 + + G_CONSTANT = 144 + + G_FCONSTANT = 145 + + G_VASTART = 146 + + G_VAARG = 147 + + G_SEXT = 148 + + G_SEXT_INREG = 149 + + G_ZEXT = 150 + + G_SHL = 151 + + G_LSHR = 152 + + G_ASHR = 153 + + G_FSHL = 154 + + G_FSHR = 155 + + G_ROTR = 156 + + G_ROTL = 157 + + G_ICMP = 158 + + G_FCMP = 159 + + G_SCMP = 160 + + G_UCMP = 161 + + G_SELECT = 162 + + G_UADDO = 163 + + G_UADDE = 164 + + G_USUBO = 165 + + G_USUBE = 166 + + G_SADDO = 167 + + G_SADDE = 168 + + G_SSUBO = 169 + + G_SSUBE = 170 + + G_UMULO = 171 + + G_SMULO = 172 + + G_UMULH = 173 + + G_SMULH = 174 + + G_UADDSAT = 175 + + G_SADDSAT = 176 + + G_USUBSAT = 177 + + G_SSUBSAT = 178 + + G_USHLSAT = 179 + + G_SSHLSAT = 180 + + G_SMULFIX = 181 + + G_UMULFIX = 182 + + G_SMULFIXSAT = 183 + + G_UMULFIXSAT = 184 + + G_SDIVFIX = 185 + + G_UDIVFIX = 186 + + G_SDIVFIXSAT = 187 + + G_UDIVFIXSAT = 188 + + G_FADD = 189 + + G_FSUB = 190 + + G_FMUL = 191 + + G_FMA = 192 + + G_FMAD = 193 + + G_FDIV = 194 + + G_FREM = 195 + + G_FMODF = 196 + + G_FPOW = 197 + + G_FPOWI = 198 + + G_FEXP = 199 + + G_FEXP2 = 200 + + G_FEXP10 = 201 + + G_FLOG = 202 + + G_FLOG2 = 203 + + G_FLOG10 = 204 + + G_FLDEXP = 205 + + G_FFREXP = 206 + + G_FNEG = 207 + + G_FPEXT = 208 + + G_FPTRUNC = 209 + + G_FPTOSI = 210 + + G_FPTOUI = 211 + + G_SITOFP = 212 + + G_UITOFP = 213 + + G_FPTOSI_SAT = 214 + + G_FPTOUI_SAT = 215 + + G_FABS = 216 + + G_FCOPYSIGN = 217 + + G_IS_FPCLASS = 218 + + G_FCANONICALIZE = 219 + + G_FMINNUM = 220 + + G_FMAXNUM = 221 + + G_FMINNUM_IEEE = 222 + + G_FMAXNUM_IEEE = 223 + + G_FMINIMUM = 224 + + G_FMAXIMUM = 225 + + G_FMINIMUMNUM = 226 + + G_FMAXIMUMNUM = 227 + + G_GET_FPENV = 228 + + G_SET_FPENV = 229 + + G_RESET_FPENV = 230 + + G_GET_FPMODE = 231 + + G_SET_FPMODE = 232 + + G_RESET_FPMODE = 233 + + G_GET_ROUNDING = 234 + + G_SET_ROUNDING = 235 + + G_PTR_ADD = 236 + + G_PTRMASK = 237 + + G_SMIN = 238 + + G_SMAX = 239 + + G_UMIN = 240 + + G_UMAX = 241 + + G_ABS = 242 + + G_LROUND = 243 + + G_LLROUND = 244 + + G_BR = 245 + + G_BRJT = 246 + + G_VSCALE = 247 + + G_INSERT_SUBVECTOR = 248 + + G_EXTRACT_SUBVECTOR = 249 + + G_INSERT_VECTOR_ELT = 250 + + G_EXTRACT_VECTOR_ELT = 251 + + G_SHUFFLE_VECTOR = 252 + + G_SPLAT_VECTOR = 253 + + G_STEP_VECTOR = 254 + + G_VECTOR_COMPRESS = 255 + + G_CTTZ = 256 + + G_CTTZ_ZERO_UNDEF = 257 + + G_CTLZ = 258 + + G_CTLZ_ZERO_UNDEF = 259 + + G_CTPOP = 260 + + G_BSWAP = 261 + + G_BITREVERSE = 262 + + G_FCEIL = 263 + + G_FCOS = 264 + + G_FSIN = 265 + + G_FSINCOS = 266 + + G_FTAN = 267 + + G_FACOS = 268 + + G_FASIN = 269 + + G_FATAN = 270 + + G_FATAN2 = 271 + + G_FCOSH = 272 + + G_FSINH = 273 + + G_FTANH = 274 + + G_FSQRT = 275 + + G_FFLOOR = 276 + + G_FRINT = 277 + + G_FNEARBYINT = 278 + + G_ADDRSPACE_CAST = 279 + + G_BLOCK_ADDR = 280 + + G_JUMP_TABLE = 281 + + G_DYN_STACKALLOC = 282 + + G_STACKSAVE = 283 + + G_STACKRESTORE = 284 + + G_STRICT_FADD = 285 + + G_STRICT_FSUB = 286 + + G_STRICT_FMUL = 287 + + G_STRICT_FDIV = 288 + + G_STRICT_FREM = 289 + + G_STRICT_FMA = 290 + + G_STRICT_FSQRT = 291 + + G_STRICT_FLDEXP = 292 + + G_READ_REGISTER = 293 + + G_WRITE_REGISTER = 294 + + G_MEMCPY = 295 + + G_MEMCPY_INLINE = 296 + + G_MEMMOVE = 297 + + G_MEMSET = 298 + + G_BZERO = 299 + + G_TRAP = 300 + + G_DEBUGTRAP = 301 + + G_UBSANTRAP = 302 + + G_VECREDUCE_SEQ_FADD = 303 + + G_VECREDUCE_SEQ_FMUL = 304 + + G_VECREDUCE_FADD = 305 + + G_VECREDUCE_FMUL = 306 + + G_VECREDUCE_FMAX = 307 + + G_VECREDUCE_FMIN = 308 + + G_VECREDUCE_FMAXIMUM = 309 + + G_VECREDUCE_FMINIMUM = 310 + + G_VECREDUCE_ADD = 311 + + G_VECREDUCE_MUL = 312 + + G_VECREDUCE_AND = 313 + + G_VECREDUCE_OR = 314 + + G_VECREDUCE_XOR = 315 + + G_VECREDUCE_SMAX = 316 + + G_VECREDUCE_SMIN = 317 + + G_VECREDUCE_UMAX = 318 + + G_VECREDUCE_UMIN = 319 + + G_SBFX = 320 + + G_UBFX = 321 + + ADD16ri_DB = 322 + + ADD16rr_DB = 323 + + ADD32ri_DB = 324 + + ADD32rr_DB = 325 + + ADD64ri32_DB = 326 + + ADD64rr_DB = 327 + + ADD8ri_DB = 328 + + ADD8rr_DB = 329 + + AVX1_SETALLONES = 330 + + AVX2_SETALLONES = 331 + + AVX512_128_SET0 = 332 + + AVX512_128_SETALLONES = 333 + + AVX512_256_SET0 = 334 + + AVX512_256_SETALLONES = 335 + + AVX512_512_SET0 = 336 + + AVX512_512_SETALLONES = 337 + + AVX512_512_SEXT_MASK_32 = 338 + + AVX512_512_SEXT_MASK_64 = 339 + + AVX512_FsFLD0F128 = 340 + + AVX512_FsFLD0SD = 341 + + AVX512_FsFLD0SH = 342 + + AVX512_FsFLD0SS = 343 + + AVX_SET0 = 344 + + CALL64m_RVMARKER = 345 + + CALL64pcrel32_RVMARKER = 346 + + CALL64r_ImpCall = 347 + + CALL64r_RVMARKER = 348 + + FsFLD0F128 = 349 + + FsFLD0SD = 350 + + FsFLD0SH = 351 + + FsFLD0SS = 352 + + G_FILD = 353 + + G_FIST = 354 + + G_FLDCW16 = 355 + + G_FNSTCW16 = 356 + + INDIRECT_THUNK_CALL32 = 357 + + INDIRECT_THUNK_CALL64 = 358 + + INDIRECT_THUNK_TCRETURN32 = 359 + + INDIRECT_THUNK_TCRETURN64 = 360 + + KSET0B = 361 + + KSET0D = 362 + + KSET0Q = 363 + + KSET0W = 364 + + KSET1B = 365 + + KSET1D = 366 + + KSET1Q = 367 + + KSET1W = 368 + + LCMPXCHG16B_NO_RBX = 369 + + LCMPXCHG16B_SAVE_RBX = 370 + + MMX_SET0 = 371 + + MORESTACK_RET = 372 + + MORESTACK_RET_RESTORE_R10 = 373 + + MOV32ImmSExti8 = 374 + + MOV32r0 = 375 + + MOV32r1 = 376 + + MOV32r_1 = 377 + + MOV32ri64 = 378 + + MOV64ImmSExti8 = 379 + + MOVSHPmr = 380 + + MOVSHPrm = 381 + + MWAITX = 382 + + MWAITX_SAVE_RBX = 383 + + PLDTILECFGV = 384 + + PLEA32r = 385 + + PLEA64r = 386 + + PTDPBF16PSV = 387 + + PTDPBSSDV = 388 + + PTDPBSUDV = 389 + + PTDPBUSDV = 390 + + PTDPBUUDV = 391 + + PTDPFP16PSV = 392 + + PTILELOADDRST1V = 393 + + PTILELOADDRSV = 394 + + PTILELOADDT1V = 395 + + PTILELOADDV = 396 + + PTILESTOREDV = 397 + + PTILEZEROV = 398 + + RDFLAGS32 = 399 + + RDFLAGS64 = 400 + + SEH_BeginEpilogue = 401 + + SEH_EndEpilogue = 402 + + SEH_EndPrologue = 403 + + SEH_PushFrame = 404 + + SEH_PushReg = 405 + + SEH_SaveReg = 406 + + SEH_SaveXMM = 407 + + SEH_SetFrame = 408 + + SEH_StackAlign = 409 + + SEH_StackAlloc = 410 + + SEH_UnwindV2Start = 411 + + SEH_UnwindVersion = 412 + + SETB_C32r = 413 + + SETB_C64r = 414 + + SHLDROT32ri = 415 + + SHLDROT64ri = 416 + + SHRDROT32ri = 417 + + SHRDROT64ri = 418 + + VMOVAPSZ128mr_NOVLX = 419 + + VMOVAPSZ128rm_NOVLX = 420 + + VMOVAPSZ256mr_NOVLX = 421 + + VMOVAPSZ256rm_NOVLX = 422 + + VMOVUPSZ128mr_NOVLX = 423 + + VMOVUPSZ128rm_NOVLX = 424 + + VMOVUPSZ256mr_NOVLX = 425 + + VMOVUPSZ256rm_NOVLX = 426 + + V_SET0 = 427 + + V_SETALLONES = 428 + + WRFLAGS32 = 429 + + WRFLAGS64 = 430 + + XABORT_DEF = 431 + + XOR32_FP = 432 + + XOR64_FP = 433 + + AAA = 434 + + AAD8i8 = 435 + + AADD32mr = 436 + + AADD32mr_EVEX = 437 + + AADD64mr = 438 + + AADD64mr_EVEX = 439 + + AAM8i8 = 440 + + AAND32mr = 441 + + AAND32mr_EVEX = 442 + + AAND64mr = 443 + + AAND64mr_EVEX = 444 + + AAS = 445 + + ABS_F = 446 + + ABS_Fp32 = 447 + + ABS_Fp64 = 448 + + ABS_Fp80 = 449 + + ADC16i16 = 450 + + ADC16mi = 451 + + ADC16mi8 = 452 + + ADC16mi8_EVEX = 453 + + ADC16mi8_ND = 454 + + ADC16mi_EVEX = 455 + + ADC16mi_ND = 456 + + ADC16mr = 457 + + ADC16mr_EVEX = 458 + + ADC16mr_ND = 459 + + ADC16ri = 460 + + ADC16ri8 = 461 + + ADC16ri8_EVEX = 462 + + ADC16ri8_ND = 463 + + ADC16ri_EVEX = 464 + + ADC16ri_ND = 465 + + ADC16rm = 466 + + ADC16rm_EVEX = 467 + + ADC16rm_ND = 468 + + ADC16rr = 469 + + ADC16rr_EVEX = 470 + + ADC16rr_EVEX_REV = 471 + + ADC16rr_ND = 472 + + ADC16rr_ND_REV = 473 + + ADC16rr_REV = 474 + + ADC32i32 = 475 + + ADC32mi = 476 + + ADC32mi8 = 477 + + ADC32mi8_EVEX = 478 + + ADC32mi8_ND = 479 + + ADC32mi_EVEX = 480 + + ADC32mi_ND = 481 + + ADC32mr = 482 + + ADC32mr_EVEX = 483 + + ADC32mr_ND = 484 + + ADC32ri = 485 + + ADC32ri8 = 486 + + ADC32ri8_EVEX = 487 + + ADC32ri8_ND = 488 + + ADC32ri_EVEX = 489 + + ADC32ri_ND = 490 + + ADC32rm = 491 + + ADC32rm_EVEX = 492 + + ADC32rm_ND = 493 + + ADC32rr = 494 + + ADC32rr_EVEX = 495 + + ADC32rr_EVEX_REV = 496 + + ADC32rr_ND = 497 + + ADC32rr_ND_REV = 498 + + ADC32rr_REV = 499 + + ADC64i32 = 500 + + ADC64mi32 = 501 + + ADC64mi32_EVEX = 502 + + ADC64mi32_ND = 503 + + ADC64mi8 = 504 + + ADC64mi8_EVEX = 505 + + ADC64mi8_ND = 506 + + ADC64mr = 507 + + ADC64mr_EVEX = 508 + + ADC64mr_ND = 509 + + ADC64ri32 = 510 + + ADC64ri32_EVEX = 511 + + ADC64ri32_ND = 512 + + ADC64ri8 = 513 + + ADC64ri8_EVEX = 514 + + ADC64ri8_ND = 515 + + ADC64rm = 516 + + ADC64rm_EVEX = 517 + + ADC64rm_ND = 518 + + ADC64rr = 519 + + ADC64rr_EVEX = 520 + + ADC64rr_EVEX_REV = 521 + + ADC64rr_ND = 522 + + ADC64rr_ND_REV = 523 + + ADC64rr_REV = 524 + + ADC8i8 = 525 + + ADC8mi = 526 + + ADC8mi8 = 527 + + ADC8mi_EVEX = 528 + + ADC8mi_ND = 529 + + ADC8mr = 530 + + ADC8mr_EVEX = 531 + + ADC8mr_ND = 532 + + ADC8ri = 533 + + ADC8ri8 = 534 + + ADC8ri_EVEX = 535 + + ADC8ri_ND = 536 + + ADC8rm = 537 + + ADC8rm_EVEX = 538 + + ADC8rm_ND = 539 + + ADC8rr = 540 + + ADC8rr_EVEX = 541 + + ADC8rr_EVEX_REV = 542 + + ADC8rr_ND = 543 + + ADC8rr_ND_REV = 544 + + ADC8rr_REV = 545 + + ADCX32rm = 546 + + ADCX32rm_EVEX = 547 + + ADCX32rm_ND = 548 + + ADCX32rr = 549 + + ADCX32rr_EVEX = 550 + + ADCX32rr_ND = 551 + + ADCX64rm = 552 + + ADCX64rm_EVEX = 553 + + ADCX64rm_ND = 554 + + ADCX64rr = 555 + + ADCX64rr_EVEX = 556 + + ADCX64rr_ND = 557 + + ADD16i16 = 558 + + ADD16mi = 559 + + ADD16mi8 = 560 + + ADD16mi8_EVEX = 561 + + ADD16mi8_ND = 562 + + ADD16mi8_NF = 563 + + ADD16mi8_NF_ND = 564 + + ADD16mi_EVEX = 565 + + ADD16mi_ND = 566 + + ADD16mi_NF = 567 + + ADD16mi_NF_ND = 568 + + ADD16mr = 569 + + ADD16mr_EVEX = 570 + + ADD16mr_ND = 571 + + ADD16mr_NF = 572 + + ADD16mr_NF_ND = 573 + + ADD16ri = 574 + + ADD16ri8 = 575 + + ADD16ri8_EVEX = 576 + + ADD16ri8_ND = 577 + + ADD16ri8_NF = 578 + + ADD16ri8_NF_ND = 579 + + ADD16ri_EVEX = 580 + + ADD16ri_ND = 581 + + ADD16ri_NF = 582 + + ADD16ri_NF_ND = 583 + + ADD16rm = 584 + + ADD16rm_EVEX = 585 + + ADD16rm_ND = 586 + + ADD16rm_NF = 587 + + ADD16rm_NF_ND = 588 + + ADD16rr = 589 + + ADD16rr_EVEX = 590 + + ADD16rr_EVEX_REV = 591 + + ADD16rr_ND = 592 + + ADD16rr_ND_REV = 593 + + ADD16rr_NF = 594 + + ADD16rr_NF_ND = 595 + + ADD16rr_NF_ND_REV = 596 + + ADD16rr_NF_REV = 597 + + ADD16rr_REV = 598 + + ADD32i32 = 599 + + ADD32mi = 600 + + ADD32mi8 = 601 + + ADD32mi8_EVEX = 602 + + ADD32mi8_ND = 603 + + ADD32mi8_NF = 604 + + ADD32mi8_NF_ND = 605 + + ADD32mi_EVEX = 606 + + ADD32mi_ND = 607 + + ADD32mi_NF = 608 + + ADD32mi_NF_ND = 609 + + ADD32mr = 610 + + ADD32mr_EVEX = 611 + + ADD32mr_ND = 612 + + ADD32mr_NF = 613 + + ADD32mr_NF_ND = 614 + + ADD32ri = 615 + + ADD32ri8 = 616 + + ADD32ri8_EVEX = 617 + + ADD32ri8_ND = 618 + + ADD32ri8_NF = 619 + + ADD32ri8_NF_ND = 620 + + ADD32ri_EVEX = 621 + + ADD32ri_ND = 622 + + ADD32ri_NF = 623 + + ADD32ri_NF_ND = 624 + + ADD32rm = 625 + + ADD32rm_EVEX = 626 + + ADD32rm_ND = 627 + + ADD32rm_NF = 628 + + ADD32rm_NF_ND = 629 + + ADD32rr = 630 + + ADD32rr_EVEX = 631 + + ADD32rr_EVEX_REV = 632 + + ADD32rr_ND = 633 + + ADD32rr_ND_REV = 634 + + ADD32rr_NF = 635 + + ADD32rr_NF_ND = 636 + + ADD32rr_NF_ND_REV = 637 + + ADD32rr_NF_REV = 638 + + ADD32rr_REV = 639 + + ADD64i32 = 640 + + ADD64mi32 = 641 + + ADD64mi32_EVEX = 642 + + ADD64mi32_ND = 643 + + ADD64mi32_NF = 644 + + ADD64mi32_NF_ND = 645 + + ADD64mi8 = 646 + + ADD64mi8_EVEX = 647 + + ADD64mi8_ND = 648 + + ADD64mi8_NF = 649 + + ADD64mi8_NF_ND = 650 + + ADD64mr = 651 + + ADD64mr_EVEX = 652 + + ADD64mr_ND = 653 + + ADD64mr_NF = 654 + + ADD64mr_NF_ND = 655 + + ADD64ri32 = 656 + + ADD64ri32_EVEX = 657 + + ADD64ri32_ND = 658 + + ADD64ri32_NF = 659 + + ADD64ri32_NF_ND = 660 + + ADD64ri8 = 661 + + ADD64ri8_EVEX = 662 + + ADD64ri8_ND = 663 + + ADD64ri8_NF = 664 + + ADD64ri8_NF_ND = 665 + + ADD64rm = 666 + + ADD64rm_EVEX = 667 + + ADD64rm_ND = 668 + + ADD64rm_NF = 669 + + ADD64rm_NF_ND = 670 + + ADD64rr = 671 + + ADD64rr_EVEX = 672 + + ADD64rr_EVEX_REV = 673 + + ADD64rr_ND = 674 + + ADD64rr_ND_REV = 675 + + ADD64rr_NF = 676 + + ADD64rr_NF_ND = 677 + + ADD64rr_NF_ND_REV = 678 + + ADD64rr_NF_REV = 679 + + ADD64rr_REV = 680 + + ADD8i8 = 681 + + ADD8mi = 682 + + ADD8mi8 = 683 + + ADD8mi_EVEX = 684 + + ADD8mi_ND = 685 + + ADD8mi_NF = 686 + + ADD8mi_NF_ND = 687 + + ADD8mr = 688 + + ADD8mr_EVEX = 689 + + ADD8mr_ND = 690 + + ADD8mr_NF = 691 + + ADD8mr_NF_ND = 692 + + ADD8ri = 693 + + ADD8ri8 = 694 + + ADD8ri_EVEX = 695 + + ADD8ri_ND = 696 + + ADD8ri_NF = 697 + + ADD8ri_NF_ND = 698 + + ADD8rm = 699 + + ADD8rm_EVEX = 700 + + ADD8rm_ND = 701 + + ADD8rm_NF = 702 + + ADD8rm_NF_ND = 703 + + ADD8rr = 704 + + ADD8rr_EVEX = 705 + + ADD8rr_EVEX_REV = 706 + + ADD8rr_ND = 707 + + ADD8rr_ND_REV = 708 + + ADD8rr_NF = 709 + + ADD8rr_NF_ND = 710 + + ADD8rr_NF_ND_REV = 711 + + ADD8rr_NF_REV = 712 + + ADD8rr_REV = 713 + + ADDPDrm = 714 + + ADDPDrr = 715 + + ADDPSrm = 716 + + ADDPSrr = 717 + + ADDR16_PREFIX = 718 + + ADDR32_PREFIX = 719 + + ADDSDrm = 720 + + ADDSDrm_Int = 721 + + ADDSDrr = 722 + + ADDSDrr_Int = 723 + + ADDSSrm = 724 + + ADDSSrm_Int = 725 + + ADDSSrr = 726 + + ADDSSrr_Int = 727 + + ADDSUBPDrm = 728 + + ADDSUBPDrr = 729 + + ADDSUBPSrm = 730 + + ADDSUBPSrr = 731 + + ADD_F32m = 732 + + ADD_F64m = 733 + + ADD_FI16m = 734 + + ADD_FI32m = 735 + + ADD_FPrST0 = 736 + + ADD_FST0r = 737 + + ADD_Fp32 = 738 + + ADD_Fp32m = 739 + + ADD_Fp64 = 740 + + ADD_Fp64m = 741 + + ADD_Fp64m32 = 742 + + ADD_Fp80 = 743 + + ADD_Fp80m32 = 744 + + ADD_Fp80m64 = 745 + + ADD_FpI16m32 = 746 + + ADD_FpI16m64 = 747 + + ADD_FpI16m80 = 748 + + ADD_FpI32m32 = 749 + + ADD_FpI32m64 = 750 + + ADD_FpI32m80 = 751 + + ADD_FrST0 = 752 + + ADJCALLSTACKDOWN32 = 753 + + ADJCALLSTACKDOWN64 = 754 + + ADJCALLSTACKUP32 = 755 + + ADJCALLSTACKUP64 = 756 + + ADOX32rm = 757 + + ADOX32rm_EVEX = 758 + + ADOX32rm_ND = 759 + + ADOX32rr = 760 + + ADOX32rr_EVEX = 761 + + ADOX32rr_ND = 762 + + ADOX64rm = 763 + + ADOX64rm_EVEX = 764 + + ADOX64rm_ND = 765 + + ADOX64rr = 766 + + ADOX64rr_EVEX = 767 + + ADOX64rr_ND = 768 + + AESDEC128KL = 769 + + AESDEC256KL = 770 + + AESDECLASTrm = 771 + + AESDECLASTrr = 772 + + AESDECWIDE128KL = 773 + + AESDECWIDE256KL = 774 + + AESDECrm = 775 + + AESDECrr = 776 + + AESENC128KL = 777 + + AESENC256KL = 778 + + AESENCLASTrm = 779 + + AESENCLASTrr = 780 + + AESENCWIDE128KL = 781 + + AESENCWIDE256KL = 782 + + AESENCrm = 783 + + AESENCrr = 784 + + AESIMCrm = 785 + + AESIMCrr = 786 + + AESKEYGENASSISTrmi = 787 + + AESKEYGENASSISTrri = 788 + + AND16i16 = 789 + + AND16mi = 790 + + AND16mi8 = 791 + + AND16mi8_EVEX = 792 + + AND16mi8_ND = 793 + + AND16mi8_NF = 794 + + AND16mi8_NF_ND = 795 + + AND16mi_EVEX = 796 + + AND16mi_ND = 797 + + AND16mi_NF = 798 + + AND16mi_NF_ND = 799 + + AND16mr = 800 + + AND16mr_EVEX = 801 + + AND16mr_ND = 802 + + AND16mr_NF = 803 + + AND16mr_NF_ND = 804 + + AND16ri = 805 + + AND16ri8 = 806 + + AND16ri8_EVEX = 807 + + AND16ri8_ND = 808 + + AND16ri8_NF = 809 + + AND16ri8_NF_ND = 810 + + AND16ri_EVEX = 811 + + AND16ri_ND = 812 + + AND16ri_NF = 813 + + AND16ri_NF_ND = 814 + + AND16rm = 815 + + AND16rm_EVEX = 816 + + AND16rm_ND = 817 + + AND16rm_NF = 818 + + AND16rm_NF_ND = 819 + + AND16rr = 820 + + AND16rr_EVEX = 821 + + AND16rr_EVEX_REV = 822 + + AND16rr_ND = 823 + + AND16rr_ND_REV = 824 + + AND16rr_NF = 825 + + AND16rr_NF_ND = 826 + + AND16rr_NF_ND_REV = 827 + + AND16rr_NF_REV = 828 + + AND16rr_REV = 829 + + AND32i32 = 830 + + AND32mi = 831 + + AND32mi8 = 832 + + AND32mi8_EVEX = 833 + + AND32mi8_ND = 834 + + AND32mi8_NF = 835 + + AND32mi8_NF_ND = 836 + + AND32mi_EVEX = 837 + + AND32mi_ND = 838 + + AND32mi_NF = 839 + + AND32mi_NF_ND = 840 + + AND32mr = 841 + + AND32mr_EVEX = 842 + + AND32mr_ND = 843 + + AND32mr_NF = 844 + + AND32mr_NF_ND = 845 + + AND32ri = 846 + + AND32ri8 = 847 + + AND32ri8_EVEX = 848 + + AND32ri8_ND = 849 + + AND32ri8_NF = 850 + + AND32ri8_NF_ND = 851 + + AND32ri_EVEX = 852 + + AND32ri_ND = 853 + + AND32ri_NF = 854 + + AND32ri_NF_ND = 855 + + AND32rm = 856 + + AND32rm_EVEX = 857 + + AND32rm_ND = 858 + + AND32rm_NF = 859 + + AND32rm_NF_ND = 860 + + AND32rr = 861 + + AND32rr_EVEX = 862 + + AND32rr_EVEX_REV = 863 + + AND32rr_ND = 864 + + AND32rr_ND_REV = 865 + + AND32rr_NF = 866 + + AND32rr_NF_ND = 867 + + AND32rr_NF_ND_REV = 868 + + AND32rr_NF_REV = 869 + + AND32rr_REV = 870 + + AND64i32 = 871 + + AND64mi32 = 872 + + AND64mi32_EVEX = 873 + + AND64mi32_ND = 874 + + AND64mi32_NF = 875 + + AND64mi32_NF_ND = 876 + + AND64mi8 = 877 + + AND64mi8_EVEX = 878 + + AND64mi8_ND = 879 + + AND64mi8_NF = 880 + + AND64mi8_NF_ND = 881 + + AND64mr = 882 + + AND64mr_EVEX = 883 + + AND64mr_ND = 884 + + AND64mr_NF = 885 + + AND64mr_NF_ND = 886 + + AND64ri32 = 887 + + AND64ri32_EVEX = 888 + + AND64ri32_ND = 889 + + AND64ri32_NF = 890 + + AND64ri32_NF_ND = 891 + + AND64ri8 = 892 + + AND64ri8_EVEX = 893 + + AND64ri8_ND = 894 + + AND64ri8_NF = 895 + + AND64ri8_NF_ND = 896 + + AND64rm = 897 + + AND64rm_EVEX = 898 + + AND64rm_ND = 899 + + AND64rm_NF = 900 + + AND64rm_NF_ND = 901 + + AND64rr = 902 + + AND64rr_EVEX = 903 + + AND64rr_EVEX_REV = 904 + + AND64rr_ND = 905 + + AND64rr_ND_REV = 906 + + AND64rr_NF = 907 + + AND64rr_NF_ND = 908 + + AND64rr_NF_ND_REV = 909 + + AND64rr_NF_REV = 910 + + AND64rr_REV = 911 + + AND8i8 = 912 + + AND8mi = 913 + + AND8mi8 = 914 + + AND8mi_EVEX = 915 + + AND8mi_ND = 916 + + AND8mi_NF = 917 + + AND8mi_NF_ND = 918 + + AND8mr = 919 + + AND8mr_EVEX = 920 + + AND8mr_ND = 921 + + AND8mr_NF = 922 + + AND8mr_NF_ND = 923 + + AND8ri = 924 + + AND8ri8 = 925 + + AND8ri_EVEX = 926 + + AND8ri_ND = 927 + + AND8ri_NF = 928 + + AND8ri_NF_ND = 929 + + AND8rm = 930 + + AND8rm_EVEX = 931 + + AND8rm_ND = 932 + + AND8rm_NF = 933 + + AND8rm_NF_ND = 934 + + AND8rr = 935 + + AND8rr_EVEX = 936 + + AND8rr_EVEX_REV = 937 + + AND8rr_ND = 938 + + AND8rr_ND_REV = 939 + + AND8rr_NF = 940 + + AND8rr_NF_ND = 941 + + AND8rr_NF_ND_REV = 942 + + AND8rr_NF_REV = 943 + + AND8rr_REV = 944 + + ANDN32rm = 945 + + ANDN32rm_EVEX = 946 + + ANDN32rm_NF = 947 + + ANDN32rr = 948 + + ANDN32rr_EVEX = 949 + + ANDN32rr_NF = 950 + + ANDN64rm = 951 + + ANDN64rm_EVEX = 952 + + ANDN64rm_NF = 953 + + ANDN64rr = 954 + + ANDN64rr_EVEX = 955 + + ANDN64rr_NF = 956 + + ANDNPDrm = 957 + + ANDNPDrr = 958 + + ANDNPSrm = 959 + + ANDNPSrr = 960 + + ANDPDrm = 961 + + ANDPDrr = 962 + + ANDPSrm = 963 + + ANDPSrr = 964 + + AOR32mr = 965 + + AOR32mr_EVEX = 966 + + AOR64mr = 967 + + AOR64mr_EVEX = 968 + + ARPL16mr = 969 + + ARPL16rr = 970 + + ASAN_CHECK_MEMACCESS = 971 + + AXOR32mr = 972 + + AXOR32mr_EVEX = 973 + + AXOR64mr = 974 + + AXOR64mr_EVEX = 975 + + BEXTR32rm = 976 + + BEXTR32rm_EVEX = 977 + + BEXTR32rm_NF = 978 + + BEXTR32rr = 979 + + BEXTR32rr_EVEX = 980 + + BEXTR32rr_NF = 981 + + BEXTR64rm = 982 + + BEXTR64rm_EVEX = 983 + + BEXTR64rm_NF = 984 + + BEXTR64rr = 985 + + BEXTR64rr_EVEX = 986 + + BEXTR64rr_NF = 987 + + BEXTRI32mi = 988 + + BEXTRI32ri = 989 + + BEXTRI64mi = 990 + + BEXTRI64ri = 991 + + BLCFILL32rm = 992 + + BLCFILL32rr = 993 + + BLCFILL64rm = 994 + + BLCFILL64rr = 995 + + BLCI32rm = 996 + + BLCI32rr = 997 + + BLCI64rm = 998 + + BLCI64rr = 999 + + BLCIC32rm = 1000 + + BLCIC32rr = 1001 + + BLCIC64rm = 1002 + + BLCIC64rr = 1003 + + BLCMSK32rm = 1004 + + BLCMSK32rr = 1005 + + BLCMSK64rm = 1006 + + BLCMSK64rr = 1007 + + BLCS32rm = 1008 + + BLCS32rr = 1009 + + BLCS64rm = 1010 + + BLCS64rr = 1011 + + BLENDPDrmi = 1012 + + BLENDPDrri = 1013 + + BLENDPSrmi = 1014 + + BLENDPSrri = 1015 + + BLENDVPDrm0 = 1016 + + BLENDVPDrr0 = 1017 + + BLENDVPSrm0 = 1018 + + BLENDVPSrr0 = 1019 + + BLSFILL32rm = 1020 + + BLSFILL32rr = 1021 + + BLSFILL64rm = 1022 + + BLSFILL64rr = 1023 + + BLSI32rm = 1024 + + BLSI32rm_EVEX = 1025 + + BLSI32rm_NF = 1026 + + BLSI32rr = 1027 + + BLSI32rr_EVEX = 1028 + + BLSI32rr_NF = 1029 + + BLSI64rm = 1030 + + BLSI64rm_EVEX = 1031 + + BLSI64rm_NF = 1032 + + BLSI64rr = 1033 + + BLSI64rr_EVEX = 1034 + + BLSI64rr_NF = 1035 + + BLSIC32rm = 1036 + + BLSIC32rr = 1037 + + BLSIC64rm = 1038 + + BLSIC64rr = 1039 + + BLSMSK32rm = 1040 + + BLSMSK32rm_EVEX = 1041 + + BLSMSK32rm_NF = 1042 + + BLSMSK32rr = 1043 + + BLSMSK32rr_EVEX = 1044 + + BLSMSK32rr_NF = 1045 + + BLSMSK64rm = 1046 + + BLSMSK64rm_EVEX = 1047 + + BLSMSK64rm_NF = 1048 + + BLSMSK64rr = 1049 + + BLSMSK64rr_EVEX = 1050 + + BLSMSK64rr_NF = 1051 + + BLSR32rm = 1052 + + BLSR32rm_EVEX = 1053 + + BLSR32rm_NF = 1054 + + BLSR32rr = 1055 + + BLSR32rr_EVEX = 1056 + + BLSR32rr_NF = 1057 + + BLSR64rm = 1058 + + BLSR64rm_EVEX = 1059 + + BLSR64rm_NF = 1060 + + BLSR64rr = 1061 + + BLSR64rr_EVEX = 1062 + + BLSR64rr_NF = 1063 + + BOUNDS16rm = 1064 + + BOUNDS32rm = 1065 + + BSF16rm = 1066 + + BSF16rr = 1067 + + BSF32rm = 1068 + + BSF32rr = 1069 + + BSF64rm = 1070 + + BSF64rr = 1071 + + BSR16rm = 1072 + + BSR16rr = 1073 + + BSR32rm = 1074 + + BSR32rr = 1075 + + BSR64rm = 1076 + + BSR64rr = 1077 + + BSWAP16r_BAD = 1078 + + BSWAP32r = 1079 + + BSWAP64r = 1080 + + BT16mi8 = 1081 + + BT16mr = 1082 + + BT16ri8 = 1083 + + BT16rr = 1084 + + BT32mi8 = 1085 + + BT32mr = 1086 + + BT32ri8 = 1087 + + BT32rr = 1088 + + BT64mi8 = 1089 + + BT64mr = 1090 + + BT64ri8 = 1091 + + BT64rr = 1092 + + BTC16mi8 = 1093 + + BTC16mr = 1094 + + BTC16ri8 = 1095 + + BTC16rr = 1096 + + BTC32mi8 = 1097 + + BTC32mr = 1098 + + BTC32ri8 = 1099 + + BTC32rr = 1100 + + BTC64mi8 = 1101 + + BTC64mr = 1102 + + BTC64ri8 = 1103 + + BTC64rr = 1104 + + BTR16mi8 = 1105 + + BTR16mr = 1106 + + BTR16ri8 = 1107 + + BTR16rr = 1108 + + BTR32mi8 = 1109 + + BTR32mr = 1110 + + BTR32ri8 = 1111 + + BTR32rr = 1112 + + BTR64mi8 = 1113 + + BTR64mr = 1114 + + BTR64ri8 = 1115 + + BTR64rr = 1116 + + BTS16mi8 = 1117 + + BTS16mr = 1118 + + BTS16ri8 = 1119 + + BTS16rr = 1120 + + BTS32mi8 = 1121 + + BTS32mr = 1122 + + BTS32ri8 = 1123 + + BTS32rr = 1124 + + BTS64mi8 = 1125 + + BTS64mr = 1126 + + BTS64ri8 = 1127 + + BTS64rr = 1128 + + BZHI32rm = 1129 + + BZHI32rm_EVEX = 1130 + + BZHI32rm_NF = 1131 + + BZHI32rr = 1132 + + BZHI32rr_EVEX = 1133 + + BZHI32rr_NF = 1134 + + BZHI64rm = 1135 + + BZHI64rm_EVEX = 1136 + + BZHI64rm_NF = 1137 + + BZHI64rr = 1138 + + BZHI64rr_EVEX = 1139 + + BZHI64rr_NF = 1140 + + CALL16m = 1141 + + CALL16m_NT = 1142 + + CALL16r = 1143 + + CALL16r_NT = 1144 + + CALL32m = 1145 + + CALL32m_NT = 1146 + + CALL32r = 1147 + + CALL32r_NT = 1148 + + CALL64m = 1149 + + CALL64m_NT = 1150 + + CALL64pcrel32 = 1151 + + CALL64r = 1152 + + CALL64r_NT = 1153 + + CALLpcrel16 = 1154 + + CALLpcrel32 = 1155 + + CATCHRET = 1156 + + CBW = 1157 + + CCMP16mi = 1158 + + CCMP16mi8 = 1159 + + CCMP16mr = 1160 + + CCMP16ri = 1161 + + CCMP16ri8 = 1162 + + CCMP16rm = 1163 + + CCMP16rr = 1164 + + CCMP16rr_REV = 1165 + + CCMP32mi = 1166 + + CCMP32mi8 = 1167 + + CCMP32mr = 1168 + + CCMP32ri = 1169 + + CCMP32ri8 = 1170 + + CCMP32rm = 1171 + + CCMP32rr = 1172 + + CCMP32rr_REV = 1173 + + CCMP64mi32 = 1174 + + CCMP64mi8 = 1175 + + CCMP64mr = 1176 + + CCMP64ri32 = 1177 + + CCMP64ri8 = 1178 + + CCMP64rm = 1179 + + CCMP64rr = 1180 + + CCMP64rr_REV = 1181 + + CCMP8mi = 1182 + + CCMP8mr = 1183 + + CCMP8ri = 1184 + + CCMP8rm = 1185 + + CCMP8rr = 1186 + + CCMP8rr_REV = 1187 + + CDQ = 1188 + + CDQE = 1189 + + CFCMOV16mr = 1190 + + CFCMOV16rm = 1191 + + CFCMOV16rm_ND = 1192 + + CFCMOV16rr = 1193 + + CFCMOV16rr_ND = 1194 + + CFCMOV16rr_REV = 1195 + + CFCMOV32mr = 1196 + + CFCMOV32rm = 1197 + + CFCMOV32rm_ND = 1198 + + CFCMOV32rr = 1199 + + CFCMOV32rr_ND = 1200 + + CFCMOV32rr_REV = 1201 + + CFCMOV64mr = 1202 + + CFCMOV64rm = 1203 + + CFCMOV64rm_ND = 1204 + + CFCMOV64rr = 1205 + + CFCMOV64rr_ND = 1206 + + CFCMOV64rr_REV = 1207 + + CHS_F = 1208 + + CHS_Fp32 = 1209 + + CHS_Fp64 = 1210 + + CHS_Fp80 = 1211 + + CLAC = 1212 + + CLC = 1213 + + CLD = 1214 + + CLDEMOTE = 1215 + + CLEANUPRET = 1216 + + CLFLUSH = 1217 + + CLFLUSHOPT = 1218 + + CLGI = 1219 + + CLI = 1220 + + CLRSSBSY = 1221 + + CLTS = 1222 + + CLUI = 1223 + + CLWB = 1224 + + CLZERO32r = 1225 + + CLZERO64r = 1226 + + CMC = 1227 + + CMOV16rm = 1228 + + CMOV16rm_ND = 1229 + + CMOV16rr = 1230 + + CMOV16rr_ND = 1231 + + CMOV32rm = 1232 + + CMOV32rm_ND = 1233 + + CMOV32rr = 1234 + + CMOV32rr_ND = 1235 + + CMOV64rm = 1236 + + CMOV64rm_ND = 1237 + + CMOV64rr = 1238 + + CMOV64rr_ND = 1239 + + CMOVBE_F = 1240 + + CMOVBE_Fp32 = 1241 + + CMOVBE_Fp64 = 1242 + + CMOVBE_Fp80 = 1243 + + CMOVB_F = 1244 + + CMOVB_Fp32 = 1245 + + CMOVB_Fp64 = 1246 + + CMOVB_Fp80 = 1247 + + CMOVE_F = 1248 + + CMOVE_Fp32 = 1249 + + CMOVE_Fp64 = 1250 + + CMOVE_Fp80 = 1251 + + CMOVNBE_F = 1252 + + CMOVNBE_Fp32 = 1253 + + CMOVNBE_Fp64 = 1254 + + CMOVNBE_Fp80 = 1255 + + CMOVNB_F = 1256 + + CMOVNB_Fp32 = 1257 + + CMOVNB_Fp64 = 1258 + + CMOVNB_Fp80 = 1259 + + CMOVNE_F = 1260 + + CMOVNE_Fp32 = 1261 + + CMOVNE_Fp64 = 1262 + + CMOVNE_Fp80 = 1263 + + CMOVNP_F = 1264 + + CMOVNP_Fp32 = 1265 + + CMOVNP_Fp64 = 1266 + + CMOVNP_Fp80 = 1267 + + CMOVP_F = 1268 + + CMOVP_Fp32 = 1269 + + CMOVP_Fp64 = 1270 + + CMOVP_Fp80 = 1271 + + CMOV_FR16 = 1272 + + CMOV_FR16X = 1273 + + CMOV_FR32 = 1274 + + CMOV_FR32X = 1275 + + CMOV_FR64 = 1276 + + CMOV_FR64X = 1277 + + CMOV_GR16 = 1278 + + CMOV_GR32 = 1279 + + CMOV_GR8 = 1280 + + CMOV_RFP32 = 1281 + + CMOV_RFP64 = 1282 + + CMOV_RFP80 = 1283 + + CMOV_VK1 = 1284 + + CMOV_VK16 = 1285 + + CMOV_VK2 = 1286 + + CMOV_VK32 = 1287 + + CMOV_VK4 = 1288 + + CMOV_VK64 = 1289 + + CMOV_VK8 = 1290 + + CMOV_VR128 = 1291 + + CMOV_VR128X = 1292 + + CMOV_VR256 = 1293 + + CMOV_VR256X = 1294 + + CMOV_VR512 = 1295 + + CMOV_VR64 = 1296 + + CMP16i16 = 1297 + + CMP16mi = 1298 + + CMP16mi8 = 1299 + + CMP16mr = 1300 + + CMP16ri = 1301 + + CMP16ri8 = 1302 + + CMP16rm = 1303 + + CMP16rr = 1304 + + CMP16rr_REV = 1305 + + CMP32i32 = 1306 + + CMP32mi = 1307 + + CMP32mi8 = 1308 + + CMP32mr = 1309 + + CMP32ri = 1310 + + CMP32ri8 = 1311 + + CMP32rm = 1312 + + CMP32rr = 1313 + + CMP32rr_REV = 1314 + + CMP64i32 = 1315 + + CMP64mi32 = 1316 + + CMP64mi8 = 1317 + + CMP64mr = 1318 + + CMP64ri32 = 1319 + + CMP64ri8 = 1320 + + CMP64rm = 1321 + + CMP64rr = 1322 + + CMP64rr_REV = 1323 + + CMP8i8 = 1324 + + CMP8mi = 1325 + + CMP8mi8 = 1326 + + CMP8mr = 1327 + + CMP8ri = 1328 + + CMP8ri8 = 1329 + + CMP8rm = 1330 + + CMP8rr = 1331 + + CMP8rr_REV = 1332 + + CMPCCXADDmr32 = 1333 + + CMPCCXADDmr32_EVEX = 1334 + + CMPCCXADDmr64 = 1335 + + CMPCCXADDmr64_EVEX = 1336 + + CMPPDrmi = 1337 + + CMPPDrri = 1338 + + CMPPSrmi = 1339 + + CMPPSrri = 1340 + + CMPSB = 1341 + + CMPSDrmi = 1342 + + CMPSDrmi_Int = 1343 + + CMPSDrri = 1344 + + CMPSDrri_Int = 1345 + + CMPSL = 1346 + + CMPSQ = 1347 + + CMPSSrmi = 1348 + + CMPSSrmi_Int = 1349 + + CMPSSrri = 1350 + + CMPSSrri_Int = 1351 + + CMPSW = 1352 + + CMPXCHG16B = 1353 + + CMPXCHG16rm = 1354 + + CMPXCHG16rr = 1355 + + CMPXCHG32rm = 1356 + + CMPXCHG32rr = 1357 + + CMPXCHG64rm = 1358 + + CMPXCHG64rr = 1359 + + CMPXCHG8B = 1360 + + CMPXCHG8rm = 1361 + + CMPXCHG8rr = 1362 + + COMISDrm = 1363 + + COMISDrm_Int = 1364 + + COMISDrr = 1365 + + COMISDrr_Int = 1366 + + COMISSrm = 1367 + + COMISSrm_Int = 1368 + + COMISSrr = 1369 + + COMISSrr_Int = 1370 + + COMP_FST0r = 1371 + + COM_FIPr = 1372 + + COM_FIr = 1373 + + COM_FST0r = 1374 + + COM_FpIr32 = 1375 + + COM_FpIr64 = 1376 + + COM_FpIr80 = 1377 + + COM_Fpr32 = 1378 + + COM_Fpr64 = 1379 + + COM_Fpr80 = 1380 + + CPUID = 1381 + + CQO = 1382 + + CRC32r32m16 = 1383 + + CRC32r32m16_EVEX = 1384 + + CRC32r32m32 = 1385 + + CRC32r32m32_EVEX = 1386 + + CRC32r32m8 = 1387 + + CRC32r32m8_EVEX = 1388 + + CRC32r32r16 = 1389 + + CRC32r32r16_EVEX = 1390 + + CRC32r32r32 = 1391 + + CRC32r32r32_EVEX = 1392 + + CRC32r32r8 = 1393 + + CRC32r32r8_EVEX = 1394 + + CRC32r64m64 = 1395 + + CRC32r64m64_EVEX = 1396 + + CRC32r64m8 = 1397 + + CRC32r64m8_EVEX = 1398 + + CRC32r64r64 = 1399 + + CRC32r64r64_EVEX = 1400 + + CRC32r64r8 = 1401 + + CRC32r64r8_EVEX = 1402 + + CS_PREFIX = 1403 + + CTEST16mi = 1404 + + CTEST16mr = 1405 + + CTEST16ri = 1406 + + CTEST16rr = 1407 + + CTEST32mi = 1408 + + CTEST32mr = 1409 + + CTEST32ri = 1410 + + CTEST32rr = 1411 + + CTEST64mi32 = 1412 + + CTEST64mr = 1413 + + CTEST64ri32 = 1414 + + CTEST64rr = 1415 + + CTEST8mi = 1416 + + CTEST8mr = 1417 + + CTEST8ri = 1418 + + CTEST8rr = 1419 + + CVTDQ2PDrm = 1420 + + CVTDQ2PDrr = 1421 + + CVTDQ2PSrm = 1422 + + CVTDQ2PSrr = 1423 + + CVTPD2DQrm = 1424 + + CVTPD2DQrr = 1425 + + CVTPD2PSrm = 1426 + + CVTPD2PSrr = 1427 + + CVTPS2DQrm = 1428 + + CVTPS2DQrr = 1429 + + CVTPS2PDrm = 1430 + + CVTPS2PDrr = 1431 + + CVTSD2SI64rm = 1432 + + CVTSD2SI64rm_Int = 1433 + + CVTSD2SI64rr = 1434 + + CVTSD2SI64rr_Int = 1435 + + CVTSD2SIrm = 1436 + + CVTSD2SIrm_Int = 1437 + + CVTSD2SIrr = 1438 + + CVTSD2SIrr_Int = 1439 + + CVTSD2SSrm = 1440 + + CVTSD2SSrm_Int = 1441 + + CVTSD2SSrr = 1442 + + CVTSD2SSrr_Int = 1443 + + CVTSI2SDrm = 1444 + + CVTSI2SDrm_Int = 1445 + + CVTSI2SDrr = 1446 + + CVTSI2SDrr_Int = 1447 + + CVTSI2SSrm = 1448 + + CVTSI2SSrm_Int = 1449 + + CVTSI2SSrr = 1450 + + CVTSI2SSrr_Int = 1451 + + CVTSI642SDrm = 1452 + + CVTSI642SDrm_Int = 1453 + + CVTSI642SDrr = 1454 + + CVTSI642SDrr_Int = 1455 + + CVTSI642SSrm = 1456 + + CVTSI642SSrm_Int = 1457 + + CVTSI642SSrr = 1458 + + CVTSI642SSrr_Int = 1459 + + CVTSS2SDrm = 1460 + + CVTSS2SDrm_Int = 1461 + + CVTSS2SDrr = 1462 + + CVTSS2SDrr_Int = 1463 + + CVTSS2SI64rm = 1464 + + CVTSS2SI64rm_Int = 1465 + + CVTSS2SI64rr = 1466 + + CVTSS2SI64rr_Int = 1467 + + CVTSS2SIrm = 1468 + + CVTSS2SIrm_Int = 1469 + + CVTSS2SIrr = 1470 + + CVTSS2SIrr_Int = 1471 + + CVTTPD2DQrm = 1472 + + CVTTPD2DQrr = 1473 + + CVTTPS2DQrm = 1474 + + CVTTPS2DQrr = 1475 + + CVTTSD2SI64rm = 1476 + + CVTTSD2SI64rm_Int = 1477 + + CVTTSD2SI64rr = 1478 + + CVTTSD2SI64rr_Int = 1479 + + CVTTSD2SIrm = 1480 + + CVTTSD2SIrm_Int = 1481 + + CVTTSD2SIrr = 1482 + + CVTTSD2SIrr_Int = 1483 + + CVTTSS2SI64rm = 1484 + + CVTTSS2SI64rm_Int = 1485 + + CVTTSS2SI64rr = 1486 + + CVTTSS2SI64rr_Int = 1487 + + CVTTSS2SIrm = 1488 + + CVTTSS2SIrm_Int = 1489 + + CVTTSS2SIrr = 1490 + + CVTTSS2SIrr_Int = 1491 + + CWD = 1492 + + CWDE = 1493 + + DAA = 1494 + + DAS = 1495 + + DATA16_PREFIX = 1496 + + DEC16m = 1497 + + DEC16m_EVEX = 1498 + + DEC16m_ND = 1499 + + DEC16m_NF = 1500 + + DEC16m_NF_ND = 1501 + + DEC16r = 1502 + + DEC16r_EVEX = 1503 + + DEC16r_ND = 1504 + + DEC16r_NF = 1505 + + DEC16r_NF_ND = 1506 + + DEC16r_alt = 1507 + + DEC32m = 1508 + + DEC32m_EVEX = 1509 + + DEC32m_ND = 1510 + + DEC32m_NF = 1511 + + DEC32m_NF_ND = 1512 + + DEC32r = 1513 + + DEC32r_EVEX = 1514 + + DEC32r_ND = 1515 + + DEC32r_NF = 1516 + + DEC32r_NF_ND = 1517 + + DEC32r_alt = 1518 + + DEC64m = 1519 + + DEC64m_EVEX = 1520 + + DEC64m_ND = 1521 + + DEC64m_NF = 1522 + + DEC64m_NF_ND = 1523 + + DEC64r = 1524 + + DEC64r_EVEX = 1525 + + DEC64r_ND = 1526 + + DEC64r_NF = 1527 + + DEC64r_NF_ND = 1528 + + DEC8m = 1529 + + DEC8m_EVEX = 1530 + + DEC8m_ND = 1531 + + DEC8m_NF = 1532 + + DEC8m_NF_ND = 1533 + + DEC8r = 1534 + + DEC8r_EVEX = 1535 + + DEC8r_ND = 1536 + + DEC8r_NF = 1537 + + DEC8r_NF_ND = 1538 + + DIV16m = 1539 + + DIV16m_EVEX = 1540 + + DIV16m_NF = 1541 + + DIV16r = 1542 + + DIV16r_EVEX = 1543 + + DIV16r_NF = 1544 + + DIV32m = 1545 + + DIV32m_EVEX = 1546 + + DIV32m_NF = 1547 + + DIV32r = 1548 + + DIV32r_EVEX = 1549 + + DIV32r_NF = 1550 + + DIV64m = 1551 + + DIV64m_EVEX = 1552 + + DIV64m_NF = 1553 + + DIV64r = 1554 + + DIV64r_EVEX = 1555 + + DIV64r_NF = 1556 + + DIV8m = 1557 + + DIV8m_EVEX = 1558 + + DIV8m_NF = 1559 + + DIV8r = 1560 + + DIV8r_EVEX = 1561 + + DIV8r_NF = 1562 + + DIVPDrm = 1563 + + DIVPDrr = 1564 + + DIVPSrm = 1565 + + DIVPSrr = 1566 + + DIVR_F32m = 1567 + + DIVR_F64m = 1568 + + DIVR_FI16m = 1569 + + DIVR_FI32m = 1570 + + DIVR_FPrST0 = 1571 + + DIVR_FST0r = 1572 + + DIVR_Fp32m = 1573 + + DIVR_Fp64m = 1574 + + DIVR_Fp64m32 = 1575 + + DIVR_Fp80m32 = 1576 + + DIVR_Fp80m64 = 1577 + + DIVR_FpI16m32 = 1578 + + DIVR_FpI16m64 = 1579 + + DIVR_FpI16m80 = 1580 + + DIVR_FpI32m32 = 1581 + + DIVR_FpI32m64 = 1582 + + DIVR_FpI32m80 = 1583 + + DIVR_FrST0 = 1584 + + DIVSDrm = 1585 + + DIVSDrm_Int = 1586 + + DIVSDrr = 1587 + + DIVSDrr_Int = 1588 + + DIVSSrm = 1589 + + DIVSSrm_Int = 1590 + + DIVSSrr = 1591 + + DIVSSrr_Int = 1592 + + DIV_F32m = 1593 + + DIV_F64m = 1594 + + DIV_FI16m = 1595 + + DIV_FI32m = 1596 + + DIV_FPrST0 = 1597 + + DIV_FST0r = 1598 + + DIV_Fp32 = 1599 + + DIV_Fp32m = 1600 + + DIV_Fp64 = 1601 + + DIV_Fp64m = 1602 + + DIV_Fp64m32 = 1603 + + DIV_Fp80 = 1604 + + DIV_Fp80m32 = 1605 + + DIV_Fp80m64 = 1606 + + DIV_FpI16m32 = 1607 + + DIV_FpI16m64 = 1608 + + DIV_FpI16m80 = 1609 + + DIV_FpI32m32 = 1610 + + DIV_FpI32m64 = 1611 + + DIV_FpI32m80 = 1612 + + DIV_FrST0 = 1613 + + DPPDrmi = 1614 + + DPPDrri = 1615 + + DPPSrmi = 1616 + + DPPSrri = 1617 + + DS_PREFIX = 1618 + + DYN_ALLOCA_32 = 1619 + + DYN_ALLOCA_64 = 1620 + + EH_RETURN = 1621 + + EH_RETURN64 = 1622 + + EH_SjLj_LongJmp32 = 1623 + + EH_SjLj_LongJmp64 = 1624 + + EH_SjLj_SetJmp32 = 1625 + + EH_SjLj_SetJmp64 = 1626 + + EH_SjLj_Setup = 1627 + + ENCLS = 1628 + + ENCLU = 1629 + + ENCLV = 1630 + + ENCODEKEY128 = 1631 + + ENCODEKEY256 = 1632 + + ENDBR32 = 1633 + + ENDBR64 = 1634 + + ENQCMD16 = 1635 + + ENQCMD32 = 1636 + + ENQCMD32_EVEX = 1637 + + ENQCMD64 = 1638 + + ENQCMD64_EVEX = 1639 + + ENQCMDS16 = 1640 + + ENQCMDS32 = 1641 + + ENQCMDS32_EVEX = 1642 + + ENQCMDS64 = 1643 + + ENQCMDS64_EVEX = 1644 + + ENTER = 1645 + + ERETS = 1646 + + ERETU = 1647 + + ES_PREFIX = 1648 + + EXTRACTPSmri = 1649 + + EXTRACTPSrri = 1650 + + EXTRQ = 1651 + + EXTRQI = 1652 + + F2XM1 = 1653 + + FARCALL16i = 1654 + + FARCALL16m = 1655 + + FARCALL32i = 1656 + + FARCALL32m = 1657 + + FARCALL64m = 1658 + + FARJMP16i = 1659 + + FARJMP16m = 1660 + + FARJMP32i = 1661 + + FARJMP32m = 1662 + + FARJMP64m = 1663 + + FBLDm = 1664 + + FBSTPm = 1665 + + FCOM32m = 1666 + + FCOM64m = 1667 + + FCOMP32m = 1668 + + FCOMP64m = 1669 + + FCOMPP = 1670 + + FCOS = 1671 + + FDECSTP = 1672 + + FEMMS = 1673 + + FFREE = 1674 + + FFREEP = 1675 + + FICOM16m = 1676 + + FICOM32m = 1677 + + FICOMP16m = 1678 + + FICOMP32m = 1679 + + FINCSTP = 1680 + + FLDCW16m = 1681 + + FLDENVm = 1682 + + FLDL2E = 1683 + + FLDL2T = 1684 + + FLDLG2 = 1685 + + FLDLN2 = 1686 + + FLDPI = 1687 + + FNCLEX = 1688 + + FNINIT = 1689 + + FNOP = 1690 + + FNSTCW16m = 1691 + + FNSTSW16r = 1692 + + FNSTSWm = 1693 + + FP32_TO_INT16_IN_MEM = 1694 + + FP32_TO_INT32_IN_MEM = 1695 + + FP32_TO_INT64_IN_MEM = 1696 + + FP64_TO_INT16_IN_MEM = 1697 + + FP64_TO_INT32_IN_MEM = 1698 + + FP64_TO_INT64_IN_MEM = 1699 + + FP80_ADDm32 = 1700 + + FP80_ADDr = 1701 + + FP80_TO_INT16_IN_MEM = 1702 + + FP80_TO_INT32_IN_MEM = 1703 + + FP80_TO_INT64_IN_MEM = 1704 + + FPATAN = 1705 + + FPREM = 1706 + + FPREM1 = 1707 + + FPTAN = 1708 + + FRNDINT = 1709 + + FRSTORm = 1710 + + FSAVEm = 1711 + + FSCALE_ = 1712 + + FSIN = 1713 + + FSINCOS = 1714 + + FSTENVm = 1715 + + FS_PREFIX = 1716 + + FXRSTOR = 1717 + + FXRSTOR64 = 1718 + + FXSAVE = 1719 + + FXSAVE64 = 1720 + + FXTRACT = 1721 + + FYL2X = 1722 + + FYL2XP1 = 1723 + + GETSEC = 1724 + + GF2P8AFFINEINVQBrmi = 1725 + + GF2P8AFFINEINVQBrri = 1726 + + GF2P8AFFINEQBrmi = 1727 + + GF2P8AFFINEQBrri = 1728 + + GF2P8MULBrm = 1729 + + GF2P8MULBrr = 1730 + + GS_PREFIX = 1731 + + HADDPDrm = 1732 + + HADDPDrr = 1733 + + HADDPSrm = 1734 + + HADDPSrr = 1735 + + HLT = 1736 + + HRESET = 1737 + + HSUBPDrm = 1738 + + HSUBPDrr = 1739 + + HSUBPSrm = 1740 + + HSUBPSrr = 1741 + + IDIV16m = 1742 + + IDIV16m_EVEX = 1743 + + IDIV16m_NF = 1744 + + IDIV16r = 1745 + + IDIV16r_EVEX = 1746 + + IDIV16r_NF = 1747 + + IDIV32m = 1748 + + IDIV32m_EVEX = 1749 + + IDIV32m_NF = 1750 + + IDIV32r = 1751 + + IDIV32r_EVEX = 1752 + + IDIV32r_NF = 1753 + + IDIV64m = 1754 + + IDIV64m_EVEX = 1755 + + IDIV64m_NF = 1756 + + IDIV64r = 1757 + + IDIV64r_EVEX = 1758 + + IDIV64r_NF = 1759 + + IDIV8m = 1760 + + IDIV8m_EVEX = 1761 + + IDIV8m_NF = 1762 + + IDIV8r = 1763 + + IDIV8r_EVEX = 1764 + + IDIV8r_NF = 1765 + + ILD_F16m = 1766 + + ILD_F32m = 1767 + + ILD_F64m = 1768 + + ILD_Fp16m32 = 1769 + + ILD_Fp16m64 = 1770 + + ILD_Fp16m80 = 1771 + + ILD_Fp32m32 = 1772 + + ILD_Fp32m64 = 1773 + + ILD_Fp32m80 = 1774 + + ILD_Fp64m32 = 1775 + + ILD_Fp64m64 = 1776 + + ILD_Fp64m80 = 1777 + + IMUL16m = 1778 + + IMUL16m_EVEX = 1779 + + IMUL16m_NF = 1780 + + IMUL16r = 1781 + + IMUL16r_EVEX = 1782 + + IMUL16r_NF = 1783 + + IMUL16rm = 1784 + + IMUL16rm_EVEX = 1785 + + IMUL16rm_ND = 1786 + + IMUL16rm_NF = 1787 + + IMUL16rm_NF_ND = 1788 + + IMUL16rmi = 1789 + + IMUL16rmi8 = 1790 + + IMUL16rmi8_EVEX = 1791 + + IMUL16rmi8_NF = 1792 + + IMUL16rmi_EVEX = 1793 + + IMUL16rmi_NF = 1794 + + IMUL16rr = 1795 + + IMUL16rr_EVEX = 1796 + + IMUL16rr_ND = 1797 + + IMUL16rr_NF = 1798 + + IMUL16rr_NF_ND = 1799 + + IMUL16rri = 1800 + + IMUL16rri8 = 1801 + + IMUL16rri8_EVEX = 1802 + + IMUL16rri8_NF = 1803 + + IMUL16rri_EVEX = 1804 + + IMUL16rri_NF = 1805 + + IMUL32m = 1806 + + IMUL32m_EVEX = 1807 + + IMUL32m_NF = 1808 + + IMUL32r = 1809 + + IMUL32r_EVEX = 1810 + + IMUL32r_NF = 1811 + + IMUL32rm = 1812 + + IMUL32rm_EVEX = 1813 + + IMUL32rm_ND = 1814 + + IMUL32rm_NF = 1815 + + IMUL32rm_NF_ND = 1816 + + IMUL32rmi = 1817 + + IMUL32rmi8 = 1818 + + IMUL32rmi8_EVEX = 1819 + + IMUL32rmi8_NF = 1820 + + IMUL32rmi_EVEX = 1821 + + IMUL32rmi_NF = 1822 + + IMUL32rr = 1823 + + IMUL32rr_EVEX = 1824 + + IMUL32rr_ND = 1825 + + IMUL32rr_NF = 1826 + + IMUL32rr_NF_ND = 1827 + + IMUL32rri = 1828 + + IMUL32rri8 = 1829 + + IMUL32rri8_EVEX = 1830 + + IMUL32rri8_NF = 1831 + + IMUL32rri_EVEX = 1832 + + IMUL32rri_NF = 1833 + + IMUL64m = 1834 + + IMUL64m_EVEX = 1835 + + IMUL64m_NF = 1836 + + IMUL64r = 1837 + + IMUL64r_EVEX = 1838 + + IMUL64r_NF = 1839 + + IMUL64rm = 1840 + + IMUL64rm_EVEX = 1841 + + IMUL64rm_ND = 1842 + + IMUL64rm_NF = 1843 + + IMUL64rm_NF_ND = 1844 + + IMUL64rmi32 = 1845 + + IMUL64rmi32_EVEX = 1846 + + IMUL64rmi32_NF = 1847 + + IMUL64rmi8 = 1848 + + IMUL64rmi8_EVEX = 1849 + + IMUL64rmi8_NF = 1850 + + IMUL64rr = 1851 + + IMUL64rr_EVEX = 1852 + + IMUL64rr_ND = 1853 + + IMUL64rr_NF = 1854 + + IMUL64rr_NF_ND = 1855 + + IMUL64rri32 = 1856 + + IMUL64rri32_EVEX = 1857 + + IMUL64rri32_NF = 1858 + + IMUL64rri8 = 1859 + + IMUL64rri8_EVEX = 1860 + + IMUL64rri8_NF = 1861 + + IMUL8m = 1862 + + IMUL8m_EVEX = 1863 + + IMUL8m_NF = 1864 + + IMUL8r = 1865 + + IMUL8r_EVEX = 1866 + + IMUL8r_NF = 1867 + + IMULZU16rmi = 1868 + + IMULZU16rmi8 = 1869 + + IMULZU16rri = 1870 + + IMULZU16rri8 = 1871 + + IMULZU32rmi = 1872 + + IMULZU32rmi8 = 1873 + + IMULZU32rri = 1874 + + IMULZU32rri8 = 1875 + + IMULZU64rmi32 = 1876 + + IMULZU64rmi8 = 1877 + + IMULZU64rri32 = 1878 + + IMULZU64rri8 = 1879 + + IN16ri = 1880 + + IN16rr = 1881 + + IN32ri = 1882 + + IN32rr = 1883 + + IN8ri = 1884 + + IN8rr = 1885 + + INC16m = 1886 + + INC16m_EVEX = 1887 + + INC16m_ND = 1888 + + INC16m_NF = 1889 + + INC16m_NF_ND = 1890 + + INC16r = 1891 + + INC16r_EVEX = 1892 + + INC16r_ND = 1893 + + INC16r_NF = 1894 + + INC16r_NF_ND = 1895 + + INC16r_alt = 1896 + + INC32m = 1897 + + INC32m_EVEX = 1898 + + INC32m_ND = 1899 + + INC32m_NF = 1900 + + INC32m_NF_ND = 1901 + + INC32r = 1902 + + INC32r_EVEX = 1903 + + INC32r_ND = 1904 + + INC32r_NF = 1905 + + INC32r_NF_ND = 1906 + + INC32r_alt = 1907 + + INC64m = 1908 + + INC64m_EVEX = 1909 + + INC64m_ND = 1910 + + INC64m_NF = 1911 + + INC64m_NF_ND = 1912 + + INC64r = 1913 + + INC64r_EVEX = 1914 + + INC64r_ND = 1915 + + INC64r_NF = 1916 + + INC64r_NF_ND = 1917 + + INC8m = 1918 + + INC8m_EVEX = 1919 + + INC8m_ND = 1920 + + INC8m_NF = 1921 + + INC8m_NF_ND = 1922 + + INC8r = 1923 + + INC8r_EVEX = 1924 + + INC8r_ND = 1925 + + INC8r_NF = 1926 + + INC8r_NF_ND = 1927 + + INCSSPD = 1928 + + INCSSPQ = 1929 + + INSB = 1930 + + INSERTPSrmi = 1931 + + INSERTPSrri = 1932 + + INSERTQ = 1933 + + INSERTQI = 1934 + + INSL = 1935 + + INSW = 1936 + + INT = 1937 + + INT3 = 1938 + + INTO = 1939 + + INVD = 1940 + + INVEPT32 = 1941 + + INVEPT64 = 1942 + + INVEPT64_EVEX = 1943 + + INVLPG = 1944 + + INVLPGA32 = 1945 + + INVLPGA64 = 1946 + + INVLPGB32 = 1947 + + INVLPGB64 = 1948 + + INVPCID32 = 1949 + + INVPCID64 = 1950 + + INVPCID64_EVEX = 1951 + + INVVPID32 = 1952 + + INVVPID64 = 1953 + + INVVPID64_EVEX = 1954 + + IRET = 1955 + + IRET16 = 1956 + + IRET32 = 1957 + + IRET64 = 1958 + + ISTT_FP16m = 1959 + + ISTT_FP32m = 1960 + + ISTT_FP64m = 1961 + + ISTT_Fp16m32 = 1962 + + ISTT_Fp16m64 = 1963 + + ISTT_Fp16m80 = 1964 + + ISTT_Fp32m32 = 1965 + + ISTT_Fp32m64 = 1966 + + ISTT_Fp32m80 = 1967 + + ISTT_Fp64m32 = 1968 + + ISTT_Fp64m64 = 1969 + + ISTT_Fp64m80 = 1970 + + IST_F16m = 1971 + + IST_F32m = 1972 + + IST_FP16m = 1973 + + IST_FP32m = 1974 + + IST_FP64m = 1975 + + IST_Fp16m32 = 1976 + + IST_Fp16m64 = 1977 + + IST_Fp16m80 = 1978 + + IST_Fp32m32 = 1979 + + IST_Fp32m64 = 1980 + + IST_Fp32m80 = 1981 + + IST_Fp64m32 = 1982 + + IST_Fp64m64 = 1983 + + IST_Fp64m80 = 1984 + + Int_eh_sjlj_setup_dispatch = 1985 + + JCC_1 = 1986 + + JCC_2 = 1987 + + JCC_4 = 1988 + + JCXZ = 1989 + + JECXZ = 1990 + + JMP16m = 1991 + + JMP16m_NT = 1992 + + JMP16r = 1993 + + JMP16r_NT = 1994 + + JMP32m = 1995 + + JMP32m_NT = 1996 + + JMP32r = 1997 + + JMP32r_NT = 1998 + + JMP64m = 1999 + + JMP64m_NT = 2000 + + JMP64m_REX = 2001 + + JMP64r = 2002 + + JMP64r_NT = 2003 + + JMP64r_REX = 2004 + + JMPABS64i = 2005 + + JMP_1 = 2006 + + JMP_2 = 2007 + + JMP_4 = 2008 + + JRCXZ = 2009 + + KADDBkk = 2010 + + KADDDkk = 2011 + + KADDQkk = 2012 + + KADDWkk = 2013 + + KANDBkk = 2014 + + KANDDkk = 2015 + + KANDNBkk = 2016 + + KANDNDkk = 2017 + + KANDNQkk = 2018 + + KANDNWkk = 2019 + + KANDQkk = 2020 + + KANDWkk = 2021 + + KCFI_CHECK = 2022 + + KMOVBkk = 2023 + + KMOVBkk_EVEX = 2024 + + KMOVBkm = 2025 + + KMOVBkm_EVEX = 2026 + + KMOVBkr = 2027 + + KMOVBkr_EVEX = 2028 + + KMOVBmk = 2029 + + KMOVBmk_EVEX = 2030 + + KMOVBrk = 2031 + + KMOVBrk_EVEX = 2032 + + KMOVDkk = 2033 + + KMOVDkk_EVEX = 2034 + + KMOVDkm = 2035 + + KMOVDkm_EVEX = 2036 + + KMOVDkr = 2037 + + KMOVDkr_EVEX = 2038 + + KMOVDmk = 2039 + + KMOVDmk_EVEX = 2040 + + KMOVDrk = 2041 + + KMOVDrk_EVEX = 2042 + + KMOVQkk = 2043 + + KMOVQkk_EVEX = 2044 + + KMOVQkm = 2045 + + KMOVQkm_EVEX = 2046 + + KMOVQkr = 2047 + + KMOVQkr_EVEX = 2048 + + KMOVQmk = 2049 + + KMOVQmk_EVEX = 2050 + + KMOVQrk = 2051 + + KMOVQrk_EVEX = 2052 + + KMOVWkk = 2053 + + KMOVWkk_EVEX = 2054 + + KMOVWkm = 2055 + + KMOVWkm_EVEX = 2056 + + KMOVWkr = 2057 + + KMOVWkr_EVEX = 2058 + + KMOVWmk = 2059 + + KMOVWmk_EVEX = 2060 + + KMOVWrk = 2061 + + KMOVWrk_EVEX = 2062 + + KNOTBkk = 2063 + + KNOTDkk = 2064 + + KNOTQkk = 2065 + + KNOTWkk = 2066 + + KORBkk = 2067 + + KORDkk = 2068 + + KORQkk = 2069 + + KORTESTBkk = 2070 + + KORTESTDkk = 2071 + + KORTESTQkk = 2072 + + KORTESTWkk = 2073 + + KORWkk = 2074 + + KSHIFTLBki = 2075 + + KSHIFTLDki = 2076 + + KSHIFTLQki = 2077 + + KSHIFTLWki = 2078 + + KSHIFTRBki = 2079 + + KSHIFTRDki = 2080 + + KSHIFTRQki = 2081 + + KSHIFTRWki = 2082 + + KTESTBkk = 2083 + + KTESTDkk = 2084 + + KTESTQkk = 2085 + + KTESTWkk = 2086 + + KUNPCKBWkk = 2087 + + KUNPCKDQkk = 2088 + + KUNPCKWDkk = 2089 + + KXNORBkk = 2090 + + KXNORDkk = 2091 + + KXNORQkk = 2092 + + KXNORWkk = 2093 + + KXORBkk = 2094 + + KXORDkk = 2095 + + KXORQkk = 2096 + + KXORWkk = 2097 + + LAHF = 2098 + + LAR16rm = 2099 + + LAR16rr = 2100 + + LAR32rm = 2101 + + LAR32rr = 2102 + + LAR64rm = 2103 + + LAR64rr = 2104 + + LCMPXCHG16 = 2105 + + LCMPXCHG16B = 2106 + + LCMPXCHG32 = 2107 + + LCMPXCHG64 = 2108 + + LCMPXCHG8 = 2109 + + LCMPXCHG8B = 2110 + + LDDQUrm = 2111 + + LDMXCSR = 2112 + + LDS16rm = 2113 + + LDS32rm = 2114 + + LDTILECFG = 2115 + + LDTILECFG_EVEX = 2116 + + LD_F0 = 2117 + + LD_F1 = 2118 + + LD_F32m = 2119 + + LD_F64m = 2120 + + LD_F80m = 2121 + + LD_Fp032 = 2122 + + LD_Fp064 = 2123 + + LD_Fp080 = 2124 + + LD_Fp132 = 2125 + + LD_Fp164 = 2126 + + LD_Fp180 = 2127 + + LD_Fp32m = 2128 + + LD_Fp32m64 = 2129 + + LD_Fp32m80 = 2130 + + LD_Fp64m = 2131 + + LD_Fp64m80 = 2132 + + LD_Fp80m = 2133 + + LD_Frr = 2134 + + LEA16r = 2135 + + LEA32r = 2136 + + LEA64_16r = 2137 + + LEA64_32r = 2138 + + LEA64_8r = 2139 + + LEA64r = 2140 + + LEAVE = 2141 + + LEAVE64 = 2142 + + LES16rm = 2143 + + LES32rm = 2144 + + LFENCE = 2145 + + LFS16rm = 2146 + + LFS32rm = 2147 + + LFS64rm = 2148 + + LGDT16m = 2149 + + LGDT32m = 2150 + + LGDT64m = 2151 + + LGS16rm = 2152 + + LGS32rm = 2153 + + LGS64rm = 2154 + + LIDT16m = 2155 + + LIDT32m = 2156 + + LIDT64m = 2157 + + LKGS16m = 2158 + + LKGS16r = 2159 + + LLDT16m = 2160 + + LLDT16r = 2161 + + LLWPCB = 2162 + + LLWPCB64 = 2163 + + LMSW16m = 2164 + + LMSW16r = 2165 + + LOADIWKEY = 2166 + + LOCK_ADD16mi = 2167 + + LOCK_ADD16mi8 = 2168 + + LOCK_ADD16mr = 2169 + + LOCK_ADD32mi = 2170 + + LOCK_ADD32mi8 = 2171 + + LOCK_ADD32mr = 2172 + + LOCK_ADD64mi32 = 2173 + + LOCK_ADD64mi8 = 2174 + + LOCK_ADD64mr = 2175 + + LOCK_ADD8mi = 2176 + + LOCK_ADD8mr = 2177 + + LOCK_AND16mi = 2178 + + LOCK_AND16mi8 = 2179 + + LOCK_AND16mr = 2180 + + LOCK_AND32mi = 2181 + + LOCK_AND32mi8 = 2182 + + LOCK_AND32mr = 2183 + + LOCK_AND64mi32 = 2184 + + LOCK_AND64mi8 = 2185 + + LOCK_AND64mr = 2186 + + LOCK_AND8mi = 2187 + + LOCK_AND8mr = 2188 + + LOCK_BTC16m = 2189 + + LOCK_BTC32m = 2190 + + LOCK_BTC64m = 2191 + + LOCK_BTC_RM16rm = 2192 + + LOCK_BTC_RM32rm = 2193 + + LOCK_BTC_RM64rm = 2194 + + LOCK_BTR16m = 2195 + + LOCK_BTR32m = 2196 + + LOCK_BTR64m = 2197 + + LOCK_BTR_RM16rm = 2198 + + LOCK_BTR_RM32rm = 2199 + + LOCK_BTR_RM64rm = 2200 + + LOCK_BTS16m = 2201 + + LOCK_BTS32m = 2202 + + LOCK_BTS64m = 2203 + + LOCK_BTS_RM16rm = 2204 + + LOCK_BTS_RM32rm = 2205 + + LOCK_BTS_RM64rm = 2206 + + LOCK_DEC16m = 2207 + + LOCK_DEC32m = 2208 + + LOCK_DEC64m = 2209 + + LOCK_DEC8m = 2210 + + LOCK_INC16m = 2211 + + LOCK_INC32m = 2212 + + LOCK_INC64m = 2213 + + LOCK_INC8m = 2214 + + LOCK_OR16mi = 2215 + + LOCK_OR16mi8 = 2216 + + LOCK_OR16mr = 2217 + + LOCK_OR32mi = 2218 + + LOCK_OR32mi8 = 2219 + + LOCK_OR32mr = 2220 + + LOCK_OR64mi32 = 2221 + + LOCK_OR64mi8 = 2222 + + LOCK_OR64mr = 2223 + + LOCK_OR8mi = 2224 + + LOCK_OR8mr = 2225 + + LOCK_PREFIX = 2226 + + LOCK_SUB16mi = 2227 + + LOCK_SUB16mi8 = 2228 + + LOCK_SUB16mr = 2229 + + LOCK_SUB32mi = 2230 + + LOCK_SUB32mi8 = 2231 + + LOCK_SUB32mr = 2232 + + LOCK_SUB64mi32 = 2233 + + LOCK_SUB64mi8 = 2234 + + LOCK_SUB64mr = 2235 + + LOCK_SUB8mi = 2236 + + LOCK_SUB8mr = 2237 + + LOCK_XOR16mi = 2238 + + LOCK_XOR16mi8 = 2239 + + LOCK_XOR16mr = 2240 + + LOCK_XOR32mi = 2241 + + LOCK_XOR32mi8 = 2242 + + LOCK_XOR32mr = 2243 + + LOCK_XOR64mi32 = 2244 + + LOCK_XOR64mi8 = 2245 + + LOCK_XOR64mr = 2246 + + LOCK_XOR8mi = 2247 + + LOCK_XOR8mr = 2248 + + LODSB = 2249 + + LODSL = 2250 + + LODSQ = 2251 + + LODSW = 2252 + + LOOP = 2253 + + LOOPE = 2254 + + LOOPNE = 2255 + + LRET16 = 2256 + + LRET32 = 2257 + + LRET64 = 2258 + + LRETI16 = 2259 + + LRETI32 = 2260 + + LRETI64 = 2261 + + LSL16rm = 2262 + + LSL16rr = 2263 + + LSL32rm = 2264 + + LSL32rr = 2265 + + LSL64rm = 2266 + + LSL64rr = 2267 + + LSS16rm = 2268 + + LSS32rm = 2269 + + LSS64rm = 2270 + + LTRm = 2271 + + LTRr = 2272 + + LWPINS32rmi = 2273 + + LWPINS32rri = 2274 + + LWPINS64rmi = 2275 + + LWPINS64rri = 2276 + + LWPVAL32rmi = 2277 + + LWPVAL32rri = 2278 + + LWPVAL64rmi = 2279 + + LWPVAL64rri = 2280 + + LXADD16 = 2281 + + LXADD32 = 2282 + + LXADD64 = 2283 + + LXADD8 = 2284 + + LZCNT16rm = 2285 + + LZCNT16rm_EVEX = 2286 + + LZCNT16rm_NF = 2287 + + LZCNT16rr = 2288 + + LZCNT16rr_EVEX = 2289 + + LZCNT16rr_NF = 2290 + + LZCNT32rm = 2291 + + LZCNT32rm_EVEX = 2292 + + LZCNT32rm_NF = 2293 + + LZCNT32rr = 2294 + + LZCNT32rr_EVEX = 2295 + + LZCNT32rr_NF = 2296 + + LZCNT64rm = 2297 + + LZCNT64rm_EVEX = 2298 + + LZCNT64rm_NF = 2299 + + LZCNT64rr = 2300 + + LZCNT64rr_EVEX = 2301 + + LZCNT64rr_NF = 2302 + + MASKMOVDQU = 2303 + + MASKMOVDQU64 = 2304 + + MASKPAIR16LOAD = 2305 + + MASKPAIR16STORE = 2306 + + MAXCPDrm = 2307 + + MAXCPDrr = 2308 + + MAXCPSrm = 2309 + + MAXCPSrr = 2310 + + MAXCSDrm = 2311 + + MAXCSDrr = 2312 + + MAXCSSrm = 2313 + + MAXCSSrr = 2314 + + MAXPDrm = 2315 + + MAXPDrr = 2316 + + MAXPSrm = 2317 + + MAXPSrr = 2318 + + MAXSDrm = 2319 + + MAXSDrm_Int = 2320 + + MAXSDrr = 2321 + + MAXSDrr_Int = 2322 + + MAXSSrm = 2323 + + MAXSSrm_Int = 2324 + + MAXSSrr = 2325 + + MAXSSrr_Int = 2326 + + MFENCE = 2327 + + MINCPDrm = 2328 + + MINCPDrr = 2329 + + MINCPSrm = 2330 + + MINCPSrr = 2331 + + MINCSDrm = 2332 + + MINCSDrr = 2333 + + MINCSSrm = 2334 + + MINCSSrr = 2335 + + MINPDrm = 2336 + + MINPDrr = 2337 + + MINPSrm = 2338 + + MINPSrr = 2339 + + MINSDrm = 2340 + + MINSDrm_Int = 2341 + + MINSDrr = 2342 + + MINSDrr_Int = 2343 + + MINSSrm = 2344 + + MINSSrm_Int = 2345 + + MINSSrr = 2346 + + MINSSrr_Int = 2347 + + MMX_CVTPD2PIrm = 2348 + + MMX_CVTPD2PIrr = 2349 + + MMX_CVTPI2PDrm = 2350 + + MMX_CVTPI2PDrr = 2351 + + MMX_CVTPI2PSrm = 2352 + + MMX_CVTPI2PSrr = 2353 + + MMX_CVTPS2PIrm = 2354 + + MMX_CVTPS2PIrr = 2355 + + MMX_CVTTPD2PIrm = 2356 + + MMX_CVTTPD2PIrr = 2357 + + MMX_CVTTPS2PIrm = 2358 + + MMX_CVTTPS2PIrr = 2359 + + MMX_EMMS = 2360 + + MMX_MASKMOVQ = 2361 + + MMX_MASKMOVQ64 = 2362 + + MMX_MOVD64from64mr = 2363 + + MMX_MOVD64from64rr = 2364 + + MMX_MOVD64grr = 2365 + + MMX_MOVD64mr = 2366 + + MMX_MOVD64rm = 2367 + + MMX_MOVD64rr = 2368 + + MMX_MOVD64to64rm = 2369 + + MMX_MOVD64to64rr = 2370 + + MMX_MOVDQ2Qrr = 2371 + + MMX_MOVFR642Qrr = 2372 + + MMX_MOVNTQmr = 2373 + + MMX_MOVQ2DQrr = 2374 + + MMX_MOVQ2FR64rr = 2375 + + MMX_MOVQ64mr = 2376 + + MMX_MOVQ64rm = 2377 + + MMX_MOVQ64rr = 2378 + + MMX_MOVQ64rr_REV = 2379 + + MMX_PABSBrm = 2380 + + MMX_PABSBrr = 2381 + + MMX_PABSDrm = 2382 + + MMX_PABSDrr = 2383 + + MMX_PABSWrm = 2384 + + MMX_PABSWrr = 2385 + + MMX_PACKSSDWrm = 2386 + + MMX_PACKSSDWrr = 2387 + + MMX_PACKSSWBrm = 2388 + + MMX_PACKSSWBrr = 2389 + + MMX_PACKUSWBrm = 2390 + + MMX_PACKUSWBrr = 2391 + + MMX_PADDBrm = 2392 + + MMX_PADDBrr = 2393 + + MMX_PADDDrm = 2394 + + MMX_PADDDrr = 2395 + + MMX_PADDQrm = 2396 + + MMX_PADDQrr = 2397 + + MMX_PADDSBrm = 2398 + + MMX_PADDSBrr = 2399 + + MMX_PADDSWrm = 2400 + + MMX_PADDSWrr = 2401 + + MMX_PADDUSBrm = 2402 + + MMX_PADDUSBrr = 2403 + + MMX_PADDUSWrm = 2404 + + MMX_PADDUSWrr = 2405 + + MMX_PADDWrm = 2406 + + MMX_PADDWrr = 2407 + + MMX_PALIGNRrmi = 2408 + + MMX_PALIGNRrri = 2409 + + MMX_PANDNrm = 2410 + + MMX_PANDNrr = 2411 + + MMX_PANDrm = 2412 + + MMX_PANDrr = 2413 + + MMX_PAVGBrm = 2414 + + MMX_PAVGBrr = 2415 + + MMX_PAVGWrm = 2416 + + MMX_PAVGWrr = 2417 + + MMX_PCMPEQBrm = 2418 + + MMX_PCMPEQBrr = 2419 + + MMX_PCMPEQDrm = 2420 + + MMX_PCMPEQDrr = 2421 + + MMX_PCMPEQWrm = 2422 + + MMX_PCMPEQWrr = 2423 + + MMX_PCMPGTBrm = 2424 + + MMX_PCMPGTBrr = 2425 + + MMX_PCMPGTDrm = 2426 + + MMX_PCMPGTDrr = 2427 + + MMX_PCMPGTWrm = 2428 + + MMX_PCMPGTWrr = 2429 + + MMX_PEXTRWrri = 2430 + + MMX_PHADDDrm = 2431 + + MMX_PHADDDrr = 2432 + + MMX_PHADDSWrm = 2433 + + MMX_PHADDSWrr = 2434 + + MMX_PHADDWrm = 2435 + + MMX_PHADDWrr = 2436 + + MMX_PHSUBDrm = 2437 + + MMX_PHSUBDrr = 2438 + + MMX_PHSUBSWrm = 2439 + + MMX_PHSUBSWrr = 2440 + + MMX_PHSUBWrm = 2441 + + MMX_PHSUBWrr = 2442 + + MMX_PINSRWrmi = 2443 + + MMX_PINSRWrri = 2444 + + MMX_PMADDUBSWrm = 2445 + + MMX_PMADDUBSWrr = 2446 + + MMX_PMADDWDrm = 2447 + + MMX_PMADDWDrr = 2448 + + MMX_PMAXSWrm = 2449 + + MMX_PMAXSWrr = 2450 + + MMX_PMAXUBrm = 2451 + + MMX_PMAXUBrr = 2452 + + MMX_PMINSWrm = 2453 + + MMX_PMINSWrr = 2454 + + MMX_PMINUBrm = 2455 + + MMX_PMINUBrr = 2456 + + MMX_PMOVMSKBrr = 2457 + + MMX_PMULHRSWrm = 2458 + + MMX_PMULHRSWrr = 2459 + + MMX_PMULHUWrm = 2460 + + MMX_PMULHUWrr = 2461 + + MMX_PMULHWrm = 2462 + + MMX_PMULHWrr = 2463 + + MMX_PMULLWrm = 2464 + + MMX_PMULLWrr = 2465 + + MMX_PMULUDQrm = 2466 + + MMX_PMULUDQrr = 2467 + + MMX_PORrm = 2468 + + MMX_PORrr = 2469 + + MMX_PSADBWrm = 2470 + + MMX_PSADBWrr = 2471 + + MMX_PSHUFBrm = 2472 + + MMX_PSHUFBrr = 2473 + + MMX_PSHUFWmi = 2474 + + MMX_PSHUFWri = 2475 + + MMX_PSIGNBrm = 2476 + + MMX_PSIGNBrr = 2477 + + MMX_PSIGNDrm = 2478 + + MMX_PSIGNDrr = 2479 + + MMX_PSIGNWrm = 2480 + + MMX_PSIGNWrr = 2481 + + MMX_PSLLDri = 2482 + + MMX_PSLLDrm = 2483 + + MMX_PSLLDrr = 2484 + + MMX_PSLLQri = 2485 + + MMX_PSLLQrm = 2486 + + MMX_PSLLQrr = 2487 + + MMX_PSLLWri = 2488 + + MMX_PSLLWrm = 2489 + + MMX_PSLLWrr = 2490 + + MMX_PSRADri = 2491 + + MMX_PSRADrm = 2492 + + MMX_PSRADrr = 2493 + + MMX_PSRAWri = 2494 + + MMX_PSRAWrm = 2495 + + MMX_PSRAWrr = 2496 + + MMX_PSRLDri = 2497 + + MMX_PSRLDrm = 2498 + + MMX_PSRLDrr = 2499 + + MMX_PSRLQri = 2500 + + MMX_PSRLQrm = 2501 + + MMX_PSRLQrr = 2502 + + MMX_PSRLWri = 2503 + + MMX_PSRLWrm = 2504 + + MMX_PSRLWrr = 2505 + + MMX_PSUBBrm = 2506 + + MMX_PSUBBrr = 2507 + + MMX_PSUBDrm = 2508 + + MMX_PSUBDrr = 2509 + + MMX_PSUBQrm = 2510 + + MMX_PSUBQrr = 2511 + + MMX_PSUBSBrm = 2512 + + MMX_PSUBSBrr = 2513 + + MMX_PSUBSWrm = 2514 + + MMX_PSUBSWrr = 2515 + + MMX_PSUBUSBrm = 2516 + + MMX_PSUBUSBrr = 2517 + + MMX_PSUBUSWrm = 2518 + + MMX_PSUBUSWrr = 2519 + + MMX_PSUBWrm = 2520 + + MMX_PSUBWrr = 2521 + + MMX_PUNPCKHBWrm = 2522 + + MMX_PUNPCKHBWrr = 2523 + + MMX_PUNPCKHDQrm = 2524 + + MMX_PUNPCKHDQrr = 2525 + + MMX_PUNPCKHWDrm = 2526 + + MMX_PUNPCKHWDrr = 2527 + + MMX_PUNPCKLBWrm = 2528 + + MMX_PUNPCKLBWrr = 2529 + + MMX_PUNPCKLDQrm = 2530 + + MMX_PUNPCKLDQrr = 2531 + + MMX_PUNPCKLWDrm = 2532 + + MMX_PUNPCKLWDrr = 2533 + + MMX_PXORrm = 2534 + + MMX_PXORrr = 2535 + + MONITOR32rrr = 2536 + + MONITOR64rrr = 2537 + + MONITORX32rrr = 2538 + + MONITORX64rrr = 2539 + + MONTMUL = 2540 + + MOV16ao16 = 2541 + + MOV16ao32 = 2542 + + MOV16ao64 = 2543 + + MOV16mi = 2544 + + MOV16mr = 2545 + + MOV16ms = 2546 + + MOV16o16a = 2547 + + MOV16o32a = 2548 + + MOV16o64a = 2549 + + MOV16ri = 2550 + + MOV16ri_alt = 2551 + + MOV16rm = 2552 + + MOV16rr = 2553 + + MOV16rr_REV = 2554 + + MOV16rs = 2555 + + MOV16sm = 2556 + + MOV16sr = 2557 + + MOV32ao16 = 2558 + + MOV32ao32 = 2559 + + MOV32ao64 = 2560 + + MOV32cr = 2561 + + MOV32dr = 2562 + + MOV32mi = 2563 + + MOV32mr = 2564 + + MOV32o16a = 2565 + + MOV32o32a = 2566 + + MOV32o64a = 2567 + + MOV32rc = 2568 + + MOV32rd = 2569 + + MOV32ri = 2570 + + MOV32ri_alt = 2571 + + MOV32rm = 2572 + + MOV32rr = 2573 + + MOV32rr_REV = 2574 + + MOV32rs = 2575 + + MOV32sr = 2576 + + MOV64ao32 = 2577 + + MOV64ao64 = 2578 + + MOV64cr = 2579 + + MOV64dr = 2580 + + MOV64mi32 = 2581 + + MOV64mr = 2582 + + MOV64o32a = 2583 + + MOV64o64a = 2584 + + MOV64rc = 2585 + + MOV64rd = 2586 + + MOV64ri = 2587 + + MOV64ri32 = 2588 + + MOV64rm = 2589 + + MOV64rr = 2590 + + MOV64rr_REV = 2591 + + MOV64rs = 2592 + + MOV64sr = 2593 + + MOV64toPQIrm = 2594 + + MOV64toPQIrr = 2595 + + MOV64toSDrr = 2596 + + MOV8ao16 = 2597 + + MOV8ao32 = 2598 + + MOV8ao64 = 2599 + + MOV8mi = 2600 + + MOV8mr = 2601 + + MOV8mr_NOREX = 2602 + + MOV8o16a = 2603 + + MOV8o32a = 2604 + + MOV8o64a = 2605 + + MOV8ri = 2606 + + MOV8ri_alt = 2607 + + MOV8rm = 2608 + + MOV8rm_NOREX = 2609 + + MOV8rr = 2610 + + MOV8rr_NOREX = 2611 + + MOV8rr_REV = 2612 + + MOVAPDmr = 2613 + + MOVAPDrm = 2614 + + MOVAPDrr = 2615 + + MOVAPDrr_REV = 2616 + + MOVAPSmr = 2617 + + MOVAPSrm = 2618 + + MOVAPSrr = 2619 + + MOVAPSrr_REV = 2620 + + MOVBE16mr = 2621 + + MOVBE16mr_EVEX = 2622 + + MOVBE16rm = 2623 + + MOVBE16rm_EVEX = 2624 + + MOVBE16rr = 2625 + + MOVBE16rr_REV = 2626 + + MOVBE32mr = 2627 + + MOVBE32mr_EVEX = 2628 + + MOVBE32rm = 2629 + + MOVBE32rm_EVEX = 2630 + + MOVBE32rr = 2631 + + MOVBE32rr_REV = 2632 + + MOVBE64mr = 2633 + + MOVBE64mr_EVEX = 2634 + + MOVBE64rm = 2635 + + MOVBE64rm_EVEX = 2636 + + MOVBE64rr = 2637 + + MOVBE64rr_REV = 2638 + + MOVDDUPrm = 2639 + + MOVDDUPrr = 2640 + + MOVDI2PDIrm = 2641 + + MOVDI2PDIrr = 2642 + + MOVDI2SSrr = 2643 + + MOVDIR64B16 = 2644 + + MOVDIR64B32 = 2645 + + MOVDIR64B32_EVEX = 2646 + + MOVDIR64B64 = 2647 + + MOVDIR64B64_EVEX = 2648 + + MOVDIRI32 = 2649 + + MOVDIRI32_EVEX = 2650 + + MOVDIRI64 = 2651 + + MOVDIRI64_EVEX = 2652 + + MOVDQAmr = 2653 + + MOVDQArm = 2654 + + MOVDQArr = 2655 + + MOVDQArr_REV = 2656 + + MOVDQUmr = 2657 + + MOVDQUrm = 2658 + + MOVDQUrr = 2659 + + MOVDQUrr_REV = 2660 + + MOVHLPSrr = 2661 + + MOVHPDmr = 2662 + + MOVHPDrm = 2663 + + MOVHPSmr = 2664 + + MOVHPSrm = 2665 + + MOVLHPSrr = 2666 + + MOVLPDmr = 2667 + + MOVLPDrm = 2668 + + MOVLPSmr = 2669 + + MOVLPSrm = 2670 + + MOVMSKPDrr = 2671 + + MOVMSKPSrr = 2672 + + MOVNTDQArm = 2673 + + MOVNTDQmr = 2674 + + MOVNTI_64mr = 2675 + + MOVNTImr = 2676 + + MOVNTPDmr = 2677 + + MOVNTPSmr = 2678 + + MOVNTSD = 2679 + + MOVNTSS = 2680 + + MOVPC32r = 2681 + + MOVPDI2DImr = 2682 + + MOVPDI2DIrr = 2683 + + MOVPQI2QImr = 2684 + + MOVPQI2QIrr = 2685 + + MOVPQIto64mr = 2686 + + MOVPQIto64rr = 2687 + + MOVQI2PQIrm = 2688 + + MOVRS16rm = 2689 + + MOVRS16rm_EVEX = 2690 + + MOVRS32rm = 2691 + + MOVRS32rm_EVEX = 2692 + + MOVRS64rm = 2693 + + MOVRS64rm_EVEX = 2694 + + MOVRS8rm = 2695 + + MOVRS8rm_EVEX = 2696 + + MOVSB = 2697 + + MOVSDmr = 2698 + + MOVSDrm = 2699 + + MOVSDrm_alt = 2700 + + MOVSDrr = 2701 + + MOVSDrr_REV = 2702 + + MOVSDto64rr = 2703 + + MOVSHDUPrm = 2704 + + MOVSHDUPrr = 2705 + + MOVSL = 2706 + + MOVSLDUPrm = 2707 + + MOVSLDUPrr = 2708 + + MOVSQ = 2709 + + MOVSS2DIrr = 2710 + + MOVSSmr = 2711 + + MOVSSrm = 2712 + + MOVSSrm_alt = 2713 + + MOVSSrr = 2714 + + MOVSSrr_REV = 2715 + + MOVSW = 2716 + + MOVSX16rm16 = 2717 + + MOVSX16rm32 = 2718 + + MOVSX16rm8 = 2719 + + MOVSX16rr16 = 2720 + + MOVSX16rr32 = 2721 + + MOVSX16rr8 = 2722 + + MOVSX32rm16 = 2723 + + MOVSX32rm32 = 2724 + + MOVSX32rm8 = 2725 + + MOVSX32rm8_NOREX = 2726 + + MOVSX32rr16 = 2727 + + MOVSX32rr32 = 2728 + + MOVSX32rr8 = 2729 + + MOVSX32rr8_NOREX = 2730 + + MOVSX64rm16 = 2731 + + MOVSX64rm32 = 2732 + + MOVSX64rm8 = 2733 + + MOVSX64rr16 = 2734 + + MOVSX64rr32 = 2735 + + MOVSX64rr8 = 2736 + + MOVUPDmr = 2737 + + MOVUPDrm = 2738 + + MOVUPDrr = 2739 + + MOVUPDrr_REV = 2740 + + MOVUPSmr = 2741 + + MOVUPSrm = 2742 + + MOVUPSrr = 2743 + + MOVUPSrr_REV = 2744 + + MOVZPQILo2PQIrr = 2745 + + MOVZX16rm16 = 2746 + + MOVZX16rm8 = 2747 + + MOVZX16rr16 = 2748 + + MOVZX16rr8 = 2749 + + MOVZX32rm16 = 2750 + + MOVZX32rm8 = 2751 + + MOVZX32rm8_NOREX = 2752 + + MOVZX32rr16 = 2753 + + MOVZX32rr8 = 2754 + + MOVZX32rr8_NOREX = 2755 + + MOVZX64rm16 = 2756 + + MOVZX64rm8 = 2757 + + MOVZX64rr16 = 2758 + + MOVZX64rr8 = 2759 + + MPSADBWrmi = 2760 + + MPSADBWrri = 2761 + + MUL16m = 2762 + + MUL16m_EVEX = 2763 + + MUL16m_NF = 2764 + + MUL16r = 2765 + + MUL16r_EVEX = 2766 + + MUL16r_NF = 2767 + + MUL32m = 2768 + + MUL32m_EVEX = 2769 + + MUL32m_NF = 2770 + + MUL32r = 2771 + + MUL32r_EVEX = 2772 + + MUL32r_NF = 2773 + + MUL64m = 2774 + + MUL64m_EVEX = 2775 + + MUL64m_NF = 2776 + + MUL64r = 2777 + + MUL64r_EVEX = 2778 + + MUL64r_NF = 2779 + + MUL8m = 2780 + + MUL8m_EVEX = 2781 + + MUL8m_NF = 2782 + + MUL8r = 2783 + + MUL8r_EVEX = 2784 + + MUL8r_NF = 2785 + + MULPDrm = 2786 + + MULPDrr = 2787 + + MULPSrm = 2788 + + MULPSrr = 2789 + + MULSDrm = 2790 + + MULSDrm_Int = 2791 + + MULSDrr = 2792 + + MULSDrr_Int = 2793 + + MULSSrm = 2794 + + MULSSrm_Int = 2795 + + MULSSrr = 2796 + + MULSSrr_Int = 2797 + + MULX32Hrm = 2798 + + MULX32Hrr = 2799 + + MULX32rm = 2800 + + MULX32rm_EVEX = 2801 + + MULX32rr = 2802 + + MULX32rr_EVEX = 2803 + + MULX64Hrm = 2804 + + MULX64Hrr = 2805 + + MULX64rm = 2806 + + MULX64rm_EVEX = 2807 + + MULX64rr = 2808 + + MULX64rr_EVEX = 2809 + + MUL_F32m = 2810 + + MUL_F64m = 2811 + + MUL_FI16m = 2812 + + MUL_FI32m = 2813 + + MUL_FPrST0 = 2814 + + MUL_FST0r = 2815 + + MUL_Fp32 = 2816 + + MUL_Fp32m = 2817 + + MUL_Fp64 = 2818 + + MUL_Fp64m = 2819 + + MUL_Fp64m32 = 2820 + + MUL_Fp80 = 2821 + + MUL_Fp80m32 = 2822 + + MUL_Fp80m64 = 2823 + + MUL_FpI16m32 = 2824 + + MUL_FpI16m64 = 2825 + + MUL_FpI16m80 = 2826 + + MUL_FpI32m32 = 2827 + + MUL_FpI32m64 = 2828 + + MUL_FpI32m80 = 2829 + + MUL_FrST0 = 2830 + + MWAITXrrr = 2831 + + MWAITrr = 2832 + + NEG16m = 2833 + + NEG16m_EVEX = 2834 + + NEG16m_ND = 2835 + + NEG16m_NF = 2836 + + NEG16m_NF_ND = 2837 + + NEG16r = 2838 + + NEG16r_EVEX = 2839 + + NEG16r_ND = 2840 + + NEG16r_NF = 2841 + + NEG16r_NF_ND = 2842 + + NEG32m = 2843 + + NEG32m_EVEX = 2844 + + NEG32m_ND = 2845 + + NEG32m_NF = 2846 + + NEG32m_NF_ND = 2847 + + NEG32r = 2848 + + NEG32r_EVEX = 2849 + + NEG32r_ND = 2850 + + NEG32r_NF = 2851 + + NEG32r_NF_ND = 2852 + + NEG64m = 2853 + + NEG64m_EVEX = 2854 + + NEG64m_ND = 2855 + + NEG64m_NF = 2856 + + NEG64m_NF_ND = 2857 + + NEG64r = 2858 + + NEG64r_EVEX = 2859 + + NEG64r_ND = 2860 + + NEG64r_NF = 2861 + + NEG64r_NF_ND = 2862 + + NEG8m = 2863 + + NEG8m_EVEX = 2864 + + NEG8m_ND = 2865 + + NEG8m_NF = 2866 + + NEG8m_NF_ND = 2867 + + NEG8r = 2868 + + NEG8r_EVEX = 2869 + + NEG8r_ND = 2870 + + NEG8r_NF = 2871 + + NEG8r_NF_ND = 2872 + + NOOP = 2873 + + NOOPL = 2874 + + NOOPLr = 2875 + + NOOPQ = 2876 + + NOOPQr = 2877 + + NOOPW = 2878 + + NOOPWr = 2879 + + NOT16m = 2880 + + NOT16m_EVEX = 2881 + + NOT16m_ND = 2882 + + NOT16r = 2883 + + NOT16r_EVEX = 2884 + + NOT16r_ND = 2885 + + NOT32m = 2886 + + NOT32m_EVEX = 2887 + + NOT32m_ND = 2888 + + NOT32r = 2889 + + NOT32r_EVEX = 2890 + + NOT32r_ND = 2891 + + NOT64m = 2892 + + NOT64m_EVEX = 2893 + + NOT64m_ND = 2894 + + NOT64r = 2895 + + NOT64r_EVEX = 2896 + + NOT64r_ND = 2897 + + NOT8m = 2898 + + NOT8m_EVEX = 2899 + + NOT8m_ND = 2900 + + NOT8r = 2901 + + NOT8r_EVEX = 2902 + + NOT8r_ND = 2903 + + OR16i16 = 2904 + + OR16mi = 2905 + + OR16mi8 = 2906 + + OR16mi8_EVEX = 2907 + + OR16mi8_ND = 2908 + + OR16mi8_NF = 2909 + + OR16mi8_NF_ND = 2910 + + OR16mi_EVEX = 2911 + + OR16mi_ND = 2912 + + OR16mi_NF = 2913 + + OR16mi_NF_ND = 2914 + + OR16mr = 2915 + + OR16mr_EVEX = 2916 + + OR16mr_ND = 2917 + + OR16mr_NF = 2918 + + OR16mr_NF_ND = 2919 + + OR16ri = 2920 + + OR16ri8 = 2921 + + OR16ri8_EVEX = 2922 + + OR16ri8_ND = 2923 + + OR16ri8_NF = 2924 + + OR16ri8_NF_ND = 2925 + + OR16ri_EVEX = 2926 + + OR16ri_ND = 2927 + + OR16ri_NF = 2928 + + OR16ri_NF_ND = 2929 + + OR16rm = 2930 + + OR16rm_EVEX = 2931 + + OR16rm_ND = 2932 + + OR16rm_NF = 2933 + + OR16rm_NF_ND = 2934 + + OR16rr = 2935 + + OR16rr_EVEX = 2936 + + OR16rr_EVEX_REV = 2937 + + OR16rr_ND = 2938 + + OR16rr_ND_REV = 2939 + + OR16rr_NF = 2940 + + OR16rr_NF_ND = 2941 + + OR16rr_NF_ND_REV = 2942 + + OR16rr_NF_REV = 2943 + + OR16rr_REV = 2944 + + OR32i32 = 2945 + + OR32mi = 2946 + + OR32mi8 = 2947 + + OR32mi8Locked = 2948 + + OR32mi8_EVEX = 2949 + + OR32mi8_ND = 2950 + + OR32mi8_NF = 2951 + + OR32mi8_NF_ND = 2952 + + OR32mi_EVEX = 2953 + + OR32mi_ND = 2954 + + OR32mi_NF = 2955 + + OR32mi_NF_ND = 2956 + + OR32mr = 2957 + + OR32mr_EVEX = 2958 + + OR32mr_ND = 2959 + + OR32mr_NF = 2960 + + OR32mr_NF_ND = 2961 + + OR32ri = 2962 + + OR32ri8 = 2963 + + OR32ri8_EVEX = 2964 + + OR32ri8_ND = 2965 + + OR32ri8_NF = 2966 + + OR32ri8_NF_ND = 2967 + + OR32ri_EVEX = 2968 + + OR32ri_ND = 2969 + + OR32ri_NF = 2970 + + OR32ri_NF_ND = 2971 + + OR32rm = 2972 + + OR32rm_EVEX = 2973 + + OR32rm_ND = 2974 + + OR32rm_NF = 2975 + + OR32rm_NF_ND = 2976 + + OR32rr = 2977 + + OR32rr_EVEX = 2978 + + OR32rr_EVEX_REV = 2979 + + OR32rr_ND = 2980 + + OR32rr_ND_REV = 2981 + + OR32rr_NF = 2982 + + OR32rr_NF_ND = 2983 + + OR32rr_NF_ND_REV = 2984 + + OR32rr_NF_REV = 2985 + + OR32rr_REV = 2986 + + OR64i32 = 2987 + + OR64mi32 = 2988 + + OR64mi32_EVEX = 2989 + + OR64mi32_ND = 2990 + + OR64mi32_NF = 2991 + + OR64mi32_NF_ND = 2992 + + OR64mi8 = 2993 + + OR64mi8_EVEX = 2994 + + OR64mi8_ND = 2995 + + OR64mi8_NF = 2996 + + OR64mi8_NF_ND = 2997 + + OR64mr = 2998 + + OR64mr_EVEX = 2999 + + OR64mr_ND = 3000 + + OR64mr_NF = 3001 + + OR64mr_NF_ND = 3002 + + OR64ri32 = 3003 + + OR64ri32_EVEX = 3004 + + OR64ri32_ND = 3005 + + OR64ri32_NF = 3006 + + OR64ri32_NF_ND = 3007 + + OR64ri8 = 3008 + + OR64ri8_EVEX = 3009 + + OR64ri8_ND = 3010 + + OR64ri8_NF = 3011 + + OR64ri8_NF_ND = 3012 + + OR64rm = 3013 + + OR64rm_EVEX = 3014 + + OR64rm_ND = 3015 + + OR64rm_NF = 3016 + + OR64rm_NF_ND = 3017 + + OR64rr = 3018 + + OR64rr_EVEX = 3019 + + OR64rr_EVEX_REV = 3020 + + OR64rr_ND = 3021 + + OR64rr_ND_REV = 3022 + + OR64rr_NF = 3023 + + OR64rr_NF_ND = 3024 + + OR64rr_NF_ND_REV = 3025 + + OR64rr_NF_REV = 3026 + + OR64rr_REV = 3027 + + OR8i8 = 3028 + + OR8mi = 3029 + + OR8mi8 = 3030 + + OR8mi_EVEX = 3031 + + OR8mi_ND = 3032 + + OR8mi_NF = 3033 + + OR8mi_NF_ND = 3034 + + OR8mr = 3035 + + OR8mr_EVEX = 3036 + + OR8mr_ND = 3037 + + OR8mr_NF = 3038 + + OR8mr_NF_ND = 3039 + + OR8ri = 3040 + + OR8ri8 = 3041 + + OR8ri_EVEX = 3042 + + OR8ri_ND = 3043 + + OR8ri_NF = 3044 + + OR8ri_NF_ND = 3045 + + OR8rm = 3046 + + OR8rm_EVEX = 3047 + + OR8rm_ND = 3048 + + OR8rm_NF = 3049 + + OR8rm_NF_ND = 3050 + + OR8rr = 3051 + + OR8rr_EVEX = 3052 + + OR8rr_EVEX_REV = 3053 + + OR8rr_ND = 3054 + + OR8rr_ND_REV = 3055 + + OR8rr_NF = 3056 + + OR8rr_NF_ND = 3057 + + OR8rr_NF_ND_REV = 3058 + + OR8rr_NF_REV = 3059 + + OR8rr_REV = 3060 + + ORPDrm = 3061 + + ORPDrr = 3062 + + ORPSrm = 3063 + + ORPSrr = 3064 + + OUT16ir = 3065 + + OUT16rr = 3066 + + OUT32ir = 3067 + + OUT32rr = 3068 + + OUT8ir = 3069 + + OUT8rr = 3070 + + OUTSB = 3071 + + OUTSL = 3072 + + OUTSW = 3073 + + PABSBrm = 3074 + + PABSBrr = 3075 + + PABSDrm = 3076 + + PABSDrr = 3077 + + PABSWrm = 3078 + + PABSWrr = 3079 + + PACKSSDWrm = 3080 + + PACKSSDWrr = 3081 + + PACKSSWBrm = 3082 + + PACKSSWBrr = 3083 + + PACKUSDWrm = 3084 + + PACKUSDWrr = 3085 + + PACKUSWBrm = 3086 + + PACKUSWBrr = 3087 + + PADDBrm = 3088 + + PADDBrr = 3089 + + PADDDrm = 3090 + + PADDDrr = 3091 + + PADDQrm = 3092 + + PADDQrr = 3093 + + PADDSBrm = 3094 + + PADDSBrr = 3095 + + PADDSWrm = 3096 + + PADDSWrr = 3097 + + PADDUSBrm = 3098 + + PADDUSBrr = 3099 + + PADDUSWrm = 3100 + + PADDUSWrr = 3101 + + PADDWrm = 3102 + + PADDWrr = 3103 + + PALIGNRrmi = 3104 + + PALIGNRrri = 3105 + + PANDNrm = 3106 + + PANDNrr = 3107 + + PANDrm = 3108 + + PANDrr = 3109 + + PAUSE = 3110 + + PAVGBrm = 3111 + + PAVGBrr = 3112 + + PAVGUSBrm = 3113 + + PAVGUSBrr = 3114 + + PAVGWrm = 3115 + + PAVGWrr = 3116 + + PBLENDVBrm0 = 3117 + + PBLENDVBrr0 = 3118 + + PBLENDWrmi = 3119 + + PBLENDWrri = 3120 + + PBNDKB = 3121 + + PCLMULQDQrmi = 3122 + + PCLMULQDQrri = 3123 + + PCMPEQBrm = 3124 + + PCMPEQBrr = 3125 + + PCMPEQDrm = 3126 + + PCMPEQDrr = 3127 + + PCMPEQQrm = 3128 + + PCMPEQQrr = 3129 + + PCMPEQWrm = 3130 + + PCMPEQWrr = 3131 + + PCMPESTRIrmi = 3132 + + PCMPESTRIrri = 3133 + + PCMPESTRMrmi = 3134 + + PCMPESTRMrri = 3135 + + PCMPGTBrm = 3136 + + PCMPGTBrr = 3137 + + PCMPGTDrm = 3138 + + PCMPGTDrr = 3139 + + PCMPGTQrm = 3140 + + PCMPGTQrr = 3141 + + PCMPGTWrm = 3142 + + PCMPGTWrr = 3143 + + PCMPISTRIrmi = 3144 + + PCMPISTRIrri = 3145 + + PCMPISTRMrmi = 3146 + + PCMPISTRMrri = 3147 + + PCONFIG = 3148 + + PDEP32rm = 3149 + + PDEP32rm_EVEX = 3150 + + PDEP32rr = 3151 + + PDEP32rr_EVEX = 3152 + + PDEP64rm = 3153 + + PDEP64rm_EVEX = 3154 + + PDEP64rr = 3155 + + PDEP64rr_EVEX = 3156 + + PEXT32rm = 3157 + + PEXT32rm_EVEX = 3158 + + PEXT32rr = 3159 + + PEXT32rr_EVEX = 3160 + + PEXT64rm = 3161 + + PEXT64rm_EVEX = 3162 + + PEXT64rr = 3163 + + PEXT64rr_EVEX = 3164 + + PEXTRBmri = 3165 + + PEXTRBrri = 3166 + + PEXTRDmri = 3167 + + PEXTRDrri = 3168 + + PEXTRQmri = 3169 + + PEXTRQrri = 3170 + + PEXTRWmri = 3171 + + PEXTRWrri = 3172 + + PEXTRWrri_REV = 3173 + + PF2IDrm = 3174 + + PF2IDrr = 3175 + + PF2IWrm = 3176 + + PF2IWrr = 3177 + + PFACCrm = 3178 + + PFACCrr = 3179 + + PFADDrm = 3180 + + PFADDrr = 3181 + + PFCMPEQrm = 3182 + + PFCMPEQrr = 3183 + + PFCMPGErm = 3184 + + PFCMPGErr = 3185 + + PFCMPGTrm = 3186 + + PFCMPGTrr = 3187 + + PFMAXrm = 3188 + + PFMAXrr = 3189 + + PFMINrm = 3190 + + PFMINrr = 3191 + + PFMULrm = 3192 + + PFMULrr = 3193 + + PFNACCrm = 3194 + + PFNACCrr = 3195 + + PFPNACCrm = 3196 + + PFPNACCrr = 3197 + + PFRCPIT1rm = 3198 + + PFRCPIT1rr = 3199 + + PFRCPIT2rm = 3200 + + PFRCPIT2rr = 3201 + + PFRCPrm = 3202 + + PFRCPrr = 3203 + + PFRSQIT1rm = 3204 + + PFRSQIT1rr = 3205 + + PFRSQRTrm = 3206 + + PFRSQRTrr = 3207 + + PFSUBRrm = 3208 + + PFSUBRrr = 3209 + + PFSUBrm = 3210 + + PFSUBrr = 3211 + + PHADDDrm = 3212 + + PHADDDrr = 3213 + + PHADDSWrm = 3214 + + PHADDSWrr = 3215 + + PHADDWrm = 3216 + + PHADDWrr = 3217 + + PHMINPOSUWrm = 3218 + + PHMINPOSUWrr = 3219 + + PHSUBDrm = 3220 + + PHSUBDrr = 3221 + + PHSUBSWrm = 3222 + + PHSUBSWrr = 3223 + + PHSUBWrm = 3224 + + PHSUBWrr = 3225 + + PI2FDrm = 3226 + + PI2FDrr = 3227 + + PI2FWrm = 3228 + + PI2FWrr = 3229 + + PINSRBrmi = 3230 + + PINSRBrri = 3231 + + PINSRDrmi = 3232 + + PINSRDrri = 3233 + + PINSRQrmi = 3234 + + PINSRQrri = 3235 + + PINSRWrmi = 3236 + + PINSRWrri = 3237 + + PMADDUBSWrm = 3238 + + PMADDUBSWrr = 3239 + + PMADDWDrm = 3240 + + PMADDWDrr = 3241 + + PMAXSBrm = 3242 + + PMAXSBrr = 3243 + + PMAXSDrm = 3244 + + PMAXSDrr = 3245 + + PMAXSWrm = 3246 + + PMAXSWrr = 3247 + + PMAXUBrm = 3248 + + PMAXUBrr = 3249 + + PMAXUDrm = 3250 + + PMAXUDrr = 3251 + + PMAXUWrm = 3252 + + PMAXUWrr = 3253 + + PMINSBrm = 3254 + + PMINSBrr = 3255 + + PMINSDrm = 3256 + + PMINSDrr = 3257 + + PMINSWrm = 3258 + + PMINSWrr = 3259 + + PMINUBrm = 3260 + + PMINUBrr = 3261 + + PMINUDrm = 3262 + + PMINUDrr = 3263 + + PMINUWrm = 3264 + + PMINUWrr = 3265 + + PMOVMSKBrr = 3266 + + PMOVSXBDrm = 3267 + + PMOVSXBDrr = 3268 + + PMOVSXBQrm = 3269 + + PMOVSXBQrr = 3270 + + PMOVSXBWrm = 3271 + + PMOVSXBWrr = 3272 + + PMOVSXDQrm = 3273 + + PMOVSXDQrr = 3274 + + PMOVSXWDrm = 3275 + + PMOVSXWDrr = 3276 + + PMOVSXWQrm = 3277 + + PMOVSXWQrr = 3278 + + PMOVZXBDrm = 3279 + + PMOVZXBDrr = 3280 + + PMOVZXBQrm = 3281 + + PMOVZXBQrr = 3282 + + PMOVZXBWrm = 3283 + + PMOVZXBWrr = 3284 + + PMOVZXDQrm = 3285 + + PMOVZXDQrr = 3286 + + PMOVZXWDrm = 3287 + + PMOVZXWDrr = 3288 + + PMOVZXWQrm = 3289 + + PMOVZXWQrr = 3290 + + PMULDQrm = 3291 + + PMULDQrr = 3292 + + PMULHRSWrm = 3293 + + PMULHRSWrr = 3294 + + PMULHRWrm = 3295 + + PMULHRWrr = 3296 + + PMULHUWrm = 3297 + + PMULHUWrr = 3298 + + PMULHWrm = 3299 + + PMULHWrr = 3300 + + PMULLDrm = 3301 + + PMULLDrr = 3302 + + PMULLWrm = 3303 + + PMULLWrr = 3304 + + PMULUDQrm = 3305 + + PMULUDQrr = 3306 + + POP16r = 3307 + + POP16rmm = 3308 + + POP16rmr = 3309 + + POP2 = 3310 + + POP2P = 3311 + + POP32r = 3312 + + POP32rmm = 3313 + + POP32rmr = 3314 + + POP64r = 3315 + + POP64rmm = 3316 + + POP64rmr = 3317 + + POPA16 = 3318 + + POPA32 = 3319 + + POPCNT16rm = 3320 + + POPCNT16rm_EVEX = 3321 + + POPCNT16rm_NF = 3322 + + POPCNT16rr = 3323 + + POPCNT16rr_EVEX = 3324 + + POPCNT16rr_NF = 3325 + + POPCNT32rm = 3326 + + POPCNT32rm_EVEX = 3327 + + POPCNT32rm_NF = 3328 + + POPCNT32rr = 3329 + + POPCNT32rr_EVEX = 3330 + + POPCNT32rr_NF = 3331 + + POPCNT64rm = 3332 + + POPCNT64rm_EVEX = 3333 + + POPCNT64rm_NF = 3334 + + POPCNT64rr = 3335 + + POPCNT64rr_EVEX = 3336 + + POPCNT64rr_NF = 3337 + + POPDS16 = 3338 + + POPDS32 = 3339 + + POPES16 = 3340 + + POPES32 = 3341 + + POPF16 = 3342 + + POPF32 = 3343 + + POPF64 = 3344 + + POPFS16 = 3345 + + POPFS32 = 3346 + + POPFS64 = 3347 + + POPGS16 = 3348 + + POPGS32 = 3349 + + POPGS64 = 3350 + + POPP64r = 3351 + + POPSS16 = 3352 + + POPSS32 = 3353 + + PORrm = 3354 + + PORrr = 3355 + + PREFETCH = 3356 + + PREFETCHIT0 = 3357 + + PREFETCHIT1 = 3358 + + PREFETCHNTA = 3359 + + PREFETCHRST2 = 3360 + + PREFETCHT0 = 3361 + + PREFETCHT1 = 3362 + + PREFETCHT2 = 3363 + + PREFETCHW = 3364 + + PREFETCHWT1 = 3365 + + PROBED_ALLOCA_32 = 3366 + + PROBED_ALLOCA_64 = 3367 + + PSADBWrm = 3368 + + PSADBWrr = 3369 + + PSHUFBrm = 3370 + + PSHUFBrr = 3371 + + PSHUFDmi = 3372 + + PSHUFDri = 3373 + + PSHUFHWmi = 3374 + + PSHUFHWri = 3375 + + PSHUFLWmi = 3376 + + PSHUFLWri = 3377 + + PSIGNBrm = 3378 + + PSIGNBrr = 3379 + + PSIGNDrm = 3380 + + PSIGNDrr = 3381 + + PSIGNWrm = 3382 + + PSIGNWrr = 3383 + + PSLLDQri = 3384 + + PSLLDri = 3385 + + PSLLDrm = 3386 + + PSLLDrr = 3387 + + PSLLQri = 3388 + + PSLLQrm = 3389 + + PSLLQrr = 3390 + + PSLLWri = 3391 + + PSLLWrm = 3392 + + PSLLWrr = 3393 + + PSMASH = 3394 + + PSRADri = 3395 + + PSRADrm = 3396 + + PSRADrr = 3397 + + PSRAWri = 3398 + + PSRAWrm = 3399 + + PSRAWrr = 3400 + + PSRLDQri = 3401 + + PSRLDri = 3402 + + PSRLDrm = 3403 + + PSRLDrr = 3404 + + PSRLQri = 3405 + + PSRLQrm = 3406 + + PSRLQrr = 3407 + + PSRLWri = 3408 + + PSRLWrm = 3409 + + PSRLWrr = 3410 + + PSUBBrm = 3411 + + PSUBBrr = 3412 + + PSUBDrm = 3413 + + PSUBDrr = 3414 + + PSUBQrm = 3415 + + PSUBQrr = 3416 + + PSUBSBrm = 3417 + + PSUBSBrr = 3418 + + PSUBSWrm = 3419 + + PSUBSWrr = 3420 + + PSUBUSBrm = 3421 + + PSUBUSBrr = 3422 + + PSUBUSWrm = 3423 + + PSUBUSWrr = 3424 + + PSUBWrm = 3425 + + PSUBWrr = 3426 + + PSWAPDrm = 3427 + + PSWAPDrr = 3428 + + PTCMMIMFP16PS = 3429 + + PTCMMIMFP16PSV = 3430 + + PTCMMRLFP16PS = 3431 + + PTCMMRLFP16PSV = 3432 + + PTCVTROWD2PSrre = 3433 + + PTCVTROWD2PSrreV = 3434 + + PTCVTROWD2PSrri = 3435 + + PTCVTROWD2PSrriV = 3436 + + PTCVTROWPS2BF16Hrre = 3437 + + PTCVTROWPS2BF16HrreV = 3438 + + PTCVTROWPS2BF16Hrri = 3439 + + PTCVTROWPS2BF16HrriV = 3440 + + PTCVTROWPS2BF16Lrre = 3441 + + PTCVTROWPS2BF16LrreV = 3442 + + PTCVTROWPS2BF16Lrri = 3443 + + PTCVTROWPS2BF16LrriV = 3444 + + PTCVTROWPS2PHHrre = 3445 + + PTCVTROWPS2PHHrreV = 3446 + + PTCVTROWPS2PHHrri = 3447 + + PTCVTROWPS2PHHrriV = 3448 + + PTCVTROWPS2PHLrre = 3449 + + PTCVTROWPS2PHLrreV = 3450 + + PTCVTROWPS2PHLrri = 3451 + + PTCVTROWPS2PHLrriV = 3452 + + PTDPBF16PS = 3453 + + PTDPBF8PS = 3454 + + PTDPBF8PSV = 3455 + + PTDPBHF8PS = 3456 + + PTDPBHF8PSV = 3457 + + PTDPBSSD = 3458 + + PTDPBSUD = 3459 + + PTDPBUSD = 3460 + + PTDPBUUD = 3461 + + PTDPFP16PS = 3462 + + PTDPHBF8PS = 3463 + + PTDPHBF8PSV = 3464 + + PTDPHF8PS = 3465 + + PTDPHF8PSV = 3466 + + PTESTrm = 3467 + + PTESTrr = 3468 + + PTILELOADD = 3469 + + PTILELOADDRS = 3470 + + PTILELOADDRST1 = 3471 + + PTILELOADDT1 = 3472 + + PTILEMOVROWrre = 3473 + + PTILEMOVROWrreV = 3474 + + PTILEMOVROWrri = 3475 + + PTILEMOVROWrriV = 3476 + + PTILESTORED = 3477 + + PTILEZERO = 3478 + + PTMMULTF32PS = 3479 + + PTMMULTF32PSV = 3480 + + PTWRITE64m = 3481 + + PTWRITE64r = 3482 + + PTWRITEm = 3483 + + PTWRITEr = 3484 + + PUNPCKHBWrm = 3485 + + PUNPCKHBWrr = 3486 + + PUNPCKHDQrm = 3487 + + PUNPCKHDQrr = 3488 + + PUNPCKHQDQrm = 3489 + + PUNPCKHQDQrr = 3490 + + PUNPCKHWDrm = 3491 + + PUNPCKHWDrr = 3492 + + PUNPCKLBWrm = 3493 + + PUNPCKLBWrr = 3494 + + PUNPCKLDQrm = 3495 + + PUNPCKLDQrr = 3496 + + PUNPCKLQDQrm = 3497 + + PUNPCKLQDQrr = 3498 + + PUNPCKLWDrm = 3499 + + PUNPCKLWDrr = 3500 + + PUSH16i = 3501 + + PUSH16i8 = 3502 + + PUSH16r = 3503 + + PUSH16rmm = 3504 + + PUSH16rmr = 3505 + + PUSH2 = 3506 + + PUSH2P = 3507 + + PUSH32i = 3508 + + PUSH32i8 = 3509 + + PUSH32r = 3510 + + PUSH32rmm = 3511 + + PUSH32rmr = 3512 + + PUSH64i32 = 3513 + + PUSH64i8 = 3514 + + PUSH64r = 3515 + + PUSH64rmm = 3516 + + PUSH64rmr = 3517 + + PUSHA16 = 3518 + + PUSHA32 = 3519 + + PUSHCS16 = 3520 + + PUSHCS32 = 3521 + + PUSHDS16 = 3522 + + PUSHDS32 = 3523 + + PUSHES16 = 3524 + + PUSHES32 = 3525 + + PUSHF16 = 3526 + + PUSHF32 = 3527 + + PUSHF64 = 3528 + + PUSHFS16 = 3529 + + PUSHFS32 = 3530 + + PUSHFS64 = 3531 + + PUSHGS16 = 3532 + + PUSHGS32 = 3533 + + PUSHGS64 = 3534 + + PUSHP64r = 3535 + + PUSHSS16 = 3536 + + PUSHSS32 = 3537 + + PVALIDATE32 = 3538 + + PVALIDATE64 = 3539 + + PXORrm = 3540 + + PXORrr = 3541 + + RCL16m1 = 3542 + + RCL16m1_EVEX = 3543 + + RCL16m1_ND = 3544 + + RCL16mCL = 3545 + + RCL16mCL_EVEX = 3546 + + RCL16mCL_ND = 3547 + + RCL16mi = 3548 + + RCL16mi_EVEX = 3549 + + RCL16mi_ND = 3550 + + RCL16r1 = 3551 + + RCL16r1_EVEX = 3552 + + RCL16r1_ND = 3553 + + RCL16rCL = 3554 + + RCL16rCL_EVEX = 3555 + + RCL16rCL_ND = 3556 + + RCL16ri = 3557 + + RCL16ri_EVEX = 3558 + + RCL16ri_ND = 3559 + + RCL32m1 = 3560 + + RCL32m1_EVEX = 3561 + + RCL32m1_ND = 3562 + + RCL32mCL = 3563 + + RCL32mCL_EVEX = 3564 + + RCL32mCL_ND = 3565 + + RCL32mi = 3566 + + RCL32mi_EVEX = 3567 + + RCL32mi_ND = 3568 + + RCL32r1 = 3569 + + RCL32r1_EVEX = 3570 + + RCL32r1_ND = 3571 + + RCL32rCL = 3572 + + RCL32rCL_EVEX = 3573 + + RCL32rCL_ND = 3574 + + RCL32ri = 3575 + + RCL32ri_EVEX = 3576 + + RCL32ri_ND = 3577 + + RCL64m1 = 3578 + + RCL64m1_EVEX = 3579 + + RCL64m1_ND = 3580 + + RCL64mCL = 3581 + + RCL64mCL_EVEX = 3582 + + RCL64mCL_ND = 3583 + + RCL64mi = 3584 + + RCL64mi_EVEX = 3585 + + RCL64mi_ND = 3586 + + RCL64r1 = 3587 + + RCL64r1_EVEX = 3588 + + RCL64r1_ND = 3589 + + RCL64rCL = 3590 + + RCL64rCL_EVEX = 3591 + + RCL64rCL_ND = 3592 + + RCL64ri = 3593 + + RCL64ri_EVEX = 3594 + + RCL64ri_ND = 3595 + + RCL8m1 = 3596 + + RCL8m1_EVEX = 3597 + + RCL8m1_ND = 3598 + + RCL8mCL = 3599 + + RCL8mCL_EVEX = 3600 + + RCL8mCL_ND = 3601 + + RCL8mi = 3602 + + RCL8mi_EVEX = 3603 + + RCL8mi_ND = 3604 + + RCL8r1 = 3605 + + RCL8r1_EVEX = 3606 + + RCL8r1_ND = 3607 + + RCL8rCL = 3608 + + RCL8rCL_EVEX = 3609 + + RCL8rCL_ND = 3610 + + RCL8ri = 3611 + + RCL8ri_EVEX = 3612 + + RCL8ri_ND = 3613 + + RCPPSm = 3614 + + RCPPSr = 3615 + + RCPSSm = 3616 + + RCPSSm_Int = 3617 + + RCPSSr = 3618 + + RCPSSr_Int = 3619 + + RCR16m1 = 3620 + + RCR16m1_EVEX = 3621 + + RCR16m1_ND = 3622 + + RCR16mCL = 3623 + + RCR16mCL_EVEX = 3624 + + RCR16mCL_ND = 3625 + + RCR16mi = 3626 + + RCR16mi_EVEX = 3627 + + RCR16mi_ND = 3628 + + RCR16r1 = 3629 + + RCR16r1_EVEX = 3630 + + RCR16r1_ND = 3631 + + RCR16rCL = 3632 + + RCR16rCL_EVEX = 3633 + + RCR16rCL_ND = 3634 + + RCR16ri = 3635 + + RCR16ri_EVEX = 3636 + + RCR16ri_ND = 3637 + + RCR32m1 = 3638 + + RCR32m1_EVEX = 3639 + + RCR32m1_ND = 3640 + + RCR32mCL = 3641 + + RCR32mCL_EVEX = 3642 + + RCR32mCL_ND = 3643 + + RCR32mi = 3644 + + RCR32mi_EVEX = 3645 + + RCR32mi_ND = 3646 + + RCR32r1 = 3647 + + RCR32r1_EVEX = 3648 + + RCR32r1_ND = 3649 + + RCR32rCL = 3650 + + RCR32rCL_EVEX = 3651 + + RCR32rCL_ND = 3652 + + RCR32ri = 3653 + + RCR32ri_EVEX = 3654 + + RCR32ri_ND = 3655 + + RCR64m1 = 3656 + + RCR64m1_EVEX = 3657 + + RCR64m1_ND = 3658 + + RCR64mCL = 3659 + + RCR64mCL_EVEX = 3660 + + RCR64mCL_ND = 3661 + + RCR64mi = 3662 + + RCR64mi_EVEX = 3663 + + RCR64mi_ND = 3664 + + RCR64r1 = 3665 + + RCR64r1_EVEX = 3666 + + RCR64r1_ND = 3667 + + RCR64rCL = 3668 + + RCR64rCL_EVEX = 3669 + + RCR64rCL_ND = 3670 + + RCR64ri = 3671 + + RCR64ri_EVEX = 3672 + + RCR64ri_ND = 3673 + + RCR8m1 = 3674 + + RCR8m1_EVEX = 3675 + + RCR8m1_ND = 3676 + + RCR8mCL = 3677 + + RCR8mCL_EVEX = 3678 + + RCR8mCL_ND = 3679 + + RCR8mi = 3680 + + RCR8mi_EVEX = 3681 + + RCR8mi_ND = 3682 + + RCR8r1 = 3683 + + RCR8r1_EVEX = 3684 + + RCR8r1_ND = 3685 + + RCR8rCL = 3686 + + RCR8rCL_EVEX = 3687 + + RCR8rCL_ND = 3688 + + RCR8ri = 3689 + + RCR8ri_EVEX = 3690 + + RCR8ri_ND = 3691 + + RDFSBASE = 3692 + + RDFSBASE64 = 3693 + + RDGSBASE = 3694 + + RDGSBASE64 = 3695 + + RDMSR = 3696 + + RDMSRLIST = 3697 + + RDMSRri = 3698 + + RDMSRri_EVEX = 3699 + + RDPID32 = 3700 + + RDPID64 = 3701 + + RDPKRUr = 3702 + + RDPMC = 3703 + + RDPRU = 3704 + + RDRAND16r = 3705 + + RDRAND32r = 3706 + + RDRAND64r = 3707 + + RDSEED16r = 3708 + + RDSEED32r = 3709 + + RDSEED64r = 3710 + + RDSSPD = 3711 + + RDSSPQ = 3712 + + RDTSC = 3713 + + RDTSCP = 3714 + + REPNE_PREFIX = 3715 + + REP_MOVSB_32 = 3716 + + REP_MOVSB_64 = 3717 + + REP_MOVSD_32 = 3718 + + REP_MOVSD_64 = 3719 + + REP_MOVSQ_32 = 3720 + + REP_MOVSQ_64 = 3721 + + REP_MOVSW_32 = 3722 + + REP_MOVSW_64 = 3723 + + REP_PREFIX = 3724 + + REP_STOSB_32 = 3725 + + REP_STOSB_64 = 3726 + + REP_STOSD_32 = 3727 + + REP_STOSD_64 = 3728 + + REP_STOSQ_32 = 3729 + + REP_STOSQ_64 = 3730 + + REP_STOSW_32 = 3731 + + REP_STOSW_64 = 3732 + + RET = 3733 + + RET16 = 3734 + + RET32 = 3735 + + RET64 = 3736 + + RETI16 = 3737 + + RETI32 = 3738 + + RETI64 = 3739 + + REX64_PREFIX = 3740 + + RMPADJUST = 3741 + + RMPQUERY = 3742 + + RMPUPDATE = 3743 + + ROL16m1 = 3744 + + ROL16m1_EVEX = 3745 + + ROL16m1_ND = 3746 + + ROL16m1_NF = 3747 + + ROL16m1_NF_ND = 3748 + + ROL16mCL = 3749 + + ROL16mCL_EVEX = 3750 + + ROL16mCL_ND = 3751 + + ROL16mCL_NF = 3752 + + ROL16mCL_NF_ND = 3753 + + ROL16mi = 3754 + + ROL16mi_EVEX = 3755 + + ROL16mi_ND = 3756 + + ROL16mi_NF = 3757 + + ROL16mi_NF_ND = 3758 + + ROL16r1 = 3759 + + ROL16r1_EVEX = 3760 + + ROL16r1_ND = 3761 + + ROL16r1_NF = 3762 + + ROL16r1_NF_ND = 3763 + + ROL16rCL = 3764 + + ROL16rCL_EVEX = 3765 + + ROL16rCL_ND = 3766 + + ROL16rCL_NF = 3767 + + ROL16rCL_NF_ND = 3768 + + ROL16ri = 3769 + + ROL16ri_EVEX = 3770 + + ROL16ri_ND = 3771 + + ROL16ri_NF = 3772 + + ROL16ri_NF_ND = 3773 + + ROL32m1 = 3774 + + ROL32m1_EVEX = 3775 + + ROL32m1_ND = 3776 + + ROL32m1_NF = 3777 + + ROL32m1_NF_ND = 3778 + + ROL32mCL = 3779 + + ROL32mCL_EVEX = 3780 + + ROL32mCL_ND = 3781 + + ROL32mCL_NF = 3782 + + ROL32mCL_NF_ND = 3783 + + ROL32mi = 3784 + + ROL32mi_EVEX = 3785 + + ROL32mi_ND = 3786 + + ROL32mi_NF = 3787 + + ROL32mi_NF_ND = 3788 + + ROL32r1 = 3789 + + ROL32r1_EVEX = 3790 + + ROL32r1_ND = 3791 + + ROL32r1_NF = 3792 + + ROL32r1_NF_ND = 3793 + + ROL32rCL = 3794 + + ROL32rCL_EVEX = 3795 + + ROL32rCL_ND = 3796 + + ROL32rCL_NF = 3797 + + ROL32rCL_NF_ND = 3798 + + ROL32ri = 3799 + + ROL32ri_EVEX = 3800 + + ROL32ri_ND = 3801 + + ROL32ri_NF = 3802 + + ROL32ri_NF_ND = 3803 + + ROL64m1 = 3804 + + ROL64m1_EVEX = 3805 + + ROL64m1_ND = 3806 + + ROL64m1_NF = 3807 + + ROL64m1_NF_ND = 3808 + + ROL64mCL = 3809 + + ROL64mCL_EVEX = 3810 + + ROL64mCL_ND = 3811 + + ROL64mCL_NF = 3812 + + ROL64mCL_NF_ND = 3813 + + ROL64mi = 3814 + + ROL64mi_EVEX = 3815 + + ROL64mi_ND = 3816 + + ROL64mi_NF = 3817 + + ROL64mi_NF_ND = 3818 + + ROL64r1 = 3819 + + ROL64r1_EVEX = 3820 + + ROL64r1_ND = 3821 + + ROL64r1_NF = 3822 + + ROL64r1_NF_ND = 3823 + + ROL64rCL = 3824 + + ROL64rCL_EVEX = 3825 + + ROL64rCL_ND = 3826 + + ROL64rCL_NF = 3827 + + ROL64rCL_NF_ND = 3828 + + ROL64ri = 3829 + + ROL64ri_EVEX = 3830 + + ROL64ri_ND = 3831 + + ROL64ri_NF = 3832 + + ROL64ri_NF_ND = 3833 + + ROL8m1 = 3834 + + ROL8m1_EVEX = 3835 + + ROL8m1_ND = 3836 + + ROL8m1_NF = 3837 + + ROL8m1_NF_ND = 3838 + + ROL8mCL = 3839 + + ROL8mCL_EVEX = 3840 + + ROL8mCL_ND = 3841 + + ROL8mCL_NF = 3842 + + ROL8mCL_NF_ND = 3843 + + ROL8mi = 3844 + + ROL8mi_EVEX = 3845 + + ROL8mi_ND = 3846 + + ROL8mi_NF = 3847 + + ROL8mi_NF_ND = 3848 + + ROL8r1 = 3849 + + ROL8r1_EVEX = 3850 + + ROL8r1_ND = 3851 + + ROL8r1_NF = 3852 + + ROL8r1_NF_ND = 3853 + + ROL8rCL = 3854 + + ROL8rCL_EVEX = 3855 + + ROL8rCL_ND = 3856 + + ROL8rCL_NF = 3857 + + ROL8rCL_NF_ND = 3858 + + ROL8ri = 3859 + + ROL8ri_EVEX = 3860 + + ROL8ri_ND = 3861 + + ROL8ri_NF = 3862 + + ROL8ri_NF_ND = 3863 + + ROR16m1 = 3864 + + ROR16m1_EVEX = 3865 + + ROR16m1_ND = 3866 + + ROR16m1_NF = 3867 + + ROR16m1_NF_ND = 3868 + + ROR16mCL = 3869 + + ROR16mCL_EVEX = 3870 + + ROR16mCL_ND = 3871 + + ROR16mCL_NF = 3872 + + ROR16mCL_NF_ND = 3873 + + ROR16mi = 3874 + + ROR16mi_EVEX = 3875 + + ROR16mi_ND = 3876 + + ROR16mi_NF = 3877 + + ROR16mi_NF_ND = 3878 + + ROR16r1 = 3879 + + ROR16r1_EVEX = 3880 + + ROR16r1_ND = 3881 + + ROR16r1_NF = 3882 + + ROR16r1_NF_ND = 3883 + + ROR16rCL = 3884 + + ROR16rCL_EVEX = 3885 + + ROR16rCL_ND = 3886 + + ROR16rCL_NF = 3887 + + ROR16rCL_NF_ND = 3888 + + ROR16ri = 3889 + + ROR16ri_EVEX = 3890 + + ROR16ri_ND = 3891 + + ROR16ri_NF = 3892 + + ROR16ri_NF_ND = 3893 + + ROR32m1 = 3894 + + ROR32m1_EVEX = 3895 + + ROR32m1_ND = 3896 + + ROR32m1_NF = 3897 + + ROR32m1_NF_ND = 3898 + + ROR32mCL = 3899 + + ROR32mCL_EVEX = 3900 + + ROR32mCL_ND = 3901 + + ROR32mCL_NF = 3902 + + ROR32mCL_NF_ND = 3903 + + ROR32mi = 3904 + + ROR32mi_EVEX = 3905 + + ROR32mi_ND = 3906 + + ROR32mi_NF = 3907 + + ROR32mi_NF_ND = 3908 + + ROR32r1 = 3909 + + ROR32r1_EVEX = 3910 + + ROR32r1_ND = 3911 + + ROR32r1_NF = 3912 + + ROR32r1_NF_ND = 3913 + + ROR32rCL = 3914 + + ROR32rCL_EVEX = 3915 + + ROR32rCL_ND = 3916 + + ROR32rCL_NF = 3917 + + ROR32rCL_NF_ND = 3918 + + ROR32ri = 3919 + + ROR32ri_EVEX = 3920 + + ROR32ri_ND = 3921 + + ROR32ri_NF = 3922 + + ROR32ri_NF_ND = 3923 + + ROR64m1 = 3924 + + ROR64m1_EVEX = 3925 + + ROR64m1_ND = 3926 + + ROR64m1_NF = 3927 + + ROR64m1_NF_ND = 3928 + + ROR64mCL = 3929 + + ROR64mCL_EVEX = 3930 + + ROR64mCL_ND = 3931 + + ROR64mCL_NF = 3932 + + ROR64mCL_NF_ND = 3933 + + ROR64mi = 3934 + + ROR64mi_EVEX = 3935 + + ROR64mi_ND = 3936 + + ROR64mi_NF = 3937 + + ROR64mi_NF_ND = 3938 + + ROR64r1 = 3939 + + ROR64r1_EVEX = 3940 + + ROR64r1_ND = 3941 + + ROR64r1_NF = 3942 + + ROR64r1_NF_ND = 3943 + + ROR64rCL = 3944 + + ROR64rCL_EVEX = 3945 + + ROR64rCL_ND = 3946 + + ROR64rCL_NF = 3947 + + ROR64rCL_NF_ND = 3948 + + ROR64ri = 3949 + + ROR64ri_EVEX = 3950 + + ROR64ri_ND = 3951 + + ROR64ri_NF = 3952 + + ROR64ri_NF_ND = 3953 + + ROR8m1 = 3954 + + ROR8m1_EVEX = 3955 + + ROR8m1_ND = 3956 + + ROR8m1_NF = 3957 + + ROR8m1_NF_ND = 3958 + + ROR8mCL = 3959 + + ROR8mCL_EVEX = 3960 + + ROR8mCL_ND = 3961 + + ROR8mCL_NF = 3962 + + ROR8mCL_NF_ND = 3963 + + ROR8mi = 3964 + + ROR8mi_EVEX = 3965 + + ROR8mi_ND = 3966 + + ROR8mi_NF = 3967 + + ROR8mi_NF_ND = 3968 + + ROR8r1 = 3969 + + ROR8r1_EVEX = 3970 + + ROR8r1_ND = 3971 + + ROR8r1_NF = 3972 + + ROR8r1_NF_ND = 3973 + + ROR8rCL = 3974 + + ROR8rCL_EVEX = 3975 + + ROR8rCL_ND = 3976 + + ROR8rCL_NF = 3977 + + ROR8rCL_NF_ND = 3978 + + ROR8ri = 3979 + + ROR8ri_EVEX = 3980 + + ROR8ri_ND = 3981 + + ROR8ri_NF = 3982 + + ROR8ri_NF_ND = 3983 + + RORX32mi = 3984 + + RORX32mi_EVEX = 3985 + + RORX32ri = 3986 + + RORX32ri_EVEX = 3987 + + RORX64mi = 3988 + + RORX64mi_EVEX = 3989 + + RORX64ri = 3990 + + RORX64ri_EVEX = 3991 + + ROUNDPDmi = 3992 + + ROUNDPDri = 3993 + + ROUNDPSmi = 3994 + + ROUNDPSri = 3995 + + ROUNDSDmi = 3996 + + ROUNDSDmi_Int = 3997 + + ROUNDSDri = 3998 + + ROUNDSDri_Int = 3999 + + ROUNDSSmi = 4000 + + ROUNDSSmi_Int = 4001 + + ROUNDSSri = 4002 + + ROUNDSSri_Int = 4003 + + RSM = 4004 + + RSQRTPSm = 4005 + + RSQRTPSr = 4006 + + RSQRTSSm = 4007 + + RSQRTSSm_Int = 4008 + + RSQRTSSr = 4009 + + RSQRTSSr_Int = 4010 + + RSTORSSP = 4011 + + SAHF = 4012 + + SALC = 4013 + + SAR16m1 = 4014 + + SAR16m1_EVEX = 4015 + + SAR16m1_ND = 4016 + + SAR16m1_NF = 4017 + + SAR16m1_NF_ND = 4018 + + SAR16mCL = 4019 + + SAR16mCL_EVEX = 4020 + + SAR16mCL_ND = 4021 + + SAR16mCL_NF = 4022 + + SAR16mCL_NF_ND = 4023 + + SAR16mi = 4024 + + SAR16mi_EVEX = 4025 + + SAR16mi_ND = 4026 + + SAR16mi_NF = 4027 + + SAR16mi_NF_ND = 4028 + + SAR16r1 = 4029 + + SAR16r1_EVEX = 4030 + + SAR16r1_ND = 4031 + + SAR16r1_NF = 4032 + + SAR16r1_NF_ND = 4033 + + SAR16rCL = 4034 + + SAR16rCL_EVEX = 4035 + + SAR16rCL_ND = 4036 + + SAR16rCL_NF = 4037 + + SAR16rCL_NF_ND = 4038 + + SAR16ri = 4039 + + SAR16ri_EVEX = 4040 + + SAR16ri_ND = 4041 + + SAR16ri_NF = 4042 + + SAR16ri_NF_ND = 4043 + + SAR32m1 = 4044 + + SAR32m1_EVEX = 4045 + + SAR32m1_ND = 4046 + + SAR32m1_NF = 4047 + + SAR32m1_NF_ND = 4048 + + SAR32mCL = 4049 + + SAR32mCL_EVEX = 4050 + + SAR32mCL_ND = 4051 + + SAR32mCL_NF = 4052 + + SAR32mCL_NF_ND = 4053 + + SAR32mi = 4054 + + SAR32mi_EVEX = 4055 + + SAR32mi_ND = 4056 + + SAR32mi_NF = 4057 + + SAR32mi_NF_ND = 4058 + + SAR32r1 = 4059 + + SAR32r1_EVEX = 4060 + + SAR32r1_ND = 4061 + + SAR32r1_NF = 4062 + + SAR32r1_NF_ND = 4063 + + SAR32rCL = 4064 + + SAR32rCL_EVEX = 4065 + + SAR32rCL_ND = 4066 + + SAR32rCL_NF = 4067 + + SAR32rCL_NF_ND = 4068 + + SAR32ri = 4069 + + SAR32ri_EVEX = 4070 + + SAR32ri_ND = 4071 + + SAR32ri_NF = 4072 + + SAR32ri_NF_ND = 4073 + + SAR64m1 = 4074 + + SAR64m1_EVEX = 4075 + + SAR64m1_ND = 4076 + + SAR64m1_NF = 4077 + + SAR64m1_NF_ND = 4078 + + SAR64mCL = 4079 + + SAR64mCL_EVEX = 4080 + + SAR64mCL_ND = 4081 + + SAR64mCL_NF = 4082 + + SAR64mCL_NF_ND = 4083 + + SAR64mi = 4084 + + SAR64mi_EVEX = 4085 + + SAR64mi_ND = 4086 + + SAR64mi_NF = 4087 + + SAR64mi_NF_ND = 4088 + + SAR64r1 = 4089 + + SAR64r1_EVEX = 4090 + + SAR64r1_ND = 4091 + + SAR64r1_NF = 4092 + + SAR64r1_NF_ND = 4093 + + SAR64rCL = 4094 + + SAR64rCL_EVEX = 4095 + + SAR64rCL_ND = 4096 + + SAR64rCL_NF = 4097 + + SAR64rCL_NF_ND = 4098 + + SAR64ri = 4099 + + SAR64ri_EVEX = 4100 + + SAR64ri_ND = 4101 + + SAR64ri_NF = 4102 + + SAR64ri_NF_ND = 4103 + + SAR8m1 = 4104 + + SAR8m1_EVEX = 4105 + + SAR8m1_ND = 4106 + + SAR8m1_NF = 4107 + + SAR8m1_NF_ND = 4108 + + SAR8mCL = 4109 + + SAR8mCL_EVEX = 4110 + + SAR8mCL_ND = 4111 + + SAR8mCL_NF = 4112 + + SAR8mCL_NF_ND = 4113 + + SAR8mi = 4114 + + SAR8mi_EVEX = 4115 + + SAR8mi_ND = 4116 + + SAR8mi_NF = 4117 + + SAR8mi_NF_ND = 4118 + + SAR8r1 = 4119 + + SAR8r1_EVEX = 4120 + + SAR8r1_ND = 4121 + + SAR8r1_NF = 4122 + + SAR8r1_NF_ND = 4123 + + SAR8rCL = 4124 + + SAR8rCL_EVEX = 4125 + + SAR8rCL_ND = 4126 + + SAR8rCL_NF = 4127 + + SAR8rCL_NF_ND = 4128 + + SAR8ri = 4129 + + SAR8ri_EVEX = 4130 + + SAR8ri_ND = 4131 + + SAR8ri_NF = 4132 + + SAR8ri_NF_ND = 4133 + + SARX32rm = 4134 + + SARX32rm_EVEX = 4135 + + SARX32rr = 4136 + + SARX32rr_EVEX = 4137 + + SARX64rm = 4138 + + SARX64rm_EVEX = 4139 + + SARX64rr = 4140 + + SARX64rr_EVEX = 4141 + + SAVEPREVSSP = 4142 + + SBB16i16 = 4143 + + SBB16mi = 4144 + + SBB16mi8 = 4145 + + SBB16mi8_EVEX = 4146 + + SBB16mi8_ND = 4147 + + SBB16mi_EVEX = 4148 + + SBB16mi_ND = 4149 + + SBB16mr = 4150 + + SBB16mr_EVEX = 4151 + + SBB16mr_ND = 4152 + + SBB16ri = 4153 + + SBB16ri8 = 4154 + + SBB16ri8_EVEX = 4155 + + SBB16ri8_ND = 4156 + + SBB16ri_EVEX = 4157 + + SBB16ri_ND = 4158 + + SBB16rm = 4159 + + SBB16rm_EVEX = 4160 + + SBB16rm_ND = 4161 + + SBB16rr = 4162 + + SBB16rr_EVEX = 4163 + + SBB16rr_EVEX_REV = 4164 + + SBB16rr_ND = 4165 + + SBB16rr_ND_REV = 4166 + + SBB16rr_REV = 4167 + + SBB32i32 = 4168 + + SBB32mi = 4169 + + SBB32mi8 = 4170 + + SBB32mi8_EVEX = 4171 + + SBB32mi8_ND = 4172 + + SBB32mi_EVEX = 4173 + + SBB32mi_ND = 4174 + + SBB32mr = 4175 + + SBB32mr_EVEX = 4176 + + SBB32mr_ND = 4177 + + SBB32ri = 4178 + + SBB32ri8 = 4179 + + SBB32ri8_EVEX = 4180 + + SBB32ri8_ND = 4181 + + SBB32ri_EVEX = 4182 + + SBB32ri_ND = 4183 + + SBB32rm = 4184 + + SBB32rm_EVEX = 4185 + + SBB32rm_ND = 4186 + + SBB32rr = 4187 + + SBB32rr_EVEX = 4188 + + SBB32rr_EVEX_REV = 4189 + + SBB32rr_ND = 4190 + + SBB32rr_ND_REV = 4191 + + SBB32rr_REV = 4192 + + SBB64i32 = 4193 + + SBB64mi32 = 4194 + + SBB64mi32_EVEX = 4195 + + SBB64mi32_ND = 4196 + + SBB64mi8 = 4197 + + SBB64mi8_EVEX = 4198 + + SBB64mi8_ND = 4199 + + SBB64mr = 4200 + + SBB64mr_EVEX = 4201 + + SBB64mr_ND = 4202 + + SBB64ri32 = 4203 + + SBB64ri32_EVEX = 4204 + + SBB64ri32_ND = 4205 + + SBB64ri8 = 4206 + + SBB64ri8_EVEX = 4207 + + SBB64ri8_ND = 4208 + + SBB64rm = 4209 + + SBB64rm_EVEX = 4210 + + SBB64rm_ND = 4211 + + SBB64rr = 4212 + + SBB64rr_EVEX = 4213 + + SBB64rr_EVEX_REV = 4214 + + SBB64rr_ND = 4215 + + SBB64rr_ND_REV = 4216 + + SBB64rr_REV = 4217 + + SBB8i8 = 4218 + + SBB8mi = 4219 + + SBB8mi8 = 4220 + + SBB8mi_EVEX = 4221 + + SBB8mi_ND = 4222 + + SBB8mr = 4223 + + SBB8mr_EVEX = 4224 + + SBB8mr_ND = 4225 + + SBB8ri = 4226 + + SBB8ri8 = 4227 + + SBB8ri_EVEX = 4228 + + SBB8ri_ND = 4229 + + SBB8rm = 4230 + + SBB8rm_EVEX = 4231 + + SBB8rm_ND = 4232 + + SBB8rr = 4233 + + SBB8rr_EVEX = 4234 + + SBB8rr_EVEX_REV = 4235 + + SBB8rr_ND = 4236 + + SBB8rr_ND_REV = 4237 + + SBB8rr_REV = 4238 + + SCASB = 4239 + + SCASL = 4240 + + SCASQ = 4241 + + SCASW = 4242 + + SEAMCALL = 4243 + + SEAMOPS = 4244 + + SEAMRET = 4245 + + SEG_ALLOCA_32 = 4246 + + SEG_ALLOCA_64 = 4247 + + SENDUIPI = 4248 + + SERIALIZE = 4249 + + SETCCm = 4250 + + SETCCm_EVEX = 4251 + + SETCCr = 4252 + + SETCCr_EVEX = 4253 + + SETSSBSY = 4254 + + SETZUCCm = 4255 + + SETZUCCr = 4256 + + SFENCE = 4257 + + SGDT16m = 4258 + + SGDT32m = 4259 + + SGDT64m = 4260 + + SHA1MSG1rm = 4261 + + SHA1MSG1rr = 4262 + + SHA1MSG2rm = 4263 + + SHA1MSG2rr = 4264 + + SHA1NEXTErm = 4265 + + SHA1NEXTErr = 4266 + + SHA1RNDS4rmi = 4267 + + SHA1RNDS4rri = 4268 + + SHA256MSG1rm = 4269 + + SHA256MSG1rr = 4270 + + SHA256MSG2rm = 4271 + + SHA256MSG2rr = 4272 + + SHA256RNDS2rm = 4273 + + SHA256RNDS2rr = 4274 + + SHL16m1 = 4275 + + SHL16m1_EVEX = 4276 + + SHL16m1_ND = 4277 + + SHL16m1_NF = 4278 + + SHL16m1_NF_ND = 4279 + + SHL16mCL = 4280 + + SHL16mCL_EVEX = 4281 + + SHL16mCL_ND = 4282 + + SHL16mCL_NF = 4283 + + SHL16mCL_NF_ND = 4284 + + SHL16mi = 4285 + + SHL16mi_EVEX = 4286 + + SHL16mi_ND = 4287 + + SHL16mi_NF = 4288 + + SHL16mi_NF_ND = 4289 + + SHL16r1 = 4290 + + SHL16r1_EVEX = 4291 + + SHL16r1_ND = 4292 + + SHL16r1_NF = 4293 + + SHL16r1_NF_ND = 4294 + + SHL16rCL = 4295 + + SHL16rCL_EVEX = 4296 + + SHL16rCL_ND = 4297 + + SHL16rCL_NF = 4298 + + SHL16rCL_NF_ND = 4299 + + SHL16ri = 4300 + + SHL16ri_EVEX = 4301 + + SHL16ri_ND = 4302 + + SHL16ri_NF = 4303 + + SHL16ri_NF_ND = 4304 + + SHL32m1 = 4305 + + SHL32m1_EVEX = 4306 + + SHL32m1_ND = 4307 + + SHL32m1_NF = 4308 + + SHL32m1_NF_ND = 4309 + + SHL32mCL = 4310 + + SHL32mCL_EVEX = 4311 + + SHL32mCL_ND = 4312 + + SHL32mCL_NF = 4313 + + SHL32mCL_NF_ND = 4314 + + SHL32mi = 4315 + + SHL32mi_EVEX = 4316 + + SHL32mi_ND = 4317 + + SHL32mi_NF = 4318 + + SHL32mi_NF_ND = 4319 + + SHL32r1 = 4320 + + SHL32r1_EVEX = 4321 + + SHL32r1_ND = 4322 + + SHL32r1_NF = 4323 + + SHL32r1_NF_ND = 4324 + + SHL32rCL = 4325 + + SHL32rCL_EVEX = 4326 + + SHL32rCL_ND = 4327 + + SHL32rCL_NF = 4328 + + SHL32rCL_NF_ND = 4329 + + SHL32ri = 4330 + + SHL32ri_EVEX = 4331 + + SHL32ri_ND = 4332 + + SHL32ri_NF = 4333 + + SHL32ri_NF_ND = 4334 + + SHL64m1 = 4335 + + SHL64m1_EVEX = 4336 + + SHL64m1_ND = 4337 + + SHL64m1_NF = 4338 + + SHL64m1_NF_ND = 4339 + + SHL64mCL = 4340 + + SHL64mCL_EVEX = 4341 + + SHL64mCL_ND = 4342 + + SHL64mCL_NF = 4343 + + SHL64mCL_NF_ND = 4344 + + SHL64mi = 4345 + + SHL64mi_EVEX = 4346 + + SHL64mi_ND = 4347 + + SHL64mi_NF = 4348 + + SHL64mi_NF_ND = 4349 + + SHL64r1 = 4350 + + SHL64r1_EVEX = 4351 + + SHL64r1_ND = 4352 + + SHL64r1_NF = 4353 + + SHL64r1_NF_ND = 4354 + + SHL64rCL = 4355 + + SHL64rCL_EVEX = 4356 + + SHL64rCL_ND = 4357 + + SHL64rCL_NF = 4358 + + SHL64rCL_NF_ND = 4359 + + SHL64ri = 4360 + + SHL64ri_EVEX = 4361 + + SHL64ri_ND = 4362 + + SHL64ri_NF = 4363 + + SHL64ri_NF_ND = 4364 + + SHL8m1 = 4365 + + SHL8m1_EVEX = 4366 + + SHL8m1_ND = 4367 + + SHL8m1_NF = 4368 + + SHL8m1_NF_ND = 4369 + + SHL8mCL = 4370 + + SHL8mCL_EVEX = 4371 + + SHL8mCL_ND = 4372 + + SHL8mCL_NF = 4373 + + SHL8mCL_NF_ND = 4374 + + SHL8mi = 4375 + + SHL8mi_EVEX = 4376 + + SHL8mi_ND = 4377 + + SHL8mi_NF = 4378 + + SHL8mi_NF_ND = 4379 + + SHL8r1 = 4380 + + SHL8r1_EVEX = 4381 + + SHL8r1_ND = 4382 + + SHL8r1_NF = 4383 + + SHL8r1_NF_ND = 4384 + + SHL8rCL = 4385 + + SHL8rCL_EVEX = 4386 + + SHL8rCL_ND = 4387 + + SHL8rCL_NF = 4388 + + SHL8rCL_NF_ND = 4389 + + SHL8ri = 4390 + + SHL8ri_EVEX = 4391 + + SHL8ri_ND = 4392 + + SHL8ri_NF = 4393 + + SHL8ri_NF_ND = 4394 + + SHLD16mrCL = 4395 + + SHLD16mrCL_EVEX = 4396 + + SHLD16mrCL_ND = 4397 + + SHLD16mrCL_NF = 4398 + + SHLD16mrCL_NF_ND = 4399 + + SHLD16mri8 = 4400 + + SHLD16mri8_EVEX = 4401 + + SHLD16mri8_ND = 4402 + + SHLD16mri8_NF = 4403 + + SHLD16mri8_NF_ND = 4404 + + SHLD16rrCL = 4405 + + SHLD16rrCL_EVEX = 4406 + + SHLD16rrCL_ND = 4407 + + SHLD16rrCL_NF = 4408 + + SHLD16rrCL_NF_ND = 4409 + + SHLD16rri8 = 4410 + + SHLD16rri8_EVEX = 4411 + + SHLD16rri8_ND = 4412 + + SHLD16rri8_NF = 4413 + + SHLD16rri8_NF_ND = 4414 + + SHLD32mrCL = 4415 + + SHLD32mrCL_EVEX = 4416 + + SHLD32mrCL_ND = 4417 + + SHLD32mrCL_NF = 4418 + + SHLD32mrCL_NF_ND = 4419 + + SHLD32mri8 = 4420 + + SHLD32mri8_EVEX = 4421 + + SHLD32mri8_ND = 4422 + + SHLD32mri8_NF = 4423 + + SHLD32mri8_NF_ND = 4424 + + SHLD32rrCL = 4425 + + SHLD32rrCL_EVEX = 4426 + + SHLD32rrCL_ND = 4427 + + SHLD32rrCL_NF = 4428 + + SHLD32rrCL_NF_ND = 4429 + + SHLD32rri8 = 4430 + + SHLD32rri8_EVEX = 4431 + + SHLD32rri8_ND = 4432 + + SHLD32rri8_NF = 4433 + + SHLD32rri8_NF_ND = 4434 + + SHLD64mrCL = 4435 + + SHLD64mrCL_EVEX = 4436 + + SHLD64mrCL_ND = 4437 + + SHLD64mrCL_NF = 4438 + + SHLD64mrCL_NF_ND = 4439 + + SHLD64mri8 = 4440 + + SHLD64mri8_EVEX = 4441 + + SHLD64mri8_ND = 4442 + + SHLD64mri8_NF = 4443 + + SHLD64mri8_NF_ND = 4444 + + SHLD64rrCL = 4445 + + SHLD64rrCL_EVEX = 4446 + + SHLD64rrCL_ND = 4447 + + SHLD64rrCL_NF = 4448 + + SHLD64rrCL_NF_ND = 4449 + + SHLD64rri8 = 4450 + + SHLD64rri8_EVEX = 4451 + + SHLD64rri8_ND = 4452 + + SHLD64rri8_NF = 4453 + + SHLD64rri8_NF_ND = 4454 + + SHLX32rm = 4455 + + SHLX32rm_EVEX = 4456 + + SHLX32rr = 4457 + + SHLX32rr_EVEX = 4458 + + SHLX64rm = 4459 + + SHLX64rm_EVEX = 4460 + + SHLX64rr = 4461 + + SHLX64rr_EVEX = 4462 + + SHR16m1 = 4463 + + SHR16m1_EVEX = 4464 + + SHR16m1_ND = 4465 + + SHR16m1_NF = 4466 + + SHR16m1_NF_ND = 4467 + + SHR16mCL = 4468 + + SHR16mCL_EVEX = 4469 + + SHR16mCL_ND = 4470 + + SHR16mCL_NF = 4471 + + SHR16mCL_NF_ND = 4472 + + SHR16mi = 4473 + + SHR16mi_EVEX = 4474 + + SHR16mi_ND = 4475 + + SHR16mi_NF = 4476 + + SHR16mi_NF_ND = 4477 + + SHR16r1 = 4478 + + SHR16r1_EVEX = 4479 + + SHR16r1_ND = 4480 + + SHR16r1_NF = 4481 + + SHR16r1_NF_ND = 4482 + + SHR16rCL = 4483 + + SHR16rCL_EVEX = 4484 + + SHR16rCL_ND = 4485 + + SHR16rCL_NF = 4486 + + SHR16rCL_NF_ND = 4487 + + SHR16ri = 4488 + + SHR16ri_EVEX = 4489 + + SHR16ri_ND = 4490 + + SHR16ri_NF = 4491 + + SHR16ri_NF_ND = 4492 + + SHR32m1 = 4493 + + SHR32m1_EVEX = 4494 + + SHR32m1_ND = 4495 + + SHR32m1_NF = 4496 + + SHR32m1_NF_ND = 4497 + + SHR32mCL = 4498 + + SHR32mCL_EVEX = 4499 + + SHR32mCL_ND = 4500 + + SHR32mCL_NF = 4501 + + SHR32mCL_NF_ND = 4502 + + SHR32mi = 4503 + + SHR32mi_EVEX = 4504 + + SHR32mi_ND = 4505 + + SHR32mi_NF = 4506 + + SHR32mi_NF_ND = 4507 + + SHR32r1 = 4508 + + SHR32r1_EVEX = 4509 + + SHR32r1_ND = 4510 + + SHR32r1_NF = 4511 + + SHR32r1_NF_ND = 4512 + + SHR32rCL = 4513 + + SHR32rCL_EVEX = 4514 + + SHR32rCL_ND = 4515 + + SHR32rCL_NF = 4516 + + SHR32rCL_NF_ND = 4517 + + SHR32ri = 4518 + + SHR32ri_EVEX = 4519 + + SHR32ri_ND = 4520 + + SHR32ri_NF = 4521 + + SHR32ri_NF_ND = 4522 + + SHR64m1 = 4523 + + SHR64m1_EVEX = 4524 + + SHR64m1_ND = 4525 + + SHR64m1_NF = 4526 + + SHR64m1_NF_ND = 4527 + + SHR64mCL = 4528 + + SHR64mCL_EVEX = 4529 + + SHR64mCL_ND = 4530 + + SHR64mCL_NF = 4531 + + SHR64mCL_NF_ND = 4532 + + SHR64mi = 4533 + + SHR64mi_EVEX = 4534 + + SHR64mi_ND = 4535 + + SHR64mi_NF = 4536 + + SHR64mi_NF_ND = 4537 + + SHR64r1 = 4538 + + SHR64r1_EVEX = 4539 + + SHR64r1_ND = 4540 + + SHR64r1_NF = 4541 + + SHR64r1_NF_ND = 4542 + + SHR64rCL = 4543 + + SHR64rCL_EVEX = 4544 + + SHR64rCL_ND = 4545 + + SHR64rCL_NF = 4546 + + SHR64rCL_NF_ND = 4547 + + SHR64ri = 4548 + + SHR64ri_EVEX = 4549 + + SHR64ri_ND = 4550 + + SHR64ri_NF = 4551 + + SHR64ri_NF_ND = 4552 + + SHR8m1 = 4553 + + SHR8m1_EVEX = 4554 + + SHR8m1_ND = 4555 + + SHR8m1_NF = 4556 + + SHR8m1_NF_ND = 4557 + + SHR8mCL = 4558 + + SHR8mCL_EVEX = 4559 + + SHR8mCL_ND = 4560 + + SHR8mCL_NF = 4561 + + SHR8mCL_NF_ND = 4562 + + SHR8mi = 4563 + + SHR8mi_EVEX = 4564 + + SHR8mi_ND = 4565 + + SHR8mi_NF = 4566 + + SHR8mi_NF_ND = 4567 + + SHR8r1 = 4568 + + SHR8r1_EVEX = 4569 + + SHR8r1_ND = 4570 + + SHR8r1_NF = 4571 + + SHR8r1_NF_ND = 4572 + + SHR8rCL = 4573 + + SHR8rCL_EVEX = 4574 + + SHR8rCL_ND = 4575 + + SHR8rCL_NF = 4576 + + SHR8rCL_NF_ND = 4577 + + SHR8ri = 4578 + + SHR8ri_EVEX = 4579 + + SHR8ri_ND = 4580 + + SHR8ri_NF = 4581 + + SHR8ri_NF_ND = 4582 + + SHRD16mrCL = 4583 + + SHRD16mrCL_EVEX = 4584 + + SHRD16mrCL_ND = 4585 + + SHRD16mrCL_NF = 4586 + + SHRD16mrCL_NF_ND = 4587 + + SHRD16mri8 = 4588 + + SHRD16mri8_EVEX = 4589 + + SHRD16mri8_ND = 4590 + + SHRD16mri8_NF = 4591 + + SHRD16mri8_NF_ND = 4592 + + SHRD16rrCL = 4593 + + SHRD16rrCL_EVEX = 4594 + + SHRD16rrCL_ND = 4595 + + SHRD16rrCL_NF = 4596 + + SHRD16rrCL_NF_ND = 4597 + + SHRD16rri8 = 4598 + + SHRD16rri8_EVEX = 4599 + + SHRD16rri8_ND = 4600 + + SHRD16rri8_NF = 4601 + + SHRD16rri8_NF_ND = 4602 + + SHRD32mrCL = 4603 + + SHRD32mrCL_EVEX = 4604 + + SHRD32mrCL_ND = 4605 + + SHRD32mrCL_NF = 4606 + + SHRD32mrCL_NF_ND = 4607 + + SHRD32mri8 = 4608 + + SHRD32mri8_EVEX = 4609 + + SHRD32mri8_ND = 4610 + + SHRD32mri8_NF = 4611 + + SHRD32mri8_NF_ND = 4612 + + SHRD32rrCL = 4613 + + SHRD32rrCL_EVEX = 4614 + + SHRD32rrCL_ND = 4615 + + SHRD32rrCL_NF = 4616 + + SHRD32rrCL_NF_ND = 4617 + + SHRD32rri8 = 4618 + + SHRD32rri8_EVEX = 4619 + + SHRD32rri8_ND = 4620 + + SHRD32rri8_NF = 4621 + + SHRD32rri8_NF_ND = 4622 + + SHRD64mrCL = 4623 + + SHRD64mrCL_EVEX = 4624 + + SHRD64mrCL_ND = 4625 + + SHRD64mrCL_NF = 4626 + + SHRD64mrCL_NF_ND = 4627 + + SHRD64mri8 = 4628 + + SHRD64mri8_EVEX = 4629 + + SHRD64mri8_ND = 4630 + + SHRD64mri8_NF = 4631 + + SHRD64mri8_NF_ND = 4632 + + SHRD64rrCL = 4633 + + SHRD64rrCL_EVEX = 4634 + + SHRD64rrCL_ND = 4635 + + SHRD64rrCL_NF = 4636 + + SHRD64rrCL_NF_ND = 4637 + + SHRD64rri8 = 4638 + + SHRD64rri8_EVEX = 4639 + + SHRD64rri8_ND = 4640 + + SHRD64rri8_NF = 4641 + + SHRD64rri8_NF_ND = 4642 + + SHRX32rm = 4643 + + SHRX32rm_EVEX = 4644 + + SHRX32rr = 4645 + + SHRX32rr_EVEX = 4646 + + SHRX64rm = 4647 + + SHRX64rm_EVEX = 4648 + + SHRX64rr = 4649 + + SHRX64rr_EVEX = 4650 + + SHUFPDrmi = 4651 + + SHUFPDrri = 4652 + + SHUFPSrmi = 4653 + + SHUFPSrri = 4654 + + SIDT16m = 4655 + + SIDT32m = 4656 + + SIDT64m = 4657 + + SKINIT = 4658 + + SLDT16m = 4659 + + SLDT16r = 4660 + + SLDT32r = 4661 + + SLDT64r = 4662 + + SLWPCB = 4663 + + SLWPCB64 = 4664 + + SMSW16m = 4665 + + SMSW16r = 4666 + + SMSW32r = 4667 + + SMSW64r = 4668 + + SQRTPDm = 4669 + + SQRTPDr = 4670 + + SQRTPSm = 4671 + + SQRTPSr = 4672 + + SQRTSDm = 4673 + + SQRTSDm_Int = 4674 + + SQRTSDr = 4675 + + SQRTSDr_Int = 4676 + + SQRTSSm = 4677 + + SQRTSSm_Int = 4678 + + SQRTSSr = 4679 + + SQRTSSr_Int = 4680 + + SQRT_F = 4681 + + SQRT_Fp32 = 4682 + + SQRT_Fp64 = 4683 + + SQRT_Fp80 = 4684 + + SS_PREFIX = 4685 + + STAC = 4686 + + STACKALLOC_W_PROBING = 4687 + + STC = 4688 + + STD = 4689 + + STGI = 4690 + + STI = 4691 + + STMXCSR = 4692 + + STOSB = 4693 + + STOSL = 4694 + + STOSQ = 4695 + + STOSW = 4696 + + STR16r = 4697 + + STR32r = 4698 + + STR64r = 4699 + + STRm = 4700 + + STTILECFG = 4701 + + STTILECFG_EVEX = 4702 + + STUI = 4703 + + ST_F32m = 4704 + + ST_F64m = 4705 + + ST_FP32m = 4706 + + ST_FP64m = 4707 + + ST_FP80m = 4708 + + ST_FPrr = 4709 + + ST_Fp32m = 4710 + + ST_Fp64m = 4711 + + ST_Fp64m32 = 4712 + + ST_Fp80m32 = 4713 + + ST_Fp80m64 = 4714 + + ST_FpP32m = 4715 + + ST_FpP64m = 4716 + + ST_FpP64m32 = 4717 + + ST_FpP80m = 4718 + + ST_FpP80m32 = 4719 + + ST_FpP80m64 = 4720 + + ST_Frr = 4721 + + SUB16i16 = 4722 + + SUB16mi = 4723 + + SUB16mi8 = 4724 + + SUB16mi8_EVEX = 4725 + + SUB16mi8_ND = 4726 + + SUB16mi8_NF = 4727 + + SUB16mi8_NF_ND = 4728 + + SUB16mi_EVEX = 4729 + + SUB16mi_ND = 4730 + + SUB16mi_NF = 4731 + + SUB16mi_NF_ND = 4732 + + SUB16mr = 4733 + + SUB16mr_EVEX = 4734 + + SUB16mr_ND = 4735 + + SUB16mr_NF = 4736 + + SUB16mr_NF_ND = 4737 + + SUB16ri = 4738 + + SUB16ri8 = 4739 + + SUB16ri8_EVEX = 4740 + + SUB16ri8_ND = 4741 + + SUB16ri8_NF = 4742 + + SUB16ri8_NF_ND = 4743 + + SUB16ri_EVEX = 4744 + + SUB16ri_ND = 4745 + + SUB16ri_NF = 4746 + + SUB16ri_NF_ND = 4747 + + SUB16rm = 4748 + + SUB16rm_EVEX = 4749 + + SUB16rm_ND = 4750 + + SUB16rm_NF = 4751 + + SUB16rm_NF_ND = 4752 + + SUB16rr = 4753 + + SUB16rr_EVEX = 4754 + + SUB16rr_EVEX_REV = 4755 + + SUB16rr_ND = 4756 + + SUB16rr_ND_REV = 4757 + + SUB16rr_NF = 4758 + + SUB16rr_NF_ND = 4759 + + SUB16rr_NF_ND_REV = 4760 + + SUB16rr_NF_REV = 4761 + + SUB16rr_REV = 4762 + + SUB32i32 = 4763 + + SUB32mi = 4764 + + SUB32mi8 = 4765 + + SUB32mi8_EVEX = 4766 + + SUB32mi8_ND = 4767 + + SUB32mi8_NF = 4768 + + SUB32mi8_NF_ND = 4769 + + SUB32mi_EVEX = 4770 + + SUB32mi_ND = 4771 + + SUB32mi_NF = 4772 + + SUB32mi_NF_ND = 4773 + + SUB32mr = 4774 + + SUB32mr_EVEX = 4775 + + SUB32mr_ND = 4776 + + SUB32mr_NF = 4777 + + SUB32mr_NF_ND = 4778 + + SUB32ri = 4779 + + SUB32ri8 = 4780 + + SUB32ri8_EVEX = 4781 + + SUB32ri8_ND = 4782 + + SUB32ri8_NF = 4783 + + SUB32ri8_NF_ND = 4784 + + SUB32ri_EVEX = 4785 + + SUB32ri_ND = 4786 + + SUB32ri_NF = 4787 + + SUB32ri_NF_ND = 4788 + + SUB32rm = 4789 + + SUB32rm_EVEX = 4790 + + SUB32rm_ND = 4791 + + SUB32rm_NF = 4792 + + SUB32rm_NF_ND = 4793 + + SUB32rr = 4794 + + SUB32rr_EVEX = 4795 + + SUB32rr_EVEX_REV = 4796 + + SUB32rr_ND = 4797 + + SUB32rr_ND_REV = 4798 + + SUB32rr_NF = 4799 + + SUB32rr_NF_ND = 4800 + + SUB32rr_NF_ND_REV = 4801 + + SUB32rr_NF_REV = 4802 + + SUB32rr_REV = 4803 + + SUB64i32 = 4804 + + SUB64mi32 = 4805 + + SUB64mi32_EVEX = 4806 + + SUB64mi32_ND = 4807 + + SUB64mi32_NF = 4808 + + SUB64mi32_NF_ND = 4809 + + SUB64mi8 = 4810 + + SUB64mi8_EVEX = 4811 + + SUB64mi8_ND = 4812 + + SUB64mi8_NF = 4813 + + SUB64mi8_NF_ND = 4814 + + SUB64mr = 4815 + + SUB64mr_EVEX = 4816 + + SUB64mr_ND = 4817 + + SUB64mr_NF = 4818 + + SUB64mr_NF_ND = 4819 + + SUB64ri32 = 4820 + + SUB64ri32_EVEX = 4821 + + SUB64ri32_ND = 4822 + + SUB64ri32_NF = 4823 + + SUB64ri32_NF_ND = 4824 + + SUB64ri8 = 4825 + + SUB64ri8_EVEX = 4826 + + SUB64ri8_ND = 4827 + + SUB64ri8_NF = 4828 + + SUB64ri8_NF_ND = 4829 + + SUB64rm = 4830 + + SUB64rm_EVEX = 4831 + + SUB64rm_ND = 4832 + + SUB64rm_NF = 4833 + + SUB64rm_NF_ND = 4834 + + SUB64rr = 4835 + + SUB64rr_EVEX = 4836 + + SUB64rr_EVEX_REV = 4837 + + SUB64rr_ND = 4838 + + SUB64rr_ND_REV = 4839 + + SUB64rr_NF = 4840 + + SUB64rr_NF_ND = 4841 + + SUB64rr_NF_ND_REV = 4842 + + SUB64rr_NF_REV = 4843 + + SUB64rr_REV = 4844 + + SUB8i8 = 4845 + + SUB8mi = 4846 + + SUB8mi8 = 4847 + + SUB8mi_EVEX = 4848 + + SUB8mi_ND = 4849 + + SUB8mi_NF = 4850 + + SUB8mi_NF_ND = 4851 + + SUB8mr = 4852 + + SUB8mr_EVEX = 4853 + + SUB8mr_ND = 4854 + + SUB8mr_NF = 4855 + + SUB8mr_NF_ND = 4856 + + SUB8ri = 4857 + + SUB8ri8 = 4858 + + SUB8ri_EVEX = 4859 + + SUB8ri_ND = 4860 + + SUB8ri_NF = 4861 + + SUB8ri_NF_ND = 4862 + + SUB8rm = 4863 + + SUB8rm_EVEX = 4864 + + SUB8rm_ND = 4865 + + SUB8rm_NF = 4866 + + SUB8rm_NF_ND = 4867 + + SUB8rr = 4868 + + SUB8rr_EVEX = 4869 + + SUB8rr_EVEX_REV = 4870 + + SUB8rr_ND = 4871 + + SUB8rr_ND_REV = 4872 + + SUB8rr_NF = 4873 + + SUB8rr_NF_ND = 4874 + + SUB8rr_NF_ND_REV = 4875 + + SUB8rr_NF_REV = 4876 + + SUB8rr_REV = 4877 + + SUBPDrm = 4878 + + SUBPDrr = 4879 + + SUBPSrm = 4880 + + SUBPSrr = 4881 + + SUBR_F32m = 4882 + + SUBR_F64m = 4883 + + SUBR_FI16m = 4884 + + SUBR_FI32m = 4885 + + SUBR_FPrST0 = 4886 + + SUBR_FST0r = 4887 + + SUBR_Fp32m = 4888 + + SUBR_Fp64m = 4889 + + SUBR_Fp64m32 = 4890 + + SUBR_Fp80m32 = 4891 + + SUBR_Fp80m64 = 4892 + + SUBR_FpI16m32 = 4893 + + SUBR_FpI16m64 = 4894 + + SUBR_FpI16m80 = 4895 + + SUBR_FpI32m32 = 4896 + + SUBR_FpI32m64 = 4897 + + SUBR_FpI32m80 = 4898 + + SUBR_FrST0 = 4899 + + SUBSDrm = 4900 + + SUBSDrm_Int = 4901 + + SUBSDrr = 4902 + + SUBSDrr_Int = 4903 + + SUBSSrm = 4904 + + SUBSSrm_Int = 4905 + + SUBSSrr = 4906 + + SUBSSrr_Int = 4907 + + SUB_F32m = 4908 + + SUB_F64m = 4909 + + SUB_FI16m = 4910 + + SUB_FI32m = 4911 + + SUB_FPrST0 = 4912 + + SUB_FST0r = 4913 + + SUB_Fp32 = 4914 + + SUB_Fp32m = 4915 + + SUB_Fp64 = 4916 + + SUB_Fp64m = 4917 + + SUB_Fp64m32 = 4918 + + SUB_Fp80 = 4919 + + SUB_Fp80m32 = 4920 + + SUB_Fp80m64 = 4921 + + SUB_FpI16m32 = 4922 + + SUB_FpI16m64 = 4923 + + SUB_FpI16m80 = 4924 + + SUB_FpI32m32 = 4925 + + SUB_FpI32m64 = 4926 + + SUB_FpI32m80 = 4927 + + SUB_FrST0 = 4928 + + SWAPGS = 4929 + + SYSCALL = 4930 + + SYSENTER = 4931 + + SYSEXIT = 4932 + + SYSEXIT64 = 4933 + + SYSRET = 4934 + + SYSRET64 = 4935 + + T1MSKC32rm = 4936 + + T1MSKC32rr = 4937 + + T1MSKC64rm = 4938 + + T1MSKC64rr = 4939 + + TAILJMPd = 4940 + + TAILJMPd64 = 4941 + + TAILJMPd64_CC = 4942 + + TAILJMPd_CC = 4943 + + TAILJMPm = 4944 + + TAILJMPm64 = 4945 + + TAILJMPm64_REX = 4946 + + TAILJMPr = 4947 + + TAILJMPr64 = 4948 + + TAILJMPr64_REX = 4949 + + TCMMIMFP16PS = 4950 + + TCMMRLFP16PS = 4951 + + TCRETURN_HIPE32ri = 4952 + + TCRETURN_WIN64ri = 4953 + + TCRETURN_WINmi64 = 4954 + + TCRETURNdi = 4955 + + TCRETURNdi64 = 4956 + + TCRETURNdi64cc = 4957 + + TCRETURNdicc = 4958 + + TCRETURNmi = 4959 + + TCRETURNmi64 = 4960 + + TCRETURNri = 4961 + + TCRETURNri64 = 4962 + + TCRETURNri64_ImpCall = 4963 + + TCVTROWD2PSrte = 4964 + + TCVTROWD2PSrti = 4965 + + TCVTROWPS2BF16Hrte = 4966 + + TCVTROWPS2BF16Hrti = 4967 + + TCVTROWPS2BF16Lrte = 4968 + + TCVTROWPS2BF16Lrti = 4969 + + TCVTROWPS2PHHrte = 4970 + + TCVTROWPS2PHHrti = 4971 + + TCVTROWPS2PHLrte = 4972 + + TCVTROWPS2PHLrti = 4973 + + TDCALL = 4974 + + TDPBF16PS = 4975 + + TDPBF8PS = 4976 + + TDPBHF8PS = 4977 + + TDPBSSD = 4978 + + TDPBSUD = 4979 + + TDPBUSD = 4980 + + TDPBUUD = 4981 + + TDPFP16PS = 4982 + + TDPHBF8PS = 4983 + + TDPHF8PS = 4984 + + TEST16i16 = 4985 + + TEST16mi = 4986 + + TEST16mr = 4987 + + TEST16ri = 4988 + + TEST16rr = 4989 + + TEST32i32 = 4990 + + TEST32mi = 4991 + + TEST32mr = 4992 + + TEST32ri = 4993 + + TEST32rr = 4994 + + TEST64i32 = 4995 + + TEST64mi32 = 4996 + + TEST64mr = 4997 + + TEST64ri32 = 4998 + + TEST64rr = 4999 + + TEST8i8 = 5000 + + TEST8mi = 5001 + + TEST8mr = 5002 + + TEST8ri = 5003 + + TEST8rr = 5004 + + TESTUI = 5005 + + TILELOADD = 5006 + + TILELOADDRS = 5007 + + TILELOADDRST1 = 5008 + + TILELOADDRST1_EVEX = 5009 + + TILELOADDRS_EVEX = 5010 + + TILELOADDT1 = 5011 + + TILELOADDT1_EVEX = 5012 + + TILELOADD_EVEX = 5013 + + TILEMOVROWrte = 5014 + + TILEMOVROWrti = 5015 + + TILERELEASE = 5016 + + TILESTORED = 5017 + + TILESTORED_EVEX = 5018 + + TILEZERO = 5019 + + TLBSYNC = 5020 + + TLSCall_32 = 5021 + + TLSCall_64 = 5022 + + TLS_addr32 = 5023 + + TLS_addr64 = 5024 + + TLS_addrX32 = 5025 + + TLS_base_addr32 = 5026 + + TLS_base_addr64 = 5027 + + TLS_base_addrX32 = 5028 + + TLS_desc32 = 5029 + + TLS_desc64 = 5030 + + TMMULTF32PS = 5031 + + TPAUSE = 5032 + + TRAP = 5033 + + TST_F = 5034 + + TST_Fp32 = 5035 + + TST_Fp64 = 5036 + + TST_Fp80 = 5037 + + TZCNT16rm = 5038 + + TZCNT16rm_EVEX = 5039 + + TZCNT16rm_NF = 5040 + + TZCNT16rr = 5041 + + TZCNT16rr_EVEX = 5042 + + TZCNT16rr_NF = 5043 + + TZCNT32rm = 5044 + + TZCNT32rm_EVEX = 5045 + + TZCNT32rm_NF = 5046 + + TZCNT32rr = 5047 + + TZCNT32rr_EVEX = 5048 + + TZCNT32rr_NF = 5049 + + TZCNT64rm = 5050 + + TZCNT64rm_EVEX = 5051 + + TZCNT64rm_NF = 5052 + + TZCNT64rr = 5053 + + TZCNT64rr_EVEX = 5054 + + TZCNT64rr_NF = 5055 + + TZMSK32rm = 5056 + + TZMSK32rr = 5057 + + TZMSK64rm = 5058 + + TZMSK64rr = 5059 + + UBSAN_UD1 = 5060 + + UCOMISDrm = 5061 + + UCOMISDrm_Int = 5062 + + UCOMISDrr = 5063 + + UCOMISDrr_Int = 5064 + + UCOMISSrm = 5065 + + UCOMISSrm_Int = 5066 + + UCOMISSrr = 5067 + + UCOMISSrr_Int = 5068 + + UCOM_FIPr = 5069 + + UCOM_FIr = 5070 + + UCOM_FPPr = 5071 + + UCOM_FPr = 5072 + + UCOM_FpIr32 = 5073 + + UCOM_FpIr64 = 5074 + + UCOM_FpIr80 = 5075 + + UCOM_Fpr32 = 5076 + + UCOM_Fpr64 = 5077 + + UCOM_Fpr80 = 5078 + + UCOM_Fr = 5079 + + UD1Lm = 5080 + + UD1Lr = 5081 + + UD1Qm = 5082 + + UD1Qr = 5083 + + UD1Wm = 5084 + + UD1Wr = 5085 + + UIRET = 5086 + + UMONITOR16 = 5087 + + UMONITOR32 = 5088 + + UMONITOR64 = 5089 + + UMWAIT = 5090 + + UNPCKHPDrm = 5091 + + UNPCKHPDrr = 5092 + + UNPCKHPSrm = 5093 + + UNPCKHPSrr = 5094 + + UNPCKLPDrm = 5095 + + UNPCKLPDrr = 5096 + + UNPCKLPSrm = 5097 + + UNPCKLPSrr = 5098 + + URDMSRri = 5099 + + URDMSRri_EVEX = 5100 + + URDMSRrr = 5101 + + URDMSRrr_EVEX = 5102 + + UWRMSRir = 5103 + + UWRMSRir_EVEX = 5104 + + UWRMSRrr = 5105 + + UWRMSRrr_EVEX = 5106 + + V4FMADDPSrm = 5107 + + V4FMADDPSrmk = 5108 + + V4FMADDPSrmkz = 5109 + + V4FMADDSSrm = 5110 + + V4FMADDSSrmk = 5111 + + V4FMADDSSrmkz = 5112 + + V4FNMADDPSrm = 5113 + + V4FNMADDPSrmk = 5114 + + V4FNMADDPSrmkz = 5115 + + V4FNMADDSSrm = 5116 + + V4FNMADDSSrmk = 5117 + + V4FNMADDSSrmkz = 5118 + + VAARG_64 = 5119 + + VAARG_X32 = 5120 + + VADDBF16Z128rm = 5121 + + VADDBF16Z128rmb = 5122 + + VADDBF16Z128rmbk = 5123 + + VADDBF16Z128rmbkz = 5124 + + VADDBF16Z128rmk = 5125 + + VADDBF16Z128rmkz = 5126 + + VADDBF16Z128rr = 5127 + + VADDBF16Z128rrk = 5128 + + VADDBF16Z128rrkz = 5129 + + VADDBF16Z256rm = 5130 + + VADDBF16Z256rmb = 5131 + + VADDBF16Z256rmbk = 5132 + + VADDBF16Z256rmbkz = 5133 + + VADDBF16Z256rmk = 5134 + + VADDBF16Z256rmkz = 5135 + + VADDBF16Z256rr = 5136 + + VADDBF16Z256rrk = 5137 + + VADDBF16Z256rrkz = 5138 + + VADDBF16Zrm = 5139 + + VADDBF16Zrmb = 5140 + + VADDBF16Zrmbk = 5141 + + VADDBF16Zrmbkz = 5142 + + VADDBF16Zrmk = 5143 + + VADDBF16Zrmkz = 5144 + + VADDBF16Zrr = 5145 + + VADDBF16Zrrk = 5146 + + VADDBF16Zrrkz = 5147 + + VADDPDYrm = 5148 + + VADDPDYrr = 5149 + + VADDPDZ128rm = 5150 + + VADDPDZ128rmb = 5151 + + VADDPDZ128rmbk = 5152 + + VADDPDZ128rmbkz = 5153 + + VADDPDZ128rmk = 5154 + + VADDPDZ128rmkz = 5155 + + VADDPDZ128rr = 5156 + + VADDPDZ128rrk = 5157 + + VADDPDZ128rrkz = 5158 + + VADDPDZ256rm = 5159 + + VADDPDZ256rmb = 5160 + + VADDPDZ256rmbk = 5161 + + VADDPDZ256rmbkz = 5162 + + VADDPDZ256rmk = 5163 + + VADDPDZ256rmkz = 5164 + + VADDPDZ256rr = 5165 + + VADDPDZ256rrk = 5166 + + VADDPDZ256rrkz = 5167 + + VADDPDZrm = 5168 + + VADDPDZrmb = 5169 + + VADDPDZrmbk = 5170 + + VADDPDZrmbkz = 5171 + + VADDPDZrmk = 5172 + + VADDPDZrmkz = 5173 + + VADDPDZrr = 5174 + + VADDPDZrrb = 5175 + + VADDPDZrrbk = 5176 + + VADDPDZrrbkz = 5177 + + VADDPDZrrk = 5178 + + VADDPDZrrkz = 5179 + + VADDPDrm = 5180 + + VADDPDrr = 5181 + + VADDPHZ128rm = 5182 + + VADDPHZ128rmb = 5183 + + VADDPHZ128rmbk = 5184 + + VADDPHZ128rmbkz = 5185 + + VADDPHZ128rmk = 5186 + + VADDPHZ128rmkz = 5187 + + VADDPHZ128rr = 5188 + + VADDPHZ128rrk = 5189 + + VADDPHZ128rrkz = 5190 + + VADDPHZ256rm = 5191 + + VADDPHZ256rmb = 5192 + + VADDPHZ256rmbk = 5193 + + VADDPHZ256rmbkz = 5194 + + VADDPHZ256rmk = 5195 + + VADDPHZ256rmkz = 5196 + + VADDPHZ256rr = 5197 + + VADDPHZ256rrk = 5198 + + VADDPHZ256rrkz = 5199 + + VADDPHZrm = 5200 + + VADDPHZrmb = 5201 + + VADDPHZrmbk = 5202 + + VADDPHZrmbkz = 5203 + + VADDPHZrmk = 5204 + + VADDPHZrmkz = 5205 + + VADDPHZrr = 5206 + + VADDPHZrrb = 5207 + + VADDPHZrrbk = 5208 + + VADDPHZrrbkz = 5209 + + VADDPHZrrk = 5210 + + VADDPHZrrkz = 5211 + + VADDPSYrm = 5212 + + VADDPSYrr = 5213 + + VADDPSZ128rm = 5214 + + VADDPSZ128rmb = 5215 + + VADDPSZ128rmbk = 5216 + + VADDPSZ128rmbkz = 5217 + + VADDPSZ128rmk = 5218 + + VADDPSZ128rmkz = 5219 + + VADDPSZ128rr = 5220 + + VADDPSZ128rrk = 5221 + + VADDPSZ128rrkz = 5222 + + VADDPSZ256rm = 5223 + + VADDPSZ256rmb = 5224 + + VADDPSZ256rmbk = 5225 + + VADDPSZ256rmbkz = 5226 + + VADDPSZ256rmk = 5227 + + VADDPSZ256rmkz = 5228 + + VADDPSZ256rr = 5229 + + VADDPSZ256rrk = 5230 + + VADDPSZ256rrkz = 5231 + + VADDPSZrm = 5232 + + VADDPSZrmb = 5233 + + VADDPSZrmbk = 5234 + + VADDPSZrmbkz = 5235 + + VADDPSZrmk = 5236 + + VADDPSZrmkz = 5237 + + VADDPSZrr = 5238 + + VADDPSZrrb = 5239 + + VADDPSZrrbk = 5240 + + VADDPSZrrbkz = 5241 + + VADDPSZrrk = 5242 + + VADDPSZrrkz = 5243 + + VADDPSrm = 5244 + + VADDPSrr = 5245 + + VADDSDZrm = 5246 + + VADDSDZrm_Int = 5247 + + VADDSDZrmk_Int = 5248 + + VADDSDZrmkz_Int = 5249 + + VADDSDZrr = 5250 + + VADDSDZrr_Int = 5251 + + VADDSDZrrb_Int = 5252 + + VADDSDZrrbk_Int = 5253 + + VADDSDZrrbkz_Int = 5254 + + VADDSDZrrk_Int = 5255 + + VADDSDZrrkz_Int = 5256 + + VADDSDrm = 5257 + + VADDSDrm_Int = 5258 + + VADDSDrr = 5259 + + VADDSDrr_Int = 5260 + + VADDSHZrm = 5261 + + VADDSHZrm_Int = 5262 + + VADDSHZrmk_Int = 5263 + + VADDSHZrmkz_Int = 5264 + + VADDSHZrr = 5265 + + VADDSHZrr_Int = 5266 + + VADDSHZrrb_Int = 5267 + + VADDSHZrrbk_Int = 5268 + + VADDSHZrrbkz_Int = 5269 + + VADDSHZrrk_Int = 5270 + + VADDSHZrrkz_Int = 5271 + + VADDSSZrm = 5272 + + VADDSSZrm_Int = 5273 + + VADDSSZrmk_Int = 5274 + + VADDSSZrmkz_Int = 5275 + + VADDSSZrr = 5276 + + VADDSSZrr_Int = 5277 + + VADDSSZrrb_Int = 5278 + + VADDSSZrrbk_Int = 5279 + + VADDSSZrrbkz_Int = 5280 + + VADDSSZrrk_Int = 5281 + + VADDSSZrrkz_Int = 5282 + + VADDSSrm = 5283 + + VADDSSrm_Int = 5284 + + VADDSSrr = 5285 + + VADDSSrr_Int = 5286 + + VADDSUBPDYrm = 5287 + + VADDSUBPDYrr = 5288 + + VADDSUBPDrm = 5289 + + VADDSUBPDrr = 5290 + + VADDSUBPSYrm = 5291 + + VADDSUBPSYrr = 5292 + + VADDSUBPSrm = 5293 + + VADDSUBPSrr = 5294 + + VAESDECLASTYrm = 5295 + + VAESDECLASTYrr = 5296 + + VAESDECLASTZ128rm = 5297 + + VAESDECLASTZ128rr = 5298 + + VAESDECLASTZ256rm = 5299 + + VAESDECLASTZ256rr = 5300 + + VAESDECLASTZrm = 5301 + + VAESDECLASTZrr = 5302 + + VAESDECLASTrm = 5303 + + VAESDECLASTrr = 5304 + + VAESDECYrm = 5305 + + VAESDECYrr = 5306 + + VAESDECZ128rm = 5307 + + VAESDECZ128rr = 5308 + + VAESDECZ256rm = 5309 + + VAESDECZ256rr = 5310 + + VAESDECZrm = 5311 + + VAESDECZrr = 5312 + + VAESDECrm = 5313 + + VAESDECrr = 5314 + + VAESENCLASTYrm = 5315 + + VAESENCLASTYrr = 5316 + + VAESENCLASTZ128rm = 5317 + + VAESENCLASTZ128rr = 5318 + + VAESENCLASTZ256rm = 5319 + + VAESENCLASTZ256rr = 5320 + + VAESENCLASTZrm = 5321 + + VAESENCLASTZrr = 5322 + + VAESENCLASTrm = 5323 + + VAESENCLASTrr = 5324 + + VAESENCYrm = 5325 + + VAESENCYrr = 5326 + + VAESENCZ128rm = 5327 + + VAESENCZ128rr = 5328 + + VAESENCZ256rm = 5329 + + VAESENCZ256rr = 5330 + + VAESENCZrm = 5331 + + VAESENCZrr = 5332 + + VAESENCrm = 5333 + + VAESENCrr = 5334 + + VAESIMCrm = 5335 + + VAESIMCrr = 5336 + + VAESKEYGENASSISTrmi = 5337 + + VAESKEYGENASSISTrri = 5338 + + VALIGNDZ128rmbi = 5339 + + VALIGNDZ128rmbik = 5340 + + VALIGNDZ128rmbikz = 5341 + + VALIGNDZ128rmi = 5342 + + VALIGNDZ128rmik = 5343 + + VALIGNDZ128rmikz = 5344 + + VALIGNDZ128rri = 5345 + + VALIGNDZ128rrik = 5346 + + VALIGNDZ128rrikz = 5347 + + VALIGNDZ256rmbi = 5348 + + VALIGNDZ256rmbik = 5349 + + VALIGNDZ256rmbikz = 5350 + + VALIGNDZ256rmi = 5351 + + VALIGNDZ256rmik = 5352 + + VALIGNDZ256rmikz = 5353 + + VALIGNDZ256rri = 5354 + + VALIGNDZ256rrik = 5355 + + VALIGNDZ256rrikz = 5356 + + VALIGNDZrmbi = 5357 + + VALIGNDZrmbik = 5358 + + VALIGNDZrmbikz = 5359 + + VALIGNDZrmi = 5360 + + VALIGNDZrmik = 5361 + + VALIGNDZrmikz = 5362 + + VALIGNDZrri = 5363 + + VALIGNDZrrik = 5364 + + VALIGNDZrrikz = 5365 + + VALIGNQZ128rmbi = 5366 + + VALIGNQZ128rmbik = 5367 + + VALIGNQZ128rmbikz = 5368 + + VALIGNQZ128rmi = 5369 + + VALIGNQZ128rmik = 5370 + + VALIGNQZ128rmikz = 5371 + + VALIGNQZ128rri = 5372 + + VALIGNQZ128rrik = 5373 + + VALIGNQZ128rrikz = 5374 + + VALIGNQZ256rmbi = 5375 + + VALIGNQZ256rmbik = 5376 + + VALIGNQZ256rmbikz = 5377 + + VALIGNQZ256rmi = 5378 + + VALIGNQZ256rmik = 5379 + + VALIGNQZ256rmikz = 5380 + + VALIGNQZ256rri = 5381 + + VALIGNQZ256rrik = 5382 + + VALIGNQZ256rrikz = 5383 + + VALIGNQZrmbi = 5384 + + VALIGNQZrmbik = 5385 + + VALIGNQZrmbikz = 5386 + + VALIGNQZrmi = 5387 + + VALIGNQZrmik = 5388 + + VALIGNQZrmikz = 5389 + + VALIGNQZrri = 5390 + + VALIGNQZrrik = 5391 + + VALIGNQZrrikz = 5392 + + VANDNPDYrm = 5393 + + VANDNPDYrr = 5394 + + VANDNPDZ128rm = 5395 + + VANDNPDZ128rmb = 5396 + + VANDNPDZ128rmbk = 5397 + + VANDNPDZ128rmbkz = 5398 + + VANDNPDZ128rmk = 5399 + + VANDNPDZ128rmkz = 5400 + + VANDNPDZ128rr = 5401 + + VANDNPDZ128rrk = 5402 + + VANDNPDZ128rrkz = 5403 + + VANDNPDZ256rm = 5404 + + VANDNPDZ256rmb = 5405 + + VANDNPDZ256rmbk = 5406 + + VANDNPDZ256rmbkz = 5407 + + VANDNPDZ256rmk = 5408 + + VANDNPDZ256rmkz = 5409 + + VANDNPDZ256rr = 5410 + + VANDNPDZ256rrk = 5411 + + VANDNPDZ256rrkz = 5412 + + VANDNPDZrm = 5413 + + VANDNPDZrmb = 5414 + + VANDNPDZrmbk = 5415 + + VANDNPDZrmbkz = 5416 + + VANDNPDZrmk = 5417 + + VANDNPDZrmkz = 5418 + + VANDNPDZrr = 5419 + + VANDNPDZrrk = 5420 + + VANDNPDZrrkz = 5421 + + VANDNPDrm = 5422 + + VANDNPDrr = 5423 + + VANDNPSYrm = 5424 + + VANDNPSYrr = 5425 + + VANDNPSZ128rm = 5426 + + VANDNPSZ128rmb = 5427 + + VANDNPSZ128rmbk = 5428 + + VANDNPSZ128rmbkz = 5429 + + VANDNPSZ128rmk = 5430 + + VANDNPSZ128rmkz = 5431 + + VANDNPSZ128rr = 5432 + + VANDNPSZ128rrk = 5433 + + VANDNPSZ128rrkz = 5434 + + VANDNPSZ256rm = 5435 + + VANDNPSZ256rmb = 5436 + + VANDNPSZ256rmbk = 5437 + + VANDNPSZ256rmbkz = 5438 + + VANDNPSZ256rmk = 5439 + + VANDNPSZ256rmkz = 5440 + + VANDNPSZ256rr = 5441 + + VANDNPSZ256rrk = 5442 + + VANDNPSZ256rrkz = 5443 + + VANDNPSZrm = 5444 + + VANDNPSZrmb = 5445 + + VANDNPSZrmbk = 5446 + + VANDNPSZrmbkz = 5447 + + VANDNPSZrmk = 5448 + + VANDNPSZrmkz = 5449 + + VANDNPSZrr = 5450 + + VANDNPSZrrk = 5451 + + VANDNPSZrrkz = 5452 + + VANDNPSrm = 5453 + + VANDNPSrr = 5454 + + VANDPDYrm = 5455 + + VANDPDYrr = 5456 + + VANDPDZ128rm = 5457 + + VANDPDZ128rmb = 5458 + + VANDPDZ128rmbk = 5459 + + VANDPDZ128rmbkz = 5460 + + VANDPDZ128rmk = 5461 + + VANDPDZ128rmkz = 5462 + + VANDPDZ128rr = 5463 + + VANDPDZ128rrk = 5464 + + VANDPDZ128rrkz = 5465 + + VANDPDZ256rm = 5466 + + VANDPDZ256rmb = 5467 + + VANDPDZ256rmbk = 5468 + + VANDPDZ256rmbkz = 5469 + + VANDPDZ256rmk = 5470 + + VANDPDZ256rmkz = 5471 + + VANDPDZ256rr = 5472 + + VANDPDZ256rrk = 5473 + + VANDPDZ256rrkz = 5474 + + VANDPDZrm = 5475 + + VANDPDZrmb = 5476 + + VANDPDZrmbk = 5477 + + VANDPDZrmbkz = 5478 + + VANDPDZrmk = 5479 + + VANDPDZrmkz = 5480 + + VANDPDZrr = 5481 + + VANDPDZrrk = 5482 + + VANDPDZrrkz = 5483 + + VANDPDrm = 5484 + + VANDPDrr = 5485 + + VANDPSYrm = 5486 + + VANDPSYrr = 5487 + + VANDPSZ128rm = 5488 + + VANDPSZ128rmb = 5489 + + VANDPSZ128rmbk = 5490 + + VANDPSZ128rmbkz = 5491 + + VANDPSZ128rmk = 5492 + + VANDPSZ128rmkz = 5493 + + VANDPSZ128rr = 5494 + + VANDPSZ128rrk = 5495 + + VANDPSZ128rrkz = 5496 + + VANDPSZ256rm = 5497 + + VANDPSZ256rmb = 5498 + + VANDPSZ256rmbk = 5499 + + VANDPSZ256rmbkz = 5500 + + VANDPSZ256rmk = 5501 + + VANDPSZ256rmkz = 5502 + + VANDPSZ256rr = 5503 + + VANDPSZ256rrk = 5504 + + VANDPSZ256rrkz = 5505 + + VANDPSZrm = 5506 + + VANDPSZrmb = 5507 + + VANDPSZrmbk = 5508 + + VANDPSZrmbkz = 5509 + + VANDPSZrmk = 5510 + + VANDPSZrmkz = 5511 + + VANDPSZrr = 5512 + + VANDPSZrrk = 5513 + + VANDPSZrrkz = 5514 + + VANDPSrm = 5515 + + VANDPSrr = 5516 + + VASTART_SAVE_XMM_REGS = 5517 + + VBCSTNEBF162PSYrm = 5518 + + VBCSTNEBF162PSrm = 5519 + + VBCSTNESH2PSYrm = 5520 + + VBCSTNESH2PSrm = 5521 + + VBLENDMPDZ128rm = 5522 + + VBLENDMPDZ128rmb = 5523 + + VBLENDMPDZ128rmbk = 5524 + + VBLENDMPDZ128rmbkz = 5525 + + VBLENDMPDZ128rmk = 5526 + + VBLENDMPDZ128rmkz = 5527 + + VBLENDMPDZ128rr = 5528 + + VBLENDMPDZ128rrk = 5529 + + VBLENDMPDZ128rrkz = 5530 + + VBLENDMPDZ256rm = 5531 + + VBLENDMPDZ256rmb = 5532 + + VBLENDMPDZ256rmbk = 5533 + + VBLENDMPDZ256rmbkz = 5534 + + VBLENDMPDZ256rmk = 5535 + + VBLENDMPDZ256rmkz = 5536 + + VBLENDMPDZ256rr = 5537 + + VBLENDMPDZ256rrk = 5538 + + VBLENDMPDZ256rrkz = 5539 + + VBLENDMPDZrm = 5540 + + VBLENDMPDZrmb = 5541 + + VBLENDMPDZrmbk = 5542 + + VBLENDMPDZrmbkz = 5543 + + VBLENDMPDZrmk = 5544 + + VBLENDMPDZrmkz = 5545 + + VBLENDMPDZrr = 5546 + + VBLENDMPDZrrk = 5547 + + VBLENDMPDZrrkz = 5548 + + VBLENDMPSZ128rm = 5549 + + VBLENDMPSZ128rmb = 5550 + + VBLENDMPSZ128rmbk = 5551 + + VBLENDMPSZ128rmbkz = 5552 + + VBLENDMPSZ128rmk = 5553 + + VBLENDMPSZ128rmkz = 5554 + + VBLENDMPSZ128rr = 5555 + + VBLENDMPSZ128rrk = 5556 + + VBLENDMPSZ128rrkz = 5557 + + VBLENDMPSZ256rm = 5558 + + VBLENDMPSZ256rmb = 5559 + + VBLENDMPSZ256rmbk = 5560 + + VBLENDMPSZ256rmbkz = 5561 + + VBLENDMPSZ256rmk = 5562 + + VBLENDMPSZ256rmkz = 5563 + + VBLENDMPSZ256rr = 5564 + + VBLENDMPSZ256rrk = 5565 + + VBLENDMPSZ256rrkz = 5566 + + VBLENDMPSZrm = 5567 + + VBLENDMPSZrmb = 5568 + + VBLENDMPSZrmbk = 5569 + + VBLENDMPSZrmbkz = 5570 + + VBLENDMPSZrmk = 5571 + + VBLENDMPSZrmkz = 5572 + + VBLENDMPSZrr = 5573 + + VBLENDMPSZrrk = 5574 + + VBLENDMPSZrrkz = 5575 + + VBLENDPDYrmi = 5576 + + VBLENDPDYrri = 5577 + + VBLENDPDrmi = 5578 + + VBLENDPDrri = 5579 + + VBLENDPSYrmi = 5580 + + VBLENDPSYrri = 5581 + + VBLENDPSrmi = 5582 + + VBLENDPSrri = 5583 + + VBLENDVPDYrmr = 5584 + + VBLENDVPDYrrr = 5585 + + VBLENDVPDrmr = 5586 + + VBLENDVPDrrr = 5587 + + VBLENDVPSYrmr = 5588 + + VBLENDVPSYrrr = 5589 + + VBLENDVPSrmr = 5590 + + VBLENDVPSrrr = 5591 + + VBROADCASTF128rm = 5592 + + VBROADCASTF32X2Z256rm = 5593 + + VBROADCASTF32X2Z256rmk = 5594 + + VBROADCASTF32X2Z256rmkz = 5595 + + VBROADCASTF32X2Z256rr = 5596 + + VBROADCASTF32X2Z256rrk = 5597 + + VBROADCASTF32X2Z256rrkz = 5598 + + VBROADCASTF32X2Zrm = 5599 + + VBROADCASTF32X2Zrmk = 5600 + + VBROADCASTF32X2Zrmkz = 5601 + + VBROADCASTF32X2Zrr = 5602 + + VBROADCASTF32X2Zrrk = 5603 + + VBROADCASTF32X2Zrrkz = 5604 + + VBROADCASTF32X4Z256rm = 5605 + + VBROADCASTF32X4Z256rmk = 5606 + + VBROADCASTF32X4Z256rmkz = 5607 + + VBROADCASTF32X4Zrm = 5608 + + VBROADCASTF32X4Zrmk = 5609 + + VBROADCASTF32X4Zrmkz = 5610 + + VBROADCASTF32X8Zrm = 5611 + + VBROADCASTF32X8Zrmk = 5612 + + VBROADCASTF32X8Zrmkz = 5613 + + VBROADCASTF64X2Z256rm = 5614 + + VBROADCASTF64X2Z256rmk = 5615 + + VBROADCASTF64X2Z256rmkz = 5616 + + VBROADCASTF64X2Zrm = 5617 + + VBROADCASTF64X2Zrmk = 5618 + + VBROADCASTF64X2Zrmkz = 5619 + + VBROADCASTF64X4Zrm = 5620 + + VBROADCASTF64X4Zrmk = 5621 + + VBROADCASTF64X4Zrmkz = 5622 + + VBROADCASTI128rm = 5623 + + VBROADCASTI32X2Z128rm = 5624 + + VBROADCASTI32X2Z128rmk = 5625 + + VBROADCASTI32X2Z128rmkz = 5626 + + VBROADCASTI32X2Z128rr = 5627 + + VBROADCASTI32X2Z128rrk = 5628 + + VBROADCASTI32X2Z128rrkz = 5629 + + VBROADCASTI32X2Z256rm = 5630 + + VBROADCASTI32X2Z256rmk = 5631 + + VBROADCASTI32X2Z256rmkz = 5632 + + VBROADCASTI32X2Z256rr = 5633 + + VBROADCASTI32X2Z256rrk = 5634 + + VBROADCASTI32X2Z256rrkz = 5635 + + VBROADCASTI32X2Zrm = 5636 + + VBROADCASTI32X2Zrmk = 5637 + + VBROADCASTI32X2Zrmkz = 5638 + + VBROADCASTI32X2Zrr = 5639 + + VBROADCASTI32X2Zrrk = 5640 + + VBROADCASTI32X2Zrrkz = 5641 + + VBROADCASTI32X4Z256rm = 5642 + + VBROADCASTI32X4Z256rmk = 5643 + + VBROADCASTI32X4Z256rmkz = 5644 + + VBROADCASTI32X4Zrm = 5645 + + VBROADCASTI32X4Zrmk = 5646 + + VBROADCASTI32X4Zrmkz = 5647 + + VBROADCASTI32X8Zrm = 5648 + + VBROADCASTI32X8Zrmk = 5649 + + VBROADCASTI32X8Zrmkz = 5650 + + VBROADCASTI64X2Z256rm = 5651 + + VBROADCASTI64X2Z256rmk = 5652 + + VBROADCASTI64X2Z256rmkz = 5653 + + VBROADCASTI64X2Zrm = 5654 + + VBROADCASTI64X2Zrmk = 5655 + + VBROADCASTI64X2Zrmkz = 5656 + + VBROADCASTI64X4Zrm = 5657 + + VBROADCASTI64X4Zrmk = 5658 + + VBROADCASTI64X4Zrmkz = 5659 + + VBROADCASTSDYrm = 5660 + + VBROADCASTSDYrr = 5661 + + VBROADCASTSDZ256rm = 5662 + + VBROADCASTSDZ256rmk = 5663 + + VBROADCASTSDZ256rmkz = 5664 + + VBROADCASTSDZ256rr = 5665 + + VBROADCASTSDZ256rrk = 5666 + + VBROADCASTSDZ256rrkz = 5667 + + VBROADCASTSDZrm = 5668 + + VBROADCASTSDZrmk = 5669 + + VBROADCASTSDZrmkz = 5670 + + VBROADCASTSDZrr = 5671 + + VBROADCASTSDZrrk = 5672 + + VBROADCASTSDZrrkz = 5673 + + VBROADCASTSSYrm = 5674 + + VBROADCASTSSYrr = 5675 + + VBROADCASTSSZ128rm = 5676 + + VBROADCASTSSZ128rmk = 5677 + + VBROADCASTSSZ128rmkz = 5678 + + VBROADCASTSSZ128rr = 5679 + + VBROADCASTSSZ128rrk = 5680 + + VBROADCASTSSZ128rrkz = 5681 + + VBROADCASTSSZ256rm = 5682 + + VBROADCASTSSZ256rmk = 5683 + + VBROADCASTSSZ256rmkz = 5684 + + VBROADCASTSSZ256rr = 5685 + + VBROADCASTSSZ256rrk = 5686 + + VBROADCASTSSZ256rrkz = 5687 + + VBROADCASTSSZrm = 5688 + + VBROADCASTSSZrmk = 5689 + + VBROADCASTSSZrmkz = 5690 + + VBROADCASTSSZrr = 5691 + + VBROADCASTSSZrrk = 5692 + + VBROADCASTSSZrrkz = 5693 + + VBROADCASTSSrm = 5694 + + VBROADCASTSSrr = 5695 + + VCMPBF16Z128rmbi = 5696 + + VCMPBF16Z128rmbik = 5697 + + VCMPBF16Z128rmi = 5698 + + VCMPBF16Z128rmik = 5699 + + VCMPBF16Z128rri = 5700 + + VCMPBF16Z128rrik = 5701 + + VCMPBF16Z256rmbi = 5702 + + VCMPBF16Z256rmbik = 5703 + + VCMPBF16Z256rmi = 5704 + + VCMPBF16Z256rmik = 5705 + + VCMPBF16Z256rri = 5706 + + VCMPBF16Z256rrik = 5707 + + VCMPBF16Zrmbi = 5708 + + VCMPBF16Zrmbik = 5709 + + VCMPBF16Zrmi = 5710 + + VCMPBF16Zrmik = 5711 + + VCMPBF16Zrri = 5712 + + VCMPBF16Zrrik = 5713 + + VCMPPDYrmi = 5714 + + VCMPPDYrri = 5715 + + VCMPPDZ128rmbi = 5716 + + VCMPPDZ128rmbik = 5717 + + VCMPPDZ128rmi = 5718 + + VCMPPDZ128rmik = 5719 + + VCMPPDZ128rri = 5720 + + VCMPPDZ128rrik = 5721 + + VCMPPDZ256rmbi = 5722 + + VCMPPDZ256rmbik = 5723 + + VCMPPDZ256rmi = 5724 + + VCMPPDZ256rmik = 5725 + + VCMPPDZ256rri = 5726 + + VCMPPDZ256rrik = 5727 + + VCMPPDZrmbi = 5728 + + VCMPPDZrmbik = 5729 + + VCMPPDZrmi = 5730 + + VCMPPDZrmik = 5731 + + VCMPPDZrri = 5732 + + VCMPPDZrrib = 5733 + + VCMPPDZrribk = 5734 + + VCMPPDZrrik = 5735 + + VCMPPDrmi = 5736 + + VCMPPDrri = 5737 + + VCMPPHZ128rmbi = 5738 + + VCMPPHZ128rmbik = 5739 + + VCMPPHZ128rmi = 5740 + + VCMPPHZ128rmik = 5741 + + VCMPPHZ128rri = 5742 + + VCMPPHZ128rrik = 5743 + + VCMPPHZ256rmbi = 5744 + + VCMPPHZ256rmbik = 5745 + + VCMPPHZ256rmi = 5746 + + VCMPPHZ256rmik = 5747 + + VCMPPHZ256rri = 5748 + + VCMPPHZ256rrik = 5749 + + VCMPPHZrmbi = 5750 + + VCMPPHZrmbik = 5751 + + VCMPPHZrmi = 5752 + + VCMPPHZrmik = 5753 + + VCMPPHZrri = 5754 + + VCMPPHZrrib = 5755 + + VCMPPHZrribk = 5756 + + VCMPPHZrrik = 5757 + + VCMPPSYrmi = 5758 + + VCMPPSYrri = 5759 + + VCMPPSZ128rmbi = 5760 + + VCMPPSZ128rmbik = 5761 + + VCMPPSZ128rmi = 5762 + + VCMPPSZ128rmik = 5763 + + VCMPPSZ128rri = 5764 + + VCMPPSZ128rrik = 5765 + + VCMPPSZ256rmbi = 5766 + + VCMPPSZ256rmbik = 5767 + + VCMPPSZ256rmi = 5768 + + VCMPPSZ256rmik = 5769 + + VCMPPSZ256rri = 5770 + + VCMPPSZ256rrik = 5771 + + VCMPPSZrmbi = 5772 + + VCMPPSZrmbik = 5773 + + VCMPPSZrmi = 5774 + + VCMPPSZrmik = 5775 + + VCMPPSZrri = 5776 + + VCMPPSZrrib = 5777 + + VCMPPSZrribk = 5778 + + VCMPPSZrrik = 5779 + + VCMPPSrmi = 5780 + + VCMPPSrri = 5781 + + VCMPSDZrmi = 5782 + + VCMPSDZrmi_Int = 5783 + + VCMPSDZrmik_Int = 5784 + + VCMPSDZrri = 5785 + + VCMPSDZrri_Int = 5786 + + VCMPSDZrrib_Int = 5787 + + VCMPSDZrribk_Int = 5788 + + VCMPSDZrrik_Int = 5789 + + VCMPSDrmi = 5790 + + VCMPSDrmi_Int = 5791 + + VCMPSDrri = 5792 + + VCMPSDrri_Int = 5793 + + VCMPSHZrmi = 5794 + + VCMPSHZrmi_Int = 5795 + + VCMPSHZrmik_Int = 5796 + + VCMPSHZrri = 5797 + + VCMPSHZrri_Int = 5798 + + VCMPSHZrrib_Int = 5799 + + VCMPSHZrribk_Int = 5800 + + VCMPSHZrrik_Int = 5801 + + VCMPSSZrmi = 5802 + + VCMPSSZrmi_Int = 5803 + + VCMPSSZrmik_Int = 5804 + + VCMPSSZrri = 5805 + + VCMPSSZrri_Int = 5806 + + VCMPSSZrrib_Int = 5807 + + VCMPSSZrribk_Int = 5808 + + VCMPSSZrrik_Int = 5809 + + VCMPSSrmi = 5810 + + VCMPSSrmi_Int = 5811 + + VCMPSSrri = 5812 + + VCMPSSrri_Int = 5813 + + VCOMISBF16Zrm = 5814 + + VCOMISBF16Zrm_Int = 5815 + + VCOMISBF16Zrr = 5816 + + VCOMISBF16Zrr_Int = 5817 + + VCOMISDZrm = 5818 + + VCOMISDZrm_Int = 5819 + + VCOMISDZrr = 5820 + + VCOMISDZrr_Int = 5821 + + VCOMISDZrrb = 5822 + + VCOMISDrm = 5823 + + VCOMISDrm_Int = 5824 + + VCOMISDrr = 5825 + + VCOMISDrr_Int = 5826 + + VCOMISHZrm = 5827 + + VCOMISHZrm_Int = 5828 + + VCOMISHZrr = 5829 + + VCOMISHZrr_Int = 5830 + + VCOMISHZrrb = 5831 + + VCOMISSZrm = 5832 + + VCOMISSZrm_Int = 5833 + + VCOMISSZrr = 5834 + + VCOMISSZrr_Int = 5835 + + VCOMISSZrrb = 5836 + + VCOMISSrm = 5837 + + VCOMISSrm_Int = 5838 + + VCOMISSrr = 5839 + + VCOMISSrr_Int = 5840 + + VCOMPRESSPDZ128mr = 5841 + + VCOMPRESSPDZ128mrk = 5842 + + VCOMPRESSPDZ128rr = 5843 + + VCOMPRESSPDZ128rrk = 5844 + + VCOMPRESSPDZ128rrkz = 5845 + + VCOMPRESSPDZ256mr = 5846 + + VCOMPRESSPDZ256mrk = 5847 + + VCOMPRESSPDZ256rr = 5848 + + VCOMPRESSPDZ256rrk = 5849 + + VCOMPRESSPDZ256rrkz = 5850 + + VCOMPRESSPDZmr = 5851 + + VCOMPRESSPDZmrk = 5852 + + VCOMPRESSPDZrr = 5853 + + VCOMPRESSPDZrrk = 5854 + + VCOMPRESSPDZrrkz = 5855 + + VCOMPRESSPSZ128mr = 5856 + + VCOMPRESSPSZ128mrk = 5857 + + VCOMPRESSPSZ128rr = 5858 + + VCOMPRESSPSZ128rrk = 5859 + + VCOMPRESSPSZ128rrkz = 5860 + + VCOMPRESSPSZ256mr = 5861 + + VCOMPRESSPSZ256mrk = 5862 + + VCOMPRESSPSZ256rr = 5863 + + VCOMPRESSPSZ256rrk = 5864 + + VCOMPRESSPSZ256rrkz = 5865 + + VCOMPRESSPSZmr = 5866 + + VCOMPRESSPSZmrk = 5867 + + VCOMPRESSPSZrr = 5868 + + VCOMPRESSPSZrrk = 5869 + + VCOMPRESSPSZrrkz = 5870 + + VCOMXSDZrm_Int = 5871 + + VCOMXSDZrr_Int = 5872 + + VCOMXSDZrrb_Int = 5873 + + VCOMXSHZrm_Int = 5874 + + VCOMXSHZrr_Int = 5875 + + VCOMXSHZrrb_Int = 5876 + + VCOMXSSZrm_Int = 5877 + + VCOMXSSZrr_Int = 5878 + + VCOMXSSZrrb_Int = 5879 + + VCVT2PH2BF8SZ128rm = 5880 + + VCVT2PH2BF8SZ128rmb = 5881 + + VCVT2PH2BF8SZ128rmbk = 5882 + + VCVT2PH2BF8SZ128rmbkz = 5883 + + VCVT2PH2BF8SZ128rmk = 5884 + + VCVT2PH2BF8SZ128rmkz = 5885 + + VCVT2PH2BF8SZ128rr = 5886 + + VCVT2PH2BF8SZ128rrk = 5887 + + VCVT2PH2BF8SZ128rrkz = 5888 + + VCVT2PH2BF8SZ256rm = 5889 + + VCVT2PH2BF8SZ256rmb = 5890 + + VCVT2PH2BF8SZ256rmbk = 5891 + + VCVT2PH2BF8SZ256rmbkz = 5892 + + VCVT2PH2BF8SZ256rmk = 5893 + + VCVT2PH2BF8SZ256rmkz = 5894 + + VCVT2PH2BF8SZ256rr = 5895 + + VCVT2PH2BF8SZ256rrk = 5896 + + VCVT2PH2BF8SZ256rrkz = 5897 + + VCVT2PH2BF8SZrm = 5898 + + VCVT2PH2BF8SZrmb = 5899 + + VCVT2PH2BF8SZrmbk = 5900 + + VCVT2PH2BF8SZrmbkz = 5901 + + VCVT2PH2BF8SZrmk = 5902 + + VCVT2PH2BF8SZrmkz = 5903 + + VCVT2PH2BF8SZrr = 5904 + + VCVT2PH2BF8SZrrk = 5905 + + VCVT2PH2BF8SZrrkz = 5906 + + VCVT2PH2BF8Z128rm = 5907 + + VCVT2PH2BF8Z128rmb = 5908 + + VCVT2PH2BF8Z128rmbk = 5909 + + VCVT2PH2BF8Z128rmbkz = 5910 + + VCVT2PH2BF8Z128rmk = 5911 + + VCVT2PH2BF8Z128rmkz = 5912 + + VCVT2PH2BF8Z128rr = 5913 + + VCVT2PH2BF8Z128rrk = 5914 + + VCVT2PH2BF8Z128rrkz = 5915 + + VCVT2PH2BF8Z256rm = 5916 + + VCVT2PH2BF8Z256rmb = 5917 + + VCVT2PH2BF8Z256rmbk = 5918 + + VCVT2PH2BF8Z256rmbkz = 5919 + + VCVT2PH2BF8Z256rmk = 5920 + + VCVT2PH2BF8Z256rmkz = 5921 + + VCVT2PH2BF8Z256rr = 5922 + + VCVT2PH2BF8Z256rrk = 5923 + + VCVT2PH2BF8Z256rrkz = 5924 + + VCVT2PH2BF8Zrm = 5925 + + VCVT2PH2BF8Zrmb = 5926 + + VCVT2PH2BF8Zrmbk = 5927 + + VCVT2PH2BF8Zrmbkz = 5928 + + VCVT2PH2BF8Zrmk = 5929 + + VCVT2PH2BF8Zrmkz = 5930 + + VCVT2PH2BF8Zrr = 5931 + + VCVT2PH2BF8Zrrk = 5932 + + VCVT2PH2BF8Zrrkz = 5933 + + VCVT2PH2HF8SZ128rm = 5934 + + VCVT2PH2HF8SZ128rmb = 5935 + + VCVT2PH2HF8SZ128rmbk = 5936 + + VCVT2PH2HF8SZ128rmbkz = 5937 + + VCVT2PH2HF8SZ128rmk = 5938 + + VCVT2PH2HF8SZ128rmkz = 5939 + + VCVT2PH2HF8SZ128rr = 5940 + + VCVT2PH2HF8SZ128rrk = 5941 + + VCVT2PH2HF8SZ128rrkz = 5942 + + VCVT2PH2HF8SZ256rm = 5943 + + VCVT2PH2HF8SZ256rmb = 5944 + + VCVT2PH2HF8SZ256rmbk = 5945 + + VCVT2PH2HF8SZ256rmbkz = 5946 + + VCVT2PH2HF8SZ256rmk = 5947 + + VCVT2PH2HF8SZ256rmkz = 5948 + + VCVT2PH2HF8SZ256rr = 5949 + + VCVT2PH2HF8SZ256rrk = 5950 + + VCVT2PH2HF8SZ256rrkz = 5951 + + VCVT2PH2HF8SZrm = 5952 + + VCVT2PH2HF8SZrmb = 5953 + + VCVT2PH2HF8SZrmbk = 5954 + + VCVT2PH2HF8SZrmbkz = 5955 + + VCVT2PH2HF8SZrmk = 5956 + + VCVT2PH2HF8SZrmkz = 5957 + + VCVT2PH2HF8SZrr = 5958 + + VCVT2PH2HF8SZrrk = 5959 + + VCVT2PH2HF8SZrrkz = 5960 + + VCVT2PH2HF8Z128rm = 5961 + + VCVT2PH2HF8Z128rmb = 5962 + + VCVT2PH2HF8Z128rmbk = 5963 + + VCVT2PH2HF8Z128rmbkz = 5964 + + VCVT2PH2HF8Z128rmk = 5965 + + VCVT2PH2HF8Z128rmkz = 5966 + + VCVT2PH2HF8Z128rr = 5967 + + VCVT2PH2HF8Z128rrk = 5968 + + VCVT2PH2HF8Z128rrkz = 5969 + + VCVT2PH2HF8Z256rm = 5970 + + VCVT2PH2HF8Z256rmb = 5971 + + VCVT2PH2HF8Z256rmbk = 5972 + + VCVT2PH2HF8Z256rmbkz = 5973 + + VCVT2PH2HF8Z256rmk = 5974 + + VCVT2PH2HF8Z256rmkz = 5975 + + VCVT2PH2HF8Z256rr = 5976 + + VCVT2PH2HF8Z256rrk = 5977 + + VCVT2PH2HF8Z256rrkz = 5978 + + VCVT2PH2HF8Zrm = 5979 + + VCVT2PH2HF8Zrmb = 5980 + + VCVT2PH2HF8Zrmbk = 5981 + + VCVT2PH2HF8Zrmbkz = 5982 + + VCVT2PH2HF8Zrmk = 5983 + + VCVT2PH2HF8Zrmkz = 5984 + + VCVT2PH2HF8Zrr = 5985 + + VCVT2PH2HF8Zrrk = 5986 + + VCVT2PH2HF8Zrrkz = 5987 + + VCVT2PS2PHXZ128rm = 5988 + + VCVT2PS2PHXZ128rmb = 5989 + + VCVT2PS2PHXZ128rmbk = 5990 + + VCVT2PS2PHXZ128rmbkz = 5991 + + VCVT2PS2PHXZ128rmk = 5992 + + VCVT2PS2PHXZ128rmkz = 5993 + + VCVT2PS2PHXZ128rr = 5994 + + VCVT2PS2PHXZ128rrk = 5995 + + VCVT2PS2PHXZ128rrkz = 5996 + + VCVT2PS2PHXZ256rm = 5997 + + VCVT2PS2PHXZ256rmb = 5998 + + VCVT2PS2PHXZ256rmbk = 5999 + + VCVT2PS2PHXZ256rmbkz = 6000 + + VCVT2PS2PHXZ256rmk = 6001 + + VCVT2PS2PHXZ256rmkz = 6002 + + VCVT2PS2PHXZ256rr = 6003 + + VCVT2PS2PHXZ256rrk = 6004 + + VCVT2PS2PHXZ256rrkz = 6005 + + VCVT2PS2PHXZrm = 6006 + + VCVT2PS2PHXZrmb = 6007 + + VCVT2PS2PHXZrmbk = 6008 + + VCVT2PS2PHXZrmbkz = 6009 + + VCVT2PS2PHXZrmk = 6010 + + VCVT2PS2PHXZrmkz = 6011 + + VCVT2PS2PHXZrr = 6012 + + VCVT2PS2PHXZrrb = 6013 + + VCVT2PS2PHXZrrbk = 6014 + + VCVT2PS2PHXZrrbkz = 6015 + + VCVT2PS2PHXZrrk = 6016 + + VCVT2PS2PHXZrrkz = 6017 + + VCVTBF162IBSZ128rm = 6018 + + VCVTBF162IBSZ128rmb = 6019 + + VCVTBF162IBSZ128rmbk = 6020 + + VCVTBF162IBSZ128rmbkz = 6021 + + VCVTBF162IBSZ128rmk = 6022 + + VCVTBF162IBSZ128rmkz = 6023 + + VCVTBF162IBSZ128rr = 6024 + + VCVTBF162IBSZ128rrk = 6025 + + VCVTBF162IBSZ128rrkz = 6026 + + VCVTBF162IBSZ256rm = 6027 + + VCVTBF162IBSZ256rmb = 6028 + + VCVTBF162IBSZ256rmbk = 6029 + + VCVTBF162IBSZ256rmbkz = 6030 + + VCVTBF162IBSZ256rmk = 6031 + + VCVTBF162IBSZ256rmkz = 6032 + + VCVTBF162IBSZ256rr = 6033 + + VCVTBF162IBSZ256rrk = 6034 + + VCVTBF162IBSZ256rrkz = 6035 + + VCVTBF162IBSZrm = 6036 + + VCVTBF162IBSZrmb = 6037 + + VCVTBF162IBSZrmbk = 6038 + + VCVTBF162IBSZrmbkz = 6039 + + VCVTBF162IBSZrmk = 6040 + + VCVTBF162IBSZrmkz = 6041 + + VCVTBF162IBSZrr = 6042 + + VCVTBF162IBSZrrk = 6043 + + VCVTBF162IBSZrrkz = 6044 + + VCVTBF162IUBSZ128rm = 6045 + + VCVTBF162IUBSZ128rmb = 6046 + + VCVTBF162IUBSZ128rmbk = 6047 + + VCVTBF162IUBSZ128rmbkz = 6048 + + VCVTBF162IUBSZ128rmk = 6049 + + VCVTBF162IUBSZ128rmkz = 6050 + + VCVTBF162IUBSZ128rr = 6051 + + VCVTBF162IUBSZ128rrk = 6052 + + VCVTBF162IUBSZ128rrkz = 6053 + + VCVTBF162IUBSZ256rm = 6054 + + VCVTBF162IUBSZ256rmb = 6055 + + VCVTBF162IUBSZ256rmbk = 6056 + + VCVTBF162IUBSZ256rmbkz = 6057 + + VCVTBF162IUBSZ256rmk = 6058 + + VCVTBF162IUBSZ256rmkz = 6059 + + VCVTBF162IUBSZ256rr = 6060 + + VCVTBF162IUBSZ256rrk = 6061 + + VCVTBF162IUBSZ256rrkz = 6062 + + VCVTBF162IUBSZrm = 6063 + + VCVTBF162IUBSZrmb = 6064 + + VCVTBF162IUBSZrmbk = 6065 + + VCVTBF162IUBSZrmbkz = 6066 + + VCVTBF162IUBSZrmk = 6067 + + VCVTBF162IUBSZrmkz = 6068 + + VCVTBF162IUBSZrr = 6069 + + VCVTBF162IUBSZrrk = 6070 + + VCVTBF162IUBSZrrkz = 6071 + + VCVTBIASPH2BF8SZ128rm = 6072 + + VCVTBIASPH2BF8SZ128rmb = 6073 + + VCVTBIASPH2BF8SZ128rmbk = 6074 + + VCVTBIASPH2BF8SZ128rmbkz = 6075 + + VCVTBIASPH2BF8SZ128rmk = 6076 + + VCVTBIASPH2BF8SZ128rmkz = 6077 + + VCVTBIASPH2BF8SZ128rr = 6078 + + VCVTBIASPH2BF8SZ128rrk = 6079 + + VCVTBIASPH2BF8SZ128rrkz = 6080 + + VCVTBIASPH2BF8SZ256rm = 6081 + + VCVTBIASPH2BF8SZ256rmb = 6082 + + VCVTBIASPH2BF8SZ256rmbk = 6083 + + VCVTBIASPH2BF8SZ256rmbkz = 6084 + + VCVTBIASPH2BF8SZ256rmk = 6085 + + VCVTBIASPH2BF8SZ256rmkz = 6086 + + VCVTBIASPH2BF8SZ256rr = 6087 + + VCVTBIASPH2BF8SZ256rrk = 6088 + + VCVTBIASPH2BF8SZ256rrkz = 6089 + + VCVTBIASPH2BF8SZrm = 6090 + + VCVTBIASPH2BF8SZrmb = 6091 + + VCVTBIASPH2BF8SZrmbk = 6092 + + VCVTBIASPH2BF8SZrmbkz = 6093 + + VCVTBIASPH2BF8SZrmk = 6094 + + VCVTBIASPH2BF8SZrmkz = 6095 + + VCVTBIASPH2BF8SZrr = 6096 + + VCVTBIASPH2BF8SZrrk = 6097 + + VCVTBIASPH2BF8SZrrkz = 6098 + + VCVTBIASPH2BF8Z128rm = 6099 + + VCVTBIASPH2BF8Z128rmb = 6100 + + VCVTBIASPH2BF8Z128rmbk = 6101 + + VCVTBIASPH2BF8Z128rmbkz = 6102 + + VCVTBIASPH2BF8Z128rmk = 6103 + + VCVTBIASPH2BF8Z128rmkz = 6104 + + VCVTBIASPH2BF8Z128rr = 6105 + + VCVTBIASPH2BF8Z128rrk = 6106 + + VCVTBIASPH2BF8Z128rrkz = 6107 + + VCVTBIASPH2BF8Z256rm = 6108 + + VCVTBIASPH2BF8Z256rmb = 6109 + + VCVTBIASPH2BF8Z256rmbk = 6110 + + VCVTBIASPH2BF8Z256rmbkz = 6111 + + VCVTBIASPH2BF8Z256rmk = 6112 + + VCVTBIASPH2BF8Z256rmkz = 6113 + + VCVTBIASPH2BF8Z256rr = 6114 + + VCVTBIASPH2BF8Z256rrk = 6115 + + VCVTBIASPH2BF8Z256rrkz = 6116 + + VCVTBIASPH2BF8Zrm = 6117 + + VCVTBIASPH2BF8Zrmb = 6118 + + VCVTBIASPH2BF8Zrmbk = 6119 + + VCVTBIASPH2BF8Zrmbkz = 6120 + + VCVTBIASPH2BF8Zrmk = 6121 + + VCVTBIASPH2BF8Zrmkz = 6122 + + VCVTBIASPH2BF8Zrr = 6123 + + VCVTBIASPH2BF8Zrrk = 6124 + + VCVTBIASPH2BF8Zrrkz = 6125 + + VCVTBIASPH2HF8SZ128rm = 6126 + + VCVTBIASPH2HF8SZ128rmb = 6127 + + VCVTBIASPH2HF8SZ128rmbk = 6128 + + VCVTBIASPH2HF8SZ128rmbkz = 6129 + + VCVTBIASPH2HF8SZ128rmk = 6130 + + VCVTBIASPH2HF8SZ128rmkz = 6131 + + VCVTBIASPH2HF8SZ128rr = 6132 + + VCVTBIASPH2HF8SZ128rrk = 6133 + + VCVTBIASPH2HF8SZ128rrkz = 6134 + + VCVTBIASPH2HF8SZ256rm = 6135 + + VCVTBIASPH2HF8SZ256rmb = 6136 + + VCVTBIASPH2HF8SZ256rmbk = 6137 + + VCVTBIASPH2HF8SZ256rmbkz = 6138 + + VCVTBIASPH2HF8SZ256rmk = 6139 + + VCVTBIASPH2HF8SZ256rmkz = 6140 + + VCVTBIASPH2HF8SZ256rr = 6141 + + VCVTBIASPH2HF8SZ256rrk = 6142 + + VCVTBIASPH2HF8SZ256rrkz = 6143 + + VCVTBIASPH2HF8SZrm = 6144 + + VCVTBIASPH2HF8SZrmb = 6145 + + VCVTBIASPH2HF8SZrmbk = 6146 + + VCVTBIASPH2HF8SZrmbkz = 6147 + + VCVTBIASPH2HF8SZrmk = 6148 + + VCVTBIASPH2HF8SZrmkz = 6149 + + VCVTBIASPH2HF8SZrr = 6150 + + VCVTBIASPH2HF8SZrrk = 6151 + + VCVTBIASPH2HF8SZrrkz = 6152 + + VCVTBIASPH2HF8Z128rm = 6153 + + VCVTBIASPH2HF8Z128rmb = 6154 + + VCVTBIASPH2HF8Z128rmbk = 6155 + + VCVTBIASPH2HF8Z128rmbkz = 6156 + + VCVTBIASPH2HF8Z128rmk = 6157 + + VCVTBIASPH2HF8Z128rmkz = 6158 + + VCVTBIASPH2HF8Z128rr = 6159 + + VCVTBIASPH2HF8Z128rrk = 6160 + + VCVTBIASPH2HF8Z128rrkz = 6161 + + VCVTBIASPH2HF8Z256rm = 6162 + + VCVTBIASPH2HF8Z256rmb = 6163 + + VCVTBIASPH2HF8Z256rmbk = 6164 + + VCVTBIASPH2HF8Z256rmbkz = 6165 + + VCVTBIASPH2HF8Z256rmk = 6166 + + VCVTBIASPH2HF8Z256rmkz = 6167 + + VCVTBIASPH2HF8Z256rr = 6168 + + VCVTBIASPH2HF8Z256rrk = 6169 + + VCVTBIASPH2HF8Z256rrkz = 6170 + + VCVTBIASPH2HF8Zrm = 6171 + + VCVTBIASPH2HF8Zrmb = 6172 + + VCVTBIASPH2HF8Zrmbk = 6173 + + VCVTBIASPH2HF8Zrmbkz = 6174 + + VCVTBIASPH2HF8Zrmk = 6175 + + VCVTBIASPH2HF8Zrmkz = 6176 + + VCVTBIASPH2HF8Zrr = 6177 + + VCVTBIASPH2HF8Zrrk = 6178 + + VCVTBIASPH2HF8Zrrkz = 6179 + + VCVTDQ2PDYrm = 6180 + + VCVTDQ2PDYrr = 6181 + + VCVTDQ2PDZ128rm = 6182 + + VCVTDQ2PDZ128rmb = 6183 + + VCVTDQ2PDZ128rmbk = 6184 + + VCVTDQ2PDZ128rmbkz = 6185 + + VCVTDQ2PDZ128rmk = 6186 + + VCVTDQ2PDZ128rmkz = 6187 + + VCVTDQ2PDZ128rr = 6188 + + VCVTDQ2PDZ128rrk = 6189 + + VCVTDQ2PDZ128rrkz = 6190 + + VCVTDQ2PDZ256rm = 6191 + + VCVTDQ2PDZ256rmb = 6192 + + VCVTDQ2PDZ256rmbk = 6193 + + VCVTDQ2PDZ256rmbkz = 6194 + + VCVTDQ2PDZ256rmk = 6195 + + VCVTDQ2PDZ256rmkz = 6196 + + VCVTDQ2PDZ256rr = 6197 + + VCVTDQ2PDZ256rrk = 6198 + + VCVTDQ2PDZ256rrkz = 6199 + + VCVTDQ2PDZrm = 6200 + + VCVTDQ2PDZrmb = 6201 + + VCVTDQ2PDZrmbk = 6202 + + VCVTDQ2PDZrmbkz = 6203 + + VCVTDQ2PDZrmk = 6204 + + VCVTDQ2PDZrmkz = 6205 + + VCVTDQ2PDZrr = 6206 + + VCVTDQ2PDZrrk = 6207 + + VCVTDQ2PDZrrkz = 6208 + + VCVTDQ2PDrm = 6209 + + VCVTDQ2PDrr = 6210 + + VCVTDQ2PHZ128rm = 6211 + + VCVTDQ2PHZ128rmb = 6212 + + VCVTDQ2PHZ128rmbk = 6213 + + VCVTDQ2PHZ128rmbkz = 6214 + + VCVTDQ2PHZ128rmk = 6215 + + VCVTDQ2PHZ128rmkz = 6216 + + VCVTDQ2PHZ128rr = 6217 + + VCVTDQ2PHZ128rrk = 6218 + + VCVTDQ2PHZ128rrkz = 6219 + + VCVTDQ2PHZ256rm = 6220 + + VCVTDQ2PHZ256rmb = 6221 + + VCVTDQ2PHZ256rmbk = 6222 + + VCVTDQ2PHZ256rmbkz = 6223 + + VCVTDQ2PHZ256rmk = 6224 + + VCVTDQ2PHZ256rmkz = 6225 + + VCVTDQ2PHZ256rr = 6226 + + VCVTDQ2PHZ256rrk = 6227 + + VCVTDQ2PHZ256rrkz = 6228 + + VCVTDQ2PHZrm = 6229 + + VCVTDQ2PHZrmb = 6230 + + VCVTDQ2PHZrmbk = 6231 + + VCVTDQ2PHZrmbkz = 6232 + + VCVTDQ2PHZrmk = 6233 + + VCVTDQ2PHZrmkz = 6234 + + VCVTDQ2PHZrr = 6235 + + VCVTDQ2PHZrrb = 6236 + + VCVTDQ2PHZrrbk = 6237 + + VCVTDQ2PHZrrbkz = 6238 + + VCVTDQ2PHZrrk = 6239 + + VCVTDQ2PHZrrkz = 6240 + + VCVTDQ2PSYrm = 6241 + + VCVTDQ2PSYrr = 6242 + + VCVTDQ2PSZ128rm = 6243 + + VCVTDQ2PSZ128rmb = 6244 + + VCVTDQ2PSZ128rmbk = 6245 + + VCVTDQ2PSZ128rmbkz = 6246 + + VCVTDQ2PSZ128rmk = 6247 + + VCVTDQ2PSZ128rmkz = 6248 + + VCVTDQ2PSZ128rr = 6249 + + VCVTDQ2PSZ128rrk = 6250 + + VCVTDQ2PSZ128rrkz = 6251 + + VCVTDQ2PSZ256rm = 6252 + + VCVTDQ2PSZ256rmb = 6253 + + VCVTDQ2PSZ256rmbk = 6254 + + VCVTDQ2PSZ256rmbkz = 6255 + + VCVTDQ2PSZ256rmk = 6256 + + VCVTDQ2PSZ256rmkz = 6257 + + VCVTDQ2PSZ256rr = 6258 + + VCVTDQ2PSZ256rrk = 6259 + + VCVTDQ2PSZ256rrkz = 6260 + + VCVTDQ2PSZrm = 6261 + + VCVTDQ2PSZrmb = 6262 + + VCVTDQ2PSZrmbk = 6263 + + VCVTDQ2PSZrmbkz = 6264 + + VCVTDQ2PSZrmk = 6265 + + VCVTDQ2PSZrmkz = 6266 + + VCVTDQ2PSZrr = 6267 + + VCVTDQ2PSZrrb = 6268 + + VCVTDQ2PSZrrbk = 6269 + + VCVTDQ2PSZrrbkz = 6270 + + VCVTDQ2PSZrrk = 6271 + + VCVTDQ2PSZrrkz = 6272 + + VCVTDQ2PSrm = 6273 + + VCVTDQ2PSrr = 6274 + + VCVTHF82PHZ128rm = 6275 + + VCVTHF82PHZ128rmk = 6276 + + VCVTHF82PHZ128rmkz = 6277 + + VCVTHF82PHZ128rr = 6278 + + VCVTHF82PHZ128rrk = 6279 + + VCVTHF82PHZ128rrkz = 6280 + + VCVTHF82PHZ256rm = 6281 + + VCVTHF82PHZ256rmk = 6282 + + VCVTHF82PHZ256rmkz = 6283 + + VCVTHF82PHZ256rr = 6284 + + VCVTHF82PHZ256rrk = 6285 + + VCVTHF82PHZ256rrkz = 6286 + + VCVTHF82PHZrm = 6287 + + VCVTHF82PHZrmk = 6288 + + VCVTHF82PHZrmkz = 6289 + + VCVTHF82PHZrr = 6290 + + VCVTHF82PHZrrk = 6291 + + VCVTHF82PHZrrkz = 6292 + + VCVTNE2PS2BF16Z128rm = 6293 + + VCVTNE2PS2BF16Z128rmb = 6294 + + VCVTNE2PS2BF16Z128rmbk = 6295 + + VCVTNE2PS2BF16Z128rmbkz = 6296 + + VCVTNE2PS2BF16Z128rmk = 6297 + + VCVTNE2PS2BF16Z128rmkz = 6298 + + VCVTNE2PS2BF16Z128rr = 6299 + + VCVTNE2PS2BF16Z128rrk = 6300 + + VCVTNE2PS2BF16Z128rrkz = 6301 + + VCVTNE2PS2BF16Z256rm = 6302 + + VCVTNE2PS2BF16Z256rmb = 6303 + + VCVTNE2PS2BF16Z256rmbk = 6304 + + VCVTNE2PS2BF16Z256rmbkz = 6305 + + VCVTNE2PS2BF16Z256rmk = 6306 + + VCVTNE2PS2BF16Z256rmkz = 6307 + + VCVTNE2PS2BF16Z256rr = 6308 + + VCVTNE2PS2BF16Z256rrk = 6309 + + VCVTNE2PS2BF16Z256rrkz = 6310 + + VCVTNE2PS2BF16Zrm = 6311 + + VCVTNE2PS2BF16Zrmb = 6312 + + VCVTNE2PS2BF16Zrmbk = 6313 + + VCVTNE2PS2BF16Zrmbkz = 6314 + + VCVTNE2PS2BF16Zrmk = 6315 + + VCVTNE2PS2BF16Zrmkz = 6316 + + VCVTNE2PS2BF16Zrr = 6317 + + VCVTNE2PS2BF16Zrrk = 6318 + + VCVTNE2PS2BF16Zrrkz = 6319 + + VCVTNEEBF162PSYrm = 6320 + + VCVTNEEBF162PSrm = 6321 + + VCVTNEEPH2PSYrm = 6322 + + VCVTNEEPH2PSrm = 6323 + + VCVTNEOBF162PSYrm = 6324 + + VCVTNEOBF162PSrm = 6325 + + VCVTNEOPH2PSYrm = 6326 + + VCVTNEOPH2PSrm = 6327 + + VCVTNEPS2BF16Yrm = 6328 + + VCVTNEPS2BF16Yrr = 6329 + + VCVTNEPS2BF16Z128rm = 6330 + + VCVTNEPS2BF16Z128rmb = 6331 + + VCVTNEPS2BF16Z128rmbk = 6332 + + VCVTNEPS2BF16Z128rmbkz = 6333 + + VCVTNEPS2BF16Z128rmk = 6334 + + VCVTNEPS2BF16Z128rmkz = 6335 + + VCVTNEPS2BF16Z128rr = 6336 + + VCVTNEPS2BF16Z128rrk = 6337 + + VCVTNEPS2BF16Z128rrkz = 6338 + + VCVTNEPS2BF16Z256rm = 6339 + + VCVTNEPS2BF16Z256rmb = 6340 + + VCVTNEPS2BF16Z256rmbk = 6341 + + VCVTNEPS2BF16Z256rmbkz = 6342 + + VCVTNEPS2BF16Z256rmk = 6343 + + VCVTNEPS2BF16Z256rmkz = 6344 + + VCVTNEPS2BF16Z256rr = 6345 + + VCVTNEPS2BF16Z256rrk = 6346 + + VCVTNEPS2BF16Z256rrkz = 6347 + + VCVTNEPS2BF16Zrm = 6348 + + VCVTNEPS2BF16Zrmb = 6349 + + VCVTNEPS2BF16Zrmbk = 6350 + + VCVTNEPS2BF16Zrmbkz = 6351 + + VCVTNEPS2BF16Zrmk = 6352 + + VCVTNEPS2BF16Zrmkz = 6353 + + VCVTNEPS2BF16Zrr = 6354 + + VCVTNEPS2BF16Zrrk = 6355 + + VCVTNEPS2BF16Zrrkz = 6356 + + VCVTNEPS2BF16rm = 6357 + + VCVTNEPS2BF16rr = 6358 + + VCVTPD2DQYrm = 6359 + + VCVTPD2DQYrr = 6360 + + VCVTPD2DQZ128rm = 6361 + + VCVTPD2DQZ128rmb = 6362 + + VCVTPD2DQZ128rmbk = 6363 + + VCVTPD2DQZ128rmbkz = 6364 + + VCVTPD2DQZ128rmk = 6365 + + VCVTPD2DQZ128rmkz = 6366 + + VCVTPD2DQZ128rr = 6367 + + VCVTPD2DQZ128rrk = 6368 + + VCVTPD2DQZ128rrkz = 6369 + + VCVTPD2DQZ256rm = 6370 + + VCVTPD2DQZ256rmb = 6371 + + VCVTPD2DQZ256rmbk = 6372 + + VCVTPD2DQZ256rmbkz = 6373 + + VCVTPD2DQZ256rmk = 6374 + + VCVTPD2DQZ256rmkz = 6375 + + VCVTPD2DQZ256rr = 6376 + + VCVTPD2DQZ256rrk = 6377 + + VCVTPD2DQZ256rrkz = 6378 + + VCVTPD2DQZrm = 6379 + + VCVTPD2DQZrmb = 6380 + + VCVTPD2DQZrmbk = 6381 + + VCVTPD2DQZrmbkz = 6382 + + VCVTPD2DQZrmk = 6383 + + VCVTPD2DQZrmkz = 6384 + + VCVTPD2DQZrr = 6385 + + VCVTPD2DQZrrb = 6386 + + VCVTPD2DQZrrbk = 6387 + + VCVTPD2DQZrrbkz = 6388 + + VCVTPD2DQZrrk = 6389 + + VCVTPD2DQZrrkz = 6390 + + VCVTPD2DQrm = 6391 + + VCVTPD2DQrr = 6392 + + VCVTPD2PHZ128rm = 6393 + + VCVTPD2PHZ128rmb = 6394 + + VCVTPD2PHZ128rmbk = 6395 + + VCVTPD2PHZ128rmbkz = 6396 + + VCVTPD2PHZ128rmk = 6397 + + VCVTPD2PHZ128rmkz = 6398 + + VCVTPD2PHZ128rr = 6399 + + VCVTPD2PHZ128rrk = 6400 + + VCVTPD2PHZ128rrkz = 6401 + + VCVTPD2PHZ256rm = 6402 + + VCVTPD2PHZ256rmb = 6403 + + VCVTPD2PHZ256rmbk = 6404 + + VCVTPD2PHZ256rmbkz = 6405 + + VCVTPD2PHZ256rmk = 6406 + + VCVTPD2PHZ256rmkz = 6407 + + VCVTPD2PHZ256rr = 6408 + + VCVTPD2PHZ256rrk = 6409 + + VCVTPD2PHZ256rrkz = 6410 + + VCVTPD2PHZrm = 6411 + + VCVTPD2PHZrmb = 6412 + + VCVTPD2PHZrmbk = 6413 + + VCVTPD2PHZrmbkz = 6414 + + VCVTPD2PHZrmk = 6415 + + VCVTPD2PHZrmkz = 6416 + + VCVTPD2PHZrr = 6417 + + VCVTPD2PHZrrb = 6418 + + VCVTPD2PHZrrbk = 6419 + + VCVTPD2PHZrrbkz = 6420 + + VCVTPD2PHZrrk = 6421 + + VCVTPD2PHZrrkz = 6422 + + VCVTPD2PSYrm = 6423 + + VCVTPD2PSYrr = 6424 + + VCVTPD2PSZ128rm = 6425 + + VCVTPD2PSZ128rmb = 6426 + + VCVTPD2PSZ128rmbk = 6427 + + VCVTPD2PSZ128rmbkz = 6428 + + VCVTPD2PSZ128rmk = 6429 + + VCVTPD2PSZ128rmkz = 6430 + + VCVTPD2PSZ128rr = 6431 + + VCVTPD2PSZ128rrk = 6432 + + VCVTPD2PSZ128rrkz = 6433 + + VCVTPD2PSZ256rm = 6434 + + VCVTPD2PSZ256rmb = 6435 + + VCVTPD2PSZ256rmbk = 6436 + + VCVTPD2PSZ256rmbkz = 6437 + + VCVTPD2PSZ256rmk = 6438 + + VCVTPD2PSZ256rmkz = 6439 + + VCVTPD2PSZ256rr = 6440 + + VCVTPD2PSZ256rrk = 6441 + + VCVTPD2PSZ256rrkz = 6442 + + VCVTPD2PSZrm = 6443 + + VCVTPD2PSZrmb = 6444 + + VCVTPD2PSZrmbk = 6445 + + VCVTPD2PSZrmbkz = 6446 + + VCVTPD2PSZrmk = 6447 + + VCVTPD2PSZrmkz = 6448 + + VCVTPD2PSZrr = 6449 + + VCVTPD2PSZrrb = 6450 + + VCVTPD2PSZrrbk = 6451 + + VCVTPD2PSZrrbkz = 6452 + + VCVTPD2PSZrrk = 6453 + + VCVTPD2PSZrrkz = 6454 + + VCVTPD2PSrm = 6455 + + VCVTPD2PSrr = 6456 + + VCVTPD2QQZ128rm = 6457 + + VCVTPD2QQZ128rmb = 6458 + + VCVTPD2QQZ128rmbk = 6459 + + VCVTPD2QQZ128rmbkz = 6460 + + VCVTPD2QQZ128rmk = 6461 + + VCVTPD2QQZ128rmkz = 6462 + + VCVTPD2QQZ128rr = 6463 + + VCVTPD2QQZ128rrk = 6464 + + VCVTPD2QQZ128rrkz = 6465 + + VCVTPD2QQZ256rm = 6466 + + VCVTPD2QQZ256rmb = 6467 + + VCVTPD2QQZ256rmbk = 6468 + + VCVTPD2QQZ256rmbkz = 6469 + + VCVTPD2QQZ256rmk = 6470 + + VCVTPD2QQZ256rmkz = 6471 + + VCVTPD2QQZ256rr = 6472 + + VCVTPD2QQZ256rrk = 6473 + + VCVTPD2QQZ256rrkz = 6474 + + VCVTPD2QQZrm = 6475 + + VCVTPD2QQZrmb = 6476 + + VCVTPD2QQZrmbk = 6477 + + VCVTPD2QQZrmbkz = 6478 + + VCVTPD2QQZrmk = 6479 + + VCVTPD2QQZrmkz = 6480 + + VCVTPD2QQZrr = 6481 + + VCVTPD2QQZrrb = 6482 + + VCVTPD2QQZrrbk = 6483 + + VCVTPD2QQZrrbkz = 6484 + + VCVTPD2QQZrrk = 6485 + + VCVTPD2QQZrrkz = 6486 + + VCVTPD2UDQZ128rm = 6487 + + VCVTPD2UDQZ128rmb = 6488 + + VCVTPD2UDQZ128rmbk = 6489 + + VCVTPD2UDQZ128rmbkz = 6490 + + VCVTPD2UDQZ128rmk = 6491 + + VCVTPD2UDQZ128rmkz = 6492 + + VCVTPD2UDQZ128rr = 6493 + + VCVTPD2UDQZ128rrk = 6494 + + VCVTPD2UDQZ128rrkz = 6495 + + VCVTPD2UDQZ256rm = 6496 + + VCVTPD2UDQZ256rmb = 6497 + + VCVTPD2UDQZ256rmbk = 6498 + + VCVTPD2UDQZ256rmbkz = 6499 + + VCVTPD2UDQZ256rmk = 6500 + + VCVTPD2UDQZ256rmkz = 6501 + + VCVTPD2UDQZ256rr = 6502 + + VCVTPD2UDQZ256rrk = 6503 + + VCVTPD2UDQZ256rrkz = 6504 + + VCVTPD2UDQZrm = 6505 + + VCVTPD2UDQZrmb = 6506 + + VCVTPD2UDQZrmbk = 6507 + + VCVTPD2UDQZrmbkz = 6508 + + VCVTPD2UDQZrmk = 6509 + + VCVTPD2UDQZrmkz = 6510 + + VCVTPD2UDQZrr = 6511 + + VCVTPD2UDQZrrb = 6512 + + VCVTPD2UDQZrrbk = 6513 + + VCVTPD2UDQZrrbkz = 6514 + + VCVTPD2UDQZrrk = 6515 + + VCVTPD2UDQZrrkz = 6516 + + VCVTPD2UQQZ128rm = 6517 + + VCVTPD2UQQZ128rmb = 6518 + + VCVTPD2UQQZ128rmbk = 6519 + + VCVTPD2UQQZ128rmbkz = 6520 + + VCVTPD2UQQZ128rmk = 6521 + + VCVTPD2UQQZ128rmkz = 6522 + + VCVTPD2UQQZ128rr = 6523 + + VCVTPD2UQQZ128rrk = 6524 + + VCVTPD2UQQZ128rrkz = 6525 + + VCVTPD2UQQZ256rm = 6526 + + VCVTPD2UQQZ256rmb = 6527 + + VCVTPD2UQQZ256rmbk = 6528 + + VCVTPD2UQQZ256rmbkz = 6529 + + VCVTPD2UQQZ256rmk = 6530 + + VCVTPD2UQQZ256rmkz = 6531 + + VCVTPD2UQQZ256rr = 6532 + + VCVTPD2UQQZ256rrk = 6533 + + VCVTPD2UQQZ256rrkz = 6534 + + VCVTPD2UQQZrm = 6535 + + VCVTPD2UQQZrmb = 6536 + + VCVTPD2UQQZrmbk = 6537 + + VCVTPD2UQQZrmbkz = 6538 + + VCVTPD2UQQZrmk = 6539 + + VCVTPD2UQQZrmkz = 6540 + + VCVTPD2UQQZrr = 6541 + + VCVTPD2UQQZrrb = 6542 + + VCVTPD2UQQZrrbk = 6543 + + VCVTPD2UQQZrrbkz = 6544 + + VCVTPD2UQQZrrk = 6545 + + VCVTPD2UQQZrrkz = 6546 + + VCVTPH2BF8SZ128rm = 6547 + + VCVTPH2BF8SZ128rmb = 6548 + + VCVTPH2BF8SZ128rmbk = 6549 + + VCVTPH2BF8SZ128rmbkz = 6550 + + VCVTPH2BF8SZ128rmk = 6551 + + VCVTPH2BF8SZ128rmkz = 6552 + + VCVTPH2BF8SZ128rr = 6553 + + VCVTPH2BF8SZ128rrk = 6554 + + VCVTPH2BF8SZ128rrkz = 6555 + + VCVTPH2BF8SZ256rm = 6556 + + VCVTPH2BF8SZ256rmb = 6557 + + VCVTPH2BF8SZ256rmbk = 6558 + + VCVTPH2BF8SZ256rmbkz = 6559 + + VCVTPH2BF8SZ256rmk = 6560 + + VCVTPH2BF8SZ256rmkz = 6561 + + VCVTPH2BF8SZ256rr = 6562 + + VCVTPH2BF8SZ256rrk = 6563 + + VCVTPH2BF8SZ256rrkz = 6564 + + VCVTPH2BF8SZrm = 6565 + + VCVTPH2BF8SZrmb = 6566 + + VCVTPH2BF8SZrmbk = 6567 + + VCVTPH2BF8SZrmbkz = 6568 + + VCVTPH2BF8SZrmk = 6569 + + VCVTPH2BF8SZrmkz = 6570 + + VCVTPH2BF8SZrr = 6571 + + VCVTPH2BF8SZrrk = 6572 + + VCVTPH2BF8SZrrkz = 6573 + + VCVTPH2BF8Z128rm = 6574 + + VCVTPH2BF8Z128rmb = 6575 + + VCVTPH2BF8Z128rmbk = 6576 + + VCVTPH2BF8Z128rmbkz = 6577 + + VCVTPH2BF8Z128rmk = 6578 + + VCVTPH2BF8Z128rmkz = 6579 + + VCVTPH2BF8Z128rr = 6580 + + VCVTPH2BF8Z128rrk = 6581 + + VCVTPH2BF8Z128rrkz = 6582 + + VCVTPH2BF8Z256rm = 6583 + + VCVTPH2BF8Z256rmb = 6584 + + VCVTPH2BF8Z256rmbk = 6585 + + VCVTPH2BF8Z256rmbkz = 6586 + + VCVTPH2BF8Z256rmk = 6587 + + VCVTPH2BF8Z256rmkz = 6588 + + VCVTPH2BF8Z256rr = 6589 + + VCVTPH2BF8Z256rrk = 6590 + + VCVTPH2BF8Z256rrkz = 6591 + + VCVTPH2BF8Zrm = 6592 + + VCVTPH2BF8Zrmb = 6593 + + VCVTPH2BF8Zrmbk = 6594 + + VCVTPH2BF8Zrmbkz = 6595 + + VCVTPH2BF8Zrmk = 6596 + + VCVTPH2BF8Zrmkz = 6597 + + VCVTPH2BF8Zrr = 6598 + + VCVTPH2BF8Zrrk = 6599 + + VCVTPH2BF8Zrrkz = 6600 + + VCVTPH2DQZ128rm = 6601 + + VCVTPH2DQZ128rmb = 6602 + + VCVTPH2DQZ128rmbk = 6603 + + VCVTPH2DQZ128rmbkz = 6604 + + VCVTPH2DQZ128rmk = 6605 + + VCVTPH2DQZ128rmkz = 6606 + + VCVTPH2DQZ128rr = 6607 + + VCVTPH2DQZ128rrk = 6608 + + VCVTPH2DQZ128rrkz = 6609 + + VCVTPH2DQZ256rm = 6610 + + VCVTPH2DQZ256rmb = 6611 + + VCVTPH2DQZ256rmbk = 6612 + + VCVTPH2DQZ256rmbkz = 6613 + + VCVTPH2DQZ256rmk = 6614 + + VCVTPH2DQZ256rmkz = 6615 + + VCVTPH2DQZ256rr = 6616 + + VCVTPH2DQZ256rrk = 6617 + + VCVTPH2DQZ256rrkz = 6618 + + VCVTPH2DQZrm = 6619 + + VCVTPH2DQZrmb = 6620 + + VCVTPH2DQZrmbk = 6621 + + VCVTPH2DQZrmbkz = 6622 + + VCVTPH2DQZrmk = 6623 + + VCVTPH2DQZrmkz = 6624 + + VCVTPH2DQZrr = 6625 + + VCVTPH2DQZrrb = 6626 + + VCVTPH2DQZrrbk = 6627 + + VCVTPH2DQZrrbkz = 6628 + + VCVTPH2DQZrrk = 6629 + + VCVTPH2DQZrrkz = 6630 + + VCVTPH2HF8SZ128rm = 6631 + + VCVTPH2HF8SZ128rmb = 6632 + + VCVTPH2HF8SZ128rmbk = 6633 + + VCVTPH2HF8SZ128rmbkz = 6634 + + VCVTPH2HF8SZ128rmk = 6635 + + VCVTPH2HF8SZ128rmkz = 6636 + + VCVTPH2HF8SZ128rr = 6637 + + VCVTPH2HF8SZ128rrk = 6638 + + VCVTPH2HF8SZ128rrkz = 6639 + + VCVTPH2HF8SZ256rm = 6640 + + VCVTPH2HF8SZ256rmb = 6641 + + VCVTPH2HF8SZ256rmbk = 6642 + + VCVTPH2HF8SZ256rmbkz = 6643 + + VCVTPH2HF8SZ256rmk = 6644 + + VCVTPH2HF8SZ256rmkz = 6645 + + VCVTPH2HF8SZ256rr = 6646 + + VCVTPH2HF8SZ256rrk = 6647 + + VCVTPH2HF8SZ256rrkz = 6648 + + VCVTPH2HF8SZrm = 6649 + + VCVTPH2HF8SZrmb = 6650 + + VCVTPH2HF8SZrmbk = 6651 + + VCVTPH2HF8SZrmbkz = 6652 + + VCVTPH2HF8SZrmk = 6653 + + VCVTPH2HF8SZrmkz = 6654 + + VCVTPH2HF8SZrr = 6655 + + VCVTPH2HF8SZrrk = 6656 + + VCVTPH2HF8SZrrkz = 6657 + + VCVTPH2HF8Z128rm = 6658 + + VCVTPH2HF8Z128rmb = 6659 + + VCVTPH2HF8Z128rmbk = 6660 + + VCVTPH2HF8Z128rmbkz = 6661 + + VCVTPH2HF8Z128rmk = 6662 + + VCVTPH2HF8Z128rmkz = 6663 + + VCVTPH2HF8Z128rr = 6664 + + VCVTPH2HF8Z128rrk = 6665 + + VCVTPH2HF8Z128rrkz = 6666 + + VCVTPH2HF8Z256rm = 6667 + + VCVTPH2HF8Z256rmb = 6668 + + VCVTPH2HF8Z256rmbk = 6669 + + VCVTPH2HF8Z256rmbkz = 6670 + + VCVTPH2HF8Z256rmk = 6671 + + VCVTPH2HF8Z256rmkz = 6672 + + VCVTPH2HF8Z256rr = 6673 + + VCVTPH2HF8Z256rrk = 6674 + + VCVTPH2HF8Z256rrkz = 6675 + + VCVTPH2HF8Zrm = 6676 + + VCVTPH2HF8Zrmb = 6677 + + VCVTPH2HF8Zrmbk = 6678 + + VCVTPH2HF8Zrmbkz = 6679 + + VCVTPH2HF8Zrmk = 6680 + + VCVTPH2HF8Zrmkz = 6681 + + VCVTPH2HF8Zrr = 6682 + + VCVTPH2HF8Zrrk = 6683 + + VCVTPH2HF8Zrrkz = 6684 + + VCVTPH2IBSZ128rm = 6685 + + VCVTPH2IBSZ128rmb = 6686 + + VCVTPH2IBSZ128rmbk = 6687 + + VCVTPH2IBSZ128rmbkz = 6688 + + VCVTPH2IBSZ128rmk = 6689 + + VCVTPH2IBSZ128rmkz = 6690 + + VCVTPH2IBSZ128rr = 6691 + + VCVTPH2IBSZ128rrk = 6692 + + VCVTPH2IBSZ128rrkz = 6693 + + VCVTPH2IBSZ256rm = 6694 + + VCVTPH2IBSZ256rmb = 6695 + + VCVTPH2IBSZ256rmbk = 6696 + + VCVTPH2IBSZ256rmbkz = 6697 + + VCVTPH2IBSZ256rmk = 6698 + + VCVTPH2IBSZ256rmkz = 6699 + + VCVTPH2IBSZ256rr = 6700 + + VCVTPH2IBSZ256rrk = 6701 + + VCVTPH2IBSZ256rrkz = 6702 + + VCVTPH2IBSZrm = 6703 + + VCVTPH2IBSZrmb = 6704 + + VCVTPH2IBSZrmbk = 6705 + + VCVTPH2IBSZrmbkz = 6706 + + VCVTPH2IBSZrmk = 6707 + + VCVTPH2IBSZrmkz = 6708 + + VCVTPH2IBSZrr = 6709 + + VCVTPH2IBSZrrb = 6710 + + VCVTPH2IBSZrrbk = 6711 + + VCVTPH2IBSZrrbkz = 6712 + + VCVTPH2IBSZrrk = 6713 + + VCVTPH2IBSZrrkz = 6714 + + VCVTPH2IUBSZ128rm = 6715 + + VCVTPH2IUBSZ128rmb = 6716 + + VCVTPH2IUBSZ128rmbk = 6717 + + VCVTPH2IUBSZ128rmbkz = 6718 + + VCVTPH2IUBSZ128rmk = 6719 + + VCVTPH2IUBSZ128rmkz = 6720 + + VCVTPH2IUBSZ128rr = 6721 + + VCVTPH2IUBSZ128rrk = 6722 + + VCVTPH2IUBSZ128rrkz = 6723 + + VCVTPH2IUBSZ256rm = 6724 + + VCVTPH2IUBSZ256rmb = 6725 + + VCVTPH2IUBSZ256rmbk = 6726 + + VCVTPH2IUBSZ256rmbkz = 6727 + + VCVTPH2IUBSZ256rmk = 6728 + + VCVTPH2IUBSZ256rmkz = 6729 + + VCVTPH2IUBSZ256rr = 6730 + + VCVTPH2IUBSZ256rrk = 6731 + + VCVTPH2IUBSZ256rrkz = 6732 + + VCVTPH2IUBSZrm = 6733 + + VCVTPH2IUBSZrmb = 6734 + + VCVTPH2IUBSZrmbk = 6735 + + VCVTPH2IUBSZrmbkz = 6736 + + VCVTPH2IUBSZrmk = 6737 + + VCVTPH2IUBSZrmkz = 6738 + + VCVTPH2IUBSZrr = 6739 + + VCVTPH2IUBSZrrb = 6740 + + VCVTPH2IUBSZrrbk = 6741 + + VCVTPH2IUBSZrrbkz = 6742 + + VCVTPH2IUBSZrrk = 6743 + + VCVTPH2IUBSZrrkz = 6744 + + VCVTPH2PDZ128rm = 6745 + + VCVTPH2PDZ128rmb = 6746 + + VCVTPH2PDZ128rmbk = 6747 + + VCVTPH2PDZ128rmbkz = 6748 + + VCVTPH2PDZ128rmk = 6749 + + VCVTPH2PDZ128rmkz = 6750 + + VCVTPH2PDZ128rr = 6751 + + VCVTPH2PDZ128rrk = 6752 + + VCVTPH2PDZ128rrkz = 6753 + + VCVTPH2PDZ256rm = 6754 + + VCVTPH2PDZ256rmb = 6755 + + VCVTPH2PDZ256rmbk = 6756 + + VCVTPH2PDZ256rmbkz = 6757 + + VCVTPH2PDZ256rmk = 6758 + + VCVTPH2PDZ256rmkz = 6759 + + VCVTPH2PDZ256rr = 6760 + + VCVTPH2PDZ256rrk = 6761 + + VCVTPH2PDZ256rrkz = 6762 + + VCVTPH2PDZrm = 6763 + + VCVTPH2PDZrmb = 6764 + + VCVTPH2PDZrmbk = 6765 + + VCVTPH2PDZrmbkz = 6766 + + VCVTPH2PDZrmk = 6767 + + VCVTPH2PDZrmkz = 6768 + + VCVTPH2PDZrr = 6769 + + VCVTPH2PDZrrb = 6770 + + VCVTPH2PDZrrbk = 6771 + + VCVTPH2PDZrrbkz = 6772 + + VCVTPH2PDZrrk = 6773 + + VCVTPH2PDZrrkz = 6774 + + VCVTPH2PSXZ128rm = 6775 + + VCVTPH2PSXZ128rmb = 6776 + + VCVTPH2PSXZ128rmbk = 6777 + + VCVTPH2PSXZ128rmbkz = 6778 + + VCVTPH2PSXZ128rmk = 6779 + + VCVTPH2PSXZ128rmkz = 6780 + + VCVTPH2PSXZ128rr = 6781 + + VCVTPH2PSXZ128rrk = 6782 + + VCVTPH2PSXZ128rrkz = 6783 + + VCVTPH2PSXZ256rm = 6784 + + VCVTPH2PSXZ256rmb = 6785 + + VCVTPH2PSXZ256rmbk = 6786 + + VCVTPH2PSXZ256rmbkz = 6787 + + VCVTPH2PSXZ256rmk = 6788 + + VCVTPH2PSXZ256rmkz = 6789 + + VCVTPH2PSXZ256rr = 6790 + + VCVTPH2PSXZ256rrk = 6791 + + VCVTPH2PSXZ256rrkz = 6792 + + VCVTPH2PSXZrm = 6793 + + VCVTPH2PSXZrmb = 6794 + + VCVTPH2PSXZrmbk = 6795 + + VCVTPH2PSXZrmbkz = 6796 + + VCVTPH2PSXZrmk = 6797 + + VCVTPH2PSXZrmkz = 6798 + + VCVTPH2PSXZrr = 6799 + + VCVTPH2PSXZrrb = 6800 + + VCVTPH2PSXZrrbk = 6801 + + VCVTPH2PSXZrrbkz = 6802 + + VCVTPH2PSXZrrk = 6803 + + VCVTPH2PSXZrrkz = 6804 + + VCVTPH2PSYrm = 6805 + + VCVTPH2PSYrr = 6806 + + VCVTPH2PSZ128rm = 6807 + + VCVTPH2PSZ128rmk = 6808 + + VCVTPH2PSZ128rmkz = 6809 + + VCVTPH2PSZ128rr = 6810 + + VCVTPH2PSZ128rrk = 6811 + + VCVTPH2PSZ128rrkz = 6812 + + VCVTPH2PSZ256rm = 6813 + + VCVTPH2PSZ256rmk = 6814 + + VCVTPH2PSZ256rmkz = 6815 + + VCVTPH2PSZ256rr = 6816 + + VCVTPH2PSZ256rrk = 6817 + + VCVTPH2PSZ256rrkz = 6818 + + VCVTPH2PSZrm = 6819 + + VCVTPH2PSZrmk = 6820 + + VCVTPH2PSZrmkz = 6821 + + VCVTPH2PSZrr = 6822 + + VCVTPH2PSZrrb = 6823 + + VCVTPH2PSZrrbk = 6824 + + VCVTPH2PSZrrbkz = 6825 + + VCVTPH2PSZrrk = 6826 + + VCVTPH2PSZrrkz = 6827 + + VCVTPH2PSrm = 6828 + + VCVTPH2PSrr = 6829 + + VCVTPH2QQZ128rm = 6830 + + VCVTPH2QQZ128rmb = 6831 + + VCVTPH2QQZ128rmbk = 6832 + + VCVTPH2QQZ128rmbkz = 6833 + + VCVTPH2QQZ128rmk = 6834 + + VCVTPH2QQZ128rmkz = 6835 + + VCVTPH2QQZ128rr = 6836 + + VCVTPH2QQZ128rrk = 6837 + + VCVTPH2QQZ128rrkz = 6838 + + VCVTPH2QQZ256rm = 6839 + + VCVTPH2QQZ256rmb = 6840 + + VCVTPH2QQZ256rmbk = 6841 + + VCVTPH2QQZ256rmbkz = 6842 + + VCVTPH2QQZ256rmk = 6843 + + VCVTPH2QQZ256rmkz = 6844 + + VCVTPH2QQZ256rr = 6845 + + VCVTPH2QQZ256rrk = 6846 + + VCVTPH2QQZ256rrkz = 6847 + + VCVTPH2QQZrm = 6848 + + VCVTPH2QQZrmb = 6849 + + VCVTPH2QQZrmbk = 6850 + + VCVTPH2QQZrmbkz = 6851 + + VCVTPH2QQZrmk = 6852 + + VCVTPH2QQZrmkz = 6853 + + VCVTPH2QQZrr = 6854 + + VCVTPH2QQZrrb = 6855 + + VCVTPH2QQZrrbk = 6856 + + VCVTPH2QQZrrbkz = 6857 + + VCVTPH2QQZrrk = 6858 + + VCVTPH2QQZrrkz = 6859 + + VCVTPH2UDQZ128rm = 6860 + + VCVTPH2UDQZ128rmb = 6861 + + VCVTPH2UDQZ128rmbk = 6862 + + VCVTPH2UDQZ128rmbkz = 6863 + + VCVTPH2UDQZ128rmk = 6864 + + VCVTPH2UDQZ128rmkz = 6865 + + VCVTPH2UDQZ128rr = 6866 + + VCVTPH2UDQZ128rrk = 6867 + + VCVTPH2UDQZ128rrkz = 6868 + + VCVTPH2UDQZ256rm = 6869 + + VCVTPH2UDQZ256rmb = 6870 + + VCVTPH2UDQZ256rmbk = 6871 + + VCVTPH2UDQZ256rmbkz = 6872 + + VCVTPH2UDQZ256rmk = 6873 + + VCVTPH2UDQZ256rmkz = 6874 + + VCVTPH2UDQZ256rr = 6875 + + VCVTPH2UDQZ256rrk = 6876 + + VCVTPH2UDQZ256rrkz = 6877 + + VCVTPH2UDQZrm = 6878 + + VCVTPH2UDQZrmb = 6879 + + VCVTPH2UDQZrmbk = 6880 + + VCVTPH2UDQZrmbkz = 6881 + + VCVTPH2UDQZrmk = 6882 + + VCVTPH2UDQZrmkz = 6883 + + VCVTPH2UDQZrr = 6884 + + VCVTPH2UDQZrrb = 6885 + + VCVTPH2UDQZrrbk = 6886 + + VCVTPH2UDQZrrbkz = 6887 + + VCVTPH2UDQZrrk = 6888 + + VCVTPH2UDQZrrkz = 6889 + + VCVTPH2UQQZ128rm = 6890 + + VCVTPH2UQQZ128rmb = 6891 + + VCVTPH2UQQZ128rmbk = 6892 + + VCVTPH2UQQZ128rmbkz = 6893 + + VCVTPH2UQQZ128rmk = 6894 + + VCVTPH2UQQZ128rmkz = 6895 + + VCVTPH2UQQZ128rr = 6896 + + VCVTPH2UQQZ128rrk = 6897 + + VCVTPH2UQQZ128rrkz = 6898 + + VCVTPH2UQQZ256rm = 6899 + + VCVTPH2UQQZ256rmb = 6900 + + VCVTPH2UQQZ256rmbk = 6901 + + VCVTPH2UQQZ256rmbkz = 6902 + + VCVTPH2UQQZ256rmk = 6903 + + VCVTPH2UQQZ256rmkz = 6904 + + VCVTPH2UQQZ256rr = 6905 + + VCVTPH2UQQZ256rrk = 6906 + + VCVTPH2UQQZ256rrkz = 6907 + + VCVTPH2UQQZrm = 6908 + + VCVTPH2UQQZrmb = 6909 + + VCVTPH2UQQZrmbk = 6910 + + VCVTPH2UQQZrmbkz = 6911 + + VCVTPH2UQQZrmk = 6912 + + VCVTPH2UQQZrmkz = 6913 + + VCVTPH2UQQZrr = 6914 + + VCVTPH2UQQZrrb = 6915 + + VCVTPH2UQQZrrbk = 6916 + + VCVTPH2UQQZrrbkz = 6917 + + VCVTPH2UQQZrrk = 6918 + + VCVTPH2UQQZrrkz = 6919 + + VCVTPH2UWZ128rm = 6920 + + VCVTPH2UWZ128rmb = 6921 + + VCVTPH2UWZ128rmbk = 6922 + + VCVTPH2UWZ128rmbkz = 6923 + + VCVTPH2UWZ128rmk = 6924 + + VCVTPH2UWZ128rmkz = 6925 + + VCVTPH2UWZ128rr = 6926 + + VCVTPH2UWZ128rrk = 6927 + + VCVTPH2UWZ128rrkz = 6928 + + VCVTPH2UWZ256rm = 6929 + + VCVTPH2UWZ256rmb = 6930 + + VCVTPH2UWZ256rmbk = 6931 + + VCVTPH2UWZ256rmbkz = 6932 + + VCVTPH2UWZ256rmk = 6933 + + VCVTPH2UWZ256rmkz = 6934 + + VCVTPH2UWZ256rr = 6935 + + VCVTPH2UWZ256rrk = 6936 + + VCVTPH2UWZ256rrkz = 6937 + + VCVTPH2UWZrm = 6938 + + VCVTPH2UWZrmb = 6939 + + VCVTPH2UWZrmbk = 6940 + + VCVTPH2UWZrmbkz = 6941 + + VCVTPH2UWZrmk = 6942 + + VCVTPH2UWZrmkz = 6943 + + VCVTPH2UWZrr = 6944 + + VCVTPH2UWZrrb = 6945 + + VCVTPH2UWZrrbk = 6946 + + VCVTPH2UWZrrbkz = 6947 + + VCVTPH2UWZrrk = 6948 + + VCVTPH2UWZrrkz = 6949 + + VCVTPH2WZ128rm = 6950 + + VCVTPH2WZ128rmb = 6951 + + VCVTPH2WZ128rmbk = 6952 + + VCVTPH2WZ128rmbkz = 6953 + + VCVTPH2WZ128rmk = 6954 + + VCVTPH2WZ128rmkz = 6955 + + VCVTPH2WZ128rr = 6956 + + VCVTPH2WZ128rrk = 6957 + + VCVTPH2WZ128rrkz = 6958 + + VCVTPH2WZ256rm = 6959 + + VCVTPH2WZ256rmb = 6960 + + VCVTPH2WZ256rmbk = 6961 + + VCVTPH2WZ256rmbkz = 6962 + + VCVTPH2WZ256rmk = 6963 + + VCVTPH2WZ256rmkz = 6964 + + VCVTPH2WZ256rr = 6965 + + VCVTPH2WZ256rrk = 6966 + + VCVTPH2WZ256rrkz = 6967 + + VCVTPH2WZrm = 6968 + + VCVTPH2WZrmb = 6969 + + VCVTPH2WZrmbk = 6970 + + VCVTPH2WZrmbkz = 6971 + + VCVTPH2WZrmk = 6972 + + VCVTPH2WZrmkz = 6973 + + VCVTPH2WZrr = 6974 + + VCVTPH2WZrrb = 6975 + + VCVTPH2WZrrbk = 6976 + + VCVTPH2WZrrbkz = 6977 + + VCVTPH2WZrrk = 6978 + + VCVTPH2WZrrkz = 6979 + + VCVTPS2DQYrm = 6980 + + VCVTPS2DQYrr = 6981 + + VCVTPS2DQZ128rm = 6982 + + VCVTPS2DQZ128rmb = 6983 + + VCVTPS2DQZ128rmbk = 6984 + + VCVTPS2DQZ128rmbkz = 6985 + + VCVTPS2DQZ128rmk = 6986 + + VCVTPS2DQZ128rmkz = 6987 + + VCVTPS2DQZ128rr = 6988 + + VCVTPS2DQZ128rrk = 6989 + + VCVTPS2DQZ128rrkz = 6990 + + VCVTPS2DQZ256rm = 6991 + + VCVTPS2DQZ256rmb = 6992 + + VCVTPS2DQZ256rmbk = 6993 + + VCVTPS2DQZ256rmbkz = 6994 + + VCVTPS2DQZ256rmk = 6995 + + VCVTPS2DQZ256rmkz = 6996 + + VCVTPS2DQZ256rr = 6997 + + VCVTPS2DQZ256rrk = 6998 + + VCVTPS2DQZ256rrkz = 6999 + + VCVTPS2DQZrm = 7000 + + VCVTPS2DQZrmb = 7001 + + VCVTPS2DQZrmbk = 7002 + + VCVTPS2DQZrmbkz = 7003 + + VCVTPS2DQZrmk = 7004 + + VCVTPS2DQZrmkz = 7005 + + VCVTPS2DQZrr = 7006 + + VCVTPS2DQZrrb = 7007 + + VCVTPS2DQZrrbk = 7008 + + VCVTPS2DQZrrbkz = 7009 + + VCVTPS2DQZrrk = 7010 + + VCVTPS2DQZrrkz = 7011 + + VCVTPS2DQrm = 7012 + + VCVTPS2DQrr = 7013 + + VCVTPS2IBSZ128rm = 7014 + + VCVTPS2IBSZ128rmb = 7015 + + VCVTPS2IBSZ128rmbk = 7016 + + VCVTPS2IBSZ128rmbkz = 7017 + + VCVTPS2IBSZ128rmk = 7018 + + VCVTPS2IBSZ128rmkz = 7019 + + VCVTPS2IBSZ128rr = 7020 + + VCVTPS2IBSZ128rrk = 7021 + + VCVTPS2IBSZ128rrkz = 7022 + + VCVTPS2IBSZ256rm = 7023 + + VCVTPS2IBSZ256rmb = 7024 + + VCVTPS2IBSZ256rmbk = 7025 + + VCVTPS2IBSZ256rmbkz = 7026 + + VCVTPS2IBSZ256rmk = 7027 + + VCVTPS2IBSZ256rmkz = 7028 + + VCVTPS2IBSZ256rr = 7029 + + VCVTPS2IBSZ256rrk = 7030 + + VCVTPS2IBSZ256rrkz = 7031 + + VCVTPS2IBSZrm = 7032 + + VCVTPS2IBSZrmb = 7033 + + VCVTPS2IBSZrmbk = 7034 + + VCVTPS2IBSZrmbkz = 7035 + + VCVTPS2IBSZrmk = 7036 + + VCVTPS2IBSZrmkz = 7037 + + VCVTPS2IBSZrr = 7038 + + VCVTPS2IBSZrrb = 7039 + + VCVTPS2IBSZrrbk = 7040 + + VCVTPS2IBSZrrbkz = 7041 + + VCVTPS2IBSZrrk = 7042 + + VCVTPS2IBSZrrkz = 7043 + + VCVTPS2IUBSZ128rm = 7044 + + VCVTPS2IUBSZ128rmb = 7045 + + VCVTPS2IUBSZ128rmbk = 7046 + + VCVTPS2IUBSZ128rmbkz = 7047 + + VCVTPS2IUBSZ128rmk = 7048 + + VCVTPS2IUBSZ128rmkz = 7049 + + VCVTPS2IUBSZ128rr = 7050 + + VCVTPS2IUBSZ128rrk = 7051 + + VCVTPS2IUBSZ128rrkz = 7052 + + VCVTPS2IUBSZ256rm = 7053 + + VCVTPS2IUBSZ256rmb = 7054 + + VCVTPS2IUBSZ256rmbk = 7055 + + VCVTPS2IUBSZ256rmbkz = 7056 + + VCVTPS2IUBSZ256rmk = 7057 + + VCVTPS2IUBSZ256rmkz = 7058 + + VCVTPS2IUBSZ256rr = 7059 + + VCVTPS2IUBSZ256rrk = 7060 + + VCVTPS2IUBSZ256rrkz = 7061 + + VCVTPS2IUBSZrm = 7062 + + VCVTPS2IUBSZrmb = 7063 + + VCVTPS2IUBSZrmbk = 7064 + + VCVTPS2IUBSZrmbkz = 7065 + + VCVTPS2IUBSZrmk = 7066 + + VCVTPS2IUBSZrmkz = 7067 + + VCVTPS2IUBSZrr = 7068 + + VCVTPS2IUBSZrrb = 7069 + + VCVTPS2IUBSZrrbk = 7070 + + VCVTPS2IUBSZrrbkz = 7071 + + VCVTPS2IUBSZrrk = 7072 + + VCVTPS2IUBSZrrkz = 7073 + + VCVTPS2PDYrm = 7074 + + VCVTPS2PDYrr = 7075 + + VCVTPS2PDZ128rm = 7076 + + VCVTPS2PDZ128rmb = 7077 + + VCVTPS2PDZ128rmbk = 7078 + + VCVTPS2PDZ128rmbkz = 7079 + + VCVTPS2PDZ128rmk = 7080 + + VCVTPS2PDZ128rmkz = 7081 + + VCVTPS2PDZ128rr = 7082 + + VCVTPS2PDZ128rrk = 7083 + + VCVTPS2PDZ128rrkz = 7084 + + VCVTPS2PDZ256rm = 7085 + + VCVTPS2PDZ256rmb = 7086 + + VCVTPS2PDZ256rmbk = 7087 + + VCVTPS2PDZ256rmbkz = 7088 + + VCVTPS2PDZ256rmk = 7089 + + VCVTPS2PDZ256rmkz = 7090 + + VCVTPS2PDZ256rr = 7091 + + VCVTPS2PDZ256rrk = 7092 + + VCVTPS2PDZ256rrkz = 7093 + + VCVTPS2PDZrm = 7094 + + VCVTPS2PDZrmb = 7095 + + VCVTPS2PDZrmbk = 7096 + + VCVTPS2PDZrmbkz = 7097 + + VCVTPS2PDZrmk = 7098 + + VCVTPS2PDZrmkz = 7099 + + VCVTPS2PDZrr = 7100 + + VCVTPS2PDZrrb = 7101 + + VCVTPS2PDZrrbk = 7102 + + VCVTPS2PDZrrbkz = 7103 + + VCVTPS2PDZrrk = 7104 + + VCVTPS2PDZrrkz = 7105 + + VCVTPS2PDrm = 7106 + + VCVTPS2PDrr = 7107 + + VCVTPS2PHXZ128rm = 7108 + + VCVTPS2PHXZ128rmb = 7109 + + VCVTPS2PHXZ128rmbk = 7110 + + VCVTPS2PHXZ128rmbkz = 7111 + + VCVTPS2PHXZ128rmk = 7112 + + VCVTPS2PHXZ128rmkz = 7113 + + VCVTPS2PHXZ128rr = 7114 + + VCVTPS2PHXZ128rrk = 7115 + + VCVTPS2PHXZ128rrkz = 7116 + + VCVTPS2PHXZ256rm = 7117 + + VCVTPS2PHXZ256rmb = 7118 + + VCVTPS2PHXZ256rmbk = 7119 + + VCVTPS2PHXZ256rmbkz = 7120 + + VCVTPS2PHXZ256rmk = 7121 + + VCVTPS2PHXZ256rmkz = 7122 + + VCVTPS2PHXZ256rr = 7123 + + VCVTPS2PHXZ256rrk = 7124 + + VCVTPS2PHXZ256rrkz = 7125 + + VCVTPS2PHXZrm = 7126 + + VCVTPS2PHXZrmb = 7127 + + VCVTPS2PHXZrmbk = 7128 + + VCVTPS2PHXZrmbkz = 7129 + + VCVTPS2PHXZrmk = 7130 + + VCVTPS2PHXZrmkz = 7131 + + VCVTPS2PHXZrr = 7132 + + VCVTPS2PHXZrrb = 7133 + + VCVTPS2PHXZrrbk = 7134 + + VCVTPS2PHXZrrbkz = 7135 + + VCVTPS2PHXZrrk = 7136 + + VCVTPS2PHXZrrkz = 7137 + + VCVTPS2PHYmr = 7138 + + VCVTPS2PHYrr = 7139 + + VCVTPS2PHZ128mr = 7140 + + VCVTPS2PHZ128mrk = 7141 + + VCVTPS2PHZ128rr = 7142 + + VCVTPS2PHZ128rrk = 7143 + + VCVTPS2PHZ128rrkz = 7144 + + VCVTPS2PHZ256mr = 7145 + + VCVTPS2PHZ256mrk = 7146 + + VCVTPS2PHZ256rr = 7147 + + VCVTPS2PHZ256rrk = 7148 + + VCVTPS2PHZ256rrkz = 7149 + + VCVTPS2PHZmr = 7150 + + VCVTPS2PHZmrk = 7151 + + VCVTPS2PHZrr = 7152 + + VCVTPS2PHZrrb = 7153 + + VCVTPS2PHZrrbk = 7154 + + VCVTPS2PHZrrbkz = 7155 + + VCVTPS2PHZrrk = 7156 + + VCVTPS2PHZrrkz = 7157 + + VCVTPS2PHmr = 7158 + + VCVTPS2PHrr = 7159 + + VCVTPS2QQZ128rm = 7160 + + VCVTPS2QQZ128rmb = 7161 + + VCVTPS2QQZ128rmbk = 7162 + + VCVTPS2QQZ128rmbkz = 7163 + + VCVTPS2QQZ128rmk = 7164 + + VCVTPS2QQZ128rmkz = 7165 + + VCVTPS2QQZ128rr = 7166 + + VCVTPS2QQZ128rrk = 7167 + + VCVTPS2QQZ128rrkz = 7168 + + VCVTPS2QQZ256rm = 7169 + + VCVTPS2QQZ256rmb = 7170 + + VCVTPS2QQZ256rmbk = 7171 + + VCVTPS2QQZ256rmbkz = 7172 + + VCVTPS2QQZ256rmk = 7173 + + VCVTPS2QQZ256rmkz = 7174 + + VCVTPS2QQZ256rr = 7175 + + VCVTPS2QQZ256rrk = 7176 + + VCVTPS2QQZ256rrkz = 7177 + + VCVTPS2QQZrm = 7178 + + VCVTPS2QQZrmb = 7179 + + VCVTPS2QQZrmbk = 7180 + + VCVTPS2QQZrmbkz = 7181 + + VCVTPS2QQZrmk = 7182 + + VCVTPS2QQZrmkz = 7183 + + VCVTPS2QQZrr = 7184 + + VCVTPS2QQZrrb = 7185 + + VCVTPS2QQZrrbk = 7186 + + VCVTPS2QQZrrbkz = 7187 + + VCVTPS2QQZrrk = 7188 + + VCVTPS2QQZrrkz = 7189 + + VCVTPS2UDQZ128rm = 7190 + + VCVTPS2UDQZ128rmb = 7191 + + VCVTPS2UDQZ128rmbk = 7192 + + VCVTPS2UDQZ128rmbkz = 7193 + + VCVTPS2UDQZ128rmk = 7194 + + VCVTPS2UDQZ128rmkz = 7195 + + VCVTPS2UDQZ128rr = 7196 + + VCVTPS2UDQZ128rrk = 7197 + + VCVTPS2UDQZ128rrkz = 7198 + + VCVTPS2UDQZ256rm = 7199 + + VCVTPS2UDQZ256rmb = 7200 + + VCVTPS2UDQZ256rmbk = 7201 + + VCVTPS2UDQZ256rmbkz = 7202 + + VCVTPS2UDQZ256rmk = 7203 + + VCVTPS2UDQZ256rmkz = 7204 + + VCVTPS2UDQZ256rr = 7205 + + VCVTPS2UDQZ256rrk = 7206 + + VCVTPS2UDQZ256rrkz = 7207 + + VCVTPS2UDQZrm = 7208 + + VCVTPS2UDQZrmb = 7209 + + VCVTPS2UDQZrmbk = 7210 + + VCVTPS2UDQZrmbkz = 7211 + + VCVTPS2UDQZrmk = 7212 + + VCVTPS2UDQZrmkz = 7213 + + VCVTPS2UDQZrr = 7214 + + VCVTPS2UDQZrrb = 7215 + + VCVTPS2UDQZrrbk = 7216 + + VCVTPS2UDQZrrbkz = 7217 + + VCVTPS2UDQZrrk = 7218 + + VCVTPS2UDQZrrkz = 7219 + + VCVTPS2UQQZ128rm = 7220 + + VCVTPS2UQQZ128rmb = 7221 + + VCVTPS2UQQZ128rmbk = 7222 + + VCVTPS2UQQZ128rmbkz = 7223 + + VCVTPS2UQQZ128rmk = 7224 + + VCVTPS2UQQZ128rmkz = 7225 + + VCVTPS2UQQZ128rr = 7226 + + VCVTPS2UQQZ128rrk = 7227 + + VCVTPS2UQQZ128rrkz = 7228 + + VCVTPS2UQQZ256rm = 7229 + + VCVTPS2UQQZ256rmb = 7230 + + VCVTPS2UQQZ256rmbk = 7231 + + VCVTPS2UQQZ256rmbkz = 7232 + + VCVTPS2UQQZ256rmk = 7233 + + VCVTPS2UQQZ256rmkz = 7234 + + VCVTPS2UQQZ256rr = 7235 + + VCVTPS2UQQZ256rrk = 7236 + + VCVTPS2UQQZ256rrkz = 7237 + + VCVTPS2UQQZrm = 7238 + + VCVTPS2UQQZrmb = 7239 + + VCVTPS2UQQZrmbk = 7240 + + VCVTPS2UQQZrmbkz = 7241 + + VCVTPS2UQQZrmk = 7242 + + VCVTPS2UQQZrmkz = 7243 + + VCVTPS2UQQZrr = 7244 + + VCVTPS2UQQZrrb = 7245 + + VCVTPS2UQQZrrbk = 7246 + + VCVTPS2UQQZrrbkz = 7247 + + VCVTPS2UQQZrrk = 7248 + + VCVTPS2UQQZrrkz = 7249 + + VCVTQQ2PDZ128rm = 7250 + + VCVTQQ2PDZ128rmb = 7251 + + VCVTQQ2PDZ128rmbk = 7252 + + VCVTQQ2PDZ128rmbkz = 7253 + + VCVTQQ2PDZ128rmk = 7254 + + VCVTQQ2PDZ128rmkz = 7255 + + VCVTQQ2PDZ128rr = 7256 + + VCVTQQ2PDZ128rrk = 7257 + + VCVTQQ2PDZ128rrkz = 7258 + + VCVTQQ2PDZ256rm = 7259 + + VCVTQQ2PDZ256rmb = 7260 + + VCVTQQ2PDZ256rmbk = 7261 + + VCVTQQ2PDZ256rmbkz = 7262 + + VCVTQQ2PDZ256rmk = 7263 + + VCVTQQ2PDZ256rmkz = 7264 + + VCVTQQ2PDZ256rr = 7265 + + VCVTQQ2PDZ256rrk = 7266 + + VCVTQQ2PDZ256rrkz = 7267 + + VCVTQQ2PDZrm = 7268 + + VCVTQQ2PDZrmb = 7269 + + VCVTQQ2PDZrmbk = 7270 + + VCVTQQ2PDZrmbkz = 7271 + + VCVTQQ2PDZrmk = 7272 + + VCVTQQ2PDZrmkz = 7273 + + VCVTQQ2PDZrr = 7274 + + VCVTQQ2PDZrrb = 7275 + + VCVTQQ2PDZrrbk = 7276 + + VCVTQQ2PDZrrbkz = 7277 + + VCVTQQ2PDZrrk = 7278 + + VCVTQQ2PDZrrkz = 7279 + + VCVTQQ2PHZ128rm = 7280 + + VCVTQQ2PHZ128rmb = 7281 + + VCVTQQ2PHZ128rmbk = 7282 + + VCVTQQ2PHZ128rmbkz = 7283 + + VCVTQQ2PHZ128rmk = 7284 + + VCVTQQ2PHZ128rmkz = 7285 + + VCVTQQ2PHZ128rr = 7286 + + VCVTQQ2PHZ128rrk = 7287 + + VCVTQQ2PHZ128rrkz = 7288 + + VCVTQQ2PHZ256rm = 7289 + + VCVTQQ2PHZ256rmb = 7290 + + VCVTQQ2PHZ256rmbk = 7291 + + VCVTQQ2PHZ256rmbkz = 7292 + + VCVTQQ2PHZ256rmk = 7293 + + VCVTQQ2PHZ256rmkz = 7294 + + VCVTQQ2PHZ256rr = 7295 + + VCVTQQ2PHZ256rrk = 7296 + + VCVTQQ2PHZ256rrkz = 7297 + + VCVTQQ2PHZrm = 7298 + + VCVTQQ2PHZrmb = 7299 + + VCVTQQ2PHZrmbk = 7300 + + VCVTQQ2PHZrmbkz = 7301 + + VCVTQQ2PHZrmk = 7302 + + VCVTQQ2PHZrmkz = 7303 + + VCVTQQ2PHZrr = 7304 + + VCVTQQ2PHZrrb = 7305 + + VCVTQQ2PHZrrbk = 7306 + + VCVTQQ2PHZrrbkz = 7307 + + VCVTQQ2PHZrrk = 7308 + + VCVTQQ2PHZrrkz = 7309 + + VCVTQQ2PSZ128rm = 7310 + + VCVTQQ2PSZ128rmb = 7311 + + VCVTQQ2PSZ128rmbk = 7312 + + VCVTQQ2PSZ128rmbkz = 7313 + + VCVTQQ2PSZ128rmk = 7314 + + VCVTQQ2PSZ128rmkz = 7315 + + VCVTQQ2PSZ128rr = 7316 + + VCVTQQ2PSZ128rrk = 7317 + + VCVTQQ2PSZ128rrkz = 7318 + + VCVTQQ2PSZ256rm = 7319 + + VCVTQQ2PSZ256rmb = 7320 + + VCVTQQ2PSZ256rmbk = 7321 + + VCVTQQ2PSZ256rmbkz = 7322 + + VCVTQQ2PSZ256rmk = 7323 + + VCVTQQ2PSZ256rmkz = 7324 + + VCVTQQ2PSZ256rr = 7325 + + VCVTQQ2PSZ256rrk = 7326 + + VCVTQQ2PSZ256rrkz = 7327 + + VCVTQQ2PSZrm = 7328 + + VCVTQQ2PSZrmb = 7329 + + VCVTQQ2PSZrmbk = 7330 + + VCVTQQ2PSZrmbkz = 7331 + + VCVTQQ2PSZrmk = 7332 + + VCVTQQ2PSZrmkz = 7333 + + VCVTQQ2PSZrr = 7334 + + VCVTQQ2PSZrrb = 7335 + + VCVTQQ2PSZrrbk = 7336 + + VCVTQQ2PSZrrbkz = 7337 + + VCVTQQ2PSZrrk = 7338 + + VCVTQQ2PSZrrkz = 7339 + + VCVTSD2SHZrm = 7340 + + VCVTSD2SHZrm_Int = 7341 + + VCVTSD2SHZrmk_Int = 7342 + + VCVTSD2SHZrmkz_Int = 7343 + + VCVTSD2SHZrr = 7344 + + VCVTSD2SHZrr_Int = 7345 + + VCVTSD2SHZrrb_Int = 7346 + + VCVTSD2SHZrrbk_Int = 7347 + + VCVTSD2SHZrrbkz_Int = 7348 + + VCVTSD2SHZrrk_Int = 7349 + + VCVTSD2SHZrrkz_Int = 7350 + + VCVTSD2SI64Zrm = 7351 + + VCVTSD2SI64Zrm_Int = 7352 + + VCVTSD2SI64Zrr = 7353 + + VCVTSD2SI64Zrr_Int = 7354 + + VCVTSD2SI64Zrrb_Int = 7355 + + VCVTSD2SI64rm = 7356 + + VCVTSD2SI64rm_Int = 7357 + + VCVTSD2SI64rr = 7358 + + VCVTSD2SI64rr_Int = 7359 + + VCVTSD2SIZrm = 7360 + + VCVTSD2SIZrm_Int = 7361 + + VCVTSD2SIZrr = 7362 + + VCVTSD2SIZrr_Int = 7363 + + VCVTSD2SIZrrb_Int = 7364 + + VCVTSD2SIrm = 7365 + + VCVTSD2SIrm_Int = 7366 + + VCVTSD2SIrr = 7367 + + VCVTSD2SIrr_Int = 7368 + + VCVTSD2SSZrm = 7369 + + VCVTSD2SSZrm_Int = 7370 + + VCVTSD2SSZrmk_Int = 7371 + + VCVTSD2SSZrmkz_Int = 7372 + + VCVTSD2SSZrr = 7373 + + VCVTSD2SSZrr_Int = 7374 + + VCVTSD2SSZrrb_Int = 7375 + + VCVTSD2SSZrrbk_Int = 7376 + + VCVTSD2SSZrrbkz_Int = 7377 + + VCVTSD2SSZrrk_Int = 7378 + + VCVTSD2SSZrrkz_Int = 7379 + + VCVTSD2SSrm = 7380 + + VCVTSD2SSrm_Int = 7381 + + VCVTSD2SSrr = 7382 + + VCVTSD2SSrr_Int = 7383 + + VCVTSD2USI64Zrm_Int = 7384 + + VCVTSD2USI64Zrr_Int = 7385 + + VCVTSD2USI64Zrrb_Int = 7386 + + VCVTSD2USIZrm_Int = 7387 + + VCVTSD2USIZrr_Int = 7388 + + VCVTSD2USIZrrb_Int = 7389 + + VCVTSH2SDZrm = 7390 + + VCVTSH2SDZrm_Int = 7391 + + VCVTSH2SDZrmk_Int = 7392 + + VCVTSH2SDZrmkz_Int = 7393 + + VCVTSH2SDZrr = 7394 + + VCVTSH2SDZrr_Int = 7395 + + VCVTSH2SDZrrb_Int = 7396 + + VCVTSH2SDZrrbk_Int = 7397 + + VCVTSH2SDZrrbkz_Int = 7398 + + VCVTSH2SDZrrk_Int = 7399 + + VCVTSH2SDZrrkz_Int = 7400 + + VCVTSH2SI64Zrm_Int = 7401 + + VCVTSH2SI64Zrr_Int = 7402 + + VCVTSH2SI64Zrrb_Int = 7403 + + VCVTSH2SIZrm_Int = 7404 + + VCVTSH2SIZrr_Int = 7405 + + VCVTSH2SIZrrb_Int = 7406 + + VCVTSH2SSZrm = 7407 + + VCVTSH2SSZrm_Int = 7408 + + VCVTSH2SSZrmk_Int = 7409 + + VCVTSH2SSZrmkz_Int = 7410 + + VCVTSH2SSZrr = 7411 + + VCVTSH2SSZrr_Int = 7412 + + VCVTSH2SSZrrb_Int = 7413 + + VCVTSH2SSZrrbk_Int = 7414 + + VCVTSH2SSZrrbkz_Int = 7415 + + VCVTSH2SSZrrk_Int = 7416 + + VCVTSH2SSZrrkz_Int = 7417 + + VCVTSH2USI64Zrm_Int = 7418 + + VCVTSH2USI64Zrr_Int = 7419 + + VCVTSH2USI64Zrrb_Int = 7420 + + VCVTSH2USIZrm_Int = 7421 + + VCVTSH2USIZrr_Int = 7422 + + VCVTSH2USIZrrb_Int = 7423 + + VCVTSI2SDZrm = 7424 + + VCVTSI2SDZrm_Int = 7425 + + VCVTSI2SDZrr = 7426 + + VCVTSI2SDZrr_Int = 7427 + + VCVTSI2SDrm = 7428 + + VCVTSI2SDrm_Int = 7429 + + VCVTSI2SDrr = 7430 + + VCVTSI2SDrr_Int = 7431 + + VCVTSI2SHZrm = 7432 + + VCVTSI2SHZrm_Int = 7433 + + VCVTSI2SHZrr = 7434 + + VCVTSI2SHZrr_Int = 7435 + + VCVTSI2SHZrrb_Int = 7436 + + VCVTSI2SSZrm = 7437 + + VCVTSI2SSZrm_Int = 7438 + + VCVTSI2SSZrr = 7439 + + VCVTSI2SSZrr_Int = 7440 + + VCVTSI2SSZrrb_Int = 7441 + + VCVTSI2SSrm = 7442 + + VCVTSI2SSrm_Int = 7443 + + VCVTSI2SSrr = 7444 + + VCVTSI2SSrr_Int = 7445 + + VCVTSI642SDZrm = 7446 + + VCVTSI642SDZrm_Int = 7447 + + VCVTSI642SDZrr = 7448 + + VCVTSI642SDZrr_Int = 7449 + + VCVTSI642SDZrrb_Int = 7450 + + VCVTSI642SDrm = 7451 + + VCVTSI642SDrm_Int = 7452 + + VCVTSI642SDrr = 7453 + + VCVTSI642SDrr_Int = 7454 + + VCVTSI642SHZrm = 7455 + + VCVTSI642SHZrm_Int = 7456 + + VCVTSI642SHZrr = 7457 + + VCVTSI642SHZrr_Int = 7458 + + VCVTSI642SHZrrb_Int = 7459 + + VCVTSI642SSZrm = 7460 + + VCVTSI642SSZrm_Int = 7461 + + VCVTSI642SSZrr = 7462 + + VCVTSI642SSZrr_Int = 7463 + + VCVTSI642SSZrrb_Int = 7464 + + VCVTSI642SSrm = 7465 + + VCVTSI642SSrm_Int = 7466 + + VCVTSI642SSrr = 7467 + + VCVTSI642SSrr_Int = 7468 + + VCVTSS2SDZrm = 7469 + + VCVTSS2SDZrm_Int = 7470 + + VCVTSS2SDZrmk_Int = 7471 + + VCVTSS2SDZrmkz_Int = 7472 + + VCVTSS2SDZrr = 7473 + + VCVTSS2SDZrr_Int = 7474 + + VCVTSS2SDZrrb_Int = 7475 + + VCVTSS2SDZrrbk_Int = 7476 + + VCVTSS2SDZrrbkz_Int = 7477 + + VCVTSS2SDZrrk_Int = 7478 + + VCVTSS2SDZrrkz_Int = 7479 + + VCVTSS2SDrm = 7480 + + VCVTSS2SDrm_Int = 7481 + + VCVTSS2SDrr = 7482 + + VCVTSS2SDrr_Int = 7483 + + VCVTSS2SHZrm = 7484 + + VCVTSS2SHZrm_Int = 7485 + + VCVTSS2SHZrmk_Int = 7486 + + VCVTSS2SHZrmkz_Int = 7487 + + VCVTSS2SHZrr = 7488 + + VCVTSS2SHZrr_Int = 7489 + + VCVTSS2SHZrrb_Int = 7490 + + VCVTSS2SHZrrbk_Int = 7491 + + VCVTSS2SHZrrbkz_Int = 7492 + + VCVTSS2SHZrrk_Int = 7493 + + VCVTSS2SHZrrkz_Int = 7494 + + VCVTSS2SI64Zrm = 7495 + + VCVTSS2SI64Zrm_Int = 7496 + + VCVTSS2SI64Zrr = 7497 + + VCVTSS2SI64Zrr_Int = 7498 + + VCVTSS2SI64Zrrb_Int = 7499 + + VCVTSS2SI64rm = 7500 + + VCVTSS2SI64rm_Int = 7501 + + VCVTSS2SI64rr = 7502 + + VCVTSS2SI64rr_Int = 7503 + + VCVTSS2SIZrm = 7504 + + VCVTSS2SIZrm_Int = 7505 + + VCVTSS2SIZrr = 7506 + + VCVTSS2SIZrr_Int = 7507 + + VCVTSS2SIZrrb_Int = 7508 + + VCVTSS2SIrm = 7509 + + VCVTSS2SIrm_Int = 7510 + + VCVTSS2SIrr = 7511 + + VCVTSS2SIrr_Int = 7512 + + VCVTSS2USI64Zrm_Int = 7513 + + VCVTSS2USI64Zrr_Int = 7514 + + VCVTSS2USI64Zrrb_Int = 7515 + + VCVTSS2USIZrm_Int = 7516 + + VCVTSS2USIZrr_Int = 7517 + + VCVTSS2USIZrrb_Int = 7518 + + VCVTTBF162IBSZ128rm = 7519 + + VCVTTBF162IBSZ128rmb = 7520 + + VCVTTBF162IBSZ128rmbk = 7521 + + VCVTTBF162IBSZ128rmbkz = 7522 + + VCVTTBF162IBSZ128rmk = 7523 + + VCVTTBF162IBSZ128rmkz = 7524 + + VCVTTBF162IBSZ128rr = 7525 + + VCVTTBF162IBSZ128rrk = 7526 + + VCVTTBF162IBSZ128rrkz = 7527 + + VCVTTBF162IBSZ256rm = 7528 + + VCVTTBF162IBSZ256rmb = 7529 + + VCVTTBF162IBSZ256rmbk = 7530 + + VCVTTBF162IBSZ256rmbkz = 7531 + + VCVTTBF162IBSZ256rmk = 7532 + + VCVTTBF162IBSZ256rmkz = 7533 + + VCVTTBF162IBSZ256rr = 7534 + + VCVTTBF162IBSZ256rrk = 7535 + + VCVTTBF162IBSZ256rrkz = 7536 + + VCVTTBF162IBSZrm = 7537 + + VCVTTBF162IBSZrmb = 7538 + + VCVTTBF162IBSZrmbk = 7539 + + VCVTTBF162IBSZrmbkz = 7540 + + VCVTTBF162IBSZrmk = 7541 + + VCVTTBF162IBSZrmkz = 7542 + + VCVTTBF162IBSZrr = 7543 + + VCVTTBF162IBSZrrk = 7544 + + VCVTTBF162IBSZrrkz = 7545 + + VCVTTBF162IUBSZ128rm = 7546 + + VCVTTBF162IUBSZ128rmb = 7547 + + VCVTTBF162IUBSZ128rmbk = 7548 + + VCVTTBF162IUBSZ128rmbkz = 7549 + + VCVTTBF162IUBSZ128rmk = 7550 + + VCVTTBF162IUBSZ128rmkz = 7551 + + VCVTTBF162IUBSZ128rr = 7552 + + VCVTTBF162IUBSZ128rrk = 7553 + + VCVTTBF162IUBSZ128rrkz = 7554 + + VCVTTBF162IUBSZ256rm = 7555 + + VCVTTBF162IUBSZ256rmb = 7556 + + VCVTTBF162IUBSZ256rmbk = 7557 + + VCVTTBF162IUBSZ256rmbkz = 7558 + + VCVTTBF162IUBSZ256rmk = 7559 + + VCVTTBF162IUBSZ256rmkz = 7560 + + VCVTTBF162IUBSZ256rr = 7561 + + VCVTTBF162IUBSZ256rrk = 7562 + + VCVTTBF162IUBSZ256rrkz = 7563 + + VCVTTBF162IUBSZrm = 7564 + + VCVTTBF162IUBSZrmb = 7565 + + VCVTTBF162IUBSZrmbk = 7566 + + VCVTTBF162IUBSZrmbkz = 7567 + + VCVTTBF162IUBSZrmk = 7568 + + VCVTTBF162IUBSZrmkz = 7569 + + VCVTTBF162IUBSZrr = 7570 + + VCVTTBF162IUBSZrrk = 7571 + + VCVTTBF162IUBSZrrkz = 7572 + + VCVTTPD2DQSZ128rm = 7573 + + VCVTTPD2DQSZ128rmb = 7574 + + VCVTTPD2DQSZ128rmbk = 7575 + + VCVTTPD2DQSZ128rmbkz = 7576 + + VCVTTPD2DQSZ128rmk = 7577 + + VCVTTPD2DQSZ128rmkz = 7578 + + VCVTTPD2DQSZ128rr = 7579 + + VCVTTPD2DQSZ128rrk = 7580 + + VCVTTPD2DQSZ128rrkz = 7581 + + VCVTTPD2DQSZ256rm = 7582 + + VCVTTPD2DQSZ256rmb = 7583 + + VCVTTPD2DQSZ256rmbk = 7584 + + VCVTTPD2DQSZ256rmbkz = 7585 + + VCVTTPD2DQSZ256rmk = 7586 + + VCVTTPD2DQSZ256rmkz = 7587 + + VCVTTPD2DQSZ256rr = 7588 + + VCVTTPD2DQSZ256rrb = 7589 + + VCVTTPD2DQSZ256rrbk = 7590 + + VCVTTPD2DQSZ256rrbkz = 7591 + + VCVTTPD2DQSZ256rrk = 7592 + + VCVTTPD2DQSZ256rrkz = 7593 + + VCVTTPD2DQSZrm = 7594 + + VCVTTPD2DQSZrmb = 7595 + + VCVTTPD2DQSZrmbk = 7596 + + VCVTTPD2DQSZrmbkz = 7597 + + VCVTTPD2DQSZrmk = 7598 + + VCVTTPD2DQSZrmkz = 7599 + + VCVTTPD2DQSZrr = 7600 + + VCVTTPD2DQSZrrb = 7601 + + VCVTTPD2DQSZrrbk = 7602 + + VCVTTPD2DQSZrrbkz = 7603 + + VCVTTPD2DQSZrrk = 7604 + + VCVTTPD2DQSZrrkz = 7605 + + VCVTTPD2DQYrm = 7606 + + VCVTTPD2DQYrr = 7607 + + VCVTTPD2DQZ128rm = 7608 + + VCVTTPD2DQZ128rmb = 7609 + + VCVTTPD2DQZ128rmbk = 7610 + + VCVTTPD2DQZ128rmbkz = 7611 + + VCVTTPD2DQZ128rmk = 7612 + + VCVTTPD2DQZ128rmkz = 7613 + + VCVTTPD2DQZ128rr = 7614 + + VCVTTPD2DQZ128rrk = 7615 + + VCVTTPD2DQZ128rrkz = 7616 + + VCVTTPD2DQZ256rm = 7617 + + VCVTTPD2DQZ256rmb = 7618 + + VCVTTPD2DQZ256rmbk = 7619 + + VCVTTPD2DQZ256rmbkz = 7620 + + VCVTTPD2DQZ256rmk = 7621 + + VCVTTPD2DQZ256rmkz = 7622 + + VCVTTPD2DQZ256rr = 7623 + + VCVTTPD2DQZ256rrk = 7624 + + VCVTTPD2DQZ256rrkz = 7625 + + VCVTTPD2DQZrm = 7626 + + VCVTTPD2DQZrmb = 7627 + + VCVTTPD2DQZrmbk = 7628 + + VCVTTPD2DQZrmbkz = 7629 + + VCVTTPD2DQZrmk = 7630 + + VCVTTPD2DQZrmkz = 7631 + + VCVTTPD2DQZrr = 7632 + + VCVTTPD2DQZrrb = 7633 + + VCVTTPD2DQZrrbk = 7634 + + VCVTTPD2DQZrrbkz = 7635 + + VCVTTPD2DQZrrk = 7636 + + VCVTTPD2DQZrrkz = 7637 + + VCVTTPD2DQrm = 7638 + + VCVTTPD2DQrr = 7639 + + VCVTTPD2QQSZ128rm = 7640 + + VCVTTPD2QQSZ128rmb = 7641 + + VCVTTPD2QQSZ128rmbk = 7642 + + VCVTTPD2QQSZ128rmbkz = 7643 + + VCVTTPD2QQSZ128rmk = 7644 + + VCVTTPD2QQSZ128rmkz = 7645 + + VCVTTPD2QQSZ128rr = 7646 + + VCVTTPD2QQSZ128rrk = 7647 + + VCVTTPD2QQSZ128rrkz = 7648 + + VCVTTPD2QQSZ256rm = 7649 + + VCVTTPD2QQSZ256rmb = 7650 + + VCVTTPD2QQSZ256rmbk = 7651 + + VCVTTPD2QQSZ256rmbkz = 7652 + + VCVTTPD2QQSZ256rmk = 7653 + + VCVTTPD2QQSZ256rmkz = 7654 + + VCVTTPD2QQSZ256rr = 7655 + + VCVTTPD2QQSZ256rrb = 7656 + + VCVTTPD2QQSZ256rrbk = 7657 + + VCVTTPD2QQSZ256rrbkz = 7658 + + VCVTTPD2QQSZ256rrk = 7659 + + VCVTTPD2QQSZ256rrkz = 7660 + + VCVTTPD2QQSZrm = 7661 + + VCVTTPD2QQSZrmb = 7662 + + VCVTTPD2QQSZrmbk = 7663 + + VCVTTPD2QQSZrmbkz = 7664 + + VCVTTPD2QQSZrmk = 7665 + + VCVTTPD2QQSZrmkz = 7666 + + VCVTTPD2QQSZrr = 7667 + + VCVTTPD2QQSZrrb = 7668 + + VCVTTPD2QQSZrrbk = 7669 + + VCVTTPD2QQSZrrbkz = 7670 + + VCVTTPD2QQSZrrk = 7671 + + VCVTTPD2QQSZrrkz = 7672 + + VCVTTPD2QQZ128rm = 7673 + + VCVTTPD2QQZ128rmb = 7674 + + VCVTTPD2QQZ128rmbk = 7675 + + VCVTTPD2QQZ128rmbkz = 7676 + + VCVTTPD2QQZ128rmk = 7677 + + VCVTTPD2QQZ128rmkz = 7678 + + VCVTTPD2QQZ128rr = 7679 + + VCVTTPD2QQZ128rrk = 7680 + + VCVTTPD2QQZ128rrkz = 7681 + + VCVTTPD2QQZ256rm = 7682 + + VCVTTPD2QQZ256rmb = 7683 + + VCVTTPD2QQZ256rmbk = 7684 + + VCVTTPD2QQZ256rmbkz = 7685 + + VCVTTPD2QQZ256rmk = 7686 + + VCVTTPD2QQZ256rmkz = 7687 + + VCVTTPD2QQZ256rr = 7688 + + VCVTTPD2QQZ256rrk = 7689 + + VCVTTPD2QQZ256rrkz = 7690 + + VCVTTPD2QQZrm = 7691 + + VCVTTPD2QQZrmb = 7692 + + VCVTTPD2QQZrmbk = 7693 + + VCVTTPD2QQZrmbkz = 7694 + + VCVTTPD2QQZrmk = 7695 + + VCVTTPD2QQZrmkz = 7696 + + VCVTTPD2QQZrr = 7697 + + VCVTTPD2QQZrrb = 7698 + + VCVTTPD2QQZrrbk = 7699 + + VCVTTPD2QQZrrbkz = 7700 + + VCVTTPD2QQZrrk = 7701 + + VCVTTPD2QQZrrkz = 7702 + + VCVTTPD2UDQSZ128rm = 7703 + + VCVTTPD2UDQSZ128rmb = 7704 + + VCVTTPD2UDQSZ128rmbk = 7705 + + VCVTTPD2UDQSZ128rmbkz = 7706 + + VCVTTPD2UDQSZ128rmk = 7707 + + VCVTTPD2UDQSZ128rmkz = 7708 + + VCVTTPD2UDQSZ128rr = 7709 + + VCVTTPD2UDQSZ128rrk = 7710 + + VCVTTPD2UDQSZ128rrkz = 7711 + + VCVTTPD2UDQSZ256rm = 7712 + + VCVTTPD2UDQSZ256rmb = 7713 + + VCVTTPD2UDQSZ256rmbk = 7714 + + VCVTTPD2UDQSZ256rmbkz = 7715 + + VCVTTPD2UDQSZ256rmk = 7716 + + VCVTTPD2UDQSZ256rmkz = 7717 + + VCVTTPD2UDQSZ256rr = 7718 + + VCVTTPD2UDQSZ256rrb = 7719 + + VCVTTPD2UDQSZ256rrbk = 7720 + + VCVTTPD2UDQSZ256rrbkz = 7721 + + VCVTTPD2UDQSZ256rrk = 7722 + + VCVTTPD2UDQSZ256rrkz = 7723 + + VCVTTPD2UDQSZrm = 7724 + + VCVTTPD2UDQSZrmb = 7725 + + VCVTTPD2UDQSZrmbk = 7726 + + VCVTTPD2UDQSZrmbkz = 7727 + + VCVTTPD2UDQSZrmk = 7728 + + VCVTTPD2UDQSZrmkz = 7729 + + VCVTTPD2UDQSZrr = 7730 + + VCVTTPD2UDQSZrrb = 7731 + + VCVTTPD2UDQSZrrbk = 7732 + + VCVTTPD2UDQSZrrbkz = 7733 + + VCVTTPD2UDQSZrrk = 7734 + + VCVTTPD2UDQSZrrkz = 7735 + + VCVTTPD2UDQZ128rm = 7736 + + VCVTTPD2UDQZ128rmb = 7737 + + VCVTTPD2UDQZ128rmbk = 7738 + + VCVTTPD2UDQZ128rmbkz = 7739 + + VCVTTPD2UDQZ128rmk = 7740 + + VCVTTPD2UDQZ128rmkz = 7741 + + VCVTTPD2UDQZ128rr = 7742 + + VCVTTPD2UDQZ128rrk = 7743 + + VCVTTPD2UDQZ128rrkz = 7744 + + VCVTTPD2UDQZ256rm = 7745 + + VCVTTPD2UDQZ256rmb = 7746 + + VCVTTPD2UDQZ256rmbk = 7747 + + VCVTTPD2UDQZ256rmbkz = 7748 + + VCVTTPD2UDQZ256rmk = 7749 + + VCVTTPD2UDQZ256rmkz = 7750 + + VCVTTPD2UDQZ256rr = 7751 + + VCVTTPD2UDQZ256rrk = 7752 + + VCVTTPD2UDQZ256rrkz = 7753 + + VCVTTPD2UDQZrm = 7754 + + VCVTTPD2UDQZrmb = 7755 + + VCVTTPD2UDQZrmbk = 7756 + + VCVTTPD2UDQZrmbkz = 7757 + + VCVTTPD2UDQZrmk = 7758 + + VCVTTPD2UDQZrmkz = 7759 + + VCVTTPD2UDQZrr = 7760 + + VCVTTPD2UDQZrrb = 7761 + + VCVTTPD2UDQZrrbk = 7762 + + VCVTTPD2UDQZrrbkz = 7763 + + VCVTTPD2UDQZrrk = 7764 + + VCVTTPD2UDQZrrkz = 7765 + + VCVTTPD2UQQSZ128rm = 7766 + + VCVTTPD2UQQSZ128rmb = 7767 + + VCVTTPD2UQQSZ128rmbk = 7768 + + VCVTTPD2UQQSZ128rmbkz = 7769 + + VCVTTPD2UQQSZ128rmk = 7770 + + VCVTTPD2UQQSZ128rmkz = 7771 + + VCVTTPD2UQQSZ128rr = 7772 + + VCVTTPD2UQQSZ128rrk = 7773 + + VCVTTPD2UQQSZ128rrkz = 7774 + + VCVTTPD2UQQSZ256rm = 7775 + + VCVTTPD2UQQSZ256rmb = 7776 + + VCVTTPD2UQQSZ256rmbk = 7777 + + VCVTTPD2UQQSZ256rmbkz = 7778 + + VCVTTPD2UQQSZ256rmk = 7779 + + VCVTTPD2UQQSZ256rmkz = 7780 + + VCVTTPD2UQQSZ256rr = 7781 + + VCVTTPD2UQQSZ256rrb = 7782 + + VCVTTPD2UQQSZ256rrbk = 7783 + + VCVTTPD2UQQSZ256rrbkz = 7784 + + VCVTTPD2UQQSZ256rrk = 7785 + + VCVTTPD2UQQSZ256rrkz = 7786 + + VCVTTPD2UQQSZrm = 7787 + + VCVTTPD2UQQSZrmb = 7788 + + VCVTTPD2UQQSZrmbk = 7789 + + VCVTTPD2UQQSZrmbkz = 7790 + + VCVTTPD2UQQSZrmk = 7791 + + VCVTTPD2UQQSZrmkz = 7792 + + VCVTTPD2UQQSZrr = 7793 + + VCVTTPD2UQQSZrrb = 7794 + + VCVTTPD2UQQSZrrbk = 7795 + + VCVTTPD2UQQSZrrbkz = 7796 + + VCVTTPD2UQQSZrrk = 7797 + + VCVTTPD2UQQSZrrkz = 7798 + + VCVTTPD2UQQZ128rm = 7799 + + VCVTTPD2UQQZ128rmb = 7800 + + VCVTTPD2UQQZ128rmbk = 7801 + + VCVTTPD2UQQZ128rmbkz = 7802 + + VCVTTPD2UQQZ128rmk = 7803 + + VCVTTPD2UQQZ128rmkz = 7804 + + VCVTTPD2UQQZ128rr = 7805 + + VCVTTPD2UQQZ128rrk = 7806 + + VCVTTPD2UQQZ128rrkz = 7807 + + VCVTTPD2UQQZ256rm = 7808 + + VCVTTPD2UQQZ256rmb = 7809 + + VCVTTPD2UQQZ256rmbk = 7810 + + VCVTTPD2UQQZ256rmbkz = 7811 + + VCVTTPD2UQQZ256rmk = 7812 + + VCVTTPD2UQQZ256rmkz = 7813 + + VCVTTPD2UQQZ256rr = 7814 + + VCVTTPD2UQQZ256rrk = 7815 + + VCVTTPD2UQQZ256rrkz = 7816 + + VCVTTPD2UQQZrm = 7817 + + VCVTTPD2UQQZrmb = 7818 + + VCVTTPD2UQQZrmbk = 7819 + + VCVTTPD2UQQZrmbkz = 7820 + + VCVTTPD2UQQZrmk = 7821 + + VCVTTPD2UQQZrmkz = 7822 + + VCVTTPD2UQQZrr = 7823 + + VCVTTPD2UQQZrrb = 7824 + + VCVTTPD2UQQZrrbk = 7825 + + VCVTTPD2UQQZrrbkz = 7826 + + VCVTTPD2UQQZrrk = 7827 + + VCVTTPD2UQQZrrkz = 7828 + + VCVTTPH2DQZ128rm = 7829 + + VCVTTPH2DQZ128rmb = 7830 + + VCVTTPH2DQZ128rmbk = 7831 + + VCVTTPH2DQZ128rmbkz = 7832 + + VCVTTPH2DQZ128rmk = 7833 + + VCVTTPH2DQZ128rmkz = 7834 + + VCVTTPH2DQZ128rr = 7835 + + VCVTTPH2DQZ128rrk = 7836 + + VCVTTPH2DQZ128rrkz = 7837 + + VCVTTPH2DQZ256rm = 7838 + + VCVTTPH2DQZ256rmb = 7839 + + VCVTTPH2DQZ256rmbk = 7840 + + VCVTTPH2DQZ256rmbkz = 7841 + + VCVTTPH2DQZ256rmk = 7842 + + VCVTTPH2DQZ256rmkz = 7843 + + VCVTTPH2DQZ256rr = 7844 + + VCVTTPH2DQZ256rrk = 7845 + + VCVTTPH2DQZ256rrkz = 7846 + + VCVTTPH2DQZrm = 7847 + + VCVTTPH2DQZrmb = 7848 + + VCVTTPH2DQZrmbk = 7849 + + VCVTTPH2DQZrmbkz = 7850 + + VCVTTPH2DQZrmk = 7851 + + VCVTTPH2DQZrmkz = 7852 + + VCVTTPH2DQZrr = 7853 + + VCVTTPH2DQZrrb = 7854 + + VCVTTPH2DQZrrbk = 7855 + + VCVTTPH2DQZrrbkz = 7856 + + VCVTTPH2DQZrrk = 7857 + + VCVTTPH2DQZrrkz = 7858 + + VCVTTPH2IBSZ128rm = 7859 + + VCVTTPH2IBSZ128rmb = 7860 + + VCVTTPH2IBSZ128rmbk = 7861 + + VCVTTPH2IBSZ128rmbkz = 7862 + + VCVTTPH2IBSZ128rmk = 7863 + + VCVTTPH2IBSZ128rmkz = 7864 + + VCVTTPH2IBSZ128rr = 7865 + + VCVTTPH2IBSZ128rrk = 7866 + + VCVTTPH2IBSZ128rrkz = 7867 + + VCVTTPH2IBSZ256rm = 7868 + + VCVTTPH2IBSZ256rmb = 7869 + + VCVTTPH2IBSZ256rmbk = 7870 + + VCVTTPH2IBSZ256rmbkz = 7871 + + VCVTTPH2IBSZ256rmk = 7872 + + VCVTTPH2IBSZ256rmkz = 7873 + + VCVTTPH2IBSZ256rr = 7874 + + VCVTTPH2IBSZ256rrk = 7875 + + VCVTTPH2IBSZ256rrkz = 7876 + + VCVTTPH2IBSZrm = 7877 + + VCVTTPH2IBSZrmb = 7878 + + VCVTTPH2IBSZrmbk = 7879 + + VCVTTPH2IBSZrmbkz = 7880 + + VCVTTPH2IBSZrmk = 7881 + + VCVTTPH2IBSZrmkz = 7882 + + VCVTTPH2IBSZrr = 7883 + + VCVTTPH2IBSZrrb = 7884 + + VCVTTPH2IBSZrrbk = 7885 + + VCVTTPH2IBSZrrbkz = 7886 + + VCVTTPH2IBSZrrk = 7887 + + VCVTTPH2IBSZrrkz = 7888 + + VCVTTPH2IUBSZ128rm = 7889 + + VCVTTPH2IUBSZ128rmb = 7890 + + VCVTTPH2IUBSZ128rmbk = 7891 + + VCVTTPH2IUBSZ128rmbkz = 7892 + + VCVTTPH2IUBSZ128rmk = 7893 + + VCVTTPH2IUBSZ128rmkz = 7894 + + VCVTTPH2IUBSZ128rr = 7895 + + VCVTTPH2IUBSZ128rrk = 7896 + + VCVTTPH2IUBSZ128rrkz = 7897 + + VCVTTPH2IUBSZ256rm = 7898 + + VCVTTPH2IUBSZ256rmb = 7899 + + VCVTTPH2IUBSZ256rmbk = 7900 + + VCVTTPH2IUBSZ256rmbkz = 7901 + + VCVTTPH2IUBSZ256rmk = 7902 + + VCVTTPH2IUBSZ256rmkz = 7903 + + VCVTTPH2IUBSZ256rr = 7904 + + VCVTTPH2IUBSZ256rrk = 7905 + + VCVTTPH2IUBSZ256rrkz = 7906 + + VCVTTPH2IUBSZrm = 7907 + + VCVTTPH2IUBSZrmb = 7908 + + VCVTTPH2IUBSZrmbk = 7909 + + VCVTTPH2IUBSZrmbkz = 7910 + + VCVTTPH2IUBSZrmk = 7911 + + VCVTTPH2IUBSZrmkz = 7912 + + VCVTTPH2IUBSZrr = 7913 + + VCVTTPH2IUBSZrrb = 7914 + + VCVTTPH2IUBSZrrbk = 7915 + + VCVTTPH2IUBSZrrbkz = 7916 + + VCVTTPH2IUBSZrrk = 7917 + + VCVTTPH2IUBSZrrkz = 7918 + + VCVTTPH2QQZ128rm = 7919 + + VCVTTPH2QQZ128rmb = 7920 + + VCVTTPH2QQZ128rmbk = 7921 + + VCVTTPH2QQZ128rmbkz = 7922 + + VCVTTPH2QQZ128rmk = 7923 + + VCVTTPH2QQZ128rmkz = 7924 + + VCVTTPH2QQZ128rr = 7925 + + VCVTTPH2QQZ128rrk = 7926 + + VCVTTPH2QQZ128rrkz = 7927 + + VCVTTPH2QQZ256rm = 7928 + + VCVTTPH2QQZ256rmb = 7929 + + VCVTTPH2QQZ256rmbk = 7930 + + VCVTTPH2QQZ256rmbkz = 7931 + + VCVTTPH2QQZ256rmk = 7932 + + VCVTTPH2QQZ256rmkz = 7933 + + VCVTTPH2QQZ256rr = 7934 + + VCVTTPH2QQZ256rrk = 7935 + + VCVTTPH2QQZ256rrkz = 7936 + + VCVTTPH2QQZrm = 7937 + + VCVTTPH2QQZrmb = 7938 + + VCVTTPH2QQZrmbk = 7939 + + VCVTTPH2QQZrmbkz = 7940 + + VCVTTPH2QQZrmk = 7941 + + VCVTTPH2QQZrmkz = 7942 + + VCVTTPH2QQZrr = 7943 + + VCVTTPH2QQZrrb = 7944 + + VCVTTPH2QQZrrbk = 7945 + + VCVTTPH2QQZrrbkz = 7946 + + VCVTTPH2QQZrrk = 7947 + + VCVTTPH2QQZrrkz = 7948 + + VCVTTPH2UDQZ128rm = 7949 + + VCVTTPH2UDQZ128rmb = 7950 + + VCVTTPH2UDQZ128rmbk = 7951 + + VCVTTPH2UDQZ128rmbkz = 7952 + + VCVTTPH2UDQZ128rmk = 7953 + + VCVTTPH2UDQZ128rmkz = 7954 + + VCVTTPH2UDQZ128rr = 7955 + + VCVTTPH2UDQZ128rrk = 7956 + + VCVTTPH2UDQZ128rrkz = 7957 + + VCVTTPH2UDQZ256rm = 7958 + + VCVTTPH2UDQZ256rmb = 7959 + + VCVTTPH2UDQZ256rmbk = 7960 + + VCVTTPH2UDQZ256rmbkz = 7961 + + VCVTTPH2UDQZ256rmk = 7962 + + VCVTTPH2UDQZ256rmkz = 7963 + + VCVTTPH2UDQZ256rr = 7964 + + VCVTTPH2UDQZ256rrk = 7965 + + VCVTTPH2UDQZ256rrkz = 7966 + + VCVTTPH2UDQZrm = 7967 + + VCVTTPH2UDQZrmb = 7968 + + VCVTTPH2UDQZrmbk = 7969 + + VCVTTPH2UDQZrmbkz = 7970 + + VCVTTPH2UDQZrmk = 7971 + + VCVTTPH2UDQZrmkz = 7972 + + VCVTTPH2UDQZrr = 7973 + + VCVTTPH2UDQZrrb = 7974 + + VCVTTPH2UDQZrrbk = 7975 + + VCVTTPH2UDQZrrbkz = 7976 + + VCVTTPH2UDQZrrk = 7977 + + VCVTTPH2UDQZrrkz = 7978 + + VCVTTPH2UQQZ128rm = 7979 + + VCVTTPH2UQQZ128rmb = 7980 + + VCVTTPH2UQQZ128rmbk = 7981 + + VCVTTPH2UQQZ128rmbkz = 7982 + + VCVTTPH2UQQZ128rmk = 7983 + + VCVTTPH2UQQZ128rmkz = 7984 + + VCVTTPH2UQQZ128rr = 7985 + + VCVTTPH2UQQZ128rrk = 7986 + + VCVTTPH2UQQZ128rrkz = 7987 + + VCVTTPH2UQQZ256rm = 7988 + + VCVTTPH2UQQZ256rmb = 7989 + + VCVTTPH2UQQZ256rmbk = 7990 + + VCVTTPH2UQQZ256rmbkz = 7991 + + VCVTTPH2UQQZ256rmk = 7992 + + VCVTTPH2UQQZ256rmkz = 7993 + + VCVTTPH2UQQZ256rr = 7994 + + VCVTTPH2UQQZ256rrk = 7995 + + VCVTTPH2UQQZ256rrkz = 7996 + + VCVTTPH2UQQZrm = 7997 + + VCVTTPH2UQQZrmb = 7998 + + VCVTTPH2UQQZrmbk = 7999 + + VCVTTPH2UQQZrmbkz = 8000 + + VCVTTPH2UQQZrmk = 8001 + + VCVTTPH2UQQZrmkz = 8002 + + VCVTTPH2UQQZrr = 8003 + + VCVTTPH2UQQZrrb = 8004 + + VCVTTPH2UQQZrrbk = 8005 + + VCVTTPH2UQQZrrbkz = 8006 + + VCVTTPH2UQQZrrk = 8007 + + VCVTTPH2UQQZrrkz = 8008 + + VCVTTPH2UWZ128rm = 8009 + + VCVTTPH2UWZ128rmb = 8010 + + VCVTTPH2UWZ128rmbk = 8011 + + VCVTTPH2UWZ128rmbkz = 8012 + + VCVTTPH2UWZ128rmk = 8013 + + VCVTTPH2UWZ128rmkz = 8014 + + VCVTTPH2UWZ128rr = 8015 + + VCVTTPH2UWZ128rrk = 8016 + + VCVTTPH2UWZ128rrkz = 8017 + + VCVTTPH2UWZ256rm = 8018 + + VCVTTPH2UWZ256rmb = 8019 + + VCVTTPH2UWZ256rmbk = 8020 + + VCVTTPH2UWZ256rmbkz = 8021 + + VCVTTPH2UWZ256rmk = 8022 + + VCVTTPH2UWZ256rmkz = 8023 + + VCVTTPH2UWZ256rr = 8024 + + VCVTTPH2UWZ256rrk = 8025 + + VCVTTPH2UWZ256rrkz = 8026 + + VCVTTPH2UWZrm = 8027 + + VCVTTPH2UWZrmb = 8028 + + VCVTTPH2UWZrmbk = 8029 + + VCVTTPH2UWZrmbkz = 8030 + + VCVTTPH2UWZrmk = 8031 + + VCVTTPH2UWZrmkz = 8032 + + VCVTTPH2UWZrr = 8033 + + VCVTTPH2UWZrrb = 8034 + + VCVTTPH2UWZrrbk = 8035 + + VCVTTPH2UWZrrbkz = 8036 + + VCVTTPH2UWZrrk = 8037 + + VCVTTPH2UWZrrkz = 8038 + + VCVTTPH2WZ128rm = 8039 + + VCVTTPH2WZ128rmb = 8040 + + VCVTTPH2WZ128rmbk = 8041 + + VCVTTPH2WZ128rmbkz = 8042 + + VCVTTPH2WZ128rmk = 8043 + + VCVTTPH2WZ128rmkz = 8044 + + VCVTTPH2WZ128rr = 8045 + + VCVTTPH2WZ128rrk = 8046 + + VCVTTPH2WZ128rrkz = 8047 + + VCVTTPH2WZ256rm = 8048 + + VCVTTPH2WZ256rmb = 8049 + + VCVTTPH2WZ256rmbk = 8050 + + VCVTTPH2WZ256rmbkz = 8051 + + VCVTTPH2WZ256rmk = 8052 + + VCVTTPH2WZ256rmkz = 8053 + + VCVTTPH2WZ256rr = 8054 + + VCVTTPH2WZ256rrk = 8055 + + VCVTTPH2WZ256rrkz = 8056 + + VCVTTPH2WZrm = 8057 + + VCVTTPH2WZrmb = 8058 + + VCVTTPH2WZrmbk = 8059 + + VCVTTPH2WZrmbkz = 8060 + + VCVTTPH2WZrmk = 8061 + + VCVTTPH2WZrmkz = 8062 + + VCVTTPH2WZrr = 8063 + + VCVTTPH2WZrrb = 8064 + + VCVTTPH2WZrrbk = 8065 + + VCVTTPH2WZrrbkz = 8066 + + VCVTTPH2WZrrk = 8067 + + VCVTTPH2WZrrkz = 8068 + + VCVTTPS2DQSZ128rm = 8069 + + VCVTTPS2DQSZ128rmb = 8070 + + VCVTTPS2DQSZ128rmbk = 8071 + + VCVTTPS2DQSZ128rmbkz = 8072 + + VCVTTPS2DQSZ128rmk = 8073 + + VCVTTPS2DQSZ128rmkz = 8074 + + VCVTTPS2DQSZ128rr = 8075 + + VCVTTPS2DQSZ128rrk = 8076 + + VCVTTPS2DQSZ128rrkz = 8077 + + VCVTTPS2DQSZ256rm = 8078 + + VCVTTPS2DQSZ256rmb = 8079 + + VCVTTPS2DQSZ256rmbk = 8080 + + VCVTTPS2DQSZ256rmbkz = 8081 + + VCVTTPS2DQSZ256rmk = 8082 + + VCVTTPS2DQSZ256rmkz = 8083 + + VCVTTPS2DQSZ256rr = 8084 + + VCVTTPS2DQSZ256rrk = 8085 + + VCVTTPS2DQSZ256rrkz = 8086 + + VCVTTPS2DQSZrm = 8087 + + VCVTTPS2DQSZrmb = 8088 + + VCVTTPS2DQSZrmbk = 8089 + + VCVTTPS2DQSZrmbkz = 8090 + + VCVTTPS2DQSZrmk = 8091 + + VCVTTPS2DQSZrmkz = 8092 + + VCVTTPS2DQSZrr = 8093 + + VCVTTPS2DQSZrrb = 8094 + + VCVTTPS2DQSZrrbk = 8095 + + VCVTTPS2DQSZrrbkz = 8096 + + VCVTTPS2DQSZrrk = 8097 + + VCVTTPS2DQSZrrkz = 8098 + + VCVTTPS2DQYrm = 8099 + + VCVTTPS2DQYrr = 8100 + + VCVTTPS2DQZ128rm = 8101 + + VCVTTPS2DQZ128rmb = 8102 + + VCVTTPS2DQZ128rmbk = 8103 + + VCVTTPS2DQZ128rmbkz = 8104 + + VCVTTPS2DQZ128rmk = 8105 + + VCVTTPS2DQZ128rmkz = 8106 + + VCVTTPS2DQZ128rr = 8107 + + VCVTTPS2DQZ128rrk = 8108 + + VCVTTPS2DQZ128rrkz = 8109 + + VCVTTPS2DQZ256rm = 8110 + + VCVTTPS2DQZ256rmb = 8111 + + VCVTTPS2DQZ256rmbk = 8112 + + VCVTTPS2DQZ256rmbkz = 8113 + + VCVTTPS2DQZ256rmk = 8114 + + VCVTTPS2DQZ256rmkz = 8115 + + VCVTTPS2DQZ256rr = 8116 + + VCVTTPS2DQZ256rrk = 8117 + + VCVTTPS2DQZ256rrkz = 8118 + + VCVTTPS2DQZrm = 8119 + + VCVTTPS2DQZrmb = 8120 + + VCVTTPS2DQZrmbk = 8121 + + VCVTTPS2DQZrmbkz = 8122 + + VCVTTPS2DQZrmk = 8123 + + VCVTTPS2DQZrmkz = 8124 + + VCVTTPS2DQZrr = 8125 + + VCVTTPS2DQZrrb = 8126 + + VCVTTPS2DQZrrbk = 8127 + + VCVTTPS2DQZrrbkz = 8128 + + VCVTTPS2DQZrrk = 8129 + + VCVTTPS2DQZrrkz = 8130 + + VCVTTPS2DQrm = 8131 + + VCVTTPS2DQrr = 8132 + + VCVTTPS2IBSZ128rm = 8133 + + VCVTTPS2IBSZ128rmb = 8134 + + VCVTTPS2IBSZ128rmbk = 8135 + + VCVTTPS2IBSZ128rmbkz = 8136 + + VCVTTPS2IBSZ128rmk = 8137 + + VCVTTPS2IBSZ128rmkz = 8138 + + VCVTTPS2IBSZ128rr = 8139 + + VCVTTPS2IBSZ128rrk = 8140 + + VCVTTPS2IBSZ128rrkz = 8141 + + VCVTTPS2IBSZ256rm = 8142 + + VCVTTPS2IBSZ256rmb = 8143 + + VCVTTPS2IBSZ256rmbk = 8144 + + VCVTTPS2IBSZ256rmbkz = 8145 + + VCVTTPS2IBSZ256rmk = 8146 + + VCVTTPS2IBSZ256rmkz = 8147 + + VCVTTPS2IBSZ256rr = 8148 + + VCVTTPS2IBSZ256rrk = 8149 + + VCVTTPS2IBSZ256rrkz = 8150 + + VCVTTPS2IBSZrm = 8151 + + VCVTTPS2IBSZrmb = 8152 + + VCVTTPS2IBSZrmbk = 8153 + + VCVTTPS2IBSZrmbkz = 8154 + + VCVTTPS2IBSZrmk = 8155 + + VCVTTPS2IBSZrmkz = 8156 + + VCVTTPS2IBSZrr = 8157 + + VCVTTPS2IBSZrrb = 8158 + + VCVTTPS2IBSZrrbk = 8159 + + VCVTTPS2IBSZrrbkz = 8160 + + VCVTTPS2IBSZrrk = 8161 + + VCVTTPS2IBSZrrkz = 8162 + + VCVTTPS2IUBSZ128rm = 8163 + + VCVTTPS2IUBSZ128rmb = 8164 + + VCVTTPS2IUBSZ128rmbk = 8165 + + VCVTTPS2IUBSZ128rmbkz = 8166 + + VCVTTPS2IUBSZ128rmk = 8167 + + VCVTTPS2IUBSZ128rmkz = 8168 + + VCVTTPS2IUBSZ128rr = 8169 + + VCVTTPS2IUBSZ128rrk = 8170 + + VCVTTPS2IUBSZ128rrkz = 8171 + + VCVTTPS2IUBSZ256rm = 8172 + + VCVTTPS2IUBSZ256rmb = 8173 + + VCVTTPS2IUBSZ256rmbk = 8174 + + VCVTTPS2IUBSZ256rmbkz = 8175 + + VCVTTPS2IUBSZ256rmk = 8176 + + VCVTTPS2IUBSZ256rmkz = 8177 + + VCVTTPS2IUBSZ256rr = 8178 + + VCVTTPS2IUBSZ256rrk = 8179 + + VCVTTPS2IUBSZ256rrkz = 8180 + + VCVTTPS2IUBSZrm = 8181 + + VCVTTPS2IUBSZrmb = 8182 + + VCVTTPS2IUBSZrmbk = 8183 + + VCVTTPS2IUBSZrmbkz = 8184 + + VCVTTPS2IUBSZrmk = 8185 + + VCVTTPS2IUBSZrmkz = 8186 + + VCVTTPS2IUBSZrr = 8187 + + VCVTTPS2IUBSZrrb = 8188 + + VCVTTPS2IUBSZrrbk = 8189 + + VCVTTPS2IUBSZrrbkz = 8190 + + VCVTTPS2IUBSZrrk = 8191 + + VCVTTPS2IUBSZrrkz = 8192 + + VCVTTPS2QQSZ128rm = 8193 + + VCVTTPS2QQSZ128rmb = 8194 + + VCVTTPS2QQSZ128rmbk = 8195 + + VCVTTPS2QQSZ128rmbkz = 8196 + + VCVTTPS2QQSZ128rmk = 8197 + + VCVTTPS2QQSZ128rmkz = 8198 + + VCVTTPS2QQSZ128rr = 8199 + + VCVTTPS2QQSZ128rrk = 8200 + + VCVTTPS2QQSZ128rrkz = 8201 + + VCVTTPS2QQSZ256rm = 8202 + + VCVTTPS2QQSZ256rmb = 8203 + + VCVTTPS2QQSZ256rmbk = 8204 + + VCVTTPS2QQSZ256rmbkz = 8205 + + VCVTTPS2QQSZ256rmk = 8206 + + VCVTTPS2QQSZ256rmkz = 8207 + + VCVTTPS2QQSZ256rr = 8208 + + VCVTTPS2QQSZ256rrb = 8209 + + VCVTTPS2QQSZ256rrbk = 8210 + + VCVTTPS2QQSZ256rrbkz = 8211 + + VCVTTPS2QQSZ256rrk = 8212 + + VCVTTPS2QQSZ256rrkz = 8213 + + VCVTTPS2QQSZrm = 8214 + + VCVTTPS2QQSZrmb = 8215 + + VCVTTPS2QQSZrmbk = 8216 + + VCVTTPS2QQSZrmbkz = 8217 + + VCVTTPS2QQSZrmk = 8218 + + VCVTTPS2QQSZrmkz = 8219 + + VCVTTPS2QQSZrr = 8220 + + VCVTTPS2QQSZrrb = 8221 + + VCVTTPS2QQSZrrbk = 8222 + + VCVTTPS2QQSZrrbkz = 8223 + + VCVTTPS2QQSZrrk = 8224 + + VCVTTPS2QQSZrrkz = 8225 + + VCVTTPS2QQZ128rm = 8226 + + VCVTTPS2QQZ128rmb = 8227 + + VCVTTPS2QQZ128rmbk = 8228 + + VCVTTPS2QQZ128rmbkz = 8229 + + VCVTTPS2QQZ128rmk = 8230 + + VCVTTPS2QQZ128rmkz = 8231 + + VCVTTPS2QQZ128rr = 8232 + + VCVTTPS2QQZ128rrk = 8233 + + VCVTTPS2QQZ128rrkz = 8234 + + VCVTTPS2QQZ256rm = 8235 + + VCVTTPS2QQZ256rmb = 8236 + + VCVTTPS2QQZ256rmbk = 8237 + + VCVTTPS2QQZ256rmbkz = 8238 + + VCVTTPS2QQZ256rmk = 8239 + + VCVTTPS2QQZ256rmkz = 8240 + + VCVTTPS2QQZ256rr = 8241 + + VCVTTPS2QQZ256rrk = 8242 + + VCVTTPS2QQZ256rrkz = 8243 + + VCVTTPS2QQZrm = 8244 + + VCVTTPS2QQZrmb = 8245 + + VCVTTPS2QQZrmbk = 8246 + + VCVTTPS2QQZrmbkz = 8247 + + VCVTTPS2QQZrmk = 8248 + + VCVTTPS2QQZrmkz = 8249 + + VCVTTPS2QQZrr = 8250 + + VCVTTPS2QQZrrb = 8251 + + VCVTTPS2QQZrrbk = 8252 + + VCVTTPS2QQZrrbkz = 8253 + + VCVTTPS2QQZrrk = 8254 + + VCVTTPS2QQZrrkz = 8255 + + VCVTTPS2UDQSZ128rm = 8256 + + VCVTTPS2UDQSZ128rmb = 8257 + + VCVTTPS2UDQSZ128rmbk = 8258 + + VCVTTPS2UDQSZ128rmbkz = 8259 + + VCVTTPS2UDQSZ128rmk = 8260 + + VCVTTPS2UDQSZ128rmkz = 8261 + + VCVTTPS2UDQSZ128rr = 8262 + + VCVTTPS2UDQSZ128rrk = 8263 + + VCVTTPS2UDQSZ128rrkz = 8264 + + VCVTTPS2UDQSZ256rm = 8265 + + VCVTTPS2UDQSZ256rmb = 8266 + + VCVTTPS2UDQSZ256rmbk = 8267 + + VCVTTPS2UDQSZ256rmbkz = 8268 + + VCVTTPS2UDQSZ256rmk = 8269 + + VCVTTPS2UDQSZ256rmkz = 8270 + + VCVTTPS2UDQSZ256rr = 8271 + + VCVTTPS2UDQSZ256rrk = 8272 + + VCVTTPS2UDQSZ256rrkz = 8273 + + VCVTTPS2UDQSZrm = 8274 + + VCVTTPS2UDQSZrmb = 8275 + + VCVTTPS2UDQSZrmbk = 8276 + + VCVTTPS2UDQSZrmbkz = 8277 + + VCVTTPS2UDQSZrmk = 8278 + + VCVTTPS2UDQSZrmkz = 8279 + + VCVTTPS2UDQSZrr = 8280 + + VCVTTPS2UDQSZrrb = 8281 + + VCVTTPS2UDQSZrrbk = 8282 + + VCVTTPS2UDQSZrrbkz = 8283 + + VCVTTPS2UDQSZrrk = 8284 + + VCVTTPS2UDQSZrrkz = 8285 + + VCVTTPS2UDQZ128rm = 8286 + + VCVTTPS2UDQZ128rmb = 8287 + + VCVTTPS2UDQZ128rmbk = 8288 + + VCVTTPS2UDQZ128rmbkz = 8289 + + VCVTTPS2UDQZ128rmk = 8290 + + VCVTTPS2UDQZ128rmkz = 8291 + + VCVTTPS2UDQZ128rr = 8292 + + VCVTTPS2UDQZ128rrk = 8293 + + VCVTTPS2UDQZ128rrkz = 8294 + + VCVTTPS2UDQZ256rm = 8295 + + VCVTTPS2UDQZ256rmb = 8296 + + VCVTTPS2UDQZ256rmbk = 8297 + + VCVTTPS2UDQZ256rmbkz = 8298 + + VCVTTPS2UDQZ256rmk = 8299 + + VCVTTPS2UDQZ256rmkz = 8300 + + VCVTTPS2UDQZ256rr = 8301 + + VCVTTPS2UDQZ256rrk = 8302 + + VCVTTPS2UDQZ256rrkz = 8303 + + VCVTTPS2UDQZrm = 8304 + + VCVTTPS2UDQZrmb = 8305 + + VCVTTPS2UDQZrmbk = 8306 + + VCVTTPS2UDQZrmbkz = 8307 + + VCVTTPS2UDQZrmk = 8308 + + VCVTTPS2UDQZrmkz = 8309 + + VCVTTPS2UDQZrr = 8310 + + VCVTTPS2UDQZrrb = 8311 + + VCVTTPS2UDQZrrbk = 8312 + + VCVTTPS2UDQZrrbkz = 8313 + + VCVTTPS2UDQZrrk = 8314 + + VCVTTPS2UDQZrrkz = 8315 + + VCVTTPS2UQQSZ128rm = 8316 + + VCVTTPS2UQQSZ128rmb = 8317 + + VCVTTPS2UQQSZ128rmbk = 8318 + + VCVTTPS2UQQSZ128rmbkz = 8319 + + VCVTTPS2UQQSZ128rmk = 8320 + + VCVTTPS2UQQSZ128rmkz = 8321 + + VCVTTPS2UQQSZ128rr = 8322 + + VCVTTPS2UQQSZ128rrk = 8323 + + VCVTTPS2UQQSZ128rrkz = 8324 + + VCVTTPS2UQQSZ256rm = 8325 + + VCVTTPS2UQQSZ256rmb = 8326 + + VCVTTPS2UQQSZ256rmbk = 8327 + + VCVTTPS2UQQSZ256rmbkz = 8328 + + VCVTTPS2UQQSZ256rmk = 8329 + + VCVTTPS2UQQSZ256rmkz = 8330 + + VCVTTPS2UQQSZ256rr = 8331 + + VCVTTPS2UQQSZ256rrb = 8332 + + VCVTTPS2UQQSZ256rrbk = 8333 + + VCVTTPS2UQQSZ256rrbkz = 8334 + + VCVTTPS2UQQSZ256rrk = 8335 + + VCVTTPS2UQQSZ256rrkz = 8336 + + VCVTTPS2UQQSZrm = 8337 + + VCVTTPS2UQQSZrmb = 8338 + + VCVTTPS2UQQSZrmbk = 8339 + + VCVTTPS2UQQSZrmbkz = 8340 + + VCVTTPS2UQQSZrmk = 8341 + + VCVTTPS2UQQSZrmkz = 8342 + + VCVTTPS2UQQSZrr = 8343 + + VCVTTPS2UQQSZrrb = 8344 + + VCVTTPS2UQQSZrrbk = 8345 + + VCVTTPS2UQQSZrrbkz = 8346 + + VCVTTPS2UQQSZrrk = 8347 + + VCVTTPS2UQQSZrrkz = 8348 + + VCVTTPS2UQQZ128rm = 8349 + + VCVTTPS2UQQZ128rmb = 8350 + + VCVTTPS2UQQZ128rmbk = 8351 + + VCVTTPS2UQQZ128rmbkz = 8352 + + VCVTTPS2UQQZ128rmk = 8353 + + VCVTTPS2UQQZ128rmkz = 8354 + + VCVTTPS2UQQZ128rr = 8355 + + VCVTTPS2UQQZ128rrk = 8356 + + VCVTTPS2UQQZ128rrkz = 8357 + + VCVTTPS2UQQZ256rm = 8358 + + VCVTTPS2UQQZ256rmb = 8359 + + VCVTTPS2UQQZ256rmbk = 8360 + + VCVTTPS2UQQZ256rmbkz = 8361 + + VCVTTPS2UQQZ256rmk = 8362 + + VCVTTPS2UQQZ256rmkz = 8363 + + VCVTTPS2UQQZ256rr = 8364 + + VCVTTPS2UQQZ256rrk = 8365 + + VCVTTPS2UQQZ256rrkz = 8366 + + VCVTTPS2UQQZrm = 8367 + + VCVTTPS2UQQZrmb = 8368 + + VCVTTPS2UQQZrmbk = 8369 + + VCVTTPS2UQQZrmbkz = 8370 + + VCVTTPS2UQQZrmk = 8371 + + VCVTTPS2UQQZrmkz = 8372 + + VCVTTPS2UQQZrr = 8373 + + VCVTTPS2UQQZrrb = 8374 + + VCVTTPS2UQQZrrbk = 8375 + + VCVTTPS2UQQZrrbkz = 8376 + + VCVTTPS2UQQZrrk = 8377 + + VCVTTPS2UQQZrrkz = 8378 + + VCVTTSD2SI64Srm = 8379 + + VCVTTSD2SI64Srm_Int = 8380 + + VCVTTSD2SI64Srr = 8381 + + VCVTTSD2SI64Srr_Int = 8382 + + VCVTTSD2SI64Srrb_Int = 8383 + + VCVTTSD2SI64Zrm = 8384 + + VCVTTSD2SI64Zrm_Int = 8385 + + VCVTTSD2SI64Zrr = 8386 + + VCVTTSD2SI64Zrr_Int = 8387 + + VCVTTSD2SI64Zrrb_Int = 8388 + + VCVTTSD2SI64rm = 8389 + + VCVTTSD2SI64rm_Int = 8390 + + VCVTTSD2SI64rr = 8391 + + VCVTTSD2SI64rr_Int = 8392 + + VCVTTSD2SISrm = 8393 + + VCVTTSD2SISrm_Int = 8394 + + VCVTTSD2SISrr = 8395 + + VCVTTSD2SISrr_Int = 8396 + + VCVTTSD2SISrrb_Int = 8397 + + VCVTTSD2SIZrm = 8398 + + VCVTTSD2SIZrm_Int = 8399 + + VCVTTSD2SIZrr = 8400 + + VCVTTSD2SIZrr_Int = 8401 + + VCVTTSD2SIZrrb_Int = 8402 + + VCVTTSD2SIrm = 8403 + + VCVTTSD2SIrm_Int = 8404 + + VCVTTSD2SIrr = 8405 + + VCVTTSD2SIrr_Int = 8406 + + VCVTTSD2USI64Srm = 8407 + + VCVTTSD2USI64Srm_Int = 8408 + + VCVTTSD2USI64Srr = 8409 + + VCVTTSD2USI64Srr_Int = 8410 + + VCVTTSD2USI64Srrb_Int = 8411 + + VCVTTSD2USI64Zrm = 8412 + + VCVTTSD2USI64Zrm_Int = 8413 + + VCVTTSD2USI64Zrr = 8414 + + VCVTTSD2USI64Zrr_Int = 8415 + + VCVTTSD2USI64Zrrb_Int = 8416 + + VCVTTSD2USISrm = 8417 + + VCVTTSD2USISrm_Int = 8418 + + VCVTTSD2USISrr = 8419 + + VCVTTSD2USISrr_Int = 8420 + + VCVTTSD2USISrrb_Int = 8421 + + VCVTTSD2USIZrm = 8422 + + VCVTTSD2USIZrm_Int = 8423 + + VCVTTSD2USIZrr = 8424 + + VCVTTSD2USIZrr_Int = 8425 + + VCVTTSD2USIZrrb_Int = 8426 + + VCVTTSH2SI64Zrm = 8427 + + VCVTTSH2SI64Zrm_Int = 8428 + + VCVTTSH2SI64Zrr = 8429 + + VCVTTSH2SI64Zrr_Int = 8430 + + VCVTTSH2SI64Zrrb_Int = 8431 + + VCVTTSH2SIZrm = 8432 + + VCVTTSH2SIZrm_Int = 8433 + + VCVTTSH2SIZrr = 8434 + + VCVTTSH2SIZrr_Int = 8435 + + VCVTTSH2SIZrrb_Int = 8436 + + VCVTTSH2USI64Zrm = 8437 + + VCVTTSH2USI64Zrm_Int = 8438 + + VCVTTSH2USI64Zrr = 8439 + + VCVTTSH2USI64Zrr_Int = 8440 + + VCVTTSH2USI64Zrrb_Int = 8441 + + VCVTTSH2USIZrm = 8442 + + VCVTTSH2USIZrm_Int = 8443 + + VCVTTSH2USIZrr = 8444 + + VCVTTSH2USIZrr_Int = 8445 + + VCVTTSH2USIZrrb_Int = 8446 + + VCVTTSS2SI64Srm = 8447 + + VCVTTSS2SI64Srm_Int = 8448 + + VCVTTSS2SI64Srr = 8449 + + VCVTTSS2SI64Srr_Int = 8450 + + VCVTTSS2SI64Srrb_Int = 8451 + + VCVTTSS2SI64Zrm = 8452 + + VCVTTSS2SI64Zrm_Int = 8453 + + VCVTTSS2SI64Zrr = 8454 + + VCVTTSS2SI64Zrr_Int = 8455 + + VCVTTSS2SI64Zrrb_Int = 8456 + + VCVTTSS2SI64rm = 8457 + + VCVTTSS2SI64rm_Int = 8458 + + VCVTTSS2SI64rr = 8459 + + VCVTTSS2SI64rr_Int = 8460 + + VCVTTSS2SISrm = 8461 + + VCVTTSS2SISrm_Int = 8462 + + VCVTTSS2SISrr = 8463 + + VCVTTSS2SISrr_Int = 8464 + + VCVTTSS2SISrrb_Int = 8465 + + VCVTTSS2SIZrm = 8466 + + VCVTTSS2SIZrm_Int = 8467 + + VCVTTSS2SIZrr = 8468 + + VCVTTSS2SIZrr_Int = 8469 + + VCVTTSS2SIZrrb_Int = 8470 + + VCVTTSS2SIrm = 8471 + + VCVTTSS2SIrm_Int = 8472 + + VCVTTSS2SIrr = 8473 + + VCVTTSS2SIrr_Int = 8474 + + VCVTTSS2USI64Srm = 8475 + + VCVTTSS2USI64Srm_Int = 8476 + + VCVTTSS2USI64Srr = 8477 + + VCVTTSS2USI64Srr_Int = 8478 + + VCVTTSS2USI64Srrb_Int = 8479 + + VCVTTSS2USI64Zrm = 8480 + + VCVTTSS2USI64Zrm_Int = 8481 + + VCVTTSS2USI64Zrr = 8482 + + VCVTTSS2USI64Zrr_Int = 8483 + + VCVTTSS2USI64Zrrb_Int = 8484 + + VCVTTSS2USISrm = 8485 + + VCVTTSS2USISrm_Int = 8486 + + VCVTTSS2USISrr = 8487 + + VCVTTSS2USISrr_Int = 8488 + + VCVTTSS2USISrrb_Int = 8489 + + VCVTTSS2USIZrm = 8490 + + VCVTTSS2USIZrm_Int = 8491 + + VCVTTSS2USIZrr = 8492 + + VCVTTSS2USIZrr_Int = 8493 + + VCVTTSS2USIZrrb_Int = 8494 + + VCVTUDQ2PDZ128rm = 8495 + + VCVTUDQ2PDZ128rmb = 8496 + + VCVTUDQ2PDZ128rmbk = 8497 + + VCVTUDQ2PDZ128rmbkz = 8498 + + VCVTUDQ2PDZ128rmk = 8499 + + VCVTUDQ2PDZ128rmkz = 8500 + + VCVTUDQ2PDZ128rr = 8501 + + VCVTUDQ2PDZ128rrk = 8502 + + VCVTUDQ2PDZ128rrkz = 8503 + + VCVTUDQ2PDZ256rm = 8504 + + VCVTUDQ2PDZ256rmb = 8505 + + VCVTUDQ2PDZ256rmbk = 8506 + + VCVTUDQ2PDZ256rmbkz = 8507 + + VCVTUDQ2PDZ256rmk = 8508 + + VCVTUDQ2PDZ256rmkz = 8509 + + VCVTUDQ2PDZ256rr = 8510 + + VCVTUDQ2PDZ256rrk = 8511 + + VCVTUDQ2PDZ256rrkz = 8512 + + VCVTUDQ2PDZrm = 8513 + + VCVTUDQ2PDZrmb = 8514 + + VCVTUDQ2PDZrmbk = 8515 + + VCVTUDQ2PDZrmbkz = 8516 + + VCVTUDQ2PDZrmk = 8517 + + VCVTUDQ2PDZrmkz = 8518 + + VCVTUDQ2PDZrr = 8519 + + VCVTUDQ2PDZrrk = 8520 + + VCVTUDQ2PDZrrkz = 8521 + + VCVTUDQ2PHZ128rm = 8522 + + VCVTUDQ2PHZ128rmb = 8523 + + VCVTUDQ2PHZ128rmbk = 8524 + + VCVTUDQ2PHZ128rmbkz = 8525 + + VCVTUDQ2PHZ128rmk = 8526 + + VCVTUDQ2PHZ128rmkz = 8527 + + VCVTUDQ2PHZ128rr = 8528 + + VCVTUDQ2PHZ128rrk = 8529 + + VCVTUDQ2PHZ128rrkz = 8530 + + VCVTUDQ2PHZ256rm = 8531 + + VCVTUDQ2PHZ256rmb = 8532 + + VCVTUDQ2PHZ256rmbk = 8533 + + VCVTUDQ2PHZ256rmbkz = 8534 + + VCVTUDQ2PHZ256rmk = 8535 + + VCVTUDQ2PHZ256rmkz = 8536 + + VCVTUDQ2PHZ256rr = 8537 + + VCVTUDQ2PHZ256rrk = 8538 + + VCVTUDQ2PHZ256rrkz = 8539 + + VCVTUDQ2PHZrm = 8540 + + VCVTUDQ2PHZrmb = 8541 + + VCVTUDQ2PHZrmbk = 8542 + + VCVTUDQ2PHZrmbkz = 8543 + + VCVTUDQ2PHZrmk = 8544 + + VCVTUDQ2PHZrmkz = 8545 + + VCVTUDQ2PHZrr = 8546 + + VCVTUDQ2PHZrrb = 8547 + + VCVTUDQ2PHZrrbk = 8548 + + VCVTUDQ2PHZrrbkz = 8549 + + VCVTUDQ2PHZrrk = 8550 + + VCVTUDQ2PHZrrkz = 8551 + + VCVTUDQ2PSZ128rm = 8552 + + VCVTUDQ2PSZ128rmb = 8553 + + VCVTUDQ2PSZ128rmbk = 8554 + + VCVTUDQ2PSZ128rmbkz = 8555 + + VCVTUDQ2PSZ128rmk = 8556 + + VCVTUDQ2PSZ128rmkz = 8557 + + VCVTUDQ2PSZ128rr = 8558 + + VCVTUDQ2PSZ128rrk = 8559 + + VCVTUDQ2PSZ128rrkz = 8560 + + VCVTUDQ2PSZ256rm = 8561 + + VCVTUDQ2PSZ256rmb = 8562 + + VCVTUDQ2PSZ256rmbk = 8563 + + VCVTUDQ2PSZ256rmbkz = 8564 + + VCVTUDQ2PSZ256rmk = 8565 + + VCVTUDQ2PSZ256rmkz = 8566 + + VCVTUDQ2PSZ256rr = 8567 + + VCVTUDQ2PSZ256rrk = 8568 + + VCVTUDQ2PSZ256rrkz = 8569 + + VCVTUDQ2PSZrm = 8570 + + VCVTUDQ2PSZrmb = 8571 + + VCVTUDQ2PSZrmbk = 8572 + + VCVTUDQ2PSZrmbkz = 8573 + + VCVTUDQ2PSZrmk = 8574 + + VCVTUDQ2PSZrmkz = 8575 + + VCVTUDQ2PSZrr = 8576 + + VCVTUDQ2PSZrrb = 8577 + + VCVTUDQ2PSZrrbk = 8578 + + VCVTUDQ2PSZrrbkz = 8579 + + VCVTUDQ2PSZrrk = 8580 + + VCVTUDQ2PSZrrkz = 8581 + + VCVTUQQ2PDZ128rm = 8582 + + VCVTUQQ2PDZ128rmb = 8583 + + VCVTUQQ2PDZ128rmbk = 8584 + + VCVTUQQ2PDZ128rmbkz = 8585 + + VCVTUQQ2PDZ128rmk = 8586 + + VCVTUQQ2PDZ128rmkz = 8587 + + VCVTUQQ2PDZ128rr = 8588 + + VCVTUQQ2PDZ128rrk = 8589 + + VCVTUQQ2PDZ128rrkz = 8590 + + VCVTUQQ2PDZ256rm = 8591 + + VCVTUQQ2PDZ256rmb = 8592 + + VCVTUQQ2PDZ256rmbk = 8593 + + VCVTUQQ2PDZ256rmbkz = 8594 + + VCVTUQQ2PDZ256rmk = 8595 + + VCVTUQQ2PDZ256rmkz = 8596 + + VCVTUQQ2PDZ256rr = 8597 + + VCVTUQQ2PDZ256rrk = 8598 + + VCVTUQQ2PDZ256rrkz = 8599 + + VCVTUQQ2PDZrm = 8600 + + VCVTUQQ2PDZrmb = 8601 + + VCVTUQQ2PDZrmbk = 8602 + + VCVTUQQ2PDZrmbkz = 8603 + + VCVTUQQ2PDZrmk = 8604 + + VCVTUQQ2PDZrmkz = 8605 + + VCVTUQQ2PDZrr = 8606 + + VCVTUQQ2PDZrrb = 8607 + + VCVTUQQ2PDZrrbk = 8608 + + VCVTUQQ2PDZrrbkz = 8609 + + VCVTUQQ2PDZrrk = 8610 + + VCVTUQQ2PDZrrkz = 8611 + + VCVTUQQ2PHZ128rm = 8612 + + VCVTUQQ2PHZ128rmb = 8613 + + VCVTUQQ2PHZ128rmbk = 8614 + + VCVTUQQ2PHZ128rmbkz = 8615 + + VCVTUQQ2PHZ128rmk = 8616 + + VCVTUQQ2PHZ128rmkz = 8617 + + VCVTUQQ2PHZ128rr = 8618 + + VCVTUQQ2PHZ128rrk = 8619 + + VCVTUQQ2PHZ128rrkz = 8620 + + VCVTUQQ2PHZ256rm = 8621 + + VCVTUQQ2PHZ256rmb = 8622 + + VCVTUQQ2PHZ256rmbk = 8623 + + VCVTUQQ2PHZ256rmbkz = 8624 + + VCVTUQQ2PHZ256rmk = 8625 + + VCVTUQQ2PHZ256rmkz = 8626 + + VCVTUQQ2PHZ256rr = 8627 + + VCVTUQQ2PHZ256rrk = 8628 + + VCVTUQQ2PHZ256rrkz = 8629 + + VCVTUQQ2PHZrm = 8630 + + VCVTUQQ2PHZrmb = 8631 + + VCVTUQQ2PHZrmbk = 8632 + + VCVTUQQ2PHZrmbkz = 8633 + + VCVTUQQ2PHZrmk = 8634 + + VCVTUQQ2PHZrmkz = 8635 + + VCVTUQQ2PHZrr = 8636 + + VCVTUQQ2PHZrrb = 8637 + + VCVTUQQ2PHZrrbk = 8638 + + VCVTUQQ2PHZrrbkz = 8639 + + VCVTUQQ2PHZrrk = 8640 + + VCVTUQQ2PHZrrkz = 8641 + + VCVTUQQ2PSZ128rm = 8642 + + VCVTUQQ2PSZ128rmb = 8643 + + VCVTUQQ2PSZ128rmbk = 8644 + + VCVTUQQ2PSZ128rmbkz = 8645 + + VCVTUQQ2PSZ128rmk = 8646 + + VCVTUQQ2PSZ128rmkz = 8647 + + VCVTUQQ2PSZ128rr = 8648 + + VCVTUQQ2PSZ128rrk = 8649 + + VCVTUQQ2PSZ128rrkz = 8650 + + VCVTUQQ2PSZ256rm = 8651 + + VCVTUQQ2PSZ256rmb = 8652 + + VCVTUQQ2PSZ256rmbk = 8653 + + VCVTUQQ2PSZ256rmbkz = 8654 + + VCVTUQQ2PSZ256rmk = 8655 + + VCVTUQQ2PSZ256rmkz = 8656 + + VCVTUQQ2PSZ256rr = 8657 + + VCVTUQQ2PSZ256rrk = 8658 + + VCVTUQQ2PSZ256rrkz = 8659 + + VCVTUQQ2PSZrm = 8660 + + VCVTUQQ2PSZrmb = 8661 + + VCVTUQQ2PSZrmbk = 8662 + + VCVTUQQ2PSZrmbkz = 8663 + + VCVTUQQ2PSZrmk = 8664 + + VCVTUQQ2PSZrmkz = 8665 + + VCVTUQQ2PSZrr = 8666 + + VCVTUQQ2PSZrrb = 8667 + + VCVTUQQ2PSZrrbk = 8668 + + VCVTUQQ2PSZrrbkz = 8669 + + VCVTUQQ2PSZrrk = 8670 + + VCVTUQQ2PSZrrkz = 8671 + + VCVTUSI2SDZrm = 8672 + + VCVTUSI2SDZrm_Int = 8673 + + VCVTUSI2SDZrr = 8674 + + VCVTUSI2SDZrr_Int = 8675 + + VCVTUSI2SHZrm = 8676 + + VCVTUSI2SHZrm_Int = 8677 + + VCVTUSI2SHZrr = 8678 + + VCVTUSI2SHZrr_Int = 8679 + + VCVTUSI2SHZrrb_Int = 8680 + + VCVTUSI2SSZrm = 8681 + + VCVTUSI2SSZrm_Int = 8682 + + VCVTUSI2SSZrr = 8683 + + VCVTUSI2SSZrr_Int = 8684 + + VCVTUSI2SSZrrb_Int = 8685 + + VCVTUSI642SDZrm = 8686 + + VCVTUSI642SDZrm_Int = 8687 + + VCVTUSI642SDZrr = 8688 + + VCVTUSI642SDZrr_Int = 8689 + + VCVTUSI642SDZrrb_Int = 8690 + + VCVTUSI642SHZrm = 8691 + + VCVTUSI642SHZrm_Int = 8692 + + VCVTUSI642SHZrr = 8693 + + VCVTUSI642SHZrr_Int = 8694 + + VCVTUSI642SHZrrb_Int = 8695 + + VCVTUSI642SSZrm = 8696 + + VCVTUSI642SSZrm_Int = 8697 + + VCVTUSI642SSZrr = 8698 + + VCVTUSI642SSZrr_Int = 8699 + + VCVTUSI642SSZrrb_Int = 8700 + + VCVTUW2PHZ128rm = 8701 + + VCVTUW2PHZ128rmb = 8702 + + VCVTUW2PHZ128rmbk = 8703 + + VCVTUW2PHZ128rmbkz = 8704 + + VCVTUW2PHZ128rmk = 8705 + + VCVTUW2PHZ128rmkz = 8706 + + VCVTUW2PHZ128rr = 8707 + + VCVTUW2PHZ128rrk = 8708 + + VCVTUW2PHZ128rrkz = 8709 + + VCVTUW2PHZ256rm = 8710 + + VCVTUW2PHZ256rmb = 8711 + + VCVTUW2PHZ256rmbk = 8712 + + VCVTUW2PHZ256rmbkz = 8713 + + VCVTUW2PHZ256rmk = 8714 + + VCVTUW2PHZ256rmkz = 8715 + + VCVTUW2PHZ256rr = 8716 + + VCVTUW2PHZ256rrk = 8717 + + VCVTUW2PHZ256rrkz = 8718 + + VCVTUW2PHZrm = 8719 + + VCVTUW2PHZrmb = 8720 + + VCVTUW2PHZrmbk = 8721 + + VCVTUW2PHZrmbkz = 8722 + + VCVTUW2PHZrmk = 8723 + + VCVTUW2PHZrmkz = 8724 + + VCVTUW2PHZrr = 8725 + + VCVTUW2PHZrrb = 8726 + + VCVTUW2PHZrrbk = 8727 + + VCVTUW2PHZrrbkz = 8728 + + VCVTUW2PHZrrk = 8729 + + VCVTUW2PHZrrkz = 8730 + + VCVTW2PHZ128rm = 8731 + + VCVTW2PHZ128rmb = 8732 + + VCVTW2PHZ128rmbk = 8733 + + VCVTW2PHZ128rmbkz = 8734 + + VCVTW2PHZ128rmk = 8735 + + VCVTW2PHZ128rmkz = 8736 + + VCVTW2PHZ128rr = 8737 + + VCVTW2PHZ128rrk = 8738 + + VCVTW2PHZ128rrkz = 8739 + + VCVTW2PHZ256rm = 8740 + + VCVTW2PHZ256rmb = 8741 + + VCVTW2PHZ256rmbk = 8742 + + VCVTW2PHZ256rmbkz = 8743 + + VCVTW2PHZ256rmk = 8744 + + VCVTW2PHZ256rmkz = 8745 + + VCVTW2PHZ256rr = 8746 + + VCVTW2PHZ256rrk = 8747 + + VCVTW2PHZ256rrkz = 8748 + + VCVTW2PHZrm = 8749 + + VCVTW2PHZrmb = 8750 + + VCVTW2PHZrmbk = 8751 + + VCVTW2PHZrmbkz = 8752 + + VCVTW2PHZrmk = 8753 + + VCVTW2PHZrmkz = 8754 + + VCVTW2PHZrr = 8755 + + VCVTW2PHZrrb = 8756 + + VCVTW2PHZrrbk = 8757 + + VCVTW2PHZrrbkz = 8758 + + VCVTW2PHZrrk = 8759 + + VCVTW2PHZrrkz = 8760 + + VDBPSADBWZ128rmi = 8761 + + VDBPSADBWZ128rmik = 8762 + + VDBPSADBWZ128rmikz = 8763 + + VDBPSADBWZ128rri = 8764 + + VDBPSADBWZ128rrik = 8765 + + VDBPSADBWZ128rrikz = 8766 + + VDBPSADBWZ256rmi = 8767 + + VDBPSADBWZ256rmik = 8768 + + VDBPSADBWZ256rmikz = 8769 + + VDBPSADBWZ256rri = 8770 + + VDBPSADBWZ256rrik = 8771 + + VDBPSADBWZ256rrikz = 8772 + + VDBPSADBWZrmi = 8773 + + VDBPSADBWZrmik = 8774 + + VDBPSADBWZrmikz = 8775 + + VDBPSADBWZrri = 8776 + + VDBPSADBWZrrik = 8777 + + VDBPSADBWZrrikz = 8778 + + VDIVBF16Z128rm = 8779 + + VDIVBF16Z128rmb = 8780 + + VDIVBF16Z128rmbk = 8781 + + VDIVBF16Z128rmbkz = 8782 + + VDIVBF16Z128rmk = 8783 + + VDIVBF16Z128rmkz = 8784 + + VDIVBF16Z128rr = 8785 + + VDIVBF16Z128rrk = 8786 + + VDIVBF16Z128rrkz = 8787 + + VDIVBF16Z256rm = 8788 + + VDIVBF16Z256rmb = 8789 + + VDIVBF16Z256rmbk = 8790 + + VDIVBF16Z256rmbkz = 8791 + + VDIVBF16Z256rmk = 8792 + + VDIVBF16Z256rmkz = 8793 + + VDIVBF16Z256rr = 8794 + + VDIVBF16Z256rrk = 8795 + + VDIVBF16Z256rrkz = 8796 + + VDIVBF16Zrm = 8797 + + VDIVBF16Zrmb = 8798 + + VDIVBF16Zrmbk = 8799 + + VDIVBF16Zrmbkz = 8800 + + VDIVBF16Zrmk = 8801 + + VDIVBF16Zrmkz = 8802 + + VDIVBF16Zrr = 8803 + + VDIVBF16Zrrk = 8804 + + VDIVBF16Zrrkz = 8805 + + VDIVPDYrm = 8806 + + VDIVPDYrr = 8807 + + VDIVPDZ128rm = 8808 + + VDIVPDZ128rmb = 8809 + + VDIVPDZ128rmbk = 8810 + + VDIVPDZ128rmbkz = 8811 + + VDIVPDZ128rmk = 8812 + + VDIVPDZ128rmkz = 8813 + + VDIVPDZ128rr = 8814 + + VDIVPDZ128rrk = 8815 + + VDIVPDZ128rrkz = 8816 + + VDIVPDZ256rm = 8817 + + VDIVPDZ256rmb = 8818 + + VDIVPDZ256rmbk = 8819 + + VDIVPDZ256rmbkz = 8820 + + VDIVPDZ256rmk = 8821 + + VDIVPDZ256rmkz = 8822 + + VDIVPDZ256rr = 8823 + + VDIVPDZ256rrk = 8824 + + VDIVPDZ256rrkz = 8825 + + VDIVPDZrm = 8826 + + VDIVPDZrmb = 8827 + + VDIVPDZrmbk = 8828 + + VDIVPDZrmbkz = 8829 + + VDIVPDZrmk = 8830 + + VDIVPDZrmkz = 8831 + + VDIVPDZrr = 8832 + + VDIVPDZrrb = 8833 + + VDIVPDZrrbk = 8834 + + VDIVPDZrrbkz = 8835 + + VDIVPDZrrk = 8836 + + VDIVPDZrrkz = 8837 + + VDIVPDrm = 8838 + + VDIVPDrr = 8839 + + VDIVPHZ128rm = 8840 + + VDIVPHZ128rmb = 8841 + + VDIVPHZ128rmbk = 8842 + + VDIVPHZ128rmbkz = 8843 + + VDIVPHZ128rmk = 8844 + + VDIVPHZ128rmkz = 8845 + + VDIVPHZ128rr = 8846 + + VDIVPHZ128rrk = 8847 + + VDIVPHZ128rrkz = 8848 + + VDIVPHZ256rm = 8849 + + VDIVPHZ256rmb = 8850 + + VDIVPHZ256rmbk = 8851 + + VDIVPHZ256rmbkz = 8852 + + VDIVPHZ256rmk = 8853 + + VDIVPHZ256rmkz = 8854 + + VDIVPHZ256rr = 8855 + + VDIVPHZ256rrk = 8856 + + VDIVPHZ256rrkz = 8857 + + VDIVPHZrm = 8858 + + VDIVPHZrmb = 8859 + + VDIVPHZrmbk = 8860 + + VDIVPHZrmbkz = 8861 + + VDIVPHZrmk = 8862 + + VDIVPHZrmkz = 8863 + + VDIVPHZrr = 8864 + + VDIVPHZrrb = 8865 + + VDIVPHZrrbk = 8866 + + VDIVPHZrrbkz = 8867 + + VDIVPHZrrk = 8868 + + VDIVPHZrrkz = 8869 + + VDIVPSYrm = 8870 + + VDIVPSYrr = 8871 + + VDIVPSZ128rm = 8872 + + VDIVPSZ128rmb = 8873 + + VDIVPSZ128rmbk = 8874 + + VDIVPSZ128rmbkz = 8875 + + VDIVPSZ128rmk = 8876 + + VDIVPSZ128rmkz = 8877 + + VDIVPSZ128rr = 8878 + + VDIVPSZ128rrk = 8879 + + VDIVPSZ128rrkz = 8880 + + VDIVPSZ256rm = 8881 + + VDIVPSZ256rmb = 8882 + + VDIVPSZ256rmbk = 8883 + + VDIVPSZ256rmbkz = 8884 + + VDIVPSZ256rmk = 8885 + + VDIVPSZ256rmkz = 8886 + + VDIVPSZ256rr = 8887 + + VDIVPSZ256rrk = 8888 + + VDIVPSZ256rrkz = 8889 + + VDIVPSZrm = 8890 + + VDIVPSZrmb = 8891 + + VDIVPSZrmbk = 8892 + + VDIVPSZrmbkz = 8893 + + VDIVPSZrmk = 8894 + + VDIVPSZrmkz = 8895 + + VDIVPSZrr = 8896 + + VDIVPSZrrb = 8897 + + VDIVPSZrrbk = 8898 + + VDIVPSZrrbkz = 8899 + + VDIVPSZrrk = 8900 + + VDIVPSZrrkz = 8901 + + VDIVPSrm = 8902 + + VDIVPSrr = 8903 + + VDIVSDZrm = 8904 + + VDIVSDZrm_Int = 8905 + + VDIVSDZrmk_Int = 8906 + + VDIVSDZrmkz_Int = 8907 + + VDIVSDZrr = 8908 + + VDIVSDZrr_Int = 8909 + + VDIVSDZrrb_Int = 8910 + + VDIVSDZrrbk_Int = 8911 + + VDIVSDZrrbkz_Int = 8912 + + VDIVSDZrrk_Int = 8913 + + VDIVSDZrrkz_Int = 8914 + + VDIVSDrm = 8915 + + VDIVSDrm_Int = 8916 + + VDIVSDrr = 8917 + + VDIVSDrr_Int = 8918 + + VDIVSHZrm = 8919 + + VDIVSHZrm_Int = 8920 + + VDIVSHZrmk_Int = 8921 + + VDIVSHZrmkz_Int = 8922 + + VDIVSHZrr = 8923 + + VDIVSHZrr_Int = 8924 + + VDIVSHZrrb_Int = 8925 + + VDIVSHZrrbk_Int = 8926 + + VDIVSHZrrbkz_Int = 8927 + + VDIVSHZrrk_Int = 8928 + + VDIVSHZrrkz_Int = 8929 + + VDIVSSZrm = 8930 + + VDIVSSZrm_Int = 8931 + + VDIVSSZrmk_Int = 8932 + + VDIVSSZrmkz_Int = 8933 + + VDIVSSZrr = 8934 + + VDIVSSZrr_Int = 8935 + + VDIVSSZrrb_Int = 8936 + + VDIVSSZrrbk_Int = 8937 + + VDIVSSZrrbkz_Int = 8938 + + VDIVSSZrrk_Int = 8939 + + VDIVSSZrrkz_Int = 8940 + + VDIVSSrm = 8941 + + VDIVSSrm_Int = 8942 + + VDIVSSrr = 8943 + + VDIVSSrr_Int = 8944 + + VDPBF16PSZ128m = 8945 + + VDPBF16PSZ128mb = 8946 + + VDPBF16PSZ128mbk = 8947 + + VDPBF16PSZ128mbkz = 8948 + + VDPBF16PSZ128mk = 8949 + + VDPBF16PSZ128mkz = 8950 + + VDPBF16PSZ128r = 8951 + + VDPBF16PSZ128rk = 8952 + + VDPBF16PSZ128rkz = 8953 + + VDPBF16PSZ256m = 8954 + + VDPBF16PSZ256mb = 8955 + + VDPBF16PSZ256mbk = 8956 + + VDPBF16PSZ256mbkz = 8957 + + VDPBF16PSZ256mk = 8958 + + VDPBF16PSZ256mkz = 8959 + + VDPBF16PSZ256r = 8960 + + VDPBF16PSZ256rk = 8961 + + VDPBF16PSZ256rkz = 8962 + + VDPBF16PSZm = 8963 + + VDPBF16PSZmb = 8964 + + VDPBF16PSZmbk = 8965 + + VDPBF16PSZmbkz = 8966 + + VDPBF16PSZmk = 8967 + + VDPBF16PSZmkz = 8968 + + VDPBF16PSZr = 8969 + + VDPBF16PSZrk = 8970 + + VDPBF16PSZrkz = 8971 + + VDPPDrmi = 8972 + + VDPPDrri = 8973 + + VDPPHPSZ128m = 8974 + + VDPPHPSZ128mb = 8975 + + VDPPHPSZ128mbk = 8976 + + VDPPHPSZ128mbkz = 8977 + + VDPPHPSZ128mk = 8978 + + VDPPHPSZ128mkz = 8979 + + VDPPHPSZ128r = 8980 + + VDPPHPSZ128rk = 8981 + + VDPPHPSZ128rkz = 8982 + + VDPPHPSZ256m = 8983 + + VDPPHPSZ256mb = 8984 + + VDPPHPSZ256mbk = 8985 + + VDPPHPSZ256mbkz = 8986 + + VDPPHPSZ256mk = 8987 + + VDPPHPSZ256mkz = 8988 + + VDPPHPSZ256r = 8989 + + VDPPHPSZ256rk = 8990 + + VDPPHPSZ256rkz = 8991 + + VDPPHPSZm = 8992 + + VDPPHPSZmb = 8993 + + VDPPHPSZmbk = 8994 + + VDPPHPSZmbkz = 8995 + + VDPPHPSZmk = 8996 + + VDPPHPSZmkz = 8997 + + VDPPHPSZr = 8998 + + VDPPHPSZrk = 8999 + + VDPPHPSZrkz = 9000 + + VDPPSYrmi = 9001 + + VDPPSYrri = 9002 + + VDPPSrmi = 9003 + + VDPPSrri = 9004 + + VERRm = 9005 + + VERRr = 9006 + + VERWm = 9007 + + VERWr = 9008 + + VEXP2PDZm = 9009 + + VEXP2PDZmb = 9010 + + VEXP2PDZmbk = 9011 + + VEXP2PDZmbkz = 9012 + + VEXP2PDZmk = 9013 + + VEXP2PDZmkz = 9014 + + VEXP2PDZr = 9015 + + VEXP2PDZrb = 9016 + + VEXP2PDZrbk = 9017 + + VEXP2PDZrbkz = 9018 + + VEXP2PDZrk = 9019 + + VEXP2PDZrkz = 9020 + + VEXP2PSZm = 9021 + + VEXP2PSZmb = 9022 + + VEXP2PSZmbk = 9023 + + VEXP2PSZmbkz = 9024 + + VEXP2PSZmk = 9025 + + VEXP2PSZmkz = 9026 + + VEXP2PSZr = 9027 + + VEXP2PSZrb = 9028 + + VEXP2PSZrbk = 9029 + + VEXP2PSZrbkz = 9030 + + VEXP2PSZrk = 9031 + + VEXP2PSZrkz = 9032 + + VEXPANDPDZ128rm = 9033 + + VEXPANDPDZ128rmk = 9034 + + VEXPANDPDZ128rmkz = 9035 + + VEXPANDPDZ128rr = 9036 + + VEXPANDPDZ128rrk = 9037 + + VEXPANDPDZ128rrkz = 9038 + + VEXPANDPDZ256rm = 9039 + + VEXPANDPDZ256rmk = 9040 + + VEXPANDPDZ256rmkz = 9041 + + VEXPANDPDZ256rr = 9042 + + VEXPANDPDZ256rrk = 9043 + + VEXPANDPDZ256rrkz = 9044 + + VEXPANDPDZrm = 9045 + + VEXPANDPDZrmk = 9046 + + VEXPANDPDZrmkz = 9047 + + VEXPANDPDZrr = 9048 + + VEXPANDPDZrrk = 9049 + + VEXPANDPDZrrkz = 9050 + + VEXPANDPSZ128rm = 9051 + + VEXPANDPSZ128rmk = 9052 + + VEXPANDPSZ128rmkz = 9053 + + VEXPANDPSZ128rr = 9054 + + VEXPANDPSZ128rrk = 9055 + + VEXPANDPSZ128rrkz = 9056 + + VEXPANDPSZ256rm = 9057 + + VEXPANDPSZ256rmk = 9058 + + VEXPANDPSZ256rmkz = 9059 + + VEXPANDPSZ256rr = 9060 + + VEXPANDPSZ256rrk = 9061 + + VEXPANDPSZ256rrkz = 9062 + + VEXPANDPSZrm = 9063 + + VEXPANDPSZrmk = 9064 + + VEXPANDPSZrmkz = 9065 + + VEXPANDPSZrr = 9066 + + VEXPANDPSZrrk = 9067 + + VEXPANDPSZrrkz = 9068 + + VEXTRACTF128mri = 9069 + + VEXTRACTF128rri = 9070 + + VEXTRACTF32X4Z256mri = 9071 + + VEXTRACTF32X4Z256mrik = 9072 + + VEXTRACTF32X4Z256rri = 9073 + + VEXTRACTF32X4Z256rrik = 9074 + + VEXTRACTF32X4Z256rrikz = 9075 + + VEXTRACTF32X4Zmri = 9076 + + VEXTRACTF32X4Zmrik = 9077 + + VEXTRACTF32X4Zrri = 9078 + + VEXTRACTF32X4Zrrik = 9079 + + VEXTRACTF32X4Zrrikz = 9080 + + VEXTRACTF32X8Zmri = 9081 + + VEXTRACTF32X8Zmrik = 9082 + + VEXTRACTF32X8Zrri = 9083 + + VEXTRACTF32X8Zrrik = 9084 + + VEXTRACTF32X8Zrrikz = 9085 + + VEXTRACTF64X2Z256mri = 9086 + + VEXTRACTF64X2Z256mrik = 9087 + + VEXTRACTF64X2Z256rri = 9088 + + VEXTRACTF64X2Z256rrik = 9089 + + VEXTRACTF64X2Z256rrikz = 9090 + + VEXTRACTF64X2Zmri = 9091 + + VEXTRACTF64X2Zmrik = 9092 + + VEXTRACTF64X2Zrri = 9093 + + VEXTRACTF64X2Zrrik = 9094 + + VEXTRACTF64X2Zrrikz = 9095 + + VEXTRACTF64X4Zmri = 9096 + + VEXTRACTF64X4Zmrik = 9097 + + VEXTRACTF64X4Zrri = 9098 + + VEXTRACTF64X4Zrrik = 9099 + + VEXTRACTF64X4Zrrikz = 9100 + + VEXTRACTI128mri = 9101 + + VEXTRACTI128rri = 9102 + + VEXTRACTI32X4Z256mri = 9103 + + VEXTRACTI32X4Z256mrik = 9104 + + VEXTRACTI32X4Z256rri = 9105 + + VEXTRACTI32X4Z256rrik = 9106 + + VEXTRACTI32X4Z256rrikz = 9107 + + VEXTRACTI32X4Zmri = 9108 + + VEXTRACTI32X4Zmrik = 9109 + + VEXTRACTI32X4Zrri = 9110 + + VEXTRACTI32X4Zrrik = 9111 + + VEXTRACTI32X4Zrrikz = 9112 + + VEXTRACTI32X8Zmri = 9113 + + VEXTRACTI32X8Zmrik = 9114 + + VEXTRACTI32X8Zrri = 9115 + + VEXTRACTI32X8Zrrik = 9116 + + VEXTRACTI32X8Zrrikz = 9117 + + VEXTRACTI64X2Z256mri = 9118 + + VEXTRACTI64X2Z256mrik = 9119 + + VEXTRACTI64X2Z256rri = 9120 + + VEXTRACTI64X2Z256rrik = 9121 + + VEXTRACTI64X2Z256rrikz = 9122 + + VEXTRACTI64X2Zmri = 9123 + + VEXTRACTI64X2Zmrik = 9124 + + VEXTRACTI64X2Zrri = 9125 + + VEXTRACTI64X2Zrrik = 9126 + + VEXTRACTI64X2Zrrikz = 9127 + + VEXTRACTI64X4Zmri = 9128 + + VEXTRACTI64X4Zmrik = 9129 + + VEXTRACTI64X4Zrri = 9130 + + VEXTRACTI64X4Zrrik = 9131 + + VEXTRACTI64X4Zrrikz = 9132 + + VEXTRACTPSZmri = 9133 + + VEXTRACTPSZrri = 9134 + + VEXTRACTPSmri = 9135 + + VEXTRACTPSrri = 9136 + + VFCMADDCPHZ128m = 9137 + + VFCMADDCPHZ128mb = 9138 + + VFCMADDCPHZ128mbk = 9139 + + VFCMADDCPHZ128mbkz = 9140 + + VFCMADDCPHZ128mk = 9141 + + VFCMADDCPHZ128mkz = 9142 + + VFCMADDCPHZ128r = 9143 + + VFCMADDCPHZ128rk = 9144 + + VFCMADDCPHZ128rkz = 9145 + + VFCMADDCPHZ256m = 9146 + + VFCMADDCPHZ256mb = 9147 + + VFCMADDCPHZ256mbk = 9148 + + VFCMADDCPHZ256mbkz = 9149 + + VFCMADDCPHZ256mk = 9150 + + VFCMADDCPHZ256mkz = 9151 + + VFCMADDCPHZ256r = 9152 + + VFCMADDCPHZ256rk = 9153 + + VFCMADDCPHZ256rkz = 9154 + + VFCMADDCPHZm = 9155 + + VFCMADDCPHZmb = 9156 + + VFCMADDCPHZmbk = 9157 + + VFCMADDCPHZmbkz = 9158 + + VFCMADDCPHZmk = 9159 + + VFCMADDCPHZmkz = 9160 + + VFCMADDCPHZr = 9161 + + VFCMADDCPHZrb = 9162 + + VFCMADDCPHZrbk = 9163 + + VFCMADDCPHZrbkz = 9164 + + VFCMADDCPHZrk = 9165 + + VFCMADDCPHZrkz = 9166 + + VFCMADDCSHZm = 9167 + + VFCMADDCSHZmk = 9168 + + VFCMADDCSHZmkz = 9169 + + VFCMADDCSHZr = 9170 + + VFCMADDCSHZrb = 9171 + + VFCMADDCSHZrbk = 9172 + + VFCMADDCSHZrbkz = 9173 + + VFCMADDCSHZrk = 9174 + + VFCMADDCSHZrkz = 9175 + + VFCMULCPHZ128rm = 9176 + + VFCMULCPHZ128rmb = 9177 + + VFCMULCPHZ128rmbk = 9178 + + VFCMULCPHZ128rmbkz = 9179 + + VFCMULCPHZ128rmk = 9180 + + VFCMULCPHZ128rmkz = 9181 + + VFCMULCPHZ128rr = 9182 + + VFCMULCPHZ128rrk = 9183 + + VFCMULCPHZ128rrkz = 9184 + + VFCMULCPHZ256rm = 9185 + + VFCMULCPHZ256rmb = 9186 + + VFCMULCPHZ256rmbk = 9187 + + VFCMULCPHZ256rmbkz = 9188 + + VFCMULCPHZ256rmk = 9189 + + VFCMULCPHZ256rmkz = 9190 + + VFCMULCPHZ256rr = 9191 + + VFCMULCPHZ256rrk = 9192 + + VFCMULCPHZ256rrkz = 9193 + + VFCMULCPHZrm = 9194 + + VFCMULCPHZrmb = 9195 + + VFCMULCPHZrmbk = 9196 + + VFCMULCPHZrmbkz = 9197 + + VFCMULCPHZrmk = 9198 + + VFCMULCPHZrmkz = 9199 + + VFCMULCPHZrr = 9200 + + VFCMULCPHZrrb = 9201 + + VFCMULCPHZrrbk = 9202 + + VFCMULCPHZrrbkz = 9203 + + VFCMULCPHZrrk = 9204 + + VFCMULCPHZrrkz = 9205 + + VFCMULCSHZrm = 9206 + + VFCMULCSHZrmk = 9207 + + VFCMULCSHZrmkz = 9208 + + VFCMULCSHZrr = 9209 + + VFCMULCSHZrrb = 9210 + + VFCMULCSHZrrbk = 9211 + + VFCMULCSHZrrbkz = 9212 + + VFCMULCSHZrrk = 9213 + + VFCMULCSHZrrkz = 9214 + + VFIXUPIMMPDZ128rmbi = 9215 + + VFIXUPIMMPDZ128rmbik = 9216 + + VFIXUPIMMPDZ128rmbikz = 9217 + + VFIXUPIMMPDZ128rmi = 9218 + + VFIXUPIMMPDZ128rmik = 9219 + + VFIXUPIMMPDZ128rmikz = 9220 + + VFIXUPIMMPDZ128rri = 9221 + + VFIXUPIMMPDZ128rrik = 9222 + + VFIXUPIMMPDZ128rrikz = 9223 + + VFIXUPIMMPDZ256rmbi = 9224 + + VFIXUPIMMPDZ256rmbik = 9225 + + VFIXUPIMMPDZ256rmbikz = 9226 + + VFIXUPIMMPDZ256rmi = 9227 + + VFIXUPIMMPDZ256rmik = 9228 + + VFIXUPIMMPDZ256rmikz = 9229 + + VFIXUPIMMPDZ256rri = 9230 + + VFIXUPIMMPDZ256rrik = 9231 + + VFIXUPIMMPDZ256rrikz = 9232 + + VFIXUPIMMPDZrmbi = 9233 + + VFIXUPIMMPDZrmbik = 9234 + + VFIXUPIMMPDZrmbikz = 9235 + + VFIXUPIMMPDZrmi = 9236 + + VFIXUPIMMPDZrmik = 9237 + + VFIXUPIMMPDZrmikz = 9238 + + VFIXUPIMMPDZrri = 9239 + + VFIXUPIMMPDZrrib = 9240 + + VFIXUPIMMPDZrribk = 9241 + + VFIXUPIMMPDZrribkz = 9242 + + VFIXUPIMMPDZrrik = 9243 + + VFIXUPIMMPDZrrikz = 9244 + + VFIXUPIMMPSZ128rmbi = 9245 + + VFIXUPIMMPSZ128rmbik = 9246 + + VFIXUPIMMPSZ128rmbikz = 9247 + + VFIXUPIMMPSZ128rmi = 9248 + + VFIXUPIMMPSZ128rmik = 9249 + + VFIXUPIMMPSZ128rmikz = 9250 + + VFIXUPIMMPSZ128rri = 9251 + + VFIXUPIMMPSZ128rrik = 9252 + + VFIXUPIMMPSZ128rrikz = 9253 + + VFIXUPIMMPSZ256rmbi = 9254 + + VFIXUPIMMPSZ256rmbik = 9255 + + VFIXUPIMMPSZ256rmbikz = 9256 + + VFIXUPIMMPSZ256rmi = 9257 + + VFIXUPIMMPSZ256rmik = 9258 + + VFIXUPIMMPSZ256rmikz = 9259 + + VFIXUPIMMPSZ256rri = 9260 + + VFIXUPIMMPSZ256rrik = 9261 + + VFIXUPIMMPSZ256rrikz = 9262 + + VFIXUPIMMPSZrmbi = 9263 + + VFIXUPIMMPSZrmbik = 9264 + + VFIXUPIMMPSZrmbikz = 9265 + + VFIXUPIMMPSZrmi = 9266 + + VFIXUPIMMPSZrmik = 9267 + + VFIXUPIMMPSZrmikz = 9268 + + VFIXUPIMMPSZrri = 9269 + + VFIXUPIMMPSZrrib = 9270 + + VFIXUPIMMPSZrribk = 9271 + + VFIXUPIMMPSZrribkz = 9272 + + VFIXUPIMMPSZrrik = 9273 + + VFIXUPIMMPSZrrikz = 9274 + + VFIXUPIMMSDZrmi = 9275 + + VFIXUPIMMSDZrmik = 9276 + + VFIXUPIMMSDZrmikz = 9277 + + VFIXUPIMMSDZrri = 9278 + + VFIXUPIMMSDZrrib = 9279 + + VFIXUPIMMSDZrribk = 9280 + + VFIXUPIMMSDZrribkz = 9281 + + VFIXUPIMMSDZrrik = 9282 + + VFIXUPIMMSDZrrikz = 9283 + + VFIXUPIMMSSZrmi = 9284 + + VFIXUPIMMSSZrmik = 9285 + + VFIXUPIMMSSZrmikz = 9286 + + VFIXUPIMMSSZrri = 9287 + + VFIXUPIMMSSZrrib = 9288 + + VFIXUPIMMSSZrribk = 9289 + + VFIXUPIMMSSZrribkz = 9290 + + VFIXUPIMMSSZrrik = 9291 + + VFIXUPIMMSSZrrikz = 9292 + + VFMADD132BF16Z128m = 9293 + + VFMADD132BF16Z128mb = 9294 + + VFMADD132BF16Z128mbk = 9295 + + VFMADD132BF16Z128mbkz = 9296 + + VFMADD132BF16Z128mk = 9297 + + VFMADD132BF16Z128mkz = 9298 + + VFMADD132BF16Z128r = 9299 + + VFMADD132BF16Z128rk = 9300 + + VFMADD132BF16Z128rkz = 9301 + + VFMADD132BF16Z256m = 9302 + + VFMADD132BF16Z256mb = 9303 + + VFMADD132BF16Z256mbk = 9304 + + VFMADD132BF16Z256mbkz = 9305 + + VFMADD132BF16Z256mk = 9306 + + VFMADD132BF16Z256mkz = 9307 + + VFMADD132BF16Z256r = 9308 + + VFMADD132BF16Z256rk = 9309 + + VFMADD132BF16Z256rkz = 9310 + + VFMADD132BF16Zm = 9311 + + VFMADD132BF16Zmb = 9312 + + VFMADD132BF16Zmbk = 9313 + + VFMADD132BF16Zmbkz = 9314 + + VFMADD132BF16Zmk = 9315 + + VFMADD132BF16Zmkz = 9316 + + VFMADD132BF16Zr = 9317 + + VFMADD132BF16Zrk = 9318 + + VFMADD132BF16Zrkz = 9319 + + VFMADD132PDYm = 9320 + + VFMADD132PDYr = 9321 + + VFMADD132PDZ128m = 9322 + + VFMADD132PDZ128mb = 9323 + + VFMADD132PDZ128mbk = 9324 + + VFMADD132PDZ128mbkz = 9325 + + VFMADD132PDZ128mk = 9326 + + VFMADD132PDZ128mkz = 9327 + + VFMADD132PDZ128r = 9328 + + VFMADD132PDZ128rk = 9329 + + VFMADD132PDZ128rkz = 9330 + + VFMADD132PDZ256m = 9331 + + VFMADD132PDZ256mb = 9332 + + VFMADD132PDZ256mbk = 9333 + + VFMADD132PDZ256mbkz = 9334 + + VFMADD132PDZ256mk = 9335 + + VFMADD132PDZ256mkz = 9336 + + VFMADD132PDZ256r = 9337 + + VFMADD132PDZ256rk = 9338 + + VFMADD132PDZ256rkz = 9339 + + VFMADD132PDZm = 9340 + + VFMADD132PDZmb = 9341 + + VFMADD132PDZmbk = 9342 + + VFMADD132PDZmbkz = 9343 + + VFMADD132PDZmk = 9344 + + VFMADD132PDZmkz = 9345 + + VFMADD132PDZr = 9346 + + VFMADD132PDZrb = 9347 + + VFMADD132PDZrbk = 9348 + + VFMADD132PDZrbkz = 9349 + + VFMADD132PDZrk = 9350 + + VFMADD132PDZrkz = 9351 + + VFMADD132PDm = 9352 + + VFMADD132PDr = 9353 + + VFMADD132PHZ128m = 9354 + + VFMADD132PHZ128mb = 9355 + + VFMADD132PHZ128mbk = 9356 + + VFMADD132PHZ128mbkz = 9357 + + VFMADD132PHZ128mk = 9358 + + VFMADD132PHZ128mkz = 9359 + + VFMADD132PHZ128r = 9360 + + VFMADD132PHZ128rk = 9361 + + VFMADD132PHZ128rkz = 9362 + + VFMADD132PHZ256m = 9363 + + VFMADD132PHZ256mb = 9364 + + VFMADD132PHZ256mbk = 9365 + + VFMADD132PHZ256mbkz = 9366 + + VFMADD132PHZ256mk = 9367 + + VFMADD132PHZ256mkz = 9368 + + VFMADD132PHZ256r = 9369 + + VFMADD132PHZ256rk = 9370 + + VFMADD132PHZ256rkz = 9371 + + VFMADD132PHZm = 9372 + + VFMADD132PHZmb = 9373 + + VFMADD132PHZmbk = 9374 + + VFMADD132PHZmbkz = 9375 + + VFMADD132PHZmk = 9376 + + VFMADD132PHZmkz = 9377 + + VFMADD132PHZr = 9378 + + VFMADD132PHZrb = 9379 + + VFMADD132PHZrbk = 9380 + + VFMADD132PHZrbkz = 9381 + + VFMADD132PHZrk = 9382 + + VFMADD132PHZrkz = 9383 + + VFMADD132PSYm = 9384 + + VFMADD132PSYr = 9385 + + VFMADD132PSZ128m = 9386 + + VFMADD132PSZ128mb = 9387 + + VFMADD132PSZ128mbk = 9388 + + VFMADD132PSZ128mbkz = 9389 + + VFMADD132PSZ128mk = 9390 + + VFMADD132PSZ128mkz = 9391 + + VFMADD132PSZ128r = 9392 + + VFMADD132PSZ128rk = 9393 + + VFMADD132PSZ128rkz = 9394 + + VFMADD132PSZ256m = 9395 + + VFMADD132PSZ256mb = 9396 + + VFMADD132PSZ256mbk = 9397 + + VFMADD132PSZ256mbkz = 9398 + + VFMADD132PSZ256mk = 9399 + + VFMADD132PSZ256mkz = 9400 + + VFMADD132PSZ256r = 9401 + + VFMADD132PSZ256rk = 9402 + + VFMADD132PSZ256rkz = 9403 + + VFMADD132PSZm = 9404 + + VFMADD132PSZmb = 9405 + + VFMADD132PSZmbk = 9406 + + VFMADD132PSZmbkz = 9407 + + VFMADD132PSZmk = 9408 + + VFMADD132PSZmkz = 9409 + + VFMADD132PSZr = 9410 + + VFMADD132PSZrb = 9411 + + VFMADD132PSZrbk = 9412 + + VFMADD132PSZrbkz = 9413 + + VFMADD132PSZrk = 9414 + + VFMADD132PSZrkz = 9415 + + VFMADD132PSm = 9416 + + VFMADD132PSr = 9417 + + VFMADD132SDZm = 9418 + + VFMADD132SDZm_Int = 9419 + + VFMADD132SDZmk_Int = 9420 + + VFMADD132SDZmkz_Int = 9421 + + VFMADD132SDZr = 9422 + + VFMADD132SDZr_Int = 9423 + + VFMADD132SDZrb = 9424 + + VFMADD132SDZrb_Int = 9425 + + VFMADD132SDZrbk_Int = 9426 + + VFMADD132SDZrbkz_Int = 9427 + + VFMADD132SDZrk_Int = 9428 + + VFMADD132SDZrkz_Int = 9429 + + VFMADD132SDm = 9430 + + VFMADD132SDm_Int = 9431 + + VFMADD132SDr = 9432 + + VFMADD132SDr_Int = 9433 + + VFMADD132SHZm = 9434 + + VFMADD132SHZm_Int = 9435 + + VFMADD132SHZmk_Int = 9436 + + VFMADD132SHZmkz_Int = 9437 + + VFMADD132SHZr = 9438 + + VFMADD132SHZr_Int = 9439 + + VFMADD132SHZrb = 9440 + + VFMADD132SHZrb_Int = 9441 + + VFMADD132SHZrbk_Int = 9442 + + VFMADD132SHZrbkz_Int = 9443 + + VFMADD132SHZrk_Int = 9444 + + VFMADD132SHZrkz_Int = 9445 + + VFMADD132SSZm = 9446 + + VFMADD132SSZm_Int = 9447 + + VFMADD132SSZmk_Int = 9448 + + VFMADD132SSZmkz_Int = 9449 + + VFMADD132SSZr = 9450 + + VFMADD132SSZr_Int = 9451 + + VFMADD132SSZrb = 9452 + + VFMADD132SSZrb_Int = 9453 + + VFMADD132SSZrbk_Int = 9454 + + VFMADD132SSZrbkz_Int = 9455 + + VFMADD132SSZrk_Int = 9456 + + VFMADD132SSZrkz_Int = 9457 + + VFMADD132SSm = 9458 + + VFMADD132SSm_Int = 9459 + + VFMADD132SSr = 9460 + + VFMADD132SSr_Int = 9461 + + VFMADD213BF16Z128m = 9462 + + VFMADD213BF16Z128mb = 9463 + + VFMADD213BF16Z128mbk = 9464 + + VFMADD213BF16Z128mbkz = 9465 + + VFMADD213BF16Z128mk = 9466 + + VFMADD213BF16Z128mkz = 9467 + + VFMADD213BF16Z128r = 9468 + + VFMADD213BF16Z128rk = 9469 + + VFMADD213BF16Z128rkz = 9470 + + VFMADD213BF16Z256m = 9471 + + VFMADD213BF16Z256mb = 9472 + + VFMADD213BF16Z256mbk = 9473 + + VFMADD213BF16Z256mbkz = 9474 + + VFMADD213BF16Z256mk = 9475 + + VFMADD213BF16Z256mkz = 9476 + + VFMADD213BF16Z256r = 9477 + + VFMADD213BF16Z256rk = 9478 + + VFMADD213BF16Z256rkz = 9479 + + VFMADD213BF16Zm = 9480 + + VFMADD213BF16Zmb = 9481 + + VFMADD213BF16Zmbk = 9482 + + VFMADD213BF16Zmbkz = 9483 + + VFMADD213BF16Zmk = 9484 + + VFMADD213BF16Zmkz = 9485 + + VFMADD213BF16Zr = 9486 + + VFMADD213BF16Zrk = 9487 + + VFMADD213BF16Zrkz = 9488 + + VFMADD213PDYm = 9489 + + VFMADD213PDYr = 9490 + + VFMADD213PDZ128m = 9491 + + VFMADD213PDZ128mb = 9492 + + VFMADD213PDZ128mbk = 9493 + + VFMADD213PDZ128mbkz = 9494 + + VFMADD213PDZ128mk = 9495 + + VFMADD213PDZ128mkz = 9496 + + VFMADD213PDZ128r = 9497 + + VFMADD213PDZ128rk = 9498 + + VFMADD213PDZ128rkz = 9499 + + VFMADD213PDZ256m = 9500 + + VFMADD213PDZ256mb = 9501 + + VFMADD213PDZ256mbk = 9502 + + VFMADD213PDZ256mbkz = 9503 + + VFMADD213PDZ256mk = 9504 + + VFMADD213PDZ256mkz = 9505 + + VFMADD213PDZ256r = 9506 + + VFMADD213PDZ256rk = 9507 + + VFMADD213PDZ256rkz = 9508 + + VFMADD213PDZm = 9509 + + VFMADD213PDZmb = 9510 + + VFMADD213PDZmbk = 9511 + + VFMADD213PDZmbkz = 9512 + + VFMADD213PDZmk = 9513 + + VFMADD213PDZmkz = 9514 + + VFMADD213PDZr = 9515 + + VFMADD213PDZrb = 9516 + + VFMADD213PDZrbk = 9517 + + VFMADD213PDZrbkz = 9518 + + VFMADD213PDZrk = 9519 + + VFMADD213PDZrkz = 9520 + + VFMADD213PDm = 9521 + + VFMADD213PDr = 9522 + + VFMADD213PHZ128m = 9523 + + VFMADD213PHZ128mb = 9524 + + VFMADD213PHZ128mbk = 9525 + + VFMADD213PHZ128mbkz = 9526 + + VFMADD213PHZ128mk = 9527 + + VFMADD213PHZ128mkz = 9528 + + VFMADD213PHZ128r = 9529 + + VFMADD213PHZ128rk = 9530 + + VFMADD213PHZ128rkz = 9531 + + VFMADD213PHZ256m = 9532 + + VFMADD213PHZ256mb = 9533 + + VFMADD213PHZ256mbk = 9534 + + VFMADD213PHZ256mbkz = 9535 + + VFMADD213PHZ256mk = 9536 + + VFMADD213PHZ256mkz = 9537 + + VFMADD213PHZ256r = 9538 + + VFMADD213PHZ256rk = 9539 + + VFMADD213PHZ256rkz = 9540 + + VFMADD213PHZm = 9541 + + VFMADD213PHZmb = 9542 + + VFMADD213PHZmbk = 9543 + + VFMADD213PHZmbkz = 9544 + + VFMADD213PHZmk = 9545 + + VFMADD213PHZmkz = 9546 + + VFMADD213PHZr = 9547 + + VFMADD213PHZrb = 9548 + + VFMADD213PHZrbk = 9549 + + VFMADD213PHZrbkz = 9550 + + VFMADD213PHZrk = 9551 + + VFMADD213PHZrkz = 9552 + + VFMADD213PSYm = 9553 + + VFMADD213PSYr = 9554 + + VFMADD213PSZ128m = 9555 + + VFMADD213PSZ128mb = 9556 + + VFMADD213PSZ128mbk = 9557 + + VFMADD213PSZ128mbkz = 9558 + + VFMADD213PSZ128mk = 9559 + + VFMADD213PSZ128mkz = 9560 + + VFMADD213PSZ128r = 9561 + + VFMADD213PSZ128rk = 9562 + + VFMADD213PSZ128rkz = 9563 + + VFMADD213PSZ256m = 9564 + + VFMADD213PSZ256mb = 9565 + + VFMADD213PSZ256mbk = 9566 + + VFMADD213PSZ256mbkz = 9567 + + VFMADD213PSZ256mk = 9568 + + VFMADD213PSZ256mkz = 9569 + + VFMADD213PSZ256r = 9570 + + VFMADD213PSZ256rk = 9571 + + VFMADD213PSZ256rkz = 9572 + + VFMADD213PSZm = 9573 + + VFMADD213PSZmb = 9574 + + VFMADD213PSZmbk = 9575 + + VFMADD213PSZmbkz = 9576 + + VFMADD213PSZmk = 9577 + + VFMADD213PSZmkz = 9578 + + VFMADD213PSZr = 9579 + + VFMADD213PSZrb = 9580 + + VFMADD213PSZrbk = 9581 + + VFMADD213PSZrbkz = 9582 + + VFMADD213PSZrk = 9583 + + VFMADD213PSZrkz = 9584 + + VFMADD213PSm = 9585 + + VFMADD213PSr = 9586 + + VFMADD213SDZm = 9587 + + VFMADD213SDZm_Int = 9588 + + VFMADD213SDZmk_Int = 9589 + + VFMADD213SDZmkz_Int = 9590 + + VFMADD213SDZr = 9591 + + VFMADD213SDZr_Int = 9592 + + VFMADD213SDZrb = 9593 + + VFMADD213SDZrb_Int = 9594 + + VFMADD213SDZrbk_Int = 9595 + + VFMADD213SDZrbkz_Int = 9596 + + VFMADD213SDZrk_Int = 9597 + + VFMADD213SDZrkz_Int = 9598 + + VFMADD213SDm = 9599 + + VFMADD213SDm_Int = 9600 + + VFMADD213SDr = 9601 + + VFMADD213SDr_Int = 9602 + + VFMADD213SHZm = 9603 + + VFMADD213SHZm_Int = 9604 + + VFMADD213SHZmk_Int = 9605 + + VFMADD213SHZmkz_Int = 9606 + + VFMADD213SHZr = 9607 + + VFMADD213SHZr_Int = 9608 + + VFMADD213SHZrb = 9609 + + VFMADD213SHZrb_Int = 9610 + + VFMADD213SHZrbk_Int = 9611 + + VFMADD213SHZrbkz_Int = 9612 + + VFMADD213SHZrk_Int = 9613 + + VFMADD213SHZrkz_Int = 9614 + + VFMADD213SSZm = 9615 + + VFMADD213SSZm_Int = 9616 + + VFMADD213SSZmk_Int = 9617 + + VFMADD213SSZmkz_Int = 9618 + + VFMADD213SSZr = 9619 + + VFMADD213SSZr_Int = 9620 + + VFMADD213SSZrb = 9621 + + VFMADD213SSZrb_Int = 9622 + + VFMADD213SSZrbk_Int = 9623 + + VFMADD213SSZrbkz_Int = 9624 + + VFMADD213SSZrk_Int = 9625 + + VFMADD213SSZrkz_Int = 9626 + + VFMADD213SSm = 9627 + + VFMADD213SSm_Int = 9628 + + VFMADD213SSr = 9629 + + VFMADD213SSr_Int = 9630 + + VFMADD231BF16Z128m = 9631 + + VFMADD231BF16Z128mb = 9632 + + VFMADD231BF16Z128mbk = 9633 + + VFMADD231BF16Z128mbkz = 9634 + + VFMADD231BF16Z128mk = 9635 + + VFMADD231BF16Z128mkz = 9636 + + VFMADD231BF16Z128r = 9637 + + VFMADD231BF16Z128rk = 9638 + + VFMADD231BF16Z128rkz = 9639 + + VFMADD231BF16Z256m = 9640 + + VFMADD231BF16Z256mb = 9641 + + VFMADD231BF16Z256mbk = 9642 + + VFMADD231BF16Z256mbkz = 9643 + + VFMADD231BF16Z256mk = 9644 + + VFMADD231BF16Z256mkz = 9645 + + VFMADD231BF16Z256r = 9646 + + VFMADD231BF16Z256rk = 9647 + + VFMADD231BF16Z256rkz = 9648 + + VFMADD231BF16Zm = 9649 + + VFMADD231BF16Zmb = 9650 + + VFMADD231BF16Zmbk = 9651 + + VFMADD231BF16Zmbkz = 9652 + + VFMADD231BF16Zmk = 9653 + + VFMADD231BF16Zmkz = 9654 + + VFMADD231BF16Zr = 9655 + + VFMADD231BF16Zrk = 9656 + + VFMADD231BF16Zrkz = 9657 + + VFMADD231PDYm = 9658 + + VFMADD231PDYr = 9659 + + VFMADD231PDZ128m = 9660 + + VFMADD231PDZ128mb = 9661 + + VFMADD231PDZ128mbk = 9662 + + VFMADD231PDZ128mbkz = 9663 + + VFMADD231PDZ128mk = 9664 + + VFMADD231PDZ128mkz = 9665 + + VFMADD231PDZ128r = 9666 + + VFMADD231PDZ128rk = 9667 + + VFMADD231PDZ128rkz = 9668 + + VFMADD231PDZ256m = 9669 + + VFMADD231PDZ256mb = 9670 + + VFMADD231PDZ256mbk = 9671 + + VFMADD231PDZ256mbkz = 9672 + + VFMADD231PDZ256mk = 9673 + + VFMADD231PDZ256mkz = 9674 + + VFMADD231PDZ256r = 9675 + + VFMADD231PDZ256rk = 9676 + + VFMADD231PDZ256rkz = 9677 + + VFMADD231PDZm = 9678 + + VFMADD231PDZmb = 9679 + + VFMADD231PDZmbk = 9680 + + VFMADD231PDZmbkz = 9681 + + VFMADD231PDZmk = 9682 + + VFMADD231PDZmkz = 9683 + + VFMADD231PDZr = 9684 + + VFMADD231PDZrb = 9685 + + VFMADD231PDZrbk = 9686 + + VFMADD231PDZrbkz = 9687 + + VFMADD231PDZrk = 9688 + + VFMADD231PDZrkz = 9689 + + VFMADD231PDm = 9690 + + VFMADD231PDr = 9691 + + VFMADD231PHZ128m = 9692 + + VFMADD231PHZ128mb = 9693 + + VFMADD231PHZ128mbk = 9694 + + VFMADD231PHZ128mbkz = 9695 + + VFMADD231PHZ128mk = 9696 + + VFMADD231PHZ128mkz = 9697 + + VFMADD231PHZ128r = 9698 + + VFMADD231PHZ128rk = 9699 + + VFMADD231PHZ128rkz = 9700 + + VFMADD231PHZ256m = 9701 + + VFMADD231PHZ256mb = 9702 + + VFMADD231PHZ256mbk = 9703 + + VFMADD231PHZ256mbkz = 9704 + + VFMADD231PHZ256mk = 9705 + + VFMADD231PHZ256mkz = 9706 + + VFMADD231PHZ256r = 9707 + + VFMADD231PHZ256rk = 9708 + + VFMADD231PHZ256rkz = 9709 + + VFMADD231PHZm = 9710 + + VFMADD231PHZmb = 9711 + + VFMADD231PHZmbk = 9712 + + VFMADD231PHZmbkz = 9713 + + VFMADD231PHZmk = 9714 + + VFMADD231PHZmkz = 9715 + + VFMADD231PHZr = 9716 + + VFMADD231PHZrb = 9717 + + VFMADD231PHZrbk = 9718 + + VFMADD231PHZrbkz = 9719 + + VFMADD231PHZrk = 9720 + + VFMADD231PHZrkz = 9721 + + VFMADD231PSYm = 9722 + + VFMADD231PSYr = 9723 + + VFMADD231PSZ128m = 9724 + + VFMADD231PSZ128mb = 9725 + + VFMADD231PSZ128mbk = 9726 + + VFMADD231PSZ128mbkz = 9727 + + VFMADD231PSZ128mk = 9728 + + VFMADD231PSZ128mkz = 9729 + + VFMADD231PSZ128r = 9730 + + VFMADD231PSZ128rk = 9731 + + VFMADD231PSZ128rkz = 9732 + + VFMADD231PSZ256m = 9733 + + VFMADD231PSZ256mb = 9734 + + VFMADD231PSZ256mbk = 9735 + + VFMADD231PSZ256mbkz = 9736 + + VFMADD231PSZ256mk = 9737 + + VFMADD231PSZ256mkz = 9738 + + VFMADD231PSZ256r = 9739 + + VFMADD231PSZ256rk = 9740 + + VFMADD231PSZ256rkz = 9741 + + VFMADD231PSZm = 9742 + + VFMADD231PSZmb = 9743 + + VFMADD231PSZmbk = 9744 + + VFMADD231PSZmbkz = 9745 + + VFMADD231PSZmk = 9746 + + VFMADD231PSZmkz = 9747 + + VFMADD231PSZr = 9748 + + VFMADD231PSZrb = 9749 + + VFMADD231PSZrbk = 9750 + + VFMADD231PSZrbkz = 9751 + + VFMADD231PSZrk = 9752 + + VFMADD231PSZrkz = 9753 + + VFMADD231PSm = 9754 + + VFMADD231PSr = 9755 + + VFMADD231SDZm = 9756 + + VFMADD231SDZm_Int = 9757 + + VFMADD231SDZmk_Int = 9758 + + VFMADD231SDZmkz_Int = 9759 + + VFMADD231SDZr = 9760 + + VFMADD231SDZr_Int = 9761 + + VFMADD231SDZrb = 9762 + + VFMADD231SDZrb_Int = 9763 + + VFMADD231SDZrbk_Int = 9764 + + VFMADD231SDZrbkz_Int = 9765 + + VFMADD231SDZrk_Int = 9766 + + VFMADD231SDZrkz_Int = 9767 + + VFMADD231SDm = 9768 + + VFMADD231SDm_Int = 9769 + + VFMADD231SDr = 9770 + + VFMADD231SDr_Int = 9771 + + VFMADD231SHZm = 9772 + + VFMADD231SHZm_Int = 9773 + + VFMADD231SHZmk_Int = 9774 + + VFMADD231SHZmkz_Int = 9775 + + VFMADD231SHZr = 9776 + + VFMADD231SHZr_Int = 9777 + + VFMADD231SHZrb = 9778 + + VFMADD231SHZrb_Int = 9779 + + VFMADD231SHZrbk_Int = 9780 + + VFMADD231SHZrbkz_Int = 9781 + + VFMADD231SHZrk_Int = 9782 + + VFMADD231SHZrkz_Int = 9783 + + VFMADD231SSZm = 9784 + + VFMADD231SSZm_Int = 9785 + + VFMADD231SSZmk_Int = 9786 + + VFMADD231SSZmkz_Int = 9787 + + VFMADD231SSZr = 9788 + + VFMADD231SSZr_Int = 9789 + + VFMADD231SSZrb = 9790 + + VFMADD231SSZrb_Int = 9791 + + VFMADD231SSZrbk_Int = 9792 + + VFMADD231SSZrbkz_Int = 9793 + + VFMADD231SSZrk_Int = 9794 + + VFMADD231SSZrkz_Int = 9795 + + VFMADD231SSm = 9796 + + VFMADD231SSm_Int = 9797 + + VFMADD231SSr = 9798 + + VFMADD231SSr_Int = 9799 + + VFMADDCPHZ128m = 9800 + + VFMADDCPHZ128mb = 9801 + + VFMADDCPHZ128mbk = 9802 + + VFMADDCPHZ128mbkz = 9803 + + VFMADDCPHZ128mk = 9804 + + VFMADDCPHZ128mkz = 9805 + + VFMADDCPHZ128r = 9806 + + VFMADDCPHZ128rk = 9807 + + VFMADDCPHZ128rkz = 9808 + + VFMADDCPHZ256m = 9809 + + VFMADDCPHZ256mb = 9810 + + VFMADDCPHZ256mbk = 9811 + + VFMADDCPHZ256mbkz = 9812 + + VFMADDCPHZ256mk = 9813 + + VFMADDCPHZ256mkz = 9814 + + VFMADDCPHZ256r = 9815 + + VFMADDCPHZ256rk = 9816 + + VFMADDCPHZ256rkz = 9817 + + VFMADDCPHZm = 9818 + + VFMADDCPHZmb = 9819 + + VFMADDCPHZmbk = 9820 + + VFMADDCPHZmbkz = 9821 + + VFMADDCPHZmk = 9822 + + VFMADDCPHZmkz = 9823 + + VFMADDCPHZr = 9824 + + VFMADDCPHZrb = 9825 + + VFMADDCPHZrbk = 9826 + + VFMADDCPHZrbkz = 9827 + + VFMADDCPHZrk = 9828 + + VFMADDCPHZrkz = 9829 + + VFMADDCSHZm = 9830 + + VFMADDCSHZmk = 9831 + + VFMADDCSHZmkz = 9832 + + VFMADDCSHZr = 9833 + + VFMADDCSHZrb = 9834 + + VFMADDCSHZrbk = 9835 + + VFMADDCSHZrbkz = 9836 + + VFMADDCSHZrk = 9837 + + VFMADDCSHZrkz = 9838 + + VFMADDPD4Ymr = 9839 + + VFMADDPD4Yrm = 9840 + + VFMADDPD4Yrr = 9841 + + VFMADDPD4Yrr_REV = 9842 + + VFMADDPD4mr = 9843 + + VFMADDPD4rm = 9844 + + VFMADDPD4rr = 9845 + + VFMADDPD4rr_REV = 9846 + + VFMADDPS4Ymr = 9847 + + VFMADDPS4Yrm = 9848 + + VFMADDPS4Yrr = 9849 + + VFMADDPS4Yrr_REV = 9850 + + VFMADDPS4mr = 9851 + + VFMADDPS4rm = 9852 + + VFMADDPS4rr = 9853 + + VFMADDPS4rr_REV = 9854 + + VFMADDSD4mr = 9855 + + VFMADDSD4mr_Int = 9856 + + VFMADDSD4rm = 9857 + + VFMADDSD4rm_Int = 9858 + + VFMADDSD4rr = 9859 + + VFMADDSD4rr_Int = 9860 + + VFMADDSD4rr_Int_REV = 9861 + + VFMADDSD4rr_REV = 9862 + + VFMADDSS4mr = 9863 + + VFMADDSS4mr_Int = 9864 + + VFMADDSS4rm = 9865 + + VFMADDSS4rm_Int = 9866 + + VFMADDSS4rr = 9867 + + VFMADDSS4rr_Int = 9868 + + VFMADDSS4rr_Int_REV = 9869 + + VFMADDSS4rr_REV = 9870 + + VFMADDSUB132PDYm = 9871 + + VFMADDSUB132PDYr = 9872 + + VFMADDSUB132PDZ128m = 9873 + + VFMADDSUB132PDZ128mb = 9874 + + VFMADDSUB132PDZ128mbk = 9875 + + VFMADDSUB132PDZ128mbkz = 9876 + + VFMADDSUB132PDZ128mk = 9877 + + VFMADDSUB132PDZ128mkz = 9878 + + VFMADDSUB132PDZ128r = 9879 + + VFMADDSUB132PDZ128rk = 9880 + + VFMADDSUB132PDZ128rkz = 9881 + + VFMADDSUB132PDZ256m = 9882 + + VFMADDSUB132PDZ256mb = 9883 + + VFMADDSUB132PDZ256mbk = 9884 + + VFMADDSUB132PDZ256mbkz = 9885 + + VFMADDSUB132PDZ256mk = 9886 + + VFMADDSUB132PDZ256mkz = 9887 + + VFMADDSUB132PDZ256r = 9888 + + VFMADDSUB132PDZ256rk = 9889 + + VFMADDSUB132PDZ256rkz = 9890 + + VFMADDSUB132PDZm = 9891 + + VFMADDSUB132PDZmb = 9892 + + VFMADDSUB132PDZmbk = 9893 + + VFMADDSUB132PDZmbkz = 9894 + + VFMADDSUB132PDZmk = 9895 + + VFMADDSUB132PDZmkz = 9896 + + VFMADDSUB132PDZr = 9897 + + VFMADDSUB132PDZrb = 9898 + + VFMADDSUB132PDZrbk = 9899 + + VFMADDSUB132PDZrbkz = 9900 + + VFMADDSUB132PDZrk = 9901 + + VFMADDSUB132PDZrkz = 9902 + + VFMADDSUB132PDm = 9903 + + VFMADDSUB132PDr = 9904 + + VFMADDSUB132PHZ128m = 9905 + + VFMADDSUB132PHZ128mb = 9906 + + VFMADDSUB132PHZ128mbk = 9907 + + VFMADDSUB132PHZ128mbkz = 9908 + + VFMADDSUB132PHZ128mk = 9909 + + VFMADDSUB132PHZ128mkz = 9910 + + VFMADDSUB132PHZ128r = 9911 + + VFMADDSUB132PHZ128rk = 9912 + + VFMADDSUB132PHZ128rkz = 9913 + + VFMADDSUB132PHZ256m = 9914 + + VFMADDSUB132PHZ256mb = 9915 + + VFMADDSUB132PHZ256mbk = 9916 + + VFMADDSUB132PHZ256mbkz = 9917 + + VFMADDSUB132PHZ256mk = 9918 + + VFMADDSUB132PHZ256mkz = 9919 + + VFMADDSUB132PHZ256r = 9920 + + VFMADDSUB132PHZ256rk = 9921 + + VFMADDSUB132PHZ256rkz = 9922 + + VFMADDSUB132PHZm = 9923 + + VFMADDSUB132PHZmb = 9924 + + VFMADDSUB132PHZmbk = 9925 + + VFMADDSUB132PHZmbkz = 9926 + + VFMADDSUB132PHZmk = 9927 + + VFMADDSUB132PHZmkz = 9928 + + VFMADDSUB132PHZr = 9929 + + VFMADDSUB132PHZrb = 9930 + + VFMADDSUB132PHZrbk = 9931 + + VFMADDSUB132PHZrbkz = 9932 + + VFMADDSUB132PHZrk = 9933 + + VFMADDSUB132PHZrkz = 9934 + + VFMADDSUB132PSYm = 9935 + + VFMADDSUB132PSYr = 9936 + + VFMADDSUB132PSZ128m = 9937 + + VFMADDSUB132PSZ128mb = 9938 + + VFMADDSUB132PSZ128mbk = 9939 + + VFMADDSUB132PSZ128mbkz = 9940 + + VFMADDSUB132PSZ128mk = 9941 + + VFMADDSUB132PSZ128mkz = 9942 + + VFMADDSUB132PSZ128r = 9943 + + VFMADDSUB132PSZ128rk = 9944 + + VFMADDSUB132PSZ128rkz = 9945 + + VFMADDSUB132PSZ256m = 9946 + + VFMADDSUB132PSZ256mb = 9947 + + VFMADDSUB132PSZ256mbk = 9948 + + VFMADDSUB132PSZ256mbkz = 9949 + + VFMADDSUB132PSZ256mk = 9950 + + VFMADDSUB132PSZ256mkz = 9951 + + VFMADDSUB132PSZ256r = 9952 + + VFMADDSUB132PSZ256rk = 9953 + + VFMADDSUB132PSZ256rkz = 9954 + + VFMADDSUB132PSZm = 9955 + + VFMADDSUB132PSZmb = 9956 + + VFMADDSUB132PSZmbk = 9957 + + VFMADDSUB132PSZmbkz = 9958 + + VFMADDSUB132PSZmk = 9959 + + VFMADDSUB132PSZmkz = 9960 + + VFMADDSUB132PSZr = 9961 + + VFMADDSUB132PSZrb = 9962 + + VFMADDSUB132PSZrbk = 9963 + + VFMADDSUB132PSZrbkz = 9964 + + VFMADDSUB132PSZrk = 9965 + + VFMADDSUB132PSZrkz = 9966 + + VFMADDSUB132PSm = 9967 + + VFMADDSUB132PSr = 9968 + + VFMADDSUB213PDYm = 9969 + + VFMADDSUB213PDYr = 9970 + + VFMADDSUB213PDZ128m = 9971 + + VFMADDSUB213PDZ128mb = 9972 + + VFMADDSUB213PDZ128mbk = 9973 + + VFMADDSUB213PDZ128mbkz = 9974 + + VFMADDSUB213PDZ128mk = 9975 + + VFMADDSUB213PDZ128mkz = 9976 + + VFMADDSUB213PDZ128r = 9977 + + VFMADDSUB213PDZ128rk = 9978 + + VFMADDSUB213PDZ128rkz = 9979 + + VFMADDSUB213PDZ256m = 9980 + + VFMADDSUB213PDZ256mb = 9981 + + VFMADDSUB213PDZ256mbk = 9982 + + VFMADDSUB213PDZ256mbkz = 9983 + + VFMADDSUB213PDZ256mk = 9984 + + VFMADDSUB213PDZ256mkz = 9985 + + VFMADDSUB213PDZ256r = 9986 + + VFMADDSUB213PDZ256rk = 9987 + + VFMADDSUB213PDZ256rkz = 9988 + + VFMADDSUB213PDZm = 9989 + + VFMADDSUB213PDZmb = 9990 + + VFMADDSUB213PDZmbk = 9991 + + VFMADDSUB213PDZmbkz = 9992 + + VFMADDSUB213PDZmk = 9993 + + VFMADDSUB213PDZmkz = 9994 + + VFMADDSUB213PDZr = 9995 + + VFMADDSUB213PDZrb = 9996 + + VFMADDSUB213PDZrbk = 9997 + + VFMADDSUB213PDZrbkz = 9998 + + VFMADDSUB213PDZrk = 9999 + + VFMADDSUB213PDZrkz = 10000 + + VFMADDSUB213PDm = 10001 + + VFMADDSUB213PDr = 10002 + + VFMADDSUB213PHZ128m = 10003 + + VFMADDSUB213PHZ128mb = 10004 + + VFMADDSUB213PHZ128mbk = 10005 + + VFMADDSUB213PHZ128mbkz = 10006 + + VFMADDSUB213PHZ128mk = 10007 + + VFMADDSUB213PHZ128mkz = 10008 + + VFMADDSUB213PHZ128r = 10009 + + VFMADDSUB213PHZ128rk = 10010 + + VFMADDSUB213PHZ128rkz = 10011 + + VFMADDSUB213PHZ256m = 10012 + + VFMADDSUB213PHZ256mb = 10013 + + VFMADDSUB213PHZ256mbk = 10014 + + VFMADDSUB213PHZ256mbkz = 10015 + + VFMADDSUB213PHZ256mk = 10016 + + VFMADDSUB213PHZ256mkz = 10017 + + VFMADDSUB213PHZ256r = 10018 + + VFMADDSUB213PHZ256rk = 10019 + + VFMADDSUB213PHZ256rkz = 10020 + + VFMADDSUB213PHZm = 10021 + + VFMADDSUB213PHZmb = 10022 + + VFMADDSUB213PHZmbk = 10023 + + VFMADDSUB213PHZmbkz = 10024 + + VFMADDSUB213PHZmk = 10025 + + VFMADDSUB213PHZmkz = 10026 + + VFMADDSUB213PHZr = 10027 + + VFMADDSUB213PHZrb = 10028 + + VFMADDSUB213PHZrbk = 10029 + + VFMADDSUB213PHZrbkz = 10030 + + VFMADDSUB213PHZrk = 10031 + + VFMADDSUB213PHZrkz = 10032 + + VFMADDSUB213PSYm = 10033 + + VFMADDSUB213PSYr = 10034 + + VFMADDSUB213PSZ128m = 10035 + + VFMADDSUB213PSZ128mb = 10036 + + VFMADDSUB213PSZ128mbk = 10037 + + VFMADDSUB213PSZ128mbkz = 10038 + + VFMADDSUB213PSZ128mk = 10039 + + VFMADDSUB213PSZ128mkz = 10040 + + VFMADDSUB213PSZ128r = 10041 + + VFMADDSUB213PSZ128rk = 10042 + + VFMADDSUB213PSZ128rkz = 10043 + + VFMADDSUB213PSZ256m = 10044 + + VFMADDSUB213PSZ256mb = 10045 + + VFMADDSUB213PSZ256mbk = 10046 + + VFMADDSUB213PSZ256mbkz = 10047 + + VFMADDSUB213PSZ256mk = 10048 + + VFMADDSUB213PSZ256mkz = 10049 + + VFMADDSUB213PSZ256r = 10050 + + VFMADDSUB213PSZ256rk = 10051 + + VFMADDSUB213PSZ256rkz = 10052 + + VFMADDSUB213PSZm = 10053 + + VFMADDSUB213PSZmb = 10054 + + VFMADDSUB213PSZmbk = 10055 + + VFMADDSUB213PSZmbkz = 10056 + + VFMADDSUB213PSZmk = 10057 + + VFMADDSUB213PSZmkz = 10058 + + VFMADDSUB213PSZr = 10059 + + VFMADDSUB213PSZrb = 10060 + + VFMADDSUB213PSZrbk = 10061 + + VFMADDSUB213PSZrbkz = 10062 + + VFMADDSUB213PSZrk = 10063 + + VFMADDSUB213PSZrkz = 10064 + + VFMADDSUB213PSm = 10065 + + VFMADDSUB213PSr = 10066 + + VFMADDSUB231PDYm = 10067 + + VFMADDSUB231PDYr = 10068 + + VFMADDSUB231PDZ128m = 10069 + + VFMADDSUB231PDZ128mb = 10070 + + VFMADDSUB231PDZ128mbk = 10071 + + VFMADDSUB231PDZ128mbkz = 10072 + + VFMADDSUB231PDZ128mk = 10073 + + VFMADDSUB231PDZ128mkz = 10074 + + VFMADDSUB231PDZ128r = 10075 + + VFMADDSUB231PDZ128rk = 10076 + + VFMADDSUB231PDZ128rkz = 10077 + + VFMADDSUB231PDZ256m = 10078 + + VFMADDSUB231PDZ256mb = 10079 + + VFMADDSUB231PDZ256mbk = 10080 + + VFMADDSUB231PDZ256mbkz = 10081 + + VFMADDSUB231PDZ256mk = 10082 + + VFMADDSUB231PDZ256mkz = 10083 + + VFMADDSUB231PDZ256r = 10084 + + VFMADDSUB231PDZ256rk = 10085 + + VFMADDSUB231PDZ256rkz = 10086 + + VFMADDSUB231PDZm = 10087 + + VFMADDSUB231PDZmb = 10088 + + VFMADDSUB231PDZmbk = 10089 + + VFMADDSUB231PDZmbkz = 10090 + + VFMADDSUB231PDZmk = 10091 + + VFMADDSUB231PDZmkz = 10092 + + VFMADDSUB231PDZr = 10093 + + VFMADDSUB231PDZrb = 10094 + + VFMADDSUB231PDZrbk = 10095 + + VFMADDSUB231PDZrbkz = 10096 + + VFMADDSUB231PDZrk = 10097 + + VFMADDSUB231PDZrkz = 10098 + + VFMADDSUB231PDm = 10099 + + VFMADDSUB231PDr = 10100 + + VFMADDSUB231PHZ128m = 10101 + + VFMADDSUB231PHZ128mb = 10102 + + VFMADDSUB231PHZ128mbk = 10103 + + VFMADDSUB231PHZ128mbkz = 10104 + + VFMADDSUB231PHZ128mk = 10105 + + VFMADDSUB231PHZ128mkz = 10106 + + VFMADDSUB231PHZ128r = 10107 + + VFMADDSUB231PHZ128rk = 10108 + + VFMADDSUB231PHZ128rkz = 10109 + + VFMADDSUB231PHZ256m = 10110 + + VFMADDSUB231PHZ256mb = 10111 + + VFMADDSUB231PHZ256mbk = 10112 + + VFMADDSUB231PHZ256mbkz = 10113 + + VFMADDSUB231PHZ256mk = 10114 + + VFMADDSUB231PHZ256mkz = 10115 + + VFMADDSUB231PHZ256r = 10116 + + VFMADDSUB231PHZ256rk = 10117 + + VFMADDSUB231PHZ256rkz = 10118 + + VFMADDSUB231PHZm = 10119 + + VFMADDSUB231PHZmb = 10120 + + VFMADDSUB231PHZmbk = 10121 + + VFMADDSUB231PHZmbkz = 10122 + + VFMADDSUB231PHZmk = 10123 + + VFMADDSUB231PHZmkz = 10124 + + VFMADDSUB231PHZr = 10125 + + VFMADDSUB231PHZrb = 10126 + + VFMADDSUB231PHZrbk = 10127 + + VFMADDSUB231PHZrbkz = 10128 + + VFMADDSUB231PHZrk = 10129 + + VFMADDSUB231PHZrkz = 10130 + + VFMADDSUB231PSYm = 10131 + + VFMADDSUB231PSYr = 10132 + + VFMADDSUB231PSZ128m = 10133 + + VFMADDSUB231PSZ128mb = 10134 + + VFMADDSUB231PSZ128mbk = 10135 + + VFMADDSUB231PSZ128mbkz = 10136 + + VFMADDSUB231PSZ128mk = 10137 + + VFMADDSUB231PSZ128mkz = 10138 + + VFMADDSUB231PSZ128r = 10139 + + VFMADDSUB231PSZ128rk = 10140 + + VFMADDSUB231PSZ128rkz = 10141 + + VFMADDSUB231PSZ256m = 10142 + + VFMADDSUB231PSZ256mb = 10143 + + VFMADDSUB231PSZ256mbk = 10144 + + VFMADDSUB231PSZ256mbkz = 10145 + + VFMADDSUB231PSZ256mk = 10146 + + VFMADDSUB231PSZ256mkz = 10147 + + VFMADDSUB231PSZ256r = 10148 + + VFMADDSUB231PSZ256rk = 10149 + + VFMADDSUB231PSZ256rkz = 10150 + + VFMADDSUB231PSZm = 10151 + + VFMADDSUB231PSZmb = 10152 + + VFMADDSUB231PSZmbk = 10153 + + VFMADDSUB231PSZmbkz = 10154 + + VFMADDSUB231PSZmk = 10155 + + VFMADDSUB231PSZmkz = 10156 + + VFMADDSUB231PSZr = 10157 + + VFMADDSUB231PSZrb = 10158 + + VFMADDSUB231PSZrbk = 10159 + + VFMADDSUB231PSZrbkz = 10160 + + VFMADDSUB231PSZrk = 10161 + + VFMADDSUB231PSZrkz = 10162 + + VFMADDSUB231PSm = 10163 + + VFMADDSUB231PSr = 10164 + + VFMADDSUBPD4Ymr = 10165 + + VFMADDSUBPD4Yrm = 10166 + + VFMADDSUBPD4Yrr = 10167 + + VFMADDSUBPD4Yrr_REV = 10168 + + VFMADDSUBPD4mr = 10169 + + VFMADDSUBPD4rm = 10170 + + VFMADDSUBPD4rr = 10171 + + VFMADDSUBPD4rr_REV = 10172 + + VFMADDSUBPS4Ymr = 10173 + + VFMADDSUBPS4Yrm = 10174 + + VFMADDSUBPS4Yrr = 10175 + + VFMADDSUBPS4Yrr_REV = 10176 + + VFMADDSUBPS4mr = 10177 + + VFMADDSUBPS4rm = 10178 + + VFMADDSUBPS4rr = 10179 + + VFMADDSUBPS4rr_REV = 10180 + + VFMSUB132BF16Z128m = 10181 + + VFMSUB132BF16Z128mb = 10182 + + VFMSUB132BF16Z128mbk = 10183 + + VFMSUB132BF16Z128mbkz = 10184 + + VFMSUB132BF16Z128mk = 10185 + + VFMSUB132BF16Z128mkz = 10186 + + VFMSUB132BF16Z128r = 10187 + + VFMSUB132BF16Z128rk = 10188 + + VFMSUB132BF16Z128rkz = 10189 + + VFMSUB132BF16Z256m = 10190 + + VFMSUB132BF16Z256mb = 10191 + + VFMSUB132BF16Z256mbk = 10192 + + VFMSUB132BF16Z256mbkz = 10193 + + VFMSUB132BF16Z256mk = 10194 + + VFMSUB132BF16Z256mkz = 10195 + + VFMSUB132BF16Z256r = 10196 + + VFMSUB132BF16Z256rk = 10197 + + VFMSUB132BF16Z256rkz = 10198 + + VFMSUB132BF16Zm = 10199 + + VFMSUB132BF16Zmb = 10200 + + VFMSUB132BF16Zmbk = 10201 + + VFMSUB132BF16Zmbkz = 10202 + + VFMSUB132BF16Zmk = 10203 + + VFMSUB132BF16Zmkz = 10204 + + VFMSUB132BF16Zr = 10205 + + VFMSUB132BF16Zrk = 10206 + + VFMSUB132BF16Zrkz = 10207 + + VFMSUB132PDYm = 10208 + + VFMSUB132PDYr = 10209 + + VFMSUB132PDZ128m = 10210 + + VFMSUB132PDZ128mb = 10211 + + VFMSUB132PDZ128mbk = 10212 + + VFMSUB132PDZ128mbkz = 10213 + + VFMSUB132PDZ128mk = 10214 + + VFMSUB132PDZ128mkz = 10215 + + VFMSUB132PDZ128r = 10216 + + VFMSUB132PDZ128rk = 10217 + + VFMSUB132PDZ128rkz = 10218 + + VFMSUB132PDZ256m = 10219 + + VFMSUB132PDZ256mb = 10220 + + VFMSUB132PDZ256mbk = 10221 + + VFMSUB132PDZ256mbkz = 10222 + + VFMSUB132PDZ256mk = 10223 + + VFMSUB132PDZ256mkz = 10224 + + VFMSUB132PDZ256r = 10225 + + VFMSUB132PDZ256rk = 10226 + + VFMSUB132PDZ256rkz = 10227 + + VFMSUB132PDZm = 10228 + + VFMSUB132PDZmb = 10229 + + VFMSUB132PDZmbk = 10230 + + VFMSUB132PDZmbkz = 10231 + + VFMSUB132PDZmk = 10232 + + VFMSUB132PDZmkz = 10233 + + VFMSUB132PDZr = 10234 + + VFMSUB132PDZrb = 10235 + + VFMSUB132PDZrbk = 10236 + + VFMSUB132PDZrbkz = 10237 + + VFMSUB132PDZrk = 10238 + + VFMSUB132PDZrkz = 10239 + + VFMSUB132PDm = 10240 + + VFMSUB132PDr = 10241 + + VFMSUB132PHZ128m = 10242 + + VFMSUB132PHZ128mb = 10243 + + VFMSUB132PHZ128mbk = 10244 + + VFMSUB132PHZ128mbkz = 10245 + + VFMSUB132PHZ128mk = 10246 + + VFMSUB132PHZ128mkz = 10247 + + VFMSUB132PHZ128r = 10248 + + VFMSUB132PHZ128rk = 10249 + + VFMSUB132PHZ128rkz = 10250 + + VFMSUB132PHZ256m = 10251 + + VFMSUB132PHZ256mb = 10252 + + VFMSUB132PHZ256mbk = 10253 + + VFMSUB132PHZ256mbkz = 10254 + + VFMSUB132PHZ256mk = 10255 + + VFMSUB132PHZ256mkz = 10256 + + VFMSUB132PHZ256r = 10257 + + VFMSUB132PHZ256rk = 10258 + + VFMSUB132PHZ256rkz = 10259 + + VFMSUB132PHZm = 10260 + + VFMSUB132PHZmb = 10261 + + VFMSUB132PHZmbk = 10262 + + VFMSUB132PHZmbkz = 10263 + + VFMSUB132PHZmk = 10264 + + VFMSUB132PHZmkz = 10265 + + VFMSUB132PHZr = 10266 + + VFMSUB132PHZrb = 10267 + + VFMSUB132PHZrbk = 10268 + + VFMSUB132PHZrbkz = 10269 + + VFMSUB132PHZrk = 10270 + + VFMSUB132PHZrkz = 10271 + + VFMSUB132PSYm = 10272 + + VFMSUB132PSYr = 10273 + + VFMSUB132PSZ128m = 10274 + + VFMSUB132PSZ128mb = 10275 + + VFMSUB132PSZ128mbk = 10276 + + VFMSUB132PSZ128mbkz = 10277 + + VFMSUB132PSZ128mk = 10278 + + VFMSUB132PSZ128mkz = 10279 + + VFMSUB132PSZ128r = 10280 + + VFMSUB132PSZ128rk = 10281 + + VFMSUB132PSZ128rkz = 10282 + + VFMSUB132PSZ256m = 10283 + + VFMSUB132PSZ256mb = 10284 + + VFMSUB132PSZ256mbk = 10285 + + VFMSUB132PSZ256mbkz = 10286 + + VFMSUB132PSZ256mk = 10287 + + VFMSUB132PSZ256mkz = 10288 + + VFMSUB132PSZ256r = 10289 + + VFMSUB132PSZ256rk = 10290 + + VFMSUB132PSZ256rkz = 10291 + + VFMSUB132PSZm = 10292 + + VFMSUB132PSZmb = 10293 + + VFMSUB132PSZmbk = 10294 + + VFMSUB132PSZmbkz = 10295 + + VFMSUB132PSZmk = 10296 + + VFMSUB132PSZmkz = 10297 + + VFMSUB132PSZr = 10298 + + VFMSUB132PSZrb = 10299 + + VFMSUB132PSZrbk = 10300 + + VFMSUB132PSZrbkz = 10301 + + VFMSUB132PSZrk = 10302 + + VFMSUB132PSZrkz = 10303 + + VFMSUB132PSm = 10304 + + VFMSUB132PSr = 10305 + + VFMSUB132SDZm = 10306 + + VFMSUB132SDZm_Int = 10307 + + VFMSUB132SDZmk_Int = 10308 + + VFMSUB132SDZmkz_Int = 10309 + + VFMSUB132SDZr = 10310 + + VFMSUB132SDZr_Int = 10311 + + VFMSUB132SDZrb = 10312 + + VFMSUB132SDZrb_Int = 10313 + + VFMSUB132SDZrbk_Int = 10314 + + VFMSUB132SDZrbkz_Int = 10315 + + VFMSUB132SDZrk_Int = 10316 + + VFMSUB132SDZrkz_Int = 10317 + + VFMSUB132SDm = 10318 + + VFMSUB132SDm_Int = 10319 + + VFMSUB132SDr = 10320 + + VFMSUB132SDr_Int = 10321 + + VFMSUB132SHZm = 10322 + + VFMSUB132SHZm_Int = 10323 + + VFMSUB132SHZmk_Int = 10324 + + VFMSUB132SHZmkz_Int = 10325 + + VFMSUB132SHZr = 10326 + + VFMSUB132SHZr_Int = 10327 + + VFMSUB132SHZrb = 10328 + + VFMSUB132SHZrb_Int = 10329 + + VFMSUB132SHZrbk_Int = 10330 + + VFMSUB132SHZrbkz_Int = 10331 + + VFMSUB132SHZrk_Int = 10332 + + VFMSUB132SHZrkz_Int = 10333 + + VFMSUB132SSZm = 10334 + + VFMSUB132SSZm_Int = 10335 + + VFMSUB132SSZmk_Int = 10336 + + VFMSUB132SSZmkz_Int = 10337 + + VFMSUB132SSZr = 10338 + + VFMSUB132SSZr_Int = 10339 + + VFMSUB132SSZrb = 10340 + + VFMSUB132SSZrb_Int = 10341 + + VFMSUB132SSZrbk_Int = 10342 + + VFMSUB132SSZrbkz_Int = 10343 + + VFMSUB132SSZrk_Int = 10344 + + VFMSUB132SSZrkz_Int = 10345 + + VFMSUB132SSm = 10346 + + VFMSUB132SSm_Int = 10347 + + VFMSUB132SSr = 10348 + + VFMSUB132SSr_Int = 10349 + + VFMSUB213BF16Z128m = 10350 + + VFMSUB213BF16Z128mb = 10351 + + VFMSUB213BF16Z128mbk = 10352 + + VFMSUB213BF16Z128mbkz = 10353 + + VFMSUB213BF16Z128mk = 10354 + + VFMSUB213BF16Z128mkz = 10355 + + VFMSUB213BF16Z128r = 10356 + + VFMSUB213BF16Z128rk = 10357 + + VFMSUB213BF16Z128rkz = 10358 + + VFMSUB213BF16Z256m = 10359 + + VFMSUB213BF16Z256mb = 10360 + + VFMSUB213BF16Z256mbk = 10361 + + VFMSUB213BF16Z256mbkz = 10362 + + VFMSUB213BF16Z256mk = 10363 + + VFMSUB213BF16Z256mkz = 10364 + + VFMSUB213BF16Z256r = 10365 + + VFMSUB213BF16Z256rk = 10366 + + VFMSUB213BF16Z256rkz = 10367 + + VFMSUB213BF16Zm = 10368 + + VFMSUB213BF16Zmb = 10369 + + VFMSUB213BF16Zmbk = 10370 + + VFMSUB213BF16Zmbkz = 10371 + + VFMSUB213BF16Zmk = 10372 + + VFMSUB213BF16Zmkz = 10373 + + VFMSUB213BF16Zr = 10374 + + VFMSUB213BF16Zrk = 10375 + + VFMSUB213BF16Zrkz = 10376 + + VFMSUB213PDYm = 10377 + + VFMSUB213PDYr = 10378 + + VFMSUB213PDZ128m = 10379 + + VFMSUB213PDZ128mb = 10380 + + VFMSUB213PDZ128mbk = 10381 + + VFMSUB213PDZ128mbkz = 10382 + + VFMSUB213PDZ128mk = 10383 + + VFMSUB213PDZ128mkz = 10384 + + VFMSUB213PDZ128r = 10385 + + VFMSUB213PDZ128rk = 10386 + + VFMSUB213PDZ128rkz = 10387 + + VFMSUB213PDZ256m = 10388 + + VFMSUB213PDZ256mb = 10389 + + VFMSUB213PDZ256mbk = 10390 + + VFMSUB213PDZ256mbkz = 10391 + + VFMSUB213PDZ256mk = 10392 + + VFMSUB213PDZ256mkz = 10393 + + VFMSUB213PDZ256r = 10394 + + VFMSUB213PDZ256rk = 10395 + + VFMSUB213PDZ256rkz = 10396 + + VFMSUB213PDZm = 10397 + + VFMSUB213PDZmb = 10398 + + VFMSUB213PDZmbk = 10399 + + VFMSUB213PDZmbkz = 10400 + + VFMSUB213PDZmk = 10401 + + VFMSUB213PDZmkz = 10402 + + VFMSUB213PDZr = 10403 + + VFMSUB213PDZrb = 10404 + + VFMSUB213PDZrbk = 10405 + + VFMSUB213PDZrbkz = 10406 + + VFMSUB213PDZrk = 10407 + + VFMSUB213PDZrkz = 10408 + + VFMSUB213PDm = 10409 + + VFMSUB213PDr = 10410 + + VFMSUB213PHZ128m = 10411 + + VFMSUB213PHZ128mb = 10412 + + VFMSUB213PHZ128mbk = 10413 + + VFMSUB213PHZ128mbkz = 10414 + + VFMSUB213PHZ128mk = 10415 + + VFMSUB213PHZ128mkz = 10416 + + VFMSUB213PHZ128r = 10417 + + VFMSUB213PHZ128rk = 10418 + + VFMSUB213PHZ128rkz = 10419 + + VFMSUB213PHZ256m = 10420 + + VFMSUB213PHZ256mb = 10421 + + VFMSUB213PHZ256mbk = 10422 + + VFMSUB213PHZ256mbkz = 10423 + + VFMSUB213PHZ256mk = 10424 + + VFMSUB213PHZ256mkz = 10425 + + VFMSUB213PHZ256r = 10426 + + VFMSUB213PHZ256rk = 10427 + + VFMSUB213PHZ256rkz = 10428 + + VFMSUB213PHZm = 10429 + + VFMSUB213PHZmb = 10430 + + VFMSUB213PHZmbk = 10431 + + VFMSUB213PHZmbkz = 10432 + + VFMSUB213PHZmk = 10433 + + VFMSUB213PHZmkz = 10434 + + VFMSUB213PHZr = 10435 + + VFMSUB213PHZrb = 10436 + + VFMSUB213PHZrbk = 10437 + + VFMSUB213PHZrbkz = 10438 + + VFMSUB213PHZrk = 10439 + + VFMSUB213PHZrkz = 10440 + + VFMSUB213PSYm = 10441 + + VFMSUB213PSYr = 10442 + + VFMSUB213PSZ128m = 10443 + + VFMSUB213PSZ128mb = 10444 + + VFMSUB213PSZ128mbk = 10445 + + VFMSUB213PSZ128mbkz = 10446 + + VFMSUB213PSZ128mk = 10447 + + VFMSUB213PSZ128mkz = 10448 + + VFMSUB213PSZ128r = 10449 + + VFMSUB213PSZ128rk = 10450 + + VFMSUB213PSZ128rkz = 10451 + + VFMSUB213PSZ256m = 10452 + + VFMSUB213PSZ256mb = 10453 + + VFMSUB213PSZ256mbk = 10454 + + VFMSUB213PSZ256mbkz = 10455 + + VFMSUB213PSZ256mk = 10456 + + VFMSUB213PSZ256mkz = 10457 + + VFMSUB213PSZ256r = 10458 + + VFMSUB213PSZ256rk = 10459 + + VFMSUB213PSZ256rkz = 10460 + + VFMSUB213PSZm = 10461 + + VFMSUB213PSZmb = 10462 + + VFMSUB213PSZmbk = 10463 + + VFMSUB213PSZmbkz = 10464 + + VFMSUB213PSZmk = 10465 + + VFMSUB213PSZmkz = 10466 + + VFMSUB213PSZr = 10467 + + VFMSUB213PSZrb = 10468 + + VFMSUB213PSZrbk = 10469 + + VFMSUB213PSZrbkz = 10470 + + VFMSUB213PSZrk = 10471 + + VFMSUB213PSZrkz = 10472 + + VFMSUB213PSm = 10473 + + VFMSUB213PSr = 10474 + + VFMSUB213SDZm = 10475 + + VFMSUB213SDZm_Int = 10476 + + VFMSUB213SDZmk_Int = 10477 + + VFMSUB213SDZmkz_Int = 10478 + + VFMSUB213SDZr = 10479 + + VFMSUB213SDZr_Int = 10480 + + VFMSUB213SDZrb = 10481 + + VFMSUB213SDZrb_Int = 10482 + + VFMSUB213SDZrbk_Int = 10483 + + VFMSUB213SDZrbkz_Int = 10484 + + VFMSUB213SDZrk_Int = 10485 + + VFMSUB213SDZrkz_Int = 10486 + + VFMSUB213SDm = 10487 + + VFMSUB213SDm_Int = 10488 + + VFMSUB213SDr = 10489 + + VFMSUB213SDr_Int = 10490 + + VFMSUB213SHZm = 10491 + + VFMSUB213SHZm_Int = 10492 + + VFMSUB213SHZmk_Int = 10493 + + VFMSUB213SHZmkz_Int = 10494 + + VFMSUB213SHZr = 10495 + + VFMSUB213SHZr_Int = 10496 + + VFMSUB213SHZrb = 10497 + + VFMSUB213SHZrb_Int = 10498 + + VFMSUB213SHZrbk_Int = 10499 + + VFMSUB213SHZrbkz_Int = 10500 + + VFMSUB213SHZrk_Int = 10501 + + VFMSUB213SHZrkz_Int = 10502 + + VFMSUB213SSZm = 10503 + + VFMSUB213SSZm_Int = 10504 + + VFMSUB213SSZmk_Int = 10505 + + VFMSUB213SSZmkz_Int = 10506 + + VFMSUB213SSZr = 10507 + + VFMSUB213SSZr_Int = 10508 + + VFMSUB213SSZrb = 10509 + + VFMSUB213SSZrb_Int = 10510 + + VFMSUB213SSZrbk_Int = 10511 + + VFMSUB213SSZrbkz_Int = 10512 + + VFMSUB213SSZrk_Int = 10513 + + VFMSUB213SSZrkz_Int = 10514 + + VFMSUB213SSm = 10515 + + VFMSUB213SSm_Int = 10516 + + VFMSUB213SSr = 10517 + + VFMSUB213SSr_Int = 10518 + + VFMSUB231BF16Z128m = 10519 + + VFMSUB231BF16Z128mb = 10520 + + VFMSUB231BF16Z128mbk = 10521 + + VFMSUB231BF16Z128mbkz = 10522 + + VFMSUB231BF16Z128mk = 10523 + + VFMSUB231BF16Z128mkz = 10524 + + VFMSUB231BF16Z128r = 10525 + + VFMSUB231BF16Z128rk = 10526 + + VFMSUB231BF16Z128rkz = 10527 + + VFMSUB231BF16Z256m = 10528 + + VFMSUB231BF16Z256mb = 10529 + + VFMSUB231BF16Z256mbk = 10530 + + VFMSUB231BF16Z256mbkz = 10531 + + VFMSUB231BF16Z256mk = 10532 + + VFMSUB231BF16Z256mkz = 10533 + + VFMSUB231BF16Z256r = 10534 + + VFMSUB231BF16Z256rk = 10535 + + VFMSUB231BF16Z256rkz = 10536 + + VFMSUB231BF16Zm = 10537 + + VFMSUB231BF16Zmb = 10538 + + VFMSUB231BF16Zmbk = 10539 + + VFMSUB231BF16Zmbkz = 10540 + + VFMSUB231BF16Zmk = 10541 + + VFMSUB231BF16Zmkz = 10542 + + VFMSUB231BF16Zr = 10543 + + VFMSUB231BF16Zrk = 10544 + + VFMSUB231BF16Zrkz = 10545 + + VFMSUB231PDYm = 10546 + + VFMSUB231PDYr = 10547 + + VFMSUB231PDZ128m = 10548 + + VFMSUB231PDZ128mb = 10549 + + VFMSUB231PDZ128mbk = 10550 + + VFMSUB231PDZ128mbkz = 10551 + + VFMSUB231PDZ128mk = 10552 + + VFMSUB231PDZ128mkz = 10553 + + VFMSUB231PDZ128r = 10554 + + VFMSUB231PDZ128rk = 10555 + + VFMSUB231PDZ128rkz = 10556 + + VFMSUB231PDZ256m = 10557 + + VFMSUB231PDZ256mb = 10558 + + VFMSUB231PDZ256mbk = 10559 + + VFMSUB231PDZ256mbkz = 10560 + + VFMSUB231PDZ256mk = 10561 + + VFMSUB231PDZ256mkz = 10562 + + VFMSUB231PDZ256r = 10563 + + VFMSUB231PDZ256rk = 10564 + + VFMSUB231PDZ256rkz = 10565 + + VFMSUB231PDZm = 10566 + + VFMSUB231PDZmb = 10567 + + VFMSUB231PDZmbk = 10568 + + VFMSUB231PDZmbkz = 10569 + + VFMSUB231PDZmk = 10570 + + VFMSUB231PDZmkz = 10571 + + VFMSUB231PDZr = 10572 + + VFMSUB231PDZrb = 10573 + + VFMSUB231PDZrbk = 10574 + + VFMSUB231PDZrbkz = 10575 + + VFMSUB231PDZrk = 10576 + + VFMSUB231PDZrkz = 10577 + + VFMSUB231PDm = 10578 + + VFMSUB231PDr = 10579 + + VFMSUB231PHZ128m = 10580 + + VFMSUB231PHZ128mb = 10581 + + VFMSUB231PHZ128mbk = 10582 + + VFMSUB231PHZ128mbkz = 10583 + + VFMSUB231PHZ128mk = 10584 + + VFMSUB231PHZ128mkz = 10585 + + VFMSUB231PHZ128r = 10586 + + VFMSUB231PHZ128rk = 10587 + + VFMSUB231PHZ128rkz = 10588 + + VFMSUB231PHZ256m = 10589 + + VFMSUB231PHZ256mb = 10590 + + VFMSUB231PHZ256mbk = 10591 + + VFMSUB231PHZ256mbkz = 10592 + + VFMSUB231PHZ256mk = 10593 + + VFMSUB231PHZ256mkz = 10594 + + VFMSUB231PHZ256r = 10595 + + VFMSUB231PHZ256rk = 10596 + + VFMSUB231PHZ256rkz = 10597 + + VFMSUB231PHZm = 10598 + + VFMSUB231PHZmb = 10599 + + VFMSUB231PHZmbk = 10600 + + VFMSUB231PHZmbkz = 10601 + + VFMSUB231PHZmk = 10602 + + VFMSUB231PHZmkz = 10603 + + VFMSUB231PHZr = 10604 + + VFMSUB231PHZrb = 10605 + + VFMSUB231PHZrbk = 10606 + + VFMSUB231PHZrbkz = 10607 + + VFMSUB231PHZrk = 10608 + + VFMSUB231PHZrkz = 10609 + + VFMSUB231PSYm = 10610 + + VFMSUB231PSYr = 10611 + + VFMSUB231PSZ128m = 10612 + + VFMSUB231PSZ128mb = 10613 + + VFMSUB231PSZ128mbk = 10614 + + VFMSUB231PSZ128mbkz = 10615 + + VFMSUB231PSZ128mk = 10616 + + VFMSUB231PSZ128mkz = 10617 + + VFMSUB231PSZ128r = 10618 + + VFMSUB231PSZ128rk = 10619 + + VFMSUB231PSZ128rkz = 10620 + + VFMSUB231PSZ256m = 10621 + + VFMSUB231PSZ256mb = 10622 + + VFMSUB231PSZ256mbk = 10623 + + VFMSUB231PSZ256mbkz = 10624 + + VFMSUB231PSZ256mk = 10625 + + VFMSUB231PSZ256mkz = 10626 + + VFMSUB231PSZ256r = 10627 + + VFMSUB231PSZ256rk = 10628 + + VFMSUB231PSZ256rkz = 10629 + + VFMSUB231PSZm = 10630 + + VFMSUB231PSZmb = 10631 + + VFMSUB231PSZmbk = 10632 + + VFMSUB231PSZmbkz = 10633 + + VFMSUB231PSZmk = 10634 + + VFMSUB231PSZmkz = 10635 + + VFMSUB231PSZr = 10636 + + VFMSUB231PSZrb = 10637 + + VFMSUB231PSZrbk = 10638 + + VFMSUB231PSZrbkz = 10639 + + VFMSUB231PSZrk = 10640 + + VFMSUB231PSZrkz = 10641 + + VFMSUB231PSm = 10642 + + VFMSUB231PSr = 10643 + + VFMSUB231SDZm = 10644 + + VFMSUB231SDZm_Int = 10645 + + VFMSUB231SDZmk_Int = 10646 + + VFMSUB231SDZmkz_Int = 10647 + + VFMSUB231SDZr = 10648 + + VFMSUB231SDZr_Int = 10649 + + VFMSUB231SDZrb = 10650 + + VFMSUB231SDZrb_Int = 10651 + + VFMSUB231SDZrbk_Int = 10652 + + VFMSUB231SDZrbkz_Int = 10653 + + VFMSUB231SDZrk_Int = 10654 + + VFMSUB231SDZrkz_Int = 10655 + + VFMSUB231SDm = 10656 + + VFMSUB231SDm_Int = 10657 + + VFMSUB231SDr = 10658 + + VFMSUB231SDr_Int = 10659 + + VFMSUB231SHZm = 10660 + + VFMSUB231SHZm_Int = 10661 + + VFMSUB231SHZmk_Int = 10662 + + VFMSUB231SHZmkz_Int = 10663 + + VFMSUB231SHZr = 10664 + + VFMSUB231SHZr_Int = 10665 + + VFMSUB231SHZrb = 10666 + + VFMSUB231SHZrb_Int = 10667 + + VFMSUB231SHZrbk_Int = 10668 + + VFMSUB231SHZrbkz_Int = 10669 + + VFMSUB231SHZrk_Int = 10670 + + VFMSUB231SHZrkz_Int = 10671 + + VFMSUB231SSZm = 10672 + + VFMSUB231SSZm_Int = 10673 + + VFMSUB231SSZmk_Int = 10674 + + VFMSUB231SSZmkz_Int = 10675 + + VFMSUB231SSZr = 10676 + + VFMSUB231SSZr_Int = 10677 + + VFMSUB231SSZrb = 10678 + + VFMSUB231SSZrb_Int = 10679 + + VFMSUB231SSZrbk_Int = 10680 + + VFMSUB231SSZrbkz_Int = 10681 + + VFMSUB231SSZrk_Int = 10682 + + VFMSUB231SSZrkz_Int = 10683 + + VFMSUB231SSm = 10684 + + VFMSUB231SSm_Int = 10685 + + VFMSUB231SSr = 10686 + + VFMSUB231SSr_Int = 10687 + + VFMSUBADD132PDYm = 10688 + + VFMSUBADD132PDYr = 10689 + + VFMSUBADD132PDZ128m = 10690 + + VFMSUBADD132PDZ128mb = 10691 + + VFMSUBADD132PDZ128mbk = 10692 + + VFMSUBADD132PDZ128mbkz = 10693 + + VFMSUBADD132PDZ128mk = 10694 + + VFMSUBADD132PDZ128mkz = 10695 + + VFMSUBADD132PDZ128r = 10696 + + VFMSUBADD132PDZ128rk = 10697 + + VFMSUBADD132PDZ128rkz = 10698 + + VFMSUBADD132PDZ256m = 10699 + + VFMSUBADD132PDZ256mb = 10700 + + VFMSUBADD132PDZ256mbk = 10701 + + VFMSUBADD132PDZ256mbkz = 10702 + + VFMSUBADD132PDZ256mk = 10703 + + VFMSUBADD132PDZ256mkz = 10704 + + VFMSUBADD132PDZ256r = 10705 + + VFMSUBADD132PDZ256rk = 10706 + + VFMSUBADD132PDZ256rkz = 10707 + + VFMSUBADD132PDZm = 10708 + + VFMSUBADD132PDZmb = 10709 + + VFMSUBADD132PDZmbk = 10710 + + VFMSUBADD132PDZmbkz = 10711 + + VFMSUBADD132PDZmk = 10712 + + VFMSUBADD132PDZmkz = 10713 + + VFMSUBADD132PDZr = 10714 + + VFMSUBADD132PDZrb = 10715 + + VFMSUBADD132PDZrbk = 10716 + + VFMSUBADD132PDZrbkz = 10717 + + VFMSUBADD132PDZrk = 10718 + + VFMSUBADD132PDZrkz = 10719 + + VFMSUBADD132PDm = 10720 + + VFMSUBADD132PDr = 10721 + + VFMSUBADD132PHZ128m = 10722 + + VFMSUBADD132PHZ128mb = 10723 + + VFMSUBADD132PHZ128mbk = 10724 + + VFMSUBADD132PHZ128mbkz = 10725 + + VFMSUBADD132PHZ128mk = 10726 + + VFMSUBADD132PHZ128mkz = 10727 + + VFMSUBADD132PHZ128r = 10728 + + VFMSUBADD132PHZ128rk = 10729 + + VFMSUBADD132PHZ128rkz = 10730 + + VFMSUBADD132PHZ256m = 10731 + + VFMSUBADD132PHZ256mb = 10732 + + VFMSUBADD132PHZ256mbk = 10733 + + VFMSUBADD132PHZ256mbkz = 10734 + + VFMSUBADD132PHZ256mk = 10735 + + VFMSUBADD132PHZ256mkz = 10736 + + VFMSUBADD132PHZ256r = 10737 + + VFMSUBADD132PHZ256rk = 10738 + + VFMSUBADD132PHZ256rkz = 10739 + + VFMSUBADD132PHZm = 10740 + + VFMSUBADD132PHZmb = 10741 + + VFMSUBADD132PHZmbk = 10742 + + VFMSUBADD132PHZmbkz = 10743 + + VFMSUBADD132PHZmk = 10744 + + VFMSUBADD132PHZmkz = 10745 + + VFMSUBADD132PHZr = 10746 + + VFMSUBADD132PHZrb = 10747 + + VFMSUBADD132PHZrbk = 10748 + + VFMSUBADD132PHZrbkz = 10749 + + VFMSUBADD132PHZrk = 10750 + + VFMSUBADD132PHZrkz = 10751 + + VFMSUBADD132PSYm = 10752 + + VFMSUBADD132PSYr = 10753 + + VFMSUBADD132PSZ128m = 10754 + + VFMSUBADD132PSZ128mb = 10755 + + VFMSUBADD132PSZ128mbk = 10756 + + VFMSUBADD132PSZ128mbkz = 10757 + + VFMSUBADD132PSZ128mk = 10758 + + VFMSUBADD132PSZ128mkz = 10759 + + VFMSUBADD132PSZ128r = 10760 + + VFMSUBADD132PSZ128rk = 10761 + + VFMSUBADD132PSZ128rkz = 10762 + + VFMSUBADD132PSZ256m = 10763 + + VFMSUBADD132PSZ256mb = 10764 + + VFMSUBADD132PSZ256mbk = 10765 + + VFMSUBADD132PSZ256mbkz = 10766 + + VFMSUBADD132PSZ256mk = 10767 + + VFMSUBADD132PSZ256mkz = 10768 + + VFMSUBADD132PSZ256r = 10769 + + VFMSUBADD132PSZ256rk = 10770 + + VFMSUBADD132PSZ256rkz = 10771 + + VFMSUBADD132PSZm = 10772 + + VFMSUBADD132PSZmb = 10773 + + VFMSUBADD132PSZmbk = 10774 + + VFMSUBADD132PSZmbkz = 10775 + + VFMSUBADD132PSZmk = 10776 + + VFMSUBADD132PSZmkz = 10777 + + VFMSUBADD132PSZr = 10778 + + VFMSUBADD132PSZrb = 10779 + + VFMSUBADD132PSZrbk = 10780 + + VFMSUBADD132PSZrbkz = 10781 + + VFMSUBADD132PSZrk = 10782 + + VFMSUBADD132PSZrkz = 10783 + + VFMSUBADD132PSm = 10784 + + VFMSUBADD132PSr = 10785 + + VFMSUBADD213PDYm = 10786 + + VFMSUBADD213PDYr = 10787 + + VFMSUBADD213PDZ128m = 10788 + + VFMSUBADD213PDZ128mb = 10789 + + VFMSUBADD213PDZ128mbk = 10790 + + VFMSUBADD213PDZ128mbkz = 10791 + + VFMSUBADD213PDZ128mk = 10792 + + VFMSUBADD213PDZ128mkz = 10793 + + VFMSUBADD213PDZ128r = 10794 + + VFMSUBADD213PDZ128rk = 10795 + + VFMSUBADD213PDZ128rkz = 10796 + + VFMSUBADD213PDZ256m = 10797 + + VFMSUBADD213PDZ256mb = 10798 + + VFMSUBADD213PDZ256mbk = 10799 + + VFMSUBADD213PDZ256mbkz = 10800 + + VFMSUBADD213PDZ256mk = 10801 + + VFMSUBADD213PDZ256mkz = 10802 + + VFMSUBADD213PDZ256r = 10803 + + VFMSUBADD213PDZ256rk = 10804 + + VFMSUBADD213PDZ256rkz = 10805 + + VFMSUBADD213PDZm = 10806 + + VFMSUBADD213PDZmb = 10807 + + VFMSUBADD213PDZmbk = 10808 + + VFMSUBADD213PDZmbkz = 10809 + + VFMSUBADD213PDZmk = 10810 + + VFMSUBADD213PDZmkz = 10811 + + VFMSUBADD213PDZr = 10812 + + VFMSUBADD213PDZrb = 10813 + + VFMSUBADD213PDZrbk = 10814 + + VFMSUBADD213PDZrbkz = 10815 + + VFMSUBADD213PDZrk = 10816 + + VFMSUBADD213PDZrkz = 10817 + + VFMSUBADD213PDm = 10818 + + VFMSUBADD213PDr = 10819 + + VFMSUBADD213PHZ128m = 10820 + + VFMSUBADD213PHZ128mb = 10821 + + VFMSUBADD213PHZ128mbk = 10822 + + VFMSUBADD213PHZ128mbkz = 10823 + + VFMSUBADD213PHZ128mk = 10824 + + VFMSUBADD213PHZ128mkz = 10825 + + VFMSUBADD213PHZ128r = 10826 + + VFMSUBADD213PHZ128rk = 10827 + + VFMSUBADD213PHZ128rkz = 10828 + + VFMSUBADD213PHZ256m = 10829 + + VFMSUBADD213PHZ256mb = 10830 + + VFMSUBADD213PHZ256mbk = 10831 + + VFMSUBADD213PHZ256mbkz = 10832 + + VFMSUBADD213PHZ256mk = 10833 + + VFMSUBADD213PHZ256mkz = 10834 + + VFMSUBADD213PHZ256r = 10835 + + VFMSUBADD213PHZ256rk = 10836 + + VFMSUBADD213PHZ256rkz = 10837 + + VFMSUBADD213PHZm = 10838 + + VFMSUBADD213PHZmb = 10839 + + VFMSUBADD213PHZmbk = 10840 + + VFMSUBADD213PHZmbkz = 10841 + + VFMSUBADD213PHZmk = 10842 + + VFMSUBADD213PHZmkz = 10843 + + VFMSUBADD213PHZr = 10844 + + VFMSUBADD213PHZrb = 10845 + + VFMSUBADD213PHZrbk = 10846 + + VFMSUBADD213PHZrbkz = 10847 + + VFMSUBADD213PHZrk = 10848 + + VFMSUBADD213PHZrkz = 10849 + + VFMSUBADD213PSYm = 10850 + + VFMSUBADD213PSYr = 10851 + + VFMSUBADD213PSZ128m = 10852 + + VFMSUBADD213PSZ128mb = 10853 + + VFMSUBADD213PSZ128mbk = 10854 + + VFMSUBADD213PSZ128mbkz = 10855 + + VFMSUBADD213PSZ128mk = 10856 + + VFMSUBADD213PSZ128mkz = 10857 + + VFMSUBADD213PSZ128r = 10858 + + VFMSUBADD213PSZ128rk = 10859 + + VFMSUBADD213PSZ128rkz = 10860 + + VFMSUBADD213PSZ256m = 10861 + + VFMSUBADD213PSZ256mb = 10862 + + VFMSUBADD213PSZ256mbk = 10863 + + VFMSUBADD213PSZ256mbkz = 10864 + + VFMSUBADD213PSZ256mk = 10865 + + VFMSUBADD213PSZ256mkz = 10866 + + VFMSUBADD213PSZ256r = 10867 + + VFMSUBADD213PSZ256rk = 10868 + + VFMSUBADD213PSZ256rkz = 10869 + + VFMSUBADD213PSZm = 10870 + + VFMSUBADD213PSZmb = 10871 + + VFMSUBADD213PSZmbk = 10872 + + VFMSUBADD213PSZmbkz = 10873 + + VFMSUBADD213PSZmk = 10874 + + VFMSUBADD213PSZmkz = 10875 + + VFMSUBADD213PSZr = 10876 + + VFMSUBADD213PSZrb = 10877 + + VFMSUBADD213PSZrbk = 10878 + + VFMSUBADD213PSZrbkz = 10879 + + VFMSUBADD213PSZrk = 10880 + + VFMSUBADD213PSZrkz = 10881 + + VFMSUBADD213PSm = 10882 + + VFMSUBADD213PSr = 10883 + + VFMSUBADD231PDYm = 10884 + + VFMSUBADD231PDYr = 10885 + + VFMSUBADD231PDZ128m = 10886 + + VFMSUBADD231PDZ128mb = 10887 + + VFMSUBADD231PDZ128mbk = 10888 + + VFMSUBADD231PDZ128mbkz = 10889 + + VFMSUBADD231PDZ128mk = 10890 + + VFMSUBADD231PDZ128mkz = 10891 + + VFMSUBADD231PDZ128r = 10892 + + VFMSUBADD231PDZ128rk = 10893 + + VFMSUBADD231PDZ128rkz = 10894 + + VFMSUBADD231PDZ256m = 10895 + + VFMSUBADD231PDZ256mb = 10896 + + VFMSUBADD231PDZ256mbk = 10897 + + VFMSUBADD231PDZ256mbkz = 10898 + + VFMSUBADD231PDZ256mk = 10899 + + VFMSUBADD231PDZ256mkz = 10900 + + VFMSUBADD231PDZ256r = 10901 + + VFMSUBADD231PDZ256rk = 10902 + + VFMSUBADD231PDZ256rkz = 10903 + + VFMSUBADD231PDZm = 10904 + + VFMSUBADD231PDZmb = 10905 + + VFMSUBADD231PDZmbk = 10906 + + VFMSUBADD231PDZmbkz = 10907 + + VFMSUBADD231PDZmk = 10908 + + VFMSUBADD231PDZmkz = 10909 + + VFMSUBADD231PDZr = 10910 + + VFMSUBADD231PDZrb = 10911 + + VFMSUBADD231PDZrbk = 10912 + + VFMSUBADD231PDZrbkz = 10913 + + VFMSUBADD231PDZrk = 10914 + + VFMSUBADD231PDZrkz = 10915 + + VFMSUBADD231PDm = 10916 + + VFMSUBADD231PDr = 10917 + + VFMSUBADD231PHZ128m = 10918 + + VFMSUBADD231PHZ128mb = 10919 + + VFMSUBADD231PHZ128mbk = 10920 + + VFMSUBADD231PHZ128mbkz = 10921 + + VFMSUBADD231PHZ128mk = 10922 + + VFMSUBADD231PHZ128mkz = 10923 + + VFMSUBADD231PHZ128r = 10924 + + VFMSUBADD231PHZ128rk = 10925 + + VFMSUBADD231PHZ128rkz = 10926 + + VFMSUBADD231PHZ256m = 10927 + + VFMSUBADD231PHZ256mb = 10928 + + VFMSUBADD231PHZ256mbk = 10929 + + VFMSUBADD231PHZ256mbkz = 10930 + + VFMSUBADD231PHZ256mk = 10931 + + VFMSUBADD231PHZ256mkz = 10932 + + VFMSUBADD231PHZ256r = 10933 + + VFMSUBADD231PHZ256rk = 10934 + + VFMSUBADD231PHZ256rkz = 10935 + + VFMSUBADD231PHZm = 10936 + + VFMSUBADD231PHZmb = 10937 + + VFMSUBADD231PHZmbk = 10938 + + VFMSUBADD231PHZmbkz = 10939 + + VFMSUBADD231PHZmk = 10940 + + VFMSUBADD231PHZmkz = 10941 + + VFMSUBADD231PHZr = 10942 + + VFMSUBADD231PHZrb = 10943 + + VFMSUBADD231PHZrbk = 10944 + + VFMSUBADD231PHZrbkz = 10945 + + VFMSUBADD231PHZrk = 10946 + + VFMSUBADD231PHZrkz = 10947 + + VFMSUBADD231PSYm = 10948 + + VFMSUBADD231PSYr = 10949 + + VFMSUBADD231PSZ128m = 10950 + + VFMSUBADD231PSZ128mb = 10951 + + VFMSUBADD231PSZ128mbk = 10952 + + VFMSUBADD231PSZ128mbkz = 10953 + + VFMSUBADD231PSZ128mk = 10954 + + VFMSUBADD231PSZ128mkz = 10955 + + VFMSUBADD231PSZ128r = 10956 + + VFMSUBADD231PSZ128rk = 10957 + + VFMSUBADD231PSZ128rkz = 10958 + + VFMSUBADD231PSZ256m = 10959 + + VFMSUBADD231PSZ256mb = 10960 + + VFMSUBADD231PSZ256mbk = 10961 + + VFMSUBADD231PSZ256mbkz = 10962 + + VFMSUBADD231PSZ256mk = 10963 + + VFMSUBADD231PSZ256mkz = 10964 + + VFMSUBADD231PSZ256r = 10965 + + VFMSUBADD231PSZ256rk = 10966 + + VFMSUBADD231PSZ256rkz = 10967 + + VFMSUBADD231PSZm = 10968 + + VFMSUBADD231PSZmb = 10969 + + VFMSUBADD231PSZmbk = 10970 + + VFMSUBADD231PSZmbkz = 10971 + + VFMSUBADD231PSZmk = 10972 + + VFMSUBADD231PSZmkz = 10973 + + VFMSUBADD231PSZr = 10974 + + VFMSUBADD231PSZrb = 10975 + + VFMSUBADD231PSZrbk = 10976 + + VFMSUBADD231PSZrbkz = 10977 + + VFMSUBADD231PSZrk = 10978 + + VFMSUBADD231PSZrkz = 10979 + + VFMSUBADD231PSm = 10980 + + VFMSUBADD231PSr = 10981 + + VFMSUBADDPD4Ymr = 10982 + + VFMSUBADDPD4Yrm = 10983 + + VFMSUBADDPD4Yrr = 10984 + + VFMSUBADDPD4Yrr_REV = 10985 + + VFMSUBADDPD4mr = 10986 + + VFMSUBADDPD4rm = 10987 + + VFMSUBADDPD4rr = 10988 + + VFMSUBADDPD4rr_REV = 10989 + + VFMSUBADDPS4Ymr = 10990 + + VFMSUBADDPS4Yrm = 10991 + + VFMSUBADDPS4Yrr = 10992 + + VFMSUBADDPS4Yrr_REV = 10993 + + VFMSUBADDPS4mr = 10994 + + VFMSUBADDPS4rm = 10995 + + VFMSUBADDPS4rr = 10996 + + VFMSUBADDPS4rr_REV = 10997 + + VFMSUBPD4Ymr = 10998 + + VFMSUBPD4Yrm = 10999 + + VFMSUBPD4Yrr = 11000 + + VFMSUBPD4Yrr_REV = 11001 + + VFMSUBPD4mr = 11002 + + VFMSUBPD4rm = 11003 + + VFMSUBPD4rr = 11004 + + VFMSUBPD4rr_REV = 11005 + + VFMSUBPS4Ymr = 11006 + + VFMSUBPS4Yrm = 11007 + + VFMSUBPS4Yrr = 11008 + + VFMSUBPS4Yrr_REV = 11009 + + VFMSUBPS4mr = 11010 + + VFMSUBPS4rm = 11011 + + VFMSUBPS4rr = 11012 + + VFMSUBPS4rr_REV = 11013 + + VFMSUBSD4mr = 11014 + + VFMSUBSD4mr_Int = 11015 + + VFMSUBSD4rm = 11016 + + VFMSUBSD4rm_Int = 11017 + + VFMSUBSD4rr = 11018 + + VFMSUBSD4rr_Int = 11019 + + VFMSUBSD4rr_Int_REV = 11020 + + VFMSUBSD4rr_REV = 11021 + + VFMSUBSS4mr = 11022 + + VFMSUBSS4mr_Int = 11023 + + VFMSUBSS4rm = 11024 + + VFMSUBSS4rm_Int = 11025 + + VFMSUBSS4rr = 11026 + + VFMSUBSS4rr_Int = 11027 + + VFMSUBSS4rr_Int_REV = 11028 + + VFMSUBSS4rr_REV = 11029 + + VFMULCPHZ128rm = 11030 + + VFMULCPHZ128rmb = 11031 + + VFMULCPHZ128rmbk = 11032 + + VFMULCPHZ128rmbkz = 11033 + + VFMULCPHZ128rmk = 11034 + + VFMULCPHZ128rmkz = 11035 + + VFMULCPHZ128rr = 11036 + + VFMULCPHZ128rrk = 11037 + + VFMULCPHZ128rrkz = 11038 + + VFMULCPHZ256rm = 11039 + + VFMULCPHZ256rmb = 11040 + + VFMULCPHZ256rmbk = 11041 + + VFMULCPHZ256rmbkz = 11042 + + VFMULCPHZ256rmk = 11043 + + VFMULCPHZ256rmkz = 11044 + + VFMULCPHZ256rr = 11045 + + VFMULCPHZ256rrk = 11046 + + VFMULCPHZ256rrkz = 11047 + + VFMULCPHZrm = 11048 + + VFMULCPHZrmb = 11049 + + VFMULCPHZrmbk = 11050 + + VFMULCPHZrmbkz = 11051 + + VFMULCPHZrmk = 11052 + + VFMULCPHZrmkz = 11053 + + VFMULCPHZrr = 11054 + + VFMULCPHZrrb = 11055 + + VFMULCPHZrrbk = 11056 + + VFMULCPHZrrbkz = 11057 + + VFMULCPHZrrk = 11058 + + VFMULCPHZrrkz = 11059 + + VFMULCSHZrm = 11060 + + VFMULCSHZrmk = 11061 + + VFMULCSHZrmkz = 11062 + + VFMULCSHZrr = 11063 + + VFMULCSHZrrb = 11064 + + VFMULCSHZrrbk = 11065 + + VFMULCSHZrrbkz = 11066 + + VFMULCSHZrrk = 11067 + + VFMULCSHZrrkz = 11068 + + VFNMADD132BF16Z128m = 11069 + + VFNMADD132BF16Z128mb = 11070 + + VFNMADD132BF16Z128mbk = 11071 + + VFNMADD132BF16Z128mbkz = 11072 + + VFNMADD132BF16Z128mk = 11073 + + VFNMADD132BF16Z128mkz = 11074 + + VFNMADD132BF16Z128r = 11075 + + VFNMADD132BF16Z128rk = 11076 + + VFNMADD132BF16Z128rkz = 11077 + + VFNMADD132BF16Z256m = 11078 + + VFNMADD132BF16Z256mb = 11079 + + VFNMADD132BF16Z256mbk = 11080 + + VFNMADD132BF16Z256mbkz = 11081 + + VFNMADD132BF16Z256mk = 11082 + + VFNMADD132BF16Z256mkz = 11083 + + VFNMADD132BF16Z256r = 11084 + + VFNMADD132BF16Z256rk = 11085 + + VFNMADD132BF16Z256rkz = 11086 + + VFNMADD132BF16Zm = 11087 + + VFNMADD132BF16Zmb = 11088 + + VFNMADD132BF16Zmbk = 11089 + + VFNMADD132BF16Zmbkz = 11090 + + VFNMADD132BF16Zmk = 11091 + + VFNMADD132BF16Zmkz = 11092 + + VFNMADD132BF16Zr = 11093 + + VFNMADD132BF16Zrk = 11094 + + VFNMADD132BF16Zrkz = 11095 + + VFNMADD132PDYm = 11096 + + VFNMADD132PDYr = 11097 + + VFNMADD132PDZ128m = 11098 + + VFNMADD132PDZ128mb = 11099 + + VFNMADD132PDZ128mbk = 11100 + + VFNMADD132PDZ128mbkz = 11101 + + VFNMADD132PDZ128mk = 11102 + + VFNMADD132PDZ128mkz = 11103 + + VFNMADD132PDZ128r = 11104 + + VFNMADD132PDZ128rk = 11105 + + VFNMADD132PDZ128rkz = 11106 + + VFNMADD132PDZ256m = 11107 + + VFNMADD132PDZ256mb = 11108 + + VFNMADD132PDZ256mbk = 11109 + + VFNMADD132PDZ256mbkz = 11110 + + VFNMADD132PDZ256mk = 11111 + + VFNMADD132PDZ256mkz = 11112 + + VFNMADD132PDZ256r = 11113 + + VFNMADD132PDZ256rk = 11114 + + VFNMADD132PDZ256rkz = 11115 + + VFNMADD132PDZm = 11116 + + VFNMADD132PDZmb = 11117 + + VFNMADD132PDZmbk = 11118 + + VFNMADD132PDZmbkz = 11119 + + VFNMADD132PDZmk = 11120 + + VFNMADD132PDZmkz = 11121 + + VFNMADD132PDZr = 11122 + + VFNMADD132PDZrb = 11123 + + VFNMADD132PDZrbk = 11124 + + VFNMADD132PDZrbkz = 11125 + + VFNMADD132PDZrk = 11126 + + VFNMADD132PDZrkz = 11127 + + VFNMADD132PDm = 11128 + + VFNMADD132PDr = 11129 + + VFNMADD132PHZ128m = 11130 + + VFNMADD132PHZ128mb = 11131 + + VFNMADD132PHZ128mbk = 11132 + + VFNMADD132PHZ128mbkz = 11133 + + VFNMADD132PHZ128mk = 11134 + + VFNMADD132PHZ128mkz = 11135 + + VFNMADD132PHZ128r = 11136 + + VFNMADD132PHZ128rk = 11137 + + VFNMADD132PHZ128rkz = 11138 + + VFNMADD132PHZ256m = 11139 + + VFNMADD132PHZ256mb = 11140 + + VFNMADD132PHZ256mbk = 11141 + + VFNMADD132PHZ256mbkz = 11142 + + VFNMADD132PHZ256mk = 11143 + + VFNMADD132PHZ256mkz = 11144 + + VFNMADD132PHZ256r = 11145 + + VFNMADD132PHZ256rk = 11146 + + VFNMADD132PHZ256rkz = 11147 + + VFNMADD132PHZm = 11148 + + VFNMADD132PHZmb = 11149 + + VFNMADD132PHZmbk = 11150 + + VFNMADD132PHZmbkz = 11151 + + VFNMADD132PHZmk = 11152 + + VFNMADD132PHZmkz = 11153 + + VFNMADD132PHZr = 11154 + + VFNMADD132PHZrb = 11155 + + VFNMADD132PHZrbk = 11156 + + VFNMADD132PHZrbkz = 11157 + + VFNMADD132PHZrk = 11158 + + VFNMADD132PHZrkz = 11159 + + VFNMADD132PSYm = 11160 + + VFNMADD132PSYr = 11161 + + VFNMADD132PSZ128m = 11162 + + VFNMADD132PSZ128mb = 11163 + + VFNMADD132PSZ128mbk = 11164 + + VFNMADD132PSZ128mbkz = 11165 + + VFNMADD132PSZ128mk = 11166 + + VFNMADD132PSZ128mkz = 11167 + + VFNMADD132PSZ128r = 11168 + + VFNMADD132PSZ128rk = 11169 + + VFNMADD132PSZ128rkz = 11170 + + VFNMADD132PSZ256m = 11171 + + VFNMADD132PSZ256mb = 11172 + + VFNMADD132PSZ256mbk = 11173 + + VFNMADD132PSZ256mbkz = 11174 + + VFNMADD132PSZ256mk = 11175 + + VFNMADD132PSZ256mkz = 11176 + + VFNMADD132PSZ256r = 11177 + + VFNMADD132PSZ256rk = 11178 + + VFNMADD132PSZ256rkz = 11179 + + VFNMADD132PSZm = 11180 + + VFNMADD132PSZmb = 11181 + + VFNMADD132PSZmbk = 11182 + + VFNMADD132PSZmbkz = 11183 + + VFNMADD132PSZmk = 11184 + + VFNMADD132PSZmkz = 11185 + + VFNMADD132PSZr = 11186 + + VFNMADD132PSZrb = 11187 + + VFNMADD132PSZrbk = 11188 + + VFNMADD132PSZrbkz = 11189 + + VFNMADD132PSZrk = 11190 + + VFNMADD132PSZrkz = 11191 + + VFNMADD132PSm = 11192 + + VFNMADD132PSr = 11193 + + VFNMADD132SDZm = 11194 + + VFNMADD132SDZm_Int = 11195 + + VFNMADD132SDZmk_Int = 11196 + + VFNMADD132SDZmkz_Int = 11197 + + VFNMADD132SDZr = 11198 + + VFNMADD132SDZr_Int = 11199 + + VFNMADD132SDZrb = 11200 + + VFNMADD132SDZrb_Int = 11201 + + VFNMADD132SDZrbk_Int = 11202 + + VFNMADD132SDZrbkz_Int = 11203 + + VFNMADD132SDZrk_Int = 11204 + + VFNMADD132SDZrkz_Int = 11205 + + VFNMADD132SDm = 11206 + + VFNMADD132SDm_Int = 11207 + + VFNMADD132SDr = 11208 + + VFNMADD132SDr_Int = 11209 + + VFNMADD132SHZm = 11210 + + VFNMADD132SHZm_Int = 11211 + + VFNMADD132SHZmk_Int = 11212 + + VFNMADD132SHZmkz_Int = 11213 + + VFNMADD132SHZr = 11214 + + VFNMADD132SHZr_Int = 11215 + + VFNMADD132SHZrb = 11216 + + VFNMADD132SHZrb_Int = 11217 + + VFNMADD132SHZrbk_Int = 11218 + + VFNMADD132SHZrbkz_Int = 11219 + + VFNMADD132SHZrk_Int = 11220 + + VFNMADD132SHZrkz_Int = 11221 + + VFNMADD132SSZm = 11222 + + VFNMADD132SSZm_Int = 11223 + + VFNMADD132SSZmk_Int = 11224 + + VFNMADD132SSZmkz_Int = 11225 + + VFNMADD132SSZr = 11226 + + VFNMADD132SSZr_Int = 11227 + + VFNMADD132SSZrb = 11228 + + VFNMADD132SSZrb_Int = 11229 + + VFNMADD132SSZrbk_Int = 11230 + + VFNMADD132SSZrbkz_Int = 11231 + + VFNMADD132SSZrk_Int = 11232 + + VFNMADD132SSZrkz_Int = 11233 + + VFNMADD132SSm = 11234 + + VFNMADD132SSm_Int = 11235 + + VFNMADD132SSr = 11236 + + VFNMADD132SSr_Int = 11237 + + VFNMADD213BF16Z128m = 11238 + + VFNMADD213BF16Z128mb = 11239 + + VFNMADD213BF16Z128mbk = 11240 + + VFNMADD213BF16Z128mbkz = 11241 + + VFNMADD213BF16Z128mk = 11242 + + VFNMADD213BF16Z128mkz = 11243 + + VFNMADD213BF16Z128r = 11244 + + VFNMADD213BF16Z128rk = 11245 + + VFNMADD213BF16Z128rkz = 11246 + + VFNMADD213BF16Z256m = 11247 + + VFNMADD213BF16Z256mb = 11248 + + VFNMADD213BF16Z256mbk = 11249 + + VFNMADD213BF16Z256mbkz = 11250 + + VFNMADD213BF16Z256mk = 11251 + + VFNMADD213BF16Z256mkz = 11252 + + VFNMADD213BF16Z256r = 11253 + + VFNMADD213BF16Z256rk = 11254 + + VFNMADD213BF16Z256rkz = 11255 + + VFNMADD213BF16Zm = 11256 + + VFNMADD213BF16Zmb = 11257 + + VFNMADD213BF16Zmbk = 11258 + + VFNMADD213BF16Zmbkz = 11259 + + VFNMADD213BF16Zmk = 11260 + + VFNMADD213BF16Zmkz = 11261 + + VFNMADD213BF16Zr = 11262 + + VFNMADD213BF16Zrk = 11263 + + VFNMADD213BF16Zrkz = 11264 + + VFNMADD213PDYm = 11265 + + VFNMADD213PDYr = 11266 + + VFNMADD213PDZ128m = 11267 + + VFNMADD213PDZ128mb = 11268 + + VFNMADD213PDZ128mbk = 11269 + + VFNMADD213PDZ128mbkz = 11270 + + VFNMADD213PDZ128mk = 11271 + + VFNMADD213PDZ128mkz = 11272 + + VFNMADD213PDZ128r = 11273 + + VFNMADD213PDZ128rk = 11274 + + VFNMADD213PDZ128rkz = 11275 + + VFNMADD213PDZ256m = 11276 + + VFNMADD213PDZ256mb = 11277 + + VFNMADD213PDZ256mbk = 11278 + + VFNMADD213PDZ256mbkz = 11279 + + VFNMADD213PDZ256mk = 11280 + + VFNMADD213PDZ256mkz = 11281 + + VFNMADD213PDZ256r = 11282 + + VFNMADD213PDZ256rk = 11283 + + VFNMADD213PDZ256rkz = 11284 + + VFNMADD213PDZm = 11285 + + VFNMADD213PDZmb = 11286 + + VFNMADD213PDZmbk = 11287 + + VFNMADD213PDZmbkz = 11288 + + VFNMADD213PDZmk = 11289 + + VFNMADD213PDZmkz = 11290 + + VFNMADD213PDZr = 11291 + + VFNMADD213PDZrb = 11292 + + VFNMADD213PDZrbk = 11293 + + VFNMADD213PDZrbkz = 11294 + + VFNMADD213PDZrk = 11295 + + VFNMADD213PDZrkz = 11296 + + VFNMADD213PDm = 11297 + + VFNMADD213PDr = 11298 + + VFNMADD213PHZ128m = 11299 + + VFNMADD213PHZ128mb = 11300 + + VFNMADD213PHZ128mbk = 11301 + + VFNMADD213PHZ128mbkz = 11302 + + VFNMADD213PHZ128mk = 11303 + + VFNMADD213PHZ128mkz = 11304 + + VFNMADD213PHZ128r = 11305 + + VFNMADD213PHZ128rk = 11306 + + VFNMADD213PHZ128rkz = 11307 + + VFNMADD213PHZ256m = 11308 + + VFNMADD213PHZ256mb = 11309 + + VFNMADD213PHZ256mbk = 11310 + + VFNMADD213PHZ256mbkz = 11311 + + VFNMADD213PHZ256mk = 11312 + + VFNMADD213PHZ256mkz = 11313 + + VFNMADD213PHZ256r = 11314 + + VFNMADD213PHZ256rk = 11315 + + VFNMADD213PHZ256rkz = 11316 + + VFNMADD213PHZm = 11317 + + VFNMADD213PHZmb = 11318 + + VFNMADD213PHZmbk = 11319 + + VFNMADD213PHZmbkz = 11320 + + VFNMADD213PHZmk = 11321 + + VFNMADD213PHZmkz = 11322 + + VFNMADD213PHZr = 11323 + + VFNMADD213PHZrb = 11324 + + VFNMADD213PHZrbk = 11325 + + VFNMADD213PHZrbkz = 11326 + + VFNMADD213PHZrk = 11327 + + VFNMADD213PHZrkz = 11328 + + VFNMADD213PSYm = 11329 + + VFNMADD213PSYr = 11330 + + VFNMADD213PSZ128m = 11331 + + VFNMADD213PSZ128mb = 11332 + + VFNMADD213PSZ128mbk = 11333 + + VFNMADD213PSZ128mbkz = 11334 + + VFNMADD213PSZ128mk = 11335 + + VFNMADD213PSZ128mkz = 11336 + + VFNMADD213PSZ128r = 11337 + + VFNMADD213PSZ128rk = 11338 + + VFNMADD213PSZ128rkz = 11339 + + VFNMADD213PSZ256m = 11340 + + VFNMADD213PSZ256mb = 11341 + + VFNMADD213PSZ256mbk = 11342 + + VFNMADD213PSZ256mbkz = 11343 + + VFNMADD213PSZ256mk = 11344 + + VFNMADD213PSZ256mkz = 11345 + + VFNMADD213PSZ256r = 11346 + + VFNMADD213PSZ256rk = 11347 + + VFNMADD213PSZ256rkz = 11348 + + VFNMADD213PSZm = 11349 + + VFNMADD213PSZmb = 11350 + + VFNMADD213PSZmbk = 11351 + + VFNMADD213PSZmbkz = 11352 + + VFNMADD213PSZmk = 11353 + + VFNMADD213PSZmkz = 11354 + + VFNMADD213PSZr = 11355 + + VFNMADD213PSZrb = 11356 + + VFNMADD213PSZrbk = 11357 + + VFNMADD213PSZrbkz = 11358 + + VFNMADD213PSZrk = 11359 + + VFNMADD213PSZrkz = 11360 + + VFNMADD213PSm = 11361 + + VFNMADD213PSr = 11362 + + VFNMADD213SDZm = 11363 + + VFNMADD213SDZm_Int = 11364 + + VFNMADD213SDZmk_Int = 11365 + + VFNMADD213SDZmkz_Int = 11366 + + VFNMADD213SDZr = 11367 + + VFNMADD213SDZr_Int = 11368 + + VFNMADD213SDZrb = 11369 + + VFNMADD213SDZrb_Int = 11370 + + VFNMADD213SDZrbk_Int = 11371 + + VFNMADD213SDZrbkz_Int = 11372 + + VFNMADD213SDZrk_Int = 11373 + + VFNMADD213SDZrkz_Int = 11374 + + VFNMADD213SDm = 11375 + + VFNMADD213SDm_Int = 11376 + + VFNMADD213SDr = 11377 + + VFNMADD213SDr_Int = 11378 + + VFNMADD213SHZm = 11379 + + VFNMADD213SHZm_Int = 11380 + + VFNMADD213SHZmk_Int = 11381 + + VFNMADD213SHZmkz_Int = 11382 + + VFNMADD213SHZr = 11383 + + VFNMADD213SHZr_Int = 11384 + + VFNMADD213SHZrb = 11385 + + VFNMADD213SHZrb_Int = 11386 + + VFNMADD213SHZrbk_Int = 11387 + + VFNMADD213SHZrbkz_Int = 11388 + + VFNMADD213SHZrk_Int = 11389 + + VFNMADD213SHZrkz_Int = 11390 + + VFNMADD213SSZm = 11391 + + VFNMADD213SSZm_Int = 11392 + + VFNMADD213SSZmk_Int = 11393 + + VFNMADD213SSZmkz_Int = 11394 + + VFNMADD213SSZr = 11395 + + VFNMADD213SSZr_Int = 11396 + + VFNMADD213SSZrb = 11397 + + VFNMADD213SSZrb_Int = 11398 + + VFNMADD213SSZrbk_Int = 11399 + + VFNMADD213SSZrbkz_Int = 11400 + + VFNMADD213SSZrk_Int = 11401 + + VFNMADD213SSZrkz_Int = 11402 + + VFNMADD213SSm = 11403 + + VFNMADD213SSm_Int = 11404 + + VFNMADD213SSr = 11405 + + VFNMADD213SSr_Int = 11406 + + VFNMADD231BF16Z128m = 11407 + + VFNMADD231BF16Z128mb = 11408 + + VFNMADD231BF16Z128mbk = 11409 + + VFNMADD231BF16Z128mbkz = 11410 + + VFNMADD231BF16Z128mk = 11411 + + VFNMADD231BF16Z128mkz = 11412 + + VFNMADD231BF16Z128r = 11413 + + VFNMADD231BF16Z128rk = 11414 + + VFNMADD231BF16Z128rkz = 11415 + + VFNMADD231BF16Z256m = 11416 + + VFNMADD231BF16Z256mb = 11417 + + VFNMADD231BF16Z256mbk = 11418 + + VFNMADD231BF16Z256mbkz = 11419 + + VFNMADD231BF16Z256mk = 11420 + + VFNMADD231BF16Z256mkz = 11421 + + VFNMADD231BF16Z256r = 11422 + + VFNMADD231BF16Z256rk = 11423 + + VFNMADD231BF16Z256rkz = 11424 + + VFNMADD231BF16Zm = 11425 + + VFNMADD231BF16Zmb = 11426 + + VFNMADD231BF16Zmbk = 11427 + + VFNMADD231BF16Zmbkz = 11428 + + VFNMADD231BF16Zmk = 11429 + + VFNMADD231BF16Zmkz = 11430 + + VFNMADD231BF16Zr = 11431 + + VFNMADD231BF16Zrk = 11432 + + VFNMADD231BF16Zrkz = 11433 + + VFNMADD231PDYm = 11434 + + VFNMADD231PDYr = 11435 + + VFNMADD231PDZ128m = 11436 + + VFNMADD231PDZ128mb = 11437 + + VFNMADD231PDZ128mbk = 11438 + + VFNMADD231PDZ128mbkz = 11439 + + VFNMADD231PDZ128mk = 11440 + + VFNMADD231PDZ128mkz = 11441 + + VFNMADD231PDZ128r = 11442 + + VFNMADD231PDZ128rk = 11443 + + VFNMADD231PDZ128rkz = 11444 + + VFNMADD231PDZ256m = 11445 + + VFNMADD231PDZ256mb = 11446 + + VFNMADD231PDZ256mbk = 11447 + + VFNMADD231PDZ256mbkz = 11448 + + VFNMADD231PDZ256mk = 11449 + + VFNMADD231PDZ256mkz = 11450 + + VFNMADD231PDZ256r = 11451 + + VFNMADD231PDZ256rk = 11452 + + VFNMADD231PDZ256rkz = 11453 + + VFNMADD231PDZm = 11454 + + VFNMADD231PDZmb = 11455 + + VFNMADD231PDZmbk = 11456 + + VFNMADD231PDZmbkz = 11457 + + VFNMADD231PDZmk = 11458 + + VFNMADD231PDZmkz = 11459 + + VFNMADD231PDZr = 11460 + + VFNMADD231PDZrb = 11461 + + VFNMADD231PDZrbk = 11462 + + VFNMADD231PDZrbkz = 11463 + + VFNMADD231PDZrk = 11464 + + VFNMADD231PDZrkz = 11465 + + VFNMADD231PDm = 11466 + + VFNMADD231PDr = 11467 + + VFNMADD231PHZ128m = 11468 + + VFNMADD231PHZ128mb = 11469 + + VFNMADD231PHZ128mbk = 11470 + + VFNMADD231PHZ128mbkz = 11471 + + VFNMADD231PHZ128mk = 11472 + + VFNMADD231PHZ128mkz = 11473 + + VFNMADD231PHZ128r = 11474 + + VFNMADD231PHZ128rk = 11475 + + VFNMADD231PHZ128rkz = 11476 + + VFNMADD231PHZ256m = 11477 + + VFNMADD231PHZ256mb = 11478 + + VFNMADD231PHZ256mbk = 11479 + + VFNMADD231PHZ256mbkz = 11480 + + VFNMADD231PHZ256mk = 11481 + + VFNMADD231PHZ256mkz = 11482 + + VFNMADD231PHZ256r = 11483 + + VFNMADD231PHZ256rk = 11484 + + VFNMADD231PHZ256rkz = 11485 + + VFNMADD231PHZm = 11486 + + VFNMADD231PHZmb = 11487 + + VFNMADD231PHZmbk = 11488 + + VFNMADD231PHZmbkz = 11489 + + VFNMADD231PHZmk = 11490 + + VFNMADD231PHZmkz = 11491 + + VFNMADD231PHZr = 11492 + + VFNMADD231PHZrb = 11493 + + VFNMADD231PHZrbk = 11494 + + VFNMADD231PHZrbkz = 11495 + + VFNMADD231PHZrk = 11496 + + VFNMADD231PHZrkz = 11497 + + VFNMADD231PSYm = 11498 + + VFNMADD231PSYr = 11499 + + VFNMADD231PSZ128m = 11500 + + VFNMADD231PSZ128mb = 11501 + + VFNMADD231PSZ128mbk = 11502 + + VFNMADD231PSZ128mbkz = 11503 + + VFNMADD231PSZ128mk = 11504 + + VFNMADD231PSZ128mkz = 11505 + + VFNMADD231PSZ128r = 11506 + + VFNMADD231PSZ128rk = 11507 + + VFNMADD231PSZ128rkz = 11508 + + VFNMADD231PSZ256m = 11509 + + VFNMADD231PSZ256mb = 11510 + + VFNMADD231PSZ256mbk = 11511 + + VFNMADD231PSZ256mbkz = 11512 + + VFNMADD231PSZ256mk = 11513 + + VFNMADD231PSZ256mkz = 11514 + + VFNMADD231PSZ256r = 11515 + + VFNMADD231PSZ256rk = 11516 + + VFNMADD231PSZ256rkz = 11517 + + VFNMADD231PSZm = 11518 + + VFNMADD231PSZmb = 11519 + + VFNMADD231PSZmbk = 11520 + + VFNMADD231PSZmbkz = 11521 + + VFNMADD231PSZmk = 11522 + + VFNMADD231PSZmkz = 11523 + + VFNMADD231PSZr = 11524 + + VFNMADD231PSZrb = 11525 + + VFNMADD231PSZrbk = 11526 + + VFNMADD231PSZrbkz = 11527 + + VFNMADD231PSZrk = 11528 + + VFNMADD231PSZrkz = 11529 + + VFNMADD231PSm = 11530 + + VFNMADD231PSr = 11531 + + VFNMADD231SDZm = 11532 + + VFNMADD231SDZm_Int = 11533 + + VFNMADD231SDZmk_Int = 11534 + + VFNMADD231SDZmkz_Int = 11535 + + VFNMADD231SDZr = 11536 + + VFNMADD231SDZr_Int = 11537 + + VFNMADD231SDZrb = 11538 + + VFNMADD231SDZrb_Int = 11539 + + VFNMADD231SDZrbk_Int = 11540 + + VFNMADD231SDZrbkz_Int = 11541 + + VFNMADD231SDZrk_Int = 11542 + + VFNMADD231SDZrkz_Int = 11543 + + VFNMADD231SDm = 11544 + + VFNMADD231SDm_Int = 11545 + + VFNMADD231SDr = 11546 + + VFNMADD231SDr_Int = 11547 + + VFNMADD231SHZm = 11548 + + VFNMADD231SHZm_Int = 11549 + + VFNMADD231SHZmk_Int = 11550 + + VFNMADD231SHZmkz_Int = 11551 + + VFNMADD231SHZr = 11552 + + VFNMADD231SHZr_Int = 11553 + + VFNMADD231SHZrb = 11554 + + VFNMADD231SHZrb_Int = 11555 + + VFNMADD231SHZrbk_Int = 11556 + + VFNMADD231SHZrbkz_Int = 11557 + + VFNMADD231SHZrk_Int = 11558 + + VFNMADD231SHZrkz_Int = 11559 + + VFNMADD231SSZm = 11560 + + VFNMADD231SSZm_Int = 11561 + + VFNMADD231SSZmk_Int = 11562 + + VFNMADD231SSZmkz_Int = 11563 + + VFNMADD231SSZr = 11564 + + VFNMADD231SSZr_Int = 11565 + + VFNMADD231SSZrb = 11566 + + VFNMADD231SSZrb_Int = 11567 + + VFNMADD231SSZrbk_Int = 11568 + + VFNMADD231SSZrbkz_Int = 11569 + + VFNMADD231SSZrk_Int = 11570 + + VFNMADD231SSZrkz_Int = 11571 + + VFNMADD231SSm = 11572 + + VFNMADD231SSm_Int = 11573 + + VFNMADD231SSr = 11574 + + VFNMADD231SSr_Int = 11575 + + VFNMADDPD4Ymr = 11576 + + VFNMADDPD4Yrm = 11577 + + VFNMADDPD4Yrr = 11578 + + VFNMADDPD4Yrr_REV = 11579 + + VFNMADDPD4mr = 11580 + + VFNMADDPD4rm = 11581 + + VFNMADDPD4rr = 11582 + + VFNMADDPD4rr_REV = 11583 + + VFNMADDPS4Ymr = 11584 + + VFNMADDPS4Yrm = 11585 + + VFNMADDPS4Yrr = 11586 + + VFNMADDPS4Yrr_REV = 11587 + + VFNMADDPS4mr = 11588 + + VFNMADDPS4rm = 11589 + + VFNMADDPS4rr = 11590 + + VFNMADDPS4rr_REV = 11591 + + VFNMADDSD4mr = 11592 + + VFNMADDSD4mr_Int = 11593 + + VFNMADDSD4rm = 11594 + + VFNMADDSD4rm_Int = 11595 + + VFNMADDSD4rr = 11596 + + VFNMADDSD4rr_Int = 11597 + + VFNMADDSD4rr_Int_REV = 11598 + + VFNMADDSD4rr_REV = 11599 + + VFNMADDSS4mr = 11600 + + VFNMADDSS4mr_Int = 11601 + + VFNMADDSS4rm = 11602 + + VFNMADDSS4rm_Int = 11603 + + VFNMADDSS4rr = 11604 + + VFNMADDSS4rr_Int = 11605 + + VFNMADDSS4rr_Int_REV = 11606 + + VFNMADDSS4rr_REV = 11607 + + VFNMSUB132BF16Z128m = 11608 + + VFNMSUB132BF16Z128mb = 11609 + + VFNMSUB132BF16Z128mbk = 11610 + + VFNMSUB132BF16Z128mbkz = 11611 + + VFNMSUB132BF16Z128mk = 11612 + + VFNMSUB132BF16Z128mkz = 11613 + + VFNMSUB132BF16Z128r = 11614 + + VFNMSUB132BF16Z128rk = 11615 + + VFNMSUB132BF16Z128rkz = 11616 + + VFNMSUB132BF16Z256m = 11617 + + VFNMSUB132BF16Z256mb = 11618 + + VFNMSUB132BF16Z256mbk = 11619 + + VFNMSUB132BF16Z256mbkz = 11620 + + VFNMSUB132BF16Z256mk = 11621 + + VFNMSUB132BF16Z256mkz = 11622 + + VFNMSUB132BF16Z256r = 11623 + + VFNMSUB132BF16Z256rk = 11624 + + VFNMSUB132BF16Z256rkz = 11625 + + VFNMSUB132BF16Zm = 11626 + + VFNMSUB132BF16Zmb = 11627 + + VFNMSUB132BF16Zmbk = 11628 + + VFNMSUB132BF16Zmbkz = 11629 + + VFNMSUB132BF16Zmk = 11630 + + VFNMSUB132BF16Zmkz = 11631 + + VFNMSUB132BF16Zr = 11632 + + VFNMSUB132BF16Zrk = 11633 + + VFNMSUB132BF16Zrkz = 11634 + + VFNMSUB132PDYm = 11635 + + VFNMSUB132PDYr = 11636 + + VFNMSUB132PDZ128m = 11637 + + VFNMSUB132PDZ128mb = 11638 + + VFNMSUB132PDZ128mbk = 11639 + + VFNMSUB132PDZ128mbkz = 11640 + + VFNMSUB132PDZ128mk = 11641 + + VFNMSUB132PDZ128mkz = 11642 + + VFNMSUB132PDZ128r = 11643 + + VFNMSUB132PDZ128rk = 11644 + + VFNMSUB132PDZ128rkz = 11645 + + VFNMSUB132PDZ256m = 11646 + + VFNMSUB132PDZ256mb = 11647 + + VFNMSUB132PDZ256mbk = 11648 + + VFNMSUB132PDZ256mbkz = 11649 + + VFNMSUB132PDZ256mk = 11650 + + VFNMSUB132PDZ256mkz = 11651 + + VFNMSUB132PDZ256r = 11652 + + VFNMSUB132PDZ256rk = 11653 + + VFNMSUB132PDZ256rkz = 11654 + + VFNMSUB132PDZm = 11655 + + VFNMSUB132PDZmb = 11656 + + VFNMSUB132PDZmbk = 11657 + + VFNMSUB132PDZmbkz = 11658 + + VFNMSUB132PDZmk = 11659 + + VFNMSUB132PDZmkz = 11660 + + VFNMSUB132PDZr = 11661 + + VFNMSUB132PDZrb = 11662 + + VFNMSUB132PDZrbk = 11663 + + VFNMSUB132PDZrbkz = 11664 + + VFNMSUB132PDZrk = 11665 + + VFNMSUB132PDZrkz = 11666 + + VFNMSUB132PDm = 11667 + + VFNMSUB132PDr = 11668 + + VFNMSUB132PHZ128m = 11669 + + VFNMSUB132PHZ128mb = 11670 + + VFNMSUB132PHZ128mbk = 11671 + + VFNMSUB132PHZ128mbkz = 11672 + + VFNMSUB132PHZ128mk = 11673 + + VFNMSUB132PHZ128mkz = 11674 + + VFNMSUB132PHZ128r = 11675 + + VFNMSUB132PHZ128rk = 11676 + + VFNMSUB132PHZ128rkz = 11677 + + VFNMSUB132PHZ256m = 11678 + + VFNMSUB132PHZ256mb = 11679 + + VFNMSUB132PHZ256mbk = 11680 + + VFNMSUB132PHZ256mbkz = 11681 + + VFNMSUB132PHZ256mk = 11682 + + VFNMSUB132PHZ256mkz = 11683 + + VFNMSUB132PHZ256r = 11684 + + VFNMSUB132PHZ256rk = 11685 + + VFNMSUB132PHZ256rkz = 11686 + + VFNMSUB132PHZm = 11687 + + VFNMSUB132PHZmb = 11688 + + VFNMSUB132PHZmbk = 11689 + + VFNMSUB132PHZmbkz = 11690 + + VFNMSUB132PHZmk = 11691 + + VFNMSUB132PHZmkz = 11692 + + VFNMSUB132PHZr = 11693 + + VFNMSUB132PHZrb = 11694 + + VFNMSUB132PHZrbk = 11695 + + VFNMSUB132PHZrbkz = 11696 + + VFNMSUB132PHZrk = 11697 + + VFNMSUB132PHZrkz = 11698 + + VFNMSUB132PSYm = 11699 + + VFNMSUB132PSYr = 11700 + + VFNMSUB132PSZ128m = 11701 + + VFNMSUB132PSZ128mb = 11702 + + VFNMSUB132PSZ128mbk = 11703 + + VFNMSUB132PSZ128mbkz = 11704 + + VFNMSUB132PSZ128mk = 11705 + + VFNMSUB132PSZ128mkz = 11706 + + VFNMSUB132PSZ128r = 11707 + + VFNMSUB132PSZ128rk = 11708 + + VFNMSUB132PSZ128rkz = 11709 + + VFNMSUB132PSZ256m = 11710 + + VFNMSUB132PSZ256mb = 11711 + + VFNMSUB132PSZ256mbk = 11712 + + VFNMSUB132PSZ256mbkz = 11713 + + VFNMSUB132PSZ256mk = 11714 + + VFNMSUB132PSZ256mkz = 11715 + + VFNMSUB132PSZ256r = 11716 + + VFNMSUB132PSZ256rk = 11717 + + VFNMSUB132PSZ256rkz = 11718 + + VFNMSUB132PSZm = 11719 + + VFNMSUB132PSZmb = 11720 + + VFNMSUB132PSZmbk = 11721 + + VFNMSUB132PSZmbkz = 11722 + + VFNMSUB132PSZmk = 11723 + + VFNMSUB132PSZmkz = 11724 + + VFNMSUB132PSZr = 11725 + + VFNMSUB132PSZrb = 11726 + + VFNMSUB132PSZrbk = 11727 + + VFNMSUB132PSZrbkz = 11728 + + VFNMSUB132PSZrk = 11729 + + VFNMSUB132PSZrkz = 11730 + + VFNMSUB132PSm = 11731 + + VFNMSUB132PSr = 11732 + + VFNMSUB132SDZm = 11733 + + VFNMSUB132SDZm_Int = 11734 + + VFNMSUB132SDZmk_Int = 11735 + + VFNMSUB132SDZmkz_Int = 11736 + + VFNMSUB132SDZr = 11737 + + VFNMSUB132SDZr_Int = 11738 + + VFNMSUB132SDZrb = 11739 + + VFNMSUB132SDZrb_Int = 11740 + + VFNMSUB132SDZrbk_Int = 11741 + + VFNMSUB132SDZrbkz_Int = 11742 + + VFNMSUB132SDZrk_Int = 11743 + + VFNMSUB132SDZrkz_Int = 11744 + + VFNMSUB132SDm = 11745 + + VFNMSUB132SDm_Int = 11746 + + VFNMSUB132SDr = 11747 + + VFNMSUB132SDr_Int = 11748 + + VFNMSUB132SHZm = 11749 + + VFNMSUB132SHZm_Int = 11750 + + VFNMSUB132SHZmk_Int = 11751 + + VFNMSUB132SHZmkz_Int = 11752 + + VFNMSUB132SHZr = 11753 + + VFNMSUB132SHZr_Int = 11754 + + VFNMSUB132SHZrb = 11755 + + VFNMSUB132SHZrb_Int = 11756 + + VFNMSUB132SHZrbk_Int = 11757 + + VFNMSUB132SHZrbkz_Int = 11758 + + VFNMSUB132SHZrk_Int = 11759 + + VFNMSUB132SHZrkz_Int = 11760 + + VFNMSUB132SSZm = 11761 + + VFNMSUB132SSZm_Int = 11762 + + VFNMSUB132SSZmk_Int = 11763 + + VFNMSUB132SSZmkz_Int = 11764 + + VFNMSUB132SSZr = 11765 + + VFNMSUB132SSZr_Int = 11766 + + VFNMSUB132SSZrb = 11767 + + VFNMSUB132SSZrb_Int = 11768 + + VFNMSUB132SSZrbk_Int = 11769 + + VFNMSUB132SSZrbkz_Int = 11770 + + VFNMSUB132SSZrk_Int = 11771 + + VFNMSUB132SSZrkz_Int = 11772 + + VFNMSUB132SSm = 11773 + + VFNMSUB132SSm_Int = 11774 + + VFNMSUB132SSr = 11775 + + VFNMSUB132SSr_Int = 11776 + + VFNMSUB213BF16Z128m = 11777 + + VFNMSUB213BF16Z128mb = 11778 + + VFNMSUB213BF16Z128mbk = 11779 + + VFNMSUB213BF16Z128mbkz = 11780 + + VFNMSUB213BF16Z128mk = 11781 + + VFNMSUB213BF16Z128mkz = 11782 + + VFNMSUB213BF16Z128r = 11783 + + VFNMSUB213BF16Z128rk = 11784 + + VFNMSUB213BF16Z128rkz = 11785 + + VFNMSUB213BF16Z256m = 11786 + + VFNMSUB213BF16Z256mb = 11787 + + VFNMSUB213BF16Z256mbk = 11788 + + VFNMSUB213BF16Z256mbkz = 11789 + + VFNMSUB213BF16Z256mk = 11790 + + VFNMSUB213BF16Z256mkz = 11791 + + VFNMSUB213BF16Z256r = 11792 + + VFNMSUB213BF16Z256rk = 11793 + + VFNMSUB213BF16Z256rkz = 11794 + + VFNMSUB213BF16Zm = 11795 + + VFNMSUB213BF16Zmb = 11796 + + VFNMSUB213BF16Zmbk = 11797 + + VFNMSUB213BF16Zmbkz = 11798 + + VFNMSUB213BF16Zmk = 11799 + + VFNMSUB213BF16Zmkz = 11800 + + VFNMSUB213BF16Zr = 11801 + + VFNMSUB213BF16Zrk = 11802 + + VFNMSUB213BF16Zrkz = 11803 + + VFNMSUB213PDYm = 11804 + + VFNMSUB213PDYr = 11805 + + VFNMSUB213PDZ128m = 11806 + + VFNMSUB213PDZ128mb = 11807 + + VFNMSUB213PDZ128mbk = 11808 + + VFNMSUB213PDZ128mbkz = 11809 + + VFNMSUB213PDZ128mk = 11810 + + VFNMSUB213PDZ128mkz = 11811 + + VFNMSUB213PDZ128r = 11812 + + VFNMSUB213PDZ128rk = 11813 + + VFNMSUB213PDZ128rkz = 11814 + + VFNMSUB213PDZ256m = 11815 + + VFNMSUB213PDZ256mb = 11816 + + VFNMSUB213PDZ256mbk = 11817 + + VFNMSUB213PDZ256mbkz = 11818 + + VFNMSUB213PDZ256mk = 11819 + + VFNMSUB213PDZ256mkz = 11820 + + VFNMSUB213PDZ256r = 11821 + + VFNMSUB213PDZ256rk = 11822 + + VFNMSUB213PDZ256rkz = 11823 + + VFNMSUB213PDZm = 11824 + + VFNMSUB213PDZmb = 11825 + + VFNMSUB213PDZmbk = 11826 + + VFNMSUB213PDZmbkz = 11827 + + VFNMSUB213PDZmk = 11828 + + VFNMSUB213PDZmkz = 11829 + + VFNMSUB213PDZr = 11830 + + VFNMSUB213PDZrb = 11831 + + VFNMSUB213PDZrbk = 11832 + + VFNMSUB213PDZrbkz = 11833 + + VFNMSUB213PDZrk = 11834 + + VFNMSUB213PDZrkz = 11835 + + VFNMSUB213PDm = 11836 + + VFNMSUB213PDr = 11837 + + VFNMSUB213PHZ128m = 11838 + + VFNMSUB213PHZ128mb = 11839 + + VFNMSUB213PHZ128mbk = 11840 + + VFNMSUB213PHZ128mbkz = 11841 + + VFNMSUB213PHZ128mk = 11842 + + VFNMSUB213PHZ128mkz = 11843 + + VFNMSUB213PHZ128r = 11844 + + VFNMSUB213PHZ128rk = 11845 + + VFNMSUB213PHZ128rkz = 11846 + + VFNMSUB213PHZ256m = 11847 + + VFNMSUB213PHZ256mb = 11848 + + VFNMSUB213PHZ256mbk = 11849 + + VFNMSUB213PHZ256mbkz = 11850 + + VFNMSUB213PHZ256mk = 11851 + + VFNMSUB213PHZ256mkz = 11852 + + VFNMSUB213PHZ256r = 11853 + + VFNMSUB213PHZ256rk = 11854 + + VFNMSUB213PHZ256rkz = 11855 + + VFNMSUB213PHZm = 11856 + + VFNMSUB213PHZmb = 11857 + + VFNMSUB213PHZmbk = 11858 + + VFNMSUB213PHZmbkz = 11859 + + VFNMSUB213PHZmk = 11860 + + VFNMSUB213PHZmkz = 11861 + + VFNMSUB213PHZr = 11862 + + VFNMSUB213PHZrb = 11863 + + VFNMSUB213PHZrbk = 11864 + + VFNMSUB213PHZrbkz = 11865 + + VFNMSUB213PHZrk = 11866 + + VFNMSUB213PHZrkz = 11867 + + VFNMSUB213PSYm = 11868 + + VFNMSUB213PSYr = 11869 + + VFNMSUB213PSZ128m = 11870 + + VFNMSUB213PSZ128mb = 11871 + + VFNMSUB213PSZ128mbk = 11872 + + VFNMSUB213PSZ128mbkz = 11873 + + VFNMSUB213PSZ128mk = 11874 + + VFNMSUB213PSZ128mkz = 11875 + + VFNMSUB213PSZ128r = 11876 + + VFNMSUB213PSZ128rk = 11877 + + VFNMSUB213PSZ128rkz = 11878 + + VFNMSUB213PSZ256m = 11879 + + VFNMSUB213PSZ256mb = 11880 + + VFNMSUB213PSZ256mbk = 11881 + + VFNMSUB213PSZ256mbkz = 11882 + + VFNMSUB213PSZ256mk = 11883 + + VFNMSUB213PSZ256mkz = 11884 + + VFNMSUB213PSZ256r = 11885 + + VFNMSUB213PSZ256rk = 11886 + + VFNMSUB213PSZ256rkz = 11887 + + VFNMSUB213PSZm = 11888 + + VFNMSUB213PSZmb = 11889 + + VFNMSUB213PSZmbk = 11890 + + VFNMSUB213PSZmbkz = 11891 + + VFNMSUB213PSZmk = 11892 + + VFNMSUB213PSZmkz = 11893 + + VFNMSUB213PSZr = 11894 + + VFNMSUB213PSZrb = 11895 + + VFNMSUB213PSZrbk = 11896 + + VFNMSUB213PSZrbkz = 11897 + + VFNMSUB213PSZrk = 11898 + + VFNMSUB213PSZrkz = 11899 + + VFNMSUB213PSm = 11900 + + VFNMSUB213PSr = 11901 + + VFNMSUB213SDZm = 11902 + + VFNMSUB213SDZm_Int = 11903 + + VFNMSUB213SDZmk_Int = 11904 + + VFNMSUB213SDZmkz_Int = 11905 + + VFNMSUB213SDZr = 11906 + + VFNMSUB213SDZr_Int = 11907 + + VFNMSUB213SDZrb = 11908 + + VFNMSUB213SDZrb_Int = 11909 + + VFNMSUB213SDZrbk_Int = 11910 + + VFNMSUB213SDZrbkz_Int = 11911 + + VFNMSUB213SDZrk_Int = 11912 + + VFNMSUB213SDZrkz_Int = 11913 + + VFNMSUB213SDm = 11914 + + VFNMSUB213SDm_Int = 11915 + + VFNMSUB213SDr = 11916 + + VFNMSUB213SDr_Int = 11917 + + VFNMSUB213SHZm = 11918 + + VFNMSUB213SHZm_Int = 11919 + + VFNMSUB213SHZmk_Int = 11920 + + VFNMSUB213SHZmkz_Int = 11921 + + VFNMSUB213SHZr = 11922 + + VFNMSUB213SHZr_Int = 11923 + + VFNMSUB213SHZrb = 11924 + + VFNMSUB213SHZrb_Int = 11925 + + VFNMSUB213SHZrbk_Int = 11926 + + VFNMSUB213SHZrbkz_Int = 11927 + + VFNMSUB213SHZrk_Int = 11928 + + VFNMSUB213SHZrkz_Int = 11929 + + VFNMSUB213SSZm = 11930 + + VFNMSUB213SSZm_Int = 11931 + + VFNMSUB213SSZmk_Int = 11932 + + VFNMSUB213SSZmkz_Int = 11933 + + VFNMSUB213SSZr = 11934 + + VFNMSUB213SSZr_Int = 11935 + + VFNMSUB213SSZrb = 11936 + + VFNMSUB213SSZrb_Int = 11937 + + VFNMSUB213SSZrbk_Int = 11938 + + VFNMSUB213SSZrbkz_Int = 11939 + + VFNMSUB213SSZrk_Int = 11940 + + VFNMSUB213SSZrkz_Int = 11941 + + VFNMSUB213SSm = 11942 + + VFNMSUB213SSm_Int = 11943 + + VFNMSUB213SSr = 11944 + + VFNMSUB213SSr_Int = 11945 + + VFNMSUB231BF16Z128m = 11946 + + VFNMSUB231BF16Z128mb = 11947 + + VFNMSUB231BF16Z128mbk = 11948 + + VFNMSUB231BF16Z128mbkz = 11949 + + VFNMSUB231BF16Z128mk = 11950 + + VFNMSUB231BF16Z128mkz = 11951 + + VFNMSUB231BF16Z128r = 11952 + + VFNMSUB231BF16Z128rk = 11953 + + VFNMSUB231BF16Z128rkz = 11954 + + VFNMSUB231BF16Z256m = 11955 + + VFNMSUB231BF16Z256mb = 11956 + + VFNMSUB231BF16Z256mbk = 11957 + + VFNMSUB231BF16Z256mbkz = 11958 + + VFNMSUB231BF16Z256mk = 11959 + + VFNMSUB231BF16Z256mkz = 11960 + + VFNMSUB231BF16Z256r = 11961 + + VFNMSUB231BF16Z256rk = 11962 + + VFNMSUB231BF16Z256rkz = 11963 + + VFNMSUB231BF16Zm = 11964 + + VFNMSUB231BF16Zmb = 11965 + + VFNMSUB231BF16Zmbk = 11966 + + VFNMSUB231BF16Zmbkz = 11967 + + VFNMSUB231BF16Zmk = 11968 + + VFNMSUB231BF16Zmkz = 11969 + + VFNMSUB231BF16Zr = 11970 + + VFNMSUB231BF16Zrk = 11971 + + VFNMSUB231BF16Zrkz = 11972 + + VFNMSUB231PDYm = 11973 + + VFNMSUB231PDYr = 11974 + + VFNMSUB231PDZ128m = 11975 + + VFNMSUB231PDZ128mb = 11976 + + VFNMSUB231PDZ128mbk = 11977 + + VFNMSUB231PDZ128mbkz = 11978 + + VFNMSUB231PDZ128mk = 11979 + + VFNMSUB231PDZ128mkz = 11980 + + VFNMSUB231PDZ128r = 11981 + + VFNMSUB231PDZ128rk = 11982 + + VFNMSUB231PDZ128rkz = 11983 + + VFNMSUB231PDZ256m = 11984 + + VFNMSUB231PDZ256mb = 11985 + + VFNMSUB231PDZ256mbk = 11986 + + VFNMSUB231PDZ256mbkz = 11987 + + VFNMSUB231PDZ256mk = 11988 + + VFNMSUB231PDZ256mkz = 11989 + + VFNMSUB231PDZ256r = 11990 + + VFNMSUB231PDZ256rk = 11991 + + VFNMSUB231PDZ256rkz = 11992 + + VFNMSUB231PDZm = 11993 + + VFNMSUB231PDZmb = 11994 + + VFNMSUB231PDZmbk = 11995 + + VFNMSUB231PDZmbkz = 11996 + + VFNMSUB231PDZmk = 11997 + + VFNMSUB231PDZmkz = 11998 + + VFNMSUB231PDZr = 11999 + + VFNMSUB231PDZrb = 12000 + + VFNMSUB231PDZrbk = 12001 + + VFNMSUB231PDZrbkz = 12002 + + VFNMSUB231PDZrk = 12003 + + VFNMSUB231PDZrkz = 12004 + + VFNMSUB231PDm = 12005 + + VFNMSUB231PDr = 12006 + + VFNMSUB231PHZ128m = 12007 + + VFNMSUB231PHZ128mb = 12008 + + VFNMSUB231PHZ128mbk = 12009 + + VFNMSUB231PHZ128mbkz = 12010 + + VFNMSUB231PHZ128mk = 12011 + + VFNMSUB231PHZ128mkz = 12012 + + VFNMSUB231PHZ128r = 12013 + + VFNMSUB231PHZ128rk = 12014 + + VFNMSUB231PHZ128rkz = 12015 + + VFNMSUB231PHZ256m = 12016 + + VFNMSUB231PHZ256mb = 12017 + + VFNMSUB231PHZ256mbk = 12018 + + VFNMSUB231PHZ256mbkz = 12019 + + VFNMSUB231PHZ256mk = 12020 + + VFNMSUB231PHZ256mkz = 12021 + + VFNMSUB231PHZ256r = 12022 + + VFNMSUB231PHZ256rk = 12023 + + VFNMSUB231PHZ256rkz = 12024 + + VFNMSUB231PHZm = 12025 + + VFNMSUB231PHZmb = 12026 + + VFNMSUB231PHZmbk = 12027 + + VFNMSUB231PHZmbkz = 12028 + + VFNMSUB231PHZmk = 12029 + + VFNMSUB231PHZmkz = 12030 + + VFNMSUB231PHZr = 12031 + + VFNMSUB231PHZrb = 12032 + + VFNMSUB231PHZrbk = 12033 + + VFNMSUB231PHZrbkz = 12034 + + VFNMSUB231PHZrk = 12035 + + VFNMSUB231PHZrkz = 12036 + + VFNMSUB231PSYm = 12037 + + VFNMSUB231PSYr = 12038 + + VFNMSUB231PSZ128m = 12039 + + VFNMSUB231PSZ128mb = 12040 + + VFNMSUB231PSZ128mbk = 12041 + + VFNMSUB231PSZ128mbkz = 12042 + + VFNMSUB231PSZ128mk = 12043 + + VFNMSUB231PSZ128mkz = 12044 + + VFNMSUB231PSZ128r = 12045 + + VFNMSUB231PSZ128rk = 12046 + + VFNMSUB231PSZ128rkz = 12047 + + VFNMSUB231PSZ256m = 12048 + + VFNMSUB231PSZ256mb = 12049 + + VFNMSUB231PSZ256mbk = 12050 + + VFNMSUB231PSZ256mbkz = 12051 + + VFNMSUB231PSZ256mk = 12052 + + VFNMSUB231PSZ256mkz = 12053 + + VFNMSUB231PSZ256r = 12054 + + VFNMSUB231PSZ256rk = 12055 + + VFNMSUB231PSZ256rkz = 12056 + + VFNMSUB231PSZm = 12057 + + VFNMSUB231PSZmb = 12058 + + VFNMSUB231PSZmbk = 12059 + + VFNMSUB231PSZmbkz = 12060 + + VFNMSUB231PSZmk = 12061 + + VFNMSUB231PSZmkz = 12062 + + VFNMSUB231PSZr = 12063 + + VFNMSUB231PSZrb = 12064 + + VFNMSUB231PSZrbk = 12065 + + VFNMSUB231PSZrbkz = 12066 + + VFNMSUB231PSZrk = 12067 + + VFNMSUB231PSZrkz = 12068 + + VFNMSUB231PSm = 12069 + + VFNMSUB231PSr = 12070 + + VFNMSUB231SDZm = 12071 + + VFNMSUB231SDZm_Int = 12072 + + VFNMSUB231SDZmk_Int = 12073 + + VFNMSUB231SDZmkz_Int = 12074 + + VFNMSUB231SDZr = 12075 + + VFNMSUB231SDZr_Int = 12076 + + VFNMSUB231SDZrb = 12077 + + VFNMSUB231SDZrb_Int = 12078 + + VFNMSUB231SDZrbk_Int = 12079 + + VFNMSUB231SDZrbkz_Int = 12080 + + VFNMSUB231SDZrk_Int = 12081 + + VFNMSUB231SDZrkz_Int = 12082 + + VFNMSUB231SDm = 12083 + + VFNMSUB231SDm_Int = 12084 + + VFNMSUB231SDr = 12085 + + VFNMSUB231SDr_Int = 12086 + + VFNMSUB231SHZm = 12087 + + VFNMSUB231SHZm_Int = 12088 + + VFNMSUB231SHZmk_Int = 12089 + + VFNMSUB231SHZmkz_Int = 12090 + + VFNMSUB231SHZr = 12091 + + VFNMSUB231SHZr_Int = 12092 + + VFNMSUB231SHZrb = 12093 + + VFNMSUB231SHZrb_Int = 12094 + + VFNMSUB231SHZrbk_Int = 12095 + + VFNMSUB231SHZrbkz_Int = 12096 + + VFNMSUB231SHZrk_Int = 12097 + + VFNMSUB231SHZrkz_Int = 12098 + + VFNMSUB231SSZm = 12099 + + VFNMSUB231SSZm_Int = 12100 + + VFNMSUB231SSZmk_Int = 12101 + + VFNMSUB231SSZmkz_Int = 12102 + + VFNMSUB231SSZr = 12103 + + VFNMSUB231SSZr_Int = 12104 + + VFNMSUB231SSZrb = 12105 + + VFNMSUB231SSZrb_Int = 12106 + + VFNMSUB231SSZrbk_Int = 12107 + + VFNMSUB231SSZrbkz_Int = 12108 + + VFNMSUB231SSZrk_Int = 12109 + + VFNMSUB231SSZrkz_Int = 12110 + + VFNMSUB231SSm = 12111 + + VFNMSUB231SSm_Int = 12112 + + VFNMSUB231SSr = 12113 + + VFNMSUB231SSr_Int = 12114 + + VFNMSUBPD4Ymr = 12115 + + VFNMSUBPD4Yrm = 12116 + + VFNMSUBPD4Yrr = 12117 + + VFNMSUBPD4Yrr_REV = 12118 + + VFNMSUBPD4mr = 12119 + + VFNMSUBPD4rm = 12120 + + VFNMSUBPD4rr = 12121 + + VFNMSUBPD4rr_REV = 12122 + + VFNMSUBPS4Ymr = 12123 + + VFNMSUBPS4Yrm = 12124 + + VFNMSUBPS4Yrr = 12125 + + VFNMSUBPS4Yrr_REV = 12126 + + VFNMSUBPS4mr = 12127 + + VFNMSUBPS4rm = 12128 + + VFNMSUBPS4rr = 12129 + + VFNMSUBPS4rr_REV = 12130 + + VFNMSUBSD4mr = 12131 + + VFNMSUBSD4mr_Int = 12132 + + VFNMSUBSD4rm = 12133 + + VFNMSUBSD4rm_Int = 12134 + + VFNMSUBSD4rr = 12135 + + VFNMSUBSD4rr_Int = 12136 + + VFNMSUBSD4rr_Int_REV = 12137 + + VFNMSUBSD4rr_REV = 12138 + + VFNMSUBSS4mr = 12139 + + VFNMSUBSS4mr_Int = 12140 + + VFNMSUBSS4rm = 12141 + + VFNMSUBSS4rm_Int = 12142 + + VFNMSUBSS4rr = 12143 + + VFNMSUBSS4rr_Int = 12144 + + VFNMSUBSS4rr_Int_REV = 12145 + + VFNMSUBSS4rr_REV = 12146 + + VFPCLASSBF16Z128mbi = 12147 + + VFPCLASSBF16Z128mbik = 12148 + + VFPCLASSBF16Z128mi = 12149 + + VFPCLASSBF16Z128mik = 12150 + + VFPCLASSBF16Z128ri = 12151 + + VFPCLASSBF16Z128rik = 12152 + + VFPCLASSBF16Z256mbi = 12153 + + VFPCLASSBF16Z256mbik = 12154 + + VFPCLASSBF16Z256mi = 12155 + + VFPCLASSBF16Z256mik = 12156 + + VFPCLASSBF16Z256ri = 12157 + + VFPCLASSBF16Z256rik = 12158 + + VFPCLASSBF16Zmbi = 12159 + + VFPCLASSBF16Zmbik = 12160 + + VFPCLASSBF16Zmi = 12161 + + VFPCLASSBF16Zmik = 12162 + + VFPCLASSBF16Zri = 12163 + + VFPCLASSBF16Zrik = 12164 + + VFPCLASSPDZ128mbi = 12165 + + VFPCLASSPDZ128mbik = 12166 + + VFPCLASSPDZ128mi = 12167 + + VFPCLASSPDZ128mik = 12168 + + VFPCLASSPDZ128ri = 12169 + + VFPCLASSPDZ128rik = 12170 + + VFPCLASSPDZ256mbi = 12171 + + VFPCLASSPDZ256mbik = 12172 + + VFPCLASSPDZ256mi = 12173 + + VFPCLASSPDZ256mik = 12174 + + VFPCLASSPDZ256ri = 12175 + + VFPCLASSPDZ256rik = 12176 + + VFPCLASSPDZmbi = 12177 + + VFPCLASSPDZmbik = 12178 + + VFPCLASSPDZmi = 12179 + + VFPCLASSPDZmik = 12180 + + VFPCLASSPDZri = 12181 + + VFPCLASSPDZrik = 12182 + + VFPCLASSPHZ128mbi = 12183 + + VFPCLASSPHZ128mbik = 12184 + + VFPCLASSPHZ128mi = 12185 + + VFPCLASSPHZ128mik = 12186 + + VFPCLASSPHZ128ri = 12187 + + VFPCLASSPHZ128rik = 12188 + + VFPCLASSPHZ256mbi = 12189 + + VFPCLASSPHZ256mbik = 12190 + + VFPCLASSPHZ256mi = 12191 + + VFPCLASSPHZ256mik = 12192 + + VFPCLASSPHZ256ri = 12193 + + VFPCLASSPHZ256rik = 12194 + + VFPCLASSPHZmbi = 12195 + + VFPCLASSPHZmbik = 12196 + + VFPCLASSPHZmi = 12197 + + VFPCLASSPHZmik = 12198 + + VFPCLASSPHZri = 12199 + + VFPCLASSPHZrik = 12200 + + VFPCLASSPSZ128mbi = 12201 + + VFPCLASSPSZ128mbik = 12202 + + VFPCLASSPSZ128mi = 12203 + + VFPCLASSPSZ128mik = 12204 + + VFPCLASSPSZ128ri = 12205 + + VFPCLASSPSZ128rik = 12206 + + VFPCLASSPSZ256mbi = 12207 + + VFPCLASSPSZ256mbik = 12208 + + VFPCLASSPSZ256mi = 12209 + + VFPCLASSPSZ256mik = 12210 + + VFPCLASSPSZ256ri = 12211 + + VFPCLASSPSZ256rik = 12212 + + VFPCLASSPSZmbi = 12213 + + VFPCLASSPSZmbik = 12214 + + VFPCLASSPSZmi = 12215 + + VFPCLASSPSZmik = 12216 + + VFPCLASSPSZri = 12217 + + VFPCLASSPSZrik = 12218 + + VFPCLASSSDZmi = 12219 + + VFPCLASSSDZmik = 12220 + + VFPCLASSSDZri = 12221 + + VFPCLASSSDZrik = 12222 + + VFPCLASSSHZmi = 12223 + + VFPCLASSSHZmik = 12224 + + VFPCLASSSHZri = 12225 + + VFPCLASSSHZrik = 12226 + + VFPCLASSSSZmi = 12227 + + VFPCLASSSSZmik = 12228 + + VFPCLASSSSZri = 12229 + + VFPCLASSSSZrik = 12230 + + VFRCZPDYrm = 12231 + + VFRCZPDYrr = 12232 + + VFRCZPDrm = 12233 + + VFRCZPDrr = 12234 + + VFRCZPSYrm = 12235 + + VFRCZPSYrr = 12236 + + VFRCZPSrm = 12237 + + VFRCZPSrr = 12238 + + VFRCZSDrm = 12239 + + VFRCZSDrr = 12240 + + VFRCZSSrm = 12241 + + VFRCZSSrr = 12242 + + VGATHERDPDYrm = 12243 + + VGATHERDPDZ128rm = 12244 + + VGATHERDPDZ256rm = 12245 + + VGATHERDPDZrm = 12246 + + VGATHERDPDrm = 12247 + + VGATHERDPSYrm = 12248 + + VGATHERDPSZ128rm = 12249 + + VGATHERDPSZ256rm = 12250 + + VGATHERDPSZrm = 12251 + + VGATHERDPSrm = 12252 + + VGATHERPF0DPDm = 12253 + + VGATHERPF0DPSm = 12254 + + VGATHERPF0QPDm = 12255 + + VGATHERPF0QPSm = 12256 + + VGATHERPF1DPDm = 12257 + + VGATHERPF1DPSm = 12258 + + VGATHERPF1QPDm = 12259 + + VGATHERPF1QPSm = 12260 + + VGATHERQPDYrm = 12261 + + VGATHERQPDZ128rm = 12262 + + VGATHERQPDZ256rm = 12263 + + VGATHERQPDZrm = 12264 + + VGATHERQPDrm = 12265 + + VGATHERQPSYrm = 12266 + + VGATHERQPSZ128rm = 12267 + + VGATHERQPSZ256rm = 12268 + + VGATHERQPSZrm = 12269 + + VGATHERQPSrm = 12270 + + VGETEXPBF16Z128m = 12271 + + VGETEXPBF16Z128mb = 12272 + + VGETEXPBF16Z128mbk = 12273 + + VGETEXPBF16Z128mbkz = 12274 + + VGETEXPBF16Z128mk = 12275 + + VGETEXPBF16Z128mkz = 12276 + + VGETEXPBF16Z128r = 12277 + + VGETEXPBF16Z128rk = 12278 + + VGETEXPBF16Z128rkz = 12279 + + VGETEXPBF16Z256m = 12280 + + VGETEXPBF16Z256mb = 12281 + + VGETEXPBF16Z256mbk = 12282 + + VGETEXPBF16Z256mbkz = 12283 + + VGETEXPBF16Z256mk = 12284 + + VGETEXPBF16Z256mkz = 12285 + + VGETEXPBF16Z256r = 12286 + + VGETEXPBF16Z256rk = 12287 + + VGETEXPBF16Z256rkz = 12288 + + VGETEXPBF16Zm = 12289 + + VGETEXPBF16Zmb = 12290 + + VGETEXPBF16Zmbk = 12291 + + VGETEXPBF16Zmbkz = 12292 + + VGETEXPBF16Zmk = 12293 + + VGETEXPBF16Zmkz = 12294 + + VGETEXPBF16Zr = 12295 + + VGETEXPBF16Zrk = 12296 + + VGETEXPBF16Zrkz = 12297 + + VGETEXPPDZ128m = 12298 + + VGETEXPPDZ128mb = 12299 + + VGETEXPPDZ128mbk = 12300 + + VGETEXPPDZ128mbkz = 12301 + + VGETEXPPDZ128mk = 12302 + + VGETEXPPDZ128mkz = 12303 + + VGETEXPPDZ128r = 12304 + + VGETEXPPDZ128rk = 12305 + + VGETEXPPDZ128rkz = 12306 + + VGETEXPPDZ256m = 12307 + + VGETEXPPDZ256mb = 12308 + + VGETEXPPDZ256mbk = 12309 + + VGETEXPPDZ256mbkz = 12310 + + VGETEXPPDZ256mk = 12311 + + VGETEXPPDZ256mkz = 12312 + + VGETEXPPDZ256r = 12313 + + VGETEXPPDZ256rk = 12314 + + VGETEXPPDZ256rkz = 12315 + + VGETEXPPDZm = 12316 + + VGETEXPPDZmb = 12317 + + VGETEXPPDZmbk = 12318 + + VGETEXPPDZmbkz = 12319 + + VGETEXPPDZmk = 12320 + + VGETEXPPDZmkz = 12321 + + VGETEXPPDZr = 12322 + + VGETEXPPDZrb = 12323 + + VGETEXPPDZrbk = 12324 + + VGETEXPPDZrbkz = 12325 + + VGETEXPPDZrk = 12326 + + VGETEXPPDZrkz = 12327 + + VGETEXPPHZ128m = 12328 + + VGETEXPPHZ128mb = 12329 + + VGETEXPPHZ128mbk = 12330 + + VGETEXPPHZ128mbkz = 12331 + + VGETEXPPHZ128mk = 12332 + + VGETEXPPHZ128mkz = 12333 + + VGETEXPPHZ128r = 12334 + + VGETEXPPHZ128rk = 12335 + + VGETEXPPHZ128rkz = 12336 + + VGETEXPPHZ256m = 12337 + + VGETEXPPHZ256mb = 12338 + + VGETEXPPHZ256mbk = 12339 + + VGETEXPPHZ256mbkz = 12340 + + VGETEXPPHZ256mk = 12341 + + VGETEXPPHZ256mkz = 12342 + + VGETEXPPHZ256r = 12343 + + VGETEXPPHZ256rk = 12344 + + VGETEXPPHZ256rkz = 12345 + + VGETEXPPHZm = 12346 + + VGETEXPPHZmb = 12347 + + VGETEXPPHZmbk = 12348 + + VGETEXPPHZmbkz = 12349 + + VGETEXPPHZmk = 12350 + + VGETEXPPHZmkz = 12351 + + VGETEXPPHZr = 12352 + + VGETEXPPHZrb = 12353 + + VGETEXPPHZrbk = 12354 + + VGETEXPPHZrbkz = 12355 + + VGETEXPPHZrk = 12356 + + VGETEXPPHZrkz = 12357 + + VGETEXPPSZ128m = 12358 + + VGETEXPPSZ128mb = 12359 + + VGETEXPPSZ128mbk = 12360 + + VGETEXPPSZ128mbkz = 12361 + + VGETEXPPSZ128mk = 12362 + + VGETEXPPSZ128mkz = 12363 + + VGETEXPPSZ128r = 12364 + + VGETEXPPSZ128rk = 12365 + + VGETEXPPSZ128rkz = 12366 + + VGETEXPPSZ256m = 12367 + + VGETEXPPSZ256mb = 12368 + + VGETEXPPSZ256mbk = 12369 + + VGETEXPPSZ256mbkz = 12370 + + VGETEXPPSZ256mk = 12371 + + VGETEXPPSZ256mkz = 12372 + + VGETEXPPSZ256r = 12373 + + VGETEXPPSZ256rk = 12374 + + VGETEXPPSZ256rkz = 12375 + + VGETEXPPSZm = 12376 + + VGETEXPPSZmb = 12377 + + VGETEXPPSZmbk = 12378 + + VGETEXPPSZmbkz = 12379 + + VGETEXPPSZmk = 12380 + + VGETEXPPSZmkz = 12381 + + VGETEXPPSZr = 12382 + + VGETEXPPSZrb = 12383 + + VGETEXPPSZrbk = 12384 + + VGETEXPPSZrbkz = 12385 + + VGETEXPPSZrk = 12386 + + VGETEXPPSZrkz = 12387 + + VGETEXPSDZm = 12388 + + VGETEXPSDZmk = 12389 + + VGETEXPSDZmkz = 12390 + + VGETEXPSDZr = 12391 + + VGETEXPSDZrb = 12392 + + VGETEXPSDZrbk = 12393 + + VGETEXPSDZrbkz = 12394 + + VGETEXPSDZrk = 12395 + + VGETEXPSDZrkz = 12396 + + VGETEXPSHZm = 12397 + + VGETEXPSHZmk = 12398 + + VGETEXPSHZmkz = 12399 + + VGETEXPSHZr = 12400 + + VGETEXPSHZrb = 12401 + + VGETEXPSHZrbk = 12402 + + VGETEXPSHZrbkz = 12403 + + VGETEXPSHZrk = 12404 + + VGETEXPSHZrkz = 12405 + + VGETEXPSSZm = 12406 + + VGETEXPSSZmk = 12407 + + VGETEXPSSZmkz = 12408 + + VGETEXPSSZr = 12409 + + VGETEXPSSZrb = 12410 + + VGETEXPSSZrbk = 12411 + + VGETEXPSSZrbkz = 12412 + + VGETEXPSSZrk = 12413 + + VGETEXPSSZrkz = 12414 + + VGETMANTBF16Z128rmbi = 12415 + + VGETMANTBF16Z128rmbik = 12416 + + VGETMANTBF16Z128rmbikz = 12417 + + VGETMANTBF16Z128rmi = 12418 + + VGETMANTBF16Z128rmik = 12419 + + VGETMANTBF16Z128rmikz = 12420 + + VGETMANTBF16Z128rri = 12421 + + VGETMANTBF16Z128rrik = 12422 + + VGETMANTBF16Z128rrikz = 12423 + + VGETMANTBF16Z256rmbi = 12424 + + VGETMANTBF16Z256rmbik = 12425 + + VGETMANTBF16Z256rmbikz = 12426 + + VGETMANTBF16Z256rmi = 12427 + + VGETMANTBF16Z256rmik = 12428 + + VGETMANTBF16Z256rmikz = 12429 + + VGETMANTBF16Z256rri = 12430 + + VGETMANTBF16Z256rrik = 12431 + + VGETMANTBF16Z256rrikz = 12432 + + VGETMANTBF16Zrmbi = 12433 + + VGETMANTBF16Zrmbik = 12434 + + VGETMANTBF16Zrmbikz = 12435 + + VGETMANTBF16Zrmi = 12436 + + VGETMANTBF16Zrmik = 12437 + + VGETMANTBF16Zrmikz = 12438 + + VGETMANTBF16Zrri = 12439 + + VGETMANTBF16Zrrik = 12440 + + VGETMANTBF16Zrrikz = 12441 + + VGETMANTPDZ128rmbi = 12442 + + VGETMANTPDZ128rmbik = 12443 + + VGETMANTPDZ128rmbikz = 12444 + + VGETMANTPDZ128rmi = 12445 + + VGETMANTPDZ128rmik = 12446 + + VGETMANTPDZ128rmikz = 12447 + + VGETMANTPDZ128rri = 12448 + + VGETMANTPDZ128rrik = 12449 + + VGETMANTPDZ128rrikz = 12450 + + VGETMANTPDZ256rmbi = 12451 + + VGETMANTPDZ256rmbik = 12452 + + VGETMANTPDZ256rmbikz = 12453 + + VGETMANTPDZ256rmi = 12454 + + VGETMANTPDZ256rmik = 12455 + + VGETMANTPDZ256rmikz = 12456 + + VGETMANTPDZ256rri = 12457 + + VGETMANTPDZ256rrik = 12458 + + VGETMANTPDZ256rrikz = 12459 + + VGETMANTPDZrmbi = 12460 + + VGETMANTPDZrmbik = 12461 + + VGETMANTPDZrmbikz = 12462 + + VGETMANTPDZrmi = 12463 + + VGETMANTPDZrmik = 12464 + + VGETMANTPDZrmikz = 12465 + + VGETMANTPDZrri = 12466 + + VGETMANTPDZrrib = 12467 + + VGETMANTPDZrribk = 12468 + + VGETMANTPDZrribkz = 12469 + + VGETMANTPDZrrik = 12470 + + VGETMANTPDZrrikz = 12471 + + VGETMANTPHZ128rmbi = 12472 + + VGETMANTPHZ128rmbik = 12473 + + VGETMANTPHZ128rmbikz = 12474 + + VGETMANTPHZ128rmi = 12475 + + VGETMANTPHZ128rmik = 12476 + + VGETMANTPHZ128rmikz = 12477 + + VGETMANTPHZ128rri = 12478 + + VGETMANTPHZ128rrik = 12479 + + VGETMANTPHZ128rrikz = 12480 + + VGETMANTPHZ256rmbi = 12481 + + VGETMANTPHZ256rmbik = 12482 + + VGETMANTPHZ256rmbikz = 12483 + + VGETMANTPHZ256rmi = 12484 + + VGETMANTPHZ256rmik = 12485 + + VGETMANTPHZ256rmikz = 12486 + + VGETMANTPHZ256rri = 12487 + + VGETMANTPHZ256rrik = 12488 + + VGETMANTPHZ256rrikz = 12489 + + VGETMANTPHZrmbi = 12490 + + VGETMANTPHZrmbik = 12491 + + VGETMANTPHZrmbikz = 12492 + + VGETMANTPHZrmi = 12493 + + VGETMANTPHZrmik = 12494 + + VGETMANTPHZrmikz = 12495 + + VGETMANTPHZrri = 12496 + + VGETMANTPHZrrib = 12497 + + VGETMANTPHZrribk = 12498 + + VGETMANTPHZrribkz = 12499 + + VGETMANTPHZrrik = 12500 + + VGETMANTPHZrrikz = 12501 + + VGETMANTPSZ128rmbi = 12502 + + VGETMANTPSZ128rmbik = 12503 + + VGETMANTPSZ128rmbikz = 12504 + + VGETMANTPSZ128rmi = 12505 + + VGETMANTPSZ128rmik = 12506 + + VGETMANTPSZ128rmikz = 12507 + + VGETMANTPSZ128rri = 12508 + + VGETMANTPSZ128rrik = 12509 + + VGETMANTPSZ128rrikz = 12510 + + VGETMANTPSZ256rmbi = 12511 + + VGETMANTPSZ256rmbik = 12512 + + VGETMANTPSZ256rmbikz = 12513 + + VGETMANTPSZ256rmi = 12514 + + VGETMANTPSZ256rmik = 12515 + + VGETMANTPSZ256rmikz = 12516 + + VGETMANTPSZ256rri = 12517 + + VGETMANTPSZ256rrik = 12518 + + VGETMANTPSZ256rrikz = 12519 + + VGETMANTPSZrmbi = 12520 + + VGETMANTPSZrmbik = 12521 + + VGETMANTPSZrmbikz = 12522 + + VGETMANTPSZrmi = 12523 + + VGETMANTPSZrmik = 12524 + + VGETMANTPSZrmikz = 12525 + + VGETMANTPSZrri = 12526 + + VGETMANTPSZrrib = 12527 + + VGETMANTPSZrribk = 12528 + + VGETMANTPSZrribkz = 12529 + + VGETMANTPSZrrik = 12530 + + VGETMANTPSZrrikz = 12531 + + VGETMANTSDZrmi = 12532 + + VGETMANTSDZrmik = 12533 + + VGETMANTSDZrmikz = 12534 + + VGETMANTSDZrri = 12535 + + VGETMANTSDZrrib = 12536 + + VGETMANTSDZrribk = 12537 + + VGETMANTSDZrribkz = 12538 + + VGETMANTSDZrrik = 12539 + + VGETMANTSDZrrikz = 12540 + + VGETMANTSHZrmi = 12541 + + VGETMANTSHZrmik = 12542 + + VGETMANTSHZrmikz = 12543 + + VGETMANTSHZrri = 12544 + + VGETMANTSHZrrib = 12545 + + VGETMANTSHZrribk = 12546 + + VGETMANTSHZrribkz = 12547 + + VGETMANTSHZrrik = 12548 + + VGETMANTSHZrrikz = 12549 + + VGETMANTSSZrmi = 12550 + + VGETMANTSSZrmik = 12551 + + VGETMANTSSZrmikz = 12552 + + VGETMANTSSZrri = 12553 + + VGETMANTSSZrrib = 12554 + + VGETMANTSSZrribk = 12555 + + VGETMANTSSZrribkz = 12556 + + VGETMANTSSZrrik = 12557 + + VGETMANTSSZrrikz = 12558 + + VGF2P8AFFINEINVQBYrmi = 12559 + + VGF2P8AFFINEINVQBYrri = 12560 + + VGF2P8AFFINEINVQBZ128rmbi = 12561 + + VGF2P8AFFINEINVQBZ128rmbik = 12562 + + VGF2P8AFFINEINVQBZ128rmbikz = 12563 + + VGF2P8AFFINEINVQBZ128rmi = 12564 + + VGF2P8AFFINEINVQBZ128rmik = 12565 + + VGF2P8AFFINEINVQBZ128rmikz = 12566 + + VGF2P8AFFINEINVQBZ128rri = 12567 + + VGF2P8AFFINEINVQBZ128rrik = 12568 + + VGF2P8AFFINEINVQBZ128rrikz = 12569 + + VGF2P8AFFINEINVQBZ256rmbi = 12570 + + VGF2P8AFFINEINVQBZ256rmbik = 12571 + + VGF2P8AFFINEINVQBZ256rmbikz = 12572 + + VGF2P8AFFINEINVQBZ256rmi = 12573 + + VGF2P8AFFINEINVQBZ256rmik = 12574 + + VGF2P8AFFINEINVQBZ256rmikz = 12575 + + VGF2P8AFFINEINVQBZ256rri = 12576 + + VGF2P8AFFINEINVQBZ256rrik = 12577 + + VGF2P8AFFINEINVQBZ256rrikz = 12578 + + VGF2P8AFFINEINVQBZrmbi = 12579 + + VGF2P8AFFINEINVQBZrmbik = 12580 + + VGF2P8AFFINEINVQBZrmbikz = 12581 + + VGF2P8AFFINEINVQBZrmi = 12582 + + VGF2P8AFFINEINVQBZrmik = 12583 + + VGF2P8AFFINEINVQBZrmikz = 12584 + + VGF2P8AFFINEINVQBZrri = 12585 + + VGF2P8AFFINEINVQBZrrik = 12586 + + VGF2P8AFFINEINVQBZrrikz = 12587 + + VGF2P8AFFINEINVQBrmi = 12588 + + VGF2P8AFFINEINVQBrri = 12589 + + VGF2P8AFFINEQBYrmi = 12590 + + VGF2P8AFFINEQBYrri = 12591 + + VGF2P8AFFINEQBZ128rmbi = 12592 + + VGF2P8AFFINEQBZ128rmbik = 12593 + + VGF2P8AFFINEQBZ128rmbikz = 12594 + + VGF2P8AFFINEQBZ128rmi = 12595 + + VGF2P8AFFINEQBZ128rmik = 12596 + + VGF2P8AFFINEQBZ128rmikz = 12597 + + VGF2P8AFFINEQBZ128rri = 12598 + + VGF2P8AFFINEQBZ128rrik = 12599 + + VGF2P8AFFINEQBZ128rrikz = 12600 + + VGF2P8AFFINEQBZ256rmbi = 12601 + + VGF2P8AFFINEQBZ256rmbik = 12602 + + VGF2P8AFFINEQBZ256rmbikz = 12603 + + VGF2P8AFFINEQBZ256rmi = 12604 + + VGF2P8AFFINEQBZ256rmik = 12605 + + VGF2P8AFFINEQBZ256rmikz = 12606 + + VGF2P8AFFINEQBZ256rri = 12607 + + VGF2P8AFFINEQBZ256rrik = 12608 + + VGF2P8AFFINEQBZ256rrikz = 12609 + + VGF2P8AFFINEQBZrmbi = 12610 + + VGF2P8AFFINEQBZrmbik = 12611 + + VGF2P8AFFINEQBZrmbikz = 12612 + + VGF2P8AFFINEQBZrmi = 12613 + + VGF2P8AFFINEQBZrmik = 12614 + + VGF2P8AFFINEQBZrmikz = 12615 + + VGF2P8AFFINEQBZrri = 12616 + + VGF2P8AFFINEQBZrrik = 12617 + + VGF2P8AFFINEQBZrrikz = 12618 + + VGF2P8AFFINEQBrmi = 12619 + + VGF2P8AFFINEQBrri = 12620 + + VGF2P8MULBYrm = 12621 + + VGF2P8MULBYrr = 12622 + + VGF2P8MULBZ128rm = 12623 + + VGF2P8MULBZ128rmk = 12624 + + VGF2P8MULBZ128rmkz = 12625 + + VGF2P8MULBZ128rr = 12626 + + VGF2P8MULBZ128rrk = 12627 + + VGF2P8MULBZ128rrkz = 12628 + + VGF2P8MULBZ256rm = 12629 + + VGF2P8MULBZ256rmk = 12630 + + VGF2P8MULBZ256rmkz = 12631 + + VGF2P8MULBZ256rr = 12632 + + VGF2P8MULBZ256rrk = 12633 + + VGF2P8MULBZ256rrkz = 12634 + + VGF2P8MULBZrm = 12635 + + VGF2P8MULBZrmk = 12636 + + VGF2P8MULBZrmkz = 12637 + + VGF2P8MULBZrr = 12638 + + VGF2P8MULBZrrk = 12639 + + VGF2P8MULBZrrkz = 12640 + + VGF2P8MULBrm = 12641 + + VGF2P8MULBrr = 12642 + + VHADDPDYrm = 12643 + + VHADDPDYrr = 12644 + + VHADDPDrm = 12645 + + VHADDPDrr = 12646 + + VHADDPSYrm = 12647 + + VHADDPSYrr = 12648 + + VHADDPSrm = 12649 + + VHADDPSrr = 12650 + + VHSUBPDYrm = 12651 + + VHSUBPDYrr = 12652 + + VHSUBPDrm = 12653 + + VHSUBPDrr = 12654 + + VHSUBPSYrm = 12655 + + VHSUBPSYrr = 12656 + + VHSUBPSrm = 12657 + + VHSUBPSrr = 12658 + + VINSERTF128rmi = 12659 + + VINSERTF128rri = 12660 + + VINSERTF32X4Z256rmi = 12661 + + VINSERTF32X4Z256rmik = 12662 + + VINSERTF32X4Z256rmikz = 12663 + + VINSERTF32X4Z256rri = 12664 + + VINSERTF32X4Z256rrik = 12665 + + VINSERTF32X4Z256rrikz = 12666 + + VINSERTF32X4Zrmi = 12667 + + VINSERTF32X4Zrmik = 12668 + + VINSERTF32X4Zrmikz = 12669 + + VINSERTF32X4Zrri = 12670 + + VINSERTF32X4Zrrik = 12671 + + VINSERTF32X4Zrrikz = 12672 + + VINSERTF32X8Zrmi = 12673 + + VINSERTF32X8Zrmik = 12674 + + VINSERTF32X8Zrmikz = 12675 + + VINSERTF32X8Zrri = 12676 + + VINSERTF32X8Zrrik = 12677 + + VINSERTF32X8Zrrikz = 12678 + + VINSERTF64X2Z256rmi = 12679 + + VINSERTF64X2Z256rmik = 12680 + + VINSERTF64X2Z256rmikz = 12681 + + VINSERTF64X2Z256rri = 12682 + + VINSERTF64X2Z256rrik = 12683 + + VINSERTF64X2Z256rrikz = 12684 + + VINSERTF64X2Zrmi = 12685 + + VINSERTF64X2Zrmik = 12686 + + VINSERTF64X2Zrmikz = 12687 + + VINSERTF64X2Zrri = 12688 + + VINSERTF64X2Zrrik = 12689 + + VINSERTF64X2Zrrikz = 12690 + + VINSERTF64X4Zrmi = 12691 + + VINSERTF64X4Zrmik = 12692 + + VINSERTF64X4Zrmikz = 12693 + + VINSERTF64X4Zrri = 12694 + + VINSERTF64X4Zrrik = 12695 + + VINSERTF64X4Zrrikz = 12696 + + VINSERTI128rmi = 12697 + + VINSERTI128rri = 12698 + + VINSERTI32X4Z256rmi = 12699 + + VINSERTI32X4Z256rmik = 12700 + + VINSERTI32X4Z256rmikz = 12701 + + VINSERTI32X4Z256rri = 12702 + + VINSERTI32X4Z256rrik = 12703 + + VINSERTI32X4Z256rrikz = 12704 + + VINSERTI32X4Zrmi = 12705 + + VINSERTI32X4Zrmik = 12706 + + VINSERTI32X4Zrmikz = 12707 + + VINSERTI32X4Zrri = 12708 + + VINSERTI32X4Zrrik = 12709 + + VINSERTI32X4Zrrikz = 12710 + + VINSERTI32X8Zrmi = 12711 + + VINSERTI32X8Zrmik = 12712 + + VINSERTI32X8Zrmikz = 12713 + + VINSERTI32X8Zrri = 12714 + + VINSERTI32X8Zrrik = 12715 + + VINSERTI32X8Zrrikz = 12716 + + VINSERTI64X2Z256rmi = 12717 + + VINSERTI64X2Z256rmik = 12718 + + VINSERTI64X2Z256rmikz = 12719 + + VINSERTI64X2Z256rri = 12720 + + VINSERTI64X2Z256rrik = 12721 + + VINSERTI64X2Z256rrikz = 12722 + + VINSERTI64X2Zrmi = 12723 + + VINSERTI64X2Zrmik = 12724 + + VINSERTI64X2Zrmikz = 12725 + + VINSERTI64X2Zrri = 12726 + + VINSERTI64X2Zrrik = 12727 + + VINSERTI64X2Zrrikz = 12728 + + VINSERTI64X4Zrmi = 12729 + + VINSERTI64X4Zrmik = 12730 + + VINSERTI64X4Zrmikz = 12731 + + VINSERTI64X4Zrri = 12732 + + VINSERTI64X4Zrrik = 12733 + + VINSERTI64X4Zrrikz = 12734 + + VINSERTPSZrmi = 12735 + + VINSERTPSZrri = 12736 + + VINSERTPSrmi = 12737 + + VINSERTPSrri = 12738 + + VLDDQUYrm = 12739 + + VLDDQUrm = 12740 + + VLDMXCSR = 12741 + + VMASKMOVDQU = 12742 + + VMASKMOVDQU64 = 12743 + + VMASKMOVPDYmr = 12744 + + VMASKMOVPDYrm = 12745 + + VMASKMOVPDmr = 12746 + + VMASKMOVPDrm = 12747 + + VMASKMOVPSYmr = 12748 + + VMASKMOVPSYrm = 12749 + + VMASKMOVPSmr = 12750 + + VMASKMOVPSrm = 12751 + + VMAXBF16Z128rm = 12752 + + VMAXBF16Z128rmb = 12753 + + VMAXBF16Z128rmbk = 12754 + + VMAXBF16Z128rmbkz = 12755 + + VMAXBF16Z128rmk = 12756 + + VMAXBF16Z128rmkz = 12757 + + VMAXBF16Z128rr = 12758 + + VMAXBF16Z128rrk = 12759 + + VMAXBF16Z128rrkz = 12760 + + VMAXBF16Z256rm = 12761 + + VMAXBF16Z256rmb = 12762 + + VMAXBF16Z256rmbk = 12763 + + VMAXBF16Z256rmbkz = 12764 + + VMAXBF16Z256rmk = 12765 + + VMAXBF16Z256rmkz = 12766 + + VMAXBF16Z256rr = 12767 + + VMAXBF16Z256rrk = 12768 + + VMAXBF16Z256rrkz = 12769 + + VMAXBF16Zrm = 12770 + + VMAXBF16Zrmb = 12771 + + VMAXBF16Zrmbk = 12772 + + VMAXBF16Zrmbkz = 12773 + + VMAXBF16Zrmk = 12774 + + VMAXBF16Zrmkz = 12775 + + VMAXBF16Zrr = 12776 + + VMAXBF16Zrrk = 12777 + + VMAXBF16Zrrkz = 12778 + + VMAXCPDYrm = 12779 + + VMAXCPDYrr = 12780 + + VMAXCPDZ128rm = 12781 + + VMAXCPDZ128rmb = 12782 + + VMAXCPDZ128rmbk = 12783 + + VMAXCPDZ128rmbkz = 12784 + + VMAXCPDZ128rmk = 12785 + + VMAXCPDZ128rmkz = 12786 + + VMAXCPDZ128rr = 12787 + + VMAXCPDZ128rrk = 12788 + + VMAXCPDZ128rrkz = 12789 + + VMAXCPDZ256rm = 12790 + + VMAXCPDZ256rmb = 12791 + + VMAXCPDZ256rmbk = 12792 + + VMAXCPDZ256rmbkz = 12793 + + VMAXCPDZ256rmk = 12794 + + VMAXCPDZ256rmkz = 12795 + + VMAXCPDZ256rr = 12796 + + VMAXCPDZ256rrk = 12797 + + VMAXCPDZ256rrkz = 12798 + + VMAXCPDZrm = 12799 + + VMAXCPDZrmb = 12800 + + VMAXCPDZrmbk = 12801 + + VMAXCPDZrmbkz = 12802 + + VMAXCPDZrmk = 12803 + + VMAXCPDZrmkz = 12804 + + VMAXCPDZrr = 12805 + + VMAXCPDZrrk = 12806 + + VMAXCPDZrrkz = 12807 + + VMAXCPDrm = 12808 + + VMAXCPDrr = 12809 + + VMAXCPHZ128rm = 12810 + + VMAXCPHZ128rmb = 12811 + + VMAXCPHZ128rmbk = 12812 + + VMAXCPHZ128rmbkz = 12813 + + VMAXCPHZ128rmk = 12814 + + VMAXCPHZ128rmkz = 12815 + + VMAXCPHZ128rr = 12816 + + VMAXCPHZ128rrk = 12817 + + VMAXCPHZ128rrkz = 12818 + + VMAXCPHZ256rm = 12819 + + VMAXCPHZ256rmb = 12820 + + VMAXCPHZ256rmbk = 12821 + + VMAXCPHZ256rmbkz = 12822 + + VMAXCPHZ256rmk = 12823 + + VMAXCPHZ256rmkz = 12824 + + VMAXCPHZ256rr = 12825 + + VMAXCPHZ256rrk = 12826 + + VMAXCPHZ256rrkz = 12827 + + VMAXCPHZrm = 12828 + + VMAXCPHZrmb = 12829 + + VMAXCPHZrmbk = 12830 + + VMAXCPHZrmbkz = 12831 + + VMAXCPHZrmk = 12832 + + VMAXCPHZrmkz = 12833 + + VMAXCPHZrr = 12834 + + VMAXCPHZrrk = 12835 + + VMAXCPHZrrkz = 12836 + + VMAXCPSYrm = 12837 + + VMAXCPSYrr = 12838 + + VMAXCPSZ128rm = 12839 + + VMAXCPSZ128rmb = 12840 + + VMAXCPSZ128rmbk = 12841 + + VMAXCPSZ128rmbkz = 12842 + + VMAXCPSZ128rmk = 12843 + + VMAXCPSZ128rmkz = 12844 + + VMAXCPSZ128rr = 12845 + + VMAXCPSZ128rrk = 12846 + + VMAXCPSZ128rrkz = 12847 + + VMAXCPSZ256rm = 12848 + + VMAXCPSZ256rmb = 12849 + + VMAXCPSZ256rmbk = 12850 + + VMAXCPSZ256rmbkz = 12851 + + VMAXCPSZ256rmk = 12852 + + VMAXCPSZ256rmkz = 12853 + + VMAXCPSZ256rr = 12854 + + VMAXCPSZ256rrk = 12855 + + VMAXCPSZ256rrkz = 12856 + + VMAXCPSZrm = 12857 + + VMAXCPSZrmb = 12858 + + VMAXCPSZrmbk = 12859 + + VMAXCPSZrmbkz = 12860 + + VMAXCPSZrmk = 12861 + + VMAXCPSZrmkz = 12862 + + VMAXCPSZrr = 12863 + + VMAXCPSZrrk = 12864 + + VMAXCPSZrrkz = 12865 + + VMAXCPSrm = 12866 + + VMAXCPSrr = 12867 + + VMAXCSDZrm = 12868 + + VMAXCSDZrr = 12869 + + VMAXCSDrm = 12870 + + VMAXCSDrr = 12871 + + VMAXCSHZrm = 12872 + + VMAXCSHZrr = 12873 + + VMAXCSSZrm = 12874 + + VMAXCSSZrr = 12875 + + VMAXCSSrm = 12876 + + VMAXCSSrr = 12877 + + VMAXPDYrm = 12878 + + VMAXPDYrr = 12879 + + VMAXPDZ128rm = 12880 + + VMAXPDZ128rmb = 12881 + + VMAXPDZ128rmbk = 12882 + + VMAXPDZ128rmbkz = 12883 + + VMAXPDZ128rmk = 12884 + + VMAXPDZ128rmkz = 12885 + + VMAXPDZ128rr = 12886 + + VMAXPDZ128rrk = 12887 + + VMAXPDZ128rrkz = 12888 + + VMAXPDZ256rm = 12889 + + VMAXPDZ256rmb = 12890 + + VMAXPDZ256rmbk = 12891 + + VMAXPDZ256rmbkz = 12892 + + VMAXPDZ256rmk = 12893 + + VMAXPDZ256rmkz = 12894 + + VMAXPDZ256rr = 12895 + + VMAXPDZ256rrk = 12896 + + VMAXPDZ256rrkz = 12897 + + VMAXPDZrm = 12898 + + VMAXPDZrmb = 12899 + + VMAXPDZrmbk = 12900 + + VMAXPDZrmbkz = 12901 + + VMAXPDZrmk = 12902 + + VMAXPDZrmkz = 12903 + + VMAXPDZrr = 12904 + + VMAXPDZrrb = 12905 + + VMAXPDZrrbk = 12906 + + VMAXPDZrrbkz = 12907 + + VMAXPDZrrk = 12908 + + VMAXPDZrrkz = 12909 + + VMAXPDrm = 12910 + + VMAXPDrr = 12911 + + VMAXPHZ128rm = 12912 + + VMAXPHZ128rmb = 12913 + + VMAXPHZ128rmbk = 12914 + + VMAXPHZ128rmbkz = 12915 + + VMAXPHZ128rmk = 12916 + + VMAXPHZ128rmkz = 12917 + + VMAXPHZ128rr = 12918 + + VMAXPHZ128rrk = 12919 + + VMAXPHZ128rrkz = 12920 + + VMAXPHZ256rm = 12921 + + VMAXPHZ256rmb = 12922 + + VMAXPHZ256rmbk = 12923 + + VMAXPHZ256rmbkz = 12924 + + VMAXPHZ256rmk = 12925 + + VMAXPHZ256rmkz = 12926 + + VMAXPHZ256rr = 12927 + + VMAXPHZ256rrk = 12928 + + VMAXPHZ256rrkz = 12929 + + VMAXPHZrm = 12930 + + VMAXPHZrmb = 12931 + + VMAXPHZrmbk = 12932 + + VMAXPHZrmbkz = 12933 + + VMAXPHZrmk = 12934 + + VMAXPHZrmkz = 12935 + + VMAXPHZrr = 12936 + + VMAXPHZrrb = 12937 + + VMAXPHZrrbk = 12938 + + VMAXPHZrrbkz = 12939 + + VMAXPHZrrk = 12940 + + VMAXPHZrrkz = 12941 + + VMAXPSYrm = 12942 + + VMAXPSYrr = 12943 + + VMAXPSZ128rm = 12944 + + VMAXPSZ128rmb = 12945 + + VMAXPSZ128rmbk = 12946 + + VMAXPSZ128rmbkz = 12947 + + VMAXPSZ128rmk = 12948 + + VMAXPSZ128rmkz = 12949 + + VMAXPSZ128rr = 12950 + + VMAXPSZ128rrk = 12951 + + VMAXPSZ128rrkz = 12952 + + VMAXPSZ256rm = 12953 + + VMAXPSZ256rmb = 12954 + + VMAXPSZ256rmbk = 12955 + + VMAXPSZ256rmbkz = 12956 + + VMAXPSZ256rmk = 12957 + + VMAXPSZ256rmkz = 12958 + + VMAXPSZ256rr = 12959 + + VMAXPSZ256rrk = 12960 + + VMAXPSZ256rrkz = 12961 + + VMAXPSZrm = 12962 + + VMAXPSZrmb = 12963 + + VMAXPSZrmbk = 12964 + + VMAXPSZrmbkz = 12965 + + VMAXPSZrmk = 12966 + + VMAXPSZrmkz = 12967 + + VMAXPSZrr = 12968 + + VMAXPSZrrb = 12969 + + VMAXPSZrrbk = 12970 + + VMAXPSZrrbkz = 12971 + + VMAXPSZrrk = 12972 + + VMAXPSZrrkz = 12973 + + VMAXPSrm = 12974 + + VMAXPSrr = 12975 + + VMAXSDZrm = 12976 + + VMAXSDZrm_Int = 12977 + + VMAXSDZrmk_Int = 12978 + + VMAXSDZrmkz_Int = 12979 + + VMAXSDZrr = 12980 + + VMAXSDZrr_Int = 12981 + + VMAXSDZrrb_Int = 12982 + + VMAXSDZrrbk_Int = 12983 + + VMAXSDZrrbkz_Int = 12984 + + VMAXSDZrrk_Int = 12985 + + VMAXSDZrrkz_Int = 12986 + + VMAXSDrm = 12987 + + VMAXSDrm_Int = 12988 + + VMAXSDrr = 12989 + + VMAXSDrr_Int = 12990 + + VMAXSHZrm = 12991 + + VMAXSHZrm_Int = 12992 + + VMAXSHZrmk_Int = 12993 + + VMAXSHZrmkz_Int = 12994 + + VMAXSHZrr = 12995 + + VMAXSHZrr_Int = 12996 + + VMAXSHZrrb_Int = 12997 + + VMAXSHZrrbk_Int = 12998 + + VMAXSHZrrbkz_Int = 12999 + + VMAXSHZrrk_Int = 13000 + + VMAXSHZrrkz_Int = 13001 + + VMAXSSZrm = 13002 + + VMAXSSZrm_Int = 13003 + + VMAXSSZrmk_Int = 13004 + + VMAXSSZrmkz_Int = 13005 + + VMAXSSZrr = 13006 + + VMAXSSZrr_Int = 13007 + + VMAXSSZrrb_Int = 13008 + + VMAXSSZrrbk_Int = 13009 + + VMAXSSZrrbkz_Int = 13010 + + VMAXSSZrrk_Int = 13011 + + VMAXSSZrrkz_Int = 13012 + + VMAXSSrm = 13013 + + VMAXSSrm_Int = 13014 + + VMAXSSrr = 13015 + + VMAXSSrr_Int = 13016 + + VMCALL = 13017 + + VMCLEARm = 13018 + + VMFUNC = 13019 + + VMINBF16Z128rm = 13020 + + VMINBF16Z128rmb = 13021 + + VMINBF16Z128rmbk = 13022 + + VMINBF16Z128rmbkz = 13023 + + VMINBF16Z128rmk = 13024 + + VMINBF16Z128rmkz = 13025 + + VMINBF16Z128rr = 13026 + + VMINBF16Z128rrk = 13027 + + VMINBF16Z128rrkz = 13028 + + VMINBF16Z256rm = 13029 + + VMINBF16Z256rmb = 13030 + + VMINBF16Z256rmbk = 13031 + + VMINBF16Z256rmbkz = 13032 + + VMINBF16Z256rmk = 13033 + + VMINBF16Z256rmkz = 13034 + + VMINBF16Z256rr = 13035 + + VMINBF16Z256rrk = 13036 + + VMINBF16Z256rrkz = 13037 + + VMINBF16Zrm = 13038 + + VMINBF16Zrmb = 13039 + + VMINBF16Zrmbk = 13040 + + VMINBF16Zrmbkz = 13041 + + VMINBF16Zrmk = 13042 + + VMINBF16Zrmkz = 13043 + + VMINBF16Zrr = 13044 + + VMINBF16Zrrk = 13045 + + VMINBF16Zrrkz = 13046 + + VMINCPDYrm = 13047 + + VMINCPDYrr = 13048 + + VMINCPDZ128rm = 13049 + + VMINCPDZ128rmb = 13050 + + VMINCPDZ128rmbk = 13051 + + VMINCPDZ128rmbkz = 13052 + + VMINCPDZ128rmk = 13053 + + VMINCPDZ128rmkz = 13054 + + VMINCPDZ128rr = 13055 + + VMINCPDZ128rrk = 13056 + + VMINCPDZ128rrkz = 13057 + + VMINCPDZ256rm = 13058 + + VMINCPDZ256rmb = 13059 + + VMINCPDZ256rmbk = 13060 + + VMINCPDZ256rmbkz = 13061 + + VMINCPDZ256rmk = 13062 + + VMINCPDZ256rmkz = 13063 + + VMINCPDZ256rr = 13064 + + VMINCPDZ256rrk = 13065 + + VMINCPDZ256rrkz = 13066 + + VMINCPDZrm = 13067 + + VMINCPDZrmb = 13068 + + VMINCPDZrmbk = 13069 + + VMINCPDZrmbkz = 13070 + + VMINCPDZrmk = 13071 + + VMINCPDZrmkz = 13072 + + VMINCPDZrr = 13073 + + VMINCPDZrrk = 13074 + + VMINCPDZrrkz = 13075 + + VMINCPDrm = 13076 + + VMINCPDrr = 13077 + + VMINCPHZ128rm = 13078 + + VMINCPHZ128rmb = 13079 + + VMINCPHZ128rmbk = 13080 + + VMINCPHZ128rmbkz = 13081 + + VMINCPHZ128rmk = 13082 + + VMINCPHZ128rmkz = 13083 + + VMINCPHZ128rr = 13084 + + VMINCPHZ128rrk = 13085 + + VMINCPHZ128rrkz = 13086 + + VMINCPHZ256rm = 13087 + + VMINCPHZ256rmb = 13088 + + VMINCPHZ256rmbk = 13089 + + VMINCPHZ256rmbkz = 13090 + + VMINCPHZ256rmk = 13091 + + VMINCPHZ256rmkz = 13092 + + VMINCPHZ256rr = 13093 + + VMINCPHZ256rrk = 13094 + + VMINCPHZ256rrkz = 13095 + + VMINCPHZrm = 13096 + + VMINCPHZrmb = 13097 + + VMINCPHZrmbk = 13098 + + VMINCPHZrmbkz = 13099 + + VMINCPHZrmk = 13100 + + VMINCPHZrmkz = 13101 + + VMINCPHZrr = 13102 + + VMINCPHZrrk = 13103 + + VMINCPHZrrkz = 13104 + + VMINCPSYrm = 13105 + + VMINCPSYrr = 13106 + + VMINCPSZ128rm = 13107 + + VMINCPSZ128rmb = 13108 + + VMINCPSZ128rmbk = 13109 + + VMINCPSZ128rmbkz = 13110 + + VMINCPSZ128rmk = 13111 + + VMINCPSZ128rmkz = 13112 + + VMINCPSZ128rr = 13113 + + VMINCPSZ128rrk = 13114 + + VMINCPSZ128rrkz = 13115 + + VMINCPSZ256rm = 13116 + + VMINCPSZ256rmb = 13117 + + VMINCPSZ256rmbk = 13118 + + VMINCPSZ256rmbkz = 13119 + + VMINCPSZ256rmk = 13120 + + VMINCPSZ256rmkz = 13121 + + VMINCPSZ256rr = 13122 + + VMINCPSZ256rrk = 13123 + + VMINCPSZ256rrkz = 13124 + + VMINCPSZrm = 13125 + + VMINCPSZrmb = 13126 + + VMINCPSZrmbk = 13127 + + VMINCPSZrmbkz = 13128 + + VMINCPSZrmk = 13129 + + VMINCPSZrmkz = 13130 + + VMINCPSZrr = 13131 + + VMINCPSZrrk = 13132 + + VMINCPSZrrkz = 13133 + + VMINCPSrm = 13134 + + VMINCPSrr = 13135 + + VMINCSDZrm = 13136 + + VMINCSDZrr = 13137 + + VMINCSDrm = 13138 + + VMINCSDrr = 13139 + + VMINCSHZrm = 13140 + + VMINCSHZrr = 13141 + + VMINCSSZrm = 13142 + + VMINCSSZrr = 13143 + + VMINCSSrm = 13144 + + VMINCSSrr = 13145 + + VMINMAXBF16Z128rmbi = 13146 + + VMINMAXBF16Z128rmbik = 13147 + + VMINMAXBF16Z128rmbikz = 13148 + + VMINMAXBF16Z128rmi = 13149 + + VMINMAXBF16Z128rmik = 13150 + + VMINMAXBF16Z128rmikz = 13151 + + VMINMAXBF16Z128rri = 13152 + + VMINMAXBF16Z128rrik = 13153 + + VMINMAXBF16Z128rrikz = 13154 + + VMINMAXBF16Z256rmbi = 13155 + + VMINMAXBF16Z256rmbik = 13156 + + VMINMAXBF16Z256rmbikz = 13157 + + VMINMAXBF16Z256rmi = 13158 + + VMINMAXBF16Z256rmik = 13159 + + VMINMAXBF16Z256rmikz = 13160 + + VMINMAXBF16Z256rri = 13161 + + VMINMAXBF16Z256rrik = 13162 + + VMINMAXBF16Z256rrikz = 13163 + + VMINMAXBF16Zrmbi = 13164 + + VMINMAXBF16Zrmbik = 13165 + + VMINMAXBF16Zrmbikz = 13166 + + VMINMAXBF16Zrmi = 13167 + + VMINMAXBF16Zrmik = 13168 + + VMINMAXBF16Zrmikz = 13169 + + VMINMAXBF16Zrri = 13170 + + VMINMAXBF16Zrrik = 13171 + + VMINMAXBF16Zrrikz = 13172 + + VMINMAXPDZ128rmbi = 13173 + + VMINMAXPDZ128rmbik = 13174 + + VMINMAXPDZ128rmbikz = 13175 + + VMINMAXPDZ128rmi = 13176 + + VMINMAXPDZ128rmik = 13177 + + VMINMAXPDZ128rmikz = 13178 + + VMINMAXPDZ128rri = 13179 + + VMINMAXPDZ128rrik = 13180 + + VMINMAXPDZ128rrikz = 13181 + + VMINMAXPDZ256rmbi = 13182 + + VMINMAXPDZ256rmbik = 13183 + + VMINMAXPDZ256rmbikz = 13184 + + VMINMAXPDZ256rmi = 13185 + + VMINMAXPDZ256rmik = 13186 + + VMINMAXPDZ256rmikz = 13187 + + VMINMAXPDZ256rri = 13188 + + VMINMAXPDZ256rrik = 13189 + + VMINMAXPDZ256rrikz = 13190 + + VMINMAXPDZrmbi = 13191 + + VMINMAXPDZrmbik = 13192 + + VMINMAXPDZrmbikz = 13193 + + VMINMAXPDZrmi = 13194 + + VMINMAXPDZrmik = 13195 + + VMINMAXPDZrmikz = 13196 + + VMINMAXPDZrri = 13197 + + VMINMAXPDZrrib = 13198 + + VMINMAXPDZrribk = 13199 + + VMINMAXPDZrribkz = 13200 + + VMINMAXPDZrrik = 13201 + + VMINMAXPDZrrikz = 13202 + + VMINMAXPHZ128rmbi = 13203 + + VMINMAXPHZ128rmbik = 13204 + + VMINMAXPHZ128rmbikz = 13205 + + VMINMAXPHZ128rmi = 13206 + + VMINMAXPHZ128rmik = 13207 + + VMINMAXPHZ128rmikz = 13208 + + VMINMAXPHZ128rri = 13209 + + VMINMAXPHZ128rrik = 13210 + + VMINMAXPHZ128rrikz = 13211 + + VMINMAXPHZ256rmbi = 13212 + + VMINMAXPHZ256rmbik = 13213 + + VMINMAXPHZ256rmbikz = 13214 + + VMINMAXPHZ256rmi = 13215 + + VMINMAXPHZ256rmik = 13216 + + VMINMAXPHZ256rmikz = 13217 + + VMINMAXPHZ256rri = 13218 + + VMINMAXPHZ256rrik = 13219 + + VMINMAXPHZ256rrikz = 13220 + + VMINMAXPHZrmbi = 13221 + + VMINMAXPHZrmbik = 13222 + + VMINMAXPHZrmbikz = 13223 + + VMINMAXPHZrmi = 13224 + + VMINMAXPHZrmik = 13225 + + VMINMAXPHZrmikz = 13226 + + VMINMAXPHZrri = 13227 + + VMINMAXPHZrrib = 13228 + + VMINMAXPHZrribk = 13229 + + VMINMAXPHZrribkz = 13230 + + VMINMAXPHZrrik = 13231 + + VMINMAXPHZrrikz = 13232 + + VMINMAXPSZ128rmbi = 13233 + + VMINMAXPSZ128rmbik = 13234 + + VMINMAXPSZ128rmbikz = 13235 + + VMINMAXPSZ128rmi = 13236 + + VMINMAXPSZ128rmik = 13237 + + VMINMAXPSZ128rmikz = 13238 + + VMINMAXPSZ128rri = 13239 + + VMINMAXPSZ128rrik = 13240 + + VMINMAXPSZ128rrikz = 13241 + + VMINMAXPSZ256rmbi = 13242 + + VMINMAXPSZ256rmbik = 13243 + + VMINMAXPSZ256rmbikz = 13244 + + VMINMAXPSZ256rmi = 13245 + + VMINMAXPSZ256rmik = 13246 + + VMINMAXPSZ256rmikz = 13247 + + VMINMAXPSZ256rri = 13248 + + VMINMAXPSZ256rrik = 13249 + + VMINMAXPSZ256rrikz = 13250 + + VMINMAXPSZrmbi = 13251 + + VMINMAXPSZrmbik = 13252 + + VMINMAXPSZrmbikz = 13253 + + VMINMAXPSZrmi = 13254 + + VMINMAXPSZrmik = 13255 + + VMINMAXPSZrmikz = 13256 + + VMINMAXPSZrri = 13257 + + VMINMAXPSZrrib = 13258 + + VMINMAXPSZrribk = 13259 + + VMINMAXPSZrribkz = 13260 + + VMINMAXPSZrrik = 13261 + + VMINMAXPSZrrikz = 13262 + + VMINMAXSDrmi = 13263 + + VMINMAXSDrmi_Int = 13264 + + VMINMAXSDrmik_Int = 13265 + + VMINMAXSDrmikz_Int = 13266 + + VMINMAXSDrri = 13267 + + VMINMAXSDrri_Int = 13268 + + VMINMAXSDrrib_Int = 13269 + + VMINMAXSDrribk_Int = 13270 + + VMINMAXSDrribkz_Int = 13271 + + VMINMAXSDrrik_Int = 13272 + + VMINMAXSDrrikz_Int = 13273 + + VMINMAXSHrmi = 13274 + + VMINMAXSHrmi_Int = 13275 + + VMINMAXSHrmik_Int = 13276 + + VMINMAXSHrmikz_Int = 13277 + + VMINMAXSHrri = 13278 + + VMINMAXSHrri_Int = 13279 + + VMINMAXSHrrib_Int = 13280 + + VMINMAXSHrribk_Int = 13281 + + VMINMAXSHrribkz_Int = 13282 + + VMINMAXSHrrik_Int = 13283 + + VMINMAXSHrrikz_Int = 13284 + + VMINMAXSSrmi = 13285 + + VMINMAXSSrmi_Int = 13286 + + VMINMAXSSrmik_Int = 13287 + + VMINMAXSSrmikz_Int = 13288 + + VMINMAXSSrri = 13289 + + VMINMAXSSrri_Int = 13290 + + VMINMAXSSrrib_Int = 13291 + + VMINMAXSSrribk_Int = 13292 + + VMINMAXSSrribkz_Int = 13293 + + VMINMAXSSrrik_Int = 13294 + + VMINMAXSSrrikz_Int = 13295 + + VMINPDYrm = 13296 + + VMINPDYrr = 13297 + + VMINPDZ128rm = 13298 + + VMINPDZ128rmb = 13299 + + VMINPDZ128rmbk = 13300 + + VMINPDZ128rmbkz = 13301 + + VMINPDZ128rmk = 13302 + + VMINPDZ128rmkz = 13303 + + VMINPDZ128rr = 13304 + + VMINPDZ128rrk = 13305 + + VMINPDZ128rrkz = 13306 + + VMINPDZ256rm = 13307 + + VMINPDZ256rmb = 13308 + + VMINPDZ256rmbk = 13309 + + VMINPDZ256rmbkz = 13310 + + VMINPDZ256rmk = 13311 + + VMINPDZ256rmkz = 13312 + + VMINPDZ256rr = 13313 + + VMINPDZ256rrk = 13314 + + VMINPDZ256rrkz = 13315 + + VMINPDZrm = 13316 + + VMINPDZrmb = 13317 + + VMINPDZrmbk = 13318 + + VMINPDZrmbkz = 13319 + + VMINPDZrmk = 13320 + + VMINPDZrmkz = 13321 + + VMINPDZrr = 13322 + + VMINPDZrrb = 13323 + + VMINPDZrrbk = 13324 + + VMINPDZrrbkz = 13325 + + VMINPDZrrk = 13326 + + VMINPDZrrkz = 13327 + + VMINPDrm = 13328 + + VMINPDrr = 13329 + + VMINPHZ128rm = 13330 + + VMINPHZ128rmb = 13331 + + VMINPHZ128rmbk = 13332 + + VMINPHZ128rmbkz = 13333 + + VMINPHZ128rmk = 13334 + + VMINPHZ128rmkz = 13335 + + VMINPHZ128rr = 13336 + + VMINPHZ128rrk = 13337 + + VMINPHZ128rrkz = 13338 + + VMINPHZ256rm = 13339 + + VMINPHZ256rmb = 13340 + + VMINPHZ256rmbk = 13341 + + VMINPHZ256rmbkz = 13342 + + VMINPHZ256rmk = 13343 + + VMINPHZ256rmkz = 13344 + + VMINPHZ256rr = 13345 + + VMINPHZ256rrk = 13346 + + VMINPHZ256rrkz = 13347 + + VMINPHZrm = 13348 + + VMINPHZrmb = 13349 + + VMINPHZrmbk = 13350 + + VMINPHZrmbkz = 13351 + + VMINPHZrmk = 13352 + + VMINPHZrmkz = 13353 + + VMINPHZrr = 13354 + + VMINPHZrrb = 13355 + + VMINPHZrrbk = 13356 + + VMINPHZrrbkz = 13357 + + VMINPHZrrk = 13358 + + VMINPHZrrkz = 13359 + + VMINPSYrm = 13360 + + VMINPSYrr = 13361 + + VMINPSZ128rm = 13362 + + VMINPSZ128rmb = 13363 + + VMINPSZ128rmbk = 13364 + + VMINPSZ128rmbkz = 13365 + + VMINPSZ128rmk = 13366 + + VMINPSZ128rmkz = 13367 + + VMINPSZ128rr = 13368 + + VMINPSZ128rrk = 13369 + + VMINPSZ128rrkz = 13370 + + VMINPSZ256rm = 13371 + + VMINPSZ256rmb = 13372 + + VMINPSZ256rmbk = 13373 + + VMINPSZ256rmbkz = 13374 + + VMINPSZ256rmk = 13375 + + VMINPSZ256rmkz = 13376 + + VMINPSZ256rr = 13377 + + VMINPSZ256rrk = 13378 + + VMINPSZ256rrkz = 13379 + + VMINPSZrm = 13380 + + VMINPSZrmb = 13381 + + VMINPSZrmbk = 13382 + + VMINPSZrmbkz = 13383 + + VMINPSZrmk = 13384 + + VMINPSZrmkz = 13385 + + VMINPSZrr = 13386 + + VMINPSZrrb = 13387 + + VMINPSZrrbk = 13388 + + VMINPSZrrbkz = 13389 + + VMINPSZrrk = 13390 + + VMINPSZrrkz = 13391 + + VMINPSrm = 13392 + + VMINPSrr = 13393 + + VMINSDZrm = 13394 + + VMINSDZrm_Int = 13395 + + VMINSDZrmk_Int = 13396 + + VMINSDZrmkz_Int = 13397 + + VMINSDZrr = 13398 + + VMINSDZrr_Int = 13399 + + VMINSDZrrb_Int = 13400 + + VMINSDZrrbk_Int = 13401 + + VMINSDZrrbkz_Int = 13402 + + VMINSDZrrk_Int = 13403 + + VMINSDZrrkz_Int = 13404 + + VMINSDrm = 13405 + + VMINSDrm_Int = 13406 + + VMINSDrr = 13407 + + VMINSDrr_Int = 13408 + + VMINSHZrm = 13409 + + VMINSHZrm_Int = 13410 + + VMINSHZrmk_Int = 13411 + + VMINSHZrmkz_Int = 13412 + + VMINSHZrr = 13413 + + VMINSHZrr_Int = 13414 + + VMINSHZrrb_Int = 13415 + + VMINSHZrrbk_Int = 13416 + + VMINSHZrrbkz_Int = 13417 + + VMINSHZrrk_Int = 13418 + + VMINSHZrrkz_Int = 13419 + + VMINSSZrm = 13420 + + VMINSSZrm_Int = 13421 + + VMINSSZrmk_Int = 13422 + + VMINSSZrmkz_Int = 13423 + + VMINSSZrr = 13424 + + VMINSSZrr_Int = 13425 + + VMINSSZrrb_Int = 13426 + + VMINSSZrrbk_Int = 13427 + + VMINSSZrrbkz_Int = 13428 + + VMINSSZrrk_Int = 13429 + + VMINSSZrrkz_Int = 13430 + + VMINSSrm = 13431 + + VMINSSrm_Int = 13432 + + VMINSSrr = 13433 + + VMINSSrr_Int = 13434 + + VMLAUNCH = 13435 + + VMLOAD32 = 13436 + + VMLOAD64 = 13437 + + VMMCALL = 13438 + + VMOV64toPQIZrm = 13439 + + VMOV64toPQIZrr = 13440 + + VMOV64toPQIrm = 13441 + + VMOV64toPQIrr = 13442 + + VMOV64toSDZrr = 13443 + + VMOV64toSDrr = 13444 + + VMOVAPDYmr = 13445 + + VMOVAPDYrm = 13446 + + VMOVAPDYrr = 13447 + + VMOVAPDYrr_REV = 13448 + + VMOVAPDZ128mr = 13449 + + VMOVAPDZ128mrk = 13450 + + VMOVAPDZ128rm = 13451 + + VMOVAPDZ128rmk = 13452 + + VMOVAPDZ128rmkz = 13453 + + VMOVAPDZ128rr = 13454 + + VMOVAPDZ128rr_REV = 13455 + + VMOVAPDZ128rrk = 13456 + + VMOVAPDZ128rrk_REV = 13457 + + VMOVAPDZ128rrkz = 13458 + + VMOVAPDZ128rrkz_REV = 13459 + + VMOVAPDZ256mr = 13460 + + VMOVAPDZ256mrk = 13461 + + VMOVAPDZ256rm = 13462 + + VMOVAPDZ256rmk = 13463 + + VMOVAPDZ256rmkz = 13464 + + VMOVAPDZ256rr = 13465 + + VMOVAPDZ256rr_REV = 13466 + + VMOVAPDZ256rrk = 13467 + + VMOVAPDZ256rrk_REV = 13468 + + VMOVAPDZ256rrkz = 13469 + + VMOVAPDZ256rrkz_REV = 13470 + + VMOVAPDZmr = 13471 + + VMOVAPDZmrk = 13472 + + VMOVAPDZrm = 13473 + + VMOVAPDZrmk = 13474 + + VMOVAPDZrmkz = 13475 + + VMOVAPDZrr = 13476 + + VMOVAPDZrr_REV = 13477 + + VMOVAPDZrrk = 13478 + + VMOVAPDZrrk_REV = 13479 + + VMOVAPDZrrkz = 13480 + + VMOVAPDZrrkz_REV = 13481 + + VMOVAPDmr = 13482 + + VMOVAPDrm = 13483 + + VMOVAPDrr = 13484 + + VMOVAPDrr_REV = 13485 + + VMOVAPSYmr = 13486 + + VMOVAPSYrm = 13487 + + VMOVAPSYrr = 13488 + + VMOVAPSYrr_REV = 13489 + + VMOVAPSZ128mr = 13490 + + VMOVAPSZ128mrk = 13491 + + VMOVAPSZ128rm = 13492 + + VMOVAPSZ128rmk = 13493 + + VMOVAPSZ128rmkz = 13494 + + VMOVAPSZ128rr = 13495 + + VMOVAPSZ128rr_REV = 13496 + + VMOVAPSZ128rrk = 13497 + + VMOVAPSZ128rrk_REV = 13498 + + VMOVAPSZ128rrkz = 13499 + + VMOVAPSZ128rrkz_REV = 13500 + + VMOVAPSZ256mr = 13501 + + VMOVAPSZ256mrk = 13502 + + VMOVAPSZ256rm = 13503 + + VMOVAPSZ256rmk = 13504 + + VMOVAPSZ256rmkz = 13505 + + VMOVAPSZ256rr = 13506 + + VMOVAPSZ256rr_REV = 13507 + + VMOVAPSZ256rrk = 13508 + + VMOVAPSZ256rrk_REV = 13509 + + VMOVAPSZ256rrkz = 13510 + + VMOVAPSZ256rrkz_REV = 13511 + + VMOVAPSZmr = 13512 + + VMOVAPSZmrk = 13513 + + VMOVAPSZrm = 13514 + + VMOVAPSZrmk = 13515 + + VMOVAPSZrmkz = 13516 + + VMOVAPSZrr = 13517 + + VMOVAPSZrr_REV = 13518 + + VMOVAPSZrrk = 13519 + + VMOVAPSZrrk_REV = 13520 + + VMOVAPSZrrkz = 13521 + + VMOVAPSZrrkz_REV = 13522 + + VMOVAPSmr = 13523 + + VMOVAPSrm = 13524 + + VMOVAPSrr = 13525 + + VMOVAPSrr_REV = 13526 + + VMOVDDUPYrm = 13527 + + VMOVDDUPYrr = 13528 + + VMOVDDUPZ128rm = 13529 + + VMOVDDUPZ128rmk = 13530 + + VMOVDDUPZ128rmkz = 13531 + + VMOVDDUPZ128rr = 13532 + + VMOVDDUPZ128rrk = 13533 + + VMOVDDUPZ128rrkz = 13534 + + VMOVDDUPZ256rm = 13535 + + VMOVDDUPZ256rmk = 13536 + + VMOVDDUPZ256rmkz = 13537 + + VMOVDDUPZ256rr = 13538 + + VMOVDDUPZ256rrk = 13539 + + VMOVDDUPZ256rrkz = 13540 + + VMOVDDUPZrm = 13541 + + VMOVDDUPZrmk = 13542 + + VMOVDDUPZrmkz = 13543 + + VMOVDDUPZrr = 13544 + + VMOVDDUPZrrk = 13545 + + VMOVDDUPZrrkz = 13546 + + VMOVDDUPrm = 13547 + + VMOVDDUPrr = 13548 + + VMOVDI2PDIZrm = 13549 + + VMOVDI2PDIZrr = 13550 + + VMOVDI2PDIrm = 13551 + + VMOVDI2PDIrr = 13552 + + VMOVDI2SSZrr = 13553 + + VMOVDI2SSrr = 13554 + + VMOVDQA32Z128mr = 13555 + + VMOVDQA32Z128mrk = 13556 + + VMOVDQA32Z128rm = 13557 + + VMOVDQA32Z128rmk = 13558 + + VMOVDQA32Z128rmkz = 13559 + + VMOVDQA32Z128rr = 13560 + + VMOVDQA32Z128rr_REV = 13561 + + VMOVDQA32Z128rrk = 13562 + + VMOVDQA32Z128rrk_REV = 13563 + + VMOVDQA32Z128rrkz = 13564 + + VMOVDQA32Z128rrkz_REV = 13565 + + VMOVDQA32Z256mr = 13566 + + VMOVDQA32Z256mrk = 13567 + + VMOVDQA32Z256rm = 13568 + + VMOVDQA32Z256rmk = 13569 + + VMOVDQA32Z256rmkz = 13570 + + VMOVDQA32Z256rr = 13571 + + VMOVDQA32Z256rr_REV = 13572 + + VMOVDQA32Z256rrk = 13573 + + VMOVDQA32Z256rrk_REV = 13574 + + VMOVDQA32Z256rrkz = 13575 + + VMOVDQA32Z256rrkz_REV = 13576 + + VMOVDQA32Zmr = 13577 + + VMOVDQA32Zmrk = 13578 + + VMOVDQA32Zrm = 13579 + + VMOVDQA32Zrmk = 13580 + + VMOVDQA32Zrmkz = 13581 + + VMOVDQA32Zrr = 13582 + + VMOVDQA32Zrr_REV = 13583 + + VMOVDQA32Zrrk = 13584 + + VMOVDQA32Zrrk_REV = 13585 + + VMOVDQA32Zrrkz = 13586 + + VMOVDQA32Zrrkz_REV = 13587 + + VMOVDQA64Z128mr = 13588 + + VMOVDQA64Z128mrk = 13589 + + VMOVDQA64Z128rm = 13590 + + VMOVDQA64Z128rmk = 13591 + + VMOVDQA64Z128rmkz = 13592 + + VMOVDQA64Z128rr = 13593 + + VMOVDQA64Z128rr_REV = 13594 + + VMOVDQA64Z128rrk = 13595 + + VMOVDQA64Z128rrk_REV = 13596 + + VMOVDQA64Z128rrkz = 13597 + + VMOVDQA64Z128rrkz_REV = 13598 + + VMOVDQA64Z256mr = 13599 + + VMOVDQA64Z256mrk = 13600 + + VMOVDQA64Z256rm = 13601 + + VMOVDQA64Z256rmk = 13602 + + VMOVDQA64Z256rmkz = 13603 + + VMOVDQA64Z256rr = 13604 + + VMOVDQA64Z256rr_REV = 13605 + + VMOVDQA64Z256rrk = 13606 + + VMOVDQA64Z256rrk_REV = 13607 + + VMOVDQA64Z256rrkz = 13608 + + VMOVDQA64Z256rrkz_REV = 13609 + + VMOVDQA64Zmr = 13610 + + VMOVDQA64Zmrk = 13611 + + VMOVDQA64Zrm = 13612 + + VMOVDQA64Zrmk = 13613 + + VMOVDQA64Zrmkz = 13614 + + VMOVDQA64Zrr = 13615 + + VMOVDQA64Zrr_REV = 13616 + + VMOVDQA64Zrrk = 13617 + + VMOVDQA64Zrrk_REV = 13618 + + VMOVDQA64Zrrkz = 13619 + + VMOVDQA64Zrrkz_REV = 13620 + + VMOVDQAYmr = 13621 + + VMOVDQAYrm = 13622 + + VMOVDQAYrr = 13623 + + VMOVDQAYrr_REV = 13624 + + VMOVDQAmr = 13625 + + VMOVDQArm = 13626 + + VMOVDQArr = 13627 + + VMOVDQArr_REV = 13628 + + VMOVDQU16Z128mr = 13629 + + VMOVDQU16Z128mrk = 13630 + + VMOVDQU16Z128rm = 13631 + + VMOVDQU16Z128rmk = 13632 + + VMOVDQU16Z128rmkz = 13633 + + VMOVDQU16Z128rr = 13634 + + VMOVDQU16Z128rr_REV = 13635 + + VMOVDQU16Z128rrk = 13636 + + VMOVDQU16Z128rrk_REV = 13637 + + VMOVDQU16Z128rrkz = 13638 + + VMOVDQU16Z128rrkz_REV = 13639 + + VMOVDQU16Z256mr = 13640 + + VMOVDQU16Z256mrk = 13641 + + VMOVDQU16Z256rm = 13642 + + VMOVDQU16Z256rmk = 13643 + + VMOVDQU16Z256rmkz = 13644 + + VMOVDQU16Z256rr = 13645 + + VMOVDQU16Z256rr_REV = 13646 + + VMOVDQU16Z256rrk = 13647 + + VMOVDQU16Z256rrk_REV = 13648 + + VMOVDQU16Z256rrkz = 13649 + + VMOVDQU16Z256rrkz_REV = 13650 + + VMOVDQU16Zmr = 13651 + + VMOVDQU16Zmrk = 13652 + + VMOVDQU16Zrm = 13653 + + VMOVDQU16Zrmk = 13654 + + VMOVDQU16Zrmkz = 13655 + + VMOVDQU16Zrr = 13656 + + VMOVDQU16Zrr_REV = 13657 + + VMOVDQU16Zrrk = 13658 + + VMOVDQU16Zrrk_REV = 13659 + + VMOVDQU16Zrrkz = 13660 + + VMOVDQU16Zrrkz_REV = 13661 + + VMOVDQU32Z128mr = 13662 + + VMOVDQU32Z128mrk = 13663 + + VMOVDQU32Z128rm = 13664 + + VMOVDQU32Z128rmk = 13665 + + VMOVDQU32Z128rmkz = 13666 + + VMOVDQU32Z128rr = 13667 + + VMOVDQU32Z128rr_REV = 13668 + + VMOVDQU32Z128rrk = 13669 + + VMOVDQU32Z128rrk_REV = 13670 + + VMOVDQU32Z128rrkz = 13671 + + VMOVDQU32Z128rrkz_REV = 13672 + + VMOVDQU32Z256mr = 13673 + + VMOVDQU32Z256mrk = 13674 + + VMOVDQU32Z256rm = 13675 + + VMOVDQU32Z256rmk = 13676 + + VMOVDQU32Z256rmkz = 13677 + + VMOVDQU32Z256rr = 13678 + + VMOVDQU32Z256rr_REV = 13679 + + VMOVDQU32Z256rrk = 13680 + + VMOVDQU32Z256rrk_REV = 13681 + + VMOVDQU32Z256rrkz = 13682 + + VMOVDQU32Z256rrkz_REV = 13683 + + VMOVDQU32Zmr = 13684 + + VMOVDQU32Zmrk = 13685 + + VMOVDQU32Zrm = 13686 + + VMOVDQU32Zrmk = 13687 + + VMOVDQU32Zrmkz = 13688 + + VMOVDQU32Zrr = 13689 + + VMOVDQU32Zrr_REV = 13690 + + VMOVDQU32Zrrk = 13691 + + VMOVDQU32Zrrk_REV = 13692 + + VMOVDQU32Zrrkz = 13693 + + VMOVDQU32Zrrkz_REV = 13694 + + VMOVDQU64Z128mr = 13695 + + VMOVDQU64Z128mrk = 13696 + + VMOVDQU64Z128rm = 13697 + + VMOVDQU64Z128rmk = 13698 + + VMOVDQU64Z128rmkz = 13699 + + VMOVDQU64Z128rr = 13700 + + VMOVDQU64Z128rr_REV = 13701 + + VMOVDQU64Z128rrk = 13702 + + VMOVDQU64Z128rrk_REV = 13703 + + VMOVDQU64Z128rrkz = 13704 + + VMOVDQU64Z128rrkz_REV = 13705 + + VMOVDQU64Z256mr = 13706 + + VMOVDQU64Z256mrk = 13707 + + VMOVDQU64Z256rm = 13708 + + VMOVDQU64Z256rmk = 13709 + + VMOVDQU64Z256rmkz = 13710 + + VMOVDQU64Z256rr = 13711 + + VMOVDQU64Z256rr_REV = 13712 + + VMOVDQU64Z256rrk = 13713 + + VMOVDQU64Z256rrk_REV = 13714 + + VMOVDQU64Z256rrkz = 13715 + + VMOVDQU64Z256rrkz_REV = 13716 + + VMOVDQU64Zmr = 13717 + + VMOVDQU64Zmrk = 13718 + + VMOVDQU64Zrm = 13719 + + VMOVDQU64Zrmk = 13720 + + VMOVDQU64Zrmkz = 13721 + + VMOVDQU64Zrr = 13722 + + VMOVDQU64Zrr_REV = 13723 + + VMOVDQU64Zrrk = 13724 + + VMOVDQU64Zrrk_REV = 13725 + + VMOVDQU64Zrrkz = 13726 + + VMOVDQU64Zrrkz_REV = 13727 + + VMOVDQU8Z128mr = 13728 + + VMOVDQU8Z128mrk = 13729 + + VMOVDQU8Z128rm = 13730 + + VMOVDQU8Z128rmk = 13731 + + VMOVDQU8Z128rmkz = 13732 + + VMOVDQU8Z128rr = 13733 + + VMOVDQU8Z128rr_REV = 13734 + + VMOVDQU8Z128rrk = 13735 + + VMOVDQU8Z128rrk_REV = 13736 + + VMOVDQU8Z128rrkz = 13737 + + VMOVDQU8Z128rrkz_REV = 13738 + + VMOVDQU8Z256mr = 13739 + + VMOVDQU8Z256mrk = 13740 + + VMOVDQU8Z256rm = 13741 + + VMOVDQU8Z256rmk = 13742 + + VMOVDQU8Z256rmkz = 13743 + + VMOVDQU8Z256rr = 13744 + + VMOVDQU8Z256rr_REV = 13745 + + VMOVDQU8Z256rrk = 13746 + + VMOVDQU8Z256rrk_REV = 13747 + + VMOVDQU8Z256rrkz = 13748 + + VMOVDQU8Z256rrkz_REV = 13749 + + VMOVDQU8Zmr = 13750 + + VMOVDQU8Zmrk = 13751 + + VMOVDQU8Zrm = 13752 + + VMOVDQU8Zrmk = 13753 + + VMOVDQU8Zrmkz = 13754 + + VMOVDQU8Zrr = 13755 + + VMOVDQU8Zrr_REV = 13756 + + VMOVDQU8Zrrk = 13757 + + VMOVDQU8Zrrk_REV = 13758 + + VMOVDQU8Zrrkz = 13759 + + VMOVDQU8Zrrkz_REV = 13760 + + VMOVDQUYmr = 13761 + + VMOVDQUYrm = 13762 + + VMOVDQUYrr = 13763 + + VMOVDQUYrr_REV = 13764 + + VMOVDQUmr = 13765 + + VMOVDQUrm = 13766 + + VMOVDQUrr = 13767 + + VMOVDQUrr_REV = 13768 + + VMOVHLPSZrr = 13769 + + VMOVHLPSrr = 13770 + + VMOVHPDZ128mr = 13771 + + VMOVHPDZ128rm = 13772 + + VMOVHPDmr = 13773 + + VMOVHPDrm = 13774 + + VMOVHPSZ128mr = 13775 + + VMOVHPSZ128rm = 13776 + + VMOVHPSmr = 13777 + + VMOVHPSrm = 13778 + + VMOVLHPSZrr = 13779 + + VMOVLHPSrr = 13780 + + VMOVLPDZ128mr = 13781 + + VMOVLPDZ128rm = 13782 + + VMOVLPDmr = 13783 + + VMOVLPDrm = 13784 + + VMOVLPSZ128mr = 13785 + + VMOVLPSZ128rm = 13786 + + VMOVLPSmr = 13787 + + VMOVLPSrm = 13788 + + VMOVMSKPDYrr = 13789 + + VMOVMSKPDrr = 13790 + + VMOVMSKPSYrr = 13791 + + VMOVMSKPSrr = 13792 + + VMOVNTDQAYrm = 13793 + + VMOVNTDQAZ128rm = 13794 + + VMOVNTDQAZ256rm = 13795 + + VMOVNTDQAZrm = 13796 + + VMOVNTDQArm = 13797 + + VMOVNTDQYmr = 13798 + + VMOVNTDQZ128mr = 13799 + + VMOVNTDQZ256mr = 13800 + + VMOVNTDQZmr = 13801 + + VMOVNTDQmr = 13802 + + VMOVNTPDYmr = 13803 + + VMOVNTPDZ128mr = 13804 + + VMOVNTPDZ256mr = 13805 + + VMOVNTPDZmr = 13806 + + VMOVNTPDmr = 13807 + + VMOVNTPSYmr = 13808 + + VMOVNTPSZ128mr = 13809 + + VMOVNTPSZ256mr = 13810 + + VMOVNTPSZmr = 13811 + + VMOVNTPSmr = 13812 + + VMOVPDI2DIZmr = 13813 + + VMOVPDI2DIZrr = 13814 + + VMOVPDI2DImr = 13815 + + VMOVPDI2DIrr = 13816 + + VMOVPQI2QIZmr = 13817 + + VMOVPQI2QIZrr = 13818 + + VMOVPQI2QImr = 13819 + + VMOVPQI2QIrr = 13820 + + VMOVPQIto64Zmr = 13821 + + VMOVPQIto64Zrr = 13822 + + VMOVPQIto64mr = 13823 + + VMOVPQIto64rr = 13824 + + VMOVQI2PQIZrm = 13825 + + VMOVQI2PQIrm = 13826 + + VMOVRSBZ128m = 13827 + + VMOVRSBZ128mk = 13828 + + VMOVRSBZ128mkz = 13829 + + VMOVRSBZ256m = 13830 + + VMOVRSBZ256mk = 13831 + + VMOVRSBZ256mkz = 13832 + + VMOVRSBZm = 13833 + + VMOVRSBZmk = 13834 + + VMOVRSBZmkz = 13835 + + VMOVRSDZ128m = 13836 + + VMOVRSDZ128mk = 13837 + + VMOVRSDZ128mkz = 13838 + + VMOVRSDZ256m = 13839 + + VMOVRSDZ256mk = 13840 + + VMOVRSDZ256mkz = 13841 + + VMOVRSDZm = 13842 + + VMOVRSDZmk = 13843 + + VMOVRSDZmkz = 13844 + + VMOVRSQZ128m = 13845 + + VMOVRSQZ128mk = 13846 + + VMOVRSQZ128mkz = 13847 + + VMOVRSQZ256m = 13848 + + VMOVRSQZ256mk = 13849 + + VMOVRSQZ256mkz = 13850 + + VMOVRSQZm = 13851 + + VMOVRSQZmk = 13852 + + VMOVRSQZmkz = 13853 + + VMOVRSWZ128m = 13854 + + VMOVRSWZ128mk = 13855 + + VMOVRSWZ128mkz = 13856 + + VMOVRSWZ256m = 13857 + + VMOVRSWZ256mk = 13858 + + VMOVRSWZ256mkz = 13859 + + VMOVRSWZm = 13860 + + VMOVRSWZmk = 13861 + + VMOVRSWZmkz = 13862 + + VMOVSDZmr = 13863 + + VMOVSDZmrk = 13864 + + VMOVSDZrm = 13865 + + VMOVSDZrm_alt = 13866 + + VMOVSDZrmk = 13867 + + VMOVSDZrmkz = 13868 + + VMOVSDZrr = 13869 + + VMOVSDZrr_REV = 13870 + + VMOVSDZrrk = 13871 + + VMOVSDZrrk_REV = 13872 + + VMOVSDZrrkz = 13873 + + VMOVSDZrrkz_REV = 13874 + + VMOVSDmr = 13875 + + VMOVSDrm = 13876 + + VMOVSDrm_alt = 13877 + + VMOVSDrr = 13878 + + VMOVSDrr_REV = 13879 + + VMOVSDto64Zrr = 13880 + + VMOVSDto64rr = 13881 + + VMOVSH2Wrr = 13882 + + VMOVSHDUPYrm = 13883 + + VMOVSHDUPYrr = 13884 + + VMOVSHDUPZ128rm = 13885 + + VMOVSHDUPZ128rmk = 13886 + + VMOVSHDUPZ128rmkz = 13887 + + VMOVSHDUPZ128rr = 13888 + + VMOVSHDUPZ128rrk = 13889 + + VMOVSHDUPZ128rrkz = 13890 + + VMOVSHDUPZ256rm = 13891 + + VMOVSHDUPZ256rmk = 13892 + + VMOVSHDUPZ256rmkz = 13893 + + VMOVSHDUPZ256rr = 13894 + + VMOVSHDUPZ256rrk = 13895 + + VMOVSHDUPZ256rrkz = 13896 + + VMOVSHDUPZrm = 13897 + + VMOVSHDUPZrmk = 13898 + + VMOVSHDUPZrmkz = 13899 + + VMOVSHDUPZrr = 13900 + + VMOVSHDUPZrrk = 13901 + + VMOVSHDUPZrrkz = 13902 + + VMOVSHDUPrm = 13903 + + VMOVSHDUPrr = 13904 + + VMOVSHZmr = 13905 + + VMOVSHZmrk = 13906 + + VMOVSHZrm = 13907 + + VMOVSHZrm_alt = 13908 + + VMOVSHZrmk = 13909 + + VMOVSHZrmkz = 13910 + + VMOVSHZrr = 13911 + + VMOVSHZrr_REV = 13912 + + VMOVSHZrrk = 13913 + + VMOVSHZrrk_REV = 13914 + + VMOVSHZrrkz = 13915 + + VMOVSHZrrkz_REV = 13916 + + VMOVSHtoW64rr = 13917 + + VMOVSLDUPYrm = 13918 + + VMOVSLDUPYrr = 13919 + + VMOVSLDUPZ128rm = 13920 + + VMOVSLDUPZ128rmk = 13921 + + VMOVSLDUPZ128rmkz = 13922 + + VMOVSLDUPZ128rr = 13923 + + VMOVSLDUPZ128rrk = 13924 + + VMOVSLDUPZ128rrkz = 13925 + + VMOVSLDUPZ256rm = 13926 + + VMOVSLDUPZ256rmk = 13927 + + VMOVSLDUPZ256rmkz = 13928 + + VMOVSLDUPZ256rr = 13929 + + VMOVSLDUPZ256rrk = 13930 + + VMOVSLDUPZ256rrkz = 13931 + + VMOVSLDUPZrm = 13932 + + VMOVSLDUPZrmk = 13933 + + VMOVSLDUPZrmkz = 13934 + + VMOVSLDUPZrr = 13935 + + VMOVSLDUPZrrk = 13936 + + VMOVSLDUPZrrkz = 13937 + + VMOVSLDUPrm = 13938 + + VMOVSLDUPrr = 13939 + + VMOVSS2DIZrr = 13940 + + VMOVSS2DIrr = 13941 + + VMOVSSZmr = 13942 + + VMOVSSZmrk = 13943 + + VMOVSSZrm = 13944 + + VMOVSSZrm_alt = 13945 + + VMOVSSZrmk = 13946 + + VMOVSSZrmkz = 13947 + + VMOVSSZrr = 13948 + + VMOVSSZrr_REV = 13949 + + VMOVSSZrrk = 13950 + + VMOVSSZrrk_REV = 13951 + + VMOVSSZrrkz = 13952 + + VMOVSSZrrkz_REV = 13953 + + VMOVSSmr = 13954 + + VMOVSSrm = 13955 + + VMOVSSrm_alt = 13956 + + VMOVSSrr = 13957 + + VMOVSSrr_REV = 13958 + + VMOVUPDYmr = 13959 + + VMOVUPDYrm = 13960 + + VMOVUPDYrr = 13961 + + VMOVUPDYrr_REV = 13962 + + VMOVUPDZ128mr = 13963 + + VMOVUPDZ128mrk = 13964 + + VMOVUPDZ128rm = 13965 + + VMOVUPDZ128rmk = 13966 + + VMOVUPDZ128rmkz = 13967 + + VMOVUPDZ128rr = 13968 + + VMOVUPDZ128rr_REV = 13969 + + VMOVUPDZ128rrk = 13970 + + VMOVUPDZ128rrk_REV = 13971 + + VMOVUPDZ128rrkz = 13972 + + VMOVUPDZ128rrkz_REV = 13973 + + VMOVUPDZ256mr = 13974 + + VMOVUPDZ256mrk = 13975 + + VMOVUPDZ256rm = 13976 + + VMOVUPDZ256rmk = 13977 + + VMOVUPDZ256rmkz = 13978 + + VMOVUPDZ256rr = 13979 + + VMOVUPDZ256rr_REV = 13980 + + VMOVUPDZ256rrk = 13981 + + VMOVUPDZ256rrk_REV = 13982 + + VMOVUPDZ256rrkz = 13983 + + VMOVUPDZ256rrkz_REV = 13984 + + VMOVUPDZmr = 13985 + + VMOVUPDZmrk = 13986 + + VMOVUPDZrm = 13987 + + VMOVUPDZrmk = 13988 + + VMOVUPDZrmkz = 13989 + + VMOVUPDZrr = 13990 + + VMOVUPDZrr_REV = 13991 + + VMOVUPDZrrk = 13992 + + VMOVUPDZrrk_REV = 13993 + + VMOVUPDZrrkz = 13994 + + VMOVUPDZrrkz_REV = 13995 + + VMOVUPDmr = 13996 + + VMOVUPDrm = 13997 + + VMOVUPDrr = 13998 + + VMOVUPDrr_REV = 13999 + + VMOVUPSYmr = 14000 + + VMOVUPSYrm = 14001 + + VMOVUPSYrr = 14002 + + VMOVUPSYrr_REV = 14003 + + VMOVUPSZ128mr = 14004 + + VMOVUPSZ128mrk = 14005 + + VMOVUPSZ128rm = 14006 + + VMOVUPSZ128rmk = 14007 + + VMOVUPSZ128rmkz = 14008 + + VMOVUPSZ128rr = 14009 + + VMOVUPSZ128rr_REV = 14010 + + VMOVUPSZ128rrk = 14011 + + VMOVUPSZ128rrk_REV = 14012 + + VMOVUPSZ128rrkz = 14013 + + VMOVUPSZ128rrkz_REV = 14014 + + VMOVUPSZ256mr = 14015 + + VMOVUPSZ256mrk = 14016 + + VMOVUPSZ256rm = 14017 + + VMOVUPSZ256rmk = 14018 + + VMOVUPSZ256rmkz = 14019 + + VMOVUPSZ256rr = 14020 + + VMOVUPSZ256rr_REV = 14021 + + VMOVUPSZ256rrk = 14022 + + VMOVUPSZ256rrk_REV = 14023 + + VMOVUPSZ256rrkz = 14024 + + VMOVUPSZ256rrkz_REV = 14025 + + VMOVUPSZmr = 14026 + + VMOVUPSZmrk = 14027 + + VMOVUPSZrm = 14028 + + VMOVUPSZrmk = 14029 + + VMOVUPSZrmkz = 14030 + + VMOVUPSZrr = 14031 + + VMOVUPSZrr_REV = 14032 + + VMOVUPSZrrk = 14033 + + VMOVUPSZrrk_REV = 14034 + + VMOVUPSZrrkz = 14035 + + VMOVUPSZrrkz_REV = 14036 + + VMOVUPSmr = 14037 + + VMOVUPSrm = 14038 + + VMOVUPSrr = 14039 + + VMOVUPSrr_REV = 14040 + + VMOVW2SHrr = 14041 + + VMOVW64toSHrr = 14042 + + VMOVWmr = 14043 + + VMOVWrm = 14044 + + VMOVZPDILo2PDIZmr = 14045 + + VMOVZPDILo2PDIZrm = 14046 + + VMOVZPDILo2PDIZrr = 14047 + + VMOVZPDILo2PDIZrr2 = 14048 + + VMOVZPQILo2PQIZrr = 14049 + + VMOVZPQILo2PQIrr = 14050 + + VMOVZPWILo2PWIZmr = 14051 + + VMOVZPWILo2PWIZrm = 14052 + + VMOVZPWILo2PWIZrr = 14053 + + VMOVZPWILo2PWIZrr2 = 14054 + + VMPSADBWYrmi = 14055 + + VMPSADBWYrri = 14056 + + VMPSADBWZ128rmi = 14057 + + VMPSADBWZ128rmik = 14058 + + VMPSADBWZ128rmikz = 14059 + + VMPSADBWZ128rri = 14060 + + VMPSADBWZ128rrik = 14061 + + VMPSADBWZ128rrikz = 14062 + + VMPSADBWZ256rmi = 14063 + + VMPSADBWZ256rmik = 14064 + + VMPSADBWZ256rmikz = 14065 + + VMPSADBWZ256rri = 14066 + + VMPSADBWZ256rrik = 14067 + + VMPSADBWZ256rrikz = 14068 + + VMPSADBWZrmi = 14069 + + VMPSADBWZrmik = 14070 + + VMPSADBWZrmikz = 14071 + + VMPSADBWZrri = 14072 + + VMPSADBWZrrik = 14073 + + VMPSADBWZrrikz = 14074 + + VMPSADBWrmi = 14075 + + VMPSADBWrri = 14076 + + VMPTRLDm = 14077 + + VMPTRSTm = 14078 + + VMREAD32mr = 14079 + + VMREAD32rr = 14080 + + VMREAD64mr = 14081 + + VMREAD64rr = 14082 + + VMRESUME = 14083 + + VMRUN32 = 14084 + + VMRUN64 = 14085 + + VMSAVE32 = 14086 + + VMSAVE64 = 14087 + + VMULBF16Z128rm = 14088 + + VMULBF16Z128rmb = 14089 + + VMULBF16Z128rmbk = 14090 + + VMULBF16Z128rmbkz = 14091 + + VMULBF16Z128rmk = 14092 + + VMULBF16Z128rmkz = 14093 + + VMULBF16Z128rr = 14094 + + VMULBF16Z128rrk = 14095 + + VMULBF16Z128rrkz = 14096 + + VMULBF16Z256rm = 14097 + + VMULBF16Z256rmb = 14098 + + VMULBF16Z256rmbk = 14099 + + VMULBF16Z256rmbkz = 14100 + + VMULBF16Z256rmk = 14101 + + VMULBF16Z256rmkz = 14102 + + VMULBF16Z256rr = 14103 + + VMULBF16Z256rrk = 14104 + + VMULBF16Z256rrkz = 14105 + + VMULBF16Zrm = 14106 + + VMULBF16Zrmb = 14107 + + VMULBF16Zrmbk = 14108 + + VMULBF16Zrmbkz = 14109 + + VMULBF16Zrmk = 14110 + + VMULBF16Zrmkz = 14111 + + VMULBF16Zrr = 14112 + + VMULBF16Zrrk = 14113 + + VMULBF16Zrrkz = 14114 + + VMULPDYrm = 14115 + + VMULPDYrr = 14116 + + VMULPDZ128rm = 14117 + + VMULPDZ128rmb = 14118 + + VMULPDZ128rmbk = 14119 + + VMULPDZ128rmbkz = 14120 + + VMULPDZ128rmk = 14121 + + VMULPDZ128rmkz = 14122 + + VMULPDZ128rr = 14123 + + VMULPDZ128rrk = 14124 + + VMULPDZ128rrkz = 14125 + + VMULPDZ256rm = 14126 + + VMULPDZ256rmb = 14127 + + VMULPDZ256rmbk = 14128 + + VMULPDZ256rmbkz = 14129 + + VMULPDZ256rmk = 14130 + + VMULPDZ256rmkz = 14131 + + VMULPDZ256rr = 14132 + + VMULPDZ256rrk = 14133 + + VMULPDZ256rrkz = 14134 + + VMULPDZrm = 14135 + + VMULPDZrmb = 14136 + + VMULPDZrmbk = 14137 + + VMULPDZrmbkz = 14138 + + VMULPDZrmk = 14139 + + VMULPDZrmkz = 14140 + + VMULPDZrr = 14141 + + VMULPDZrrb = 14142 + + VMULPDZrrbk = 14143 + + VMULPDZrrbkz = 14144 + + VMULPDZrrk = 14145 + + VMULPDZrrkz = 14146 + + VMULPDrm = 14147 + + VMULPDrr = 14148 + + VMULPHZ128rm = 14149 + + VMULPHZ128rmb = 14150 + + VMULPHZ128rmbk = 14151 + + VMULPHZ128rmbkz = 14152 + + VMULPHZ128rmk = 14153 + + VMULPHZ128rmkz = 14154 + + VMULPHZ128rr = 14155 + + VMULPHZ128rrk = 14156 + + VMULPHZ128rrkz = 14157 + + VMULPHZ256rm = 14158 + + VMULPHZ256rmb = 14159 + + VMULPHZ256rmbk = 14160 + + VMULPHZ256rmbkz = 14161 + + VMULPHZ256rmk = 14162 + + VMULPHZ256rmkz = 14163 + + VMULPHZ256rr = 14164 + + VMULPHZ256rrk = 14165 + + VMULPHZ256rrkz = 14166 + + VMULPHZrm = 14167 + + VMULPHZrmb = 14168 + + VMULPHZrmbk = 14169 + + VMULPHZrmbkz = 14170 + + VMULPHZrmk = 14171 + + VMULPHZrmkz = 14172 + + VMULPHZrr = 14173 + + VMULPHZrrb = 14174 + + VMULPHZrrbk = 14175 + + VMULPHZrrbkz = 14176 + + VMULPHZrrk = 14177 + + VMULPHZrrkz = 14178 + + VMULPSYrm = 14179 + + VMULPSYrr = 14180 + + VMULPSZ128rm = 14181 + + VMULPSZ128rmb = 14182 + + VMULPSZ128rmbk = 14183 + + VMULPSZ128rmbkz = 14184 + + VMULPSZ128rmk = 14185 + + VMULPSZ128rmkz = 14186 + + VMULPSZ128rr = 14187 + + VMULPSZ128rrk = 14188 + + VMULPSZ128rrkz = 14189 + + VMULPSZ256rm = 14190 + + VMULPSZ256rmb = 14191 + + VMULPSZ256rmbk = 14192 + + VMULPSZ256rmbkz = 14193 + + VMULPSZ256rmk = 14194 + + VMULPSZ256rmkz = 14195 + + VMULPSZ256rr = 14196 + + VMULPSZ256rrk = 14197 + + VMULPSZ256rrkz = 14198 + + VMULPSZrm = 14199 + + VMULPSZrmb = 14200 + + VMULPSZrmbk = 14201 + + VMULPSZrmbkz = 14202 + + VMULPSZrmk = 14203 + + VMULPSZrmkz = 14204 + + VMULPSZrr = 14205 + + VMULPSZrrb = 14206 + + VMULPSZrrbk = 14207 + + VMULPSZrrbkz = 14208 + + VMULPSZrrk = 14209 + + VMULPSZrrkz = 14210 + + VMULPSrm = 14211 + + VMULPSrr = 14212 + + VMULSDZrm = 14213 + + VMULSDZrm_Int = 14214 + + VMULSDZrmk_Int = 14215 + + VMULSDZrmkz_Int = 14216 + + VMULSDZrr = 14217 + + VMULSDZrr_Int = 14218 + + VMULSDZrrb_Int = 14219 + + VMULSDZrrbk_Int = 14220 + + VMULSDZrrbkz_Int = 14221 + + VMULSDZrrk_Int = 14222 + + VMULSDZrrkz_Int = 14223 + + VMULSDrm = 14224 + + VMULSDrm_Int = 14225 + + VMULSDrr = 14226 + + VMULSDrr_Int = 14227 + + VMULSHZrm = 14228 + + VMULSHZrm_Int = 14229 + + VMULSHZrmk_Int = 14230 + + VMULSHZrmkz_Int = 14231 + + VMULSHZrr = 14232 + + VMULSHZrr_Int = 14233 + + VMULSHZrrb_Int = 14234 + + VMULSHZrrbk_Int = 14235 + + VMULSHZrrbkz_Int = 14236 + + VMULSHZrrk_Int = 14237 + + VMULSHZrrkz_Int = 14238 + + VMULSSZrm = 14239 + + VMULSSZrm_Int = 14240 + + VMULSSZrmk_Int = 14241 + + VMULSSZrmkz_Int = 14242 + + VMULSSZrr = 14243 + + VMULSSZrr_Int = 14244 + + VMULSSZrrb_Int = 14245 + + VMULSSZrrbk_Int = 14246 + + VMULSSZrrbkz_Int = 14247 + + VMULSSZrrk_Int = 14248 + + VMULSSZrrkz_Int = 14249 + + VMULSSrm = 14250 + + VMULSSrm_Int = 14251 + + VMULSSrr = 14252 + + VMULSSrr_Int = 14253 + + VMWRITE32rm = 14254 + + VMWRITE32rr = 14255 + + VMWRITE64rm = 14256 + + VMWRITE64rr = 14257 + + VMXOFF = 14258 + + VMXON = 14259 + + VORPDYrm = 14260 + + VORPDYrr = 14261 + + VORPDZ128rm = 14262 + + VORPDZ128rmb = 14263 + + VORPDZ128rmbk = 14264 + + VORPDZ128rmbkz = 14265 + + VORPDZ128rmk = 14266 + + VORPDZ128rmkz = 14267 + + VORPDZ128rr = 14268 + + VORPDZ128rrk = 14269 + + VORPDZ128rrkz = 14270 + + VORPDZ256rm = 14271 + + VORPDZ256rmb = 14272 + + VORPDZ256rmbk = 14273 + + VORPDZ256rmbkz = 14274 + + VORPDZ256rmk = 14275 + + VORPDZ256rmkz = 14276 + + VORPDZ256rr = 14277 + + VORPDZ256rrk = 14278 + + VORPDZ256rrkz = 14279 + + VORPDZrm = 14280 + + VORPDZrmb = 14281 + + VORPDZrmbk = 14282 + + VORPDZrmbkz = 14283 + + VORPDZrmk = 14284 + + VORPDZrmkz = 14285 + + VORPDZrr = 14286 + + VORPDZrrk = 14287 + + VORPDZrrkz = 14288 + + VORPDrm = 14289 + + VORPDrr = 14290 + + VORPSYrm = 14291 + + VORPSYrr = 14292 + + VORPSZ128rm = 14293 + + VORPSZ128rmb = 14294 + + VORPSZ128rmbk = 14295 + + VORPSZ128rmbkz = 14296 + + VORPSZ128rmk = 14297 + + VORPSZ128rmkz = 14298 + + VORPSZ128rr = 14299 + + VORPSZ128rrk = 14300 + + VORPSZ128rrkz = 14301 + + VORPSZ256rm = 14302 + + VORPSZ256rmb = 14303 + + VORPSZ256rmbk = 14304 + + VORPSZ256rmbkz = 14305 + + VORPSZ256rmk = 14306 + + VORPSZ256rmkz = 14307 + + VORPSZ256rr = 14308 + + VORPSZ256rrk = 14309 + + VORPSZ256rrkz = 14310 + + VORPSZrm = 14311 + + VORPSZrmb = 14312 + + VORPSZrmbk = 14313 + + VORPSZrmbkz = 14314 + + VORPSZrmk = 14315 + + VORPSZrmkz = 14316 + + VORPSZrr = 14317 + + VORPSZrrk = 14318 + + VORPSZrrkz = 14319 + + VORPSrm = 14320 + + VORPSrr = 14321 + + VP2INTERSECTDZ128rm = 14322 + + VP2INTERSECTDZ128rmb = 14323 + + VP2INTERSECTDZ128rr = 14324 + + VP2INTERSECTDZ256rm = 14325 + + VP2INTERSECTDZ256rmb = 14326 + + VP2INTERSECTDZ256rr = 14327 + + VP2INTERSECTDZrm = 14328 + + VP2INTERSECTDZrmb = 14329 + + VP2INTERSECTDZrr = 14330 + + VP2INTERSECTQZ128rm = 14331 + + VP2INTERSECTQZ128rmb = 14332 + + VP2INTERSECTQZ128rr = 14333 + + VP2INTERSECTQZ256rm = 14334 + + VP2INTERSECTQZ256rmb = 14335 + + VP2INTERSECTQZ256rr = 14336 + + VP2INTERSECTQZrm = 14337 + + VP2INTERSECTQZrmb = 14338 + + VP2INTERSECTQZrr = 14339 + + VP4DPWSSDSrm = 14340 + + VP4DPWSSDSrmk = 14341 + + VP4DPWSSDSrmkz = 14342 + + VP4DPWSSDrm = 14343 + + VP4DPWSSDrmk = 14344 + + VP4DPWSSDrmkz = 14345 + + VPABSBYrm = 14346 + + VPABSBYrr = 14347 + + VPABSBZ128rm = 14348 + + VPABSBZ128rmk = 14349 + + VPABSBZ128rmkz = 14350 + + VPABSBZ128rr = 14351 + + VPABSBZ128rrk = 14352 + + VPABSBZ128rrkz = 14353 + + VPABSBZ256rm = 14354 + + VPABSBZ256rmk = 14355 + + VPABSBZ256rmkz = 14356 + + VPABSBZ256rr = 14357 + + VPABSBZ256rrk = 14358 + + VPABSBZ256rrkz = 14359 + + VPABSBZrm = 14360 + + VPABSBZrmk = 14361 + + VPABSBZrmkz = 14362 + + VPABSBZrr = 14363 + + VPABSBZrrk = 14364 + + VPABSBZrrkz = 14365 + + VPABSBrm = 14366 + + VPABSBrr = 14367 + + VPABSDYrm = 14368 + + VPABSDYrr = 14369 + + VPABSDZ128rm = 14370 + + VPABSDZ128rmb = 14371 + + VPABSDZ128rmbk = 14372 + + VPABSDZ128rmbkz = 14373 + + VPABSDZ128rmk = 14374 + + VPABSDZ128rmkz = 14375 + + VPABSDZ128rr = 14376 + + VPABSDZ128rrk = 14377 + + VPABSDZ128rrkz = 14378 + + VPABSDZ256rm = 14379 + + VPABSDZ256rmb = 14380 + + VPABSDZ256rmbk = 14381 + + VPABSDZ256rmbkz = 14382 + + VPABSDZ256rmk = 14383 + + VPABSDZ256rmkz = 14384 + + VPABSDZ256rr = 14385 + + VPABSDZ256rrk = 14386 + + VPABSDZ256rrkz = 14387 + + VPABSDZrm = 14388 + + VPABSDZrmb = 14389 + + VPABSDZrmbk = 14390 + + VPABSDZrmbkz = 14391 + + VPABSDZrmk = 14392 + + VPABSDZrmkz = 14393 + + VPABSDZrr = 14394 + + VPABSDZrrk = 14395 + + VPABSDZrrkz = 14396 + + VPABSDrm = 14397 + + VPABSDrr = 14398 + + VPABSQZ128rm = 14399 + + VPABSQZ128rmb = 14400 + + VPABSQZ128rmbk = 14401 + + VPABSQZ128rmbkz = 14402 + + VPABSQZ128rmk = 14403 + + VPABSQZ128rmkz = 14404 + + VPABSQZ128rr = 14405 + + VPABSQZ128rrk = 14406 + + VPABSQZ128rrkz = 14407 + + VPABSQZ256rm = 14408 + + VPABSQZ256rmb = 14409 + + VPABSQZ256rmbk = 14410 + + VPABSQZ256rmbkz = 14411 + + VPABSQZ256rmk = 14412 + + VPABSQZ256rmkz = 14413 + + VPABSQZ256rr = 14414 + + VPABSQZ256rrk = 14415 + + VPABSQZ256rrkz = 14416 + + VPABSQZrm = 14417 + + VPABSQZrmb = 14418 + + VPABSQZrmbk = 14419 + + VPABSQZrmbkz = 14420 + + VPABSQZrmk = 14421 + + VPABSQZrmkz = 14422 + + VPABSQZrr = 14423 + + VPABSQZrrk = 14424 + + VPABSQZrrkz = 14425 + + VPABSWYrm = 14426 + + VPABSWYrr = 14427 + + VPABSWZ128rm = 14428 + + VPABSWZ128rmk = 14429 + + VPABSWZ128rmkz = 14430 + + VPABSWZ128rr = 14431 + + VPABSWZ128rrk = 14432 + + VPABSWZ128rrkz = 14433 + + VPABSWZ256rm = 14434 + + VPABSWZ256rmk = 14435 + + VPABSWZ256rmkz = 14436 + + VPABSWZ256rr = 14437 + + VPABSWZ256rrk = 14438 + + VPABSWZ256rrkz = 14439 + + VPABSWZrm = 14440 + + VPABSWZrmk = 14441 + + VPABSWZrmkz = 14442 + + VPABSWZrr = 14443 + + VPABSWZrrk = 14444 + + VPABSWZrrkz = 14445 + + VPABSWrm = 14446 + + VPABSWrr = 14447 + + VPACKSSDWYrm = 14448 + + VPACKSSDWYrr = 14449 + + VPACKSSDWZ128rm = 14450 + + VPACKSSDWZ128rmb = 14451 + + VPACKSSDWZ128rmbk = 14452 + + VPACKSSDWZ128rmbkz = 14453 + + VPACKSSDWZ128rmk = 14454 + + VPACKSSDWZ128rmkz = 14455 + + VPACKSSDWZ128rr = 14456 + + VPACKSSDWZ128rrk = 14457 + + VPACKSSDWZ128rrkz = 14458 + + VPACKSSDWZ256rm = 14459 + + VPACKSSDWZ256rmb = 14460 + + VPACKSSDWZ256rmbk = 14461 + + VPACKSSDWZ256rmbkz = 14462 + + VPACKSSDWZ256rmk = 14463 + + VPACKSSDWZ256rmkz = 14464 + + VPACKSSDWZ256rr = 14465 + + VPACKSSDWZ256rrk = 14466 + + VPACKSSDWZ256rrkz = 14467 + + VPACKSSDWZrm = 14468 + + VPACKSSDWZrmb = 14469 + + VPACKSSDWZrmbk = 14470 + + VPACKSSDWZrmbkz = 14471 + + VPACKSSDWZrmk = 14472 + + VPACKSSDWZrmkz = 14473 + + VPACKSSDWZrr = 14474 + + VPACKSSDWZrrk = 14475 + + VPACKSSDWZrrkz = 14476 + + VPACKSSDWrm = 14477 + + VPACKSSDWrr = 14478 + + VPACKSSWBYrm = 14479 + + VPACKSSWBYrr = 14480 + + VPACKSSWBZ128rm = 14481 + + VPACKSSWBZ128rmk = 14482 + + VPACKSSWBZ128rmkz = 14483 + + VPACKSSWBZ128rr = 14484 + + VPACKSSWBZ128rrk = 14485 + + VPACKSSWBZ128rrkz = 14486 + + VPACKSSWBZ256rm = 14487 + + VPACKSSWBZ256rmk = 14488 + + VPACKSSWBZ256rmkz = 14489 + + VPACKSSWBZ256rr = 14490 + + VPACKSSWBZ256rrk = 14491 + + VPACKSSWBZ256rrkz = 14492 + + VPACKSSWBZrm = 14493 + + VPACKSSWBZrmk = 14494 + + VPACKSSWBZrmkz = 14495 + + VPACKSSWBZrr = 14496 + + VPACKSSWBZrrk = 14497 + + VPACKSSWBZrrkz = 14498 + + VPACKSSWBrm = 14499 + + VPACKSSWBrr = 14500 + + VPACKUSDWYrm = 14501 + + VPACKUSDWYrr = 14502 + + VPACKUSDWZ128rm = 14503 + + VPACKUSDWZ128rmb = 14504 + + VPACKUSDWZ128rmbk = 14505 + + VPACKUSDWZ128rmbkz = 14506 + + VPACKUSDWZ128rmk = 14507 + + VPACKUSDWZ128rmkz = 14508 + + VPACKUSDWZ128rr = 14509 + + VPACKUSDWZ128rrk = 14510 + + VPACKUSDWZ128rrkz = 14511 + + VPACKUSDWZ256rm = 14512 + + VPACKUSDWZ256rmb = 14513 + + VPACKUSDWZ256rmbk = 14514 + + VPACKUSDWZ256rmbkz = 14515 + + VPACKUSDWZ256rmk = 14516 + + VPACKUSDWZ256rmkz = 14517 + + VPACKUSDWZ256rr = 14518 + + VPACKUSDWZ256rrk = 14519 + + VPACKUSDWZ256rrkz = 14520 + + VPACKUSDWZrm = 14521 + + VPACKUSDWZrmb = 14522 + + VPACKUSDWZrmbk = 14523 + + VPACKUSDWZrmbkz = 14524 + + VPACKUSDWZrmk = 14525 + + VPACKUSDWZrmkz = 14526 + + VPACKUSDWZrr = 14527 + + VPACKUSDWZrrk = 14528 + + VPACKUSDWZrrkz = 14529 + + VPACKUSDWrm = 14530 + + VPACKUSDWrr = 14531 + + VPACKUSWBYrm = 14532 + + VPACKUSWBYrr = 14533 + + VPACKUSWBZ128rm = 14534 + + VPACKUSWBZ128rmk = 14535 + + VPACKUSWBZ128rmkz = 14536 + + VPACKUSWBZ128rr = 14537 + + VPACKUSWBZ128rrk = 14538 + + VPACKUSWBZ128rrkz = 14539 + + VPACKUSWBZ256rm = 14540 + + VPACKUSWBZ256rmk = 14541 + + VPACKUSWBZ256rmkz = 14542 + + VPACKUSWBZ256rr = 14543 + + VPACKUSWBZ256rrk = 14544 + + VPACKUSWBZ256rrkz = 14545 + + VPACKUSWBZrm = 14546 + + VPACKUSWBZrmk = 14547 + + VPACKUSWBZrmkz = 14548 + + VPACKUSWBZrr = 14549 + + VPACKUSWBZrrk = 14550 + + VPACKUSWBZrrkz = 14551 + + VPACKUSWBrm = 14552 + + VPACKUSWBrr = 14553 + + VPADDBYrm = 14554 + + VPADDBYrr = 14555 + + VPADDBZ128rm = 14556 + + VPADDBZ128rmk = 14557 + + VPADDBZ128rmkz = 14558 + + VPADDBZ128rr = 14559 + + VPADDBZ128rrk = 14560 + + VPADDBZ128rrkz = 14561 + + VPADDBZ256rm = 14562 + + VPADDBZ256rmk = 14563 + + VPADDBZ256rmkz = 14564 + + VPADDBZ256rr = 14565 + + VPADDBZ256rrk = 14566 + + VPADDBZ256rrkz = 14567 + + VPADDBZrm = 14568 + + VPADDBZrmk = 14569 + + VPADDBZrmkz = 14570 + + VPADDBZrr = 14571 + + VPADDBZrrk = 14572 + + VPADDBZrrkz = 14573 + + VPADDBrm = 14574 + + VPADDBrr = 14575 + + VPADDDYrm = 14576 + + VPADDDYrr = 14577 + + VPADDDZ128rm = 14578 + + VPADDDZ128rmb = 14579 + + VPADDDZ128rmbk = 14580 + + VPADDDZ128rmbkz = 14581 + + VPADDDZ128rmk = 14582 + + VPADDDZ128rmkz = 14583 + + VPADDDZ128rr = 14584 + + VPADDDZ128rrk = 14585 + + VPADDDZ128rrkz = 14586 + + VPADDDZ256rm = 14587 + + VPADDDZ256rmb = 14588 + + VPADDDZ256rmbk = 14589 + + VPADDDZ256rmbkz = 14590 + + VPADDDZ256rmk = 14591 + + VPADDDZ256rmkz = 14592 + + VPADDDZ256rr = 14593 + + VPADDDZ256rrk = 14594 + + VPADDDZ256rrkz = 14595 + + VPADDDZrm = 14596 + + VPADDDZrmb = 14597 + + VPADDDZrmbk = 14598 + + VPADDDZrmbkz = 14599 + + VPADDDZrmk = 14600 + + VPADDDZrmkz = 14601 + + VPADDDZrr = 14602 + + VPADDDZrrk = 14603 + + VPADDDZrrkz = 14604 + + VPADDDrm = 14605 + + VPADDDrr = 14606 + + VPADDQYrm = 14607 + + VPADDQYrr = 14608 + + VPADDQZ128rm = 14609 + + VPADDQZ128rmb = 14610 + + VPADDQZ128rmbk = 14611 + + VPADDQZ128rmbkz = 14612 + + VPADDQZ128rmk = 14613 + + VPADDQZ128rmkz = 14614 + + VPADDQZ128rr = 14615 + + VPADDQZ128rrk = 14616 + + VPADDQZ128rrkz = 14617 + + VPADDQZ256rm = 14618 + + VPADDQZ256rmb = 14619 + + VPADDQZ256rmbk = 14620 + + VPADDQZ256rmbkz = 14621 + + VPADDQZ256rmk = 14622 + + VPADDQZ256rmkz = 14623 + + VPADDQZ256rr = 14624 + + VPADDQZ256rrk = 14625 + + VPADDQZ256rrkz = 14626 + + VPADDQZrm = 14627 + + VPADDQZrmb = 14628 + + VPADDQZrmbk = 14629 + + VPADDQZrmbkz = 14630 + + VPADDQZrmk = 14631 + + VPADDQZrmkz = 14632 + + VPADDQZrr = 14633 + + VPADDQZrrk = 14634 + + VPADDQZrrkz = 14635 + + VPADDQrm = 14636 + + VPADDQrr = 14637 + + VPADDSBYrm = 14638 + + VPADDSBYrr = 14639 + + VPADDSBZ128rm = 14640 + + VPADDSBZ128rmk = 14641 + + VPADDSBZ128rmkz = 14642 + + VPADDSBZ128rr = 14643 + + VPADDSBZ128rrk = 14644 + + VPADDSBZ128rrkz = 14645 + + VPADDSBZ256rm = 14646 + + VPADDSBZ256rmk = 14647 + + VPADDSBZ256rmkz = 14648 + + VPADDSBZ256rr = 14649 + + VPADDSBZ256rrk = 14650 + + VPADDSBZ256rrkz = 14651 + + VPADDSBZrm = 14652 + + VPADDSBZrmk = 14653 + + VPADDSBZrmkz = 14654 + + VPADDSBZrr = 14655 + + VPADDSBZrrk = 14656 + + VPADDSBZrrkz = 14657 + + VPADDSBrm = 14658 + + VPADDSBrr = 14659 + + VPADDSWYrm = 14660 + + VPADDSWYrr = 14661 + + VPADDSWZ128rm = 14662 + + VPADDSWZ128rmk = 14663 + + VPADDSWZ128rmkz = 14664 + + VPADDSWZ128rr = 14665 + + VPADDSWZ128rrk = 14666 + + VPADDSWZ128rrkz = 14667 + + VPADDSWZ256rm = 14668 + + VPADDSWZ256rmk = 14669 + + VPADDSWZ256rmkz = 14670 + + VPADDSWZ256rr = 14671 + + VPADDSWZ256rrk = 14672 + + VPADDSWZ256rrkz = 14673 + + VPADDSWZrm = 14674 + + VPADDSWZrmk = 14675 + + VPADDSWZrmkz = 14676 + + VPADDSWZrr = 14677 + + VPADDSWZrrk = 14678 + + VPADDSWZrrkz = 14679 + + VPADDSWrm = 14680 + + VPADDSWrr = 14681 + + VPADDUSBYrm = 14682 + + VPADDUSBYrr = 14683 + + VPADDUSBZ128rm = 14684 + + VPADDUSBZ128rmk = 14685 + + VPADDUSBZ128rmkz = 14686 + + VPADDUSBZ128rr = 14687 + + VPADDUSBZ128rrk = 14688 + + VPADDUSBZ128rrkz = 14689 + + VPADDUSBZ256rm = 14690 + + VPADDUSBZ256rmk = 14691 + + VPADDUSBZ256rmkz = 14692 + + VPADDUSBZ256rr = 14693 + + VPADDUSBZ256rrk = 14694 + + VPADDUSBZ256rrkz = 14695 + + VPADDUSBZrm = 14696 + + VPADDUSBZrmk = 14697 + + VPADDUSBZrmkz = 14698 + + VPADDUSBZrr = 14699 + + VPADDUSBZrrk = 14700 + + VPADDUSBZrrkz = 14701 + + VPADDUSBrm = 14702 + + VPADDUSBrr = 14703 + + VPADDUSWYrm = 14704 + + VPADDUSWYrr = 14705 + + VPADDUSWZ128rm = 14706 + + VPADDUSWZ128rmk = 14707 + + VPADDUSWZ128rmkz = 14708 + + VPADDUSWZ128rr = 14709 + + VPADDUSWZ128rrk = 14710 + + VPADDUSWZ128rrkz = 14711 + + VPADDUSWZ256rm = 14712 + + VPADDUSWZ256rmk = 14713 + + VPADDUSWZ256rmkz = 14714 + + VPADDUSWZ256rr = 14715 + + VPADDUSWZ256rrk = 14716 + + VPADDUSWZ256rrkz = 14717 + + VPADDUSWZrm = 14718 + + VPADDUSWZrmk = 14719 + + VPADDUSWZrmkz = 14720 + + VPADDUSWZrr = 14721 + + VPADDUSWZrrk = 14722 + + VPADDUSWZrrkz = 14723 + + VPADDUSWrm = 14724 + + VPADDUSWrr = 14725 + + VPADDWYrm = 14726 + + VPADDWYrr = 14727 + + VPADDWZ128rm = 14728 + + VPADDWZ128rmk = 14729 + + VPADDWZ128rmkz = 14730 + + VPADDWZ128rr = 14731 + + VPADDWZ128rrk = 14732 + + VPADDWZ128rrkz = 14733 + + VPADDWZ256rm = 14734 + + VPADDWZ256rmk = 14735 + + VPADDWZ256rmkz = 14736 + + VPADDWZ256rr = 14737 + + VPADDWZ256rrk = 14738 + + VPADDWZ256rrkz = 14739 + + VPADDWZrm = 14740 + + VPADDWZrmk = 14741 + + VPADDWZrmkz = 14742 + + VPADDWZrr = 14743 + + VPADDWZrrk = 14744 + + VPADDWZrrkz = 14745 + + VPADDWrm = 14746 + + VPADDWrr = 14747 + + VPALIGNRYrmi = 14748 + + VPALIGNRYrri = 14749 + + VPALIGNRZ128rmi = 14750 + + VPALIGNRZ128rmik = 14751 + + VPALIGNRZ128rmikz = 14752 + + VPALIGNRZ128rri = 14753 + + VPALIGNRZ128rrik = 14754 + + VPALIGNRZ128rrikz = 14755 + + VPALIGNRZ256rmi = 14756 + + VPALIGNRZ256rmik = 14757 + + VPALIGNRZ256rmikz = 14758 + + VPALIGNRZ256rri = 14759 + + VPALIGNRZ256rrik = 14760 + + VPALIGNRZ256rrikz = 14761 + + VPALIGNRZrmi = 14762 + + VPALIGNRZrmik = 14763 + + VPALIGNRZrmikz = 14764 + + VPALIGNRZrri = 14765 + + VPALIGNRZrrik = 14766 + + VPALIGNRZrrikz = 14767 + + VPALIGNRrmi = 14768 + + VPALIGNRrri = 14769 + + VPANDDZ128rm = 14770 + + VPANDDZ128rmb = 14771 + + VPANDDZ128rmbk = 14772 + + VPANDDZ128rmbkz = 14773 + + VPANDDZ128rmk = 14774 + + VPANDDZ128rmkz = 14775 + + VPANDDZ128rr = 14776 + + VPANDDZ128rrk = 14777 + + VPANDDZ128rrkz = 14778 + + VPANDDZ256rm = 14779 + + VPANDDZ256rmb = 14780 + + VPANDDZ256rmbk = 14781 + + VPANDDZ256rmbkz = 14782 + + VPANDDZ256rmk = 14783 + + VPANDDZ256rmkz = 14784 + + VPANDDZ256rr = 14785 + + VPANDDZ256rrk = 14786 + + VPANDDZ256rrkz = 14787 + + VPANDDZrm = 14788 + + VPANDDZrmb = 14789 + + VPANDDZrmbk = 14790 + + VPANDDZrmbkz = 14791 + + VPANDDZrmk = 14792 + + VPANDDZrmkz = 14793 + + VPANDDZrr = 14794 + + VPANDDZrrk = 14795 + + VPANDDZrrkz = 14796 + + VPANDNDZ128rm = 14797 + + VPANDNDZ128rmb = 14798 + + VPANDNDZ128rmbk = 14799 + + VPANDNDZ128rmbkz = 14800 + + VPANDNDZ128rmk = 14801 + + VPANDNDZ128rmkz = 14802 + + VPANDNDZ128rr = 14803 + + VPANDNDZ128rrk = 14804 + + VPANDNDZ128rrkz = 14805 + + VPANDNDZ256rm = 14806 + + VPANDNDZ256rmb = 14807 + + VPANDNDZ256rmbk = 14808 + + VPANDNDZ256rmbkz = 14809 + + VPANDNDZ256rmk = 14810 + + VPANDNDZ256rmkz = 14811 + + VPANDNDZ256rr = 14812 + + VPANDNDZ256rrk = 14813 + + VPANDNDZ256rrkz = 14814 + + VPANDNDZrm = 14815 + + VPANDNDZrmb = 14816 + + VPANDNDZrmbk = 14817 + + VPANDNDZrmbkz = 14818 + + VPANDNDZrmk = 14819 + + VPANDNDZrmkz = 14820 + + VPANDNDZrr = 14821 + + VPANDNDZrrk = 14822 + + VPANDNDZrrkz = 14823 + + VPANDNQZ128rm = 14824 + + VPANDNQZ128rmb = 14825 + + VPANDNQZ128rmbk = 14826 + + VPANDNQZ128rmbkz = 14827 + + VPANDNQZ128rmk = 14828 + + VPANDNQZ128rmkz = 14829 + + VPANDNQZ128rr = 14830 + + VPANDNQZ128rrk = 14831 + + VPANDNQZ128rrkz = 14832 + + VPANDNQZ256rm = 14833 + + VPANDNQZ256rmb = 14834 + + VPANDNQZ256rmbk = 14835 + + VPANDNQZ256rmbkz = 14836 + + VPANDNQZ256rmk = 14837 + + VPANDNQZ256rmkz = 14838 + + VPANDNQZ256rr = 14839 + + VPANDNQZ256rrk = 14840 + + VPANDNQZ256rrkz = 14841 + + VPANDNQZrm = 14842 + + VPANDNQZrmb = 14843 + + VPANDNQZrmbk = 14844 + + VPANDNQZrmbkz = 14845 + + VPANDNQZrmk = 14846 + + VPANDNQZrmkz = 14847 + + VPANDNQZrr = 14848 + + VPANDNQZrrk = 14849 + + VPANDNQZrrkz = 14850 + + VPANDNYrm = 14851 + + VPANDNYrr = 14852 + + VPANDNrm = 14853 + + VPANDNrr = 14854 + + VPANDQZ128rm = 14855 + + VPANDQZ128rmb = 14856 + + VPANDQZ128rmbk = 14857 + + VPANDQZ128rmbkz = 14858 + + VPANDQZ128rmk = 14859 + + VPANDQZ128rmkz = 14860 + + VPANDQZ128rr = 14861 + + VPANDQZ128rrk = 14862 + + VPANDQZ128rrkz = 14863 + + VPANDQZ256rm = 14864 + + VPANDQZ256rmb = 14865 + + VPANDQZ256rmbk = 14866 + + VPANDQZ256rmbkz = 14867 + + VPANDQZ256rmk = 14868 + + VPANDQZ256rmkz = 14869 + + VPANDQZ256rr = 14870 + + VPANDQZ256rrk = 14871 + + VPANDQZ256rrkz = 14872 + + VPANDQZrm = 14873 + + VPANDQZrmb = 14874 + + VPANDQZrmbk = 14875 + + VPANDQZrmbkz = 14876 + + VPANDQZrmk = 14877 + + VPANDQZrmkz = 14878 + + VPANDQZrr = 14879 + + VPANDQZrrk = 14880 + + VPANDQZrrkz = 14881 + + VPANDYrm = 14882 + + VPANDYrr = 14883 + + VPANDrm = 14884 + + VPANDrr = 14885 + + VPAVGBYrm = 14886 + + VPAVGBYrr = 14887 + + VPAVGBZ128rm = 14888 + + VPAVGBZ128rmk = 14889 + + VPAVGBZ128rmkz = 14890 + + VPAVGBZ128rr = 14891 + + VPAVGBZ128rrk = 14892 + + VPAVGBZ128rrkz = 14893 + + VPAVGBZ256rm = 14894 + + VPAVGBZ256rmk = 14895 + + VPAVGBZ256rmkz = 14896 + + VPAVGBZ256rr = 14897 + + VPAVGBZ256rrk = 14898 + + VPAVGBZ256rrkz = 14899 + + VPAVGBZrm = 14900 + + VPAVGBZrmk = 14901 + + VPAVGBZrmkz = 14902 + + VPAVGBZrr = 14903 + + VPAVGBZrrk = 14904 + + VPAVGBZrrkz = 14905 + + VPAVGBrm = 14906 + + VPAVGBrr = 14907 + + VPAVGWYrm = 14908 + + VPAVGWYrr = 14909 + + VPAVGWZ128rm = 14910 + + VPAVGWZ128rmk = 14911 + + VPAVGWZ128rmkz = 14912 + + VPAVGWZ128rr = 14913 + + VPAVGWZ128rrk = 14914 + + VPAVGWZ128rrkz = 14915 + + VPAVGWZ256rm = 14916 + + VPAVGWZ256rmk = 14917 + + VPAVGWZ256rmkz = 14918 + + VPAVGWZ256rr = 14919 + + VPAVGWZ256rrk = 14920 + + VPAVGWZ256rrkz = 14921 + + VPAVGWZrm = 14922 + + VPAVGWZrmk = 14923 + + VPAVGWZrmkz = 14924 + + VPAVGWZrr = 14925 + + VPAVGWZrrk = 14926 + + VPAVGWZrrkz = 14927 + + VPAVGWrm = 14928 + + VPAVGWrr = 14929 + + VPBLENDDYrmi = 14930 + + VPBLENDDYrri = 14931 + + VPBLENDDrmi = 14932 + + VPBLENDDrri = 14933 + + VPBLENDMBZ128rm = 14934 + + VPBLENDMBZ128rmk = 14935 + + VPBLENDMBZ128rmkz = 14936 + + VPBLENDMBZ128rr = 14937 + + VPBLENDMBZ128rrk = 14938 + + VPBLENDMBZ128rrkz = 14939 + + VPBLENDMBZ256rm = 14940 + + VPBLENDMBZ256rmk = 14941 + + VPBLENDMBZ256rmkz = 14942 + + VPBLENDMBZ256rr = 14943 + + VPBLENDMBZ256rrk = 14944 + + VPBLENDMBZ256rrkz = 14945 + + VPBLENDMBZrm = 14946 + + VPBLENDMBZrmk = 14947 + + VPBLENDMBZrmkz = 14948 + + VPBLENDMBZrr = 14949 + + VPBLENDMBZrrk = 14950 + + VPBLENDMBZrrkz = 14951 + + VPBLENDMDZ128rm = 14952 + + VPBLENDMDZ128rmb = 14953 + + VPBLENDMDZ128rmbk = 14954 + + VPBLENDMDZ128rmbkz = 14955 + + VPBLENDMDZ128rmk = 14956 + + VPBLENDMDZ128rmkz = 14957 + + VPBLENDMDZ128rr = 14958 + + VPBLENDMDZ128rrk = 14959 + + VPBLENDMDZ128rrkz = 14960 + + VPBLENDMDZ256rm = 14961 + + VPBLENDMDZ256rmb = 14962 + + VPBLENDMDZ256rmbk = 14963 + + VPBLENDMDZ256rmbkz = 14964 + + VPBLENDMDZ256rmk = 14965 + + VPBLENDMDZ256rmkz = 14966 + + VPBLENDMDZ256rr = 14967 + + VPBLENDMDZ256rrk = 14968 + + VPBLENDMDZ256rrkz = 14969 + + VPBLENDMDZrm = 14970 + + VPBLENDMDZrmb = 14971 + + VPBLENDMDZrmbk = 14972 + + VPBLENDMDZrmbkz = 14973 + + VPBLENDMDZrmk = 14974 + + VPBLENDMDZrmkz = 14975 + + VPBLENDMDZrr = 14976 + + VPBLENDMDZrrk = 14977 + + VPBLENDMDZrrkz = 14978 + + VPBLENDMQZ128rm = 14979 + + VPBLENDMQZ128rmb = 14980 + + VPBLENDMQZ128rmbk = 14981 + + VPBLENDMQZ128rmbkz = 14982 + + VPBLENDMQZ128rmk = 14983 + + VPBLENDMQZ128rmkz = 14984 + + VPBLENDMQZ128rr = 14985 + + VPBLENDMQZ128rrk = 14986 + + VPBLENDMQZ128rrkz = 14987 + + VPBLENDMQZ256rm = 14988 + + VPBLENDMQZ256rmb = 14989 + + VPBLENDMQZ256rmbk = 14990 + + VPBLENDMQZ256rmbkz = 14991 + + VPBLENDMQZ256rmk = 14992 + + VPBLENDMQZ256rmkz = 14993 + + VPBLENDMQZ256rr = 14994 + + VPBLENDMQZ256rrk = 14995 + + VPBLENDMQZ256rrkz = 14996 + + VPBLENDMQZrm = 14997 + + VPBLENDMQZrmb = 14998 + + VPBLENDMQZrmbk = 14999 + + VPBLENDMQZrmbkz = 15000 + + VPBLENDMQZrmk = 15001 + + VPBLENDMQZrmkz = 15002 + + VPBLENDMQZrr = 15003 + + VPBLENDMQZrrk = 15004 + + VPBLENDMQZrrkz = 15005 + + VPBLENDMWZ128rm = 15006 + + VPBLENDMWZ128rmk = 15007 + + VPBLENDMWZ128rmkz = 15008 + + VPBLENDMWZ128rr = 15009 + + VPBLENDMWZ128rrk = 15010 + + VPBLENDMWZ128rrkz = 15011 + + VPBLENDMWZ256rm = 15012 + + VPBLENDMWZ256rmk = 15013 + + VPBLENDMWZ256rmkz = 15014 + + VPBLENDMWZ256rr = 15015 + + VPBLENDMWZ256rrk = 15016 + + VPBLENDMWZ256rrkz = 15017 + + VPBLENDMWZrm = 15018 + + VPBLENDMWZrmk = 15019 + + VPBLENDMWZrmkz = 15020 + + VPBLENDMWZrr = 15021 + + VPBLENDMWZrrk = 15022 + + VPBLENDMWZrrkz = 15023 + + VPBLENDVBYrmr = 15024 + + VPBLENDVBYrrr = 15025 + + VPBLENDVBrmr = 15026 + + VPBLENDVBrrr = 15027 + + VPBLENDWYrmi = 15028 + + VPBLENDWYrri = 15029 + + VPBLENDWrmi = 15030 + + VPBLENDWrri = 15031 + + VPBROADCASTBYrm = 15032 + + VPBROADCASTBYrr = 15033 + + VPBROADCASTBZ128rm = 15034 + + VPBROADCASTBZ128rmk = 15035 + + VPBROADCASTBZ128rmkz = 15036 + + VPBROADCASTBZ128rr = 15037 + + VPBROADCASTBZ128rrk = 15038 + + VPBROADCASTBZ128rrkz = 15039 + + VPBROADCASTBZ256rm = 15040 + + VPBROADCASTBZ256rmk = 15041 + + VPBROADCASTBZ256rmkz = 15042 + + VPBROADCASTBZ256rr = 15043 + + VPBROADCASTBZ256rrk = 15044 + + VPBROADCASTBZ256rrkz = 15045 + + VPBROADCASTBZrm = 15046 + + VPBROADCASTBZrmk = 15047 + + VPBROADCASTBZrmkz = 15048 + + VPBROADCASTBZrr = 15049 + + VPBROADCASTBZrrk = 15050 + + VPBROADCASTBZrrkz = 15051 + + VPBROADCASTBrZ128rr = 15052 + + VPBROADCASTBrZ128rrk = 15053 + + VPBROADCASTBrZ128rrkz = 15054 + + VPBROADCASTBrZ256rr = 15055 + + VPBROADCASTBrZ256rrk = 15056 + + VPBROADCASTBrZ256rrkz = 15057 + + VPBROADCASTBrZrr = 15058 + + VPBROADCASTBrZrrk = 15059 + + VPBROADCASTBrZrrkz = 15060 + + VPBROADCASTBrm = 15061 + + VPBROADCASTBrr = 15062 + + VPBROADCASTDYrm = 15063 + + VPBROADCASTDYrr = 15064 + + VPBROADCASTDZ128rm = 15065 + + VPBROADCASTDZ128rmk = 15066 + + VPBROADCASTDZ128rmkz = 15067 + + VPBROADCASTDZ128rr = 15068 + + VPBROADCASTDZ128rrk = 15069 + + VPBROADCASTDZ128rrkz = 15070 + + VPBROADCASTDZ256rm = 15071 + + VPBROADCASTDZ256rmk = 15072 + + VPBROADCASTDZ256rmkz = 15073 + + VPBROADCASTDZ256rr = 15074 + + VPBROADCASTDZ256rrk = 15075 + + VPBROADCASTDZ256rrkz = 15076 + + VPBROADCASTDZrm = 15077 + + VPBROADCASTDZrmk = 15078 + + VPBROADCASTDZrmkz = 15079 + + VPBROADCASTDZrr = 15080 + + VPBROADCASTDZrrk = 15081 + + VPBROADCASTDZrrkz = 15082 + + VPBROADCASTDrZ128rr = 15083 + + VPBROADCASTDrZ128rrk = 15084 + + VPBROADCASTDrZ128rrkz = 15085 + + VPBROADCASTDrZ256rr = 15086 + + VPBROADCASTDrZ256rrk = 15087 + + VPBROADCASTDrZ256rrkz = 15088 + + VPBROADCASTDrZrr = 15089 + + VPBROADCASTDrZrrk = 15090 + + VPBROADCASTDrZrrkz = 15091 + + VPBROADCASTDrm = 15092 + + VPBROADCASTDrr = 15093 + + VPBROADCASTMB2QZ128rr = 15094 + + VPBROADCASTMB2QZ256rr = 15095 + + VPBROADCASTMB2QZrr = 15096 + + VPBROADCASTMW2DZ128rr = 15097 + + VPBROADCASTMW2DZ256rr = 15098 + + VPBROADCASTMW2DZrr = 15099 + + VPBROADCASTQYrm = 15100 + + VPBROADCASTQYrr = 15101 + + VPBROADCASTQZ128rm = 15102 + + VPBROADCASTQZ128rmk = 15103 + + VPBROADCASTQZ128rmkz = 15104 + + VPBROADCASTQZ128rr = 15105 + + VPBROADCASTQZ128rrk = 15106 + + VPBROADCASTQZ128rrkz = 15107 + + VPBROADCASTQZ256rm = 15108 + + VPBROADCASTQZ256rmk = 15109 + + VPBROADCASTQZ256rmkz = 15110 + + VPBROADCASTQZ256rr = 15111 + + VPBROADCASTQZ256rrk = 15112 + + VPBROADCASTQZ256rrkz = 15113 + + VPBROADCASTQZrm = 15114 + + VPBROADCASTQZrmk = 15115 + + VPBROADCASTQZrmkz = 15116 + + VPBROADCASTQZrr = 15117 + + VPBROADCASTQZrrk = 15118 + + VPBROADCASTQZrrkz = 15119 + + VPBROADCASTQrZ128rr = 15120 + + VPBROADCASTQrZ128rrk = 15121 + + VPBROADCASTQrZ128rrkz = 15122 + + VPBROADCASTQrZ256rr = 15123 + + VPBROADCASTQrZ256rrk = 15124 + + VPBROADCASTQrZ256rrkz = 15125 + + VPBROADCASTQrZrr = 15126 + + VPBROADCASTQrZrrk = 15127 + + VPBROADCASTQrZrrkz = 15128 + + VPBROADCASTQrm = 15129 + + VPBROADCASTQrr = 15130 + + VPBROADCASTWYrm = 15131 + + VPBROADCASTWYrr = 15132 + + VPBROADCASTWZ128rm = 15133 + + VPBROADCASTWZ128rmk = 15134 + + VPBROADCASTWZ128rmkz = 15135 + + VPBROADCASTWZ128rr = 15136 + + VPBROADCASTWZ128rrk = 15137 + + VPBROADCASTWZ128rrkz = 15138 + + VPBROADCASTWZ256rm = 15139 + + VPBROADCASTWZ256rmk = 15140 + + VPBROADCASTWZ256rmkz = 15141 + + VPBROADCASTWZ256rr = 15142 + + VPBROADCASTWZ256rrk = 15143 + + VPBROADCASTWZ256rrkz = 15144 + + VPBROADCASTWZrm = 15145 + + VPBROADCASTWZrmk = 15146 + + VPBROADCASTWZrmkz = 15147 + + VPBROADCASTWZrr = 15148 + + VPBROADCASTWZrrk = 15149 + + VPBROADCASTWZrrkz = 15150 + + VPBROADCASTWrZ128rr = 15151 + + VPBROADCASTWrZ128rrk = 15152 + + VPBROADCASTWrZ128rrkz = 15153 + + VPBROADCASTWrZ256rr = 15154 + + VPBROADCASTWrZ256rrk = 15155 + + VPBROADCASTWrZ256rrkz = 15156 + + VPBROADCASTWrZrr = 15157 + + VPBROADCASTWrZrrk = 15158 + + VPBROADCASTWrZrrkz = 15159 + + VPBROADCASTWrm = 15160 + + VPBROADCASTWrr = 15161 + + VPCLMULQDQYrmi = 15162 + + VPCLMULQDQYrri = 15163 + + VPCLMULQDQZ128rmi = 15164 + + VPCLMULQDQZ128rri = 15165 + + VPCLMULQDQZ256rmi = 15166 + + VPCLMULQDQZ256rri = 15167 + + VPCLMULQDQZrmi = 15168 + + VPCLMULQDQZrri = 15169 + + VPCLMULQDQrmi = 15170 + + VPCLMULQDQrri = 15171 + + VPCMOVYrmr = 15172 + + VPCMOVYrrm = 15173 + + VPCMOVYrrr = 15174 + + VPCMOVYrrr_REV = 15175 + + VPCMOVrmr = 15176 + + VPCMOVrrm = 15177 + + VPCMOVrrr = 15178 + + VPCMOVrrr_REV = 15179 + + VPCMPBZ128rmi = 15180 + + VPCMPBZ128rmik = 15181 + + VPCMPBZ128rri = 15182 + + VPCMPBZ128rrik = 15183 + + VPCMPBZ256rmi = 15184 + + VPCMPBZ256rmik = 15185 + + VPCMPBZ256rri = 15186 + + VPCMPBZ256rrik = 15187 + + VPCMPBZrmi = 15188 + + VPCMPBZrmik = 15189 + + VPCMPBZrri = 15190 + + VPCMPBZrrik = 15191 + + VPCMPDZ128rmbi = 15192 + + VPCMPDZ128rmbik = 15193 + + VPCMPDZ128rmi = 15194 + + VPCMPDZ128rmik = 15195 + + VPCMPDZ128rri = 15196 + + VPCMPDZ128rrik = 15197 + + VPCMPDZ256rmbi = 15198 + + VPCMPDZ256rmbik = 15199 + + VPCMPDZ256rmi = 15200 + + VPCMPDZ256rmik = 15201 + + VPCMPDZ256rri = 15202 + + VPCMPDZ256rrik = 15203 + + VPCMPDZrmbi = 15204 + + VPCMPDZrmbik = 15205 + + VPCMPDZrmi = 15206 + + VPCMPDZrmik = 15207 + + VPCMPDZrri = 15208 + + VPCMPDZrrik = 15209 + + VPCMPEQBYrm = 15210 + + VPCMPEQBYrr = 15211 + + VPCMPEQBZ128rm = 15212 + + VPCMPEQBZ128rmk = 15213 + + VPCMPEQBZ128rr = 15214 + + VPCMPEQBZ128rrk = 15215 + + VPCMPEQBZ256rm = 15216 + + VPCMPEQBZ256rmk = 15217 + + VPCMPEQBZ256rr = 15218 + + VPCMPEQBZ256rrk = 15219 + + VPCMPEQBZrm = 15220 + + VPCMPEQBZrmk = 15221 + + VPCMPEQBZrr = 15222 + + VPCMPEQBZrrk = 15223 + + VPCMPEQBrm = 15224 + + VPCMPEQBrr = 15225 + + VPCMPEQDYrm = 15226 + + VPCMPEQDYrr = 15227 + + VPCMPEQDZ128rm = 15228 + + VPCMPEQDZ128rmb = 15229 + + VPCMPEQDZ128rmbk = 15230 + + VPCMPEQDZ128rmk = 15231 + + VPCMPEQDZ128rr = 15232 + + VPCMPEQDZ128rrk = 15233 + + VPCMPEQDZ256rm = 15234 + + VPCMPEQDZ256rmb = 15235 + + VPCMPEQDZ256rmbk = 15236 + + VPCMPEQDZ256rmk = 15237 + + VPCMPEQDZ256rr = 15238 + + VPCMPEQDZ256rrk = 15239 + + VPCMPEQDZrm = 15240 + + VPCMPEQDZrmb = 15241 + + VPCMPEQDZrmbk = 15242 + + VPCMPEQDZrmk = 15243 + + VPCMPEQDZrr = 15244 + + VPCMPEQDZrrk = 15245 + + VPCMPEQDrm = 15246 + + VPCMPEQDrr = 15247 + + VPCMPEQQYrm = 15248 + + VPCMPEQQYrr = 15249 + + VPCMPEQQZ128rm = 15250 + + VPCMPEQQZ128rmb = 15251 + + VPCMPEQQZ128rmbk = 15252 + + VPCMPEQQZ128rmk = 15253 + + VPCMPEQQZ128rr = 15254 + + VPCMPEQQZ128rrk = 15255 + + VPCMPEQQZ256rm = 15256 + + VPCMPEQQZ256rmb = 15257 + + VPCMPEQQZ256rmbk = 15258 + + VPCMPEQQZ256rmk = 15259 + + VPCMPEQQZ256rr = 15260 + + VPCMPEQQZ256rrk = 15261 + + VPCMPEQQZrm = 15262 + + VPCMPEQQZrmb = 15263 + + VPCMPEQQZrmbk = 15264 + + VPCMPEQQZrmk = 15265 + + VPCMPEQQZrr = 15266 + + VPCMPEQQZrrk = 15267 + + VPCMPEQQrm = 15268 + + VPCMPEQQrr = 15269 + + VPCMPEQWYrm = 15270 + + VPCMPEQWYrr = 15271 + + VPCMPEQWZ128rm = 15272 + + VPCMPEQWZ128rmk = 15273 + + VPCMPEQWZ128rr = 15274 + + VPCMPEQWZ128rrk = 15275 + + VPCMPEQWZ256rm = 15276 + + VPCMPEQWZ256rmk = 15277 + + VPCMPEQWZ256rr = 15278 + + VPCMPEQWZ256rrk = 15279 + + VPCMPEQWZrm = 15280 + + VPCMPEQWZrmk = 15281 + + VPCMPEQWZrr = 15282 + + VPCMPEQWZrrk = 15283 + + VPCMPEQWrm = 15284 + + VPCMPEQWrr = 15285 + + VPCMPESTRIrmi = 15286 + + VPCMPESTRIrri = 15287 + + VPCMPESTRMrmi = 15288 + + VPCMPESTRMrri = 15289 + + VPCMPGTBYrm = 15290 + + VPCMPGTBYrr = 15291 + + VPCMPGTBZ128rm = 15292 + + VPCMPGTBZ128rmk = 15293 + + VPCMPGTBZ128rr = 15294 + + VPCMPGTBZ128rrk = 15295 + + VPCMPGTBZ256rm = 15296 + + VPCMPGTBZ256rmk = 15297 + + VPCMPGTBZ256rr = 15298 + + VPCMPGTBZ256rrk = 15299 + + VPCMPGTBZrm = 15300 + + VPCMPGTBZrmk = 15301 + + VPCMPGTBZrr = 15302 + + VPCMPGTBZrrk = 15303 + + VPCMPGTBrm = 15304 + + VPCMPGTBrr = 15305 + + VPCMPGTDYrm = 15306 + + VPCMPGTDYrr = 15307 + + VPCMPGTDZ128rm = 15308 + + VPCMPGTDZ128rmb = 15309 + + VPCMPGTDZ128rmbk = 15310 + + VPCMPGTDZ128rmk = 15311 + + VPCMPGTDZ128rr = 15312 + + VPCMPGTDZ128rrk = 15313 + + VPCMPGTDZ256rm = 15314 + + VPCMPGTDZ256rmb = 15315 + + VPCMPGTDZ256rmbk = 15316 + + VPCMPGTDZ256rmk = 15317 + + VPCMPGTDZ256rr = 15318 + + VPCMPGTDZ256rrk = 15319 + + VPCMPGTDZrm = 15320 + + VPCMPGTDZrmb = 15321 + + VPCMPGTDZrmbk = 15322 + + VPCMPGTDZrmk = 15323 + + VPCMPGTDZrr = 15324 + + VPCMPGTDZrrk = 15325 + + VPCMPGTDrm = 15326 + + VPCMPGTDrr = 15327 + + VPCMPGTQYrm = 15328 + + VPCMPGTQYrr = 15329 + + VPCMPGTQZ128rm = 15330 + + VPCMPGTQZ128rmb = 15331 + + VPCMPGTQZ128rmbk = 15332 + + VPCMPGTQZ128rmk = 15333 + + VPCMPGTQZ128rr = 15334 + + VPCMPGTQZ128rrk = 15335 + + VPCMPGTQZ256rm = 15336 + + VPCMPGTQZ256rmb = 15337 + + VPCMPGTQZ256rmbk = 15338 + + VPCMPGTQZ256rmk = 15339 + + VPCMPGTQZ256rr = 15340 + + VPCMPGTQZ256rrk = 15341 + + VPCMPGTQZrm = 15342 + + VPCMPGTQZrmb = 15343 + + VPCMPGTQZrmbk = 15344 + + VPCMPGTQZrmk = 15345 + + VPCMPGTQZrr = 15346 + + VPCMPGTQZrrk = 15347 + + VPCMPGTQrm = 15348 + + VPCMPGTQrr = 15349 + + VPCMPGTWYrm = 15350 + + VPCMPGTWYrr = 15351 + + VPCMPGTWZ128rm = 15352 + + VPCMPGTWZ128rmk = 15353 + + VPCMPGTWZ128rr = 15354 + + VPCMPGTWZ128rrk = 15355 + + VPCMPGTWZ256rm = 15356 + + VPCMPGTWZ256rmk = 15357 + + VPCMPGTWZ256rr = 15358 + + VPCMPGTWZ256rrk = 15359 + + VPCMPGTWZrm = 15360 + + VPCMPGTWZrmk = 15361 + + VPCMPGTWZrr = 15362 + + VPCMPGTWZrrk = 15363 + + VPCMPGTWrm = 15364 + + VPCMPGTWrr = 15365 + + VPCMPISTRIrmi = 15366 + + VPCMPISTRIrri = 15367 + + VPCMPISTRMrmi = 15368 + + VPCMPISTRMrri = 15369 + + VPCMPQZ128rmbi = 15370 + + VPCMPQZ128rmbik = 15371 + + VPCMPQZ128rmi = 15372 + + VPCMPQZ128rmik = 15373 + + VPCMPQZ128rri = 15374 + + VPCMPQZ128rrik = 15375 + + VPCMPQZ256rmbi = 15376 + + VPCMPQZ256rmbik = 15377 + + VPCMPQZ256rmi = 15378 + + VPCMPQZ256rmik = 15379 + + VPCMPQZ256rri = 15380 + + VPCMPQZ256rrik = 15381 + + VPCMPQZrmbi = 15382 + + VPCMPQZrmbik = 15383 + + VPCMPQZrmi = 15384 + + VPCMPQZrmik = 15385 + + VPCMPQZrri = 15386 + + VPCMPQZrrik = 15387 + + VPCMPUBZ128rmi = 15388 + + VPCMPUBZ128rmik = 15389 + + VPCMPUBZ128rri = 15390 + + VPCMPUBZ128rrik = 15391 + + VPCMPUBZ256rmi = 15392 + + VPCMPUBZ256rmik = 15393 + + VPCMPUBZ256rri = 15394 + + VPCMPUBZ256rrik = 15395 + + VPCMPUBZrmi = 15396 + + VPCMPUBZrmik = 15397 + + VPCMPUBZrri = 15398 + + VPCMPUBZrrik = 15399 + + VPCMPUDZ128rmbi = 15400 + + VPCMPUDZ128rmbik = 15401 + + VPCMPUDZ128rmi = 15402 + + VPCMPUDZ128rmik = 15403 + + VPCMPUDZ128rri = 15404 + + VPCMPUDZ128rrik = 15405 + + VPCMPUDZ256rmbi = 15406 + + VPCMPUDZ256rmbik = 15407 + + VPCMPUDZ256rmi = 15408 + + VPCMPUDZ256rmik = 15409 + + VPCMPUDZ256rri = 15410 + + VPCMPUDZ256rrik = 15411 + + VPCMPUDZrmbi = 15412 + + VPCMPUDZrmbik = 15413 + + VPCMPUDZrmi = 15414 + + VPCMPUDZrmik = 15415 + + VPCMPUDZrri = 15416 + + VPCMPUDZrrik = 15417 + + VPCMPUQZ128rmbi = 15418 + + VPCMPUQZ128rmbik = 15419 + + VPCMPUQZ128rmi = 15420 + + VPCMPUQZ128rmik = 15421 + + VPCMPUQZ128rri = 15422 + + VPCMPUQZ128rrik = 15423 + + VPCMPUQZ256rmbi = 15424 + + VPCMPUQZ256rmbik = 15425 + + VPCMPUQZ256rmi = 15426 + + VPCMPUQZ256rmik = 15427 + + VPCMPUQZ256rri = 15428 + + VPCMPUQZ256rrik = 15429 + + VPCMPUQZrmbi = 15430 + + VPCMPUQZrmbik = 15431 + + VPCMPUQZrmi = 15432 + + VPCMPUQZrmik = 15433 + + VPCMPUQZrri = 15434 + + VPCMPUQZrrik = 15435 + + VPCMPUWZ128rmi = 15436 + + VPCMPUWZ128rmik = 15437 + + VPCMPUWZ128rri = 15438 + + VPCMPUWZ128rrik = 15439 + + VPCMPUWZ256rmi = 15440 + + VPCMPUWZ256rmik = 15441 + + VPCMPUWZ256rri = 15442 + + VPCMPUWZ256rrik = 15443 + + VPCMPUWZrmi = 15444 + + VPCMPUWZrmik = 15445 + + VPCMPUWZrri = 15446 + + VPCMPUWZrrik = 15447 + + VPCMPWZ128rmi = 15448 + + VPCMPWZ128rmik = 15449 + + VPCMPWZ128rri = 15450 + + VPCMPWZ128rrik = 15451 + + VPCMPWZ256rmi = 15452 + + VPCMPWZ256rmik = 15453 + + VPCMPWZ256rri = 15454 + + VPCMPWZ256rrik = 15455 + + VPCMPWZrmi = 15456 + + VPCMPWZrmik = 15457 + + VPCMPWZrri = 15458 + + VPCMPWZrrik = 15459 + + VPCOMBmi = 15460 + + VPCOMBri = 15461 + + VPCOMDmi = 15462 + + VPCOMDri = 15463 + + VPCOMPRESSBZ128mr = 15464 + + VPCOMPRESSBZ128mrk = 15465 + + VPCOMPRESSBZ128rr = 15466 + + VPCOMPRESSBZ128rrk = 15467 + + VPCOMPRESSBZ128rrkz = 15468 + + VPCOMPRESSBZ256mr = 15469 + + VPCOMPRESSBZ256mrk = 15470 + + VPCOMPRESSBZ256rr = 15471 + + VPCOMPRESSBZ256rrk = 15472 + + VPCOMPRESSBZ256rrkz = 15473 + + VPCOMPRESSBZmr = 15474 + + VPCOMPRESSBZmrk = 15475 + + VPCOMPRESSBZrr = 15476 + + VPCOMPRESSBZrrk = 15477 + + VPCOMPRESSBZrrkz = 15478 + + VPCOMPRESSDZ128mr = 15479 + + VPCOMPRESSDZ128mrk = 15480 + + VPCOMPRESSDZ128rr = 15481 + + VPCOMPRESSDZ128rrk = 15482 + + VPCOMPRESSDZ128rrkz = 15483 + + VPCOMPRESSDZ256mr = 15484 + + VPCOMPRESSDZ256mrk = 15485 + + VPCOMPRESSDZ256rr = 15486 + + VPCOMPRESSDZ256rrk = 15487 + + VPCOMPRESSDZ256rrkz = 15488 + + VPCOMPRESSDZmr = 15489 + + VPCOMPRESSDZmrk = 15490 + + VPCOMPRESSDZrr = 15491 + + VPCOMPRESSDZrrk = 15492 + + VPCOMPRESSDZrrkz = 15493 + + VPCOMPRESSQZ128mr = 15494 + + VPCOMPRESSQZ128mrk = 15495 + + VPCOMPRESSQZ128rr = 15496 + + VPCOMPRESSQZ128rrk = 15497 + + VPCOMPRESSQZ128rrkz = 15498 + + VPCOMPRESSQZ256mr = 15499 + + VPCOMPRESSQZ256mrk = 15500 + + VPCOMPRESSQZ256rr = 15501 + + VPCOMPRESSQZ256rrk = 15502 + + VPCOMPRESSQZ256rrkz = 15503 + + VPCOMPRESSQZmr = 15504 + + VPCOMPRESSQZmrk = 15505 + + VPCOMPRESSQZrr = 15506 + + VPCOMPRESSQZrrk = 15507 + + VPCOMPRESSQZrrkz = 15508 + + VPCOMPRESSWZ128mr = 15509 + + VPCOMPRESSWZ128mrk = 15510 + + VPCOMPRESSWZ128rr = 15511 + + VPCOMPRESSWZ128rrk = 15512 + + VPCOMPRESSWZ128rrkz = 15513 + + VPCOMPRESSWZ256mr = 15514 + + VPCOMPRESSWZ256mrk = 15515 + + VPCOMPRESSWZ256rr = 15516 + + VPCOMPRESSWZ256rrk = 15517 + + VPCOMPRESSWZ256rrkz = 15518 + + VPCOMPRESSWZmr = 15519 + + VPCOMPRESSWZmrk = 15520 + + VPCOMPRESSWZrr = 15521 + + VPCOMPRESSWZrrk = 15522 + + VPCOMPRESSWZrrkz = 15523 + + VPCOMQmi = 15524 + + VPCOMQri = 15525 + + VPCOMUBmi = 15526 + + VPCOMUBri = 15527 + + VPCOMUDmi = 15528 + + VPCOMUDri = 15529 + + VPCOMUQmi = 15530 + + VPCOMUQri = 15531 + + VPCOMUWmi = 15532 + + VPCOMUWri = 15533 + + VPCOMWmi = 15534 + + VPCOMWri = 15535 + + VPCONFLICTDZ128rm = 15536 + + VPCONFLICTDZ128rmb = 15537 + + VPCONFLICTDZ128rmbk = 15538 + + VPCONFLICTDZ128rmbkz = 15539 + + VPCONFLICTDZ128rmk = 15540 + + VPCONFLICTDZ128rmkz = 15541 + + VPCONFLICTDZ128rr = 15542 + + VPCONFLICTDZ128rrk = 15543 + + VPCONFLICTDZ128rrkz = 15544 + + VPCONFLICTDZ256rm = 15545 + + VPCONFLICTDZ256rmb = 15546 + + VPCONFLICTDZ256rmbk = 15547 + + VPCONFLICTDZ256rmbkz = 15548 + + VPCONFLICTDZ256rmk = 15549 + + VPCONFLICTDZ256rmkz = 15550 + + VPCONFLICTDZ256rr = 15551 + + VPCONFLICTDZ256rrk = 15552 + + VPCONFLICTDZ256rrkz = 15553 + + VPCONFLICTDZrm = 15554 + + VPCONFLICTDZrmb = 15555 + + VPCONFLICTDZrmbk = 15556 + + VPCONFLICTDZrmbkz = 15557 + + VPCONFLICTDZrmk = 15558 + + VPCONFLICTDZrmkz = 15559 + + VPCONFLICTDZrr = 15560 + + VPCONFLICTDZrrk = 15561 + + VPCONFLICTDZrrkz = 15562 + + VPCONFLICTQZ128rm = 15563 + + VPCONFLICTQZ128rmb = 15564 + + VPCONFLICTQZ128rmbk = 15565 + + VPCONFLICTQZ128rmbkz = 15566 + + VPCONFLICTQZ128rmk = 15567 + + VPCONFLICTQZ128rmkz = 15568 + + VPCONFLICTQZ128rr = 15569 + + VPCONFLICTQZ128rrk = 15570 + + VPCONFLICTQZ128rrkz = 15571 + + VPCONFLICTQZ256rm = 15572 + + VPCONFLICTQZ256rmb = 15573 + + VPCONFLICTQZ256rmbk = 15574 + + VPCONFLICTQZ256rmbkz = 15575 + + VPCONFLICTQZ256rmk = 15576 + + VPCONFLICTQZ256rmkz = 15577 + + VPCONFLICTQZ256rr = 15578 + + VPCONFLICTQZ256rrk = 15579 + + VPCONFLICTQZ256rrkz = 15580 + + VPCONFLICTQZrm = 15581 + + VPCONFLICTQZrmb = 15582 + + VPCONFLICTQZrmbk = 15583 + + VPCONFLICTQZrmbkz = 15584 + + VPCONFLICTQZrmk = 15585 + + VPCONFLICTQZrmkz = 15586 + + VPCONFLICTQZrr = 15587 + + VPCONFLICTQZrrk = 15588 + + VPCONFLICTQZrrkz = 15589 + + VPDPBSSDSYrm = 15590 + + VPDPBSSDSYrr = 15591 + + VPDPBSSDSZ128rm = 15592 + + VPDPBSSDSZ128rmb = 15593 + + VPDPBSSDSZ128rmbk = 15594 + + VPDPBSSDSZ128rmbkz = 15595 + + VPDPBSSDSZ128rmk = 15596 + + VPDPBSSDSZ128rmkz = 15597 + + VPDPBSSDSZ128rr = 15598 + + VPDPBSSDSZ128rrk = 15599 + + VPDPBSSDSZ128rrkz = 15600 + + VPDPBSSDSZ256rm = 15601 + + VPDPBSSDSZ256rmb = 15602 + + VPDPBSSDSZ256rmbk = 15603 + + VPDPBSSDSZ256rmbkz = 15604 + + VPDPBSSDSZ256rmk = 15605 + + VPDPBSSDSZ256rmkz = 15606 + + VPDPBSSDSZ256rr = 15607 + + VPDPBSSDSZ256rrk = 15608 + + VPDPBSSDSZ256rrkz = 15609 + + VPDPBSSDSZrm = 15610 + + VPDPBSSDSZrmb = 15611 + + VPDPBSSDSZrmbk = 15612 + + VPDPBSSDSZrmbkz = 15613 + + VPDPBSSDSZrmk = 15614 + + VPDPBSSDSZrmkz = 15615 + + VPDPBSSDSZrr = 15616 + + VPDPBSSDSZrrk = 15617 + + VPDPBSSDSZrrkz = 15618 + + VPDPBSSDSrm = 15619 + + VPDPBSSDSrr = 15620 + + VPDPBSSDYrm = 15621 + + VPDPBSSDYrr = 15622 + + VPDPBSSDZ128rm = 15623 + + VPDPBSSDZ128rmb = 15624 + + VPDPBSSDZ128rmbk = 15625 + + VPDPBSSDZ128rmbkz = 15626 + + VPDPBSSDZ128rmk = 15627 + + VPDPBSSDZ128rmkz = 15628 + + VPDPBSSDZ128rr = 15629 + + VPDPBSSDZ128rrk = 15630 + + VPDPBSSDZ128rrkz = 15631 + + VPDPBSSDZ256rm = 15632 + + VPDPBSSDZ256rmb = 15633 + + VPDPBSSDZ256rmbk = 15634 + + VPDPBSSDZ256rmbkz = 15635 + + VPDPBSSDZ256rmk = 15636 + + VPDPBSSDZ256rmkz = 15637 + + VPDPBSSDZ256rr = 15638 + + VPDPBSSDZ256rrk = 15639 + + VPDPBSSDZ256rrkz = 15640 + + VPDPBSSDZrm = 15641 + + VPDPBSSDZrmb = 15642 + + VPDPBSSDZrmbk = 15643 + + VPDPBSSDZrmbkz = 15644 + + VPDPBSSDZrmk = 15645 + + VPDPBSSDZrmkz = 15646 + + VPDPBSSDZrr = 15647 + + VPDPBSSDZrrk = 15648 + + VPDPBSSDZrrkz = 15649 + + VPDPBSSDrm = 15650 + + VPDPBSSDrr = 15651 + + VPDPBSUDSYrm = 15652 + + VPDPBSUDSYrr = 15653 + + VPDPBSUDSZ128rm = 15654 + + VPDPBSUDSZ128rmb = 15655 + + VPDPBSUDSZ128rmbk = 15656 + + VPDPBSUDSZ128rmbkz = 15657 + + VPDPBSUDSZ128rmk = 15658 + + VPDPBSUDSZ128rmkz = 15659 + + VPDPBSUDSZ128rr = 15660 + + VPDPBSUDSZ128rrk = 15661 + + VPDPBSUDSZ128rrkz = 15662 + + VPDPBSUDSZ256rm = 15663 + + VPDPBSUDSZ256rmb = 15664 + + VPDPBSUDSZ256rmbk = 15665 + + VPDPBSUDSZ256rmbkz = 15666 + + VPDPBSUDSZ256rmk = 15667 + + VPDPBSUDSZ256rmkz = 15668 + + VPDPBSUDSZ256rr = 15669 + + VPDPBSUDSZ256rrk = 15670 + + VPDPBSUDSZ256rrkz = 15671 + + VPDPBSUDSZrm = 15672 + + VPDPBSUDSZrmb = 15673 + + VPDPBSUDSZrmbk = 15674 + + VPDPBSUDSZrmbkz = 15675 + + VPDPBSUDSZrmk = 15676 + + VPDPBSUDSZrmkz = 15677 + + VPDPBSUDSZrr = 15678 + + VPDPBSUDSZrrk = 15679 + + VPDPBSUDSZrrkz = 15680 + + VPDPBSUDSrm = 15681 + + VPDPBSUDSrr = 15682 + + VPDPBSUDYrm = 15683 + + VPDPBSUDYrr = 15684 + + VPDPBSUDZ128rm = 15685 + + VPDPBSUDZ128rmb = 15686 + + VPDPBSUDZ128rmbk = 15687 + + VPDPBSUDZ128rmbkz = 15688 + + VPDPBSUDZ128rmk = 15689 + + VPDPBSUDZ128rmkz = 15690 + + VPDPBSUDZ128rr = 15691 + + VPDPBSUDZ128rrk = 15692 + + VPDPBSUDZ128rrkz = 15693 + + VPDPBSUDZ256rm = 15694 + + VPDPBSUDZ256rmb = 15695 + + VPDPBSUDZ256rmbk = 15696 + + VPDPBSUDZ256rmbkz = 15697 + + VPDPBSUDZ256rmk = 15698 + + VPDPBSUDZ256rmkz = 15699 + + VPDPBSUDZ256rr = 15700 + + VPDPBSUDZ256rrk = 15701 + + VPDPBSUDZ256rrkz = 15702 + + VPDPBSUDZrm = 15703 + + VPDPBSUDZrmb = 15704 + + VPDPBSUDZrmbk = 15705 + + VPDPBSUDZrmbkz = 15706 + + VPDPBSUDZrmk = 15707 + + VPDPBSUDZrmkz = 15708 + + VPDPBSUDZrr = 15709 + + VPDPBSUDZrrk = 15710 + + VPDPBSUDZrrkz = 15711 + + VPDPBSUDrm = 15712 + + VPDPBSUDrr = 15713 + + VPDPBUSDSYrm = 15714 + + VPDPBUSDSYrr = 15715 + + VPDPBUSDSZ128rm = 15716 + + VPDPBUSDSZ128rmb = 15717 + + VPDPBUSDSZ128rmbk = 15718 + + VPDPBUSDSZ128rmbkz = 15719 + + VPDPBUSDSZ128rmk = 15720 + + VPDPBUSDSZ128rmkz = 15721 + + VPDPBUSDSZ128rr = 15722 + + VPDPBUSDSZ128rrk = 15723 + + VPDPBUSDSZ128rrkz = 15724 + + VPDPBUSDSZ256rm = 15725 + + VPDPBUSDSZ256rmb = 15726 + + VPDPBUSDSZ256rmbk = 15727 + + VPDPBUSDSZ256rmbkz = 15728 + + VPDPBUSDSZ256rmk = 15729 + + VPDPBUSDSZ256rmkz = 15730 + + VPDPBUSDSZ256rr = 15731 + + VPDPBUSDSZ256rrk = 15732 + + VPDPBUSDSZ256rrkz = 15733 + + VPDPBUSDSZrm = 15734 + + VPDPBUSDSZrmb = 15735 + + VPDPBUSDSZrmbk = 15736 + + VPDPBUSDSZrmbkz = 15737 + + VPDPBUSDSZrmk = 15738 + + VPDPBUSDSZrmkz = 15739 + + VPDPBUSDSZrr = 15740 + + VPDPBUSDSZrrk = 15741 + + VPDPBUSDSZrrkz = 15742 + + VPDPBUSDSrm = 15743 + + VPDPBUSDSrr = 15744 + + VPDPBUSDYrm = 15745 + + VPDPBUSDYrr = 15746 + + VPDPBUSDZ128rm = 15747 + + VPDPBUSDZ128rmb = 15748 + + VPDPBUSDZ128rmbk = 15749 + + VPDPBUSDZ128rmbkz = 15750 + + VPDPBUSDZ128rmk = 15751 + + VPDPBUSDZ128rmkz = 15752 + + VPDPBUSDZ128rr = 15753 + + VPDPBUSDZ128rrk = 15754 + + VPDPBUSDZ128rrkz = 15755 + + VPDPBUSDZ256rm = 15756 + + VPDPBUSDZ256rmb = 15757 + + VPDPBUSDZ256rmbk = 15758 + + VPDPBUSDZ256rmbkz = 15759 + + VPDPBUSDZ256rmk = 15760 + + VPDPBUSDZ256rmkz = 15761 + + VPDPBUSDZ256rr = 15762 + + VPDPBUSDZ256rrk = 15763 + + VPDPBUSDZ256rrkz = 15764 + + VPDPBUSDZrm = 15765 + + VPDPBUSDZrmb = 15766 + + VPDPBUSDZrmbk = 15767 + + VPDPBUSDZrmbkz = 15768 + + VPDPBUSDZrmk = 15769 + + VPDPBUSDZrmkz = 15770 + + VPDPBUSDZrr = 15771 + + VPDPBUSDZrrk = 15772 + + VPDPBUSDZrrkz = 15773 + + VPDPBUSDrm = 15774 + + VPDPBUSDrr = 15775 + + VPDPBUUDSYrm = 15776 + + VPDPBUUDSYrr = 15777 + + VPDPBUUDSZ128rm = 15778 + + VPDPBUUDSZ128rmb = 15779 + + VPDPBUUDSZ128rmbk = 15780 + + VPDPBUUDSZ128rmbkz = 15781 + + VPDPBUUDSZ128rmk = 15782 + + VPDPBUUDSZ128rmkz = 15783 + + VPDPBUUDSZ128rr = 15784 + + VPDPBUUDSZ128rrk = 15785 + + VPDPBUUDSZ128rrkz = 15786 + + VPDPBUUDSZ256rm = 15787 + + VPDPBUUDSZ256rmb = 15788 + + VPDPBUUDSZ256rmbk = 15789 + + VPDPBUUDSZ256rmbkz = 15790 + + VPDPBUUDSZ256rmk = 15791 + + VPDPBUUDSZ256rmkz = 15792 + + VPDPBUUDSZ256rr = 15793 + + VPDPBUUDSZ256rrk = 15794 + + VPDPBUUDSZ256rrkz = 15795 + + VPDPBUUDSZrm = 15796 + + VPDPBUUDSZrmb = 15797 + + VPDPBUUDSZrmbk = 15798 + + VPDPBUUDSZrmbkz = 15799 + + VPDPBUUDSZrmk = 15800 + + VPDPBUUDSZrmkz = 15801 + + VPDPBUUDSZrr = 15802 + + VPDPBUUDSZrrk = 15803 + + VPDPBUUDSZrrkz = 15804 + + VPDPBUUDSrm = 15805 + + VPDPBUUDSrr = 15806 + + VPDPBUUDYrm = 15807 + + VPDPBUUDYrr = 15808 + + VPDPBUUDZ128rm = 15809 + + VPDPBUUDZ128rmb = 15810 + + VPDPBUUDZ128rmbk = 15811 + + VPDPBUUDZ128rmbkz = 15812 + + VPDPBUUDZ128rmk = 15813 + + VPDPBUUDZ128rmkz = 15814 + + VPDPBUUDZ128rr = 15815 + + VPDPBUUDZ128rrk = 15816 + + VPDPBUUDZ128rrkz = 15817 + + VPDPBUUDZ256rm = 15818 + + VPDPBUUDZ256rmb = 15819 + + VPDPBUUDZ256rmbk = 15820 + + VPDPBUUDZ256rmbkz = 15821 + + VPDPBUUDZ256rmk = 15822 + + VPDPBUUDZ256rmkz = 15823 + + VPDPBUUDZ256rr = 15824 + + VPDPBUUDZ256rrk = 15825 + + VPDPBUUDZ256rrkz = 15826 + + VPDPBUUDZrm = 15827 + + VPDPBUUDZrmb = 15828 + + VPDPBUUDZrmbk = 15829 + + VPDPBUUDZrmbkz = 15830 + + VPDPBUUDZrmk = 15831 + + VPDPBUUDZrmkz = 15832 + + VPDPBUUDZrr = 15833 + + VPDPBUUDZrrk = 15834 + + VPDPBUUDZrrkz = 15835 + + VPDPBUUDrm = 15836 + + VPDPBUUDrr = 15837 + + VPDPWSSDSYrm = 15838 + + VPDPWSSDSYrr = 15839 + + VPDPWSSDSZ128rm = 15840 + + VPDPWSSDSZ128rmb = 15841 + + VPDPWSSDSZ128rmbk = 15842 + + VPDPWSSDSZ128rmbkz = 15843 + + VPDPWSSDSZ128rmk = 15844 + + VPDPWSSDSZ128rmkz = 15845 + + VPDPWSSDSZ128rr = 15846 + + VPDPWSSDSZ128rrk = 15847 + + VPDPWSSDSZ128rrkz = 15848 + + VPDPWSSDSZ256rm = 15849 + + VPDPWSSDSZ256rmb = 15850 + + VPDPWSSDSZ256rmbk = 15851 + + VPDPWSSDSZ256rmbkz = 15852 + + VPDPWSSDSZ256rmk = 15853 + + VPDPWSSDSZ256rmkz = 15854 + + VPDPWSSDSZ256rr = 15855 + + VPDPWSSDSZ256rrk = 15856 + + VPDPWSSDSZ256rrkz = 15857 + + VPDPWSSDSZrm = 15858 + + VPDPWSSDSZrmb = 15859 + + VPDPWSSDSZrmbk = 15860 + + VPDPWSSDSZrmbkz = 15861 + + VPDPWSSDSZrmk = 15862 + + VPDPWSSDSZrmkz = 15863 + + VPDPWSSDSZrr = 15864 + + VPDPWSSDSZrrk = 15865 + + VPDPWSSDSZrrkz = 15866 + + VPDPWSSDSrm = 15867 + + VPDPWSSDSrr = 15868 + + VPDPWSSDYrm = 15869 + + VPDPWSSDYrr = 15870 + + VPDPWSSDZ128rm = 15871 + + VPDPWSSDZ128rmb = 15872 + + VPDPWSSDZ128rmbk = 15873 + + VPDPWSSDZ128rmbkz = 15874 + + VPDPWSSDZ128rmk = 15875 + + VPDPWSSDZ128rmkz = 15876 + + VPDPWSSDZ128rr = 15877 + + VPDPWSSDZ128rrk = 15878 + + VPDPWSSDZ128rrkz = 15879 + + VPDPWSSDZ256rm = 15880 + + VPDPWSSDZ256rmb = 15881 + + VPDPWSSDZ256rmbk = 15882 + + VPDPWSSDZ256rmbkz = 15883 + + VPDPWSSDZ256rmk = 15884 + + VPDPWSSDZ256rmkz = 15885 + + VPDPWSSDZ256rr = 15886 + + VPDPWSSDZ256rrk = 15887 + + VPDPWSSDZ256rrkz = 15888 + + VPDPWSSDZrm = 15889 + + VPDPWSSDZrmb = 15890 + + VPDPWSSDZrmbk = 15891 + + VPDPWSSDZrmbkz = 15892 + + VPDPWSSDZrmk = 15893 + + VPDPWSSDZrmkz = 15894 + + VPDPWSSDZrr = 15895 + + VPDPWSSDZrrk = 15896 + + VPDPWSSDZrrkz = 15897 + + VPDPWSSDrm = 15898 + + VPDPWSSDrr = 15899 + + VPDPWSUDSYrm = 15900 + + VPDPWSUDSYrr = 15901 + + VPDPWSUDSZ128rm = 15902 + + VPDPWSUDSZ128rmb = 15903 + + VPDPWSUDSZ128rmbk = 15904 + + VPDPWSUDSZ128rmbkz = 15905 + + VPDPWSUDSZ128rmk = 15906 + + VPDPWSUDSZ128rmkz = 15907 + + VPDPWSUDSZ128rr = 15908 + + VPDPWSUDSZ128rrk = 15909 + + VPDPWSUDSZ128rrkz = 15910 + + VPDPWSUDSZ256rm = 15911 + + VPDPWSUDSZ256rmb = 15912 + + VPDPWSUDSZ256rmbk = 15913 + + VPDPWSUDSZ256rmbkz = 15914 + + VPDPWSUDSZ256rmk = 15915 + + VPDPWSUDSZ256rmkz = 15916 + + VPDPWSUDSZ256rr = 15917 + + VPDPWSUDSZ256rrk = 15918 + + VPDPWSUDSZ256rrkz = 15919 + + VPDPWSUDSZrm = 15920 + + VPDPWSUDSZrmb = 15921 + + VPDPWSUDSZrmbk = 15922 + + VPDPWSUDSZrmbkz = 15923 + + VPDPWSUDSZrmk = 15924 + + VPDPWSUDSZrmkz = 15925 + + VPDPWSUDSZrr = 15926 + + VPDPWSUDSZrrk = 15927 + + VPDPWSUDSZrrkz = 15928 + + VPDPWSUDSrm = 15929 + + VPDPWSUDSrr = 15930 + + VPDPWSUDYrm = 15931 + + VPDPWSUDYrr = 15932 + + VPDPWSUDZ128rm = 15933 + + VPDPWSUDZ128rmb = 15934 + + VPDPWSUDZ128rmbk = 15935 + + VPDPWSUDZ128rmbkz = 15936 + + VPDPWSUDZ128rmk = 15937 + + VPDPWSUDZ128rmkz = 15938 + + VPDPWSUDZ128rr = 15939 + + VPDPWSUDZ128rrk = 15940 + + VPDPWSUDZ128rrkz = 15941 + + VPDPWSUDZ256rm = 15942 + + VPDPWSUDZ256rmb = 15943 + + VPDPWSUDZ256rmbk = 15944 + + VPDPWSUDZ256rmbkz = 15945 + + VPDPWSUDZ256rmk = 15946 + + VPDPWSUDZ256rmkz = 15947 + + VPDPWSUDZ256rr = 15948 + + VPDPWSUDZ256rrk = 15949 + + VPDPWSUDZ256rrkz = 15950 + + VPDPWSUDZrm = 15951 + + VPDPWSUDZrmb = 15952 + + VPDPWSUDZrmbk = 15953 + + VPDPWSUDZrmbkz = 15954 + + VPDPWSUDZrmk = 15955 + + VPDPWSUDZrmkz = 15956 + + VPDPWSUDZrr = 15957 + + VPDPWSUDZrrk = 15958 + + VPDPWSUDZrrkz = 15959 + + VPDPWSUDrm = 15960 + + VPDPWSUDrr = 15961 + + VPDPWUSDSYrm = 15962 + + VPDPWUSDSYrr = 15963 + + VPDPWUSDSZ128rm = 15964 + + VPDPWUSDSZ128rmb = 15965 + + VPDPWUSDSZ128rmbk = 15966 + + VPDPWUSDSZ128rmbkz = 15967 + + VPDPWUSDSZ128rmk = 15968 + + VPDPWUSDSZ128rmkz = 15969 + + VPDPWUSDSZ128rr = 15970 + + VPDPWUSDSZ128rrk = 15971 + + VPDPWUSDSZ128rrkz = 15972 + + VPDPWUSDSZ256rm = 15973 + + VPDPWUSDSZ256rmb = 15974 + + VPDPWUSDSZ256rmbk = 15975 + + VPDPWUSDSZ256rmbkz = 15976 + + VPDPWUSDSZ256rmk = 15977 + + VPDPWUSDSZ256rmkz = 15978 + + VPDPWUSDSZ256rr = 15979 + + VPDPWUSDSZ256rrk = 15980 + + VPDPWUSDSZ256rrkz = 15981 + + VPDPWUSDSZrm = 15982 + + VPDPWUSDSZrmb = 15983 + + VPDPWUSDSZrmbk = 15984 + + VPDPWUSDSZrmbkz = 15985 + + VPDPWUSDSZrmk = 15986 + + VPDPWUSDSZrmkz = 15987 + + VPDPWUSDSZrr = 15988 + + VPDPWUSDSZrrk = 15989 + + VPDPWUSDSZrrkz = 15990 + + VPDPWUSDSrm = 15991 + + VPDPWUSDSrr = 15992 + + VPDPWUSDYrm = 15993 + + VPDPWUSDYrr = 15994 + + VPDPWUSDZ128rm = 15995 + + VPDPWUSDZ128rmb = 15996 + + VPDPWUSDZ128rmbk = 15997 + + VPDPWUSDZ128rmbkz = 15998 + + VPDPWUSDZ128rmk = 15999 + + VPDPWUSDZ128rmkz = 16000 + + VPDPWUSDZ128rr = 16001 + + VPDPWUSDZ128rrk = 16002 + + VPDPWUSDZ128rrkz = 16003 + + VPDPWUSDZ256rm = 16004 + + VPDPWUSDZ256rmb = 16005 + + VPDPWUSDZ256rmbk = 16006 + + VPDPWUSDZ256rmbkz = 16007 + + VPDPWUSDZ256rmk = 16008 + + VPDPWUSDZ256rmkz = 16009 + + VPDPWUSDZ256rr = 16010 + + VPDPWUSDZ256rrk = 16011 + + VPDPWUSDZ256rrkz = 16012 + + VPDPWUSDZrm = 16013 + + VPDPWUSDZrmb = 16014 + + VPDPWUSDZrmbk = 16015 + + VPDPWUSDZrmbkz = 16016 + + VPDPWUSDZrmk = 16017 + + VPDPWUSDZrmkz = 16018 + + VPDPWUSDZrr = 16019 + + VPDPWUSDZrrk = 16020 + + VPDPWUSDZrrkz = 16021 + + VPDPWUSDrm = 16022 + + VPDPWUSDrr = 16023 + + VPDPWUUDSYrm = 16024 + + VPDPWUUDSYrr = 16025 + + VPDPWUUDSZ128rm = 16026 + + VPDPWUUDSZ128rmb = 16027 + + VPDPWUUDSZ128rmbk = 16028 + + VPDPWUUDSZ128rmbkz = 16029 + + VPDPWUUDSZ128rmk = 16030 + + VPDPWUUDSZ128rmkz = 16031 + + VPDPWUUDSZ128rr = 16032 + + VPDPWUUDSZ128rrk = 16033 + + VPDPWUUDSZ128rrkz = 16034 + + VPDPWUUDSZ256rm = 16035 + + VPDPWUUDSZ256rmb = 16036 + + VPDPWUUDSZ256rmbk = 16037 + + VPDPWUUDSZ256rmbkz = 16038 + + VPDPWUUDSZ256rmk = 16039 + + VPDPWUUDSZ256rmkz = 16040 + + VPDPWUUDSZ256rr = 16041 + + VPDPWUUDSZ256rrk = 16042 + + VPDPWUUDSZ256rrkz = 16043 + + VPDPWUUDSZrm = 16044 + + VPDPWUUDSZrmb = 16045 + + VPDPWUUDSZrmbk = 16046 + + VPDPWUUDSZrmbkz = 16047 + + VPDPWUUDSZrmk = 16048 + + VPDPWUUDSZrmkz = 16049 + + VPDPWUUDSZrr = 16050 + + VPDPWUUDSZrrk = 16051 + + VPDPWUUDSZrrkz = 16052 + + VPDPWUUDSrm = 16053 + + VPDPWUUDSrr = 16054 + + VPDPWUUDYrm = 16055 + + VPDPWUUDYrr = 16056 + + VPDPWUUDZ128rm = 16057 + + VPDPWUUDZ128rmb = 16058 + + VPDPWUUDZ128rmbk = 16059 + + VPDPWUUDZ128rmbkz = 16060 + + VPDPWUUDZ128rmk = 16061 + + VPDPWUUDZ128rmkz = 16062 + + VPDPWUUDZ128rr = 16063 + + VPDPWUUDZ128rrk = 16064 + + VPDPWUUDZ128rrkz = 16065 + + VPDPWUUDZ256rm = 16066 + + VPDPWUUDZ256rmb = 16067 + + VPDPWUUDZ256rmbk = 16068 + + VPDPWUUDZ256rmbkz = 16069 + + VPDPWUUDZ256rmk = 16070 + + VPDPWUUDZ256rmkz = 16071 + + VPDPWUUDZ256rr = 16072 + + VPDPWUUDZ256rrk = 16073 + + VPDPWUUDZ256rrkz = 16074 + + VPDPWUUDZrm = 16075 + + VPDPWUUDZrmb = 16076 + + VPDPWUUDZrmbk = 16077 + + VPDPWUUDZrmbkz = 16078 + + VPDPWUUDZrmk = 16079 + + VPDPWUUDZrmkz = 16080 + + VPDPWUUDZrr = 16081 + + VPDPWUUDZrrk = 16082 + + VPDPWUUDZrrkz = 16083 + + VPDPWUUDrm = 16084 + + VPDPWUUDrr = 16085 + + VPERM2F128rmi = 16086 + + VPERM2F128rri = 16087 + + VPERM2I128rmi = 16088 + + VPERM2I128rri = 16089 + + VPERMBZ128rm = 16090 + + VPERMBZ128rmk = 16091 + + VPERMBZ128rmkz = 16092 + + VPERMBZ128rr = 16093 + + VPERMBZ128rrk = 16094 + + VPERMBZ128rrkz = 16095 + + VPERMBZ256rm = 16096 + + VPERMBZ256rmk = 16097 + + VPERMBZ256rmkz = 16098 + + VPERMBZ256rr = 16099 + + VPERMBZ256rrk = 16100 + + VPERMBZ256rrkz = 16101 + + VPERMBZrm = 16102 + + VPERMBZrmk = 16103 + + VPERMBZrmkz = 16104 + + VPERMBZrr = 16105 + + VPERMBZrrk = 16106 + + VPERMBZrrkz = 16107 + + VPERMDYrm = 16108 + + VPERMDYrr = 16109 + + VPERMDZ256rm = 16110 + + VPERMDZ256rmb = 16111 + + VPERMDZ256rmbk = 16112 + + VPERMDZ256rmbkz = 16113 + + VPERMDZ256rmk = 16114 + + VPERMDZ256rmkz = 16115 + + VPERMDZ256rr = 16116 + + VPERMDZ256rrk = 16117 + + VPERMDZ256rrkz = 16118 + + VPERMDZrm = 16119 + + VPERMDZrmb = 16120 + + VPERMDZrmbk = 16121 + + VPERMDZrmbkz = 16122 + + VPERMDZrmk = 16123 + + VPERMDZrmkz = 16124 + + VPERMDZrr = 16125 + + VPERMDZrrk = 16126 + + VPERMDZrrkz = 16127 + + VPERMI2BZ128rm = 16128 + + VPERMI2BZ128rmk = 16129 + + VPERMI2BZ128rmkz = 16130 + + VPERMI2BZ128rr = 16131 + + VPERMI2BZ128rrk = 16132 + + VPERMI2BZ128rrkz = 16133 + + VPERMI2BZ256rm = 16134 + + VPERMI2BZ256rmk = 16135 + + VPERMI2BZ256rmkz = 16136 + + VPERMI2BZ256rr = 16137 + + VPERMI2BZ256rrk = 16138 + + VPERMI2BZ256rrkz = 16139 + + VPERMI2BZrm = 16140 + + VPERMI2BZrmk = 16141 + + VPERMI2BZrmkz = 16142 + + VPERMI2BZrr = 16143 + + VPERMI2BZrrk = 16144 + + VPERMI2BZrrkz = 16145 + + VPERMI2DZ128rm = 16146 + + VPERMI2DZ128rmb = 16147 + + VPERMI2DZ128rmbk = 16148 + + VPERMI2DZ128rmbkz = 16149 + + VPERMI2DZ128rmk = 16150 + + VPERMI2DZ128rmkz = 16151 + + VPERMI2DZ128rr = 16152 + + VPERMI2DZ128rrk = 16153 + + VPERMI2DZ128rrkz = 16154 + + VPERMI2DZ256rm = 16155 + + VPERMI2DZ256rmb = 16156 + + VPERMI2DZ256rmbk = 16157 + + VPERMI2DZ256rmbkz = 16158 + + VPERMI2DZ256rmk = 16159 + + VPERMI2DZ256rmkz = 16160 + + VPERMI2DZ256rr = 16161 + + VPERMI2DZ256rrk = 16162 + + VPERMI2DZ256rrkz = 16163 + + VPERMI2DZrm = 16164 + + VPERMI2DZrmb = 16165 + + VPERMI2DZrmbk = 16166 + + VPERMI2DZrmbkz = 16167 + + VPERMI2DZrmk = 16168 + + VPERMI2DZrmkz = 16169 + + VPERMI2DZrr = 16170 + + VPERMI2DZrrk = 16171 + + VPERMI2DZrrkz = 16172 + + VPERMI2PDZ128rm = 16173 + + VPERMI2PDZ128rmb = 16174 + + VPERMI2PDZ128rmbk = 16175 + + VPERMI2PDZ128rmbkz = 16176 + + VPERMI2PDZ128rmk = 16177 + + VPERMI2PDZ128rmkz = 16178 + + VPERMI2PDZ128rr = 16179 + + VPERMI2PDZ128rrk = 16180 + + VPERMI2PDZ128rrkz = 16181 + + VPERMI2PDZ256rm = 16182 + + VPERMI2PDZ256rmb = 16183 + + VPERMI2PDZ256rmbk = 16184 + + VPERMI2PDZ256rmbkz = 16185 + + VPERMI2PDZ256rmk = 16186 + + VPERMI2PDZ256rmkz = 16187 + + VPERMI2PDZ256rr = 16188 + + VPERMI2PDZ256rrk = 16189 + + VPERMI2PDZ256rrkz = 16190 + + VPERMI2PDZrm = 16191 + + VPERMI2PDZrmb = 16192 + + VPERMI2PDZrmbk = 16193 + + VPERMI2PDZrmbkz = 16194 + + VPERMI2PDZrmk = 16195 + + VPERMI2PDZrmkz = 16196 + + VPERMI2PDZrr = 16197 + + VPERMI2PDZrrk = 16198 + + VPERMI2PDZrrkz = 16199 + + VPERMI2PSZ128rm = 16200 + + VPERMI2PSZ128rmb = 16201 + + VPERMI2PSZ128rmbk = 16202 + + VPERMI2PSZ128rmbkz = 16203 + + VPERMI2PSZ128rmk = 16204 + + VPERMI2PSZ128rmkz = 16205 + + VPERMI2PSZ128rr = 16206 + + VPERMI2PSZ128rrk = 16207 + + VPERMI2PSZ128rrkz = 16208 + + VPERMI2PSZ256rm = 16209 + + VPERMI2PSZ256rmb = 16210 + + VPERMI2PSZ256rmbk = 16211 + + VPERMI2PSZ256rmbkz = 16212 + + VPERMI2PSZ256rmk = 16213 + + VPERMI2PSZ256rmkz = 16214 + + VPERMI2PSZ256rr = 16215 + + VPERMI2PSZ256rrk = 16216 + + VPERMI2PSZ256rrkz = 16217 + + VPERMI2PSZrm = 16218 + + VPERMI2PSZrmb = 16219 + + VPERMI2PSZrmbk = 16220 + + VPERMI2PSZrmbkz = 16221 + + VPERMI2PSZrmk = 16222 + + VPERMI2PSZrmkz = 16223 + + VPERMI2PSZrr = 16224 + + VPERMI2PSZrrk = 16225 + + VPERMI2PSZrrkz = 16226 + + VPERMI2QZ128rm = 16227 + + VPERMI2QZ128rmb = 16228 + + VPERMI2QZ128rmbk = 16229 + + VPERMI2QZ128rmbkz = 16230 + + VPERMI2QZ128rmk = 16231 + + VPERMI2QZ128rmkz = 16232 + + VPERMI2QZ128rr = 16233 + + VPERMI2QZ128rrk = 16234 + + VPERMI2QZ128rrkz = 16235 + + VPERMI2QZ256rm = 16236 + + VPERMI2QZ256rmb = 16237 + + VPERMI2QZ256rmbk = 16238 + + VPERMI2QZ256rmbkz = 16239 + + VPERMI2QZ256rmk = 16240 + + VPERMI2QZ256rmkz = 16241 + + VPERMI2QZ256rr = 16242 + + VPERMI2QZ256rrk = 16243 + + VPERMI2QZ256rrkz = 16244 + + VPERMI2QZrm = 16245 + + VPERMI2QZrmb = 16246 + + VPERMI2QZrmbk = 16247 + + VPERMI2QZrmbkz = 16248 + + VPERMI2QZrmk = 16249 + + VPERMI2QZrmkz = 16250 + + VPERMI2QZrr = 16251 + + VPERMI2QZrrk = 16252 + + VPERMI2QZrrkz = 16253 + + VPERMI2WZ128rm = 16254 + + VPERMI2WZ128rmk = 16255 + + VPERMI2WZ128rmkz = 16256 + + VPERMI2WZ128rr = 16257 + + VPERMI2WZ128rrk = 16258 + + VPERMI2WZ128rrkz = 16259 + + VPERMI2WZ256rm = 16260 + + VPERMI2WZ256rmk = 16261 + + VPERMI2WZ256rmkz = 16262 + + VPERMI2WZ256rr = 16263 + + VPERMI2WZ256rrk = 16264 + + VPERMI2WZ256rrkz = 16265 + + VPERMI2WZrm = 16266 + + VPERMI2WZrmk = 16267 + + VPERMI2WZrmkz = 16268 + + VPERMI2WZrr = 16269 + + VPERMI2WZrrk = 16270 + + VPERMI2WZrrkz = 16271 + + VPERMIL2PDYmr = 16272 + + VPERMIL2PDYrm = 16273 + + VPERMIL2PDYrr = 16274 + + VPERMIL2PDYrr_REV = 16275 + + VPERMIL2PDmr = 16276 + + VPERMIL2PDrm = 16277 + + VPERMIL2PDrr = 16278 + + VPERMIL2PDrr_REV = 16279 + + VPERMIL2PSYmr = 16280 + + VPERMIL2PSYrm = 16281 + + VPERMIL2PSYrr = 16282 + + VPERMIL2PSYrr_REV = 16283 + + VPERMIL2PSmr = 16284 + + VPERMIL2PSrm = 16285 + + VPERMIL2PSrr = 16286 + + VPERMIL2PSrr_REV = 16287 + + VPERMILPDYmi = 16288 + + VPERMILPDYri = 16289 + + VPERMILPDYrm = 16290 + + VPERMILPDYrr = 16291 + + VPERMILPDZ128mbi = 16292 + + VPERMILPDZ128mbik = 16293 + + VPERMILPDZ128mbikz = 16294 + + VPERMILPDZ128mi = 16295 + + VPERMILPDZ128mik = 16296 + + VPERMILPDZ128mikz = 16297 + + VPERMILPDZ128ri = 16298 + + VPERMILPDZ128rik = 16299 + + VPERMILPDZ128rikz = 16300 + + VPERMILPDZ128rm = 16301 + + VPERMILPDZ128rmb = 16302 + + VPERMILPDZ128rmbk = 16303 + + VPERMILPDZ128rmbkz = 16304 + + VPERMILPDZ128rmk = 16305 + + VPERMILPDZ128rmkz = 16306 + + VPERMILPDZ128rr = 16307 + + VPERMILPDZ128rrk = 16308 + + VPERMILPDZ128rrkz = 16309 + + VPERMILPDZ256mbi = 16310 + + VPERMILPDZ256mbik = 16311 + + VPERMILPDZ256mbikz = 16312 + + VPERMILPDZ256mi = 16313 + + VPERMILPDZ256mik = 16314 + + VPERMILPDZ256mikz = 16315 + + VPERMILPDZ256ri = 16316 + + VPERMILPDZ256rik = 16317 + + VPERMILPDZ256rikz = 16318 + + VPERMILPDZ256rm = 16319 + + VPERMILPDZ256rmb = 16320 + + VPERMILPDZ256rmbk = 16321 + + VPERMILPDZ256rmbkz = 16322 + + VPERMILPDZ256rmk = 16323 + + VPERMILPDZ256rmkz = 16324 + + VPERMILPDZ256rr = 16325 + + VPERMILPDZ256rrk = 16326 + + VPERMILPDZ256rrkz = 16327 + + VPERMILPDZmbi = 16328 + + VPERMILPDZmbik = 16329 + + VPERMILPDZmbikz = 16330 + + VPERMILPDZmi = 16331 + + VPERMILPDZmik = 16332 + + VPERMILPDZmikz = 16333 + + VPERMILPDZri = 16334 + + VPERMILPDZrik = 16335 + + VPERMILPDZrikz = 16336 + + VPERMILPDZrm = 16337 + + VPERMILPDZrmb = 16338 + + VPERMILPDZrmbk = 16339 + + VPERMILPDZrmbkz = 16340 + + VPERMILPDZrmk = 16341 + + VPERMILPDZrmkz = 16342 + + VPERMILPDZrr = 16343 + + VPERMILPDZrrk = 16344 + + VPERMILPDZrrkz = 16345 + + VPERMILPDmi = 16346 + + VPERMILPDri = 16347 + + VPERMILPDrm = 16348 + + VPERMILPDrr = 16349 + + VPERMILPSYmi = 16350 + + VPERMILPSYri = 16351 + + VPERMILPSYrm = 16352 + + VPERMILPSYrr = 16353 + + VPERMILPSZ128mbi = 16354 + + VPERMILPSZ128mbik = 16355 + + VPERMILPSZ128mbikz = 16356 + + VPERMILPSZ128mi = 16357 + + VPERMILPSZ128mik = 16358 + + VPERMILPSZ128mikz = 16359 + + VPERMILPSZ128ri = 16360 + + VPERMILPSZ128rik = 16361 + + VPERMILPSZ128rikz = 16362 + + VPERMILPSZ128rm = 16363 + + VPERMILPSZ128rmb = 16364 + + VPERMILPSZ128rmbk = 16365 + + VPERMILPSZ128rmbkz = 16366 + + VPERMILPSZ128rmk = 16367 + + VPERMILPSZ128rmkz = 16368 + + VPERMILPSZ128rr = 16369 + + VPERMILPSZ128rrk = 16370 + + VPERMILPSZ128rrkz = 16371 + + VPERMILPSZ256mbi = 16372 + + VPERMILPSZ256mbik = 16373 + + VPERMILPSZ256mbikz = 16374 + + VPERMILPSZ256mi = 16375 + + VPERMILPSZ256mik = 16376 + + VPERMILPSZ256mikz = 16377 + + VPERMILPSZ256ri = 16378 + + VPERMILPSZ256rik = 16379 + + VPERMILPSZ256rikz = 16380 + + VPERMILPSZ256rm = 16381 + + VPERMILPSZ256rmb = 16382 + + VPERMILPSZ256rmbk = 16383 + + VPERMILPSZ256rmbkz = 16384 + + VPERMILPSZ256rmk = 16385 + + VPERMILPSZ256rmkz = 16386 + + VPERMILPSZ256rr = 16387 + + VPERMILPSZ256rrk = 16388 + + VPERMILPSZ256rrkz = 16389 + + VPERMILPSZmbi = 16390 + + VPERMILPSZmbik = 16391 + + VPERMILPSZmbikz = 16392 + + VPERMILPSZmi = 16393 + + VPERMILPSZmik = 16394 + + VPERMILPSZmikz = 16395 + + VPERMILPSZri = 16396 + + VPERMILPSZrik = 16397 + + VPERMILPSZrikz = 16398 + + VPERMILPSZrm = 16399 + + VPERMILPSZrmb = 16400 + + VPERMILPSZrmbk = 16401 + + VPERMILPSZrmbkz = 16402 + + VPERMILPSZrmk = 16403 + + VPERMILPSZrmkz = 16404 + + VPERMILPSZrr = 16405 + + VPERMILPSZrrk = 16406 + + VPERMILPSZrrkz = 16407 + + VPERMILPSmi = 16408 + + VPERMILPSri = 16409 + + VPERMILPSrm = 16410 + + VPERMILPSrr = 16411 + + VPERMPDYmi = 16412 + + VPERMPDYri = 16413 + + VPERMPDZ256mbi = 16414 + + VPERMPDZ256mbik = 16415 + + VPERMPDZ256mbikz = 16416 + + VPERMPDZ256mi = 16417 + + VPERMPDZ256mik = 16418 + + VPERMPDZ256mikz = 16419 + + VPERMPDZ256ri = 16420 + + VPERMPDZ256rik = 16421 + + VPERMPDZ256rikz = 16422 + + VPERMPDZ256rm = 16423 + + VPERMPDZ256rmb = 16424 + + VPERMPDZ256rmbk = 16425 + + VPERMPDZ256rmbkz = 16426 + + VPERMPDZ256rmk = 16427 + + VPERMPDZ256rmkz = 16428 + + VPERMPDZ256rr = 16429 + + VPERMPDZ256rrk = 16430 + + VPERMPDZ256rrkz = 16431 + + VPERMPDZmbi = 16432 + + VPERMPDZmbik = 16433 + + VPERMPDZmbikz = 16434 + + VPERMPDZmi = 16435 + + VPERMPDZmik = 16436 + + VPERMPDZmikz = 16437 + + VPERMPDZri = 16438 + + VPERMPDZrik = 16439 + + VPERMPDZrikz = 16440 + + VPERMPDZrm = 16441 + + VPERMPDZrmb = 16442 + + VPERMPDZrmbk = 16443 + + VPERMPDZrmbkz = 16444 + + VPERMPDZrmk = 16445 + + VPERMPDZrmkz = 16446 + + VPERMPDZrr = 16447 + + VPERMPDZrrk = 16448 + + VPERMPDZrrkz = 16449 + + VPERMPSYrm = 16450 + + VPERMPSYrr = 16451 + + VPERMPSZ256rm = 16452 + + VPERMPSZ256rmb = 16453 + + VPERMPSZ256rmbk = 16454 + + VPERMPSZ256rmbkz = 16455 + + VPERMPSZ256rmk = 16456 + + VPERMPSZ256rmkz = 16457 + + VPERMPSZ256rr = 16458 + + VPERMPSZ256rrk = 16459 + + VPERMPSZ256rrkz = 16460 + + VPERMPSZrm = 16461 + + VPERMPSZrmb = 16462 + + VPERMPSZrmbk = 16463 + + VPERMPSZrmbkz = 16464 + + VPERMPSZrmk = 16465 + + VPERMPSZrmkz = 16466 + + VPERMPSZrr = 16467 + + VPERMPSZrrk = 16468 + + VPERMPSZrrkz = 16469 + + VPERMQYmi = 16470 + + VPERMQYri = 16471 + + VPERMQZ256mbi = 16472 + + VPERMQZ256mbik = 16473 + + VPERMQZ256mbikz = 16474 + + VPERMQZ256mi = 16475 + + VPERMQZ256mik = 16476 + + VPERMQZ256mikz = 16477 + + VPERMQZ256ri = 16478 + + VPERMQZ256rik = 16479 + + VPERMQZ256rikz = 16480 + + VPERMQZ256rm = 16481 + + VPERMQZ256rmb = 16482 + + VPERMQZ256rmbk = 16483 + + VPERMQZ256rmbkz = 16484 + + VPERMQZ256rmk = 16485 + + VPERMQZ256rmkz = 16486 + + VPERMQZ256rr = 16487 + + VPERMQZ256rrk = 16488 + + VPERMQZ256rrkz = 16489 + + VPERMQZmbi = 16490 + + VPERMQZmbik = 16491 + + VPERMQZmbikz = 16492 + + VPERMQZmi = 16493 + + VPERMQZmik = 16494 + + VPERMQZmikz = 16495 + + VPERMQZri = 16496 + + VPERMQZrik = 16497 + + VPERMQZrikz = 16498 + + VPERMQZrm = 16499 + + VPERMQZrmb = 16500 + + VPERMQZrmbk = 16501 + + VPERMQZrmbkz = 16502 + + VPERMQZrmk = 16503 + + VPERMQZrmkz = 16504 + + VPERMQZrr = 16505 + + VPERMQZrrk = 16506 + + VPERMQZrrkz = 16507 + + VPERMT2BZ128rm = 16508 + + VPERMT2BZ128rmk = 16509 + + VPERMT2BZ128rmkz = 16510 + + VPERMT2BZ128rr = 16511 + + VPERMT2BZ128rrk = 16512 + + VPERMT2BZ128rrkz = 16513 + + VPERMT2BZ256rm = 16514 + + VPERMT2BZ256rmk = 16515 + + VPERMT2BZ256rmkz = 16516 + + VPERMT2BZ256rr = 16517 + + VPERMT2BZ256rrk = 16518 + + VPERMT2BZ256rrkz = 16519 + + VPERMT2BZrm = 16520 + + VPERMT2BZrmk = 16521 + + VPERMT2BZrmkz = 16522 + + VPERMT2BZrr = 16523 + + VPERMT2BZrrk = 16524 + + VPERMT2BZrrkz = 16525 + + VPERMT2DZ128rm = 16526 + + VPERMT2DZ128rmb = 16527 + + VPERMT2DZ128rmbk = 16528 + + VPERMT2DZ128rmbkz = 16529 + + VPERMT2DZ128rmk = 16530 + + VPERMT2DZ128rmkz = 16531 + + VPERMT2DZ128rr = 16532 + + VPERMT2DZ128rrk = 16533 + + VPERMT2DZ128rrkz = 16534 + + VPERMT2DZ256rm = 16535 + + VPERMT2DZ256rmb = 16536 + + VPERMT2DZ256rmbk = 16537 + + VPERMT2DZ256rmbkz = 16538 + + VPERMT2DZ256rmk = 16539 + + VPERMT2DZ256rmkz = 16540 + + VPERMT2DZ256rr = 16541 + + VPERMT2DZ256rrk = 16542 + + VPERMT2DZ256rrkz = 16543 + + VPERMT2DZrm = 16544 + + VPERMT2DZrmb = 16545 + + VPERMT2DZrmbk = 16546 + + VPERMT2DZrmbkz = 16547 + + VPERMT2DZrmk = 16548 + + VPERMT2DZrmkz = 16549 + + VPERMT2DZrr = 16550 + + VPERMT2DZrrk = 16551 + + VPERMT2DZrrkz = 16552 + + VPERMT2PDZ128rm = 16553 + + VPERMT2PDZ128rmb = 16554 + + VPERMT2PDZ128rmbk = 16555 + + VPERMT2PDZ128rmbkz = 16556 + + VPERMT2PDZ128rmk = 16557 + + VPERMT2PDZ128rmkz = 16558 + + VPERMT2PDZ128rr = 16559 + + VPERMT2PDZ128rrk = 16560 + + VPERMT2PDZ128rrkz = 16561 + + VPERMT2PDZ256rm = 16562 + + VPERMT2PDZ256rmb = 16563 + + VPERMT2PDZ256rmbk = 16564 + + VPERMT2PDZ256rmbkz = 16565 + + VPERMT2PDZ256rmk = 16566 + + VPERMT2PDZ256rmkz = 16567 + + VPERMT2PDZ256rr = 16568 + + VPERMT2PDZ256rrk = 16569 + + VPERMT2PDZ256rrkz = 16570 + + VPERMT2PDZrm = 16571 + + VPERMT2PDZrmb = 16572 + + VPERMT2PDZrmbk = 16573 + + VPERMT2PDZrmbkz = 16574 + + VPERMT2PDZrmk = 16575 + + VPERMT2PDZrmkz = 16576 + + VPERMT2PDZrr = 16577 + + VPERMT2PDZrrk = 16578 + + VPERMT2PDZrrkz = 16579 + + VPERMT2PSZ128rm = 16580 + + VPERMT2PSZ128rmb = 16581 + + VPERMT2PSZ128rmbk = 16582 + + VPERMT2PSZ128rmbkz = 16583 + + VPERMT2PSZ128rmk = 16584 + + VPERMT2PSZ128rmkz = 16585 + + VPERMT2PSZ128rr = 16586 + + VPERMT2PSZ128rrk = 16587 + + VPERMT2PSZ128rrkz = 16588 + + VPERMT2PSZ256rm = 16589 + + VPERMT2PSZ256rmb = 16590 + + VPERMT2PSZ256rmbk = 16591 + + VPERMT2PSZ256rmbkz = 16592 + + VPERMT2PSZ256rmk = 16593 + + VPERMT2PSZ256rmkz = 16594 + + VPERMT2PSZ256rr = 16595 + + VPERMT2PSZ256rrk = 16596 + + VPERMT2PSZ256rrkz = 16597 + + VPERMT2PSZrm = 16598 + + VPERMT2PSZrmb = 16599 + + VPERMT2PSZrmbk = 16600 + + VPERMT2PSZrmbkz = 16601 + + VPERMT2PSZrmk = 16602 + + VPERMT2PSZrmkz = 16603 + + VPERMT2PSZrr = 16604 + + VPERMT2PSZrrk = 16605 + + VPERMT2PSZrrkz = 16606 + + VPERMT2QZ128rm = 16607 + + VPERMT2QZ128rmb = 16608 + + VPERMT2QZ128rmbk = 16609 + + VPERMT2QZ128rmbkz = 16610 + + VPERMT2QZ128rmk = 16611 + + VPERMT2QZ128rmkz = 16612 + + VPERMT2QZ128rr = 16613 + + VPERMT2QZ128rrk = 16614 + + VPERMT2QZ128rrkz = 16615 + + VPERMT2QZ256rm = 16616 + + VPERMT2QZ256rmb = 16617 + + VPERMT2QZ256rmbk = 16618 + + VPERMT2QZ256rmbkz = 16619 + + VPERMT2QZ256rmk = 16620 + + VPERMT2QZ256rmkz = 16621 + + VPERMT2QZ256rr = 16622 + + VPERMT2QZ256rrk = 16623 + + VPERMT2QZ256rrkz = 16624 + + VPERMT2QZrm = 16625 + + VPERMT2QZrmb = 16626 + + VPERMT2QZrmbk = 16627 + + VPERMT2QZrmbkz = 16628 + + VPERMT2QZrmk = 16629 + + VPERMT2QZrmkz = 16630 + + VPERMT2QZrr = 16631 + + VPERMT2QZrrk = 16632 + + VPERMT2QZrrkz = 16633 + + VPERMT2WZ128rm = 16634 + + VPERMT2WZ128rmk = 16635 + + VPERMT2WZ128rmkz = 16636 + + VPERMT2WZ128rr = 16637 + + VPERMT2WZ128rrk = 16638 + + VPERMT2WZ128rrkz = 16639 + + VPERMT2WZ256rm = 16640 + + VPERMT2WZ256rmk = 16641 + + VPERMT2WZ256rmkz = 16642 + + VPERMT2WZ256rr = 16643 + + VPERMT2WZ256rrk = 16644 + + VPERMT2WZ256rrkz = 16645 + + VPERMT2WZrm = 16646 + + VPERMT2WZrmk = 16647 + + VPERMT2WZrmkz = 16648 + + VPERMT2WZrr = 16649 + + VPERMT2WZrrk = 16650 + + VPERMT2WZrrkz = 16651 + + VPERMWZ128rm = 16652 + + VPERMWZ128rmk = 16653 + + VPERMWZ128rmkz = 16654 + + VPERMWZ128rr = 16655 + + VPERMWZ128rrk = 16656 + + VPERMWZ128rrkz = 16657 + + VPERMWZ256rm = 16658 + + VPERMWZ256rmk = 16659 + + VPERMWZ256rmkz = 16660 + + VPERMWZ256rr = 16661 + + VPERMWZ256rrk = 16662 + + VPERMWZ256rrkz = 16663 + + VPERMWZrm = 16664 + + VPERMWZrmk = 16665 + + VPERMWZrmkz = 16666 + + VPERMWZrr = 16667 + + VPERMWZrrk = 16668 + + VPERMWZrrkz = 16669 + + VPEXPANDBZ128rm = 16670 + + VPEXPANDBZ128rmk = 16671 + + VPEXPANDBZ128rmkz = 16672 + + VPEXPANDBZ128rr = 16673 + + VPEXPANDBZ128rrk = 16674 + + VPEXPANDBZ128rrkz = 16675 + + VPEXPANDBZ256rm = 16676 + + VPEXPANDBZ256rmk = 16677 + + VPEXPANDBZ256rmkz = 16678 + + VPEXPANDBZ256rr = 16679 + + VPEXPANDBZ256rrk = 16680 + + VPEXPANDBZ256rrkz = 16681 + + VPEXPANDBZrm = 16682 + + VPEXPANDBZrmk = 16683 + + VPEXPANDBZrmkz = 16684 + + VPEXPANDBZrr = 16685 + + VPEXPANDBZrrk = 16686 + + VPEXPANDBZrrkz = 16687 + + VPEXPANDDZ128rm = 16688 + + VPEXPANDDZ128rmk = 16689 + + VPEXPANDDZ128rmkz = 16690 + + VPEXPANDDZ128rr = 16691 + + VPEXPANDDZ128rrk = 16692 + + VPEXPANDDZ128rrkz = 16693 + + VPEXPANDDZ256rm = 16694 + + VPEXPANDDZ256rmk = 16695 + + VPEXPANDDZ256rmkz = 16696 + + VPEXPANDDZ256rr = 16697 + + VPEXPANDDZ256rrk = 16698 + + VPEXPANDDZ256rrkz = 16699 + + VPEXPANDDZrm = 16700 + + VPEXPANDDZrmk = 16701 + + VPEXPANDDZrmkz = 16702 + + VPEXPANDDZrr = 16703 + + VPEXPANDDZrrk = 16704 + + VPEXPANDDZrrkz = 16705 + + VPEXPANDQZ128rm = 16706 + + VPEXPANDQZ128rmk = 16707 + + VPEXPANDQZ128rmkz = 16708 + + VPEXPANDQZ128rr = 16709 + + VPEXPANDQZ128rrk = 16710 + + VPEXPANDQZ128rrkz = 16711 + + VPEXPANDQZ256rm = 16712 + + VPEXPANDQZ256rmk = 16713 + + VPEXPANDQZ256rmkz = 16714 + + VPEXPANDQZ256rr = 16715 + + VPEXPANDQZ256rrk = 16716 + + VPEXPANDQZ256rrkz = 16717 + + VPEXPANDQZrm = 16718 + + VPEXPANDQZrmk = 16719 + + VPEXPANDQZrmkz = 16720 + + VPEXPANDQZrr = 16721 + + VPEXPANDQZrrk = 16722 + + VPEXPANDQZrrkz = 16723 + + VPEXPANDWZ128rm = 16724 + + VPEXPANDWZ128rmk = 16725 + + VPEXPANDWZ128rmkz = 16726 + + VPEXPANDWZ128rr = 16727 + + VPEXPANDWZ128rrk = 16728 + + VPEXPANDWZ128rrkz = 16729 + + VPEXPANDWZ256rm = 16730 + + VPEXPANDWZ256rmk = 16731 + + VPEXPANDWZ256rmkz = 16732 + + VPEXPANDWZ256rr = 16733 + + VPEXPANDWZ256rrk = 16734 + + VPEXPANDWZ256rrkz = 16735 + + VPEXPANDWZrm = 16736 + + VPEXPANDWZrmk = 16737 + + VPEXPANDWZrmkz = 16738 + + VPEXPANDWZrr = 16739 + + VPEXPANDWZrrk = 16740 + + VPEXPANDWZrrkz = 16741 + + VPEXTRBZmri = 16742 + + VPEXTRBZrri = 16743 + + VPEXTRBmri = 16744 + + VPEXTRBrri = 16745 + + VPEXTRDZmri = 16746 + + VPEXTRDZrri = 16747 + + VPEXTRDmri = 16748 + + VPEXTRDrri = 16749 + + VPEXTRQZmri = 16750 + + VPEXTRQZrri = 16751 + + VPEXTRQmri = 16752 + + VPEXTRQrri = 16753 + + VPEXTRWZmri = 16754 + + VPEXTRWZrri = 16755 + + VPEXTRWZrri_REV = 16756 + + VPEXTRWmri = 16757 + + VPEXTRWrri = 16758 + + VPEXTRWrri_REV = 16759 + + VPGATHERDDYrm = 16760 + + VPGATHERDDZ128rm = 16761 + + VPGATHERDDZ256rm = 16762 + + VPGATHERDDZrm = 16763 + + VPGATHERDDrm = 16764 + + VPGATHERDQYrm = 16765 + + VPGATHERDQZ128rm = 16766 + + VPGATHERDQZ256rm = 16767 + + VPGATHERDQZrm = 16768 + + VPGATHERDQrm = 16769 + + VPGATHERQDYrm = 16770 + + VPGATHERQDZ128rm = 16771 + + VPGATHERQDZ256rm = 16772 + + VPGATHERQDZrm = 16773 + + VPGATHERQDrm = 16774 + + VPGATHERQQYrm = 16775 + + VPGATHERQQZ128rm = 16776 + + VPGATHERQQZ256rm = 16777 + + VPGATHERQQZrm = 16778 + + VPGATHERQQrm = 16779 + + VPHADDBDrm = 16780 + + VPHADDBDrr = 16781 + + VPHADDBQrm = 16782 + + VPHADDBQrr = 16783 + + VPHADDBWrm = 16784 + + VPHADDBWrr = 16785 + + VPHADDDQrm = 16786 + + VPHADDDQrr = 16787 + + VPHADDDYrm = 16788 + + VPHADDDYrr = 16789 + + VPHADDDrm = 16790 + + VPHADDDrr = 16791 + + VPHADDSWYrm = 16792 + + VPHADDSWYrr = 16793 + + VPHADDSWrm = 16794 + + VPHADDSWrr = 16795 + + VPHADDUBDrm = 16796 + + VPHADDUBDrr = 16797 + + VPHADDUBQrm = 16798 + + VPHADDUBQrr = 16799 + + VPHADDUBWrm = 16800 + + VPHADDUBWrr = 16801 + + VPHADDUDQrm = 16802 + + VPHADDUDQrr = 16803 + + VPHADDUWDrm = 16804 + + VPHADDUWDrr = 16805 + + VPHADDUWQrm = 16806 + + VPHADDUWQrr = 16807 + + VPHADDWDrm = 16808 + + VPHADDWDrr = 16809 + + VPHADDWQrm = 16810 + + VPHADDWQrr = 16811 + + VPHADDWYrm = 16812 + + VPHADDWYrr = 16813 + + VPHADDWrm = 16814 + + VPHADDWrr = 16815 + + VPHMINPOSUWrm = 16816 + + VPHMINPOSUWrr = 16817 + + VPHSUBBWrm = 16818 + + VPHSUBBWrr = 16819 + + VPHSUBDQrm = 16820 + + VPHSUBDQrr = 16821 + + VPHSUBDYrm = 16822 + + VPHSUBDYrr = 16823 + + VPHSUBDrm = 16824 + + VPHSUBDrr = 16825 + + VPHSUBSWYrm = 16826 + + VPHSUBSWYrr = 16827 + + VPHSUBSWrm = 16828 + + VPHSUBSWrr = 16829 + + VPHSUBWDrm = 16830 + + VPHSUBWDrr = 16831 + + VPHSUBWYrm = 16832 + + VPHSUBWYrr = 16833 + + VPHSUBWrm = 16834 + + VPHSUBWrr = 16835 + + VPINSRBZrmi = 16836 + + VPINSRBZrri = 16837 + + VPINSRBrmi = 16838 + + VPINSRBrri = 16839 + + VPINSRDZrmi = 16840 + + VPINSRDZrri = 16841 + + VPINSRDrmi = 16842 + + VPINSRDrri = 16843 + + VPINSRQZrmi = 16844 + + VPINSRQZrri = 16845 + + VPINSRQrmi = 16846 + + VPINSRQrri = 16847 + + VPINSRWZrmi = 16848 + + VPINSRWZrri = 16849 + + VPINSRWrmi = 16850 + + VPINSRWrri = 16851 + + VPLZCNTDZ128rm = 16852 + + VPLZCNTDZ128rmb = 16853 + + VPLZCNTDZ128rmbk = 16854 + + VPLZCNTDZ128rmbkz = 16855 + + VPLZCNTDZ128rmk = 16856 + + VPLZCNTDZ128rmkz = 16857 + + VPLZCNTDZ128rr = 16858 + + VPLZCNTDZ128rrk = 16859 + + VPLZCNTDZ128rrkz = 16860 + + VPLZCNTDZ256rm = 16861 + + VPLZCNTDZ256rmb = 16862 + + VPLZCNTDZ256rmbk = 16863 + + VPLZCNTDZ256rmbkz = 16864 + + VPLZCNTDZ256rmk = 16865 + + VPLZCNTDZ256rmkz = 16866 + + VPLZCNTDZ256rr = 16867 + + VPLZCNTDZ256rrk = 16868 + + VPLZCNTDZ256rrkz = 16869 + + VPLZCNTDZrm = 16870 + + VPLZCNTDZrmb = 16871 + + VPLZCNTDZrmbk = 16872 + + VPLZCNTDZrmbkz = 16873 + + VPLZCNTDZrmk = 16874 + + VPLZCNTDZrmkz = 16875 + + VPLZCNTDZrr = 16876 + + VPLZCNTDZrrk = 16877 + + VPLZCNTDZrrkz = 16878 + + VPLZCNTQZ128rm = 16879 + + VPLZCNTQZ128rmb = 16880 + + VPLZCNTQZ128rmbk = 16881 + + VPLZCNTQZ128rmbkz = 16882 + + VPLZCNTQZ128rmk = 16883 + + VPLZCNTQZ128rmkz = 16884 + + VPLZCNTQZ128rr = 16885 + + VPLZCNTQZ128rrk = 16886 + + VPLZCNTQZ128rrkz = 16887 + + VPLZCNTQZ256rm = 16888 + + VPLZCNTQZ256rmb = 16889 + + VPLZCNTQZ256rmbk = 16890 + + VPLZCNTQZ256rmbkz = 16891 + + VPLZCNTQZ256rmk = 16892 + + VPLZCNTQZ256rmkz = 16893 + + VPLZCNTQZ256rr = 16894 + + VPLZCNTQZ256rrk = 16895 + + VPLZCNTQZ256rrkz = 16896 + + VPLZCNTQZrm = 16897 + + VPLZCNTQZrmb = 16898 + + VPLZCNTQZrmbk = 16899 + + VPLZCNTQZrmbkz = 16900 + + VPLZCNTQZrmk = 16901 + + VPLZCNTQZrmkz = 16902 + + VPLZCNTQZrr = 16903 + + VPLZCNTQZrrk = 16904 + + VPLZCNTQZrrkz = 16905 + + VPMACSDDrm = 16906 + + VPMACSDDrr = 16907 + + VPMACSDQHrm = 16908 + + VPMACSDQHrr = 16909 + + VPMACSDQLrm = 16910 + + VPMACSDQLrr = 16911 + + VPMACSSDDrm = 16912 + + VPMACSSDDrr = 16913 + + VPMACSSDQHrm = 16914 + + VPMACSSDQHrr = 16915 + + VPMACSSDQLrm = 16916 + + VPMACSSDQLrr = 16917 + + VPMACSSWDrm = 16918 + + VPMACSSWDrr = 16919 + + VPMACSSWWrm = 16920 + + VPMACSSWWrr = 16921 + + VPMACSWDrm = 16922 + + VPMACSWDrr = 16923 + + VPMACSWWrm = 16924 + + VPMACSWWrr = 16925 + + VPMADCSSWDrm = 16926 + + VPMADCSSWDrr = 16927 + + VPMADCSWDrm = 16928 + + VPMADCSWDrr = 16929 + + VPMADD52HUQYrm = 16930 + + VPMADD52HUQYrr = 16931 + + VPMADD52HUQZ128m = 16932 + + VPMADD52HUQZ128mb = 16933 + + VPMADD52HUQZ128mbk = 16934 + + VPMADD52HUQZ128mbkz = 16935 + + VPMADD52HUQZ128mk = 16936 + + VPMADD52HUQZ128mkz = 16937 + + VPMADD52HUQZ128r = 16938 + + VPMADD52HUQZ128rk = 16939 + + VPMADD52HUQZ128rkz = 16940 + + VPMADD52HUQZ256m = 16941 + + VPMADD52HUQZ256mb = 16942 + + VPMADD52HUQZ256mbk = 16943 + + VPMADD52HUQZ256mbkz = 16944 + + VPMADD52HUQZ256mk = 16945 + + VPMADD52HUQZ256mkz = 16946 + + VPMADD52HUQZ256r = 16947 + + VPMADD52HUQZ256rk = 16948 + + VPMADD52HUQZ256rkz = 16949 + + VPMADD52HUQZm = 16950 + + VPMADD52HUQZmb = 16951 + + VPMADD52HUQZmbk = 16952 + + VPMADD52HUQZmbkz = 16953 + + VPMADD52HUQZmk = 16954 + + VPMADD52HUQZmkz = 16955 + + VPMADD52HUQZr = 16956 + + VPMADD52HUQZrk = 16957 + + VPMADD52HUQZrkz = 16958 + + VPMADD52HUQrm = 16959 + + VPMADD52HUQrr = 16960 + + VPMADD52LUQYrm = 16961 + + VPMADD52LUQYrr = 16962 + + VPMADD52LUQZ128m = 16963 + + VPMADD52LUQZ128mb = 16964 + + VPMADD52LUQZ128mbk = 16965 + + VPMADD52LUQZ128mbkz = 16966 + + VPMADD52LUQZ128mk = 16967 + + VPMADD52LUQZ128mkz = 16968 + + VPMADD52LUQZ128r = 16969 + + VPMADD52LUQZ128rk = 16970 + + VPMADD52LUQZ128rkz = 16971 + + VPMADD52LUQZ256m = 16972 + + VPMADD52LUQZ256mb = 16973 + + VPMADD52LUQZ256mbk = 16974 + + VPMADD52LUQZ256mbkz = 16975 + + VPMADD52LUQZ256mk = 16976 + + VPMADD52LUQZ256mkz = 16977 + + VPMADD52LUQZ256r = 16978 + + VPMADD52LUQZ256rk = 16979 + + VPMADD52LUQZ256rkz = 16980 + + VPMADD52LUQZm = 16981 + + VPMADD52LUQZmb = 16982 + + VPMADD52LUQZmbk = 16983 + + VPMADD52LUQZmbkz = 16984 + + VPMADD52LUQZmk = 16985 + + VPMADD52LUQZmkz = 16986 + + VPMADD52LUQZr = 16987 + + VPMADD52LUQZrk = 16988 + + VPMADD52LUQZrkz = 16989 + + VPMADD52LUQrm = 16990 + + VPMADD52LUQrr = 16991 + + VPMADDUBSWYrm = 16992 + + VPMADDUBSWYrr = 16993 + + VPMADDUBSWZ128rm = 16994 + + VPMADDUBSWZ128rmk = 16995 + + VPMADDUBSWZ128rmkz = 16996 + + VPMADDUBSWZ128rr = 16997 + + VPMADDUBSWZ128rrk = 16998 + + VPMADDUBSWZ128rrkz = 16999 + + VPMADDUBSWZ256rm = 17000 + + VPMADDUBSWZ256rmk = 17001 + + VPMADDUBSWZ256rmkz = 17002 + + VPMADDUBSWZ256rr = 17003 + + VPMADDUBSWZ256rrk = 17004 + + VPMADDUBSWZ256rrkz = 17005 + + VPMADDUBSWZrm = 17006 + + VPMADDUBSWZrmk = 17007 + + VPMADDUBSWZrmkz = 17008 + + VPMADDUBSWZrr = 17009 + + VPMADDUBSWZrrk = 17010 + + VPMADDUBSWZrrkz = 17011 + + VPMADDUBSWrm = 17012 + + VPMADDUBSWrr = 17013 + + VPMADDWDYrm = 17014 + + VPMADDWDYrr = 17015 + + VPMADDWDZ128rm = 17016 + + VPMADDWDZ128rmk = 17017 + + VPMADDWDZ128rmkz = 17018 + + VPMADDWDZ128rr = 17019 + + VPMADDWDZ128rrk = 17020 + + VPMADDWDZ128rrkz = 17021 + + VPMADDWDZ256rm = 17022 + + VPMADDWDZ256rmk = 17023 + + VPMADDWDZ256rmkz = 17024 + + VPMADDWDZ256rr = 17025 + + VPMADDWDZ256rrk = 17026 + + VPMADDWDZ256rrkz = 17027 + + VPMADDWDZrm = 17028 + + VPMADDWDZrmk = 17029 + + VPMADDWDZrmkz = 17030 + + VPMADDWDZrr = 17031 + + VPMADDWDZrrk = 17032 + + VPMADDWDZrrkz = 17033 + + VPMADDWDrm = 17034 + + VPMADDWDrr = 17035 + + VPMASKMOVDYmr = 17036 + + VPMASKMOVDYrm = 17037 + + VPMASKMOVDmr = 17038 + + VPMASKMOVDrm = 17039 + + VPMASKMOVQYmr = 17040 + + VPMASKMOVQYrm = 17041 + + VPMASKMOVQmr = 17042 + + VPMASKMOVQrm = 17043 + + VPMAXSBYrm = 17044 + + VPMAXSBYrr = 17045 + + VPMAXSBZ128rm = 17046 + + VPMAXSBZ128rmk = 17047 + + VPMAXSBZ128rmkz = 17048 + + VPMAXSBZ128rr = 17049 + + VPMAXSBZ128rrk = 17050 + + VPMAXSBZ128rrkz = 17051 + + VPMAXSBZ256rm = 17052 + + VPMAXSBZ256rmk = 17053 + + VPMAXSBZ256rmkz = 17054 + + VPMAXSBZ256rr = 17055 + + VPMAXSBZ256rrk = 17056 + + VPMAXSBZ256rrkz = 17057 + + VPMAXSBZrm = 17058 + + VPMAXSBZrmk = 17059 + + VPMAXSBZrmkz = 17060 + + VPMAXSBZrr = 17061 + + VPMAXSBZrrk = 17062 + + VPMAXSBZrrkz = 17063 + + VPMAXSBrm = 17064 + + VPMAXSBrr = 17065 + + VPMAXSDYrm = 17066 + + VPMAXSDYrr = 17067 + + VPMAXSDZ128rm = 17068 + + VPMAXSDZ128rmb = 17069 + + VPMAXSDZ128rmbk = 17070 + + VPMAXSDZ128rmbkz = 17071 + + VPMAXSDZ128rmk = 17072 + + VPMAXSDZ128rmkz = 17073 + + VPMAXSDZ128rr = 17074 + + VPMAXSDZ128rrk = 17075 + + VPMAXSDZ128rrkz = 17076 + + VPMAXSDZ256rm = 17077 + + VPMAXSDZ256rmb = 17078 + + VPMAXSDZ256rmbk = 17079 + + VPMAXSDZ256rmbkz = 17080 + + VPMAXSDZ256rmk = 17081 + + VPMAXSDZ256rmkz = 17082 + + VPMAXSDZ256rr = 17083 + + VPMAXSDZ256rrk = 17084 + + VPMAXSDZ256rrkz = 17085 + + VPMAXSDZrm = 17086 + + VPMAXSDZrmb = 17087 + + VPMAXSDZrmbk = 17088 + + VPMAXSDZrmbkz = 17089 + + VPMAXSDZrmk = 17090 + + VPMAXSDZrmkz = 17091 + + VPMAXSDZrr = 17092 + + VPMAXSDZrrk = 17093 + + VPMAXSDZrrkz = 17094 + + VPMAXSDrm = 17095 + + VPMAXSDrr = 17096 + + VPMAXSQZ128rm = 17097 + + VPMAXSQZ128rmb = 17098 + + VPMAXSQZ128rmbk = 17099 + + VPMAXSQZ128rmbkz = 17100 + + VPMAXSQZ128rmk = 17101 + + VPMAXSQZ128rmkz = 17102 + + VPMAXSQZ128rr = 17103 + + VPMAXSQZ128rrk = 17104 + + VPMAXSQZ128rrkz = 17105 + + VPMAXSQZ256rm = 17106 + + VPMAXSQZ256rmb = 17107 + + VPMAXSQZ256rmbk = 17108 + + VPMAXSQZ256rmbkz = 17109 + + VPMAXSQZ256rmk = 17110 + + VPMAXSQZ256rmkz = 17111 + + VPMAXSQZ256rr = 17112 + + VPMAXSQZ256rrk = 17113 + + VPMAXSQZ256rrkz = 17114 + + VPMAXSQZrm = 17115 + + VPMAXSQZrmb = 17116 + + VPMAXSQZrmbk = 17117 + + VPMAXSQZrmbkz = 17118 + + VPMAXSQZrmk = 17119 + + VPMAXSQZrmkz = 17120 + + VPMAXSQZrr = 17121 + + VPMAXSQZrrk = 17122 + + VPMAXSQZrrkz = 17123 + + VPMAXSWYrm = 17124 + + VPMAXSWYrr = 17125 + + VPMAXSWZ128rm = 17126 + + VPMAXSWZ128rmk = 17127 + + VPMAXSWZ128rmkz = 17128 + + VPMAXSWZ128rr = 17129 + + VPMAXSWZ128rrk = 17130 + + VPMAXSWZ128rrkz = 17131 + + VPMAXSWZ256rm = 17132 + + VPMAXSWZ256rmk = 17133 + + VPMAXSWZ256rmkz = 17134 + + VPMAXSWZ256rr = 17135 + + VPMAXSWZ256rrk = 17136 + + VPMAXSWZ256rrkz = 17137 + + VPMAXSWZrm = 17138 + + VPMAXSWZrmk = 17139 + + VPMAXSWZrmkz = 17140 + + VPMAXSWZrr = 17141 + + VPMAXSWZrrk = 17142 + + VPMAXSWZrrkz = 17143 + + VPMAXSWrm = 17144 + + VPMAXSWrr = 17145 + + VPMAXUBYrm = 17146 + + VPMAXUBYrr = 17147 + + VPMAXUBZ128rm = 17148 + + VPMAXUBZ128rmk = 17149 + + VPMAXUBZ128rmkz = 17150 + + VPMAXUBZ128rr = 17151 + + VPMAXUBZ128rrk = 17152 + + VPMAXUBZ128rrkz = 17153 + + VPMAXUBZ256rm = 17154 + + VPMAXUBZ256rmk = 17155 + + VPMAXUBZ256rmkz = 17156 + + VPMAXUBZ256rr = 17157 + + VPMAXUBZ256rrk = 17158 + + VPMAXUBZ256rrkz = 17159 + + VPMAXUBZrm = 17160 + + VPMAXUBZrmk = 17161 + + VPMAXUBZrmkz = 17162 + + VPMAXUBZrr = 17163 + + VPMAXUBZrrk = 17164 + + VPMAXUBZrrkz = 17165 + + VPMAXUBrm = 17166 + + VPMAXUBrr = 17167 + + VPMAXUDYrm = 17168 + + VPMAXUDYrr = 17169 + + VPMAXUDZ128rm = 17170 + + VPMAXUDZ128rmb = 17171 + + VPMAXUDZ128rmbk = 17172 + + VPMAXUDZ128rmbkz = 17173 + + VPMAXUDZ128rmk = 17174 + + VPMAXUDZ128rmkz = 17175 + + VPMAXUDZ128rr = 17176 + + VPMAXUDZ128rrk = 17177 + + VPMAXUDZ128rrkz = 17178 + + VPMAXUDZ256rm = 17179 + + VPMAXUDZ256rmb = 17180 + + VPMAXUDZ256rmbk = 17181 + + VPMAXUDZ256rmbkz = 17182 + + VPMAXUDZ256rmk = 17183 + + VPMAXUDZ256rmkz = 17184 + + VPMAXUDZ256rr = 17185 + + VPMAXUDZ256rrk = 17186 + + VPMAXUDZ256rrkz = 17187 + + VPMAXUDZrm = 17188 + + VPMAXUDZrmb = 17189 + + VPMAXUDZrmbk = 17190 + + VPMAXUDZrmbkz = 17191 + + VPMAXUDZrmk = 17192 + + VPMAXUDZrmkz = 17193 + + VPMAXUDZrr = 17194 + + VPMAXUDZrrk = 17195 + + VPMAXUDZrrkz = 17196 + + VPMAXUDrm = 17197 + + VPMAXUDrr = 17198 + + VPMAXUQZ128rm = 17199 + + VPMAXUQZ128rmb = 17200 + + VPMAXUQZ128rmbk = 17201 + + VPMAXUQZ128rmbkz = 17202 + + VPMAXUQZ128rmk = 17203 + + VPMAXUQZ128rmkz = 17204 + + VPMAXUQZ128rr = 17205 + + VPMAXUQZ128rrk = 17206 + + VPMAXUQZ128rrkz = 17207 + + VPMAXUQZ256rm = 17208 + + VPMAXUQZ256rmb = 17209 + + VPMAXUQZ256rmbk = 17210 + + VPMAXUQZ256rmbkz = 17211 + + VPMAXUQZ256rmk = 17212 + + VPMAXUQZ256rmkz = 17213 + + VPMAXUQZ256rr = 17214 + + VPMAXUQZ256rrk = 17215 + + VPMAXUQZ256rrkz = 17216 + + VPMAXUQZrm = 17217 + + VPMAXUQZrmb = 17218 + + VPMAXUQZrmbk = 17219 + + VPMAXUQZrmbkz = 17220 + + VPMAXUQZrmk = 17221 + + VPMAXUQZrmkz = 17222 + + VPMAXUQZrr = 17223 + + VPMAXUQZrrk = 17224 + + VPMAXUQZrrkz = 17225 + + VPMAXUWYrm = 17226 + + VPMAXUWYrr = 17227 + + VPMAXUWZ128rm = 17228 + + VPMAXUWZ128rmk = 17229 + + VPMAXUWZ128rmkz = 17230 + + VPMAXUWZ128rr = 17231 + + VPMAXUWZ128rrk = 17232 + + VPMAXUWZ128rrkz = 17233 + + VPMAXUWZ256rm = 17234 + + VPMAXUWZ256rmk = 17235 + + VPMAXUWZ256rmkz = 17236 + + VPMAXUWZ256rr = 17237 + + VPMAXUWZ256rrk = 17238 + + VPMAXUWZ256rrkz = 17239 + + VPMAXUWZrm = 17240 + + VPMAXUWZrmk = 17241 + + VPMAXUWZrmkz = 17242 + + VPMAXUWZrr = 17243 + + VPMAXUWZrrk = 17244 + + VPMAXUWZrrkz = 17245 + + VPMAXUWrm = 17246 + + VPMAXUWrr = 17247 + + VPMINSBYrm = 17248 + + VPMINSBYrr = 17249 + + VPMINSBZ128rm = 17250 + + VPMINSBZ128rmk = 17251 + + VPMINSBZ128rmkz = 17252 + + VPMINSBZ128rr = 17253 + + VPMINSBZ128rrk = 17254 + + VPMINSBZ128rrkz = 17255 + + VPMINSBZ256rm = 17256 + + VPMINSBZ256rmk = 17257 + + VPMINSBZ256rmkz = 17258 + + VPMINSBZ256rr = 17259 + + VPMINSBZ256rrk = 17260 + + VPMINSBZ256rrkz = 17261 + + VPMINSBZrm = 17262 + + VPMINSBZrmk = 17263 + + VPMINSBZrmkz = 17264 + + VPMINSBZrr = 17265 + + VPMINSBZrrk = 17266 + + VPMINSBZrrkz = 17267 + + VPMINSBrm = 17268 + + VPMINSBrr = 17269 + + VPMINSDYrm = 17270 + + VPMINSDYrr = 17271 + + VPMINSDZ128rm = 17272 + + VPMINSDZ128rmb = 17273 + + VPMINSDZ128rmbk = 17274 + + VPMINSDZ128rmbkz = 17275 + + VPMINSDZ128rmk = 17276 + + VPMINSDZ128rmkz = 17277 + + VPMINSDZ128rr = 17278 + + VPMINSDZ128rrk = 17279 + + VPMINSDZ128rrkz = 17280 + + VPMINSDZ256rm = 17281 + + VPMINSDZ256rmb = 17282 + + VPMINSDZ256rmbk = 17283 + + VPMINSDZ256rmbkz = 17284 + + VPMINSDZ256rmk = 17285 + + VPMINSDZ256rmkz = 17286 + + VPMINSDZ256rr = 17287 + + VPMINSDZ256rrk = 17288 + + VPMINSDZ256rrkz = 17289 + + VPMINSDZrm = 17290 + + VPMINSDZrmb = 17291 + + VPMINSDZrmbk = 17292 + + VPMINSDZrmbkz = 17293 + + VPMINSDZrmk = 17294 + + VPMINSDZrmkz = 17295 + + VPMINSDZrr = 17296 + + VPMINSDZrrk = 17297 + + VPMINSDZrrkz = 17298 + + VPMINSDrm = 17299 + + VPMINSDrr = 17300 + + VPMINSQZ128rm = 17301 + + VPMINSQZ128rmb = 17302 + + VPMINSQZ128rmbk = 17303 + + VPMINSQZ128rmbkz = 17304 + + VPMINSQZ128rmk = 17305 + + VPMINSQZ128rmkz = 17306 + + VPMINSQZ128rr = 17307 + + VPMINSQZ128rrk = 17308 + + VPMINSQZ128rrkz = 17309 + + VPMINSQZ256rm = 17310 + + VPMINSQZ256rmb = 17311 + + VPMINSQZ256rmbk = 17312 + + VPMINSQZ256rmbkz = 17313 + + VPMINSQZ256rmk = 17314 + + VPMINSQZ256rmkz = 17315 + + VPMINSQZ256rr = 17316 + + VPMINSQZ256rrk = 17317 + + VPMINSQZ256rrkz = 17318 + + VPMINSQZrm = 17319 + + VPMINSQZrmb = 17320 + + VPMINSQZrmbk = 17321 + + VPMINSQZrmbkz = 17322 + + VPMINSQZrmk = 17323 + + VPMINSQZrmkz = 17324 + + VPMINSQZrr = 17325 + + VPMINSQZrrk = 17326 + + VPMINSQZrrkz = 17327 + + VPMINSWYrm = 17328 + + VPMINSWYrr = 17329 + + VPMINSWZ128rm = 17330 + + VPMINSWZ128rmk = 17331 + + VPMINSWZ128rmkz = 17332 + + VPMINSWZ128rr = 17333 + + VPMINSWZ128rrk = 17334 + + VPMINSWZ128rrkz = 17335 + + VPMINSWZ256rm = 17336 + + VPMINSWZ256rmk = 17337 + + VPMINSWZ256rmkz = 17338 + + VPMINSWZ256rr = 17339 + + VPMINSWZ256rrk = 17340 + + VPMINSWZ256rrkz = 17341 + + VPMINSWZrm = 17342 + + VPMINSWZrmk = 17343 + + VPMINSWZrmkz = 17344 + + VPMINSWZrr = 17345 + + VPMINSWZrrk = 17346 + + VPMINSWZrrkz = 17347 + + VPMINSWrm = 17348 + + VPMINSWrr = 17349 + + VPMINUBYrm = 17350 + + VPMINUBYrr = 17351 + + VPMINUBZ128rm = 17352 + + VPMINUBZ128rmk = 17353 + + VPMINUBZ128rmkz = 17354 + + VPMINUBZ128rr = 17355 + + VPMINUBZ128rrk = 17356 + + VPMINUBZ128rrkz = 17357 + + VPMINUBZ256rm = 17358 + + VPMINUBZ256rmk = 17359 + + VPMINUBZ256rmkz = 17360 + + VPMINUBZ256rr = 17361 + + VPMINUBZ256rrk = 17362 + + VPMINUBZ256rrkz = 17363 + + VPMINUBZrm = 17364 + + VPMINUBZrmk = 17365 + + VPMINUBZrmkz = 17366 + + VPMINUBZrr = 17367 + + VPMINUBZrrk = 17368 + + VPMINUBZrrkz = 17369 + + VPMINUBrm = 17370 + + VPMINUBrr = 17371 + + VPMINUDYrm = 17372 + + VPMINUDYrr = 17373 + + VPMINUDZ128rm = 17374 + + VPMINUDZ128rmb = 17375 + + VPMINUDZ128rmbk = 17376 + + VPMINUDZ128rmbkz = 17377 + + VPMINUDZ128rmk = 17378 + + VPMINUDZ128rmkz = 17379 + + VPMINUDZ128rr = 17380 + + VPMINUDZ128rrk = 17381 + + VPMINUDZ128rrkz = 17382 + + VPMINUDZ256rm = 17383 + + VPMINUDZ256rmb = 17384 + + VPMINUDZ256rmbk = 17385 + + VPMINUDZ256rmbkz = 17386 + + VPMINUDZ256rmk = 17387 + + VPMINUDZ256rmkz = 17388 + + VPMINUDZ256rr = 17389 + + VPMINUDZ256rrk = 17390 + + VPMINUDZ256rrkz = 17391 + + VPMINUDZrm = 17392 + + VPMINUDZrmb = 17393 + + VPMINUDZrmbk = 17394 + + VPMINUDZrmbkz = 17395 + + VPMINUDZrmk = 17396 + + VPMINUDZrmkz = 17397 + + VPMINUDZrr = 17398 + + VPMINUDZrrk = 17399 + + VPMINUDZrrkz = 17400 + + VPMINUDrm = 17401 + + VPMINUDrr = 17402 + + VPMINUQZ128rm = 17403 + + VPMINUQZ128rmb = 17404 + + VPMINUQZ128rmbk = 17405 + + VPMINUQZ128rmbkz = 17406 + + VPMINUQZ128rmk = 17407 + + VPMINUQZ128rmkz = 17408 + + VPMINUQZ128rr = 17409 + + VPMINUQZ128rrk = 17410 + + VPMINUQZ128rrkz = 17411 + + VPMINUQZ256rm = 17412 + + VPMINUQZ256rmb = 17413 + + VPMINUQZ256rmbk = 17414 + + VPMINUQZ256rmbkz = 17415 + + VPMINUQZ256rmk = 17416 + + VPMINUQZ256rmkz = 17417 + + VPMINUQZ256rr = 17418 + + VPMINUQZ256rrk = 17419 + + VPMINUQZ256rrkz = 17420 + + VPMINUQZrm = 17421 + + VPMINUQZrmb = 17422 + + VPMINUQZrmbk = 17423 + + VPMINUQZrmbkz = 17424 + + VPMINUQZrmk = 17425 + + VPMINUQZrmkz = 17426 + + VPMINUQZrr = 17427 + + VPMINUQZrrk = 17428 + + VPMINUQZrrkz = 17429 + + VPMINUWYrm = 17430 + + VPMINUWYrr = 17431 + + VPMINUWZ128rm = 17432 + + VPMINUWZ128rmk = 17433 + + VPMINUWZ128rmkz = 17434 + + VPMINUWZ128rr = 17435 + + VPMINUWZ128rrk = 17436 + + VPMINUWZ128rrkz = 17437 + + VPMINUWZ256rm = 17438 + + VPMINUWZ256rmk = 17439 + + VPMINUWZ256rmkz = 17440 + + VPMINUWZ256rr = 17441 + + VPMINUWZ256rrk = 17442 + + VPMINUWZ256rrkz = 17443 + + VPMINUWZrm = 17444 + + VPMINUWZrmk = 17445 + + VPMINUWZrmkz = 17446 + + VPMINUWZrr = 17447 + + VPMINUWZrrk = 17448 + + VPMINUWZrrkz = 17449 + + VPMINUWrm = 17450 + + VPMINUWrr = 17451 + + VPMOVB2MZ128kr = 17452 + + VPMOVB2MZ256kr = 17453 + + VPMOVB2MZkr = 17454 + + VPMOVD2MZ128kr = 17455 + + VPMOVD2MZ256kr = 17456 + + VPMOVD2MZkr = 17457 + + VPMOVDBZ128mr = 17458 + + VPMOVDBZ128mrk = 17459 + + VPMOVDBZ128rr = 17460 + + VPMOVDBZ128rrk = 17461 + + VPMOVDBZ128rrkz = 17462 + + VPMOVDBZ256mr = 17463 + + VPMOVDBZ256mrk = 17464 + + VPMOVDBZ256rr = 17465 + + VPMOVDBZ256rrk = 17466 + + VPMOVDBZ256rrkz = 17467 + + VPMOVDBZmr = 17468 + + VPMOVDBZmrk = 17469 + + VPMOVDBZrr = 17470 + + VPMOVDBZrrk = 17471 + + VPMOVDBZrrkz = 17472 + + VPMOVDWZ128mr = 17473 + + VPMOVDWZ128mrk = 17474 + + VPMOVDWZ128rr = 17475 + + VPMOVDWZ128rrk = 17476 + + VPMOVDWZ128rrkz = 17477 + + VPMOVDWZ256mr = 17478 + + VPMOVDWZ256mrk = 17479 + + VPMOVDWZ256rr = 17480 + + VPMOVDWZ256rrk = 17481 + + VPMOVDWZ256rrkz = 17482 + + VPMOVDWZmr = 17483 + + VPMOVDWZmrk = 17484 + + VPMOVDWZrr = 17485 + + VPMOVDWZrrk = 17486 + + VPMOVDWZrrkz = 17487 + + VPMOVM2BZ128rk = 17488 + + VPMOVM2BZ256rk = 17489 + + VPMOVM2BZrk = 17490 + + VPMOVM2DZ128rk = 17491 + + VPMOVM2DZ256rk = 17492 + + VPMOVM2DZrk = 17493 + + VPMOVM2QZ128rk = 17494 + + VPMOVM2QZ256rk = 17495 + + VPMOVM2QZrk = 17496 + + VPMOVM2WZ128rk = 17497 + + VPMOVM2WZ256rk = 17498 + + VPMOVM2WZrk = 17499 + + VPMOVMSKBYrr = 17500 + + VPMOVMSKBrr = 17501 + + VPMOVQ2MZ128kr = 17502 + + VPMOVQ2MZ256kr = 17503 + + VPMOVQ2MZkr = 17504 + + VPMOVQBZ128mr = 17505 + + VPMOVQBZ128mrk = 17506 + + VPMOVQBZ128rr = 17507 + + VPMOVQBZ128rrk = 17508 + + VPMOVQBZ128rrkz = 17509 + + VPMOVQBZ256mr = 17510 + + VPMOVQBZ256mrk = 17511 + + VPMOVQBZ256rr = 17512 + + VPMOVQBZ256rrk = 17513 + + VPMOVQBZ256rrkz = 17514 + + VPMOVQBZmr = 17515 + + VPMOVQBZmrk = 17516 + + VPMOVQBZrr = 17517 + + VPMOVQBZrrk = 17518 + + VPMOVQBZrrkz = 17519 + + VPMOVQDZ128mr = 17520 + + VPMOVQDZ128mrk = 17521 + + VPMOVQDZ128rr = 17522 + + VPMOVQDZ128rrk = 17523 + + VPMOVQDZ128rrkz = 17524 + + VPMOVQDZ256mr = 17525 + + VPMOVQDZ256mrk = 17526 + + VPMOVQDZ256rr = 17527 + + VPMOVQDZ256rrk = 17528 + + VPMOVQDZ256rrkz = 17529 + + VPMOVQDZmr = 17530 + + VPMOVQDZmrk = 17531 + + VPMOVQDZrr = 17532 + + VPMOVQDZrrk = 17533 + + VPMOVQDZrrkz = 17534 + + VPMOVQWZ128mr = 17535 + + VPMOVQWZ128mrk = 17536 + + VPMOVQWZ128rr = 17537 + + VPMOVQWZ128rrk = 17538 + + VPMOVQWZ128rrkz = 17539 + + VPMOVQWZ256mr = 17540 + + VPMOVQWZ256mrk = 17541 + + VPMOVQWZ256rr = 17542 + + VPMOVQWZ256rrk = 17543 + + VPMOVQWZ256rrkz = 17544 + + VPMOVQWZmr = 17545 + + VPMOVQWZmrk = 17546 + + VPMOVQWZrr = 17547 + + VPMOVQWZrrk = 17548 + + VPMOVQWZrrkz = 17549 + + VPMOVSDBZ128mr = 17550 + + VPMOVSDBZ128mrk = 17551 + + VPMOVSDBZ128rr = 17552 + + VPMOVSDBZ128rrk = 17553 + + VPMOVSDBZ128rrkz = 17554 + + VPMOVSDBZ256mr = 17555 + + VPMOVSDBZ256mrk = 17556 + + VPMOVSDBZ256rr = 17557 + + VPMOVSDBZ256rrk = 17558 + + VPMOVSDBZ256rrkz = 17559 + + VPMOVSDBZmr = 17560 + + VPMOVSDBZmrk = 17561 + + VPMOVSDBZrr = 17562 + + VPMOVSDBZrrk = 17563 + + VPMOVSDBZrrkz = 17564 + + VPMOVSDWZ128mr = 17565 + + VPMOVSDWZ128mrk = 17566 + + VPMOVSDWZ128rr = 17567 + + VPMOVSDWZ128rrk = 17568 + + VPMOVSDWZ128rrkz = 17569 + + VPMOVSDWZ256mr = 17570 + + VPMOVSDWZ256mrk = 17571 + + VPMOVSDWZ256rr = 17572 + + VPMOVSDWZ256rrk = 17573 + + VPMOVSDWZ256rrkz = 17574 + + VPMOVSDWZmr = 17575 + + VPMOVSDWZmrk = 17576 + + VPMOVSDWZrr = 17577 + + VPMOVSDWZrrk = 17578 + + VPMOVSDWZrrkz = 17579 + + VPMOVSQBZ128mr = 17580 + + VPMOVSQBZ128mrk = 17581 + + VPMOVSQBZ128rr = 17582 + + VPMOVSQBZ128rrk = 17583 + + VPMOVSQBZ128rrkz = 17584 + + VPMOVSQBZ256mr = 17585 + + VPMOVSQBZ256mrk = 17586 + + VPMOVSQBZ256rr = 17587 + + VPMOVSQBZ256rrk = 17588 + + VPMOVSQBZ256rrkz = 17589 + + VPMOVSQBZmr = 17590 + + VPMOVSQBZmrk = 17591 + + VPMOVSQBZrr = 17592 + + VPMOVSQBZrrk = 17593 + + VPMOVSQBZrrkz = 17594 + + VPMOVSQDZ128mr = 17595 + + VPMOVSQDZ128mrk = 17596 + + VPMOVSQDZ128rr = 17597 + + VPMOVSQDZ128rrk = 17598 + + VPMOVSQDZ128rrkz = 17599 + + VPMOVSQDZ256mr = 17600 + + VPMOVSQDZ256mrk = 17601 + + VPMOVSQDZ256rr = 17602 + + VPMOVSQDZ256rrk = 17603 + + VPMOVSQDZ256rrkz = 17604 + + VPMOVSQDZmr = 17605 + + VPMOVSQDZmrk = 17606 + + VPMOVSQDZrr = 17607 + + VPMOVSQDZrrk = 17608 + + VPMOVSQDZrrkz = 17609 + + VPMOVSQWZ128mr = 17610 + + VPMOVSQWZ128mrk = 17611 + + VPMOVSQWZ128rr = 17612 + + VPMOVSQWZ128rrk = 17613 + + VPMOVSQWZ128rrkz = 17614 + + VPMOVSQWZ256mr = 17615 + + VPMOVSQWZ256mrk = 17616 + + VPMOVSQWZ256rr = 17617 + + VPMOVSQWZ256rrk = 17618 + + VPMOVSQWZ256rrkz = 17619 + + VPMOVSQWZmr = 17620 + + VPMOVSQWZmrk = 17621 + + VPMOVSQWZrr = 17622 + + VPMOVSQWZrrk = 17623 + + VPMOVSQWZrrkz = 17624 + + VPMOVSWBZ128mr = 17625 + + VPMOVSWBZ128mrk = 17626 + + VPMOVSWBZ128rr = 17627 + + VPMOVSWBZ128rrk = 17628 + + VPMOVSWBZ128rrkz = 17629 + + VPMOVSWBZ256mr = 17630 + + VPMOVSWBZ256mrk = 17631 + + VPMOVSWBZ256rr = 17632 + + VPMOVSWBZ256rrk = 17633 + + VPMOVSWBZ256rrkz = 17634 + + VPMOVSWBZmr = 17635 + + VPMOVSWBZmrk = 17636 + + VPMOVSWBZrr = 17637 + + VPMOVSWBZrrk = 17638 + + VPMOVSWBZrrkz = 17639 + + VPMOVSXBDYrm = 17640 + + VPMOVSXBDYrr = 17641 + + VPMOVSXBDZ128rm = 17642 + + VPMOVSXBDZ128rmk = 17643 + + VPMOVSXBDZ128rmkz = 17644 + + VPMOVSXBDZ128rr = 17645 + + VPMOVSXBDZ128rrk = 17646 + + VPMOVSXBDZ128rrkz = 17647 + + VPMOVSXBDZ256rm = 17648 + + VPMOVSXBDZ256rmk = 17649 + + VPMOVSXBDZ256rmkz = 17650 + + VPMOVSXBDZ256rr = 17651 + + VPMOVSXBDZ256rrk = 17652 + + VPMOVSXBDZ256rrkz = 17653 + + VPMOVSXBDZrm = 17654 + + VPMOVSXBDZrmk = 17655 + + VPMOVSXBDZrmkz = 17656 + + VPMOVSXBDZrr = 17657 + + VPMOVSXBDZrrk = 17658 + + VPMOVSXBDZrrkz = 17659 + + VPMOVSXBDrm = 17660 + + VPMOVSXBDrr = 17661 + + VPMOVSXBQYrm = 17662 + + VPMOVSXBQYrr = 17663 + + VPMOVSXBQZ128rm = 17664 + + VPMOVSXBQZ128rmk = 17665 + + VPMOVSXBQZ128rmkz = 17666 + + VPMOVSXBQZ128rr = 17667 + + VPMOVSXBQZ128rrk = 17668 + + VPMOVSXBQZ128rrkz = 17669 + + VPMOVSXBQZ256rm = 17670 + + VPMOVSXBQZ256rmk = 17671 + + VPMOVSXBQZ256rmkz = 17672 + + VPMOVSXBQZ256rr = 17673 + + VPMOVSXBQZ256rrk = 17674 + + VPMOVSXBQZ256rrkz = 17675 + + VPMOVSXBQZrm = 17676 + + VPMOVSXBQZrmk = 17677 + + VPMOVSXBQZrmkz = 17678 + + VPMOVSXBQZrr = 17679 + + VPMOVSXBQZrrk = 17680 + + VPMOVSXBQZrrkz = 17681 + + VPMOVSXBQrm = 17682 + + VPMOVSXBQrr = 17683 + + VPMOVSXBWYrm = 17684 + + VPMOVSXBWYrr = 17685 + + VPMOVSXBWZ128rm = 17686 + + VPMOVSXBWZ128rmk = 17687 + + VPMOVSXBWZ128rmkz = 17688 + + VPMOVSXBWZ128rr = 17689 + + VPMOVSXBWZ128rrk = 17690 + + VPMOVSXBWZ128rrkz = 17691 + + VPMOVSXBWZ256rm = 17692 + + VPMOVSXBWZ256rmk = 17693 + + VPMOVSXBWZ256rmkz = 17694 + + VPMOVSXBWZ256rr = 17695 + + VPMOVSXBWZ256rrk = 17696 + + VPMOVSXBWZ256rrkz = 17697 + + VPMOVSXBWZrm = 17698 + + VPMOVSXBWZrmk = 17699 + + VPMOVSXBWZrmkz = 17700 + + VPMOVSXBWZrr = 17701 + + VPMOVSXBWZrrk = 17702 + + VPMOVSXBWZrrkz = 17703 + + VPMOVSXBWrm = 17704 + + VPMOVSXBWrr = 17705 + + VPMOVSXDQYrm = 17706 + + VPMOVSXDQYrr = 17707 + + VPMOVSXDQZ128rm = 17708 + + VPMOVSXDQZ128rmk = 17709 + + VPMOVSXDQZ128rmkz = 17710 + + VPMOVSXDQZ128rr = 17711 + + VPMOVSXDQZ128rrk = 17712 + + VPMOVSXDQZ128rrkz = 17713 + + VPMOVSXDQZ256rm = 17714 + + VPMOVSXDQZ256rmk = 17715 + + VPMOVSXDQZ256rmkz = 17716 + + VPMOVSXDQZ256rr = 17717 + + VPMOVSXDQZ256rrk = 17718 + + VPMOVSXDQZ256rrkz = 17719 + + VPMOVSXDQZrm = 17720 + + VPMOVSXDQZrmk = 17721 + + VPMOVSXDQZrmkz = 17722 + + VPMOVSXDQZrr = 17723 + + VPMOVSXDQZrrk = 17724 + + VPMOVSXDQZrrkz = 17725 + + VPMOVSXDQrm = 17726 + + VPMOVSXDQrr = 17727 + + VPMOVSXWDYrm = 17728 + + VPMOVSXWDYrr = 17729 + + VPMOVSXWDZ128rm = 17730 + + VPMOVSXWDZ128rmk = 17731 + + VPMOVSXWDZ128rmkz = 17732 + + VPMOVSXWDZ128rr = 17733 + + VPMOVSXWDZ128rrk = 17734 + + VPMOVSXWDZ128rrkz = 17735 + + VPMOVSXWDZ256rm = 17736 + + VPMOVSXWDZ256rmk = 17737 + + VPMOVSXWDZ256rmkz = 17738 + + VPMOVSXWDZ256rr = 17739 + + VPMOVSXWDZ256rrk = 17740 + + VPMOVSXWDZ256rrkz = 17741 + + VPMOVSXWDZrm = 17742 + + VPMOVSXWDZrmk = 17743 + + VPMOVSXWDZrmkz = 17744 + + VPMOVSXWDZrr = 17745 + + VPMOVSXWDZrrk = 17746 + + VPMOVSXWDZrrkz = 17747 + + VPMOVSXWDrm = 17748 + + VPMOVSXWDrr = 17749 + + VPMOVSXWQYrm = 17750 + + VPMOVSXWQYrr = 17751 + + VPMOVSXWQZ128rm = 17752 + + VPMOVSXWQZ128rmk = 17753 + + VPMOVSXWQZ128rmkz = 17754 + + VPMOVSXWQZ128rr = 17755 + + VPMOVSXWQZ128rrk = 17756 + + VPMOVSXWQZ128rrkz = 17757 + + VPMOVSXWQZ256rm = 17758 + + VPMOVSXWQZ256rmk = 17759 + + VPMOVSXWQZ256rmkz = 17760 + + VPMOVSXWQZ256rr = 17761 + + VPMOVSXWQZ256rrk = 17762 + + VPMOVSXWQZ256rrkz = 17763 + + VPMOVSXWQZrm = 17764 + + VPMOVSXWQZrmk = 17765 + + VPMOVSXWQZrmkz = 17766 + + VPMOVSXWQZrr = 17767 + + VPMOVSXWQZrrk = 17768 + + VPMOVSXWQZrrkz = 17769 + + VPMOVSXWQrm = 17770 + + VPMOVSXWQrr = 17771 + + VPMOVUSDBZ128mr = 17772 + + VPMOVUSDBZ128mrk = 17773 + + VPMOVUSDBZ128rr = 17774 + + VPMOVUSDBZ128rrk = 17775 + + VPMOVUSDBZ128rrkz = 17776 + + VPMOVUSDBZ256mr = 17777 + + VPMOVUSDBZ256mrk = 17778 + + VPMOVUSDBZ256rr = 17779 + + VPMOVUSDBZ256rrk = 17780 + + VPMOVUSDBZ256rrkz = 17781 + + VPMOVUSDBZmr = 17782 + + VPMOVUSDBZmrk = 17783 + + VPMOVUSDBZrr = 17784 + + VPMOVUSDBZrrk = 17785 + + VPMOVUSDBZrrkz = 17786 + + VPMOVUSDWZ128mr = 17787 + + VPMOVUSDWZ128mrk = 17788 + + VPMOVUSDWZ128rr = 17789 + + VPMOVUSDWZ128rrk = 17790 + + VPMOVUSDWZ128rrkz = 17791 + + VPMOVUSDWZ256mr = 17792 + + VPMOVUSDWZ256mrk = 17793 + + VPMOVUSDWZ256rr = 17794 + + VPMOVUSDWZ256rrk = 17795 + + VPMOVUSDWZ256rrkz = 17796 + + VPMOVUSDWZmr = 17797 + + VPMOVUSDWZmrk = 17798 + + VPMOVUSDWZrr = 17799 + + VPMOVUSDWZrrk = 17800 + + VPMOVUSDWZrrkz = 17801 + + VPMOVUSQBZ128mr = 17802 + + VPMOVUSQBZ128mrk = 17803 + + VPMOVUSQBZ128rr = 17804 + + VPMOVUSQBZ128rrk = 17805 + + VPMOVUSQBZ128rrkz = 17806 + + VPMOVUSQBZ256mr = 17807 + + VPMOVUSQBZ256mrk = 17808 + + VPMOVUSQBZ256rr = 17809 + + VPMOVUSQBZ256rrk = 17810 + + VPMOVUSQBZ256rrkz = 17811 + + VPMOVUSQBZmr = 17812 + + VPMOVUSQBZmrk = 17813 + + VPMOVUSQBZrr = 17814 + + VPMOVUSQBZrrk = 17815 + + VPMOVUSQBZrrkz = 17816 + + VPMOVUSQDZ128mr = 17817 + + VPMOVUSQDZ128mrk = 17818 + + VPMOVUSQDZ128rr = 17819 + + VPMOVUSQDZ128rrk = 17820 + + VPMOVUSQDZ128rrkz = 17821 + + VPMOVUSQDZ256mr = 17822 + + VPMOVUSQDZ256mrk = 17823 + + VPMOVUSQDZ256rr = 17824 + + VPMOVUSQDZ256rrk = 17825 + + VPMOVUSQDZ256rrkz = 17826 + + VPMOVUSQDZmr = 17827 + + VPMOVUSQDZmrk = 17828 + + VPMOVUSQDZrr = 17829 + + VPMOVUSQDZrrk = 17830 + + VPMOVUSQDZrrkz = 17831 + + VPMOVUSQWZ128mr = 17832 + + VPMOVUSQWZ128mrk = 17833 + + VPMOVUSQWZ128rr = 17834 + + VPMOVUSQWZ128rrk = 17835 + + VPMOVUSQWZ128rrkz = 17836 + + VPMOVUSQWZ256mr = 17837 + + VPMOVUSQWZ256mrk = 17838 + + VPMOVUSQWZ256rr = 17839 + + VPMOVUSQWZ256rrk = 17840 + + VPMOVUSQWZ256rrkz = 17841 + + VPMOVUSQWZmr = 17842 + + VPMOVUSQWZmrk = 17843 + + VPMOVUSQWZrr = 17844 + + VPMOVUSQWZrrk = 17845 + + VPMOVUSQWZrrkz = 17846 + + VPMOVUSWBZ128mr = 17847 + + VPMOVUSWBZ128mrk = 17848 + + VPMOVUSWBZ128rr = 17849 + + VPMOVUSWBZ128rrk = 17850 + + VPMOVUSWBZ128rrkz = 17851 + + VPMOVUSWBZ256mr = 17852 + + VPMOVUSWBZ256mrk = 17853 + + VPMOVUSWBZ256rr = 17854 + + VPMOVUSWBZ256rrk = 17855 + + VPMOVUSWBZ256rrkz = 17856 + + VPMOVUSWBZmr = 17857 + + VPMOVUSWBZmrk = 17858 + + VPMOVUSWBZrr = 17859 + + VPMOVUSWBZrrk = 17860 + + VPMOVUSWBZrrkz = 17861 + + VPMOVW2MZ128kr = 17862 + + VPMOVW2MZ256kr = 17863 + + VPMOVW2MZkr = 17864 + + VPMOVWBZ128mr = 17865 + + VPMOVWBZ128mrk = 17866 + + VPMOVWBZ128rr = 17867 + + VPMOVWBZ128rrk = 17868 + + VPMOVWBZ128rrkz = 17869 + + VPMOVWBZ256mr = 17870 + + VPMOVWBZ256mrk = 17871 + + VPMOVWBZ256rr = 17872 + + VPMOVWBZ256rrk = 17873 + + VPMOVWBZ256rrkz = 17874 + + VPMOVWBZmr = 17875 + + VPMOVWBZmrk = 17876 + + VPMOVWBZrr = 17877 + + VPMOVWBZrrk = 17878 + + VPMOVWBZrrkz = 17879 + + VPMOVZXBDYrm = 17880 + + VPMOVZXBDYrr = 17881 + + VPMOVZXBDZ128rm = 17882 + + VPMOVZXBDZ128rmk = 17883 + + VPMOVZXBDZ128rmkz = 17884 + + VPMOVZXBDZ128rr = 17885 + + VPMOVZXBDZ128rrk = 17886 + + VPMOVZXBDZ128rrkz = 17887 + + VPMOVZXBDZ256rm = 17888 + + VPMOVZXBDZ256rmk = 17889 + + VPMOVZXBDZ256rmkz = 17890 + + VPMOVZXBDZ256rr = 17891 + + VPMOVZXBDZ256rrk = 17892 + + VPMOVZXBDZ256rrkz = 17893 + + VPMOVZXBDZrm = 17894 + + VPMOVZXBDZrmk = 17895 + + VPMOVZXBDZrmkz = 17896 + + VPMOVZXBDZrr = 17897 + + VPMOVZXBDZrrk = 17898 + + VPMOVZXBDZrrkz = 17899 + + VPMOVZXBDrm = 17900 + + VPMOVZXBDrr = 17901 + + VPMOVZXBQYrm = 17902 + + VPMOVZXBQYrr = 17903 + + VPMOVZXBQZ128rm = 17904 + + VPMOVZXBQZ128rmk = 17905 + + VPMOVZXBQZ128rmkz = 17906 + + VPMOVZXBQZ128rr = 17907 + + VPMOVZXBQZ128rrk = 17908 + + VPMOVZXBQZ128rrkz = 17909 + + VPMOVZXBQZ256rm = 17910 + + VPMOVZXBQZ256rmk = 17911 + + VPMOVZXBQZ256rmkz = 17912 + + VPMOVZXBQZ256rr = 17913 + + VPMOVZXBQZ256rrk = 17914 + + VPMOVZXBQZ256rrkz = 17915 + + VPMOVZXBQZrm = 17916 + + VPMOVZXBQZrmk = 17917 + + VPMOVZXBQZrmkz = 17918 + + VPMOVZXBQZrr = 17919 + + VPMOVZXBQZrrk = 17920 + + VPMOVZXBQZrrkz = 17921 + + VPMOVZXBQrm = 17922 + + VPMOVZXBQrr = 17923 + + VPMOVZXBWYrm = 17924 + + VPMOVZXBWYrr = 17925 + + VPMOVZXBWZ128rm = 17926 + + VPMOVZXBWZ128rmk = 17927 + + VPMOVZXBWZ128rmkz = 17928 + + VPMOVZXBWZ128rr = 17929 + + VPMOVZXBWZ128rrk = 17930 + + VPMOVZXBWZ128rrkz = 17931 + + VPMOVZXBWZ256rm = 17932 + + VPMOVZXBWZ256rmk = 17933 + + VPMOVZXBWZ256rmkz = 17934 + + VPMOVZXBWZ256rr = 17935 + + VPMOVZXBWZ256rrk = 17936 + + VPMOVZXBWZ256rrkz = 17937 + + VPMOVZXBWZrm = 17938 + + VPMOVZXBWZrmk = 17939 + + VPMOVZXBWZrmkz = 17940 + + VPMOVZXBWZrr = 17941 + + VPMOVZXBWZrrk = 17942 + + VPMOVZXBWZrrkz = 17943 + + VPMOVZXBWrm = 17944 + + VPMOVZXBWrr = 17945 + + VPMOVZXDQYrm = 17946 + + VPMOVZXDQYrr = 17947 + + VPMOVZXDQZ128rm = 17948 + + VPMOVZXDQZ128rmk = 17949 + + VPMOVZXDQZ128rmkz = 17950 + + VPMOVZXDQZ128rr = 17951 + + VPMOVZXDQZ128rrk = 17952 + + VPMOVZXDQZ128rrkz = 17953 + + VPMOVZXDQZ256rm = 17954 + + VPMOVZXDQZ256rmk = 17955 + + VPMOVZXDQZ256rmkz = 17956 + + VPMOVZXDQZ256rr = 17957 + + VPMOVZXDQZ256rrk = 17958 + + VPMOVZXDQZ256rrkz = 17959 + + VPMOVZXDQZrm = 17960 + + VPMOVZXDQZrmk = 17961 + + VPMOVZXDQZrmkz = 17962 + + VPMOVZXDQZrr = 17963 + + VPMOVZXDQZrrk = 17964 + + VPMOVZXDQZrrkz = 17965 + + VPMOVZXDQrm = 17966 + + VPMOVZXDQrr = 17967 + + VPMOVZXWDYrm = 17968 + + VPMOVZXWDYrr = 17969 + + VPMOVZXWDZ128rm = 17970 + + VPMOVZXWDZ128rmk = 17971 + + VPMOVZXWDZ128rmkz = 17972 + + VPMOVZXWDZ128rr = 17973 + + VPMOVZXWDZ128rrk = 17974 + + VPMOVZXWDZ128rrkz = 17975 + + VPMOVZXWDZ256rm = 17976 + + VPMOVZXWDZ256rmk = 17977 + + VPMOVZXWDZ256rmkz = 17978 + + VPMOVZXWDZ256rr = 17979 + + VPMOVZXWDZ256rrk = 17980 + + VPMOVZXWDZ256rrkz = 17981 + + VPMOVZXWDZrm = 17982 + + VPMOVZXWDZrmk = 17983 + + VPMOVZXWDZrmkz = 17984 + + VPMOVZXWDZrr = 17985 + + VPMOVZXWDZrrk = 17986 + + VPMOVZXWDZrrkz = 17987 + + VPMOVZXWDrm = 17988 + + VPMOVZXWDrr = 17989 + + VPMOVZXWQYrm = 17990 + + VPMOVZXWQYrr = 17991 + + VPMOVZXWQZ128rm = 17992 + + VPMOVZXWQZ128rmk = 17993 + + VPMOVZXWQZ128rmkz = 17994 + + VPMOVZXWQZ128rr = 17995 + + VPMOVZXWQZ128rrk = 17996 + + VPMOVZXWQZ128rrkz = 17997 + + VPMOVZXWQZ256rm = 17998 + + VPMOVZXWQZ256rmk = 17999 + + VPMOVZXWQZ256rmkz = 18000 + + VPMOVZXWQZ256rr = 18001 + + VPMOVZXWQZ256rrk = 18002 + + VPMOVZXWQZ256rrkz = 18003 + + VPMOVZXWQZrm = 18004 + + VPMOVZXWQZrmk = 18005 + + VPMOVZXWQZrmkz = 18006 + + VPMOVZXWQZrr = 18007 + + VPMOVZXWQZrrk = 18008 + + VPMOVZXWQZrrkz = 18009 + + VPMOVZXWQrm = 18010 + + VPMOVZXWQrr = 18011 + + VPMULDQYrm = 18012 + + VPMULDQYrr = 18013 + + VPMULDQZ128rm = 18014 + + VPMULDQZ128rmb = 18015 + + VPMULDQZ128rmbk = 18016 + + VPMULDQZ128rmbkz = 18017 + + VPMULDQZ128rmk = 18018 + + VPMULDQZ128rmkz = 18019 + + VPMULDQZ128rr = 18020 + + VPMULDQZ128rrk = 18021 + + VPMULDQZ128rrkz = 18022 + + VPMULDQZ256rm = 18023 + + VPMULDQZ256rmb = 18024 + + VPMULDQZ256rmbk = 18025 + + VPMULDQZ256rmbkz = 18026 + + VPMULDQZ256rmk = 18027 + + VPMULDQZ256rmkz = 18028 + + VPMULDQZ256rr = 18029 + + VPMULDQZ256rrk = 18030 + + VPMULDQZ256rrkz = 18031 + + VPMULDQZrm = 18032 + + VPMULDQZrmb = 18033 + + VPMULDQZrmbk = 18034 + + VPMULDQZrmbkz = 18035 + + VPMULDQZrmk = 18036 + + VPMULDQZrmkz = 18037 + + VPMULDQZrr = 18038 + + VPMULDQZrrk = 18039 + + VPMULDQZrrkz = 18040 + + VPMULDQrm = 18041 + + VPMULDQrr = 18042 + + VPMULHRSWYrm = 18043 + + VPMULHRSWYrr = 18044 + + VPMULHRSWZ128rm = 18045 + + VPMULHRSWZ128rmk = 18046 + + VPMULHRSWZ128rmkz = 18047 + + VPMULHRSWZ128rr = 18048 + + VPMULHRSWZ128rrk = 18049 + + VPMULHRSWZ128rrkz = 18050 + + VPMULHRSWZ256rm = 18051 + + VPMULHRSWZ256rmk = 18052 + + VPMULHRSWZ256rmkz = 18053 + + VPMULHRSWZ256rr = 18054 + + VPMULHRSWZ256rrk = 18055 + + VPMULHRSWZ256rrkz = 18056 + + VPMULHRSWZrm = 18057 + + VPMULHRSWZrmk = 18058 + + VPMULHRSWZrmkz = 18059 + + VPMULHRSWZrr = 18060 + + VPMULHRSWZrrk = 18061 + + VPMULHRSWZrrkz = 18062 + + VPMULHRSWrm = 18063 + + VPMULHRSWrr = 18064 + + VPMULHUWYrm = 18065 + + VPMULHUWYrr = 18066 + + VPMULHUWZ128rm = 18067 + + VPMULHUWZ128rmk = 18068 + + VPMULHUWZ128rmkz = 18069 + + VPMULHUWZ128rr = 18070 + + VPMULHUWZ128rrk = 18071 + + VPMULHUWZ128rrkz = 18072 + + VPMULHUWZ256rm = 18073 + + VPMULHUWZ256rmk = 18074 + + VPMULHUWZ256rmkz = 18075 + + VPMULHUWZ256rr = 18076 + + VPMULHUWZ256rrk = 18077 + + VPMULHUWZ256rrkz = 18078 + + VPMULHUWZrm = 18079 + + VPMULHUWZrmk = 18080 + + VPMULHUWZrmkz = 18081 + + VPMULHUWZrr = 18082 + + VPMULHUWZrrk = 18083 + + VPMULHUWZrrkz = 18084 + + VPMULHUWrm = 18085 + + VPMULHUWrr = 18086 + + VPMULHWYrm = 18087 + + VPMULHWYrr = 18088 + + VPMULHWZ128rm = 18089 + + VPMULHWZ128rmk = 18090 + + VPMULHWZ128rmkz = 18091 + + VPMULHWZ128rr = 18092 + + VPMULHWZ128rrk = 18093 + + VPMULHWZ128rrkz = 18094 + + VPMULHWZ256rm = 18095 + + VPMULHWZ256rmk = 18096 + + VPMULHWZ256rmkz = 18097 + + VPMULHWZ256rr = 18098 + + VPMULHWZ256rrk = 18099 + + VPMULHWZ256rrkz = 18100 + + VPMULHWZrm = 18101 + + VPMULHWZrmk = 18102 + + VPMULHWZrmkz = 18103 + + VPMULHWZrr = 18104 + + VPMULHWZrrk = 18105 + + VPMULHWZrrkz = 18106 + + VPMULHWrm = 18107 + + VPMULHWrr = 18108 + + VPMULLDYrm = 18109 + + VPMULLDYrr = 18110 + + VPMULLDZ128rm = 18111 + + VPMULLDZ128rmb = 18112 + + VPMULLDZ128rmbk = 18113 + + VPMULLDZ128rmbkz = 18114 + + VPMULLDZ128rmk = 18115 + + VPMULLDZ128rmkz = 18116 + + VPMULLDZ128rr = 18117 + + VPMULLDZ128rrk = 18118 + + VPMULLDZ128rrkz = 18119 + + VPMULLDZ256rm = 18120 + + VPMULLDZ256rmb = 18121 + + VPMULLDZ256rmbk = 18122 + + VPMULLDZ256rmbkz = 18123 + + VPMULLDZ256rmk = 18124 + + VPMULLDZ256rmkz = 18125 + + VPMULLDZ256rr = 18126 + + VPMULLDZ256rrk = 18127 + + VPMULLDZ256rrkz = 18128 + + VPMULLDZrm = 18129 + + VPMULLDZrmb = 18130 + + VPMULLDZrmbk = 18131 + + VPMULLDZrmbkz = 18132 + + VPMULLDZrmk = 18133 + + VPMULLDZrmkz = 18134 + + VPMULLDZrr = 18135 + + VPMULLDZrrk = 18136 + + VPMULLDZrrkz = 18137 + + VPMULLDrm = 18138 + + VPMULLDrr = 18139 + + VPMULLQZ128rm = 18140 + + VPMULLQZ128rmb = 18141 + + VPMULLQZ128rmbk = 18142 + + VPMULLQZ128rmbkz = 18143 + + VPMULLQZ128rmk = 18144 + + VPMULLQZ128rmkz = 18145 + + VPMULLQZ128rr = 18146 + + VPMULLQZ128rrk = 18147 + + VPMULLQZ128rrkz = 18148 + + VPMULLQZ256rm = 18149 + + VPMULLQZ256rmb = 18150 + + VPMULLQZ256rmbk = 18151 + + VPMULLQZ256rmbkz = 18152 + + VPMULLQZ256rmk = 18153 + + VPMULLQZ256rmkz = 18154 + + VPMULLQZ256rr = 18155 + + VPMULLQZ256rrk = 18156 + + VPMULLQZ256rrkz = 18157 + + VPMULLQZrm = 18158 + + VPMULLQZrmb = 18159 + + VPMULLQZrmbk = 18160 + + VPMULLQZrmbkz = 18161 + + VPMULLQZrmk = 18162 + + VPMULLQZrmkz = 18163 + + VPMULLQZrr = 18164 + + VPMULLQZrrk = 18165 + + VPMULLQZrrkz = 18166 + + VPMULLWYrm = 18167 + + VPMULLWYrr = 18168 + + VPMULLWZ128rm = 18169 + + VPMULLWZ128rmk = 18170 + + VPMULLWZ128rmkz = 18171 + + VPMULLWZ128rr = 18172 + + VPMULLWZ128rrk = 18173 + + VPMULLWZ128rrkz = 18174 + + VPMULLWZ256rm = 18175 + + VPMULLWZ256rmk = 18176 + + VPMULLWZ256rmkz = 18177 + + VPMULLWZ256rr = 18178 + + VPMULLWZ256rrk = 18179 + + VPMULLWZ256rrkz = 18180 + + VPMULLWZrm = 18181 + + VPMULLWZrmk = 18182 + + VPMULLWZrmkz = 18183 + + VPMULLWZrr = 18184 + + VPMULLWZrrk = 18185 + + VPMULLWZrrkz = 18186 + + VPMULLWrm = 18187 + + VPMULLWrr = 18188 + + VPMULTISHIFTQBZ128rm = 18189 + + VPMULTISHIFTQBZ128rmb = 18190 + + VPMULTISHIFTQBZ128rmbk = 18191 + + VPMULTISHIFTQBZ128rmbkz = 18192 + + VPMULTISHIFTQBZ128rmk = 18193 + + VPMULTISHIFTQBZ128rmkz = 18194 + + VPMULTISHIFTQBZ128rr = 18195 + + VPMULTISHIFTQBZ128rrk = 18196 + + VPMULTISHIFTQBZ128rrkz = 18197 + + VPMULTISHIFTQBZ256rm = 18198 + + VPMULTISHIFTQBZ256rmb = 18199 + + VPMULTISHIFTQBZ256rmbk = 18200 + + VPMULTISHIFTQBZ256rmbkz = 18201 + + VPMULTISHIFTQBZ256rmk = 18202 + + VPMULTISHIFTQBZ256rmkz = 18203 + + VPMULTISHIFTQBZ256rr = 18204 + + VPMULTISHIFTQBZ256rrk = 18205 + + VPMULTISHIFTQBZ256rrkz = 18206 + + VPMULTISHIFTQBZrm = 18207 + + VPMULTISHIFTQBZrmb = 18208 + + VPMULTISHIFTQBZrmbk = 18209 + + VPMULTISHIFTQBZrmbkz = 18210 + + VPMULTISHIFTQBZrmk = 18211 + + VPMULTISHIFTQBZrmkz = 18212 + + VPMULTISHIFTQBZrr = 18213 + + VPMULTISHIFTQBZrrk = 18214 + + VPMULTISHIFTQBZrrkz = 18215 + + VPMULUDQYrm = 18216 + + VPMULUDQYrr = 18217 + + VPMULUDQZ128rm = 18218 + + VPMULUDQZ128rmb = 18219 + + VPMULUDQZ128rmbk = 18220 + + VPMULUDQZ128rmbkz = 18221 + + VPMULUDQZ128rmk = 18222 + + VPMULUDQZ128rmkz = 18223 + + VPMULUDQZ128rr = 18224 + + VPMULUDQZ128rrk = 18225 + + VPMULUDQZ128rrkz = 18226 + + VPMULUDQZ256rm = 18227 + + VPMULUDQZ256rmb = 18228 + + VPMULUDQZ256rmbk = 18229 + + VPMULUDQZ256rmbkz = 18230 + + VPMULUDQZ256rmk = 18231 + + VPMULUDQZ256rmkz = 18232 + + VPMULUDQZ256rr = 18233 + + VPMULUDQZ256rrk = 18234 + + VPMULUDQZ256rrkz = 18235 + + VPMULUDQZrm = 18236 + + VPMULUDQZrmb = 18237 + + VPMULUDQZrmbk = 18238 + + VPMULUDQZrmbkz = 18239 + + VPMULUDQZrmk = 18240 + + VPMULUDQZrmkz = 18241 + + VPMULUDQZrr = 18242 + + VPMULUDQZrrk = 18243 + + VPMULUDQZrrkz = 18244 + + VPMULUDQrm = 18245 + + VPMULUDQrr = 18246 + + VPOPCNTBZ128rm = 18247 + + VPOPCNTBZ128rmk = 18248 + + VPOPCNTBZ128rmkz = 18249 + + VPOPCNTBZ128rr = 18250 + + VPOPCNTBZ128rrk = 18251 + + VPOPCNTBZ128rrkz = 18252 + + VPOPCNTBZ256rm = 18253 + + VPOPCNTBZ256rmk = 18254 + + VPOPCNTBZ256rmkz = 18255 + + VPOPCNTBZ256rr = 18256 + + VPOPCNTBZ256rrk = 18257 + + VPOPCNTBZ256rrkz = 18258 + + VPOPCNTBZrm = 18259 + + VPOPCNTBZrmk = 18260 + + VPOPCNTBZrmkz = 18261 + + VPOPCNTBZrr = 18262 + + VPOPCNTBZrrk = 18263 + + VPOPCNTBZrrkz = 18264 + + VPOPCNTDZ128rm = 18265 + + VPOPCNTDZ128rmb = 18266 + + VPOPCNTDZ128rmbk = 18267 + + VPOPCNTDZ128rmbkz = 18268 + + VPOPCNTDZ128rmk = 18269 + + VPOPCNTDZ128rmkz = 18270 + + VPOPCNTDZ128rr = 18271 + + VPOPCNTDZ128rrk = 18272 + + VPOPCNTDZ128rrkz = 18273 + + VPOPCNTDZ256rm = 18274 + + VPOPCNTDZ256rmb = 18275 + + VPOPCNTDZ256rmbk = 18276 + + VPOPCNTDZ256rmbkz = 18277 + + VPOPCNTDZ256rmk = 18278 + + VPOPCNTDZ256rmkz = 18279 + + VPOPCNTDZ256rr = 18280 + + VPOPCNTDZ256rrk = 18281 + + VPOPCNTDZ256rrkz = 18282 + + VPOPCNTDZrm = 18283 + + VPOPCNTDZrmb = 18284 + + VPOPCNTDZrmbk = 18285 + + VPOPCNTDZrmbkz = 18286 + + VPOPCNTDZrmk = 18287 + + VPOPCNTDZrmkz = 18288 + + VPOPCNTDZrr = 18289 + + VPOPCNTDZrrk = 18290 + + VPOPCNTDZrrkz = 18291 + + VPOPCNTQZ128rm = 18292 + + VPOPCNTQZ128rmb = 18293 + + VPOPCNTQZ128rmbk = 18294 + + VPOPCNTQZ128rmbkz = 18295 + + VPOPCNTQZ128rmk = 18296 + + VPOPCNTQZ128rmkz = 18297 + + VPOPCNTQZ128rr = 18298 + + VPOPCNTQZ128rrk = 18299 + + VPOPCNTQZ128rrkz = 18300 + + VPOPCNTQZ256rm = 18301 + + VPOPCNTQZ256rmb = 18302 + + VPOPCNTQZ256rmbk = 18303 + + VPOPCNTQZ256rmbkz = 18304 + + VPOPCNTQZ256rmk = 18305 + + VPOPCNTQZ256rmkz = 18306 + + VPOPCNTQZ256rr = 18307 + + VPOPCNTQZ256rrk = 18308 + + VPOPCNTQZ256rrkz = 18309 + + VPOPCNTQZrm = 18310 + + VPOPCNTQZrmb = 18311 + + VPOPCNTQZrmbk = 18312 + + VPOPCNTQZrmbkz = 18313 + + VPOPCNTQZrmk = 18314 + + VPOPCNTQZrmkz = 18315 + + VPOPCNTQZrr = 18316 + + VPOPCNTQZrrk = 18317 + + VPOPCNTQZrrkz = 18318 + + VPOPCNTWZ128rm = 18319 + + VPOPCNTWZ128rmk = 18320 + + VPOPCNTWZ128rmkz = 18321 + + VPOPCNTWZ128rr = 18322 + + VPOPCNTWZ128rrk = 18323 + + VPOPCNTWZ128rrkz = 18324 + + VPOPCNTWZ256rm = 18325 + + VPOPCNTWZ256rmk = 18326 + + VPOPCNTWZ256rmkz = 18327 + + VPOPCNTWZ256rr = 18328 + + VPOPCNTWZ256rrk = 18329 + + VPOPCNTWZ256rrkz = 18330 + + VPOPCNTWZrm = 18331 + + VPOPCNTWZrmk = 18332 + + VPOPCNTWZrmkz = 18333 + + VPOPCNTWZrr = 18334 + + VPOPCNTWZrrk = 18335 + + VPOPCNTWZrrkz = 18336 + + VPORDZ128rm = 18337 + + VPORDZ128rmb = 18338 + + VPORDZ128rmbk = 18339 + + VPORDZ128rmbkz = 18340 + + VPORDZ128rmk = 18341 + + VPORDZ128rmkz = 18342 + + VPORDZ128rr = 18343 + + VPORDZ128rrk = 18344 + + VPORDZ128rrkz = 18345 + + VPORDZ256rm = 18346 + + VPORDZ256rmb = 18347 + + VPORDZ256rmbk = 18348 + + VPORDZ256rmbkz = 18349 + + VPORDZ256rmk = 18350 + + VPORDZ256rmkz = 18351 + + VPORDZ256rr = 18352 + + VPORDZ256rrk = 18353 + + VPORDZ256rrkz = 18354 + + VPORDZrm = 18355 + + VPORDZrmb = 18356 + + VPORDZrmbk = 18357 + + VPORDZrmbkz = 18358 + + VPORDZrmk = 18359 + + VPORDZrmkz = 18360 + + VPORDZrr = 18361 + + VPORDZrrk = 18362 + + VPORDZrrkz = 18363 + + VPORQZ128rm = 18364 + + VPORQZ128rmb = 18365 + + VPORQZ128rmbk = 18366 + + VPORQZ128rmbkz = 18367 + + VPORQZ128rmk = 18368 + + VPORQZ128rmkz = 18369 + + VPORQZ128rr = 18370 + + VPORQZ128rrk = 18371 + + VPORQZ128rrkz = 18372 + + VPORQZ256rm = 18373 + + VPORQZ256rmb = 18374 + + VPORQZ256rmbk = 18375 + + VPORQZ256rmbkz = 18376 + + VPORQZ256rmk = 18377 + + VPORQZ256rmkz = 18378 + + VPORQZ256rr = 18379 + + VPORQZ256rrk = 18380 + + VPORQZ256rrkz = 18381 + + VPORQZrm = 18382 + + VPORQZrmb = 18383 + + VPORQZrmbk = 18384 + + VPORQZrmbkz = 18385 + + VPORQZrmk = 18386 + + VPORQZrmkz = 18387 + + VPORQZrr = 18388 + + VPORQZrrk = 18389 + + VPORQZrrkz = 18390 + + VPORYrm = 18391 + + VPORYrr = 18392 + + VPORrm = 18393 + + VPORrr = 18394 + + VPPERMrmr = 18395 + + VPPERMrrm = 18396 + + VPPERMrrr = 18397 + + VPPERMrrr_REV = 18398 + + VPROLDZ128mbi = 18399 + + VPROLDZ128mbik = 18400 + + VPROLDZ128mbikz = 18401 + + VPROLDZ128mi = 18402 + + VPROLDZ128mik = 18403 + + VPROLDZ128mikz = 18404 + + VPROLDZ128ri = 18405 + + VPROLDZ128rik = 18406 + + VPROLDZ128rikz = 18407 + + VPROLDZ256mbi = 18408 + + VPROLDZ256mbik = 18409 + + VPROLDZ256mbikz = 18410 + + VPROLDZ256mi = 18411 + + VPROLDZ256mik = 18412 + + VPROLDZ256mikz = 18413 + + VPROLDZ256ri = 18414 + + VPROLDZ256rik = 18415 + + VPROLDZ256rikz = 18416 + + VPROLDZmbi = 18417 + + VPROLDZmbik = 18418 + + VPROLDZmbikz = 18419 + + VPROLDZmi = 18420 + + VPROLDZmik = 18421 + + VPROLDZmikz = 18422 + + VPROLDZri = 18423 + + VPROLDZrik = 18424 + + VPROLDZrikz = 18425 + + VPROLQZ128mbi = 18426 + + VPROLQZ128mbik = 18427 + + VPROLQZ128mbikz = 18428 + + VPROLQZ128mi = 18429 + + VPROLQZ128mik = 18430 + + VPROLQZ128mikz = 18431 + + VPROLQZ128ri = 18432 + + VPROLQZ128rik = 18433 + + VPROLQZ128rikz = 18434 + + VPROLQZ256mbi = 18435 + + VPROLQZ256mbik = 18436 + + VPROLQZ256mbikz = 18437 + + VPROLQZ256mi = 18438 + + VPROLQZ256mik = 18439 + + VPROLQZ256mikz = 18440 + + VPROLQZ256ri = 18441 + + VPROLQZ256rik = 18442 + + VPROLQZ256rikz = 18443 + + VPROLQZmbi = 18444 + + VPROLQZmbik = 18445 + + VPROLQZmbikz = 18446 + + VPROLQZmi = 18447 + + VPROLQZmik = 18448 + + VPROLQZmikz = 18449 + + VPROLQZri = 18450 + + VPROLQZrik = 18451 + + VPROLQZrikz = 18452 + + VPROLVDZ128rm = 18453 + + VPROLVDZ128rmb = 18454 + + VPROLVDZ128rmbk = 18455 + + VPROLVDZ128rmbkz = 18456 + + VPROLVDZ128rmk = 18457 + + VPROLVDZ128rmkz = 18458 + + VPROLVDZ128rr = 18459 + + VPROLVDZ128rrk = 18460 + + VPROLVDZ128rrkz = 18461 + + VPROLVDZ256rm = 18462 + + VPROLVDZ256rmb = 18463 + + VPROLVDZ256rmbk = 18464 + + VPROLVDZ256rmbkz = 18465 + + VPROLVDZ256rmk = 18466 + + VPROLVDZ256rmkz = 18467 + + VPROLVDZ256rr = 18468 + + VPROLVDZ256rrk = 18469 + + VPROLVDZ256rrkz = 18470 + + VPROLVDZrm = 18471 + + VPROLVDZrmb = 18472 + + VPROLVDZrmbk = 18473 + + VPROLVDZrmbkz = 18474 + + VPROLVDZrmk = 18475 + + VPROLVDZrmkz = 18476 + + VPROLVDZrr = 18477 + + VPROLVDZrrk = 18478 + + VPROLVDZrrkz = 18479 + + VPROLVQZ128rm = 18480 + + VPROLVQZ128rmb = 18481 + + VPROLVQZ128rmbk = 18482 + + VPROLVQZ128rmbkz = 18483 + + VPROLVQZ128rmk = 18484 + + VPROLVQZ128rmkz = 18485 + + VPROLVQZ128rr = 18486 + + VPROLVQZ128rrk = 18487 + + VPROLVQZ128rrkz = 18488 + + VPROLVQZ256rm = 18489 + + VPROLVQZ256rmb = 18490 + + VPROLVQZ256rmbk = 18491 + + VPROLVQZ256rmbkz = 18492 + + VPROLVQZ256rmk = 18493 + + VPROLVQZ256rmkz = 18494 + + VPROLVQZ256rr = 18495 + + VPROLVQZ256rrk = 18496 + + VPROLVQZ256rrkz = 18497 + + VPROLVQZrm = 18498 + + VPROLVQZrmb = 18499 + + VPROLVQZrmbk = 18500 + + VPROLVQZrmbkz = 18501 + + VPROLVQZrmk = 18502 + + VPROLVQZrmkz = 18503 + + VPROLVQZrr = 18504 + + VPROLVQZrrk = 18505 + + VPROLVQZrrkz = 18506 + + VPRORDZ128mbi = 18507 + + VPRORDZ128mbik = 18508 + + VPRORDZ128mbikz = 18509 + + VPRORDZ128mi = 18510 + + VPRORDZ128mik = 18511 + + VPRORDZ128mikz = 18512 + + VPRORDZ128ri = 18513 + + VPRORDZ128rik = 18514 + + VPRORDZ128rikz = 18515 + + VPRORDZ256mbi = 18516 + + VPRORDZ256mbik = 18517 + + VPRORDZ256mbikz = 18518 + + VPRORDZ256mi = 18519 + + VPRORDZ256mik = 18520 + + VPRORDZ256mikz = 18521 + + VPRORDZ256ri = 18522 + + VPRORDZ256rik = 18523 + + VPRORDZ256rikz = 18524 + + VPRORDZmbi = 18525 + + VPRORDZmbik = 18526 + + VPRORDZmbikz = 18527 + + VPRORDZmi = 18528 + + VPRORDZmik = 18529 + + VPRORDZmikz = 18530 + + VPRORDZri = 18531 + + VPRORDZrik = 18532 + + VPRORDZrikz = 18533 + + VPRORQZ128mbi = 18534 + + VPRORQZ128mbik = 18535 + + VPRORQZ128mbikz = 18536 + + VPRORQZ128mi = 18537 + + VPRORQZ128mik = 18538 + + VPRORQZ128mikz = 18539 + + VPRORQZ128ri = 18540 + + VPRORQZ128rik = 18541 + + VPRORQZ128rikz = 18542 + + VPRORQZ256mbi = 18543 + + VPRORQZ256mbik = 18544 + + VPRORQZ256mbikz = 18545 + + VPRORQZ256mi = 18546 + + VPRORQZ256mik = 18547 + + VPRORQZ256mikz = 18548 + + VPRORQZ256ri = 18549 + + VPRORQZ256rik = 18550 + + VPRORQZ256rikz = 18551 + + VPRORQZmbi = 18552 + + VPRORQZmbik = 18553 + + VPRORQZmbikz = 18554 + + VPRORQZmi = 18555 + + VPRORQZmik = 18556 + + VPRORQZmikz = 18557 + + VPRORQZri = 18558 + + VPRORQZrik = 18559 + + VPRORQZrikz = 18560 + + VPRORVDZ128rm = 18561 + + VPRORVDZ128rmb = 18562 + + VPRORVDZ128rmbk = 18563 + + VPRORVDZ128rmbkz = 18564 + + VPRORVDZ128rmk = 18565 + + VPRORVDZ128rmkz = 18566 + + VPRORVDZ128rr = 18567 + + VPRORVDZ128rrk = 18568 + + VPRORVDZ128rrkz = 18569 + + VPRORVDZ256rm = 18570 + + VPRORVDZ256rmb = 18571 + + VPRORVDZ256rmbk = 18572 + + VPRORVDZ256rmbkz = 18573 + + VPRORVDZ256rmk = 18574 + + VPRORVDZ256rmkz = 18575 + + VPRORVDZ256rr = 18576 + + VPRORVDZ256rrk = 18577 + + VPRORVDZ256rrkz = 18578 + + VPRORVDZrm = 18579 + + VPRORVDZrmb = 18580 + + VPRORVDZrmbk = 18581 + + VPRORVDZrmbkz = 18582 + + VPRORVDZrmk = 18583 + + VPRORVDZrmkz = 18584 + + VPRORVDZrr = 18585 + + VPRORVDZrrk = 18586 + + VPRORVDZrrkz = 18587 + + VPRORVQZ128rm = 18588 + + VPRORVQZ128rmb = 18589 + + VPRORVQZ128rmbk = 18590 + + VPRORVQZ128rmbkz = 18591 + + VPRORVQZ128rmk = 18592 + + VPRORVQZ128rmkz = 18593 + + VPRORVQZ128rr = 18594 + + VPRORVQZ128rrk = 18595 + + VPRORVQZ128rrkz = 18596 + + VPRORVQZ256rm = 18597 + + VPRORVQZ256rmb = 18598 + + VPRORVQZ256rmbk = 18599 + + VPRORVQZ256rmbkz = 18600 + + VPRORVQZ256rmk = 18601 + + VPRORVQZ256rmkz = 18602 + + VPRORVQZ256rr = 18603 + + VPRORVQZ256rrk = 18604 + + VPRORVQZ256rrkz = 18605 + + VPRORVQZrm = 18606 + + VPRORVQZrmb = 18607 + + VPRORVQZrmbk = 18608 + + VPRORVQZrmbkz = 18609 + + VPRORVQZrmk = 18610 + + VPRORVQZrmkz = 18611 + + VPRORVQZrr = 18612 + + VPRORVQZrrk = 18613 + + VPRORVQZrrkz = 18614 + + VPROTBmi = 18615 + + VPROTBmr = 18616 + + VPROTBri = 18617 + + VPROTBrm = 18618 + + VPROTBrr = 18619 + + VPROTBrr_REV = 18620 + + VPROTDmi = 18621 + + VPROTDmr = 18622 + + VPROTDri = 18623 + + VPROTDrm = 18624 + + VPROTDrr = 18625 + + VPROTDrr_REV = 18626 + + VPROTQmi = 18627 + + VPROTQmr = 18628 + + VPROTQri = 18629 + + VPROTQrm = 18630 + + VPROTQrr = 18631 + + VPROTQrr_REV = 18632 + + VPROTWmi = 18633 + + VPROTWmr = 18634 + + VPROTWri = 18635 + + VPROTWrm = 18636 + + VPROTWrr = 18637 + + VPROTWrr_REV = 18638 + + VPSADBWYrm = 18639 + + VPSADBWYrr = 18640 + + VPSADBWZ128rm = 18641 + + VPSADBWZ128rr = 18642 + + VPSADBWZ256rm = 18643 + + VPSADBWZ256rr = 18644 + + VPSADBWZrm = 18645 + + VPSADBWZrr = 18646 + + VPSADBWrm = 18647 + + VPSADBWrr = 18648 + + VPSCATTERDDZ128mr = 18649 + + VPSCATTERDDZ256mr = 18650 + + VPSCATTERDDZmr = 18651 + + VPSCATTERDQZ128mr = 18652 + + VPSCATTERDQZ256mr = 18653 + + VPSCATTERDQZmr = 18654 + + VPSCATTERQDZ128mr = 18655 + + VPSCATTERQDZ256mr = 18656 + + VPSCATTERQDZmr = 18657 + + VPSCATTERQQZ128mr = 18658 + + VPSCATTERQQZ256mr = 18659 + + VPSCATTERQQZmr = 18660 + + VPSHABmr = 18661 + + VPSHABrm = 18662 + + VPSHABrr = 18663 + + VPSHABrr_REV = 18664 + + VPSHADmr = 18665 + + VPSHADrm = 18666 + + VPSHADrr = 18667 + + VPSHADrr_REV = 18668 + + VPSHAQmr = 18669 + + VPSHAQrm = 18670 + + VPSHAQrr = 18671 + + VPSHAQrr_REV = 18672 + + VPSHAWmr = 18673 + + VPSHAWrm = 18674 + + VPSHAWrr = 18675 + + VPSHAWrr_REV = 18676 + + VPSHLBmr = 18677 + + VPSHLBrm = 18678 + + VPSHLBrr = 18679 + + VPSHLBrr_REV = 18680 + + VPSHLDDZ128rmbi = 18681 + + VPSHLDDZ128rmbik = 18682 + + VPSHLDDZ128rmbikz = 18683 + + VPSHLDDZ128rmi = 18684 + + VPSHLDDZ128rmik = 18685 + + VPSHLDDZ128rmikz = 18686 + + VPSHLDDZ128rri = 18687 + + VPSHLDDZ128rrik = 18688 + + VPSHLDDZ128rrikz = 18689 + + VPSHLDDZ256rmbi = 18690 + + VPSHLDDZ256rmbik = 18691 + + VPSHLDDZ256rmbikz = 18692 + + VPSHLDDZ256rmi = 18693 + + VPSHLDDZ256rmik = 18694 + + VPSHLDDZ256rmikz = 18695 + + VPSHLDDZ256rri = 18696 + + VPSHLDDZ256rrik = 18697 + + VPSHLDDZ256rrikz = 18698 + + VPSHLDDZrmbi = 18699 + + VPSHLDDZrmbik = 18700 + + VPSHLDDZrmbikz = 18701 + + VPSHLDDZrmi = 18702 + + VPSHLDDZrmik = 18703 + + VPSHLDDZrmikz = 18704 + + VPSHLDDZrri = 18705 + + VPSHLDDZrrik = 18706 + + VPSHLDDZrrikz = 18707 + + VPSHLDQZ128rmbi = 18708 + + VPSHLDQZ128rmbik = 18709 + + VPSHLDQZ128rmbikz = 18710 + + VPSHLDQZ128rmi = 18711 + + VPSHLDQZ128rmik = 18712 + + VPSHLDQZ128rmikz = 18713 + + VPSHLDQZ128rri = 18714 + + VPSHLDQZ128rrik = 18715 + + VPSHLDQZ128rrikz = 18716 + + VPSHLDQZ256rmbi = 18717 + + VPSHLDQZ256rmbik = 18718 + + VPSHLDQZ256rmbikz = 18719 + + VPSHLDQZ256rmi = 18720 + + VPSHLDQZ256rmik = 18721 + + VPSHLDQZ256rmikz = 18722 + + VPSHLDQZ256rri = 18723 + + VPSHLDQZ256rrik = 18724 + + VPSHLDQZ256rrikz = 18725 + + VPSHLDQZrmbi = 18726 + + VPSHLDQZrmbik = 18727 + + VPSHLDQZrmbikz = 18728 + + VPSHLDQZrmi = 18729 + + VPSHLDQZrmik = 18730 + + VPSHLDQZrmikz = 18731 + + VPSHLDQZrri = 18732 + + VPSHLDQZrrik = 18733 + + VPSHLDQZrrikz = 18734 + + VPSHLDVDZ128m = 18735 + + VPSHLDVDZ128mb = 18736 + + VPSHLDVDZ128mbk = 18737 + + VPSHLDVDZ128mbkz = 18738 + + VPSHLDVDZ128mk = 18739 + + VPSHLDVDZ128mkz = 18740 + + VPSHLDVDZ128r = 18741 + + VPSHLDVDZ128rk = 18742 + + VPSHLDVDZ128rkz = 18743 + + VPSHLDVDZ256m = 18744 + + VPSHLDVDZ256mb = 18745 + + VPSHLDVDZ256mbk = 18746 + + VPSHLDVDZ256mbkz = 18747 + + VPSHLDVDZ256mk = 18748 + + VPSHLDVDZ256mkz = 18749 + + VPSHLDVDZ256r = 18750 + + VPSHLDVDZ256rk = 18751 + + VPSHLDVDZ256rkz = 18752 + + VPSHLDVDZm = 18753 + + VPSHLDVDZmb = 18754 + + VPSHLDVDZmbk = 18755 + + VPSHLDVDZmbkz = 18756 + + VPSHLDVDZmk = 18757 + + VPSHLDVDZmkz = 18758 + + VPSHLDVDZr = 18759 + + VPSHLDVDZrk = 18760 + + VPSHLDVDZrkz = 18761 + + VPSHLDVQZ128m = 18762 + + VPSHLDVQZ128mb = 18763 + + VPSHLDVQZ128mbk = 18764 + + VPSHLDVQZ128mbkz = 18765 + + VPSHLDVQZ128mk = 18766 + + VPSHLDVQZ128mkz = 18767 + + VPSHLDVQZ128r = 18768 + + VPSHLDVQZ128rk = 18769 + + VPSHLDVQZ128rkz = 18770 + + VPSHLDVQZ256m = 18771 + + VPSHLDVQZ256mb = 18772 + + VPSHLDVQZ256mbk = 18773 + + VPSHLDVQZ256mbkz = 18774 + + VPSHLDVQZ256mk = 18775 + + VPSHLDVQZ256mkz = 18776 + + VPSHLDVQZ256r = 18777 + + VPSHLDVQZ256rk = 18778 + + VPSHLDVQZ256rkz = 18779 + + VPSHLDVQZm = 18780 + + VPSHLDVQZmb = 18781 + + VPSHLDVQZmbk = 18782 + + VPSHLDVQZmbkz = 18783 + + VPSHLDVQZmk = 18784 + + VPSHLDVQZmkz = 18785 + + VPSHLDVQZr = 18786 + + VPSHLDVQZrk = 18787 + + VPSHLDVQZrkz = 18788 + + VPSHLDVWZ128m = 18789 + + VPSHLDVWZ128mk = 18790 + + VPSHLDVWZ128mkz = 18791 + + VPSHLDVWZ128r = 18792 + + VPSHLDVWZ128rk = 18793 + + VPSHLDVWZ128rkz = 18794 + + VPSHLDVWZ256m = 18795 + + VPSHLDVWZ256mk = 18796 + + VPSHLDVWZ256mkz = 18797 + + VPSHLDVWZ256r = 18798 + + VPSHLDVWZ256rk = 18799 + + VPSHLDVWZ256rkz = 18800 + + VPSHLDVWZm = 18801 + + VPSHLDVWZmk = 18802 + + VPSHLDVWZmkz = 18803 + + VPSHLDVWZr = 18804 + + VPSHLDVWZrk = 18805 + + VPSHLDVWZrkz = 18806 + + VPSHLDWZ128rmi = 18807 + + VPSHLDWZ128rmik = 18808 + + VPSHLDWZ128rmikz = 18809 + + VPSHLDWZ128rri = 18810 + + VPSHLDWZ128rrik = 18811 + + VPSHLDWZ128rrikz = 18812 + + VPSHLDWZ256rmi = 18813 + + VPSHLDWZ256rmik = 18814 + + VPSHLDWZ256rmikz = 18815 + + VPSHLDWZ256rri = 18816 + + VPSHLDWZ256rrik = 18817 + + VPSHLDWZ256rrikz = 18818 + + VPSHLDWZrmi = 18819 + + VPSHLDWZrmik = 18820 + + VPSHLDWZrmikz = 18821 + + VPSHLDWZrri = 18822 + + VPSHLDWZrrik = 18823 + + VPSHLDWZrrikz = 18824 + + VPSHLDmr = 18825 + + VPSHLDrm = 18826 + + VPSHLDrr = 18827 + + VPSHLDrr_REV = 18828 + + VPSHLQmr = 18829 + + VPSHLQrm = 18830 + + VPSHLQrr = 18831 + + VPSHLQrr_REV = 18832 + + VPSHLWmr = 18833 + + VPSHLWrm = 18834 + + VPSHLWrr = 18835 + + VPSHLWrr_REV = 18836 + + VPSHRDDZ128rmbi = 18837 + + VPSHRDDZ128rmbik = 18838 + + VPSHRDDZ128rmbikz = 18839 + + VPSHRDDZ128rmi = 18840 + + VPSHRDDZ128rmik = 18841 + + VPSHRDDZ128rmikz = 18842 + + VPSHRDDZ128rri = 18843 + + VPSHRDDZ128rrik = 18844 + + VPSHRDDZ128rrikz = 18845 + + VPSHRDDZ256rmbi = 18846 + + VPSHRDDZ256rmbik = 18847 + + VPSHRDDZ256rmbikz = 18848 + + VPSHRDDZ256rmi = 18849 + + VPSHRDDZ256rmik = 18850 + + VPSHRDDZ256rmikz = 18851 + + VPSHRDDZ256rri = 18852 + + VPSHRDDZ256rrik = 18853 + + VPSHRDDZ256rrikz = 18854 + + VPSHRDDZrmbi = 18855 + + VPSHRDDZrmbik = 18856 + + VPSHRDDZrmbikz = 18857 + + VPSHRDDZrmi = 18858 + + VPSHRDDZrmik = 18859 + + VPSHRDDZrmikz = 18860 + + VPSHRDDZrri = 18861 + + VPSHRDDZrrik = 18862 + + VPSHRDDZrrikz = 18863 + + VPSHRDQZ128rmbi = 18864 + + VPSHRDQZ128rmbik = 18865 + + VPSHRDQZ128rmbikz = 18866 + + VPSHRDQZ128rmi = 18867 + + VPSHRDQZ128rmik = 18868 + + VPSHRDQZ128rmikz = 18869 + + VPSHRDQZ128rri = 18870 + + VPSHRDQZ128rrik = 18871 + + VPSHRDQZ128rrikz = 18872 + + VPSHRDQZ256rmbi = 18873 + + VPSHRDQZ256rmbik = 18874 + + VPSHRDQZ256rmbikz = 18875 + + VPSHRDQZ256rmi = 18876 + + VPSHRDQZ256rmik = 18877 + + VPSHRDQZ256rmikz = 18878 + + VPSHRDQZ256rri = 18879 + + VPSHRDQZ256rrik = 18880 + + VPSHRDQZ256rrikz = 18881 + + VPSHRDQZrmbi = 18882 + + VPSHRDQZrmbik = 18883 + + VPSHRDQZrmbikz = 18884 + + VPSHRDQZrmi = 18885 + + VPSHRDQZrmik = 18886 + + VPSHRDQZrmikz = 18887 + + VPSHRDQZrri = 18888 + + VPSHRDQZrrik = 18889 + + VPSHRDQZrrikz = 18890 + + VPSHRDVDZ128m = 18891 + + VPSHRDVDZ128mb = 18892 + + VPSHRDVDZ128mbk = 18893 + + VPSHRDVDZ128mbkz = 18894 + + VPSHRDVDZ128mk = 18895 + + VPSHRDVDZ128mkz = 18896 + + VPSHRDVDZ128r = 18897 + + VPSHRDVDZ128rk = 18898 + + VPSHRDVDZ128rkz = 18899 + + VPSHRDVDZ256m = 18900 + + VPSHRDVDZ256mb = 18901 + + VPSHRDVDZ256mbk = 18902 + + VPSHRDVDZ256mbkz = 18903 + + VPSHRDVDZ256mk = 18904 + + VPSHRDVDZ256mkz = 18905 + + VPSHRDVDZ256r = 18906 + + VPSHRDVDZ256rk = 18907 + + VPSHRDVDZ256rkz = 18908 + + VPSHRDVDZm = 18909 + + VPSHRDVDZmb = 18910 + + VPSHRDVDZmbk = 18911 + + VPSHRDVDZmbkz = 18912 + + VPSHRDVDZmk = 18913 + + VPSHRDVDZmkz = 18914 + + VPSHRDVDZr = 18915 + + VPSHRDVDZrk = 18916 + + VPSHRDVDZrkz = 18917 + + VPSHRDVQZ128m = 18918 + + VPSHRDVQZ128mb = 18919 + + VPSHRDVQZ128mbk = 18920 + + VPSHRDVQZ128mbkz = 18921 + + VPSHRDVQZ128mk = 18922 + + VPSHRDVQZ128mkz = 18923 + + VPSHRDVQZ128r = 18924 + + VPSHRDVQZ128rk = 18925 + + VPSHRDVQZ128rkz = 18926 + + VPSHRDVQZ256m = 18927 + + VPSHRDVQZ256mb = 18928 + + VPSHRDVQZ256mbk = 18929 + + VPSHRDVQZ256mbkz = 18930 + + VPSHRDVQZ256mk = 18931 + + VPSHRDVQZ256mkz = 18932 + + VPSHRDVQZ256r = 18933 + + VPSHRDVQZ256rk = 18934 + + VPSHRDVQZ256rkz = 18935 + + VPSHRDVQZm = 18936 + + VPSHRDVQZmb = 18937 + + VPSHRDVQZmbk = 18938 + + VPSHRDVQZmbkz = 18939 + + VPSHRDVQZmk = 18940 + + VPSHRDVQZmkz = 18941 + + VPSHRDVQZr = 18942 + + VPSHRDVQZrk = 18943 + + VPSHRDVQZrkz = 18944 + + VPSHRDVWZ128m = 18945 + + VPSHRDVWZ128mk = 18946 + + VPSHRDVWZ128mkz = 18947 + + VPSHRDVWZ128r = 18948 + + VPSHRDVWZ128rk = 18949 + + VPSHRDVWZ128rkz = 18950 + + VPSHRDVWZ256m = 18951 + + VPSHRDVWZ256mk = 18952 + + VPSHRDVWZ256mkz = 18953 + + VPSHRDVWZ256r = 18954 + + VPSHRDVWZ256rk = 18955 + + VPSHRDVWZ256rkz = 18956 + + VPSHRDVWZm = 18957 + + VPSHRDVWZmk = 18958 + + VPSHRDVWZmkz = 18959 + + VPSHRDVWZr = 18960 + + VPSHRDVWZrk = 18961 + + VPSHRDVWZrkz = 18962 + + VPSHRDWZ128rmi = 18963 + + VPSHRDWZ128rmik = 18964 + + VPSHRDWZ128rmikz = 18965 + + VPSHRDWZ128rri = 18966 + + VPSHRDWZ128rrik = 18967 + + VPSHRDWZ128rrikz = 18968 + + VPSHRDWZ256rmi = 18969 + + VPSHRDWZ256rmik = 18970 + + VPSHRDWZ256rmikz = 18971 + + VPSHRDWZ256rri = 18972 + + VPSHRDWZ256rrik = 18973 + + VPSHRDWZ256rrikz = 18974 + + VPSHRDWZrmi = 18975 + + VPSHRDWZrmik = 18976 + + VPSHRDWZrmikz = 18977 + + VPSHRDWZrri = 18978 + + VPSHRDWZrrik = 18979 + + VPSHRDWZrrikz = 18980 + + VPSHUFBITQMBZ128rm = 18981 + + VPSHUFBITQMBZ128rmk = 18982 + + VPSHUFBITQMBZ128rr = 18983 + + VPSHUFBITQMBZ128rrk = 18984 + + VPSHUFBITQMBZ256rm = 18985 + + VPSHUFBITQMBZ256rmk = 18986 + + VPSHUFBITQMBZ256rr = 18987 + + VPSHUFBITQMBZ256rrk = 18988 + + VPSHUFBITQMBZrm = 18989 + + VPSHUFBITQMBZrmk = 18990 + + VPSHUFBITQMBZrr = 18991 + + VPSHUFBITQMBZrrk = 18992 + + VPSHUFBYrm = 18993 + + VPSHUFBYrr = 18994 + + VPSHUFBZ128rm = 18995 + + VPSHUFBZ128rmk = 18996 + + VPSHUFBZ128rmkz = 18997 + + VPSHUFBZ128rr = 18998 + + VPSHUFBZ128rrk = 18999 + + VPSHUFBZ128rrkz = 19000 + + VPSHUFBZ256rm = 19001 + + VPSHUFBZ256rmk = 19002 + + VPSHUFBZ256rmkz = 19003 + + VPSHUFBZ256rr = 19004 + + VPSHUFBZ256rrk = 19005 + + VPSHUFBZ256rrkz = 19006 + + VPSHUFBZrm = 19007 + + VPSHUFBZrmk = 19008 + + VPSHUFBZrmkz = 19009 + + VPSHUFBZrr = 19010 + + VPSHUFBZrrk = 19011 + + VPSHUFBZrrkz = 19012 + + VPSHUFBrm = 19013 + + VPSHUFBrr = 19014 + + VPSHUFDYmi = 19015 + + VPSHUFDYri = 19016 + + VPSHUFDZ128mbi = 19017 + + VPSHUFDZ128mbik = 19018 + + VPSHUFDZ128mbikz = 19019 + + VPSHUFDZ128mi = 19020 + + VPSHUFDZ128mik = 19021 + + VPSHUFDZ128mikz = 19022 + + VPSHUFDZ128ri = 19023 + + VPSHUFDZ128rik = 19024 + + VPSHUFDZ128rikz = 19025 + + VPSHUFDZ256mbi = 19026 + + VPSHUFDZ256mbik = 19027 + + VPSHUFDZ256mbikz = 19028 + + VPSHUFDZ256mi = 19029 + + VPSHUFDZ256mik = 19030 + + VPSHUFDZ256mikz = 19031 + + VPSHUFDZ256ri = 19032 + + VPSHUFDZ256rik = 19033 + + VPSHUFDZ256rikz = 19034 + + VPSHUFDZmbi = 19035 + + VPSHUFDZmbik = 19036 + + VPSHUFDZmbikz = 19037 + + VPSHUFDZmi = 19038 + + VPSHUFDZmik = 19039 + + VPSHUFDZmikz = 19040 + + VPSHUFDZri = 19041 + + VPSHUFDZrik = 19042 + + VPSHUFDZrikz = 19043 + + VPSHUFDmi = 19044 + + VPSHUFDri = 19045 + + VPSHUFHWYmi = 19046 + + VPSHUFHWYri = 19047 + + VPSHUFHWZ128mi = 19048 + + VPSHUFHWZ128mik = 19049 + + VPSHUFHWZ128mikz = 19050 + + VPSHUFHWZ128ri = 19051 + + VPSHUFHWZ128rik = 19052 + + VPSHUFHWZ128rikz = 19053 + + VPSHUFHWZ256mi = 19054 + + VPSHUFHWZ256mik = 19055 + + VPSHUFHWZ256mikz = 19056 + + VPSHUFHWZ256ri = 19057 + + VPSHUFHWZ256rik = 19058 + + VPSHUFHWZ256rikz = 19059 + + VPSHUFHWZmi = 19060 + + VPSHUFHWZmik = 19061 + + VPSHUFHWZmikz = 19062 + + VPSHUFHWZri = 19063 + + VPSHUFHWZrik = 19064 + + VPSHUFHWZrikz = 19065 + + VPSHUFHWmi = 19066 + + VPSHUFHWri = 19067 + + VPSHUFLWYmi = 19068 + + VPSHUFLWYri = 19069 + + VPSHUFLWZ128mi = 19070 + + VPSHUFLWZ128mik = 19071 + + VPSHUFLWZ128mikz = 19072 + + VPSHUFLWZ128ri = 19073 + + VPSHUFLWZ128rik = 19074 + + VPSHUFLWZ128rikz = 19075 + + VPSHUFLWZ256mi = 19076 + + VPSHUFLWZ256mik = 19077 + + VPSHUFLWZ256mikz = 19078 + + VPSHUFLWZ256ri = 19079 + + VPSHUFLWZ256rik = 19080 + + VPSHUFLWZ256rikz = 19081 + + VPSHUFLWZmi = 19082 + + VPSHUFLWZmik = 19083 + + VPSHUFLWZmikz = 19084 + + VPSHUFLWZri = 19085 + + VPSHUFLWZrik = 19086 + + VPSHUFLWZrikz = 19087 + + VPSHUFLWmi = 19088 + + VPSHUFLWri = 19089 + + VPSIGNBYrm = 19090 + + VPSIGNBYrr = 19091 + + VPSIGNBrm = 19092 + + VPSIGNBrr = 19093 + + VPSIGNDYrm = 19094 + + VPSIGNDYrr = 19095 + + VPSIGNDrm = 19096 + + VPSIGNDrr = 19097 + + VPSIGNWYrm = 19098 + + VPSIGNWYrr = 19099 + + VPSIGNWrm = 19100 + + VPSIGNWrr = 19101 + + VPSLLDQYri = 19102 + + VPSLLDQZ128mi = 19103 + + VPSLLDQZ128ri = 19104 + + VPSLLDQZ256mi = 19105 + + VPSLLDQZ256ri = 19106 + + VPSLLDQZmi = 19107 + + VPSLLDQZri = 19108 + + VPSLLDQri = 19109 + + VPSLLDYri = 19110 + + VPSLLDYrm = 19111 + + VPSLLDYrr = 19112 + + VPSLLDZ128mbi = 19113 + + VPSLLDZ128mbik = 19114 + + VPSLLDZ128mbikz = 19115 + + VPSLLDZ128mi = 19116 + + VPSLLDZ128mik = 19117 + + VPSLLDZ128mikz = 19118 + + VPSLLDZ128ri = 19119 + + VPSLLDZ128rik = 19120 + + VPSLLDZ128rikz = 19121 + + VPSLLDZ128rm = 19122 + + VPSLLDZ128rmk = 19123 + + VPSLLDZ128rmkz = 19124 + + VPSLLDZ128rr = 19125 + + VPSLLDZ128rrk = 19126 + + VPSLLDZ128rrkz = 19127 + + VPSLLDZ256mbi = 19128 + + VPSLLDZ256mbik = 19129 + + VPSLLDZ256mbikz = 19130 + + VPSLLDZ256mi = 19131 + + VPSLLDZ256mik = 19132 + + VPSLLDZ256mikz = 19133 + + VPSLLDZ256ri = 19134 + + VPSLLDZ256rik = 19135 + + VPSLLDZ256rikz = 19136 + + VPSLLDZ256rm = 19137 + + VPSLLDZ256rmk = 19138 + + VPSLLDZ256rmkz = 19139 + + VPSLLDZ256rr = 19140 + + VPSLLDZ256rrk = 19141 + + VPSLLDZ256rrkz = 19142 + + VPSLLDZmbi = 19143 + + VPSLLDZmbik = 19144 + + VPSLLDZmbikz = 19145 + + VPSLLDZmi = 19146 + + VPSLLDZmik = 19147 + + VPSLLDZmikz = 19148 + + VPSLLDZri = 19149 + + VPSLLDZrik = 19150 + + VPSLLDZrikz = 19151 + + VPSLLDZrm = 19152 + + VPSLLDZrmk = 19153 + + VPSLLDZrmkz = 19154 + + VPSLLDZrr = 19155 + + VPSLLDZrrk = 19156 + + VPSLLDZrrkz = 19157 + + VPSLLDri = 19158 + + VPSLLDrm = 19159 + + VPSLLDrr = 19160 + + VPSLLQYri = 19161 + + VPSLLQYrm = 19162 + + VPSLLQYrr = 19163 + + VPSLLQZ128mbi = 19164 + + VPSLLQZ128mbik = 19165 + + VPSLLQZ128mbikz = 19166 + + VPSLLQZ128mi = 19167 + + VPSLLQZ128mik = 19168 + + VPSLLQZ128mikz = 19169 + + VPSLLQZ128ri = 19170 + + VPSLLQZ128rik = 19171 + + VPSLLQZ128rikz = 19172 + + VPSLLQZ128rm = 19173 + + VPSLLQZ128rmk = 19174 + + VPSLLQZ128rmkz = 19175 + + VPSLLQZ128rr = 19176 + + VPSLLQZ128rrk = 19177 + + VPSLLQZ128rrkz = 19178 + + VPSLLQZ256mbi = 19179 + + VPSLLQZ256mbik = 19180 + + VPSLLQZ256mbikz = 19181 + + VPSLLQZ256mi = 19182 + + VPSLLQZ256mik = 19183 + + VPSLLQZ256mikz = 19184 + + VPSLLQZ256ri = 19185 + + VPSLLQZ256rik = 19186 + + VPSLLQZ256rikz = 19187 + + VPSLLQZ256rm = 19188 + + VPSLLQZ256rmk = 19189 + + VPSLLQZ256rmkz = 19190 + + VPSLLQZ256rr = 19191 + + VPSLLQZ256rrk = 19192 + + VPSLLQZ256rrkz = 19193 + + VPSLLQZmbi = 19194 + + VPSLLQZmbik = 19195 + + VPSLLQZmbikz = 19196 + + VPSLLQZmi = 19197 + + VPSLLQZmik = 19198 + + VPSLLQZmikz = 19199 + + VPSLLQZri = 19200 + + VPSLLQZrik = 19201 + + VPSLLQZrikz = 19202 + + VPSLLQZrm = 19203 + + VPSLLQZrmk = 19204 + + VPSLLQZrmkz = 19205 + + VPSLLQZrr = 19206 + + VPSLLQZrrk = 19207 + + VPSLLQZrrkz = 19208 + + VPSLLQri = 19209 + + VPSLLQrm = 19210 + + VPSLLQrr = 19211 + + VPSLLVDYrm = 19212 + + VPSLLVDYrr = 19213 + + VPSLLVDZ128rm = 19214 + + VPSLLVDZ128rmb = 19215 + + VPSLLVDZ128rmbk = 19216 + + VPSLLVDZ128rmbkz = 19217 + + VPSLLVDZ128rmk = 19218 + + VPSLLVDZ128rmkz = 19219 + + VPSLLVDZ128rr = 19220 + + VPSLLVDZ128rrk = 19221 + + VPSLLVDZ128rrkz = 19222 + + VPSLLVDZ256rm = 19223 + + VPSLLVDZ256rmb = 19224 + + VPSLLVDZ256rmbk = 19225 + + VPSLLVDZ256rmbkz = 19226 + + VPSLLVDZ256rmk = 19227 + + VPSLLVDZ256rmkz = 19228 + + VPSLLVDZ256rr = 19229 + + VPSLLVDZ256rrk = 19230 + + VPSLLVDZ256rrkz = 19231 + + VPSLLVDZrm = 19232 + + VPSLLVDZrmb = 19233 + + VPSLLVDZrmbk = 19234 + + VPSLLVDZrmbkz = 19235 + + VPSLLVDZrmk = 19236 + + VPSLLVDZrmkz = 19237 + + VPSLLVDZrr = 19238 + + VPSLLVDZrrk = 19239 + + VPSLLVDZrrkz = 19240 + + VPSLLVDrm = 19241 + + VPSLLVDrr = 19242 + + VPSLLVQYrm = 19243 + + VPSLLVQYrr = 19244 + + VPSLLVQZ128rm = 19245 + + VPSLLVQZ128rmb = 19246 + + VPSLLVQZ128rmbk = 19247 + + VPSLLVQZ128rmbkz = 19248 + + VPSLLVQZ128rmk = 19249 + + VPSLLVQZ128rmkz = 19250 + + VPSLLVQZ128rr = 19251 + + VPSLLVQZ128rrk = 19252 + + VPSLLVQZ128rrkz = 19253 + + VPSLLVQZ256rm = 19254 + + VPSLLVQZ256rmb = 19255 + + VPSLLVQZ256rmbk = 19256 + + VPSLLVQZ256rmbkz = 19257 + + VPSLLVQZ256rmk = 19258 + + VPSLLVQZ256rmkz = 19259 + + VPSLLVQZ256rr = 19260 + + VPSLLVQZ256rrk = 19261 + + VPSLLVQZ256rrkz = 19262 + + VPSLLVQZrm = 19263 + + VPSLLVQZrmb = 19264 + + VPSLLVQZrmbk = 19265 + + VPSLLVQZrmbkz = 19266 + + VPSLLVQZrmk = 19267 + + VPSLLVQZrmkz = 19268 + + VPSLLVQZrr = 19269 + + VPSLLVQZrrk = 19270 + + VPSLLVQZrrkz = 19271 + + VPSLLVQrm = 19272 + + VPSLLVQrr = 19273 + + VPSLLVWZ128rm = 19274 + + VPSLLVWZ128rmk = 19275 + + VPSLLVWZ128rmkz = 19276 + + VPSLLVWZ128rr = 19277 + + VPSLLVWZ128rrk = 19278 + + VPSLLVWZ128rrkz = 19279 + + VPSLLVWZ256rm = 19280 + + VPSLLVWZ256rmk = 19281 + + VPSLLVWZ256rmkz = 19282 + + VPSLLVWZ256rr = 19283 + + VPSLLVWZ256rrk = 19284 + + VPSLLVWZ256rrkz = 19285 + + VPSLLVWZrm = 19286 + + VPSLLVWZrmk = 19287 + + VPSLLVWZrmkz = 19288 + + VPSLLVWZrr = 19289 + + VPSLLVWZrrk = 19290 + + VPSLLVWZrrkz = 19291 + + VPSLLWYri = 19292 + + VPSLLWYrm = 19293 + + VPSLLWYrr = 19294 + + VPSLLWZ128mi = 19295 + + VPSLLWZ128mik = 19296 + + VPSLLWZ128mikz = 19297 + + VPSLLWZ128ri = 19298 + + VPSLLWZ128rik = 19299 + + VPSLLWZ128rikz = 19300 + + VPSLLWZ128rm = 19301 + + VPSLLWZ128rmk = 19302 + + VPSLLWZ128rmkz = 19303 + + VPSLLWZ128rr = 19304 + + VPSLLWZ128rrk = 19305 + + VPSLLWZ128rrkz = 19306 + + VPSLLWZ256mi = 19307 + + VPSLLWZ256mik = 19308 + + VPSLLWZ256mikz = 19309 + + VPSLLWZ256ri = 19310 + + VPSLLWZ256rik = 19311 + + VPSLLWZ256rikz = 19312 + + VPSLLWZ256rm = 19313 + + VPSLLWZ256rmk = 19314 + + VPSLLWZ256rmkz = 19315 + + VPSLLWZ256rr = 19316 + + VPSLLWZ256rrk = 19317 + + VPSLLWZ256rrkz = 19318 + + VPSLLWZmi = 19319 + + VPSLLWZmik = 19320 + + VPSLLWZmikz = 19321 + + VPSLLWZri = 19322 + + VPSLLWZrik = 19323 + + VPSLLWZrikz = 19324 + + VPSLLWZrm = 19325 + + VPSLLWZrmk = 19326 + + VPSLLWZrmkz = 19327 + + VPSLLWZrr = 19328 + + VPSLLWZrrk = 19329 + + VPSLLWZrrkz = 19330 + + VPSLLWri = 19331 + + VPSLLWrm = 19332 + + VPSLLWrr = 19333 + + VPSRADYri = 19334 + + VPSRADYrm = 19335 + + VPSRADYrr = 19336 + + VPSRADZ128mbi = 19337 + + VPSRADZ128mbik = 19338 + + VPSRADZ128mbikz = 19339 + + VPSRADZ128mi = 19340 + + VPSRADZ128mik = 19341 + + VPSRADZ128mikz = 19342 + + VPSRADZ128ri = 19343 + + VPSRADZ128rik = 19344 + + VPSRADZ128rikz = 19345 + + VPSRADZ128rm = 19346 + + VPSRADZ128rmk = 19347 + + VPSRADZ128rmkz = 19348 + + VPSRADZ128rr = 19349 + + VPSRADZ128rrk = 19350 + + VPSRADZ128rrkz = 19351 + + VPSRADZ256mbi = 19352 + + VPSRADZ256mbik = 19353 + + VPSRADZ256mbikz = 19354 + + VPSRADZ256mi = 19355 + + VPSRADZ256mik = 19356 + + VPSRADZ256mikz = 19357 + + VPSRADZ256ri = 19358 + + VPSRADZ256rik = 19359 + + VPSRADZ256rikz = 19360 + + VPSRADZ256rm = 19361 + + VPSRADZ256rmk = 19362 + + VPSRADZ256rmkz = 19363 + + VPSRADZ256rr = 19364 + + VPSRADZ256rrk = 19365 + + VPSRADZ256rrkz = 19366 + + VPSRADZmbi = 19367 + + VPSRADZmbik = 19368 + + VPSRADZmbikz = 19369 + + VPSRADZmi = 19370 + + VPSRADZmik = 19371 + + VPSRADZmikz = 19372 + + VPSRADZri = 19373 + + VPSRADZrik = 19374 + + VPSRADZrikz = 19375 + + VPSRADZrm = 19376 + + VPSRADZrmk = 19377 + + VPSRADZrmkz = 19378 + + VPSRADZrr = 19379 + + VPSRADZrrk = 19380 + + VPSRADZrrkz = 19381 + + VPSRADri = 19382 + + VPSRADrm = 19383 + + VPSRADrr = 19384 + + VPSRAQZ128mbi = 19385 + + VPSRAQZ128mbik = 19386 + + VPSRAQZ128mbikz = 19387 + + VPSRAQZ128mi = 19388 + + VPSRAQZ128mik = 19389 + + VPSRAQZ128mikz = 19390 + + VPSRAQZ128ri = 19391 + + VPSRAQZ128rik = 19392 + + VPSRAQZ128rikz = 19393 + + VPSRAQZ128rm = 19394 + + VPSRAQZ128rmk = 19395 + + VPSRAQZ128rmkz = 19396 + + VPSRAQZ128rr = 19397 + + VPSRAQZ128rrk = 19398 + + VPSRAQZ128rrkz = 19399 + + VPSRAQZ256mbi = 19400 + + VPSRAQZ256mbik = 19401 + + VPSRAQZ256mbikz = 19402 + + VPSRAQZ256mi = 19403 + + VPSRAQZ256mik = 19404 + + VPSRAQZ256mikz = 19405 + + VPSRAQZ256ri = 19406 + + VPSRAQZ256rik = 19407 + + VPSRAQZ256rikz = 19408 + + VPSRAQZ256rm = 19409 + + VPSRAQZ256rmk = 19410 + + VPSRAQZ256rmkz = 19411 + + VPSRAQZ256rr = 19412 + + VPSRAQZ256rrk = 19413 + + VPSRAQZ256rrkz = 19414 + + VPSRAQZmbi = 19415 + + VPSRAQZmbik = 19416 + + VPSRAQZmbikz = 19417 + + VPSRAQZmi = 19418 + + VPSRAQZmik = 19419 + + VPSRAQZmikz = 19420 + + VPSRAQZri = 19421 + + VPSRAQZrik = 19422 + + VPSRAQZrikz = 19423 + + VPSRAQZrm = 19424 + + VPSRAQZrmk = 19425 + + VPSRAQZrmkz = 19426 + + VPSRAQZrr = 19427 + + VPSRAQZrrk = 19428 + + VPSRAQZrrkz = 19429 + + VPSRAVDYrm = 19430 + + VPSRAVDYrr = 19431 + + VPSRAVDZ128rm = 19432 + + VPSRAVDZ128rmb = 19433 + + VPSRAVDZ128rmbk = 19434 + + VPSRAVDZ128rmbkz = 19435 + + VPSRAVDZ128rmk = 19436 + + VPSRAVDZ128rmkz = 19437 + + VPSRAVDZ128rr = 19438 + + VPSRAVDZ128rrk = 19439 + + VPSRAVDZ128rrkz = 19440 + + VPSRAVDZ256rm = 19441 + + VPSRAVDZ256rmb = 19442 + + VPSRAVDZ256rmbk = 19443 + + VPSRAVDZ256rmbkz = 19444 + + VPSRAVDZ256rmk = 19445 + + VPSRAVDZ256rmkz = 19446 + + VPSRAVDZ256rr = 19447 + + VPSRAVDZ256rrk = 19448 + + VPSRAVDZ256rrkz = 19449 + + VPSRAVDZrm = 19450 + + VPSRAVDZrmb = 19451 + + VPSRAVDZrmbk = 19452 + + VPSRAVDZrmbkz = 19453 + + VPSRAVDZrmk = 19454 + + VPSRAVDZrmkz = 19455 + + VPSRAVDZrr = 19456 + + VPSRAVDZrrk = 19457 + + VPSRAVDZrrkz = 19458 + + VPSRAVDrm = 19459 + + VPSRAVDrr = 19460 + + VPSRAVQZ128rm = 19461 + + VPSRAVQZ128rmb = 19462 + + VPSRAVQZ128rmbk = 19463 + + VPSRAVQZ128rmbkz = 19464 + + VPSRAVQZ128rmk = 19465 + + VPSRAVQZ128rmkz = 19466 + + VPSRAVQZ128rr = 19467 + + VPSRAVQZ128rrk = 19468 + + VPSRAVQZ128rrkz = 19469 + + VPSRAVQZ256rm = 19470 + + VPSRAVQZ256rmb = 19471 + + VPSRAVQZ256rmbk = 19472 + + VPSRAVQZ256rmbkz = 19473 + + VPSRAVQZ256rmk = 19474 + + VPSRAVQZ256rmkz = 19475 + + VPSRAVQZ256rr = 19476 + + VPSRAVQZ256rrk = 19477 + + VPSRAVQZ256rrkz = 19478 + + VPSRAVQZrm = 19479 + + VPSRAVQZrmb = 19480 + + VPSRAVQZrmbk = 19481 + + VPSRAVQZrmbkz = 19482 + + VPSRAVQZrmk = 19483 + + VPSRAVQZrmkz = 19484 + + VPSRAVQZrr = 19485 + + VPSRAVQZrrk = 19486 + + VPSRAVQZrrkz = 19487 + + VPSRAVWZ128rm = 19488 + + VPSRAVWZ128rmk = 19489 + + VPSRAVWZ128rmkz = 19490 + + VPSRAVWZ128rr = 19491 + + VPSRAVWZ128rrk = 19492 + + VPSRAVWZ128rrkz = 19493 + + VPSRAVWZ256rm = 19494 + + VPSRAVWZ256rmk = 19495 + + VPSRAVWZ256rmkz = 19496 + + VPSRAVWZ256rr = 19497 + + VPSRAVWZ256rrk = 19498 + + VPSRAVWZ256rrkz = 19499 + + VPSRAVWZrm = 19500 + + VPSRAVWZrmk = 19501 + + VPSRAVWZrmkz = 19502 + + VPSRAVWZrr = 19503 + + VPSRAVWZrrk = 19504 + + VPSRAVWZrrkz = 19505 + + VPSRAWYri = 19506 + + VPSRAWYrm = 19507 + + VPSRAWYrr = 19508 + + VPSRAWZ128mi = 19509 + + VPSRAWZ128mik = 19510 + + VPSRAWZ128mikz = 19511 + + VPSRAWZ128ri = 19512 + + VPSRAWZ128rik = 19513 + + VPSRAWZ128rikz = 19514 + + VPSRAWZ128rm = 19515 + + VPSRAWZ128rmk = 19516 + + VPSRAWZ128rmkz = 19517 + + VPSRAWZ128rr = 19518 + + VPSRAWZ128rrk = 19519 + + VPSRAWZ128rrkz = 19520 + + VPSRAWZ256mi = 19521 + + VPSRAWZ256mik = 19522 + + VPSRAWZ256mikz = 19523 + + VPSRAWZ256ri = 19524 + + VPSRAWZ256rik = 19525 + + VPSRAWZ256rikz = 19526 + + VPSRAWZ256rm = 19527 + + VPSRAWZ256rmk = 19528 + + VPSRAWZ256rmkz = 19529 + + VPSRAWZ256rr = 19530 + + VPSRAWZ256rrk = 19531 + + VPSRAWZ256rrkz = 19532 + + VPSRAWZmi = 19533 + + VPSRAWZmik = 19534 + + VPSRAWZmikz = 19535 + + VPSRAWZri = 19536 + + VPSRAWZrik = 19537 + + VPSRAWZrikz = 19538 + + VPSRAWZrm = 19539 + + VPSRAWZrmk = 19540 + + VPSRAWZrmkz = 19541 + + VPSRAWZrr = 19542 + + VPSRAWZrrk = 19543 + + VPSRAWZrrkz = 19544 + + VPSRAWri = 19545 + + VPSRAWrm = 19546 + + VPSRAWrr = 19547 + + VPSRLDQYri = 19548 + + VPSRLDQZ128mi = 19549 + + VPSRLDQZ128ri = 19550 + + VPSRLDQZ256mi = 19551 + + VPSRLDQZ256ri = 19552 + + VPSRLDQZmi = 19553 + + VPSRLDQZri = 19554 + + VPSRLDQri = 19555 + + VPSRLDYri = 19556 + + VPSRLDYrm = 19557 + + VPSRLDYrr = 19558 + + VPSRLDZ128mbi = 19559 + + VPSRLDZ128mbik = 19560 + + VPSRLDZ128mbikz = 19561 + + VPSRLDZ128mi = 19562 + + VPSRLDZ128mik = 19563 + + VPSRLDZ128mikz = 19564 + + VPSRLDZ128ri = 19565 + + VPSRLDZ128rik = 19566 + + VPSRLDZ128rikz = 19567 + + VPSRLDZ128rm = 19568 + + VPSRLDZ128rmk = 19569 + + VPSRLDZ128rmkz = 19570 + + VPSRLDZ128rr = 19571 + + VPSRLDZ128rrk = 19572 + + VPSRLDZ128rrkz = 19573 + + VPSRLDZ256mbi = 19574 + + VPSRLDZ256mbik = 19575 + + VPSRLDZ256mbikz = 19576 + + VPSRLDZ256mi = 19577 + + VPSRLDZ256mik = 19578 + + VPSRLDZ256mikz = 19579 + + VPSRLDZ256ri = 19580 + + VPSRLDZ256rik = 19581 + + VPSRLDZ256rikz = 19582 + + VPSRLDZ256rm = 19583 + + VPSRLDZ256rmk = 19584 + + VPSRLDZ256rmkz = 19585 + + VPSRLDZ256rr = 19586 + + VPSRLDZ256rrk = 19587 + + VPSRLDZ256rrkz = 19588 + + VPSRLDZmbi = 19589 + + VPSRLDZmbik = 19590 + + VPSRLDZmbikz = 19591 + + VPSRLDZmi = 19592 + + VPSRLDZmik = 19593 + + VPSRLDZmikz = 19594 + + VPSRLDZri = 19595 + + VPSRLDZrik = 19596 + + VPSRLDZrikz = 19597 + + VPSRLDZrm = 19598 + + VPSRLDZrmk = 19599 + + VPSRLDZrmkz = 19600 + + VPSRLDZrr = 19601 + + VPSRLDZrrk = 19602 + + VPSRLDZrrkz = 19603 + + VPSRLDri = 19604 + + VPSRLDrm = 19605 + + VPSRLDrr = 19606 + + VPSRLQYri = 19607 + + VPSRLQYrm = 19608 + + VPSRLQYrr = 19609 + + VPSRLQZ128mbi = 19610 + + VPSRLQZ128mbik = 19611 + + VPSRLQZ128mbikz = 19612 + + VPSRLQZ128mi = 19613 + + VPSRLQZ128mik = 19614 + + VPSRLQZ128mikz = 19615 + + VPSRLQZ128ri = 19616 + + VPSRLQZ128rik = 19617 + + VPSRLQZ128rikz = 19618 + + VPSRLQZ128rm = 19619 + + VPSRLQZ128rmk = 19620 + + VPSRLQZ128rmkz = 19621 + + VPSRLQZ128rr = 19622 + + VPSRLQZ128rrk = 19623 + + VPSRLQZ128rrkz = 19624 + + VPSRLQZ256mbi = 19625 + + VPSRLQZ256mbik = 19626 + + VPSRLQZ256mbikz = 19627 + + VPSRLQZ256mi = 19628 + + VPSRLQZ256mik = 19629 + + VPSRLQZ256mikz = 19630 + + VPSRLQZ256ri = 19631 + + VPSRLQZ256rik = 19632 + + VPSRLQZ256rikz = 19633 + + VPSRLQZ256rm = 19634 + + VPSRLQZ256rmk = 19635 + + VPSRLQZ256rmkz = 19636 + + VPSRLQZ256rr = 19637 + + VPSRLQZ256rrk = 19638 + + VPSRLQZ256rrkz = 19639 + + VPSRLQZmbi = 19640 + + VPSRLQZmbik = 19641 + + VPSRLQZmbikz = 19642 + + VPSRLQZmi = 19643 + + VPSRLQZmik = 19644 + + VPSRLQZmikz = 19645 + + VPSRLQZri = 19646 + + VPSRLQZrik = 19647 + + VPSRLQZrikz = 19648 + + VPSRLQZrm = 19649 + + VPSRLQZrmk = 19650 + + VPSRLQZrmkz = 19651 + + VPSRLQZrr = 19652 + + VPSRLQZrrk = 19653 + + VPSRLQZrrkz = 19654 + + VPSRLQri = 19655 + + VPSRLQrm = 19656 + + VPSRLQrr = 19657 + + VPSRLVDYrm = 19658 + + VPSRLVDYrr = 19659 + + VPSRLVDZ128rm = 19660 + + VPSRLVDZ128rmb = 19661 + + VPSRLVDZ128rmbk = 19662 + + VPSRLVDZ128rmbkz = 19663 + + VPSRLVDZ128rmk = 19664 + + VPSRLVDZ128rmkz = 19665 + + VPSRLVDZ128rr = 19666 + + VPSRLVDZ128rrk = 19667 + + VPSRLVDZ128rrkz = 19668 + + VPSRLVDZ256rm = 19669 + + VPSRLVDZ256rmb = 19670 + + VPSRLVDZ256rmbk = 19671 + + VPSRLVDZ256rmbkz = 19672 + + VPSRLVDZ256rmk = 19673 + + VPSRLVDZ256rmkz = 19674 + + VPSRLVDZ256rr = 19675 + + VPSRLVDZ256rrk = 19676 + + VPSRLVDZ256rrkz = 19677 + + VPSRLVDZrm = 19678 + + VPSRLVDZrmb = 19679 + + VPSRLVDZrmbk = 19680 + + VPSRLVDZrmbkz = 19681 + + VPSRLVDZrmk = 19682 + + VPSRLVDZrmkz = 19683 + + VPSRLVDZrr = 19684 + + VPSRLVDZrrk = 19685 + + VPSRLVDZrrkz = 19686 + + VPSRLVDrm = 19687 + + VPSRLVDrr = 19688 + + VPSRLVQYrm = 19689 + + VPSRLVQYrr = 19690 + + VPSRLVQZ128rm = 19691 + + VPSRLVQZ128rmb = 19692 + + VPSRLVQZ128rmbk = 19693 + + VPSRLVQZ128rmbkz = 19694 + + VPSRLVQZ128rmk = 19695 + + VPSRLVQZ128rmkz = 19696 + + VPSRLVQZ128rr = 19697 + + VPSRLVQZ128rrk = 19698 + + VPSRLVQZ128rrkz = 19699 + + VPSRLVQZ256rm = 19700 + + VPSRLVQZ256rmb = 19701 + + VPSRLVQZ256rmbk = 19702 + + VPSRLVQZ256rmbkz = 19703 + + VPSRLVQZ256rmk = 19704 + + VPSRLVQZ256rmkz = 19705 + + VPSRLVQZ256rr = 19706 + + VPSRLVQZ256rrk = 19707 + + VPSRLVQZ256rrkz = 19708 + + VPSRLVQZrm = 19709 + + VPSRLVQZrmb = 19710 + + VPSRLVQZrmbk = 19711 + + VPSRLVQZrmbkz = 19712 + + VPSRLVQZrmk = 19713 + + VPSRLVQZrmkz = 19714 + + VPSRLVQZrr = 19715 + + VPSRLVQZrrk = 19716 + + VPSRLVQZrrkz = 19717 + + VPSRLVQrm = 19718 + + VPSRLVQrr = 19719 + + VPSRLVWZ128rm = 19720 + + VPSRLVWZ128rmk = 19721 + + VPSRLVWZ128rmkz = 19722 + + VPSRLVWZ128rr = 19723 + + VPSRLVWZ128rrk = 19724 + + VPSRLVWZ128rrkz = 19725 + + VPSRLVWZ256rm = 19726 + + VPSRLVWZ256rmk = 19727 + + VPSRLVWZ256rmkz = 19728 + + VPSRLVWZ256rr = 19729 + + VPSRLVWZ256rrk = 19730 + + VPSRLVWZ256rrkz = 19731 + + VPSRLVWZrm = 19732 + + VPSRLVWZrmk = 19733 + + VPSRLVWZrmkz = 19734 + + VPSRLVWZrr = 19735 + + VPSRLVWZrrk = 19736 + + VPSRLVWZrrkz = 19737 + + VPSRLWYri = 19738 + + VPSRLWYrm = 19739 + + VPSRLWYrr = 19740 + + VPSRLWZ128mi = 19741 + + VPSRLWZ128mik = 19742 + + VPSRLWZ128mikz = 19743 + + VPSRLWZ128ri = 19744 + + VPSRLWZ128rik = 19745 + + VPSRLWZ128rikz = 19746 + + VPSRLWZ128rm = 19747 + + VPSRLWZ128rmk = 19748 + + VPSRLWZ128rmkz = 19749 + + VPSRLWZ128rr = 19750 + + VPSRLWZ128rrk = 19751 + + VPSRLWZ128rrkz = 19752 + + VPSRLWZ256mi = 19753 + + VPSRLWZ256mik = 19754 + + VPSRLWZ256mikz = 19755 + + VPSRLWZ256ri = 19756 + + VPSRLWZ256rik = 19757 + + VPSRLWZ256rikz = 19758 + + VPSRLWZ256rm = 19759 + + VPSRLWZ256rmk = 19760 + + VPSRLWZ256rmkz = 19761 + + VPSRLWZ256rr = 19762 + + VPSRLWZ256rrk = 19763 + + VPSRLWZ256rrkz = 19764 + + VPSRLWZmi = 19765 + + VPSRLWZmik = 19766 + + VPSRLWZmikz = 19767 + + VPSRLWZri = 19768 + + VPSRLWZrik = 19769 + + VPSRLWZrikz = 19770 + + VPSRLWZrm = 19771 + + VPSRLWZrmk = 19772 + + VPSRLWZrmkz = 19773 + + VPSRLWZrr = 19774 + + VPSRLWZrrk = 19775 + + VPSRLWZrrkz = 19776 + + VPSRLWri = 19777 + + VPSRLWrm = 19778 + + VPSRLWrr = 19779 + + VPSUBBYrm = 19780 + + VPSUBBYrr = 19781 + + VPSUBBZ128rm = 19782 + + VPSUBBZ128rmk = 19783 + + VPSUBBZ128rmkz = 19784 + + VPSUBBZ128rr = 19785 + + VPSUBBZ128rrk = 19786 + + VPSUBBZ128rrkz = 19787 + + VPSUBBZ256rm = 19788 + + VPSUBBZ256rmk = 19789 + + VPSUBBZ256rmkz = 19790 + + VPSUBBZ256rr = 19791 + + VPSUBBZ256rrk = 19792 + + VPSUBBZ256rrkz = 19793 + + VPSUBBZrm = 19794 + + VPSUBBZrmk = 19795 + + VPSUBBZrmkz = 19796 + + VPSUBBZrr = 19797 + + VPSUBBZrrk = 19798 + + VPSUBBZrrkz = 19799 + + VPSUBBrm = 19800 + + VPSUBBrr = 19801 + + VPSUBDYrm = 19802 + + VPSUBDYrr = 19803 + + VPSUBDZ128rm = 19804 + + VPSUBDZ128rmb = 19805 + + VPSUBDZ128rmbk = 19806 + + VPSUBDZ128rmbkz = 19807 + + VPSUBDZ128rmk = 19808 + + VPSUBDZ128rmkz = 19809 + + VPSUBDZ128rr = 19810 + + VPSUBDZ128rrk = 19811 + + VPSUBDZ128rrkz = 19812 + + VPSUBDZ256rm = 19813 + + VPSUBDZ256rmb = 19814 + + VPSUBDZ256rmbk = 19815 + + VPSUBDZ256rmbkz = 19816 + + VPSUBDZ256rmk = 19817 + + VPSUBDZ256rmkz = 19818 + + VPSUBDZ256rr = 19819 + + VPSUBDZ256rrk = 19820 + + VPSUBDZ256rrkz = 19821 + + VPSUBDZrm = 19822 + + VPSUBDZrmb = 19823 + + VPSUBDZrmbk = 19824 + + VPSUBDZrmbkz = 19825 + + VPSUBDZrmk = 19826 + + VPSUBDZrmkz = 19827 + + VPSUBDZrr = 19828 + + VPSUBDZrrk = 19829 + + VPSUBDZrrkz = 19830 + + VPSUBDrm = 19831 + + VPSUBDrr = 19832 + + VPSUBQYrm = 19833 + + VPSUBQYrr = 19834 + + VPSUBQZ128rm = 19835 + + VPSUBQZ128rmb = 19836 + + VPSUBQZ128rmbk = 19837 + + VPSUBQZ128rmbkz = 19838 + + VPSUBQZ128rmk = 19839 + + VPSUBQZ128rmkz = 19840 + + VPSUBQZ128rr = 19841 + + VPSUBQZ128rrk = 19842 + + VPSUBQZ128rrkz = 19843 + + VPSUBQZ256rm = 19844 + + VPSUBQZ256rmb = 19845 + + VPSUBQZ256rmbk = 19846 + + VPSUBQZ256rmbkz = 19847 + + VPSUBQZ256rmk = 19848 + + VPSUBQZ256rmkz = 19849 + + VPSUBQZ256rr = 19850 + + VPSUBQZ256rrk = 19851 + + VPSUBQZ256rrkz = 19852 + + VPSUBQZrm = 19853 + + VPSUBQZrmb = 19854 + + VPSUBQZrmbk = 19855 + + VPSUBQZrmbkz = 19856 + + VPSUBQZrmk = 19857 + + VPSUBQZrmkz = 19858 + + VPSUBQZrr = 19859 + + VPSUBQZrrk = 19860 + + VPSUBQZrrkz = 19861 + + VPSUBQrm = 19862 + + VPSUBQrr = 19863 + + VPSUBSBYrm = 19864 + + VPSUBSBYrr = 19865 + + VPSUBSBZ128rm = 19866 + + VPSUBSBZ128rmk = 19867 + + VPSUBSBZ128rmkz = 19868 + + VPSUBSBZ128rr = 19869 + + VPSUBSBZ128rrk = 19870 + + VPSUBSBZ128rrkz = 19871 + + VPSUBSBZ256rm = 19872 + + VPSUBSBZ256rmk = 19873 + + VPSUBSBZ256rmkz = 19874 + + VPSUBSBZ256rr = 19875 + + VPSUBSBZ256rrk = 19876 + + VPSUBSBZ256rrkz = 19877 + + VPSUBSBZrm = 19878 + + VPSUBSBZrmk = 19879 + + VPSUBSBZrmkz = 19880 + + VPSUBSBZrr = 19881 + + VPSUBSBZrrk = 19882 + + VPSUBSBZrrkz = 19883 + + VPSUBSBrm = 19884 + + VPSUBSBrr = 19885 + + VPSUBSWYrm = 19886 + + VPSUBSWYrr = 19887 + + VPSUBSWZ128rm = 19888 + + VPSUBSWZ128rmk = 19889 + + VPSUBSWZ128rmkz = 19890 + + VPSUBSWZ128rr = 19891 + + VPSUBSWZ128rrk = 19892 + + VPSUBSWZ128rrkz = 19893 + + VPSUBSWZ256rm = 19894 + + VPSUBSWZ256rmk = 19895 + + VPSUBSWZ256rmkz = 19896 + + VPSUBSWZ256rr = 19897 + + VPSUBSWZ256rrk = 19898 + + VPSUBSWZ256rrkz = 19899 + + VPSUBSWZrm = 19900 + + VPSUBSWZrmk = 19901 + + VPSUBSWZrmkz = 19902 + + VPSUBSWZrr = 19903 + + VPSUBSWZrrk = 19904 + + VPSUBSWZrrkz = 19905 + + VPSUBSWrm = 19906 + + VPSUBSWrr = 19907 + + VPSUBUSBYrm = 19908 + + VPSUBUSBYrr = 19909 + + VPSUBUSBZ128rm = 19910 + + VPSUBUSBZ128rmk = 19911 + + VPSUBUSBZ128rmkz = 19912 + + VPSUBUSBZ128rr = 19913 + + VPSUBUSBZ128rrk = 19914 + + VPSUBUSBZ128rrkz = 19915 + + VPSUBUSBZ256rm = 19916 + + VPSUBUSBZ256rmk = 19917 + + VPSUBUSBZ256rmkz = 19918 + + VPSUBUSBZ256rr = 19919 + + VPSUBUSBZ256rrk = 19920 + + VPSUBUSBZ256rrkz = 19921 + + VPSUBUSBZrm = 19922 + + VPSUBUSBZrmk = 19923 + + VPSUBUSBZrmkz = 19924 + + VPSUBUSBZrr = 19925 + + VPSUBUSBZrrk = 19926 + + VPSUBUSBZrrkz = 19927 + + VPSUBUSBrm = 19928 + + VPSUBUSBrr = 19929 + + VPSUBUSWYrm = 19930 + + VPSUBUSWYrr = 19931 + + VPSUBUSWZ128rm = 19932 + + VPSUBUSWZ128rmk = 19933 + + VPSUBUSWZ128rmkz = 19934 + + VPSUBUSWZ128rr = 19935 + + VPSUBUSWZ128rrk = 19936 + + VPSUBUSWZ128rrkz = 19937 + + VPSUBUSWZ256rm = 19938 + + VPSUBUSWZ256rmk = 19939 + + VPSUBUSWZ256rmkz = 19940 + + VPSUBUSWZ256rr = 19941 + + VPSUBUSWZ256rrk = 19942 + + VPSUBUSWZ256rrkz = 19943 + + VPSUBUSWZrm = 19944 + + VPSUBUSWZrmk = 19945 + + VPSUBUSWZrmkz = 19946 + + VPSUBUSWZrr = 19947 + + VPSUBUSWZrrk = 19948 + + VPSUBUSWZrrkz = 19949 + + VPSUBUSWrm = 19950 + + VPSUBUSWrr = 19951 + + VPSUBWYrm = 19952 + + VPSUBWYrr = 19953 + + VPSUBWZ128rm = 19954 + + VPSUBWZ128rmk = 19955 + + VPSUBWZ128rmkz = 19956 + + VPSUBWZ128rr = 19957 + + VPSUBWZ128rrk = 19958 + + VPSUBWZ128rrkz = 19959 + + VPSUBWZ256rm = 19960 + + VPSUBWZ256rmk = 19961 + + VPSUBWZ256rmkz = 19962 + + VPSUBWZ256rr = 19963 + + VPSUBWZ256rrk = 19964 + + VPSUBWZ256rrkz = 19965 + + VPSUBWZrm = 19966 + + VPSUBWZrmk = 19967 + + VPSUBWZrmkz = 19968 + + VPSUBWZrr = 19969 + + VPSUBWZrrk = 19970 + + VPSUBWZrrkz = 19971 + + VPSUBWrm = 19972 + + VPSUBWrr = 19973 + + VPTERNLOGDZ128rmbi = 19974 + + VPTERNLOGDZ128rmbik = 19975 + + VPTERNLOGDZ128rmbikz = 19976 + + VPTERNLOGDZ128rmi = 19977 + + VPTERNLOGDZ128rmik = 19978 + + VPTERNLOGDZ128rmikz = 19979 + + VPTERNLOGDZ128rri = 19980 + + VPTERNLOGDZ128rrik = 19981 + + VPTERNLOGDZ128rrikz = 19982 + + VPTERNLOGDZ256rmbi = 19983 + + VPTERNLOGDZ256rmbik = 19984 + + VPTERNLOGDZ256rmbikz = 19985 + + VPTERNLOGDZ256rmi = 19986 + + VPTERNLOGDZ256rmik = 19987 + + VPTERNLOGDZ256rmikz = 19988 + + VPTERNLOGDZ256rri = 19989 + + VPTERNLOGDZ256rrik = 19990 + + VPTERNLOGDZ256rrikz = 19991 + + VPTERNLOGDZrmbi = 19992 + + VPTERNLOGDZrmbik = 19993 + + VPTERNLOGDZrmbikz = 19994 + + VPTERNLOGDZrmi = 19995 + + VPTERNLOGDZrmik = 19996 + + VPTERNLOGDZrmikz = 19997 + + VPTERNLOGDZrri = 19998 + + VPTERNLOGDZrrik = 19999 + + VPTERNLOGDZrrikz = 20000 + + VPTERNLOGQZ128rmbi = 20001 + + VPTERNLOGQZ128rmbik = 20002 + + VPTERNLOGQZ128rmbikz = 20003 + + VPTERNLOGQZ128rmi = 20004 + + VPTERNLOGQZ128rmik = 20005 + + VPTERNLOGQZ128rmikz = 20006 + + VPTERNLOGQZ128rri = 20007 + + VPTERNLOGQZ128rrik = 20008 + + VPTERNLOGQZ128rrikz = 20009 + + VPTERNLOGQZ256rmbi = 20010 + + VPTERNLOGQZ256rmbik = 20011 + + VPTERNLOGQZ256rmbikz = 20012 + + VPTERNLOGQZ256rmi = 20013 + + VPTERNLOGQZ256rmik = 20014 + + VPTERNLOGQZ256rmikz = 20015 + + VPTERNLOGQZ256rri = 20016 + + VPTERNLOGQZ256rrik = 20017 + + VPTERNLOGQZ256rrikz = 20018 + + VPTERNLOGQZrmbi = 20019 + + VPTERNLOGQZrmbik = 20020 + + VPTERNLOGQZrmbikz = 20021 + + VPTERNLOGQZrmi = 20022 + + VPTERNLOGQZrmik = 20023 + + VPTERNLOGQZrmikz = 20024 + + VPTERNLOGQZrri = 20025 + + VPTERNLOGQZrrik = 20026 + + VPTERNLOGQZrrikz = 20027 + + VPTESTMBZ128rm = 20028 + + VPTESTMBZ128rmk = 20029 + + VPTESTMBZ128rr = 20030 + + VPTESTMBZ128rrk = 20031 + + VPTESTMBZ256rm = 20032 + + VPTESTMBZ256rmk = 20033 + + VPTESTMBZ256rr = 20034 + + VPTESTMBZ256rrk = 20035 + + VPTESTMBZrm = 20036 + + VPTESTMBZrmk = 20037 + + VPTESTMBZrr = 20038 + + VPTESTMBZrrk = 20039 + + VPTESTMDZ128rm = 20040 + + VPTESTMDZ128rmb = 20041 + + VPTESTMDZ128rmbk = 20042 + + VPTESTMDZ128rmk = 20043 + + VPTESTMDZ128rr = 20044 + + VPTESTMDZ128rrk = 20045 + + VPTESTMDZ256rm = 20046 + + VPTESTMDZ256rmb = 20047 + + VPTESTMDZ256rmbk = 20048 + + VPTESTMDZ256rmk = 20049 + + VPTESTMDZ256rr = 20050 + + VPTESTMDZ256rrk = 20051 + + VPTESTMDZrm = 20052 + + VPTESTMDZrmb = 20053 + + VPTESTMDZrmbk = 20054 + + VPTESTMDZrmk = 20055 + + VPTESTMDZrr = 20056 + + VPTESTMDZrrk = 20057 + + VPTESTMQZ128rm = 20058 + + VPTESTMQZ128rmb = 20059 + + VPTESTMQZ128rmbk = 20060 + + VPTESTMQZ128rmk = 20061 + + VPTESTMQZ128rr = 20062 + + VPTESTMQZ128rrk = 20063 + + VPTESTMQZ256rm = 20064 + + VPTESTMQZ256rmb = 20065 + + VPTESTMQZ256rmbk = 20066 + + VPTESTMQZ256rmk = 20067 + + VPTESTMQZ256rr = 20068 + + VPTESTMQZ256rrk = 20069 + + VPTESTMQZrm = 20070 + + VPTESTMQZrmb = 20071 + + VPTESTMQZrmbk = 20072 + + VPTESTMQZrmk = 20073 + + VPTESTMQZrr = 20074 + + VPTESTMQZrrk = 20075 + + VPTESTMWZ128rm = 20076 + + VPTESTMWZ128rmk = 20077 + + VPTESTMWZ128rr = 20078 + + VPTESTMWZ128rrk = 20079 + + VPTESTMWZ256rm = 20080 + + VPTESTMWZ256rmk = 20081 + + VPTESTMWZ256rr = 20082 + + VPTESTMWZ256rrk = 20083 + + VPTESTMWZrm = 20084 + + VPTESTMWZrmk = 20085 + + VPTESTMWZrr = 20086 + + VPTESTMWZrrk = 20087 + + VPTESTNMBZ128rm = 20088 + + VPTESTNMBZ128rmk = 20089 + + VPTESTNMBZ128rr = 20090 + + VPTESTNMBZ128rrk = 20091 + + VPTESTNMBZ256rm = 20092 + + VPTESTNMBZ256rmk = 20093 + + VPTESTNMBZ256rr = 20094 + + VPTESTNMBZ256rrk = 20095 + + VPTESTNMBZrm = 20096 + + VPTESTNMBZrmk = 20097 + + VPTESTNMBZrr = 20098 + + VPTESTNMBZrrk = 20099 + + VPTESTNMDZ128rm = 20100 + + VPTESTNMDZ128rmb = 20101 + + VPTESTNMDZ128rmbk = 20102 + + VPTESTNMDZ128rmk = 20103 + + VPTESTNMDZ128rr = 20104 + + VPTESTNMDZ128rrk = 20105 + + VPTESTNMDZ256rm = 20106 + + VPTESTNMDZ256rmb = 20107 + + VPTESTNMDZ256rmbk = 20108 + + VPTESTNMDZ256rmk = 20109 + + VPTESTNMDZ256rr = 20110 + + VPTESTNMDZ256rrk = 20111 + + VPTESTNMDZrm = 20112 + + VPTESTNMDZrmb = 20113 + + VPTESTNMDZrmbk = 20114 + + VPTESTNMDZrmk = 20115 + + VPTESTNMDZrr = 20116 + + VPTESTNMDZrrk = 20117 + + VPTESTNMQZ128rm = 20118 + + VPTESTNMQZ128rmb = 20119 + + VPTESTNMQZ128rmbk = 20120 + + VPTESTNMQZ128rmk = 20121 + + VPTESTNMQZ128rr = 20122 + + VPTESTNMQZ128rrk = 20123 + + VPTESTNMQZ256rm = 20124 + + VPTESTNMQZ256rmb = 20125 + + VPTESTNMQZ256rmbk = 20126 + + VPTESTNMQZ256rmk = 20127 + + VPTESTNMQZ256rr = 20128 + + VPTESTNMQZ256rrk = 20129 + + VPTESTNMQZrm = 20130 + + VPTESTNMQZrmb = 20131 + + VPTESTNMQZrmbk = 20132 + + VPTESTNMQZrmk = 20133 + + VPTESTNMQZrr = 20134 + + VPTESTNMQZrrk = 20135 + + VPTESTNMWZ128rm = 20136 + + VPTESTNMWZ128rmk = 20137 + + VPTESTNMWZ128rr = 20138 + + VPTESTNMWZ128rrk = 20139 + + VPTESTNMWZ256rm = 20140 + + VPTESTNMWZ256rmk = 20141 + + VPTESTNMWZ256rr = 20142 + + VPTESTNMWZ256rrk = 20143 + + VPTESTNMWZrm = 20144 + + VPTESTNMWZrmk = 20145 + + VPTESTNMWZrr = 20146 + + VPTESTNMWZrrk = 20147 + + VPTESTYrm = 20148 + + VPTESTYrr = 20149 + + VPTESTrm = 20150 + + VPTESTrr = 20151 + + VPUNPCKHBWYrm = 20152 + + VPUNPCKHBWYrr = 20153 + + VPUNPCKHBWZ128rm = 20154 + + VPUNPCKHBWZ128rmk = 20155 + + VPUNPCKHBWZ128rmkz = 20156 + + VPUNPCKHBWZ128rr = 20157 + + VPUNPCKHBWZ128rrk = 20158 + + VPUNPCKHBWZ128rrkz = 20159 + + VPUNPCKHBWZ256rm = 20160 + + VPUNPCKHBWZ256rmk = 20161 + + VPUNPCKHBWZ256rmkz = 20162 + + VPUNPCKHBWZ256rr = 20163 + + VPUNPCKHBWZ256rrk = 20164 + + VPUNPCKHBWZ256rrkz = 20165 + + VPUNPCKHBWZrm = 20166 + + VPUNPCKHBWZrmk = 20167 + + VPUNPCKHBWZrmkz = 20168 + + VPUNPCKHBWZrr = 20169 + + VPUNPCKHBWZrrk = 20170 + + VPUNPCKHBWZrrkz = 20171 + + VPUNPCKHBWrm = 20172 + + VPUNPCKHBWrr = 20173 + + VPUNPCKHDQYrm = 20174 + + VPUNPCKHDQYrr = 20175 + + VPUNPCKHDQZ128rm = 20176 + + VPUNPCKHDQZ128rmb = 20177 + + VPUNPCKHDQZ128rmbk = 20178 + + VPUNPCKHDQZ128rmbkz = 20179 + + VPUNPCKHDQZ128rmk = 20180 + + VPUNPCKHDQZ128rmkz = 20181 + + VPUNPCKHDQZ128rr = 20182 + + VPUNPCKHDQZ128rrk = 20183 + + VPUNPCKHDQZ128rrkz = 20184 + + VPUNPCKHDQZ256rm = 20185 + + VPUNPCKHDQZ256rmb = 20186 + + VPUNPCKHDQZ256rmbk = 20187 + + VPUNPCKHDQZ256rmbkz = 20188 + + VPUNPCKHDQZ256rmk = 20189 + + VPUNPCKHDQZ256rmkz = 20190 + + VPUNPCKHDQZ256rr = 20191 + + VPUNPCKHDQZ256rrk = 20192 + + VPUNPCKHDQZ256rrkz = 20193 + + VPUNPCKHDQZrm = 20194 + + VPUNPCKHDQZrmb = 20195 + + VPUNPCKHDQZrmbk = 20196 + + VPUNPCKHDQZrmbkz = 20197 + + VPUNPCKHDQZrmk = 20198 + + VPUNPCKHDQZrmkz = 20199 + + VPUNPCKHDQZrr = 20200 + + VPUNPCKHDQZrrk = 20201 + + VPUNPCKHDQZrrkz = 20202 + + VPUNPCKHDQrm = 20203 + + VPUNPCKHDQrr = 20204 + + VPUNPCKHQDQYrm = 20205 + + VPUNPCKHQDQYrr = 20206 + + VPUNPCKHQDQZ128rm = 20207 + + VPUNPCKHQDQZ128rmb = 20208 + + VPUNPCKHQDQZ128rmbk = 20209 + + VPUNPCKHQDQZ128rmbkz = 20210 + + VPUNPCKHQDQZ128rmk = 20211 + + VPUNPCKHQDQZ128rmkz = 20212 + + VPUNPCKHQDQZ128rr = 20213 + + VPUNPCKHQDQZ128rrk = 20214 + + VPUNPCKHQDQZ128rrkz = 20215 + + VPUNPCKHQDQZ256rm = 20216 + + VPUNPCKHQDQZ256rmb = 20217 + + VPUNPCKHQDQZ256rmbk = 20218 + + VPUNPCKHQDQZ256rmbkz = 20219 + + VPUNPCKHQDQZ256rmk = 20220 + + VPUNPCKHQDQZ256rmkz = 20221 + + VPUNPCKHQDQZ256rr = 20222 + + VPUNPCKHQDQZ256rrk = 20223 + + VPUNPCKHQDQZ256rrkz = 20224 + + VPUNPCKHQDQZrm = 20225 + + VPUNPCKHQDQZrmb = 20226 + + VPUNPCKHQDQZrmbk = 20227 + + VPUNPCKHQDQZrmbkz = 20228 + + VPUNPCKHQDQZrmk = 20229 + + VPUNPCKHQDQZrmkz = 20230 + + VPUNPCKHQDQZrr = 20231 + + VPUNPCKHQDQZrrk = 20232 + + VPUNPCKHQDQZrrkz = 20233 + + VPUNPCKHQDQrm = 20234 + + VPUNPCKHQDQrr = 20235 + + VPUNPCKHWDYrm = 20236 + + VPUNPCKHWDYrr = 20237 + + VPUNPCKHWDZ128rm = 20238 + + VPUNPCKHWDZ128rmk = 20239 + + VPUNPCKHWDZ128rmkz = 20240 + + VPUNPCKHWDZ128rr = 20241 + + VPUNPCKHWDZ128rrk = 20242 + + VPUNPCKHWDZ128rrkz = 20243 + + VPUNPCKHWDZ256rm = 20244 + + VPUNPCKHWDZ256rmk = 20245 + + VPUNPCKHWDZ256rmkz = 20246 + + VPUNPCKHWDZ256rr = 20247 + + VPUNPCKHWDZ256rrk = 20248 + + VPUNPCKHWDZ256rrkz = 20249 + + VPUNPCKHWDZrm = 20250 + + VPUNPCKHWDZrmk = 20251 + + VPUNPCKHWDZrmkz = 20252 + + VPUNPCKHWDZrr = 20253 + + VPUNPCKHWDZrrk = 20254 + + VPUNPCKHWDZrrkz = 20255 + + VPUNPCKHWDrm = 20256 + + VPUNPCKHWDrr = 20257 + + VPUNPCKLBWYrm = 20258 + + VPUNPCKLBWYrr = 20259 + + VPUNPCKLBWZ128rm = 20260 + + VPUNPCKLBWZ128rmk = 20261 + + VPUNPCKLBWZ128rmkz = 20262 + + VPUNPCKLBWZ128rr = 20263 + + VPUNPCKLBWZ128rrk = 20264 + + VPUNPCKLBWZ128rrkz = 20265 + + VPUNPCKLBWZ256rm = 20266 + + VPUNPCKLBWZ256rmk = 20267 + + VPUNPCKLBWZ256rmkz = 20268 + + VPUNPCKLBWZ256rr = 20269 + + VPUNPCKLBWZ256rrk = 20270 + + VPUNPCKLBWZ256rrkz = 20271 + + VPUNPCKLBWZrm = 20272 + + VPUNPCKLBWZrmk = 20273 + + VPUNPCKLBWZrmkz = 20274 + + VPUNPCKLBWZrr = 20275 + + VPUNPCKLBWZrrk = 20276 + + VPUNPCKLBWZrrkz = 20277 + + VPUNPCKLBWrm = 20278 + + VPUNPCKLBWrr = 20279 + + VPUNPCKLDQYrm = 20280 + + VPUNPCKLDQYrr = 20281 + + VPUNPCKLDQZ128rm = 20282 + + VPUNPCKLDQZ128rmb = 20283 + + VPUNPCKLDQZ128rmbk = 20284 + + VPUNPCKLDQZ128rmbkz = 20285 + + VPUNPCKLDQZ128rmk = 20286 + + VPUNPCKLDQZ128rmkz = 20287 + + VPUNPCKLDQZ128rr = 20288 + + VPUNPCKLDQZ128rrk = 20289 + + VPUNPCKLDQZ128rrkz = 20290 + + VPUNPCKLDQZ256rm = 20291 + + VPUNPCKLDQZ256rmb = 20292 + + VPUNPCKLDQZ256rmbk = 20293 + + VPUNPCKLDQZ256rmbkz = 20294 + + VPUNPCKLDQZ256rmk = 20295 + + VPUNPCKLDQZ256rmkz = 20296 + + VPUNPCKLDQZ256rr = 20297 + + VPUNPCKLDQZ256rrk = 20298 + + VPUNPCKLDQZ256rrkz = 20299 + + VPUNPCKLDQZrm = 20300 + + VPUNPCKLDQZrmb = 20301 + + VPUNPCKLDQZrmbk = 20302 + + VPUNPCKLDQZrmbkz = 20303 + + VPUNPCKLDQZrmk = 20304 + + VPUNPCKLDQZrmkz = 20305 + + VPUNPCKLDQZrr = 20306 + + VPUNPCKLDQZrrk = 20307 + + VPUNPCKLDQZrrkz = 20308 + + VPUNPCKLDQrm = 20309 + + VPUNPCKLDQrr = 20310 + + VPUNPCKLQDQYrm = 20311 + + VPUNPCKLQDQYrr = 20312 + + VPUNPCKLQDQZ128rm = 20313 + + VPUNPCKLQDQZ128rmb = 20314 + + VPUNPCKLQDQZ128rmbk = 20315 + + VPUNPCKLQDQZ128rmbkz = 20316 + + VPUNPCKLQDQZ128rmk = 20317 + + VPUNPCKLQDQZ128rmkz = 20318 + + VPUNPCKLQDQZ128rr = 20319 + + VPUNPCKLQDQZ128rrk = 20320 + + VPUNPCKLQDQZ128rrkz = 20321 + + VPUNPCKLQDQZ256rm = 20322 + + VPUNPCKLQDQZ256rmb = 20323 + + VPUNPCKLQDQZ256rmbk = 20324 + + VPUNPCKLQDQZ256rmbkz = 20325 + + VPUNPCKLQDQZ256rmk = 20326 + + VPUNPCKLQDQZ256rmkz = 20327 + + VPUNPCKLQDQZ256rr = 20328 + + VPUNPCKLQDQZ256rrk = 20329 + + VPUNPCKLQDQZ256rrkz = 20330 + + VPUNPCKLQDQZrm = 20331 + + VPUNPCKLQDQZrmb = 20332 + + VPUNPCKLQDQZrmbk = 20333 + + VPUNPCKLQDQZrmbkz = 20334 + + VPUNPCKLQDQZrmk = 20335 + + VPUNPCKLQDQZrmkz = 20336 + + VPUNPCKLQDQZrr = 20337 + + VPUNPCKLQDQZrrk = 20338 + + VPUNPCKLQDQZrrkz = 20339 + + VPUNPCKLQDQrm = 20340 + + VPUNPCKLQDQrr = 20341 + + VPUNPCKLWDYrm = 20342 + + VPUNPCKLWDYrr = 20343 + + VPUNPCKLWDZ128rm = 20344 + + VPUNPCKLWDZ128rmk = 20345 + + VPUNPCKLWDZ128rmkz = 20346 + + VPUNPCKLWDZ128rr = 20347 + + VPUNPCKLWDZ128rrk = 20348 + + VPUNPCKLWDZ128rrkz = 20349 + + VPUNPCKLWDZ256rm = 20350 + + VPUNPCKLWDZ256rmk = 20351 + + VPUNPCKLWDZ256rmkz = 20352 + + VPUNPCKLWDZ256rr = 20353 + + VPUNPCKLWDZ256rrk = 20354 + + VPUNPCKLWDZ256rrkz = 20355 + + VPUNPCKLWDZrm = 20356 + + VPUNPCKLWDZrmk = 20357 + + VPUNPCKLWDZrmkz = 20358 + + VPUNPCKLWDZrr = 20359 + + VPUNPCKLWDZrrk = 20360 + + VPUNPCKLWDZrrkz = 20361 + + VPUNPCKLWDrm = 20362 + + VPUNPCKLWDrr = 20363 + + VPXORDZ128rm = 20364 + + VPXORDZ128rmb = 20365 + + VPXORDZ128rmbk = 20366 + + VPXORDZ128rmbkz = 20367 + + VPXORDZ128rmk = 20368 + + VPXORDZ128rmkz = 20369 + + VPXORDZ128rr = 20370 + + VPXORDZ128rrk = 20371 + + VPXORDZ128rrkz = 20372 + + VPXORDZ256rm = 20373 + + VPXORDZ256rmb = 20374 + + VPXORDZ256rmbk = 20375 + + VPXORDZ256rmbkz = 20376 + + VPXORDZ256rmk = 20377 + + VPXORDZ256rmkz = 20378 + + VPXORDZ256rr = 20379 + + VPXORDZ256rrk = 20380 + + VPXORDZ256rrkz = 20381 + + VPXORDZrm = 20382 + + VPXORDZrmb = 20383 + + VPXORDZrmbk = 20384 + + VPXORDZrmbkz = 20385 + + VPXORDZrmk = 20386 + + VPXORDZrmkz = 20387 + + VPXORDZrr = 20388 + + VPXORDZrrk = 20389 + + VPXORDZrrkz = 20390 + + VPXORQZ128rm = 20391 + + VPXORQZ128rmb = 20392 + + VPXORQZ128rmbk = 20393 + + VPXORQZ128rmbkz = 20394 + + VPXORQZ128rmk = 20395 + + VPXORQZ128rmkz = 20396 + + VPXORQZ128rr = 20397 + + VPXORQZ128rrk = 20398 + + VPXORQZ128rrkz = 20399 + + VPXORQZ256rm = 20400 + + VPXORQZ256rmb = 20401 + + VPXORQZ256rmbk = 20402 + + VPXORQZ256rmbkz = 20403 + + VPXORQZ256rmk = 20404 + + VPXORQZ256rmkz = 20405 + + VPXORQZ256rr = 20406 + + VPXORQZ256rrk = 20407 + + VPXORQZ256rrkz = 20408 + + VPXORQZrm = 20409 + + VPXORQZrmb = 20410 + + VPXORQZrmbk = 20411 + + VPXORQZrmbkz = 20412 + + VPXORQZrmk = 20413 + + VPXORQZrmkz = 20414 + + VPXORQZrr = 20415 + + VPXORQZrrk = 20416 + + VPXORQZrrkz = 20417 + + VPXORYrm = 20418 + + VPXORYrr = 20419 + + VPXORrm = 20420 + + VPXORrr = 20421 + + VRANGEPDZ128rmbi = 20422 + + VRANGEPDZ128rmbik = 20423 + + VRANGEPDZ128rmbikz = 20424 + + VRANGEPDZ128rmi = 20425 + + VRANGEPDZ128rmik = 20426 + + VRANGEPDZ128rmikz = 20427 + + VRANGEPDZ128rri = 20428 + + VRANGEPDZ128rrik = 20429 + + VRANGEPDZ128rrikz = 20430 + + VRANGEPDZ256rmbi = 20431 + + VRANGEPDZ256rmbik = 20432 + + VRANGEPDZ256rmbikz = 20433 + + VRANGEPDZ256rmi = 20434 + + VRANGEPDZ256rmik = 20435 + + VRANGEPDZ256rmikz = 20436 + + VRANGEPDZ256rri = 20437 + + VRANGEPDZ256rrik = 20438 + + VRANGEPDZ256rrikz = 20439 + + VRANGEPDZrmbi = 20440 + + VRANGEPDZrmbik = 20441 + + VRANGEPDZrmbikz = 20442 + + VRANGEPDZrmi = 20443 + + VRANGEPDZrmik = 20444 + + VRANGEPDZrmikz = 20445 + + VRANGEPDZrri = 20446 + + VRANGEPDZrrib = 20447 + + VRANGEPDZrribk = 20448 + + VRANGEPDZrribkz = 20449 + + VRANGEPDZrrik = 20450 + + VRANGEPDZrrikz = 20451 + + VRANGEPSZ128rmbi = 20452 + + VRANGEPSZ128rmbik = 20453 + + VRANGEPSZ128rmbikz = 20454 + + VRANGEPSZ128rmi = 20455 + + VRANGEPSZ128rmik = 20456 + + VRANGEPSZ128rmikz = 20457 + + VRANGEPSZ128rri = 20458 + + VRANGEPSZ128rrik = 20459 + + VRANGEPSZ128rrikz = 20460 + + VRANGEPSZ256rmbi = 20461 + + VRANGEPSZ256rmbik = 20462 + + VRANGEPSZ256rmbikz = 20463 + + VRANGEPSZ256rmi = 20464 + + VRANGEPSZ256rmik = 20465 + + VRANGEPSZ256rmikz = 20466 + + VRANGEPSZ256rri = 20467 + + VRANGEPSZ256rrik = 20468 + + VRANGEPSZ256rrikz = 20469 + + VRANGEPSZrmbi = 20470 + + VRANGEPSZrmbik = 20471 + + VRANGEPSZrmbikz = 20472 + + VRANGEPSZrmi = 20473 + + VRANGEPSZrmik = 20474 + + VRANGEPSZrmikz = 20475 + + VRANGEPSZrri = 20476 + + VRANGEPSZrrib = 20477 + + VRANGEPSZrribk = 20478 + + VRANGEPSZrribkz = 20479 + + VRANGEPSZrrik = 20480 + + VRANGEPSZrrikz = 20481 + + VRANGESDZrmi = 20482 + + VRANGESDZrmik = 20483 + + VRANGESDZrmikz = 20484 + + VRANGESDZrri = 20485 + + VRANGESDZrrib = 20486 + + VRANGESDZrribk = 20487 + + VRANGESDZrribkz = 20488 + + VRANGESDZrrik = 20489 + + VRANGESDZrrikz = 20490 + + VRANGESSZrmi = 20491 + + VRANGESSZrmik = 20492 + + VRANGESSZrmikz = 20493 + + VRANGESSZrri = 20494 + + VRANGESSZrrib = 20495 + + VRANGESSZrribk = 20496 + + VRANGESSZrribkz = 20497 + + VRANGESSZrrik = 20498 + + VRANGESSZrrikz = 20499 + + VRCP14PDZ128m = 20500 + + VRCP14PDZ128mb = 20501 + + VRCP14PDZ128mbk = 20502 + + VRCP14PDZ128mbkz = 20503 + + VRCP14PDZ128mk = 20504 + + VRCP14PDZ128mkz = 20505 + + VRCP14PDZ128r = 20506 + + VRCP14PDZ128rk = 20507 + + VRCP14PDZ128rkz = 20508 + + VRCP14PDZ256m = 20509 + + VRCP14PDZ256mb = 20510 + + VRCP14PDZ256mbk = 20511 + + VRCP14PDZ256mbkz = 20512 + + VRCP14PDZ256mk = 20513 + + VRCP14PDZ256mkz = 20514 + + VRCP14PDZ256r = 20515 + + VRCP14PDZ256rk = 20516 + + VRCP14PDZ256rkz = 20517 + + VRCP14PDZm = 20518 + + VRCP14PDZmb = 20519 + + VRCP14PDZmbk = 20520 + + VRCP14PDZmbkz = 20521 + + VRCP14PDZmk = 20522 + + VRCP14PDZmkz = 20523 + + VRCP14PDZr = 20524 + + VRCP14PDZrk = 20525 + + VRCP14PDZrkz = 20526 + + VRCP14PSZ128m = 20527 + + VRCP14PSZ128mb = 20528 + + VRCP14PSZ128mbk = 20529 + + VRCP14PSZ128mbkz = 20530 + + VRCP14PSZ128mk = 20531 + + VRCP14PSZ128mkz = 20532 + + VRCP14PSZ128r = 20533 + + VRCP14PSZ128rk = 20534 + + VRCP14PSZ128rkz = 20535 + + VRCP14PSZ256m = 20536 + + VRCP14PSZ256mb = 20537 + + VRCP14PSZ256mbk = 20538 + + VRCP14PSZ256mbkz = 20539 + + VRCP14PSZ256mk = 20540 + + VRCP14PSZ256mkz = 20541 + + VRCP14PSZ256r = 20542 + + VRCP14PSZ256rk = 20543 + + VRCP14PSZ256rkz = 20544 + + VRCP14PSZm = 20545 + + VRCP14PSZmb = 20546 + + VRCP14PSZmbk = 20547 + + VRCP14PSZmbkz = 20548 + + VRCP14PSZmk = 20549 + + VRCP14PSZmkz = 20550 + + VRCP14PSZr = 20551 + + VRCP14PSZrk = 20552 + + VRCP14PSZrkz = 20553 + + VRCP14SDZrm = 20554 + + VRCP14SDZrmk = 20555 + + VRCP14SDZrmkz = 20556 + + VRCP14SDZrr = 20557 + + VRCP14SDZrrk = 20558 + + VRCP14SDZrrkz = 20559 + + VRCP14SSZrm = 20560 + + VRCP14SSZrmk = 20561 + + VRCP14SSZrmkz = 20562 + + VRCP14SSZrr = 20563 + + VRCP14SSZrrk = 20564 + + VRCP14SSZrrkz = 20565 + + VRCP28PDZm = 20566 + + VRCP28PDZmb = 20567 + + VRCP28PDZmbk = 20568 + + VRCP28PDZmbkz = 20569 + + VRCP28PDZmk = 20570 + + VRCP28PDZmkz = 20571 + + VRCP28PDZr = 20572 + + VRCP28PDZrb = 20573 + + VRCP28PDZrbk = 20574 + + VRCP28PDZrbkz = 20575 + + VRCP28PDZrk = 20576 + + VRCP28PDZrkz = 20577 + + VRCP28PSZm = 20578 + + VRCP28PSZmb = 20579 + + VRCP28PSZmbk = 20580 + + VRCP28PSZmbkz = 20581 + + VRCP28PSZmk = 20582 + + VRCP28PSZmkz = 20583 + + VRCP28PSZr = 20584 + + VRCP28PSZrb = 20585 + + VRCP28PSZrbk = 20586 + + VRCP28PSZrbkz = 20587 + + VRCP28PSZrk = 20588 + + VRCP28PSZrkz = 20589 + + VRCP28SDZm = 20590 + + VRCP28SDZmk = 20591 + + VRCP28SDZmkz = 20592 + + VRCP28SDZr = 20593 + + VRCP28SDZrb = 20594 + + VRCP28SDZrbk = 20595 + + VRCP28SDZrbkz = 20596 + + VRCP28SDZrk = 20597 + + VRCP28SDZrkz = 20598 + + VRCP28SSZm = 20599 + + VRCP28SSZmk = 20600 + + VRCP28SSZmkz = 20601 + + VRCP28SSZr = 20602 + + VRCP28SSZrb = 20603 + + VRCP28SSZrbk = 20604 + + VRCP28SSZrbkz = 20605 + + VRCP28SSZrk = 20606 + + VRCP28SSZrkz = 20607 + + VRCPBF16Z128m = 20608 + + VRCPBF16Z128mb = 20609 + + VRCPBF16Z128mbk = 20610 + + VRCPBF16Z128mbkz = 20611 + + VRCPBF16Z128mk = 20612 + + VRCPBF16Z128mkz = 20613 + + VRCPBF16Z128r = 20614 + + VRCPBF16Z128rk = 20615 + + VRCPBF16Z128rkz = 20616 + + VRCPBF16Z256m = 20617 + + VRCPBF16Z256mb = 20618 + + VRCPBF16Z256mbk = 20619 + + VRCPBF16Z256mbkz = 20620 + + VRCPBF16Z256mk = 20621 + + VRCPBF16Z256mkz = 20622 + + VRCPBF16Z256r = 20623 + + VRCPBF16Z256rk = 20624 + + VRCPBF16Z256rkz = 20625 + + VRCPBF16Zm = 20626 + + VRCPBF16Zmb = 20627 + + VRCPBF16Zmbk = 20628 + + VRCPBF16Zmbkz = 20629 + + VRCPBF16Zmk = 20630 + + VRCPBF16Zmkz = 20631 + + VRCPBF16Zr = 20632 + + VRCPBF16Zrk = 20633 + + VRCPBF16Zrkz = 20634 + + VRCPPHZ128m = 20635 + + VRCPPHZ128mb = 20636 + + VRCPPHZ128mbk = 20637 + + VRCPPHZ128mbkz = 20638 + + VRCPPHZ128mk = 20639 + + VRCPPHZ128mkz = 20640 + + VRCPPHZ128r = 20641 + + VRCPPHZ128rk = 20642 + + VRCPPHZ128rkz = 20643 + + VRCPPHZ256m = 20644 + + VRCPPHZ256mb = 20645 + + VRCPPHZ256mbk = 20646 + + VRCPPHZ256mbkz = 20647 + + VRCPPHZ256mk = 20648 + + VRCPPHZ256mkz = 20649 + + VRCPPHZ256r = 20650 + + VRCPPHZ256rk = 20651 + + VRCPPHZ256rkz = 20652 + + VRCPPHZm = 20653 + + VRCPPHZmb = 20654 + + VRCPPHZmbk = 20655 + + VRCPPHZmbkz = 20656 + + VRCPPHZmk = 20657 + + VRCPPHZmkz = 20658 + + VRCPPHZr = 20659 + + VRCPPHZrk = 20660 + + VRCPPHZrkz = 20661 + + VRCPPSYm = 20662 + + VRCPPSYr = 20663 + + VRCPPSm = 20664 + + VRCPPSr = 20665 + + VRCPSHZrm = 20666 + + VRCPSHZrmk = 20667 + + VRCPSHZrmkz = 20668 + + VRCPSHZrr = 20669 + + VRCPSHZrrk = 20670 + + VRCPSHZrrkz = 20671 + + VRCPSSm = 20672 + + VRCPSSm_Int = 20673 + + VRCPSSr = 20674 + + VRCPSSr_Int = 20675 + + VREDUCEBF16Z128rmbi = 20676 + + VREDUCEBF16Z128rmbik = 20677 + + VREDUCEBF16Z128rmbikz = 20678 + + VREDUCEBF16Z128rmi = 20679 + + VREDUCEBF16Z128rmik = 20680 + + VREDUCEBF16Z128rmikz = 20681 + + VREDUCEBF16Z128rri = 20682 + + VREDUCEBF16Z128rrik = 20683 + + VREDUCEBF16Z128rrikz = 20684 + + VREDUCEBF16Z256rmbi = 20685 + + VREDUCEBF16Z256rmbik = 20686 + + VREDUCEBF16Z256rmbikz = 20687 + + VREDUCEBF16Z256rmi = 20688 + + VREDUCEBF16Z256rmik = 20689 + + VREDUCEBF16Z256rmikz = 20690 + + VREDUCEBF16Z256rri = 20691 + + VREDUCEBF16Z256rrik = 20692 + + VREDUCEBF16Z256rrikz = 20693 + + VREDUCEBF16Zrmbi = 20694 + + VREDUCEBF16Zrmbik = 20695 + + VREDUCEBF16Zrmbikz = 20696 + + VREDUCEBF16Zrmi = 20697 + + VREDUCEBF16Zrmik = 20698 + + VREDUCEBF16Zrmikz = 20699 + + VREDUCEBF16Zrri = 20700 + + VREDUCEBF16Zrrik = 20701 + + VREDUCEBF16Zrrikz = 20702 + + VREDUCEPDZ128rmbi = 20703 + + VREDUCEPDZ128rmbik = 20704 + + VREDUCEPDZ128rmbikz = 20705 + + VREDUCEPDZ128rmi = 20706 + + VREDUCEPDZ128rmik = 20707 + + VREDUCEPDZ128rmikz = 20708 + + VREDUCEPDZ128rri = 20709 + + VREDUCEPDZ128rrik = 20710 + + VREDUCEPDZ128rrikz = 20711 + + VREDUCEPDZ256rmbi = 20712 + + VREDUCEPDZ256rmbik = 20713 + + VREDUCEPDZ256rmbikz = 20714 + + VREDUCEPDZ256rmi = 20715 + + VREDUCEPDZ256rmik = 20716 + + VREDUCEPDZ256rmikz = 20717 + + VREDUCEPDZ256rri = 20718 + + VREDUCEPDZ256rrik = 20719 + + VREDUCEPDZ256rrikz = 20720 + + VREDUCEPDZrmbi = 20721 + + VREDUCEPDZrmbik = 20722 + + VREDUCEPDZrmbikz = 20723 + + VREDUCEPDZrmi = 20724 + + VREDUCEPDZrmik = 20725 + + VREDUCEPDZrmikz = 20726 + + VREDUCEPDZrri = 20727 + + VREDUCEPDZrrib = 20728 + + VREDUCEPDZrribk = 20729 + + VREDUCEPDZrribkz = 20730 + + VREDUCEPDZrrik = 20731 + + VREDUCEPDZrrikz = 20732 + + VREDUCEPHZ128rmbi = 20733 + + VREDUCEPHZ128rmbik = 20734 + + VREDUCEPHZ128rmbikz = 20735 + + VREDUCEPHZ128rmi = 20736 + + VREDUCEPHZ128rmik = 20737 + + VREDUCEPHZ128rmikz = 20738 + + VREDUCEPHZ128rri = 20739 + + VREDUCEPHZ128rrik = 20740 + + VREDUCEPHZ128rrikz = 20741 + + VREDUCEPHZ256rmbi = 20742 + + VREDUCEPHZ256rmbik = 20743 + + VREDUCEPHZ256rmbikz = 20744 + + VREDUCEPHZ256rmi = 20745 + + VREDUCEPHZ256rmik = 20746 + + VREDUCEPHZ256rmikz = 20747 + + VREDUCEPHZ256rri = 20748 + + VREDUCEPHZ256rrik = 20749 + + VREDUCEPHZ256rrikz = 20750 + + VREDUCEPHZrmbi = 20751 + + VREDUCEPHZrmbik = 20752 + + VREDUCEPHZrmbikz = 20753 + + VREDUCEPHZrmi = 20754 + + VREDUCEPHZrmik = 20755 + + VREDUCEPHZrmikz = 20756 + + VREDUCEPHZrri = 20757 + + VREDUCEPHZrrib = 20758 + + VREDUCEPHZrribk = 20759 + + VREDUCEPHZrribkz = 20760 + + VREDUCEPHZrrik = 20761 + + VREDUCEPHZrrikz = 20762 + + VREDUCEPSZ128rmbi = 20763 + + VREDUCEPSZ128rmbik = 20764 + + VREDUCEPSZ128rmbikz = 20765 + + VREDUCEPSZ128rmi = 20766 + + VREDUCEPSZ128rmik = 20767 + + VREDUCEPSZ128rmikz = 20768 + + VREDUCEPSZ128rri = 20769 + + VREDUCEPSZ128rrik = 20770 + + VREDUCEPSZ128rrikz = 20771 + + VREDUCEPSZ256rmbi = 20772 + + VREDUCEPSZ256rmbik = 20773 + + VREDUCEPSZ256rmbikz = 20774 + + VREDUCEPSZ256rmi = 20775 + + VREDUCEPSZ256rmik = 20776 + + VREDUCEPSZ256rmikz = 20777 + + VREDUCEPSZ256rri = 20778 + + VREDUCEPSZ256rrik = 20779 + + VREDUCEPSZ256rrikz = 20780 + + VREDUCEPSZrmbi = 20781 + + VREDUCEPSZrmbik = 20782 + + VREDUCEPSZrmbikz = 20783 + + VREDUCEPSZrmi = 20784 + + VREDUCEPSZrmik = 20785 + + VREDUCEPSZrmikz = 20786 + + VREDUCEPSZrri = 20787 + + VREDUCEPSZrrib = 20788 + + VREDUCEPSZrribk = 20789 + + VREDUCEPSZrribkz = 20790 + + VREDUCEPSZrrik = 20791 + + VREDUCEPSZrrikz = 20792 + + VREDUCESDZrmi = 20793 + + VREDUCESDZrmik = 20794 + + VREDUCESDZrmikz = 20795 + + VREDUCESDZrri = 20796 + + VREDUCESDZrrib = 20797 + + VREDUCESDZrribk = 20798 + + VREDUCESDZrribkz = 20799 + + VREDUCESDZrrik = 20800 + + VREDUCESDZrrikz = 20801 + + VREDUCESHZrmi = 20802 + + VREDUCESHZrmik = 20803 + + VREDUCESHZrmikz = 20804 + + VREDUCESHZrri = 20805 + + VREDUCESHZrrib = 20806 + + VREDUCESHZrribk = 20807 + + VREDUCESHZrribkz = 20808 + + VREDUCESHZrrik = 20809 + + VREDUCESHZrrikz = 20810 + + VREDUCESSZrmi = 20811 + + VREDUCESSZrmik = 20812 + + VREDUCESSZrmikz = 20813 + + VREDUCESSZrri = 20814 + + VREDUCESSZrrib = 20815 + + VREDUCESSZrribk = 20816 + + VREDUCESSZrribkz = 20817 + + VREDUCESSZrrik = 20818 + + VREDUCESSZrrikz = 20819 + + VRNDSCALEBF16Z128rmbi = 20820 + + VRNDSCALEBF16Z128rmbik = 20821 + + VRNDSCALEBF16Z128rmbikz = 20822 + + VRNDSCALEBF16Z128rmi = 20823 + + VRNDSCALEBF16Z128rmik = 20824 + + VRNDSCALEBF16Z128rmikz = 20825 + + VRNDSCALEBF16Z128rri = 20826 + + VRNDSCALEBF16Z128rrik = 20827 + + VRNDSCALEBF16Z128rrikz = 20828 + + VRNDSCALEBF16Z256rmbi = 20829 + + VRNDSCALEBF16Z256rmbik = 20830 + + VRNDSCALEBF16Z256rmbikz = 20831 + + VRNDSCALEBF16Z256rmi = 20832 + + VRNDSCALEBF16Z256rmik = 20833 + + VRNDSCALEBF16Z256rmikz = 20834 + + VRNDSCALEBF16Z256rri = 20835 + + VRNDSCALEBF16Z256rrik = 20836 + + VRNDSCALEBF16Z256rrikz = 20837 + + VRNDSCALEBF16Zrmbi = 20838 + + VRNDSCALEBF16Zrmbik = 20839 + + VRNDSCALEBF16Zrmbikz = 20840 + + VRNDSCALEBF16Zrmi = 20841 + + VRNDSCALEBF16Zrmik = 20842 + + VRNDSCALEBF16Zrmikz = 20843 + + VRNDSCALEBF16Zrri = 20844 + + VRNDSCALEBF16Zrrik = 20845 + + VRNDSCALEBF16Zrrikz = 20846 + + VRNDSCALEPDZ128rmbi = 20847 + + VRNDSCALEPDZ128rmbik = 20848 + + VRNDSCALEPDZ128rmbikz = 20849 + + VRNDSCALEPDZ128rmi = 20850 + + VRNDSCALEPDZ128rmik = 20851 + + VRNDSCALEPDZ128rmikz = 20852 + + VRNDSCALEPDZ128rri = 20853 + + VRNDSCALEPDZ128rrik = 20854 + + VRNDSCALEPDZ128rrikz = 20855 + + VRNDSCALEPDZ256rmbi = 20856 + + VRNDSCALEPDZ256rmbik = 20857 + + VRNDSCALEPDZ256rmbikz = 20858 + + VRNDSCALEPDZ256rmi = 20859 + + VRNDSCALEPDZ256rmik = 20860 + + VRNDSCALEPDZ256rmikz = 20861 + + VRNDSCALEPDZ256rri = 20862 + + VRNDSCALEPDZ256rrik = 20863 + + VRNDSCALEPDZ256rrikz = 20864 + + VRNDSCALEPDZrmbi = 20865 + + VRNDSCALEPDZrmbik = 20866 + + VRNDSCALEPDZrmbikz = 20867 + + VRNDSCALEPDZrmi = 20868 + + VRNDSCALEPDZrmik = 20869 + + VRNDSCALEPDZrmikz = 20870 + + VRNDSCALEPDZrri = 20871 + + VRNDSCALEPDZrrib = 20872 + + VRNDSCALEPDZrribk = 20873 + + VRNDSCALEPDZrribkz = 20874 + + VRNDSCALEPDZrrik = 20875 + + VRNDSCALEPDZrrikz = 20876 + + VRNDSCALEPHZ128rmbi = 20877 + + VRNDSCALEPHZ128rmbik = 20878 + + VRNDSCALEPHZ128rmbikz = 20879 + + VRNDSCALEPHZ128rmi = 20880 + + VRNDSCALEPHZ128rmik = 20881 + + VRNDSCALEPHZ128rmikz = 20882 + + VRNDSCALEPHZ128rri = 20883 + + VRNDSCALEPHZ128rrik = 20884 + + VRNDSCALEPHZ128rrikz = 20885 + + VRNDSCALEPHZ256rmbi = 20886 + + VRNDSCALEPHZ256rmbik = 20887 + + VRNDSCALEPHZ256rmbikz = 20888 + + VRNDSCALEPHZ256rmi = 20889 + + VRNDSCALEPHZ256rmik = 20890 + + VRNDSCALEPHZ256rmikz = 20891 + + VRNDSCALEPHZ256rri = 20892 + + VRNDSCALEPHZ256rrik = 20893 + + VRNDSCALEPHZ256rrikz = 20894 + + VRNDSCALEPHZrmbi = 20895 + + VRNDSCALEPHZrmbik = 20896 + + VRNDSCALEPHZrmbikz = 20897 + + VRNDSCALEPHZrmi = 20898 + + VRNDSCALEPHZrmik = 20899 + + VRNDSCALEPHZrmikz = 20900 + + VRNDSCALEPHZrri = 20901 + + VRNDSCALEPHZrrib = 20902 + + VRNDSCALEPHZrribk = 20903 + + VRNDSCALEPHZrribkz = 20904 + + VRNDSCALEPHZrrik = 20905 + + VRNDSCALEPHZrrikz = 20906 + + VRNDSCALEPSZ128rmbi = 20907 + + VRNDSCALEPSZ128rmbik = 20908 + + VRNDSCALEPSZ128rmbikz = 20909 + + VRNDSCALEPSZ128rmi = 20910 + + VRNDSCALEPSZ128rmik = 20911 + + VRNDSCALEPSZ128rmikz = 20912 + + VRNDSCALEPSZ128rri = 20913 + + VRNDSCALEPSZ128rrik = 20914 + + VRNDSCALEPSZ128rrikz = 20915 + + VRNDSCALEPSZ256rmbi = 20916 + + VRNDSCALEPSZ256rmbik = 20917 + + VRNDSCALEPSZ256rmbikz = 20918 + + VRNDSCALEPSZ256rmi = 20919 + + VRNDSCALEPSZ256rmik = 20920 + + VRNDSCALEPSZ256rmikz = 20921 + + VRNDSCALEPSZ256rri = 20922 + + VRNDSCALEPSZ256rrik = 20923 + + VRNDSCALEPSZ256rrikz = 20924 + + VRNDSCALEPSZrmbi = 20925 + + VRNDSCALEPSZrmbik = 20926 + + VRNDSCALEPSZrmbikz = 20927 + + VRNDSCALEPSZrmi = 20928 + + VRNDSCALEPSZrmik = 20929 + + VRNDSCALEPSZrmikz = 20930 + + VRNDSCALEPSZrri = 20931 + + VRNDSCALEPSZrrib = 20932 + + VRNDSCALEPSZrribk = 20933 + + VRNDSCALEPSZrribkz = 20934 + + VRNDSCALEPSZrrik = 20935 + + VRNDSCALEPSZrrikz = 20936 + + VRNDSCALESDZrmi = 20937 + + VRNDSCALESDZrmi_Int = 20938 + + VRNDSCALESDZrmik_Int = 20939 + + VRNDSCALESDZrmikz_Int = 20940 + + VRNDSCALESDZrri = 20941 + + VRNDSCALESDZrri_Int = 20942 + + VRNDSCALESDZrrib_Int = 20943 + + VRNDSCALESDZrribk_Int = 20944 + + VRNDSCALESDZrribkz_Int = 20945 + + VRNDSCALESDZrrik_Int = 20946 + + VRNDSCALESDZrrikz_Int = 20947 + + VRNDSCALESHZrmi = 20948 + + VRNDSCALESHZrmi_Int = 20949 + + VRNDSCALESHZrmik_Int = 20950 + + VRNDSCALESHZrmikz_Int = 20951 + + VRNDSCALESHZrri = 20952 + + VRNDSCALESHZrri_Int = 20953 + + VRNDSCALESHZrrib_Int = 20954 + + VRNDSCALESHZrribk_Int = 20955 + + VRNDSCALESHZrribkz_Int = 20956 + + VRNDSCALESHZrrik_Int = 20957 + + VRNDSCALESHZrrikz_Int = 20958 + + VRNDSCALESSZrmi = 20959 + + VRNDSCALESSZrmi_Int = 20960 + + VRNDSCALESSZrmik_Int = 20961 + + VRNDSCALESSZrmikz_Int = 20962 + + VRNDSCALESSZrri = 20963 + + VRNDSCALESSZrri_Int = 20964 + + VRNDSCALESSZrrib_Int = 20965 + + VRNDSCALESSZrribk_Int = 20966 + + VRNDSCALESSZrribkz_Int = 20967 + + VRNDSCALESSZrrik_Int = 20968 + + VRNDSCALESSZrrikz_Int = 20969 + + VROUNDPDYmi = 20970 + + VROUNDPDYri = 20971 + + VROUNDPDmi = 20972 + + VROUNDPDri = 20973 + + VROUNDPSYmi = 20974 + + VROUNDPSYri = 20975 + + VROUNDPSmi = 20976 + + VROUNDPSri = 20977 + + VROUNDSDmi = 20978 + + VROUNDSDmi_Int = 20979 + + VROUNDSDri = 20980 + + VROUNDSDri_Int = 20981 + + VROUNDSSmi = 20982 + + VROUNDSSmi_Int = 20983 + + VROUNDSSri = 20984 + + VROUNDSSri_Int = 20985 + + VRSQRT14PDZ128m = 20986 + + VRSQRT14PDZ128mb = 20987 + + VRSQRT14PDZ128mbk = 20988 + + VRSQRT14PDZ128mbkz = 20989 + + VRSQRT14PDZ128mk = 20990 + + VRSQRT14PDZ128mkz = 20991 + + VRSQRT14PDZ128r = 20992 + + VRSQRT14PDZ128rk = 20993 + + VRSQRT14PDZ128rkz = 20994 + + VRSQRT14PDZ256m = 20995 + + VRSQRT14PDZ256mb = 20996 + + VRSQRT14PDZ256mbk = 20997 + + VRSQRT14PDZ256mbkz = 20998 + + VRSQRT14PDZ256mk = 20999 + + VRSQRT14PDZ256mkz = 21000 + + VRSQRT14PDZ256r = 21001 + + VRSQRT14PDZ256rk = 21002 + + VRSQRT14PDZ256rkz = 21003 + + VRSQRT14PDZm = 21004 + + VRSQRT14PDZmb = 21005 + + VRSQRT14PDZmbk = 21006 + + VRSQRT14PDZmbkz = 21007 + + VRSQRT14PDZmk = 21008 + + VRSQRT14PDZmkz = 21009 + + VRSQRT14PDZr = 21010 + + VRSQRT14PDZrk = 21011 + + VRSQRT14PDZrkz = 21012 + + VRSQRT14PSZ128m = 21013 + + VRSQRT14PSZ128mb = 21014 + + VRSQRT14PSZ128mbk = 21015 + + VRSQRT14PSZ128mbkz = 21016 + + VRSQRT14PSZ128mk = 21017 + + VRSQRT14PSZ128mkz = 21018 + + VRSQRT14PSZ128r = 21019 + + VRSQRT14PSZ128rk = 21020 + + VRSQRT14PSZ128rkz = 21021 + + VRSQRT14PSZ256m = 21022 + + VRSQRT14PSZ256mb = 21023 + + VRSQRT14PSZ256mbk = 21024 + + VRSQRT14PSZ256mbkz = 21025 + + VRSQRT14PSZ256mk = 21026 + + VRSQRT14PSZ256mkz = 21027 + + VRSQRT14PSZ256r = 21028 + + VRSQRT14PSZ256rk = 21029 + + VRSQRT14PSZ256rkz = 21030 + + VRSQRT14PSZm = 21031 + + VRSQRT14PSZmb = 21032 + + VRSQRT14PSZmbk = 21033 + + VRSQRT14PSZmbkz = 21034 + + VRSQRT14PSZmk = 21035 + + VRSQRT14PSZmkz = 21036 + + VRSQRT14PSZr = 21037 + + VRSQRT14PSZrk = 21038 + + VRSQRT14PSZrkz = 21039 + + VRSQRT14SDZrm = 21040 + + VRSQRT14SDZrmk = 21041 + + VRSQRT14SDZrmkz = 21042 + + VRSQRT14SDZrr = 21043 + + VRSQRT14SDZrrk = 21044 + + VRSQRT14SDZrrkz = 21045 + + VRSQRT14SSZrm = 21046 + + VRSQRT14SSZrmk = 21047 + + VRSQRT14SSZrmkz = 21048 + + VRSQRT14SSZrr = 21049 + + VRSQRT14SSZrrk = 21050 + + VRSQRT14SSZrrkz = 21051 + + VRSQRT28PDZm = 21052 + + VRSQRT28PDZmb = 21053 + + VRSQRT28PDZmbk = 21054 + + VRSQRT28PDZmbkz = 21055 + + VRSQRT28PDZmk = 21056 + + VRSQRT28PDZmkz = 21057 + + VRSQRT28PDZr = 21058 + + VRSQRT28PDZrb = 21059 + + VRSQRT28PDZrbk = 21060 + + VRSQRT28PDZrbkz = 21061 + + VRSQRT28PDZrk = 21062 + + VRSQRT28PDZrkz = 21063 + + VRSQRT28PSZm = 21064 + + VRSQRT28PSZmb = 21065 + + VRSQRT28PSZmbk = 21066 + + VRSQRT28PSZmbkz = 21067 + + VRSQRT28PSZmk = 21068 + + VRSQRT28PSZmkz = 21069 + + VRSQRT28PSZr = 21070 + + VRSQRT28PSZrb = 21071 + + VRSQRT28PSZrbk = 21072 + + VRSQRT28PSZrbkz = 21073 + + VRSQRT28PSZrk = 21074 + + VRSQRT28PSZrkz = 21075 + + VRSQRT28SDZm = 21076 + + VRSQRT28SDZmk = 21077 + + VRSQRT28SDZmkz = 21078 + + VRSQRT28SDZr = 21079 + + VRSQRT28SDZrb = 21080 + + VRSQRT28SDZrbk = 21081 + + VRSQRT28SDZrbkz = 21082 + + VRSQRT28SDZrk = 21083 + + VRSQRT28SDZrkz = 21084 + + VRSQRT28SSZm = 21085 + + VRSQRT28SSZmk = 21086 + + VRSQRT28SSZmkz = 21087 + + VRSQRT28SSZr = 21088 + + VRSQRT28SSZrb = 21089 + + VRSQRT28SSZrbk = 21090 + + VRSQRT28SSZrbkz = 21091 + + VRSQRT28SSZrk = 21092 + + VRSQRT28SSZrkz = 21093 + + VRSQRTBF16Z128m = 21094 + + VRSQRTBF16Z128mb = 21095 + + VRSQRTBF16Z128mbk = 21096 + + VRSQRTBF16Z128mbkz = 21097 + + VRSQRTBF16Z128mk = 21098 + + VRSQRTBF16Z128mkz = 21099 + + VRSQRTBF16Z128r = 21100 + + VRSQRTBF16Z128rk = 21101 + + VRSQRTBF16Z128rkz = 21102 + + VRSQRTBF16Z256m = 21103 + + VRSQRTBF16Z256mb = 21104 + + VRSQRTBF16Z256mbk = 21105 + + VRSQRTBF16Z256mbkz = 21106 + + VRSQRTBF16Z256mk = 21107 + + VRSQRTBF16Z256mkz = 21108 + + VRSQRTBF16Z256r = 21109 + + VRSQRTBF16Z256rk = 21110 + + VRSQRTBF16Z256rkz = 21111 + + VRSQRTBF16Zm = 21112 + + VRSQRTBF16Zmb = 21113 + + VRSQRTBF16Zmbk = 21114 + + VRSQRTBF16Zmbkz = 21115 + + VRSQRTBF16Zmk = 21116 + + VRSQRTBF16Zmkz = 21117 + + VRSQRTBF16Zr = 21118 + + VRSQRTBF16Zrk = 21119 + + VRSQRTBF16Zrkz = 21120 + + VRSQRTPHZ128m = 21121 + + VRSQRTPHZ128mb = 21122 + + VRSQRTPHZ128mbk = 21123 + + VRSQRTPHZ128mbkz = 21124 + + VRSQRTPHZ128mk = 21125 + + VRSQRTPHZ128mkz = 21126 + + VRSQRTPHZ128r = 21127 + + VRSQRTPHZ128rk = 21128 + + VRSQRTPHZ128rkz = 21129 + + VRSQRTPHZ256m = 21130 + + VRSQRTPHZ256mb = 21131 + + VRSQRTPHZ256mbk = 21132 + + VRSQRTPHZ256mbkz = 21133 + + VRSQRTPHZ256mk = 21134 + + VRSQRTPHZ256mkz = 21135 + + VRSQRTPHZ256r = 21136 + + VRSQRTPHZ256rk = 21137 + + VRSQRTPHZ256rkz = 21138 + + VRSQRTPHZm = 21139 + + VRSQRTPHZmb = 21140 + + VRSQRTPHZmbk = 21141 + + VRSQRTPHZmbkz = 21142 + + VRSQRTPHZmk = 21143 + + VRSQRTPHZmkz = 21144 + + VRSQRTPHZr = 21145 + + VRSQRTPHZrk = 21146 + + VRSQRTPHZrkz = 21147 + + VRSQRTPSYm = 21148 + + VRSQRTPSYr = 21149 + + VRSQRTPSm = 21150 + + VRSQRTPSr = 21151 + + VRSQRTSHZrm = 21152 + + VRSQRTSHZrmk = 21153 + + VRSQRTSHZrmkz = 21154 + + VRSQRTSHZrr = 21155 + + VRSQRTSHZrrk = 21156 + + VRSQRTSHZrrkz = 21157 + + VRSQRTSSm = 21158 + + VRSQRTSSm_Int = 21159 + + VRSQRTSSr = 21160 + + VRSQRTSSr_Int = 21161 + + VSCALEFBF16Z128rm = 21162 + + VSCALEFBF16Z128rmb = 21163 + + VSCALEFBF16Z128rmbk = 21164 + + VSCALEFBF16Z128rmbkz = 21165 + + VSCALEFBF16Z128rmk = 21166 + + VSCALEFBF16Z128rmkz = 21167 + + VSCALEFBF16Z128rr = 21168 + + VSCALEFBF16Z128rrk = 21169 + + VSCALEFBF16Z128rrkz = 21170 + + VSCALEFBF16Z256rm = 21171 + + VSCALEFBF16Z256rmb = 21172 + + VSCALEFBF16Z256rmbk = 21173 + + VSCALEFBF16Z256rmbkz = 21174 + + VSCALEFBF16Z256rmk = 21175 + + VSCALEFBF16Z256rmkz = 21176 + + VSCALEFBF16Z256rr = 21177 + + VSCALEFBF16Z256rrk = 21178 + + VSCALEFBF16Z256rrkz = 21179 + + VSCALEFBF16Zrm = 21180 + + VSCALEFBF16Zrmb = 21181 + + VSCALEFBF16Zrmbk = 21182 + + VSCALEFBF16Zrmbkz = 21183 + + VSCALEFBF16Zrmk = 21184 + + VSCALEFBF16Zrmkz = 21185 + + VSCALEFBF16Zrr = 21186 + + VSCALEFBF16Zrrk = 21187 + + VSCALEFBF16Zrrkz = 21188 + + VSCALEFPDZ128rm = 21189 + + VSCALEFPDZ128rmb = 21190 + + VSCALEFPDZ128rmbk = 21191 + + VSCALEFPDZ128rmbkz = 21192 + + VSCALEFPDZ128rmk = 21193 + + VSCALEFPDZ128rmkz = 21194 + + VSCALEFPDZ128rr = 21195 + + VSCALEFPDZ128rrk = 21196 + + VSCALEFPDZ128rrkz = 21197 + + VSCALEFPDZ256rm = 21198 + + VSCALEFPDZ256rmb = 21199 + + VSCALEFPDZ256rmbk = 21200 + + VSCALEFPDZ256rmbkz = 21201 + + VSCALEFPDZ256rmk = 21202 + + VSCALEFPDZ256rmkz = 21203 + + VSCALEFPDZ256rr = 21204 + + VSCALEFPDZ256rrk = 21205 + + VSCALEFPDZ256rrkz = 21206 + + VSCALEFPDZrm = 21207 + + VSCALEFPDZrmb = 21208 + + VSCALEFPDZrmbk = 21209 + + VSCALEFPDZrmbkz = 21210 + + VSCALEFPDZrmk = 21211 + + VSCALEFPDZrmkz = 21212 + + VSCALEFPDZrr = 21213 + + VSCALEFPDZrrb = 21214 + + VSCALEFPDZrrbk = 21215 + + VSCALEFPDZrrbkz = 21216 + + VSCALEFPDZrrk = 21217 + + VSCALEFPDZrrkz = 21218 + + VSCALEFPHZ128rm = 21219 + + VSCALEFPHZ128rmb = 21220 + + VSCALEFPHZ128rmbk = 21221 + + VSCALEFPHZ128rmbkz = 21222 + + VSCALEFPHZ128rmk = 21223 + + VSCALEFPHZ128rmkz = 21224 + + VSCALEFPHZ128rr = 21225 + + VSCALEFPHZ128rrk = 21226 + + VSCALEFPHZ128rrkz = 21227 + + VSCALEFPHZ256rm = 21228 + + VSCALEFPHZ256rmb = 21229 + + VSCALEFPHZ256rmbk = 21230 + + VSCALEFPHZ256rmbkz = 21231 + + VSCALEFPHZ256rmk = 21232 + + VSCALEFPHZ256rmkz = 21233 + + VSCALEFPHZ256rr = 21234 + + VSCALEFPHZ256rrk = 21235 + + VSCALEFPHZ256rrkz = 21236 + + VSCALEFPHZrm = 21237 + + VSCALEFPHZrmb = 21238 + + VSCALEFPHZrmbk = 21239 + + VSCALEFPHZrmbkz = 21240 + + VSCALEFPHZrmk = 21241 + + VSCALEFPHZrmkz = 21242 + + VSCALEFPHZrr = 21243 + + VSCALEFPHZrrb = 21244 + + VSCALEFPHZrrbk = 21245 + + VSCALEFPHZrrbkz = 21246 + + VSCALEFPHZrrk = 21247 + + VSCALEFPHZrrkz = 21248 + + VSCALEFPSZ128rm = 21249 + + VSCALEFPSZ128rmb = 21250 + + VSCALEFPSZ128rmbk = 21251 + + VSCALEFPSZ128rmbkz = 21252 + + VSCALEFPSZ128rmk = 21253 + + VSCALEFPSZ128rmkz = 21254 + + VSCALEFPSZ128rr = 21255 + + VSCALEFPSZ128rrk = 21256 + + VSCALEFPSZ128rrkz = 21257 + + VSCALEFPSZ256rm = 21258 + + VSCALEFPSZ256rmb = 21259 + + VSCALEFPSZ256rmbk = 21260 + + VSCALEFPSZ256rmbkz = 21261 + + VSCALEFPSZ256rmk = 21262 + + VSCALEFPSZ256rmkz = 21263 + + VSCALEFPSZ256rr = 21264 + + VSCALEFPSZ256rrk = 21265 + + VSCALEFPSZ256rrkz = 21266 + + VSCALEFPSZrm = 21267 + + VSCALEFPSZrmb = 21268 + + VSCALEFPSZrmbk = 21269 + + VSCALEFPSZrmbkz = 21270 + + VSCALEFPSZrmk = 21271 + + VSCALEFPSZrmkz = 21272 + + VSCALEFPSZrr = 21273 + + VSCALEFPSZrrb = 21274 + + VSCALEFPSZrrbk = 21275 + + VSCALEFPSZrrbkz = 21276 + + VSCALEFPSZrrk = 21277 + + VSCALEFPSZrrkz = 21278 + + VSCALEFSDZrm = 21279 + + VSCALEFSDZrmk = 21280 + + VSCALEFSDZrmkz = 21281 + + VSCALEFSDZrr = 21282 + + VSCALEFSDZrrb_Int = 21283 + + VSCALEFSDZrrbk_Int = 21284 + + VSCALEFSDZrrbkz_Int = 21285 + + VSCALEFSDZrrk = 21286 + + VSCALEFSDZrrkz = 21287 + + VSCALEFSHZrm = 21288 + + VSCALEFSHZrmk = 21289 + + VSCALEFSHZrmkz = 21290 + + VSCALEFSHZrr = 21291 + + VSCALEFSHZrrb_Int = 21292 + + VSCALEFSHZrrbk_Int = 21293 + + VSCALEFSHZrrbkz_Int = 21294 + + VSCALEFSHZrrk = 21295 + + VSCALEFSHZrrkz = 21296 + + VSCALEFSSZrm = 21297 + + VSCALEFSSZrmk = 21298 + + VSCALEFSSZrmkz = 21299 + + VSCALEFSSZrr = 21300 + + VSCALEFSSZrrb_Int = 21301 + + VSCALEFSSZrrbk_Int = 21302 + + VSCALEFSSZrrbkz_Int = 21303 + + VSCALEFSSZrrk = 21304 + + VSCALEFSSZrrkz = 21305 + + VSCATTERDPDZ128mr = 21306 + + VSCATTERDPDZ256mr = 21307 + + VSCATTERDPDZmr = 21308 + + VSCATTERDPSZ128mr = 21309 + + VSCATTERDPSZ256mr = 21310 + + VSCATTERDPSZmr = 21311 + + VSCATTERPF0DPDm = 21312 + + VSCATTERPF0DPSm = 21313 + + VSCATTERPF0QPDm = 21314 + + VSCATTERPF0QPSm = 21315 + + VSCATTERPF1DPDm = 21316 + + VSCATTERPF1DPSm = 21317 + + VSCATTERPF1QPDm = 21318 + + VSCATTERPF1QPSm = 21319 + + VSCATTERQPDZ128mr = 21320 + + VSCATTERQPDZ256mr = 21321 + + VSCATTERQPDZmr = 21322 + + VSCATTERQPSZ128mr = 21323 + + VSCATTERQPSZ256mr = 21324 + + VSCATTERQPSZmr = 21325 + + VSHA512MSG1rr = 21326 + + VSHA512MSG2rr = 21327 + + VSHA512RNDS2rr = 21328 + + VSHUFF32X4Z256rmbi = 21329 + + VSHUFF32X4Z256rmbik = 21330 + + VSHUFF32X4Z256rmbikz = 21331 + + VSHUFF32X4Z256rmi = 21332 + + VSHUFF32X4Z256rmik = 21333 + + VSHUFF32X4Z256rmikz = 21334 + + VSHUFF32X4Z256rri = 21335 + + VSHUFF32X4Z256rrik = 21336 + + VSHUFF32X4Z256rrikz = 21337 + + VSHUFF32X4Zrmbi = 21338 + + VSHUFF32X4Zrmbik = 21339 + + VSHUFF32X4Zrmbikz = 21340 + + VSHUFF32X4Zrmi = 21341 + + VSHUFF32X4Zrmik = 21342 + + VSHUFF32X4Zrmikz = 21343 + + VSHUFF32X4Zrri = 21344 + + VSHUFF32X4Zrrik = 21345 + + VSHUFF32X4Zrrikz = 21346 + + VSHUFF64X2Z256rmbi = 21347 + + VSHUFF64X2Z256rmbik = 21348 + + VSHUFF64X2Z256rmbikz = 21349 + + VSHUFF64X2Z256rmi = 21350 + + VSHUFF64X2Z256rmik = 21351 + + VSHUFF64X2Z256rmikz = 21352 + + VSHUFF64X2Z256rri = 21353 + + VSHUFF64X2Z256rrik = 21354 + + VSHUFF64X2Z256rrikz = 21355 + + VSHUFF64X2Zrmbi = 21356 + + VSHUFF64X2Zrmbik = 21357 + + VSHUFF64X2Zrmbikz = 21358 + + VSHUFF64X2Zrmi = 21359 + + VSHUFF64X2Zrmik = 21360 + + VSHUFF64X2Zrmikz = 21361 + + VSHUFF64X2Zrri = 21362 + + VSHUFF64X2Zrrik = 21363 + + VSHUFF64X2Zrrikz = 21364 + + VSHUFI32X4Z256rmbi = 21365 + + VSHUFI32X4Z256rmbik = 21366 + + VSHUFI32X4Z256rmbikz = 21367 + + VSHUFI32X4Z256rmi = 21368 + + VSHUFI32X4Z256rmik = 21369 + + VSHUFI32X4Z256rmikz = 21370 + + VSHUFI32X4Z256rri = 21371 + + VSHUFI32X4Z256rrik = 21372 + + VSHUFI32X4Z256rrikz = 21373 + + VSHUFI32X4Zrmbi = 21374 + + VSHUFI32X4Zrmbik = 21375 + + VSHUFI32X4Zrmbikz = 21376 + + VSHUFI32X4Zrmi = 21377 + + VSHUFI32X4Zrmik = 21378 + + VSHUFI32X4Zrmikz = 21379 + + VSHUFI32X4Zrri = 21380 + + VSHUFI32X4Zrrik = 21381 + + VSHUFI32X4Zrrikz = 21382 + + VSHUFI64X2Z256rmbi = 21383 + + VSHUFI64X2Z256rmbik = 21384 + + VSHUFI64X2Z256rmbikz = 21385 + + VSHUFI64X2Z256rmi = 21386 + + VSHUFI64X2Z256rmik = 21387 + + VSHUFI64X2Z256rmikz = 21388 + + VSHUFI64X2Z256rri = 21389 + + VSHUFI64X2Z256rrik = 21390 + + VSHUFI64X2Z256rrikz = 21391 + + VSHUFI64X2Zrmbi = 21392 + + VSHUFI64X2Zrmbik = 21393 + + VSHUFI64X2Zrmbikz = 21394 + + VSHUFI64X2Zrmi = 21395 + + VSHUFI64X2Zrmik = 21396 + + VSHUFI64X2Zrmikz = 21397 + + VSHUFI64X2Zrri = 21398 + + VSHUFI64X2Zrrik = 21399 + + VSHUFI64X2Zrrikz = 21400 + + VSHUFPDYrmi = 21401 + + VSHUFPDYrri = 21402 + + VSHUFPDZ128rmbi = 21403 + + VSHUFPDZ128rmbik = 21404 + + VSHUFPDZ128rmbikz = 21405 + + VSHUFPDZ128rmi = 21406 + + VSHUFPDZ128rmik = 21407 + + VSHUFPDZ128rmikz = 21408 + + VSHUFPDZ128rri = 21409 + + VSHUFPDZ128rrik = 21410 + + VSHUFPDZ128rrikz = 21411 + + VSHUFPDZ256rmbi = 21412 + + VSHUFPDZ256rmbik = 21413 + + VSHUFPDZ256rmbikz = 21414 + + VSHUFPDZ256rmi = 21415 + + VSHUFPDZ256rmik = 21416 + + VSHUFPDZ256rmikz = 21417 + + VSHUFPDZ256rri = 21418 + + VSHUFPDZ256rrik = 21419 + + VSHUFPDZ256rrikz = 21420 + + VSHUFPDZrmbi = 21421 + + VSHUFPDZrmbik = 21422 + + VSHUFPDZrmbikz = 21423 + + VSHUFPDZrmi = 21424 + + VSHUFPDZrmik = 21425 + + VSHUFPDZrmikz = 21426 + + VSHUFPDZrri = 21427 + + VSHUFPDZrrik = 21428 + + VSHUFPDZrrikz = 21429 + + VSHUFPDrmi = 21430 + + VSHUFPDrri = 21431 + + VSHUFPSYrmi = 21432 + + VSHUFPSYrri = 21433 + + VSHUFPSZ128rmbi = 21434 + + VSHUFPSZ128rmbik = 21435 + + VSHUFPSZ128rmbikz = 21436 + + VSHUFPSZ128rmi = 21437 + + VSHUFPSZ128rmik = 21438 + + VSHUFPSZ128rmikz = 21439 + + VSHUFPSZ128rri = 21440 + + VSHUFPSZ128rrik = 21441 + + VSHUFPSZ128rrikz = 21442 + + VSHUFPSZ256rmbi = 21443 + + VSHUFPSZ256rmbik = 21444 + + VSHUFPSZ256rmbikz = 21445 + + VSHUFPSZ256rmi = 21446 + + VSHUFPSZ256rmik = 21447 + + VSHUFPSZ256rmikz = 21448 + + VSHUFPSZ256rri = 21449 + + VSHUFPSZ256rrik = 21450 + + VSHUFPSZ256rrikz = 21451 + + VSHUFPSZrmbi = 21452 + + VSHUFPSZrmbik = 21453 + + VSHUFPSZrmbikz = 21454 + + VSHUFPSZrmi = 21455 + + VSHUFPSZrmik = 21456 + + VSHUFPSZrmikz = 21457 + + VSHUFPSZrri = 21458 + + VSHUFPSZrrik = 21459 + + VSHUFPSZrrikz = 21460 + + VSHUFPSrmi = 21461 + + VSHUFPSrri = 21462 + + VSM3MSG1rm = 21463 + + VSM3MSG1rr = 21464 + + VSM3MSG2rm = 21465 + + VSM3MSG2rr = 21466 + + VSM3RNDS2rmi = 21467 + + VSM3RNDS2rri = 21468 + + VSM4KEY4Yrm = 21469 + + VSM4KEY4Yrr = 21470 + + VSM4KEY4Z128rm = 21471 + + VSM4KEY4Z128rr = 21472 + + VSM4KEY4Z256rm = 21473 + + VSM4KEY4Z256rr = 21474 + + VSM4KEY4Zrm = 21475 + + VSM4KEY4Zrr = 21476 + + VSM4KEY4rm = 21477 + + VSM4KEY4rr = 21478 + + VSM4RNDS4Yrm = 21479 + + VSM4RNDS4Yrr = 21480 + + VSM4RNDS4Z128rm = 21481 + + VSM4RNDS4Z128rr = 21482 + + VSM4RNDS4Z256rm = 21483 + + VSM4RNDS4Z256rr = 21484 + + VSM4RNDS4Zrm = 21485 + + VSM4RNDS4Zrr = 21486 + + VSM4RNDS4rm = 21487 + + VSM4RNDS4rr = 21488 + + VSQRTBF16Z128m = 21489 + + VSQRTBF16Z128mb = 21490 + + VSQRTBF16Z128mbk = 21491 + + VSQRTBF16Z128mbkz = 21492 + + VSQRTBF16Z128mk = 21493 + + VSQRTBF16Z128mkz = 21494 + + VSQRTBF16Z128r = 21495 + + VSQRTBF16Z128rk = 21496 + + VSQRTBF16Z128rkz = 21497 + + VSQRTBF16Z256m = 21498 + + VSQRTBF16Z256mb = 21499 + + VSQRTBF16Z256mbk = 21500 + + VSQRTBF16Z256mbkz = 21501 + + VSQRTBF16Z256mk = 21502 + + VSQRTBF16Z256mkz = 21503 + + VSQRTBF16Z256r = 21504 + + VSQRTBF16Z256rk = 21505 + + VSQRTBF16Z256rkz = 21506 + + VSQRTBF16Zm = 21507 + + VSQRTBF16Zmb = 21508 + + VSQRTBF16Zmbk = 21509 + + VSQRTBF16Zmbkz = 21510 + + VSQRTBF16Zmk = 21511 + + VSQRTBF16Zmkz = 21512 + + VSQRTBF16Zr = 21513 + + VSQRTBF16Zrk = 21514 + + VSQRTBF16Zrkz = 21515 + + VSQRTPDYm = 21516 + + VSQRTPDYr = 21517 + + VSQRTPDZ128m = 21518 + + VSQRTPDZ128mb = 21519 + + VSQRTPDZ128mbk = 21520 + + VSQRTPDZ128mbkz = 21521 + + VSQRTPDZ128mk = 21522 + + VSQRTPDZ128mkz = 21523 + + VSQRTPDZ128r = 21524 + + VSQRTPDZ128rk = 21525 + + VSQRTPDZ128rkz = 21526 + + VSQRTPDZ256m = 21527 + + VSQRTPDZ256mb = 21528 + + VSQRTPDZ256mbk = 21529 + + VSQRTPDZ256mbkz = 21530 + + VSQRTPDZ256mk = 21531 + + VSQRTPDZ256mkz = 21532 + + VSQRTPDZ256r = 21533 + + VSQRTPDZ256rk = 21534 + + VSQRTPDZ256rkz = 21535 + + VSQRTPDZm = 21536 + + VSQRTPDZmb = 21537 + + VSQRTPDZmbk = 21538 + + VSQRTPDZmbkz = 21539 + + VSQRTPDZmk = 21540 + + VSQRTPDZmkz = 21541 + + VSQRTPDZr = 21542 + + VSQRTPDZrb = 21543 + + VSQRTPDZrbk = 21544 + + VSQRTPDZrbkz = 21545 + + VSQRTPDZrk = 21546 + + VSQRTPDZrkz = 21547 + + VSQRTPDm = 21548 + + VSQRTPDr = 21549 + + VSQRTPHZ128m = 21550 + + VSQRTPHZ128mb = 21551 + + VSQRTPHZ128mbk = 21552 + + VSQRTPHZ128mbkz = 21553 + + VSQRTPHZ128mk = 21554 + + VSQRTPHZ128mkz = 21555 + + VSQRTPHZ128r = 21556 + + VSQRTPHZ128rk = 21557 + + VSQRTPHZ128rkz = 21558 + + VSQRTPHZ256m = 21559 + + VSQRTPHZ256mb = 21560 + + VSQRTPHZ256mbk = 21561 + + VSQRTPHZ256mbkz = 21562 + + VSQRTPHZ256mk = 21563 + + VSQRTPHZ256mkz = 21564 + + VSQRTPHZ256r = 21565 + + VSQRTPHZ256rk = 21566 + + VSQRTPHZ256rkz = 21567 + + VSQRTPHZm = 21568 + + VSQRTPHZmb = 21569 + + VSQRTPHZmbk = 21570 + + VSQRTPHZmbkz = 21571 + + VSQRTPHZmk = 21572 + + VSQRTPHZmkz = 21573 + + VSQRTPHZr = 21574 + + VSQRTPHZrb = 21575 + + VSQRTPHZrbk = 21576 + + VSQRTPHZrbkz = 21577 + + VSQRTPHZrk = 21578 + + VSQRTPHZrkz = 21579 + + VSQRTPSYm = 21580 + + VSQRTPSYr = 21581 + + VSQRTPSZ128m = 21582 + + VSQRTPSZ128mb = 21583 + + VSQRTPSZ128mbk = 21584 + + VSQRTPSZ128mbkz = 21585 + + VSQRTPSZ128mk = 21586 + + VSQRTPSZ128mkz = 21587 + + VSQRTPSZ128r = 21588 + + VSQRTPSZ128rk = 21589 + + VSQRTPSZ128rkz = 21590 + + VSQRTPSZ256m = 21591 + + VSQRTPSZ256mb = 21592 + + VSQRTPSZ256mbk = 21593 + + VSQRTPSZ256mbkz = 21594 + + VSQRTPSZ256mk = 21595 + + VSQRTPSZ256mkz = 21596 + + VSQRTPSZ256r = 21597 + + VSQRTPSZ256rk = 21598 + + VSQRTPSZ256rkz = 21599 + + VSQRTPSZm = 21600 + + VSQRTPSZmb = 21601 + + VSQRTPSZmbk = 21602 + + VSQRTPSZmbkz = 21603 + + VSQRTPSZmk = 21604 + + VSQRTPSZmkz = 21605 + + VSQRTPSZr = 21606 + + VSQRTPSZrb = 21607 + + VSQRTPSZrbk = 21608 + + VSQRTPSZrbkz = 21609 + + VSQRTPSZrk = 21610 + + VSQRTPSZrkz = 21611 + + VSQRTPSm = 21612 + + VSQRTPSr = 21613 + + VSQRTSDZm = 21614 + + VSQRTSDZm_Int = 21615 + + VSQRTSDZmk_Int = 21616 + + VSQRTSDZmkz_Int = 21617 + + VSQRTSDZr = 21618 + + VSQRTSDZr_Int = 21619 + + VSQRTSDZrb_Int = 21620 + + VSQRTSDZrbk_Int = 21621 + + VSQRTSDZrbkz_Int = 21622 + + VSQRTSDZrk_Int = 21623 + + VSQRTSDZrkz_Int = 21624 + + VSQRTSDm = 21625 + + VSQRTSDm_Int = 21626 + + VSQRTSDr = 21627 + + VSQRTSDr_Int = 21628 + + VSQRTSHZm = 21629 + + VSQRTSHZm_Int = 21630 + + VSQRTSHZmk_Int = 21631 + + VSQRTSHZmkz_Int = 21632 + + VSQRTSHZr = 21633 + + VSQRTSHZr_Int = 21634 + + VSQRTSHZrb_Int = 21635 + + VSQRTSHZrbk_Int = 21636 + + VSQRTSHZrbkz_Int = 21637 + + VSQRTSHZrk_Int = 21638 + + VSQRTSHZrkz_Int = 21639 + + VSQRTSSZm = 21640 + + VSQRTSSZm_Int = 21641 + + VSQRTSSZmk_Int = 21642 + + VSQRTSSZmkz_Int = 21643 + + VSQRTSSZr = 21644 + + VSQRTSSZr_Int = 21645 + + VSQRTSSZrb_Int = 21646 + + VSQRTSSZrbk_Int = 21647 + + VSQRTSSZrbkz_Int = 21648 + + VSQRTSSZrk_Int = 21649 + + VSQRTSSZrkz_Int = 21650 + + VSQRTSSm = 21651 + + VSQRTSSm_Int = 21652 + + VSQRTSSr = 21653 + + VSQRTSSr_Int = 21654 + + VSTMXCSR = 21655 + + VSUBBF16Z128rm = 21656 + + VSUBBF16Z128rmb = 21657 + + VSUBBF16Z128rmbk = 21658 + + VSUBBF16Z128rmbkz = 21659 + + VSUBBF16Z128rmk = 21660 + + VSUBBF16Z128rmkz = 21661 + + VSUBBF16Z128rr = 21662 + + VSUBBF16Z128rrk = 21663 + + VSUBBF16Z128rrkz = 21664 + + VSUBBF16Z256rm = 21665 + + VSUBBF16Z256rmb = 21666 + + VSUBBF16Z256rmbk = 21667 + + VSUBBF16Z256rmbkz = 21668 + + VSUBBF16Z256rmk = 21669 + + VSUBBF16Z256rmkz = 21670 + + VSUBBF16Z256rr = 21671 + + VSUBBF16Z256rrk = 21672 + + VSUBBF16Z256rrkz = 21673 + + VSUBBF16Zrm = 21674 + + VSUBBF16Zrmb = 21675 + + VSUBBF16Zrmbk = 21676 + + VSUBBF16Zrmbkz = 21677 + + VSUBBF16Zrmk = 21678 + + VSUBBF16Zrmkz = 21679 + + VSUBBF16Zrr = 21680 + + VSUBBF16Zrrk = 21681 + + VSUBBF16Zrrkz = 21682 + + VSUBPDYrm = 21683 + + VSUBPDYrr = 21684 + + VSUBPDZ128rm = 21685 + + VSUBPDZ128rmb = 21686 + + VSUBPDZ128rmbk = 21687 + + VSUBPDZ128rmbkz = 21688 + + VSUBPDZ128rmk = 21689 + + VSUBPDZ128rmkz = 21690 + + VSUBPDZ128rr = 21691 + + VSUBPDZ128rrk = 21692 + + VSUBPDZ128rrkz = 21693 + + VSUBPDZ256rm = 21694 + + VSUBPDZ256rmb = 21695 + + VSUBPDZ256rmbk = 21696 + + VSUBPDZ256rmbkz = 21697 + + VSUBPDZ256rmk = 21698 + + VSUBPDZ256rmkz = 21699 + + VSUBPDZ256rr = 21700 + + VSUBPDZ256rrk = 21701 + + VSUBPDZ256rrkz = 21702 + + VSUBPDZrm = 21703 + + VSUBPDZrmb = 21704 + + VSUBPDZrmbk = 21705 + + VSUBPDZrmbkz = 21706 + + VSUBPDZrmk = 21707 + + VSUBPDZrmkz = 21708 + + VSUBPDZrr = 21709 + + VSUBPDZrrb = 21710 + + VSUBPDZrrbk = 21711 + + VSUBPDZrrbkz = 21712 + + VSUBPDZrrk = 21713 + + VSUBPDZrrkz = 21714 + + VSUBPDrm = 21715 + + VSUBPDrr = 21716 + + VSUBPHZ128rm = 21717 + + VSUBPHZ128rmb = 21718 + + VSUBPHZ128rmbk = 21719 + + VSUBPHZ128rmbkz = 21720 + + VSUBPHZ128rmk = 21721 + + VSUBPHZ128rmkz = 21722 + + VSUBPHZ128rr = 21723 + + VSUBPHZ128rrk = 21724 + + VSUBPHZ128rrkz = 21725 + + VSUBPHZ256rm = 21726 + + VSUBPHZ256rmb = 21727 + + VSUBPHZ256rmbk = 21728 + + VSUBPHZ256rmbkz = 21729 + + VSUBPHZ256rmk = 21730 + + VSUBPHZ256rmkz = 21731 + + VSUBPHZ256rr = 21732 + + VSUBPHZ256rrk = 21733 + + VSUBPHZ256rrkz = 21734 + + VSUBPHZrm = 21735 + + VSUBPHZrmb = 21736 + + VSUBPHZrmbk = 21737 + + VSUBPHZrmbkz = 21738 + + VSUBPHZrmk = 21739 + + VSUBPHZrmkz = 21740 + + VSUBPHZrr = 21741 + + VSUBPHZrrb = 21742 + + VSUBPHZrrbk = 21743 + + VSUBPHZrrbkz = 21744 + + VSUBPHZrrk = 21745 + + VSUBPHZrrkz = 21746 + + VSUBPSYrm = 21747 + + VSUBPSYrr = 21748 + + VSUBPSZ128rm = 21749 + + VSUBPSZ128rmb = 21750 + + VSUBPSZ128rmbk = 21751 + + VSUBPSZ128rmbkz = 21752 + + VSUBPSZ128rmk = 21753 + + VSUBPSZ128rmkz = 21754 + + VSUBPSZ128rr = 21755 + + VSUBPSZ128rrk = 21756 + + VSUBPSZ128rrkz = 21757 + + VSUBPSZ256rm = 21758 + + VSUBPSZ256rmb = 21759 + + VSUBPSZ256rmbk = 21760 + + VSUBPSZ256rmbkz = 21761 + + VSUBPSZ256rmk = 21762 + + VSUBPSZ256rmkz = 21763 + + VSUBPSZ256rr = 21764 + + VSUBPSZ256rrk = 21765 + + VSUBPSZ256rrkz = 21766 + + VSUBPSZrm = 21767 + + VSUBPSZrmb = 21768 + + VSUBPSZrmbk = 21769 + + VSUBPSZrmbkz = 21770 + + VSUBPSZrmk = 21771 + + VSUBPSZrmkz = 21772 + + VSUBPSZrr = 21773 + + VSUBPSZrrb = 21774 + + VSUBPSZrrbk = 21775 + + VSUBPSZrrbkz = 21776 + + VSUBPSZrrk = 21777 + + VSUBPSZrrkz = 21778 + + VSUBPSrm = 21779 + + VSUBPSrr = 21780 + + VSUBSDZrm = 21781 + + VSUBSDZrm_Int = 21782 + + VSUBSDZrmk_Int = 21783 + + VSUBSDZrmkz_Int = 21784 + + VSUBSDZrr = 21785 + + VSUBSDZrr_Int = 21786 + + VSUBSDZrrb_Int = 21787 + + VSUBSDZrrbk_Int = 21788 + + VSUBSDZrrbkz_Int = 21789 + + VSUBSDZrrk_Int = 21790 + + VSUBSDZrrkz_Int = 21791 + + VSUBSDrm = 21792 + + VSUBSDrm_Int = 21793 + + VSUBSDrr = 21794 + + VSUBSDrr_Int = 21795 + + VSUBSHZrm = 21796 + + VSUBSHZrm_Int = 21797 + + VSUBSHZrmk_Int = 21798 + + VSUBSHZrmkz_Int = 21799 + + VSUBSHZrr = 21800 + + VSUBSHZrr_Int = 21801 + + VSUBSHZrrb_Int = 21802 + + VSUBSHZrrbk_Int = 21803 + + VSUBSHZrrbkz_Int = 21804 + + VSUBSHZrrk_Int = 21805 + + VSUBSHZrrkz_Int = 21806 + + VSUBSSZrm = 21807 + + VSUBSSZrm_Int = 21808 + + VSUBSSZrmk_Int = 21809 + + VSUBSSZrmkz_Int = 21810 + + VSUBSSZrr = 21811 + + VSUBSSZrr_Int = 21812 + + VSUBSSZrrb_Int = 21813 + + VSUBSSZrrbk_Int = 21814 + + VSUBSSZrrbkz_Int = 21815 + + VSUBSSZrrk_Int = 21816 + + VSUBSSZrrkz_Int = 21817 + + VSUBSSrm = 21818 + + VSUBSSrm_Int = 21819 + + VSUBSSrr = 21820 + + VSUBSSrr_Int = 21821 + + VTESTPDYrm = 21822 + + VTESTPDYrr = 21823 + + VTESTPDrm = 21824 + + VTESTPDrr = 21825 + + VTESTPSYrm = 21826 + + VTESTPSYrr = 21827 + + VTESTPSrm = 21828 + + VTESTPSrr = 21829 + + VUCOMISDZrm = 21830 + + VUCOMISDZrm_Int = 21831 + + VUCOMISDZrr = 21832 + + VUCOMISDZrr_Int = 21833 + + VUCOMISDZrrb = 21834 + + VUCOMISDrm = 21835 + + VUCOMISDrm_Int = 21836 + + VUCOMISDrr = 21837 + + VUCOMISDrr_Int = 21838 + + VUCOMISHZrm = 21839 + + VUCOMISHZrm_Int = 21840 + + VUCOMISHZrr = 21841 + + VUCOMISHZrr_Int = 21842 + + VUCOMISHZrrb = 21843 + + VUCOMISSZrm = 21844 + + VUCOMISSZrm_Int = 21845 + + VUCOMISSZrr = 21846 + + VUCOMISSZrr_Int = 21847 + + VUCOMISSZrrb = 21848 + + VUCOMISSrm = 21849 + + VUCOMISSrm_Int = 21850 + + VUCOMISSrr = 21851 + + VUCOMISSrr_Int = 21852 + + VUCOMXSDZrm = 21853 + + VUCOMXSDZrm_Int = 21854 + + VUCOMXSDZrr = 21855 + + VUCOMXSDZrr_Int = 21856 + + VUCOMXSDZrrb_Int = 21857 + + VUCOMXSHZrm = 21858 + + VUCOMXSHZrm_Int = 21859 + + VUCOMXSHZrr = 21860 + + VUCOMXSHZrr_Int = 21861 + + VUCOMXSHZrrb_Int = 21862 + + VUCOMXSSZrm = 21863 + + VUCOMXSSZrm_Int = 21864 + + VUCOMXSSZrr = 21865 + + VUCOMXSSZrr_Int = 21866 + + VUCOMXSSZrrb_Int = 21867 + + VUNPCKHPDYrm = 21868 + + VUNPCKHPDYrr = 21869 + + VUNPCKHPDZ128rm = 21870 + + VUNPCKHPDZ128rmb = 21871 + + VUNPCKHPDZ128rmbk = 21872 + + VUNPCKHPDZ128rmbkz = 21873 + + VUNPCKHPDZ128rmk = 21874 + + VUNPCKHPDZ128rmkz = 21875 + + VUNPCKHPDZ128rr = 21876 + + VUNPCKHPDZ128rrk = 21877 + + VUNPCKHPDZ128rrkz = 21878 + + VUNPCKHPDZ256rm = 21879 + + VUNPCKHPDZ256rmb = 21880 + + VUNPCKHPDZ256rmbk = 21881 + + VUNPCKHPDZ256rmbkz = 21882 + + VUNPCKHPDZ256rmk = 21883 + + VUNPCKHPDZ256rmkz = 21884 + + VUNPCKHPDZ256rr = 21885 + + VUNPCKHPDZ256rrk = 21886 + + VUNPCKHPDZ256rrkz = 21887 + + VUNPCKHPDZrm = 21888 + + VUNPCKHPDZrmb = 21889 + + VUNPCKHPDZrmbk = 21890 + + VUNPCKHPDZrmbkz = 21891 + + VUNPCKHPDZrmk = 21892 + + VUNPCKHPDZrmkz = 21893 + + VUNPCKHPDZrr = 21894 + + VUNPCKHPDZrrk = 21895 + + VUNPCKHPDZrrkz = 21896 + + VUNPCKHPDrm = 21897 + + VUNPCKHPDrr = 21898 + + VUNPCKHPSYrm = 21899 + + VUNPCKHPSYrr = 21900 + + VUNPCKHPSZ128rm = 21901 + + VUNPCKHPSZ128rmb = 21902 + + VUNPCKHPSZ128rmbk = 21903 + + VUNPCKHPSZ128rmbkz = 21904 + + VUNPCKHPSZ128rmk = 21905 + + VUNPCKHPSZ128rmkz = 21906 + + VUNPCKHPSZ128rr = 21907 + + VUNPCKHPSZ128rrk = 21908 + + VUNPCKHPSZ128rrkz = 21909 + + VUNPCKHPSZ256rm = 21910 + + VUNPCKHPSZ256rmb = 21911 + + VUNPCKHPSZ256rmbk = 21912 + + VUNPCKHPSZ256rmbkz = 21913 + + VUNPCKHPSZ256rmk = 21914 + + VUNPCKHPSZ256rmkz = 21915 + + VUNPCKHPSZ256rr = 21916 + + VUNPCKHPSZ256rrk = 21917 + + VUNPCKHPSZ256rrkz = 21918 + + VUNPCKHPSZrm = 21919 + + VUNPCKHPSZrmb = 21920 + + VUNPCKHPSZrmbk = 21921 + + VUNPCKHPSZrmbkz = 21922 + + VUNPCKHPSZrmk = 21923 + + VUNPCKHPSZrmkz = 21924 + + VUNPCKHPSZrr = 21925 + + VUNPCKHPSZrrk = 21926 + + VUNPCKHPSZrrkz = 21927 + + VUNPCKHPSrm = 21928 + + VUNPCKHPSrr = 21929 + + VUNPCKLPDYrm = 21930 + + VUNPCKLPDYrr = 21931 + + VUNPCKLPDZ128rm = 21932 + + VUNPCKLPDZ128rmb = 21933 + + VUNPCKLPDZ128rmbk = 21934 + + VUNPCKLPDZ128rmbkz = 21935 + + VUNPCKLPDZ128rmk = 21936 + + VUNPCKLPDZ128rmkz = 21937 + + VUNPCKLPDZ128rr = 21938 + + VUNPCKLPDZ128rrk = 21939 + + VUNPCKLPDZ128rrkz = 21940 + + VUNPCKLPDZ256rm = 21941 + + VUNPCKLPDZ256rmb = 21942 + + VUNPCKLPDZ256rmbk = 21943 + + VUNPCKLPDZ256rmbkz = 21944 + + VUNPCKLPDZ256rmk = 21945 + + VUNPCKLPDZ256rmkz = 21946 + + VUNPCKLPDZ256rr = 21947 + + VUNPCKLPDZ256rrk = 21948 + + VUNPCKLPDZ256rrkz = 21949 + + VUNPCKLPDZrm = 21950 + + VUNPCKLPDZrmb = 21951 + + VUNPCKLPDZrmbk = 21952 + + VUNPCKLPDZrmbkz = 21953 + + VUNPCKLPDZrmk = 21954 + + VUNPCKLPDZrmkz = 21955 + + VUNPCKLPDZrr = 21956 + + VUNPCKLPDZrrk = 21957 + + VUNPCKLPDZrrkz = 21958 + + VUNPCKLPDrm = 21959 + + VUNPCKLPDrr = 21960 + + VUNPCKLPSYrm = 21961 + + VUNPCKLPSYrr = 21962 + + VUNPCKLPSZ128rm = 21963 + + VUNPCKLPSZ128rmb = 21964 + + VUNPCKLPSZ128rmbk = 21965 + + VUNPCKLPSZ128rmbkz = 21966 + + VUNPCKLPSZ128rmk = 21967 + + VUNPCKLPSZ128rmkz = 21968 + + VUNPCKLPSZ128rr = 21969 + + VUNPCKLPSZ128rrk = 21970 + + VUNPCKLPSZ128rrkz = 21971 + + VUNPCKLPSZ256rm = 21972 + + VUNPCKLPSZ256rmb = 21973 + + VUNPCKLPSZ256rmbk = 21974 + + VUNPCKLPSZ256rmbkz = 21975 + + VUNPCKLPSZ256rmk = 21976 + + VUNPCKLPSZ256rmkz = 21977 + + VUNPCKLPSZ256rr = 21978 + + VUNPCKLPSZ256rrk = 21979 + + VUNPCKLPSZ256rrkz = 21980 + + VUNPCKLPSZrm = 21981 + + VUNPCKLPSZrmb = 21982 + + VUNPCKLPSZrmbk = 21983 + + VUNPCKLPSZrmbkz = 21984 + + VUNPCKLPSZrmk = 21985 + + VUNPCKLPSZrmkz = 21986 + + VUNPCKLPSZrr = 21987 + + VUNPCKLPSZrrk = 21988 + + VUNPCKLPSZrrkz = 21989 + + VUNPCKLPSrm = 21990 + + VUNPCKLPSrr = 21991 + + VXORPDYrm = 21992 + + VXORPDYrr = 21993 + + VXORPDZ128rm = 21994 + + VXORPDZ128rmb = 21995 + + VXORPDZ128rmbk = 21996 + + VXORPDZ128rmbkz = 21997 + + VXORPDZ128rmk = 21998 + + VXORPDZ128rmkz = 21999 + + VXORPDZ128rr = 22000 + + VXORPDZ128rrk = 22001 + + VXORPDZ128rrkz = 22002 + + VXORPDZ256rm = 22003 + + VXORPDZ256rmb = 22004 + + VXORPDZ256rmbk = 22005 + + VXORPDZ256rmbkz = 22006 + + VXORPDZ256rmk = 22007 + + VXORPDZ256rmkz = 22008 + + VXORPDZ256rr = 22009 + + VXORPDZ256rrk = 22010 + + VXORPDZ256rrkz = 22011 + + VXORPDZrm = 22012 + + VXORPDZrmb = 22013 + + VXORPDZrmbk = 22014 + + VXORPDZrmbkz = 22015 + + VXORPDZrmk = 22016 + + VXORPDZrmkz = 22017 + + VXORPDZrr = 22018 + + VXORPDZrrk = 22019 + + VXORPDZrrkz = 22020 + + VXORPDrm = 22021 + + VXORPDrr = 22022 + + VXORPSYrm = 22023 + + VXORPSYrr = 22024 + + VXORPSZ128rm = 22025 + + VXORPSZ128rmb = 22026 + + VXORPSZ128rmbk = 22027 + + VXORPSZ128rmbkz = 22028 + + VXORPSZ128rmk = 22029 + + VXORPSZ128rmkz = 22030 + + VXORPSZ128rr = 22031 + + VXORPSZ128rrk = 22032 + + VXORPSZ128rrkz = 22033 + + VXORPSZ256rm = 22034 + + VXORPSZ256rmb = 22035 + + VXORPSZ256rmbk = 22036 + + VXORPSZ256rmbkz = 22037 + + VXORPSZ256rmk = 22038 + + VXORPSZ256rmkz = 22039 + + VXORPSZ256rr = 22040 + + VXORPSZ256rrk = 22041 + + VXORPSZ256rrkz = 22042 + + VXORPSZrm = 22043 + + VXORPSZrmb = 22044 + + VXORPSZrmbk = 22045 + + VXORPSZrmbkz = 22046 + + VXORPSZrmk = 22047 + + VXORPSZrmkz = 22048 + + VXORPSZrr = 22049 + + VXORPSZrrk = 22050 + + VXORPSZrrkz = 22051 + + VXORPSrm = 22052 + + VXORPSrr = 22053 + + VZEROALL = 22054 + + VZEROUPPER = 22055 + + WAIT = 22056 + + WBINVD = 22057 + + WBNOINVD = 22058 + + WRFSBASE = 22059 + + WRFSBASE64 = 22060 + + WRGSBASE = 22061 + + WRGSBASE64 = 22062 + + WRMSR = 22063 + + WRMSRLIST = 22064 + + WRMSRNS = 22065 + + WRMSRNSir = 22066 + + WRMSRNSir_EVEX = 22067 + + WRPKRUr = 22068 + + WRSSD = 22069 + + WRSSD_EVEX = 22070 + + WRSSQ = 22071 + + WRSSQ_EVEX = 22072 + + WRUSSD = 22073 + + WRUSSD_EVEX = 22074 + + WRUSSQ = 22075 + + WRUSSQ_EVEX = 22076 + + XABORT = 22077 + + XACQUIRE_PREFIX = 22078 + + XADD16rm = 22079 + + XADD16rr = 22080 + + XADD32rm = 22081 + + XADD32rr = 22082 + + XADD64rm = 22083 + + XADD64rr = 22084 + + XADD8rm = 22085 + + XADD8rr = 22086 + + XAM_F = 22087 + + XAM_Fp32 = 22088 + + XAM_Fp64 = 22089 + + XAM_Fp80 = 22090 + + XBEGIN = 22091 + + XBEGIN_2 = 22092 + + XBEGIN_4 = 22093 + + XCHG16ar = 22094 + + XCHG16rm = 22095 + + XCHG16rr = 22096 + + XCHG32ar = 22097 + + XCHG32rm = 22098 + + XCHG32rr = 22099 + + XCHG64ar = 22100 + + XCHG64rm = 22101 + + XCHG64rr = 22102 + + XCHG8rm = 22103 + + XCHG8rr = 22104 + + XCH_F = 22105 + + XCRYPTCBC = 22106 + + XCRYPTCFB = 22107 + + XCRYPTCTR = 22108 + + XCRYPTECB = 22109 + + XCRYPTOFB = 22110 + + XEND = 22111 + + XGETBV = 22112 + + XLAT = 22113 + + XOR16i16 = 22114 + + XOR16mi = 22115 + + XOR16mi8 = 22116 + + XOR16mi8_EVEX = 22117 + + XOR16mi8_ND = 22118 + + XOR16mi8_NF = 22119 + + XOR16mi8_NF_ND = 22120 + + XOR16mi_EVEX = 22121 + + XOR16mi_ND = 22122 + + XOR16mi_NF = 22123 + + XOR16mi_NF_ND = 22124 + + XOR16mr = 22125 + + XOR16mr_EVEX = 22126 + + XOR16mr_ND = 22127 + + XOR16mr_NF = 22128 + + XOR16mr_NF_ND = 22129 + + XOR16ri = 22130 + + XOR16ri8 = 22131 + + XOR16ri8_EVEX = 22132 + + XOR16ri8_ND = 22133 + + XOR16ri8_NF = 22134 + + XOR16ri8_NF_ND = 22135 + + XOR16ri_EVEX = 22136 + + XOR16ri_ND = 22137 + + XOR16ri_NF = 22138 + + XOR16ri_NF_ND = 22139 + + XOR16rm = 22140 + + XOR16rm_EVEX = 22141 + + XOR16rm_ND = 22142 + + XOR16rm_NF = 22143 + + XOR16rm_NF_ND = 22144 + + XOR16rr = 22145 + + XOR16rr_EVEX = 22146 + + XOR16rr_EVEX_REV = 22147 + + XOR16rr_ND = 22148 + + XOR16rr_ND_REV = 22149 + + XOR16rr_NF = 22150 + + XOR16rr_NF_ND = 22151 + + XOR16rr_NF_ND_REV = 22152 + + XOR16rr_NF_REV = 22153 + + XOR16rr_REV = 22154 + + XOR32i32 = 22155 + + XOR32mi = 22156 + + XOR32mi8 = 22157 + + XOR32mi8_EVEX = 22158 + + XOR32mi8_ND = 22159 + + XOR32mi8_NF = 22160 + + XOR32mi8_NF_ND = 22161 + + XOR32mi_EVEX = 22162 + + XOR32mi_ND = 22163 + + XOR32mi_NF = 22164 + + XOR32mi_NF_ND = 22165 + + XOR32mr = 22166 + + XOR32mr_EVEX = 22167 + + XOR32mr_ND = 22168 + + XOR32mr_NF = 22169 + + XOR32mr_NF_ND = 22170 + + XOR32ri = 22171 + + XOR32ri8 = 22172 + + XOR32ri8_EVEX = 22173 + + XOR32ri8_ND = 22174 + + XOR32ri8_NF = 22175 + + XOR32ri8_NF_ND = 22176 + + XOR32ri_EVEX = 22177 + + XOR32ri_ND = 22178 + + XOR32ri_NF = 22179 + + XOR32ri_NF_ND = 22180 + + XOR32rm = 22181 + + XOR32rm_EVEX = 22182 + + XOR32rm_ND = 22183 + + XOR32rm_NF = 22184 + + XOR32rm_NF_ND = 22185 + + XOR32rr = 22186 + + XOR32rr_EVEX = 22187 + + XOR32rr_EVEX_REV = 22188 + + XOR32rr_ND = 22189 + + XOR32rr_ND_REV = 22190 + + XOR32rr_NF = 22191 + + XOR32rr_NF_ND = 22192 + + XOR32rr_NF_ND_REV = 22193 + + XOR32rr_NF_REV = 22194 + + XOR32rr_REV = 22195 + + XOR64i32 = 22196 + + XOR64mi32 = 22197 + + XOR64mi32_EVEX = 22198 + + XOR64mi32_ND = 22199 + + XOR64mi32_NF = 22200 + + XOR64mi32_NF_ND = 22201 + + XOR64mi8 = 22202 + + XOR64mi8_EVEX = 22203 + + XOR64mi8_ND = 22204 + + XOR64mi8_NF = 22205 + + XOR64mi8_NF_ND = 22206 + + XOR64mr = 22207 + + XOR64mr_EVEX = 22208 + + XOR64mr_ND = 22209 + + XOR64mr_NF = 22210 + + XOR64mr_NF_ND = 22211 + + XOR64ri32 = 22212 + + XOR64ri32_EVEX = 22213 + + XOR64ri32_ND = 22214 + + XOR64ri32_NF = 22215 + + XOR64ri32_NF_ND = 22216 + + XOR64ri8 = 22217 + + XOR64ri8_EVEX = 22218 + + XOR64ri8_ND = 22219 + + XOR64ri8_NF = 22220 + + XOR64ri8_NF_ND = 22221 + + XOR64rm = 22222 + + XOR64rm_EVEX = 22223 + + XOR64rm_ND = 22224 + + XOR64rm_NF = 22225 + + XOR64rm_NF_ND = 22226 + + XOR64rr = 22227 + + XOR64rr_EVEX = 22228 + + XOR64rr_EVEX_REV = 22229 + + XOR64rr_ND = 22230 + + XOR64rr_ND_REV = 22231 + + XOR64rr_NF = 22232 + + XOR64rr_NF_ND = 22233 + + XOR64rr_NF_ND_REV = 22234 + + XOR64rr_NF_REV = 22235 + + XOR64rr_REV = 22236 + + XOR8i8 = 22237 + + XOR8mi = 22238 + + XOR8mi8 = 22239 + + XOR8mi_EVEX = 22240 + + XOR8mi_ND = 22241 + + XOR8mi_NF = 22242 + + XOR8mi_NF_ND = 22243 + + XOR8mr = 22244 + + XOR8mr_EVEX = 22245 + + XOR8mr_ND = 22246 + + XOR8mr_NF = 22247 + + XOR8mr_NF_ND = 22248 + + XOR8ri = 22249 + + XOR8ri8 = 22250 + + XOR8ri_EVEX = 22251 + + XOR8ri_ND = 22252 + + XOR8ri_NF = 22253 + + XOR8ri_NF_ND = 22254 + + XOR8rm = 22255 + + XOR8rm_EVEX = 22256 + + XOR8rm_ND = 22257 + + XOR8rm_NF = 22258 + + XOR8rm_NF_ND = 22259 + + XOR8rr = 22260 + + XOR8rr_EVEX = 22261 + + XOR8rr_EVEX_REV = 22262 + + XOR8rr_ND = 22263 + + XOR8rr_ND_REV = 22264 + + XOR8rr_NF = 22265 + + XOR8rr_NF_ND = 22266 + + XOR8rr_NF_ND_REV = 22267 + + XOR8rr_NF_REV = 22268 + + XOR8rr_NOREX = 22269 + + XOR8rr_REV = 22270 + + XORPDrm = 22271 + + XORPDrr = 22272 + + XORPSrm = 22273 + + XORPSrr = 22274 + + XRELEASE_PREFIX = 22275 + + XRESLDTRK = 22276 + + XRSTOR = 22277 + + XRSTOR64 = 22278 + + XRSTORS = 22279 + + XRSTORS64 = 22280 + + XSAVE = 22281 + + XSAVE64 = 22282 + + XSAVEC = 22283 + + XSAVEC64 = 22284 + + XSAVEOPT = 22285 + + XSAVEOPT64 = 22286 + + XSAVES = 22287 + + XSAVES64 = 22288 + + XSETBV = 22289 + + XSHA1 = 22290 + + XSHA256 = 22291 + + XSTORE = 22292 + + XSUSLDTRK = 22293 + + XTEST = 22294 + + INSTRUCTION_LIST_END = 22295 + +class REG(enum.Enum): + NoRegister = 0 + + AH = 1 + + AL = 2 + + AX = 3 + + BH = 4 + + BL = 5 + + BP = 6 + + BPH = 7 + + BPL = 8 + + BX = 9 + + CH = 10 + + CL = 11 + + CS = 12 + + CX = 13 + + DF = 14 + + DH = 15 + + DI = 16 + + DIH = 17 + + DIL = 18 + + DL = 19 + + DS = 20 + + DX = 21 + + EAX = 22 + + EBP = 23 + + EBX = 24 + + ECX = 25 + + EDI = 26 + + EDX = 27 + + EFLAGS = 28 + + EIP = 29 + + EIZ = 30 + + ES = 31 + + ESI = 32 + + ESP = 33 + + FPCW = 34 + + FPSW = 35 + + FS = 36 + + FS_BASE = 37 + + GS = 38 + + GS_BASE = 39 + + HAX = 40 + + HBP = 41 + + HBX = 42 + + HCX = 43 + + HDI = 44 + + HDX = 45 + + HIP = 46 + + HSI = 47 + + HSP = 48 + + IP = 49 + + MXCSR = 50 + + RAX = 51 + + RBP = 52 + + RBX = 53 + + RCX = 54 + + RDI = 55 + + RDX = 56 + + RFLAGS = 57 + + RIP = 58 + + RIZ = 59 + + RSI = 60 + + RSP = 61 + + SI = 62 + + SIH = 63 + + SIL = 64 + + SP = 65 + + SPH = 66 + + SPL = 67 + + SS = 68 + + SSP = 69 + + _EFLAGS = 70 + + CR0 = 71 + + CR1 = 72 + + CR2 = 73 + + CR3 = 74 + + CR4 = 75 + + CR5 = 76 + + CR6 = 77 + + CR7 = 78 + + CR8 = 79 + + CR9 = 80 + + CR10 = 81 + + CR11 = 82 + + CR12 = 83 + + CR13 = 84 + + CR14 = 85 + + CR15 = 86 + + DR0 = 87 + + DR1 = 88 + + DR2 = 89 + + DR3 = 90 + + DR4 = 91 + + DR5 = 92 + + DR6 = 93 + + DR7 = 94 + + DR8 = 95 + + DR9 = 96 + + DR10 = 97 + + DR11 = 98 + + DR12 = 99 + + DR13 = 100 + + DR14 = 101 + + DR15 = 102 + + FP0 = 103 + + FP1 = 104 + + FP2 = 105 + + FP3 = 106 + + FP4 = 107 + + FP5 = 108 + + FP6 = 109 + + FP7 = 110 + + MM0 = 111 + + MM1 = 112 + + MM2 = 113 + + MM3 = 114 + + MM4 = 115 + + MM5 = 116 + + MM6 = 117 + + MM7 = 118 + + R8 = 119 + + R9 = 120 + + R10 = 121 + + R11 = 122 + + R12 = 123 + + R13 = 124 + + R14 = 125 + + R15 = 126 + + ST0 = 127 + + ST1 = 128 + + ST2 = 129 + + ST3 = 130 + + ST4 = 131 + + ST5 = 132 + + ST6 = 133 + + ST7 = 134 + + XMM0 = 135 + + XMM1 = 136 + + XMM2 = 137 + + XMM3 = 138 + + XMM4 = 139 + + XMM5 = 140 + + XMM6 = 141 + + XMM7 = 142 + + XMM8 = 143 + + XMM9 = 144 + + XMM10 = 145 + + XMM11 = 146 + + XMM12 = 147 + + XMM13 = 148 + + XMM14 = 149 + + XMM15 = 150 + + R8B = 151 + + R9B = 152 + + R10B = 153 + + R11B = 154 + + R12B = 155 + + R13B = 156 + + R14B = 157 + + R15B = 158 + + R8BH = 159 + + R9BH = 160 + + R10BH = 161 + + R11BH = 162 + + R12BH = 163 + + R13BH = 164 + + R14BH = 165 + + R15BH = 166 + + R8D = 167 + + R9D = 168 + + R10D = 169 + + R11D = 170 + + R12D = 171 + + R13D = 172 + + R14D = 173 + + R15D = 174 + + R8W = 175 + + R9W = 176 + + R10W = 177 + + R11W = 178 + + R12W = 179 + + R13W = 180 + + R14W = 181 + + R15W = 182 + + R8WH = 183 + + R9WH = 184 + + R10WH = 185 + + R11WH = 186 + + R12WH = 187 + + R13WH = 188 + + R14WH = 189 + + R15WH = 190 + + YMM0 = 191 + + YMM1 = 192 + + YMM2 = 193 + + YMM3 = 194 + + YMM4 = 195 + + YMM5 = 196 + + YMM6 = 197 + + YMM7 = 198 + + YMM8 = 199 + + YMM9 = 200 + + YMM10 = 201 + + YMM11 = 202 + + YMM12 = 203 + + YMM13 = 204 + + YMM14 = 205 + + YMM15 = 206 + + K0 = 207 + + K1 = 208 + + K2 = 209 + + K3 = 210 + + K4 = 211 + + K5 = 212 + + K6 = 213 + + K7 = 214 + + XMM16 = 215 + + XMM17 = 216 + + XMM18 = 217 + + XMM19 = 218 + + XMM20 = 219 + + XMM21 = 220 + + XMM22 = 221 + + XMM23 = 222 + + XMM24 = 223 + + XMM25 = 224 + + XMM26 = 225 + + XMM27 = 226 + + XMM28 = 227 + + XMM29 = 228 + + XMM30 = 229 + + XMM31 = 230 + + YMM16 = 231 + + YMM17 = 232 + + YMM18 = 233 + + YMM19 = 234 + + YMM20 = 235 + + YMM21 = 236 + + YMM22 = 237 + + YMM23 = 238 + + YMM24 = 239 + + YMM25 = 240 + + YMM26 = 241 + + YMM27 = 242 + + YMM28 = 243 + + YMM29 = 244 + + YMM30 = 245 + + YMM31 = 246 + + ZMM0 = 247 + + ZMM1 = 248 + + ZMM2 = 249 + + ZMM3 = 250 + + ZMM4 = 251 + + ZMM5 = 252 + + ZMM6 = 253 + + ZMM7 = 254 + + ZMM8 = 255 + + ZMM9 = 256 + + ZMM10 = 257 + + ZMM11 = 258 + + ZMM12 = 259 + + ZMM13 = 260 + + ZMM14 = 261 + + ZMM15 = 262 + + ZMM16 = 263 + + ZMM17 = 264 + + ZMM18 = 265 + + ZMM19 = 266 + + ZMM20 = 267 + + ZMM21 = 268 + + ZMM22 = 269 + + ZMM23 = 270 + + ZMM24 = 271 + + ZMM25 = 272 + + ZMM26 = 273 + + ZMM27 = 274 + + ZMM28 = 275 + + ZMM29 = 276 + + ZMM30 = 277 + + ZMM31 = 278 + + K0_K1 = 279 + + K2_K3 = 280 + + K4_K5 = 281 + + K6_K7 = 282 + + TMMCFG = 283 + + TMM0 = 284 + + TMM1 = 285 + + TMM2 = 286 + + TMM3 = 287 + + TMM4 = 288 + + TMM5 = 289 + + TMM6 = 290 + + TMM7 = 291 + + R16 = 292 + + R17 = 293 + + R18 = 294 + + R19 = 295 + + R20 = 296 + + R21 = 297 + + R22 = 298 + + R23 = 299 + + R24 = 300 + + R25 = 301 + + R26 = 302 + + R27 = 303 + + R28 = 304 + + R29 = 305 + + R30 = 306 + + R31 = 307 + + R16B = 308 + + R17B = 309 + + R18B = 310 + + R19B = 311 + + R20B = 312 + + R21B = 313 + + R22B = 314 + + R23B = 315 + + R24B = 316 + + R25B = 317 + + R26B = 318 + + R27B = 319 + + R28B = 320 + + R29B = 321 + + R30B = 322 + + R31B = 323 + + R16BH = 324 + + R17BH = 325 + + R18BH = 326 + + R19BH = 327 + + R20BH = 328 + + R21BH = 329 + + R22BH = 330 + + R23BH = 331 + + R24BH = 332 + + R25BH = 333 + + R26BH = 334 + + R27BH = 335 + + R28BH = 336 + + R29BH = 337 + + R30BH = 338 + + R31BH = 339 + + R16D = 340 + + R17D = 341 + + R18D = 342 + + R19D = 343 + + R20D = 344 + + R21D = 345 + + R22D = 346 + + R23D = 347 + + R24D = 348 + + R25D = 349 + + R26D = 350 + + R27D = 351 + + R28D = 352 + + R29D = 353 + + R30D = 354 + + R31D = 355 + + R16W = 356 + + R17W = 357 + + R18W = 358 + + R19W = 359 + + R20W = 360 + + R21W = 361 + + R22W = 362 + + R23W = 363 + + R24W = 364 + + R25W = 365 + + R26W = 366 + + R27W = 367 + + R28W = 368 + + R29W = 369 + + R30W = 370 + + R31W = 371 + + R16WH = 372 + + R17WH = 373 + + R18WH = 374 + + R19WH = 375 + + R20WH = 376 + + R21WH = 377 + + R22WH = 378 + + R23WH = 379 + + R24WH = 380 + + R25WH = 381 + + R26WH = 382 + + R27WH = 383 + + R28WH = 384 + + R29WH = 385 + + R30WH = 386 + + R31WH = 387 + + NUM_TARGET_REGS = 388 + +class Instruction(lief.assembly.Instruction): + __match_args__: tuple = ... + + @property + def operands(self) -> Iterator[Optional[Operand]]: ... + + @property + def opcode(self) -> OPCODE: ... + + @property + def has_lock_prefix(self) -> bool: ... + + @property + def is_lockable(self) -> bool: ... + + @property + def is_atomic(self) -> bool: ... + + def lock(self) -> Optional[Instruction]: ... + + def unlock(self) -> Optional[Instruction]: ... + +class Operand: + @property + def to_string(self) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/assembly/x86/operands.pyi b/vendor/lief/api/python/lief/assembly/x86/operands.pyi new file mode 100644 index 0000000..2caeb7d --- /dev/null +++ b/vendor/lief/api/python/lief/assembly/x86/operands.pyi @@ -0,0 +1,38 @@ +import lief.assembly.x86 + + +class Immediate(lief.assembly.x86.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... + +class Register(lief.assembly.x86.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> lief.assembly.x86.REG: ... + +class Memory(lief.assembly.x86.Operand): + __match_args__: tuple = ... + + @property + def base(self) -> lief.assembly.x86.REG: ... + + @property + def scaled_register(self) -> lief.assembly.x86.REG: ... + + @property + def segment_register(self) -> lief.assembly.x86.REG: ... + + @property + def scale(self) -> int: ... + + @property + def displacement(self) -> int: ... + +class PCRelative(lief.assembly.x86.Operand): + __match_args__: tuple = ... + + @property + def value(self) -> int: ... diff --git a/vendor/lief/api/python/lief/dsc.pyi b/vendor/lief/api/python/lief/dsc.pyi new file mode 100644 index 0000000..6f23024 --- /dev/null +++ b/vendor/lief/api/python/lief/dsc.pyi @@ -0,0 +1,226 @@ +from collections.abc import Iterator, Sequence +import enum +import os +from typing import Optional, Union, overload + +import lief +import lief.MachO +import lief.assembly + + +@overload +def enable_cache() -> bool: ... + +@overload +def enable_cache(target_cache_dir: Union[str | os.PathLike]) -> bool: ... + +class DyldSharedCache: + class VERSION(enum.Enum): + UNKNOWN = 0 + + DYLD_95_3 = 1 + + DYLD_195_5 = 2 + + DYLD_239_3 = 3 + + DYLD_360_14 = 4 + + DYLD_421_1 = 5 + + DYLD_832_7_1 = 6 + + DYLD_940 = 7 + + DYLD_1042_1 = 8 + + DYLD_1231_3 = 9 + + DYLD_1284_13 = 10 + + UNRELEASED = 11 + + class PLATFORM(enum.Enum): + UNKNOWN = 0 + + MACOS = 1 + + IOS = 2 + + TVOS = 3 + + WATCHOS = 4 + + BRIDGEOS = 5 + + IOSMAC = 6 + + IOS_SIMULATOR = 7 + + TVOS_SIMULATOR = 8 + + WATCHOS_SIMULATOR = 9 + + DRIVERKIT = 10 + + VISIONOS = 11 + + VISIONOS_SIMULATOR = 12 + + FIRMWARE = 13 + + SEPOS = 14 + + ANY = 4294967295 + + class ARCH(enum.Enum): + UNKNOWN = 0 + + I386 = 1 + + X86_64 = 2 + + X86_64H = 3 + + ARMV5 = 4 + + ARMV6 = 5 + + ARMV7 = 6 + + ARM64 = 7 + + ARM64E = 8 + + @staticmethod + def from_path(path: str, arch: str = '') -> Optional[DyldSharedCache]: ... + + @staticmethod + def from_files(files: Sequence[str]) -> Optional[DyldSharedCache]: ... + + @property + def filename(self) -> str: ... + + @property + def version(self) -> DyldSharedCache.VERSION: ... + + @property + def filepath(self) -> str: ... + + @property + def load_address(self) -> int: ... + + @property + def arch_name(self) -> str: ... + + @property + def platform(self) -> DyldSharedCache.PLATFORM: ... + + @property + def arch(self) -> DyldSharedCache.ARCH: ... + + @property + def has_subcaches(self) -> bool: ... + + def find_lib_from_va(self, virtual_address: int) -> Optional[Dylib]: ... + + def find_lib_from_path(self, path: str) -> Optional[Dylib]: ... + + def find_lib_from_name(self, name: str) -> Optional[Dylib]: ... + + @property + def libraries(self) -> Sequence[Optional[Dylib]]: ... + + @property + def mapping_info(self) -> Sequence[Optional[MappingInfo]]: ... + + @property + def subcaches(self) -> Sequence[Optional[SubCache]]: ... + + def get_content_from_va(self, addr: int, size: int) -> bytes: ... + + def cache_for_address(self, address: int) -> Optional[DyldSharedCache]: ... + + @property + def main_cache(self) -> Optional[DyldSharedCache]: ... + + def find_subcache(self, filename: str) -> Optional[DyldSharedCache]: ... + + def va_to_offset(self, virtual_address: int) -> Union[int, lief.lief_errors]: ... + + def disassemble(self, arg: int, /) -> Iterator[Optional[lief.assembly.Instruction]]: ... + + def enable_caching(self, target_dir: str) -> None: ... + + def flush_cache(self) -> None: ... + +@overload +def load(files: Sequence[str]) -> Optional[DyldSharedCache]: ... + +@overload +def load(path: Union[str | os.PathLike], arch: str = '') -> Optional[DyldSharedCache]: ... + +class Dylib: + class extract_opt_t: + def __init__(self) -> None: ... + + pack: bool + + fix_branches: bool + + fix_memory: bool + + fix_relocations: bool + + fix_objc: bool + + create_dyld_chained_fixup_cmd: bool + + @property + def path(self) -> str: ... + + @property + def address(self) -> int: ... + + @property + def modtime(self) -> int: ... + + @property + def inode(self) -> int: ... + + @property + def padding(self) -> int: ... + + def get(self, opt: Dylib.extract_opt_t = ...) -> Optional[lief.MachO.Binary]: ... + +class SubCache: + @property + def uuid(self) -> list[int]: ... + + @property + def vm_offset(self) -> int: ... + + @property + def suffix(self) -> str: ... + + @property + def cache(self) -> Optional[DyldSharedCache]: ... + +class MappingInfo: + @property + def address(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def end_address(self) -> int: ... + + @property + def file_offset(self) -> int: ... + + @property + def max_prot(self) -> int: ... + + @property + def init_prot(self) -> int: ... diff --git a/vendor/lief/api/python/lief/dwarf/__init__.pyi b/vendor/lief/api/python/lief/dwarf/__init__.pyi new file mode 100644 index 0000000..e134022 --- /dev/null +++ b/vendor/lief/api/python/lief/dwarf/__init__.pyi @@ -0,0 +1,389 @@ +from collections.abc import Iterator +import enum +import os +from typing import Optional, Union, overload + +import lief +import lief.assembly +from lief.dwarf import ( + editor as editor, + parameters as parameters, + types as types +) + + +def load(path: Union[str | os.PathLike]) -> Optional[DebugInfo]: ... + +class Scope: + class TYPE(enum.Enum): + UNKNOWN = 0 + + UNION = 1 + + CLASS = 2 + + STRUCT = 3 + + NAMESPACE = 4 + + FUNCTION = 5 + + COMPILATION_UNIT = 6 + + @property + def name(self) -> str: ... + + @property + def parent(self) -> Optional[Scope]: ... + + @property + def type(self) -> Scope.TYPE: ... + + def chained(self, sep: str = '::') -> str: ... + +class Type: + class KIND(enum.Enum): + UNKNOWN = 0 + + UNSPECIFIED = 1 + + BASE = 2 + + CONST_KIND = 3 + + CLASS = 4 + + ARRAY = 5 + + POINTER = 6 + + STRUCT = 7 + + UNION = 8 + + TYPEDEF = 9 + + REF = 10 + + SET_TYPE = 11 + + STRING = 12 + + SUBROUTINE = 13 + + POINTER_MEMBER = 14 + + PACKED = 15 + + FILE = 16 + + THROWN = 17 + + VOLATILE = 18 + + RESTRICT = 19 + + INTERFACE = 20 + + SHARED = 21 + + RVALREF = 22 + + TEMPLATE_ALIAS = 23 + + COARRAY = 24 + + DYNAMIC = 25 + + ATOMIC = 26 + + IMMUTABLE = 27 + + ENUM = 28 + + @property + def kind(self) -> Type.KIND: ... + + @property + def name(self) -> Optional[str]: ... + + @property + def size(self) -> Optional[int]: ... + + @property + def location(self) -> lief.debug_location_t: ... + + @property + def is_unspecified(self) -> bool: ... + + @property + def scope(self) -> Optional[Scope]: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + +class Variable: + @property + def name(self) -> str: ... + + @property + def linkage_name(self) -> str: ... + + @property + def address(self) -> Optional[int]: ... + + @property + def size(self) -> Optional[int]: ... + + @property + def is_constexpr(self) -> bool: ... + + @property + def is_stack_based(self) -> bool: ... + + @property + def debug_location(self) -> lief.debug_location_t: ... + + @property + def type(self) -> Optional[Type]: ... + + @property + def scope(self) -> Optional[Scope]: ... + + @property + def description(self) -> str: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + +class Function: + @property + def name(self) -> str: ... + + @property + def linkage_name(self) -> str: ... + + @property + def address(self) -> Optional[int]: ... + + @property + def variables(self) -> Iterator[Optional[Variable]]: ... + + @property + def is_artificial(self) -> bool: ... + + @property + def is_external(self) -> bool: ... + + @property + def size(self) -> int: ... + + @property + def ranges(self) -> list[lief.range_t]: ... + + @property + def debug_location(self) -> lief.debug_location_t: ... + + @property + def type(self) -> Optional[Type]: ... + + @property + def parameters(self) -> list[Optional[Parameter]]: ... + + @property + def thrown_types(self) -> list[Optional[Type]]: ... + + @property + def scope(self) -> Optional[Scope]: ... + + @property + def instructions(self) -> Iterator[Optional[lief.assembly.Instruction]]: ... + + @property + def lexical_blocks(self) -> Iterator[Optional[LexicalBlock]]: ... + + @property + def description(self) -> str: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + +class Parameter: + class Location: + class Type(enum.Enum): + UNKNOWN = 0 + + REGISTER = 1 + + @property + def type(self) -> Parameter.Location.Type: ... + + class RegisterLoc(Parameter.Location): + @property + def id(self) -> int: ... + + @property + def name(self) -> str: ... + + @property + def type(self) -> Optional[Type]: ... + + @property + def location(self) -> Optional[Parameter.Location]: ... + +class CompilationUnit: + class Language: + class LANG(enum.Enum): + @staticmethod + def from_value(arg: int, /) -> CompilationUnit.Language.LANG: ... + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __int__(self) -> int: ... + + UNKNOWN = 0 + + C = 1 + + CPP = 2 + + RUST = 3 + + DART = 4 + + MODULA = 5 + + FORTRAN = 6 + + SWIFT = 7 + + D = 8 + + JAVA = 9 + + COBOL = 10 + + lang: CompilationUnit.Language.LANG + + version: int + + @property + def name(self) -> str: ... + + @property + def producer(self) -> str: ... + + @property + def compilation_dir(self) -> str: ... + + @property + def language(self) -> CompilationUnit.Language: ... + + @property + def low_address(self) -> int: ... + + @property + def high_address(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def ranges(self) -> list[lief.range_t]: ... + + @overload + def find_function(self, name: str) -> Optional[Function]: ... + + @overload + def find_function(self, addr: int) -> Optional[Function]: ... + + @overload + def find_variable(self, addr: int) -> Optional[Variable]: ... + + @overload + def find_variable(self, name: str) -> Optional[Variable]: ... + + @property + def types(self) -> Iterator[Optional[Type]]: ... + + @property + def functions(self) -> Iterator[Optional[Function]]: ... + + @property + def imported_functions(self) -> Iterator[Optional[Function]]: ... + + @property + def variables(self) -> Iterator[Optional[Variable]]: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + +class DebugInfo(lief.DebugInfo): + @overload + def find_function(self, name: str) -> Optional[Function]: ... + + @overload + def find_function(self, addr: int) -> Optional[Function]: ... + + @overload + def find_variable(self, addr: int) -> Optional[Variable]: ... + + @overload + def find_variable(self, name: str) -> Optional[Variable]: ... + + def find_type(self, name: str) -> Optional[Type]: ... + + @property + def compilation_units(self) -> Iterator[Optional[CompilationUnit]]: ... + +class Editor: + class ARCH(enum.Enum): + UNKNOWN = 0 + + X64 = 1 + + X86 = 2 + + AARCH64 = 3 + + ARM = 4 + + class FORMAT(enum.Enum): + ELF = 0 + + PE = 2 + + MACHO = 1 + + @staticmethod + def from_binary(bin: lief.Binary) -> Optional[Editor]: ... + + @staticmethod + def create(fmt: Editor.FORMAT, arch: Editor.ARCH) -> Optional[Editor]: ... + + def create_compilation_unit(self) -> Optional[editor.CompilationUnit]: ... + + def write(self, output: Union[str | os.PathLike]) -> None: ... + +class LexicalBlock: + @property + def name(self) -> str: ... + + @property + def description(self) -> str: ... + + @property + def sub_blocks(self) -> Iterator[Optional[LexicalBlock]]: ... + + @property + def addr(self) -> int | None: ... + + @property + def size(self) -> int: ... + + @property + def low_pc(self) -> int | None: ... + + @property + def high_pc(self) -> int | None: ... + + @property + def ranges(self) -> list[lief.range_t]: ... diff --git a/vendor/lief/api/python/lief/dwarf/editor.pyi b/vendor/lief/api/python/lief/dwarf/editor.pyi new file mode 100644 index 0000000..7827a89 --- /dev/null +++ b/vendor/lief/api/python/lief/dwarf/editor.pyi @@ -0,0 +1,158 @@ +from collections.abc import Sequence +import enum +from typing import Optional, overload + + +class Type: + def pointer_to(self) -> Optional[PointerType]: ... + +class PointerType(Type): + pass + +class EnumType(Type): + class Value: + pass + + def set_size(self, size: int) -> EnumType: ... + + def set_underlying_type(self, type: Type) -> EnumType: ... + + def add_value(self, name: str, value: int) -> Optional[EnumType.Value]: ... + +class BaseType(Type): + class ENCODING(enum.Enum): + NONE = 0 + + ADDRESS = 1 + + SIGNED = 2 + + SIGNED_CHAR = 3 + + UNSIGNED = 4 + + UNSIGNED_CHAR = 5 + + BOOLEAN = 6 + + FLOAT = 7 + +class ArrayType(Type): + pass + +class FunctionType(Type): + class Parameter: + pass + + def set_return_type(self, type: Type) -> FunctionType: ... + + def add_parameter(self, type: Type) -> Optional[FunctionType.Parameter]: ... + +class TypeDef(Type): + pass + +class StructType(Type): + class TYPE(enum.Enum): + CLASS = 0 + + STRUCT = 1 + + UNION = 2 + + class Member: + pass + + def set_size(self, size: int) -> StructType: ... + + def add_member(self, name: str, type: Type, offset: int = -1) -> Optional[StructType.Member]: ... + + def add_bitfield(self, name: str, type: Type, bitsize: int, bitoffset: int = -1) -> Optional[StructType.Member]: ... + +class Function: + class range_t: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, start: int, end: int) -> None: ... + + start: int + + end: int + + class Parameter: + @overload + def assign_register(self, arg: str, /) -> Function.Parameter: ... + + @overload + def assign_register(self, arg: int, /) -> Function.Parameter: ... + + class LexicalBlock: + @overload + def add_block(self, start: int, end: int) -> Optional[Function.LexicalBlock]: ... + + @overload + def add_block(self, range: Sequence[Function.range_t]) -> Optional[Function.LexicalBlock]: ... + + def add_description(self, description: str) -> Function.LexicalBlock: ... + + def add_name(self, name: str) -> Function.LexicalBlock: ... + + class Label: + pass + + def set_address(self, addr: int) -> Function: ... + + def set_low_high(self, low: int, high: int) -> Function: ... + + def set_ranges(self, ranges: Sequence[Function.range_t]) -> Function: ... + + def set_external(self) -> Function: ... + + def set_return_type(self, type: Type) -> Function: ... + + def add_parameter(self, name: str, type: Type) -> Optional[Function.Parameter]: ... + + def create_stack_variable(self, name: str) -> Optional[Variable]: ... + + def add_lexical_block(self, start: int, end: int) -> Optional[Function.LexicalBlock]: ... + + def add_label(self, addr: int, label: str) -> Optional[Function.Label]: ... + + def add_description(self, description: str) -> Function: ... + +class Variable: + def set_addr(self, addr: int) -> Variable: ... + + def set_stack_offset(self, offset: int) -> Variable: ... + + def set_external(self) -> Variable: ... + + def set_type(self, type: Type) -> Variable: ... + + def add_description(self, description: str) -> Variable: ... + +class CompilationUnit: + def set_producer(self, arg: str, /) -> CompilationUnit: ... + + def create_function(self, name: str) -> Optional[Function]: ... + + def create_variable(self, name: str) -> Optional[Variable]: ... + + def create_generic_type(self, name: str) -> Optional[Type]: ... + + def create_enum(self, name: str) -> Optional[EnumType]: ... + + def create_typedef(self, name: str, ty: Type) -> Optional[TypeDef]: ... + + def create_structure(self, name: str, kind: StructType.TYPE = StructType.TYPE.STRUCT) -> Optional[StructType]: ... + + def create_base_type(self, name: str, size: int, encoding: BaseType.ENCODING = BaseType.ENCODING.NONE) -> Optional[BaseType]: ... + + def create_function_type(self, name: str) -> Optional[FunctionType]: ... + + def create_pointer_type(self, ty: Type) -> Optional[PointerType]: ... + + def create_void_type(self) -> Optional[Type]: ... + + def create_array(self, name: str, ty: Type, count: int) -> Optional[ArrayType]: ... diff --git a/vendor/lief/api/python/lief/dwarf/parameters.pyi b/vendor/lief/api/python/lief/dwarf/parameters.pyi new file mode 100644 index 0000000..d419b51 --- /dev/null +++ b/vendor/lief/api/python/lief/dwarf/parameters.pyi @@ -0,0 +1,14 @@ +from typing import Optional + +import lief.dwarf + + +class Formal(lief.dwarf.Parameter): + @property + def type(self) -> Optional[lief.dwarf.Type]: ... + +class TemplateValue(lief.dwarf.Parameter): + pass + +class TemplateType(lief.dwarf.Parameter): + pass diff --git a/vendor/lief/api/python/lief/dwarf/types.pyi b/vendor/lief/api/python/lief/dwarf/types.pyi new file mode 100644 index 0000000..cc0d8de --- /dev/null +++ b/vendor/lief/api/python/lief/dwarf/types.pyi @@ -0,0 +1,187 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.dwarf + + +class ClassLike(lief.dwarf.Type): + class Member: + @property + def name(self) -> str: ... + + @property + def type(self) -> Optional[lief.dwarf.Type]: ... + + @property + def is_external(self) -> bool: ... + + @property + def is_declaration(self) -> bool: ... + + @property + def offset(self) -> Optional[int]: ... + + @property + def bit_offset(self) -> Optional[int]: ... + + @property + def bit_size(self) -> Optional[int]: ... + + @property + def members(self) -> list[ClassLike.Member]: ... + + def find_member(self, offset: int) -> Optional[ClassLike.Member]: ... + + @property + def functions(self) -> Iterator[Optional[lief.dwarf.Function]]: ... + +class Structure(ClassLike): + pass + +class Class(ClassLike): + pass + +class Union(ClassLike): + pass + +class Packed(ClassLike): + pass + +class Pointer(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Const(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Base(lief.dwarf.Type): + class ENCODING(enum.Enum): + NONE = 0 + + SIGNED = 1 + + SIGNED_CHAR = 2 + + UNSIGNED = 3 + + UNSIGNED_CHAR = 4 + + FLOAT = 5 + + BOOLEAN = 6 + + ADDRESS = 7 + + @property + def encoding(self) -> Base.ENCODING: ... + +class Array(lief.dwarf.Type): + class size_info_t: + @property + def type(self) -> lief.dwarf.Type | None: ... + + @property + def name(self) -> str: ... + + @property + def size(self) -> int: ... + + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + + @property + def size_info(self) -> Array.size_info_t: ... + +class Typedef(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Atomic(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Coarray(lief.dwarf.Type): + pass + +class Dynamic(lief.dwarf.Type): + pass + +class Enum(lief.dwarf.Type): + class Entry: + @property + def name(self) -> str: ... + + @property + def value(self) -> int | None: ... + + @property + def entries(self) -> list[Enum.Entry]: ... + + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + + def find_entry(self, value: int) -> Enum.Entry | None: ... + +class File(lief.dwarf.Type): + pass + +class Immutable(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Interface(lief.dwarf.Type): + pass + +class PointerToMember(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + + @property + def containing_type(self) -> Optional[lief.dwarf.Type]: ... + +class RValueReference(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Reference(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Restrict(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class SetTy(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Shared(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class StringTy(lief.dwarf.Type): + pass + +class Subroutine(lief.dwarf.Type): + @property + def return_type(self) -> Optional[lief.dwarf.Type]: ... + + @property + def parameters(self) -> list[Optional[lief.dwarf.Parameter]]: ... + +class TemplateAlias(lief.dwarf.Type): + @property + def parameters(self) -> list[Optional[lief.dwarf.Parameter]]: ... + + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Thrown(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... + +class Volatile(lief.dwarf.Type): + @property + def underlying_type(self) -> lief.dwarf.Type | None: ... diff --git a/vendor/lief/api/python/lief/logging.pyi b/vendor/lief/api/python/lief/logging.pyi new file mode 100644 index 0000000..0d2b39a --- /dev/null +++ b/vendor/lief/api/python/lief/logging.pyi @@ -0,0 +1,56 @@ +import enum +import os +from typing import Union, overload + + +class Level(enum.Enum): + Off = 0 + + Trace = 1 + + Debug = 2 + + Critical = 6 + + Err = 5 + + Warn = 4 + + Info = 3 + +class Scoped: + def __enter__(self) -> Scoped | None: ... + + def __exit__(self, *args) -> None: ... + +def disable() -> None: ... + +def enable() -> None: ... + +def set_level(level: Level) -> None: ... + +@overload +def level_scope(level: Level) -> Scoped: ... + +@overload +def level_scope(name: str, lvl: Level) -> Scoped: ... + +def get_level() -> Level: ... + +def set_path(path: Union[str | os.PathLike]) -> None: ... + +def log(level: Level, msg: str) -> None: ... + +def debug(*msg) -> None: ... + +def info(*args) -> None: ... + +def warn(*msg) -> None: ... + +def err(*msg) -> None: ... + +def critical(*msg) -> None: ... + +def enable_debug() -> None: ... + +def reset() -> None: ... diff --git a/vendor/lief/api/python/lief/objc.pyi b/vendor/lief/api/python/lief/objc.pyi new file mode 100644 index 0000000..051e6e8 --- /dev/null +++ b/vendor/lief/api/python/lief/objc.pyi @@ -0,0 +1,120 @@ +from collections.abc import Iterator +from typing import Optional + + +class DeclOpt: + def __init__(self) -> None: ... + + show_annotations: bool + +class Metadata: + def to_decl(self, opt: DeclOpt = ...) -> str: ... + + @property + def classes(self) -> Iterator[Optional[Class]]: ... + + @property + def protocols(self) -> Iterator[Optional[Protocol]]: ... + + @property + def categories(self) -> Iterator[Optional[Category]]: ... + + def get_class(self, name: str) -> Optional[Class]: ... + + def get_protocol(self, name: str) -> Optional[Protocol]: ... + +class Class: + @property + def name(self) -> str: ... + + @property + def demangled_name(self) -> str: ... + + @property + def super_class(self) -> Optional[Class]: ... + + @property + def super_name(self) -> str: ... + + @property + def demangled_super_name(self) -> str: ... + + @property + def is_meta(self) -> bool: ... + + @property + def methods(self) -> Iterator[Optional[Method]]: ... + + @property + def protocols(self) -> Iterator[Optional[Protocol]]: ... + + @property + def properties(self) -> Iterator[Optional[Property]]: ... + + @property + def ivars(self) -> Iterator[Optional[IVar]]: ... + + def to_decl(self, opt: DeclOpt = ...) -> str: ... + +class Category: + @property + def name(self) -> str: ... + + @property + def class_name(self) -> str: ... + + @property + def methods(self) -> Iterator[Optional[Method]]: ... + + @property + def protocols(self) -> Iterator[Optional[Protocol]]: ... + + @property + def properties(self) -> Iterator[Optional[Property]]: ... + + def to_decl(self, opt: DeclOpt = ...) -> str: ... + +class IVar: + @property + def name(self) -> str: ... + + @property + def mangled_type(self) -> str: ... + +class Protocol: + @property + def mangled_name(self) -> str: ... + + @property + def protocols(self) -> Iterator[Optional[Protocol]]: ... + + @property + def optional_methods(self) -> Iterator[Optional[Method]]: ... + + @property + def required_methods(self) -> Iterator[Optional[Method]]: ... + + @property + def properties(self) -> Iterator[Optional[Property]]: ... + + def to_decl(self, opt: DeclOpt = ...) -> str: ... + +class Method: + @property + def name(self) -> str: ... + + @property + def mangled_type(self) -> str: ... + + @property + def address(self) -> int: ... + + @property + def is_instance(self) -> bool: ... + +class Property: + @property + def name(self) -> str: ... + + @property + def attribute(self) -> str: ... diff --git a/vendor/lief/api/python/lief/pdb/__init__.pyi b/vendor/lief/api/python/lief/pdb/__init__.pyi new file mode 100644 index 0000000..dded960 --- /dev/null +++ b/vendor/lief/api/python/lief/pdb/__init__.pyi @@ -0,0 +1,353 @@ +from collections.abc import Iterator +import enum +import os +from typing import Optional, Union, overload + +import lief +from lief.pdb import types as types + + +def load(path: str) -> Optional[DebugInfo]: ... + +class BuildMetadata: + class LANG(enum.Enum): + C = 0 + + CPP = 1 + + FORTRAN = 2 + + MASM = 3 + + PASCAL_LANG = 4 + + BASIC = 5 + + COBOL = 6 + + LINK = 7 + + CVTRES = 8 + + CVTPGD = 9 + + CSHARP = 10 + + VB = 11 + + ILASM = 12 + + JAVA = 13 + + JSCRIPT = 14 + + MSIL = 15 + + HLSL = 16 + + OBJC = 17 + + OBJCPP = 18 + + SWIFT = 19 + + ALIASOBJ = 20 + + RUST = 21 + + GO = 22 + + UNKNOWN = 255 + + class CPU(enum.Enum): + INTEL_8080 = 0 + + INTEL_8086 = 1 + + INTEL_80286 = 2 + + INTEL_80386 = 3 + + INTEL_80486 = 4 + + PENTIUM = 5 + + PENTIUMPRO = 6 + + PENTIUM3 = 7 + + MIPS = 16 + + MIPS16 = 17 + + MIPS32 = 18 + + MIPS64 = 19 + + MIPSI = 20 + + MIPSII = 21 + + MIPSIII = 22 + + MIPSIV = 23 + + MIPSV = 24 + + M68000 = 32 + + M68010 = 33 + + M68020 = 34 + + M68030 = 35 + + M68040 = 36 + + ALPHA = 48 + + ALPHA_21164 = 49 + + ALPHA_21164A = 50 + + ALPHA_21264 = 51 + + ALPHA_21364 = 52 + + PPC601 = 64 + + PPC603 = 65 + + PPC604 = 66 + + PPC620 = 67 + + PPCFP = 68 + + PPCBE = 69 + + SH3 = 80 + + SH3E = 81 + + SH3DSP = 82 + + SH4 = 83 + + SHMEDIA = 84 + + ARM3 = 96 + + ARM4 = 97 + + ARM4T = 98 + + ARM5 = 99 + + ARM5T = 100 + + ARM6 = 101 + + ARM_XMAC = 102 + + ARM_WMMX = 103 + + ARM7 = 104 + + OMNI = 112 + + IA64 = 128 + + IA64_2 = 129 + + CEE = 144 + + AM33 = 160 + + M32R = 176 + + TRICORE = 192 + + X64 = 208 + + EBC = 224 + + THUMB = 240 + + ARMNT = 244 + + ARM64 = 246 + + HYBRID_X86ARM64 = 247 + + ARM64EC = 248 + + ARM64X = 249 + + D3D11_SHADER = 256 + + UNKNOWN = 255 + + class version_t: + major: int + + minor: int + + build: int + + qfe: int + + class build_info_t: + cwd: str + + build_tool: str + + source_file: str + + pdb: str + + command_line: str + + @property + def frontend_version(self) -> BuildMetadata.version_t: ... + + @property + def backend_version(self) -> BuildMetadata.version_t: ... + + @property + def version(self) -> str: ... + + @property + def language(self) -> BuildMetadata.LANG: ... + + @property + def target_cpu(self) -> BuildMetadata.CPU: ... + + @property + def build_info(self) -> BuildMetadata.build_info_t | None: ... + + @property + def env(self) -> list[str]: ... + + def __str__(self) -> str: ... + +class Type: + class KIND(enum.Enum): + UNKNOWN = 0 + + CLASS = 1 + + POINTER = 2 + + SIMPLE = 3 + + ENUM = 4 + + FUNCTION = 5 + + MODIFIER = 6 + + BITFIELD = 7 + + ARRAY = 8 + + UNION = 9 + + STRUCTURE = 10 + + INTERFACE = 11 + + @property + def kind(self) -> Type.KIND: ... + + @property + def name(self) -> str | None: ... + + @property + def size(self) -> int | None: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + +class DebugInfo(lief.DebugInfo): + @property + def age(self) -> int: ... + + @property + def guid(self) -> str: ... + + @staticmethod + def from_file(filepath: Union[str | os.PathLike]) -> Optional[DebugInfo]: ... + + @overload + def find_type(self, name: str) -> Optional[Type]: ... + + @overload + def find_type(self, index: int) -> Optional[Type]: ... + + def find_public_symbol(self, name: str) -> Optional[PublicSymbol]: ... + + @property + def public_symbols(self) -> Iterator[Optional[PublicSymbol]]: ... + + @property + def compilation_units(self) -> Iterator[Optional[CompilationUnit]]: ... + + @property + def types(self) -> Iterator[Optional[Type]]: ... + + def __str__(self) -> str: ... + +class PublicSymbol: + @property + def name(self) -> str: ... + + @property + def section_name(self) -> str: ... + + @property + def RVA(self) -> int: ... + + @property + def demangled_name(self) -> str: ... + + def __str__(self) -> str: ... + +class CompilationUnit: + @property + def module_name(self) -> str: ... + + @property + def object_filename(self) -> str: ... + + @property + def sources(self) -> Iterator[str]: ... + + @property + def functions(self) -> Iterator[Optional[Function]]: ... + + @property + def build_metadata(self) -> Optional[BuildMetadata]: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + + def __str__(self) -> str: ... + +class Function: + @property + def name(self) -> str: ... + + @property + def RVA(self) -> int: ... + + @property + def code_size(self) -> int: ... + + @property + def section_name(self) -> str: ... + + @property + def debug_location(self) -> lief.debug_location_t: ... + + def to_decl(self, opt: lief.DeclOpt | None = None) -> str: ... + + def __str__(self) -> str: ... diff --git a/vendor/lief/api/python/lief/pdb/types.pyi b/vendor/lief/api/python/lief/pdb/types.pyi new file mode 100644 index 0000000..8245400 --- /dev/null +++ b/vendor/lief/api/python/lief/pdb/types.pyi @@ -0,0 +1,240 @@ +from collections.abc import Iterator +import enum +from typing import Optional + +import lief.pdb + + +class Simple(lief.pdb.Type): + class TYPES(enum.Enum): + UNKNOWN = 0 + + VOID = 3 + + SCHAR = 16 + + UCHAR = 32 + + RCHAR = 112 + + WCHAR = 113 + + CHAR16 = 122 + + CHAR32 = 123 + + CHAR8 = 124 + + SBYTE = 104 + + UBYTE = 105 + + SSHORT = 17 + + USHORT = 33 + + SINT16 = 114 + + UINT16 = 115 + + SLONG = 18 + + ULONG = 34 + + SINT32 = 116 + + UINT32 = 117 + + SQUAD = 19 + + UQUAD = 35 + + SINT64 = 118 + + UINT64 = 119 + + SOCTA = 20 + + UOCTA = 36 + + SINT128 = 120 + + UINT128 = 121 + + FLOAT16 = 70 + + FLOAT32 = 64 + + FLOAT32_PARTIAL_PRECISION = 69 + + FLOAT48 = 68 + + FLOAT64 = 65 + + FLOAT80 = 66 + + FLOAT128 = 67 + + COMPLEX16 = 86 + + COMPLEX32 = 80 + + COMPLEX32_PARTIAL_PRECISION = 85 + + COMPLEX48 = 84 + + COMPLEX64 = 81 + + COMPLEX80 = 82 + + COMPLEX128 = 83 + + BOOL8 = 48 + + BOOL16 = 49 + + BOOL32 = 50 + + BOOL64 = 51 + + BOOL128 = 52 + + class MODES(enum.Enum): + DIRECT = 0 + + FAR_POINTER = 512 + + HUGE_POINTER = 768 + + NEAR_POINTER32 = 1024 + + FAR_POINTER32 = 1280 + + NEAR_POINTER64 = 1536 + + NEAR_POINTER128 = 1792 + + @property + def type(self) -> Simple.TYPES: ... + + @property + def modes(self) -> Simple.MODES: ... + + @property + def is_pointer(self) -> bool: ... + + @property + def is_signed(self) -> bool: ... + +class Array(lief.pdb.Type): + @property + def numberof_elements(self) -> int: ... + + @property + def element_type(self) -> Optional[lief.pdb.Type]: ... + + @property + def index_type(self) -> Optional[lief.pdb.Type]: ... + +class BitField(lief.pdb.Type): + pass + +class ClassLike(lief.pdb.Type): + @property + def attributes(self) -> Iterator[Optional[Attribute]]: ... + + @property + def methods(self) -> Iterator[Optional[Method]]: ... + + @property + def unique_name(self) -> str: ... + +class Class(ClassLike): + pass + +class Structure(ClassLike): + pass + +class Interface(ClassLike): + pass + +class Attribute: + @property + def name(self) -> str: ... + + @property + def type(self) -> Optional[lief.pdb.Type]: ... + + @property + def field_offset(self) -> int: ... + +class Method: + class TYPE(enum.Enum): + VANILLA = 0 + + VIRTUAL = 1 + + STATIC = 2 + + FRIEND = 3 + + INTRODUCING_VIRTUAL = 4 + + PURE_VIRTUAL = 5 + + PURE_INTRODUCING_VIRTUAL = 6 + + class ACCESS(enum.Enum): + NONE = 0 + + PRIVATE = 1 + + PROTECTED = 2 + + PUBLIC = 3 + + @property + def name(self) -> str: ... + + @property + def type(self) -> Method.TYPE: ... + + @property + def access(self) -> Method.ACCESS: ... + +class Enum(lief.pdb.Type): + class Entry: + @property + def name(self) -> str: ... + + @property + def value(self) -> int: ... + + @property + def unique_name(self) -> str: ... + + @property + def entries(self) -> list[Enum.Entry]: ... + + @property + def underlying_type(self) -> lief.pdb.Type | None: ... + + def find_entry(self, value: int) -> Enum.Entry | None: ... + +class Function(lief.pdb.Type): + @property + def return_type(self) -> Optional[lief.pdb.Type]: ... + + @property + def parameters(self) -> list[Optional[lief.pdb.Type]]: ... + +class Modifier(lief.pdb.Type): + @property + def underlying_type(self) -> Optional[lief.pdb.Type]: ... + +class Pointer(lief.pdb.Type): + @property + def underlying_type(self) -> Optional[lief.pdb.Type]: ... + +class Union(ClassLike): + pass diff --git a/vendor/lief/api/python/lief/py.typed b/vendor/lief/api/python/lief/py.typed new file mode 100644 index 0000000..e69de29 diff --git a/vendor/lief/api/python/lief/runtime/__init__.pyi b/vendor/lief/api/python/lief/runtime/__init__.pyi new file mode 100644 index 0000000..6250706 --- /dev/null +++ b/vendor/lief/api/python/lief/runtime/__init__.pyi @@ -0,0 +1,311 @@ +from collections.abc import Iterator, Mapping +import enum +from typing import Any, Final, Optional, overload + +import lief +import lief.assembly +from lief.runtime import ( + android as android, + linux as linux, + osx as osx, + windows as windows +) + + +class ARCH(enum.Enum): + NONE = 0 + + X86_64 = 1 + + ARM64 = 2 + + RISCV64 = 3 + +class PLATFORMS(enum.Enum): + NONE = 0 + + LINUX = 1 + + WINDOWS = 2 + + ANDROID = 3 + + OSX = 4 + + IOS = 5 + +enabled: bool = ... + +platform: PLATFORMS = ... + +arch: ARCH = ... + +class Host: + name: Final[str] = ... + + home_dir: Final[str] = ... + + tmp_dir: Final[str] = ... + + config_dir: Final[str] = ... + + cache_dir: Final[str] = ... + +class Process: + class EnvVars: + @property + def vars(self) -> dict[str, str]: ... + + @vars.setter + def vars(self, arg: Mapping[str, str], /) -> None: ... + + pid: Final[int] = ... + + tid: Final[int] = ... + + arch: Final[ARCH] = ... + + page_size: Final[int] = ... + + platform: Final[PLATFORMS] = ... + + @staticmethod + def get_env(key: str) -> str | None: ... + + envs: Final[Process.EnvVars] = ... + +class Module: + @property + def name(self) -> str: ... + + @property + def path(self) -> str: ... + + @property + def imagebase(self) -> int: ... + + @property + def end(self) -> int: ... + + @property + def size(self) -> int: ... + + def contains(self, addr: int) -> bool: ... + + @overload + def dump(self) -> bytes: ... + + @overload + def dump(self, filepath: str) -> bytes: ... + + def __str__(self) -> str: ... + +def modules() -> Iterator[Optional[Module]]: ... + +def module_from_name(name: str) -> Optional[Module]: ... + +def module_from_path(path: str) -> Optional[Module]: ... + +def module_from_addr(addr: int) -> Optional[Module]: ... + +class Memory: + class MMAP_FLAGS(enum.IntFlag): + def __repr__(self, /): ... + + NONE = 0 + + PRIVATE = 1 + + ANONYMOUS = 2 + + SHARED = 4 + + FIXED = 8 + + JIT = 16 + + NONE: Memory.PERM = ... + + PRIVATE: Memory.MMAP_FLAGS = ... + + ANONYMOUS: Memory.MMAP_FLAGS = ... + + SHARED: Memory.MMAP_FLAGS = ... + + FIXED: Memory.MMAP_FLAGS = ... + + JIT: Memory.MMAP_FLAGS = ... + + class PERM(enum.IntFlag): + def __repr__(self, /): ... + + NONE = 0 + + READ = 1 + + WRITE = 2 + + EXEC = 4 + + READ: Memory.PERM = ... + + WRITE: Memory.PERM = ... + + EXEC: Memory.PERM = ... + + class Chunk: + @overload + def __init__(self, addr: Any, size: int, permissions: int) -> None: ... + + @overload + def __init__(self, addr: Any, size: int) -> None: ... + + @overload + def __init__(self, addr: Any) -> None: ... + + @property + def addr_ptr(self) -> Any: ... + + @property + def addr(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def permissions(self) -> int: ... + + @property + def page_start(self) -> int: ... + + @property + def page_end(self) -> int: ... + + def change_permissions(self, permission: int) -> Memory.Chunk: ... + + def make_x(self) -> Memory.Chunk: ... + + def make_rw(self) -> Memory.Chunk: ... + + def make_rx(self) -> Memory.Chunk: ... + + def make_rwx(self) -> Memory.Chunk: ... + + def make_ro(self) -> Memory.Chunk: ... + + def cache_flush(self) -> Memory.Chunk: ... + + def is_valid(self) -> bool: ... + + def __bool__(self) -> bool: ... + + def deallocate(self) -> lief.ok_error_t: ... + + def __str__(self) -> str: ... + + @staticmethod + def mmap(size: int, flags: int, permissions: int = 0) -> Memory.Chunk | None: ... + + @staticmethod + def mmap_hint(hint: int, size: int, flags: int, permissions: int = 0) -> Memory.Chunk | None: ... + + @staticmethod + def munmap(chunk: Memory.Chunk) -> lief.ok_error_t: ... + + @staticmethod + def mprotect(chunk: Memory.Chunk, flags: int) -> lief.ok_error_t: ... + + @staticmethod + def perm_str(flags: int) -> str: ... + + @overload + @staticmethod + def write(ptr: Any, size: int, addr: int) -> lief.ok_error_t: ... + + @overload + @staticmethod + def write(buffer: memoryview, addr: int) -> lief.ok_error_t: ... + + @overload + @staticmethod + def write(buffer: bytes, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_u8(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_i8(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_u16(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_i16(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_u32(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_i32(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_u64(value: int, addr: int) -> lief.ok_error_t: ... + + @staticmethod + def write_i64(value: int, addr: int) -> lief.ok_error_t: ... + + @overload + @staticmethod + def read(addr: int, size: int) -> bytes: ... + + @overload + @staticmethod + def read(addr: int, out: Any, size: int) -> None: ... + + @staticmethod + def read_u8(addr: int) -> int: ... + + @staticmethod + def read_i8(addr: int) -> int: ... + + @staticmethod + def read_u16(addr: int) -> int: ... + + @staticmethod + def read_i16(addr: int) -> int: ... + + @staticmethod + def read_u32(addr: int) -> int: ... + + @staticmethod + def read_i32(addr: int) -> int: ... + + @staticmethod + def read_u64(addr: int) -> int: ... + + @staticmethod + def read_i64(addr: int) -> int: ... + +class MemoryLayout: + class Region: + @property + def name(self) -> str: ... + + @property + def addr(self) -> int: ... + + @property + def size(self) -> int: ... + + @property + def end_addr(self) -> int: ... + + def contains(self, addr: int) -> bool: ... + + def __str__(self) -> str: ... + +def memory_layout() -> Iterator[Optional[MemoryLayout.Region]]: ... + +def disassemble(addr: int) -> Iterator[Optional[lief.assembly.Instruction]]: ... + +def assemble(address: int, assembly: str, config: lief.assembly.AssemblerConfig = ...) -> bytes: ... diff --git a/vendor/lief/api/python/lief/runtime/android.pyi b/vendor/lief/api/python/lief/runtime/android.pyi new file mode 100644 index 0000000..883ef7b --- /dev/null +++ b/vendor/lief/api/python/lief/runtime/android.pyi @@ -0,0 +1,52 @@ +import os +from typing import Any, Final, Optional, Union, overload + +import lief.ELF +import lief.runtime + + +class Module(lief.runtime.Module): + @property + def handle(self) -> Any: ... + + def dlsym(self, name: str) -> Any: ... + + @staticmethod + def from_handle(handle: Any) -> Optional[Module]: ... + + @overload + def parse_from_path(self) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_path(self, config: lief.ELF.ParserConfig) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_memory(self) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_memory(self, config: lief.ELF.ParserConfig) -> Optional[lief.ELF.Binary]: ... + +def dlopen(name: Union[str, os.PathLike]) -> Optional[Module]: ... + +class Host: + sdk_version: Final[int | None] = ... + +class Property: + @property + def name(self) -> str: ... + + @property + def value(self) -> str: ... + + @property + def serial(self) -> int: ... + + def __str__(self) -> str: ... + +class Process(lief.runtime.Process): + cmdline: Final[str] = ... + + @staticmethod + def get_system_property(name: str) -> Property | None: ... + + properties: Final[list[Property]] = ... diff --git a/vendor/lief/api/python/lief/runtime/linux.pyi b/vendor/lief/api/python/lief/runtime/linux.pyi new file mode 100644 index 0000000..655351e --- /dev/null +++ b/vendor/lief/api/python/lief/runtime/linux.pyi @@ -0,0 +1,43 @@ +import os +from typing import Any, Final, Optional, Union, overload + +import lief.ELF +import lief.runtime + + +class Module(lief.runtime.Module): + @property + def handle(self) -> Any: ... + + def dlsym(self, name: str) -> Any: ... + + @staticmethod + def from_handle(handle: Any) -> Optional[Module]: ... + + @overload + def parse_from_path(self) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_path(self, config: lief.ELF.ParserConfig) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_memory(self) -> Optional[lief.ELF.Binary]: ... + + @overload + def parse_from_memory(self, config: lief.ELF.ParserConfig) -> Optional[lief.ELF.Binary]: ... + +def dlopen(name: Union[str, os.PathLike]) -> Optional[Module]: ... + +class Host: + sys_name: Final[str] = ... + + sys_release: Final[str] = ... + + sys_version: Final[str] = ... + + hardware: Final[str] = ... + +class Process(lief.runtime.Process): + cmdline: Final[str] = ... + + glibc_version: Final[str] = ... diff --git a/vendor/lief/api/python/lief/runtime/osx.pyi b/vendor/lief/api/python/lief/runtime/osx.pyi new file mode 100644 index 0000000..17f905d --- /dev/null +++ b/vendor/lief/api/python/lief/runtime/osx.pyi @@ -0,0 +1,80 @@ +import os +from typing import Any, Final, Optional, Union, overload + +import lief.MachO +import lief.runtime + + +class Module(lief.runtime.Module): + @property + def handle(self) -> Any: ... + + def dlsym(self, name: str) -> Any: ... + + @staticmethod + def from_handle(handle: Any) -> Optional[Module]: ... + + @overload + def parse_from_path(self) -> Optional[lief.MachO.Binary]: ... + + @overload + def parse_from_path(self, config: lief.MachO.ParserConfig) -> Optional[lief.MachO.Binary]: ... + + @overload + def parse_from_memory(self) -> Optional[lief.MachO.Binary]: ... + + @overload + def parse_from_memory(self, config: lief.MachO.ParserConfig) -> Optional[lief.MachO.Binary]: ... + +def dlopen(name: Union[str, os.PathLike]) -> Optional[Module]: ... + +class Host: + class version_t: + def __init__(self, major: int, minor: int, patch: int) -> None: ... + + major: int + + minor: int + + patch: int + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __le__(self, arg: Host.version_t, /) -> bool: ... + + def __gt__(self, arg: Host.version_t, /) -> bool: ... + + def __ge__(self, arg: Host.version_t, /) -> bool: ... + + def __lt__(self, arg: Host.version_t, /) -> bool: ... + + @staticmethod + def big_sur() -> Host.version_t: ... + + @staticmethod + def monterey() -> Host.version_t: ... + + @staticmethod + def ventura() -> Host.version_t: ... + + @staticmethod + def sonoma() -> Host.version_t: ... + + @staticmethod + def sequoia() -> Host.version_t: ... + + @staticmethod + def tahoe() -> Host.version_t: ... + + def __str__(self) -> str: ... + + os_version_name: Final[str] = ... + + os_version: Final[Host.version_t] = ... + + is_sip_enabled: Final[bool] = ... + +class Process(lief.runtime.Process): + dyld_version: Final[str] = ... diff --git a/vendor/lief/api/python/lief/runtime/windows.pyi b/vendor/lief/api/python/lief/runtime/windows.pyi new file mode 100644 index 0000000..4c59534 --- /dev/null +++ b/vendor/lief/api/python/lief/runtime/windows.pyi @@ -0,0 +1,189 @@ +from collections.abc import Iterator, Mapping +import os +from typing import Any, Final, Optional, Union, overload + +import lief +import lief.PE +import lief.runtime + + +class Module(lief.runtime.Module): + @property + def handle(self) -> Any: ... + + def dlsym(self, name: str) -> Any: ... + + @staticmethod + def from_handle(handle: Any) -> Optional[Module]: ... + + @overload + def parse_from_path(self) -> Optional[lief.PE.Binary]: ... + + @overload + def parse_from_path(self, config: lief.PE.ParserConfig) -> Optional[lief.PE.Binary]: ... + + @overload + def parse_from_memory(self) -> Optional[lief.PE.Binary]: ... + + @overload + def parse_from_memory(self, config: lief.PE.ParserConfig) -> Optional[lief.PE.Binary]: ... + +def dlopen(name: Union[str, os.PathLike]) -> Optional[Module]: ... + +def find_module(name: str) -> Optional[Module]: ... + +class Host: + class version_t: + @overload + def __init__(self) -> None: ... + + @overload + def __init__(self, major: int, minor: int, build_number: int) -> None: ... + + major: int + + minor: int + + build_number: int + + def __eq__(self, arg, /) -> bool: ... + + def __ne__(self, arg, /) -> bool: ... + + def __le__(self, arg: Host.version_t, /) -> bool: ... + + def __gt__(self, arg: Host.version_t, /) -> bool: ... + + def __ge__(self, arg: Host.version_t, /) -> bool: ... + + def __lt__(self, arg: Host.version_t, /) -> bool: ... + + def __str__(self) -> str: ... + + version: Final[Host.version_t] = ... + +class LdrDataTableEntry: + @property + def dll_base(self) -> int: ... + + @property + def entry_point(self) -> int: ... + + @property + def size_of_image(self) -> int: ... + + @property + def full_dll_name(self) -> str: ... + + @property + def base_dll_name(self) -> str: ... + + @property + def flags(self) -> int: ... + + @property + def obsolete_load_count(self) -> int: ... + + @property + def tls_index(self) -> int: ... + + @property + def time_date_stamp(self) -> int: ... + + @property + def entry_point_activation_context(self) -> int: ... + + @property + def lock(self) -> int: ... + + @property + def ddag_node(self) -> int | None: ... + + @property + def load_context(self) -> int | None: ... + + @property + def parent_dll_base(self) -> int | None: ... + + @property + def switch_back_context(self) -> int | None: ... + + @property + def original_base(self) -> int | None: ... + + @property + def load_time(self) -> int | None: ... + + @property + def base_name_hash_value(self) -> int | None: ... + + @property + def load_reason(self) -> int | None: ... + + @property + def implicit_path_options(self) -> int | None: ... + + @property + def reference_count(self) -> int | None: ... + + @property + def dependent_load_flags(self) -> int | None: ... + + @property + def signing_level(self) -> int | None: ... + + @property + def check_sum(self) -> int | None: ... + + @property + def active_patch_image_base(self) -> int | None: ... + + @property + def hot_patch_state(self) -> int | None: ... + + def __str__(self) -> str: ... + +class PEB: + @property + def being_debugged(self) -> bool: ... + + @property + def ldr(self) -> int: ... + + @property + def process_parameters(self) -> int: ... + + @property + def atl_thunk_slist_ptr(self) -> int: ... + + @property + def atl_thunk_slist_ptr32(self) -> int: ... + + @property + def post_process_init_routine(self) -> int: ... + + @property + def session_id(self) -> int: ... + + @property + def entries(self) -> Iterator[Optional[LdrDataTableEntry]]: ... + +class Process(lief.runtime.Process): + peb: Final[Optional[PEB]] = ... + +class injection_context_t: + def __init__(self) -> None: ... + + target_path: str + + args: str + + library: str + + @property + def env(self) -> dict[str, str]: ... + + @env.setter + def env(self, arg: Mapping[str, str], /) -> None: ... + +def inject_spawn(ctx: injection_context_t) -> Union[lief.ok_t, lief.lief_errors]: ... diff --git a/vendor/lief/api/python/platforms/CMakeLists.txt b/vendor/lief/api/python/platforms/CMakeLists.txt deleted file mode 100644 index 98d74f4..0000000 --- a/vendor/lief/api/python/platforms/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -set(LIEF_PYTHON_PLATFORM_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyPlatform.cpp" -) - -set(LIEF_PYTHON_PLATFORM_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyPlatform.hpp") - -source_group("Source Files\\Platform" FILES ${LIEF_PYTHON_PLATFORM_SRC}) -source_group("Header Files\\Platform" FILES ${LIEF_PYTHON_PLATFORM_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_PLATFORM_HDR}" "${LIEF_PYTHON_PLATFORM_SRC}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../") - -include("${CMAKE_CURRENT_LIST_DIR}/android/CMakeLists.txt") diff --git a/vendor/lief/api/python/platforms/android/CMakeLists.txt b/vendor/lief/api/python/platforms/android/CMakeLists.txt deleted file mode 100644 index 43a3475..0000000 --- a/vendor/lief/api/python/platforms/android/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -set(LIEF_PYTHON_ANDROID_SRC - "${CMAKE_CURRENT_LIST_DIR}/pyAndroid.cpp" - "${CMAKE_CURRENT_LIST_DIR}/pyVersion.cpp" -) - -set(LIEF_PYTHON_ANDROID_HDR - "${CMAKE_CURRENT_LIST_DIR}/pyAndroid.hpp") - -source_group("Source Files\\Android" FILES ${LIEF_PYTHON_ANDROID_SRC}) -source_group("Header Files\\Android" FILES ${LIEF_PYTHON_ANDROID_HDR}) - -target_sources(pyLIEF PRIVATE "${LIEF_PYTHON_ANDROID_SRC}" "${LIEF_PYTHON_ANDROID_HDR}") -target_include_directories(pyLIEF PUBLIC "${CMAKE_CURRENT_LIST_DIR}" "${CMAKE_CURRENT_LIST_DIR}/../../") - diff --git a/vendor/lief/api/python/platforms/android/pyAndroid.cpp b/vendor/lief/api/python/platforms/android/pyAndroid.cpp deleted file mode 100644 index ed93771..0000000 --- a/vendor/lief/api/python/platforms/android/pyAndroid.cpp +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAndroid.hpp" - -namespace LIEF { -namespace Android { - -void init_python_module(py::module& m) { - py::module lief_android_module = m.def_submodule("Android", "Python API for Android platform"); - - init_versions(lief_android_module); - -} - -} -} diff --git a/vendor/lief/api/python/platforms/android/pyAndroid.hpp b/vendor/lief/api/python/platforms/android/pyAndroid.hpp deleted file mode 100644 index 3cf50a9..0000000 --- a/vendor/lief/api/python/platforms/android/pyAndroid.hpp +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ANDROID_H_ -#define PY_LIEF_ANDROID_H_ - -#include "LIEF/platforms/android.hpp" -#include "pyLIEF.hpp" - -namespace LIEF { -namespace Android { - -void init_python_module(py::module&); -void init_versions(py::module&); - -} -} - -#endif diff --git a/vendor/lief/api/python/platforms/android/pyVersion.cpp b/vendor/lief/api/python/platforms/android/pyVersion.cpp deleted file mode 100644 index d2a2da2..0000000 --- a/vendor/lief/api/python/platforms/android/pyVersion.cpp +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyAndroid.hpp" -#include "LIEF/platforms/android/version.hpp" - -#define PY_ENUM(x) to_string(x), x - -namespace LIEF { -namespace Android { - -void init_versions(py::module& m) { - py::enum_(m, "ANDROID_VERSIONS") - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_UNKNOWN)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_601)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_700)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_710)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_712)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_800)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_810)) - .value(PY_ENUM(ANDROID_VERSIONS::VERSION_900)); - - m.def("code_name", - &code_name, - "Return the Android code associated with a " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) ".\n" - - "For example: ``Nougat``", - "version"_a); - - m.def("version_string", - &version_string, - "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " as a string.\n" - - "For example: ``7.0.1``", - "version"_a); -} - -} -} diff --git a/vendor/lief/api/python/platforms/pyPlatform.cpp b/vendor/lief/api/python/platforms/pyPlatform.cpp deleted file mode 100644 index 8a9e645..0000000 --- a/vendor/lief/api/python/platforms/pyPlatform.cpp +++ /dev/null @@ -1,35 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyPlatform.hpp" -#include "enums_wrapper.hpp" - -namespace LIEF { - -void init_python_platforms(py::module& m) { - LIEF::enum_(m, "PLATFORMS") - .value("UNKNOWN", PLATFORMS::UNKNOWN) - .value("LINUX", PLATFORMS::LINUX) - .value("ANDROID", PLATFORMS::ANDROID_PLAT) - .value("WINDOWS", PLATFORMS::WINDOWS) - .value("IOS", PLATFORMS::IOS) - .value("OSX", PLATFORMS::OSX); - - m.def("current_platform", ¤t_platform, - "Return the current plaform (Linux, Windows, ...) as a :attr:`lief.PLATFORMS` enum"); - -} - -} diff --git a/vendor/lief/api/python/platforms/pyPlatform.hpp b/vendor/lief/api/python/platforms/pyPlatform.hpp deleted file mode 100644 index 5b8eeb8..0000000 --- a/vendor/lief/api/python/platforms/pyPlatform.hpp +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_PLATFORM_H_ -#define PY_LIEF_PLATFORM_H_ - -#include "LIEF/platforms.hpp" -#include "pyLIEF.hpp" - -namespace LIEF { - -void init_python_platforms(py::module&); - -} - -#endif diff --git a/vendor/lief/api/python/pyErr.cpp b/vendor/lief/api/python/pyErr.cpp deleted file mode 100644 index b40054a..0000000 --- a/vendor/lief/api/python/pyErr.cpp +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyErr.hpp" - -void init_LIEF_errors(py::module& m) { - py::class_(m, "ok_t", - R"delim( - Opaque value returned when a **void** function - is executed successfully. - )delim") - .def("__bool__", [] (const LIEF::ok_t& ok) { return true; }); - - py::enum_(m, "lief_errors", R"delim( - Enum class which represents an error generated by LIEF's functions - )delim") - .value("read_error", lief_errors::read_error) - .value("not_found", lief_errors::not_found) - .value("not_implemented", lief_errors::not_implemented) - .value("not_supported", lief_errors::not_supported) - .value("corrupted", lief_errors::corrupted) - .value("conversion_error", lief_errors::conversion_error) - .value("read_out_of_bound", lief_errors::read_out_of_bound) - .value("asn1_bad_tag", lief_errors::asn1_bad_tag) - .value("file_error", lief_errors::file_error) - .value("file_format_error", lief_errors::file_format_error) - .value("parsing_error", lief_errors::parsing_error) - .value("build_error", lief_errors::build_error) - .value("data_too_large", lief_errors::data_too_large) - ; -} diff --git a/vendor/lief/api/python/pyErr.hpp b/vendor/lief/api/python/pyErr.hpp deleted file mode 100644 index aebeb82..0000000 --- a/vendor/lief/api/python/pyErr.hpp +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ERR_H_ -#define PY_LIEF_ERR_H_ -#include -#include "LIEF/errors.hpp" - -namespace py = pybind11; - - -template >{}, int> = 0> -py::object error_or(Func f, Ts&&... args) { - auto&& ret = f(std::forward(args)...); - if (!ret) { - return py::cast(LIEF::as_lief_err(ret)); - } - return py::cast(ret.value()); -} - - -template >{}, int> = 0> -py::object error_or(Func f, Ts&&... args) { - auto&& ret = std::mem_fn(f)(std::forward(args)...); - if (!ret) { - return py::cast(LIEF::as_lief_err(ret)); - } - return py::cast(ret.value()); -} - - -void init_LIEF_errors(py::module&); - -#endif diff --git a/vendor/lief/api/python/pyExceptions.cpp b/vendor/lief/api/python/pyExceptions.cpp deleted file mode 100644 index adca363..0000000 --- a/vendor/lief/api/python/pyExceptions.cpp +++ /dev/null @@ -1,35 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyLIEF.hpp" -#include "LIEF/exception.hpp" - -void init_LIEF_exceptions(py::module& m) { - auto& exception = py::register_exception(m, "exception"); - auto& bad_file = py::register_exception(m, "bad_file", exception.ptr()); - py::register_exception(m, "bad_format", bad_file.ptr()); - py::register_exception(m, "not_implemented", exception.ptr()); - py::register_exception(m, "not_supported", exception.ptr()); - py::register_exception(m, "read_out_of_bound", exception.ptr()); - py::register_exception(m, "integrity_error", exception.ptr()); - py::register_exception(m, "not_found", exception.ptr()); - py::register_exception(m, "corrupted", exception.ptr()); - py::register_exception(m, "conversion_error", exception.ptr()); - py::register_exception(m, "type_error", exception.ptr()); - py::register_exception(m, "builder_error", exception.ptr()); - py::register_exception(m, "parser_error", exception.ptr()); - auto& pe_error = py::register_exception(m, "pe_error", exception.ptr()); - py::register_exception(m, "pe_bad_section_name", pe_error.ptr()); -} diff --git a/vendor/lief/api/python/pyHash.cpp b/vendor/lief/api/python/pyHash.cpp deleted file mode 100644 index a0cfdd7..0000000 --- a/vendor/lief/api/python/pyHash.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/config.h" -#include "LIEF/hash.hpp" - -#include "pyLIEF.hpp" - -void init_hash_functions(py::module& m) { - m.def("hash", static_cast(&LIEF::hash)); - m.def("hash", static_cast&)>(&LIEF::hash)); - m.def("hash", - [] (py::bytes bytes) { - std::string x = bytes; - std::vector data = {std::begin(x), std::end(x)}; - return LIEF::hash(data); - }); - - m.def("hash", - [] (const std::string& bytes) { - std::vector data = {std::begin(bytes), std::end(bytes)}; - return LIEF::hash(data); - }); -} diff --git a/vendor/lief/api/python/pyIterators.hpp b/vendor/lief/api/python/pyIterators.hpp deleted file mode 100644 index ac4d52a..0000000 --- a/vendor/lief/api/python/pyIterators.hpp +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_ITERATORS_H_ -#define PY_LIEF_ITERATORS_H_ -#include - -#include "LIEF/LIEF.hpp" - -namespace py = pybind11; - -template -void init_ref_iterator(py::handle& m, const char* it_name) { - py::class_(m, it_name) - .def("__getitem__", - [](T& v, size_t i) -> typename T::reference { - if (i >= v.size()) - throw py::index_error(); - return v[i]; - }, - py::return_value_policy::reference_internal, py::keep_alive<1, 0>()) - - .def("__len__", - [] (T& v) { - return v.size(); - }) - - .def("__iter__", - [] (const T& v) { - return py::make_iterator(std::begin(v), std::end(v)); - }, py::keep_alive<0, 1>()) - - .def("__next__", - [] (T& v) -> typename T::reference { - if (v == std::end(v)) { - throw py::stop_iteration(); - } - return *(v++); - }, py::return_value_policy::reference_internal, py::keep_alive<1, 0>()); - - - -} - -#endif diff --git a/vendor/lief/api/python/pyJson.cpp b/vendor/lief/api/python/pyJson.cpp deleted file mode 100644 index d7a6b52..0000000 --- a/vendor/lief/api/python/pyJson.cpp +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/config.h" -#include "LIEF/json.hpp" -#include "LIEF/Abstract/json.hpp" -#include "LIEF/Object.hpp" - -#include "pyLIEF.hpp" - -void init_json_functions(py::module& m) { - m.def("to_json", &LIEF::to_json); - m.def("to_json_from_abstract", &LIEF::to_json_from_abstract); -} diff --git a/vendor/lief/api/python/pyLIEF.cpp b/vendor/lief/api/python/pyLIEF.cpp deleted file mode 100644 index 9790351..0000000 --- a/vendor/lief/api/python/pyLIEF.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "LIEF/logging.hpp" -#include "LIEF/version.h" -#include "pyLIEF.hpp" -#include "pyAbstract.hpp" - -#if defined(LIEF_ELF_SUPPORT) - #include "ELF/pyELF.hpp" -#endif - -#if defined(LIEF_PE_SUPPORT) - #include "PE/pyPE.hpp" -#endif - -#if defined(LIEF_MACHO_SUPPORT) - #include "MachO/pyMachO.hpp" -#endif - -#if defined(LIEF_OAT_SUPPORT) - #include "OAT/pyOAT.hpp" -#endif - -#if defined(LIEF_VDEX_SUPPORT) - #include "VDEX/pyVDEX.hpp" -#endif - -#if defined(LIEF_DEX_SUPPORT) - #include "DEX/pyDEX.hpp" -#endif - -#if defined(LIEF_ART_SUPPORT) - #include "ART/pyART.hpp" -#endif - - -#include "platforms/android/pyAndroid.hpp" -#include "platforms/pyPlatform.hpp" - - -PYBIND11_MODULE(lief, LIEF_module) { - - LIEF_module.attr("__version__") = py::str(LIEF_VERSION); - LIEF_module.attr("__tag__") = py::str(LIEF_TAG); - LIEF_module.attr("__commit__") = py::str(LIEF_COMMIT); - LIEF_module.attr("__is_tagged__") = py::bool_(LIEF_TAGGED); - LIEF_module.doc() = "Python API for LIEF"; - - LIEF::init_python_platforms(LIEF_module); - - init_LIEF_Object_class(LIEF_module); - - init_LIEF_errors(LIEF_module); - - init_LIEF_Logger(LIEF_module); - - // Init custom LIEF exceptions - init_LIEF_exceptions(LIEF_module); - - // Init the LIEF module - LIEF::init_python_module(LIEF_module); - - init_hash_functions(LIEF_module); - - - // Init the ELF module -#if defined(LIEF_ELF_SUPPORT) - LIEF::ELF::init_python_module(LIEF_module); -#endif - - // Init the PE module -#if defined(LIEF_PE_SUPPORT) - LIEF::PE::init_python_module(LIEF_module); -#endif - - // Init the MachO module -#if defined(LIEF_MACHO_SUPPORT) - LIEF::MachO::init_python_module(LIEF_module); -#endif - -// Init the OAT module -#if defined(LIEF_OAT_SUPPORT) - LIEF::OAT::init_python_module(LIEF_module); -#endif - -// Init the VDEX module -#if defined(LIEF_VDEX_SUPPORT) - LIEF::VDEX::init_python_module(LIEF_module); -#endif - -// Init the DEX module -#if defined(LIEF_DEX_SUPPORT) - LIEF::DEX::init_python_module(LIEF_module); -#endif - -// Init the ART module -#if defined(LIEF_ART_SUPPORT) - LIEF::ART::init_python_module(LIEF_module); -#endif - - LIEF::Android::init_python_module(LIEF_module); - - // Init util functions - init_utils_functions(LIEF_module); - - - init_json_functions(LIEF_module); -} diff --git a/vendor/lief/api/python/pyLIEF.hpp b/vendor/lief/api/python/pyLIEF.hpp deleted file mode 100644 index bbac3a8..0000000 --- a/vendor/lief/api/python/pyLIEF.hpp +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PY_LIEF_H_ -#define PY_LIEF_H_ - -#include -#include -#include -#include - -#include - -#include "encoding.hpp" - -#include "pyErr.hpp" - -#define RST_CLASS_REF(X) ":class:`~"#X"`" -#define RST_CLASS_REF_FULL(X) ":class:`"#X"`" - -#define RST_ATTR_REF(X) ":attr:`~"#X"`" -#define RST_ATTR_REF_FULL(X) ":attr:`"#X"`" - -#define RST_METH_REF(X) ":class:`~"#X"`" -#define RST_METH_REF_FULL(X) ":class:`"#X"`" - -namespace py = pybind11; - -using namespace pybind11::literals; - -void init_LIEF_Object_class(py::module&); -void init_LIEF_Logger(py::module&); -void init_LIEF_exceptions(py::module&); -void init_LIEF_module(py::module&); -void init_hash_functions(py::module&); - - -void init_utils_functions(py::module&); - -void init_json_functions(py::module&); - -#endif diff --git a/vendor/lief/api/python/pyLogger.cpp b/vendor/lief/api/python/pyLogger.cpp deleted file mode 100644 index 210bc6d..0000000 --- a/vendor/lief/api/python/pyLogger.cpp +++ /dev/null @@ -1,45 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pyLIEF.hpp" - -#include "LIEF/logging.hpp" - -#define PY_ENUM(x) LIEF::logging::to_string(x), x - -void init_LIEF_Logger(py::module& m) { - py::module logging = m.def_submodule("logging"); - - py::enum_(logging, "LOGGING_LEVEL") - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_TRACE)) - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG)) - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_CRITICAL)) - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_ERR)) - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_WARN)) - .value(PY_ENUM(LIEF::logging::LOGGING_LEVEL::LOG_INFO)); - - logging.def("disable", - &LIEF::logging::disable, - "Disable the logger globally"); - - logging.def("enable", - &LIEF::logging::enable, - "Enable the logger globally"); - - logging.def("set_level", - &LIEF::logging::set_level, - "Change logging level", - "level"_a); -} diff --git a/vendor/lief/api/python/pyObject.cpp b/vendor/lief/api/python/pyObject.cpp deleted file mode 100644 index 4f65c86..0000000 --- a/vendor/lief/api/python/pyObject.cpp +++ /dev/null @@ -1,6 +0,0 @@ -#include "pyLIEF.hpp" -#include "LIEF/Object.hpp" - -void init_LIEF_Object_class(py::module& m) { - py::class_(m, "Object"); -} diff --git a/vendor/lief/api/python/pyUtils.cpp b/vendor/lief/api/python/pyUtils.cpp deleted file mode 100644 index c6e6cbc..0000000 --- a/vendor/lief/api/python/pyUtils.cpp +++ /dev/null @@ -1,217 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "LIEF/PE/utils.hpp" -#include "LIEF/MachO/utils.hpp" -#include "LIEF/ELF/utils.hpp" - -#include "LIEF/OAT.hpp" -#include "LIEF/DEX.hpp" -#include "LIEF/VDEX.hpp" -#include "LIEF/ART.hpp" - -#define LIEF_PE_FORCE_UNDEF -#include "LIEF/PE/undef.h" -#include "pyLIEF.hpp" - -void init_utils_functions(py::module& m) { - - - m.def("shell", - [] (void) { - const auto& InteractiveShellEmbed = py::module::import("IPython").attr("terminal").attr("embed").attr("InteractiveShellEmbed"); - const auto& ipshell = InteractiveShellEmbed("banner1"_a = "Dropping into IPython", "exit_msg"_a = "Leaving Interpreter, back to program."); - return ipshell(); - }, - "Drop into an IPython Interpreter"); - - - m.def("demangle", [] (const std::string& name) -> py::object { - #if defined(__unix__) - int status; - char* demangled_name = abi::__cxa_demangle(name.c_str(), 0, 0, &status); - if (status == 0) { - std::string realname = demangled_name; - free(demangled_name); - return py::str(realname); - } else { - return py::none(); - } - #else - return py::none(); - #endif - }); - - m.def("breakp", - [] (void) { - py::object set_trace = py::module::import("pdb").attr("set_trace"); - return set_trace(); - }, - "Trigger 'pdb.set_trace()'"); - -#if defined(LIEF_PE_SUPPORT) - m.def("is_pe", - static_cast(&LIEF::PE::is_pe), - "Check if the given file is a ``PE`` (from filename)", - "filename"_a); - - m.def("is_pe", - static_cast&)>(&LIEF::PE::is_pe), - "Check if the given raw data is a ``PE``", - "raw"_a); -#endif - -#if defined(LIEF_ELF_SUPPORT) - m.def("is_elf", - static_cast(&LIEF::ELF::is_elf), - "Check if the given file is an ``ELF``", - "filename"_a); - - - m.def("is_elf", - static_cast&)>(&LIEF::ELF::is_elf), - "Check if the given raw data is an ``ELF``", - "raw"_a); -#endif - -#if defined(LIEF_MACHO_SUPPORT) - m.def("is_macho", - static_cast(&LIEF::MachO::is_macho), - "Check if the given file is a ``MachO`` (from filename)", - "filename"_a); - - - m.def("is_macho", - static_cast&)>(&LIEF::MachO::is_macho), - "Check if the given raw data is a ``MachO``", - "raw"_a); - -#endif - - -#if defined(LIEF_OAT_SUPPORT) - m.def("is_oat", - static_cast(&LIEF::OAT::is_oat), - "Check if the given file is an ``OAT`` (from filename)", - "filename"_a); - - - m.def("is_oat", - static_cast&)>(&LIEF::OAT::is_oat), - "Check if the given raw data is an ``OAT``", - "raw"_a); - - m.def("is_oat", - static_cast(&LIEF::OAT::is_oat), - "Check if the given " RST_CLASS_REF(lief.ELF.Binary) " is an ``OAT``", - "elf"_a); - - - m.def("oat_version", - static_cast(&LIEF::OAT::version), - "Return the OAT version of the given file", - "filename"_a); - - - m.def("oat_version", - static_cast&)>(&LIEF::OAT::version), - "Return the OAT version of the raw data", - "raw"_a); - - m.def("oat_version", - static_cast(&LIEF::OAT::version), - "Return the OAT version of the given " RST_CLASS_REF(lief.ELF.Binary) "", - "elf"_a); - -#endif - -#if defined(LIEF_DEX_SUPPORT) - m.def("is_dex", - static_cast(&LIEF::DEX::is_dex), - "Check if the given file is a ``DEX`` (from filename)", - "filename"_a); - - - m.def("is_dex", - static_cast&)>(&LIEF::DEX::is_dex), - "Check if the given raw data is a ``DEX``", - "raw"_a); - - m.def("dex_version", - static_cast(&LIEF::DEX::version), - "Return the OAT version of the given file", - "filename"_a); - - - m.def("dex_version", - static_cast&)>(&LIEF::DEX::version), - "Return the DEX version of the raw data", - "raw"_a); - -#endif - - -#if defined(LIEF_VDEX_SUPPORT) - m.def("is_vdex", - static_cast(&LIEF::VDEX::is_vdex), - "Check if the given file is a ``VDEX`` (from filename)", - "filename"_a); - - m.def("is_vdex", - static_cast&)>(&LIEF::VDEX::is_vdex), - "Check if the given raw data is a ``VDEX``", - "raw"_a); - - m.def("vdex_version", - static_cast(&LIEF::VDEX::version), - "Return the VDEX version of the given file", - "filename"_a); - - - m.def("vdex_version", - static_cast&)>(&LIEF::VDEX::version), - "Return the VDEX version of the raw data", - "raw"_a); - -#endif - - -#if defined(LIEF_ART_SUPPORT) - m.def("is_art", - static_cast(&LIEF::ART::is_art), - "Check if the given file is an ``ART`` (from filename)", - "filename"_a); - - m.def("is_art", - static_cast&)>(&LIEF::ART::is_art), - "Check if the given raw data is an ``ART``", - "raw"_a); - - m.def("art_version", - static_cast(&LIEF::ART::version), - "Return the ART version of the given file", - "filename"_a); - - - m.def("art_version", - static_cast&)>(&LIEF::ART::version), - "Return the ART version of the raw data", - "raw"_a); - -#endif - - -} diff --git a/vendor/lief/api/python/pyproject.toml b/vendor/lief/api/python/pyproject.toml new file mode 100644 index 0000000..5b57771 --- /dev/null +++ b/vendor/lief/api/python/pyproject.toml @@ -0,0 +1,35 @@ +[build-system] +requires = [] +build-backend = "setup" +backend-path = ["backend"] + +[project] +name = "lief" +authors = [ + {name = "Romain Thomas", email = "contact@lief.re"}, +] +description = "Library to instrument executable formats" +requires-python = ">=3.10" +keywords = ["parser", "elf", "pe", "macho", "reverse-engineering"] +license = {text = "Apache License 2.0"} +classifiers = [ + "Development Status :: 4 - Beta", + "Programming Language :: Python :: 3", + "Programming Language :: C++", + "Topic :: Software Development :: Libraries", +] +dynamic = ["version", "readme"] + +[tool.scikit-build] +cmake.version = ">=3.24" + +[[tool.dynamic-metadata]] +provider = {path = "backend", module = "dynamic_provider"} + +[project.urls] +homepage = "https://lief-project.github.io/" +documentation = "https://lief-project.github.io/doc/latest/" +repository = "https://github.com/lief-project/LIEF" +changelog = "https://lief-project.github.io/doc/latest/changelog.html" +Funding = "https://github.com/sponsors/lief-project" +Tracker = "https://github.com/lief-project/LIEF/issues" diff --git a/vendor/lief/api/python/src/ART/CMakeLists.txt b/vendor/lief/api/python/src/ART/CMakeLists.txt new file mode 100644 index 0000000..af10998 --- /dev/null +++ b/vendor/lief/api/python/src/ART/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + pyUtils.cpp + init.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/ART/init.cpp b/vendor/lief/api/python/src/ART/init.cpp new file mode 100644 index 0000000..5589207 --- /dev/null +++ b/vendor/lief/api/python/src/ART/init.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ART/pyART.hpp" +#include "ART/init.hpp" + +#include "LIEF/ART/Parser.hpp" +#include "LIEF/ART/File.hpp" +#include "LIEF/ART/Header.hpp" +#include "LIEF/ART/enums.hpp" +#include "LIEF/ART/EnumToString.hpp" + +#define CREATE(X,Y) create(Y) + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::ART::py { + +inline void init_objects(nb::module_& m) { + CREATE(Parser, m); + CREATE(File, m); + CREATE(Header, m); +} + +inline void init_enums(nb::module_& m) { + nb::enum_(m, "STORAGE_MODES") + .value(PY_ENUM(STORAGE_MODES::STORAGE_UNCOMPRESSED)) + .value(PY_ENUM(STORAGE_MODES::STORAGE_LZ4)) + .value(PY_ENUM(STORAGE_MODES::STORAGE_LZ4HC)); +} + +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("ART", "Python API for ART format"); + + init_enums(mod); + init_objects(mod); + init_utils(mod); +} +} diff --git a/vendor/lief/api/python/src/ART/init.hpp b/vendor/lief/api/python/src/ART/init.hpp new file mode 100644 index 0000000..569e81a --- /dev/null +++ b/vendor/lief/api/python/src/ART/init.hpp @@ -0,0 +1,24 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ART_INIT_H +#define PY_LIEF_ART_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::ART::py { +void init(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/ART/objects/CMakeLists.txt b/vendor/lief/api/python/src/ART/objects/CMakeLists.txt new file mode 100644 index 0000000..976a565 --- /dev/null +++ b/vendor/lief/api/python/src/ART/objects/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + pyHeader.cpp + pyParser.cpp + pyFile.cpp +) diff --git a/vendor/lief/api/python/src/ART/objects/pyFile.cpp b/vendor/lief/api/python/src/ART/objects/pyFile.cpp new file mode 100644 index 0000000..a5b3402 --- /dev/null +++ b/vendor/lief/api/python/src/ART/objects/pyFile.cpp @@ -0,0 +1,36 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/ART/File.hpp" + +#include "ART/pyART.hpp" + +#include +#include + +namespace LIEF::ART::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "File", "ART File representation"_doc) + + .def_prop_ro("header", + nb::overload_cast<>(&File::header), + "Return the ART " RST_CLASS_REF(lief.ART.Header) ""_doc, + nb::rv_policy::reference_internal) + LIEF_DEFAULT_STR(Header); +} + +} diff --git a/vendor/lief/api/python/src/ART/objects/pyHeader.cpp b/vendor/lief/api/python/src/ART/objects/pyHeader.cpp new file mode 100644 index 0000000..8d9106a --- /dev/null +++ b/vendor/lief/api/python/src/ART/objects/pyHeader.cpp @@ -0,0 +1,95 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/ART/Header.hpp" + +#include "ART/pyART.hpp" + +#include +#include +#include + +namespace LIEF::ART::py { + +template<> +void create
(nb::module_& m) { + + nb::class_(m, "Header", "ART Header representation"_doc) + .def_prop_ro("magic", + nb::overload_cast<>(&Header::magic, nb::const_) + ) + .def_prop_ro("version", + nb::overload_cast<>(&Header::version, nb::const_) + ) + .def_prop_ro("image_begin", + nb::overload_cast<>(&Header::image_begin, nb::const_) + ) + .def_prop_ro("image_size", + nb::overload_cast<>(&Header::image_size, nb::const_) + ) + .def_prop_ro("oat_checksum", + nb::overload_cast<>(&Header::oat_checksum, nb::const_) + ) + .def_prop_ro("oat_file_begin", + nb::overload_cast<>(&Header::oat_file_begin, nb::const_) + ) + .def_prop_ro("oat_file_end", + nb::overload_cast<>(&Header::oat_file_end, nb::const_) + ) + .def_prop_ro("oat_data_end", + nb::overload_cast<>(&Header::oat_data_end, nb::const_) + ) + .def_prop_ro("patch_delta", + nb::overload_cast<>(&Header::patch_delta, nb::const_) + ) + .def_prop_ro("image_roots", + nb::overload_cast<>(&Header::image_roots, nb::const_) + ) + .def_prop_ro("pointer_size", + nb::overload_cast<>(&Header::pointer_size, nb::const_) + ) + .def_prop_ro("compile_pic", + nb::overload_cast<>(&Header::compile_pic, nb::const_) + ) + .def_prop_ro("nb_sections", + nb::overload_cast<>(&Header::nb_sections, nb::const_) + ) + .def_prop_ro("nb_methods", + nb::overload_cast<>(&Header::nb_methods, nb::const_) + ) + .def_prop_ro("boot_image_begin", + nb::overload_cast<>(&Header::boot_image_begin, nb::const_) + ) + .def_prop_ro("boot_image_size", + nb::overload_cast<>(&Header::boot_image_size, nb::const_) + ) + .def_prop_ro("boot_oat_begin", + nb::overload_cast<>(&Header::boot_oat_begin, nb::const_) + ) + .def_prop_ro("boot_oat_size", + nb::overload_cast<>(&Header::boot_oat_size, nb::const_) + ) + .def_prop_ro("storage_mode", + nb::overload_cast<>(&Header::storage_mode, nb::const_) + ) + .def_prop_ro("data_size", + nb::overload_cast<>(&Header::data_size, nb::const_) + ) + + LIEF_DEFAULT_STR(Header); +} +} + + diff --git a/vendor/lief/api/python/src/ART/objects/pyParser.cpp b/vendor/lief/api/python/src/ART/objects/pyParser.cpp new file mode 100644 index 0000000..2854a3e --- /dev/null +++ b/vendor/lief/api/python/src/ART/objects/pyParser.cpp @@ -0,0 +1,70 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/ART/Parser.hpp" +#include "LIEF/ART/File.hpp" +#include "LIEF/logging.hpp" + +#include "ART/pyART.hpp" + +#include "typing/InputParser.hpp" +#include "pyutils.hpp" +#include "pyIOStream.hpp" + +#include +#include + +#include +#include +#include +#include + +namespace LIEF::ART::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse", + static_cast(*)(std::string_view)>(&Parser::parse), + "Parse the given filename and return an " RST_CLASS_REF(lief.ART.File) " object"_doc, + "filename"_a, + nb::rv_policy::take_ownership); + + m.def("parse", + static_cast(*)(std::vector, std::string_view)>( + &Parser::parse), + "Parse the given raw data and return an " RST_CLASS_REF(lief.ART.File) " object"_doc, + "raw"_a, "name"_a = "", + nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const std::string& name) -> std::unique_ptr { + if (auto path_str = path_to_str(obj)) { + return Parser::parse(std::move(*path_str)); + } + + if (auto stream = PyIOStream::from_python(obj)) { + auto ptr = std::make_unique(std::move(*stream)); + return Parser::parse(stream->content(), name); + } + logging::log(logging::Level::Err, + "LIEF parser interface does not support Python object: " + + type2str(obj)); + return nullptr; + }, + "obj"_a, "name"_a = "", nb::rv_policy::take_ownership); +} +} diff --git a/vendor/lief/api/python/src/ART/pyART.hpp b/vendor/lief/api/python/src/ART/pyART.hpp new file mode 100644 index 0000000..316e5d0 --- /dev/null +++ b/vendor/lief/api/python/src/ART/pyART.hpp @@ -0,0 +1,26 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ART_H +#define PY_LIEF_ART_H +#include "pyLIEF.hpp" + +namespace LIEF::ART::py { +template +void create(nb::module_&); + +void init_utils(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/ART/pyUtils.cpp b/vendor/lief/api/python/src/ART/pyUtils.cpp new file mode 100644 index 0000000..58b7218 --- /dev/null +++ b/vendor/lief/api/python/src/ART/pyUtils.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ART/pyART.hpp" + +#include "LIEF/ART/utils.hpp" + +#include +#include +#include + +namespace LIEF::ART::py { + +void init_utils(nb::module_& m) { + lief_mod->def("is_art", + nb::overload_cast(&is_art), + "Check if the **file** given in parameter is an ART"_doc, + "path"_a); + + lief_mod->def("is_art", + nb::overload_cast&>(&is_art), + "Check if the **raw data** given in parameter is an ART"_doc, + "raw"_a); + + m.def("version", + nb::overload_cast(&version), + "Return the ART version of the **file** given in parameter"_doc, + "file"_a); + + m.def("version", + nb::overload_cast&>(&version), + "Return the ART version of the **raw data** given in parameter"_doc, + "raw"_a); + + + m.def("android_version", + &android_version, + "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given ART version "_doc, + "art_version"_a); +} + +} + diff --git a/vendor/lief/api/python/src/Abstract/CMakeLists.txt b/vendor/lief/api/python/src/Abstract/CMakeLists.txt new file mode 100644 index 0000000..dd49021 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/CMakeLists.txt @@ -0,0 +1,10 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyHeader.cpp + pySymbol.cpp + pyRelocation.cpp + pySection.cpp + pyFunction.cpp + pyBinary.cpp + pyDebugInfo.cpp +) diff --git a/vendor/lief/api/python/src/Abstract/init.cpp b/vendor/lief/api/python/src/Abstract/init.cpp new file mode 100644 index 0000000..83207a9 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/init.cpp @@ -0,0 +1,45 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyLIEF.hpp" +#include "Abstract/init.hpp" + +#include "LIEF/Abstract/Header.hpp" +#include "LIEF/Abstract/Binary.hpp" +#include "LIEF/Abstract/Section.hpp" +#include "LIEF/Abstract/Symbol.hpp" +#include "LIEF/Abstract/Parser.hpp" +#include "LIEF/Abstract/Relocation.hpp" +#include "LIEF/Abstract/Function.hpp" +#include "LIEF/Abstract/DebugInfo.hpp" + +#define CREATE(X,Y) create(Y) + +namespace LIEF::py { + +void init_objects(nb::module_& m) { + CREATE(Header, m); + CREATE(Binary, m); + CREATE(Section, m); + CREATE(Symbol, m); + CREATE(Parser, m); + CREATE(Relocation, m); + CREATE(Function, m); + CREATE(DebugInfo, m); +} +void init_abstract(nb::module_& m) { + init_objects(m); +} +} diff --git a/vendor/lief/api/python/src/Abstract/init.hpp b/vendor/lief/api/python/src/Abstract/init.hpp new file mode 100644 index 0000000..3bdd587 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/init.hpp @@ -0,0 +1,29 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ABSTRACT_H +#define PY_LIEF_ABSTRACT_H + +namespace nanobind { +class module_; +} + +namespace LIEF::py { +template +void create(nanobind::module_&); + +void init_abstract(nanobind::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/Abstract/pyBinary.cpp b/vendor/lief/api/python/src/Abstract/pyBinary.cpp new file mode 100644 index 0000000..b036a88 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyBinary.cpp @@ -0,0 +1,445 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include + +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" +#include "pyErr.hpp" +#include "pySafeString.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/extra/stl/pathlike.h" +#include "pyIterator.hpp" +#include "nanobind/utils.hpp" + +#include "LIEF/logging.hpp" + +#include "LIEF/Abstract/Binary.hpp" +#include "LIEF/Abstract/Relocation.hpp" +#include "LIEF/Abstract/Symbol.hpp" +#include "LIEF/Abstract/Section.hpp" +#include "LIEF/Abstract/Header.hpp" + +#include "LIEF/Abstract/DebugInfo.hpp" + +#include "LIEF/asm/Engine.hpp" +#include "LIEF/asm/Instruction.hpp" + +#include "pyOwningIterator.hpp" + +#include "Abstract/pyDebugInfoTyHook.hpp" + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_ pybinary(m, "Binary", + R"doc( + Generic interface representing a binary executable. + + This class provides a unified interface across multiple binary formats + such as ELF, PE, Mach-O, and others. It enables users to access binary + components like headers, sections, symbols, relocations, + and functions in a format-agnostic way. + + Subclasses (like :class:`lief.PE.Binary`) implement format-specific API + )doc"_doc); + + nb::enum_(pybinary, "VA_TYPES", + "Enumeration of virtual address types used for patching and memory access."_doc + ) + .value("AUTO", Binary::VA_TYPES::AUTO, + "Automatically determine if the address is absolute or relative (default behavior)"_doc + ) + .value("RVA", Binary::VA_TYPES::RVA, + "Relative Virtual Address (RVA), offset from image base."_doc + ) + .value("VA", Binary::VA_TYPES::VA, + "Absolute Virtual Address." + ); + + nb::enum_(pybinary, "FORMATS") + .value("UNKNOWN", Binary::FORMATS::UNKNOWN) + .value("ELF", Binary::FORMATS::ELF) + .value("PE", Binary::FORMATS::PE) + .value("MACHO", Binary::FORMATS::MACHO) + .value("OAT", Binary::FORMATS::OAT); + + init_ref_iterator(pybinary, "it_sections"); + init_ref_iterator(pybinary, "it_symbols"); + init_ref_iterator(pybinary, "it_relocations"); + + pybinary + .def_prop_ro("debug_info", + &Binary::debug_info, + R"doc( + Return debug info if present. It can be either a + :class:`lief.dwarf.DebugInfo` or a :class:`lief.pdb.DebugInfo` + + For ELF and Mach-O binaries, it returns the given DebugInfo object **only** + if the binary embeds the DWARF debug info in the binary itself. + + For PE file, this function tries to find the **external** PDB using + the :attr:`lief.PE.CodeViewPDB.filename` output (if present). One can also + use :func:`lief.pdb.load` to manually load a PDB. + + .. warning:: + + This function requires LIEF's extended version otherwise it + **always** returns ``None`` + )doc"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("format", + &Binary::format, + "File format (:class:`~.FORMATS`) of the underlying binary."_doc) + + .def_prop_ro("is_pie", + &Binary::is_pie, + "Check if the binary is position independent"_doc) + + .def_prop_ro("has_nx", + &Binary::has_nx, + "Check if the binary has ``NX`` protection (non executable stack)"_doc) + + .def_prop_ro("header", + &Binary::header, + "Binary's abstract header (" RST_CLASS_REF(lief.Header) ")"_doc) + + .def_prop_ro("entrypoint", + &Binary::entrypoint, + "Binary's entrypoint"_doc) + + .def("remove_section", + nb::overload_cast(&Binary::remove_section), + "Remove the section with the given name"_doc, + "name"_a, "clear"_a = false, nb::lock_self()) + + .def_prop_ro("sections", + nb::overload_cast<>(&Binary::sections), + "Return an iterator over the binary's abstract sections (" RST_CLASS_REF(lief.Section) ")"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Binary::relocations), + "Return an iterator over abstract " RST_CLASS_REF(lief.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("exported_functions", + &Binary::exported_functions, + "Return the binary's exported " RST_CLASS_REF(lief.Function) ""_doc) + + .def_prop_ro("imported_functions", + &Binary::imported_functions, + "Return the binary's imported " RST_CLASS_REF(lief.Function) " (name)"_doc) + + .def_prop_ro("libraries", + [] (const Binary& binary) { + const std::vector& imported_libraries = binary.imported_libraries(); + std::vector imported_libraries_encoded; + imported_libraries_encoded.reserve(imported_libraries.size()); + + std::transform( + std::begin(imported_libraries), std::end(imported_libraries), + std::back_inserter(imported_libraries_encoded), + &safe_string); + return imported_libraries_encoded; + }, + "Return binary's imported libraries (name)"_doc, + nb::sig("def libraries(self) -> list[Union[str,bytes]]")) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Binary::symbols), + "Return an iterator over the binary's abstract " RST_CLASS_REF(lief.Symbol) ""_doc, + nb::keep_alive<0, 1>()) + + .def("has_symbol", + &Binary::has_symbol, + "Check if a " RST_CLASS_REF(lief.Symbol) " with the given name exists"_doc, + "symbol_name"_a) + + .def("get_symbol", + nb::overload_cast(&Binary::get_symbol), + R"delim( + Return the :class:`~lief.Symbol` from the given ``name``. + + If the symbol can't be found, it returns None. + )delim"_doc, + "symbol_name"_a, + nb::rv_policy::reference_internal) + + .def("get_function_address", + [] (const Binary& self, const std::string& name) { + return error_or(&Binary::get_function_address, self, name); + }, + "Return the address of the given function name"_doc, + "function_name"_a) + + .def("patch_address", + nb::overload_cast&, Binary::VA_TYPES>(&Binary::patch_address), + R"delim( + Patch the address with the given list of bytes. + The virtual address is specified in the first argument and the content in the second (as a list of bytes). + + If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or + a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. + )delim"_doc, + "address"_a, "patch_value"_a, "va_type"_a = Binary::VA_TYPES::AUTO, + nb::lock_self()) + + .def("patch_address", + nb::overload_cast(&Binary::patch_address), + R"delim( + Patch the address with the given integer value. + The virtual address is specified in the first argument, the integer in the second and the integer's size in the third one. + + If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or + a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. + )delim"_doc, + "address"_a, "patch_value"_a, "size"_a = 8, "va_type"_a = Binary::VA_TYPES::AUTO, + nb::lock_self()) + + + .def("get_content_from_virtual_address", &Binary::get_content_from_virtual_address, + R"delim( + Return the content located at the provided virtual address. + The virtual address is specified in the first argument and size to read (in bytes) in the second. + + If the underlying binary is a PE, one can specify if the virtual address is a :attr:`~lief.Binary.VA_TYPES.RVA` or + a :attr:`~lief.Binary.VA_TYPES.VA`. By default, it is set to :attr:`~lief.Binary.VA_TYPES.AUTO`. + )delim"_doc, + "virtual_address"_a, "size"_a, "va_type"_a = Binary::VA_TYPES::AUTO) + + .def("get_int_from_virtual_address", + [] (const Binary& self, uint64_t va, size_t int_size, Binary::VA_TYPES type) -> IntOrNone { + if (int_size == sizeof(uint8_t)) { + return value_or_none(&Binary::get_int_from_virtual_address, self, va, type); + } + + if (int_size == sizeof(uint16_t)) { + return value_or_none(&Binary::get_int_from_virtual_address, self, va, type); + } + + if (int_size == sizeof(uint32_t)) { + return value_or_none(&Binary::get_int_from_virtual_address, self, va, type); + } + + if (int_size == sizeof(uint64_t)) { + return value_or_none(&Binary::get_int_from_virtual_address, self, va, type); + } + + return nb::none(); + }, R"doc( + Get an integer representation of the data at the given address + )doc"_doc, "address"_a, "interger_size"_a, "type"_a = Binary::VA_TYPES::AUTO + ) + + .def_prop_ro("abstract", + [] (nb::object& self) -> nb::object { + auto* ab = nb::cast(self); + const nb::handle base_type = nb::type(); + nb::object py_inst = nb::inst_reference(base_type, ab, self); + nb::inst_set_state(py_inst, /*ready=*/true, /*destruct=*/false); + return py_inst; + }, + R"delim( + Return the abstract representation of the current binary (:class:`lief.Binary`) + )delim"_doc, + nb::sig("def abstract(self) -> lief.Binary"), + nb::rv_policy::reference_internal) + + .def_prop_ro("concrete", + [] (nb::object& self) { + return nb::cast(nb::cast(self)); + }, + R"delim( + The *concrete* representation of the binary. Basically, this property casts a :class:`lief.Binary` + into a :class:`lief.PE.Binary`, :class:`lief.ELF.Binary` or :class:`lief.MachO.Binary`. + + See also: :attr:`lief.Binary.abstract` + )delim"_doc, + nb::sig("def concrete(self) -> lief.ELF.Binary | lief.PE.Binary | lief.MachO.Binary"), + nb::rv_policy::reference) + + .def_prop_ro("ctor_functions", + &Binary::ctor_functions, + "Constructor functions that are called prior to any other functions"_doc) + + .def("xref", + &Binary::xref, + "Return all **virtual addresses** that *use* the ``address`` given in parameter"_doc, + "virtual_address"_a) + + .def("offset_to_virtual_address", + [] (const Binary& self, uint64_t offset, uint64_t slide) { + return error_or(&Binary::offset_to_virtual_address, self, offset, slide); + }, + "Convert an offset into a virtual address."_doc, + "offset"_a, "slide"_a = 0) + + .def_prop_ro("imagebase", + &Binary::imagebase, + "Default image base (i.e. if the ASLR is not enabled)"_doc) + + .def_prop_ro("original_size", + nb::overload_cast<>(&LIEF::Binary::original_size, nb::const_), + "Original size of the binary"_doc) + + .def("disassemble", [] (const Binary& self, uint64_t address) { + auto insts = LIEF::py::owning_range(self.disassemble(address)); + return nb::make_iterator( + nb::type(), "instructions_it", insts + ); + }, "address"_a, nb::keep_alive<0, 1>(), + R"doc( + Disassemble code starting at the given virtual address. + + .. code-block:: python + + insts = binary.disassemble(0xacde, 100); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + + .def("disassemble", [] (const Binary& self, uint64_t address, size_t size) { + auto insts = LIEF::py::owning_range(self.disassemble(address, size)); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "address"_a, "size"_a, nb::keep_alive<0, 1>(), + R"doc( + Disassemble code starting at the given virtual address and with the given + size. + + .. code-block:: python + + insts = binary.disassemble(0xacde, 100); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + + .def("disassemble", [] (const Binary& self, const std::string& function) { + auto insts = LIEF::py::owning_range(self.disassemble(function)); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "function_name"_a, nb::keep_alive<0, 1>(), + R"doc( + Disassemble code for the given symbol name + + .. code-block:: python + + insts = binary.disassemble("__libc_start_main"); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + + .def("disassemble_from_bytes", + [] (const Binary& self, const nb::bytes& buffer, uint64_t address) { + auto insts = LIEF::py::owning_range(self.disassemble( + reinterpret_cast(buffer.c_str()), + buffer.size(), address + )); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "buffer"_a, "address"_a = 0, nb::keep_alive<0, 1>(), nb::keep_alive<0, 2>(), + R"doc( + Disassemble code from the provided bytes + + .. code-block:: python + + raw = bytes(binary.get_section(".text").content) + insts = binary.disassemble_from_bytes(raw); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + + .def("assemble", + [] (Binary& self, uint64_t address, const std::string& Asm, + assembly::AssemblerConfig& config) + { + return nb::to_bytes(self.assemble(address, Asm, config)); + }, "address"_a, "assembly"_a, "config"_a = assembly::AssemblerConfig::default_config(), + R"doc( + Assemble **and patch** the provided assembly code at the specified address. + + The function returns the generated assembly bytes. + + Example: + + .. code-block:: python + + bin.assemble(0x12000440, """ + xor rax, rbx; + mov rcx, rax; + """) + + If you need to configure the assembly engine or to define addresses for + symbols, you can provide your own :class:`~.assembly.AssemblerConfig` instance. + )doc"_doc + ) + + .def_prop_ro("page_size", &Binary::page_size, + R"doc( + Get the default memory page size according to the architecture and the + format of the current binary + )doc"_doc + ) + + .def("load_debug_info", [] (Binary& self, const nb::PathLike& pathlike) { + return self.load_debug_info(pathlike); + }, "path"_a, nb::lock_self(), nb::rv_policy::reference_internal, + R"doc( + Load and associate an external debug file (e.g., DWARF or PDB) with this + binary. + + This method attempts to load the debug information from the file located + at the given path, and binds it to the current binary instance. If + successful, it returns the loaded :class:`~.DebugInfo` object. + + .. warning:: + + It is the caller's responsibility to ensure that the debug file is + compatible with the binary. Incorrect associations may lead to + inconsistent or invalid results. + + .. note:: + + This function does not verify that the debug file matches the binary's + unique identifier (e.g., build ID, GUID). + )doc"_doc + ) + + .def_prop_ro("virtual_size", + &Binary::virtual_size, + "Size of the binary when mapped in memory"_a) + + LIEF_DEFAULT_STR(Binary); + +} +} diff --git a/vendor/lief/api/python/src/Abstract/pyDebugInfo.cpp b/vendor/lief/api/python/src/Abstract/pyDebugInfo.cpp new file mode 100644 index 0000000..f0f2393 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyDebugInfo.cpp @@ -0,0 +1,39 @@ +#include "pyLIEF.hpp" +#include "LIEF/Abstract/DebugInfo.hpp" +#include "Abstract/init.hpp" + +#include +#include + +#include "enums_wrapper.hpp" + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_ dbg_info(m, "DebugInfo", + R"doc( + This class provides a generic interface for accessing debug information + from different formats such as DWARF and PDB. + + Users can use this interface to access high-level debug features like + resolving function addresses. + + See: :class:`~lief.pdb.DebugInfo`, :class:`lief.dwarf.DebugInfo` + )doc"_doc + ); + enum_(dbg_info, "FORMAT") + .value("UNKNOWN", DebugInfo::FORMAT::UNKNOWN) + .value("DWARF", DebugInfo::FORMAT::DWARF) + .value("PDB", DebugInfo::FORMAT::PDB); + + dbg_info + .def_prop_ro("format", &DebugInfo::format, + "The actual debug format (PDB/DWARF)"_doc + ) + .def("find_function_address", &DebugInfo::find_function_address, + "Attempt to resolve the address of the function specified by ``name``."_doc, + "name"_a + ); +} + +} diff --git a/vendor/lief/api/python/src/Abstract/pyDebugInfoTyHook.hpp b/vendor/lief/api/python/src/Abstract/pyDebugInfoTyHook.hpp new file mode 100644 index 0000000..b2f9ebf --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyDebugInfoTyHook.hpp @@ -0,0 +1,23 @@ +#pragma once + +#include + +#include "LIEF/DWARF/DebugInfo.hpp" +#include "LIEF/PDB/DebugInfo.hpp" + +namespace nanobind::detail { +template<> struct type_hook { + static const std::type_info* get(const LIEF::DebugInfo *src) { + if (src) { + if (LIEF::dwarf::DebugInfo::classof(src)) { + return &typeid(LIEF::dwarf::DebugInfo); + } + + if (LIEF::pdb::DebugInfo::classof(src)) { + return &typeid(LIEF::pdb::DebugInfo); + } + } + return &typeid(LIEF::dwarf::Type); + } +}; +} diff --git a/vendor/lief/api/python/src/Abstract/pyFunction.cpp b/vendor/lief/api/python/src/Abstract/pyFunction.cpp new file mode 100644 index 0000000..a87de0a --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyFunction.cpp @@ -0,0 +1,76 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include + +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" + +#include "LIEF/Abstract/Function.hpp" +#include "enums_wrapper.hpp" + +#define PY_ENUM(x) LIEF::to_string(x), x + +namespace LIEF::py { + +template<> +void create(nb::module_& m) { + nb::class_ pyfunction(m, "Function", + R"delim( + Class which represents a Function in an executable file format. + )delim"_doc); + + enum_(pyfunction, "FLAGS", nb::is_flag()) + .value(PY_ENUM(Function::FLAGS::NONE)) + .value(PY_ENUM(Function::FLAGS::IMPORTED)) + .value(PY_ENUM(Function::FLAGS::EXPORTED)) + .value(PY_ENUM(Function::FLAGS::CONSTRUCTOR)) + .value(PY_ENUM(Function::FLAGS::DESTRUCTOR)) + .value(PY_ENUM(Function::FLAGS::DEBUG_INFO)); + + pyfunction + .def(nb::init()) + .def(nb::init()) + .def(nb::init()) + .def(nb::init()) + + .def("add", &Function::add, + "Add the given " RST_CLASS_REF(lief.Function.FLAGS) ""_doc, + "flag"_a) + + .def("has", &Function::has, + "Check if the function has the given flag"_doc, + "flag"_a) + + .def_prop_ro("flags", &Function::flags, + "Function flags"_doc) + + .def_prop_ro("flags_list", + &Function::flags_list, + "Function flags as a list of " RST_CLASS_REF(lief.Function.FLAGS) ""_doc) + + .def_prop_rw("address", + nb::overload_cast<>(&Function::address, nb::const_), + nb::overload_cast(&Function::address), + "Function's address"_doc) + + LIEF_DEFAULT_STR(Function); +} +} diff --git a/vendor/lief/api/python/src/Abstract/pyHeader.cpp b/vendor/lief/api/python/src/Abstract/pyHeader.cpp new file mode 100644 index 0000000..7db3829 --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyHeader.cpp @@ -0,0 +1,117 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include + +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" + +#include "LIEF/Abstract/Header.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::py { + +template<> +void create
(nb::module_& m) { + nb::class_ obj(m, "Header", + R"delim( + Class which represents an abstracted Header + )delim"_doc); + + #define ENTRY(X) .value(to_string(Header::ARCHITECTURES::X), Header::ARCHITECTURES::X) + enum_(obj, "ARCHITECTURES") + ENTRY(UNKNOWN) + ENTRY(ARM) + ENTRY(ARM64) + ENTRY(MIPS) + ENTRY(X86) + ENTRY(X86_64) + ENTRY(PPC) + ENTRY(SPARC) + ENTRY(SYSZ) + ENTRY(XCORE) + ENTRY(RISCV) + ENTRY(LOONGARCH) + ENTRY(PPC64) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Header::ENDIANNESS::X), Header::ENDIANNESS::X) + enum_(obj, "ENDIANNESS") + ENTRY(UNKNOWN) + ENTRY(BIG) + ENTRY(LITTLE) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Header::MODES::X), Header::MODES::X) + enum_(obj, "MODES") + ENTRY(NONE) + ENTRY(BITS_16) + ENTRY(BITS_32) + ENTRY(BITS_64) + ENTRY(THUMB) + ENTRY(ARM64E) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Header::OBJECT_TYPES::X), Header::OBJECT_TYPES::X) + enum_(obj, "OBJECT_TYPES") + ENTRY(UNKNOWN) + ENTRY(EXECUTABLE) + ENTRY(LIBRARY) + ENTRY(OBJECT) + ; + #undef ENTRY + + obj + .def_prop_ro("architecture", + nb::overload_cast<>(&Header::architecture, nb::const_), + "Target architecture"_doc) + + .def_prop_ro("modes", + nb::overload_cast<>(&Header::modes, nb::const_), + "Architecture details"_doc) + + .def_prop_ro("modes_list", + nb::overload_cast<>(&Header::modes_list, nb::const_), + "*Modes* as a list"_doc) + + .def_prop_ro("entrypoint", + nb::overload_cast<>(&Header::entrypoint, nb::const_), + "Binary entrypoint"_doc) + + .def_prop_ro("object_type", + nb::overload_cast<>(&Header::object_type, nb::const_), + "Type of the binary (executable, library...)"_doc) + + .def_prop_ro("endianness", + nb::overload_cast<>(&Header::endianness, nb::const_), + "Binary endianness"_doc) + + .def_prop_ro("is_32", + &Header::is_32, + "``True`` if the binary targets a ``32-bits`` architecture"_doc) + + .def_prop_ro("is_64", + &Header::is_64, + "``True`` if the binary targets a ``64-bits`` architecture"_doc) + + LIEF_DEFAULT_STR(Header); +} +} diff --git a/vendor/lief/api/python/src/Abstract/pyRelocation.cpp b/vendor/lief/api/python/src/Abstract/pyRelocation.cpp new file mode 100644 index 0000000..9ad5f9a --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pyRelocation.cpp @@ -0,0 +1,46 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" + +#include "LIEF/Abstract/hash.hpp" +#include "LIEF/Abstract/Relocation.hpp" + +namespace LIEF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Relocation", + R"delim( + Class which represents an abstracted Relocation + )delim") + + .def_prop_rw("address", + nb::overload_cast<>(&Relocation::address, nb::const_), + nb::overload_cast(&Relocation::address), + "Relocation's address"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&Relocation::size, nb::const_), + nb::overload_cast(&Relocation::size), + "Relocation's size (in **bits**)"_doc) + + LIEF_DEFAULT_STR(Relocation); +} +} diff --git a/vendor/lief/api/python/src/Abstract/pySection.cpp b/vendor/lief/api/python/src/Abstract/pySection.cpp new file mode 100644 index 0000000..146a6cb --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pySection.cpp @@ -0,0 +1,143 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "Abstract/init.hpp" + +#include "pyLIEF.hpp" +#include "pySafeString.hpp" +#include "typing.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "LIEF/Abstract/Section.hpp" + + +namespace LIEF::py { + +struct search_result : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(search_result, nanobind::object); + + NB_OBJECT_DEFAULT(search_result, object, "Optional[int]", check) + + static bool check(handle) { + return true; + } +}; + +template<> +void create
(nb::module_& m) { + nb::class_(m, "Section", + R"delim( + Class which represents an abstracted section + )delim"_doc) + + .def_prop_rw("name", + [] (const Section& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&Section::name), + "Section's name"_doc) + + .def_prop_ro("fullname", + [] (const Section& obj) { + return nb::to_bytes(obj.fullname()); + }, + "Return the **fullname** of the section including the trailing bytes"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&Section::size, nb::const_), + nb::overload_cast(&Section::size), + "Section's size"_doc) + + .def_prop_rw("offset", + nb::overload_cast<>(&Section::offset, nb::const_), + nb::overload_cast(&Section::offset), + "Section's file offset"_doc) + + .def_prop_rw("virtual_address", + nb::overload_cast<>(&Section::virtual_address, nb::const_), + nb::overload_cast(&Section::virtual_address), + "Section's virtual address"_doc) + + .def_prop_rw("content", + nb::overload_cast<>(&Section::content, nb::const_), + nb::overload_cast&>(&Section::content), + "Section's content"_doc) + + .def_prop_ro("entropy", + &Section::entropy, + "Section's entropy"_doc) + + .def("search", + [] (const Section& self, + uint64_t number, size_t pos, size_t size) -> search_result + { + size_t res = self.search(number, pos, size); + if (res == Section::npos) { + return nb::none(); + } + return nb::cast(res); + }, + "Look for **integer** within the current section"_doc, + "number"_a, "pos"_a = 0, "size"_a = 0) + + .def("search", + [] (const Section& self, + const std::string& str, size_t pos) -> search_result + { + size_t res = self.search(str, pos); + if (res == Section::npos) { + return nb::none(); + } + return nb::cast(res); + }, + "Look for **string** within the current section"_doc, + "str"_a, "pos"_a = 0) + + .def("search", + [] (const Section& self, nb::bytes bytes, size_t pos) -> search_result + { + std::string raw_str(bytes.c_str(), bytes.size()); + const std::vector raw = { + std::make_move_iterator(std::begin(raw_str)), + std::make_move_iterator(std::end(raw_str)) + }; + size_t res = self.search(raw, pos); + if (res == Section::npos) { + return nb::none(); + } + return nb::cast(res); + }, + "Look for the given bytes within the current section"_doc, + "bytes"_a, "pos"_a = 0) + + .def("search_all", + nb::overload_cast(&Section::search_all, nb::const_), + "Look for **all** integers within the current section"_doc, + "number"_a, "size"_a = 0) + + .def("search_all", + nb::overload_cast(&Section::search_all, nb::const_), + "Look for all **strings** within the current section"_doc, + "str"_a) + + LIEF_DEFAULT_STR(Section); + +} +} diff --git a/vendor/lief/api/python/src/Abstract/pySymbol.cpp b/vendor/lief/api/python/src/Abstract/pySymbol.cpp new file mode 100644 index 0000000..bdb50ef --- /dev/null +++ b/vendor/lief/api/python/src/Abstract/pySymbol.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/Abstract/Symbol.hpp" + +namespace LIEF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Symbol", + R"delim( + This class represents a symbol in an executable format. + )delim"_doc) + + .def_prop_rw("name", + [] (const Symbol& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&Symbol::name), + "Symbol's name"_doc) + + .def_prop_rw("value", + nb::overload_cast<>(&Symbol::value, nb::const_), + nb::overload_cast(&Symbol::value), + "Symbol's value"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&Symbol::size, nb::const_), + nb::overload_cast(&Symbol::size), + "Symbol's size"_doc) + + LIEF_DEFAULT_STR(Symbol); +} +} diff --git a/vendor/lief/api/python/src/BinaryStream/CMakeLists.txt b/vendor/lief/api/python/src/BinaryStream/CMakeLists.txt new file mode 100644 index 0000000..e04101f --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/CMakeLists.txt @@ -0,0 +1,7 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyBinaryStream.cpp + pyVectorStream.cpp + pySpanStream.cpp + pyFileStream.cpp +) diff --git a/vendor/lief/api/python/src/BinaryStream/init.cpp b/vendor/lief/api/python/src/BinaryStream/init.cpp new file mode 100644 index 0000000..741f043 --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/init.cpp @@ -0,0 +1,31 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "BinaryStream/init.hpp" + +namespace LIEF { +class BinaryStream; +class VectorStream; +class SpanStream; +class FileStream; +} + +namespace LIEF::py { +void init_binarystream(nb::module_& m) { + create(m); + create(m); + create(m); + create(m); +} +} diff --git a/vendor/lief/api/python/src/BinaryStream/init.hpp b/vendor/lief/api/python/src/BinaryStream/init.hpp new file mode 100644 index 0000000..c4b4180 --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/init.hpp @@ -0,0 +1,22 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_BINARYSTREAM_INIT_H +#define PY_LIEF_BINARYSTREAM_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::py { +void init_binarystream(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/BinaryStream/pyBinaryStream.cpp b/vendor/lief/api/python/src/BinaryStream/pyBinaryStream.cpp new file mode 100644 index 0000000..6e685eb --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/pyBinaryStream.cpp @@ -0,0 +1,178 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyLIEF.hpp" + +#include "nanobind/extra/stl/lief_result.h" +#include "nanobind/extra/stl/u16string.h" + +#include +#include +#include + +#include + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "BinaryStream") + .def_prop_ro("size", &BinaryStream::size) + .def("__bool__", &BinaryStream::is_valid) + .def("__len__", &BinaryStream::size) + + .def_prop_ro("is_memory_stream", &BinaryStream::is_memory_stream) + + .def_prop_ro("pos", &BinaryStream::pos) + .def("increment_pos", &BinaryStream::increment_pos, + "value"_a, nb::rv_policy::reference_internal + ) + .def("decrement_pos", &BinaryStream::decrement_pos, + "value"_a + ) + .def("setpos", &BinaryStream::setpos, + "value"_a + ) + + .def("read_uleb128", [] (BinaryStream& self) { + size_t size = 0; + return std::make_tuple(self.read_uleb128(&size), size); + }) + + .def("read_sleb128", [] (BinaryStream& self) { + size_t size = 0; + return std::make_tuple(self.read_sleb128(&size), size); + }) + + .def("read_dwarf_encoded", &BinaryStream::read_dwarf_encoded, + "encoding"_a + ) + + .def("read_string", &BinaryStream::read_string, + "maxsize"_a = (size_t)(-1llu) + ) + + .def("peek_string", &BinaryStream::peek_string, + "maxsize"_a = (size_t)(-1llu) + ) + + .def("peek_string_at", &BinaryStream::peek_string_at, + "offset"_a, "maxsize"_a = (size_t)(-1llu) + ) + + .def("read_u16string", + nb::overload_cast<>(&BinaryStream::read_u16string, nb::const_)) + + .def("read_u16string", + nb::overload_cast(&BinaryStream::read_u16string, nb::const_), + "length"_a + ) + + .def("peek_u16string", + nb::overload_cast<>(&BinaryStream::peek_u16string, nb::const_)) + + .def("peek_u16string", + nb::overload_cast(&BinaryStream::peek_u16string, nb::const_), + "length"_a + ) + + .def("peek_u16string", + nb::overload_cast(&BinaryStream::peek_u16string_at, nb::const_), + "offset"_a, "length"_a + ) + + .def("read_mutf8", + nb::overload_cast(&BinaryStream::read_mutf8, nb::const_), + "maxsize"_a = (size_t)(-1llu) + ) + + .def("peek_data", + [] (BinaryStream& self, uint64_t offset, uint64_t size, uint64_t virtual_address) -> std::optional + { + std::vector data; + if (!self.peek_data(data, offset, size, virtual_address)) { + return std::nullopt; + } + return nb::bytes(data.data(), data.size()); + }, "offset"_a, "size"_a, "virtual_address"_a = 0 + ) + + .def("read_data", + [] (BinaryStream& self, uint64_t size) -> std::optional + { + std::vector data; + if (!self.read_data(data, size)) { + return std::nullopt; + } + return nb::bytes(data.data(), data.size()); + }, "size"_a + ) + + .def("read_data", + [] (BinaryStream& self) -> std::optional + { + std::vector data; + if (!self.read_data(data)) { + return std::nullopt; + } + return nb::bytes(data.data(), data.size()); + } + ) + + .def("align", &BinaryStream::align, "align_on"_a) + .def("set_endian_swap", &BinaryStream::set_endian_swap, "swap"_a) + + .def("read_u8", &BinaryStream::read) + .def("read_i8", &BinaryStream::read) + + .def("peek_u8", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_u8", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + .def("peek_i8", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_i8", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + + .def("read_u16", &BinaryStream::read) + .def("read_i16", &BinaryStream::read) + + .def("peek_u16", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_u16", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + .def("peek_i16", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_i16", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + + .def("read_u32", &BinaryStream::read) + .def("read_i32", &BinaryStream::read) + + .def("peek_u32", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_u32", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + .def("peek_i32", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_i32", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + + .def("read_u64", &BinaryStream::read) + .def("read_i64", &BinaryStream::read) + + .def("peek_u64", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_u64", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + .def("peek_i64", nb::overload_cast<>(&BinaryStream::peek, nb::const_)) + .def("peek_i64", nb::overload_cast(&BinaryStream::peek, nb::const_), "offset"_a) + + .def_prop_ro("start", nb::overload_cast<>(&BinaryStream::start)) + .def_prop_ro("start_addr", [] (BinaryStream& self) { return (uintptr_t)self.start(); }) + + .def_prop_ro("end", nb::overload_cast<>(&BinaryStream::end)) + .def_prop_ro("end_addr", [] (BinaryStream& self) { return (uintptr_t)self.end(); }) + + .def_prop_ro("p", nb::overload_cast<>(&BinaryStream::p)) + .def_prop_ro("p_addr", [] (BinaryStream& self) { return (uintptr_t)self.p(); }) + ; +} +} diff --git a/vendor/lief/api/python/src/BinaryStream/pyFileStream.cpp b/vendor/lief/api/python/src/BinaryStream/pyFileStream.cpp new file mode 100644 index 0000000..0d6927f --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/pyFileStream.cpp @@ -0,0 +1,39 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyLIEF.hpp" + + +#include +#include +#include + +#include "typing/StrOrPath.hpp" + +#include "nanobind/extra/memoryview.hpp" +#include "nanobind/extra/stl/lief_result.h" + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "FileStream") + .def_static("from_file", [] (typing::StrOrPath file) { + return FileStream::from_file(*file.to_string()); + }) + .def_prop_ro("content", [] (FileStream& self) { + return nb::to_bytes(self.content()); + }) + ; +} +} diff --git a/vendor/lief/api/python/src/BinaryStream/pySpanStream.cpp b/vendor/lief/api/python/src/BinaryStream/pySpanStream.cpp new file mode 100644 index 0000000..cde14a6 --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/pySpanStream.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyLIEF.hpp" + +#include +#include +#include +#include + +#include "nanobind/extra/memoryview.hpp" +#include "nanobind/extra/stl/lief_result.h" + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "SpanStream") + .def("slice", nb::overload_cast(&SpanStream::slice, nb::const_), + "offset"_a, "size"_a + ) + + .def("slice", nb::overload_cast(&SpanStream::slice, nb::const_), + "offset"_a + ) + + .def("to_vector", &SpanStream::to_vector) + + .def_prop_ro("content", [] (SpanStream& self) { + return nb::to_bytes(self.content()); + }) + + .def_prop_ro("__bytes__", [] (SpanStream& self) { + return nb::to_bytes(self.content()); + }) + + ; +} +} diff --git a/vendor/lief/api/python/src/BinaryStream/pyVectorStream.cpp b/vendor/lief/api/python/src/BinaryStream/pyVectorStream.cpp new file mode 100644 index 0000000..c5e57a9 --- /dev/null +++ b/vendor/lief/api/python/src/BinaryStream/pyVectorStream.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyLIEF.hpp" + + +#include +#include +#include + +#include "nanobind/extra/memoryview.hpp" +#include "nanobind/extra/stl/lief_result.h" +#include "typing/StrOrPath.hpp" + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "VectorStream") + .def_static("from_file", [] (typing::StrOrPath path) { + return VectorStream::from_file(*path.to_string()); + }, "path"_a) + + .def_static("from_bytes", [] (nb::bytes buffer) { + return std::make_unique(nb::to_vector(buffer)); + }, "buffer"_a) + + .def_prop_ro("content", [] (VectorStream& self) { + return nb::to_memoryview(self.content()); + }) + + .def("slice", nb::overload_cast(&VectorStream::slice, nb::const_), + "offset", "size") + + .def("slice", nb::overload_cast(&VectorStream::slice, nb::const_), + "offset") + ; +} +} diff --git a/vendor/lief/api/python/src/CMakeLists.txt b/vendor/lief/api/python/src/CMakeLists.txt new file mode 100644 index 0000000..321ede0 --- /dev/null +++ b/vendor/lief/api/python/src/CMakeLists.txt @@ -0,0 +1,60 @@ +target_include_directories(pyLIEF PUBLIC + "${CMAKE_CURRENT_SOURCE_DIR}" +) + +target_sources(pyLIEF PRIVATE + pyLIEF.cpp + pySafeString.cpp + pyErr.cpp + pyIOStream.cpp + pyutils.cpp + pyParser.cpp + pyWriteStream.cpp + pyDebugDeclOpt.cpp +) + +add_subdirectory(typing) +add_subdirectory(Abstract) +add_subdirectory(platforms) + +add_subdirectory(DWARF) +add_subdirectory(PDB) +add_subdirectory(ObjC) +add_subdirectory(DyldSharedCache) +add_subdirectory(asm) +add_subdirectory(BinaryStream) + +add_subdirectory(runtime) + +if(LIEF_ELF) + add_subdirectory(ELF) +endif() + +if(LIEF_PE) + add_subdirectory(PE) +endif() + +if(LIEF_MACHO) + add_subdirectory(MachO) +endif() + +if(LIEF_COFF) + add_subdirectory(COFF) +endif() + +if(LIEF_OAT) + add_subdirectory(OAT) +endif() + +if(LIEF_DEX) + add_subdirectory(DEX) +endif() + +if(LIEF_VDEX) + add_subdirectory(VDEX) +endif() + +if(LIEF_ART) + add_subdirectory(ART) +endif() + diff --git a/vendor/lief/api/python/src/COFF/CMakeLists.txt b/vendor/lief/api/python/src/COFF/CMakeLists.txt new file mode 100644 index 0000000..ba6d99e --- /dev/null +++ b/vendor/lief/api/python/src/COFF/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyUtils.cpp +) + +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/COFF/init.cpp b/vendor/lief/api/python/src/COFF/init.cpp new file mode 100644 index 0000000..36325ad --- /dev/null +++ b/vendor/lief/api/python/src/COFF/init.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/init.hpp" +#include "COFF/pyCOFF.hpp" + +namespace LIEF::COFF { +class ParserConfig; +class Parser; +class Binary; +class Header; +class String; +class RegularHeader; +class BigObjHeader; +class Symbol; +class Section; +class Relocation; +class AuxiliarySymbol; +} + +namespace LIEF::COFF::py { + +void init(nb::module_& m) { + nb::module_ coff_mod = m.def_submodule("COFF", "Python API for the COFF format"); + init_utils(coff_mod); + + create
(coff_mod); + create(coff_mod); + create(coff_mod); + create(coff_mod); + create(coff_mod); + create(coff_mod); + create
(coff_mod); + create(coff_mod); + create(coff_mod); +} +} diff --git a/vendor/lief/api/python/src/COFF/init.hpp b/vendor/lief/api/python/src/COFF/init.hpp new file mode 100644 index 0000000..11a47ee --- /dev/null +++ b/vendor/lief/api/python/src/COFF/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_COFF_INIT_H +#define PY_LIEF_COFF_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::COFF::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/CMakeLists.txt b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/CMakeLists.txt new file mode 100644 index 0000000..3fa31ab --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/CMakeLists.txt @@ -0,0 +1,8 @@ +target_sources(pyLIEF PRIVATE + pyAuxiliarybfAndefSymbol.cpp + pyAuxiliaryCLRToken.cpp + pyAuxiliaryFile.cpp + pyAuxiliaryFunctionDefinition.cpp + pyAuxiliarySectionDefinition.cpp + pyAuxiliaryWeakExternal.cpp +) diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryCLRToken.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryCLRToken.cpp new file mode 100644 index 0000000..8a8f28a --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryCLRToken.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp" +#include "LIEF/COFF/Symbol.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliaryCLRToken", + R"doc( + Auxiliary symbol associated with the ``CLR_TOKEN`` storage class + )doc"_doc + ); + + aux + .def_prop_ro("aux_type", &AuxiliaryCLRToken::aux_type, + "``IMAGE_AUX_SYMBOL_TYPE`` which should be ``IMAGE_AUX_SYMBOL_TYPE_TOKEN_DEF`` (1)"_doc + ) + + .def_prop_ro("reserved", &AuxiliaryCLRToken::reserved, + "Reserved value (should be 0)"_doc + ) + + .def_prop_ro("symbol_idx", &AuxiliaryCLRToken::symbol_idx, + "Index in the symbol table"_doc + ) + + .def_prop_ro("symbol", nb::overload_cast<>(&AuxiliaryCLRToken::symbol), + "Symbol referenced by :attr:`~.symbol_idx` (if resolved)"_doc + ) + + .def_prop_ro("rgb_reserved", &AuxiliaryCLRToken::rgb_reserved, + "Reserved (padding) values. Should be 0"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFile.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFile.cpp new file mode 100644 index 0000000..0eefb24 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFile.cpp @@ -0,0 +1,44 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp" + +#include +#include + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliaryFile", + R"doc( + This auxiliary symbol represents a filename (auxiliary format 4) + + The :attr:`lief.Symbol.name` itself should start with ``.file``, and this + auxiliary record gives the name of a source-code file. + + Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-4-files + )doc"_doc + ); + + aux + .def_prop_ro("filename", nb::overload_cast<>(&AuxiliaryFile::filename, nb::const_), + "The associated filename"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFunctionDefinition.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFunctionDefinition.cpp new file mode 100644 index 0000000..b2fbb93 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryFunctionDefinition.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "AuxiliaryFunctionDefinition", + R"doc( + This auxiliary symbol marks the beginning of a function definition. + + Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-1-function-definitions + )doc"_doc + ) + .def_prop_ro("tag_index", + nb::overload_cast<>(&AuxiliaryFunctionDefinition::tag_index, nb::const_), + R"doc( + The symbol-table index of the corresponding ``.bf`` (begin function) + symbol record. + )doc"_doc + ) + + .def_prop_ro("total_size", + nb::overload_cast<>(&AuxiliaryFunctionDefinition::total_size, nb::const_), + R"doc( + The size of the executable code for the function itself. + + If the function is in its own section, the ``SizeOfRawData`` in the section + header is greater or equal to this field, depending on alignment considerations + )doc"_doc + ) + + .def_prop_ro("ptr_to_line_number", + nb::overload_cast<>(&AuxiliaryFunctionDefinition::ptr_to_line_number, nb::const_), + R"doc( + The file offset of the first COFF line-number entry for the function, + or zero if none exists (deprecated) + )doc"_doc + ) + + .def_prop_ro("ptr_to_next_func", + nb::overload_cast<>(&AuxiliaryFunctionDefinition::ptr_to_next_func, nb::const_), + R"doc( + The symbol-table index of the record for the next function. If the function + is the last in the symbol table, this field is set to zero + )doc"_doc + ) + + .def_prop_ro("padding", + nb::overload_cast<>(&AuxiliaryFunctionDefinition::padding, nb::const_), + "Padding value (should be 0)"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarySectionDefinition.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarySectionDefinition.cpp new file mode 100644 index 0000000..c4656c7 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarySectionDefinition.cpp @@ -0,0 +1,142 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliarySectionDefinition", + R"doc( + This auxiliary symbol exposes information about the associated section. + + It **duplicates** some information that are provided in the section header + )doc"_doc + ); + + using COMDAT_SELECTION = AuxiliarySectionDefinition::COMDAT_SELECTION; + nb::enum_(aux, "COMDAT_SELECTION", + R"doc( + Values for the AuxiliarySectionDefinition::selection attribute + + See: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#comdat-sections-object-only + )doc"_doc + ) + .value("NONE", COMDAT_SELECTION::NONE) + .value("NODUPLICATES", COMDAT_SELECTION::NODUPLICATES, + R"doc( + If this symbol is already defined, the linker issues a + ``multiply defined symbol`` error. + )doc"_doc + ) + + .value("ANY", COMDAT_SELECTION::ANY, + R"doc( + Any section that defines the same COMDAT symbol can be linked; the rest + are removed. + )doc"_doc + ) + + .value("SAME_SIZE", COMDAT_SELECTION::SAME_SIZE, + R"doc( + The linker chooses an arbitrary section among the definitions for this + symbol. If all definitions are not the same size, a ``multiply defined symbol`` + error is issued. + )doc"_doc + ) + + .value("EXACT_MATCH", COMDAT_SELECTION::EXACT_MATCH, + R"doc( + The linker chooses an arbitrary section among the definitions for this + symbol. If all definitions do not match exactly, a + ``multiply defined symbol`` error is issued. + )doc"_doc + ) + + .value("ASSOCIATIVE", COMDAT_SELECTION::ASSOCIATIVE, + R"doc( + The section is linked if a certain other COMDAT section is linked. + This other section is indicated by the Number field of the auxiliary + symbol record for the section definition. This setting is useful for + definitions that have components in multiple sections + (for example, code in one and data in another), but where all must be + linked or discarded as a set. The other section this section is + associated with must be a COMDAT section, which can be another + associative COMDAT section. An associative COMDAT section's section + association chain can't form a loop. The section association chain must + eventually come to a COMDAT section that doesn't have + :attr:`~.COMDAT_SELECTION.ASSOCIATIVE` set. + )doc"_doc + ) + + .value("LARGEST", COMDAT_SELECTION::LARGEST, + R"doc( + The linker chooses the largest definition from among all of the definitions + for this symbol. If multiple definitions have this size, the choice + between them is arbitrary. + )doc"_doc + ) + ; + + aux + .def_prop_ro("length", nb::overload_cast<>(&AuxiliarySectionDefinition::length, nb::const_), + R"doc( + The size of section data. The same as ``SizeOfRawData`` in the section header. + )doc"_doc + ) + + .def_prop_ro("nb_relocs", nb::overload_cast<>(&AuxiliarySectionDefinition::nb_relocs, nb::const_), + R"doc( + The number of relocation entries for the section. + )doc"_doc + ) + + .def_prop_ro("nb_line_numbers", nb::overload_cast<>(&AuxiliarySectionDefinition::nb_line_numbers, nb::const_), + R"doc( + The number of line-number entries for the section. + )doc"_doc + ) + + .def_prop_ro("checksum", nb::overload_cast<>(&AuxiliarySectionDefinition::checksum, nb::const_), + R"doc( + The checksum for communal data. It is applicable if the + ``IMAGE_SCN_LNK_COMDAT`` flag is set in the section header. + )doc"_doc + ) + + .def_prop_ro("section_idx", nb::overload_cast<>(&AuxiliarySectionDefinition::section_idx, nb::const_), + R"doc( + One-based index into the section table for the associated section. + This is used when the COMDAT selection setting is 5. + )doc"_doc + ) + + .def_prop_ro("selection", nb::overload_cast<>(&AuxiliarySectionDefinition::selection, nb::const_), + R"doc( + The COMDAT selection number. This is applicable if the section is a COMDAT + section. + )doc"_doc + ) + + .def_prop_ro("reserved", nb::overload_cast<>(&AuxiliarySectionDefinition::reserved, nb::const_), + "Reserved value (should be 0)"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryWeakExternal.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryWeakExternal.cpp new file mode 100644 index 0000000..308e758 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliaryWeakExternal.cpp @@ -0,0 +1,63 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "nanobind/extra/stl/lief_span.h" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliaryWeakExternal", + R"doc( + "Weak externals" are a mechanism for object files that allows flexibility at + link time. A module can contain an unresolved external symbol (``sym1``), but + it can also include an auxiliary record that indicates that if ``sym1`` is not + present at link time, another external symbol (``sym2``) is used to resolve + references instead. + + If a definition of ``sym1`` is linked, then an external reference to the + symbol is resolved normally. If a definition of ``sym1`` is not linked, then all + references to the weak external for ``sym1`` refer to ``sym2`` instead. The external + symbol, ``sym2``, must always be linked; typically, it is defined in the module + that contains the weak reference to ``sym1``. + + Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-3-weak-externals + )doc"_doc + ); + + nb::enum_(aux, "CHARACTERISTICS") + .value("SEARCH_NOLIBRARY", AuxiliaryWeakExternal::CHARACTERISTICS::SEARCH_NOLIBRARY) + .value("SEARCH_LIBRARY", AuxiliaryWeakExternal::CHARACTERISTICS::SEARCH_LIBRARY) + .value("SEARCH_ALIAS", AuxiliaryWeakExternal::CHARACTERISTICS::SEARCH_ALIAS) + .value("ANTI_DEPENDENCY", AuxiliaryWeakExternal::CHARACTERISTICS::ANTI_DEPENDENCY); + + aux + .def_prop_ro("sym_idx", nb::overload_cast<>(&AuxiliaryWeakExternal::sym_idx, nb::const_), + R"doc( + The symbol-table index of sym2, the symbol to be linked if ``sym1`` is not + found. + )doc"_doc + ) + + .def_prop_ro("characteristics", nb::overload_cast<>(&AuxiliaryWeakExternal::characteristics, nb::const_)) + .def_prop_ro("padding", nb::overload_cast<>(&AuxiliaryWeakExternal::padding, nb::const_)) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarybfAndefSymbol.cpp b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarybfAndefSymbol.cpp new file mode 100644 index 0000000..efd96dc --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/AuxiliarySymbols/pyAuxiliarybfAndefSymbol.cpp @@ -0,0 +1,27 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliarybfAndefSymbol"); +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/CMakeLists.txt b/vendor/lief/api/python/src/COFF/objects/CMakeLists.txt new file mode 100644 index 0000000..92fbf52 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/CMakeLists.txt @@ -0,0 +1,15 @@ +target_sources(pyLIEF PRIVATE + pyAuxiliarySymbol.cpp + pyBigObjHeader.cpp + pyBinary.cpp + pyHeader.cpp + pyParser.cpp + pyParserConfig.cpp + pyRegularHeader.cpp + pyRelocation.cpp + pySection.cpp + pyString.cpp + pySymbol.cpp +) + +add_subdirectory(AuxiliarySymbols) diff --git a/vendor/lief/api/python/src/COFF/objects/pyAuxiliarySymbol.cpp b/vendor/lief/api/python/src/COFF/objects/pyAuxiliarySymbol.cpp new file mode 100644 index 0000000..97e8250 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyAuxiliarySymbol.cpp @@ -0,0 +1,78 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyLIEF.hpp" +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/AuxiliarySymbol.hpp" + +#include +#include + +#include "enums_wrapper.hpp" + +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/stl/unique_ptr.h" + +namespace LIEF::COFF { +class AuxiliaryCLRToken; +class AuxiliaryFunctionDefinition; +class AuxiliaryWeakExternal; +class AuxiliarybfAndefSymbol; +class AuxiliarySectionDefinition; +class AuxiliaryFile; +} + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ aux(m, "AuxiliarySymbol", + R"doc( + Class that represents an auxiliary symbol. + + An auxiliary symbol has the same size as a regular :class:`lief.PE.Symbol` + (18 bytes) but its content depends on the parent symbol. + )doc"_doc + ); + + enum_(aux, "TYPE", + "Type discriminator for the subclasses"_doc + ) + .value("UNKNOWN", AuxiliarySymbol::TYPE::UNKNOWN) + .value("CLR_TOKEN", AuxiliarySymbol::TYPE::CLR_TOKEN) + .value("FUNC_DEF", AuxiliarySymbol::TYPE::FUNC_DEF) + .value("BF_AND_EF", AuxiliarySymbol::TYPE::BF_AND_EF) + .value("WEAK_EXTERNAL", AuxiliarySymbol::TYPE::WEAK_EXTERNAL) + .value("FILE", AuxiliarySymbol::TYPE::FILE) + .value("SEC_DEF", AuxiliarySymbol::TYPE::SEC_DEF); + + aux + .def_prop_ro("type", &AuxiliarySymbol::type) + .def_prop_ro("payload", nb::overload_cast<>(&AuxiliarySymbol::payload), + "For unknown type **only**, return the raw representation of this symbol"_doc) + + LIEF_DEFAULT_STR(AuxiliarySymbol) + LIEF_CLONABLE(AuxiliarySymbol); + + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyBigObjHeader.cpp b/vendor/lief/api/python/src/COFF/objects/pyBigObjHeader.cpp new file mode 100644 index 0000000..208add8 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyBigObjHeader.cpp @@ -0,0 +1,74 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" +#include "LIEF/COFF/BigObjHeader.hpp" + +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ hdr(m, "BigObjHeader", + R"doc( + This class represents the header for a COFF object compiled + with ``/bigobj`` support (i.e. the number of sections can exceed 65536). + + The raw definition of the bigobj header is located in ``winnt.h`` and named + ``ANON_OBJECT_HEADER_BIGOBJ`` + )doc"_doc); + + hdr + .def_prop_rw("version", + nb::overload_cast<>(&BigObjHeader::version, nb::const_), + nb::overload_cast(&BigObjHeader::version), + "The version of this header which must be >= 2"_doc + ) + + .def_prop_ro("uuid", + nb::overload_cast<>(&BigObjHeader::uuid, nb::const_), + R"doc( + Originally named ``ClassID``, this uuid should match: + ``{D1BAA1C7-BAEE-4ba9-AF20-FAF66AA4DCB8}``. + )doc"_doc + ) + + .def_prop_rw("sizeof_data", + nb::overload_cast<>(&BigObjHeader::sizeof_data, nb::const_), + nb::overload_cast(&BigObjHeader::sizeof_data), + "Size of data that follows the header"_doc + ) + + .def_prop_rw("flags", + nb::overload_cast<>(&BigObjHeader::flags, nb::const_), + nb::overload_cast(&BigObjHeader::flags), + "1 means that it contains metadata"_doc + ) + + .def_prop_rw("metadata_size", + nb::overload_cast<>(&BigObjHeader::metadata_size, nb::const_), + nb::overload_cast(&BigObjHeader::metadata_size), + "Size of CLR metadata"_doc + ) + + .def_prop_rw("metadata_offset", + nb::overload_cast<>(&BigObjHeader::metadata_offset, nb::const_), + nb::overload_cast(&BigObjHeader::metadata_offset), + "Offset of CLR metadata"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyBinary.cpp b/vendor/lief/api/python/src/COFF/objects/pyBinary.cpp new file mode 100644 index 0000000..c373890 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyBinary.cpp @@ -0,0 +1,200 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +#include "COFF/pyCOFF.hpp" +#include "LIEF/COFF/Binary.hpp" +#include "LIEF/COFF/Relocation.hpp" +#include "LIEF/COFF/Symbol.hpp" +#include "LIEF/COFF/Section.hpp" +#include "LIEF/COFF/String.hpp" + +#include "LIEF/asm/Engine.hpp" +#include "LIEF/asm/Instruction.hpp" + +#include "pyOwningIterator.hpp" + +#include + +#include + +#include "pyIterator.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ bin(m, "Binary", + "Class that represents a COFF Binary"_doc); + + struct it_symbols : public Binary::it_symbols { + using Binary::it_symbols::it_symbols; + }; + + struct it_strings_table : public Binary::it_strings_table { + using Binary::it_strings_table::it_strings_table; + }; + + init_ref_iterator(bin, "it_section"); + init_ref_iterator(bin, "it_relocations"); + init_ref_iterator(bin, "it_symbols"); + init_ref_iterator(bin, "it_strings_table"); + init_ref_iterator(bin, "it_functions"); + + bin + .def_prop_ro("header", nb::overload_cast<>(&Binary::header), + "The COFF header"_doc + ) + .def_prop_ro("sections", + nb::overload_cast<>(&Binary::sections), + "Iterator over the different sections located in this COFF binary"_doc, + nb::keep_alive<0, 1>() + ) + + .def("get_section", + nb::overload_cast(&Binary::get_section), + R"doc( + Return the :class:`~lief.COFF.Section` matching the given name. + + Section names that do not fit in the 8 bytes allocated by the COFF format + are stored in the COFF string table while the section itself only holds a + ``/`` placeholder. This function transparently resolves both + forms, so a long name can be looked up with its **regular** value: + + .. code-block:: python + + sec = binary.get_section(".debug_rnglists") + sec.name # '/18' + sec.coff_string.string # '.debug_rnglists' + )doc"_doc, "name"_a, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Binary::relocations), + "Iterator over **all** the relocations used by this COFF binary"_doc, + nb::keep_alive<0, 1>() + ) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Binary::symbols), + "Iterator over the COFF's symbols"_doc, + nb::keep_alive<0, 1>() + ) + + .def_prop_ro("functions", + nb::overload_cast<>(&Binary::functions), + "Iterator over the functions implemented in this COFF", + nb::keep_alive<0, 1>()) + + .def_prop_ro("string_table", + nb::overload_cast<>(&Binary::string_table), + "Iterator over the COFF's strings"_doc, + nb::keep_alive<0, 1>() + ) + + .def("find_string", nb::overload_cast(&Binary::find_string), + R"doc( + Try to find the COFF string at the given offset in the COFF string table. + + .. warning:: + + This offset must include the first 4 bytes holding the size of + the table. Hence, the first string starts a the offset 4. + )doc"_doc, "offset"_a, + nb::rv_policy::reference_internal) + + .def("find_function", + nb::overload_cast(&Binary::find_function), + "Try to find the function (symbol) with the given name"_doc, + "name"_a, nb::rv_policy::reference_internal + ) + + .def("find_demangled_function", + nb::overload_cast(&Binary::find_demangled_function), + "Try to find the function (symbol) with the given **demangled** name"_doc, + "name"_a, nb::rv_policy::reference_internal + ) + + + .def("disassemble", [] (const Binary& self, const Symbol& function) { + auto insts = LIEF::py::owning_range(self.disassemble(function)); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "function"_a, nb::keep_alive<0, 1>(), + R"doc( + Disassemble code for the given symbol + + .. code-block:: python + + func = binary.find_demangled_function("int __cdecl my_function(int, int)"); + insts = binary.disassemble("main"); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc) + + .def("disassemble", [] (const Binary& self, const std::string& function) { + auto insts = LIEF::py::owning_range(self.disassemble(function)); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "function_name"_a, nb::keep_alive<0, 1>(), + R"doc( + Disassemble code for the given symbol name + + .. code-block:: python + + insts = binary.disassemble("main"); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + + .def("disassemble_from_bytes", + [] (const Binary& self, const nb::bytes& buffer, uint64_t address) { + auto insts = LIEF::py::owning_range(self.disassemble( + reinterpret_cast(buffer.c_str()), + buffer.size(), address + )); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "buffer"_a, "address"_a = 0, nb::keep_alive<0, 1>(), nb::keep_alive<0, 2>(), + R"doc( + Disassemble code from the provided bytes + + .. code-block:: python + + raw = bytes(binary.get_section(".text").content) + insts = binary.disassemble_from_bytes(raw); + for inst in insts: + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc + ) + LIEF_DEFAULT_STR(Binary); + +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyHeader.cpp b/vendor/lief/api/python/src/COFF/objects/pyHeader.cpp new file mode 100644 index 0000000..72dcfae --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyHeader.cpp @@ -0,0 +1,91 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include + +#include "LIEF/COFF/Header.hpp" +#include "enums_wrapper.hpp" + +#include + +namespace LIEF::COFF { +class BigObjHeader; +class RegularHeader; +namespace py { + +template<> +void create
(nb::module_& m) { + using namespace LIEF::py; + + nb::class_
hdr(m, "Header", + R"doc( + Class that represents the COFF header. It is subclassed by + :class:`~.RegularHeader` and :class:`~.BigObjHeader` for normal vs + ``/bigobj`` files + )doc"_doc); + + nb::enum_(hdr, "KIND") + .value("UNKNOWN", Header::KIND::UNKNOWN) + .value("REGULAR", Header::KIND::REGULAR) + .value("BIGOBJ", Header::KIND::BIGOBJ); + + hdr + .def_prop_ro("kind", &Header::kind, + R"doc( + The type of this header: whether it is regular or using the ``/bigobj`` + format + )doc"_doc + ) + + .def_prop_rw("machine", + nb::overload_cast<>(&Header::machine, nb::const_), + nb::overload_cast(&Header::machine), + "The machine type targeted by this COFF"_doc + ) + + .def_prop_rw("nb_sections", + nb::overload_cast<>(&Header::nb_sections, nb::const_), + nb::overload_cast(&Header::nb_sections), + "The number of sections"_doc + ) + + .def_prop_rw("pointerto_symbol_table", + nb::overload_cast<>(&Header::pointerto_symbol_table, nb::const_), + nb::overload_cast(&Header::pointerto_symbol_table), + "Offset of the symbols table"_doc + ) + + .def_prop_rw("nb_symbols", + nb::overload_cast<>(&Header::nb_symbols, nb::const_), + nb::overload_cast(&Header::nb_symbols), + "Number of symbols (including auxiliary symbols)"_doc + ) + + .def_prop_rw("timedatestamp", + nb::overload_cast<>(&Header::timedatestamp, nb::const_), + nb::overload_cast(&Header::timedatestamp), + "Timestamp when the COFF has been generated"_doc + ) + + LIEF_DEFAULT_STR(Header) + LIEF_CLONABLE(Header); + + create(m); + create(m); +} + +} +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyParser.cpp b/vendor/lief/api/python/src/COFF/objects/pyParser.cpp new file mode 100644 index 0000000..4e80575 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyParser.cpp @@ -0,0 +1,47 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include +#include +#include +#include + +#include "typing/InputParser.hpp" + +#include "LIEF/COFF/Parser.hpp" +#include "LIEF/COFF/Binary.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse", + [] (typing::InputParser obj, const ParserConfig& config) -> std::unique_ptr { + return Parser::parse(obj.into_stream(), config); + }, + R"delim( + Parse the COFF binary specified in the first parameter and return a :class:`lief.COFF.Binary` object + + The second argument is an optional configuration + that can be used to define which part(s) of the COFF should be parsed or skipped. + )delim"_doc, + "obj"_a, "config"_a = ParserConfig::default_conf(), + nb::rv_policy::take_ownership); + +} +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyParserConfig.cpp b/vendor/lief/api/python/src/COFF/objects/pyParserConfig.cpp new file mode 100644 index 0000000..b86c4c6 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyParserConfig.cpp @@ -0,0 +1,36 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" +#include "LIEF/COFF/ParserConfig.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ParserConfig", + R"delim( + )delim"_doc) + .def(nb::init<>()) + .def_prop_ro_static("default_conf", + [] (const nb::object& /* self */) { return ParserConfig::default_conf(); }, + "Default configuration"_doc) + + .def_prop_ro_static("all", + [] (const nb::object& /* self */) { return ParserConfig::all(); }, + "All parsing options enabled"_doc); + +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyRegularHeader.cpp b/vendor/lief/api/python/src/COFF/objects/pyRegularHeader.cpp new file mode 100644 index 0000000..990a6a7 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyRegularHeader.cpp @@ -0,0 +1,42 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" +#include "LIEF/COFF/RegularHeader.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "RegularHeader", + R"doc( + This class represents the COFF header for non-bigobj + )doc"_doc) + + .def_prop_rw("sizeof_optionalheader", + nb::overload_cast<>(&RegularHeader::sizeof_optionalheader, nb::const_), + nb::overload_cast(&RegularHeader::sizeof_optionalheader), + "The size of the optional header that follows this header (should be 0)"_doc + ) + + .def_prop_rw("characteristics", + nb::overload_cast<>(&RegularHeader::characteristics, nb::const_), + nb::overload_cast(&RegularHeader::characteristics), + "Characteristics"_doc + ) + ; + +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyRelocation.cpp b/vendor/lief/api/python/src/COFF/objects/pyRelocation.cpp new file mode 100644 index 0000000..946d998 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyRelocation.cpp @@ -0,0 +1,142 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/Relocation.hpp" +#include "LIEF/COFF/Symbol.hpp" +#include "LIEF/COFF/Section.hpp" + +#include "enums_wrapper.hpp" + +#include +#include +#include +#include + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ relocation(m, "Relocation"); + + #define ENTRY(X) .value(to_string(Relocation::TYPE::X), Relocation::TYPE::X) + enum_(relocation, "TYPE") + ENTRY(UNKNOWN) + + ENTRY(AMD64_ABSOLUTE) + ENTRY(AMD64_ADDR32) + ENTRY(AMD64_ADDR32NB) + ENTRY(AMD64_ADDR64) + ENTRY(AMD64_PAIR) + ENTRY(AMD64_REL32) + ENTRY(AMD64_REL32_1) + ENTRY(AMD64_REL32_2) + ENTRY(AMD64_REL32_3) + ENTRY(AMD64_REL32_4) + ENTRY(AMD64_REL32_5) + ENTRY(AMD64_SECREL) + ENTRY(AMD64_SECREL7) + ENTRY(AMD64_SECTION) + ENTRY(AMD64_SREL32) + ENTRY(AMD64_SSPAN32) + ENTRY(AMD64_TOKEN) + + ENTRY(ARM64_ABSOLUTE) + ENTRY(ARM64_ADDR32) + ENTRY(ARM64_ADDR32NB) + ENTRY(ARM64_ADDR64) + ENTRY(ARM64_BRANCH14) + ENTRY(ARM64_BRANCH19) + ENTRY(ARM64_BRANCH26) + ENTRY(ARM64_PAGEBASE_REL21) + ENTRY(ARM64_PAGEOFFSET_12A) + ENTRY(ARM64_PAGEOFFSET_12L) + ENTRY(ARM64_REL21) + ENTRY(ARM64_REL32) + ENTRY(ARM64_SECREL) + ENTRY(ARM64_SECREL_HIGH12A) + ENTRY(ARM64_SECREL_LOW12A) + ENTRY(ARM64_SECREL_LOW12L) + ENTRY(ARM64_SECTION) + ENTRY(ARM64_TOKEN) + + ENTRY(ARM_ABSOLUTE) + ENTRY(ARM_ADDR32) + ENTRY(ARM_ADDR32NB) + ENTRY(ARM_BLX11) + ENTRY(ARM_BLX23T) + ENTRY(ARM_BLX24) + ENTRY(ARM_BRANCH11) + ENTRY(ARM_BRANCH20T) + ENTRY(ARM_BRANCH24) + ENTRY(ARM_BRANCH24T) + ENTRY(ARM_MOV32A) + ENTRY(ARM_MOV32T) + ENTRY(ARM_PAIR) + ENTRY(ARM_REL32) + ENTRY(ARM_SECREL) + ENTRY(ARM_SECTION) + ENTRY(ARM_TOKEN) + + ENTRY(I386_ABSOLUTE) + ENTRY(I386_DIR16) + ENTRY(I386_DIR32) + ENTRY(I386_DIR32NB) + ENTRY(I386_REL16) + ENTRY(I386_REL32) + ENTRY(I386_SECREL) + ENTRY(I386_SECREL7) + ENTRY(I386_SECTION) + ENTRY(I386_SEG12) + ENTRY(I386_TOKEN) + + ENTRY(MIPS_ABSOLUTE) + ENTRY(MIPS_GPREL) + ENTRY(MIPS_JMPADDR) + ENTRY(MIPS_JMPADDR16) + ENTRY(MIPS_LITERAL) + ENTRY(MIPS_PAIR) + ENTRY(MIPS_REFHALF) + ENTRY(MIPS_REFHI) + ENTRY(MIPS_REFLO) + ENTRY(MIPS_REFWORD) + ENTRY(MIPS_REFWORDNB) + ENTRY(MIPS_SECREL) + ENTRY(MIPS_SECRELHI) + ENTRY(MIPS_SECRELLO) + ENTRY(MIPS_SECTION) + ; + #undef ENTRY + + relocation + .def_prop_ro("symbol_idx", &Relocation::symbol_idx, + "Symbol index associated with this relocation"_doc + ) + .def_prop_ro("symbol", nb::overload_cast<>(&Relocation::symbol), + "Symbol associated with the relocation (if any)"_doc + ) + .def_prop_ro("type", &Relocation::type, + "Type of the relocation"_doc + ) + .def_prop_ro("section", nb::overload_cast<>(&Relocation::section), + "Section in which the relocation takes place"_doc + ) + LIEF_DEFAULT_STR(Relocation); +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pySection.cpp b/vendor/lief/api/python/src/COFF/objects/pySection.cpp new file mode 100644 index 0000000..4dd09e1 --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pySection.cpp @@ -0,0 +1,171 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/Section.hpp" +#include "LIEF/COFF/Relocation.hpp" +#include "LIEF/COFF/Symbol.hpp" +#include "LIEF/COFF/String.hpp" + +#include +#include +#include +#include +#include + +#include "nanobind/utils.hpp" + +#include "pyIterator.hpp" + +namespace LIEF::COFF::py { + +template<> +void create
(nb::module_& m) { + using namespace LIEF::py; + nb::class_ sec(m, "Section", + R"doc( + This class represents a COFF section + )doc"_doc); + + init_ref_iterator(sec, "it_relocations"); + init_ref_iterator(sec, "it_symbols"); + + nb::class_(sec, "ComdatInfo", + R"doc( + This class wraps comdat information which is composed of the symbol associated + with the comdat section and its selection flag + )doc"_doc + ) + .def_ro("symbol", &Section::ComdatInfo::symbol) + .def_ro("kind", &Section::ComdatInfo::kind) + ; + + sec + .def_prop_rw("virtual_size", + nb::overload_cast<>(&Section::virtual_size, nb::const_), + nb::overload_cast(&Section::virtual_size), + "Virtual size of the section (should be 0)"_doc) + + .def_prop_rw("sizeof_raw_data", + nb::overload_cast<>(&Section::sizeof_raw_data, nb::const_), + nb::overload_cast(&Section::sizeof_raw_data), + "Return the size of the data in the section."_doc) + + .def_prop_rw("pointerto_raw_data", + nb::overload_cast<>(&Section::pointerto_raw_data, nb::const_), + nb::overload_cast(&Section::pointerto_raw_data), + "Offset to the section's content"_doc) + + .def_prop_rw("pointerto_relocation", + nb::overload_cast<>(&Section::pointerto_relocation, nb::const_), + nb::overload_cast(&Section::pointerto_relocation), + "Offset to the relocation table"_doc) + + .def_prop_rw("pointerto_line_numbers", + nb::overload_cast<>(&Section::pointerto_line_numbers, nb::const_), + nb::overload_cast(&Section::pointerto_line_numbers), + R"delim( + The file pointer to the beginning of line-number entries for the section. + This is set to zero if there are no COFF line numbers. This value should + be zero for an image because COFF debugging information is deprecated + and modern debug information relies on the PDB files. + )delim"_doc) + + .def_prop_rw("numberof_relocations", + nb::overload_cast<>(&Section::numberof_relocations, nb::const_), + nb::overload_cast(&Section::numberof_relocations), + R"delim( + Number of relocations. + + .. warning:: + + If the number of relocations is greater than 0xFFFF (maximum value for + 16-bits integer), then the number of relocations is stored in the + virtual address attribute. + )delim"_doc) + + .def_prop_rw("numberof_line_numbers", + nb::overload_cast<>(&Section::numberof_line_numbers, nb::const_), + nb::overload_cast(&Section::numberof_line_numbers), + R"delim( + The number of line-number entries for the section. + This value should be zero for an image because COFF debugging information is + deprecated. + + See: :attr:`~lief.COFF.Section.pointerto_line_numbers` + )delim"_doc) + + .def_prop_rw("characteristics", + nb::overload_cast<>(&Section::characteristics, nb::const_), + nb::overload_cast(&Section::characteristics), + "The characteristics that describe the purpose of the section"_doc) + + .def_prop_ro("characteristics_lists", + &Section::characteristics_list, + "characteristics as a ``list``"_doc) + + .def("has_characteristic", &Section::has_characteristic, + "``True`` if the section has the given characteristic"_doc, + "characteristic"_a) + + .def_prop_ro("is_discardable", &Section::is_discardable, + R"doc( + True if the section can be discarded as needed. + + This is typically the case for debug-related sections. + )doc"_doc + ) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Section::relocations), + "Iterator over the relocations performed in this section"_doc, + nb::keep_alive<0, 1>() + ) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Section::symbols), + "Iterator over the symbols associated with this section"_doc, + nb::keep_alive<0, 1>() + ) + + .def_prop_ro("has_extended_relocations", + &Section::has_extended_relocations, + R"doc( + Whether there is a large number of relocations whose number need to be + stored in the virtual address attribute + )doc"_doc + ) + + .def_prop_ro("comdat_info", &Section::comdat_info, + R"doc( + Return comdat information (only if the section has the + :attr:`lief.PE.Section.CHARACTERISTICS.LNK_COMDAT` characteristic) + )doc"_doc + ) + + .def_prop_ro("coff_string", nb::overload_cast<>(&Section::coff_string), + R"doc( + Return the COFF string associated with the section's name (or None) + + This coff string is usually present for long section names whose length + does not fit in the 8 bytes allocated by the COFF format. + )doc"_doc + ) + + LIEF_DEFAULT_STR(Section); +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pyString.cpp b/vendor/lief/api/python/src/COFF/objects/pyString.cpp new file mode 100644 index 0000000..80eae3b --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pyString.cpp @@ -0,0 +1,56 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/String.hpp" + +#include +#include +#include +#include + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "String", + R"doc( + This class represents a string located in the COFF string table. + + Some of these strings can be used for section's name where its length is greater than 8 + bytes. See: :attr:`~.Section.coff_string`. + + Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-string-table + )doc"_doc + ) + + .def_prop_rw("string", nb::overload_cast<>(&String::str, nb::const_), + nb::overload_cast(&String::str), + nb::rv_policy::reference_internal, + "The actual string"_doc) + + .def_prop_rw("offset", nb::overload_cast<>(&String::offset, nb::const_), + nb::overload_cast(&String::offset), + nb::rv_policy::reference_internal, + R"doc( + The offset of this string the in the COFF string table. + This offset includes the first 4-bytes that holds the table size + )doc"_doc) + + LIEF_DEFAULT_STR(String); +} + +} diff --git a/vendor/lief/api/python/src/COFF/objects/pySymbol.cpp b/vendor/lief/api/python/src/COFF/objects/pySymbol.cpp new file mode 100644 index 0000000..f42f3af --- /dev/null +++ b/vendor/lief/api/python/src/COFF/objects/pySymbol.cpp @@ -0,0 +1,186 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/Symbol.hpp" +#include "LIEF/COFF/String.hpp" +#include "LIEF/COFF/Section.hpp" +#include "LIEF/COFF/AuxiliarySymbol.hpp" + +#include +#include +#include +#include +#include + +#include "enums_wrapper.hpp" +#include "pyIterator.hpp" + +namespace LIEF::COFF::py { + +template<> +void create(nb::module_& m) { + nb::class_ sym(m, "Symbol", + R"doc( + Class that represents a COFF symbol. + + .. warning:: + + The :attr:`lief.Symbol.value` should be interpreted in perspective of + the :attr:`~.Symbol.storage_class` + + Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-symbol-table + )doc"_doc + ); + + LIEF::py::init_ref_iterator(sym, "it_auxiliary_symbols_t"); + + #define ENTRY(X) .value(to_string(Symbol::STORAGE_CLASS::X), Symbol::STORAGE_CLASS::X) + enum_(sym, "STORAGE_CLASS", + "Reference: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#storage-class"_doc + ) + ENTRY(END_OF_FUNCTION) + ENTRY(NONE) + ENTRY(AUTOMATIC) + ENTRY(EXTERNAL) + ENTRY(STATIC) + ENTRY(REGISTER) + ENTRY(EXTERNAL_DEF) + ENTRY(LABEL) + ENTRY(UNDEFINED_LABEL) + ENTRY(MEMBER_OF_STRUCT) + ENTRY(ARGUMENT) + ENTRY(STRUCT_TAG) + ENTRY(MEMBER_OF_UNION) + ENTRY(UNION_TAG) + ENTRY(TYPE_DEFINITION) + ENTRY(UNDEFINED_STATIC) + ENTRY(ENUM_TAG) + ENTRY(MEMBER_OF_ENUM) + ENTRY(REGISTER_PARAM) + ENTRY(BIT_FIELD) + ENTRY(BLOCK) + ENTRY(FUNCTION) + ENTRY(END_OF_STRUCT) + ENTRY(FILE) + ENTRY(SECTION) + ENTRY(WEAK_EXTERNAL) + ENTRY(CLR_TOKEN) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Symbol::BASE_TYPE::X), Symbol::BASE_TYPE::X) + enum_(sym, "BASE_TYPE") + ENTRY(TY_NULL) + ENTRY(TY_VOID) + ENTRY(TY_CHAR) + ENTRY(TY_SHORT) + ENTRY(TY_INT) + ENTRY(TY_LONG) + ENTRY(TY_FLOAT) + ENTRY(TY_DOUBLE) + ENTRY(TY_STRUCT) + ENTRY(TY_UNION) + ENTRY(TY_ENUM) + ENTRY(TY_MOE) + ENTRY(TY_BYTE) + ENTRY(TY_WORD) + ENTRY(TY_UINT) + ENTRY(TY_DWORD) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Symbol::COMPLEX_TYPE::X), Symbol::COMPLEX_TYPE::X) + enum_(sym, "COMPLEX_TYPE") + ENTRY(TY_NULL) + ENTRY(TY_POINTER) + ENTRY(TY_FUNCTION) + ENTRY(TY_ARRAY) + ; + #undef ENTRY + + sym + .def_prop_rw("type", nb::overload_cast<>(&Symbol::type, nb::const_), + nb::overload_cast(&Symbol::type), + nb::rv_policy::reference, + R"doc( + The symbol type. The first byte represents the base type (see: :attr:`~.base_type`) + while the upper byte represents the complex type, if any (see: :attr:`~.complex_type`). + )doc"_doc + ) + + .def_prop_ro("base_type", nb::overload_cast<>(&Symbol::base_type, nb::const_), + "The simple (base) data type"_doc) + + .def_prop_ro("complex_type", nb::overload_cast<>(&Symbol::complex_type, nb::const_), + "The complex type (if any)"_doc) + + .def_prop_ro("storage_class", nb::overload_cast<>(&Symbol::storage_class, nb::const_), + R"doc( + Storage class of the symbol which indicates what kind of definition a + symbol represents. + )doc"_doc + ) + + .def_prop_rw("section_idx", nb::overload_cast<>(&Symbol::section_idx, nb::const_), + nb::overload_cast(&Symbol::section_idx), + nb::rv_policy::reference, + R"doc( + The signed integer that identifies the section, using a one-based index + into the section table. Some values have special meaning: + + * 0: The symbol record is not yet assigned a section. A value of zero + indicates that a reference to an external symbol is defined elsewhere. + A value of non-zero is a common symbol with a size that is specified + by the value. + * -1: The symbol has an absolute (non-relocatable) value and is not an + address. + * -2: The symbol provides general type or debugging information but does + not correspond to a section. Microsoft tools use this setting along + with ``.file`` records + )doc"_doc + ) + + .def_prop_ro("section", nb::overload_cast<>(&Symbol::section), + "Section associated with this symbol (if any)" + ) + + .def_prop_ro("is_external", nb::overload_cast<>(&Symbol::is_external, nb::const_)) + .def_prop_ro("is_absolute", nb::overload_cast<>(&Symbol::is_absolute, nb::const_)) + .def_prop_ro("is_weak_external", nb::overload_cast<>(&Symbol::is_weak_external, nb::const_)) + .def_prop_ro("is_undefined", nb::overload_cast<>(&Symbol::is_undefined, nb::const_)) + .def_prop_ro("is_function_line_info", nb::overload_cast<>(&Symbol::is_function_line_info, nb::const_)) + .def_prop_ro("is_file_record", nb::overload_cast<>(&Symbol::is_file_record, nb::const_)) + .def_prop_ro("is_function", nb::overload_cast<>(&Symbol::is_function, nb::const_)) + + .def_prop_ro("auxiliary_symbols", nb::overload_cast<>(&Symbol::auxiliary_symbols), + "Auxiliary symbols associated with this symbol."_doc) + + .def_prop_ro("coff_name", nb::overload_cast<>(&Symbol::coff_name), + "COFF string used to represents the (long) symbol name"_doc) + + .def_prop_ro("demangled_name", &Symbol::demangled_name, + R"doc( + Demangled representation of the symbol or an empty string if it can't + be demangled + )doc" + ) + + + LIEF_DEFAULT_STR(Symbol); +} + +} diff --git a/vendor/lief/api/python/src/COFF/pyCOFF.hpp b/vendor/lief/api/python/src/COFF/pyCOFF.hpp new file mode 100644 index 0000000..75fa88f --- /dev/null +++ b/vendor/lief/api/python/src/COFF/pyCOFF.hpp @@ -0,0 +1,26 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_COFF_H +#define PY_LIEF_COFF_H +#include "pyLIEF.hpp" + +namespace LIEF::COFF::py { +template +void create(nb::module_&); + +void init_utils(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/COFF/pyUtils.cpp b/vendor/lief/api/python/src/COFF/pyUtils.cpp new file mode 100644 index 0000000..cbd1c0c --- /dev/null +++ b/vendor/lief/api/python/src/COFF/pyUtils.cpp @@ -0,0 +1,33 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "COFF/pyCOFF.hpp" + +#include "LIEF/COFF/utils.hpp" + +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::COFF::py { + +void init_utils(nb::module_&) { + lief_mod->def("is_coff", + [] (nb::PathLike path) { return is_coff(path.to_string()); }, + "Check if the given file is a COFF"_doc, + "file"_a + ); +} +} diff --git a/vendor/lief/api/python/src/DEX/CMakeLists.txt b/vendor/lief/api/python/src/DEX/CMakeLists.txt new file mode 100644 index 0000000..7f916d8 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyEnums.cpp + pyUtils.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/DEX/init.cpp b/vendor/lief/api/python/src/DEX/init.cpp new file mode 100644 index 0000000..ae6c4a2 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/init.cpp @@ -0,0 +1,56 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "DEX/pyDEX.hpp" +#include "DEX/init.hpp" + +#include "LIEF/DEX/Parser.hpp" +#include "LIEF/DEX/File.hpp" +#include "LIEF/DEX/Header.hpp" +#include "LIEF/DEX/Class.hpp" +#include "LIEF/DEX/Method.hpp" +#include "LIEF/DEX/Field.hpp" +#include "LIEF/DEX/Prototype.hpp" +#include "LIEF/DEX/Type.hpp" +#include "LIEF/DEX/MapList.hpp" +#include "LIEF/DEX/MapItem.hpp" +#include "LIEF/DEX/CodeInfo.hpp" + +#define CREATE(X,Y) create(Y) + +namespace LIEF::DEX::py { +void init_objects(nb::module_& m) { + CREATE(Parser, m); + CREATE(File, m); + CREATE(Header, m); + CREATE(Class, m); + CREATE(Method, m); + CREATE(Field, m); + CREATE(Prototype, m); + CREATE(Type, m); + CREATE(MapList, m); + CREATE(MapItem, m); + CREATE(CodeInfo, m); +} + +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("DEX", "Python API for DEX format"); + + init_enums(mod); + init_objects(mod); + init_utils(mod); +} + +} diff --git a/vendor/lief/api/python/src/DEX/init.hpp b/vendor/lief/api/python/src/DEX/init.hpp new file mode 100644 index 0000000..94829f7 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/init.hpp @@ -0,0 +1,25 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_DEX_INIT_H +#define PY_LIEF_DEX_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::DEX::py { +void init(nb::module_& m); +void init_enums(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/DEX/objects/CMakeLists.txt b/vendor/lief/api/python/src/DEX/objects/CMakeLists.txt new file mode 100644 index 0000000..b400556 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/CMakeLists.txt @@ -0,0 +1,13 @@ +target_sources(pyLIEF PRIVATE + pyHeader.cpp + pyParser.cpp + pyFile.cpp + pyClass.cpp + pyField.cpp + pyMethod.cpp + pyCodeInfo.cpp + pyMapList.cpp + pyMapItem.cpp + pyType.cpp + pyPrototype.cpp +) diff --git a/vendor/lief/api/python/src/DEX/objects/pyClass.cpp b/vendor/lief/api/python/src/DEX/objects/pyClass.cpp new file mode 100644 index 0000000..f5ed894 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyClass.cpp @@ -0,0 +1,97 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "DEX/pyDEX.hpp" + +#include "LIEF/DEX/Class.hpp" +#include "LIEF/DEX/Field.hpp" +#include "LIEF/DEX/Method.hpp" + +#include "pyIterator.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cls(m, "Class", "DEX Class representation"_doc); + + init_ref_iterator(cls, "it_methods"); + init_ref_iterator(cls, "it_fields"); + + init_ref_iterator(cls, "it_named_methods"); + init_ref_iterator(cls, "it_named_fields"); + + cls + .def_prop_ro("fullname", &Class::fullname, + "Mangled class name (e.g. ``Lcom/example/android/MyActivity;``)"_doc) + + .def_prop_ro("pretty_name", &Class::pretty_name, + "Demangled class name (e.g. ``com.example.android.MyActivity``)"_doc) + + .def_prop_ro("name", &Class::name, + "Class name (e.g. ``MyActivity``)"_doc) + + .def_prop_ro("source_filename", &Class::source_filename, + "Original filename"_doc) + + .def_prop_ro("package_name", &Class::package_name, + "Package Name (e.g. ``com.example.android``)"_doc) + + .def_prop_ro("has_parent", &Class::has_parent, + "True if the current class extends another one"_doc) + + .def_prop_ro("parent", nb::overload_cast<>(&Class::parent), + "" RST_CLASS_REF(lief.DEX.Class) " parent class"_doc) + + .def_prop_ro("methods", nb::overload_cast<>(&Class::methods), + "Iterator over " RST_CLASS_REF(lief.DEX.Method) " implemented in this class"_doc) + + .def("get_method", nb::overload_cast(&Class::methods), + "Iterator over " RST_CLASS_REF(lief.DEX.Method) " (s) having the given name"_doc, + "name"_a) + + .def_prop_ro("fields", nb::overload_cast<>(&Class::fields), + "Iterator over " RST_CLASS_REF(lief.DEX.Field) " in this class"_doc) + + .def("get_field", nb::overload_cast(&Class::fields), + "Iterator over " RST_CLASS_REF(lief.DEX.Field) " (s) having the given name"_doc, + "name"_a) + + .def_prop_ro("access_flags", + nb::overload_cast<>(&Class::access_flags, nb::const_), + "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) ""_doc) + + .def_prop_ro("dex2dex_info", &Class::dex2dex_info, + "De-optimize information"_doc) + + .def_prop_ro("index", &Class::index, + "Original index in the DEX class pool"_doc) + + .def("has", nb::overload_cast(&Class::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present"_doc, + "flag"_a) + + LIEF_DEFAULT_STR(Class); +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyCodeInfo.cpp b/vendor/lief/api/python/src/DEX/objects/pyCodeInfo.cpp new file mode 100644 index 0000000..436c198 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyCodeInfo.cpp @@ -0,0 +1,36 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/CodeInfo.hpp" + +#include "DEX/pyDEX.hpp" + +#include +#include + +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "CodeInfo", "DEX CodeInfo representation"_doc) + .def_prop_ro("nb_registers", nb::overload_cast<>(&CodeInfo::nb_registers, nb::const_), + "Number of registers used by the method"_doc) + + LIEF_DEFAULT_STR(CodeInfo); +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyField.cpp b/vendor/lief/api/python/src/DEX/objects/pyField.cpp new file mode 100644 index 0000000..8c79130 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyField.cpp @@ -0,0 +1,49 @@ +#include "LIEF/DEX/Field.hpp" +#include "LIEF/DEX/Class.hpp" +#include "LIEF/DEX/Type.hpp" + +#include "DEX/pyDEX.hpp" + +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "Field", "DEX Field representation"_doc) + .def_prop_ro("name", + &Field::name, + "Field's name"_doc) + + .def_prop_ro("index", &Field::index, + "Original DEX file index of the field"_doc) + + .def_prop_ro("has_class", &Field::has_class, + "True if a class is associated with this field"_doc) + + .def_prop_ro("cls", nb::overload_cast<>(&Field::cls), + "" RST_CLASS_REF(lief.DEX.Class) " associated with this field"_doc) + + .def_prop_ro("is_static", &Field::is_static, + "True if the field is static"_doc) + + .def_prop_ro("type", nb::overload_cast<>(&Field::type), + "" RST_CLASS_REF(lief.DEX.Type) " of this field"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("access_flags", + nb::overload_cast<>(&Field::access_flags, nb::const_), + "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) ""_doc) + + .def("has", + nb::overload_cast(&Field::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present"_doc, + "flag"_a) + + LIEF_DEFAULT_STR(Field); +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyFile.cpp b/vendor/lief/api/python/src/DEX/objects/pyFile.cpp new file mode 100644 index 0000000..ce044db --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyFile.cpp @@ -0,0 +1,123 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/File.hpp" +#include "LIEF/DEX/Class.hpp" +#include "LIEF/DEX/Method.hpp" +#include "LIEF/DEX/Type.hpp" +#include "LIEF/DEX/Prototype.hpp" +#include "LIEF/DEX/Field.hpp" + +#include "pyIterator.hpp" +#include "DEX/pyDEX.hpp" + +#include + +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ file(m, "File", "DEX File representation"_doc); + + init_ref_iterator(file, "it_classes"); + init_ref_iterator(file, "it_methods"); + init_ref_iterator(file, "it_strings"); + init_ref_iterator(file, "it_types"); + init_ref_iterator(file, "it_prototypes"); + init_ref_iterator(file, "it_fields"); + + file + .def_prop_ro("version", &File::version, + "Dex version"_doc) + + .def_prop_ro("header", nb::overload_cast<>(&File::header, nb::const_), + "Dex File " RST_CLASS_REF(lief.DEX.Header) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("classes", nb::overload_cast<>(&File::classes), + "Iterator over Dex " RST_CLASS_REF(lief.DEX.Class) ""_doc, + nb::keep_alive<0, 1>()) + + .def("has_class", &File::has_class, + "Check if a class with a name given in parameter exists"_doc, + "classname"_a) + + .def("get_class", + nb::overload_cast(&File::get_class), + "classname"_a, nb::rv_policy::reference_internal) + + .def("get_class", + nb::overload_cast(&File::get_class), + "classname"_a, nb::rv_policy::reference_internal) + + .def_prop_ro("methods", nb::overload_cast<>(&File::methods), + "Iterator over Dex " RST_CLASS_REF(lief.DEX.Method) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("fields", nb::overload_cast<>(&File::fields), + "Iterator over Dex " RST_CLASS_REF(lief.DEX.Field) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("strings", nb::overload_cast<>(&File::strings), + "Iterator over Dex strings"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("types", nb::overload_cast<>(&File::types), + "Iterator over Dex " RST_CLASS_REF(lief.DEX.Type) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("prototypes", + nb::overload_cast<>(&File::prototypes), + "Iterator over Dex " RST_CLASS_REF(lief.DEX.Prototype) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("map", nb::overload_cast<>(&File::map, nb::const_), + "Dex " RST_CLASS_REF(lief.DEX.MapList) ""_doc) + + .def("raw", &File::raw, + "Original raw file"_doc, + "deoptimize"_a = true) + + .def_prop_rw("name", + nb::overload_cast<>(&File::name, nb::const_), + nb::overload_cast(&File::name), + "Name of the dex file"_doc) + + .def_prop_rw("location", + nb::overload_cast<>(&File::location, nb::const_), + nb::overload_cast(&File::location), + "Original location of the dex file"_doc) + + //.def_prop_ro("dex2dex_info", + // &File::dex2dex_info) + + .def_prop_ro("dex2dex_json_info", + &File::dex2dex_json_info) + + .def("save", &File::save, + "Save the **original** file into the file given in first parameter"_doc, + "output"_a = "", "deoptimize"_a = true) + + LIEF_DEFAULT_STR(File); +} + +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyHeader.cpp b/vendor/lief/api/python/src/DEX/objects/pyHeader.cpp new file mode 100644 index 0000000..d98cf04 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyHeader.cpp @@ -0,0 +1,104 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/Header.hpp" + +#include "DEX/pyDEX.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create
(nb::module_& m) { + + nb::class_(m, "Header", "DEX Header"_doc) + + .def_prop_ro("magic", + nb::overload_cast<>(&Header::magic, nb::const_), + "Magic value") + + .def_prop_ro("checksum", + nb::overload_cast<>(&Header::checksum, nb::const_), + "Checksum value of the rest of the file (without " RST_ATTR_REF(lief.DEX.Header.magic) ")"_doc) + + .def_prop_ro("signature", + nb::overload_cast<>(&Header::signature, nb::const_), + R"delim( + SHA-1 signature of the rest of the file + (without :attr:`~lief.DEX.Header.magic` and :attr:`~lief.DEX.Header.checksum`). + )delim"_doc) + + .def_prop_ro("file_size", + nb::overload_cast<>(&Header::file_size, nb::const_), + "Size of the current DEX file"_doc) + + .def_prop_ro("header_size", + nb::overload_cast<>(&Header::header_size, nb::const_), + "Size of this header. Should be ``0x70``"_doc) + + .def_prop_ro("endian_tag", + nb::overload_cast<>(&Header::endian_tag, nb::const_), + "Endianness tag. Should be ``ENDIAN_CONSTANT``"_doc) + + .def_prop_ro("map_offset", + nb::overload_cast<>(&Header::map, nb::const_), + "Offset from the start of the file to the map item"_doc) + + .def_prop_ro("strings", + nb::overload_cast<>(&Header::strings, nb::const_), + "String identifiers"_doc) + + .def_prop_ro("link", + nb::overload_cast<>(&Header::link, nb::const_), + "Link (raw data)"_doc) + + .def_prop_ro("types", + nb::overload_cast<>(&Header::types, nb::const_), + "Type identifiers"_doc) + + .def_prop_ro("prototypes", + nb::overload_cast<>(&Header::prototypes, nb::const_), + "Prototypes identifiers"_doc) + + .def_prop_ro("fields", nb::overload_cast<>(&Header::fields, nb::const_), + "Fields identifiers"_doc) + + .def_prop_ro("methods", nb::overload_cast<>(&Header::methods, nb::const_), + "Methods identifiers"_doc) + + .def_prop_ro("classes", nb::overload_cast<>(&Header::classes, nb::const_), + "Classes identifiers"_doc) + + .def_prop_ro("data", nb::overload_cast<>(&Header::data, nb::const_), + "Raw data. Should be align on 32-bits"_doc) + + .def_prop_ro("nb_classes", + nb::overload_cast<>(&Header::nb_classes, nb::const_), + "Number of classes in the current DEX"_doc) + + .def_prop_ro("nb_methods", + nb::overload_cast<>(&Header::nb_methods, nb::const_), + "Number of methods in the current DEX"_doc) + + LIEF_DEFAULT_STR(Header); +} +} + + diff --git a/vendor/lief/api/python/src/DEX/objects/pyMapItem.cpp b/vendor/lief/api/python/src/DEX/objects/pyMapItem.cpp new file mode 100644 index 0000000..140491c --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyMapItem.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/MapItem.hpp" +#include "LIEF/DEX/EnumToString.hpp" + +#include "DEX/pyDEX.hpp" +#include "enums_wrapper.hpp" + +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + + nb::class_ mapitem(m, "MapItem", + "DEX MapItem representation"_doc); + + enum_(mapitem, "TYPES") + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::HEADER)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::STRING_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::TYPE_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::PROTO_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::FIELD_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::METHOD_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CLASS_DEF)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CALL_SITE_ID)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::METHOD_HANDLE)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::MAP_LIST)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::TYPE_LIST)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION_SET_REF_LIST)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION_SET)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CLASS_DATA)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::CODE)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::STRING_DATA)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::DEBUG_INFO)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATION)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ENCODED_ARRAY)) + .value(PY_ENUM(LIEF::DEX::MapItem::TYPES::ANNOTATIONS_DIRECTORY)); + + mapitem + .def_prop_ro("type", + nb::overload_cast<>(&MapItem::type, nb::const_), + "" RST_CLASS_REF(lief.DEX.MapItem.TYPES) " of the item"_doc) + + .def_prop_ro("offset", + nb::overload_cast<>(&MapItem::offset, nb::const_), + "Offset from the start of the file to the items in question"_doc) + + .def_prop_ro("size", + nb::overload_cast<>(&MapItem::size, nb::const_), + "Count of the number of items to be found at the indicated offset"_doc) + + LIEF_DEFAULT_STR(MapItem); +} + +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyMapList.cpp b/vendor/lief/api/python/src/DEX/objects/pyMapList.cpp new file mode 100644 index 0000000..14c00e1 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyMapList.cpp @@ -0,0 +1,56 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/MapList.hpp" + +#include "DEX/pyDEX.hpp" +#include "pyIterator.hpp" + +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ map_list(m, "MapList", + "DEX MapList representation"_doc); + + init_ref_iterator(map_list, "it_items_t"); + + map_list + .def_prop_ro("items", nb::overload_cast<>(&MapList::items), + "Iterator over " RST_CLASS_REF(lief.DEX.MapItem) ""_doc) + + .def("has", &MapList::has, + "Check if the given " RST_CLASS_REF(lief.DEX.MapItem.TYPES) " is present"_doc, + "type"_a) + + .def("get", nb::overload_cast(&MapList::get), + R"delim( + Return the :class:`~lief.DEX.MapItem` from the given + :class:`~lief.DEX.MapItem.TYPES` + )delim"_doc, "type"_a, nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&MapList::get)) + + LIEF_DEFAULT_STR(MapList); + +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyMethod.cpp b/vendor/lief/api/python/src/DEX/objects/pyMethod.cpp new file mode 100644 index 0000000..18a7de4 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyMethod.cpp @@ -0,0 +1,77 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/Method.hpp" +#include "LIEF/DEX/Prototype.hpp" +#include "LIEF/DEX/Class.hpp" + +#include "DEX/pyDEX.hpp" + +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "Method", "DEX Method representation"_doc) + .def_prop_ro("name", &Method::name, + "Method's name"_doc) + + .def_prop_ro("index", &Method::index, + "Original DEX file index of the method"_doc) + + .def_prop_ro("has_class", &Method::has_class, + "True if a class is associated with this method"_doc) + + .def_prop_ro("cls", nb::overload_cast<>(&Method::cls, nb::const_), + "" RST_CLASS_REF(lief.DEX.Class) " associated with this method"_doc) + + .def_prop_ro("code_offset", nb::overload_cast<>(&Method::code_offset, nb::const_), + "Offset to the Dalvik Bytecode"_doc) + + .def_prop_ro("bytecode", nb::overload_cast<>(&Method::bytecode, nb::const_), + "Dalvik Bytecode as a list of bytes"_doc) + + .def_prop_ro("is_virtual", &Method::is_virtual, + "True if the method is a virtual (not **private**, **static**, **final**, **constructor**)"_doc) + + .def_prop_ro("prototype", + nb::overload_cast<>(&Method::prototype, nb::const_), + "" RST_CLASS_REF(lief.DEX.Prototype) " of this method"_doc) + + .def_prop_ro("access_flags", + nb::overload_cast<>(&Method::access_flags, nb::const_), + "List of " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) ""_doc) + + .def("has", nb::overload_cast(&Method::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.DEX.ACCESS_FLAGS) " is present"_doc, + "flag"_a) + + .def("insert_dex2dex_info", &Method::insert_dex2dex_info, + "Insert de-optimization information"_doc, + "pc"_a, "index"_a) + + .def_prop_ro("code_info", nb::overload_cast<>(&Method::code_info, nb::const_), + "" RST_CLASS_REF(lief.DEX.CodeInfo) " associated with this method"_doc) + + + LIEF_DEFAULT_STR(Method); +} + +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyParser.cpp b/vendor/lief/api/python/src/DEX/objects/pyParser.cpp new file mode 100644 index 0000000..8350106 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyParser.cpp @@ -0,0 +1,71 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "DEX/pyDEX.hpp" + +#include "LIEF/DEX/Parser.hpp" +#include "LIEF/DEX/File.hpp" +#include "LIEF/logging.hpp" + +#include "pyutils.hpp" +#include "pyIOStream.hpp" +#include "typing/InputParser.hpp" + +#include +#include + +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse", + static_cast(*)(std::string_view)>(&Parser::parse), + "Parse the given filename and return a " RST_CLASS_REF(lief.DEX.File) " object"_doc, + "filename"_a, + nb::rv_policy::take_ownership); + + m.def("parse", + static_cast(*)(std::vector, std::string_view)>( + &Parser::parse), + "Parse the given raw data and return a " RST_CLASS_REF(lief.DEX.File) " object"_doc, + "raw"_a, "name"_a = "", + nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const std::string& name) -> std::unique_ptr { + if (auto path_str = path_to_str(obj)) { + return DEX::Parser::parse(std::move(*path_str)); + } + + if (auto stream = PyIOStream::from_python(obj)) { + auto ptr = std::make_unique(std::move(*stream)); + return DEX::Parser::parse(stream->content(), name); + } + + logging::log(logging::Level::Err, + "LIEF parser interface does not support Python object: " + + type2str(obj)); + return nullptr; + }, "obj"_a, "name"_a = "", + nb::rv_policy::take_ownership); +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyPrototype.cpp b/vendor/lief/api/python/src/DEX/objects/pyPrototype.cpp new file mode 100644 index 0000000..6f018d4 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyPrototype.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/Prototype.hpp" +#include "LIEF/DEX/Type.hpp" + +#include "DEX/pyDEX.hpp" +#include "pyIterator.hpp" + +#include +#include +#include +#include + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ proto(m, "Prototype", + "DEX Prototype representation"_doc); + + init_ref_iterator(proto, "it_params"); + + proto + .def_prop_ro("return_type", + nb::overload_cast<>(&Prototype::return_type, nb::const_), + "" RST_CLASS_REF(lief.DEX.Type) " returned"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("parameters_type", + nb::overload_cast<>(&Prototype::parameters_type), + "Iterator over parameters " RST_CLASS_REF(lief.DEX.Type) ""_doc) + + LIEF_DEFAULT_STR(Prototype); +} +} diff --git a/vendor/lief/api/python/src/DEX/objects/pyType.cpp b/vendor/lief/api/python/src/DEX/objects/pyType.cpp new file mode 100644 index 0000000..e1f8c95 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/objects/pyType.cpp @@ -0,0 +1,102 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DEX/Type.hpp" +#include "LIEF/DEX/Class.hpp" + +#include "LIEF/DEX/EnumToString.hpp" + +#include "DEX/pyDEX.hpp" + +#include +#include +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::DEX::py { + +template<> +void create(nb::module_& m) { + + nb::class_ pytype(m, "Type", + "DEX Type representation"_doc); + + nb::enum_(pytype, "TYPES") + .value(PY_ENUM(Type::TYPES::UNKNOWN)) + .value(PY_ENUM(Type::TYPES::ARRAY)) + .value(PY_ENUM(Type::TYPES::PRIMITIVE)) + .value(PY_ENUM(Type::TYPES::CLASS)); + + nb::enum_(pytype, "PRIMITIVES") + .value(PY_ENUM(Type::PRIMITIVES::VOID_T)) + .value(PY_ENUM(Type::PRIMITIVES::BOOLEAN)) + .value(PY_ENUM(Type::PRIMITIVES::BYTE)) + .value(PY_ENUM(Type::PRIMITIVES::SHORT)) + .value(PY_ENUM(Type::PRIMITIVES::CHAR)) + .value(PY_ENUM(Type::PRIMITIVES::INT)) + .value(PY_ENUM(Type::PRIMITIVES::LONG)) + .value(PY_ENUM(Type::PRIMITIVES::FLOAT)) + .value(PY_ENUM(Type::PRIMITIVES::DOUBLE)); + + pytype + .def_prop_ro("type", &Type::type, + "" RST_CLASS_REF(lief.DEX.Type.TYPES) " of this object"_doc) + + .def_prop_ro("value", + [] (Type& type) -> nb::object { + switch (type.type()) { + case Type::TYPES::ARRAY: + { + return nb::cast(type.array()); + } + + case Type::TYPES::CLASS: + { + return nb::cast(type.cls(), nb::rv_policy::reference_internal); + } + + case Type::TYPES::PRIMITIVE: + { + return nb::cast(type.primitive()); + } + + case Type::TYPES::UNKNOWN: + default: + { + return nb::none(); + } + } + }, + "Depending on the " RST_CLASS_REF(lief.DEX.Type.TYPES) ", return " + " " RST_CLASS_REF(lief.DEX.Class) " or " RST_CLASS_REF(lief.DEX.Type.PRIMITIVES) " or array"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("dim", + &Type::dim, + "If the current type is an array, return its dimension otherwise 0") + + .def_prop_ro("underlying_array_type", + nb::overload_cast<>(&Type::underlying_array_type, nb::const_), + "Underlying type of the array"_doc, + nb::rv_policy::reference_internal) + + .def_static("pretty_name", &Type::pretty_name, + "Pretty name of primitives"_doc, + "primitive"_a) + + LIEF_DEFAULT_STR(Type); +} +} diff --git a/vendor/lief/api/python/src/DEX/pyDEX.hpp b/vendor/lief/api/python/src/DEX/pyDEX.hpp new file mode 100644 index 0000000..12838e3 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/pyDEX.hpp @@ -0,0 +1,27 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_DEX_H +#define PY_LIEF_DEX_H + +#include "pyLIEF.hpp" + +namespace LIEF::DEX::py { +template +void create(nb::module_&); +} + + +#endif diff --git a/vendor/lief/api/python/src/DEX/pyEnums.cpp b/vendor/lief/api/python/src/DEX/pyEnums.cpp new file mode 100644 index 0000000..e040200 --- /dev/null +++ b/vendor/lief/api/python/src/DEX/pyEnums.cpp @@ -0,0 +1,47 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "DEX/pyDEX.hpp" +#include "LIEF/DEX/enums.hpp" +#include "LIEF/DEX/EnumToString.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::DEX::py { +void init_enums(nb::module_& m) { + + nb::enum_(m, "ACCESS_FLAGS") + .value(PY_ENUM(ACCESS_FLAGS::ACC_UNKNOWN)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_PUBLIC)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_PRIVATE)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_PROTECTED)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_STATIC)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_FINAL)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_SYNCHRONIZED)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_VOLATILE)) + .value("BRIDGE", ACCESS_FLAGS::ACC_BRIDGE) + .value("TRANSIENT", ACCESS_FLAGS::ACC_TRANSIENT) + .value(PY_ENUM(ACCESS_FLAGS::ACC_VARARGS)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_NATIVE)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_INTERFACE)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_ABSTRACT)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_STRICT)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_SYNTHETIC)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_ANNOTATION)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_ENUM)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_CONSTRUCTOR)) + .value(PY_ENUM(ACCESS_FLAGS::ACC_DECLARED_SYNCHRONIZED)); +} +} diff --git a/vendor/lief/api/python/src/DEX/pyUtils.cpp b/vendor/lief/api/python/src/DEX/pyUtils.cpp new file mode 100644 index 0000000..6f0de5a --- /dev/null +++ b/vendor/lief/api/python/src/DEX/pyUtils.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "DEX/pyDEX.hpp" + +#include "LIEF/DEX/utils.hpp" + +#include +#include +#include + +namespace LIEF::DEX::py { + +void init_utils(nb::module_& m) { + lief_mod->def("is_dex", + nb::overload_cast(&is_dex), + "Check if the **file** given in parameter is a DEX"_doc, + "path"_a); + + lief_mod->def("is_dex", + nb::overload_cast&>(&is_dex), + "Check if the **raw data** given in parameter is a DEX"_doc, + "raw"_a); + + m.def("version", + nb::overload_cast(&version), + "Return the DEX version of the **file** given in parameter"_doc, + "file"_a); + + m.def("version", + nb::overload_cast&>(&version), + "Return the DEX version of the **raw data** given in parameter"_doc, + "raw"_a); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/CMakeLists.txt b/vendor/lief/api/python/src/DWARF/CMakeLists.txt new file mode 100644 index 0000000..56b6406 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/CMakeLists.txt @@ -0,0 +1,15 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyCompilationUnit.cpp + pyDebugInfo.cpp + pyEditor.cpp + pyFunction.cpp + pyParameter.cpp + pyScope.cpp + pyType.cpp + pyVariable.cpp + pyLexicalBlock.cpp +) + +add_subdirectory(types) +add_subdirectory(editor) diff --git a/vendor/lief/api/python/src/DWARF/editor/CMakeLists.txt b/vendor/lief/api/python/src/DWARF/editor/CMakeLists.txt new file mode 100644 index 0000000..4befcbe --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/CMakeLists.txt @@ -0,0 +1,13 @@ +target_sources(pyLIEF PRIVATE + pyFunction.cpp + pyVariable.cpp + pyCompilationUnit.cpp + pyType.cpp + pyPointerType.cpp + pyEnumType.cpp + pyBaseType.cpp + pyArrayType.cpp + pyFunctionType.cpp + pyTypeDef.cpp + pyStructType.cpp +) diff --git a/vendor/lief/api/python/src/DWARF/editor/pyArrayType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyArrayType.cpp new file mode 100644 index 0000000..cbe6151 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyArrayType.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/editor/ArrayType.hpp" + +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "ArrayType", + R"doc( + This class represents an array type. + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyBaseType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyBaseType.cpp new file mode 100644 index 0000000..c470bfa --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyBaseType.cpp @@ -0,0 +1,27 @@ +#include "LIEF/DWARF/editor/BaseType.hpp" + +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ BT(m, "BaseType", + R"doc( + This class represents a primitive type like ``int, char``. + )doc"_doc + ); + + using ENCODING = dw::editor::BaseType::ENCODING; + nb::enum_(BT, "ENCODING") + .value("NONE", ENCODING::NONE) + .value("ADDRESS", ENCODING::ADDRESS) + .value("SIGNED", ENCODING::SIGNED) + .value("SIGNED_CHAR", ENCODING::SIGNED_CHAR) + .value("UNSIGNED", ENCODING::UNSIGNED) + .value("UNSIGNED_CHAR", ENCODING::UNSIGNED_CHAR) + .value("BOOLEAN", ENCODING::BOOLEAN) + .value("FLOAT", ENCODING::FLOAT) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyCompilationUnit.cpp b/vendor/lief/api/python/src/DWARF/editor/pyCompilationUnit.cpp new file mode 100644 index 0000000..51db330 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyCompilationUnit.cpp @@ -0,0 +1,79 @@ +#include "LIEF/DWARF/editor/CompilationUnit.hpp" +#include "LIEF/DWARF/editor/Function.hpp" +#include "LIEF/DWARF/editor/Variable.hpp" +#include "LIEF/DWARF/editor/ArrayType.hpp" +#include "LIEF/DWARF/editor/TypeDef.hpp" +#include "LIEF/DWARF/editor/StructType.hpp" +#include "LIEF/DWARF/editor/EnumType.hpp" +#include "LIEF/DWARF/editor/PointerType.hpp" +#include "LIEF/DWARF/editor/Type.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ CU(m, "CompilationUnit", + R"doc( + This class represents an **editable** DWARF compilation unit + )doc"_doc + ); + + CU + .def("set_producer", &dw::editor::CompilationUnit::set_producer, + R"doc( + Set the ``DW_AT_producer`` producer attribute. + + This attribute aims to inform about the program that generated this + compilation unit (e.g. ``LIEF Extended``) + )doc"_doc, nb::rv_policy::reference_internal) + + .def("create_function", &dw::editor::CompilationUnit::create_function, + "Create a new function owned by this compilation unit"_doc, + "name"_a) + + .def("create_variable", &dw::editor::CompilationUnit::create_variable, + "Create a new **global** variable owned by this compilation unit"_doc, + "name"_a) + + .def("create_generic_type", &dw::editor::CompilationUnit::create_generic_type, + "Create a ``DW_TAG_unspecified_type`` type with the given name"_doc, + "name"_a) + + .def("create_enum", &dw::editor::CompilationUnit::create_enum, + "Create an enum type (``DW_TAG_enumeration_type``)"_doc, + "name"_a) + + .def("create_typedef", &dw::editor::CompilationUnit::create_typedef, + R"doc( + Create a typedef with the name provided in the first parameter which aliases + the type provided in the second parameter + )doc"_doc, "name"_a, "ty"_a) + + .def("create_structure", &dw::editor::CompilationUnit::create_structure, + "Create a struct-like type (struct, class, union) with the given name"_doc, + "name"_a, "kind"_a = dw::editor::StructType::TYPE::STRUCT) + + .def("create_base_type", &dw::editor::CompilationUnit::create_base_type, + "Create a primitive type with the given name and size."_doc, + "name"_a, "size"_a, "encoding"_a = dw::editor::BaseType::ENCODING::NONE) + + .def("create_function_type", &dw::editor::CompilationUnit::create_function_type, + "Create a function type with the given name."_doc, "name"_a) + + .def("create_pointer_type", &dw::editor::CompilationUnit::create_pointer_type, + "Create a pointer on the provided type."_doc, "ty"_a) + + .def("create_void_type", &dw::editor::CompilationUnit::create_void_type, + "Create a ``void`` type"_doc) + + .def("create_array", &dw::editor::CompilationUnit::create_array, + "Create an array type with the given name, type and size."_doc, + "name"_a, "ty"_a, "count"_a) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyEnumType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyEnumType.cpp new file mode 100644 index 0000000..1553e17 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyEnumType.cpp @@ -0,0 +1,40 @@ +#include "LIEF/DWARF/editor/EnumType.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ E(m, "EnumType", + R"doc( + This class represents an editable enum type (``DW_TAG_enumeration_type``) + )doc"_doc + ); + + nb::class_(E, "Value", + "This class represents an enum value"_doc + ); + + E + .def("set_size", &dw::editor::EnumType::set_size, + R"doc( + Define the number of bytes required to hold an instance of the + enumeration (``DW_AT_byte_size``). + )doc"_doc, "size"_a, nb::rv_policy::reference_internal) + + .def("set_underlying_type", &dw::editor::EnumType::set_underlying_type, + "Set the underlying type that is used to encode this enum"_doc, + "type"_a, nb::rv_policy::reference_internal + ) + + .def("add_value", &dw::editor::EnumType::add_value, + R"doc( + Add an enum value by specifying its name and its integer value. + )doc"_doc, "name"_a, "value"_a, nb::rv_policy::reference_internal) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyFunction.cpp b/vendor/lief/api/python/src/DWARF/editor/pyFunction.cpp new file mode 100644 index 0000000..7438ea3 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyFunction.cpp @@ -0,0 +1,141 @@ +#include "LIEF/DWARF/editor/Function.hpp" +#include "LIEF/DWARF/editor/Variable.hpp" +#include "LIEF/DWARF/editor/Type.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ F(m, "Function", + R"doc( + This class represents an **editable** DWARF function (``DW_TAG_subprogram``) + )doc"_doc + ); + + using range_t = dw::editor::Function::range_t; + nb::class_(F, "range_t") + .def(nb::init<>()) + .def(nb::init(), "start"_a, "end"_a) + .def_rw("start", &range_t::start) + .def_rw("end", &range_t::end); + + using Parameter = dw::editor::Function::Parameter; + nb::class_ FP(F, "Parameter", + R"doc( + This class represents a parameter of the current function (``DW_TAG_formal_parameter``) + )doc"_doc + ); + + FP + .def("assign_register", nb::overload_cast(&Parameter::assign_register), + "Assign this parameter to a specific named register."_doc, + nb::rv_policy::reference_internal + ) + .def("assign_register", nb::overload_cast(&Parameter::assign_register), + R"doc(Assign this parameter to the given DWARF register id (e.g. ``DW_OP_reg0``))doc"_doc, + nb::rv_policy::reference_internal + ); + + using LexicalBlock = dw::editor::Function::LexicalBlock; + nb::class_ FLB(F, "LexicalBlock", + "This class mirrors the ``DW_TAG_lexical_block`` DWARF tag"_doc + ); + + FLB + .def("add_block", nb::overload_cast(&LexicalBlock::add_block), + R"doc( + Create a sub-block with the given low/high addresses. + + If the function managed to create the new block, it returns + the newly created block, otherwise it returns the current block + )doc"_doc, "start"_a, "end"_a, nb::rv_policy::reference_internal + ) + + .def("add_block", nb::overload_cast&>(&LexicalBlock::add_block), + R"doc( + Create a sub-block with the given range of addresses. + + If the function managed to create the new block, it returns + the newly created block, otherwise it returns the current block + )doc"_doc, "range"_a, nb::rv_policy::reference_internal + ) + + .def("add_description", &LexicalBlock::add_description, + R"doc( + Create a ``DW_AT_description`` entry with the description + provided in parameter. + )doc"_doc, "description"_a, nb::rv_policy::reference_internal + ) + + .def("add_name", &LexicalBlock::add_name, + R"doc( + Create a ``DW_AT_name`` entry to associate a name to this entry + )doc"_doc, "name"_a, nb::rv_policy::reference_internal + ) + ; + + nb::class_ FL(F, "Label", + "This class mirrors the ``DW_TAG_label`` DWARF tag"_doc + ); + + F + .def("set_address", &dw::editor::Function::set_address, + "Set the address of this function by defining ``DW_AT_entry_pc``"_doc, + "addr"_a, nb::rv_policy::reference_internal) + + .def("set_low_high", &dw::editor::Function::set_low_high, + R"doc( + Set the upper and lower bound addresses for this function. This assumes + that the function is contiguous between ``low`` and ``high``. + + Underneath, the function defines ``DW_AT_low_pc`` and ``DW_AT_high_pc`` + )doc"_doc, "low"_a, "high"_a, nb::rv_policy::reference_internal) + + .def("set_ranges", &dw::editor::Function::set_ranges, + R"doc( + Set the ranges of addresses owned by the implementation of this function + by setting the ``DW_AT_ranges`` attribute. + + This setter should be used for non-contiguous functions. + )doc"_doc, "ranges"_a, nb::rv_policy::reference_internal) + + .def("set_external", &dw::editor::Function::set_external, + R"doc( + Set the function as external by defining ``DW_AT_external`` to true. + This means that the function is **imported** by the current compilation + unit.)doc"_doc, nb::rv_policy::reference_internal) + + .def("set_return_type", &dw::editor::Function::set_return_type, + "Set the return type of this function"_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def("add_parameter", &dw::editor::Function::add_parameter, + "Add a parameter to the current function"_doc, + "name"_a, "type"_a) + + .def("create_stack_variable", &dw::editor::Function::create_stack_variable, + "Create a stack-based variable owned by the current function"_doc, + "name"_a) + + .def("add_lexical_block", &dw::editor::Function::add_lexical_block, + "Add a lexical block with the given range"_doc, + "start"_a, "end"_a) + + .def("add_label", &dw::editor::Function::add_label, + "Add a label at the given address"_doc, + "addr"_a, "label"_a) + + .def("add_description", &dw::editor::Function::add_description, + R"doc( + Create a `DW_AT_description` entry with the description + provided in parameter. + )doc"_doc, "description"_a, nb::rv_policy::reference_internal) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyFunctionType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyFunctionType.cpp new file mode 100644 index 0000000..187a63f --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyFunctionType.cpp @@ -0,0 +1,30 @@ +#include "LIEF/DWARF/editor/FunctionType.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ F(m, "FunctionType", + R"doc( + This class represents a function type (``DW_TAG_subroutine_type``) + )doc"_doc + ); + + nb::class_ FP(F, "Parameter", + "This class represents a function's parameter"_doc + ); + F + .def("set_return_type", &dw::editor::FunctionType::set_return_type, + "Set the return type of this function"_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def("add_parameter", &dw::editor::FunctionType::add_parameter, + "Add a parameter"_doc, "type"_a) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyPointerType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyPointerType.cpp new file mode 100644 index 0000000..9a1bb25 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyPointerType.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/editor/PointerType.hpp" + +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "PointerType", + R"doc( + This class represents a pointer to another type. + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyStructType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyStructType.cpp new file mode 100644 index 0000000..564e00b --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyStructType.cpp @@ -0,0 +1,50 @@ +#include "LIEF/DWARF/editor/StructType.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ S(m, "StructType", + R"doc( + This class represents a struct-like type which can be: + + - ``DW_TAG_class_type`` + - ``DW_TAG_structure_type`` + - ``DW_TAG_union_type`` + )doc"_doc + ); + + using TYPE = dw::editor::StructType::TYPE; + nb::enum_(S, "TYPE") + .value("CLASS", TYPE::CLASS, "Discriminant for ``DW_TAG_class_type``"_doc) + .value("STRUCT", TYPE::STRUCT, "Discriminant for ``DW_TAG_structure_type``"_doc) + .value("UNION", TYPE::UNION, "Discriminant for ``DW_TAG_union_type``"_doc); + + nb::class_(S, "Member", + "This class represents a member of the struct-like"_doc + ); + + S + .def("set_size", &dw::editor::StructType::set_size, + R"doc( + Define the overall size which is equivalent to the ``sizeof`` of the + current type. + + This function defines the ``DW_AT_byte_size`` attribute + )doc"_doc, "size"_a, nb::rv_policy::reference_internal) + + .def("add_member", &editor::StructType::add_member, + "Adds a member to the current struct-like"_doc, + "name"_a, "type"_a, "offset"_a = -1) + + .def("add_bitfield", &editor::StructType::add_bitfield, + "Adds a member to the current struct-like"_doc, + "name"_a, "type"_a, "bitsize"_a, "bitoffset"_a = -1) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyType.cpp b/vendor/lief/api/python/src/DWARF/editor/pyType.cpp new file mode 100644 index 0000000..6cc3e54 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyType.cpp @@ -0,0 +1,39 @@ +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/DWARF/editor/PointerType.hpp" +#include "LIEF/DWARF/editor/EnumType.hpp" +#include "LIEF/DWARF/editor/BaseType.hpp" +#include "LIEF/DWARF/editor/ArrayType.hpp" +#include "LIEF/DWARF/editor/FunctionType.hpp" +#include "LIEF/DWARF/editor/TypeDef.hpp" +#include "LIEF/DWARF/editor/StructType.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "Type", + R"doc( + This class is the base class for any types created when editing DWARF debug + info. + + A type is owned by a :class:`lief.dwarf.editor.CompilationUnit` and should be + created from this class. + )doc"_doc + ) + .def("pointer_to", &dw::editor::Type::pointer_to, + "Create a pointer type pointing to this type"_doc) + ; + + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyTypeDef.cpp b/vendor/lief/api/python/src/DWARF/editor/pyTypeDef.cpp new file mode 100644 index 0000000..321e88f --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyTypeDef.cpp @@ -0,0 +1,13 @@ +#include "LIEF/DWARF/editor/TypeDef.hpp" + +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "TypeDef", + "This class represents a typedef (``DW_TAG_typedef``)."_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/editor/pyVariable.cpp b/vendor/lief/api/python/src/DWARF/editor/pyVariable.cpp new file mode 100644 index 0000000..f31eeb7 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/editor/pyVariable.cpp @@ -0,0 +1,53 @@ +#include "LIEF/DWARF/editor/Variable.hpp" +#include "LIEF/DWARF/editor/Type.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ V(m, "Variable", + R"doc( + This class represents an **editable** DWARF variable which can be + scoped by a function or a compilation unit (``DW_TAG_variable``) + )doc"_doc + ); + + V + .def("set_addr", &dw::editor::Variable::set_addr, + R"doc( + Set the global address of this variable. Setting this address is only + relevant in the case of a static global variable. For stack variable, you + should use :meth:`~.Variable.set_stack_offset`. + + This function sets the ``DW_AT_location`` attribute + )doc"_doc, "addr"_a, nb::rv_policy::reference_internal) + + .def("set_stack_offset", &dw::editor::Variable::set_stack_offset, + R"doc( + Set the stack offset of this variable. + + This function sets the ``DW_AT_location`` attribute + )doc"_doc, "offset"_a, nb::rv_policy::reference_internal) + + .def("set_external", &dw::editor::Variable::set_external, + R"doc( + Mark this variable as **imported** + )doc"_doc, nb::rv_policy::reference_internal) + + .def("set_type", &dw::editor::Variable::set_type, + R"doc( + Set the type of the current variable + )doc"_doc, "type"_a, nb::rv_policy::reference_internal) + + .def("add_description", &dw::editor::Variable::add_description, + R"doc( + Create a ``DW_AT_description`` entry with the description + provided in parameter. + )doc"_doc, "description"_a, nb::rv_policy::reference_internal) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/init.cpp b/vendor/lief/api/python/src/DWARF/init.cpp new file mode 100644 index 0000000..6437b58 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/init.cpp @@ -0,0 +1,32 @@ +#include "DWARF/init.hpp" +#include "DWARF/pyDwarf.hpp" + +#include "LIEF/DWARF/DebugInfo.hpp" +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/DWARF/Editor.hpp" + +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::dwarf::py { +void init(nb::module_& m) { + nb::module_ dwarf = m.def_submodule("dwarf"); + + dwarf.def("load", [] (nb::PathLike path) { return load(path); }, + R"doc( + Load the DWARF from the given path + )doc"_doc, "path"_a + ); + + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); + create(dwarf); +} +} diff --git a/vendor/lief/api/python/src/DWARF/init.hpp b/vendor/lief/api/python/src/DWARF/init.hpp new file mode 100644 index 0000000..b608cb5 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/init.hpp @@ -0,0 +1,8 @@ +#ifndef PY_LIEF_DBG_DWARF_INIT_H +#define PY_LIEF_DBG_DWARF_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::dwarf::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/DWARF/pyCompilationUnit.cpp b/vendor/lief/api/python/src/DWARF/pyCompilationUnit.cpp new file mode 100644 index 0000000..10a2082 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyCompilationUnit.cpp @@ -0,0 +1,269 @@ +#include "LIEF/DWARF/CompilationUnit.hpp" +#include "LIEF/DWARF/Function.hpp" +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DebugDeclOpt.hpp" +#include "DWARF/pyDwarf.hpp" +#include "DWARF/pyTypes.hpp" + +#include "enums_wrapper.hpp" + +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ CU(m, "CompilationUnit", + R"doc( + This class represents a DWARF compilation unit + )doc"_doc + ); + + nb::class_ Lang(CU, "Language", + R"doc( + Languages supported by the DWARF (v5) format. + See: https://dwarfstd.org/languages.html + + Some languages (like C++11, C++17, ..) have a version (11, 17, ...) which + is stored in a dedicated attribute: :attr:`~.version` + )doc"_doc + ); + + enum_(Lang, "LANG") + .value("UNKNOWN", dw::CompilationUnit::Language::LANG::UNKNOWN) + .value("C", dw::CompilationUnit::Language::LANG::C) + .value("CPP", dw::CompilationUnit::Language::LANG::CPP) + .value("RUST", dw::CompilationUnit::Language::LANG::RUST) + .value("DART", dw::CompilationUnit::Language::LANG::DART) + .value("MODULA", dw::CompilationUnit::Language::LANG::MODULA) + .value("FORTRAN", dw::CompilationUnit::Language::LANG::FORTRAN) + .value("SWIFT", dw::CompilationUnit::Language::LANG::SWIFT) + .value("D", dw::CompilationUnit::Language::LANG::D) + .value("JAVA", dw::CompilationUnit::Language::LANG::JAVA) + .value("COBOL", dw::CompilationUnit::Language::LANG::COBOL) + ; + + Lang + .def_rw("lang", &dw::CompilationUnit::Language::lang, + "The language itself") + .def_rw("version", &dw::CompilationUnit::Language::version, + "Version of the language (e.g. 17 for C++17)"); + + CU + .def_prop_ro("name", &dw::CompilationUnit::name, + R"doc( + Name of the file associated with this compilation unit (e.g. ``test.cpp``) + Return an **empty** string if the name is not found or can't be resolved + + This value matches the ``DW_AT_name`` attribute. + )doc"_doc + ) + .def_prop_ro("producer", &dw::CompilationUnit::producer, + R"doc( + Information about the program (or library) that generated this compilation + unit. For instance, it can output: ``Debian clang version 17.0.6``. + + It returns an **empty** string if the producer is not present or can't be + resolved. + + This value matches the ``DW_AT_producer`` attribute. + )doc"_doc + + ) + + .def_prop_ro("compilation_dir", &dw::CompilationUnit::compilation_dir, + R"doc( + Return the path to the directory in which the compilation took place for + compiling this compilation unit (e.g. ``/workdir/build``) + + It returns an **empty** string if the entry is not present or can't be + resolved. + + This value matches the ``DW_AT_comp_dir`` attribute. + )doc"_doc + ) + + .def_prop_ro("language", &dw::CompilationUnit::language, + R"doc( + Original language of this compilation unit. + + This value matches the ``DW_AT_language`` attribute. + )doc"_doc + ) + + .def_prop_ro("low_address", &dw::CompilationUnit::low_address, + R"doc( + Return the lowest virtual address owned by this compilation unit. + )doc"_doc + ) + + .def_prop_ro("high_address", &dw::CompilationUnit::high_address, + R"doc( + Return the highest virtual address owned by this compilation unit + )doc"_doc + ) + + .def_prop_ro("size", &dw::CompilationUnit::size, + R"doc( + Return the size of the compilation unit according to its range of address. + + If the compilation is fragmented (i.e. there are some address ranges + between the lowest address and the highest that are not owned by the CU), + then it returns the sum of **all** the address ranges owned by this CU. + + If the compilation unit is **not** fragmented, then it basically returns + ``high_address - low_address``. + )doc"_doc + ) + + .def_prop_ro("ranges", &dw::CompilationUnit::ranges, + R"doc( + Return a list of address ranges owned by this compilation unit. + + If the compilation unit owns a contiguous range, it returns + **a single** range. + )doc"_doc + ) + + .def("find_function", + nb::overload_cast(&dw::CompilationUnit::find_function, nb::const_), + R"doc( + Try to find the function whose name is given in parameter. + + The provided name can be demangled. + )doc"_doc, "name"_a + ) + + .def("find_function", + nb::overload_cast(&dw::CompilationUnit::find_function, nb::const_), + R"doc( + Try to find the function at the given address + )doc"_doc, "addr"_a + ) + + .def("find_variable", + nb::overload_cast(&dw::CompilationUnit::find_variable, nb::const_), + R"doc( + Try to find the variable at the given address + )doc"_doc, "addr"_a + ) + + .def("find_variable", + nb::overload_cast(&dw::CompilationUnit::find_variable, nb::const_), + R"doc( + Try to find the variable with the given name (mangled or not) + )doc"_doc, "name"_a + ) + + .def_prop_ro("types", + [] (dw::CompilationUnit& self) { + auto types = LIEF::py::owning_range(self.types()); + return nb::make_iterator( + nb::type(), "types_it", types + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the different types defined in this + compilation unit. + )doc"_doc + ) + + .def_prop_ro("functions", + [] (dw::CompilationUnit& self) { + auto functions = LIEF::py::owning_range(self.functions()); + return nb::make_iterator( + nb::type(), "functions_it", functions + ); + }, nb::keep_alive<0, 1>(), + R"delim( + Return an iterator over the functions implemented in this compilation + unit. + + Note that this iterator only iterates over the functions that have a + **concrete** implementation in the compilation unit. + + For instance with this code: + + .. code-block:: cpp + + inline const char* get_secret_env() { + return getenv("MY_SECRET_ENV"); + } + + int main() { + printf("%s", get_secret_env()); + return 0; + } + + The iterator will only return **one function** for ``main`` since + ``get_secret_env`` is inlined and thus, its implementation is located in + ``main``. + )delim"_doc + ) + + .def_prop_ro("imported_functions", + [] (dw::CompilationUnit& self) { + auto imported_functions = LIEF::py::owning_range(self.imported_functions()); + return nb::make_iterator( + nb::type(), "functions_it", imported_functions + ); + }, nb::keep_alive<0, 1>(), + R"delim( + Return an iterator over the functions **imported** in this compilation + unit **but not** implemented. + + For instance with this code: + + .. code-block:: cpp + + #include + int main() { + printf("Hello\n"); + return 0; + } + + ``printf`` is imported from the standard libc so the function is returned by + the iterator. On the other hand, ``main()`` is implemented in this + compilation unit so it is not returned by :attr:`.imported_functions` but + :attr:`.functions`. + )delim"_doc + ) + + .def_prop_ro("variables", + [] (dw::CompilationUnit& self) { + auto variables = LIEF::py::owning_range(self.variables()); + return nb::make_iterator( + nb::type(), "vars_it", variables); + }, nb::keep_alive<0, 1>(), + R"delim( + Return an iterator over the variables defined in any scope + of this compilation unit: + + .. code-block:: cpp + + static int A = 1; // Returned by the iterator + static const char* B = "Hello"; // Returned by the iterator + + int get() { + static int C = 2; // Returned by the iterator + return C; + } + )delim"_doc + ) + + .def("to_decl", + [] (const dw::CompilationUnit& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for the functions defined in this " + "compilation unit"_doc, + "opt"_a.none() = nb::none()) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyDebugInfo.cpp b/vendor/lief/api/python/src/DWARF/pyDebugInfo.cpp new file mode 100644 index 0000000..0535f56 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyDebugInfo.cpp @@ -0,0 +1,74 @@ +#include "LIEF/Abstract/DebugInfo.hpp" +#include "LIEF/DWARF/DebugInfo.hpp" +#include "LIEF/DWARF/Function.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ dbg_info(m, "DebugInfo", + R"doc( + This class represents a DWARF debug information. It can embed different + compilation units which can be accessed through :attr:`~.compilation_units`. + + This class can be instantiated from :attr:`lief.Binary.debug_info` or + :func:`lief.dwarf.load` + )doc"_doc + ); + + dbg_info + .def("find_function", nb::overload_cast(&DebugInfo::find_function, nb::const_), + R"doc( + Try to find the function with the given name (mangled or not) + + .. code-block:: python + + info: lief.dwarf.DebugInfo = ... + if func := info.find_function("_ZNSt6localeD1Ev"): + print("Found") + if func := info.find_function("std::locale::~locale()"): + print("Found") + )doc"_doc, "name"_a + ) + + .def("find_function", nb::overload_cast(&DebugInfo::find_function, nb::const_), + R"doc( + Try to find the function at the given **virtual** address. + )doc"_doc, "addr"_a + ) + + .def("find_variable", nb::overload_cast(&DebugInfo::find_variable, nb::const_), + R"doc( + Try to find the (static) variable at the given virtual address. + )doc"_doc, "addr"_a + ) + + .def("find_variable", nb::overload_cast(&DebugInfo::find_variable, nb::const_), + R"doc( + Try to find the variable with the given name. This name can be mangled or not. + )doc"_doc, "name"_a + ) + + .def("find_type", nb::overload_cast(&DebugInfo::find_type, nb::const_), + R"doc( + Try to find the type with the given name. + )doc"_doc, "name"_a + ) + + .def_prop_ro("compilation_units", + [] (DebugInfo& self) { + auto units = LIEF::py::owning_range(self.compilation_units()); + return nb::make_iterator( + nb::type(), "compilation_units_it", units); + }, nb::keep_alive<0, 1>(), + "Iterator on the CompilationUnit embedded in this dwarf"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyDwarf.hpp b/vendor/lief/api/python/src/DWARF/pyDwarf.hpp new file mode 100644 index 0000000..74d0361 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyDwarf.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_DBG_DWARF_H +#define PY_LIEF_DBG_DWARF_H +#include "pyLIEF.hpp" + +namespace LIEF::dwarf::py { + +namespace dw = LIEF::dwarf; + +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/DWARF/pyEditor.cpp b/vendor/lief/api/python/src/DWARF/pyEditor.cpp new file mode 100644 index 0000000..cd546ae --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyEditor.cpp @@ -0,0 +1,63 @@ +#include "LIEF/DWARF/Editor.hpp" +#include "LIEF/DWARF/editor/CompilationUnit.hpp" +#include "LIEF/Abstract/Binary.hpp" + +#include "DWARF/pyDwarf.hpp" + +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::module_ m_editor = m.def_submodule("editor"); + + create(m_editor); + create(m_editor); + create(m_editor); + create(m_editor); + + nb::class_ editor(m, "Editor", + R"doc( + This class exposes the main API to create DWARF information + )doc"_doc + ); + + nb::enum_(editor, "ARCH") + .value("UNKNOWN", dw::Editor::ARCH::UNKNOWN) + .value("X64", dw::Editor::ARCH::X64) + .value("X86", dw::Editor::ARCH::X86) + .value("AARCH64", dw::Editor::ARCH::AARCH64) + .value("ARM", dw::Editor::ARCH::ARM) + ; + + nb::enum_(editor, "FORMAT") + .value("ELF", dw::Editor::FORMAT::ELF) + .value("PE", dw::Editor::FORMAT::PE) + .value("MACHO", dw::Editor::FORMAT::MACHO) + ; + + editor + .def_static("from_binary", &dw::Editor::from_binary, + "Instantiate an editor for the given binary object"_doc, + "bin"_a + ) + .def_static("create", &dw::Editor::create, + "Instantiate an editor for the given format and arch"_doc, + "fmt"_a, "arch"_a + ) + .def("create_compilation_unit", &dw::Editor::create_compilation_unit, + "Create a new compilation unit"_doc, nb::lock_self() + ) + .def("write", [] (dw::Editor& self, nb::PathLike path) { + self.write(path); + }, + "Write the DWARF file to the specified output"_doc, + "output"_a, nb::lock_self() + ) + ; + +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyFunction.cpp b/vendor/lief/api/python/src/DWARF/pyFunction.cpp new file mode 100644 index 0000000..0dc15f7 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyFunction.cpp @@ -0,0 +1,170 @@ +#include "LIEF/DWARF/DebugInfo.hpp" +#include "LIEF/DWARF/Function.hpp" +#include "LIEF/DWARF/Scope.hpp" +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/Parameter.hpp" +#include "DWARF/pyDwarf.hpp" +#include "pyErr.hpp" + +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ func(m, "Function", + R"doc( + This class represents a DWARF function which can be associated with either: + ``DW_TAG_subprogram`` or ``DW_TAG_inlined_subroutine``. + )doc"_doc + ); + + func + .def_prop_ro("name", &dw::Function::name, + R"doc( + The name of the function (``DW_AT_name``) + )doc"_doc + ) + + .def_prop_ro("linkage_name", &dw::Function::linkage_name, + R"doc( + The name of the function which is used for linking (`DW_AT_linkage_name`). + + This name differs from :attr:`~.name` as it is usually mangled. The function + returns an empty string if the linkage name is not available. + )doc"_doc + ) + + .def_prop_ro("address", + [] (const dw::Function& self) { + return LIEF::py::value_or_none(&dw::Function::address, self); + }, + R"doc( + Return the address of the function (``DW_AT_entry_pc`` or ``DW_AT_low_pc``) or + ``None`` if it's not available. + )doc"_doc + ) + + .def_prop_ro("variables", + [] (dw::Function& self) { + auto vars = LIEF::py::owning_range(self.variables()); + return nb::make_iterator( + nb::type(), "variables_it", vars); + }, nb::keep_alive<0, 1>(), + R"delim( + Return an iterator over the variables (``DW_TAG_variable``) defined within the + scope of this function. This includes regular stack-based variables as + well as static ones. + )delim"_doc + ) + + .def_prop_ro("is_artificial", &dw::Function::is_artificial, + R"doc( + Whether this function is created by the compiler and not + present in the original source code. + )doc"_doc + ) + + .def_prop_ro("is_external", &dw::Function::is_external, + R"doc( + Whether the function is defined **outside** the current compilation unit + (``DW_AT_external``). + )doc"_doc + ) + + .def_prop_ro("size", &dw::Function::size, + R"doc( + Return the size taken by this function in the binary. + )doc"_doc + ) + + .def_prop_ro("ranges", &dw::Function::ranges, + R"doc( + Ranges of virtual addresses owned by this function. + )doc"_doc + ) + + .def_prop_ro("debug_location", &dw::Function::debug_location, + R"doc( + Original source code location. + )doc"_doc + ) + + .def_prop_ro("type", &dw::Function::type, + R"doc( + Return the :class:`~.Type` associated with the **return type** of this + function + )doc"_doc + ) + + .def_prop_ro("parameters", &dw::Function::parameters, + R"doc( + Return the list of parameters used by this function + (including template parameters) + )doc"_doc + ) + + .def_prop_ro("thrown_types", &dw::Function::thrown_types, + R"doc( + List of exceptions (types) that can be thrown by the function. + For instance, given this Swift code: + + .. code-block:: swift + + func summarize(_ ratings: [Int]) throws(StatisticsError) { + // ... + } + + :attr:`~.thrown_types` returns one element associated with the + :class:`~.Type`: ``StatisticsError``. + )doc"_doc + ) + + .def_prop_ro("scope", &dw::Function::scope, + R"doc( + Scope in which this function is defined + )doc"_doc + ) + .def_prop_ro("instructions", + [] (dw::Function& self) { + auto insts = LIEF::py::owning_range(self.instructions()); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, nb::keep_alive<0, 1>(), + R"doc( + Disassemble the current function by returning an iterator over the + :class:`lief.assembly.Instruction`. + )doc"_doc + ) + + .def_prop_ro("lexical_blocks", + [] (dw::Function& self) { + auto lexical_blocks = LIEF::py::owning_range(self.lexical_blocks()); + return nb::make_iterator( + nb::type(), "lexical_blocks_it", lexical_blocks); + }, nb::keep_alive<0, 1>(), + R"delim( + Iterator over the :class:`~.LexicalBlock` owned by this function + )delim"_doc + ) + + .def_prop_ro("description", &dw::Function::description, + "Description (``DW_AT_description``) of this function or an empty string"_doc + ) + + .def("to_decl", + [] (const dw::Function& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for this function"_doc, + "opt"_a.none() = nb::none() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyLexicalBlock.cpp b/vendor/lief/api/python/src/DWARF/pyLexicalBlock.cpp new file mode 100644 index 0000000..143085a --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyLexicalBlock.cpp @@ -0,0 +1,67 @@ +#include "LIEF/DWARF/LexicalBlock.hpp" +#include "DWARF/pyDwarf.hpp" +#include "pyErr.hpp" + +#include +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ LB(m, "LexicalBlock", + R"doc( + This class represents a DWARF lexical block (``DW_TAG_lexical_block``) + )doc"_doc + ); + + LB + .def_prop_ro("name", &dw::LexicalBlock::name, + "Return the *name* associated with this lexical block or an empty string"_doc + ) + + .def_prop_ro("description", &dw::LexicalBlock::description, + "Return the description associated with this lexical block or an empty string"_doc + ) + + .def_prop_ro("sub_blocks", + [] (dw::LexicalBlock& self) { + auto sub_blocks = LIEF::py::owning_range(self.sub_blocks()); + return nb::make_iterator( + nb::type(), "sub_blocks_it", sub_blocks); + }, nb::keep_alive<0, 1>(), + "Return an iterator over the sub-LexicalBlock owned by this block."_doc + ) + .def_prop_ro("addr", &dw::LexicalBlock::addr, + "Return the start address of this block"_doc + ) + + .def_prop_ro("size", &dw::LexicalBlock::size, + R"doc( + Return the size of this block as the difference of the highest address and + the lowest address. + )doc"_doc + ) + .def_prop_ro("low_pc", &dw::LexicalBlock::low_pc, + "Return the lowest virtual address owned by this block."_doc + ) + + .def_prop_ro("high_pc", &dw::LexicalBlock::high_pc, + "Return the highest virtual address owned by this block."_doc + ) + .def_prop_ro("ranges", &dw::LexicalBlock::ranges, + R"doc( + Return a list of address ranges owned by this block. + + If the lexical block owns a contiguous range, it should return + **a single** range. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyParameter.cpp b/vendor/lief/api/python/src/DWARF/pyParameter.cpp new file mode 100644 index 0000000..a2fa523 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyParameter.cpp @@ -0,0 +1,144 @@ +#include "LIEF/DWARF/Parameter.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace nanobind::detail { +template<> struct type_hook { + static const std::type_info* get(const LIEF::dwarf::Parameter::Location *src) { + using Parameter = LIEF::dwarf::Parameter; + if (src) { + if (Parameter::RegisterLoc::classof(src)) { + return &typeid(Parameter::RegisterLoc); + } + } + return &typeid(Parameter::Location); + } +}; +} + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ param(m, "Parameter", + R"doc( + This class represents a DWARF parameter which can be either: + - A regular function parameter (see: :class:`.parameters.Formal`) + - A template type parameter (see: :class:`.parameters.TemplateType`) + - A template value parameter (see: :class:`.parameters.TemplateValue`) + )doc"_doc + ); + + using Location = dw::Parameter::Location; + using RegisterLoc = dw::Parameter::RegisterLoc; + + nb::class_ loc(param, "Location", + R"doc( + This class exposes information about the location of a parameter + )doc"_doc); + + nb::enum_(loc, "Type") + .value("UNKNOWN", Location::Type::UNKNOWN) + .value("REGISTER", Location::Type::REG); + + loc + .def_ro("type", &Location::type); + + nb::class_(param, "RegisterLoc", + R"doc( + This class represents a register location + )doc"_doc) + + .def_ro("id", &RegisterLoc::id, "DWARF id of the register"_doc); + + param + .def_prop_ro("name", &dw::Parameter::name, + R"doc( + Name of the parameter + )doc"_doc + ) + + .def_prop_ro("type", &dw::Parameter::type, + R"doc( + Type of this parameter + )doc"_doc + ) + + .def_prop_ro("location", &dw::Parameter::location, + R"doc( + Location of this parameter. For instance it can be a specific register + that is not following the calling convention. + )doc"_doc + ) + ; + + nb::module_ m_params = m.def_submodule("parameters"); + /* Formal */ { + nb::class_(m_params, "Formal", + R"doc( + This class represents a regular function parameter. + + For instance, given this prototype: + + .. code-block:: cpp + + int main(int argc, const char** argv); + + The function ``main`` has two :class:`.Formal` parameters: + + 1. ``argc`` (:attr:`lief.dwarf.Parameter.name`) typed as ``int`` + (:class:`~lief.dwarf.types.Base` from :attr:`lief.dwarf.Parameter.type`) + 2. ``argv`` (:attr:`lief.dwarf.Parameter.name`) typed as ``const char**`` + (:class:`~lief.dwarf.types.Const`) + )doc"_doc + ) + /* NOT NEEDED but dirty workaround to void stubgen generating this + * kind of error: + * lief/dwarf/parameters.pyi:1: error: Name "lief" is not defined [name-defined] + * + * CAN BE REMOVED if one of these classes are API enhanced + */ + .def_prop_ro("type", &dw::parameters::Formal::type) + ; + } + + /* TemplateValue */ { + nb::class_(m_params, "TemplateValue", + R"doc( + This class represents a template **value** parameter. + + For instance, given this prototype: + + .. code-block:: cpp + + template + void generic(); + + The function ``generic`` has one :class:`.TemplateValue` parameter: ``X`` + )doc"_doc + ); + } + + /* TemplateType */ { + nb::class_(m_params, "TemplateType", + R"doc( + This class represents a template **type** parameter. + + For instance, given this prototype: + + .. code-block:: cpp + + template + void generic(); + + The function ``generic`` has one :class:`.TemplateType` parameter: ``Y`` + )doc"_doc + ); + } + +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyScope.cpp b/vendor/lief/api/python/src/DWARF/pyScope.cpp new file mode 100644 index 0000000..1885ecf --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyScope.cpp @@ -0,0 +1,55 @@ +#include "LIEF/DWARF/Scope.hpp" +#include "DWARF/pyDwarf.hpp" +#include "pyErr.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ scope(m, "Scope", + R"doc( + This class materializes a scope in which :class:`~.dwarf.Function`, + :class:`~.dwarf.Variable`, :class:`~.dwarf.Type`, ... can be defined. + )doc"_doc + ); + + nb::enum_(scope, "TYPE") + .value("UNKNOWN", dw::Scope::TYPE::UNKNOWN) + .value("UNION", dw::Scope::TYPE::UNION) + .value("CLASS", dw::Scope::TYPE::CLASS) + .value("STRUCT", dw::Scope::TYPE::STRUCT) + .value("NAMESPACE", dw::Scope::TYPE::NAMESPACE) + .value("FUNCTION", dw::Scope::TYPE::FUNCTION) + .value("COMPILATION_UNIT", dw::Scope::TYPE::COMPILATION_UNIT) + ; + + scope + .def_prop_ro("name", &dw::Scope::name, + R"doc( + Name of the scope. For instance namespace's name or function's name. + )doc"_doc + ) + + .def_prop_ro("parent", &dw::Scope::parent, + R"doc( + Parent scope (if any). + )doc"_doc + ) + + .def_prop_ro("type", &dw::Scope::type, + R"doc( + The current scope type. + )doc"_doc + ) + + .def("chained", &dw::Scope::chained, + R"doc( + Represent the whole chain of all (parent) scopes using the provided + separator. E.g. ``ns1::ns2::Class1::Struct2::Type``. + )doc"_doc, "sep"_a = "::" + ) + ; +} +} diff --git a/vendor/lief/api/python/src/DWARF/pyType.cpp b/vendor/lief/api/python/src/DWARF/pyType.cpp new file mode 100644 index 0000000..8405280 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyType.cpp @@ -0,0 +1,191 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/Scope.hpp" +#include "DWARF/pyDwarf.hpp" +#include "pyErr.hpp" + +#include "DWARF/pyTypes.hpp" + +#include +#include + +namespace LIEF::dwarf::types { +class ClassLike; +class Pointer; +class Const; +class Base; +class Array; +class Typedef; +class Atomic; +class Coarray; +class Dynamic; +class Enum; +class File; +class Immutable; +class Interface; +class PointerToMember; +class RValueReference; +class Reference; +class Restrict; +class SetTy; +class Shared; +class StringTy; +class Subroutine; +class TemplateAlias; +class Thrown; +class Volatile; +} + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::module_ types = m.def_submodule("types", "DWARF Types"_doc); + + nb::class_ type(m, "Type", + R"doc( + This class represents a DWARF Type which includes: + + - ``DW_TAG_array_type`` + - ``DW_TAG_const_type`` + - ``DW_TAG_pointer_type`` + - ``DW_TAG_structure_type`` + - ``DW_TAG_base_type`` + - ``DW_TAG_class_type`` + - ``DW_TAG_enumeration_type`` + - ``DW_TAG_string_type`` + - ``DW_TAG_union_type`` + - ``DW_TAG_volatile_type`` + - ``DW_TAG_unspecified_type`` + - ``DW_TAG_typedef`` + - ``DW_TAG_reference_type`` + - ``DW_TAG_subroutine_type`` + - ``DW_TAG_ptr_to_member_type`` + - ``DW_TAG_set_type`` + - ``DW_TAG_packed_type`` + - ``DW_TAG_file_type`` + - ``DW_TAG_thrown_type`` + - ``DW_TAG_restrict_type`` + - ``DW_TAG_interface_type`` + - ``DW_TAG_shared_type`` + - ``DW_TAG_rvalue_reference_type`` + - ``DW_TAG_template_alias`` + - ``DW_TAG_coarray_type`` + - ``DW_TAG_dynamic_type`` + - ``DW_TAG_atomic_type`` + - ``DW_TAG_immutable_type`` + + )doc"_doc + ); + + nb::enum_(type, "KIND") + .value("UNKNOWN", Type::KIND::UNKNOWN) + .value("UNSPECIFIED", Type::KIND::UNSPECIFIED) + .value("BASE", Type::KIND::BASE) + .value("CONST_KIND", Type::KIND::CONST_KIND) + .value("CLASS", Type::KIND::CLASS) + .value("ARRAY", Type::KIND::ARRAY) + .value("POINTER", Type::KIND::POINTER) + .value("STRUCT", Type::KIND::STRUCT) + .value("UNION", Type::KIND::UNION) + .value("TYPEDEF", Type::KIND::TYPEDEF) + .value("REF", Type::KIND::REF) + .value("SET_TYPE", Type::KIND::SET_TYPE) + .value("STRING", Type::KIND::STRING) + .value("SUBROUTINE", Type::KIND::SUBROUTINE) + .value("POINTER_MEMBER", Type::KIND::POINTER_MEMBER) + .value("PACKED", Type::KIND::PACKED) + .value("FILE", Type::KIND::FILE) + .value("THROWN", Type::KIND::THROWN) + .value("VOLATILE", Type::KIND::VOLATILE) + .value("RESTRICT", Type::KIND::RESTRICT) + .value("INTERFACE", Type::KIND::INTERFACE) + .value("SHARED", Type::KIND::SHARED) + .value("RVALREF", Type::KIND::RVALREF) + .value("TEMPLATE_ALIAS", Type::KIND::TEMPLATE_ALIAS) + .value("COARRAY", Type::KIND::COARRAY) + .value("DYNAMIC", Type::KIND::DYNAMIC) + .value("ATOMIC", Type::KIND::ATOMIC) + .value("IMMUTABLE", Type::KIND::IMMUTABLE) + .value("ENUM", Type::KIND::ENUM) + ; + type + .def_prop_ro("kind", &dw::Type::kind, + R"doc( + Discriminator for the type's subclasses + )doc"_doc + ) + .def_prop_ro("name", + [] (const dw::Type& self) { + return LIEF::py::value_or_none(&dw::Type::name, self); + }, + R"doc( + Return the type's name or ``None`` if it can't be resolved. + + The name is resolved using either ``DW_AT_name`` or ``DW_AT_picture_string``. + )doc"_doc + ) + + .def_prop_ro("size", + [] (const dw::Type& self) { + return LIEF::py::value_or_none(&dw::Type::size, self); + }, + R"doc( + Return the size of the type or ``None`` if it can't be computed. + + This size should match the equivalent of ``sizeof(Type)``. + )doc"_doc + ) + + .def_prop_ro("location", &dw::Type::location, + R"doc( + Return the debug location where this type is defined. + )doc"_doc + ) + + .def_prop_ro("is_unspecified", &dw::Type::is_unspecified, + R"doc( + Whether this type is a ``DW_TAG_unspecified_type`` + )doc"_doc + ) + + .def_prop_ro("scope", &dw::Type::scope, + R"doc( + Scope in which this type is defined + )doc"_doc + ) + + .def("to_decl", + [] (const dw::Type& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for this type"_doc, + "opt"_a.none() = nb::none() + ); + ; + + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/pyTypes.hpp b/vendor/lief/api/python/src/DWARF/pyTypes.hpp new file mode 100644 index 0000000..7c669f2 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyTypes.hpp @@ -0,0 +1,147 @@ +#pragma once + +#include +#include "LIEF/DWARF/types/Base.hpp" +#include "LIEF/DWARF/types/Array.hpp" +#include "LIEF/DWARF/types/ClassLike.hpp" +#include "LIEF/DWARF/types/Pointer.hpp" +#include "LIEF/DWARF/types/Const.hpp" + + +#include "LIEF/DWARF/types/Typedef.hpp" +#include "LIEF/DWARF/types/Atomic.hpp" +#include "LIEF/DWARF/types/Coarray.hpp" +#include "LIEF/DWARF/types/Dynamic.hpp" +#include "LIEF/DWARF/types/File.hpp" +#include "LIEF/DWARF/types/Immutable.hpp" +#include "LIEF/DWARF/types/Interface.hpp" +#include "LIEF/DWARF/types/PointerToMember.hpp" +#include "LIEF/DWARF/types/RValueRef.hpp" +#include "LIEF/DWARF/types/Reference.hpp" +#include "LIEF/DWARF/types/Restrict.hpp" +#include "LIEF/DWARF/types/SetTy.hpp" +#include "LIEF/DWARF/types/Shared.hpp" +#include "LIEF/DWARF/types/StringTy.hpp" +#include "LIEF/DWARF/types/Subroutine.hpp" +#include "LIEF/DWARF/types/TemplateAlias.hpp" +#include "LIEF/DWARF/types/Thrown.hpp" +#include "LIEF/DWARF/types/Volatile.hpp" +#include "LIEF/DWARF/types/Enum.hpp" + +namespace nanobind::detail { +template<> struct type_hook { + static const std::type_info* get(const LIEF::dwarf::Type *src) { + using namespace LIEF::dwarf::types; + if (src) { + if (Base::classof(src)) { + return &typeid(Base); + } + + if (Array::classof(src)) { + return &typeid(Array); + } + + if (Const::classof(src)) { + return &typeid(Const); + } + + if (Pointer::classof(src)) { + return &typeid(Pointer); + } + + if (Structure::classof(src)) { + return &typeid(Structure); + } + + if (Class::classof(src)) { + return &typeid(Class); + } + + if (Union::classof(src)) { + return &typeid(Union); + } + + if (Packed::classof(src)) { + return &typeid(Packed); + } + + if (Typedef::classof(src)) { + return &typeid(Typedef); + } + + if (Atomic::classof(src)) { + return &typeid(Atomic); + } + + if (Coarray::classof(src)) { + return &typeid(Coarray); + } + + if (Dynamic::classof(src)) { + return &typeid(Dynamic); + } + + if (File::classof(src)) { + return &typeid(File); + } + + if (Immutable::classof(src)) { + return &typeid(Immutable); + } + + if (Interface::classof(src)) { + return &typeid(Interface); + } + + if (PointerToMember::classof(src)) { + return &typeid(PointerToMember); + } + + if (RValueReference::classof(src)) { + return &typeid(RValueReference); + } + + if (Reference::classof(src)) { + return &typeid(Reference); + } + + if (Restrict::classof(src)) { + return &typeid(Restrict); + } + + if (SetTy::classof(src)) { + return &typeid(SetTy); + } + + if (Shared::classof(src)) { + return &typeid(Shared); + } + + if (StringTy::classof(src)) { + return &typeid(StringTy); + } + + if (Subroutine::classof(src)) { + return &typeid(Subroutine); + } + + if (TemplateAlias::classof(src)) { + return &typeid(TemplateAlias); + } + + if (Thrown::classof(src)) { + return &typeid(Thrown); + } + + if (Volatile::classof(src)) { + return &typeid(Volatile); + } + + if (Enum::classof(src)) { + return &typeid(Enum); + } + } + return &typeid(LIEF::dwarf::Type); + } +}; +} diff --git a/vendor/lief/api/python/src/DWARF/pyVariable.cpp b/vendor/lief/api/python/src/DWARF/pyVariable.cpp new file mode 100644 index 0000000..b5da30d --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/pyVariable.cpp @@ -0,0 +1,105 @@ +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/DWARF/Scope.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "DWARF/pyDwarf.hpp" +#include "pyErr.hpp" +#include "DWARF/pyTypes.hpp" + + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ var(m, "Variable", + R"doc( + This class represents a DWARF variable which can be owned by a + :class:`~.Function` or a :class:`~.CompilationUnit`. + )doc"_doc + ); + + var + .def_prop_ro("name", &dw::Variable::name, + R"doc( + Name of the variable (usually demangled) + )doc"_doc + ) + .def_prop_ro("linkage_name", &dw::Variable::linkage_name, + R"doc( + The name of the variable which is used for linking (``DW_AT_linkage_name``). + + This name differs from :attr:`~.name` as it is usually mangled. The function + returns an empty string if the linkage name is not available. + )doc"_doc + ) + .def_prop_ro("address", + [] (const dw::Variable& self) { + return LIEF::py::value_or_none(&dw::Variable::address, self); + }, + R"doc( + Address of the variable. + + If the variable is **static**, it returns the **virtual address** + where it is defined. + If the variable is stack-based, it returns the **relative offset** from + the frame-base register. + + If the address can't be resolved, it returns ``None``. + )doc"_doc + ) + .def_prop_ro("size", + [] (const dw::Variable& self) { + return LIEF::py::value_or_none(&dw::Variable::size, self); + }, + R"doc( + Return the size of the variable (or a lief_errors if it can't be + resolved). + + This size is defined by the type of the variable. + )doc"_doc + ) + .def_prop_ro("is_constexpr", + &dw::Variable::is_constexpr, + R"doc( + Whether it's a ``constexpr`` variable. + )doc"_doc + ) + .def_prop_ro("is_stack_based", + &dw::Variable::is_stack_based, + "Whether this variable is allocated on the stack"_doc + ) + .def_prop_ro("debug_location", + &dw::Variable::debug_location, + R"doc( + The original source location where the variable is defined. + )doc"_doc + ) + .def_prop_ro("type", &dw::Variable::type, + R"doc( + Return the type of this variable. + )doc"_doc + ) + .def_prop_ro("scope", &dw::Variable::scope, + R"doc( + Scope in which this variable is defined + )doc"_doc + ) + + .def_prop_ro("description", &dw::Variable::description, + R"doc( + Description (``DW_AT_description``) of the variable or an empty string. + )doc"_doc + ) + + .def("to_decl", + [] (const dw::Variable& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for this variable"_doc, + "opt"_a.none() = nb::none() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/CMakeLists.txt b/vendor/lief/api/python/src/DWARF/types/CMakeLists.txt new file mode 100644 index 0000000..4673b88 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/CMakeLists.txt @@ -0,0 +1,26 @@ +target_sources(pyLIEF PRIVATE + pyClassLike.cpp + pyPointer.cpp + pyConst.cpp + pyBase.cpp + pyArray.cpp + pyTypedef.cpp + pyAtomic.cpp + pyCoarray.cpp + pyDynamic.cpp + pyEnum.cpp + pyFile.cpp + pyImmutable.cpp + pyInterface.cpp + pyPointerToMember.cpp + pyRValueRef.cpp + pyReference.cpp + pyRestrict.cpp + pySetTy.cpp + pyShared.cpp + pyStringTy.cpp + pySubroutine.cpp + pyTemplateAlias.cpp + pyThrown.cpp + pyVolatile.cpp +) diff --git a/vendor/lief/api/python/src/DWARF/types/pyArray.cpp b/vendor/lief/api/python/src/DWARF/types/pyArray.cpp new file mode 100644 index 0000000..bc884b8 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyArray.cpp @@ -0,0 +1,60 @@ +#include "LIEF/DWARF/types/Array.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Array", + R"doc( + This class represents a ``DW_TAG_array_type`` + )doc"_doc + ); + + nb::class_(type, "size_info_t", + R"doc( + Class that wraps information about the dimension of this array + )doc"_doc + ) + .def_prop_ro("type", [] (dw::types::Array::size_info_t& self) { + return self.type.get(); + }, + R"doc( + Type of the **index** for this array. + + For instance in ``uint8_t[3]`` the index type could be set to a ``size_t``. + )doc"_doc, nb::keep_alive<0, 1>() + ) + .def_ro("name", &dw::types::Array::size_info_t::name, + R"doc( + Name of the index (usually not relevant like ``__ARRAY_SIZE_TYPE__``) + )doc"_doc + ) + .def_ro("size", &dw::types::Array::size_info_t::size, + R"doc( + Size of the array. For instance in ``uint8_t[3]``, it returns 3. + )doc"_doc + ) + ; + + type + .def_prop_ro("underlying_type", &dw::types::Array::underlying_type, + R"doc( + The underlying type of this array. + )doc"_doc + ) + + .def_prop_ro("size_info", &dw::types::Array::size_info, + R"doc( + Return information about the size of this array. + + This size info is usually embedded in a ``DW_TAG_subrange_type`` DIE which + is represented by the :class:`.Array.size_info_t` class. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyAtomic.cpp b/vendor/lief/api/python/src/DWARF/types/pyAtomic.cpp new file mode 100644 index 0000000..efee84b --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyAtomic.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Atomic.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Atomic", + R"doc( + This class represents the ``DW_TAG_atomic_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Atomic::underlying_type, + R"doc( + The underlying type being atomized by this type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyBase.cpp b/vendor/lief/api/python/src/DWARF/types/pyBase.cpp new file mode 100644 index 0000000..335fcbd --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyBase.cpp @@ -0,0 +1,34 @@ +#include "LIEF/DWARF/types/Base.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Base", + R"doc( + This class wraps the ``DW_TAG_base_type`` type which can be used -- for + instance -- to represent integers or primitive types. + )doc"_doc + ); + + nb::enum_(type, "ENCODING") + .value("NONE", dw::types::Base::ENCODING::NONE) + .value("SIGNED", dw::types::Base::ENCODING::SIGNED, "Mirror ``DW_ATE_signed``"_doc) + .value("SIGNED_CHAR", dw::types::Base::ENCODING::SIGNED_CHAR, "Mirror ``DW_ATE_signed_char``"_doc) + .value("UNSIGNED", dw::types::Base::ENCODING::UNSIGNED, "Mirror ``DW_ATE_unsigned``"_doc) + .value("UNSIGNED_CHAR", dw::types::Base::ENCODING::UNSIGNED_CHAR, "Mirror ``DW_ATE_unsigned_char``"_doc) + .value("FLOAT", dw::types::Base::ENCODING::FLOAT, "Mirror ``DW_ATE_float``"_doc) + .value("BOOLEAN", dw::types::Base::ENCODING::BOOLEAN, "Mirror ``DW_ATE_boolean``"_doc) + .value("ADDRESS", dw::types::Base::ENCODING::ADDRESS, "Mirror ``DW_ATE_address``"_doc) + ; + + type + .def_prop_ro("encoding", &dw::types::Base::encoding, + R"doc( + Describe how the base type is encoded and should be interpreted. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyClassLike.cpp b/vendor/lief/api/python/src/DWARF/types/pyClassLike.cpp new file mode 100644 index 0000000..a285edd --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyClassLike.cpp @@ -0,0 +1,141 @@ +#include "LIEF/DWARF/types/ClassLike.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +#include "pyErr.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ class_like(m, "ClassLike", + R"doc( + This class abstracts a DWARF aggregate (``DW_TAG_structure_type``, + ``DW_TAG_class_type``, ``DW_TAG_union_type``). + )doc"_doc + ); + + nb::class_(class_like, "Member", + R"doc( + This class represents a class/struct/union attribute. + )doc"_doc + ) + .def_prop_ro("name", &dw::types::ClassLike::Member::name, + R"doc( + Name of the member + )doc"_doc + ) + + .def_prop_ro("type", &dw::types::ClassLike::Member::type, + R"doc( + Type of the current member + )doc"_doc + ) + + .def_prop_ro("is_external", &dw::types::ClassLike::Member::is_external, + R"doc( + )doc"_doc + ) + + .def_prop_ro("is_declaration", &dw::types::ClassLike::Member::is_declaration, + R"doc( + )doc"_doc + ) + + .def_prop_ro("offset", + [] (const dw::types::ClassLike::Member& self) { + return LIEF::py::value_or_none(&dw::types::ClassLike::Member::offset, self); + }, + R"doc( + Offset of the current member in the struct/union/class + + If the offset can't be resolved it returns None + )doc"_doc + ) + .def_prop_ro("bit_offset", + [] (const dw::types::ClassLike::Member& self) { + return LIEF::py::value_or_none(&dw::types::ClassLike::Member::bit_offset, self); + }, + R"doc( + Offset of the current member in **bits** in the current struct/union/class + + This function differs from :attr:`~.offset` for aggregates using bit-field + declaration: + + .. code-block:: cpp + + struct S { + int flag : 4; + int opt : 1 + }; + + Usually, ``offset * 8 == bit_offset`` + + If the offset can't be resolved it returns None + )doc"_doc + ) + + .def_prop_ro("bit_size", + [] (const dw::types::ClassLike::Member& self) { + return LIEF::py::value_or_none(&dw::types::ClassLike::Member::bit_size, self); + }, + R"doc( + If the current member is a bit-field, this function returns its size in bits. + )doc"_doc + ) + ; + + class_like + .def_prop_ro("members", &dw::types::ClassLike::members, + R"doc( + Return a list of all the members defined in this class-like type. + )doc"_doc + ) + .def("find_member", &dw::types::ClassLike::find_member, + R"doc( + Try to find the attribute at the given offset + )doc"_doc, "offset"_a + ) + .def_prop_ro("functions", + [] (dw::types::ClassLike& self) { + auto funcs = LIEF::py::owning_range(self.functions()); + return nb::make_iterator( + nb::type(), "functions_it", funcs + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the functions defined by the class-like.)doc"_doc + ) + ; + + nb::class_ Struct(m, "Structure", + R"doc( + This class represents a DWARF ``struct`` type (``DW_TAG_structure_type``) + )doc"_doc + ); + + nb::class_ Class(m, "Class", + R"doc( + This class represents a DWARF ``class`` type (``DW_TAG_class_type``) + )doc"_doc + ); + + nb::class_ Union(m, "Union", + R"doc( + This class represents a DWARF ``union`` type (``DW_TAG_union_type``) + )doc"_doc + ); + + + nb::class_ Packed(m, "Packed", + R"doc( + This class represents a DWARF ``packed`` type (``DW_TAG_packed_type``) + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyCoarray.cpp b/vendor/lief/api/python/src/DWARF/types/pyCoarray.cpp new file mode 100644 index 0000000..a0cc3eb --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyCoarray.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Coarray.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Coarray", + R"doc( + This class represents the ``DW_TAG_coarray_type`` type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyConst.cpp b/vendor/lief/api/python/src/DWARF/types/pyConst.cpp new file mode 100644 index 0000000..59fb410 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyConst.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Const.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Const", + R"doc( + This class represents a ``DW_TAG_const_type`` modifier + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Const::underlying_type, + R"doc( + The underlying type being const-ed by this type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyDynamic.cpp b/vendor/lief/api/python/src/DWARF/types/pyDynamic.cpp new file mode 100644 index 0000000..5863441 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyDynamic.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Dynamic.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Dynamic", + R"doc( + This class represents the ``DW_TAG_dynamic_type`` type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyEnum.cpp b/vendor/lief/api/python/src/DWARF/types/pyEnum.cpp new file mode 100644 index 0000000..8148eba --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyEnum.cpp @@ -0,0 +1,52 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Enum.hpp" +#include "DWARF/pyDwarf.hpp" + +#include + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + using Enum = dw::types::Enum; + nb::class_ type(m, "Enum", + R"doc( + This class represents the ``DW_TAG_enumeration_type`` type + )doc"_doc + ); + + nb::class_(type, "Entry", + R"doc( + This class represents an enum entry which is essentially composed of a + name and its value (integer). + )doc"_doc + ) + .def_prop_ro("name", &Enum::Entry::name, + "Enum entry's name"_doc + ) + + .def_prop_ro("value", &Enum::Entry::value, + "Enum entry's value"_doc + ) + ; + + type + .def_prop_ro("entries", &Enum::entries, + "Entries associated with this enum"_doc + ) + + .def_prop_ro("underlying_type", &Enum::underlying_type, + "The underlying type that is used to encode this enum"_doc, + nb::rv_policy::reference_internal + ) + + .def("find_entry", &Enum::find_entry, + "Try to find the entry matching the given value"_doc, + "value"_a + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyFile.cpp b/vendor/lief/api/python/src/DWARF/types/pyFile.cpp new file mode 100644 index 0000000..489e9c7 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyFile.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/File.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "File", + R"doc( + This class represents the ``DW_TAG_file_type`` type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyImmutable.cpp b/vendor/lief/api/python/src/DWARF/types/pyImmutable.cpp new file mode 100644 index 0000000..eef1ca0 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyImmutable.cpp @@ -0,0 +1,24 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Immutable.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Immutable", + R"doc( + This class represents the ``DW_TAG_immutable_type`` type + )doc"_doc + ); + + + type + .def_prop_ro("underlying_type", &dw::types::Immutable::underlying_type, + R"doc( + The underlying type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyInterface.cpp b/vendor/lief/api/python/src/DWARF/types/pyInterface.cpp new file mode 100644 index 0000000..f55cbc9 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyInterface.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Interface.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Interface", + R"doc( + This class represents the ``DW_TAG_interface_type`` type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyPointer.cpp b/vendor/lief/api/python/src/DWARF/types/pyPointer.cpp new file mode 100644 index 0000000..f070c74 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyPointer.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/types/Pointer.hpp" +#include "DWARF/pyDwarf.hpp" +#include "DWARF/pyTypes.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Pointer", + R"doc( + This class represents a ``DW_TAG_pointer_type`` DWARF type. + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Pointer::underlying_type, + R"doc( + The type pointed by this pointer + )doc"_doc, nb::rv_policy::reference_internal + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyPointerToMember.cpp b/vendor/lief/api/python/src/DWARF/types/pyPointerToMember.cpp new file mode 100644 index 0000000..66c92b8 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyPointerToMember.cpp @@ -0,0 +1,30 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/PointerToMember.hpp" +#include "DWARF/pyDwarf.hpp" + +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "PointerToMember", + R"doc( + This class represents the ``DW_TAG_ptr_to_member_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::PointerToMember::underlying_type, + R"doc( + The type of the member referenced by this pointer. + )doc"_doc + ) + .def_prop_ro("containing_type", &dw::types::PointerToMember::containing_type, + R"doc( + The type that embeds this member. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyRValueRef.cpp b/vendor/lief/api/python/src/DWARF/types/pyRValueRef.cpp new file mode 100644 index 0000000..1779eab --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyRValueRef.cpp @@ -0,0 +1,24 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/RValueRef.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "RValueReference", + R"doc( + This class represents the ``DW_TAG_rvalue_reference_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::RValueReference::underlying_type, + R"doc( + The underlying type referenced by this rvalue-type. + )doc"_doc + ) + + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyReference.cpp b/vendor/lief/api/python/src/DWARF/types/pyReference.cpp new file mode 100644 index 0000000..ccf994b --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyReference.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Reference.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Reference", + R"doc( + This class represents the ``DW_TAG_reference_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Reference::underlying_type, + R"doc( + The underlying type referenced by this ref-type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyRestrict.cpp b/vendor/lief/api/python/src/DWARF/types/pyRestrict.cpp new file mode 100644 index 0000000..fdeba04 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyRestrict.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Restrict.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Restrict", + R"doc( + This class represents the ``DW_TAG_restrict_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Restrict::underlying_type, + R"doc( + The underlying type referenced by this restrict-type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pySetTy.cpp b/vendor/lief/api/python/src/DWARF/types/pySetTy.cpp new file mode 100644 index 0000000..771df87 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pySetTy.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/SetTy.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "SetTy", + R"doc( + This class represents the ``DW_TAG_set_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::SetTy::underlying_type, + R"doc( + The underlying type referenced by this set-type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyShared.cpp b/vendor/lief/api/python/src/DWARF/types/pyShared.cpp new file mode 100644 index 0000000..d888099 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyShared.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Shared.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Shared", + R"doc( + This class represents the ``DW_TAG_shared_type`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Shared::underlying_type, + R"doc( + The underlying type referenced by this shared-type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyStringTy.cpp b/vendor/lief/api/python/src/DWARF/types/pyStringTy.cpp new file mode 100644 index 0000000..e1c8a27 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyStringTy.cpp @@ -0,0 +1,15 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/StringTy.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "StringTy", + R"doc( + This class represents the ``DW_TAG_string_type`` type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pySubroutine.cpp b/vendor/lief/api/python/src/DWARF/types/pySubroutine.cpp new file mode 100644 index 0000000..0adca82 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pySubroutine.cpp @@ -0,0 +1,33 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Subroutine.hpp" +#include "LIEF/DWARF/Parameter.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Subroutine", + R"doc( + This class represents the ``DW_TAG_subroutine_type`` type + )doc"_doc + ); + + type + .def_prop_ro("return_type", &dw::types::Subroutine::return_type, + R"doc( + Return the :class:`~.dwarf.Type` associated with the **return type** of this + function + )doc"_doc + ) + .def_prop_ro("parameters", &dw::types::Subroutine::parameters, + R"doc( + Parameters of this subroutine + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyTemplateAlias.cpp b/vendor/lief/api/python/src/DWARF/types/pyTemplateAlias.cpp new file mode 100644 index 0000000..5a479a3 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyTemplateAlias.cpp @@ -0,0 +1,33 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/TemplateAlias.hpp" +#include "LIEF/DWARF/Parameter.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "TemplateAlias", + R"doc( + This class represents the ``DW_TAG_template_alias`` type + )doc"_doc + ); + + type + .def_prop_ro("parameters", &dw::types::TemplateAlias::parameters, + R"doc( + Parameters associated with the underlying template + )doc"_doc + ) + + .def_prop_ro("underlying_type", &dw::types::TemplateAlias::underlying_type, + R"doc( + The underlying type aliased by this type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyThrown.cpp b/vendor/lief/api/python/src/DWARF/types/pyThrown.cpp new file mode 100644 index 0000000..93933c5 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyThrown.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Thrown.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Thrown", + R"doc( + This class represents a ``DW_TAG_thrown_type`` + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Thrown::underlying_type, + R"doc( + The underlying type being thrown + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyTypedef.cpp b/vendor/lief/api/python/src/DWARF/types/pyTypedef.cpp new file mode 100644 index 0000000..2688e0b --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyTypedef.cpp @@ -0,0 +1,26 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Typedef.hpp" +#include "DWARF/pyDwarf.hpp" + +#include +#include + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Typedef", + R"doc( + This class represents a ``DW_TAG_typedef`` type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Typedef::underlying_type, + R"doc( + The type aliased by this typedef + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DWARF/types/pyVolatile.cpp b/vendor/lief/api/python/src/DWARF/types/pyVolatile.cpp new file mode 100644 index 0000000..cd1b0b8 --- /dev/null +++ b/vendor/lief/api/python/src/DWARF/types/pyVolatile.cpp @@ -0,0 +1,23 @@ +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/types/Volatile.hpp" +#include "DWARF/pyDwarf.hpp" + +namespace LIEF::dwarf::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Volatile", + R"doc( + This class represents a ``DW_TAG_volatile_type`` + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &dw::types::Volatile::underlying_type, + R"doc( + The underlying type. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/CMakeLists.txt b/vendor/lief/api/python/src/DyldSharedCache/CMakeLists.txt new file mode 100644 index 0000000..3c65999 --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyDyldSharedCache.cpp + pyDylib.cpp + pyMappingInfo.cpp + pySubCache.cpp + pyUtils.cpp +) + diff --git a/vendor/lief/api/python/src/DyldSharedCache/init.cpp b/vendor/lief/api/python/src/DyldSharedCache/init.cpp new file mode 100644 index 0000000..104cf96 --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/init.cpp @@ -0,0 +1,63 @@ +#include "DyldSharedCache/init.hpp" +#include "DyldSharedCache/pyDyldSharedCache.hpp" +#include "LIEF/DyldSharedCache/caching.hpp" + +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::dsc { +class DyldSharedCache; +class Dylib; +class SubCache; +class MappingInfo; +} + +namespace LIEF::dsc::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("dsc"); + init_utils(m); + + mod.def("enable_cache", nb::overload_cast<>(&enable_cache), + R"doc( + Enable globally cache/memoization. One can also leverage this function + by setting the environment variable ``DYLDSC_ENABLE_CACHE`` to ``1`` + + By default, LIEF will use the directory specified by the environment + variable ``DYLDSC_CACHE_DIR`` as its cache-root directory: + + .. code-block:: console + + DYLDSC_ENABLE_CACHE=1 DYLDSC_CACHE_DIR=/tmp/my_dir python ./my-script.py + + Otherwise, if ``DYLDSC_CACHE_DIR`` is not set, LIEF will use the following + directory (in this priority): + + 1. System or user cache directory + + - macOS: ``DARWIN_USER_TEMP_DIR`` / ``DARWIN_USER_CACHE_DIR`` + ``/dyld_shared_cache`` + - Linux: ``${XDG_CACHE_HOME}/dyld_shared_cache`` + - Windows: ``%LOCALAPPDATA%\dyld_shared_cache`` + + 2. Home directory + + - macOS/Linux: ``$HOME/.dyld_shared_cache`` + - Windows: ``%USERPROFILE%\.dyld_shared_cache`` + + See :meth:`lief.dsc.DyldSharedCache.enable_caching` for a finer granularity + )doc"_doc + ); + + mod.def("enable_cache", [] (nb::PathLike path) { return enable_cache(path); }, + R"doc( + Same behavior as the other :meth:`~.enable_cache` function but using a + user-provided cache directory instead of an inferred one. + )doc"_doc, "target_cache_dir"_a + ); + + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/init.hpp b/vendor/lief/api/python/src/DyldSharedCache/init.hpp new file mode 100644 index 0000000..0cc4b7f --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/init.hpp @@ -0,0 +1,9 @@ +#ifndef PY_LIEF_DSC_INIT_H +#define PY_LIEF_DSC_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::dsc::py { +void init(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.cpp b/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.cpp new file mode 100644 index 0000000..af4f99d --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.cpp @@ -0,0 +1,318 @@ +#include "LIEF/DyldSharedCache/DyldSharedCache.hpp" +#include "DyldSharedCache/pyDyldSharedCache.hpp" + +#include +#include +#include +#include +#include + +#include "nanobind/extra/random_access_iterator.hpp" +#include "nanobind/utils.hpp" + +#include "typing.hpp" +#include "pyutils.hpp" +#include "pyErr.hpp" + +#include "pyOwningIterator.hpp" + +namespace LIEF::dsc::py { +template<> +void create(nb::module_& m) { + nb::class_ cache(m, "DyldSharedCache", + R"doc( + This class represents a dyld shared cache file. + )doc"_doc + ); + + nb::enum_(cache, "VERSION") + .value("UNKNOWN", dsc::DyldSharedCache::VERSION::UNKNOWN) + .value("DYLD_95_3", dsc::DyldSharedCache::VERSION::DYLD_95_3, + "dyld-95.3 (2007-10-30)"_doc) + .value("DYLD_195_5", dsc::DyldSharedCache::VERSION::DYLD_195_5, + "dyld-195.5 (2011-07-13)"_doc) + .value("DYLD_239_3", dsc::DyldSharedCache::VERSION::DYLD_239_3, + "dyld-239.3 (2013-10-29)"_doc) + .value("DYLD_360_14", dsc::DyldSharedCache::VERSION::DYLD_360_14, + "dyld-360.14 (2015-09-04)"_doc) + .value("DYLD_421_1", dsc::DyldSharedCache::VERSION::DYLD_421_1, + "dyld-421.1 (2016-09-22)"_doc) + .value("DYLD_832_7_1", dsc::DyldSharedCache::VERSION::DYLD_832_7_1, + "dyld-832.7.1 (2020-11-19)"_doc) + .value("DYLD_940", dsc::DyldSharedCache::VERSION::DYLD_940, + "dyld-940 (2021-02-09)"_doc) + .value("DYLD_1042_1", dsc::DyldSharedCache::VERSION::DYLD_1042_1, + "dyld-1042.1 (2022-10-19)"_doc) + .value("DYLD_1231_3", dsc::DyldSharedCache::VERSION::DYLD_1231_3, + "dyld-1231.3 (2024-09-24)"_doc) + .value("DYLD_1284_13", dsc::DyldSharedCache::VERSION::DYLD_1284_13, + "dyld-1284.4 (2025-04-25)"_doc) + .value("UNRELEASED", dsc::DyldSharedCache::VERSION::UNRELEASED, + R"doc( + This value is used for versions of dyld not publicly released or + not yet supported by LIEF. + )doc"_doc) + ; + + + nb::enum_(cache, "PLATFORM", + R"doc(Platforms supported by the dyld shared cache)doc"_doc + ) + .value("UNKNOWN", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::UNKNOWN) + .value("MACOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::MACOS) + .value("IOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::IOS) + .value("TVOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::TVOS) + .value("WATCHOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::WATCHOS) + .value("BRIDGEOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::BRIDGEOS) + .value("IOSMAC", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::IOSMAC) + .value("IOS_SIMULATOR", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::IOS_SIMULATOR) + .value("TVOS_SIMULATOR", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::TVOS_SIMULATOR) + .value("WATCHOS_SIMULATOR", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::WATCHOS_SIMULATOR) + .value("DRIVERKIT", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::DRIVERKIT) + .value("VISIONOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::VISIONOS) + .value("VISIONOS_SIMULATOR", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::VISIONOS_SIMULATOR) + .value("FIRMWARE", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::FIRMWARE) + .value("SEPOS", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::SEPOS) + .value("ANY", dsc::DyldSharedCache::DYLD_TARGET_PLATFORM::ANY) + ; + + nb::enum_(cache, "ARCH", + R"doc(Architecture supported by the dyld shared cache)doc"_doc + ) + .value("UNKNOWN", dsc::DyldSharedCache::DYLD_TARGET_ARCH::UNKNOWN) + .value("I386", dsc::DyldSharedCache::DYLD_TARGET_ARCH::I386) + .value("X86_64", dsc::DyldSharedCache::DYLD_TARGET_ARCH::X86_64) + .value("X86_64H", dsc::DyldSharedCache::DYLD_TARGET_ARCH::X86_64H) + .value("ARMV5", dsc::DyldSharedCache::DYLD_TARGET_ARCH::ARMV5) + .value("ARMV6", dsc::DyldSharedCache::DYLD_TARGET_ARCH::ARMV6) + .value("ARMV7", dsc::DyldSharedCache::DYLD_TARGET_ARCH::ARMV7) + .value("ARM64", dsc::DyldSharedCache::DYLD_TARGET_ARCH::ARM64) + .value("ARM64E", dsc::DyldSharedCache::DYLD_TARGET_ARCH::ARM64E) + ; + + cache + .def_static("from_path", &dsc::DyldSharedCache::from_path, + R"doc( + See: :meth:`lief.dsc.load` for the details + )doc"_doc, "path"_a, "arch"_a = "" + ) + .def_static("from_files", &dsc::DyldSharedCache::from_files, + R"doc( + See: :meth:`lief.dsc.load` for the details + )doc"_doc, "files"_a + ) + .def_prop_ro("filename", &dsc::DyldSharedCache::filename, + R"doc( + Filename of the dyld shared file associated with this object. + + For instance: ``dyld_shared_cache_arm64e, dyld_shared_cache_arm64e.62.dyldlinkedit`` + )doc"_doc + ) + .def_prop_ro("version", &dsc::DyldSharedCache::version, + R"doc( + Version of dyld used by this cache + )doc"_doc + ) + .def_prop_ro("filepath", &dsc::DyldSharedCache::filepath, + R"doc( + Full path to the original dyld shared cache file associated with object + (e.g. ``/cache/visionos/dyld_shared_cache_arm64e.42``) + )doc"_doc + ) + .def_prop_ro("load_address", &dsc::DyldSharedCache::load_address, + R"doc(Base address of this cache)doc"_doc + ) + .def_prop_ro("arch_name", &dsc::DyldSharedCache::arch_name, + R"doc(Name of the architecture targeted by this cache (``x86_64h``))doc"_doc + ) + .def_prop_ro("platform", &dsc::DyldSharedCache::platform, + R"doc(Platform targeted by this cache (e.g. vision-os))doc"_doc + ) + .def_prop_ro("arch", &dsc::DyldSharedCache::arch, + R"doc(Architecture targeted by this cache)doc"_doc + ) + .def_prop_ro("has_subcaches", &dsc::DyldSharedCache::has_subcaches, + R"doc(True if the subcaches are associated with this cache)doc"_doc + ) + .def("find_lib_from_va", &dsc::DyldSharedCache::find_lib_from_va, + R"doc( + Find the :class:`lief.dsc.Dylib` that encompasses the given virtual address. + It returns ``None`` if a Dylib can't be found. + )doc", "virtual_address"_a, + nb::keep_alive<0, 1>() + ) + .def("find_lib_from_path", &dsc::DyldSharedCache::find_lib_from_path, + R"doc( + Find the Dylib whose :attr:`lief.dsc.Dylib.path` matches the provided path. + )doc", "path"_a, + nb::keep_alive<0, 1>() + ) + .def("find_lib_from_name", &dsc::DyldSharedCache::find_lib_from_name, + R"doc( + Find the Dylib whose filename of :attr:`lief.dsc.Dylib.path` matches the + provided name. + + If multiple libraries have the same name (but with a different path), + the **first one** matching the provided name is returned. + )doc", "name"_a, + nb::keep_alive<0, 1>() + ) + .def_prop_ro("libraries", + [] (const DyldSharedCache& self) { + auto libraries = LIEF::py::owning_random_access_range(self.libraries()); + return nb::make_random_access_iterator(nb::type(), "dylib_iterator", libraries); + }, nb::keep_alive<0, 1>(), + R"doc( + Return a list-like of the :class:`~.Dylib` embedded in this dyld shared cache + )doc"_doc + ) + + .def_prop_ro("mapping_info", + [] (const DyldSharedCache& self) { + auto mapping = LIEF::py::owning_random_access_range(self.mapping_info()); + return nb::make_random_access_iterator(nb::type(), "mapping_info_iterator", mapping); + }, nb::keep_alive<0, 1>(), + R"doc( + Return a list-like of the :class:`~.MappingInfo` embedded in this dyld shared cache + )doc"_doc + ) + + .def_prop_ro("subcaches", + [] (const DyldSharedCache& self) { + auto subcaches = LIEF::py::owning_random_access_range(self.subcaches()); + return nb::make_random_access_iterator(nb::type(), "subcache_iterator", subcaches); + }, nb::keep_alive<0, 1>(), + R"doc( + Return a list-like of :class:`~.SubCache` embedded in this (main) + dyld shared cache + )doc"_doc + ) + + .def("get_content_from_va", + [] (const DyldSharedCache& self, uint64_t addr, size_t size) { + return nb::to_bytes(self.get_content_from_va(addr, size)); + }, + R"doc( + Return the content at the specified virtual address + )doc"_doc, "addr"_a, "size"_a + ) + + .def("cache_for_address", &DyldSharedCache::cache_for_address, + R"doc( + Find the sub-DyldSharedCache that wraps the given virtual address + )doc"_doc, "address"_a, nb::keep_alive<0, 1>() + ) + + .def_prop_ro("main_cache", &DyldSharedCache::main_cache, + R"doc( + Return the principal dyld shared cache in the case of multiple subcaches + )doc"_doc, nb::keep_alive<1, 0>() + ) + + .def("find_subcache", &DyldSharedCache::find_subcache, + R"doc( + Try to find the DyldSharedCache associated with the filename given + in the first parameter. + )doc"_doc, "filename"_a, nb::keep_alive<1, 0>() + ) + + .def("va_to_offset", [] (DyldSharedCache& self, uint64_t va) { + return LIEF::py::error_or(&DyldSharedCache::va_to_offset, self, va); + }, + R"doc( + Convert the given virtual address into an offset. + + .. warning:: + + If the shared cache contains multiple subcaches, + this function needs to be called on the targeted subcache. + See :func:`~.DyldSharedCache.cache_for_address` to find the + associated subcache. + )doc"_doc, "virtual_address"_a + ) + + .def("disassemble", + [] (const DyldSharedCache& self, uint64_t addr) { + auto insts = LIEF::py::owning_range(self.disassemble(addr)); + return nb::make_iterator( + nb::type(), "instructions_iterator", insts + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Disassemble instructions at the provided virtual address. + + This function returns an iterator over :class:`lief.assembly.Instruction`. + )doc"_doc + ) + + .def("enable_caching", &DyldSharedCache::enable_caching, + R"doc( + When enabled, this function allows to record and to keep in *cache*, + dyld shared cache information that are costly to access. + + For instance, GOT symbols, rebases information, stub symbols, ... + + It is **highly** recommended to enable this function when processing + a dyld shared cache several times or when extracting a large number of + :class:`lief.dsc.Dylib` with enhanced extraction options + (e.g. :attr:`lief.dsc.Dylib.extract_opt_t.fix_branches`) + + One can enable caching by calling this function: + + .. code-block:: python + + dyld_cache = lief.dsc.load("macos-15.0.1/"); + dyld_cache.enable_caching("~/.cache/lief-dsc"); + + One can also enable this cache optimization **globally** using the + function: :func:`lief.dsc.enable_cache` or by setting the environment variable + ``DYLDSC_ENABLE_CACHE`` to 1. + )doc"_doc, "target_dir"_a + ) + + .def("flush_cache", &DyldSharedCache::flush_cache, + R"doc( + Flush internal information into the on-disk cache (see: :meth:`~.enable_caching`) + )doc"_doc + ) + ; + + m.def("load", nb::overload_cast&>(&dsc::load), + R"doc( + Load a shared cache from a list of files. + + .. code-block:: python + + files = [ + "/tmp/dsc/dyld_shared_cache_arm64e", + "/tmp/dsc/dyld_shared_cache_arm64e.1" + ] + cache = lief.dsc.load(files) + )doc"_doc, "files"_a); + + m.def("load", [] (nb::PathLike path, const std::string& arch) { + return load(path, arch); + }, + R"doc( + Load a shared cache from a single file or from a directory specified + by the ``path`` parameter. + + In the case where multiple architectures are + available in the ``path`` directory, the ``arch`` parameter can be used to + define which architecture should be preferred. + + **Example:** + + .. code-block:: python + + # From a directory (split caches) + cache = lief.dsc.load("vision-pro-2.0/") + + # From a single cache file + cache = lief.dsc.load("ios-14.2/dyld_shared_cache_arm64") + + # From a directory with multiple architectures + cache = lief.dsc.load("macos-12.6/", "x86_64h") + )doc"_doc, "path"_a, "arch"_a = ""); +} +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.hpp b/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.hpp new file mode 100644 index 0000000..f10e12c --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pyDyldSharedCache.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_DSC_H +#define PY_LIEF_DSC_H +#include "pyLIEF.hpp" + +namespace LIEF::dsc::py { + +namespace dsc = LIEF::dsc; + +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/DyldSharedCache/pyDylib.cpp b/vendor/lief/api/python/src/DyldSharedCache/pyDylib.cpp new file mode 100644 index 0000000..c7b3a37 --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pyDylib.cpp @@ -0,0 +1,143 @@ +#include "LIEF/DyldSharedCache/Dylib.hpp" +#include "LIEF/MachO/Binary.hpp" +#include "DyldSharedCache/pyDyldSharedCache.hpp" + +#include +#include +#include + + +namespace LIEF::dsc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Dylib", + R"doc( + This class represents a library embedded in a dyld shared cache. + It mirrors the original ``dyld_cache_image_info`` structure. + )doc"_doc + ); + + nb::class_(obj, "extract_opt_t", + R"doc( + This structure is used to tweak the extraction process while calling + :meth:`lief.dsc.Dylib.get`. These options allow to deoptimize the dylib and + get an accurate representation of the original Mach-O binary. + )doc" + ) + .def(nb::init<>()) + .def_rw("pack", &Dylib::extract_opt_t::pack, + R"doc( + Whether the segment's offsets should be packed to avoid + an in-memory size while writing back the binary. + + .. note:: + + This option does not have an impact on the performances + )doc"_doc + ) + + .def_rw("fix_branches", &Dylib::extract_opt_t::fix_branches, + R"doc( + Fix call instructions that target addresses outside the current dylib + virtual space. + + .. warning:: + + Enabling this option can have a significant impact on the + performances. Make sure to enable the internal cache mechanism: + :func:`lief.dsc.enable_cache` or :meth:`lief.dsc.DyldSharedCache.enable_caching` + )doc"_doc + ) + + .def_rw("fix_memory", &Dylib::extract_opt_t::fix_memory, + R"doc( + Fix memory accesses performed outside the dylib's virtual space + + .. warning:: + + Enabling this option can have a significant impact on the + performances. Make sure to enable the internal cache mechanism: + :func:`lief.dsc.enable_cache` or :meth:`lief.dsc.DyldSharedCache.enable_caching` + )doc"_doc + ) + + .def_rw("fix_relocations", &Dylib::extract_opt_t::fix_relocations, + R"doc( + Recover and fix relocations + + .. warning:: + + Enabling this option can have a significant impact on the + performances. Make sure to enable the internal cache mechanism: + :func:`lief.dsc.enable_cache` or :meth:`lief.dsc.DyldSharedCache.enable_caching` + )doc"_doc + ) + + .def_rw("fix_objc", &Dylib::extract_opt_t::fix_relocations, + R"doc( + Fix Objective-C information + + .. warning:: + + Enabling this option can have a significant impact on the + performances. Make sure to enable the internal cache mechanism: + :func:`lief.dsc.enable_cache` or :meth:`lief.dsc.DyldSharedCache.enable_caching` + )doc"_doc + ) + + .def_prop_rw("create_dyld_chained_fixup_cmd", + [] (const Dylib::extract_opt_t& opt) -> bool { + return opt.create_dyld_chained_fixup_cmd.value_or(false); + }, + [] (Dylib::extract_opt_t& self, bool value) { + self.create_dyld_chained_fixup_cmd = value; + }, + R"doc( + Whether the ``LC_DYLD_CHAINED_FIXUPS`` command should be (re)created. + + If this value is not set, LIEF will add the command only if it's + meaningful regarding the other options + )doc"_doc + ) + ; + + obj + .def_prop_ro("path", &dsc::Dylib::path, + R"doc(Original path of the library (e.g. ``/usr/lib/libcryptex.dylib``))doc"_doc + ) + .def_prop_ro("address", &dsc::Dylib::address, + R"doc(In-memory address of the library)doc"_doc + ) + .def_prop_ro("modtime", &dsc::Dylib::modtime, + R"doc( + Modification time of the library matching ``stat.st_mtime``, or 0 + )doc"_doc + ) + .def_prop_ro("inode", &dsc::Dylib::inode, + R"doc( + File serial number matching ``stat.st_ino`` or 0 + + Note that for shared cache targeting iOS, this value can hold a hash of + the path (if modtime is set to 0) + )doc"_doc + ) + .def_prop_ro("padding", &dsc::Dylib::padding, + R"doc(Padding alignment value (should be 0))doc"_doc + ) + + .def("get", &dsc::Dylib::get, + R"doc( + Get a :class:`lief.MachO.Binary` representation for this Dylib. + + One can use this function to write back the Mach-O binary on the disk: + + .. code-block:: python + + dyld_cache: lief.dsc.DyldSharedCache = ... + dyld_cache.libraries[10].get().write("libsystem.dylib") + + )doc"_doc, "opt"_a = Dylib::extract_opt_t() + ) + ; +} +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/pyMappingInfo.cpp b/vendor/lief/api/python/src/DyldSharedCache/pyMappingInfo.cpp new file mode 100644 index 0000000..0ba4a8f --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pyMappingInfo.cpp @@ -0,0 +1,37 @@ +#include "LIEF/DyldSharedCache/MappingInfo.hpp" +#include "DyldSharedCache/pyDyldSharedCache.hpp" + +namespace LIEF::dsc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "MappingInfo", + R"doc( + This class represents a ``dyld_cache_mapping_info`` entry. + + It provides information about the relationship between on-disk shared cache + and in-memory shared cache. + )doc"_doc + ); + + obj + .def_prop_ro("address", &dsc::MappingInfo::address, + R"doc(The in-memory address where this dyld shared cache region is mapped)doc"_doc + ) + .def_prop_ro("size", &dsc::MappingInfo::size, + R"doc(Size of the region being mapped)doc"_doc + ) + .def_prop_ro("end_address", &dsc::MappingInfo::end_address, + R"doc(End virtual address of the region)doc"_doc + ) + .def_prop_ro("file_offset", &dsc::MappingInfo::file_offset, + R"doc(On-disk file offset)doc"_doc + ) + .def_prop_ro("max_prot", &dsc::MappingInfo::max_prot, + R"doc(Max memory protection)doc"_doc + ) + .def_prop_ro("init_prot", &dsc::MappingInfo::init_prot, + R"doc(Initial memory protection)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/pySubCache.cpp b/vendor/lief/api/python/src/DyldSharedCache/pySubCache.cpp new file mode 100644 index 0000000..f4fa659 --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pySubCache.cpp @@ -0,0 +1,43 @@ +#include "LIEF/DyldSharedCache/SubCache.hpp" +#include "LIEF/DyldSharedCache/DyldSharedCache.hpp" +#include "DyldSharedCache/pyDyldSharedCache.hpp" + +#include +#include +#include + +namespace LIEF::dsc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "SubCache", + R"doc( + This class represents a subcache in the case of large/split dyld shared + cache. + + It mirror (and abstracts) the original ``dyld_subcache_entry`` / ``dyld_subcache_entry_v1`` + )doc"_doc + ); + + obj + .def_prop_ro("uuid", &SubCache::uuid, + R"doc(The uuid of the subcache file)doc"_doc + ) + .def_prop_ro("vm_offset", &SubCache::vm_offset, + R"doc(The offset of this subcache from the main cache base address)doc"_doc + ) + .def_prop_ro("suffix", &SubCache::suffix, + R"doc( + The file name suffix of the subCache file + (e.g. ``.25.data``, ``.03.development``) + )doc"_doc + ) + .def_prop_ro("cache", [] (const SubCache& self) { + return std::unique_ptr(const_cast(self.cache().release())); + }, + R"doc( + The associated :class:`~.DyldSharedCache` object for this subcache + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/DyldSharedCache/pyUtils.cpp b/vendor/lief/api/python/src/DyldSharedCache/pyUtils.cpp new file mode 100644 index 0000000..d46c3a9 --- /dev/null +++ b/vendor/lief/api/python/src/DyldSharedCache/pyUtils.cpp @@ -0,0 +1,34 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "DyldSharedCache/pyDyldSharedCache.hpp" +#include "DyldSharedCache/init.hpp" + +#include "LIEF/DyldSharedCache/utils.hpp" + +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::dsc::py { + +void init_utils(nb::module_&) { + lief_mod->def("is_shared_cache", + [] (nb::PathLike path) { return is_shared_cache(path); }, + "Check if the given file is a dyld shared cache"_doc, + "file"_a + ); +} +} diff --git a/vendor/lief/api/python/src/ELF/CMakeLists.txt b/vendor/lief/api/python/src/ELF/CMakeLists.txt new file mode 100644 index 0000000..bec2b8e --- /dev/null +++ b/vendor/lief/api/python/src/ELF/CMakeLists.txt @@ -0,0 +1,7 @@ +target_sources(pyLIEF PRIVATE + init.cpp + enums.cpp + pyProcessorFlags.cpp +) + +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/ELF/enums.cpp b/vendor/lief/api/python/src/ELF/enums.cpp new file mode 100644 index 0000000..370d603 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/enums.cpp @@ -0,0 +1,208 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/enums.hpp" +#include "LIEF/ELF/enums.hpp" +#include "LIEF/ELF/EnumToString.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::ELF::py { +void init_enums(nb::module_& m) { + #define ENTRY(X) .value(to_string(ARCH::X), ARCH::X) + enum_(m, "ARCH") + ENTRY(NONE) + ENTRY(M32) + ENTRY(SPARC) + ENTRY(I386) + ENTRY(M68K) + ENTRY(M88K) + ENTRY(IAMCU) + ENTRY(I860) + ENTRY(MIPS) + ENTRY(S370) + ENTRY(MIPS_RS3_LE) + ENTRY(PARISC) + ENTRY(VPP500) + ENTRY(SPARC32PLUS) + ENTRY(I60) + ENTRY(PPC) + ENTRY(PPC64) + ENTRY(S390) + ENTRY(SPU) + ENTRY(V800) + ENTRY(FR20) + ENTRY(RH32) + ENTRY(RCE) + ENTRY(ARM) + ENTRY(ALPHA) + ENTRY(SH) + ENTRY(SPARCV9) + ENTRY(TRICORE) + ENTRY(ARC) + ENTRY(H8_300) + ENTRY(H8_300H) + ENTRY(H8S) + ENTRY(H8_500) + ENTRY(IA_64) + ENTRY(MIPS_X) + ENTRY(COLDFIRE) + ENTRY(M68HC12) + ENTRY(MMA) + ENTRY(PCP) + ENTRY(NCPU) + ENTRY(NDR1) + ENTRY(STARCORE) + ENTRY(ME16) + ENTRY(ST100) + ENTRY(TINYJ) + ENTRY(X86_64) + ENTRY(PDSP) + ENTRY(PDP10) + ENTRY(PDP11) + ENTRY(FX66) + ENTRY(ST9PLUS) + ENTRY(ST7) + ENTRY(M68HC16) + ENTRY(M68HC11) + ENTRY(M68HC08) + ENTRY(M68HC05) + ENTRY(SVX) + ENTRY(ST19) + ENTRY(VAX) + ENTRY(CRIS) + ENTRY(JAVELIN) + ENTRY(FIREPATH) + ENTRY(ZSP) + ENTRY(MMIX) + ENTRY(HUANY) + ENTRY(PRISM) + ENTRY(AVR) + ENTRY(FR30) + ENTRY(D10V) + ENTRY(D30V) + ENTRY(V850) + ENTRY(M32R) + ENTRY(MN10300) + ENTRY(MN10200) + ENTRY(PJ) + ENTRY(OPENRISC) + ENTRY(ARC_COMPACT) + ENTRY(XTENSA) + ENTRY(VIDEOCORE) + ENTRY(TMM_GPP) + ENTRY(NS32K) + ENTRY(TPC) + ENTRY(SNP1K) + ENTRY(ST200) + ENTRY(IP2K) + ENTRY(MAX) + ENTRY(CR) + ENTRY(F2MC16) + ENTRY(MSP430) + ENTRY(BLACKFIN) + ENTRY(SE_C33) + ENTRY(SEP) + ENTRY(ARCA) + ENTRY(UNICORE) + ENTRY(EXCESS) + ENTRY(DXP) + ENTRY(ALTERA_NIOS2) + ENTRY(CRX) + ENTRY(XGATE) + ENTRY(C166) + ENTRY(M16C) + ENTRY(DSPIC30F) + ENTRY(CE) + ENTRY(M32C) + ENTRY(TSK3000) + ENTRY(RS08) + ENTRY(SHARC) + ENTRY(ECOG2) + ENTRY(SCORE7) + ENTRY(DSP24) + ENTRY(VIDEOCORE3) + ENTRY(LATTICEMICO32) + ENTRY(SE_C17) + ENTRY(TI_C6000) + ENTRY(TI_C2000) + ENTRY(TI_C5500) + ENTRY(MMDSP_PLUS) + ENTRY(CYPRESS_M8C) + ENTRY(R32C) + ENTRY(TRIMEDIA) + ENTRY(HEXAGON) + ENTRY(M8051) + ENTRY(STXP7X) + ENTRY(NDS32) + ENTRY(ECOG1) + /* ENTRY(ECOG1X) */ + ENTRY(MAXQ30) + ENTRY(XIMO16) + ENTRY(MANIK) + ENTRY(CRAYNV2) + ENTRY(RX) + ENTRY(METAG) + ENTRY(MCST_ELBRUS) + ENTRY(ECOG16) + ENTRY(CR16) + ENTRY(ETPU) + ENTRY(SLE9X) + ENTRY(L10M) + ENTRY(K10M) + ENTRY(AARCH64) + ENTRY(AVR32) + ENTRY(STM8) + ENTRY(TILE64) + ENTRY(TILEPRO) + ENTRY(CUDA) + ENTRY(TILEGX) + ENTRY(CLOUDSHIELD) + ENTRY(COREA_1ST) + ENTRY(COREA_2ND) + ENTRY(ARC_COMPACT2) + ENTRY(OPEN8) + ENTRY(RL78) + ENTRY(VIDEOCORE5) + ENTRY(M78KOR) + ENTRY(M56800EX) + ENTRY(BA1) + ENTRY(BA2) + ENTRY(XCORE) + ENTRY(MCHP_PIC) + ENTRY(INTEL205) + ENTRY(INTEL206) + ENTRY(INTEL207) + ENTRY(INTEL208) + ENTRY(INTEL209) + ENTRY(KM32) + ENTRY(KMX32) + ENTRY(KMX16) + ENTRY(KMX8) + ENTRY(KVARC) + ENTRY(CDP) + ENTRY(COGE) + ENTRY(COOL) + ENTRY(NORC) + ENTRY(CSR_KALIMBA) + ENTRY(AMDGPU) + ENTRY(RISCV) + ENTRY(BPF) + ENTRY(CSKY) + ENTRY(LOONGARCH) + ENTRY(ALPHA_ALT) + ; + #undef ENTRY +} +} diff --git a/vendor/lief/api/python/src/ELF/enums.hpp b/vendor/lief/api/python/src/ELF/enums.hpp new file mode 100644 index 0000000..a6ebf51 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/enums.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ELF_ENUMS_H +#define PY_LIEF_ELF_ENUMS_H +#include "pyLIEF.hpp" + +namespace LIEF::ELF::py { +void init_enums(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/ELF/init.cpp b/vendor/lief/api/python/src/ELF/init.cpp new file mode 100644 index 0000000..4abddf3 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/init.cpp @@ -0,0 +1,136 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/init.hpp" +#include "ELF/enums.hpp" +#include "ELF/pyELF.hpp" + +#include +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +#include "LIEF/ELF/Builder.hpp" +#include "LIEF/ELF/Binary.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" +#include "LIEF/ELF/DynamicEntryArray.hpp" +#include "LIEF/ELF/DynamicEntryFlags.hpp" +#include "LIEF/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/ELF/DynamicEntryRpath.hpp" +#include "LIEF/ELF/DynamicEntryRunPath.hpp" +#include "LIEF/ELF/DynamicSharedObject.hpp" +#include "LIEF/ELF/DynamicEntryAuxiliary.hpp" +#include "LIEF/ELF/DynamicEntryFilter.hpp" +#include "LIEF/ELF/GnuHash.hpp" +#include "LIEF/ELF/Header.hpp" +#include "LIEF/ELF/Parser.hpp" +#include "LIEF/ELF/Relocation.hpp" +#include "LIEF/ELF/Section.hpp" +#include "LIEF/ELF/Segment.hpp" +#include "LIEF/ELF/SymbolVersion.hpp" +#include "LIEF/ELF/SymbolVersionAux.hpp" +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" +#include "LIEF/ELF/SymbolVersionDefinition.hpp" +#include "LIEF/ELF/SymbolVersionRequirement.hpp" +#include "LIEF/ELF/SysvHash.hpp" +#include "LIEF/ELF/utils.hpp" + +#include "LIEF/ELF/Note.hpp" +#include "LIEF/ELF/NoteDetails/AndroidIdent.hpp" +#include "LIEF/ELF/NoteDetails/QNXStack.hpp" +#include "LIEF/ELF/NoteDetails/NoteAbi.hpp" +#include "LIEF/ELF/NoteDetails/NoteGnuProperty.hpp" +#include "LIEF/ELF/NoteDetails/core/CoreAuxv.hpp" +#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" +#include "LIEF/ELF/NoteDetails/core/CorePrPsInfo.hpp" +#include "LIEF/ELF/NoteDetails/core/CoreSigInfo.hpp" +#include "LIEF/ELF/NoteDetails/core/CorePrStatus.hpp" + +#define CREATE(X,Y) create(Y) + +namespace LIEF::ELF::py { + +void init_notes(nb::module_& m) { + CREATE(Note, m); + CREATE(NoteGnuProperty, m); + CREATE(AndroidIdent, m); + CREATE(NoteAbi, m); + CREATE(CoreAuxv, m); + CREATE(CoreFile, m); + CREATE(CorePrPsInfo, m); + CREATE(CoreSigInfo, m); + CREATE(CorePrStatus, m); + CREATE(QNXStack, m); +} + +void init_objects(nb::module_& m) { + CREATE(ParserConfig, m); + CREATE(Parser, m); + CREATE(SymbolVersion, m); + CREATE(Binary, m); + CREATE(PROCESSOR_FLAGS, m); + CREATE(Header, m); + CREATE(Section, m); + CREATE(Segment, m); + CREATE(Symbol, m); + CREATE(Relocation, m); + CREATE(SymbolVersionAux, m); + CREATE(SymbolVersionAuxRequirement, m); + CREATE(SymbolVersionDefinition,m ); + CREATE(SymbolVersionRequirement, m); + CREATE(DynamicEntry, m); + CREATE(DynamicEntryLibrary, m); + CREATE(DynamicSharedObject, m); + CREATE(DynamicEntryAuxiliary, m); + CREATE(DynamicEntryFilter, m); + CREATE(DynamicEntryArray, m); + CREATE(DynamicEntryRpath, m); + CREATE(DynamicEntryRunPath, m); + CREATE(DynamicEntryFlags, m); + CREATE(GnuHash, m); + CREATE(SysvHash, m); + CREATE(Builder, m); + + init_notes(m); +} + +inline void init_utils(nb::module_& m) { + lief_mod->def("is_elf", + [] (nb::PathLike path) { + return is_elf(path.to_string()); + }, "Check if the given file is an ``ELF``", "filename"_a + ); + + lief_mod->def("is_elf", + nb::overload_cast&>(&is_elf), + "Check if the given raw data is an ``ELF``", + "raw"_a); + + m.def("check_layout", [] (const Binary& bin) -> std::pair { + std::string error; + if (!check_layout(bin, &error)) { + return std::make_pair(false, std::move(error)); + } + return std::make_pair(true, ""); + }, "Check that the layout of the given binary is correct."_doc, "binary"_a); +} + +void init(nb::module_& m) { + nb::module_ elf_mod = m.def_submodule("ELF", "Python API for the ELF format"); + init_utils(elf_mod); + init_enums(elf_mod); + init_objects(elf_mod); +} +} diff --git a/vendor/lief/api/python/src/ELF/init.hpp b/vendor/lief/api/python/src/ELF/init.hpp new file mode 100644 index 0000000..bc10aa9 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ELF_INIT_H +#define PY_LIEF_ELF_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::ELF::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/ELF/objects/CMakeLists.txt b/vendor/lief/api/python/src/ELF/objects/CMakeLists.txt new file mode 100644 index 0000000..a870443 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/CMakeLists.txt @@ -0,0 +1,31 @@ +target_sources(pyLIEF PRIVATE + pyParser.cpp + pyBinary.cpp + pyBuilder.cpp + pyDynamicEntry.cpp + pyDynamicEntryArray.cpp + pyDynamicEntryFlags.cpp + pyDynamicEntryLibrary.cpp + pyDynamicEntryRpath.cpp + pyDynamicEntryRunPath.cpp + pyDynamicSharedObject.cpp + pyDynamicEntryAuxiliary.cpp + pyDynamicEntryFilter.cpp + pyGnuHash.cpp + pyHeader.cpp + pyParserConfig.cpp + pyNote.cpp + pyRelocation.cpp + pyRelocationTypes.cpp + pySection.cpp + pySegment.cpp + pySymbol.cpp + pySymbolVersion.cpp + pySymbolVersionAux.cpp + pySymbolVersionAuxRequirement.cpp + pySymbolVersionRequirement.cpp + pySymbolVersionDefinition.cpp + pySysvHash.cpp +) + +add_subdirectory(NoteDetails) diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/CMakeLists.txt b/vendor/lief/api/python/src/ELF/objects/NoteDetails/CMakeLists.txt new file mode 100644 index 0000000..d762c1e --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/CMakeLists.txt @@ -0,0 +1,10 @@ +target_sources(pyLIEF PRIVATE + pyAndroidIdent.cpp + pyNoteAbi.cpp + pyNoteGnuProperty.cpp + pyQNXStack.cpp +) + +add_subdirectory(core) +add_subdirectory(properties) + diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/CMakeLists.txt b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/CMakeLists.txt new file mode 100644 index 0000000..628848b --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/CMakeLists.txt @@ -0,0 +1,7 @@ +target_sources(pyLIEF PRIVATE + pyCorePrPsInfo.cpp + pyCoreFile.cpp + pyCorePrStatus.cpp + pyCoreAuxv.cpp + pyCoreSigInfo.cpp +) diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp new file mode 100644 index 0000000..4c7e68b --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreAuxv.cpp @@ -0,0 +1,108 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/core/CoreAuxv.hpp" + +#include "pyErr.hpp" +#include "enums_wrapper.hpp" + + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + + nb::class_ cls(m, "CoreAuxv"); + #define PY_ENUM(X) .value(LIEF::ELF::to_string(CoreAuxv::TYPE::X), CoreAuxv::TYPE::X) + LIEF::enum_(cls, "TYPE") + PY_ENUM(END) + PY_ENUM(IGNORE_TY) + PY_ENUM(EXECFD) + PY_ENUM(PHDR) + PY_ENUM(PHENT) + PY_ENUM(PHNUM) + PY_ENUM(PAGESZ) + PY_ENUM(BASE) + PY_ENUM(FLAGS) + PY_ENUM(ENTRY) + PY_ENUM(NOTELF) + PY_ENUM(UID) + PY_ENUM(EUID) + PY_ENUM(GID) + PY_ENUM(EGID) + PY_ENUM(TGT_PLATFORM) + PY_ENUM(HWCAP) + PY_ENUM(CLKTCK) + PY_ENUM(FPUCW) + PY_ENUM(DCACHEBSIZE) + PY_ENUM(ICACHEBSIZE) + PY_ENUM(UCACHEBSIZE) + PY_ENUM(IGNOREPPC) + PY_ENUM(SECURE) + PY_ENUM(BASE_PLATFORM) + PY_ENUM(RANDOM) + PY_ENUM(HWCAP2) + PY_ENUM(EXECFN) + PY_ENUM(SYSINFO) + PY_ENUM(SYSINFO_EHDR) + ; + #undef PY_ENUM + + cls + .def_prop_ro("values", &CoreAuxv::values, + R"doc( + Return the auxiliary vector as a dictionary of :class:`.TYPE` / `int` + )doc" + ) + + .def("get", + [] (const CoreAuxv& self, CoreAuxv::TYPE type) { + return LIEF::py::value_or_none(&CoreAuxv::get, self, type); + }, "type"_a, + R"doc( + Get the auxv value from the provided type. Return `None` if + it is not present. + )doc"_doc + ) + + .def("__getitem__", + [] (const CoreAuxv& self, CoreAuxv::TYPE type) { + return LIEF::py::value_or_none(&CoreAuxv::get, self, type); + } + ) + + .def("set", nb::overload_cast(&CoreAuxv::set), + "type"_a, "value"_a, + R"doc( + Change the value for the given type. + )doc") + .def("set", nb::overload_cast&>(&CoreAuxv::set), + R"doc( + Replace **all** the values by the given dictionary. + )doc") + + .def("__setitem__", nb::overload_cast(&CoreAuxv::set)) + .def("__setitem__", nb::overload_cast&>(&CoreAuxv::set)) + + LIEF_DEFAULT_STR(CoreAuxv); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreFile.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreFile.cpp new file mode 100644 index 0000000..d2fe165 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreFile.cpp @@ -0,0 +1,67 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "CoreFile"); + nb::bind_vector(cls, "files_t"); + + nb::class_(cls, "entry_t") + .def_rw("start", &CoreFile::entry_t::start, + "Start address of mapped file"_doc) + + .def_rw("end", &CoreFile::entry_t::end, + "End address of mapped file"_doc) + + .def_rw("file_ofs", &CoreFile::entry_t::file_ofs, + "Offset (in core) of mapped file"_doc) + + .def_rw("path", &CoreFile::entry_t::path, + "Path of mapped file"_doc) + + LIEF_DEFAULT_STR(CoreFile::entry_t); + + cls + .def_prop_rw("files", + nb::overload_cast<>(&CoreFile::files, nb::const_), + nb::overload_cast(&CoreFile::files), + "List of files mapped in core. (list of " RST_CLASS_REF(lief.ELF.CoreFileEntry) ")"_doc) + + .def("__len__", + &CoreFile::count, + "Number of files mapped in core"_doc) + + .def("__iter__", + [] (const CoreFile& f) { + return nb::make_iterator(nanobind::type(), "corefile_it", + std::begin(f), std::end(f)); + }, nb::keep_alive<0, 1>()) + + LIEF_DEFAULT_STR(CoreFile); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp new file mode 100644 index 0000000..d1ae924 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrPsInfo.cpp @@ -0,0 +1,58 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include + +#include "pyErr.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/core/CorePrPsInfo.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "CorePrPsInfo"); + nb::class_(cls, "info_t") + .def_rw("state", &CorePrPsInfo::info_t::state) + .def_rw("sname", &CorePrPsInfo::info_t::sname) + .def_rw("zombie", &CorePrPsInfo::info_t::zombie) + .def_rw("nice", &CorePrPsInfo::info_t::nice) + .def_rw("flag", &CorePrPsInfo::info_t::flag) + .def_rw("uid", &CorePrPsInfo::info_t::uid) + .def_rw("gid", &CorePrPsInfo::info_t::gid) + .def_rw("pid", &CorePrPsInfo::info_t::pid) + .def_rw("ppid", &CorePrPsInfo::info_t::ppid) + .def_rw("pgrp", &CorePrPsInfo::info_t::pgrp) + .def_rw("sid", &CorePrPsInfo::info_t::sid) + .def_rw("filename", &CorePrPsInfo::info_t::filename) + .def_rw("args", &CorePrPsInfo::info_t::args) + .def_prop_ro("filename_stripped", &CorePrPsInfo::info_t::filename_stripped) + .def_prop_ro("args_stripped", &CorePrPsInfo::info_t::args_stripped); + + cls + .def_prop_rw("info", + [] (const CorePrPsInfo& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&CorePrPsInfo::info, nb::const_), self); + }, + nb::overload_cast(&CorePrPsInfo::info) + ) + LIEF_DEFAULT_STR(CorePrPsInfo); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp new file mode 100644 index 0000000..ebb8888 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCorePrStatus.cpp @@ -0,0 +1,256 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "pyErr.hpp" +#include "ELF/pyELF.hpp" +#include "LIEF/ELF/NoteDetails/core/CorePrStatus.hpp" + +#include "enums_wrapper.hpp" + +#define GET_SET_REGISTER(ARCH) \ + .def("get", [] (const CorePrStatus& self, CorePrStatus::Registers::ARCH reg) { \ + return LIEF::py::value_or_none(nb::overload_cast(&CorePrStatus::get, nb::const_), self, reg); \ + }, "Get the register value or non if it is not present", "reg"_a) \ + .def("__getitem__", [] (const CorePrStatus& self, CorePrStatus::Registers::ARCH reg) { \ + return LIEF::py::value_or_none(nb::overload_cast(&CorePrStatus::get, nb::const_), self, reg); \ + }) \ + .def("set", nb::overload_cast(&CorePrStatus::set), \ + "Change the register value", "reg"_a, "value"_a) \ + .def("__setitem__", nb::overload_cast(&CorePrStatus::set)) + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "CorePrStatus"); + + nb::class_(cls, "timeval_t") + .def_rw("sec", &CorePrStatus::timeval_t::sec) + .def_rw("usec", &CorePrStatus::timeval_t::usec); + + nb::class_(cls, "siginfo_t") + .def_rw("sicode", &CorePrStatus::siginfo_t::code) + .def_rw("errno", &CorePrStatus::siginfo_t::err) + .def_rw("signo", &CorePrStatus::siginfo_t::signo); + + nb::class_(cls, "pr_status_t") + .def_rw("info", &CorePrStatus::pr_status_t::info) + .def_rw("cursig", &CorePrStatus::pr_status_t::cursig) + .def_rw("reserved", &CorePrStatus::pr_status_t::reserved) + .def_rw("sigpend", &CorePrStatus::pr_status_t::sigpend) + .def_rw("sighold", &CorePrStatus::pr_status_t::sighold) + .def_rw("pid", &CorePrStatus::pr_status_t::pid) + .def_rw("ppid", &CorePrStatus::pr_status_t::ppid) + .def_rw("pgrp", &CorePrStatus::pr_status_t::pgrp) + .def_rw("sid", &CorePrStatus::pr_status_t::sid) + .def_rw("utime", &CorePrStatus::pr_status_t::utime) + .def_rw("stime", &CorePrStatus::pr_status_t::stime) + .def_rw("cutime", &CorePrStatus::pr_status_t::cutime) + .def_rw("cstime", &CorePrStatus::pr_status_t::cstime); + + nb::class_ Registers(cls, "Registers"); + cls + .def_prop_rw("status", + nb::overload_cast<>(&CorePrStatus::status, nb::const_), + nb::overload_cast(&CorePrStatus::status), + R"doc( + Status information from a core dump + + This structure mirrors the kernel's ``prstatus`` data embedded in + ``NT_PRSTATUS`` core-dump notes and exposes signal state, process + identifiers, and CPU-time accounting. + )doc"_doc) + + .def_prop_ro("architecture", &CorePrStatus::architecture, + R"doc(Original target architecture.)doc"_doc) + + .def_prop_ro("pc", [] (const CorePrStatus& self) { + return LIEF::py::value_or_none(&CorePrStatus::pc, self); + }, + R"doc( + Return the program counter value (`rip`, `pc`, `eip` etc) + )doc"_doc) + + .def_prop_ro("sp", [] (const CorePrStatus& self) { + return LIEF::py::value_or_none(&CorePrStatus::sp, self); + }, + R"doc( + Return the stack pointer value + )doc"_doc) + + .def_prop_ro("return_value", [] (const CorePrStatus& self) { + return LIEF::py::value_or_none(&CorePrStatus::return_value, self); + }, + R"doc( + The value of the register that holds the return value according to + the calling convention. + )doc"_doc) + + .def_prop_ro("register_values", &CorePrStatus::register_values, + R"doc( + List of the register values. + This list is **guaranteed** to be as long as the number of registers defined + in the :class:`~.Registers` or empty if it can't be resolved. + + Thus, one can access a specific register through: + + .. code-block:: python + + reg_vals: list[int] = note.register_values() + x20 = reg_vals[CorePrStatus.Registers.AARCH64.X20.value] + )doc"_doc + ) + + GET_SET_REGISTER(X86) + GET_SET_REGISTER(X86_64) + GET_SET_REGISTER(ARM) + GET_SET_REGISTER(AARCH64) + LIEF_DEFAULT_STR(CorePrStatus); + + + #define ENTRY(X) .value(to_string(CorePrStatus::Registers::X86::X), CorePrStatus::Registers::X86::X) + enum_(Registers, "X86", + R"doc( + Registers for the x86 architecture (:attr:`~.ARCH.i386`) + )doc"_doc) + ENTRY(EBX) + ENTRY(ECX) + ENTRY(EDX) + ENTRY(ESI) + ENTRY(EDI) + ENTRY(EBP) + ENTRY(EAX) + ENTRY(DS) + ENTRY(ES) + ENTRY(FS) + ENTRY(GS) + ENTRY(ORIG_EAX) + ENTRY(EIP) + ENTRY(CS) + ENTRY(EFLAGS) + ENTRY(ESP) + ENTRY(SS) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(CorePrStatus::Registers::X86_64::X), CorePrStatus::Registers::X86_64::X) + enum_(Registers, "X86_64", + R"doc( + Registers for the x86-64 architecture (:attr:`~.ARCH.x86_64`) + )doc"_doc) + ENTRY(R15) + ENTRY(R14) + ENTRY(R13) + ENTRY(R12) + ENTRY(RBP) + ENTRY(RBX) + ENTRY(R11) + ENTRY(R10) + ENTRY(R9) + ENTRY(R8) + ENTRY(RAX) + ENTRY(RCX) + ENTRY(RDX) + ENTRY(RSI) + ENTRY(RDI) + ENTRY(ORIG_RAX) + ENTRY(RIP) + ENTRY(CS) + ENTRY(EFLAGS) + ENTRY(RSP) + ENTRY(SS) + ENTRY(FS_BASE) + ENTRY(GS_BASE) + ENTRY(DS) + ENTRY(ES) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(CorePrStatus::Registers::ARM::X), CorePrStatus::Registers::ARM::X) + enum_(Registers, "ARM", + R"doc( + Registers for the ARM architecture (:attr:`~.ARCH.ARM`) + )doc"_doc) + ENTRY(R0) + ENTRY(R1) + ENTRY(R2) + ENTRY(R3) + ENTRY(R4) + ENTRY(R5) + ENTRY(R6) + ENTRY(R7) + ENTRY(R8) + ENTRY(R9) + ENTRY(R10) + ENTRY(R11) + ENTRY(R12) + ENTRY(R13) + ENTRY(R14) + ENTRY(R15) + ENTRY(CPSR) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(CorePrStatus::Registers::AARCH64::X), CorePrStatus::Registers::AARCH64::X) + enum_(Registers, "AARCH64", + R"doc( + Registers for the AARCH64 architecture (:attr:`~.ARCH.AARCH64`) + )doc"_doc) + ENTRY(X0) + ENTRY(X1) + ENTRY(X2) + ENTRY(X3) + ENTRY(X4) + ENTRY(X5) + ENTRY(X6) + ENTRY(X7) + ENTRY(X8) + ENTRY(X9) + ENTRY(X10) + ENTRY(X11) + ENTRY(X12) + ENTRY(X13) + ENTRY(X14) + ENTRY(X15) + ENTRY(X16) + ENTRY(X17) + ENTRY(X18) + ENTRY(X19) + ENTRY(X20) + ENTRY(X21) + ENTRY(X22) + ENTRY(X23) + ENTRY(X24) + ENTRY(X25) + ENTRY(X26) + ENTRY(X27) + ENTRY(X28) + ENTRY(X29) + ENTRY(X30) + ENTRY(X31) + ENTRY(PC) + ENTRY(PSTATE) + ; + #undef ENTRY + + +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp new file mode 100644 index 0000000..c70767f --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/core/pyCoreSigInfo.cpp @@ -0,0 +1,54 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "pyErr.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/core/CoreSigInfo.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "CoreSigInfo") + .def_prop_rw("signo", + [] (const CoreSigInfo& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&CoreSigInfo::signo, nb::const_), self); + }, + nb::overload_cast(&CoreSigInfo::signo), + "Signal number"_doc) + + .def_prop_rw("sigcode", + [] (const CoreSigInfo& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&CoreSigInfo::sigcode, nb::const_), self); + }, + nb::overload_cast(&CoreSigInfo::sigcode), + "Signal code"_doc) + + .def_prop_rw("sigerrno", + [] (const CoreSigInfo& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&CoreSigInfo::sigerrno, nb::const_), self); + }, + nb::overload_cast(&CoreSigInfo::sigerrno), + "If non-zero, an errno value associated with this signal"_doc) + + LIEF_DEFAULT_STR(CoreSigInfo); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/CMakeLists.txt b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/CMakeLists.txt new file mode 100644 index 0000000..6b91b17 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/CMakeLists.txt @@ -0,0 +1,10 @@ +target_sources(pyLIEF PRIVATE + pyAArch64Feature.cpp + pyAArch64PAuth.cpp + pyGeneric.cpp + pyNeeded.cpp + pyNoteNoCopyOnProtected.cpp + pyX86Features.cpp + pyX86ISA.cpp + pyStackSize.cpp +) diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64Feature.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64Feature.cpp new file mode 100644 index 0000000..0898ff3 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64Feature.cpp @@ -0,0 +1,52 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include + +#include "enums_wrapper.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/AArch64Feature.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ + Class(m, "AArch64Feature", + R"doc( + This class represents the ``GNU_PROPERTY_AARCH64_FEATURE_1_AND`` note. + )doc"_doc); + + Class + .def_prop_ro("features", &AArch64Feature::features, + R"doc( + Return the list of the supported features. + )doc"_doc); + +# define ENTRY(X, D) .value(to_string(AArch64Feature::FEATURE::X), AArch64Feature::FEATURE::X, D) + enum_(Class, "FEATURE") + ENTRY(UNKNOWN, "") + ENTRY(BTI, "Support Branch Target Identification (BTI)") + ENTRY(PAC, "Support Pointer authentication (PAC)") + ENTRY(GCS, "Support Guarded Control Stack (GCS)") + ; +# undef ENTRY +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64PAuth.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64PAuth.cpp new file mode 100644 index 0000000..e1bc095 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyAArch64PAuth.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/AArch64PAuth.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ + Class(m, "AArch64PAuth", + R"doc( + This class represents the ``GNU_PROPERTY_AARCH64_FEATURE_PAUTH`` note. + + .. note:: + + If both: :attr:`.AArch64PAuth.platform` and :attr:`.AArch64PAuth.version` are set to + 0, this means that the binary is incompatible with PAuth ABI extension. + )doc"_doc); + + Class + .def_prop_ro("platform", &AArch64PAuth::platform, + R"doc( + 64-bit value that specifies the platform vendor. + + A ``0`` value is associated with an *invalid* platform while the value ``1`` + is associated with a baremetal platform. + )doc"_doc) + + .def_prop_ro("version", &AArch64PAuth::version, + R"doc( + 64-bit value that identifies the signing schema used by the ELF file. + )doc"_doc) + ; + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyGeneric.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyGeneric.cpp new file mode 100644 index 0000000..06cef40 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyGeneric.cpp @@ -0,0 +1,36 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/Generic.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Generic", + R"doc( + This class represents a property which doesn't have a concrete LIEF implementation. + )doc") + .def_prop_ro("raw_type", &Generic::type, + R"doc( + The original raw type as an integer. This value might depend + on the architecture and/or the file type. + )doc"); + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNeeded.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNeeded.cpp new file mode 100644 index 0000000..503609b --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNeeded.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include + +#include "enums_wrapper.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/Needed.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + using NEED = Needed::NEED; + nb::class_ + Class(m, "Needed", + R"doc( + This class represents the ``GNU_PROPERTY_1_NEEDED`` note property + which provides information about additional features the object file + needs at runtime. + )doc"_doc); + + enum_(Class, "NEED") + .value("NEED", NEED::UNKNOWN, "") + .value("INDIRECT_EXTERN_ACCESS", NEED::INDIRECT_EXTERN_ACCESS, + "The object needs indirect external access") + ; + + Class + .def_prop_ro("needs", &Needed::needs, + R"doc( + Return the list of the needed features. + )doc"_doc); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNoteNoCopyOnProtected.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNoteNoCopyOnProtected.cpp new file mode 100644 index 0000000..25eb8b0 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyNoteNoCopyOnProtected.cpp @@ -0,0 +1,35 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/NoteNoCopyOnProtected.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ Class( + m, "NoteNoCopyOnProtected", + R"doc( + This class provides an interface over the ``GNU_PROPERTY_NO_COPY_ON_PROTECTED`` + property. This property indicates that the linker shouldn't copy relocations + against protected symbols. + )doc"_doc + ); + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyStackSize.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyStackSize.cpp new file mode 100644 index 0000000..43fa1ce --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyStackSize.cpp @@ -0,0 +1,33 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/StackSize.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "StackSize", + R"doc( + This class provides an interface over the ``GNU_PROPERTY_STACK_SIZE`` property + This property can be used by the loader to raise the stack limit. + )doc") + .def_prop_ro("stack_size", &StackSize::stack_size); + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86Features.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86Features.cpp new file mode 100644 index 0000000..fd0f0ab --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86Features.cpp @@ -0,0 +1,87 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include + +#include "enums_wrapper.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/properties/X86Feature.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ Class(m, "X86Features", + R"doc( + This class interfaces the different ``GNU_PROPERTY_X86_FEATURE_*`` + properties which includes: + + - ``GNU_PROPERTY_X86_FEATURE_1_AND`` + - ``GNU_PROPERTY_X86_FEATURE_2_USED`` + - ``GNU_PROPERTY_X86_FEATURE_2_NEEDED`` + )doc"_doc + ); + Class + .def_prop_ro("features", &X86Features::features, + R"doc( + List of the features as a pair of (:class:`~.FLAG`, :class:`~.FEATURE`). + )doc"_doc + ); + +# define ENTRY(X,D) .value(to_string(X86Features::FLAG::X), X86Features::FLAG::X, D) + enum_(Class, "FLAG", + R"doc( + Flag according to the ``_AND``, ``_USED`` or ``_NEEDED`` suffixes + )doc"_doc + ) + ENTRY(NONE, "For the original ``GNU_PROPERTY_X86_FEATURE_1_AND`` property") + ENTRY(NEEDED, "For the original ``GNU_PROPERTY_X86_FEATURE_2_NEEDED`` property") + ENTRY(USED, "For the original ``GNU_PROPERTY_X86_FEATURE_2_USED`` property") + ; +# undef ENTRY + +# define ENTRY(X) .value(to_string(X86Features::FEATURE::X), X86Features::FEATURE::X) + enum_(Class, "FEATURE", + R"doc( + Features provided by these different properties + )doc" + ) + ENTRY(UNKNOWN) + ENTRY(IBT) + ENTRY(SHSTK) + ENTRY(LAM_U48) + ENTRY(LAM_U57) + ENTRY(X86) + ENTRY(X87) + ENTRY(MMX) + ENTRY(XMM) + ENTRY(YMM) + ENTRY(ZMM) + ENTRY(FXSR) + ENTRY(XSAVE) + ENTRY(XSAVEOPT) + ENTRY(XSAVEC) + ENTRY(TMM) + ENTRY(MASK) + ; +# undef ENTRY +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86ISA.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86ISA.cpp new file mode 100644 index 0000000..a545b1c --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/properties/pyX86ISA.cpp @@ -0,0 +1,99 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include +#include + +#include "LIEF/ELF/NoteDetails/properties/X86ISA.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ Class(m, "X86ISA", + R"doc( + This class interfaces the different ``GNU_PROPERTY_X86_ISA_*`` + properties which includes: + + - ``GNU_PROPERTY_X86_ISA_1_USED`` + - ``GNU_PROPERTY_X86_ISA_1_NEEDED`` + - ``GNU_PROPERTY_X86_COMPAT_ISA_1_USED`` + - ``GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED`` + - ``GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED`` + - ``GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED`` + )doc"_doc + ); + Class + .def_prop_ro("values", &X86ISA::values, + R"doc( + List of the ISA values in this property + )doc" + ); + +# define ENTRY(X) .value(to_string(X86ISA::FLAG::X), X86ISA::FLAG::X) + enum_(Class, "FLAG") + ENTRY(NONE) + ENTRY(NEEDED) + ENTRY(USED) + ; +# undef ENTRY + +# define ENTRY(X) .value(to_string(X86ISA::ISA::X), X86ISA::ISA::X) + enum_(Class, "ISA") + ENTRY(UNKNOWN) + ENTRY(BASELINE) + ENTRY(V2) + ENTRY(V3) + ENTRY(V4) + ENTRY(CMOV) + ENTRY(FMA) + ENTRY(I486) + ENTRY(I586) + ENTRY(I686) + ENTRY(SSE) + ENTRY(SSE2) + ENTRY(SSE3) + ENTRY(SSSE3) + ENTRY(SSE4_1) + ENTRY(SSE4_2) + ENTRY(AVX) + ENTRY(AVX2) + ENTRY(AVX512F) + ENTRY(AVX512CD) + ENTRY(AVX512ER) + ENTRY(AVX512PF) + ENTRY(AVX512VL) + ENTRY(AVX512DQ) + ENTRY(AVX512BW) + ENTRY(AVX512_4FMAPS) + ENTRY(AVX512_4VNNIW) + ENTRY(AVX512_BITALG) + ENTRY(AVX512_IFMA) + ENTRY(AVX512_VBMI) + ENTRY(AVX512_VBMI2) + ENTRY(AVX512_VNNI) + ENTRY(AVX512_BF16) + ; +# undef ENTRY + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyAndroidIdent.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyAndroidIdent.cpp new file mode 100644 index 0000000..89e6ec7 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyAndroidIdent.cpp @@ -0,0 +1,47 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/AndroidIdent.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "AndroidIdent") + .def_prop_rw("sdk_version", + nb::overload_cast<>(&AndroidIdent::sdk_version, nb::const_), + nb::overload_cast(&AndroidIdent::sdk_version), + "Target SDK platform"_doc) + + .def_prop_rw("ndk_version", + nb::overload_cast<>(&AndroidIdent::ndk_version, nb::const_), + nb::overload_cast(&AndroidIdent::ndk_version), + "Android NDK version used to build the current binary"_doc) + + .def_prop_rw("ndk_build_number", + nb::overload_cast<>(&AndroidIdent::ndk_build_number, nb::const_), + nb::overload_cast(&AndroidIdent::ndk_build_number), + "Android NDK build number"_doc) + + LIEF_DEFAULT_STR(AndroidIdent); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteAbi.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteAbi.cpp new file mode 100644 index 0000000..d53fdef --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteAbi.cpp @@ -0,0 +1,64 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/NoteAbi.hpp" +#include "enums_wrapper.hpp" +#include "pyErr.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ nabi(m, "NoteAbi", + R"doc( + Class that wraps the `NT_GNU_ABI_TAG` note + )doc"_doc + ); + + #define ENTRY(X) .value(to_string(NoteAbi::ABI::X), NoteAbi::ABI::X) + enum_(nabi, "ABI", "ABI recognized by this note"_doc) + ENTRY(LINUX) + ENTRY(GNU) + ENTRY(SOLARIS2) + ENTRY(FREEBSD) + ENTRY(NETBSD) + ENTRY(SYLLABLE) + ENTRY(NACL) + ; + #undef ENTRY + + nabi + .def_prop_ro("abi", + [] (const NoteAbi& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&NoteAbi::abi, nb::const_), self); + }, + R"doc(Return the target :class:`~.ABI`)doc"_doc) + + .def_prop_ro("version", + [] (const NoteAbi& self) { + return LIEF::py::value_or_none(nb::overload_cast<>(&NoteAbi::version, nb::const_), self); + }, + "Return the target version as ``(Major, Minor, Patch)``"_doc) + + LIEF_DEFAULT_STR(NoteAbi); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteGnuProperty.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteGnuProperty.cpp new file mode 100644 index 0000000..990bd26 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyNoteGnuProperty.cpp @@ -0,0 +1,91 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/NoteDetails/NoteGnuProperty.hpp" +#include "LIEF/ELF/NoteDetails/properties/AArch64Feature.hpp" +#include "LIEF/ELF/NoteDetails/properties/AArch64PAuth.hpp" +#include "LIEF/ELF/NoteDetails/properties/X86Feature.hpp" +#include "LIEF/ELF/NoteDetails/properties/X86ISA.hpp" +#include "LIEF/ELF/NoteDetails/properties/StackSize.hpp" +#include "LIEF/ELF/NoteDetails/properties/NoteNoCopyOnProtected.hpp" +#include "LIEF/ELF/NoteDetails/properties/Generic.hpp" +#include "LIEF/ELF/NoteDetails/properties/Needed.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ Class(m, "NoteGnuProperty", + R"doc( + This object represents the `NT_GNU_PROPERTY_TYPE_0` note. + )doc"_doc); + + nb::class_ Property(Class, "Property", + R"doc( + This class wraps the different properties that can be used in a + `NT_GNU_PROPERTY_TYPE_0` note + )doc"_doc); + Property + .def_prop_ro("type", &NoteGnuProperty::Property::type) + LIEF_DEFAULT_STR(NoteGnuProperty::Property); + +# define ENTRY(X) .value(to_string(NoteGnuProperty::Property::TYPE::X), NoteGnuProperty::Property::TYPE::X) + enum_(Property, "TYPE", + R"doc( + LIEF's mirror types of the original `GNU_PROPERTY_` values + )doc"_doc) + ENTRY(UNKNOWN) + ENTRY(GENERIC) + ENTRY(AARCH64_FEATURES) + ENTRY(AARCH64_PAUTH) + ENTRY(STACK_SIZE) + ENTRY(NO_COPY_ON_PROTECTED) + ENTRY(X86_ISA) + ENTRY(X86_FEATURE) + ENTRY(NEEDED) + ; +# undef ENTRY + + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); + + Class + .def_prop_ro("properties", &NoteGnuProperty::properties, + R"doc( + Return the properties as a list of Property + )doc") + .def("find", &NoteGnuProperty::find, + R"doc( + Find the property with the given type or return None + )doc") + LIEF_DEFAULT_STR(NoteGnuProperty); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyQNXStack.cpp b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyQNXStack.cpp new file mode 100644 index 0000000..b661b24 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/NoteDetails/pyQNXStack.cpp @@ -0,0 +1,47 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/NoteDetails/QNXStack.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "QNXStack") + .def_prop_rw("stack_size", + nb::overload_cast<>(&QNXStack::stack_size, nb::const_), + nb::overload_cast(&QNXStack::stack_size), + "Size of the stack"_doc) + + .def_prop_rw("stack_allocated", + nb::overload_cast<>(&QNXStack::stack_allocated, nb::const_), + nb::overload_cast(&QNXStack::stack_allocated), + "Size of the stack pre-allocated (upfront)"_doc) + + .def_prop_rw("is_executable", + nb::overload_cast<>(&QNXStack::is_executable, nb::const_), + nb::overload_cast(&QNXStack::set_is_executable), + "Whether the stack is executable"_doc) + + LIEF_DEFAULT_STR(QNXStack); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyBinary.cpp b/vendor/lief/api/python/src/ELF/objects/pyBinary.cpp new file mode 100644 index 0000000..192b1fc --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyBinary.cpp @@ -0,0 +1,927 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "nanobind/utils.hpp" +#include +#include +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/extra/stl/pathlike.h" + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/Binary.hpp" +#include "LIEF/ELF/Builder.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" +#include "LIEF/ELF/DynamicEntryArray.hpp" +#include "LIEF/ELF/DynamicEntryFlags.hpp" +#include "LIEF/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/ELF/DynamicEntryRpath.hpp" +#include "LIEF/ELF/DynamicEntryRunPath.hpp" +#include "LIEF/ELF/DynamicSharedObject.hpp" +#include "LIEF/ELF/GnuHash.hpp" +#include "LIEF/ELF/Note.hpp" +#include "LIEF/ELF/Relocation.hpp" +#include "LIEF/ELF/Section.hpp" +#include "LIEF/ELF/Segment.hpp" +#include "LIEF/ELF/Symbol.hpp" +#include "LIEF/ELF/SymbolVersion.hpp" +#include "LIEF/ELF/SymbolVersionDefinition.hpp" +#include "LIEF/ELF/SymbolVersionRequirement.hpp" +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" +#include "LIEF/ELF/SysvHash.hpp" + +#include "pyIterator.hpp" +#include "pyErr.hpp" +#include "pySafeString.hpp" + +namespace LIEF::ELF::py { +using namespace LIEF::py; + +template<> +void create(nb::module_& m) { + nb::class_ bin(m, "Binary", + R"delim( + Class which represents an ELF binary + )delim"_doc); + + init_ref_iterator(bin, "it_notes"); + init_ref_iterator(bin, "it_symbols_version_requirement"); + init_ref_iterator(bin, "it_symbols_version_definition"); + init_ref_iterator(bin, "it_segments"); + init_ref_iterator(bin, "it_sections"); + init_ref_iterator(bin, "it_dynamic_entries"); + init_ref_iterator(bin, "it_symbols_version"); + + // We don't need to register it_object_relocations, it_dynamic_relocations + // as it it the same underlying type + init_ref_iterator(bin, "it_filter_relocation"); + init_ref_iterator(bin, "it_relocations"); + + init_ref_iterator(bin, "it_dyn_symtab_symbols"); + init_ref_iterator(bin, "it_symbols"); // For it_dynamic_symbols / it_symtab_symbols + init_ref_iterator(bin, "it_filter_symbols"); // For it_imported_symbols + + nb::enum_(bin, "PHDR_RELOC", R"delim( + This enum describes the different ways to relocate the segments table. + )delim"_doc) + .value("AUTO", Binary::PHDR_RELOC::AUTO, + R"delim( + Defer the choice of the layout to LIEF. + )delim"_doc) + .value("PIE_SHIFT", Binary::PHDR_RELOC::PIE_SHIFT, + R"delim( + The content of the binary right after the segments table is shifted + and the relocations are updated accordingly. + This kind of shift only works with PIE binaries. + )delim"_doc) + .value("BSS_END", Binary::PHDR_RELOC::BSS_END, + R"delim( + The new segments table is relocated right after the first bss-like + segments. + )delim"_doc) + .value("FILE_END", Binary::PHDR_RELOC::BINARY_END, + R"delim( + The new segments table is relocated at the end of the binary. + )delim"_doc) + .value("SEGMENT_GAP", Binary::PHDR_RELOC::SEGMENT_GAP, + R"delim( + The new segments table is relocated between two LOAD segments. + This kind of relocation is only doable when there is an alignment + enforcement. + )delim"_doc); + + nb::enum_(bin, "SEC_INSERT_POS", R"delim( + This enum defines where the content of a newly added section should be + inserted. + )delim"_doc) + .value("AUTO", Binary::SEC_INSERT_POS::AUTO, + "Defer the choice to LIEF"_doc + ) + .value("POST_SECTION", Binary::SEC_INSERT_POS::POST_SECTION, + R"doc( + Insert the section after the last valid offset in the **segments** table. + + With this choice, the section is inserted after the loaded content but + before any debug information. + )doc"_doc + ) + .value("POST_SEGMENT", Binary::SEC_INSERT_POS::POST_SEGMENT, + R"doc( + Insert the section after the last valid offset in the **section** table. + + With this choice, the section is inserted at the very end of the binary. + )doc"_doc + ) + ; + + bin + .def_prop_ro("type", + &Binary::type, + "Return the binary's " RST_CLASS_REF(lief.ELF.ELF_CLASS) ""_doc) + + .def_prop_ro("header", + nb::overload_cast<>(&Binary::header), + "Return " RST_CLASS_REF(lief.ELF.Header) " object"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("sections", + nb::overload_cast<>(&Binary::sections), + "Return an iterator over binary's " RST_CLASS_REF(lief.ELF.Section) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("segments", + nb::overload_cast<>(&Binary::segments), + "Return an iterator to binary's " RST_CLASS_REF(lief.ELF.Segment) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("dynamic_entries", + nb::overload_cast<>(&Binary::dynamic_entries), + "Return an iterator to " RST_CLASS_REF(lief.ELF.DynamicEntry) " entries"_doc, + nb::keep_alive<0, 1>()) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.ELF.DynamicEntry) " in the binary"_doc, + "dynamic_entry", + nb::rv_policy::reference_internal) + + .def_prop_ro("symtab_symbols", + nb::overload_cast<>(&Binary::symtab_symbols), + "Return an iterator to static " RST_CLASS_REF(lief.ELF.Symbol) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("dynamic_symbols", + nb::overload_cast<>(&Binary::dynamic_symbols), + "Return an iterator to dynamic " RST_CLASS_REF(lief.ELF.Symbol) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Binary::symbols), + "Return an iterator over both **static** and **dynamic** " RST_CLASS_REF(lief.ELF.Symbol) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("exported_symbols", + nb::overload_cast<>(&Binary::exported_symbols), + "Return dynamic " RST_CLASS_REF(lief.ELF.Symbol) " which are exported"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("imported_symbols", + nb::overload_cast<>(&Binary::imported_symbols), + "Return dynamic " RST_CLASS_REF(lief.ELF.Symbol) " which are imported"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("dynamic_relocations", + nb::overload_cast<>(&Binary::dynamic_relocations), + "Return an iterator over dynamic " RST_CLASS_REF(lief.ELF.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def("add_dynamic_relocation", + &Binary::add_dynamic_relocation, R"delim( + Add a new *dynamic* relocation. + + We consider a dynamic relocation as a relocation which is not plt-related. + + See: :meth:`lief.ELF.Binary.add_pltgot_relocation` + )delim"_doc, + "relocation"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add_pltgot_relocation", + &Binary::add_pltgot_relocation, R"delim( + Add a .plt.got relocation. This kind of relocation is usually + associated with a PLT stub that aims at resolving the underlying symbol. + + See: :meth:`lief.ELF.Binary.add_dynamic_relocation` + )delim"_doc, + "relocation"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add_object_relocation", + &Binary::add_object_relocation, + R"delim( + Add relocation for object file (.o) + + The first parameter is the relocation to add while the second parameter + is the :class:`~lief.ELF.Section` associated with the relocation. + + If there is an error, this function returns a nullptr. Otherwise, it returns + the relocation added. + )delim"_doc, + "relocation"_a, "section"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def_prop_ro("pltgot_relocations", + nb::overload_cast<>(&Binary::pltgot_relocations), + "Return an iterator over PLT/GOT " RST_CLASS_REF(lief.ELF.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("object_relocations", + nb::overload_cast<>(&Binary::object_relocations), + "Return an iterator over object " RST_CLASS_REF(lief.ELF.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Binary::relocations), + "Return an iterator over **all** " RST_CLASS_REF(lief.ELF.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("symbols_version", + nb::overload_cast<>(&Binary::symbols_version), + "Return an iterator over " RST_CLASS_REF(lief.ELF.SymbolVersion) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("symbols_version_requirement", + nb::overload_cast<>(&Binary::symbols_version_requirement), + "Return an iterator to " RST_CLASS_REF(lief.ELF.SymbolVersionRequirement) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("symbols_version_definition", + nb::overload_cast<>(&Binary::symbols_version_definition), + "Return an iterator to " RST_CLASS_REF(lief.ELF.SymbolVersionDefinition) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("use_gnu_hash", + &Binary::use_gnu_hash, + "``True`` if GNU hash is used"_doc) + + .def_prop_ro("gnu_hash", + &Binary::gnu_hash, + "Return the " RST_CLASS_REF(lief.ELF.GnuHash) " object\n\n" + "Hashes are used by the loader to speed up symbol resolution (GNU Version)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("use_sysv_hash", + &Binary::use_sysv_hash, + "``True`` if SYSV hash is used") + + .def_prop_ro("sysv_hash", + &Binary::sysv_hash, + "Return the " RST_CLASS_REF(lief.ELF.SysvHash) " object\n\n" + "Hashes are used by the loader to speed up symbol resolution (SYSV version)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("imagebase", + &Binary::imagebase, + "Return the program image base. (e.g. ``0x400000``)"_doc) + + .def_prop_ro("virtual_size", + &Binary::virtual_size, + "Return the size of the mapped binary"_doc) + + .def_prop_ro("is_pie", + &Binary::is_pie, + R"delim( + Check if the binary has been compiled with `-fpie -pie` flags + + To do so we check if there is a `PT_INTERP` segment and if + the binary type is `ET_DYN` (Shared object) + )delim"_doc) + + .def_prop_ro("has_interpreter", + &Binary::has_interpreter, + "Check if the binary uses a loader (also named linker or interpreter)"_doc) + + .def_prop_ro("functions", + &Binary::functions, + "List of the functions found in the binary"_doc) + + .def_prop_rw("interpreter", + nb::overload_cast<>(&Binary::interpreter, nb::const_), + nb::overload_cast(&Binary::interpreter), + "ELF interpreter (loader) if any. (e.g. ``/lib64/ld-linux-x86-64.so.2``)"_doc) + + .def("section_from_offset", + nb::overload_cast(&Binary::section_from_offset), + R"delim( + Return the :class:`~lief.ELF.Section` which encompasses the given offset. + It returns None if a section can't be found. + + If ``skip_nobits`` is set (which is the case by default), this function won't + consider sections for which the type is ``SHT_NOBITS`` (like ``.bss, .tbss, ...``) + )delim"_doc, + "offset"_a, "skip_nobits"_a = true, + nb::rv_policy::reference_internal) + + .def("section_from_virtual_address", + nb::overload_cast(&Binary::section_from_virtual_address), + R"delim( + Return the :class:`~lief.ELF.Section` which encompasses the given virtual address. + It returns None if a section can't be found. + + If ``skip_nobits`` is set (which is the case by default), this function won't + consider sections for which the type is ``SHT_NOBITS`` (like ``.bss, .tbss, ...``) + )delim"_doc, + "address"_a, "skip_nobits"_a = true, + nb::rv_policy::reference_internal) + + .def("segment_from_virtual_address", + nb::overload_cast(&Binary::segment_from_virtual_address), + R"delim( + Return the :class:`~lief.ELF.Segment` which encompasses the given virtual address. + It returns None if a segment can't be found. + )delim"_doc, + "address"_a, + nb::rv_policy::reference_internal) + + .def("segment_from_offset", + nb::overload_cast(&Binary::segment_from_offset), + R"delim( + Return the :class:`~lief.ELF.Segment` which encompasses the given offset. + It returns None if a segment can't be found. + )delim"_doc, + "offset"_a, + nb::rv_policy::reference_internal) + + .def("get", + nb::overload_cast(&Binary::get), + R"delim( + Return the first binary's :class:`~lief.ELF.DynamicEntry` from the given + :class:`~lief.ELF.DynamicEntry.TAG`. + + It returns None if the dynamic entry can't be found. + )delim"_doc, + "tag"_a, + nb::rv_policy::reference_internal) + + .def("get", + nb::overload_cast(&Binary::get), + R"delim( + Return the first binary's :class:`~lief.ELF.Segment` from the given + :class:`~lief.ELF.SEGMENT_TYPES` + + It returns None if the segment can't be found. + )delim"_doc, + "type"_a, + nb::rv_policy::reference_internal) + + .def("get", + nb::overload_cast(&Binary::get), + R"delim( + Return the first binary's :class:`~lief.ELF.Note` from the given + :class:`~lief.ELF.Note.TYPE`. + + It returns None if the note can't be found. + )delim"_doc, + "type"_a, + nb::rv_policy::reference_internal) + + .def("get", + nb::overload_cast(&Binary::get), + R"delim( + Return the first binary's :class:`~lief.ELF.Section` from the given + :class:`~lief.ELF.ELF_SECTION_TYPES` + + It returns None if the section can't be found. + )delim"_doc, + "type"_a, + nb::rv_policy::reference_internal) + + .def("has", + nb::overload_cast(&Binary::has, nb::const_), + R"delim( + Check if there exists a :class:`~lief.ELF.DynamicEntry` with the given + :class:`~lief.ELF.DynamicEntry.TAG` + )delim"_doc, + "tag"_a) + + .def("has", + nb::overload_cast(&Binary::has, nb::const_), + "Check if a " RST_CLASS_REF(lief.ELF.Segment) " of *type* (" RST_CLASS_REF(lief.ELF.SEGMENT_TYPES) ") exists"_doc, + "type"_a) + + .def("has", + nb::overload_cast(&Binary::has, nb::const_), + "Check if a " RST_CLASS_REF(lief.ELF.Note) " of *type* (" RST_CLASS_REF(lief.ELF.Note.TYPE) ") exists"_doc, + "type"_a) + + .def("has", + nb::overload_cast(&Binary::has, nb::const_), + "Check if a " RST_CLASS_REF(lief.ELF.Section) " of *type* (" RST_CLASS_REF(lief.ELF.SECTION_TYPES) ") exists"_doc, + "type"_a) + + .def("patch_pltgot", + nb::overload_cast(&Binary::patch_pltgot), + "Patch the imported symbol's name with the ``address``"_doc, + "symbol_name"_a, "address"_a, nb::lock_self()) + + .def("patch_pltgot", + nb::overload_cast(&Binary::patch_pltgot), + "Patch the imported " RST_CLASS_REF(lief.ELF.Symbol) " with the ``address``"_doc, + "symbol"_a, "address"_a, nb::lock_self()) + + .def("dynsym_idx", + nb::overload_cast(&Binary::dynsym_idx, nb::const_), + R"doc( + Get the symbol index in the **dynamic** symbol from the given name or + return -1 if the symbol does not exist. + )doc"_doc, "name"_a) + + .def("dynsym_idx", + nb::overload_cast(&Binary::dynsym_idx, nb::const_), + R"doc( + Get the symbol index in the **dynamic** symbol table for the given symbol + or return -1 if the symbol does not exist + )doc"_doc, "symbol"_a) + + .def("symtab_idx", + nb::overload_cast(&Binary::symtab_idx, nb::const_), + R"doc( + Get the symbol index in the ``.symtab`` section from the given name or + return -1 if the symbol does not exist. + )doc"_doc, "name"_a) + + .def("symtab_idx", + nb::overload_cast(&Binary::symtab_idx, nb::const_), + R"doc( + Get the symbol index in the ``.symtab`` section or return -1 if the + symbol does not exist + )doc"_doc, "symbol"_a) + + .def("has_section", + &Binary::has_section, + "Check if a " RST_CLASS_REF(lief.ELF.Section) " with the given name exists in the binary"_doc, + "section_name"_a) + + .def("has_section_with_offset", + &Binary::has_section_with_offset, + "Check if a " RST_CLASS_REF(lief.ELF.Section) " that encompasses the given offset exists"_doc, + "offset"_a) + + .def("has_section_with_va", + &Binary::has_section_with_va, + "Check if a " RST_CLASS_REF(lief.ELF.Section) " that encompasses the given virtual address exists"_doc, + "virtual_address"_a) + + .def("get_section", + nb::overload_cast(&Binary::get_section), + R"delim( + Return the :class:`~lief.ELF.Section` with the given ``name`` + + It returns None if the section can't be found. + )delim"_doc, + "section_name"_a, + nb::rv_policy::reference_internal) + + .def("add_symtab_symbol", + &Binary::add_symtab_symbol, + "Add a **static** " RST_CLASS_REF(lief.ELF.Symbol) " to the binary"_doc, + "symbol"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add_dynamic_symbol", + nb::overload_cast(&Binary::add_dynamic_symbol), + R"delim( + Add a **dynamic** :class:`~lief.ELF.Symbol` to the binary + + The function also takes an optional :class:`lief.ELF.SymbolVersion` + )delim"_doc, + "symbol"_a, "symbol_version"_a = nullptr, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("virtual_address_to_offset", + [] (const Binary& self, uint64_t address) { + return error_or(&Binary::virtual_address_to_offset, self, address); + }, + "Convert the virtual address to a file offset"_doc, + "virtual_address"_a) + + .def("add", + nb::overload_cast(&Binary::add), + R"delim( + Add the given :class:`~lief.ELF.Section` to the binary. + + If the section does not aim at being loaded in memory, + the ``loaded`` parameter has to be set to ``False`` (default: ``True``) + )delim"_doc, + "section"_a, "loaded"_a = true, "pos"_a = Binary::SEC_INSERT_POS::AUTO, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.ELF.Segment) " in the binary"_doc, + "segment"_a, "base"_a = 0, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.ELF.Note) " in the binary"_doc, + "note"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("replace", + nb::overload_cast(&Binary::replace), + R"delim( + Replace the :class:`~lief.ELF.Segment` given in 2nd parameter with the + :class:`~lief.ELF.Segment` given in the first parameter and return the updated segment. + + .. warning:: + + The ``original_segment`` is no longer valid after this function + )delim"_doc, + "new_segment"_a, "original_segment"_a, "base"_a = 0, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("extend", + nb::overload_cast(&Binary::extend), + "Extend the given " RST_CLASS_REF(lief.ELF.Segment) " by the given size"_doc, + "segment"_a, "size"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("extend", + nb::overload_cast(&Binary::extend), + "Extend the given " RST_CLASS_REF(lief.ELF.Section) " by the given size"_doc, + "segment"_a, "size"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove the given " RST_CLASS_REF(lief.ELF.DynamicEntry) " from the dynamic table"_doc, + "dynamic_entry"_a, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove **all** the " RST_CLASS_REF(lief.ELF.DynamicEntry) " with the given " RST_CLASS_REF(lief.ELF.DynamicEntry.TAG) ""_doc, + "tag"_a, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove the given " RST_CLASS_REF(lief.ELF.Section) ". The ``clear`` parameter specifies whether or not " + "we must fill its content with ``0`` before removing"_doc, + "section"_a, "clear"_a = false, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + R"doc( + Remove the segment provided in parameter. If ``clear`` is set, the + original content of the segment will be filled with zeros before removal. + )doc"_doc, "segment"_a, "clear"_a = false, nb::lock_self()) + + + .def("remove", + nb::overload_cast(&Binary::remove), + R"doc( + Remove **all** segments with the given type. If ``clear`` is set, the + original content of the segment will be filled with zeros before removal. + )doc"_doc, "type"_a, "clear"_a = false, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove the given " RST_CLASS_REF(lief.ELF.Note) ""_doc, + "note"_a, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove **all** the " RST_CLASS_REF(lief.ELF.Note) " with the given " RST_CLASS_REF(lief.ELF.Note.TYPE) ""_doc, + "type"_a, nb::lock_self()) + + .def_prop_ro("has_notes", + &Binary::has_notes, + "``True`` if the binary contains notes"_doc) + + .def_prop_ro("notes", + nb::overload_cast<>(&Binary::notes), + "Return an iterator over the " RST_CLASS_REF(lief.ELF.Note) " entries"_doc, + nb::keep_alive<0, 1>()) + + .def("strip", + &Binary::strip, + "Strip the binary"_doc, nb::lock_self()) + + .def("permute_dynamic_symbols", + &Binary::permute_dynamic_symbols, + "Apply the given permutation on the dynamic symbols table"_doc, + "permutation"_a, nb::lock_self()) + + .def("write", + [] (Binary& self, nb::PathLike path) { return self.write(path); }, + "Rebuild the binary and write it in a file"_doc, + "output"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("write", + [] (Binary& self, nb::PathLike path, const Builder::config_t& config) { + return self.write(path, config); + }, + "Rebuild the binary with the given configuration and write it in a file"_doc, + "output"_a, "config"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("write_to_bytes", [] (Binary& bin, const Builder::config_t& config) -> nb::bytes { + std::ostringstream out; + bin.write(out, config); + return nb::to_bytes(out.str()); + }, "config"_a, nb::lock_self()) + + .def("write_to_bytes", [] (Binary& bin) -> nb::bytes { + std::ostringstream out; + bin.write(out); + return nb::to_bytes(out.str()); + }, nb::lock_self()) + + .def_prop_ro("last_offset_section", + &Binary::last_offset_section, + "Return the last offset used in binary according to **sections table**"_doc) + + .def_prop_ro("last_offset_segment", + &Binary::last_offset_segment, + "Return the last offset used in binary according to **segments table**"_doc) + + .def_prop_ro("next_virtual_address", + &Binary::next_virtual_address, + "Return the next virtual address available"_doc) + + .def("add_library", + &Binary::add_library, + "Add a library with the given name as dependency"_doc, + "library_name"_a, nb::lock_self()) + + .def("has_library", + &Binary::has_library, + "Check if the given library name exists in the current binary"_doc, + "library_name"_a) + + .def("remove_library", + &Binary::remove_library, + "Remove the given library"_doc, + "library_name"_a, nb::lock_self()) + + .def("get_library", + nb::overload_cast(&Binary::get_library), + R"delim( + Return the :class:`~lief.ELF.DynamicEntryLibrary` with the given ``name`` + + It returns None if the library can't be found. + )delim"_doc, + "library_name"_a, + nb::rv_policy::reference_internal) + + .def("has_dynamic_symbol", + &Binary::has_dynamic_symbol, + "Check if the symbol with the given ``name`` exists in the **dynamic** symbol table"_doc, + "symbol_name"_a) + + .def("get_dynamic_symbol", + nb::overload_cast(&Binary::get_dynamic_symbol), + R"delim( + Get the dynamic symbol from the given name. + + It returns None if it can't be found. + )delim"_doc, + "symbol_name"_a, + nb::rv_policy::reference_internal) + + .def("has_symtab_symbol", + &Binary::has_symtab_symbol, + "Check if the symbol with the given ``name`` exists in the **static** symbol table"_doc, + "symbol_name"_a) + + .def("get_symtab_symbol", + nb::overload_cast(&Binary::get_symtab_symbol), + R"delim( + Get the **static** symbol from the given ``name``. + + It returns None if it can't be found. + )delim"_doc, + "symbol_name"_a, + nb::rv_policy::reference_internal) + + .def("get_strings", + nb::overload_cast(&Binary::strings, nb::const_), + "Return list of strings used in the current ELF file with a minimal size given in first parameter (Default: 5)\n" + "It looks for strings in the ``.rodata`` section"_doc, + "min_size"_a = 5, + nb::rv_policy::move) + + .def_prop_ro("strings", + [] (const Binary& bin) { + const std::vector& elf_strings = bin.strings(); + std::vector elf_strings_encoded; + elf_strings_encoded.reserve(elf_strings.size()); + + std::transform(std::begin(elf_strings), std::end(elf_strings), + std::back_inserter(elf_strings_encoded), + &safe_string); + + return elf_strings_encoded; + }, + "Return list of strings used in the current ELF file.\n" + "Basically this function looks for strings in the ``.rodata`` section"_doc, + nb::rv_policy::move) + + .def("remove_symtab_symbol", + nb::overload_cast(&Binary::remove_symtab_symbol), + "Remove the given " RST_CLASS_REF(lief.ELF.Symbol) " from the ``.symtab`` section"_doc, + nb::lock_self()) + + .def("remove_dynamic_symbol", + nb::overload_cast(&Binary::remove_dynamic_symbol), + "Remove the given " RST_CLASS_REF(lief.ELF.Symbol) " from the ``.dynsym`` section"_doc, + nb::lock_self()) + + .def("remove_dynamic_symbol", + nb::overload_cast(&Binary::remove_dynamic_symbol), + "Remove the " RST_CLASS_REF(lief.ELF.Symbol) " with the name given in parameter from the ``.dynsym`` section"_doc, + nb::lock_self()) + + .def("add_exported_function", + &Binary::add_exported_function, + "Create a symbol for the function at the given ``address`` and create an export"_doc, + "address"_a, "name"_a = "", + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("export_symbol", + nb::overload_cast(&Binary::export_symbol), + "Export the given symbol and create an entry if it doesn't exist"_doc, + "symbol"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("export_symbol", + nb::overload_cast(&Binary::export_symbol), + "Export the symbol with the given name and create an entry if it doesn't exist"_doc, + "symbol_name"_a, "value"_a = 0, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("get_relocation", + nb::overload_cast(&Binary::get_relocation), + "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given symbol name"_doc, + "symbol_name"_a, + nb::rv_policy::reference_internal) + + .def("get_relocation", + nb::overload_cast(&Binary::get_relocation), + "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given " RST_CLASS_REF(lief.ELF.Symbol) ""_doc, + "symbol"_a, + nb::rv_policy::reference_internal) + + .def("get_relocation", + nb::overload_cast(&Binary::get_relocation), + "Return the " RST_CLASS_REF(lief.ELF.Relocation) " associated with the given address"_doc, + "address"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("dtor_functions", + &Binary::dtor_functions, + "List of the binary destructors (typically, the functions located in the ``.fini_array``)"_doc) + + .def_prop_ro("eof_offset", + &Binary::eof_offset, + "Return the last offset used by the ELF binary according to both, the sections table " + "and the segments table."_doc) + + .def_prop_ro("has_overlay", + &Binary::has_overlay, + "True if data are appended to the end of the binary"_doc) + + .def_prop_ro("is_targeting_android", &Binary::is_targeting_android, + R"doc(True if the current binary is targeting Android)doc"_doc + ) + + .def("get_section_idx", [] (const Binary& self, const Section& sec) { + return error_or( + nb::overload_cast(&Binary::get_section_idx, nb::const_), + self, sec); + }, + R"doc(Find the index of the section given in the first parameter)doc"_doc + ) + + .def("get_section_idx", [] (const Binary& self, const std::string& name) { + return error_or( + nb::overload_cast(&Binary::get_section_idx, nb::const_), + self, name); + }, + R"doc(Find the index of the section with the name given in the first parameter)doc"_doc + ) + + .def_prop_rw("overlay", + nb::overload_cast<>(&Binary::overlay, nb::const_), + [] (Binary& self, nb::bytes& bytes) { + const auto* ptr = reinterpret_cast(bytes.c_str()); + std::vector buffer(ptr, ptr + bytes.size()); + self.overlay(std::move(buffer)); + }, + "Overlay data that is not part of the ELF format"_doc) + + .def("relocate_phdr_table", + &Binary::relocate_phdr_table, + R"delim( + Force relocating the segments table in a specific way + (see: :class:`~lief.ELF.Binary.PHDR_RELOC`). + + This function can be used to enforce a specific relocation of the + segments table. Upon successful relocation, the function returns + the offset of the relocated segments table. Otherwise, if the function + fails, it returns 0 + )delim"_doc, "type"_a = Binary::PHDR_RELOC::AUTO, nb::lock_self()) + + .def("get_relocated_dynamic_array", &Binary::get_relocated_dynamic_array, + R"doc( + Return the array defined by the given tag (e.g. + :attr:`~.DynamicEntry.TAG.INIT_ARRAY`) with relocations applied (if any) + )doc"_doc, + "array_tag"_a + ) + + .def("find_version_requirement", + nb::overload_cast(&Binary::find_version_requirement), + R"doc( + Try to find the :class:`~.SymbolVersionRequirement` associated with the given library + name (e.g. ``libc.so.6``) + )doc"_doc, "libname"_a, nb::rv_policy::reference_internal + ) + + .def("remove_version_requirement", &Binary::remove_version_requirement, + R"doc( + Deletes all required symbol versions linked to the specified library name. + The function returns true if the operation succeeds, false otherwise. + + .. warning:: + + To maintain consistency, this function also removes versions associated + with dynamic symbols that are linked to the specified library name. + )doc"_doc, "libname"_a, nb::lock_self() + ) + + .def(nb::self += Segment(), nb::rv_policy::reference_internal) + .def(nb::self += Section(), nb::rv_policy::reference_internal) + .def(nb::self += DynamicEntry(), nb::rv_policy::reference_internal) + .def("__iadd__", [] (Binary& self, const Note& note) { + self += note; + return &self; + }, nb::rv_policy::reference_internal) + .def(nb::self -= DynamicEntry(), nb::rv_policy::reference_internal) + .def(nb::self -= DynamicEntry::TAG(), nb::rv_policy::reference_internal) + .def("__isub__", [] (Binary& self, const Note& note) { + self -= note; + return &self; + }, nb::rv_policy::reference_internal) + .def(nb::self -= Note::TYPE(), nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&Binary::operator[]), + nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&Binary::operator[]), + nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&Binary::operator[]), + nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&Binary::operator[]), + nb::rv_policy::reference_internal) + + .def("__contains__", + nb::overload_cast(&Binary::has, nb::const_), + "Check if a " RST_CLASS_REF(lief.ELF.Segment) " of *type* (" RST_CLASS_REF(lief.ELF.SEGMENT_TYPES) ") exists"_doc) + + .def("__contains__", + nb::overload_cast(&Binary::has, nb::const_), + "Check if the " RST_CLASS_REF(lief.ELF.DynamicEntry) " associated with the given " RST_CLASS_REF(lief.ELF.DynamicEntry.TAG) " exists"_doc) + + .def("__contains__", + nb::overload_cast(&Binary::has, nb::const_), + "Check if the " RST_CLASS_REF(lief.ELF.Note) " associated with the given " RST_CLASS_REF(lief.ELF.Note.TYPE) " exists"_doc) + + .def("__contains__", + nb::overload_cast(&Binary::has, nb::const_), + "Check if the " RST_CLASS_REF(lief.ELF.Section) " associated with the given " RST_CLASS_REF(lief.ELF.SECTION_TYPES) " exists"_doc) + + LIEF_DEFAULT_STR(Binary); + +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyBuilder.cpp b/vendor/lief/api/python/src/ELF/objects/pyBuilder.cpp new file mode 100644 index 0000000..707bcb3 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyBuilder.cpp @@ -0,0 +1,100 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/Binary.hpp" +#include "LIEF/ELF/Builder.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ builder(m, "Builder", + R"delim( + Class which takes an :class:`lief.ELF.Binary` object and reconstructs a valid binary + )delim"_doc); + + nb::class_(builder, "config_t", + "Interface to tweak the " RST_CLASS_REF(lief.ELF.Builder) ""_doc) + .def(nb::init<>()) + .def_rw("force_relocate", &Builder::config_t::force_relocate, + "Force to relocate all the ELF structures that can be relocated (mostly for testing)"_doc) + + .def_rw("skip_dynamic", &Builder::config_t::skip_dynamic, + "Skip relocating the PT_DYNAMIC segment (only relevant if :attr:`~.force_relocate` is set)"_doc) + + .def_rw("dt_hash", &Builder::config_t::dt_hash, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.HASH`"_doc) + .def_rw("dyn_str", &Builder::config_t::dyn_str, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.STRTAB`"_doc) + .def_rw("dynamic_section", &Builder::config_t::dynamic_section, "Rebuild the `PT_DYNAMIC` segment"_doc) + .def_rw("fini_array", &Builder::config_t::fini_array, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.FINI_ARRAY`"_doc) + .def_rw("init_array", &Builder::config_t::init_array, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.INIT_ARRAY`"_doc) + .def_rw("interpreter", &Builder::config_t::interpreter, "Rebuild the `PT_INTERP` segment"_doc) + .def_rw("jmprel", &Builder::config_t::jmprel, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.JMPREL`"_doc) + .def_rw("notes", &Builder::config_t::notes, "Rebuild `PT_NOTES` segment(s)"_doc) + .def_rw("preinit_array", &Builder::config_t::preinit_array, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.PREINIT_ARRAY`"_doc) + .def_rw("relr", &Builder::config_t::relr, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.RELR`"_doc) + .def_rw("android_rela", &Builder::config_t::android_rela, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.ANDROID_RELA`"_doc) + .def_rw("rela", &Builder::config_t::rela, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.RELA`"_doc) + .def_rw("static_symtab", &Builder::config_t::static_symtab, "Rebuild `.symtab` section"_doc) + .def_rw("sym_verdef", &Builder::config_t::sym_verdef, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.VERDEF`"_doc) + .def_rw("sym_verneed", &Builder::config_t::sym_verneed, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.VERNEED`"_doc) + .def_rw("sym_versym", &Builder::config_t::sym_versym, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.VERSYM`"_doc) + .def_rw("symtab", &Builder::config_t::symtab, "Rebuild :attr:`~lief.ELF.DynamicEntry.TAG.SYMTAB`"_doc) + .def_rw("coredump_notes", &Builder::config_t::coredump_notes, "Rebuild the Coredump notes"_doc) + .def_rw("keep_empty_version_requirement", &Builder::config_t::keep_empty_version_requirement, + R"doc( + Remove entries in ``.gnu.version_r`` if they are not associated with at least + one version + )doc"_doc + ) + ; + + builder + .def(nb::init(), + "elf"_a) + + .def(nb::init(), + "elf"_a, "config"_a) + + .def("build", + [] (Builder& self) { + return self.build(); + }, + "Perform the build of the provided ELF binary"_doc, + nb::lock_self()) + + .def_prop_ro("config", &Builder::config, + "Configuration of the builder"_doc, + nb::rv_policy::reference_internal) + + .def("write", + nb::overload_cast(&Builder::write, nb::const_), + "Write the build result into the ``output`` file"_doc, + "output"_a, nb::lock_self()) + + .def("get_build", + &Builder::get_build, + "Return the build result as a ``list`` of bytes"_doc, + nb::lock_self(), + nb::rv_policy::reference_internal); + +} +} + diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntry.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntry.cpp new file mode 100644 index 0000000..3364ccb --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntry.cpp @@ -0,0 +1,231 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ entry(m, "DynamicEntry", + R"delim( + Class which represents an entry in the dynamic table + These entries are located in the ``.dynamic`` section or the ``PT_DYNAMIC`` segment + )delim"_doc); + + #define ENTRY(X) .value(to_string(DynamicEntry::TAG::X), DynamicEntry::TAG::X) + enum_(entry, "TAG") + ENTRY(UNKNOWN) + .value("NULL", DynamicEntry::TAG::DT_NULL_) + ENTRY(NEEDED) + ENTRY(PLTRELSZ) + ENTRY(PLTGOT) + ENTRY(HASH) + ENTRY(STRTAB) + ENTRY(SYMTAB) + ENTRY(RELA) + ENTRY(RELASZ) + ENTRY(RELAENT) + ENTRY(STRSZ) + ENTRY(SYMENT) + ENTRY(INIT) + ENTRY(FINI) + ENTRY(SONAME) + ENTRY(RPATH) + ENTRY(SYMBOLIC) + ENTRY(REL) + ENTRY(RELSZ) + ENTRY(RELENT) + ENTRY(PLTREL) + ENTRY(DEBUG_TAG) + ENTRY(TEXTREL) + ENTRY(JMPREL) + ENTRY(BIND_NOW) + ENTRY(INIT_ARRAY) + ENTRY(FINI_ARRAY) + ENTRY(INIT_ARRAYSZ) + ENTRY(FINI_ARRAYSZ) + ENTRY(RUNPATH) + ENTRY(FLAGS) + ENTRY(PREINIT_ARRAY) + ENTRY(PREINIT_ARRAYSZ) + ENTRY(SYMTAB_SHNDX) + ENTRY(RELRSZ) + ENTRY(RELR) + ENTRY(RELRENT) + ENTRY(GNU_HASH) + ENTRY(TLSDESC_PLT) + ENTRY(TLSDESC_GOT) + ENTRY(RELACOUNT) + ENTRY(RELCOUNT) + ENTRY(FLAGS_1) + ENTRY(VERSYM) + ENTRY(VERDEF) + ENTRY(VERDEFNUM) + ENTRY(VERNEED) + ENTRY(VERNEEDNUM) + ENTRY(AUXILIARY) + ENTRY(FILTER) + ENTRY(ANDROID_REL_OFFSET) + ENTRY(ANDROID_REL_SIZE) + ENTRY(ANDROID_REL) + ENTRY(ANDROID_RELSZ) + ENTRY(ANDROID_RELA) + ENTRY(ANDROID_RELASZ) + ENTRY(ANDROID_RELR) + ENTRY(ANDROID_RELRSZ) + ENTRY(ANDROID_RELRENT) + ENTRY(ANDROID_RELRCOUNT) + ENTRY(MIPS_RLD_VERSION) + ENTRY(MIPS_TIME_STAMP) + ENTRY(MIPS_ICHECKSUM) + ENTRY(MIPS_IVERSION) + ENTRY(MIPS_FLAGS) + ENTRY(MIPS_BASE_ADDRESS) + ENTRY(MIPS_MSYM) + ENTRY(MIPS_CONFLICT) + ENTRY(MIPS_LIBLIST) + ENTRY(MIPS_LOCAL_GOTNO) + ENTRY(MIPS_CONFLICTNO) + ENTRY(MIPS_LIBLISTNO) + ENTRY(MIPS_SYMTABNO) + ENTRY(MIPS_UNREFEXTNO) + ENTRY(MIPS_GOTSYM) + ENTRY(MIPS_HIPAGENO) + ENTRY(MIPS_RLD_MAP) + ENTRY(MIPS_DELTA_CLASS) + ENTRY(MIPS_DELTA_CLASS_NO) + ENTRY(MIPS_DELTA_INSTANCE) + ENTRY(MIPS_DELTA_INSTANCE_NO) + ENTRY(MIPS_DELTA_RELOC) + ENTRY(MIPS_DELTA_RELOC_NO) + ENTRY(MIPS_DELTA_SYM) + ENTRY(MIPS_DELTA_SYM_NO) + ENTRY(MIPS_DELTA_CLASSSYM) + ENTRY(MIPS_DELTA_CLASSSYM_NO) + ENTRY(MIPS_CXX_FLAGS) + ENTRY(MIPS_PIXIE_INIT) + ENTRY(MIPS_SYMBOL_LIB) + ENTRY(MIPS_LOCALPAGE_GOTIDX) + ENTRY(MIPS_LOCAL_GOTIDX) + ENTRY(MIPS_HIDDEN_GOTIDX) + ENTRY(MIPS_PROTECTED_GOTIDX) + ENTRY(MIPS_OPTIONS) + ENTRY(MIPS_INTERFACE) + ENTRY(MIPS_DYNSTR_ALIGN) + ENTRY(MIPS_INTERFACE_SIZE) + ENTRY(MIPS_RLD_TEXT_RESOLVE_ADDR) + ENTRY(MIPS_PERF_SUFFIX) + ENTRY(MIPS_COMPACT_SIZE) + ENTRY(MIPS_GP_VALUE) + ENTRY(MIPS_AUX_DYNAMIC) + ENTRY(MIPS_PLTGOT) + ENTRY(MIPS_RWPLT) + ENTRY(MIPS_RLD_MAP_REL) + ENTRY(MIPS_XHASH) + + ENTRY(AARCH64_BTI_PLT) + ENTRY(AARCH64_PAC_PLT) + ENTRY(AARCH64_VARIANT_PCS) + ENTRY(AARCH64_MEMTAG_MODE) + ENTRY(AARCH64_MEMTAG_HEAP) + ENTRY(AARCH64_MEMTAG_STACK) + ENTRY(AARCH64_MEMTAG_GLOBALS) + ENTRY(AARCH64_MEMTAG_GLOBALSSZ) + + ENTRY(HEXAGON_SYMSZ) + ENTRY(HEXAGON_VER) + ENTRY(HEXAGON_PLT) + + ENTRY(PPC_GOT) + ENTRY(PPC_OPT) + + ENTRY(PPC64_GLINK) + ENTRY(PPC64_OPT) + + ENTRY(RISCV_VARIANT_CC) + + ENTRY(X86_64_PLT) + ENTRY(X86_64_PLTSZ) + ENTRY(X86_64_PLTENT) + + ENTRY(IA_64_PLT_RESERVE) + ENTRY(IA_64_VMS_SUBTYPE) + ENTRY(IA_64_VMS_IMGIOCNT) + ENTRY(IA_64_VMS_LNKFLAGS) + ENTRY(IA_64_VMS_VIR_MEM_BLK_SIZ) + ENTRY(IA_64_VMS_IDENT) + ENTRY(IA_64_VMS_NEEDED_IDENT) + ENTRY(IA_64_VMS_IMG_RELA_CNT) + ENTRY(IA_64_VMS_SEG_RELA_CNT) + ENTRY(IA_64_VMS_FIXUP_RELA_CNT) + ENTRY(IA_64_VMS_FIXUP_NEEDED) + ENTRY(IA_64_VMS_SYMVEC_CNT) + ENTRY(IA_64_VMS_XLATED) + ENTRY(IA_64_VMS_STACKSIZE) + ENTRY(IA_64_VMS_UNWINDSZ) + ENTRY(IA_64_VMS_UNWIND_CODSEG) + ENTRY(IA_64_VMS_UNWIND_INFOSEG) + ENTRY(IA_64_VMS_LINKTIME) + ENTRY(IA_64_VMS_SEG_NO) + ENTRY(IA_64_VMS_SYMVEC_OFFSET) + ENTRY(IA_64_VMS_SYMVEC_SEG) + ENTRY(IA_64_VMS_UNWIND_OFFSET) + ENTRY(IA_64_VMS_UNWIND_SEG) + ENTRY(IA_64_VMS_STRTAB_OFFSET) + ENTRY(IA_64_VMS_SYSVER_OFFSET) + ENTRY(IA_64_VMS_IMG_RELA_OFF) + ENTRY(IA_64_VMS_SEG_RELA_OFF) + ENTRY(IA_64_VMS_FIXUP_RELA_OFF) + ENTRY(IA_64_VMS_PLTGOT_OFFSET) + ENTRY(IA_64_VMS_PLTGOT_SEG) + ENTRY(IA_64_VMS_FPMODE) + ; + #undef ENTRY + + entry + .def(nb::init<>(), + "Default constructor"_doc) + + .def(nb::init(), + "Constructor from a " RST_CLASS_REF(lief.ELF.DynamicEntry.TAG) " and value"_doc, + "tag"_a, "value"_a) + + .def_prop_rw("tag", + nb::overload_cast<>(&DynamicEntry::tag, nb::const_), + nb::overload_cast(&DynamicEntry::tag), + "Return the entry's " RST_CLASS_REF(lief.ELF.DynamicEntry.TAG) " which represent the entry type"_doc) + + .def_prop_rw("value", + nb::overload_cast<>(&DynamicEntry::value, nb::const_), + nb::overload_cast(&DynamicEntry::value), + R"delim( + Return the entry's value + + The meaning of the value strongly depends on the tag. + It can be an offset, an index, a flag, ... + )delim"_doc) + + LIEF_DEFAULT_STR(DynamicEntry); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryArray.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryArray.cpp new file mode 100644 index 0000000..a6cf37d --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryArray.cpp @@ -0,0 +1,84 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/DynamicEntryArray.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryArray", + R"delim( + Class that represents an array in the dynamic table. + This entry is associated with constructors: + - ``DT_PREINIT_ARRAY`` + - ``DT_INIT_ARRAY`` + - ``DT_FINI_ARRAY`` + + The underlying values are 64-bits integers to cover both: + ELF32 and ELF64 binaries. + )delim"_doc) + + .def(nb::init(), + "tag"_a, "array"_a) + + .def_prop_rw("array", + nb::overload_cast<>(&DynamicEntryArray::array, nb::const_), + nb::overload_cast&>(&DynamicEntryArray::array), + "Return the array as a list of integers"_doc, + nb::rv_policy::reference_internal) + + .def("insert", + &DynamicEntryArray::insert, + "Insert the given ``function`` at ``pos``"_doc, + "pos"_a, "function"_a, + nb::rv_policy::reference_internal) + + .def("append", + &DynamicEntryArray::append, + "Append the given ``function`` "_doc, + "function"_a, + nb::rv_policy::reference_internal) + + .def("remove", + &DynamicEntryArray::remove, + "Remove the given ``function`` "_doc, + "function"_a, + nb::rv_policy::reference_internal) + + .def(nb::self += uint64_t()) + .def(nb::self -= uint64_t()) + + .def("__getitem__", + nb::overload_cast(&DynamicEntryArray::operator[]), + nb::rv_policy::reference_internal) + + .def("__len__", + &DynamicEntryArray::size) + + LIEF_DEFAULT_STR(DynamicEntryArray); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryAuxiliary.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryAuxiliary.cpp new file mode 100644 index 0000000..0546ef6 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryAuxiliary.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicEntryAuxiliary.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryAuxiliary", + R"doc( + Class which represents a ``DT_AUXILIARY`` entry in the dynamic table. + This kind of entry is used to specify a shared object that should be + loaded before the current one. + )doc"_doc) + + .def(nb::init(), + "Constructor from library name"_doc, + "library_name"_a) + + .def_prop_rw("name", + [] (const DynamicEntryAuxiliary& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&DynamicEntryAuxiliary::name), + "Return the library name"_doc) + + LIEF_DEFAULT_STR(DynamicEntryAuxiliary); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFilter.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFilter.cpp new file mode 100644 index 0000000..e55e857 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFilter.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicEntryFilter.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryFilter", + R"doc( + Class which represents a ``DT_FILTER`` entry in the dynamic table. + This kind of entry is used to specify a shared object for which the + current one is a filter. + )doc"_doc) + + .def(nb::init(), + "Constructor from library name"_doc, + "library_name"_a) + + .def_prop_rw("name", + [] (const DynamicEntryFilter& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&DynamicEntryFilter::name), + "Return the library name"_doc) + + LIEF_DEFAULT_STR(DynamicEntryFilter); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFlags.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFlags.cpp new file mode 100644 index 0000000..730c8e8 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryFlags.cpp @@ -0,0 +1,107 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/DynamicEntryFlags.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ entry(m, "DynamicEntryFlags"); + + #define ENTRY(X) .value(to_string(DynamicEntryFlags::FLAG::X), DynamicEntryFlags::FLAG::X) + enum_(entry, "FLAG") + ENTRY(ORIGIN) + ENTRY(SYMBOLIC) + ENTRY(TEXTREL) + ENTRY(BIND_NOW) + ENTRY(STATIC_TLS) + ENTRY(NOW) + ENTRY(GLOBAL) + ENTRY(GROUP) + ENTRY(NODELETE) + ENTRY(LOADFLTR) + ENTRY(INITFIRST) + ENTRY(NOOPEN) + ENTRY(HANDLE_ORIGIN) + ENTRY(DIRECT) + ENTRY(TRANS) + ENTRY(INTERPOSE) + ENTRY(NODEFLIB) + ENTRY(NODUMP) + ENTRY(CONFALT) + ENTRY(ENDFILTEE) + ENTRY(DISPRELDNE) + ENTRY(DISPRELPND) + ENTRY(NODIRECT) + ENTRY(IGNMULDEF) + ENTRY(NOKSYMS) + ENTRY(NOHDR) + ENTRY(EDITED) + ENTRY(NORELOC) + ENTRY(SYMINTPOSE) + ENTRY(GLOBAUDIT) + ENTRY(SINGLETON) + ENTRY(PIE) + ENTRY(KMOD) + ENTRY(WEAKFILTER) + ENTRY(NOCOMMON) + ; + #undef ENTRY + + entry + .def_prop_ro("flags", + &DynamicEntryFlags::flags, + "Return list of :class:`~.FLAG`"_doc, + nb::rv_policy::move) + + .def("has", + nb::overload_cast(&DynamicEntryFlags::has, nb::const_), + "Check if this entry contains the given :class:`~.FLAG`"_doc, + "flag"_a) + + + .def("add", + nb::overload_cast(&DynamicEntryFlags::add), + "Add the given :class:`~.FLAG`"_doc, + "flag"_a) + + .def("remove", + nb::overload_cast(&DynamicEntryFlags::remove), + "Remove the given :class:`~.FLAG`"_doc, + "flag"_a) + + .def(nb::self += DynamicEntryFlags::FLAG()) + .def(nb::self -= DynamicEntryFlags::FLAG()) + + .def("__contains__", + nb::overload_cast(&DynamicEntryFlags::has, nb::const_), + "Check if the given :class:`~.FLAG` is present"_doc) + + LIEF_DEFAULT_STR(DynamicEntryFlags); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryLibrary.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryLibrary.cpp new file mode 100644 index 0000000..8f166ec --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryLibrary.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryLibrary", + R"delim( + Class which represents a ``DT_NEEDED`` entry in the dynamic table. + + This kind of entry is usually used to create library dependency. + )delim"_doc) + + .def(nb::init(), + "Constructor from a library name"_doc, + "library_name"_a) + + .def_prop_rw("name", + [] (const DynamicEntryLibrary& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&DynamicEntryLibrary::name), + "Library associated with this entry (e.g. ``libc.so.6``)"_doc) + + LIEF_DEFAULT_STR(DynamicEntryLibrary); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRpath.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRpath.cpp new file mode 100644 index 0000000..cb33887 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRpath.cpp @@ -0,0 +1,80 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicEntryRpath.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryRpath", + R"delim( + Class which represents a ``DT_RPATH`` entry. This attribute is + deprecated (cf. ``man ld``) in favour of ``DT_RUNPATH`` (See :class:`~lief.ELF.DynamicEntryRunPath`) + )delim"_doc) + + .def(nb::init(), + "Constructor from (r)path"_doc, + "path"_a = "") + + .def(nb::init &>(), + "Constructor from a list of paths"_doc, + "paths"_a) + + .def_prop_rw("rpath", + [] (const DynamicEntryRpath& obj) { + return LIEF::py::safe_string(obj.rpath()); + }, + nb::overload_cast(&DynamicEntryRpath::rpath), + "The actual rpath as a string"_doc) + + .def_prop_rw("paths", + nb::overload_cast<>(&DynamicEntryRpath::paths, nb::const_), + nb::overload_cast&>(&DynamicEntryRpath::paths), + "Paths as a list"_doc) + + .def("insert", &DynamicEntryRpath::insert, + "Insert a ``path`` at the given ``position``"_doc, + "position"_a, "path"_a, + nb::rv_policy::reference_internal) + + .def("append", &DynamicEntryRpath::append, + "Append the given ``path`` "_doc, + "path"_a, + nb::rv_policy::reference_internal) + + .def("remove", &DynamicEntryRpath::remove, + "Remove the given ``path`` "_doc, + "path"_a, + nb::rv_policy::reference_internal) + + .def(nb::self += std::string()) + .def(nb::self -= std::string()) + + LIEF_DEFAULT_STR(DynamicEntryRpath); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRunPath.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRunPath.cpp new file mode 100644 index 0000000..157aa47 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicEntryRunPath.cpp @@ -0,0 +1,79 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicEntryRunPath.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicEntryRunPath", + R"delim( + Class that represents a ``DT_RUNPATH`` which is used by the loader + to resolve libraries (:class:`~lief.ELF.DynamicEntryLibrary`). + )delim"_doc) + + .def(nb::init(), + "Constructor from a (run)path"_doc, + "path"_a = "") + + .def(nb::init &>(), + "Constructor from a list of paths"_doc, + "paths"_a) + + .def_prop_rw("runpath", + [] (const DynamicEntryRunPath& obj) { + return LIEF::py::safe_string(obj.runpath()); + }, + nb::overload_cast(&DynamicEntryRunPath::runpath), + "Runpath raw value"_doc) + + .def_prop_rw("paths", + nb::overload_cast<>(&DynamicEntryRunPath::paths, nb::const_), + nb::overload_cast&>(&DynamicEntryRunPath::paths), + "Paths as a list"_doc) + + .def("insert", &DynamicEntryRunPath::insert, + "Insert a ``path`` at the given ``position``"_doc, + "position"_a, "path"_a, + nb::rv_policy::reference_internal) + + .def("append", &DynamicEntryRunPath::append, + "Append the given ``path`` "_doc, + "path"_a, nb::rv_policy::reference_internal) + + .def("remove", &DynamicEntryRunPath::remove, + "Remove the given ``path`` ", + "path"_a, + nb::rv_policy::reference_internal) + + .def(nb::self += std::string()) + .def(nb::self -= std::string()) + + LIEF_DEFAULT_STR(DynamicEntryRunPath); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyDynamicSharedObject.cpp b/vendor/lief/api/python/src/ELF/objects/pyDynamicSharedObject.cpp new file mode 100644 index 0000000..f2c30a3 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyDynamicSharedObject.cpp @@ -0,0 +1,52 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/DynamicSharedObject.hpp" +#include "LIEF/ELF/DynamicEntry.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DynamicSharedObject", + R"delim( + Class which represents a ``DT_SONAME`` entry in the dynamic table + This kind of entry is usually used to name the original library. + + This entry is not present for executables. + )delim"_doc) + + .def(nb::init(), + "Constructor from library name"_doc, + "library_name"_a) + + .def_prop_rw("name", + [] (const DynamicSharedObject& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&DynamicSharedObject::name), + "Return the library name"_doc) + + LIEF_DEFAULT_STR(DynamicSharedObject); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyGnuHash.cpp b/vendor/lief/api/python/src/ELF/objects/pyGnuHash.cpp new file mode 100644 index 0000000..03fa5fe --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyGnuHash.cpp @@ -0,0 +1,93 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/GnuHash.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "GnuHash", + R"delim( + Class which provides a view over the GNU Hash implementation. + Most of the fields are read-only since the values are re-computed by the :class:`lief.ELF.Builder`. + )delim"_doc) + .def(nb::init<>()) + + .def_prop_ro("nb_buckets", + &GnuHash::nb_buckets, + "Return the number of buckets"_doc) + + .def_prop_ro("symbol_index", + &GnuHash::symbol_index, + "Index of the first symbol in the dynamic symbols table which is accessible with the hash table"_doc) + + .def_prop_ro("shift2", + &GnuHash::shift2, + "Shift count used in the bloom filter"_doc) + + .def_prop_ro("bloom_filters", + &GnuHash::bloom_filters, + "Bloom filters"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("buckets", + &GnuHash::buckets, + "hash buckets"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("hash_values", + &GnuHash::hash_values, + "Hash values"_doc, + nb::rv_policy::reference_internal) + + .def("check_bloom_filter", + &GnuHash::check_bloom_filter, + "Check if the given hash passes the bloom filter"_doc, + "hash"_a) + + .def("check_bucket", + &GnuHash::check_bucket, + "Check if the given hash passes the bucket filter"_doc, + "hash"_a) + + .def("check", + nb::overload_cast(&GnuHash::check, nb::const_), + "Check if the symbol *probably* exists. If " + "the returned value is ``false`` you can assume at ``100%`` that " + "the symbol with the given name doesn't exist. If ``true`` you can't " + "do any assumption"_doc, + "symbol_name"_a) + + .def("check", + nb::overload_cast(&GnuHash::check, nb::const_), + "Check if the symbol associated with the given hash *probably* exists. If " + "the returned value is ``false`` you can assume at ``100%`` that " + "the symbol doesn't exist. If ``true`` you can't " + "do any assumption"_doc, + "hash_value"_a) + + LIEF_DEFAULT_STR(GnuHash); +} + +} + diff --git a/vendor/lief/api/python/src/ELF/objects/pyHeader.cpp b/vendor/lief/api/python/src/ELF/objects/pyHeader.cpp new file mode 100644 index 0000000..40cd682 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyHeader.cpp @@ -0,0 +1,259 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/Header.hpp" + +namespace LIEF::ELF::py { + +template<> +void create
(nb::module_& m) { + + nb::class_ header(m, "Header", + R"delim( + Class which represents the ELF's header. This class mirrors the raw ELF + ``Elfxx_Ehdr`` structure. + )delim"_doc); + + #define ENTRY(X, D) .value(to_string(Header::FILE_TYPE::X), Header::FILE_TYPE::X, D) + enum_(header, "FILE_TYPE", + R"delim( + The type of the underlying ELF file. This enum matches the semantic of + ``ET_NONE``, ``ET_REL``, ... + )delim"_doc + ) + ENTRY(NONE, "Can't be determined/Invalid"_doc) + ENTRY(REL, "Relocatable file (or object file)"_doc) + ENTRY(EXEC, "non-pie executable"_doc) + ENTRY(DYN, "Shared library **or** a pie-executable"_doc) + ENTRY(CORE, "Core dump file"_doc) + ; + #undef ENTRY + + #define ENTRY(X, D) .value(to_string(Header::VERSION::X), Header::VERSION::X, D) + enum_(header, "VERSION", + R"delim( + Matches the result of ``Elfxx_Ehdr.e_version`` + )delim"_doc + ) + ENTRY(NONE, "Invalid ELF version"_doc) + ENTRY(CURRENT, "Current version (default)"_doc) + ; + #undef ENTRY + + #define ENTRY(X, D) .value(to_string(Header::CLASS::X), Header::CLASS::X, D) + enum_(header, "CLASS", + R"delim( + Matches the result of ``Elfxx_Ehdr.e_ident[EI_CLASS]`` + )delim"_doc + ) + ENTRY(NONE, "Invalid class"_doc) + ENTRY(ELF32, "32-bit objects"_doc) + ENTRY(ELF64, "64-bit objects"_doc) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Header::OS_ABI::X), Header::OS_ABI::X) + enum_(header, "OS_ABI") + ENTRY(SYSTEMV) + ENTRY(HPUX) + ENTRY(NETBSD) + /* ENTRY(GNU) */ + ENTRY(LINUX) + ENTRY(HURD) + ENTRY(SOLARIS) + ENTRY(AIX) + ENTRY(IRIX) + ENTRY(FREEBSD) + ENTRY(TRU64) + ENTRY(MODESTO) + ENTRY(OPENBSD) + ENTRY(OPENVMS) + ENTRY(NSK) + ENTRY(AROS) + ENTRY(FENIXOS) + ENTRY(CLOUDABI) + /*ENTRY(C6000_ELFABI)*/ + ENTRY(AMDGPU_HSA) + ENTRY(C6000_LINUX) + ENTRY(ARM) + ENTRY(STANDALONE) + ; + #undef ENTRY + + #define ENTRY(X, D) .value(to_string(Header::ELF_DATA::X), Header::ELF_DATA::X, D) + enum_(header, "ELF_DATA", + R"delim( + Matches the result of ``Elfxx_Ehdr.e_ident[EI_DATA]`` + )delim"_doc + ) + ENTRY(NONE, "Invalid data encoding"_doc) + ENTRY(LSB, "2's complement, little endian"_doc) + ENTRY(MSB, "2's complement, big endian"_doc) + ; + #undef ENTRY + + header + .def(nb::init<>()) + + .def_prop_rw("identity_class", + nb::overload_cast<>(&Header::identity_class, nb::const_), + nb::overload_cast(&Header::identity_class), + "Header's class."_doc) + + .def_prop_rw("identity_data", + nb::overload_cast<>(&Header::identity_data, nb::const_), + nb::overload_cast(&Header::identity_data), + "Specify the data encoding"_doc) + + .def_prop_rw("identity_version", + nb::overload_cast<>(&Header::identity_version, nb::const_), + nb::overload_cast(&Header::identity_version)) + + .def_prop_rw("identity_os_abi", + nb::overload_cast<>(&Header::identity_os_abi, nb::const_), + nb::overload_cast(&Header::identity_os_abi), + "Identifies the version of the ABI for which the object is prepared."_doc) + + .def_prop_rw("identity_abi_version", + nb::overload_cast<>(&Header::identity_abi_version, nb::const_), + nb::overload_cast(&Header::identity_abi_version), + "Return the ABI version (integer)."_doc) + + .def_prop_rw("identity", + nb::overload_cast<>(&Header::identity), + [] (Header& header, const nb::object& obj) { + if (nb::isinstance(obj)) { + header.identity(nb::cast(obj)); + return; + } + + if (nb::isinstance(obj)) { + header.identity(nb::cast(obj)); + return; + } + + if (nb::isinstance(obj)) { + header.identity(nb::cast(obj)); + return; + } + + std::string error_str = nb::repr(obj).c_str(); + error_str = error_str + " is not supported!"; + throw nb::type_error(error_str.c_str()); + }, + "Header's identity."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("file_type", + nb::overload_cast<>(&Header::file_type, nb::const_), + nb::overload_cast(&Header::file_type), + "Return binary's type. This field determines if the binary is an " + "executable, a library..."_doc) + + .def_prop_rw("machine_type", + nb::overload_cast<>(&Header::machine_type, nb::const_), + nb::overload_cast(&Header::machine_type), + "Return the target architecture"_doc) + + .def_prop_ro("is_mips_n64", &Header::is_mips_n64, + "Whether this header uses the MIPS n64 ELF encoding"_doc) + + .def_prop_rw("object_file_version", + nb::overload_cast<>(&Header::object_file_version, nb::const_), + nb::overload_cast(&Header::object_file_version), + "Return the version"_doc) + + .def_prop_rw("entrypoint", + nb::overload_cast<>(&Header::entrypoint, nb::const_), + nb::overload_cast(&Header::entrypoint), + "Return the binary entry point"_doc) + + .def_prop_rw("program_header_offset", + nb::overload_cast<>(&Header::program_headers_offset, nb::const_), + nb::overload_cast(&Header::program_headers_offset), + "Offset of program table (also known as segments table)"_doc) + + .def_prop_rw("section_header_offset", + nb::overload_cast<>(&Header::section_headers_offset, nb::const_), + nb::overload_cast(&Header::section_headers_offset), + "Offset of section table"_doc) + + .def_prop_rw("processor_flag", + nb::overload_cast<>(&Header::processor_flag, nb::const_), + nb::overload_cast(&Header::processor_flag), + "Processor-specific flags"_doc) + + .def("has", &Header::has, + "Check if the given processor flag is present"_doc) + + .def_prop_ro("flags_list", &Header::flags_list, + "Processor flags as a list"_doc) + + .def_prop_rw("header_size", + nb::overload_cast<>(&Header::header_size, nb::const_), + nb::overload_cast(&Header::header_size), + R"delim( + Return the size of the ELF header + This size should be 64 for an ``ELF64`` binary and 52 for an ``ELF32``. + )delim"_doc) + + .def_prop_rw("program_header_size", + nb::overload_cast<>(&Header::program_header_size, nb::const_), + nb::overload_cast(&Header::program_header_size), + R"delim( + Return the size of the raw ``Elfxx_Phdr`` structure (see :class:`lief.ELF.Segment`) + This size should be 56 for an ``ELF64`` binary and 32 for an ``ELF32``. + )delim"_doc) + + .def_prop_rw("numberof_segments", + nb::overload_cast<>(&Header::numberof_segments, nb::const_), + nb::overload_cast(&Header::numberof_segments), + "Return the number of program headers (segments)"_doc) + + .def_prop_rw("section_header_size", + nb::overload_cast<>(&Header::section_header_size, nb::const_), + nb::overload_cast(&Header::section_header_size), + R"delim( + Return the size of the raw ``Elfxx_Shdr`` (:class:`lief.ELF.Section`) + + This size should be 64 for an ``ELF64`` binary and 40 for an ``ELF32``. + )delim"_doc) + + .def_prop_rw("numberof_sections", + nb::overload_cast<>(&Header::numberof_sections, nb::const_), + nb::overload_cast(&Header::numberof_sections), + "Return the number of sections"_doc) + + .def_prop_rw("section_name_table_idx", + nb::overload_cast<>(&Header::section_name_table_idx, nb::const_), + nb::overload_cast(&Header::section_name_table_idx), + "Return the section index which contains sections' names"_doc) + + LIEF_DEFAULT_STR(Header); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyNote.cpp b/vendor/lief/api/python/src/ELF/objects/pyNote.cpp new file mode 100644 index 0000000..f1d2ed7 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyNote.cpp @@ -0,0 +1,162 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/Note.hpp" +#include "LIEF/ELF/NoteDetails.hpp" + +#include "enums_wrapper.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_ note(m, "Note", + R"delim( + Class which represents an ELF note. + )delim"_doc); + + #define ENTRY(X) .value(to_string(Note::TYPE::X), Note::TYPE::X) + enum_(note, "TYPE", "LIEF representation of the ELF `NT_` values.") + ENTRY(UNKNOWN) + ENTRY(GNU_ABI_TAG) + ENTRY(GNU_HWCAP) + ENTRY(GNU_BUILD_ID) + ENTRY(GNU_GOLD_VERSION) + ENTRY(GNU_PROPERTY_TYPE_0) + ENTRY(GNU_BUILD_ATTRIBUTE_OPEN) + ENTRY(GNU_BUILD_ATTRIBUTE_FUNC) + ENTRY(CRASHPAD) + ENTRY(CORE_PRSTATUS) + ENTRY(CORE_FPREGSET) + ENTRY(CORE_PRPSINFO) + ENTRY(CORE_TASKSTRUCT) + ENTRY(CORE_AUXV) + ENTRY(CORE_PSTATUS) + ENTRY(CORE_FPREGS) + ENTRY(CORE_PSINFO) + ENTRY(CORE_LWPSTATUS) + ENTRY(CORE_LWPSINFO) + ENTRY(CORE_WIN32PSTATUS) + ENTRY(CORE_FILE) + ENTRY(CORE_PRXFPREG) + ENTRY(CORE_SIGINFO) + ENTRY(CORE_ARM_VFP) + ENTRY(CORE_ARM_TLS) + ENTRY(CORE_ARM_HW_BREAK) + ENTRY(CORE_ARM_HW_WATCH) + ENTRY(CORE_ARM_SYSTEM_CALL) + ENTRY(CORE_ARM_SVE) + ENTRY(CORE_ARM_PAC_MASK) + ENTRY(CORE_ARM_PACA_KEYS) + ENTRY(CORE_ARM_PACG_KEYS) + ENTRY(CORE_TAGGED_ADDR_CTRL) + ENTRY(CORE_PAC_ENABLED_KEYS) + ENTRY(CORE_X86_TLS) + ENTRY(CORE_X86_IOPERM) + ENTRY(CORE_X86_XSTATE) + ENTRY(CORE_X86_CET) + ENTRY(ANDROID_MEMTAG) + ENTRY(ANDROID_KUSER) + ENTRY(ANDROID_IDENT) + ENTRY(GO_BUILDID) + ENTRY(STAPSDT) + ENTRY(QNX_STACK) + ; + #undef ENTRY + + const auto create_overload_0 = nb::overload_cast(&Note::create); + const auto create_overload_1 = nb::overload_cast(&Note::create); + note + .def_static("create", create_overload_0, + R"doc( + Create a note from the owner name, the original type (`NT_xxx` value) + and the description. + + Depending on the note, the filetype, the architecture and the ELF class might be needed. + )doc"_doc, + "name"_a, "original_type"_a, "description"_a, "section_name"_a, + "file_type"_a = Header::FILE_TYPE::NONE, "arch"_a = ARCH::NONE, "cls"_a = Header::CLASS::NONE) + + .def_static("create", + [] (nb::bytes bytes, std::string section, Header::FILE_TYPE ftype, ARCH arch, Header::CLASS cls) -> std::unique_ptr { + std::unique_ptr stream = to_stream(bytes); + if (!stream) { + return nullptr; + } + return Note::create(*stream, std::move(section), ftype, arch, cls); + }, + R"doc( + Create a note from the given `bytes` buffer. + + Depending on the note, the filetype, the architecture and the ELF class might + be needed. + )doc"_doc, + "raw"_a, "section_name"_a = "", + "file_type"_a = Header::FILE_TYPE::NONE, "arch"_a = ARCH::NONE, + "cls"_a = Header::CLASS::NONE) + + .def_static("create", create_overload_1, + R"doc( + Create a note from the owner name, the type, and the description + + Depending on the note, the filetype, the architecture and the ELF class might + be needed. + )doc"_doc, + "name"_a, "type"_a, "description"_a, "section_name"_a, + "arch"_a = ARCH::NONE, "cls"_a = Header::CLASS::NONE) + + .def_prop_rw("name", + nb::overload_cast<>(&Note::name, nb::const_), + nb::overload_cast(&Note::name), + "Return the *name* of the note also known as the owner."_doc) + + .def_prop_ro("original_type", + nb::overload_cast<>(&Note::original_type, nb::const_), + R"doc( + Return the original `NT_` value of the note. + + This value should be interpreted according the :attr:`~.name` of the + note. + )doc"_doc) + + .def_prop_ro("type", + nb::overload_cast<>(&Note::type, nb::const_), + R"doc( + Return the LIEF type representation of the note. + )doc"_doc) + + .def_prop_rw("description", + nb::overload_cast<>(&Note::description, nb::const_), + nb::overload_cast(&Note::description), + "Return the description associated with the note"_doc) + + .def_prop_ro("size", &Note::size, "Size of the **raw** note"_doc) + + LIEF_CLONABLE(Note) + LIEF_DEFAULT_STR(Note); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyParser.cpp b/vendor/lief/api/python/src/ELF/objects/pyParser.cpp new file mode 100644 index 0000000..d5ba54f --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyParser.cpp @@ -0,0 +1,73 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include +#include +#include + +#include "typing/InputParser.hpp" + +#include "LIEF/ELF/Parser.hpp" +#include "LIEF/ELF/Binary.hpp" + +#include "LIEF/BinaryStream/BinaryStream.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse_from_memory", + nb::overload_cast(&Parser::parse_from_memory), + "Parse the ELF binary at the given memory address"_doc, + "address"_a, "config"_a = ParserConfig::all(), + nb::rv_policy::take_ownership); + + m.def("parse_from_memory", + nb::overload_cast(&Parser::parse_from_memory), + "Parse the ELF binary at the given memory address and with the given size"_doc, + "address"_a, "size"_a, "config"_a = ParserConfig::all(), + nb::rv_policy::take_ownership); + + m.def("parse_from_dump", + [] (typing::InputParser obj, uint64_t addr, const ParserConfig& config) { + return Parser::parse_from_dump(obj.into_stream(), addr, config); + }, + R"delim( + Parse the ELF binary from a memory dump given in the first parameter. + + A dump is a raw capture of the process' memory that was mapped starting at + the virtual address given in the second parameter. + )delim"_doc, + "obj"_a, "addr"_a, "config"_a = ParserConfig::all(), + nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const ParserConfig& config) -> std::unique_ptr { + return Parser::parse(obj.into_stream(), config); + }, + R"delim( + Parse the ELF binary from the given Python object and return a :class:`lief.ELF.Binary` object + + The second argument is an optional configuration (:class:`~lief.ELF.ParserConfig`) + that can be used to define which part(s) of the ELF should be parsed or skipped. + )delim"_doc, + "obj"_a, "config"_a = ParserConfig::all(), + nb::rv_policy::take_ownership); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyParserConfig.cpp b/vendor/lief/api/python/src/ELF/objects/pyParserConfig.cpp new file mode 100644 index 0000000..2d65787 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyParserConfig.cpp @@ -0,0 +1,75 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" +#include "LIEF/ELF/ParserConfig.hpp" + +#include "enums_wrapper.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + + nb::class_ pconfig(m, "ParserConfig", + R"delim( + This class is used to tweak the ELF Parser + )delim"_doc); + + enum_(pconfig, "DYNSYM_COUNT") + .value("AUTO", ParserConfig::DYNSYM_COUNT::AUTO) + .value("SECTION", ParserConfig::DYNSYM_COUNT::SECTION) + .value("HASH", ParserConfig::DYNSYM_COUNT::HASH) + .value("RELOCATIONS", ParserConfig::DYNSYM_COUNT::RELOCATIONS); + + pconfig + .def(nb::init<>()) + .def_rw("parse_relocations", &ParserConfig::parse_relocations, + "Whether relocations (including plt-like relocations) should be parsed."_doc) + .def_rw("parse_dyn_symbols", &ParserConfig::parse_dyn_symbols, + "Whether dynamic symbols (those from `.dynsym`) should be parsed"_doc) + .def_rw("parse_symtab_symbols", &ParserConfig::parse_symtab_symbols, + "Whether debug symbols (those from `.symtab`) should be parsed"_doc) + .def_rw("parse_symbol_versions", &ParserConfig::parse_symbol_versions, + "Whether versioning symbols should be parsed"_doc) + .def_rw("parse_notes", &ParserConfig::parse_notes, + "Whether ELF notes information should be parsed"_doc) + .def_rw("parse_overlay", &ParserConfig::parse_overlay, + "Whether the overlay data should be parsed") + .def_rw("count_mtd", &ParserConfig::count_mtd, + R"delim( + The :class:`~lief.ELF.DYNSYM_COUNT_METHODS` to use for counting the dynamic symbols + + For *weird* binaries (e.g sectionless) you can choose the method for counting dynamic symbols + (:class:`lief.ELF.DYNSYM_COUNT_METHODS`). By default, the value is set to + :attr:`lief.ELF.DYNSYM_COUNT_METHODS.COUNT_AUTO` + )delim"_doc) + .def_rw("page_size", &ParserConfig::page_size, + R"doc( + Memory page size if the binary uses a non-standard value. + + For instance, SPARCV9 binary can use a page size from 0x2000 to 0x100000. + )doc"_doc + ) + + .def_prop_ro_static("all", + [] (const nb::object& /* self */) { return ParserConfig::all(); }, + R"delim( + Return a parser configuration such as all the objects supported by LIEF are parsed + )delim"_doc); +} + +} + diff --git a/vendor/lief/api/python/src/ELF/objects/pyRelocation.cpp b/vendor/lief/api/python/src/ELF/objects/pyRelocation.cpp new file mode 100644 index 0000000..2aedf41 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyRelocation.cpp @@ -0,0 +1,168 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" +#include "pyErr.hpp" + +#include "LIEF/ELF/Relocation.hpp" +#include "LIEF/ELF/Symbol.hpp" +#include "LIEF/ELF/Section.hpp" + +namespace LIEF::ELF::py { + +void init_relocation_types(nb::class_& m); + +template<> +void create(nb::module_& m) { + nb::class_ reloc(m, "Relocation", + R"delim( + Class that represents an ELF relocation. + )delim"_doc); + + init_relocation_types(reloc); + + enum_(reloc, "PURPOSE") + .value("NONE", Relocation::PURPOSE::NONE) + .value("PLTGOT", Relocation::PURPOSE::PLTGOT) + .value("DYNAMIC", Relocation::PURPOSE::DYNAMIC) + .value("OBJECT", Relocation::PURPOSE::OBJECT); + + enum_(reloc, "ENCODING") + .value("UNKNOWN", Relocation::ENCODING::UNKNOWN) + .value("ANDROID_SLEB", Relocation::ENCODING::ANDROID_SLEB, + "The relocation is using the packed Android-SLEB128 format"_doc) + .value("REL", Relocation::ENCODING::REL, + "The relocation is using the regular Elf_Rel structure"_doc) + .value("RELR", Relocation::ENCODING::RELR, + "The relocation is using the relative relocation format"_doc) + .value("RELA", Relocation::ENCODING::RELA, + "The relocation is using the regular Elf_Rela structure"_doc); + + reloc + .def(nb::init<>()) + .def(nb::init(), "arch"_a) + .def(nb::init(), + "address"_a, "type"_a, "encoding"_a) + + .def_prop_rw("addend", + nb::overload_cast<>(&Relocation::addend, nb::const_), + nb::overload_cast(&Relocation::addend), + "Additional value"_doc) + + .def_prop_rw("info", + nb::overload_cast<>(&Relocation::info, nb::const_), + nb::overload_cast(&Relocation::info), + "Extra information like the symbol index"_doc) + + .def_prop_rw("purpose", + nb::overload_cast<>(&Relocation::purpose, nb::const_), + nb::overload_cast(&Relocation::purpose), + R"delim( + Purpose of the relocation. + This value provides the information about how the relocation is used (PLT/GOT resolution, ``.o`` file, ...) + )delim"_doc) + + .def_prop_rw("type", + nb::overload_cast<>(&Relocation::type, nb::const_), + nb::overload_cast(&Relocation::type), + R"delim(Relocation type.)delim"_doc) + + .def_prop_ro("has_symbol", + &Relocation::has_symbol, + "``True`` if a " RST_CLASS_REF(lief.ELF.Symbol) " is associated with the relocation"_doc) + + .def_prop_rw("symbol", + nb::overload_cast<>(&Relocation::symbol, nb::const_), + nb::overload_cast(&Relocation::symbol), + R"delim( + :class:`~lief.ELF.Symbol` associated with the relocation or None + if no symbol is associated with this relocation. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_section", + &Relocation::has_section, + R"delim( + ``True`` if this relocation has a :class:`lief.ELF.Section` associated with. + + This is usually the case for object files (``.o``) + )delim"_doc) + + .def_prop_ro("section", + nb::overload_cast<>(&Relocation::section), + R"delim( + :class:`~lief.ELF.Section` in which the relocation is applied or None if not relevant + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("symbol_table", + nb::overload_cast<>(&Relocation::symbol_table), + R"delim( + The symbol table :class:`~lief.ELF.Section` which the relocation references + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("is_rela", + &Relocation::is_rela, + "``True`` if the relocation **uses** the :attr:`~lief.ELF.Relocation.addend` property"_doc) + + .def_prop_ro("is_rel", + &Relocation::is_rel, + "``True`` if the relocation **doesn't use** the :attr:`~lief.ELF.Relocation.addend` property"_doc) + + .def("r_info", nb::overload_cast(&Relocation::r_info, nb::const_), + R"delim( + (re)Compute the raw ``r_info`` attribute based on the given ELF class and + endianness + )delim"_doc, "clazz"_a, "data"_a) + + .def("r_info", nb::overload_cast(&Relocation::r_info, nb::const_), + R"delim( + (re)Compute the raw ``r_info`` attribute based on the ELF Header + )delim"_doc, "header"_a) + + .def_prop_ro("is_relatively_encoded", &Relocation::is_relatively_encoded, + "True if the relocation is using the relative encoding"_doc) + + .def_prop_ro("is_android_packed", &Relocation::is_android_packed, + "True if the relocation is using the Android packed relocation format"_doc) + + .def_prop_ro("is_rel", &Relocation::is_rel, + R"delim( + Check if the relocation uses the implicit addend + (i.e. not present in the ELF structure) + )delim"_doc) + + .def_prop_ro("encoding", &Relocation::encoding, + "The encoding of the relocation") + + .def("resolve", [] (const Relocation& self, uint64_t base_address) { + return LIEF::py::error_or(&Relocation::resolve, self, base_address); + }, "base_address"_a = 0, + R"doc( + Try to resolve the value of the relocation such as + ``*address() = resolve()`` + )doc"_doc + ) + + LIEF_DEFAULT_STR(Relocation); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pyRelocationTypes.cpp b/vendor/lief/api/python/src/ELF/objects/pyRelocationTypes.cpp new file mode 100644 index 0000000..ce23be6 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pyRelocationTypes.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/Relocation.hpp" + +namespace LIEF::ELF::py { + +void init_relocation_types(nb::class_& m) { + + #define ELF_RELOC(X, _) .value(to_string(Relocation::TYPE::X), Relocation::TYPE::X) + enum_(m, "TYPE") + #include "LIEF/ELF/Relocations/x86_64.def" + #include "LIEF/ELF/Relocations/AArch64.def" + #include "LIEF/ELF/Relocations/ARM.def" + #include "LIEF/ELF/Relocations/Hexagon.def" + #include "LIEF/ELF/Relocations/i386.def" + #include "LIEF/ELF/Relocations/LoongArch.def" + #include "LIEF/ELF/Relocations/Mips.def" + #include "LIEF/ELF/Relocations/PowerPC.def" + #include "LIEF/ELF/Relocations/PowerPC64.def" + #include "LIEF/ELF/Relocations/Sparc.def" + #include "LIEF/ELF/Relocations/SystemZ.def" + #include "LIEF/ELF/Relocations/RISCV.def" + #include "LIEF/ELF/Relocations/BPF.def" + #include "LIEF/ELF/Relocations/SH4.def" + ; + #undef ELF_RELOC +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySection.cpp b/vendor/lief/api/python/src/ELF/objects/pySection.cpp new file mode 100644 index 0000000..410a8e3 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySection.cpp @@ -0,0 +1,288 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" +#include "pyIterator.hpp" +#include "enums_wrapper.hpp" + +#include +#include +#include +#include + +#include "LIEF/Abstract/Section.hpp" +#include "LIEF/ELF/Section.hpp" +#include "LIEF/ELF/Segment.hpp" + +#include +#include + +namespace LIEF::ELF::py { + +template<> +void create
(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ sec(m, "Section", + R"delim( + Class which represents an ELF section. + )delim"_doc + ); + + init_ref_iterator(sec, "it_segments"); + + #define ENTRY(X) .value(to_string(Section::FLAGS::X), Section::FLAGS::X) + enum_(sec, "FLAGS", nb::is_flag()) + ENTRY(NONE) + ENTRY(WRITE) + ENTRY(ALLOC) + ENTRY(EXECINSTR) + ENTRY(MERGE) + ENTRY(STRINGS) + ENTRY(INFO_LINK) + ENTRY(LINK_ORDER) + ENTRY(OS_NONCONFORMING) + ENTRY(GROUP) + ENTRY(TLS) + ENTRY(COMPRESSED) + ENTRY(GNU_RETAIN) + ENTRY(EXCLUDE) + ENTRY(XCORE_SHF_DP_SECTION) + ENTRY(XCORE_SHF_CP_SECTION) + ENTRY(X86_64_LARGE) + ENTRY(HEX_GPREL) + + ENTRY(MIPS_NODUPES) + ENTRY(MIPS_NAMES) + ENTRY(MIPS_LOCAL) + ENTRY(MIPS_NOSTRIP) + ENTRY(MIPS_GPREL) + ENTRY(MIPS_MERGE) + ENTRY(MIPS_ADDR) + ENTRY(MIPS_STRING) + ENTRY(ARM_PURECODE) + ENTRY(AARCH64_PURECODE) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Section::TYPE::X), Section::TYPE::X) + enum_(sec, "TYPE") + ENTRY(SHT_NULL_) + ENTRY(PROGBITS) + ENTRY(SYMTAB) + ENTRY(STRTAB) + ENTRY(RELA) + ENTRY(HASH) + ENTRY(DYNAMIC) + ENTRY(NOTE) + ENTRY(NOBITS) + ENTRY(REL) + ENTRY(SHLIB) + ENTRY(DYNSYM) + ENTRY(INIT_ARRAY) + ENTRY(FINI_ARRAY) + ENTRY(PREINIT_ARRAY) + ENTRY(GROUP) + ENTRY(SYMTAB_SHNDX) + ENTRY(RELR) + + ENTRY(ANDROID_REL) + ENTRY(ANDROID_RELA) + ENTRY(LLVM_ADDRSIG) + ENTRY(ANDROID_RELR) + ENTRY(GNU_ATTRIBUTES) + ENTRY(GNU_HASH) + ENTRY(GNU_VERDEF) + ENTRY(GNU_VERNEED) + ENTRY(GNU_VERSYM) + + ENTRY(ARM_EXIDX) + ENTRY(ARM_PREEMPTMAP) + ENTRY(ARM_ATTRIBUTES) + ENTRY(ARM_DEBUGOVERLAY) + ENTRY(ARM_OVERLAYSECTION) + ENTRY(HEX_ORDERED) + ENTRY(X86_64_UNWIND) + + ENTRY(MIPS_LIBLIST) + ENTRY(MIPS_MSYM) + ENTRY(MIPS_CONFLICT) + ENTRY(MIPS_GPTAB) + ENTRY(MIPS_UCODE) + ENTRY(MIPS_DEBUG) + ENTRY(MIPS_REGINFO) + ENTRY(MIPS_PACKAGE) + ENTRY(MIPS_PACKSYM) + ENTRY(MIPS_RELD) + ENTRY(MIPS_IFACE) + ENTRY(MIPS_CONTENT) + ENTRY(MIPS_OPTIONS) + ENTRY(MIPS_SHDR) + ENTRY(MIPS_FDESC) + ENTRY(MIPS_EXTSYM) + ENTRY(MIPS_DENSE) + ENTRY(MIPS_PDESC) + ENTRY(MIPS_LOCSYM) + ENTRY(MIPS_AUXSYM) + ENTRY(MIPS_OPTSYM) + ENTRY(MIPS_LOCSTR) + ENTRY(MIPS_LINE) + ENTRY(MIPS_RFDESC) + ENTRY(MIPS_DELTASYM) + ENTRY(MIPS_DELTAINST) + ENTRY(MIPS_DELTACLASS) + ENTRY(MIPS_DWARF) + ENTRY(MIPS_DELTADECL) + ENTRY(MIPS_SYMBOL_LIB) + ENTRY(MIPS_EVENTS) + ENTRY(MIPS_TRANSLATE) + ENTRY(MIPS_PIXIE) + ENTRY(MIPS_XLATE) + ENTRY(MIPS_XLATE_DEBUG) + ENTRY(MIPS_WHIRL) + ENTRY(MIPS_EH_REGION) + ENTRY(MIPS_XLATE_OLD) + ENTRY(MIPS_PDR_EXCEPTION) + ENTRY(MIPS_ABIFLAGS) + ENTRY(MIPS_XHASH) + + ENTRY(RISCV_ATTRIBUTES) + + ENTRY(AARCH64_ATTRIBUTES) + ENTRY(AARCH64_AUTH_RELR) + ENTRY(AARCH64_MEMTAG_GLOBALS_STATIC) + ENTRY(AARCH64_MEMTAG_GLOBALS_DYNAMIC) + ; + #undef ENTRY + + sec + .def(nb::init<>(), + "Default constructor"_doc) + + .def("as_frame", + &Section::as_frame, + nb::rv_policy::reference_internal) + + .def_prop_ro("is_frame", + &Section::is_frame) + + .def(nb::init(), + "Constructor from a name and a section type"_doc, + "name"_a, "type"_a = Section::TYPE::PROGBITS) + + .def_prop_rw("type", + nb::overload_cast<>(&Section::type, nb::const_), + nb::overload_cast(&Section::type), + "Return the type of the section"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&Section::flags, nb::const_), + nb::overload_cast(&Section::flags), + "Return the section's flags as an integer"_doc) + + .def_prop_ro("flags_list", &Section::flags_list, + "Return section's flags as a list"_doc) + + .def_prop_rw("file_offset", + nb::overload_cast<>(&Section::file_offset, nb::const_), + nb::overload_cast(&Section::file_offset), + "Offset of the section's content"_doc) + + .def_prop_ro("original_size", + &Section::original_size, + R"delim( + Original size of the section's data. + + This value is used by the :class:`~lief.ELF.Builder` to determine if it needs + to be relocated to avoid an overwrite of the data + )delim"_doc) + + .def_prop_rw("alignment", + nb::overload_cast<>(&Section::alignment, nb::const_), + nb::overload_cast(&Section::alignment), + "Section alignment"_doc) + + .def_prop_rw("information", + nb::overload_cast<>(&Section::information, nb::const_), + nb::overload_cast(&Section::information), + "Section information (this value depends on the section)"_doc) + + .def_prop_rw("entry_size", + nb::overload_cast<>(&Section::entry_size, nb::const_), + nb::overload_cast(&Section::entry_size), + R"delim( + This property returns the size of an element in the case of a section that + contains an array. + + :Example: + + The `.dynamic` section contains an array of :class:`~lief.ELF.DynamicEntry`. As the + size of the raw C structure of this entry is 0x10 (``sizeof(Elf64_Dyn)``) + in a ELF64, the :attr:`~lief.ELF.Section.entry_size`, + is set to this value. + )delim"_doc) + + .def_prop_rw("link", + nb::overload_cast<>(&Section::link, nb::const_), + nb::overload_cast(&Section::link), + "Index to another section"_doc) + + .def_prop_ro("segments", + nb::overload_cast<>(&Section::segments), + "Return segment(s) associated with the given section"_doc, + nb::keep_alive<0, 1>()) + + .def("clear", &Section::clear, + "Clear the content of the section with the given ``value``"_doc, + "value"_a = 0, + nb::rv_policy::reference_internal) + + .def("add", &Section::add, + "Add the given flag to the list of :attr:`~lief.ELF.Section.flags`"_doc, + "flag"_a) + + .def("remove", &Section::remove, + "Remove the given flag from the list of " ":attr:`~lief.ELF.Section.flags`"_doc, + "flag"_a) + + .def("has", + nb::overload_cast(&Section::has, nb::const_), + "Check if the given flag is present"_doc, + "flag"_a) + + .def("has", + nb::overload_cast(&Section::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Segment) " is present " + "in :attr:`~lief.ELF.Section.segments`"_doc, + "segment"_a) + + .def(nb::self += Section::FLAGS()) + .def(nb::self -= Section::FLAGS()) + + .def("__contains__", + nb::overload_cast(&Section::has, nb::const_), + "Check if the given flag is present"_doc) + + + .def("__contains__", + nb::overload_cast(&Section::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Segment) " is present " + "in :attr:`~lief.ELF.Section.segments`"_doc) + + LIEF_DEFAULT_STR(Section); +} + + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySegment.cpp b/vendor/lief/api/python/src/ELF/objects/pySegment.cpp new file mode 100644 index 0000000..b2c11df --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySegment.cpp @@ -0,0 +1,238 @@ +/* opyright 2017 - 2023 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include +#include +#include + +#include "LIEF/ELF/Segment.hpp" +#include "LIEF/ELF/Section.hpp" + +#include "ELF/pyELF.hpp" +#include "pyErr.hpp" +#include "pyIterator.hpp" +#include "nanobind/extra/stl/lief_span.h" + +#include "enums_wrapper.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ seg(m, "Segment", + R"delim( + Class which represents the ELF segments + )delim"_doc + ); + + init_ref_iterator(seg, "it_sections"); + + #define ENTRY(X) .value(to_string(Segment::TYPE::X), Segment::TYPE::X) + enum_(seg, "TYPE") + ENTRY(PT_NULL_) + ENTRY(LOAD) + ENTRY(DYNAMIC) + ENTRY(INTERP) + ENTRY(NOTE) + ENTRY(SHLIB) + ENTRY(PHDR) + ENTRY(TLS) + ENTRY(GNU_EH_FRAME) + ENTRY(GNU_STACK) + ENTRY(GNU_PROPERTY) + ENTRY(GNU_RELRO) + ENTRY(PAX_FLAGS) + ENTRY(ARM_ARCHEXT) + ENTRY(ARM_EXIDX) + ENTRY(AARCH64_MEMTAG_MTE) + ENTRY(MIPS_REGINFO) + ENTRY(MIPS_RTPROC) + ENTRY(MIPS_OPTIONS) + ENTRY(MIPS_ABIFLAGS) + ENTRY(RISCV_ATTRIBUTES) + ENTRY(IA_64_EXT) + ENTRY(IA_64_UNWIND) + ENTRY(HP_TLS) + ENTRY(HP_CORE_NONE) + ENTRY(HP_CORE_VERSION) + ENTRY(HP_CORE_KERNEL) + ENTRY(HP_CORE_COMM) + ENTRY(HP_CORE_PROC) + ENTRY(HP_CORE_LOADABLE) + ENTRY(HP_CORE_STACK) + ENTRY(HP_CORE_SHM) + ENTRY(HP_CORE_MMF) + ENTRY(HP_PARALLEL) + ENTRY(HP_FASTBIND) + ENTRY(HP_OPT_ANNOT) + ENTRY(HP_HSL_ANNOT) + ENTRY(HP_STACK) + ENTRY(HP_CORE_UTSNAME) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Segment::FLAGS::X), Segment::FLAGS::X) + enum_(seg, "FLAGS", nb::is_flag()) + ENTRY(R) + ENTRY(W) + ENTRY(X) + ENTRY(NONE) + ; + #undef ENTRY + + seg + .def(nb::init<>()) + .def_static("from_raw", + [] (nb::bytes raw) { + const std::vector& cpp_raw = {raw.c_str(), raw.c_str() + raw.size()}; + auto* f_ptr = nb::overload_cast&>(&Segment::from_raw); + return error_or(f_ptr, cpp_raw); + }) + + .def_prop_rw("type", + nb::overload_cast<>(&Segment::type, nb::const_), + nb::overload_cast(&Segment::type), + "Segment's type"_doc) + + .def_prop_rw("flags", + [] (const Segment& S) { return (Segment::FLAGS)((uint32_t)S.flags() & 7); }, + nb::overload_cast(&Segment::flags), + "The flag permissions associated with this segment"_doc) + + .def_prop_rw("raw_flags", + [] (const Segment& S) { return (uint32_t)S.flags(); }, + nb::overload_cast(&Segment::flags), + "The flag permissions as an integer"_doc) + + .def_prop_rw("file_offset", + nb::overload_cast<>(&Segment::file_offset, nb::const_), + nb::overload_cast(&Segment::file_offset), + "The file offset of the data associated with this segment"_doc) + + .def_prop_rw("virtual_address", + nb::overload_cast<>(&Segment::virtual_address, nb::const_), + nb::overload_cast(&Segment::virtual_address), + R"delim( + The virtual address of the segment. + + .. warning:: + The ELF format specifications require the following relationship: + + .. math:: + \text{virtual address} \equiv \text{file offset} \pmod{\text{page size}} + \text{virtual address} \equiv \text{file offset} \pmod{\text{alignment}} + )delim"_doc) + + .def_prop_rw("physical_address", + nb::overload_cast<>(&Segment::physical_address, nb::const_), + nb::overload_cast(&Segment::physical_address), + R"delim( + The physical address of the segment. This value is not really relevant + on systems like Linux or Android. On the other hand, Qualcomm trustlets + might use this value. + + Usually this value matches :attr:`~lief.ELF.Segment.virtual_address` + )delim"_doc) + + .def_prop_rw("physical_size", + nb::overload_cast<>(&Segment::physical_size, nb::const_), + nb::overload_cast(&Segment::physical_size), + "The **file** size of the data associated with this segment"_doc) + + .def_prop_rw("virtual_size", + nb::overload_cast<>(&Segment::virtual_size, nb::const_), + nb::overload_cast(&Segment::virtual_size), + R"delim( + The in-memory size of this segment. + + Usually, if the ``.bss`` segment is wrapped by this segment + then, virtual_size is larger than physical_size + )delim"_doc) + + .def_prop_rw("alignment", + nb::overload_cast<>(&Segment::alignment, nb::const_), + nb::overload_cast(&Segment::alignment), + "The offset alignment of the segment"_doc) + + .def_prop_rw("content", + nb::overload_cast<>(&Segment::content, nb::const_), + nb::overload_cast>(&Segment::content), + "The raw data associated with this segment."_doc) + + .def("add", &Segment::add, + "Add the given flag to the list of :attr:`~lief.ELF.Segment.flags`"_doc, + "flag"_a) + + .def("remove", &Segment::remove, + "Remove the given flag from the list of :attr:`~lief.ELF.Segment.flags`"_doc, + "flag"_a) + + .def("has", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given flag is present"_doc, + "flag"_a) + + .def("has", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Section) " is present " + "in :attr:`~lief.ELF.Segment.sections`"_doc, + "section"_a) + + .def("has", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Section) " 's name is present " + "in :attr:`~lief.ELF.Segment.sections`"_doc, + "section_name"_a) + + .def("clear", &Segment::clear, "Clear the content of this segment"_doc) + + .def("fill", &Segment::fill, + "value"_a, + "Fill the content of this segment with the value provided in parameter"_doc + ) + + .def_prop_ro("sections", + nb::overload_cast<>(&Segment::sections), + "Iterator over the " RST_CLASS_REF(lief.ELF.Section) " wrapped by this segment"_doc, + nb::keep_alive<0, 1>()) + + .def(nb::self += Segment::FLAGS()) + .def(nb::self -= Segment::FLAGS()) + + .def("__contains__", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given flag is present"_doc) + + .def("__contains__", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Section) " is present " + "in :attr:`~lief.ELF.Segment.sections`"_doc) + + .def("__contains__", + nb::overload_cast(&Segment::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.ELF.Section) " 's name is present " + "in :attr:`~lief.ELF.Segment.sections`"_doc) + + LIEF_DEFAULT_STR(Segment); + +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbol.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbol.cpp new file mode 100644 index 0000000..99471ed --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbol.cpp @@ -0,0 +1,172 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" +#include "pyIterator.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/Symbol.hpp" +#include "LIEF/ELF/SymbolVersion.hpp" +#include "LIEF/ELF/Section.hpp" + +#include +#include +#include + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + + nb::class_ sym(m, "Symbol", + R"delim( + Class which represents an ELF symbol + )delim"_doc); + + #define ENTRY(X) .value(to_string(Symbol::BINDING::X), Symbol::BINDING::X) + enum_(sym, "BINDING") + ENTRY(LOCAL) + ENTRY(GLOBAL) + ENTRY(WEAK) + ENTRY(GNU_UNIQUE) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Symbol::TYPE::X), Symbol::TYPE::X) + enum_(sym, "TYPE") + ENTRY(NOTYPE) + ENTRY(OBJECT) + ENTRY(FUNC) + ENTRY(SECTION) + ENTRY(FILE) + ENTRY(COMMON) + ENTRY(TLS) + ENTRY(GNU_IFUNC) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(Symbol::VISIBILITY::X), Symbol::VISIBILITY::X) + enum_(sym, "VISIBILITY") + ENTRY(DEFAULT) + ENTRY(INTERNAL) + ENTRY(HIDDEN) + ENTRY(PROTECTED) + ; + #undef ENTRY + + sym + .def(nb::init<>()) + .def_prop_ro("demangled_name", + &Symbol::demangled_name, + "Symbol's name demangled or an empty string if the demangling is not possible/failed"_doc) + + .def_prop_rw("type", + nb::overload_cast<>(&Symbol::type, nb::const_), + nb::overload_cast(&Symbol::type), + "The symbol's type provides a general classification for the associated entity."_doc) + + .def_prop_rw("binding", + nb::overload_cast<>(&Symbol::binding, nb::const_), + nb::overload_cast(&Symbol::binding), + "A symbol's binding determines the linkage visibility and behavior."_doc) + + .def_prop_rw("information", + nb::overload_cast<>(&Symbol::information, nb::const_), + nb::overload_cast(&Symbol::information), + "This property specifies the symbol's type and binding attributes"_doc) + + .def_prop_rw("other", + nb::overload_cast<>(&Symbol::other, nb::const_), + nb::overload_cast(&Symbol::other), + "Alias for " RST_ATTR_REF(lief.ELF.Symbol.visibility) ""_doc) + + .def_prop_rw("visibility", + nb::overload_cast<>(&Symbol::visibility, nb::const_), + nb::overload_cast(&Symbol::visibility), + R"delim( + Symbol visibility. It's basically an alias on :attr:`~.Symbol.other` + )delim"_doc) + + .def_prop_rw("value", // Even though it is already defined in the base class (Abstract/Symbol) + // We keep the definition to provide a dedicated documentation + nb::overload_cast<>(&Symbol::value, nb::const_), + nb::overload_cast(&Symbol::value), + R"delim( + This member has different meaning depending on the symbol's type and the type of the ELF file (library, object, ...) + + - In relocatable files, this property contains the alignment constraints + of the symbol for which the section index is `SHN_COMMON`. + - In relocatable files, can also contain a section's offset for a defined symbol. + That is, `value` is an offset from the beginning of the section associated with this symbol. + - In executable and libraries, this property contains a virtual address. + )delim"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&Symbol::size, nb::const_), + nb::overload_cast(&Symbol::size), + "Many symbols have associated sizes. For example, a data object's size is the number of " + "bytes contained in the object. This member holds `0` if the symbol has no size or " + "an unknown size."_doc) + + .def_prop_rw("shndx", + nb::overload_cast<>(&Symbol::shndx, nb::const_), + nb::overload_cast(&Symbol::shndx), + "Section index associated with the symbol"_doc) + + .def_prop_ro("has_version", + &Symbol::has_version, + "Check if this symbols has a " RST_CLASS_REF(lief.ELF.SymbolVersion) ""_doc) + + .def_prop_ro("symbol_version", + nb::overload_cast<>(&Symbol::symbol_version), + R"delim( + Return the :class:`~lief.ELF.SymbolVersion` associated with this symbol + + It returns None if no version is tied to this symbol. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("section", + nb::overload_cast<>(&Symbol::section), + R"delim( + Return the section (:class:`~lief.ELF.Section`) associated with this symbol + if any. Otherwise, return None. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("is_static", + &Symbol::is_static, + "True if the symbol has static visibility"_doc) + + .def_prop_ro("is_function", + &Symbol::is_function, + "True if the symbol is a function"_doc) + + .def_prop_ro("is_variable", + &Symbol::is_variable, + "True if the symbol is a variable"_doc) + + .def_prop_rw("exported", + &Symbol::is_exported, &Symbol::set_exported, + "Whether the symbol is **exported**"_doc) + + .def_prop_rw("imported", + &Symbol::is_imported, &Symbol::set_imported, + "Whether the symbol is **imported**"_doc) + + LIEF_DEFAULT_STR(Symbol); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbolVersion.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbolVersion.cpp new file mode 100644 index 0000000..a130b3c --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbolVersion.cpp @@ -0,0 +1,92 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/SymbolVersion.hpp" +#include "LIEF/ELF/SymbolVersionAux.hpp" +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" + +#include +#include +#include + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SymbolVersion") + .def(nb::init<>(),"Default constructor") + .def(nb::init(), "Constructor from :attr:`~lief.SymbolVersion.value`"_doc) + + .def_prop_ro_static("local", + [] (const nb::object&) { + return SymbolVersion::local(); + }, + "Generate a *local* " RST_CLASS_REF(lief.ELF.SymbolVersion) ""_doc) + + .def_prop_ro_static("global_", + [] (const nb::object&) { + return SymbolVersion::global(); + }, + "Generate a *global* " RST_CLASS_REF(lief.ELF.SymbolVersion) ""_doc) + + .def_prop_rw("value", + nb::overload_cast<>(&SymbolVersion::value, nb::const_), + nb::overload_cast(&SymbolVersion::value), + R"delim( + Value associated with the symbol. + + If the given SymbolVersion has no auxiliary version: + + - `0` : The symbol is local + - `1` : The symbol is global + + All other values are used for versions in the own object or in any of + the dependencies. This is the version the symbol is tied to. + )delim"_doc) + + .def_prop_ro("has_auxiliary_version", + &SymbolVersion::has_auxiliary_version, + "Check if this symbols has a " RST_CLASS_REF(lief.ELF.SymbolVersionAux) ""_doc) + + .def_prop_rw( + "symbol_version_auxiliary", + nb::overload_cast<>(&SymbolVersion::symbol_version_auxiliary), + nb::overload_cast(&SymbolVersion::symbol_version_auxiliary), + R"delim( + Return the :class:`~lief.ELF.SymbolVersionAux` associated with this version or None if not present. + + The value can be changed by assigning a :class:`~lief.ELF.SymbolVersionAuxRequirement` which + must already exist in the :class:`~lief.ELF.SymbolVersionRequirement`. One can use + :meth:`~lief.ELF.SymbolVersionAuxRequirement.add_aux_requirement` to add a new + :class:`~lief.ELF.SymbolVersionAuxRequirement`. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def("drop_version", &SymbolVersion::drop_version, + "Drop the versioning requirement and replace the value (local/global)"_doc, + "value"_a) + + .def("as_global", &SymbolVersion::as_global, + "Redefine this version as global by dropping its auxiliary version"_doc) + + .def("as_local", &SymbolVersion::as_local, + "Redefine this version as local by dropping its auxiliary version"_doc) + + LIEF_DEFAULT_STR(SymbolVersion); + +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAux.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAux.cpp new file mode 100644 index 0000000..688f9ff --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAux.cpp @@ -0,0 +1,41 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" +#include "pySafeString.hpp" + +#include "LIEF/ELF/SymbolVersionAux.hpp" + +#include +#include +#include + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SymbolVersionAux", + "Class which represents an Auxiliary Symbol version"_doc) + + .def_prop_rw("name", + [] (const SymbolVersionAux& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&SymbolVersionAux::name), + "Symbol's name (e.g. ``GLIBC_2.2.5``)"_doc) + + LIEF_DEFAULT_STR(SymbolVersionAux); +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAuxRequirement.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAuxRequirement.cpp new file mode 100644 index 0000000..3586e07 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionAuxRequirement.cpp @@ -0,0 +1,54 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" + +#include +#include +#include + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SymbolVersionAuxRequirement") + .def(nb::init<>(),"Default constructor"_doc) + + .def_prop_rw("hash", + nb::overload_cast<>(&SymbolVersionAuxRequirement::hash, nb::const_), + nb::overload_cast(&SymbolVersionAuxRequirement::hash), + "Hash value of the dependency name (use ELF hashing function)"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&SymbolVersionAuxRequirement::flags, nb::const_), + nb::overload_cast(&SymbolVersionAuxRequirement::flags), + "Bitmask of flags"_doc) + + .def_prop_rw("other", + nb::overload_cast<>(&SymbolVersionAuxRequirement::other, nb::const_), + nb::overload_cast(&SymbolVersionAuxRequirement::other), + R"delim( + It returns the unique version index for the file which is used in the + version symbol table. If the highest bit (bit 15) is set this + is a hidden symbol which cannot be referenced from outside the + object. + )delim"_doc) + + LIEF_DEFAULT_STR(SymbolVersionAuxRequirement); + +} +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbolVersionDefinition.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionDefinition.cpp new file mode 100644 index 0000000..1dbdff5 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionDefinition.cpp @@ -0,0 +1,67 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "pyIterator.hpp" +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/SymbolVersionAux.hpp" +#include "LIEF/ELF/SymbolVersionDefinition.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ sym_ver_def(m, "SymbolVersionDefinition", + "Class which represents an entry defined in ``DT_VERDEF`` or ``.gnu.version_d``"_doc); + + init_ref_iterator(sym_ver_def, "it_version_aux"); + sym_ver_def + .def_prop_rw("version", + nb::overload_cast<>(&SymbolVersionDefinition::version, nb::const_), + nb::overload_cast(&SymbolVersionDefinition::version), + R"delim( + Version revision. Should be 1 + + This field should always have the value ``1``. It will be changed + if the versioning implementation has to be changed in an incompatible way. + )delim"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&SymbolVersionDefinition::flags, nb::const_), + nb::overload_cast(&SymbolVersionDefinition::flags), + "Version information"_doc) + + .def_prop_rw("hash", + nb::overload_cast<>(&SymbolVersionDefinition::hash, nb::const_), + nb::overload_cast(&SymbolVersionDefinition::hash), + "Hash value of the symbol's name (using ELF hash function)"_doc) + + .def_prop_ro("ndx", &SymbolVersionDefinition::ndx, + "Numeric value used as an index in the :class:`~.ELF.SymbolVersion` table"_doc) + + .def_prop_ro("auxiliary_symbols", + nb::overload_cast<>(&SymbolVersionDefinition::symbols_aux), + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(SymbolVersionDefinition); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySymbolVersionRequirement.cpp b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionRequirement.cpp new file mode 100644 index 0000000..65e3c9c --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySymbolVersionRequirement.cpp @@ -0,0 +1,97 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/ELF/SymbolVersionAux.hpp" +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" +#include "LIEF/ELF/SymbolVersionRequirement.hpp" + +#include "pyIterator.hpp" +#include "ELF/pyELF.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + // Symbol Version Requirement object + nb::class_ sym_ver_req(m, "SymbolVersionRequirement", + "Class which represents an entry in the ``DT_VERNEED`` or ``.gnu.version_r`` table"_doc); + + init_ref_iterator(sym_ver_req, "it_aux_requirement"); + + sym_ver_req + .def_prop_rw("version", + nb::overload_cast<>(&SymbolVersionRequirement::version, nb::const_), + nb::overload_cast(&SymbolVersionRequirement::version), + "Version revision. Should be 1"_doc) + + .def_prop_rw("name", + nb::overload_cast<>(&SymbolVersionRequirement::name, nb::const_), + nb::overload_cast(&SymbolVersionRequirement::name), + "Library's name associated with this requirement (e.g. ``libc.so.6``)"_doc) + + .def("get_auxiliary_symbols", + nb::overload_cast<>(&SymbolVersionRequirement::auxiliary_symbols), + "Auxiliary entries (iterator over " RST_CLASS_REF(lief.ELF.SymbolVersionAuxRequirement) ")"_doc, + nb::rv_policy::reference_internal) + + .def("add_auxiliary_requirement", + static_cast(&SymbolVersionRequirement::add_aux_requirement), + "Add an auxiliary version requirement to the existing entries"_doc, + nb::lock_self()) + + .def("find_aux", nb::overload_cast(&SymbolVersionRequirement::find_aux), + R"doc( + Try to find the :class:`~.SymbolVersionAuxRequirement` with the given name + (e.g. ``GLIBC_2.27``) + )doc"_doc, + nb::rv_policy::reference_internal, "name"_a) + + .def("remove_aux_requirement", nb::overload_cast(&SymbolVersionRequirement::remove_aux_requirement), + R"doc( + Try to remove the auxiliary requirement symbol with the given name. + The function returns true if the operation succeeds, false otherwise. + + .. warning:: + + This function invalidates all the references (pointers) of + :class:`~.SymbolVersionAuxRequirement`. Therefore, the user is responsible + to ensure that the auxiliary requirement is no longer used in the + ELF binary (e.g. in :class:`~.SymbolVersion`) + )doc"_doc, "name"_a, nb::lock_self()) + + .def("remove_aux_requirement", nb::overload_cast(&SymbolVersionRequirement::remove_aux_requirement), + R"doc( + Try to remove the given auxiliary requirement symbol. + The function returns true if the operation succeeds, false otherwise. + + .. warning:: + + This function invalidates all the references (pointers) of + :class:`~.SymbolVersionAuxRequirement`. Therefore, the user is responsible + to ensure that the auxiliary requirement is no longer used in the + ELF binary (e.g. in :class:`~.SymbolVersion`) + )doc"_doc, "aux"_a, nb::lock_self()) + + LIEF_DEFAULT_STR(SymbolVersionRequirement); +} + +} diff --git a/vendor/lief/api/python/src/ELF/objects/pySysvHash.cpp b/vendor/lief/api/python/src/ELF/objects/pySysvHash.cpp new file mode 100644 index 0000000..f70be2b --- /dev/null +++ b/vendor/lief/api/python/src/ELF/objects/pySysvHash.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "ELF/pyELF.hpp" + +#include "LIEF/ELF/SysvHash.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SysvHash", + R"delim( + Class which represents the SYSV hash for the symbols resolution + + References: + + * http://www.linker-aliens.org/blogs/ali/entry/gnu_hash_elf_sections/ + * https://docs.oracle.com/cd/E23824_01/html/819-0690/chapter6-48031.html + )delim"_doc) + .def(nb::init<>()) + + .def_prop_ro("nbucket", + &SysvHash::nbucket, + "Return the number of buckets"_doc) + + .def_prop_rw("nchain", + nb::overload_cast<>(&SysvHash::nchain, nb::const_), + nb::overload_cast(&SysvHash::nchain), + "Return the number of *chains* (symbol table index)"_doc) + + .def_prop_ro("buckets", + &SysvHash::buckets, + "Buckets values"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("chains", + &SysvHash::chains, + "Chains values"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(SysvHash); +} +} diff --git a/vendor/lief/api/python/src/ELF/pyELF.hpp b/vendor/lief/api/python/src/ELF/pyELF.hpp new file mode 100644 index 0000000..13c678d --- /dev/null +++ b/vendor/lief/api/python/src/ELF/pyELF.hpp @@ -0,0 +1,24 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ELF_H +#define PY_LIEF_ELF_H +#include "pyLIEF.hpp" + +namespace LIEF::ELF::py { +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/ELF/pyProcessorFlags.cpp b/vendor/lief/api/python/src/ELF/pyProcessorFlags.cpp new file mode 100644 index 0000000..f9f3615 --- /dev/null +++ b/vendor/lief/api/python/src/ELF/pyProcessorFlags.cpp @@ -0,0 +1,103 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ELF/pyELF.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/ELF/ProcessorFlags.hpp" + +namespace LIEF::ELF::py { + +template<> +void create(nb::module_& m) { + #define ENTRY(X) .value(to_string(PROCESSOR_FLAGS::X), PROCESSOR_FLAGS::X) + enum_(m, "PROCESSOR_FLAGS") + ENTRY(ARM_EABI_UNKNOWN) + ENTRY(ARM_SOFT_FLOAT) + ENTRY(ARM_VFP_FLOAT) + ENTRY(ARM_EABI_VER1) + ENTRY(ARM_EABI_VER2) + ENTRY(ARM_EABI_VER3) + ENTRY(ARM_EABI_VER4) + ENTRY(ARM_EABI_VER5) + ENTRY(HEXAGON_MACH_V2) + ENTRY(HEXAGON_MACH_V3) + ENTRY(HEXAGON_MACH_V4) + ENTRY(HEXAGON_MACH_V5) + ENTRY(HEXAGON_ISA_V2) + ENTRY(HEXAGON_ISA_V3) + ENTRY(HEXAGON_ISA_V4) + ENTRY(HEXAGON_ISA_V5) + ENTRY(LOONGARCH_ABI_SOFT_FLOAT) + ENTRY(LOONGARCH_ABI_SINGLE_FLOAT) + ENTRY(LOONGARCH_ABI_DOUBLE_FLOAT) + ENTRY(MIPS_NOREORDER) + ENTRY(MIPS_PIC) + ENTRY(MIPS_CPIC) + ENTRY(MIPS_ABI2) + ENTRY(MIPS_32BITMODE) + ENTRY(MIPS_FP64) + ENTRY(MIPS_NAN2008) + ENTRY(MIPS_ABI_O32) + ENTRY(MIPS_ABI_O64) + ENTRY(MIPS_ABI_EABI32) + ENTRY(MIPS_ABI_EABI64) + ENTRY(MIPS_MACH_3900) + ENTRY(MIPS_MACH_4010) + ENTRY(MIPS_MACH_4100) + ENTRY(MIPS_MACH_4650) + ENTRY(MIPS_MACH_4120) + ENTRY(MIPS_MACH_4111) + ENTRY(MIPS_MACH_SB1) + ENTRY(MIPS_MACH_OCTEON) + ENTRY(MIPS_MACH_XLR) + ENTRY(MIPS_MACH_OCTEON2) + ENTRY(MIPS_MACH_OCTEON3) + ENTRY(MIPS_MACH_5400) + ENTRY(MIPS_MACH_5900) + ENTRY(MIPS_MACH_5500) + ENTRY(MIPS_MACH_9000) + ENTRY(MIPS_MACH_LS2E) + ENTRY(MIPS_MACH_LS2F) + ENTRY(MIPS_MACH_LS3A) + ENTRY(MIPS_MICROMIPS) + ENTRY(MIPS_ARCH_ASE_M16) + ENTRY(MIPS_ARCH_ASE_MDMX) + ENTRY(MIPS_ARCH_1) + ENTRY(MIPS_ARCH_2) + ENTRY(MIPS_ARCH_3) + ENTRY(MIPS_ARCH_4) + ENTRY(MIPS_ARCH_5) + ENTRY(MIPS_ARCH_32) + ENTRY(MIPS_ARCH_64) + ENTRY(MIPS_ARCH_32R2) + ENTRY(MIPS_ARCH_64R2) + ENTRY(MIPS_ARCH_32R6) + ENTRY(MIPS_ARCH_64R6) + ENTRY(RISCV_RVC) + ENTRY(RISCV_FLOAT_ABI_SOFT) + ENTRY(RISCV_FLOAT_ABI_SINGLE) + ENTRY(RISCV_FLOAT_ABI_DOUBLE) + ENTRY(RISCV_FLOAT_ABI_QUAD) + ENTRY(RISCV_FLOAT_ABI_RVE) + ENTRY(RISCV_FLOAT_ABI_TSO) + ; + #undef ENTRY + +} + +} diff --git a/vendor/lief/api/python/src/MachO/CMakeLists.txt b/vendor/lief/api/python/src/MachO/CMakeLists.txt new file mode 100644 index 0000000..0c773d1 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + enums.cpp + pyUtils.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/MachO/enums.cpp b/vendor/lief/api/python/src/MachO/enums.cpp new file mode 100644 index 0000000..7b676d4 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/enums.cpp @@ -0,0 +1,124 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "MachO/pyMachO.hpp" +#include "LIEF/MachO/enums.hpp" +#include "LIEF/MachO/EnumToString.hpp" +#include "LIEF/MachO/DyldChainedFormat.hpp" + +#include "enums_wrapper.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::MachO::py { +void init_enums(nb::module_& m) { + + enum_(m, "MACHO_TYPES") + .value(PY_ENUM(MACHO_TYPES::MAGIC)) + .value(PY_ENUM(MACHO_TYPES::CIGAM)) + .value(PY_ENUM(MACHO_TYPES::MAGIC_64)) + .value(PY_ENUM(MACHO_TYPES::CIGAM_64)) + .value(PY_ENUM(MACHO_TYPES::MAGIC_FAT)) + .value(PY_ENUM(MACHO_TYPES::CIGAM_FAT)) + .value(PY_ENUM(MACHO_TYPES::NEURAL_MODEL)) + ; + + enum_(m, "X86_RELOCATION") + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_VANILLA)) + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_PAIR)) + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_SECTDIFF)) + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_PB_LA_PTR)) + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_LOCAL_SECTDIFF)) + .value(PY_ENUM(X86_RELOCATION::GENERIC_RELOC_TLV)); + + enum_(m, "X86_64_RELOCATION") + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_UNSIGNED)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_SIGNED)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_BRANCH)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_GOT_LOAD)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_GOT)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_SUBTRACTOR)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_SIGNED_1)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_SIGNED_2)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_SIGNED_4)) + .value(PY_ENUM(X86_64_RELOCATION::X86_64_RELOC_TLV)); + + enum_(m, "PPC_RELOCATION") + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_VANILLA)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_PAIR)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_BR14)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_BR24)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_HI16)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_LO16)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_HA16)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_LO14)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_SECTDIFF)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_PB_LA_PTR)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_HI16_SECTDIFF)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_LO16_SECTDIFF)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_HA16_SECTDIFF)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_JBSR)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_LO14_SECTDIFF)) + .value(PY_ENUM(PPC_RELOCATION::PPC_RELOC_LOCAL_SECTDIFF)); + + enum_(m, "ARM_RELOCATION") + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_VANILLA)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_PAIR)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_SECTDIFF)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_LOCAL_SECTDIFF)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_PB_LA_PTR)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_BR24)) + .value(PY_ENUM(ARM_RELOCATION::ARM_THUMB_RELOC_BR22)) + .value(PY_ENUM(ARM_RELOCATION::ARM_THUMB_32BIT_BRANCH)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_HALF)) + .value(PY_ENUM(ARM_RELOCATION::ARM_RELOC_HALF_SECTDIFF)); + + enum_(m, "ARM64_RELOCATION") + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_UNSIGNED)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_SUBTRACTOR)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_BRANCH26)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_PAGE21)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_PAGEOFF12)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_GOT_LOAD_PAGE21)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_GOT_LOAD_PAGEOFF12)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_POINTER_TO_GOT)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_TLVP_LOAD_PAGE21)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_TLVP_LOAD_PAGEOFF12)) + .value(PY_ENUM(ARM64_RELOCATION::ARM64_RELOC_ADDEND)); + + enum_(m, "DYLD_CHAINED_FORMAT") + .value(PY_ENUM(DYLD_CHAINED_FORMAT::IMPORT)) + .value(PY_ENUM(DYLD_CHAINED_FORMAT::IMPORT_ADDEND)) + .value(PY_ENUM(DYLD_CHAINED_FORMAT::IMPORT_ADDEND64)); + + enum_(m, "DYLD_CHAINED_PTR_FORMAT") + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::NONE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_64)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_32)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_32_CACHE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_32_FIRMWARE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_64_OFFSET)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_KERNEL)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_64_KERNEL_CACHE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_USERLAND)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_FIRMWARE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_X86_64_KERNEL_CACHE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_USERLAND24)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_SHARED_CACHE)) + .value(PY_ENUM(DYLD_CHAINED_PTR_FORMAT::PTR_ARM64E_SEGMENTED)); + +} +} diff --git a/vendor/lief/api/python/src/MachO/enums.hpp b/vendor/lief/api/python/src/MachO/enums.hpp new file mode 100644 index 0000000..679ed0a --- /dev/null +++ b/vendor/lief/api/python/src/MachO/enums.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_MACHO_ENUMS_H +#define PY_LIEF_MACHO_ENUMS_H +#include "pyLIEF.hpp" + +namespace LIEF::MachO::py { +void init_enums(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/MachO/init.cpp b/vendor/lief/api/python/src/MachO/init.cpp new file mode 100644 index 0000000..10ef2c5 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/init.cpp @@ -0,0 +1,147 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "MachO/init.hpp" +#include "MachO/enums.hpp" +#include "MachO/pyMachO.hpp" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE(X,Y) create(Y) + +namespace LIEF::MachO::py { + +void init_objects(nb::module_& m) { + CREATE(ParserConfig, m); + CREATE(Parser, m); + + CREATE(ChainedPointerAnalysis, m); + CREATE(FatBinary, m); + CREATE(Binary, m); + CREATE(Header, m); + CREATE(LoadCommand, m); + CREATE(UUIDCommand, m); + CREATE(SymbolCommand, m); + CREATE(SegmentCommand, m); + CREATE(Section, m); + CREATE(MainCommand, m); + CREATE(NoteCommand, m); + CREATE(DynamicSymbolCommand, m); + CREATE(DylinkerCommand, m); + CREATE(DyldInfo, m); + CREATE(DyldChainedFixups, m); + CREATE(DyldExportsTrie, m); + CREATE(DylibCommand, m); + CREATE(ThreadCommand, m); + CREATE(ThreadLocalVariables, m); + CREATE(RPathCommand, m); + CREATE(Symbol, m); + CREATE(Relocation, m); + CREATE(RelocationObject, m); + CREATE(RelocationDyld, m); + CREATE(RelocationFixup, m); + CREATE(BindingInfo, m); + CREATE(DyldBindingInfo, m); + CREATE(ExportInfo, m); + CREATE(FunctionStarts, m); + CREATE(FunctionVariants, m); + CREATE(FunctionVariantFixups, m); + CREATE(LazyLoadDylibInfo, m); + CREATE(AtomInfo, m); + CREATE(CodeSignature, m); + CREATE(CodeSignatureDir, m); + CREATE(DataInCode, m); + CREATE(DataCodeEntry, m); + CREATE(SourceVersion, m); + CREATE(Routine, m); + CREATE(VersionMin, m); + CREATE(SegmentSplitInfo, m); + CREATE(SubFramework, m); + CREATE(SubClient, m); + CREATE(DyldEnvironment, m); + CREATE(EncryptionInfo, m); + CREATE(BuildVersion, m); + CREATE(FilesetCommand, m); + CREATE(ChainedBindingInfo, m); + CREATE(TwoLevelHints, m); + CREATE(LinkerOptHint, m); + CREATE(IndirectBindingInfo, m); + CREATE(UnknownCommand, m); + CREATE(Stub, m); + CREATE(Builder, m); +} + +void init(nb::module_& m) { + nb::module_ macho_mod = m.def_submodule("MachO", "Python API for the MachO format"); + init_enums(macho_mod); + init_objects(macho_mod); + init_utils(macho_mod); +} +} diff --git a/vendor/lief/api/python/src/MachO/init.hpp b/vendor/lief/api/python/src/MachO/init.hpp new file mode 100644 index 0000000..337980c --- /dev/null +++ b/vendor/lief/api/python/src/MachO/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_MACHO_INIT_H +#define PY_LIEF_MACHO_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::MachO::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/MachO/objects/CMakeLists.txt b/vendor/lief/api/python/src/MachO/objects/CMakeLists.txt new file mode 100644 index 0000000..0b2f8fe --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/CMakeLists.txt @@ -0,0 +1,58 @@ +target_sources(pyLIEF PRIVATE + pyAtomInfo.cpp + pyBinary.cpp + pyBindingInfo.cpp + pyBuildVersion.cpp + pyBuilder.cpp + pyChainedBindingInfo.cpp + pyChainedPointerAnalysis.cpp + pyCodeSignature.cpp + pyCodeSignatureDir.cpp + pyDataCodeEntry.cpp + pyDataInCode.cpp + pyDyldBindingInfo.cpp + pyDyldChainedFixups.cpp + pyDyldEnvironment.cpp + pyDyldExportsTrie.cpp + pyDyldInfo.cpp + pyDylibCommand.cpp + pyDylinker.cpp + pyDynamicSymbolCommand.cpp + pyEncryptionInfo.cpp + pyExportInfo.cpp + pyFatBinary.cpp + pyFilesetCommand.cpp + pyFunctionStarts.cpp + pyFunctionVariants.cpp + pyFunctionVariantFixups.cpp + pyHeader.cpp + pyIndirectBindingInfo.cpp + pyLazyLoadDylibInfo.cpp + pyLinkerOptHint.cpp + pyLoadCommand.cpp + pyMainCommand.cpp + pyNoteCommand.cpp + pyParser.cpp + pyParserConfig.cpp + pyRPathCommand.cpp + pyRelocation.cpp + pyRelocationDyld.cpp + pyRelocationFixup.cpp + pyRelocationObject.cpp + pyRoutine.cpp + pySection.cpp + pySegmentCommand.cpp + pySegmentSplitInfo.cpp + pySourceVersion.cpp + pyStub.cpp + pySubClient.cpp + pySubFramework.cpp + pySymbol.cpp + pySymbolCommand.cpp + pyThreadCommand.cpp + pyThreadLocalVariables.cpp + pyTwoLevelHints.cpp + pyUUID.cpp + pyUnknownCommand.cpp + pyVersionMin.cpp +) diff --git a/vendor/lief/api/python/src/MachO/objects/pyAtomInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyAtomInfo.cpp new file mode 100644 index 0000000..cab3ceb --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyAtomInfo.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/AtomInfo.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "AtomInfo", + R"delim( + Class which represents the LC_ATOM_INFO command + )delim"_doc) + + .def_prop_rw("data_offset", + nb::overload_cast<>(&AtomInfo::data_offset, nb::const_), + nb::overload_cast(&AtomInfo::data_offset), + "Offset in the binary where the payload starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&AtomInfo::data_size, nb::const_), + nb::overload_cast(&AtomInfo::data_size), + "Size of the payload"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&AtomInfo::content, nb::const_), + "The original payload"_doc) + + LIEF_DEFAULT_STR(AtomInfo); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyBinary.cpp b/vendor/lief/api/python/src/MachO/objects/pyBinary.cpp new file mode 100644 index 0000000..f381af7 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyBinary.cpp @@ -0,0 +1,857 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "nanobind/utils.hpp" +#include +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/extra/stl/pathlike.h" +#include "nanobind/extra/random_access_iterator.hpp" + +#include "LIEF/MachO/Binary.hpp" +#include "LIEF/MachO/BuildVersion.hpp" +#include "LIEF/MachO/Builder.hpp" +#include "LIEF/MachO/ChainedBindingInfo.hpp" +#include "LIEF/MachO/CodeSignature.hpp" +#include "LIEF/MachO/CodeSignatureDir.hpp" +#include "LIEF/MachO/DataInCode.hpp" +#include "LIEF/MachO/DyldBindingInfo.hpp" +#include "LIEF/MachO/DyldChainedFixups.hpp" +#include "LIEF/MachO/DyldEnvironment.hpp" +#include "LIEF/MachO/DyldExportsTrie.hpp" +#include "LIEF/MachO/DyldInfo.hpp" +#include "LIEF/MachO/DylibCommand.hpp" +#include "LIEF/MachO/DylinkerCommand.hpp" +#include "LIEF/MachO/DynamicSymbolCommand.hpp" +#include "LIEF/MachO/EncryptionInfo.hpp" +#include "LIEF/MachO/ExportInfo.hpp" +#include "LIEF/MachO/FunctionStarts.hpp" +#include "LIEF/MachO/FunctionVariants.hpp" +#include "LIEF/MachO/FunctionVariantFixups.hpp" +#include "LIEF/MachO/LazyLoadDylibInfo.hpp" +#include "LIEF/MachO/LinkEdit.hpp" +#include "LIEF/MachO/LinkerOptHint.hpp" +#include "LIEF/MachO/AtomInfo.hpp" +#include "LIEF/MachO/MainCommand.hpp" +#include "LIEF/MachO/NoteCommand.hpp" +#include "LIEF/MachO/Routine.hpp" +#include "LIEF/MachO/RPathCommand.hpp" +#include "LIEF/MachO/Relocation.hpp" +#include "LIEF/MachO/RelocationFixup.hpp" +#include "LIEF/MachO/Section.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" +#include "LIEF/MachO/SegmentSplitInfo.hpp" +#include "LIEF/MachO/SourceVersion.hpp" +#include "LIEF/MachO/SubFramework.hpp" +#include "LIEF/MachO/SubClient.hpp" +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/MachO/SymbolCommand.hpp" +#include "LIEF/MachO/ThreadCommand.hpp" +#include "LIEF/MachO/TwoLevelHints.hpp" +#include "LIEF/MachO/UUIDCommand.hpp" +#include "LIEF/MachO/VersionMin.hpp" + +#include "LIEF/ObjC/Metadata.hpp" + +#include "pyErr.hpp" +#include "MachO/pyMachO.hpp" +#include "pyIterator.hpp" + +namespace LIEF::MachO::py { +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ bin(m, "Binary", + R"delim( + Class which represents a MachO binary + )delim"_doc); + + init_ref_iterator(bin, "it_commands"); + + init_ref_iterator(bin, "it_symbols"); + init_ref_iterator(bin, "it_filter_symbols"); + init_ref_iterator(bin, "it_sections"); + init_ref_iterator(bin, "it_segments"); + init_ref_iterator(bin, "it_libraries"); + init_ref_iterator(bin, "it_lazy_load_dylib_info"); + init_ref_iterator(bin, "it_relocations"); + init_ref_iterator(bin, "it_rpaths"); + init_ref_iterator(bin, "it_sub_clients"); + init_ref_iterator(bin, "it_notes"); + + nb::class_(bin, "range_t") + .def_rw("start", &Binary::range_t::start) + .def_rw("end", &Binary::range_t::end); + + // --> Already registered with FatMachO (same container) + //init_ref_iterator(bin, "it_fileset_binaries"); + + bin + .def_prop_ro("header", + nb::overload_cast<>(&Binary::header), + "Return binary's " RST_CLASS_REF(lief.MachO.Header) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("sections", + nb::overload_cast<>(&Binary::sections), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Section) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Binary::relocations), + "Return an iterator over binary's " RST_CLASS_REF(lief.MachO.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("segments", + nb::overload_cast<>(&Binary::segments), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.SegmentCommand) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("libraries", + nb::overload_cast<>(&Binary::libraries), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.DylibCommand) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("lazy_load_dylib_infos", + nb::overload_cast<>(&Binary::lazy_load_dylib_infos), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.LazyLoadDylibInfo) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Binary::symbols), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Symbol) ""_doc, + nb::keep_alive<0, 1>()) + + .def("has_symbol", + &Binary::has_symbol, + "Check if a " RST_CLASS_REF(lief.MachO.Symbol) " with the given name exists"_doc, + "name"_a) + + .def("get_symbol", + nb::overload_cast(&Binary::get_symbol), + "Return the " RST_CLASS_REF(lief.MachO.Symbol) " from the given name"_doc, + "name"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("imported_symbols", + nb::overload_cast<>(&Binary::imported_symbols), + "Return the binary's " RST_CLASS_REF(lief.MachO.Symbol) " which are imported"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("exported_symbols", + nb::overload_cast<>(&Binary::exported_symbols), + "Return the binary's " RST_CLASS_REF(lief.MachO.Symbol) " which are exported"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("commands", + nb::overload_cast<>(&Binary::commands), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.Command) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("filesets", + nb::overload_cast<>(&Binary::filesets), + "Return binary's " RST_CLASS_REF(lief.MachO.Filesets) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_filesets", + &Binary::has_filesets, + "Return ``True`` if the binary has filesets"_doc) + + .def_prop_ro("fileset_name", &Binary::fileset_name, + R"doc( + Name associated with the ``LC_FILESET_ENTRY`` for this MachO. + For instance: ``com.apple.kec.corecrypto`` + )doc"_doc) + + .def_prop_ro("fileset_addr", &Binary::fileset_addr, + "Original address associated with the ``LC_FILESET_ENTRY`` for this MachO."_doc) + + .def_prop_ro("imagebase", + &Binary::imagebase, + R"delim( + Return the binary's ``imagebase`` which is the base address + where segments are mapped (without the ASLR). ``0`` if not relevant. + )delim"_doc) + + .def_prop_ro("virtual_size", + &Binary::virtual_size, + "Binary's memory size when mapped"_doc) + + .def_prop_ro("fat_offset", + &Binary::fat_offset, + "Return binary's *fat offset*. ``0`` if not relevant."_doc, + nb::rv_policy::copy) + + .def("section_from_offset", + nb::overload_cast(&Binary::section_from_offset), + "Return the " RST_CLASS_REF(lief.MachO.Section) " which encompasses the offset"_doc, + nb::rv_policy::reference_internal) + + .def("section_from_virtual_address", + nb::overload_cast(&Binary::section_from_virtual_address), + "Return the " RST_CLASS_REF(lief.MachO.Section) " which encompasses the virtual address"_doc, + nb::rv_policy::reference_internal) + + .def("segment_from_offset", + nb::overload_cast(&Binary::segment_from_offset), + "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " which encompasses the offset"_doc, + nb::rv_policy::reference_internal) + + .def("segment_from_virtual_address", + nb::overload_cast(&Binary::segment_from_virtual_address), + "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " which encompasses the virtual address"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_entrypoint", + &Binary::has_entrypoint, + R"delim( + ``True`` if the binary has an entrypoint. + + Basically for libraries it will return ``false`` + )delim"_doc) + + .def_prop_ro("has_uuid", + &Binary::has_uuid, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.UUIDCommand) " command."_doc) + + .def_prop_ro("uuid", + nb::overload_cast<>(&Binary::uuid), + "Return the binary's " RST_CLASS_REF(lief.MachO.UUIDCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_main_command", + &Binary::has_main_command, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.MainCommand) " command."_doc) + + .def_prop_ro("main_command", + nb::overload_cast<>(&Binary::main_command), + "Return the binary's " RST_CLASS_REF(lief.MachO.MainCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dylinker", + &Binary::has_dylinker, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DylinkerCommand) " command."_doc) + + .def_prop_ro("dylinker", + nb::overload_cast<>(&Binary::dylinker), + "Return the binary's " RST_CLASS_REF(lief.MachO.DylinkerCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dyld_info", + &Binary::has_dyld_info, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldInfo) " command."_doc) + + .def_prop_ro("dyld_info", + nb::overload_cast<>(&Binary::dyld_info), + "Return the binary's " RST_CLASS_REF(lief.MachO.DyldInfo) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_function_starts", + &Binary::has_function_starts, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.FunctionStarts) " command."_doc) + + .def_prop_ro("function_starts", + nb::overload_cast<>(&Binary::function_starts), + "Return the binary's " RST_CLASS_REF(lief.MachO.FunctionStarts) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_source_version", + &Binary::has_source_version, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SourceVersion) " command."_doc) + + .def_prop_ro("source_version", + nb::overload_cast<>(&Binary::source_version), + "Return the binary's " RST_CLASS_REF(lief.MachO.SourceVersion) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_version_min", + &Binary::has_version_min, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.VersionMin) " command."_doc) + + .def_prop_ro("version_min", + nb::overload_cast<>(&Binary::version_min), + "Return the binary's " RST_CLASS_REF(lief.MachO.VersionMin) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_routine_command", + &Binary::has_routine_command, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.Routine) " command."_doc) + + .def_prop_ro("routine_command", + nb::overload_cast<>(&Binary::routine_command), + "Return the binary's " RST_CLASS_REF(lief.MachO.Routine) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_thread_command", + &Binary::has_thread_command, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.ThreadCommand) " command."_doc) + + .def_prop_ro("thread_command", + nb::overload_cast<>(&Binary::thread_command), + "Return the binary's " RST_CLASS_REF(lief.MachO.ThreadCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_rpath", + &Binary::has_rpath, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.RPathCommand) " command."_doc) + + .def_prop_ro("rpath", + nb::overload_cast<>(&Binary::rpath), + "Return the binary's " RST_CLASS_REF(lief.MachO.RPathCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("rpaths", + nb::overload_cast<>(&Binary::rpaths), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.RPathCommand) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("has_symbol_command", + &Binary::has_symbol_command, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SymbolCommand) " command."_doc) + + .def_prop_ro("symbol_command", + nb::overload_cast<>(&Binary::symbol_command), + "Return the binary's " RST_CLASS_REF(lief.MachO.SymbolCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dynamic_symbol_command", + &Binary::has_dynamic_symbol_command, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DynamicSymbolCommand) " command."_doc) + + .def_prop_ro("dynamic_symbol_command", + nb::overload_cast<>(&Binary::dynamic_symbol_command), + "Return the binary's " RST_CLASS_REF(lief.MachO.DynamicSymbolCommand) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_code_signature", + &Binary::has_code_signature, + "``True`` if the binary is signed (i.e. has a " RST_CLASS_REF(lief.MachO.CodeSignature) " command)"_doc) + + .def_prop_ro("code_signature", + nb::overload_cast<>(&Binary::code_signature), + "Return the binary's " RST_CLASS_REF(lief.MachO.CodeSignature) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_code_signature_dir", + &Binary::has_code_signature_dir, + "``True`` if the binary is signed (i.e. has a " RST_CLASS_REF(lief.MachO.CodeSignatureDir) " command) " + "with the command LC_DYLIB_CODE_SIGN_DRS"_doc) + + .def_prop_ro("code_signature_dir", + nb::overload_cast<>(&Binary::code_signature_dir), + "Return the binary's " RST_CLASS_REF(lief.MachO.CodeSignatureDir) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_data_in_code", + &Binary::has_data_in_code, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DataInCode) " command"_doc) + + .def_prop_ro("data_in_code", + nb::overload_cast<>(&Binary::data_in_code), + "Return the binary's " RST_CLASS_REF(lief.MachO.DataInCode) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_segment_split_info", + &Binary::has_segment_split_info, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SegmentSplitInfo) " command"_doc) + + .def_prop_ro("segment_split_info", + nb::overload_cast<>(&Binary::segment_split_info), + "Return the binary's " RST_CLASS_REF(lief.MachO.SegmentSplitInfo) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("subclients", + nb::overload_cast<>(&Binary::subclients), + "Return an iterator over the binary's " RST_CLASS_REF(lief.MachO.SubClient) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("has_subclients", + &Binary::has_subclients, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SubClient) " command"_doc) + + .def_prop_ro("has_sub_framework", + &Binary::has_sub_framework, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.SubFramework) " command"_doc) + + .def_prop_ro("sub_framework", + nb::overload_cast<>(&Binary::sub_framework), + "Return the binary's " RST_CLASS_REF(lief.MachO.SubFramework) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dyld_environment", + &Binary::has_dyld_environment, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldEnvironment) " command"_doc) + + .def_prop_ro("dyld_environment", + nb::overload_cast<>(&Binary::dyld_environment), + "Return the binary's " RST_CLASS_REF(lief.MachO.DyldEnvironment) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_encryption_info", + &Binary::has_encryption_info, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.EncryptionInfo) " command"_doc) + + .def_prop_ro("encryption_info", + nb::overload_cast<>(&Binary::encryption_info), + "Return the binary's " RST_CLASS_REF(lief.MachO.EncryptionInfo) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_build_version", + &Binary::has_build_version, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.BuildVersion) " command"_doc) + + .def_prop_ro("platform", + &Binary::platform, + "Return the platform for which this Mach-O has been compiled"_doc) + + .def_prop_ro("is_ios", + &Binary::is_ios, + "True if this binary targets iOS"_doc) + + .def_prop_ro("is_macos", + &Binary::is_macos, + "True if this binary targets macOS"_doc) + + .def_prop_ro("build_version", + nb::overload_cast<>(&Binary::build_version), + "Return the binary's " RST_CLASS_REF(lief.MachO.BuildVersion) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dyld_chained_fixups", + &Binary::has_dyld_chained_fixups, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldChainedFixups) " command"_doc) + + .def_prop_ro("dyld_chained_fixups", + nb::overload_cast<>(&Binary::dyld_chained_fixups), + "Return the binary's " RST_CLASS_REF(lief.MachO.DyldChainedFixups) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dyld_exports_trie", + &Binary::has_dyld_exports_trie, + "``True`` if the binary has a " RST_CLASS_REF(lief.MachO.DyldExportsTrie) " command"_doc) + + .def_prop_ro("dyld_exports_trie", + nb::overload_cast<>(&Binary::dyld_exports_trie), + "Return the binary's " RST_CLASS_REF(lief.MachO.DyldExportsTrie) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_two_level_hints", + &Binary::has_two_level_hints, + "``True`` if the binary embeds the Two Level Hint command (" RST_CLASS_REF(lief.MachO.TwoLevelHints) ")"_doc) + + .def_prop_ro("two_level_hints", + nb::overload_cast<>(&Binary::two_level_hints), + "Return the binary's " RST_CLASS_REF(lief.MachO.TwoLevelHints) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_linker_opt_hint", + &Binary::has_linker_opt_hint, + "``True`` if the binary embeds the Linker optimization hint command (" RST_CLASS_REF(lief.MachO.LinkerOptHint) ")"_doc) + + .def_prop_ro("linker_opt_hint", + nb::overload_cast<>(&Binary::linker_opt_hint), + "Return the binary's " RST_CLASS_REF(lief.MachO.LinkerOptHint) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_atom_info", + &Binary::has_atom_info, + "``True`` if the binary embeds the ``LC_ATOM_INFO`` command (" RST_CLASS_REF(lief.MachO.AtomInfo) ")"_doc) + + .def_prop_ro("atom_info", + nb::overload_cast<>(&Binary::atom_info), + "Return the binary's " RST_CLASS_REF(lief.MachO.AtomInfo) " if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_function_variants", + &Binary::has_function_variants, + "``True`` if the binary has a ``LC_FUNCTION_VARIANTS`` command"_doc) + + .def_prop_ro("function_variants", + nb::overload_cast<>(&Binary::function_variants), + "Return ``LC_FUNCTION_VARIANTS`` command"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_function_variant_fixups", + &Binary::has_function_variant_fixups, + "``True`` if the binary has a ``LC_FUNCTION_VARIANT_FIXUPS`` command"_doc) + + .def_prop_ro("function_variant_fixups", + nb::overload_cast<>(&Binary::function_variant_fixups), + "Return ``LC_FUNCTION_VARIANT_FIXUPS`` command"_doc, + nb::rv_policy::reference_internal) + + .def("virtual_address_to_offset", + [] (const Binary& self, uint64_t va) { + return error_or(&Binary::virtual_address_to_offset, self, va); + }, + "Convert the virtual address to an offset in the binary"_doc, + "virtual_address"_a) + + .def("has_section", + &Binary::has_section, + "Check if a section with the given name exists"_doc, + "name"_a) + + .def("get_section", + nb::overload_cast(&Binary::get_section), + "Return the section from the given name or None if the section does not exist"_doc, + "name"_a, + nb::rv_policy::reference_internal) + + .def("has_segment", + &Binary::has_segment, + "Check if a " RST_CLASS_REF(lief.MachO.SegmentCommand) " with the given name exists"_doc, + "name"_a) + + .def("get_segment", + nb::overload_cast(&Binary::get_segment), + "Return the " RST_CLASS_REF(lief.MachO.SegmentCommand) " from the given name"_doc, + "name"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("va_ranges", + &Binary::va_ranges, + "Return the range of virtual addresses as a tuple ``(va_start, va_end)``"_doc) + + .def_prop_ro("off_ranges", + &Binary::off_ranges, + "Return the range of offsets as a tuple ``(off_start, off_end)``"_doc) + + .def_prop_ro("tlv_initial_content_range", + &Binary::tlv_initial_content_range, + "Return the TLV initial content range"_doc) + + .def("is_valid_addr", + &Binary::is_valid_addr, + R"delim( + Check if the given address is encompassed between the range of virtual addresses. + + See: :attr:`~lief.MachO.Binary.va_ranges` + )delim"_doc, + "address"_a) + + .def("write", + [] (Binary& self, nb::PathLike path) { return self.write(path); }, + "Rebuild the binary and write its content in the file given in the first parameter"_doc, + "output"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("write", + [] (Binary& self, nb::PathLike path, const Builder::config_t& config) { + return self.write(path, config); + }, + R"doc( + Rebuild the binary and write its content in the file given in the first parameter. + The ``config`` parameter can be used to tweak the building process. + )doc"_doc, + "output"_a, "config"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("write_to_bytes", [] (Binary& bin, const Builder::config_t& config) -> nb::bytes { + std::ostringstream out; + bin.write(out, config); + return nb::to_bytes(out.str()); + }, "config"_a, nb::lock_self()) + + .def("write_to_bytes", [] (Binary& bin) -> nb::bytes { + std::ostringstream out; + bin.write(out); + return nb::to_bytes(out.str()); + }, nb::lock_self()) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.MachO.DylibCommand) ""_doc, + "dylib_command"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.MachO.SegmentCommand) ""_doc, + "segment"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.MachO.LoadCommand) ""_doc, + "load_command"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add", + nb::overload_cast(&Binary::add), + "Add a new " RST_CLASS_REF(lief.MachO.LoadCommand) " at ``index``"_doc, + "load_command"_a, "index"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove a " RST_CLASS_REF(lief.MachO.LoadCommand) ""_doc, + "load_command"_a, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove **all** the " RST_CLASS_REF(lief.MachO.LoadCommand) " with the given " + "" RST_CLASS_REF(lief.MachO.LoadCommand.TYPE) ""_doc, + "type"_a, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove the given " RST_CLASS_REF(lief.MachO.Symbol)""_doc, + "symbol"_a, nb::lock_self()) + + .def("remove_command", + nb::overload_cast(&Binary::remove_command), + "Remove the " RST_CLASS_REF(lief.MachO.LoadCommand) " at the given ``index``"_doc, + "index"_a, nb::lock_self()) + + .def("remove_section", + nb::overload_cast(&Binary::remove_section), + "Remove the section with the given name"_doc, + "name"_a, "clear"_a = false, nb::lock_self()) + + .def("remove_section", + nb::overload_cast(&Binary::remove_section), + R"delim( + Remove the section from the segment with the name + given in the first parameter and with the section's name provided in the + second parameter.)delim"_doc, + "segname"_a, "secname"_a, "clear"_a = false, nb::lock_self()) + + .def("remove_signature", + nb::overload_cast<>(&Binary::remove_signature), + "Remove the " RST_CLASS_REF(lief.MachO.CodeSignature) " (if any)"_doc, + nb::lock_self()) + + .def("remove_symbol", + nb::overload_cast(&Binary::remove_symbol), + "Remove all symbol(s) with the given name"_doc, + "name"_a, nb::lock_self()) + + .def("can_remove", + nb::overload_cast(&Binary::can_remove, nb::const_), + "Check if the given symbol can be safely removed."_doc, + "symbol"_a) + + .def("can_remove_symbol", + nb::overload_cast(&Binary::can_remove_symbol, nb::const_), + "Check if the given symbol name can be safely removed."_doc, + "symbol_name"_a) + + .def("unexport", + nb::overload_cast(&Binary::unexport), + "Remove the symbol from the export table"_doc, + "name"_a, nb::lock_self()) + + .def("unexport", + nb::overload_cast(&Binary::unexport), + "Remove the symbol from the export table"_doc, + "symbol"_a, nb::lock_self()) + + .def("extend", + nb::overload_cast(&Binary::extend), + "Extend a " RST_CLASS_REF(lief.MachO.LoadCommand) " by ``size``"_doc, + "load_command"_a, "size"_a, nb::lock_self()) + + .def("extend_segment", + nb::overload_cast(&Binary::extend_segment), + "Extend the **content** of the given " RST_CLASS_REF(lief.MachO.SegmentCommand) " by ``size``"_doc, + "segment_command"_a, "size"_a, nb::lock_self()) + + .def("add_section", + nb::overload_cast(&Binary::add_section), + "Add a new " RST_CLASS_REF(lief.MachO.Section) " in the given " RST_CLASS_REF(lief.MachO.SegmentCommand) ""_doc, + "segment"_a, "section"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add_section", + nb::overload_cast(&Binary::add_section), + "Add a new " RST_CLASS_REF(lief.MachO.Section) " within the ``__TEXT`` segment"_doc, + "section"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("find_library", nb::overload_cast(&Binary::find_library), + R"doc( + Try to find the library with the given library name. + + This function tries to match the fullpath of the :class:`~.DylibCommand` or the + library name suffix. + )doc"_doc, "name"_a, nb::rv_policy::reference_internal) + + .def("extend_section", + nb::overload_cast(&Binary::extend_section), + "Extend the **content** of the given " RST_CLASS_REF(lief.MachO.Section) " by ``size``"_doc, + "section"_a, "size"_a, nb::lock_self()) + + .def("add_library", + nb::overload_cast(&Binary::add_library), + "Add a new library dependency"_doc, + "library_name"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("get", + nb::overload_cast(&Binary::get), + "Return the **first** " RST_CLASS_REF(lief.MachO.LoadCommand) " with the given " + "" RST_CLASS_REF(lief.MachO.LoadCommand.TYPE) " or None if it is not present."_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def("has", + nb::overload_cast(&Binary::has, nb::const_), + "Check if the current binary has a " RST_CLASS_REF(lief.MachO.LoadCommand) " with the given " + "" RST_CLASS_REF(lief.MachO.LoadCommand.TYPE) ""_doc, + "type"_a) + + .def_prop_ro("unwind_functions", + &Binary::unwind_functions, + "Return list of " RST_CLASS_REF(lief.Function) " found in the ``__unwind_info`` section"_doc) + + .def_prop_ro("functions", + &Binary::functions, + "Return list of **all** " RST_CLASS_REF(lief.Function) " found"_doc) + + .def("get_section", + nb::overload_cast(&Binary::get_section), + R"delim( + Return the section from the segment with the name + given in the first parameter and with the section's name provided in the + second parameter. If the section cannot be found, it returns a nullptr + )delim"_doc, + "segname"_a, "secname"_a, + nb::rv_policy::reference_internal) + + .def("shift", + [] (Binary& self, size_t width) { + return error_or(&Binary::shift, self, width); + }, + R"delim( + Shift the content located right after the Load commands table. + This operation can be used to add a new command + )delim"_doc, + "value"_a, nb::lock_self()) + + .def("shift_linkedit", + [] (Binary& self, size_t width) { + return error_or(&Binary::shift_linkedit, self, width); + }, + "Shift the position on the __LINKEDIT data by `width`"_doc, + "value"_a, nb::lock_self()) + + .def("add_exported_function", + &Binary::add_exported_function, + "Add a new export in the binary"_doc, + "address"_a, "name"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("add_local_symbol", + &Binary::add_local_symbol, + "Add a new symbol in the LC_SYMTAB"_doc, + "address"_a, "name"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def_prop_ro("bindings", + [] (const Binary& self) { + auto bindings = self.bindings(); + return nb::make_iterator( + nb::type(), "bindings_it", bindings + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the binding info which can come from either + :class:`~.DyldInfo` or :class:`~.DyldChainedFixups` commands. + )doc"_doc + ) + + .def_prop_ro("symbol_stubs", + [] (const Binary& self) { + auto stubs = self.symbol_stubs(); + return nb::make_random_access_iterator(nb::type(), "stub_iterator", stubs); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the symbol stubs. + + These stubs are involved when calling an **imported** function and are + similar to the ELF's plt/got mechanism. + + There are located in sections like: ``__stubs,__auth_stubs,__symbol_stub,__picsymbolstub4`` + )doc"_doc + ) + + .def_prop_ro("has_nx_heap", &Binary::has_nx_heap, + R"doc( + Return True if the **heap** is flagged as non-executable. False + otherwise. + )doc"_doc) + + .def_prop_ro("has_nx_stack", &Binary::has_nx_stack, + R"doc( + Return True if the **stack** is flagged as non-executable. False + otherwise. + )doc"_doc) + + .def_prop_ro("support_arm64_ptr_auth", &Binary::support_arm64_ptr_auth, + R"doc( + Check if the binary is supporting ARM64 pointer authentication (arm64e) + )doc" + ) + + .def_prop_ro("objc_metadata", &Binary::objc_metadata, + R"doc( + Return Objective-C metadata info if present + + .. warning:: + + This is only available with the extended version of LIEF. + )doc"_doc + ) + + .def_prop_ro("notes", + nb::overload_cast<>(&Binary::notes), + "Iterator over the different ``LC_NOTE`` commands"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("has_notes", &Binary::has_notes, + "True if the binary contains ``LC_NOTE`` command(s)") + + .def("__getitem__", + nb::overload_cast(&Binary::operator[]), + nb::rv_policy::reference_internal) + + .def("__contains__", + nb::overload_cast(&Binary::has, nb::const_)) + + .def_prop_ro("overlay", + nb::overload_cast<>(&Binary::overlay, nb::const_)) + + .def_prop_ro("available_command_space", &Binary::available_command_space) + + LIEF_DEFAULT_STR(Binary); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyBindingInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyBindingInfo.cpp new file mode 100644 index 0000000..3f087a4 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyBindingInfo.cpp @@ -0,0 +1,93 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/BindingInfo.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/MachO/DylibCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "BindingInfo", + R"delim( + Class that provides an interface over an entry in DyldInfo structure + + This class does not represent a structure that exists in the Mach-O format + specifications but it provides a *view* of a binding operation that is performed + by the Dyld binding bytecode (``LC_DYLD_INFO``) or the Dyld chained fixups (``DYLD_CHAINED_FIXUPS``) + + See: :class:`~lief.MachO.ChainedBindingInfo`, :class:`~lief.MachO.DyldBindingInfo` + )delim"_doc) + + + .def_prop_rw("address", + nb::overload_cast<>(&BindingInfo::address, nb::const_), + nb::overload_cast(&BindingInfo::address), + "Binding's address"_doc) + + .def_prop_rw("library_ordinal", + nb::overload_cast<>(&BindingInfo::library_ordinal, nb::const_), + nb::overload_cast(&BindingInfo::library_ordinal)) + + .def_prop_rw("addend", + nb::overload_cast<>(&BindingInfo::addend, nb::const_), + nb::overload_cast(&BindingInfo::addend), + "Value added to the segment's virtual address when binding"_doc) + + .def_prop_rw("weak_import", + nb::overload_cast<>(&BindingInfo::is_weak_import, nb::const_), + nb::overload_cast(&BindingInfo::set_weak_import)) + + .def_prop_ro("has_library", + &BindingInfo::has_library, + "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.DylibCommand) " associated with"_doc) + + .def_prop_ro("library", + nb::overload_cast<>(&BindingInfo::library), + "" RST_CLASS_REF(lief.MachO.DylibCommand) " associated with the binding if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_segment", + &BindingInfo::has_segment, + "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with"_doc) + + .def_prop_ro("segment", + nb::overload_cast<>(&BindingInfo::segment), + "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the binding if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_symbol", + &BindingInfo::has_symbol, + "``True`` if the binding info has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with"_doc) + + .def_prop_ro("symbol", + nb::overload_cast<>(&BindingInfo::symbol), + "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the binding if any, or None"_doc, + nb::rv_policy::reference_internal) + + + LIEF_DEFAULT_STR(BindingInfo); + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyBuildVersion.cpp b/vendor/lief/api/python/src/MachO/objects/pyBuildVersion.cpp new file mode 100644 index 0000000..1f4ade7 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyBuildVersion.cpp @@ -0,0 +1,127 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include +#include +#include + +#include "LIEF/MachO/BuildVersion.hpp" +#include "LIEF/MachO/EnumToString.hpp" + +#include "enums_wrapper.hpp" + +#include "MachO/pyMachO.hpp" + +#define PY_ENUM(x) LIEF::MachO::to_string(x), x + +namespace LIEF::MachO::py { +template<> +void create(nb::module_& m) { + + nb::class_ cls(m, "BuildVersion"); + nb::class_ tool_version_cls(m, "BuildToolVersion", + R"delim( + Class that represents a tool's version that was involved in the build + of the binary + )delim"_doc); + + // Build Tool Version + // ================== + tool_version_cls + .def_prop_ro("tool", + &BuildToolVersion::tool, + "" RST_CLASS_REF(.BuildVersion.TOOLS) " type"_doc) + + .def_prop_ro("version", + &BuildToolVersion::version, + "Version of the tool"_doc) + + LIEF_DEFAULT_STR(BuildToolVersion); + + LIEF::enum_(tool_version_cls, "TOOLS") + .value(PY_ENUM(BuildToolVersion::TOOLS::UNKNOWN)) + .value(PY_ENUM(BuildToolVersion::TOOLS::CLANG)) + .value(PY_ENUM(BuildToolVersion::TOOLS::SWIFT)) + .value(PY_ENUM(BuildToolVersion::TOOLS::LD)) + .value(PY_ENUM(BuildToolVersion::TOOLS::LLD)) + + .value(PY_ENUM(BuildToolVersion::TOOLS::METAL)) + .value(PY_ENUM(BuildToolVersion::TOOLS::AIRLLD)) + .value(PY_ENUM(BuildToolVersion::TOOLS::AIRNT)) + .value(PY_ENUM(BuildToolVersion::TOOLS::AIRNT_PLUGIN)) + .value(PY_ENUM(BuildToolVersion::TOOLS::AIRPACK)) + .value(PY_ENUM(BuildToolVersion::TOOLS::GPUARCHIVER)) + .value(PY_ENUM(BuildToolVersion::TOOLS::METAL_FRAMEWORK)) + ; + + + enum_(cls, "PLATFORMS") + .value(PY_ENUM(BuildVersion::PLATFORMS::UNKNOWN)) + .value(PY_ENUM(BuildVersion::PLATFORMS::MACOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::IOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::TVOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::WATCHOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::BRIDGEOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::MAC_CATALYST)) + .value(PY_ENUM(BuildVersion::PLATFORMS::IOS_SIMULATOR)) + .value(PY_ENUM(BuildVersion::PLATFORMS::TVOS_SIMULATOR)) + .value(PY_ENUM(BuildVersion::PLATFORMS::WATCHOS_SIMULATOR)) + .value(PY_ENUM(BuildVersion::PLATFORMS::DRIVERKIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::VISIONOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::VISIONOS_SIMULATOR)) + .value(PY_ENUM(BuildVersion::PLATFORMS::FIRMWARE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::SEPOS)) + .value(PY_ENUM(BuildVersion::PLATFORMS::MACOS_EXCLAVE_CORE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::MACOS_EXCLAVE_KIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::IOS_EXCLAVE_CORE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::IOS_EXCLAVE_KIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::TVOS_EXCLAVE_CORE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::TVOS_EXCLAVE_KIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::WATCHOS_EXCLAVE_CORE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::WATCHOS_EXCLAVE_KIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::VISIONOS_EXCLAVE_CORE)) + .value(PY_ENUM(BuildVersion::PLATFORMS::VISIONOS_EXCLAVE_KIT)) + .value(PY_ENUM(BuildVersion::PLATFORMS::ANY)) + ; + + cls + .def_prop_rw("platform", + nb::overload_cast<>(&BuildVersion::platform, nb::const_), + nb::overload_cast(&BuildVersion::platform), + "Target " RST_CLASS_REF(.BuildVersion.PLATFORMS) ""_doc) + + .def_prop_rw("minos", + nb::overload_cast<>(&BuildVersion::minos, nb::const_), + nb::overload_cast(&BuildVersion::minos), + "Minimal OS version on which this binary was built to run"_doc) + + .def_prop_rw("sdk", + nb::overload_cast<>(&BuildVersion::sdk, nb::const_), + nb::overload_cast(&BuildVersion::sdk), + "SDK Version"_doc) + + .def_prop_ro("tools", + nb::overload_cast<>(&BuildVersion::tools, nb::const_), + "List of " RST_CLASS_REF(BuildToolVersion) " used while building this binary"_doc) + + LIEF_DEFAULT_STR(BuildVersion); + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyBuilder.cpp b/vendor/lief/api/python/src/MachO/objects/pyBuilder.cpp new file mode 100644 index 0000000..598205c --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyBuilder.cpp @@ -0,0 +1,76 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "MachO/pyMachO.hpp" +#include "pyErr.hpp" + +#include "LIEF/MachO/Binary.hpp" +#include "LIEF/MachO/FatBinary.hpp" +#include "LIEF/MachO/Builder.hpp" + +#include + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ builder(m, "Builder", + R"delim( + Class used to reconstruct a Mach-O binary from its object representation + )delim"_doc); + + nb::class_(builder, "config_t", + "Interface to tweak the " RST_CLASS_REF(lief.MachO.Builder) ""_doc) + .def(nb::init<>()) + .def_rw("linkedit", &Builder::config_t::linkedit); + + builder + .def_static("write", + [] (Binary& bin, const std::string& out) { + auto target = nb::overload_cast(&Builder::write); + return error_or(target, bin, out); + }, + R"delim( + )delim", + "binary"_a.lock(), "output"_a) + .def_static("write", + [] (Binary& bin, const std::string& out, Builder::config_t config) { + auto target = nb::overload_cast(&Builder::write); + return error_or(target, bin, out, config); + }, + R"delim( + )delim", + "binary"_a.lock(), "output"_a, "config"_a) + .def_static("write", + [] (FatBinary& fat, const std::string& out) { + auto target = nb::overload_cast(&Builder::write); + return error_or(target, fat, out); + }, + R"delim( + )delim", + "fat_binary"_a.lock(), "output"_a) + .def_static("write", + [] (FatBinary& fat, const std::string& out, Builder::config_t config) { + auto target = nb::overload_cast(&Builder::write); + return error_or(target, fat, out, config); + }, + R"delim( + )delim", + "fat_binary"_a.lock(), "output"_a, "config"_a); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyChainedBindingInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyChainedBindingInfo.cpp new file mode 100644 index 0000000..80a1da7 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyChainedBindingInfo.cpp @@ -0,0 +1,59 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include + +#include "LIEF/MachO/ChainedBindingInfo.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ChainedBindingInfo", + R"delim( + This class represents a symbol binding operation associated with + the LC_DYLD_CHAINED_FIXUPS command. + + This class does not represent a structure that exists in the Mach-O format + specifications but it provides a *view* on an entry. + + See also: :class:`~lief.MachO.BindingInfo` + )delim"_doc) + + .def_prop_ro("format", &ChainedBindingInfo::format, + R"delim(:class:`~lief.MachO.DYLD_CHAINED_FORMAT` of the import)delim"_doc) + + .def_prop_ro("ptr_format", &ChainedBindingInfo::ptr_format, + R"delim(:class:`~lief.MachO.DYLD_CHAINED_PTR_FORMAT` of the import)delim"_doc) + + .def_prop_rw("offset", + nb::overload_cast<>(&ChainedBindingInfo::offset, nb::const_), + nb::overload_cast(&ChainedBindingInfo::offset), + R"delim(Offset of the entry in the chained fixups)delim"_doc) + + .def_prop_ro("sign_extended_addend", + &ChainedBindingInfo::sign_extended_addend) + + LIEF_DEFAULT_STR(ChainedBindingInfo); + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyChainedPointerAnalysis.cpp b/vendor/lief/api/python/src/MachO/objects/pyChainedPointerAnalysis.cpp new file mode 100644 index 0000000..a32c206 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyChainedPointerAnalysis.cpp @@ -0,0 +1,603 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include +#include +#include +#include + +#include "LIEF/MachO/ChainedPointerAnalysis.hpp" + +#include "MachO/pyMachO.hpp" +#include "typing.hpp" + +namespace LIEF::MachO::py { + +struct ChainedPointer : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(ChainedPointer, nanobind::object); + + NB_OBJECT_DEFAULT(ChainedPointer, object, + "Union[" + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_bind24_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_bind24_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_bind_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_64_kernel_cache_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_bind_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_cache_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_32_firmware_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_segmented_rebase_t, " + "lief.MachO.ChainedPointerAnalysis.dyld_chained_ptr_arm64e_auth_segmented_rebase_t, " + "int, " + "None" + "]", + check) + + static bool check(handle) { + return true; + } +}; + +template<> +void create(nb::module_& m) { + nb::class_ clazz(m, "ChainedPointerAnalysis"); + nb::class_( + clazz, "dyld_chained_ptr_arm64e_rebase_t" + ) + .def_prop_ro("unpack_target", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t::unpack_target) + + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("high8", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t& ptr) { + return (uint64_t)ptr.high8; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t& ptr) { + return (bool)ptr.auth; + } + ) + + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_bind_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("zero", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (uint64_t)ptr.zero; + } + ) + .def_prop_ro("addend", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (uint64_t)ptr.addend; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_auth_rebase_t" + ) + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("diversity", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.diversity; + } + ) + .def_prop_ro("addr_div", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.addr_div; + } + ) + .def_prop_ro("key", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.key; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t& ptr) { + return (uint64_t)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_auth_bind_t") + + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("zero", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.zero; + } + ) + .def_prop_ro("diversity", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.diversity; + } + ) + .def_prop_ro("addr_div", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.addr_div; + } + ) + .def_prop_ro("key", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.key; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_64_rebase_t" + ) + + .def_prop_ro("unpack_target", + &ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t::unpack_target) + + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("high8", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t& ptr) { + return (uint64_t)ptr.high8; + } + ) + .def_prop_ro("reserved", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t& ptr) { + return (uint64_t)ptr.reserved; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t& ptr) { + return (bool)ptr.bind; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_64_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_bind24_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("zero", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (uint64_t)ptr.zero; + } + ) + .def_prop_ro("addend", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (uint64_t)ptr.addend; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_auth_bind24_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("zero", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.zero; + } + ) + .def_prop_ro("diversity", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.diversity; + } + ) + .def_prop_ro("addr_div", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.addr_div; + } + ) + .def_prop_ro("key", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.key; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (bool)ptr.bind; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_64_bind_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("addend", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t& ptr) { + return (uint64_t)ptr.addend; + } + ) + .def_prop_ro("reserved", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t& ptr) { + return (uint64_t)ptr.reserved; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t& ptr) { + return (bool)ptr.bind; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_64_bind_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_64_kernel_cache_rebase_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("cache_level", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.cache_level; + } + ) + .def_prop_ro("diversity", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.diversity; + } + ) + .def_prop_ro("addr_div", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.addr_div; + } + ) + .def_prop_ro("key", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.key; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("is_auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t& ptr) { + return (bool)ptr.is_auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_32_rebase_t" + ) + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_rebase_t& ptr) { + return (uint64_t)ptr.bind; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_32_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_32_bind_t" + ) + .def_prop_ro("ordinal", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_bind_t& ptr) { + return (uint64_t)ptr.ordinal; + } + ) + .def_prop_ro("addend", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_bind_t& ptr) { + return (uint64_t)ptr.addend; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_bind_t& ptr) { + return (uint64_t)ptr.next; + } + ) + .def_prop_ro("bind", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_bind_t& ptr) { + return (bool)ptr.bind; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_32_bind_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_32_cache_rebase_t" + ) + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_cache_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_cache_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_32_cache_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_32_firmware_rebase_t" + ) + .def_prop_ro("target", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_firmware_rebase_t& ptr) { + return (uint64_t)ptr.target; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_32_firmware_rebase_t& ptr) { + return (uint64_t)ptr.next; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_32_firmware_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_segmented_rebase_t" + ) + .def_prop_ro("target_seg_offset", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t& ptr) { + return (uint32_t)ptr.target_seg_offset; + } + ) + .def_prop_ro("target_seg_index", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t& ptr) { + return (uint32_t)ptr.target_seg_index; + } + ) + .def_prop_ro("padding", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t& ptr) { + return (uint32_t)ptr.padding; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t& ptr) { + return (uint32_t)ptr.next; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t); + ; + nb::class_( + clazz, "dyld_chained_ptr_arm64e_auth_segmented_rebase_t" + ) + .def_prop_ro("target_seg_offset", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.target_seg_offset; + } + ) + .def_prop_ro("target_seg_index", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.target_seg_index; + } + ) + .def_prop_ro("diversity", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.diversity; + } + ) + .def_prop_ro("addr_div", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.addr_div; + } + ) + .def_prop_ro("key", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.key; + } + ) + .def_prop_ro("next", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (uint32_t)ptr.next; + } + ) + .def_prop_ro("auth", + [] (const ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase_t& ptr) { + return (bool)ptr.auth; + } + ) + LIEF_DEFAULT_STR(ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase_t); + ; + clazz + .def_static("stride", + &ChainedPointerAnalysis::stride, "fmt"_a) + .def_static("from_value", + &ChainedPointerAnalysis::from_value, "ptr"_a, "size"_a) + .def_prop_ro("value", + &ChainedPointerAnalysis::value) + .def_prop_ro("size", + &ChainedPointerAnalysis::size) + .def_prop_ro("dyld_chained_ptr_arm64e_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_rebase) + .def_prop_ro("dyld_chained_ptr_arm64e_bind", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind) + .def_prop_ro("dyld_chained_ptr_arm64e_auth_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_rebase) + .def_prop_ro("dyld_chained_ptr_arm64e_auth_bind", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind) + .def_prop_ro("dyld_chained_ptr_64_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_64_rebase) + .def_prop_ro("dyld_chained_ptr_arm64e_bind24", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_bind24) + .def_prop_ro("dyld_chained_ptr_arm64e_auth_bind24", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_bind24) + .def_prop_ro("dyld_chained_ptr_64_bind", + &ChainedPointerAnalysis::dyld_chained_ptr_64_bind) + .def_prop_ro("dyld_chained_ptr_64_kernel_cache_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_64_kernel_cache_rebase) + .def_prop_ro("dyld_chained_ptr_32_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_32_rebase) + .def_prop_ro("dyld_chained_ptr_32_bind", + &ChainedPointerAnalysis::dyld_chained_ptr_32_bind) + .def_prop_ro("dyld_chained_ptr_32_cache_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_32_cache_rebase) + .def_prop_ro("dyld_chained_ptr_32_firmware_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_32_firmware_rebase) + .def_prop_ro("dyld_chained_ptr_arm64e_segmented_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_segmented_rebase) + .def_prop_ro("dyld_chained_ptr_arm64e_auth_segmented_rebase", + &ChainedPointerAnalysis::dyld_chained_ptr_arm64e_auth_segmented_rebase) + .def("get_as", + [] (const ChainedPointerAnalysis& self, DYLD_CHAINED_PTR_FORMAT fmt) -> ChainedPointer { + ChainedPointerAnalysis::union_pointer_t ptr = self.get_as(fmt); + return std::visit([&ptr] (const auto& value) -> ChainedPointer { + using T = std::decay_t; + if constexpr (std::is_same_v) { + return nb::cast(ptr.raw); + } else { + return nb::cast(value); + } + }, ptr.content); + } + ) + ; + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyCodeSignature.cpp b/vendor/lief/api/python/src/MachO/objects/pyCodeSignature.cpp new file mode 100644 index 0000000..9fe5416 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyCodeSignature.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include + +#include "LIEF/MachO/CodeSignature.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "CodeSignature") + .def_prop_rw("data_offset", + nb::overload_cast<>(&CodeSignature::data_offset, nb::const_), + nb::overload_cast(&CodeSignature::data_offset), + "Offset in the binary where the signature starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&CodeSignature::data_size, nb::const_), + nb::overload_cast(&CodeSignature::data_size), + "Size of the raw signature"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&CodeSignature::content, nb::const_), + "The raw signature as a bytes stream"_doc) + + LIEF_DEFAULT_STR(CodeSignature); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyCodeSignatureDir.cpp b/vendor/lief/api/python/src/MachO/objects/pyCodeSignatureDir.cpp new file mode 100644 index 0000000..1e13283 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyCodeSignatureDir.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include + +#include "LIEF/MachO/hash.hpp" +#include "LIEF/MachO/CodeSignatureDir.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/stl/string.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "CodeSignatureDir") + .def_prop_rw("data_offset", + nb::overload_cast<>(&CodeSignatureDir::data_offset, nb::const_), + nb::overload_cast(&CodeSignatureDir::data_offset), + "Offset in the binary where the signature starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&CodeSignatureDir::data_offset, nb::const_), + nb::overload_cast(&CodeSignatureDir::data_offset), + "Size of the raw signature"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&CodeSignatureDir::content, nb::const_), + "The raw signature as a bytes stream"_doc) + + LIEF_DEFAULT_STR(CodeSignatureDir); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDataCodeEntry.cpp b/vendor/lief/api/python/src/MachO/objects/pyDataCodeEntry.cpp new file mode 100644 index 0000000..5cfc147 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDataCodeEntry.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include + +#include "LIEF/MachO/DataCodeEntry.hpp" +#include "LIEF/MachO/EnumToString.hpp" + +#include "enums_wrapper.hpp" + +#include "MachO/pyMachO.hpp" + +#define PY_ENUM(x) LIEF::MachO::to_string(x), x + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "DataCodeEntry", + R"delim( + Interface over an entry in the :class:`~lief.MachO.DataInCode` command + )delim"_doc); + + enum_(cls, "TYPES") + .value(PY_ENUM(DataCodeEntry::TYPES::UNKNOWN)) + .value(PY_ENUM(DataCodeEntry::TYPES::DATA)) + .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_8)) + .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_16)) + .value(PY_ENUM(DataCodeEntry::TYPES::JUMP_TABLE_32)) + .value(PY_ENUM(DataCodeEntry::TYPES::ABS_JUMP_TABLE_32)); + + cls + // TODO(romain): + //.def(nb::init()) + .def_prop_rw("offset", + nb::overload_cast<>(&DataCodeEntry::offset, nb::const_), + nb::overload_cast(&DataCodeEntry::offset), + "Offset of the data"_doc) + + .def_prop_rw("length", + nb::overload_cast<>(&DataCodeEntry::length, nb::const_), + nb::overload_cast(&DataCodeEntry::length), + "Length of the data"_doc) + + .def_prop_rw("type", + nb::overload_cast<>(&DataCodeEntry::type, nb::const_), + nb::overload_cast(&DataCodeEntry::type), + "Type of the data (" RST_CLASS_REF(lief.MachO.DataCodeEntry.TYPES) ""_doc) + + LIEF_DEFAULT_STR(DataCodeEntry); + + + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDataInCode.cpp b/vendor/lief/api/python/src/MachO/objects/pyDataInCode.cpp new file mode 100644 index 0000000..576ef87 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDataInCode.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include + +#include "LIEF/MachO/DataInCode.hpp" + +#include "pyIterator.hpp" +#include "MachO/pyMachO.hpp" + +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + init_ref_iterator(m, "it_data_in_code_entries"); + + nb::class_(m, "DataInCode", + R"delim( + Interface of the LC_DATA_IN_CODE command + + This command is used to list slices of code sections that contain data. The *slices* + information are stored as an array of :class:`~lief.MachO.DataCodeEntry` + )delim"_doc) + + .def_prop_rw("data_offset", + nb::overload_cast<>(&DataInCode::data_offset, nb::const_), + nb::overload_cast(&DataInCode::data_offset), + "Start of the array of the DataCodeEntry entries"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&DataInCode::data_size, nb::const_), + nb::overload_cast(&DataInCode::data_size), + "Whole size of the array (``size = sizeof(DataCodeEntry) * nb_elements``)"_doc) + + .def_prop_ro("entries", + nb::overload_cast<>(&DataInCode::entries), + "Iterator over " RST_CLASS_REF(lief.MachO.DataCodeEntry) ""_doc, + nb::rv_policy::reference_internal) + + .def("add", &DataInCode::add, + "Add a new " RST_CLASS_REF(lief.MachO.DataCodeEntry) ""_doc, + "entry"_a) + + .def_prop_ro("content", + nb::overload_cast<>(&DataInCode::content, nb::const_), + "The original content as a bytes stream"_doc) + + LIEF_DEFAULT_STR(DataInCode); + + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDyldBindingInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyDyldBindingInfo.cpp new file mode 100644 index 0000000..6a1b276 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDyldBindingInfo.cpp @@ -0,0 +1,81 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/DyldBindingInfo.hpp" +#include "enums_wrapper.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "DyldBindingInfo", + R"delim( + This class represents a symbol binding operation associated with + the LC_DYLD_INFO bytecode. + + This class does not represent a structure that exists in the Mach-O format + specifications but it provides a *view* on an entry of the Dyld binding opcodes. + + See also: :class:`~lief.MachO.BindingInfo` + )delim"_doc); + + + enum_(cls, "CLASS") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(DyldBindingInfo::CLASS::WEAK)) + .value(PY_ENUM(DyldBindingInfo::CLASS::LAZY)) + .value(PY_ENUM(DyldBindingInfo::CLASS::STANDARD)) + .value(PY_ENUM(DyldBindingInfo::CLASS::THREADED)) + #undef PY_ENUM + ; + + enum_(cls, "TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(DyldBindingInfo::TYPE::POINTER)) + .value(PY_ENUM(DyldBindingInfo::TYPE::TEXT_ABSOLUTE32)) + .value(PY_ENUM(DyldBindingInfo::TYPE::TEXT_PCREL32)) + #undef PY_ENUM + ; + + cls + .def_prop_rw("binding_class", + nb::overload_cast<>(&DyldBindingInfo::binding_class, nb::const_), + nb::overload_cast(&DyldBindingInfo::binding_class), + "" RST_CLASS_REF(lief.MachO.BINDING_CLASS) " of the binding"_doc) + + .def_prop_rw("binding_type", + nb::overload_cast<>(&DyldBindingInfo::binding_type, nb::const_), + nb::overload_cast(&DyldBindingInfo::binding_type), + R"delim( + :class:`~lief.MachO.BIND_TYPES` of the binding. + + Usually, it is :attr:`~lief.MachO.BIND_TYPES.POINTER`. + )delim"_doc) + + + .def_prop_ro("original_offset", &DyldBindingInfo::original_offset, + "Original relative offset of the binding opcodes"_doc) + + LIEF_DEFAULT_STR(DyldBindingInfo); + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDyldChainedFixups.cpp b/vendor/lief/api/python/src/MachO/objects/pyDyldChainedFixups.cpp new file mode 100644 index 0000000..71fcea6 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDyldChainedFixups.cpp @@ -0,0 +1,166 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "nanobind/extra/stl/lief_span.h" + +#include "pyIterator.hpp" +#include "LIEF/MachO/DyldChainedFixups.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" +#include "LIEF/MachO/ChainedBindingInfo.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ chained(m, "DyldChainedFixups", + R"delim( + Class that represents the LC_DYLD_CHAINED_FIXUPS command + + This command aims at providing rebase and binding information like + the :class:`~lief.MachO.DyldInfo` 's bytecode. Compared to the :class:`~lief.MachO.DyldInfo` bytecode, + these chained fixups are taking less space. + )delim"_doc); + + init_ref_iterator(chained, "it_binding_info"); + init_ref_iterator(chained, "it_chained_starts_in_segments_t"); + + nb::class_(chained, "chained_starts_in_segment", + R"delim( + Structure that mirrors the raw dyld_chained_starts_in_segment + which aims at providing information about the chained rebase/bind fixups + + The relocations provided by this structure can be accessed through :attr:`~lief.MachO.SegmentCommand.relocations` + )delim"_doc) + .def_ro("offset", &DyldChainedFixups::chained_starts_in_segment::offset, + "Original offset of the structure, relative to :attr:`~lief.MachO.DyldChainedFixups.starts_offset`"_doc) + .def_ro("size", &DyldChainedFixups::chained_starts_in_segment::size, + "``sizeof(size) + sizeof(page_size) + ... + sizeof(pointer_format)``"_doc) + .def_ro("page_size", &DyldChainedFixups::chained_starts_in_segment::page_size, + "Likely 0x1000 for x86/x86_64 architectures and 0x4000 for ARM64 architecture"_doc) + .def_ro("segment_offset", &DyldChainedFixups::chained_starts_in_segment::segment_offset, + R"delim( + Offset of the segment's data from the beginning of the file. + (it should match :attr:`~lief.MachO.SegmentCommand.file_offset`) + )delim"_doc) + .def_ro("page_start", &DyldChainedFixups::chained_starts_in_segment::page_start, + R"delim( + Offset in the :class:`~lief.MachO.SegmentCommand` of the first + element of the chain. + )delim"_doc) + .def_ro("pointer_format", &DyldChainedFixups::chained_starts_in_segment::pointer_format, + R"delim(How pointers are encoded)delim"_doc) + .def_ro("max_valid_pointer", &DyldChainedFixups::chained_starts_in_segment::max_valid_pointer, + R"delim(for 32-bit OS, any value beyond this is not a pointer)delim"_doc) + .def_prop_ro("page_count", + &DyldChainedFixups::chained_starts_in_segment::page_count, + "How many pages are in the :attr:`~lief.MachO.DyldChainedFixups.page_start` array"_doc) + + .def_prop_ro("segment", + [] (DyldChainedFixups::chained_starts_in_segment& self) -> SegmentCommand* { + return &self.segment; + }, + ":class:`~lief.MachO.SegmentCommand` in which the rebase/bind fixups take place"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(DyldChainedFixups::chained_starts_in_segment); + + chained + .def_prop_rw("data_offset", + nb::overload_cast<>(&DyldChainedFixups::data_offset, nb::const_), + nb::overload_cast(&DyldChainedFixups::data_offset), + R"delim( + Offset of the LC_DYLD_CHAINED_FIXUPS chained payload. + This offset should point in the ``__LINKEDIT`` segment + )delim"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&DyldChainedFixups::data_size, nb::const_), + nb::overload_cast(&DyldChainedFixups::data_size), + "Size of the LC_DYLD_CHAINED_FIXUPS payload"_doc) + + .def_prop_ro("payload", + nb::overload_cast<>(&DyldChainedFixups::payload, nb::const_), + "Return the raw content of the command") + + .def_prop_ro("bindings", + nb::overload_cast<>(&DyldChainedFixups::bindings), + "Iterator over the bindings " RST_CLASS_REF(lief.MachO.ChainedBindingInfo) + " associated with this command"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("chained_starts_in_segments", + nb::overload_cast<>(&DyldChainedFixups::chained_starts_in_segments), + "Iterator over the chained fixup metadata, " RST_CLASS_REF(lief.MachO.DyldChainedFixups.chained_starts_in_segment) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_rw("fixups_version", + nb::overload_cast<>(&DyldChainedFixups::fixups_version, nb::const_), + nb::overload_cast(&DyldChainedFixups::fixups_version), + R"delim( + Chained fixups version. The loader (as of dyld v852.2) checks + that this value is set to 0. + )delim"_doc) + + .def_prop_rw("starts_offset", + nb::overload_cast<>(&DyldChainedFixups::starts_offset, nb::const_), + nb::overload_cast(&DyldChainedFixups::starts_offset), + R"delim(offset of dyld_chained_starts_in_image in chain_data)delim"_doc) + + .def_prop_rw("imports_offset", + nb::overload_cast<>(&DyldChainedFixups::imports_offset, nb::const_), + nb::overload_cast(&DyldChainedFixups::imports_offset), + R"delim(Offset of imports table in chain data)delim"_doc) + + .def_prop_rw("symbols_offset", + nb::overload_cast<>(&DyldChainedFixups::symbols_offset, nb::const_), + nb::overload_cast(&DyldChainedFixups::symbols_offset), + R"delim(Offset of symbol strings in chain data)delim"_doc) + + .def_prop_rw("imports_count", + nb::overload_cast<>(&DyldChainedFixups::imports_count, nb::const_), + nb::overload_cast(&DyldChainedFixups::imports_count), + R"delim(Number of imported symbol names)delim"_doc) + + .def_prop_rw("symbols_format", + nb::overload_cast<>(&DyldChainedFixups::symbols_format, nb::const_), + nb::overload_cast(&DyldChainedFixups::symbols_format), + R"delim( + The compression algorithm (if any) used to store the symbols + 0 means uncompressed while 1 means zlib compressed. + + As of the version v852.2 of dyld loader, it only supports + **uncompressed** format + )delim"_doc) + + .def_prop_rw("imports_format", + nb::overload_cast<>(&DyldChainedFixups::imports_format, nb::const_), + nb::overload_cast(&DyldChainedFixups::imports_format), + R"delim( + The format of the imports (:class:`~lief.MachO.ChainedBindingInfo`) + )delim"_doc) + + LIEF_DEFAULT_STR(DyldChainedFixups); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDyldEnvironment.cpp b/vendor/lief/api/python/src/MachO/objects/pyDyldEnvironment.cpp new file mode 100644 index 0000000..6855752 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDyldEnvironment.cpp @@ -0,0 +1,46 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include +#include +#include +#include + +#include "LIEF/MachO/DyldEnvironment.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "DyldEnvironment", + R"delim( + Class that represents a LC_DYLD_ENVIRONMENT which is + used by the Mach-O linker/loader to initialize an environment variable + )delim"_doc) + + .def_prop_rw("value", + nb::overload_cast<>(&DyldEnvironment::value, nb::const_), + nb::overload_cast(&DyldEnvironment::value), + "Environment variable as a string"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(DyldEnvironment); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDyldExportsTrie.cpp b/vendor/lief/api/python/src/MachO/objects/pyDyldExportsTrie.cpp new file mode 100644 index 0000000..765bb8a --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDyldExportsTrie.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "pyIterator.hpp" +#include "nanobind/extra/stl/lief_span.h" + +#include "LIEF/MachO/DyldExportsTrie.hpp" +#include "LIEF/MachO/ExportInfo.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ exports_trie(m, "DyldExportsTrie", + R"delim( + Class that represents the LC_DYLD_EXPORTS_TRIE command + + In recent Mach-O binaries, this command replace the DyldInfo export trie buffer + )delim"_doc); + + init_ref_iterator(exports_trie, "it_export_info"); + + exports_trie + .def_prop_rw("data_offset", + nb::overload_cast<>(&DyldExportsTrie::data_offset, nb::const_), + nb::overload_cast(&DyldExportsTrie::data_offset), + "Offset of the trie in the binary. This offset should point in the __LINKEDIT"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&DyldExportsTrie::data_size, nb::const_), + nb::overload_cast(&DyldExportsTrie::data_size), + "Raw size of the trie"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&DyldExportsTrie::content, nb::const_), + "The raw export trie"_doc) + + .def_prop_ro("exports", + nb::overload_cast<>(&DyldExportsTrie::exports), + R"delim( + Iterator over the :class:`~lief.MachO.ExportInfo` associated with + this trie. + )delim"_doc) + + .def("show_export_trie", + &DyldExportsTrie::show_export_trie, + "Show the trie in a human-readable way"_doc) + + LIEF_DEFAULT_STR(DyldExportsTrie); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDyldInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyDyldInfo.cpp new file mode 100644 index 0000000..079345c --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDyldInfo.cpp @@ -0,0 +1,306 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/DyldInfo.hpp" +#include "LIEF/MachO/ExportInfo.hpp" +#include "LIEF/MachO/DyldBindingInfo.hpp" + +#include "pyIterator.hpp" +#include "nanobind/extra/stl/lief_span.h" + +#include "MachO/pyMachO.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +// (rtti)Trick to avoid duplication clash with DyldExportsTrie::it_export_info +class dyldinfo_it_export_info : public DyldInfo::it_export_info { + public: + using DyldInfo::it_export_info::it_export_info; +}; + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ dyld(m, "DyldInfo", + R"delim( + Class that represents the LC_DYLD_INFO and LC_DYLD_INFO_ONLY commands + )delim"_doc); + + enum_(dyld, "REBASE_TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(DyldInfo::REBASE_TYPE::POINTER)) + .value(PY_ENUM(DyldInfo::REBASE_TYPE::TEXT_ABSOLUTE32)) + .value(PY_ENUM(DyldInfo::REBASE_TYPE::TEXT_PCREL32)) + .value(PY_ENUM(DyldInfo::REBASE_TYPE::THREADED)) + #undef PY_ENUM + ; + + enum_(dyld, "REBASE_OPCODES") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::DONE)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::SET_TYPE_IMM)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::SET_SEGMENT_AND_OFFSET_ULEB)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::ADD_ADDR_ULEB)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::ADD_ADDR_IMM_SCALED)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::DO_REBASE_IMM_TIMES)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::DO_REBASE_ULEB_TIMES)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::DO_REBASE_ADD_ADDR_ULEB)) + .value(PY_ENUM(DyldInfo::REBASE_OPCODES::DO_REBASE_ULEB_TIMES_SKIPPING_ULEB)) + #undef PY_ENUM + ; + + enum_(dyld, "BIND_OPCODES") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(DyldInfo::BIND_OPCODES::DONE)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_DYLIB_ORDINAL_IMM)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_DYLIB_ORDINAL_ULEB)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_DYLIB_SPECIAL_IMM)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_SYMBOL_TRAILING_FLAGS_IMM)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_TYPE_IMM)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_ADDEND_SLEB)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::SET_SEGMENT_AND_OFFSET_ULEB)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::ADD_ADDR_ULEB)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::DO_BIND)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::DO_BIND_ADD_ADDR_ULEB)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::DO_BIND_ADD_ADDR_IMM_SCALED)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::DO_BIND_ULEB_TIMES_SKIPPING_ULEB)) + /* .value(PY_ENUM(DyldInfo::BIND_OPCODES::THREADED)) */ + .value(PY_ENUM(DyldInfo::BIND_OPCODES::THREADED_APPLY)) + .value(PY_ENUM(DyldInfo::BIND_OPCODES::THREADED_SET_BIND_ORDINAL_TABLE_SIZE_ULEB)) + #undef PY_ENUM + ; + + init_ref_iterator(dyld, "it_binding_info"); + init_ref_iterator(dyld, "it_export_info"); + + dyld + .def_prop_rw("rebase", + nb::overload_cast<>(&DyldInfo::rebase, nb::const_), + nb::overload_cast(&DyldInfo::rebase), + R"delim( + *Rebase* information as a tuple ``(offset, size)`` + + Dyld rebases an image whenever dyld loads it at an address different + from its preferred address. The rebase information is a stream + of byte sized opcodes for which symbolic names start with ``REBASE_OPCODE_``. + + Conceptually the rebase information is a table of tuples: ``(seg-index, seg-offset, type)`` + + The opcodes are a compressed way to encode the table by only + encoding when a column changes. In addition simple patterns + like "every n'th offset for m times" can be encoded in a few bytes + + .. seealso:: + + ``/usr/include/mach-o/loader.h`` + )delim"_doc) + + .def_prop_rw("rebase_opcodes", + nb::overload_cast<>(&DyldInfo::rebase_opcodes, nb::const_), + nb::overload_cast(&DyldInfo::rebase_opcodes), + "Return the rebase's opcodes as ``list`` of bytes"_doc) + + .def_prop_ro("show_rebases_opcodes", + &DyldInfo::show_rebases_opcodes, + "Return the rebase opcodes in a human-readable way"_doc) + + .def_prop_rw("bind", + nb::overload_cast<>(&DyldInfo::bind, nb::const_), + nb::overload_cast(&DyldInfo::bind), + R"delim( + *Bind* information as a tuple ``(offset, size)`` + + Dyld binds an image during the loading process, if the image + requires any pointers to be initialized to symbols in other images. + The rebase information is a stream of byte sized opcodes for which symbolic names start with ``BIND_OPCODE_``. + + Conceptually the bind information is a table of tuples: + ``(seg-index, seg-offset, type, symbol-library-ordinal, symbol-name, addend)`` + The opcodes are a compressed way to encode the table by only encoding when a column changes. In addition simple patterns + like for runs of pointers initialized to the same value can be encoded in a few bytes. + + .. seealso:: + + ``/usr/include/mach-o/loader.h`` + )delim"_doc) + + .def_prop_rw("bind_opcodes", + nb::overload_cast<>(&DyldInfo::bind_opcodes, nb::const_), + nb::overload_cast(&DyldInfo::bind_opcodes), + "Return the binding's opcodes as ``list`` of bytes"_doc) + + .def_prop_ro("show_bind_opcodes", + &DyldInfo::show_bind_opcodes, + "Return the bind opcodes in a human-readable way") + + .def_prop_rw("weak_bind", + nb::overload_cast<>(&DyldInfo::weak_bind, nb::const_), + nb::overload_cast(&DyldInfo::weak_bind), + R"delim( + *Weak Bind* information as a tuple ``(offset, size)`` + + Some C++ programs require dyld to unique symbols so that all + images in the process use the same copy of some code/data. + + This step is done after binding. + The content of the weak_bind info is an opcode stream like the bind_info. + But it is sorted alphabetically by symbol name. This enables dyld to walk + all images with weak binding information in order and look for collisions. + If there are no collisions, dyld does no updating. + That means that some fixups are also encoded in the bind_info. + For instance, all calls to ``operator new`` are first bound to ``libstdc++.dylib`` + using the information in bind_info. + Then if some image overrides operator new that is detected when + the weak_bind information is processed and the call to operator new is then rebound. + + .. seealso:: + + ``/usr/include/mach-o/loader.h`` + )delim"_doc) + + .def_prop_rw("weak_bind_opcodes", + nb::overload_cast<>(&DyldInfo::weak_bind_opcodes, nb::const_), + nb::overload_cast(&DyldInfo::weak_bind_opcodes), + "Return **Weak** binding's opcodes as ``list`` of bytes"_doc) + + .def_prop_ro("show_weak_bind_opcodes", + &DyldInfo::show_weak_bind_opcodes, + "Return the weak bind opcodes in a human-readable way") + + .def_prop_rw("lazy_bind", + nb::overload_cast<>(&DyldInfo::lazy_bind, nb::const_), + nb::overload_cast(&DyldInfo::lazy_bind), + R"delim( + *Lazy Bind* information as a tuple ``(offset, size)`` + + Some uses of external symbols do not need to be bound immediately. + Instead they can be lazily bound on first use. + The lazy_bind contains a stream of BIND opcodes to bind all lazy symbols. + Normal use is that dyld ignores the lazy_bind section when loading an image. + Instead the static linker arranged for the lazy pointer to initially point + to a helper function which pushes the offset into the lazy_bind area for the symbol + needing to be bound, then jumps to dyld which simply adds the offset to + lazy_bind_off to get the information on what to bind. + + .. seealso:: + + ``/usr/include/mach-o/loader.h`` + )delim"_doc) + + .def_prop_rw("lazy_bind_opcodes", + nb::overload_cast<>(&DyldInfo::lazy_bind_opcodes, nb::const_), + nb::overload_cast(&DyldInfo::lazy_bind_opcodes), + "Return **lazy** binding's opcodes as ``list`` of bytes"_doc) + + .def_prop_ro("show_lazy_bind_opcodes", + &DyldInfo::show_lazy_bind_opcodes, + "Return the lazy bind opcodes in a human-readable way"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("bindings", + nb::overload_cast<>(&DyldInfo::bindings), + "Return an iterator over Dyld's " RST_CLASS_REF(lief.MachO.BindingInfo) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("export_info", + nb::overload_cast<>(&DyldInfo::export_info, nb::const_), + nb::overload_cast(&DyldInfo::export_info), + R"delim( + *Export* information as a tuple ``(offset, size)`` + + The symbols exported by a dylib are encoded in a trie. + This is a compact representation that factors out common prefixes. + + It also reduces ``LINKEDIT`` pages in RAM because it encodes all + information (name, address, flags) in one small, contiguous range. + The export area is a stream of nodes. The first node sequentially + is the start node for the trie. + + Nodes for a symbol start with a byte that is the length of the exported + symbol information for the string so far. + If there is no exported symbol, the byte is zero. + If there is exported info, it follows the length byte. + The exported info normally consists of a flags and offset both encoded + in `uleb128 `_. + The offset is location of the content named by the symbol. + It is the offset from the mach_header for the image. + + After the initial byte and optional exported symbol information + is a byte of how many edges (0-255) that this node has leaving + it, followed by each edge. + Each edge is a zero terminated cstring of the addition chars + in the symbol, followed by a uleb128 offset for the node that + edge points to. + + .. seealso:: + + ``/usr/include/mach-o/loader.h`` + )delim"_doc) + + .def_prop_rw("export_trie", + nb::overload_cast<>(&DyldInfo::export_trie, nb::const_), + nb::overload_cast(&DyldInfo::export_trie), + "Return Export's trie as ``list`` of bytes"_doc) + + .def_prop_ro("exports", + nb::overload_cast<>(&DyldInfo::exports), + "Return an iterator over Dyld's " RST_CLASS_REF(lief.MachO.ExportInfo) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("show_export_trie", + &DyldInfo::show_export_trie, + "Return the export trie in a human-readable way"_doc, + nb::rv_policy::reference_internal) + + .def("set_rebase_offset", &DyldInfo::set_rebase_offset, + "offset"_a) + + .def("set_rebase_size", &DyldInfo::set_rebase_size, + "size"_a) + + .def("set_bind_offset", &DyldInfo::set_bind_offset, + "offset"_a) + + .def("set_bind_size", &DyldInfo::set_bind_size, + "size"_a) + + .def("set_weak_bind_offset", &DyldInfo::set_weak_bind_offset, + "offset"_a) + + .def("set_weak_bind_size", &DyldInfo::set_weak_bind_size, + "size"_a) + + .def("set_lazy_bind_offset", &DyldInfo::set_lazy_bind_offset, + "offset"_a) + + .def("set_lazy_bind_size", &DyldInfo::set_lazy_bind_size, + "size"_a) + + .def("set_export_offset", &DyldInfo::set_export_offset, + "offset"_a) + + .def("set_export_size", &DyldInfo::set_export_size, + "size"_a) + + LIEF_DEFAULT_STR(DyldInfo); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDylibCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyDylibCommand.cpp new file mode 100644 index 0000000..ef86bcc --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDylibCommand.cpp @@ -0,0 +1,92 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "LIEF/MachO/DylibCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "DylibCommand", + R"delim(Class which represents a library dependency)delim"_doc) + + .def_prop_rw("name", + nb::overload_cast<>(&DylibCommand::name, nb::const_), + nb::overload_cast(&DylibCommand::name), + "Library's name"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("name_offset", &DylibCommand::name_offset, + "Original string offset of the name") + + .def_prop_rw("timestamp", + nb::overload_cast<>(&DylibCommand::timestamp, nb::const_), + nb::overload_cast(&DylibCommand::timestamp), + "Library's timestamp"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("current_version", + nb::overload_cast<>(&DylibCommand::current_version, nb::const_), + nb::overload_cast(&DylibCommand::current_version), + "Library's current version"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("compatibility_version", + nb::overload_cast<>(&DylibCommand::compatibility_version, nb::const_), + nb::overload_cast(&DylibCommand::compatibility_version), + "Library's compatibility version"_doc, + nb::rv_policy::reference_internal) + + .def_static("weak_lib", + &DylibCommand::weak_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.LOAD_WEAK_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + .def_static("id_dylib", + &DylibCommand::id_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.ID_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + .def_static("load_dylib", + &DylibCommand::load_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.LOAD_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + .def_static("reexport_dylib", + &DylibCommand::reexport_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.REEXPORT_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + .def_static("load_upward_dylib", + &DylibCommand::load_upward_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.LOAD_UPWARD_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + .def_static("lazy_load_dylib", + &DylibCommand::lazy_load_dylib, + "Factory function to generate a " RST_CLASS_REF(lief.MachO.LoadCommand.TYPE.LAZY_LOAD_DYLIB) " library"_doc, + "name"_a, "timestamp"_a = 0, "current_version"_a = 0, "compat_version"_a = 0) + + LIEF_DEFAULT_STR(DylibCommand); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDylinker.cpp b/vendor/lief/api/python/src/MachO/objects/pyDylinker.cpp new file mode 100644 index 0000000..66bf940 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDylinker.cpp @@ -0,0 +1,45 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/DylinkerCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "DylinkerCommand", + R"delim( + Class that represents the Mach-O linker, also named loader + Most of the time, :attr:`~lief.MachO.DylinkerCommand.name` returns ``/usr/lib/dyld`` + )delim"_doc) + .def(nb::init()) + + .def_prop_rw("name", + nb::overload_cast<>(&DylinkerCommand::name, nb::const_), + nb::overload_cast(&DylinkerCommand::name), + "Path to the loader/linker"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(DylinkerCommand); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyDynamicSymbolCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyDynamicSymbolCommand.cpp new file mode 100644 index 0000000..a11a153 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyDynamicSymbolCommand.cpp @@ -0,0 +1,185 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/DynamicSymbolCommand.hpp" +#include "LIEF/MachO/Symbol.hpp" + +#include "MachO/pyMachO.hpp" +#include "pyIterator.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ dynsym(m, "DynamicSymbolCommand", + R"delim( + Class that represents the LC_DYSYMTAB command. + This command completes the LC_SYMTAB (SymbolCommand) to provide + a better granularity over the symbols layout. + )delim"_doc); + + init_ref_iterator(dynsym, "it_indirect_symbols"); + + dynsym + .def_prop_rw("idx_local_symbol", + nb::overload_cast<>(&DynamicSymbolCommand::idx_local_symbol, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::idx_local_symbol), + "Index of the first symbol in the group of local symbols."_doc + ) + + .def_prop_rw("nb_local_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::nb_local_symbols, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_local_symbols), + "Number of symbols in the group of local symbols."_doc + ) + + .def_prop_rw("idx_external_define_symbol", + nb::overload_cast<>(&DynamicSymbolCommand::idx_external_define_symbol, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::idx_external_define_symbol), + "Index of the first symbol in the group of defined external symbols."_doc + ) + + .def_prop_rw("nb_external_define_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::nb_external_define_symbols, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_external_define_symbols), + "Number of symbols in the group of defined external symbols."_doc + ) + + .def_prop_rw("idx_undefined_symbol", + nb::overload_cast<>(&DynamicSymbolCommand::idx_undefined_symbol, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::idx_undefined_symbol), + "Index of the first symbol in the group of undefined external symbols."_doc + ) + + .def_prop_rw("nb_undefined_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::nb_undefined_symbols, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_undefined_symbols), + "Number of symbols in the group of undefined external symbols."_doc + ) + + .def_prop_rw("toc_offset", + nb::overload_cast<>(&DynamicSymbolCommand::toc_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::toc_offset), + R"delim( + Byte offset from the start of the file to the table of contents data. + Table of content is used by legacy Mach-O loader and this field should be set to 0 + )delim"_doc) + + .def_prop_rw("nb_toc", + nb::overload_cast<>(&DynamicSymbolCommand::nb_toc, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_toc), + R"delim( + Number of entries in the table of contents + Should be set to 0 on recent Mach-O + )delim"_doc) + + .def_prop_rw("module_table_offset", + nb::overload_cast<>(&DynamicSymbolCommand::module_table_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::module_table_offset), + R"delim( + Byte offset from the start of the file to the module table data. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_rw("nb_module_table", + nb::overload_cast<>(&DynamicSymbolCommand::nb_module_table, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_module_table), + R"delim( + Number of entries in the module table. + This field seems unused by recent Mach-O loader and should be set to 0. + )delim"_doc) + + .def_prop_rw("external_reference_symbol_offset", + nb::overload_cast<>(&DynamicSymbolCommand::external_reference_symbol_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::external_reference_symbol_offset), + R"delim( + Byte offset from the start of the file to the external reference table data. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_rw("nb_external_reference_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::nb_external_reference_symbols, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_external_reference_symbols), + R"delim( + Number of entries in the external reference table. + This field seems unused by recent Mach-O loader and should be set to 0. + )delim"_doc) + + .def_prop_rw("indirect_symbol_offset", + nb::overload_cast<>(&DynamicSymbolCommand::indirect_symbol_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::indirect_symbol_offset), + R"delim( + Byte offset from the start of the file to the indirect symbol table data. + + Indirect symbol table is used by the loader to speed-up symbol resolution during + the *lazy binding* process + + References: + + * ``dyld-519.2.1/src/ImageLoaderMachOCompressed.cpp`` + * ``dyld-519.2.1/src/ImageLoaderMachOClassic.cpp`` + )delim"_doc) + + .def_prop_rw("nb_indirect_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::nb_indirect_symbols, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_indirect_symbols), + "Number of entries in the indirect symbol table."_doc) + + .def_prop_rw("external_relocation_offset", + nb::overload_cast<>(&DynamicSymbolCommand::external_relocation_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::external_relocation_offset), + R"delim( + Byte offset from the start of the file to the module table data. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_rw("nb_external_relocations", + nb::overload_cast<>(&DynamicSymbolCommand::nb_external_relocations, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_external_relocations), + R"delim( + Number of entries in the external relocation table. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_rw("local_relocation_offset", + nb::overload_cast<>(&DynamicSymbolCommand::local_relocation_offset, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::local_relocation_offset), + R"delim( + Byte offset from the start of the file to the local relocation table data. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_rw("nb_local_relocations", + nb::overload_cast<>(&DynamicSymbolCommand::nb_local_relocations, nb::const_), + nb::overload_cast(&DynamicSymbolCommand::nb_local_relocations), + R"delim( + Number of entries in the local relocation table. + This field seems unused by recent Mach-O loader and should be set to 0 + )delim"_doc) + + .def_prop_ro("indirect_symbols", + nb::overload_cast<>(&DynamicSymbolCommand::indirect_symbols), + "Iterator over the indirect symbols indexed by this command"_doc, + nb::keep_alive<0, 1>()) + + LIEF_DEFAULT_STR(DynamicSymbolCommand); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyEncryptionInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyEncryptionInfo.cpp new file mode 100644 index 0000000..944c255 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyEncryptionInfo.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/EncryptionInfo.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "EncryptionInfo", + R"delim( + Class that represents the LC_ENCRYPTION_INFO / LC_ENCRYPTION_INFO_64 commands + + The encryption info is usually present in Mach-O executables that + target iOS to encrypt some sections of the binary + )delim"_doc) + + .def_prop_rw("crypt_offset", + nb::overload_cast<>(&EncryptionInfo::crypt_offset, nb::const_), + nb::overload_cast(&EncryptionInfo::crypt_offset), + "File offset of encrypted range"_doc) + + .def_prop_rw("crypt_size", + nb::overload_cast<>(&EncryptionInfo::crypt_size, nb::const_), + nb::overload_cast(&EncryptionInfo::crypt_size), + "File size of encrypted range"_doc) + + .def_prop_rw("crypt_id", + nb::overload_cast<>(&EncryptionInfo::crypt_id, nb::const_), + nb::overload_cast(&EncryptionInfo::crypt_id), + "The encryption system. 0 means not encrypted"_doc) + + LIEF_DEFAULT_STR(EncryptionInfo); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyExportInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyExportInfo.cpp new file mode 100644 index 0000000..7024b85 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyExportInfo.cpp @@ -0,0 +1,109 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/ExportInfo.hpp" +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/MachO/DylibCommand.hpp" + +#include "MachO/pyMachO.hpp" +#include "pyIterator.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls(m, "ExportInfo", + R"delim( + Class that provides an interface over the Dyld export info + + This class does not represent a structure that exists in the Mach-O format + specification but provides a *view* on an entry of the Dyld export trie. + )delim"_doc); + + enum_(cls, "KIND") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(ExportInfo::KIND::REGULAR)) + .value(PY_ENUM(ExportInfo::KIND::THREAD_LOCAL_KIND)) + .value(PY_ENUM(ExportInfo::KIND::ABSOLUTE_KIND)) + #undef PY_ENUM + ; + + enum_(cls, "FLAGS", nb::is_flag()) + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(ExportInfo::FLAGS::WEAK_DEFINITION)) + .value(PY_ENUM(ExportInfo::FLAGS::REEXPORT)) + .value(PY_ENUM(ExportInfo::FLAGS::STUB_AND_RESOLVER)) + .value(PY_ENUM(ExportInfo::FLAGS::STATIC_RESOLVER)) + #undef PY_ENUM + ; + + cls + .def_prop_ro("node_offset", + nb::overload_cast<>(&ExportInfo::node_offset, nb::const_), + "Original offset in the export Trie"_doc) + + .def_prop_ro("kind", + nb::overload_cast<>(&ExportInfo::kind, nb::const_), + "The export's kind: regular, thread local, absolute, ... (" RST_CLASS_REF(lief.MachO.ExportInfo.KIND) ")"_doc) + + .def_prop_ro("flags_list", + nb::overload_cast<>(&ExportInfo::flags_list, nb::const_), + "Return flags as a list of " RST_CLASS_REF(lief.MachO.ExportInfo.FLAGS) ""_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&ExportInfo::flags, nb::const_), + nb::overload_cast(&ExportInfo::flags), + "Some information (" RST_CLASS_REF(lief.MachO.ExportInfo.FLAGS) ") about the export (like weak export, reexport, ...)"_doc) + + .def_prop_rw("address", + nb::overload_cast<>(&ExportInfo::address, nb::const_), + nb::overload_cast(&ExportInfo::address), + "The address of the export"_doc) + + .def_prop_ro("alias", + nb::overload_cast<>(&ExportInfo::alias, nb::const_), + "" RST_CLASS_REF(lief.MachO.Symbol) " alias if the current symbol is re-exported"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("alias_library", + nb::overload_cast<>(&ExportInfo::alias_library, nb::const_), + "If the current symbol has an alias, it returns the " RST_CLASS_REF(lief.MachO.DylibCommand) " " + " command associated with"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_symbol", + &ExportInfo::has_symbol, + "``True`` if the export info has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with"_doc) + + .def("has", + &ExportInfo::has, + "Check if the flag " RST_CLASS_REF(lief.MachO.ExportInfo.FLAGS) " given in first parameter is present"_doc, + "flag"_a) + + .def_prop_ro("symbol", + nb::overload_cast<>(&ExportInfo::symbol), + "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the export if any, or None "_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(ExportInfo); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyFatBinary.cpp b/vendor/lief/api/python/src/MachO/objects/pyFatBinary.cpp new file mode 100644 index 0000000..6a6ab15 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyFatBinary.cpp @@ -0,0 +1,102 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +#include "LIEF/MachO/FatBinary.hpp" +#include "LIEF/MachO/Binary.hpp" + +#include "pyIterator.hpp" +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ fat(m, "FatBinary", + R"delim( + Class which represents a Mach-O (fat) binary + This object is also used for representing Mach-O binaries that are **NOT FAT** + )delim"_doc); + + init_ref_iterator(fat, "it_binaries"); + + fat + .def_static("create", + [] (FatBinary::binaries_t binaries) { + return FatBinary::create(std::move(binaries)); + }, + R"delim( + Create a :class:`~lief.MachO.FatBinary` from the provided list of + :class:`~lief.MachO.Binary` objects. + + The binaries **must** target different architectures (i.e. unique + cpu_type / cpu_subtype pairs). If a duplicate architecture is detected, + this function returns None. + )delim"_doc, + "binaries"_a) + + .def_prop_ro("size", &FatBinary::size, + "Number of " RST_CLASS_REF(lief.MachO.Binary) " registered"_doc) + + .def("at", + nb::overload_cast(&FatBinary::at), + "Return the " RST_CLASS_REF(lief.MachO.Binary) " at the given index or None if it is not present"_doc, + "index"_a, + nb::rv_policy::reference_internal) + + .def("take", + nb::overload_cast(&FatBinary::take), + "Return the " RST_CLASS_REF(lief.MachO.Binary) " that matches the " + "given " RST_CLASS_REF(lief.MachO.Header.CPU_TYPE) ""_doc, + "cpu"_a, nb::rv_policy::take_ownership) + + .def("write", [] (FatBinary& fat, nb::PathLike path) { fat.write(path); }, + "Build a Mach-O universal binary"_doc, + "filename"_a, nb::lock_self()) + + .def("raw", &FatBinary::raw, + "Build a Mach-O universal binary and return its bytes"_doc, + nb::lock_self()) + + .def("get", nb::overload_cast(&FatBinary::get), + "Gets the :class:`~.Binary` that matches the given architecture"_doc, + nb::rv_policy::reference_internal) + + .def("__len__", &FatBinary::size) + + .def("__getitem__", + nb::overload_cast(&FatBinary::operator[]), + nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&FatBinary::operator[]), + nb::rv_policy::reference_internal) + + .def("__iter__", + nb::overload_cast<>(&FatBinary::begin), + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(FatBinary); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyFilesetCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyFilesetCommand.cpp new file mode 100644 index 0000000..1da13ee --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyFilesetCommand.cpp @@ -0,0 +1,54 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/FilesetCommand.hpp" +#include "LIEF/MachO/Binary.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "FilesetCommand", + "Class associated with the LC_FILESET_ENTRY commands"_doc) + .def_prop_rw("name", + nb::overload_cast<>(&FilesetCommand::name, nb::const_), + nb::overload_cast(&FilesetCommand::name), + "Name of the underlying MachO binary"_doc) + + .def_prop_rw("virtual_address", + nb::overload_cast<>(&FilesetCommand::virtual_address, nb::const_), + nb::overload_cast(&FilesetCommand::virtual_address), + "Memory address where the MachO file should be mapped"_doc) + + .def_prop_rw("file_offset", + nb::overload_cast<>(&FilesetCommand::file_offset, nb::const_), + nb::overload_cast(&FilesetCommand::file_offset), + "Original offset in the kernel cache"_doc) + + .def_prop_ro("binary", + nb::overload_cast<>(&FilesetCommand::binary, nb::const_), + "Return the " RST_CLASS_REF(lief.MachO.Binary) " object associated with the entry"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(FilesetCommand); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyFunctionStarts.cpp b/vendor/lief/api/python/src/MachO/objects/pyFunctionStarts.cpp new file mode 100644 index 0000000..09345a3 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyFunctionStarts.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/FunctionStarts.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "FunctionStarts", + R"delim( + Class which represents the LC_FUNCTION_STARTS command + + This command is an array of ULEB128 encoded values + )delim"_doc) + + .def_prop_rw("data_offset", + nb::overload_cast<>(&FunctionStarts::data_offset, nb::const_), + nb::overload_cast(&FunctionStarts::data_offset), + "Offset in the binary where *start functions* are located"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&FunctionStarts::data_size, nb::const_), + nb::overload_cast(&FunctionStarts::data_size), + "Size of the functions list in the binary"_doc) + + .def_prop_rw("functions", + nb::overload_cast<>(&FunctionStarts::functions, nb::const_), + nb::overload_cast>(&FunctionStarts::functions), + R"delim( + Addresses of every function entry point in the executable + + This allows functions to exist for which there are no entries in the symbol table. + + .. warning:: + + The address is relative to the ``__TEXT`` segment + )delim"_doc, + nb::rv_policy::reference_internal) + + .def("add_function", &FunctionStarts::add_function, + "Add a new function"_doc, + "address"_a, nb::lock_self()) + + .def_prop_ro("content", + nb::overload_cast<>(&FunctionStarts::content, nb::const_), + "The original content as a bytes stream"_doc) + + LIEF_DEFAULT_STR(FunctionStarts); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyFunctionVariantFixups.cpp b/vendor/lief/api/python/src/MachO/objects/pyFunctionVariantFixups.cpp new file mode 100644 index 0000000..a9e826c --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyFunctionVariantFixups.cpp @@ -0,0 +1,126 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/FunctionVariantFixups.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" + +#include "pyIterator.hpp" +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +using Fixup = FunctionVariantFixups::Fixup; + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cmd(m, "FunctionVariantFixups", + R"doc( + Class which represents the ``LC_FUNCTION_VARIANT_FIXUPS`` command. + + This command contains the relocations that must be applied to the GOT-like + slots associated with a :class:`~lief.MachO.FunctionVariants` table. At + runtime, ``dyld`` resolves each slot to the best implementation and + (re-)signs it according to the pointer-authentication information. + )doc"_doc); + + nb::class_(cmd, "Fixup", + R"doc( + A single relocation associated with a function-variant. It mirrors the + ``FunctionVariantFixups::InternalFixup`` structure used by ``dyld`` and + describes a slot that must be fixed up to point to the variant referenced by + :attr:`~.variant_index`. + )doc"_doc) + .def(nb::init<>()) + .def(nb::init(), + "seg_offset"_a, "seg_index"_a, "variant_index"_a, "pac_auth"_a, + "pac_address"_a, "pac_key"_a, "pac_diversity"_a) + + .def_prop_rw("seg_offset", + nb::overload_cast<>(&Fixup::seg_offset, nb::const_), + nb::overload_cast(&Fixup::seg_offset), + "Offset of the slot to fix up, relative to :attr:`~.seg_index`"_doc) + + .def_prop_rw("seg_index", + nb::overload_cast<>(&Fixup::seg_index, nb::const_), + nb::overload_cast(&Fixup::seg_index), + "Index of the segment that owns the slot to fix up"_doc) + + .def_prop_rw("variant_index", + nb::overload_cast<>(&Fixup::variant_index, nb::const_), + nb::overload_cast(&Fixup::variant_index), + "Index of the FunctionVariants runtime table used to resolve the slot"_doc) + + .def_prop_rw("pac_auth", + nb::overload_cast<>(&Fixup::pac_auth, nb::const_), + nb::overload_cast(&Fixup::pac_auth), + "Whether the slot is signed with pointer authentication (arm64e)"_doc) + + .def_prop_rw("pac_address", + nb::overload_cast<>(&Fixup::pac_address, nb::const_), + nb::overload_cast(&Fixup::pac_address), + "Whether the PAC signature mixes the storage address (address diversity)"_doc) + + .def_prop_rw("pac_key", + nb::overload_cast<>(&Fixup::pac_key, nb::const_), + nb::overload_cast(&Fixup::pac_key), + "PAC key used to sign the slot"_doc) + + .def_prop_rw("pac_diversity", + nb::overload_cast<>(&Fixup::pac_diversity, nb::const_), + nb::overload_cast(&Fixup::pac_diversity), + "PAC diversity (discriminator) of the slot"_doc) + + .def_prop_ro("segment", + nb::overload_cast<>(&Fixup::segment), + "" RST_CLASS_REF(lief.MachO.SegmentCommand) " referenced by " + ":attr:`~.seg_index` if it could be resolved, or None"_doc, + nb::rv_policy::reference_internal) + LIEF_DEFAULT_STR(Fixup); + + init_ref_iterator(cmd, "it_fixups"); + + cmd + .def_prop_rw("data_offset", + nb::overload_cast<>(&FunctionVariantFixups::data_offset, nb::const_), + nb::overload_cast(&FunctionVariantFixups::data_offset), + "Offset in the binary where the payload starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&FunctionVariantFixups::data_size, nb::const_), + nb::overload_cast(&FunctionVariantFixups::data_size), + "Size of the payload"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&FunctionVariantFixups::content, nb::const_), + "Payload content"_doc) + + .def_prop_ro("fixups", nb::overload_cast<>(&FunctionVariantFixups::fixups), + "Iterator over the different :class:`~.Fixup` entries"_doc, + nb::keep_alive<0, 1>()) + + .def("add", &FunctionVariantFixups::add, + "Append a new :class:`~.Fixup`"_doc, "fixup"_a) + + LIEF_DEFAULT_STR(FunctionVariantFixups); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyFunctionVariants.cpp b/vendor/lief/api/python/src/MachO/objects/pyFunctionVariants.cpp new file mode 100644 index 0000000..2431d2e --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyFunctionVariants.cpp @@ -0,0 +1,198 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/FunctionVariants.hpp" +#include "pyIterator.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +using RuntimeTableEntry = FunctionVariants::RuntimeTableEntry; +using RuntimeTable = FunctionVariants::RuntimeTable; +using FLAGS = FunctionVariants::RuntimeTableEntry::FLAGS; +using KIND = FunctionVariants::RuntimeTable::KIND; + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ cmd(m, "FunctionVariants", + R"doc( + Class representing the ``LC_FUNCTION_VARIANTS`` load command. + + Introduced publicly in ``dyld-1284.13`` (April 2025), this command supports + **function multiversioning**, the ability to associate multiple implementations + of the same function, each optimized for a specific platform, architecture, + or runtime context. + + At runtime, the system dispatches the most appropriate variant based on + hardware capabilities or execution environment. + + For example: + + .. code-block:: cpp + + FUNCTION_VARIANT_TABLE(my_function, + { (void*)my_function$Rosetta, "rosetta" }, // Rosetta translation + { (void*)my_function$Haswell, "haswell" }, // Haswell-optimized + { (void*)my_function$Base, "default" } // Default fallback + ); + )doc"_doc); + + + + nb::class_ runtime_entry(cmd, "RuntimeTableEntry", + R"doc( + This class exposes information about a given implementation. + )doc"_doc + ); + + #define FUNCTION_VARIANT_FLAG(X, _, __) .value(MachO::to_string(FLAGS::X), FLAGS::X) + nb::enum_(runtime_entry, "FLAGS") + #include "LIEF/MachO/FunctionVariants/Arm64.def" + #include "LIEF/MachO/FunctionVariants/PerProcess.def" + #include "LIEF/MachO/FunctionVariants/SystemWide.def" + #include "LIEF/MachO/FunctionVariants/X86_64.def" + .value("UNKNOWN", FLAGS::UNKNOWN) + ; + #undef FUNCTION_VARIANT_FLAG + + runtime_entry + .def_prop_rw("impl", + nb::overload_cast<>(&RuntimeTableEntry::impl, nb::const_), + nb::overload_cast(&RuntimeTableEntry::impl), + R"doc( + The relative address of the implementation or an index if + :attr:`~.another_table` is set. + )doc"_doc + ) + + .def_prop_rw("another_table", + nb::overload_cast<>(&RuntimeTableEntry::another_table, nb::const_), + nb::overload_cast(&RuntimeTableEntry::another_table), + R"doc( + Indicates whether :attr:`~.impl` refers to an entry in another runtime table, + rather than a direct function implementation address. + )doc"_doc + ) + + .def_prop_ro("flag_bit_nums", &RuntimeTableEntry::flag_bit_nums, + R"doc( + The ``flagBitNums`` value as a slice of bytes + )doc"_doc + ) + + .def_prop_ro("flags", &RuntimeTableEntry::flags, + R"doc( + Return the **interpreted** :attr:`~.flag_bit_nums` + )doc"_doc + ) + LIEF_DEFAULT_STR(RuntimeTableEntry); + + nb::class_ runtime_table(cmd, "RuntimeTable", + R"doc( + Represents a runtime table of function variants sharing a common namespace + (referred to internally as ``FunctionVariantsRuntimeTable`` in ``dyld``). + + Each table holds multiple :class:`~.RuntimeTableEntry` instances that map to + function implementations optimized for a given :class:`~.RuntimeTable.KIND`. + )doc"_doc + ); + + nb::enum_(runtime_table, "KIND", + R"doc( + Enumeration describing the namespace or category of a function variant. + + Each :class:`~.RuntimeTable` is associated with one :class:`~.RuntimeTable.KIND`, + which indicates the domain or context under which its variant entries + should be considered valid or applicable. + + These categories map to the runtime dispatch logic used by ``dyld`` + when selecting the optimal function variant. + )doc"_doc) + .value("UNKNOWN", KIND::UNKNOWN, + "Fallback/default kind when the category is not recognized"_doc + ) + + .value("PER_PROCESS", KIND::PER_PROCESS, + "Variants that apply on a per-process basis"_doc + ) + + .value("SYSTEM_WIDE", KIND::SYSTEM_WIDE, + "Variants that are selected based on system-wide capabilities or configurations"_doc + ) + + .value("ARM64", KIND::ARM64, + "Variants optimized for the ARM64 architecture."_doc + ) + + .value("X86_64", KIND::X86_64, + "Variants optimized for the x86-64 architecture."_doc + ) + ; + + init_ref_iterator(runtime_table, "it_entries"); + + runtime_table + .def_prop_ro("kind", &RuntimeTable::kind, + "Kind of the runtime table"_doc + ) + + .def_prop_ro("offset", &RuntimeTable::offset, + "Original offset in the payload"_doc + ) + + .def_prop_ro("entries", nb::overload_cast<>(&RuntimeTable::entries), + "Iterator over the different :class:`~.RuntimeTableEntry` entries"_doc, + nb::keep_alive<0, 1>() + ) + LIEF_DEFAULT_STR(RuntimeTable); + ; + + init_ref_iterator(cmd, "it_runtime_table"); + + cmd + .def_prop_rw("data_offset", + nb::overload_cast<>(&FunctionVariants::data_offset, nb::const_), + nb::overload_cast(&FunctionVariants::data_offset), + "Offset in the binary where the payload starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&FunctionVariants::data_size, nb::const_), + nb::overload_cast(&FunctionVariants::data_size), + "Size of the payload"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&FunctionVariants::content, nb::const_), + "Payload content"_doc) + + .def_prop_ro("runtime_table", nb::overload_cast<>(&FunctionVariants::runtime_table), + R"doc( + Iterator over the different :class:`~.RuntimeTable` entries located in the content + of this ``__LINKEDIT`` command + )doc"_doc, + nb::keep_alive<0, 1>() + ) + + LIEF_DEFAULT_STR(FunctionVariants); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyHeader.cpp b/vendor/lief/api/python/src/MachO/objects/pyHeader.cpp new file mode 100644 index 0000000..4e8101b --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyHeader.cpp @@ -0,0 +1,200 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "LIEF/MachO/Header.hpp" + +#include "MachO/pyMachO.hpp" + +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +template<> +void create
(nb::module_& m) { + + nb::class_ cls(m, "Header", + "Class that represents the Mach-O header"_doc); + + + enum_(cls, "CPU_TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Header::CPU_TYPE::ANY)) + .value(PY_ENUM(Header::CPU_TYPE::X86)) + .value(PY_ENUM(Header::CPU_TYPE::X86_64)) + .value(PY_ENUM(Header::CPU_TYPE::MIPS)) + .value(PY_ENUM(Header::CPU_TYPE::MC98000)) + .value(PY_ENUM(Header::CPU_TYPE::HPPA)) + .value(PY_ENUM(Header::CPU_TYPE::ARM)) + .value(PY_ENUM(Header::CPU_TYPE::ARM64)) + .value(PY_ENUM(Header::CPU_TYPE::MC88000)) + .value(PY_ENUM(Header::CPU_TYPE::SPARC)) + .value(PY_ENUM(Header::CPU_TYPE::I860)) + .value(PY_ENUM(Header::CPU_TYPE::ALPHA)) + .value(PY_ENUM(Header::CPU_TYPE::POWERPC)) + .value(PY_ENUM(Header::CPU_TYPE::POWERPC64)) + .value(PY_ENUM(Header::CPU_TYPE::APPLE_GPU)) + .value(PY_ENUM(Header::CPU_TYPE::AMD_GPU)) + .value(PY_ENUM(Header::CPU_TYPE::INTEL_GPU)) + .value(PY_ENUM(Header::CPU_TYPE::AIR64)) + #undef PY_ENUM + ; + + enum_(cls, "FILE_TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Header::FILE_TYPE::UNKNOWN)) + .value(PY_ENUM(Header::FILE_TYPE::OBJECT)) + .value(PY_ENUM(Header::FILE_TYPE::EXECUTE)) + .value(PY_ENUM(Header::FILE_TYPE::FVMLIB)) + .value(PY_ENUM(Header::FILE_TYPE::CORE)) + .value(PY_ENUM(Header::FILE_TYPE::PRELOAD)) + .value(PY_ENUM(Header::FILE_TYPE::DYLIB)) + .value(PY_ENUM(Header::FILE_TYPE::DYLINKER)) + .value(PY_ENUM(Header::FILE_TYPE::BUNDLE)) + .value(PY_ENUM(Header::FILE_TYPE::DYLIB_STUB)) + .value(PY_ENUM(Header::FILE_TYPE::DSYM)) + .value(PY_ENUM(Header::FILE_TYPE::KEXT_BUNDLE)) + .value(PY_ENUM(Header::FILE_TYPE::FILESET)) + .value(PY_ENUM(Header::FILE_TYPE::GPU_EXECUTE)) + .value(PY_ENUM(Header::FILE_TYPE::GPU_DYLIB)) + #undef PY_ENUM + ; + + enum_(cls, "FLAGS", nb::is_flag()) + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Header::FLAGS::NOUNDEFS)) + .value(PY_ENUM(Header::FLAGS::INCRLINK)) + .value(PY_ENUM(Header::FLAGS::DYLDLINK)) + .value(PY_ENUM(Header::FLAGS::BINDATLOAD)) + .value(PY_ENUM(Header::FLAGS::PREBOUND)) + .value(PY_ENUM(Header::FLAGS::SPLIT_SEGS)) + .value(PY_ENUM(Header::FLAGS::LAZY_INIT)) + .value(PY_ENUM(Header::FLAGS::TWOLEVEL)) + .value(PY_ENUM(Header::FLAGS::FORCE_FLAT)) + .value(PY_ENUM(Header::FLAGS::NOMULTIDEFS)) + .value(PY_ENUM(Header::FLAGS::NOFIXPREBINDING)) + .value(PY_ENUM(Header::FLAGS::PREBINDABLE)) + .value(PY_ENUM(Header::FLAGS::ALLMODSBOUND)) + .value(PY_ENUM(Header::FLAGS::SUBSECTIONS_VIA_SYMBOLS)) + .value(PY_ENUM(Header::FLAGS::CANONICAL)) + .value(PY_ENUM(Header::FLAGS::WEAK_DEFINES)) + .value(PY_ENUM(Header::FLAGS::BINDS_TO_WEAK)) + .value(PY_ENUM(Header::FLAGS::ALLOW_STACK_EXECUTION)) + .value(PY_ENUM(Header::FLAGS::ROOT_SAFE)) + .value(PY_ENUM(Header::FLAGS::SETUID_SAFE)) + .value(PY_ENUM(Header::FLAGS::NO_REEXPORTED_DYLIBS)) + .value(PY_ENUM(Header::FLAGS::PIE)) + .value(PY_ENUM(Header::FLAGS::DEAD_STRIPPABLE_DYLIB)) + .value(PY_ENUM(Header::FLAGS::HAS_TLV_DESCRIPTORS)) + .value(PY_ENUM(Header::FLAGS::NO_HEAP_EXECUTION)) + .value(PY_ENUM(Header::FLAGS::APP_EXTENSION_SAFE)) + .value(PY_ENUM(Header::FLAGS::NLIST_OUTOFSYNC_WITH_DYLDINFO)) + .value(PY_ENUM(Header::FLAGS::SIM_SUPPORT)) + .value(PY_ENUM(Header::FLAGS::IMPLICIT_PAGEZERO)) + .value(PY_ENUM(Header::FLAGS::DYLIB_IN_CACHE)) + #undef PY_ENUM + ; + + cls + .def(nb::init<>()) + + .def_prop_rw("magic", + nb::overload_cast<>(&Header::magic, nb::const_), + nb::overload_cast(&Header::magic), + R"delim( + The Mach-O magic bytes. These bytes determine whether it is + a 32 bits Mach-O, a 64 bits Mach-O files etc. + )delim"_doc) + + .def_prop_rw("cpu_type", + nb::overload_cast<>(&Header::cpu_type, nb::const_), + nb::overload_cast(&Header::cpu_type), + "Target CPU"_doc) + + .def_prop_rw("cpu_subtype", + nb::overload_cast<>(&Header::cpu_subtype, nb::const_), + nb::overload_cast(&Header::cpu_subtype), + R"delim( + Return the CPU subtype supported by the Mach-O binary. + For ARM architectures, this value could represent the minimum version + for which the Mach-O binary has been compiled for. + )delim"_doc) + + .def_prop_rw("file_type", + nb::overload_cast<>(&Header::file_type, nb::const_), + nb::overload_cast(&Header::file_type), + "Binary's type"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&Header::flags, nb::const_), + nb::overload_cast(&Header::flags), + "Binary's flags"_doc) + + .def_prop_rw("nb_cmds", + nb::overload_cast<>(&Header::nb_cmds, nb::const_), + nb::overload_cast(&Header::nb_cmds), + "Number of " RST_CLASS_REF(lief.MachO.LoadCommand) ""_doc) + + .def_prop_rw("sizeof_cmds", + nb::overload_cast<>(&Header::sizeof_cmds, nb::const_), + nb::overload_cast(&Header::sizeof_cmds), + "Size of all " RST_CLASS_REF(lief.MachO.LoadCommand) ""_doc) + + .def_prop_rw("reserved", + nb::overload_cast<>(&Header::reserved, nb::const_), + nb::overload_cast(&Header::reserved), + "According to the official documentation, a reserved value"_doc) + + .def_prop_ro("flags_list", + &Header::flags_list, + "" RST_CLASS_REF(lief.MachO.Header.FLAGS) " as a list"_doc) + + .def_prop_ro("is_32bit", &Header::is_32bit, + R"doc(True if the binary is 32-bits)doc"_doc) + + .def_prop_ro("is_64bit", &Header::is_64bit, + R"doc(True if the binary is 64-bits)doc"_doc) + + .def("add", + nb::overload_cast(&Header::add), + "Add the given " RST_CLASS_REF(lief.MachO.Header.FLAGS) ""_doc, + "flag"_a) + + .def("remove", + nb::overload_cast(&Header::remove), + "Remove the given " RST_CLASS_REF(lief.MachO.Header.FLAGS) ""_doc, + "flag"_a) + + .def("has", + nb::overload_cast(&Header::has, nb::const_), + "``True`` if the given " RST_CLASS_REF(lief.MachO.Header.FLAGS) " is in the " + ":attr:`~lief.MachO.Header.flags`"_doc, + "flag"_a) + + .def(nb::self += Header::FLAGS(), nb::rv_policy::reference_internal) + .def(nb::self -= Header::FLAGS(), nb::rv_policy::reference_internal) + + .def("__contains__", + nb::overload_cast(&Header::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.MachO.Header.FLAGS) " is present"_doc) + + LIEF_DEFAULT_STR(Header); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyIndirectBindingInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyIndirectBindingInfo.cpp new file mode 100644 index 0000000..01ddabf --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyIndirectBindingInfo.cpp @@ -0,0 +1,31 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/MachO/IndirectBindingInfo.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "IndirectBindingInfo", + R"delim( + This class represents a binding operation inferred from the indirect symbol + table. + )delim"_doc); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyLazyLoadDylibInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pyLazyLoadDylibInfo.cpp new file mode 100644 index 0000000..b59b6dc --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyLazyLoadDylibInfo.cpp @@ -0,0 +1,143 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "LIEF/MachO/LazyLoadDylibInfo.hpp" + +#include "pyIterator.hpp" +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +using Fixup = LazyLoadDylibInfo::Fixup; + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cmd(m, "LazyLoadDylibInfo", + R"doc( + Class representing the ``LC_LAZY_LOAD_DYLIB_INFO`` load command. + + This command describes how to **lazily load a dylib**: instead of binding + the library and its symbols at launch time, ``dyld`` keeps the information + required to resolve the dylib on the first use of one of its symbols. + )doc"_doc); + + nb::class_(cmd, "Fixup", + R"doc( + A single lazy-binding fixup decoded from the chain referenced by + :attr:`~.chain_start_image_offset` and decoded according to + :attr:`~lief.MachO.LazyLoadDylibInfo.pointer_format`. + )doc"_doc) + .def_prop_rw("address", + nb::overload_cast<>(&Fixup::address, nb::const_), + nb::overload_cast(&Fixup::address), + "Virtual address of the slot bound by this fixup"_doc) + + .def_prop_ro("ordinal", &Fixup::ordinal, + "Index of the bound symbol in " + ":attr:`~lief.MachO.LazyLoadDylibInfo.symbols`"_doc) + + .def_prop_ro("symbol", &Fixup::symbol, + "Name of the bound symbol (resolved from :attr:`~.ordinal`)"_doc) + + .def_prop_ro("is_auth", &Fixup::is_auth, + "Whether the bound pointer is authenticated (``arm64e`` PAC)"_doc) + + LIEF_DEFAULT_STR(Fixup); + + init_ref_iterator(cmd, "it_fixups"); + + cmd + .def_prop_rw("data_offset", + nb::overload_cast<>(&LazyLoadDylibInfo::data_offset, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::data_offset), + "Offset in the ``__LINKEDIT`` segment where the payload starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&LazyLoadDylibInfo::data_size, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::data_size), + "Size of the payload"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&LazyLoadDylibInfo::content, nb::const_), + "The original content of this payload"_doc) + + .def_prop_rw("load_path", + nb::overload_cast<>(&LazyLoadDylibInfo::load_path, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::load_path), + "Load path of the dylib to bind lazily"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("flag_image_offset", + nb::overload_cast<>(&LazyLoadDylibInfo::flag_image_offset, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::flag_image_offset), + "Image offset of the global flag that is set once the dylib has been loaded by dyld"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("flags", + nb::overload_cast<>(&LazyLoadDylibInfo::flags, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::flags), + "Raw flags associated with this command (see :attr:`.may_be_missing`)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("may_be_missing", + nb::overload_cast<>(&LazyLoadDylibInfo::may_be_missing, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::may_be_missing), + "Whether the dylib is allowed to be missing at runtime (weak linked)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("pointer_format", + nb::overload_cast<>(&LazyLoadDylibInfo::pointer_format, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::pointer_format), + "Chained-fixups pointer format used by the binding chain"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("chain_start_image_offset", + nb::overload_cast<>(&LazyLoadDylibInfo::chain_start_image_offset, nb::const_), + nb::overload_cast(&LazyLoadDylibInfo::chain_start_image_offset), + "Image offset of the fixup chain start used to bind the dylib's symbols"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("symbols", + nb::overload_cast<>(&LazyLoadDylibInfo::symbols, nb::const_), + nb::overload_cast>(&LazyLoadDylibInfo::symbols), + "List of the symbol names to bind lazily for this dylib"_doc, + nb::rv_policy::reference_internal) + + .def("add_symbol", &LazyLoadDylibInfo::add_symbol, + "Append a symbol name to the list of symbols to bind lazily"_doc, + "symbol"_a, nb::rv_policy::reference_internal) + + .def("clear_symbols", &LazyLoadDylibInfo::clear_symbols, + "Remove all the symbol names to bind lazily"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("fixups", nb::overload_cast<>(&LazyLoadDylibInfo::fixups), + "Iterator over the lazy-binding :class:`~.Fixup` entries decoded from " + "the chain"_doc, + nb::keep_alive<0, 1>()) + + LIEF_DEFAULT_STR(LazyLoadDylibInfo); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyLinkerOptHint.cpp b/vendor/lief/api/python/src/MachO/objects/pyLinkerOptHint.cpp new file mode 100644 index 0000000..5eec7b8 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyLinkerOptHint.cpp @@ -0,0 +1,52 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/LinkerOptHint.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "LinkerOptHint", + R"delim( + Class which represents the `LC_LINKER_OPTIMIZATION_HINT` command + )delim"_doc) + + .def_prop_rw("data_offset", + nb::overload_cast<>(&LinkerOptHint::data_offset, nb::const_), + nb::overload_cast(&LinkerOptHint::data_offset), + "Offset in the binary where the payload starts"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&LinkerOptHint::data_offset, nb::const_), + nb::overload_cast(&LinkerOptHint::data_offset), + "Size of the raw payload"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&LinkerOptHint::content, nb::const_), + "The raw payload"_doc) + + LIEF_DEFAULT_STR(LinkerOptHint); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyLoadCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyLoadCommand.cpp new file mode 100644 index 0000000..ca49eaf --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyLoadCommand.cpp @@ -0,0 +1,132 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "LIEF/MachO/LoadCommand.hpp" + +#include "MachO/pyMachO.hpp" + +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_ cls(m, "LoadCommand", + "Base class for the Mach-O load commands"_doc); + + + + enum_(cls, "TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(LoadCommand::TYPE::UNKNOWN)) + .value(PY_ENUM(LoadCommand::TYPE::SEGMENT)) + .value(PY_ENUM(LoadCommand::TYPE::SYMTAB)) + .value(PY_ENUM(LoadCommand::TYPE::SYMSEG)) + .value(PY_ENUM(LoadCommand::TYPE::THREAD)) + .value(PY_ENUM(LoadCommand::TYPE::UNIXTHREAD)) + .value(PY_ENUM(LoadCommand::TYPE::LOADFVMLIB)) + .value(PY_ENUM(LoadCommand::TYPE::IDFVMLIB)) + .value(PY_ENUM(LoadCommand::TYPE::IDENT)) + .value(PY_ENUM(LoadCommand::TYPE::FVMFILE)) + .value(PY_ENUM(LoadCommand::TYPE::PREPAGE)) + .value(PY_ENUM(LoadCommand::TYPE::DYSYMTAB)) + .value(PY_ENUM(LoadCommand::TYPE::LOAD_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::ID_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::LOAD_DYLINKER)) + .value(PY_ENUM(LoadCommand::TYPE::ID_DYLINKER)) + .value(PY_ENUM(LoadCommand::TYPE::PREBOUND_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::ROUTINES)) + .value(PY_ENUM(LoadCommand::TYPE::SUB_FRAMEWORK)) + .value(PY_ENUM(LoadCommand::TYPE::SUB_UMBRELLA)) + .value(PY_ENUM(LoadCommand::TYPE::SUB_CLIENT)) + .value(PY_ENUM(LoadCommand::TYPE::SUB_LIBRARY)) + .value(PY_ENUM(LoadCommand::TYPE::TWOLEVEL_HINTS)) + .value(PY_ENUM(LoadCommand::TYPE::PREBIND_CKSUM)) + .value(PY_ENUM(LoadCommand::TYPE::LOAD_WEAK_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::SEGMENT_64)) + .value(PY_ENUM(LoadCommand::TYPE::ROUTINES_64)) + .value(PY_ENUM(LoadCommand::TYPE::UUID)) + .value(PY_ENUM(LoadCommand::TYPE::RPATH)) + .value(PY_ENUM(LoadCommand::TYPE::CODE_SIGNATURE)) + .value(PY_ENUM(LoadCommand::TYPE::SEGMENT_SPLIT_INFO)) + .value(PY_ENUM(LoadCommand::TYPE::REEXPORT_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::LAZY_LOAD_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::ENCRYPTION_INFO)) + .value(PY_ENUM(LoadCommand::TYPE::DYLD_INFO)) + .value(PY_ENUM(LoadCommand::TYPE::DYLD_INFO_ONLY)) + .value(PY_ENUM(LoadCommand::TYPE::LOAD_UPWARD_DYLIB)) + .value(PY_ENUM(LoadCommand::TYPE::VERSION_MIN_MACOSX)) + .value(PY_ENUM(LoadCommand::TYPE::VERSION_MIN_IPHONEOS)) + .value(PY_ENUM(LoadCommand::TYPE::FUNCTION_STARTS)) + .value(PY_ENUM(LoadCommand::TYPE::DYLD_ENVIRONMENT)) + .value(PY_ENUM(LoadCommand::TYPE::MAIN)) + .value(PY_ENUM(LoadCommand::TYPE::DATA_IN_CODE)) + .value(PY_ENUM(LoadCommand::TYPE::SOURCE_VERSION)) + .value(PY_ENUM(LoadCommand::TYPE::DYLIB_CODE_SIGN_DRS)) + .value(PY_ENUM(LoadCommand::TYPE::ENCRYPTION_INFO_64)) + .value(PY_ENUM(LoadCommand::TYPE::LINKER_OPTION)) + .value(PY_ENUM(LoadCommand::TYPE::LINKER_OPTIMIZATION_HINT)) + .value(PY_ENUM(LoadCommand::TYPE::VERSION_MIN_TVOS)) + .value(PY_ENUM(LoadCommand::TYPE::VERSION_MIN_WATCHOS)) + .value(PY_ENUM(LoadCommand::TYPE::NOTE)) + .value(PY_ENUM(LoadCommand::TYPE::BUILD_VERSION)) + .value(PY_ENUM(LoadCommand::TYPE::DYLD_EXPORTS_TRIE)) + .value(PY_ENUM(LoadCommand::TYPE::DYLD_CHAINED_FIXUPS)) + .value(PY_ENUM(LoadCommand::TYPE::FILESET_ENTRY)) + .value(PY_ENUM(LoadCommand::TYPE::ATOM_INFO)) + .value(PY_ENUM(LoadCommand::TYPE::FUNCTION_VARIANTS)) + .value(PY_ENUM(LoadCommand::TYPE::FUNCTION_VARIANT_FIXUPS)) + .value(PY_ENUM(LoadCommand::TYPE::TARGET_TRIPLE)) + .value(PY_ENUM(LoadCommand::TYPE::LAZY_LOAD_DYLIB_INFO)) + .value(PY_ENUM(LoadCommand::TYPE::LIEF_UNKNOWN)) + #undef PY_ENUM + ; + + cls + .def(nb::init<>()) + + .def_prop_rw("command", + nb::overload_cast<>(&LoadCommand::command, nb::const_), + nb::overload_cast(&LoadCommand::command), + "Command type"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&LoadCommand::size, nb::const_), + nb::overload_cast(&LoadCommand::size), + "Size of the command (should be greater than ``sizeof(load_command)``)"_doc) + + .def_prop_rw("data", + nb::overload_cast<>(&LoadCommand::data, nb::const_), + nb::overload_cast(&LoadCommand::data), + "Command's data"_doc) + + .def_prop_rw("command_offset", + nb::overload_cast<>(&LoadCommand::command_offset, nb::const_), + nb::overload_cast(&LoadCommand::command_offset), + "Offset of the command within the *Load Command Table*"_doc) + + LIEF_DEFAULT_STR(LoadCommand); + + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyMainCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyMainCommand.cpp new file mode 100644 index 0000000..3371057 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyMainCommand.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/MainCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "MainCommand", + R"delim( + Class that represents the LC_MAIN command. This kind + of command can be used to determine the entrypoint of an executable + )delim"_doc) + .def(nb::init()) + + .def_prop_rw("entrypoint", + nb::overload_cast<>(&MainCommand::entrypoint, nb::const_), + nb::overload_cast(&MainCommand::entrypoint), + "Offset of the *main* function relative to the ``__TEXT`` segment"_doc) + + .def_prop_rw("stack_size", + nb::overload_cast<>(&MainCommand::stack_size, nb::const_), + nb::overload_cast(&MainCommand::stack_size), + "The initial stack size (if not 0)"_doc) + + LIEF_DEFAULT_STR(MainCommand); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyNoteCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyNoteCommand.cpp new file mode 100644 index 0000000..e50c4a8 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyNoteCommand.cpp @@ -0,0 +1,64 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "LIEF/MachO/NoteCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "NoteCommand", + R"delim( + Class that represent the ``LC_NOTE`` command. + + This command is used to include arbitrary notes or metadata within a binary. + )delim"_doc) + + .def_prop_rw("note_offset", + nb::overload_cast<>(&NoteCommand::note_offset, nb::const_), + nb::overload_cast(&NoteCommand::note_offset), + "Offset of the data associated with this note"_doc) + + .def_prop_rw("note_size", + nb::overload_cast<>(&NoteCommand::note_size, nb::const_), + nb::overload_cast(&NoteCommand::note_size), + "Size of the data referenced by the :attr:`~.note_offset`"_doc) + + .def_prop_ro("owner_str", &NoteCommand::owner_str, + "Owner as a zero-terminated string"_doc) + + .def_prop_rw("owner", + nb::overload_cast<>(&NoteCommand::owner, nb::const_), + [] (NoteCommand& self, nb::bytes owner_bytes) { + std::vector owner = to_vector(owner_bytes); + span note_owner = self.owner(); + owner.resize(note_owner.size()); + std::copy(owner.begin(), owner.end(), note_owner.begin()); + }, + "Owner of the note (e.g. ``AIR_METALLIB``)"_doc) + + LIEF_DEFAULT_STR(NoteCommand); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyParser.cpp b/vendor/lief/api/python/src/MachO/objects/pyParser.cpp new file mode 100644 index 0000000..7e36aee --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyParser.cpp @@ -0,0 +1,70 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "typing/InputParser.hpp" + +#include "LIEF/MachO/Parser.hpp" +#include "LIEF/MachO/FatBinary.hpp" + +#include "LIEF/BinaryStream/BinaryStream.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + + m.def("parse_from_memory", + nb::overload_cast(&MachO::Parser::parse_from_memory), + R"delim( + Parse the Mach-O binary from the address given in the first parameter + )delim"_doc, "address"_a, "config"_a = ParserConfig::deep(), + nb::rv_policy::take_ownership); + + m.def("parse_from_dump", + [] (typing::InputParser obj, uint64_t addr, const ParserConfig& config) { + return Parser::parse_from_dump(obj.into_stream(), addr, config); + }, + R"delim( + Parse the Mach-O binary from a memory dump given in the first parameter. + + A dump is a raw capture of the process memory that was mapped starting at + the virtual address given in the second parameter. + )delim"_doc, + "obj"_a, "addr"_a, "config"_a = ParserConfig::deep(), + nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const ParserConfig& config) -> std::unique_ptr { + return Parser::parse(obj.into_stream(), config); + }, + R"delim( + Parse the given binary from the given input and return a :class:`~lief.MachO.FatBinary` object + + One can configure the parser with the ``config`` parameter. See :class:`~lief.MachO.ParserConfig` + )delim"_doc, + "obj"_a, "config"_a = ParserConfig::deep(), + nb::rv_policy::take_ownership); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyParserConfig.cpp b/vendor/lief/api/python/src/MachO/objects/pyParserConfig.cpp new file mode 100644 index 0000000..cf36e5f --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyParserConfig.cpp @@ -0,0 +1,77 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "LIEF/MachO/ParserConfig.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "ParserConfig", + R"delim( + This class is used to tweak the MachO Parser (:class:`~lief.MachO.Parser`) + )delim"_doc) + + .def(nb::init<>()) + .def_rw("parse_dyld_exports", &ParserConfig::parse_dyld_exports, + "Parse the Dyld export trie"_doc) + + .def_rw("parse_dyld_bindings", &ParserConfig::parse_dyld_bindings, + "Parse the Dyld binding opcodes"_doc) + + .def_rw("parse_dyld_rebases", &ParserConfig::parse_dyld_rebases, + "Parse the Dyld rebase opcodes"_doc) + + .def_rw("fix_from_memory", &ParserConfig::fix_from_memory, + R"delim( + When parsing Mach-O from memory, this option + can be used to *undo* relocations and symbols bindings. + + When activated, this option requires parse_dyld_bindings + and parse_dyld_rebases to be enabled. + )delim"_doc) + + .def_rw("from_dyld_shared_cache", &ParserConfig::from_dyld_shared_cache, + R"delim( + Whether the binary is coming/extracted from Dyld shared cache + )delim"_doc) + + .def("full_dyldinfo", &ParserConfig::full_dyldinfo, + R"delim( + If ``flag`` is set to ``true``, Exports, Bindings and Rebases opcodes are parsed. + + .. warning:: + + Enabling this flag can slow down the parsing + )delim"_doc, "flag"_a) + + .def_prop_ro_static("deep", + [] (const nb::object& /* self */) { return ParserConfig::deep(); }, + R"delim( + Return a parser configuration such as all the objects supported by LIEF are parsed + )delim"_doc) + + .def_prop_ro_static("quick", + [] (const nb::object& /* self */) { return ParserConfig::quick(); }, + R"delim( + Return a configuration to parse the most important MachO structures + )delim"_doc); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRPathCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyRPathCommand.cpp new file mode 100644 index 0000000..ec23ebf --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRPathCommand.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2021 J.Rieck (based on R. Thomas's work) + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include + +#include "LIEF/MachO/hash.hpp" +#include "LIEF/MachO/RPathCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "RPathCommand") + + .def_static("create", &RPathCommand::create, + "Create a new RPathCommand for the provided ``path``"_doc, + "path"_a + ) + + .def_prop_ro("path_offset", &RPathCommand::path_offset, + "Original string offset of the path") + + .def_prop_rw("path", + nb::overload_cast<>(&RPathCommand::path, nb::const_), + nb::overload_cast(&RPathCommand::path), + "@rpath path"_doc, nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(RPathCommand); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRelocation.cpp b/vendor/lief/api/python/src/MachO/objects/pyRelocation.cpp new file mode 100644 index 0000000..3d502a1 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRelocation.cpp @@ -0,0 +1,188 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/Relocation.hpp" +#include "LIEF/MachO/DyldInfo.hpp" +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/MachO/Section.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" + +#include "MachO/pyMachO.hpp" +#include "typing.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + + +struct relocations_typing : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(relocations_typing, nb::object); + NB_OBJECT_DEFAULT(relocations_typing, object, + "Union[" + "lief.MachO.X86_RELOCATION, " + "lief.MachO.X86_64_RELOCATION, " + "lief.MachO.PPC_RELOCATION, " + "lief.MachO.ARM_RELOCATION, " + "lief.MachO.ARM64_RELOCATION, " + "lief.MachO.DyldInfo.REBASE_TYPE, " + "]", check) + + static bool check(handle) { + return true; + } +}; +} + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_ cls(m, "Relocation", + R"delim( + It extends the LIEF :class:`lief.Relocation` abstract class and it is sub-classed by + + 1. :class:`~lief.MachO.RelocationObject` + 2. :class:`~lief.MachO.RelocationDyld` + )delim"_doc); + + enum_(cls, "ORIGIN") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Relocation::ORIGIN::UNKNOWN)) + .value(PY_ENUM(Relocation::ORIGIN::DYLDINFO)) + .value(PY_ENUM(Relocation::ORIGIN::RELOC_TABLE)) + .value(PY_ENUM(Relocation::ORIGIN::CHAINED_FIXUPS)) + #undef PY_ENUM + ; + + cls + .def_prop_rw("address", + static_cast(&MachO::Relocation::address), + static_cast(&MachO::Relocation::address), + R"delim( + For :attr:`~lief.MachO.FILE_TYPES.OBJECT` or (:attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.Relocation.ORIGIN.RELOC_TABLE`) this is an + offset from the start of the :class:`~lief.MachO.Section` + to the item containing the address requiring relocation. + + For :attr:`~lief.MachO.Header.FILE_TYPE.EXECUTE` / :attr:`~lief.MachO.Header.FILE_TYPE.DYLIB` or + (:attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.Relocation.ORIGIN.DYLDINFO`) + this is a :attr:`~lief.MachO.SegmentCommand.virtual_address`. + )delim"_doc) + + .def_prop_rw("pc_relative", + nb::overload_cast<>(&Relocation::is_pc_relative, nb::const_), + nb::overload_cast(&Relocation::pc_relative), + R"delim( + Indicates whether the item containing the address to be + relocated is part of a CPU instruction that uses PC-relative addressing. + + For addresses contained in PC-relative instructions, the CPU adds the address of + the instruction to the address contained in the instruction. + )delim"_doc) + + .def_prop_rw("type", + [] (const Relocation& reloc) -> relocations_typing { + if (reloc.origin() == Relocation::ORIGIN::DYLDINFO) { + return nb::cast(DyldInfo::REBASE_TYPE(reloc.type())); + } + + if (reloc.origin() == Relocation::ORIGIN::RELOC_TABLE) { + switch (reloc.architecture()) { + case Header::CPU_TYPE::X86: + return nb::cast(X86_RELOCATION(reloc.type())); + + case Header::CPU_TYPE::X86_64: + return nb::cast(X86_64_RELOCATION(reloc.type())); + + case Header::CPU_TYPE::ARM: + return nb::cast(ARM_RELOCATION(reloc.type())); + + case Header::CPU_TYPE::ARM64: + return nb::cast(ARM64_RELOCATION(reloc.type())); + + case Header::CPU_TYPE::POWERPC: + return nb::cast(PPC_RELOCATION(reloc.type())); + + default: + return nb::cast(reloc.type()); + } + } + + return nb::cast(reloc.type()); + }, + nb::overload_cast(&Relocation::type), + R"delim( + Type of the relocation according to the :attr:`~lief.MachO.Relocation.architecture` + and/or :attr:`~lief.MachO.Relocation.origin` + + If :attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.Relocation.ORIGIN.RELOC_TABLE`: + + See: + + * :class:`lief.MachO.X86_RELOCATION` + * :class:`lief.MachO.X86_64_RELOCATION` + * :class:`lief.MachO.PPC_RELOCATION` + * :class:`lief.MachO.ARM_RELOCATION` + * :class:`lief.MachO.ARM64_RELOCATION` + + If :attr:`~lief.MachO.Relocation.origin` is :attr:`~lief.MachO.Relocation.ORIGIN.DYLDINFO`, + the value is associated with :class:`~lief.MachO.DyldInfo.REBASE_TYPE`. + )delim"_doc) + + .def_prop_ro("architecture", + &Relocation::architecture, + "" RST_CLASS_REF(lief.MachO.Header.CPU_TYPE) " of the relocation"_doc) + + .def_prop_ro("has_symbol", + &Relocation::has_symbol, + "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.Symbol) " associated with"_doc) + + .def_prop_ro("symbol", + nb::overload_cast<>(&Relocation::symbol), + "" RST_CLASS_REF(lief.MachO.Symbol) " associated with the relocation if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_section", + &Relocation::has_section, + "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.Section) " associated with"_doc) + + .def_prop_ro("section", + nb::overload_cast<>(&Relocation::section), + "" RST_CLASS_REF(lief.MachO.Section) " associated with the relocation if any, or None"_doc, + nb::rv_policy::reference_internal) + + + .def_prop_ro("origin", &Relocation::origin, + R"delim( + :class:`~lief.MachO.Relocation.ORIGIN` of the relocation + + * For :attr:`~lief.MachO.Header.FILE_TYPE.OBJECT` file it should be :attr:`~lief.MachO.Relocation.ORIGIN.RELOC_TABLE` + * For :attr:`~lief.MachO.Header.FILE_TYPE.EXECUTE` or :attr:`~lief.MachO.FILE_TYPES.DYLIB` it should be :attr:`~lief.MachO.Relocation.ORIGIN.DYLDINFO`") + )delim"_doc) + + .def_prop_ro("has_segment", &Relocation::has_segment, + "``True`` if the relocation has a " RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with"_doc) + + .def_prop_ro("segment", + nb::overload_cast<>(&Relocation::segment), + "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the relocation if any, or None"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(Relocation); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRelocationDyld.cpp b/vendor/lief/api/python/src/MachO/objects/pyRelocationDyld.cpp new file mode 100644 index 0000000..ae3810f --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRelocationDyld.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/RelocationDyld.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "RelocationDyld", + R"delim( + Class that represents a relocation found in the :class:`~lief.MachO.DyldInfo` structure. + + While this class does not have an associated structure in the Mach-O format specification, + it provides a convenient interface for the :attr:`lief.MachO.DyldInfo.rebase` values + + See also: :class:`~lief.MachO.RelocationObject` + )delim"_doc) + + .def("__le__", nb::overload_cast(&RelocationDyld::operator<=, nb::const_)) + .def("__lt__", nb::overload_cast(&RelocationDyld::operator<, nb::const_)) + .def("__ge__", nb::overload_cast(&RelocationDyld::operator>=, nb::const_)) + .def("__gt__", nb::overload_cast(&RelocationDyld::operator>, nb::const_)) + + LIEF_DEFAULT_STR(RelocationDyld); + + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRelocationFixup.cpp b/vendor/lief/api/python/src/MachO/objects/pyRelocationFixup.cpp new file mode 100644 index 0000000..d31f0a2 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRelocationFixup.cpp @@ -0,0 +1,57 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/RelocationFixup.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "RelocationFixup", + R"delim( + Class that represents a rebase relocation found in the LC_DYLD_CHAINED_FIXUPS command. + + This class extends :class:`lief.Relocation` (and :class:`lief.MachO.Relocation`) in which + :attr:`~lief.Relocation.address` is set to the absolute virtual address + where the relocation must take place (e.g. ``0x10000d270``). + + On the other hand, :attr:`~lief.MachO.RelocationFixup.target` contains the value + that should be set at :attr:`~lief.Relocation.address` if the + imagebase is :attr:`~lief.Binary.imagebase` (e.g. ``0x1000073a8``). + + If the Mach-O loader chooses another base address (like ``0x7ff100000``), it must set + ``0x10000d270`` to ``0x7ff1073a8``. + )delim"_doc) + + .def_prop_rw("target", + nb::overload_cast<>(&RelocationFixup::target, nb::const_), + nb::overload_cast(&RelocationFixup::target)) + + .def_prop_rw("next", + nb::overload_cast<>(&RelocationFixup::next, nb::const_), + nb::overload_cast(&RelocationFixup::next), + "(unscaled) next offset in the chain"_doc + ) + + LIEF_DEFAULT_STR(RelocationFixup); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRelocationObject.cpp b/vendor/lief/api/python/src/MachO/objects/pyRelocationObject.cpp new file mode 100644 index 0000000..f063682 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRelocationObject.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/RelocationObject.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "RelocationObject", + R"delim( + Class that represents a relocation present in the MachO object + file (``.o``). Usually, this kind of relocation is found in the :class:`lief.MachO.Section`. + )delim"_doc) + + .def_prop_rw("value", + nb::overload_cast<>(&RelocationObject::value, nb::const_), + nb::overload_cast(&RelocationObject::value), + R"delim( + For **scattered** relocations, the address of the relocatable expression + for the item in the file that needs to be updated if the address is changed. + + For relocatable expressions with the difference of two section addresses, + the address from which to subtract (in mathematical terms, the minuend) + is contained in the first relocation entry and the address to subtract (the subtrahend) + is contained in the second relocation entry.", + )delim"_doc) + + + .def_prop_ro("is_scattered", &RelocationObject::is_scattered, + "``True`` if the relocation is a scattered one"_doc) + + LIEF_DEFAULT_STR(RelocationObject); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyRoutine.cpp b/vendor/lief/api/python/src/MachO/objects/pyRoutine.cpp new file mode 100644 index 0000000..1086a4e --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyRoutine.cpp @@ -0,0 +1,79 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include + +#include "LIEF/MachO/Routine.hpp" + +#include "MachO/pyMachO.hpp" + +#include "nanobind/stl/string.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "Routine", + R"delim( + Class that represents the ``LC_ROUTINE/LC_ROUTINE64`` commands. + According to the Mach-O ``loader.h`` documentation: + + The routines command contains the address of the dynamic shared library + initialization routine and an index into the module table for the module + that defines the routine. Before any modules are used from the library the + dynamic linker fully binds the module that defines the initialization routine + and then calls it. This gets called before any module initialization + routines (used for C++ static constructors) in the library. + )delim"_doc) + + .def_prop_rw("init_address", + nb::overload_cast<>(&Routine::init_address, nb::const_), + nb::overload_cast(&Routine::init_address), + "Address of initialization routine"_doc) + + .def_prop_rw("init_module", + nb::overload_cast<>(&Routine::init_module, nb::const_), + nb::overload_cast(&Routine::init_module), + "Index into the module table that the init routine is defined in"_doc) + + .def_prop_rw("reserved1", + nb::overload_cast<>(&Routine::reserved1, nb::const_), + nb::overload_cast(&Routine::reserved1)) + + .def_prop_rw("reserved2", + nb::overload_cast<>(&Routine::reserved2, nb::const_), + nb::overload_cast(&Routine::reserved2)) + + .def_prop_rw("reserved3", + nb::overload_cast<>(&Routine::reserved3, nb::const_), + nb::overload_cast(&Routine::reserved3)) + + .def_prop_rw("reserved4", + nb::overload_cast<>(&Routine::reserved4, nb::const_), + nb::overload_cast(&Routine::reserved4)) + + .def_prop_rw("reserved5", + nb::overload_cast<>(&Routine::reserved5, nb::const_), + nb::overload_cast(&Routine::reserved5)) + + .def_prop_rw("reserved6", + nb::overload_cast<>(&Routine::reserved6, nb::const_), + nb::overload_cast(&Routine::reserved6)) + + LIEF_DEFAULT_STR(Routine); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySection.cpp b/vendor/lief/api/python/src/MachO/objects/pySection.cpp new file mode 100644 index 0000000..a3b5db8 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySection.cpp @@ -0,0 +1,201 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "LIEF/MachO/Section.hpp" +#include "LIEF/MachO/Relocation.hpp" +#include "LIEF/MachO/SegmentCommand.hpp" + +#include "MachO/pyMachO.hpp" +#include "pyIterator.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + + +// (rtti)Trick to avoid duplication clash with SegmentCommand::it_relocations +class section_it_relocations : public Section::it_relocations { + public: + using Section::it_relocations::it_relocations; +}; + +template<> +void create
(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ sec(m, "Section", + "Class that represents a Mach-O section"_doc); + + init_ref_iterator(sec, "it_relocations"); + + enum_(sec, "TYPE") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Section::TYPE::REGULAR)) + .value(PY_ENUM(Section::TYPE::ZEROFILL)) + .value(PY_ENUM(Section::TYPE::CSTRING_LITERALS)) + .value(PY_ENUM(Section::TYPE::IS_4BYTE_LITERALS)) + .value(PY_ENUM(Section::TYPE::IS_8BYTE_LITERALS)) + .value(PY_ENUM(Section::TYPE::LITERAL_POINTERS)) + .value(PY_ENUM(Section::TYPE::NON_LAZY_SYMBOL_POINTERS)) + .value(PY_ENUM(Section::TYPE::LAZY_SYMBOL_POINTERS)) + .value(PY_ENUM(Section::TYPE::SYMBOL_STUBS)) + .value(PY_ENUM(Section::TYPE::MOD_INIT_FUNC_POINTERS)) + .value(PY_ENUM(Section::TYPE::MOD_TERM_FUNC_POINTERS)) + .value(PY_ENUM(Section::TYPE::COALESCED)) + .value(PY_ENUM(Section::TYPE::GB_ZEROFILL)) + .value(PY_ENUM(Section::TYPE::INTERPOSING)) + .value(PY_ENUM(Section::TYPE::IS_16BYTE_LITERALS)) + .value(PY_ENUM(Section::TYPE::DTRACE_DOF)) + .value(PY_ENUM(Section::TYPE::LAZY_DYLIB_SYMBOL_POINTERS)) + .value(PY_ENUM(Section::TYPE::THREAD_LOCAL_REGULAR)) + .value(PY_ENUM(Section::TYPE::THREAD_LOCAL_ZEROFILL)) + .value(PY_ENUM(Section::TYPE::THREAD_LOCAL_VARIABLES)) + .value(PY_ENUM(Section::TYPE::THREAD_LOCAL_VARIABLE_POINTERS)) + .value(PY_ENUM(Section::TYPE::THREAD_LOCAL_INIT_FUNCTION_POINTERS)) + .value(PY_ENUM(Section::TYPE::INIT_FUNC_OFFSETS)) + #undef PY_ENUM + ; + + enum_(sec, "FLAGS", nb::is_flag()) + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(Section::FLAGS::PURE_INSTRUCTIONS)) + .value(PY_ENUM(Section::FLAGS::NO_TOC)) + .value(PY_ENUM(Section::FLAGS::STRIP_STATIC_SYMS)) + .value(PY_ENUM(Section::FLAGS::NO_DEAD_STRIP)) + .value(PY_ENUM(Section::FLAGS::LIVE_SUPPORT)) + .value(PY_ENUM(Section::FLAGS::SELF_MODIFYING_CODE)) + .value(PY_ENUM(Section::FLAGS::DEBUG_INFO)) + .value(PY_ENUM(Section::FLAGS::SOME_INSTRUCTIONS)) + .value(PY_ENUM(Section::FLAGS::EXT_RELOC)) + .value(PY_ENUM(Section::FLAGS::LOC_RELOC)) + #undef PY_ENUM + ; + + sec + .def_static("create", + nb::overload_cast(&Section::create), + "Create a section with the given name, content and type", + "name"_a, "content"_a, "type"_a = Section::TYPE::REGULAR) + + .def_static("create", + nb::overload_cast(&Section::create), + "Create a section with the given name", + "name"_a, "type"_a = Section::TYPE::REGULAR) + + .def_prop_rw("alignment", + nb::overload_cast<>(&Section::alignment, nb::const_), + nb::overload_cast(&Section::alignment), + "Section's alignment as a power of 2"_doc) + + .def_prop_rw("relocation_offset", + nb::overload_cast<>(&Section::relocation_offset, nb::const_), + nb::overload_cast(&Section::relocation_offset), + R"delim( + Offset of the relocation table. This value should be 0 + for executable and libraries as the relocations are managed by the :attr:`lief.MachO.DyldInfo.rebase` + + On the other hand, for object files (``.o``) this value should not be 0 + )delim"_doc) + + .def_prop_rw("numberof_relocations", + nb::overload_cast<>(&Section::numberof_relocations, nb::const_), + nb::overload_cast(&Section::numberof_relocations), + "Number of relocations associated with this section"_doc) + + .def_prop_rw("type", + nb::overload_cast<>(&Section::type, nb::const_), + nb::overload_cast(&Section::type), + R"delim( + Type of the section. This value can help to determine + the purpose of the section (c.f. :class:`~lief.MachO.Section.TYPE`) + )delim"_doc) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Section::relocations), + "Iterator over the " RST_CLASS_REF(lief.MachO.Relocation) " (if any)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("reserved1", + nb::overload_cast<>(&Section::reserved1, nb::const_), + nb::overload_cast(&Section::reserved1), + "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*"_doc) + + .def_prop_rw("reserved2", + nb::overload_cast<>(&Section::reserved2, nb::const_), + nb::overload_cast(&Section::reserved2), + "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*"_doc) + + .def_prop_rw("reserved3", + nb::overload_cast<>(&Section::reserved3, nb::const_), + nb::overload_cast(&Section::reserved3), + "According to the official ``loader.h`` file, this value is reserved for *offset* or *index*"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&Section::flags, nb::const_), + nb::overload_cast(&Section::flags), + "Section's flags masked with SECTION_FLAGS_MASK (see: :class:`~lief.MachO.Section.FLAGS`)"_doc) + + .def_prop_ro("flags_list", + nb::overload_cast<>(&Section::flags_list, nb::const_), + nb::rv_policy::reference_internal) + + .def_prop_ro("segment", + nb::overload_cast<>(&Section::segment), + "" RST_CLASS_REF(lief.MachO.SegmentCommand) " associated with the section or None if not present"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_rw("segment_name", + nb::overload_cast<>(&Section::segment_name, nb::const_), + nb::overload_cast(&Section::segment_name), + R"delim(The segment name associated with the section)delim"_doc) + + .def_prop_ro("has_segment", &Section::has_segment, + "True if the current section has a segment associated with"_doc) + + .def("has", + nb::overload_cast(&Section::has, nb::const_), + "Check if the section has the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) ""_doc, + "flag"_a) + + .def("add", + nb::overload_cast(&Section::add), + "Add the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) ""_doc, + "flag"_a) + + .def("remove", + nb::overload_cast(&Section::remove), + "Remove the given " RST_CLASS_REF(lief.MachO.SECTION_FLAGS) ""_doc, + "flag"_a) + + .def(nb::self += Section::FLAGS(), nb::rv_policy::reference_internal) + .def(nb::self -= Section::FLAGS(), nb::rv_policy::reference_internal) + + .def("__contains__", + nb::overload_cast(&Section::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.MachO.MACHO_SECTION_FLAGS) " is present"_doc) + + LIEF_DEFAULT_STR(Section); + +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySegmentCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pySegmentCommand.cpp new file mode 100644 index 0000000..3f72805 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySegmentCommand.cpp @@ -0,0 +1,169 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "MachO/pyMachO.hpp" +#include "pyIterator.hpp" +#include "pySafeString.hpp" +#include "nanobind/extra/stl/lief_span.h" + +#include "LIEF/MachO/SegmentCommand.hpp" +#include "LIEF/MachO/Section.hpp" +#include "LIEF/MachO/Relocation.hpp" +#include "LIEF/MachO/LinkEdit.hpp" + +#include +#include +#include +#include + +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + + nb::class_ seg_cmd(m, "SegmentCommand", + R"delim( + Class which represents a :attr:`~.LoadCommand.TYPE.SEGMENT` / + :attr:`~.LoadCommand.TYPE.SEGMENT_64` command + )delim"_doc); + + init_ref_iterator(seg_cmd, "it_sections"); + + try { + /* + * it_relocations could be already registered by the Section + */ + init_ref_iterator(seg_cmd, "it_relocations"); + } catch (const std::runtime_error&) { } + + enum_(seg_cmd, "VM_PROTECTIONS") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(SegmentCommand::VM_PROTECTIONS::READ)) + .value(PY_ENUM(SegmentCommand::VM_PROTECTIONS::WRITE)) + .value(PY_ENUM(SegmentCommand::VM_PROTECTIONS::EXECUTE)) + #undef PY_ENUM + ; + + enum_(seg_cmd, "FLAGS") + #define PY_ENUM(x) to_string(x), x + .value(PY_ENUM(SegmentCommand::FLAGS::HIGHVM)) + .value(PY_ENUM(SegmentCommand::FLAGS::FVMLIB)) + .value(PY_ENUM(SegmentCommand::FLAGS::NORELOC)) + .value(PY_ENUM(SegmentCommand::FLAGS::PROTECTED_VERSION_1)) + .value(PY_ENUM(SegmentCommand::FLAGS::READ_ONLY)) + #undef PY_ENUM + ; + + seg_cmd + .def(nb::init<>()) + .def(nb::init()) + .def(nb::init()) + + .def_prop_rw("name", + [] (const SegmentCommand& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&SegmentCommand::name), + "Segment's name"_doc) + + .def_prop_rw("virtual_address", + nb::overload_cast<>(&SegmentCommand::virtual_address, nb::const_), + nb::overload_cast(&SegmentCommand::virtual_address), + "Segment's virtual address"_doc) + + .def_prop_rw("virtual_size", + nb::overload_cast<>(&SegmentCommand::virtual_size, nb::const_), + nb::overload_cast(&SegmentCommand::virtual_size), + "Segment's virtual size"_doc) + + .def_prop_rw("file_size", + nb::overload_cast<>(&SegmentCommand::file_size, nb::const_), + nb::overload_cast(&SegmentCommand::file_size), + "Segment's file size"_doc) + + .def_prop_rw("file_offset", + nb::overload_cast<>(&SegmentCommand::file_offset, nb::const_), + nb::overload_cast(&SegmentCommand::file_offset), + "Segment's file offset"_doc) + + .def_prop_rw("max_protection", + nb::overload_cast<>(&SegmentCommand::max_protection, nb::const_), + nb::overload_cast(&SegmentCommand::max_protection), + "Segment's max protection"_doc) + + .def_prop_rw("init_protection", + nb::overload_cast<>(&SegmentCommand::init_protection, nb::const_), + nb::overload_cast(&SegmentCommand::init_protection), + "Segment's initial protection"_doc) + + .def_prop_rw("numberof_sections", + nb::overload_cast<>(&SegmentCommand::numberof_sections, nb::const_), + nb::overload_cast(&SegmentCommand::numberof_sections), + "Number of sections in this segment"_doc) + + .def_prop_ro("sections", nb::overload_cast<>(&SegmentCommand::sections), + "Segment's sections"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("relocations", + nb::overload_cast<>(&SegmentCommand::relocations), + "Segment's relocations"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("index", &SegmentCommand::index, + "Relative index of the segment in the segment table"_doc) + + .def_prop_rw("content", + nb::overload_cast<>(&SegmentCommand::content, nb::const_), + nb::overload_cast(&SegmentCommand::content), + "Segment's content"_doc) + + .def_prop_rw("flags", + nb::overload_cast<>(&SegmentCommand::flags, nb::const_), + nb::overload_cast(&SegmentCommand::flags), + "Segment's flags"_doc) + + .def("has", + nb::overload_cast(&SegmentCommand::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.MachO.Section) " belongs to the current segment"_doc, + "section"_a) + + .def("has_section", + nb::overload_cast(&SegmentCommand::has_section, nb::const_), + "Check if the given section name belongs to the current segment"_doc, + "section_name"_a) + + .def("add_section", + nb::overload_cast(&SegmentCommand::add_section), + "section"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("get_section", + nb::overload_cast(&SegmentCommand::get_section), + R"delim( + Get the :class:`~lief.MachO.Section` with the given name + )delim"_doc, "name"_a, nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(SegmentCommand); + nb::class_(m, "LinkEdit"); +} +} + + diff --git a/vendor/lief/api/python/src/MachO/objects/pySegmentSplitInfo.cpp b/vendor/lief/api/python/src/MachO/objects/pySegmentSplitInfo.cpp new file mode 100644 index 0000000..6824aeb --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySegmentSplitInfo.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/SegmentSplitInfo.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "SegmentSplitInfo", + "Class that represents the :attr:`~.LoadCommand.TYPE.SEGMENT_SPLIT_INFO` command"_doc) + + .def_prop_rw("data_offset", + nb::overload_cast<>(&SegmentSplitInfo::data_offset, nb::const_), + nb::overload_cast(&SegmentSplitInfo::data_offset), + "Offset in the binary where the data start"_doc) + + .def_prop_rw("data_size", + nb::overload_cast<>(&SegmentSplitInfo::data_size, nb::const_), + nb::overload_cast(&SegmentSplitInfo::data_size), + "Size of the raw data"_doc) + + .def_prop_ro("content", + nb::overload_cast<>(&SegmentSplitInfo::content, nb::const_), + "The original content as a bytes stream"_doc) + + LIEF_DEFAULT_STR(SegmentSplitInfo); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySourceVersion.cpp b/vendor/lief/api/python/src/MachO/objects/pySourceVersion.cpp new file mode 100644 index 0000000..74205c7 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySourceVersion.cpp @@ -0,0 +1,45 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/SourceVersion.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "SourceVersion", + R"delim( + Class that represents the MachO :attr:`~.LoadCommand.TYPE.SOURCE_VERSION` + This command is used to provide the *version* of the sources used to build the binary + )delim"_doc) + + .def_prop_rw("version", + nb::overload_cast<>(&SourceVersion::version, nb::const_), + nb::overload_cast(&SourceVersion::version), + "Version as a tuple of **5** integers"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(SourceVersion); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyStub.cpp b/vendor/lief/api/python/src/MachO/objects/pyStub.cpp new file mode 100644 index 0000000..0c521be --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyStub.cpp @@ -0,0 +1,93 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "LIEF/MachO/Stub.hpp" + +#include "nanobind/utils.hpp" +#include +#include +#include + +#include "MachO/pyMachO.hpp" + +#include "pyLIEF.hpp" +#include "pyErr.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + nb::class_ object(m, "Stub", + R"doc( + This class represents a stub entry in sections like ``__stubs,__auth_stubs``. + + It wraps assembly instructions which are used to access the *got* where the + address of the symbol is resolved. + + Example: + + .. code-block:: text + + 0000000236a3c1bc: ___memcpy_chk + adrp x17, #0x241513aa8 + add x17, x17, #0x241513aa8 + ldr x16, [x17] + braa x16, x17 + )doc"_doc + ); + + nb::class_(object, "target_info_t") + .def(nb::init<>()) + .def(nb::init()) + .def_rw("arch", &Stub::target_info_t::arch) + .def_rw("subtype", &Stub::target_info_t::subtype); + + object + .def(nb::init>(), + "target_info"_a, "address"_a, "raw_stub"_a + ) + .def_prop_ro("address", &Stub::address, + "The virtual address where the stub is located"_doc + ) + .def_prop_ro("raw", + nb::overload_cast<>(&Stub::raw, nb::const_), + "The (raw) instructions of this entry as a memory view of bytes"_doc) + + .def_prop_ro("target", + [] (Stub& self) { + return LIEF::py::error_or(&Stub::target, self); + }, + R"doc( + The address resolved by this stub. + + For instance, given this stub: + + .. code-block:: + + 0x3eec: adrp x16, #4096 + 0x3ef0: ldr x16, [x16, #24] + 0x3ef4: br x16 + + The function returns: ``0x4018``. + + .. warning:: + + This function is only available with LIEF's extended version + )doc"_doc) + + LIEF_DEFAULT_STR(Stub); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySubClient.cpp b/vendor/lief/api/python/src/MachO/objects/pySubClient.cpp new file mode 100644 index 0000000..56fa18a --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySubClient.cpp @@ -0,0 +1,51 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/SubClient.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "SubClient", + R"delim( + Class that represents the SubClient command. + According to the Mach-O ``loader.h`` documentation: + + > For dynamically linked shared libraries that are subframework of an umbrella + > framework they can allow clients other than the umbrella framework or other + > subframeworks in the same umbrella framework. To do this the subframework + > is built with "-allowable_client client_name" and an LC_SUB_CLIENT load + > command is created for each -allowable_client flag. The client_name is + > usually a framework name. It can also be a name used for bundles clients + > where the bundle is built with "-client_name client_name". + )delim"_doc) + + .def_prop_rw("client", + nb::overload_cast<>(&SubClient::client, nb::const_), + nb::overload_cast(&SubClient::client), + "Name of the sub client"_doc) + + LIEF_DEFAULT_STR(SubClient); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySubFramework.cpp b/vendor/lief/api/python/src/MachO/objects/pySubFramework.cpp new file mode 100644 index 0000000..66edaa1 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySubFramework.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/SubFramework.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "SubFramework", + R"delim( + Class that represents the SubFramework command. + According to the Mach-O ``loader.h`` documentation: + + + > A dynamically linked shared library may be a subframework of an umbrella + > framework. If so it will be linked with "-umbrella umbrella_name" where + > Where "umbrella_name" is the name of the umbrella framework. A subframework + > can only be linked against by its umbrella framework or other subframeworks + > that are part of the same umbrella framework. Otherwise the static link + > editor produces an error and states to link against the umbrella framework. + > The name of the umbrella framework for subframeworks is recorded in the + > following structure. + )delim"_doc) + + .def_prop_rw("umbrella", + nb::overload_cast<>(&SubFramework::umbrella, nb::const_), + nb::overload_cast(&SubFramework::umbrella), + "Name of the umbrella framework"_doc) + + LIEF_DEFAULT_STR(SubFramework); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySymbol.cpp b/vendor/lief/api/python/src/MachO/objects/pySymbol.cpp new file mode 100644 index 0000000..5e20e06 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySymbol.cpp @@ -0,0 +1,143 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/Section.hpp" +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/MachO/BindingInfo.hpp" +#include "LIEF/MachO/ExportInfo.hpp" +#include "LIEF/MachO/DylibCommand.hpp" + +#include "pyIterator.hpp" +#include "MachO/pyMachO.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_ symbol(m, "Symbol", + R"delim( + Class that represents a Symbol in a Mach-O file. + + A Mach-O symbol can come from: + + 1. The symbols command (LC_SYMTAB / SymbolCommand) + 2. The Dyld Export trie + 3. The Dyld Symbol bindings + )delim"_doc); + + enum_(symbol, "CATEGORY") + .value("NONE", Symbol::CATEGORY::NONE) + .value("LOCAL", Symbol::CATEGORY::LOCAL) + .value("EXTERNAL", Symbol::CATEGORY::EXTERNAL) + .value("UNDEFINED", Symbol::CATEGORY::UNDEFINED) + .value("INDIRECT_ABS", Symbol::CATEGORY::INDIRECT_ABS) + .value("INDIRECT_LOCAL", Symbol::CATEGORY::INDIRECT_LOCAL) + .value("INDIRECT_ABS_LOCAL", Symbol::CATEGORY::INDIRECT_ABS_LOCAL) + ; + + enum_(symbol, "ORIGIN") + .value("UNKNOWN", Symbol::ORIGIN::UNKNOWN) + .value("DYLD_EXPORT", Symbol::ORIGIN::DYLD_EXPORT) + .value("DYLD_BIND", Symbol::ORIGIN::DYLD_BIND) + .value("SYMTAB", Symbol::ORIGIN::SYMTAB) + ; + + enum_(symbol, "TYPE") + .value("UNDEFINED", Symbol::TYPE::UNDEFINED) + .value("ABSOLUTE_SYM", Symbol::TYPE::ABSOLUTE_SYM) + .value("SECTION", Symbol::TYPE::SECTION) + .value("PREBOUND", Symbol::TYPE::PREBOUND) + .value("INDIRECT", Symbol::TYPE::INDIRECT) + ; + symbol + .def(nb::init<>()) + + .def_prop_ro("demangled_name", + &Symbol::demangled_name, + "Symbol's unmangled name"_doc) + + .def_prop_ro("category", + &Symbol::category, + "Category of the symbol according to the `LC_DYSYMTAB` command"_doc) + + .def_prop_rw("raw_type", + nb::overload_cast<>(&Symbol::raw_type, nb::const_), + nb::overload_cast(&Symbol::raw_type), + R"doc( + Raw value of ``nlist_xx.n_type`` + )doc"_doc + ) + + .def_prop_ro("type", + nb::overload_cast<>(&Symbol::type, nb::const_), + R"doc( + Type as defined by ``nlist_xx.n_type & N_TYPE`` + )doc"_doc) + + .def_prop_rw("numberof_sections", + nb::overload_cast<>(&Symbol::numberof_sections, nb::const_), + nb::overload_cast(&Symbol::numberof_sections), + R"delim( + It returns the number of sections in which this symbol can be found. + If the symbol can't be found in any section, it returns 0 (NO_SECT) + )delim"_doc) + + .def_prop_rw("description", + nb::overload_cast<>(&Symbol::description, nb::const_), + nb::overload_cast(&Symbol::description), + "Return information about the symbol"_doc) + + .def_prop_ro("has_export_info", + &Symbol::has_export_info, + "``True`` if the symbol has an " RST_CLASS_REF(lief.MachO.ExportInfo) " associated with"_doc) + + .def_prop_ro("origin", + &Symbol::origin, + "Return the " RST_CLASS_REF(lief.MachO.Symbol.ORIGIN) " of this symbol"_doc) + + .def_prop_ro("export_info", + nb::overload_cast<>(&Symbol::export_info), + "" RST_CLASS_REF(lief.MachO.ExportInfo) " associated with the symbol if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_binding_info", + &Symbol::has_binding_info, + "``True`` if the symbol has an " RST_CLASS_REF(lief.MachO.BindingInfo) " associated with"_doc) + + .def_prop_ro("binding_info", + nb::overload_cast<>(&Symbol::binding_info), + "" RST_CLASS_REF(lief.MachO.BindingInfo) " associated with the symbol if any, or None"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("library", + nb::overload_cast<>(&Symbol::library), + "" RST_CLASS_REF(lief.MachO.DylibCommand) " the library where the symbol is exposed"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("is_external", &Symbol::is_external, + "True if the symbol is defined as an external symbol."_doc) + + .def_prop_ro("library_ordinal", &Symbol::library_ordinal, + "Library ordinal + 1 (0 means self)"_doc) + + LIEF_DEFAULT_STR(Symbol); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pySymbolCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pySymbolCommand.cpp new file mode 100644 index 0000000..3f2b5b3 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pySymbolCommand.cpp @@ -0,0 +1,57 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/SymbolCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "SymbolCommand", + R"delim(Class that represents the LC_SYMTAB command)delim"_doc) + .def(nb::init<>()) + + .def_prop_rw("symbol_offset", + nb::overload_cast<>(&SymbolCommand::symbol_offset, nb::const_), + nb::overload_cast(&SymbolCommand::symbol_offset), + "Offset from the start of the file to the n_list associated with the command"_doc) + + .def_prop_rw("numberof_symbols", + nb::overload_cast<>(&SymbolCommand::numberof_symbols, nb::const_), + nb::overload_cast(&SymbolCommand::numberof_symbols), + "Number of symbols registered"_doc) + + .def_prop_rw("strings_offset", + nb::overload_cast<>(&SymbolCommand::strings_offset, nb::const_), + nb::overload_cast(&SymbolCommand::strings_offset), + "Offset from the start of the file to the string table"_doc) + + .def_prop_rw("strings_size", + nb::overload_cast<>(&SymbolCommand::strings_size, nb::const_), + nb::overload_cast(&SymbolCommand::strings_size), + "Size of the string table"_doc) + + LIEF_DEFAULT_STR(SymbolCommand); +} +} + + diff --git a/vendor/lief/api/python/src/MachO/objects/pyThreadCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyThreadCommand.cpp new file mode 100644 index 0000000..5121f3f --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyThreadCommand.cpp @@ -0,0 +1,90 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include "nanobind/utils.hpp" + +#include "LIEF/MachO/ThreadCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "ThreadCommand", + R"delim( + Class that represents the LC_THREAD / LC_UNIXTHREAD commands and that + can be used to get the binary entrypoint when the LC_MAIN (MainCommand) is not present + + Generally speaking, this command aims at defining the original state + of the main thread which includes the registers' values + )delim"_doc) + .def(nb::init()) + + .def_prop_rw("flavor", + nb::overload_cast<>(&ThreadCommand::flavor, nb::const_), + nb::overload_cast(&ThreadCommand::flavor), + R"delim( + Integer that defines a special *flavor* for the thread. + + The meaning of this value depends on the :attr:`~lief.MachO.ThreadCommand.architecture`. + The list of the values can be found in the XNU kernel files: + + - xnu/osfmk/mach/arm/thread_status.h for the ARM/AArch64 architectures + - xnu/osfmk/mach/i386/thread_status.h for the x86/x86-64 architectures + )delim"_doc) + + + .def_prop_rw("state", + nb::overload_cast<>(&ThreadCommand::state, nb::const_), + nb::overload_cast>(&ThreadCommand::state), + R"delim( + The actual thread state as a vector of bytes. Depending on the architecture(), + these data can be casted into x86_thread_state_t, x86_thread_state64_t, ... + )delim"_doc) + + + .def_prop_rw("count", + nb::overload_cast<>(&ThreadCommand::count, nb::const_), + nb::overload_cast(&ThreadCommand::count), + R"delim( + Size of the thread state data with 32-bits alignment. + + This value should match len(:attr:`~lief.MachO.ThreadCommand.state`) + )delim"_doc) + + .def_prop_ro("pc", + nb::overload_cast<>(&ThreadCommand::pc, nb::const_), + R"delim( + Return the initial Program Counter regardless of the underlying architecture. + This value, when non null, can be used to determine the binary's entrypoint. + + Underneath, it works by looking for the PC register value in the :attr:`~lief.MachO.ThreadCommand.state` data + )delim"_doc) + + .def_prop_rw("architecture", + nb::overload_cast<>(&ThreadCommand::architecture, nb::const_), + nb::overload_cast(&ThreadCommand::architecture), + "The CPU architecture that is targeted by this ThreadCommand"_doc) + + LIEF_DEFAULT_STR(ThreadCommand); +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyThreadLocalVariables.cpp b/vendor/lief/api/python/src/MachO/objects/pyThreadLocalVariables.cpp new file mode 100644 index 0000000..c279f9b --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyThreadLocalVariables.cpp @@ -0,0 +1,102 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "LIEF/MachO/ThreadLocalVariables.hpp" +#include "LIEF/MachO/Section.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/random_access_iterator.hpp" +#include + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cls(m, "ThreadLocalVariables", + R"doc( + This class represents a MachO section whose type is + :attr:`~lief.MachO.Section.TYPE.THREAD_LOCAL_VARIABLES`. + + It contains an array of thread-local variable descriptors + (:class:`~.ThreadLocalVariables.Thunk`) used by dyld to lazily initialize + thread-local storage on first access. + )doc"_doc); + + nb::class_ thunk(cls, "Thunk", + R"doc( + Descriptor for a single thread-local variable. + + The layout mirrors the ``tlv_descriptor`` structure from ````. + )doc"_doc); + + thunk + .def(nb::init<>()) + .def(nb::init(), + "func"_a, "key"_a, "offset"_a) + .def_rw("func", &ThreadLocalVariables::Thunk::func, + "Address of the initializer function (``tlv_thunk``)"_doc) + .def_rw("key", &ThreadLocalVariables::Thunk::key, + "``pthread_key_t`` key used by the runtime"_doc) + .def_rw("offset", &ThreadLocalVariables::Thunk::offset, + "Offset of the variable in the TLS block"_doc) + .def("__str__", &ThreadLocalVariables::Thunk::to_string); + + cls + .def_prop_ro("thunks", + [] (const ThreadLocalVariables& self) { + auto range = self.thunks(); + return nb::make_random_access_iterator( + nb::type(), "thunks_it", range + ); + }, + R"doc( + Return an iterator over the :class:`~.ThreadLocalVariables.Thunk` + descriptors stored in this section. + )doc"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("nb_thunks", &ThreadLocalVariables::nb_thunks, + "Number of :class:`~.ThreadLocalVariables.Thunk` descriptors"_doc) + + .def("get", &ThreadLocalVariables::get, + R"doc( + Return the :class:`~.ThreadLocalVariables.Thunk` at the given index, or + None if the index is out of range. + )doc"_doc, "idx"_a) + + .def("set", &ThreadLocalVariables::set, + R"doc( + Change the :class:`~.ThreadLocalVariables.Thunk` at the given index. + )doc"_doc, "idx"_a, "thunk"_a) + + .def("__getitem__", + nb::overload_cast(&ThreadLocalVariables::operator[], nb::const_), + R"doc( + Return the :class:`~.ThreadLocalVariables.Thunk` at the given index, or + None if the index is out of range. + )doc"_doc, "idx"_a) + + .def("__setitem__", + nb::overload_cast(&ThreadLocalVariables::set), + R"doc( + Change the :class:`~.ThreadLocalVariables.Thunk` at the given index. + )doc"_doc, "idx"_a, "thunk"_a); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyTwoLevelHints.cpp b/vendor/lief/api/python/src/MachO/objects/pyTwoLevelHints.cpp new file mode 100644 index 0000000..514575d --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyTwoLevelHints.cpp @@ -0,0 +1,45 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "LIEF/MachO/TwoLevelHints.hpp" + +#include "MachO/pyMachO.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "pyIterator.hpp" + +namespace LIEF::MachO::py { +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cmd(m, "TwoLevelHints", + R"delim(Class which represents the `LC_TWOLEVEL_HINTS` command)delim"_doc); + + init_ref_iterator(cmd, "it_hints_t"); + + cmd + .def_prop_ro("hints", nb::overload_cast<>(&TwoLevelHints::hints)) + .def_prop_ro("content", + nb::overload_cast<>(&TwoLevelHints::content, nb::const_), + "The original content as a bytes stream"_doc) + + LIEF_DEFAULT_STR(TwoLevelHints); + +} +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyUUID.cpp b/vendor/lief/api/python/src/MachO/objects/pyUUID.cpp new file mode 100644 index 0000000..f3e87b4 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyUUID.cpp @@ -0,0 +1,47 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/UUIDCommand.hpp" + +#include "MachO/pyMachO.hpp" + +#ifdef uuid_t +#pragma message("Windows #define uuid_t, undefine it for this file.") +#undef uuid_t +#endif + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "UUIDCommand", + "Class that represents the UUID command"_doc) + + .def_prop_rw("uuid", + nb::overload_cast<>(&UUIDCommand::uuid, nb::const_), + nb::overload_cast(&UUIDCommand::uuid), + "UUID as a list"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(UUIDCommand); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyUnknownCommand.cpp b/vendor/lief/api/python/src/MachO/objects/pyUnknownCommand.cpp new file mode 100644 index 0000000..e8d564f --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyUnknownCommand.cpp @@ -0,0 +1,39 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/UnknownCommand.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "UnknownCommand", + "Generic class when the command is not recognized by LIEF"_doc) + + .def_prop_ro("original_command", + nb::overload_cast<>(&UnknownCommand::original_command, nb::const_)) + + LIEF_DEFAULT_STR(UnknownCommand); +} + +} diff --git a/vendor/lief/api/python/src/MachO/objects/pyVersionMin.cpp b/vendor/lief/api/python/src/MachO/objects/pyVersionMin.cpp new file mode 100644 index 0000000..275c890 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/objects/pyVersionMin.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/MachO/VersionMin.hpp" + +#include "MachO/pyMachO.hpp" + +namespace LIEF::MachO::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "VersionMin", + "Class that wraps the LC_VERSION_MIN_MACOSX, LC_VERSION_MIN_IPHONEOS, ... commands"_doc) + + .def_prop_rw("version", + nb::overload_cast<>(&VersionMin::version, nb::const_), + nb::overload_cast(&VersionMin::version), + "Version as a tuple of **3** integers"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("sdk", + nb::overload_cast<>(&VersionMin::sdk, nb::const_), + nb::overload_cast(&VersionMin::sdk), + "SDK as a tuple of **3** integers"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(VersionMin); +} + +} diff --git a/vendor/lief/api/python/src/MachO/pyMachO.hpp b/vendor/lief/api/python/src/MachO/pyMachO.hpp new file mode 100644 index 0000000..be97746 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/pyMachO.hpp @@ -0,0 +1,26 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_MACHO_H +#define PY_LIEF_MACHO_H +#include "pyLIEF.hpp" + +namespace LIEF::MachO::py { +template +void create(nb::module_&); + +void init_utils(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/MachO/pyUtils.cpp b/vendor/lief/api/python/src/MachO/pyUtils.cpp new file mode 100644 index 0000000..3efa126 --- /dev/null +++ b/vendor/lief/api/python/src/MachO/pyUtils.cpp @@ -0,0 +1,76 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "MachO/pyMachO.hpp" +#include +#include +#include + +#include "nanobind/extra/stl/pathlike.h" + +#include "LIEF/MachO/utils.hpp" +#include "LIEF/MachO/FatBinary.hpp" +#include "LIEF/MachO/Binary.hpp" + +namespace LIEF::MachO::py { + +void init_utils(nb::module_& m) { + lief_mod->def("is_macho", + [] (nb::PathLike path) { return is_macho(path.to_string()); }, + "Check if the given file is a ``MachO`` (from filename)"_doc, + "filename"_a + ); + + lief_mod->def("is_macho", + nb::overload_cast&>(&is_macho), + "Check if the given raw data is a ``MachO``"_doc, + "raw"_a + ); + + m.def("is_fat", + [] (nb::PathLike path) { return is_fat(path.to_string()); }, + "Check if the given Mach-O is fat"_doc, + "file"_a + ); + + m.def("is_64", + [] (nb::PathLike path) { return is_64(path.to_string()); }, + "Check if the given Mach-O is 64-bits"_doc, + "file"_a + ); + + m.def("check_layout", + [] (const Binary& bin) { + std::string on_error; + const bool is_valid = check_layout(bin, &on_error); + return std::pair{is_valid, on_error}; + }, + "Check the layout of the given Mach-O binary. It checks if it can be signed " + "according to ``cctools-921/libstuff/checkout.c``"_doc, + "file"_a + ); + + m.def("check_layout", + [] (const FatBinary& bin) { + std::string on_error; + const bool is_valid = check_layout(bin, &on_error); + return std::pair{is_valid, on_error}; + }, + R"delim( + Check the layout of the given FAT Mach-O by checking individually the layout + of the binaries embedded in the FAT. + )delim"_doc, "file"_a); +} +} diff --git a/vendor/lief/api/python/src/OAT/CMakeLists.txt b/vendor/lief/api/python/src/OAT/CMakeLists.txt new file mode 100644 index 0000000..7f916d8 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyEnums.cpp + pyUtils.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/OAT/init.cpp b/vendor/lief/api/python/src/OAT/init.cpp new file mode 100644 index 0000000..627b84c --- /dev/null +++ b/vendor/lief/api/python/src/OAT/init.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "OAT/pyOAT.hpp" +#include "OAT/init.hpp" + +#include "LIEF/OAT/Parser.hpp" +#include "LIEF/OAT/Binary.hpp" +#include "LIEF/OAT/Header.hpp" +#include "LIEF/OAT/DexFile.hpp" +#include "LIEF/OAT/Class.hpp" +#include "LIEF/OAT/Method.hpp" + +#define CREATE(X,Y) create(Y) + +namespace LIEF::OAT::py { + +inline void init_objects(nb::module_& m) { + CREATE(Parser, m); + CREATE(Binary, m); + CREATE(Header, m); + CREATE(DexFile, m); + CREATE(Class, m); + CREATE(Method, m); +} + +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("OAT", "Python API for OAT format"); + + init_enums(mod); + init_utils(mod); + + init_objects(mod); +} + + +} diff --git a/vendor/lief/api/python/src/OAT/init.hpp b/vendor/lief/api/python/src/OAT/init.hpp new file mode 100644 index 0000000..fa0ff5e --- /dev/null +++ b/vendor/lief/api/python/src/OAT/init.hpp @@ -0,0 +1,25 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_OAT_INIT_H +#define PY_LIEF_OAT_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::OAT::py { +void init(nb::module_& m); +void init_enums(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/OAT/objects/CMakeLists.txt b/vendor/lief/api/python/src/OAT/objects/CMakeLists.txt new file mode 100644 index 0000000..dd7aa18 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + pyHeader.cpp + pyParser.cpp + pyDexFile.cpp + pyClass.cpp + pyMethod.cpp + pyParser.cpp + pyBinary.cpp +) diff --git a/vendor/lief/api/python/src/OAT/objects/pyBinary.cpp b/vendor/lief/api/python/src/OAT/objects/pyBinary.cpp new file mode 100644 index 0000000..38e71f1 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyBinary.cpp @@ -0,0 +1,84 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/OAT/Binary.hpp" +#include "LIEF/OAT/Class.hpp" +#include "LIEF/OAT/Method.hpp" +#include "LIEF/OAT/DexFile.hpp" +#include "LIEF/DEX/File.hpp" +#include "LIEF/ELF/Binary.hpp" +#include "pyIterator.hpp" + +#include "OAT/pyOAT.hpp" + +#include +#include + +namespace LIEF::OAT::py { +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ bin(m, "Binary", "OAT binary representation"_doc); + + init_ref_iterator(bin, "it_dex_files"); + init_ref_iterator(bin, "it_oat_dex_files"); + init_ref_iterator(bin, "it_classes"); + init_ref_iterator(bin, "it_methods"); + + bin + .def_prop_ro("header", + nb::overload_cast<>(&Binary::header), + "Return the OAT " RST_CLASS_REF(lief.OAT.Header) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("dex_files", + nb::overload_cast<>(&Binary::dex_files), + "Return an iterator over " RST_CLASS_REF(lief.DEX.File) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("oat_dex_files", + nb::overload_cast<>(&Binary::oat_dex_files), + "Return an iterator over " RST_CLASS_REF(lief.OAT.DexFile) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("classes", + nb::overload_cast<>(&Binary::classes), + "Return an iterator over " RST_CLASS_REF(lief.OAT.Class) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("methods", + nb::overload_cast<>(&Binary::methods), + "Return an iterator over " RST_CLASS_REF(lief.OAT.Method) ""_doc, + nb::keep_alive<0, 1>()) + + .def("has_class", &Binary::has_class, + "Check if the class with the given name is present in the current OAT binary"_doc) + + .def("get_class", + nb::overload_cast(&Binary::get_class), + "Return the " RST_CLASS_REF(lief.OAT.Class) " from its name"_doc, + "class_name"_a, nb::rv_policy::reference_internal) + + .def("get_class", + nb::overload_cast(&Binary::get_class), + "Return the " RST_CLASS_REF(lief.OAT.Class) " from its **index**"_doc, + "class_index"_a, nb::rv_policy::reference_internal) + + .def_prop_ro("dex2dex_json_info", &Binary::dex2dex_json_info) + LIEF_DEFAULT_STR(Binary); +} + +} diff --git a/vendor/lief/api/python/src/OAT/objects/pyClass.cpp b/vendor/lief/api/python/src/OAT/objects/pyClass.cpp new file mode 100644 index 0000000..81407a0 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyClass.cpp @@ -0,0 +1,84 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/OAT/Class.hpp" +#include "LIEF/OAT/Method.hpp" +#include "LIEF/DEX/Method.hpp" + +#include "pyIterator.hpp" +#include "OAT/pyOAT.hpp" + +#include +#include +#include +#include + +namespace LIEF::OAT::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ cls(m, "Class", "OAT Class representation"_doc); + + init_ref_iterator(cls, "it_methods"); + + cls + .def(nb::init<>()) + + .def("has_dex_class", &Class::has_dex_class, + "True if a " RST_CLASS_REF_FULL(lief.DEX.Class) " object " + "is associated with this **OAT** Class"_doc) + + .def_prop_ro("status", &Class::status, + "Class " RST_CLASS_REF(lief.OAT.OAT_CLASS_STATUS) ""_doc) + + .def_prop_ro("type", &Class::type, + "Information (" RST_CLASS_REF(lief.OAT.OAT_CLASS_TYPES) ") about how methods " + "are optimized"_doc) + + .def_prop_ro("fullname", &Class::fullname, + "Class mangled name (e.g. ``Lcom/android/MyActivity;``)"_doc) + + .def_prop_ro("index", &Class::index, + "Index the **DEX** classes pool (" RST_ATTR_REF_FULL(lief.DEX.File.classes) ")"_doc) + + .def_prop_ro("methods", nb::overload_cast<>(&Class::methods), + "Iterator over " RST_CLASS_REF_FULL(lief.OAT.Method) ""_doc) + + .def_prop_ro("bitmap", &Class::bitmap, + "Bitmap information used to quickly find which methods are " + "optimized"_doc) + + .def("is_quickened", + nb::overload_cast(&Class::is_quickened, nb::const_), + "Check if the given " RST_CLASS_REF_FULL(lief.DEX.Method) " is compiled into native code"_doc, + "dex_method"_a) + + .def("is_quickened", + nb::overload_cast(&Class::is_quickened, nb::const_), + "Check if the Method at the given index is compiled into native code"_doc, + "method_index"_a) + + .def("method_offsets_index", + nb::overload_cast(&Class::method_offsets_index, nb::const_)) + + .def("method_offsets_index", + nb::overload_cast(&Class::method_offsets_index, nb::const_)) + + LIEF_DEFAULT_STR(Class); +} + +} diff --git a/vendor/lief/api/python/src/OAT/objects/pyDexFile.cpp b/vendor/lief/api/python/src/OAT/objects/pyDexFile.cpp new file mode 100644 index 0000000..a472b7f --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyDexFile.cpp @@ -0,0 +1,57 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/OAT/DexFile.hpp" +#include "LIEF/DEX/File.hpp" + +#include "OAT/pyOAT.hpp" + +#include +#include +#include + +namespace LIEF::OAT::py { +template<> +void create(nb::module_& m) { + + nb::class_(m, "DexFile", "OAT DexFile representation"_doc) + .def(nb::init<>()) + + .def_prop_rw("location", + nb::overload_cast<>(&DexFile::location, nb::const_), + nb::overload_cast(&DexFile::location), + "Original location of the DEX file"_doc) + + .def_prop_rw("checksum", + nb::overload_cast<>(&DexFile::checksum, nb::const_), + nb::overload_cast(&DexFile::checksum), + "Checksum of the underlying DEX file"_doc) + + .def_prop_rw("dex_offset", + nb::overload_cast<>(&DexFile::dex_offset, nb::const_), + nb::overload_cast(&DexFile::dex_offset), + "Offset to the raw " RST_CLASS_REF_FULL(lief.DEX.File) ""_doc) + + .def_prop_ro("has_dex_file", + &DexFile::has_dex_file, + "Check if the " RST_CLASS_REF_FULL(lief.DEX.File) " is present"_doc) + + .def_prop_ro("dex_file", nb::overload_cast<>(&DexFile::dex_file), + "Associated " RST_CLASS_REF_FULL(lief.DEX.File) ""_doc) + + LIEF_DEFAULT_STR(DexFile); + +} +} diff --git a/vendor/lief/api/python/src/OAT/objects/pyHeader.cpp b/vendor/lief/api/python/src/OAT/objects/pyHeader.cpp new file mode 100644 index 0000000..a07efa1 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyHeader.cpp @@ -0,0 +1,171 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/OAT/Header.hpp" + +#include "OAT/pyOAT.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::OAT::py { + +template<> +void create
(nb::module_& m) { + + nb::class_ hdr(m, "Header", "OAT Header representation"_doc); + nb::class_ it_key_values_t(hdr, "it_key_values_t"); + + nb::class_(hdr, "element_t") + .def_rw("key", &Header::element_t::key) + .def_prop_rw("value", + [] (const Header::element_t& self) { + return self.value; + }, + [] (const Header::element_t& self, const std::string& value) { + *self.value = value; + }, nb::rv_policy::reference_internal); + + + it_key_values_t + .def("__getitem__", + [] (Header::it_key_values_t& v, size_t i) { + if (i >= v.size()) { + throw nb::index_error(); + } + return v[i]; + }, + nb::rv_policy::reference_internal) + + .def("__len__", + [](Header::it_key_values_t& v) { + return v.size(); + }) + + .def("__iter__", + [](Header::it_key_values_t& v) { + return std::begin(v); + }, nb::rv_policy::reference_internal) + + .def("__next__", + [] (Header::it_key_values_t& v) { + if (v == std::end(v)) { + throw nb::stop_iteration(); + } + return *(v++); + + }, nb::rv_policy::reference_internal); + + hdr + .def(nb::init<>()) + + .def_prop_ro("key_values", nb::overload_cast<>(&Header::key_values), + "Configuration used for the ``dex2oat`` transformation"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("keys", &Header::keys, + "List of " RST_CLASS_REF(lief.OAT.HEADER_KEYS) " present"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("values", &Header::values, + "List of values associated with " RST_ATTR_REF(lief.OAT.Header.keys) ""_doc, + nb::rv_policy::move) + + .def_prop_ro("magic", nb::overload_cast<>(&Header::magic, nb::const_), + R"delim(Magic number which shoud be ``oat\x0A``)delim"_doc) + + .def_prop_ro("version", nb::overload_cast<>(&Header::version, nb::const_), + "Underlying version of the OAT file"_doc) + + .def_prop_ro("checksum", nb::overload_cast<>(&Header::checksum, nb::const_), + "Checksum of the OAT file"_doc) + + .def_prop_ro("instruction_set", + nb::overload_cast<>(&Header::instruction_set, nb::const_), + "List of " RST_CLASS_REF(lief.OAT.INSTRUCTION_SETS) ""_doc) + + .def_prop_ro("nb_dex_files", + nb::overload_cast<>(&Header::nb_dex_files, nb::const_), + "Number of " RST_CLASS_REF_FULL(lief.DEX.File) " registered in the current OAT"_doc) + + .def_prop_ro("oat_dex_files_offset", + nb::overload_cast<>(&Header::oat_dex_files_offset, nb::const_), + R"delim( + Offset to the raw :class:`lief.OAT.Dexfile` + + .. warning:: + + This attribute is only relevant for OAT for which the version is above 131 + )delim"_doc) + + .def_prop_ro("executable_offset", + nb::overload_cast<>(&Header::executable_offset, nb::const_)) + + .def_prop_ro("i2i_bridge_offset", + nb::overload_cast<>(&Header::i2i_bridge_offset, nb::const_)) + + .def_prop_ro("i2c_code_bridge_offset", + nb::overload_cast<>(&Header::i2c_code_bridge_offset, nb::const_)) + + .def_prop_ro("jni_dlsym_lookup_offset", + nb::overload_cast<>(&Header::jni_dlsym_lookup_offset, nb::const_)) + + .def_prop_ro("quick_generic_jni_trampoline_offset", + nb::overload_cast<>(&Header::quick_generic_jni_trampoline_offset, nb::const_)) + + .def_prop_ro("quick_imt_conflict_trampoline_offset", + nb::overload_cast<>(&Header::quick_imt_conflict_trampoline_offset, nb::const_)) + + .def_prop_ro("quick_resolution_trampoline_offset", + nb::overload_cast<>(&Header::quick_resolution_trampoline_offset, nb::const_)) + + .def_prop_ro("quick_to_interpreter_bridge_offset", + nb::overload_cast<>(&Header::quick_to_interpreter_bridge_offset, nb::const_)) + + .def_prop_ro("image_patch_delta", + nb::overload_cast<>(&Header::image_patch_delta, nb::const_)) + + .def_prop_ro("image_file_location_oat_checksum", + nb::overload_cast<>(&Header::image_file_location_oat_checksum, nb::const_)) + + .def_prop_ro("image_file_location_oat_data_begin", + nb::overload_cast<>(&Header::image_file_location_oat_data_begin, nb::const_)) + + .def_prop_ro("key_value_size", + nb::overload_cast<>(&Header::key_value_size, nb::const_)) + + .def("get", nb::overload_cast(&Header::get), + "key"_a, nb::rv_policy::reference_internal) + + .def("set", + nb::overload_cast(&Header::set), + "key"_a, "value"_a, nb::rv_policy::reference_internal) + + .def("__getitem__", + nb::overload_cast(&Header::operator[]), + nb::rv_policy::reference_internal) + + .def("__setitem__", + nb::overload_cast(&Header::set), + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(Header); + +} + +} diff --git a/vendor/lief/api/python/src/OAT/objects/pyMethod.cpp b/vendor/lief/api/python/src/OAT/objects/pyMethod.cpp new file mode 100644 index 0000000..ef8a0b0 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyMethod.cpp @@ -0,0 +1,65 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/OAT/Method.hpp" +#include "LIEF/OAT/Class.hpp" +#include "LIEF/DEX/Method.hpp" + +#include "OAT/pyOAT.hpp" + +#include +#include +#include + +namespace LIEF::OAT::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "Method", "OAT Method representation"_doc) + .def(nb::init<>()) + + .def_prop_ro("name", &Method::name, + "Method's name"_doc) + + .def_prop_ro("oat_class", + nb::overload_cast<>(&Method::oat_class), + "" RST_CLASS_REF(lief.OAT.Class) " associated with the method (or None)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("dex_method", + nb::overload_cast<>(&Method::dex_method), + "Mirrored " RST_CLASS_REF(lief.DEX.Method) " associated with the OAT method (or None)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_dex_method", + &Method::has_dex_method, + "Check if a " RST_CLASS_REF(lief.DEX.Method) " is associated with the OAT method"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("is_dex2dex_optimized", &Method::is_dex2dex_optimized, + "True if the optimization is **DEX**"_doc) + + .def_prop_ro("is_compiled", &Method::is_compiled, + "True if the optimization is **native**"_doc) + + .def_prop_rw("quick_code", + nb::overload_cast<>(&Method::quick_code, nb::const_), + nb::overload_cast(&Method::quick_code), + "Quick code associated with the method"_doc) + + LIEF_DEFAULT_STR(Method); +} +} diff --git a/vendor/lief/api/python/src/OAT/objects/pyParser.cpp b/vendor/lief/api/python/src/OAT/objects/pyParser.cpp new file mode 100644 index 0000000..9357944 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/objects/pyParser.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "OAT/pyOAT.hpp" + +#include "pyIOStream.hpp" +#include "pyutils.hpp" +#include "typing/InputParser.hpp" + +#include "LIEF/OAT/Parser.hpp" +#include "LIEF/OAT/Binary.hpp" +#include "LIEF/logging.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::OAT::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse", + static_cast(*)(std::string_view)>(&Parser::parse), + "Parse the given OAT file and return a " RST_CLASS_REF(lief.OAT.Binary) " object"_doc, + "oat_file"_a, nb::rv_policy::take_ownership); + + m.def("parse", + static_cast(*)(std::string_view, std::string_view)>( + &Parser::parse), + "Parse the given OAT with its VDEX file and return a " RST_CLASS_REF(lief.OAT.Binary) " object"_doc, + "oat_file"_a, "vdex_file"_a, nb::rv_policy::take_ownership); + + m.def("parse", + static_cast(*)(std::vector)>(&Parser::parse), + "Parse the given raw data and return a " RST_CLASS_REF(lief.OAT.Binary) " object"_doc, + "raw"_a, nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj) -> std::unique_ptr { + if (auto path_str = path_to_str(obj)) { + return Parser::parse(std::move(*path_str)); + } + + if (auto stream = PyIOStream::from_python(obj)) { + auto ptr = std::make_unique(std::move(*stream)); + return Parser::parse(stream->content()); + } + logging::log(logging::Level::Err, + "LIEF parser interface does not support Python object: " + + type2str(obj)); + return nullptr; + }, + "obj"_a, + nb::rv_policy::take_ownership); +} +} diff --git a/vendor/lief/api/python/src/OAT/pyEnums.cpp b/vendor/lief/api/python/src/OAT/pyEnums.cpp new file mode 100644 index 0000000..f3274c2 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/pyEnums.cpp @@ -0,0 +1,70 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "OAT/pyOAT.hpp" +#include "LIEF/OAT/enums.hpp" +#include "LIEF/OAT/EnumToString.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::OAT::py { + +void init_enums(nb::module_& m) { + + nb::enum_(m, "OAT_CLASS_TYPES") + .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_ALL_COMPILED)) + .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_SOME_COMPILED)) + .value(PY_ENUM(OAT_CLASS_TYPES::OAT_CLASS_NONE_COMPILED)); + + nb::enum_(m, "OAT_CLASS_STATUS") + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RETIRED)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_ERROR)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_NOTREADY)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_IDX)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_LOADED)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RESOLVING)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RESOLVED)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFYING)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_RETRY_VERIFICATION_AT_RUNTIME)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFYING_AT_RUNTIME)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_VERIFIED)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_INITIALIZING)) + .value(PY_ENUM(OAT_CLASS_STATUS::STATUS_INITIALIZED)); + + nb::enum_(m, "HEADER_KEYS") + .value(PY_ENUM(HEADER_KEYS::KEY_IMAGE_LOCATION)) + .value(PY_ENUM(HEADER_KEYS::KEY_DEX2OAT_CMD_LINE)) + .value(PY_ENUM(HEADER_KEYS::KEY_DEX2OAT_HOST)) + .value(PY_ENUM(HEADER_KEYS::KEY_PIC)) + .value(PY_ENUM(HEADER_KEYS::KEY_HAS_PATCH_INFO)) + .value(PY_ENUM(HEADER_KEYS::KEY_DEBUGGABLE)) + .value(PY_ENUM(HEADER_KEYS::KEY_NATIVE_DEBUGGABLE)) + .value(PY_ENUM(HEADER_KEYS::KEY_COMPILER_FILTER)) + .value(PY_ENUM(HEADER_KEYS::KEY_CLASS_PATH)) + .value(PY_ENUM(HEADER_KEYS::KEY_BOOT_CLASS_PATH)) + .value(PY_ENUM(HEADER_KEYS::KEY_CONCURRENT_COPYING)); + + + nb::enum_(m, "INSTRUCTION_SETS") + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_NONE)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_ARM)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_ARM_64)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_THUMB2)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_X86)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_X86_64)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_MIPS)) + .value(PY_ENUM(INSTRUCTION_SETS::INST_SET_MIPS_64)); +} +} diff --git a/vendor/lief/api/python/src/OAT/pyOAT.hpp b/vendor/lief/api/python/src/OAT/pyOAT.hpp new file mode 100644 index 0000000..493e51a --- /dev/null +++ b/vendor/lief/api/python/src/OAT/pyOAT.hpp @@ -0,0 +1,26 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_OAT_H +#define PY_LIEF_OAT_H + +#include "pyLIEF.hpp" + +namespace LIEF::OAT::py { +template +void create(nb::module_&); +} + +#endif diff --git a/vendor/lief/api/python/src/OAT/pyUtils.cpp b/vendor/lief/api/python/src/OAT/pyUtils.cpp new file mode 100644 index 0000000..ca27247 --- /dev/null +++ b/vendor/lief/api/python/src/OAT/pyUtils.cpp @@ -0,0 +1,63 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyOAT.hpp" + +#include "LIEF/OAT/utils.hpp" +#include "LIEF/OAT/Binary.hpp" + +#include +#include +#include + +namespace LIEF::OAT::py { + +void init_utils(nb::module_& m) { + lief_mod->def("is_oat", + nb::overload_cast(&is_oat), + "Check if the " RST_CLASS_REF(lief.ELF.Binary) " given in parameter is an OAT"_doc, + "binary"_a); + + lief_mod->def("is_oat", + nb::overload_cast(&is_oat), + "Check if the **file** given in parameter is an OAT"_doc, + "path"_a); + + lief_mod->def("is_oat", + nb::overload_cast&>(&is_oat), + "Check if the **raw data** given in parameter is an OAT"_doc, + "raw"_a); + + m.def("version", + nb::overload_cast(&version), + "Return the OAT version of the " RST_CLASS_REF(lief.ELF.Binary) " given in parameter"_doc, + "binary"_a); + + m.def("version", + nb::overload_cast(&version), + "Return the OAT version of the **file** given in parameter"_doc, + "file"_a); + + m.def("version", + nb::overload_cast&>(&version), + "Return the OAT version of the **raw data** given in parameter"_doc, + "raw"_a); + + m.def("android_version", + &android_version, + "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given OAT version"_doc); +} +} + diff --git a/vendor/lief/api/python/src/ObjC/CMakeLists.txt b/vendor/lief/api/python/src/ObjC/CMakeLists.txt new file mode 100644 index 0000000..4cf1825 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/CMakeLists.txt @@ -0,0 +1,11 @@ +target_sources(pyLIEF PRIVATE + init.cpp + objects/pyMetadata.cpp + objects/pyClass.cpp + objects/pyCategory.cpp + objects/pyMethod.cpp + objects/pyIVar.cpp + objects/pyProtocol.cpp + objects/pyProperty.cpp + objects/pyDeclOpt.cpp +) diff --git a/vendor/lief/api/python/src/ObjC/init.cpp b/vendor/lief/api/python/src/ObjC/init.cpp new file mode 100644 index 0000000..0ea7b63 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/init.cpp @@ -0,0 +1,31 @@ +#include "ObjC/init.hpp" +#include "ObjC/pyObjC.hpp" + +#include +#include + +namespace LIEF::objc { +class Metadata; +class Class; +class Category; +class IVar; +class Property; +class Method; +class Protocol; +struct DeclOpt; +} + +namespace LIEF::objc::py { +void init(nb::module_& m) { + nb::module_ objc = m.def_submodule("objc"); + + create(objc); + create(objc); + create(objc); + create(objc); + create(objc); + create(objc); + create(objc); + create(objc); +} +} diff --git a/vendor/lief/api/python/src/ObjC/init.hpp b/vendor/lief/api/python/src/ObjC/init.hpp new file mode 100644 index 0000000..9284e23 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/init.hpp @@ -0,0 +1,8 @@ +#ifndef PY_LIEF_OBJC_INIT_H +#define PY_LIEF_OBJC_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::objc::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/ObjC/objects/pyCategory.cpp b/vendor/lief/api/python/src/ObjC/objects/pyCategory.cpp new file mode 100644 index 0000000..9b2191c --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyCategory.cpp @@ -0,0 +1,74 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Category.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ category(m, "Category", + R"doc( + This class represents an Objective-C category (e.g. + ``@interface NSString (MyAdditions)``) + )doc"_doc + ); + category + .def_prop_ro("name", &objc::Category::name, + R"doc( + Name of the category + )doc"_doc + ) + .def_prop_ro("class_name", &objc::Category::class_name, + R"doc( + (demangled) name of the class extended by this category + )doc"_doc + ) + .def_prop_ro("methods", + [] (objc::Category& self) { + auto methods = LIEF::py::owning_range(self.methods()); + return nb::make_iterator( + nb::type(), "methods_it", methods + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the different methods defined by this category. + )doc"_doc + ) + .def_prop_ro("protocols", + [] (objc::Category& self) { + auto protocols = LIEF::py::owning_range(self.protocols()); + return nb::make_iterator( + nb::type(), "protocols_it", protocols + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the different protocols adopted by this category. + )doc"_doc + ) + .def_prop_ro("properties", + [] (objc::Category& self) { + auto properties = LIEF::py::owning_range(self.properties()); + return nb::make_iterator( + nb::type(), "properties_it", properties + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the properties of this category. + )doc"_doc + ) + .def("to_decl", &Category::to_decl, + R"doc( + Generate a header-like string for this specific category. + + The generated output can be configured with the provided :class:`~.DeclOpt` + parameter. + )doc"_doc, "opt"_a = DeclOpt() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyClass.cpp b/vendor/lief/api/python/src/ObjC/objects/pyClass.cpp new file mode 100644 index 0000000..3c1a609 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyClass.cpp @@ -0,0 +1,110 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Class.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ clazz(m, "Class", + R"doc( + This class represents an Objective-C class (``@interface``) + )doc"_doc + ); + clazz + .def_prop_ro("name", &objc::Class::name, + R"doc( + Name of the class + )doc"_doc + ) + .def_prop_ro("demangled_name", &objc::Class::demangled_name, + R"doc( + Demangled name of the class + )doc"_doc + ) + .def_prop_ro("super_class", &objc::Class::super_class, + R"doc( + Parent class in case of inheritance. + + This is set **only** when the superclass is defined in the same binary. + For root classes (e.g. ``NSObject``) or superclasses imported from another + image, it is ``None`` even though :attr:`super_name` / + :attr:`demangled_super_name` may still be resolved. + )doc"_doc, nb::keep_alive<0, 1>() + ) + .def_prop_ro("super_name", &objc::Class::super_name, + R"doc( + (raw) name of the superclass (empty for root classes or when it could not + be resolved). + )doc"_doc + ) + .def_prop_ro("demangled_super_name", &objc::Class::demangled_super_name, + R"doc( + Demangled name of the superclass. + )doc"_doc + ) + .def_prop_ro("is_meta", &objc::Class::is_meta, + R"doc( + + )doc"_doc + ) + .def_prop_ro("methods", + [] (objc::Class& self) { + auto methods = LIEF::py::owning_range(self.methods()); + return nb::make_iterator( + nb::type(), "methods_it", methods + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the different methods defined by this class. + )doc"_doc + ) + .def_prop_ro("protocols", + [] (objc::Class& self) { + auto protocols = LIEF::py::owning_range(self.protocols()); + return nb::make_iterator( + nb::type(), "protocols_it", protocols + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the different protocols implemented by this class. + )doc"_doc + ) + .def_prop_ro("properties", + [] (objc::Class& self) { + auto properties = LIEF::py::owning_range(self.properties()); + return nb::make_iterator( + nb::type(), "properties_it", properties + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the properties of this class. + )doc"_doc + ) + .def_prop_ro("ivars", + [] (objc::Class& self) { + auto ivars = LIEF::py::owning_range(self.ivars()); + return nb::make_iterator( + nb::type(), "ivars_it", ivars + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the different instance variables defined in this class. + )doc"_doc + ) + .def("to_decl", &Class::to_decl, + R"doc( + Generate a header-like string for this specific class. + + The generated output can be configured with the provided :class:`~.DeclOpt` + parameter. + )doc"_doc, "opt"_a = DeclOpt() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyDeclOpt.cpp b/vendor/lief/api/python/src/ObjC/objects/pyDeclOpt.cpp new file mode 100644 index 0000000..ac70a2c --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyDeclOpt.cpp @@ -0,0 +1,21 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/DeclOpt.hpp" + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "DeclOpt", + R"doc( + This structure wraps options to tweak the generated output of + functions like :func:`lief.objc.Metadata.to_decl` + )doc"_doc + ) + .def(nb::init<>()) + .def_rw("show_annotations", &DeclOpt::show_annotations, + R"doc( + Whether annotations like method's address should be printed. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyIVar.cpp b/vendor/lief/api/python/src/ObjC/objects/pyIVar.cpp new file mode 100644 index 0000000..1777fdf --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyIVar.cpp @@ -0,0 +1,29 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/IVar.hpp" + +#include + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ ivar(m, "IVar", + R"doc( + This class represents an instance variable (ivar) + )doc"_doc + ); + ivar + .def_prop_ro("name", &objc::IVar::name, + R"doc( + Name of the instance variable + )doc"_doc + ) + .def_prop_ro("mangled_type", &objc::IVar::mangled_type, + R"doc( + Type of the instance var in its mangled representation (e.g. ``[29i]``) + )doc"_doc + ) + ; + +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyMetadata.cpp b/vendor/lief/api/python/src/ObjC/objects/pyMetadata.cpp new file mode 100644 index 0000000..0be780a --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyMetadata.cpp @@ -0,0 +1,82 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Metadata.hpp" +#include "LIEF/ObjC/Class.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ meta(m, "Metadata", + R"doc( + This class is the main interface to inspect Objective-C metadata + + It can be instantiated using the function :attr:`lief.MachO.Binary.objc_metadata` + )doc"_doc + ); + meta + .def("to_decl", &Metadata::to_decl, + R"doc( + Generate a header-like of all the Objective-C metadata identified in the + binary. + + The generated output can be configured with the provided :class:`~.DeclOpt` + parameter. + )doc"_doc, "opt"_a = DeclOpt() + ) + .def_prop_ro("classes", + [] (objc::Metadata& self) { + auto classes = LIEF::py::owning_range(self.classes()); + return nb::make_iterator( + nb::type(), "classes_it", classes + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the different Objective-C classes (``@interface``). + )doc"_doc + ) + .def_prop_ro("protocols", + [] (objc::Metadata& self) { + auto protocols = LIEF::py::owning_range(self.protocols()); + return nb::make_iterator( + nb::type(), "protocols_it", protocols + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the Objective-C protocols declared in this + binary (``@protocol``). + )doc"_doc + ) + .def_prop_ro("categories", + [] (objc::Metadata& self) { + auto categories = LIEF::py::owning_range(self.categories()); + return nb::make_iterator( + nb::type(), "categories_it", categories + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Return an iterator over the Objective-C categories declared in this + binary (e.g. ``@interface NSString (MyAdditions)``). + )doc"_doc + ) + + .def("get_class", &objc::Metadata::get_class, + R"doc( + Try to find the Objective-C class with the given **mangled** name. + )doc"_doc, "name"_a, nb::keep_alive<0, 1>() + ) + + .def("get_protocol", &objc::Metadata::get_protocol, + R"doc( + Try to find the Objective-C protocol with the given **mangled** name. + )doc"_doc, "name"_a, nb::keep_alive<0, 1>() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyMethod.cpp b/vendor/lief/api/python/src/ObjC/objects/pyMethod.cpp new file mode 100644 index 0000000..e1e0c17 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyMethod.cpp @@ -0,0 +1,38 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Method.hpp" + +#include + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ meth(m, "Method", + R"doc( + This class represents an Objective-C Method. + )doc"_doc + ); + meth + .def_prop_ro("name", &objc::Method::name, + R"doc( + Name of the method + )doc"_doc + ) + .def_prop_ro("mangled_type", &objc::Method::mangled_type, + R"doc( + Prototype of the method in its mangled representation (e.g. ``@16@0:8``) + )doc"_doc + ) + .def_prop_ro("address", &objc::Method::address, + R"doc( + Virtual address where this method is implemented in the binary + )doc"_doc + ) + .def_prop_ro("is_instance", &objc::Method::is_instance, + R"doc( + Whether it's an instance method or not. + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyProperty.cpp b/vendor/lief/api/python/src/ObjC/objects/pyProperty.cpp new file mode 100644 index 0000000..2797654 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyProperty.cpp @@ -0,0 +1,29 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Property.hpp" + +#include + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ prop(m, "Property", + R"doc( + This class represents a ``@property`` in Objective-C + )doc"_doc + ); + + prop + .def_prop_ro("name", &objc::Property::name, + R"doc( + Name of the property + )doc"_doc + ) + .def_prop_ro("attribute", &objc::Property::attribute, + R"doc( + (raw) property's attributes (e.g. ``T@"NSString",C,D,N``) + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/objects/pyProtocol.cpp b/vendor/lief/api/python/src/ObjC/objects/pyProtocol.cpp new file mode 100644 index 0000000..1a3bdc2 --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/objects/pyProtocol.cpp @@ -0,0 +1,84 @@ +#include "ObjC/pyObjC.hpp" +#include "LIEF/ObjC/Protocol.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::objc::py { +template<> +void create(nb::module_& m) { + nb::class_ protocol(m, "Protocol", + R"doc( + This class represents an Objective-C ``@protocol`` + )doc"_doc + ); + + protocol + .def_prop_ro("mangled_name", &objc::Protocol::mangled_name, + R"doc( + Mangled name of the protocol + )doc"_doc + ) + + .def_prop_ro("protocols", + [] (objc::Protocol& self) { + auto protocols = LIEF::py::owning_range(self.protocols()); + return nb::make_iterator( + nb::type(), "protocols_it", protocols + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the protocols adopted by this protocol (e.g. the + ```` in ``@protocol Foo ``). + )doc"_doc + ) + + .def_prop_ro("optional_methods", + [] (objc::Protocol& self) { + auto methods = LIEF::py::owning_range(self.optional_methods()); + return nb::make_iterator( + nb::type(), "optional_methods_it", methods + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the methods that could be overridden + )doc"_doc + ) + .def_prop_ro("required_methods", + [] (objc::Protocol& self) { + auto methods = LIEF::py::owning_range(self.required_methods()); + return nb::make_iterator( + nb::type(), "required_methods_it", methods + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the methods of this protocol that must be implemented + )doc"_doc + ) + .def_prop_ro("properties", + [] (objc::Protocol& self) { + auto props = LIEF::py::owning_range(self.properties()); + return nb::make_iterator( + nb::type(), "properties_it", props + ); + }, nb::keep_alive<0, 1>(), + R"doc( + Iterator over the properties defined in this protocol + )doc"_doc + ) + + .def("to_decl", &Protocol::to_decl, + R"doc( + Generate a header-like string for this specific protocol. + + The generated output can be configured with the provided :class:`~.DeclOpt` + parameter. + )doc"_doc, "opt"_a = DeclOpt() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/ObjC/pyObjC.hpp b/vendor/lief/api/python/src/ObjC/pyObjC.hpp new file mode 100644 index 0000000..a37b43c --- /dev/null +++ b/vendor/lief/api/python/src/ObjC/pyObjC.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_OBJC_H +#define PY_LIEF_OBJC_H +#include "pyLIEF.hpp" + +namespace LIEF::objc::py { + +namespace objc = LIEF::objc; + +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/PDB/CMakeLists.txt b/vendor/lief/api/python/src/PDB/CMakeLists.txt new file mode 100644 index 0000000..2173c72 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/CMakeLists.txt @@ -0,0 +1,11 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyBuildMetadata.cpp + pyCompilationUnit.cpp + pyDebugInfo.cpp + pyFunction.cpp + pyPublicSymbol.cpp + pyType.cpp + pyUtils.cpp +) +add_subdirectory(types) diff --git a/vendor/lief/api/python/src/PDB/init.cpp b/vendor/lief/api/python/src/PDB/init.cpp new file mode 100644 index 0000000..491d47b --- /dev/null +++ b/vendor/lief/api/python/src/PDB/init.cpp @@ -0,0 +1,29 @@ +#include "PDB/init.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include + +#include "LIEF/PDB/DebugInfo.hpp" +#include "LIEF/PDB/BuildMetadata.hpp" +#include "LIEF/PDB/Type.hpp" + +namespace LIEF::pdb::py { +void init(nb::module_& m) { + nb::module_ pdb = m.def_submodule("pdb"); + + pdb.def("load", &LIEF::pdb::load, + R"doc( + Load the PDB from the given path + )doc"_doc, "path"_a + ); + init_utils(m); + + create(pdb); + create(pdb); + create(pdb); + create(pdb); + create(pdb); + create(pdb); +} +} diff --git a/vendor/lief/api/python/src/PDB/init.hpp b/vendor/lief/api/python/src/PDB/init.hpp new file mode 100644 index 0000000..4c464fa --- /dev/null +++ b/vendor/lief/api/python/src/PDB/init.hpp @@ -0,0 +1,9 @@ +#ifndef PY_LIEF_DBG_PDB_INIT_H +#define PY_LIEF_DBG_PDB_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::pdb::py { +void init(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/PDB/pyBuildMetadata.cpp b/vendor/lief/api/python/src/PDB/pyBuildMetadata.cpp new file mode 100644 index 0000000..b11f6ba --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyBuildMetadata.cpp @@ -0,0 +1,175 @@ +#include +#include "LIEF/PDB/BuildMetadata.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include +#include + +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "BuildMetadata", + R"doc( + This class wraps build metadata represented by the codeview symbols: + ``S_COMPILE3, S_COMPILE2, S_BUILDINFO`` + )doc"_doc + ); + + using LANG = pdb::BuildMetadata::LANG; + nb::enum_(obj, "LANG") + .value("C", LANG::C) + .value("CPP", LANG::CPP) + .value("FORTRAN", LANG::FORTRAN) + .value("MASM", LANG::MASM) + .value("PASCAL_LANG", LANG::PASCAL_LANG) + .value("BASIC", LANG::BASIC) + .value("COBOL", LANG::COBOL) + .value("LINK", LANG::LINK) + .value("CVTRES", LANG::CVTRES) + .value("CVTPGD", LANG::CVTPGD) + .value("CSHARP", LANG::CSHARP) + .value("VB", LANG::VB) + .value("ILASM", LANG::ILASM) + .value("JAVA", LANG::JAVA) + .value("JSCRIPT", LANG::JSCRIPT) + .value("MSIL", LANG::MSIL) + .value("HLSL", LANG::HLSL) + .value("OBJC", LANG::OBJC) + .value("OBJCPP", LANG::OBJCPP) + .value("SWIFT", LANG::SWIFT) + .value("ALIASOBJ", LANG::ALIASOBJ) + .value("RUST", LANG::RUST) + .value("GO", LANG::GO) + .value("UNKNOWN", LANG::UNKNOWN); + + using CPU = pdb::BuildMetadata::CPU; + nb::enum_(obj, "CPU") + .value("INTEL_8080", CPU::INTEL_8080) + .value("INTEL_8086", CPU::INTEL_8086) + .value("INTEL_80286", CPU::INTEL_80286) + .value("INTEL_80386", CPU::INTEL_80386) + .value("INTEL_80486", CPU::INTEL_80486) + .value("PENTIUM", CPU::PENTIUM) + .value("PENTIUMPRO", CPU::PENTIUMPRO) + .value("PENTIUM3", CPU::PENTIUM3) + .value("MIPS", CPU::MIPS) + .value("MIPS16", CPU::MIPS16) + .value("MIPS32", CPU::MIPS32) + .value("MIPS64", CPU::MIPS64) + .value("MIPSI", CPU::MIPSI) + .value("MIPSII", CPU::MIPSII) + .value("MIPSIII", CPU::MIPSIII) + .value("MIPSIV", CPU::MIPSIV) + .value("MIPSV", CPU::MIPSV) + .value("M68000", CPU::M68000) + .value("M68010", CPU::M68010) + .value("M68020", CPU::M68020) + .value("M68030", CPU::M68030) + .value("M68040", CPU::M68040) + .value("ALPHA", CPU::ALPHA) + .value("ALPHA_21164", CPU::ALPHA_21164) + .value("ALPHA_21164A", CPU::ALPHA_21164A) + .value("ALPHA_21264", CPU::ALPHA_21264) + .value("ALPHA_21364", CPU::ALPHA_21364) + .value("PPC601", CPU::PPC601) + .value("PPC603", CPU::PPC603) + .value("PPC604", CPU::PPC604) + .value("PPC620", CPU::PPC620) + .value("PPCFP", CPU::PPCFP) + .value("PPCBE", CPU::PPCBE) + .value("SH3", CPU::SH3) + .value("SH3E", CPU::SH3E) + .value("SH3DSP", CPU::SH3DSP) + .value("SH4", CPU::SH4) + .value("SHMEDIA", CPU::SHMEDIA) + .value("ARM3", CPU::ARM3) + .value("ARM4", CPU::ARM4) + .value("ARM4T", CPU::ARM4T) + .value("ARM5", CPU::ARM5) + .value("ARM5T", CPU::ARM5T) + .value("ARM6", CPU::ARM6) + .value("ARM_XMAC", CPU::ARM_XMAC) + .value("ARM_WMMX", CPU::ARM_WMMX) + .value("ARM7", CPU::ARM7) + .value("OMNI", CPU::OMNI) + .value("IA64", CPU::IA64) + .value("IA64_2", CPU::IA64_2) + .value("CEE", CPU::CEE) + .value("AM33", CPU::AM33) + .value("M32R", CPU::M32R) + .value("TRICORE", CPU::TRICORE) + .value("X64", CPU::X64) + .value("EBC", CPU::EBC) + .value("THUMB", CPU::THUMB) + .value("ARMNT", CPU::ARMNT) + .value("ARM64", CPU::ARM64) + .value("HYBRID_X86ARM64", CPU::HYBRID_X86ARM64) + .value("ARM64EC", CPU::ARM64EC) + .value("ARM64X", CPU::ARM64X) + .value("D3D11_SHADER", CPU::D3D11_SHADER) + .value("UNKNOWN", CPU::UNKNOWN); + + using version_t = BuildMetadata::version_t; + nb::class_(obj, "version_t", + "This structure represents a version for the backend or the frontend"_doc + ) + .def_rw("major", &version_t::major, "Major version"_doc) + .def_rw("minor", &version_t::minor, "Minor version"_doc) + .def_rw("build", &version_t::build, "Build version"_doc) + .def_rw("qfe", &version_t::qfe, "Quick Fix Engineering version"_doc); + + + using build_info_t = BuildMetadata::build_info_t; + nb::class_(obj, "build_info_t", + "Build information represented by the ``S_BUILDINFO`` symbol"_doc + ) + .def_rw("cwd", &build_info_t::cwd, + "Working directory where the *build tool* was invoked"_doc) + .def_rw("build_tool", &build_info_t::build_tool, + R"doc(Path to the build tool (e.g. ``C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.36.32532\bin\HostX64\x64\CL.exe``)doc"_doc) + .def_rw("source_file", &build_info_t::source_file, + "Source file consumed by the *build tool*"_doc) + .def_rw("pdb", &build_info_t::pdb, + "PDB path"_doc) + .def_rw("command_line", &build_info_t::command_line, + "Command line arguments used to invoke the *build tool*"_doc); + + obj + .def_prop_ro("frontend_version", &BuildMetadata::frontend_version, + "Version of the frontend (e.g. ``19.36.32537``)"_doc + ) + + .def_prop_ro("backend_version", &BuildMetadata::backend_version, + "Version of the backend (e.g. ``14.36.32537``)"_doc + ) + + .def_prop_ro("version", &BuildMetadata::version, + R"doc( + Version of the *tool* as a string. For instance, ``Microsoft (R) CVTRES``, + ``Microsoft (R) LINK``. + )doc"_doc + ) + + .def_prop_ro("language", &BuildMetadata::language, + "Source language"_doc + ) + + .def_prop_ro("target_cpu", &BuildMetadata::target_cpu, + "Target CPU"_doc + ) + + .def_prop_ro("build_info", &BuildMetadata::build_info, + "Build information represented by the ``S_BUILDINFO`` symbol"_doc + ) + + .def_prop_ro("env", &BuildMetadata::env, + "Environment information represented by the ``S_ENVBLOCK`` symbol"_doc + ) + + LIEF_DEFAULT_STR(pdb::BuildMetadata); +} + +} diff --git a/vendor/lief/api/python/src/PDB/pyCompilationUnit.cpp b/vendor/lief/api/python/src/PDB/pyCompilationUnit.cpp new file mode 100644 index 0000000..edef28c --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyCompilationUnit.cpp @@ -0,0 +1,72 @@ +#include +#include "LIEF/PDB/CompilationUnit.hpp" +#include "LIEF/PDB/BuildMetadata.hpp" +#include "LIEF/DebugDeclOpt.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "CompilationUnit", + R"doc( + This class represents a Compilation Unit (or Module) in a PDB file + )doc"_doc + ) + .def_prop_ro("module_name", &pdb::CompilationUnit::module_name, + R"doc( + Name (or path) to the COFF object (``.obj``) associated with this + compilation unit (e.g. ``e:\obj.amd64fre\minkernel\ntos\hvl\mp\objfre\amd64\hvlp.obj``) + )doc"_doc + ) + + .def_prop_ro("object_filename", &pdb::CompilationUnit::object_filename, + R"doc( + Name of path to the original binary object (COFF, Archive) in which + the compilation unit was located before being linked. + e.g. ``e:\obj.amd64fre\minkernel\ntos\hvl\mp\objfre\amd64\hvl.lib`` + )doc"_doc + ) + + .def_prop_ro("sources", + [] (const pdb::CompilationUnit& self) { + auto sources = self.sources(); + return nb::make_iterator( + nb::type(), "sources_it", sources); + }, + R"doc( + Iterator over the sources files that compose this compilation unit. + These files include **headers** (``.h, .hpp``, ...). + )doc"_doc, nb::keep_alive<0, 1>() + ) + .def_prop_ro("functions", + [] (const pdb::CompilationUnit& self) { + auto functions = LIEF::py::owning_range(self.functions()); + return nb::make_iterator( + nb::type(), "functions_it", functions); + }, + R"doc( + Return an iterator over the functions defined in this compilation unit. + If the PDB does not contain or has an empty DBI stream, it returns + an empty iterator. + )doc"_doc, nb::keep_alive<0, 1>() + ) + .def_prop_ro("build_metadata", &CompilationUnit::build_metadata, + nb::rv_policy::take_ownership, nb::keep_alive<0, 1>()) + + .def("to_decl", + [] (const pdb::CompilationUnit& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for the functions defined in this " + "compilation unit"_doc, + "opt"_a.none() = nb::none()) + LIEF_DEFAULT_STR(CompilationUnit); +} + +} diff --git a/vendor/lief/api/python/src/PDB/pyDebugInfo.cpp b/vendor/lief/api/python/src/PDB/pyDebugInfo.cpp new file mode 100644 index 0000000..22d3c93 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyDebugInfo.cpp @@ -0,0 +1,94 @@ +#include + +#include "LIEF/Abstract/DebugInfo.hpp" +#include "LIEF/PDB/DebugInfo.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ dbg_info(m, "DebugInfo", + R"doc( + This class provides an interface for PDB files. + + One can instantiate this class using :func:`lief.pdb.load` or + :meth:`lief.pdb.DebugInfo.from_file` + )doc"_doc + ); + dbg_info + .def_prop_ro("age", &pdb::DebugInfo::age, + "The number of times the PDB file has been written."_doc) + + .def_prop_ro("guid", &pdb::DebugInfo::guid, + "Unique identifier of the PDB file."_doc) + + .def_static("from_file", + [] (nb::PathLike path) { return pdb::DebugInfo::from_file(path); }, + R"doc( + Instantiate this class from the given PDB file. It returns ``None`` + if the PDB can't be processed. + )doc"_doc, "filepath"_a + ) + + .def("find_type", nb::overload_cast(&pdb::DebugInfo::find_type, nb::const_), + "Find the type with the given name"_doc, "name"_a + ) + + .def("find_type", nb::overload_cast(&pdb::DebugInfo::find_type, nb::const_), + "Find type at the given index"_doc, "index"_a + ) + + .def("find_public_symbol", &pdb::DebugInfo::find_public_symbol, + R"doc( + Try to find the PublicSymbol from the given name (based on the public symbol stream) + The function returns ``None`` if the symbol can't be found. + + .. code-block:: python + + debug_info: lief.pdb.DebugInfo = ... + if sym := debug_info.find_public_symbol("MiSyncSystemPdes"): + print("found") + )doc"_doc, "name"_a + ) + .def_prop_ro("public_symbols", + [] (pdb::DebugInfo& self) { + auto symbols = LIEF::py::owning_range(self.public_symbols()); + return nb::make_iterator( + nb::type(), "public_symbols_it", symbols); + }, + R"doc( + Return an iterator over the public symbol stream. + )doc"_doc, nb::keep_alive<0, 1>()) + + .def_prop_ro("compilation_units", + [] (pdb::DebugInfo& self) { + auto units = LIEF::py::owning_range(self.compilation_units()); + return nb::make_iterator( + nb::type(), "compilation_units_it", units); + }, + R"doc( + Iterator over the :class:`.CompilationUnit` from the PDB's DBI stream. + CompilationUnit are also named "Module" in the PDB's official documentation + )doc"_doc, nb::keep_alive<0, 1>()) + + .def_prop_ro("types", + [] (pdb::DebugInfo& self) { + auto types = LIEF::py::owning_range(self.types()); + return nb::make_iterator( + nb::type(), "types_it", types); + }, + R"doc( + Return an iterator over the different types registered in this PDB file + )doc"_doc, nb::keep_alive<0, 1>()) + + LIEF_DEFAULT_STR(DebugInfo); +} + +} diff --git a/vendor/lief/api/python/src/PDB/pyFunction.cpp b/vendor/lief/api/python/src/PDB/pyFunction.cpp new file mode 100644 index 0000000..b869a6a --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyFunction.cpp @@ -0,0 +1,43 @@ +#include +#include "LIEF/PDB/Function.hpp" +#include "LIEF/DebugDeclOpt.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ clazz(m, "Function", + R"doc( + )doc"_doc + ); + clazz + .def_prop_ro("name", &pdb::Function::name, + "Name of the function"_doc) + + .def_prop_ro("RVA", &pdb::Function::RVA, + "The **Relative** Virtual Address of the function"_doc) + + .def_prop_ro("code_size", &pdb::Function::code_size, + "The size of the function"_doc) + + .def_prop_ro("section_name", &pdb::Function::section_name, + "The name of the section in which this function is defined"_doc) + + .def_prop_ro("debug_location", &pdb::Function::debug_location, + "Original source code location."_doc) + + .def("to_decl", + [] (const pdb::Function& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for this function"_doc, + "opt"_a.none() = nb::none()) + + LIEF_DEFAULT_STR(Function); + +} + +} diff --git a/vendor/lief/api/python/src/PDB/pyPDB.hpp b/vendor/lief/api/python/src/PDB/pyPDB.hpp new file mode 100644 index 0000000..ea335b6 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyPDB.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_DBG_PDB_H +#define PY_LIEF_DBG_PDB_H +#include "pyLIEF.hpp" + +namespace LIEF::pdb::py { + +namespace pdb = LIEF::pdb; + +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/PDB/pyPublicSymbol.cpp b/vendor/lief/api/python/src/PDB/pyPublicSymbol.cpp new file mode 100644 index 0000000..23a1b7d --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyPublicSymbol.cpp @@ -0,0 +1,42 @@ +#include +#include "LIEF/PDB/PublicSymbol.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ clazz(m, "PublicSymbol", + R"doc( + This class provides general information (RVA, name) about a symbol + from the PDB's public symbol stream (or Public symbol hash stream) + )doc"_doc + ); + clazz + .def_prop_ro("name", &PublicSymbol::name, + "Name of the symbol"_doc) + + .def_prop_ro("section_name", &PublicSymbol::section_name, + R"doc( + Name of the section in which this symbol is defined (e.g. ``.text``). + This function returns an empty string if the section's name can't be found + )doc"_doc + ) + + .def_prop_ro("RVA", &PublicSymbol::RVA, + R"doc( + **Relative** Virtual Address of this symbol. + + This function returns 0 if the RVA can't be computed. + )doc"_doc + ) + + .def_prop_ro("demangled_name", &PublicSymbol::demangled_name, + "Demangled representation of the symbol"_doc) + + LIEF_DEFAULT_STR(PublicSymbol); +} + +} diff --git a/vendor/lief/api/python/src/PDB/pyType.cpp b/vendor/lief/api/python/src/PDB/pyType.cpp new file mode 100644 index 0000000..0698b20 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyType.cpp @@ -0,0 +1,79 @@ +#include "PDB/pyPDB.hpp" +#include "LIEF/PDB/Type.hpp" + +#include +#include + +namespace LIEF::pdb::types { +class Simple; +class Array; +class BitField; +class ClassLike; +class Enum; +class Function; +class Modifier; +class Pointer; +class Union; +} + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::module_ types = m.def_submodule("types", "PDB Types"_doc); + nb::class_ type(m, "Type", + R"doc()doc"_doc + ); + + nb::enum_(type, "KIND") + .value("UNKNOWN", Type::KIND::UNKNOWN) + .value("CLASS", Type::KIND::CLASS) + .value("POINTER", Type::KIND::POINTER) + .value("SIMPLE", Type::KIND::SIMPLE) + .value("ENUM", Type::KIND::ENUM) + .value("FUNCTION", Type::KIND::FUNCTION) + .value("MODIFIER", Type::KIND::MODIFIER) + .value("BITFIELD", Type::KIND::BITFIELD) + .value("ARRAY", Type::KIND::ARRAY) + .value("UNION", Type::KIND::UNION) + .value("STRUCTURE", Type::KIND::STRUCTURE) + .value("INTERFACE", Type::KIND::INTERFACE) + ; + + type + .def_prop_ro("kind", &pdb::Type::kind, + R"doc( + Discriminator for the type's subclasses + )doc"_doc + ) + + .def_prop_ro("name", &pdb::Type::name, + "Type's name (if present)"_doc + ) + + .def_prop_ro("size", &pdb::Type::size, + R"doc( + Size of the type. This size should match the value of ``sizeof(...)`` + applied to this type. + )doc"_doc + ) + + .def("to_decl", + [] (const pdb::Type& self, const DeclOpt* opt) { + return opt ? self.to_decl(*opt) : self.to_decl(); + }, + "Generates a C/C++ definition for this type"_doc, + "opt"_a.none() = nb::none() + ) + ; + + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); + create(types); +} +} diff --git a/vendor/lief/api/python/src/PDB/pyType.hpp b/vendor/lief/api/python/src/PDB/pyType.hpp new file mode 100644 index 0000000..a329355 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyType.hpp @@ -0,0 +1,67 @@ +#pragma once + +#include + +#include "LIEF/PDB/types/Simple.hpp" +#include "LIEF/PDB/types/Array.hpp" +#include "LIEF/PDB/types/BitField.hpp" +#include "LIEF/PDB/types/ClassLike.hpp" +#include "LIEF/PDB/types/Enum.hpp" +#include "LIEF/PDB/types/Function.hpp" +#include "LIEF/PDB/types/Modifier.hpp" +#include "LIEF/PDB/types/Pointer.hpp" +#include "LIEF/PDB/types/Union.hpp" + +namespace nanobind::detail { +template<> struct type_hook { + static const std::type_info* get(const LIEF::pdb::Type *src) { + using namespace LIEF::pdb::types; + if (src) { + if (Simple::classof(src)) { + return &typeid(Simple); + } + + if (Array::classof(src)) { + return &typeid(Array); + } + + if (BitField::classof(src)) { + return &typeid(BitField); + } + + if (Class::classof(src)) { + return &typeid(Class); + } + + if (Structure::classof(src)) { + return &typeid(Structure); + } + + if (Interface::classof(src)) { + return &typeid(Interface); + } + + if (Enum::classof(src)) { + return &typeid(Enum); + } + + if (Function::classof(src)) { + return &typeid(Function); + } + + if (Modifier::classof(src)) { + return &typeid(Modifier); + } + + if (Pointer::classof(src)) { + return &typeid(Pointer); + } + + if (Union::classof(src)) { + return &typeid(Union); + } + } + return &typeid(LIEF::pdb::Type); + } +}; +} diff --git a/vendor/lief/api/python/src/PDB/pyUtils.cpp b/vendor/lief/api/python/src/PDB/pyUtils.cpp new file mode 100644 index 0000000..5134121 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/pyUtils.cpp @@ -0,0 +1,31 @@ +/* Copyright 2025 - 2026 R. Thomas + * Copyright 2025 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PDB/pyPDB.hpp" +#include "LIEF/PDB/utils.hpp" + +#include "nanobind/extra/stl/pathlike.h" +#include + +namespace LIEF::pdb::py { + +void init_utils(nb::module_&) { + lief_mod->def("is_pdb", [] (nb::PathLike path) { + return is_pdb(path); + }, + "Check if the given file is a ``PDB``"_doc, "file"_a + ); +} +} diff --git a/vendor/lief/api/python/src/PDB/types/CMakeLists.txt b/vendor/lief/api/python/src/PDB/types/CMakeLists.txt new file mode 100644 index 0000000..611380c --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/CMakeLists.txt @@ -0,0 +1,13 @@ +target_sources(pyLIEF PRIVATE + pySimple.cpp + pyAttribute.cpp + pyMethod.cpp + pyArray.cpp + pyBitField.cpp + pyClassLike.cpp + pyEnum.cpp + pyFunction.cpp + pyModifier.cpp + pyPointer.cpp + pyUnion.cpp +) diff --git a/vendor/lief/api/python/src/PDB/types/pyArray.cpp b/vendor/lief/api/python/src/PDB/types/pyArray.cpp new file mode 100644 index 0000000..058f639 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyArray.cpp @@ -0,0 +1,31 @@ +#include "LIEF/PDB/types/Array.hpp" +#include "PDB/pyPDB.hpp" + +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + using Array = pdb::types::Array; + nb::class_ type(m, "Array", + R"doc( + This class represents a ``LF_ARRAY`` PDB type. + )doc"_doc + ); + + type + .def_prop_ro("numberof_elements", &Array::numberof_elements, + "Number of elements in this array"_doc + ) + + .def_prop_ro("element_type", &Array::element_type, + "Type of the elements"_doc + ) + + .def_prop_ro("index_type", &Array::index_type, + "Type of the index"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyAttribute.cpp b/vendor/lief/api/python/src/PDB/types/pyAttribute.cpp new file mode 100644 index 0000000..865c627 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyAttribute.cpp @@ -0,0 +1,38 @@ +#include "LIEF/PDB/types/Attribute.hpp" +#include "PDB/pyPDB.hpp" +#include "PDB/pyType.hpp" + +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Attribute", + R"doc( + This class represents an attribute (``LF_MEMBER``) in an aggregate (class, + struct, union, ...) + )doc"_doc + ); + + type + .def_prop_ro("name", &pdb::types::Attribute::name, + R"doc( + Name of this attribute. + )doc"_doc + ) + + .def_prop_ro("type", &pdb::types::Attribute::type, + R"doc( + Type of this attribute + )doc"_doc + ) + .def_prop_ro("field_offset", &pdb::types::Attribute::field_offset, + R"doc( + Offset of this attribute in the aggregate + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyBitField.cpp b/vendor/lief/api/python/src/PDB/types/pyBitField.cpp new file mode 100644 index 0000000..74eb8e1 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyBitField.cpp @@ -0,0 +1,14 @@ +#include "LIEF/PDB/types/BitField.hpp" +#include "PDB/pyPDB.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "BitField", + R"doc( + This class represents a ``LF_BITFIELD`` PDB type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyClassLike.cpp b/vendor/lief/api/python/src/PDB/types/pyClassLike.cpp new file mode 100644 index 0000000..389fd04 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyClassLike.cpp @@ -0,0 +1,71 @@ +#include "LIEF/PDB/types/ClassLike.hpp" +#include "LIEF/PDB/types/Attribute.hpp" +#include "LIEF/PDB/types/Method.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "ClassLike", + R"doc( + This class abstracts the following PDB types: ``LF_STRUCTURE``, ``LF_INTERFACE``, + ``LF_CLASS`` or ``LF_UNION``. + )doc"_doc + ); + + type + .def_prop_ro("attributes", + [] (pdb::types::ClassLike& self) { + auto attrs = LIEF::py::owning_range(self.attributes()); + return nb::make_iterator( + nb::type(), "attributes_it", attrs); + }, + R"doc( + Return an iterator over the different attributes defined in this class-like type + )doc"_doc, nb::keep_alive<0, 1>()) + + .def_prop_ro("methods", + [] (pdb::types::ClassLike& self) { + auto methods = LIEF::py::owning_range(self.methods()); + return nb::make_iterator( + nb::type(), "methods_it", methods); + }, + R"doc( + Return an iterator over the different methods implemented in this class-like type + )doc"_doc, nb::keep_alive<0, 1>()) + + .def_prop_ro("unique_name", &pdb::types::ClassLike::unique_name, + R"doc( + Mangled type name. + )doc"_doc + ) + ; + + nb::class_ clazz(m, "Class", + R"doc( + Interface for the ``LF_CLASS`` PDB type + )doc"_doc + ); + + nb::class_ structure(m, "Structure", + R"doc( + Interface for the ``LF_STRUCTURE`` PDB type + )doc"_doc + ); + nb::class_ Interface(m, "Interface", + R"doc( + Interface for the ``LF_INTERFACE`` PDB type + )doc"_doc + ); + + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyEnum.cpp b/vendor/lief/api/python/src/PDB/types/pyEnum.cpp new file mode 100644 index 0000000..d3724ab --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyEnum.cpp @@ -0,0 +1,57 @@ +#include "LIEF/PDB/types/Enum.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + using Enum = pdb::types::Enum; + nb::class_ type(m, "Enum", + R"doc( + This class represents a ``LF_ENUM`` PDB type + )doc"_doc + ); + + nb::class_ entry(type, "Entry", + R"doc( + This class represents an enum entry which is essentially composed of a name + and its value (integer). + )doc"_doc + ); + + entry + .def_prop_ro("name", &Enum::Entry::name, + "Enum entry's name"_doc + ) + + .def_prop_ro("value", &Enum::Entry::value, + "Enum entry's value (if any)"_doc + ) + ; + + type + .def_prop_ro("unique_name", &Enum::unique_name, + "Enum's mangled name"_doc + ) + + .def_prop_ro("entries", &Enum::entries, + "Return the different entries associated with this enum"_doc + ) + + .def_prop_ro("underlying_type", &Enum::underlying_type, + "The underlying type that is used to encode this enum"_doc + ) + + .def("find_entry", &Enum::find_entry, + "Try to find the enum matching the given value"_doc, + "value"_a + ) + ; + +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyFunction.cpp b/vendor/lief/api/python/src/PDB/types/pyFunction.cpp new file mode 100644 index 0000000..91ac896 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyFunction.cpp @@ -0,0 +1,27 @@ +#include "LIEF/PDB/types/Function.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + using Function = pdb::types::Function; + nb::class_ type(m, "Function", + R"doc( + This class represents a ``LF_PROCEDURE`` PDB type + )doc"_doc + ); + + type + .def_prop_ro("return_type", &Function::return_type, + "Type returned by this function"_doc + ) + + .def_prop_ro("parameters", &Function::parameters, + "Types of the function's parameters"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyMethod.cpp b/vendor/lief/api/python/src/PDB/types/pyMethod.cpp new file mode 100644 index 0000000..51ae7d6 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyMethod.cpp @@ -0,0 +1,48 @@ +#include "LIEF/PDB/types/Method.hpp" +#include "PDB/pyPDB.hpp" + +#include +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + using Method = pdb::types::Method; + + nb::class_ method(m, "Method", + R"doc( + This class represents a Method (``LF_ONEMETHOD``) that can be defined in + ClassLike PDB type + )doc"_doc + ); + + nb::enum_(method, "TYPE") + .value("VANILLA", Method::TYPE::VANILLA, "Regular instance method") + .value("VIRTUAL", Method::TYPE::VIRTUAL, "Virtual method") + .value("STATIC", Method::TYPE::STATIC, "Static method") + .value("FRIEND", Method::TYPE::FRIEND, "Friend method") + .value("INTRODUCING_VIRTUAL", Method::TYPE::INTRODUCING_VIRTUAL, + "Virtual method that introduces a new vtable slot") + .value("PURE_VIRTUAL", Method::TYPE::PURE_VIRTUAL, "Pure virtual method (abstract)") + .value("PURE_INTRODUCING_VIRTUAL", Method::TYPE::PURE_INTRODUCING_VIRTUAL, + "Pure virtual method that introduces a new vtable slot"); + + nb::enum_(method, "ACCESS") + .value("NONE", Method::ACCESS::NONE, "No access specifier (or unknown)") + .value("PRIVATE", Method::ACCESS::PRIVATE, "Private access") + .value("PROTECTED", Method::ACCESS::PROTECTED, "Protected access") + .value("PUBLIC", Method::ACCESS::PUBLIC, "Public access"); + + method + .def_prop_ro("name", &Method::name, + "Name of the method"_doc) + + .def_prop_ro("type", &Method::type, + "Type/Properties of the method (virtual, static, etc.)"_doc) + + .def_prop_ro("access", &Method::access, + "Visibility access (public, private, ...)"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyModifier.cpp b/vendor/lief/api/python/src/PDB/types/pyModifier.cpp new file mode 100644 index 0000000..2a1e373 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyModifier.cpp @@ -0,0 +1,25 @@ +#include "LIEF/PDB/types/Modifier.hpp" +#include "PDB/pyPDB.hpp" +#include "PDB/pyType.hpp" + +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Modifier", + R"doc( + This class represents a ``LF_MODIFIER`` PDB type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &pdb::types::Modifier::underlying_type, + R"doc( + Underlying type targeted by this modifier + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyPointer.cpp b/vendor/lief/api/python/src/PDB/types/pyPointer.cpp new file mode 100644 index 0000000..67dabe4 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyPointer.cpp @@ -0,0 +1,25 @@ +#include "LIEF/PDB/types/Pointer.hpp" +#include "PDB/pyPDB.hpp" +#include "PDB/pyType.hpp" + +#include + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Pointer", + R"doc( + This class represents a ``LF_POINTER`` PDB type + )doc"_doc + ); + + type + .def_prop_ro("underlying_type", &pdb::types::Pointer::underlying_type, + R"doc( + The underlying type pointed to by this pointer + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pySimple.cpp b/vendor/lief/api/python/src/PDB/types/pySimple.cpp new file mode 100644 index 0000000..5c121d3 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pySimple.cpp @@ -0,0 +1,107 @@ +#include "LIEF/PDB/types/Simple.hpp" +#include "PDB/pyPDB.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + using Simple = pdb::types::Simple; + + nb::class_ type(m, "Simple", + R"doc( + This class represents primitive types (int, float, ...) which are + also named *simple* types in the PDB format. + )doc"_doc + ); + + nb::enum_(type, "TYPES") + .value("UNKNOWN", Simple::TYPES::UNKNOWN) + .value("VOID", Simple::TYPES::VOID_, "Void type (return type or void*)") + + .value("SCHAR", Simple::TYPES::SCHAR, "Signed Character") + .value("UCHAR", Simple::TYPES::UCHAR, "Unsigned Character") + .value("RCHAR", Simple::TYPES::RCHAR, "'Real' Character (char)") + + .value("WCHAR", Simple::TYPES::WCHAR, "Wide Character (wchar_t)") + .value("CHAR16", Simple::TYPES::CHAR16, "16-bit Character (char16_t)") + .value("CHAR32", Simple::TYPES::CHAR32, "32-bit Character (char32_t)") + .value("CHAR8", Simple::TYPES::CHAR8, "8-bit Character (char8_t)") + + .value("SBYTE", Simple::TYPES::SBYTE, "Signed Byte") + .value("UBYTE", Simple::TYPES::UBYTE, "Unsigned Byte") + + .value("SSHORT", Simple::TYPES::SSHORT, "Signed Short") + .value("USHORT", Simple::TYPES::USHORT, "Unsigned Short") + + .value("SINT16", Simple::TYPES::SINT16, "Explicit Signed 16-bit Integer") + .value("UINT16", Simple::TYPES::UINT16, "Explicit Unsigned 16-bit Integer") + + .value("SLONG", Simple::TYPES::SLONG, "Signed Long") + .value("ULONG", Simple::TYPES::ULONG, "Unsigned Long") + + .value("SINT32", Simple::TYPES::SINT32, "Explicit Signed 32-bit Integer") + .value("UINT32", Simple::TYPES::UINT32, "Explicit Unsigned 32-bit Integer") + + .value("SQUAD", Simple::TYPES::SQUAD, "Signed Quadword") + .value("UQUAD", Simple::TYPES::UQUAD, "Unsigned Quadword") + + .value("SINT64", Simple::TYPES::SINT64, "Explicit Signed 64-bit Integer") + .value("UINT64", Simple::TYPES::UINT64, "Explicit Unsigned 64-bit Integer") + + .value("SOCTA", Simple::TYPES::SOCTA, "Signed Octaword") + .value("UOCTA", Simple::TYPES::UOCTA, "Unsigned Octaword") + + .value("SINT128", Simple::TYPES::SINT128, "Explicit Signed 128-bit Integer") + .value("UINT128", Simple::TYPES::UINT128, "Explicit Unsigned 128-bit Integer") + + .value("FLOAT16", Simple::TYPES::FLOAT16, "16-bit Floating point") + .value("FLOAT32", Simple::TYPES::FLOAT32, "32-bit Floating point (float)") + .value("FLOAT32_PARTIAL_PRECISION", Simple::TYPES::FLOAT32_PARTIAL_PRECISION) + + .value("FLOAT48", Simple::TYPES::FLOAT48, "48-bit Floating point") + .value("FLOAT64", Simple::TYPES::FLOAT64, "64-bit Floating point (double)") + .value("FLOAT80", Simple::TYPES::FLOAT80, "80-bit Floating point") + .value("FLOAT128", Simple::TYPES::FLOAT128, "128-bit Floating point") + + .value("COMPLEX16", Simple::TYPES::COMPLEX16) + .value("COMPLEX32", Simple::TYPES::COMPLEX32) + .value("COMPLEX32_PARTIAL_PRECISION", Simple::TYPES::COMPLEX32_PARTIAL_PRECISION) + .value("COMPLEX48", Simple::TYPES::COMPLEX48) + .value("COMPLEX64", Simple::TYPES::COMPLEX64) + .value("COMPLEX80", Simple::TYPES::COMPLEX80) + .value("COMPLEX128", Simple::TYPES::COMPLEX128) + + .value("BOOL8", Simple::TYPES::BOOL8, "8-bit Boolean") + .value("BOOL16", Simple::TYPES::BOOL16, "16-bit Boolean") + .value("BOOL32", Simple::TYPES::BOOL32, "32-bit Boolean") + .value("BOOL64", Simple::TYPES::BOOL64, "64-bit Boolean") + .value("BOOL128", Simple::TYPES::BOOL128, "128-bit Boolean"); + + + nb::enum_(type, "MODES") + .value("DIRECT", Simple::MODES::DIRECT, "Not a pointer (direct access)") + .value("FAR_POINTER", Simple::MODES::FAR_POINTER, "Far pointer") + .value("HUGE_POINTER", Simple::MODES::HUGE_POINTER, "Huge pointer") + .value("NEAR_POINTER32", Simple::MODES::NEAR_POINTER32, "32-bit Near pointer") + .value("FAR_POINTER32", Simple::MODES::FAR_POINTER32, "32-bit Far pointer") + .value("NEAR_POINTER64", Simple::MODES::NEAR_POINTER64, "64-bit Near pointer") + .value("NEAR_POINTER128", Simple::MODES::NEAR_POINTER128, "128-bit Near pointer"); + + type + .def_prop_ro("type", &Simple::type, + "Returns the underlying primitive type."_doc + ) + + .def_prop_ro("modes", &Simple::modes, + "Returns the mode (pointer type) of this Simple type."_doc + ) + + .def_prop_ro("is_pointer", &Simple::is_pointer, + "Check if this simple type is a pointer."_doc + ) + + .def_prop_ro("is_signed", &Simple::is_pointer, + "Check if the underlying type is signed."_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PDB/types/pyUnion.cpp b/vendor/lief/api/python/src/PDB/types/pyUnion.cpp new file mode 100644 index 0000000..5969076 --- /dev/null +++ b/vendor/lief/api/python/src/PDB/types/pyUnion.cpp @@ -0,0 +1,14 @@ +#include "LIEF/PDB/types/Union.hpp" +#include "PDB/pyPDB.hpp" + +namespace LIEF::pdb::py { +template<> +void create(nb::module_& m) { + nb::class_ type(m, "Union", + R"doc( + This class represents a ``LF_UNION`` PDB type + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/CMakeLists.txt b/vendor/lief/api/python/src/PE/CMakeLists.txt new file mode 100644 index 0000000..0c773d1 --- /dev/null +++ b/vendor/lief/api/python/src/PE/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + enums.cpp + pyUtils.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/PE/enums.cpp b/vendor/lief/api/python/src/PE/enums.cpp new file mode 100644 index 0000000..4f22234 --- /dev/null +++ b/vendor/lief/api/python/src/PE/enums.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyPE.hpp" +#include "LIEF/PE/enums.hpp" +#include "LIEF/PE/EnumToString.hpp" +#include "enums_wrapper.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { +void init_enums(nb::module_& m) { + + enum_(m, "PE_TYPE") + .value(PY_ENUM(PE_TYPE::PE32)) + .value(PY_ENUM(PE_TYPE::PE32_PLUS)); + + enum_(m, "ALGORITHMS") + .value(PY_ENUM(ALGORITHMS::UNKNOWN)) + .value(PY_ENUM(ALGORITHMS::SHA_512)) + .value(PY_ENUM(ALGORITHMS::SHA_384)) + .value(PY_ENUM(ALGORITHMS::SHA_256)) + .value(PY_ENUM(ALGORITHMS::SHA_1)) + .value(PY_ENUM(ALGORITHMS::MD5)) + .value(PY_ENUM(ALGORITHMS::MD4)) + .value(PY_ENUM(ALGORITHMS::MD2)) + .value(PY_ENUM(ALGORITHMS::RSA)) + .value(PY_ENUM(ALGORITHMS::EC)) + + .value(PY_ENUM(ALGORITHMS::MD5_RSA)) + .value(PY_ENUM(ALGORITHMS::SHA1_DSA)) + .value(PY_ENUM(ALGORITHMS::SHA1_RSA)) + + .value(PY_ENUM(ALGORITHMS::SHA_256_RSA)) + .value(PY_ENUM(ALGORITHMS::SHA_384_RSA)) + .value(PY_ENUM(ALGORITHMS::SHA_512_RSA)) + + .value(PY_ENUM(ALGORITHMS::SHA1_ECDSA)) + .value(PY_ENUM(ALGORITHMS::SHA_256_ECDSA)) + .value(PY_ENUM(ALGORITHMS::SHA_384_ECDSA)) + .value(PY_ENUM(ALGORITHMS::SHA_512_ECDSA)); +} +} diff --git a/vendor/lief/api/python/src/PE/enums.hpp b/vendor/lief/api/python/src/PE/enums.hpp new file mode 100644 index 0000000..606f200 --- /dev/null +++ b/vendor/lief/api/python/src/PE/enums.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_PE_ENUMS_H +#define PY_LIEF_PE_ENUMS_H +#include "pyLIEF.hpp" + +namespace LIEF::PE::py { +void init_enums(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/PE/init.cpp b/vendor/lief/api/python/src/PE/init.cpp new file mode 100644 index 0000000..ce52c90 --- /dev/null +++ b/vendor/lief/api/python/src/PE/init.cpp @@ -0,0 +1,148 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/init.hpp" +#include "PE/enums.hpp" +#include "PE/pyPE.hpp" + +#include "LIEF/PE/Binary.hpp" +#include "LIEF/PE/CodeIntegrity.hpp" +#include "LIEF/PE/Export.hpp" +#include "LIEF/PE/LoadConfigurations.hpp" +#include "LIEF/PE/Parser.hpp" +#include "LIEF/PE/ParserConfig.hpp" +#include "LIEF/PE/RelocationEntry.hpp" +#include "LIEF/PE/ExceptionInfo.hpp" +#include "LIEF/PE/RichHeader.hpp" +#include "LIEF/PE/TLS.hpp" +#include "LIEF/PE/debug/CodeView.hpp" +#include "LIEF/PE/debug/Repro.hpp" +#include "LIEF/PE/debug/FPO.hpp" +#include "LIEF/PE/debug/ExDllCharacteristics.hpp" +#include "LIEF/PE/debug/VCFeature.hpp" +#include "LIEF/PE/debug/CodeViewPDB.hpp" +#include "LIEF/PE/debug/Pogo.hpp" +#include "LIEF/PE/debug/PogoEntry.hpp" +#include "LIEF/PE/debug/PDBChecksum.hpp" +#include "LIEF/PE/resources/langs.hpp" +#include "LIEF/PE/signature/attributes.hpp" +#include "LIEF/PE/signature/PKCS9TSTInfo.hpp" +#include "LIEF/PE/signature/SpcIndirectData.hpp" +#include "LIEF/PE/signature/GenericContent.hpp" + +#define CREATE(X,Y) create(Y) + +namespace LIEF::PE::py { + +void init_resources(nb::module_& m) { + CREATE(ResourcesManager, m); + CREATE(ResourceNode, m); + CREATE(ResourceData, m); + CREATE(ResourceDirectory, m); + CREATE(ResourceVersion, m); + CREATE(ResourceStringTable, m); + CREATE(ResourceStringFileInfo, m); + CREATE(ResourceVar, m); + CREATE(ResourceVarFileInfo, m); + CREATE(ResourceIcon, m); + CREATE(ResourceDialog, m); + CREATE(ResourceDialogExtended, m); + CREATE(ResourceDialogRegular, m); + CREATE(ResourceAccelerator, m); + CREATE(RESOURCE_LANGS, m); +} + +void init_load_configs(nb::module_& m) { + CREATE(LoadConfiguration, m); +} + +void init_debug(nb::module_& m) { + CREATE(Debug, m); + CREATE(CodeView, m); + CREATE(CodeViewPDB, m); + CREATE(Repro, m); + CREATE(Pogo, m); + CREATE(PogoEntry, m); + CREATE(PDBChecksum, m); + CREATE(VCFeature, m); + CREATE(ExDllCharacteristics, m); + CREATE(FPO, m); +} + +void init_signature(nb::module_& m) { + CREATE(Signature, m); + CREATE(RsaInfo, m); + CREATE(x509, m); + CREATE(ContentInfo, m); + CREATE(GenericContent, m); + CREATE(SpcIndirectData, m); + CREATE(SignerInfo, m); + CREATE(CodeIntegrity, m); + CREATE(Attribute, m); + CREATE(ContentType, m); + CREATE(GenericType, m); + CREATE(MsSpcNestedSignature, m); + CREATE(MsSpcStatementType, m); + CREATE(MsManifestBinaryID, m); + CREATE(PKCS9AtSequenceNumber, m); + CREATE(PKCS9CounterSignature, m); + CREATE(PKCS9MessageDigest, m); + CREATE(PKCS9SigningTime, m); + CREATE(SpcSpOpusInfo, m); + CREATE(MsCounterSign, m); + CREATE(SpcRelaxedPeMarkerCheck, m); + CREATE(SigningCertificateV2, m); + CREATE(PKCS9TSTInfo, m); +} + +void init_objects(nb::module_& m) { + CREATE(ParserConfig, m); + CREATE(Parser, m); + + CREATE(DosHeader, m); + CREATE(Header, m); + CREATE(OptionalHeader, m); + CREATE(RichHeader, m); + CREATE(RichEntry, m); + CREATE(DataDirectory, m); + CREATE(Section, m); + CREATE(Relocation, m); + CREATE(RelocationEntry, m); + CREATE(Export, m); + CREATE(ExportEntry, m); + CREATE(TLS, m); + CREATE(Import, m); + CREATE(ImportEntry, m); + CREATE(DelayImport, m); + CREATE(DelayImportEntry, m); + CREATE(ExceptionInfo, m); + { + init_debug(m); + init_resources(m); + init_signature(m); + init_load_configs(m); + } + CREATE(Binary, m); + CREATE(Builder, m); + CREATE(Factory, m); +} + +void init(nb::module_& m) { + nb::module_ pe_mod = m.def_submodule("PE", "Python API for the PE format"); + init_enums(pe_mod); + init_objects(pe_mod); + init_utils(pe_mod); +} +} diff --git a/vendor/lief/api/python/src/PE/init.hpp b/vendor/lief/api/python/src/PE/init.hpp new file mode 100644 index 0000000..c4ee8ce --- /dev/null +++ b/vendor/lief/api/python/src/PE/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_PE_INIT_H +#define PY_LIEF_PE_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::PE::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/PE/objects/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/CMakeLists.txt new file mode 100644 index 0000000..4543a0b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/CMakeLists.txt @@ -0,0 +1,33 @@ +target_sources(pyLIEF PRIVATE + pyBinary.cpp + pyBuilder.cpp + pyCodeIntegrity.cpp + pyDataDirectory.cpp + pyDelayImport.cpp + pyDelayImportEntry.cpp + pyDosHeader.cpp + pyExceptionInfo.cpp + pyExport.cpp + pyExportEntry.cpp + pyFactory.cpp + pyHeader.cpp + pyImport.cpp + pyImportEntry.cpp + pyLang.cpp + pyOptionalHeader.cpp + pyParser.cpp + pyParserConfig.cpp + pyRelocation.cpp + pyRelocationEntry.cpp + pyResourcesManager.cpp + pyRichEntry.cpp + pyRichHeader.cpp + pySection.cpp + pyTLS.cpp +) + +add_subdirectory(resources) +add_subdirectory(signature) +add_subdirectory(LoadConfigurations) +add_subdirectory(debug) +add_subdirectory(exceptions_info) diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/CMakeLists.txt new file mode 100644 index 0000000..4bfaf70 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + pyMetadata.cpp + pyMetadataARM64.cpp + pyMetadataX86.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadata.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadata.cpp new file mode 100644 index 0000000..56a0ed9 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadata.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/Metadata.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include +#include + +namespace LIEF::PE { +class CHPEMetadataARM64; +class CHPEMetadataX86; +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ meta(m, "CHPEMetadata", + R"delim( + Base class for any Compiled Hybrid Portable Executable (CHPE) metadata. + + This class is inherited by architecture-specific implementation. + )delim"_doc); + + nb::enum_(meta, "KIND", + "Discriminator for the subclasses"_doc + ) + .value("UNKNOWN", CHPEMetadata::KIND::UNKNOWN) + .value("ARM64", CHPEMetadata::KIND::ARM64) + .value("X86", CHPEMetadata::KIND::X86); + + meta + .def_prop_ro("version", &CHPEMetadata::version, + "Version of the structure"_doc + ) + .def_prop_ro("kind", &CHPEMetadata::kind, + "Determine the type of the concrete implementation" + ) + LIEF_CLONABLE(CHPEMetadata) + LIEF_DEFAULT_STR(CHPEMetadata); + + create(m); + create(m); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataARM64.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataARM64.cpp new file mode 100644 index 0000000..7e99deb --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataARM64.cpp @@ -0,0 +1,231 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/MetadataARM64.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include + +#include "pyIterator.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ meta(m, "CHPEMetadataARM64", + R"doc( + This class represents ARM64-specific metadata used in CHPE + (Compatible Hybrid PE) binaries, particularly for hybrid architectures like + ARM64EC and ARM64X. + + It extends the :class:`~.CHPEMetadata` base class and provides access to metadata + describing code ranges, redirections, entry points, and other hybrid-specific + information relevant for binary analysis. + )doc"_doc); + + init_ref_iterator(meta, "it_range_entries"); + init_ref_iterator(meta, "it_redirection_entries"); + init_ref_iterator(meta, "it_code_range_entry_point"); + + /* Code range */ { + using range_entry_t = CHPEMetadataARM64::range_entry_t; + nb::class_ range(meta, "range_entry_t", + "Structure that describes architecture-specific ranges"_doc + ); + nb::enum_(range, "TYPE") + .value("ARM64", range_entry_t::TYPE::ARM64, "Pure ARM64 code"_doc) + .value("ARM64EC", range_entry_t::TYPE::ARM64EC, + "ARM64EC hybrid code (compatible with x64)."_doc) + .value("AMD64", range_entry_t::TYPE::AMD64, "x64 code"_doc); + + range + .def_rw("start_offset", &range_entry_t::start_offset, + "Raw data (includes start RVA and type)"_doc + ) + .def_rw("length", &range_entry_t::length, + "Range's length"_doc + ) + .def_prop_ro("type", &range_entry_t::type, + "Architecture for this range"_doc + ) + .def_prop_ro("start", &range_entry_t::start, + "Start of the range (RVA)"_doc + ) + .def_prop_ro("end", &range_entry_t::end, + "End of the range (RVA)"_doc + ) + ; + } + + /* Redirection Entry */ { + using redirection_entry_t = CHPEMetadataARM64::redirection_entry_t; + nb::class_(meta, "redirection_entry_t", + "Structure that describes a redirection"_doc + ) + .def_rw("src", &redirection_entry_t::src) + .def_rw("dst", &redirection_entry_t::dst) + ; + } + + /* Code range entrypoint */ { + using code_range_entry_point_t = CHPEMetadataARM64::code_range_entry_point_t; + nb::class_(meta, "code_range_entry_point_t", + R"doc( + Mirror of `IMAGE_ARM64EC_CODE_RANGE_ENTRY_POINT`: + Represents a mapping between code range and its entry point. + )doc"_doc + ) + .def_rw("start_rva", &code_range_entry_point_t::start_rva, + "Start of the code range."_doc + ) + .def_rw("end_rva", &code_range_entry_point_t::end_rva, + "End of the code range (RVA)."_doc + ) + .def_rw("entrypoint", &code_range_entry_point_t::entrypoint, + "RVA of the entry point for this range."_doc + ) + ; + } + + meta + .def_prop_rw("code_map", + nb::overload_cast<>(&CHPEMetadataARM64::code_map, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::code_map), + nb::rv_policy::reference_internal) + + .def_prop_rw("code_map_count", + nb::overload_cast<>(&CHPEMetadataARM64::code_map_count, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::code_map_count), + nb::rv_policy::reference_internal) + + .def_prop_rw("code_ranges_to_entrypoints", + nb::overload_cast<>(&CHPEMetadataARM64::code_ranges_to_entrypoints, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::code_ranges_to_entrypoints), + nb::rv_policy::reference_internal) + + .def_prop_rw("redirection_metadata", + nb::overload_cast<>(&CHPEMetadataARM64::redirection_metadata, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::redirection_metadata), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_call_no_redirect", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_call_no_redirect, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_call_no_redirect), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_ret", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_ret, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_ret), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_call", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_call, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_call), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_icall", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_icall, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_icall), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_icall_cfg", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_icall_cfg, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_icall_cfg), + nb::rv_policy::reference_internal) + + .def_prop_rw("alternate_entry_point", + nb::overload_cast<>(&CHPEMetadataARM64::alternate_entry_point, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::alternate_entry_point), + nb::rv_policy::reference_internal) + + .def_prop_rw("auxiliary_iat", + nb::overload_cast<>(&CHPEMetadataARM64::auxiliary_iat, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::auxiliary_iat), + nb::rv_policy::reference_internal) + + .def_prop_rw("code_ranges_to_entry_points_count", + nb::overload_cast<>(&CHPEMetadataARM64::code_ranges_to_entry_points_count, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::code_ranges_to_entry_points_count), + nb::rv_policy::reference_internal) + + .def_prop_rw("redirection_metadata_count", + nb::overload_cast<>(&CHPEMetadataARM64::redirection_metadata_count, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::redirection_metadata_count), + nb::rv_policy::reference_internal) + + .def_prop_rw("get_x64_information_function_pointer", + nb::overload_cast<>(&CHPEMetadataARM64::get_x64_information_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::get_x64_information_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("set_x64_information_function_pointer", + nb::overload_cast<>(&CHPEMetadataARM64::set_x64_information_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::set_x64_information_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("extra_rfe_table", + nb::overload_cast<>(&CHPEMetadataARM64::extra_rfe_table, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::extra_rfe_table), + nb::rv_policy::reference_internal) + + .def_prop_rw("extra_rfe_table_size", + nb::overload_cast<>(&CHPEMetadataARM64::extra_rfe_table_size, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::extra_rfe_table_size), + nb::rv_policy::reference_internal) + + .def_prop_rw("os_arm64x_dispatch_fptr", + nb::overload_cast<>(&CHPEMetadataARM64::os_arm64x_dispatch_fptr, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::os_arm64x_dispatch_fptr), + nb::rv_policy::reference_internal) + + .def_prop_rw("auxiliary_iat_copy", + nb::overload_cast<>(&CHPEMetadataARM64::auxiliary_iat_copy, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::auxiliary_iat_copy), + nb::rv_policy::reference_internal) + + .def_prop_rw("auxiliary_delay_import", + nb::overload_cast<>(&CHPEMetadataARM64::auxiliary_delay_import, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::auxiliary_delay_import), + nb::rv_policy::reference_internal) + + .def_prop_rw("auxiliary_delay_import_copy", + nb::overload_cast<>(&CHPEMetadataARM64::auxiliary_delay_import_copy, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::auxiliary_delay_import_copy), + nb::rv_policy::reference_internal) + + .def_prop_rw("bitfield_info", + nb::overload_cast<>(&CHPEMetadataARM64::bitfield_info, nb::const_), + nb::overload_cast(&CHPEMetadataARM64::bitfield_info), + nb::rv_policy::reference_internal) + + .def_prop_ro("code_ranges", + nb::overload_cast<>(&CHPEMetadataARM64::code_ranges), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + + .def_prop_ro("redirections", + nb::overload_cast<>(&CHPEMetadataARM64::redirections), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + + .def_prop_ro("code_range_entry_point", + nb::overload_cast<>(&CHPEMetadataARM64::code_range_entry_point), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + ; + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataX86.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataX86.cpp new file mode 100644 index 0000000..b648ce5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CHPEMetadata/pyMetadataX86.cpp @@ -0,0 +1,91 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/MetadataX86.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ meta(m, "CHPEMetadataX86", + R"doc( + This class represents hybrid metadata for X86. + )doc"_doc); + + meta + .def_prop_rw("chpe_code_address_range_offset", + nb::overload_cast<>(&CHPEMetadataX86::chpe_code_address_range_offset, nb::const_), + nb::overload_cast(&CHPEMetadataX86::chpe_code_address_range_offset), + nb::rv_policy::reference_internal) + + .def_prop_rw("chpe_code_address_range_count", + nb::overload_cast<>(&CHPEMetadataX86::chpe_code_address_range_count, nb::const_), + nb::overload_cast(&CHPEMetadataX86::chpe_code_address_range_count), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_exception_handler_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_exception_handler_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_exception_handler_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_call_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_call_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_call_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_indirect_call_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_indirect_call_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_indirect_call_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_indirect_call_cfg_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_indirect_call_cfg_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_indirect_call_cfg_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_ret_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_ret_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_ret_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_ret_leaf_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_ret_leaf_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_ret_leaf_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_dispatch_jump_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_dispatch_jump_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_dispatch_jump_function_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("compiler_iat_pointer", + nb::overload_cast<>(&CHPEMetadataX86::compiler_iat_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::compiler_iat_pointer), + nb::rv_policy::reference_internal) + + .def_prop_rw("wowa64_rdtsc_function_pointer", + nb::overload_cast<>(&CHPEMetadataX86::wowa64_rdtsc_function_pointer, nb::const_), + nb::overload_cast(&CHPEMetadataX86::wowa64_rdtsc_function_pointer), + nb::rv_policy::reference_internal) + ; +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CMakeLists.txt new file mode 100644 index 0000000..d4ae8a3 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + pyLoadConfiguration.cpp + pyEnclaveConfiguration.cpp + pyEnclaveImport.cpp + pyVolatileMetadata.cpp +) + +add_subdirectory(CHPEMetadata) +add_subdirectory(DynamicRelocation) diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/CMakeLists.txt new file mode 100644 index 0000000..04605cb --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/CMakeLists.txt @@ -0,0 +1,13 @@ +target_sources(pyLIEF PRIVATE + pyDynamicFixup.cpp + pyDynamicFixupARM64Kernel.cpp + pyDynamicFixupARM64X.cpp + pyDynamicFixupControlTransfer.cpp + pyDynamicFixupGeneric.cpp + pyDynamicFixupUnknown.cpp + pyDynamicRelocationBase.cpp + pyDynamicRelocationV1.cpp + pyDynamicRelocationV2.cpp + pyFunctionOverride.cpp + pyFunctionOverrideInfo.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixup.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixup.cpp new file mode 100644 index 0000000..f812882 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixup.cpp @@ -0,0 +1,89 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixup.hpp" + +#include +#include + +namespace LIEF::PE { +class DynamicFixupARM64Kernel; +class DynamicFixupARM64X; +class DynamicFixupControlTransfer; +class DynamicFixupGeneric; +class DynamicFixupUnknown; +class FunctionOverride; +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "DynamicFixup", + R"doc( + This is the base class for any fixups located in :class:`~lief.PE.DynamicRelocation` + )doc"_doc + ); + using KIND = DynamicFixup::KIND; + enum_(obj, "KIND") + .value("UNKNOWN", KIND::UNKNOWN, + R"doc( + If the :class:`~lief.PE.DynamicRelocation.symbol` is a special value that is not + supported by LIEF. + )doc"_doc + ) + .value("GENERIC", KIND::GENERIC, + R"doc( + If :class:`~lief.PE.DynamicRelocation.symbol` is not a special value. + )doc"_doc + ) + .value("ARM64X", KIND::ARM64X, + R"doc( + If :class:`~lief.PE.DynamicRelocation.symbol` is set to ``IMAGE_DYNAMIC_RELOCATION_ARM64X``. + )doc"_doc + ) + .value("FUNCTION_OVERRIDE", KIND::FUNCTION_OVERRIDE, + R"doc( + If :class:`~lief.PE.DynamicRelocation.symbol` is set to ``IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE``. + )doc"_doc + ) + .value("ARM64_KERNEL_IMPORT_CALL_TRANSFER", KIND::ARM64_KERNEL_IMPORT_CALL_TRANSFER, + R"doc( + If :class:`~lief.PE.DynamicRelocation.symbol` is set to ``IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER``. + )doc"_doc + ) + ; + + obj + .def_prop_ro("kind", &DynamicFixup::kind, + "Encoding of the fixups"_doc + ) + + LIEF_DEFAULT_STR(DynamicFixup) + LIEF_CLONABLE(DynamicFixup); + + create(m); + create(m); + create(m); + create(m); + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64Kernel.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64Kernel.cpp new file mode 100644 index 0000000..231de49 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64Kernel.cpp @@ -0,0 +1,80 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyIterator.hpp" +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupARM64Kernel.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ obj(m, "DynamicFixupARM64Kernel", + R"doc( + This class wraps fixups associated with the (special) symbol value: + ``IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER (8)``. + )doc"_doc + ); + + obj.def_ro_static("NO_IAT_INDEX",&DynamicFixupARM64Kernel::NO_IAT_INDEX); + + using IMPORT_TYPE = DynamicFixupARM64Kernel::IMPORT_TYPE; + nb::enum_(obj, "IMPORT_TYPE") + .value("STATIC", IMPORT_TYPE::STATIC) + .value("DELAYED", IMPORT_TYPE::DELAYED); + + init_ref_iterator(obj, "it_relocations"); + + using reloc_entry_t = DynamicFixupARM64Kernel::reloc_entry_t; + nb::class_(obj, "reloc_entry_t", + "Mirror ``IMAGE_IMPORT_CONTROL_TRANSFER_ARM64_RELOCATION``"_doc + ) + .def_rw("rva", &reloc_entry_t::rva, + "RVA to the call instruction"_doc) + + .def_rw("indirect_call", &reloc_entry_t::indirect_call, + "True if target instruction is a ``blr``, false if it's a ``br``."_doc) + + .def_rw("register_index", &reloc_entry_t::register_index, + R"doc( + Register index used for the indirect call/jump. + For instance, if the instruction is ``br x3``, this index is set to ``3`` + )doc"_doc) + + .def_rw("import_type", &reloc_entry_t::import_type, + "See: :class:`~.IMPORT_TYPE`"_doc) + + .def_rw("iat_index", &reloc_entry_t::iat_index, + R"doc( + IAT index of the corresponding import. ``0x7FFF`` is a special value + indicating no index. + )doc"_doc) + LIEF_DEFAULT_STR(reloc_entry_t); + + obj + .def_prop_ro("relocations", + nb::overload_cast<>(&DynamicFixupARM64Kernel::relocations), + "Iterator over the relocations"_doc, + nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64X.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64X.cpp new file mode 100644 index 0000000..59e55d7 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupARM64X.cpp @@ -0,0 +1,73 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyIterator.hpp" + +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupARM64X.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ obj(m, "DynamicFixupARM64X", + R"doc( + This class represents ``IMAGE_DYNAMIC_RELOCATION_ARM64X`` + )doc"_doc + ); + using FIXUP_TYPE = DynamicFixupARM64X::FIXUP_TYPE; + enum_(obj, "FIXUP_TYPE") + .value("ZEROFILL", FIXUP_TYPE::ZEROFILL) + .value("VALUE", FIXUP_TYPE::VALUE) + .value("DELTA", FIXUP_TYPE::DELTA); + + using reloc_entry_t = DynamicFixupARM64X::reloc_entry_t; + nb::class_(obj, "reloc_entry_t") + .def_rw("rva", &reloc_entry_t::rva, + "RVA where the fixup takes place"_doc) + .def_rw("type", &reloc_entry_t::type, + "Fixup's kind"_doc) + .def_rw("size", &reloc_entry_t::size, + "Size of the value to patch"_doc) + .def_rw("raw_bytes", &reloc_entry_t::bytes, + R"doc( + If the type is class:`~.FIXUP_TYPE.VALUE`, the bytes associated with the + fixup. + )doc"_doc) + .def_rw("value", &reloc_entry_t::value, + R"doc( + If the type is class:`~.FIXUP_TYPE.DELTA`, the (signed) value + )doc"_doc) + LIEF_DEFAULT_STR(reloc_entry_t); + + init_ref_iterator(obj, "it_relocations"); + + obj + .def_prop_ro("relocations", nb::overload_cast<>(&DynamicFixupARM64X::relocations), + "Iterator over the different fixup entries"_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupControlTransfer.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupControlTransfer.cpp new file mode 100644 index 0000000..798f0a0 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupControlTransfer.cpp @@ -0,0 +1,66 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyIterator.hpp" +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupControlTransfer.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ obj(m, "DynamicFixupControlTransfer", + R"doc( + This class wraps fixups associated with the (special) symbol value: + ``IMAGE_DYNAMIC_RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER (3)``. + )doc"_doc + ); + + obj.def_ro_static("NO_IAT_INDEX",&DynamicFixupControlTransfer::NO_IAT_INDEX); + + init_ref_iterator(obj, "it_relocations"); + + using reloc_entry_t = DynamicFixupControlTransfer::reloc_entry_t; + nb::class_(obj, "reloc_entry_t", + "Mirror `IMAGE_IMPORT_CONTROL_TRANSFER_DYNAMIC_RELOCATION`"_doc + ) + .def_rw("rva", &reloc_entry_t::rva, + "RVA to the instruction"_doc) + + .def_rw("is_call", &reloc_entry_t::is_call, + "True if target instruction is a ``call``, false otherwise"_doc) + + .def_rw("iat_index", &reloc_entry_t::iat_index, + R"doc( + IAT index of the corresponding import. ``0x7FFF`` is a special value + indicating no index. + )doc"_doc) + LIEF_DEFAULT_STR(reloc_entry_t); + + obj + .def_prop_ro("relocations", + nb::overload_cast<>(&DynamicFixupControlTransfer::relocations), + "Iterator over the relocations"_doc, + nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupGeneric.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupGeneric.cpp new file mode 100644 index 0000000..5d83c87 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupGeneric.cpp @@ -0,0 +1,48 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyIterator.hpp" + +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupGeneric.hpp" +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/PE/RelocationEntry.hpp" + +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ obj(m, "DynamicFixupGeneric", + R"doc( + This class represents a generic entry where the fixups are regular + relocations (:class:`lief.PE.Relocation`) + )doc"_doc + ); + init_ref_iterator(obj, "it_relocations"); + + obj + .def_prop_ro("relocations", nb::overload_cast<>(&DynamicFixupGeneric::relocations), + "Iterator over the relocations"_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>() + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupUnknown.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupUnknown.cpp new file mode 100644 index 0000000..c1e8c66 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicFixupUnknown.cpp @@ -0,0 +1,37 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupUnknown.hpp" + +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "DynamicFixupUnknown", + R"doc( + This class represents a special dynamic relocation where the format of the + fixups is not supported by LIEF. + )doc"_doc + ); + obj + .def_prop_ro("payload", + nb::overload_cast<>(&DynamicFixupUnknown::payload), + "Raw fixups"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationBase.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationBase.cpp new file mode 100644 index 0000000..fce003c --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationBase.cpp @@ -0,0 +1,101 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationBase.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixup.hpp" + +#include +#include + +namespace LIEF::PE { +class DynamicRelocationV1; +class DynamicRelocationV2; +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "DynamicRelocation", + R"doc( + This is the base class for any ``IMAGE_DYNAMIC_RELOCATION32``, + ``IMAGE_DYNAMIC_RELOCATION32_V2``, ``IMAGE_DYNAMIC_RELOCATION64``, + ``IMAGE_DYNAMIC_RELOCATION64_V2`` dynamic relocations. + )doc"_doc + ); + using IMAGE_DYNAMIC_RELOCATION = DynamicRelocation::IMAGE_DYNAMIC_RELOCATION; + enum_(obj, "IMAGE_DYNAMIC_RELOCATION", + "Special symbol values as defined in ``link.exe - GetDVRTSpecialSymbolName``"_doc + ) + .value("RELOCATION_GUARD_RF_PROLOGUE", IMAGE_DYNAMIC_RELOCATION::RELOCATION_GUARD_RF_PROLOGUE, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_GUARD_RF_PROLOGUE``") + + .value("RELOCATION_GUARD_RF_EPILOGUE", IMAGE_DYNAMIC_RELOCATION::RELOCATION_GUARD_RF_EPILOGUE, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_GUARD_RF_EPILOGUE``") + + .value("RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER", IMAGE_DYNAMIC_RELOCATION::RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER``") + + .value("RELOCATION_GUARD_INDIR_CONTROL_TRANSFER", IMAGE_DYNAMIC_RELOCATION::RELOCATION_GUARD_INDIR_CONTROL_TRANSFER, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_GUARD_INDIR_CONTROL_TRANSFER``") + + .value("RELOCATION_GUARD_SWITCHTABLE_BRANCH", IMAGE_DYNAMIC_RELOCATION::RELOCATION_GUARD_SWITCHTABLE_BRANCH, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_GUARD_SWITCHTABLE_BRANCH``") + + .value("RELOCATION_ARM64X", IMAGE_DYNAMIC_RELOCATION::RELOCATION_ARM64X, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_ARM64X``") + + .value("RELOCATION_FUNCTION_OVERRIDE", IMAGE_DYNAMIC_RELOCATION::RELOCATION_FUNCTION_OVERRIDE, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE``") + + .value("RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER", IMAGE_DYNAMIC_RELOCATION::RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER, + "Mirror ``IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER``") + ; + + obj + .def_prop_ro("version", &DynamicRelocation::version, + "Version of the structure"_doc + ) + + .def_prop_rw("symbol", + nb::overload_cast<>(&DynamicRelocation::symbol, nb::const_), + nb::overload_cast(&DynamicRelocation::symbol), + R"doc( + Symbol address. Some values have a special meaning + (c.f. :class:`~.IMAGE_DYNAMIC_RELOCATION`) and define how fixups are encoded. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("fixups", + nb::overload_cast<>(&DynamicRelocation::fixups, nb::const_), + R"doc( + Return fixups information, where the interpretation may depend on the + symbol's value + )doc"_doc, nb::rv_policy::reference_internal + ) + + LIEF_DEFAULT_STR(DynamicRelocation) + LIEF_CLONABLE(DynamicRelocation); + + create(m); + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV1.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV1.cpp new file mode 100644 index 0000000..fa52b76 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV1.cpp @@ -0,0 +1,31 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationV1.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "DynamicRelocationV1", + R"doc( + This class represents a dynamic relocation (``IMAGE_DYNAMIC_RELOCATION32`` or + ``IMAGE_DYNAMIC_RELOCATION64``). + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV2.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV2.cpp new file mode 100644 index 0000000..600d400 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyDynamicRelocationV2.cpp @@ -0,0 +1,31 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationV2.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "DynamicRelocationV2", + R"doc( + This class represents a dynamic relocation (``IMAGE_DYNAMIC_RELOCATION64_V2`` or + ``IMAGE_DYNAMIC_RELOCATION32_V2``) + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverride.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverride.cpp new file mode 100644 index 0000000..6953eef --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverride.cpp @@ -0,0 +1,83 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyIterator.hpp" + +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/FunctionOverride.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/FunctionOverrideInfo.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + create(m); + + nb::class_ obj(m, "FunctionOverride", + "This class represents ``IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE``"_doc + ); + + using image_bdd_dynamic_relocation_t = FunctionOverride::image_bdd_dynamic_relocation_t; + nb::class_(obj, "image_bdd_dynamic_relocation_t", + "Mirror ``IMAGE_BDD_DYNAMIC_RELOCATION``"_doc + ) + .def_rw("left", &image_bdd_dynamic_relocation_t::left) + .def_rw("right", &image_bdd_dynamic_relocation_t::right) + .def_rw("value", &image_bdd_dynamic_relocation_t::value); + + using image_bdd_info_t = FunctionOverride::image_bdd_info_t; + nb::class_(obj, "image_bdd_info_t", + "Mirror ``IMAGE_BDD_INFO``" + ) + .def_rw("version", &image_bdd_info_t::version) + .def_rw("original_size", &image_bdd_info_t::original_size) + .def_rw("original_offset", &image_bdd_info_t::original_offset) + .def_rw("relocations", &image_bdd_info_t::relocations) + .def_rw("payload", &image_bdd_info_t::payload); + + init_ref_iterator(obj, "it_func_overriding_info"); + init_ref_iterator(obj, "it_bdd_info"); + + obj + .def_prop_ro("func_overriding_info", + nb::overload_cast<>(&FunctionOverride::func_overriding_info), + "Iterator over the overriding info"_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>() + ) + .def_prop_ro("bdd_info", nb::overload_cast<>(&FunctionOverride::bdd_info), + "Iterator over the BDD info"_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>() + ) + + .def("find_bdd_info", + nb::overload_cast(&FunctionOverride::find_bdd_info), + "Find the ``IMAGE_BDD_INFO`` at the given offset"_doc, + nb::rv_policy::reference_internal + ) + + .def("find_bdd_info", + nb::overload_cast(&FunctionOverride::find_bdd_info), + "Find the ``IMAGE_BDD_INFO`` associated with the given function override info"_doc, + nb::rv_policy::reference_internal + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverrideInfo.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverrideInfo.cpp new file mode 100644 index 0000000..462cab7 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/DynamicRelocation/pyFunctionOverrideInfo.cpp @@ -0,0 +1,68 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyIterator.hpp" + +#include "PE/pyPE.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/FunctionOverrideInfo.hpp" +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/PE/RelocationEntry.hpp" + +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ obj(m, "FunctionOverrideInfo"); + + init_ref_iterator(obj, "it_relocations"); + + obj + .def_prop_rw("original_rva", + nb::overload_cast<>(&FunctionOverrideInfo::original_rva, nb::const_), + nb::overload_cast(&FunctionOverrideInfo::original_rva), + "RVA of original function"_doc, nb::rv_policy::reference_internal) + + .def_prop_rw("bdd_offset", + nb::overload_cast<>(&FunctionOverrideInfo::bdd_offset, nb::const_), + nb::overload_cast(&FunctionOverrideInfo::bdd_offset), + "Offset into the BDD region"_doc, nb::rv_policy::reference_internal) + + .def_prop_ro("rva_size", + nb::overload_cast<>(&FunctionOverrideInfo::rva_size, nb::const_), + "Size in bytes taken by RVAs"_doc, nb::rv_policy::reference_internal) + + .def_prop_ro("base_reloc_size", + nb::overload_cast<>(&FunctionOverrideInfo::base_reloc_size, nb::const_), + "Size in bytes taken by BaseRelocs"_doc, nb::rv_policy::reference_internal) + + .def_prop_ro("relocations", + nb::overload_cast<>(&FunctionOverrideInfo::relocations), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>() + ) + + .def_prop_ro("functions_rva", + nb::overload_cast<>(&FunctionOverrideInfo::functions_rva, nb::const_) + ) + + LIEF_DEFAULT_STR(FunctionOverrideInfo); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveConfiguration.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveConfiguration.cpp new file mode 100644 index 0000000..7c0a27a --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveConfiguration.cpp @@ -0,0 +1,177 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/EnclaveConfiguration.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include "pyIterator.hpp" + +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + using id_array_t = EnclaveConfiguration::id_array_t; + + nb::class_ conf(m, "EnclaveConfiguration", + "This class represents the enclave configuration"_doc); + + init_ref_iterator(conf, "it_imports"); + + conf + .def_prop_rw("size", + nb::overload_cast<>(&EnclaveConfiguration::size, nb::const_), + nb::overload_cast(&EnclaveConfiguration::size), + R"doc( + The size of the ``IMAGE_ENCLAVE_CONFIG64/IMAGE_ENCLAVE_CONFIG32`` structure, + in bytes. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("min_required_config_size", + nb::overload_cast<>(&EnclaveConfiguration::min_required_config_size, nb::const_), + nb::overload_cast(&EnclaveConfiguration::min_required_config_size), + R"doc( + The minimum size of the ``IMAGE_ENCLAVE_CONFIG(32,64)`` structure that the + image loader must be able to process in order for the enclave to be usable. + + This member allows an enclave to inform an earlier version of the image + loader that the image loader can safely load the enclave and ignore + optional members added to ``IMAGE_ENCLAVE_CONFIG(32,64)`` for later versions + of the enclave. If the size of ``IMAGE_ENCLAVE_CONFIG(32,64)`` that the image + loader can process is less than ``MinimumRequiredConfigSize``, the enclave + cannot be run securely. + + If ``MinimumRequiredConfigSize`` is zero, the minimum size of the + ``IMAGE_ENCLAVE_CONFIG(32,64)`` structure that the image loader must be able + to process in order for the enclave to be usable is assumed to be the size + of the structure through and including the ``MinimumRequiredConfigSize`` member. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("policy_flags", + nb::overload_cast<>(&EnclaveConfiguration::policy_flags, nb::const_), + nb::overload_cast(&EnclaveConfiguration::policy_flags), + "A flag that indicates whether the enclave permits debugging."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("is_debuggable", + nb::overload_cast<>(&EnclaveConfiguration::is_debuggable, nb::const_), + "Whether this enclave can be debugged"_doc + ) + + .def_prop_rw("import_list_rva", + nb::overload_cast<>(&EnclaveConfiguration::import_list_rva, nb::const_), + nb::overload_cast(&EnclaveConfiguration::import_list_rva), + R"doc( + The RVA of the array of images that the enclave image may import, with + identity information for each image. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("import_entry_size", + nb::overload_cast<>(&EnclaveConfiguration::import_entry_size, nb::const_), + nb::overload_cast(&EnclaveConfiguration::import_entry_size), + R"doc( + The size of each image in the array of images that the :attr:`~.import_list_rva` + member points to. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("nb_imports", + nb::overload_cast<>(&EnclaveConfiguration::nb_imports, nb::const_), + R"doc( + The number of images in the array of images that the :attr:`~.import_list_rva` + member points to. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("imports", + nb::overload_cast<>(&EnclaveConfiguration::imports), + "Iterator over the enclave's imports"_doc, + nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal + ) + + .def_prop_rw("family_id", + nb::overload_cast<>(&EnclaveConfiguration::family_id, nb::const_), + nb::overload_cast(&EnclaveConfiguration::family_id), + R"doc( + The family identifier that the author of the enclave assigned to the + enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("image_id", + nb::overload_cast<>(&EnclaveConfiguration::image_id, nb::const_), + nb::overload_cast(&EnclaveConfiguration::image_id), + R"doc( + The image identifier that the author of the enclave assigned to the enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("image_version", + nb::overload_cast<>(&EnclaveConfiguration::image_version, nb::const_), + nb::overload_cast(&EnclaveConfiguration::image_version), + R"doc( + The version number that the author of the enclave assigned to the enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("security_version", + nb::overload_cast<>(&EnclaveConfiguration::security_version, nb::const_), + nb::overload_cast(&EnclaveConfiguration::security_version), + R"doc( + The security version number that the author of the enclave assigned to the + enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("enclave_size", + nb::overload_cast<>(&EnclaveConfiguration::enclave_size, nb::const_), + nb::overload_cast(&EnclaveConfiguration::enclave_size), + R"doc( + The expected virtual size of the private address range for the enclave, + in bytes. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("nb_threads", + nb::overload_cast<>(&EnclaveConfiguration::nb_threads, nb::const_), + nb::overload_cast(&EnclaveConfiguration::nb_threads), + R"doc( + The maximum number of threads that can be created within the enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("enclave_flags", + nb::overload_cast<>(&EnclaveConfiguration::enclave_flags, nb::const_), + nb::overload_cast(&EnclaveConfiguration::enclave_flags), + R"doc( + A flag that indicates whether the image is suitable for use as the primary + image in the enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + LIEF_DEFAULT_STR(EnclaveConfiguration); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveImport.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveImport.cpp new file mode 100644 index 0000000..19f35c7 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyEnclaveImport.cpp @@ -0,0 +1,146 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/EnclaveImport.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using long_id_t = EnclaveImport::long_id_t; + using short_id_t = EnclaveImport::short_id_t; + + nb::class_ imp(m, "EnclaveImport", + "Defines an entry in the array of images that an enclave can import."_doc); + + using TYPE = EnclaveImport::TYPE; + nb::enum_(imp, "TYPE") + .value("NONE", TYPE::NONE, + R"doc( + None of the identifiers of the image need to match the value in the + import record. + )doc"_doc + ) + + .value("UNIQUE_ID", TYPE::UNIQUE_ID, + R"doc( + The value of the enclave unique identifier of the image must match the + value in the import record. Otherwise, loading of the image fails. + )doc"_doc + ) + + .value("AUTHOR_ID", TYPE::AUTHOR_ID, + R"doc( + The value of the enclave author identifier of the image must match the + value in the import record. Otherwise, loading of the image fails. If + this flag is set and the import record indicates an author identifier + of all zeros, the imported image must be part of the Windows installation. + )doc"_doc + ) + + .value("FAMILY_ID", TYPE::FAMILY_ID, + R"doc( + The value of the enclave family identifier of the image must match the + value in the import record. Otherwise, loading of the image fails. + )doc"_doc + ) + + .value("IMAGE_ID", TYPE::IMAGE_ID, + R"doc( + The value of the enclave image identifier of the image must match the + value in the import record. Otherwise, loading of the image fail + )doc"_doc + ) + ; + + imp + .def_prop_rw("type", + nb::overload_cast<>(&EnclaveImport::type, nb::const_), + nb::overload_cast(&EnclaveImport::type), + R"doc( + The type of identifier of the image that must match the value in the import + record. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("min_security_version", + nb::overload_cast<>(&EnclaveImport::min_security_version, nb::const_), + nb::overload_cast(&EnclaveImport::min_security_version), + R"doc( + The minimum enclave security version that each image must have for the + image to be imported successfully. The image is rejected unless its enclave + security version is equal to or greater than the minimum value in the + import record. Set the value in the import record to zero to turn off the + security version check. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("id", + nb::overload_cast<>(&EnclaveImport::id, nb::const_), + nb::overload_cast(&EnclaveImport::id), + R"doc( + The unique identifier of the primary module for the enclave, if the + :attr:`~.type` is :class:`~.TYPE.UNIQUE_ID`. Otherwise, the author + identifier of the primary module for the enclave. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("family_id", + nb::overload_cast<>(&EnclaveImport::family_id, nb::const_), + nb::overload_cast(&EnclaveImport::family_id), + "The family identifier of the primary module for the enclave."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("image_id", + nb::overload_cast<>(&EnclaveImport::image_id, nb::const_), + nb::overload_cast(&EnclaveImport::image_id), + "The image identifier of the primary module for the enclave."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("import_name_rva", + nb::overload_cast<>(&EnclaveImport::import_name_rva, nb::const_), + nb::overload_cast(&EnclaveImport::import_name_rva), + R"doc( + The relative virtual address of a NULL-terminated string that contains the + same value found in the import directory for the image. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("import_name", + nb::overload_cast<>(&EnclaveImport::import_name, nb::const_), + nb::overload_cast(&EnclaveImport::import_name), + "Resolved import name"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("reserved", + nb::overload_cast<>(&EnclaveImport::reserved, nb::const_), + nb::overload_cast(&EnclaveImport::reserved), + "Reserved. Should be 0"_doc, nb::rv_policy::reference_internal + ) + + LIEF_DEFAULT_STR(EnclaveImport); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp new file mode 100644 index 0000000..90306a8 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyLoadConfiguration.cpp @@ -0,0 +1,517 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/LoadConfigurations.hpp" +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/Metadata.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationBase.hpp" +#include "enums_wrapper.hpp" + +#include +#include +#include +#include +#include +#include + +#include "pyIterator.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + create(m); + create(m); + create(m); + create(m); + create(m); + + nb::class_ config(m, "LoadConfiguration", + R"delim( + This class represents the load configuration data associated with the + ``IMAGE_LOAD_CONFIG_DIRECTORY``. + + This structure is frequently updated by Microsoft to add new metadata. + + Reference: https://github.com/MicrosoftDocs/sdk-api/blob/cbeab4d371e8bc7e352c4d3a4c5819caa08c6a1c/sdk-api-src/content/winnt/ns-winnt-image_load_config_directory64.md#L2 + )delim"_doc); + + using guard_cf_function_t = LoadConfiguration::guard_function_t; + nb::class_(config, "guard_function_t") + .def_rw("rva", &guard_cf_function_t::rva) + .def_rw("extra", &guard_cf_function_t::extra); + + init_ref_iterator(config, "it_guard_functions"); + init_ref_iterator(config, "it_dynamic_relocations_t"); + + enum_(config, "IMAGE_GUARD", nb::is_flag()) + #define ENTRY(X) .value(to_string(LoadConfiguration::IMAGE_GUARD::X), LoadConfiguration::IMAGE_GUARD::X) + ENTRY(NONE) + ENTRY(CF_INSTRUMENTED) + ENTRY(CFW_INSTRUMENTED) + ENTRY(CF_FUNCTION_TABLE_PRESENT) + ENTRY(SECURITY_COOKIE_UNUSED) + ENTRY(PROTECT_DELAYLOAD_IAT) + ENTRY(DELAYLOAD_IAT_IN_ITS_OWN_SECTION) + ENTRY(CF_EXPORT_SUPPRESSION_INFO_PRESENT) + ENTRY(CF_ENABLE_EXPORT_SUPPRESSION) + ENTRY(CF_LONGJUMP_TABLE_PRESENT) + ENTRY(RF_INSTRUMENTED) + ENTRY(RF_ENABLE) + ENTRY(RF_STRICT) + ENTRY(RETPOLINE_PRESENT) + ENTRY(EH_CONTINUATION_TABLE_PRESENT) + ENTRY(XFG_ENABLED) + ENTRY(CASTGUARD_PRESENT) + ENTRY(MEMCPY_PRESENT) + #undef ENTRY + ; + + config + .def_prop_rw("characteristics", + nb::overload_cast<>(&LoadConfiguration::characteristics, nb::const_), + nb::overload_cast(&LoadConfiguration::characteristics), + R"doc( + Characteristics of the structure which is defined by its size + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("size", + nb::overload_cast<>(&LoadConfiguration::size, nb::const_), + nb::overload_cast(&LoadConfiguration::size), + "Size of the current structure"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("timedatestamp", + nb::overload_cast<>(&LoadConfiguration::timedatestamp, nb::const_), + nb::overload_cast(&LoadConfiguration::timedatestamp), + "The date and time stamp value"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("major_version", + nb::overload_cast<>(&LoadConfiguration::major_version, nb::const_), + nb::overload_cast(&LoadConfiguration::major_version), + "Major version"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("minor_version", + nb::overload_cast<>(&LoadConfiguration::minor_version, nb::const_), + nb::overload_cast(&LoadConfiguration::minor_version), + "Minor version"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("global_flags_clear", + nb::overload_cast<>(&LoadConfiguration::global_flags_clear, nb::const_), + nb::overload_cast(&LoadConfiguration::global_flags_clear), + R"doc( + The global flags that control system behavior. For more information, see + ``Gflags.exe``. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("global_flags_set", + nb::overload_cast<>(&LoadConfiguration::global_flags_set, nb::const_), + nb::overload_cast(&LoadConfiguration::global_flags_set), + R"doc( + The global flags that control system behavior. For more information, see + ``Gflags.exe``. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("critical_section_default_timeout", + nb::overload_cast<>(&LoadConfiguration::critical_section_default_timeout, nb::const_), + nb::overload_cast(&LoadConfiguration::critical_section_default_timeout), + "The critical section default time-out value."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("decommit_free_block_threshold", + nb::overload_cast<>(&LoadConfiguration::decommit_free_block_threshold, nb::const_), + nb::overload_cast(&LoadConfiguration::decommit_free_block_threshold), + R"doc( + The size of the minimum block that must be freed before it is freed + (de-committed), in bytes. This value is advisory. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("decommit_total_free_threshold", + nb::overload_cast<>(&LoadConfiguration::decommit_total_free_threshold, nb::const_), + nb::overload_cast(&LoadConfiguration::decommit_total_free_threshold), + R"doc( + The size of the minimum total memory that must be freed in the process + heap before it is freed (de-committed), in bytes. This value is advisory. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("lock_prefix_table", + nb::overload_cast<>(&LoadConfiguration::lock_prefix_table, nb::const_), + nb::overload_cast(&LoadConfiguration::lock_prefix_table), + R"doc( + The VA of a list of addresses where the ``LOCK`` prefix is used. These will + be replaced by ``NOP`` on single-processor systems. This member is available + only for ``x86``. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("maximum_allocation_size", + nb::overload_cast<>(&LoadConfiguration::maximum_allocation_size, nb::const_), + nb::overload_cast(&LoadConfiguration::maximum_allocation_size), + R"doc( + The maximum allocation size, in bytes. This member is obsolete and is + used only for debugging purposes. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("virtual_memory_threshold", + nb::overload_cast<>(&LoadConfiguration::virtual_memory_threshold, nb::const_), + nb::overload_cast(&LoadConfiguration::virtual_memory_threshold), + R"doc( + The maximum block size that can be allocated from heap segments, in bytes. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("process_affinity_mask", + nb::overload_cast<>(&LoadConfiguration::process_affinity_mask, nb::const_), + nb::overload_cast(&LoadConfiguration::process_affinity_mask), + R"doc( + The process affinity mask. For more information, see + ``GetProcessAffinityMask``. This member is available only for ``.exe`` files. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("process_heap_flags", + nb::overload_cast<>(&LoadConfiguration::process_heap_flags, nb::const_), + nb::overload_cast(&LoadConfiguration::process_heap_flags), + "The process heap flags. For more information, see ``HeapCreate``."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("csd_version", + nb::overload_cast<>(&LoadConfiguration::csd_version, nb::const_), + nb::overload_cast(&LoadConfiguration::csd_version), + "The service pack version."_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("dependent_load_flags", + nb::overload_cast<>(&LoadConfiguration::dependent_load_flags, nb::const_), + nb::overload_cast(&LoadConfiguration::dependent_load_flags), + R"doc( + Alias for :attr:`~.reserved1`. + + The default load flags used when the operating system resolves the + statically linked imports of a module. For more information, see + ``LoadLibraryEx``. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("reserved1", + nb::overload_cast<>(&LoadConfiguration::reserved1, nb::const_), + nb::overload_cast(&LoadConfiguration::dependent_load_flags), + "See: :attr:`~.dependent_load_flags`"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("editlist", + nb::overload_cast<>(&LoadConfiguration::editlist, nb::const_), + nb::overload_cast(&LoadConfiguration::editlist), + "Reserved for use by the system."_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("security_cookie", + nb::overload_cast<>(&LoadConfiguration::security_cookie, nb::const_), + nb::overload_cast(&LoadConfiguration::security_cookie), + R"doc( + A pointer to a cookie that is used by Visual C++ or GS implementation. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("se_handler_table", + nb::overload_cast<>(&LoadConfiguration::se_handler_table, nb::const_), + nb::overload_cast(&LoadConfiguration::se_handler_table), + R"doc( + The VA of the sorted table of RVAs of each valid, unique handler in the + image. This member is available only for x86. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("seh_functions", + nb::overload_cast<>(&LoadConfiguration::seh_functions, nb::const_), + "Return the list of the function RVA in the SEH table (if any)"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("se_handler_count", + nb::overload_cast<>(&LoadConfiguration::se_handler_count, nb::const_), + nb::overload_cast(&LoadConfiguration::se_handler_count), + R"doc( + The count of unique handlers in the table. This member is available only + for x86. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_cf_check_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_cf_check_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_cf_check_function_pointer), + R"doc( + The VA where Control Flow Guard check-function pointer is stored. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_cf_dispatch_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_cf_dispatch_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_cf_dispatch_function_pointer), + R"doc( + The VA where Control Flow Guard dispatch-function pointer is stored. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_cf_function_table", + nb::overload_cast<>(&LoadConfiguration::guard_cf_function_table, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_cf_function_table), + R"doc( + The VA of the sorted table of RVAs of each Control Flow Guard function in + the image. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_cf_function_count", + nb::overload_cast<>(&LoadConfiguration::guard_cf_function_count, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_cf_function_count), + R"doc( + The count of unique RVAs in the :attr:`~.guard_cf_function_table` table. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("guard_cf_functions", + nb::overload_cast<>(&LoadConfiguration::guard_cf_functions), + R"doc( + Iterator over the Control Flow Guard functions referenced by + :attr:`~.guard_cf_function_table` + )doc"_doc, nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_flags", + nb::overload_cast<>(&LoadConfiguration::guard_flags, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_flags), + "Control Flow Guard related flags."_doc, nb::rv_policy::reference_internal + ) + + .def("has", nb::overload_cast(&LoadConfiguration::has, nb::const_), + "Check if the given flag is present"_doc) + + .def_prop_ro("guard_cf_flags_list", + nb::overload_cast<>(&LoadConfiguration::guard_cf_flags_list, nb::const_), + "List of flags"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("code_integrity", + nb::overload_cast<>(&LoadConfiguration::code_integrity, nb::const_), + nb::overload_cast(&LoadConfiguration::code_integrity), + "Code integrity information."_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_address_taken_iat_entry_table", + nb::overload_cast<>(&LoadConfiguration::guard_address_taken_iat_entry_table, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_address_taken_iat_entry_table), + R"doc( + The VA where Control Flow Guard address taken IAT table is stored. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_address_taken_iat_entry_count", + nb::overload_cast<>(&LoadConfiguration::guard_address_taken_iat_entry_count, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_address_taken_iat_entry_count), + R"doc( + The count of unique RVAs in the table pointed by + :attr:`~.guard_address_taken_iat_entry_table`. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("guard_address_taken_iat_entries", + nb::overload_cast<>(&LoadConfiguration::guard_address_taken_iat_entries), + R"doc( + List of RVA pointed by :attr:`~.guard_address_taken_iat_entry_table` + )doc"_doc + ) + + .def_prop_rw("guard_long_jump_target_table", + nb::overload_cast<>(&LoadConfiguration::guard_long_jump_target_table, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_long_jump_target_table), + R"doc( + The VA where Control Flow Guard long jump target table is stored. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_long_jump_target_count", + nb::overload_cast<>(&LoadConfiguration::guard_long_jump_target_count, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_long_jump_target_count), + R"doc( + The count of unique RVAs in the table pointed by + :attr:`~.guard_long_jump_target_table`. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("guard_long_jump_targets", + nb::overload_cast<>(&LoadConfiguration::guard_long_jump_targets), + R"doc( + List of RVA pointed by :attr:`~.guard_long_jump_target_table` + )doc"_doc + ) + + .def_prop_rw("dynamic_value_reloc_table", + nb::overload_cast<>(&LoadConfiguration::dynamic_value_reloc_table, nb::const_), + nb::overload_cast(&LoadConfiguration::dynamic_value_reloc_table), + R"doc( + VA pointing to a ``IMAGE_DYNAMIC_RELOCATION_TABLE`` + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("hybrid_metadata_pointer", + nb::overload_cast<>(&LoadConfiguration::hybrid_metadata_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::hybrid_metadata_pointer), + R"doc( + Alias for :attr:`~.chpe_metadata_pointer`. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("chpe_metadata_pointer", + nb::overload_cast<>(&LoadConfiguration::chpe_metadata_pointer, nb::const_), + R"doc( + VA to the extra Compiled Hybrid Portable Executable (CHPE) metadata. + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_ro("chpe_metadata", + nb::overload_cast<>(&LoadConfiguration::chpe_metadata), + R"doc( + Compiled Hybrid Portable Executable (CHPE) metadata (if any) + )doc"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_rf_failure_routine", + nb::overload_cast<>(&LoadConfiguration::guard_rf_failure_routine, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_rf_failure_routine), + "VA of the failure routine"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_rf_failure_routine_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_rf_failure_routine_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_rf_failure_routine_function_pointer), + "VA of the failure routine ``fptr``."_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("dynamic_value_reloctable_offset", + nb::overload_cast<>(&LoadConfiguration::dynamic_value_reloctable_offset, nb::const_), + nb::overload_cast(&LoadConfiguration::dynamic_value_reloctable_offset), + "Offset of dynamic relocation table relative to the relocation table"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("dynamic_value_reloctable_section", + nb::overload_cast<>(&LoadConfiguration::dynamic_value_reloctable_section, nb::const_), + nb::overload_cast(&LoadConfiguration::dynamic_value_reloctable_section), + "The section index of the dynamic value relocation table"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("dynamic_relocations", + nb::overload_cast<>(&LoadConfiguration::dynamic_relocations), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + + .def_prop_rw("reserved2", + nb::overload_cast<>(&LoadConfiguration::reserved2, nb::const_), + nb::overload_cast(&LoadConfiguration::reserved2), + "Must be 0"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("guard_rf_verify_stackpointer_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_rf_verify_stackpointer_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_rf_verify_stackpointer_function_pointer), + "VA of the Function verifying the stack pointer"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("hotpatch_table_offset", + nb::overload_cast<>(&LoadConfiguration::hotpatch_table_offset, nb::const_), + nb::overload_cast(&LoadConfiguration::hotpatch_table_offset), + "Offset to the *hotpatch* table"_doc, nb::rv_policy::reference_internal + ) + + .def_prop_rw("reserved3", + nb::overload_cast<>(&LoadConfiguration::reserved3, nb::const_), + nb::overload_cast(&LoadConfiguration::reserved3)) + + .def_prop_rw("enclave_configuration_ptr", + nb::overload_cast<>(&LoadConfiguration::enclave_configuration_ptr, nb::const_), + nb::overload_cast(&LoadConfiguration::enclave_configuration_ptr)) + + .def_prop_ro("enclave_config", + nb::overload_cast<>(&LoadConfiguration::enclave_config), + nb::rv_policy::reference_internal + ) + + .def_prop_rw("volatile_metadata_pointer", + nb::overload_cast<>(&LoadConfiguration::volatile_metadata_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::volatile_metadata_pointer)) + + .def_prop_ro("volatile_metadata", + nb::overload_cast<>(&LoadConfiguration::volatile_metadata)) + + .def_prop_rw("guard_eh_continuation_table", + nb::overload_cast<>(&LoadConfiguration::guard_eh_continuation_table, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_eh_continuation_table)) + + .def_prop_rw("guard_eh_continuation_count", + nb::overload_cast<>(&LoadConfiguration::guard_eh_continuation_count, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_eh_continuation_count)) + + .def_prop_ro("guard_eh_continuation_functions", + nb::overload_cast<>(&LoadConfiguration::guard_eh_continuation_functions), + R"doc( + List of RVA pointed by :attr:`~.guard_eh_continuation_table` + )doc"_doc + ) + + .def_prop_rw("guard_xfg_check_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_xfg_check_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_xfg_check_function_pointer)) + + .def_prop_rw("guard_xfg_dispatch_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_xfg_dispatch_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_xfg_dispatch_function_pointer)) + + .def_prop_rw("guard_xfg_table_dispatch_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_xfg_table_dispatch_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_xfg_table_dispatch_function_pointer)) + + .def_prop_rw("cast_guard_os_determined_failure_mode", + nb::overload_cast<>(&LoadConfiguration::cast_guard_os_determined_failure_mode, nb::const_), + nb::overload_cast(&LoadConfiguration::cast_guard_os_determined_failure_mode)) + + .def_prop_rw("guard_memcpy_function_pointer", + nb::overload_cast<>(&LoadConfiguration::guard_memcpy_function_pointer, nb::const_), + nb::overload_cast(&LoadConfiguration::guard_memcpy_function_pointer)) + + .def_prop_rw("uma_function_pointers", + nb::overload_cast<>(&LoadConfiguration::uma_function_pointers, nb::const_), + nb::overload_cast(&LoadConfiguration::uma_function_pointers)) + + LIEF_COPYABLE(LoadConfiguration) + LIEF_DEFAULT_STR(LoadConfiguration); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyVolatileMetadata.cpp b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyVolatileMetadata.cpp new file mode 100644 index 0000000..c504df5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/LoadConfigurations/pyVolatileMetadata.cpp @@ -0,0 +1,114 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/LoadConfigurations/VolatileMetadata.hpp" +#include "PE/pyPE.hpp" + +#include +#include + +#include "pyIterator.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ meta(m, "VolatileMetadata", + R"doc( + This class represents volatile metadata which can be enabled at link time + with ``/volatileMetadata``. + + This metadata aims to improve performances when running x64 code on ARM64. + )doc"_doc + ); + + using range_t = VolatileMetadata::range_t; + + nb::class_(meta, "range_t") + .def_rw("start", &range_t::start) + .def_rw("size", &range_t::size) + .def_prop_ro("end", &range_t::end); + + init_ref_iterator(meta, "it_info_ranges_t"); + + meta + .def_prop_rw("size", + nb::overload_cast<>(&VolatileMetadata::size, nb::const_), + nb::overload_cast(&VolatileMetadata::size), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("min_version", + nb::overload_cast<>(&VolatileMetadata::min_version, nb::const_), + nb::overload_cast(&VolatileMetadata::min_version), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("max_version", + nb::overload_cast<>(&VolatileMetadata::max_version, nb::const_), + nb::overload_cast(&VolatileMetadata::max_version), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("access_table_rva", + nb::overload_cast<>(&VolatileMetadata::access_table_rva, nb::const_), + nb::overload_cast(&VolatileMetadata::access_table_rva), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("access_table", + nb::overload_cast<>(&VolatileMetadata::access_table, nb::const_), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("access_table_size", + nb::overload_cast<>(&VolatileMetadata::access_table_size, nb::const_), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("info_range_rva", + nb::overload_cast<>(&VolatileMetadata::info_range_rva, nb::const_), + nb::overload_cast(&VolatileMetadata::info_range_rva), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("info_ranges_size", + nb::overload_cast<>(&VolatileMetadata::info_ranges_size, nb::const_), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_ro("info_ranges", + nb::overload_cast<>(&VolatileMetadata::info_ranges), + R"doc()doc"_doc, + nb::rv_policy::reference_internal + ) + LIEF_DEFAULT_STR(VolatileMetadata); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/debug/CMakeLists.txt new file mode 100644 index 0000000..1f79bd9 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/CMakeLists.txt @@ -0,0 +1,12 @@ +target_sources(pyLIEF PRIVATE + pyCodeView.cpp + pyCodeViewPDB.cpp + pyDebug.cpp + pyExDllCharacteristics.cpp + pyFPO.cpp + pyPDBChecksum.cpp + pyPogo.cpp + pyPogoEntry.cpp + pyRepro.cpp + pyVCFeatures.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyCodeView.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyCodeView.cpp new file mode 100644 index 0000000..de64755 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyCodeView.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/debug/CodeView.hpp" +#include "enums_wrapper.hpp" + +#include +#include +#include +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ cv(m, "CodeView"); + + enum_(cv, "SIGNATURES") + .value(PY_ENUM(CodeView::SIGNATURES::UNKNOWN)) + .value(PY_ENUM(CodeView::SIGNATURES::PDB_70)) + .value(PY_ENUM(CodeView::SIGNATURES::PDB_20)) + .value(PY_ENUM(CodeView::SIGNATURES::CV_50)) + .value(PY_ENUM(CodeView::SIGNATURES::CV_41)); + cv + .def(nb::init<>()) + .def(nb::init()) + .def_prop_ro("cv_signature", + nb::overload_cast<>(&CodeView::signature, nb::const_), + "Type of the code view (" RST_CLASS_REF(lief.PE.CodeView.SIGNATURES) ")"_doc) + + LIEF_DEFAULT_STR(CodeView); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyCodeViewPDB.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyCodeViewPDB.cpp new file mode 100644 index 0000000..fd76cbe --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyCodeViewPDB.cpp @@ -0,0 +1,86 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/debug/CodeViewPDB.hpp" + +#include +#include +#include +#include + +#include "pySafeString.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "CodeViewPDB", + R"delim(CodeView PDB specialization)delim"_doc) + .def(nb::init<>(), "Default constructor"_doc) + .def(nb::init(), + "Filename-based constructor"_doc, + "filename"_a) + + .def_prop_ro("parent", + [] (nb::object& self) -> nb::object { + auto* ab = nb::cast(self); + const nb::handle base_type = nb::type(); + nb::object py_inst = nb::inst_reference(base_type, ab, self); + nb::inst_set_state(py_inst, /*ready=*/true, /*destruct=*/false); + return py_inst; + }, + R"delim( + Return a reference to the parent :class:`lief.PE.CodeView` + )delim"_doc, + nb::sig("def parent(self) -> lief.PE.CodeView"), + nb::rv_policy::reference_internal) + + .def_prop_ro("guid", &CodeViewPDB::guid, + R"doc( + The GUID signature to verify against the .pdb file signature. + + This attribute might be used to lookup remote PDB file on a symbol server + )doc"_doc + ) + + .def_prop_rw("signature", + nb::overload_cast<>(&CodeViewPDB::signature, nb::const_), + nb::overload_cast(&CodeViewPDB::signature), + R"doc( + The 32-bit signature to verify against the .pdb file signature. + )doc"_doc) + + .def_prop_rw("age", + nb::overload_cast<>(&CodeViewPDB::age, nb::const_), + nb::overload_cast(&CodeViewPDB::age), + R"doc( + Age value to verify. The age does not necessarily correspond to any known + time value, it is used to determine if a .pdb file is out of sync with + a corresponding .exe file. + )doc"_doc) + + .def_prop_rw("filename", + [] (const CodeViewPDB& self) { + return LIEF::py::safe_string(self.filename()); + }, + nb::overload_cast(&CodeViewPDB::filename), + "The path to the ``.pdb`` file"_doc) + + LIEF_DEFAULT_STR(CodeViewPDB); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyDebug.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyDebug.cpp new file mode 100644 index 0000000..aad0be9 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyDebug.cpp @@ -0,0 +1,119 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/Debug.hpp" +#include "LIEF/PE/Section.hpp" + +#include "enums_wrapper.hpp" + +#include +#include +#include +#include + +#include "nanobind/extra/stl/lief_span.h" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ debug(m, "Debug", + R"delim( + This class represents a generic entry in the debug data directory. + For known types, this class is extended to provide a dedicated API + (see: :class:`~.CodeView`) + )delim"_doc); + + enum_(debug, "TYPES", "The entry types") + .value(PY_ENUM(Debug::TYPES::UNKNOWN)) + .value(PY_ENUM(Debug::TYPES::COFF), "COFF debug information"_doc) + .value(PY_ENUM(Debug::TYPES::CODEVIEW), "CodeView debug information (pdb & cie)"_doc) + .value(PY_ENUM(Debug::TYPES::FPO), "Frame pointer omission information"_doc) + .value(PY_ENUM(Debug::TYPES::MISC), "CodeView Debug Information"_doc) + .value(PY_ENUM(Debug::TYPES::EXCEPTION), "A copy of .pdata section."_doc) + .value(PY_ENUM(Debug::TYPES::FIXUP), "Reserved"_doc) + .value(PY_ENUM(Debug::TYPES::OMAP_TO_SRC), "The mapping from an RVA in image to an RVA in source image."_doc) + .value(PY_ENUM(Debug::TYPES::OMAP_FROM_SRC), "The mapping from an RVA in source image to an RVA in image."_doc) + .value(PY_ENUM(Debug::TYPES::BORLAND), "Reserved for Borland."_doc) + .value(PY_ENUM(Debug::TYPES::RESERVED10), "Reserved"_doc) + .value(PY_ENUM(Debug::TYPES::CLSID), "Reserved"_doc) + .value(PY_ENUM(Debug::TYPES::VC_FEATURE)) + .value(PY_ENUM(Debug::TYPES::POGO), "Profile Guided Optimization metadata"_doc) + .value(PY_ENUM(Debug::TYPES::ILTCG)) + .value(PY_ENUM(Debug::TYPES::MPX)) + .value(PY_ENUM(Debug::TYPES::REPRO), "PE determinism or reproducibility"_doc) + .value(PY_ENUM(Debug::TYPES::PDBCHECKSUM), "Checksum of the PDB file content"_doc) + .value(PY_ENUM(Debug::TYPES::EX_DLLCHARACTERISTICS)); + + debug + .def(nb::init<>()) + + .def_prop_rw("characteristics", + nb::overload_cast<>(&Debug::characteristics, nb::const_), + nb::overload_cast(&Debug::characteristics), + "Reserved should be 0"_doc) + + .def_prop_rw("timestamp", + nb::overload_cast<>(&Debug::timestamp, nb::const_), + nb::overload_cast(&Debug::timestamp), + "The time and date when the debug data was created."_doc) + + .def_prop_rw("major_version", + nb::overload_cast<>(&Debug::major_version, nb::const_), + nb::overload_cast(&Debug::major_version), + "The major version number of the debug data format."_doc) + + .def_prop_rw("minor_version", + nb::overload_cast<>(&Debug::minor_version, nb::const_), + nb::overload_cast(&Debug::minor_version), + "The minor version number of the debug data format."_doc) + + .def_prop_ro("type", + nb::overload_cast<>(&Debug::type, nb::const_), + "The format (" RST_CLASS_REF(lief.PE.Debug.TYPES) ") of the debugging information"_doc) + + .def_prop_rw("sizeof_data", + nb::overload_cast<>(&Debug::sizeof_data, nb::const_), + nb::overload_cast(&Debug::sizeof_data), + "Size of the debug data"_doc) + + .def_prop_rw("addressof_rawdata", + nb::overload_cast<>(&Debug::addressof_rawdata, nb::const_), + nb::overload_cast(&Debug::addressof_rawdata), + "Address of the debug data relative to the image base"_doc) + + .def_prop_rw("pointerto_rawdata", + nb::overload_cast<>(&Debug::pointerto_rawdata, nb::const_), + nb::overload_cast(&Debug::pointerto_rawdata), + "File offset of the debug data"_doc) + + .def_prop_ro("section", nb::overload_cast<>(&Debug::section), + "The section where debug data is located"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("payload", nb::overload_cast<>(&Debug::payload, nb::const_), + "Debug data associated with this entry"_doc, + nb::rv_policy::reference_internal) + + LIEF_CLONABLE(Debug) + LIEF_DEFAULT_STR(Debug); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyExDllCharacteristics.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyExDllCharacteristics.cpp new file mode 100644 index 0000000..b5b31fd --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyExDllCharacteristics.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/debug/ExDllCharacteristics.hpp" + +#include +#include +#include +#include +#include +#include "nanobind/utils.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ dbg(m, "ExDllCharacteristics", + R"delim( + This class represents the ``IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS`` debug + entry + )delim"_doc); + + using CHARACTERISTICS = ExDllCharacteristics::CHARACTERISTICS; + enum_(dbg, "CHARACTERISTICS", nb::is_flag(), + "Extended DLL Characteristics"_doc + ) + .value("CET_COMPAT", CHARACTERISTICS::CET_COMPAT) + .value("CET_COMPAT_STRICT_MODE", CHARACTERISTICS::CET_COMPAT_STRICT_MODE) + .value("CET_SET_CONTEXT_IP_VALIDATION_RELAXED_MODE", CHARACTERISTICS::CET_SET_CONTEXT_IP_VALIDATION_RELAXED_MODE) + .value("CET_DYNAMIC_APIS_ALLOW_IN_PROC", CHARACTERISTICS::CET_DYNAMIC_APIS_ALLOW_IN_PROC) + .value("CET_RESERVED_1", CHARACTERISTICS::CET_RESERVED_1) + .value("CET_RESERVED_2", CHARACTERISTICS::CET_RESERVED_2) + .value("FORWARD_CFI_COMPAT", CHARACTERISTICS::FORWARD_CFI_COMPAT) + .value("HOTPATCH_COMPATIBLE", CHARACTERISTICS::HOTPATCH_COMPATIBLE); + + dbg + .def("has", &ExDllCharacteristics::has, + "Check if the given CHARACTERISTICS is used"_doc, "characteristic"_a + ) + .def_prop_ro("ex_characteristics", &ExDllCharacteristics::characteristics, + "The extended characteristics"_doc + ) + .def_prop_ro("ex_characteristics_list", &ExDllCharacteristics::characteristics_list, + "Characteristics as a vector"_doc + ); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyFPO.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyFPO.cpp new file mode 100644 index 0000000..03c85c5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyFPO.cpp @@ -0,0 +1,80 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "LIEF/PE/debug/FPO.hpp" + +#include +#include +#include "nanobind/utils.hpp" +#include "nanobind/stl/string.h" +#include "enums_wrapper.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ dbg(m, "FPO", + R"doc( + This class represents the ``IMAGE_DEBUG_TYPE_FPO`` debug entry + )doc"_doc); + + using FRAME_TYPE = FPO::FRAME_TYPE; + enum_(dbg, "FRAME_TYPE") + .value("FPO_", FRAME_TYPE::FPO) + .value("TRAP", FRAME_TYPE::TRAP) + .value("TSS", FRAME_TYPE::TSS) + .value("NON_FPO", FRAME_TYPE::NON_FPO); + + using entry_t = FPO::entry_t; + nb::class_(dbg, "entry_t", + R"doc( + Represents the stack frame layout for a x86 function when frame pointer + omission (FPO) optimization is used. + )doc"_doc + ) + .def_rw("rva", &entry_t::rva, + "The function RVA"_doc) + .def_rw("proc_size", &entry_t::proc_size, + "The number of bytes in the function."_doc) + .def_rw("nb_locals", &entry_t::nb_locals, + "The number of local variables."_doc) + .def_rw("parameters_size", &entry_t::parameters_size, + "The size of the parameters."_doc) + .def_rw("prolog_size", &entry_t::prolog_size, + "The number of bytes in the function prolog code."_doc) + .def_rw("nb_saved_regs", &entry_t::nb_saved_regs, + "Number of registers saved."_doc) + .def_rw("use_seh", &entry_t::use_seh, + "Whether the function uses structured exception handling."_doc) + .def_rw("use_bp", &entry_t::use_bp, + "Whether the EBP register has been allocated."_doc) + .def_rw("reserved", &entry_t::reserved, + "reserved for future use"_doc) + .def_rw("type", &entry_t::type, + "Variable that indicates the frame type."_doc) + LIEF_DEFAULT_STR(entry_t); + + init_ref_iterator(dbg, "it_entries"); + + dbg + .def_prop_ro("entries", nb::overload_cast<>(&FPO::entries), + "Iterator over the different FPO entries"_doc, + nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal + ); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyPDBChecksum.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyPDBChecksum.cpp new file mode 100644 index 0000000..1adf718 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyPDBChecksum.cpp @@ -0,0 +1,57 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/debug/PDBChecksum.hpp" + +#include +#include +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using HASH_ALGO = PDBChecksum::HASH_ALGO; + nb::class_ entry(m, "PDBChecksum", + R"doc( + This class represents the PDB Checksum debug entry which is essentially + an array of bytes representing the checksum of the PDB content. + )doc"_doc); + + nb::enum_(entry, "HASH_ALGO") + .value("UNKNOWN", HASH_ALGO::UNKNOWN) + .value("SHA256", HASH_ALGO::SHA256); + + entry + .def(nb::init>(), "algo"_a, "hash"_a) + .def_prop_rw("hash", + nb::overload_cast<>(&PDBChecksum::hash), + nb::overload_cast>(&PDBChecksum::hash), + "Hash of the PDB content"_doc + ) + + .def_prop_rw("algorithm", + nb::overload_cast<>(&PDBChecksum::algorithm, nb::const_), + nb::overload_cast(&PDBChecksum::algorithm), + "Algorithm used for hashing the PDB content"_doc + ) + LIEF_DEFAULT_STR(PDBChecksum); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyPogo.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyPogo.cpp new file mode 100644 index 0000000..b21afc7 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyPogo.cpp @@ -0,0 +1,59 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/PE/debug/Pogo.hpp" + +#include +#include +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ pogo(m, "Pogo"); + + init_ref_iterator(pogo, "it_entries"); + + enum_(pogo, "SIGNATURES") + .value(PY_ENUM(Pogo::SIGNATURES::UNKNOWN)) + .value(PY_ENUM(Pogo::SIGNATURES::ZERO)) + .value(PY_ENUM(Pogo::SIGNATURES::LCTG)) + .value(PY_ENUM(Pogo::SIGNATURES::PGI)) + .value(PY_ENUM(Pogo::SIGNATURES::PGO)) + .value(PY_ENUM(Pogo::SIGNATURES::PGU)) + .value(PY_ENUM(Pogo::SIGNATURES::SPGO)); + + pogo + .def(nb::init<>()) + + .def_prop_ro("entries", + nb::overload_cast<>(&Pogo::entries), + nb::keep_alive<0, 1>()) + + .def_prop_ro("signature", + nb::overload_cast<>(&Pogo::signature, nb::const_), + "Type of the pogo (" RST_CLASS_REF(lief.PE.Pogo.SIGNATURES) ")"_doc) + + LIEF_DEFAULT_STR(Pogo); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyPogoEntry.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyPogoEntry.cpp new file mode 100644 index 0000000..9789339 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyPogoEntry.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/debug/PogoEntry.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PogoEntry") + .def(nb::init<>()) + + .def_prop_rw("name", + [] (const PogoEntry& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&PogoEntry::name)) + + .def_prop_rw("start_rva", + nb::overload_cast<>(&PogoEntry::start_rva, nb::const_), + nb::overload_cast(&PogoEntry::start_rva)) + + .def_prop_rw("size", + nb::overload_cast<>(&PogoEntry::size, nb::const_), + nb::overload_cast(&PogoEntry::size)) + + LIEF_COPYABLE(PogoEntry) + LIEF_DEFAULT_STR(PogoEntry); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyRepro.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyRepro.cpp new file mode 100644 index 0000000..dfc1efb --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyRepro.cpp @@ -0,0 +1,46 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/debug/Repro.hpp" + +#include +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Repro", + R"delim( + This class represents a reproducible build entry from the debug directory. + (``IMAGE_DEBUG_TYPE_REPRO``). + This entry is usually generated with the undocumented `/Brepro` linker flag. + + See: https://nikhilism.com/post/2020/windows-deterministic-builds/ + )delim"_doc) + .def_prop_rw("hash", + [] (const Repro& repro) { + return nb::to_memoryview(repro.hash()); + }, + [] (Repro& repro, nb::bytes bytes) { + repro.hash(nb::to_vector(bytes)); + }, "The hash associated with the reproducible build"_doc) + LIEF_DEFAULT_STR(Repro); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/debug/pyVCFeatures.cpp b/vendor/lief/api/python/src/PE/objects/debug/pyVCFeatures.cpp new file mode 100644 index 0000000..19e25d2 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/debug/pyVCFeatures.cpp @@ -0,0 +1,71 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/debug/VCFeature.hpp" + +#include +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "VCFeature", + R"delim( + This class represents the ``IMAGE_DEBUG_TYPE_VC_FEATURE`` debug entry + )delim"_doc) + .def_prop_rw("pre_vcpp", + nb::overload_cast<>(&VCFeature::pre_vcpp, nb::const_), + nb::overload_cast(&VCFeature::pre_vcpp), + "Count for ``Pre-VC++ 11.00``"_doc, nb::rv_policy::reference_internal + ) + .def_prop_rw("c_cpp", + nb::overload_cast<>(&VCFeature::c_cpp, nb::const_), + nb::overload_cast(&VCFeature::c_cpp), + "Count for ``C/C++``"_doc, + nb::rv_policy::reference_internal + ) + .def_prop_rw("gs", + nb::overload_cast<>(&VCFeature::gs, nb::const_), + nb::overload_cast(&VCFeature::gs), + "Count for ``/GS`` (number of guard stack)"_doc, + nb::rv_policy::reference_internal + ) + .def_prop_rw("sdl", + nb::overload_cast<>(&VCFeature::sdl, nb::const_), + nb::overload_cast(&VCFeature::sdl), + R"doc( + Whether ``/sdl`` was enabled for this binary. + + ``sdl`` stands for Security Development Lifecycle and provides enhanced + security features like changing security-relevant warnings into errors or + enforcing guard stack. + )doc"_doc, + nb::rv_policy::reference_internal + ) + .def_prop_rw("guards", + nb::overload_cast<>(&VCFeature::guards, nb::const_), + nb::overload_cast(&VCFeature::guards), + "Count for ``/guardN``"_doc, + nb::rv_policy::reference_internal + ) + ; + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/CMakeLists.txt new file mode 100644 index 0000000..2049093 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/CMakeLists.txt @@ -0,0 +1,4 @@ +target_sources(pyLIEF PRIVATE + pyUnpackedFunction.cpp + pyPackedFunction.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyPackedFunction.cpp b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyPackedFunction.cpp new file mode 100644 index 0000000..45bcf0b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyPackedFunction.cpp @@ -0,0 +1,82 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/exceptions_info/AArch64/PackedFunction.hpp" + +#include +#include +#include + + +namespace LIEF::PE::py { + +using namespace unwind_aarch64; + +template<> +void create(nb::module_& m) { + nb::class_(m, "PackedFunction", + R"doc( + This class represents a packed AArch64 exception entry. + + An exception entry can be packed if the unwind data fit in 30 bits + + Reference: https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#packed-unwind-data + )doc"_doc) + + .def_prop_rw("frame_size", + nb::overload_cast<>(&PackedFunction::frame_size, nb::const_), + nb::overload_cast(&PackedFunction::frame_size), + "Size of the allocated stack"_doc) + + .def_prop_rw("reg_I", + nb::overload_cast<>(&PackedFunction::reg_I, nb::const_), + nb::overload_cast(&PackedFunction::reg_I), + R"doc( + Number of non-volatile INT registers (x19-x28) saved in the canonical + stack location. + )doc"_doc + ) + + .def_prop_rw("reg_F", + nb::overload_cast<>(&PackedFunction::reg_F, nb::const_), + nb::overload_cast(&PackedFunction::reg_F), + R"doc( + Number of non-volatile FP registers (d8-d15) saved in the canonical stack + location + )doc"_doc + ) + + .def_prop_rw("H", + nb::overload_cast<>(&PackedFunction::H, nb::const_), + nb::overload_cast(&PackedFunction::H), + R"doc( + 1-bit flag indicating whether the function homes the integer parameter + registers (x0-x7) by storing them at the very start of the function. + (0 = doesn't home registers, 1 = homes registers). + )doc"_doc + ) + + .def_prop_rw("CR", + nb::overload_cast<>(&PackedFunction::CR, nb::const_), + nb::overload_cast(&PackedFunction::CR), + R"doc( + Flag indicating whether the function includes extra instructions to set + up a frame chain and return link. + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyUnpackedFunction.cpp b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyUnpackedFunction.cpp new file mode 100644 index 0000000..b7eb6ad --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/AArch64/pyUnpackedFunction.cpp @@ -0,0 +1,146 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/exceptions_info/AArch64/UnpackedFunction.hpp" +#include "pyIterator.hpp" + +#include +#include +#include +#include + +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::PE::py { + +using namespace unwind_aarch64; + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ unpacked(m, "UnpackedFunction", + R"doc( + This class represents an unpacked AArch64 exception entry + + Reference: https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#xdata-records + )doc"_doc); + + using epilog_scope_t = UnpackedFunction::epilog_scope_t; + + nb::class_(unpacked, "epilog_scope_t", + R"doc( + This structure describes an epilog scope. + )doc"_doc + ) + .def_rw("start_offset", &epilog_scope_t::start_offset, + R"doc( + Offset of the epilog relative to the start of the function + )doc"_doc + ) + .def_rw("start_index", &epilog_scope_t::start_index, + R"doc( + Byte index of the first unwind code that describes this epilog + )doc"_doc + ) + .def_rw("reserved", &epilog_scope_t::reserved, + R"doc( + Reserved for future expansion. Should be 0. + )doc"_doc + ) + ; + + init_ref_iterator(unpacked, "it_epilog_scopes"); + + unpacked + .def_prop_rw("xdata_rva", + nb::overload_cast<>(&UnpackedFunction::xdata_rva, nb::const_), + nb::overload_cast(&UnpackedFunction::xdata_rva), + "RVA where this unpacked data is located (usually pointing in ``.xdata``)"_doc + ) + + .def_prop_rw("version", + nb::overload_cast<>(&UnpackedFunction::version, nb::const_), + nb::overload_cast(&UnpackedFunction::version), + R"doc( + Describes the version of the remaining ``.xdata``. + + Currently (2025-01-04), only version 0 is defined, so values of 1-3 aren't + permitted. + )doc"_doc + ) + + .def_prop_rw("X", + nb::overload_cast<>(&UnpackedFunction::X, nb::const_), + nb::overload_cast(&UnpackedFunction::X), + R"doc( + 1-bit field that indicates the presence (1) or absence (0) of exception + data. + )doc"_doc + ) + + .def_prop_rw("E", + nb::overload_cast<>(&UnpackedFunction::E, nb::const_), + nb::overload_cast(&UnpackedFunction::E), + R"doc( + 1-bit field that indicates that information describing a single epilog is + packed into the header (1) rather than requiring more scope words later (0). + )doc"_doc + ) + + .def_prop_ro("epilog_count", &UnpackedFunction::epilog_count, + R"doc( + **If E == 0**, specifies the count of the total number of epilog scopes. + Otherwise, return 0. + )doc"_doc + ) + .def_prop_ro("epilog_offset", &UnpackedFunction::epilog_offset, + R"doc( + **If E() == 1**, index of the first unwind code that describes the one and + only epilog. + )doc"_doc + ) + .def_prop_rw("code_words", + nb::overload_cast<>(&UnpackedFunction::code_words, nb::const_), + nb::overload_cast(&UnpackedFunction::code_words), + R"doc( + Number of 32-bit words needed to contain all of the unwind codes + )doc"_doc) + + .def_prop_rw("exception_handler", + nb::overload_cast<>(&UnpackedFunction::exception_handler, nb::const_), + nb::overload_cast(&UnpackedFunction::exception_handler), + "Exception handler RVA (if any)"_doc) + + .def_prop_rw("unwind_code", + nb::overload_cast<>(&UnpackedFunction::unwind_code), + nb::overload_cast>(&UnpackedFunction::unwind_code), + "Bytes that contain unwind codes"_doc + ) + + .def_prop_ro("epilog_scopes", + nb::overload_cast<>(&UnpackedFunction::epilog_scopes), + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>(), + "Iterator over the epilog scopes"_doc + ) + + .def_prop_ro("is_extended", + nb::overload_cast<>(&UnpackedFunction::is_extended, nb::const_), + "Whether it uses 2-words encoding"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/exceptions_info/CMakeLists.txt new file mode 100644 index 0000000..362ec37 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/CMakeLists.txt @@ -0,0 +1,7 @@ +target_sources(pyLIEF PRIVATE + pyRuntimeFunctionX64.cpp + pyRuntimeFunctionAArch64.cpp + pyUnwindCodeX64.cpp +) + +add_subdirectory(AArch64) diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionAArch64.cpp b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionAArch64.cpp new file mode 100644 index 0000000..374b6a3 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionAArch64.cpp @@ -0,0 +1,70 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/exceptions_info/RuntimeFunctionAArch64.hpp" + +#include +#include +#include + +namespace LIEF::PE::unwind_aarch64 { +class PackedFunction; +class UnpackedFunction; +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ rfunc(m, "RuntimeFunctionAArch64", + R"doc( + This class represents an entry in the exception table (``.pdata`` section) + for the AArch64 architecture. + + Since the ARM64 unwinding info can be encoded in a *packed* and *unpacked* + format, this class is inherited by :class:`lief.PE.unwind_aarch64.PackedFunction` + and :class:`lief.PE.unwind_aarch64.UnpackedFunction` + + Reference: https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling#arm64-exception-handling-information + )doc"_doc); + + using PACKED_FLAGS = RuntimeFunctionAArch64::PACKED_FLAGS; + nb::enum_(rfunc, "PACKED_FLAGS") + .value("UNPACKED", PACKED_FLAGS::UNPACKED) + .value("PACKED", PACKED_FLAGS::PACKED) + .value("PACKED_FRAGMENT", PACKED_FLAGS::PACKED_FRAGMENT) + .value("RESERVED", PACKED_FLAGS::RESERVED); + + rfunc + .def_prop_ro("length", &RuntimeFunctionAArch64::length, + "Length of the function in bytes"_doc) + + .def_prop_ro("flag", &RuntimeFunctionAArch64::flag, + "Flag describing the format the unwind data"_doc) + + .def_prop_ro("rva_end", &RuntimeFunctionAArch64::rva_end, + "Function end address"_doc) + ; + + nb::module_ submod = m.def_submodule("unwind_aarch64", + "Module related to PE-ARM64 unwinding code"_doc + ); + create(submod); + create(submod); + +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionX64.cpp b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionX64.cpp new file mode 100644 index 0000000..16a04fa --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyRuntimeFunctionX64.cpp @@ -0,0 +1,275 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/exceptions_info/RuntimeFunctionX64.hpp" +#include "LIEF/PE/exceptions_info/UnwindCodeX64.hpp" +#include "enums_wrapper.hpp" + +#include +#include +#include +#include +#include + +#include + +namespace LIEF::PE::unwind_x64::py { +void init(nb::module_& m); +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ rfunc(m, "RuntimeFunctionX64", + R"doc( + This class represents an entry in the exception table (``.pdata`` section) + for the x86-64 architecture. + + Reference: https://learn.microsoft.com/en-us/cpp/build/exception-handling-x64 + )doc"_doc); + + unwind_x64::py::init(m); + + enum_(rfunc, "UNWIND_FLAGS", nb::is_flag()) + .value("EXCEPTION_HANDLER", RuntimeFunctionX64::UNWIND_FLAGS::EXCEPTION_HANDLER, + R"doc( + The function has an exception handler that should be called when looking + for functions that need to examine exception + )doc"_doc + ) + + .value("TERMINATE_HANDLER", RuntimeFunctionX64::UNWIND_FLAGS::TERMINATE_HANDLER, + R"doc( + The function has a termination handler that should be called when + unwinding an exception. + )doc"_doc + ) + + .value("CHAIN_INFO", RuntimeFunctionX64::UNWIND_FLAGS::CHAIN_INFO, + R"doc( + The chained info payload references a previous ``RUNTIME_FUNCTION`` + )doc"_doc + ); + + enum_(rfunc, "UNWIND_OPCODES") + .value("PUSH_NONVOL", RuntimeFunctionX64::UNWIND_OPCODES::PUSH_NONVOL, + R"doc( + Push a nonvolatile integer register, decrementing RSP by 8. + The operation info is the number of the register. Because of the + constraints on epilogs, ``PUSH_NONVOL`` unwind codes must appear first + in the prolog and correspondingly, last in the unwind code array. + This relative ordering applies to all other unwind codes except + :attr:`~.UNWIND_OPCODES.PUSH_MACHFRAME`. + )doc"_doc + ) + + .value("ALLOC_LARGE", RuntimeFunctionX64::UNWIND_OPCODES::ALLOC_LARGE, + R"doc( + Allocate a large-sized area on the stack. + There are two forms. If the operation info equals 0, + then the size of the allocation divided by 8 is recorded in the next slot, + allowing an allocation up to 512K - 8. If the operation info equals 1, + then the unscaled size of the allocation is recorded in the next two + slots in little-endian format, allowing allocations up to 4GB - 8. + )doc"_doc + ) + + .value("ALLOC_SMALL", RuntimeFunctionX64::UNWIND_OPCODES::ALLOC_SMALL, + R"doc( + Allocate a small-sized area on the stack. The size of the allocation is + the operation info field * 8 + 8, allowing allocations up to 128 bytes. + )doc"_doc + ) + + .value("SET_FPREG", RuntimeFunctionX64::UNWIND_OPCODES::SET_FPREG, + R"doc( + Establish the frame pointer register by setting the register to some + offset of the current RSP. The offset is equal to the Frame Register + offset (scaled) field in the UNWIND_INFO * 16, allowing offsets from + 0 to 240. The use of an offset permits establishing a frame pointer that + points to the middle of the fixed stack allocation, helping code density + by allowing more accesses to use short instruction forms. The operation + info field is reserved and shouldn't be used. + )doc"_doc + ) + + .value("SAVE_NONVOL", RuntimeFunctionX64::UNWIND_OPCODES::SAVE_NONVOL, + R"doc( + Save a nonvolatile integer register on the stack using a MOV instead of a + PUSH. This code is primarily used for shrink-wrapping, where a nonvolatile + register is saved to the stack in a position that was previously allocated. + The operation info is the number of the register. The scaled-by-8 stack + offset is recorded in the next unwind operation code slot, as described + in the note above. + )doc"_doc + ) + + .value("SAVE_NONVOL_FAR", RuntimeFunctionX64::UNWIND_OPCODES::SAVE_NONVOL_FAR, + R"doc( + Save a nonvolatile integer register on the stack with a long offset, + using a MOV instead of a PUSH. This code is primarily used for + shrink-wrapping, where a nonvolatile register is saved to the stack in a + position that was previously allocated. The operation info is the number + of the register. The unscaled stack offset is recorded in the next two + unwind operation code slots, as described in the note above. + )doc"_doc) + + .value("SAVE_XMM128", RuntimeFunctionX64::UNWIND_OPCODES::SAVE_XMM128, + R"doc( + Save all 128 bits of a nonvolatile XMM register on the stack. + The operation info is the number of the register. The scaled-by-16 stack + offset is recorded in the next slot. + )doc"_doc + ) + + .value("SAVE_XMM128_FAR", RuntimeFunctionX64::UNWIND_OPCODES::SAVE_XMM128_FAR, + R"doc( + Save all 128 bits of a nonvolatile XMM register on the stack with a + long offset. The operation info is the number of the register. + The unscaled stack offset is recorded in the next two slots. + )doc"_doc + ) + + .value("PUSH_MACHFRAME", RuntimeFunctionX64::UNWIND_OPCODES::PUSH_MACHFRAME, + R"doc( + Push a machine frame. This unwind code is used to record the effect of a + hardware interrupt or exception. + )doc"_doc + ) + + .value("EPILOG", RuntimeFunctionX64::UNWIND_OPCODES::EPILOG, + R"doc( + This entry is only relevant for version 2. It describes the function + epilog. + )doc"_doc + ) + + .value("SPARE", RuntimeFunctionX64::UNWIND_OPCODES::SPARE, + R"doc( + Reserved + Originally SAVE_XMM128_FAR in version 1, but deprecated and removed + )doc"_doc + ) + ; + + enum_(rfunc, "UNWIND_REG") + .value("RAX", RuntimeFunctionX64::UNWIND_REG::RAX) + .value("RCX", RuntimeFunctionX64::UNWIND_REG::RCX) + .value("RDX", RuntimeFunctionX64::UNWIND_REG::RDX) + .value("RBX", RuntimeFunctionX64::UNWIND_REG::RBX) + .value("RSP", RuntimeFunctionX64::UNWIND_REG::RSP) + .value("RBP", RuntimeFunctionX64::UNWIND_REG::RBP) + .value("RSI", RuntimeFunctionX64::UNWIND_REG::RSI) + .value("RDI", RuntimeFunctionX64::UNWIND_REG::RDI) + .value("R8", RuntimeFunctionX64::UNWIND_REG::R8) + .value("R9", RuntimeFunctionX64::UNWIND_REG::R9) + .value("R10", RuntimeFunctionX64::UNWIND_REG::R10) + .value("R11", RuntimeFunctionX64::UNWIND_REG::R11) + .value("R12", RuntimeFunctionX64::UNWIND_REG::R12) + .value("R13", RuntimeFunctionX64::UNWIND_REG::R13) + .value("R14", RuntimeFunctionX64::UNWIND_REG::R14) + .value("R15", RuntimeFunctionX64::UNWIND_REG::R15); + + using unwind_info_t = RuntimeFunctionX64::unwind_info_t; + nb::class_(rfunc, "unwind_info_t") + .def_rw("version", &unwind_info_t::version, + "Version number of the unwind data, currently 1 or 2."_doc + ) + + .def_rw("flags", &unwind_info_t::flags, + "See: :class:`lief.PE.RuntimeFunctionX64.UNWIND_FLAGS`"_doc + ) + + .def_rw("sizeof_prologue", &unwind_info_t::sizeof_prologue, + "Length of the function prolog in bytes."_doc + ) + + .def_rw("count_opcodes", &unwind_info_t::count_opcodes, + R"doc( + The number of slots in the unwind codes array. Some unwind codes, for + example, :attr:`lief.PE.RuntimeFunctionX64.UNWIND_OPCODES.SAVE_NONVOL`, + require more than one slot in the array. + )doc"_doc + ) + + .def_rw("frame_reg", &unwind_info_t::frame_reg, + R"doc( + If nonzero, then the function uses a frame pointer (FP), and this field + is the number of the nonvolatile register used as the frame pointer, + using the same encoding for the operation info field of :class:`~.UNWIND_OPCODES` + node + )doc"_doc + ) + + .def_rw("frame_reg_offset", &unwind_info_t::frame_reg_offset, + R"doc( + If the frame register field is nonzero, this field is the scaled offset + from RSP that is applied to the FP register when it's established + )doc"_doc + ) + + .def_rw("raw_opcodes", &unwind_info_t::raw_opcodes, + R"doc( + An array of items that explains the effect of the prolog on the + nonvolatile registers and RSP + )doc"_doc + ) + + .def_rw("handler", &unwind_info_t::handler, + R"doc( + An image-relative pointer to either the function's language-specific + exception or termination handler. This value is set if one of these + flags is set: :attr:`lief.PE.RuntimeFunctionX64.UNWIND_FLAGS.EXCEPTION_HANDLER`, + :attr:`lief.PE.RuntimeFunctionX64.UNWIND_FLAGS.TERMINATE_HANDLER`. + )doc"_doc + ) + + .def_rw("chained", &unwind_info_t::chained, + R"doc( + If :attr:`lief.PE.RuntimeFunctionX64.UNWIND_FLAGS.CHAIN_INFO` is set, this attribute + references the chained runtime function. + )doc"_doc + ) + + .def("has", &unwind_info_t::has, + "Check if the given flag is used"_doc) + + .def_prop_ro("opcodes", &unwind_info_t::opcodes, + "Enhanced representation of the unwind code"_doc) + LIEF_DEFAULT_STR(unwind_info_t); + + rfunc + .def_prop_ro("rva_end", &RuntimeFunctionX64::rva_end, + "Function end address"_doc + ) + + .def_prop_ro("unwind_rva", &RuntimeFunctionX64::unwind_rva, + "Unwind info address"_doc + ) + + .def_prop_ro("size", &RuntimeFunctionX64::size, + "Size of the function (in bytes)"_doc + ) + + .def_prop_ro("unwind_info", nb::overload_cast<>(&RuntimeFunctionX64::unwind_info), + "Detailed unwind information"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/exceptions_info/pyUnwindCodeX64.cpp b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyUnwindCodeX64.cpp new file mode 100644 index 0000000..89f4c88 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/exceptions_info/pyUnwindCodeX64.cpp @@ -0,0 +1,160 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include + +#include "LIEF/PE/exceptions_info/UnwindCodeX64.hpp" +#include +#include +#include + +namespace LIEF::PE::unwind_x64::py { +template void create(nb::module_&); + + +template<> +void create(nb::module_& m) { + nb::class_(m, "Code", "Base class for all unwind operations"_doc) + .def_prop_ro("opcode", &Code::opcode, + "The original opcode"_doc + ) + + .def_prop_ro("position", &Code::position, + "Offset in the prolog"_doc + ) + LIEF_DEFAULT_STR(Code); +} + + +template<> +void create(nb::module_& m) { + nb::class_(m, "Alloc", + R"doc( + This class represents a stack-allocation operation + (:attr:`lief.PE.RuntimeFunctionX64.UNWIND_OPCODES.ALLOC_SMALL`, :attr:`lief.PE.RuntimeFunctionX64.UNWIND_OPCODES.ALLOC_LARGE`) + )doc"_doc) + + .def_prop_ro("size", &Alloc::size, + "The size allocated"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "PushNonVol", + R"doc( + Push a nonvolatile integer register, decrementing RSP by 8 + )doc"_doc) + + .def_prop_ro("reg", &PushNonVol::reg, + "The register pushed"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "PushMachFrame", + R"doc( + Push a machine frame + )doc"_doc) + + .def_prop_ro("value", &PushMachFrame::value, + "0 or 1"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "SetFPReg", + R"doc( + Establish the frame pointer register by setting the register to some offset + of the current RSP + )doc"_doc) + + .def_prop_ro("reg", &SetFPReg::reg, + "Frame pointer register"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "SaveNonVolatile", + R"doc( + Save a nonvolatile integer register on the stack using a MOV instead of a + PUSH. + )doc"_doc) + + .def_prop_ro("reg", &SaveNonVolatile::reg, + "The register to save"_doc + ) + + .def_prop_ro("offset", &SaveNonVolatile::offset, + "The offset where to save the register"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "SaveXMM128", + R"doc( + Save all 128 bits of a nonvolatile XMM register on the stack + )doc"_doc) + + .def_prop_ro("num", &SaveXMM128::num, + "XMM register number"_doc + ) + + .def_prop_ro("offset", &SaveXMM128::offset, + "The offset where to save the register"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "Epilog", + R"doc( + Describes the function's epilog + )doc"_doc) + + .def_prop_ro("flags", &Epilog::flags) + + .def_prop_ro("size", &Epilog::size, + "Size of the epilog"_doc + ); +} + +template<> +void create(nb::module_& m) { + nb::class_(m, "Spare"); +} + +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("unwind_x64", + "This namespace wraps code related to PE-x64 unwinding code"_doc + ); + + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyBinary.cpp b/vendor/lief/api/python/src/PE/objects/pyBinary.cpp new file mode 100644 index 0000000..beff016 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyBinary.cpp @@ -0,0 +1,592 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/Parser.hpp" +#include "LIEF/PE/Builder.hpp" +#include "LIEF/PE/Binary.hpp" +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/PE/RelocationEntry.hpp" +#include "LIEF/PE/Section.hpp" +#include "LIEF/PE/ResourceNode.hpp" +#include "LIEF/COFF/String.hpp" +#include "LIEF/PE/DataDirectory.hpp" +#include "LIEF/PE/TLS.hpp" +#include "LIEF/PE/Debug.hpp" +#include "LIEF/PE/Export.hpp" +#include "LIEF/PE/RichHeader.hpp" +#include "LIEF/PE/ExceptionInfo.hpp" +#include "LIEF/PE/LoadConfigurations/LoadConfiguration.hpp" + +#include "PE/pyPE.hpp" + +#include "pyErr.hpp" +#include "pyIterator.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/extra/stl/pathlike.h" +#include "nanobind/utils.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ bin(m, "Binary", + R"delim( + Class which represents a PE binary which is the main interface + to manage and modify a PE executable. + + This object can be instantiated through :func:`lief.parse` or :func:`lief.PE.parse` while + the constructor of this object can be used to craft a binary from scratch (see: :ref:`02-pe-from-scratch`) + )delim"_doc); + + init_ref_iterator(bin, "it_section"); + init_ref_iterator(bin, "it_data_directories"); + init_ref_iterator(bin, "it_relocations"); + init_ref_iterator(bin, "it_imports"); + init_ref_iterator(bin, "it_delay_imports"); + init_ref_iterator(bin, "it_symbols"); + init_ref_iterator(bin, "it_const_signatures"); + init_ref_iterator(bin, "it_debug"); + init_ref_iterator(bin, "it_strings_table"); + init_ref_iterator(bin, "it_exceptions"); + + bin + .def_prop_ro("sections", + nb::overload_cast<>(&Binary::sections), + "Return an iterator over the PE's " RST_CLASS_REF(lief.PE.Section) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("dos_header", + nb::overload_cast<>(&Binary::dos_header, nb::const_), + "Return the " RST_CLASS_REF(lief.PE.DosHeader) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("header", + nb::overload_cast<>(&Binary::header, nb::const_), + "Return the " RST_CLASS_REF(lief.PE.Header) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("optional_header", + nb::overload_cast<>(&Binary::optional_header, nb::const_), + R"doc( + Header that follows the :attr:`~.header`. It is named optional from the + COFF specifications but it is mandatory in a PE file. + )doc"_doc, + nb::rv_policy::reference_internal) + + .def("compute_checksum", + &Binary::compute_checksum, + R"delim( + Re-compute the value of :attr:`~lief.PE.OptionalHeader.checksum`. + If both values do not match, it could mean that the binary has been modified + after the compilation. + + This value is computed by LIEF for the current binary object. + )delim"_doc) + + .def_prop_ro("virtual_size", + &Binary::virtual_size, + R"delim( + Return the binary's virtual size. + + This value should match :attr:`~lief.PE.OptionalHeader.sizeof_image` + )delim"_doc) + + .def_prop_ro("sizeof_headers", + &Binary::sizeof_headers, + "Size of all the PE headers"_doc) + + .def("rva_to_offset", + &Binary::rva_to_offset, + "rva_address"_a, + R"delim( + Convert a relative virtual address to an offset + + The conversion is performed by looking for the section that encompasses the provided RVA. + )delim"_doc) + + .def("va_to_offset", + &Binary::va_to_offset, + "va_address"_a, + R"delim( + Convert an **absolute** virtual address into an offset + + See: :meth:`~lief.PE.Binary.rva_to_offset` + )delim"_doc) + + .def("offset_to_rva", + &Binary::offset_to_rva, + "offset"_a, + "Convert the given offset into a relative virtual address (RVA)."_doc) + + .def("section_from_offset", + nb::overload_cast(&Binary::section_from_offset), + R"delim( + Return the :class:`~lief.PE.Section` which encompasses the provided offset. + It returns None if a section can't be found. + )delim"_doc, + "offset"_a, + nb::rv_policy::reference_internal) + + .def("section_from_rva", + nb::overload_cast(&Binary::section_from_rva), + R"delim( + Return the :class:`~lief.PE.Section` which encompasses the provided **relative** virtual address. + If a section can't be found, it returns None. + )delim"_doc, + "rva"_a, + nb::rv_policy::reference_internal) + + .def_prop_rw("tls", + nb::overload_cast<>(&Binary::tls), + nb::overload_cast(&Binary::tls), + "" RST_CLASS_REF(lief.PE.TLS) " object (if present)"_doc, + nb::rv_policy::reference_internal) + + .def("remove_tls", &Binary::remove_tls, + "Remove the TLS from the binary"_doc, nb::lock_self()) + + .def_prop_rw("rich_header", + nb::overload_cast<>(&Binary::rich_header), + nb::overload_cast(&Binary::rich_header), + "" RST_CLASS_REF(lief.PE.RichHeader) " object (if present)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_rich_header", &Binary::has_rich_header, + "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.RichHeader) " object"_doc) + + .def_prop_ro("has_debug", &Binary::has_debug, + "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Debug) " object"_doc) + + .def_prop_ro("has_tls", &Binary::has_tls, + "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.TLS) " object"_doc) + + .def_prop_ro("has_imports", &Binary::has_imports, + "``True`` if the current binary has imports (" RST_CLASS_REF(lief.PE.Import) ")"_doc) + + .def_prop_ro("has_exports", &Binary::has_exports, + "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Export) " object"_doc) + + .def_prop_ro("has_resources", &Binary::has_resources, + "``True`` if the current binary has a " RST_CLASS_REF(lief.PE.Resources) " object"_doc) + + .def_prop_ro("has_exceptions", &Binary::has_exceptions, + "``True`` if the current binary uses ``Exceptions``"_doc) + + .def_prop_ro("has_relocations", &Binary::has_relocations, + "``True`` if the current binary uses " RST_CLASS_REF(lief.PE.Relocation) ""_doc) + + .def_prop_ro("has_configuration", &Binary::has_configuration, + "``True`` if the current binary has " RST_CLASS_REF(lief.PE.LoadConfiguration) ""_doc) + + .def_prop_ro("has_signatures", &Binary::has_signatures, + "``True`` if the binary is signed with the PE authenticode (" RST_CLASS_REF(lief.PE.Signature) ")"_doc) + + .def_prop_ro("is_reproducible_build", &Binary::is_reproducible_build, + "``True`` if the binary was compiled with a reproducible build directive (" RST_CLASS_REF(lief.PE.Debug) ")"_doc) + + .def_prop_ro("functions", + &Binary::functions, + "**All** " RST_CLASS_REF(lief.Function) " found in the binary"_doc) + + .def_prop_ro("exception_functions", + &Binary::exception_functions, + "" RST_CLASS_REF(lief.Function) " found in the Exception directory"_doc) + + .def_prop_ro("signatures", + nb::overload_cast<>(&Binary::signatures, nb::const_), + "Return an iterator over the " RST_CLASS_REF(lief.PE.Signature) " objects"_doc, + nb::keep_alive<0, 1>()) + + .def("authentihash", + [] (const Binary& bin, ALGORITHMS algo) { + return nb::to_bytes(bin.authentihash(algo)); + }, + "Compute the authentihash according to the " RST_CLASS_REF(lief.PE.ALGORITHMS) " " + "given in the first parameter"_doc, + "algorithm"_a) + + .def("verify_signature", + nb::overload_cast(&Binary::verify_signature, nb::const_), + R"delim( + Verify the binary against the embedded signature(s) (if any) + + First off, it checks that the embedded signatures are correct (c.f. :meth:`lief.PE.Signature.check`) + and then it checks that the authentihash matches :attr:`lief.PE.ContentInfo.digest` + + One can tweak the verification process with the :class:`lief.PE.Signature.VERIFICATION_CHECKS` flags + + .. seealso:: + + :meth:`lief.PE.Signature.check` + )delim"_doc, + "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT) + + .def("verify_signature", + nb::overload_cast(&Binary::verify_signature, nb::const_), + R"delim( + Verify the binary with the Signature object provided in the first parameter + It can be used to verify a detached signature: + + .. code-block:: python + + detached = lief.PE.Signature.parse("sig.pkcs7") + binary.verify_signature(detached) + )delim"_doc, + "signature"_a, "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT) + + .def_prop_ro("authentihash_md5", + [] (const Binary& bin) { + return nb::to_bytes(bin.authentihash(ALGORITHMS::MD5)); + }, + "Authentihash **MD5** value"_doc) + + .def_prop_ro("authentihash_sha1", + [] (const Binary& bin) { + return nb::to_bytes(bin.authentihash(ALGORITHMS::SHA_1)); + }, + "Authentihash **SHA1** value"_doc) + + .def_prop_ro("authentihash_sha256", + [] (const Binary& bin) { + return nb::to_bytes(bin.authentihash(ALGORITHMS::SHA_256)); + }, + "Authentihash **SHA-256** value"_doc) + + .def_prop_ro("authentihash_sha512", + [] (const Binary& bin) { + return nb::to_bytes(bin.authentihash(ALGORITHMS::SHA_512)); + }, + "Authentihash **SHA-512** value"_doc) + + .def_prop_ro("debug", + nb::overload_cast<>(&Binary::debug), + "Return the " RST_CLASS_REF(lief.PE.Debug) ""_doc, + nb::rv_policy::reference_internal) + + .def("add_debug_info", &Binary::add_debug_info, + "Add a new debug entry"_doc, + "entry"_a, nb::lock_self(), nb::rv_policy::reference_internal) + + .def("remove_debug", &Binary::remove_debug, + "Remove a specific debug entry"_doc, + "entry"_a, nb::lock_self()) + + .def("clear_debug", &Binary::clear_debug, + "Remove all debug info from the binary"_doc, nb::lock_self()) + + .def_prop_ro("codeview_pdb", + nb::overload_cast<>(&Binary::codeview_pdb, nb::const_), + "Return the :class:`~.CodeViewPDB` if present"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("load_configuration", + nb::overload_cast<>(&Binary::load_configuration), + "Return the " RST_CLASS_REF(lief.PE.LoadConfiguration) " object or None if not present"_doc, + nb::rv_policy::reference_internal) + + .def("get_export", + nb::overload_cast<>(&Binary::get_export), + "Return the " RST_CLASS_REF(lief.PE.Export) " object"_doc, + nb::rv_policy::reference_internal) + + .def("set_export", &Binary::set_export, + "Add or replace the export table"_doc, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def_prop_ro("symbols", + nb::overload_cast<>(&Binary::symbols), + "Return binary's " RST_CLASS_REF(lief.PE.Symbol) ""_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + + .def("get_section", + nb::overload_cast(&Binary::get_section), + "Return the " RST_CLASS_REF(lief.PE.Section) " object from the given name or None if not found"_doc, + "section_name"_a, + nb::rv_policy::reference_internal) + + .def("add_section", + &Binary::add_section, + "Add a " RST_CLASS_REF(lief.PE.Section) " to the binary."_doc, + "section"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def_prop_ro("relocations", + nb::overload_cast<>(&Binary::relocations), + "Return an iterator over the " RST_CLASS_REF(lief.PE.Relocation) ""_doc, + nb::keep_alive<0, 1>()) + + .def("add_relocation", + &Binary::add_relocation, + "Add a " RST_CLASS_REF(lief.PE.Relocation) " to the binary"_doc, + "relocation"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("remove_all_relocations", &Binary::remove_all_relocations, nb::lock_self()) + + .def("remove", + nb::overload_cast(&Binary::remove), + "Remove the " RST_CLASS_REF(lief.PE.Section) " given in first parameter"_doc, + "section"_a, "clear"_a = false, nb::lock_self()) + + .def_prop_ro("data_directories", + nb::overload_cast<>(&Binary::data_directories), + "Return an iterator over the " RST_CLASS_REF(lief.PE.DataDirectory) ""_doc, + nb::keep_alive<0, 1>()) + + .def("data_directory", + nb::overload_cast(&Binary::data_directory), + "Return the " RST_CLASS_REF(lief.PE.DataDirectory) " object from the given " RST_CLASS_REF(lief.PE.DataDirectory.TYPES) " type"_doc, + "type"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("imports", + nb::overload_cast<>(&Binary::imports), + "Return an iterator over the " RST_CLASS_REF(lief.PE.Import) " libraries"_doc, + nb::keep_alive<0, 1>()) + + .def("has_import", + &Binary::has_import, + "``True`` if the binary imports the given library name"_doc, + "import_name"_a) + + .def("get_import", + nb::overload_cast(&Binary::get_import), + "Return the :class:`~.Import` from the given name or None if it can't be found"_doc, + "import_name"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("delay_imports", + nb::overload_cast<>(&Binary::delay_imports), + "Return an iterator over the " RST_CLASS_REF(lief.PE.DelayImport) " "_doc) + + .def_prop_ro("has_delay_imports", &Binary::has_delay_imports, + "``True`` if the current binary has delay imports (" RST_CLASS_REF(lief.PE.DelayImport) ")"_doc) + + .def("has_delay_import", + &Binary::has_delay_import, + "``True`` if the binary imports the given library name"_doc, + "import_name"_a) + + .def("get_delay_import", + nb::overload_cast(&Binary::get_delay_import), + "Return the " RST_CLASS_REF(lief.PE.DelayImport) " from the given name or None if not found"_doc, + "import_name"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("resources_manager", + [] (Binary& self) { + return error_or(&Binary::resources_manager, self); + }, nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal, + "Return the " RST_CLASS_REF(lief.PE.ResourcesManager) " to manage resources"_doc) + + .def_prop_ro("resources", + nb::overload_cast<>(&Binary::resources), + "Return the " RST_CLASS_REF(lief.PE.ResourceNode) " tree or None if not present"_doc, + nb::rv_policy::reference_internal, nb::keep_alive<0, 1>()) + + .def_prop_ro("overlay", + nb::overload_cast<>(&Binary::overlay, nb::const_), + "Return the overlay content as a ``list`` of bytes"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("overlay_offset", &Binary::overlay_offset, + "Return the original overlay offset") + + .def_prop_rw("dos_stub", + nb::overload_cast<>(&Binary::dos_stub, nb::const_), + nb::overload_cast>(&Binary::dos_stub), + "DOS stub content as a ``list`` of bytes"_doc) + + .def("add_import", &Binary::add_import, + R"doc( + Add an imported library (i.e. ``DLL``) to the binary. + + The second parameter ``pos`` defines where to insert the import. + If negative (default), the import is appended to the end of the list. + )doc"_doc, + "import_name"_a, "pos"_a = -1, + nb::lock_self(), + nb::rv_policy::reference_internal) + + .def("remove_import", &Binary::remove_import, + "Remove the imported library with the given name"_doc, + "name"_a, nb::lock_self()) + + .def("remove_all_imports", &Binary::remove_all_imports, + "Remove all imported libraries"_doc, nb::lock_self()) + + .def("set_resources", + nb::overload_cast(&Binary::set_resources), + R"doc( + Change or set the current resource tree with the new one provided in + parameter. + )doc"_doc, "new_tree"_a, + nb::lock_self(), + nb::rv_policy::reference_internal + ) + + .def_prop_ro("exceptions", nb::overload_cast<>(&Binary::exceptions), + R"doc( + Iterator over the exception (``_RUNTIME_FUNCTION``) functions. + + .. warning:: + + This property requires that the option :attr:`lief.PE.ParserConfig.parse_exceptions` + was turned on (default is ``False``) when parsing the binary. + )doc"_doc, + nb::keep_alive<0, 1>(), nb::rv_policy::reference_internal) + + .def_prop_ro("export_dir", nb::overload_cast<>(&Binary::export_dir), + "Return the data directory associated with the export table"_doc + ) + + .def_prop_ro("import_dir", nb::overload_cast<>(&Binary::import_dir), + "Return the data directory associated with the import table"_doc + ) + + .def_prop_ro("rsrc_dir", nb::overload_cast<>(&Binary::rsrc_dir), + "Return the data directory associated with the resources tree"_doc + ) + + .def_prop_ro("exceptions_dir", nb::overload_cast<>(&Binary::exceptions_dir), + "Return the data directory associated with the exceptions"_doc + ) + + .def_prop_ro("cert_dir", nb::overload_cast<>(&Binary::cert_dir), + R"doc( + Return the data directory associated with the certificate table + (authenticode). + )doc"_doc + ) + + .def_prop_ro("relocation_dir", nb::overload_cast<>(&Binary::relocation_dir), + "Return the data directory associated with the relocation table"_doc + ) + + .def_prop_ro("debug_dir", nb::overload_cast<>(&Binary::debug_dir), + "Return the data directory associated with the debug table"_doc + ) + + .def_prop_ro("tls_dir", nb::overload_cast<>(&Binary::tls_dir), + "Return the data directory associated with TLS"_doc + ) + + .def_prop_ro("load_config_dir", nb::overload_cast<>(&Binary::load_config_dir), + "Return the data directory associated with the load config"_doc + ) + + .def_prop_ro("iat_dir", nb::overload_cast<>(&Binary::iat_dir), + "Return the data directory associated with the IAT"_doc + ) + + .def_prop_ro("delay_dir", nb::overload_cast<>(&Binary::delay_dir), + "Return the data directory associated with delayed imports"_doc + ) + + .def_prop_ro("is_arm64ec", &Binary::is_arm64ec, + "True if this binary is compiled in ARM64EC mode (emulation compatible)"_doc + ) + + .def_prop_ro("is_arm64x", &Binary::is_arm64x, + R"doc( + True if this binary is compiled in ARM64X mode (contains both ARM64 and + ARM64EC)doc"_doc + ) + + .def("write", + [] (Binary& self, nb::PathLike path) { self.write(path); }, + "Build the binary and write the result in the given ``output`` file"_doc, + "output_path"_a, nb::lock_self()) + + .def("write", + [] (Binary& self, nb::PathLike path, const Builder::config_t& config) { + self.write(path, config); + }, + "Build the binary with the given config and write the result in the given ``output`` file"_doc, + "output_path"_a, "config"_a, nb::lock_self()) + + .def("write_to_bytes", [] (Binary& bin, const Builder::config_t& config) -> nb::bytes { + std::ostringstream out; + bin.write(out, config); + return nb::to_bytes(out.str()); + }, "config"_a, nb::lock_self()) + + .def("write_to_bytes", [] (Binary& bin) -> nb::bytes { + std::ostringstream out; + bin.write(out); + return nb::to_bytes(out.str()); + }, nb::lock_self()) + + .def("fill_address", &Binary::fill_address, + "Fill the content at the provided address with a fixed value"_doc, + "address"_a, "size"_a, "value"_a = 0, "addr_type"_a = Binary::VA_TYPES::AUTO, + nb::lock_self()) + + .def_prop_ro("coff_string_table", nb::overload_cast<>(&Binary::coff_string_table), + "Iterator over the strings located in the COFF string table"_doc, + nb::keep_alive<0, 1>()) + + .def("find_coff_string", nb::overload_cast(&Binary::find_coff_string), + R"doc( + Try to find the COFF string at the given offset in the COFF string table. + + .. warning:: + + This offset must include the first 4 bytes holding the size of + the table. Hence, the first string starts a the offset 4. + )doc"_doc, "offset"_a, + nb::rv_policy::reference_internal) + + .def("find_exception_at", nb::overload_cast(&Binary::find_exception_at), + R"doc( + Try to find the exception info at the given RVA. + + .. warning:: + + This property requires that the option :attr:`lief.PE.ParserConfig.parse_exceptions` + was turned on (default is ``False``) when parsing the binary. + )doc"_doc, "rva"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("nested_pe_binary", nb::overload_cast<>(&Binary::nested_pe_binary), + R"doc( + If the current binary contains dynamic relocations + (e.g. :class:`lief.PE.DynamicFixupARM64X`), this function returns the + **relocated** view of the current PE. + + This can be used to get the alternative PE binary, targeting a different + architecture. + + .. warning:: + + This property requires that the option :attr:`lief.PE.ParserConfig.parse_arm64x_binary` + was turned on (default is ``False``) when parsing the binary. + )doc"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(Binary); + +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyBuilder.cpp b/vendor/lief/api/python/src/PE/objects/pyBuilder.cpp new file mode 100644 index 0000000..5ba0ace --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyBuilder.cpp @@ -0,0 +1,154 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "pyErr.hpp" +#include "LIEF/PE/Builder.hpp" +#include "LIEF/PE/Binary.hpp" + +#include +#include +#include "nanobind/utils.hpp" +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ builder(m, "Builder"); + + nb::class_ config(builder, "config_t", + R"doc( + This structure is used to configure the build operation. + + The default value of these attributes is set to ``False`` if the + operation modifies the binary layout even though nothing changed. + For instance, building the import table **always** requires relocating the + table to another place. Thus, the default value is false and must + be explicitly set to true. + )doc"_doc + ); + config + .def(nb::init<>()) + .def_rw("imports", &Builder::config_t::imports, + R"doc( + Whether the builder should reconstruct the imports table. + This option should be turned on if you modify imports. + + Please check LIEF website for more details + )doc"_doc) + .def_rw("exports", &Builder::config_t::exports, + R"doc( + Whether the builder should reconstruct the export table + This option should be turned on if you modify exports. + + Please check LIEF website for more details + )doc"_doc) + .def_rw("resources", &Builder::config_t::resources, + R"doc( + Whether the builder should regenerate the resources tree + )doc"_doc) + .def_rw("relocations", &Builder::config_t::relocations, + R"doc( + Whether the builder should regenerate relocations + )doc"_doc) + .def_rw("load_configuration", &Builder::config_t::load_configuration, + R"doc( + Whether the builder should regenerate the load configuration + )doc"_doc) + .def_rw("tls", &Builder::config_t::tls, + R"doc( + Whether the builder should regenerate the TLS info + )doc"_doc) + .def_rw("overlay", &Builder::config_t::overlay, + R"doc( + Whether the builder should write back any overlay data + )doc"_doc) + .def_rw("debug", &Builder::config_t::debug, + R"doc( + Whether the builder should regenerate debug entries + )doc"_doc) + .def_rw("dos_stub", &Builder::config_t::dos_stub, + R"doc( + Whether the builder should write back dos stub (including the rich header) + )doc"_doc) + + .def_rw("rsrc_section", &Builder::config_t::rsrc_section, + R"doc( + If the resources tree needs to be relocated, this attribute defines the + name of the new section that contains the relocated tree. + )doc"_doc) + + .def_rw("idata_section", &Builder::config_t::idata_section, + R"doc( + Section that holds the relocated import table (IAT/ILT) + )doc"_doc) + + .def_rw("tls_section", &Builder::config_t::tls_section, + R"doc( + Section that holds the relocated TLS info + )doc"_doc) + + .def_rw("reloc_section", &Builder::config_t::reloc_section, + R"doc( + Section that holds the relocated relocations + )doc"_doc) + + .def_rw("export_section", &Builder::config_t::export_section, + R"doc( + Section that holds the export table + )doc"_doc) + + .def_rw("debug_section", &Builder::config_t::debug_section, + R"doc( + Section that holds the debug entries + )doc"_doc) + + .def_rw("resolved_iat_cbk", &Builder::config_t::resolved_iat_cbk) + .def_rw("force_relocating", &Builder::config_t::force_relocating) + ; + + builder + .def(nb::init(), + "binary"_a, "config"_a) + + .def_prop_ro("rsrc_data", [] (const Builder& self) { + return nb::to_memoryview(self.rsrc_data()); + }) + + .def("build", + [] (Builder& self) { + return error_or(static_cast(&Builder::build), self); + }, + "Perform the build process"_doc, nb::lock_self()) + + .def("write", + static_cast(&Builder::write), + "Write the build result into the ``output`` file"_doc, + "output"_a, nb::lock_self()) + + .def("raw_bytes", [] (Builder& self) { + std::ostringstream out; + self.write(out); + return nb::to_bytes(out.str()); + }, nb::lock_self()) + ; + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyCodeIntegrity.cpp b/vendor/lief/api/python/src/PE/objects/pyCodeIntegrity.cpp new file mode 100644 index 0000000..25c7811 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyCodeIntegrity.cpp @@ -0,0 +1,54 @@ + +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/CodeIntegrity.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "CodeIntegrity") + .def(nb::init<>()) + + .def_prop_rw("flags", + nb::overload_cast<>(&CodeIntegrity::flags, nb::const_), + nb::overload_cast(&CodeIntegrity::flags), + "Flags to indicate if CI information is available, etc."_doc) + + .def_prop_rw("catalog", + nb::overload_cast<>(&CodeIntegrity::catalog, nb::const_), + nb::overload_cast(&CodeIntegrity::catalog), + "``0xFFFF`` means not available"_doc) + + .def_prop_rw("catalog_offset", + nb::overload_cast<>(&CodeIntegrity::catalog_offset, nb::const_), + nb::overload_cast(&CodeIntegrity::catalog_offset)) + + .def_prop_rw("reserved", + nb::overload_cast<>(&CodeIntegrity::reserved, nb::const_), + nb::overload_cast(&CodeIntegrity::reserved), + "Additional bitmask to be defined later"_doc) + + LIEF_DEFAULT_STR(CodeIntegrity); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyDataDirectory.cpp b/vendor/lief/api/python/src/PE/objects/pyDataDirectory.cpp new file mode 100644 index 0000000..3d6728e --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyDataDirectory.cpp @@ -0,0 +1,89 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include "nanobind/extra/stl/lief_span.h" + +#include "enums_wrapper.hpp" +#include "LIEF/PE/DataDirectory.hpp" +#include "LIEF/PE/Section.hpp" + +#include "PE/pyPE.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ data_dir(m, "DataDirectory", + R"delim( + Class that represents a PE data directory entry + )delim"_doc); + + enum_(data_dir, "TYPES") + .value(PY_ENUM(DataDirectory::TYPES::EXPORT_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::IMPORT_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::RESOURCE_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::EXCEPTION_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::CERTIFICATE_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::BASE_RELOCATION_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::DEBUG_DIR)) + .value(PY_ENUM(DataDirectory::TYPES::ARCHITECTURE)) + .value(PY_ENUM(DataDirectory::TYPES::GLOBAL_PTR)) + .value(PY_ENUM(DataDirectory::TYPES::TLS_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::LOAD_CONFIG_TABLE)) + .value(PY_ENUM(DataDirectory::TYPES::BOUND_IMPORT)) + .value(PY_ENUM(DataDirectory::TYPES::IAT)) + .value(PY_ENUM(DataDirectory::TYPES::DELAY_IMPORT_DESCRIPTOR)) + .value(PY_ENUM(DataDirectory::TYPES::CLR_RUNTIME_HEADER)) + .value(PY_ENUM(DataDirectory::TYPES::RESERVED)) + .value(PY_ENUM(DataDirectory::TYPES::UNKNOWN)); + + data_dir + .def(nb::init<>()) + .def_prop_rw("rva", + nb::overload_cast<>(&DataDirectory::RVA, nb::const_), + nb::overload_cast(&DataDirectory::RVA), + "**Relative** virtual address of the content associated with the current data directory"_doc) + + .def_prop_rw("size", + nb::overload_cast<>(&DataDirectory::size, nb::const_), + nb::overload_cast(&DataDirectory::size), + "Size in bytes of the content associated with the current data directory"_doc) + + .def_prop_ro("section", + nb::overload_cast<>(&DataDirectory::section), + "" RST_CLASS_REF(lief.PE.Section) " associated with the current data directory or None if not linked"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("content", nb::overload_cast<>(&DataDirectory::content, nb::const_), + "Raw content (bytes) referenced by this data directory"_doc) + + .def_prop_ro("type", + &DataDirectory::type, + "Type (" RST_CLASS_REF(lief.PE.DataDirectory.TYPES) ") of the current data directory"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("has_section", + &DataDirectory::has_section, + "``True`` if the current data directory is tied to a " RST_CLASS_REF(lief.PE.Section) ""_doc) + + LIEF_COPYABLE(DataDirectory) + LIEF_DEFAULT_STR(DataDirectory); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyDelayImport.cpp b/vendor/lief/api/python/src/PE/objects/pyDelayImport.cpp new file mode 100644 index 0000000..2d4631f --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyDelayImport.cpp @@ -0,0 +1,117 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/DelayImport.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ imp(m, "DelayImport", + R"delim( + Class that represents a PE delay import + )delim"_doc); + + init_ref_iterator(imp, "it_entries"); + + imp + .def(nb::init(), + "Constructor from a library name"_doc, + "library_name"_a) + + .def_prop_ro("entries", + nb::overload_cast<>(&DelayImport::entries), + "Iterator over the " RST_CLASS_REF(lief.PE.DelayImportEntry) " (functions)"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_rw("name", + [] (const DelayImport& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&DelayImport::name), + "Library name (e.g. ``kernel32.dll``)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("attribute", + nb::overload_cast<>(&DelayImport::attribute, nb::const_), + nb::overload_cast(&DelayImport::attribute), + R"delim( + Reserved and **should** be zero according to the PE specifications + )delim"_doc) + + .def_prop_rw("handle", + nb::overload_cast<>(&DelayImport::handle, nb::const_), + nb::overload_cast(&DelayImport::handle), + R"delim( + The RVA of the module handle (in the ``.data`` section) + It is used for storage by the routine that is supplied to manage delay-loading. + )delim"_doc) + + .def_prop_rw("iat", + nb::overload_cast<>(&DelayImport::iat, nb::const_), + nb::overload_cast(&DelayImport::iat), + R"delim( + RVA of the delay-load import address table. + )delim"_doc) + + .def_prop_rw("names_table", + nb::overload_cast<>(&DelayImport::names_table, nb::const_), + nb::overload_cast(&DelayImport::names_table), + R"delim( + RVA of the delay-load import names table. + The content of this table has the same layout as the Import lookup table + )delim"_doc) + + .def_prop_rw("biat", + nb::overload_cast<>(&DelayImport::biat, nb::const_), + nb::overload_cast(&DelayImport::biat), + R"delim( + RVA of the **bound** delay-load import address table or 0 + if the table does not exist. + )delim"_doc) + + + .def_prop_rw("uiat", + nb::overload_cast<>(&DelayImport::uiat, nb::const_), + nb::overload_cast(&DelayImport::uiat), + R"delim( + RVA of the **unload** delay-load import address table or 0 + if the table does not exist. + + According to the PE specifications, this table is an + exact copy of the delay import address table that can be + used to restore the original IAT in the case of unloading. + )delim"_doc) + + .def_prop_rw("timestamp", + nb::overload_cast<>(&DelayImport::timestamp, nb::const_), + nb::overload_cast(&DelayImport::timestamp), + R"delim( + The timestamp of the DLL to which this image has been bound. + )delim"_doc) + + LIEF_COPYABLE(DelayImport) + LIEF_DEFAULT_STR(DelayImport); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyDelayImportEntry.cpp b/vendor/lief/api/python/src/PE/objects/pyDelayImportEntry.cpp new file mode 100644 index 0000000..af9f87d --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyDelayImportEntry.cpp @@ -0,0 +1,85 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +#include "LIEF/PE/DelayImportEntry.hpp" + +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DelayImportEntry", + R"delim( + Class that represents an entry (i.e. a delay import) in the delay import table (:class:`~lief.PE.DelayImport`). + + It extends the :class:`lief.Symbol` generic class that provides the :attr:`lief.Symbol.name` + and :attr:`lief.Symbol.value` + + The meaning of :attr:`lief.Symbol.value` for this PE object is the address (as an RVA) in the IAT + where the resolution should take place + )delim"_doc) + .def(nb::init<>()) + + .def_prop_ro("demangled_name", + &DelayImportEntry::demangled_name, + R"doc( + Demangled representation of the symbol or an empty string if it can't + be demangled. + )doc"_doc + ) + + .def_prop_rw("name", + [] (const DelayImportEntry& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&DelayImportEntry::name), + "Delay import name if not ordinal"_doc) + + .def_prop_rw("data", + nb::overload_cast<>(&DelayImportEntry::data, nb::const_), + nb::overload_cast(&DelayImportEntry::data), + "Raw value"_doc) + + .def_prop_ro("is_ordinal", + &DelayImportEntry::is_ordinal, + "``True`` if it is an import by ordinal"_doc) + + .def_prop_ro("ordinal", + &DelayImportEntry::ordinal, + "Ordinal value (if any). See: :attr:`~lief.PE.DelayImportEntry.is_ordinal`"_doc) + + .def_prop_ro("hint", + &DelayImportEntry::hint, + "Index into the :attr:`lief.PE.Export.entries` that is used to speed-up the symbol resolution"_doc) + + .def_prop_ro("iat_value", + &DelayImportEntry::iat_value, + R"delim( + Value of the current entry in the delay-loaded import address table. + See: :attr:`~DelayImportEntry.iat` + )delim"_doc) + + LIEF_COPYABLE(DelayImportEntry) + LIEF_DEFAULT_STR(DelayImportEntry); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyDosHeader.cpp b/vendor/lief/api/python/src/PE/objects/pyDosHeader.cpp new file mode 100644 index 0000000..1625219 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyDosHeader.cpp @@ -0,0 +1,108 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/DosHeader.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "DosHeader", + R"delim( + Class which represents the DosHeader, the **first** structure present at the beginning of a PE file. + + Most of the attributes of this structures are not relevant, except :attr:`~lief.PE.DosHeader.addressof_new_exeheader` + )delim"_doc) + .def_static("create", &DosHeader::create, nb::rv_policy::move) + + .def_prop_rw("magic", + nb::overload_cast<>(&DosHeader::magic, nb::const_), + nb::overload_cast(&DosHeader::magic)) + + .def_prop_rw("used_bytes_in_last_page", + nb::overload_cast<>(&DosHeader::used_bytes_in_last_page, nb::const_), + nb::overload_cast(&DosHeader::used_bytes_in_last_page)) + + .def_prop_rw("file_size_in_pages", + nb::overload_cast<>(&DosHeader::file_size_in_pages, nb::const_), + nb::overload_cast(&DosHeader::file_size_in_pages)) + + .def_prop_rw("numberof_relocation", + nb::overload_cast<>(&DosHeader::numberof_relocation, nb::const_), + nb::overload_cast(&DosHeader::numberof_relocation)) + + .def_prop_rw("header_size_in_paragraphs", + nb::overload_cast<>(&DosHeader::header_size_in_paragraphs, nb::const_), + nb::overload_cast(&DosHeader::header_size_in_paragraphs)) + + .def_prop_rw("minimum_extra_paragraphs", + nb::overload_cast<>(&DosHeader::minimum_extra_paragraphs, nb::const_), + nb::overload_cast(&DosHeader::minimum_extra_paragraphs)) + + .def_prop_rw("maximum_extra_paragraphs", + nb::overload_cast<>(&DosHeader::maximum_extra_paragraphs, nb::const_), + nb::overload_cast(&DosHeader::maximum_extra_paragraphs)) + + .def_prop_rw("initial_relative_ss", + nb::overload_cast<>(&DosHeader::initial_relative_ss, nb::const_), + nb::overload_cast(&DosHeader::initial_relative_ss)) + + .def_prop_rw("initial_sp", + nb::overload_cast<>(&DosHeader::initial_sp, nb::const_), + nb::overload_cast(&DosHeader::initial_sp)) + + .def_prop_rw("checksum", + nb::overload_cast<>(&DosHeader::checksum, nb::const_), + nb::overload_cast(&DosHeader::checksum)) + + .def_prop_rw("initial_ip", + nb::overload_cast<>(&DosHeader::initial_ip, nb::const_), + nb::overload_cast(&DosHeader::initial_ip)) + + .def_prop_rw("initial_relative_cs", + nb::overload_cast<>(&DosHeader::initial_relative_cs, nb::const_), + nb::overload_cast(&DosHeader::initial_relative_cs)) + + .def_prop_rw("addressof_relocation_table", + nb::overload_cast<>(&DosHeader::addressof_relocation_table, nb::const_), + nb::overload_cast(&DosHeader::addressof_relocation_table)) + + .def_prop_rw("overlay_number", + nb::overload_cast<>(&DosHeader::overlay_number, nb::const_), + nb::overload_cast(&DosHeader::overlay_number)) + + .def_prop_rw("oem_id", + nb::overload_cast<>(&DosHeader::oem_id, nb::const_), + nb::overload_cast(&DosHeader::oem_id)) + + .def_prop_rw("oem_info", + nb::overload_cast<>(&DosHeader::oem_info, nb::const_), + nb::overload_cast(&DosHeader::oem_info)) + + .def_prop_rw("addressof_new_exeheader", + nb::overload_cast<>(&DosHeader::addressof_new_exeheader, nb::const_), + nb::overload_cast(&DosHeader::addressof_new_exeheader)) + + LIEF_COPYABLE(DosHeader) + LIEF_DEFAULT_STR(DosHeader); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyExceptionInfo.cpp b/vendor/lief/api/python/src/PE/objects/pyExceptionInfo.cpp new file mode 100644 index 0000000..b8fb8e5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyExceptionInfo.cpp @@ -0,0 +1,64 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "LIEF/PE/ExceptionInfo.hpp" + +#include +#include +#include +#include + +namespace LIEF::PE { +class RuntimeFunctionX64; +class RuntimeFunctionAArch64; +} + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + + nb::class_ exception(m, "ExceptionInfo", + "This class is the base class for any exception or runtime function entry"_doc + ); + + nb::enum_(exception, "ARCH", + "Arch discriminator for the subclasses"_doc + ) + .value("UNKNOWN", ExceptionInfo::ARCH::UNKNOWN) + .value("ARM64", ExceptionInfo::ARCH::ARM64) + .value("X86_64", ExceptionInfo::ARCH::X86_64) + ; + + exception + .def_prop_ro("arch", &ExceptionInfo::arch, + "Target architecture of this exception"_doc + ) + .def_prop_ro("rva_start", &ExceptionInfo::rva_start, + "Function start address"_doc + ) + .def_prop_ro("offset", nb::overload_cast<>(&ExceptionInfo::offset, nb::const_), + "Offset in the binary where the raw exception information associated with " + "this entry is defined"_doc + ) + LIEF_CLONABLE(ExceptionInfo) + LIEF_DEFAULT_STR(ExceptionInfo); + + create(m); + create(m); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyExport.cpp b/vendor/lief/api/python/src/PE/objects/pyExport.cpp new file mode 100644 index 0000000..21a2f0b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyExport.cpp @@ -0,0 +1,134 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/Export.hpp" + +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ exp(m, "Export", + R"delim( + Class which represents a PE Export + )delim"_doc); + + init_ref_iterator(exp, "it_entries"); + + exp + .def(nb::init<>(), "Default constructor"_doc) + .def(nb::init&>(), + "name"_a, "entries"_a, + "Constructor from DLL name and its exports"_doc) + + .def_prop_rw("name", + [] (const Export& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&Export::name), + "The name of the library exported (e.g. ``KERNEL32.dll``)"_doc) + + .def_prop_rw("export_flags", + nb::overload_cast<>(&Export::export_flags, nb::const_), + nb::overload_cast(&Export::export_flags), + "According to the PE specifications this value is reserved and should be set to 0"_doc) + + .def_prop_rw("timestamp", + nb::overload_cast<>(&Export::timestamp, nb::const_), + nb::overload_cast(&Export::timestamp), + "The time and date that the export data was created"_doc) + + .def_prop_rw("major_version", + nb::overload_cast<>(&Export::major_version, nb::const_), + nb::overload_cast(&Export::major_version), + "The major version number (can be user-defined)"_doc) + + .def_prop_rw("minor_version", + nb::overload_cast<>(&Export::minor_version, nb::const_), + nb::overload_cast(&Export::minor_version), + "The minor version number (can be user-defined)"_doc) + + .def_prop_rw("ordinal_base", + nb::overload_cast<>(&Export::ordinal_base, nb::const_), + nb::overload_cast(&Export::ordinal_base), + "The starting number for the exports. Usually this value is set to 1"_doc) + + .def_prop_ro("entries", + nb::overload_cast<>(&Export::entries), + "Iterator over the " RST_CLASS_REF(lief.PE.ExportEntry) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("name_rva", &Export::name_rva, + "Address of the ASCII DLL's name (RVA)"_doc) + + .def_prop_ro("export_addr_table_rva", &Export::export_addr_table_rva, + "RVA of the export address table"_doc) + + .def_prop_ro("export_addr_table_cnt", &Export::export_addr_table_cnt, + "Number of entries in the export address table"_doc) + + .def_prop_ro("names_addr_table_rva", &Export::names_addr_table_rva, + "RVA to the list of exported names"_doc) + + .def_prop_ro("names_addr_table_cnt", &Export::names_addr_table_cnt, + "Number of exports by name"_doc) + + .def_prop_ro("ord_addr_table_rva", &Export::ord_addr_table_rva, + "RVA to the list of exported ordinals"_doc) + + .def("find_entry", nb::overload_cast(&Export::find_entry), + "Find the export with the given name"_doc, + "name"_a, nb::rv_policy::reference_internal) + + .def("find_entry", nb::overload_cast(&Export::find_entry), + "Find the export entry with the given ordinal number"_doc, + "ordinal"_a, nb::rv_policy::reference_internal) + + .def("find_entry_at", nb::overload_cast(&Export::find_entry_at), + "Find the export entry at the provided RVA"_doc, + "rva_addr"_a, nb::rv_policy::reference_internal) + + .def("add_entry", nb::overload_cast(&Export::add_entry), + "Add the given export and return the newly created and added entry"_doc, + "exp"_a, nb::rv_policy::reference_internal) + + .def("add_entry", nb::overload_cast(&Export::add_entry), + "Add the given export and return the newly created and added entry"_doc, + "name"_a, "addr"_a, nb::rv_policy::reference_internal) + + .def("remove_entry", nb::overload_cast(&Export::remove_entry), + "Remove the given export entry", "entry"_a) + + .def("remove_entry", nb::overload_cast(&Export::remove_entry), + "Remove the export entry with the given name", "name"_a) + + .def("remove_entry", nb::overload_cast(&Export::remove_entry), + "Remove the export entry with the given RVA", "rva"_a) + + LIEF_COPYABLE(Export) + LIEF_DEFAULT_STR(Export); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyExportEntry.cpp b/vendor/lief/api/python/src/PE/objects/pyExportEntry.cpp new file mode 100644 index 0000000..5ce7314 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyExportEntry.cpp @@ -0,0 +1,86 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/ExportEntry.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ export_entry(m, "ExportEntry", + R"delim( + Class which represents a PE Export entry (cf. :class:`lief.PE.Export`) + )delim"_doc); + + nb::class_(export_entry, "forward_information_t") + .def_rw("library", &ExportEntry::forward_information_t::library) + .def_rw("function", &ExportEntry::forward_information_t::function) + LIEF_DEFAULT_STR(ExportEntry::forward_information_t); + + export_entry + .def(nb::init<>(), "Default constructor"_doc) + .def(nb::init(), + "name"_a, "addr"_a, + "Constructor with export name and address"_doc) + + .def_prop_rw("name", + [] (const ExportEntry& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&ExportEntry::name)) + + .def_prop_rw("ordinal", + nb::overload_cast<>(&ExportEntry::ordinal, nb::const_), + nb::overload_cast(&ExportEntry::ordinal)) + + .def_prop_rw("address", + nb::overload_cast<>(&ExportEntry::address, nb::const_), + nb::overload_cast(&ExportEntry::address)) + + .def_prop_rw("is_extern", + nb::overload_cast<>(&ExportEntry::is_extern, nb::const_), + nb::overload_cast(&ExportEntry::is_extern)) + + .def_prop_ro("is_forwarded", + &ExportEntry::is_forwarded) + + .def_prop_ro("forward_information", + &ExportEntry::forward_information) + + .def_prop_ro("function_rva", + &ExportEntry::function_rva) + + .def_prop_ro("demangled_name", + &ExportEntry::demangled_name, + R"doc( + Demangled representation of the symbol or an empty string if it can't + be demangled. + )doc"_doc + ) + + .def("set_forward_info", &ExportEntry::set_forward_info, + "lib"_a, "function"_a) + + LIEF_DEFAULT_STR(ExportEntry); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyFactory.cpp b/vendor/lief/api/python/src/PE/objects/pyFactory.cpp new file mode 100644 index 0000000..f0da482 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyFactory.cpp @@ -0,0 +1,54 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "pyErr.hpp" +#include "LIEF/PE/Factory.hpp" +#include "LIEF/PE/Binary.hpp" +#include "LIEF/PE/LoadConfigurations.hpp" +#include "LIEF/PE/TLS.hpp" +#include "LIEF/PE/RichHeader.hpp" +#include "LIEF/PE/ResourceNode.hpp" +#include "LIEF/PE/Export.hpp" +#include "LIEF/PE/Debug.hpp" +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/PE/RelocationEntry.hpp" +#include "LIEF/PE/Section.hpp" + +#include +#include +#include "nanobind/utils.hpp" +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ factory(m, "Factory"); + + factory + .def_static("create", &Factory::create) + .def("add_section", &Factory::add_section, + nb::rv_policy::reference) + .def("get", &Factory::get) + ; + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyHeader.cpp b/vendor/lief/api/python/src/PE/objects/pyHeader.cpp new file mode 100644 index 0000000..d061456 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyHeader.cpp @@ -0,0 +1,173 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/PE/Header.hpp" + +#include +#include +#include +#include +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create
(nb::module_& m) { + nb::class_ hdr(m, "Header", + R"delim( + Class that represents the PE header (which follows the :class:`lief.PE.DosHeader`) + )delim"_doc); + + enum_(hdr, "MACHINE_TYPES") + .value(PY_ENUM(Header::MACHINE_TYPES::UNKNOWN)) + .value(PY_ENUM(Header::MACHINE_TYPES::ALPHA)) + .value(PY_ENUM(Header::MACHINE_TYPES::ALPHA64)) + .value(PY_ENUM(Header::MACHINE_TYPES::AM33)) + .value(PY_ENUM(Header::MACHINE_TYPES::AMD64)) + .value(PY_ENUM(Header::MACHINE_TYPES::ARM)) + .value(PY_ENUM(Header::MACHINE_TYPES::ARMNT)) + .value(PY_ENUM(Header::MACHINE_TYPES::ARM64)) + .value(PY_ENUM(Header::MACHINE_TYPES::EBC)) + .value(PY_ENUM(Header::MACHINE_TYPES::I386)) + .value(PY_ENUM(Header::MACHINE_TYPES::IA64)) + .value(PY_ENUM(Header::MACHINE_TYPES::LOONGARCH32)) + .value(PY_ENUM(Header::MACHINE_TYPES::LOONGARCH64)) + .value(PY_ENUM(Header::MACHINE_TYPES::M32R)) + .value(PY_ENUM(Header::MACHINE_TYPES::MIPS16)) + .value(PY_ENUM(Header::MACHINE_TYPES::MIPSFPU)) + .value(PY_ENUM(Header::MACHINE_TYPES::MIPSFPU16)) + .value(PY_ENUM(Header::MACHINE_TYPES::POWERPC)) + .value(PY_ENUM(Header::MACHINE_TYPES::POWERPCFP)) + .value(PY_ENUM(Header::MACHINE_TYPES::POWERPCBE)) + .value(PY_ENUM(Header::MACHINE_TYPES::R4000)) + .value(PY_ENUM(Header::MACHINE_TYPES::SH3)) + .value(PY_ENUM(Header::MACHINE_TYPES::SH3DSP)) + .value(PY_ENUM(Header::MACHINE_TYPES::SH4)) + .value(PY_ENUM(Header::MACHINE_TYPES::SH5)) + .value(PY_ENUM(Header::MACHINE_TYPES::THUMB)) + .value(PY_ENUM(Header::MACHINE_TYPES::WCEMIPSV2)) + .value(PY_ENUM(Header::MACHINE_TYPES::ARM64EC)) + .value(PY_ENUM(Header::MACHINE_TYPES::ARM64X)) + .value(PY_ENUM(Header::MACHINE_TYPES::CHPE_X86)) + ; + + enum_(hdr, "CHARACTERISTICS", nb::is_flag()) + .value(PY_ENUM(Header::CHARACTERISTICS::RELOCS_STRIPPED)) + .value(PY_ENUM(Header::CHARACTERISTICS::EXECUTABLE_IMAGE)) + .value(PY_ENUM(Header::CHARACTERISTICS::LINE_NUMS_STRIPPED)) + .value(PY_ENUM(Header::CHARACTERISTICS::LOCAL_SYMS_STRIPPED)) + .value(PY_ENUM(Header::CHARACTERISTICS::AGGRESSIVE_WS_TRIM)) + .value(PY_ENUM(Header::CHARACTERISTICS::LARGE_ADDRESS_AWARE)) + .value(PY_ENUM(Header::CHARACTERISTICS::BYTES_REVERSED_LO)) + .value(PY_ENUM(Header::CHARACTERISTICS::NEED_32BIT_MACHINE)) + .value(PY_ENUM(Header::CHARACTERISTICS::DEBUG_STRIPPED)) + .value(PY_ENUM(Header::CHARACTERISTICS::REMOVABLE_RUN_FROM_SWAP)) + .value(PY_ENUM(Header::CHARACTERISTICS::NET_RUN_FROM_SWAP)) + .value(PY_ENUM(Header::CHARACTERISTICS::SYSTEM)) + .value(PY_ENUM(Header::CHARACTERISTICS::DLL)) + .value(PY_ENUM(Header::CHARACTERISTICS::UP_SYSTEM_ONLY)) + .value(PY_ENUM(Header::CHARACTERISTICS::BYTES_REVERSED_HI)); + + hdr + .def_static("create", &Header::create, "type"_a) + + .def_prop_rw("signature", + nb::overload_cast<>(&Header::signature, nb::const_), + nb::overload_cast(&Header::signature), + R"delim( + Signature (or magic byte) of the header. It must be: ``PE\0\0`` + )delim"_doc) + + .def_prop_rw("machine", + nb::overload_cast<>(&Header::machine, nb::const_), + nb::overload_cast(&Header::machine), + "The target machine architecture (" RST_CLASS_REF(lief.PE.Header.MACHINE_TYPES) ")"_doc) + + .def_prop_rw("numberof_sections", + nb::overload_cast<>(&Header::numberof_sections, nb::const_), + nb::overload_cast(&Header::numberof_sections), + "Number of sections in the binary"_doc) + + .def_prop_rw("time_date_stamps", + nb::overload_cast<>(&Header::time_date_stamp, nb::const_), + nb::overload_cast(&Header::time_date_stamp), + "The low 32 bits of the number of seconds since 00:00 January 1, 1970 that indicates when the file was created."_doc) + + .def_prop_rw("pointerto_symbol_table", + nb::overload_cast<>(&Header::pointerto_symbol_table, nb::const_), + nb::overload_cast(&Header::pointerto_symbol_table), + R"delim( + The file offset of the COFF symbol table, or zero if no COFF symbol table is present. + + This value should be zero for an image because COFF debugging information is deprecated. + )delim"_doc) + + .def_prop_rw("numberof_symbols", + nb::overload_cast<>(&Header::numberof_symbols, nb::const_), + nb::overload_cast(&Header::numberof_symbols), + R"delim( + The number of entries in the symbol table. This data can be used to locate the string table + which immediately follows the symbol table. + + This value should be zero for an image because COFF debugging information is deprecated. + )delim"_doc) + + .def_prop_rw("sizeof_optional_header", + nb::overload_cast<>(&Header::sizeof_optional_header, nb::const_), + nb::overload_cast(&Header::sizeof_optional_header), + R"delim( + Size of the :class:`~lief.PE.OptionalHeader` **AND** the data directories which follows this header. + + This value is equivalent to: ``sizeof(pe_optional_header) + NB_DATA_DIR * sizeof(data_directory)`` + + This size **should** be either: + + * 0xE0 (224) for a PE32 (32 bits) + * 0xF0 (240) for a PE32+ (64 bits) + )delim"_doc) + + .def_prop_rw("characteristics", + nb::overload_cast<>(&Header::characteristics, nb::const_), + nb::overload_cast(&Header::characteristics), + "The " RST_CLASS_REF(lief.PE.Header.CHARACTERISTICS) " that indicate the attributes of the file."_doc) + + .def("has_characteristic", + &Header::has_characteristic, + "``True`` if the header has the given " RST_CLASS_REF(lief.PE.Header.CHARACTERISTICS) ""_doc, + "characteristic"_a) + + .def("add_characteristic", + &Header::add_characteristic, + "Add the given " RST_CLASS_REF(lief.PE.Header.CHARACTERISTICS) " to the header"_doc, + "characteristic"_a) + + .def("remove_characteristic", + &Header::remove_characteristic, + "Remove the given " RST_CLASS_REF(lief.PE.Header.CHARACTERISTICS) " from the header"_doc, + "characteristic"_a) + + .def_prop_ro("characteristics_list", + &Header::characteristics_list, + "Return the " RST_CLASS_REF(lief.PE.Header.CHARACTERISTICS) " as a ``list``"_doc) + + LIEF_COPYABLE(Header) + LIEF_DEFAULT_STR(Header); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyImport.cpp b/vendor/lief/api/python/src/PE/objects/pyImport.cpp new file mode 100644 index 0000000..2afa816 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyImport.cpp @@ -0,0 +1,166 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pyErr.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/Import.hpp" +#include "LIEF/PE/DataDirectory.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ imp(m, "Import", + R"delim( + Class that represents a PE import + )delim"_doc); + + init_ref_iterator(imp, "it_entries"); + + imp + .def(nb::init<>(), + "Default constructor"_doc) + + .def(nb::init(), + "Constructor from a library name"_doc, + "library_name"_a) + + .def_prop_ro("forwarder_chain", + &Import::forwarder_chain, + "The index of the first forwarder reference"_doc) + + .def_prop_ro("timedatestamp", + &Import::timedatestamp, + R"delim( + The stamp that is set to zero until the image is bound. + + After the image is bound, this field is set to the time/data stamp of the DLL + )delim"_doc) + + .def_prop_ro("entries", + nb::overload_cast<>(&Import::entries), + "Iterator over the " RST_CLASS_REF(lief.PE.ImportEntry) " (functions)"_doc, + nb::keep_alive<1, 0>()) + + .def_prop_rw("name", + [] (const Import& obj) { + return safe_string(obj.name()); + }, + nb::overload_cast(&Import::name), + "Library name (e.g. ``kernel32.dll``)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("directory", + nb::overload_cast<>(&Import::directory), + R"delim( + Return the :class:`~lief.PE.DataDirectory` associated with this import. + + It should be the one at index :attr:`lief.PE.DataDirectory.TYPES.IMPORT_TABLE`. + It can return None if the Import directory can't be resolved. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("iat_directory", + nb::overload_cast<>(&Import::iat_directory), + R"delim( + Return the :class:`~lief.PE.DataDirectory` associated with the ``IAT`` table. + + It should be the one at index :attr:`lief.PE.DataDirectory.TYPES.IAT`. It can + return None if the IAT directory can't be resolved. + )delim"_doc, + nb::rv_policy::reference_internal) + + .def_prop_rw("import_address_table_rva", + nb::overload_cast<>(&Import::import_address_table_rva, nb::const_), + nb::overload_cast(&Import::import_address_table_rva), + R"delim( + The RVA of the import address table (``IAT``). The content of this + table is **identical** to the content of the Import Lookup Table (``ILT``) + until the image is bound. + + .. warning:: + + This address could change when re-building the binary + )delim"_doc) + + .def_prop_rw("import_lookup_table_rva", + nb::overload_cast<>(&Import::import_lookup_table_rva, nb::const_), + nb::overload_cast(&Import::import_lookup_table_rva), + R"delim( + The RVA of the import lookup table. This table + contains the :attr:`~lief.PE.ImportEntry.name` or the :attr:`~lief.PE.ImportEntry.ordinal` + for all the imports. + )delim"_doc) + + .def("get_function_rva_from_iat", + [] (const Import& self, const std::string& name) { + return error_or(&Import::get_function_rva_from_iat, self, name); + }, + "Return the relative virtual address of the given function within the *Import Address Table*"_doc, + "function_name"_a) + + .def("add_entry", + nb::overload_cast(&Import::add_entry), + "Add an " RST_CLASS_REF(lief.PE.ImportEntry) " (function) to the current import"_doc, + "entry"_a, + nb::rv_policy::reference_internal) + + .def("add_entry", + nb::overload_cast(&Import::add_entry), + "Add an " RST_CLASS_REF(lief.PE.ImportEntry) " (function) to the current import"_doc, + "function_name"_a, + nb::rv_policy::reference_internal) + + .def("get_entry", + nb::overload_cast(&Import::get_entry), + "Return the " RST_CLASS_REF(lief.PE.ImportEntry) " with the given name or None if not found"_doc, + "function_name"_a, + nb::rv_policy::reference_internal) + + .def_prop_ro("name_rva", &Import::name_rva, + "The original name rva"_doc + ) + + .def("remove_entry", + nb::overload_cast(&Import::remove_entry), + R"doc( + Remove the import entry with the given name. + + Return True if the deletion succeeds, False otherwise + )doc"_doc, "name"_a + ) + + .def("remove_entry", + nb::overload_cast(&Import::remove_entry), + R"doc( + Remove the import entry with the given ordinal number + + Return True if the deletion succeeds, False otherwise + )doc"_doc, "ord"_a + ) + + LIEF_DEFAULT_STR(Import); + +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyImportEntry.cpp b/vendor/lief/api/python/src/PE/objects/pyImportEntry.cpp new file mode 100644 index 0000000..454ff5d --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyImportEntry.cpp @@ -0,0 +1,100 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +#include "LIEF/PE/ImportEntry.hpp" + +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ImportEntry", + R"delim( + Class that represents an entry (i.e. an import) in the import table (:class:`~lief.PE.Import`). + + It extends the :class:`lief.Symbol` generic class that provides the :attr:`lief.Symbol.name` + and :attr:`lief.Symbol.value` + )delim"_doc) + .def(nb::init<>()) + + .def(nb::init(), + "Constructor from a :attr:`~ImportEntry.name`"_doc, + "import_name"_a) + + .def(nb::init(), + "data"_a, "type"_a) + + .def_prop_rw("name", + [] (const ImportEntry& obj) { + return LIEF::py::safe_string(obj.name()); + }, + nb::overload_cast(&ImportEntry::name), + "Import name if not ordinal"_doc) + + .def_prop_rw("data", + nb::overload_cast<>(&ImportEntry::data, nb::const_), + nb::overload_cast(&ImportEntry::data), + "Raw value"_doc) + + .def_prop_ro("demangled_name", + &ImportEntry::demangled_name, + R"doc( + Demangled representation of the symbol or an empty string if it can't + be demangled. + )doc"_doc + ) + + .def_prop_ro("is_ordinal", + &ImportEntry::is_ordinal, + "``True`` if it is an import by ordinal"_doc) + + .def_prop_ro("ordinal", + &ImportEntry::ordinal, + "Ordinal value (if any). See: :attr:`~lief.PE.ImportEntry.is_ordinal`"_doc) + + .def_prop_ro("hint", + &ImportEntry::hint, + "Index into the :attr:`lief.PE.Export.entries` that is used to speed-up the symbol resolution"_doc) + + .def_prop_rw("iat_value", + nb::overload_cast<>(&ImportEntry::iat_value, nb::const_), + nb::overload_cast(&ImportEntry::iat_value), + "Value of the current entry in the Import Address Table. It should match the lookup table value."_doc) + + .def_prop_rw("ilt_value", + nb::overload_cast<>(&ImportEntry::ilt_value, nb::const_), + nb::overload_cast(&ImportEntry::ilt_value), + R"doc( + Original value in the import lookup table. + + This value should match the :attr:`~ImportEntry.iat_value` + )doc"_doc + ) + + .def_prop_ro("iat_address", + nb::overload_cast<>(&ImportEntry::iat_address, nb::const_), + "**Original** address of the entry in the Import Address Table"_doc) + + LIEF_COPYABLE(ImportEntry) + LIEF_DEFAULT_STR(ImportEntry); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyLang.cpp b/vendor/lief/api/python/src/PE/objects/pyLang.cpp new file mode 100644 index 0000000..fec2541 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyLang.cpp @@ -0,0 +1,132 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/resources/langs.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + enum_(m, "RESOURCE_LANGS") + .value("NEUTRAL", RESOURCE_LANGS::NEUTRAL) + .value("INVARIANT", RESOURCE_LANGS::INVARIANT) + .value("AFRIKAANS", RESOURCE_LANGS::AFRIKAANS) + .value("ALBANIAN", RESOURCE_LANGS::ALBANIAN) + .value("ARABIC", RESOURCE_LANGS::ARABIC) + .value("ARMENIAN", RESOURCE_LANGS::ARMENIAN) + .value("ASSAMESE", RESOURCE_LANGS::ASSAMESE) + .value("AZERI", RESOURCE_LANGS::AZERI) + .value("BASQUE", RESOURCE_LANGS::BASQUE) + .value("BELARUSIAN", RESOURCE_LANGS::BELARUSIAN) + .value("BANGLA", RESOURCE_LANGS::BANGLA) + .value("BULGARIAN", RESOURCE_LANGS::BULGARIAN) + .value("CATALAN", RESOURCE_LANGS::CATALAN) + .value("CHINESE", RESOURCE_LANGS::CHINESE) + .value("CROATIAN", RESOURCE_LANGS::CROATIAN) + .value("BOSNIAN", RESOURCE_LANGS::BOSNIAN) + .value("CZECH", RESOURCE_LANGS::CZECH) + .value("DANISH", RESOURCE_LANGS::DANISH) + .value("DIVEHI", RESOURCE_LANGS::DIVEHI) + .value("DUTCH", RESOURCE_LANGS::DUTCH) + .value("ENGLISH", RESOURCE_LANGS::ENGLISH) + .value("ESTONIAN", RESOURCE_LANGS::ESTONIAN) + .value("FAEROESE", RESOURCE_LANGS::FAEROESE) + .value("FARSI", RESOURCE_LANGS::FARSI) + .value("FINNISH", RESOURCE_LANGS::FINNISH) + .value("FRENCH", RESOURCE_LANGS::FRENCH) + .value("GALICIAN", RESOURCE_LANGS::GALICIAN) + .value("GEORGIAN", RESOURCE_LANGS::GEORGIAN) + .value("GERMAN", RESOURCE_LANGS::GERMAN) + .value("GREEK", RESOURCE_LANGS::GREEK) + .value("GUJARATI", RESOURCE_LANGS::GUJARATI) + .value("HEBREW", RESOURCE_LANGS::HEBREW) + .value("HINDI", RESOURCE_LANGS::HINDI) + .value("HUNGARIAN", RESOURCE_LANGS::HUNGARIAN) + .value("ICELANDIC", RESOURCE_LANGS::ICELANDIC) + .value("INDONESIAN", RESOURCE_LANGS::INDONESIAN) + .value("ITALIAN", RESOURCE_LANGS::ITALIAN) + .value("JAPANESE", RESOURCE_LANGS::JAPANESE) + .value("KANNADA", RESOURCE_LANGS::KANNADA) + .value("KASHMIRI", RESOURCE_LANGS::KASHMIRI) + .value("KAZAK", RESOURCE_LANGS::KAZAK) + .value("KONKANI", RESOURCE_LANGS::KONKANI) + .value("KOREAN", RESOURCE_LANGS::KOREAN) + .value("KYRGYZ", RESOURCE_LANGS::KYRGYZ) + .value("LATVIAN", RESOURCE_LANGS::LATVIAN) + .value("LITHUANIAN", RESOURCE_LANGS::LITHUANIAN) + .value("MACEDONIAN", RESOURCE_LANGS::MACEDONIAN) + .value("MALAY", RESOURCE_LANGS::MALAY) + .value("MALAYALAM", RESOURCE_LANGS::MALAYALAM) + .value("MANIPURI", RESOURCE_LANGS::MANIPURI) + .value("MARATHI", RESOURCE_LANGS::MARATHI) + .value("MONGOLIAN", RESOURCE_LANGS::MONGOLIAN) + .value("NEPALI", RESOURCE_LANGS::NEPALI) + .value("NORWEGIAN", RESOURCE_LANGS::NORWEGIAN) + .value("ORIYA", RESOURCE_LANGS::ORIYA) + .value("POLISH", RESOURCE_LANGS::POLISH) + .value("PORTUGUESE", RESOURCE_LANGS::PORTUGUESE) + .value("PUNJABI", RESOURCE_LANGS::PUNJABI) + .value("ROMANIAN", RESOURCE_LANGS::ROMANIAN) + .value("RUSSIAN", RESOURCE_LANGS::RUSSIAN) + .value("SANSKRIT", RESOURCE_LANGS::SANSKRIT) + .value("SERBIAN", RESOURCE_LANGS::SERBIAN) + .value("SINDHI", RESOURCE_LANGS::SINDHI) + .value("SLOVAK", RESOURCE_LANGS::SLOVAK) + .value("SLOVENIAN", RESOURCE_LANGS::SLOVENIAN) + .value("SPANISH", RESOURCE_LANGS::SPANISH) + .value("SWAHILI", RESOURCE_LANGS::SWAHILI) + .value("SWEDISH", RESOURCE_LANGS::SWEDISH) + .value("SYRIAC", RESOURCE_LANGS::SYRIAC) + .value("TAMIL", RESOURCE_LANGS::TAMIL) + .value("TATAR", RESOURCE_LANGS::TATAR) + .value("TELUGU", RESOURCE_LANGS::TELUGU) + .value("THAI", RESOURCE_LANGS::THAI) + .value("TURKISH", RESOURCE_LANGS::TURKISH) + .value("UKRAINIAN", RESOURCE_LANGS::UKRAINIAN) + .value("URDU", RESOURCE_LANGS::URDU) + .value("UZBEK", RESOURCE_LANGS::UZBEK) + .value("VIETNAMESE", RESOURCE_LANGS::VIETNAMESE) + .value("GAELIC", RESOURCE_LANGS::GAELIC) + .value("MALTESE", RESOURCE_LANGS::MALTESE) + .value("MAORI", RESOURCE_LANGS::MAORI) + .value("RHAETO_ROMANCE", RESOURCE_LANGS::RHAETO_ROMANCE) + .value("SAMI", RESOURCE_LANGS::SAMI) + .value("SORBIAN", RESOURCE_LANGS::SORBIAN) + .value("SUTU", RESOURCE_LANGS::SUTU) + .value("TSONGA", RESOURCE_LANGS::TSONGA) + .value("TSWANA", RESOURCE_LANGS::TSWANA) + .value("VENDA", RESOURCE_LANGS::VENDA) + .value("XHOSA", RESOURCE_LANGS::XHOSA) + .value("ZULU", RESOURCE_LANGS::ZULU) + .value("ESPERANTO", RESOURCE_LANGS::ESPERANTO) + .value("WALON", RESOURCE_LANGS::WALON) + .value("CORNISH", RESOURCE_LANGS::CORNISH) + .value("WELSH", RESOURCE_LANGS::WELSH) + .value("BRETON", RESOURCE_LANGS::BRETON) + .value("INUKTITUT", RESOURCE_LANGS::INUKTITUT) + .value("IRISH", RESOURCE_LANGS::IRISH) + .value("LOWER_SORBIAN", RESOURCE_LANGS::LOWER_SORBIAN) + .value("PULAR", RESOURCE_LANGS::PULAR) + .value("QUECHUA", RESOURCE_LANGS::QUECHUA) + .value("TAMAZIGHT", RESOURCE_LANGS::TAMAZIGHT) + .value("TIGRINYA", RESOURCE_LANGS::TIGRINYA) + .value("VALENCIAN", RESOURCE_LANGS::VALENCIAN); + +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyOptionalHeader.cpp b/vendor/lief/api/python/src/PE/objects/pyOptionalHeader.cpp new file mode 100644 index 0000000..a61acbf --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyOptionalHeader.cpp @@ -0,0 +1,320 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/PE/OptionalHeader.hpp" + +#include +#include +#include +#include +#include + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ opt_header(m, "OptionalHeader", + R"delim( + Class which represents the PE OptionalHeader structure. + )delim"_doc); + + enum_(opt_header, "SUBSYSTEM") + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::UNKNOWN)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::NATIVE)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::WINDOWS_GUI)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::WINDOWS_CUI)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::OS2_CUI)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::POSIX_CUI)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::NATIVE_WINDOWS)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::WINDOWS_CE_GUI)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::EFI_APPLICATION)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::EFI_BOOT_SERVICE_DRIVER)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::EFI_RUNTIME_DRIVER)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::EFI_ROM)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::XBOX)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::WINDOWS_BOOT_APPLICATION)) + .value(PY_ENUM(OptionalHeader::SUBSYSTEM::XBOX_CODE_CATALOG)); + + enum_(opt_header, "DLL_CHARACTERISTICS", nb::is_flag(), nb::is_arithmetic()) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::HIGH_ENTROPY_VA)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::DYNAMIC_BASE)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::FORCE_INTEGRITY)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::NX_COMPAT)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::NO_ISOLATION)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::NO_SEH)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::NO_BIND)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::APPCONTAINER)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::WDM_DRIVER)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::GUARD_CF)) + .value(PY_ENUM(OptionalHeader::DLL_CHARACTERISTICS::TERMINAL_SERVER_AWARE)); + + opt_header + .def_static("create", OptionalHeader::create, "type"_a) + + .def_prop_rw("magic", + nb::overload_cast<>(&OptionalHeader::magic, nb::const_), + nb::overload_cast(&OptionalHeader::magic), + "Magic value (" RST_CLASS_REF(lief.PE.PE_TYPE) ") that identifies a ``PE32`` from a ``PE64``"_doc) + + .def_prop_rw("major_linker_version", + nb::overload_cast<>(&OptionalHeader::major_linker_version, nb::const_), + nb::overload_cast(&OptionalHeader::major_linker_version), + "The linker major version number"_doc) + + .def_prop_rw("minor_linker_version", + nb::overload_cast<>(&OptionalHeader::minor_linker_version, nb::const_), + nb::overload_cast(&OptionalHeader::minor_linker_version), + "The linker minor version number"_doc) + + .def_prop_rw("sizeof_code", + nb::overload_cast<>(&OptionalHeader::sizeof_code, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_code), + R"delim( + The size of the code ``.text`` section or the sum of + all the sections that contain code (ie. :class:`~lief.PE.Section` with + the flag :attr:`~lief.PE.Section.CHARACTERISTICS.CNT_CODE`) + )delim"_doc) + + .def_prop_rw("sizeof_initialized_data", + nb::overload_cast<>(&OptionalHeader::sizeof_initialized_data, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_initialized_data), + R"delim( + The size of the initialized data which are usually located in the ``.data`` section. + If the initialized data are split across multiple sections, it is the sum of the sections. + + The sections associated with the initialized data are usually identified with the + flag :attr:`~lief.PE.Section.CHARACTERISTICS.CNT_INITIALIZED_DATA` + )delim"_doc) + + .def_prop_rw("sizeof_uninitialized_data", + nb::overload_cast<>(&OptionalHeader::sizeof_uninitialized_data, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_uninitialized_data), + R"delim( + The size of the uninitialized data which are usually located in the ``.bss`` section. + If the uninitialized data are split across multiple sections, it is the sum of the sections. + + The sections associated with the uninitialized data are usually identified with the + flag :attr:`~lief.PE.Section.CHARACTERISTICS.CNT_UNINITIALIZED_DATA` + )delim"_doc) + + .def_prop_rw("addressof_entrypoint", + nb::overload_cast<>(&OptionalHeader::addressof_entrypoint, nb::const_), + nb::overload_cast(&OptionalHeader::addressof_entrypoint), + R"delim( + The address of the entry point relative to the image base when the executable file is + loaded into memory. For program images, this is the starting address. For device + drivers, this is the address of the initialization function. + + An entry point is optional for DLLs. When no entry point is present, this field must be zero. + )delim"_doc) + + .def_prop_rw("baseof_code", + nb::overload_cast<>(&OptionalHeader::baseof_code, nb::const_), + nb::overload_cast(&OptionalHeader::baseof_code), + "Address relative to the imagebase where the binary's code starts"_doc) + + .def_prop_rw("baseof_data", + nb::overload_cast<>(&OptionalHeader::baseof_data, nb::const_), + nb::overload_cast(&OptionalHeader::baseof_data), + R"delim( + Address relative to the imagebase where the binary's data starts. + + .. warning:: + + This value is not present for ``PE64`` files + + )delim"_doc) + + .def_prop_rw("imagebase", + nb::overload_cast<>(&OptionalHeader::imagebase, nb::const_), + nb::overload_cast(&OptionalHeader::imagebase), + "The preferred base address when mapping the binary in memory"_doc) + + .def_prop_rw("section_alignment", + nb::overload_cast<>(&OptionalHeader::section_alignment, nb::const_), + nb::overload_cast(&OptionalHeader::section_alignment), + R"delim( + The alignment (in bytes) of sections when they are loaded into memory. + It must be greater than or equal to :attr:`~lief.PE.OptionalHeader.file_alignment` and + the default is the page size for the architecture. + )delim"_doc) + + .def_prop_rw("file_alignment", + nb::overload_cast<>(&OptionalHeader::file_alignment, nb::const_), + nb::overload_cast(&OptionalHeader::file_alignment), + R"delim( + The alignment factor (in bytes) that is used to align the raw data of + sections in the image file. + The value should be a **power of 2** between 512 and 64K, inclusive. + The default value is 512. + If the :attr:`~lief.PE.OptionalHeader.section_alignment` is less than the architecture's page size, + then :attr:`~lief.PE.OptionalHeader.file_alignment` must match :attr:`~lief.PE.OptionalHeader.section_alignment`. + )delim"_doc) + + + .def_prop_rw("major_operating_system_version", + nb::overload_cast<>(&OptionalHeader::major_operating_system_version, nb::const_), + nb::overload_cast(&OptionalHeader::major_operating_system_version), + "The major version number of the required operating system."_doc) + + .def_prop_rw("minor_operating_system_version", + nb::overload_cast<>(&OptionalHeader::minor_operating_system_version, nb::const_), + nb::overload_cast(&OptionalHeader::minor_operating_system_version), + "The minor version number of the required operating system."_doc) + + .def_prop_rw("major_image_version", + nb::overload_cast<>(&OptionalHeader::major_image_version, nb::const_), + nb::overload_cast(&OptionalHeader::major_image_version), + "The major version number of the image."_doc) + + .def_prop_rw("minor_image_version", + nb::overload_cast<>(&OptionalHeader::minor_image_version, nb::const_), + nb::overload_cast(&OptionalHeader::minor_image_version), + "The minor version number of the image."_doc) + + .def_prop_rw("major_subsystem_version", + nb::overload_cast<>(&OptionalHeader::major_subsystem_version, nb::const_), + nb::overload_cast(&OptionalHeader::major_subsystem_version), + "The major version number of the subsystem."_doc) + + .def_prop_rw("minor_subsystem_version", + nb::overload_cast<>(&OptionalHeader::minor_subsystem_version, nb::const_), + nb::overload_cast(&OptionalHeader::minor_subsystem_version), + "The minor version number of the subsystem"_doc) + + .def_prop_rw("win32_version_value", + nb::overload_cast<>(&OptionalHeader::win32_version_value, nb::const_), + nb::overload_cast(&OptionalHeader::win32_version_value), + "Reserved, must be zero."_doc) + + .def_prop_rw("sizeof_image", + nb::overload_cast<>(&OptionalHeader::sizeof_image, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_image), + R"delim( + The size (in bytes) of the image, including all headers, as the image is loaded in memory. + It must be a multiple of :attr:`~lief.PE.OptionalHeader.section_alignment` and should match :attr:`~lief.PE.Binary.virtual_size`. + )delim"_doc) + + .def_prop_rw("sizeof_headers", + nb::overload_cast<>(&OptionalHeader::sizeof_headers, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_headers), + R"delim( + The combined size of an MS-DOS stub, PE header, and section headers rounded up + to a multiple of :attr:`~lief.PE.OptionalHeader.file_alignment`. + )delim"_doc) + + .def_prop_rw("checksum", + nb::overload_cast<>(&OptionalHeader::checksum, nb::const_), + nb::overload_cast(&OptionalHeader::checksum), + R"delim( + The image file checksum. The algorithm for computing the checksum is incorporated into ``IMAGHELP.DLL``. + The following are checked for validation at load time all **drivers**, any **DLL loaded at boot** + time, and any **DLL** that is loaded into a **critical** Windows process. + )delim"_doc) + + + .def_prop_rw("subsystem", + nb::overload_cast<>(&OptionalHeader::subsystem, nb::const_), + nb::overload_cast(&OptionalHeader::subsystem), + R"delim( + Target subsystem (:class:`~lief.PE.OptionalHeader.SUBSYSTEM`) like Driver, XBox, Windows GUI, .. + )delim"_doc) + + .def_prop_rw("dll_characteristics", + nb::overload_cast<>(&OptionalHeader::dll_characteristics, nb::const_), + nb::overload_cast(&OptionalHeader::dll_characteristics), + R"delim( + Some characteristics (:class:`~lief.PE.OptionalHeader.DLL_CHARACTERISTICS`) of the underlying binary like the support of the PIE. + + The prefix ``dll`` comes from the official PE specifications but these characteristics + are also used for **executables** + )delim"_doc) + + .def("add", + nb::overload_cast(&OptionalHeader::add), + "Add the given " RST_CLASS_REF(lief.PE.OptionalHeader.DLL_CHARACTERISTICS) ""_doc, + "characteristic"_a) + + .def("remove", + nb::overload_cast(&OptionalHeader::remove), + "Remove the given " RST_CLASS_REF(lief.PE.OptionalHeader.DLL_CHARACTERISTICS) ""_doc, + "characteristic"_a) + + .def_prop_ro("dll_characteristics_lists", + &OptionalHeader::dll_characteristics_list, + ":attr:`~lief.PE.OptionalHeader.dll_characteristics` as a list of " RST_CLASS_REF(lief.PE.OptionalHeader.DLL_CHARACTERISTICS) ""_doc) + + .def("has", + nb::overload_cast(&OptionalHeader::has, nb::const_), + "``True`` if the given " RST_CLASS_REF(lief.PE.OptionalHeader.DLL_CHARACTERISTICS) " is in the " + ":attr:`~lief.PE.OptionalHeader.dll_characteristics`"_doc, + "characteristics"_a) + + .def_prop_rw("sizeof_stack_reserve", + nb::overload_cast<>(&OptionalHeader::sizeof_stack_reserve, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_stack_reserve), + R"delim( + The size of the stack to reserve. + + Only :attr:`~lief.PE.OptionalHeader.sizeof_stack_commit` is committed, the rest is made + available one page at a time until the reserve size is reached. + )delim"_doc) + + .def_prop_rw("sizeof_stack_commit", + nb::overload_cast<>(&OptionalHeader::sizeof_stack_commit, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_stack_commit), + "The size of the stack to commit."_doc) + + .def_prop_rw("sizeof_heap_reserve", + nb::overload_cast<>(&OptionalHeader::sizeof_heap_reserve, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_heap_reserve), + R"delim( + The size of the local heap space to reserve. + + Only :attr:`~lief.PE.OptionalHeader.sizeof_heap_commit` is available one page at a time until + the reserve size is reached. + )delim"_doc) + + .def_prop_rw("sizeof_heap_commit", + nb::overload_cast<>(&OptionalHeader::sizeof_heap_commit, nb::const_), + nb::overload_cast(&OptionalHeader::sizeof_heap_commit), + "The size of the local heap space to commit."_doc) + + .def_prop_rw("loader_flags", + nb::overload_cast<>(&OptionalHeader::loader_flags, nb::const_), + nb::overload_cast(&OptionalHeader::loader_flags), + "According to the PE specifications, this value is *reserved* and **should** be 0."_doc) + + .def_prop_rw("numberof_rva_and_size", + nb::overload_cast<>(&OptionalHeader::numberof_rva_and_size, nb::const_), + nb::overload_cast(&OptionalHeader::numberof_rva_and_size), + "The number of " RST_CLASS_REF(lief.PE.DataDirectory) " that follow this header"_doc) + + .def(nb::self += OptionalHeader::DLL_CHARACTERISTICS(), nb::rv_policy::reference_internal) + .def(nb::self -= OptionalHeader::DLL_CHARACTERISTICS(), nb::rv_policy::reference_internal) + + .def("__contains__", + nb::overload_cast(&OptionalHeader::has, nb::const_), + "Check if the given " RST_CLASS_REF(lief.PE.OptionalHeader.DLL_CHARACTERISTICS) " is present"_doc) + + LIEF_COPYABLE(OptionalHeader) + LIEF_DEFAULT_STR(OptionalHeader); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyParser.cpp b/vendor/lief/api/python/src/PE/objects/pyParser.cpp new file mode 100644 index 0000000..8d04882 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyParser.cpp @@ -0,0 +1,67 @@ + +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include +#include +#include +#include + +#include "typing/InputParser.hpp" + +#include "LIEF/PE/Parser.hpp" +#include "LIEF/PE/Binary.hpp" + +#include "LIEF/BinaryStream/BinaryStream.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse_from_memory", nb::overload_cast(&Parser::parse_from_memory), + "Parse the PE binary at the given memory address"_doc, + "address"_a, "config"_a = ParserConfig::default_conf()); + + m.def("parse_from_memory", nb::overload_cast(&Parser::parse_from_memory), + "Parse the PE binary at the given memory address and with the given size"_doc, + "address"_a, "size"_a, "config"_a = ParserConfig::default_conf()); + + m.def("parse_from_dump", + [] (typing::InputParser obj, uint64_t addr, const ParserConfig& config) { + return Parser::parse_from_dump(obj.into_stream(), addr, config); + }, + R"delim( + Parse the PE binary from a memory dump given in the first parameter. + + A dump is a raw capture of the process' memory that was mapped starting at + the virtual address given in the second parameter. + )delim"_doc, + "obj"_a, "addr"_a, "config"_a = ParserConfig::default_conf(), + nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const ParserConfig& config) -> std::unique_ptr { + return Parser::parse(obj.into_stream(), config); + }, + "Parse the PE binary from the given parameter and return a :class:`lief.PE.Binary` object"_doc, + "obj"_a, "config"_a = ParserConfig::default_conf(), + nb::rv_policy::take_ownership); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyParserConfig.cpp b/vendor/lief/api/python/src/PE/objects/pyParserConfig.cpp new file mode 100644 index 0000000..75d184a --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyParserConfig.cpp @@ -0,0 +1,86 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "LIEF/PE/ParserConfig.hpp" + +#include "PE/pyPE.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "ParserConfig", + R"delim( + This class is used to configure the behavior of the PE Parser (:func:`lief.PE.parse`) + )delim"_doc) + + .def(nb::init<>()) + .def_rw("parse_signature", &ParserConfig::parse_signature, + "Whether to parse the PE Authenticode signature."_doc) + + .def_rw("parse_exports", &ParserConfig::parse_exports, + "Whether to parse the PE Export Directory."_doc) + + .def_rw("parse_imports", &ParserConfig::parse_imports, + "Whether to parse the PE Import Directory."_doc) + + .def_rw("parse_rsrc", &ParserConfig::parse_rsrc, + "Whether to parse the PE resources tree."_doc) + + .def_rw("parse_reloc", &ParserConfig::parse_reloc, + "Whether to parse PE relocations."_doc) + + .def_rw("parse_exceptions", &ParserConfig::parse_exceptions, + R"doc( + Whether to parse in-depth exception metadata. + + This option is disabled by default because it can introduce significant + parsing overhead. + )doc"_doc + ) + + .def_rw("parse_arm64x_binary", &ParserConfig::parse_arm64x_binary, + R"doc( + Whether to parse nested ARM64X binaries. + + This option is disabled by default because it can introduce significant + parsing overhead. + )doc"_doc) + + .def_rw("rebase", &ParserConfig::rebase, + R"doc( + If set, this value holds the original image base from which the binary + should be rebased. This is used to *undo* relocations and IAT bindings + when parsing a PE loaded in memory. + )doc"_doc) + + .def_prop_ro_static("default_conf", + [] (const nb::object& /* self */) { return ParserConfig::default_conf(); }, + "Default configuration for the PE Parser."_doc) + + .def_prop_ro_static("all", + [] (const nb::object& /* self */) { return ParserConfig::all(); }, + "Configuration that enables **all** optional parsing features."_doc) + + LIEF_DEFAULT_STR(ParserConfig); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyRelocation.cpp b/vendor/lief/api/python/src/PE/objects/pyRelocation.cpp new file mode 100644 index 0000000..c0a2496 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyRelocation.cpp @@ -0,0 +1,69 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/PE/RelocationEntry.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ reloc(m, "Relocation", + R"delim( + Class which represents the *Base Relocation Block* + Usually, we find this structure in the ``.reloc`` section + )delim"_doc); + + init_ref_iterator(reloc, "it_entries"); + + reloc + .def(nb::init<>()) + + .def_prop_rw("virtual_address", + nb::overload_cast<>(&Relocation::virtual_address, nb::const_), + nb::overload_cast(&Relocation::virtual_address), + "The RVA for which the offset of the relocation entries (RelocationEntry) is added"_doc) + + .def_prop_rw("block_size", + nb::overload_cast<>(&Relocation::block_size, nb::const_), + nb::overload_cast(&Relocation::block_size), + R"delim( + The total number of bytes in the base relocation block. + ``block_size = sizeof(BaseRelocationBlock) + nb_of_relocs * sizeof(uint16_t = RelocationEntry)`` + )delim"_doc) + + .def_prop_ro("entries", + nb::overload_cast<>(&Relocation::entries), + "Iterator over the " RST_CLASS_REF(lief.PE.RelocationEntry) ""_doc) + + .def("add_entry", + &Relocation::add_entry, + "Add a new " RST_CLASS_REF(lief.PE.RelocationEntry) ""_doc, + "new_entry"_a, + nb::rv_policy::reference_internal) + + LIEF_COPYABLE(Relocation) + LIEF_DEFAULT_STR(Relocation); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyRelocationEntry.cpp b/vendor/lief/api/python/src/PE/objects/pyRelocationEntry.cpp new file mode 100644 index 0000000..d04e07d --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyRelocationEntry.cpp @@ -0,0 +1,81 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/RelocationEntry.hpp" + +#include "enums_wrapper.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ entry(m, "RelocationEntry", + R"delim( + Class which represents an entry of the PE relocation table. + + It extends the :class:`lief.Relocation` object to provide an uniform API across the file formats. + )delim"_doc); + + #define ENTRY(X) .value(to_string(RelocationEntry::BASE_TYPES::X), RelocationEntry::BASE_TYPES::X) + enum_(entry, "BASE_TYPES") + ENTRY(UNKNOWN) + ENTRY(ABS) + ENTRY(HIGH) + ENTRY(LOW) + ENTRY(HIGHLOW) + ENTRY(HIGHADJ) + ENTRY(MIPS_JMPADDR) + ENTRY(ARM_MOV32) + ENTRY(RISCV_HI20) + ENTRY(SECTION) + ENTRY(THUMB_MOV32) + ENTRY(RISCV_LOW12I) + ENTRY(RISCV_LOW12S) + ENTRY(MIPS_JMPADDR16) + ENTRY(DIR64) + ENTRY(HIGH3ADJ); + #undef ENTRY + + entry + .def(nb::init<>()) + .def(nb::init()) + .def_prop_ro("data", + nb::overload_cast<>(&RelocationEntry::data, nb::const_), + R"delim( + Raw data of the relocation: + + * The **high** 4 bits store the relocation :attr:`~lief.PE.RelocationEntry.type` + * The **low** 12 bits store the relocation offset (:attr:`~lief.PE.RelocationEntry.position`) + )delim"_doc) + + .def_prop_rw("position", + nb::overload_cast<>(&RelocationEntry::position, nb::const_), + nb::overload_cast(&RelocationEntry::position), + "Offset - relative to :attr:`~lief.PE.Relocation.virtual_address` - where the relocation occurs"_doc) + + .def_prop_rw("type", + nb::overload_cast<>(&RelocationEntry::type, nb::const_), + nb::overload_cast(&RelocationEntry::type), + "Type of the relocation"_doc) + + LIEF_DEFAULT_STR(RelocationEntry); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyResourcesManager.cpp b/vendor/lief/api/python/src/PE/objects/pyResourcesManager.cpp new file mode 100644 index 0000000..beca40c --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyResourcesManager.cpp @@ -0,0 +1,174 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pyErr.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/ResourcesManager.hpp" +#include "LIEF/PE/ResourceNode.hpp" +#include "enums_wrapper.hpp" + +#include +#include + +#include "nanobind/extra/stl/u16string.h" +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ manager(m, "ResourcesManager", + "The Resource Manager provides an enhanced API to manipulate the resource tree"_doc); + + init_ref_iterator(manager, "it_const_dialogs"); + init_ref_iterator(manager, "it_const_icons"); + init_ref_iterator(manager, "it_const_accelerators"); + + nb::class_(manager, "string_entry_t") + .def_rw("string", &ResourcesManager::string_entry_t::string) + .def_rw("id", &ResourcesManager::string_entry_t::id) + LIEF_DEFAULT_STR(ResourcesManager::string_entry_t); + ; + + #define ENTRY(X) .value(to_string(ResourcesManager::TYPE::X), ResourcesManager::TYPE::X) + enum_(manager, "TYPE") + ENTRY(CURSOR) + ENTRY(BITMAP) + ENTRY(ICON) + ENTRY(MENU) + ENTRY(DIALOG) + ENTRY(STRING) + ENTRY(FONTDIR) + ENTRY(FONT) + ENTRY(ACCELERATOR) + ENTRY(RCDATA) + ENTRY(MESSAGETABLE) + ENTRY(GROUP_CURSOR) + ENTRY(GROUP_ICON) + ENTRY(VERSION) + ENTRY(DLGINCLUDE) + ENTRY(PLUGPLAY) + ENTRY(VXD) + ENTRY(ANICURSOR) + ENTRY(ANIICON) + ENTRY(HTML) + ENTRY(MANIFEST) + ; + #undef ENTRY + + manager + .def(nb::init(), nb::keep_alive<0, 1>(), + "node"_a) + + .def_prop_ro("has_manifest", + &ResourcesManager::has_manifest, + "``True`` if the resources contain a Manifest element"_doc) + + .def_prop_rw("manifest", + [] (const ResourcesManager& obj) { + return safe_string(obj.manifest()); + }, + nb::overload_cast(&ResourcesManager::manifest), + "Manifest as a ``string``"_doc) + + + .def_prop_ro("has_version", + &ResourcesManager::has_version, + "``True`` if the resources contain a " RST_CLASS_REF(lief.PE.ResourceVersion) ""_doc) + + .def_prop_ro("version", &ResourcesManager::version, + "Return a list of version info (``VS_VERSIONINFO``)."_doc) + + .def_prop_ro("has_icons", + &ResourcesManager::has_icons, + "``True`` if the resources contain " RST_CLASS_REF(lief.PE.ResourceIcon) ""_doc) + + .def_prop_ro("icons", &ResourcesManager::icons, + "Return the list of the " RST_CLASS_REF(lief.PE.ResourceIcon) " present in the resource"_doc, + nb::keep_alive<0, 1>()) + + .def("change_icon", + &ResourcesManager::change_icon, + "Switch the given icons"_doc, + "old_one"_a, "new_one"_a) + + .def_prop_ro("has_dialogs", + &ResourcesManager::has_dialogs, + "``True`` if the resources contain " RST_CLASS_REF(lief.PE.ResourceDialog) ""_doc) + + .def_prop_ro("dialogs", + &ResourcesManager::dialogs, + "Return the list of the " RST_CLASS_REF(lief.PE.ResourceDialog) " present in the resource"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("types", + &ResourcesManager::get_types, + "Return list of :class:`~.TYPE` present in the resources"_doc) + + .def("add_icon", + &ResourcesManager::add_icon, + "Add an icon to the resources"_doc, + "icon"_a) + + .def("has_type", + &ResourcesManager::has_type, + "``True`` if the resource has the given :class:`~.TYPE`"_doc, + "type"_a) + + .def_prop_ro("has_string_table", + &ResourcesManager::has_string_table, + "``True`` if resources contain " RST_CLASS_REF(lief.PE.ResourceStringTable) ""_doc) + + .def_prop_ro("string_table", &ResourcesManager::string_table, + "Return the list of the strings embedded in the string table (``RT_STRING``)"_doc) + + .def_prop_ro("has_html", + &ResourcesManager::has_html, + "``True`` if resources contain HTML resource"_doc) + + .def_prop_ro("html", + &ResourcesManager::html, + "HTML resource as the list of ``string``"_doc) + + .def_prop_ro("has_accelerator", + &ResourcesManager::has_accelerator, + "``True`` if resources contain " RST_CLASS_REF(lief.PE.ResourceAccelerator) ""_doc) + + .def_prop_ro("accelerator", &ResourcesManager::accelerator, + "Return list of " RST_CLASS_REF(lief.PE.ResourceAccelerator) " present in the resource"_doc, + nb::keep_alive<1, 0>()) + + .def("get_node_type", + nb::overload_cast(&ResourcesManager::get_node_type), + R"delim( + Return :class:`~lief.PE.ResourceNode` with the given :class:`~.TYPE` + or None if not found. + )delim"_doc, + "type"_a, + nb::rv_policy::reference_internal) + + .def("print", &ResourcesManager::print, + "Print the current resource tree", + "max_depth"_a = 0) + + LIEF_DEFAULT_STR(ResourcesManager); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/pyRichEntry.cpp b/vendor/lief/api/python/src/PE/objects/pyRichEntry.cpp new file mode 100644 index 0000000..2fddb4b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyRichEntry.cpp @@ -0,0 +1,59 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/RichEntry.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "RichEntry", + R"delim( + Class which represents an entry associated to the RichHeader + )delim"_doc) + .def(nb::init<>()) + .def(nb::init(), + "Constructor from " + ":attr:`~lief.PE.RichEntry.id`, " + ":attr:`~lief.PE.RichEntry.build_id` and " + ":attr:`~lief.PE.RichEntry.count`"_doc, + "id"_a, "build_id"_a, "count"_a) + + .def_prop_rw("id", + nb::overload_cast<>(&RichEntry::id, nb::const_), + nb::overload_cast(&RichEntry::id), + "Type of the entry"_doc) + + .def_prop_rw("build_id", + nb::overload_cast<>(&RichEntry::build_id, nb::const_), + nb::overload_cast(&RichEntry::build_id), + "Builder number of the tool (if any)"_doc) + + .def_prop_rw("count", + nb::overload_cast<>(&RichEntry::count, nb::const_), + nb::overload_cast(&RichEntry::count), + "*Occurrence* count"_doc) + + LIEF_COPYABLE(RichEntry) + LIEF_DEFAULT_STR(RichEntry); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyRichHeader.cpp b/vendor/lief/api/python/src/PE/objects/pyRichHeader.cpp new file mode 100644 index 0000000..0e4cb78 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyRichHeader.cpp @@ -0,0 +1,105 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/RichHeader.hpp" + +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ rich(m, "RichHeader", + R"delim( + Class which represents the not-so-documented rich header + + This structure is usually located at the end of the :attr:`~lief.PE.Binary.dos_stub` + and contains information about the build environment. + + It is generated by the Microsoft linker `link.exe` and there are no options to disable + or remove this information. + )delim"_doc); + + init_ref_iterator(rich, "it_entries"); + + rich + .def(nb::init<>()) + .def_prop_rw("key", + nb::overload_cast<>(&RichHeader::key, nb::const_), + nb::overload_cast(&RichHeader::key), + "Key used to encode the header (xor operation)"_doc) + + .def_prop_ro("entries", + nb::overload_cast<>(&RichHeader::entries), + "Return an iterator over the " RST_CLASS_REF(lief.PE.RichEntry) " within the header"_doc, + nb::keep_alive<1, 0>()) + + .def("add_entry", + nb::overload_cast(&RichHeader::add_entry), + "Add a new " RST_CLASS_REF(lief.PE.RichEntry) ""_doc, + "entry"_a) + + .def("add_entry", + nb::overload_cast(&RichHeader::add_entry), + "Add a new " RST_CLASS_REF(lief.PE.RichEntry) " given its " + ":attr:`~lief.PE.RichEntry.id`, " + ":attr:`~lief.PE.RichEntry.build_id`, " + ":attr:`~lief.PE.RichEntry.count`"_doc, + "id"_a, "build_id"_a, "count"_a) + + .def("raw", + nb::overload_cast<>(&RichHeader::raw, nb::const_), + R"delim( + The raw structure of the Rich header without xor-encoding. + + This function is equivalent as calling the other raw function with a `xor_key` set to 0 + )delim"_doc) + + .def("raw", + nb::overload_cast(&RichHeader::raw, nb::const_), + R"delim( + Given this rich header, this function re-computes + the raw bytes of the structure with the provided xor-key. + + You can access the decoded data's structure with the `xor_key` set to 0 + )delim"_doc, "xor_key"_a) + + .def("hash", + nb::overload_cast(&RichHeader::hash, nb::const_), + R"delim( + Compute the hash of the decoded rich header structure with the given hash :class:`~lief.PE.ALGORITHMS` + )delim"_doc, "algo"_a) + + .def("hash", + nb::overload_cast(&RichHeader::hash, nb::const_), + R"delim( + Compute the hash of the rich header structure encoded with the provided key and the given hash + :class:`~lief.PE.ALGORITHMS` + )delim"_doc, + "algo"_a, "xor_key"_a) + + LIEF_COPYABLE(RichHeader) + LIEF_DEFAULT_STR(RichHeader); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pySection.cpp b/vendor/lief/api/python/src/PE/objects/pySection.cpp new file mode 100644 index 0000000..acdf604 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pySection.cpp @@ -0,0 +1,190 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/Section.hpp" +#include "LIEF/COFF/String.hpp" +#include "enums_wrapper.hpp" + +#include +#include +#include +#include +#include "nanobind/utils.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::PE::py { + +template<> +void create
(nb::module_& m) { + nb::class_ sec(m, "Section", + R"delim( + Class which represents a PE section. + + It extends the base class :class:`lief.Section` + )delim"_doc); + + enum_(sec, "CHARACTERISTICS", nb::is_flag()) + .value(PY_ENUM(Section::CHARACTERISTICS::TYPE_NO_PAD)) + .value(PY_ENUM(Section::CHARACTERISTICS::CNT_CODE)) + .value(PY_ENUM(Section::CHARACTERISTICS::CNT_INITIALIZED_DATA)) + .value(PY_ENUM(Section::CHARACTERISTICS::CNT_UNINITIALIZED_DATA)) + .value(PY_ENUM(Section::CHARACTERISTICS::LNK_OTHER)) + .value(PY_ENUM(Section::CHARACTERISTICS::LNK_INFO)) + .value(PY_ENUM(Section::CHARACTERISTICS::LNK_REMOVE)) + .value(PY_ENUM(Section::CHARACTERISTICS::LNK_COMDAT)) + .value(PY_ENUM(Section::CHARACTERISTICS::GPREL)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_PURGEABLE)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_16BIT)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_LOCKED)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_PRELOAD)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_1BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_2BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_4BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_8BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_16BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_32BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_64BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_128BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_256BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_512BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_1024BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_2048BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_4096BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::ALIGN_8192BYTES)) + .value(PY_ENUM(Section::CHARACTERISTICS::LNK_NRELOC_OVFL)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_DISCARDABLE)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_NOT_CACHED)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_NOT_PAGED)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_SHARED)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_EXECUTE)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_READ)) + .value(PY_ENUM(Section::CHARACTERISTICS::MEM_WRITE)); + + sec + .def(nb::init<>()) + .def(nb::init>(), + "name"_a, "content"_a) + + .def(nb::init(), + "name"_a) + + .def_prop_rw("virtual_size", + nb::overload_cast<>(&Section::virtual_size, nb::const_), + nb::overload_cast(&Section::virtual_size), + R"delim( + The total size of the section when loaded into memory. + + If this value is greater than :attr:`~lief.PE.Section.sizeof_raw_data`, + the section is zero-padded. + )delim"_doc) + + .def_prop_rw("sizeof_raw_data", + nb::overload_cast<>(&Section::sizeof_raw_data, nb::const_), + nb::overload_cast(&Section::sizeof_raw_data), + "Alias of :attr:`~lief.PE.Section.size` (size of the data in the section)"_doc) + + .def_prop_rw("pointerto_raw_data", + nb::overload_cast<>(&Section::pointerto_raw_data, nb::const_), + nb::overload_cast(&Section::pointerto_raw_data), + "The offset of the section data in the PE file. Alias of :attr:`~lief.PE.Section.offset`"_doc) + + .def_prop_rw("pointerto_relocation", + nb::overload_cast<>(&Section::pointerto_relocation, nb::const_), + nb::overload_cast(&Section::pointerto_relocation), + R"delim( + The file pointer to the beginning of the COFF relocation entries for + the section. This is set to zero for executable images or if there are + no relocations. + + For modern PE binaries, this value is usually set to 0 as the relocations are managed by + :class:`~lief.PE.Relocation`. + )delim"_doc) + + .def_prop_rw("pointerto_line_numbers", + nb::overload_cast<>(&Section::pointerto_line_numbers, nb::const_), + nb::overload_cast(&Section::pointerto_line_numbers), + R"delim( + The file pointer to the beginning of line-number entries for the section. + This is set to zero if there are no COFF line numbers. This value should + be zero for an image because COFF debugging information is deprecated + and modern debug information relies on the PDB files. + )delim"_doc) + + .def_prop_rw("numberof_relocations", + nb::overload_cast<>(&Section::numberof_relocations, nb::const_), + nb::overload_cast(&Section::numberof_relocations), + R"delim( + The number of relocation entries for the section. + + See: :attr:`~lief.PE.Section.pointerto_relocation` + )delim"_doc) + + .def_prop_rw("numberof_line_numbers", + nb::overload_cast<>(&Section::numberof_line_numbers, nb::const_), + nb::overload_cast(&Section::numberof_line_numbers), + R"delim( + The number of line-number entries for the section. + This value should be zero for an image because COFF debugging information is + deprecated. + + See: :attr:`~lief.PE.Section.pointerto_line_numbers` + )delim"_doc) + + + .def_prop_rw("characteristics", + nb::overload_cast<>(&Section::characteristics, nb::const_), + nb::overload_cast(&Section::characteristics), + "The " RST_CLASS_REF(lief.PE.Section.CHARACTERISTICS) " that describe the characteristics of the section"_doc) + + .def_prop_ro("characteristics_lists", + &Section::characteristics_list, + ":attr:`~lief.PE.Section.characteristics` as a ``list``"_doc) + + .def("has_characteristic", + &Section::has_characteristic, + "``True`` if the section has the given " RST_CLASS_REF(lief.PE.Section.CHARACTERISTICS) ""_doc, + "characteristic"_a) + + .def_prop_ro("is_discardable", &Section::is_discardable, + R"doc( + True if the section can be discarded as needed. + + This is typically the case for debug-related sections. + )doc"_doc + ) + + .def_prop_ro("coff_string", nb::overload_cast<>(&Section::coff_string), + R"doc( + Return the COFF string associated with the section's name (or None) + + This coff string is usually present for long section names whose length + does not fit in the 8 bytes allocated by the PE format. + )doc"_doc + ) + + .def_prop_ro("padding", + [] (const Section& sec) { + return nb::to_bytes(sec.padding()); + }, + "Section padding content as bytes"_doc) + + LIEF_COPYABLE(Section) + LIEF_DEFAULT_STR(Section); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/pyTLS.cpp b/vendor/lief/api/python/src/PE/objects/pyTLS.cpp new file mode 100644 index 0000000..c2b45e3 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/pyTLS.cpp @@ -0,0 +1,138 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "nanobind/extra/stl/lief_span.h" + +#include "LIEF/PE/TLS.hpp" +#include "LIEF/PE/Section.hpp" +#include "LIEF/PE/DataDirectory.hpp" + +#include +#include + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "TLS", + R"delim( + Class which represents the PE Thread Local Storage. + This PE structure is also used to implement binary/library constructors. + )delim"_doc) + .def(nb::init<>(), + "Default constructor"_doc) + + .def_prop_rw("callbacks", + nb::overload_cast<>(&TLS::callbacks, nb::const_), + nb::overload_cast>(&TLS::callbacks), + R"delim( + List of the callbacks associated with the current TLS. + + These functions are called before any other functions. + )delim"_doc) + + .def_prop_rw("addressof_index", + nb::overload_cast<>(&TLS::addressof_index, nb::const_), + nb::overload_cast(&TLS::addressof_index), + R"delim( + The location to receive the TLS index assigned by the loader. + This location should be located in a writable section like ``.data``. + )delim"_doc) + + .def_prop_rw("addressof_callbacks", + nb::overload_cast<>(&TLS::addressof_callbacks, nb::const_), + nb::overload_cast(&TLS::addressof_callbacks), + R"delim( + Pointer to an array of TLS callback functions. + + The array is null-terminated, so if there is no callback, + this field points to 4 bytes set to zero. + + See: :attr:`~lief.PE.TLS.callbacks` + )delim"_doc) + + .def_prop_rw("sizeof_zero_fill", + nb::overload_cast<>(&TLS::sizeof_zero_fill, nb::const_), + nb::overload_cast(&TLS::sizeof_zero_fill), + R"delim( + Size in bytes of the zeros to be *padded* after the data specified by + :attr:`~.data_template`. + )delim"_doc) + + + .def_prop_rw("characteristics", + nb::overload_cast<>(&TLS::characteristics, nb::const_), + nb::overload_cast(&TLS::characteristics), + R"delim( + The four bits [23:20] describe alignment info. + Possible values are those defined as ``IMAGE_SCN_ALIGN_*``, which are + also used to describe alignment of section in object files. + The other 28 bits are reserved for future use. + )delim"_doc) + + .def_prop_rw("addressof_raw_data", + nb::overload_cast<>(&TLS::addressof_raw_data, nb::const_), + nb::overload_cast>(&TLS::addressof_raw_data), + R"delim( + Tuple ``(start address, end address)`` of the TLS template. + The template is a block of data that is used to initialize TLS data. + The system copies all of this data each time a thread is created, so it + must not be corrupted. + + .. note:: + + These addresses are not RVA. It is addresses for which there should + be a base relocation in the ``.reloc`` section. + )delim"_doc) + + .def_prop_rw("data_template", + nb::overload_cast<>(&TLS::data_template, nb::const_), + nb::overload_cast>(&TLS::data_template), + "The initial content used to initialize TLS data."_doc) + + .def_prop_ro("has_section", + &TLS::has_section, + "``True`` if there is a " RST_CLASS_REF(lief.PE.Section) " associated with the TLS object"_doc) + + .def_prop_ro("has_data_directory", + &TLS::has_data_directory, + "``True`` if there is a " RST_CLASS_REF(lief.PE.DataDirectory) " associated with the TLS object"_doc) + + .def_prop_ro("directory", + nb::overload_cast<>(&TLS::directory), + "" RST_CLASS_REF(lief.PE.DataDirectory) " associated with the TLS object (or None if not linked)"_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("section", + nb::overload_cast<>(&TLS::section), + "" RST_CLASS_REF(lief.PE.Section) " associated with the TLS object (or None if not linked)"_doc, + nb::rv_policy::reference_internal) + + .def("add_callback", &TLS::add_callback, + "Add a new TLS callback"_doc, + "addr"_a, + nb::lock_self(), + nb::rv_policy::reference_internal) + + LIEF_COPYABLE(TLS) + LIEF_DEFAULT_STR(TLS); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/resources/CMakeLists.txt new file mode 100644 index 0000000..dc8034f --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/CMakeLists.txt @@ -0,0 +1,16 @@ +target_sources(pyLIEF PRIVATE + pyAcceleratorCodes.cpp + pyResourceAccelerator.cpp + pyResourceData.cpp + pyResourceDialog.cpp + pyResourceDialogExtended.cpp + pyResourceDialogRegular.cpp + pyResourceDirectory.cpp + pyResourceIcon.cpp + pyResourceNode.cpp + pyResourceStringFileInfo.cpp + pyResourceStringTable.cpp + pyResourceVar.cpp + pyResourceVarFileInfo.cpp + pyResourceVersion.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyAcceleratorCodes.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyAcceleratorCodes.cpp new file mode 100644 index 0000000..b70dd1a --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyAcceleratorCodes.cpp @@ -0,0 +1,201 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/resources/AcceleratorCodes.hpp" +#include "PE/pyPE.hpp" + +#include "enums_wrapper.hpp" + +namespace LIEF::PE::py { +template<> +void create(nb::module_& m) { + #define ENTRY(X) .value(to_string(ACCELERATOR_CODES::X), ACCELERATOR_CODES::X) + enum_(m, "ACCELERATOR_CODES") + ENTRY(LBUTTON) + ENTRY(RBUTTON) + ENTRY(CANCEL) + ENTRY(MBUTTON) + ENTRY(XBUTTON1_K) + ENTRY(XBUTTON2_K) + ENTRY(BACK) + ENTRY(TAB) + ENTRY(CLEAR) + ENTRY(RETURN) + ENTRY(SHIFT) + ENTRY(CONTROL) + ENTRY(MENU) + ENTRY(PAUSE) + ENTRY(CAPITAL) + ENTRY(KANA) + ENTRY(IME_ON) + ENTRY(JUNJA) + ENTRY(FINAL) + ENTRY(KANJI) + ENTRY(IME_OFF) + ENTRY(ESCAPE) + ENTRY(CONVERT) + ENTRY(NONCONVERT) + ENTRY(ACCEPT) + ENTRY(MODECHANGE) + ENTRY(SPACE) + ENTRY(PRIOR) + ENTRY(NEXT) + ENTRY(END) + ENTRY(HOME) + ENTRY(LEFT) + ENTRY(UP) + ENTRY(RIGHT) + ENTRY(DOWN) + ENTRY(SELECT) + ENTRY(PRINT) + ENTRY(EXECUTE) + ENTRY(SNAPSHOT) + ENTRY(INSERT) + ENTRY(DELETE_K) + ENTRY(HELP) + ENTRY(NUM_0) + ENTRY(NUM_1) + ENTRY(NUM_2) + ENTRY(NUM_3) + ENTRY(NUM_4) + ENTRY(NUM_5) + ENTRY(NUM_6) + ENTRY(NUM_7) + ENTRY(NUM_8) + ENTRY(NUM_9) + ENTRY(A) + ENTRY(B) + ENTRY(C) + ENTRY(D) + ENTRY(E) + ENTRY(F) + ENTRY(G) + ENTRY(H) + ENTRY(I) + ENTRY(J) + ENTRY(K) + ENTRY(L) + ENTRY(M) + ENTRY(N) + ENTRY(O) + ENTRY(P) + ENTRY(Q) + ENTRY(R) + ENTRY(S) + ENTRY(T) + ENTRY(U) + ENTRY(V) + ENTRY(W) + ENTRY(X) + ENTRY(Y) + ENTRY(Z) + ENTRY(LWIN) + ENTRY(RWIN) + ENTRY(APPS) + ENTRY(SLEEP) + ENTRY(NUMPAD0) + ENTRY(NUMPAD1) + ENTRY(NUMPAD2) + ENTRY(NUMPAD3) + ENTRY(NUMPAD4) + ENTRY(NUMPAD5) + ENTRY(NUMPAD6) + ENTRY(NUMPAD7) + ENTRY(NUMPAD8) + ENTRY(NUMPAD9) + ENTRY(MULTIPLY) + ENTRY(ADD) + ENTRY(SEPARATOR) + ENTRY(SUBTRACT) + ENTRY(DECIMAL) + ENTRY(DIVIDE) + ENTRY(F1) + ENTRY(F2) + ENTRY(F3) + ENTRY(F4) + ENTRY(F5) + ENTRY(F6) + ENTRY(F7) + ENTRY(F8) + ENTRY(F9) + ENTRY(F10) + ENTRY(F11) + ENTRY(F12) + ENTRY(F13) + ENTRY(F14) + ENTRY(F15) + ENTRY(F16) + ENTRY(F17) + ENTRY(F18) + ENTRY(F19) + ENTRY(F20) + ENTRY(F21) + ENTRY(F22) + ENTRY(F23) + ENTRY(F24) + ENTRY(NUMLOCK) + ENTRY(SCROLL) + ENTRY(LSHIFT) + ENTRY(RSHIFT) + ENTRY(LCONTROL) + ENTRY(RCONTROL) + ENTRY(LMENU) + ENTRY(RMENU) + ENTRY(BROWSER_BACK) + ENTRY(BROWSER_FORWARD) + ENTRY(BROWSER_REFRESH) + ENTRY(BROWSER_STOP) + ENTRY(BROWSER_SEARCH) + ENTRY(BROWSER_FAVORITES) + ENTRY(BROWSER_HOME) + ENTRY(VOLUME_MUTE) + ENTRY(VOLUME_DOWN) + ENTRY(VOLUME_UP) + ENTRY(MEDIA_NEXT_TRACK) + ENTRY(MEDIA_PREV_TRACK) + ENTRY(MEDIA_STOP) + ENTRY(MEDIA_PLAY_PAUSE) + ENTRY(LAUNCH_MAIL) + ENTRY(LAUNCH_MEDIA_SELECT) + ENTRY(LAUNCH_APP1) + ENTRY(LAUNCH_APP2) + ENTRY(OEM_1) + ENTRY(OEM_PLUS) + ENTRY(OEM_COMMA) + ENTRY(OEM_MINUS) + ENTRY(OEM_PERIOD) + ENTRY(OEM_2) + ENTRY(OEM_4) + ENTRY(OEM_5) + ENTRY(OEM_6) + ENTRY(OEM_7) + ENTRY(OEM_8) + ENTRY(OEM_102) + ENTRY(PROCESSKEY) + ENTRY(PACKET) + ENTRY(ATTN) + ENTRY(CRSEL) + ENTRY(EXSEL) + ENTRY(EREOF) + ENTRY(PLAY) + ENTRY(ZOOM) + ENTRY(NONAME) + ENTRY(PA1) + ENTRY(OEM_CLEAR) + ; + #undef ENTRY +} +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceAccelerator.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceAccelerator.cpp new file mode 100644 index 0000000..57cd16b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceAccelerator.cpp @@ -0,0 +1,105 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "PE/pyPE.hpp" + +#include "LIEF/PE/resources/ResourceAccelerator.hpp" +#include "enums_wrapper.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + create(m); + + nb::class_ obj(m, "ResourceAccelerator"); + enum_(obj, "FLAGS", nb::is_flag(), + R"doc( + From: https://docs.microsoft.com/en-us/windows/win32/menurc/acceltableentry + )doc"_doc + ) + .value("VIRTKEY", ResourceAccelerator::FLAGS::VIRTKEY, + R"doc( + The accelerator key is a virtual-key code. If this flag is not specified, + the accelerator key is assumed to specify an ASCII character code. + )doc"_doc) + + .value("NOINVERT", ResourceAccelerator::FLAGS::NOINVERT, + R"doc( + A menu item on the menu bar is not highlighted when an accelerator is + used. This attribute is obsolete and retained only for backward + compatibility with resource files designed for 16-bit Windows. + )doc"_doc) + + .value("SHIFT", ResourceAccelerator::FLAGS::SHIFT, + R"doc( + The accelerator is activated only if the user presses the SHIFT key. + This flag applies only to virtual keys. + )doc"_doc) + + .value("CONTROL", ResourceAccelerator::FLAGS::CONTROL, + R"doc( + The accelerator is activated only if the user presses the CTRL key. + This flag applies only to virtual keys. + )doc"_doc) + + .value("ALT", ResourceAccelerator::FLAGS::ALT, + R"doc( + The accelerator is activated only if the user presses the ALT key. + This flag applies only to virtual keys. + )doc"_doc) + + .value("END", ResourceAccelerator::FLAGS::END, + R"doc( + The entry is last in an accelerator table. + )doc"_doc) + ; + + obj + .def_prop_ro("flags", + nb::overload_cast<>(&ResourceAccelerator::flags, nb::const_), + "Describe the keyboard accelerator characteristics."_doc) + + .def_prop_ro("ansi", + nb::overload_cast<>(&ResourceAccelerator::ansi, nb::const_), + "An ANSI character value or a virtual-key code that identifies the accelerator key."_doc) + + .def_prop_ro("ansi_str", + nb::overload_cast<>(&ResourceAccelerator::ansi_str, nb::const_)) + + .def_prop_ro("id", + nb::overload_cast<>(&ResourceAccelerator::id, nb::const_), + "An identifier for the keyboard accelerator."_doc) + + .def_prop_ro("padding", + nb::overload_cast<>(&ResourceAccelerator::padding, nb::const_), + "The number of bytes inserted to ensure that the structure is aligned on a DWORD boundary."_doc) + + .def("has", &ResourceAccelerator::has, + "Whether the entry has the given flag"_doc) + + .def("add", &ResourceAccelerator::add, + "Append the given flag"_doc) + + .def("remove", &ResourceAccelerator::remove, + "Remove the given flag"_doc) + + LIEF_DEFAULT_STR(ResourceAccelerator); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceData.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceData.cpp new file mode 100644 index 0000000..3342dcb --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceData.cpp @@ -0,0 +1,72 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "LIEF/PE/ResourceData.hpp" + +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ResourceData", + R"delim( + Class which represents a Data Node in the PE resources tree + )delim"_doc) + .def(nb::init<>(), + "Default constructor"_doc) + + .def(nb::init&, uint32_t>(), + "content"_a, "code_page"_a = 0) + + .def_prop_rw("code_page", + nb::overload_cast<>(&ResourceData::code_page, nb::const_), + nb::overload_cast(&ResourceData::code_page), + R"delim( + Return the code page that is used to decode code point + values within the resource data. Typically, the code page is the Unicode code page. + )delim"_doc) + + .def_prop_rw("content", + nb::overload_cast<>(&ResourceData::content, nb::const_), + [] (ResourceData& self, nb::bytes bytes) { + self.content(nanobind::to_vector(bytes)); + }, "Resource content"_doc) + + .def_prop_rw("reserved", + nb::overload_cast<>(&ResourceData::reserved, nb::const_), + nb::overload_cast(&ResourceData::reserved), + "Reserved value. Should be ``0``"_doc) + + .def_prop_ro("offset", + &ResourceData::offset, + R"delim( + Offset of the content within the resource + + .. warning:: + + This value can change when re-building the resource table + )delim"_doc) + + LIEF_DEFAULT_STR(ResourceData); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialog.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialog.cpp new file mode 100644 index 0000000..4f8989e --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialog.cpp @@ -0,0 +1,333 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "enums_wrapper.hpp" + +#include "LIEF/PE/resources/ResourceDialog.hpp" + +#include +#include +#include +#include +#include + +#include "PE/ordinal_or_str.hpp" +#include "nanobind/extra/stl/u16string.h" +#include "nanobind/extra/stl/lief_span.h" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ dialog(m, "ResourceDialog", + R"delim( + This class is the base class for either a regular (legacy) Dialog or + an extended Dialog. These different kinds of Dialogs are documented by MS + at the following addresses: + + - https://learn.microsoft.com/en-us/windows/win32/api/winuser/ns-winuser-dlgtemplate + - https://learn.microsoft.com/fr-fr/windows/win32/dlgbox/dlgitemtemplateex + )delim"_doc); + + #define ENTRY(X) .value(to_string(ResourceDialog::DIALOG_STYLES::X), ResourceDialog::DIALOG_STYLES::X) + enum_(dialog, "DIALOG_STYLES", nb::is_flag(), + "From: https://learn.microsoft.com/en-us/windows/win32/dlgbox/dialog-box-styles"_doc + ) + ENTRY(ABSALIGN) + ENTRY(SYSMODAL) + ENTRY(LOCALEDIT) + ENTRY(SETFONT) + ENTRY(MODALFRAME) + ENTRY(NOIDLEMSG) + ENTRY(SETFOREGROUND) + ENTRY(S3DLOOK) + ENTRY(FIXEDSYS) + ENTRY(NOFAILCREATE) + ENTRY(CONTROL) + ENTRY(CENTER) + ENTRY(CENTERMOUSE) + ENTRY(CONTEXTHELP) + ENTRY(SHELLFONT) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(ResourceDialog::WINDOW_STYLES::X), ResourceDialog::WINDOW_STYLES::X) + enum_(dialog, "WINDOW_STYLES", nb::is_flag(), + "From: https://docs.microsoft.com/en-us/windows/win32/winmsg/window-styles"_doc + ) + ENTRY(OVERLAPPED) + ENTRY(POPUP) + ENTRY(CHILD) + ENTRY(MINIMIZE) + ENTRY(VISIBLE) + ENTRY(DISABLED) + ENTRY(CLIPSIBLINGS) + ENTRY(CLIPCHILDREN) + ENTRY(MAXIMIZE) + ENTRY(CAPTION) + ENTRY(BORDER) + ENTRY(DLGFRAME) + ENTRY(VSCROLL) + ENTRY(HSCROLL) + ENTRY(SYSMENU) + ENTRY(THICKFRAME) + ENTRY(GROUP) + ENTRY(TABSTOP) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(ResourceDialog::WINDOW_EXTENDED_STYLES::X), ResourceDialog::WINDOW_EXTENDED_STYLES::X) + enum_(dialog, "WINDOW_EXTENDED_STYLES", nb::is_flag(), + "From: https://docs.microsoft.com/en-us/windows/win32/winmsg/extended-window-styles"_doc + ) + ENTRY(DLGMODALFRAME) + ENTRY(NOPARENTNOTIFY) + ENTRY(TOPMOST) + ENTRY(ACCEPTFILES) + ENTRY(TRANSPARENT_STY) + ENTRY(MDICHILD) + ENTRY(TOOLWINDOW) + ENTRY(WINDOWEDGE) + ENTRY(CLIENTEDGE) + ENTRY(CONTEXTHELP) + ENTRY(RIGHT) + ENTRY(LEFT) + ENTRY(RTLREADING) + ENTRY(LEFTSCROLLBAR) + ENTRY(CONTROLPARENT) + ENTRY(STATICEDGE) + ENTRY(APPWINDOW) + ; + #undef ENTRY + + #define ENTRY(X) .value(to_string(ResourceDialog::CONTROL_STYLES::X), ResourceDialog::CONTROL_STYLES::X) + enum_(dialog, "CONTROL_STYLES", nb::is_flag(), + "From: https://learn.microsoft.com/en-us/windows/win32/controls/common-control-styles"_doc + ) + ENTRY(TOP) + ENTRY(NOMOVEY) + ENTRY(BOTTOM) + ENTRY(NORESIZE) + ENTRY(NOPARENTALIGN) + ENTRY(ADJUSTABLE) + ENTRY(NODIVIDER) + ENTRY(VERT) + ENTRY(LEFT) + ENTRY(RIGHT) + ENTRY(NOMOVEX) + ; + #undef ENTRY + + nb::enum_(dialog, "TYPE", + R"doc( + Enum for discriminating the kind of the Dialog (regular vs extended) + )doc"_doc + ) + .value("UNKNOWN", ResourceDialog::TYPE::UNKNOWN) + .value("REGULAR", ResourceDialog::TYPE::REGULAR) + .value("EXTENDED", ResourceDialog::TYPE::EXTENDED); + + nb::class_(dialog, "Item") + .def_prop_rw("style", + nb::overload_cast<>(&ResourceDialog::Item::style, nb::const_), + nb::overload_cast(&ResourceDialog::Item::style), + nb::rv_policy::reference_internal, + R"doc( + The style of the control. This can be a combination of :class:`~.WINDOW_STYLES` + or :class:`~.CONTROL_STYLES`. + )doc"_doc + ) + + .def_prop_rw("extended_style", + nb::overload_cast<>(&ResourceDialog::Item::extended_style, nb::const_), + nb::overload_cast(&ResourceDialog::Item::extended_style), + nb::rv_policy::reference_internal, + R"doc( + The extended styles for a window. This member is not used to create + controls in dialog boxes, but applications that use dialog box templates + can use it to create other types of windows. + + It can take a combination of :class:`~.WINDOW_EXTENDED_STYLES` + )doc"_doc + ) + + .def_prop_rw("id", + nb::overload_cast<>(&ResourceDialog::Item::id, nb::const_), + nb::overload_cast(&ResourceDialog::Item::id), + nb::rv_policy::reference_internal, + "The control identifier."_doc + ) + + .def_prop_rw("x", + nb::overload_cast<>(&ResourceDialog::Item::x, nb::const_), + nb::overload_cast(&ResourceDialog::Item::x), + nb::rv_policy::reference_internal, + R"doc( + The x-coordinate, in dialog box units, of the upper-left corner of the + control. This coordinate is always relative to the upper-left corner of + the dialog box's client area. + )doc"_doc + ) + + .def_prop_rw("y", + nb::overload_cast<>(&ResourceDialog::Item::y, nb::const_), + nb::overload_cast(&ResourceDialog::Item::y), + nb::rv_policy::reference_internal, + R"doc( + The y-coordinate, in dialog box units, of the upper-left corner of the + control. This coordinate is always relative to the upper-left corner of + the dialog box's client area. + )doc"_doc + ) + + .def_prop_rw("cx", + nb::overload_cast<>(&ResourceDialog::Item::cx, nb::const_), + nb::overload_cast(&ResourceDialog::Item::cx), + nb::rv_policy::reference_internal, + "The width, in dialog box units, of the control."_doc) + + .def_prop_rw("cy", + nb::overload_cast<>(&ResourceDialog::Item::cy, nb::const_), + nb::overload_cast(&ResourceDialog::Item::cy), + nb::rv_policy::reference_internal, + "The height, in dialog box units, of the control."_doc) + + .def("has", nb::overload_cast(&ResourceDialog::Item::has, nb::const_), + "style"_a, "Check if this item has the given :class:`~.WINDOW_STYLES`"_doc) + + .def("has", nb::overload_cast(&ResourceDialog::Item::has, nb::const_), + "style"_a, "Check if this item has the given :class:`~.CONTROL_STYLES`"_doc) + + .def_prop_ro("window_styles", &ResourceDialog::Item::window_styles, + "List of :class:`~.WINDOW_STYLES` used by this item"_doc) + + .def_prop_ro("control_styles", &ResourceDialog::Item::control_styles, + "List of :class:`~.CONTROL_STYLES` used by this item"_doc) + + .def_prop_ro("clazz", nb::overload_cast<>(&ResourceDialog::Item::clazz, nb::const_), + R"doc( + Window class of the control. This can be either: a string that specifies + the name of a registered window class or an ordinal value of a predefined + system class. + )doc"_doc) + + .def_prop_ro("title", nb::overload_cast<>(&ResourceDialog::Item::title, nb::const_), + R"doc( + Title of the item which can be either: a string that specifies the + initial text or an ordinal value of a resource, such as an icon, in an + executable file + )doc"_doc) + + .def_prop_ro("creation_data", nb::overload_cast<>(&ResourceDialog::Item::creation_data, nb::const_), + "Creation data that is passed to the control's window procedure"_doc) + + LIEF_DEFAULT_STR(ResourceDialog::Item); + ; + + dialog + .def_prop_ro("type", &ResourceDialog::type) + .def_prop_rw("style", + nb::overload_cast<>(&ResourceDialog::style, nb::const_), + nb::overload_cast(&ResourceDialog::style), + nb::rv_policy::reference_internal, + R"doc( + The style of the dialog box. This member can be a combination of window + style values (such as :attr:`~.WINDOW_STYLES.CAPTION` and + :attr:`~.WINDOW_STYLES.SYSMENU`) and dialog box style values + (such as :attr:`~.DIALOG_STYLES.CENTER`). + )doc"_doc + ) + + .def_prop_rw("extended_style", + nb::overload_cast<>(&ResourceDialog::extended_style, nb::const_), + nb::overload_cast(&ResourceDialog::extended_style), + nb::rv_policy::reference_internal, + R"doc( + The extended styles for a window. This member is not used to create dialog + boxes, but applications that use dialog box templates can use it to create + other types of windows. For a list of values, see :class:`~.WINDOW_EXTENDED_STYLES` + )doc"_doc + ) + + .def_prop_rw("x", + nb::overload_cast<>(&ResourceDialog::x, nb::const_), + nb::overload_cast(&ResourceDialog::x), + nb::rv_policy::reference_internal, + R"doc( + The x-coordinate, in dialog box units, of the upper-left corner of the + dialog box. + )doc"_doc + ) + + .def_prop_rw("y", + nb::overload_cast<>(&ResourceDialog::y, nb::const_), + nb::overload_cast(&ResourceDialog::y), + nb::rv_policy::reference_internal, + R"doc( + The y-coordinate, in dialog box units, of the upper-left corner of the + dialog box. + )doc"_doc + ) + + .def_prop_rw("cx", + nb::overload_cast<>(&ResourceDialog::cx, nb::const_), + nb::overload_cast(&ResourceDialog::cx), + nb::rv_policy::reference_internal, + "The width, in dialog box units, of the dialog box."_doc + ) + + .def_prop_rw("cy", + nb::overload_cast<>(&ResourceDialog::cy, nb::const_), + nb::overload_cast(&ResourceDialog::cy), + nb::rv_policy::reference_internal, + "The height, in dialog box units, of the dialog box"_doc + ) + + .def("has", nb::overload_cast(&ResourceDialog::has, nb::const_), + "Check if the dialog uses the given dialog style"_doc) + + .def("has", nb::overload_cast(&ResourceDialog::has, nb::const_), + "Check if the dialog uses the given window style"_doc) + + .def("has", nb::overload_cast(&ResourceDialog::has, nb::const_), + "Check if the dialog uses the given extended window style"_doc) + + .def_prop_ro("styles_list", &ResourceDialog::styles_list, + "List of :class:`~.DIALOG_STYLES` used by this dialog"_doc) + + .def_prop_ro("windows_styles_list", &ResourceDialog::windows_styles_list, + "List of :class:`~.WINDOW_STYLES` used by this dialog"_doc) + + .def_prop_ro("windows_ext_styles_list", &ResourceDialog::windows_ext_styles_list, + "List of :class:`~.WINDOW_EXTENDED_STYLES` used by this dialog"_doc) + + .def_prop_rw("title", nb::overload_cast<>(&ResourceDialog::title_utf8, nb::const_), + nb::overload_cast(&ResourceDialog::title), + nb::rv_policy::reference_internal, + "title of the dialog box"_doc) + .def_prop_ro("menu", nb::overload_cast<>(&ResourceDialog::menu, nb::const_), + "ordinal or name value of a menu resource"_doc) + + .def_prop_ro("window_class", nb::overload_cast<>(&ResourceDialog::window_class, nb::const_), + "ordinal of a predefined system window class or name of a registered window class"_doc + ) + + + LIEF_CLONABLE(ResourceDialog) + LIEF_DEFAULT_STR(ResourceDialog); +} +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogExtended.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogExtended.cpp new file mode 100644 index 0000000..db1546b --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogExtended.cpp @@ -0,0 +1,114 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceDialogExtended.hpp" + +#include +#include +#include +#include "nanobind/extra/stl/u16string.h" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ dialog(m, "ResourceDialogExtended", + R"delim( + Implementation for the new extended dialogbox format. + + See: https://learn.microsoft.com/en-us/windows/win32/dlgbox/dlgtemplateex + )delim"_doc); + + init_ref_iterator(dialog, "it_items"); + + nb::class_(dialog, "font_t", + R"doc( + Font information for the font to use for the text in the dialog box and + its controls + )doc"_doc + ) + .def_rw("point_size", &ResourceDialogExtended::font_t::point_size, + "The point size of the font"_doc) + .def_rw("weight", &ResourceDialogExtended::font_t::weight, + "The weight of the font"_doc) + .def_rw("italic", &ResourceDialogExtended::font_t::italic, + "Indicates whether the font is italic"_doc) + .def_rw("charset", &ResourceDialogExtended::font_t::charset, + "The character set to be used"_doc) + .def_rw("typeface", &ResourceDialogExtended::font_t::typeface, + "The name of the typeface for the font."_doc) + .def("__bool__", &ResourceDialogExtended::font_t::is_defined) + LIEF_DEFAULT_STR(ResourceDialogExtended::font_t); + + nb::class_(dialog, "Item", + R"doc( + This class represents a ``DLGTEMPLATEEX`` item (``DLGITEMTEMPLATEEX``). + + See: https://learn.microsoft.com/en-us/windows/win32/dlgbox/dlgitemtemplateex + )doc"_doc) + .def(nb::init<>()) + + .def_prop_rw("help_id", nb::overload_cast<>(&ResourceDialogExtended::Item::help_id, nb::const_), + nb::overload_cast(&ResourceDialogExtended::Item::help_id), + R"doc( + The help context identifier for the control. When the system sends a + ``WM_HELP`` message, it passes the ``helpID`` value in the ``dwContextId`` + member of the ``HELPINFO`` structure. + )doc"_doc + ) + + LIEF_DEFAULT_STR(ResourceDialogExtended::Item); + + dialog + .def(nb::init<>()) + .def_prop_ro("version", nb::overload_cast<>(&ResourceDialogExtended::version, nb::const_), + R"doc( + The version number of the extended dialog box template. This member must + be set to 1. + )doc"_doc) + + .def_prop_ro("signature", nb::overload_cast<>(&ResourceDialogExtended::signature, nb::const_), + R"doc( + Indicates whether a template is an extended dialog box template. + If signature is 0xFFFF, this is an extended dialog box template. + In this case, the dlgVer member specifies the template version number. + )doc"_doc) + + .def_prop_ro("help_id", nb::overload_cast<>(&ResourceDialogExtended::help_id, nb::const_), + R"doc( + The help context identifier for the dialog box window. When the system + sends a ``WM_HELP`` message, it passes the ``helpID`` value in the + ``dwContextId`` member of the ``HELPINFO`` structure. + )doc"_doc) + + .def_prop_ro("items", nb::overload_cast<>(&ResourceDialogExtended::items), + "Iterator over the different control items"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("font", nb::overload_cast<>(&ResourceDialogExtended::font, nb::const_), + "Additional font information"_doc) + + .def("add_item", &ResourceDialogExtended::add_item, + "item"_a, "Add a new control item to the dialog"_doc) + + LIEF_DEFAULT_STR(ResourceDialogExtended); + +} +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogRegular.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogRegular.cpp new file mode 100644 index 0000000..c79f8d0 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDialogRegular.cpp @@ -0,0 +1,82 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceDialogRegular.hpp" + +#include +#include +#include +#include "nanobind/extra/stl/u16string.h" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ dialog(m, "ResourceDialogRegular", + R"doc( + Implementation for a regular/legacy dialog box. + + See: https://learn.microsoft.com/en-us/windows/win32/api/winuser/ns-winuser-dlgtemplate + )doc"_doc); + + init_ref_iterator(dialog, "it_items"); + + nb::class_(dialog, "font_t", + R"doc( + This structure represents additional font information that might be + embedded at the end of the DLGTEMPLATE stream + )doc"_doc + ) + .def_rw("point_size", &ResourceDialogRegular::font_t::point_size) + .def_rw("name", &ResourceDialogRegular::font_t::name) + .def("__bool__", &ResourceDialogRegular::font_t::is_defined) + LIEF_DEFAULT_STR(ResourceDialogRegular::font_t); + + nb::class_(dialog, "Item", + R"doc( + This class represents a ``DLGTEMPLATE`` item (``DLGITEMTEMPLATE``) + See: https://learn.microsoft.com/en-us/windows/win32/api/winuser/ns-winuser-dlgitemtemplate + )doc"_doc) + .def(nb::init<>()) + + LIEF_DEFAULT_STR(ResourceDialogRegular::Item); + + dialog + .def(nb::init<>()) + + .def_prop_ro("nb_items", &ResourceDialogRegular::nb_items, + "Number of control items"_doc) + + .def_prop_ro("items", nb::overload_cast<>(&ResourceDialogRegular::items), + "Iterator over the different control items"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("font", nb::overload_cast<>(&ResourceDialogRegular::font, nb::const_), + "Additional font information"_doc) + + .def("add_item", &ResourceDialogRegular::add_item, + "item"_a, "Add a new control item to the dialog"_doc) + + + LIEF_DEFAULT_STR(ResourceDialogRegular); + + +} +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceDirectory.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDirectory.cpp new file mode 100644 index 0000000..715cfc9 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceDirectory.cpp @@ -0,0 +1,76 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/ResourceDirectory.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ResourceDirectory") + .def(nb::init<>(), + "Default constructor"_doc) + + .def(nb::init(), + "Constructor from an ID"_doc) + + .def_prop_rw("characteristics", + nb::overload_cast<>(&ResourceDirectory::characteristics, nb::const_), + nb::overload_cast(&ResourceDirectory::characteristics), + "Resource characteristics. This field is reserved for future use. " + "It is currently set to zero."_doc) + + .def_prop_rw("time_date_stamp", + nb::overload_cast<>(&ResourceDirectory::time_date_stamp, nb::const_), + nb::overload_cast(&ResourceDirectory::time_date_stamp), + "The time that the resource data was created by the " + "resource compiler."_doc) + + .def_prop_rw("major_version", + nb::overload_cast<>(&ResourceDirectory::major_version, nb::const_), + nb::overload_cast(&ResourceDirectory::major_version), + "The major version number, set by the user."_doc) + + .def_prop_rw("minor_version", + nb::overload_cast<>(&ResourceDirectory::minor_version, nb::const_), + nb::overload_cast(&ResourceDirectory::minor_version), + "The minor version number, set by the user."_doc) + + .def_prop_rw("numberof_name_entries", + nb::overload_cast<>(&ResourceDirectory::numberof_name_entries, nb::const_), + nb::overload_cast(&ResourceDirectory::numberof_name_entries), + "The number of directory entries immediately " + "following the table that use strings to identify Type, " + "Name, or Language entries (depending on the level " + "of the table"_doc) + + .def_prop_rw("numberof_id_entries", + nb::overload_cast<>(&ResourceDirectory::numberof_id_entries, nb::const_), + nb::overload_cast(&ResourceDirectory::numberof_id_entries), + "The number of directory entries immediately " + "following the Name entries that use numeric IDs for " + "Type, Name, or Language entries."_doc) + + LIEF_DEFAULT_STR(ResourceDirectory); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceIcon.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceIcon.cpp new file mode 100644 index 0000000..02c998a --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceIcon.cpp @@ -0,0 +1,103 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "nanobind/extra/stl/lief_span.h" +#include "nanobind/utils.hpp" + +#include "LIEF/PE/resources/ResourceIcon.hpp" +#include "pyErr.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ResourceIcon") + .def_prop_rw("id", + nb::overload_cast<>(&ResourceIcon::id, nb::const_), + nb::overload_cast(&ResourceIcon::id), + "Id associated with the icon"_doc) + + .def_prop_rw("lang", + nb::overload_cast<>(&ResourceIcon::lang, nb::const_), + nb::overload_cast(&ResourceIcon::lang), + "Language associated with the icon"_doc) + + .def_prop_rw("sublang", + nb::overload_cast<>(&ResourceIcon::sublang, nb::const_), + nb::overload_cast(&ResourceIcon::sublang), + "Sublanguage associated with the icon"_doc) + + .def_prop_rw("width", + nb::overload_cast<>(&ResourceIcon::width, nb::const_), + nb::overload_cast(&ResourceIcon::width), + "Width in pixels of the image"_doc) + + .def_prop_rw("height", + nb::overload_cast<>(&ResourceIcon::height, nb::const_), + nb::overload_cast(&ResourceIcon::height), + "Height in pixels of the image"_doc) + + .def_prop_rw("color_count", + nb::overload_cast<>(&ResourceIcon::color_count, nb::const_), + nb::overload_cast(&ResourceIcon::color_count), + "Number of colors in image (0 if >=8bpp)"_doc) + + .def_prop_rw("reserved", + nb::overload_cast<>(&ResourceIcon::reserved, nb::const_), + nb::overload_cast(&ResourceIcon::reserved), + "Reserved (must be 0)"_doc) + + .def_prop_rw("planes", + nb::overload_cast<>(&ResourceIcon::planes, nb::const_), + nb::overload_cast(&ResourceIcon::planes), + "Color Planes"_doc) + + .def_prop_rw("bit_count", + nb::overload_cast<>(&ResourceIcon::bit_count, nb::const_), + nb::overload_cast(&ResourceIcon::bit_count), + "Bits per pixel"_doc) + + .def_prop_rw("pixels", + nb::overload_cast<>(&ResourceIcon::pixels, nb::const_), + nb::overload_cast>(&ResourceIcon::pixels)) + + .def("save", &ResourceIcon::save, + "Save the icon to the given filepath"_doc, + "filepath"_a) + + .def("serialize", [] (ResourceIcon& self) { + return nb::to_bytes(self.serialize()); + }, + "Serialize the current icon into bytes"_doc) + + .def_static("from_serialization", [] (nb::bytes bytes) { + return LIEF::py::error_or( + nb::overload_cast(&ResourceIcon::from_serialization), + (const uint8_t*)bytes.data(), bytes.size()); + }, + "Create an icon instance from the serialized bytes"_doc) + + LIEF_DEFAULT_STR(ResourceIcon); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceNode.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceNode.cpp new file mode 100644 index 0000000..5d68ca6 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceNode.cpp @@ -0,0 +1,125 @@ + +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pySafeString.hpp" + +#include "LIEF/utils.hpp" +#include "LIEF/PE/ResourceNode.hpp" +#include "LIEF/PE/ResourceData.hpp" +#include "LIEF/PE/ResourceDirectory.hpp" + +#include +#include + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ res_node(m, "ResourceNode", + R"delim( + Class which represents a Node in the resource tree. + + It is extended by :class:`lief.PE.ResourceData` and :class:`lief.PE.ResourceDirectory` + )delim"_doc); + + init_ref_iterator(res_node, "it_childs"); + + res_node + .def_static("parse", [] (nb::bytes bytes, uint64_t rva) { + return ResourceNode::parse((const uint8_t*)bytes.data(), bytes.size(), rva); + }, + R"doc( + Parse the resource tree from the provided bytes and + with the original RVA provided in the second parameter. + + The RVA value should be come from the :attr:`lief.PE.DataDirectory.rva` associated with + the resource tree. + )doc"_doc, + "bytes"_a, "rva"_a, nb::rv_policy::take_ownership + ) + + .def_prop_rw("id", + nb::overload_cast<>(&ResourceNode::id, nb::const_), + nb::overload_cast(&ResourceNode::id), + "Integer that identifies the Type, Name, or Language ID entry."_doc + ) + + .def_prop_ro("is_directory", &ResourceNode::is_directory, + "``True`` if the current node is a :class:`~.ResourceDirectory`"_doc + ) + + .def_prop_ro("is_data", &ResourceNode::is_data, + "``True`` if the current node is a :class:`~.ResourceData`"_doc + ) + + .def_prop_ro("has_name", &ResourceNode::has_name, + "``True`` if the current node uses a name"_doc + ) + + .def_prop_rw("name", + &ResourceNode::utf8_name, + nb::overload_cast(&ResourceNode::name), + "Resource's name"_doc + ) + + .def_prop_ro("childs", nb::overload_cast<>(&ResourceNode::childs), + "Node's children"_doc, nb::keep_alive<0, 1>() + ) + + .def("add_child", + nb::overload_cast(&ResourceNode::add_child), + "Add a new child to the current node"_doc, + "node"_a, nb::rv_policy::reference_internal + ) + + .def("delete_child", + nb::overload_cast(&ResourceNode::delete_child), + "Delete the given :class:`~.ResourceNode` from the current children"_doc, + "node"_a + ) + + .def("delete_child", + nb::overload_cast(&ResourceNode::delete_child), + R"doc( + Delete the :class:`~.ResourceNode` with the given :attr:`~.ResourceNode.id` + from the current children + )doc"_doc, "id"_a + ) + + .def_prop_ro("depth", &ResourceNode::depth, + "Current depth of the node in the resource tree"_doc + ) + + .def("__eq__", [] (const ResourceNode& lhs, const ResourceNode& rhs) { + return lhs == rhs; + }, nb::is_operator()) + + .def("__ne__", [] (const ResourceNode& lhs, const ResourceNode& rhs) { + return lhs != rhs; + }, nb::is_operator()) + + LIEF_CLONABLE(ResourceNode) + LIEF_DEFAULT_STR(ResourceNode); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringFileInfo.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringFileInfo.cpp new file mode 100644 index 0000000..8bf0c16 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringFileInfo.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceStringFileInfo.hpp" +#include "LIEF/PE/resources/ResourceStringTable.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "ResourceStringFileInfo", + R"delim( + Representation of the ``StringFileInfo`` structure + + See: https://docs.microsoft.com/en-us/windows/win32/menurc/stringfileinfo + )delim"_doc); + + LIEF::py::init_ref_iterator(obj, "it_elements"); + + obj + .def_prop_ro("type", nb::overload_cast<>(&ResourceStringFileInfo::type, nb::const_), + R"doc( + The type of data in the version resource: + * ``1`` if it contains text data + * ``0`` if it contains binary data + )doc"_doc + ) + + .def_prop_ro("key", nb::overload_cast<>(&ResourceStringFileInfo::key_u8, nb::const_), + R"doc(Signature of the structure. Must be the unicode string "StringFileInfo")doc"_doc + ) + + .def_prop_ro("children", nb::overload_cast<>(&ResourceStringFileInfo::children), + "Iterator over the children values"_doc + ) + + LIEF_DEFAULT_STR(ResourceStringFileInfo); +} +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringTable.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringTable.cpp new file mode 100644 index 0000000..6390d74 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceStringTable.cpp @@ -0,0 +1,82 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceStringTable.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using entry_t = ResourceStringTable::entry_t; + nb::class_ obj(m, "ResourceStringTable", + R"doc( + This class represents the ``StringTable`` structure. This structure + can be seen as a dictionary of key, values with key and values defined as + utf-16 strings. + )doc"_doc + ); + + LIEF::py::init_ref_iterator(obj, "it_entries"); + + nb::class_(obj, "entry_t", + R"doc( + An entry in this table which is composed of an UTF-16 key and an UTF-16 + value. + )doc"_doc + ) + .def_rw("key", &entry_t::key) + .def_rw("value", &entry_t::value) + .def("__bool__", &entry_t::is_defined) + ; + + obj + .def_prop_ro("key", &ResourceStringTable::key_u8, + R"doc( + An 8-digit hexadecimal number stored as a Unicode string. The four most + significant digits represent the language identifier. The four least + significant digits represent the code page for which the data is formatted. + Each Microsoft Standard Language identifier contains two parts: + the low-order 10 bits specify the major language, and the high-order 6 + bits specify the sublanguage. + )doc"_doc + ) + .def_prop_ro("type", nb::overload_cast<>(&ResourceStringTable::type, nb::const_), + R"doc( + The type of data in the version resource: + * ``1`` if it contains text data + * ``0`` if it contains binary data + )doc"_doc + ) + .def_prop_ro("entries", nb::overload_cast<>(&ResourceStringTable::entries), + R"doc(Iterator over the different :class:`~.entry_t` in this table)doc"_doc + ) + + .def("get", nb::overload_cast(&ResourceStringTable::get, nb::const_), + "key"_a) + + .def("__getitem__", nb::overload_cast(&ResourceStringTable::get, nb::const_), + "key") + ; +} +} diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceVar.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVar.cpp new file mode 100644 index 0000000..88cea8e --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVar.cpp @@ -0,0 +1,67 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceVar.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "ResourceVar", + R"doc( + This class represents an element of the :class:`~.ResourceVarFileInfo` structure + It typically contains a list of language and code page identifier pairs that + the version of the application or DLL supports. + + See: https://learn.microsoft.com/en-us/windows/win32/menurc/var-str + )doc"_doc + ); + obj + .def_prop_ro("type", nb::overload_cast<>(&ResourceVar::type, nb::const_), + R"doc( + The type of data in the version resource: + * ``1`` if it contains text data + * ``0`` if it contains binary data + )doc"_doc + ) + .def_prop_ro("key", nb::overload_cast<>(&ResourceVar::key_u8, nb::const_), + R"doc(Signature of the structure. Must be the unicode string "Translation")doc"_doc + ) + + .def_prop_ro("values", nb::overload_cast<>(&ResourceVar::values, nb::const_), + R"doc( + Return the translation values. + + The low-order word of each uint32_t must contain a Microsoft language + identifier, and the high-order word must contain the IBM code page number. + Either high-order or low-order word can be zero, indicating that the file + is language or code page independent + )doc"_doc + ) + + LIEF_DEFAULT_STR(ResourceVar); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceVarFileInfo.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVarFileInfo.cpp new file mode 100644 index 0000000..270be2c --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVarFileInfo.cpp @@ -0,0 +1,68 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/resources/ResourceVarFileInfo.hpp" +#include "LIEF/PE/resources/ResourceVar.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "ResourceVarFileInfo", + R"doc( + Representation of the ``VarFileInfo`` structure + + This structure represents the organization of data in a file-version resource. + It contains version information not dependent on a particular language and + code page combination. + + See: https://learn.microsoft.com/en-us/windows/win32/menurc/varfileinfo + )doc"_doc + ); + LIEF::py::init_ref_iterator(obj, "it_vars"); + + obj + .def_prop_ro("type", nb::overload_cast<>(&ResourceVarFileInfo::type, nb::const_), + R"doc( + The type of data in the version resource: + * ``1`` if it contains text data + * ``0`` if it contains binary data + )doc"_doc + ) + + .def_prop_ro("key", nb::overload_cast<>(&ResourceVarFileInfo::key_u8, nb::const_), + R"doc(Signature of the structure. Must be the unicode string "VarFileInfo")doc"_doc + ) + + .def_prop_ro("vars", nb::overload_cast<>(&ResourceVarFileInfo::vars), + R"doc(Iterator over the embedded variables associated to the structure)doc"_doc + ) + + LIEF_DEFAULT_STR(ResourceVarFileInfo); + + +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/resources/pyResourceVersion.cpp b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVersion.cpp new file mode 100644 index 0000000..3b77bff --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/resources/pyResourceVersion.cpp @@ -0,0 +1,236 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/resources/ResourceVersion.hpp" +#include "LIEF/PE/resources/ResourceVarFileInfo.hpp" +#include "LIEF/PE/resources/ResourceStringFileInfo.hpp" + +#include +#include + +#include +#include +#include +#include + +namespace LIEF::PE::py { + +void create_fixed_file_info_t(nb::handle m) { + using fixed_file_info_t = ResourceVersion::fixed_file_info_t; + + nb::class_ finfo(m, "fixed_file_info_t", + R"doc( + This structure represents the ``VS_FIXEDFILEINFO`` structure defined + in ``verrsrc.h``. + )doc"_doc + ); + + nb::enum_(finfo, "VERSION_OS") + #define ENTRY(X) .value(to_string(fixed_file_info_t::VERSION_OS::X), fixed_file_info_t::VERSION_OS::X) + ENTRY(DOS_WINDOWS16) + ENTRY(DOS_WINDOWS32) + ENTRY(NT) + ENTRY(NT_WINDOWS32) + ENTRY(OS216) + ENTRY(OS216_PM16) + ENTRY(OS232) + ENTRY(OS232_PM32) + ENTRY(PM16) + ENTRY(PM32) + ENTRY(UNKNOWN) + ENTRY(WINCE) + ENTRY(WINDOWS16) + ENTRY(WINDOWS32) + #undef ENTRY + ; + + nb::enum_(finfo, "FILE_TYPE") + #define ENTRY(X) .value(to_string(fixed_file_info_t::FILE_TYPE::X), fixed_file_info_t::FILE_TYPE::X) + ENTRY(UNKNOWN) + ENTRY(APP) + ENTRY(DLL) + ENTRY(DRV) + ENTRY(FONT) + ENTRY(STATIC_LIB) + ENTRY(VXD) + #undef ENTRY + ; + + nb::enum_(finfo, "FILE_FLAGS") + #define ENTRY(X) .value(to_string(fixed_file_info_t::FILE_FLAGS::X), fixed_file_info_t::FILE_FLAGS::X) + ENTRY(DEBUG) + ENTRY(INFO_INFERRED) + ENTRY(PATCHED) + ENTRY(PRERELEASE) + ENTRY(PRIVATEBUILD) + ENTRY(SPECIALBUILD) + #undef ENTRY + ; + + nb::enum_(finfo, "FILE_TYPE_DETAILS") + #define ENTRY(X) .value(to_string(fixed_file_info_t::FILE_TYPE_DETAILS::X), fixed_file_info_t::FILE_TYPE_DETAILS::X) + ENTRY(DRV_COMM) + ENTRY(DRV_DISPLAY) + ENTRY(DRV_INPUTMETHOD) + ENTRY(DRV_INSTALLABLE) + ENTRY(DRV_KEYBOARD) + ENTRY(DRV_LANGUAGE) + ENTRY(DRV_MOUSE) + ENTRY(DRV_NETWORK) + ENTRY(DRV_PRINTER) + ENTRY(DRV_SOUND) + ENTRY(DRV_SYSTEM) + ENTRY(DRV_VERSIONED_PRINTER) + ENTRY(FONT_RASTER) + ENTRY(FONT_TRUETYPE) + ENTRY(FONT_VECTOR) + ENTRY(UNKNOWN) + #undef ENTRY + ; + finfo + .def_rw("signature", &fixed_file_info_t::signature, + R"doc( + Contains the value ``0xFEEF04BD``. This is used with the ``szKey`` member of + the ``VS_VERSIONINFO`` structure when searching a file for the + ``VS_FIXEDFILEINFO`` structure. + )doc"_doc) + + .def_rw("struct_version", &fixed_file_info_t::struct_version, + R"doc( + The binary version number of this structure. The high-order word of + this member contains the major version number, and the low-order word + contains the minor version number. + )doc"_doc) + + .def_rw("file_version_ms", &fixed_file_info_t::file_version_ms, + R"doc( + The most significant 32 bits of the file's binary version number. + This member is used with :attr:`~.file_version_ls` to form a 64-bit value + used for numeric comparisons. + )doc"_doc) + + .def_rw("file_version_ls", &fixed_file_info_t::file_version_ls, + R"doc( + The least significant 32 bits of the file's binary version number. + This member is used with :attr:`~.file_version_ms` to form a 64-bit value + used for numeric comparisons. + )doc"_doc) + + .def_rw("product_version_ms", &fixed_file_info_t::product_version_ms, + R"doc( + The most significant 32 bits of the binary version number of the product + with which this file was distributed. This member is used with + :attr:`~.product_version_ls` to form a 64-bit value used for numeric + comparisons. + )doc"_doc) + + .def_rw("product_version_ls", &fixed_file_info_t::product_version_ls, + R"doc( + The least significant 32 bits of the binary version number of the product + with which this file was distributed. This member is used with + :attr:`~.product_version_ms` to form a 64-bit value used for numeric + comparisons. + )doc"_doc) + + .def_rw("file_flags_mask", &fixed_file_info_t::file_flags_mask, + R"doc( + Contains a bitmask that specifies the valid bits in file_flags. + A bit is valid only if it was defined when the file was created. + )doc"_doc) + + .def_rw("file_flags", &fixed_file_info_t::file_flags, + R"doc( + Contains a bitmask that specifies the Boolean attributes of the file. + This member can include one or more of the values specified in + :class:`~.FILE_FLAGS`. + )doc"_doc) + + .def_rw("file_os", &fixed_file_info_t::file_os, + R"doc( + The operating system for which this file was designed. This member can + be one of the values specified in :class:`~.VERSION_OS`. + )doc"_doc) + + .def_rw("file_type", &fixed_file_info_t::file_type, + R"doc( + The general type of file. This member can be one of the values specified + in :class:`~.FILE_TYPE`. All other values are reserved. + )doc"_doc) + + .def_rw("file_subtype", &fixed_file_info_t::file_subtype, + R"doc( + The function of the file. The possible values depend on the value of + file_type. + )doc"_doc) + + .def_rw("file_date_ms", &fixed_file_info_t::file_date_ms, + R"doc( + The most significant 32 bits of the file's 64-bit binary creation date + and time stamp. + )doc"_doc) + + .def_rw("file_date_ls", &fixed_file_info_t::file_date_ls, + R"doc( + The least significant 32 bits of the file's 64-bit binary creation date + and time stamp. + )doc"_doc) + + .def("has", &fixed_file_info_t::has, + "Check if the given flag is present"_doc, "flag"_a) + + .def_prop_ro("flags", &fixed_file_info_t::flags, + "List of flags"_doc) + + .def_prop_ro("file_type_details", &fixed_file_info_t::file_type_details) + + LIEF_DEFAULT_STR(fixed_file_info_t); +} + +template<> +void create(nb::module_& m) { + nb::class_ rv(m, "ResourceVersion", + R"delim( + Class that represents the data associated with the ``RT_VERSION`` entry + + See: VS_VERSIONINFO -- https://docs.microsoft.com/en-us/windows/win32/menurc/vs-versioninfo + )delim"_doc); + + create_fixed_file_info_t(rv); + + rv + .def_prop_ro("key", nb::overload_cast<>(&ResourceVersion::key, nb::const_), + R"doc(The Unicode string `L"VS_VERSION_INFO"`")doc"_doc) + .def_prop_ro("type", nb::overload_cast<>(&ResourceVersion::type, nb::const_), + R"doc( + The type of data in the version resource: + * ``1`` if it contains text data + * ``0`` if it contains binary data + )doc"_doc) + + .def_prop_ro("file_info", nb::overload_cast<>(&ResourceVersion::file_info, nb::const_), + "Return the fixed file info (``VS_FIXEDFILEINFO``)"_doc) + + .def_prop_ro("string_file_info", nb::overload_cast<>(&ResourceVersion::string_file_info, nb::const_), + "Return the ``StringFileInfo`` element"_doc) + + .def_prop_ro("var_file_info", nb::overload_cast<>(&ResourceVersion::var_file_info, nb::const_), + "Return the ``VarFileInfo`` element"_doc) + LIEF_DEFAULT_STR(ResourceVersion); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/signature/CMakeLists.txt new file mode 100644 index 0000000..cfb9006 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/CMakeLists.txt @@ -0,0 +1,12 @@ +target_sources(pyLIEF PRIVATE + pyAttribute.cpp + pyContentInfo.cpp + pyGenericContent.cpp + pyPKCS9TSTInfo.cpp + pyRsaInfo.cpp + pySignature.cpp + pySignerInfo.cpp + pySpcIndirectData.cpp + pyx509.cpp +) +add_subdirectory(attributes) diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/CMakeLists.txt b/vendor/lief/api/python/src/PE/objects/signature/attributes/CMakeLists.txt new file mode 100644 index 0000000..64ee411 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/CMakeLists.txt @@ -0,0 +1,15 @@ +target_sources(pyLIEF PRIVATE + pyContentType.cpp + pyGenericType.cpp + pyMsCounterSign.cpp + pyMsManifestBinaryID.cpp + pyMsSpcNestedSignature.cpp + pyMsSpcStatementType.cpp + pyPKCS9AtSequenceNumber.cpp + pyPKCS9CounterSignature.cpp + pyPKCS9MessageDigest.cpp + pyPKCS9SigningTime.cpp + pySpcRelaxedPeMarkerCheck.cpp + pySigningCertificateV2.cpp + pySpcSpOpusInfo.cpp +) diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyContentType.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyContentType.cpp new file mode 100644 index 0000000..7e20749 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyContentType.cpp @@ -0,0 +1,43 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/ContentType.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "ContentType", + R"delim( + Interface over the structure described by the OID ``1.2.840.113549.1.9.3`` (PKCS #9) + The internal structure is described in the: + `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ + + .. code-block:: text + + ContentType ::= OBJECT IDENTIFIER + + )delim"_doc) + .def_prop_ro("oid", + &ContentType::oid, "OID as described in RFC #2985 (string object)"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyGenericType.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyGenericType.cpp new file mode 100644 index 0000000..e7b869d --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyGenericType.cpp @@ -0,0 +1,44 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/Attribute.hpp" +#include "LIEF/PE/signature/attributes/GenericType.hpp" + +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "GenericType", + R"delim( + Interface over an attribute for which the internal structure is not supported by LIEF + )delim"_doc) + .def_prop_ro("oid", + &GenericType::oid, + "OID of the original attribute"_doc) + + .def_prop_ro("raw_content", + [] (const GenericType& type) { + return nb::to_memoryview(type.raw_content()); + }, "Original DER blob of the attribute"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsCounterSign.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsCounterSign.cpp new file mode 100644 index 0000000..e83c050 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsCounterSign.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +#include "LIEF/PE/signature/attributes/MsCounterSign.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ CounterSig(m, "MsCounterSign", + R"delim( + This class exposes the ms-counter-signature. + )delim"_doc); + + init_ref_iterator(CounterSig, "it_const_crt"); + init_ref_iterator(CounterSig, "it_const_signers_t"); + + CounterSig + .def_prop_ro("version", &MsCounterSign::version) + .def_prop_ro("digest_algorithm", &MsCounterSign::digest_algorithm) + .def_prop_ro("content_info", &MsCounterSign::content_info) + .def_prop_ro("certificates", + nb::overload_cast<>(&MsCounterSign::certificates), + "Return an iterator over " RST_CLASS_REF(lief.PE.x509) " certificates"_doc, + nb::keep_alive<0, 1>()) + .def_prop_ro("signers", + nb::overload_cast<>(&MsCounterSign::signers), + "Return an iterator over the signers (" RST_CLASS_REF(lief.PE.SignerInfo) ")"_doc, + nb::keep_alive<0, 1>()); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsManifestBinaryID.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsManifestBinaryID.cpp new file mode 100644 index 0000000..209ea14 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsManifestBinaryID.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/MsManifestBinaryID.hpp" +#include +#include + +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "MsManifestBinaryID", + R"delim( + Interface over the structure described by the OID ``1.3.6.1.4.1.311.10.3.28`` (``szOID_PLATFORM_MANIFEST_BINARY_ID``) + + The internal structure is not documented but we can infer the following structure: + + .. code-block:: text + + szOID_PLATFORM_MANIFEST_BINARY_ID ::= SET OF BinaryID + + BinaryID ::= UTF8STRING + + )delim") + + .def_prop_rw("manifest_id", + nb::overload_cast<>(&MsManifestBinaryID::manifest_id, nb::const_), + nb::overload_cast(&MsManifestBinaryID::manifest_id), + "The manifest id") + LIEF_DEFAULT_STR(MsManifestBinaryID); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp new file mode 100644 index 0000000..45b5ebf --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcNestedSignature.cpp @@ -0,0 +1,46 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/MsSpcNestedSignature.hpp" + +#include +#include + +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "MsSpcNestedSignature", + R"delim( + Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.4.1`` + + The internal structure is not documented but we can infer the following structure: + + .. code-block:: text + + MsSpcNestedSignature ::= SET OF SignedData + + With ``SignedData``, the structure described in PKCS #7 RFC (See: :class:`lief.PE.Signature`) + )delim"_doc) + .def_prop_ro("signature", &MsSpcNestedSignature::sig, + "Underlying " RST_CLASS_REF(lief.PE.Signature) " object"_doc, + nb::rv_policy::reference_internal); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcStatementType.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcStatementType.cpp new file mode 100644 index 0000000..29672c8 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyMsSpcStatementType.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/MsSpcStatementType.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "MsSpcStatementType", + R"delim( + Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.1.11`` + + The internal structure is described in the official document: + `Windows Authenticode Portable Executable Signature Format `_ + + .. code-block:: text + + SpcStatementType ::= SEQUENCE of OBJECT IDENTIFIER + + )delim"_doc) + + .def_prop_ro("oid", + &MsSpcStatementType::oid, + R"delim( + According to the documentation: + + :: + + The SpcStatementType MUST contain one Object Identifier with either + the value ``1.3.6.1.4.1.311.2.1.21 (SPC_INDIVIDUAL_SP_KEY_PURPOSE_OBJID)`` or + ``1.3.6.1.4.1.311.2.1.22 (SPC_COMMERCIAL_SP_KEY_PURPOSE_OBJID)``. + )delim"_doc); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp new file mode 100644 index 0000000..43c91a5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9AtSequenceNumber.cpp @@ -0,0 +1,52 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/PKCS9AtSequenceNumber.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PKCS9AtSequenceNumber", + R"delim( + Interface over the structure described by the OID ``1.2.840.113549.1.9.25.4`` (PKCS #9) + + The internal structure is described in the + `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ + + .. code-block:: text + + sequenceNumber ATTRIBUTE ::= { + WITH SYNTAX SequenceNumber + EQUALITY MATCHING RULE integerMat + SINGLE VALUE TRUE + ID pkcs-9-at-sequenceNumber + } + + SequenceNumber ::= INTEGER (1..MAX) + + )delim"_doc) + + .def_prop_ro("number", + &PKCS9AtSequenceNumber::number, + "Number as described in the RFC"_doc); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp new file mode 100644 index 0000000..238b0fe --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9CounterSignature.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/PKCS9CounterSignature.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PKCS9CounterSignature", + R"delim( + Interface over the structure described by the OID ``1.2.840.113549.1.9.6`` (PKCS #9) + + The internal structure is described in the + `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ + + .. code-block:: text + + counterSignature ATTRIBUTE ::= { + WITH SYNTAX SignerInfo + ID pkcs-9-at-counterSignature + } + + )delim"_doc) + .def_prop_ro("signer", + &PKCS9CounterSignature::signer, + "Return the " RST_CLASS_REF(lief.PE.SignerInfo) " as described in the RFC #2985"_doc, + nb::rv_policy::reference_internal); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp new file mode 100644 index 0000000..5cb94f9 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9MessageDigest.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/PKCS9MessageDigest.hpp" + +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PKCS9MessageDigest", + R"delim( + Interface over the structure described by the OID ``1.2.840.113549.1.9.4`` (PKCS #9) + + The internal structure is described in the + `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ + + .. code-block:: text + + messageDigest ATTRIBUTE ::= { + WITH SYNTAX MessageDigest + EQUALITY MATCHING RULE octet + SINGLE VALUE TRUE + ID pkcs-9-at-messageDigest + } + + MessageDigest ::= OCTET STRING + + )delim"_doc) + + .def_prop_ro("digest", + [] (const PKCS9MessageDigest& digest) { + return nb::to_bytes(digest.digest()); + }, "Message digest as a blob of bytes as described in the RFC"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp new file mode 100644 index 0000000..5d4a5c5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pyPKCS9SigningTime.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/PKCS9SigningTime.hpp" + +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PKCS9SigningTime", + R"delim( + Interface over the structure described by the OID ``1.2.840.113549.1.9.5`` (PKCS #9) + + The internal structure is described in the + `RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 `_ + + .. code-block:: text + + signingTime ATTRIBUTE ::= { + WITH SYNTAX SigningTime + EQUALITY MATCHING RULE signingTimeMatch + SINGLE VALUE TRUE + ID pkcs-9-at-signingTime + } + + SigningTime ::= Time -- imported from ISO/IEC 9594-8 + + )delim"_doc) + + .def_prop_ro("time", &PKCS9SigningTime::time, + "Time as a list [year, month, day, hour, min, sec]"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pySigningCertificateV2.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySigningCertificateV2.cpp new file mode 100644 index 0000000..b87415c --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySigningCertificateV2.cpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/SigningCertificateV2.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SigningCertificateV2", + R"doc( + .. code-block:: text + + SigningCertificateV2 ::= SEQUENCE { + certs SEQUENCE OF ESSCertIDv2, + policies SEQUENCE OF PolicyInformation OPTIONAL + } + + ESSCertIDv2 ::= SEQUENCE { + hashAlgorithm AlgorithmIdentifier DEFAULT {algorithm id-sha256}, + certHash OCTET STRING, + issuerSerial IssuerSerial OPTIONAL + } + + IssuerSerial ::= SEQUENCE { + issuer GeneralNames, + serialNumber CertificateSerialNumber + } + + PolicyInformation ::= SEQUENCE { + policyIdentifier OBJECT IDENTIFIER, + policyQualifiers SEQUENCE SIZE (1..MAX) OF PolicyQualifierInfo OPTIONAL + } + )doc"_doc + ) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcRelaxedPeMarkerCheck.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcRelaxedPeMarkerCheck.cpp new file mode 100644 index 0000000..64210d6 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcRelaxedPeMarkerCheck.cpp @@ -0,0 +1,32 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SpcRelaxedPeMarkerCheck", + R"delim( + )delim"_doc + ) + .def_prop_ro("value", nb::overload_cast<>(&SpcRelaxedPeMarkerCheck::value, nb::const_)) + ; +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp new file mode 100644 index 0000000..9af33ac --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/attributes/pySpcSpOpusInfo.cpp @@ -0,0 +1,55 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +#include "LIEF/PE/signature/attributes/SpcSpOpusInfo.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SpcSpOpusInfo", + R"delim( + Interface over the structure described by the OID ``1.3.6.1.4.1.311.2.1.12`` + The internal structure is described in the official document: `Windows Authenticode Portable Executable Signature Format `_ + + .. code-block:: text + + SpcSpOpusInfo ::= SEQUENCE { + programName [0] EXPLICIT SpcString OPTIONAL, + moreInfo [1] EXPLICIT SpcLink OPTIONAL + } + )delim"_doc + ) + .def_prop_ro("program_name", + [] (const SpcSpOpusInfo& info) { + return LIEF::py::safe_string(info.program_name()); + }, + "Program description provided by the publisher"_doc) + + .def_prop_ro("more_info", + [] (const SpcSpOpusInfo& info) { + return LIEF::py::safe_string(info.more_info()); + }, + "Other information such as an URL"_doc); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyAttribute.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyAttribute.cpp new file mode 100644 index 0000000..03f79b5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyAttribute.cpp @@ -0,0 +1,58 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/Attribute.hpp" + +#include +#include +#include "enums_wrapper.hpp" +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ Class(m, + "Attribute", "Interface over PKCS #7 attribute"_doc + ); + + #define ENTRY(X) .value(to_string(Attribute::TYPE::X), Attribute::TYPE::X) + enum_(Class, "TYPE") + ENTRY(UNKNOWN) + ENTRY(CONTENT_TYPE) + ENTRY(GENERIC_TYPE) + ENTRY(SPC_SP_OPUS_INFO) + ENTRY(MS_COUNTER_SIGN) + ENTRY(MS_SPC_NESTED_SIGN) + ENTRY(MS_SPC_STATEMENT_TYPE) + ENTRY(SPC_RELAXED_PE_MARKER_CHECK) + ENTRY(SIGNING_CERTIFICATE_V2) + ENTRY(MS_PLATFORM_MANIFEST_BINARY_ID) + ENTRY(PKCS9_AT_SEQUENCE_NUMBER) + ENTRY(PKCS9_COUNTER_SIGNATURE) + ENTRY(PKCS9_MESSAGE_DIGEST) + ENTRY(PKCS9_SIGNING_TIME) + ; + #undef ENTRY + + Class + .def_prop_ro("type", &Attribute::type, + "Concrete type of the attribute"_doc) + + LIEF_DEFAULT_STR(Attribute); +} +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyContentInfo.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyContentInfo.cpp new file mode 100644 index 0000000..f2e254c --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyContentInfo.cpp @@ -0,0 +1,111 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/ContentInfo.hpp" +#include "LIEF/PE/signature/SpcIndirectData.hpp" +#include "LIEF/PE/signature/GenericContent.hpp" + +#include +#include +#include +#include + +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + + nb::class_ info(m, "ContentInfo", + R"delim( + ContentInfo as described in the `RFC 2315 `_ + + .. code-block:: text + + ContentInfo ::= SEQUENCE { + contentType ContentType, + content [0] EXPLICIT ANY DEFINED BY contentType OPTIONAL + } + + ContentType ::= OBJECT IDENTIFIER + + In the case of PE signature, ContentType **must** be set to SPC_INDIRECT_DATA_OBJID + OID: ``1.3.6.1.4.1.311.2.1.4`` and content is defined by the structure: ``SpcIndirectDataContent`` + + .. code-block:: text + + SpcIndirectDataContent ::= SEQUENCE { + data SpcAttributeTypeAndOptionalValue, + messageDigest DigestInfo + } + + SpcAttributeTypeAndOptionalValue ::= SEQUENCE { + type ObjectID, + value [0] EXPLICIT ANY OPTIONAL + } + + For PE signature, ``SpcAttributeTypeAndOptionalValue.type`` + is set to ``SPC_PE_IMAGE_DATAOBJ`` (OID: ``1.3.6.1.4.1.311.2.1.15``) and the value is defined by + ``SpcPeImageData`` + + .. code-block:: text + + DigestInfo ::= SEQUENCE { + digestAlgorithm AlgorithmIdentifier, + digest OCTETSTRING + } + + AlgorithmIdentifier ::= SEQUENCE { + algorithm ObjectID, + parameters [0] EXPLICIT ANY OPTIONAL + } + )delim"_doc); + + nb::class_ content(info, "Content"); + content + .def_prop_ro("content_type", + &ContentInfo::Content::content_type, + "OID of the content type. This value should match ``SPC_INDIRECT_DATA_OBJID``"_doc) + LIEF_CLONABLE(ContentInfo::Content); + + info + .def_prop_ro("content_type", + &ContentInfo::content_type, + "An alias for :attr:`~.ContentInfo.content_type`"_doc) + + .def_prop_ro("digest", + [] (const ContentInfo& self) -> nb::bytes { + return nb::to_bytes(self.digest()); + }, + R"delim( + Return the digest (authentihash) if the underlying content type is + ``SPC_INDIRECT_DATA_OBJID``. Return empty bytes otherwise. + )delim"_doc + ) + .def_prop_ro("digest_algorithm", &ContentInfo::digest_algorithm, + "Return the hash algorithm used to generate the :attr:`.digest`"_doc) + + .def_prop_ro("value", nb::overload_cast<>(&ContentInfo::value), + nb::rv_policy::reference_internal) + + LIEF_COPYABLE(ContentInfo) + LIEF_DEFAULT_STR(ContentInfo); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyGenericContent.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyGenericContent.cpp new file mode 100644 index 0000000..461cfbf --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyGenericContent.cpp @@ -0,0 +1,34 @@ + +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/GenericContent.hpp" + +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "GenericContent"); + +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyPKCS9TSTInfo.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyPKCS9TSTInfo.cpp new file mode 100644 index 0000000..703e7b2 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyPKCS9TSTInfo.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/PKCS9TSTInfo.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PKCS9TSTInfo", + R"doc( + Interface over the structure described by the OID ``1.2.840.113549.1.9.16.1.4`` (PKCS #9) + + The internal structure is described in the `RFC #3161 `_ + + .. code-block:: text + + TSTInfo ::= SEQUENCE { + version INTEGER { v1(1) }, + policy TSAPolicyId, + messageImprint MessageImprint, + serialNumber INTEGER, + genTime GeneralizedTime, + accuracy Accuracy OPTIONAL, + ordering BOOLEAN DEFAULT FALSE, + nonce INTEGER OPTIONAL, + tsa [0] GeneralName OPTIONAL, + extensions [1] IMPLICIT Extensions OPTIONAL + } + + TSAPolicyId ::= OBJECT IDENTIFIER + MessageImprint ::= SEQUENCE { + hashAlgorithm AlgorithmIdentifier, + hashedMessage OCTET STRING + } + + Accuracy ::= SEQUENCE { + seconds INTEGER OPTIONAL, + millis [0] INTEGER (1..999) OPTIONAL, + micros [1] INTEGER (1..999) OPTIONAL + } + )doc"_doc + ); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyRsaInfo.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyRsaInfo.cpp new file mode 100644 index 0000000..4d1144a --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyRsaInfo.cpp @@ -0,0 +1,74 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/RsaInfo.hpp" + +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + + nb::class_(m, "RsaInfo", "Object representing a RSA key") + .def_prop_ro("has_public_key", + &RsaInfo::has_public_key, + "True if it embeds a public key"_doc) + + .def_prop_ro("has_private_key", + &RsaInfo::has_private_key, + "True if it embeds a private key"_doc) + + .def_prop_ro("N", + [] (const RsaInfo& info) { + return nb::to_bytes(info.N()); + }, + "RSA public modulus (in bytes)"_doc) + + .def_prop_ro("E", + [] (const RsaInfo& info) { + return nb::to_bytes(info.E()); + }, "RSA public exponent (in bytes)"_doc) + + .def_prop_ro("D", + [] (const RsaInfo& info) { + return nb::to_bytes(info.D()); + }, "RSA private exponent (in bytes)"_doc) + + .def_prop_ro("P", + [] (const RsaInfo& info) { + return nb::to_bytes(info.P()); + }, "First prime factor (in bytes)"_doc) + + .def_prop_ro("Q", + [] (const RsaInfo& info) { + return nb::to_bytes(info.Q()); + }, "Second prime factor (in bytes)") + + .def_prop_ro("key_size", + &RsaInfo::key_size, "Size of the public modulus in bits"_doc) + + .def_prop_ro("__len__", &RsaInfo::key_size) + + LIEF_DEFAULT_STR(RsaInfo); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/pySignature.cpp b/vendor/lief/api/python/src/PE/objects/signature/pySignature.cpp new file mode 100644 index 0000000..2898938 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pySignature.cpp @@ -0,0 +1,205 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include "nanobind/extra/stl/pathlike.h" +#include "nanobind/utils.hpp" + +#include "enums_wrapper.hpp" + +#include "LIEF/PE/signature/Signature.hpp" +#include "LIEF/PE/signature/SignatureParser.hpp" + +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ signature(m, "Signature"); + enum_ verif_flags_enums + (signature, "VERIFICATION_FLAGS", nb::is_flag()); + verif_flags_enums + .value("OK", Signature::VERIFICATION_FLAGS::OK) + .value("INVALID_SIGNER", Signature::VERIFICATION_FLAGS::INVALID_SIGNER) + .value("UNSUPPORTED_ALGORITHM", Signature::VERIFICATION_FLAGS::UNSUPPORTED_ALGORITHM) + .value("INCONSISTENT_DIGEST_ALGORITHM", Signature::VERIFICATION_FLAGS::INCONSISTENT_DIGEST_ALGORITHM) + .value("CERT_NOT_FOUND", Signature::VERIFICATION_FLAGS::CERT_NOT_FOUND) + .value("CORRUPTED_CONTENT_INFO", Signature::VERIFICATION_FLAGS::CORRUPTED_CONTENT_INFO) + .value("CORRUPTED_AUTH_DATA", Signature::VERIFICATION_FLAGS::CORRUPTED_AUTH_DATA) + .value("MISSING_PKCS9_MESSAGE_DIGEST", Signature::VERIFICATION_FLAGS::MISSING_PKCS9_MESSAGE_DIGEST) + .value("BAD_DIGEST", Signature::VERIFICATION_FLAGS::BAD_DIGEST) + .value("BAD_SIGNATURE", Signature::VERIFICATION_FLAGS::BAD_SIGNATURE) + .value("NO_SIGNATURE", Signature::VERIFICATION_FLAGS::NO_SIGNATURE) + .value("CERT_EXPIRED", Signature::VERIFICATION_FLAGS::CERT_EXPIRED) + .value("CERT_FUTURE", Signature::VERIFICATION_FLAGS::CERT_FUTURE); + + enum_(signature, "VERIFICATION_CHECKS", nb::is_flag(), + R"delim( + Flags to tweak the verification process of the signature + See :meth:`lief.PE.Signature.check` and :meth:`lief.PE.Binary.verify_signature` + )delim"_doc) + .value("DEFAULT", Signature::VERIFICATION_CHECKS::DEFAULT, + "Default behavior that tries to follow the Microsoft verification process as close as possible"_doc) + + .value("HASH_ONLY", Signature::VERIFICATION_CHECKS::HASH_ONLY, + R"delim( + Only check that :meth:`lief.PE.Binary.authentihash` matches :attr:`lief.PE.ContentInfo.digest` + regardless of the signature's validity + )delim"_doc) + + .value("LIFETIME_SIGNING", Signature::VERIFICATION_CHECKS::LIFETIME_SIGNING, + R"delim( + Same semantic as `WTD_LIFETIME_SIGNING_FLAG `_ + )delim"_doc) + + .value("SKIP_CERT_TIME", Signature::VERIFICATION_CHECKS::SKIP_CERT_TIME, + R"delim( + Skip the verification of the certificates time validities so that even though + a certificate expired, it returns :attr:`lief.PE.Signature.VERIFICATION_FLAGS.OK` + )delim"_doc); + + init_ref_iterator(signature, "it_const_crt"); + init_ref_iterator(signature, "it_const_signers_t"); + + signature + .def_static("parse", + [] (nb::PathLike path) -> std::unique_ptr { + auto sig = SignatureParser::parse(path.to_string()); + if (!sig) { + return nullptr; + } + return std::make_unique(std::move(sig.value())); + }, + "Parse the DER PKCS #7 signature from the file path given in the first parameter"_doc, + "path"_a, nb::rv_policy::take_ownership) + + .def_static("parse", + [] (const std::vector& raw, bool skip_header) -> std::unique_ptr { + auto sig = SignatureParser::parse(raw, skip_header); + if (!sig) { + return nullptr; + } + return std::make_unique(std::move(sig.value())); + }, + "Parse the raw (DER) PKCS #7 signature given in the first parameter"_doc, + "raw"_a, "skip_header"_a = false) + + .def_prop_ro("version", + &Signature::version, + "Version of the signature. It should be 1"_doc) + + .def_prop_ro("digest_algorithm", + &Signature::digest_algorithm, + "Return the algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") \ + used to sign the content of " RST_CLASS_REF(lief.PE.ContentInfo) ""_doc) + + .def_prop_ro("content_info", + &Signature::content_info, + "Return the " RST_CLASS_REF(lief.PE.ContentInfo) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("certificates", + nb::overload_cast<>(&Signature::certificates, nb::const_), + "Return an iterator over " RST_CLASS_REF(lief.PE.x509) " certificates"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("signers", + nb::overload_cast<>(&Signature::signers, nb::const_), + "Return an iterator over the signers (" RST_CLASS_REF(lief.PE.SignerInfo) ")"_doc, + nb::keep_alive<0, 1>()) + + .def("find_crt", + nb::overload_cast&>(&Signature::find_crt, nb::const_), + "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its serial number"_doc, + nb::rv_policy::reference_internal, + "serialno"_a) + + .def("find_crt_subject", + nb::overload_cast(&Signature::find_crt_subject, nb::const_), + "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its subject"_doc, + nb::rv_policy::reference, + "subject"_a) + + .def("find_crt_subject", + nb::overload_cast&>(&Signature::find_crt_subject, nb::const_), + "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its subject **AND** its serial number"_doc, + nb::rv_policy::reference, + "subject"_a, "serialno"_a) + + .def("find_crt_issuer", + nb::overload_cast(&Signature::find_crt_issuer, nb::const_), + "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its issuer"_doc, + nb::rv_policy::reference, + "issuer"_a) + + .def("find_crt_issuer", + nb::overload_cast&>(&Signature::find_crt_issuer, nb::const_), + "Find the " RST_CLASS_REF(lief.PE.x509) " certificate according to its issuer **AND** its serial number"_doc, + nb::rv_policy::reference, + "issuer"_a, "serialno"_a) + + .def("check", + &Signature::check, + // Note: This documentation needs to be sync with LIEF::PE::Signature::check + R"delim( + Check the integrity of the signature and return a :class:`lief.PE.Signature.VERIFICATION_FLAGS` + + By default, it performs the following verifications: + + 1. It must contain only **one** signer info (:attr:`~lief.PE.Signature.signers`) + 2. :attr:`lief.PE.Signature.digest_algorithm` must match: + + * :attr:`lief.PE.ContentInfo.digest_algorithm` + * :attr:`lief.PE.SignerInfo.digest_algorithm` + + 3. The x509 certificate specified by :attr:`lief.PE.SignerInfo.serial_number` **and** :attr:`lief.PE.SignerInfo.issuer` + must exist within :attr:`lief.PE.Signature.certificates` + 4. Given the x509 certificate, compare :attr:`lief.PE.SignerInfo.encrypted_digest` against either: + + * hash of authenticated attributes (:attr:`~lief.PE.SignerInfo.authenticated_attributes`) if present + * hash of ContentInfo + + 5. If they are Authenticated attributes, check that a PKCS9_MESSAGE_DIGEST (:class:`lief.PE.PKCS9MessageDigest`) attribute exists + and that its value matches hash of ContentInfo + 6. Check the validity of the PKCS #9 counter signature if present + 7. If the signature doesn't embed a signing-time in the counter signature, check the certificate + validity. (See :attr:`lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING` and :attr:`lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME`) + + See: :class:`lief.PE.Signature.VERIFICATION_CHECKS` to tweak the behavior + + )delim"_doc, + "checks"_a = Signature::VERIFICATION_CHECKS::DEFAULT + ) + + .def_prop_ro("raw_der", + [] (const Signature& sig) { + return nb::to_memoryview(sig.raw_der()); + }, + "Return the raw original signature as a byte object"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(Signature); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/pySignerInfo.cpp b/vendor/lief/api/python/src/PE/objects/signature/pySignerInfo.cpp new file mode 100644 index 0000000..23ae7c5 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pySignerInfo.cpp @@ -0,0 +1,141 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/PE/signature/SignerInfo.hpp" +#include "LIEF/PE/signature/Attribute.hpp" +#include "LIEF/PE/signature/x509.hpp" + +#include "PE/pyPE.hpp" +#include "pyIterator.hpp" +#include "pySafeString.hpp" + +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + nb::class_ signer(m, "SignerInfo", + R"delim( + SignerInfo as described in the `RFC 2315 #Section 9.2 `_ + + .. code-block:: text + + SignerInfo ::= SEQUENCE { + version Version, + issuerAndSerialNumber IssuerAndSerialNumber, + digestAlgorithm DigestAlgorithmIdentifier, + authenticatedAttributes [0] IMPLICIT Attributes OPTIONAL, + digestEncryptionAlgorithm DigestEncryptionAlgorithmIdentifier, + encryptedDigest EncryptedDigest, + unauthenticatedAttributes [1] IMPLICIT Attributes OPTIONAL + } + + EncryptedDigest ::= OCTET STRING + )delim"_doc); + + init_ref_iterator(signer, "it_const_attributes_t"); + + signer + .def_prop_ro("version", + &SignerInfo::version, + "Should be 1"_doc) + + .def_prop_ro("serial_number", + [] (const SignerInfo& info) { + return nb::to_bytes(info.serial_number()); + }, + "The X509 serial number used to sign the signed-data (see: :attr:`lief.PE.x509.serial_number`)"_doc) + + .def_prop_ro("issuer", + [] (const SignerInfo& object) { + return safe_string(object.issuer()); + }, + "The X509 issuer used to sign the signed-data (see: :attr:`lief.PE.x509.issuer`)"_doc, + nb::rv_policy::copy) + + .def_prop_ro("digest_algorithm", + &SignerInfo::digest_algorithm, + "Algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") used to hash the file. " + "This value should match " RST_ATTR_REF_FULL(ContentInfo.digest_algorithm) " " + "and " RST_ATTR_REF_FULL(Signature.digest_algorithm) ""_doc) + + .def_prop_ro("encryption_algorithm", + &SignerInfo::encryption_algorithm, + "Return algorithm (" RST_CLASS_REF(lief.PE.ALGORITHMS) ") used to encrypt the digest"_doc) + + .def_prop_ro("encrypted_digest", + [] (const SignerInfo& info) { + return nb::to_bytes(info.encrypted_digest()); + }, + "Return the signature created by the signing certificate's private key"_doc) + + .def_prop_ro("authenticated_attributes", + &SignerInfo::authenticated_attributes, + "Return an iterator over the authenticated attributes (" + "" RST_CLASS_REF(lief.PE.Attribute) ")"_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("unauthenticated_attributes", + &SignerInfo::unauthenticated_attributes, + "Return an iterator over the unauthenticated attributes (" + "" RST_CLASS_REF(lief.PE.Attribute) ")"_doc, + nb::keep_alive<0, 1>()) + + .def("get_attribute", + &SignerInfo::get_attribute, + R"delim( + Return the authenticated or un-authenticated attribute matching the + given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` + It returns **the first** entry that matches the given type. If it can't be + found, it returns None + )delim"_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def("get_auth_attribute", + &SignerInfo::get_auth_attribute, + R"delim( + Return the authenticated attribute matching the + given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` + It returns **the first** entry that matches the given type. If it can't be + found, it returns None + )delim"_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def("get_unauth_attribute", + &SignerInfo::get_unauth_attribute, + R"delim( + Return the un-authenticated attribute matching the + given :class:`lief.PE.SIG_ATTRIBUTE_TYPES` + It returns **the first** entry that matches the given type. If it can't be + found, it returns None + )delim"_doc, + "type"_a, nb::rv_policy::reference_internal) + + .def_prop_ro("cert", + nb::overload_cast<>(&SignerInfo::cert), + "" RST_CLASS_REF(lief.PE.x509) " certificate used by this signer. If it can't be found, it returns None"_doc, + nb::rv_policy::reference_internal) + + LIEF_DEFAULT_STR(SignerInfo); +} + +} + diff --git a/vendor/lief/api/python/src/PE/objects/signature/pySpcIndirectData.cpp b/vendor/lief/api/python/src/PE/objects/signature/pySpcIndirectData.cpp new file mode 100644 index 0000000..b5e47f1 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pySpcIndirectData.cpp @@ -0,0 +1,45 @@ + +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" + +#include "LIEF/PE/signature/SpcIndirectData.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "SpcIndirectData") + .def_prop_ro("digest_algorithm", &SpcIndirectData::digest_algorithm, + R"delim( + Digest used to hash the file. This should match + :attr:`~lief.PE.SignerInfo.digest_algorithm` + )delim"_doc) + + .def_prop_ro("digest", + nb::overload_cast<>(&SpcIndirectData::digest, nb::const_)) + .def_prop_ro("file", &SpcIndirectData::file) + .def_prop_ro("url", &SpcIndirectData::url) + LIEF_DEFAULT_STR(SpcIndirectData); +} + +} diff --git a/vendor/lief/api/python/src/PE/objects/signature/pyx509.cpp b/vendor/lief/api/python/src/PE/objects/signature/pyx509.cpp new file mode 100644 index 0000000..134a553 --- /dev/null +++ b/vendor/lief/api/python/src/PE/objects/signature/pyx509.cpp @@ -0,0 +1,202 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "enums_wrapper.hpp" + +#include "LIEF/PE/signature/x509.hpp" +#include "LIEF/PE/signature/RsaInfo.hpp" + +#include "PE/pyPE.hpp" +#include "pySafeString.hpp" + +#include +#include +#include +#include +#include +#include +#include "nanobind/utils.hpp" + +namespace LIEF::PE::py { + +template<> +void create(nb::module_& m) { + nb::class_ cls_x509(m, "x509", "Interface over a x509 certificate"); + + enum_(cls_x509, "VERIFICATION_FLAGS", nb::is_flag(), + "Verification flags associated with " RST_METH_REF(lief.PE.x509.verify) ""_doc) + .value("OK", x509::VERIFICATION_FLAGS::OK, "The verification succeed"_doc) + .value("BADCERT_EXPIRED", x509::VERIFICATION_FLAGS::BADCERT_EXPIRED, "The certificate validity has expired"_doc) + .value("BADCERT_REVOKED", x509::VERIFICATION_FLAGS::BADCERT_REVOKED, "The certificate has been revoked (is on a CRL)"_doc) + .value("BADCERT_CN_MISMATCH", x509::VERIFICATION_FLAGS::BADCERT_CN_MISMATCH, "The certificate Common Name (CN) does not match with the expected CN."_doc) + .value("BADCERT_NOT_TRUSTED", x509::VERIFICATION_FLAGS::BADCERT_NOT_TRUSTED, "The certificate is not correctly signed by the trusted CA."_doc) + .value("BADCRL_NOT_TRUSTED", x509::VERIFICATION_FLAGS::BADCRL_NOT_TRUSTED, "The CRL is not correctly signed by the trusted CA."_doc) + .value("BADCRL_EXPIRED", x509::VERIFICATION_FLAGS::BADCRL_EXPIRED, "The CRL is expired."_doc) + .value("BADCERT_MISSING", x509::VERIFICATION_FLAGS::BADCERT_MISSING, "Certificate was missing."_doc) + .value("BADCERT_SKIP_VERIFY", x509::VERIFICATION_FLAGS::BADCERT_SKIP_VERIFY, "Certificate verification was skipped."_doc) + .value("BADCERT_OTHERNATURE", x509::VERIFICATION_FLAGS::BADCERT_OTHER, "Other reason"_doc) + .value("BADCERT_FUTURE", x509::VERIFICATION_FLAGS::BADCERT_FUTURE, "The certificate validity starts in the future."_doc) + .value("BADCRL_FUTURE", x509::VERIFICATION_FLAGS::BADCRL_FUTURE, "The CRL is from the future"_doc) + .value("BADCERT_KEY_USAGE", x509::VERIFICATION_FLAGS::BADCERT_KEY_USAGE, "Usage does not match the keyUsage extension."_doc) + .value("BADCERT_EXT_KEY_USAGE", x509::VERIFICATION_FLAGS::BADCERT_EXT_KEY_USAGE, "Usage does not match the extendedKeyUsage extension."_doc) + .value("BADCERT_NS_CERT_TYPE", x509::VERIFICATION_FLAGS::BADCERT_NS_CERT_TYPE, "Usage does not match the nsCertType extension."_doc) + .value("BADCERT_BAD_MD", x509::VERIFICATION_FLAGS::BADCERT_BAD_MD, "The certificate is signed with an unacceptable hash."_doc) + .value("BADCERT_BAD_PK", x509::VERIFICATION_FLAGS::BADCERT_BAD_PK, "The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA)."_doc) + .value("BADCERT_BAD_KEY", x509::VERIFICATION_FLAGS::BADCERT_BAD_KEY, "The certificate is signed with an unacceptable key (eg bad curve, RSA too short)."_doc) + .value("BADCRL_BAD_MD", x509::VERIFICATION_FLAGS::BADCRL_BAD_MD, "The CRL is signed with an unacceptable hash."_doc) + .value("BADCRL_BAD_PK", x509::VERIFICATION_FLAGS::BADCRL_BAD_PK, "The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA)."_doc) + .value("BADCRL_BAD_KEY", x509::VERIFICATION_FLAGS::BADCRL_BAD_KEY, "The CRL is signed with an unacceptable key (eg bad curve, RSA too short)."_doc); + + enum_(cls_x509, "KEY_TYPES", "Public key scheme used by the x509 certificate"_doc) + .value("NONE", x509::KEY_TYPES::NONE, "Unknown scheme"_doc) + .value("RSA", x509::KEY_TYPES::RSA, "RSA scheme") + .value("ECKEY", x509::KEY_TYPES::ECKEY, "Elliptic-curve scheme"_doc) + .value("ECKEY_DH", x509::KEY_TYPES::ECKEY_DH, "Elliptic-curve Diffie-Hellman"_doc) + .value("ECDSA", x509::KEY_TYPES::ECDSA, "Elliptic-curve Digital Signature Algorithm"_doc) + .value("RSA_ALT", x509::KEY_TYPES::RSA_ALT, "RSA scheme with an alternative implementation for signing and decrypting"_doc) + .value("RSASSA_PSS", x509::KEY_TYPES::RSASSA_PSS, "RSA Probabilistic signature scheme"_doc); + + enum_(cls_x509, "KEY_USAGE", "Key usage as defined in `RFC #5280 - section-4.2.1.3 `_"_doc) + .value("DIGITAL_SIGNATURE", x509::KEY_USAGE::DIGITAL_SIGNATURE, "The key is used for digital signature"_doc) + .value("NON_REPUDIATION", x509::KEY_USAGE::NON_REPUDIATION, "The key is used for digital signature AND to protects against falsely denying some action"_doc) + .value("KEY_ENCIPHERMENT", x509::KEY_USAGE::KEY_ENCIPHERMENT, "The key is used for enciphering private or secret keys"_doc) + .value("DATA_ENCIPHERMENT", x509::KEY_USAGE::DATA_ENCIPHERMENT, "The key is used for directly enciphering raw user data without the use of an intermediate symmetric cipher"_doc) + .value("KEY_AGREEMENT", x509::KEY_USAGE::KEY_AGREEMENT, "The Key is used for key agreement. (e.g. with Diffie-Hellman)"_doc) + .value("KEY_CERT_SIGN", x509::KEY_USAGE::KEY_CERT_SIGN, "The key is used for verifying signatures on public key certificates"_doc) + .value("CRL_SIGN", x509::KEY_USAGE::CRL_SIGN, "The key is used for verifying signatures on certificate revocation lists"_doc) + .value("ENCIPHER_ONLY", x509::KEY_USAGE::ENCIPHER_ONLY, "In **association with** KEY_AGREEMENT (otherwise the meaning is undefined), the key is only used for enciphering data while performing key agreement"_doc) + .value("DECIPHER_ONLY", x509::KEY_USAGE::DECIPHER_ONLY, "In **association with** KEY_AGREEMENT (otherwise the meaning is undefined), the key is only used for deciphering data while performing key agreement"_doc); + + cls_x509 + .def_static("parse", + nb::overload_cast(&x509::parse), + "Parse " RST_CLASS_REF(lief.PE.x509) " certificate(s) from a file path given in the first parameter.\n" + "It returns a **list** of " RST_CLASS_REF(lief.PE.x509) " objects"_doc, + "path"_a) + + .def_static("parse", + nb::overload_cast&>(&x509::parse), + "Parse " RST_CLASS_REF(lief.PE.x509) " certificate(s) from a raw blob given in the first parameter.\n" + "It returns a **list** of " RST_CLASS_REF(lief.PE.x509) " objects"_doc, + "raw"_a) + + .def_prop_ro("version", + &x509::version, + "X.509 version. (1=v1, 2=v2, 3=v3)"_doc) + + .def_prop_ro("serial_number", + [] (const x509& crt) { + return nb::to_bytes(crt.serial_number()); + }, + "Unique id for certificate issued by a specific CA."_doc) + + .def_prop_ro("signature_algorithm", + &x509::signature_algorithm, + "Signature algorithm (OID)"_doc) + + .def_prop_ro("valid_from", + &x509::valid_from, + "Start time of certificate validity"_doc) + + .def_prop_ro("valid_to", + &x509::valid_to, + "End time of certificate validity"_doc) + + .def_prop_ro("issuer", + [] (const x509& object) { + return LIEF::py::safe_string(object.issuer()); + }, + "Issuer of the certificate"_doc) + + .def_prop_ro("subject", + [] (const x509& object) { + return LIEF::py::safe_string(object.subject()); + }, + "Subject of the certificate"_doc) + + .def_prop_ro("raw", + [] (const x509& crt) { + return nb::to_bytes(crt.raw()); + }, + "The raw bytes associated with this x509 cert (DER encoded)"_doc) + + .def_prop_ro("key_type", + &x509::key_type, + "Return the underlying public-key scheme (" RST_CLASS_REF(lief.PE.x509.KEY_TYPES) ")"_doc) + + .def_prop_ro("rsa_info", + &x509::rsa_info, + "If the underlying public-key scheme is RSA, return the " RST_CLASS_REF(lief.PE.RsaInfo) " associated with this certificate. " + "Otherwise, return None"_doc, + nb::rv_policy::take_ownership) + + .def_prop_ro("key_usage", + &x509::key_usage, + "Purpose of the key contained in the certificate (see " RST_CLASS_REF(lief.PE.x509.KEY_USAGE) ")"_doc) + + .def_prop_ro("ext_key_usage", + &x509::ext_key_usage, + "Indicates one or more purposes for which the certified public key may be used (list of OID)"_doc) + + .def_prop_ro("certificate_policies", + &x509::certificate_policies, + "Policy information terms as list of OID (see RFC #5280)"_doc) + + .def_prop_ro("is_ca", + &x509::is_ca) + + .def_prop_ro("signature", + [] (const x509& cert) { + return nb::to_bytes(cert.signature()); + }, "The signature of the certificate") + + .def("verify", + nb::overload_cast(&x509::verify, nb::const_), + R"delim( + Verify that this certificate has been used **to trust** the given :class:`~lief.PE.x509` certificate + + It returns a set of flags defined by :class:`~lief.PE.x509.VERIFICATION_FLAGS` + + :Example: + + .. code-block:: python + + ca = lief.PE.x509.parse("ca.crt")[0] + signer = lief.PE.x509.parse("signer.crt")[0] + print(ca.verify(signer)) # lief.PE.x509.VERIFICATION_FLAGS.OK + + )delim"_doc, + "ca"_a) + + .def("is_trusted_by", + &x509::is_trusted_by, + R"delim( + Verify this certificate against a list of root CA (list of :class:`~lief.PE.x509` objects) + It returns a set of flags defined by :class:`~lief.PE.x509.VERIFICATION_FLAGS` + + :Example: + + .. code-block:: python + + signer = binary.signatures[0].signers[0] + microsoft_ca_bundle = lief.PE.x509.parse("bundle.pem") + print(signer.cert.is_trusted_by(microsoft_ca_bundle)) + )delim"_doc, + "ca_list"_a) + + LIEF_DEFAULT_STR(x509); +} +} + diff --git a/vendor/lief/api/python/src/PE/ordinal_or_str.hpp b/vendor/lief/api/python/src/PE/ordinal_or_str.hpp new file mode 100644 index 0000000..2d53caa --- /dev/null +++ b/vendor/lief/api/python/src/PE/ordinal_or_str.hpp @@ -0,0 +1,36 @@ +#pragma once + +#include +#include + +#include "LIEF/PE/resources/ResourceDialog.hpp" +#include "nanobind/extra/stl/u16string.h" + +NAMESPACE_BEGIN(NB_NAMESPACE) +NAMESPACE_BEGIN(detail) + +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::PE::ResourceDialog::ordinal_or_str_t, const_name("Optional[Union[int, str]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(const LIEF::PE::ResourceDialog::ordinal_or_str_t& val, + rv_policy rp, cleanup_list *cl) noexcept + { + if (val.ordinal) { + return int_(*val.ordinal).release(); + } + + if (val.string.empty()) { + return none().release(); + } + + return type_caster::from_cpp(val.string, rp, cl).inc_ref(); + } +}; + +NAMESPACE_END(detail) +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/PE/pyPE.hpp b/vendor/lief/api/python/src/PE/pyPE.hpp new file mode 100644 index 0000000..e400947 --- /dev/null +++ b/vendor/lief/api/python/src/PE/pyPE.hpp @@ -0,0 +1,26 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_PE_H +#define PY_LIEF_PE_H +#include "pyLIEF.hpp" + +namespace LIEF::PE::py { +template +void create(nb::module_&); + +void init_utils(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/PE/pyUtils.cpp b/vendor/lief/api/python/src/PE/pyUtils.cpp new file mode 100644 index 0000000..750bfbd --- /dev/null +++ b/vendor/lief/api/python/src/PE/pyUtils.cpp @@ -0,0 +1,122 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PE/pyPE.hpp" +#include "pyErr.hpp" + +#include "LIEF/PE/utils.hpp" +#include "LIEF/PE/Import.hpp" +#include "LIEF/PE/Binary.hpp" + +#include "LIEF/PE/signature/OIDToString.hpp" + +#include +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +namespace LIEF::PE::py { + +void init_utils(nb::module_& m) { + using namespace LIEF::py; + + nb::enum_(m, "IMPHASH_MODE", + "Enum to define the behavior of :func:`~lief.PE.get_imphash`"_doc) + .value("DEFAULT", IMPHASH_MODE::DEFAULT, "Default implementation") + .value("LIEF", IMPHASH_MODE::LIEF, "Same as DEFAULT") + .value("PEFILE", IMPHASH_MODE::PEFILE, "Use pefile algorithm") + .value("VT", IMPHASH_MODE::VT, "Same as PEFILE since Virus Total is using pefile"); + + m.def("oid_to_string", &oid_to_string, + "Convert an OID to a human-readable string"_doc); + + + lief_mod->def("is_pe", + [] (nb::PathLike path) { return is_pe(path.to_string()); }, + "Check if the given file is a ``PE``"_doc, + "file"_a); + + lief_mod->def("is_pe", + nb::overload_cast&>(&is_pe), + "Check if the given raw data is a ``PE``"_doc, + "raw"_a); + + m.def("get_type", + [] (nb::PathLike file) { + return error_or(static_cast (*)(std::string_view)>(&get_type), + file.to_string()); + }, + R"delim( + If the input file is a valid ``PE``, return the :class:`~.lief.PE.PE_TYPE`. + Otherwise, return a :class:`lief.lief_errors`. + )delim"_doc, + "file"_a); + + + m.def("get_type", + [] (const std::vector& raw) { + return error_or(static_cast (*)(const std::vector&)>(&get_type), raw); + }, + "raw"_a); + + m.def("get_imphash", + &get_imphash, + R"delim( + Compute the hash of imported functions + + Properties of the hash generated: + + * Order agnostic + * Case agnostic + * Ordinal (**in some extent**) agnostic + + If one needs the same output as Virus Total (i.e. pefile), you can use :attr:`~lief.PE.IMPHASH_MODE.PEFILE` + as second parameter. + + .. warning:: + The algorithm used to compute the *imphash* value has some variations compared to Yara, pefile, + VT implementation + + .. seealso:: + https://www.fireeye.com/blog/threat-research/2014/01/tracking-malware-import-hashing.html + )delim"_doc, + "binary"_a, "mode"_a = IMPHASH_MODE::DEFAULT); + + m.def("resolve_ordinals", + [] (const Import& import, bool strict = false, bool use_std = false) { + return error_or(resolve_ordinals, import, strict, use_std); + }, + R"delim( + Take a :class:`~lief.PE.Import` as input and try to resolve its ordinal imports. + + If the ``strict`` boolean parameter is set, a :attr:`lief.lief_errors.not_found` error is + returned upon the first non-resolvable ordinal. + )delim", + "imp"_a, "strict"_a = false, "use_std"_a = false, + nb::rv_policy::copy); + + m.def("check_layout", [] (const Binary& bin) -> std::pair { + std::string error; + if (!check_layout(bin, &error)) { + return std::make_pair(false, std::move(error)); + } + return std::make_pair(true, ""); + }, + R"doc( + Check that the layout of the given binary is correct from the Windows loader + perspective. + )doc"_doc, "binary"_a); +} +} diff --git a/vendor/lief/api/python/src/VDEX/CMakeLists.txt b/vendor/lief/api/python/src/VDEX/CMakeLists.txt new file mode 100644 index 0000000..19ea759 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyUtils.cpp +) +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/VDEX/init.cpp b/vendor/lief/api/python/src/VDEX/init.cpp new file mode 100644 index 0000000..a2f0066 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/init.cpp @@ -0,0 +1,39 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "VDEX/pyVDEX.hpp" +#include "VDEX/init.hpp" + +#include +#include +#include + +#define CREATE(X,Y) create(Y) + +namespace LIEF::VDEX::py { + +inline void init_objects(nb::module_& m) { + CREATE(Parser, m); + CREATE(File, m); + CREATE(Header, m); +} + +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("VDEX", "Python API for VDEX format"_doc); + + init_objects(mod); + init_utils(mod); +} +} diff --git a/vendor/lief/api/python/src/VDEX/init.hpp b/vendor/lief/api/python/src/VDEX/init.hpp new file mode 100644 index 0000000..ba79ad5 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/init.hpp @@ -0,0 +1,24 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_VDEX_INIT_H +#define PY_LIEF_VDEX_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::VDEX::py { +void init(nb::module_& m); +void init_utils(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/VDEX/objects/CMakeLists.txt b/vendor/lief/api/python/src/VDEX/objects/CMakeLists.txt new file mode 100644 index 0000000..976a565 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/objects/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + pyHeader.cpp + pyParser.cpp + pyFile.cpp +) diff --git a/vendor/lief/api/python/src/VDEX/objects/pyFile.cpp b/vendor/lief/api/python/src/VDEX/objects/pyFile.cpp new file mode 100644 index 0000000..3c0e9bb --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/objects/pyFile.cpp @@ -0,0 +1,59 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/VDEX/File.hpp" +#include "LIEF/DEX/File.hpp" + +#include "pyIterator.hpp" + +#include "VDEX/pyVDEX.hpp" + +#include +#include + +namespace LIEF::VDEX::py { +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + nb::class_ file(m, "File", "VDEX File representation"_doc); + + /* + * it_dex_files is also registered by OAT/pyBinary.cpp and pybind11 + * seems not able to see their (limited) scope such as it raises + * generic_type: type "it_dex_files" is already registered! + * + * NOTE(romain): I tried to add py::local_module in pyIterator.hpp without + * success + */ + try { + init_ref_iterator(file, "it_dex_files"); + } catch (const std::runtime_error&) {} + + file + .def_prop_ro("header", nb::overload_cast<>(&File::header), + "Return the VDEX " RST_CLASS_REF(lief.VDEX.Header) ""_doc, + nb::rv_policy::reference_internal) + + .def_prop_ro("dex_files", nb::overload_cast<>(&File::dex_files), + "Return an iterator over " RST_CLASS_REF(lief.DEX.File) ""_doc, + nb::keep_alive<0, 1>()) + + .def_prop_ro("dex2dex_json_info", &File::dex2dex_json_info) + + LIEF_DEFAULT_STR(File); +} + +} + diff --git a/vendor/lief/api/python/src/VDEX/objects/pyHeader.cpp b/vendor/lief/api/python/src/VDEX/objects/pyHeader.cpp new file mode 100644 index 0000000..f17b199 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/objects/pyHeader.cpp @@ -0,0 +1,60 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/VDEX/Header.hpp" + +#include "VDEX/pyVDEX.hpp" + +#include +#include +#include +#include + +namespace LIEF::VDEX::py { + +template<> +void create
(nb::module_& m) { + + nb::class_(m, "Header", "VDEX Header representation"_doc) + + .def_prop_ro("magic", + nb::overload_cast<>(&Header::magic, nb::const_), + "Magic value used to identify VDEX"_doc) + + .def_prop_ro("version", + nb::overload_cast<>(&Header::version, nb::const_), + "VDEX version number"_doc) + + .def_prop_ro("nb_dex_files", + nb::overload_cast<>(&Header::nb_dex_files, nb::const_), + "Number of " RST_CLASS_REF(lief.DEX.File) " files registered"_doc) + + .def_prop_ro("dex_size", + nb::overload_cast<>(&Header::dex_size, nb::const_), + "Size of **all** " RST_CLASS_REF(lief.DEX.File) ""_doc) + + .def_prop_ro("verifier_deps_size", + nb::overload_cast<>(&Header::verifier_deps_size, nb::const_), + "Size of verifier deps section"_doc) + + .def_prop_ro("quickening_info_size", + nb::overload_cast<>(&Header::quickening_info_size, nb::const_), + "Size of quickening info section"_doc) + + LIEF_DEFAULT_STR(Header); + +} + +} diff --git a/vendor/lief/api/python/src/VDEX/objects/pyParser.cpp b/vendor/lief/api/python/src/VDEX/objects/pyParser.cpp new file mode 100644 index 0000000..4f139b7 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/objects/pyParser.cpp @@ -0,0 +1,61 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "VDEX/pyVDEX.hpp" + +#include "LIEF/VDEX/Parser.hpp" +#include "LIEF/VDEX/File.hpp" +#include "LIEF/logging.hpp" + +#include "pyIOStream.hpp" +#include "pyutils.hpp" +#include "typing/InputParser.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF::VDEX::py { + +template<> +void create(nb::module_& m) { + using namespace LIEF::py; + + m.def("parse", + static_cast(*)(std::string_view)>(&Parser::parse), + "Parse the given filename and return a " RST_CLASS_REF(lief.VDEX.File) " object"_doc, + "filename"_a, nb::rv_policy::take_ownership); + + m.def("parse", + [] (typing::InputParser obj, const std::string& name) -> std::unique_ptr { + if (auto path_str = path_to_str(obj)) { + return Parser::parse(std::move(*path_str)); + } + + if (auto stream = PyIOStream::from_python(obj)) { + auto ptr = std::make_unique(std::move(*stream)); + return Parser::parse(stream->content(), name); + } + logging::log(logging::Level::Err, + "LIEF parser interface does not support Python object: " + + type2str(obj)); + return nullptr; + }, + "obj"_a, "name"_a = "", + nb::rv_policy::take_ownership); +} +} diff --git a/vendor/lief/api/python/src/VDEX/pyUtils.cpp b/vendor/lief/api/python/src/VDEX/pyUtils.cpp new file mode 100644 index 0000000..d4f1720 --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/pyUtils.cpp @@ -0,0 +1,49 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "VDEX/pyVDEX.hpp" + +#include "LIEF/VDEX/utils.hpp" +#include +#include +#include + +namespace LIEF::VDEX::py { + +void init_utils(nb::module_& m) { + lief_mod->def("is_vdex", nb::overload_cast(&is_vdex), + "Check if the **file** given in parameter is a VDEX"_doc, + "path"_a); + + lief_mod->def("is_vdex", nb::overload_cast&>(&is_vdex), + "Check if the **raw data** given in parameter is a VDEX"_doc, + "raw"_a); + + m.def("version", nb::overload_cast(&version), + "Return the VDEX version of the **file** given in parameter"_doc, + "file"_a); + + m.def("version", nb::overload_cast&>(&version), + "Return the VDEX version of the **raw data** given in parameter"_doc, + "raw"_a); + + m.def("android_version", + &android_version, + "Return the " RST_CLASS_REF(lief.Android.ANDROID_VERSIONS) " associated with the given VDEX version"_doc, + "vdex_version"_a); +} + +} + diff --git a/vendor/lief/api/python/src/VDEX/pyVDEX.hpp b/vendor/lief/api/python/src/VDEX/pyVDEX.hpp new file mode 100644 index 0000000..49311bd --- /dev/null +++ b/vendor/lief/api/python/src/VDEX/pyVDEX.hpp @@ -0,0 +1,27 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_VDEX_H +#define PY_LIEF_VDEX_H + +#include "pyLIEF.hpp" + +namespace LIEF::VDEX::py { +template +void create(nb::module_&); +} + + +#endif diff --git a/vendor/lief/api/python/src/asm/CMakeLists.txt b/vendor/lief/api/python/src/asm/CMakeLists.txt new file mode 100644 index 0000000..e7f2a7e --- /dev/null +++ b/vendor/lief/api/python/src/asm/CMakeLists.txt @@ -0,0 +1,14 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyEngine.cpp + pyInstruction.cpp + pyAssemblerConfig.cpp +) + +add_subdirectory(aarch64) +add_subdirectory(x86) +add_subdirectory(mips) +add_subdirectory(arm) +add_subdirectory(powerpc) +add_subdirectory(riscv) +add_subdirectory(ebpf) diff --git a/vendor/lief/api/python/src/asm/aarch64/CMakeLists.txt b/vendor/lief/api/python/src/asm/aarch64/CMakeLists.txt new file mode 100644 index 0000000..c5e4e70 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyOperand.cpp + pyRegister.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/aarch64/init.cpp b/vendor/lief/api/python/src/asm/aarch64/init.cpp new file mode 100644 index 0000000..7662da1 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/init.cpp @@ -0,0 +1,20 @@ +#include "asm/aarch64/init.hpp" +namespace LIEF::assembly::aarch64 { +enum class OPCODE; +enum class REG; +enum class SYSREG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::aarch64::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("aarch64"); + + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/init.hpp b/vendor/lief/api/python/src/asm/aarch64/init.hpp new file mode 100644 index 0000000..909566a --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_AARCH64_INIT_H +#define PY_LIEF_ASM_AARCH64_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::aarch64::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/aarch64/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/aarch64/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/aarch64/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/aarch64/operands/pyImmediate.cpp new file mode 100644 index 0000000..618f73e --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/operands/pyImmediate.cpp @@ -0,0 +1,28 @@ +#include "asm/aarch64/init.hpp" +#include "LIEF/asm/aarch64/operands/Immediate.hpp" + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + For instance: + + .. code-block:: text + + mov x0, #8; + | + +---> Immediate(8) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/aarch64/operands/pyMemory.cpp new file mode 100644 index 0000000..141dcaf --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/operands/pyMemory.cpp @@ -0,0 +1,103 @@ +#include + +#include "asm/aarch64/init.hpp" +#include "LIEF/asm/aarch64/operands/Memory.hpp" + +namespace nanobind::detail { +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::assembly::aarch64::operands::Memory::offset_t, + const_name("Optional[Union[lief.assembly.aarch64.REG, int]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::assembly::aarch64::operands::Memory::offset_t val, + rv_policy, cleanup_list *) noexcept + { + using namespace LIEF::assembly::aarch64; + using namespace LIEF::assembly::aarch64::operands; + switch (val.type) { + case Memory::offset_t::TYPE::REG: + return make_caster::from_cpp(val.reg, rv_policy::copy, + /*cleanup_list*/nullptr); + + case Memory::offset_t::TYPE::DISP: + return make_caster::from_cpp(val.displacement, rv_policy::copy, + /*cleanup_list*/nullptr); + case Memory::offset_t::TYPE::NONE: + return nb::none(); + } + return nb::none(); + } +}; +} + + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + .. code-block:: text + + ldr x0, [x1, x2, lsl #3] + | | | + +------------+ | +--------+ + | | | + v v v + Base Reg Offset Shift + )doc"_doc + ); + + nb::enum_(obj, "SHIFT") + .value("UNKNOWN", operands::Memory::SHIFT::UNKNOWN) + .value("LSL", operands::Memory::SHIFT::LSL) + .value("UXTX", operands::Memory::SHIFT::UXTX) + .value("UXTW", operands::Memory::SHIFT::UXTW) + .value("SXTX", operands::Memory::SHIFT::SXTX) + .value("SXTW", operands::Memory::SHIFT::SXTW) + ; + + nb::class_(obj, "shift_info_t", + R"doc(This structure holds shift info (type + value))doc"_doc + ) + .def_ro("type", &operands::Memory::shift_info_t::type) + .def_ro("value", &operands::Memory::shift_info_t::value) + ; + + obj.attr("__match_args__") = nb::make_tuple("base", "offset", "shift"); + + obj + .def_prop_ro("base", &operands::Memory::base, + R"doc( + The base register. + + For ``str x3, [x8, #8]`` it would return ``x8``. + )doc"_doc + ) + .def_prop_ro("offset", &operands::Memory::offset, + R"doc( + The addressing offset. + + It can be either: + + - A register (e.g. ``ldr x0, [x1, x3]``) + - An offset (e.g. ``ldr x0, [x1, #8]``) + )doc"_doc + ) + .def_prop_ro("shift", &operands::Memory::shift, + R"doc( + Shift information. + + For instance, for ``ldr x1, [x2, x3, lsl #3]`` it would + return a :attr:`~.Memory.SHIFT.LSL` with a :attr:`~.Memory.shift_info_t.value` + set to ``3``. + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/aarch64/operands/pyPCRelative.cpp new file mode 100644 index 0000000..2b7f2e6 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/operands/pyPCRelative.cpp @@ -0,0 +1,30 @@ +#include "asm/aarch64/init.hpp" +#include "LIEF/asm/aarch64/operands/PCRelative.hpp" + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a PC-relative operand. + + .. code-block:: text + + ldr x0, #8 + | + v + PC Relative operand + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &aarch64::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``pc`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/aarch64/operands/pyRegister.cpp new file mode 100644 index 0000000..2932a57 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/operands/pyRegister.cpp @@ -0,0 +1,68 @@ +#include + +#include "asm/aarch64/init.hpp" +#include "LIEF/asm/aarch64/operands/Register.hpp" + +namespace nanobind::detail { +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::assembly::aarch64::operands::Register::reg_t, + const_name("Optional[Union[lief.assembly.aarch64.REG, lief.assembly.aarch64.SYSREG]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::assembly::aarch64::operands::Register::reg_t val, + rv_policy, cleanup_list *) noexcept + { + using namespace LIEF::assembly::aarch64; + using namespace LIEF::assembly::aarch64::operands; + switch (val.type) { + case Register::reg_t::TYPE::REG: + return make_caster::from_cpp(val.reg, rv_policy::copy, + /*cleanup_list*/nullptr); + + case Register::reg_t::TYPE::SYSREG: + return make_caster::from_cpp(val.sysreg, rv_policy::copy, + /*cleanup_list*/nullptr); + case Register::reg_t::TYPE::NONE: + return nb::none(); + } + return nb::none(); + } +}; +} + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + .. code-block:: text + + mrs x0, TPIDR_EL0 + | | + +------+ +-------+ + | | + v v + REG SYSREG + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Register::value, + R"doc( + The effective register as either: a :class:`lief.assembly.aarch64.REG` or + a :class:`lief.assembly.aarch64.SYSREG`. + )doc"_doc + ) + ; + + +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/pyInstruction.cpp b/vendor/lief/api/python/src/asm/aarch64/pyInstruction.cpp new file mode 100644 index 0000000..c0d2213 --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/pyInstruction.cpp @@ -0,0 +1,36 @@ +#include "LIEF/asm/aarch64/Instruction.hpp" +#include "LIEF/asm/aarch64/Operand.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include "asm/aarch64/init.hpp" + +#include + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc( + This class represents an AArch64 instruction + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("operands", [] (const aarch64::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/pyOpcode.cpp b/vendor/lief/api/python/src/asm/aarch64/pyOpcode.cpp new file mode 100644 index 0000000..ddf239e --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/pyOpcode.cpp @@ -0,0 +1,9147 @@ +#include "asm/aarch64/init.hpp" + +#include "LIEF/asm/aarch64/opcodes.hpp" + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::aarch64::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::aarch64::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::aarch64::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::aarch64::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::aarch64::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::aarch64::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::aarch64::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::aarch64::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::aarch64::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::aarch64::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::aarch64::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::aarch64::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::aarch64::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::aarch64::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::aarch64::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::aarch64::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::aarch64::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::aarch64::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::aarch64::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::aarch64::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::aarch64::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::aarch64::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::aarch64::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::aarch64::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::aarch64::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::aarch64::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::aarch64::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::aarch64::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::aarch64::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::aarch64::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::aarch64::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::aarch64::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::aarch64::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::aarch64::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::aarch64::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::aarch64::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::aarch64::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::aarch64::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::aarch64::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::aarch64::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::aarch64::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::aarch64::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::aarch64::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::aarch64::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::aarch64::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::aarch64::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::aarch64::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::aarch64::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::aarch64::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::aarch64::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::aarch64::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::aarch64::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::aarch64::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::aarch64::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::aarch64::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::aarch64::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::aarch64::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::aarch64::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::aarch64::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::aarch64::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::aarch64::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::aarch64::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::aarch64::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::aarch64::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::aarch64::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::aarch64::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::aarch64::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::aarch64::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::aarch64::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::aarch64::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::aarch64::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::aarch64::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::aarch64::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::aarch64::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::aarch64::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::aarch64::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::aarch64::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::aarch64::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::aarch64::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::aarch64::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::aarch64::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::aarch64::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::aarch64::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::aarch64::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::aarch64::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::aarch64::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::aarch64::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::aarch64::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::aarch64::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::aarch64::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::aarch64::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::aarch64::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::aarch64::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::aarch64::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::aarch64::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::aarch64::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::aarch64::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::aarch64::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::aarch64::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::aarch64::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::aarch64::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::aarch64::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::aarch64::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::aarch64::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::aarch64::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::aarch64::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::aarch64::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::aarch64::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::aarch64::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::aarch64::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::aarch64::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::aarch64::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::aarch64::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::aarch64::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::aarch64::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::aarch64::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::aarch64::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::aarch64::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::aarch64::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::aarch64::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::aarch64::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::aarch64::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::aarch64::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::aarch64::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::aarch64::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::aarch64::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::aarch64::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::aarch64::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::aarch64::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::aarch64::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::aarch64::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::aarch64::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::aarch64::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::aarch64::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::aarch64::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::aarch64::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::aarch64::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::aarch64::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::aarch64::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::aarch64::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::aarch64::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::aarch64::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::aarch64::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::aarch64::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::aarch64::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::aarch64::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::aarch64::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::aarch64::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::aarch64::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::aarch64::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::aarch64::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::aarch64::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::aarch64::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::aarch64::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::aarch64::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::aarch64::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::aarch64::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::aarch64::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::aarch64::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::aarch64::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::aarch64::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::aarch64::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::aarch64::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::aarch64::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::aarch64::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::aarch64::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::aarch64::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::aarch64::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::aarch64::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::aarch64::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::aarch64::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::aarch64::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::aarch64::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::aarch64::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::aarch64::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::aarch64::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::aarch64::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::aarch64::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::aarch64::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::aarch64::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::aarch64::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::aarch64::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::aarch64::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::aarch64::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::aarch64::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::aarch64::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::aarch64::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::aarch64::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::aarch64::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::aarch64::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::aarch64::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::aarch64::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::aarch64::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::aarch64::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::aarch64::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::aarch64::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::aarch64::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::aarch64::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::aarch64::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::aarch64::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::aarch64::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::aarch64::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::aarch64::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::aarch64::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::aarch64::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::aarch64::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::aarch64::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::aarch64::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::aarch64::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::aarch64::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::aarch64::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::aarch64::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::aarch64::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::aarch64::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::aarch64::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::aarch64::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::aarch64::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::aarch64::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::aarch64::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::aarch64::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::aarch64::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::aarch64::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::aarch64::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::aarch64::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::aarch64::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::aarch64::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::aarch64::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::aarch64::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::aarch64::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::aarch64::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::aarch64::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::aarch64::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::aarch64::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::aarch64::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::aarch64::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::aarch64::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::aarch64::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::aarch64::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::aarch64::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::aarch64::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::aarch64::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::aarch64::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::aarch64::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::aarch64::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::aarch64::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::aarch64::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::aarch64::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::aarch64::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::aarch64::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::aarch64::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::aarch64::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::aarch64::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::aarch64::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::aarch64::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::aarch64::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::aarch64::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::aarch64::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::aarch64::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::aarch64::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::aarch64::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::aarch64::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::aarch64::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::aarch64::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::aarch64::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::aarch64::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::aarch64::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::aarch64::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::aarch64::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::aarch64::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::aarch64::OPCODE::G_UBFX) + .value("ABS_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_B_UNDEF) + .value("ABS_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_D_UNDEF) + .value("ABS_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_H_UNDEF) + .value("ABS_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_S_UNDEF) + .value("ADDHA_MPPZ_D_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::ADDHA_MPPZ_D_PSEUDO_D) + .value("ADDHA_MPPZ_S_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::ADDHA_MPPZ_S_PSEUDO_S) + .value("ADDSWrr", LIEF::assembly::aarch64::OPCODE::ADDSWrr) + .value("ADDSXrr", LIEF::assembly::aarch64::OPCODE::ADDSXrr) + .value("ADDVA_MPPZ_D_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::ADDVA_MPPZ_D_PSEUDO_D) + .value("ADDVA_MPPZ_S_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::ADDVA_MPPZ_S_PSEUDO_S) + .value("ADDWrr", LIEF::assembly::aarch64::OPCODE::ADDWrr) + .value("ADDXrr", LIEF::assembly::aarch64::OPCODE::ADDXrr) + .value("ADD_VG2_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z2Z_D_PSEUDO) + .value("ADD_VG2_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z2Z_S_PSEUDO) + .value("ADD_VG2_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2ZZ_D_PSEUDO) + .value("ADD_VG2_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2ZZ_S_PSEUDO) + .value("ADD_VG2_M2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z_D_PSEUDO) + .value("ADD_VG2_M2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z_S_PSEUDO) + .value("ADD_VG4_M4Z4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z4Z_D_PSEUDO) + .value("ADD_VG4_M4Z4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z4Z_S_PSEUDO) + .value("ADD_VG4_M4ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4ZZ_D_PSEUDO) + .value("ADD_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4ZZ_S_PSEUDO) + .value("ADD_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_D_PSEUDO) + .value("ADD_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_S_PSEUDO) + .value("ADD_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_B_ZERO) + .value("ADD_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_D_ZERO) + .value("ADD_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_H_ZERO) + .value("ADD_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_S_ZERO) + .value("ADDlowTLS", LIEF::assembly::aarch64::OPCODE::ADDlowTLS) + .value("ADJCALLSTACKDOWN", LIEF::assembly::aarch64::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::aarch64::OPCODE::ADJCALLSTACKUP) + .value("AESIMCrrTied", LIEF::assembly::aarch64::OPCODE::AESIMCrrTied) + .value("AESMCrrTied", LIEF::assembly::aarch64::OPCODE::AESMCrrTied) + .value("ANDSWrr", LIEF::assembly::aarch64::OPCODE::ANDSWrr) + .value("ANDSXrr", LIEF::assembly::aarch64::OPCODE::ANDSXrr) + .value("ANDWrr", LIEF::assembly::aarch64::OPCODE::ANDWrr) + .value("ANDXrr", LIEF::assembly::aarch64::OPCODE::ANDXrr) + .value("AND_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_B_ZERO) + .value("AND_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_D_ZERO) + .value("AND_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_H_ZERO) + .value("AND_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_S_ZERO) + .value("ASRD_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::ASRD_ZPZI_B_ZERO) + .value("ASRD_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::ASRD_ZPZI_D_ZERO) + .value("ASRD_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::ASRD_ZPZI_H_ZERO) + .value("ASRD_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::ASRD_ZPZI_S_ZERO) + .value("ASR_ZPZI_B_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_B_UNDEF) + .value("ASR_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_B_ZERO) + .value("ASR_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_D_UNDEF) + .value("ASR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_D_ZERO) + .value("ASR_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_H_UNDEF) + .value("ASR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_H_ZERO) + .value("ASR_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_S_UNDEF) + .value("ASR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZI_S_ZERO) + .value("ASR_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_B_UNDEF) + .value("ASR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_B_ZERO) + .value("ASR_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_D_UNDEF) + .value("ASR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_D_ZERO) + .value("ASR_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_H_UNDEF) + .value("ASR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_H_ZERO) + .value("ASR_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_S_UNDEF) + .value("ASR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::ASR_ZPZZ_S_ZERO) + .value("AUTH_TCRETURN", LIEF::assembly::aarch64::OPCODE::AUTH_TCRETURN) + .value("AUTH_TCRETURN_BTI", LIEF::assembly::aarch64::OPCODE::AUTH_TCRETURN_BTI) + .value("AUTPAC", LIEF::assembly::aarch64::OPCODE::AUTPAC) + .value("AUTx16x17", LIEF::assembly::aarch64::OPCODE::AUTx16x17) + .value("AUTxMxN", LIEF::assembly::aarch64::OPCODE::AUTxMxN) + .value("AllocateSMESaveBuffer", LIEF::assembly::aarch64::OPCODE::AllocateSMESaveBuffer) + .value("AllocateZABuffer", LIEF::assembly::aarch64::OPCODE::AllocateZABuffer) + .value("BFADD_VG2_M2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFADD_VG2_M2Z_H_PSEUDO) + .value("BFADD_VG4_M4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFADD_VG4_M4Z_H_PSEUDO) + .value("BFADD_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFADD_ZPZZ_UNDEF) + .value("BFADD_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFADD_ZPZZ_ZERO) + .value("BFDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2Z2Z_HtoS_PSEUDO) + .value("BFDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("BFDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2ZZ_HtoS_PSEUDO) + .value("BFDOT_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4Z4Z_HtoS_PSEUDO) + .value("BFDOT_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4ZZI_HtoS_PSEUDO) + .value("BFDOT_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4ZZ_HtoS_PSEUDO) + .value("BFMAXNM_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMAXNM_ZPZZ_UNDEF) + .value("BFMAXNM_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFMAXNM_ZPZZ_ZERO) + .value("BFMAX_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMAX_ZPZZ_UNDEF) + .value("BFMAX_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFMAX_ZPZZ_ZERO) + .value("BFMINNM_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMINNM_ZPZZ_UNDEF) + .value("BFMINNM_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFMINNM_ZPZZ_ZERO) + .value("BFMIN_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMIN_ZPZZ_UNDEF) + .value("BFMIN_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFMIN_ZPZZ_ZERO) + .value("BFMLAL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_MZZI_HtoS_PSEUDO) + .value("BFMLAL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_MZZ_HtoS_PSEUDO) + .value("BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("BFMLAL_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2ZZI_HtoS_PSEUDO) + .value("BFMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2ZZ_HtoS_PSEUDO) + .value("BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("BFMLAL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4ZZI_HtoS_PSEUDO) + .value("BFMLAL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4ZZ_HtoS_PSEUDO) + .value("BFMLA_VG2_M2Z2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2Z2Z_PSEUDO) + .value("BFMLA_VG2_M2ZZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2ZZI_PSEUDO) + .value("BFMLA_VG2_M2ZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2ZZ_PSEUDO) + .value("BFMLA_VG4_M4Z4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4Z4Z_PSEUDO) + .value("BFMLA_VG4_M4ZZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4ZZI_PSEUDO) + .value("BFMLA_VG4_M4ZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4ZZ_PSEUDO) + .value("BFMLA_ZPZZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMLA_ZPZZZ_UNDEF) + .value("BFMLSL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_MZZI_HtoS_PSEUDO) + .value("BFMLSL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_MZZ_HtoS_PSEUDO) + .value("BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("BFMLSL_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2ZZI_HtoS_PSEUDO) + .value("BFMLSL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2ZZ_HtoS_PSEUDO) + .value("BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("BFMLSL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4ZZI_HtoS_PSEUDO) + .value("BFMLSL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4ZZ_HtoS_PSEUDO) + .value("BFMLS_VG2_M2Z2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2Z2Z_PSEUDO) + .value("BFMLS_VG2_M2ZZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2ZZI_PSEUDO) + .value("BFMLS_VG2_M2ZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2ZZ_PSEUDO) + .value("BFMLS_VG4_M4Z4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4Z4Z_PSEUDO) + .value("BFMLS_VG4_M4ZZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4ZZI_PSEUDO) + .value("BFMLS_VG4_M4ZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4ZZ_PSEUDO) + .value("BFMLS_ZPZZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMLS_ZPZZZ_UNDEF) + .value("BFMOP4A_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2Z2Z_H_PSEUDO) + .value("BFMOP4A_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2Z2Z_S_PSEUDO) + .value("BFMOP4A_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2ZZ_H_PSEUDO) + .value("BFMOP4A_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2ZZ_S_PSEUDO) + .value("BFMOP4A_MZ2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZ2Z_H_PSEUDO) + .value("BFMOP4A_MZ2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZ2Z_S_PSEUDO) + .value("BFMOP4A_MZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZZ_H_PSEUDO) + .value("BFMOP4A_MZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZZ_S_PSEUDO) + .value("BFMOP4S_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2Z2Z_H_PSEUDO) + .value("BFMOP4S_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2Z2Z_S_PSEUDO) + .value("BFMOP4S_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2ZZ_H_PSEUDO) + .value("BFMOP4S_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2ZZ_S_PSEUDO) + .value("BFMOP4S_MZ2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZ2Z_H_PSEUDO) + .value("BFMOP4S_MZ2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZ2Z_S_PSEUDO) + .value("BFMOP4S_MZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZZ_H_PSEUDO) + .value("BFMOP4S_MZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZZ_S_PSEUDO) + .value("BFMOPA_MPPZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOPA_MPPZZ_H_PSEUDO) + .value("BFMOPA_MPPZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOPA_MPPZZ_PSEUDO) + .value("BFMOPS_MPPZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOPS_MPPZZ_H_PSEUDO) + .value("BFMOPS_MPPZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFMOPS_MPPZZ_PSEUDO) + .value("BFMUL_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFMUL_ZPZZ_UNDEF) + .value("BFMUL_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFMUL_ZPZZ_ZERO) + .value("BFSUB_VG2_M2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFSUB_VG2_M2Z_H_PSEUDO) + .value("BFSUB_VG4_M4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFSUB_VG4_M4Z_H_PSEUDO) + .value("BFSUB_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFSUB_ZPZZ_UNDEF) + .value("BFSUB_ZPZZ_ZERO", LIEF::assembly::aarch64::OPCODE::BFSUB_ZPZZ_ZERO) + .value("BFTMOPA_M2ZZZI_HtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFTMOPA_M2ZZZI_HtoH_PSEUDO) + .value("BFTMOPA_M2ZZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFTMOPA_M2ZZZI_HtoS_PSEUDO) + .value("BFVDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFVDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("BICSWrr", LIEF::assembly::aarch64::OPCODE::BICSWrr) + .value("BICSXrr", LIEF::assembly::aarch64::OPCODE::BICSXrr) + .value("BICWrr", LIEF::assembly::aarch64::OPCODE::BICWrr) + .value("BICXrr", LIEF::assembly::aarch64::OPCODE::BICXrr) + .value("BIC_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::BIC_ZPZZ_B_ZERO) + .value("BIC_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::BIC_ZPZZ_D_ZERO) + .value("BIC_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::BIC_ZPZZ_H_ZERO) + .value("BIC_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::BIC_ZPZZ_S_ZERO) + .value("BLRA", LIEF::assembly::aarch64::OPCODE::BLRA) + .value("BLRA_RVMARKER", LIEF::assembly::aarch64::OPCODE::BLRA_RVMARKER) + .value("BLRNoIP", LIEF::assembly::aarch64::OPCODE::BLRNoIP) + .value("BLR_BTI", LIEF::assembly::aarch64::OPCODE::BLR_BTI) + .value("BLR_RVMARKER", LIEF::assembly::aarch64::OPCODE::BLR_RVMARKER) + .value("BLR_X16", LIEF::assembly::aarch64::OPCODE::BLR_X16) + .value("BMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BMOPA_MPPZZ_S_PSEUDO) + .value("BMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::BMOPS_MPPZZ_S_PSEUDO) + .value("BRA", LIEF::assembly::aarch64::OPCODE::BRA) + .value("BR_JumpTable", LIEF::assembly::aarch64::OPCODE::BR_JumpTable) + .value("BSPv16i8", LIEF::assembly::aarch64::OPCODE::BSPv16i8) + .value("BSPv8i8", LIEF::assembly::aarch64::OPCODE::BSPv8i8) + .value("CATCHRET", LIEF::assembly::aarch64::OPCODE::CATCHRET) + .value("CBBAssertExt", LIEF::assembly::aarch64::OPCODE::CBBAssertExt) + .value("CBHAssertExt", LIEF::assembly::aarch64::OPCODE::CBHAssertExt) + .value("CBWPri", LIEF::assembly::aarch64::OPCODE::CBWPri) + .value("CBWPrr", LIEF::assembly::aarch64::OPCODE::CBWPrr) + .value("CBXPri", LIEF::assembly::aarch64::OPCODE::CBXPri) + .value("CBXPrr", LIEF::assembly::aarch64::OPCODE::CBXPrr) + .value("CHECK_MATCHING_VL_PSEUDO", LIEF::assembly::aarch64::OPCODE::CHECK_MATCHING_VL_PSEUDO) + .value("CLEANUPRET", LIEF::assembly::aarch64::OPCODE::CLEANUPRET) + .value("CLS_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_B_UNDEF) + .value("CLS_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_D_UNDEF) + .value("CLS_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_H_UNDEF) + .value("CLS_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_S_UNDEF) + .value("CLZ_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_B_UNDEF) + .value("CLZ_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_D_UNDEF) + .value("CLZ_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_H_UNDEF) + .value("CLZ_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_S_UNDEF) + .value("CMP_SWAP_128", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_128) + .value("CMP_SWAP_128_ACQUIRE", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_128_ACQUIRE) + .value("CMP_SWAP_128_MONOTONIC", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_128_MONOTONIC) + .value("CMP_SWAP_128_RELEASE", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_128_RELEASE) + .value("CMP_SWAP_16", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_16) + .value("CMP_SWAP_32", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_32) + .value("CMP_SWAP_64", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_64) + .value("CMP_SWAP_8", LIEF::assembly::aarch64::OPCODE::CMP_SWAP_8) + .value("CNOT_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_B_UNDEF) + .value("CNOT_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_D_UNDEF) + .value("CNOT_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_H_UNDEF) + .value("CNOT_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_S_UNDEF) + .value("CNT_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_B_UNDEF) + .value("CNT_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_D_UNDEF) + .value("CNT_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_H_UNDEF) + .value("CNT_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_S_UNDEF) + .value("COALESCER_BARRIER_FPR128", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR128) + .value("COALESCER_BARRIER_FPR16", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR16) + .value("COALESCER_BARRIER_FPR32", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR32) + .value("COALESCER_BARRIER_FPR64", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR64) + .value("CommitZASavePseudo", LIEF::assembly::aarch64::OPCODE::CommitZASavePseudo) + .value("EMITBKEY", LIEF::assembly::aarch64::OPCODE::EMITBKEY) + .value("EMITMTETAGGED", LIEF::assembly::aarch64::OPCODE::EMITMTETAGGED) + .value("EONWrr", LIEF::assembly::aarch64::OPCODE::EONWrr) + .value("EONXrr", LIEF::assembly::aarch64::OPCODE::EONXrr) + .value("EORWrr", LIEF::assembly::aarch64::OPCODE::EORWrr) + .value("EORXrr", LIEF::assembly::aarch64::OPCODE::EORXrr) + .value("EOR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_B_ZERO) + .value("EOR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_D_ZERO) + .value("EOR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_H_ZERO) + .value("EOR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_S_ZERO) + .value("EXT_ZZI_CONSTRUCTIVE", LIEF::assembly::aarch64::OPCODE::EXT_ZZI_CONSTRUCTIVE) + .value("EntryPStateSM", LIEF::assembly::aarch64::OPCODE::EntryPStateSM) + .value("F128CSEL", LIEF::assembly::aarch64::OPCODE::F128CSEL) + .value("FABD_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_D_UNDEF) + .value("FABD_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_D_ZERO) + .value("FABD_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_H_UNDEF) + .value("FABD_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_H_ZERO) + .value("FABD_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_S_UNDEF) + .value("FABD_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FABD_ZPZZ_S_ZERO) + .value("FABS_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_D_UNDEF) + .value("FABS_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_H_UNDEF) + .value("FABS_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_S_UNDEF) + .value("FADD_VG2_M2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_D_PSEUDO) + .value("FADD_VG2_M2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_H_PSEUDO) + .value("FADD_VG2_M2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_S_PSEUDO) + .value("FADD_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_D_PSEUDO) + .value("FADD_VG4_M4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_H_PSEUDO) + .value("FADD_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_S_PSEUDO) + .value("FADD_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_D_UNDEF) + .value("FADD_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_D_ZERO) + .value("FADD_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_H_UNDEF) + .value("FADD_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_H_ZERO) + .value("FADD_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_S_UNDEF) + .value("FADD_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZI_S_ZERO) + .value("FADD_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_D_UNDEF) + .value("FADD_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_D_ZERO) + .value("FADD_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_H_UNDEF) + .value("FADD_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_H_ZERO) + .value("FADD_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_S_UNDEF) + .value("FADD_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FADD_ZPZZ_S_ZERO) + .value("FAMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPZZ_D_UNDEF) + .value("FAMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPZZ_H_UNDEF) + .value("FAMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPZZ_S_UNDEF) + .value("FAMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPZZ_D_UNDEF) + .value("FAMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPZZ_H_UNDEF) + .value("FAMIN_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPZZ_S_UNDEF) + .value("FCVTZS_ZPmZ_DtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_DtoD_UNDEF) + .value("FCVTZS_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_DtoS_UNDEF) + .value("FCVTZS_ZPmZ_HtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoD_UNDEF) + .value("FCVTZS_ZPmZ_HtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoH_UNDEF) + .value("FCVTZS_ZPmZ_HtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoS_UNDEF) + .value("FCVTZS_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_StoD_UNDEF) + .value("FCVTZS_ZPmZ_StoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_StoS_UNDEF) + .value("FCVTZU_ZPmZ_DtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_DtoD_UNDEF) + .value("FCVTZU_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_DtoS_UNDEF) + .value("FCVTZU_ZPmZ_HtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoD_UNDEF) + .value("FCVTZU_ZPmZ_HtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoH_UNDEF) + .value("FCVTZU_ZPmZ_HtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoS_UNDEF) + .value("FCVTZU_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoD_UNDEF) + .value("FCVTZU_ZPmZ_StoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoS_UNDEF) + .value("FCVT_ZPmZ_DtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoH_UNDEF) + .value("FCVT_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoS_UNDEF) + .value("FCVT_ZPmZ_HtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoD_UNDEF) + .value("FCVT_ZPmZ_HtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoS_UNDEF) + .value("FCVT_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoD_UNDEF) + .value("FCVT_ZPmZ_StoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoH_UNDEF) + .value("FDIVR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPZZ_D_ZERO) + .value("FDIVR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPZZ_H_ZERO) + .value("FDIVR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPZZ_S_ZERO) + .value("FDIV_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_D_UNDEF) + .value("FDIV_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_D_ZERO) + .value("FDIV_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_H_UNDEF) + .value("FDIV_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_H_ZERO) + .value("FDIV_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_S_UNDEF) + .value("FDIV_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_S_ZERO); + opcodes.value("FDOT_VG2_M2Z2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoH_PSEUDO) + .value("FDOT_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoS_PSEUDO) + .value("FDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_HtoS_PSEUDO) + .value("FDOT_VG2_M2ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_BtoH_PSEUDO) + .value("FDOT_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_BtoS_PSEUDO) + .value("FDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("FDOT_VG2_M2ZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_BtoH_PSEUDO) + .value("FDOT_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_BtoS_PSEUDO) + .value("FDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_HtoS_PSEUDO) + .value("FDOT_VG4_M4Z4Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_BtoH_PSEUDO) + .value("FDOT_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_BtoS_PSEUDO) + .value("FDOT_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_HtoS_PSEUDO) + .value("FDOT_VG4_M4ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_BtoH_PSEUDO) + .value("FDOT_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_BtoS_PSEUDO) + .value("FDOT_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_HtoS_PSEUDO) + .value("FDOT_VG4_M4ZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_BtoH_PSEUDO) + .value("FDOT_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_BtoS_PSEUDO) + .value("FDOT_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_HtoS_PSEUDO) + .value("FLOGB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPZZ_D_ZERO) + .value("FLOGB_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPZZ_H_ZERO) + .value("FLOGB_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPZZ_S_ZERO) + .value("FMAXNM_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_D_UNDEF) + .value("FMAXNM_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_D_ZERO) + .value("FMAXNM_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_H_UNDEF) + .value("FMAXNM_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_H_ZERO) + .value("FMAXNM_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_S_UNDEF) + .value("FMAXNM_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZI_S_ZERO) + .value("FMAXNM_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_D_UNDEF) + .value("FMAXNM_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_D_ZERO) + .value("FMAXNM_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_H_UNDEF) + .value("FMAXNM_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_H_ZERO) + .value("FMAXNM_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_S_UNDEF) + .value("FMAXNM_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPZZ_S_ZERO) + .value("FMAX_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_D_UNDEF) + .value("FMAX_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_D_ZERO) + .value("FMAX_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_H_UNDEF) + .value("FMAX_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_H_ZERO) + .value("FMAX_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_S_UNDEF) + .value("FMAX_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZI_S_ZERO) + .value("FMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_D_UNDEF) + .value("FMAX_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_D_ZERO) + .value("FMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_H_UNDEF) + .value("FMAX_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_H_ZERO) + .value("FMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_S_UNDEF) + .value("FMAX_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMAX_ZPZZ_S_ZERO) + .value("FMINNM_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_D_UNDEF) + .value("FMINNM_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_D_ZERO) + .value("FMINNM_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_H_UNDEF) + .value("FMINNM_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_H_ZERO) + .value("FMINNM_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_S_UNDEF) + .value("FMINNM_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZI_S_ZERO) + .value("FMINNM_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_D_UNDEF) + .value("FMINNM_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_D_ZERO) + .value("FMINNM_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_H_UNDEF) + .value("FMINNM_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_H_ZERO) + .value("FMINNM_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_S_UNDEF) + .value("FMINNM_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPZZ_S_ZERO) + .value("FMIN_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_D_UNDEF) + .value("FMIN_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_D_ZERO) + .value("FMIN_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_H_UNDEF) + .value("FMIN_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_H_ZERO) + .value("FMIN_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_S_UNDEF) + .value("FMIN_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZI_S_ZERO) + .value("FMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_D_UNDEF) + .value("FMIN_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_D_ZERO) + .value("FMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_H_UNDEF) + .value("FMIN_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_H_ZERO) + .value("FMIN_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_S_UNDEF) + .value("FMIN_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMIN_ZPZZ_S_ZERO) + .value("FMLALL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_MZZI_BtoS_PSEUDO) + .value("FMLALL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_MZZ_BtoS_PSEUDO) + .value("FMLALL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("FMLALL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZI_BtoS_PSEUDO) + .value("FMLALL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZ_BtoS_PSEUDO) + .value("FMLALL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("FMLALL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZI_BtoS_PSEUDO) + .value("FMLALL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZ_BtoS_PSEUDO) + .value("FMLAL_MZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZI_BtoH_PSEUDO) + .value("FMLAL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZI_HtoS_PSEUDO) + .value("FMLAL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZ_HtoS_PSEUDO) + .value("FMLAL_VG2_M2Z2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2Z2Z_BtoH_PSEUDO) + .value("FMLAL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("FMLAL_VG2_M2ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZI_BtoH_PSEUDO) + .value("FMLAL_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZI_HtoS_PSEUDO) + .value("FMLAL_VG2_M2ZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZ_BtoH_PSEUDO) + .value("FMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZ_HtoS_PSEUDO) + .value("FMLAL_VG2_MZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_MZZ_BtoH_PSEUDO) + .value("FMLAL_VG4_M4Z4Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4Z4Z_BtoH_PSEUDO) + .value("FMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("FMLAL_VG4_M4ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZI_BtoH_PSEUDO) + .value("FMLAL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZI_HtoS_PSEUDO) + .value("FMLAL_VG4_M4ZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZ_BtoH_PSEUDO) + .value("FMLAL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZ_HtoS_PSEUDO) + .value("FMLA_VG2_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_D_PSEUDO) + .value("FMLA_VG2_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_H_PSEUDO) + .value("FMLA_VG2_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_S_PSEUDO) + .value("FMLA_VG2_M2ZZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_D_PSEUDO) + .value("FMLA_VG2_M2ZZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_H_PSEUDO) + .value("FMLA_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_S_PSEUDO) + .value("FMLA_VG2_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_D_PSEUDO) + .value("FMLA_VG2_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_H_PSEUDO) + .value("FMLA_VG2_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_S_PSEUDO) + .value("FMLA_VG4_M4Z4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_D_PSEUDO) + .value("FMLA_VG4_M4Z4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_H_PSEUDO) + .value("FMLA_VG4_M4Z4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_S_PSEUDO) + .value("FMLA_VG4_M4ZZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_D_PSEUDO) + .value("FMLA_VG4_M4ZZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_H_PSEUDO) + .value("FMLA_VG4_M4ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_S_PSEUDO) + .value("FMLA_VG4_M4ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_D_PSEUDO) + .value("FMLA_VG4_M4ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_H_PSEUDO) + .value("FMLA_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_S_PSEUDO) + .value("FMLA_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLA_ZPZZZ_D_UNDEF) + .value("FMLA_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLA_ZPZZZ_H_UNDEF) + .value("FMLA_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLA_ZPZZZ_S_UNDEF) + .value("FMLSL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_MZZI_HtoS_PSEUDO) + .value("FMLSL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_MZZ_HtoS_PSEUDO) + .value("FMLSL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("FMLSL_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2ZZI_HtoS_PSEUDO) + .value("FMLSL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2ZZ_HtoS_PSEUDO) + .value("FMLSL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("FMLSL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4ZZI_HtoS_PSEUDO) + .value("FMLSL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4ZZ_HtoS_PSEUDO) + .value("FMLS_VG2_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_D_PSEUDO) + .value("FMLS_VG2_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_H_PSEUDO) + .value("FMLS_VG2_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_S_PSEUDO) + .value("FMLS_VG2_M2ZZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_D_PSEUDO) + .value("FMLS_VG2_M2ZZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_H_PSEUDO) + .value("FMLS_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_S_PSEUDO) + .value("FMLS_VG2_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_D_PSEUDO) + .value("FMLS_VG2_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_H_PSEUDO) + .value("FMLS_VG2_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_S_PSEUDO) + .value("FMLS_VG4_M4Z4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_D_PSEUDO) + .value("FMLS_VG4_M4Z4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_H_PSEUDO) + .value("FMLS_VG4_M4Z4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_S_PSEUDO) + .value("FMLS_VG4_M4ZZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_D_PSEUDO) + .value("FMLS_VG4_M4ZZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_H_PSEUDO) + .value("FMLS_VG4_M4ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_S_PSEUDO) + .value("FMLS_VG4_M4ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_D_PSEUDO) + .value("FMLS_VG4_M4ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_H_PSEUDO) + .value("FMLS_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_S_PSEUDO) + .value("FMLS_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLS_ZPZZZ_D_UNDEF) + .value("FMLS_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLS_ZPZZZ_H_UNDEF) + .value("FMLS_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMLS_ZPZZZ_S_UNDEF) + .value("FMOP4A_M2Z2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_BtoH_PSEUDO) + .value("FMOP4A_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_BtoS_PSEUDO) + .value("FMOP4A_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_D_PSEUDO) + .value("FMOP4A_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_H_PSEUDO) + .value("FMOP4A_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_HtoS_PSEUDO) + .value("FMOP4A_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_S_PSEUDO) + .value("FMOP4A_M2ZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_BtoH_PSEUDO) + .value("FMOP4A_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_BtoS_PSEUDO) + .value("FMOP4A_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_D_PSEUDO) + .value("FMOP4A_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_H_PSEUDO) + .value("FMOP4A_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_HtoS_PSEUDO) + .value("FMOP4A_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_S_PSEUDO) + .value("FMOP4A_MZ2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_BtoH_PSEUDO) + .value("FMOP4A_MZ2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_BtoS_PSEUDO) + .value("FMOP4A_MZ2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_D_PSEUDO) + .value("FMOP4A_MZ2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_H_PSEUDO) + .value("FMOP4A_MZ2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_HtoS_PSEUDO) + .value("FMOP4A_MZ2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_S_PSEUDO) + .value("FMOP4A_MZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_BtoH_PSEUDO) + .value("FMOP4A_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_BtoS_PSEUDO) + .value("FMOP4A_MZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_D_PSEUDO) + .value("FMOP4A_MZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_H_PSEUDO) + .value("FMOP4A_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_HtoS_PSEUDO) + .value("FMOP4A_MZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_S_PSEUDO) + .value("FMOP4S_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_D_PSEUDO) + .value("FMOP4S_M2Z2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_H_PSEUDO) + .value("FMOP4S_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_HtoS_PSEUDO) + .value("FMOP4S_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_S_PSEUDO) + .value("FMOP4S_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_D_PSEUDO) + .value("FMOP4S_M2ZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_H_PSEUDO) + .value("FMOP4S_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_HtoS_PSEUDO) + .value("FMOP4S_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_S_PSEUDO) + .value("FMOP4S_MZ2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_D_PSEUDO) + .value("FMOP4S_MZ2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_H_PSEUDO) + .value("FMOP4S_MZ2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_HtoS_PSEUDO) + .value("FMOP4S_MZ2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_S_PSEUDO) + .value("FMOP4S_MZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_D_PSEUDO) + .value("FMOP4S_MZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_H_PSEUDO) + .value("FMOP4S_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_HtoS_PSEUDO) + .value("FMOP4S_MZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_S_PSEUDO) + .value("FMOPAL_MPPZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPAL_MPPZZ_PSEUDO) + .value("FMOPA_MPPZZ_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_BtoH_PSEUDO) + .value("FMOPA_MPPZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_BtoS_PSEUDO) + .value("FMOPA_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_D_PSEUDO) + .value("FMOPA_MPPZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_H_PSEUDO) + .value("FMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_S_PSEUDO) + .value("FMOPSL_MPPZZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPSL_MPPZZ_PSEUDO) + .value("FMOPS_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_D_PSEUDO) + .value("FMOPS_MPPZZ_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_H_PSEUDO) + .value("FMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_S_PSEUDO) + .value("FMOVD0", LIEF::assembly::aarch64::OPCODE::FMOVD0) + .value("FMOVH0", LIEF::assembly::aarch64::OPCODE::FMOVH0) + .value("FMOVS0", LIEF::assembly::aarch64::OPCODE::FMOVS0) + .value("FMULX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_D_UNDEF) + .value("FMULX_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_D_ZERO) + .value("FMULX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_H_UNDEF) + .value("FMULX_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_H_ZERO) + .value("FMULX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_S_UNDEF) + .value("FMULX_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMULX_ZPZZ_S_ZERO) + .value("FMUL_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_D_UNDEF) + .value("FMUL_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_D_ZERO) + .value("FMUL_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_H_UNDEF) + .value("FMUL_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_H_ZERO) + .value("FMUL_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_S_UNDEF) + .value("FMUL_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZI_S_ZERO) + .value("FMUL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_D_UNDEF) + .value("FMUL_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_D_ZERO) + .value("FMUL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_H_UNDEF) + .value("FMUL_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_H_ZERO) + .value("FMUL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_S_UNDEF) + .value("FMUL_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FMUL_ZPZZ_S_ZERO) + .value("FNEG_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_D_UNDEF) + .value("FNEG_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_H_UNDEF) + .value("FNEG_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_S_UNDEF) + .value("FNMLA_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPZZZ_D_UNDEF) + .value("FNMLA_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPZZZ_H_UNDEF) + .value("FNMLA_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPZZZ_S_UNDEF) + .value("FNMLS_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPZZZ_D_UNDEF) + .value("FNMLS_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPZZZ_H_UNDEF) + .value("FNMLS_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPZZZ_S_UNDEF) + .value("FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO", LIEF::assembly::aarch64::OPCODE::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO) + .value("FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO", LIEF::assembly::aarch64::OPCODE::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO) + .value("FRECPX_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_D_UNDEF) + .value("FRECPX_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_H_UNDEF) + .value("FRECPX_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_S_UNDEF) + .value("FRINT32X_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPmZ_D_UNDEF) + .value("FRINT32X_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPmZ_S_UNDEF) + .value("FRINT32Z_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPmZ_D_UNDEF) + .value("FRINT32Z_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPmZ_S_UNDEF) + .value("FRINT64X_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPmZ_D_UNDEF) + .value("FRINT64X_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPmZ_S_UNDEF) + .value("FRINT64Z_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPmZ_D_UNDEF) + .value("FRINT64Z_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPmZ_S_UNDEF) + .value("FRINTA_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_D_UNDEF) + .value("FRINTA_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_H_UNDEF) + .value("FRINTA_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_S_UNDEF) + .value("FRINTI_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_D_UNDEF) + .value("FRINTI_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_H_UNDEF) + .value("FRINTI_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_S_UNDEF) + .value("FRINTM_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_D_UNDEF) + .value("FRINTM_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_H_UNDEF) + .value("FRINTM_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_S_UNDEF) + .value("FRINTN_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_D_UNDEF) + .value("FRINTN_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_H_UNDEF) + .value("FRINTN_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_S_UNDEF) + .value("FRINTP_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_D_UNDEF) + .value("FRINTP_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_H_UNDEF) + .value("FRINTP_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_S_UNDEF) + .value("FRINTX_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_D_UNDEF) + .value("FRINTX_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_H_UNDEF) + .value("FRINTX_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_S_UNDEF) + .value("FRINTZ_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_D_UNDEF) + .value("FRINTZ_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_H_UNDEF) + .value("FRINTZ_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_S_UNDEF) + .value("FSQRT_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_D_UNDEF) + .value("FSQRT_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_H_UNDEF) + .value("FSQRT_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_S_UNDEF) + .value("FSUBR_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_D_UNDEF) + .value("FSUBR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_D_ZERO) + .value("FSUBR_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_H_UNDEF) + .value("FSUBR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_H_ZERO) + .value("FSUBR_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_S_UNDEF) + .value("FSUBR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZI_S_ZERO) + .value("FSUBR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZZ_D_ZERO) + .value("FSUBR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZZ_H_ZERO) + .value("FSUBR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPZZ_S_ZERO) + .value("FSUB_VG2_M2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_D_PSEUDO) + .value("FSUB_VG2_M2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_H_PSEUDO) + .value("FSUB_VG2_M2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_S_PSEUDO) + .value("FSUB_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_D_PSEUDO) + .value("FSUB_VG4_M4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_H_PSEUDO) + .value("FSUB_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_S_PSEUDO) + .value("FSUB_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_D_UNDEF) + .value("FSUB_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_D_ZERO) + .value("FSUB_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_H_UNDEF) + .value("FSUB_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_H_ZERO) + .value("FSUB_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_S_UNDEF) + .value("FSUB_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_S_ZERO) + .value("FSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_D_UNDEF) + .value("FSUB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_D_ZERO) + .value("FSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_H_UNDEF) + .value("FSUB_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_H_ZERO) + .value("FSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_S_UNDEF) + .value("FSUB_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_S_ZERO) + .value("FTMOPA_M2ZZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_BtoH_PSEUDO) + .value("FTMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_BtoS_PSEUDO) + .value("FTMOPA_M2ZZZI_HtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_HtoH_PSEUDO) + .value("FTMOPA_M2ZZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_HtoS_PSEUDO) + .value("FTMOPA_M2ZZZI_StoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_StoS_PSEUDO) + .value("FVDOTB_VG4_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FVDOTB_VG4_M2ZZI_BtoS_PSEUDO) + .value("FVDOTT_VG4_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FVDOTT_VG4_M2ZZI_BtoS_PSEUDO) + .value("FVDOT_VG2_M2ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FVDOT_VG2_M2ZZI_BtoH_PSEUDO) + .value("FVDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FVDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("G_AARCH64_PREFETCH", LIEF::assembly::aarch64::OPCODE::G_AARCH64_PREFETCH) + .value("G_AARCH64_RANGE_PREFETCH", LIEF::assembly::aarch64::OPCODE::G_AARCH64_RANGE_PREFETCH) + .value("G_ADD_LOW", LIEF::assembly::aarch64::OPCODE::G_ADD_LOW) + .value("G_BSP", LIEF::assembly::aarch64::OPCODE::G_BSP); + opcodes.value("G_DUP", LIEF::assembly::aarch64::OPCODE::G_DUP) + .value("G_DUPLANE16", LIEF::assembly::aarch64::OPCODE::G_DUPLANE16) + .value("G_DUPLANE32", LIEF::assembly::aarch64::OPCODE::G_DUPLANE32) + .value("G_DUPLANE64", LIEF::assembly::aarch64::OPCODE::G_DUPLANE64) + .value("G_DUPLANE8", LIEF::assembly::aarch64::OPCODE::G_DUPLANE8) + .value("G_EXT", LIEF::assembly::aarch64::OPCODE::G_EXT) + .value("G_FCMEQ", LIEF::assembly::aarch64::OPCODE::G_FCMEQ) + .value("G_FCMGE", LIEF::assembly::aarch64::OPCODE::G_FCMGE) + .value("G_FCMGT", LIEF::assembly::aarch64::OPCODE::G_FCMGT) + .value("G_FPTRUNC_ODD", LIEF::assembly::aarch64::OPCODE::G_FPTRUNC_ODD) + .value("G_PMULL", LIEF::assembly::aarch64::OPCODE::G_PMULL) + .value("G_REV16", LIEF::assembly::aarch64::OPCODE::G_REV16) + .value("G_REV32", LIEF::assembly::aarch64::OPCODE::G_REV32) + .value("G_REV64", LIEF::assembly::aarch64::OPCODE::G_REV64) + .value("G_SADDLP", LIEF::assembly::aarch64::OPCODE::G_SADDLP) + .value("G_SADDLV", LIEF::assembly::aarch64::OPCODE::G_SADDLV) + .value("G_SDOT", LIEF::assembly::aarch64::OPCODE::G_SDOT) + .value("G_SITOF", LIEF::assembly::aarch64::OPCODE::G_SITOF) + .value("G_SLI", LIEF::assembly::aarch64::OPCODE::G_SLI) + .value("G_SMULL", LIEF::assembly::aarch64::OPCODE::G_SMULL) + .value("G_SQSHLU_I", LIEF::assembly::aarch64::OPCODE::G_SQSHLU_I) + .value("G_SRI", LIEF::assembly::aarch64::OPCODE::G_SRI) + .value("G_SRSHR_I", LIEF::assembly::aarch64::OPCODE::G_SRSHR_I) + .value("G_TRN1", LIEF::assembly::aarch64::OPCODE::G_TRN1) + .value("G_TRN2", LIEF::assembly::aarch64::OPCODE::G_TRN2) + .value("G_UADDLP", LIEF::assembly::aarch64::OPCODE::G_UADDLP) + .value("G_UADDLV", LIEF::assembly::aarch64::OPCODE::G_UADDLV) + .value("G_UDOT", LIEF::assembly::aarch64::OPCODE::G_UDOT) + .value("G_UITOF", LIEF::assembly::aarch64::OPCODE::G_UITOF) + .value("G_UMULL", LIEF::assembly::aarch64::OPCODE::G_UMULL) + .value("G_URSHR_I", LIEF::assembly::aarch64::OPCODE::G_URSHR_I) + .value("G_USDOT", LIEF::assembly::aarch64::OPCODE::G_USDOT) + .value("G_UZP1", LIEF::assembly::aarch64::OPCODE::G_UZP1) + .value("G_UZP2", LIEF::assembly::aarch64::OPCODE::G_UZP2) + .value("G_VASHR", LIEF::assembly::aarch64::OPCODE::G_VASHR) + .value("G_VLSHR", LIEF::assembly::aarch64::OPCODE::G_VLSHR) + .value("G_ZIP1", LIEF::assembly::aarch64::OPCODE::G_ZIP1) + .value("G_ZIP2", LIEF::assembly::aarch64::OPCODE::G_ZIP2) + .value("GetSMESaveSize", LIEF::assembly::aarch64::OPCODE::GetSMESaveSize) + .value("HOM_Epilog", LIEF::assembly::aarch64::OPCODE::HOM_Epilog) + .value("HOM_Prolog", LIEF::assembly::aarch64::OPCODE::HOM_Prolog) + .value("HWASAN_CHECK_MEMACCESS", LIEF::assembly::aarch64::OPCODE::HWASAN_CHECK_MEMACCESS) + .value("HWASAN_CHECK_MEMACCESS_FIXEDSHADOW", LIEF::assembly::aarch64::OPCODE::HWASAN_CHECK_MEMACCESS_FIXEDSHADOW) + .value("HWASAN_CHECK_MEMACCESS_SHORTGRANULES", LIEF::assembly::aarch64::OPCODE::HWASAN_CHECK_MEMACCESS_SHORTGRANULES) + .value("HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW", LIEF::assembly::aarch64::OPCODE::HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW) + .value("INSERT_MXIPZ_H_PSEUDO_B", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_PSEUDO_B) + .value("INSERT_MXIPZ_H_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_PSEUDO_D) + .value("INSERT_MXIPZ_H_PSEUDO_H", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_PSEUDO_H) + .value("INSERT_MXIPZ_H_PSEUDO_Q", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_PSEUDO_Q) + .value("INSERT_MXIPZ_H_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_PSEUDO_S) + .value("INSERT_MXIPZ_V_PSEUDO_B", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_B) + .value("INSERT_MXIPZ_V_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_D) + .value("INSERT_MXIPZ_V_PSEUDO_H", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_H) + .value("INSERT_MXIPZ_V_PSEUDO_Q", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_Q) + .value("INSERT_MXIPZ_V_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_S) + .value("IRGstack", LIEF::assembly::aarch64::OPCODE::IRGstack) + .value("InOutZAUsePseudo", LIEF::assembly::aarch64::OPCODE::InOutZAUsePseudo) + .value("InitTPIDR2Obj", LIEF::assembly::aarch64::OPCODE::InitTPIDR2Obj) + .value("JumpTableDest16", LIEF::assembly::aarch64::OPCODE::JumpTableDest16) + .value("JumpTableDest32", LIEF::assembly::aarch64::OPCODE::JumpTableDest32) + .value("JumpTableDest8", LIEF::assembly::aarch64::OPCODE::JumpTableDest8) + .value("KCFI_CHECK", LIEF::assembly::aarch64::OPCODE::KCFI_CHECK) + .value("LD1B_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1B_2Z_IMM_PSEUDO) + .value("LD1B_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1B_2Z_PSEUDO) + .value("LD1B_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1B_4Z_IMM_PSEUDO) + .value("LD1B_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1B_4Z_PSEUDO) + .value("LD1D_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1D_2Z_IMM_PSEUDO) + .value("LD1D_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1D_2Z_PSEUDO) + .value("LD1D_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1D_4Z_IMM_PSEUDO) + .value("LD1D_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1D_4Z_PSEUDO) + .value("LD1H_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1H_2Z_IMM_PSEUDO) + .value("LD1H_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1H_2Z_PSEUDO) + .value("LD1H_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1H_4Z_IMM_PSEUDO) + .value("LD1H_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1H_4Z_PSEUDO) + .value("LD1W_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1W_2Z_IMM_PSEUDO) + .value("LD1W_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1W_2Z_PSEUDO) + .value("LD1W_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1W_4Z_IMM_PSEUDO) + .value("LD1W_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LD1W_4Z_PSEUDO) + .value("LD1_MXIPXX_H_PSEUDO_B", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_PSEUDO_B) + .value("LD1_MXIPXX_H_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_PSEUDO_D) + .value("LD1_MXIPXX_H_PSEUDO_H", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_PSEUDO_H) + .value("LD1_MXIPXX_H_PSEUDO_Q", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_PSEUDO_Q) + .value("LD1_MXIPXX_H_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_PSEUDO_S) + .value("LD1_MXIPXX_V_PSEUDO_B", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_PSEUDO_B) + .value("LD1_MXIPXX_V_PSEUDO_D", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_PSEUDO_D) + .value("LD1_MXIPXX_V_PSEUDO_H", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_PSEUDO_H) + .value("LD1_MXIPXX_V_PSEUDO_Q", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_PSEUDO_Q) + .value("LD1_MXIPXX_V_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_PSEUDO_S) + .value("LDNT1B_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z_IMM_PSEUDO) + .value("LDNT1B_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z_PSEUDO) + .value("LDNT1B_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z_IMM_PSEUDO) + .value("LDNT1B_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z_PSEUDO) + .value("LDNT1D_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z_IMM_PSEUDO) + .value("LDNT1D_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z_PSEUDO) + .value("LDNT1D_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z_IMM_PSEUDO) + .value("LDNT1D_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z_PSEUDO) + .value("LDNT1H_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z_IMM_PSEUDO) + .value("LDNT1H_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z_PSEUDO) + .value("LDNT1H_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z_IMM_PSEUDO) + .value("LDNT1H_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z_PSEUDO) + .value("LDNT1W_2Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z_IMM_PSEUDO) + .value("LDNT1W_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z_PSEUDO) + .value("LDNT1W_4Z_IMM_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z_IMM_PSEUDO) + .value("LDNT1W_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z_PSEUDO) + .value("LDR_PPXI", LIEF::assembly::aarch64::OPCODE::LDR_PPXI) + .value("LDR_TX_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDR_TX_PSEUDO) + .value("LDR_ZA_PSEUDO", LIEF::assembly::aarch64::OPCODE::LDR_ZA_PSEUDO) + .value("LDR_ZZXI", LIEF::assembly::aarch64::OPCODE::LDR_ZZXI) + .value("LDR_ZZXI_STRIDED_CONTIGUOUS", LIEF::assembly::aarch64::OPCODE::LDR_ZZXI_STRIDED_CONTIGUOUS) + .value("LDR_ZZZXI", LIEF::assembly::aarch64::OPCODE::LDR_ZZZXI) + .value("LDR_ZZZZXI", LIEF::assembly::aarch64::OPCODE::LDR_ZZZZXI) + .value("LDR_ZZZZXI_STRIDED_CONTIGUOUS", LIEF::assembly::aarch64::OPCODE::LDR_ZZZZXI_STRIDED_CONTIGUOUS) + .value("LOADauthptrstatic", LIEF::assembly::aarch64::OPCODE::LOADauthptrstatic) + .value("LOADgot", LIEF::assembly::aarch64::OPCODE::LOADgot) + .value("LOADgotAUTH", LIEF::assembly::aarch64::OPCODE::LOADgotAUTH) + .value("LOADgotPAC", LIEF::assembly::aarch64::OPCODE::LOADgotPAC) + .value("LSL_ZPZI_B_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_B_UNDEF) + .value("LSL_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_B_ZERO) + .value("LSL_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_D_UNDEF) + .value("LSL_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_D_ZERO) + .value("LSL_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_H_UNDEF) + .value("LSL_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_H_ZERO) + .value("LSL_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_S_UNDEF) + .value("LSL_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZI_S_ZERO) + .value("LSL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_B_UNDEF) + .value("LSL_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_B_ZERO) + .value("LSL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_D_UNDEF) + .value("LSL_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_D_ZERO) + .value("LSL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_H_UNDEF) + .value("LSL_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_H_ZERO) + .value("LSL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_S_UNDEF) + .value("LSL_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::LSL_ZPZZ_S_ZERO) + .value("LSR_ZPZI_B_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_B_UNDEF) + .value("LSR_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_B_ZERO) + .value("LSR_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_D_UNDEF) + .value("LSR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_D_ZERO) + .value("LSR_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_H_UNDEF) + .value("LSR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_H_ZERO) + .value("LSR_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_S_UNDEF) + .value("LSR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZI_S_ZERO) + .value("LSR_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_B_UNDEF) + .value("LSR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_B_ZERO) + .value("LSR_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_D_UNDEF) + .value("LSR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_D_ZERO) + .value("LSR_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_H_UNDEF) + .value("LSR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_H_ZERO) + .value("LSR_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_S_UNDEF) + .value("LSR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::LSR_ZPZZ_S_ZERO) + .value("MLA_ZPZZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::MLA_ZPZZZ_B_UNDEF) + .value("MLA_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::MLA_ZPZZZ_D_UNDEF) + .value("MLA_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::MLA_ZPZZZ_H_UNDEF) + .value("MLA_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::MLA_ZPZZZ_S_UNDEF) + .value("MLS_ZPZZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::MLS_ZPZZZ_B_UNDEF) + .value("MLS_ZPZZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::MLS_ZPZZZ_D_UNDEF) + .value("MLS_ZPZZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::MLS_ZPZZZ_H_UNDEF) + .value("MLS_ZPZZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::MLS_ZPZZZ_S_UNDEF) + .value("MOPSMemoryCopyPseudo", LIEF::assembly::aarch64::OPCODE::MOPSMemoryCopyPseudo) + .value("MOPSMemoryMovePseudo", LIEF::assembly::aarch64::OPCODE::MOPSMemoryMovePseudo) + .value("MOPSMemorySetPseudo", LIEF::assembly::aarch64::OPCODE::MOPSMemorySetPseudo) + .value("MOPSMemorySetTaggingPseudo", LIEF::assembly::aarch64::OPCODE::MOPSMemorySetTaggingPseudo) + .value("MOVAZ_2ZMI_H_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_B_PSEUDO) + .value("MOVAZ_2ZMI_H_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_D_PSEUDO) + .value("MOVAZ_2ZMI_H_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_H_PSEUDO) + .value("MOVAZ_2ZMI_H_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_S_PSEUDO) + .value("MOVAZ_2ZMI_V_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_B_PSEUDO) + .value("MOVAZ_2ZMI_V_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_D_PSEUDO) + .value("MOVAZ_2ZMI_V_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_H_PSEUDO) + .value("MOVAZ_2ZMI_V_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_S_PSEUDO) + .value("MOVAZ_4ZMI_H_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_B_PSEUDO) + .value("MOVAZ_4ZMI_H_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_D_PSEUDO) + .value("MOVAZ_4ZMI_H_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_H_PSEUDO) + .value("MOVAZ_4ZMI_H_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_S_PSEUDO) + .value("MOVAZ_4ZMI_V_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_B_PSEUDO) + .value("MOVAZ_4ZMI_V_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_D_PSEUDO) + .value("MOVAZ_4ZMI_V_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_H_PSEUDO) + .value("MOVAZ_4ZMI_V_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_S_PSEUDO) + .value("MOVAZ_VG2_2ZMXI_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_VG2_2ZMXI_PSEUDO) + .value("MOVAZ_VG4_4ZMXI_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_VG4_4ZMXI_PSEUDO) + .value("MOVAZ_ZMI_H_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_B_PSEUDO) + .value("MOVAZ_ZMI_H_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_D_PSEUDO) + .value("MOVAZ_ZMI_H_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_H_PSEUDO) + .value("MOVAZ_ZMI_H_Q_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_Q_PSEUDO) + .value("MOVAZ_ZMI_H_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_S_PSEUDO) + .value("MOVAZ_ZMI_V_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_B_PSEUDO) + .value("MOVAZ_ZMI_V_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_D_PSEUDO) + .value("MOVAZ_ZMI_V_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_H_PSEUDO) + .value("MOVAZ_ZMI_V_Q_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_Q_PSEUDO) + .value("MOVAZ_ZMI_V_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_S_PSEUDO) + .value("MOVA_MXI2Z_H_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_B_PSEUDO) + .value("MOVA_MXI2Z_H_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_D_PSEUDO) + .value("MOVA_MXI2Z_H_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_H_PSEUDO) + .value("MOVA_MXI2Z_H_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_S_PSEUDO) + .value("MOVA_MXI2Z_V_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_B_PSEUDO) + .value("MOVA_MXI2Z_V_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_D_PSEUDO) + .value("MOVA_MXI2Z_V_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_H_PSEUDO) + .value("MOVA_MXI2Z_V_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_S_PSEUDO) + .value("MOVA_MXI4Z_H_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_B_PSEUDO) + .value("MOVA_MXI4Z_H_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_D_PSEUDO) + .value("MOVA_MXI4Z_H_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_H_PSEUDO) + .value("MOVA_MXI4Z_H_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_S_PSEUDO) + .value("MOVA_MXI4Z_V_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_B_PSEUDO) + .value("MOVA_MXI4Z_V_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_D_PSEUDO) + .value("MOVA_MXI4Z_V_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_H_PSEUDO) + .value("MOVA_MXI4Z_V_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_S_PSEUDO) + .value("MOVA_VG2_MXI2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_VG2_MXI2Z_PSEUDO) + .value("MOVA_VG4_MXI4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVA_VG4_MXI4Z_PSEUDO) + .value("MOVMCSym", LIEF::assembly::aarch64::OPCODE::MOVMCSym) + .value("MOVT_TIZ_PSEUDO", LIEF::assembly::aarch64::OPCODE::MOVT_TIZ_PSEUDO) + .value("MOVaddr", LIEF::assembly::aarch64::OPCODE::MOVaddr) + .value("MOVaddrBA", LIEF::assembly::aarch64::OPCODE::MOVaddrBA) + .value("MOVaddrCP", LIEF::assembly::aarch64::OPCODE::MOVaddrCP) + .value("MOVaddrEXT", LIEF::assembly::aarch64::OPCODE::MOVaddrEXT) + .value("MOVaddrJT", LIEF::assembly::aarch64::OPCODE::MOVaddrJT) + .value("MOVaddrPAC", LIEF::assembly::aarch64::OPCODE::MOVaddrPAC) + .value("MOVaddrTLS", LIEF::assembly::aarch64::OPCODE::MOVaddrTLS) + .value("MOVbaseTLS", LIEF::assembly::aarch64::OPCODE::MOVbaseTLS) + .value("MOVi32imm", LIEF::assembly::aarch64::OPCODE::MOVi32imm) + .value("MOVi64imm", LIEF::assembly::aarch64::OPCODE::MOVi64imm) + .value("MRS_FPCR", LIEF::assembly::aarch64::OPCODE::MRS_FPCR) + .value("MRS_FPSR", LIEF::assembly::aarch64::OPCODE::MRS_FPSR) + .value("MSR_FPCR", LIEF::assembly::aarch64::OPCODE::MSR_FPCR) + .value("MSR_FPMR", LIEF::assembly::aarch64::OPCODE::MSR_FPMR) + .value("MSR_FPSR", LIEF::assembly::aarch64::OPCODE::MSR_FPSR) + .value("MSRpstatePseudo", LIEF::assembly::aarch64::OPCODE::MSRpstatePseudo) + .value("MUL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_B_UNDEF) + .value("MUL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_D_UNDEF) + .value("MUL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_H_UNDEF) + .value("MUL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_S_UNDEF) + .value("NEG_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_B_UNDEF) + .value("NEG_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_D_UNDEF) + .value("NEG_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_H_UNDEF) + .value("NEG_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_S_UNDEF) + .value("NOT_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_B_UNDEF) + .value("NOT_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_D_UNDEF) + .value("NOT_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_H_UNDEF) + .value("NOT_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_S_UNDEF) + .value("ORNWrr", LIEF::assembly::aarch64::OPCODE::ORNWrr) + .value("ORNXrr", LIEF::assembly::aarch64::OPCODE::ORNXrr) + .value("ORRWrr", LIEF::assembly::aarch64::OPCODE::ORRWrr) + .value("ORRXrr", LIEF::assembly::aarch64::OPCODE::ORRXrr) + .value("ORR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_B_ZERO) + .value("ORR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_D_ZERO) + .value("ORR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_H_ZERO) + .value("ORR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_S_ZERO) + .value("PAC", LIEF::assembly::aarch64::OPCODE::PAC) + .value("PAUTH_EPILOGUE", LIEF::assembly::aarch64::OPCODE::PAUTH_EPILOGUE) + .value("PAUTH_PROLOGUE", LIEF::assembly::aarch64::OPCODE::PAUTH_PROLOGUE) + .value("PROBED_STACKALLOC", LIEF::assembly::aarch64::OPCODE::PROBED_STACKALLOC) + .value("PROBED_STACKALLOC_DYN", LIEF::assembly::aarch64::OPCODE::PROBED_STACKALLOC_DYN) + .value("PROBED_STACKALLOC_VAR", LIEF::assembly::aarch64::OPCODE::PROBED_STACKALLOC_VAR) + .value("PTEST_PP_ANY", LIEF::assembly::aarch64::OPCODE::PTEST_PP_ANY) + .value("PTEST_PP_FIRST", LIEF::assembly::aarch64::OPCODE::PTEST_PP_FIRST) + .value("RET_ReallyLR", LIEF::assembly::aarch64::OPCODE::RET_ReallyLR) + .value("RequiresZASavePseudo", LIEF::assembly::aarch64::OPCODE::RequiresZASavePseudo) + .value("RequiresZT0SavePseudo", LIEF::assembly::aarch64::OPCODE::RequiresZT0SavePseudo) + .value("RestoreZAPseudo", LIEF::assembly::aarch64::OPCODE::RestoreZAPseudo) + .value("SABD_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SABD_ZPZZ_B_UNDEF) + .value("SABD_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SABD_ZPZZ_D_UNDEF) + .value("SABD_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SABD_ZPZZ_H_UNDEF) + .value("SABD_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SABD_ZPZZ_S_UNDEF) + .value("SCVTF_ZPmZ_DtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoD_UNDEF) + .value("SCVTF_ZPmZ_DtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoH_UNDEF) + .value("SCVTF_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoS_UNDEF) + .value("SCVTF_ZPmZ_HtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_HtoH_UNDEF) + .value("SCVTF_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoD_UNDEF) + .value("SCVTF_ZPmZ_StoH_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoH_UNDEF) + .value("SCVTF_ZPmZ_StoS_UNDEF", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoS_UNDEF) + .value("SDIV_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SDIV_ZPZZ_D_UNDEF) + .value("SDIV_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SDIV_ZPZZ_S_UNDEF) + .value("SDOT_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_BtoS_PSEUDO) + .value("SDOT_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_HtoD_PSEUDO) + .value("SDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_HtoS_PSEUDO) + .value("SDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_BToS_PSEUDO) + .value("SDOT_VG2_M2ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HToS_PSEUDO) + .value("SDOT_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HtoD_PSEUDO) + .value("SDOT_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_BtoS_PSEUDO) + .value("SDOT_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoD_PSEUDO) + .value("SDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoS_PSEUDO) + .value("SDOT_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_BtoS_PSEUDO) + .value("SDOT_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoD_PSEUDO) + .value("SDOT_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoS_PSEUDO) + .value("SDOT_VG4_M4ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_BToS_PSEUDO) + .value("SDOT_VG4_M4ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_HToS_PSEUDO) + .value("SDOT_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_HtoD_PSEUDO) + .value("SDOT_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_BtoS_PSEUDO) + .value("SDOT_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_HtoD_PSEUDO) + .value("SDOT_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_HtoS_PSEUDO) + .value("SEH_AddFP", LIEF::assembly::aarch64::OPCODE::SEH_AddFP) + .value("SEH_AllocZ", LIEF::assembly::aarch64::OPCODE::SEH_AllocZ) + .value("SEH_EpilogEnd", LIEF::assembly::aarch64::OPCODE::SEH_EpilogEnd) + .value("SEH_EpilogStart", LIEF::assembly::aarch64::OPCODE::SEH_EpilogStart) + .value("SEH_Nop", LIEF::assembly::aarch64::OPCODE::SEH_Nop) + .value("SEH_PACSignLR", LIEF::assembly::aarch64::OPCODE::SEH_PACSignLR) + .value("SEH_PrologEnd", LIEF::assembly::aarch64::OPCODE::SEH_PrologEnd) + .value("SEH_SaveAnyRegI", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegI) + .value("SEH_SaveAnyRegIP", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegIP) + .value("SEH_SaveAnyRegQP", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegQP) + .value("SEH_SaveAnyRegQPX", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegQPX) + .value("SEH_SaveFPLR", LIEF::assembly::aarch64::OPCODE::SEH_SaveFPLR) + .value("SEH_SaveFPLR_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFPLR_X); + opcodes.value("SEH_SaveFReg", LIEF::assembly::aarch64::OPCODE::SEH_SaveFReg) + .value("SEH_SaveFRegP", LIEF::assembly::aarch64::OPCODE::SEH_SaveFRegP) + .value("SEH_SaveFRegP_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFRegP_X) + .value("SEH_SaveFReg_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFReg_X) + .value("SEH_SavePReg", LIEF::assembly::aarch64::OPCODE::SEH_SavePReg) + .value("SEH_SaveReg", LIEF::assembly::aarch64::OPCODE::SEH_SaveReg) + .value("SEH_SaveRegP", LIEF::assembly::aarch64::OPCODE::SEH_SaveRegP) + .value("SEH_SaveRegP_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveRegP_X) + .value("SEH_SaveReg_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveReg_X) + .value("SEH_SaveZReg", LIEF::assembly::aarch64::OPCODE::SEH_SaveZReg) + .value("SEH_SetFP", LIEF::assembly::aarch64::OPCODE::SEH_SetFP) + .value("SEH_StackAlloc", LIEF::assembly::aarch64::OPCODE::SEH_StackAlloc) + .value("SHSUB_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_B_UNDEF) + .value("SHSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_D_UNDEF) + .value("SHSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_H_UNDEF) + .value("SHSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_S_UNDEF) + .value("SMAX_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_B_UNDEF) + .value("SMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_D_UNDEF) + .value("SMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_H_UNDEF) + .value("SMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_S_UNDEF) + .value("SMEStateAllocPseudo", LIEF::assembly::aarch64::OPCODE::SMEStateAllocPseudo) + .value("SMIN_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_B_UNDEF) + .value("SMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_D_UNDEF) + .value("SMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_H_UNDEF) + .value("SMIN_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_S_UNDEF) + .value("SMLALL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZI_BtoS_PSEUDO) + .value("SMLALL_MZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZI_HtoD_PSEUDO) + .value("SMLALL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZ_BtoS_PSEUDO) + .value("SMLALL_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZ_HtoD_PSEUDO) + .value("SMLALL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("SMLALL_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2Z2Z_HtoD_PSEUDO) + .value("SMLALL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZI_BtoS_PSEUDO) + .value("SMLALL_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZI_HtoD_PSEUDO) + .value("SMLALL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZ_BtoS_PSEUDO) + .value("SMLALL_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZ_HtoD_PSEUDO) + .value("SMLALL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("SMLALL_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4Z4Z_HtoD_PSEUDO) + .value("SMLALL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZI_BtoS_PSEUDO) + .value("SMLALL_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZI_HtoD_PSEUDO) + .value("SMLALL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZ_BtoS_PSEUDO) + .value("SMLALL_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZ_HtoD_PSEUDO) + .value("SMLAL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_MZZI_HtoS_PSEUDO) + .value("SMLAL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_MZZ_HtoS_PSEUDO) + .value("SMLAL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("SMLAL_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2ZZI_S_PSEUDO) + .value("SMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2ZZ_HtoS_PSEUDO) + .value("SMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("SMLAL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4ZZI_HtoS_PSEUDO) + .value("SMLAL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4ZZ_HtoS_PSEUDO) + .value("SMLSLL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZI_BtoS_PSEUDO) + .value("SMLSLL_MZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZI_HtoD_PSEUDO) + .value("SMLSLL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZ_BtoS_PSEUDO) + .value("SMLSLL_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZ_HtoD_PSEUDO) + .value("SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO) + .value("SMLSLL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZI_BtoS_PSEUDO) + .value("SMLSLL_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZI_HtoD_PSEUDO) + .value("SMLSLL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZ_BtoS_PSEUDO) + .value("SMLSLL_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZ_HtoD_PSEUDO) + .value("SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO) + .value("SMLSLL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZI_BtoS_PSEUDO) + .value("SMLSLL_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZI_HtoD_PSEUDO) + .value("SMLSLL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZ_BtoS_PSEUDO) + .value("SMLSLL_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZ_HtoD_PSEUDO) + .value("SMLSL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_MZZI_HtoS_PSEUDO) + .value("SMLSL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_MZZ_HtoS_PSEUDO) + .value("SMLSL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("SMLSL_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2ZZI_S_PSEUDO) + .value("SMLSL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2ZZ_HtoS_PSEUDO) + .value("SMLSL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("SMLSL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4ZZI_HtoS_PSEUDO) + .value("SMLSL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4ZZ_HtoS_PSEUDO) + .value("SMOP4A_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_BToS_PSEUDO) + .value("SMOP4A_M2Z2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_HToS_PSEUDO) + .value("SMOP4A_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_HtoD_PSEUDO) + .value("SMOP4A_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_BToS_PSEUDO) + .value("SMOP4A_M2ZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_HToS_PSEUDO) + .value("SMOP4A_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_HtoD_PSEUDO) + .value("SMOP4A_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_BToS_PSEUDO) + .value("SMOP4A_MZ2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_HToS_PSEUDO) + .value("SMOP4A_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_HtoD_PSEUDO) + .value("SMOP4A_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_BToS_PSEUDO) + .value("SMOP4A_MZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_HToS_PSEUDO) + .value("SMOP4A_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_HtoD_PSEUDO) + .value("SMOP4S_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_BToS_PSEUDO) + .value("SMOP4S_M2Z2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_HToS_PSEUDO) + .value("SMOP4S_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_HtoD_PSEUDO) + .value("SMOP4S_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_BToS_PSEUDO) + .value("SMOP4S_M2ZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_HToS_PSEUDO) + .value("SMOP4S_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_HtoD_PSEUDO) + .value("SMOP4S_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_BToS_PSEUDO) + .value("SMOP4S_MZ2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_HToS_PSEUDO) + .value("SMOP4S_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_HtoD_PSEUDO) + .value("SMOP4S_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_BToS_PSEUDO) + .value("SMOP4S_MZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_HToS_PSEUDO) + .value("SMOP4S_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_HtoD_PSEUDO) + .value("SMOPA_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_D_PSEUDO) + .value("SMOPA_MPPZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_HtoS_PSEUDO) + .value("SMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_S_PSEUDO) + .value("SMOPS_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_D_PSEUDO) + .value("SMOPS_MPPZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_HtoS_PSEUDO) + .value("SMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_S_PSEUDO) + .value("SMULH_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SMULH_ZPZZ_B_UNDEF) + .value("SMULH_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SMULH_ZPZZ_D_UNDEF) + .value("SMULH_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SMULH_ZPZZ_H_UNDEF) + .value("SMULH_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SMULH_ZPZZ_S_UNDEF) + .value("SPACE", LIEF::assembly::aarch64::OPCODE::SPACE) + .value("SQABS_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_B_UNDEF) + .value("SQABS_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_D_UNDEF) + .value("SQABS_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_H_UNDEF) + .value("SQABS_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_S_UNDEF) + .value("SQNEG_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_B_UNDEF) + .value("SQNEG_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_D_UNDEF) + .value("SQNEG_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_H_UNDEF) + .value("SQNEG_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_S_UNDEF) + .value("SQRSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPZZ_B_UNDEF) + .value("SQRSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPZZ_D_UNDEF) + .value("SQRSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPZZ_H_UNDEF) + .value("SQRSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPZZ_S_UNDEF) + .value("SQSHLU_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPZI_B_ZERO) + .value("SQSHLU_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPZI_D_ZERO) + .value("SQSHLU_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPZI_H_ZERO) + .value("SQSHLU_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPZI_S_ZERO) + .value("SQSHL_ZPZI_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_B_UNDEF) + .value("SQSHL_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_B_ZERO) + .value("SQSHL_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_D_UNDEF) + .value("SQSHL_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_D_ZERO) + .value("SQSHL_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_H_UNDEF) + .value("SQSHL_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_H_ZERO) + .value("SQSHL_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_S_UNDEF) + .value("SQSHL_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZI_S_ZERO) + .value("SQSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_B_UNDEF) + .value("SQSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_D_UNDEF) + .value("SQSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_H_UNDEF) + .value("SQSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_S_UNDEF) + .value("SRSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_B_UNDEF) + .value("SRSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_D_UNDEF) + .value("SRSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_H_UNDEF) + .value("SRSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_S_UNDEF) + .value("SRSHR_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_B_ZERO) + .value("SRSHR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_D_ZERO) + .value("SRSHR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_H_ZERO) + .value("SRSHR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_S_ZERO) + .value("STGloop", LIEF::assembly::aarch64::OPCODE::STGloop) + .value("STGloop_wback", LIEF::assembly::aarch64::OPCODE::STGloop_wback) + .value("STMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::STMOPA_M2ZZZI_BtoS_PSEUDO) + .value("STMOPA_M2ZZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::STMOPA_M2ZZZI_HtoS_PSEUDO) + .value("STR_PPXI", LIEF::assembly::aarch64::OPCODE::STR_PPXI) + .value("STR_TX_PSEUDO", LIEF::assembly::aarch64::OPCODE::STR_TX_PSEUDO) + .value("STR_ZZXI", LIEF::assembly::aarch64::OPCODE::STR_ZZXI) + .value("STR_ZZXI_STRIDED_CONTIGUOUS", LIEF::assembly::aarch64::OPCODE::STR_ZZXI_STRIDED_CONTIGUOUS) + .value("STR_ZZZXI", LIEF::assembly::aarch64::OPCODE::STR_ZZZXI) + .value("STR_ZZZZXI", LIEF::assembly::aarch64::OPCODE::STR_ZZZZXI) + .value("STR_ZZZZXI_STRIDED_CONTIGUOUS", LIEF::assembly::aarch64::OPCODE::STR_ZZZZXI_STRIDED_CONTIGUOUS) + .value("STZGloop", LIEF::assembly::aarch64::OPCODE::STZGloop) + .value("STZGloop_wback", LIEF::assembly::aarch64::OPCODE::STZGloop_wback) + .value("SUBR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_B_ZERO) + .value("SUBR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_D_ZERO) + .value("SUBR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_H_ZERO) + .value("SUBR_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_S_ZERO) + .value("SUBSWrr", LIEF::assembly::aarch64::OPCODE::SUBSWrr) + .value("SUBSXrr", LIEF::assembly::aarch64::OPCODE::SUBSXrr) + .value("SUBWrr", LIEF::assembly::aarch64::OPCODE::SUBWrr) + .value("SUBXrr", LIEF::assembly::aarch64::OPCODE::SUBXrr) + .value("SUB_VG2_M2Z2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z2Z_D_PSEUDO) + .value("SUB_VG2_M2Z2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z2Z_S_PSEUDO) + .value("SUB_VG2_M2ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2ZZ_D_PSEUDO) + .value("SUB_VG2_M2ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2ZZ_S_PSEUDO) + .value("SUB_VG2_M2Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z_D_PSEUDO) + .value("SUB_VG2_M2Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z_S_PSEUDO) + .value("SUB_VG4_M4Z4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z4Z_D_PSEUDO) + .value("SUB_VG4_M4Z4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z4Z_S_PSEUDO) + .value("SUB_VG4_M4ZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4ZZ_D_PSEUDO) + .value("SUB_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4ZZ_S_PSEUDO) + .value("SUB_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_D_PSEUDO) + .value("SUB_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_S_PSEUDO) + .value("SUB_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_B_ZERO) + .value("SUB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_D_ZERO) + .value("SUB_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_H_ZERO) + .value("SUB_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_S_ZERO) + .value("SUDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUDOT_VG2_M2ZZI_BToS_PSEUDO) + .value("SUDOT_VG2_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUDOT_VG2_M2ZZ_BToS_PSEUDO) + .value("SUDOT_VG4_M4ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUDOT_VG4_M4ZZI_BToS_PSEUDO) + .value("SUDOT_VG4_M4ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUDOT_VG4_M4ZZ_BToS_PSEUDO) + .value("SUMLALL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMLALL_MZZI_BtoS_PSEUDO) + .value("SUMLALL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG2_M2ZZI_BtoS_PSEUDO) + .value("SUMLALL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG2_M2ZZ_BtoS_PSEUDO) + .value("SUMLALL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG4_M4ZZI_BtoS_PSEUDO) + .value("SUMLALL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG4_M4ZZ_BtoS_PSEUDO) + .value("SUMOP4A_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2Z2Z_BToS_PSEUDO) + .value("SUMOP4A_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2Z2Z_HtoD_PSEUDO) + .value("SUMOP4A_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2ZZ_BToS_PSEUDO) + .value("SUMOP4A_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2ZZ_HtoD_PSEUDO) + .value("SUMOP4A_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZ2Z_BToS_PSEUDO) + .value("SUMOP4A_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZ2Z_HtoD_PSEUDO) + .value("SUMOP4A_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZZ_BToS_PSEUDO) + .value("SUMOP4A_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZZ_HtoD_PSEUDO) + .value("SUMOP4S_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2Z2Z_BToS_PSEUDO) + .value("SUMOP4S_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2Z2Z_HtoD_PSEUDO) + .value("SUMOP4S_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2ZZ_BToS_PSEUDO) + .value("SUMOP4S_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2ZZ_HtoD_PSEUDO) + .value("SUMOP4S_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZ2Z_BToS_PSEUDO) + .value("SUMOP4S_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZ2Z_HtoD_PSEUDO) + .value("SUMOP4S_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZZ_BToS_PSEUDO) + .value("SUMOP4S_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZZ_HtoD_PSEUDO) + .value("SUMOPA_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOPA_MPPZZ_D_PSEUDO) + .value("SUMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOPA_MPPZZ_S_PSEUDO) + .value("SUMOPS_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOPS_MPPZZ_D_PSEUDO) + .value("SUMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUMOPS_MPPZZ_S_PSEUDO) + .value("SUTMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUTMOPA_M2ZZZI_BtoS_PSEUDO) + .value("SUVDOT_VG4_M4ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUVDOT_VG4_M4ZZI_BToS_PSEUDO) + .value("SVDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SVDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("SVDOT_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SVDOT_VG4_M4ZZI_BtoS_PSEUDO) + .value("SVDOT_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SVDOT_VG4_M4ZZI_HtoD_PSEUDO) + .value("SXTB_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_D_UNDEF) + .value("SXTB_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_H_UNDEF) + .value("SXTB_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_S_UNDEF) + .value("SXTH_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTH_ZPmZ_D_UNDEF) + .value("SXTH_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTH_ZPmZ_S_UNDEF) + .value("SXTW_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SXTW_ZPmZ_D_UNDEF) + .value("SpeculationBarrierISBDSBEndBB", LIEF::assembly::aarch64::OPCODE::SpeculationBarrierISBDSBEndBB) + .value("SpeculationBarrierSBEndBB", LIEF::assembly::aarch64::OPCODE::SpeculationBarrierSBEndBB) + .value("SpeculationSafeValueW", LIEF::assembly::aarch64::OPCODE::SpeculationSafeValueW) + .value("SpeculationSafeValueX", LIEF::assembly::aarch64::OPCODE::SpeculationSafeValueX) + .value("StoreSwiftAsyncContext", LIEF::assembly::aarch64::OPCODE::StoreSwiftAsyncContext) + .value("TAGPstack", LIEF::assembly::aarch64::OPCODE::TAGPstack) + .value("TCRETURNdi", LIEF::assembly::aarch64::OPCODE::TCRETURNdi) + .value("TCRETURNri", LIEF::assembly::aarch64::OPCODE::TCRETURNri) + .value("TCRETURNriALL", LIEF::assembly::aarch64::OPCODE::TCRETURNriALL) + .value("TCRETURNrinotx16", LIEF::assembly::aarch64::OPCODE::TCRETURNrinotx16) + .value("TCRETURNrix16x17", LIEF::assembly::aarch64::OPCODE::TCRETURNrix16x17) + .value("TCRETURNrix17", LIEF::assembly::aarch64::OPCODE::TCRETURNrix17) + .value("TLSDESCCALL", LIEF::assembly::aarch64::OPCODE::TLSDESCCALL) + .value("TLSDESC_AUTH_CALLSEQ", LIEF::assembly::aarch64::OPCODE::TLSDESC_AUTH_CALLSEQ) + .value("TLSDESC_CALLSEQ", LIEF::assembly::aarch64::OPCODE::TLSDESC_CALLSEQ) + .value("UABD_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UABD_ZPZZ_B_UNDEF) + .value("UABD_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UABD_ZPZZ_D_UNDEF) + .value("UABD_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UABD_ZPZZ_H_UNDEF) + .value("UABD_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UABD_ZPZZ_S_UNDEF) + .value("UCVTF_ZPmZ_DtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoD_UNDEF) + .value("UCVTF_ZPmZ_DtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoH_UNDEF) + .value("UCVTF_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoS_UNDEF) + .value("UCVTF_ZPmZ_HtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_HtoH_UNDEF) + .value("UCVTF_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoD_UNDEF) + .value("UCVTF_ZPmZ_StoH_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoH_UNDEF) + .value("UCVTF_ZPmZ_StoS_UNDEF", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoS_UNDEF) + .value("UDIV_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UDIV_ZPZZ_D_UNDEF) + .value("UDIV_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UDIV_ZPZZ_S_UNDEF) + .value("UDOT_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_BtoS_PSEUDO) + .value("UDOT_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoD_PSEUDO) + .value("UDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoS_PSEUDO) + .value("UDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_BToS_PSEUDO) + .value("UDOT_VG2_M2ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HToS_PSEUDO) + .value("UDOT_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HtoD_PSEUDO) + .value("UDOT_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_BtoS_PSEUDO) + .value("UDOT_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_HtoD_PSEUDO) + .value("UDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_HtoS_PSEUDO) + .value("UDOT_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_BtoS_PSEUDO) + .value("UDOT_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_HtoD_PSEUDO) + .value("UDOT_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_HtoS_PSEUDO) + .value("UDOT_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_BtoS_PSEUDO) + .value("UDOT_VG4_M4ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_HToS_PSEUDO) + .value("UDOT_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_HtoD_PSEUDO) + .value("UDOT_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_BtoS_PSEUDO) + .value("UDOT_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_HtoD_PSEUDO) + .value("UDOT_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_HtoS_PSEUDO) + .value("UHSUB_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_B_UNDEF) + .value("UHSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_D_UNDEF) + .value("UHSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_H_UNDEF) + .value("UHSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_S_UNDEF) + .value("UMAX_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_B_UNDEF) + .value("UMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_D_UNDEF) + .value("UMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_H_UNDEF) + .value("UMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_S_UNDEF) + .value("UMIN_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_B_UNDEF) + .value("UMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_D_UNDEF) + .value("UMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_H_UNDEF) + .value("UMIN_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_S_UNDEF) + .value("UMLALL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZI_BtoS_PSEUDO) + .value("UMLALL_MZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZI_HtoD_PSEUDO) + .value("UMLALL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZ_BtoS_PSEUDO) + .value("UMLALL_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZ_HtoD_PSEUDO) + .value("UMLALL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("UMLALL_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2Z2Z_HtoD_PSEUDO) + .value("UMLALL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZI_BtoS_PSEUDO) + .value("UMLALL_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZI_HtoD_PSEUDO) + .value("UMLALL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZ_BtoS_PSEUDO) + .value("UMLALL_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZ_HtoD_PSEUDO) + .value("UMLALL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("UMLALL_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4Z4Z_HtoD_PSEUDO) + .value("UMLALL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZI_BtoS_PSEUDO) + .value("UMLALL_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZI_HtoD_PSEUDO) + .value("UMLALL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZ_BtoS_PSEUDO) + .value("UMLALL_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZ_HtoD_PSEUDO) + .value("UMLAL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_MZZI_HtoS_PSEUDO) + .value("UMLAL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_MZZ_HtoS_PSEUDO) + .value("UMLAL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("UMLAL_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZI_S_PSEUDO) + .value("UMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZ_HtoS_PSEUDO); + opcodes.value("UMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("UMLAL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZI_HtoS_PSEUDO) + .value("UMLAL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZ_HtoS_PSEUDO) + .value("UMLSLL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZI_BtoS_PSEUDO) + .value("UMLSLL_MZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZI_HtoD_PSEUDO) + .value("UMLSLL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZ_BtoS_PSEUDO) + .value("UMLSLL_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZ_HtoD_PSEUDO) + .value("UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO) + .value("UMLSLL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZI_BtoS_PSEUDO) + .value("UMLSLL_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZI_HtoD_PSEUDO) + .value("UMLSLL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZ_BtoS_PSEUDO) + .value("UMLSLL_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZ_HtoD_PSEUDO) + .value("UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO) + .value("UMLSLL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_BtoS_PSEUDO) + .value("UMLSLL_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_HtoD_PSEUDO) + .value("UMLSLL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_BtoS_PSEUDO) + .value("UMLSLL_VG4_M4ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_HtoD_PSEUDO) + .value("UMLSL_MZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_MZZI_HtoS_PSEUDO) + .value("UMLSL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_MZZ_HtoS_PSEUDO) + .value("UMLSL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2Z2Z_HtoS_PSEUDO) + .value("UMLSL_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2ZZI_S_PSEUDO) + .value("UMLSL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2ZZ_HtoS_PSEUDO) + .value("UMLSL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4Z4Z_HtoS_PSEUDO) + .value("UMLSL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4ZZI_HtoS_PSEUDO) + .value("UMLSL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4ZZ_HtoS_PSEUDO) + .value("UMOP4A_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_BToS_PSEUDO) + .value("UMOP4A_M2Z2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_HToS_PSEUDO) + .value("UMOP4A_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_HtoD_PSEUDO) + .value("UMOP4A_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_BToS_PSEUDO) + .value("UMOP4A_M2ZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_HToS_PSEUDO) + .value("UMOP4A_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_HtoD_PSEUDO) + .value("UMOP4A_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_BToS_PSEUDO) + .value("UMOP4A_MZ2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_HToS_PSEUDO) + .value("UMOP4A_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_HtoD_PSEUDO) + .value("UMOP4A_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_BToS_PSEUDO) + .value("UMOP4A_MZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_HToS_PSEUDO) + .value("UMOP4A_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_HtoD_PSEUDO) + .value("UMOP4S_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_BToS_PSEUDO) + .value("UMOP4S_M2Z2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_HToS_PSEUDO) + .value("UMOP4S_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_HtoD_PSEUDO) + .value("UMOP4S_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_BToS_PSEUDO) + .value("UMOP4S_M2ZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_HToS_PSEUDO) + .value("UMOP4S_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_HtoD_PSEUDO) + .value("UMOP4S_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_BToS_PSEUDO) + .value("UMOP4S_MZ2Z_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_HToS_PSEUDO) + .value("UMOP4S_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_HtoD_PSEUDO) + .value("UMOP4S_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_BToS_PSEUDO) + .value("UMOP4S_MZZ_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_HToS_PSEUDO) + .value("UMOP4S_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_HtoD_PSEUDO) + .value("UMOPA_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_D_PSEUDO) + .value("UMOPA_MPPZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_HtoS_PSEUDO) + .value("UMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_S_PSEUDO) + .value("UMOPS_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_D_PSEUDO) + .value("UMOPS_MPPZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_HtoS_PSEUDO) + .value("UMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_S_PSEUDO) + .value("UMULH_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_B_UNDEF) + .value("UMULH_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_D_UNDEF) + .value("UMULH_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_H_UNDEF) + .value("UMULH_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_S_UNDEF) + .value("UQRSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_B_UNDEF) + .value("UQRSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_D_UNDEF) + .value("UQRSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_H_UNDEF) + .value("UQRSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_S_UNDEF) + .value("UQSHL_ZPZI_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_B_UNDEF) + .value("UQSHL_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_B_ZERO) + .value("UQSHL_ZPZI_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_D_UNDEF) + .value("UQSHL_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_D_ZERO) + .value("UQSHL_ZPZI_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_H_UNDEF) + .value("UQSHL_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_H_ZERO) + .value("UQSHL_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_S_UNDEF) + .value("UQSHL_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZI_S_ZERO) + .value("UQSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_B_UNDEF) + .value("UQSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_D_UNDEF) + .value("UQSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_H_UNDEF) + .value("UQSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_S_UNDEF) + .value("URECPE_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::URECPE_ZPmZ_S_UNDEF) + .value("URSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_B_UNDEF) + .value("URSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_D_UNDEF) + .value("URSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_H_UNDEF) + .value("URSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_S_UNDEF) + .value("URSHR_ZPZI_B_ZERO", LIEF::assembly::aarch64::OPCODE::URSHR_ZPZI_B_ZERO) + .value("URSHR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::URSHR_ZPZI_D_ZERO) + .value("URSHR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::URSHR_ZPZI_H_ZERO) + .value("URSHR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::URSHR_ZPZI_S_ZERO) + .value("URSQRTE_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::URSQRTE_ZPmZ_S_UNDEF) + .value("USDOT_VG2_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2Z2Z_BToS_PSEUDO) + .value("USDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2ZZI_BToS_PSEUDO) + .value("USDOT_VG2_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2ZZ_BToS_PSEUDO) + .value("USDOT_VG4_M4Z4Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4Z4Z_BToS_PSEUDO) + .value("USDOT_VG4_M4ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4ZZI_BToS_PSEUDO) + .value("USDOT_VG4_M4ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4ZZ_BToS_PSEUDO) + .value("USMLALL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_MZZI_BtoS_PSEUDO) + .value("USMLALL_MZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_MZZ_BtoS_PSEUDO) + .value("USMLALL_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2Z2Z_BtoS_PSEUDO) + .value("USMLALL_VG2_M2ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2ZZI_BtoS_PSEUDO) + .value("USMLALL_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2ZZ_BtoS_PSEUDO) + .value("USMLALL_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4Z4Z_BtoS_PSEUDO) + .value("USMLALL_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4ZZI_BtoS_PSEUDO) + .value("USMLALL_VG4_M4ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4ZZ_BtoS_PSEUDO) + .value("USMOP4A_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2Z2Z_BToS_PSEUDO) + .value("USMOP4A_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2Z2Z_HtoD_PSEUDO) + .value("USMOP4A_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2ZZ_BToS_PSEUDO) + .value("USMOP4A_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2ZZ_HtoD_PSEUDO) + .value("USMOP4A_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZ2Z_BToS_PSEUDO) + .value("USMOP4A_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZ2Z_HtoD_PSEUDO) + .value("USMOP4A_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZZ_BToS_PSEUDO) + .value("USMOP4A_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZZ_HtoD_PSEUDO) + .value("USMOP4S_M2Z2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2Z2Z_BToS_PSEUDO) + .value("USMOP4S_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2Z2Z_HtoD_PSEUDO) + .value("USMOP4S_M2ZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2ZZ_BToS_PSEUDO) + .value("USMOP4S_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2ZZ_HtoD_PSEUDO) + .value("USMOP4S_MZ2Z_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZ2Z_BToS_PSEUDO) + .value("USMOP4S_MZ2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZ2Z_HtoD_PSEUDO) + .value("USMOP4S_MZZ_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZZ_BToS_PSEUDO) + .value("USMOP4S_MZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZZ_HtoD_PSEUDO) + .value("USMOPA_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOPA_MPPZZ_D_PSEUDO) + .value("USMOPA_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOPA_MPPZZ_S_PSEUDO) + .value("USMOPS_MPPZZ_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOPS_MPPZZ_D_PSEUDO) + .value("USMOPS_MPPZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::USMOPS_MPPZZ_S_PSEUDO) + .value("USTMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USTMOPA_M2ZZZI_BtoS_PSEUDO) + .value("USVDOT_VG4_M4ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::USVDOT_VG4_M4ZZI_BToS_PSEUDO) + .value("UTMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UTMOPA_M2ZZZI_BtoS_PSEUDO) + .value("UTMOPA_M2ZZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UTMOPA_M2ZZZI_HtoS_PSEUDO) + .value("UVDOT_VG2_M2ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UVDOT_VG2_M2ZZI_HtoS_PSEUDO) + .value("UVDOT_VG4_M4ZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UVDOT_VG4_M4ZZI_BtoS_PSEUDO) + .value("UVDOT_VG4_M4ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UVDOT_VG4_M4ZZI_HtoD_PSEUDO) + .value("UXTB_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_D_UNDEF) + .value("UXTB_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_H_UNDEF) + .value("UXTB_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_S_UNDEF) + .value("UXTH_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTH_ZPmZ_D_UNDEF) + .value("UXTH_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTH_ZPmZ_S_UNDEF) + .value("UXTW_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UXTW_ZPmZ_D_UNDEF) + .value("ZERO_MXI_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_2Z_PSEUDO) + .value("ZERO_MXI_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_4Z_PSEUDO) + .value("ZERO_MXI_VG2_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_2Z_PSEUDO) + .value("ZERO_MXI_VG2_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_4Z_PSEUDO) + .value("ZERO_MXI_VG2_Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_Z_PSEUDO) + .value("ZERO_MXI_VG4_2Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_2Z_PSEUDO) + .value("ZERO_MXI_VG4_4Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_4Z_PSEUDO) + .value("ZERO_MXI_VG4_Z_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_Z_PSEUDO) + .value("ZERO_M_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_M_PSEUDO) + .value("ZERO_T_PSEUDO", LIEF::assembly::aarch64::OPCODE::ZERO_T_PSEUDO) + .value("ABSWr", LIEF::assembly::aarch64::OPCODE::ABSWr) + .value("ABSXr", LIEF::assembly::aarch64::OPCODE::ABSXr) + .value("ABS_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_B) + .value("ABS_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_D) + .value("ABS_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_H) + .value("ABS_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ABS_ZPmZ_S) + .value("ABS_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::ABS_ZPzZ_B) + .value("ABS_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::ABS_ZPzZ_D) + .value("ABS_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::ABS_ZPzZ_H) + .value("ABS_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::ABS_ZPzZ_S) + .value("ABSv16i8", LIEF::assembly::aarch64::OPCODE::ABSv16i8) + .value("ABSv1i64", LIEF::assembly::aarch64::OPCODE::ABSv1i64) + .value("ABSv2i32", LIEF::assembly::aarch64::OPCODE::ABSv2i32) + .value("ABSv2i64", LIEF::assembly::aarch64::OPCODE::ABSv2i64) + .value("ABSv4i16", LIEF::assembly::aarch64::OPCODE::ABSv4i16) + .value("ABSv4i32", LIEF::assembly::aarch64::OPCODE::ABSv4i32) + .value("ABSv8i16", LIEF::assembly::aarch64::OPCODE::ABSv8i16) + .value("ABSv8i8", LIEF::assembly::aarch64::OPCODE::ABSv8i8) + .value("ADCLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ADCLB_ZZZ_D) + .value("ADCLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADCLB_ZZZ_S) + .value("ADCLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ADCLT_ZZZ_D) + .value("ADCLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADCLT_ZZZ_S) + .value("ADCSWr", LIEF::assembly::aarch64::OPCODE::ADCSWr) + .value("ADCSXr", LIEF::assembly::aarch64::OPCODE::ADCSXr) + .value("ADCWr", LIEF::assembly::aarch64::OPCODE::ADCWr) + .value("ADCXr", LIEF::assembly::aarch64::OPCODE::ADCXr) + .value("ADDG", LIEF::assembly::aarch64::OPCODE::ADDG) + .value("ADDHA_MPPZ_D", LIEF::assembly::aarch64::OPCODE::ADDHA_MPPZ_D) + .value("ADDHA_MPPZ_S", LIEF::assembly::aarch64::OPCODE::ADDHA_MPPZ_S) + .value("ADDHNB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ADDHNB_ZZZ_B) + .value("ADDHNB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ADDHNB_ZZZ_H) + .value("ADDHNB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADDHNB_ZZZ_S) + .value("ADDHNT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ADDHNT_ZZZ_B) + .value("ADDHNT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ADDHNT_ZZZ_H) + .value("ADDHNT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADDHNT_ZZZ_S) + .value("ADDHNv2i64_v2i32", LIEF::assembly::aarch64::OPCODE::ADDHNv2i64_v2i32) + .value("ADDHNv2i64_v4i32", LIEF::assembly::aarch64::OPCODE::ADDHNv2i64_v4i32) + .value("ADDHNv4i32_v4i16", LIEF::assembly::aarch64::OPCODE::ADDHNv4i32_v4i16) + .value("ADDHNv4i32_v8i16", LIEF::assembly::aarch64::OPCODE::ADDHNv4i32_v8i16) + .value("ADDHNv8i16_v16i8", LIEF::assembly::aarch64::OPCODE::ADDHNv8i16_v16i8) + .value("ADDHNv8i16_v8i8", LIEF::assembly::aarch64::OPCODE::ADDHNv8i16_v8i8) + .value("ADDPL_XXI", LIEF::assembly::aarch64::OPCODE::ADDPL_XXI) + .value("ADDPT_shift", LIEF::assembly::aarch64::OPCODE::ADDPT_shift) + .value("ADDP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ADDP_ZPmZ_B) + .value("ADDP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ADDP_ZPmZ_D) + .value("ADDP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ADDP_ZPmZ_H) + .value("ADDP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ADDP_ZPmZ_S) + .value("ADDPv16i8", LIEF::assembly::aarch64::OPCODE::ADDPv16i8) + .value("ADDPv2i32", LIEF::assembly::aarch64::OPCODE::ADDPv2i32) + .value("ADDPv2i64", LIEF::assembly::aarch64::OPCODE::ADDPv2i64) + .value("ADDPv2i64p", LIEF::assembly::aarch64::OPCODE::ADDPv2i64p) + .value("ADDPv4i16", LIEF::assembly::aarch64::OPCODE::ADDPv4i16) + .value("ADDPv4i32", LIEF::assembly::aarch64::OPCODE::ADDPv4i32) + .value("ADDPv8i16", LIEF::assembly::aarch64::OPCODE::ADDPv8i16) + .value("ADDPv8i8", LIEF::assembly::aarch64::OPCODE::ADDPv8i8) + .value("ADDQP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ADDQP_ZZZ_B) + .value("ADDQP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ADDQP_ZZZ_D) + .value("ADDQP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ADDQP_ZZZ_H) + .value("ADDQP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADDQP_ZZZ_S) + .value("ADDQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::ADDQV_VPZ_B) + .value("ADDQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::ADDQV_VPZ_D) + .value("ADDQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::ADDQV_VPZ_H) + .value("ADDQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::ADDQV_VPZ_S) + .value("ADDSPL_XXI", LIEF::assembly::aarch64::OPCODE::ADDSPL_XXI) + .value("ADDSUBP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ADDSUBP_ZZZ_B) + .value("ADDSUBP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ADDSUBP_ZZZ_D) + .value("ADDSUBP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ADDSUBP_ZZZ_H) + .value("ADDSUBP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADDSUBP_ZZZ_S) + .value("ADDSVL_XXI", LIEF::assembly::aarch64::OPCODE::ADDSVL_XXI) + .value("ADDSWri", LIEF::assembly::aarch64::OPCODE::ADDSWri) + .value("ADDSWrs", LIEF::assembly::aarch64::OPCODE::ADDSWrs) + .value("ADDSWrx", LIEF::assembly::aarch64::OPCODE::ADDSWrx) + .value("ADDSXri", LIEF::assembly::aarch64::OPCODE::ADDSXri) + .value("ADDSXrs", LIEF::assembly::aarch64::OPCODE::ADDSXrs) + .value("ADDSXrx", LIEF::assembly::aarch64::OPCODE::ADDSXrx) + .value("ADDSXrx64", LIEF::assembly::aarch64::OPCODE::ADDSXrx64) + .value("ADDVA_MPPZ_D", LIEF::assembly::aarch64::OPCODE::ADDVA_MPPZ_D) + .value("ADDVA_MPPZ_S", LIEF::assembly::aarch64::OPCODE::ADDVA_MPPZ_S) + .value("ADDVL_XXI", LIEF::assembly::aarch64::OPCODE::ADDVL_XXI) + .value("ADDVv16i8v", LIEF::assembly::aarch64::OPCODE::ADDVv16i8v) + .value("ADDVv4i16v", LIEF::assembly::aarch64::OPCODE::ADDVv4i16v) + .value("ADDVv4i32v", LIEF::assembly::aarch64::OPCODE::ADDVv4i32v) + .value("ADDVv8i16v", LIEF::assembly::aarch64::OPCODE::ADDVv8i16v) + .value("ADDVv8i8v", LIEF::assembly::aarch64::OPCODE::ADDVv8i8v) + .value("ADDWri", LIEF::assembly::aarch64::OPCODE::ADDWri) + .value("ADDWrs", LIEF::assembly::aarch64::OPCODE::ADDWrs) + .value("ADDWrx", LIEF::assembly::aarch64::OPCODE::ADDWrx) + .value("ADDXri", LIEF::assembly::aarch64::OPCODE::ADDXri) + .value("ADDXrs", LIEF::assembly::aarch64::OPCODE::ADDXrs) + .value("ADDXrx", LIEF::assembly::aarch64::OPCODE::ADDXrx) + .value("ADDXrx64", LIEF::assembly::aarch64::OPCODE::ADDXrx64) + .value("ADD_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_B) + .value("ADD_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_D) + .value("ADD_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_H) + .value("ADD_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_S) + .value("ADD_VG2_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z2Z_D) + .value("ADD_VG2_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z2Z_S) + .value("ADD_VG2_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2ZZ_D) + .value("ADD_VG2_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2ZZ_S) + .value("ADD_VG2_M2Z_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z_D) + .value("ADD_VG2_M2Z_S", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z_S) + .value("ADD_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::ADD_VG4_4ZZ_B) + .value("ADD_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG4_4ZZ_D) + .value("ADD_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::ADD_VG4_4ZZ_H) + .value("ADD_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_VG4_4ZZ_S) + .value("ADD_VG4_M4Z4Z_D", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z4Z_D) + .value("ADD_VG4_M4Z4Z_S", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z4Z_S) + .value("ADD_VG4_M4ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4ZZ_D) + .value("ADD_VG4_M4ZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4ZZ_S) + .value("ADD_VG4_M4Z_D", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_D) + .value("ADD_VG4_M4Z_S", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_S) + .value("ADD_ZI_B", LIEF::assembly::aarch64::OPCODE::ADD_ZI_B) + .value("ADD_ZI_D", LIEF::assembly::aarch64::OPCODE::ADD_ZI_D) + .value("ADD_ZI_H", LIEF::assembly::aarch64::OPCODE::ADD_ZI_H) + .value("ADD_ZI_S", LIEF::assembly::aarch64::OPCODE::ADD_ZI_S) + .value("ADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ADD_ZPmZ_B) + .value("ADD_ZPmZ_CPA", LIEF::assembly::aarch64::OPCODE::ADD_ZPmZ_CPA) + .value("ADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ADD_ZPmZ_D) + .value("ADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ADD_ZPmZ_H) + .value("ADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ADD_ZPmZ_S) + .value("ADD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ADD_ZZZ_B) + .value("ADD_ZZZ_CPA", LIEF::assembly::aarch64::OPCODE::ADD_ZZZ_CPA) + .value("ADD_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_ZZZ_D) + .value("ADD_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ADD_ZZZ_H) + .value("ADD_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_ZZZ_S) + .value("ADDv16i8", LIEF::assembly::aarch64::OPCODE::ADDv16i8) + .value("ADDv1i64", LIEF::assembly::aarch64::OPCODE::ADDv1i64) + .value("ADDv2i32", LIEF::assembly::aarch64::OPCODE::ADDv2i32) + .value("ADDv2i64", LIEF::assembly::aarch64::OPCODE::ADDv2i64) + .value("ADDv4i16", LIEF::assembly::aarch64::OPCODE::ADDv4i16) + .value("ADDv4i32", LIEF::assembly::aarch64::OPCODE::ADDv4i32) + .value("ADDv8i16", LIEF::assembly::aarch64::OPCODE::ADDv8i16) + .value("ADDv8i8", LIEF::assembly::aarch64::OPCODE::ADDv8i8) + .value("ADR", LIEF::assembly::aarch64::OPCODE::ADR) + .value("ADRP", LIEF::assembly::aarch64::OPCODE::ADRP) + .value("ADR_LSL_ZZZ_D_0", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_D_0) + .value("ADR_LSL_ZZZ_D_1", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_D_1) + .value("ADR_LSL_ZZZ_D_2", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_D_2) + .value("ADR_LSL_ZZZ_D_3", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_D_3) + .value("ADR_LSL_ZZZ_S_0", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_S_0) + .value("ADR_LSL_ZZZ_S_1", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_S_1) + .value("ADR_LSL_ZZZ_S_2", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_S_2) + .value("ADR_LSL_ZZZ_S_3", LIEF::assembly::aarch64::OPCODE::ADR_LSL_ZZZ_S_3) + .value("ADR_SXTW_ZZZ_D_0", LIEF::assembly::aarch64::OPCODE::ADR_SXTW_ZZZ_D_0) + .value("ADR_SXTW_ZZZ_D_1", LIEF::assembly::aarch64::OPCODE::ADR_SXTW_ZZZ_D_1) + .value("ADR_SXTW_ZZZ_D_2", LIEF::assembly::aarch64::OPCODE::ADR_SXTW_ZZZ_D_2) + .value("ADR_SXTW_ZZZ_D_3", LIEF::assembly::aarch64::OPCODE::ADR_SXTW_ZZZ_D_3) + .value("ADR_UXTW_ZZZ_D_0", LIEF::assembly::aarch64::OPCODE::ADR_UXTW_ZZZ_D_0) + .value("ADR_UXTW_ZZZ_D_1", LIEF::assembly::aarch64::OPCODE::ADR_UXTW_ZZZ_D_1) + .value("ADR_UXTW_ZZZ_D_2", LIEF::assembly::aarch64::OPCODE::ADR_UXTW_ZZZ_D_2) + .value("ADR_UXTW_ZZZ_D_3", LIEF::assembly::aarch64::OPCODE::ADR_UXTW_ZZZ_D_3) + .value("AESDIMC_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESDIMC_2ZZI_B) + .value("AESDIMC_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESDIMC_4ZZI_B) + .value("AESD_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESD_2ZZI_B) + .value("AESD_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESD_4ZZI_B) + .value("AESD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::AESD_ZZZ_B); + opcodes.value("AESDrr", LIEF::assembly::aarch64::OPCODE::AESDrr) + .value("AESEMC_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESEMC_2ZZI_B) + .value("AESEMC_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESEMC_4ZZI_B) + .value("AESE_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESE_2ZZI_B) + .value("AESE_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESE_4ZZI_B) + .value("AESE_ZZZ_B", LIEF::assembly::aarch64::OPCODE::AESE_ZZZ_B) + .value("AESErr", LIEF::assembly::aarch64::OPCODE::AESErr) + .value("AESIMC_ZZ_B", LIEF::assembly::aarch64::OPCODE::AESIMC_ZZ_B) + .value("AESIMCrr", LIEF::assembly::aarch64::OPCODE::AESIMCrr) + .value("AESMC_ZZ_B", LIEF::assembly::aarch64::OPCODE::AESMC_ZZ_B) + .value("AESMCrr", LIEF::assembly::aarch64::OPCODE::AESMCrr) + .value("ANDQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::ANDQV_VPZ_B) + .value("ANDQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::ANDQV_VPZ_D) + .value("ANDQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::ANDQV_VPZ_H) + .value("ANDQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::ANDQV_VPZ_S) + .value("ANDSWri", LIEF::assembly::aarch64::OPCODE::ANDSWri) + .value("ANDSWrs", LIEF::assembly::aarch64::OPCODE::ANDSWrs) + .value("ANDSXri", LIEF::assembly::aarch64::OPCODE::ANDSXri) + .value("ANDSXrs", LIEF::assembly::aarch64::OPCODE::ANDSXrs) + .value("ANDS_PPzPP", LIEF::assembly::aarch64::OPCODE::ANDS_PPzPP) + .value("ANDV_VPZ_B", LIEF::assembly::aarch64::OPCODE::ANDV_VPZ_B) + .value("ANDV_VPZ_D", LIEF::assembly::aarch64::OPCODE::ANDV_VPZ_D) + .value("ANDV_VPZ_H", LIEF::assembly::aarch64::OPCODE::ANDV_VPZ_H) + .value("ANDV_VPZ_S", LIEF::assembly::aarch64::OPCODE::ANDV_VPZ_S) + .value("ANDWri", LIEF::assembly::aarch64::OPCODE::ANDWri) + .value("ANDWrs", LIEF::assembly::aarch64::OPCODE::ANDWrs) + .value("ANDXri", LIEF::assembly::aarch64::OPCODE::ANDXri) + .value("ANDXrs", LIEF::assembly::aarch64::OPCODE::ANDXrs) + .value("AND_PPzPP", LIEF::assembly::aarch64::OPCODE::AND_PPzPP) + .value("AND_ZI", LIEF::assembly::aarch64::OPCODE::AND_ZI) + .value("AND_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::AND_ZPmZ_B) + .value("AND_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::AND_ZPmZ_D) + .value("AND_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::AND_ZPmZ_H) + .value("AND_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::AND_ZPmZ_S) + .value("AND_ZZZ", LIEF::assembly::aarch64::OPCODE::AND_ZZZ) + .value("ANDv16i8", LIEF::assembly::aarch64::OPCODE::ANDv16i8) + .value("ANDv8i8", LIEF::assembly::aarch64::OPCODE::ANDv8i8) + .value("APAS", LIEF::assembly::aarch64::OPCODE::APAS) + .value("ASRD_ZPmI_B", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_B) + .value("ASRD_ZPmI_D", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_D) + .value("ASRD_ZPmI_H", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_H) + .value("ASRD_ZPmI_S", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_S) + .value("ASRR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ASRR_ZPmZ_B) + .value("ASRR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ASRR_ZPmZ_D) + .value("ASRR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ASRR_ZPmZ_H) + .value("ASRR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ASRR_ZPmZ_S) + .value("ASRVWr", LIEF::assembly::aarch64::OPCODE::ASRVWr) + .value("ASRVXr", LIEF::assembly::aarch64::OPCODE::ASRVXr) + .value("ASR_WIDE_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZPmZ_B) + .value("ASR_WIDE_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZPmZ_H) + .value("ASR_WIDE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZPmZ_S) + .value("ASR_WIDE_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZZZ_B) + .value("ASR_WIDE_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZZZ_H) + .value("ASR_WIDE_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ASR_WIDE_ZZZ_S) + .value("ASR_ZPmI_B", LIEF::assembly::aarch64::OPCODE::ASR_ZPmI_B) + .value("ASR_ZPmI_D", LIEF::assembly::aarch64::OPCODE::ASR_ZPmI_D) + .value("ASR_ZPmI_H", LIEF::assembly::aarch64::OPCODE::ASR_ZPmI_H) + .value("ASR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::ASR_ZPmI_S) + .value("ASR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ASR_ZPmZ_B) + .value("ASR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ASR_ZPmZ_D) + .value("ASR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ASR_ZPmZ_H) + .value("ASR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ASR_ZPmZ_S) + .value("ASR_ZZI_B", LIEF::assembly::aarch64::OPCODE::ASR_ZZI_B) + .value("ASR_ZZI_D", LIEF::assembly::aarch64::OPCODE::ASR_ZZI_D) + .value("ASR_ZZI_H", LIEF::assembly::aarch64::OPCODE::ASR_ZZI_H) + .value("ASR_ZZI_S", LIEF::assembly::aarch64::OPCODE::ASR_ZZI_S) + .value("AUTDA", LIEF::assembly::aarch64::OPCODE::AUTDA) + .value("AUTDB", LIEF::assembly::aarch64::OPCODE::AUTDB) + .value("AUTDZA", LIEF::assembly::aarch64::OPCODE::AUTDZA) + .value("AUTDZB", LIEF::assembly::aarch64::OPCODE::AUTDZB) + .value("AUTIA", LIEF::assembly::aarch64::OPCODE::AUTIA) + .value("AUTIA1716", LIEF::assembly::aarch64::OPCODE::AUTIA1716) + .value("AUTIA171615", LIEF::assembly::aarch64::OPCODE::AUTIA171615) + .value("AUTIASP", LIEF::assembly::aarch64::OPCODE::AUTIASP) + .value("AUTIASPPCi", LIEF::assembly::aarch64::OPCODE::AUTIASPPCi) + .value("AUTIASPPCr", LIEF::assembly::aarch64::OPCODE::AUTIASPPCr) + .value("AUTIAZ", LIEF::assembly::aarch64::OPCODE::AUTIAZ) + .value("AUTIB", LIEF::assembly::aarch64::OPCODE::AUTIB) + .value("AUTIB1716", LIEF::assembly::aarch64::OPCODE::AUTIB1716) + .value("AUTIB171615", LIEF::assembly::aarch64::OPCODE::AUTIB171615) + .value("AUTIBSP", LIEF::assembly::aarch64::OPCODE::AUTIBSP) + .value("AUTIBSPPCi", LIEF::assembly::aarch64::OPCODE::AUTIBSPPCi) + .value("AUTIBSPPCr", LIEF::assembly::aarch64::OPCODE::AUTIBSPPCr) + .value("AUTIBZ", LIEF::assembly::aarch64::OPCODE::AUTIBZ) + .value("AUTIZA", LIEF::assembly::aarch64::OPCODE::AUTIZA) + .value("AUTIZB", LIEF::assembly::aarch64::OPCODE::AUTIZB) + .value("AXFLAG", LIEF::assembly::aarch64::OPCODE::AXFLAG) + .value("B", LIEF::assembly::aarch64::OPCODE::B) + .value("BCAX", LIEF::assembly::aarch64::OPCODE::BCAX) + .value("BCAX_ZZZZ", LIEF::assembly::aarch64::OPCODE::BCAX_ZZZZ) + .value("BCcc", LIEF::assembly::aarch64::OPCODE::BCcc) + .value("BDEP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::BDEP_ZZZ_B) + .value("BDEP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::BDEP_ZZZ_D) + .value("BDEP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::BDEP_ZZZ_H) + .value("BDEP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::BDEP_ZZZ_S) + .value("BEXT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::BEXT_ZZZ_B) + .value("BEXT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::BEXT_ZZZ_D) + .value("BEXT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::BEXT_ZZZ_H) + .value("BEXT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::BEXT_ZZZ_S) + .value("BF16DOTlanev4bf16", LIEF::assembly::aarch64::OPCODE::BF16DOTlanev4bf16) + .value("BF16DOTlanev8bf16", LIEF::assembly::aarch64::OPCODE::BF16DOTlanev8bf16) + .value("BF1CVTL", LIEF::assembly::aarch64::OPCODE::BF1CVTL) + .value("BF1CVTL2", LIEF::assembly::aarch64::OPCODE::BF1CVTL2) + .value("BF1CVTLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF1CVTLT_ZZ_BtoH) + .value("BF1CVTL_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF1CVTL_2ZZ_BtoH) + .value("BF1CVT_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF1CVT_2ZZ_BtoH) + .value("BF1CVT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF1CVT_ZZ_BtoH) + .value("BF2CVTL", LIEF::assembly::aarch64::OPCODE::BF2CVTL) + .value("BF2CVTL2", LIEF::assembly::aarch64::OPCODE::BF2CVTL2) + .value("BF2CVTLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF2CVTLT_ZZ_BtoH) + .value("BF2CVTL_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF2CVTL_2ZZ_BtoH) + .value("BF2CVT_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF2CVT_2ZZ_BtoH) + .value("BF2CVT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::BF2CVT_ZZ_BtoH) + .value("BFADD_VG2_M2Z_H", LIEF::assembly::aarch64::OPCODE::BFADD_VG2_M2Z_H) + .value("BFADD_VG4_M4Z_H", LIEF::assembly::aarch64::OPCODE::BFADD_VG4_M4Z_H) + .value("BFADD_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFADD_ZPmZZ) + .value("BFADD_ZZZ", LIEF::assembly::aarch64::OPCODE::BFADD_ZZZ) + .value("BFCLAMP_VG2_2ZZZ_H", LIEF::assembly::aarch64::OPCODE::BFCLAMP_VG2_2ZZZ_H) + .value("BFCLAMP_VG4_4ZZZ_H", LIEF::assembly::aarch64::OPCODE::BFCLAMP_VG4_4ZZZ_H) + .value("BFCLAMP_ZZZ", LIEF::assembly::aarch64::OPCODE::BFCLAMP_ZZZ) + .value("BFCVT", LIEF::assembly::aarch64::OPCODE::BFCVT) + .value("BFCVTN", LIEF::assembly::aarch64::OPCODE::BFCVTN) + .value("BFCVTN2", LIEF::assembly::aarch64::OPCODE::BFCVTN2) + .value("BFCVTNT_ZPmZ", LIEF::assembly::aarch64::OPCODE::BFCVTNT_ZPmZ) + .value("BFCVTNT_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::BFCVTNT_ZPzZ_StoH) + .value("BFCVTN_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::BFCVTN_Z2Z_HtoB) + .value("BFCVTN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::BFCVTN_Z2Z_StoH) + .value("BFCVT_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::BFCVT_Z2Z_HtoB) + .value("BFCVT_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::BFCVT_Z2Z_StoH) + .value("BFCVT_ZPmZ", LIEF::assembly::aarch64::OPCODE::BFCVT_ZPmZ) + .value("BFCVT_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::BFCVT_ZPzZ_StoH) + .value("BFDOT_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2Z2Z_HtoS) + .value("BFDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2ZZI_HtoS) + .value("BFDOT_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG2_M2ZZ_HtoS) + .value("BFDOT_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4Z4Z_HtoS) + .value("BFDOT_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4ZZI_HtoS) + .value("BFDOT_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFDOT_VG4_M4ZZ_HtoS) + .value("BFDOT_ZZI", LIEF::assembly::aarch64::OPCODE::BFDOT_ZZI) + .value("BFDOT_ZZZ", LIEF::assembly::aarch64::OPCODE::BFDOT_ZZZ) + .value("BFDOTv4bf16", LIEF::assembly::aarch64::OPCODE::BFDOTv4bf16) + .value("BFDOTv8bf16", LIEF::assembly::aarch64::OPCODE::BFDOTv8bf16) + .value("BFMAXNM_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMAXNM_VG2_2Z2Z_H) + .value("BFMAXNM_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMAXNM_VG2_2ZZ_H) + .value("BFMAXNM_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMAXNM_VG4_4Z2Z_H) + .value("BFMAXNM_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMAXNM_VG4_4ZZ_H) + .value("BFMAXNM_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMAXNM_ZPmZZ) + .value("BFMAX_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMAX_VG2_2Z2Z_H) + .value("BFMAX_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMAX_VG2_2ZZ_H) + .value("BFMAX_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMAX_VG4_4Z2Z_H) + .value("BFMAX_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMAX_VG4_4ZZ_H) + .value("BFMAX_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMAX_ZPmZZ) + .value("BFMINNM_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMINNM_VG2_2Z2Z_H) + .value("BFMINNM_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMINNM_VG2_2ZZ_H) + .value("BFMINNM_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMINNM_VG4_4Z2Z_H) + .value("BFMINNM_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMINNM_VG4_4ZZ_H) + .value("BFMINNM_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMINNM_ZPmZZ) + .value("BFMIN_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMIN_VG2_2Z2Z_H) + .value("BFMIN_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMIN_VG2_2ZZ_H) + .value("BFMIN_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMIN_VG4_4Z2Z_H) + .value("BFMIN_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMIN_VG4_4ZZ_H) + .value("BFMIN_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMIN_ZPmZZ) + .value("BFMLALB", LIEF::assembly::aarch64::OPCODE::BFMLALB) + .value("BFMLALBIdx", LIEF::assembly::aarch64::OPCODE::BFMLALBIdx) + .value("BFMLALB_ZZZ", LIEF::assembly::aarch64::OPCODE::BFMLALB_ZZZ) + .value("BFMLALB_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMLALB_ZZZI) + .value("BFMLALT", LIEF::assembly::aarch64::OPCODE::BFMLALT) + .value("BFMLALTIdx", LIEF::assembly::aarch64::OPCODE::BFMLALTIdx) + .value("BFMLALT_ZZZ", LIEF::assembly::aarch64::OPCODE::BFMLALT_ZZZ) + .value("BFMLALT_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMLALT_ZZZI) + .value("BFMLAL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_MZZI_HtoS) + .value("BFMLAL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_MZZ_HtoS) + .value("BFMLAL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2Z2Z_HtoS) + .value("BFMLAL_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2ZZI_HtoS) + .value("BFMLAL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG2_M2ZZ_HtoS) + .value("BFMLAL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4Z4Z_HtoS) + .value("BFMLAL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4ZZI_HtoS) + .value("BFMLAL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLAL_VG4_M4ZZ_HtoS) + .value("BFMLA_VG2_M2Z2Z", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2Z2Z) + .value("BFMLA_VG2_M2ZZ", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2ZZ) + .value("BFMLA_VG2_M2ZZI", LIEF::assembly::aarch64::OPCODE::BFMLA_VG2_M2ZZI) + .value("BFMLA_VG4_M4Z4Z", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4Z4Z) + .value("BFMLA_VG4_M4ZZ", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4ZZ) + .value("BFMLA_VG4_M4ZZI", LIEF::assembly::aarch64::OPCODE::BFMLA_VG4_M4ZZI) + .value("BFMLA_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMLA_ZPmZZ) + .value("BFMLA_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMLA_ZZZI) + .value("BFMLSLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::BFMLSLB_ZZZI_S) + .value("BFMLSLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::BFMLSLB_ZZZ_S) + .value("BFMLSLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::BFMLSLT_ZZZI_S) + .value("BFMLSLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::BFMLSLT_ZZZ_S) + .value("BFMLSL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_MZZI_HtoS) + .value("BFMLSL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_MZZ_HtoS) + .value("BFMLSL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2Z2Z_HtoS) + .value("BFMLSL_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2ZZI_HtoS) + .value("BFMLSL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG2_M2ZZ_HtoS) + .value("BFMLSL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4Z4Z_HtoS) + .value("BFMLSL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4ZZI_HtoS) + .value("BFMLSL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMLSL_VG4_M4ZZ_HtoS) + .value("BFMLS_VG2_M2Z2Z", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2Z2Z) + .value("BFMLS_VG2_M2ZZ", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2ZZ) + .value("BFMLS_VG2_M2ZZI", LIEF::assembly::aarch64::OPCODE::BFMLS_VG2_M2ZZI) + .value("BFMLS_VG4_M4Z4Z", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4Z4Z) + .value("BFMLS_VG4_M4ZZ", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4ZZ) + .value("BFMLS_VG4_M4ZZI", LIEF::assembly::aarch64::OPCODE::BFMLS_VG4_M4ZZI) + .value("BFMLS_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMLS_ZPmZZ) + .value("BFMLS_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMLS_ZZZI) + .value("BFMMLA", LIEF::assembly::aarch64::OPCODE::BFMMLA) + .value("BFMMLA_ZZZ_H", LIEF::assembly::aarch64::OPCODE::BFMMLA_ZZZ_H) + .value("BFMMLA_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::BFMMLA_ZZZ_HtoS) + .value("BFMOP4A_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2Z2Z_H) + .value("BFMOP4A_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2Z2Z_S) + .value("BFMOP4A_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2ZZ_H) + .value("BFMOP4A_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::BFMOP4A_M2ZZ_S) + .value("BFMOP4A_MZ2Z_H", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZ2Z_H) + .value("BFMOP4A_MZ2Z_S", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZ2Z_S) + .value("BFMOP4A_MZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZZ_H) + .value("BFMOP4A_MZZ_S", LIEF::assembly::aarch64::OPCODE::BFMOP4A_MZZ_S) + .value("BFMOP4S_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2Z2Z_H) + .value("BFMOP4S_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2Z2Z_S) + .value("BFMOP4S_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2ZZ_H) + .value("BFMOP4S_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::BFMOP4S_M2ZZ_S) + .value("BFMOP4S_MZ2Z_H", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZ2Z_H) + .value("BFMOP4S_MZ2Z_S", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZ2Z_S) + .value("BFMOP4S_MZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZZ_H) + .value("BFMOP4S_MZZ_S", LIEF::assembly::aarch64::OPCODE::BFMOP4S_MZZ_S) + .value("BFMOPA_MPPZZ", LIEF::assembly::aarch64::OPCODE::BFMOPA_MPPZZ) + .value("BFMOPA_MPPZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOPA_MPPZZ_H) + .value("BFMOPS_MPPZZ", LIEF::assembly::aarch64::OPCODE::BFMOPS_MPPZZ) + .value("BFMOPS_MPPZZ_H", LIEF::assembly::aarch64::OPCODE::BFMOPS_MPPZZ_H) + .value("BFMUL_2Z2Z", LIEF::assembly::aarch64::OPCODE::BFMUL_2Z2Z) + .value("BFMUL_2ZZ", LIEF::assembly::aarch64::OPCODE::BFMUL_2ZZ) + .value("BFMUL_4Z4Z", LIEF::assembly::aarch64::OPCODE::BFMUL_4Z4Z) + .value("BFMUL_4ZZ", LIEF::assembly::aarch64::OPCODE::BFMUL_4ZZ) + .value("BFMUL_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFMUL_ZPmZZ) + .value("BFMUL_ZZZ", LIEF::assembly::aarch64::OPCODE::BFMUL_ZZZ) + .value("BFMUL_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMUL_ZZZI) + .value("BFMWri", LIEF::assembly::aarch64::OPCODE::BFMWri) + .value("BFMXri", LIEF::assembly::aarch64::OPCODE::BFMXri) + .value("BFSCALE_2Z2Z", LIEF::assembly::aarch64::OPCODE::BFSCALE_2Z2Z) + .value("BFSCALE_2ZZ", LIEF::assembly::aarch64::OPCODE::BFSCALE_2ZZ) + .value("BFSCALE_4Z4Z", LIEF::assembly::aarch64::OPCODE::BFSCALE_4Z4Z) + .value("BFSCALE_4ZZ", LIEF::assembly::aarch64::OPCODE::BFSCALE_4ZZ) + .value("BFSCALE_ZPZZ_H", LIEF::assembly::aarch64::OPCODE::BFSCALE_ZPZZ_H) + .value("BFSUB_VG2_M2Z_H", LIEF::assembly::aarch64::OPCODE::BFSUB_VG2_M2Z_H) + .value("BFSUB_VG4_M4Z_H", LIEF::assembly::aarch64::OPCODE::BFSUB_VG4_M4Z_H) + .value("BFSUB_ZPmZZ", LIEF::assembly::aarch64::OPCODE::BFSUB_ZPmZZ) + .value("BFSUB_ZZZ", LIEF::assembly::aarch64::OPCODE::BFSUB_ZZZ) + .value("BFTMOPA_M2ZZZI_HtoH", LIEF::assembly::aarch64::OPCODE::BFTMOPA_M2ZZZI_HtoH) + .value("BFTMOPA_M2ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFTMOPA_M2ZZZI_HtoS) + .value("BFVDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::BFVDOT_VG2_M2ZZI_HtoS) + .value("BGRP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::BGRP_ZZZ_B) + .value("BGRP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::BGRP_ZZZ_D) + .value("BGRP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::BGRP_ZZZ_H) + .value("BGRP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::BGRP_ZZZ_S) + .value("BICSWrs", LIEF::assembly::aarch64::OPCODE::BICSWrs) + .value("BICSXrs", LIEF::assembly::aarch64::OPCODE::BICSXrs) + .value("BICS_PPzPP", LIEF::assembly::aarch64::OPCODE::BICS_PPzPP) + .value("BICWrs", LIEF::assembly::aarch64::OPCODE::BICWrs) + .value("BICXrs", LIEF::assembly::aarch64::OPCODE::BICXrs) + .value("BIC_PPzPP", LIEF::assembly::aarch64::OPCODE::BIC_PPzPP) + .value("BIC_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::BIC_ZPmZ_B) + .value("BIC_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::BIC_ZPmZ_D) + .value("BIC_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::BIC_ZPmZ_H) + .value("BIC_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::BIC_ZPmZ_S) + .value("BIC_ZZZ", LIEF::assembly::aarch64::OPCODE::BIC_ZZZ) + .value("BICv16i8", LIEF::assembly::aarch64::OPCODE::BICv16i8) + .value("BICv2i32", LIEF::assembly::aarch64::OPCODE::BICv2i32) + .value("BICv4i16", LIEF::assembly::aarch64::OPCODE::BICv4i16) + .value("BICv4i32", LIEF::assembly::aarch64::OPCODE::BICv4i32) + .value("BICv8i16", LIEF::assembly::aarch64::OPCODE::BICv8i16) + .value("BICv8i8", LIEF::assembly::aarch64::OPCODE::BICv8i8) + .value("BIFv16i8", LIEF::assembly::aarch64::OPCODE::BIFv16i8) + .value("BIFv8i8", LIEF::assembly::aarch64::OPCODE::BIFv8i8) + .value("BITv16i8", LIEF::assembly::aarch64::OPCODE::BITv16i8) + .value("BITv8i8", LIEF::assembly::aarch64::OPCODE::BITv8i8) + .value("BL", LIEF::assembly::aarch64::OPCODE::BL) + .value("BLR", LIEF::assembly::aarch64::OPCODE::BLR) + .value("BLRAA", LIEF::assembly::aarch64::OPCODE::BLRAA) + .value("BLRAAZ", LIEF::assembly::aarch64::OPCODE::BLRAAZ) + .value("BLRAB", LIEF::assembly::aarch64::OPCODE::BLRAB) + .value("BLRABZ", LIEF::assembly::aarch64::OPCODE::BLRABZ) + .value("BMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::BMOPA_MPPZZ_S) + .value("BMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::BMOPS_MPPZZ_S) + .value("BR", LIEF::assembly::aarch64::OPCODE::BR) + .value("BRAA", LIEF::assembly::aarch64::OPCODE::BRAA) + .value("BRAAZ", LIEF::assembly::aarch64::OPCODE::BRAAZ) + .value("BRAB", LIEF::assembly::aarch64::OPCODE::BRAB) + .value("BRABZ", LIEF::assembly::aarch64::OPCODE::BRABZ) + .value("BRB_IALL", LIEF::assembly::aarch64::OPCODE::BRB_IALL) + .value("BRB_INJ", LIEF::assembly::aarch64::OPCODE::BRB_INJ) + .value("BRK", LIEF::assembly::aarch64::OPCODE::BRK) + .value("BRKAS_PPzP", LIEF::assembly::aarch64::OPCODE::BRKAS_PPzP) + .value("BRKA_PPmP", LIEF::assembly::aarch64::OPCODE::BRKA_PPmP) + .value("BRKA_PPzP", LIEF::assembly::aarch64::OPCODE::BRKA_PPzP) + .value("BRKBS_PPzP", LIEF::assembly::aarch64::OPCODE::BRKBS_PPzP) + .value("BRKB_PPmP", LIEF::assembly::aarch64::OPCODE::BRKB_PPmP) + .value("BRKB_PPzP", LIEF::assembly::aarch64::OPCODE::BRKB_PPzP) + .value("BRKNS_PPzP", LIEF::assembly::aarch64::OPCODE::BRKNS_PPzP) + .value("BRKN_PPzP", LIEF::assembly::aarch64::OPCODE::BRKN_PPzP) + .value("BRKPAS_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPAS_PPzPP) + .value("BRKPA_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPA_PPzPP); + opcodes.value("BRKPBS_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPBS_PPzPP) + .value("BRKPB_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPB_PPzPP) + .value("BSL1N_ZZZZ", LIEF::assembly::aarch64::OPCODE::BSL1N_ZZZZ) + .value("BSL2N_ZZZZ", LIEF::assembly::aarch64::OPCODE::BSL2N_ZZZZ) + .value("BSL_ZZZZ", LIEF::assembly::aarch64::OPCODE::BSL_ZZZZ) + .value("BSLv16i8", LIEF::assembly::aarch64::OPCODE::BSLv16i8) + .value("BSLv8i8", LIEF::assembly::aarch64::OPCODE::BSLv8i8) + .value("Bcc", LIEF::assembly::aarch64::OPCODE::Bcc) + .value("CADD_ZZI_B", LIEF::assembly::aarch64::OPCODE::CADD_ZZI_B) + .value("CADD_ZZI_D", LIEF::assembly::aarch64::OPCODE::CADD_ZZI_D) + .value("CADD_ZZI_H", LIEF::assembly::aarch64::OPCODE::CADD_ZZI_H) + .value("CADD_ZZI_S", LIEF::assembly::aarch64::OPCODE::CADD_ZZI_S) + .value("CASAB", LIEF::assembly::aarch64::OPCODE::CASAB) + .value("CASAH", LIEF::assembly::aarch64::OPCODE::CASAH) + .value("CASALB", LIEF::assembly::aarch64::OPCODE::CASALB) + .value("CASALH", LIEF::assembly::aarch64::OPCODE::CASALH) + .value("CASALTX", LIEF::assembly::aarch64::OPCODE::CASALTX) + .value("CASALW", LIEF::assembly::aarch64::OPCODE::CASALW) + .value("CASALX", LIEF::assembly::aarch64::OPCODE::CASALX) + .value("CASATX", LIEF::assembly::aarch64::OPCODE::CASATX) + .value("CASAW", LIEF::assembly::aarch64::OPCODE::CASAW) + .value("CASAX", LIEF::assembly::aarch64::OPCODE::CASAX) + .value("CASB", LIEF::assembly::aarch64::OPCODE::CASB) + .value("CASH", LIEF::assembly::aarch64::OPCODE::CASH) + .value("CASLB", LIEF::assembly::aarch64::OPCODE::CASLB) + .value("CASLH", LIEF::assembly::aarch64::OPCODE::CASLH) + .value("CASLTX", LIEF::assembly::aarch64::OPCODE::CASLTX) + .value("CASLW", LIEF::assembly::aarch64::OPCODE::CASLW) + .value("CASLX", LIEF::assembly::aarch64::OPCODE::CASLX) + .value("CASPALTX", LIEF::assembly::aarch64::OPCODE::CASPALTX) + .value("CASPALW", LIEF::assembly::aarch64::OPCODE::CASPALW) + .value("CASPALX", LIEF::assembly::aarch64::OPCODE::CASPALX) + .value("CASPATX", LIEF::assembly::aarch64::OPCODE::CASPATX) + .value("CASPAW", LIEF::assembly::aarch64::OPCODE::CASPAW) + .value("CASPAX", LIEF::assembly::aarch64::OPCODE::CASPAX) + .value("CASPLTX", LIEF::assembly::aarch64::OPCODE::CASPLTX) + .value("CASPLW", LIEF::assembly::aarch64::OPCODE::CASPLW) + .value("CASPLX", LIEF::assembly::aarch64::OPCODE::CASPLX) + .value("CASPTX", LIEF::assembly::aarch64::OPCODE::CASPTX) + .value("CASPW", LIEF::assembly::aarch64::OPCODE::CASPW) + .value("CASPX", LIEF::assembly::aarch64::OPCODE::CASPX) + .value("CASTX", LIEF::assembly::aarch64::OPCODE::CASTX) + .value("CASW", LIEF::assembly::aarch64::OPCODE::CASW) + .value("CASX", LIEF::assembly::aarch64::OPCODE::CASX) + .value("CBBEQWrr", LIEF::assembly::aarch64::OPCODE::CBBEQWrr) + .value("CBBGEWrr", LIEF::assembly::aarch64::OPCODE::CBBGEWrr) + .value("CBBGTWrr", LIEF::assembly::aarch64::OPCODE::CBBGTWrr) + .value("CBBHIWrr", LIEF::assembly::aarch64::OPCODE::CBBHIWrr) + .value("CBBHSWrr", LIEF::assembly::aarch64::OPCODE::CBBHSWrr) + .value("CBBNEWrr", LIEF::assembly::aarch64::OPCODE::CBBNEWrr) + .value("CBEQWri", LIEF::assembly::aarch64::OPCODE::CBEQWri) + .value("CBEQWrr", LIEF::assembly::aarch64::OPCODE::CBEQWrr) + .value("CBEQXri", LIEF::assembly::aarch64::OPCODE::CBEQXri) + .value("CBEQXrr", LIEF::assembly::aarch64::OPCODE::CBEQXrr) + .value("CBGEWrr", LIEF::assembly::aarch64::OPCODE::CBGEWrr) + .value("CBGEXrr", LIEF::assembly::aarch64::OPCODE::CBGEXrr) + .value("CBGTWri", LIEF::assembly::aarch64::OPCODE::CBGTWri) + .value("CBGTWrr", LIEF::assembly::aarch64::OPCODE::CBGTWrr) + .value("CBGTXri", LIEF::assembly::aarch64::OPCODE::CBGTXri) + .value("CBGTXrr", LIEF::assembly::aarch64::OPCODE::CBGTXrr) + .value("CBHEQWrr", LIEF::assembly::aarch64::OPCODE::CBHEQWrr) + .value("CBHGEWrr", LIEF::assembly::aarch64::OPCODE::CBHGEWrr) + .value("CBHGTWrr", LIEF::assembly::aarch64::OPCODE::CBHGTWrr) + .value("CBHHIWrr", LIEF::assembly::aarch64::OPCODE::CBHHIWrr) + .value("CBHHSWrr", LIEF::assembly::aarch64::OPCODE::CBHHSWrr) + .value("CBHIWri", LIEF::assembly::aarch64::OPCODE::CBHIWri) + .value("CBHIWrr", LIEF::assembly::aarch64::OPCODE::CBHIWrr) + .value("CBHIXri", LIEF::assembly::aarch64::OPCODE::CBHIXri) + .value("CBHIXrr", LIEF::assembly::aarch64::OPCODE::CBHIXrr) + .value("CBHNEWrr", LIEF::assembly::aarch64::OPCODE::CBHNEWrr) + .value("CBHSWrr", LIEF::assembly::aarch64::OPCODE::CBHSWrr) + .value("CBHSXrr", LIEF::assembly::aarch64::OPCODE::CBHSXrr) + .value("CBLOWri", LIEF::assembly::aarch64::OPCODE::CBLOWri) + .value("CBLOXri", LIEF::assembly::aarch64::OPCODE::CBLOXri) + .value("CBLTWri", LIEF::assembly::aarch64::OPCODE::CBLTWri) + .value("CBLTXri", LIEF::assembly::aarch64::OPCODE::CBLTXri) + .value("CBNEWri", LIEF::assembly::aarch64::OPCODE::CBNEWri) + .value("CBNEWrr", LIEF::assembly::aarch64::OPCODE::CBNEWrr) + .value("CBNEXri", LIEF::assembly::aarch64::OPCODE::CBNEXri) + .value("CBNEXrr", LIEF::assembly::aarch64::OPCODE::CBNEXrr) + .value("CBNZW", LIEF::assembly::aarch64::OPCODE::CBNZW) + .value("CBNZX", LIEF::assembly::aarch64::OPCODE::CBNZX) + .value("CBZW", LIEF::assembly::aarch64::OPCODE::CBZW) + .value("CBZX", LIEF::assembly::aarch64::OPCODE::CBZX) + .value("CCMNWi", LIEF::assembly::aarch64::OPCODE::CCMNWi) + .value("CCMNWr", LIEF::assembly::aarch64::OPCODE::CCMNWr) + .value("CCMNXi", LIEF::assembly::aarch64::OPCODE::CCMNXi) + .value("CCMNXr", LIEF::assembly::aarch64::OPCODE::CCMNXr) + .value("CCMPWi", LIEF::assembly::aarch64::OPCODE::CCMPWi) + .value("CCMPWr", LIEF::assembly::aarch64::OPCODE::CCMPWr) + .value("CCMPXi", LIEF::assembly::aarch64::OPCODE::CCMPXi) + .value("CCMPXr", LIEF::assembly::aarch64::OPCODE::CCMPXr) + .value("CDOT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::CDOT_ZZZI_D) + .value("CDOT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::CDOT_ZZZI_S) + .value("CDOT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::CDOT_ZZZ_D) + .value("CDOT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::CDOT_ZZZ_S) + .value("CFINV", LIEF::assembly::aarch64::OPCODE::CFINV) + .value("CHKFEAT", LIEF::assembly::aarch64::OPCODE::CHKFEAT) + .value("CLASTA_RPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTA_RPZ_B) + .value("CLASTA_RPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTA_RPZ_D) + .value("CLASTA_RPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTA_RPZ_H) + .value("CLASTA_RPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTA_RPZ_S) + .value("CLASTA_VPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTA_VPZ_B) + .value("CLASTA_VPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTA_VPZ_D) + .value("CLASTA_VPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTA_VPZ_H) + .value("CLASTA_VPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTA_VPZ_S) + .value("CLASTA_ZPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTA_ZPZ_B) + .value("CLASTA_ZPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTA_ZPZ_D) + .value("CLASTA_ZPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTA_ZPZ_H) + .value("CLASTA_ZPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTA_ZPZ_S) + .value("CLASTB_RPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTB_RPZ_B) + .value("CLASTB_RPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTB_RPZ_D) + .value("CLASTB_RPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTB_RPZ_H) + .value("CLASTB_RPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTB_RPZ_S) + .value("CLASTB_VPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTB_VPZ_B) + .value("CLASTB_VPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTB_VPZ_D) + .value("CLASTB_VPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTB_VPZ_H) + .value("CLASTB_VPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTB_VPZ_S) + .value("CLASTB_ZPZ_B", LIEF::assembly::aarch64::OPCODE::CLASTB_ZPZ_B) + .value("CLASTB_ZPZ_D", LIEF::assembly::aarch64::OPCODE::CLASTB_ZPZ_D) + .value("CLASTB_ZPZ_H", LIEF::assembly::aarch64::OPCODE::CLASTB_ZPZ_H) + .value("CLASTB_ZPZ_S", LIEF::assembly::aarch64::OPCODE::CLASTB_ZPZ_S) + .value("CLREX", LIEF::assembly::aarch64::OPCODE::CLREX) + .value("CLSWr", LIEF::assembly::aarch64::OPCODE::CLSWr) + .value("CLSXr", LIEF::assembly::aarch64::OPCODE::CLSXr) + .value("CLS_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_B) + .value("CLS_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_D) + .value("CLS_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_H) + .value("CLS_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::CLS_ZPmZ_S) + .value("CLS_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::CLS_ZPzZ_B) + .value("CLS_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::CLS_ZPzZ_D) + .value("CLS_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::CLS_ZPzZ_H) + .value("CLS_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::CLS_ZPzZ_S) + .value("CLSv16i8", LIEF::assembly::aarch64::OPCODE::CLSv16i8) + .value("CLSv2i32", LIEF::assembly::aarch64::OPCODE::CLSv2i32) + .value("CLSv4i16", LIEF::assembly::aarch64::OPCODE::CLSv4i16) + .value("CLSv4i32", LIEF::assembly::aarch64::OPCODE::CLSv4i32) + .value("CLSv8i16", LIEF::assembly::aarch64::OPCODE::CLSv8i16) + .value("CLSv8i8", LIEF::assembly::aarch64::OPCODE::CLSv8i8) + .value("CLZWr", LIEF::assembly::aarch64::OPCODE::CLZWr) + .value("CLZXr", LIEF::assembly::aarch64::OPCODE::CLZXr) + .value("CLZ_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_B) + .value("CLZ_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_D) + .value("CLZ_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_H) + .value("CLZ_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::CLZ_ZPmZ_S) + .value("CLZ_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::CLZ_ZPzZ_B) + .value("CLZ_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::CLZ_ZPzZ_D) + .value("CLZ_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::CLZ_ZPzZ_H) + .value("CLZ_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::CLZ_ZPzZ_S) + .value("CLZv16i8", LIEF::assembly::aarch64::OPCODE::CLZv16i8) + .value("CLZv2i32", LIEF::assembly::aarch64::OPCODE::CLZv2i32) + .value("CLZv4i16", LIEF::assembly::aarch64::OPCODE::CLZv4i16) + .value("CLZv4i32", LIEF::assembly::aarch64::OPCODE::CLZv4i32) + .value("CLZv8i16", LIEF::assembly::aarch64::OPCODE::CLZv8i16) + .value("CLZv8i8", LIEF::assembly::aarch64::OPCODE::CLZv8i8) + .value("CMEQv16i8", LIEF::assembly::aarch64::OPCODE::CMEQv16i8) + .value("CMEQv16i8rz", LIEF::assembly::aarch64::OPCODE::CMEQv16i8rz) + .value("CMEQv1i64", LIEF::assembly::aarch64::OPCODE::CMEQv1i64) + .value("CMEQv1i64rz", LIEF::assembly::aarch64::OPCODE::CMEQv1i64rz) + .value("CMEQv2i32", LIEF::assembly::aarch64::OPCODE::CMEQv2i32) + .value("CMEQv2i32rz", LIEF::assembly::aarch64::OPCODE::CMEQv2i32rz) + .value("CMEQv2i64", LIEF::assembly::aarch64::OPCODE::CMEQv2i64) + .value("CMEQv2i64rz", LIEF::assembly::aarch64::OPCODE::CMEQv2i64rz) + .value("CMEQv4i16", LIEF::assembly::aarch64::OPCODE::CMEQv4i16) + .value("CMEQv4i16rz", LIEF::assembly::aarch64::OPCODE::CMEQv4i16rz) + .value("CMEQv4i32", LIEF::assembly::aarch64::OPCODE::CMEQv4i32) + .value("CMEQv4i32rz", LIEF::assembly::aarch64::OPCODE::CMEQv4i32rz) + .value("CMEQv8i16", LIEF::assembly::aarch64::OPCODE::CMEQv8i16) + .value("CMEQv8i16rz", LIEF::assembly::aarch64::OPCODE::CMEQv8i16rz) + .value("CMEQv8i8", LIEF::assembly::aarch64::OPCODE::CMEQv8i8) + .value("CMEQv8i8rz", LIEF::assembly::aarch64::OPCODE::CMEQv8i8rz) + .value("CMGEv16i8", LIEF::assembly::aarch64::OPCODE::CMGEv16i8) + .value("CMGEv16i8rz", LIEF::assembly::aarch64::OPCODE::CMGEv16i8rz) + .value("CMGEv1i64", LIEF::assembly::aarch64::OPCODE::CMGEv1i64) + .value("CMGEv1i64rz", LIEF::assembly::aarch64::OPCODE::CMGEv1i64rz) + .value("CMGEv2i32", LIEF::assembly::aarch64::OPCODE::CMGEv2i32) + .value("CMGEv2i32rz", LIEF::assembly::aarch64::OPCODE::CMGEv2i32rz) + .value("CMGEv2i64", LIEF::assembly::aarch64::OPCODE::CMGEv2i64) + .value("CMGEv2i64rz", LIEF::assembly::aarch64::OPCODE::CMGEv2i64rz) + .value("CMGEv4i16", LIEF::assembly::aarch64::OPCODE::CMGEv4i16) + .value("CMGEv4i16rz", LIEF::assembly::aarch64::OPCODE::CMGEv4i16rz) + .value("CMGEv4i32", LIEF::assembly::aarch64::OPCODE::CMGEv4i32) + .value("CMGEv4i32rz", LIEF::assembly::aarch64::OPCODE::CMGEv4i32rz) + .value("CMGEv8i16", LIEF::assembly::aarch64::OPCODE::CMGEv8i16) + .value("CMGEv8i16rz", LIEF::assembly::aarch64::OPCODE::CMGEv8i16rz) + .value("CMGEv8i8", LIEF::assembly::aarch64::OPCODE::CMGEv8i8) + .value("CMGEv8i8rz", LIEF::assembly::aarch64::OPCODE::CMGEv8i8rz) + .value("CMGTv16i8", LIEF::assembly::aarch64::OPCODE::CMGTv16i8) + .value("CMGTv16i8rz", LIEF::assembly::aarch64::OPCODE::CMGTv16i8rz) + .value("CMGTv1i64", LIEF::assembly::aarch64::OPCODE::CMGTv1i64) + .value("CMGTv1i64rz", LIEF::assembly::aarch64::OPCODE::CMGTv1i64rz) + .value("CMGTv2i32", LIEF::assembly::aarch64::OPCODE::CMGTv2i32) + .value("CMGTv2i32rz", LIEF::assembly::aarch64::OPCODE::CMGTv2i32rz) + .value("CMGTv2i64", LIEF::assembly::aarch64::OPCODE::CMGTv2i64) + .value("CMGTv2i64rz", LIEF::assembly::aarch64::OPCODE::CMGTv2i64rz) + .value("CMGTv4i16", LIEF::assembly::aarch64::OPCODE::CMGTv4i16) + .value("CMGTv4i16rz", LIEF::assembly::aarch64::OPCODE::CMGTv4i16rz) + .value("CMGTv4i32", LIEF::assembly::aarch64::OPCODE::CMGTv4i32) + .value("CMGTv4i32rz", LIEF::assembly::aarch64::OPCODE::CMGTv4i32rz) + .value("CMGTv8i16", LIEF::assembly::aarch64::OPCODE::CMGTv8i16) + .value("CMGTv8i16rz", LIEF::assembly::aarch64::OPCODE::CMGTv8i16rz) + .value("CMGTv8i8", LIEF::assembly::aarch64::OPCODE::CMGTv8i8) + .value("CMGTv8i8rz", LIEF::assembly::aarch64::OPCODE::CMGTv8i8rz) + .value("CMHIv16i8", LIEF::assembly::aarch64::OPCODE::CMHIv16i8) + .value("CMHIv1i64", LIEF::assembly::aarch64::OPCODE::CMHIv1i64) + .value("CMHIv2i32", LIEF::assembly::aarch64::OPCODE::CMHIv2i32) + .value("CMHIv2i64", LIEF::assembly::aarch64::OPCODE::CMHIv2i64) + .value("CMHIv4i16", LIEF::assembly::aarch64::OPCODE::CMHIv4i16) + .value("CMHIv4i32", LIEF::assembly::aarch64::OPCODE::CMHIv4i32) + .value("CMHIv8i16", LIEF::assembly::aarch64::OPCODE::CMHIv8i16) + .value("CMHIv8i8", LIEF::assembly::aarch64::OPCODE::CMHIv8i8) + .value("CMHSv16i8", LIEF::assembly::aarch64::OPCODE::CMHSv16i8) + .value("CMHSv1i64", LIEF::assembly::aarch64::OPCODE::CMHSv1i64) + .value("CMHSv2i32", LIEF::assembly::aarch64::OPCODE::CMHSv2i32) + .value("CMHSv2i64", LIEF::assembly::aarch64::OPCODE::CMHSv2i64) + .value("CMHSv4i16", LIEF::assembly::aarch64::OPCODE::CMHSv4i16) + .value("CMHSv4i32", LIEF::assembly::aarch64::OPCODE::CMHSv4i32) + .value("CMHSv8i16", LIEF::assembly::aarch64::OPCODE::CMHSv8i16) + .value("CMHSv8i8", LIEF::assembly::aarch64::OPCODE::CMHSv8i8) + .value("CMLA_ZZZI_H", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZI_H) + .value("CMLA_ZZZI_S", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZI_S) + .value("CMLA_ZZZ_B", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZ_B) + .value("CMLA_ZZZ_D", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZ_D) + .value("CMLA_ZZZ_H", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZ_H) + .value("CMLA_ZZZ_S", LIEF::assembly::aarch64::OPCODE::CMLA_ZZZ_S) + .value("CMLEv16i8rz", LIEF::assembly::aarch64::OPCODE::CMLEv16i8rz) + .value("CMLEv1i64rz", LIEF::assembly::aarch64::OPCODE::CMLEv1i64rz) + .value("CMLEv2i32rz", LIEF::assembly::aarch64::OPCODE::CMLEv2i32rz) + .value("CMLEv2i64rz", LIEF::assembly::aarch64::OPCODE::CMLEv2i64rz) + .value("CMLEv4i16rz", LIEF::assembly::aarch64::OPCODE::CMLEv4i16rz) + .value("CMLEv4i32rz", LIEF::assembly::aarch64::OPCODE::CMLEv4i32rz) + .value("CMLEv8i16rz", LIEF::assembly::aarch64::OPCODE::CMLEv8i16rz) + .value("CMLEv8i8rz", LIEF::assembly::aarch64::OPCODE::CMLEv8i8rz) + .value("CMLTv16i8rz", LIEF::assembly::aarch64::OPCODE::CMLTv16i8rz) + .value("CMLTv1i64rz", LIEF::assembly::aarch64::OPCODE::CMLTv1i64rz) + .value("CMLTv2i32rz", LIEF::assembly::aarch64::OPCODE::CMLTv2i32rz) + .value("CMLTv2i64rz", LIEF::assembly::aarch64::OPCODE::CMLTv2i64rz) + .value("CMLTv4i16rz", LIEF::assembly::aarch64::OPCODE::CMLTv4i16rz) + .value("CMLTv4i32rz", LIEF::assembly::aarch64::OPCODE::CMLTv4i32rz) + .value("CMLTv8i16rz", LIEF::assembly::aarch64::OPCODE::CMLTv8i16rz) + .value("CMLTv8i8rz", LIEF::assembly::aarch64::OPCODE::CMLTv8i8rz) + .value("CMPEQ_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_B) + .value("CMPEQ_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_D) + .value("CMPEQ_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_H) + .value("CMPEQ_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_S) + .value("CMPEQ_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZZ_B) + .value("CMPEQ_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZZ_D) + .value("CMPEQ_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZZ_H) + .value("CMPEQ_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZZ_S) + .value("CMPEQ_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPEQ_WIDE_PPzZZ_B) + .value("CMPEQ_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPEQ_WIDE_PPzZZ_H) + .value("CMPEQ_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPEQ_WIDE_PPzZZ_S) + .value("CMPGE_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZI_B) + .value("CMPGE_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZI_D) + .value("CMPGE_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZI_H) + .value("CMPGE_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZI_S) + .value("CMPGE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZZ_B) + .value("CMPGE_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZZ_D) + .value("CMPGE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZZ_H) + .value("CMPGE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPGE_PPzZZ_S) + .value("CMPGE_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPGE_WIDE_PPzZZ_B) + .value("CMPGE_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPGE_WIDE_PPzZZ_H) + .value("CMPGE_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPGE_WIDE_PPzZZ_S) + .value("CMPGT_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZI_B) + .value("CMPGT_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZI_D) + .value("CMPGT_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZI_H) + .value("CMPGT_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZI_S) + .value("CMPGT_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZZ_B) + .value("CMPGT_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZZ_D) + .value("CMPGT_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZZ_H) + .value("CMPGT_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPGT_PPzZZ_S) + .value("CMPGT_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPGT_WIDE_PPzZZ_B) + .value("CMPGT_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPGT_WIDE_PPzZZ_H) + .value("CMPGT_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPGT_WIDE_PPzZZ_S) + .value("CMPHI_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZI_B) + .value("CMPHI_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZI_D) + .value("CMPHI_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZI_H) + .value("CMPHI_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZI_S) + .value("CMPHI_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZZ_B) + .value("CMPHI_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZZ_D) + .value("CMPHI_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZZ_H) + .value("CMPHI_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPHI_PPzZZ_S) + .value("CMPHI_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPHI_WIDE_PPzZZ_B) + .value("CMPHI_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPHI_WIDE_PPzZZ_H) + .value("CMPHI_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPHI_WIDE_PPzZZ_S) + .value("CMPHS_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZI_B) + .value("CMPHS_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZI_D) + .value("CMPHS_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZI_H) + .value("CMPHS_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZI_S) + .value("CMPHS_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZZ_B) + .value("CMPHS_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZZ_D) + .value("CMPHS_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZZ_H) + .value("CMPHS_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPHS_PPzZZ_S) + .value("CMPHS_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPHS_WIDE_PPzZZ_B) + .value("CMPHS_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPHS_WIDE_PPzZZ_H) + .value("CMPHS_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPHS_WIDE_PPzZZ_S) + .value("CMPLE_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_B) + .value("CMPLE_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_D) + .value("CMPLE_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_H) + .value("CMPLE_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_S); + opcodes.value("CMPLE_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_B) + .value("CMPLE_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_H) + .value("CMPLE_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_S) + .value("CMPLO_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLO_PPzZI_B) + .value("CMPLO_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPLO_PPzZI_D) + .value("CMPLO_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPLO_PPzZI_H) + .value("CMPLO_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLO_PPzZI_S) + .value("CMPLO_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLO_WIDE_PPzZZ_B) + .value("CMPLO_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPLO_WIDE_PPzZZ_H) + .value("CMPLO_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPLO_WIDE_PPzZZ_S) + .value("CMPLS_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLS_PPzZI_B) + .value("CMPLS_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPLS_PPzZI_D) + .value("CMPLS_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPLS_PPzZI_H) + .value("CMPLS_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLS_PPzZI_S) + .value("CMPLS_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLS_WIDE_PPzZZ_B) + .value("CMPLS_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPLS_WIDE_PPzZZ_H) + .value("CMPLS_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPLS_WIDE_PPzZZ_S) + .value("CMPLT_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLT_PPzZI_B) + .value("CMPLT_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPLT_PPzZI_D) + .value("CMPLT_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPLT_PPzZI_H) + .value("CMPLT_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLT_PPzZI_S) + .value("CMPLT_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLT_WIDE_PPzZZ_B) + .value("CMPLT_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPLT_WIDE_PPzZZ_H) + .value("CMPLT_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPLT_WIDE_PPzZZ_S) + .value("CMPNE_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZI_B) + .value("CMPNE_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZI_D) + .value("CMPNE_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZI_H) + .value("CMPNE_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZI_S) + .value("CMPNE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZZ_B) + .value("CMPNE_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZZ_D) + .value("CMPNE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZZ_H) + .value("CMPNE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPNE_PPzZZ_S) + .value("CMPNE_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPNE_WIDE_PPzZZ_B) + .value("CMPNE_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPNE_WIDE_PPzZZ_H) + .value("CMPNE_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPNE_WIDE_PPzZZ_S) + .value("CMTSTv16i8", LIEF::assembly::aarch64::OPCODE::CMTSTv16i8) + .value("CMTSTv1i64", LIEF::assembly::aarch64::OPCODE::CMTSTv1i64) + .value("CMTSTv2i32", LIEF::assembly::aarch64::OPCODE::CMTSTv2i32) + .value("CMTSTv2i64", LIEF::assembly::aarch64::OPCODE::CMTSTv2i64) + .value("CMTSTv4i16", LIEF::assembly::aarch64::OPCODE::CMTSTv4i16) + .value("CMTSTv4i32", LIEF::assembly::aarch64::OPCODE::CMTSTv4i32) + .value("CMTSTv8i16", LIEF::assembly::aarch64::OPCODE::CMTSTv8i16) + .value("CMTSTv8i8", LIEF::assembly::aarch64::OPCODE::CMTSTv8i8) + .value("CNOT_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_B) + .value("CNOT_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_D) + .value("CNOT_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_H) + .value("CNOT_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::CNOT_ZPmZ_S) + .value("CNOT_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::CNOT_ZPzZ_B) + .value("CNOT_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::CNOT_ZPzZ_D) + .value("CNOT_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::CNOT_ZPzZ_H) + .value("CNOT_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::CNOT_ZPzZ_S) + .value("CNTB_XPiI", LIEF::assembly::aarch64::OPCODE::CNTB_XPiI) + .value("CNTD_XPiI", LIEF::assembly::aarch64::OPCODE::CNTD_XPiI) + .value("CNTH_XPiI", LIEF::assembly::aarch64::OPCODE::CNTH_XPiI) + .value("CNTP_XCI_B", LIEF::assembly::aarch64::OPCODE::CNTP_XCI_B) + .value("CNTP_XCI_D", LIEF::assembly::aarch64::OPCODE::CNTP_XCI_D) + .value("CNTP_XCI_H", LIEF::assembly::aarch64::OPCODE::CNTP_XCI_H) + .value("CNTP_XCI_S", LIEF::assembly::aarch64::OPCODE::CNTP_XCI_S) + .value("CNTP_XPP_B", LIEF::assembly::aarch64::OPCODE::CNTP_XPP_B) + .value("CNTP_XPP_D", LIEF::assembly::aarch64::OPCODE::CNTP_XPP_D) + .value("CNTP_XPP_H", LIEF::assembly::aarch64::OPCODE::CNTP_XPP_H) + .value("CNTP_XPP_S", LIEF::assembly::aarch64::OPCODE::CNTP_XPP_S) + .value("CNTW_XPiI", LIEF::assembly::aarch64::OPCODE::CNTW_XPiI) + .value("CNTWr", LIEF::assembly::aarch64::OPCODE::CNTWr) + .value("CNTXr", LIEF::assembly::aarch64::OPCODE::CNTXr) + .value("CNT_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_B) + .value("CNT_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_D) + .value("CNT_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_H) + .value("CNT_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::CNT_ZPmZ_S) + .value("CNT_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::CNT_ZPzZ_B) + .value("CNT_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::CNT_ZPzZ_D) + .value("CNT_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::CNT_ZPzZ_H) + .value("CNT_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::CNT_ZPzZ_S) + .value("CNTv16i8", LIEF::assembly::aarch64::OPCODE::CNTv16i8) + .value("CNTv8i8", LIEF::assembly::aarch64::OPCODE::CNTv8i8) + .value("COMPACT_ZPZ_B", LIEF::assembly::aarch64::OPCODE::COMPACT_ZPZ_B) + .value("COMPACT_ZPZ_D", LIEF::assembly::aarch64::OPCODE::COMPACT_ZPZ_D) + .value("COMPACT_ZPZ_H", LIEF::assembly::aarch64::OPCODE::COMPACT_ZPZ_H) + .value("COMPACT_ZPZ_S", LIEF::assembly::aarch64::OPCODE::COMPACT_ZPZ_S) + .value("CPYE", LIEF::assembly::aarch64::OPCODE::CPYE) + .value("CPYEN", LIEF::assembly::aarch64::OPCODE::CPYEN) + .value("CPYERN", LIEF::assembly::aarch64::OPCODE::CPYERN) + .value("CPYERT", LIEF::assembly::aarch64::OPCODE::CPYERT) + .value("CPYERTN", LIEF::assembly::aarch64::OPCODE::CPYERTN) + .value("CPYERTRN", LIEF::assembly::aarch64::OPCODE::CPYERTRN) + .value("CPYERTWN", LIEF::assembly::aarch64::OPCODE::CPYERTWN) + .value("CPYET", LIEF::assembly::aarch64::OPCODE::CPYET) + .value("CPYETN", LIEF::assembly::aarch64::OPCODE::CPYETN) + .value("CPYETRN", LIEF::assembly::aarch64::OPCODE::CPYETRN) + .value("CPYETWN", LIEF::assembly::aarch64::OPCODE::CPYETWN) + .value("CPYEWN", LIEF::assembly::aarch64::OPCODE::CPYEWN) + .value("CPYEWT", LIEF::assembly::aarch64::OPCODE::CPYEWT) + .value("CPYEWTN", LIEF::assembly::aarch64::OPCODE::CPYEWTN) + .value("CPYEWTRN", LIEF::assembly::aarch64::OPCODE::CPYEWTRN) + .value("CPYEWTWN", LIEF::assembly::aarch64::OPCODE::CPYEWTWN) + .value("CPYFE", LIEF::assembly::aarch64::OPCODE::CPYFE) + .value("CPYFEN", LIEF::assembly::aarch64::OPCODE::CPYFEN) + .value("CPYFERN", LIEF::assembly::aarch64::OPCODE::CPYFERN) + .value("CPYFERT", LIEF::assembly::aarch64::OPCODE::CPYFERT) + .value("CPYFERTN", LIEF::assembly::aarch64::OPCODE::CPYFERTN) + .value("CPYFERTRN", LIEF::assembly::aarch64::OPCODE::CPYFERTRN) + .value("CPYFERTWN", LIEF::assembly::aarch64::OPCODE::CPYFERTWN) + .value("CPYFET", LIEF::assembly::aarch64::OPCODE::CPYFET) + .value("CPYFETN", LIEF::assembly::aarch64::OPCODE::CPYFETN) + .value("CPYFETRN", LIEF::assembly::aarch64::OPCODE::CPYFETRN) + .value("CPYFETWN", LIEF::assembly::aarch64::OPCODE::CPYFETWN) + .value("CPYFEWN", LIEF::assembly::aarch64::OPCODE::CPYFEWN) + .value("CPYFEWT", LIEF::assembly::aarch64::OPCODE::CPYFEWT) + .value("CPYFEWTN", LIEF::assembly::aarch64::OPCODE::CPYFEWTN) + .value("CPYFEWTRN", LIEF::assembly::aarch64::OPCODE::CPYFEWTRN) + .value("CPYFEWTWN", LIEF::assembly::aarch64::OPCODE::CPYFEWTWN) + .value("CPYFM", LIEF::assembly::aarch64::OPCODE::CPYFM) + .value("CPYFMN", LIEF::assembly::aarch64::OPCODE::CPYFMN) + .value("CPYFMRN", LIEF::assembly::aarch64::OPCODE::CPYFMRN) + .value("CPYFMRT", LIEF::assembly::aarch64::OPCODE::CPYFMRT) + .value("CPYFMRTN", LIEF::assembly::aarch64::OPCODE::CPYFMRTN) + .value("CPYFMRTRN", LIEF::assembly::aarch64::OPCODE::CPYFMRTRN) + .value("CPYFMRTWN", LIEF::assembly::aarch64::OPCODE::CPYFMRTWN) + .value("CPYFMT", LIEF::assembly::aarch64::OPCODE::CPYFMT) + .value("CPYFMTN", LIEF::assembly::aarch64::OPCODE::CPYFMTN) + .value("CPYFMTRN", LIEF::assembly::aarch64::OPCODE::CPYFMTRN) + .value("CPYFMTWN", LIEF::assembly::aarch64::OPCODE::CPYFMTWN) + .value("CPYFMWN", LIEF::assembly::aarch64::OPCODE::CPYFMWN) + .value("CPYFMWT", LIEF::assembly::aarch64::OPCODE::CPYFMWT) + .value("CPYFMWTN", LIEF::assembly::aarch64::OPCODE::CPYFMWTN) + .value("CPYFMWTRN", LIEF::assembly::aarch64::OPCODE::CPYFMWTRN) + .value("CPYFMWTWN", LIEF::assembly::aarch64::OPCODE::CPYFMWTWN) + .value("CPYFP", LIEF::assembly::aarch64::OPCODE::CPYFP) + .value("CPYFPN", LIEF::assembly::aarch64::OPCODE::CPYFPN) + .value("CPYFPRN", LIEF::assembly::aarch64::OPCODE::CPYFPRN) + .value("CPYFPRT", LIEF::assembly::aarch64::OPCODE::CPYFPRT) + .value("CPYFPRTN", LIEF::assembly::aarch64::OPCODE::CPYFPRTN) + .value("CPYFPRTRN", LIEF::assembly::aarch64::OPCODE::CPYFPRTRN) + .value("CPYFPRTWN", LIEF::assembly::aarch64::OPCODE::CPYFPRTWN) + .value("CPYFPT", LIEF::assembly::aarch64::OPCODE::CPYFPT) + .value("CPYFPTN", LIEF::assembly::aarch64::OPCODE::CPYFPTN) + .value("CPYFPTRN", LIEF::assembly::aarch64::OPCODE::CPYFPTRN) + .value("CPYFPTWN", LIEF::assembly::aarch64::OPCODE::CPYFPTWN) + .value("CPYFPWN", LIEF::assembly::aarch64::OPCODE::CPYFPWN) + .value("CPYFPWT", LIEF::assembly::aarch64::OPCODE::CPYFPWT) + .value("CPYFPWTN", LIEF::assembly::aarch64::OPCODE::CPYFPWTN) + .value("CPYFPWTRN", LIEF::assembly::aarch64::OPCODE::CPYFPWTRN) + .value("CPYFPWTWN", LIEF::assembly::aarch64::OPCODE::CPYFPWTWN) + .value("CPYM", LIEF::assembly::aarch64::OPCODE::CPYM) + .value("CPYMN", LIEF::assembly::aarch64::OPCODE::CPYMN) + .value("CPYMRN", LIEF::assembly::aarch64::OPCODE::CPYMRN) + .value("CPYMRT", LIEF::assembly::aarch64::OPCODE::CPYMRT) + .value("CPYMRTN", LIEF::assembly::aarch64::OPCODE::CPYMRTN) + .value("CPYMRTRN", LIEF::assembly::aarch64::OPCODE::CPYMRTRN) + .value("CPYMRTWN", LIEF::assembly::aarch64::OPCODE::CPYMRTWN) + .value("CPYMT", LIEF::assembly::aarch64::OPCODE::CPYMT) + .value("CPYMTN", LIEF::assembly::aarch64::OPCODE::CPYMTN) + .value("CPYMTRN", LIEF::assembly::aarch64::OPCODE::CPYMTRN) + .value("CPYMTWN", LIEF::assembly::aarch64::OPCODE::CPYMTWN) + .value("CPYMWN", LIEF::assembly::aarch64::OPCODE::CPYMWN) + .value("CPYMWT", LIEF::assembly::aarch64::OPCODE::CPYMWT) + .value("CPYMWTN", LIEF::assembly::aarch64::OPCODE::CPYMWTN) + .value("CPYMWTRN", LIEF::assembly::aarch64::OPCODE::CPYMWTRN) + .value("CPYMWTWN", LIEF::assembly::aarch64::OPCODE::CPYMWTWN) + .value("CPYP", LIEF::assembly::aarch64::OPCODE::CPYP) + .value("CPYPN", LIEF::assembly::aarch64::OPCODE::CPYPN) + .value("CPYPRN", LIEF::assembly::aarch64::OPCODE::CPYPRN) + .value("CPYPRT", LIEF::assembly::aarch64::OPCODE::CPYPRT) + .value("CPYPRTN", LIEF::assembly::aarch64::OPCODE::CPYPRTN) + .value("CPYPRTRN", LIEF::assembly::aarch64::OPCODE::CPYPRTRN) + .value("CPYPRTWN", LIEF::assembly::aarch64::OPCODE::CPYPRTWN) + .value("CPYPT", LIEF::assembly::aarch64::OPCODE::CPYPT) + .value("CPYPTN", LIEF::assembly::aarch64::OPCODE::CPYPTN) + .value("CPYPTRN", LIEF::assembly::aarch64::OPCODE::CPYPTRN) + .value("CPYPTWN", LIEF::assembly::aarch64::OPCODE::CPYPTWN) + .value("CPYPWN", LIEF::assembly::aarch64::OPCODE::CPYPWN) + .value("CPYPWT", LIEF::assembly::aarch64::OPCODE::CPYPWT) + .value("CPYPWTN", LIEF::assembly::aarch64::OPCODE::CPYPWTN) + .value("CPYPWTRN", LIEF::assembly::aarch64::OPCODE::CPYPWTRN) + .value("CPYPWTWN", LIEF::assembly::aarch64::OPCODE::CPYPWTWN) + .value("CPY_ZPmI_B", LIEF::assembly::aarch64::OPCODE::CPY_ZPmI_B) + .value("CPY_ZPmI_D", LIEF::assembly::aarch64::OPCODE::CPY_ZPmI_D) + .value("CPY_ZPmI_H", LIEF::assembly::aarch64::OPCODE::CPY_ZPmI_H) + .value("CPY_ZPmI_S", LIEF::assembly::aarch64::OPCODE::CPY_ZPmI_S) + .value("CPY_ZPmR_B", LIEF::assembly::aarch64::OPCODE::CPY_ZPmR_B) + .value("CPY_ZPmR_D", LIEF::assembly::aarch64::OPCODE::CPY_ZPmR_D) + .value("CPY_ZPmR_H", LIEF::assembly::aarch64::OPCODE::CPY_ZPmR_H) + .value("CPY_ZPmR_S", LIEF::assembly::aarch64::OPCODE::CPY_ZPmR_S) + .value("CPY_ZPmV_B", LIEF::assembly::aarch64::OPCODE::CPY_ZPmV_B) + .value("CPY_ZPmV_D", LIEF::assembly::aarch64::OPCODE::CPY_ZPmV_D) + .value("CPY_ZPmV_H", LIEF::assembly::aarch64::OPCODE::CPY_ZPmV_H) + .value("CPY_ZPmV_S", LIEF::assembly::aarch64::OPCODE::CPY_ZPmV_S) + .value("CPY_ZPzI_B", LIEF::assembly::aarch64::OPCODE::CPY_ZPzI_B) + .value("CPY_ZPzI_D", LIEF::assembly::aarch64::OPCODE::CPY_ZPzI_D) + .value("CPY_ZPzI_H", LIEF::assembly::aarch64::OPCODE::CPY_ZPzI_H) + .value("CPY_ZPzI_S", LIEF::assembly::aarch64::OPCODE::CPY_ZPzI_S) + .value("CRC32Brr", LIEF::assembly::aarch64::OPCODE::CRC32Brr) + .value("CRC32CBrr", LIEF::assembly::aarch64::OPCODE::CRC32CBrr) + .value("CRC32CHrr", LIEF::assembly::aarch64::OPCODE::CRC32CHrr) + .value("CRC32CWrr", LIEF::assembly::aarch64::OPCODE::CRC32CWrr) + .value("CRC32CXrr", LIEF::assembly::aarch64::OPCODE::CRC32CXrr) + .value("CRC32Hrr", LIEF::assembly::aarch64::OPCODE::CRC32Hrr) + .value("CRC32Wrr", LIEF::assembly::aarch64::OPCODE::CRC32Wrr) + .value("CRC32Xrr", LIEF::assembly::aarch64::OPCODE::CRC32Xrr) + .value("CSELWr", LIEF::assembly::aarch64::OPCODE::CSELWr) + .value("CSELXr", LIEF::assembly::aarch64::OPCODE::CSELXr) + .value("CSINCWr", LIEF::assembly::aarch64::OPCODE::CSINCWr) + .value("CSINCXr", LIEF::assembly::aarch64::OPCODE::CSINCXr) + .value("CSINVWr", LIEF::assembly::aarch64::OPCODE::CSINVWr) + .value("CSINVXr", LIEF::assembly::aarch64::OPCODE::CSINVXr) + .value("CSNEGWr", LIEF::assembly::aarch64::OPCODE::CSNEGWr) + .value("CSNEGXr", LIEF::assembly::aarch64::OPCODE::CSNEGXr) + .value("CTERMEQ_WW", LIEF::assembly::aarch64::OPCODE::CTERMEQ_WW) + .value("CTERMEQ_XX", LIEF::assembly::aarch64::OPCODE::CTERMEQ_XX) + .value("CTERMNE_WW", LIEF::assembly::aarch64::OPCODE::CTERMNE_WW) + .value("CTERMNE_XX", LIEF::assembly::aarch64::OPCODE::CTERMNE_XX) + .value("CTZWr", LIEF::assembly::aarch64::OPCODE::CTZWr) + .value("CTZXr", LIEF::assembly::aarch64::OPCODE::CTZXr) + .value("DCPS1", LIEF::assembly::aarch64::OPCODE::DCPS1) + .value("DCPS2", LIEF::assembly::aarch64::OPCODE::DCPS2) + .value("DCPS3", LIEF::assembly::aarch64::OPCODE::DCPS3) + .value("DECB_XPiI", LIEF::assembly::aarch64::OPCODE::DECB_XPiI) + .value("DECD_XPiI", LIEF::assembly::aarch64::OPCODE::DECD_XPiI) + .value("DECD_ZPiI", LIEF::assembly::aarch64::OPCODE::DECD_ZPiI) + .value("DECH_XPiI", LIEF::assembly::aarch64::OPCODE::DECH_XPiI) + .value("DECH_ZPiI", LIEF::assembly::aarch64::OPCODE::DECH_ZPiI) + .value("DECP_XP_B", LIEF::assembly::aarch64::OPCODE::DECP_XP_B) + .value("DECP_XP_D", LIEF::assembly::aarch64::OPCODE::DECP_XP_D) + .value("DECP_XP_H", LIEF::assembly::aarch64::OPCODE::DECP_XP_H) + .value("DECP_XP_S", LIEF::assembly::aarch64::OPCODE::DECP_XP_S) + .value("DECP_ZP_D", LIEF::assembly::aarch64::OPCODE::DECP_ZP_D) + .value("DECP_ZP_H", LIEF::assembly::aarch64::OPCODE::DECP_ZP_H) + .value("DECP_ZP_S", LIEF::assembly::aarch64::OPCODE::DECP_ZP_S) + .value("DECW_XPiI", LIEF::assembly::aarch64::OPCODE::DECW_XPiI) + .value("DECW_ZPiI", LIEF::assembly::aarch64::OPCODE::DECW_ZPiI) + .value("DMB", LIEF::assembly::aarch64::OPCODE::DMB) + .value("DRPS", LIEF::assembly::aarch64::OPCODE::DRPS) + .value("DSB", LIEF::assembly::aarch64::OPCODE::DSB) + .value("DSBnXS", LIEF::assembly::aarch64::OPCODE::DSBnXS) + .value("DUPM_ZI", LIEF::assembly::aarch64::OPCODE::DUPM_ZI) + .value("DUPQ_ZZI_B", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_B) + .value("DUPQ_ZZI_D", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_D) + .value("DUPQ_ZZI_H", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_H) + .value("DUPQ_ZZI_S", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_S) + .value("DUP_ZI_B", LIEF::assembly::aarch64::OPCODE::DUP_ZI_B) + .value("DUP_ZI_D", LIEF::assembly::aarch64::OPCODE::DUP_ZI_D) + .value("DUP_ZI_H", LIEF::assembly::aarch64::OPCODE::DUP_ZI_H) + .value("DUP_ZI_S", LIEF::assembly::aarch64::OPCODE::DUP_ZI_S) + .value("DUP_ZR_B", LIEF::assembly::aarch64::OPCODE::DUP_ZR_B) + .value("DUP_ZR_D", LIEF::assembly::aarch64::OPCODE::DUP_ZR_D) + .value("DUP_ZR_H", LIEF::assembly::aarch64::OPCODE::DUP_ZR_H) + .value("DUP_ZR_S", LIEF::assembly::aarch64::OPCODE::DUP_ZR_S) + .value("DUP_ZZI_B", LIEF::assembly::aarch64::OPCODE::DUP_ZZI_B) + .value("DUP_ZZI_D", LIEF::assembly::aarch64::OPCODE::DUP_ZZI_D) + .value("DUP_ZZI_H", LIEF::assembly::aarch64::OPCODE::DUP_ZZI_H) + .value("DUP_ZZI_Q", LIEF::assembly::aarch64::OPCODE::DUP_ZZI_Q) + .value("DUP_ZZI_S", LIEF::assembly::aarch64::OPCODE::DUP_ZZI_S) + .value("DUPi16", LIEF::assembly::aarch64::OPCODE::DUPi16) + .value("DUPi32", LIEF::assembly::aarch64::OPCODE::DUPi32) + .value("DUPi64", LIEF::assembly::aarch64::OPCODE::DUPi64) + .value("DUPi8", LIEF::assembly::aarch64::OPCODE::DUPi8) + .value("DUPv16i8gpr", LIEF::assembly::aarch64::OPCODE::DUPv16i8gpr) + .value("DUPv16i8lane", LIEF::assembly::aarch64::OPCODE::DUPv16i8lane) + .value("DUPv2i32gpr", LIEF::assembly::aarch64::OPCODE::DUPv2i32gpr) + .value("DUPv2i32lane", LIEF::assembly::aarch64::OPCODE::DUPv2i32lane) + .value("DUPv2i64gpr", LIEF::assembly::aarch64::OPCODE::DUPv2i64gpr) + .value("DUPv2i64lane", LIEF::assembly::aarch64::OPCODE::DUPv2i64lane) + .value("DUPv4i16gpr", LIEF::assembly::aarch64::OPCODE::DUPv4i16gpr) + .value("DUPv4i16lane", LIEF::assembly::aarch64::OPCODE::DUPv4i16lane) + .value("DUPv4i32gpr", LIEF::assembly::aarch64::OPCODE::DUPv4i32gpr) + .value("DUPv4i32lane", LIEF::assembly::aarch64::OPCODE::DUPv4i32lane) + .value("DUPv8i16gpr", LIEF::assembly::aarch64::OPCODE::DUPv8i16gpr) + .value("DUPv8i16lane", LIEF::assembly::aarch64::OPCODE::DUPv8i16lane) + .value("DUPv8i8gpr", LIEF::assembly::aarch64::OPCODE::DUPv8i8gpr) + .value("DUPv8i8lane", LIEF::assembly::aarch64::OPCODE::DUPv8i8lane) + .value("EONWrs", LIEF::assembly::aarch64::OPCODE::EONWrs) + .value("EONXrs", LIEF::assembly::aarch64::OPCODE::EONXrs) + .value("EOR3", LIEF::assembly::aarch64::OPCODE::EOR3) + .value("EOR3_ZZZZ", LIEF::assembly::aarch64::OPCODE::EOR3_ZZZZ) + .value("EORBT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::EORBT_ZZZ_B) + .value("EORBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::EORBT_ZZZ_D) + .value("EORBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::EORBT_ZZZ_H) + .value("EORBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::EORBT_ZZZ_S) + .value("EORQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::EORQV_VPZ_B) + .value("EORQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::EORQV_VPZ_D) + .value("EORQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::EORQV_VPZ_H) + .value("EORQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::EORQV_VPZ_S) + .value("EORS_PPzPP", LIEF::assembly::aarch64::OPCODE::EORS_PPzPP) + .value("EORTB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::EORTB_ZZZ_B) + .value("EORTB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::EORTB_ZZZ_D) + .value("EORTB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::EORTB_ZZZ_H) + .value("EORTB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::EORTB_ZZZ_S) + .value("EORV_VPZ_B", LIEF::assembly::aarch64::OPCODE::EORV_VPZ_B) + .value("EORV_VPZ_D", LIEF::assembly::aarch64::OPCODE::EORV_VPZ_D) + .value("EORV_VPZ_H", LIEF::assembly::aarch64::OPCODE::EORV_VPZ_H) + .value("EORV_VPZ_S", LIEF::assembly::aarch64::OPCODE::EORV_VPZ_S) + .value("EORWri", LIEF::assembly::aarch64::OPCODE::EORWri) + .value("EORWrs", LIEF::assembly::aarch64::OPCODE::EORWrs) + .value("EORXri", LIEF::assembly::aarch64::OPCODE::EORXri) + .value("EORXrs", LIEF::assembly::aarch64::OPCODE::EORXrs) + .value("EOR_PPzPP", LIEF::assembly::aarch64::OPCODE::EOR_PPzPP) + .value("EOR_ZI", LIEF::assembly::aarch64::OPCODE::EOR_ZI) + .value("EOR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_B) + .value("EOR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_D) + .value("EOR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_H); + opcodes.value("EOR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_S) + .value("EOR_ZZZ", LIEF::assembly::aarch64::OPCODE::EOR_ZZZ) + .value("EORv16i8", LIEF::assembly::aarch64::OPCODE::EORv16i8) + .value("EORv8i8", LIEF::assembly::aarch64::OPCODE::EORv8i8) + .value("ERET", LIEF::assembly::aarch64::OPCODE::ERET) + .value("ERETAA", LIEF::assembly::aarch64::OPCODE::ERETAA) + .value("ERETAB", LIEF::assembly::aarch64::OPCODE::ERETAB) + .value("EXPAND_ZPZ_B", LIEF::assembly::aarch64::OPCODE::EXPAND_ZPZ_B) + .value("EXPAND_ZPZ_D", LIEF::assembly::aarch64::OPCODE::EXPAND_ZPZ_D) + .value("EXPAND_ZPZ_H", LIEF::assembly::aarch64::OPCODE::EXPAND_ZPZ_H) + .value("EXPAND_ZPZ_S", LIEF::assembly::aarch64::OPCODE::EXPAND_ZPZ_S) + .value("EXTQ_ZZI", LIEF::assembly::aarch64::OPCODE::EXTQ_ZZI) + .value("EXTRACT_ZPMXI_H_B", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_H_B) + .value("EXTRACT_ZPMXI_H_D", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_H_D) + .value("EXTRACT_ZPMXI_H_H", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_H_H) + .value("EXTRACT_ZPMXI_H_Q", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_H_Q) + .value("EXTRACT_ZPMXI_H_S", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_H_S) + .value("EXTRACT_ZPMXI_V_B", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_V_B) + .value("EXTRACT_ZPMXI_V_D", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_V_D) + .value("EXTRACT_ZPMXI_V_H", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_V_H) + .value("EXTRACT_ZPMXI_V_Q", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_V_Q) + .value("EXTRACT_ZPMXI_V_S", LIEF::assembly::aarch64::OPCODE::EXTRACT_ZPMXI_V_S) + .value("EXTRWrri", LIEF::assembly::aarch64::OPCODE::EXTRWrri) + .value("EXTRXrri", LIEF::assembly::aarch64::OPCODE::EXTRXrri) + .value("EXT_ZZI", LIEF::assembly::aarch64::OPCODE::EXT_ZZI) + .value("EXT_ZZI_B", LIEF::assembly::aarch64::OPCODE::EXT_ZZI_B) + .value("EXTv16i8", LIEF::assembly::aarch64::OPCODE::EXTv16i8) + .value("EXTv8i8", LIEF::assembly::aarch64::OPCODE::EXTv8i8) + .value("F1CVTL", LIEF::assembly::aarch64::OPCODE::F1CVTL) + .value("F1CVTL2", LIEF::assembly::aarch64::OPCODE::F1CVTL2) + .value("F1CVTLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F1CVTLT_ZZ_BtoH) + .value("F1CVTL_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F1CVTL_2ZZ_BtoH) + .value("F1CVT_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F1CVT_2ZZ_BtoH) + .value("F1CVT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F1CVT_ZZ_BtoH) + .value("F2CVTL", LIEF::assembly::aarch64::OPCODE::F2CVTL) + .value("F2CVTL2", LIEF::assembly::aarch64::OPCODE::F2CVTL2) + .value("F2CVTLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F2CVTLT_ZZ_BtoH) + .value("F2CVTL_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F2CVTL_2ZZ_BtoH) + .value("F2CVT_2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F2CVT_2ZZ_BtoH) + .value("F2CVT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::F2CVT_ZZ_BtoH) + .value("FABD16", LIEF::assembly::aarch64::OPCODE::FABD16) + .value("FABD32", LIEF::assembly::aarch64::OPCODE::FABD32) + .value("FABD64", LIEF::assembly::aarch64::OPCODE::FABD64) + .value("FABD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FABD_ZPmZ_D) + .value("FABD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FABD_ZPmZ_H) + .value("FABD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FABD_ZPmZ_S) + .value("FABDv2f32", LIEF::assembly::aarch64::OPCODE::FABDv2f32) + .value("FABDv2f64", LIEF::assembly::aarch64::OPCODE::FABDv2f64) + .value("FABDv4f16", LIEF::assembly::aarch64::OPCODE::FABDv4f16) + .value("FABDv4f32", LIEF::assembly::aarch64::OPCODE::FABDv4f32) + .value("FABDv8f16", LIEF::assembly::aarch64::OPCODE::FABDv8f16) + .value("FABSDr", LIEF::assembly::aarch64::OPCODE::FABSDr) + .value("FABSHr", LIEF::assembly::aarch64::OPCODE::FABSHr) + .value("FABSSr", LIEF::assembly::aarch64::OPCODE::FABSSr) + .value("FABS_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_D) + .value("FABS_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_H) + .value("FABS_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FABS_ZPmZ_S) + .value("FABS_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FABS_ZPzZ_D) + .value("FABS_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FABS_ZPzZ_H) + .value("FABS_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FABS_ZPzZ_S) + .value("FABSv2f32", LIEF::assembly::aarch64::OPCODE::FABSv2f32) + .value("FABSv2f64", LIEF::assembly::aarch64::OPCODE::FABSv2f64) + .value("FABSv4f16", LIEF::assembly::aarch64::OPCODE::FABSv4f16) + .value("FABSv4f32", LIEF::assembly::aarch64::OPCODE::FABSv4f32) + .value("FABSv8f16", LIEF::assembly::aarch64::OPCODE::FABSv8f16) + .value("FACGE16", LIEF::assembly::aarch64::OPCODE::FACGE16) + .value("FACGE32", LIEF::assembly::aarch64::OPCODE::FACGE32) + .value("FACGE64", LIEF::assembly::aarch64::OPCODE::FACGE64) + .value("FACGE_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FACGE_PPzZZ_D) + .value("FACGE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FACGE_PPzZZ_H) + .value("FACGE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FACGE_PPzZZ_S) + .value("FACGEv2f32", LIEF::assembly::aarch64::OPCODE::FACGEv2f32) + .value("FACGEv2f64", LIEF::assembly::aarch64::OPCODE::FACGEv2f64) + .value("FACGEv4f16", LIEF::assembly::aarch64::OPCODE::FACGEv4f16) + .value("FACGEv4f32", LIEF::assembly::aarch64::OPCODE::FACGEv4f32) + .value("FACGEv8f16", LIEF::assembly::aarch64::OPCODE::FACGEv8f16) + .value("FACGT16", LIEF::assembly::aarch64::OPCODE::FACGT16) + .value("FACGT32", LIEF::assembly::aarch64::OPCODE::FACGT32) + .value("FACGT64", LIEF::assembly::aarch64::OPCODE::FACGT64) + .value("FACGT_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FACGT_PPzZZ_D) + .value("FACGT_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FACGT_PPzZZ_H) + .value("FACGT_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FACGT_PPzZZ_S) + .value("FACGTv2f32", LIEF::assembly::aarch64::OPCODE::FACGTv2f32) + .value("FACGTv2f64", LIEF::assembly::aarch64::OPCODE::FACGTv2f64) + .value("FACGTv4f16", LIEF::assembly::aarch64::OPCODE::FACGTv4f16) + .value("FACGTv4f32", LIEF::assembly::aarch64::OPCODE::FACGTv4f32) + .value("FACGTv8f16", LIEF::assembly::aarch64::OPCODE::FACGTv8f16) + .value("FADDA_VPZ_D", LIEF::assembly::aarch64::OPCODE::FADDA_VPZ_D) + .value("FADDA_VPZ_H", LIEF::assembly::aarch64::OPCODE::FADDA_VPZ_H) + .value("FADDA_VPZ_S", LIEF::assembly::aarch64::OPCODE::FADDA_VPZ_S) + .value("FADDDrr", LIEF::assembly::aarch64::OPCODE::FADDDrr) + .value("FADDHrr", LIEF::assembly::aarch64::OPCODE::FADDHrr) + .value("FADDP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FADDP_ZPmZZ_D) + .value("FADDP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FADDP_ZPmZZ_H) + .value("FADDP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FADDP_ZPmZZ_S) + .value("FADDPv2f32", LIEF::assembly::aarch64::OPCODE::FADDPv2f32) + .value("FADDPv2f64", LIEF::assembly::aarch64::OPCODE::FADDPv2f64) + .value("FADDPv2i16p", LIEF::assembly::aarch64::OPCODE::FADDPv2i16p) + .value("FADDPv2i32p", LIEF::assembly::aarch64::OPCODE::FADDPv2i32p) + .value("FADDPv2i64p", LIEF::assembly::aarch64::OPCODE::FADDPv2i64p) + .value("FADDPv4f16", LIEF::assembly::aarch64::OPCODE::FADDPv4f16) + .value("FADDPv4f32", LIEF::assembly::aarch64::OPCODE::FADDPv4f32) + .value("FADDPv8f16", LIEF::assembly::aarch64::OPCODE::FADDPv8f16) + .value("FADDQV_D", LIEF::assembly::aarch64::OPCODE::FADDQV_D) + .value("FADDQV_H", LIEF::assembly::aarch64::OPCODE::FADDQV_H) + .value("FADDQV_S", LIEF::assembly::aarch64::OPCODE::FADDQV_S) + .value("FADDSrr", LIEF::assembly::aarch64::OPCODE::FADDSrr) + .value("FADDV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FADDV_VPZ_D) + .value("FADDV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FADDV_VPZ_H) + .value("FADDV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FADDV_VPZ_S) + .value("FADD_VG2_M2Z_D", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_D) + .value("FADD_VG2_M2Z_H", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_H) + .value("FADD_VG2_M2Z_S", LIEF::assembly::aarch64::OPCODE::FADD_VG2_M2Z_S) + .value("FADD_VG4_M4Z_D", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_D) + .value("FADD_VG4_M4Z_H", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_H) + .value("FADD_VG4_M4Z_S", LIEF::assembly::aarch64::OPCODE::FADD_VG4_M4Z_S) + .value("FADD_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FADD_ZPmI_D) + .value("FADD_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FADD_ZPmI_H) + .value("FADD_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FADD_ZPmI_S) + .value("FADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FADD_ZPmZ_D) + .value("FADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FADD_ZPmZ_H) + .value("FADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FADD_ZPmZ_S) + .value("FADD_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FADD_ZZZ_D) + .value("FADD_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FADD_ZZZ_H) + .value("FADD_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FADD_ZZZ_S) + .value("FADDv2f32", LIEF::assembly::aarch64::OPCODE::FADDv2f32) + .value("FADDv2f64", LIEF::assembly::aarch64::OPCODE::FADDv2f64) + .value("FADDv4f16", LIEF::assembly::aarch64::OPCODE::FADDv4f16) + .value("FADDv4f32", LIEF::assembly::aarch64::OPCODE::FADDv4f32) + .value("FADDv8f16", LIEF::assembly::aarch64::OPCODE::FADDv8f16) + .value("FAMAX_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FAMAX_2Z2Z_D) + .value("FAMAX_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FAMAX_2Z2Z_H) + .value("FAMAX_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FAMAX_2Z2Z_S) + .value("FAMAX_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FAMAX_4Z4Z_D) + .value("FAMAX_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FAMAX_4Z4Z_H) + .value("FAMAX_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FAMAX_4Z4Z_S) + .value("FAMAX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPmZ_D) + .value("FAMAX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPmZ_H) + .value("FAMAX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FAMAX_ZPmZ_S) + .value("FAMAXv2f32", LIEF::assembly::aarch64::OPCODE::FAMAXv2f32) + .value("FAMAXv2f64", LIEF::assembly::aarch64::OPCODE::FAMAXv2f64) + .value("FAMAXv4f16", LIEF::assembly::aarch64::OPCODE::FAMAXv4f16) + .value("FAMAXv4f32", LIEF::assembly::aarch64::OPCODE::FAMAXv4f32) + .value("FAMAXv8f16", LIEF::assembly::aarch64::OPCODE::FAMAXv8f16) + .value("FAMIN_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FAMIN_2Z2Z_D) + .value("FAMIN_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FAMIN_2Z2Z_H) + .value("FAMIN_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FAMIN_2Z2Z_S) + .value("FAMIN_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FAMIN_4Z4Z_D) + .value("FAMIN_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FAMIN_4Z4Z_H) + .value("FAMIN_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FAMIN_4Z4Z_S) + .value("FAMIN_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPmZ_D) + .value("FAMIN_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPmZ_H) + .value("FAMIN_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FAMIN_ZPmZ_S) + .value("FAMINv2f32", LIEF::assembly::aarch64::OPCODE::FAMINv2f32) + .value("FAMINv2f64", LIEF::assembly::aarch64::OPCODE::FAMINv2f64) + .value("FAMINv4f16", LIEF::assembly::aarch64::OPCODE::FAMINv4f16) + .value("FAMINv4f32", LIEF::assembly::aarch64::OPCODE::FAMINv4f32) + .value("FAMINv8f16", LIEF::assembly::aarch64::OPCODE::FAMINv8f16) + .value("FCADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FCADD_ZPmZ_D) + .value("FCADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FCADD_ZPmZ_H) + .value("FCADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FCADD_ZPmZ_S) + .value("FCADDv2f32", LIEF::assembly::aarch64::OPCODE::FCADDv2f32) + .value("FCADDv2f64", LIEF::assembly::aarch64::OPCODE::FCADDv2f64) + .value("FCADDv4f16", LIEF::assembly::aarch64::OPCODE::FCADDv4f16) + .value("FCADDv4f32", LIEF::assembly::aarch64::OPCODE::FCADDv4f32) + .value("FCADDv8f16", LIEF::assembly::aarch64::OPCODE::FCADDv8f16) + .value("FCCMPDrr", LIEF::assembly::aarch64::OPCODE::FCCMPDrr) + .value("FCCMPEDrr", LIEF::assembly::aarch64::OPCODE::FCCMPEDrr) + .value("FCCMPEHrr", LIEF::assembly::aarch64::OPCODE::FCCMPEHrr) + .value("FCCMPESrr", LIEF::assembly::aarch64::OPCODE::FCCMPESrr) + .value("FCCMPHrr", LIEF::assembly::aarch64::OPCODE::FCCMPHrr) + .value("FCCMPSrr", LIEF::assembly::aarch64::OPCODE::FCCMPSrr) + .value("FCLAMP_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG2_2Z2Z_D) + .value("FCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG2_2Z2Z_H) + .value("FCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG2_2Z2Z_S) + .value("FCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG4_4Z4Z_D) + .value("FCLAMP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG4_4Z4Z_H) + .value("FCLAMP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FCLAMP_VG4_4Z4Z_S) + .value("FCLAMP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FCLAMP_ZZZ_D) + .value("FCLAMP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FCLAMP_ZZZ_H) + .value("FCLAMP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FCLAMP_ZZZ_S) + .value("FCMEQ16", LIEF::assembly::aarch64::OPCODE::FCMEQ16) + .value("FCMEQ32", LIEF::assembly::aarch64::OPCODE::FCMEQ32) + .value("FCMEQ64", LIEF::assembly::aarch64::OPCODE::FCMEQ64) + .value("FCMEQ_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZ0_D) + .value("FCMEQ_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZ0_H) + .value("FCMEQ_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZ0_S) + .value("FCMEQ_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZZ_D) + .value("FCMEQ_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZZ_H) + .value("FCMEQ_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMEQ_PPzZZ_S) + .value("FCMEQv1i16rz", LIEF::assembly::aarch64::OPCODE::FCMEQv1i16rz) + .value("FCMEQv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMEQv1i32rz) + .value("FCMEQv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMEQv1i64rz) + .value("FCMEQv2f32", LIEF::assembly::aarch64::OPCODE::FCMEQv2f32) + .value("FCMEQv2f64", LIEF::assembly::aarch64::OPCODE::FCMEQv2f64) + .value("FCMEQv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMEQv2i32rz) + .value("FCMEQv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMEQv2i64rz) + .value("FCMEQv4f16", LIEF::assembly::aarch64::OPCODE::FCMEQv4f16) + .value("FCMEQv4f32", LIEF::assembly::aarch64::OPCODE::FCMEQv4f32) + .value("FCMEQv4i16rz", LIEF::assembly::aarch64::OPCODE::FCMEQv4i16rz) + .value("FCMEQv4i32rz", LIEF::assembly::aarch64::OPCODE::FCMEQv4i32rz) + .value("FCMEQv8f16", LIEF::assembly::aarch64::OPCODE::FCMEQv8f16) + .value("FCMEQv8i16rz", LIEF::assembly::aarch64::OPCODE::FCMEQv8i16rz) + .value("FCMGE16", LIEF::assembly::aarch64::OPCODE::FCMGE16) + .value("FCMGE32", LIEF::assembly::aarch64::OPCODE::FCMGE32) + .value("FCMGE64", LIEF::assembly::aarch64::OPCODE::FCMGE64) + .value("FCMGE_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZ0_D) + .value("FCMGE_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZ0_H) + .value("FCMGE_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZ0_S) + .value("FCMGE_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZZ_D) + .value("FCMGE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZZ_H) + .value("FCMGE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMGE_PPzZZ_S) + .value("FCMGEv1i16rz", LIEF::assembly::aarch64::OPCODE::FCMGEv1i16rz) + .value("FCMGEv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMGEv1i32rz) + .value("FCMGEv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMGEv1i64rz) + .value("FCMGEv2f32", LIEF::assembly::aarch64::OPCODE::FCMGEv2f32) + .value("FCMGEv2f64", LIEF::assembly::aarch64::OPCODE::FCMGEv2f64) + .value("FCMGEv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMGEv2i32rz) + .value("FCMGEv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMGEv2i64rz) + .value("FCMGEv4f16", LIEF::assembly::aarch64::OPCODE::FCMGEv4f16) + .value("FCMGEv4f32", LIEF::assembly::aarch64::OPCODE::FCMGEv4f32) + .value("FCMGEv4i16rz", LIEF::assembly::aarch64::OPCODE::FCMGEv4i16rz) + .value("FCMGEv4i32rz", LIEF::assembly::aarch64::OPCODE::FCMGEv4i32rz) + .value("FCMGEv8f16", LIEF::assembly::aarch64::OPCODE::FCMGEv8f16) + .value("FCMGEv8i16rz", LIEF::assembly::aarch64::OPCODE::FCMGEv8i16rz) + .value("FCMGT16", LIEF::assembly::aarch64::OPCODE::FCMGT16) + .value("FCMGT32", LIEF::assembly::aarch64::OPCODE::FCMGT32) + .value("FCMGT64", LIEF::assembly::aarch64::OPCODE::FCMGT64) + .value("FCMGT_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZ0_D) + .value("FCMGT_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZ0_H) + .value("FCMGT_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZ0_S) + .value("FCMGT_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZZ_D) + .value("FCMGT_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZZ_H) + .value("FCMGT_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMGT_PPzZZ_S) + .value("FCMGTv1i16rz", LIEF::assembly::aarch64::OPCODE::FCMGTv1i16rz) + .value("FCMGTv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv1i32rz) + .value("FCMGTv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMGTv1i64rz) + .value("FCMGTv2f32", LIEF::assembly::aarch64::OPCODE::FCMGTv2f32) + .value("FCMGTv2f64", LIEF::assembly::aarch64::OPCODE::FCMGTv2f64) + .value("FCMGTv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv2i32rz) + .value("FCMGTv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMGTv2i64rz) + .value("FCMGTv4f16", LIEF::assembly::aarch64::OPCODE::FCMGTv4f16) + .value("FCMGTv4f32", LIEF::assembly::aarch64::OPCODE::FCMGTv4f32) + .value("FCMGTv4i16rz", LIEF::assembly::aarch64::OPCODE::FCMGTv4i16rz) + .value("FCMGTv4i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv4i32rz) + .value("FCMGTv8f16", LIEF::assembly::aarch64::OPCODE::FCMGTv8f16) + .value("FCMGTv8i16rz", LIEF::assembly::aarch64::OPCODE::FCMGTv8i16rz) + .value("FCMLA_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FCMLA_ZPmZZ_D) + .value("FCMLA_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FCMLA_ZPmZZ_H) + .value("FCMLA_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FCMLA_ZPmZZ_S) + .value("FCMLA_ZZZI_H", LIEF::assembly::aarch64::OPCODE::FCMLA_ZZZI_H) + .value("FCMLA_ZZZI_S", LIEF::assembly::aarch64::OPCODE::FCMLA_ZZZI_S) + .value("FCMLAv2f32", LIEF::assembly::aarch64::OPCODE::FCMLAv2f32) + .value("FCMLAv2f64", LIEF::assembly::aarch64::OPCODE::FCMLAv2f64) + .value("FCMLAv4f16", LIEF::assembly::aarch64::OPCODE::FCMLAv4f16) + .value("FCMLAv4f16_indexed", LIEF::assembly::aarch64::OPCODE::FCMLAv4f16_indexed) + .value("FCMLAv4f32", LIEF::assembly::aarch64::OPCODE::FCMLAv4f32) + .value("FCMLAv4f32_indexed", LIEF::assembly::aarch64::OPCODE::FCMLAv4f32_indexed) + .value("FCMLAv8f16", LIEF::assembly::aarch64::OPCODE::FCMLAv8f16) + .value("FCMLAv8f16_indexed", LIEF::assembly::aarch64::OPCODE::FCMLAv8f16_indexed) + .value("FCMLE_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMLE_PPzZ0_D) + .value("FCMLE_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMLE_PPzZ0_H) + .value("FCMLE_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMLE_PPzZ0_S) + .value("FCMLEv1i16rz", LIEF::assembly::aarch64::OPCODE::FCMLEv1i16rz) + .value("FCMLEv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMLEv1i32rz) + .value("FCMLEv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMLEv1i64rz) + .value("FCMLEv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMLEv2i32rz) + .value("FCMLEv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMLEv2i64rz) + .value("FCMLEv4i16rz", LIEF::assembly::aarch64::OPCODE::FCMLEv4i16rz) + .value("FCMLEv4i32rz", LIEF::assembly::aarch64::OPCODE::FCMLEv4i32rz) + .value("FCMLEv8i16rz", LIEF::assembly::aarch64::OPCODE::FCMLEv8i16rz) + .value("FCMLT_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMLT_PPzZ0_D) + .value("FCMLT_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMLT_PPzZ0_H) + .value("FCMLT_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMLT_PPzZ0_S) + .value("FCMLTv1i16rz", LIEF::assembly::aarch64::OPCODE::FCMLTv1i16rz) + .value("FCMLTv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMLTv1i32rz) + .value("FCMLTv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMLTv1i64rz) + .value("FCMLTv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMLTv2i32rz) + .value("FCMLTv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMLTv2i64rz) + .value("FCMLTv4i16rz", LIEF::assembly::aarch64::OPCODE::FCMLTv4i16rz) + .value("FCMLTv4i32rz", LIEF::assembly::aarch64::OPCODE::FCMLTv4i32rz) + .value("FCMLTv8i16rz", LIEF::assembly::aarch64::OPCODE::FCMLTv8i16rz) + .value("FCMNE_PPzZ0_D", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZ0_D) + .value("FCMNE_PPzZ0_H", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZ0_H) + .value("FCMNE_PPzZ0_S", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZ0_S) + .value("FCMNE_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZZ_D) + .value("FCMNE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZZ_H) + .value("FCMNE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMNE_PPzZZ_S) + .value("FCMPDri", LIEF::assembly::aarch64::OPCODE::FCMPDri) + .value("FCMPDrr", LIEF::assembly::aarch64::OPCODE::FCMPDrr) + .value("FCMPEDri", LIEF::assembly::aarch64::OPCODE::FCMPEDri) + .value("FCMPEDrr", LIEF::assembly::aarch64::OPCODE::FCMPEDrr) + .value("FCMPEHri", LIEF::assembly::aarch64::OPCODE::FCMPEHri) + .value("FCMPEHrr", LIEF::assembly::aarch64::OPCODE::FCMPEHrr) + .value("FCMPESri", LIEF::assembly::aarch64::OPCODE::FCMPESri) + .value("FCMPESrr", LIEF::assembly::aarch64::OPCODE::FCMPESrr) + .value("FCMPHri", LIEF::assembly::aarch64::OPCODE::FCMPHri) + .value("FCMPHrr", LIEF::assembly::aarch64::OPCODE::FCMPHrr) + .value("FCMPSri", LIEF::assembly::aarch64::OPCODE::FCMPSri) + .value("FCMPSrr", LIEF::assembly::aarch64::OPCODE::FCMPSrr); + opcodes.value("FCMUO_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_D) + .value("FCMUO_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_H) + .value("FCMUO_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_S) + .value("FCPY_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FCPY_ZPmI_D) + .value("FCPY_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FCPY_ZPmI_H) + .value("FCPY_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FCPY_ZPmI_S) + .value("FCSELDrrr", LIEF::assembly::aarch64::OPCODE::FCSELDrrr) + .value("FCSELHrrr", LIEF::assembly::aarch64::OPCODE::FCSELHrrr) + .value("FCSELSrrr", LIEF::assembly::aarch64::OPCODE::FCSELSrrr) + .value("FCVTASDHr", LIEF::assembly::aarch64::OPCODE::FCVTASDHr) + .value("FCVTASDSr", LIEF::assembly::aarch64::OPCODE::FCVTASDSr) + .value("FCVTASSDr", LIEF::assembly::aarch64::OPCODE::FCVTASSDr) + .value("FCVTASSHr", LIEF::assembly::aarch64::OPCODE::FCVTASSHr) + .value("FCVTASUWDr", LIEF::assembly::aarch64::OPCODE::FCVTASUWDr) + .value("FCVTASUWHr", LIEF::assembly::aarch64::OPCODE::FCVTASUWHr) + .value("FCVTASUWSr", LIEF::assembly::aarch64::OPCODE::FCVTASUWSr) + .value("FCVTASUXDr", LIEF::assembly::aarch64::OPCODE::FCVTASUXDr) + .value("FCVTASUXHr", LIEF::assembly::aarch64::OPCODE::FCVTASUXHr) + .value("FCVTASUXSr", LIEF::assembly::aarch64::OPCODE::FCVTASUXSr) + .value("FCVTASv1f16", LIEF::assembly::aarch64::OPCODE::FCVTASv1f16) + .value("FCVTASv1i32", LIEF::assembly::aarch64::OPCODE::FCVTASv1i32) + .value("FCVTASv1i64", LIEF::assembly::aarch64::OPCODE::FCVTASv1i64) + .value("FCVTASv2f32", LIEF::assembly::aarch64::OPCODE::FCVTASv2f32) + .value("FCVTASv2f64", LIEF::assembly::aarch64::OPCODE::FCVTASv2f64) + .value("FCVTASv4f16", LIEF::assembly::aarch64::OPCODE::FCVTASv4f16) + .value("FCVTASv4f32", LIEF::assembly::aarch64::OPCODE::FCVTASv4f32) + .value("FCVTASv8f16", LIEF::assembly::aarch64::OPCODE::FCVTASv8f16) + .value("FCVTAUDHr", LIEF::assembly::aarch64::OPCODE::FCVTAUDHr) + .value("FCVTAUDSr", LIEF::assembly::aarch64::OPCODE::FCVTAUDSr) + .value("FCVTAUSDr", LIEF::assembly::aarch64::OPCODE::FCVTAUSDr) + .value("FCVTAUSHr", LIEF::assembly::aarch64::OPCODE::FCVTAUSHr) + .value("FCVTAUUWDr", LIEF::assembly::aarch64::OPCODE::FCVTAUUWDr) + .value("FCVTAUUWHr", LIEF::assembly::aarch64::OPCODE::FCVTAUUWHr) + .value("FCVTAUUWSr", LIEF::assembly::aarch64::OPCODE::FCVTAUUWSr) + .value("FCVTAUUXDr", LIEF::assembly::aarch64::OPCODE::FCVTAUUXDr) + .value("FCVTAUUXHr", LIEF::assembly::aarch64::OPCODE::FCVTAUUXHr) + .value("FCVTAUUXSr", LIEF::assembly::aarch64::OPCODE::FCVTAUUXSr) + .value("FCVTAUv1f16", LIEF::assembly::aarch64::OPCODE::FCVTAUv1f16) + .value("FCVTAUv1i32", LIEF::assembly::aarch64::OPCODE::FCVTAUv1i32) + .value("FCVTAUv1i64", LIEF::assembly::aarch64::OPCODE::FCVTAUv1i64) + .value("FCVTAUv2f32", LIEF::assembly::aarch64::OPCODE::FCVTAUv2f32) + .value("FCVTAUv2f64", LIEF::assembly::aarch64::OPCODE::FCVTAUv2f64) + .value("FCVTAUv4f16", LIEF::assembly::aarch64::OPCODE::FCVTAUv4f16) + .value("FCVTAUv4f32", LIEF::assembly::aarch64::OPCODE::FCVTAUv4f32) + .value("FCVTAUv8f16", LIEF::assembly::aarch64::OPCODE::FCVTAUv8f16) + .value("FCVTDHr", LIEF::assembly::aarch64::OPCODE::FCVTDHr) + .value("FCVTDSr", LIEF::assembly::aarch64::OPCODE::FCVTDSr) + .value("FCVTHDr", LIEF::assembly::aarch64::OPCODE::FCVTHDr) + .value("FCVTHSr", LIEF::assembly::aarch64::OPCODE::FCVTHSr) + .value("FCVTLT_ZPmZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTLT_ZPmZ_HtoS) + .value("FCVTLT_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTLT_ZPmZ_StoD) + .value("FCVTLT_ZPzZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTLT_ZPzZ_HtoS) + .value("FCVTLT_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTLT_ZPzZ_StoD) + .value("FCVTL_2ZZ_H_S", LIEF::assembly::aarch64::OPCODE::FCVTL_2ZZ_H_S) + .value("FCVTLv2i32", LIEF::assembly::aarch64::OPCODE::FCVTLv2i32) + .value("FCVTLv4i16", LIEF::assembly::aarch64::OPCODE::FCVTLv4i16) + .value("FCVTLv4i32", LIEF::assembly::aarch64::OPCODE::FCVTLv4i32) + .value("FCVTLv8i16", LIEF::assembly::aarch64::OPCODE::FCVTLv8i16) + .value("FCVTMSDHr", LIEF::assembly::aarch64::OPCODE::FCVTMSDHr) + .value("FCVTMSDSr", LIEF::assembly::aarch64::OPCODE::FCVTMSDSr) + .value("FCVTMSSDr", LIEF::assembly::aarch64::OPCODE::FCVTMSSDr) + .value("FCVTMSSHr", LIEF::assembly::aarch64::OPCODE::FCVTMSSHr) + .value("FCVTMSUWDr", LIEF::assembly::aarch64::OPCODE::FCVTMSUWDr) + .value("FCVTMSUWHr", LIEF::assembly::aarch64::OPCODE::FCVTMSUWHr) + .value("FCVTMSUWSr", LIEF::assembly::aarch64::OPCODE::FCVTMSUWSr) + .value("FCVTMSUXDr", LIEF::assembly::aarch64::OPCODE::FCVTMSUXDr) + .value("FCVTMSUXHr", LIEF::assembly::aarch64::OPCODE::FCVTMSUXHr) + .value("FCVTMSUXSr", LIEF::assembly::aarch64::OPCODE::FCVTMSUXSr) + .value("FCVTMSv1f16", LIEF::assembly::aarch64::OPCODE::FCVTMSv1f16) + .value("FCVTMSv1i32", LIEF::assembly::aarch64::OPCODE::FCVTMSv1i32) + .value("FCVTMSv1i64", LIEF::assembly::aarch64::OPCODE::FCVTMSv1i64) + .value("FCVTMSv2f32", LIEF::assembly::aarch64::OPCODE::FCVTMSv2f32) + .value("FCVTMSv2f64", LIEF::assembly::aarch64::OPCODE::FCVTMSv2f64) + .value("FCVTMSv4f16", LIEF::assembly::aarch64::OPCODE::FCVTMSv4f16) + .value("FCVTMSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTMSv4f32) + .value("FCVTMSv8f16", LIEF::assembly::aarch64::OPCODE::FCVTMSv8f16) + .value("FCVTMUDHr", LIEF::assembly::aarch64::OPCODE::FCVTMUDHr) + .value("FCVTMUDSr", LIEF::assembly::aarch64::OPCODE::FCVTMUDSr) + .value("FCVTMUSDr", LIEF::assembly::aarch64::OPCODE::FCVTMUSDr) + .value("FCVTMUSHr", LIEF::assembly::aarch64::OPCODE::FCVTMUSHr) + .value("FCVTMUUWDr", LIEF::assembly::aarch64::OPCODE::FCVTMUUWDr) + .value("FCVTMUUWHr", LIEF::assembly::aarch64::OPCODE::FCVTMUUWHr) + .value("FCVTMUUWSr", LIEF::assembly::aarch64::OPCODE::FCVTMUUWSr) + .value("FCVTMUUXDr", LIEF::assembly::aarch64::OPCODE::FCVTMUUXDr) + .value("FCVTMUUXHr", LIEF::assembly::aarch64::OPCODE::FCVTMUUXHr) + .value("FCVTMUUXSr", LIEF::assembly::aarch64::OPCODE::FCVTMUUXSr) + .value("FCVTMUv1f16", LIEF::assembly::aarch64::OPCODE::FCVTMUv1f16) + .value("FCVTMUv1i32", LIEF::assembly::aarch64::OPCODE::FCVTMUv1i32) + .value("FCVTMUv1i64", LIEF::assembly::aarch64::OPCODE::FCVTMUv1i64) + .value("FCVTMUv2f32", LIEF::assembly::aarch64::OPCODE::FCVTMUv2f32) + .value("FCVTMUv2f64", LIEF::assembly::aarch64::OPCODE::FCVTMUv2f64) + .value("FCVTMUv4f16", LIEF::assembly::aarch64::OPCODE::FCVTMUv4f16) + .value("FCVTMUv4f32", LIEF::assembly::aarch64::OPCODE::FCVTMUv4f32) + .value("FCVTMUv8f16", LIEF::assembly::aarch64::OPCODE::FCVTMUv8f16) + .value("FCVTNB_Z2Z_StoB", LIEF::assembly::aarch64::OPCODE::FCVTNB_Z2Z_StoB) + .value("FCVTNSDHr", LIEF::assembly::aarch64::OPCODE::FCVTNSDHr) + .value("FCVTNSDSr", LIEF::assembly::aarch64::OPCODE::FCVTNSDSr) + .value("FCVTNSSDr", LIEF::assembly::aarch64::OPCODE::FCVTNSSDr) + .value("FCVTNSSHr", LIEF::assembly::aarch64::OPCODE::FCVTNSSHr) + .value("FCVTNSUWDr", LIEF::assembly::aarch64::OPCODE::FCVTNSUWDr) + .value("FCVTNSUWHr", LIEF::assembly::aarch64::OPCODE::FCVTNSUWHr) + .value("FCVTNSUWSr", LIEF::assembly::aarch64::OPCODE::FCVTNSUWSr) + .value("FCVTNSUXDr", LIEF::assembly::aarch64::OPCODE::FCVTNSUXDr) + .value("FCVTNSUXHr", LIEF::assembly::aarch64::OPCODE::FCVTNSUXHr) + .value("FCVTNSUXSr", LIEF::assembly::aarch64::OPCODE::FCVTNSUXSr) + .value("FCVTNSv1f16", LIEF::assembly::aarch64::OPCODE::FCVTNSv1f16) + .value("FCVTNSv1i32", LIEF::assembly::aarch64::OPCODE::FCVTNSv1i32) + .value("FCVTNSv1i64", LIEF::assembly::aarch64::OPCODE::FCVTNSv1i64) + .value("FCVTNSv2f32", LIEF::assembly::aarch64::OPCODE::FCVTNSv2f32) + .value("FCVTNSv2f64", LIEF::assembly::aarch64::OPCODE::FCVTNSv2f64) + .value("FCVTNSv4f16", LIEF::assembly::aarch64::OPCODE::FCVTNSv4f16) + .value("FCVTNSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTNSv4f32) + .value("FCVTNSv8f16", LIEF::assembly::aarch64::OPCODE::FCVTNSv8f16) + .value("FCVTNT_Z2Z_StoB", LIEF::assembly::aarch64::OPCODE::FCVTNT_Z2Z_StoB) + .value("FCVTNT_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTNT_ZPmZ_DtoS) + .value("FCVTNT_ZPmZ_StoH", LIEF::assembly::aarch64::OPCODE::FCVTNT_ZPmZ_StoH) + .value("FCVTNT_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTNT_ZPzZ_DtoS) + .value("FCVTNT_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::FCVTNT_ZPzZ_StoH) + .value("FCVTNUDHr", LIEF::assembly::aarch64::OPCODE::FCVTNUDHr) + .value("FCVTNUDSr", LIEF::assembly::aarch64::OPCODE::FCVTNUDSr) + .value("FCVTNUSDr", LIEF::assembly::aarch64::OPCODE::FCVTNUSDr) + .value("FCVTNUSHr", LIEF::assembly::aarch64::OPCODE::FCVTNUSHr) + .value("FCVTNUUWDr", LIEF::assembly::aarch64::OPCODE::FCVTNUUWDr) + .value("FCVTNUUWHr", LIEF::assembly::aarch64::OPCODE::FCVTNUUWHr) + .value("FCVTNUUWSr", LIEF::assembly::aarch64::OPCODE::FCVTNUUWSr) + .value("FCVTNUUXDr", LIEF::assembly::aarch64::OPCODE::FCVTNUUXDr) + .value("FCVTNUUXHr", LIEF::assembly::aarch64::OPCODE::FCVTNUUXHr) + .value("FCVTNUUXSr", LIEF::assembly::aarch64::OPCODE::FCVTNUUXSr) + .value("FCVTNUv1f16", LIEF::assembly::aarch64::OPCODE::FCVTNUv1f16) + .value("FCVTNUv1i32", LIEF::assembly::aarch64::OPCODE::FCVTNUv1i32) + .value("FCVTNUv1i64", LIEF::assembly::aarch64::OPCODE::FCVTNUv1i64) + .value("FCVTNUv2f32", LIEF::assembly::aarch64::OPCODE::FCVTNUv2f32) + .value("FCVTNUv2f64", LIEF::assembly::aarch64::OPCODE::FCVTNUv2f64) + .value("FCVTNUv4f16", LIEF::assembly::aarch64::OPCODE::FCVTNUv4f16) + .value("FCVTNUv4f32", LIEF::assembly::aarch64::OPCODE::FCVTNUv4f32) + .value("FCVTNUv8f16", LIEF::assembly::aarch64::OPCODE::FCVTNUv8f16) + .value("FCVTN_F16v16f8", LIEF::assembly::aarch64::OPCODE::FCVTN_F16v16f8) + .value("FCVTN_F16v8f8", LIEF::assembly::aarch64::OPCODE::FCVTN_F16v8f8) + .value("FCVTN_F322v16f8", LIEF::assembly::aarch64::OPCODE::FCVTN_F322v16f8) + .value("FCVTN_F32v8f8", LIEF::assembly::aarch64::OPCODE::FCVTN_F32v8f8) + .value("FCVTN_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::FCVTN_Z2Z_HtoB) + .value("FCVTN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::FCVTN_Z2Z_StoH) + .value("FCVTN_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::FCVTN_Z4Z_StoB) + .value("FCVTNv2i32", LIEF::assembly::aarch64::OPCODE::FCVTNv2i32) + .value("FCVTNv4i16", LIEF::assembly::aarch64::OPCODE::FCVTNv4i16) + .value("FCVTNv4i32", LIEF::assembly::aarch64::OPCODE::FCVTNv4i32) + .value("FCVTNv8i16", LIEF::assembly::aarch64::OPCODE::FCVTNv8i16) + .value("FCVTPSDHr", LIEF::assembly::aarch64::OPCODE::FCVTPSDHr) + .value("FCVTPSDSr", LIEF::assembly::aarch64::OPCODE::FCVTPSDSr) + .value("FCVTPSSDr", LIEF::assembly::aarch64::OPCODE::FCVTPSSDr) + .value("FCVTPSSHr", LIEF::assembly::aarch64::OPCODE::FCVTPSSHr) + .value("FCVTPSUWDr", LIEF::assembly::aarch64::OPCODE::FCVTPSUWDr) + .value("FCVTPSUWHr", LIEF::assembly::aarch64::OPCODE::FCVTPSUWHr) + .value("FCVTPSUWSr", LIEF::assembly::aarch64::OPCODE::FCVTPSUWSr) + .value("FCVTPSUXDr", LIEF::assembly::aarch64::OPCODE::FCVTPSUXDr) + .value("FCVTPSUXHr", LIEF::assembly::aarch64::OPCODE::FCVTPSUXHr) + .value("FCVTPSUXSr", LIEF::assembly::aarch64::OPCODE::FCVTPSUXSr) + .value("FCVTPSv1f16", LIEF::assembly::aarch64::OPCODE::FCVTPSv1f16) + .value("FCVTPSv1i32", LIEF::assembly::aarch64::OPCODE::FCVTPSv1i32) + .value("FCVTPSv1i64", LIEF::assembly::aarch64::OPCODE::FCVTPSv1i64) + .value("FCVTPSv2f32", LIEF::assembly::aarch64::OPCODE::FCVTPSv2f32) + .value("FCVTPSv2f64", LIEF::assembly::aarch64::OPCODE::FCVTPSv2f64) + .value("FCVTPSv4f16", LIEF::assembly::aarch64::OPCODE::FCVTPSv4f16) + .value("FCVTPSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTPSv4f32) + .value("FCVTPSv8f16", LIEF::assembly::aarch64::OPCODE::FCVTPSv8f16) + .value("FCVTPUDHr", LIEF::assembly::aarch64::OPCODE::FCVTPUDHr) + .value("FCVTPUDSr", LIEF::assembly::aarch64::OPCODE::FCVTPUDSr) + .value("FCVTPUSDr", LIEF::assembly::aarch64::OPCODE::FCVTPUSDr) + .value("FCVTPUSHr", LIEF::assembly::aarch64::OPCODE::FCVTPUSHr) + .value("FCVTPUUWDr", LIEF::assembly::aarch64::OPCODE::FCVTPUUWDr) + .value("FCVTPUUWHr", LIEF::assembly::aarch64::OPCODE::FCVTPUUWHr) + .value("FCVTPUUWSr", LIEF::assembly::aarch64::OPCODE::FCVTPUUWSr) + .value("FCVTPUUXDr", LIEF::assembly::aarch64::OPCODE::FCVTPUUXDr) + .value("FCVTPUUXHr", LIEF::assembly::aarch64::OPCODE::FCVTPUUXHr) + .value("FCVTPUUXSr", LIEF::assembly::aarch64::OPCODE::FCVTPUUXSr) + .value("FCVTPUv1f16", LIEF::assembly::aarch64::OPCODE::FCVTPUv1f16) + .value("FCVTPUv1i32", LIEF::assembly::aarch64::OPCODE::FCVTPUv1i32) + .value("FCVTPUv1i64", LIEF::assembly::aarch64::OPCODE::FCVTPUv1i64) + .value("FCVTPUv2f32", LIEF::assembly::aarch64::OPCODE::FCVTPUv2f32) + .value("FCVTPUv2f64", LIEF::assembly::aarch64::OPCODE::FCVTPUv2f64) + .value("FCVTPUv4f16", LIEF::assembly::aarch64::OPCODE::FCVTPUv4f16) + .value("FCVTPUv4f32", LIEF::assembly::aarch64::OPCODE::FCVTPUv4f32) + .value("FCVTPUv8f16", LIEF::assembly::aarch64::OPCODE::FCVTPUv8f16) + .value("FCVTSDr", LIEF::assembly::aarch64::OPCODE::FCVTSDr) + .value("FCVTSHr", LIEF::assembly::aarch64::OPCODE::FCVTSHr) + .value("FCVTXNT_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTXNT_ZPmZ_DtoS) + .value("FCVTXNT_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTXNT_ZPzZ_StoD) + .value("FCVTXNv1i64", LIEF::assembly::aarch64::OPCODE::FCVTXNv1i64) + .value("FCVTXNv2f32", LIEF::assembly::aarch64::OPCODE::FCVTXNv2f32) + .value("FCVTXNv4f32", LIEF::assembly::aarch64::OPCODE::FCVTXNv4f32) + .value("FCVTX_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTX_ZPmZ_DtoS) + .value("FCVTX_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTX_ZPzZ_DtoS) + .value("FCVTZSDHr", LIEF::assembly::aarch64::OPCODE::FCVTZSDHr) + .value("FCVTZSDSr", LIEF::assembly::aarch64::OPCODE::FCVTZSDSr) + .value("FCVTZSN_Z2Z_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZSN_Z2Z_DtoS) + .value("FCVTZSN_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::FCVTZSN_Z2Z_HtoB) + .value("FCVTZSN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::FCVTZSN_Z2Z_StoH) + .value("FCVTZSSDr", LIEF::assembly::aarch64::OPCODE::FCVTZSSDr) + .value("FCVTZSSHr", LIEF::assembly::aarch64::OPCODE::FCVTZSSHr) + .value("FCVTZSSWDri", LIEF::assembly::aarch64::OPCODE::FCVTZSSWDri) + .value("FCVTZSSWHri", LIEF::assembly::aarch64::OPCODE::FCVTZSSWHri) + .value("FCVTZSSWSri", LIEF::assembly::aarch64::OPCODE::FCVTZSSWSri) + .value("FCVTZSSXDri", LIEF::assembly::aarch64::OPCODE::FCVTZSSXDri) + .value("FCVTZSSXHri", LIEF::assembly::aarch64::OPCODE::FCVTZSSXHri) + .value("FCVTZSSXSri", LIEF::assembly::aarch64::OPCODE::FCVTZSSXSri) + .value("FCVTZSUWDr", LIEF::assembly::aarch64::OPCODE::FCVTZSUWDr) + .value("FCVTZSUWHr", LIEF::assembly::aarch64::OPCODE::FCVTZSUWHr) + .value("FCVTZSUWSr", LIEF::assembly::aarch64::OPCODE::FCVTZSUWSr) + .value("FCVTZSUXDr", LIEF::assembly::aarch64::OPCODE::FCVTZSUXDr) + .value("FCVTZSUXHr", LIEF::assembly::aarch64::OPCODE::FCVTZSUXHr) + .value("FCVTZSUXSr", LIEF::assembly::aarch64::OPCODE::FCVTZSUXSr) + .value("FCVTZS_2Z2Z_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_2Z2Z_StoS) + .value("FCVTZS_4Z4Z_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_4Z4Z_StoS) + .value("FCVTZS_ZPmZ_DtoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_DtoD) + .value("FCVTZS_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_DtoS) + .value("FCVTZS_ZPmZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoD) + .value("FCVTZS_ZPmZ_HtoH", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoH) + .value("FCVTZS_ZPmZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_HtoS) + .value("FCVTZS_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_StoD) + .value("FCVTZS_ZPmZ_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPmZ_StoS) + .value("FCVTZS_ZPzZ_DtoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_DtoD) + .value("FCVTZS_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_DtoS) + .value("FCVTZS_ZPzZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_HtoD) + .value("FCVTZS_ZPzZ_HtoH", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_HtoH) + .value("FCVTZS_ZPzZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_HtoS) + .value("FCVTZS_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_StoD) + .value("FCVTZS_ZPzZ_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZS_ZPzZ_StoS) + .value("FCVTZSd", LIEF::assembly::aarch64::OPCODE::FCVTZSd) + .value("FCVTZSh", LIEF::assembly::aarch64::OPCODE::FCVTZSh) + .value("FCVTZSs", LIEF::assembly::aarch64::OPCODE::FCVTZSs) + .value("FCVTZSv1f16", LIEF::assembly::aarch64::OPCODE::FCVTZSv1f16) + .value("FCVTZSv1i32", LIEF::assembly::aarch64::OPCODE::FCVTZSv1i32) + .value("FCVTZSv1i64", LIEF::assembly::aarch64::OPCODE::FCVTZSv1i64) + .value("FCVTZSv2f32", LIEF::assembly::aarch64::OPCODE::FCVTZSv2f32) + .value("FCVTZSv2f64", LIEF::assembly::aarch64::OPCODE::FCVTZSv2f64) + .value("FCVTZSv2i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv2i32_shift) + .value("FCVTZSv2i64_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv2i64_shift) + .value("FCVTZSv4f16", LIEF::assembly::aarch64::OPCODE::FCVTZSv4f16) + .value("FCVTZSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTZSv4f32) + .value("FCVTZSv4i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv4i16_shift) + .value("FCVTZSv4i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv4i32_shift) + .value("FCVTZSv8f16", LIEF::assembly::aarch64::OPCODE::FCVTZSv8f16) + .value("FCVTZSv8i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv8i16_shift) + .value("FCVTZUDHr", LIEF::assembly::aarch64::OPCODE::FCVTZUDHr) + .value("FCVTZUDSr", LIEF::assembly::aarch64::OPCODE::FCVTZUDSr) + .value("FCVTZUN_Z2Z_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZUN_Z2Z_DtoS) + .value("FCVTZUN_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::FCVTZUN_Z2Z_HtoB) + .value("FCVTZUN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::FCVTZUN_Z2Z_StoH) + .value("FCVTZUSDr", LIEF::assembly::aarch64::OPCODE::FCVTZUSDr) + .value("FCVTZUSHr", LIEF::assembly::aarch64::OPCODE::FCVTZUSHr) + .value("FCVTZUSWDri", LIEF::assembly::aarch64::OPCODE::FCVTZUSWDri) + .value("FCVTZUSWHri", LIEF::assembly::aarch64::OPCODE::FCVTZUSWHri) + .value("FCVTZUSWSri", LIEF::assembly::aarch64::OPCODE::FCVTZUSWSri) + .value("FCVTZUSXDri", LIEF::assembly::aarch64::OPCODE::FCVTZUSXDri) + .value("FCVTZUSXHri", LIEF::assembly::aarch64::OPCODE::FCVTZUSXHri) + .value("FCVTZUSXSri", LIEF::assembly::aarch64::OPCODE::FCVTZUSXSri) + .value("FCVTZUUWDr", LIEF::assembly::aarch64::OPCODE::FCVTZUUWDr) + .value("FCVTZUUWHr", LIEF::assembly::aarch64::OPCODE::FCVTZUUWHr) + .value("FCVTZUUWSr", LIEF::assembly::aarch64::OPCODE::FCVTZUUWSr) + .value("FCVTZUUXDr", LIEF::assembly::aarch64::OPCODE::FCVTZUUXDr) + .value("FCVTZUUXHr", LIEF::assembly::aarch64::OPCODE::FCVTZUUXHr) + .value("FCVTZUUXSr", LIEF::assembly::aarch64::OPCODE::FCVTZUUXSr) + .value("FCVTZU_2Z2Z_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_2Z2Z_StoS) + .value("FCVTZU_4Z4Z_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_4Z4Z_StoS) + .value("FCVTZU_ZPmZ_DtoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_DtoD) + .value("FCVTZU_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_DtoS) + .value("FCVTZU_ZPmZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoD) + .value("FCVTZU_ZPmZ_HtoH", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoH) + .value("FCVTZU_ZPmZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoS) + .value("FCVTZU_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoD) + .value("FCVTZU_ZPmZ_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoS) + .value("FCVTZU_ZPzZ_DtoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_DtoD) + .value("FCVTZU_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_DtoS) + .value("FCVTZU_ZPzZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_HtoD) + .value("FCVTZU_ZPzZ_HtoH", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_HtoH) + .value("FCVTZU_ZPzZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_HtoS) + .value("FCVTZU_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_StoD) + .value("FCVTZU_ZPzZ_StoS", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPzZ_StoS) + .value("FCVTZUd", LIEF::assembly::aarch64::OPCODE::FCVTZUd) + .value("FCVTZUh", LIEF::assembly::aarch64::OPCODE::FCVTZUh) + .value("FCVTZUs", LIEF::assembly::aarch64::OPCODE::FCVTZUs) + .value("FCVTZUv1f16", LIEF::assembly::aarch64::OPCODE::FCVTZUv1f16) + .value("FCVTZUv1i32", LIEF::assembly::aarch64::OPCODE::FCVTZUv1i32) + .value("FCVTZUv1i64", LIEF::assembly::aarch64::OPCODE::FCVTZUv1i64) + .value("FCVTZUv2f32", LIEF::assembly::aarch64::OPCODE::FCVTZUv2f32) + .value("FCVTZUv2f64", LIEF::assembly::aarch64::OPCODE::FCVTZUv2f64) + .value("FCVTZUv2i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZUv2i32_shift) + .value("FCVTZUv2i64_shift", LIEF::assembly::aarch64::OPCODE::FCVTZUv2i64_shift) + .value("FCVTZUv4f16", LIEF::assembly::aarch64::OPCODE::FCVTZUv4f16) + .value("FCVTZUv4f32", LIEF::assembly::aarch64::OPCODE::FCVTZUv4f32) + .value("FCVTZUv4i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZUv4i16_shift) + .value("FCVTZUv4i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZUv4i32_shift) + .value("FCVTZUv8f16", LIEF::assembly::aarch64::OPCODE::FCVTZUv8f16) + .value("FCVTZUv8i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZUv8i16_shift) + .value("FCVT_2ZZ_H_S", LIEF::assembly::aarch64::OPCODE::FCVT_2ZZ_H_S) + .value("FCVT_Z2Z_HtoB", LIEF::assembly::aarch64::OPCODE::FCVT_Z2Z_HtoB) + .value("FCVT_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::FCVT_Z2Z_StoH) + .value("FCVT_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::FCVT_Z4Z_StoB) + .value("FCVT_ZPmZ_DtoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoH) + .value("FCVT_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoS); + opcodes.value("FCVT_ZPmZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoD) + .value("FCVT_ZPmZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoS) + .value("FCVT_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoD) + .value("FCVT_ZPmZ_StoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoH) + .value("FCVT_ZPzZ_DtoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_DtoH) + .value("FCVT_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_DtoS) + .value("FCVT_ZPzZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_HtoD) + .value("FCVT_ZPzZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_HtoS) + .value("FCVT_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_StoD) + .value("FCVT_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPzZ_StoH) + .value("FDIVDrr", LIEF::assembly::aarch64::OPCODE::FDIVDrr) + .value("FDIVHrr", LIEF::assembly::aarch64::OPCODE::FDIVHrr) + .value("FDIVR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPmZ_D) + .value("FDIVR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPmZ_H) + .value("FDIVR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FDIVR_ZPmZ_S) + .value("FDIVSrr", LIEF::assembly::aarch64::OPCODE::FDIVSrr) + .value("FDIV_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FDIV_ZPmZ_D) + .value("FDIV_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FDIV_ZPmZ_H) + .value("FDIV_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FDIV_ZPmZ_S) + .value("FDIVv2f32", LIEF::assembly::aarch64::OPCODE::FDIVv2f32) + .value("FDIVv2f64", LIEF::assembly::aarch64::OPCODE::FDIVv2f64) + .value("FDIVv4f16", LIEF::assembly::aarch64::OPCODE::FDIVv4f16) + .value("FDIVv4f32", LIEF::assembly::aarch64::OPCODE::FDIVv4f32) + .value("FDIVv8f16", LIEF::assembly::aarch64::OPCODE::FDIVv8f16) + .value("FDOT_VG2_M2Z2Z_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoH) + .value("FDOT_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoS) + .value("FDOT_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_HtoS) + .value("FDOT_VG2_M2ZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_BtoH) + .value("FDOT_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_BtoS) + .value("FDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_HtoS) + .value("FDOT_VG2_M2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_BtoH) + .value("FDOT_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_BtoS) + .value("FDOT_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZ_HtoS) + .value("FDOT_VG4_M4Z4Z_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_BtoH) + .value("FDOT_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_BtoS) + .value("FDOT_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4Z4Z_HtoS) + .value("FDOT_VG4_M4ZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_BtoH) + .value("FDOT_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_BtoS) + .value("FDOT_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZI_HtoS) + .value("FDOT_VG4_M4ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_BtoH) + .value("FDOT_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_BtoS) + .value("FDOT_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FDOT_VG4_M4ZZ_HtoS) + .value("FDOT_ZZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZI_BtoH) + .value("FDOT_ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZI_BtoS) + .value("FDOT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZI_S) + .value("FDOT_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZ_BtoH) + .value("FDOT_ZZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZ_BtoS) + .value("FDOT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FDOT_ZZZ_S) + .value("FDOTlanev2f32", LIEF::assembly::aarch64::OPCODE::FDOTlanev2f32) + .value("FDOTlanev4f16", LIEF::assembly::aarch64::OPCODE::FDOTlanev4f16) + .value("FDOTlanev4f16_v2f32", LIEF::assembly::aarch64::OPCODE::FDOTlanev4f16_v2f32) + .value("FDOTlanev4f32", LIEF::assembly::aarch64::OPCODE::FDOTlanev4f32) + .value("FDOTlanev8f16", LIEF::assembly::aarch64::OPCODE::FDOTlanev8f16) + .value("FDOTlanev8f16_v4f32", LIEF::assembly::aarch64::OPCODE::FDOTlanev8f16_v4f32) + .value("FDOTv2f32", LIEF::assembly::aarch64::OPCODE::FDOTv2f32) + .value("FDOTv4f16", LIEF::assembly::aarch64::OPCODE::FDOTv4f16) + .value("FDOTv4f16_v2f32", LIEF::assembly::aarch64::OPCODE::FDOTv4f16_v2f32) + .value("FDOTv4f32", LIEF::assembly::aarch64::OPCODE::FDOTv4f32) + .value("FDOTv8f16", LIEF::assembly::aarch64::OPCODE::FDOTv8f16) + .value("FDOTv8f16_v4f32", LIEF::assembly::aarch64::OPCODE::FDOTv8f16_v4f32) + .value("FDUP_ZI_D", LIEF::assembly::aarch64::OPCODE::FDUP_ZI_D) + .value("FDUP_ZI_H", LIEF::assembly::aarch64::OPCODE::FDUP_ZI_H) + .value("FDUP_ZI_S", LIEF::assembly::aarch64::OPCODE::FDUP_ZI_S) + .value("FEXPA_ZZ_D", LIEF::assembly::aarch64::OPCODE::FEXPA_ZZ_D) + .value("FEXPA_ZZ_H", LIEF::assembly::aarch64::OPCODE::FEXPA_ZZ_H) + .value("FEXPA_ZZ_S", LIEF::assembly::aarch64::OPCODE::FEXPA_ZZ_S) + .value("FIRSTP_XPP_B", LIEF::assembly::aarch64::OPCODE::FIRSTP_XPP_B) + .value("FIRSTP_XPP_D", LIEF::assembly::aarch64::OPCODE::FIRSTP_XPP_D) + .value("FIRSTP_XPP_H", LIEF::assembly::aarch64::OPCODE::FIRSTP_XPP_H) + .value("FIRSTP_XPP_S", LIEF::assembly::aarch64::OPCODE::FIRSTP_XPP_S) + .value("FJCVTZS", LIEF::assembly::aarch64::OPCODE::FJCVTZS) + .value("FLOGB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPmZ_D) + .value("FLOGB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPmZ_H) + .value("FLOGB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPmZ_S) + .value("FLOGB_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPzZ_D) + .value("FLOGB_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPzZ_H) + .value("FLOGB_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FLOGB_ZPzZ_S) + .value("FMADDDrrr", LIEF::assembly::aarch64::OPCODE::FMADDDrrr) + .value("FMADDHrrr", LIEF::assembly::aarch64::OPCODE::FMADDHrrr) + .value("FMADDSrrr", LIEF::assembly::aarch64::OPCODE::FMADDSrrr) + .value("FMAD_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMAD_ZPmZZ_D) + .value("FMAD_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMAD_ZPmZZ_H) + .value("FMAD_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMAD_ZPmZZ_S) + .value("FMAXDrr", LIEF::assembly::aarch64::OPCODE::FMAXDrr) + .value("FMAXHrr", LIEF::assembly::aarch64::OPCODE::FMAXHrr) + .value("FMAXNMDrr", LIEF::assembly::aarch64::OPCODE::FMAXNMDrr) + .value("FMAXNMHrr", LIEF::assembly::aarch64::OPCODE::FMAXNMHrr) + .value("FMAXNMP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMAXNMP_ZPmZZ_D) + .value("FMAXNMP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMAXNMP_ZPmZZ_H) + .value("FMAXNMP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMAXNMP_ZPmZZ_S) + .value("FMAXNMPv2f32", LIEF::assembly::aarch64::OPCODE::FMAXNMPv2f32) + .value("FMAXNMPv2f64", LIEF::assembly::aarch64::OPCODE::FMAXNMPv2f64) + .value("FMAXNMPv2i16p", LIEF::assembly::aarch64::OPCODE::FMAXNMPv2i16p) + .value("FMAXNMPv2i32p", LIEF::assembly::aarch64::OPCODE::FMAXNMPv2i32p) + .value("FMAXNMPv2i64p", LIEF::assembly::aarch64::OPCODE::FMAXNMPv2i64p) + .value("FMAXNMPv4f16", LIEF::assembly::aarch64::OPCODE::FMAXNMPv4f16) + .value("FMAXNMPv4f32", LIEF::assembly::aarch64::OPCODE::FMAXNMPv4f32) + .value("FMAXNMPv8f16", LIEF::assembly::aarch64::OPCODE::FMAXNMPv8f16) + .value("FMAXNMQV_D", LIEF::assembly::aarch64::OPCODE::FMAXNMQV_D) + .value("FMAXNMQV_H", LIEF::assembly::aarch64::OPCODE::FMAXNMQV_H) + .value("FMAXNMQV_S", LIEF::assembly::aarch64::OPCODE::FMAXNMQV_S) + .value("FMAXNMSrr", LIEF::assembly::aarch64::OPCODE::FMAXNMSrr) + .value("FMAXNMV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMAXNMV_VPZ_D) + .value("FMAXNMV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMAXNMV_VPZ_H) + .value("FMAXNMV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FMAXNMV_VPZ_S) + .value("FMAXNMVv4i16v", LIEF::assembly::aarch64::OPCODE::FMAXNMVv4i16v) + .value("FMAXNMVv4i32v", LIEF::assembly::aarch64::OPCODE::FMAXNMVv4i32v) + .value("FMAXNMVv8i16v", LIEF::assembly::aarch64::OPCODE::FMAXNMVv8i16v) + .value("FMAXNM_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2Z2Z_D) + .value("FMAXNM_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2Z2Z_H) + .value("FMAXNM_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2Z2Z_S) + .value("FMAXNM_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2ZZ_D) + .value("FMAXNM_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2ZZ_H) + .value("FMAXNM_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG2_2ZZ_S) + .value("FMAXNM_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4Z4Z_D) + .value("FMAXNM_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4Z4Z_H) + .value("FMAXNM_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4Z4Z_S) + .value("FMAXNM_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4ZZ_D) + .value("FMAXNM_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4ZZ_H) + .value("FMAXNM_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_VG4_4ZZ_S) + .value("FMAXNM_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmI_D) + .value("FMAXNM_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmI_H) + .value("FMAXNM_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmI_S) + .value("FMAXNM_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmZ_D) + .value("FMAXNM_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmZ_H) + .value("FMAXNM_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMAXNM_ZPmZ_S) + .value("FMAXNMv2f32", LIEF::assembly::aarch64::OPCODE::FMAXNMv2f32) + .value("FMAXNMv2f64", LIEF::assembly::aarch64::OPCODE::FMAXNMv2f64) + .value("FMAXNMv4f16", LIEF::assembly::aarch64::OPCODE::FMAXNMv4f16) + .value("FMAXNMv4f32", LIEF::assembly::aarch64::OPCODE::FMAXNMv4f32) + .value("FMAXNMv8f16", LIEF::assembly::aarch64::OPCODE::FMAXNMv8f16) + .value("FMAXP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMAXP_ZPmZZ_D) + .value("FMAXP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMAXP_ZPmZZ_H) + .value("FMAXP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMAXP_ZPmZZ_S) + .value("FMAXPv2f32", LIEF::assembly::aarch64::OPCODE::FMAXPv2f32) + .value("FMAXPv2f64", LIEF::assembly::aarch64::OPCODE::FMAXPv2f64) + .value("FMAXPv2i16p", LIEF::assembly::aarch64::OPCODE::FMAXPv2i16p) + .value("FMAXPv2i32p", LIEF::assembly::aarch64::OPCODE::FMAXPv2i32p) + .value("FMAXPv2i64p", LIEF::assembly::aarch64::OPCODE::FMAXPv2i64p) + .value("FMAXPv4f16", LIEF::assembly::aarch64::OPCODE::FMAXPv4f16) + .value("FMAXPv4f32", LIEF::assembly::aarch64::OPCODE::FMAXPv4f32) + .value("FMAXPv8f16", LIEF::assembly::aarch64::OPCODE::FMAXPv8f16) + .value("FMAXQV_D", LIEF::assembly::aarch64::OPCODE::FMAXQV_D) + .value("FMAXQV_H", LIEF::assembly::aarch64::OPCODE::FMAXQV_H) + .value("FMAXQV_S", LIEF::assembly::aarch64::OPCODE::FMAXQV_S) + .value("FMAXSrr", LIEF::assembly::aarch64::OPCODE::FMAXSrr) + .value("FMAXV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMAXV_VPZ_D) + .value("FMAXV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMAXV_VPZ_H) + .value("FMAXV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FMAXV_VPZ_S) + .value("FMAXVv4i16v", LIEF::assembly::aarch64::OPCODE::FMAXVv4i16v) + .value("FMAXVv4i32v", LIEF::assembly::aarch64::OPCODE::FMAXVv4i32v) + .value("FMAXVv8i16v", LIEF::assembly::aarch64::OPCODE::FMAXVv8i16v) + .value("FMAX_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2Z2Z_D) + .value("FMAX_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2Z2Z_H) + .value("FMAX_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2Z2Z_S) + .value("FMAX_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2ZZ_D) + .value("FMAX_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2ZZ_H) + .value("FMAX_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMAX_VG2_2ZZ_S) + .value("FMAX_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4Z4Z_D) + .value("FMAX_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4Z4Z_H) + .value("FMAX_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4Z4Z_S) + .value("FMAX_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4ZZ_D) + .value("FMAX_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4ZZ_H) + .value("FMAX_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMAX_VG4_4ZZ_S) + .value("FMAX_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmI_D) + .value("FMAX_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmI_H) + .value("FMAX_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmI_S) + .value("FMAX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmZ_D) + .value("FMAX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmZ_H) + .value("FMAX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMAX_ZPmZ_S) + .value("FMAXv2f32", LIEF::assembly::aarch64::OPCODE::FMAXv2f32) + .value("FMAXv2f64", LIEF::assembly::aarch64::OPCODE::FMAXv2f64) + .value("FMAXv4f16", LIEF::assembly::aarch64::OPCODE::FMAXv4f16) + .value("FMAXv4f32", LIEF::assembly::aarch64::OPCODE::FMAXv4f32) + .value("FMAXv8f16", LIEF::assembly::aarch64::OPCODE::FMAXv8f16) + .value("FMINDrr", LIEF::assembly::aarch64::OPCODE::FMINDrr) + .value("FMINHrr", LIEF::assembly::aarch64::OPCODE::FMINHrr) + .value("FMINNMDrr", LIEF::assembly::aarch64::OPCODE::FMINNMDrr) + .value("FMINNMHrr", LIEF::assembly::aarch64::OPCODE::FMINNMHrr) + .value("FMINNMP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMINNMP_ZPmZZ_D) + .value("FMINNMP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMINNMP_ZPmZZ_H) + .value("FMINNMP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMINNMP_ZPmZZ_S) + .value("FMINNMPv2f32", LIEF::assembly::aarch64::OPCODE::FMINNMPv2f32) + .value("FMINNMPv2f64", LIEF::assembly::aarch64::OPCODE::FMINNMPv2f64) + .value("FMINNMPv2i16p", LIEF::assembly::aarch64::OPCODE::FMINNMPv2i16p) + .value("FMINNMPv2i32p", LIEF::assembly::aarch64::OPCODE::FMINNMPv2i32p) + .value("FMINNMPv2i64p", LIEF::assembly::aarch64::OPCODE::FMINNMPv2i64p) + .value("FMINNMPv4f16", LIEF::assembly::aarch64::OPCODE::FMINNMPv4f16) + .value("FMINNMPv4f32", LIEF::assembly::aarch64::OPCODE::FMINNMPv4f32) + .value("FMINNMPv8f16", LIEF::assembly::aarch64::OPCODE::FMINNMPv8f16) + .value("FMINNMQV_D", LIEF::assembly::aarch64::OPCODE::FMINNMQV_D) + .value("FMINNMQV_H", LIEF::assembly::aarch64::OPCODE::FMINNMQV_H) + .value("FMINNMQV_S", LIEF::assembly::aarch64::OPCODE::FMINNMQV_S) + .value("FMINNMSrr", LIEF::assembly::aarch64::OPCODE::FMINNMSrr) + .value("FMINNMV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMINNMV_VPZ_D) + .value("FMINNMV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMINNMV_VPZ_H) + .value("FMINNMV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FMINNMV_VPZ_S) + .value("FMINNMVv4i16v", LIEF::assembly::aarch64::OPCODE::FMINNMVv4i16v) + .value("FMINNMVv4i32v", LIEF::assembly::aarch64::OPCODE::FMINNMVv4i32v) + .value("FMINNMVv8i16v", LIEF::assembly::aarch64::OPCODE::FMINNMVv8i16v) + .value("FMINNM_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2Z2Z_D) + .value("FMINNM_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2Z2Z_H) + .value("FMINNM_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2Z2Z_S) + .value("FMINNM_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2ZZ_D) + .value("FMINNM_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2ZZ_H) + .value("FMINNM_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMINNM_VG2_2ZZ_S) + .value("FMINNM_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4Z4Z_D) + .value("FMINNM_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4Z4Z_H) + .value("FMINNM_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4Z4Z_S) + .value("FMINNM_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4ZZ_D) + .value("FMINNM_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4ZZ_H) + .value("FMINNM_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMINNM_VG4_4ZZ_S) + .value("FMINNM_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmI_D) + .value("FMINNM_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmI_H) + .value("FMINNM_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmI_S) + .value("FMINNM_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmZ_D) + .value("FMINNM_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmZ_H) + .value("FMINNM_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMINNM_ZPmZ_S) + .value("FMINNMv2f32", LIEF::assembly::aarch64::OPCODE::FMINNMv2f32) + .value("FMINNMv2f64", LIEF::assembly::aarch64::OPCODE::FMINNMv2f64) + .value("FMINNMv4f16", LIEF::assembly::aarch64::OPCODE::FMINNMv4f16) + .value("FMINNMv4f32", LIEF::assembly::aarch64::OPCODE::FMINNMv4f32) + .value("FMINNMv8f16", LIEF::assembly::aarch64::OPCODE::FMINNMv8f16) + .value("FMINP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMINP_ZPmZZ_D) + .value("FMINP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMINP_ZPmZZ_H) + .value("FMINP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMINP_ZPmZZ_S) + .value("FMINPv2f32", LIEF::assembly::aarch64::OPCODE::FMINPv2f32) + .value("FMINPv2f64", LIEF::assembly::aarch64::OPCODE::FMINPv2f64) + .value("FMINPv2i16p", LIEF::assembly::aarch64::OPCODE::FMINPv2i16p) + .value("FMINPv2i32p", LIEF::assembly::aarch64::OPCODE::FMINPv2i32p) + .value("FMINPv2i64p", LIEF::assembly::aarch64::OPCODE::FMINPv2i64p) + .value("FMINPv4f16", LIEF::assembly::aarch64::OPCODE::FMINPv4f16) + .value("FMINPv4f32", LIEF::assembly::aarch64::OPCODE::FMINPv4f32) + .value("FMINPv8f16", LIEF::assembly::aarch64::OPCODE::FMINPv8f16) + .value("FMINQV_D", LIEF::assembly::aarch64::OPCODE::FMINQV_D) + .value("FMINQV_H", LIEF::assembly::aarch64::OPCODE::FMINQV_H) + .value("FMINQV_S", LIEF::assembly::aarch64::OPCODE::FMINQV_S) + .value("FMINSrr", LIEF::assembly::aarch64::OPCODE::FMINSrr) + .value("FMINV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_D) + .value("FMINV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_H) + .value("FMINV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_S) + .value("FMINVv4i16v", LIEF::assembly::aarch64::OPCODE::FMINVv4i16v) + .value("FMINVv4i32v", LIEF::assembly::aarch64::OPCODE::FMINVv4i32v) + .value("FMINVv8i16v", LIEF::assembly::aarch64::OPCODE::FMINVv8i16v) + .value("FMIN_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2Z2Z_D) + .value("FMIN_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2Z2Z_H) + .value("FMIN_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2Z2Z_S) + .value("FMIN_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2ZZ_D) + .value("FMIN_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2ZZ_H) + .value("FMIN_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMIN_VG2_2ZZ_S) + .value("FMIN_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4Z4Z_D) + .value("FMIN_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4Z4Z_H) + .value("FMIN_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4Z4Z_S) + .value("FMIN_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4ZZ_D) + .value("FMIN_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4ZZ_H) + .value("FMIN_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMIN_VG4_4ZZ_S) + .value("FMIN_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmI_D) + .value("FMIN_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmI_H) + .value("FMIN_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmI_S) + .value("FMIN_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmZ_D) + .value("FMIN_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmZ_H) + .value("FMIN_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMIN_ZPmZ_S) + .value("FMINv2f32", LIEF::assembly::aarch64::OPCODE::FMINv2f32) + .value("FMINv2f64", LIEF::assembly::aarch64::OPCODE::FMINv2f64) + .value("FMINv4f16", LIEF::assembly::aarch64::OPCODE::FMINv4f16) + .value("FMINv4f32", LIEF::assembly::aarch64::OPCODE::FMINv4f32) + .value("FMINv8f16", LIEF::assembly::aarch64::OPCODE::FMINv8f16) + .value("FMLAL2lanev4f16", LIEF::assembly::aarch64::OPCODE::FMLAL2lanev4f16) + .value("FMLAL2lanev8f16", LIEF::assembly::aarch64::OPCODE::FMLAL2lanev8f16) + .value("FMLAL2v4f16", LIEF::assembly::aarch64::OPCODE::FMLAL2v4f16) + .value("FMLAL2v8f16", LIEF::assembly::aarch64::OPCODE::FMLAL2v8f16) + .value("FMLALB_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALB_ZZZ) + .value("FMLALB_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALB_ZZZI) + .value("FMLALB_ZZZI_SHH", LIEF::assembly::aarch64::OPCODE::FMLALB_ZZZI_SHH) + .value("FMLALB_ZZZ_SHH", LIEF::assembly::aarch64::OPCODE::FMLALB_ZZZ_SHH) + .value("FMLALBlanev8f16", LIEF::assembly::aarch64::OPCODE::FMLALBlanev8f16) + .value("FMLALBv16i8_v8f16", LIEF::assembly::aarch64::OPCODE::FMLALBv16i8_v8f16) + .value("FMLALLBB_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALLBB_ZZZ) + .value("FMLALLBB_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALLBB_ZZZI) + .value("FMLALLBBlanev4f32", LIEF::assembly::aarch64::OPCODE::FMLALLBBlanev4f32) + .value("FMLALLBBv4f32", LIEF::assembly::aarch64::OPCODE::FMLALLBBv4f32) + .value("FMLALLBT_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALLBT_ZZZ) + .value("FMLALLBT_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALLBT_ZZZI) + .value("FMLALLBTlanev4f32", LIEF::assembly::aarch64::OPCODE::FMLALLBTlanev4f32) + .value("FMLALLBTv4f32", LIEF::assembly::aarch64::OPCODE::FMLALLBTv4f32) + .value("FMLALLTB_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALLTB_ZZZ) + .value("FMLALLTB_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALLTB_ZZZI) + .value("FMLALLTBlanev4f32", LIEF::assembly::aarch64::OPCODE::FMLALLTBlanev4f32) + .value("FMLALLTBv4f32", LIEF::assembly::aarch64::OPCODE::FMLALLTBv4f32) + .value("FMLALLTT_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALLTT_ZZZ) + .value("FMLALLTT_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALLTT_ZZZI) + .value("FMLALLTTlanev4f32", LIEF::assembly::aarch64::OPCODE::FMLALLTTlanev4f32) + .value("FMLALLTTv4f32", LIEF::assembly::aarch64::OPCODE::FMLALLTTv4f32) + .value("FMLALL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_MZZI_BtoS) + .value("FMLALL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_MZZ_BtoS) + .value("FMLALL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2Z2Z_BtoS) + .value("FMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZI_BtoS) + .value("FMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZ_BtoS) + .value("FMLALL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4Z4Z_BtoS) + .value("FMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZI_BtoS); + opcodes.value("FMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZ_BtoS) + .value("FMLALT_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZ) + .value("FMLALT_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZI) + .value("FMLALT_ZZZI_SHH", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZI_SHH) + .value("FMLALT_ZZZ_SHH", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZ_SHH) + .value("FMLALTlanev8f16", LIEF::assembly::aarch64::OPCODE::FMLALTlanev8f16) + .value("FMLALTv16i8_v8f16", LIEF::assembly::aarch64::OPCODE::FMLALTv16i8_v8f16) + .value("FMLAL_MZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZI_BtoH) + .value("FMLAL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZI_HtoS) + .value("FMLAL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_MZZ_HtoS) + .value("FMLAL_VG2_M2Z2Z_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2Z2Z_BtoH) + .value("FMLAL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2Z2Z_HtoS) + .value("FMLAL_VG2_M2ZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZI_BtoH) + .value("FMLAL_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZI_HtoS) + .value("FMLAL_VG2_M2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZ_BtoH) + .value("FMLAL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_M2ZZ_HtoS) + .value("FMLAL_VG2_MZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG2_MZZ_BtoH) + .value("FMLAL_VG4_M4Z4Z_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4Z4Z_BtoH) + .value("FMLAL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4Z4Z_HtoS) + .value("FMLAL_VG4_M4ZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZI_BtoH) + .value("FMLAL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZI_HtoS) + .value("FMLAL_VG4_M4ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZ_BtoH) + .value("FMLAL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLAL_VG4_M4ZZ_HtoS) + .value("FMLALlanev4f16", LIEF::assembly::aarch64::OPCODE::FMLALlanev4f16) + .value("FMLALlanev8f16", LIEF::assembly::aarch64::OPCODE::FMLALlanev8f16) + .value("FMLALv4f16", LIEF::assembly::aarch64::OPCODE::FMLALv4f16) + .value("FMLALv8f16", LIEF::assembly::aarch64::OPCODE::FMLALv8f16) + .value("FMLA_VG2_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_D) + .value("FMLA_VG2_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_H) + .value("FMLA_VG2_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2Z2Z_S) + .value("FMLA_VG2_M2ZZI_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_D) + .value("FMLA_VG2_M2ZZI_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_H) + .value("FMLA_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZI_S) + .value("FMLA_VG2_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_D) + .value("FMLA_VG2_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_H) + .value("FMLA_VG2_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG2_M2ZZ_S) + .value("FMLA_VG4_M4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_D) + .value("FMLA_VG4_M4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_H) + .value("FMLA_VG4_M4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4Z4Z_S) + .value("FMLA_VG4_M4ZZI_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_D) + .value("FMLA_VG4_M4ZZI_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_H) + .value("FMLA_VG4_M4ZZI_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZI_S) + .value("FMLA_VG4_M4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_D) + .value("FMLA_VG4_M4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_H) + .value("FMLA_VG4_M4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMLA_VG4_M4ZZ_S) + .value("FMLA_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMLA_ZPmZZ_D) + .value("FMLA_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMLA_ZPmZZ_H) + .value("FMLA_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMLA_ZPmZZ_S) + .value("FMLA_ZZZI_D", LIEF::assembly::aarch64::OPCODE::FMLA_ZZZI_D) + .value("FMLA_ZZZI_H", LIEF::assembly::aarch64::OPCODE::FMLA_ZZZI_H) + .value("FMLA_ZZZI_S", LIEF::assembly::aarch64::OPCODE::FMLA_ZZZI_S) + .value("FMLAv1i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv1i16_indexed) + .value("FMLAv1i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv1i32_indexed) + .value("FMLAv1i64_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv1i64_indexed) + .value("FMLAv2f32", LIEF::assembly::aarch64::OPCODE::FMLAv2f32) + .value("FMLAv2f64", LIEF::assembly::aarch64::OPCODE::FMLAv2f64) + .value("FMLAv2i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv2i32_indexed) + .value("FMLAv2i64_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv2i64_indexed) + .value("FMLAv4f16", LIEF::assembly::aarch64::OPCODE::FMLAv4f16) + .value("FMLAv4f32", LIEF::assembly::aarch64::OPCODE::FMLAv4f32) + .value("FMLAv4i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv4i16_indexed) + .value("FMLAv4i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv4i32_indexed) + .value("FMLAv8f16", LIEF::assembly::aarch64::OPCODE::FMLAv8f16) + .value("FMLAv8i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLAv8i16_indexed) + .value("FMLLA_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLLA_ZZZ_HtoS) + .value("FMLSL2lanev4f16", LIEF::assembly::aarch64::OPCODE::FMLSL2lanev4f16) + .value("FMLSL2lanev8f16", LIEF::assembly::aarch64::OPCODE::FMLSL2lanev8f16) + .value("FMLSL2v4f16", LIEF::assembly::aarch64::OPCODE::FMLSL2v4f16) + .value("FMLSL2v8f16", LIEF::assembly::aarch64::OPCODE::FMLSL2v8f16) + .value("FMLSLB_ZZZI_SHH", LIEF::assembly::aarch64::OPCODE::FMLSLB_ZZZI_SHH) + .value("FMLSLB_ZZZ_SHH", LIEF::assembly::aarch64::OPCODE::FMLSLB_ZZZ_SHH) + .value("FMLSLT_ZZZI_SHH", LIEF::assembly::aarch64::OPCODE::FMLSLT_ZZZI_SHH) + .value("FMLSLT_ZZZ_SHH", LIEF::assembly::aarch64::OPCODE::FMLSLT_ZZZ_SHH) + .value("FMLSL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_MZZI_HtoS) + .value("FMLSL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_MZZ_HtoS) + .value("FMLSL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2Z2Z_HtoS) + .value("FMLSL_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2ZZI_HtoS) + .value("FMLSL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG2_M2ZZ_HtoS) + .value("FMLSL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4Z4Z_HtoS) + .value("FMLSL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4ZZI_HtoS) + .value("FMLSL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMLSL_VG4_M4ZZ_HtoS) + .value("FMLSLlanev4f16", LIEF::assembly::aarch64::OPCODE::FMLSLlanev4f16) + .value("FMLSLlanev8f16", LIEF::assembly::aarch64::OPCODE::FMLSLlanev8f16) + .value("FMLSLv4f16", LIEF::assembly::aarch64::OPCODE::FMLSLv4f16) + .value("FMLSLv8f16", LIEF::assembly::aarch64::OPCODE::FMLSLv8f16) + .value("FMLS_VG2_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_D) + .value("FMLS_VG2_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_H) + .value("FMLS_VG2_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2Z2Z_S) + .value("FMLS_VG2_M2ZZI_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_D) + .value("FMLS_VG2_M2ZZI_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_H) + .value("FMLS_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZI_S) + .value("FMLS_VG2_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_D) + .value("FMLS_VG2_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_H) + .value("FMLS_VG2_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG2_M2ZZ_S) + .value("FMLS_VG4_M4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_D) + .value("FMLS_VG4_M4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_H) + .value("FMLS_VG4_M4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4Z4Z_S) + .value("FMLS_VG4_M4ZZI_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_D) + .value("FMLS_VG4_M4ZZI_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_H) + .value("FMLS_VG4_M4ZZI_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZI_S) + .value("FMLS_VG4_M4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_D) + .value("FMLS_VG4_M4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_H) + .value("FMLS_VG4_M4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMLS_VG4_M4ZZ_S) + .value("FMLS_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMLS_ZPmZZ_D) + .value("FMLS_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMLS_ZPmZZ_H) + .value("FMLS_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMLS_ZPmZZ_S) + .value("FMLS_ZZZI_D", LIEF::assembly::aarch64::OPCODE::FMLS_ZZZI_D) + .value("FMLS_ZZZI_H", LIEF::assembly::aarch64::OPCODE::FMLS_ZZZI_H) + .value("FMLS_ZZZI_S", LIEF::assembly::aarch64::OPCODE::FMLS_ZZZI_S) + .value("FMLSv1i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv1i16_indexed) + .value("FMLSv1i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv1i32_indexed) + .value("FMLSv1i64_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv1i64_indexed) + .value("FMLSv2f32", LIEF::assembly::aarch64::OPCODE::FMLSv2f32) + .value("FMLSv2f64", LIEF::assembly::aarch64::OPCODE::FMLSv2f64) + .value("FMLSv2i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv2i32_indexed) + .value("FMLSv2i64_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv2i64_indexed) + .value("FMLSv4f16", LIEF::assembly::aarch64::OPCODE::FMLSv4f16) + .value("FMLSv4f32", LIEF::assembly::aarch64::OPCODE::FMLSv4f32) + .value("FMLSv4i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv4i16_indexed) + .value("FMLSv4i32_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv4i32_indexed) + .value("FMLSv8f16", LIEF::assembly::aarch64::OPCODE::FMLSv8f16) + .value("FMLSv8i16_indexed", LIEF::assembly::aarch64::OPCODE::FMLSv8i16_indexed) + .value("FMMLA_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMMLA_ZZZ_BtoH) + .value("FMMLA_ZZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMMLA_ZZZ_BtoS) + .value("FMMLA_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FMMLA_ZZZ_D) + .value("FMMLA_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FMMLA_ZZZ_H) + .value("FMMLA_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FMMLA_ZZZ_S) + .value("FMMLAv4f32", LIEF::assembly::aarch64::OPCODE::FMMLAv4f32) + .value("FMMLAv8f16", LIEF::assembly::aarch64::OPCODE::FMMLAv8f16) + .value("FMMLAv8f16_v4f32", LIEF::assembly::aarch64::OPCODE::FMMLAv8f16_v4f32) + .value("FMMLAv8f16_v8f16", LIEF::assembly::aarch64::OPCODE::FMMLAv8f16_v8f16) + .value("FMOP4A_M2Z2Z_BtoH", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_BtoH) + .value("FMOP4A_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_BtoS) + .value("FMOP4A_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_D) + .value("FMOP4A_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_H) + .value("FMOP4A_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_HtoS) + .value("FMOP4A_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2Z2Z_S) + .value("FMOP4A_M2ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_BtoH) + .value("FMOP4A_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_BtoS) + .value("FMOP4A_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_D) + .value("FMOP4A_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_H) + .value("FMOP4A_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_HtoS) + .value("FMOP4A_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMOP4A_M2ZZ_S) + .value("FMOP4A_MZ2Z_BtoH", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_BtoH) + .value("FMOP4A_MZ2Z_BtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_BtoS) + .value("FMOP4A_MZ2Z_D", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_D) + .value("FMOP4A_MZ2Z_H", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_H) + .value("FMOP4A_MZ2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_HtoS) + .value("FMOP4A_MZ2Z_S", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZ2Z_S) + .value("FMOP4A_MZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_BtoH) + .value("FMOP4A_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_BtoS) + .value("FMOP4A_MZZ_D", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_D) + .value("FMOP4A_MZZ_H", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_H) + .value("FMOP4A_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_HtoS) + .value("FMOP4A_MZZ_S", LIEF::assembly::aarch64::OPCODE::FMOP4A_MZZ_S) + .value("FMOP4S_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_D) + .value("FMOP4S_M2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_H) + .value("FMOP4S_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_HtoS) + .value("FMOP4S_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2Z2Z_S) + .value("FMOP4S_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_D) + .value("FMOP4S_M2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_H) + .value("FMOP4S_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_HtoS) + .value("FMOP4S_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMOP4S_M2ZZ_S) + .value("FMOP4S_MZ2Z_D", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_D) + .value("FMOP4S_MZ2Z_H", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_H) + .value("FMOP4S_MZ2Z_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_HtoS) + .value("FMOP4S_MZ2Z_S", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZ2Z_S) + .value("FMOP4S_MZZ_D", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_D) + .value("FMOP4S_MZZ_H", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_H) + .value("FMOP4S_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_HtoS) + .value("FMOP4S_MZZ_S", LIEF::assembly::aarch64::OPCODE::FMOP4S_MZZ_S) + .value("FMOPAL_MPPZZ", LIEF::assembly::aarch64::OPCODE::FMOPAL_MPPZZ) + .value("FMOPA_MPPZZ_BtoH", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_BtoH) + .value("FMOPA_MPPZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_BtoS) + .value("FMOPA_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_D) + .value("FMOPA_MPPZZ_H", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_H) + .value("FMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::FMOPA_MPPZZ_S) + .value("FMOPSL_MPPZZ", LIEF::assembly::aarch64::OPCODE::FMOPSL_MPPZZ) + .value("FMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_D) + .value("FMOPS_MPPZZ_H", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_H) + .value("FMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::FMOPS_MPPZZ_S) + .value("FMOVDXHighr", LIEF::assembly::aarch64::OPCODE::FMOVDXHighr) + .value("FMOVDXr", LIEF::assembly::aarch64::OPCODE::FMOVDXr) + .value("FMOVDi", LIEF::assembly::aarch64::OPCODE::FMOVDi) + .value("FMOVDr", LIEF::assembly::aarch64::OPCODE::FMOVDr) + .value("FMOVHWr", LIEF::assembly::aarch64::OPCODE::FMOVHWr) + .value("FMOVHXr", LIEF::assembly::aarch64::OPCODE::FMOVHXr) + .value("FMOVHi", LIEF::assembly::aarch64::OPCODE::FMOVHi) + .value("FMOVHr", LIEF::assembly::aarch64::OPCODE::FMOVHr) + .value("FMOVSWr", LIEF::assembly::aarch64::OPCODE::FMOVSWr) + .value("FMOVSi", LIEF::assembly::aarch64::OPCODE::FMOVSi) + .value("FMOVSr", LIEF::assembly::aarch64::OPCODE::FMOVSr) + .value("FMOVWHr", LIEF::assembly::aarch64::OPCODE::FMOVWHr) + .value("FMOVWSr", LIEF::assembly::aarch64::OPCODE::FMOVWSr) + .value("FMOVXDHighr", LIEF::assembly::aarch64::OPCODE::FMOVXDHighr) + .value("FMOVXDr", LIEF::assembly::aarch64::OPCODE::FMOVXDr) + .value("FMOVXHr", LIEF::assembly::aarch64::OPCODE::FMOVXHr) + .value("FMOVv2f32_ns", LIEF::assembly::aarch64::OPCODE::FMOVv2f32_ns) + .value("FMOVv2f64_ns", LIEF::assembly::aarch64::OPCODE::FMOVv2f64_ns) + .value("FMOVv4f16_ns", LIEF::assembly::aarch64::OPCODE::FMOVv4f16_ns) + .value("FMOVv4f32_ns", LIEF::assembly::aarch64::OPCODE::FMOVv4f32_ns) + .value("FMOVv8f16_ns", LIEF::assembly::aarch64::OPCODE::FMOVv8f16_ns) + .value("FMSB_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FMSB_ZPmZZ_D) + .value("FMSB_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FMSB_ZPmZZ_H) + .value("FMSB_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FMSB_ZPmZZ_S) + .value("FMSUBDrrr", LIEF::assembly::aarch64::OPCODE::FMSUBDrrr) + .value("FMSUBHrrr", LIEF::assembly::aarch64::OPCODE::FMSUBHrrr) + .value("FMSUBSrrr", LIEF::assembly::aarch64::OPCODE::FMSUBSrrr) + .value("FMULDrr", LIEF::assembly::aarch64::OPCODE::FMULDrr) + .value("FMULHrr", LIEF::assembly::aarch64::OPCODE::FMULHrr) + .value("FMULSrr", LIEF::assembly::aarch64::OPCODE::FMULSrr) + .value("FMULX16", LIEF::assembly::aarch64::OPCODE::FMULX16) + .value("FMULX32", LIEF::assembly::aarch64::OPCODE::FMULX32) + .value("FMULX64", LIEF::assembly::aarch64::OPCODE::FMULX64) + .value("FMULX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMULX_ZPmZ_D) + .value("FMULX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMULX_ZPmZ_H) + .value("FMULX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMULX_ZPmZ_S) + .value("FMULXv1i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv1i16_indexed) + .value("FMULXv1i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv1i32_indexed) + .value("FMULXv1i64_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv1i64_indexed) + .value("FMULXv2f32", LIEF::assembly::aarch64::OPCODE::FMULXv2f32) + .value("FMULXv2f64", LIEF::assembly::aarch64::OPCODE::FMULXv2f64) + .value("FMULXv2i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv2i32_indexed) + .value("FMULXv2i64_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv2i64_indexed) + .value("FMULXv4f16", LIEF::assembly::aarch64::OPCODE::FMULXv4f16) + .value("FMULXv4f32", LIEF::assembly::aarch64::OPCODE::FMULXv4f32) + .value("FMULXv4i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv4i16_indexed) + .value("FMULXv4i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv4i32_indexed) + .value("FMULXv8f16", LIEF::assembly::aarch64::OPCODE::FMULXv8f16) + .value("FMULXv8i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULXv8i16_indexed) + .value("FMUL_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FMUL_2Z2Z_D) + .value("FMUL_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FMUL_2Z2Z_H) + .value("FMUL_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FMUL_2Z2Z_S) + .value("FMUL_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_2ZZ_D) + .value("FMUL_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FMUL_2ZZ_H) + .value("FMUL_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_2ZZ_S) + .value("FMUL_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_D) + .value("FMUL_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_H) + .value("FMUL_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_S) + .value("FMUL_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_D) + .value("FMUL_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_H) + .value("FMUL_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_S) + .value("FMUL_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmI_D) + .value("FMUL_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmI_H) + .value("FMUL_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmI_S) + .value("FMUL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmZ_D) + .value("FMUL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmZ_H) + .value("FMUL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmZ_S) + .value("FMUL_ZZZI_D", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZI_D) + .value("FMUL_ZZZI_H", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZI_H) + .value("FMUL_ZZZI_S", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZI_S) + .value("FMUL_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZ_D) + .value("FMUL_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZ_H) + .value("FMUL_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_ZZZ_S) + .value("FMULv1i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULv1i16_indexed) + .value("FMULv1i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULv1i32_indexed) + .value("FMULv1i64_indexed", LIEF::assembly::aarch64::OPCODE::FMULv1i64_indexed) + .value("FMULv2f32", LIEF::assembly::aarch64::OPCODE::FMULv2f32) + .value("FMULv2f64", LIEF::assembly::aarch64::OPCODE::FMULv2f64) + .value("FMULv2i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULv2i32_indexed) + .value("FMULv2i64_indexed", LIEF::assembly::aarch64::OPCODE::FMULv2i64_indexed) + .value("FMULv4f16", LIEF::assembly::aarch64::OPCODE::FMULv4f16) + .value("FMULv4f32", LIEF::assembly::aarch64::OPCODE::FMULv4f32) + .value("FMULv4i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULv4i16_indexed) + .value("FMULv4i32_indexed", LIEF::assembly::aarch64::OPCODE::FMULv4i32_indexed) + .value("FMULv8f16", LIEF::assembly::aarch64::OPCODE::FMULv8f16) + .value("FMULv8i16_indexed", LIEF::assembly::aarch64::OPCODE::FMULv8i16_indexed) + .value("FNEGDr", LIEF::assembly::aarch64::OPCODE::FNEGDr) + .value("FNEGHr", LIEF::assembly::aarch64::OPCODE::FNEGHr) + .value("FNEGSr", LIEF::assembly::aarch64::OPCODE::FNEGSr) + .value("FNEG_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_D) + .value("FNEG_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_H) + .value("FNEG_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FNEG_ZPmZ_S) + .value("FNEG_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FNEG_ZPzZ_D) + .value("FNEG_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FNEG_ZPzZ_H) + .value("FNEG_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FNEG_ZPzZ_S) + .value("FNEGv2f32", LIEF::assembly::aarch64::OPCODE::FNEGv2f32) + .value("FNEGv2f64", LIEF::assembly::aarch64::OPCODE::FNEGv2f64) + .value("FNEGv4f16", LIEF::assembly::aarch64::OPCODE::FNEGv4f16) + .value("FNEGv4f32", LIEF::assembly::aarch64::OPCODE::FNEGv4f32) + .value("FNEGv8f16", LIEF::assembly::aarch64::OPCODE::FNEGv8f16) + .value("FNMADDDrrr", LIEF::assembly::aarch64::OPCODE::FNMADDDrrr) + .value("FNMADDHrrr", LIEF::assembly::aarch64::OPCODE::FNMADDHrrr) + .value("FNMADDSrrr", LIEF::assembly::aarch64::OPCODE::FNMADDSrrr) + .value("FNMAD_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FNMAD_ZPmZZ_D) + .value("FNMAD_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FNMAD_ZPmZZ_H) + .value("FNMAD_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FNMAD_ZPmZZ_S) + .value("FNMLA_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPmZZ_D) + .value("FNMLA_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPmZZ_H) + .value("FNMLA_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FNMLA_ZPmZZ_S) + .value("FNMLS_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPmZZ_D) + .value("FNMLS_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPmZZ_H) + .value("FNMLS_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FNMLS_ZPmZZ_S) + .value("FNMSB_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::FNMSB_ZPmZZ_D) + .value("FNMSB_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::FNMSB_ZPmZZ_H) + .value("FNMSB_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::FNMSB_ZPmZZ_S) + .value("FNMSUBDrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBDrrr) + .value("FNMSUBHrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBHrrr) + .value("FNMSUBSrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBSrrr) + .value("FNMULDrr", LIEF::assembly::aarch64::OPCODE::FNMULDrr); + opcodes.value("FNMULHrr", LIEF::assembly::aarch64::OPCODE::FNMULHrr) + .value("FNMULSrr", LIEF::assembly::aarch64::OPCODE::FNMULSrr) + .value("FRECPE_ZZ_D", LIEF::assembly::aarch64::OPCODE::FRECPE_ZZ_D) + .value("FRECPE_ZZ_H", LIEF::assembly::aarch64::OPCODE::FRECPE_ZZ_H) + .value("FRECPE_ZZ_S", LIEF::assembly::aarch64::OPCODE::FRECPE_ZZ_S) + .value("FRECPEv1f16", LIEF::assembly::aarch64::OPCODE::FRECPEv1f16) + .value("FRECPEv1i32", LIEF::assembly::aarch64::OPCODE::FRECPEv1i32) + .value("FRECPEv1i64", LIEF::assembly::aarch64::OPCODE::FRECPEv1i64) + .value("FRECPEv2f32", LIEF::assembly::aarch64::OPCODE::FRECPEv2f32) + .value("FRECPEv2f64", LIEF::assembly::aarch64::OPCODE::FRECPEv2f64) + .value("FRECPEv4f16", LIEF::assembly::aarch64::OPCODE::FRECPEv4f16) + .value("FRECPEv4f32", LIEF::assembly::aarch64::OPCODE::FRECPEv4f32) + .value("FRECPEv8f16", LIEF::assembly::aarch64::OPCODE::FRECPEv8f16) + .value("FRECPS16", LIEF::assembly::aarch64::OPCODE::FRECPS16) + .value("FRECPS32", LIEF::assembly::aarch64::OPCODE::FRECPS32) + .value("FRECPS64", LIEF::assembly::aarch64::OPCODE::FRECPS64) + .value("FRECPS_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FRECPS_ZZZ_D) + .value("FRECPS_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FRECPS_ZZZ_H) + .value("FRECPS_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FRECPS_ZZZ_S) + .value("FRECPSv2f32", LIEF::assembly::aarch64::OPCODE::FRECPSv2f32) + .value("FRECPSv2f64", LIEF::assembly::aarch64::OPCODE::FRECPSv2f64) + .value("FRECPSv4f16", LIEF::assembly::aarch64::OPCODE::FRECPSv4f16) + .value("FRECPSv4f32", LIEF::assembly::aarch64::OPCODE::FRECPSv4f32) + .value("FRECPSv8f16", LIEF::assembly::aarch64::OPCODE::FRECPSv8f16) + .value("FRECPX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_D) + .value("FRECPX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_H) + .value("FRECPX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPmZ_S) + .value("FRECPX_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPzZ_D) + .value("FRECPX_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPzZ_H) + .value("FRECPX_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRECPX_ZPzZ_S) + .value("FRECPXv1f16", LIEF::assembly::aarch64::OPCODE::FRECPXv1f16) + .value("FRECPXv1i32", LIEF::assembly::aarch64::OPCODE::FRECPXv1i32) + .value("FRECPXv1i64", LIEF::assembly::aarch64::OPCODE::FRECPXv1i64) + .value("FRINT32XDr", LIEF::assembly::aarch64::OPCODE::FRINT32XDr) + .value("FRINT32XSr", LIEF::assembly::aarch64::OPCODE::FRINT32XSr) + .value("FRINT32X_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPmZ_D) + .value("FRINT32X_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPmZ_S) + .value("FRINT32X_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPzZ_D) + .value("FRINT32X_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINT32X_ZPzZ_S) + .value("FRINT32Xv2f32", LIEF::assembly::aarch64::OPCODE::FRINT32Xv2f32) + .value("FRINT32Xv2f64", LIEF::assembly::aarch64::OPCODE::FRINT32Xv2f64) + .value("FRINT32Xv4f32", LIEF::assembly::aarch64::OPCODE::FRINT32Xv4f32) + .value("FRINT32ZDr", LIEF::assembly::aarch64::OPCODE::FRINT32ZDr) + .value("FRINT32ZSr", LIEF::assembly::aarch64::OPCODE::FRINT32ZSr) + .value("FRINT32Z_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPmZ_D) + .value("FRINT32Z_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPmZ_S) + .value("FRINT32Z_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPzZ_D) + .value("FRINT32Z_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINT32Z_ZPzZ_S) + .value("FRINT32Zv2f32", LIEF::assembly::aarch64::OPCODE::FRINT32Zv2f32) + .value("FRINT32Zv2f64", LIEF::assembly::aarch64::OPCODE::FRINT32Zv2f64) + .value("FRINT32Zv4f32", LIEF::assembly::aarch64::OPCODE::FRINT32Zv4f32) + .value("FRINT64XDr", LIEF::assembly::aarch64::OPCODE::FRINT64XDr) + .value("FRINT64XSr", LIEF::assembly::aarch64::OPCODE::FRINT64XSr) + .value("FRINT64X_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPmZ_D) + .value("FRINT64X_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPmZ_S) + .value("FRINT64X_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPzZ_D) + .value("FRINT64X_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINT64X_ZPzZ_S) + .value("FRINT64Xv2f32", LIEF::assembly::aarch64::OPCODE::FRINT64Xv2f32) + .value("FRINT64Xv2f64", LIEF::assembly::aarch64::OPCODE::FRINT64Xv2f64) + .value("FRINT64Xv4f32", LIEF::assembly::aarch64::OPCODE::FRINT64Xv4f32) + .value("FRINT64ZDr", LIEF::assembly::aarch64::OPCODE::FRINT64ZDr) + .value("FRINT64ZSr", LIEF::assembly::aarch64::OPCODE::FRINT64ZSr) + .value("FRINT64Z_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPmZ_D) + .value("FRINT64Z_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPmZ_S) + .value("FRINT64Z_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPzZ_D) + .value("FRINT64Z_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINT64Z_ZPzZ_S) + .value("FRINT64Zv2f32", LIEF::assembly::aarch64::OPCODE::FRINT64Zv2f32) + .value("FRINT64Zv2f64", LIEF::assembly::aarch64::OPCODE::FRINT64Zv2f64) + .value("FRINT64Zv4f32", LIEF::assembly::aarch64::OPCODE::FRINT64Zv4f32) + .value("FRINTADr", LIEF::assembly::aarch64::OPCODE::FRINTADr) + .value("FRINTAHr", LIEF::assembly::aarch64::OPCODE::FRINTAHr) + .value("FRINTASr", LIEF::assembly::aarch64::OPCODE::FRINTASr) + .value("FRINTA_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FRINTA_2Z2Z_S) + .value("FRINTA_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FRINTA_4Z4Z_S) + .value("FRINTA_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_D) + .value("FRINTA_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_H) + .value("FRINTA_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPmZ_S) + .value("FRINTA_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPzZ_D) + .value("FRINTA_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPzZ_H) + .value("FRINTA_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTA_ZPzZ_S) + .value("FRINTAv2f32", LIEF::assembly::aarch64::OPCODE::FRINTAv2f32) + .value("FRINTAv2f64", LIEF::assembly::aarch64::OPCODE::FRINTAv2f64) + .value("FRINTAv4f16", LIEF::assembly::aarch64::OPCODE::FRINTAv4f16) + .value("FRINTAv4f32", LIEF::assembly::aarch64::OPCODE::FRINTAv4f32) + .value("FRINTAv8f16", LIEF::assembly::aarch64::OPCODE::FRINTAv8f16) + .value("FRINTIDr", LIEF::assembly::aarch64::OPCODE::FRINTIDr) + .value("FRINTIHr", LIEF::assembly::aarch64::OPCODE::FRINTIHr) + .value("FRINTISr", LIEF::assembly::aarch64::OPCODE::FRINTISr) + .value("FRINTI_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_D) + .value("FRINTI_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_H) + .value("FRINTI_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPmZ_S) + .value("FRINTI_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPzZ_D) + .value("FRINTI_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPzZ_H) + .value("FRINTI_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTI_ZPzZ_S) + .value("FRINTIv2f32", LIEF::assembly::aarch64::OPCODE::FRINTIv2f32) + .value("FRINTIv2f64", LIEF::assembly::aarch64::OPCODE::FRINTIv2f64) + .value("FRINTIv4f16", LIEF::assembly::aarch64::OPCODE::FRINTIv4f16) + .value("FRINTIv4f32", LIEF::assembly::aarch64::OPCODE::FRINTIv4f32) + .value("FRINTIv8f16", LIEF::assembly::aarch64::OPCODE::FRINTIv8f16) + .value("FRINTMDr", LIEF::assembly::aarch64::OPCODE::FRINTMDr) + .value("FRINTMHr", LIEF::assembly::aarch64::OPCODE::FRINTMHr) + .value("FRINTMSr", LIEF::assembly::aarch64::OPCODE::FRINTMSr) + .value("FRINTM_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FRINTM_2Z2Z_S) + .value("FRINTM_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FRINTM_4Z4Z_S) + .value("FRINTM_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_D) + .value("FRINTM_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_H) + .value("FRINTM_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPmZ_S) + .value("FRINTM_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPzZ_D) + .value("FRINTM_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPzZ_H) + .value("FRINTM_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTM_ZPzZ_S) + .value("FRINTMv2f32", LIEF::assembly::aarch64::OPCODE::FRINTMv2f32) + .value("FRINTMv2f64", LIEF::assembly::aarch64::OPCODE::FRINTMv2f64) + .value("FRINTMv4f16", LIEF::assembly::aarch64::OPCODE::FRINTMv4f16) + .value("FRINTMv4f32", LIEF::assembly::aarch64::OPCODE::FRINTMv4f32) + .value("FRINTMv8f16", LIEF::assembly::aarch64::OPCODE::FRINTMv8f16) + .value("FRINTNDr", LIEF::assembly::aarch64::OPCODE::FRINTNDr) + .value("FRINTNHr", LIEF::assembly::aarch64::OPCODE::FRINTNHr) + .value("FRINTNSr", LIEF::assembly::aarch64::OPCODE::FRINTNSr) + .value("FRINTN_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FRINTN_2Z2Z_S) + .value("FRINTN_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FRINTN_4Z4Z_S) + .value("FRINTN_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_D) + .value("FRINTN_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_H) + .value("FRINTN_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPmZ_S) + .value("FRINTN_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPzZ_D) + .value("FRINTN_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPzZ_H) + .value("FRINTN_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTN_ZPzZ_S) + .value("FRINTNv2f32", LIEF::assembly::aarch64::OPCODE::FRINTNv2f32) + .value("FRINTNv2f64", LIEF::assembly::aarch64::OPCODE::FRINTNv2f64) + .value("FRINTNv4f16", LIEF::assembly::aarch64::OPCODE::FRINTNv4f16) + .value("FRINTNv4f32", LIEF::assembly::aarch64::OPCODE::FRINTNv4f32) + .value("FRINTNv8f16", LIEF::assembly::aarch64::OPCODE::FRINTNv8f16) + .value("FRINTPDr", LIEF::assembly::aarch64::OPCODE::FRINTPDr) + .value("FRINTPHr", LIEF::assembly::aarch64::OPCODE::FRINTPHr) + .value("FRINTPSr", LIEF::assembly::aarch64::OPCODE::FRINTPSr) + .value("FRINTP_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FRINTP_2Z2Z_S) + .value("FRINTP_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FRINTP_4Z4Z_S) + .value("FRINTP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_D) + .value("FRINTP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_H) + .value("FRINTP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPmZ_S) + .value("FRINTP_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPzZ_D) + .value("FRINTP_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPzZ_H) + .value("FRINTP_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTP_ZPzZ_S) + .value("FRINTPv2f32", LIEF::assembly::aarch64::OPCODE::FRINTPv2f32) + .value("FRINTPv2f64", LIEF::assembly::aarch64::OPCODE::FRINTPv2f64) + .value("FRINTPv4f16", LIEF::assembly::aarch64::OPCODE::FRINTPv4f16) + .value("FRINTPv4f32", LIEF::assembly::aarch64::OPCODE::FRINTPv4f32) + .value("FRINTPv8f16", LIEF::assembly::aarch64::OPCODE::FRINTPv8f16) + .value("FRINTXDr", LIEF::assembly::aarch64::OPCODE::FRINTXDr) + .value("FRINTXHr", LIEF::assembly::aarch64::OPCODE::FRINTXHr) + .value("FRINTXSr", LIEF::assembly::aarch64::OPCODE::FRINTXSr) + .value("FRINTX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_D) + .value("FRINTX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_H) + .value("FRINTX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPmZ_S) + .value("FRINTX_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPzZ_D) + .value("FRINTX_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPzZ_H) + .value("FRINTX_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTX_ZPzZ_S) + .value("FRINTXv2f32", LIEF::assembly::aarch64::OPCODE::FRINTXv2f32) + .value("FRINTXv2f64", LIEF::assembly::aarch64::OPCODE::FRINTXv2f64) + .value("FRINTXv4f16", LIEF::assembly::aarch64::OPCODE::FRINTXv4f16) + .value("FRINTXv4f32", LIEF::assembly::aarch64::OPCODE::FRINTXv4f32) + .value("FRINTXv8f16", LIEF::assembly::aarch64::OPCODE::FRINTXv8f16) + .value("FRINTZDr", LIEF::assembly::aarch64::OPCODE::FRINTZDr) + .value("FRINTZHr", LIEF::assembly::aarch64::OPCODE::FRINTZHr) + .value("FRINTZSr", LIEF::assembly::aarch64::OPCODE::FRINTZSr) + .value("FRINTZ_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_D) + .value("FRINTZ_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_H) + .value("FRINTZ_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPmZ_S) + .value("FRINTZ_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPzZ_D) + .value("FRINTZ_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPzZ_H) + .value("FRINTZ_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::FRINTZ_ZPzZ_S) + .value("FRINTZv2f32", LIEF::assembly::aarch64::OPCODE::FRINTZv2f32) + .value("FRINTZv2f64", LIEF::assembly::aarch64::OPCODE::FRINTZv2f64) + .value("FRINTZv4f16", LIEF::assembly::aarch64::OPCODE::FRINTZv4f16) + .value("FRINTZv4f32", LIEF::assembly::aarch64::OPCODE::FRINTZv4f32) + .value("FRINTZv8f16", LIEF::assembly::aarch64::OPCODE::FRINTZv8f16) + .value("FRSQRTE_ZZ_D", LIEF::assembly::aarch64::OPCODE::FRSQRTE_ZZ_D) + .value("FRSQRTE_ZZ_H", LIEF::assembly::aarch64::OPCODE::FRSQRTE_ZZ_H) + .value("FRSQRTE_ZZ_S", LIEF::assembly::aarch64::OPCODE::FRSQRTE_ZZ_S) + .value("FRSQRTEv1f16", LIEF::assembly::aarch64::OPCODE::FRSQRTEv1f16) + .value("FRSQRTEv1i32", LIEF::assembly::aarch64::OPCODE::FRSQRTEv1i32) + .value("FRSQRTEv1i64", LIEF::assembly::aarch64::OPCODE::FRSQRTEv1i64) + .value("FRSQRTEv2f32", LIEF::assembly::aarch64::OPCODE::FRSQRTEv2f32) + .value("FRSQRTEv2f64", LIEF::assembly::aarch64::OPCODE::FRSQRTEv2f64) + .value("FRSQRTEv4f16", LIEF::assembly::aarch64::OPCODE::FRSQRTEv4f16) + .value("FRSQRTEv4f32", LIEF::assembly::aarch64::OPCODE::FRSQRTEv4f32) + .value("FRSQRTEv8f16", LIEF::assembly::aarch64::OPCODE::FRSQRTEv8f16) + .value("FRSQRTS16", LIEF::assembly::aarch64::OPCODE::FRSQRTS16) + .value("FRSQRTS32", LIEF::assembly::aarch64::OPCODE::FRSQRTS32) + .value("FRSQRTS64", LIEF::assembly::aarch64::OPCODE::FRSQRTS64) + .value("FRSQRTS_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FRSQRTS_ZZZ_D) + .value("FRSQRTS_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FRSQRTS_ZZZ_H) + .value("FRSQRTS_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FRSQRTS_ZZZ_S) + .value("FRSQRTSv2f32", LIEF::assembly::aarch64::OPCODE::FRSQRTSv2f32) + .value("FRSQRTSv2f64", LIEF::assembly::aarch64::OPCODE::FRSQRTSv2f64) + .value("FRSQRTSv4f16", LIEF::assembly::aarch64::OPCODE::FRSQRTSv4f16) + .value("FRSQRTSv4f32", LIEF::assembly::aarch64::OPCODE::FRSQRTSv4f32) + .value("FRSQRTSv8f16", LIEF::assembly::aarch64::OPCODE::FRSQRTSv8f16) + .value("FSCALE_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::FSCALE_2Z2Z_D) + .value("FSCALE_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::FSCALE_2Z2Z_H) + .value("FSCALE_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::FSCALE_2Z2Z_S) + .value("FSCALE_2ZZ_D", LIEF::assembly::aarch64::OPCODE::FSCALE_2ZZ_D) + .value("FSCALE_2ZZ_H", LIEF::assembly::aarch64::OPCODE::FSCALE_2ZZ_H) + .value("FSCALE_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FSCALE_2ZZ_S) + .value("FSCALE_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FSCALE_4Z4Z_D) + .value("FSCALE_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FSCALE_4Z4Z_H) + .value("FSCALE_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FSCALE_4Z4Z_S) + .value("FSCALE_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FSCALE_4ZZ_D) + .value("FSCALE_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FSCALE_4ZZ_H) + .value("FSCALE_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FSCALE_4ZZ_S) + .value("FSCALE_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FSCALE_ZPmZ_D) + .value("FSCALE_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FSCALE_ZPmZ_H) + .value("FSCALE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSCALE_ZPmZ_S) + .value("FSCALEv2f32", LIEF::assembly::aarch64::OPCODE::FSCALEv2f32) + .value("FSCALEv2f64", LIEF::assembly::aarch64::OPCODE::FSCALEv2f64) + .value("FSCALEv4f16", LIEF::assembly::aarch64::OPCODE::FSCALEv4f16) + .value("FSCALEv4f32", LIEF::assembly::aarch64::OPCODE::FSCALEv4f32) + .value("FSCALEv8f16", LIEF::assembly::aarch64::OPCODE::FSCALEv8f16) + .value("FSQRTDr", LIEF::assembly::aarch64::OPCODE::FSQRTDr) + .value("FSQRTHr", LIEF::assembly::aarch64::OPCODE::FSQRTHr) + .value("FSQRTSr", LIEF::assembly::aarch64::OPCODE::FSQRTSr) + .value("FSQRT_ZPZz_D", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPZz_D) + .value("FSQRT_ZPZz_H", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPZz_H) + .value("FSQRT_ZPZz_S", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPZz_S) + .value("FSQRT_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_D) + .value("FSQRT_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_H) + .value("FSQRT_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSQRT_ZPmZ_S) + .value("FSQRTv2f32", LIEF::assembly::aarch64::OPCODE::FSQRTv2f32) + .value("FSQRTv2f64", LIEF::assembly::aarch64::OPCODE::FSQRTv2f64) + .value("FSQRTv4f16", LIEF::assembly::aarch64::OPCODE::FSQRTv4f16) + .value("FSQRTv4f32", LIEF::assembly::aarch64::OPCODE::FSQRTv4f32) + .value("FSQRTv8f16", LIEF::assembly::aarch64::OPCODE::FSQRTv8f16) + .value("FSUBDrr", LIEF::assembly::aarch64::OPCODE::FSUBDrr) + .value("FSUBHrr", LIEF::assembly::aarch64::OPCODE::FSUBHrr) + .value("FSUBR_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmI_D) + .value("FSUBR_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmI_H) + .value("FSUBR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmI_S) + .value("FSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_D) + .value("FSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_H) + .value("FSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_S) + .value("FSUBSrr", LIEF::assembly::aarch64::OPCODE::FSUBSrr) + .value("FSUB_VG2_M2Z_D", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_D) + .value("FSUB_VG2_M2Z_H", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_H) + .value("FSUB_VG2_M2Z_S", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_S) + .value("FSUB_VG4_M4Z_D", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_D) + .value("FSUB_VG4_M4Z_H", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_H) + .value("FSUB_VG4_M4Z_S", LIEF::assembly::aarch64::OPCODE::FSUB_VG4_M4Z_S) + .value("FSUB_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmI_D) + .value("FSUB_ZPmI_H", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmI_H) + .value("FSUB_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmI_S) + .value("FSUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmZ_D) + .value("FSUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmZ_H) + .value("FSUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSUB_ZPmZ_S) + .value("FSUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FSUB_ZZZ_D) + .value("FSUB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FSUB_ZZZ_H) + .value("FSUB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FSUB_ZZZ_S) + .value("FSUBv2f32", LIEF::assembly::aarch64::OPCODE::FSUBv2f32) + .value("FSUBv2f64", LIEF::assembly::aarch64::OPCODE::FSUBv2f64) + .value("FSUBv4f16", LIEF::assembly::aarch64::OPCODE::FSUBv4f16) + .value("FSUBv4f32", LIEF::assembly::aarch64::OPCODE::FSUBv4f32) + .value("FSUBv8f16", LIEF::assembly::aarch64::OPCODE::FSUBv8f16) + .value("FTMAD_ZZI_D", LIEF::assembly::aarch64::OPCODE::FTMAD_ZZI_D) + .value("FTMAD_ZZI_H", LIEF::assembly::aarch64::OPCODE::FTMAD_ZZI_H) + .value("FTMAD_ZZI_S", LIEF::assembly::aarch64::OPCODE::FTMAD_ZZI_S) + .value("FTMOPA_M2ZZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_BtoH) + .value("FTMOPA_M2ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_BtoS) + .value("FTMOPA_M2ZZZI_HtoH", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_HtoH) + .value("FTMOPA_M2ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_HtoS) + .value("FTMOPA_M2ZZZI_StoS", LIEF::assembly::aarch64::OPCODE::FTMOPA_M2ZZZI_StoS) + .value("FTSMUL_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FTSMUL_ZZZ_D) + .value("FTSMUL_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FTSMUL_ZZZ_H) + .value("FTSMUL_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FTSMUL_ZZZ_S) + .value("FTSSEL_ZZZ_D", LIEF::assembly::aarch64::OPCODE::FTSSEL_ZZZ_D) + .value("FTSSEL_ZZZ_H", LIEF::assembly::aarch64::OPCODE::FTSSEL_ZZZ_H) + .value("FTSSEL_ZZZ_S", LIEF::assembly::aarch64::OPCODE::FTSSEL_ZZZ_S) + .value("FVDOTB_VG4_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FVDOTB_VG4_M2ZZI_BtoS) + .value("FVDOTT_VG4_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FVDOTT_VG4_M2ZZI_BtoS) + .value("FVDOT_VG2_M2ZZI_BtoH", LIEF::assembly::aarch64::OPCODE::FVDOT_VG2_M2ZZI_BtoH) + .value("FVDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::FVDOT_VG2_M2ZZI_HtoS) + .value("GCSPOPCX", LIEF::assembly::aarch64::OPCODE::GCSPOPCX) + .value("GCSPOPM", LIEF::assembly::aarch64::OPCODE::GCSPOPM) + .value("GCSPOPX", LIEF::assembly::aarch64::OPCODE::GCSPOPX) + .value("GCSPUSHM", LIEF::assembly::aarch64::OPCODE::GCSPUSHM) + .value("GCSPUSHX", LIEF::assembly::aarch64::OPCODE::GCSPUSHX) + .value("GCSSS1", LIEF::assembly::aarch64::OPCODE::GCSSS1) + .value("GCSSS2", LIEF::assembly::aarch64::OPCODE::GCSSS2) + .value("GCSSTR", LIEF::assembly::aarch64::OPCODE::GCSSTR) + .value("GCSSTTR", LIEF::assembly::aarch64::OPCODE::GCSSTTR) + .value("GLD1B_D", LIEF::assembly::aarch64::OPCODE::GLD1B_D) + .value("GLD1B_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1B_D_IMM) + .value("GLD1B_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1B_D_SXTW) + .value("GLD1B_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1B_D_UXTW) + .value("GLD1B_S_IMM", LIEF::assembly::aarch64::OPCODE::GLD1B_S_IMM) + .value("GLD1B_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1B_S_SXTW) + .value("GLD1B_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1B_S_UXTW) + .value("GLD1D", LIEF::assembly::aarch64::OPCODE::GLD1D) + .value("GLD1D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1D_IMM) + .value("GLD1D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_SCALED) + .value("GLD1D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1D_SXTW) + .value("GLD1D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_SXTW_SCALED) + .value("GLD1D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW); + opcodes.value("GLD1D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW_SCALED) + .value("GLD1H_D", LIEF::assembly::aarch64::OPCODE::GLD1H_D) + .value("GLD1H_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1H_D_IMM) + .value("GLD1H_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_D_SCALED) + .value("GLD1H_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1H_D_SXTW) + .value("GLD1H_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_D_SXTW_SCALED) + .value("GLD1H_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1H_D_UXTW) + .value("GLD1H_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_D_UXTW_SCALED) + .value("GLD1H_S_IMM", LIEF::assembly::aarch64::OPCODE::GLD1H_S_IMM) + .value("GLD1H_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1H_S_SXTW) + .value("GLD1H_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_S_SXTW_SCALED) + .value("GLD1H_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1H_S_UXTW) + .value("GLD1H_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_S_UXTW_SCALED) + .value("GLD1Q", LIEF::assembly::aarch64::OPCODE::GLD1Q) + .value("GLD1SB_D", LIEF::assembly::aarch64::OPCODE::GLD1SB_D) + .value("GLD1SB_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1SB_D_IMM) + .value("GLD1SB_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1SB_D_SXTW) + .value("GLD1SB_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1SB_D_UXTW) + .value("GLD1SB_S_IMM", LIEF::assembly::aarch64::OPCODE::GLD1SB_S_IMM) + .value("GLD1SB_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1SB_S_SXTW) + .value("GLD1SB_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1SB_S_UXTW) + .value("GLD1SH_D", LIEF::assembly::aarch64::OPCODE::GLD1SH_D) + .value("GLD1SH_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_IMM) + .value("GLD1SH_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_SCALED) + .value("GLD1SH_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_SXTW) + .value("GLD1SH_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_SXTW_SCALED) + .value("GLD1SH_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_UXTW) + .value("GLD1SH_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SH_D_UXTW_SCALED) + .value("GLD1SH_S_IMM", LIEF::assembly::aarch64::OPCODE::GLD1SH_S_IMM) + .value("GLD1SH_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1SH_S_SXTW) + .value("GLD1SH_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SH_S_SXTW_SCALED) + .value("GLD1SH_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1SH_S_UXTW) + .value("GLD1SH_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SH_S_UXTW_SCALED) + .value("GLD1SW_D", LIEF::assembly::aarch64::OPCODE::GLD1SW_D) + .value("GLD1SW_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_IMM) + .value("GLD1SW_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_SCALED) + .value("GLD1SW_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_SXTW) + .value("GLD1SW_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_SXTW_SCALED) + .value("GLD1SW_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_UXTW) + .value("GLD1SW_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1SW_D_UXTW_SCALED) + .value("GLD1W_D", LIEF::assembly::aarch64::OPCODE::GLD1W_D) + .value("GLD1W_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1W_D_IMM) + .value("GLD1W_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1W_D_SCALED) + .value("GLD1W_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1W_D_SXTW) + .value("GLD1W_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1W_D_SXTW_SCALED) + .value("GLD1W_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1W_D_UXTW) + .value("GLD1W_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1W_D_UXTW_SCALED) + .value("GLD1W_IMM", LIEF::assembly::aarch64::OPCODE::GLD1W_IMM) + .value("GLD1W_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1W_SXTW) + .value("GLD1W_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1W_SXTW_SCALED) + .value("GLD1W_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1W_UXTW) + .value("GLD1W_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1W_UXTW_SCALED) + .value("GLDFF1B_D", LIEF::assembly::aarch64::OPCODE::GLDFF1B_D) + .value("GLDFF1B_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1B_D_IMM) + .value("GLDFF1B_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1B_D_SXTW) + .value("GLDFF1B_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1B_D_UXTW) + .value("GLDFF1B_S_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1B_S_IMM) + .value("GLDFF1B_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1B_S_SXTW) + .value("GLDFF1B_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1B_S_UXTW) + .value("GLDFF1D", LIEF::assembly::aarch64::OPCODE::GLDFF1D) + .value("GLDFF1D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1D_IMM) + .value("GLDFF1D_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1D_SCALED) + .value("GLDFF1D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1D_SXTW) + .value("GLDFF1D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1D_SXTW_SCALED) + .value("GLDFF1D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1D_UXTW) + .value("GLDFF1D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1D_UXTW_SCALED) + .value("GLDFF1H_D", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D) + .value("GLDFF1H_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_IMM) + .value("GLDFF1H_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_SCALED) + .value("GLDFF1H_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_SXTW) + .value("GLDFF1H_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_SXTW_SCALED) + .value("GLDFF1H_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_UXTW) + .value("GLDFF1H_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1H_D_UXTW_SCALED) + .value("GLDFF1H_S_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1H_S_IMM) + .value("GLDFF1H_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1H_S_SXTW) + .value("GLDFF1H_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1H_S_SXTW_SCALED) + .value("GLDFF1H_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1H_S_UXTW) + .value("GLDFF1H_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1H_S_UXTW_SCALED) + .value("GLDFF1SB_D", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_D) + .value("GLDFF1SB_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_D_IMM) + .value("GLDFF1SB_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_D_SXTW) + .value("GLDFF1SB_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_D_UXTW) + .value("GLDFF1SB_S_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_S_IMM) + .value("GLDFF1SB_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_S_SXTW) + .value("GLDFF1SB_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SB_S_UXTW) + .value("GLDFF1SH_D", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D) + .value("GLDFF1SH_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_IMM) + .value("GLDFF1SH_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_SCALED) + .value("GLDFF1SH_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_SXTW) + .value("GLDFF1SH_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_SXTW_SCALED) + .value("GLDFF1SH_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_UXTW) + .value("GLDFF1SH_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_D_UXTW_SCALED) + .value("GLDFF1SH_S_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_S_IMM) + .value("GLDFF1SH_S_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_S_SXTW) + .value("GLDFF1SH_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_S_SXTW_SCALED) + .value("GLDFF1SH_S_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_S_UXTW) + .value("GLDFF1SH_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SH_S_UXTW_SCALED) + .value("GLDFF1SW_D", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D) + .value("GLDFF1SW_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_IMM) + .value("GLDFF1SW_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_SCALED) + .value("GLDFF1SW_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_SXTW) + .value("GLDFF1SW_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_SXTW_SCALED) + .value("GLDFF1SW_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_UXTW) + .value("GLDFF1SW_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1SW_D_UXTW_SCALED) + .value("GLDFF1W_D", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D) + .value("GLDFF1W_D_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_IMM) + .value("GLDFF1W_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_SCALED) + .value("GLDFF1W_D_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_SXTW) + .value("GLDFF1W_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_SXTW_SCALED) + .value("GLDFF1W_D_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_UXTW) + .value("GLDFF1W_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_D_UXTW_SCALED) + .value("GLDFF1W_IMM", LIEF::assembly::aarch64::OPCODE::GLDFF1W_IMM) + .value("GLDFF1W_SXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1W_SXTW) + .value("GLDFF1W_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_SXTW_SCALED) + .value("GLDFF1W_UXTW", LIEF::assembly::aarch64::OPCODE::GLDFF1W_UXTW) + .value("GLDFF1W_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_UXTW_SCALED) + .value("GMI", LIEF::assembly::aarch64::OPCODE::GMI) + .value("HINT", LIEF::assembly::aarch64::OPCODE::HINT) + .value("HISTCNT_ZPzZZ_D", LIEF::assembly::aarch64::OPCODE::HISTCNT_ZPzZZ_D) + .value("HISTCNT_ZPzZZ_S", LIEF::assembly::aarch64::OPCODE::HISTCNT_ZPzZZ_S) + .value("HISTSEG_ZZZ", LIEF::assembly::aarch64::OPCODE::HISTSEG_ZZZ) + .value("HLT", LIEF::assembly::aarch64::OPCODE::HLT) + .value("HVC", LIEF::assembly::aarch64::OPCODE::HVC) + .value("INCB_XPiI", LIEF::assembly::aarch64::OPCODE::INCB_XPiI) + .value("INCD_XPiI", LIEF::assembly::aarch64::OPCODE::INCD_XPiI) + .value("INCD_ZPiI", LIEF::assembly::aarch64::OPCODE::INCD_ZPiI) + .value("INCH_XPiI", LIEF::assembly::aarch64::OPCODE::INCH_XPiI) + .value("INCH_ZPiI", LIEF::assembly::aarch64::OPCODE::INCH_ZPiI) + .value("INCP_XP_B", LIEF::assembly::aarch64::OPCODE::INCP_XP_B) + .value("INCP_XP_D", LIEF::assembly::aarch64::OPCODE::INCP_XP_D) + .value("INCP_XP_H", LIEF::assembly::aarch64::OPCODE::INCP_XP_H) + .value("INCP_XP_S", LIEF::assembly::aarch64::OPCODE::INCP_XP_S) + .value("INCP_ZP_D", LIEF::assembly::aarch64::OPCODE::INCP_ZP_D) + .value("INCP_ZP_H", LIEF::assembly::aarch64::OPCODE::INCP_ZP_H) + .value("INCP_ZP_S", LIEF::assembly::aarch64::OPCODE::INCP_ZP_S) + .value("INCW_XPiI", LIEF::assembly::aarch64::OPCODE::INCW_XPiI) + .value("INCW_ZPiI", LIEF::assembly::aarch64::OPCODE::INCW_ZPiI) + .value("INDEX_II_B", LIEF::assembly::aarch64::OPCODE::INDEX_II_B) + .value("INDEX_II_D", LIEF::assembly::aarch64::OPCODE::INDEX_II_D) + .value("INDEX_II_H", LIEF::assembly::aarch64::OPCODE::INDEX_II_H) + .value("INDEX_II_S", LIEF::assembly::aarch64::OPCODE::INDEX_II_S) + .value("INDEX_IR_B", LIEF::assembly::aarch64::OPCODE::INDEX_IR_B) + .value("INDEX_IR_D", LIEF::assembly::aarch64::OPCODE::INDEX_IR_D) + .value("INDEX_IR_H", LIEF::assembly::aarch64::OPCODE::INDEX_IR_H) + .value("INDEX_IR_S", LIEF::assembly::aarch64::OPCODE::INDEX_IR_S) + .value("INDEX_RI_B", LIEF::assembly::aarch64::OPCODE::INDEX_RI_B) + .value("INDEX_RI_D", LIEF::assembly::aarch64::OPCODE::INDEX_RI_D) + .value("INDEX_RI_H", LIEF::assembly::aarch64::OPCODE::INDEX_RI_H) + .value("INDEX_RI_S", LIEF::assembly::aarch64::OPCODE::INDEX_RI_S) + .value("INDEX_RR_B", LIEF::assembly::aarch64::OPCODE::INDEX_RR_B) + .value("INDEX_RR_D", LIEF::assembly::aarch64::OPCODE::INDEX_RR_D) + .value("INDEX_RR_H", LIEF::assembly::aarch64::OPCODE::INDEX_RR_H) + .value("INDEX_RR_S", LIEF::assembly::aarch64::OPCODE::INDEX_RR_S) + .value("INSERT_MXIPZ_H_B", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_B) + .value("INSERT_MXIPZ_H_D", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_D) + .value("INSERT_MXIPZ_H_H", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_H) + .value("INSERT_MXIPZ_H_Q", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_Q) + .value("INSERT_MXIPZ_H_S", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_H_S) + .value("INSERT_MXIPZ_V_B", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_B) + .value("INSERT_MXIPZ_V_D", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_D) + .value("INSERT_MXIPZ_V_H", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_H) + .value("INSERT_MXIPZ_V_Q", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_Q) + .value("INSERT_MXIPZ_V_S", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_S) + .value("INSR_ZR_B", LIEF::assembly::aarch64::OPCODE::INSR_ZR_B) + .value("INSR_ZR_D", LIEF::assembly::aarch64::OPCODE::INSR_ZR_D) + .value("INSR_ZR_H", LIEF::assembly::aarch64::OPCODE::INSR_ZR_H) + .value("INSR_ZR_S", LIEF::assembly::aarch64::OPCODE::INSR_ZR_S) + .value("INSR_ZV_B", LIEF::assembly::aarch64::OPCODE::INSR_ZV_B) + .value("INSR_ZV_D", LIEF::assembly::aarch64::OPCODE::INSR_ZV_D) + .value("INSR_ZV_H", LIEF::assembly::aarch64::OPCODE::INSR_ZV_H) + .value("INSR_ZV_S", LIEF::assembly::aarch64::OPCODE::INSR_ZV_S) + .value("INSvi16gpr", LIEF::assembly::aarch64::OPCODE::INSvi16gpr) + .value("INSvi16lane", LIEF::assembly::aarch64::OPCODE::INSvi16lane) + .value("INSvi32gpr", LIEF::assembly::aarch64::OPCODE::INSvi32gpr) + .value("INSvi32lane", LIEF::assembly::aarch64::OPCODE::INSvi32lane) + .value("INSvi64gpr", LIEF::assembly::aarch64::OPCODE::INSvi64gpr) + .value("INSvi64lane", LIEF::assembly::aarch64::OPCODE::INSvi64lane) + .value("INSvi8gpr", LIEF::assembly::aarch64::OPCODE::INSvi8gpr) + .value("INSvi8lane", LIEF::assembly::aarch64::OPCODE::INSvi8lane) + .value("IRG", LIEF::assembly::aarch64::OPCODE::IRG) + .value("ISB", LIEF::assembly::aarch64::OPCODE::ISB) + .value("LASTA_RPZ_B", LIEF::assembly::aarch64::OPCODE::LASTA_RPZ_B) + .value("LASTA_RPZ_D", LIEF::assembly::aarch64::OPCODE::LASTA_RPZ_D) + .value("LASTA_RPZ_H", LIEF::assembly::aarch64::OPCODE::LASTA_RPZ_H) + .value("LASTA_RPZ_S", LIEF::assembly::aarch64::OPCODE::LASTA_RPZ_S) + .value("LASTA_VPZ_B", LIEF::assembly::aarch64::OPCODE::LASTA_VPZ_B) + .value("LASTA_VPZ_D", LIEF::assembly::aarch64::OPCODE::LASTA_VPZ_D) + .value("LASTA_VPZ_H", LIEF::assembly::aarch64::OPCODE::LASTA_VPZ_H) + .value("LASTA_VPZ_S", LIEF::assembly::aarch64::OPCODE::LASTA_VPZ_S) + .value("LASTB_RPZ_B", LIEF::assembly::aarch64::OPCODE::LASTB_RPZ_B) + .value("LASTB_RPZ_D", LIEF::assembly::aarch64::OPCODE::LASTB_RPZ_D) + .value("LASTB_RPZ_H", LIEF::assembly::aarch64::OPCODE::LASTB_RPZ_H) + .value("LASTB_RPZ_S", LIEF::assembly::aarch64::OPCODE::LASTB_RPZ_S) + .value("LASTB_VPZ_B", LIEF::assembly::aarch64::OPCODE::LASTB_VPZ_B) + .value("LASTB_VPZ_D", LIEF::assembly::aarch64::OPCODE::LASTB_VPZ_D) + .value("LASTB_VPZ_H", LIEF::assembly::aarch64::OPCODE::LASTB_VPZ_H) + .value("LASTB_VPZ_S", LIEF::assembly::aarch64::OPCODE::LASTB_VPZ_S) + .value("LASTP_XPP_B", LIEF::assembly::aarch64::OPCODE::LASTP_XPP_B) + .value("LASTP_XPP_D", LIEF::assembly::aarch64::OPCODE::LASTP_XPP_D) + .value("LASTP_XPP_H", LIEF::assembly::aarch64::OPCODE::LASTP_XPP_H) + .value("LASTP_XPP_S", LIEF::assembly::aarch64::OPCODE::LASTP_XPP_S) + .value("LD1B", LIEF::assembly::aarch64::OPCODE::LD1B) + .value("LD1B_2Z", LIEF::assembly::aarch64::OPCODE::LD1B_2Z) + .value("LD1B_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_2Z_IMM) + .value("LD1B_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1B_2Z_STRIDED) + .value("LD1B_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_2Z_STRIDED_IMM) + .value("LD1B_4Z", LIEF::assembly::aarch64::OPCODE::LD1B_4Z) + .value("LD1B_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_4Z_IMM) + .value("LD1B_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1B_4Z_STRIDED) + .value("LD1B_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_4Z_STRIDED_IMM) + .value("LD1B_D", LIEF::assembly::aarch64::OPCODE::LD1B_D) + .value("LD1B_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_D_IMM) + .value("LD1B_H", LIEF::assembly::aarch64::OPCODE::LD1B_H) + .value("LD1B_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_H_IMM) + .value("LD1B_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_IMM) + .value("LD1B_S", LIEF::assembly::aarch64::OPCODE::LD1B_S) + .value("LD1B_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1B_S_IMM) + .value("LD1D", LIEF::assembly::aarch64::OPCODE::LD1D) + .value("LD1D_2Z", LIEF::assembly::aarch64::OPCODE::LD1D_2Z) + .value("LD1D_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_2Z_IMM) + .value("LD1D_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1D_2Z_STRIDED) + .value("LD1D_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_2Z_STRIDED_IMM) + .value("LD1D_4Z", LIEF::assembly::aarch64::OPCODE::LD1D_4Z) + .value("LD1D_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_4Z_IMM) + .value("LD1D_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1D_4Z_STRIDED) + .value("LD1D_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_4Z_STRIDED_IMM) + .value("LD1D_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_IMM) + .value("LD1D_Q", LIEF::assembly::aarch64::OPCODE::LD1D_Q) + .value("LD1D_Q_IMM", LIEF::assembly::aarch64::OPCODE::LD1D_Q_IMM) + .value("LD1Fourv16b", LIEF::assembly::aarch64::OPCODE::LD1Fourv16b) + .value("LD1Fourv16b_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv16b_POST) + .value("LD1Fourv1d", LIEF::assembly::aarch64::OPCODE::LD1Fourv1d) + .value("LD1Fourv1d_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv1d_POST) + .value("LD1Fourv2d", LIEF::assembly::aarch64::OPCODE::LD1Fourv2d) + .value("LD1Fourv2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv2d_POST) + .value("LD1Fourv2s", LIEF::assembly::aarch64::OPCODE::LD1Fourv2s) + .value("LD1Fourv2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv2s_POST) + .value("LD1Fourv4h", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h) + .value("LD1Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h_POST) + .value("LD1Fourv4s", LIEF::assembly::aarch64::OPCODE::LD1Fourv4s) + .value("LD1Fourv4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv4s_POST) + .value("LD1Fourv8b", LIEF::assembly::aarch64::OPCODE::LD1Fourv8b) + .value("LD1Fourv8b_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv8b_POST) + .value("LD1Fourv8h", LIEF::assembly::aarch64::OPCODE::LD1Fourv8h) + .value("LD1Fourv8h_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv8h_POST) + .value("LD1H", LIEF::assembly::aarch64::OPCODE::LD1H) + .value("LD1H_2Z", LIEF::assembly::aarch64::OPCODE::LD1H_2Z) + .value("LD1H_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_2Z_IMM) + .value("LD1H_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1H_2Z_STRIDED) + .value("LD1H_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_2Z_STRIDED_IMM) + .value("LD1H_4Z", LIEF::assembly::aarch64::OPCODE::LD1H_4Z) + .value("LD1H_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_4Z_IMM) + .value("LD1H_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1H_4Z_STRIDED) + .value("LD1H_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_4Z_STRIDED_IMM) + .value("LD1H_D", LIEF::assembly::aarch64::OPCODE::LD1H_D) + .value("LD1H_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_D_IMM) + .value("LD1H_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_IMM) + .value("LD1H_S", LIEF::assembly::aarch64::OPCODE::LD1H_S) + .value("LD1H_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1H_S_IMM) + .value("LD1Onev16b", LIEF::assembly::aarch64::OPCODE::LD1Onev16b) + .value("LD1Onev16b_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev16b_POST) + .value("LD1Onev1d", LIEF::assembly::aarch64::OPCODE::LD1Onev1d) + .value("LD1Onev1d_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev1d_POST) + .value("LD1Onev2d", LIEF::assembly::aarch64::OPCODE::LD1Onev2d) + .value("LD1Onev2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev2d_POST) + .value("LD1Onev2s", LIEF::assembly::aarch64::OPCODE::LD1Onev2s) + .value("LD1Onev2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev2s_POST) + .value("LD1Onev4h", LIEF::assembly::aarch64::OPCODE::LD1Onev4h) + .value("LD1Onev4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev4h_POST) + .value("LD1Onev4s", LIEF::assembly::aarch64::OPCODE::LD1Onev4s) + .value("LD1Onev4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev4s_POST) + .value("LD1Onev8b", LIEF::assembly::aarch64::OPCODE::LD1Onev8b) + .value("LD1Onev8b_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev8b_POST) + .value("LD1Onev8h", LIEF::assembly::aarch64::OPCODE::LD1Onev8h) + .value("LD1Onev8h_POST", LIEF::assembly::aarch64::OPCODE::LD1Onev8h_POST) + .value("LD1RB_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RB_D_IMM) + .value("LD1RB_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RB_H_IMM) + .value("LD1RB_IMM", LIEF::assembly::aarch64::OPCODE::LD1RB_IMM) + .value("LD1RB_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RB_S_IMM) + .value("LD1RD_IMM", LIEF::assembly::aarch64::OPCODE::LD1RD_IMM) + .value("LD1RH_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RH_D_IMM) + .value("LD1RH_IMM", LIEF::assembly::aarch64::OPCODE::LD1RH_IMM) + .value("LD1RH_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RH_S_IMM) + .value("LD1RO_B", LIEF::assembly::aarch64::OPCODE::LD1RO_B) + .value("LD1RO_B_IMM", LIEF::assembly::aarch64::OPCODE::LD1RO_B_IMM) + .value("LD1RO_D", LIEF::assembly::aarch64::OPCODE::LD1RO_D) + .value("LD1RO_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RO_D_IMM) + .value("LD1RO_H", LIEF::assembly::aarch64::OPCODE::LD1RO_H) + .value("LD1RO_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RO_H_IMM) + .value("LD1RO_W", LIEF::assembly::aarch64::OPCODE::LD1RO_W) + .value("LD1RO_W_IMM", LIEF::assembly::aarch64::OPCODE::LD1RO_W_IMM) + .value("LD1RQ_B", LIEF::assembly::aarch64::OPCODE::LD1RQ_B) + .value("LD1RQ_B_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_B_IMM) + .value("LD1RQ_D", LIEF::assembly::aarch64::OPCODE::LD1RQ_D) + .value("LD1RQ_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_D_IMM) + .value("LD1RQ_H", LIEF::assembly::aarch64::OPCODE::LD1RQ_H) + .value("LD1RQ_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_H_IMM) + .value("LD1RQ_W", LIEF::assembly::aarch64::OPCODE::LD1RQ_W) + .value("LD1RQ_W_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_W_IMM) + .value("LD1RSB_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_D_IMM); + opcodes.value("LD1RSB_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_H_IMM) + .value("LD1RSB_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_S_IMM) + .value("LD1RSH_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSH_D_IMM) + .value("LD1RSH_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSH_S_IMM) + .value("LD1RSW_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSW_IMM) + .value("LD1RW_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RW_D_IMM) + .value("LD1RW_IMM", LIEF::assembly::aarch64::OPCODE::LD1RW_IMM) + .value("LD1Rv16b", LIEF::assembly::aarch64::OPCODE::LD1Rv16b) + .value("LD1Rv16b_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv16b_POST) + .value("LD1Rv1d", LIEF::assembly::aarch64::OPCODE::LD1Rv1d) + .value("LD1Rv1d_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv1d_POST) + .value("LD1Rv2d", LIEF::assembly::aarch64::OPCODE::LD1Rv2d) + .value("LD1Rv2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv2d_POST) + .value("LD1Rv2s", LIEF::assembly::aarch64::OPCODE::LD1Rv2s) + .value("LD1Rv2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv2s_POST) + .value("LD1Rv4h", LIEF::assembly::aarch64::OPCODE::LD1Rv4h) + .value("LD1Rv4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv4h_POST) + .value("LD1Rv4s", LIEF::assembly::aarch64::OPCODE::LD1Rv4s) + .value("LD1Rv4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv4s_POST) + .value("LD1Rv8b", LIEF::assembly::aarch64::OPCODE::LD1Rv8b) + .value("LD1Rv8b_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv8b_POST) + .value("LD1Rv8h", LIEF::assembly::aarch64::OPCODE::LD1Rv8h) + .value("LD1Rv8h_POST", LIEF::assembly::aarch64::OPCODE::LD1Rv8h_POST) + .value("LD1SB_D", LIEF::assembly::aarch64::OPCODE::LD1SB_D) + .value("LD1SB_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1SB_D_IMM) + .value("LD1SB_H", LIEF::assembly::aarch64::OPCODE::LD1SB_H) + .value("LD1SB_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1SB_H_IMM) + .value("LD1SB_S", LIEF::assembly::aarch64::OPCODE::LD1SB_S) + .value("LD1SB_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1SB_S_IMM) + .value("LD1SH_D", LIEF::assembly::aarch64::OPCODE::LD1SH_D) + .value("LD1SH_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1SH_D_IMM) + .value("LD1SH_S", LIEF::assembly::aarch64::OPCODE::LD1SH_S) + .value("LD1SH_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1SH_S_IMM) + .value("LD1SW_D", LIEF::assembly::aarch64::OPCODE::LD1SW_D) + .value("LD1SW_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1SW_D_IMM) + .value("LD1Threev16b", LIEF::assembly::aarch64::OPCODE::LD1Threev16b) + .value("LD1Threev16b_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev16b_POST) + .value("LD1Threev1d", LIEF::assembly::aarch64::OPCODE::LD1Threev1d) + .value("LD1Threev1d_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev1d_POST) + .value("LD1Threev2d", LIEF::assembly::aarch64::OPCODE::LD1Threev2d) + .value("LD1Threev2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev2d_POST) + .value("LD1Threev2s", LIEF::assembly::aarch64::OPCODE::LD1Threev2s) + .value("LD1Threev2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev2s_POST) + .value("LD1Threev4h", LIEF::assembly::aarch64::OPCODE::LD1Threev4h) + .value("LD1Threev4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev4h_POST) + .value("LD1Threev4s", LIEF::assembly::aarch64::OPCODE::LD1Threev4s) + .value("LD1Threev4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev4s_POST) + .value("LD1Threev8b", LIEF::assembly::aarch64::OPCODE::LD1Threev8b) + .value("LD1Threev8b_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev8b_POST) + .value("LD1Threev8h", LIEF::assembly::aarch64::OPCODE::LD1Threev8h) + .value("LD1Threev8h_POST", LIEF::assembly::aarch64::OPCODE::LD1Threev8h_POST) + .value("LD1Twov16b", LIEF::assembly::aarch64::OPCODE::LD1Twov16b) + .value("LD1Twov16b_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov16b_POST) + .value("LD1Twov1d", LIEF::assembly::aarch64::OPCODE::LD1Twov1d) + .value("LD1Twov1d_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov1d_POST) + .value("LD1Twov2d", LIEF::assembly::aarch64::OPCODE::LD1Twov2d) + .value("LD1Twov2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov2d_POST) + .value("LD1Twov2s", LIEF::assembly::aarch64::OPCODE::LD1Twov2s) + .value("LD1Twov2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov2s_POST) + .value("LD1Twov4h", LIEF::assembly::aarch64::OPCODE::LD1Twov4h) + .value("LD1Twov4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov4h_POST) + .value("LD1Twov4s", LIEF::assembly::aarch64::OPCODE::LD1Twov4s) + .value("LD1Twov4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov4s_POST) + .value("LD1Twov8b", LIEF::assembly::aarch64::OPCODE::LD1Twov8b) + .value("LD1Twov8b_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov8b_POST) + .value("LD1Twov8h", LIEF::assembly::aarch64::OPCODE::LD1Twov8h) + .value("LD1Twov8h_POST", LIEF::assembly::aarch64::OPCODE::LD1Twov8h_POST) + .value("LD1W", LIEF::assembly::aarch64::OPCODE::LD1W) + .value("LD1W_2Z", LIEF::assembly::aarch64::OPCODE::LD1W_2Z) + .value("LD1W_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_2Z_IMM) + .value("LD1W_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1W_2Z_STRIDED) + .value("LD1W_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_2Z_STRIDED_IMM) + .value("LD1W_4Z", LIEF::assembly::aarch64::OPCODE::LD1W_4Z) + .value("LD1W_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_4Z_IMM) + .value("LD1W_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LD1W_4Z_STRIDED) + .value("LD1W_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_4Z_STRIDED_IMM) + .value("LD1W_D", LIEF::assembly::aarch64::OPCODE::LD1W_D) + .value("LD1W_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_D_IMM) + .value("LD1W_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_IMM) + .value("LD1W_Q", LIEF::assembly::aarch64::OPCODE::LD1W_Q) + .value("LD1W_Q_IMM", LIEF::assembly::aarch64::OPCODE::LD1W_Q_IMM) + .value("LD1_MXIPXX_H_B", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_B) + .value("LD1_MXIPXX_H_D", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_D) + .value("LD1_MXIPXX_H_H", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_H) + .value("LD1_MXIPXX_H_Q", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_Q) + .value("LD1_MXIPXX_H_S", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_H_S) + .value("LD1_MXIPXX_V_B", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_B) + .value("LD1_MXIPXX_V_D", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_D) + .value("LD1_MXIPXX_V_H", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_H) + .value("LD1_MXIPXX_V_Q", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_Q) + .value("LD1_MXIPXX_V_S", LIEF::assembly::aarch64::OPCODE::LD1_MXIPXX_V_S) + .value("LD1i16", LIEF::assembly::aarch64::OPCODE::LD1i16) + .value("LD1i16_POST", LIEF::assembly::aarch64::OPCODE::LD1i16_POST) + .value("LD1i32", LIEF::assembly::aarch64::OPCODE::LD1i32) + .value("LD1i32_POST", LIEF::assembly::aarch64::OPCODE::LD1i32_POST) + .value("LD1i64", LIEF::assembly::aarch64::OPCODE::LD1i64) + .value("LD1i64_POST", LIEF::assembly::aarch64::OPCODE::LD1i64_POST) + .value("LD1i8", LIEF::assembly::aarch64::OPCODE::LD1i8) + .value("LD1i8_POST", LIEF::assembly::aarch64::OPCODE::LD1i8_POST) + .value("LD2B", LIEF::assembly::aarch64::OPCODE::LD2B) + .value("LD2B_IMM", LIEF::assembly::aarch64::OPCODE::LD2B_IMM) + .value("LD2D", LIEF::assembly::aarch64::OPCODE::LD2D) + .value("LD2D_IMM", LIEF::assembly::aarch64::OPCODE::LD2D_IMM) + .value("LD2H", LIEF::assembly::aarch64::OPCODE::LD2H) + .value("LD2H_IMM", LIEF::assembly::aarch64::OPCODE::LD2H_IMM) + .value("LD2Q", LIEF::assembly::aarch64::OPCODE::LD2Q) + .value("LD2Q_IMM", LIEF::assembly::aarch64::OPCODE::LD2Q_IMM) + .value("LD2Rv16b", LIEF::assembly::aarch64::OPCODE::LD2Rv16b) + .value("LD2Rv16b_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv16b_POST) + .value("LD2Rv1d", LIEF::assembly::aarch64::OPCODE::LD2Rv1d) + .value("LD2Rv1d_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv1d_POST) + .value("LD2Rv2d", LIEF::assembly::aarch64::OPCODE::LD2Rv2d) + .value("LD2Rv2d_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv2d_POST) + .value("LD2Rv2s", LIEF::assembly::aarch64::OPCODE::LD2Rv2s) + .value("LD2Rv2s_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv2s_POST) + .value("LD2Rv4h", LIEF::assembly::aarch64::OPCODE::LD2Rv4h) + .value("LD2Rv4h_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv4h_POST) + .value("LD2Rv4s", LIEF::assembly::aarch64::OPCODE::LD2Rv4s) + .value("LD2Rv4s_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv4s_POST) + .value("LD2Rv8b", LIEF::assembly::aarch64::OPCODE::LD2Rv8b) + .value("LD2Rv8b_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv8b_POST) + .value("LD2Rv8h", LIEF::assembly::aarch64::OPCODE::LD2Rv8h) + .value("LD2Rv8h_POST", LIEF::assembly::aarch64::OPCODE::LD2Rv8h_POST) + .value("LD2Twov16b", LIEF::assembly::aarch64::OPCODE::LD2Twov16b) + .value("LD2Twov16b_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov16b_POST) + .value("LD2Twov2d", LIEF::assembly::aarch64::OPCODE::LD2Twov2d) + .value("LD2Twov2d_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov2d_POST) + .value("LD2Twov2s", LIEF::assembly::aarch64::OPCODE::LD2Twov2s) + .value("LD2Twov2s_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov2s_POST) + .value("LD2Twov4h", LIEF::assembly::aarch64::OPCODE::LD2Twov4h) + .value("LD2Twov4h_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov4h_POST) + .value("LD2Twov4s", LIEF::assembly::aarch64::OPCODE::LD2Twov4s) + .value("LD2Twov4s_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov4s_POST) + .value("LD2Twov8b", LIEF::assembly::aarch64::OPCODE::LD2Twov8b) + .value("LD2Twov8b_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov8b_POST) + .value("LD2Twov8h", LIEF::assembly::aarch64::OPCODE::LD2Twov8h) + .value("LD2Twov8h_POST", LIEF::assembly::aarch64::OPCODE::LD2Twov8h_POST) + .value("LD2W", LIEF::assembly::aarch64::OPCODE::LD2W) + .value("LD2W_IMM", LIEF::assembly::aarch64::OPCODE::LD2W_IMM) + .value("LD2i16", LIEF::assembly::aarch64::OPCODE::LD2i16) + .value("LD2i16_POST", LIEF::assembly::aarch64::OPCODE::LD2i16_POST) + .value("LD2i32", LIEF::assembly::aarch64::OPCODE::LD2i32) + .value("LD2i32_POST", LIEF::assembly::aarch64::OPCODE::LD2i32_POST) + .value("LD2i64", LIEF::assembly::aarch64::OPCODE::LD2i64) + .value("LD2i64_POST", LIEF::assembly::aarch64::OPCODE::LD2i64_POST) + .value("LD2i8", LIEF::assembly::aarch64::OPCODE::LD2i8) + .value("LD2i8_POST", LIEF::assembly::aarch64::OPCODE::LD2i8_POST) + .value("LD3B", LIEF::assembly::aarch64::OPCODE::LD3B) + .value("LD3B_IMM", LIEF::assembly::aarch64::OPCODE::LD3B_IMM) + .value("LD3D", LIEF::assembly::aarch64::OPCODE::LD3D) + .value("LD3D_IMM", LIEF::assembly::aarch64::OPCODE::LD3D_IMM) + .value("LD3H", LIEF::assembly::aarch64::OPCODE::LD3H) + .value("LD3H_IMM", LIEF::assembly::aarch64::OPCODE::LD3H_IMM) + .value("LD3Q", LIEF::assembly::aarch64::OPCODE::LD3Q) + .value("LD3Q_IMM", LIEF::assembly::aarch64::OPCODE::LD3Q_IMM) + .value("LD3Rv16b", LIEF::assembly::aarch64::OPCODE::LD3Rv16b) + .value("LD3Rv16b_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv16b_POST) + .value("LD3Rv1d", LIEF::assembly::aarch64::OPCODE::LD3Rv1d) + .value("LD3Rv1d_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv1d_POST) + .value("LD3Rv2d", LIEF::assembly::aarch64::OPCODE::LD3Rv2d) + .value("LD3Rv2d_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv2d_POST) + .value("LD3Rv2s", LIEF::assembly::aarch64::OPCODE::LD3Rv2s) + .value("LD3Rv2s_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv2s_POST) + .value("LD3Rv4h", LIEF::assembly::aarch64::OPCODE::LD3Rv4h) + .value("LD3Rv4h_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv4h_POST) + .value("LD3Rv4s", LIEF::assembly::aarch64::OPCODE::LD3Rv4s) + .value("LD3Rv4s_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv4s_POST) + .value("LD3Rv8b", LIEF::assembly::aarch64::OPCODE::LD3Rv8b) + .value("LD3Rv8b_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv8b_POST) + .value("LD3Rv8h", LIEF::assembly::aarch64::OPCODE::LD3Rv8h) + .value("LD3Rv8h_POST", LIEF::assembly::aarch64::OPCODE::LD3Rv8h_POST) + .value("LD3Threev16b", LIEF::assembly::aarch64::OPCODE::LD3Threev16b) + .value("LD3Threev16b_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev16b_POST) + .value("LD3Threev2d", LIEF::assembly::aarch64::OPCODE::LD3Threev2d) + .value("LD3Threev2d_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev2d_POST) + .value("LD3Threev2s", LIEF::assembly::aarch64::OPCODE::LD3Threev2s) + .value("LD3Threev2s_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev2s_POST) + .value("LD3Threev4h", LIEF::assembly::aarch64::OPCODE::LD3Threev4h) + .value("LD3Threev4h_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev4h_POST) + .value("LD3Threev4s", LIEF::assembly::aarch64::OPCODE::LD3Threev4s) + .value("LD3Threev4s_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev4s_POST) + .value("LD3Threev8b", LIEF::assembly::aarch64::OPCODE::LD3Threev8b) + .value("LD3Threev8b_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev8b_POST) + .value("LD3Threev8h", LIEF::assembly::aarch64::OPCODE::LD3Threev8h) + .value("LD3Threev8h_POST", LIEF::assembly::aarch64::OPCODE::LD3Threev8h_POST) + .value("LD3W", LIEF::assembly::aarch64::OPCODE::LD3W) + .value("LD3W_IMM", LIEF::assembly::aarch64::OPCODE::LD3W_IMM) + .value("LD3i16", LIEF::assembly::aarch64::OPCODE::LD3i16) + .value("LD3i16_POST", LIEF::assembly::aarch64::OPCODE::LD3i16_POST) + .value("LD3i32", LIEF::assembly::aarch64::OPCODE::LD3i32) + .value("LD3i32_POST", LIEF::assembly::aarch64::OPCODE::LD3i32_POST) + .value("LD3i64", LIEF::assembly::aarch64::OPCODE::LD3i64) + .value("LD3i64_POST", LIEF::assembly::aarch64::OPCODE::LD3i64_POST) + .value("LD3i8", LIEF::assembly::aarch64::OPCODE::LD3i8) + .value("LD3i8_POST", LIEF::assembly::aarch64::OPCODE::LD3i8_POST) + .value("LD4B", LIEF::assembly::aarch64::OPCODE::LD4B) + .value("LD4B_IMM", LIEF::assembly::aarch64::OPCODE::LD4B_IMM) + .value("LD4D", LIEF::assembly::aarch64::OPCODE::LD4D) + .value("LD4D_IMM", LIEF::assembly::aarch64::OPCODE::LD4D_IMM) + .value("LD4Fourv16b", LIEF::assembly::aarch64::OPCODE::LD4Fourv16b) + .value("LD4Fourv16b_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv16b_POST) + .value("LD4Fourv2d", LIEF::assembly::aarch64::OPCODE::LD4Fourv2d) + .value("LD4Fourv2d_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv2d_POST) + .value("LD4Fourv2s", LIEF::assembly::aarch64::OPCODE::LD4Fourv2s) + .value("LD4Fourv2s_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv2s_POST) + .value("LD4Fourv4h", LIEF::assembly::aarch64::OPCODE::LD4Fourv4h) + .value("LD4Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv4h_POST) + .value("LD4Fourv4s", LIEF::assembly::aarch64::OPCODE::LD4Fourv4s) + .value("LD4Fourv4s_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv4s_POST) + .value("LD4Fourv8b", LIEF::assembly::aarch64::OPCODE::LD4Fourv8b) + .value("LD4Fourv8b_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv8b_POST) + .value("LD4Fourv8h", LIEF::assembly::aarch64::OPCODE::LD4Fourv8h) + .value("LD4Fourv8h_POST", LIEF::assembly::aarch64::OPCODE::LD4Fourv8h_POST) + .value("LD4H", LIEF::assembly::aarch64::OPCODE::LD4H) + .value("LD4H_IMM", LIEF::assembly::aarch64::OPCODE::LD4H_IMM) + .value("LD4Q", LIEF::assembly::aarch64::OPCODE::LD4Q) + .value("LD4Q_IMM", LIEF::assembly::aarch64::OPCODE::LD4Q_IMM) + .value("LD4Rv16b", LIEF::assembly::aarch64::OPCODE::LD4Rv16b) + .value("LD4Rv16b_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv16b_POST) + .value("LD4Rv1d", LIEF::assembly::aarch64::OPCODE::LD4Rv1d) + .value("LD4Rv1d_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv1d_POST) + .value("LD4Rv2d", LIEF::assembly::aarch64::OPCODE::LD4Rv2d) + .value("LD4Rv2d_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv2d_POST) + .value("LD4Rv2s", LIEF::assembly::aarch64::OPCODE::LD4Rv2s) + .value("LD4Rv2s_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv2s_POST) + .value("LD4Rv4h", LIEF::assembly::aarch64::OPCODE::LD4Rv4h) + .value("LD4Rv4h_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv4h_POST) + .value("LD4Rv4s", LIEF::assembly::aarch64::OPCODE::LD4Rv4s) + .value("LD4Rv4s_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv4s_POST) + .value("LD4Rv8b", LIEF::assembly::aarch64::OPCODE::LD4Rv8b) + .value("LD4Rv8b_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv8b_POST) + .value("LD4Rv8h", LIEF::assembly::aarch64::OPCODE::LD4Rv8h) + .value("LD4Rv8h_POST", LIEF::assembly::aarch64::OPCODE::LD4Rv8h_POST) + .value("LD4W", LIEF::assembly::aarch64::OPCODE::LD4W) + .value("LD4W_IMM", LIEF::assembly::aarch64::OPCODE::LD4W_IMM) + .value("LD4i16", LIEF::assembly::aarch64::OPCODE::LD4i16) + .value("LD4i16_POST", LIEF::assembly::aarch64::OPCODE::LD4i16_POST) + .value("LD4i32", LIEF::assembly::aarch64::OPCODE::LD4i32) + .value("LD4i32_POST", LIEF::assembly::aarch64::OPCODE::LD4i32_POST) + .value("LD4i64", LIEF::assembly::aarch64::OPCODE::LD4i64) + .value("LD4i64_POST", LIEF::assembly::aarch64::OPCODE::LD4i64_POST) + .value("LD4i8", LIEF::assembly::aarch64::OPCODE::LD4i8) + .value("LD4i8_POST", LIEF::assembly::aarch64::OPCODE::LD4i8_POST) + .value("LD64B", LIEF::assembly::aarch64::OPCODE::LD64B) + .value("LDADDAB", LIEF::assembly::aarch64::OPCODE::LDADDAB) + .value("LDADDAH", LIEF::assembly::aarch64::OPCODE::LDADDAH) + .value("LDADDALB", LIEF::assembly::aarch64::OPCODE::LDADDALB) + .value("LDADDALH", LIEF::assembly::aarch64::OPCODE::LDADDALH) + .value("LDADDALW", LIEF::assembly::aarch64::OPCODE::LDADDALW) + .value("LDADDALX", LIEF::assembly::aarch64::OPCODE::LDADDALX) + .value("LDADDAW", LIEF::assembly::aarch64::OPCODE::LDADDAW) + .value("LDADDAX", LIEF::assembly::aarch64::OPCODE::LDADDAX) + .value("LDADDB", LIEF::assembly::aarch64::OPCODE::LDADDB) + .value("LDADDH", LIEF::assembly::aarch64::OPCODE::LDADDH) + .value("LDADDLB", LIEF::assembly::aarch64::OPCODE::LDADDLB) + .value("LDADDLH", LIEF::assembly::aarch64::OPCODE::LDADDLH) + .value("LDADDLW", LIEF::assembly::aarch64::OPCODE::LDADDLW) + .value("LDADDLX", LIEF::assembly::aarch64::OPCODE::LDADDLX) + .value("LDADDW", LIEF::assembly::aarch64::OPCODE::LDADDW) + .value("LDADDX", LIEF::assembly::aarch64::OPCODE::LDADDX) + .value("LDAP1", LIEF::assembly::aarch64::OPCODE::LDAP1) + .value("LDAPPi", LIEF::assembly::aarch64::OPCODE::LDAPPi) + .value("LDAPRB", LIEF::assembly::aarch64::OPCODE::LDAPRB) + .value("LDAPRH", LIEF::assembly::aarch64::OPCODE::LDAPRH) + .value("LDAPRW", LIEF::assembly::aarch64::OPCODE::LDAPRW) + .value("LDAPRWpost", LIEF::assembly::aarch64::OPCODE::LDAPRWpost) + .value("LDAPRX", LIEF::assembly::aarch64::OPCODE::LDAPRX) + .value("LDAPRXpost", LIEF::assembly::aarch64::OPCODE::LDAPRXpost) + .value("LDAPURBi", LIEF::assembly::aarch64::OPCODE::LDAPURBi) + .value("LDAPURHi", LIEF::assembly::aarch64::OPCODE::LDAPURHi) + .value("LDAPURSBWi", LIEF::assembly::aarch64::OPCODE::LDAPURSBWi) + .value("LDAPURSBXi", LIEF::assembly::aarch64::OPCODE::LDAPURSBXi) + .value("LDAPURSHWi", LIEF::assembly::aarch64::OPCODE::LDAPURSHWi) + .value("LDAPURSHXi", LIEF::assembly::aarch64::OPCODE::LDAPURSHXi) + .value("LDAPURSWi", LIEF::assembly::aarch64::OPCODE::LDAPURSWi) + .value("LDAPURXi", LIEF::assembly::aarch64::OPCODE::LDAPURXi) + .value("LDAPURbi", LIEF::assembly::aarch64::OPCODE::LDAPURbi) + .value("LDAPURdi", LIEF::assembly::aarch64::OPCODE::LDAPURdi) + .value("LDAPURhi", LIEF::assembly::aarch64::OPCODE::LDAPURhi) + .value("LDAPURi", LIEF::assembly::aarch64::OPCODE::LDAPURi) + .value("LDAPURqi", LIEF::assembly::aarch64::OPCODE::LDAPURqi) + .value("LDAPURsi", LIEF::assembly::aarch64::OPCODE::LDAPURsi) + .value("LDAPi", LIEF::assembly::aarch64::OPCODE::LDAPi) + .value("LDARB", LIEF::assembly::aarch64::OPCODE::LDARB) + .value("LDARH", LIEF::assembly::aarch64::OPCODE::LDARH) + .value("LDARW", LIEF::assembly::aarch64::OPCODE::LDARW) + .value("LDARX", LIEF::assembly::aarch64::OPCODE::LDARX) + .value("LDATXRW", LIEF::assembly::aarch64::OPCODE::LDATXRW) + .value("LDATXRX", LIEF::assembly::aarch64::OPCODE::LDATXRX) + .value("LDAXPW", LIEF::assembly::aarch64::OPCODE::LDAXPW) + .value("LDAXPX", LIEF::assembly::aarch64::OPCODE::LDAXPX) + .value("LDAXRB", LIEF::assembly::aarch64::OPCODE::LDAXRB) + .value("LDAXRH", LIEF::assembly::aarch64::OPCODE::LDAXRH) + .value("LDAXRW", LIEF::assembly::aarch64::OPCODE::LDAXRW) + .value("LDAXRX", LIEF::assembly::aarch64::OPCODE::LDAXRX) + .value("LDBFADD", LIEF::assembly::aarch64::OPCODE::LDBFADD) + .value("LDBFADDA", LIEF::assembly::aarch64::OPCODE::LDBFADDA) + .value("LDBFADDAL", LIEF::assembly::aarch64::OPCODE::LDBFADDAL) + .value("LDBFADDL", LIEF::assembly::aarch64::OPCODE::LDBFADDL) + .value("LDBFMAX", LIEF::assembly::aarch64::OPCODE::LDBFMAX); + opcodes.value("LDBFMAXA", LIEF::assembly::aarch64::OPCODE::LDBFMAXA) + .value("LDBFMAXAL", LIEF::assembly::aarch64::OPCODE::LDBFMAXAL) + .value("LDBFMAXL", LIEF::assembly::aarch64::OPCODE::LDBFMAXL) + .value("LDBFMAXNM", LIEF::assembly::aarch64::OPCODE::LDBFMAXNM) + .value("LDBFMAXNMA", LIEF::assembly::aarch64::OPCODE::LDBFMAXNMA) + .value("LDBFMAXNMAL", LIEF::assembly::aarch64::OPCODE::LDBFMAXNMAL) + .value("LDBFMAXNML", LIEF::assembly::aarch64::OPCODE::LDBFMAXNML) + .value("LDBFMIN", LIEF::assembly::aarch64::OPCODE::LDBFMIN) + .value("LDBFMINA", LIEF::assembly::aarch64::OPCODE::LDBFMINA) + .value("LDBFMINAL", LIEF::assembly::aarch64::OPCODE::LDBFMINAL) + .value("LDBFMINL", LIEF::assembly::aarch64::OPCODE::LDBFMINL) + .value("LDBFMINNM", LIEF::assembly::aarch64::OPCODE::LDBFMINNM) + .value("LDBFMINNMA", LIEF::assembly::aarch64::OPCODE::LDBFMINNMA) + .value("LDBFMINNMAL", LIEF::assembly::aarch64::OPCODE::LDBFMINNMAL) + .value("LDBFMINNML", LIEF::assembly::aarch64::OPCODE::LDBFMINNML) + .value("LDCLRAB", LIEF::assembly::aarch64::OPCODE::LDCLRAB) + .value("LDCLRAH", LIEF::assembly::aarch64::OPCODE::LDCLRAH) + .value("LDCLRALB", LIEF::assembly::aarch64::OPCODE::LDCLRALB) + .value("LDCLRALH", LIEF::assembly::aarch64::OPCODE::LDCLRALH) + .value("LDCLRALW", LIEF::assembly::aarch64::OPCODE::LDCLRALW) + .value("LDCLRALX", LIEF::assembly::aarch64::OPCODE::LDCLRALX) + .value("LDCLRAW", LIEF::assembly::aarch64::OPCODE::LDCLRAW) + .value("LDCLRAX", LIEF::assembly::aarch64::OPCODE::LDCLRAX) + .value("LDCLRB", LIEF::assembly::aarch64::OPCODE::LDCLRB) + .value("LDCLRH", LIEF::assembly::aarch64::OPCODE::LDCLRH) + .value("LDCLRLB", LIEF::assembly::aarch64::OPCODE::LDCLRLB) + .value("LDCLRLH", LIEF::assembly::aarch64::OPCODE::LDCLRLH) + .value("LDCLRLW", LIEF::assembly::aarch64::OPCODE::LDCLRLW) + .value("LDCLRLX", LIEF::assembly::aarch64::OPCODE::LDCLRLX) + .value("LDCLRP", LIEF::assembly::aarch64::OPCODE::LDCLRP) + .value("LDCLRPA", LIEF::assembly::aarch64::OPCODE::LDCLRPA) + .value("LDCLRPAL", LIEF::assembly::aarch64::OPCODE::LDCLRPAL) + .value("LDCLRPL", LIEF::assembly::aarch64::OPCODE::LDCLRPL) + .value("LDCLRW", LIEF::assembly::aarch64::OPCODE::LDCLRW) + .value("LDCLRX", LIEF::assembly::aarch64::OPCODE::LDCLRX) + .value("LDEORAB", LIEF::assembly::aarch64::OPCODE::LDEORAB) + .value("LDEORAH", LIEF::assembly::aarch64::OPCODE::LDEORAH) + .value("LDEORALB", LIEF::assembly::aarch64::OPCODE::LDEORALB) + .value("LDEORALH", LIEF::assembly::aarch64::OPCODE::LDEORALH) + .value("LDEORALW", LIEF::assembly::aarch64::OPCODE::LDEORALW) + .value("LDEORALX", LIEF::assembly::aarch64::OPCODE::LDEORALX) + .value("LDEORAW", LIEF::assembly::aarch64::OPCODE::LDEORAW) + .value("LDEORAX", LIEF::assembly::aarch64::OPCODE::LDEORAX) + .value("LDEORB", LIEF::assembly::aarch64::OPCODE::LDEORB) + .value("LDEORH", LIEF::assembly::aarch64::OPCODE::LDEORH) + .value("LDEORLB", LIEF::assembly::aarch64::OPCODE::LDEORLB) + .value("LDEORLH", LIEF::assembly::aarch64::OPCODE::LDEORLH) + .value("LDEORLW", LIEF::assembly::aarch64::OPCODE::LDEORLW) + .value("LDEORLX", LIEF::assembly::aarch64::OPCODE::LDEORLX) + .value("LDEORW", LIEF::assembly::aarch64::OPCODE::LDEORW) + .value("LDEORX", LIEF::assembly::aarch64::OPCODE::LDEORX) + .value("LDFADDAD", LIEF::assembly::aarch64::OPCODE::LDFADDAD) + .value("LDFADDAH", LIEF::assembly::aarch64::OPCODE::LDFADDAH) + .value("LDFADDALD", LIEF::assembly::aarch64::OPCODE::LDFADDALD) + .value("LDFADDALH", LIEF::assembly::aarch64::OPCODE::LDFADDALH) + .value("LDFADDALS", LIEF::assembly::aarch64::OPCODE::LDFADDALS) + .value("LDFADDAS", LIEF::assembly::aarch64::OPCODE::LDFADDAS) + .value("LDFADDD", LIEF::assembly::aarch64::OPCODE::LDFADDD) + .value("LDFADDH", LIEF::assembly::aarch64::OPCODE::LDFADDH) + .value("LDFADDLD", LIEF::assembly::aarch64::OPCODE::LDFADDLD) + .value("LDFADDLH", LIEF::assembly::aarch64::OPCODE::LDFADDLH) + .value("LDFADDLS", LIEF::assembly::aarch64::OPCODE::LDFADDLS) + .value("LDFADDS", LIEF::assembly::aarch64::OPCODE::LDFADDS) + .value("LDFF1B", LIEF::assembly::aarch64::OPCODE::LDFF1B) + .value("LDFF1B_D", LIEF::assembly::aarch64::OPCODE::LDFF1B_D) + .value("LDFF1B_H", LIEF::assembly::aarch64::OPCODE::LDFF1B_H) + .value("LDFF1B_S", LIEF::assembly::aarch64::OPCODE::LDFF1B_S) + .value("LDFF1D", LIEF::assembly::aarch64::OPCODE::LDFF1D) + .value("LDFF1H", LIEF::assembly::aarch64::OPCODE::LDFF1H) + .value("LDFF1H_D", LIEF::assembly::aarch64::OPCODE::LDFF1H_D) + .value("LDFF1H_S", LIEF::assembly::aarch64::OPCODE::LDFF1H_S) + .value("LDFF1SB_D", LIEF::assembly::aarch64::OPCODE::LDFF1SB_D) + .value("LDFF1SB_H", LIEF::assembly::aarch64::OPCODE::LDFF1SB_H) + .value("LDFF1SB_S", LIEF::assembly::aarch64::OPCODE::LDFF1SB_S) + .value("LDFF1SH_D", LIEF::assembly::aarch64::OPCODE::LDFF1SH_D) + .value("LDFF1SH_S", LIEF::assembly::aarch64::OPCODE::LDFF1SH_S) + .value("LDFF1SW_D", LIEF::assembly::aarch64::OPCODE::LDFF1SW_D) + .value("LDFF1W", LIEF::assembly::aarch64::OPCODE::LDFF1W) + .value("LDFF1W_D", LIEF::assembly::aarch64::OPCODE::LDFF1W_D) + .value("LDFMAXAD", LIEF::assembly::aarch64::OPCODE::LDFMAXAD) + .value("LDFMAXAH", LIEF::assembly::aarch64::OPCODE::LDFMAXAH) + .value("LDFMAXALD", LIEF::assembly::aarch64::OPCODE::LDFMAXALD) + .value("LDFMAXALH", LIEF::assembly::aarch64::OPCODE::LDFMAXALH) + .value("LDFMAXALS", LIEF::assembly::aarch64::OPCODE::LDFMAXALS) + .value("LDFMAXAS", LIEF::assembly::aarch64::OPCODE::LDFMAXAS) + .value("LDFMAXD", LIEF::assembly::aarch64::OPCODE::LDFMAXD) + .value("LDFMAXH", LIEF::assembly::aarch64::OPCODE::LDFMAXH) + .value("LDFMAXLD", LIEF::assembly::aarch64::OPCODE::LDFMAXLD) + .value("LDFMAXLH", LIEF::assembly::aarch64::OPCODE::LDFMAXLH) + .value("LDFMAXLS", LIEF::assembly::aarch64::OPCODE::LDFMAXLS) + .value("LDFMAXNMAD", LIEF::assembly::aarch64::OPCODE::LDFMAXNMAD) + .value("LDFMAXNMAH", LIEF::assembly::aarch64::OPCODE::LDFMAXNMAH) + .value("LDFMAXNMALD", LIEF::assembly::aarch64::OPCODE::LDFMAXNMALD) + .value("LDFMAXNMALH", LIEF::assembly::aarch64::OPCODE::LDFMAXNMALH) + .value("LDFMAXNMALS", LIEF::assembly::aarch64::OPCODE::LDFMAXNMALS) + .value("LDFMAXNMAS", LIEF::assembly::aarch64::OPCODE::LDFMAXNMAS) + .value("LDFMAXNMD", LIEF::assembly::aarch64::OPCODE::LDFMAXNMD) + .value("LDFMAXNMH", LIEF::assembly::aarch64::OPCODE::LDFMAXNMH) + .value("LDFMAXNMLD", LIEF::assembly::aarch64::OPCODE::LDFMAXNMLD) + .value("LDFMAXNMLH", LIEF::assembly::aarch64::OPCODE::LDFMAXNMLH) + .value("LDFMAXNMLS", LIEF::assembly::aarch64::OPCODE::LDFMAXNMLS) + .value("LDFMAXNMS", LIEF::assembly::aarch64::OPCODE::LDFMAXNMS) + .value("LDFMAXS", LIEF::assembly::aarch64::OPCODE::LDFMAXS) + .value("LDFMINAD", LIEF::assembly::aarch64::OPCODE::LDFMINAD) + .value("LDFMINAH", LIEF::assembly::aarch64::OPCODE::LDFMINAH) + .value("LDFMINALD", LIEF::assembly::aarch64::OPCODE::LDFMINALD) + .value("LDFMINALH", LIEF::assembly::aarch64::OPCODE::LDFMINALH) + .value("LDFMINALS", LIEF::assembly::aarch64::OPCODE::LDFMINALS) + .value("LDFMINAS", LIEF::assembly::aarch64::OPCODE::LDFMINAS) + .value("LDFMIND", LIEF::assembly::aarch64::OPCODE::LDFMIND) + .value("LDFMINH", LIEF::assembly::aarch64::OPCODE::LDFMINH) + .value("LDFMINLD", LIEF::assembly::aarch64::OPCODE::LDFMINLD) + .value("LDFMINLH", LIEF::assembly::aarch64::OPCODE::LDFMINLH) + .value("LDFMINLS", LIEF::assembly::aarch64::OPCODE::LDFMINLS) + .value("LDFMINNMAD", LIEF::assembly::aarch64::OPCODE::LDFMINNMAD) + .value("LDFMINNMAH", LIEF::assembly::aarch64::OPCODE::LDFMINNMAH) + .value("LDFMINNMALD", LIEF::assembly::aarch64::OPCODE::LDFMINNMALD) + .value("LDFMINNMALH", LIEF::assembly::aarch64::OPCODE::LDFMINNMALH) + .value("LDFMINNMALS", LIEF::assembly::aarch64::OPCODE::LDFMINNMALS) + .value("LDFMINNMAS", LIEF::assembly::aarch64::OPCODE::LDFMINNMAS) + .value("LDFMINNMD", LIEF::assembly::aarch64::OPCODE::LDFMINNMD) + .value("LDFMINNMH", LIEF::assembly::aarch64::OPCODE::LDFMINNMH) + .value("LDFMINNMLD", LIEF::assembly::aarch64::OPCODE::LDFMINNMLD) + .value("LDFMINNMLH", LIEF::assembly::aarch64::OPCODE::LDFMINNMLH) + .value("LDFMINNMLS", LIEF::assembly::aarch64::OPCODE::LDFMINNMLS) + .value("LDFMINNMS", LIEF::assembly::aarch64::OPCODE::LDFMINNMS) + .value("LDFMINS", LIEF::assembly::aarch64::OPCODE::LDFMINS) + .value("LDG", LIEF::assembly::aarch64::OPCODE::LDG) + .value("LDGM", LIEF::assembly::aarch64::OPCODE::LDGM) + .value("LDIAPPW", LIEF::assembly::aarch64::OPCODE::LDIAPPW) + .value("LDIAPPWpost", LIEF::assembly::aarch64::OPCODE::LDIAPPWpost) + .value("LDIAPPX", LIEF::assembly::aarch64::OPCODE::LDIAPPX) + .value("LDIAPPXpost", LIEF::assembly::aarch64::OPCODE::LDIAPPXpost) + .value("LDLARB", LIEF::assembly::aarch64::OPCODE::LDLARB) + .value("LDLARH", LIEF::assembly::aarch64::OPCODE::LDLARH) + .value("LDLARW", LIEF::assembly::aarch64::OPCODE::LDLARW) + .value("LDLARX", LIEF::assembly::aarch64::OPCODE::LDLARX) + .value("LDNF1B_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1B_D_IMM) + .value("LDNF1B_H_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1B_H_IMM) + .value("LDNF1B_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1B_IMM) + .value("LDNF1B_S_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1B_S_IMM) + .value("LDNF1D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1D_IMM) + .value("LDNF1H_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1H_D_IMM) + .value("LDNF1H_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1H_IMM) + .value("LDNF1H_S_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1H_S_IMM) + .value("LDNF1SB_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SB_D_IMM) + .value("LDNF1SB_H_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SB_H_IMM) + .value("LDNF1SB_S_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SB_S_IMM) + .value("LDNF1SH_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SH_D_IMM) + .value("LDNF1SH_S_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SH_S_IMM) + .value("LDNF1SW_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1SW_D_IMM) + .value("LDNF1W_D_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1W_D_IMM) + .value("LDNF1W_IMM", LIEF::assembly::aarch64::OPCODE::LDNF1W_IMM) + .value("LDNPDi", LIEF::assembly::aarch64::OPCODE::LDNPDi) + .value("LDNPQi", LIEF::assembly::aarch64::OPCODE::LDNPQi) + .value("LDNPSi", LIEF::assembly::aarch64::OPCODE::LDNPSi) + .value("LDNPWi", LIEF::assembly::aarch64::OPCODE::LDNPWi) + .value("LDNPXi", LIEF::assembly::aarch64::OPCODE::LDNPXi) + .value("LDNT1B_2Z", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z) + .value("LDNT1B_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z_IMM) + .value("LDNT1B_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z_STRIDED) + .value("LDNT1B_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1B_2Z_STRIDED_IMM) + .value("LDNT1B_4Z", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z) + .value("LDNT1B_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z_IMM) + .value("LDNT1B_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z_STRIDED) + .value("LDNT1B_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1B_4Z_STRIDED_IMM) + .value("LDNT1B_ZRI", LIEF::assembly::aarch64::OPCODE::LDNT1B_ZRI) + .value("LDNT1B_ZRR", LIEF::assembly::aarch64::OPCODE::LDNT1B_ZRR) + .value("LDNT1B_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1B_ZZR_D) + .value("LDNT1B_ZZR_S", LIEF::assembly::aarch64::OPCODE::LDNT1B_ZZR_S) + .value("LDNT1D_2Z", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z) + .value("LDNT1D_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z_IMM) + .value("LDNT1D_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z_STRIDED) + .value("LDNT1D_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1D_2Z_STRIDED_IMM) + .value("LDNT1D_4Z", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z) + .value("LDNT1D_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z_IMM) + .value("LDNT1D_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z_STRIDED) + .value("LDNT1D_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1D_4Z_STRIDED_IMM) + .value("LDNT1D_ZRI", LIEF::assembly::aarch64::OPCODE::LDNT1D_ZRI) + .value("LDNT1D_ZRR", LIEF::assembly::aarch64::OPCODE::LDNT1D_ZRR) + .value("LDNT1D_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1D_ZZR_D) + .value("LDNT1H_2Z", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z) + .value("LDNT1H_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z_IMM) + .value("LDNT1H_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z_STRIDED) + .value("LDNT1H_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1H_2Z_STRIDED_IMM) + .value("LDNT1H_4Z", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z) + .value("LDNT1H_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z_IMM) + .value("LDNT1H_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z_STRIDED) + .value("LDNT1H_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1H_4Z_STRIDED_IMM) + .value("LDNT1H_ZRI", LIEF::assembly::aarch64::OPCODE::LDNT1H_ZRI) + .value("LDNT1H_ZRR", LIEF::assembly::aarch64::OPCODE::LDNT1H_ZRR) + .value("LDNT1H_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1H_ZZR_D) + .value("LDNT1H_ZZR_S", LIEF::assembly::aarch64::OPCODE::LDNT1H_ZZR_S) + .value("LDNT1SB_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1SB_ZZR_D) + .value("LDNT1SB_ZZR_S", LIEF::assembly::aarch64::OPCODE::LDNT1SB_ZZR_S) + .value("LDNT1SH_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1SH_ZZR_D) + .value("LDNT1SH_ZZR_S", LIEF::assembly::aarch64::OPCODE::LDNT1SH_ZZR_S) + .value("LDNT1SW_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1SW_ZZR_D) + .value("LDNT1W_2Z", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z) + .value("LDNT1W_2Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z_IMM) + .value("LDNT1W_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z_STRIDED) + .value("LDNT1W_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1W_2Z_STRIDED_IMM) + .value("LDNT1W_4Z", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z) + .value("LDNT1W_4Z_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z_IMM) + .value("LDNT1W_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z_STRIDED) + .value("LDNT1W_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::LDNT1W_4Z_STRIDED_IMM) + .value("LDNT1W_ZRI", LIEF::assembly::aarch64::OPCODE::LDNT1W_ZRI) + .value("LDNT1W_ZRR", LIEF::assembly::aarch64::OPCODE::LDNT1W_ZRR) + .value("LDNT1W_ZZR_D", LIEF::assembly::aarch64::OPCODE::LDNT1W_ZZR_D) + .value("LDNT1W_ZZR_S", LIEF::assembly::aarch64::OPCODE::LDNT1W_ZZR_S) + .value("LDPDi", LIEF::assembly::aarch64::OPCODE::LDPDi) + .value("LDPDpost", LIEF::assembly::aarch64::OPCODE::LDPDpost) + .value("LDPDpre", LIEF::assembly::aarch64::OPCODE::LDPDpre) + .value("LDPQi", LIEF::assembly::aarch64::OPCODE::LDPQi) + .value("LDPQpost", LIEF::assembly::aarch64::OPCODE::LDPQpost) + .value("LDPQpre", LIEF::assembly::aarch64::OPCODE::LDPQpre) + .value("LDPSWi", LIEF::assembly::aarch64::OPCODE::LDPSWi) + .value("LDPSWpost", LIEF::assembly::aarch64::OPCODE::LDPSWpost) + .value("LDPSWpre", LIEF::assembly::aarch64::OPCODE::LDPSWpre) + .value("LDPSi", LIEF::assembly::aarch64::OPCODE::LDPSi) + .value("LDPSpost", LIEF::assembly::aarch64::OPCODE::LDPSpost) + .value("LDPSpre", LIEF::assembly::aarch64::OPCODE::LDPSpre) + .value("LDPWi", LIEF::assembly::aarch64::OPCODE::LDPWi) + .value("LDPWpost", LIEF::assembly::aarch64::OPCODE::LDPWpost) + .value("LDPWpre", LIEF::assembly::aarch64::OPCODE::LDPWpre) + .value("LDPXi", LIEF::assembly::aarch64::OPCODE::LDPXi) + .value("LDPXpost", LIEF::assembly::aarch64::OPCODE::LDPXpost) + .value("LDPXpre", LIEF::assembly::aarch64::OPCODE::LDPXpre) + .value("LDRAAindexed", LIEF::assembly::aarch64::OPCODE::LDRAAindexed) + .value("LDRAAwriteback", LIEF::assembly::aarch64::OPCODE::LDRAAwriteback) + .value("LDRABindexed", LIEF::assembly::aarch64::OPCODE::LDRABindexed) + .value("LDRABwriteback", LIEF::assembly::aarch64::OPCODE::LDRABwriteback) + .value("LDRBBpost", LIEF::assembly::aarch64::OPCODE::LDRBBpost) + .value("LDRBBpre", LIEF::assembly::aarch64::OPCODE::LDRBBpre) + .value("LDRBBroW", LIEF::assembly::aarch64::OPCODE::LDRBBroW) + .value("LDRBBroX", LIEF::assembly::aarch64::OPCODE::LDRBBroX) + .value("LDRBBui", LIEF::assembly::aarch64::OPCODE::LDRBBui) + .value("LDRBpost", LIEF::assembly::aarch64::OPCODE::LDRBpost) + .value("LDRBpre", LIEF::assembly::aarch64::OPCODE::LDRBpre) + .value("LDRBroW", LIEF::assembly::aarch64::OPCODE::LDRBroW) + .value("LDRBroX", LIEF::assembly::aarch64::OPCODE::LDRBroX) + .value("LDRBui", LIEF::assembly::aarch64::OPCODE::LDRBui) + .value("LDRDl", LIEF::assembly::aarch64::OPCODE::LDRDl) + .value("LDRDpost", LIEF::assembly::aarch64::OPCODE::LDRDpost) + .value("LDRDpre", LIEF::assembly::aarch64::OPCODE::LDRDpre) + .value("LDRDroW", LIEF::assembly::aarch64::OPCODE::LDRDroW) + .value("LDRDroX", LIEF::assembly::aarch64::OPCODE::LDRDroX) + .value("LDRDui", LIEF::assembly::aarch64::OPCODE::LDRDui) + .value("LDRHHpost", LIEF::assembly::aarch64::OPCODE::LDRHHpost) + .value("LDRHHpre", LIEF::assembly::aarch64::OPCODE::LDRHHpre) + .value("LDRHHroW", LIEF::assembly::aarch64::OPCODE::LDRHHroW) + .value("LDRHHroX", LIEF::assembly::aarch64::OPCODE::LDRHHroX) + .value("LDRHHui", LIEF::assembly::aarch64::OPCODE::LDRHHui) + .value("LDRHpost", LIEF::assembly::aarch64::OPCODE::LDRHpost) + .value("LDRHpre", LIEF::assembly::aarch64::OPCODE::LDRHpre) + .value("LDRHroW", LIEF::assembly::aarch64::OPCODE::LDRHroW) + .value("LDRHroX", LIEF::assembly::aarch64::OPCODE::LDRHroX) + .value("LDRHui", LIEF::assembly::aarch64::OPCODE::LDRHui) + .value("LDRQl", LIEF::assembly::aarch64::OPCODE::LDRQl) + .value("LDRQpost", LIEF::assembly::aarch64::OPCODE::LDRQpost) + .value("LDRQpre", LIEF::assembly::aarch64::OPCODE::LDRQpre) + .value("LDRQroW", LIEF::assembly::aarch64::OPCODE::LDRQroW) + .value("LDRQroX", LIEF::assembly::aarch64::OPCODE::LDRQroX) + .value("LDRQui", LIEF::assembly::aarch64::OPCODE::LDRQui) + .value("LDRSBWpost", LIEF::assembly::aarch64::OPCODE::LDRSBWpost) + .value("LDRSBWpre", LIEF::assembly::aarch64::OPCODE::LDRSBWpre) + .value("LDRSBWroW", LIEF::assembly::aarch64::OPCODE::LDRSBWroW) + .value("LDRSBWroX", LIEF::assembly::aarch64::OPCODE::LDRSBWroX) + .value("LDRSBWui", LIEF::assembly::aarch64::OPCODE::LDRSBWui) + .value("LDRSBXpost", LIEF::assembly::aarch64::OPCODE::LDRSBXpost) + .value("LDRSBXpre", LIEF::assembly::aarch64::OPCODE::LDRSBXpre) + .value("LDRSBXroW", LIEF::assembly::aarch64::OPCODE::LDRSBXroW) + .value("LDRSBXroX", LIEF::assembly::aarch64::OPCODE::LDRSBXroX) + .value("LDRSBXui", LIEF::assembly::aarch64::OPCODE::LDRSBXui) + .value("LDRSHWpost", LIEF::assembly::aarch64::OPCODE::LDRSHWpost) + .value("LDRSHWpre", LIEF::assembly::aarch64::OPCODE::LDRSHWpre) + .value("LDRSHWroW", LIEF::assembly::aarch64::OPCODE::LDRSHWroW) + .value("LDRSHWroX", LIEF::assembly::aarch64::OPCODE::LDRSHWroX) + .value("LDRSHWui", LIEF::assembly::aarch64::OPCODE::LDRSHWui) + .value("LDRSHXpost", LIEF::assembly::aarch64::OPCODE::LDRSHXpost) + .value("LDRSHXpre", LIEF::assembly::aarch64::OPCODE::LDRSHXpre) + .value("LDRSHXroW", LIEF::assembly::aarch64::OPCODE::LDRSHXroW) + .value("LDRSHXroX", LIEF::assembly::aarch64::OPCODE::LDRSHXroX) + .value("LDRSHXui", LIEF::assembly::aarch64::OPCODE::LDRSHXui) + .value("LDRSWl", LIEF::assembly::aarch64::OPCODE::LDRSWl) + .value("LDRSWpost", LIEF::assembly::aarch64::OPCODE::LDRSWpost) + .value("LDRSWpre", LIEF::assembly::aarch64::OPCODE::LDRSWpre) + .value("LDRSWroW", LIEF::assembly::aarch64::OPCODE::LDRSWroW) + .value("LDRSWroX", LIEF::assembly::aarch64::OPCODE::LDRSWroX) + .value("LDRSWui", LIEF::assembly::aarch64::OPCODE::LDRSWui) + .value("LDRSl", LIEF::assembly::aarch64::OPCODE::LDRSl) + .value("LDRSpost", LIEF::assembly::aarch64::OPCODE::LDRSpost) + .value("LDRSpre", LIEF::assembly::aarch64::OPCODE::LDRSpre) + .value("LDRSroW", LIEF::assembly::aarch64::OPCODE::LDRSroW) + .value("LDRSroX", LIEF::assembly::aarch64::OPCODE::LDRSroX) + .value("LDRSui", LIEF::assembly::aarch64::OPCODE::LDRSui) + .value("LDRWl", LIEF::assembly::aarch64::OPCODE::LDRWl) + .value("LDRWpost", LIEF::assembly::aarch64::OPCODE::LDRWpost) + .value("LDRWpre", LIEF::assembly::aarch64::OPCODE::LDRWpre) + .value("LDRWroW", LIEF::assembly::aarch64::OPCODE::LDRWroW); + opcodes.value("LDRWroX", LIEF::assembly::aarch64::OPCODE::LDRWroX) + .value("LDRWui", LIEF::assembly::aarch64::OPCODE::LDRWui) + .value("LDRXl", LIEF::assembly::aarch64::OPCODE::LDRXl) + .value("LDRXpost", LIEF::assembly::aarch64::OPCODE::LDRXpost) + .value("LDRXpre", LIEF::assembly::aarch64::OPCODE::LDRXpre) + .value("LDRXroW", LIEF::assembly::aarch64::OPCODE::LDRXroW) + .value("LDRXroX", LIEF::assembly::aarch64::OPCODE::LDRXroX) + .value("LDRXui", LIEF::assembly::aarch64::OPCODE::LDRXui) + .value("LDR_PXI", LIEF::assembly::aarch64::OPCODE::LDR_PXI) + .value("LDR_TX", LIEF::assembly::aarch64::OPCODE::LDR_TX) + .value("LDR_ZA", LIEF::assembly::aarch64::OPCODE::LDR_ZA) + .value("LDR_ZXI", LIEF::assembly::aarch64::OPCODE::LDR_ZXI) + .value("LDSETAB", LIEF::assembly::aarch64::OPCODE::LDSETAB) + .value("LDSETAH", LIEF::assembly::aarch64::OPCODE::LDSETAH) + .value("LDSETALB", LIEF::assembly::aarch64::OPCODE::LDSETALB) + .value("LDSETALH", LIEF::assembly::aarch64::OPCODE::LDSETALH) + .value("LDSETALW", LIEF::assembly::aarch64::OPCODE::LDSETALW) + .value("LDSETALX", LIEF::assembly::aarch64::OPCODE::LDSETALX) + .value("LDSETAW", LIEF::assembly::aarch64::OPCODE::LDSETAW) + .value("LDSETAX", LIEF::assembly::aarch64::OPCODE::LDSETAX) + .value("LDSETB", LIEF::assembly::aarch64::OPCODE::LDSETB) + .value("LDSETH", LIEF::assembly::aarch64::OPCODE::LDSETH) + .value("LDSETLB", LIEF::assembly::aarch64::OPCODE::LDSETLB) + .value("LDSETLH", LIEF::assembly::aarch64::OPCODE::LDSETLH) + .value("LDSETLW", LIEF::assembly::aarch64::OPCODE::LDSETLW) + .value("LDSETLX", LIEF::assembly::aarch64::OPCODE::LDSETLX) + .value("LDSETP", LIEF::assembly::aarch64::OPCODE::LDSETP) + .value("LDSETPA", LIEF::assembly::aarch64::OPCODE::LDSETPA) + .value("LDSETPAL", LIEF::assembly::aarch64::OPCODE::LDSETPAL) + .value("LDSETPL", LIEF::assembly::aarch64::OPCODE::LDSETPL) + .value("LDSETW", LIEF::assembly::aarch64::OPCODE::LDSETW) + .value("LDSETX", LIEF::assembly::aarch64::OPCODE::LDSETX) + .value("LDSMAXAB", LIEF::assembly::aarch64::OPCODE::LDSMAXAB) + .value("LDSMAXAH", LIEF::assembly::aarch64::OPCODE::LDSMAXAH) + .value("LDSMAXALB", LIEF::assembly::aarch64::OPCODE::LDSMAXALB) + .value("LDSMAXALH", LIEF::assembly::aarch64::OPCODE::LDSMAXALH) + .value("LDSMAXALW", LIEF::assembly::aarch64::OPCODE::LDSMAXALW) + .value("LDSMAXALX", LIEF::assembly::aarch64::OPCODE::LDSMAXALX) + .value("LDSMAXAW", LIEF::assembly::aarch64::OPCODE::LDSMAXAW) + .value("LDSMAXAX", LIEF::assembly::aarch64::OPCODE::LDSMAXAX) + .value("LDSMAXB", LIEF::assembly::aarch64::OPCODE::LDSMAXB) + .value("LDSMAXH", LIEF::assembly::aarch64::OPCODE::LDSMAXH) + .value("LDSMAXLB", LIEF::assembly::aarch64::OPCODE::LDSMAXLB) + .value("LDSMAXLH", LIEF::assembly::aarch64::OPCODE::LDSMAXLH) + .value("LDSMAXLW", LIEF::assembly::aarch64::OPCODE::LDSMAXLW) + .value("LDSMAXLX", LIEF::assembly::aarch64::OPCODE::LDSMAXLX) + .value("LDSMAXW", LIEF::assembly::aarch64::OPCODE::LDSMAXW) + .value("LDSMAXX", LIEF::assembly::aarch64::OPCODE::LDSMAXX) + .value("LDSMINAB", LIEF::assembly::aarch64::OPCODE::LDSMINAB) + .value("LDSMINAH", LIEF::assembly::aarch64::OPCODE::LDSMINAH) + .value("LDSMINALB", LIEF::assembly::aarch64::OPCODE::LDSMINALB) + .value("LDSMINALH", LIEF::assembly::aarch64::OPCODE::LDSMINALH) + .value("LDSMINALW", LIEF::assembly::aarch64::OPCODE::LDSMINALW) + .value("LDSMINALX", LIEF::assembly::aarch64::OPCODE::LDSMINALX) + .value("LDSMINAW", LIEF::assembly::aarch64::OPCODE::LDSMINAW) + .value("LDSMINAX", LIEF::assembly::aarch64::OPCODE::LDSMINAX) + .value("LDSMINB", LIEF::assembly::aarch64::OPCODE::LDSMINB) + .value("LDSMINH", LIEF::assembly::aarch64::OPCODE::LDSMINH) + .value("LDSMINLB", LIEF::assembly::aarch64::OPCODE::LDSMINLB) + .value("LDSMINLH", LIEF::assembly::aarch64::OPCODE::LDSMINLH) + .value("LDSMINLW", LIEF::assembly::aarch64::OPCODE::LDSMINLW) + .value("LDSMINLX", LIEF::assembly::aarch64::OPCODE::LDSMINLX) + .value("LDSMINW", LIEF::assembly::aarch64::OPCODE::LDSMINW) + .value("LDSMINX", LIEF::assembly::aarch64::OPCODE::LDSMINX) + .value("LDTADDALW", LIEF::assembly::aarch64::OPCODE::LDTADDALW) + .value("LDTADDALX", LIEF::assembly::aarch64::OPCODE::LDTADDALX) + .value("LDTADDAW", LIEF::assembly::aarch64::OPCODE::LDTADDAW) + .value("LDTADDAX", LIEF::assembly::aarch64::OPCODE::LDTADDAX) + .value("LDTADDLW", LIEF::assembly::aarch64::OPCODE::LDTADDLW) + .value("LDTADDLX", LIEF::assembly::aarch64::OPCODE::LDTADDLX) + .value("LDTADDW", LIEF::assembly::aarch64::OPCODE::LDTADDW) + .value("LDTADDX", LIEF::assembly::aarch64::OPCODE::LDTADDX) + .value("LDTCLRALW", LIEF::assembly::aarch64::OPCODE::LDTCLRALW) + .value("LDTCLRALX", LIEF::assembly::aarch64::OPCODE::LDTCLRALX) + .value("LDTCLRAW", LIEF::assembly::aarch64::OPCODE::LDTCLRAW) + .value("LDTCLRAX", LIEF::assembly::aarch64::OPCODE::LDTCLRAX) + .value("LDTCLRLW", LIEF::assembly::aarch64::OPCODE::LDTCLRLW) + .value("LDTCLRLX", LIEF::assembly::aarch64::OPCODE::LDTCLRLX) + .value("LDTCLRW", LIEF::assembly::aarch64::OPCODE::LDTCLRW) + .value("LDTCLRX", LIEF::assembly::aarch64::OPCODE::LDTCLRX) + .value("LDTNPQi", LIEF::assembly::aarch64::OPCODE::LDTNPQi) + .value("LDTNPXi", LIEF::assembly::aarch64::OPCODE::LDTNPXi) + .value("LDTPQi", LIEF::assembly::aarch64::OPCODE::LDTPQi) + .value("LDTPQpost", LIEF::assembly::aarch64::OPCODE::LDTPQpost) + .value("LDTPQpre", LIEF::assembly::aarch64::OPCODE::LDTPQpre) + .value("LDTPi", LIEF::assembly::aarch64::OPCODE::LDTPi) + .value("LDTPpost", LIEF::assembly::aarch64::OPCODE::LDTPpost) + .value("LDTPpre", LIEF::assembly::aarch64::OPCODE::LDTPpre) + .value("LDTRBi", LIEF::assembly::aarch64::OPCODE::LDTRBi) + .value("LDTRHi", LIEF::assembly::aarch64::OPCODE::LDTRHi) + .value("LDTRSBWi", LIEF::assembly::aarch64::OPCODE::LDTRSBWi) + .value("LDTRSBXi", LIEF::assembly::aarch64::OPCODE::LDTRSBXi) + .value("LDTRSHWi", LIEF::assembly::aarch64::OPCODE::LDTRSHWi) + .value("LDTRSHXi", LIEF::assembly::aarch64::OPCODE::LDTRSHXi) + .value("LDTRSWi", LIEF::assembly::aarch64::OPCODE::LDTRSWi) + .value("LDTRWi", LIEF::assembly::aarch64::OPCODE::LDTRWi) + .value("LDTRXi", LIEF::assembly::aarch64::OPCODE::LDTRXi) + .value("LDTSETALW", LIEF::assembly::aarch64::OPCODE::LDTSETALW) + .value("LDTSETALX", LIEF::assembly::aarch64::OPCODE::LDTSETALX) + .value("LDTSETAW", LIEF::assembly::aarch64::OPCODE::LDTSETAW) + .value("LDTSETAX", LIEF::assembly::aarch64::OPCODE::LDTSETAX) + .value("LDTSETLW", LIEF::assembly::aarch64::OPCODE::LDTSETLW) + .value("LDTSETLX", LIEF::assembly::aarch64::OPCODE::LDTSETLX) + .value("LDTSETW", LIEF::assembly::aarch64::OPCODE::LDTSETW) + .value("LDTSETX", LIEF::assembly::aarch64::OPCODE::LDTSETX) + .value("LDTXRWr", LIEF::assembly::aarch64::OPCODE::LDTXRWr) + .value("LDTXRXr", LIEF::assembly::aarch64::OPCODE::LDTXRXr) + .value("LDUMAXAB", LIEF::assembly::aarch64::OPCODE::LDUMAXAB) + .value("LDUMAXAH", LIEF::assembly::aarch64::OPCODE::LDUMAXAH) + .value("LDUMAXALB", LIEF::assembly::aarch64::OPCODE::LDUMAXALB) + .value("LDUMAXALH", LIEF::assembly::aarch64::OPCODE::LDUMAXALH) + .value("LDUMAXALW", LIEF::assembly::aarch64::OPCODE::LDUMAXALW) + .value("LDUMAXALX", LIEF::assembly::aarch64::OPCODE::LDUMAXALX) + .value("LDUMAXAW", LIEF::assembly::aarch64::OPCODE::LDUMAXAW) + .value("LDUMAXAX", LIEF::assembly::aarch64::OPCODE::LDUMAXAX) + .value("LDUMAXB", LIEF::assembly::aarch64::OPCODE::LDUMAXB) + .value("LDUMAXH", LIEF::assembly::aarch64::OPCODE::LDUMAXH) + .value("LDUMAXLB", LIEF::assembly::aarch64::OPCODE::LDUMAXLB) + .value("LDUMAXLH", LIEF::assembly::aarch64::OPCODE::LDUMAXLH) + .value("LDUMAXLW", LIEF::assembly::aarch64::OPCODE::LDUMAXLW) + .value("LDUMAXLX", LIEF::assembly::aarch64::OPCODE::LDUMAXLX) + .value("LDUMAXW", LIEF::assembly::aarch64::OPCODE::LDUMAXW) + .value("LDUMAXX", LIEF::assembly::aarch64::OPCODE::LDUMAXX) + .value("LDUMINAB", LIEF::assembly::aarch64::OPCODE::LDUMINAB) + .value("LDUMINAH", LIEF::assembly::aarch64::OPCODE::LDUMINAH) + .value("LDUMINALB", LIEF::assembly::aarch64::OPCODE::LDUMINALB) + .value("LDUMINALH", LIEF::assembly::aarch64::OPCODE::LDUMINALH) + .value("LDUMINALW", LIEF::assembly::aarch64::OPCODE::LDUMINALW) + .value("LDUMINALX", LIEF::assembly::aarch64::OPCODE::LDUMINALX) + .value("LDUMINAW", LIEF::assembly::aarch64::OPCODE::LDUMINAW) + .value("LDUMINAX", LIEF::assembly::aarch64::OPCODE::LDUMINAX) + .value("LDUMINB", LIEF::assembly::aarch64::OPCODE::LDUMINB) + .value("LDUMINH", LIEF::assembly::aarch64::OPCODE::LDUMINH) + .value("LDUMINLB", LIEF::assembly::aarch64::OPCODE::LDUMINLB) + .value("LDUMINLH", LIEF::assembly::aarch64::OPCODE::LDUMINLH) + .value("LDUMINLW", LIEF::assembly::aarch64::OPCODE::LDUMINLW) + .value("LDUMINLX", LIEF::assembly::aarch64::OPCODE::LDUMINLX) + .value("LDUMINW", LIEF::assembly::aarch64::OPCODE::LDUMINW) + .value("LDUMINX", LIEF::assembly::aarch64::OPCODE::LDUMINX) + .value("LDURBBi", LIEF::assembly::aarch64::OPCODE::LDURBBi) + .value("LDURBi", LIEF::assembly::aarch64::OPCODE::LDURBi) + .value("LDURDi", LIEF::assembly::aarch64::OPCODE::LDURDi) + .value("LDURHHi", LIEF::assembly::aarch64::OPCODE::LDURHHi) + .value("LDURHi", LIEF::assembly::aarch64::OPCODE::LDURHi) + .value("LDURQi", LIEF::assembly::aarch64::OPCODE::LDURQi) + .value("LDURSBWi", LIEF::assembly::aarch64::OPCODE::LDURSBWi) + .value("LDURSBXi", LIEF::assembly::aarch64::OPCODE::LDURSBXi) + .value("LDURSHWi", LIEF::assembly::aarch64::OPCODE::LDURSHWi) + .value("LDURSHXi", LIEF::assembly::aarch64::OPCODE::LDURSHXi) + .value("LDURSWi", LIEF::assembly::aarch64::OPCODE::LDURSWi) + .value("LDURSi", LIEF::assembly::aarch64::OPCODE::LDURSi) + .value("LDURWi", LIEF::assembly::aarch64::OPCODE::LDURWi) + .value("LDURXi", LIEF::assembly::aarch64::OPCODE::LDURXi) + .value("LDXPW", LIEF::assembly::aarch64::OPCODE::LDXPW) + .value("LDXPX", LIEF::assembly::aarch64::OPCODE::LDXPX) + .value("LDXRB", LIEF::assembly::aarch64::OPCODE::LDXRB) + .value("LDXRH", LIEF::assembly::aarch64::OPCODE::LDXRH) + .value("LDXRW", LIEF::assembly::aarch64::OPCODE::LDXRW) + .value("LDXRX", LIEF::assembly::aarch64::OPCODE::LDXRX) + .value("LSLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSLR_ZPmZ_B) + .value("LSLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::LSLR_ZPmZ_D) + .value("LSLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSLR_ZPmZ_H) + .value("LSLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSLR_ZPmZ_S) + .value("LSLVWr", LIEF::assembly::aarch64::OPCODE::LSLVWr) + .value("LSLVXr", LIEF::assembly::aarch64::OPCODE::LSLVXr) + .value("LSL_WIDE_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZPmZ_B) + .value("LSL_WIDE_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZPmZ_H) + .value("LSL_WIDE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZPmZ_S) + .value("LSL_WIDE_ZZZ_B", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZZZ_B) + .value("LSL_WIDE_ZZZ_H", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZZZ_H) + .value("LSL_WIDE_ZZZ_S", LIEF::assembly::aarch64::OPCODE::LSL_WIDE_ZZZ_S) + .value("LSL_ZPmI_B", LIEF::assembly::aarch64::OPCODE::LSL_ZPmI_B) + .value("LSL_ZPmI_D", LIEF::assembly::aarch64::OPCODE::LSL_ZPmI_D) + .value("LSL_ZPmI_H", LIEF::assembly::aarch64::OPCODE::LSL_ZPmI_H) + .value("LSL_ZPmI_S", LIEF::assembly::aarch64::OPCODE::LSL_ZPmI_S) + .value("LSL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSL_ZPmZ_B) + .value("LSL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::LSL_ZPmZ_D) + .value("LSL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSL_ZPmZ_H) + .value("LSL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSL_ZPmZ_S) + .value("LSL_ZZI_B", LIEF::assembly::aarch64::OPCODE::LSL_ZZI_B) + .value("LSL_ZZI_D", LIEF::assembly::aarch64::OPCODE::LSL_ZZI_D) + .value("LSL_ZZI_H", LIEF::assembly::aarch64::OPCODE::LSL_ZZI_H) + .value("LSL_ZZI_S", LIEF::assembly::aarch64::OPCODE::LSL_ZZI_S) + .value("LSRR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSRR_ZPmZ_B) + .value("LSRR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::LSRR_ZPmZ_D) + .value("LSRR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSRR_ZPmZ_H) + .value("LSRR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSRR_ZPmZ_S) + .value("LSRVWr", LIEF::assembly::aarch64::OPCODE::LSRVWr) + .value("LSRVXr", LIEF::assembly::aarch64::OPCODE::LSRVXr) + .value("LSR_WIDE_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZPmZ_B) + .value("LSR_WIDE_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZPmZ_H) + .value("LSR_WIDE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZPmZ_S) + .value("LSR_WIDE_ZZZ_B", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZZZ_B) + .value("LSR_WIDE_ZZZ_H", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZZZ_H) + .value("LSR_WIDE_ZZZ_S", LIEF::assembly::aarch64::OPCODE::LSR_WIDE_ZZZ_S) + .value("LSR_ZPmI_B", LIEF::assembly::aarch64::OPCODE::LSR_ZPmI_B) + .value("LSR_ZPmI_D", LIEF::assembly::aarch64::OPCODE::LSR_ZPmI_D) + .value("LSR_ZPmI_H", LIEF::assembly::aarch64::OPCODE::LSR_ZPmI_H) + .value("LSR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::LSR_ZPmI_S) + .value("LSR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::LSR_ZPmZ_B) + .value("LSR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::LSR_ZPmZ_D) + .value("LSR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::LSR_ZPmZ_H) + .value("LSR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::LSR_ZPmZ_S) + .value("LSR_ZZI_B", LIEF::assembly::aarch64::OPCODE::LSR_ZZI_B) + .value("LSR_ZZI_D", LIEF::assembly::aarch64::OPCODE::LSR_ZZI_D) + .value("LSR_ZZI_H", LIEF::assembly::aarch64::OPCODE::LSR_ZZI_H) + .value("LSR_ZZI_S", LIEF::assembly::aarch64::OPCODE::LSR_ZZI_S) + .value("LUT2_B", LIEF::assembly::aarch64::OPCODE::LUT2_B) + .value("LUT2_H", LIEF::assembly::aarch64::OPCODE::LUT2_H) + .value("LUT4_B", LIEF::assembly::aarch64::OPCODE::LUT4_B) + .value("LUT4_H", LIEF::assembly::aarch64::OPCODE::LUT4_H) + .value("LUTI2_2ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_2ZTZI_B) + .value("LUTI2_2ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_2ZTZI_H) + .value("LUTI2_2ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI2_2ZTZI_S) + .value("LUTI2_4ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_4ZTZI_B) + .value("LUTI2_4ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_4ZTZI_H) + .value("LUTI2_4ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI2_4ZTZI_S) + .value("LUTI2_S_2ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_S_2ZTZI_B) + .value("LUTI2_S_2ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_S_2ZTZI_H) + .value("LUTI2_S_4ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_S_4ZTZI_B) + .value("LUTI2_S_4ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_S_4ZTZI_H) + .value("LUTI2_ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_ZTZI_B) + .value("LUTI2_ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_ZTZI_H) + .value("LUTI2_ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI2_ZTZI_S) + .value("LUTI2_ZZZI_B", LIEF::assembly::aarch64::OPCODE::LUTI2_ZZZI_B) + .value("LUTI2_ZZZI_H", LIEF::assembly::aarch64::OPCODE::LUTI2_ZZZI_H) + .value("LUTI4_2ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_2ZTZI_B) + .value("LUTI4_2ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_2ZTZI_H) + .value("LUTI4_2ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI4_2ZTZI_S) + .value("LUTI4_4ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_4ZTZI_H) + .value("LUTI4_4ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI4_4ZTZI_S) + .value("LUTI4_4ZZT2Z", LIEF::assembly::aarch64::OPCODE::LUTI4_4ZZT2Z) + .value("LUTI4_S_2ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_S_2ZTZI_B) + .value("LUTI4_S_2ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_S_2ZTZI_H) + .value("LUTI4_S_4ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_S_4ZTZI_H) + .value("LUTI4_S_4ZZT2Z", LIEF::assembly::aarch64::OPCODE::LUTI4_S_4ZZT2Z) + .value("LUTI4_Z2ZZI", LIEF::assembly::aarch64::OPCODE::LUTI4_Z2ZZI) + .value("LUTI4_ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_B) + .value("LUTI4_ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_H) + .value("LUTI4_ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_S) + .value("LUTI4_ZZZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_ZZZI_B) + .value("LUTI4_ZZZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_ZZZI_H) + .value("LUTI6_4Z2Z2ZI", LIEF::assembly::aarch64::OPCODE::LUTI6_4Z2Z2ZI) + .value("LUTI6_4ZT3Z", LIEF::assembly::aarch64::OPCODE::LUTI6_4ZT3Z) + .value("LUTI6_S_4Z2Z2ZI", LIEF::assembly::aarch64::OPCODE::LUTI6_S_4Z2Z2ZI) + .value("LUTI6_S_4ZT3Z", LIEF::assembly::aarch64::OPCODE::LUTI6_S_4ZT3Z) + .value("LUTI6_Z2ZZ", LIEF::assembly::aarch64::OPCODE::LUTI6_Z2ZZ) + .value("LUTI6_Z2ZZI_H", LIEF::assembly::aarch64::OPCODE::LUTI6_Z2ZZI_H) + .value("LUTI6_ZTZ", LIEF::assembly::aarch64::OPCODE::LUTI6_ZTZ) + .value("MADDPT", LIEF::assembly::aarch64::OPCODE::MADDPT) + .value("MADDWrrr", LIEF::assembly::aarch64::OPCODE::MADDWrrr) + .value("MADDXrrr", LIEF::assembly::aarch64::OPCODE::MADDXrrr) + .value("MAD_CPA", LIEF::assembly::aarch64::OPCODE::MAD_CPA) + .value("MAD_ZPmZZ_B", LIEF::assembly::aarch64::OPCODE::MAD_ZPmZZ_B) + .value("MAD_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::MAD_ZPmZZ_D) + .value("MAD_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::MAD_ZPmZZ_H) + .value("MAD_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::MAD_ZPmZZ_S) + .value("MATCH_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::MATCH_PPzZZ_B) + .value("MATCH_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::MATCH_PPzZZ_H) + .value("MLA_CPA", LIEF::assembly::aarch64::OPCODE::MLA_CPA) + .value("MLA_ZPmZZ_B", LIEF::assembly::aarch64::OPCODE::MLA_ZPmZZ_B) + .value("MLA_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::MLA_ZPmZZ_D) + .value("MLA_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::MLA_ZPmZZ_H) + .value("MLA_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::MLA_ZPmZZ_S) + .value("MLA_ZZZI_D", LIEF::assembly::aarch64::OPCODE::MLA_ZZZI_D) + .value("MLA_ZZZI_H", LIEF::assembly::aarch64::OPCODE::MLA_ZZZI_H) + .value("MLA_ZZZI_S", LIEF::assembly::aarch64::OPCODE::MLA_ZZZI_S) + .value("MLAv16i8", LIEF::assembly::aarch64::OPCODE::MLAv16i8) + .value("MLAv2i32", LIEF::assembly::aarch64::OPCODE::MLAv2i32) + .value("MLAv2i32_indexed", LIEF::assembly::aarch64::OPCODE::MLAv2i32_indexed) + .value("MLAv4i16", LIEF::assembly::aarch64::OPCODE::MLAv4i16) + .value("MLAv4i16_indexed", LIEF::assembly::aarch64::OPCODE::MLAv4i16_indexed) + .value("MLAv4i32", LIEF::assembly::aarch64::OPCODE::MLAv4i32) + .value("MLAv4i32_indexed", LIEF::assembly::aarch64::OPCODE::MLAv4i32_indexed) + .value("MLAv8i16", LIEF::assembly::aarch64::OPCODE::MLAv8i16) + .value("MLAv8i16_indexed", LIEF::assembly::aarch64::OPCODE::MLAv8i16_indexed) + .value("MLAv8i8", LIEF::assembly::aarch64::OPCODE::MLAv8i8) + .value("MLS_ZPmZZ_B", LIEF::assembly::aarch64::OPCODE::MLS_ZPmZZ_B) + .value("MLS_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::MLS_ZPmZZ_D) + .value("MLS_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::MLS_ZPmZZ_H) + .value("MLS_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::MLS_ZPmZZ_S) + .value("MLS_ZZZI_D", LIEF::assembly::aarch64::OPCODE::MLS_ZZZI_D) + .value("MLS_ZZZI_H", LIEF::assembly::aarch64::OPCODE::MLS_ZZZI_H) + .value("MLS_ZZZI_S", LIEF::assembly::aarch64::OPCODE::MLS_ZZZI_S) + .value("MLSv16i8", LIEF::assembly::aarch64::OPCODE::MLSv16i8) + .value("MLSv2i32", LIEF::assembly::aarch64::OPCODE::MLSv2i32) + .value("MLSv2i32_indexed", LIEF::assembly::aarch64::OPCODE::MLSv2i32_indexed) + .value("MLSv4i16", LIEF::assembly::aarch64::OPCODE::MLSv4i16) + .value("MLSv4i16_indexed", LIEF::assembly::aarch64::OPCODE::MLSv4i16_indexed) + .value("MLSv4i32", LIEF::assembly::aarch64::OPCODE::MLSv4i32) + .value("MLSv4i32_indexed", LIEF::assembly::aarch64::OPCODE::MLSv4i32_indexed) + .value("MLSv8i16", LIEF::assembly::aarch64::OPCODE::MLSv8i16) + .value("MLSv8i16_indexed", LIEF::assembly::aarch64::OPCODE::MLSv8i16_indexed) + .value("MLSv8i8", LIEF::assembly::aarch64::OPCODE::MLSv8i8) + .value("MOPSSETGE", LIEF::assembly::aarch64::OPCODE::MOPSSETGE) + .value("MOPSSETGEN", LIEF::assembly::aarch64::OPCODE::MOPSSETGEN) + .value("MOPSSETGET", LIEF::assembly::aarch64::OPCODE::MOPSSETGET) + .value("MOPSSETGETN", LIEF::assembly::aarch64::OPCODE::MOPSSETGETN) + .value("MOVAZ_2ZMI_H_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_B) + .value("MOVAZ_2ZMI_H_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_D); + opcodes.value("MOVAZ_2ZMI_H_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_H) + .value("MOVAZ_2ZMI_H_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_S) + .value("MOVAZ_2ZMI_V_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_B) + .value("MOVAZ_2ZMI_V_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_D) + .value("MOVAZ_2ZMI_V_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_H) + .value("MOVAZ_2ZMI_V_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_S) + .value("MOVAZ_4ZMI_H_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_B) + .value("MOVAZ_4ZMI_H_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_D) + .value("MOVAZ_4ZMI_H_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_H) + .value("MOVAZ_4ZMI_H_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_H_S) + .value("MOVAZ_4ZMI_V_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_B) + .value("MOVAZ_4ZMI_V_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_D) + .value("MOVAZ_4ZMI_V_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_H) + .value("MOVAZ_4ZMI_V_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_4ZMI_V_S) + .value("MOVAZ_VG2_2ZMXI", LIEF::assembly::aarch64::OPCODE::MOVAZ_VG2_2ZMXI) + .value("MOVAZ_VG4_4ZMXI", LIEF::assembly::aarch64::OPCODE::MOVAZ_VG4_4ZMXI) + .value("MOVAZ_ZMI_H_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_B) + .value("MOVAZ_ZMI_H_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_D) + .value("MOVAZ_ZMI_H_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_H) + .value("MOVAZ_ZMI_H_Q", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_Q) + .value("MOVAZ_ZMI_H_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_H_S) + .value("MOVAZ_ZMI_V_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_B) + .value("MOVAZ_ZMI_V_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_D) + .value("MOVAZ_ZMI_V_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_H) + .value("MOVAZ_ZMI_V_Q", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_Q) + .value("MOVAZ_ZMI_V_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_ZMI_V_S) + .value("MOVA_2ZMXI_H_B", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_H_B) + .value("MOVA_2ZMXI_H_D", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_H_D) + .value("MOVA_2ZMXI_H_H", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_H_H) + .value("MOVA_2ZMXI_H_S", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_H_S) + .value("MOVA_2ZMXI_V_B", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_V_B) + .value("MOVA_2ZMXI_V_D", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_V_D) + .value("MOVA_2ZMXI_V_H", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_V_H) + .value("MOVA_2ZMXI_V_S", LIEF::assembly::aarch64::OPCODE::MOVA_2ZMXI_V_S) + .value("MOVA_4ZMXI_H_B", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_H_B) + .value("MOVA_4ZMXI_H_D", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_H_D) + .value("MOVA_4ZMXI_H_H", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_H_H) + .value("MOVA_4ZMXI_H_S", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_H_S) + .value("MOVA_4ZMXI_V_B", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_V_B) + .value("MOVA_4ZMXI_V_D", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_V_D) + .value("MOVA_4ZMXI_V_H", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_V_H) + .value("MOVA_4ZMXI_V_S", LIEF::assembly::aarch64::OPCODE::MOVA_4ZMXI_V_S) + .value("MOVA_MXI2Z_H_B", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_B) + .value("MOVA_MXI2Z_H_D", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_D) + .value("MOVA_MXI2Z_H_H", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_H) + .value("MOVA_MXI2Z_H_S", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_H_S) + .value("MOVA_MXI2Z_V_B", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_B) + .value("MOVA_MXI2Z_V_D", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_D) + .value("MOVA_MXI2Z_V_H", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_H) + .value("MOVA_MXI2Z_V_S", LIEF::assembly::aarch64::OPCODE::MOVA_MXI2Z_V_S) + .value("MOVA_MXI4Z_H_B", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_B) + .value("MOVA_MXI4Z_H_D", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_D) + .value("MOVA_MXI4Z_H_H", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_H) + .value("MOVA_MXI4Z_H_S", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_H_S) + .value("MOVA_MXI4Z_V_B", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_B) + .value("MOVA_MXI4Z_V_D", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_D) + .value("MOVA_MXI4Z_V_H", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_H) + .value("MOVA_MXI4Z_V_S", LIEF::assembly::aarch64::OPCODE::MOVA_MXI4Z_V_S) + .value("MOVA_VG2_2ZMXI", LIEF::assembly::aarch64::OPCODE::MOVA_VG2_2ZMXI) + .value("MOVA_VG2_MXI2Z", LIEF::assembly::aarch64::OPCODE::MOVA_VG2_MXI2Z) + .value("MOVA_VG4_4ZMXI", LIEF::assembly::aarch64::OPCODE::MOVA_VG4_4ZMXI) + .value("MOVA_VG4_MXI4Z", LIEF::assembly::aarch64::OPCODE::MOVA_VG4_MXI4Z) + .value("MOVID", LIEF::assembly::aarch64::OPCODE::MOVID) + .value("MOVIv16b_ns", LIEF::assembly::aarch64::OPCODE::MOVIv16b_ns) + .value("MOVIv2d_ns", LIEF::assembly::aarch64::OPCODE::MOVIv2d_ns) + .value("MOVIv2i32", LIEF::assembly::aarch64::OPCODE::MOVIv2i32) + .value("MOVIv2s_msl", LIEF::assembly::aarch64::OPCODE::MOVIv2s_msl) + .value("MOVIv4i16", LIEF::assembly::aarch64::OPCODE::MOVIv4i16) + .value("MOVIv4i32", LIEF::assembly::aarch64::OPCODE::MOVIv4i32) + .value("MOVIv4s_msl", LIEF::assembly::aarch64::OPCODE::MOVIv4s_msl) + .value("MOVIv8b_ns", LIEF::assembly::aarch64::OPCODE::MOVIv8b_ns) + .value("MOVIv8i16", LIEF::assembly::aarch64::OPCODE::MOVIv8i16) + .value("MOVKWi", LIEF::assembly::aarch64::OPCODE::MOVKWi) + .value("MOVKXi", LIEF::assembly::aarch64::OPCODE::MOVKXi) + .value("MOVNWi", LIEF::assembly::aarch64::OPCODE::MOVNWi) + .value("MOVNXi", LIEF::assembly::aarch64::OPCODE::MOVNXi) + .value("MOVPRFX_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPmZ_B) + .value("MOVPRFX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPmZ_D) + .value("MOVPRFX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPmZ_H) + .value("MOVPRFX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPmZ_S) + .value("MOVPRFX_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPzZ_B) + .value("MOVPRFX_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPzZ_D) + .value("MOVPRFX_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPzZ_H) + .value("MOVPRFX_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZPzZ_S) + .value("MOVPRFX_ZZ", LIEF::assembly::aarch64::OPCODE::MOVPRFX_ZZ) + .value("MOVT_TIX", LIEF::assembly::aarch64::OPCODE::MOVT_TIX) + .value("MOVT_TIZ", LIEF::assembly::aarch64::OPCODE::MOVT_TIZ) + .value("MOVT_XTI", LIEF::assembly::aarch64::OPCODE::MOVT_XTI) + .value("MOVZWi", LIEF::assembly::aarch64::OPCODE::MOVZWi) + .value("MOVZXi", LIEF::assembly::aarch64::OPCODE::MOVZXi) + .value("MRRS", LIEF::assembly::aarch64::OPCODE::MRRS) + .value("MRS", LIEF::assembly::aarch64::OPCODE::MRS) + .value("MSB_ZPmZZ_B", LIEF::assembly::aarch64::OPCODE::MSB_ZPmZZ_B) + .value("MSB_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::MSB_ZPmZZ_D) + .value("MSB_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::MSB_ZPmZZ_H) + .value("MSB_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::MSB_ZPmZZ_S) + .value("MSR", LIEF::assembly::aarch64::OPCODE::MSR) + .value("MSRR", LIEF::assembly::aarch64::OPCODE::MSRR) + .value("MSRpstateImm1", LIEF::assembly::aarch64::OPCODE::MSRpstateImm1) + .value("MSRpstateImm4", LIEF::assembly::aarch64::OPCODE::MSRpstateImm4) + .value("MSRpstatesvcrImm1", LIEF::assembly::aarch64::OPCODE::MSRpstatesvcrImm1) + .value("MSUBPT", LIEF::assembly::aarch64::OPCODE::MSUBPT) + .value("MSUBWrrr", LIEF::assembly::aarch64::OPCODE::MSUBWrrr) + .value("MSUBXrrr", LIEF::assembly::aarch64::OPCODE::MSUBXrrr) + .value("MUL_ZI_B", LIEF::assembly::aarch64::OPCODE::MUL_ZI_B) + .value("MUL_ZI_D", LIEF::assembly::aarch64::OPCODE::MUL_ZI_D) + .value("MUL_ZI_H", LIEF::assembly::aarch64::OPCODE::MUL_ZI_H) + .value("MUL_ZI_S", LIEF::assembly::aarch64::OPCODE::MUL_ZI_S) + .value("MUL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::MUL_ZPmZ_B) + .value("MUL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::MUL_ZPmZ_D) + .value("MUL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::MUL_ZPmZ_H) + .value("MUL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::MUL_ZPmZ_S) + .value("MUL_ZZZI_D", LIEF::assembly::aarch64::OPCODE::MUL_ZZZI_D) + .value("MUL_ZZZI_H", LIEF::assembly::aarch64::OPCODE::MUL_ZZZI_H) + .value("MUL_ZZZI_S", LIEF::assembly::aarch64::OPCODE::MUL_ZZZI_S) + .value("MUL_ZZZ_B", LIEF::assembly::aarch64::OPCODE::MUL_ZZZ_B) + .value("MUL_ZZZ_D", LIEF::assembly::aarch64::OPCODE::MUL_ZZZ_D) + .value("MUL_ZZZ_H", LIEF::assembly::aarch64::OPCODE::MUL_ZZZ_H) + .value("MUL_ZZZ_S", LIEF::assembly::aarch64::OPCODE::MUL_ZZZ_S) + .value("MULv16i8", LIEF::assembly::aarch64::OPCODE::MULv16i8) + .value("MULv2i32", LIEF::assembly::aarch64::OPCODE::MULv2i32) + .value("MULv2i32_indexed", LIEF::assembly::aarch64::OPCODE::MULv2i32_indexed) + .value("MULv4i16", LIEF::assembly::aarch64::OPCODE::MULv4i16) + .value("MULv4i16_indexed", LIEF::assembly::aarch64::OPCODE::MULv4i16_indexed) + .value("MULv4i32", LIEF::assembly::aarch64::OPCODE::MULv4i32) + .value("MULv4i32_indexed", LIEF::assembly::aarch64::OPCODE::MULv4i32_indexed) + .value("MULv8i16", LIEF::assembly::aarch64::OPCODE::MULv8i16) + .value("MULv8i16_indexed", LIEF::assembly::aarch64::OPCODE::MULv8i16_indexed) + .value("MULv8i8", LIEF::assembly::aarch64::OPCODE::MULv8i8) + .value("MVNIv2i32", LIEF::assembly::aarch64::OPCODE::MVNIv2i32) + .value("MVNIv2s_msl", LIEF::assembly::aarch64::OPCODE::MVNIv2s_msl) + .value("MVNIv4i16", LIEF::assembly::aarch64::OPCODE::MVNIv4i16) + .value("MVNIv4i32", LIEF::assembly::aarch64::OPCODE::MVNIv4i32) + .value("MVNIv4s_msl", LIEF::assembly::aarch64::OPCODE::MVNIv4s_msl) + .value("MVNIv8i16", LIEF::assembly::aarch64::OPCODE::MVNIv8i16) + .value("NANDS_PPzPP", LIEF::assembly::aarch64::OPCODE::NANDS_PPzPP) + .value("NAND_PPzPP", LIEF::assembly::aarch64::OPCODE::NAND_PPzPP) + .value("NBSL_ZZZZ", LIEF::assembly::aarch64::OPCODE::NBSL_ZZZZ) + .value("NEG_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_B) + .value("NEG_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_D) + .value("NEG_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_H) + .value("NEG_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_S) + .value("NEG_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::NEG_ZPzZ_B) + .value("NEG_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::NEG_ZPzZ_D) + .value("NEG_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::NEG_ZPzZ_H) + .value("NEG_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::NEG_ZPzZ_S) + .value("NEGv16i8", LIEF::assembly::aarch64::OPCODE::NEGv16i8) + .value("NEGv1i64", LIEF::assembly::aarch64::OPCODE::NEGv1i64) + .value("NEGv2i32", LIEF::assembly::aarch64::OPCODE::NEGv2i32) + .value("NEGv2i64", LIEF::assembly::aarch64::OPCODE::NEGv2i64) + .value("NEGv4i16", LIEF::assembly::aarch64::OPCODE::NEGv4i16) + .value("NEGv4i32", LIEF::assembly::aarch64::OPCODE::NEGv4i32) + .value("NEGv8i16", LIEF::assembly::aarch64::OPCODE::NEGv8i16) + .value("NEGv8i8", LIEF::assembly::aarch64::OPCODE::NEGv8i8) + .value("NMATCH_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::NMATCH_PPzZZ_B) + .value("NMATCH_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::NMATCH_PPzZZ_H) + .value("NOP", LIEF::assembly::aarch64::OPCODE::NOP) + .value("NORS_PPzPP", LIEF::assembly::aarch64::OPCODE::NORS_PPzPP) + .value("NOR_PPzPP", LIEF::assembly::aarch64::OPCODE::NOR_PPzPP) + .value("NOT_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_B) + .value("NOT_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_D) + .value("NOT_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_H) + .value("NOT_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_S) + .value("NOT_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::NOT_ZPzZ_B) + .value("NOT_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::NOT_ZPzZ_D) + .value("NOT_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::NOT_ZPzZ_H) + .value("NOT_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::NOT_ZPzZ_S) + .value("NOTv16i8", LIEF::assembly::aarch64::OPCODE::NOTv16i8) + .value("NOTv8i8", LIEF::assembly::aarch64::OPCODE::NOTv8i8) + .value("ORNS_PPzPP", LIEF::assembly::aarch64::OPCODE::ORNS_PPzPP) + .value("ORNWrs", LIEF::assembly::aarch64::OPCODE::ORNWrs) + .value("ORNXrs", LIEF::assembly::aarch64::OPCODE::ORNXrs) + .value("ORN_PPzPP", LIEF::assembly::aarch64::OPCODE::ORN_PPzPP) + .value("ORNv16i8", LIEF::assembly::aarch64::OPCODE::ORNv16i8) + .value("ORNv8i8", LIEF::assembly::aarch64::OPCODE::ORNv8i8) + .value("ORQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::ORQV_VPZ_B) + .value("ORQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::ORQV_VPZ_D) + .value("ORQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::ORQV_VPZ_H) + .value("ORQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::ORQV_VPZ_S) + .value("ORRS_PPzPP", LIEF::assembly::aarch64::OPCODE::ORRS_PPzPP) + .value("ORRWri", LIEF::assembly::aarch64::OPCODE::ORRWri) + .value("ORRWrs", LIEF::assembly::aarch64::OPCODE::ORRWrs) + .value("ORRXri", LIEF::assembly::aarch64::OPCODE::ORRXri) + .value("ORRXrs", LIEF::assembly::aarch64::OPCODE::ORRXrs) + .value("ORR_PPzPP", LIEF::assembly::aarch64::OPCODE::ORR_PPzPP) + .value("ORR_ZI", LIEF::assembly::aarch64::OPCODE::ORR_ZI) + .value("ORR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::ORR_ZPmZ_B) + .value("ORR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::ORR_ZPmZ_D) + .value("ORR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::ORR_ZPmZ_H) + .value("ORR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::ORR_ZPmZ_S) + .value("ORR_ZZZ", LIEF::assembly::aarch64::OPCODE::ORR_ZZZ) + .value("ORRv16i8", LIEF::assembly::aarch64::OPCODE::ORRv16i8) + .value("ORRv2i32", LIEF::assembly::aarch64::OPCODE::ORRv2i32) + .value("ORRv4i16", LIEF::assembly::aarch64::OPCODE::ORRv4i16) + .value("ORRv4i32", LIEF::assembly::aarch64::OPCODE::ORRv4i32) + .value("ORRv8i16", LIEF::assembly::aarch64::OPCODE::ORRv8i16) + .value("ORRv8i8", LIEF::assembly::aarch64::OPCODE::ORRv8i8) + .value("ORV_VPZ_B", LIEF::assembly::aarch64::OPCODE::ORV_VPZ_B) + .value("ORV_VPZ_D", LIEF::assembly::aarch64::OPCODE::ORV_VPZ_D) + .value("ORV_VPZ_H", LIEF::assembly::aarch64::OPCODE::ORV_VPZ_H) + .value("ORV_VPZ_S", LIEF::assembly::aarch64::OPCODE::ORV_VPZ_S) + .value("PACDA", LIEF::assembly::aarch64::OPCODE::PACDA) + .value("PACDB", LIEF::assembly::aarch64::OPCODE::PACDB) + .value("PACDZA", LIEF::assembly::aarch64::OPCODE::PACDZA) + .value("PACDZB", LIEF::assembly::aarch64::OPCODE::PACDZB) + .value("PACGA", LIEF::assembly::aarch64::OPCODE::PACGA) + .value("PACIA", LIEF::assembly::aarch64::OPCODE::PACIA) + .value("PACIA1716", LIEF::assembly::aarch64::OPCODE::PACIA1716) + .value("PACIA171615", LIEF::assembly::aarch64::OPCODE::PACIA171615) + .value("PACIASP", LIEF::assembly::aarch64::OPCODE::PACIASP) + .value("PACIASPPC", LIEF::assembly::aarch64::OPCODE::PACIASPPC) + .value("PACIAZ", LIEF::assembly::aarch64::OPCODE::PACIAZ) + .value("PACIB", LIEF::assembly::aarch64::OPCODE::PACIB) + .value("PACIB1716", LIEF::assembly::aarch64::OPCODE::PACIB1716) + .value("PACIB171615", LIEF::assembly::aarch64::OPCODE::PACIB171615) + .value("PACIBSP", LIEF::assembly::aarch64::OPCODE::PACIBSP) + .value("PACIBSPPC", LIEF::assembly::aarch64::OPCODE::PACIBSPPC) + .value("PACIBZ", LIEF::assembly::aarch64::OPCODE::PACIBZ) + .value("PACIZA", LIEF::assembly::aarch64::OPCODE::PACIZA) + .value("PACIZB", LIEF::assembly::aarch64::OPCODE::PACIZB) + .value("PACM", LIEF::assembly::aarch64::OPCODE::PACM) + .value("PACNBIASPPC", LIEF::assembly::aarch64::OPCODE::PACNBIASPPC) + .value("PACNBIBSPPC", LIEF::assembly::aarch64::OPCODE::PACNBIBSPPC) + .value("PEXT_2PCI_B", LIEF::assembly::aarch64::OPCODE::PEXT_2PCI_B) + .value("PEXT_2PCI_D", LIEF::assembly::aarch64::OPCODE::PEXT_2PCI_D) + .value("PEXT_2PCI_H", LIEF::assembly::aarch64::OPCODE::PEXT_2PCI_H) + .value("PEXT_2PCI_S", LIEF::assembly::aarch64::OPCODE::PEXT_2PCI_S) + .value("PEXT_PCI_B", LIEF::assembly::aarch64::OPCODE::PEXT_PCI_B) + .value("PEXT_PCI_D", LIEF::assembly::aarch64::OPCODE::PEXT_PCI_D) + .value("PEXT_PCI_H", LIEF::assembly::aarch64::OPCODE::PEXT_PCI_H) + .value("PEXT_PCI_S", LIEF::assembly::aarch64::OPCODE::PEXT_PCI_S) + .value("PFALSE", LIEF::assembly::aarch64::OPCODE::PFALSE) + .value("PFIRST_B", LIEF::assembly::aarch64::OPCODE::PFIRST_B) + .value("PMLAL_2ZZZ_Q", LIEF::assembly::aarch64::OPCODE::PMLAL_2ZZZ_Q) + .value("PMOV_PZI_B", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_B) + .value("PMOV_PZI_D", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_D) + .value("PMOV_PZI_H", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_H) + .value("PMOV_PZI_S", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_S) + .value("PMOV_ZIP_B", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_B) + .value("PMOV_ZIP_D", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_D) + .value("PMOV_ZIP_H", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_H) + .value("PMOV_ZIP_S", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_S) + .value("PMULLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::PMULLB_ZZZ_D) + .value("PMULLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::PMULLB_ZZZ_H) + .value("PMULLB_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::PMULLB_ZZZ_Q) + .value("PMULLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::PMULLT_ZZZ_D) + .value("PMULLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::PMULLT_ZZZ_H) + .value("PMULLT_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::PMULLT_ZZZ_Q) + .value("PMULL_2ZZZ_Q", LIEF::assembly::aarch64::OPCODE::PMULL_2ZZZ_Q) + .value("PMULLv16i8", LIEF::assembly::aarch64::OPCODE::PMULLv16i8) + .value("PMULLv1i64", LIEF::assembly::aarch64::OPCODE::PMULLv1i64) + .value("PMULLv2i64", LIEF::assembly::aarch64::OPCODE::PMULLv2i64) + .value("PMULLv8i8", LIEF::assembly::aarch64::OPCODE::PMULLv8i8) + .value("PMUL_ZZZ_B", LIEF::assembly::aarch64::OPCODE::PMUL_ZZZ_B) + .value("PMULv16i8", LIEF::assembly::aarch64::OPCODE::PMULv16i8) + .value("PMULv8i8", LIEF::assembly::aarch64::OPCODE::PMULv8i8) + .value("PNEXT_B", LIEF::assembly::aarch64::OPCODE::PNEXT_B) + .value("PNEXT_D", LIEF::assembly::aarch64::OPCODE::PNEXT_D) + .value("PNEXT_H", LIEF::assembly::aarch64::OPCODE::PNEXT_H) + .value("PNEXT_S", LIEF::assembly::aarch64::OPCODE::PNEXT_S) + .value("PRFB_D_PZI", LIEF::assembly::aarch64::OPCODE::PRFB_D_PZI) + .value("PRFB_D_SCALED", LIEF::assembly::aarch64::OPCODE::PRFB_D_SCALED) + .value("PRFB_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFB_D_SXTW_SCALED) + .value("PRFB_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFB_D_UXTW_SCALED) + .value("PRFB_PRI", LIEF::assembly::aarch64::OPCODE::PRFB_PRI) + .value("PRFB_PRR", LIEF::assembly::aarch64::OPCODE::PRFB_PRR) + .value("PRFB_S_PZI", LIEF::assembly::aarch64::OPCODE::PRFB_S_PZI) + .value("PRFB_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFB_S_SXTW_SCALED) + .value("PRFB_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFB_S_UXTW_SCALED) + .value("PRFD_D_PZI", LIEF::assembly::aarch64::OPCODE::PRFD_D_PZI) + .value("PRFD_D_SCALED", LIEF::assembly::aarch64::OPCODE::PRFD_D_SCALED) + .value("PRFD_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFD_D_SXTW_SCALED) + .value("PRFD_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFD_D_UXTW_SCALED) + .value("PRFD_PRI", LIEF::assembly::aarch64::OPCODE::PRFD_PRI) + .value("PRFD_PRR", LIEF::assembly::aarch64::OPCODE::PRFD_PRR) + .value("PRFD_S_PZI", LIEF::assembly::aarch64::OPCODE::PRFD_S_PZI) + .value("PRFD_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFD_S_SXTW_SCALED) + .value("PRFD_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFD_S_UXTW_SCALED) + .value("PRFH_D_PZI", LIEF::assembly::aarch64::OPCODE::PRFH_D_PZI) + .value("PRFH_D_SCALED", LIEF::assembly::aarch64::OPCODE::PRFH_D_SCALED) + .value("PRFH_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFH_D_SXTW_SCALED) + .value("PRFH_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFH_D_UXTW_SCALED) + .value("PRFH_PRI", LIEF::assembly::aarch64::OPCODE::PRFH_PRI) + .value("PRFH_PRR", LIEF::assembly::aarch64::OPCODE::PRFH_PRR) + .value("PRFH_S_PZI", LIEF::assembly::aarch64::OPCODE::PRFH_S_PZI) + .value("PRFH_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFH_S_SXTW_SCALED) + .value("PRFH_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFH_S_UXTW_SCALED) + .value("PRFMl", LIEF::assembly::aarch64::OPCODE::PRFMl) + .value("PRFMroW", LIEF::assembly::aarch64::OPCODE::PRFMroW) + .value("PRFMroX", LIEF::assembly::aarch64::OPCODE::PRFMroX) + .value("PRFMui", LIEF::assembly::aarch64::OPCODE::PRFMui) + .value("PRFUMi", LIEF::assembly::aarch64::OPCODE::PRFUMi) + .value("PRFW_D_PZI", LIEF::assembly::aarch64::OPCODE::PRFW_D_PZI) + .value("PRFW_D_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_D_SCALED) + .value("PRFW_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_D_SXTW_SCALED) + .value("PRFW_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_D_UXTW_SCALED) + .value("PRFW_PRI", LIEF::assembly::aarch64::OPCODE::PRFW_PRI) + .value("PRFW_PRR", LIEF::assembly::aarch64::OPCODE::PRFW_PRR) + .value("PRFW_S_PZI", LIEF::assembly::aarch64::OPCODE::PRFW_S_PZI) + .value("PRFW_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_SXTW_SCALED); + opcodes.value("PRFW_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_UXTW_SCALED) + .value("PSEL_PPPRI_B", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_B) + .value("PSEL_PPPRI_D", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_D) + .value("PSEL_PPPRI_H", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_H) + .value("PSEL_PPPRI_S", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_S) + .value("PTEST_PP", LIEF::assembly::aarch64::OPCODE::PTEST_PP) + .value("PTRUES_B", LIEF::assembly::aarch64::OPCODE::PTRUES_B) + .value("PTRUES_D", LIEF::assembly::aarch64::OPCODE::PTRUES_D) + .value("PTRUES_H", LIEF::assembly::aarch64::OPCODE::PTRUES_H) + .value("PTRUES_S", LIEF::assembly::aarch64::OPCODE::PTRUES_S) + .value("PTRUE_B", LIEF::assembly::aarch64::OPCODE::PTRUE_B) + .value("PTRUE_C_B", LIEF::assembly::aarch64::OPCODE::PTRUE_C_B) + .value("PTRUE_C_D", LIEF::assembly::aarch64::OPCODE::PTRUE_C_D) + .value("PTRUE_C_H", LIEF::assembly::aarch64::OPCODE::PTRUE_C_H) + .value("PTRUE_C_S", LIEF::assembly::aarch64::OPCODE::PTRUE_C_S) + .value("PTRUE_D", LIEF::assembly::aarch64::OPCODE::PTRUE_D) + .value("PTRUE_H", LIEF::assembly::aarch64::OPCODE::PTRUE_H) + .value("PTRUE_S", LIEF::assembly::aarch64::OPCODE::PTRUE_S) + .value("PUNPKHI_PP", LIEF::assembly::aarch64::OPCODE::PUNPKHI_PP) + .value("PUNPKLO_PP", LIEF::assembly::aarch64::OPCODE::PUNPKLO_PP) + .value("RADDHNB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::RADDHNB_ZZZ_B) + .value("RADDHNB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::RADDHNB_ZZZ_H) + .value("RADDHNB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::RADDHNB_ZZZ_S) + .value("RADDHNT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::RADDHNT_ZZZ_B) + .value("RADDHNT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::RADDHNT_ZZZ_H) + .value("RADDHNT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::RADDHNT_ZZZ_S) + .value("RADDHNv2i64_v2i32", LIEF::assembly::aarch64::OPCODE::RADDHNv2i64_v2i32) + .value("RADDHNv2i64_v4i32", LIEF::assembly::aarch64::OPCODE::RADDHNv2i64_v4i32) + .value("RADDHNv4i32_v4i16", LIEF::assembly::aarch64::OPCODE::RADDHNv4i32_v4i16) + .value("RADDHNv4i32_v8i16", LIEF::assembly::aarch64::OPCODE::RADDHNv4i32_v8i16) + .value("RADDHNv8i16_v16i8", LIEF::assembly::aarch64::OPCODE::RADDHNv8i16_v16i8) + .value("RADDHNv8i16_v8i8", LIEF::assembly::aarch64::OPCODE::RADDHNv8i16_v8i8) + .value("RAX1", LIEF::assembly::aarch64::OPCODE::RAX1) + .value("RAX1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::RAX1_ZZZ_D) + .value("RBITWr", LIEF::assembly::aarch64::OPCODE::RBITWr) + .value("RBITXr", LIEF::assembly::aarch64::OPCODE::RBITXr) + .value("RBIT_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::RBIT_ZPmZ_B) + .value("RBIT_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::RBIT_ZPmZ_D) + .value("RBIT_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::RBIT_ZPmZ_H) + .value("RBIT_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::RBIT_ZPmZ_S) + .value("RBIT_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::RBIT_ZPzZ_B) + .value("RBIT_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::RBIT_ZPzZ_D) + .value("RBIT_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::RBIT_ZPzZ_H) + .value("RBIT_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::RBIT_ZPzZ_S) + .value("RBITv16i8", LIEF::assembly::aarch64::OPCODE::RBITv16i8) + .value("RBITv8i8", LIEF::assembly::aarch64::OPCODE::RBITv8i8) + .value("RCWCAS", LIEF::assembly::aarch64::OPCODE::RCWCAS) + .value("RCWCASA", LIEF::assembly::aarch64::OPCODE::RCWCASA) + .value("RCWCASAL", LIEF::assembly::aarch64::OPCODE::RCWCASAL) + .value("RCWCASL", LIEF::assembly::aarch64::OPCODE::RCWCASL) + .value("RCWCASP", LIEF::assembly::aarch64::OPCODE::RCWCASP) + .value("RCWCASPA", LIEF::assembly::aarch64::OPCODE::RCWCASPA) + .value("RCWCASPAL", LIEF::assembly::aarch64::OPCODE::RCWCASPAL) + .value("RCWCASPL", LIEF::assembly::aarch64::OPCODE::RCWCASPL) + .value("RCWCLR", LIEF::assembly::aarch64::OPCODE::RCWCLR) + .value("RCWCLRA", LIEF::assembly::aarch64::OPCODE::RCWCLRA) + .value("RCWCLRAL", LIEF::assembly::aarch64::OPCODE::RCWCLRAL) + .value("RCWCLRL", LIEF::assembly::aarch64::OPCODE::RCWCLRL) + .value("RCWCLRP", LIEF::assembly::aarch64::OPCODE::RCWCLRP) + .value("RCWCLRPA", LIEF::assembly::aarch64::OPCODE::RCWCLRPA) + .value("RCWCLRPAL", LIEF::assembly::aarch64::OPCODE::RCWCLRPAL) + .value("RCWCLRPL", LIEF::assembly::aarch64::OPCODE::RCWCLRPL) + .value("RCWCLRS", LIEF::assembly::aarch64::OPCODE::RCWCLRS) + .value("RCWCLRSA", LIEF::assembly::aarch64::OPCODE::RCWCLRSA) + .value("RCWCLRSAL", LIEF::assembly::aarch64::OPCODE::RCWCLRSAL) + .value("RCWCLRSL", LIEF::assembly::aarch64::OPCODE::RCWCLRSL) + .value("RCWCLRSP", LIEF::assembly::aarch64::OPCODE::RCWCLRSP) + .value("RCWCLRSPA", LIEF::assembly::aarch64::OPCODE::RCWCLRSPA) + .value("RCWCLRSPAL", LIEF::assembly::aarch64::OPCODE::RCWCLRSPAL) + .value("RCWCLRSPL", LIEF::assembly::aarch64::OPCODE::RCWCLRSPL) + .value("RCWSCAS", LIEF::assembly::aarch64::OPCODE::RCWSCAS) + .value("RCWSCASA", LIEF::assembly::aarch64::OPCODE::RCWSCASA) + .value("RCWSCASAL", LIEF::assembly::aarch64::OPCODE::RCWSCASAL) + .value("RCWSCASL", LIEF::assembly::aarch64::OPCODE::RCWSCASL) + .value("RCWSCASP", LIEF::assembly::aarch64::OPCODE::RCWSCASP) + .value("RCWSCASPA", LIEF::assembly::aarch64::OPCODE::RCWSCASPA) + .value("RCWSCASPAL", LIEF::assembly::aarch64::OPCODE::RCWSCASPAL) + .value("RCWSCASPL", LIEF::assembly::aarch64::OPCODE::RCWSCASPL) + .value("RCWSET", LIEF::assembly::aarch64::OPCODE::RCWSET) + .value("RCWSETA", LIEF::assembly::aarch64::OPCODE::RCWSETA) + .value("RCWSETAL", LIEF::assembly::aarch64::OPCODE::RCWSETAL) + .value("RCWSETL", LIEF::assembly::aarch64::OPCODE::RCWSETL) + .value("RCWSETP", LIEF::assembly::aarch64::OPCODE::RCWSETP) + .value("RCWSETPA", LIEF::assembly::aarch64::OPCODE::RCWSETPA) + .value("RCWSETPAL", LIEF::assembly::aarch64::OPCODE::RCWSETPAL) + .value("RCWSETPL", LIEF::assembly::aarch64::OPCODE::RCWSETPL) + .value("RCWSETS", LIEF::assembly::aarch64::OPCODE::RCWSETS) + .value("RCWSETSA", LIEF::assembly::aarch64::OPCODE::RCWSETSA) + .value("RCWSETSAL", LIEF::assembly::aarch64::OPCODE::RCWSETSAL) + .value("RCWSETSL", LIEF::assembly::aarch64::OPCODE::RCWSETSL) + .value("RCWSETSP", LIEF::assembly::aarch64::OPCODE::RCWSETSP) + .value("RCWSETSPA", LIEF::assembly::aarch64::OPCODE::RCWSETSPA) + .value("RCWSETSPAL", LIEF::assembly::aarch64::OPCODE::RCWSETSPAL) + .value("RCWSETSPL", LIEF::assembly::aarch64::OPCODE::RCWSETSPL) + .value("RCWSWP", LIEF::assembly::aarch64::OPCODE::RCWSWP) + .value("RCWSWPA", LIEF::assembly::aarch64::OPCODE::RCWSWPA) + .value("RCWSWPAL", LIEF::assembly::aarch64::OPCODE::RCWSWPAL) + .value("RCWSWPL", LIEF::assembly::aarch64::OPCODE::RCWSWPL) + .value("RCWSWPP", LIEF::assembly::aarch64::OPCODE::RCWSWPP) + .value("RCWSWPPA", LIEF::assembly::aarch64::OPCODE::RCWSWPPA) + .value("RCWSWPPAL", LIEF::assembly::aarch64::OPCODE::RCWSWPPAL) + .value("RCWSWPPL", LIEF::assembly::aarch64::OPCODE::RCWSWPPL) + .value("RCWSWPS", LIEF::assembly::aarch64::OPCODE::RCWSWPS) + .value("RCWSWPSA", LIEF::assembly::aarch64::OPCODE::RCWSWPSA) + .value("RCWSWPSAL", LIEF::assembly::aarch64::OPCODE::RCWSWPSAL) + .value("RCWSWPSL", LIEF::assembly::aarch64::OPCODE::RCWSWPSL) + .value("RCWSWPSP", LIEF::assembly::aarch64::OPCODE::RCWSWPSP) + .value("RCWSWPSPA", LIEF::assembly::aarch64::OPCODE::RCWSWPSPA) + .value("RCWSWPSPAL", LIEF::assembly::aarch64::OPCODE::RCWSWPSPAL) + .value("RCWSWPSPL", LIEF::assembly::aarch64::OPCODE::RCWSWPSPL) + .value("RDFFRS_PPz", LIEF::assembly::aarch64::OPCODE::RDFFRS_PPz) + .value("RDFFR_P", LIEF::assembly::aarch64::OPCODE::RDFFR_P) + .value("RDFFR_PPz", LIEF::assembly::aarch64::OPCODE::RDFFR_PPz) + .value("RDSVLI_XI", LIEF::assembly::aarch64::OPCODE::RDSVLI_XI) + .value("RDVLI_XI", LIEF::assembly::aarch64::OPCODE::RDVLI_XI) + .value("RET", LIEF::assembly::aarch64::OPCODE::RET) + .value("RETAA", LIEF::assembly::aarch64::OPCODE::RETAA) + .value("RETAASPPCi", LIEF::assembly::aarch64::OPCODE::RETAASPPCi) + .value("RETAASPPCr", LIEF::assembly::aarch64::OPCODE::RETAASPPCr) + .value("RETAB", LIEF::assembly::aarch64::OPCODE::RETAB) + .value("RETABSPPCi", LIEF::assembly::aarch64::OPCODE::RETABSPPCi) + .value("RETABSPPCr", LIEF::assembly::aarch64::OPCODE::RETABSPPCr) + .value("REV16Wr", LIEF::assembly::aarch64::OPCODE::REV16Wr) + .value("REV16Xr", LIEF::assembly::aarch64::OPCODE::REV16Xr) + .value("REV16v16i8", LIEF::assembly::aarch64::OPCODE::REV16v16i8) + .value("REV16v8i8", LIEF::assembly::aarch64::OPCODE::REV16v8i8) + .value("REV32Xr", LIEF::assembly::aarch64::OPCODE::REV32Xr) + .value("REV32v16i8", LIEF::assembly::aarch64::OPCODE::REV32v16i8) + .value("REV32v4i16", LIEF::assembly::aarch64::OPCODE::REV32v4i16) + .value("REV32v8i16", LIEF::assembly::aarch64::OPCODE::REV32v8i16) + .value("REV32v8i8", LIEF::assembly::aarch64::OPCODE::REV32v8i8) + .value("REV64v16i8", LIEF::assembly::aarch64::OPCODE::REV64v16i8) + .value("REV64v2i32", LIEF::assembly::aarch64::OPCODE::REV64v2i32) + .value("REV64v4i16", LIEF::assembly::aarch64::OPCODE::REV64v4i16) + .value("REV64v4i32", LIEF::assembly::aarch64::OPCODE::REV64v4i32) + .value("REV64v8i16", LIEF::assembly::aarch64::OPCODE::REV64v8i16) + .value("REV64v8i8", LIEF::assembly::aarch64::OPCODE::REV64v8i8) + .value("REVB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::REVB_ZPmZ_D) + .value("REVB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::REVB_ZPmZ_H) + .value("REVB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::REVB_ZPmZ_S) + .value("REVB_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::REVB_ZPzZ_D) + .value("REVB_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::REVB_ZPzZ_H) + .value("REVB_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::REVB_ZPzZ_S) + .value("REVD_ZPmZ", LIEF::assembly::aarch64::OPCODE::REVD_ZPmZ) + .value("REVD_ZPzZ", LIEF::assembly::aarch64::OPCODE::REVD_ZPzZ) + .value("REVH_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::REVH_ZPmZ_D) + .value("REVH_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::REVH_ZPmZ_S) + .value("REVH_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::REVH_ZPzZ_D) + .value("REVH_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::REVH_ZPzZ_S) + .value("REVW_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::REVW_ZPmZ_D) + .value("REVW_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::REVW_ZPzZ_D) + .value("REVWr", LIEF::assembly::aarch64::OPCODE::REVWr) + .value("REVXr", LIEF::assembly::aarch64::OPCODE::REVXr) + .value("REV_PP_B", LIEF::assembly::aarch64::OPCODE::REV_PP_B) + .value("REV_PP_D", LIEF::assembly::aarch64::OPCODE::REV_PP_D) + .value("REV_PP_H", LIEF::assembly::aarch64::OPCODE::REV_PP_H) + .value("REV_PP_S", LIEF::assembly::aarch64::OPCODE::REV_PP_S) + .value("REV_ZZ_B", LIEF::assembly::aarch64::OPCODE::REV_ZZ_B) + .value("REV_ZZ_D", LIEF::assembly::aarch64::OPCODE::REV_ZZ_D) + .value("REV_ZZ_H", LIEF::assembly::aarch64::OPCODE::REV_ZZ_H) + .value("REV_ZZ_S", LIEF::assembly::aarch64::OPCODE::REV_ZZ_S) + .value("RMIF", LIEF::assembly::aarch64::OPCODE::RMIF) + .value("RORVWr", LIEF::assembly::aarch64::OPCODE::RORVWr) + .value("RORVXr", LIEF::assembly::aarch64::OPCODE::RORVXr) + .value("RPRFM", LIEF::assembly::aarch64::OPCODE::RPRFM) + .value("RSHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::RSHRNB_ZZI_B) + .value("RSHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::RSHRNB_ZZI_H) + .value("RSHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::RSHRNB_ZZI_S) + .value("RSHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::RSHRNT_ZZI_B) + .value("RSHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::RSHRNT_ZZI_H) + .value("RSHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::RSHRNT_ZZI_S) + .value("RSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv16i8_shift) + .value("RSHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv2i32_shift) + .value("RSHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv4i16_shift) + .value("RSHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv4i32_shift) + .value("RSHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv8i16_shift) + .value("RSHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::RSHRNv8i8_shift) + .value("RSUBHNB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::RSUBHNB_ZZZ_B) + .value("RSUBHNB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::RSUBHNB_ZZZ_H) + .value("RSUBHNB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::RSUBHNB_ZZZ_S) + .value("RSUBHNT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::RSUBHNT_ZZZ_B) + .value("RSUBHNT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::RSUBHNT_ZZZ_H) + .value("RSUBHNT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::RSUBHNT_ZZZ_S) + .value("RSUBHNv2i64_v2i32", LIEF::assembly::aarch64::OPCODE::RSUBHNv2i64_v2i32) + .value("RSUBHNv2i64_v4i32", LIEF::assembly::aarch64::OPCODE::RSUBHNv2i64_v4i32) + .value("RSUBHNv4i32_v4i16", LIEF::assembly::aarch64::OPCODE::RSUBHNv4i32_v4i16) + .value("RSUBHNv4i32_v8i16", LIEF::assembly::aarch64::OPCODE::RSUBHNv4i32_v8i16) + .value("RSUBHNv8i16_v16i8", LIEF::assembly::aarch64::OPCODE::RSUBHNv8i16_v16i8) + .value("RSUBHNv8i16_v8i8", LIEF::assembly::aarch64::OPCODE::RSUBHNv8i16_v8i8) + .value("SABALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SABALB_ZZZ_D) + .value("SABALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SABALB_ZZZ_H) + .value("SABALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SABALB_ZZZ_S) + .value("SABALT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SABALT_ZZZ_D) + .value("SABALT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SABALT_ZZZ_H) + .value("SABALT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SABALT_ZZZ_S) + .value("SABAL_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::SABAL_ZZZ_BtoH) + .value("SABAL_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SABAL_ZZZ_HtoS) + .value("SABAL_ZZZ_StoD", LIEF::assembly::aarch64::OPCODE::SABAL_ZZZ_StoD) + .value("SABALv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SABALv16i8_v8i16) + .value("SABALv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SABALv2i32_v2i64) + .value("SABALv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SABALv4i16_v4i32) + .value("SABALv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SABALv4i32_v2i64) + .value("SABALv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SABALv8i16_v4i32) + .value("SABALv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SABALv8i8_v8i16) + .value("SABA_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SABA_ZZZ_B) + .value("SABA_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SABA_ZZZ_D) + .value("SABA_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SABA_ZZZ_H) + .value("SABA_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SABA_ZZZ_S) + .value("SABAv16i8", LIEF::assembly::aarch64::OPCODE::SABAv16i8) + .value("SABAv2i32", LIEF::assembly::aarch64::OPCODE::SABAv2i32) + .value("SABAv4i16", LIEF::assembly::aarch64::OPCODE::SABAv4i16) + .value("SABAv4i32", LIEF::assembly::aarch64::OPCODE::SABAv4i32) + .value("SABAv8i16", LIEF::assembly::aarch64::OPCODE::SABAv8i16) + .value("SABAv8i8", LIEF::assembly::aarch64::OPCODE::SABAv8i8) + .value("SABDLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SABDLB_ZZZ_D) + .value("SABDLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SABDLB_ZZZ_H) + .value("SABDLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SABDLB_ZZZ_S) + .value("SABDLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SABDLT_ZZZ_D) + .value("SABDLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SABDLT_ZZZ_H) + .value("SABDLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SABDLT_ZZZ_S) + .value("SABDLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SABDLv16i8_v8i16) + .value("SABDLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SABDLv2i32_v2i64) + .value("SABDLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SABDLv4i16_v4i32) + .value("SABDLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SABDLv4i32_v2i64) + .value("SABDLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SABDLv8i16_v4i32) + .value("SABDLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SABDLv8i8_v8i16) + .value("SABD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SABD_ZPmZ_B) + .value("SABD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SABD_ZPmZ_D) + .value("SABD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SABD_ZPmZ_H) + .value("SABD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SABD_ZPmZ_S) + .value("SABDv16i8", LIEF::assembly::aarch64::OPCODE::SABDv16i8) + .value("SABDv2i32", LIEF::assembly::aarch64::OPCODE::SABDv2i32) + .value("SABDv4i16", LIEF::assembly::aarch64::OPCODE::SABDv4i16) + .value("SABDv4i32", LIEF::assembly::aarch64::OPCODE::SABDv4i32) + .value("SABDv8i16", LIEF::assembly::aarch64::OPCODE::SABDv8i16) + .value("SABDv8i8", LIEF::assembly::aarch64::OPCODE::SABDv8i8) + .value("SADALP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_D) + .value("SADALP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_H) + .value("SADALP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_S) + .value("SADALPv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADALPv16i8_v8i16) + .value("SADALPv2i32_v1i64", LIEF::assembly::aarch64::OPCODE::SADALPv2i32_v1i64) + .value("SADALPv4i16_v2i32", LIEF::assembly::aarch64::OPCODE::SADALPv4i16_v2i32) + .value("SADALPv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADALPv4i32_v2i64) + .value("SADALPv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADALPv8i16_v4i32) + .value("SADALPv8i8_v4i16", LIEF::assembly::aarch64::OPCODE::SADALPv8i8_v4i16) + .value("SADDLBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SADDLBT_ZZZ_D) + .value("SADDLBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SADDLBT_ZZZ_H) + .value("SADDLBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SADDLBT_ZZZ_S) + .value("SADDLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SADDLB_ZZZ_D) + .value("SADDLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SADDLB_ZZZ_H) + .value("SADDLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SADDLB_ZZZ_S) + .value("SADDLPv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADDLPv16i8_v8i16) + .value("SADDLPv2i32_v1i64", LIEF::assembly::aarch64::OPCODE::SADDLPv2i32_v1i64) + .value("SADDLPv4i16_v2i32", LIEF::assembly::aarch64::OPCODE::SADDLPv4i16_v2i32) + .value("SADDLPv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADDLPv4i32_v2i64) + .value("SADDLPv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADDLPv8i16_v4i32) + .value("SADDLPv8i8_v4i16", LIEF::assembly::aarch64::OPCODE::SADDLPv8i8_v4i16) + .value("SADDLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SADDLT_ZZZ_D) + .value("SADDLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SADDLT_ZZZ_H) + .value("SADDLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SADDLT_ZZZ_S) + .value("SADDLVv16i8v", LIEF::assembly::aarch64::OPCODE::SADDLVv16i8v) + .value("SADDLVv4i16v", LIEF::assembly::aarch64::OPCODE::SADDLVv4i16v) + .value("SADDLVv4i32v", LIEF::assembly::aarch64::OPCODE::SADDLVv4i32v) + .value("SADDLVv8i16v", LIEF::assembly::aarch64::OPCODE::SADDLVv8i16v) + .value("SADDLVv8i8v", LIEF::assembly::aarch64::OPCODE::SADDLVv8i8v) + .value("SADDLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADDLv16i8_v8i16) + .value("SADDLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADDLv2i32_v2i64) + .value("SADDLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADDLv4i16_v4i32) + .value("SADDLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADDLv4i32_v2i64) + .value("SADDLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADDLv8i16_v4i32) + .value("SADDLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADDLv8i8_v8i16) + .value("SADDV_VPZ_B", LIEF::assembly::aarch64::OPCODE::SADDV_VPZ_B) + .value("SADDV_VPZ_H", LIEF::assembly::aarch64::OPCODE::SADDV_VPZ_H) + .value("SADDV_VPZ_S", LIEF::assembly::aarch64::OPCODE::SADDV_VPZ_S) + .value("SADDWB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SADDWB_ZZZ_D) + .value("SADDWB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SADDWB_ZZZ_H) + .value("SADDWB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SADDWB_ZZZ_S) + .value("SADDWT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SADDWT_ZZZ_D) + .value("SADDWT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SADDWT_ZZZ_H) + .value("SADDWT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SADDWT_ZZZ_S) + .value("SADDWv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADDWv16i8_v8i16) + .value("SADDWv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADDWv2i32_v2i64) + .value("SADDWv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADDWv4i16_v4i32) + .value("SADDWv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SADDWv4i32_v2i64) + .value("SADDWv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SADDWv8i16_v4i32) + .value("SADDWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADDWv8i8_v8i16) + .value("SB", LIEF::assembly::aarch64::OPCODE::SB) + .value("SBCLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SBCLB_ZZZ_D) + .value("SBCLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SBCLB_ZZZ_S) + .value("SBCLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SBCLT_ZZZ_D) + .value("SBCLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SBCLT_ZZZ_S) + .value("SBCSWr", LIEF::assembly::aarch64::OPCODE::SBCSWr) + .value("SBCSXr", LIEF::assembly::aarch64::OPCODE::SBCSXr) + .value("SBCWr", LIEF::assembly::aarch64::OPCODE::SBCWr) + .value("SBCXr", LIEF::assembly::aarch64::OPCODE::SBCXr) + .value("SBFMWri", LIEF::assembly::aarch64::OPCODE::SBFMWri) + .value("SBFMXri", LIEF::assembly::aarch64::OPCODE::SBFMXri) + .value("SCLAMP_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_B) + .value("SCLAMP_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_D) + .value("SCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_H); + opcodes.value("SCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_S) + .value("SCLAMP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_B) + .value("SCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_D) + .value("SCLAMP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_H) + .value("SCLAMP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_S) + .value("SCLAMP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SCLAMP_ZZZ_B) + .value("SCLAMP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SCLAMP_ZZZ_D) + .value("SCLAMP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_ZZZ_H) + .value("SCLAMP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SCLAMP_ZZZ_S) + .value("SCVTFDSr", LIEF::assembly::aarch64::OPCODE::SCVTFDSr) + .value("SCVTFHDr", LIEF::assembly::aarch64::OPCODE::SCVTFHDr) + .value("SCVTFHSr", LIEF::assembly::aarch64::OPCODE::SCVTFHSr) + .value("SCVTFLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::SCVTFLT_ZZ_BtoH) + .value("SCVTFLT_ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SCVTFLT_ZZ_HtoS) + .value("SCVTFLT_ZZ_StoD", LIEF::assembly::aarch64::OPCODE::SCVTFLT_ZZ_StoD) + .value("SCVTFSDr", LIEF::assembly::aarch64::OPCODE::SCVTFSDr) + .value("SCVTFSWDri", LIEF::assembly::aarch64::OPCODE::SCVTFSWDri) + .value("SCVTFSWHri", LIEF::assembly::aarch64::OPCODE::SCVTFSWHri) + .value("SCVTFSWSri", LIEF::assembly::aarch64::OPCODE::SCVTFSWSri) + .value("SCVTFSXDri", LIEF::assembly::aarch64::OPCODE::SCVTFSXDri) + .value("SCVTFSXHri", LIEF::assembly::aarch64::OPCODE::SCVTFSXHri) + .value("SCVTFSXSri", LIEF::assembly::aarch64::OPCODE::SCVTFSXSri) + .value("SCVTFUWDri", LIEF::assembly::aarch64::OPCODE::SCVTFUWDri) + .value("SCVTFUWHri", LIEF::assembly::aarch64::OPCODE::SCVTFUWHri) + .value("SCVTFUWSri", LIEF::assembly::aarch64::OPCODE::SCVTFUWSri) + .value("SCVTFUXDri", LIEF::assembly::aarch64::OPCODE::SCVTFUXDri) + .value("SCVTFUXHri", LIEF::assembly::aarch64::OPCODE::SCVTFUXHri) + .value("SCVTFUXSri", LIEF::assembly::aarch64::OPCODE::SCVTFUXSri) + .value("SCVTF_2Z2Z_StoS", LIEF::assembly::aarch64::OPCODE::SCVTF_2Z2Z_StoS) + .value("SCVTF_4Z4Z_StoS", LIEF::assembly::aarch64::OPCODE::SCVTF_4Z4Z_StoS) + .value("SCVTF_ZPmZ_DtoD", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoD) + .value("SCVTF_ZPmZ_DtoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoH) + .value("SCVTF_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_DtoS) + .value("SCVTF_ZPmZ_HtoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_HtoH) + .value("SCVTF_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoD) + .value("SCVTF_ZPmZ_StoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoH) + .value("SCVTF_ZPmZ_StoS", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPmZ_StoS) + .value("SCVTF_ZPzZ_DtoD", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_DtoD) + .value("SCVTF_ZPzZ_DtoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_DtoH) + .value("SCVTF_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_DtoS) + .value("SCVTF_ZPzZ_HtoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_HtoH) + .value("SCVTF_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_StoD) + .value("SCVTF_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_StoH) + .value("SCVTF_ZPzZ_StoS", LIEF::assembly::aarch64::OPCODE::SCVTF_ZPzZ_StoS) + .value("SCVTF_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::SCVTF_ZZ_BtoH) + .value("SCVTF_ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SCVTF_ZZ_HtoS) + .value("SCVTF_ZZ_StoD", LIEF::assembly::aarch64::OPCODE::SCVTF_ZZ_StoD) + .value("SCVTFd", LIEF::assembly::aarch64::OPCODE::SCVTFd) + .value("SCVTFh", LIEF::assembly::aarch64::OPCODE::SCVTFh) + .value("SCVTFs", LIEF::assembly::aarch64::OPCODE::SCVTFs) + .value("SCVTFv1i16", LIEF::assembly::aarch64::OPCODE::SCVTFv1i16) + .value("SCVTFv1i32", LIEF::assembly::aarch64::OPCODE::SCVTFv1i32) + .value("SCVTFv1i64", LIEF::assembly::aarch64::OPCODE::SCVTFv1i64) + .value("SCVTFv2f32", LIEF::assembly::aarch64::OPCODE::SCVTFv2f32) + .value("SCVTFv2f64", LIEF::assembly::aarch64::OPCODE::SCVTFv2f64) + .value("SCVTFv2i32_shift", LIEF::assembly::aarch64::OPCODE::SCVTFv2i32_shift) + .value("SCVTFv2i64_shift", LIEF::assembly::aarch64::OPCODE::SCVTFv2i64_shift) + .value("SCVTFv4f16", LIEF::assembly::aarch64::OPCODE::SCVTFv4f16) + .value("SCVTFv4f32", LIEF::assembly::aarch64::OPCODE::SCVTFv4f32) + .value("SCVTFv4i16_shift", LIEF::assembly::aarch64::OPCODE::SCVTFv4i16_shift) + .value("SCVTFv4i32_shift", LIEF::assembly::aarch64::OPCODE::SCVTFv4i32_shift) + .value("SCVTFv8f16", LIEF::assembly::aarch64::OPCODE::SCVTFv8f16) + .value("SCVTFv8i16_shift", LIEF::assembly::aarch64::OPCODE::SCVTFv8i16_shift) + .value("SDIVR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SDIVR_ZPmZ_D) + .value("SDIVR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SDIVR_ZPmZ_S) + .value("SDIVWr", LIEF::assembly::aarch64::OPCODE::SDIVWr) + .value("SDIVXr", LIEF::assembly::aarch64::OPCODE::SDIVXr) + .value("SDIV_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SDIV_ZPmZ_D) + .value("SDIV_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SDIV_ZPmZ_S) + .value("SDOT_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_BtoS) + .value("SDOT_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_HtoD) + .value("SDOT_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2Z2Z_HtoS) + .value("SDOT_VG2_M2ZZI_BToS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_BToS) + .value("SDOT_VG2_M2ZZI_HToS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HToS) + .value("SDOT_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HtoD) + .value("SDOT_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_BtoS) + .value("SDOT_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoD) + .value("SDOT_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoS) + .value("SDOT_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_BtoS) + .value("SDOT_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoD) + .value("SDOT_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoS) + .value("SDOT_VG4_M4ZZI_BToS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_BToS) + .value("SDOT_VG4_M4ZZI_HToS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_HToS) + .value("SDOT_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZI_HtoD) + .value("SDOT_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_BtoS) + .value("SDOT_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_HtoD) + .value("SDOT_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4ZZ_HtoS) + .value("SDOT_ZZZI_BtoH", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZI_BtoH) + .value("SDOT_ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZI_BtoS) + .value("SDOT_ZZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZI_HtoD) + .value("SDOT_ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZI_HtoS) + .value("SDOT_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZ_BtoH) + .value("SDOT_ZZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZ_BtoS) + .value("SDOT_ZZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZ_HtoD) + .value("SDOT_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SDOT_ZZZ_HtoS) + .value("SDOTlanev16i8", LIEF::assembly::aarch64::OPCODE::SDOTlanev16i8) + .value("SDOTlanev8i8", LIEF::assembly::aarch64::OPCODE::SDOTlanev8i8) + .value("SDOTv16i8", LIEF::assembly::aarch64::OPCODE::SDOTv16i8) + .value("SDOTv8i8", LIEF::assembly::aarch64::OPCODE::SDOTv8i8) + .value("SEL_PPPP", LIEF::assembly::aarch64::OPCODE::SEL_PPPP) + .value("SEL_VG2_2ZC2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SEL_VG2_2ZC2Z2Z_B) + .value("SEL_VG2_2ZC2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SEL_VG2_2ZC2Z2Z_D) + .value("SEL_VG2_2ZC2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SEL_VG2_2ZC2Z2Z_H) + .value("SEL_VG2_2ZC2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SEL_VG2_2ZC2Z2Z_S) + .value("SEL_VG4_4ZC4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SEL_VG4_4ZC4Z4Z_B) + .value("SEL_VG4_4ZC4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SEL_VG4_4ZC4Z4Z_D) + .value("SEL_VG4_4ZC4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SEL_VG4_4ZC4Z4Z_H) + .value("SEL_VG4_4ZC4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SEL_VG4_4ZC4Z4Z_S) + .value("SEL_ZPZZ_B", LIEF::assembly::aarch64::OPCODE::SEL_ZPZZ_B) + .value("SEL_ZPZZ_D", LIEF::assembly::aarch64::OPCODE::SEL_ZPZZ_D) + .value("SEL_ZPZZ_H", LIEF::assembly::aarch64::OPCODE::SEL_ZPZZ_H) + .value("SEL_ZPZZ_S", LIEF::assembly::aarch64::OPCODE::SEL_ZPZZ_S) + .value("SETE", LIEF::assembly::aarch64::OPCODE::SETE) + .value("SETEN", LIEF::assembly::aarch64::OPCODE::SETEN) + .value("SETET", LIEF::assembly::aarch64::OPCODE::SETET) + .value("SETETN", LIEF::assembly::aarch64::OPCODE::SETETN) + .value("SETF16", LIEF::assembly::aarch64::OPCODE::SETF16) + .value("SETF8", LIEF::assembly::aarch64::OPCODE::SETF8) + .value("SETFFR", LIEF::assembly::aarch64::OPCODE::SETFFR) + .value("SETGM", LIEF::assembly::aarch64::OPCODE::SETGM) + .value("SETGMN", LIEF::assembly::aarch64::OPCODE::SETGMN) + .value("SETGMT", LIEF::assembly::aarch64::OPCODE::SETGMT) + .value("SETGMTN", LIEF::assembly::aarch64::OPCODE::SETGMTN) + .value("SETGOE", LIEF::assembly::aarch64::OPCODE::SETGOE) + .value("SETGOEN", LIEF::assembly::aarch64::OPCODE::SETGOEN) + .value("SETGOET", LIEF::assembly::aarch64::OPCODE::SETGOET) + .value("SETGOETN", LIEF::assembly::aarch64::OPCODE::SETGOETN) + .value("SETGOM", LIEF::assembly::aarch64::OPCODE::SETGOM) + .value("SETGOMN", LIEF::assembly::aarch64::OPCODE::SETGOMN) + .value("SETGOMT", LIEF::assembly::aarch64::OPCODE::SETGOMT) + .value("SETGOMTN", LIEF::assembly::aarch64::OPCODE::SETGOMTN) + .value("SETGOP", LIEF::assembly::aarch64::OPCODE::SETGOP) + .value("SETGOPN", LIEF::assembly::aarch64::OPCODE::SETGOPN) + .value("SETGOPT", LIEF::assembly::aarch64::OPCODE::SETGOPT) + .value("SETGOPTN", LIEF::assembly::aarch64::OPCODE::SETGOPTN) + .value("SETGP", LIEF::assembly::aarch64::OPCODE::SETGP) + .value("SETGPN", LIEF::assembly::aarch64::OPCODE::SETGPN) + .value("SETGPT", LIEF::assembly::aarch64::OPCODE::SETGPT) + .value("SETGPTN", LIEF::assembly::aarch64::OPCODE::SETGPTN) + .value("SETM", LIEF::assembly::aarch64::OPCODE::SETM) + .value("SETMN", LIEF::assembly::aarch64::OPCODE::SETMN) + .value("SETMT", LIEF::assembly::aarch64::OPCODE::SETMT) + .value("SETMTN", LIEF::assembly::aarch64::OPCODE::SETMTN) + .value("SETP", LIEF::assembly::aarch64::OPCODE::SETP) + .value("SETPN", LIEF::assembly::aarch64::OPCODE::SETPN) + .value("SETPT", LIEF::assembly::aarch64::OPCODE::SETPT) + .value("SETPTN", LIEF::assembly::aarch64::OPCODE::SETPTN) + .value("SHA1Crrr", LIEF::assembly::aarch64::OPCODE::SHA1Crrr) + .value("SHA1Hrr", LIEF::assembly::aarch64::OPCODE::SHA1Hrr) + .value("SHA1Mrrr", LIEF::assembly::aarch64::OPCODE::SHA1Mrrr) + .value("SHA1Prrr", LIEF::assembly::aarch64::OPCODE::SHA1Prrr) + .value("SHA1SU0rrr", LIEF::assembly::aarch64::OPCODE::SHA1SU0rrr) + .value("SHA1SU1rr", LIEF::assembly::aarch64::OPCODE::SHA1SU1rr) + .value("SHA256H2rrr", LIEF::assembly::aarch64::OPCODE::SHA256H2rrr) + .value("SHA256Hrrr", LIEF::assembly::aarch64::OPCODE::SHA256Hrrr) + .value("SHA256SU0rr", LIEF::assembly::aarch64::OPCODE::SHA256SU0rr) + .value("SHA256SU1rrr", LIEF::assembly::aarch64::OPCODE::SHA256SU1rrr) + .value("SHA512H", LIEF::assembly::aarch64::OPCODE::SHA512H) + .value("SHA512H2", LIEF::assembly::aarch64::OPCODE::SHA512H2) + .value("SHA512SU0", LIEF::assembly::aarch64::OPCODE::SHA512SU0) + .value("SHA512SU1", LIEF::assembly::aarch64::OPCODE::SHA512SU1) + .value("SHADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SHADD_ZPmZ_B) + .value("SHADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SHADD_ZPmZ_D) + .value("SHADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SHADD_ZPmZ_H) + .value("SHADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SHADD_ZPmZ_S) + .value("SHADDv16i8", LIEF::assembly::aarch64::OPCODE::SHADDv16i8) + .value("SHADDv2i32", LIEF::assembly::aarch64::OPCODE::SHADDv2i32) + .value("SHADDv4i16", LIEF::assembly::aarch64::OPCODE::SHADDv4i16) + .value("SHADDv4i32", LIEF::assembly::aarch64::OPCODE::SHADDv4i32) + .value("SHADDv8i16", LIEF::assembly::aarch64::OPCODE::SHADDv8i16) + .value("SHADDv8i8", LIEF::assembly::aarch64::OPCODE::SHADDv8i8) + .value("SHLLv16i8", LIEF::assembly::aarch64::OPCODE::SHLLv16i8) + .value("SHLLv2i32", LIEF::assembly::aarch64::OPCODE::SHLLv2i32) + .value("SHLLv4i16", LIEF::assembly::aarch64::OPCODE::SHLLv4i16) + .value("SHLLv4i32", LIEF::assembly::aarch64::OPCODE::SHLLv4i32) + .value("SHLLv8i16", LIEF::assembly::aarch64::OPCODE::SHLLv8i16) + .value("SHLLv8i8", LIEF::assembly::aarch64::OPCODE::SHLLv8i8) + .value("SHLd", LIEF::assembly::aarch64::OPCODE::SHLd) + .value("SHLv16i8_shift", LIEF::assembly::aarch64::OPCODE::SHLv16i8_shift) + .value("SHLv2i32_shift", LIEF::assembly::aarch64::OPCODE::SHLv2i32_shift) + .value("SHLv2i64_shift", LIEF::assembly::aarch64::OPCODE::SHLv2i64_shift) + .value("SHLv4i16_shift", LIEF::assembly::aarch64::OPCODE::SHLv4i16_shift) + .value("SHLv4i32_shift", LIEF::assembly::aarch64::OPCODE::SHLv4i32_shift) + .value("SHLv8i16_shift", LIEF::assembly::aarch64::OPCODE::SHLv8i16_shift) + .value("SHLv8i8_shift", LIEF::assembly::aarch64::OPCODE::SHLv8i8_shift) + .value("SHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::SHRNB_ZZI_B) + .value("SHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SHRNB_ZZI_H) + .value("SHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SHRNB_ZZI_S) + .value("SHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::SHRNT_ZZI_B) + .value("SHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SHRNT_ZZI_H) + .value("SHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SHRNT_ZZI_S) + .value("SHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SHRNv16i8_shift) + .value("SHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::SHRNv2i32_shift) + .value("SHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::SHRNv4i16_shift) + .value("SHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::SHRNv4i32_shift) + .value("SHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::SHRNv8i16_shift) + .value("SHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::SHRNv8i8_shift) + .value("SHSUBR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SHSUBR_ZPmZ_B) + .value("SHSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SHSUBR_ZPmZ_D) + .value("SHSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SHSUBR_ZPmZ_H) + .value("SHSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SHSUBR_ZPmZ_S) + .value("SHSUB_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPmZ_B) + .value("SHSUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPmZ_D) + .value("SHSUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPmZ_H) + .value("SHSUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPmZ_S) + .value("SHSUBv16i8", LIEF::assembly::aarch64::OPCODE::SHSUBv16i8) + .value("SHSUBv2i32", LIEF::assembly::aarch64::OPCODE::SHSUBv2i32) + .value("SHSUBv4i16", LIEF::assembly::aarch64::OPCODE::SHSUBv4i16) + .value("SHSUBv4i32", LIEF::assembly::aarch64::OPCODE::SHSUBv4i32) + .value("SHSUBv8i16", LIEF::assembly::aarch64::OPCODE::SHSUBv8i16) + .value("SHSUBv8i8", LIEF::assembly::aarch64::OPCODE::SHSUBv8i8) + .value("SHUH", LIEF::assembly::aarch64::OPCODE::SHUH) + .value("SLI_ZZI_B", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_B) + .value("SLI_ZZI_D", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_D) + .value("SLI_ZZI_H", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_H) + .value("SLI_ZZI_S", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_S) + .value("SLId", LIEF::assembly::aarch64::OPCODE::SLId) + .value("SLIv16i8_shift", LIEF::assembly::aarch64::OPCODE::SLIv16i8_shift) + .value("SLIv2i32_shift", LIEF::assembly::aarch64::OPCODE::SLIv2i32_shift) + .value("SLIv2i64_shift", LIEF::assembly::aarch64::OPCODE::SLIv2i64_shift) + .value("SLIv4i16_shift", LIEF::assembly::aarch64::OPCODE::SLIv4i16_shift) + .value("SLIv4i32_shift", LIEF::assembly::aarch64::OPCODE::SLIv4i32_shift) + .value("SLIv8i16_shift", LIEF::assembly::aarch64::OPCODE::SLIv8i16_shift) + .value("SLIv8i8_shift", LIEF::assembly::aarch64::OPCODE::SLIv8i8_shift) + .value("SM3PARTW1", LIEF::assembly::aarch64::OPCODE::SM3PARTW1) + .value("SM3PARTW2", LIEF::assembly::aarch64::OPCODE::SM3PARTW2) + .value("SM3SS1", LIEF::assembly::aarch64::OPCODE::SM3SS1) + .value("SM3TT1A", LIEF::assembly::aarch64::OPCODE::SM3TT1A) + .value("SM3TT1B", LIEF::assembly::aarch64::OPCODE::SM3TT1B) + .value("SM3TT2A", LIEF::assembly::aarch64::OPCODE::SM3TT2A) + .value("SM3TT2B", LIEF::assembly::aarch64::OPCODE::SM3TT2B) + .value("SM4E", LIEF::assembly::aarch64::OPCODE::SM4E) + .value("SM4EKEY_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SM4EKEY_ZZZ_S) + .value("SM4ENCKEY", LIEF::assembly::aarch64::OPCODE::SM4ENCKEY) + .value("SM4E_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SM4E_ZZZ_S) + .value("SMADDLrrr", LIEF::assembly::aarch64::OPCODE::SMADDLrrr) + .value("SMAXP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_B) + .value("SMAXP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_D) + .value("SMAXP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_H) + .value("SMAXP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_S) + .value("SMAXPv16i8", LIEF::assembly::aarch64::OPCODE::SMAXPv16i8) + .value("SMAXPv2i32", LIEF::assembly::aarch64::OPCODE::SMAXPv2i32) + .value("SMAXPv4i16", LIEF::assembly::aarch64::OPCODE::SMAXPv4i16) + .value("SMAXPv4i32", LIEF::assembly::aarch64::OPCODE::SMAXPv4i32) + .value("SMAXPv8i16", LIEF::assembly::aarch64::OPCODE::SMAXPv8i16) + .value("SMAXPv8i8", LIEF::assembly::aarch64::OPCODE::SMAXPv8i8) + .value("SMAXQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::SMAXQV_VPZ_B) + .value("SMAXQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::SMAXQV_VPZ_D) + .value("SMAXQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::SMAXQV_VPZ_H) + .value("SMAXQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::SMAXQV_VPZ_S) + .value("SMAXV_VPZ_B", LIEF::assembly::aarch64::OPCODE::SMAXV_VPZ_B) + .value("SMAXV_VPZ_D", LIEF::assembly::aarch64::OPCODE::SMAXV_VPZ_D) + .value("SMAXV_VPZ_H", LIEF::assembly::aarch64::OPCODE::SMAXV_VPZ_H) + .value("SMAXV_VPZ_S", LIEF::assembly::aarch64::OPCODE::SMAXV_VPZ_S) + .value("SMAXVv16i8v", LIEF::assembly::aarch64::OPCODE::SMAXVv16i8v) + .value("SMAXVv4i16v", LIEF::assembly::aarch64::OPCODE::SMAXVv4i16v) + .value("SMAXVv4i32v", LIEF::assembly::aarch64::OPCODE::SMAXVv4i32v) + .value("SMAXVv8i16v", LIEF::assembly::aarch64::OPCODE::SMAXVv8i16v) + .value("SMAXVv8i8v", LIEF::assembly::aarch64::OPCODE::SMAXVv8i8v) + .value("SMAXWri", LIEF::assembly::aarch64::OPCODE::SMAXWri) + .value("SMAXWrr", LIEF::assembly::aarch64::OPCODE::SMAXWrr) + .value("SMAXXri", LIEF::assembly::aarch64::OPCODE::SMAXXri) + .value("SMAXXrr", LIEF::assembly::aarch64::OPCODE::SMAXXrr) + .value("SMAX_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2Z2Z_B) + .value("SMAX_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2Z2Z_D) + .value("SMAX_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2Z2Z_H) + .value("SMAX_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2Z2Z_S) + .value("SMAX_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2ZZ_B) + .value("SMAX_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2ZZ_D) + .value("SMAX_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2ZZ_H) + .value("SMAX_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::SMAX_VG2_2ZZ_S) + .value("SMAX_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4Z4Z_B) + .value("SMAX_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4Z4Z_D) + .value("SMAX_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4Z4Z_H) + .value("SMAX_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4Z4Z_S) + .value("SMAX_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4ZZ_B) + .value("SMAX_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4ZZ_D) + .value("SMAX_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4ZZ_H) + .value("SMAX_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::SMAX_VG4_4ZZ_S) + .value("SMAX_ZI_B", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_B) + .value("SMAX_ZI_D", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_D) + .value("SMAX_ZI_H", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_H) + .value("SMAX_ZI_S", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_S) + .value("SMAX_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMAX_ZPmZ_B) + .value("SMAX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMAX_ZPmZ_D) + .value("SMAX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMAX_ZPmZ_H) + .value("SMAX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMAX_ZPmZ_S) + .value("SMAXv16i8", LIEF::assembly::aarch64::OPCODE::SMAXv16i8) + .value("SMAXv2i32", LIEF::assembly::aarch64::OPCODE::SMAXv2i32) + .value("SMAXv4i16", LIEF::assembly::aarch64::OPCODE::SMAXv4i16) + .value("SMAXv4i32", LIEF::assembly::aarch64::OPCODE::SMAXv4i32) + .value("SMAXv8i16", LIEF::assembly::aarch64::OPCODE::SMAXv8i16) + .value("SMAXv8i8", LIEF::assembly::aarch64::OPCODE::SMAXv8i8) + .value("SMC", LIEF::assembly::aarch64::OPCODE::SMC) + .value("SMINP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_B) + .value("SMINP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_D) + .value("SMINP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_H) + .value("SMINP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_S) + .value("SMINPv16i8", LIEF::assembly::aarch64::OPCODE::SMINPv16i8) + .value("SMINPv2i32", LIEF::assembly::aarch64::OPCODE::SMINPv2i32); + opcodes.value("SMINPv4i16", LIEF::assembly::aarch64::OPCODE::SMINPv4i16) + .value("SMINPv4i32", LIEF::assembly::aarch64::OPCODE::SMINPv4i32) + .value("SMINPv8i16", LIEF::assembly::aarch64::OPCODE::SMINPv8i16) + .value("SMINPv8i8", LIEF::assembly::aarch64::OPCODE::SMINPv8i8) + .value("SMINQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::SMINQV_VPZ_B) + .value("SMINQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::SMINQV_VPZ_D) + .value("SMINQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::SMINQV_VPZ_H) + .value("SMINQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::SMINQV_VPZ_S) + .value("SMINV_VPZ_B", LIEF::assembly::aarch64::OPCODE::SMINV_VPZ_B) + .value("SMINV_VPZ_D", LIEF::assembly::aarch64::OPCODE::SMINV_VPZ_D) + .value("SMINV_VPZ_H", LIEF::assembly::aarch64::OPCODE::SMINV_VPZ_H) + .value("SMINV_VPZ_S", LIEF::assembly::aarch64::OPCODE::SMINV_VPZ_S) + .value("SMINVv16i8v", LIEF::assembly::aarch64::OPCODE::SMINVv16i8v) + .value("SMINVv4i16v", LIEF::assembly::aarch64::OPCODE::SMINVv4i16v) + .value("SMINVv4i32v", LIEF::assembly::aarch64::OPCODE::SMINVv4i32v) + .value("SMINVv8i16v", LIEF::assembly::aarch64::OPCODE::SMINVv8i16v) + .value("SMINVv8i8v", LIEF::assembly::aarch64::OPCODE::SMINVv8i8v) + .value("SMINWri", LIEF::assembly::aarch64::OPCODE::SMINWri) + .value("SMINWrr", LIEF::assembly::aarch64::OPCODE::SMINWrr) + .value("SMINXri", LIEF::assembly::aarch64::OPCODE::SMINXri) + .value("SMINXrr", LIEF::assembly::aarch64::OPCODE::SMINXrr) + .value("SMIN_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2Z2Z_B) + .value("SMIN_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2Z2Z_D) + .value("SMIN_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2Z2Z_H) + .value("SMIN_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2Z2Z_S) + .value("SMIN_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2ZZ_B) + .value("SMIN_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2ZZ_D) + .value("SMIN_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2ZZ_H) + .value("SMIN_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::SMIN_VG2_2ZZ_S) + .value("SMIN_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4Z4Z_B) + .value("SMIN_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4Z4Z_D) + .value("SMIN_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4Z4Z_H) + .value("SMIN_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4Z4Z_S) + .value("SMIN_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4ZZ_B) + .value("SMIN_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4ZZ_D) + .value("SMIN_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4ZZ_H) + .value("SMIN_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::SMIN_VG4_4ZZ_S) + .value("SMIN_ZI_B", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_B) + .value("SMIN_ZI_D", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_D) + .value("SMIN_ZI_H", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_H) + .value("SMIN_ZI_S", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_S) + .value("SMIN_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMIN_ZPmZ_B) + .value("SMIN_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMIN_ZPmZ_D) + .value("SMIN_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMIN_ZPmZ_H) + .value("SMIN_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMIN_ZPmZ_S) + .value("SMINv16i8", LIEF::assembly::aarch64::OPCODE::SMINv16i8) + .value("SMINv2i32", LIEF::assembly::aarch64::OPCODE::SMINv2i32) + .value("SMINv4i16", LIEF::assembly::aarch64::OPCODE::SMINv4i16) + .value("SMINv4i32", LIEF::assembly::aarch64::OPCODE::SMINv4i32) + .value("SMINv8i16", LIEF::assembly::aarch64::OPCODE::SMINv8i16) + .value("SMINv8i8", LIEF::assembly::aarch64::OPCODE::SMINv8i8) + .value("SMLALB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMLALB_ZZZI_D) + .value("SMLALB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMLALB_ZZZI_S) + .value("SMLALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMLALB_ZZZ_D) + .value("SMLALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMLALB_ZZZ_H) + .value("SMLALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMLALB_ZZZ_S) + .value("SMLALL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZI_BtoS) + .value("SMLALL_MZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZI_HtoD) + .value("SMLALL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZ_BtoS) + .value("SMLALL_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_MZZ_HtoD) + .value("SMLALL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2Z2Z_BtoS) + .value("SMLALL_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2Z2Z_HtoD) + .value("SMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZI_BtoS) + .value("SMLALL_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZI_HtoD) + .value("SMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZ_BtoS) + .value("SMLALL_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG2_M2ZZ_HtoD) + .value("SMLALL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4Z4Z_BtoS) + .value("SMLALL_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4Z4Z_HtoD) + .value("SMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZI_BtoS) + .value("SMLALL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZI_HtoD) + .value("SMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZ_BtoS) + .value("SMLALL_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLALL_VG4_M4ZZ_HtoD) + .value("SMLALT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMLALT_ZZZI_D) + .value("SMLALT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMLALT_ZZZI_S) + .value("SMLALT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMLALT_ZZZ_D) + .value("SMLALT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMLALT_ZZZ_H) + .value("SMLALT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMLALT_ZZZ_S) + .value("SMLAL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_MZZI_HtoS) + .value("SMLAL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_MZZ_HtoS) + .value("SMLAL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2Z2Z_HtoS) + .value("SMLAL_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2ZZI_S) + .value("SMLAL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_VG2_M2ZZ_HtoS) + .value("SMLAL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4Z4Z_HtoS) + .value("SMLAL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4ZZI_HtoS) + .value("SMLAL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLAL_VG4_M4ZZ_HtoS) + .value("SMLALv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMLALv16i8_v8i16) + .value("SMLALv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SMLALv2i32_indexed) + .value("SMLALv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMLALv2i32_v2i64) + .value("SMLALv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SMLALv4i16_indexed) + .value("SMLALv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMLALv4i16_v4i32) + .value("SMLALv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SMLALv4i32_indexed) + .value("SMLALv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMLALv4i32_v2i64) + .value("SMLALv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SMLALv8i16_indexed) + .value("SMLALv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMLALv8i16_v4i32) + .value("SMLALv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMLALv8i8_v8i16) + .value("SMLSLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMLSLB_ZZZI_D) + .value("SMLSLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMLSLB_ZZZI_S) + .value("SMLSLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMLSLB_ZZZ_D) + .value("SMLSLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMLSLB_ZZZ_H) + .value("SMLSLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMLSLB_ZZZ_S) + .value("SMLSLL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZI_BtoS) + .value("SMLSLL_MZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZI_HtoD) + .value("SMLSLL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZ_BtoS) + .value("SMLSLL_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_MZZ_HtoD) + .value("SMLSLL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2Z2Z_BtoS) + .value("SMLSLL_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2Z2Z_HtoD) + .value("SMLSLL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZI_BtoS) + .value("SMLSLL_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZI_HtoD) + .value("SMLSLL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZ_BtoS) + .value("SMLSLL_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG2_M2ZZ_HtoD) + .value("SMLSLL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4Z4Z_BtoS) + .value("SMLSLL_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4Z4Z_HtoD) + .value("SMLSLL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZI_BtoS) + .value("SMLSLL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZI_HtoD) + .value("SMLSLL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZ_BtoS) + .value("SMLSLL_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMLSLL_VG4_M4ZZ_HtoD) + .value("SMLSLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMLSLT_ZZZI_D) + .value("SMLSLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMLSLT_ZZZI_S) + .value("SMLSLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMLSLT_ZZZ_D) + .value("SMLSLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMLSLT_ZZZ_H) + .value("SMLSLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMLSLT_ZZZ_S) + .value("SMLSL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_MZZI_HtoS) + .value("SMLSL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_MZZ_HtoS) + .value("SMLSL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2Z2Z_HtoS) + .value("SMLSL_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2ZZI_S) + .value("SMLSL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_VG2_M2ZZ_HtoS) + .value("SMLSL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4Z4Z_HtoS) + .value("SMLSL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4ZZI_HtoS) + .value("SMLSL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMLSL_VG4_M4ZZ_HtoS) + .value("SMLSLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMLSLv16i8_v8i16) + .value("SMLSLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SMLSLv2i32_indexed) + .value("SMLSLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMLSLv2i32_v2i64) + .value("SMLSLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SMLSLv4i16_indexed) + .value("SMLSLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMLSLv4i16_v4i32) + .value("SMLSLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SMLSLv4i32_indexed) + .value("SMLSLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMLSLv4i32_v2i64) + .value("SMLSLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SMLSLv8i16_indexed) + .value("SMLSLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMLSLv8i16_v4i32) + .value("SMLSLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMLSLv8i8_v8i16) + .value("SMMLA", LIEF::assembly::aarch64::OPCODE::SMMLA) + .value("SMMLA_ZZZ", LIEF::assembly::aarch64::OPCODE::SMMLA_ZZZ) + .value("SMOP4A_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_BToS) + .value("SMOP4A_M2Z2Z_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_HToS) + .value("SMOP4A_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2Z2Z_HtoD) + .value("SMOP4A_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_BToS) + .value("SMOP4A_M2ZZ_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_HToS) + .value("SMOP4A_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4A_M2ZZ_HtoD) + .value("SMOP4A_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_BToS) + .value("SMOP4A_MZ2Z_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_HToS) + .value("SMOP4A_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZ2Z_HtoD) + .value("SMOP4A_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_BToS) + .value("SMOP4A_MZZ_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_HToS) + .value("SMOP4A_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4A_MZZ_HtoD) + .value("SMOP4S_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_BToS) + .value("SMOP4S_M2Z2Z_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_HToS) + .value("SMOP4S_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2Z2Z_HtoD) + .value("SMOP4S_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_BToS) + .value("SMOP4S_M2ZZ_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_HToS) + .value("SMOP4S_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4S_M2ZZ_HtoD) + .value("SMOP4S_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_BToS) + .value("SMOP4S_MZ2Z_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_HToS) + .value("SMOP4S_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZ2Z_HtoD) + .value("SMOP4S_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_BToS) + .value("SMOP4S_MZZ_HToS", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_HToS) + .value("SMOP4S_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SMOP4S_MZZ_HtoD) + .value("SMOPA_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_D) + .value("SMOPA_MPPZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_HtoS) + .value("SMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::SMOPA_MPPZZ_S) + .value("SMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_D) + .value("SMOPS_MPPZZ_HtoS", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_HtoS) + .value("SMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::SMOPS_MPPZZ_S) + .value("SMOVvi16to32", LIEF::assembly::aarch64::OPCODE::SMOVvi16to32) + .value("SMOVvi16to32_idx0", LIEF::assembly::aarch64::OPCODE::SMOVvi16to32_idx0) + .value("SMOVvi16to64", LIEF::assembly::aarch64::OPCODE::SMOVvi16to64) + .value("SMOVvi16to64_idx0", LIEF::assembly::aarch64::OPCODE::SMOVvi16to64_idx0) + .value("SMOVvi32to64", LIEF::assembly::aarch64::OPCODE::SMOVvi32to64) + .value("SMOVvi32to64_idx0", LIEF::assembly::aarch64::OPCODE::SMOVvi32to64_idx0) + .value("SMOVvi8to32", LIEF::assembly::aarch64::OPCODE::SMOVvi8to32) + .value("SMOVvi8to32_idx0", LIEF::assembly::aarch64::OPCODE::SMOVvi8to32_idx0) + .value("SMOVvi8to64", LIEF::assembly::aarch64::OPCODE::SMOVvi8to64) + .value("SMOVvi8to64_idx0", LIEF::assembly::aarch64::OPCODE::SMOVvi8to64_idx0) + .value("SMSUBLrrr", LIEF::assembly::aarch64::OPCODE::SMSUBLrrr) + .value("SMULH_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMULH_ZPmZ_B) + .value("SMULH_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMULH_ZPmZ_D) + .value("SMULH_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMULH_ZPmZ_H) + .value("SMULH_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMULH_ZPmZ_S) + .value("SMULH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SMULH_ZZZ_B) + .value("SMULH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMULH_ZZZ_D) + .value("SMULH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMULH_ZZZ_H) + .value("SMULH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMULH_ZZZ_S) + .value("SMULHrr", LIEF::assembly::aarch64::OPCODE::SMULHrr) + .value("SMULLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMULLB_ZZZI_D) + .value("SMULLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMULLB_ZZZI_S) + .value("SMULLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMULLB_ZZZ_D) + .value("SMULLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMULLB_ZZZ_H) + .value("SMULLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMULLB_ZZZ_S) + .value("SMULLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SMULLT_ZZZI_D) + .value("SMULLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SMULLT_ZZZI_S) + .value("SMULLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SMULLT_ZZZ_D) + .value("SMULLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SMULLT_ZZZ_H) + .value("SMULLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SMULLT_ZZZ_S) + .value("SMULLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMULLv16i8_v8i16) + .value("SMULLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SMULLv2i32_indexed) + .value("SMULLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMULLv2i32_v2i64) + .value("SMULLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SMULLv4i16_indexed) + .value("SMULLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMULLv4i16_v4i32) + .value("SMULLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SMULLv4i32_indexed) + .value("SMULLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SMULLv4i32_v2i64) + .value("SMULLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SMULLv8i16_indexed) + .value("SMULLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SMULLv8i16_v4i32) + .value("SMULLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SMULLv8i8_v8i16) + .value("SPLICE_ZPZZ_B", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZZ_B) + .value("SPLICE_ZPZZ_D", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZZ_D) + .value("SPLICE_ZPZZ_H", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZZ_H) + .value("SPLICE_ZPZZ_S", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZZ_S) + .value("SPLICE_ZPZ_B", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZ_B) + .value("SPLICE_ZPZ_D", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZ_D) + .value("SPLICE_ZPZ_H", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZ_H) + .value("SPLICE_ZPZ_S", LIEF::assembly::aarch64::OPCODE::SPLICE_ZPZ_S) + .value("SQABS_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_B) + .value("SQABS_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_D) + .value("SQABS_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_H) + .value("SQABS_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_S) + .value("SQABS_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::SQABS_ZPzZ_B) + .value("SQABS_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::SQABS_ZPzZ_D) + .value("SQABS_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::SQABS_ZPzZ_H) + .value("SQABS_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::SQABS_ZPzZ_S) + .value("SQABSv16i8", LIEF::assembly::aarch64::OPCODE::SQABSv16i8) + .value("SQABSv1i16", LIEF::assembly::aarch64::OPCODE::SQABSv1i16) + .value("SQABSv1i32", LIEF::assembly::aarch64::OPCODE::SQABSv1i32) + .value("SQABSv1i64", LIEF::assembly::aarch64::OPCODE::SQABSv1i64) + .value("SQABSv1i8", LIEF::assembly::aarch64::OPCODE::SQABSv1i8) + .value("SQABSv2i32", LIEF::assembly::aarch64::OPCODE::SQABSv2i32) + .value("SQABSv2i64", LIEF::assembly::aarch64::OPCODE::SQABSv2i64) + .value("SQABSv4i16", LIEF::assembly::aarch64::OPCODE::SQABSv4i16) + .value("SQABSv4i32", LIEF::assembly::aarch64::OPCODE::SQABSv4i32) + .value("SQABSv8i16", LIEF::assembly::aarch64::OPCODE::SQABSv8i16) + .value("SQABSv8i8", LIEF::assembly::aarch64::OPCODE::SQABSv8i8) + .value("SQADD_ZI_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_B) + .value("SQADD_ZI_D", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_D) + .value("SQADD_ZI_H", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_H) + .value("SQADD_ZI_S", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_S) + .value("SQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZPmZ_B) + .value("SQADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQADD_ZPmZ_D) + .value("SQADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQADD_ZPmZ_H) + .value("SQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQADD_ZPmZ_S) + .value("SQADD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZZZ_B) + .value("SQADD_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQADD_ZZZ_D) + .value("SQADD_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQADD_ZZZ_H) + .value("SQADD_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQADD_ZZZ_S) + .value("SQADDv16i8", LIEF::assembly::aarch64::OPCODE::SQADDv16i8) + .value("SQADDv1i16", LIEF::assembly::aarch64::OPCODE::SQADDv1i16) + .value("SQADDv1i32", LIEF::assembly::aarch64::OPCODE::SQADDv1i32) + .value("SQADDv1i64", LIEF::assembly::aarch64::OPCODE::SQADDv1i64) + .value("SQADDv1i8", LIEF::assembly::aarch64::OPCODE::SQADDv1i8) + .value("SQADDv2i32", LIEF::assembly::aarch64::OPCODE::SQADDv2i32) + .value("SQADDv2i64", LIEF::assembly::aarch64::OPCODE::SQADDv2i64) + .value("SQADDv4i16", LIEF::assembly::aarch64::OPCODE::SQADDv4i16) + .value("SQADDv4i32", LIEF::assembly::aarch64::OPCODE::SQADDv4i32) + .value("SQADDv8i16", LIEF::assembly::aarch64::OPCODE::SQADDv8i16) + .value("SQADDv8i8", LIEF::assembly::aarch64::OPCODE::SQADDv8i8) + .value("SQCADD_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQCADD_ZZI_B) + .value("SQCADD_ZZI_D", LIEF::assembly::aarch64::OPCODE::SQCADD_ZZI_D) + .value("SQCADD_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQCADD_ZZI_H) + .value("SQCADD_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQCADD_ZZI_S) + .value("SQCVTN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::SQCVTN_Z2Z_StoH) + .value("SQCVTN_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::SQCVTN_Z4Z_DtoH) + .value("SQCVTN_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::SQCVTN_Z4Z_StoB) + .value("SQCVTUN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::SQCVTUN_Z2Z_StoH) + .value("SQCVTUN_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::SQCVTUN_Z4Z_DtoH) + .value("SQCVTUN_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::SQCVTUN_Z4Z_StoB) + .value("SQCVTU_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::SQCVTU_Z2Z_StoH) + .value("SQCVTU_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::SQCVTU_Z4Z_DtoH) + .value("SQCVTU_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::SQCVTU_Z4Z_StoB) + .value("SQCVT_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::SQCVT_Z2Z_StoH) + .value("SQCVT_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::SQCVT_Z4Z_DtoH) + .value("SQCVT_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::SQCVT_Z4Z_StoB) + .value("SQDECB_XPiI", LIEF::assembly::aarch64::OPCODE::SQDECB_XPiI) + .value("SQDECB_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQDECB_XPiWdI) + .value("SQDECD_XPiI", LIEF::assembly::aarch64::OPCODE::SQDECD_XPiI) + .value("SQDECD_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQDECD_XPiWdI) + .value("SQDECD_ZPiI", LIEF::assembly::aarch64::OPCODE::SQDECD_ZPiI) + .value("SQDECH_XPiI", LIEF::assembly::aarch64::OPCODE::SQDECH_XPiI) + .value("SQDECH_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQDECH_XPiWdI) + .value("SQDECH_ZPiI", LIEF::assembly::aarch64::OPCODE::SQDECH_ZPiI) + .value("SQDECP_XPWd_B", LIEF::assembly::aarch64::OPCODE::SQDECP_XPWd_B) + .value("SQDECP_XPWd_D", LIEF::assembly::aarch64::OPCODE::SQDECP_XPWd_D) + .value("SQDECP_XPWd_H", LIEF::assembly::aarch64::OPCODE::SQDECP_XPWd_H) + .value("SQDECP_XPWd_S", LIEF::assembly::aarch64::OPCODE::SQDECP_XPWd_S) + .value("SQDECP_XP_B", LIEF::assembly::aarch64::OPCODE::SQDECP_XP_B) + .value("SQDECP_XP_D", LIEF::assembly::aarch64::OPCODE::SQDECP_XP_D) + .value("SQDECP_XP_H", LIEF::assembly::aarch64::OPCODE::SQDECP_XP_H) + .value("SQDECP_XP_S", LIEF::assembly::aarch64::OPCODE::SQDECP_XP_S) + .value("SQDECP_ZP_D", LIEF::assembly::aarch64::OPCODE::SQDECP_ZP_D) + .value("SQDECP_ZP_H", LIEF::assembly::aarch64::OPCODE::SQDECP_ZP_H) + .value("SQDECP_ZP_S", LIEF::assembly::aarch64::OPCODE::SQDECP_ZP_S) + .value("SQDECW_XPiI", LIEF::assembly::aarch64::OPCODE::SQDECW_XPiI) + .value("SQDECW_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQDECW_XPiWdI) + .value("SQDECW_ZPiI", LIEF::assembly::aarch64::OPCODE::SQDECW_ZPiI) + .value("SQDMLALBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_D); + opcodes.value("SQDMLALBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_H) + .value("SQDMLALBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_S) + .value("SQDMLALB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZI_D) + .value("SQDMLALB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZI_S) + .value("SQDMLALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZ_D) + .value("SQDMLALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZ_H) + .value("SQDMLALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZ_S) + .value("SQDMLALT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMLALT_ZZZI_D) + .value("SQDMLALT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMLALT_ZZZI_S) + .value("SQDMLALT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLALT_ZZZ_D) + .value("SQDMLALT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLALT_ZZZ_H) + .value("SQDMLALT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLALT_ZZZ_S) + .value("SQDMLALi16", LIEF::assembly::aarch64::OPCODE::SQDMLALi16) + .value("SQDMLALi32", LIEF::assembly::aarch64::OPCODE::SQDMLALi32) + .value("SQDMLALv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv1i32_indexed) + .value("SQDMLALv1i64_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv1i64_indexed) + .value("SQDMLALv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv2i32_indexed) + .value("SQDMLALv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMLALv2i32_v2i64) + .value("SQDMLALv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv4i16_indexed) + .value("SQDMLALv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMLALv4i16_v4i32) + .value("SQDMLALv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv4i32_indexed) + .value("SQDMLALv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMLALv4i32_v2i64) + .value("SQDMLALv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLALv8i16_indexed) + .value("SQDMLALv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMLALv8i16_v4i32) + .value("SQDMLSLBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLSLBT_ZZZ_D) + .value("SQDMLSLBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLSLBT_ZZZ_H) + .value("SQDMLSLBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLSLBT_ZZZ_S) + .value("SQDMLSLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMLSLB_ZZZI_D) + .value("SQDMLSLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMLSLB_ZZZI_S) + .value("SQDMLSLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLSLB_ZZZ_D) + .value("SQDMLSLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLSLB_ZZZ_H) + .value("SQDMLSLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLSLB_ZZZ_S) + .value("SQDMLSLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMLSLT_ZZZI_D) + .value("SQDMLSLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMLSLT_ZZZI_S) + .value("SQDMLSLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLSLT_ZZZ_D) + .value("SQDMLSLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLSLT_ZZZ_H) + .value("SQDMLSLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLSLT_ZZZ_S) + .value("SQDMLSLi16", LIEF::assembly::aarch64::OPCODE::SQDMLSLi16) + .value("SQDMLSLi32", LIEF::assembly::aarch64::OPCODE::SQDMLSLi32) + .value("SQDMLSLv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv1i32_indexed) + .value("SQDMLSLv1i64_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv1i64_indexed) + .value("SQDMLSLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv2i32_indexed) + .value("SQDMLSLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMLSLv2i32_v2i64) + .value("SQDMLSLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv4i16_indexed) + .value("SQDMLSLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMLSLv4i16_v4i32) + .value("SQDMLSLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv4i32_indexed) + .value("SQDMLSLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMLSLv4i32_v2i64) + .value("SQDMLSLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMLSLv8i16_indexed) + .value("SQDMLSLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMLSLv8i16_v4i32) + .value("SQDMULH_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2Z2Z_B) + .value("SQDMULH_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2Z2Z_D) + .value("SQDMULH_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2Z2Z_H) + .value("SQDMULH_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2Z2Z_S) + .value("SQDMULH_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2ZZ_B) + .value("SQDMULH_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2ZZ_D) + .value("SQDMULH_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2ZZ_H) + .value("SQDMULH_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG2_2ZZ_S) + .value("SQDMULH_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4Z4Z_B) + .value("SQDMULH_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4Z4Z_D) + .value("SQDMULH_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4Z4Z_H) + .value("SQDMULH_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4Z4Z_S) + .value("SQDMULH_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4ZZ_B) + .value("SQDMULH_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4ZZ_D) + .value("SQDMULH_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4ZZ_H) + .value("SQDMULH_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_VG4_4ZZ_S) + .value("SQDMULH_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZI_D) + .value("SQDMULH_ZZZI_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZI_H) + .value("SQDMULH_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZI_S) + .value("SQDMULH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZ_B) + .value("SQDMULH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZ_D) + .value("SQDMULH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZ_H) + .value("SQDMULH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMULH_ZZZ_S) + .value("SQDMULHv1i16", LIEF::assembly::aarch64::OPCODE::SQDMULHv1i16) + .value("SQDMULHv1i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv1i16_indexed) + .value("SQDMULHv1i32", LIEF::assembly::aarch64::OPCODE::SQDMULHv1i32) + .value("SQDMULHv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv1i32_indexed) + .value("SQDMULHv2i32", LIEF::assembly::aarch64::OPCODE::SQDMULHv2i32) + .value("SQDMULHv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv2i32_indexed) + .value("SQDMULHv4i16", LIEF::assembly::aarch64::OPCODE::SQDMULHv4i16) + .value("SQDMULHv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv4i16_indexed) + .value("SQDMULHv4i32", LIEF::assembly::aarch64::OPCODE::SQDMULHv4i32) + .value("SQDMULHv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv4i32_indexed) + .value("SQDMULHv8i16", LIEF::assembly::aarch64::OPCODE::SQDMULHv8i16) + .value("SQDMULHv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULHv8i16_indexed) + .value("SQDMULLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMULLB_ZZZI_D) + .value("SQDMULLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMULLB_ZZZI_S) + .value("SQDMULLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMULLB_ZZZ_D) + .value("SQDMULLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMULLB_ZZZ_H) + .value("SQDMULLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMULLB_ZZZ_S) + .value("SQDMULLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMULLT_ZZZI_D) + .value("SQDMULLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMULLT_ZZZI_S) + .value("SQDMULLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMULLT_ZZZ_D) + .value("SQDMULLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMULLT_ZZZ_H) + .value("SQDMULLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMULLT_ZZZ_S) + .value("SQDMULLi16", LIEF::assembly::aarch64::OPCODE::SQDMULLi16) + .value("SQDMULLi32", LIEF::assembly::aarch64::OPCODE::SQDMULLi32) + .value("SQDMULLv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv1i32_indexed) + .value("SQDMULLv1i64_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv1i64_indexed) + .value("SQDMULLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv2i32_indexed) + .value("SQDMULLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMULLv2i32_v2i64) + .value("SQDMULLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv4i16_indexed) + .value("SQDMULLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMULLv4i16_v4i32) + .value("SQDMULLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv4i32_indexed) + .value("SQDMULLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SQDMULLv4i32_v2i64) + .value("SQDMULLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQDMULLv8i16_indexed) + .value("SQDMULLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SQDMULLv8i16_v4i32) + .value("SQINCB_XPiI", LIEF::assembly::aarch64::OPCODE::SQINCB_XPiI) + .value("SQINCB_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQINCB_XPiWdI) + .value("SQINCD_XPiI", LIEF::assembly::aarch64::OPCODE::SQINCD_XPiI) + .value("SQINCD_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQINCD_XPiWdI) + .value("SQINCD_ZPiI", LIEF::assembly::aarch64::OPCODE::SQINCD_ZPiI) + .value("SQINCH_XPiI", LIEF::assembly::aarch64::OPCODE::SQINCH_XPiI) + .value("SQINCH_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQINCH_XPiWdI) + .value("SQINCH_ZPiI", LIEF::assembly::aarch64::OPCODE::SQINCH_ZPiI) + .value("SQINCP_XPWd_B", LIEF::assembly::aarch64::OPCODE::SQINCP_XPWd_B) + .value("SQINCP_XPWd_D", LIEF::assembly::aarch64::OPCODE::SQINCP_XPWd_D) + .value("SQINCP_XPWd_H", LIEF::assembly::aarch64::OPCODE::SQINCP_XPWd_H) + .value("SQINCP_XPWd_S", LIEF::assembly::aarch64::OPCODE::SQINCP_XPWd_S) + .value("SQINCP_XP_B", LIEF::assembly::aarch64::OPCODE::SQINCP_XP_B) + .value("SQINCP_XP_D", LIEF::assembly::aarch64::OPCODE::SQINCP_XP_D) + .value("SQINCP_XP_H", LIEF::assembly::aarch64::OPCODE::SQINCP_XP_H) + .value("SQINCP_XP_S", LIEF::assembly::aarch64::OPCODE::SQINCP_XP_S) + .value("SQINCP_ZP_D", LIEF::assembly::aarch64::OPCODE::SQINCP_ZP_D) + .value("SQINCP_ZP_H", LIEF::assembly::aarch64::OPCODE::SQINCP_ZP_H) + .value("SQINCP_ZP_S", LIEF::assembly::aarch64::OPCODE::SQINCP_ZP_S) + .value("SQINCW_XPiI", LIEF::assembly::aarch64::OPCODE::SQINCW_XPiI) + .value("SQINCW_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQINCW_XPiWdI) + .value("SQINCW_ZPiI", LIEF::assembly::aarch64::OPCODE::SQINCW_ZPiI) + .value("SQNEG_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_B) + .value("SQNEG_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_D) + .value("SQNEG_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_H) + .value("SQNEG_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_S) + .value("SQNEG_ZPzZ_B", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPzZ_B) + .value("SQNEG_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPzZ_D) + .value("SQNEG_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPzZ_H) + .value("SQNEG_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPzZ_S) + .value("SQNEGv16i8", LIEF::assembly::aarch64::OPCODE::SQNEGv16i8) + .value("SQNEGv1i16", LIEF::assembly::aarch64::OPCODE::SQNEGv1i16) + .value("SQNEGv1i32", LIEF::assembly::aarch64::OPCODE::SQNEGv1i32) + .value("SQNEGv1i64", LIEF::assembly::aarch64::OPCODE::SQNEGv1i64) + .value("SQNEGv1i8", LIEF::assembly::aarch64::OPCODE::SQNEGv1i8) + .value("SQNEGv2i32", LIEF::assembly::aarch64::OPCODE::SQNEGv2i32) + .value("SQNEGv2i64", LIEF::assembly::aarch64::OPCODE::SQNEGv2i64) + .value("SQNEGv4i16", LIEF::assembly::aarch64::OPCODE::SQNEGv4i16) + .value("SQNEGv4i32", LIEF::assembly::aarch64::OPCODE::SQNEGv4i32) + .value("SQNEGv8i16", LIEF::assembly::aarch64::OPCODE::SQNEGv8i16) + .value("SQNEGv8i8", LIEF::assembly::aarch64::OPCODE::SQNEGv8i8) + .value("SQRDCMLAH_ZZZI_H", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZI_H) + .value("SQRDCMLAH_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZI_S) + .value("SQRDCMLAH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZ_B) + .value("SQRDCMLAH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZ_D) + .value("SQRDCMLAH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZ_H) + .value("SQRDCMLAH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQRDCMLAH_ZZZ_S) + .value("SQRDMLAH_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZI_D) + .value("SQRDMLAH_ZZZI_H", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZI_H) + .value("SQRDMLAH_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZI_S) + .value("SQRDMLAH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZ_B) + .value("SQRDMLAH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZ_D) + .value("SQRDMLAH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZ_H) + .value("SQRDMLAH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQRDMLAH_ZZZ_S) + .value("SQRDMLAHv1i16", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv1i16) + .value("SQRDMLAHv1i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv1i16_indexed) + .value("SQRDMLAHv1i32", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv1i32) + .value("SQRDMLAHv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv1i32_indexed) + .value("SQRDMLAHv2i32", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv2i32) + .value("SQRDMLAHv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv2i32_indexed) + .value("SQRDMLAHv4i16", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv4i16) + .value("SQRDMLAHv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv4i16_indexed) + .value("SQRDMLAHv4i32", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv4i32) + .value("SQRDMLAHv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv4i32_indexed) + .value("SQRDMLAHv8i16", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv8i16) + .value("SQRDMLAHv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLAHv8i16_indexed) + .value("SQRDMLSH_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZI_D) + .value("SQRDMLSH_ZZZI_H", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZI_H) + .value("SQRDMLSH_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZI_S) + .value("SQRDMLSH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZ_B) + .value("SQRDMLSH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZ_D) + .value("SQRDMLSH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZ_H) + .value("SQRDMLSH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQRDMLSH_ZZZ_S) + .value("SQRDMLSHv1i16", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv1i16) + .value("SQRDMLSHv1i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv1i16_indexed) + .value("SQRDMLSHv1i32", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv1i32) + .value("SQRDMLSHv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv1i32_indexed) + .value("SQRDMLSHv2i32", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv2i32) + .value("SQRDMLSHv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv2i32_indexed) + .value("SQRDMLSHv4i16", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv4i16) + .value("SQRDMLSHv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv4i16_indexed) + .value("SQRDMLSHv4i32", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv4i32) + .value("SQRDMLSHv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv4i32_indexed) + .value("SQRDMLSHv8i16", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv8i16) + .value("SQRDMLSHv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMLSHv8i16_indexed) + .value("SQRDMULH_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZI_D) + .value("SQRDMULH_ZZZI_H", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZI_H) + .value("SQRDMULH_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZI_S) + .value("SQRDMULH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZ_B) + .value("SQRDMULH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZ_D) + .value("SQRDMULH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZ_H) + .value("SQRDMULH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQRDMULH_ZZZ_S) + .value("SQRDMULHv1i16", LIEF::assembly::aarch64::OPCODE::SQRDMULHv1i16) + .value("SQRDMULHv1i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv1i16_indexed) + .value("SQRDMULHv1i32", LIEF::assembly::aarch64::OPCODE::SQRDMULHv1i32) + .value("SQRDMULHv1i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv1i32_indexed) + .value("SQRDMULHv2i32", LIEF::assembly::aarch64::OPCODE::SQRDMULHv2i32) + .value("SQRDMULHv2i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv2i32_indexed) + .value("SQRDMULHv4i16", LIEF::assembly::aarch64::OPCODE::SQRDMULHv4i16) + .value("SQRDMULHv4i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv4i16_indexed) + .value("SQRDMULHv4i32", LIEF::assembly::aarch64::OPCODE::SQRDMULHv4i32) + .value("SQRDMULHv4i32_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv4i32_indexed) + .value("SQRDMULHv8i16", LIEF::assembly::aarch64::OPCODE::SQRDMULHv8i16) + .value("SQRDMULHv8i16_indexed", LIEF::assembly::aarch64::OPCODE::SQRDMULHv8i16_indexed) + .value("SQRSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQRSHLR_ZPmZ_B) + .value("SQRSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQRSHLR_ZPmZ_D) + .value("SQRSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQRSHLR_ZPmZ_H) + .value("SQRSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQRSHLR_ZPmZ_S) + .value("SQRSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPmZ_B) + .value("SQRSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPmZ_D) + .value("SQRSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPmZ_H) + .value("SQRSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQRSHL_ZPmZ_S) + .value("SQRSHLv16i8", LIEF::assembly::aarch64::OPCODE::SQRSHLv16i8) + .value("SQRSHLv1i16", LIEF::assembly::aarch64::OPCODE::SQRSHLv1i16) + .value("SQRSHLv1i32", LIEF::assembly::aarch64::OPCODE::SQRSHLv1i32) + .value("SQRSHLv1i64", LIEF::assembly::aarch64::OPCODE::SQRSHLv1i64) + .value("SQRSHLv1i8", LIEF::assembly::aarch64::OPCODE::SQRSHLv1i8) + .value("SQRSHLv2i32", LIEF::assembly::aarch64::OPCODE::SQRSHLv2i32) + .value("SQRSHLv2i64", LIEF::assembly::aarch64::OPCODE::SQRSHLv2i64) + .value("SQRSHLv4i16", LIEF::assembly::aarch64::OPCODE::SQRSHLv4i16) + .value("SQRSHLv4i32", LIEF::assembly::aarch64::OPCODE::SQRSHLv4i32) + .value("SQRSHLv8i16", LIEF::assembly::aarch64::OPCODE::SQRSHLv8i16) + .value("SQRSHLv8i8", LIEF::assembly::aarch64::OPCODE::SQRSHLv8i8) + .value("SQRSHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRNB_ZZI_B) + .value("SQRSHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRNB_ZZI_H) + .value("SQRSHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQRSHRNB_ZZI_S) + .value("SQRSHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRNT_ZZI_B) + .value("SQRSHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRNT_ZZI_H) + .value("SQRSHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQRSHRNT_ZZI_S) + .value("SQRSHRN_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRN_VG4_Z4ZI_B) + .value("SQRSHRN_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRN_VG4_Z4ZI_H) + .value("SQRSHRN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::SQRSHRN_Z2ZI_HtoB) + .value("SQRSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQRSHRN_Z2ZI_StoH) + .value("SQRSHRNb", LIEF::assembly::aarch64::OPCODE::SQRSHRNb) + .value("SQRSHRNh", LIEF::assembly::aarch64::OPCODE::SQRSHRNh) + .value("SQRSHRNs", LIEF::assembly::aarch64::OPCODE::SQRSHRNs) + .value("SQRSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv16i8_shift) + .value("SQRSHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv2i32_shift) + .value("SQRSHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv4i16_shift) + .value("SQRSHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv4i32_shift) + .value("SQRSHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv8i16_shift) + .value("SQRSHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv8i8_shift) + .value("SQRSHRUNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRUNB_ZZI_B) + .value("SQRSHRUNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRUNB_ZZI_H) + .value("SQRSHRUNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQRSHRUNB_ZZI_S) + .value("SQRSHRUNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRUNT_ZZI_B) + .value("SQRSHRUNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRUNT_ZZI_H) + .value("SQRSHRUNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQRSHRUNT_ZZI_S) + .value("SQRSHRUN_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRUN_VG4_Z4ZI_B) + .value("SQRSHRUN_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRUN_VG4_Z4ZI_H) + .value("SQRSHRUN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::SQRSHRUN_Z2ZI_HtoB) + .value("SQRSHRUN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQRSHRUN_Z2ZI_StoH) + .value("SQRSHRUNb", LIEF::assembly::aarch64::OPCODE::SQRSHRUNb) + .value("SQRSHRUNh", LIEF::assembly::aarch64::OPCODE::SQRSHRUNh) + .value("SQRSHRUNs", LIEF::assembly::aarch64::OPCODE::SQRSHRUNs) + .value("SQRSHRUNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv16i8_shift) + .value("SQRSHRUNv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv2i32_shift) + .value("SQRSHRUNv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv4i16_shift) + .value("SQRSHRUNv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv4i32_shift) + .value("SQRSHRUNv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv8i16_shift) + .value("SQRSHRUNv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRUNv8i8_shift) + .value("SQRSHRU_VG2_Z2ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRU_VG2_Z2ZI_H) + .value("SQRSHRU_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRU_VG4_Z4ZI_B) + .value("SQRSHRU_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRU_VG4_Z4ZI_H) + .value("SQRSHR_VG2_Z2ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHR_VG2_Z2ZI_H) + .value("SQRSHR_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHR_VG4_Z4ZI_B) + .value("SQRSHR_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHR_VG4_Z4ZI_H) + .value("SQSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQSHLR_ZPmZ_B) + .value("SQSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQSHLR_ZPmZ_D) + .value("SQSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQSHLR_ZPmZ_H) + .value("SQSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSHLR_ZPmZ_S) + .value("SQSHLU_ZPmI_B", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPmI_B) + .value("SQSHLU_ZPmI_D", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPmI_D) + .value("SQSHLU_ZPmI_H", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPmI_H) + .value("SQSHLU_ZPmI_S", LIEF::assembly::aarch64::OPCODE::SQSHLU_ZPmI_S) + .value("SQSHLUb", LIEF::assembly::aarch64::OPCODE::SQSHLUb) + .value("SQSHLUd", LIEF::assembly::aarch64::OPCODE::SQSHLUd) + .value("SQSHLUh", LIEF::assembly::aarch64::OPCODE::SQSHLUh) + .value("SQSHLUs", LIEF::assembly::aarch64::OPCODE::SQSHLUs) + .value("SQSHLUv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv16i8_shift) + .value("SQSHLUv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv2i32_shift) + .value("SQSHLUv2i64_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv2i64_shift) + .value("SQSHLUv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv4i16_shift) + .value("SQSHLUv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv4i32_shift) + .value("SQSHLUv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv8i16_shift) + .value("SQSHLUv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHLUv8i8_shift) + .value("SQSHL_ZPmI_B", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmI_B) + .value("SQSHL_ZPmI_D", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmI_D) + .value("SQSHL_ZPmI_H", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmI_H) + .value("SQSHL_ZPmI_S", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmI_S) + .value("SQSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_B) + .value("SQSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_D) + .value("SQSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_H) + .value("SQSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_S); + opcodes.value("SQSHLb", LIEF::assembly::aarch64::OPCODE::SQSHLb) + .value("SQSHLd", LIEF::assembly::aarch64::OPCODE::SQSHLd) + .value("SQSHLh", LIEF::assembly::aarch64::OPCODE::SQSHLh) + .value("SQSHLs", LIEF::assembly::aarch64::OPCODE::SQSHLs) + .value("SQSHLv16i8", LIEF::assembly::aarch64::OPCODE::SQSHLv16i8) + .value("SQSHLv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv16i8_shift) + .value("SQSHLv1i16", LIEF::assembly::aarch64::OPCODE::SQSHLv1i16) + .value("SQSHLv1i32", LIEF::assembly::aarch64::OPCODE::SQSHLv1i32) + .value("SQSHLv1i64", LIEF::assembly::aarch64::OPCODE::SQSHLv1i64) + .value("SQSHLv1i8", LIEF::assembly::aarch64::OPCODE::SQSHLv1i8) + .value("SQSHLv2i32", LIEF::assembly::aarch64::OPCODE::SQSHLv2i32) + .value("SQSHLv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv2i32_shift) + .value("SQSHLv2i64", LIEF::assembly::aarch64::OPCODE::SQSHLv2i64) + .value("SQSHLv2i64_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv2i64_shift) + .value("SQSHLv4i16", LIEF::assembly::aarch64::OPCODE::SQSHLv4i16) + .value("SQSHLv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv4i16_shift) + .value("SQSHLv4i32", LIEF::assembly::aarch64::OPCODE::SQSHLv4i32) + .value("SQSHLv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv4i32_shift) + .value("SQSHLv8i16", LIEF::assembly::aarch64::OPCODE::SQSHLv8i16) + .value("SQSHLv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv8i16_shift) + .value("SQSHLv8i8", LIEF::assembly::aarch64::OPCODE::SQSHLv8i8) + .value("SQSHLv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHLv8i8_shift) + .value("SQSHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQSHRNB_ZZI_B) + .value("SQSHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQSHRNB_ZZI_H) + .value("SQSHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQSHRNB_ZZI_S) + .value("SQSHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQSHRNT_ZZI_B) + .value("SQSHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQSHRNT_ZZI_H) + .value("SQSHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQSHRNT_ZZI_S) + .value("SQSHRN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::SQSHRN_Z2ZI_HtoB) + .value("SQSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQSHRN_Z2ZI_StoH) + .value("SQSHRNb", LIEF::assembly::aarch64::OPCODE::SQSHRNb) + .value("SQSHRNh", LIEF::assembly::aarch64::OPCODE::SQSHRNh) + .value("SQSHRNs", LIEF::assembly::aarch64::OPCODE::SQSHRNs) + .value("SQSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv16i8_shift) + .value("SQSHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv2i32_shift) + .value("SQSHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv4i16_shift) + .value("SQSHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv4i32_shift) + .value("SQSHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv8i16_shift) + .value("SQSHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHRNv8i8_shift) + .value("SQSHRUNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQSHRUNB_ZZI_B) + .value("SQSHRUNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQSHRUNB_ZZI_H) + .value("SQSHRUNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQSHRUNB_ZZI_S) + .value("SQSHRUNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::SQSHRUNT_ZZI_B) + .value("SQSHRUNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SQSHRUNT_ZZI_H) + .value("SQSHRUNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SQSHRUNT_ZZI_S) + .value("SQSHRUN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::SQSHRUN_Z2ZI_HtoB) + .value("SQSHRUN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQSHRUN_Z2ZI_StoH) + .value("SQSHRUNb", LIEF::assembly::aarch64::OPCODE::SQSHRUNb) + .value("SQSHRUNh", LIEF::assembly::aarch64::OPCODE::SQSHRUNh) + .value("SQSHRUNs", LIEF::assembly::aarch64::OPCODE::SQSHRUNs) + .value("SQSHRUNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv16i8_shift) + .value("SQSHRUNv2i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv2i32_shift) + .value("SQSHRUNv4i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv4i16_shift) + .value("SQSHRUNv4i32_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv4i32_shift) + .value("SQSHRUNv8i16_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv8i16_shift) + .value("SQSHRUNv8i8_shift", LIEF::assembly::aarch64::OPCODE::SQSHRUNv8i8_shift) + .value("SQSUBR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQSUBR_ZPmZ_B) + .value("SQSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQSUBR_ZPmZ_D) + .value("SQSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQSUBR_ZPmZ_H) + .value("SQSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSUBR_ZPmZ_S) + .value("SQSUB_ZI_B", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_B) + .value("SQSUB_ZI_D", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_D) + .value("SQSUB_ZI_H", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_H) + .value("SQSUB_ZI_S", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_S) + .value("SQSUB_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQSUB_ZPmZ_B) + .value("SQSUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQSUB_ZPmZ_D) + .value("SQSUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQSUB_ZPmZ_H) + .value("SQSUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSUB_ZPmZ_S) + .value("SQSUB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SQSUB_ZZZ_B) + .value("SQSUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQSUB_ZZZ_D) + .value("SQSUB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQSUB_ZZZ_H) + .value("SQSUB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQSUB_ZZZ_S) + .value("SQSUBv16i8", LIEF::assembly::aarch64::OPCODE::SQSUBv16i8) + .value("SQSUBv1i16", LIEF::assembly::aarch64::OPCODE::SQSUBv1i16) + .value("SQSUBv1i32", LIEF::assembly::aarch64::OPCODE::SQSUBv1i32) + .value("SQSUBv1i64", LIEF::assembly::aarch64::OPCODE::SQSUBv1i64) + .value("SQSUBv1i8", LIEF::assembly::aarch64::OPCODE::SQSUBv1i8) + .value("SQSUBv2i32", LIEF::assembly::aarch64::OPCODE::SQSUBv2i32) + .value("SQSUBv2i64", LIEF::assembly::aarch64::OPCODE::SQSUBv2i64) + .value("SQSUBv4i16", LIEF::assembly::aarch64::OPCODE::SQSUBv4i16) + .value("SQSUBv4i32", LIEF::assembly::aarch64::OPCODE::SQSUBv4i32) + .value("SQSUBv8i16", LIEF::assembly::aarch64::OPCODE::SQSUBv8i16) + .value("SQSUBv8i8", LIEF::assembly::aarch64::OPCODE::SQSUBv8i8) + .value("SQXTNB_ZZ_B", LIEF::assembly::aarch64::OPCODE::SQXTNB_ZZ_B) + .value("SQXTNB_ZZ_H", LIEF::assembly::aarch64::OPCODE::SQXTNB_ZZ_H) + .value("SQXTNB_ZZ_S", LIEF::assembly::aarch64::OPCODE::SQXTNB_ZZ_S) + .value("SQXTNT_ZZ_B", LIEF::assembly::aarch64::OPCODE::SQXTNT_ZZ_B) + .value("SQXTNT_ZZ_H", LIEF::assembly::aarch64::OPCODE::SQXTNT_ZZ_H) + .value("SQXTNT_ZZ_S", LIEF::assembly::aarch64::OPCODE::SQXTNT_ZZ_S) + .value("SQXTNv16i8", LIEF::assembly::aarch64::OPCODE::SQXTNv16i8) + .value("SQXTNv1i16", LIEF::assembly::aarch64::OPCODE::SQXTNv1i16) + .value("SQXTNv1i32", LIEF::assembly::aarch64::OPCODE::SQXTNv1i32) + .value("SQXTNv1i8", LIEF::assembly::aarch64::OPCODE::SQXTNv1i8) + .value("SQXTNv2i32", LIEF::assembly::aarch64::OPCODE::SQXTNv2i32) + .value("SQXTNv4i16", LIEF::assembly::aarch64::OPCODE::SQXTNv4i16) + .value("SQXTNv4i32", LIEF::assembly::aarch64::OPCODE::SQXTNv4i32) + .value("SQXTNv8i16", LIEF::assembly::aarch64::OPCODE::SQXTNv8i16) + .value("SQXTNv8i8", LIEF::assembly::aarch64::OPCODE::SQXTNv8i8) + .value("SQXTUNB_ZZ_B", LIEF::assembly::aarch64::OPCODE::SQXTUNB_ZZ_B) + .value("SQXTUNB_ZZ_H", LIEF::assembly::aarch64::OPCODE::SQXTUNB_ZZ_H) + .value("SQXTUNB_ZZ_S", LIEF::assembly::aarch64::OPCODE::SQXTUNB_ZZ_S) + .value("SQXTUNT_ZZ_B", LIEF::assembly::aarch64::OPCODE::SQXTUNT_ZZ_B) + .value("SQXTUNT_ZZ_H", LIEF::assembly::aarch64::OPCODE::SQXTUNT_ZZ_H) + .value("SQXTUNT_ZZ_S", LIEF::assembly::aarch64::OPCODE::SQXTUNT_ZZ_S) + .value("SQXTUNv16i8", LIEF::assembly::aarch64::OPCODE::SQXTUNv16i8) + .value("SQXTUNv1i16", LIEF::assembly::aarch64::OPCODE::SQXTUNv1i16) + .value("SQXTUNv1i32", LIEF::assembly::aarch64::OPCODE::SQXTUNv1i32) + .value("SQXTUNv1i8", LIEF::assembly::aarch64::OPCODE::SQXTUNv1i8) + .value("SQXTUNv2i32", LIEF::assembly::aarch64::OPCODE::SQXTUNv2i32) + .value("SQXTUNv4i16", LIEF::assembly::aarch64::OPCODE::SQXTUNv4i16) + .value("SQXTUNv4i32", LIEF::assembly::aarch64::OPCODE::SQXTUNv4i32) + .value("SQXTUNv8i16", LIEF::assembly::aarch64::OPCODE::SQXTUNv8i16) + .value("SQXTUNv8i8", LIEF::assembly::aarch64::OPCODE::SQXTUNv8i8) + .value("SRHADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SRHADD_ZPmZ_B) + .value("SRHADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SRHADD_ZPmZ_D) + .value("SRHADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SRHADD_ZPmZ_H) + .value("SRHADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SRHADD_ZPmZ_S) + .value("SRHADDv16i8", LIEF::assembly::aarch64::OPCODE::SRHADDv16i8) + .value("SRHADDv2i32", LIEF::assembly::aarch64::OPCODE::SRHADDv2i32) + .value("SRHADDv4i16", LIEF::assembly::aarch64::OPCODE::SRHADDv4i16) + .value("SRHADDv4i32", LIEF::assembly::aarch64::OPCODE::SRHADDv4i32) + .value("SRHADDv8i16", LIEF::assembly::aarch64::OPCODE::SRHADDv8i16) + .value("SRHADDv8i8", LIEF::assembly::aarch64::OPCODE::SRHADDv8i8) + .value("SRI_ZZI_B", LIEF::assembly::aarch64::OPCODE::SRI_ZZI_B) + .value("SRI_ZZI_D", LIEF::assembly::aarch64::OPCODE::SRI_ZZI_D) + .value("SRI_ZZI_H", LIEF::assembly::aarch64::OPCODE::SRI_ZZI_H) + .value("SRI_ZZI_S", LIEF::assembly::aarch64::OPCODE::SRI_ZZI_S) + .value("SRId", LIEF::assembly::aarch64::OPCODE::SRId) + .value("SRIv16i8_shift", LIEF::assembly::aarch64::OPCODE::SRIv16i8_shift) + .value("SRIv2i32_shift", LIEF::assembly::aarch64::OPCODE::SRIv2i32_shift) + .value("SRIv2i64_shift", LIEF::assembly::aarch64::OPCODE::SRIv2i64_shift) + .value("SRIv4i16_shift", LIEF::assembly::aarch64::OPCODE::SRIv4i16_shift) + .value("SRIv4i32_shift", LIEF::assembly::aarch64::OPCODE::SRIv4i32_shift) + .value("SRIv8i16_shift", LIEF::assembly::aarch64::OPCODE::SRIv8i16_shift) + .value("SRIv8i8_shift", LIEF::assembly::aarch64::OPCODE::SRIv8i8_shift) + .value("SRSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SRSHLR_ZPmZ_B) + .value("SRSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SRSHLR_ZPmZ_D) + .value("SRSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SRSHLR_ZPmZ_H) + .value("SRSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SRSHLR_ZPmZ_S) + .value("SRSHL_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2Z2Z_B) + .value("SRSHL_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2Z2Z_D) + .value("SRSHL_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2Z2Z_H) + .value("SRSHL_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2Z2Z_S) + .value("SRSHL_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2ZZ_B) + .value("SRSHL_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2ZZ_D) + .value("SRSHL_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2ZZ_H) + .value("SRSHL_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::SRSHL_VG2_2ZZ_S) + .value("SRSHL_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4Z4Z_B) + .value("SRSHL_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4Z4Z_D) + .value("SRSHL_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4Z4Z_H) + .value("SRSHL_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4Z4Z_S) + .value("SRSHL_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4ZZ_B) + .value("SRSHL_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4ZZ_D) + .value("SRSHL_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4ZZ_H) + .value("SRSHL_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::SRSHL_VG4_4ZZ_S) + .value("SRSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPmZ_B) + .value("SRSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPmZ_D) + .value("SRSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPmZ_H) + .value("SRSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPmZ_S) + .value("SRSHLv16i8", LIEF::assembly::aarch64::OPCODE::SRSHLv16i8) + .value("SRSHLv1i64", LIEF::assembly::aarch64::OPCODE::SRSHLv1i64) + .value("SRSHLv2i32", LIEF::assembly::aarch64::OPCODE::SRSHLv2i32) + .value("SRSHLv2i64", LIEF::assembly::aarch64::OPCODE::SRSHLv2i64) + .value("SRSHLv4i16", LIEF::assembly::aarch64::OPCODE::SRSHLv4i16) + .value("SRSHLv4i32", LIEF::assembly::aarch64::OPCODE::SRSHLv4i32) + .value("SRSHLv8i16", LIEF::assembly::aarch64::OPCODE::SRSHLv8i16) + .value("SRSHLv8i8", LIEF::assembly::aarch64::OPCODE::SRSHLv8i8) + .value("SRSHR_ZPmI_B", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPmI_B) + .value("SRSHR_ZPmI_D", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPmI_D) + .value("SRSHR_ZPmI_H", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPmI_H) + .value("SRSHR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPmI_S) + .value("SRSHRd", LIEF::assembly::aarch64::OPCODE::SRSHRd) + .value("SRSHRv16i8_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv16i8_shift) + .value("SRSHRv2i32_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv2i32_shift) + .value("SRSHRv2i64_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv2i64_shift) + .value("SRSHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv4i16_shift) + .value("SRSHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv4i32_shift) + .value("SRSHRv8i16_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv8i16_shift) + .value("SRSHRv8i8_shift", LIEF::assembly::aarch64::OPCODE::SRSHRv8i8_shift) + .value("SRSRA_ZZI_B", LIEF::assembly::aarch64::OPCODE::SRSRA_ZZI_B) + .value("SRSRA_ZZI_D", LIEF::assembly::aarch64::OPCODE::SRSRA_ZZI_D) + .value("SRSRA_ZZI_H", LIEF::assembly::aarch64::OPCODE::SRSRA_ZZI_H) + .value("SRSRA_ZZI_S", LIEF::assembly::aarch64::OPCODE::SRSRA_ZZI_S) + .value("SRSRAd", LIEF::assembly::aarch64::OPCODE::SRSRAd) + .value("SRSRAv16i8_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv16i8_shift) + .value("SRSRAv2i32_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv2i32_shift) + .value("SRSRAv2i64_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv2i64_shift) + .value("SRSRAv4i16_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv4i16_shift) + .value("SRSRAv4i32_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv4i32_shift) + .value("SRSRAv8i16_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv8i16_shift) + .value("SRSRAv8i8_shift", LIEF::assembly::aarch64::OPCODE::SRSRAv8i8_shift) + .value("SSHLLB_ZZI_D", LIEF::assembly::aarch64::OPCODE::SSHLLB_ZZI_D) + .value("SSHLLB_ZZI_H", LIEF::assembly::aarch64::OPCODE::SSHLLB_ZZI_H) + .value("SSHLLB_ZZI_S", LIEF::assembly::aarch64::OPCODE::SSHLLB_ZZI_S) + .value("SSHLLT_ZZI_D", LIEF::assembly::aarch64::OPCODE::SSHLLT_ZZI_D) + .value("SSHLLT_ZZI_H", LIEF::assembly::aarch64::OPCODE::SSHLLT_ZZI_H) + .value("SSHLLT_ZZI_S", LIEF::assembly::aarch64::OPCODE::SSHLLT_ZZI_S) + .value("SSHLLv16i8_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv16i8_shift) + .value("SSHLLv2i32_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv2i32_shift) + .value("SSHLLv4i16_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv4i16_shift) + .value("SSHLLv4i32_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv4i32_shift) + .value("SSHLLv8i16_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv8i16_shift) + .value("SSHLLv8i8_shift", LIEF::assembly::aarch64::OPCODE::SSHLLv8i8_shift) + .value("SSHLv16i8", LIEF::assembly::aarch64::OPCODE::SSHLv16i8) + .value("SSHLv1i64", LIEF::assembly::aarch64::OPCODE::SSHLv1i64) + .value("SSHLv2i32", LIEF::assembly::aarch64::OPCODE::SSHLv2i32) + .value("SSHLv2i64", LIEF::assembly::aarch64::OPCODE::SSHLv2i64) + .value("SSHLv4i16", LIEF::assembly::aarch64::OPCODE::SSHLv4i16) + .value("SSHLv4i32", LIEF::assembly::aarch64::OPCODE::SSHLv4i32) + .value("SSHLv8i16", LIEF::assembly::aarch64::OPCODE::SSHLv8i16) + .value("SSHLv8i8", LIEF::assembly::aarch64::OPCODE::SSHLv8i8) + .value("SSHRd", LIEF::assembly::aarch64::OPCODE::SSHRd) + .value("SSHRv16i8_shift", LIEF::assembly::aarch64::OPCODE::SSHRv16i8_shift) + .value("SSHRv2i32_shift", LIEF::assembly::aarch64::OPCODE::SSHRv2i32_shift) + .value("SSHRv2i64_shift", LIEF::assembly::aarch64::OPCODE::SSHRv2i64_shift) + .value("SSHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::SSHRv4i16_shift) + .value("SSHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::SSHRv4i32_shift) + .value("SSHRv8i16_shift", LIEF::assembly::aarch64::OPCODE::SSHRv8i16_shift) + .value("SSHRv8i8_shift", LIEF::assembly::aarch64::OPCODE::SSHRv8i8_shift) + .value("SSRA_ZZI_B", LIEF::assembly::aarch64::OPCODE::SSRA_ZZI_B) + .value("SSRA_ZZI_D", LIEF::assembly::aarch64::OPCODE::SSRA_ZZI_D) + .value("SSRA_ZZI_H", LIEF::assembly::aarch64::OPCODE::SSRA_ZZI_H) + .value("SSRA_ZZI_S", LIEF::assembly::aarch64::OPCODE::SSRA_ZZI_S) + .value("SSRAd", LIEF::assembly::aarch64::OPCODE::SSRAd) + .value("SSRAv16i8_shift", LIEF::assembly::aarch64::OPCODE::SSRAv16i8_shift) + .value("SSRAv2i32_shift", LIEF::assembly::aarch64::OPCODE::SSRAv2i32_shift) + .value("SSRAv2i64_shift", LIEF::assembly::aarch64::OPCODE::SSRAv2i64_shift) + .value("SSRAv4i16_shift", LIEF::assembly::aarch64::OPCODE::SSRAv4i16_shift) + .value("SSRAv4i32_shift", LIEF::assembly::aarch64::OPCODE::SSRAv4i32_shift) + .value("SSRAv8i16_shift", LIEF::assembly::aarch64::OPCODE::SSRAv8i16_shift) + .value("SSRAv8i8_shift", LIEF::assembly::aarch64::OPCODE::SSRAv8i8_shift) + .value("SST1B_D", LIEF::assembly::aarch64::OPCODE::SST1B_D) + .value("SST1B_D_IMM", LIEF::assembly::aarch64::OPCODE::SST1B_D_IMM) + .value("SST1B_D_SXTW", LIEF::assembly::aarch64::OPCODE::SST1B_D_SXTW) + .value("SST1B_D_UXTW", LIEF::assembly::aarch64::OPCODE::SST1B_D_UXTW) + .value("SST1B_S_IMM", LIEF::assembly::aarch64::OPCODE::SST1B_S_IMM) + .value("SST1B_S_SXTW", LIEF::assembly::aarch64::OPCODE::SST1B_S_SXTW) + .value("SST1B_S_UXTW", LIEF::assembly::aarch64::OPCODE::SST1B_S_UXTW) + .value("SST1D", LIEF::assembly::aarch64::OPCODE::SST1D) + .value("SST1D_IMM", LIEF::assembly::aarch64::OPCODE::SST1D_IMM) + .value("SST1D_SCALED", LIEF::assembly::aarch64::OPCODE::SST1D_SCALED) + .value("SST1D_SXTW", LIEF::assembly::aarch64::OPCODE::SST1D_SXTW) + .value("SST1D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1D_SXTW_SCALED) + .value("SST1D_UXTW", LIEF::assembly::aarch64::OPCODE::SST1D_UXTW) + .value("SST1D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1D_UXTW_SCALED) + .value("SST1H_D", LIEF::assembly::aarch64::OPCODE::SST1H_D) + .value("SST1H_D_IMM", LIEF::assembly::aarch64::OPCODE::SST1H_D_IMM) + .value("SST1H_D_SCALED", LIEF::assembly::aarch64::OPCODE::SST1H_D_SCALED) + .value("SST1H_D_SXTW", LIEF::assembly::aarch64::OPCODE::SST1H_D_SXTW) + .value("SST1H_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1H_D_SXTW_SCALED) + .value("SST1H_D_UXTW", LIEF::assembly::aarch64::OPCODE::SST1H_D_UXTW) + .value("SST1H_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1H_D_UXTW_SCALED) + .value("SST1H_S_IMM", LIEF::assembly::aarch64::OPCODE::SST1H_S_IMM) + .value("SST1H_S_SXTW", LIEF::assembly::aarch64::OPCODE::SST1H_S_SXTW) + .value("SST1H_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1H_S_SXTW_SCALED) + .value("SST1H_S_UXTW", LIEF::assembly::aarch64::OPCODE::SST1H_S_UXTW) + .value("SST1H_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1H_S_UXTW_SCALED) + .value("SST1Q", LIEF::assembly::aarch64::OPCODE::SST1Q) + .value("SST1W_D", LIEF::assembly::aarch64::OPCODE::SST1W_D) + .value("SST1W_D_IMM", LIEF::assembly::aarch64::OPCODE::SST1W_D_IMM) + .value("SST1W_D_SCALED", LIEF::assembly::aarch64::OPCODE::SST1W_D_SCALED) + .value("SST1W_D_SXTW", LIEF::assembly::aarch64::OPCODE::SST1W_D_SXTW) + .value("SST1W_D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1W_D_SXTW_SCALED) + .value("SST1W_D_UXTW", LIEF::assembly::aarch64::OPCODE::SST1W_D_UXTW) + .value("SST1W_D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1W_D_UXTW_SCALED) + .value("SST1W_IMM", LIEF::assembly::aarch64::OPCODE::SST1W_IMM) + .value("SST1W_SXTW", LIEF::assembly::aarch64::OPCODE::SST1W_SXTW) + .value("SST1W_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1W_SXTW_SCALED) + .value("SST1W_UXTW", LIEF::assembly::aarch64::OPCODE::SST1W_UXTW) + .value("SST1W_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1W_UXTW_SCALED) + .value("SSUBLBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBLBT_ZZZ_D) + .value("SSUBLBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBLBT_ZZZ_H) + .value("SSUBLBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBLBT_ZZZ_S) + .value("SSUBLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBLB_ZZZ_D) + .value("SSUBLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBLB_ZZZ_H) + .value("SSUBLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBLB_ZZZ_S) + .value("SSUBLTB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBLTB_ZZZ_D) + .value("SSUBLTB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBLTB_ZZZ_H) + .value("SSUBLTB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBLTB_ZZZ_S) + .value("SSUBLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBLT_ZZZ_D) + .value("SSUBLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBLT_ZZZ_H) + .value("SSUBLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBLT_ZZZ_S) + .value("SSUBLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBLv16i8_v8i16) + .value("SSUBLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SSUBLv2i32_v2i64) + .value("SSUBLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBLv4i16_v4i32) + .value("SSUBLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SSUBLv4i32_v2i64) + .value("SSUBLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBLv8i16_v4i32) + .value("SSUBLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBLv8i8_v8i16) + .value("SSUBWB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBWB_ZZZ_D) + .value("SSUBWB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBWB_ZZZ_H) + .value("SSUBWB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBWB_ZZZ_S) + .value("SSUBWT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SSUBWT_ZZZ_D) + .value("SSUBWT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SSUBWT_ZZZ_H) + .value("SSUBWT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SSUBWT_ZZZ_S) + .value("SSUBWv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBWv16i8_v8i16) + .value("SSUBWv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::SSUBWv2i32_v2i64) + .value("SSUBWv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBWv4i16_v4i32) + .value("SSUBWv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SSUBWv4i32_v2i64) + .value("SSUBWv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBWv8i16_v4i32) + .value("SSUBWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBWv8i8_v8i16); + opcodes.value("ST1B", LIEF::assembly::aarch64::OPCODE::ST1B) + .value("ST1B_2Z", LIEF::assembly::aarch64::OPCODE::ST1B_2Z) + .value("ST1B_2Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_2Z_IMM) + .value("ST1B_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1B_2Z_STRIDED) + .value("ST1B_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_2Z_STRIDED_IMM) + .value("ST1B_4Z", LIEF::assembly::aarch64::OPCODE::ST1B_4Z) + .value("ST1B_4Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_4Z_IMM) + .value("ST1B_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1B_4Z_STRIDED) + .value("ST1B_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_4Z_STRIDED_IMM) + .value("ST1B_D", LIEF::assembly::aarch64::OPCODE::ST1B_D) + .value("ST1B_D_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_D_IMM) + .value("ST1B_H", LIEF::assembly::aarch64::OPCODE::ST1B_H) + .value("ST1B_H_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_H_IMM) + .value("ST1B_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_IMM) + .value("ST1B_S", LIEF::assembly::aarch64::OPCODE::ST1B_S) + .value("ST1B_S_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_S_IMM) + .value("ST1D", LIEF::assembly::aarch64::OPCODE::ST1D) + .value("ST1D_2Z", LIEF::assembly::aarch64::OPCODE::ST1D_2Z) + .value("ST1D_2Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_2Z_IMM) + .value("ST1D_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1D_2Z_STRIDED) + .value("ST1D_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_2Z_STRIDED_IMM) + .value("ST1D_4Z", LIEF::assembly::aarch64::OPCODE::ST1D_4Z) + .value("ST1D_4Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_4Z_IMM) + .value("ST1D_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1D_4Z_STRIDED) + .value("ST1D_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_4Z_STRIDED_IMM) + .value("ST1D_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_IMM) + .value("ST1D_Q", LIEF::assembly::aarch64::OPCODE::ST1D_Q) + .value("ST1D_Q_IMM", LIEF::assembly::aarch64::OPCODE::ST1D_Q_IMM) + .value("ST1Fourv16b", LIEF::assembly::aarch64::OPCODE::ST1Fourv16b) + .value("ST1Fourv16b_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv16b_POST) + .value("ST1Fourv1d", LIEF::assembly::aarch64::OPCODE::ST1Fourv1d) + .value("ST1Fourv1d_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv1d_POST) + .value("ST1Fourv2d", LIEF::assembly::aarch64::OPCODE::ST1Fourv2d) + .value("ST1Fourv2d_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv2d_POST) + .value("ST1Fourv2s", LIEF::assembly::aarch64::OPCODE::ST1Fourv2s) + .value("ST1Fourv2s_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv2s_POST) + .value("ST1Fourv4h", LIEF::assembly::aarch64::OPCODE::ST1Fourv4h) + .value("ST1Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv4h_POST) + .value("ST1Fourv4s", LIEF::assembly::aarch64::OPCODE::ST1Fourv4s) + .value("ST1Fourv4s_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv4s_POST) + .value("ST1Fourv8b", LIEF::assembly::aarch64::OPCODE::ST1Fourv8b) + .value("ST1Fourv8b_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv8b_POST) + .value("ST1Fourv8h", LIEF::assembly::aarch64::OPCODE::ST1Fourv8h) + .value("ST1Fourv8h_POST", LIEF::assembly::aarch64::OPCODE::ST1Fourv8h_POST) + .value("ST1H", LIEF::assembly::aarch64::OPCODE::ST1H) + .value("ST1H_2Z", LIEF::assembly::aarch64::OPCODE::ST1H_2Z) + .value("ST1H_2Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_2Z_IMM) + .value("ST1H_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1H_2Z_STRIDED) + .value("ST1H_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_2Z_STRIDED_IMM) + .value("ST1H_4Z", LIEF::assembly::aarch64::OPCODE::ST1H_4Z) + .value("ST1H_4Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_4Z_IMM) + .value("ST1H_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1H_4Z_STRIDED) + .value("ST1H_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_4Z_STRIDED_IMM) + .value("ST1H_D", LIEF::assembly::aarch64::OPCODE::ST1H_D) + .value("ST1H_D_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_D_IMM) + .value("ST1H_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_IMM) + .value("ST1H_S", LIEF::assembly::aarch64::OPCODE::ST1H_S) + .value("ST1H_S_IMM", LIEF::assembly::aarch64::OPCODE::ST1H_S_IMM) + .value("ST1Onev16b", LIEF::assembly::aarch64::OPCODE::ST1Onev16b) + .value("ST1Onev16b_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev16b_POST) + .value("ST1Onev1d", LIEF::assembly::aarch64::OPCODE::ST1Onev1d) + .value("ST1Onev1d_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev1d_POST) + .value("ST1Onev2d", LIEF::assembly::aarch64::OPCODE::ST1Onev2d) + .value("ST1Onev2d_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev2d_POST) + .value("ST1Onev2s", LIEF::assembly::aarch64::OPCODE::ST1Onev2s) + .value("ST1Onev2s_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev2s_POST) + .value("ST1Onev4h", LIEF::assembly::aarch64::OPCODE::ST1Onev4h) + .value("ST1Onev4h_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev4h_POST) + .value("ST1Onev4s", LIEF::assembly::aarch64::OPCODE::ST1Onev4s) + .value("ST1Onev4s_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev4s_POST) + .value("ST1Onev8b", LIEF::assembly::aarch64::OPCODE::ST1Onev8b) + .value("ST1Onev8b_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev8b_POST) + .value("ST1Onev8h", LIEF::assembly::aarch64::OPCODE::ST1Onev8h) + .value("ST1Onev8h_POST", LIEF::assembly::aarch64::OPCODE::ST1Onev8h_POST) + .value("ST1Threev16b", LIEF::assembly::aarch64::OPCODE::ST1Threev16b) + .value("ST1Threev16b_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev16b_POST) + .value("ST1Threev1d", LIEF::assembly::aarch64::OPCODE::ST1Threev1d) + .value("ST1Threev1d_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev1d_POST) + .value("ST1Threev2d", LIEF::assembly::aarch64::OPCODE::ST1Threev2d) + .value("ST1Threev2d_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev2d_POST) + .value("ST1Threev2s", LIEF::assembly::aarch64::OPCODE::ST1Threev2s) + .value("ST1Threev2s_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev2s_POST) + .value("ST1Threev4h", LIEF::assembly::aarch64::OPCODE::ST1Threev4h) + .value("ST1Threev4h_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev4h_POST) + .value("ST1Threev4s", LIEF::assembly::aarch64::OPCODE::ST1Threev4s) + .value("ST1Threev4s_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev4s_POST) + .value("ST1Threev8b", LIEF::assembly::aarch64::OPCODE::ST1Threev8b) + .value("ST1Threev8b_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev8b_POST) + .value("ST1Threev8h", LIEF::assembly::aarch64::OPCODE::ST1Threev8h) + .value("ST1Threev8h_POST", LIEF::assembly::aarch64::OPCODE::ST1Threev8h_POST) + .value("ST1Twov16b", LIEF::assembly::aarch64::OPCODE::ST1Twov16b) + .value("ST1Twov16b_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov16b_POST) + .value("ST1Twov1d", LIEF::assembly::aarch64::OPCODE::ST1Twov1d) + .value("ST1Twov1d_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov1d_POST) + .value("ST1Twov2d", LIEF::assembly::aarch64::OPCODE::ST1Twov2d) + .value("ST1Twov2d_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov2d_POST) + .value("ST1Twov2s", LIEF::assembly::aarch64::OPCODE::ST1Twov2s) + .value("ST1Twov2s_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov2s_POST) + .value("ST1Twov4h", LIEF::assembly::aarch64::OPCODE::ST1Twov4h) + .value("ST1Twov4h_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov4h_POST) + .value("ST1Twov4s", LIEF::assembly::aarch64::OPCODE::ST1Twov4s) + .value("ST1Twov4s_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov4s_POST) + .value("ST1Twov8b", LIEF::assembly::aarch64::OPCODE::ST1Twov8b) + .value("ST1Twov8b_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov8b_POST) + .value("ST1Twov8h", LIEF::assembly::aarch64::OPCODE::ST1Twov8h) + .value("ST1Twov8h_POST", LIEF::assembly::aarch64::OPCODE::ST1Twov8h_POST) + .value("ST1W", LIEF::assembly::aarch64::OPCODE::ST1W) + .value("ST1W_2Z", LIEF::assembly::aarch64::OPCODE::ST1W_2Z) + .value("ST1W_2Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_2Z_IMM) + .value("ST1W_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1W_2Z_STRIDED) + .value("ST1W_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_2Z_STRIDED_IMM) + .value("ST1W_4Z", LIEF::assembly::aarch64::OPCODE::ST1W_4Z) + .value("ST1W_4Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_4Z_IMM) + .value("ST1W_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1W_4Z_STRIDED) + .value("ST1W_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_4Z_STRIDED_IMM) + .value("ST1W_D", LIEF::assembly::aarch64::OPCODE::ST1W_D) + .value("ST1W_D_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_D_IMM) + .value("ST1W_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_IMM) + .value("ST1W_Q", LIEF::assembly::aarch64::OPCODE::ST1W_Q) + .value("ST1W_Q_IMM", LIEF::assembly::aarch64::OPCODE::ST1W_Q_IMM) + .value("ST1_MXIPXX_H_B", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_H_B) + .value("ST1_MXIPXX_H_D", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_H_D) + .value("ST1_MXIPXX_H_H", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_H_H) + .value("ST1_MXIPXX_H_Q", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_H_Q) + .value("ST1_MXIPXX_H_S", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_H_S) + .value("ST1_MXIPXX_V_B", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_V_B) + .value("ST1_MXIPXX_V_D", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_V_D) + .value("ST1_MXIPXX_V_H", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_V_H) + .value("ST1_MXIPXX_V_Q", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_V_Q) + .value("ST1_MXIPXX_V_S", LIEF::assembly::aarch64::OPCODE::ST1_MXIPXX_V_S) + .value("ST1i16", LIEF::assembly::aarch64::OPCODE::ST1i16) + .value("ST1i16_POST", LIEF::assembly::aarch64::OPCODE::ST1i16_POST) + .value("ST1i32", LIEF::assembly::aarch64::OPCODE::ST1i32) + .value("ST1i32_POST", LIEF::assembly::aarch64::OPCODE::ST1i32_POST) + .value("ST1i64", LIEF::assembly::aarch64::OPCODE::ST1i64) + .value("ST1i64_POST", LIEF::assembly::aarch64::OPCODE::ST1i64_POST) + .value("ST1i8", LIEF::assembly::aarch64::OPCODE::ST1i8) + .value("ST1i8_POST", LIEF::assembly::aarch64::OPCODE::ST1i8_POST) + .value("ST2B", LIEF::assembly::aarch64::OPCODE::ST2B) + .value("ST2B_IMM", LIEF::assembly::aarch64::OPCODE::ST2B_IMM) + .value("ST2D", LIEF::assembly::aarch64::OPCODE::ST2D) + .value("ST2D_IMM", LIEF::assembly::aarch64::OPCODE::ST2D_IMM) + .value("ST2GPostIndex", LIEF::assembly::aarch64::OPCODE::ST2GPostIndex) + .value("ST2GPreIndex", LIEF::assembly::aarch64::OPCODE::ST2GPreIndex) + .value("ST2Gi", LIEF::assembly::aarch64::OPCODE::ST2Gi) + .value("ST2H", LIEF::assembly::aarch64::OPCODE::ST2H) + .value("ST2H_IMM", LIEF::assembly::aarch64::OPCODE::ST2H_IMM) + .value("ST2Q", LIEF::assembly::aarch64::OPCODE::ST2Q) + .value("ST2Q_IMM", LIEF::assembly::aarch64::OPCODE::ST2Q_IMM) + .value("ST2Twov16b", LIEF::assembly::aarch64::OPCODE::ST2Twov16b) + .value("ST2Twov16b_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov16b_POST) + .value("ST2Twov2d", LIEF::assembly::aarch64::OPCODE::ST2Twov2d) + .value("ST2Twov2d_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov2d_POST) + .value("ST2Twov2s", LIEF::assembly::aarch64::OPCODE::ST2Twov2s) + .value("ST2Twov2s_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov2s_POST) + .value("ST2Twov4h", LIEF::assembly::aarch64::OPCODE::ST2Twov4h) + .value("ST2Twov4h_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov4h_POST) + .value("ST2Twov4s", LIEF::assembly::aarch64::OPCODE::ST2Twov4s) + .value("ST2Twov4s_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov4s_POST) + .value("ST2Twov8b", LIEF::assembly::aarch64::OPCODE::ST2Twov8b) + .value("ST2Twov8b_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov8b_POST) + .value("ST2Twov8h", LIEF::assembly::aarch64::OPCODE::ST2Twov8h) + .value("ST2Twov8h_POST", LIEF::assembly::aarch64::OPCODE::ST2Twov8h_POST) + .value("ST2W", LIEF::assembly::aarch64::OPCODE::ST2W) + .value("ST2W_IMM", LIEF::assembly::aarch64::OPCODE::ST2W_IMM) + .value("ST2i16", LIEF::assembly::aarch64::OPCODE::ST2i16) + .value("ST2i16_POST", LIEF::assembly::aarch64::OPCODE::ST2i16_POST) + .value("ST2i32", LIEF::assembly::aarch64::OPCODE::ST2i32) + .value("ST2i32_POST", LIEF::assembly::aarch64::OPCODE::ST2i32_POST) + .value("ST2i64", LIEF::assembly::aarch64::OPCODE::ST2i64) + .value("ST2i64_POST", LIEF::assembly::aarch64::OPCODE::ST2i64_POST) + .value("ST2i8", LIEF::assembly::aarch64::OPCODE::ST2i8) + .value("ST2i8_POST", LIEF::assembly::aarch64::OPCODE::ST2i8_POST) + .value("ST3B", LIEF::assembly::aarch64::OPCODE::ST3B) + .value("ST3B_IMM", LIEF::assembly::aarch64::OPCODE::ST3B_IMM) + .value("ST3D", LIEF::assembly::aarch64::OPCODE::ST3D) + .value("ST3D_IMM", LIEF::assembly::aarch64::OPCODE::ST3D_IMM) + .value("ST3H", LIEF::assembly::aarch64::OPCODE::ST3H) + .value("ST3H_IMM", LIEF::assembly::aarch64::OPCODE::ST3H_IMM) + .value("ST3Q", LIEF::assembly::aarch64::OPCODE::ST3Q) + .value("ST3Q_IMM", LIEF::assembly::aarch64::OPCODE::ST3Q_IMM) + .value("ST3Threev16b", LIEF::assembly::aarch64::OPCODE::ST3Threev16b) + .value("ST3Threev16b_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev16b_POST) + .value("ST3Threev2d", LIEF::assembly::aarch64::OPCODE::ST3Threev2d) + .value("ST3Threev2d_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev2d_POST) + .value("ST3Threev2s", LIEF::assembly::aarch64::OPCODE::ST3Threev2s) + .value("ST3Threev2s_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev2s_POST) + .value("ST3Threev4h", LIEF::assembly::aarch64::OPCODE::ST3Threev4h) + .value("ST3Threev4h_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev4h_POST) + .value("ST3Threev4s", LIEF::assembly::aarch64::OPCODE::ST3Threev4s) + .value("ST3Threev4s_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev4s_POST) + .value("ST3Threev8b", LIEF::assembly::aarch64::OPCODE::ST3Threev8b) + .value("ST3Threev8b_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev8b_POST) + .value("ST3Threev8h", LIEF::assembly::aarch64::OPCODE::ST3Threev8h) + .value("ST3Threev8h_POST", LIEF::assembly::aarch64::OPCODE::ST3Threev8h_POST) + .value("ST3W", LIEF::assembly::aarch64::OPCODE::ST3W) + .value("ST3W_IMM", LIEF::assembly::aarch64::OPCODE::ST3W_IMM) + .value("ST3i16", LIEF::assembly::aarch64::OPCODE::ST3i16) + .value("ST3i16_POST", LIEF::assembly::aarch64::OPCODE::ST3i16_POST) + .value("ST3i32", LIEF::assembly::aarch64::OPCODE::ST3i32) + .value("ST3i32_POST", LIEF::assembly::aarch64::OPCODE::ST3i32_POST) + .value("ST3i64", LIEF::assembly::aarch64::OPCODE::ST3i64) + .value("ST3i64_POST", LIEF::assembly::aarch64::OPCODE::ST3i64_POST) + .value("ST3i8", LIEF::assembly::aarch64::OPCODE::ST3i8) + .value("ST3i8_POST", LIEF::assembly::aarch64::OPCODE::ST3i8_POST) + .value("ST4B", LIEF::assembly::aarch64::OPCODE::ST4B) + .value("ST4B_IMM", LIEF::assembly::aarch64::OPCODE::ST4B_IMM) + .value("ST4D", LIEF::assembly::aarch64::OPCODE::ST4D) + .value("ST4D_IMM", LIEF::assembly::aarch64::OPCODE::ST4D_IMM) + .value("ST4Fourv16b", LIEF::assembly::aarch64::OPCODE::ST4Fourv16b) + .value("ST4Fourv16b_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv16b_POST) + .value("ST4Fourv2d", LIEF::assembly::aarch64::OPCODE::ST4Fourv2d) + .value("ST4Fourv2d_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv2d_POST) + .value("ST4Fourv2s", LIEF::assembly::aarch64::OPCODE::ST4Fourv2s) + .value("ST4Fourv2s_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv2s_POST) + .value("ST4Fourv4h", LIEF::assembly::aarch64::OPCODE::ST4Fourv4h) + .value("ST4Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv4h_POST) + .value("ST4Fourv4s", LIEF::assembly::aarch64::OPCODE::ST4Fourv4s) + .value("ST4Fourv4s_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv4s_POST) + .value("ST4Fourv8b", LIEF::assembly::aarch64::OPCODE::ST4Fourv8b) + .value("ST4Fourv8b_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv8b_POST) + .value("ST4Fourv8h", LIEF::assembly::aarch64::OPCODE::ST4Fourv8h) + .value("ST4Fourv8h_POST", LIEF::assembly::aarch64::OPCODE::ST4Fourv8h_POST) + .value("ST4H", LIEF::assembly::aarch64::OPCODE::ST4H) + .value("ST4H_IMM", LIEF::assembly::aarch64::OPCODE::ST4H_IMM) + .value("ST4Q", LIEF::assembly::aarch64::OPCODE::ST4Q) + .value("ST4Q_IMM", LIEF::assembly::aarch64::OPCODE::ST4Q_IMM) + .value("ST4W", LIEF::assembly::aarch64::OPCODE::ST4W) + .value("ST4W_IMM", LIEF::assembly::aarch64::OPCODE::ST4W_IMM) + .value("ST4i16", LIEF::assembly::aarch64::OPCODE::ST4i16) + .value("ST4i16_POST", LIEF::assembly::aarch64::OPCODE::ST4i16_POST) + .value("ST4i32", LIEF::assembly::aarch64::OPCODE::ST4i32) + .value("ST4i32_POST", LIEF::assembly::aarch64::OPCODE::ST4i32_POST) + .value("ST4i64", LIEF::assembly::aarch64::OPCODE::ST4i64) + .value("ST4i64_POST", LIEF::assembly::aarch64::OPCODE::ST4i64_POST) + .value("ST4i8", LIEF::assembly::aarch64::OPCODE::ST4i8) + .value("ST4i8_POST", LIEF::assembly::aarch64::OPCODE::ST4i8_POST) + .value("ST64B", LIEF::assembly::aarch64::OPCODE::ST64B) + .value("ST64BV", LIEF::assembly::aarch64::OPCODE::ST64BV) + .value("ST64BV0", LIEF::assembly::aarch64::OPCODE::ST64BV0) + .value("STBFADD", LIEF::assembly::aarch64::OPCODE::STBFADD) + .value("STBFADDL", LIEF::assembly::aarch64::OPCODE::STBFADDL) + .value("STBFMAX", LIEF::assembly::aarch64::OPCODE::STBFMAX) + .value("STBFMAXL", LIEF::assembly::aarch64::OPCODE::STBFMAXL) + .value("STBFMAXNM", LIEF::assembly::aarch64::OPCODE::STBFMAXNM) + .value("STBFMAXNML", LIEF::assembly::aarch64::OPCODE::STBFMAXNML) + .value("STBFMIN", LIEF::assembly::aarch64::OPCODE::STBFMIN) + .value("STBFMINL", LIEF::assembly::aarch64::OPCODE::STBFMINL) + .value("STBFMINNM", LIEF::assembly::aarch64::OPCODE::STBFMINNM) + .value("STBFMINNML", LIEF::assembly::aarch64::OPCODE::STBFMINNML) + .value("STCPH", LIEF::assembly::aarch64::OPCODE::STCPH) + .value("STFADDD", LIEF::assembly::aarch64::OPCODE::STFADDD) + .value("STFADDH", LIEF::assembly::aarch64::OPCODE::STFADDH) + .value("STFADDLD", LIEF::assembly::aarch64::OPCODE::STFADDLD) + .value("STFADDLH", LIEF::assembly::aarch64::OPCODE::STFADDLH) + .value("STFADDLS", LIEF::assembly::aarch64::OPCODE::STFADDLS) + .value("STFADDS", LIEF::assembly::aarch64::OPCODE::STFADDS) + .value("STFMAXD", LIEF::assembly::aarch64::OPCODE::STFMAXD) + .value("STFMAXH", LIEF::assembly::aarch64::OPCODE::STFMAXH) + .value("STFMAXLD", LIEF::assembly::aarch64::OPCODE::STFMAXLD) + .value("STFMAXLH", LIEF::assembly::aarch64::OPCODE::STFMAXLH) + .value("STFMAXLS", LIEF::assembly::aarch64::OPCODE::STFMAXLS) + .value("STFMAXNMD", LIEF::assembly::aarch64::OPCODE::STFMAXNMD) + .value("STFMAXNMH", LIEF::assembly::aarch64::OPCODE::STFMAXNMH) + .value("STFMAXNMLD", LIEF::assembly::aarch64::OPCODE::STFMAXNMLD) + .value("STFMAXNMLH", LIEF::assembly::aarch64::OPCODE::STFMAXNMLH) + .value("STFMAXNMLS", LIEF::assembly::aarch64::OPCODE::STFMAXNMLS) + .value("STFMAXNMS", LIEF::assembly::aarch64::OPCODE::STFMAXNMS) + .value("STFMAXS", LIEF::assembly::aarch64::OPCODE::STFMAXS) + .value("STFMIND", LIEF::assembly::aarch64::OPCODE::STFMIND) + .value("STFMINH", LIEF::assembly::aarch64::OPCODE::STFMINH) + .value("STFMINLD", LIEF::assembly::aarch64::OPCODE::STFMINLD) + .value("STFMINLH", LIEF::assembly::aarch64::OPCODE::STFMINLH) + .value("STFMINLS", LIEF::assembly::aarch64::OPCODE::STFMINLS) + .value("STFMINNMD", LIEF::assembly::aarch64::OPCODE::STFMINNMD) + .value("STFMINNMH", LIEF::assembly::aarch64::OPCODE::STFMINNMH) + .value("STFMINNMLD", LIEF::assembly::aarch64::OPCODE::STFMINNMLD) + .value("STFMINNMLH", LIEF::assembly::aarch64::OPCODE::STFMINNMLH) + .value("STFMINNMLS", LIEF::assembly::aarch64::OPCODE::STFMINNMLS) + .value("STFMINNMS", LIEF::assembly::aarch64::OPCODE::STFMINNMS) + .value("STFMINS", LIEF::assembly::aarch64::OPCODE::STFMINS) + .value("STGM", LIEF::assembly::aarch64::OPCODE::STGM) + .value("STGPi", LIEF::assembly::aarch64::OPCODE::STGPi) + .value("STGPostIndex", LIEF::assembly::aarch64::OPCODE::STGPostIndex) + .value("STGPpost", LIEF::assembly::aarch64::OPCODE::STGPpost) + .value("STGPpre", LIEF::assembly::aarch64::OPCODE::STGPpre) + .value("STGPreIndex", LIEF::assembly::aarch64::OPCODE::STGPreIndex) + .value("STGi", LIEF::assembly::aarch64::OPCODE::STGi) + .value("STILPW", LIEF::assembly::aarch64::OPCODE::STILPW) + .value("STILPWpre", LIEF::assembly::aarch64::OPCODE::STILPWpre) + .value("STILPX", LIEF::assembly::aarch64::OPCODE::STILPX) + .value("STILPXpre", LIEF::assembly::aarch64::OPCODE::STILPXpre) + .value("STL1", LIEF::assembly::aarch64::OPCODE::STL1) + .value("STLLRB", LIEF::assembly::aarch64::OPCODE::STLLRB) + .value("STLLRH", LIEF::assembly::aarch64::OPCODE::STLLRH) + .value("STLLRW", LIEF::assembly::aarch64::OPCODE::STLLRW) + .value("STLLRX", LIEF::assembly::aarch64::OPCODE::STLLRX) + .value("STLPi", LIEF::assembly::aarch64::OPCODE::STLPi) + .value("STLRB", LIEF::assembly::aarch64::OPCODE::STLRB) + .value("STLRH", LIEF::assembly::aarch64::OPCODE::STLRH); + opcodes.value("STLRW", LIEF::assembly::aarch64::OPCODE::STLRW) + .value("STLRWpre", LIEF::assembly::aarch64::OPCODE::STLRWpre) + .value("STLRX", LIEF::assembly::aarch64::OPCODE::STLRX) + .value("STLRXpre", LIEF::assembly::aarch64::OPCODE::STLRXpre) + .value("STLTXRW", LIEF::assembly::aarch64::OPCODE::STLTXRW) + .value("STLTXRX", LIEF::assembly::aarch64::OPCODE::STLTXRX) + .value("STLURBi", LIEF::assembly::aarch64::OPCODE::STLURBi) + .value("STLURHi", LIEF::assembly::aarch64::OPCODE::STLURHi) + .value("STLURWi", LIEF::assembly::aarch64::OPCODE::STLURWi) + .value("STLURXi", LIEF::assembly::aarch64::OPCODE::STLURXi) + .value("STLURbi", LIEF::assembly::aarch64::OPCODE::STLURbi) + .value("STLURdi", LIEF::assembly::aarch64::OPCODE::STLURdi) + .value("STLURhi", LIEF::assembly::aarch64::OPCODE::STLURhi) + .value("STLURqi", LIEF::assembly::aarch64::OPCODE::STLURqi) + .value("STLURsi", LIEF::assembly::aarch64::OPCODE::STLURsi) + .value("STLXPW", LIEF::assembly::aarch64::OPCODE::STLXPW) + .value("STLXPX", LIEF::assembly::aarch64::OPCODE::STLXPX) + .value("STLXRB", LIEF::assembly::aarch64::OPCODE::STLXRB) + .value("STLXRH", LIEF::assembly::aarch64::OPCODE::STLXRH) + .value("STLXRW", LIEF::assembly::aarch64::OPCODE::STLXRW) + .value("STLXRX", LIEF::assembly::aarch64::OPCODE::STLXRX) + .value("STMOPA_M2ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::STMOPA_M2ZZZI_BtoS) + .value("STMOPA_M2ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::STMOPA_M2ZZZI_HtoS) + .value("STNPDi", LIEF::assembly::aarch64::OPCODE::STNPDi) + .value("STNPQi", LIEF::assembly::aarch64::OPCODE::STNPQi) + .value("STNPSi", LIEF::assembly::aarch64::OPCODE::STNPSi) + .value("STNPWi", LIEF::assembly::aarch64::OPCODE::STNPWi) + .value("STNPXi", LIEF::assembly::aarch64::OPCODE::STNPXi) + .value("STNT1B_2Z", LIEF::assembly::aarch64::OPCODE::STNT1B_2Z) + .value("STNT1B_2Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1B_2Z_IMM) + .value("STNT1B_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1B_2Z_STRIDED) + .value("STNT1B_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1B_2Z_STRIDED_IMM) + .value("STNT1B_4Z", LIEF::assembly::aarch64::OPCODE::STNT1B_4Z) + .value("STNT1B_4Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1B_4Z_IMM) + .value("STNT1B_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1B_4Z_STRIDED) + .value("STNT1B_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1B_4Z_STRIDED_IMM) + .value("STNT1B_ZRI", LIEF::assembly::aarch64::OPCODE::STNT1B_ZRI) + .value("STNT1B_ZRR", LIEF::assembly::aarch64::OPCODE::STNT1B_ZRR) + .value("STNT1B_ZZR_D", LIEF::assembly::aarch64::OPCODE::STNT1B_ZZR_D) + .value("STNT1B_ZZR_S", LIEF::assembly::aarch64::OPCODE::STNT1B_ZZR_S) + .value("STNT1D_2Z", LIEF::assembly::aarch64::OPCODE::STNT1D_2Z) + .value("STNT1D_2Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1D_2Z_IMM) + .value("STNT1D_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1D_2Z_STRIDED) + .value("STNT1D_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1D_2Z_STRIDED_IMM) + .value("STNT1D_4Z", LIEF::assembly::aarch64::OPCODE::STNT1D_4Z) + .value("STNT1D_4Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1D_4Z_IMM) + .value("STNT1D_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1D_4Z_STRIDED) + .value("STNT1D_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1D_4Z_STRIDED_IMM) + .value("STNT1D_ZRI", LIEF::assembly::aarch64::OPCODE::STNT1D_ZRI) + .value("STNT1D_ZRR", LIEF::assembly::aarch64::OPCODE::STNT1D_ZRR) + .value("STNT1D_ZZR_D", LIEF::assembly::aarch64::OPCODE::STNT1D_ZZR_D) + .value("STNT1H_2Z", LIEF::assembly::aarch64::OPCODE::STNT1H_2Z) + .value("STNT1H_2Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1H_2Z_IMM) + .value("STNT1H_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1H_2Z_STRIDED) + .value("STNT1H_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1H_2Z_STRIDED_IMM) + .value("STNT1H_4Z", LIEF::assembly::aarch64::OPCODE::STNT1H_4Z) + .value("STNT1H_4Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1H_4Z_IMM) + .value("STNT1H_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1H_4Z_STRIDED) + .value("STNT1H_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1H_4Z_STRIDED_IMM) + .value("STNT1H_ZRI", LIEF::assembly::aarch64::OPCODE::STNT1H_ZRI) + .value("STNT1H_ZRR", LIEF::assembly::aarch64::OPCODE::STNT1H_ZRR) + .value("STNT1H_ZZR_D", LIEF::assembly::aarch64::OPCODE::STNT1H_ZZR_D) + .value("STNT1H_ZZR_S", LIEF::assembly::aarch64::OPCODE::STNT1H_ZZR_S) + .value("STNT1W_2Z", LIEF::assembly::aarch64::OPCODE::STNT1W_2Z) + .value("STNT1W_2Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1W_2Z_IMM) + .value("STNT1W_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1W_2Z_STRIDED) + .value("STNT1W_2Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1W_2Z_STRIDED_IMM) + .value("STNT1W_4Z", LIEF::assembly::aarch64::OPCODE::STNT1W_4Z) + .value("STNT1W_4Z_IMM", LIEF::assembly::aarch64::OPCODE::STNT1W_4Z_IMM) + .value("STNT1W_4Z_STRIDED", LIEF::assembly::aarch64::OPCODE::STNT1W_4Z_STRIDED) + .value("STNT1W_4Z_STRIDED_IMM", LIEF::assembly::aarch64::OPCODE::STNT1W_4Z_STRIDED_IMM) + .value("STNT1W_ZRI", LIEF::assembly::aarch64::OPCODE::STNT1W_ZRI) + .value("STNT1W_ZRR", LIEF::assembly::aarch64::OPCODE::STNT1W_ZRR) + .value("STNT1W_ZZR_D", LIEF::assembly::aarch64::OPCODE::STNT1W_ZZR_D) + .value("STNT1W_ZZR_S", LIEF::assembly::aarch64::OPCODE::STNT1W_ZZR_S) + .value("STPDi", LIEF::assembly::aarch64::OPCODE::STPDi) + .value("STPDpost", LIEF::assembly::aarch64::OPCODE::STPDpost) + .value("STPDpre", LIEF::assembly::aarch64::OPCODE::STPDpre) + .value("STPQi", LIEF::assembly::aarch64::OPCODE::STPQi) + .value("STPQpost", LIEF::assembly::aarch64::OPCODE::STPQpost) + .value("STPQpre", LIEF::assembly::aarch64::OPCODE::STPQpre) + .value("STPSi", LIEF::assembly::aarch64::OPCODE::STPSi) + .value("STPSpost", LIEF::assembly::aarch64::OPCODE::STPSpost) + .value("STPSpre", LIEF::assembly::aarch64::OPCODE::STPSpre) + .value("STPWi", LIEF::assembly::aarch64::OPCODE::STPWi) + .value("STPWpost", LIEF::assembly::aarch64::OPCODE::STPWpost) + .value("STPWpre", LIEF::assembly::aarch64::OPCODE::STPWpre) + .value("STPXi", LIEF::assembly::aarch64::OPCODE::STPXi) + .value("STPXpost", LIEF::assembly::aarch64::OPCODE::STPXpost) + .value("STPXpre", LIEF::assembly::aarch64::OPCODE::STPXpre) + .value("STRBBpost", LIEF::assembly::aarch64::OPCODE::STRBBpost) + .value("STRBBpre", LIEF::assembly::aarch64::OPCODE::STRBBpre) + .value("STRBBroW", LIEF::assembly::aarch64::OPCODE::STRBBroW) + .value("STRBBroX", LIEF::assembly::aarch64::OPCODE::STRBBroX) + .value("STRBBui", LIEF::assembly::aarch64::OPCODE::STRBBui) + .value("STRBpost", LIEF::assembly::aarch64::OPCODE::STRBpost) + .value("STRBpre", LIEF::assembly::aarch64::OPCODE::STRBpre) + .value("STRBroW", LIEF::assembly::aarch64::OPCODE::STRBroW) + .value("STRBroX", LIEF::assembly::aarch64::OPCODE::STRBroX) + .value("STRBui", LIEF::assembly::aarch64::OPCODE::STRBui) + .value("STRDpost", LIEF::assembly::aarch64::OPCODE::STRDpost) + .value("STRDpre", LIEF::assembly::aarch64::OPCODE::STRDpre) + .value("STRDroW", LIEF::assembly::aarch64::OPCODE::STRDroW) + .value("STRDroX", LIEF::assembly::aarch64::OPCODE::STRDroX) + .value("STRDui", LIEF::assembly::aarch64::OPCODE::STRDui) + .value("STRHHpost", LIEF::assembly::aarch64::OPCODE::STRHHpost) + .value("STRHHpre", LIEF::assembly::aarch64::OPCODE::STRHHpre) + .value("STRHHroW", LIEF::assembly::aarch64::OPCODE::STRHHroW) + .value("STRHHroX", LIEF::assembly::aarch64::OPCODE::STRHHroX) + .value("STRHHui", LIEF::assembly::aarch64::OPCODE::STRHHui) + .value("STRHpost", LIEF::assembly::aarch64::OPCODE::STRHpost) + .value("STRHpre", LIEF::assembly::aarch64::OPCODE::STRHpre) + .value("STRHroW", LIEF::assembly::aarch64::OPCODE::STRHroW) + .value("STRHroX", LIEF::assembly::aarch64::OPCODE::STRHroX) + .value("STRHui", LIEF::assembly::aarch64::OPCODE::STRHui) + .value("STRQpost", LIEF::assembly::aarch64::OPCODE::STRQpost) + .value("STRQpre", LIEF::assembly::aarch64::OPCODE::STRQpre) + .value("STRQroW", LIEF::assembly::aarch64::OPCODE::STRQroW) + .value("STRQroX", LIEF::assembly::aarch64::OPCODE::STRQroX) + .value("STRQui", LIEF::assembly::aarch64::OPCODE::STRQui) + .value("STRSpost", LIEF::assembly::aarch64::OPCODE::STRSpost) + .value("STRSpre", LIEF::assembly::aarch64::OPCODE::STRSpre) + .value("STRSroW", LIEF::assembly::aarch64::OPCODE::STRSroW) + .value("STRSroX", LIEF::assembly::aarch64::OPCODE::STRSroX) + .value("STRSui", LIEF::assembly::aarch64::OPCODE::STRSui) + .value("STRWpost", LIEF::assembly::aarch64::OPCODE::STRWpost) + .value("STRWpre", LIEF::assembly::aarch64::OPCODE::STRWpre) + .value("STRWroW", LIEF::assembly::aarch64::OPCODE::STRWroW) + .value("STRWroX", LIEF::assembly::aarch64::OPCODE::STRWroX) + .value("STRWui", LIEF::assembly::aarch64::OPCODE::STRWui) + .value("STRXpost", LIEF::assembly::aarch64::OPCODE::STRXpost) + .value("STRXpre", LIEF::assembly::aarch64::OPCODE::STRXpre) + .value("STRXroW", LIEF::assembly::aarch64::OPCODE::STRXroW) + .value("STRXroX", LIEF::assembly::aarch64::OPCODE::STRXroX) + .value("STRXui", LIEF::assembly::aarch64::OPCODE::STRXui) + .value("STR_PXI", LIEF::assembly::aarch64::OPCODE::STR_PXI) + .value("STR_TX", LIEF::assembly::aarch64::OPCODE::STR_TX) + .value("STR_ZA", LIEF::assembly::aarch64::OPCODE::STR_ZA) + .value("STR_ZXI", LIEF::assembly::aarch64::OPCODE::STR_ZXI) + .value("STSHH", LIEF::assembly::aarch64::OPCODE::STSHH) + .value("STTNPQi", LIEF::assembly::aarch64::OPCODE::STTNPQi) + .value("STTNPXi", LIEF::assembly::aarch64::OPCODE::STTNPXi) + .value("STTPQi", LIEF::assembly::aarch64::OPCODE::STTPQi) + .value("STTPQpost", LIEF::assembly::aarch64::OPCODE::STTPQpost) + .value("STTPQpre", LIEF::assembly::aarch64::OPCODE::STTPQpre) + .value("STTPi", LIEF::assembly::aarch64::OPCODE::STTPi) + .value("STTPpost", LIEF::assembly::aarch64::OPCODE::STTPpost) + .value("STTPpre", LIEF::assembly::aarch64::OPCODE::STTPpre) + .value("STTRBi", LIEF::assembly::aarch64::OPCODE::STTRBi) + .value("STTRHi", LIEF::assembly::aarch64::OPCODE::STTRHi) + .value("STTRWi", LIEF::assembly::aarch64::OPCODE::STTRWi) + .value("STTRXi", LIEF::assembly::aarch64::OPCODE::STTRXi) + .value("STTXRWr", LIEF::assembly::aarch64::OPCODE::STTXRWr) + .value("STTXRXr", LIEF::assembly::aarch64::OPCODE::STTXRXr) + .value("STURBBi", LIEF::assembly::aarch64::OPCODE::STURBBi) + .value("STURBi", LIEF::assembly::aarch64::OPCODE::STURBi) + .value("STURDi", LIEF::assembly::aarch64::OPCODE::STURDi) + .value("STURHHi", LIEF::assembly::aarch64::OPCODE::STURHHi) + .value("STURHi", LIEF::assembly::aarch64::OPCODE::STURHi) + .value("STURQi", LIEF::assembly::aarch64::OPCODE::STURQi) + .value("STURSi", LIEF::assembly::aarch64::OPCODE::STURSi) + .value("STURWi", LIEF::assembly::aarch64::OPCODE::STURWi) + .value("STURXi", LIEF::assembly::aarch64::OPCODE::STURXi) + .value("STXPW", LIEF::assembly::aarch64::OPCODE::STXPW) + .value("STXPX", LIEF::assembly::aarch64::OPCODE::STXPX) + .value("STXRB", LIEF::assembly::aarch64::OPCODE::STXRB) + .value("STXRH", LIEF::assembly::aarch64::OPCODE::STXRH) + .value("STXRW", LIEF::assembly::aarch64::OPCODE::STXRW) + .value("STXRX", LIEF::assembly::aarch64::OPCODE::STXRX) + .value("STZ2GPostIndex", LIEF::assembly::aarch64::OPCODE::STZ2GPostIndex) + .value("STZ2GPreIndex", LIEF::assembly::aarch64::OPCODE::STZ2GPreIndex) + .value("STZ2Gi", LIEF::assembly::aarch64::OPCODE::STZ2Gi) + .value("STZGM", LIEF::assembly::aarch64::OPCODE::STZGM) + .value("STZGPostIndex", LIEF::assembly::aarch64::OPCODE::STZGPostIndex) + .value("STZGPreIndex", LIEF::assembly::aarch64::OPCODE::STZGPreIndex) + .value("STZGi", LIEF::assembly::aarch64::OPCODE::STZGi) + .value("SUBG", LIEF::assembly::aarch64::OPCODE::SUBG) + .value("SUBHNB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SUBHNB_ZZZ_B) + .value("SUBHNB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SUBHNB_ZZZ_H) + .value("SUBHNB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SUBHNB_ZZZ_S) + .value("SUBHNT_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SUBHNT_ZZZ_B) + .value("SUBHNT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SUBHNT_ZZZ_H) + .value("SUBHNT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SUBHNT_ZZZ_S) + .value("SUBHNv2i64_v2i32", LIEF::assembly::aarch64::OPCODE::SUBHNv2i64_v2i32) + .value("SUBHNv2i64_v4i32", LIEF::assembly::aarch64::OPCODE::SUBHNv2i64_v4i32) + .value("SUBHNv4i32_v4i16", LIEF::assembly::aarch64::OPCODE::SUBHNv4i32_v4i16) + .value("SUBHNv4i32_v8i16", LIEF::assembly::aarch64::OPCODE::SUBHNv4i32_v8i16) + .value("SUBHNv8i16_v16i8", LIEF::assembly::aarch64::OPCODE::SUBHNv8i16_v16i8) + .value("SUBHNv8i16_v8i8", LIEF::assembly::aarch64::OPCODE::SUBHNv8i16_v8i8) + .value("SUBP", LIEF::assembly::aarch64::OPCODE::SUBP) + .value("SUBPS", LIEF::assembly::aarch64::OPCODE::SUBPS) + .value("SUBPT_shift", LIEF::assembly::aarch64::OPCODE::SUBPT_shift) + .value("SUBP_ZPmZZ_B", LIEF::assembly::aarch64::OPCODE::SUBP_ZPmZZ_B) + .value("SUBP_ZPmZZ_D", LIEF::assembly::aarch64::OPCODE::SUBP_ZPmZZ_D) + .value("SUBP_ZPmZZ_H", LIEF::assembly::aarch64::OPCODE::SUBP_ZPmZZ_H) + .value("SUBP_ZPmZZ_S", LIEF::assembly::aarch64::OPCODE::SUBP_ZPmZZ_S) + .value("SUBR_ZI_B", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_B) + .value("SUBR_ZI_D", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_D) + .value("SUBR_ZI_H", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_H) + .value("SUBR_ZI_S", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_S) + .value("SUBR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SUBR_ZPmZ_B) + .value("SUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SUBR_ZPmZ_D) + .value("SUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SUBR_ZPmZ_H) + .value("SUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUBR_ZPmZ_S) + .value("SUBSWri", LIEF::assembly::aarch64::OPCODE::SUBSWri) + .value("SUBSWrs", LIEF::assembly::aarch64::OPCODE::SUBSWrs) + .value("SUBSWrx", LIEF::assembly::aarch64::OPCODE::SUBSWrx) + .value("SUBSXri", LIEF::assembly::aarch64::OPCODE::SUBSXri) + .value("SUBSXrs", LIEF::assembly::aarch64::OPCODE::SUBSXrs) + .value("SUBSXrx", LIEF::assembly::aarch64::OPCODE::SUBSXrx) + .value("SUBSXrx64", LIEF::assembly::aarch64::OPCODE::SUBSXrx64) + .value("SUBWri", LIEF::assembly::aarch64::OPCODE::SUBWri) + .value("SUBWrs", LIEF::assembly::aarch64::OPCODE::SUBWrs) + .value("SUBWrx", LIEF::assembly::aarch64::OPCODE::SUBWrx) + .value("SUBXri", LIEF::assembly::aarch64::OPCODE::SUBXri) + .value("SUBXrs", LIEF::assembly::aarch64::OPCODE::SUBXrs) + .value("SUBXrx", LIEF::assembly::aarch64::OPCODE::SUBXrx) + .value("SUBXrx64", LIEF::assembly::aarch64::OPCODE::SUBXrx64) + .value("SUB_VG2_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z2Z_D) + .value("SUB_VG2_M2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z2Z_S) + .value("SUB_VG2_M2ZZ_D", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2ZZ_D) + .value("SUB_VG2_M2ZZ_S", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2ZZ_S) + .value("SUB_VG2_M2Z_D", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z_D) + .value("SUB_VG2_M2Z_S", LIEF::assembly::aarch64::OPCODE::SUB_VG2_M2Z_S) + .value("SUB_VG4_M4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z4Z_D) + .value("SUB_VG4_M4Z4Z_S", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z4Z_S) + .value("SUB_VG4_M4ZZ_D", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4ZZ_D) + .value("SUB_VG4_M4ZZ_S", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4ZZ_S) + .value("SUB_VG4_M4Z_D", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_D) + .value("SUB_VG4_M4Z_S", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_S) + .value("SUB_ZI_B", LIEF::assembly::aarch64::OPCODE::SUB_ZI_B) + .value("SUB_ZI_D", LIEF::assembly::aarch64::OPCODE::SUB_ZI_D) + .value("SUB_ZI_H", LIEF::assembly::aarch64::OPCODE::SUB_ZI_H) + .value("SUB_ZI_S", LIEF::assembly::aarch64::OPCODE::SUB_ZI_S) + .value("SUB_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_B) + .value("SUB_ZPmZ_CPA", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_CPA) + .value("SUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_D) + .value("SUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_H) + .value("SUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_S) + .value("SUB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_B) + .value("SUB_ZZZ_CPA", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_CPA) + .value("SUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_D) + .value("SUB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_H) + .value("SUB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_S) + .value("SUBv16i8", LIEF::assembly::aarch64::OPCODE::SUBv16i8) + .value("SUBv1i64", LIEF::assembly::aarch64::OPCODE::SUBv1i64) + .value("SUBv2i32", LIEF::assembly::aarch64::OPCODE::SUBv2i32) + .value("SUBv2i64", LIEF::assembly::aarch64::OPCODE::SUBv2i64) + .value("SUBv4i16", LIEF::assembly::aarch64::OPCODE::SUBv4i16) + .value("SUBv4i32", LIEF::assembly::aarch64::OPCODE::SUBv4i32) + .value("SUBv8i16", LIEF::assembly::aarch64::OPCODE::SUBv8i16) + .value("SUBv8i8", LIEF::assembly::aarch64::OPCODE::SUBv8i8) + .value("SUDOT_VG2_M2ZZI_BToS", LIEF::assembly::aarch64::OPCODE::SUDOT_VG2_M2ZZI_BToS) + .value("SUDOT_VG2_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUDOT_VG2_M2ZZ_BToS) + .value("SUDOT_VG4_M4ZZI_BToS", LIEF::assembly::aarch64::OPCODE::SUDOT_VG4_M4ZZI_BToS) + .value("SUDOT_VG4_M4ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUDOT_VG4_M4ZZ_BToS) + .value("SUDOT_ZZZI", LIEF::assembly::aarch64::OPCODE::SUDOT_ZZZI) + .value("SUDOTlanev16i8", LIEF::assembly::aarch64::OPCODE::SUDOTlanev16i8) + .value("SUDOTlanev8i8", LIEF::assembly::aarch64::OPCODE::SUDOTlanev8i8) + .value("SUMLALL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SUMLALL_MZZI_BtoS) + .value("SUMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG2_M2ZZI_BtoS) + .value("SUMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG2_M2ZZ_BtoS) + .value("SUMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG4_M4ZZI_BtoS) + .value("SUMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::SUMLALL_VG4_M4ZZ_BtoS) + .value("SUMOP4A_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2Z2Z_BToS) + .value("SUMOP4A_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2Z2Z_HtoD) + .value("SUMOP4A_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2ZZ_BToS) + .value("SUMOP4A_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4A_M2ZZ_HtoD) + .value("SUMOP4A_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZ2Z_BToS) + .value("SUMOP4A_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZ2Z_HtoD) + .value("SUMOP4A_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZZ_BToS) + .value("SUMOP4A_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4A_MZZ_HtoD) + .value("SUMOP4S_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2Z2Z_BToS) + .value("SUMOP4S_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2Z2Z_HtoD) + .value("SUMOP4S_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2ZZ_BToS) + .value("SUMOP4S_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4S_M2ZZ_HtoD) + .value("SUMOP4S_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZ2Z_BToS) + .value("SUMOP4S_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZ2Z_HtoD) + .value("SUMOP4S_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZZ_BToS) + .value("SUMOP4S_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::SUMOP4S_MZZ_HtoD) + .value("SUMOPA_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::SUMOPA_MPPZZ_D) + .value("SUMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::SUMOPA_MPPZZ_S) + .value("SUMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::SUMOPS_MPPZZ_D) + .value("SUMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::SUMOPS_MPPZZ_S) + .value("SUNPKHI_ZZ_D", LIEF::assembly::aarch64::OPCODE::SUNPKHI_ZZ_D) + .value("SUNPKHI_ZZ_H", LIEF::assembly::aarch64::OPCODE::SUNPKHI_ZZ_H) + .value("SUNPKHI_ZZ_S", LIEF::assembly::aarch64::OPCODE::SUNPKHI_ZZ_S) + .value("SUNPKLO_ZZ_D", LIEF::assembly::aarch64::OPCODE::SUNPKLO_ZZ_D) + .value("SUNPKLO_ZZ_H", LIEF::assembly::aarch64::OPCODE::SUNPKLO_ZZ_H) + .value("SUNPKLO_ZZ_S", LIEF::assembly::aarch64::OPCODE::SUNPKLO_ZZ_S) + .value("SUNPK_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::SUNPK_VG2_2ZZ_D) + .value("SUNPK_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::SUNPK_VG2_2ZZ_H) + .value("SUNPK_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::SUNPK_VG2_2ZZ_S) + .value("SUNPK_VG4_4Z2Z_D", LIEF::assembly::aarch64::OPCODE::SUNPK_VG4_4Z2Z_D) + .value("SUNPK_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::SUNPK_VG4_4Z2Z_H) + .value("SUNPK_VG4_4Z2Z_S", LIEF::assembly::aarch64::OPCODE::SUNPK_VG4_4Z2Z_S) + .value("SUQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_B) + .value("SUQADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_D) + .value("SUQADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_H) + .value("SUQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_S); + opcodes.value("SUQADDv16i8", LIEF::assembly::aarch64::OPCODE::SUQADDv16i8) + .value("SUQADDv1i16", LIEF::assembly::aarch64::OPCODE::SUQADDv1i16) + .value("SUQADDv1i32", LIEF::assembly::aarch64::OPCODE::SUQADDv1i32) + .value("SUQADDv1i64", LIEF::assembly::aarch64::OPCODE::SUQADDv1i64) + .value("SUQADDv1i8", LIEF::assembly::aarch64::OPCODE::SUQADDv1i8) + .value("SUQADDv2i32", LIEF::assembly::aarch64::OPCODE::SUQADDv2i32) + .value("SUQADDv2i64", LIEF::assembly::aarch64::OPCODE::SUQADDv2i64) + .value("SUQADDv4i16", LIEF::assembly::aarch64::OPCODE::SUQADDv4i16) + .value("SUQADDv4i32", LIEF::assembly::aarch64::OPCODE::SUQADDv4i32) + .value("SUQADDv8i16", LIEF::assembly::aarch64::OPCODE::SUQADDv8i16) + .value("SUQADDv8i8", LIEF::assembly::aarch64::OPCODE::SUQADDv8i8) + .value("SUTMOPA_M2ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SUTMOPA_M2ZZZI_BtoS) + .value("SUVDOT_VG4_M4ZZI_BToS", LIEF::assembly::aarch64::OPCODE::SUVDOT_VG4_M4ZZI_BToS) + .value("SVC", LIEF::assembly::aarch64::OPCODE::SVC) + .value("SVDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::SVDOT_VG2_M2ZZI_HtoS) + .value("SVDOT_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::SVDOT_VG4_M4ZZI_BtoS) + .value("SVDOT_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::SVDOT_VG4_M4ZZI_HtoD) + .value("SWPAB", LIEF::assembly::aarch64::OPCODE::SWPAB) + .value("SWPAH", LIEF::assembly::aarch64::OPCODE::SWPAH) + .value("SWPALB", LIEF::assembly::aarch64::OPCODE::SWPALB) + .value("SWPALH", LIEF::assembly::aarch64::OPCODE::SWPALH) + .value("SWPALW", LIEF::assembly::aarch64::OPCODE::SWPALW) + .value("SWPALX", LIEF::assembly::aarch64::OPCODE::SWPALX) + .value("SWPAW", LIEF::assembly::aarch64::OPCODE::SWPAW) + .value("SWPAX", LIEF::assembly::aarch64::OPCODE::SWPAX) + .value("SWPB", LIEF::assembly::aarch64::OPCODE::SWPB) + .value("SWPH", LIEF::assembly::aarch64::OPCODE::SWPH) + .value("SWPLB", LIEF::assembly::aarch64::OPCODE::SWPLB) + .value("SWPLH", LIEF::assembly::aarch64::OPCODE::SWPLH) + .value("SWPLW", LIEF::assembly::aarch64::OPCODE::SWPLW) + .value("SWPLX", LIEF::assembly::aarch64::OPCODE::SWPLX) + .value("SWPP", LIEF::assembly::aarch64::OPCODE::SWPP) + .value("SWPPA", LIEF::assembly::aarch64::OPCODE::SWPPA) + .value("SWPPAL", LIEF::assembly::aarch64::OPCODE::SWPPAL) + .value("SWPPL", LIEF::assembly::aarch64::OPCODE::SWPPL) + .value("SWPTALW", LIEF::assembly::aarch64::OPCODE::SWPTALW) + .value("SWPTALX", LIEF::assembly::aarch64::OPCODE::SWPTALX) + .value("SWPTAW", LIEF::assembly::aarch64::OPCODE::SWPTAW) + .value("SWPTAX", LIEF::assembly::aarch64::OPCODE::SWPTAX) + .value("SWPTLW", LIEF::assembly::aarch64::OPCODE::SWPTLW) + .value("SWPTLX", LIEF::assembly::aarch64::OPCODE::SWPTLX) + .value("SWPTW", LIEF::assembly::aarch64::OPCODE::SWPTW) + .value("SWPTX", LIEF::assembly::aarch64::OPCODE::SWPTX) + .value("SWPW", LIEF::assembly::aarch64::OPCODE::SWPW) + .value("SWPX", LIEF::assembly::aarch64::OPCODE::SWPX) + .value("SXTB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_D) + .value("SXTB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_H) + .value("SXTB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SXTB_ZPmZ_S) + .value("SXTB_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::SXTB_ZPzZ_D) + .value("SXTB_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::SXTB_ZPzZ_H) + .value("SXTB_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::SXTB_ZPzZ_S) + .value("SXTH_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SXTH_ZPmZ_D) + .value("SXTH_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SXTH_ZPmZ_S) + .value("SXTH_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::SXTH_ZPzZ_D) + .value("SXTH_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::SXTH_ZPzZ_S) + .value("SXTW_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SXTW_ZPmZ_D) + .value("SXTW_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::SXTW_ZPzZ_D) + .value("SYSLxt", LIEF::assembly::aarch64::OPCODE::SYSLxt) + .value("SYSPxt", LIEF::assembly::aarch64::OPCODE::SYSPxt) + .value("SYSPxt_XZR", LIEF::assembly::aarch64::OPCODE::SYSPxt_XZR) + .value("SYSxt", LIEF::assembly::aarch64::OPCODE::SYSxt) + .value("TBLQ_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TBLQ_ZZZ_B) + .value("TBLQ_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TBLQ_ZZZ_D) + .value("TBLQ_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TBLQ_ZZZ_H) + .value("TBLQ_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TBLQ_ZZZ_S) + .value("TBL_ZZZZ_B", LIEF::assembly::aarch64::OPCODE::TBL_ZZZZ_B) + .value("TBL_ZZZZ_D", LIEF::assembly::aarch64::OPCODE::TBL_ZZZZ_D) + .value("TBL_ZZZZ_H", LIEF::assembly::aarch64::OPCODE::TBL_ZZZZ_H) + .value("TBL_ZZZZ_S", LIEF::assembly::aarch64::OPCODE::TBL_ZZZZ_S) + .value("TBL_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TBL_ZZZ_B) + .value("TBL_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TBL_ZZZ_D) + .value("TBL_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TBL_ZZZ_H) + .value("TBL_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TBL_ZZZ_S) + .value("TBLv16i8Four", LIEF::assembly::aarch64::OPCODE::TBLv16i8Four) + .value("TBLv16i8One", LIEF::assembly::aarch64::OPCODE::TBLv16i8One) + .value("TBLv16i8Three", LIEF::assembly::aarch64::OPCODE::TBLv16i8Three) + .value("TBLv16i8Two", LIEF::assembly::aarch64::OPCODE::TBLv16i8Two) + .value("TBLv8i8Four", LIEF::assembly::aarch64::OPCODE::TBLv8i8Four) + .value("TBLv8i8One", LIEF::assembly::aarch64::OPCODE::TBLv8i8One) + .value("TBLv8i8Three", LIEF::assembly::aarch64::OPCODE::TBLv8i8Three) + .value("TBLv8i8Two", LIEF::assembly::aarch64::OPCODE::TBLv8i8Two) + .value("TBNZW", LIEF::assembly::aarch64::OPCODE::TBNZW) + .value("TBNZX", LIEF::assembly::aarch64::OPCODE::TBNZX) + .value("TBXQ_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TBXQ_ZZZ_B) + .value("TBXQ_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TBXQ_ZZZ_D) + .value("TBXQ_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TBXQ_ZZZ_H) + .value("TBXQ_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TBXQ_ZZZ_S) + .value("TBX_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TBX_ZZZ_B) + .value("TBX_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TBX_ZZZ_D) + .value("TBX_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TBX_ZZZ_H) + .value("TBX_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TBX_ZZZ_S) + .value("TBXv16i8Four", LIEF::assembly::aarch64::OPCODE::TBXv16i8Four) + .value("TBXv16i8One", LIEF::assembly::aarch64::OPCODE::TBXv16i8One) + .value("TBXv16i8Three", LIEF::assembly::aarch64::OPCODE::TBXv16i8Three) + .value("TBXv16i8Two", LIEF::assembly::aarch64::OPCODE::TBXv16i8Two) + .value("TBXv8i8Four", LIEF::assembly::aarch64::OPCODE::TBXv8i8Four) + .value("TBXv8i8One", LIEF::assembly::aarch64::OPCODE::TBXv8i8One) + .value("TBXv8i8Three", LIEF::assembly::aarch64::OPCODE::TBXv8i8Three) + .value("TBXv8i8Two", LIEF::assembly::aarch64::OPCODE::TBXv8i8Two) + .value("TBZW", LIEF::assembly::aarch64::OPCODE::TBZW) + .value("TBZX", LIEF::assembly::aarch64::OPCODE::TBZX) + .value("TCHANGEBri", LIEF::assembly::aarch64::OPCODE::TCHANGEBri) + .value("TCHANGEBrr", LIEF::assembly::aarch64::OPCODE::TCHANGEBrr) + .value("TCHANGEFri", LIEF::assembly::aarch64::OPCODE::TCHANGEFri) + .value("TCHANGEFrr", LIEF::assembly::aarch64::OPCODE::TCHANGEFrr) + .value("TENTER", LIEF::assembly::aarch64::OPCODE::TENTER) + .value("TEXIT", LIEF::assembly::aarch64::OPCODE::TEXIT) + .value("TRCIT", LIEF::assembly::aarch64::OPCODE::TRCIT) + .value("TRN1_PPP_B", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_B) + .value("TRN1_PPP_D", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_D) + .value("TRN1_PPP_H", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_H) + .value("TRN1_PPP_S", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_S) + .value("TRN1_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TRN1_ZZZ_B) + .value("TRN1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TRN1_ZZZ_D) + .value("TRN1_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TRN1_ZZZ_H) + .value("TRN1_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::TRN1_ZZZ_Q) + .value("TRN1_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TRN1_ZZZ_S) + .value("TRN1v16i8", LIEF::assembly::aarch64::OPCODE::TRN1v16i8) + .value("TRN1v2i32", LIEF::assembly::aarch64::OPCODE::TRN1v2i32) + .value("TRN1v2i64", LIEF::assembly::aarch64::OPCODE::TRN1v2i64) + .value("TRN1v4i16", LIEF::assembly::aarch64::OPCODE::TRN1v4i16) + .value("TRN1v4i32", LIEF::assembly::aarch64::OPCODE::TRN1v4i32) + .value("TRN1v8i16", LIEF::assembly::aarch64::OPCODE::TRN1v8i16) + .value("TRN1v8i8", LIEF::assembly::aarch64::OPCODE::TRN1v8i8) + .value("TRN2_PPP_B", LIEF::assembly::aarch64::OPCODE::TRN2_PPP_B) + .value("TRN2_PPP_D", LIEF::assembly::aarch64::OPCODE::TRN2_PPP_D) + .value("TRN2_PPP_H", LIEF::assembly::aarch64::OPCODE::TRN2_PPP_H) + .value("TRN2_PPP_S", LIEF::assembly::aarch64::OPCODE::TRN2_PPP_S) + .value("TRN2_ZZZ_B", LIEF::assembly::aarch64::OPCODE::TRN2_ZZZ_B) + .value("TRN2_ZZZ_D", LIEF::assembly::aarch64::OPCODE::TRN2_ZZZ_D) + .value("TRN2_ZZZ_H", LIEF::assembly::aarch64::OPCODE::TRN2_ZZZ_H) + .value("TRN2_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::TRN2_ZZZ_Q) + .value("TRN2_ZZZ_S", LIEF::assembly::aarch64::OPCODE::TRN2_ZZZ_S) + .value("TRN2v16i8", LIEF::assembly::aarch64::OPCODE::TRN2v16i8) + .value("TRN2v2i32", LIEF::assembly::aarch64::OPCODE::TRN2v2i32) + .value("TRN2v2i64", LIEF::assembly::aarch64::OPCODE::TRN2v2i64) + .value("TRN2v4i16", LIEF::assembly::aarch64::OPCODE::TRN2v4i16) + .value("TRN2v4i32", LIEF::assembly::aarch64::OPCODE::TRN2v4i32) + .value("TRN2v8i16", LIEF::assembly::aarch64::OPCODE::TRN2v8i16) + .value("TRN2v8i8", LIEF::assembly::aarch64::OPCODE::TRN2v8i8) + .value("TSB", LIEF::assembly::aarch64::OPCODE::TSB) + .value("UABALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_D) + .value("UABALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_H) + .value("UABALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_S) + .value("UABALT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABALT_ZZZ_D) + .value("UABALT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABALT_ZZZ_H) + .value("UABALT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABALT_ZZZ_S) + .value("UABAL_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::UABAL_ZZZ_BtoH) + .value("UABAL_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UABAL_ZZZ_HtoS) + .value("UABAL_ZZZ_StoD", LIEF::assembly::aarch64::OPCODE::UABAL_ZZZ_StoD) + .value("UABALv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UABALv16i8_v8i16) + .value("UABALv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UABALv2i32_v2i64) + .value("UABALv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UABALv4i16_v4i32) + .value("UABALv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UABALv4i32_v2i64) + .value("UABALv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UABALv8i16_v4i32) + .value("UABALv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UABALv8i8_v8i16) + .value("UABA_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UABA_ZZZ_B) + .value("UABA_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABA_ZZZ_D) + .value("UABA_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABA_ZZZ_H) + .value("UABA_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABA_ZZZ_S) + .value("UABAv16i8", LIEF::assembly::aarch64::OPCODE::UABAv16i8) + .value("UABAv2i32", LIEF::assembly::aarch64::OPCODE::UABAv2i32) + .value("UABAv4i16", LIEF::assembly::aarch64::OPCODE::UABAv4i16) + .value("UABAv4i32", LIEF::assembly::aarch64::OPCODE::UABAv4i32) + .value("UABAv8i16", LIEF::assembly::aarch64::OPCODE::UABAv8i16) + .value("UABAv8i8", LIEF::assembly::aarch64::OPCODE::UABAv8i8) + .value("UABDLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABDLB_ZZZ_D) + .value("UABDLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABDLB_ZZZ_H) + .value("UABDLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABDLB_ZZZ_S) + .value("UABDLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABDLT_ZZZ_D) + .value("UABDLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABDLT_ZZZ_H) + .value("UABDLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABDLT_ZZZ_S) + .value("UABDLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UABDLv16i8_v8i16) + .value("UABDLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UABDLv2i32_v2i64) + .value("UABDLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UABDLv4i16_v4i32) + .value("UABDLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UABDLv4i32_v2i64) + .value("UABDLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UABDLv8i16_v4i32) + .value("UABDLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UABDLv8i8_v8i16) + .value("UABD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UABD_ZPmZ_B) + .value("UABD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UABD_ZPmZ_D) + .value("UABD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UABD_ZPmZ_H) + .value("UABD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UABD_ZPmZ_S) + .value("UABDv16i8", LIEF::assembly::aarch64::OPCODE::UABDv16i8) + .value("UABDv2i32", LIEF::assembly::aarch64::OPCODE::UABDv2i32) + .value("UABDv4i16", LIEF::assembly::aarch64::OPCODE::UABDv4i16) + .value("UABDv4i32", LIEF::assembly::aarch64::OPCODE::UABDv4i32) + .value("UABDv8i16", LIEF::assembly::aarch64::OPCODE::UABDv8i16) + .value("UABDv8i8", LIEF::assembly::aarch64::OPCODE::UABDv8i8) + .value("UADALP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UADALP_ZPmZ_D) + .value("UADALP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UADALP_ZPmZ_H) + .value("UADALP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UADALP_ZPmZ_S) + .value("UADALPv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADALPv16i8_v8i16) + .value("UADALPv2i32_v1i64", LIEF::assembly::aarch64::OPCODE::UADALPv2i32_v1i64) + .value("UADALPv4i16_v2i32", LIEF::assembly::aarch64::OPCODE::UADALPv4i16_v2i32) + .value("UADALPv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADALPv4i32_v2i64) + .value("UADALPv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADALPv8i16_v4i32) + .value("UADALPv8i8_v4i16", LIEF::assembly::aarch64::OPCODE::UADALPv8i8_v4i16) + .value("UADDLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UADDLB_ZZZ_D) + .value("UADDLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UADDLB_ZZZ_H) + .value("UADDLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UADDLB_ZZZ_S) + .value("UADDLPv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADDLPv16i8_v8i16) + .value("UADDLPv2i32_v1i64", LIEF::assembly::aarch64::OPCODE::UADDLPv2i32_v1i64) + .value("UADDLPv4i16_v2i32", LIEF::assembly::aarch64::OPCODE::UADDLPv4i16_v2i32) + .value("UADDLPv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADDLPv4i32_v2i64) + .value("UADDLPv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADDLPv8i16_v4i32) + .value("UADDLPv8i8_v4i16", LIEF::assembly::aarch64::OPCODE::UADDLPv8i8_v4i16) + .value("UADDLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UADDLT_ZZZ_D) + .value("UADDLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UADDLT_ZZZ_H) + .value("UADDLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UADDLT_ZZZ_S) + .value("UADDLVv16i8v", LIEF::assembly::aarch64::OPCODE::UADDLVv16i8v) + .value("UADDLVv4i16v", LIEF::assembly::aarch64::OPCODE::UADDLVv4i16v) + .value("UADDLVv4i32v", LIEF::assembly::aarch64::OPCODE::UADDLVv4i32v) + .value("UADDLVv8i16v", LIEF::assembly::aarch64::OPCODE::UADDLVv8i16v) + .value("UADDLVv8i8v", LIEF::assembly::aarch64::OPCODE::UADDLVv8i8v) + .value("UADDLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADDLv16i8_v8i16) + .value("UADDLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADDLv2i32_v2i64) + .value("UADDLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADDLv4i16_v4i32) + .value("UADDLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADDLv4i32_v2i64) + .value("UADDLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADDLv8i16_v4i32) + .value("UADDLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADDLv8i8_v8i16) + .value("UADDV_VPZ_B", LIEF::assembly::aarch64::OPCODE::UADDV_VPZ_B) + .value("UADDV_VPZ_D", LIEF::assembly::aarch64::OPCODE::UADDV_VPZ_D) + .value("UADDV_VPZ_H", LIEF::assembly::aarch64::OPCODE::UADDV_VPZ_H) + .value("UADDV_VPZ_S", LIEF::assembly::aarch64::OPCODE::UADDV_VPZ_S) + .value("UADDWB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UADDWB_ZZZ_D) + .value("UADDWB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UADDWB_ZZZ_H) + .value("UADDWB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UADDWB_ZZZ_S) + .value("UADDWT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UADDWT_ZZZ_D) + .value("UADDWT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UADDWT_ZZZ_H) + .value("UADDWT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UADDWT_ZZZ_S) + .value("UADDWv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADDWv16i8_v8i16) + .value("UADDWv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADDWv2i32_v2i64) + .value("UADDWv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADDWv4i16_v4i32) + .value("UADDWv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UADDWv4i32_v2i64) + .value("UADDWv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UADDWv8i16_v4i32) + .value("UADDWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UADDWv8i8_v8i16) + .value("UBFMWri", LIEF::assembly::aarch64::OPCODE::UBFMWri) + .value("UBFMXri", LIEF::assembly::aarch64::OPCODE::UBFMXri) + .value("UCLAMP_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_B) + .value("UCLAMP_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_D) + .value("UCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_H) + .value("UCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_S) + .value("UCLAMP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_B) + .value("UCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_D) + .value("UCLAMP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_H) + .value("UCLAMP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_S) + .value("UCLAMP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_ZZZ_B) + .value("UCLAMP_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_ZZZ_D) + .value("UCLAMP_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UCLAMP_ZZZ_H) + .value("UCLAMP_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UCLAMP_ZZZ_S) + .value("UCVTFDSr", LIEF::assembly::aarch64::OPCODE::UCVTFDSr) + .value("UCVTFHDr", LIEF::assembly::aarch64::OPCODE::UCVTFHDr) + .value("UCVTFHSr", LIEF::assembly::aarch64::OPCODE::UCVTFHSr) + .value("UCVTFLT_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::UCVTFLT_ZZ_BtoH) + .value("UCVTFLT_ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UCVTFLT_ZZ_HtoS) + .value("UCVTFLT_ZZ_StoD", LIEF::assembly::aarch64::OPCODE::UCVTFLT_ZZ_StoD) + .value("UCVTFSDr", LIEF::assembly::aarch64::OPCODE::UCVTFSDr) + .value("UCVTFSWDri", LIEF::assembly::aarch64::OPCODE::UCVTFSWDri) + .value("UCVTFSWHri", LIEF::assembly::aarch64::OPCODE::UCVTFSWHri) + .value("UCVTFSWSri", LIEF::assembly::aarch64::OPCODE::UCVTFSWSri) + .value("UCVTFSXDri", LIEF::assembly::aarch64::OPCODE::UCVTFSXDri) + .value("UCVTFSXHri", LIEF::assembly::aarch64::OPCODE::UCVTFSXHri) + .value("UCVTFSXSri", LIEF::assembly::aarch64::OPCODE::UCVTFSXSri) + .value("UCVTFUWDri", LIEF::assembly::aarch64::OPCODE::UCVTFUWDri) + .value("UCVTFUWHri", LIEF::assembly::aarch64::OPCODE::UCVTFUWHri) + .value("UCVTFUWSri", LIEF::assembly::aarch64::OPCODE::UCVTFUWSri) + .value("UCVTFUXDri", LIEF::assembly::aarch64::OPCODE::UCVTFUXDri) + .value("UCVTFUXHri", LIEF::assembly::aarch64::OPCODE::UCVTFUXHri) + .value("UCVTFUXSri", LIEF::assembly::aarch64::OPCODE::UCVTFUXSri) + .value("UCVTF_2Z2Z_StoS", LIEF::assembly::aarch64::OPCODE::UCVTF_2Z2Z_StoS) + .value("UCVTF_4Z4Z_StoS", LIEF::assembly::aarch64::OPCODE::UCVTF_4Z4Z_StoS) + .value("UCVTF_ZPmZ_DtoD", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoD) + .value("UCVTF_ZPmZ_DtoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoH) + .value("UCVTF_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_DtoS) + .value("UCVTF_ZPmZ_HtoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_HtoH) + .value("UCVTF_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoD) + .value("UCVTF_ZPmZ_StoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoH) + .value("UCVTF_ZPmZ_StoS", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPmZ_StoS) + .value("UCVTF_ZPzZ_DtoD", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_DtoD) + .value("UCVTF_ZPzZ_DtoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_DtoH) + .value("UCVTF_ZPzZ_DtoS", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_DtoS) + .value("UCVTF_ZPzZ_HtoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_HtoH) + .value("UCVTF_ZPzZ_StoD", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_StoD) + .value("UCVTF_ZPzZ_StoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_StoH) + .value("UCVTF_ZPzZ_StoS", LIEF::assembly::aarch64::OPCODE::UCVTF_ZPzZ_StoS) + .value("UCVTF_ZZ_BtoH", LIEF::assembly::aarch64::OPCODE::UCVTF_ZZ_BtoH) + .value("UCVTF_ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UCVTF_ZZ_HtoS) + .value("UCVTF_ZZ_StoD", LIEF::assembly::aarch64::OPCODE::UCVTF_ZZ_StoD) + .value("UCVTFd", LIEF::assembly::aarch64::OPCODE::UCVTFd) + .value("UCVTFh", LIEF::assembly::aarch64::OPCODE::UCVTFh) + .value("UCVTFs", LIEF::assembly::aarch64::OPCODE::UCVTFs) + .value("UCVTFv1i16", LIEF::assembly::aarch64::OPCODE::UCVTFv1i16) + .value("UCVTFv1i32", LIEF::assembly::aarch64::OPCODE::UCVTFv1i32) + .value("UCVTFv1i64", LIEF::assembly::aarch64::OPCODE::UCVTFv1i64) + .value("UCVTFv2f32", LIEF::assembly::aarch64::OPCODE::UCVTFv2f32) + .value("UCVTFv2f64", LIEF::assembly::aarch64::OPCODE::UCVTFv2f64) + .value("UCVTFv2i32_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv2i32_shift) + .value("UCVTFv2i64_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv2i64_shift) + .value("UCVTFv4f16", LIEF::assembly::aarch64::OPCODE::UCVTFv4f16) + .value("UCVTFv4f32", LIEF::assembly::aarch64::OPCODE::UCVTFv4f32); + opcodes.value("UCVTFv4i16_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv4i16_shift) + .value("UCVTFv4i32_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv4i32_shift) + .value("UCVTFv8f16", LIEF::assembly::aarch64::OPCODE::UCVTFv8f16) + .value("UCVTFv8i16_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv8i16_shift) + .value("UDF", LIEF::assembly::aarch64::OPCODE::UDF) + .value("UDIVR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UDIVR_ZPmZ_D) + .value("UDIVR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UDIVR_ZPmZ_S) + .value("UDIVWr", LIEF::assembly::aarch64::OPCODE::UDIVWr) + .value("UDIVXr", LIEF::assembly::aarch64::OPCODE::UDIVXr) + .value("UDIV_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UDIV_ZPmZ_D) + .value("UDIV_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UDIV_ZPmZ_S) + .value("UDOT_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_BtoS) + .value("UDOT_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoD) + .value("UDOT_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoS) + .value("UDOT_VG2_M2ZZI_BToS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_BToS) + .value("UDOT_VG2_M2ZZI_HToS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HToS) + .value("UDOT_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HtoD) + .value("UDOT_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_BtoS) + .value("UDOT_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_HtoD) + .value("UDOT_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_HtoS) + .value("UDOT_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_BtoS) + .value("UDOT_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_HtoD) + .value("UDOT_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4Z4Z_HtoS) + .value("UDOT_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_BtoS) + .value("UDOT_VG4_M4ZZI_HToS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_HToS) + .value("UDOT_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZI_HtoD) + .value("UDOT_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_BtoS) + .value("UDOT_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_HtoD) + .value("UDOT_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_VG4_M4ZZ_HtoS) + .value("UDOT_ZZZI_BtoH", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZI_BtoH) + .value("UDOT_ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZI_BtoS) + .value("UDOT_ZZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZI_HtoD) + .value("UDOT_ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZI_HtoS) + .value("UDOT_ZZZ_BtoH", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZ_BtoH) + .value("UDOT_ZZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZ_BtoS) + .value("UDOT_ZZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZ_HtoD) + .value("UDOT_ZZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UDOT_ZZZ_HtoS) + .value("UDOTlanev16i8", LIEF::assembly::aarch64::OPCODE::UDOTlanev16i8) + .value("UDOTlanev8i8", LIEF::assembly::aarch64::OPCODE::UDOTlanev8i8) + .value("UDOTv16i8", LIEF::assembly::aarch64::OPCODE::UDOTv16i8) + .value("UDOTv8i8", LIEF::assembly::aarch64::OPCODE::UDOTv8i8) + .value("UHADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UHADD_ZPmZ_B) + .value("UHADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UHADD_ZPmZ_D) + .value("UHADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UHADD_ZPmZ_H) + .value("UHADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UHADD_ZPmZ_S) + .value("UHADDv16i8", LIEF::assembly::aarch64::OPCODE::UHADDv16i8) + .value("UHADDv2i32", LIEF::assembly::aarch64::OPCODE::UHADDv2i32) + .value("UHADDv4i16", LIEF::assembly::aarch64::OPCODE::UHADDv4i16) + .value("UHADDv4i32", LIEF::assembly::aarch64::OPCODE::UHADDv4i32) + .value("UHADDv8i16", LIEF::assembly::aarch64::OPCODE::UHADDv8i16) + .value("UHADDv8i8", LIEF::assembly::aarch64::OPCODE::UHADDv8i8) + .value("UHSUBR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UHSUBR_ZPmZ_B) + .value("UHSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UHSUBR_ZPmZ_D) + .value("UHSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UHSUBR_ZPmZ_H) + .value("UHSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UHSUBR_ZPmZ_S) + .value("UHSUB_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPmZ_B) + .value("UHSUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPmZ_D) + .value("UHSUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPmZ_H) + .value("UHSUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPmZ_S) + .value("UHSUBv16i8", LIEF::assembly::aarch64::OPCODE::UHSUBv16i8) + .value("UHSUBv2i32", LIEF::assembly::aarch64::OPCODE::UHSUBv2i32) + .value("UHSUBv4i16", LIEF::assembly::aarch64::OPCODE::UHSUBv4i16) + .value("UHSUBv4i32", LIEF::assembly::aarch64::OPCODE::UHSUBv4i32) + .value("UHSUBv8i16", LIEF::assembly::aarch64::OPCODE::UHSUBv8i16) + .value("UHSUBv8i8", LIEF::assembly::aarch64::OPCODE::UHSUBv8i8) + .value("UMADDLrrr", LIEF::assembly::aarch64::OPCODE::UMADDLrrr) + .value("UMAXP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UMAXP_ZPmZ_B) + .value("UMAXP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UMAXP_ZPmZ_D) + .value("UMAXP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UMAXP_ZPmZ_H) + .value("UMAXP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UMAXP_ZPmZ_S) + .value("UMAXPv16i8", LIEF::assembly::aarch64::OPCODE::UMAXPv16i8) + .value("UMAXPv2i32", LIEF::assembly::aarch64::OPCODE::UMAXPv2i32) + .value("UMAXPv4i16", LIEF::assembly::aarch64::OPCODE::UMAXPv4i16) + .value("UMAXPv4i32", LIEF::assembly::aarch64::OPCODE::UMAXPv4i32) + .value("UMAXPv8i16", LIEF::assembly::aarch64::OPCODE::UMAXPv8i16) + .value("UMAXPv8i8", LIEF::assembly::aarch64::OPCODE::UMAXPv8i8) + .value("UMAXQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::UMAXQV_VPZ_B) + .value("UMAXQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::UMAXQV_VPZ_D) + .value("UMAXQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::UMAXQV_VPZ_H) + .value("UMAXQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::UMAXQV_VPZ_S) + .value("UMAXV_VPZ_B", LIEF::assembly::aarch64::OPCODE::UMAXV_VPZ_B) + .value("UMAXV_VPZ_D", LIEF::assembly::aarch64::OPCODE::UMAXV_VPZ_D) + .value("UMAXV_VPZ_H", LIEF::assembly::aarch64::OPCODE::UMAXV_VPZ_H) + .value("UMAXV_VPZ_S", LIEF::assembly::aarch64::OPCODE::UMAXV_VPZ_S) + .value("UMAXVv16i8v", LIEF::assembly::aarch64::OPCODE::UMAXVv16i8v) + .value("UMAXVv4i16v", LIEF::assembly::aarch64::OPCODE::UMAXVv4i16v) + .value("UMAXVv4i32v", LIEF::assembly::aarch64::OPCODE::UMAXVv4i32v) + .value("UMAXVv8i16v", LIEF::assembly::aarch64::OPCODE::UMAXVv8i16v) + .value("UMAXVv8i8v", LIEF::assembly::aarch64::OPCODE::UMAXVv8i8v) + .value("UMAXWri", LIEF::assembly::aarch64::OPCODE::UMAXWri) + .value("UMAXWrr", LIEF::assembly::aarch64::OPCODE::UMAXWrr) + .value("UMAXXri", LIEF::assembly::aarch64::OPCODE::UMAXXri) + .value("UMAXXrr", LIEF::assembly::aarch64::OPCODE::UMAXXrr) + .value("UMAX_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2Z2Z_B) + .value("UMAX_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2Z2Z_D) + .value("UMAX_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2Z2Z_H) + .value("UMAX_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2Z2Z_S) + .value("UMAX_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2ZZ_B) + .value("UMAX_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2ZZ_D) + .value("UMAX_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2ZZ_H) + .value("UMAX_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::UMAX_VG2_2ZZ_S) + .value("UMAX_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4Z4Z_B) + .value("UMAX_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4Z4Z_D) + .value("UMAX_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4Z4Z_H) + .value("UMAX_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4Z4Z_S) + .value("UMAX_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4ZZ_B) + .value("UMAX_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4ZZ_D) + .value("UMAX_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4ZZ_H) + .value("UMAX_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::UMAX_VG4_4ZZ_S) + .value("UMAX_ZI_B", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_B) + .value("UMAX_ZI_D", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_D) + .value("UMAX_ZI_H", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_H) + .value("UMAX_ZI_S", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_S) + .value("UMAX_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UMAX_ZPmZ_B) + .value("UMAX_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UMAX_ZPmZ_D) + .value("UMAX_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UMAX_ZPmZ_H) + .value("UMAX_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UMAX_ZPmZ_S) + .value("UMAXv16i8", LIEF::assembly::aarch64::OPCODE::UMAXv16i8) + .value("UMAXv2i32", LIEF::assembly::aarch64::OPCODE::UMAXv2i32) + .value("UMAXv4i16", LIEF::assembly::aarch64::OPCODE::UMAXv4i16) + .value("UMAXv4i32", LIEF::assembly::aarch64::OPCODE::UMAXv4i32) + .value("UMAXv8i16", LIEF::assembly::aarch64::OPCODE::UMAXv8i16) + .value("UMAXv8i8", LIEF::assembly::aarch64::OPCODE::UMAXv8i8) + .value("UMINP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UMINP_ZPmZ_B) + .value("UMINP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UMINP_ZPmZ_D) + .value("UMINP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UMINP_ZPmZ_H) + .value("UMINP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UMINP_ZPmZ_S) + .value("UMINPv16i8", LIEF::assembly::aarch64::OPCODE::UMINPv16i8) + .value("UMINPv2i32", LIEF::assembly::aarch64::OPCODE::UMINPv2i32) + .value("UMINPv4i16", LIEF::assembly::aarch64::OPCODE::UMINPv4i16) + .value("UMINPv4i32", LIEF::assembly::aarch64::OPCODE::UMINPv4i32) + .value("UMINPv8i16", LIEF::assembly::aarch64::OPCODE::UMINPv8i16) + .value("UMINPv8i8", LIEF::assembly::aarch64::OPCODE::UMINPv8i8) + .value("UMINQV_VPZ_B", LIEF::assembly::aarch64::OPCODE::UMINQV_VPZ_B) + .value("UMINQV_VPZ_D", LIEF::assembly::aarch64::OPCODE::UMINQV_VPZ_D) + .value("UMINQV_VPZ_H", LIEF::assembly::aarch64::OPCODE::UMINQV_VPZ_H) + .value("UMINQV_VPZ_S", LIEF::assembly::aarch64::OPCODE::UMINQV_VPZ_S) + .value("UMINV_VPZ_B", LIEF::assembly::aarch64::OPCODE::UMINV_VPZ_B) + .value("UMINV_VPZ_D", LIEF::assembly::aarch64::OPCODE::UMINV_VPZ_D) + .value("UMINV_VPZ_H", LIEF::assembly::aarch64::OPCODE::UMINV_VPZ_H) + .value("UMINV_VPZ_S", LIEF::assembly::aarch64::OPCODE::UMINV_VPZ_S) + .value("UMINVv16i8v", LIEF::assembly::aarch64::OPCODE::UMINVv16i8v) + .value("UMINVv4i16v", LIEF::assembly::aarch64::OPCODE::UMINVv4i16v) + .value("UMINVv4i32v", LIEF::assembly::aarch64::OPCODE::UMINVv4i32v) + .value("UMINVv8i16v", LIEF::assembly::aarch64::OPCODE::UMINVv8i16v) + .value("UMINVv8i8v", LIEF::assembly::aarch64::OPCODE::UMINVv8i8v) + .value("UMINWri", LIEF::assembly::aarch64::OPCODE::UMINWri) + .value("UMINWrr", LIEF::assembly::aarch64::OPCODE::UMINWrr) + .value("UMINXri", LIEF::assembly::aarch64::OPCODE::UMINXri) + .value("UMINXrr", LIEF::assembly::aarch64::OPCODE::UMINXrr) + .value("UMIN_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2Z2Z_B) + .value("UMIN_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2Z2Z_D) + .value("UMIN_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2Z2Z_H) + .value("UMIN_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2Z2Z_S) + .value("UMIN_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2ZZ_B) + .value("UMIN_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2ZZ_D) + .value("UMIN_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2ZZ_H) + .value("UMIN_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::UMIN_VG2_2ZZ_S) + .value("UMIN_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4Z4Z_B) + .value("UMIN_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4Z4Z_D) + .value("UMIN_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4Z4Z_H) + .value("UMIN_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4Z4Z_S) + .value("UMIN_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4ZZ_B) + .value("UMIN_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4ZZ_D) + .value("UMIN_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4ZZ_H) + .value("UMIN_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::UMIN_VG4_4ZZ_S) + .value("UMIN_ZI_B", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_B) + .value("UMIN_ZI_D", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_D) + .value("UMIN_ZI_H", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_H) + .value("UMIN_ZI_S", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_S) + .value("UMIN_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UMIN_ZPmZ_B) + .value("UMIN_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UMIN_ZPmZ_D) + .value("UMIN_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UMIN_ZPmZ_H) + .value("UMIN_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UMIN_ZPmZ_S) + .value("UMINv16i8", LIEF::assembly::aarch64::OPCODE::UMINv16i8) + .value("UMINv2i32", LIEF::assembly::aarch64::OPCODE::UMINv2i32) + .value("UMINv4i16", LIEF::assembly::aarch64::OPCODE::UMINv4i16) + .value("UMINv4i32", LIEF::assembly::aarch64::OPCODE::UMINv4i32) + .value("UMINv8i16", LIEF::assembly::aarch64::OPCODE::UMINv8i16) + .value("UMINv8i8", LIEF::assembly::aarch64::OPCODE::UMINv8i8) + .value("UMLALB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMLALB_ZZZI_D) + .value("UMLALB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMLALB_ZZZI_S) + .value("UMLALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMLALB_ZZZ_D) + .value("UMLALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMLALB_ZZZ_H) + .value("UMLALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMLALB_ZZZ_S) + .value("UMLALL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZI_BtoS) + .value("UMLALL_MZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZI_HtoD) + .value("UMLALL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZ_BtoS) + .value("UMLALL_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_MZZ_HtoD) + .value("UMLALL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2Z2Z_BtoS) + .value("UMLALL_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2Z2Z_HtoD) + .value("UMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZI_BtoS) + .value("UMLALL_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZI_HtoD) + .value("UMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZ_BtoS) + .value("UMLALL_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG2_M2ZZ_HtoD) + .value("UMLALL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4Z4Z_BtoS) + .value("UMLALL_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4Z4Z_HtoD) + .value("UMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZI_BtoS) + .value("UMLALL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZI_HtoD) + .value("UMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZ_BtoS) + .value("UMLALL_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLALL_VG4_M4ZZ_HtoD) + .value("UMLALT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMLALT_ZZZI_D) + .value("UMLALT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMLALT_ZZZI_S) + .value("UMLALT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMLALT_ZZZ_D) + .value("UMLALT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMLALT_ZZZ_H) + .value("UMLALT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMLALT_ZZZ_S) + .value("UMLAL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_MZZI_HtoS) + .value("UMLAL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_MZZ_HtoS) + .value("UMLAL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2Z2Z_HtoS) + .value("UMLAL_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZI_S) + .value("UMLAL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZ_HtoS) + .value("UMLAL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4Z4Z_HtoS) + .value("UMLAL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZI_HtoS) + .value("UMLAL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZ_HtoS) + .value("UMLALv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMLALv16i8_v8i16) + .value("UMLALv2i32_indexed", LIEF::assembly::aarch64::OPCODE::UMLALv2i32_indexed) + .value("UMLALv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMLALv2i32_v2i64) + .value("UMLALv4i16_indexed", LIEF::assembly::aarch64::OPCODE::UMLALv4i16_indexed) + .value("UMLALv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMLALv4i16_v4i32) + .value("UMLALv4i32_indexed", LIEF::assembly::aarch64::OPCODE::UMLALv4i32_indexed) + .value("UMLALv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMLALv4i32_v2i64) + .value("UMLALv8i16_indexed", LIEF::assembly::aarch64::OPCODE::UMLALv8i16_indexed) + .value("UMLALv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMLALv8i16_v4i32) + .value("UMLALv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMLALv8i8_v8i16) + .value("UMLSLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMLSLB_ZZZI_D) + .value("UMLSLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMLSLB_ZZZI_S) + .value("UMLSLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMLSLB_ZZZ_D) + .value("UMLSLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMLSLB_ZZZ_H) + .value("UMLSLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMLSLB_ZZZ_S) + .value("UMLSLL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZI_BtoS) + .value("UMLSLL_MZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZI_HtoD) + .value("UMLSLL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZ_BtoS) + .value("UMLSLL_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZ_HtoD) + .value("UMLSLL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2Z2Z_BtoS) + .value("UMLSLL_VG2_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2Z2Z_HtoD) + .value("UMLSLL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZI_BtoS) + .value("UMLSLL_VG2_M2ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZI_HtoD) + .value("UMLSLL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZ_BtoS) + .value("UMLSLL_VG2_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG2_M2ZZ_HtoD) + .value("UMLSLL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_BtoS) + .value("UMLSLL_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_HtoD) + .value("UMLSLL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_BtoS) + .value("UMLSLL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_HtoD) + .value("UMLSLL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_BtoS) + .value("UMLSLL_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_HtoD) + .value("UMLSLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZI_D) + .value("UMLSLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZI_S) + .value("UMLSLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZ_D) + .value("UMLSLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZ_H) + .value("UMLSLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZ_S) + .value("UMLSL_MZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_MZZI_HtoS) + .value("UMLSL_MZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_MZZ_HtoS) + .value("UMLSL_VG2_M2Z2Z_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2Z2Z_HtoS) + .value("UMLSL_VG2_M2ZZI_S", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2ZZI_S) + .value("UMLSL_VG2_M2ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_VG2_M2ZZ_HtoS) + .value("UMLSL_VG4_M4Z4Z_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4Z4Z_HtoS) + .value("UMLSL_VG4_M4ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4ZZI_HtoS) + .value("UMLSL_VG4_M4ZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMLSL_VG4_M4ZZ_HtoS) + .value("UMLSLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMLSLv16i8_v8i16) + .value("UMLSLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::UMLSLv2i32_indexed) + .value("UMLSLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMLSLv2i32_v2i64) + .value("UMLSLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::UMLSLv4i16_indexed) + .value("UMLSLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMLSLv4i16_v4i32) + .value("UMLSLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::UMLSLv4i32_indexed) + .value("UMLSLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMLSLv4i32_v2i64) + .value("UMLSLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::UMLSLv8i16_indexed) + .value("UMLSLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMLSLv8i16_v4i32) + .value("UMLSLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMLSLv8i8_v8i16) + .value("UMMLA", LIEF::assembly::aarch64::OPCODE::UMMLA) + .value("UMMLA_ZZZ", LIEF::assembly::aarch64::OPCODE::UMMLA_ZZZ) + .value("UMOP4A_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_BToS) + .value("UMOP4A_M2Z2Z_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_HToS) + .value("UMOP4A_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2Z2Z_HtoD) + .value("UMOP4A_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_BToS) + .value("UMOP4A_M2ZZ_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_HToS) + .value("UMOP4A_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4A_M2ZZ_HtoD) + .value("UMOP4A_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_BToS) + .value("UMOP4A_MZ2Z_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_HToS) + .value("UMOP4A_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZ2Z_HtoD) + .value("UMOP4A_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_BToS) + .value("UMOP4A_MZZ_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_HToS) + .value("UMOP4A_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4A_MZZ_HtoD) + .value("UMOP4S_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_BToS) + .value("UMOP4S_M2Z2Z_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_HToS) + .value("UMOP4S_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2Z2Z_HtoD) + .value("UMOP4S_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_BToS) + .value("UMOP4S_M2ZZ_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_HToS) + .value("UMOP4S_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4S_M2ZZ_HtoD) + .value("UMOP4S_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_BToS) + .value("UMOP4S_MZ2Z_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_HToS) + .value("UMOP4S_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZ2Z_HtoD) + .value("UMOP4S_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_BToS) + .value("UMOP4S_MZZ_HToS", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_HToS) + .value("UMOP4S_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMOP4S_MZZ_HtoD) + .value("UMOPA_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_D) + .value("UMOPA_MPPZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_HtoS) + .value("UMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_S) + .value("UMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_D) + .value("UMOPS_MPPZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_HtoS) + .value("UMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_S); + opcodes.value("UMOVvi16", LIEF::assembly::aarch64::OPCODE::UMOVvi16) + .value("UMOVvi16_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi16_idx0) + .value("UMOVvi32", LIEF::assembly::aarch64::OPCODE::UMOVvi32) + .value("UMOVvi32_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi32_idx0) + .value("UMOVvi64", LIEF::assembly::aarch64::OPCODE::UMOVvi64) + .value("UMOVvi64_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi64_idx0) + .value("UMOVvi8", LIEF::assembly::aarch64::OPCODE::UMOVvi8) + .value("UMOVvi8_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi8_idx0) + .value("UMSUBLrrr", LIEF::assembly::aarch64::OPCODE::UMSUBLrrr) + .value("UMULH_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UMULH_ZPmZ_B) + .value("UMULH_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UMULH_ZPmZ_D) + .value("UMULH_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UMULH_ZPmZ_H) + .value("UMULH_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UMULH_ZPmZ_S) + .value("UMULH_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UMULH_ZZZ_B) + .value("UMULH_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMULH_ZZZ_D) + .value("UMULH_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMULH_ZZZ_H) + .value("UMULH_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMULH_ZZZ_S) + .value("UMULHrr", LIEF::assembly::aarch64::OPCODE::UMULHrr) + .value("UMULLB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMULLB_ZZZI_D) + .value("UMULLB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMULLB_ZZZI_S) + .value("UMULLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMULLB_ZZZ_D) + .value("UMULLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMULLB_ZZZ_H) + .value("UMULLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMULLB_ZZZ_S) + .value("UMULLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMULLT_ZZZI_D) + .value("UMULLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMULLT_ZZZI_S) + .value("UMULLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UMULLT_ZZZ_D) + .value("UMULLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UMULLT_ZZZ_H) + .value("UMULLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UMULLT_ZZZ_S) + .value("UMULLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMULLv16i8_v8i16) + .value("UMULLv2i32_indexed", LIEF::assembly::aarch64::OPCODE::UMULLv2i32_indexed) + .value("UMULLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMULLv2i32_v2i64) + .value("UMULLv4i16_indexed", LIEF::assembly::aarch64::OPCODE::UMULLv4i16_indexed) + .value("UMULLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMULLv4i16_v4i32) + .value("UMULLv4i32_indexed", LIEF::assembly::aarch64::OPCODE::UMULLv4i32_indexed) + .value("UMULLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::UMULLv4i32_v2i64) + .value("UMULLv8i16_indexed", LIEF::assembly::aarch64::OPCODE::UMULLv8i16_indexed) + .value("UMULLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::UMULLv8i16_v4i32) + .value("UMULLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::UMULLv8i8_v8i16) + .value("UQADD_ZI_B", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_B) + .value("UQADD_ZI_D", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_D) + .value("UQADD_ZI_H", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_H) + .value("UQADD_ZI_S", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_S) + .value("UQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQADD_ZPmZ_B) + .value("UQADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQADD_ZPmZ_D) + .value("UQADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQADD_ZPmZ_H) + .value("UQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQADD_ZPmZ_S) + .value("UQADD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UQADD_ZZZ_B) + .value("UQADD_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UQADD_ZZZ_D) + .value("UQADD_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UQADD_ZZZ_H) + .value("UQADD_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UQADD_ZZZ_S) + .value("UQADDv16i8", LIEF::assembly::aarch64::OPCODE::UQADDv16i8) + .value("UQADDv1i16", LIEF::assembly::aarch64::OPCODE::UQADDv1i16) + .value("UQADDv1i32", LIEF::assembly::aarch64::OPCODE::UQADDv1i32) + .value("UQADDv1i64", LIEF::assembly::aarch64::OPCODE::UQADDv1i64) + .value("UQADDv1i8", LIEF::assembly::aarch64::OPCODE::UQADDv1i8) + .value("UQADDv2i32", LIEF::assembly::aarch64::OPCODE::UQADDv2i32) + .value("UQADDv2i64", LIEF::assembly::aarch64::OPCODE::UQADDv2i64) + .value("UQADDv4i16", LIEF::assembly::aarch64::OPCODE::UQADDv4i16) + .value("UQADDv4i32", LIEF::assembly::aarch64::OPCODE::UQADDv4i32) + .value("UQADDv8i16", LIEF::assembly::aarch64::OPCODE::UQADDv8i16) + .value("UQADDv8i8", LIEF::assembly::aarch64::OPCODE::UQADDv8i8) + .value("UQCVTN_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::UQCVTN_Z2Z_StoH) + .value("UQCVTN_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::UQCVTN_Z4Z_DtoH) + .value("UQCVTN_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::UQCVTN_Z4Z_StoB) + .value("UQCVT_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::UQCVT_Z2Z_StoH) + .value("UQCVT_Z4Z_DtoH", LIEF::assembly::aarch64::OPCODE::UQCVT_Z4Z_DtoH) + .value("UQCVT_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::UQCVT_Z4Z_StoB) + .value("UQDECB_WPiI", LIEF::assembly::aarch64::OPCODE::UQDECB_WPiI) + .value("UQDECB_XPiI", LIEF::assembly::aarch64::OPCODE::UQDECB_XPiI) + .value("UQDECD_WPiI", LIEF::assembly::aarch64::OPCODE::UQDECD_WPiI) + .value("UQDECD_XPiI", LIEF::assembly::aarch64::OPCODE::UQDECD_XPiI) + .value("UQDECD_ZPiI", LIEF::assembly::aarch64::OPCODE::UQDECD_ZPiI) + .value("UQDECH_WPiI", LIEF::assembly::aarch64::OPCODE::UQDECH_WPiI) + .value("UQDECH_XPiI", LIEF::assembly::aarch64::OPCODE::UQDECH_XPiI) + .value("UQDECH_ZPiI", LIEF::assembly::aarch64::OPCODE::UQDECH_ZPiI) + .value("UQDECP_WP_B", LIEF::assembly::aarch64::OPCODE::UQDECP_WP_B) + .value("UQDECP_WP_D", LIEF::assembly::aarch64::OPCODE::UQDECP_WP_D) + .value("UQDECP_WP_H", LIEF::assembly::aarch64::OPCODE::UQDECP_WP_H) + .value("UQDECP_WP_S", LIEF::assembly::aarch64::OPCODE::UQDECP_WP_S) + .value("UQDECP_XP_B", LIEF::assembly::aarch64::OPCODE::UQDECP_XP_B) + .value("UQDECP_XP_D", LIEF::assembly::aarch64::OPCODE::UQDECP_XP_D) + .value("UQDECP_XP_H", LIEF::assembly::aarch64::OPCODE::UQDECP_XP_H) + .value("UQDECP_XP_S", LIEF::assembly::aarch64::OPCODE::UQDECP_XP_S) + .value("UQDECP_ZP_D", LIEF::assembly::aarch64::OPCODE::UQDECP_ZP_D) + .value("UQDECP_ZP_H", LIEF::assembly::aarch64::OPCODE::UQDECP_ZP_H) + .value("UQDECP_ZP_S", LIEF::assembly::aarch64::OPCODE::UQDECP_ZP_S) + .value("UQDECW_WPiI", LIEF::assembly::aarch64::OPCODE::UQDECW_WPiI) + .value("UQDECW_XPiI", LIEF::assembly::aarch64::OPCODE::UQDECW_XPiI) + .value("UQDECW_ZPiI", LIEF::assembly::aarch64::OPCODE::UQDECW_ZPiI) + .value("UQINCB_WPiI", LIEF::assembly::aarch64::OPCODE::UQINCB_WPiI) + .value("UQINCB_XPiI", LIEF::assembly::aarch64::OPCODE::UQINCB_XPiI) + .value("UQINCD_WPiI", LIEF::assembly::aarch64::OPCODE::UQINCD_WPiI) + .value("UQINCD_XPiI", LIEF::assembly::aarch64::OPCODE::UQINCD_XPiI) + .value("UQINCD_ZPiI", LIEF::assembly::aarch64::OPCODE::UQINCD_ZPiI) + .value("UQINCH_WPiI", LIEF::assembly::aarch64::OPCODE::UQINCH_WPiI) + .value("UQINCH_XPiI", LIEF::assembly::aarch64::OPCODE::UQINCH_XPiI) + .value("UQINCH_ZPiI", LIEF::assembly::aarch64::OPCODE::UQINCH_ZPiI) + .value("UQINCP_WP_B", LIEF::assembly::aarch64::OPCODE::UQINCP_WP_B) + .value("UQINCP_WP_D", LIEF::assembly::aarch64::OPCODE::UQINCP_WP_D) + .value("UQINCP_WP_H", LIEF::assembly::aarch64::OPCODE::UQINCP_WP_H) + .value("UQINCP_WP_S", LIEF::assembly::aarch64::OPCODE::UQINCP_WP_S) + .value("UQINCP_XP_B", LIEF::assembly::aarch64::OPCODE::UQINCP_XP_B) + .value("UQINCP_XP_D", LIEF::assembly::aarch64::OPCODE::UQINCP_XP_D) + .value("UQINCP_XP_H", LIEF::assembly::aarch64::OPCODE::UQINCP_XP_H) + .value("UQINCP_XP_S", LIEF::assembly::aarch64::OPCODE::UQINCP_XP_S) + .value("UQINCP_ZP_D", LIEF::assembly::aarch64::OPCODE::UQINCP_ZP_D) + .value("UQINCP_ZP_H", LIEF::assembly::aarch64::OPCODE::UQINCP_ZP_H) + .value("UQINCP_ZP_S", LIEF::assembly::aarch64::OPCODE::UQINCP_ZP_S) + .value("UQINCW_WPiI", LIEF::assembly::aarch64::OPCODE::UQINCW_WPiI) + .value("UQINCW_XPiI", LIEF::assembly::aarch64::OPCODE::UQINCW_XPiI) + .value("UQINCW_ZPiI", LIEF::assembly::aarch64::OPCODE::UQINCW_ZPiI) + .value("UQRSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQRSHLR_ZPmZ_B) + .value("UQRSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQRSHLR_ZPmZ_D) + .value("UQRSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQRSHLR_ZPmZ_H) + .value("UQRSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQRSHLR_ZPmZ_S) + .value("UQRSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPmZ_B) + .value("UQRSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPmZ_D) + .value("UQRSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPmZ_H) + .value("UQRSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPmZ_S) + .value("UQRSHLv16i8", LIEF::assembly::aarch64::OPCODE::UQRSHLv16i8) + .value("UQRSHLv1i16", LIEF::assembly::aarch64::OPCODE::UQRSHLv1i16) + .value("UQRSHLv1i32", LIEF::assembly::aarch64::OPCODE::UQRSHLv1i32) + .value("UQRSHLv1i64", LIEF::assembly::aarch64::OPCODE::UQRSHLv1i64) + .value("UQRSHLv1i8", LIEF::assembly::aarch64::OPCODE::UQRSHLv1i8) + .value("UQRSHLv2i32", LIEF::assembly::aarch64::OPCODE::UQRSHLv2i32) + .value("UQRSHLv2i64", LIEF::assembly::aarch64::OPCODE::UQRSHLv2i64) + .value("UQRSHLv4i16", LIEF::assembly::aarch64::OPCODE::UQRSHLv4i16) + .value("UQRSHLv4i32", LIEF::assembly::aarch64::OPCODE::UQRSHLv4i32) + .value("UQRSHLv8i16", LIEF::assembly::aarch64::OPCODE::UQRSHLv8i16) + .value("UQRSHLv8i8", LIEF::assembly::aarch64::OPCODE::UQRSHLv8i8) + .value("UQRSHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::UQRSHRNB_ZZI_B) + .value("UQRSHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::UQRSHRNB_ZZI_H) + .value("UQRSHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::UQRSHRNB_ZZI_S) + .value("UQRSHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::UQRSHRNT_ZZI_B) + .value("UQRSHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::UQRSHRNT_ZZI_H) + .value("UQRSHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::UQRSHRNT_ZZI_S) + .value("UQRSHRN_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::UQRSHRN_VG4_Z4ZI_B) + .value("UQRSHRN_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::UQRSHRN_VG4_Z4ZI_H) + .value("UQRSHRN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::UQRSHRN_Z2ZI_HtoB) + .value("UQRSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::UQRSHRN_Z2ZI_StoH) + .value("UQRSHRNb", LIEF::assembly::aarch64::OPCODE::UQRSHRNb) + .value("UQRSHRNh", LIEF::assembly::aarch64::OPCODE::UQRSHRNh) + .value("UQRSHRNs", LIEF::assembly::aarch64::OPCODE::UQRSHRNs) + .value("UQRSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv16i8_shift) + .value("UQRSHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv2i32_shift) + .value("UQRSHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv4i16_shift) + .value("UQRSHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv4i32_shift) + .value("UQRSHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv8i16_shift) + .value("UQRSHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::UQRSHRNv8i8_shift) + .value("UQRSHR_VG2_Z2ZI_H", LIEF::assembly::aarch64::OPCODE::UQRSHR_VG2_Z2ZI_H) + .value("UQRSHR_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::UQRSHR_VG4_Z4ZI_B) + .value("UQRSHR_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::UQRSHR_VG4_Z4ZI_H) + .value("UQSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQSHLR_ZPmZ_B) + .value("UQSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQSHLR_ZPmZ_D) + .value("UQSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQSHLR_ZPmZ_H) + .value("UQSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQSHLR_ZPmZ_S) + .value("UQSHL_ZPmI_B", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmI_B) + .value("UQSHL_ZPmI_D", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmI_D) + .value("UQSHL_ZPmI_H", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmI_H) + .value("UQSHL_ZPmI_S", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmI_S) + .value("UQSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmZ_B) + .value("UQSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmZ_D) + .value("UQSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmZ_H) + .value("UQSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPmZ_S) + .value("UQSHLb", LIEF::assembly::aarch64::OPCODE::UQSHLb) + .value("UQSHLd", LIEF::assembly::aarch64::OPCODE::UQSHLd) + .value("UQSHLh", LIEF::assembly::aarch64::OPCODE::UQSHLh) + .value("UQSHLs", LIEF::assembly::aarch64::OPCODE::UQSHLs) + .value("UQSHLv16i8", LIEF::assembly::aarch64::OPCODE::UQSHLv16i8) + .value("UQSHLv16i8_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv16i8_shift) + .value("UQSHLv1i16", LIEF::assembly::aarch64::OPCODE::UQSHLv1i16) + .value("UQSHLv1i32", LIEF::assembly::aarch64::OPCODE::UQSHLv1i32) + .value("UQSHLv1i64", LIEF::assembly::aarch64::OPCODE::UQSHLv1i64) + .value("UQSHLv1i8", LIEF::assembly::aarch64::OPCODE::UQSHLv1i8) + .value("UQSHLv2i32", LIEF::assembly::aarch64::OPCODE::UQSHLv2i32) + .value("UQSHLv2i32_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv2i32_shift) + .value("UQSHLv2i64", LIEF::assembly::aarch64::OPCODE::UQSHLv2i64) + .value("UQSHLv2i64_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv2i64_shift) + .value("UQSHLv4i16", LIEF::assembly::aarch64::OPCODE::UQSHLv4i16) + .value("UQSHLv4i16_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv4i16_shift) + .value("UQSHLv4i32", LIEF::assembly::aarch64::OPCODE::UQSHLv4i32) + .value("UQSHLv4i32_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv4i32_shift) + .value("UQSHLv8i16", LIEF::assembly::aarch64::OPCODE::UQSHLv8i16) + .value("UQSHLv8i16_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv8i16_shift) + .value("UQSHLv8i8", LIEF::assembly::aarch64::OPCODE::UQSHLv8i8) + .value("UQSHLv8i8_shift", LIEF::assembly::aarch64::OPCODE::UQSHLv8i8_shift) + .value("UQSHRNB_ZZI_B", LIEF::assembly::aarch64::OPCODE::UQSHRNB_ZZI_B) + .value("UQSHRNB_ZZI_H", LIEF::assembly::aarch64::OPCODE::UQSHRNB_ZZI_H) + .value("UQSHRNB_ZZI_S", LIEF::assembly::aarch64::OPCODE::UQSHRNB_ZZI_S) + .value("UQSHRNT_ZZI_B", LIEF::assembly::aarch64::OPCODE::UQSHRNT_ZZI_B) + .value("UQSHRNT_ZZI_H", LIEF::assembly::aarch64::OPCODE::UQSHRNT_ZZI_H) + .value("UQSHRNT_ZZI_S", LIEF::assembly::aarch64::OPCODE::UQSHRNT_ZZI_S) + .value("UQSHRN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::UQSHRN_Z2ZI_HtoB) + .value("UQSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::UQSHRN_Z2ZI_StoH) + .value("UQSHRNb", LIEF::assembly::aarch64::OPCODE::UQSHRNb) + .value("UQSHRNh", LIEF::assembly::aarch64::OPCODE::UQSHRNh) + .value("UQSHRNs", LIEF::assembly::aarch64::OPCODE::UQSHRNs) + .value("UQSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv16i8_shift) + .value("UQSHRNv2i32_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv2i32_shift) + .value("UQSHRNv4i16_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv4i16_shift) + .value("UQSHRNv4i32_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv4i32_shift) + .value("UQSHRNv8i16_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv8i16_shift) + .value("UQSHRNv8i8_shift", LIEF::assembly::aarch64::OPCODE::UQSHRNv8i8_shift) + .value("UQSUBR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQSUBR_ZPmZ_B) + .value("UQSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQSUBR_ZPmZ_D) + .value("UQSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQSUBR_ZPmZ_H) + .value("UQSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQSUBR_ZPmZ_S) + .value("UQSUB_ZI_B", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_B) + .value("UQSUB_ZI_D", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_D) + .value("UQSUB_ZI_H", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_H) + .value("UQSUB_ZI_S", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_S) + .value("UQSUB_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::UQSUB_ZPmZ_B) + .value("UQSUB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UQSUB_ZPmZ_D) + .value("UQSUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UQSUB_ZPmZ_H) + .value("UQSUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UQSUB_ZPmZ_S) + .value("UQSUB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UQSUB_ZZZ_B) + .value("UQSUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UQSUB_ZZZ_D) + .value("UQSUB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UQSUB_ZZZ_H) + .value("UQSUB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UQSUB_ZZZ_S) + .value("UQSUBv16i8", LIEF::assembly::aarch64::OPCODE::UQSUBv16i8) + .value("UQSUBv1i16", LIEF::assembly::aarch64::OPCODE::UQSUBv1i16) + .value("UQSUBv1i32", LIEF::assembly::aarch64::OPCODE::UQSUBv1i32) + .value("UQSUBv1i64", LIEF::assembly::aarch64::OPCODE::UQSUBv1i64) + .value("UQSUBv1i8", LIEF::assembly::aarch64::OPCODE::UQSUBv1i8) + .value("UQSUBv2i32", LIEF::assembly::aarch64::OPCODE::UQSUBv2i32) + .value("UQSUBv2i64", LIEF::assembly::aarch64::OPCODE::UQSUBv2i64) + .value("UQSUBv4i16", LIEF::assembly::aarch64::OPCODE::UQSUBv4i16) + .value("UQSUBv4i32", LIEF::assembly::aarch64::OPCODE::UQSUBv4i32) + .value("UQSUBv8i16", LIEF::assembly::aarch64::OPCODE::UQSUBv8i16) + .value("UQSUBv8i8", LIEF::assembly::aarch64::OPCODE::UQSUBv8i8) + .value("UQXTNB_ZZ_B", LIEF::assembly::aarch64::OPCODE::UQXTNB_ZZ_B) + .value("UQXTNB_ZZ_H", LIEF::assembly::aarch64::OPCODE::UQXTNB_ZZ_H) + .value("UQXTNB_ZZ_S", LIEF::assembly::aarch64::OPCODE::UQXTNB_ZZ_S) + .value("UQXTNT_ZZ_B", LIEF::assembly::aarch64::OPCODE::UQXTNT_ZZ_B) + .value("UQXTNT_ZZ_H", LIEF::assembly::aarch64::OPCODE::UQXTNT_ZZ_H) + .value("UQXTNT_ZZ_S", LIEF::assembly::aarch64::OPCODE::UQXTNT_ZZ_S) + .value("UQXTNv16i8", LIEF::assembly::aarch64::OPCODE::UQXTNv16i8) + .value("UQXTNv1i16", LIEF::assembly::aarch64::OPCODE::UQXTNv1i16) + .value("UQXTNv1i32", LIEF::assembly::aarch64::OPCODE::UQXTNv1i32) + .value("UQXTNv1i8", LIEF::assembly::aarch64::OPCODE::UQXTNv1i8) + .value("UQXTNv2i32", LIEF::assembly::aarch64::OPCODE::UQXTNv2i32) + .value("UQXTNv4i16", LIEF::assembly::aarch64::OPCODE::UQXTNv4i16) + .value("UQXTNv4i32", LIEF::assembly::aarch64::OPCODE::UQXTNv4i32) + .value("UQXTNv8i16", LIEF::assembly::aarch64::OPCODE::UQXTNv8i16) + .value("UQXTNv8i8", LIEF::assembly::aarch64::OPCODE::UQXTNv8i8) + .value("URECPE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URECPE_ZPmZ_S) + .value("URECPE_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::URECPE_ZPzZ_S) + .value("URECPEv2i32", LIEF::assembly::aarch64::OPCODE::URECPEv2i32) + .value("URECPEv4i32", LIEF::assembly::aarch64::OPCODE::URECPEv4i32) + .value("URHADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::URHADD_ZPmZ_B) + .value("URHADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::URHADD_ZPmZ_D) + .value("URHADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::URHADD_ZPmZ_H) + .value("URHADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URHADD_ZPmZ_S) + .value("URHADDv16i8", LIEF::assembly::aarch64::OPCODE::URHADDv16i8) + .value("URHADDv2i32", LIEF::assembly::aarch64::OPCODE::URHADDv2i32) + .value("URHADDv4i16", LIEF::assembly::aarch64::OPCODE::URHADDv4i16) + .value("URHADDv4i32", LIEF::assembly::aarch64::OPCODE::URHADDv4i32) + .value("URHADDv8i16", LIEF::assembly::aarch64::OPCODE::URHADDv8i16) + .value("URHADDv8i8", LIEF::assembly::aarch64::OPCODE::URHADDv8i8) + .value("URSHLR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::URSHLR_ZPmZ_B) + .value("URSHLR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::URSHLR_ZPmZ_D) + .value("URSHLR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::URSHLR_ZPmZ_H) + .value("URSHLR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URSHLR_ZPmZ_S) + .value("URSHL_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2Z2Z_B) + .value("URSHL_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2Z2Z_D) + .value("URSHL_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2Z2Z_H) + .value("URSHL_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2Z2Z_S) + .value("URSHL_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2ZZ_B) + .value("URSHL_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2ZZ_D) + .value("URSHL_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2ZZ_H) + .value("URSHL_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::URSHL_VG2_2ZZ_S) + .value("URSHL_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4Z4Z_B) + .value("URSHL_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4Z4Z_D) + .value("URSHL_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4Z4Z_H) + .value("URSHL_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4Z4Z_S) + .value("URSHL_VG4_4ZZ_B", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4ZZ_B) + .value("URSHL_VG4_4ZZ_D", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4ZZ_D) + .value("URSHL_VG4_4ZZ_H", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4ZZ_H) + .value("URSHL_VG4_4ZZ_S", LIEF::assembly::aarch64::OPCODE::URSHL_VG4_4ZZ_S) + .value("URSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::URSHL_ZPmZ_B) + .value("URSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::URSHL_ZPmZ_D) + .value("URSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::URSHL_ZPmZ_H) + .value("URSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URSHL_ZPmZ_S) + .value("URSHLv16i8", LIEF::assembly::aarch64::OPCODE::URSHLv16i8) + .value("URSHLv1i64", LIEF::assembly::aarch64::OPCODE::URSHLv1i64) + .value("URSHLv2i32", LIEF::assembly::aarch64::OPCODE::URSHLv2i32) + .value("URSHLv2i64", LIEF::assembly::aarch64::OPCODE::URSHLv2i64) + .value("URSHLv4i16", LIEF::assembly::aarch64::OPCODE::URSHLv4i16) + .value("URSHLv4i32", LIEF::assembly::aarch64::OPCODE::URSHLv4i32) + .value("URSHLv8i16", LIEF::assembly::aarch64::OPCODE::URSHLv8i16) + .value("URSHLv8i8", LIEF::assembly::aarch64::OPCODE::URSHLv8i8) + .value("URSHR_ZPmI_B", LIEF::assembly::aarch64::OPCODE::URSHR_ZPmI_B) + .value("URSHR_ZPmI_D", LIEF::assembly::aarch64::OPCODE::URSHR_ZPmI_D) + .value("URSHR_ZPmI_H", LIEF::assembly::aarch64::OPCODE::URSHR_ZPmI_H) + .value("URSHR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::URSHR_ZPmI_S) + .value("URSHRd", LIEF::assembly::aarch64::OPCODE::URSHRd) + .value("URSHRv16i8_shift", LIEF::assembly::aarch64::OPCODE::URSHRv16i8_shift) + .value("URSHRv2i32_shift", LIEF::assembly::aarch64::OPCODE::URSHRv2i32_shift) + .value("URSHRv2i64_shift", LIEF::assembly::aarch64::OPCODE::URSHRv2i64_shift) + .value("URSHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i16_shift); + opcodes.value("URSHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i32_shift) + .value("URSHRv8i16_shift", LIEF::assembly::aarch64::OPCODE::URSHRv8i16_shift) + .value("URSHRv8i8_shift", LIEF::assembly::aarch64::OPCODE::URSHRv8i8_shift) + .value("URSQRTE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URSQRTE_ZPmZ_S) + .value("URSQRTE_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::URSQRTE_ZPzZ_S) + .value("URSQRTEv2i32", LIEF::assembly::aarch64::OPCODE::URSQRTEv2i32) + .value("URSQRTEv4i32", LIEF::assembly::aarch64::OPCODE::URSQRTEv4i32) + .value("URSRA_ZZI_B", LIEF::assembly::aarch64::OPCODE::URSRA_ZZI_B) + .value("URSRA_ZZI_D", LIEF::assembly::aarch64::OPCODE::URSRA_ZZI_D) + .value("URSRA_ZZI_H", LIEF::assembly::aarch64::OPCODE::URSRA_ZZI_H) + .value("URSRA_ZZI_S", LIEF::assembly::aarch64::OPCODE::URSRA_ZZI_S) + .value("URSRAd", LIEF::assembly::aarch64::OPCODE::URSRAd) + .value("URSRAv16i8_shift", LIEF::assembly::aarch64::OPCODE::URSRAv16i8_shift) + .value("URSRAv2i32_shift", LIEF::assembly::aarch64::OPCODE::URSRAv2i32_shift) + .value("URSRAv2i64_shift", LIEF::assembly::aarch64::OPCODE::URSRAv2i64_shift) + .value("URSRAv4i16_shift", LIEF::assembly::aarch64::OPCODE::URSRAv4i16_shift) + .value("URSRAv4i32_shift", LIEF::assembly::aarch64::OPCODE::URSRAv4i32_shift) + .value("URSRAv8i16_shift", LIEF::assembly::aarch64::OPCODE::URSRAv8i16_shift) + .value("URSRAv8i8_shift", LIEF::assembly::aarch64::OPCODE::URSRAv8i8_shift) + .value("USDOT_VG2_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2Z2Z_BToS) + .value("USDOT_VG2_M2ZZI_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2ZZI_BToS) + .value("USDOT_VG2_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG2_M2ZZ_BToS) + .value("USDOT_VG4_M4Z4Z_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4Z4Z_BToS) + .value("USDOT_VG4_M4ZZI_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4ZZI_BToS) + .value("USDOT_VG4_M4ZZ_BToS", LIEF::assembly::aarch64::OPCODE::USDOT_VG4_M4ZZ_BToS) + .value("USDOT_ZZZ", LIEF::assembly::aarch64::OPCODE::USDOT_ZZZ) + .value("USDOT_ZZZI", LIEF::assembly::aarch64::OPCODE::USDOT_ZZZI) + .value("USDOTlanev16i8", LIEF::assembly::aarch64::OPCODE::USDOTlanev16i8) + .value("USDOTlanev8i8", LIEF::assembly::aarch64::OPCODE::USDOTlanev8i8) + .value("USDOTv16i8", LIEF::assembly::aarch64::OPCODE::USDOTv16i8) + .value("USDOTv8i8", LIEF::assembly::aarch64::OPCODE::USDOTv8i8) + .value("USHLLB_ZZI_D", LIEF::assembly::aarch64::OPCODE::USHLLB_ZZI_D) + .value("USHLLB_ZZI_H", LIEF::assembly::aarch64::OPCODE::USHLLB_ZZI_H) + .value("USHLLB_ZZI_S", LIEF::assembly::aarch64::OPCODE::USHLLB_ZZI_S) + .value("USHLLT_ZZI_D", LIEF::assembly::aarch64::OPCODE::USHLLT_ZZI_D) + .value("USHLLT_ZZI_H", LIEF::assembly::aarch64::OPCODE::USHLLT_ZZI_H) + .value("USHLLT_ZZI_S", LIEF::assembly::aarch64::OPCODE::USHLLT_ZZI_S) + .value("USHLLv16i8_shift", LIEF::assembly::aarch64::OPCODE::USHLLv16i8_shift) + .value("USHLLv2i32_shift", LIEF::assembly::aarch64::OPCODE::USHLLv2i32_shift) + .value("USHLLv4i16_shift", LIEF::assembly::aarch64::OPCODE::USHLLv4i16_shift) + .value("USHLLv4i32_shift", LIEF::assembly::aarch64::OPCODE::USHLLv4i32_shift) + .value("USHLLv8i16_shift", LIEF::assembly::aarch64::OPCODE::USHLLv8i16_shift) + .value("USHLLv8i8_shift", LIEF::assembly::aarch64::OPCODE::USHLLv8i8_shift) + .value("USHLv16i8", LIEF::assembly::aarch64::OPCODE::USHLv16i8) + .value("USHLv1i64", LIEF::assembly::aarch64::OPCODE::USHLv1i64) + .value("USHLv2i32", LIEF::assembly::aarch64::OPCODE::USHLv2i32) + .value("USHLv2i64", LIEF::assembly::aarch64::OPCODE::USHLv2i64) + .value("USHLv4i16", LIEF::assembly::aarch64::OPCODE::USHLv4i16) + .value("USHLv4i32", LIEF::assembly::aarch64::OPCODE::USHLv4i32) + .value("USHLv8i16", LIEF::assembly::aarch64::OPCODE::USHLv8i16) + .value("USHLv8i8", LIEF::assembly::aarch64::OPCODE::USHLv8i8) + .value("USHRd", LIEF::assembly::aarch64::OPCODE::USHRd) + .value("USHRv16i8_shift", LIEF::assembly::aarch64::OPCODE::USHRv16i8_shift) + .value("USHRv2i32_shift", LIEF::assembly::aarch64::OPCODE::USHRv2i32_shift) + .value("USHRv2i64_shift", LIEF::assembly::aarch64::OPCODE::USHRv2i64_shift) + .value("USHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::USHRv4i16_shift) + .value("USHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::USHRv4i32_shift) + .value("USHRv8i16_shift", LIEF::assembly::aarch64::OPCODE::USHRv8i16_shift) + .value("USHRv8i8_shift", LIEF::assembly::aarch64::OPCODE::USHRv8i8_shift) + .value("USMLALL_MZZI_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_MZZI_BtoS) + .value("USMLALL_MZZ_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_MZZ_BtoS) + .value("USMLALL_VG2_M2Z2Z_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2Z2Z_BtoS) + .value("USMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2ZZI_BtoS) + .value("USMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG2_M2ZZ_BtoS) + .value("USMLALL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4Z4Z_BtoS) + .value("USMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4ZZI_BtoS) + .value("USMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::USMLALL_VG4_M4ZZ_BtoS) + .value("USMMLA", LIEF::assembly::aarch64::OPCODE::USMMLA) + .value("USMMLA_ZZZ", LIEF::assembly::aarch64::OPCODE::USMMLA_ZZZ) + .value("USMOP4A_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2Z2Z_BToS) + .value("USMOP4A_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2Z2Z_HtoD) + .value("USMOP4A_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2ZZ_BToS) + .value("USMOP4A_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4A_M2ZZ_HtoD) + .value("USMOP4A_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZ2Z_BToS) + .value("USMOP4A_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZ2Z_HtoD) + .value("USMOP4A_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZZ_BToS) + .value("USMOP4A_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4A_MZZ_HtoD) + .value("USMOP4S_M2Z2Z_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2Z2Z_BToS) + .value("USMOP4S_M2Z2Z_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2Z2Z_HtoD) + .value("USMOP4S_M2ZZ_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2ZZ_BToS) + .value("USMOP4S_M2ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4S_M2ZZ_HtoD) + .value("USMOP4S_MZ2Z_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZ2Z_BToS) + .value("USMOP4S_MZ2Z_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZ2Z_HtoD) + .value("USMOP4S_MZZ_BToS", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZZ_BToS) + .value("USMOP4S_MZZ_HtoD", LIEF::assembly::aarch64::OPCODE::USMOP4S_MZZ_HtoD) + .value("USMOPA_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::USMOPA_MPPZZ_D) + .value("USMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::USMOPA_MPPZZ_S) + .value("USMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::USMOPS_MPPZZ_D) + .value("USMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::USMOPS_MPPZZ_S) + .value("USQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::USQADD_ZPmZ_B) + .value("USQADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::USQADD_ZPmZ_D) + .value("USQADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::USQADD_ZPmZ_H) + .value("USQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::USQADD_ZPmZ_S) + .value("USQADDv16i8", LIEF::assembly::aarch64::OPCODE::USQADDv16i8) + .value("USQADDv1i16", LIEF::assembly::aarch64::OPCODE::USQADDv1i16) + .value("USQADDv1i32", LIEF::assembly::aarch64::OPCODE::USQADDv1i32) + .value("USQADDv1i64", LIEF::assembly::aarch64::OPCODE::USQADDv1i64) + .value("USQADDv1i8", LIEF::assembly::aarch64::OPCODE::USQADDv1i8) + .value("USQADDv2i32", LIEF::assembly::aarch64::OPCODE::USQADDv2i32) + .value("USQADDv2i64", LIEF::assembly::aarch64::OPCODE::USQADDv2i64) + .value("USQADDv4i16", LIEF::assembly::aarch64::OPCODE::USQADDv4i16) + .value("USQADDv4i32", LIEF::assembly::aarch64::OPCODE::USQADDv4i32) + .value("USQADDv8i16", LIEF::assembly::aarch64::OPCODE::USQADDv8i16) + .value("USQADDv8i8", LIEF::assembly::aarch64::OPCODE::USQADDv8i8) + .value("USRA_ZZI_B", LIEF::assembly::aarch64::OPCODE::USRA_ZZI_B) + .value("USRA_ZZI_D", LIEF::assembly::aarch64::OPCODE::USRA_ZZI_D) + .value("USRA_ZZI_H", LIEF::assembly::aarch64::OPCODE::USRA_ZZI_H) + .value("USRA_ZZI_S", LIEF::assembly::aarch64::OPCODE::USRA_ZZI_S) + .value("USRAd", LIEF::assembly::aarch64::OPCODE::USRAd) + .value("USRAv16i8_shift", LIEF::assembly::aarch64::OPCODE::USRAv16i8_shift) + .value("USRAv2i32_shift", LIEF::assembly::aarch64::OPCODE::USRAv2i32_shift) + .value("USRAv2i64_shift", LIEF::assembly::aarch64::OPCODE::USRAv2i64_shift) + .value("USRAv4i16_shift", LIEF::assembly::aarch64::OPCODE::USRAv4i16_shift) + .value("USRAv4i32_shift", LIEF::assembly::aarch64::OPCODE::USRAv4i32_shift) + .value("USRAv8i16_shift", LIEF::assembly::aarch64::OPCODE::USRAv8i16_shift) + .value("USRAv8i8_shift", LIEF::assembly::aarch64::OPCODE::USRAv8i8_shift) + .value("USTMOPA_M2ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::USTMOPA_M2ZZZI_BtoS) + .value("USUBLB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::USUBLB_ZZZ_D) + .value("USUBLB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::USUBLB_ZZZ_H) + .value("USUBLB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::USUBLB_ZZZ_S) + .value("USUBLT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::USUBLT_ZZZ_D) + .value("USUBLT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::USUBLT_ZZZ_H) + .value("USUBLT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::USUBLT_ZZZ_S) + .value("USUBLv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::USUBLv16i8_v8i16) + .value("USUBLv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::USUBLv2i32_v2i64) + .value("USUBLv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::USUBLv4i16_v4i32) + .value("USUBLv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::USUBLv4i32_v2i64) + .value("USUBLv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::USUBLv8i16_v4i32) + .value("USUBLv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::USUBLv8i8_v8i16) + .value("USUBWB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::USUBWB_ZZZ_D) + .value("USUBWB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::USUBWB_ZZZ_H) + .value("USUBWB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::USUBWB_ZZZ_S) + .value("USUBWT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::USUBWT_ZZZ_D) + .value("USUBWT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::USUBWT_ZZZ_H) + .value("USUBWT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::USUBWT_ZZZ_S) + .value("USUBWv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::USUBWv16i8_v8i16) + .value("USUBWv2i32_v2i64", LIEF::assembly::aarch64::OPCODE::USUBWv2i32_v2i64) + .value("USUBWv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::USUBWv4i16_v4i32) + .value("USUBWv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::USUBWv4i32_v2i64) + .value("USUBWv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::USUBWv8i16_v4i32) + .value("USUBWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::USUBWv8i8_v8i16) + .value("USVDOT_VG4_M4ZZI_BToS", LIEF::assembly::aarch64::OPCODE::USVDOT_VG4_M4ZZI_BToS) + .value("UTMOPA_M2ZZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UTMOPA_M2ZZZI_BtoS) + .value("UTMOPA_M2ZZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UTMOPA_M2ZZZI_HtoS) + .value("UUNPKHI_ZZ_D", LIEF::assembly::aarch64::OPCODE::UUNPKHI_ZZ_D) + .value("UUNPKHI_ZZ_H", LIEF::assembly::aarch64::OPCODE::UUNPKHI_ZZ_H) + .value("UUNPKHI_ZZ_S", LIEF::assembly::aarch64::OPCODE::UUNPKHI_ZZ_S) + .value("UUNPKLO_ZZ_D", LIEF::assembly::aarch64::OPCODE::UUNPKLO_ZZ_D) + .value("UUNPKLO_ZZ_H", LIEF::assembly::aarch64::OPCODE::UUNPKLO_ZZ_H) + .value("UUNPKLO_ZZ_S", LIEF::assembly::aarch64::OPCODE::UUNPKLO_ZZ_S) + .value("UUNPK_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::UUNPK_VG2_2ZZ_D) + .value("UUNPK_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::UUNPK_VG2_2ZZ_H) + .value("UUNPK_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::UUNPK_VG2_2ZZ_S) + .value("UUNPK_VG4_4Z2Z_D", LIEF::assembly::aarch64::OPCODE::UUNPK_VG4_4Z2Z_D) + .value("UUNPK_VG4_4Z2Z_H", LIEF::assembly::aarch64::OPCODE::UUNPK_VG4_4Z2Z_H) + .value("UUNPK_VG4_4Z2Z_S", LIEF::assembly::aarch64::OPCODE::UUNPK_VG4_4Z2Z_S) + .value("UVDOT_VG2_M2ZZI_HtoS", LIEF::assembly::aarch64::OPCODE::UVDOT_VG2_M2ZZI_HtoS) + .value("UVDOT_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UVDOT_VG4_M4ZZI_BtoS) + .value("UVDOT_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UVDOT_VG4_M4ZZI_HtoD) + .value("UXTB_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_D) + .value("UXTB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_H) + .value("UXTB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UXTB_ZPmZ_S) + .value("UXTB_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::UXTB_ZPzZ_D) + .value("UXTB_ZPzZ_H", LIEF::assembly::aarch64::OPCODE::UXTB_ZPzZ_H) + .value("UXTB_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::UXTB_ZPzZ_S) + .value("UXTH_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UXTH_ZPmZ_D) + .value("UXTH_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::UXTH_ZPmZ_S) + .value("UXTH_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::UXTH_ZPzZ_D) + .value("UXTH_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::UXTH_ZPzZ_S) + .value("UXTW_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::UXTW_ZPmZ_D) + .value("UXTW_ZPzZ_D", LIEF::assembly::aarch64::OPCODE::UXTW_ZPzZ_D) + .value("UZP1_PPP_B", LIEF::assembly::aarch64::OPCODE::UZP1_PPP_B) + .value("UZP1_PPP_D", LIEF::assembly::aarch64::OPCODE::UZP1_PPP_D) + .value("UZP1_PPP_H", LIEF::assembly::aarch64::OPCODE::UZP1_PPP_H) + .value("UZP1_PPP_S", LIEF::assembly::aarch64::OPCODE::UZP1_PPP_S) + .value("UZP1_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UZP1_ZZZ_B) + .value("UZP1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UZP1_ZZZ_D) + .value("UZP1_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UZP1_ZZZ_H) + .value("UZP1_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::UZP1_ZZZ_Q) + .value("UZP1_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UZP1_ZZZ_S) + .value("UZP1v16i8", LIEF::assembly::aarch64::OPCODE::UZP1v16i8) + .value("UZP1v2i32", LIEF::assembly::aarch64::OPCODE::UZP1v2i32) + .value("UZP1v2i64", LIEF::assembly::aarch64::OPCODE::UZP1v2i64) + .value("UZP1v4i16", LIEF::assembly::aarch64::OPCODE::UZP1v4i16) + .value("UZP1v4i32", LIEF::assembly::aarch64::OPCODE::UZP1v4i32) + .value("UZP1v8i16", LIEF::assembly::aarch64::OPCODE::UZP1v8i16) + .value("UZP1v8i8", LIEF::assembly::aarch64::OPCODE::UZP1v8i8) + .value("UZP2_PPP_B", LIEF::assembly::aarch64::OPCODE::UZP2_PPP_B) + .value("UZP2_PPP_D", LIEF::assembly::aarch64::OPCODE::UZP2_PPP_D) + .value("UZP2_PPP_H", LIEF::assembly::aarch64::OPCODE::UZP2_PPP_H) + .value("UZP2_PPP_S", LIEF::assembly::aarch64::OPCODE::UZP2_PPP_S) + .value("UZP2_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UZP2_ZZZ_B) + .value("UZP2_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UZP2_ZZZ_D) + .value("UZP2_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UZP2_ZZZ_H) + .value("UZP2_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::UZP2_ZZZ_Q) + .value("UZP2_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UZP2_ZZZ_S) + .value("UZP2v16i8", LIEF::assembly::aarch64::OPCODE::UZP2v16i8) + .value("UZP2v2i32", LIEF::assembly::aarch64::OPCODE::UZP2v2i32) + .value("UZP2v2i64", LIEF::assembly::aarch64::OPCODE::UZP2v2i64) + .value("UZP2v4i16", LIEF::assembly::aarch64::OPCODE::UZP2v4i16) + .value("UZP2v4i32", LIEF::assembly::aarch64::OPCODE::UZP2v4i32) + .value("UZP2v8i16", LIEF::assembly::aarch64::OPCODE::UZP2v8i16) + .value("UZP2v8i8", LIEF::assembly::aarch64::OPCODE::UZP2v8i8) + .value("UZPQ1_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UZPQ1_ZZZ_B) + .value("UZPQ1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UZPQ1_ZZZ_D) + .value("UZPQ1_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UZPQ1_ZZZ_H) + .value("UZPQ1_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UZPQ1_ZZZ_S) + .value("UZPQ2_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UZPQ2_ZZZ_B) + .value("UZPQ2_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UZPQ2_ZZZ_D) + .value("UZPQ2_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UZPQ2_ZZZ_H) + .value("UZPQ2_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UZPQ2_ZZZ_S) + .value("UZP_VG2_2ZZZ_B", LIEF::assembly::aarch64::OPCODE::UZP_VG2_2ZZZ_B) + .value("UZP_VG2_2ZZZ_D", LIEF::assembly::aarch64::OPCODE::UZP_VG2_2ZZZ_D) + .value("UZP_VG2_2ZZZ_H", LIEF::assembly::aarch64::OPCODE::UZP_VG2_2ZZZ_H) + .value("UZP_VG2_2ZZZ_Q", LIEF::assembly::aarch64::OPCODE::UZP_VG2_2ZZZ_Q) + .value("UZP_VG2_2ZZZ_S", LIEF::assembly::aarch64::OPCODE::UZP_VG2_2ZZZ_S) + .value("UZP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UZP_VG4_4Z4Z_B) + .value("UZP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UZP_VG4_4Z4Z_D) + .value("UZP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::UZP_VG4_4Z4Z_H) + .value("UZP_VG4_4Z4Z_Q", LIEF::assembly::aarch64::OPCODE::UZP_VG4_4Z4Z_Q) + .value("UZP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::UZP_VG4_4Z4Z_S) + .value("WFET", LIEF::assembly::aarch64::OPCODE::WFET) + .value("WFIT", LIEF::assembly::aarch64::OPCODE::WFIT) + .value("WHILEGE_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGE_2PXX_B) + .value("WHILEGE_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGE_2PXX_D) + .value("WHILEGE_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGE_2PXX_H) + .value("WHILEGE_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGE_2PXX_S) + .value("WHILEGE_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGE_CXX_B) + .value("WHILEGE_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGE_CXX_D) + .value("WHILEGE_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGE_CXX_H) + .value("WHILEGE_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGE_CXX_S) + .value("WHILEGE_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILEGE_PWW_B) + .value("WHILEGE_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILEGE_PWW_D) + .value("WHILEGE_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILEGE_PWW_H) + .value("WHILEGE_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILEGE_PWW_S) + .value("WHILEGE_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGE_PXX_B) + .value("WHILEGE_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGE_PXX_D) + .value("WHILEGE_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGE_PXX_H) + .value("WHILEGE_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGE_PXX_S) + .value("WHILEGT_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_B) + .value("WHILEGT_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_D) + .value("WHILEGT_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_H) + .value("WHILEGT_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_S) + .value("WHILEGT_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_B) + .value("WHILEGT_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_D) + .value("WHILEGT_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_H) + .value("WHILEGT_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_S) + .value("WHILEGT_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_PWW_B) + .value("WHILEGT_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_PWW_D) + .value("WHILEGT_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_PWW_H) + .value("WHILEGT_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_PWW_S) + .value("WHILEGT_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_PXX_B) + .value("WHILEGT_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_PXX_D) + .value("WHILEGT_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_PXX_H) + .value("WHILEGT_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_PXX_S) + .value("WHILEHI_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHI_2PXX_B) + .value("WHILEHI_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHI_2PXX_D) + .value("WHILEHI_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHI_2PXX_H) + .value("WHILEHI_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHI_2PXX_S) + .value("WHILEHI_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHI_CXX_B) + .value("WHILEHI_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHI_CXX_D) + .value("WHILEHI_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHI_CXX_H) + .value("WHILEHI_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHI_CXX_S) + .value("WHILEHI_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILEHI_PWW_B) + .value("WHILEHI_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILEHI_PWW_D) + .value("WHILEHI_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILEHI_PWW_H) + .value("WHILEHI_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILEHI_PWW_S) + .value("WHILEHI_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHI_PXX_B) + .value("WHILEHI_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHI_PXX_D) + .value("WHILEHI_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHI_PXX_H) + .value("WHILEHI_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHI_PXX_S) + .value("WHILEHS_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHS_2PXX_B) + .value("WHILEHS_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHS_2PXX_D) + .value("WHILEHS_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHS_2PXX_H) + .value("WHILEHS_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHS_2PXX_S) + .value("WHILEHS_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHS_CXX_B) + .value("WHILEHS_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHS_CXX_D) + .value("WHILEHS_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHS_CXX_H) + .value("WHILEHS_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHS_CXX_S) + .value("WHILEHS_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILEHS_PWW_B) + .value("WHILEHS_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILEHS_PWW_D) + .value("WHILEHS_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILEHS_PWW_H) + .value("WHILEHS_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILEHS_PWW_S) + .value("WHILEHS_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEHS_PXX_B) + .value("WHILEHS_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEHS_PXX_D) + .value("WHILEHS_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEHS_PXX_H) + .value("WHILEHS_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEHS_PXX_S) + .value("WHILELE_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELE_2PXX_B) + .value("WHILELE_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELE_2PXX_D) + .value("WHILELE_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELE_2PXX_H) + .value("WHILELE_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELE_2PXX_S) + .value("WHILELE_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILELE_CXX_B) + .value("WHILELE_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILELE_CXX_D) + .value("WHILELE_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILELE_CXX_H) + .value("WHILELE_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILELE_CXX_S) + .value("WHILELE_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_B) + .value("WHILELE_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_D) + .value("WHILELE_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_H) + .value("WHILELE_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_S) + .value("WHILELE_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_B); + opcodes.value("WHILELE_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_D) + .value("WHILELE_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_H) + .value("WHILELE_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_S) + .value("WHILELO_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELO_2PXX_B) + .value("WHILELO_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELO_2PXX_D) + .value("WHILELO_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELO_2PXX_H) + .value("WHILELO_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELO_2PXX_S) + .value("WHILELO_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILELO_CXX_B) + .value("WHILELO_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILELO_CXX_D) + .value("WHILELO_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILELO_CXX_H) + .value("WHILELO_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILELO_CXX_S) + .value("WHILELO_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILELO_PWW_B) + .value("WHILELO_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILELO_PWW_D) + .value("WHILELO_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILELO_PWW_H) + .value("WHILELO_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILELO_PWW_S) + .value("WHILELO_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELO_PXX_B) + .value("WHILELO_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELO_PXX_D) + .value("WHILELO_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELO_PXX_H) + .value("WHILELO_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELO_PXX_S) + .value("WHILELS_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELS_2PXX_B) + .value("WHILELS_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELS_2PXX_D) + .value("WHILELS_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELS_2PXX_H) + .value("WHILELS_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELS_2PXX_S) + .value("WHILELS_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILELS_CXX_B) + .value("WHILELS_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILELS_CXX_D) + .value("WHILELS_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILELS_CXX_H) + .value("WHILELS_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILELS_CXX_S) + .value("WHILELS_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILELS_PWW_B) + .value("WHILELS_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILELS_PWW_D) + .value("WHILELS_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILELS_PWW_H) + .value("WHILELS_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILELS_PWW_S) + .value("WHILELS_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELS_PXX_B) + .value("WHILELS_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELS_PXX_D) + .value("WHILELS_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELS_PXX_H) + .value("WHILELS_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELS_PXX_S) + .value("WHILELT_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELT_2PXX_B) + .value("WHILELT_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELT_2PXX_D) + .value("WHILELT_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELT_2PXX_H) + .value("WHILELT_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELT_2PXX_S) + .value("WHILELT_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILELT_CXX_B) + .value("WHILELT_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILELT_CXX_D) + .value("WHILELT_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILELT_CXX_H) + .value("WHILELT_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILELT_CXX_S) + .value("WHILELT_PWW_B", LIEF::assembly::aarch64::OPCODE::WHILELT_PWW_B) + .value("WHILELT_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILELT_PWW_D) + .value("WHILELT_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILELT_PWW_H) + .value("WHILELT_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILELT_PWW_S) + .value("WHILELT_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELT_PXX_B) + .value("WHILELT_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELT_PXX_D) + .value("WHILELT_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELT_PXX_H) + .value("WHILELT_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELT_PXX_S) + .value("WHILERW_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILERW_PXX_B) + .value("WHILERW_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILERW_PXX_D) + .value("WHILERW_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILERW_PXX_H) + .value("WHILERW_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILERW_PXX_S) + .value("WHILEWR_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEWR_PXX_B) + .value("WHILEWR_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEWR_PXX_D) + .value("WHILEWR_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEWR_PXX_H) + .value("WHILEWR_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEWR_PXX_S) + .value("WRFFR", LIEF::assembly::aarch64::OPCODE::WRFFR) + .value("XAFLAG", LIEF::assembly::aarch64::OPCODE::XAFLAG) + .value("XAR", LIEF::assembly::aarch64::OPCODE::XAR) + .value("XAR_ZZZI_B", LIEF::assembly::aarch64::OPCODE::XAR_ZZZI_B) + .value("XAR_ZZZI_D", LIEF::assembly::aarch64::OPCODE::XAR_ZZZI_D) + .value("XAR_ZZZI_H", LIEF::assembly::aarch64::OPCODE::XAR_ZZZI_H) + .value("XAR_ZZZI_S", LIEF::assembly::aarch64::OPCODE::XAR_ZZZI_S) + .value("XPACD", LIEF::assembly::aarch64::OPCODE::XPACD) + .value("XPACI", LIEF::assembly::aarch64::OPCODE::XPACI) + .value("XPACLRI", LIEF::assembly::aarch64::OPCODE::XPACLRI) + .value("XTNv16i8", LIEF::assembly::aarch64::OPCODE::XTNv16i8) + .value("XTNv2i32", LIEF::assembly::aarch64::OPCODE::XTNv2i32) + .value("XTNv4i16", LIEF::assembly::aarch64::OPCODE::XTNv4i16) + .value("XTNv4i32", LIEF::assembly::aarch64::OPCODE::XTNv4i32) + .value("XTNv8i16", LIEF::assembly::aarch64::OPCODE::XTNv8i16) + .value("XTNv8i8", LIEF::assembly::aarch64::OPCODE::XTNv8i8) + .value("ZERO_M", LIEF::assembly::aarch64::OPCODE::ZERO_M) + .value("ZERO_MXI_2Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_2Z) + .value("ZERO_MXI_4Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_4Z) + .value("ZERO_MXI_VG2_2Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_2Z) + .value("ZERO_MXI_VG2_4Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_4Z) + .value("ZERO_MXI_VG2_Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG2_Z) + .value("ZERO_MXI_VG4_2Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_2Z) + .value("ZERO_MXI_VG4_4Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_4Z) + .value("ZERO_MXI_VG4_Z", LIEF::assembly::aarch64::OPCODE::ZERO_MXI_VG4_Z) + .value("ZERO_T", LIEF::assembly::aarch64::OPCODE::ZERO_T) + .value("ZIP1_PPP_B", LIEF::assembly::aarch64::OPCODE::ZIP1_PPP_B) + .value("ZIP1_PPP_D", LIEF::assembly::aarch64::OPCODE::ZIP1_PPP_D) + .value("ZIP1_PPP_H", LIEF::assembly::aarch64::OPCODE::ZIP1_PPP_H) + .value("ZIP1_PPP_S", LIEF::assembly::aarch64::OPCODE::ZIP1_PPP_S) + .value("ZIP1_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ZIP1_ZZZ_B) + .value("ZIP1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ZIP1_ZZZ_D) + .value("ZIP1_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ZIP1_ZZZ_H) + .value("ZIP1_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::ZIP1_ZZZ_Q) + .value("ZIP1_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ZIP1_ZZZ_S) + .value("ZIP1v16i8", LIEF::assembly::aarch64::OPCODE::ZIP1v16i8) + .value("ZIP1v2i32", LIEF::assembly::aarch64::OPCODE::ZIP1v2i32) + .value("ZIP1v2i64", LIEF::assembly::aarch64::OPCODE::ZIP1v2i64) + .value("ZIP1v4i16", LIEF::assembly::aarch64::OPCODE::ZIP1v4i16) + .value("ZIP1v4i32", LIEF::assembly::aarch64::OPCODE::ZIP1v4i32) + .value("ZIP1v8i16", LIEF::assembly::aarch64::OPCODE::ZIP1v8i16) + .value("ZIP1v8i8", LIEF::assembly::aarch64::OPCODE::ZIP1v8i8) + .value("ZIP2_PPP_B", LIEF::assembly::aarch64::OPCODE::ZIP2_PPP_B) + .value("ZIP2_PPP_D", LIEF::assembly::aarch64::OPCODE::ZIP2_PPP_D) + .value("ZIP2_PPP_H", LIEF::assembly::aarch64::OPCODE::ZIP2_PPP_H) + .value("ZIP2_PPP_S", LIEF::assembly::aarch64::OPCODE::ZIP2_PPP_S) + .value("ZIP2_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ZIP2_ZZZ_B) + .value("ZIP2_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ZIP2_ZZZ_D) + .value("ZIP2_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ZIP2_ZZZ_H) + .value("ZIP2_ZZZ_Q", LIEF::assembly::aarch64::OPCODE::ZIP2_ZZZ_Q) + .value("ZIP2_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ZIP2_ZZZ_S) + .value("ZIP2v16i8", LIEF::assembly::aarch64::OPCODE::ZIP2v16i8) + .value("ZIP2v2i32", LIEF::assembly::aarch64::OPCODE::ZIP2v2i32) + .value("ZIP2v2i64", LIEF::assembly::aarch64::OPCODE::ZIP2v2i64) + .value("ZIP2v4i16", LIEF::assembly::aarch64::OPCODE::ZIP2v4i16) + .value("ZIP2v4i32", LIEF::assembly::aarch64::OPCODE::ZIP2v4i32) + .value("ZIP2v8i16", LIEF::assembly::aarch64::OPCODE::ZIP2v8i16) + .value("ZIP2v8i8", LIEF::assembly::aarch64::OPCODE::ZIP2v8i8) + .value("ZIPQ1_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ZIPQ1_ZZZ_B) + .value("ZIPQ1_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ZIPQ1_ZZZ_D) + .value("ZIPQ1_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ZIPQ1_ZZZ_H) + .value("ZIPQ1_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ZIPQ1_ZZZ_S) + .value("ZIPQ2_ZZZ_B", LIEF::assembly::aarch64::OPCODE::ZIPQ2_ZZZ_B) + .value("ZIPQ2_ZZZ_D", LIEF::assembly::aarch64::OPCODE::ZIPQ2_ZZZ_D) + .value("ZIPQ2_ZZZ_H", LIEF::assembly::aarch64::OPCODE::ZIPQ2_ZZZ_H) + .value("ZIPQ2_ZZZ_S", LIEF::assembly::aarch64::OPCODE::ZIPQ2_ZZZ_S) + .value("ZIP_VG2_2ZZZ_B", LIEF::assembly::aarch64::OPCODE::ZIP_VG2_2ZZZ_B) + .value("ZIP_VG2_2ZZZ_D", LIEF::assembly::aarch64::OPCODE::ZIP_VG2_2ZZZ_D) + .value("ZIP_VG2_2ZZZ_H", LIEF::assembly::aarch64::OPCODE::ZIP_VG2_2ZZZ_H) + .value("ZIP_VG2_2ZZZ_Q", LIEF::assembly::aarch64::OPCODE::ZIP_VG2_2ZZZ_Q) + .value("ZIP_VG2_2ZZZ_S", LIEF::assembly::aarch64::OPCODE::ZIP_VG2_2ZZZ_S) + .value("ZIP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::ZIP_VG4_4Z4Z_B) + .value("ZIP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::ZIP_VG4_4Z4Z_D) + .value("ZIP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::ZIP_VG4_4Z4Z_H) + .value("ZIP_VG4_4Z4Z_Q", LIEF::assembly::aarch64::OPCODE::ZIP_VG4_4Z4Z_Q) + .value("ZIP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::ZIP_VG4_4Z4Z_S) + .value("INSTRUCTION_LIST_END", LIEF::assembly::aarch64::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/pyOperand.cpp b/vendor/lief/api/python/src/asm/aarch64/pyOperand.cpp new file mode 100644 index 0000000..edaa90f --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/aarch64/Operand.hpp" + +#include "asm/aarch64/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::aarch64::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for an AArch64 instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(aarch64::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/aarch64/pyRegister.cpp b/vendor/lief/api/python/src/asm/aarch64/pyRegister.cpp new file mode 100644 index 0000000..bdfa16a --- /dev/null +++ b/vendor/lief/api/python/src/asm/aarch64/pyRegister.cpp @@ -0,0 +1,2544 @@ +#include "asm/aarch64/init.hpp" + +#include "LIEF/asm/aarch64/registers.hpp" + +namespace LIEF::assembly::aarch64::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::aarch64::REG::NoRegister) + .value("FFR", LIEF::assembly::aarch64::REG::FFR) + .value("FP", LIEF::assembly::aarch64::REG::FP) + .value("FPCR", LIEF::assembly::aarch64::REG::FPCR) + .value("FPMR", LIEF::assembly::aarch64::REG::FPMR) + .value("FPSR", LIEF::assembly::aarch64::REG::FPSR) + .value("LR", LIEF::assembly::aarch64::REG::LR) + .value("NZCV", LIEF::assembly::aarch64::REG::NZCV) + .value("SP", LIEF::assembly::aarch64::REG::SP) + .value("VG", LIEF::assembly::aarch64::REG::VG) + .value("WSP", LIEF::assembly::aarch64::REG::WSP) + .value("WSP_HI", LIEF::assembly::aarch64::REG::WSP_HI) + .value("WZR", LIEF::assembly::aarch64::REG::WZR) + .value("WZR_HI", LIEF::assembly::aarch64::REG::WZR_HI) + .value("XZR", LIEF::assembly::aarch64::REG::XZR) + .value("ZA", LIEF::assembly::aarch64::REG::ZA) + .value("B0", LIEF::assembly::aarch64::REG::B0) + .value("B1", LIEF::assembly::aarch64::REG::B1) + .value("B2", LIEF::assembly::aarch64::REG::B2) + .value("B3", LIEF::assembly::aarch64::REG::B3) + .value("B4", LIEF::assembly::aarch64::REG::B4) + .value("B5", LIEF::assembly::aarch64::REG::B5) + .value("B6", LIEF::assembly::aarch64::REG::B6) + .value("B7", LIEF::assembly::aarch64::REG::B7) + .value("B8", LIEF::assembly::aarch64::REG::B8) + .value("B9", LIEF::assembly::aarch64::REG::B9) + .value("B10", LIEF::assembly::aarch64::REG::B10) + .value("B11", LIEF::assembly::aarch64::REG::B11) + .value("B12", LIEF::assembly::aarch64::REG::B12) + .value("B13", LIEF::assembly::aarch64::REG::B13) + .value("B14", LIEF::assembly::aarch64::REG::B14) + .value("B15", LIEF::assembly::aarch64::REG::B15) + .value("B16", LIEF::assembly::aarch64::REG::B16) + .value("B17", LIEF::assembly::aarch64::REG::B17) + .value("B18", LIEF::assembly::aarch64::REG::B18) + .value("B19", LIEF::assembly::aarch64::REG::B19) + .value("B20", LIEF::assembly::aarch64::REG::B20) + .value("B21", LIEF::assembly::aarch64::REG::B21) + .value("B22", LIEF::assembly::aarch64::REG::B22) + .value("B23", LIEF::assembly::aarch64::REG::B23) + .value("B24", LIEF::assembly::aarch64::REG::B24) + .value("B25", LIEF::assembly::aarch64::REG::B25) + .value("B26", LIEF::assembly::aarch64::REG::B26) + .value("B27", LIEF::assembly::aarch64::REG::B27) + .value("B28", LIEF::assembly::aarch64::REG::B28) + .value("B29", LIEF::assembly::aarch64::REG::B29) + .value("B30", LIEF::assembly::aarch64::REG::B30) + .value("B31", LIEF::assembly::aarch64::REG::B31) + .value("D0", LIEF::assembly::aarch64::REG::D0) + .value("D1", LIEF::assembly::aarch64::REG::D1) + .value("D2", LIEF::assembly::aarch64::REG::D2) + .value("D3", LIEF::assembly::aarch64::REG::D3) + .value("D4", LIEF::assembly::aarch64::REG::D4) + .value("D5", LIEF::assembly::aarch64::REG::D5) + .value("D6", LIEF::assembly::aarch64::REG::D6) + .value("D7", LIEF::assembly::aarch64::REG::D7) + .value("D8", LIEF::assembly::aarch64::REG::D8) + .value("D9", LIEF::assembly::aarch64::REG::D9) + .value("D10", LIEF::assembly::aarch64::REG::D10) + .value("D11", LIEF::assembly::aarch64::REG::D11) + .value("D12", LIEF::assembly::aarch64::REG::D12) + .value("D13", LIEF::assembly::aarch64::REG::D13) + .value("D14", LIEF::assembly::aarch64::REG::D14) + .value("D15", LIEF::assembly::aarch64::REG::D15) + .value("D16", LIEF::assembly::aarch64::REG::D16) + .value("D17", LIEF::assembly::aarch64::REG::D17) + .value("D18", LIEF::assembly::aarch64::REG::D18) + .value("D19", LIEF::assembly::aarch64::REG::D19) + .value("D20", LIEF::assembly::aarch64::REG::D20) + .value("D21", LIEF::assembly::aarch64::REG::D21) + .value("D22", LIEF::assembly::aarch64::REG::D22) + .value("D23", LIEF::assembly::aarch64::REG::D23) + .value("D24", LIEF::assembly::aarch64::REG::D24) + .value("D25", LIEF::assembly::aarch64::REG::D25) + .value("D26", LIEF::assembly::aarch64::REG::D26) + .value("D27", LIEF::assembly::aarch64::REG::D27) + .value("D28", LIEF::assembly::aarch64::REG::D28) + .value("D29", LIEF::assembly::aarch64::REG::D29) + .value("D30", LIEF::assembly::aarch64::REG::D30) + .value("D31", LIEF::assembly::aarch64::REG::D31) + .value("H0", LIEF::assembly::aarch64::REG::H0) + .value("H1", LIEF::assembly::aarch64::REG::H1) + .value("H2", LIEF::assembly::aarch64::REG::H2) + .value("H3", LIEF::assembly::aarch64::REG::H3) + .value("H4", LIEF::assembly::aarch64::REG::H4) + .value("H5", LIEF::assembly::aarch64::REG::H5) + .value("H6", LIEF::assembly::aarch64::REG::H6) + .value("H7", LIEF::assembly::aarch64::REG::H7) + .value("H8", LIEF::assembly::aarch64::REG::H8) + .value("H9", LIEF::assembly::aarch64::REG::H9) + .value("H10", LIEF::assembly::aarch64::REG::H10) + .value("H11", LIEF::assembly::aarch64::REG::H11) + .value("H12", LIEF::assembly::aarch64::REG::H12) + .value("H13", LIEF::assembly::aarch64::REG::H13) + .value("H14", LIEF::assembly::aarch64::REG::H14) + .value("H15", LIEF::assembly::aarch64::REG::H15) + .value("H16", LIEF::assembly::aarch64::REG::H16) + .value("H17", LIEF::assembly::aarch64::REG::H17) + .value("H18", LIEF::assembly::aarch64::REG::H18) + .value("H19", LIEF::assembly::aarch64::REG::H19) + .value("H20", LIEF::assembly::aarch64::REG::H20) + .value("H21", LIEF::assembly::aarch64::REG::H21) + .value("H22", LIEF::assembly::aarch64::REG::H22) + .value("H23", LIEF::assembly::aarch64::REG::H23) + .value("H24", LIEF::assembly::aarch64::REG::H24) + .value("H25", LIEF::assembly::aarch64::REG::H25) + .value("H26", LIEF::assembly::aarch64::REG::H26) + .value("H27", LIEF::assembly::aarch64::REG::H27) + .value("H28", LIEF::assembly::aarch64::REG::H28) + .value("H29", LIEF::assembly::aarch64::REG::H29) + .value("H30", LIEF::assembly::aarch64::REG::H30) + .value("H31", LIEF::assembly::aarch64::REG::H31) + .value("P0", LIEF::assembly::aarch64::REG::P0) + .value("P1", LIEF::assembly::aarch64::REG::P1) + .value("P2", LIEF::assembly::aarch64::REG::P2) + .value("P3", LIEF::assembly::aarch64::REG::P3) + .value("P4", LIEF::assembly::aarch64::REG::P4) + .value("P5", LIEF::assembly::aarch64::REG::P5) + .value("P6", LIEF::assembly::aarch64::REG::P6) + .value("P7", LIEF::assembly::aarch64::REG::P7) + .value("P8", LIEF::assembly::aarch64::REG::P8) + .value("P9", LIEF::assembly::aarch64::REG::P9) + .value("P10", LIEF::assembly::aarch64::REG::P10) + .value("P11", LIEF::assembly::aarch64::REG::P11) + .value("P12", LIEF::assembly::aarch64::REG::P12) + .value("P13", LIEF::assembly::aarch64::REG::P13) + .value("P14", LIEF::assembly::aarch64::REG::P14) + .value("P15", LIEF::assembly::aarch64::REG::P15) + .value("PN0", LIEF::assembly::aarch64::REG::PN0) + .value("PN1", LIEF::assembly::aarch64::REG::PN1) + .value("PN2", LIEF::assembly::aarch64::REG::PN2) + .value("PN3", LIEF::assembly::aarch64::REG::PN3) + .value("PN4", LIEF::assembly::aarch64::REG::PN4) + .value("PN5", LIEF::assembly::aarch64::REG::PN5) + .value("PN6", LIEF::assembly::aarch64::REG::PN6) + .value("PN7", LIEF::assembly::aarch64::REG::PN7) + .value("PN8", LIEF::assembly::aarch64::REG::PN8) + .value("PN9", LIEF::assembly::aarch64::REG::PN9) + .value("PN10", LIEF::assembly::aarch64::REG::PN10) + .value("PN11", LIEF::assembly::aarch64::REG::PN11) + .value("PN12", LIEF::assembly::aarch64::REG::PN12) + .value("PN13", LIEF::assembly::aarch64::REG::PN13) + .value("PN14", LIEF::assembly::aarch64::REG::PN14) + .value("PN15", LIEF::assembly::aarch64::REG::PN15) + .value("Q0", LIEF::assembly::aarch64::REG::Q0) + .value("Q1", LIEF::assembly::aarch64::REG::Q1) + .value("Q2", LIEF::assembly::aarch64::REG::Q2) + .value("Q3", LIEF::assembly::aarch64::REG::Q3) + .value("Q4", LIEF::assembly::aarch64::REG::Q4) + .value("Q5", LIEF::assembly::aarch64::REG::Q5) + .value("Q6", LIEF::assembly::aarch64::REG::Q6) + .value("Q7", LIEF::assembly::aarch64::REG::Q7) + .value("Q8", LIEF::assembly::aarch64::REG::Q8) + .value("Q9", LIEF::assembly::aarch64::REG::Q9) + .value("Q10", LIEF::assembly::aarch64::REG::Q10) + .value("Q11", LIEF::assembly::aarch64::REG::Q11) + .value("Q12", LIEF::assembly::aarch64::REG::Q12) + .value("Q13", LIEF::assembly::aarch64::REG::Q13) + .value("Q14", LIEF::assembly::aarch64::REG::Q14) + .value("Q15", LIEF::assembly::aarch64::REG::Q15) + .value("Q16", LIEF::assembly::aarch64::REG::Q16) + .value("Q17", LIEF::assembly::aarch64::REG::Q17) + .value("Q18", LIEF::assembly::aarch64::REG::Q18) + .value("Q19", LIEF::assembly::aarch64::REG::Q19) + .value("Q20", LIEF::assembly::aarch64::REG::Q20) + .value("Q21", LIEF::assembly::aarch64::REG::Q21) + .value("Q22", LIEF::assembly::aarch64::REG::Q22) + .value("Q23", LIEF::assembly::aarch64::REG::Q23) + .value("Q24", LIEF::assembly::aarch64::REG::Q24) + .value("Q25", LIEF::assembly::aarch64::REG::Q25) + .value("Q26", LIEF::assembly::aarch64::REG::Q26) + .value("Q27", LIEF::assembly::aarch64::REG::Q27) + .value("Q28", LIEF::assembly::aarch64::REG::Q28) + .value("Q29", LIEF::assembly::aarch64::REG::Q29) + .value("Q30", LIEF::assembly::aarch64::REG::Q30) + .value("Q31", LIEF::assembly::aarch64::REG::Q31) + .value("S0", LIEF::assembly::aarch64::REG::S0) + .value("S1", LIEF::assembly::aarch64::REG::S1) + .value("S2", LIEF::assembly::aarch64::REG::S2) + .value("S3", LIEF::assembly::aarch64::REG::S3) + .value("S4", LIEF::assembly::aarch64::REG::S4) + .value("S5", LIEF::assembly::aarch64::REG::S5) + .value("S6", LIEF::assembly::aarch64::REG::S6) + .value("S7", LIEF::assembly::aarch64::REG::S7) + .value("S8", LIEF::assembly::aarch64::REG::S8) + .value("S9", LIEF::assembly::aarch64::REG::S9) + .value("S10", LIEF::assembly::aarch64::REG::S10) + .value("S11", LIEF::assembly::aarch64::REG::S11) + .value("S12", LIEF::assembly::aarch64::REG::S12) + .value("S13", LIEF::assembly::aarch64::REG::S13) + .value("S14", LIEF::assembly::aarch64::REG::S14) + .value("S15", LIEF::assembly::aarch64::REG::S15) + .value("S16", LIEF::assembly::aarch64::REG::S16) + .value("S17", LIEF::assembly::aarch64::REG::S17) + .value("S18", LIEF::assembly::aarch64::REG::S18) + .value("S19", LIEF::assembly::aarch64::REG::S19) + .value("S20", LIEF::assembly::aarch64::REG::S20) + .value("S21", LIEF::assembly::aarch64::REG::S21) + .value("S22", LIEF::assembly::aarch64::REG::S22) + .value("S23", LIEF::assembly::aarch64::REG::S23) + .value("S24", LIEF::assembly::aarch64::REG::S24) + .value("S25", LIEF::assembly::aarch64::REG::S25) + .value("S26", LIEF::assembly::aarch64::REG::S26) + .value("S27", LIEF::assembly::aarch64::REG::S27) + .value("S28", LIEF::assembly::aarch64::REG::S28) + .value("S29", LIEF::assembly::aarch64::REG::S29) + .value("S30", LIEF::assembly::aarch64::REG::S30) + .value("S31", LIEF::assembly::aarch64::REG::S31) + .value("W0", LIEF::assembly::aarch64::REG::W0) + .value("W1", LIEF::assembly::aarch64::REG::W1) + .value("W2", LIEF::assembly::aarch64::REG::W2) + .value("W3", LIEF::assembly::aarch64::REG::W3) + .value("W4", LIEF::assembly::aarch64::REG::W4) + .value("W5", LIEF::assembly::aarch64::REG::W5) + .value("W6", LIEF::assembly::aarch64::REG::W6) + .value("W7", LIEF::assembly::aarch64::REG::W7) + .value("W8", LIEF::assembly::aarch64::REG::W8) + .value("W9", LIEF::assembly::aarch64::REG::W9) + .value("W10", LIEF::assembly::aarch64::REG::W10) + .value("W11", LIEF::assembly::aarch64::REG::W11) + .value("W12", LIEF::assembly::aarch64::REG::W12) + .value("W13", LIEF::assembly::aarch64::REG::W13) + .value("W14", LIEF::assembly::aarch64::REG::W14) + .value("W15", LIEF::assembly::aarch64::REG::W15) + .value("W16", LIEF::assembly::aarch64::REG::W16) + .value("W17", LIEF::assembly::aarch64::REG::W17) + .value("W18", LIEF::assembly::aarch64::REG::W18) + .value("W19", LIEF::assembly::aarch64::REG::W19) + .value("W20", LIEF::assembly::aarch64::REG::W20) + .value("W21", LIEF::assembly::aarch64::REG::W21) + .value("W22", LIEF::assembly::aarch64::REG::W22) + .value("W23", LIEF::assembly::aarch64::REG::W23) + .value("W24", LIEF::assembly::aarch64::REG::W24) + .value("W25", LIEF::assembly::aarch64::REG::W25) + .value("W26", LIEF::assembly::aarch64::REG::W26) + .value("W27", LIEF::assembly::aarch64::REG::W27) + .value("W28", LIEF::assembly::aarch64::REG::W28) + .value("W29", LIEF::assembly::aarch64::REG::W29) + .value("W30", LIEF::assembly::aarch64::REG::W30) + .value("X0", LIEF::assembly::aarch64::REG::X0) + .value("X1", LIEF::assembly::aarch64::REG::X1) + .value("X2", LIEF::assembly::aarch64::REG::X2) + .value("X3", LIEF::assembly::aarch64::REG::X3) + .value("X4", LIEF::assembly::aarch64::REG::X4) + .value("X5", LIEF::assembly::aarch64::REG::X5) + .value("X6", LIEF::assembly::aarch64::REG::X6) + .value("X7", LIEF::assembly::aarch64::REG::X7) + .value("X8", LIEF::assembly::aarch64::REG::X8) + .value("X9", LIEF::assembly::aarch64::REG::X9) + .value("X10", LIEF::assembly::aarch64::REG::X10) + .value("X11", LIEF::assembly::aarch64::REG::X11) + .value("X12", LIEF::assembly::aarch64::REG::X12) + .value("X13", LIEF::assembly::aarch64::REG::X13) + .value("X14", LIEF::assembly::aarch64::REG::X14) + .value("X15", LIEF::assembly::aarch64::REG::X15) + .value("X16", LIEF::assembly::aarch64::REG::X16) + .value("X17", LIEF::assembly::aarch64::REG::X17) + .value("X18", LIEF::assembly::aarch64::REG::X18) + .value("X19", LIEF::assembly::aarch64::REG::X19) + .value("X20", LIEF::assembly::aarch64::REG::X20) + .value("X21", LIEF::assembly::aarch64::REG::X21) + .value("X22", LIEF::assembly::aarch64::REG::X22) + .value("X23", LIEF::assembly::aarch64::REG::X23) + .value("X24", LIEF::assembly::aarch64::REG::X24) + .value("X25", LIEF::assembly::aarch64::REG::X25) + .value("X26", LIEF::assembly::aarch64::REG::X26) + .value("X27", LIEF::assembly::aarch64::REG::X27) + .value("X28", LIEF::assembly::aarch64::REG::X28) + .value("Z0", LIEF::assembly::aarch64::REG::Z0) + .value("Z1", LIEF::assembly::aarch64::REG::Z1) + .value("Z2", LIEF::assembly::aarch64::REG::Z2) + .value("Z3", LIEF::assembly::aarch64::REG::Z3) + .value("Z4", LIEF::assembly::aarch64::REG::Z4) + .value("Z5", LIEF::assembly::aarch64::REG::Z5) + .value("Z6", LIEF::assembly::aarch64::REG::Z6) + .value("Z7", LIEF::assembly::aarch64::REG::Z7) + .value("Z8", LIEF::assembly::aarch64::REG::Z8) + .value("Z9", LIEF::assembly::aarch64::REG::Z9) + .value("Z10", LIEF::assembly::aarch64::REG::Z10) + .value("Z11", LIEF::assembly::aarch64::REG::Z11) + .value("Z12", LIEF::assembly::aarch64::REG::Z12) + .value("Z13", LIEF::assembly::aarch64::REG::Z13) + .value("Z14", LIEF::assembly::aarch64::REG::Z14) + .value("Z15", LIEF::assembly::aarch64::REG::Z15) + .value("Z16", LIEF::assembly::aarch64::REG::Z16) + .value("Z17", LIEF::assembly::aarch64::REG::Z17) + .value("Z18", LIEF::assembly::aarch64::REG::Z18) + .value("Z19", LIEF::assembly::aarch64::REG::Z19) + .value("Z20", LIEF::assembly::aarch64::REG::Z20) + .value("Z21", LIEF::assembly::aarch64::REG::Z21) + .value("Z22", LIEF::assembly::aarch64::REG::Z22) + .value("Z23", LIEF::assembly::aarch64::REG::Z23) + .value("Z24", LIEF::assembly::aarch64::REG::Z24) + .value("Z25", LIEF::assembly::aarch64::REG::Z25) + .value("Z26", LIEF::assembly::aarch64::REG::Z26) + .value("Z27", LIEF::assembly::aarch64::REG::Z27) + .value("Z28", LIEF::assembly::aarch64::REG::Z28) + .value("Z29", LIEF::assembly::aarch64::REG::Z29) + .value("Z30", LIEF::assembly::aarch64::REG::Z30) + .value("Z31", LIEF::assembly::aarch64::REG::Z31); + reg.value("ZAB0", LIEF::assembly::aarch64::REG::ZAB0) + .value("ZAD0", LIEF::assembly::aarch64::REG::ZAD0) + .value("ZAD1", LIEF::assembly::aarch64::REG::ZAD1) + .value("ZAD2", LIEF::assembly::aarch64::REG::ZAD2) + .value("ZAD3", LIEF::assembly::aarch64::REG::ZAD3) + .value("ZAD4", LIEF::assembly::aarch64::REG::ZAD4) + .value("ZAD5", LIEF::assembly::aarch64::REG::ZAD5) + .value("ZAD6", LIEF::assembly::aarch64::REG::ZAD6) + .value("ZAD7", LIEF::assembly::aarch64::REG::ZAD7) + .value("ZAH0", LIEF::assembly::aarch64::REG::ZAH0) + .value("ZAH1", LIEF::assembly::aarch64::REG::ZAH1) + .value("ZAQ0", LIEF::assembly::aarch64::REG::ZAQ0) + .value("ZAQ1", LIEF::assembly::aarch64::REG::ZAQ1) + .value("ZAQ2", LIEF::assembly::aarch64::REG::ZAQ2) + .value("ZAQ3", LIEF::assembly::aarch64::REG::ZAQ3) + .value("ZAQ4", LIEF::assembly::aarch64::REG::ZAQ4) + .value("ZAQ5", LIEF::assembly::aarch64::REG::ZAQ5) + .value("ZAQ6", LIEF::assembly::aarch64::REG::ZAQ6) + .value("ZAQ7", LIEF::assembly::aarch64::REG::ZAQ7) + .value("ZAQ8", LIEF::assembly::aarch64::REG::ZAQ8) + .value("ZAQ9", LIEF::assembly::aarch64::REG::ZAQ9) + .value("ZAQ10", LIEF::assembly::aarch64::REG::ZAQ10) + .value("ZAQ11", LIEF::assembly::aarch64::REG::ZAQ11) + .value("ZAQ12", LIEF::assembly::aarch64::REG::ZAQ12) + .value("ZAQ13", LIEF::assembly::aarch64::REG::ZAQ13) + .value("ZAQ14", LIEF::assembly::aarch64::REG::ZAQ14) + .value("ZAQ15", LIEF::assembly::aarch64::REG::ZAQ15) + .value("ZAS0", LIEF::assembly::aarch64::REG::ZAS0) + .value("ZAS1", LIEF::assembly::aarch64::REG::ZAS1) + .value("ZAS2", LIEF::assembly::aarch64::REG::ZAS2) + .value("ZAS3", LIEF::assembly::aarch64::REG::ZAS3) + .value("ZT0", LIEF::assembly::aarch64::REG::ZT0) + .value("B0_HI", LIEF::assembly::aarch64::REG::B0_HI) + .value("B1_HI", LIEF::assembly::aarch64::REG::B1_HI) + .value("B2_HI", LIEF::assembly::aarch64::REG::B2_HI) + .value("B3_HI", LIEF::assembly::aarch64::REG::B3_HI) + .value("B4_HI", LIEF::assembly::aarch64::REG::B4_HI) + .value("B5_HI", LIEF::assembly::aarch64::REG::B5_HI) + .value("B6_HI", LIEF::assembly::aarch64::REG::B6_HI) + .value("B7_HI", LIEF::assembly::aarch64::REG::B7_HI) + .value("B8_HI", LIEF::assembly::aarch64::REG::B8_HI) + .value("B9_HI", LIEF::assembly::aarch64::REG::B9_HI) + .value("B10_HI", LIEF::assembly::aarch64::REG::B10_HI) + .value("B11_HI", LIEF::assembly::aarch64::REG::B11_HI) + .value("B12_HI", LIEF::assembly::aarch64::REG::B12_HI) + .value("B13_HI", LIEF::assembly::aarch64::REG::B13_HI) + .value("B14_HI", LIEF::assembly::aarch64::REG::B14_HI) + .value("B15_HI", LIEF::assembly::aarch64::REG::B15_HI) + .value("B16_HI", LIEF::assembly::aarch64::REG::B16_HI) + .value("B17_HI", LIEF::assembly::aarch64::REG::B17_HI) + .value("B18_HI", LIEF::assembly::aarch64::REG::B18_HI) + .value("B19_HI", LIEF::assembly::aarch64::REG::B19_HI) + .value("B20_HI", LIEF::assembly::aarch64::REG::B20_HI) + .value("B21_HI", LIEF::assembly::aarch64::REG::B21_HI) + .value("B22_HI", LIEF::assembly::aarch64::REG::B22_HI) + .value("B23_HI", LIEF::assembly::aarch64::REG::B23_HI) + .value("B24_HI", LIEF::assembly::aarch64::REG::B24_HI) + .value("B25_HI", LIEF::assembly::aarch64::REG::B25_HI) + .value("B26_HI", LIEF::assembly::aarch64::REG::B26_HI) + .value("B27_HI", LIEF::assembly::aarch64::REG::B27_HI) + .value("B28_HI", LIEF::assembly::aarch64::REG::B28_HI) + .value("B29_HI", LIEF::assembly::aarch64::REG::B29_HI) + .value("B30_HI", LIEF::assembly::aarch64::REG::B30_HI) + .value("B31_HI", LIEF::assembly::aarch64::REG::B31_HI) + .value("D0_HI", LIEF::assembly::aarch64::REG::D0_HI) + .value("D1_HI", LIEF::assembly::aarch64::REG::D1_HI) + .value("D2_HI", LIEF::assembly::aarch64::REG::D2_HI) + .value("D3_HI", LIEF::assembly::aarch64::REG::D3_HI) + .value("D4_HI", LIEF::assembly::aarch64::REG::D4_HI) + .value("D5_HI", LIEF::assembly::aarch64::REG::D5_HI) + .value("D6_HI", LIEF::assembly::aarch64::REG::D6_HI) + .value("D7_HI", LIEF::assembly::aarch64::REG::D7_HI) + .value("D8_HI", LIEF::assembly::aarch64::REG::D8_HI) + .value("D9_HI", LIEF::assembly::aarch64::REG::D9_HI) + .value("D10_HI", LIEF::assembly::aarch64::REG::D10_HI) + .value("D11_HI", LIEF::assembly::aarch64::REG::D11_HI) + .value("D12_HI", LIEF::assembly::aarch64::REG::D12_HI) + .value("D13_HI", LIEF::assembly::aarch64::REG::D13_HI) + .value("D14_HI", LIEF::assembly::aarch64::REG::D14_HI) + .value("D15_HI", LIEF::assembly::aarch64::REG::D15_HI) + .value("D16_HI", LIEF::assembly::aarch64::REG::D16_HI) + .value("D17_HI", LIEF::assembly::aarch64::REG::D17_HI) + .value("D18_HI", LIEF::assembly::aarch64::REG::D18_HI) + .value("D19_HI", LIEF::assembly::aarch64::REG::D19_HI) + .value("D20_HI", LIEF::assembly::aarch64::REG::D20_HI) + .value("D21_HI", LIEF::assembly::aarch64::REG::D21_HI) + .value("D22_HI", LIEF::assembly::aarch64::REG::D22_HI) + .value("D23_HI", LIEF::assembly::aarch64::REG::D23_HI) + .value("D24_HI", LIEF::assembly::aarch64::REG::D24_HI) + .value("D25_HI", LIEF::assembly::aarch64::REG::D25_HI) + .value("D26_HI", LIEF::assembly::aarch64::REG::D26_HI) + .value("D27_HI", LIEF::assembly::aarch64::REG::D27_HI) + .value("D28_HI", LIEF::assembly::aarch64::REG::D28_HI) + .value("D29_HI", LIEF::assembly::aarch64::REG::D29_HI) + .value("D30_HI", LIEF::assembly::aarch64::REG::D30_HI) + .value("D31_HI", LIEF::assembly::aarch64::REG::D31_HI) + .value("H0_HI", LIEF::assembly::aarch64::REG::H0_HI) + .value("H1_HI", LIEF::assembly::aarch64::REG::H1_HI) + .value("H2_HI", LIEF::assembly::aarch64::REG::H2_HI) + .value("H3_HI", LIEF::assembly::aarch64::REG::H3_HI) + .value("H4_HI", LIEF::assembly::aarch64::REG::H4_HI) + .value("H5_HI", LIEF::assembly::aarch64::REG::H5_HI) + .value("H6_HI", LIEF::assembly::aarch64::REG::H6_HI) + .value("H7_HI", LIEF::assembly::aarch64::REG::H7_HI) + .value("H8_HI", LIEF::assembly::aarch64::REG::H8_HI) + .value("H9_HI", LIEF::assembly::aarch64::REG::H9_HI) + .value("H10_HI", LIEF::assembly::aarch64::REG::H10_HI) + .value("H11_HI", LIEF::assembly::aarch64::REG::H11_HI) + .value("H12_HI", LIEF::assembly::aarch64::REG::H12_HI) + .value("H13_HI", LIEF::assembly::aarch64::REG::H13_HI) + .value("H14_HI", LIEF::assembly::aarch64::REG::H14_HI) + .value("H15_HI", LIEF::assembly::aarch64::REG::H15_HI) + .value("H16_HI", LIEF::assembly::aarch64::REG::H16_HI) + .value("H17_HI", LIEF::assembly::aarch64::REG::H17_HI) + .value("H18_HI", LIEF::assembly::aarch64::REG::H18_HI) + .value("H19_HI", LIEF::assembly::aarch64::REG::H19_HI) + .value("H20_HI", LIEF::assembly::aarch64::REG::H20_HI) + .value("H21_HI", LIEF::assembly::aarch64::REG::H21_HI) + .value("H22_HI", LIEF::assembly::aarch64::REG::H22_HI) + .value("H23_HI", LIEF::assembly::aarch64::REG::H23_HI) + .value("H24_HI", LIEF::assembly::aarch64::REG::H24_HI) + .value("H25_HI", LIEF::assembly::aarch64::REG::H25_HI) + .value("H26_HI", LIEF::assembly::aarch64::REG::H26_HI) + .value("H27_HI", LIEF::assembly::aarch64::REG::H27_HI) + .value("H28_HI", LIEF::assembly::aarch64::REG::H28_HI) + .value("H29_HI", LIEF::assembly::aarch64::REG::H29_HI) + .value("H30_HI", LIEF::assembly::aarch64::REG::H30_HI) + .value("H31_HI", LIEF::assembly::aarch64::REG::H31_HI) + .value("Q0_HI", LIEF::assembly::aarch64::REG::Q0_HI) + .value("Q1_HI", LIEF::assembly::aarch64::REG::Q1_HI) + .value("Q2_HI", LIEF::assembly::aarch64::REG::Q2_HI) + .value("Q3_HI", LIEF::assembly::aarch64::REG::Q3_HI) + .value("Q4_HI", LIEF::assembly::aarch64::REG::Q4_HI) + .value("Q5_HI", LIEF::assembly::aarch64::REG::Q5_HI) + .value("Q6_HI", LIEF::assembly::aarch64::REG::Q6_HI) + .value("Q7_HI", LIEF::assembly::aarch64::REG::Q7_HI) + .value("Q8_HI", LIEF::assembly::aarch64::REG::Q8_HI) + .value("Q9_HI", LIEF::assembly::aarch64::REG::Q9_HI) + .value("Q10_HI", LIEF::assembly::aarch64::REG::Q10_HI) + .value("Q11_HI", LIEF::assembly::aarch64::REG::Q11_HI) + .value("Q12_HI", LIEF::assembly::aarch64::REG::Q12_HI) + .value("Q13_HI", LIEF::assembly::aarch64::REG::Q13_HI) + .value("Q14_HI", LIEF::assembly::aarch64::REG::Q14_HI) + .value("Q15_HI", LIEF::assembly::aarch64::REG::Q15_HI) + .value("Q16_HI", LIEF::assembly::aarch64::REG::Q16_HI) + .value("Q17_HI", LIEF::assembly::aarch64::REG::Q17_HI) + .value("Q18_HI", LIEF::assembly::aarch64::REG::Q18_HI) + .value("Q19_HI", LIEF::assembly::aarch64::REG::Q19_HI) + .value("Q20_HI", LIEF::assembly::aarch64::REG::Q20_HI) + .value("Q21_HI", LIEF::assembly::aarch64::REG::Q21_HI) + .value("Q22_HI", LIEF::assembly::aarch64::REG::Q22_HI) + .value("Q23_HI", LIEF::assembly::aarch64::REG::Q23_HI) + .value("Q24_HI", LIEF::assembly::aarch64::REG::Q24_HI) + .value("Q25_HI", LIEF::assembly::aarch64::REG::Q25_HI) + .value("Q26_HI", LIEF::assembly::aarch64::REG::Q26_HI) + .value("Q27_HI", LIEF::assembly::aarch64::REG::Q27_HI) + .value("Q28_HI", LIEF::assembly::aarch64::REG::Q28_HI) + .value("Q29_HI", LIEF::assembly::aarch64::REG::Q29_HI) + .value("Q30_HI", LIEF::assembly::aarch64::REG::Q30_HI) + .value("Q31_HI", LIEF::assembly::aarch64::REG::Q31_HI) + .value("S0_HI", LIEF::assembly::aarch64::REG::S0_HI) + .value("S1_HI", LIEF::assembly::aarch64::REG::S1_HI) + .value("S2_HI", LIEF::assembly::aarch64::REG::S2_HI) + .value("S3_HI", LIEF::assembly::aarch64::REG::S3_HI) + .value("S4_HI", LIEF::assembly::aarch64::REG::S4_HI) + .value("S5_HI", LIEF::assembly::aarch64::REG::S5_HI) + .value("S6_HI", LIEF::assembly::aarch64::REG::S6_HI) + .value("S7_HI", LIEF::assembly::aarch64::REG::S7_HI) + .value("S8_HI", LIEF::assembly::aarch64::REG::S8_HI) + .value("S9_HI", LIEF::assembly::aarch64::REG::S9_HI) + .value("S10_HI", LIEF::assembly::aarch64::REG::S10_HI) + .value("S11_HI", LIEF::assembly::aarch64::REG::S11_HI) + .value("S12_HI", LIEF::assembly::aarch64::REG::S12_HI) + .value("S13_HI", LIEF::assembly::aarch64::REG::S13_HI) + .value("S14_HI", LIEF::assembly::aarch64::REG::S14_HI) + .value("S15_HI", LIEF::assembly::aarch64::REG::S15_HI) + .value("S16_HI", LIEF::assembly::aarch64::REG::S16_HI) + .value("S17_HI", LIEF::assembly::aarch64::REG::S17_HI) + .value("S18_HI", LIEF::assembly::aarch64::REG::S18_HI) + .value("S19_HI", LIEF::assembly::aarch64::REG::S19_HI) + .value("S20_HI", LIEF::assembly::aarch64::REG::S20_HI) + .value("S21_HI", LIEF::assembly::aarch64::REG::S21_HI) + .value("S22_HI", LIEF::assembly::aarch64::REG::S22_HI) + .value("S23_HI", LIEF::assembly::aarch64::REG::S23_HI) + .value("S24_HI", LIEF::assembly::aarch64::REG::S24_HI) + .value("S25_HI", LIEF::assembly::aarch64::REG::S25_HI) + .value("S26_HI", LIEF::assembly::aarch64::REG::S26_HI) + .value("S27_HI", LIEF::assembly::aarch64::REG::S27_HI) + .value("S28_HI", LIEF::assembly::aarch64::REG::S28_HI) + .value("S29_HI", LIEF::assembly::aarch64::REG::S29_HI) + .value("S30_HI", LIEF::assembly::aarch64::REG::S30_HI) + .value("S31_HI", LIEF::assembly::aarch64::REG::S31_HI) + .value("W0_HI", LIEF::assembly::aarch64::REG::W0_HI) + .value("W1_HI", LIEF::assembly::aarch64::REG::W1_HI) + .value("W2_HI", LIEF::assembly::aarch64::REG::W2_HI) + .value("W3_HI", LIEF::assembly::aarch64::REG::W3_HI) + .value("W4_HI", LIEF::assembly::aarch64::REG::W4_HI) + .value("W5_HI", LIEF::assembly::aarch64::REG::W5_HI) + .value("W6_HI", LIEF::assembly::aarch64::REG::W6_HI) + .value("W7_HI", LIEF::assembly::aarch64::REG::W7_HI) + .value("W8_HI", LIEF::assembly::aarch64::REG::W8_HI) + .value("W9_HI", LIEF::assembly::aarch64::REG::W9_HI) + .value("W10_HI", LIEF::assembly::aarch64::REG::W10_HI) + .value("W11_HI", LIEF::assembly::aarch64::REG::W11_HI) + .value("W12_HI", LIEF::assembly::aarch64::REG::W12_HI) + .value("W13_HI", LIEF::assembly::aarch64::REG::W13_HI) + .value("W14_HI", LIEF::assembly::aarch64::REG::W14_HI) + .value("W15_HI", LIEF::assembly::aarch64::REG::W15_HI) + .value("W16_HI", LIEF::assembly::aarch64::REG::W16_HI) + .value("W17_HI", LIEF::assembly::aarch64::REG::W17_HI) + .value("W18_HI", LIEF::assembly::aarch64::REG::W18_HI) + .value("W19_HI", LIEF::assembly::aarch64::REG::W19_HI) + .value("W20_HI", LIEF::assembly::aarch64::REG::W20_HI) + .value("W21_HI", LIEF::assembly::aarch64::REG::W21_HI) + .value("W22_HI", LIEF::assembly::aarch64::REG::W22_HI) + .value("W23_HI", LIEF::assembly::aarch64::REG::W23_HI) + .value("W24_HI", LIEF::assembly::aarch64::REG::W24_HI) + .value("W25_HI", LIEF::assembly::aarch64::REG::W25_HI) + .value("W26_HI", LIEF::assembly::aarch64::REG::W26_HI) + .value("W27_HI", LIEF::assembly::aarch64::REG::W27_HI) + .value("W28_HI", LIEF::assembly::aarch64::REG::W28_HI) + .value("W29_HI", LIEF::assembly::aarch64::REG::W29_HI) + .value("W30_HI", LIEF::assembly::aarch64::REG::W30_HI) + .value("D0_D1", LIEF::assembly::aarch64::REG::D0_D1) + .value("D1_D2", LIEF::assembly::aarch64::REG::D1_D2) + .value("D2_D3", LIEF::assembly::aarch64::REG::D2_D3) + .value("D3_D4", LIEF::assembly::aarch64::REG::D3_D4) + .value("D4_D5", LIEF::assembly::aarch64::REG::D4_D5) + .value("D5_D6", LIEF::assembly::aarch64::REG::D5_D6) + .value("D6_D7", LIEF::assembly::aarch64::REG::D6_D7) + .value("D7_D8", LIEF::assembly::aarch64::REG::D7_D8) + .value("D8_D9", LIEF::assembly::aarch64::REG::D8_D9) + .value("D9_D10", LIEF::assembly::aarch64::REG::D9_D10) + .value("D10_D11", LIEF::assembly::aarch64::REG::D10_D11) + .value("D11_D12", LIEF::assembly::aarch64::REG::D11_D12) + .value("D12_D13", LIEF::assembly::aarch64::REG::D12_D13) + .value("D13_D14", LIEF::assembly::aarch64::REG::D13_D14) + .value("D14_D15", LIEF::assembly::aarch64::REG::D14_D15) + .value("D15_D16", LIEF::assembly::aarch64::REG::D15_D16) + .value("D16_D17", LIEF::assembly::aarch64::REG::D16_D17) + .value("D17_D18", LIEF::assembly::aarch64::REG::D17_D18) + .value("D18_D19", LIEF::assembly::aarch64::REG::D18_D19) + .value("D19_D20", LIEF::assembly::aarch64::REG::D19_D20) + .value("D20_D21", LIEF::assembly::aarch64::REG::D20_D21) + .value("D21_D22", LIEF::assembly::aarch64::REG::D21_D22) + .value("D22_D23", LIEF::assembly::aarch64::REG::D22_D23) + .value("D23_D24", LIEF::assembly::aarch64::REG::D23_D24) + .value("D24_D25", LIEF::assembly::aarch64::REG::D24_D25) + .value("D25_D26", LIEF::assembly::aarch64::REG::D25_D26) + .value("D26_D27", LIEF::assembly::aarch64::REG::D26_D27) + .value("D27_D28", LIEF::assembly::aarch64::REG::D27_D28) + .value("D28_D29", LIEF::assembly::aarch64::REG::D28_D29) + .value("D29_D30", LIEF::assembly::aarch64::REG::D29_D30) + .value("D30_D31", LIEF::assembly::aarch64::REG::D30_D31) + .value("D31_D0", LIEF::assembly::aarch64::REG::D31_D0) + .value("D0_D1_D2_D3", LIEF::assembly::aarch64::REG::D0_D1_D2_D3) + .value("D1_D2_D3_D4", LIEF::assembly::aarch64::REG::D1_D2_D3_D4) + .value("D2_D3_D4_D5", LIEF::assembly::aarch64::REG::D2_D3_D4_D5) + .value("D3_D4_D5_D6", LIEF::assembly::aarch64::REG::D3_D4_D5_D6) + .value("D4_D5_D6_D7", LIEF::assembly::aarch64::REG::D4_D5_D6_D7) + .value("D5_D6_D7_D8", LIEF::assembly::aarch64::REG::D5_D6_D7_D8) + .value("D6_D7_D8_D9", LIEF::assembly::aarch64::REG::D6_D7_D8_D9) + .value("D7_D8_D9_D10", LIEF::assembly::aarch64::REG::D7_D8_D9_D10) + .value("D8_D9_D10_D11", LIEF::assembly::aarch64::REG::D8_D9_D10_D11) + .value("D9_D10_D11_D12", LIEF::assembly::aarch64::REG::D9_D10_D11_D12) + .value("D10_D11_D12_D13", LIEF::assembly::aarch64::REG::D10_D11_D12_D13) + .value("D11_D12_D13_D14", LIEF::assembly::aarch64::REG::D11_D12_D13_D14) + .value("D12_D13_D14_D15", LIEF::assembly::aarch64::REG::D12_D13_D14_D15) + .value("D13_D14_D15_D16", LIEF::assembly::aarch64::REG::D13_D14_D15_D16) + .value("D14_D15_D16_D17", LIEF::assembly::aarch64::REG::D14_D15_D16_D17) + .value("D15_D16_D17_D18", LIEF::assembly::aarch64::REG::D15_D16_D17_D18) + .value("D16_D17_D18_D19", LIEF::assembly::aarch64::REG::D16_D17_D18_D19) + .value("D17_D18_D19_D20", LIEF::assembly::aarch64::REG::D17_D18_D19_D20) + .value("D18_D19_D20_D21", LIEF::assembly::aarch64::REG::D18_D19_D20_D21) + .value("D19_D20_D21_D22", LIEF::assembly::aarch64::REG::D19_D20_D21_D22) + .value("D20_D21_D22_D23", LIEF::assembly::aarch64::REG::D20_D21_D22_D23) + .value("D21_D22_D23_D24", LIEF::assembly::aarch64::REG::D21_D22_D23_D24) + .value("D22_D23_D24_D25", LIEF::assembly::aarch64::REG::D22_D23_D24_D25) + .value("D23_D24_D25_D26", LIEF::assembly::aarch64::REG::D23_D24_D25_D26) + .value("D24_D25_D26_D27", LIEF::assembly::aarch64::REG::D24_D25_D26_D27) + .value("D25_D26_D27_D28", LIEF::assembly::aarch64::REG::D25_D26_D27_D28) + .value("D26_D27_D28_D29", LIEF::assembly::aarch64::REG::D26_D27_D28_D29) + .value("D27_D28_D29_D30", LIEF::assembly::aarch64::REG::D27_D28_D29_D30) + .value("D28_D29_D30_D31", LIEF::assembly::aarch64::REG::D28_D29_D30_D31) + .value("D29_D30_D31_D0", LIEF::assembly::aarch64::REG::D29_D30_D31_D0) + .value("D30_D31_D0_D1", LIEF::assembly::aarch64::REG::D30_D31_D0_D1) + .value("D31_D0_D1_D2", LIEF::assembly::aarch64::REG::D31_D0_D1_D2) + .value("D0_D1_D2", LIEF::assembly::aarch64::REG::D0_D1_D2) + .value("D1_D2_D3", LIEF::assembly::aarch64::REG::D1_D2_D3) + .value("D2_D3_D4", LIEF::assembly::aarch64::REG::D2_D3_D4) + .value("D3_D4_D5", LIEF::assembly::aarch64::REG::D3_D4_D5) + .value("D4_D5_D6", LIEF::assembly::aarch64::REG::D4_D5_D6) + .value("D5_D6_D7", LIEF::assembly::aarch64::REG::D5_D6_D7) + .value("D6_D7_D8", LIEF::assembly::aarch64::REG::D6_D7_D8) + .value("D7_D8_D9", LIEF::assembly::aarch64::REG::D7_D8_D9) + .value("D8_D9_D10", LIEF::assembly::aarch64::REG::D8_D9_D10) + .value("D9_D10_D11", LIEF::assembly::aarch64::REG::D9_D10_D11) + .value("D10_D11_D12", LIEF::assembly::aarch64::REG::D10_D11_D12) + .value("D11_D12_D13", LIEF::assembly::aarch64::REG::D11_D12_D13) + .value("D12_D13_D14", LIEF::assembly::aarch64::REG::D12_D13_D14); + reg.value("D13_D14_D15", LIEF::assembly::aarch64::REG::D13_D14_D15) + .value("D14_D15_D16", LIEF::assembly::aarch64::REG::D14_D15_D16) + .value("D15_D16_D17", LIEF::assembly::aarch64::REG::D15_D16_D17) + .value("D16_D17_D18", LIEF::assembly::aarch64::REG::D16_D17_D18) + .value("D17_D18_D19", LIEF::assembly::aarch64::REG::D17_D18_D19) + .value("D18_D19_D20", LIEF::assembly::aarch64::REG::D18_D19_D20) + .value("D19_D20_D21", LIEF::assembly::aarch64::REG::D19_D20_D21) + .value("D20_D21_D22", LIEF::assembly::aarch64::REG::D20_D21_D22) + .value("D21_D22_D23", LIEF::assembly::aarch64::REG::D21_D22_D23) + .value("D22_D23_D24", LIEF::assembly::aarch64::REG::D22_D23_D24) + .value("D23_D24_D25", LIEF::assembly::aarch64::REG::D23_D24_D25) + .value("D24_D25_D26", LIEF::assembly::aarch64::REG::D24_D25_D26) + .value("D25_D26_D27", LIEF::assembly::aarch64::REG::D25_D26_D27) + .value("D26_D27_D28", LIEF::assembly::aarch64::REG::D26_D27_D28) + .value("D27_D28_D29", LIEF::assembly::aarch64::REG::D27_D28_D29) + .value("D28_D29_D30", LIEF::assembly::aarch64::REG::D28_D29_D30) + .value("D29_D30_D31", LIEF::assembly::aarch64::REG::D29_D30_D31) + .value("D30_D31_D0", LIEF::assembly::aarch64::REG::D30_D31_D0) + .value("D31_D0_D1", LIEF::assembly::aarch64::REG::D31_D0_D1) + .value("P0_P1", LIEF::assembly::aarch64::REG::P0_P1) + .value("P1_P2", LIEF::assembly::aarch64::REG::P1_P2) + .value("P2_P3", LIEF::assembly::aarch64::REG::P2_P3) + .value("P3_P4", LIEF::assembly::aarch64::REG::P3_P4) + .value("P4_P5", LIEF::assembly::aarch64::REG::P4_P5) + .value("P5_P6", LIEF::assembly::aarch64::REG::P5_P6) + .value("P6_P7", LIEF::assembly::aarch64::REG::P6_P7) + .value("P7_P8", LIEF::assembly::aarch64::REG::P7_P8) + .value("P8_P9", LIEF::assembly::aarch64::REG::P8_P9) + .value("P9_P10", LIEF::assembly::aarch64::REG::P9_P10) + .value("P10_P11", LIEF::assembly::aarch64::REG::P10_P11) + .value("P11_P12", LIEF::assembly::aarch64::REG::P11_P12) + .value("P12_P13", LIEF::assembly::aarch64::REG::P12_P13) + .value("P13_P14", LIEF::assembly::aarch64::REG::P13_P14) + .value("P14_P15", LIEF::assembly::aarch64::REG::P14_P15) + .value("P15_P0", LIEF::assembly::aarch64::REG::P15_P0) + .value("Q0_Q1", LIEF::assembly::aarch64::REG::Q0_Q1) + .value("Q1_Q2", LIEF::assembly::aarch64::REG::Q1_Q2) + .value("Q2_Q3", LIEF::assembly::aarch64::REG::Q2_Q3) + .value("Q3_Q4", LIEF::assembly::aarch64::REG::Q3_Q4) + .value("Q4_Q5", LIEF::assembly::aarch64::REG::Q4_Q5) + .value("Q5_Q6", LIEF::assembly::aarch64::REG::Q5_Q6) + .value("Q6_Q7", LIEF::assembly::aarch64::REG::Q6_Q7) + .value("Q7_Q8", LIEF::assembly::aarch64::REG::Q7_Q8) + .value("Q8_Q9", LIEF::assembly::aarch64::REG::Q8_Q9) + .value("Q9_Q10", LIEF::assembly::aarch64::REG::Q9_Q10) + .value("Q10_Q11", LIEF::assembly::aarch64::REG::Q10_Q11) + .value("Q11_Q12", LIEF::assembly::aarch64::REG::Q11_Q12) + .value("Q12_Q13", LIEF::assembly::aarch64::REG::Q12_Q13) + .value("Q13_Q14", LIEF::assembly::aarch64::REG::Q13_Q14) + .value("Q14_Q15", LIEF::assembly::aarch64::REG::Q14_Q15) + .value("Q15_Q16", LIEF::assembly::aarch64::REG::Q15_Q16) + .value("Q16_Q17", LIEF::assembly::aarch64::REG::Q16_Q17) + .value("Q17_Q18", LIEF::assembly::aarch64::REG::Q17_Q18) + .value("Q18_Q19", LIEF::assembly::aarch64::REG::Q18_Q19) + .value("Q19_Q20", LIEF::assembly::aarch64::REG::Q19_Q20) + .value("Q20_Q21", LIEF::assembly::aarch64::REG::Q20_Q21) + .value("Q21_Q22", LIEF::assembly::aarch64::REG::Q21_Q22) + .value("Q22_Q23", LIEF::assembly::aarch64::REG::Q22_Q23) + .value("Q23_Q24", LIEF::assembly::aarch64::REG::Q23_Q24) + .value("Q24_Q25", LIEF::assembly::aarch64::REG::Q24_Q25) + .value("Q25_Q26", LIEF::assembly::aarch64::REG::Q25_Q26) + .value("Q26_Q27", LIEF::assembly::aarch64::REG::Q26_Q27) + .value("Q27_Q28", LIEF::assembly::aarch64::REG::Q27_Q28) + .value("Q28_Q29", LIEF::assembly::aarch64::REG::Q28_Q29) + .value("Q29_Q30", LIEF::assembly::aarch64::REG::Q29_Q30) + .value("Q30_Q31", LIEF::assembly::aarch64::REG::Q30_Q31) + .value("Q31_Q0", LIEF::assembly::aarch64::REG::Q31_Q0) + .value("Q0_Q1_Q2_Q3", LIEF::assembly::aarch64::REG::Q0_Q1_Q2_Q3) + .value("Q1_Q2_Q3_Q4", LIEF::assembly::aarch64::REG::Q1_Q2_Q3_Q4) + .value("Q2_Q3_Q4_Q5", LIEF::assembly::aarch64::REG::Q2_Q3_Q4_Q5) + .value("Q3_Q4_Q5_Q6", LIEF::assembly::aarch64::REG::Q3_Q4_Q5_Q6) + .value("Q4_Q5_Q6_Q7", LIEF::assembly::aarch64::REG::Q4_Q5_Q6_Q7) + .value("Q5_Q6_Q7_Q8", LIEF::assembly::aarch64::REG::Q5_Q6_Q7_Q8) + .value("Q6_Q7_Q8_Q9", LIEF::assembly::aarch64::REG::Q6_Q7_Q8_Q9) + .value("Q7_Q8_Q9_Q10", LIEF::assembly::aarch64::REG::Q7_Q8_Q9_Q10) + .value("Q8_Q9_Q10_Q11", LIEF::assembly::aarch64::REG::Q8_Q9_Q10_Q11) + .value("Q9_Q10_Q11_Q12", LIEF::assembly::aarch64::REG::Q9_Q10_Q11_Q12) + .value("Q10_Q11_Q12_Q13", LIEF::assembly::aarch64::REG::Q10_Q11_Q12_Q13) + .value("Q11_Q12_Q13_Q14", LIEF::assembly::aarch64::REG::Q11_Q12_Q13_Q14) + .value("Q12_Q13_Q14_Q15", LIEF::assembly::aarch64::REG::Q12_Q13_Q14_Q15) + .value("Q13_Q14_Q15_Q16", LIEF::assembly::aarch64::REG::Q13_Q14_Q15_Q16) + .value("Q14_Q15_Q16_Q17", LIEF::assembly::aarch64::REG::Q14_Q15_Q16_Q17) + .value("Q15_Q16_Q17_Q18", LIEF::assembly::aarch64::REG::Q15_Q16_Q17_Q18) + .value("Q16_Q17_Q18_Q19", LIEF::assembly::aarch64::REG::Q16_Q17_Q18_Q19) + .value("Q17_Q18_Q19_Q20", LIEF::assembly::aarch64::REG::Q17_Q18_Q19_Q20) + .value("Q18_Q19_Q20_Q21", LIEF::assembly::aarch64::REG::Q18_Q19_Q20_Q21) + .value("Q19_Q20_Q21_Q22", LIEF::assembly::aarch64::REG::Q19_Q20_Q21_Q22) + .value("Q20_Q21_Q22_Q23", LIEF::assembly::aarch64::REG::Q20_Q21_Q22_Q23) + .value("Q21_Q22_Q23_Q24", LIEF::assembly::aarch64::REG::Q21_Q22_Q23_Q24) + .value("Q22_Q23_Q24_Q25", LIEF::assembly::aarch64::REG::Q22_Q23_Q24_Q25) + .value("Q23_Q24_Q25_Q26", LIEF::assembly::aarch64::REG::Q23_Q24_Q25_Q26) + .value("Q24_Q25_Q26_Q27", LIEF::assembly::aarch64::REG::Q24_Q25_Q26_Q27) + .value("Q25_Q26_Q27_Q28", LIEF::assembly::aarch64::REG::Q25_Q26_Q27_Q28) + .value("Q26_Q27_Q28_Q29", LIEF::assembly::aarch64::REG::Q26_Q27_Q28_Q29) + .value("Q27_Q28_Q29_Q30", LIEF::assembly::aarch64::REG::Q27_Q28_Q29_Q30) + .value("Q28_Q29_Q30_Q31", LIEF::assembly::aarch64::REG::Q28_Q29_Q30_Q31) + .value("Q29_Q30_Q31_Q0", LIEF::assembly::aarch64::REG::Q29_Q30_Q31_Q0) + .value("Q30_Q31_Q0_Q1", LIEF::assembly::aarch64::REG::Q30_Q31_Q0_Q1) + .value("Q31_Q0_Q1_Q2", LIEF::assembly::aarch64::REG::Q31_Q0_Q1_Q2) + .value("Q0_Q1_Q2", LIEF::assembly::aarch64::REG::Q0_Q1_Q2) + .value("Q1_Q2_Q3", LIEF::assembly::aarch64::REG::Q1_Q2_Q3) + .value("Q2_Q3_Q4", LIEF::assembly::aarch64::REG::Q2_Q3_Q4) + .value("Q3_Q4_Q5", LIEF::assembly::aarch64::REG::Q3_Q4_Q5) + .value("Q4_Q5_Q6", LIEF::assembly::aarch64::REG::Q4_Q5_Q6) + .value("Q5_Q6_Q7", LIEF::assembly::aarch64::REG::Q5_Q6_Q7) + .value("Q6_Q7_Q8", LIEF::assembly::aarch64::REG::Q6_Q7_Q8) + .value("Q7_Q8_Q9", LIEF::assembly::aarch64::REG::Q7_Q8_Q9) + .value("Q8_Q9_Q10", LIEF::assembly::aarch64::REG::Q8_Q9_Q10) + .value("Q9_Q10_Q11", LIEF::assembly::aarch64::REG::Q9_Q10_Q11) + .value("Q10_Q11_Q12", LIEF::assembly::aarch64::REG::Q10_Q11_Q12) + .value("Q11_Q12_Q13", LIEF::assembly::aarch64::REG::Q11_Q12_Q13) + .value("Q12_Q13_Q14", LIEF::assembly::aarch64::REG::Q12_Q13_Q14) + .value("Q13_Q14_Q15", LIEF::assembly::aarch64::REG::Q13_Q14_Q15) + .value("Q14_Q15_Q16", LIEF::assembly::aarch64::REG::Q14_Q15_Q16) + .value("Q15_Q16_Q17", LIEF::assembly::aarch64::REG::Q15_Q16_Q17) + .value("Q16_Q17_Q18", LIEF::assembly::aarch64::REG::Q16_Q17_Q18) + .value("Q17_Q18_Q19", LIEF::assembly::aarch64::REG::Q17_Q18_Q19) + .value("Q18_Q19_Q20", LIEF::assembly::aarch64::REG::Q18_Q19_Q20) + .value("Q19_Q20_Q21", LIEF::assembly::aarch64::REG::Q19_Q20_Q21) + .value("Q20_Q21_Q22", LIEF::assembly::aarch64::REG::Q20_Q21_Q22) + .value("Q21_Q22_Q23", LIEF::assembly::aarch64::REG::Q21_Q22_Q23) + .value("Q22_Q23_Q24", LIEF::assembly::aarch64::REG::Q22_Q23_Q24) + .value("Q23_Q24_Q25", LIEF::assembly::aarch64::REG::Q23_Q24_Q25) + .value("Q24_Q25_Q26", LIEF::assembly::aarch64::REG::Q24_Q25_Q26) + .value("Q25_Q26_Q27", LIEF::assembly::aarch64::REG::Q25_Q26_Q27) + .value("Q26_Q27_Q28", LIEF::assembly::aarch64::REG::Q26_Q27_Q28) + .value("Q27_Q28_Q29", LIEF::assembly::aarch64::REG::Q27_Q28_Q29) + .value("Q28_Q29_Q30", LIEF::assembly::aarch64::REG::Q28_Q29_Q30) + .value("Q29_Q30_Q31", LIEF::assembly::aarch64::REG::Q29_Q30_Q31) + .value("Q30_Q31_Q0", LIEF::assembly::aarch64::REG::Q30_Q31_Q0) + .value("Q31_Q0_Q1", LIEF::assembly::aarch64::REG::Q31_Q0_Q1) + .value("X22_X23_X24_X25_X26_X27_X28_FP", LIEF::assembly::aarch64::REG::X22_X23_X24_X25_X26_X27_X28_FP) + .value("X0_X1_X2_X3_X4_X5_X6_X7", LIEF::assembly::aarch64::REG::X0_X1_X2_X3_X4_X5_X6_X7) + .value("X2_X3_X4_X5_X6_X7_X8_X9", LIEF::assembly::aarch64::REG::X2_X3_X4_X5_X6_X7_X8_X9) + .value("X4_X5_X6_X7_X8_X9_X10_X11", LIEF::assembly::aarch64::REG::X4_X5_X6_X7_X8_X9_X10_X11) + .value("X6_X7_X8_X9_X10_X11_X12_X13", LIEF::assembly::aarch64::REG::X6_X7_X8_X9_X10_X11_X12_X13) + .value("X8_X9_X10_X11_X12_X13_X14_X15", LIEF::assembly::aarch64::REG::X8_X9_X10_X11_X12_X13_X14_X15) + .value("X10_X11_X12_X13_X14_X15_X16_X17", LIEF::assembly::aarch64::REG::X10_X11_X12_X13_X14_X15_X16_X17) + .value("X12_X13_X14_X15_X16_X17_X18_X19", LIEF::assembly::aarch64::REG::X12_X13_X14_X15_X16_X17_X18_X19) + .value("X14_X15_X16_X17_X18_X19_X20_X21", LIEF::assembly::aarch64::REG::X14_X15_X16_X17_X18_X19_X20_X21) + .value("X16_X17_X18_X19_X20_X21_X22_X23", LIEF::assembly::aarch64::REG::X16_X17_X18_X19_X20_X21_X22_X23) + .value("X18_X19_X20_X21_X22_X23_X24_X25", LIEF::assembly::aarch64::REG::X18_X19_X20_X21_X22_X23_X24_X25) + .value("X20_X21_X22_X23_X24_X25_X26_X27", LIEF::assembly::aarch64::REG::X20_X21_X22_X23_X24_X25_X26_X27) + .value("W30_WZR", LIEF::assembly::aarch64::REG::W30_WZR) + .value("W0_W1", LIEF::assembly::aarch64::REG::W0_W1) + .value("W2_W3", LIEF::assembly::aarch64::REG::W2_W3) + .value("W4_W5", LIEF::assembly::aarch64::REG::W4_W5) + .value("W6_W7", LIEF::assembly::aarch64::REG::W6_W7) + .value("W8_W9", LIEF::assembly::aarch64::REG::W8_W9) + .value("W10_W11", LIEF::assembly::aarch64::REG::W10_W11) + .value("W12_W13", LIEF::assembly::aarch64::REG::W12_W13) + .value("W14_W15", LIEF::assembly::aarch64::REG::W14_W15) + .value("W16_W17", LIEF::assembly::aarch64::REG::W16_W17) + .value("W18_W19", LIEF::assembly::aarch64::REG::W18_W19) + .value("W20_W21", LIEF::assembly::aarch64::REG::W20_W21) + .value("W22_W23", LIEF::assembly::aarch64::REG::W22_W23) + .value("W24_W25", LIEF::assembly::aarch64::REG::W24_W25) + .value("W26_W27", LIEF::assembly::aarch64::REG::W26_W27) + .value("W28_W29", LIEF::assembly::aarch64::REG::W28_W29) + .value("LR_XZR", LIEF::assembly::aarch64::REG::LR_XZR) + .value("X28_FP", LIEF::assembly::aarch64::REG::X28_FP) + .value("X0_X1", LIEF::assembly::aarch64::REG::X0_X1) + .value("X2_X3", LIEF::assembly::aarch64::REG::X2_X3) + .value("X4_X5", LIEF::assembly::aarch64::REG::X4_X5) + .value("X6_X7", LIEF::assembly::aarch64::REG::X6_X7) + .value("X8_X9", LIEF::assembly::aarch64::REG::X8_X9) + .value("X10_X11", LIEF::assembly::aarch64::REG::X10_X11) + .value("X12_X13", LIEF::assembly::aarch64::REG::X12_X13) + .value("X14_X15", LIEF::assembly::aarch64::REG::X14_X15) + .value("X16_X17", LIEF::assembly::aarch64::REG::X16_X17) + .value("X18_X19", LIEF::assembly::aarch64::REG::X18_X19) + .value("X20_X21", LIEF::assembly::aarch64::REG::X20_X21) + .value("X22_X23", LIEF::assembly::aarch64::REG::X22_X23) + .value("X24_X25", LIEF::assembly::aarch64::REG::X24_X25) + .value("X26_X27", LIEF::assembly::aarch64::REG::X26_X27) + .value("Z0_Z1", LIEF::assembly::aarch64::REG::Z0_Z1) + .value("Z1_Z2", LIEF::assembly::aarch64::REG::Z1_Z2) + .value("Z2_Z3", LIEF::assembly::aarch64::REG::Z2_Z3) + .value("Z3_Z4", LIEF::assembly::aarch64::REG::Z3_Z4) + .value("Z4_Z5", LIEF::assembly::aarch64::REG::Z4_Z5) + .value("Z5_Z6", LIEF::assembly::aarch64::REG::Z5_Z6) + .value("Z6_Z7", LIEF::assembly::aarch64::REG::Z6_Z7) + .value("Z7_Z8", LIEF::assembly::aarch64::REG::Z7_Z8) + .value("Z8_Z9", LIEF::assembly::aarch64::REG::Z8_Z9) + .value("Z9_Z10", LIEF::assembly::aarch64::REG::Z9_Z10) + .value("Z10_Z11", LIEF::assembly::aarch64::REG::Z10_Z11) + .value("Z11_Z12", LIEF::assembly::aarch64::REG::Z11_Z12) + .value("Z12_Z13", LIEF::assembly::aarch64::REG::Z12_Z13) + .value("Z13_Z14", LIEF::assembly::aarch64::REG::Z13_Z14) + .value("Z14_Z15", LIEF::assembly::aarch64::REG::Z14_Z15) + .value("Z15_Z16", LIEF::assembly::aarch64::REG::Z15_Z16) + .value("Z16_Z17", LIEF::assembly::aarch64::REG::Z16_Z17) + .value("Z17_Z18", LIEF::assembly::aarch64::REG::Z17_Z18) + .value("Z18_Z19", LIEF::assembly::aarch64::REG::Z18_Z19) + .value("Z19_Z20", LIEF::assembly::aarch64::REG::Z19_Z20) + .value("Z20_Z21", LIEF::assembly::aarch64::REG::Z20_Z21) + .value("Z21_Z22", LIEF::assembly::aarch64::REG::Z21_Z22) + .value("Z22_Z23", LIEF::assembly::aarch64::REG::Z22_Z23) + .value("Z23_Z24", LIEF::assembly::aarch64::REG::Z23_Z24) + .value("Z24_Z25", LIEF::assembly::aarch64::REG::Z24_Z25) + .value("Z25_Z26", LIEF::assembly::aarch64::REG::Z25_Z26) + .value("Z26_Z27", LIEF::assembly::aarch64::REG::Z26_Z27) + .value("Z27_Z28", LIEF::assembly::aarch64::REG::Z27_Z28) + .value("Z28_Z29", LIEF::assembly::aarch64::REG::Z28_Z29) + .value("Z29_Z30", LIEF::assembly::aarch64::REG::Z29_Z30) + .value("Z30_Z31", LIEF::assembly::aarch64::REG::Z30_Z31) + .value("Z31_Z0", LIEF::assembly::aarch64::REG::Z31_Z0) + .value("Z0_Z1_Z2_Z3", LIEF::assembly::aarch64::REG::Z0_Z1_Z2_Z3) + .value("Z1_Z2_Z3_Z4", LIEF::assembly::aarch64::REG::Z1_Z2_Z3_Z4) + .value("Z2_Z3_Z4_Z5", LIEF::assembly::aarch64::REG::Z2_Z3_Z4_Z5) + .value("Z3_Z4_Z5_Z6", LIEF::assembly::aarch64::REG::Z3_Z4_Z5_Z6) + .value("Z4_Z5_Z6_Z7", LIEF::assembly::aarch64::REG::Z4_Z5_Z6_Z7) + .value("Z5_Z6_Z7_Z8", LIEF::assembly::aarch64::REG::Z5_Z6_Z7_Z8) + .value("Z6_Z7_Z8_Z9", LIEF::assembly::aarch64::REG::Z6_Z7_Z8_Z9) + .value("Z7_Z8_Z9_Z10", LIEF::assembly::aarch64::REG::Z7_Z8_Z9_Z10) + .value("Z8_Z9_Z10_Z11", LIEF::assembly::aarch64::REG::Z8_Z9_Z10_Z11) + .value("Z9_Z10_Z11_Z12", LIEF::assembly::aarch64::REG::Z9_Z10_Z11_Z12) + .value("Z10_Z11_Z12_Z13", LIEF::assembly::aarch64::REG::Z10_Z11_Z12_Z13) + .value("Z11_Z12_Z13_Z14", LIEF::assembly::aarch64::REG::Z11_Z12_Z13_Z14) + .value("Z12_Z13_Z14_Z15", LIEF::assembly::aarch64::REG::Z12_Z13_Z14_Z15) + .value("Z13_Z14_Z15_Z16", LIEF::assembly::aarch64::REG::Z13_Z14_Z15_Z16) + .value("Z14_Z15_Z16_Z17", LIEF::assembly::aarch64::REG::Z14_Z15_Z16_Z17) + .value("Z15_Z16_Z17_Z18", LIEF::assembly::aarch64::REG::Z15_Z16_Z17_Z18) + .value("Z16_Z17_Z18_Z19", LIEF::assembly::aarch64::REG::Z16_Z17_Z18_Z19) + .value("Z17_Z18_Z19_Z20", LIEF::assembly::aarch64::REG::Z17_Z18_Z19_Z20) + .value("Z18_Z19_Z20_Z21", LIEF::assembly::aarch64::REG::Z18_Z19_Z20_Z21) + .value("Z19_Z20_Z21_Z22", LIEF::assembly::aarch64::REG::Z19_Z20_Z21_Z22) + .value("Z20_Z21_Z22_Z23", LIEF::assembly::aarch64::REG::Z20_Z21_Z22_Z23) + .value("Z21_Z22_Z23_Z24", LIEF::assembly::aarch64::REG::Z21_Z22_Z23_Z24) + .value("Z22_Z23_Z24_Z25", LIEF::assembly::aarch64::REG::Z22_Z23_Z24_Z25) + .value("Z23_Z24_Z25_Z26", LIEF::assembly::aarch64::REG::Z23_Z24_Z25_Z26) + .value("Z24_Z25_Z26_Z27", LIEF::assembly::aarch64::REG::Z24_Z25_Z26_Z27) + .value("Z25_Z26_Z27_Z28", LIEF::assembly::aarch64::REG::Z25_Z26_Z27_Z28) + .value("Z26_Z27_Z28_Z29", LIEF::assembly::aarch64::REG::Z26_Z27_Z28_Z29) + .value("Z27_Z28_Z29_Z30", LIEF::assembly::aarch64::REG::Z27_Z28_Z29_Z30) + .value("Z28_Z29_Z30_Z31", LIEF::assembly::aarch64::REG::Z28_Z29_Z30_Z31) + .value("Z29_Z30_Z31_Z0", LIEF::assembly::aarch64::REG::Z29_Z30_Z31_Z0) + .value("Z30_Z31_Z0_Z1", LIEF::assembly::aarch64::REG::Z30_Z31_Z0_Z1) + .value("Z31_Z0_Z1_Z2", LIEF::assembly::aarch64::REG::Z31_Z0_Z1_Z2) + .value("Z0_Z1_Z2", LIEF::assembly::aarch64::REG::Z0_Z1_Z2) + .value("Z1_Z2_Z3", LIEF::assembly::aarch64::REG::Z1_Z2_Z3) + .value("Z2_Z3_Z4", LIEF::assembly::aarch64::REG::Z2_Z3_Z4) + .value("Z3_Z4_Z5", LIEF::assembly::aarch64::REG::Z3_Z4_Z5) + .value("Z4_Z5_Z6", LIEF::assembly::aarch64::REG::Z4_Z5_Z6) + .value("Z5_Z6_Z7", LIEF::assembly::aarch64::REG::Z5_Z6_Z7) + .value("Z6_Z7_Z8", LIEF::assembly::aarch64::REG::Z6_Z7_Z8) + .value("Z7_Z8_Z9", LIEF::assembly::aarch64::REG::Z7_Z8_Z9) + .value("Z8_Z9_Z10", LIEF::assembly::aarch64::REG::Z8_Z9_Z10) + .value("Z9_Z10_Z11", LIEF::assembly::aarch64::REG::Z9_Z10_Z11) + .value("Z10_Z11_Z12", LIEF::assembly::aarch64::REG::Z10_Z11_Z12) + .value("Z11_Z12_Z13", LIEF::assembly::aarch64::REG::Z11_Z12_Z13) + .value("Z12_Z13_Z14", LIEF::assembly::aarch64::REG::Z12_Z13_Z14) + .value("Z13_Z14_Z15", LIEF::assembly::aarch64::REG::Z13_Z14_Z15) + .value("Z14_Z15_Z16", LIEF::assembly::aarch64::REG::Z14_Z15_Z16) + .value("Z15_Z16_Z17", LIEF::assembly::aarch64::REG::Z15_Z16_Z17) + .value("Z16_Z17_Z18", LIEF::assembly::aarch64::REG::Z16_Z17_Z18) + .value("Z17_Z18_Z19", LIEF::assembly::aarch64::REG::Z17_Z18_Z19) + .value("Z18_Z19_Z20", LIEF::assembly::aarch64::REG::Z18_Z19_Z20) + .value("Z19_Z20_Z21", LIEF::assembly::aarch64::REG::Z19_Z20_Z21) + .value("Z20_Z21_Z22", LIEF::assembly::aarch64::REG::Z20_Z21_Z22) + .value("Z21_Z22_Z23", LIEF::assembly::aarch64::REG::Z21_Z22_Z23) + .value("Z22_Z23_Z24", LIEF::assembly::aarch64::REG::Z22_Z23_Z24) + .value("Z23_Z24_Z25", LIEF::assembly::aarch64::REG::Z23_Z24_Z25) + .value("Z24_Z25_Z26", LIEF::assembly::aarch64::REG::Z24_Z25_Z26) + .value("Z25_Z26_Z27", LIEF::assembly::aarch64::REG::Z25_Z26_Z27) + .value("Z26_Z27_Z28", LIEF::assembly::aarch64::REG::Z26_Z27_Z28) + .value("Z27_Z28_Z29", LIEF::assembly::aarch64::REG::Z27_Z28_Z29) + .value("Z28_Z29_Z30", LIEF::assembly::aarch64::REG::Z28_Z29_Z30) + .value("Z29_Z30_Z31", LIEF::assembly::aarch64::REG::Z29_Z30_Z31) + .value("Z30_Z31_Z0", LIEF::assembly::aarch64::REG::Z30_Z31_Z0) + .value("Z31_Z0_Z1", LIEF::assembly::aarch64::REG::Z31_Z0_Z1) + .value("Z16_Z24", LIEF::assembly::aarch64::REG::Z16_Z24) + .value("Z17_Z25", LIEF::assembly::aarch64::REG::Z17_Z25) + .value("Z18_Z26", LIEF::assembly::aarch64::REG::Z18_Z26) + .value("Z19_Z27", LIEF::assembly::aarch64::REG::Z19_Z27) + .value("Z20_Z28", LIEF::assembly::aarch64::REG::Z20_Z28) + .value("Z21_Z29", LIEF::assembly::aarch64::REG::Z21_Z29) + .value("Z22_Z30", LIEF::assembly::aarch64::REG::Z22_Z30) + .value("Z23_Z31", LIEF::assembly::aarch64::REG::Z23_Z31) + .value("Z0_Z8", LIEF::assembly::aarch64::REG::Z0_Z8) + .value("Z1_Z9", LIEF::assembly::aarch64::REG::Z1_Z9) + .value("Z2_Z10", LIEF::assembly::aarch64::REG::Z2_Z10) + .value("Z3_Z11", LIEF::assembly::aarch64::REG::Z3_Z11) + .value("Z4_Z12", LIEF::assembly::aarch64::REG::Z4_Z12) + .value("Z5_Z13", LIEF::assembly::aarch64::REG::Z5_Z13) + .value("Z6_Z14", LIEF::assembly::aarch64::REG::Z6_Z14) + .value("Z7_Z15", LIEF::assembly::aarch64::REG::Z7_Z15) + .value("Z16_Z20_Z24_Z28", LIEF::assembly::aarch64::REG::Z16_Z20_Z24_Z28) + .value("Z17_Z21_Z25_Z29", LIEF::assembly::aarch64::REG::Z17_Z21_Z25_Z29) + .value("Z18_Z22_Z26_Z30", LIEF::assembly::aarch64::REG::Z18_Z22_Z26_Z30) + .value("Z19_Z23_Z27_Z31", LIEF::assembly::aarch64::REG::Z19_Z23_Z27_Z31) + .value("Z0_Z4_Z8_Z12", LIEF::assembly::aarch64::REG::Z0_Z4_Z8_Z12) + .value("Z1_Z5_Z9_Z13", LIEF::assembly::aarch64::REG::Z1_Z5_Z9_Z13) + .value("Z2_Z6_Z10_Z14", LIEF::assembly::aarch64::REG::Z2_Z6_Z10_Z14) + .value("Z3_Z7_Z11_Z15", LIEF::assembly::aarch64::REG::Z3_Z7_Z11_Z15) + .value("NUM_TARGET_REGS", LIEF::assembly::aarch64::REG::NUM_TARGET_REGS) + ; +} + +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "SYSREG"); + reg.value("OSDTRRX_EL1", LIEF::assembly::aarch64::SYSREG::OSDTRRX_EL1) + .value("DBGBVR0_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR0_EL1) + .value("DBGBCR0_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR0_EL1) + .value("DBGWVR0_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR0_EL1) + .value("DBGWCR0_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR0_EL1) + .value("DBGBVR1_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR1_EL1) + .value("DBGBCR1_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR1_EL1) + .value("DBGWVR1_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR1_EL1) + .value("DBGWCR1_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR1_EL1) + .value("MDCCINT_EL1", LIEF::assembly::aarch64::SYSREG::MDCCINT_EL1) + .value("MDSCR_EL1", LIEF::assembly::aarch64::SYSREG::MDSCR_EL1) + .value("DBGBVR2_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR2_EL1) + .value("DBGBCR2_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR2_EL1) + .value("DBGWVR2_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR2_EL1) + .value("DBGWCR2_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR2_EL1) + .value("OSDTRTX_EL1", LIEF::assembly::aarch64::SYSREG::OSDTRTX_EL1) + .value("DBGBVR3_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR3_EL1) + .value("DBGBCR3_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR3_EL1) + .value("DBGWVR3_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR3_EL1) + .value("DBGWCR3_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR3_EL1) + .value("MDSELR_EL1", LIEF::assembly::aarch64::SYSREG::MDSELR_EL1) + .value("DBGBVR4_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR4_EL1) + .value("DBGBCR4_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR4_EL1) + .value("DBGWVR4_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR4_EL1) + .value("DBGWCR4_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR4_EL1) + .value("MDSTEPOP_EL1", LIEF::assembly::aarch64::SYSREG::MDSTEPOP_EL1) + .value("DBGBVR5_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR5_EL1) + .value("DBGBCR5_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR5_EL1) + .value("DBGWVR5_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR5_EL1) + .value("DBGWCR5_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR5_EL1) + .value("OSECCR_EL1", LIEF::assembly::aarch64::SYSREG::OSECCR_EL1) + .value("DBGBVR6_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR6_EL1) + .value("DBGBCR6_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR6_EL1) + .value("DBGWVR6_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR6_EL1) + .value("DBGWCR6_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR6_EL1) + .value("DBGBVR7_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR7_EL1) + .value("DBGBCR7_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR7_EL1) + .value("DBGWVR7_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR7_EL1) + .value("DBGWCR7_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR7_EL1) + .value("DBGBVR8_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR8_EL1) + .value("DBGBCR8_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR8_EL1) + .value("DBGWVR8_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR8_EL1) + .value("DBGWCR8_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR8_EL1) + .value("DBGBVR9_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR9_EL1) + .value("DBGBCR9_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR9_EL1) + .value("DBGWVR9_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR9_EL1) + .value("DBGWCR9_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR9_EL1) + .value("DBGBVR10_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR10_EL1) + .value("DBGBCR10_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR10_EL1) + .value("DBGWVR10_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR10_EL1) + .value("DBGWCR10_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR10_EL1) + .value("DBGBVR11_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR11_EL1) + .value("DBGBCR11_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR11_EL1) + .value("DBGWVR11_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR11_EL1) + .value("DBGWCR11_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR11_EL1) + .value("DBGBVR12_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR12_EL1) + .value("DBGBCR12_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR12_EL1) + .value("DBGWVR12_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR12_EL1) + .value("DBGWCR12_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR12_EL1) + .value("DBGBVR13_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR13_EL1) + .value("DBGBCR13_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR13_EL1) + .value("DBGWVR13_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR13_EL1) + .value("DBGWCR13_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR13_EL1) + .value("DBGBVR14_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR14_EL1) + .value("DBGBCR14_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR14_EL1) + .value("DBGWVR14_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR14_EL1) + .value("DBGWCR14_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR14_EL1) + .value("DBGBVR15_EL1", LIEF::assembly::aarch64::SYSREG::DBGBVR15_EL1) + .value("DBGBCR15_EL1", LIEF::assembly::aarch64::SYSREG::DBGBCR15_EL1) + .value("DBGWVR15_EL1", LIEF::assembly::aarch64::SYSREG::DBGWVR15_EL1) + .value("DBGWCR15_EL1", LIEF::assembly::aarch64::SYSREG::DBGWCR15_EL1) + .value("MDRAR_EL1", LIEF::assembly::aarch64::SYSREG::MDRAR_EL1) + .value("OSLAR_EL1", LIEF::assembly::aarch64::SYSREG::OSLAR_EL1) + .value("OSLSR_EL1", LIEF::assembly::aarch64::SYSREG::OSLSR_EL1) + .value("OSDLR_EL1", LIEF::assembly::aarch64::SYSREG::OSDLR_EL1) + .value("DBGPRCR_EL1", LIEF::assembly::aarch64::SYSREG::DBGPRCR_EL1) + .value("DBGCLAIMSET_EL1", LIEF::assembly::aarch64::SYSREG::DBGCLAIMSET_EL1) + .value("DBGCLAIMCLR_EL1", LIEF::assembly::aarch64::SYSREG::DBGCLAIMCLR_EL1) + .value("DBGAUTHSTATUS_EL1", LIEF::assembly::aarch64::SYSREG::DBGAUTHSTATUS_EL1) + .value("SPMCGCR0_EL1", LIEF::assembly::aarch64::SYSREG::SPMCGCR0_EL1) + .value("SPMCGCR1_EL1", LIEF::assembly::aarch64::SYSREG::SPMCGCR1_EL1) + .value("SPMACCESSR_EL1", LIEF::assembly::aarch64::SYSREG::SPMACCESSR_EL1) + .value("SPMIIDR_EL1", LIEF::assembly::aarch64::SYSREG::SPMIIDR_EL1) + .value("SPMDEVARCH_EL1", LIEF::assembly::aarch64::SYSREG::SPMDEVARCH_EL1) + .value("SPMDEVAFF_EL1", LIEF::assembly::aarch64::SYSREG::SPMDEVAFF_EL1) + .value("SPMCFGR_EL1", LIEF::assembly::aarch64::SYSREG::SPMCFGR_EL1) + .value("SPMINTENSET_EL1", LIEF::assembly::aarch64::SYSREG::SPMINTENSET_EL1) + .value("SPMINTENCLR_EL1", LIEF::assembly::aarch64::SYSREG::SPMINTENCLR_EL1) + .value("PMEVCNTSVR0_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR0_EL1) + .value("PMEVCNTSVR1_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR1_EL1) + .value("PMEVCNTSVR2_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR2_EL1) + .value("PMEVCNTSVR3_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR3_EL1) + .value("PMEVCNTSVR4_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR4_EL1) + .value("PMEVCNTSVR5_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR5_EL1) + .value("PMEVCNTSVR6_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR6_EL1) + .value("PMEVCNTSVR7_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR7_EL1) + .value("PMEVCNTSVR8_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR8_EL1) + .value("PMEVCNTSVR9_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR9_EL1) + .value("PMEVCNTSVR10_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR10_EL1) + .value("PMEVCNTSVR11_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR11_EL1) + .value("PMEVCNTSVR12_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR12_EL1) + .value("PMEVCNTSVR13_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR13_EL1) + .value("PMEVCNTSVR14_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR14_EL1) + .value("PMEVCNTSVR15_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR15_EL1) + .value("PMEVCNTSVR16_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR16_EL1) + .value("PMEVCNTSVR17_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR17_EL1) + .value("PMEVCNTSVR18_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR18_EL1) + .value("PMEVCNTSVR19_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR19_EL1) + .value("PMEVCNTSVR20_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR20_EL1) + .value("PMEVCNTSVR21_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR21_EL1) + .value("PMEVCNTSVR22_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR22_EL1) + .value("PMEVCNTSVR23_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR23_EL1) + .value("PMEVCNTSVR24_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR24_EL1) + .value("PMEVCNTSVR25_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR25_EL1) + .value("PMEVCNTSVR26_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR26_EL1) + .value("PMEVCNTSVR27_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR27_EL1) + .value("PMEVCNTSVR28_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR28_EL1) + .value("PMEVCNTSVR29_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR29_EL1) + .value("PMEVCNTSVR30_EL1", LIEF::assembly::aarch64::SYSREG::PMEVCNTSVR30_EL1) + .value("PMCCNTSVR_EL1", LIEF::assembly::aarch64::SYSREG::PMCCNTSVR_EL1) + .value("PMICNTSVR_EL1", LIEF::assembly::aarch64::SYSREG::PMICNTSVR_EL1) + .value("TRCTRACEIDR", LIEF::assembly::aarch64::SYSREG::TRCTRACEIDR) + .value("TRCVICTLR", LIEF::assembly::aarch64::SYSREG::TRCVICTLR) + .value("TRCSEQEVR0", LIEF::assembly::aarch64::SYSREG::TRCSEQEVR0) + .value("TRCCNTRLDVR0", LIEF::assembly::aarch64::SYSREG::TRCCNTRLDVR0) + .value("TRCIDR8", LIEF::assembly::aarch64::SYSREG::TRCIDR8) + .value("TRCIMSPEC0", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC0) + .value("TRCPRGCTLR", LIEF::assembly::aarch64::SYSREG::TRCPRGCTLR) + .value("TRCQCTLR", LIEF::assembly::aarch64::SYSREG::TRCQCTLR) + .value("TRCVIIECTLR", LIEF::assembly::aarch64::SYSREG::TRCVIIECTLR) + .value("TRCSEQEVR1", LIEF::assembly::aarch64::SYSREG::TRCSEQEVR1) + .value("TRCCNTRLDVR1", LIEF::assembly::aarch64::SYSREG::TRCCNTRLDVR1) + .value("TRCIDR9", LIEF::assembly::aarch64::SYSREG::TRCIDR9) + .value("TRCIMSPEC1", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC1) + .value("TRCPROCSELR", LIEF::assembly::aarch64::SYSREG::TRCPROCSELR) + .value("TRCITEEDCR", LIEF::assembly::aarch64::SYSREG::TRCITEEDCR) + .value("TRCVISSCTLR", LIEF::assembly::aarch64::SYSREG::TRCVISSCTLR) + .value("TRCSEQEVR2", LIEF::assembly::aarch64::SYSREG::TRCSEQEVR2) + .value("TRCCNTRLDVR2", LIEF::assembly::aarch64::SYSREG::TRCCNTRLDVR2) + .value("TRCIDR10", LIEF::assembly::aarch64::SYSREG::TRCIDR10) + .value("TRCIMSPEC2", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC2) + .value("TRCSTATR", LIEF::assembly::aarch64::SYSREG::TRCSTATR) + .value("TRCVIPCSSCTLR", LIEF::assembly::aarch64::SYSREG::TRCVIPCSSCTLR) + .value("TRCCNTRLDVR3", LIEF::assembly::aarch64::SYSREG::TRCCNTRLDVR3) + .value("TRCIDR11", LIEF::assembly::aarch64::SYSREG::TRCIDR11) + .value("TRCIMSPEC3", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC3) + .value("TRCCONFIGR", LIEF::assembly::aarch64::SYSREG::TRCCONFIGR) + .value("TRCCNTCTLR0", LIEF::assembly::aarch64::SYSREG::TRCCNTCTLR0) + .value("TRCIDR12", LIEF::assembly::aarch64::SYSREG::TRCIDR12) + .value("TRCIMSPEC4", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC4) + .value("TRCCNTCTLR1", LIEF::assembly::aarch64::SYSREG::TRCCNTCTLR1) + .value("TRCIDR13", LIEF::assembly::aarch64::SYSREG::TRCIDR13) + .value("TRCIMSPEC5", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC5) + .value("TRCAUXCTLR", LIEF::assembly::aarch64::SYSREG::TRCAUXCTLR) + .value("TRCSEQRSTEVR", LIEF::assembly::aarch64::SYSREG::TRCSEQRSTEVR) + .value("TRCCNTCTLR2", LIEF::assembly::aarch64::SYSREG::TRCCNTCTLR2) + .value("TRCIMSPEC6", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC6) + .value("TRCSEQSTR", LIEF::assembly::aarch64::SYSREG::TRCSEQSTR) + .value("TRCCNTCTLR3", LIEF::assembly::aarch64::SYSREG::TRCCNTCTLR3) + .value("TRCIMSPEC7", LIEF::assembly::aarch64::SYSREG::TRCIMSPEC7) + .value("TRCEVENTCTL0R", LIEF::assembly::aarch64::SYSREG::TRCEVENTCTL0R) + .value("TRCVDCTLR", LIEF::assembly::aarch64::SYSREG::TRCVDCTLR) + .value("TRCEXTINSELR", LIEF::assembly::aarch64::SYSREG::TRCEXTINSELR) + .value("TRCCNTVR0", LIEF::assembly::aarch64::SYSREG::TRCCNTVR0) + .value("TRCIDR0", LIEF::assembly::aarch64::SYSREG::TRCIDR0) + .value("TRCEVENTCTL1R", LIEF::assembly::aarch64::SYSREG::TRCEVENTCTL1R) + .value("TRCVDSACCTLR", LIEF::assembly::aarch64::SYSREG::TRCVDSACCTLR) + .value("TRCEXTINSELR1", LIEF::assembly::aarch64::SYSREG::TRCEXTINSELR1) + .value("TRCCNTVR1", LIEF::assembly::aarch64::SYSREG::TRCCNTVR1) + .value("TRCIDR1", LIEF::assembly::aarch64::SYSREG::TRCIDR1) + .value("TRCRSR", LIEF::assembly::aarch64::SYSREG::TRCRSR) + .value("TRCVDARCCTLR", LIEF::assembly::aarch64::SYSREG::TRCVDARCCTLR) + .value("TRCEXTINSELR2", LIEF::assembly::aarch64::SYSREG::TRCEXTINSELR2) + .value("TRCCNTVR2", LIEF::assembly::aarch64::SYSREG::TRCCNTVR2) + .value("TRCIDR2", LIEF::assembly::aarch64::SYSREG::TRCIDR2) + .value("TRCSTALLCTLR", LIEF::assembly::aarch64::SYSREG::TRCSTALLCTLR) + .value("TRCEXTINSELR3", LIEF::assembly::aarch64::SYSREG::TRCEXTINSELR3) + .value("TRCCNTVR3", LIEF::assembly::aarch64::SYSREG::TRCCNTVR3) + .value("TRCIDR3", LIEF::assembly::aarch64::SYSREG::TRCIDR3) + .value("TRCTSCTLR", LIEF::assembly::aarch64::SYSREG::TRCTSCTLR) + .value("TRCIDR4", LIEF::assembly::aarch64::SYSREG::TRCIDR4) + .value("TRCSYNCPR", LIEF::assembly::aarch64::SYSREG::TRCSYNCPR) + .value("TRCIDR5", LIEF::assembly::aarch64::SYSREG::TRCIDR5) + .value("TRCCCCTLR", LIEF::assembly::aarch64::SYSREG::TRCCCCTLR) + .value("TRCIDR6", LIEF::assembly::aarch64::SYSREG::TRCIDR6) + .value("TRCBBCTLR", LIEF::assembly::aarch64::SYSREG::TRCBBCTLR) + .value("TRCIDR7", LIEF::assembly::aarch64::SYSREG::TRCIDR7) + .value("TRCRSCTLR16", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR16) + .value("TRCSSCCR0", LIEF::assembly::aarch64::SYSREG::TRCSSCCR0) + .value("TRCSSPCICR0", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR0) + .value("TRCOSLAR", LIEF::assembly::aarch64::SYSREG::TRCOSLAR) + .value("TRCRSCTLR17", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR17) + .value("TRCSSCCR1", LIEF::assembly::aarch64::SYSREG::TRCSSCCR1) + .value("TRCSSPCICR1", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR1) + .value("TRCOSLSR", LIEF::assembly::aarch64::SYSREG::TRCOSLSR) + .value("TRCRSCTLR2", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR2) + .value("TRCRSCTLR18", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR18) + .value("TRCSSCCR2", LIEF::assembly::aarch64::SYSREG::TRCSSCCR2) + .value("TRCSSPCICR2", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR2) + .value("TRCRSCTLR3", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR3) + .value("TRCRSCTLR19", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR19) + .value("TRCSSCCR3", LIEF::assembly::aarch64::SYSREG::TRCSSCCR3) + .value("TRCSSPCICR3", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR3) + .value("TRCRSCTLR4", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR4) + .value("TRCRSCTLR20", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR20) + .value("TRCSSCCR4", LIEF::assembly::aarch64::SYSREG::TRCSSCCR4) + .value("TRCSSPCICR4", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR4) + .value("TRCPDCR", LIEF::assembly::aarch64::SYSREG::TRCPDCR) + .value("TRCRSCTLR5", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR5) + .value("TRCRSCTLR21", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR21) + .value("TRCSSCCR5", LIEF::assembly::aarch64::SYSREG::TRCSSCCR5) + .value("TRCSSPCICR5", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR5) + .value("TRCPDSR", LIEF::assembly::aarch64::SYSREG::TRCPDSR) + .value("TRCRSCTLR6", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR6) + .value("TRCRSCTLR22", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR22) + .value("TRCSSCCR6", LIEF::assembly::aarch64::SYSREG::TRCSSCCR6) + .value("TRCSSPCICR6", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR6) + .value("TRCRSCTLR7", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR7) + .value("TRCRSCTLR23", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR23) + .value("TRCSSCCR7", LIEF::assembly::aarch64::SYSREG::TRCSSCCR7) + .value("TRCSSPCICR7", LIEF::assembly::aarch64::SYSREG::TRCSSPCICR7) + .value("TRCRSCTLR8", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR8) + .value("TRCRSCTLR24", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR24) + .value("TRCSSCSR0", LIEF::assembly::aarch64::SYSREG::TRCSSCSR0) + .value("TRCRSCTLR9", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR9) + .value("TRCRSCTLR25", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR25) + .value("TRCSSCSR1", LIEF::assembly::aarch64::SYSREG::TRCSSCSR1) + .value("TRCRSCTLR10", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR10) + .value("TRCRSCTLR26", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR26) + .value("TRCSSCSR2", LIEF::assembly::aarch64::SYSREG::TRCSSCSR2) + .value("TRCRSCTLR11", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR11) + .value("TRCRSCTLR27", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR27) + .value("TRCSSCSR3", LIEF::assembly::aarch64::SYSREG::TRCSSCSR3) + .value("TRCRSCTLR12", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR12) + .value("TRCRSCTLR28", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR28) + .value("TRCSSCSR4", LIEF::assembly::aarch64::SYSREG::TRCSSCSR4) + .value("TRCRSCTLR13", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR13) + .value("TRCRSCTLR29", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR29) + .value("TRCSSCSR5", LIEF::assembly::aarch64::SYSREG::TRCSSCSR5) + .value("TRCRSCTLR14", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR14) + .value("TRCRSCTLR30", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR30) + .value("TRCSSCSR6", LIEF::assembly::aarch64::SYSREG::TRCSSCSR6) + .value("TRCRSCTLR15", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR15) + .value("TRCRSCTLR31", LIEF::assembly::aarch64::SYSREG::TRCRSCTLR31) + .value("TRCSSCSR7", LIEF::assembly::aarch64::SYSREG::TRCSSCSR7) + .value("TRCACVR0", LIEF::assembly::aarch64::SYSREG::TRCACVR0) + .value("TRCACVR8", LIEF::assembly::aarch64::SYSREG::TRCACVR8) + .value("TRCACATR0", LIEF::assembly::aarch64::SYSREG::TRCACATR0) + .value("TRCACATR8", LIEF::assembly::aarch64::SYSREG::TRCACATR8) + .value("TRCDVCVR0", LIEF::assembly::aarch64::SYSREG::TRCDVCVR0) + .value("TRCDVCVR4", LIEF::assembly::aarch64::SYSREG::TRCDVCVR4) + .value("TRCDVCMR0", LIEF::assembly::aarch64::SYSREG::TRCDVCMR0) + .value("TRCDVCMR4", LIEF::assembly::aarch64::SYSREG::TRCDVCMR4) + .value("TRCACVR1", LIEF::assembly::aarch64::SYSREG::TRCACVR1) + .value("TRCACVR9", LIEF::assembly::aarch64::SYSREG::TRCACVR9) + .value("TRCACATR1", LIEF::assembly::aarch64::SYSREG::TRCACATR1) + .value("TRCACATR9", LIEF::assembly::aarch64::SYSREG::TRCACATR9) + .value("TRCACVR2", LIEF::assembly::aarch64::SYSREG::TRCACVR2) + .value("TRCACVR10", LIEF::assembly::aarch64::SYSREG::TRCACVR10) + .value("TRCACATR2", LIEF::assembly::aarch64::SYSREG::TRCACATR2) + .value("TRCACATR10", LIEF::assembly::aarch64::SYSREG::TRCACATR10) + .value("TRCDVCVR1", LIEF::assembly::aarch64::SYSREG::TRCDVCVR1) + .value("TRCDVCVR5", LIEF::assembly::aarch64::SYSREG::TRCDVCVR5) + .value("TRCDVCMR1", LIEF::assembly::aarch64::SYSREG::TRCDVCMR1) + .value("TRCDVCMR5", LIEF::assembly::aarch64::SYSREG::TRCDVCMR5) + .value("TRCACVR3", LIEF::assembly::aarch64::SYSREG::TRCACVR3) + .value("TRCACVR11", LIEF::assembly::aarch64::SYSREG::TRCACVR11) + .value("TRCACATR3", LIEF::assembly::aarch64::SYSREG::TRCACATR3) + .value("TRCACATR11", LIEF::assembly::aarch64::SYSREG::TRCACATR11) + .value("TRCACVR4", LIEF::assembly::aarch64::SYSREG::TRCACVR4) + .value("TRCACVR12", LIEF::assembly::aarch64::SYSREG::TRCACVR12) + .value("TRCACATR4", LIEF::assembly::aarch64::SYSREG::TRCACATR4) + .value("TRCACATR12", LIEF::assembly::aarch64::SYSREG::TRCACATR12) + .value("TRCDVCVR2", LIEF::assembly::aarch64::SYSREG::TRCDVCVR2) + .value("TRCDVCVR6", LIEF::assembly::aarch64::SYSREG::TRCDVCVR6) + .value("TRCDVCMR2", LIEF::assembly::aarch64::SYSREG::TRCDVCMR2) + .value("TRCDVCMR6", LIEF::assembly::aarch64::SYSREG::TRCDVCMR6) + .value("TRCACVR5", LIEF::assembly::aarch64::SYSREG::TRCACVR5) + .value("TRCACVR13", LIEF::assembly::aarch64::SYSREG::TRCACVR13) + .value("TRCACATR5", LIEF::assembly::aarch64::SYSREG::TRCACATR5) + .value("TRCACATR13", LIEF::assembly::aarch64::SYSREG::TRCACATR13) + .value("TRCACVR6", LIEF::assembly::aarch64::SYSREG::TRCACVR6) + .value("TRCACVR14", LIEF::assembly::aarch64::SYSREG::TRCACVR14) + .value("TRCACATR6", LIEF::assembly::aarch64::SYSREG::TRCACATR6) + .value("TRCACATR14", LIEF::assembly::aarch64::SYSREG::TRCACATR14) + .value("TRCDVCVR3", LIEF::assembly::aarch64::SYSREG::TRCDVCVR3) + .value("TRCDVCVR7", LIEF::assembly::aarch64::SYSREG::TRCDVCVR7) + .value("TRCDVCMR3", LIEF::assembly::aarch64::SYSREG::TRCDVCMR3) + .value("TRCDVCMR7", LIEF::assembly::aarch64::SYSREG::TRCDVCMR7) + .value("TRCACVR7", LIEF::assembly::aarch64::SYSREG::TRCACVR7) + .value("TRCACVR15", LIEF::assembly::aarch64::SYSREG::TRCACVR15) + .value("TRCACATR7", LIEF::assembly::aarch64::SYSREG::TRCACATR7) + .value("TRCACATR15", LIEF::assembly::aarch64::SYSREG::TRCACATR15) + .value("TRCCIDCVR0", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR0) + .value("TRCVMIDCVR0", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR0) + .value("TRCCIDCCTLR0", LIEF::assembly::aarch64::SYSREG::TRCCIDCCTLR0) + .value("TRCCIDCCTLR1", LIEF::assembly::aarch64::SYSREG::TRCCIDCCTLR1) + .value("TRCCIDCVR1", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR1) + .value("TRCVMIDCVR1", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR1) + .value("TRCVMIDCCTLR0", LIEF::assembly::aarch64::SYSREG::TRCVMIDCCTLR0); + reg.value("TRCVMIDCCTLR1", LIEF::assembly::aarch64::SYSREG::TRCVMIDCCTLR1) + .value("TRCCIDCVR2", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR2) + .value("TRCVMIDCVR2", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR2) + .value("TRCCIDCVR3", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR3) + .value("TRCVMIDCVR3", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR3) + .value("TRCCIDCVR4", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR4) + .value("TRCVMIDCVR4", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR4) + .value("TRCCIDCVR5", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR5) + .value("TRCVMIDCVR5", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR5) + .value("TRCCIDCVR6", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR6) + .value("TRCVMIDCVR6", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR6) + .value("TRCCIDCVR7", LIEF::assembly::aarch64::SYSREG::TRCCIDCVR7) + .value("TRCVMIDCVR7", LIEF::assembly::aarch64::SYSREG::TRCVMIDCVR7) + .value("TRCITCTRL", LIEF::assembly::aarch64::SYSREG::TRCITCTRL) + .value("TRCDEVID", LIEF::assembly::aarch64::SYSREG::TRCDEVID) + .value("TRCDEVTYPE", LIEF::assembly::aarch64::SYSREG::TRCDEVTYPE) + .value("TRCPIDR4", LIEF::assembly::aarch64::SYSREG::TRCPIDR4) + .value("TRCPIDR5", LIEF::assembly::aarch64::SYSREG::TRCPIDR5) + .value("TRCPIDR6", LIEF::assembly::aarch64::SYSREG::TRCPIDR6) + .value("TRCPIDR7", LIEF::assembly::aarch64::SYSREG::TRCPIDR7) + .value("TRCCLAIMSET", LIEF::assembly::aarch64::SYSREG::TRCCLAIMSET) + .value("TRCPIDR0", LIEF::assembly::aarch64::SYSREG::TRCPIDR0) + .value("TRCCLAIMCLR", LIEF::assembly::aarch64::SYSREG::TRCCLAIMCLR) + .value("TRCPIDR1", LIEF::assembly::aarch64::SYSREG::TRCPIDR1) + .value("TRCDEVAFF0", LIEF::assembly::aarch64::SYSREG::TRCDEVAFF0) + .value("TRCPIDR2", LIEF::assembly::aarch64::SYSREG::TRCPIDR2) + .value("TRCDEVAFF1", LIEF::assembly::aarch64::SYSREG::TRCDEVAFF1) + .value("TRCPIDR3", LIEF::assembly::aarch64::SYSREG::TRCPIDR3) + .value("TRCLAR", LIEF::assembly::aarch64::SYSREG::TRCLAR) + .value("TRCCIDR0", LIEF::assembly::aarch64::SYSREG::TRCCIDR0) + .value("TRCLSR", LIEF::assembly::aarch64::SYSREG::TRCLSR) + .value("TRCCIDR1", LIEF::assembly::aarch64::SYSREG::TRCCIDR1) + .value("TRCAUTHSTATUS", LIEF::assembly::aarch64::SYSREG::TRCAUTHSTATUS) + .value("TRCCIDR2", LIEF::assembly::aarch64::SYSREG::TRCCIDR2) + .value("TRCDEVARCH", LIEF::assembly::aarch64::SYSREG::TRCDEVARCH) + .value("TRCCIDR3", LIEF::assembly::aarch64::SYSREG::TRCCIDR3) + .value("BRBINF0_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF0_EL1) + .value("BRBSRC0_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC0_EL1) + .value("BRBTGT0_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT0_EL1) + .value("BRBINF16_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF16_EL1) + .value("BRBSRC16_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC16_EL1) + .value("BRBTGT16_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT16_EL1) + .value("BRBINF1_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF1_EL1) + .value("BRBSRC1_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC1_EL1) + .value("BRBTGT1_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT1_EL1) + .value("BRBINF17_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF17_EL1) + .value("BRBSRC17_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC17_EL1) + .value("BRBTGT17_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT17_EL1) + .value("BRBINF2_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF2_EL1) + .value("BRBSRC2_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC2_EL1) + .value("BRBTGT2_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT2_EL1) + .value("BRBINF18_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF18_EL1) + .value("BRBSRC18_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC18_EL1) + .value("BRBTGT18_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT18_EL1) + .value("BRBINF3_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF3_EL1) + .value("BRBSRC3_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC3_EL1) + .value("BRBTGT3_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT3_EL1) + .value("BRBINF19_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF19_EL1) + .value("BRBSRC19_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC19_EL1) + .value("BRBTGT19_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT19_EL1) + .value("BRBINF4_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF4_EL1) + .value("BRBSRC4_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC4_EL1) + .value("BRBTGT4_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT4_EL1) + .value("BRBINF20_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF20_EL1) + .value("BRBSRC20_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC20_EL1) + .value("BRBTGT20_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT20_EL1) + .value("BRBINF5_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF5_EL1) + .value("BRBSRC5_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC5_EL1) + .value("BRBTGT5_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT5_EL1) + .value("BRBINF21_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF21_EL1) + .value("BRBSRC21_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC21_EL1) + .value("BRBTGT21_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT21_EL1) + .value("BRBINF6_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF6_EL1) + .value("BRBSRC6_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC6_EL1) + .value("BRBTGT6_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT6_EL1) + .value("BRBINF22_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF22_EL1) + .value("BRBSRC22_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC22_EL1) + .value("BRBTGT22_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT22_EL1) + .value("BRBINF7_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF7_EL1) + .value("BRBSRC7_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC7_EL1) + .value("BRBTGT7_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT7_EL1) + .value("BRBINF23_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF23_EL1) + .value("BRBSRC23_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC23_EL1) + .value("BRBTGT23_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT23_EL1) + .value("BRBINF8_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF8_EL1) + .value("BRBSRC8_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC8_EL1) + .value("BRBTGT8_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT8_EL1) + .value("BRBINF24_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF24_EL1) + .value("BRBSRC24_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC24_EL1) + .value("BRBTGT24_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT24_EL1) + .value("BRBINF9_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF9_EL1) + .value("BRBSRC9_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC9_EL1) + .value("BRBTGT9_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT9_EL1) + .value("BRBINF25_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF25_EL1) + .value("BRBSRC25_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC25_EL1) + .value("BRBTGT25_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT25_EL1) + .value("BRBINF10_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF10_EL1) + .value("BRBSRC10_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC10_EL1) + .value("BRBTGT10_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT10_EL1) + .value("BRBINF26_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF26_EL1) + .value("BRBSRC26_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC26_EL1) + .value("BRBTGT26_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT26_EL1) + .value("BRBINF11_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF11_EL1) + .value("BRBSRC11_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC11_EL1) + .value("BRBTGT11_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT11_EL1) + .value("BRBINF27_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF27_EL1) + .value("BRBSRC27_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC27_EL1) + .value("BRBTGT27_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT27_EL1) + .value("BRBINF12_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF12_EL1) + .value("BRBSRC12_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC12_EL1) + .value("BRBTGT12_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT12_EL1) + .value("BRBINF28_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF28_EL1) + .value("BRBSRC28_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC28_EL1) + .value("BRBTGT28_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT28_EL1) + .value("BRBINF13_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF13_EL1) + .value("BRBSRC13_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC13_EL1) + .value("BRBTGT13_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT13_EL1) + .value("BRBINF29_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF29_EL1) + .value("BRBSRC29_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC29_EL1) + .value("BRBTGT29_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT29_EL1) + .value("BRBINF14_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF14_EL1) + .value("BRBSRC14_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC14_EL1) + .value("BRBTGT14_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT14_EL1) + .value("BRBINF30_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF30_EL1) + .value("BRBSRC30_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC30_EL1) + .value("BRBTGT30_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT30_EL1) + .value("BRBINF15_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF15_EL1) + .value("BRBSRC15_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC15_EL1) + .value("BRBTGT15_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT15_EL1) + .value("BRBINF31_EL1", LIEF::assembly::aarch64::SYSREG::BRBINF31_EL1) + .value("BRBSRC31_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRC31_EL1) + .value("BRBTGT31_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGT31_EL1) + .value("BRBCR_EL1", LIEF::assembly::aarch64::SYSREG::BRBCR_EL1) + .value("BRBFCR_EL1", LIEF::assembly::aarch64::SYSREG::BRBFCR_EL1) + .value("BRBTS_EL1", LIEF::assembly::aarch64::SYSREG::BRBTS_EL1) + .value("BRBINFINJ_EL1", LIEF::assembly::aarch64::SYSREG::BRBINFINJ_EL1) + .value("BRBSRCINJ_EL1", LIEF::assembly::aarch64::SYSREG::BRBSRCINJ_EL1) + .value("BRBTGTINJ_EL1", LIEF::assembly::aarch64::SYSREG::BRBTGTINJ_EL1) + .value("BRBIDR0_EL1", LIEF::assembly::aarch64::SYSREG::BRBIDR0_EL1) + .value("TEECR32_EL1", LIEF::assembly::aarch64::SYSREG::TEECR32_EL1) + .value("TEEHBR32_EL1", LIEF::assembly::aarch64::SYSREG::TEEHBR32_EL1) + .value("MDCCSR_EL0", LIEF::assembly::aarch64::SYSREG::MDCCSR_EL0) + .value("DBGDTR_EL0", LIEF::assembly::aarch64::SYSREG::DBGDTR_EL0) + .value("DBGDTRRX_EL0", LIEF::assembly::aarch64::SYSREG::DBGDTRRX_EL0) + .value("SPMCR_EL0", LIEF::assembly::aarch64::SYSREG::SPMCR_EL0) + .value("SPMCNTENSET_EL0", LIEF::assembly::aarch64::SYSREG::SPMCNTENSET_EL0) + .value("SPMCNTENCLR_EL0", LIEF::assembly::aarch64::SYSREG::SPMCNTENCLR_EL0) + .value("SPMOVSCLR_EL0", LIEF::assembly::aarch64::SYSREG::SPMOVSCLR_EL0) + .value("SPMZR_EL0", LIEF::assembly::aarch64::SYSREG::SPMZR_EL0) + .value("SPMSELR_EL0", LIEF::assembly::aarch64::SYSREG::SPMSELR_EL0) + .value("SPMOVSSET_EL0", LIEF::assembly::aarch64::SYSREG::SPMOVSSET_EL0) + .value("SPMEVCNTR0_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR0_EL0) + .value("SPMEVCNTR1_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR1_EL0) + .value("SPMEVCNTR2_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR2_EL0) + .value("SPMEVCNTR3_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR3_EL0) + .value("SPMEVCNTR4_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR4_EL0) + .value("SPMEVCNTR5_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR5_EL0) + .value("SPMEVCNTR6_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR6_EL0) + .value("SPMEVCNTR7_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR7_EL0) + .value("SPMEVCNTR8_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR8_EL0) + .value("SPMEVCNTR9_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR9_EL0) + .value("SPMEVCNTR10_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR10_EL0) + .value("SPMEVCNTR11_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR11_EL0) + .value("SPMEVCNTR12_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR12_EL0) + .value("SPMEVCNTR13_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR13_EL0) + .value("SPMEVCNTR14_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR14_EL0) + .value("SPMEVCNTR15_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVCNTR15_EL0) + .value("SPMEVTYPER0_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER0_EL0) + .value("SPMEVTYPER1_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER1_EL0) + .value("SPMEVTYPER2_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER2_EL0) + .value("SPMEVTYPER3_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER3_EL0) + .value("SPMEVTYPER4_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER4_EL0) + .value("SPMEVTYPER5_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER5_EL0) + .value("SPMEVTYPER6_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER6_EL0) + .value("SPMEVTYPER7_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER7_EL0) + .value("SPMEVTYPER8_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER8_EL0) + .value("SPMEVTYPER9_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER9_EL0) + .value("SPMEVTYPER10_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER10_EL0) + .value("SPMEVTYPER11_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER11_EL0) + .value("SPMEVTYPER12_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER12_EL0) + .value("SPMEVTYPER13_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER13_EL0) + .value("SPMEVTYPER14_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER14_EL0) + .value("SPMEVTYPER15_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVTYPER15_EL0) + .value("SPMEVFILTR0_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR0_EL0) + .value("SPMEVFILTR1_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR1_EL0) + .value("SPMEVFILTR2_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR2_EL0) + .value("SPMEVFILTR3_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR3_EL0) + .value("SPMEVFILTR4_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR4_EL0) + .value("SPMEVFILTR5_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR5_EL0) + .value("SPMEVFILTR6_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR6_EL0) + .value("SPMEVFILTR7_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR7_EL0) + .value("SPMEVFILTR8_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR8_EL0) + .value("SPMEVFILTR9_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR9_EL0) + .value("SPMEVFILTR10_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR10_EL0) + .value("SPMEVFILTR11_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR11_EL0) + .value("SPMEVFILTR12_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR12_EL0) + .value("SPMEVFILTR13_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR13_EL0) + .value("SPMEVFILTR14_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR14_EL0) + .value("SPMEVFILTR15_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILTR15_EL0) + .value("SPMEVFILT2R0_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R0_EL0) + .value("SPMEVFILT2R1_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R1_EL0) + .value("SPMEVFILT2R2_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R2_EL0) + .value("SPMEVFILT2R3_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R3_EL0) + .value("SPMEVFILT2R4_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R4_EL0) + .value("SPMEVFILT2R5_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R5_EL0) + .value("SPMEVFILT2R6_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R6_EL0) + .value("SPMEVFILT2R7_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R7_EL0) + .value("SPMEVFILT2R8_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R8_EL0) + .value("SPMEVFILT2R9_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R9_EL0) + .value("SPMEVFILT2R10_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R10_EL0) + .value("SPMEVFILT2R11_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R11_EL0) + .value("SPMEVFILT2R12_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R12_EL0) + .value("SPMEVFILT2R13_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R13_EL0) + .value("SPMEVFILT2R14_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R14_EL0) + .value("SPMEVFILT2R15_EL0", LIEF::assembly::aarch64::SYSREG::SPMEVFILT2R15_EL0) + .value("DBGVCR32_EL2", LIEF::assembly::aarch64::SYSREG::DBGVCR32_EL2) + .value("BRBCR_EL2", LIEF::assembly::aarch64::SYSREG::BRBCR_EL2) + .value("SPMACCESSR_EL2", LIEF::assembly::aarch64::SYSREG::SPMACCESSR_EL2) + .value("BRBCR_EL12", LIEF::assembly::aarch64::SYSREG::BRBCR_EL12) + .value("SPMACCESSR_EL12", LIEF::assembly::aarch64::SYSREG::SPMACCESSR_EL12) + .value("SPMACCESSR_EL3", LIEF::assembly::aarch64::SYSREG::SPMACCESSR_EL3) + .value("SPMROOTCR_EL3", LIEF::assembly::aarch64::SYSREG::SPMROOTCR_EL3) + .value("SPMSCR_EL1", LIEF::assembly::aarch64::SYSREG::SPMSCR_EL1) + .value("MIDR_EL1", LIEF::assembly::aarch64::SYSREG::MIDR_EL1) + .value("MPUIR_EL1", LIEF::assembly::aarch64::SYSREG::MPUIR_EL1) + .value("MPIDR_EL1", LIEF::assembly::aarch64::SYSREG::MPIDR_EL1) + .value("REVIDR_EL1", LIEF::assembly::aarch64::SYSREG::REVIDR_EL1) + .value("ID_PFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_PFR0_EL1) + .value("ID_PFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_PFR1_EL1) + .value("ID_DFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_DFR0_EL1) + .value("ID_AFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AFR0_EL1) + .value("ID_MMFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR0_EL1) + .value("ID_MMFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR1_EL1) + .value("ID_MMFR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR2_EL1) + .value("ID_MMFR3_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR3_EL1) + .value("ID_ISAR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR0_EL1) + .value("ID_ISAR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR1_EL1) + .value("ID_ISAR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR2_EL1) + .value("ID_ISAR3_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR3_EL1) + .value("ID_ISAR4_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR4_EL1) + .value("ID_ISAR5_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR5_EL1) + .value("ID_MMFR4_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR4_EL1) + .value("ID_ISAR6_EL1", LIEF::assembly::aarch64::SYSREG::ID_ISAR6_EL1) + .value("MVFR0_EL1", LIEF::assembly::aarch64::SYSREG::MVFR0_EL1) + .value("MVFR1_EL1", LIEF::assembly::aarch64::SYSREG::MVFR1_EL1) + .value("MVFR2_EL1", LIEF::assembly::aarch64::SYSREG::MVFR2_EL1) + .value("ID_PFR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_PFR2_EL1) + .value("ID_DFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_DFR1_EL1) + .value("ID_MMFR5_EL1", LIEF::assembly::aarch64::SYSREG::ID_MMFR5_EL1) + .value("ID_AA64PFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64PFR0_EL1) + .value("ID_AA64PFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64PFR1_EL1) + .value("ID_AA64PFR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64PFR2_EL1) + .value("ID_AA64ZFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64ZFR0_EL1) + .value("ID_AA64SMFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64SMFR0_EL1) + .value("ID_AA64FPFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64FPFR0_EL1) + .value("ID_AA64DFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64DFR0_EL1) + .value("ID_AA64DFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64DFR1_EL1) + .value("ID_AA64DFR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64DFR2_EL1) + .value("ID_AA64AFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64AFR0_EL1) + .value("ID_AA64AFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64AFR1_EL1) + .value("ID_AA64ISAR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64ISAR0_EL1) + .value("ID_AA64ISAR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64ISAR1_EL1) + .value("ID_AA64ISAR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64ISAR2_EL1) + .value("ID_AA64ISAR3_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64ISAR3_EL1) + .value("ID_AA64MMFR0_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64MMFR0_EL1) + .value("ID_AA64MMFR1_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64MMFR1_EL1) + .value("ID_AA64MMFR2_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64MMFR2_EL1) + .value("ID_AA64MMFR3_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64MMFR3_EL1) + .value("ID_AA64MMFR4_EL1", LIEF::assembly::aarch64::SYSREG::ID_AA64MMFR4_EL1) + .value("SCTLR_EL1", LIEF::assembly::aarch64::SYSREG::SCTLR_EL1) + .value("ACTLR_EL1", LIEF::assembly::aarch64::SYSREG::ACTLR_EL1) + .value("CPACR_EL1", LIEF::assembly::aarch64::SYSREG::CPACR_EL1) + .value("SCTLR2_EL1", LIEF::assembly::aarch64::SYSREG::SCTLR2_EL1) + .value("RGSR_EL1", LIEF::assembly::aarch64::SYSREG::RGSR_EL1) + .value("GCR_EL1", LIEF::assembly::aarch64::SYSREG::GCR_EL1) + .value("ZCR_EL1", LIEF::assembly::aarch64::SYSREG::ZCR_EL1) + .value("TRFCR_EL1", LIEF::assembly::aarch64::SYSREG::TRFCR_EL1) + .value("TRCITECR_EL1", LIEF::assembly::aarch64::SYSREG::TRCITECR_EL1) + .value("SMPRI_EL1", LIEF::assembly::aarch64::SYSREG::SMPRI_EL1) + .value("SMCR_EL1", LIEF::assembly::aarch64::SYSREG::SMCR_EL1) + .value("SCTLRMASK_EL1", LIEF::assembly::aarch64::SYSREG::SCTLRMASK_EL1) + .value("ACTLRMASK_EL1", LIEF::assembly::aarch64::SYSREG::ACTLRMASK_EL1) + .value("CPACRMASK_EL1", LIEF::assembly::aarch64::SYSREG::CPACRMASK_EL1) + .value("SCTLR2MASK_EL1", LIEF::assembly::aarch64::SYSREG::SCTLR2MASK_EL1) + .value("CPACRALIAS_EL1", LIEF::assembly::aarch64::SYSREG::CPACRALIAS_EL1) + .value("ACTLRALIAS_EL1", LIEF::assembly::aarch64::SYSREG::ACTLRALIAS_EL1) + .value("SCTLRALIAS_EL1", LIEF::assembly::aarch64::SYSREG::SCTLRALIAS_EL1) + .value("SCTLR2ALIAS_EL1", LIEF::assembly::aarch64::SYSREG::SCTLR2ALIAS_EL1) + .value("TTBR0_EL1", LIEF::assembly::aarch64::SYSREG::TTBR0_EL1) + .value("TTBR1_EL1", LIEF::assembly::aarch64::SYSREG::TTBR1_EL1) + .value("TCR_EL1", LIEF::assembly::aarch64::SYSREG::TCR_EL1) + .value("TCR2_EL1", LIEF::assembly::aarch64::SYSREG::TCR2_EL1) + .value("IRTBRU_EL1", LIEF::assembly::aarch64::SYSREG::IRTBRU_EL1) + .value("IRTBRP_EL1", LIEF::assembly::aarch64::SYSREG::IRTBRP_EL1) + .value("DPOTBR0_EL1", LIEF::assembly::aarch64::SYSREG::DPOTBR0_EL1) + .value("DPOTBR1_EL1", LIEF::assembly::aarch64::SYSREG::DPOTBR1_EL1) + .value("APIAKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APIAKeyLo_EL1) + .value("APIAKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APIAKeyHi_EL1) + .value("APIBKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APIBKeyLo_EL1) + .value("APIBKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APIBKeyHi_EL1); + reg.value("LDSTT_EL1", LIEF::assembly::aarch64::SYSREG::LDSTT_EL1) + .value("APDAKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APDAKeyLo_EL1) + .value("APDAKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APDAKeyHi_EL1) + .value("APDBKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APDBKeyLo_EL1) + .value("APDBKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APDBKeyHi_EL1) + .value("TPMIN0_EL1", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL1) + .value("TPMAX0_EL1", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL1) + .value("TPMIN1_EL1", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL1) + .value("TPMAX1_EL1", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL1) + .value("APGAKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APGAKeyLo_EL1) + .value("APGAKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APGAKeyHi_EL1) + .value("GCSCR_EL1", LIEF::assembly::aarch64::SYSREG::GCSCR_EL1) + .value("GCSPR_EL1", LIEF::assembly::aarch64::SYSREG::GCSPR_EL1) + .value("GCSCRE0_EL1", LIEF::assembly::aarch64::SYSREG::GCSCRE0_EL1) + .value("TCRMASK_EL1", LIEF::assembly::aarch64::SYSREG::TCRMASK_EL1) + .value("TCR2MASK_EL1", LIEF::assembly::aarch64::SYSREG::TCR2MASK_EL1) + .value("TCRALIAS_EL1", LIEF::assembly::aarch64::SYSREG::TCRALIAS_EL1) + .value("TCR2ALIAS_EL1", LIEF::assembly::aarch64::SYSREG::TCR2ALIAS_EL1) + .value("FGDTP0_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP0_EL1) + .value("FGDTP1_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP1_EL1) + .value("FGDTP2_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP2_EL1) + .value("FGDTP3_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP3_EL1) + .value("FGDTP4_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP4_EL1) + .value("FGDTP5_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP5_EL1) + .value("FGDTP6_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP6_EL1) + .value("FGDTP7_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP7_EL1) + .value("FGDTP8_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP8_EL1) + .value("FGDTP9_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP9_EL1) + .value("FGDTP10_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP10_EL1) + .value("FGDTP11_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP11_EL1) + .value("FGDTP12_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP12_EL1) + .value("FGDTP13_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP13_EL1) + .value("FGDTP14_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP14_EL1) + .value("FGDTP15_EL1", LIEF::assembly::aarch64::SYSREG::FGDTP15_EL1) + .value("FGDTU0_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU0_EL1) + .value("FGDTU1_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU1_EL1) + .value("FGDTU2_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU2_EL1) + .value("FGDTU3_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU3_EL1) + .value("FGDTU4_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU4_EL1) + .value("FGDTU5_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU5_EL1) + .value("FGDTU6_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU6_EL1) + .value("FGDTU7_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU7_EL1) + .value("FGDTU8_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU8_EL1) + .value("FGDTU9_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU9_EL1) + .value("FGDTU10_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU10_EL1) + .value("FGDTU11_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU11_EL1) + .value("FGDTU12_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU12_EL1) + .value("FGDTU13_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU13_EL1) + .value("FGDTU14_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU14_EL1) + .value("FGDTU15_EL1", LIEF::assembly::aarch64::SYSREG::FGDTU15_EL1) + .value("AFGDTP0_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP0_EL1) + .value("AFGDTP1_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP1_EL1) + .value("AFGDTP2_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP2_EL1) + .value("AFGDTP3_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP3_EL1) + .value("AFGDTP4_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP4_EL1) + .value("AFGDTP5_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP5_EL1) + .value("AFGDTP6_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP6_EL1) + .value("AFGDTP7_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP7_EL1) + .value("AFGDTP8_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP8_EL1) + .value("AFGDTP9_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP9_EL1) + .value("AFGDTP10_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP10_EL1) + .value("AFGDTP11_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP11_EL1) + .value("AFGDTP12_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP12_EL1) + .value("AFGDTP13_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP13_EL1) + .value("AFGDTP14_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP14_EL1) + .value("AFGDTP15_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTP15_EL1) + .value("AFGDTU0_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU0_EL1) + .value("AFGDTU1_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU1_EL1) + .value("AFGDTU2_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU2_EL1) + .value("AFGDTU3_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU3_EL1) + .value("AFGDTU4_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU4_EL1) + .value("AFGDTU5_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU5_EL1) + .value("AFGDTU6_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU6_EL1) + .value("AFGDTU7_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU7_EL1) + .value("AFGDTU8_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU8_EL1) + .value("AFGDTU9_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU9_EL1) + .value("AFGDTU10_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU10_EL1) + .value("AFGDTU11_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU11_EL1) + .value("AFGDTU12_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU12_EL1) + .value("AFGDTU13_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU13_EL1) + .value("AFGDTU14_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU14_EL1) + .value("AFGDTU15_EL1", LIEF::assembly::aarch64::SYSREG::AFGDTU15_EL1) + .value("SPSR_EL1", LIEF::assembly::aarch64::SYSREG::SPSR_EL1) + .value("ELR_EL1", LIEF::assembly::aarch64::SYSREG::ELR_EL1) + .value("STINDEX_EL1", LIEF::assembly::aarch64::SYSREG::STINDEX_EL1) + .value("TINDEX_EL1", LIEF::assembly::aarch64::SYSREG::TINDEX_EL1) + .value("SP_EL0", LIEF::assembly::aarch64::SYSREG::SP_EL0) + .value("SPSel", LIEF::assembly::aarch64::SYSREG::SPSel) + .value("CurrentEL", LIEF::assembly::aarch64::SYSREG::CurrentEL) + .value("PAN", LIEF::assembly::aarch64::SYSREG::PAN) + .value("UAO", LIEF::assembly::aarch64::SYSREG::UAO) + .value("ALLINT", LIEF::assembly::aarch64::SYSREG::ALLINT) + .value("PM", LIEF::assembly::aarch64::SYSREG::PM) + .value("ICC_PMR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PMR_EL1) + .value("AFSR0_EL1", LIEF::assembly::aarch64::SYSREG::AFSR0_EL1) + .value("AFSR1_EL1", LIEF::assembly::aarch64::SYSREG::AFSR1_EL1) + .value("ESR_EL1", LIEF::assembly::aarch64::SYSREG::ESR_EL1) + .value("ERRIDR_EL1", LIEF::assembly::aarch64::SYSREG::ERRIDR_EL1) + .value("ERRSELR_EL1", LIEF::assembly::aarch64::SYSREG::ERRSELR_EL1) + .value("ERXGSR_EL1", LIEF::assembly::aarch64::SYSREG::ERXGSR_EL1) + .value("ERXFR_EL1", LIEF::assembly::aarch64::SYSREG::ERXFR_EL1) + .value("ERXCTLR_EL1", LIEF::assembly::aarch64::SYSREG::ERXCTLR_EL1) + .value("ERXSTATUS_EL1", LIEF::assembly::aarch64::SYSREG::ERXSTATUS_EL1) + .value("ERXADDR_EL1", LIEF::assembly::aarch64::SYSREG::ERXADDR_EL1) + .value("ERXPFGF_EL1", LIEF::assembly::aarch64::SYSREG::ERXPFGF_EL1) + .value("ERXPFGCTL_EL1", LIEF::assembly::aarch64::SYSREG::ERXPFGCTL_EL1) + .value("ERXPFGCDN_EL1", LIEF::assembly::aarch64::SYSREG::ERXPFGCDN_EL1) + .value("ERXMISC0_EL1", LIEF::assembly::aarch64::SYSREG::ERXMISC0_EL1) + .value("ERXMISC1_EL1", LIEF::assembly::aarch64::SYSREG::ERXMISC1_EL1) + .value("ERXMISC2_EL1", LIEF::assembly::aarch64::SYSREG::ERXMISC2_EL1) + .value("ERXMISC3_EL1", LIEF::assembly::aarch64::SYSREG::ERXMISC3_EL1) + .value("TFSR_EL1", LIEF::assembly::aarch64::SYSREG::TFSR_EL1) + .value("TFSRE0_EL1", LIEF::assembly::aarch64::SYSREG::TFSRE0_EL1) + .value("FAR_EL1", LIEF::assembly::aarch64::SYSREG::FAR_EL1) + .value("PFAR_EL1", LIEF::assembly::aarch64::SYSREG::PFAR_EL1) + .value("PRENR_EL1", LIEF::assembly::aarch64::SYSREG::PRENR_EL1) + .value("PRSELR_EL1", LIEF::assembly::aarch64::SYSREG::PRSELR_EL1) + .value("PRBAR_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR_EL1) + .value("PRLAR_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR_EL1) + .value("PRBAR1_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR1_EL1) + .value("PRLAR1_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR1_EL1) + .value("PRBAR2_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR2_EL1) + .value("PRLAR2_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR2_EL1) + .value("PRBAR3_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR3_EL1) + .value("PRLAR3_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR3_EL1) + .value("PRBAR4_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR4_EL1) + .value("PRLAR4_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR4_EL1) + .value("PRBAR5_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR5_EL1) + .value("PRLAR5_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR5_EL1) + .value("PRBAR6_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR6_EL1) + .value("PRLAR6_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR6_EL1) + .value("PRBAR7_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR7_EL1) + .value("PRLAR7_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR7_EL1) + .value("PRBAR8_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR8_EL1) + .value("PRLAR8_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR8_EL1) + .value("PRBAR9_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR9_EL1) + .value("PRLAR9_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR9_EL1) + .value("PRBAR10_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR10_EL1) + .value("PRLAR10_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR10_EL1) + .value("PRBAR11_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR11_EL1) + .value("PRLAR11_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR11_EL1) + .value("PRBAR12_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR12_EL1) + .value("PRLAR12_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR12_EL1) + .value("PRBAR13_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR13_EL1) + .value("PRLAR13_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR13_EL1) + .value("PRBAR14_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR14_EL1) + .value("PRLAR14_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR14_EL1) + .value("PRBAR15_EL1", LIEF::assembly::aarch64::SYSREG::PRBAR15_EL1) + .value("PRLAR15_EL1", LIEF::assembly::aarch64::SYSREG::PRLAR15_EL1) + .value("PAR_EL1", LIEF::assembly::aarch64::SYSREG::PAR_EL1) + .value("PMSCR_EL1", LIEF::assembly::aarch64::SYSREG::PMSCR_EL1) + .value("PMSNEVFR_EL1", LIEF::assembly::aarch64::SYSREG::PMSNEVFR_EL1) + .value("PMSICR_EL1", LIEF::assembly::aarch64::SYSREG::PMSICR_EL1) + .value("PMSIRR_EL1", LIEF::assembly::aarch64::SYSREG::PMSIRR_EL1) + .value("PMSFCR_EL1", LIEF::assembly::aarch64::SYSREG::PMSFCR_EL1) + .value("PMSEVFR_EL1", LIEF::assembly::aarch64::SYSREG::PMSEVFR_EL1) + .value("PMSLATFR_EL1", LIEF::assembly::aarch64::SYSREG::PMSLATFR_EL1) + .value("PMSIDR_EL1", LIEF::assembly::aarch64::SYSREG::PMSIDR_EL1) + .value("PMBLIMITR_EL1", LIEF::assembly::aarch64::SYSREG::PMBLIMITR_EL1) + .value("PMBPTR_EL1", LIEF::assembly::aarch64::SYSREG::PMBPTR_EL1) + .value("PMBSR_EL1", LIEF::assembly::aarch64::SYSREG::PMBSR_EL1) + .value("PMSDSFR_EL1", LIEF::assembly::aarch64::SYSREG::PMSDSFR_EL1) + .value("PMBMAR_EL1", LIEF::assembly::aarch64::SYSREG::PMBMAR_EL1) + .value("PMBIDR_EL1", LIEF::assembly::aarch64::SYSREG::PMBIDR_EL1) + .value("TRBLIMITR_EL1", LIEF::assembly::aarch64::SYSREG::TRBLIMITR_EL1) + .value("TRBPTR_EL1", LIEF::assembly::aarch64::SYSREG::TRBPTR_EL1) + .value("TRBBASER_EL1", LIEF::assembly::aarch64::SYSREG::TRBBASER_EL1) + .value("TRBSR_EL1", LIEF::assembly::aarch64::SYSREG::TRBSR_EL1) + .value("TRBMAR_EL1", LIEF::assembly::aarch64::SYSREG::TRBMAR_EL1) + .value("TRBMPAM_EL1", LIEF::assembly::aarch64::SYSREG::TRBMPAM_EL1) + .value("TRBTRG_EL1", LIEF::assembly::aarch64::SYSREG::TRBTRG_EL1) + .value("TRBIDR_EL1", LIEF::assembly::aarch64::SYSREG::TRBIDR_EL1) + .value("PMSSCR_EL1", LIEF::assembly::aarch64::SYSREG::PMSSCR_EL1) + .value("PMINTENSET_EL1", LIEF::assembly::aarch64::SYSREG::PMINTENSET_EL1) + .value("PMINTENCLR_EL1", LIEF::assembly::aarch64::SYSREG::PMINTENCLR_EL1) + .value("PMUACR_EL1", LIEF::assembly::aarch64::SYSREG::PMUACR_EL1) + .value("PMECR_EL1", LIEF::assembly::aarch64::SYSREG::PMECR_EL1) + .value("PMMIR_EL1", LIEF::assembly::aarch64::SYSREG::PMMIR_EL1) + .value("PMIAR_EL1", LIEF::assembly::aarch64::SYSREG::PMIAR_EL1) + .value("MAIR_EL1", LIEF::assembly::aarch64::SYSREG::MAIR_EL1) + .value("MAIR2_EL1", LIEF::assembly::aarch64::SYSREG::MAIR2_EL1) + .value("PIRE0_EL1", LIEF::assembly::aarch64::SYSREG::PIRE0_EL1) + .value("PIR_EL1", LIEF::assembly::aarch64::SYSREG::PIR_EL1) + .value("POR_EL1", LIEF::assembly::aarch64::SYSREG::POR_EL1) + .value("S2POR_EL1", LIEF::assembly::aarch64::SYSREG::S2POR_EL1) + .value("TTTBRU_EL1", LIEF::assembly::aarch64::SYSREG::TTTBRU_EL1) + .value("TTTBRP_EL1", LIEF::assembly::aarch64::SYSREG::TTTBRP_EL1) + .value("AMAIR_EL1", LIEF::assembly::aarch64::SYSREG::AMAIR_EL1) + .value("AMAIR2_EL1", LIEF::assembly::aarch64::SYSREG::AMAIR2_EL1) + .value("LORSA_EL1", LIEF::assembly::aarch64::SYSREG::LORSA_EL1) + .value("LOREA_EL1", LIEF::assembly::aarch64::SYSREG::LOREA_EL1) + .value("LORN_EL1", LIEF::assembly::aarch64::SYSREG::LORN_EL1) + .value("LORC_EL1", LIEF::assembly::aarch64::SYSREG::LORC_EL1) + .value("MPAMIDR_EL1", LIEF::assembly::aarch64::SYSREG::MPAMIDR_EL1) + .value("MPAMBWIDR_EL1", LIEF::assembly::aarch64::SYSREG::MPAMBWIDR_EL1) + .value("TLBIDIDR_EL1", LIEF::assembly::aarch64::SYSREG::TLBIDIDR_EL1) + .value("LORID_EL1", LIEF::assembly::aarch64::SYSREG::LORID_EL1) + .value("MPAM1_EL1", LIEF::assembly::aarch64::SYSREG::MPAM1_EL1) + .value("MPAM0_EL1", LIEF::assembly::aarch64::SYSREG::MPAM0_EL1) + .value("MPAMCTL_EL1", LIEF::assembly::aarch64::SYSREG::MPAMCTL_EL1) + .value("MPAMSM_EL1", LIEF::assembly::aarch64::SYSREG::MPAMSM_EL1) + .value("MPAMBW1_EL1", LIEF::assembly::aarch64::SYSREG::MPAMBW1_EL1) + .value("MPAMBW0_EL1", LIEF::assembly::aarch64::SYSREG::MPAMBW0_EL1) + .value("MPAMBWSM_EL1", LIEF::assembly::aarch64::SYSREG::MPAMBWSM_EL1) + .value("VBAR_EL1", LIEF::assembly::aarch64::SYSREG::VBAR_EL1) + .value("RVBAR_EL1", LIEF::assembly::aarch64::SYSREG::RVBAR_EL1) + .value("RMR_EL1", LIEF::assembly::aarch64::SYSREG::RMR_EL1) + .value("ISR_EL1", LIEF::assembly::aarch64::SYSREG::ISR_EL1) + .value("DISR_EL1", LIEF::assembly::aarch64::SYSREG::DISR_EL1) + .value("ICC_IAR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IAR0_EL1) + .value("ICC_EOIR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_EOIR0_EL1) + .value("ICC_HPPIR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_HPPIR0_EL1) + .value("ICC_BPR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_BPR0_EL1) + .value("ICC_AP0R0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP0R0_EL1) + .value("ICC_AP0R1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP0R1_EL1) + .value("ICC_AP0R2_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP0R2_EL1) + .value("ICC_AP0R3_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP0R3_EL1) + .value("ICC_AP1R0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP1R0_EL1) + .value("ICC_AP1R1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP1R1_EL1) + .value("ICC_AP1R2_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP1R2_EL1) + .value("ICC_AP1R3_EL1", LIEF::assembly::aarch64::SYSREG::ICC_AP1R3_EL1) + .value("ICC_NMIAR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_NMIAR1_EL1) + .value("ICC_PPI_HMR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_HMR0_EL1) + .value("ICC_PPI_HMR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_HMR1_EL1) + .value("ICC_IDR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IDR0_EL1) + .value("ICC_HPPIR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_HPPIR_EL1) + .value("ICC_ICSR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_ICSR_EL1) + .value("ICC_IAFFIDR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IAFFIDR_EL1) + .value("ICC_PPI_ENABLER0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_ENABLER0_EL1) + .value("ICC_PPI_ENABLER1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_ENABLER1_EL1) + .value("ICC_DIR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_DIR_EL1) + .value("ICC_RPR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_RPR_EL1) + .value("ICC_SGI1R_EL1", LIEF::assembly::aarch64::SYSREG::ICC_SGI1R_EL1) + .value("ICC_ASGI1R_EL1", LIEF::assembly::aarch64::SYSREG::ICC_ASGI1R_EL1) + .value("ICC_SGI0R_EL1", LIEF::assembly::aarch64::SYSREG::ICC_SGI0R_EL1) + .value("ICC_IAR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IAR1_EL1) + .value("ICC_EOIR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_EOIR1_EL1) + .value("ICC_HPPIR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_HPPIR1_EL1) + .value("ICC_BPR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_BPR1_EL1) + .value("ICC_CTLR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_CTLR_EL1) + .value("ICC_SRE_EL1", LIEF::assembly::aarch64::SYSREG::ICC_SRE_EL1) + .value("ICC_IGRPEN0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IGRPEN0_EL1) + .value("ICC_IGRPEN1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_IGRPEN1_EL1) + .value("ICC_PPI_CACTIVER0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_CACTIVER0_EL1) + .value("ICC_PPI_CACTIVER1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_CACTIVER1_EL1) + .value("ICC_PPI_SACTIVER0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_SACTIVER0_EL1) + .value("ICC_PPI_SACTIVER1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_SACTIVER1_EL1) + .value("ICC_PPI_CPENDR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_CPENDR0_EL1) + .value("ICC_PPI_CPENDR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_CPENDR1_EL1) + .value("ICC_PPI_SPENDR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_SPENDR0_EL1) + .value("ICC_PPI_SPENDR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_SPENDR1_EL1) + .value("ICC_PPI_PRIORITYR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR0_EL1) + .value("ICC_PPI_PRIORITYR1_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR1_EL1) + .value("ICC_PPI_PRIORITYR2_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR2_EL1) + .value("ICC_PPI_PRIORITYR3_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR3_EL1) + .value("ICC_PPI_PRIORITYR4_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR4_EL1) + .value("ICC_PPI_PRIORITYR5_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR5_EL1) + .value("ICC_PPI_PRIORITYR6_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR6_EL1) + .value("ICC_PPI_PRIORITYR7_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR7_EL1) + .value("ICC_PPI_PRIORITYR8_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR8_EL1) + .value("ICC_PPI_PRIORITYR9_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR9_EL1) + .value("ICC_PPI_PRIORITYR10_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR10_EL1) + .value("ICC_PPI_PRIORITYR11_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR11_EL1) + .value("ICC_PPI_PRIORITYR12_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR12_EL1) + .value("ICC_PPI_PRIORITYR13_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR13_EL1) + .value("ICC_PPI_PRIORITYR14_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR14_EL1) + .value("ICC_PPI_PRIORITYR15_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PPI_PRIORITYR15_EL1) + .value("TPIDR3_EL1", LIEF::assembly::aarch64::SYSREG::TPIDR3_EL1) + .value("CONTEXTIDR_EL1", LIEF::assembly::aarch64::SYSREG::CONTEXTIDR_EL1) + .value("RCWSMASK_EL1", LIEF::assembly::aarch64::SYSREG::RCWSMASK_EL1) + .value("TPIDR_EL1", LIEF::assembly::aarch64::SYSREG::TPIDR_EL1) + .value("ACCDATA_EL1", LIEF::assembly::aarch64::SYSREG::ACCDATA_EL1) + .value("RCWMASK_EL1", LIEF::assembly::aarch64::SYSREG::RCWMASK_EL1) + .value("SCXTNUM_EL1", LIEF::assembly::aarch64::SYSREG::SCXTNUM_EL1) + .value("CNTKCTL_EL1", LIEF::assembly::aarch64::SYSREG::CNTKCTL_EL1) + .value("CCSIDR_EL1", LIEF::assembly::aarch64::SYSREG::CCSIDR_EL1) + .value("CLIDR_EL1", LIEF::assembly::aarch64::SYSREG::CLIDR_EL1) + .value("CCSIDR2_EL1", LIEF::assembly::aarch64::SYSREG::CCSIDR2_EL1) + .value("GMID_EL1", LIEF::assembly::aarch64::SYSREG::GMID_EL1) + .value("SMIDR_EL1", LIEF::assembly::aarch64::SYSREG::SMIDR_EL1) + .value("AIDR_EL1", LIEF::assembly::aarch64::SYSREG::AIDR_EL1) + .value("ICC_APR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_APR_EL1) + .value("ICC_CR0_EL1", LIEF::assembly::aarch64::SYSREG::ICC_CR0_EL1) + .value("ICC_PCR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_PCR_EL1) + .value("ICC_HAPR_EL1", LIEF::assembly::aarch64::SYSREG::ICC_HAPR_EL1) + .value("CSSELR_EL1", LIEF::assembly::aarch64::SYSREG::CSSELR_EL1) + .value("CTR_EL0", LIEF::assembly::aarch64::SYSREG::CTR_EL0) + .value("DCZID_EL0", LIEF::assembly::aarch64::SYSREG::DCZID_EL0) + .value("TPMIN0_EL0", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL0) + .value("TPMAX0_EL0", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL0) + .value("TPMIN1_EL0", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL0) + .value("TPMAX1_EL0", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL0) + .value("RNDR", LIEF::assembly::aarch64::SYSREG::RNDR) + .value("RNDRRS", LIEF::assembly::aarch64::SYSREG::RNDRRS) + .value("GCSPR_EL0", LIEF::assembly::aarch64::SYSREG::GCSPR_EL0) + .value("TINDEX_EL0", LIEF::assembly::aarch64::SYSREG::TINDEX_EL0) + .value("NZCV", LIEF::assembly::aarch64::SYSREG::NZCV) + .value("DAIF", LIEF::assembly::aarch64::SYSREG::DAIF) + .value("SVCR", LIEF::assembly::aarch64::SYSREG::SVCR) + .value("DIT", LIEF::assembly::aarch64::SYSREG::DIT); + reg.value("SSBS", LIEF::assembly::aarch64::SYSREG::SSBS) + .value("TCO", LIEF::assembly::aarch64::SYSREG::TCO) + .value("FPCR", LIEF::assembly::aarch64::SYSREG::FPCR) + .value("FPSR", LIEF::assembly::aarch64::SYSREG::FPSR) + .value("FPMR", LIEF::assembly::aarch64::SYSREG::FPMR) + .value("DSPSR_EL0", LIEF::assembly::aarch64::SYSREG::DSPSR_EL0) + .value("DLR_EL0", LIEF::assembly::aarch64::SYSREG::DLR_EL0) + .value("DPOCR_EL0", LIEF::assembly::aarch64::SYSREG::DPOCR_EL0) + .value("PMICNTR_EL0", LIEF::assembly::aarch64::SYSREG::PMICNTR_EL0) + .value("PMICFILTR_EL0", LIEF::assembly::aarch64::SYSREG::PMICFILTR_EL0) + .value("PMCR_EL0", LIEF::assembly::aarch64::SYSREG::PMCR_EL0) + .value("PMCNTENSET_EL0", LIEF::assembly::aarch64::SYSREG::PMCNTENSET_EL0) + .value("PMCNTENCLR_EL0", LIEF::assembly::aarch64::SYSREG::PMCNTENCLR_EL0) + .value("PMOVSCLR_EL0", LIEF::assembly::aarch64::SYSREG::PMOVSCLR_EL0) + .value("PMSWINC_EL0", LIEF::assembly::aarch64::SYSREG::PMSWINC_EL0) + .value("PMSELR_EL0", LIEF::assembly::aarch64::SYSREG::PMSELR_EL0) + .value("PMCEID0_EL0", LIEF::assembly::aarch64::SYSREG::PMCEID0_EL0) + .value("PMCEID1_EL0", LIEF::assembly::aarch64::SYSREG::PMCEID1_EL0) + .value("PMCCNTR_EL0", LIEF::assembly::aarch64::SYSREG::PMCCNTR_EL0) + .value("PMXEVTYPER_EL0", LIEF::assembly::aarch64::SYSREG::PMXEVTYPER_EL0) + .value("PMXEVCNTR_EL0", LIEF::assembly::aarch64::SYSREG::PMXEVCNTR_EL0) + .value("PMZR_EL0", LIEF::assembly::aarch64::SYSREG::PMZR_EL0) + .value("PMUSERENR_EL0", LIEF::assembly::aarch64::SYSREG::PMUSERENR_EL0) + .value("PMOVSSET_EL0", LIEF::assembly::aarch64::SYSREG::PMOVSSET_EL0) + .value("POR_EL0", LIEF::assembly::aarch64::SYSREG::POR_EL0) + .value("TPIDR3_EL0", LIEF::assembly::aarch64::SYSREG::TPIDR3_EL0) + .value("TPIDR_EL0", LIEF::assembly::aarch64::SYSREG::TPIDR_EL0) + .value("TPIDRRO_EL0", LIEF::assembly::aarch64::SYSREG::TPIDRRO_EL0) + .value("TPIDR2_EL0", LIEF::assembly::aarch64::SYSREG::TPIDR2_EL0) + .value("SCXTNUM_EL0", LIEF::assembly::aarch64::SYSREG::SCXTNUM_EL0) + .value("AMCR_EL0", LIEF::assembly::aarch64::SYSREG::AMCR_EL0) + .value("AMCFGR_EL0", LIEF::assembly::aarch64::SYSREG::AMCFGR_EL0) + .value("AMCGCR_EL0", LIEF::assembly::aarch64::SYSREG::AMCGCR_EL0) + .value("AMUSERENR_EL0", LIEF::assembly::aarch64::SYSREG::AMUSERENR_EL0) + .value("AMCNTENCLR0_EL0", LIEF::assembly::aarch64::SYSREG::AMCNTENCLR0_EL0) + .value("AMCNTENSET0_EL0", LIEF::assembly::aarch64::SYSREG::AMCNTENSET0_EL0) + .value("AMCG1IDR_EL0", LIEF::assembly::aarch64::SYSREG::AMCG1IDR_EL0) + .value("AMCNTENCLR1_EL0", LIEF::assembly::aarch64::SYSREG::AMCNTENCLR1_EL0) + .value("AMCNTENSET1_EL0", LIEF::assembly::aarch64::SYSREG::AMCNTENSET1_EL0) + .value("AMEVCNTR00_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR00_EL0) + .value("AMEVCNTR01_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR01_EL0) + .value("AMEVCNTR02_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR02_EL0) + .value("AMEVCNTR03_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR03_EL0) + .value("AMEVTYPER00_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER00_EL0) + .value("AMEVTYPER01_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER01_EL0) + .value("AMEVTYPER02_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER02_EL0) + .value("AMEVTYPER03_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER03_EL0) + .value("AMEVCNTR10_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR10_EL0) + .value("AMEVCNTR11_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR11_EL0) + .value("AMEVCNTR12_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR12_EL0) + .value("AMEVCNTR13_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR13_EL0) + .value("AMEVCNTR14_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR14_EL0) + .value("AMEVCNTR15_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR15_EL0) + .value("AMEVCNTR16_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR16_EL0) + .value("AMEVCNTR17_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR17_EL0) + .value("AMEVCNTR18_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR18_EL0) + .value("AMEVCNTR19_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR19_EL0) + .value("AMEVCNTR110_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR110_EL0) + .value("AMEVCNTR111_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR111_EL0) + .value("AMEVCNTR112_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR112_EL0) + .value("AMEVCNTR113_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR113_EL0) + .value("AMEVCNTR114_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR114_EL0) + .value("AMEVCNTR115_EL0", LIEF::assembly::aarch64::SYSREG::AMEVCNTR115_EL0) + .value("AMEVTYPER10_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER10_EL0) + .value("AMEVTYPER11_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER11_EL0) + .value("AMEVTYPER12_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER12_EL0) + .value("AMEVTYPER13_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER13_EL0) + .value("AMEVTYPER14_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER14_EL0) + .value("AMEVTYPER15_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER15_EL0) + .value("AMEVTYPER16_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER16_EL0) + .value("AMEVTYPER17_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER17_EL0) + .value("AMEVTYPER18_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER18_EL0) + .value("AMEVTYPER19_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER19_EL0) + .value("AMEVTYPER110_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER110_EL0) + .value("AMEVTYPER111_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER111_EL0) + .value("AMEVTYPER112_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER112_EL0) + .value("AMEVTYPER113_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER113_EL0) + .value("AMEVTYPER114_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER114_EL0) + .value("AMEVTYPER115_EL0", LIEF::assembly::aarch64::SYSREG::AMEVTYPER115_EL0) + .value("CNTFRQ_EL0", LIEF::assembly::aarch64::SYSREG::CNTFRQ_EL0) + .value("CNTPCT_EL0", LIEF::assembly::aarch64::SYSREG::CNTPCT_EL0) + .value("CNTVCT_EL0", LIEF::assembly::aarch64::SYSREG::CNTVCT_EL0) + .value("CNTPCTSS_EL0", LIEF::assembly::aarch64::SYSREG::CNTPCTSS_EL0) + .value("CNTVCTSS_EL0", LIEF::assembly::aarch64::SYSREG::CNTVCTSS_EL0) + .value("CNTP_TVAL_EL0", LIEF::assembly::aarch64::SYSREG::CNTP_TVAL_EL0) + .value("CNTP_CTL_EL0", LIEF::assembly::aarch64::SYSREG::CNTP_CTL_EL0) + .value("CNTP_CVAL_EL0", LIEF::assembly::aarch64::SYSREG::CNTP_CVAL_EL0) + .value("CNTV_TVAL_EL0", LIEF::assembly::aarch64::SYSREG::CNTV_TVAL_EL0) + .value("CNTV_CTL_EL0", LIEF::assembly::aarch64::SYSREG::CNTV_CTL_EL0) + .value("CNTV_CVAL_EL0", LIEF::assembly::aarch64::SYSREG::CNTV_CVAL_EL0) + .value("PMEVCNTR0_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR0_EL0) + .value("PMEVCNTR1_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR1_EL0) + .value("PMEVCNTR2_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR2_EL0) + .value("PMEVCNTR3_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR3_EL0) + .value("PMEVCNTR4_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR4_EL0) + .value("PMEVCNTR5_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR5_EL0) + .value("PMEVCNTR6_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR6_EL0) + .value("PMEVCNTR7_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR7_EL0) + .value("PMEVCNTR8_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR8_EL0) + .value("PMEVCNTR9_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR9_EL0) + .value("PMEVCNTR10_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR10_EL0) + .value("PMEVCNTR11_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR11_EL0) + .value("PMEVCNTR12_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR12_EL0) + .value("PMEVCNTR13_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR13_EL0) + .value("PMEVCNTR14_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR14_EL0) + .value("PMEVCNTR15_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR15_EL0) + .value("PMEVCNTR16_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR16_EL0) + .value("PMEVCNTR17_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR17_EL0) + .value("PMEVCNTR18_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR18_EL0) + .value("PMEVCNTR19_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR19_EL0) + .value("PMEVCNTR20_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR20_EL0) + .value("PMEVCNTR21_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR21_EL0) + .value("PMEVCNTR22_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR22_EL0) + .value("PMEVCNTR23_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR23_EL0) + .value("PMEVCNTR24_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR24_EL0) + .value("PMEVCNTR25_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR25_EL0) + .value("PMEVCNTR26_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR26_EL0) + .value("PMEVCNTR27_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR27_EL0) + .value("PMEVCNTR28_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR28_EL0) + .value("PMEVCNTR29_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR29_EL0) + .value("PMEVCNTR30_EL0", LIEF::assembly::aarch64::SYSREG::PMEVCNTR30_EL0) + .value("PMEVTYPER0_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER0_EL0) + .value("PMEVTYPER1_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER1_EL0) + .value("PMEVTYPER2_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER2_EL0) + .value("PMEVTYPER3_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER3_EL0) + .value("PMEVTYPER4_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER4_EL0) + .value("PMEVTYPER5_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER5_EL0) + .value("PMEVTYPER6_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER6_EL0) + .value("PMEVTYPER7_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER7_EL0) + .value("PMEVTYPER8_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER8_EL0) + .value("PMEVTYPER9_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER9_EL0) + .value("PMEVTYPER10_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER10_EL0) + .value("PMEVTYPER11_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER11_EL0) + .value("PMEVTYPER12_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER12_EL0) + .value("PMEVTYPER13_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER13_EL0) + .value("PMEVTYPER14_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER14_EL0) + .value("PMEVTYPER15_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER15_EL0) + .value("PMEVTYPER16_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER16_EL0) + .value("PMEVTYPER17_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER17_EL0) + .value("PMEVTYPER18_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER18_EL0) + .value("PMEVTYPER19_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER19_EL0) + .value("PMEVTYPER20_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER20_EL0) + .value("PMEVTYPER21_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER21_EL0) + .value("PMEVTYPER22_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER22_EL0) + .value("PMEVTYPER23_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER23_EL0) + .value("PMEVTYPER24_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER24_EL0) + .value("PMEVTYPER25_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER25_EL0) + .value("PMEVTYPER26_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER26_EL0) + .value("PMEVTYPER27_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER27_EL0) + .value("PMEVTYPER28_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER28_EL0) + .value("PMEVTYPER29_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER29_EL0) + .value("PMEVTYPER30_EL0", LIEF::assembly::aarch64::SYSREG::PMEVTYPER30_EL0) + .value("PMCCFILTR_EL0", LIEF::assembly::aarch64::SYSREG::PMCCFILTR_EL0) + .value("VPIDR_EL2", LIEF::assembly::aarch64::SYSREG::VPIDR_EL2) + .value("MPUIR_EL2", LIEF::assembly::aarch64::SYSREG::MPUIR_EL2) + .value("VMPIDR_EL2", LIEF::assembly::aarch64::SYSREG::VMPIDR_EL2) + .value("SCTLR_EL2", LIEF::assembly::aarch64::SYSREG::SCTLR_EL2) + .value("ACTLR_EL2", LIEF::assembly::aarch64::SYSREG::ACTLR_EL2) + .value("SCTLR2_EL2", LIEF::assembly::aarch64::SYSREG::SCTLR2_EL2) + .value("HCR_EL2", LIEF::assembly::aarch64::SYSREG::HCR_EL2) + .value("MDCR_EL2", LIEF::assembly::aarch64::SYSREG::MDCR_EL2) + .value("CPTR_EL2", LIEF::assembly::aarch64::SYSREG::CPTR_EL2) + .value("HSTR_EL2", LIEF::assembly::aarch64::SYSREG::HSTR_EL2) + .value("HFGRTR_EL2", LIEF::assembly::aarch64::SYSREG::HFGRTR_EL2) + .value("HFGWTR_EL2", LIEF::assembly::aarch64::SYSREG::HFGWTR_EL2) + .value("HFGITR_EL2", LIEF::assembly::aarch64::SYSREG::HFGITR_EL2) + .value("HACR_EL2", LIEF::assembly::aarch64::SYSREG::HACR_EL2) + .value("ZCR_EL2", LIEF::assembly::aarch64::SYSREG::ZCR_EL2) + .value("TRFCR_EL2", LIEF::assembly::aarch64::SYSREG::TRFCR_EL2) + .value("HCRX_EL2", LIEF::assembly::aarch64::SYSREG::HCRX_EL2) + .value("TRCITECR_EL2", LIEF::assembly::aarch64::SYSREG::TRCITECR_EL2) + .value("SMPRIMAP_EL2", LIEF::assembly::aarch64::SYSREG::SMPRIMAP_EL2) + .value("SMCR_EL2", LIEF::assembly::aarch64::SYSREG::SMCR_EL2) + .value("SDER32_EL2", LIEF::assembly::aarch64::SYSREG::SDER32_EL2) + .value("SCTLRMASK_EL2", LIEF::assembly::aarch64::SYSREG::SCTLRMASK_EL2) + .value("ACTLRMASK_EL2", LIEF::assembly::aarch64::SYSREG::ACTLRMASK_EL2) + .value("CPTRMASK_EL2", LIEF::assembly::aarch64::SYSREG::CPTRMASK_EL2) + .value("SCTLR2MASK_EL2", LIEF::assembly::aarch64::SYSREG::SCTLR2MASK_EL2) + .value("NVHCR_EL2", LIEF::assembly::aarch64::SYSREG::NVHCR_EL2) + .value("NVHCRX_EL2", LIEF::assembly::aarch64::SYSREG::NVHCRX_EL2) + .value("NVHCRMASK_EL2", LIEF::assembly::aarch64::SYSREG::NVHCRMASK_EL2) + .value("NVHCRXMASK_EL2", LIEF::assembly::aarch64::SYSREG::NVHCRXMASK_EL2) + .value("HCRMASK_EL2", LIEF::assembly::aarch64::SYSREG::HCRMASK_EL2) + .value("HCRXMASK_EL2", LIEF::assembly::aarch64::SYSREG::HCRXMASK_EL2) + .value("TTBR0_EL2", LIEF::assembly::aarch64::SYSREG::TTBR0_EL2) + .value("TTBR1_EL2", LIEF::assembly::aarch64::SYSREG::TTBR1_EL2) + .value("TCR_EL2", LIEF::assembly::aarch64::SYSREG::TCR_EL2) + .value("TCR2_EL2", LIEF::assembly::aarch64::SYSREG::TCR2_EL2) + .value("IRTBRU_EL2", LIEF::assembly::aarch64::SYSREG::IRTBRU_EL2) + .value("IRTBRP_EL2", LIEF::assembly::aarch64::SYSREG::IRTBRP_EL2) + .value("DPOTBR0_EL2", LIEF::assembly::aarch64::SYSREG::DPOTBR0_EL2) + .value("DPOTBR1_EL2", LIEF::assembly::aarch64::SYSREG::DPOTBR1_EL2) + .value("VTTBR_EL2", LIEF::assembly::aarch64::SYSREG::VTTBR_EL2) + .value("VTCR_EL2", LIEF::assembly::aarch64::SYSREG::VTCR_EL2) + .value("LDSTT_EL2", LIEF::assembly::aarch64::SYSREG::LDSTT_EL2) + .value("VNCR_EL2", LIEF::assembly::aarch64::SYSREG::VNCR_EL2) + .value("VNCCR_EL2", LIEF::assembly::aarch64::SYSREG::VNCCR_EL2) + .value("TPMIN0_EL2", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL2) + .value("TPMAX0_EL2", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL2) + .value("TPMIN1_EL2", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL2) + .value("TPMAX1_EL2", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL2) + .value("HDBSSBR_EL2", LIEF::assembly::aarch64::SYSREG::HDBSSBR_EL2) + .value("HDBSSPROD_EL2", LIEF::assembly::aarch64::SYSREG::HDBSSPROD_EL2) + .value("HACDBSBR_EL2", LIEF::assembly::aarch64::SYSREG::HACDBSBR_EL2) + .value("HACDBSCONS_EL2", LIEF::assembly::aarch64::SYSREG::HACDBSCONS_EL2) + .value("GCSCR_EL2", LIEF::assembly::aarch64::SYSREG::GCSCR_EL2) + .value("GCSPR_EL2", LIEF::assembly::aarch64::SYSREG::GCSPR_EL2) + .value("VSTTBR_EL2", LIEF::assembly::aarch64::SYSREG::VSTTBR_EL2) + .value("VSTCR_EL2", LIEF::assembly::aarch64::SYSREG::VSTCR_EL2) + .value("TCRMASK_EL2", LIEF::assembly::aarch64::SYSREG::TCRMASK_EL2) + .value("TCR2MASK_EL2", LIEF::assembly::aarch64::SYSREG::TCR2MASK_EL2) + .value("VTLBID0_EL2", LIEF::assembly::aarch64::SYSREG::VTLBID0_EL2) + .value("VTLBID1_EL2", LIEF::assembly::aarch64::SYSREG::VTLBID1_EL2) + .value("VTLBID2_EL2", LIEF::assembly::aarch64::SYSREG::VTLBID2_EL2) + .value("VTLBID3_EL2", LIEF::assembly::aarch64::SYSREG::VTLBID3_EL2) + .value("VTLBIDOS0_EL2", LIEF::assembly::aarch64::SYSREG::VTLBIDOS0_EL2) + .value("VTLBIDOS1_EL2", LIEF::assembly::aarch64::SYSREG::VTLBIDOS1_EL2) + .value("VTLBIDOS2_EL2", LIEF::assembly::aarch64::SYSREG::VTLBIDOS2_EL2) + .value("VTLBIDOS3_EL2", LIEF::assembly::aarch64::SYSREG::VTLBIDOS3_EL2) + .value("DACR32_EL2", LIEF::assembly::aarch64::SYSREG::DACR32_EL2) + .value("HDFGRTR2_EL2", LIEF::assembly::aarch64::SYSREG::HDFGRTR2_EL2) + .value("HDFGWTR2_EL2", LIEF::assembly::aarch64::SYSREG::HDFGWTR2_EL2) + .value("HFGRTR2_EL2", LIEF::assembly::aarch64::SYSREG::HFGRTR2_EL2) + .value("HFGWTR2_EL2", LIEF::assembly::aarch64::SYSREG::HFGWTR2_EL2) + .value("HDFGRTR_EL2", LIEF::assembly::aarch64::SYSREG::HDFGRTR_EL2) + .value("HDFGWTR_EL2", LIEF::assembly::aarch64::SYSREG::HDFGWTR_EL2) + .value("HAFGRTR_EL2", LIEF::assembly::aarch64::SYSREG::HAFGRTR_EL2) + .value("HFGITR2_EL2", LIEF::assembly::aarch64::SYSREG::HFGITR2_EL2) + .value("FGDTP0_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP0_EL2) + .value("FGDTP1_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP1_EL2) + .value("FGDTP2_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP2_EL2) + .value("FGDTP3_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP3_EL2) + .value("FGDTP4_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP4_EL2) + .value("FGDTP5_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP5_EL2) + .value("FGDTP6_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP6_EL2) + .value("FGDTP7_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP7_EL2) + .value("FGDTP8_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP8_EL2) + .value("FGDTP9_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP9_EL2) + .value("FGDTP10_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP10_EL2) + .value("FGDTP11_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP11_EL2) + .value("FGDTP12_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP12_EL2) + .value("FGDTP13_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP13_EL2) + .value("FGDTP14_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP14_EL2) + .value("FGDTP15_EL2", LIEF::assembly::aarch64::SYSREG::FGDTP15_EL2) + .value("FGDTU0_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU0_EL2) + .value("FGDTU1_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU1_EL2) + .value("FGDTU2_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU2_EL2) + .value("FGDTU3_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU3_EL2) + .value("FGDTU4_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU4_EL2) + .value("FGDTU5_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU5_EL2) + .value("FGDTU6_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU6_EL2) + .value("FGDTU7_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU7_EL2) + .value("FGDTU8_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU8_EL2) + .value("FGDTU9_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU9_EL2) + .value("FGDTU10_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU10_EL2) + .value("FGDTU11_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU11_EL2) + .value("FGDTU12_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU12_EL2) + .value("FGDTU13_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU13_EL2) + .value("FGDTU14_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU14_EL2) + .value("FGDTU15_EL2", LIEF::assembly::aarch64::SYSREG::FGDTU15_EL2) + .value("AFGDTP0_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP0_EL2) + .value("AFGDTP1_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP1_EL2) + .value("AFGDTP2_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP2_EL2) + .value("AFGDTP3_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP3_EL2) + .value("AFGDTP4_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP4_EL2) + .value("AFGDTP5_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP5_EL2) + .value("AFGDTP6_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP6_EL2) + .value("AFGDTP7_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP7_EL2) + .value("AFGDTP8_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP8_EL2) + .value("AFGDTP9_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP9_EL2) + .value("AFGDTP10_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP10_EL2) + .value("AFGDTP11_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP11_EL2) + .value("AFGDTP12_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP12_EL2) + .value("AFGDTP13_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP13_EL2) + .value("AFGDTP14_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP14_EL2) + .value("AFGDTP15_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTP15_EL2) + .value("AFGDTU0_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU0_EL2) + .value("AFGDTU1_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU1_EL2) + .value("AFGDTU2_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU2_EL2) + .value("AFGDTU3_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU3_EL2) + .value("AFGDTU4_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU4_EL2) + .value("AFGDTU5_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU5_EL2) + .value("AFGDTU6_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU6_EL2) + .value("AFGDTU7_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU7_EL2) + .value("AFGDTU8_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU8_EL2) + .value("AFGDTU9_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU9_EL2) + .value("AFGDTU10_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU10_EL2) + .value("AFGDTU11_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU11_EL2) + .value("AFGDTU12_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU12_EL2) + .value("AFGDTU13_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU13_EL2) + .value("AFGDTU14_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU14_EL2) + .value("AFGDTU15_EL2", LIEF::assembly::aarch64::SYSREG::AFGDTU15_EL2) + .value("SPSR_EL2", LIEF::assembly::aarch64::SYSREG::SPSR_EL2) + .value("ELR_EL2", LIEF::assembly::aarch64::SYSREG::ELR_EL2) + .value("STINDEX_EL2", LIEF::assembly::aarch64::SYSREG::STINDEX_EL2) + .value("TINDEX_EL2", LIEF::assembly::aarch64::SYSREG::TINDEX_EL2) + .value("SP_EL1", LIEF::assembly::aarch64::SYSREG::SP_EL1) + .value("SPSR_irq", LIEF::assembly::aarch64::SYSREG::SPSR_irq) + .value("SPSR_abt", LIEF::assembly::aarch64::SYSREG::SPSR_abt) + .value("SPSR_und", LIEF::assembly::aarch64::SYSREG::SPSR_und); + reg.value("SPSR_fiq", LIEF::assembly::aarch64::SYSREG::SPSR_fiq) + .value("IFSR32_EL2", LIEF::assembly::aarch64::SYSREG::IFSR32_EL2) + .value("AFSR0_EL2", LIEF::assembly::aarch64::SYSREG::AFSR0_EL2) + .value("AFSR1_EL2", LIEF::assembly::aarch64::SYSREG::AFSR1_EL2) + .value("ESR_EL2", LIEF::assembly::aarch64::SYSREG::ESR_EL2) + .value("VSESR_EL2", LIEF::assembly::aarch64::SYSREG::VSESR_EL2) + .value("FPEXC32_EL2", LIEF::assembly::aarch64::SYSREG::FPEXC32_EL2) + .value("TFSR_EL2", LIEF::assembly::aarch64::SYSREG::TFSR_EL2) + .value("FAR_EL2", LIEF::assembly::aarch64::SYSREG::FAR_EL2) + .value("HPFAR_EL2", LIEF::assembly::aarch64::SYSREG::HPFAR_EL2) + .value("PFAR_EL2", LIEF::assembly::aarch64::SYSREG::PFAR_EL2) + .value("PRENR_EL2", LIEF::assembly::aarch64::SYSREG::PRENR_EL2) + .value("PRSELR_EL2", LIEF::assembly::aarch64::SYSREG::PRSELR_EL2) + .value("PRBAR_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR_EL2) + .value("PRLAR_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR_EL2) + .value("PRBAR1_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR1_EL2) + .value("PRLAR1_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR1_EL2) + .value("PRBAR2_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR2_EL2) + .value("PRLAR2_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR2_EL2) + .value("PRBAR3_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR3_EL2) + .value("PRLAR3_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR3_EL2) + .value("PRBAR4_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR4_EL2) + .value("PRLAR4_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR4_EL2) + .value("PRBAR5_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR5_EL2) + .value("PRLAR5_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR5_EL2) + .value("PRBAR6_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR6_EL2) + .value("PRLAR6_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR6_EL2) + .value("PRBAR7_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR7_EL2) + .value("PRLAR7_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR7_EL2) + .value("PRBAR8_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR8_EL2) + .value("PRLAR8_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR8_EL2) + .value("PRBAR9_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR9_EL2) + .value("PRLAR9_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR9_EL2) + .value("PRBAR10_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR10_EL2) + .value("PRLAR10_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR10_EL2) + .value("PRBAR11_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR11_EL2) + .value("PRLAR11_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR11_EL2) + .value("PRBAR12_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR12_EL2) + .value("PRLAR12_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR12_EL2) + .value("PRBAR13_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR13_EL2) + .value("PRLAR13_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR13_EL2) + .value("PRBAR14_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR14_EL2) + .value("PRLAR14_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR14_EL2) + .value("PRBAR15_EL2", LIEF::assembly::aarch64::SYSREG::PRBAR15_EL2) + .value("PRLAR15_EL2", LIEF::assembly::aarch64::SYSREG::PRLAR15_EL2) + .value("PMSCR_EL2", LIEF::assembly::aarch64::SYSREG::PMSCR_EL2) + .value("PMBSR_EL2", LIEF::assembly::aarch64::SYSREG::PMBSR_EL2) + .value("TRBSR_EL2", LIEF::assembly::aarch64::SYSREG::TRBSR_EL2) + .value("MAIR2_EL2", LIEF::assembly::aarch64::SYSREG::MAIR2_EL2) + .value("MAIR_EL2", LIEF::assembly::aarch64::SYSREG::MAIR_EL2) + .value("PIRE0_EL2", LIEF::assembly::aarch64::SYSREG::PIRE0_EL2) + .value("PIR_EL2", LIEF::assembly::aarch64::SYSREG::PIR_EL2) + .value("POR_EL2", LIEF::assembly::aarch64::SYSREG::POR_EL2) + .value("S2PIR_EL2", LIEF::assembly::aarch64::SYSREG::S2PIR_EL2) + .value("TTTBRU_EL2", LIEF::assembly::aarch64::SYSREG::TTTBRU_EL2) + .value("TTTBRP_EL2", LIEF::assembly::aarch64::SYSREG::TTTBRP_EL2) + .value("AMAIR_EL2", LIEF::assembly::aarch64::SYSREG::AMAIR_EL2) + .value("AMAIR2_EL2", LIEF::assembly::aarch64::SYSREG::AMAIR2_EL2) + .value("MPAMHCR_EL2", LIEF::assembly::aarch64::SYSREG::MPAMHCR_EL2) + .value("MPAMVPMV_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPMV_EL2) + .value("MPAM2_EL2", LIEF::assembly::aarch64::SYSREG::MPAM2_EL2) + .value("MPAMCTL_EL2", LIEF::assembly::aarch64::SYSREG::MPAMCTL_EL2) + .value("MPAMBW2_EL2", LIEF::assembly::aarch64::SYSREG::MPAMBW2_EL2) + .value("MPAMBWCAP_EL2", LIEF::assembly::aarch64::SYSREG::MPAMBWCAP_EL2) + .value("MPAMVPM0_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM0_EL2) + .value("MPAMVPM1_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM1_EL2) + .value("MPAMVPM2_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM2_EL2) + .value("MPAMVPM3_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM3_EL2) + .value("MPAMVPM4_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM4_EL2) + .value("MPAMVPM5_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM5_EL2) + .value("MPAMVPM6_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM6_EL2) + .value("MPAMVPM7_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM7_EL2) + .value("MPAMVIDCR_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVIDCR_EL2) + .value("MPAMVIDSR_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVIDSR_EL2) + .value("MECID_P0_EL2", LIEF::assembly::aarch64::SYSREG::MECID_P0_EL2) + .value("MECID_A0_EL2", LIEF::assembly::aarch64::SYSREG::MECID_A0_EL2) + .value("MECID_P1_EL2", LIEF::assembly::aarch64::SYSREG::MECID_P1_EL2) + .value("MECID_A1_EL2", LIEF::assembly::aarch64::SYSREG::MECID_A1_EL2) + .value("MECIDR_EL2", LIEF::assembly::aarch64::SYSREG::MECIDR_EL2) + .value("VMECID_P_EL2", LIEF::assembly::aarch64::SYSREG::VMECID_P_EL2) + .value("VMECID_A_EL2", LIEF::assembly::aarch64::SYSREG::VMECID_A_EL2) + .value("VBAR_EL2", LIEF::assembly::aarch64::SYSREG::VBAR_EL2) + .value("RVBAR_EL2", LIEF::assembly::aarch64::SYSREG::RVBAR_EL2) + .value("RMR_EL2", LIEF::assembly::aarch64::SYSREG::RMR_EL2) + .value("VDISR_EL2", LIEF::assembly::aarch64::SYSREG::VDISR_EL2) + .value("ICH_AP0R0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R0_EL2) + .value("ICH_AP0R1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R1_EL2) + .value("ICH_AP0R2_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R2_EL2) + .value("ICH_AP0R3_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R3_EL2) + .value("ICH_APR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_APR_EL2) + .value("ICH_HPPIR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_HPPIR_EL2) + .value("ICH_AP1R0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP1R0_EL2) + .value("ICH_AP1R1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP1R1_EL2) + .value("ICH_AP1R2_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP1R2_EL2) + .value("ICH_AP1R3_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP1R3_EL2) + .value("ICH_HFGRTR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_HFGRTR_EL2) + .value("ICC_SRE_EL2", LIEF::assembly::aarch64::SYSREG::ICC_SRE_EL2) + .value("ICH_HFGWTR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_HFGWTR_EL2) + .value("ICH_HFGITR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_HFGITR_EL2) + .value("ICH_PPI_DVIR0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_DVIR0_EL2) + .value("ICH_PPI_DVIR1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_DVIR1_EL2) + .value("ICH_PPI_ENABLER0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_ENABLER0_EL2) + .value("ICH_PPI_ENABLER1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_ENABLER1_EL2) + .value("ICH_PPI_PENDR0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PENDR0_EL2) + .value("ICH_PPI_PENDR1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PENDR1_EL2) + .value("ICH_PPI_ACTIVER0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_ACTIVER0_EL2) + .value("ICH_PPI_ACTIVER1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_ACTIVER1_EL2) + .value("ICH_HCR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_HCR_EL2) + .value("ICH_VTR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_VTR_EL2) + .value("ICH_MISR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_MISR_EL2) + .value("ICH_EISR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_EISR_EL2) + .value("ICH_VCTLR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_VCTLR_EL2) + .value("ICH_ELRSR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_ELRSR_EL2) + .value("ICH_CONTEXTR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_CONTEXTR_EL2) + .value("ICH_VMCR_EL2", LIEF::assembly::aarch64::SYSREG::ICH_VMCR_EL2) + .value("ICH_LR0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR0_EL2) + .value("ICH_LR1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR1_EL2) + .value("ICH_LR2_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR2_EL2) + .value("ICH_LR3_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR3_EL2) + .value("ICH_LR4_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR4_EL2) + .value("ICH_LR5_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR5_EL2) + .value("ICH_LR6_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR6_EL2) + .value("ICH_LR7_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR7_EL2) + .value("ICH_LR8_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR8_EL2) + .value("ICH_LR9_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR9_EL2) + .value("ICH_LR10_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR10_EL2) + .value("ICH_LR11_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR11_EL2) + .value("ICH_LR12_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR12_EL2) + .value("ICH_LR13_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR13_EL2) + .value("ICH_LR14_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR14_EL2) + .value("ICH_LR15_EL2", LIEF::assembly::aarch64::SYSREG::ICH_LR15_EL2) + .value("ICH_PPI_PRIORITYR0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR0_EL2) + .value("ICH_PPI_PRIORITYR1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR1_EL2) + .value("ICH_PPI_PRIORITYR2_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR2_EL2) + .value("ICH_PPI_PRIORITYR3_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR3_EL2) + .value("ICH_PPI_PRIORITYR4_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR4_EL2) + .value("ICH_PPI_PRIORITYR5_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR5_EL2) + .value("ICH_PPI_PRIORITYR6_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR6_EL2) + .value("ICH_PPI_PRIORITYR7_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR7_EL2) + .value("ICH_PPI_PRIORITYR8_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR8_EL2) + .value("ICH_PPI_PRIORITYR9_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR9_EL2) + .value("ICH_PPI_PRIORITYR10_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR10_EL2) + .value("ICH_PPI_PRIORITYR11_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR11_EL2) + .value("ICH_PPI_PRIORITYR12_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR12_EL2) + .value("ICH_PPI_PRIORITYR13_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR13_EL2) + .value("ICH_PPI_PRIORITYR14_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR14_EL2) + .value("ICH_PPI_PRIORITYR15_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_PRIORITYR15_EL2) + .value("TPIDR3_EL2", LIEF::assembly::aarch64::SYSREG::TPIDR3_EL2) + .value("CONTEXTIDR_EL2", LIEF::assembly::aarch64::SYSREG::CONTEXTIDR_EL2) + .value("TPIDR_EL2", LIEF::assembly::aarch64::SYSREG::TPIDR_EL2) + .value("SCXTNUM_EL2", LIEF::assembly::aarch64::SYSREG::SCXTNUM_EL2) + .value("AMEVCNTVOFF00_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF00_EL2) + .value("AMEVCNTVOFF01_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF01_EL2) + .value("AMEVCNTVOFF02_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF02_EL2) + .value("AMEVCNTVOFF03_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF03_EL2) + .value("AMEVCNTVOFF04_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF04_EL2) + .value("AMEVCNTVOFF05_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF05_EL2) + .value("AMEVCNTVOFF06_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF06_EL2) + .value("AMEVCNTVOFF07_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF07_EL2) + .value("AMEVCNTVOFF08_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF08_EL2) + .value("AMEVCNTVOFF09_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF09_EL2) + .value("AMEVCNTVOFF010_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF010_EL2) + .value("AMEVCNTVOFF011_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF011_EL2) + .value("AMEVCNTVOFF012_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF012_EL2) + .value("AMEVCNTVOFF013_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF013_EL2) + .value("AMEVCNTVOFF014_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF014_EL2) + .value("AMEVCNTVOFF015_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF015_EL2) + .value("AMEVCNTVOFF10_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF10_EL2) + .value("AMEVCNTVOFF11_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF11_EL2) + .value("AMEVCNTVOFF12_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF12_EL2) + .value("AMEVCNTVOFF13_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF13_EL2) + .value("AMEVCNTVOFF14_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF14_EL2) + .value("AMEVCNTVOFF15_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF15_EL2) + .value("AMEVCNTVOFF16_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF16_EL2) + .value("AMEVCNTVOFF17_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF17_EL2) + .value("AMEVCNTVOFF18_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF18_EL2) + .value("AMEVCNTVOFF19_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF19_EL2) + .value("AMEVCNTVOFF110_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF110_EL2) + .value("AMEVCNTVOFF111_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF111_EL2) + .value("AMEVCNTVOFF112_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF112_EL2) + .value("AMEVCNTVOFF113_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF113_EL2) + .value("AMEVCNTVOFF114_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF114_EL2) + .value("AMEVCNTVOFF115_EL2", LIEF::assembly::aarch64::SYSREG::AMEVCNTVOFF115_EL2) + .value("CNTVOFF_EL2", LIEF::assembly::aarch64::SYSREG::CNTVOFF_EL2) + .value("CNTSCALE_EL2", LIEF::assembly::aarch64::SYSREG::CNTSCALE_EL2) + .value("CNTISCALE_EL2", LIEF::assembly::aarch64::SYSREG::CNTISCALE_EL2) + .value("CNTPOFF_EL2", LIEF::assembly::aarch64::SYSREG::CNTPOFF_EL2) + .value("CNTVFRQ_EL2", LIEF::assembly::aarch64::SYSREG::CNTVFRQ_EL2) + .value("CNTHCTL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHCTL_EL2) + .value("CNTHP_TVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHP_TVAL_EL2) + .value("CNTHP_CTL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHP_CTL_EL2) + .value("CNTHP_CVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHP_CVAL_EL2) + .value("CNTHV_TVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHV_TVAL_EL2) + .value("CNTHV_CTL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHV_CTL_EL2) + .value("CNTHV_CVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHV_CVAL_EL2) + .value("CNTHVS_TVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHVS_TVAL_EL2) + .value("CNTHVS_CTL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHVS_CTL_EL2) + .value("CNTHVS_CVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHVS_CVAL_EL2) + .value("CNTHPS_TVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHPS_TVAL_EL2) + .value("CNTHPS_CTL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHPS_CTL_EL2) + .value("CNTHPS_CVAL_EL2", LIEF::assembly::aarch64::SYSREG::CNTHPS_CVAL_EL2) + .value("SCTLR_EL12", LIEF::assembly::aarch64::SYSREG::SCTLR_EL12) + .value("ACTLR_EL12", LIEF::assembly::aarch64::SYSREG::ACTLR_EL12) + .value("CPACR_EL12", LIEF::assembly::aarch64::SYSREG::CPACR_EL12) + .value("SCTLR2_EL12", LIEF::assembly::aarch64::SYSREG::SCTLR2_EL12) + .value("ZCR_EL12", LIEF::assembly::aarch64::SYSREG::ZCR_EL12) + .value("TRFCR_EL12", LIEF::assembly::aarch64::SYSREG::TRFCR_EL12) + .value("TRCITECR_EL12", LIEF::assembly::aarch64::SYSREG::TRCITECR_EL12) + .value("SMCR_EL12", LIEF::assembly::aarch64::SYSREG::SMCR_EL12) + .value("SCTLRMASK_EL12", LIEF::assembly::aarch64::SYSREG::SCTLRMASK_EL12) + .value("ACTLRMASK_EL12", LIEF::assembly::aarch64::SYSREG::ACTLRMASK_EL12) + .value("CPACRMASK_EL12", LIEF::assembly::aarch64::SYSREG::CPACRMASK_EL12) + .value("SCTLR2MASK_EL12", LIEF::assembly::aarch64::SYSREG::SCTLR2MASK_EL12) + .value("TTBR0_EL12", LIEF::assembly::aarch64::SYSREG::TTBR0_EL12) + .value("TTBR1_EL12", LIEF::assembly::aarch64::SYSREG::TTBR1_EL12) + .value("TCR_EL12", LIEF::assembly::aarch64::SYSREG::TCR_EL12) + .value("TCR2_EL12", LIEF::assembly::aarch64::SYSREG::TCR2_EL12) + .value("IRTBRU_EL12", LIEF::assembly::aarch64::SYSREG::IRTBRU_EL12) + .value("IRTBRP_EL12", LIEF::assembly::aarch64::SYSREG::IRTBRP_EL12) + .value("DPOTBR0_EL12", LIEF::assembly::aarch64::SYSREG::DPOTBR0_EL12) + .value("DPOTBR1_EL12", LIEF::assembly::aarch64::SYSREG::DPOTBR1_EL12) + .value("LDSTT_EL12", LIEF::assembly::aarch64::SYSREG::LDSTT_EL12) + .value("TPMIN0_EL12", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL12) + .value("TPMAX0_EL12", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL12) + .value("TPMIN1_EL12", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL12) + .value("TPMAX1_EL12", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL12) + .value("GCSCR_EL12", LIEF::assembly::aarch64::SYSREG::GCSCR_EL12) + .value("GCSPR_EL12", LIEF::assembly::aarch64::SYSREG::GCSPR_EL12) + .value("TCRMASK_EL12", LIEF::assembly::aarch64::SYSREG::TCRMASK_EL12) + .value("TCR2MASK_EL12", LIEF::assembly::aarch64::SYSREG::TCR2MASK_EL12) + .value("FGDTP0_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP0_EL12) + .value("FGDTP1_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP1_EL12) + .value("FGDTP2_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP2_EL12) + .value("FGDTP3_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP3_EL12) + .value("FGDTP4_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP4_EL12) + .value("FGDTP5_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP5_EL12) + .value("FGDTP6_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP6_EL12) + .value("FGDTP7_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP7_EL12) + .value("FGDTP8_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP8_EL12) + .value("FGDTP9_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP9_EL12) + .value("FGDTP10_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP10_EL12) + .value("FGDTP11_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP11_EL12) + .value("FGDTP12_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP12_EL12) + .value("FGDTP13_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP13_EL12) + .value("FGDTP14_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP14_EL12) + .value("FGDTP15_EL12", LIEF::assembly::aarch64::SYSREG::FGDTP15_EL12) + .value("FGDTU0_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU0_EL12) + .value("FGDTU1_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU1_EL12) + .value("FGDTU2_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU2_EL12) + .value("FGDTU3_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU3_EL12) + .value("FGDTU4_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU4_EL12) + .value("FGDTU5_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU5_EL12) + .value("FGDTU6_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU6_EL12) + .value("FGDTU7_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU7_EL12) + .value("FGDTU8_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU8_EL12) + .value("FGDTU9_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU9_EL12) + .value("FGDTU10_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU10_EL12) + .value("FGDTU11_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU11_EL12) + .value("FGDTU12_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU12_EL12) + .value("FGDTU13_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU13_EL12) + .value("FGDTU14_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU14_EL12) + .value("FGDTU15_EL12", LIEF::assembly::aarch64::SYSREG::FGDTU15_EL12) + .value("AFGDTP0_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP0_EL12) + .value("AFGDTP1_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP1_EL12) + .value("AFGDTP2_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP2_EL12) + .value("AFGDTP3_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP3_EL12) + .value("AFGDTP4_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP4_EL12) + .value("AFGDTP5_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP5_EL12) + .value("AFGDTP6_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP6_EL12) + .value("AFGDTP7_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP7_EL12) + .value("AFGDTP8_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP8_EL12) + .value("AFGDTP9_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP9_EL12) + .value("AFGDTP10_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP10_EL12) + .value("AFGDTP11_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP11_EL12) + .value("AFGDTP12_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP12_EL12) + .value("AFGDTP13_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP13_EL12) + .value("AFGDTP14_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP14_EL12) + .value("AFGDTP15_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTP15_EL12) + .value("AFGDTU0_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU0_EL12) + .value("AFGDTU1_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU1_EL12) + .value("AFGDTU2_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU2_EL12) + .value("AFGDTU3_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU3_EL12) + .value("AFGDTU4_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU4_EL12) + .value("AFGDTU5_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU5_EL12) + .value("AFGDTU6_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU6_EL12) + .value("AFGDTU7_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU7_EL12) + .value("AFGDTU8_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU8_EL12) + .value("AFGDTU9_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU9_EL12) + .value("AFGDTU10_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU10_EL12) + .value("AFGDTU11_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU11_EL12) + .value("AFGDTU12_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU12_EL12) + .value("AFGDTU13_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU13_EL12) + .value("AFGDTU14_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU14_EL12) + .value("AFGDTU15_EL12", LIEF::assembly::aarch64::SYSREG::AFGDTU15_EL12) + .value("SPSR_EL12", LIEF::assembly::aarch64::SYSREG::SPSR_EL12) + .value("ELR_EL12", LIEF::assembly::aarch64::SYSREG::ELR_EL12) + .value("STINDEX_EL12", LIEF::assembly::aarch64::SYSREG::STINDEX_EL12) + .value("TINDEX_EL12", LIEF::assembly::aarch64::SYSREG::TINDEX_EL12) + .value("AFSR0_EL12", LIEF::assembly::aarch64::SYSREG::AFSR0_EL12) + .value("AFSR1_EL12", LIEF::assembly::aarch64::SYSREG::AFSR1_EL12); + reg.value("ESR_EL12", LIEF::assembly::aarch64::SYSREG::ESR_EL12) + .value("TFSR_EL12", LIEF::assembly::aarch64::SYSREG::TFSR_EL12) + .value("FAR_EL12", LIEF::assembly::aarch64::SYSREG::FAR_EL12) + .value("PFAR_EL12", LIEF::assembly::aarch64::SYSREG::PFAR_EL12) + .value("PMSCR_EL12", LIEF::assembly::aarch64::SYSREG::PMSCR_EL12) + .value("PMBSR_EL12", LIEF::assembly::aarch64::SYSREG::PMBSR_EL12) + .value("TRBSR_EL12", LIEF::assembly::aarch64::SYSREG::TRBSR_EL12) + .value("MAIR_EL12", LIEF::assembly::aarch64::SYSREG::MAIR_EL12) + .value("MAIR2_EL12", LIEF::assembly::aarch64::SYSREG::MAIR2_EL12) + .value("PIRE0_EL12", LIEF::assembly::aarch64::SYSREG::PIRE0_EL12) + .value("PIR_EL12", LIEF::assembly::aarch64::SYSREG::PIR_EL12) + .value("POR_EL12", LIEF::assembly::aarch64::SYSREG::POR_EL12) + .value("TTTBRU_EL12", LIEF::assembly::aarch64::SYSREG::TTTBRU_EL12) + .value("TTTBRP_EL12", LIEF::assembly::aarch64::SYSREG::TTTBRP_EL12) + .value("AMAIR_EL12", LIEF::assembly::aarch64::SYSREG::AMAIR_EL12) + .value("AMAIR2_EL12", LIEF::assembly::aarch64::SYSREG::AMAIR2_EL12) + .value("MPAM1_EL12", LIEF::assembly::aarch64::SYSREG::MPAM1_EL12) + .value("MPAMCTL_EL12", LIEF::assembly::aarch64::SYSREG::MPAMCTL_EL12) + .value("MPAMBW1_EL12", LIEF::assembly::aarch64::SYSREG::MPAMBW1_EL12) + .value("VBAR_EL12", LIEF::assembly::aarch64::SYSREG::VBAR_EL12) + .value("TPIDR3_EL12", LIEF::assembly::aarch64::SYSREG::TPIDR3_EL12) + .value("CONTEXTIDR_EL12", LIEF::assembly::aarch64::SYSREG::CONTEXTIDR_EL12) + .value("SCXTNUM_EL12", LIEF::assembly::aarch64::SYSREG::SCXTNUM_EL12) + .value("CNTKCTL_EL12", LIEF::assembly::aarch64::SYSREG::CNTKCTL_EL12) + .value("CNTP_TVAL_EL02", LIEF::assembly::aarch64::SYSREG::CNTP_TVAL_EL02) + .value("CNTP_CTL_EL02", LIEF::assembly::aarch64::SYSREG::CNTP_CTL_EL02) + .value("CNTP_CVAL_EL02", LIEF::assembly::aarch64::SYSREG::CNTP_CVAL_EL02) + .value("CNTV_TVAL_EL02", LIEF::assembly::aarch64::SYSREG::CNTV_TVAL_EL02) + .value("CNTV_CTL_EL02", LIEF::assembly::aarch64::SYSREG::CNTV_CTL_EL02) + .value("CNTV_CVAL_EL02", LIEF::assembly::aarch64::SYSREG::CNTV_CVAL_EL02) + .value("SCTLR_EL3", LIEF::assembly::aarch64::SYSREG::SCTLR_EL3) + .value("ACTLR_EL3", LIEF::assembly::aarch64::SYSREG::ACTLR_EL3) + .value("SCTLR2_EL3", LIEF::assembly::aarch64::SYSREG::SCTLR2_EL3) + .value("SCR_EL3", LIEF::assembly::aarch64::SYSREG::SCR_EL3) + .value("SDER32_EL3", LIEF::assembly::aarch64::SYSREG::SDER32_EL3) + .value("CPTR_EL3", LIEF::assembly::aarch64::SYSREG::CPTR_EL3) + .value("FGWTE3_EL3", LIEF::assembly::aarch64::SYSREG::FGWTE3_EL3) + .value("ZCR_EL3", LIEF::assembly::aarch64::SYSREG::ZCR_EL3) + .value("SMCR_EL3", LIEF::assembly::aarch64::SYSREG::SMCR_EL3) + .value("MDCR_EL3", LIEF::assembly::aarch64::SYSREG::MDCR_EL3) + .value("TTBR0_EL3", LIEF::assembly::aarch64::SYSREG::TTBR0_EL3) + .value("TCR_EL3", LIEF::assembly::aarch64::SYSREG::TCR_EL3) + .value("IRTBRP_EL3", LIEF::assembly::aarch64::SYSREG::IRTBRP_EL3) + .value("DPOTBR0_EL3", LIEF::assembly::aarch64::SYSREG::DPOTBR0_EL3) + .value("GPTBR_EL3", LIEF::assembly::aarch64::SYSREG::GPTBR_EL3) + .value("GPCBW_EL3", LIEF::assembly::aarch64::SYSREG::GPCBW_EL3) + .value("GPCCR_EL3", LIEF::assembly::aarch64::SYSREG::GPCCR_EL3) + .value("GCSCR_EL3", LIEF::assembly::aarch64::SYSREG::GCSCR_EL3) + .value("GCSPR_EL3", LIEF::assembly::aarch64::SYSREG::GCSPR_EL3) + .value("FGDTP0_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP0_EL3) + .value("FGDTP1_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP1_EL3) + .value("FGDTP2_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP2_EL3) + .value("FGDTP3_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP3_EL3) + .value("FGDTP4_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP4_EL3) + .value("FGDTP5_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP5_EL3) + .value("FGDTP6_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP6_EL3) + .value("FGDTP7_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP7_EL3) + .value("FGDTP8_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP8_EL3) + .value("FGDTP9_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP9_EL3) + .value("FGDTP10_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP10_EL3) + .value("FGDTP11_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP11_EL3) + .value("FGDTP12_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP12_EL3) + .value("FGDTP13_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP13_EL3) + .value("FGDTP14_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP14_EL3) + .value("FGDTP15_EL3", LIEF::assembly::aarch64::SYSREG::FGDTP15_EL3) + .value("AFGDTP0_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP0_EL3) + .value("AFGDTP1_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP1_EL3) + .value("AFGDTP2_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP2_EL3) + .value("AFGDTP3_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP3_EL3) + .value("AFGDTP4_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP4_EL3) + .value("AFGDTP5_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP5_EL3) + .value("AFGDTP6_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP6_EL3) + .value("AFGDTP7_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP7_EL3) + .value("AFGDTP8_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP8_EL3) + .value("AFGDTP9_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP9_EL3) + .value("AFGDTP10_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP10_EL3) + .value("AFGDTP11_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP11_EL3) + .value("AFGDTP12_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP12_EL3) + .value("AFGDTP13_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP13_EL3) + .value("AFGDTP14_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP14_EL3) + .value("AFGDTP15_EL3", LIEF::assembly::aarch64::SYSREG::AFGDTP15_EL3) + .value("SPSR_EL3", LIEF::assembly::aarch64::SYSREG::SPSR_EL3) + .value("ELR_EL3", LIEF::assembly::aarch64::SYSREG::ELR_EL3) + .value("STINDEX_EL3", LIEF::assembly::aarch64::SYSREG::STINDEX_EL3) + .value("TINDEX_EL3", LIEF::assembly::aarch64::SYSREG::TINDEX_EL3) + .value("SP_EL2", LIEF::assembly::aarch64::SYSREG::SP_EL2) + .value("AFSR0_EL3", LIEF::assembly::aarch64::SYSREG::AFSR0_EL3) + .value("AFSR1_EL3", LIEF::assembly::aarch64::SYSREG::AFSR1_EL3) + .value("ESR_EL3", LIEF::assembly::aarch64::SYSREG::ESR_EL3) + .value("VSESR_EL3", LIEF::assembly::aarch64::SYSREG::VSESR_EL3) + .value("TFSR_EL3", LIEF::assembly::aarch64::SYSREG::TFSR_EL3) + .value("FAR_EL3", LIEF::assembly::aarch64::SYSREG::FAR_EL3) + .value("MFAR_EL3", LIEF::assembly::aarch64::SYSREG::MFAR_EL3) + .value("PMBSR_EL3", LIEF::assembly::aarch64::SYSREG::PMBSR_EL3) + .value("TRBSR_EL3", LIEF::assembly::aarch64::SYSREG::TRBSR_EL3) + .value("MAIR2_EL3", LIEF::assembly::aarch64::SYSREG::MAIR2_EL3) + .value("MAIR_EL3", LIEF::assembly::aarch64::SYSREG::MAIR_EL3) + .value("PIR_EL3", LIEF::assembly::aarch64::SYSREG::PIR_EL3) + .value("POR_EL3", LIEF::assembly::aarch64::SYSREG::POR_EL3) + .value("TTTBRP_EL3", LIEF::assembly::aarch64::SYSREG::TTTBRP_EL3) + .value("AMAIR_EL3", LIEF::assembly::aarch64::SYSREG::AMAIR_EL3) + .value("AMAIR2_EL3", LIEF::assembly::aarch64::SYSREG::AMAIR2_EL3) + .value("MPAM3_EL3", LIEF::assembly::aarch64::SYSREG::MPAM3_EL3) + .value("MPAMCTL_EL3", LIEF::assembly::aarch64::SYSREG::MPAMCTL_EL3) + .value("MPAMBW3_EL3", LIEF::assembly::aarch64::SYSREG::MPAMBW3_EL3) + .value("MPAMVIDSR_EL3", LIEF::assembly::aarch64::SYSREG::MPAMVIDSR_EL3) + .value("MECID_RL_A_EL3", LIEF::assembly::aarch64::SYSREG::MECID_RL_A_EL3) + .value("VBAR_EL3", LIEF::assembly::aarch64::SYSREG::VBAR_EL3) + .value("RVBAR_EL3", LIEF::assembly::aarch64::SYSREG::RVBAR_EL3) + .value("RMR_EL3", LIEF::assembly::aarch64::SYSREG::RMR_EL3) + .value("VDISR_EL3", LIEF::assembly::aarch64::SYSREG::VDISR_EL3) + .value("ICC_APR_EL3", LIEF::assembly::aarch64::SYSREG::ICC_APR_EL3) + .value("ICC_PCR_EL3", LIEF::assembly::aarch64::SYSREG::ICC_PCR_EL3) + .value("ICC_DOMHPPIR_EL3", LIEF::assembly::aarch64::SYSREG::ICC_DOMHPPIR_EL3) + .value("ICC_PPI_DOMAINR0_EL3", LIEF::assembly::aarch64::SYSREG::ICC_PPI_DOMAINR0_EL3) + .value("ICC_PPI_DOMAINR1_EL3", LIEF::assembly::aarch64::SYSREG::ICC_PPI_DOMAINR1_EL3) + .value("ICC_PPI_DOMAINR2_EL3", LIEF::assembly::aarch64::SYSREG::ICC_PPI_DOMAINR2_EL3) + .value("ICC_PPI_DOMAINR3_EL3", LIEF::assembly::aarch64::SYSREG::ICC_PPI_DOMAINR3_EL3) + .value("ICC_CR0_EL3", LIEF::assembly::aarch64::SYSREG::ICC_CR0_EL3) + .value("ICC_HPPIR_EL3", LIEF::assembly::aarch64::SYSREG::ICC_HPPIR_EL3) + .value("ICC_CTLR_EL3", LIEF::assembly::aarch64::SYSREG::ICC_CTLR_EL3) + .value("ICC_SRE_EL3", LIEF::assembly::aarch64::SYSREG::ICC_SRE_EL3) + .value("ICC_IGRPEN1_EL3", LIEF::assembly::aarch64::SYSREG::ICC_IGRPEN1_EL3) + .value("TPIDR3_EL3", LIEF::assembly::aarch64::SYSREG::TPIDR3_EL3) + .value("TPIDR_EL3", LIEF::assembly::aarch64::SYSREG::TPIDR_EL3) + .value("SCXTNUM_EL3", LIEF::assembly::aarch64::SYSREG::SCXTNUM_EL3) + .value("CNTPS_TVAL_EL1", LIEF::assembly::aarch64::SYSREG::CNTPS_TVAL_EL1) + .value("CNTPS_CTL_EL1", LIEF::assembly::aarch64::SYSREG::CNTPS_CTL_EL1) + .value("CNTPS_CVAL_EL1", LIEF::assembly::aarch64::SYSREG::CNTPS_CVAL_EL1) + .value("NUM_TARGET_SYSREGS", LIEF::assembly::aarch64::SYSREG::NUM_TARGET_SYSREGS) + ; +} + +} diff --git a/vendor/lief/api/python/src/asm/arm/CMakeLists.txt b/vendor/lief/api/python/src/asm/arm/CMakeLists.txt new file mode 100644 index 0000000..3d0bc18 --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyRegister.cpp +) diff --git a/vendor/lief/api/python/src/asm/arm/init.cpp b/vendor/lief/api/python/src/asm/arm/init.cpp new file mode 100644 index 0000000..3b1b805 --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/init.cpp @@ -0,0 +1,14 @@ +#include "asm/arm/init.hpp" +namespace LIEF::assembly::arm { +enum class OPCODE; +class Instruction; +} + +namespace LIEF::assembly::arm::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("arm"); + + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/arm/init.hpp b/vendor/lief/api/python/src/asm/arm/init.hpp new file mode 100644 index 0000000..2f72c1e --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_ARM_INIT_H +#define PY_LIEF_ASM_ARM_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::arm::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/arm/pyInstruction.cpp b/vendor/lief/api/python/src/asm/arm/pyInstruction.cpp new file mode 100644 index 0000000..0b8f404 --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/pyInstruction.cpp @@ -0,0 +1,20 @@ +#include "LIEF/asm/arm/Instruction.hpp" + +#include "asm/arm/init.hpp" + +namespace LIEF::assembly::arm::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents an ARM/Thumb instruction)doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/arm/pyOpcode.cpp b/vendor/lief/api/python/src/asm/arm/pyOpcode.cpp new file mode 100644 index 0000000..695f121 --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/pyOpcode.cpp @@ -0,0 +1,4531 @@ +#include "asm/arm/init.hpp" + +#include "LIEF/asm/arm/opcodes.hpp" + +namespace LIEF::assembly::arm::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::arm::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::arm::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::arm::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::arm::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::arm::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::arm::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::arm::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::arm::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::arm::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::arm::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::arm::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::arm::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::arm::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::arm::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::arm::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::arm::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::arm::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::arm::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::arm::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::arm::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::arm::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::arm::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::arm::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::arm::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::arm::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::arm::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::arm::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::arm::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::arm::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::arm::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::arm::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::arm::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::arm::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::arm::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::arm::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::arm::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::arm::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::arm::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::arm::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::arm::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::arm::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::arm::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::arm::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::arm::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::arm::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::arm::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::arm::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::arm::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::arm::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::arm::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::arm::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::arm::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::arm::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::arm::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::arm::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::arm::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::arm::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::arm::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::arm::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::arm::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::arm::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::arm::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::arm::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::arm::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::arm::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::arm::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::arm::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::arm::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::arm::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::arm::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::arm::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::arm::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::arm::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::arm::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::arm::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::arm::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::arm::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::arm::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::arm::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::arm::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::arm::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::arm::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::arm::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::arm::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::arm::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::arm::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::arm::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::arm::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::arm::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::arm::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::arm::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::arm::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::arm::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::arm::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::arm::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::arm::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::arm::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::arm::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::arm::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::arm::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::arm::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::arm::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::arm::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::arm::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::arm::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::arm::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::arm::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::arm::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::arm::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::arm::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::arm::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::arm::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::arm::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::arm::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::arm::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::arm::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::arm::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::arm::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::arm::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::arm::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::arm::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::arm::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::arm::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::arm::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::arm::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::arm::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::arm::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::arm::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::arm::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::arm::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::arm::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::arm::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::arm::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::arm::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::arm::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::arm::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::arm::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::arm::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::arm::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::arm::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::arm::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::arm::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::arm::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::arm::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::arm::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::arm::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::arm::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::arm::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::arm::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::arm::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::arm::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::arm::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::arm::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::arm::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::arm::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::arm::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::arm::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::arm::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::arm::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::arm::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::arm::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::arm::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::arm::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::arm::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::arm::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::arm::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::arm::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::arm::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::arm::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::arm::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::arm::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::arm::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::arm::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::arm::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::arm::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::arm::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::arm::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::arm::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::arm::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::arm::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::arm::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::arm::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::arm::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::arm::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::arm::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::arm::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::arm::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::arm::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::arm::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::arm::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::arm::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::arm::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::arm::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::arm::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::arm::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::arm::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::arm::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::arm::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::arm::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::arm::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::arm::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::arm::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::arm::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::arm::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::arm::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::arm::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::arm::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::arm::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::arm::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::arm::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::arm::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::arm::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::arm::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::arm::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::arm::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::arm::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::arm::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::arm::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::arm::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::arm::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::arm::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::arm::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::arm::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::arm::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::arm::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::arm::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::arm::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::arm::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::arm::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::arm::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::arm::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::arm::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::arm::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::arm::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::arm::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::arm::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::arm::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::arm::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::arm::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::arm::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::arm::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::arm::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::arm::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::arm::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::arm::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::arm::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::arm::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::arm::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::arm::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::arm::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::arm::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::arm::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::arm::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::arm::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::arm::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::arm::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::arm::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::arm::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::arm::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::arm::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::arm::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::arm::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::arm::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::arm::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::arm::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::arm::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::arm::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::arm::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::arm::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::arm::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::arm::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::arm::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::arm::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::arm::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::arm::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::arm::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::arm::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::arm::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::arm::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::arm::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::arm::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::arm::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::arm::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::arm::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::arm::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::arm::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::arm::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::arm::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::arm::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::arm::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::arm::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::arm::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::arm::OPCODE::G_UBFX) + .value("ADDSri", LIEF::assembly::arm::OPCODE::ADDSri) + .value("ADDSrr", LIEF::assembly::arm::OPCODE::ADDSrr) + .value("ADDSrsi", LIEF::assembly::arm::OPCODE::ADDSrsi) + .value("ADDSrsr", LIEF::assembly::arm::OPCODE::ADDSrsr) + .value("ADJCALLSTACKDOWN", LIEF::assembly::arm::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::arm::OPCODE::ADJCALLSTACKUP) + .value("ASRi", LIEF::assembly::arm::OPCODE::ASRi) + .value("ASRr", LIEF::assembly::arm::OPCODE::ASRr) + .value("ASRs1", LIEF::assembly::arm::OPCODE::ASRs1) + .value("B", LIEF::assembly::arm::OPCODE::B) + .value("BCCZi64", LIEF::assembly::arm::OPCODE::BCCZi64) + .value("BCCi64", LIEF::assembly::arm::OPCODE::BCCi64) + .value("BLX_noip", LIEF::assembly::arm::OPCODE::BLX_noip) + .value("BLX_pred_noip", LIEF::assembly::arm::OPCODE::BLX_pred_noip) + .value("BL_PUSHLR", LIEF::assembly::arm::OPCODE::BL_PUSHLR) + .value("BMOVPCB_CALL", LIEF::assembly::arm::OPCODE::BMOVPCB_CALL) + .value("BMOVPCRX_CALL", LIEF::assembly::arm::OPCODE::BMOVPCRX_CALL) + .value("BR_JTadd", LIEF::assembly::arm::OPCODE::BR_JTadd) + .value("BR_JTm_i12", LIEF::assembly::arm::OPCODE::BR_JTm_i12) + .value("BR_JTm_rs", LIEF::assembly::arm::OPCODE::BR_JTm_rs) + .value("BR_JTr", LIEF::assembly::arm::OPCODE::BR_JTr) + .value("BX_CALL", LIEF::assembly::arm::OPCODE::BX_CALL) + .value("CMP_SWAP_16", LIEF::assembly::arm::OPCODE::CMP_SWAP_16) + .value("CMP_SWAP_32", LIEF::assembly::arm::OPCODE::CMP_SWAP_32) + .value("CMP_SWAP_64", LIEF::assembly::arm::OPCODE::CMP_SWAP_64) + .value("CMP_SWAP_8", LIEF::assembly::arm::OPCODE::CMP_SWAP_8) + .value("CONSTPOOL_ENTRY", LIEF::assembly::arm::OPCODE::CONSTPOOL_ENTRY) + .value("COPY_STRUCT_BYVAL_I32", LIEF::assembly::arm::OPCODE::COPY_STRUCT_BYVAL_I32) + .value("ITasm", LIEF::assembly::arm::OPCODE::ITasm) + .value("Int_eh_sjlj_dispatchsetup", LIEF::assembly::arm::OPCODE::Int_eh_sjlj_dispatchsetup) + .value("Int_eh_sjlj_longjmp", LIEF::assembly::arm::OPCODE::Int_eh_sjlj_longjmp) + .value("Int_eh_sjlj_setjmp", LIEF::assembly::arm::OPCODE::Int_eh_sjlj_setjmp) + .value("Int_eh_sjlj_setjmp_nofp", LIEF::assembly::arm::OPCODE::Int_eh_sjlj_setjmp_nofp) + .value("Int_eh_sjlj_setup_dispatch", LIEF::assembly::arm::OPCODE::Int_eh_sjlj_setup_dispatch) + .value("JUMPTABLE_ADDRS", LIEF::assembly::arm::OPCODE::JUMPTABLE_ADDRS) + .value("JUMPTABLE_INSTS", LIEF::assembly::arm::OPCODE::JUMPTABLE_INSTS) + .value("JUMPTABLE_TBB", LIEF::assembly::arm::OPCODE::JUMPTABLE_TBB) + .value("JUMPTABLE_TBH", LIEF::assembly::arm::OPCODE::JUMPTABLE_TBH) + .value("KCFI_CHECK_ARM", LIEF::assembly::arm::OPCODE::KCFI_CHECK_ARM) + .value("KCFI_CHECK_Thumb1", LIEF::assembly::arm::OPCODE::KCFI_CHECK_Thumb1) + .value("KCFI_CHECK_Thumb2", LIEF::assembly::arm::OPCODE::KCFI_CHECK_Thumb2) + .value("LDMIA_RET", LIEF::assembly::arm::OPCODE::LDMIA_RET) + .value("LDRBT_POST", LIEF::assembly::arm::OPCODE::LDRBT_POST) + .value("LDRConstPool", LIEF::assembly::arm::OPCODE::LDRConstPool) + .value("LDRHTii", LIEF::assembly::arm::OPCODE::LDRHTii) + .value("LDRLIT_ga_abs", LIEF::assembly::arm::OPCODE::LDRLIT_ga_abs) + .value("LDRLIT_ga_pcrel", LIEF::assembly::arm::OPCODE::LDRLIT_ga_pcrel) + .value("LDRLIT_ga_pcrel_ldr", LIEF::assembly::arm::OPCODE::LDRLIT_ga_pcrel_ldr) + .value("LDRSBTii", LIEF::assembly::arm::OPCODE::LDRSBTii) + .value("LDRSHTii", LIEF::assembly::arm::OPCODE::LDRSHTii) + .value("LDRT_POST", LIEF::assembly::arm::OPCODE::LDRT_POST) + .value("LEApcrel", LIEF::assembly::arm::OPCODE::LEApcrel) + .value("LEApcrelJT", LIEF::assembly::arm::OPCODE::LEApcrelJT) + .value("LOADDUAL", LIEF::assembly::arm::OPCODE::LOADDUAL) + .value("LSLi", LIEF::assembly::arm::OPCODE::LSLi) + .value("LSLr", LIEF::assembly::arm::OPCODE::LSLr) + .value("LSRi", LIEF::assembly::arm::OPCODE::LSRi) + .value("LSRr", LIEF::assembly::arm::OPCODE::LSRr) + .value("LSRs1", LIEF::assembly::arm::OPCODE::LSRs1) + .value("MEMCPY", LIEF::assembly::arm::OPCODE::MEMCPY) + .value("MLAv5", LIEF::assembly::arm::OPCODE::MLAv5) + .value("MOVCCi", LIEF::assembly::arm::OPCODE::MOVCCi) + .value("MOVCCi16", LIEF::assembly::arm::OPCODE::MOVCCi16) + .value("MOVCCi32imm", LIEF::assembly::arm::OPCODE::MOVCCi32imm) + .value("MOVCCr", LIEF::assembly::arm::OPCODE::MOVCCr) + .value("MOVCCsi", LIEF::assembly::arm::OPCODE::MOVCCsi) + .value("MOVCCsr", LIEF::assembly::arm::OPCODE::MOVCCsr) + .value("MOVPCRX", LIEF::assembly::arm::OPCODE::MOVPCRX) + .value("MOVTi16_ga_pcrel", LIEF::assembly::arm::OPCODE::MOVTi16_ga_pcrel) + .value("MOV_ga_pcrel", LIEF::assembly::arm::OPCODE::MOV_ga_pcrel) + .value("MOV_ga_pcrel_ldr", LIEF::assembly::arm::OPCODE::MOV_ga_pcrel_ldr) + .value("MOVi16_ga_pcrel", LIEF::assembly::arm::OPCODE::MOVi16_ga_pcrel) + .value("MOVi32imm", LIEF::assembly::arm::OPCODE::MOVi32imm) + .value("MQPRCopy", LIEF::assembly::arm::OPCODE::MQPRCopy) + .value("MQQPRLoad", LIEF::assembly::arm::OPCODE::MQQPRLoad) + .value("MQQPRStore", LIEF::assembly::arm::OPCODE::MQQPRStore) + .value("MQQQQPRLoad", LIEF::assembly::arm::OPCODE::MQQQQPRLoad) + .value("MQQQQPRStore", LIEF::assembly::arm::OPCODE::MQQQQPRStore) + .value("MULv5", LIEF::assembly::arm::OPCODE::MULv5) + .value("MVE_MEMCPYLOOPINST", LIEF::assembly::arm::OPCODE::MVE_MEMCPYLOOPINST) + .value("MVE_MEMSETLOOPINST", LIEF::assembly::arm::OPCODE::MVE_MEMSETLOOPINST) + .value("MVNCCi", LIEF::assembly::arm::OPCODE::MVNCCi) + .value("PICADD", LIEF::assembly::arm::OPCODE::PICADD) + .value("PICLDR", LIEF::assembly::arm::OPCODE::PICLDR) + .value("PICLDRB", LIEF::assembly::arm::OPCODE::PICLDRB) + .value("PICLDRH", LIEF::assembly::arm::OPCODE::PICLDRH) + .value("PICLDRSB", LIEF::assembly::arm::OPCODE::PICLDRSB) + .value("PICLDRSH", LIEF::assembly::arm::OPCODE::PICLDRSH) + .value("PICSTR", LIEF::assembly::arm::OPCODE::PICSTR) + .value("PICSTRB", LIEF::assembly::arm::OPCODE::PICSTRB) + .value("PICSTRH", LIEF::assembly::arm::OPCODE::PICSTRH) + .value("RORi", LIEF::assembly::arm::OPCODE::RORi) + .value("RORr", LIEF::assembly::arm::OPCODE::RORr) + .value("RRX", LIEF::assembly::arm::OPCODE::RRX) + .value("RRXi", LIEF::assembly::arm::OPCODE::RRXi) + .value("RSBSri", LIEF::assembly::arm::OPCODE::RSBSri) + .value("RSBSrsi", LIEF::assembly::arm::OPCODE::RSBSrsi) + .value("RSBSrsr", LIEF::assembly::arm::OPCODE::RSBSrsr) + .value("SEH_EpilogEnd", LIEF::assembly::arm::OPCODE::SEH_EpilogEnd) + .value("SEH_EpilogStart", LIEF::assembly::arm::OPCODE::SEH_EpilogStart) + .value("SEH_Nop", LIEF::assembly::arm::OPCODE::SEH_Nop) + .value("SEH_Nop_Ret", LIEF::assembly::arm::OPCODE::SEH_Nop_Ret) + .value("SEH_PrologEnd", LIEF::assembly::arm::OPCODE::SEH_PrologEnd) + .value("SEH_SaveFRegs", LIEF::assembly::arm::OPCODE::SEH_SaveFRegs) + .value("SEH_SaveLR", LIEF::assembly::arm::OPCODE::SEH_SaveLR) + .value("SEH_SaveRegs", LIEF::assembly::arm::OPCODE::SEH_SaveRegs) + .value("SEH_SaveRegs_Ret", LIEF::assembly::arm::OPCODE::SEH_SaveRegs_Ret) + .value("SEH_SaveSP", LIEF::assembly::arm::OPCODE::SEH_SaveSP) + .value("SEH_StackAlloc", LIEF::assembly::arm::OPCODE::SEH_StackAlloc) + .value("SMLALv5", LIEF::assembly::arm::OPCODE::SMLALv5) + .value("SMULLv5", LIEF::assembly::arm::OPCODE::SMULLv5) + .value("SPACE", LIEF::assembly::arm::OPCODE::SPACE) + .value("STOREDUAL", LIEF::assembly::arm::OPCODE::STOREDUAL) + .value("STRBT_POST", LIEF::assembly::arm::OPCODE::STRBT_POST) + .value("STRBi_preidx", LIEF::assembly::arm::OPCODE::STRBi_preidx) + .value("STRBr_preidx", LIEF::assembly::arm::OPCODE::STRBr_preidx) + .value("STRH_preidx", LIEF::assembly::arm::OPCODE::STRH_preidx) + .value("STRT_POST", LIEF::assembly::arm::OPCODE::STRT_POST) + .value("STRi_preidx", LIEF::assembly::arm::OPCODE::STRi_preidx) + .value("STRr_preidx", LIEF::assembly::arm::OPCODE::STRr_preidx) + .value("SUBS_PC_LR", LIEF::assembly::arm::OPCODE::SUBS_PC_LR) + .value("SUBSri", LIEF::assembly::arm::OPCODE::SUBSri) + .value("SUBSrr", LIEF::assembly::arm::OPCODE::SUBSrr) + .value("SUBSrsi", LIEF::assembly::arm::OPCODE::SUBSrsi) + .value("SUBSrsr", LIEF::assembly::arm::OPCODE::SUBSrsr) + .value("SpeculationBarrierISBDSBEndBB", LIEF::assembly::arm::OPCODE::SpeculationBarrierISBDSBEndBB) + .value("SpeculationBarrierSBEndBB", LIEF::assembly::arm::OPCODE::SpeculationBarrierSBEndBB) + .value("TAILJMPd", LIEF::assembly::arm::OPCODE::TAILJMPd) + .value("TAILJMPr", LIEF::assembly::arm::OPCODE::TAILJMPr) + .value("TAILJMPr4", LIEF::assembly::arm::OPCODE::TAILJMPr4) + .value("TCRETURNdi", LIEF::assembly::arm::OPCODE::TCRETURNdi) + .value("TCRETURNri", LIEF::assembly::arm::OPCODE::TCRETURNri) + .value("TCRETURNrinotr12", LIEF::assembly::arm::OPCODE::TCRETURNrinotr12) + .value("TPsoft", LIEF::assembly::arm::OPCODE::TPsoft) + .value("UMLALv5", LIEF::assembly::arm::OPCODE::UMLALv5) + .value("UMULLv5", LIEF::assembly::arm::OPCODE::UMULLv5) + .value("VLD1LNdAsm_16", LIEF::assembly::arm::OPCODE::VLD1LNdAsm_16) + .value("VLD1LNdAsm_32", LIEF::assembly::arm::OPCODE::VLD1LNdAsm_32) + .value("VLD1LNdAsm_8", LIEF::assembly::arm::OPCODE::VLD1LNdAsm_8) + .value("VLD1LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD1LNdWB_fixed_Asm_16) + .value("VLD1LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD1LNdWB_fixed_Asm_32) + .value("VLD1LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD1LNdWB_fixed_Asm_8) + .value("VLD1LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD1LNdWB_register_Asm_16) + .value("VLD1LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD1LNdWB_register_Asm_32) + .value("VLD1LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD1LNdWB_register_Asm_8) + .value("VLD2LNdAsm_16", LIEF::assembly::arm::OPCODE::VLD2LNdAsm_16) + .value("VLD2LNdAsm_32", LIEF::assembly::arm::OPCODE::VLD2LNdAsm_32) + .value("VLD2LNdAsm_8", LIEF::assembly::arm::OPCODE::VLD2LNdAsm_8) + .value("VLD2LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD2LNdWB_fixed_Asm_16) + .value("VLD2LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD2LNdWB_fixed_Asm_32) + .value("VLD2LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD2LNdWB_fixed_Asm_8) + .value("VLD2LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD2LNdWB_register_Asm_16) + .value("VLD2LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD2LNdWB_register_Asm_32) + .value("VLD2LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD2LNdWB_register_Asm_8) + .value("VLD2LNqAsm_16", LIEF::assembly::arm::OPCODE::VLD2LNqAsm_16) + .value("VLD2LNqAsm_32", LIEF::assembly::arm::OPCODE::VLD2LNqAsm_32) + .value("VLD2LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD2LNqWB_fixed_Asm_16) + .value("VLD2LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD2LNqWB_fixed_Asm_32) + .value("VLD2LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD2LNqWB_register_Asm_16) + .value("VLD2LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD2LNqWB_register_Asm_32) + .value("VLD3DUPdAsm_16", LIEF::assembly::arm::OPCODE::VLD3DUPdAsm_16) + .value("VLD3DUPdAsm_32", LIEF::assembly::arm::OPCODE::VLD3DUPdAsm_32) + .value("VLD3DUPdAsm_8", LIEF::assembly::arm::OPCODE::VLD3DUPdAsm_8) + .value("VLD3DUPdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_fixed_Asm_16) + .value("VLD3DUPdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_fixed_Asm_32) + .value("VLD3DUPdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_fixed_Asm_8) + .value("VLD3DUPdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_register_Asm_16) + .value("VLD3DUPdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_register_Asm_32) + .value("VLD3DUPdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD3DUPdWB_register_Asm_8) + .value("VLD3DUPqAsm_16", LIEF::assembly::arm::OPCODE::VLD3DUPqAsm_16) + .value("VLD3DUPqAsm_32", LIEF::assembly::arm::OPCODE::VLD3DUPqAsm_32) + .value("VLD3DUPqAsm_8", LIEF::assembly::arm::OPCODE::VLD3DUPqAsm_8) + .value("VLD3DUPqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_fixed_Asm_16) + .value("VLD3DUPqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_fixed_Asm_32) + .value("VLD3DUPqWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_fixed_Asm_8) + .value("VLD3DUPqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_register_Asm_16) + .value("VLD3DUPqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_register_Asm_32) + .value("VLD3DUPqWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD3DUPqWB_register_Asm_8) + .value("VLD3LNdAsm_16", LIEF::assembly::arm::OPCODE::VLD3LNdAsm_16) + .value("VLD3LNdAsm_32", LIEF::assembly::arm::OPCODE::VLD3LNdAsm_32) + .value("VLD3LNdAsm_8", LIEF::assembly::arm::OPCODE::VLD3LNdAsm_8) + .value("VLD3LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3LNdWB_fixed_Asm_16) + .value("VLD3LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3LNdWB_fixed_Asm_32) + .value("VLD3LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD3LNdWB_fixed_Asm_8) + .value("VLD3LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3LNdWB_register_Asm_16) + .value("VLD3LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3LNdWB_register_Asm_32) + .value("VLD3LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD3LNdWB_register_Asm_8) + .value("VLD3LNqAsm_16", LIEF::assembly::arm::OPCODE::VLD3LNqAsm_16) + .value("VLD3LNqAsm_32", LIEF::assembly::arm::OPCODE::VLD3LNqAsm_32) + .value("VLD3LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3LNqWB_fixed_Asm_16) + .value("VLD3LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3LNqWB_fixed_Asm_32) + .value("VLD3LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3LNqWB_register_Asm_16) + .value("VLD3LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3LNqWB_register_Asm_32) + .value("VLD3dAsm_16", LIEF::assembly::arm::OPCODE::VLD3dAsm_16) + .value("VLD3dAsm_32", LIEF::assembly::arm::OPCODE::VLD3dAsm_32) + .value("VLD3dAsm_8", LIEF::assembly::arm::OPCODE::VLD3dAsm_8) + .value("VLD3dWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3dWB_fixed_Asm_16) + .value("VLD3dWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3dWB_fixed_Asm_32) + .value("VLD3dWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD3dWB_fixed_Asm_8) + .value("VLD3dWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3dWB_register_Asm_16) + .value("VLD3dWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3dWB_register_Asm_32) + .value("VLD3dWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD3dWB_register_Asm_8) + .value("VLD3qAsm_16", LIEF::assembly::arm::OPCODE::VLD3qAsm_16) + .value("VLD3qAsm_32", LIEF::assembly::arm::OPCODE::VLD3qAsm_32) + .value("VLD3qAsm_8", LIEF::assembly::arm::OPCODE::VLD3qAsm_8) + .value("VLD3qWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD3qWB_fixed_Asm_16) + .value("VLD3qWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD3qWB_fixed_Asm_32) + .value("VLD3qWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD3qWB_fixed_Asm_8) + .value("VLD3qWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD3qWB_register_Asm_16) + .value("VLD3qWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD3qWB_register_Asm_32) + .value("VLD3qWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD3qWB_register_Asm_8) + .value("VLD4DUPdAsm_16", LIEF::assembly::arm::OPCODE::VLD4DUPdAsm_16) + .value("VLD4DUPdAsm_32", LIEF::assembly::arm::OPCODE::VLD4DUPdAsm_32) + .value("VLD4DUPdAsm_8", LIEF::assembly::arm::OPCODE::VLD4DUPdAsm_8) + .value("VLD4DUPdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_fixed_Asm_16) + .value("VLD4DUPdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_fixed_Asm_32) + .value("VLD4DUPdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_fixed_Asm_8) + .value("VLD4DUPdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_register_Asm_16) + .value("VLD4DUPdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_register_Asm_32) + .value("VLD4DUPdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD4DUPdWB_register_Asm_8) + .value("VLD4DUPqAsm_16", LIEF::assembly::arm::OPCODE::VLD4DUPqAsm_16) + .value("VLD4DUPqAsm_32", LIEF::assembly::arm::OPCODE::VLD4DUPqAsm_32) + .value("VLD4DUPqAsm_8", LIEF::assembly::arm::OPCODE::VLD4DUPqAsm_8) + .value("VLD4DUPqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_fixed_Asm_16) + .value("VLD4DUPqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_fixed_Asm_32) + .value("VLD4DUPqWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_fixed_Asm_8) + .value("VLD4DUPqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_register_Asm_16) + .value("VLD4DUPqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_register_Asm_32) + .value("VLD4DUPqWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD4DUPqWB_register_Asm_8) + .value("VLD4LNdAsm_16", LIEF::assembly::arm::OPCODE::VLD4LNdAsm_16) + .value("VLD4LNdAsm_32", LIEF::assembly::arm::OPCODE::VLD4LNdAsm_32) + .value("VLD4LNdAsm_8", LIEF::assembly::arm::OPCODE::VLD4LNdAsm_8) + .value("VLD4LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4LNdWB_fixed_Asm_16) + .value("VLD4LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4LNdWB_fixed_Asm_32) + .value("VLD4LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD4LNdWB_fixed_Asm_8) + .value("VLD4LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4LNdWB_register_Asm_16) + .value("VLD4LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4LNdWB_register_Asm_32) + .value("VLD4LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD4LNdWB_register_Asm_8) + .value("VLD4LNqAsm_16", LIEF::assembly::arm::OPCODE::VLD4LNqAsm_16) + .value("VLD4LNqAsm_32", LIEF::assembly::arm::OPCODE::VLD4LNqAsm_32) + .value("VLD4LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4LNqWB_fixed_Asm_16) + .value("VLD4LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4LNqWB_fixed_Asm_32) + .value("VLD4LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4LNqWB_register_Asm_16) + .value("VLD4LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4LNqWB_register_Asm_32) + .value("VLD4dAsm_16", LIEF::assembly::arm::OPCODE::VLD4dAsm_16) + .value("VLD4dAsm_32", LIEF::assembly::arm::OPCODE::VLD4dAsm_32) + .value("VLD4dAsm_8", LIEF::assembly::arm::OPCODE::VLD4dAsm_8) + .value("VLD4dWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4dWB_fixed_Asm_16) + .value("VLD4dWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4dWB_fixed_Asm_32) + .value("VLD4dWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD4dWB_fixed_Asm_8) + .value("VLD4dWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4dWB_register_Asm_16) + .value("VLD4dWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4dWB_register_Asm_32) + .value("VLD4dWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD4dWB_register_Asm_8) + .value("VLD4qAsm_16", LIEF::assembly::arm::OPCODE::VLD4qAsm_16) + .value("VLD4qAsm_32", LIEF::assembly::arm::OPCODE::VLD4qAsm_32) + .value("VLD4qAsm_8", LIEF::assembly::arm::OPCODE::VLD4qAsm_8) + .value("VLD4qWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VLD4qWB_fixed_Asm_16) + .value("VLD4qWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VLD4qWB_fixed_Asm_32) + .value("VLD4qWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VLD4qWB_fixed_Asm_8) + .value("VLD4qWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VLD4qWB_register_Asm_16) + .value("VLD4qWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VLD4qWB_register_Asm_32) + .value("VLD4qWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VLD4qWB_register_Asm_8) + .value("VMOVD0", LIEF::assembly::arm::OPCODE::VMOVD0) + .value("VMOVDcc", LIEF::assembly::arm::OPCODE::VMOVDcc) + .value("VMOVHcc", LIEF::assembly::arm::OPCODE::VMOVHcc) + .value("VMOVQ0", LIEF::assembly::arm::OPCODE::VMOVQ0) + .value("VMOVScc", LIEF::assembly::arm::OPCODE::VMOVScc) + .value("VST1LNdAsm_16", LIEF::assembly::arm::OPCODE::VST1LNdAsm_16) + .value("VST1LNdAsm_32", LIEF::assembly::arm::OPCODE::VST1LNdAsm_32) + .value("VST1LNdAsm_8", LIEF::assembly::arm::OPCODE::VST1LNdAsm_8) + .value("VST1LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST1LNdWB_fixed_Asm_16) + .value("VST1LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST1LNdWB_fixed_Asm_32) + .value("VST1LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST1LNdWB_fixed_Asm_8) + .value("VST1LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST1LNdWB_register_Asm_16) + .value("VST1LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST1LNdWB_register_Asm_32) + .value("VST1LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST1LNdWB_register_Asm_8) + .value("VST2LNdAsm_16", LIEF::assembly::arm::OPCODE::VST2LNdAsm_16) + .value("VST2LNdAsm_32", LIEF::assembly::arm::OPCODE::VST2LNdAsm_32); + opcodes.value("VST2LNdAsm_8", LIEF::assembly::arm::OPCODE::VST2LNdAsm_8) + .value("VST2LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_16) + .value("VST2LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_32) + .value("VST2LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_8) + .value("VST2LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST2LNdWB_register_Asm_16) + .value("VST2LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST2LNdWB_register_Asm_32) + .value("VST2LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST2LNdWB_register_Asm_8) + .value("VST2LNqAsm_16", LIEF::assembly::arm::OPCODE::VST2LNqAsm_16) + .value("VST2LNqAsm_32", LIEF::assembly::arm::OPCODE::VST2LNqAsm_32) + .value("VST2LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST2LNqWB_fixed_Asm_16) + .value("VST2LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST2LNqWB_fixed_Asm_32) + .value("VST2LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST2LNqWB_register_Asm_16) + .value("VST2LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST2LNqWB_register_Asm_32) + .value("VST3LNdAsm_16", LIEF::assembly::arm::OPCODE::VST3LNdAsm_16) + .value("VST3LNdAsm_32", LIEF::assembly::arm::OPCODE::VST3LNdAsm_32) + .value("VST3LNdAsm_8", LIEF::assembly::arm::OPCODE::VST3LNdAsm_8) + .value("VST3LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST3LNdWB_fixed_Asm_16) + .value("VST3LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST3LNdWB_fixed_Asm_32) + .value("VST3LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST3LNdWB_fixed_Asm_8) + .value("VST3LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST3LNdWB_register_Asm_16) + .value("VST3LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST3LNdWB_register_Asm_32) + .value("VST3LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST3LNdWB_register_Asm_8) + .value("VST3LNqAsm_16", LIEF::assembly::arm::OPCODE::VST3LNqAsm_16) + .value("VST3LNqAsm_32", LIEF::assembly::arm::OPCODE::VST3LNqAsm_32) + .value("VST3LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST3LNqWB_fixed_Asm_16) + .value("VST3LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST3LNqWB_fixed_Asm_32) + .value("VST3LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST3LNqWB_register_Asm_16) + .value("VST3LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST3LNqWB_register_Asm_32) + .value("VST3dAsm_16", LIEF::assembly::arm::OPCODE::VST3dAsm_16) + .value("VST3dAsm_32", LIEF::assembly::arm::OPCODE::VST3dAsm_32) + .value("VST3dAsm_8", LIEF::assembly::arm::OPCODE::VST3dAsm_8) + .value("VST3dWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST3dWB_fixed_Asm_16) + .value("VST3dWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST3dWB_fixed_Asm_32) + .value("VST3dWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST3dWB_fixed_Asm_8) + .value("VST3dWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST3dWB_register_Asm_16) + .value("VST3dWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST3dWB_register_Asm_32) + .value("VST3dWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST3dWB_register_Asm_8) + .value("VST3qAsm_16", LIEF::assembly::arm::OPCODE::VST3qAsm_16) + .value("VST3qAsm_32", LIEF::assembly::arm::OPCODE::VST3qAsm_32) + .value("VST3qAsm_8", LIEF::assembly::arm::OPCODE::VST3qAsm_8) + .value("VST3qWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST3qWB_fixed_Asm_16) + .value("VST3qWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST3qWB_fixed_Asm_32) + .value("VST3qWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST3qWB_fixed_Asm_8) + .value("VST3qWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST3qWB_register_Asm_16) + .value("VST3qWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST3qWB_register_Asm_32) + .value("VST3qWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST3qWB_register_Asm_8) + .value("VST4LNdAsm_16", LIEF::assembly::arm::OPCODE::VST4LNdAsm_16) + .value("VST4LNdAsm_32", LIEF::assembly::arm::OPCODE::VST4LNdAsm_32) + .value("VST4LNdAsm_8", LIEF::assembly::arm::OPCODE::VST4LNdAsm_8) + .value("VST4LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST4LNdWB_fixed_Asm_16) + .value("VST4LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST4LNdWB_fixed_Asm_32) + .value("VST4LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST4LNdWB_fixed_Asm_8) + .value("VST4LNdWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST4LNdWB_register_Asm_16) + .value("VST4LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST4LNdWB_register_Asm_32) + .value("VST4LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST4LNdWB_register_Asm_8) + .value("VST4LNqAsm_16", LIEF::assembly::arm::OPCODE::VST4LNqAsm_16) + .value("VST4LNqAsm_32", LIEF::assembly::arm::OPCODE::VST4LNqAsm_32) + .value("VST4LNqWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST4LNqWB_fixed_Asm_16) + .value("VST4LNqWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST4LNqWB_fixed_Asm_32) + .value("VST4LNqWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST4LNqWB_register_Asm_16) + .value("VST4LNqWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST4LNqWB_register_Asm_32) + .value("VST4dAsm_16", LIEF::assembly::arm::OPCODE::VST4dAsm_16) + .value("VST4dAsm_32", LIEF::assembly::arm::OPCODE::VST4dAsm_32) + .value("VST4dAsm_8", LIEF::assembly::arm::OPCODE::VST4dAsm_8) + .value("VST4dWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST4dWB_fixed_Asm_16) + .value("VST4dWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST4dWB_fixed_Asm_32) + .value("VST4dWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST4dWB_fixed_Asm_8) + .value("VST4dWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST4dWB_register_Asm_16) + .value("VST4dWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST4dWB_register_Asm_32) + .value("VST4dWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST4dWB_register_Asm_8) + .value("VST4qAsm_16", LIEF::assembly::arm::OPCODE::VST4qAsm_16) + .value("VST4qAsm_32", LIEF::assembly::arm::OPCODE::VST4qAsm_32) + .value("VST4qAsm_8", LIEF::assembly::arm::OPCODE::VST4qAsm_8) + .value("VST4qWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST4qWB_fixed_Asm_16) + .value("VST4qWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST4qWB_fixed_Asm_32) + .value("VST4qWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST4qWB_fixed_Asm_8) + .value("VST4qWB_register_Asm_16", LIEF::assembly::arm::OPCODE::VST4qWB_register_Asm_16) + .value("VST4qWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST4qWB_register_Asm_32) + .value("VST4qWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST4qWB_register_Asm_8) + .value("WIN__CHKSTK", LIEF::assembly::arm::OPCODE::WIN__CHKSTK) + .value("WIN__DBZCHK", LIEF::assembly::arm::OPCODE::WIN__DBZCHK) + .value("t2ADDSri", LIEF::assembly::arm::OPCODE::t2ADDSri) + .value("t2ADDSrr", LIEF::assembly::arm::OPCODE::t2ADDSrr) + .value("t2ADDSrs", LIEF::assembly::arm::OPCODE::t2ADDSrs) + .value("t2BF_LabelPseudo", LIEF::assembly::arm::OPCODE::t2BF_LabelPseudo) + .value("t2BR_JT", LIEF::assembly::arm::OPCODE::t2BR_JT) + .value("t2CALL_BTI", LIEF::assembly::arm::OPCODE::t2CALL_BTI) + .value("t2DoLoopStart", LIEF::assembly::arm::OPCODE::t2DoLoopStart) + .value("t2DoLoopStartTP", LIEF::assembly::arm::OPCODE::t2DoLoopStartTP) + .value("t2LDMIA_RET", LIEF::assembly::arm::OPCODE::t2LDMIA_RET) + .value("t2LDRB_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2LDRB_OFFSET_imm) + .value("t2LDRB_POST_imm", LIEF::assembly::arm::OPCODE::t2LDRB_POST_imm) + .value("t2LDRB_PRE_imm", LIEF::assembly::arm::OPCODE::t2LDRB_PRE_imm) + .value("t2LDRBpcrel", LIEF::assembly::arm::OPCODE::t2LDRBpcrel) + .value("t2LDRConstPool", LIEF::assembly::arm::OPCODE::t2LDRConstPool) + .value("t2LDRH_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2LDRH_OFFSET_imm) + .value("t2LDRH_POST_imm", LIEF::assembly::arm::OPCODE::t2LDRH_POST_imm) + .value("t2LDRH_PRE_imm", LIEF::assembly::arm::OPCODE::t2LDRH_PRE_imm) + .value("t2LDRHpcrel", LIEF::assembly::arm::OPCODE::t2LDRHpcrel) + .value("t2LDRLIT_ga_pcrel", LIEF::assembly::arm::OPCODE::t2LDRLIT_ga_pcrel) + .value("t2LDRSB_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2LDRSB_OFFSET_imm) + .value("t2LDRSB_POST_imm", LIEF::assembly::arm::OPCODE::t2LDRSB_POST_imm) + .value("t2LDRSB_PRE_imm", LIEF::assembly::arm::OPCODE::t2LDRSB_PRE_imm) + .value("t2LDRSBpcrel", LIEF::assembly::arm::OPCODE::t2LDRSBpcrel) + .value("t2LDRSH_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2LDRSH_OFFSET_imm) + .value("t2LDRSH_POST_imm", LIEF::assembly::arm::OPCODE::t2LDRSH_POST_imm) + .value("t2LDRSH_PRE_imm", LIEF::assembly::arm::OPCODE::t2LDRSH_PRE_imm) + .value("t2LDRSHpcrel", LIEF::assembly::arm::OPCODE::t2LDRSHpcrel) + .value("t2LDR_POST_imm", LIEF::assembly::arm::OPCODE::t2LDR_POST_imm) + .value("t2LDR_PRE_imm", LIEF::assembly::arm::OPCODE::t2LDR_PRE_imm) + .value("t2LDRpci_pic", LIEF::assembly::arm::OPCODE::t2LDRpci_pic) + .value("t2LDRpcrel", LIEF::assembly::arm::OPCODE::t2LDRpcrel) + .value("t2LEApcrel", LIEF::assembly::arm::OPCODE::t2LEApcrel) + .value("t2LEApcrelJT", LIEF::assembly::arm::OPCODE::t2LEApcrelJT) + .value("t2LoopDec", LIEF::assembly::arm::OPCODE::t2LoopDec) + .value("t2LoopEnd", LIEF::assembly::arm::OPCODE::t2LoopEnd) + .value("t2LoopEndDec", LIEF::assembly::arm::OPCODE::t2LoopEndDec) + .value("t2MOVCCasr", LIEF::assembly::arm::OPCODE::t2MOVCCasr) + .value("t2MOVCCi", LIEF::assembly::arm::OPCODE::t2MOVCCi) + .value("t2MOVCCi16", LIEF::assembly::arm::OPCODE::t2MOVCCi16) + .value("t2MOVCCi32imm", LIEF::assembly::arm::OPCODE::t2MOVCCi32imm) + .value("t2MOVCClsl", LIEF::assembly::arm::OPCODE::t2MOVCClsl) + .value("t2MOVCClsr", LIEF::assembly::arm::OPCODE::t2MOVCClsr) + .value("t2MOVCCr", LIEF::assembly::arm::OPCODE::t2MOVCCr) + .value("t2MOVCCror", LIEF::assembly::arm::OPCODE::t2MOVCCror) + .value("t2MOVSsi", LIEF::assembly::arm::OPCODE::t2MOVSsi) + .value("t2MOVSsr", LIEF::assembly::arm::OPCODE::t2MOVSsr) + .value("t2MOVTi16_ga_pcrel", LIEF::assembly::arm::OPCODE::t2MOVTi16_ga_pcrel) + .value("t2MOV_ga_pcrel", LIEF::assembly::arm::OPCODE::t2MOV_ga_pcrel) + .value("t2MOVi16_ga_pcrel", LIEF::assembly::arm::OPCODE::t2MOVi16_ga_pcrel) + .value("t2MOVi32imm", LIEF::assembly::arm::OPCODE::t2MOVi32imm) + .value("t2MOVsi", LIEF::assembly::arm::OPCODE::t2MOVsi) + .value("t2MOVsr", LIEF::assembly::arm::OPCODE::t2MOVsr) + .value("t2MVNCCi", LIEF::assembly::arm::OPCODE::t2MVNCCi) + .value("t2RSBSri", LIEF::assembly::arm::OPCODE::t2RSBSri) + .value("t2RSBSrs", LIEF::assembly::arm::OPCODE::t2RSBSrs) + .value("t2STRB_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2STRB_OFFSET_imm) + .value("t2STRB_POST_imm", LIEF::assembly::arm::OPCODE::t2STRB_POST_imm) + .value("t2STRB_PRE_imm", LIEF::assembly::arm::OPCODE::t2STRB_PRE_imm) + .value("t2STRB_preidx", LIEF::assembly::arm::OPCODE::t2STRB_preidx) + .value("t2STRH_OFFSET_imm", LIEF::assembly::arm::OPCODE::t2STRH_OFFSET_imm) + .value("t2STRH_POST_imm", LIEF::assembly::arm::OPCODE::t2STRH_POST_imm) + .value("t2STRH_PRE_imm", LIEF::assembly::arm::OPCODE::t2STRH_PRE_imm) + .value("t2STRH_preidx", LIEF::assembly::arm::OPCODE::t2STRH_preidx) + .value("t2STR_POST_imm", LIEF::assembly::arm::OPCODE::t2STR_POST_imm) + .value("t2STR_PRE_imm", LIEF::assembly::arm::OPCODE::t2STR_PRE_imm) + .value("t2STR_preidx", LIEF::assembly::arm::OPCODE::t2STR_preidx) + .value("t2SUBSri", LIEF::assembly::arm::OPCODE::t2SUBSri) + .value("t2SUBSrr", LIEF::assembly::arm::OPCODE::t2SUBSrr) + .value("t2SUBSrs", LIEF::assembly::arm::OPCODE::t2SUBSrs) + .value("t2SpeculationBarrierISBDSBEndBB", LIEF::assembly::arm::OPCODE::t2SpeculationBarrierISBDSBEndBB) + .value("t2SpeculationBarrierSBEndBB", LIEF::assembly::arm::OPCODE::t2SpeculationBarrierSBEndBB) + .value("t2TBB_JT", LIEF::assembly::arm::OPCODE::t2TBB_JT) + .value("t2TBH_JT", LIEF::assembly::arm::OPCODE::t2TBH_JT) + .value("t2WhileLoopSetup", LIEF::assembly::arm::OPCODE::t2WhileLoopSetup) + .value("t2WhileLoopStart", LIEF::assembly::arm::OPCODE::t2WhileLoopStart) + .value("t2WhileLoopStartLR", LIEF::assembly::arm::OPCODE::t2WhileLoopStartLR) + .value("t2WhileLoopStartTP", LIEF::assembly::arm::OPCODE::t2WhileLoopStartTP) + .value("tADCS", LIEF::assembly::arm::OPCODE::tADCS) + .value("tADDSi3", LIEF::assembly::arm::OPCODE::tADDSi3) + .value("tADDSi8", LIEF::assembly::arm::OPCODE::tADDSi8) + .value("tADDSrr", LIEF::assembly::arm::OPCODE::tADDSrr) + .value("tADDframe", LIEF::assembly::arm::OPCODE::tADDframe) + .value("tADJCALLSTACKDOWN", LIEF::assembly::arm::OPCODE::tADJCALLSTACKDOWN) + .value("tADJCALLSTACKUP", LIEF::assembly::arm::OPCODE::tADJCALLSTACKUP) + .value("tBLXNS_CALL", LIEF::assembly::arm::OPCODE::tBLXNS_CALL) + .value("tBLXr_noip", LIEF::assembly::arm::OPCODE::tBLXr_noip) + .value("tBL_PUSHLR", LIEF::assembly::arm::OPCODE::tBL_PUSHLR) + .value("tBRIND", LIEF::assembly::arm::OPCODE::tBRIND) + .value("tBR_JTr", LIEF::assembly::arm::OPCODE::tBR_JTr) + .value("tBXNS_RET", LIEF::assembly::arm::OPCODE::tBXNS_RET) + .value("tBX_CALL", LIEF::assembly::arm::OPCODE::tBX_CALL) + .value("tBX_RET", LIEF::assembly::arm::OPCODE::tBX_RET) + .value("tBX_RET_vararg", LIEF::assembly::arm::OPCODE::tBX_RET_vararg) + .value("tBfar", LIEF::assembly::arm::OPCODE::tBfar) + .value("tCMP_SWAP_16", LIEF::assembly::arm::OPCODE::tCMP_SWAP_16) + .value("tCMP_SWAP_32", LIEF::assembly::arm::OPCODE::tCMP_SWAP_32) + .value("tCMP_SWAP_8", LIEF::assembly::arm::OPCODE::tCMP_SWAP_8) + .value("tLDMIA_UPD", LIEF::assembly::arm::OPCODE::tLDMIA_UPD) + .value("tLDRConstPool", LIEF::assembly::arm::OPCODE::tLDRConstPool) + .value("tLDRLIT_ga_abs", LIEF::assembly::arm::OPCODE::tLDRLIT_ga_abs) + .value("tLDRLIT_ga_pcrel", LIEF::assembly::arm::OPCODE::tLDRLIT_ga_pcrel) + .value("tLDR_postidx", LIEF::assembly::arm::OPCODE::tLDR_postidx) + .value("tLDRpci_pic", LIEF::assembly::arm::OPCODE::tLDRpci_pic) + .value("tLEApcrel", LIEF::assembly::arm::OPCODE::tLEApcrel) + .value("tLEApcrelJT", LIEF::assembly::arm::OPCODE::tLEApcrelJT) + .value("tLSLSri", LIEF::assembly::arm::OPCODE::tLSLSri) + .value("tMOVCCr_pseudo", LIEF::assembly::arm::OPCODE::tMOVCCr_pseudo) + .value("tMOVi32imm", LIEF::assembly::arm::OPCODE::tMOVi32imm) + .value("tPOP_RET", LIEF::assembly::arm::OPCODE::tPOP_RET) + .value("tRSBS", LIEF::assembly::arm::OPCODE::tRSBS) + .value("tSBCS", LIEF::assembly::arm::OPCODE::tSBCS) + .value("tSUBSi3", LIEF::assembly::arm::OPCODE::tSUBSi3) + .value("tSUBSi8", LIEF::assembly::arm::OPCODE::tSUBSi8) + .value("tSUBSrr", LIEF::assembly::arm::OPCODE::tSUBSrr) + .value("tTAILJMPd", LIEF::assembly::arm::OPCODE::tTAILJMPd) + .value("tTAILJMPdND", LIEF::assembly::arm::OPCODE::tTAILJMPdND) + .value("tTAILJMPr", LIEF::assembly::arm::OPCODE::tTAILJMPr) + .value("tTBB_JT", LIEF::assembly::arm::OPCODE::tTBB_JT) + .value("tTBH_JT", LIEF::assembly::arm::OPCODE::tTBH_JT) + .value("tTPsoft", LIEF::assembly::arm::OPCODE::tTPsoft) + .value("ADCri", LIEF::assembly::arm::OPCODE::ADCri) + .value("ADCrr", LIEF::assembly::arm::OPCODE::ADCrr) + .value("ADCrsi", LIEF::assembly::arm::OPCODE::ADCrsi) + .value("ADCrsr", LIEF::assembly::arm::OPCODE::ADCrsr) + .value("ADDri", LIEF::assembly::arm::OPCODE::ADDri) + .value("ADDrr", LIEF::assembly::arm::OPCODE::ADDrr) + .value("ADDrsi", LIEF::assembly::arm::OPCODE::ADDrsi) + .value("ADDrsr", LIEF::assembly::arm::OPCODE::ADDrsr) + .value("ADR", LIEF::assembly::arm::OPCODE::ADR) + .value("AESD", LIEF::assembly::arm::OPCODE::AESD) + .value("AESE", LIEF::assembly::arm::OPCODE::AESE) + .value("AESIMC", LIEF::assembly::arm::OPCODE::AESIMC) + .value("AESMC", LIEF::assembly::arm::OPCODE::AESMC) + .value("ANDri", LIEF::assembly::arm::OPCODE::ANDri) + .value("ANDrr", LIEF::assembly::arm::OPCODE::ANDrr) + .value("ANDrsi", LIEF::assembly::arm::OPCODE::ANDrsi) + .value("ANDrsr", LIEF::assembly::arm::OPCODE::ANDrsr) + .value("BF16VDOTI_VDOTD", LIEF::assembly::arm::OPCODE::BF16VDOTI_VDOTD) + .value("BF16VDOTI_VDOTQ", LIEF::assembly::arm::OPCODE::BF16VDOTI_VDOTQ) + .value("BF16VDOTS_VDOTD", LIEF::assembly::arm::OPCODE::BF16VDOTS_VDOTD) + .value("BF16VDOTS_VDOTQ", LIEF::assembly::arm::OPCODE::BF16VDOTS_VDOTQ) + .value("BF16_VCVT", LIEF::assembly::arm::OPCODE::BF16_VCVT) + .value("BF16_VCVTB", LIEF::assembly::arm::OPCODE::BF16_VCVTB) + .value("BF16_VCVTT", LIEF::assembly::arm::OPCODE::BF16_VCVTT) + .value("BFC", LIEF::assembly::arm::OPCODE::BFC) + .value("BFI", LIEF::assembly::arm::OPCODE::BFI) + .value("BICri", LIEF::assembly::arm::OPCODE::BICri) + .value("BICrr", LIEF::assembly::arm::OPCODE::BICrr) + .value("BICrsi", LIEF::assembly::arm::OPCODE::BICrsi) + .value("BICrsr", LIEF::assembly::arm::OPCODE::BICrsr) + .value("BKPT", LIEF::assembly::arm::OPCODE::BKPT) + .value("BL", LIEF::assembly::arm::OPCODE::BL) + .value("BLX", LIEF::assembly::arm::OPCODE::BLX) + .value("BLX_pred", LIEF::assembly::arm::OPCODE::BLX_pred) + .value("BLXi", LIEF::assembly::arm::OPCODE::BLXi) + .value("BL_pred", LIEF::assembly::arm::OPCODE::BL_pred) + .value("BX", LIEF::assembly::arm::OPCODE::BX) + .value("BXJ", LIEF::assembly::arm::OPCODE::BXJ) + .value("BX_RET", LIEF::assembly::arm::OPCODE::BX_RET) + .value("BX_pred", LIEF::assembly::arm::OPCODE::BX_pred) + .value("Bcc", LIEF::assembly::arm::OPCODE::Bcc) + .value("CDE_CX1", LIEF::assembly::arm::OPCODE::CDE_CX1) + .value("CDE_CX1A", LIEF::assembly::arm::OPCODE::CDE_CX1A) + .value("CDE_CX1D", LIEF::assembly::arm::OPCODE::CDE_CX1D) + .value("CDE_CX1DA", LIEF::assembly::arm::OPCODE::CDE_CX1DA) + .value("CDE_CX2", LIEF::assembly::arm::OPCODE::CDE_CX2) + .value("CDE_CX2A", LIEF::assembly::arm::OPCODE::CDE_CX2A) + .value("CDE_CX2D", LIEF::assembly::arm::OPCODE::CDE_CX2D) + .value("CDE_CX2DA", LIEF::assembly::arm::OPCODE::CDE_CX2DA) + .value("CDE_CX3", LIEF::assembly::arm::OPCODE::CDE_CX3) + .value("CDE_CX3A", LIEF::assembly::arm::OPCODE::CDE_CX3A) + .value("CDE_CX3D", LIEF::assembly::arm::OPCODE::CDE_CX3D) + .value("CDE_CX3DA", LIEF::assembly::arm::OPCODE::CDE_CX3DA) + .value("CDE_VCX1A_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX1A_fpdp) + .value("CDE_VCX1A_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX1A_fpsp) + .value("CDE_VCX1A_vec", LIEF::assembly::arm::OPCODE::CDE_VCX1A_vec) + .value("CDE_VCX1_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX1_fpdp) + .value("CDE_VCX1_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX1_fpsp) + .value("CDE_VCX1_vec", LIEF::assembly::arm::OPCODE::CDE_VCX1_vec) + .value("CDE_VCX2A_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX2A_fpdp) + .value("CDE_VCX2A_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX2A_fpsp) + .value("CDE_VCX2A_vec", LIEF::assembly::arm::OPCODE::CDE_VCX2A_vec) + .value("CDE_VCX2_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX2_fpdp) + .value("CDE_VCX2_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX2_fpsp) + .value("CDE_VCX2_vec", LIEF::assembly::arm::OPCODE::CDE_VCX2_vec) + .value("CDE_VCX3A_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX3A_fpdp) + .value("CDE_VCX3A_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX3A_fpsp) + .value("CDE_VCX3A_vec", LIEF::assembly::arm::OPCODE::CDE_VCX3A_vec) + .value("CDE_VCX3_fpdp", LIEF::assembly::arm::OPCODE::CDE_VCX3_fpdp) + .value("CDE_VCX3_fpsp", LIEF::assembly::arm::OPCODE::CDE_VCX3_fpsp) + .value("CDE_VCX3_vec", LIEF::assembly::arm::OPCODE::CDE_VCX3_vec) + .value("CDP", LIEF::assembly::arm::OPCODE::CDP) + .value("CDP2", LIEF::assembly::arm::OPCODE::CDP2) + .value("CLREX", LIEF::assembly::arm::OPCODE::CLREX) + .value("CLZ", LIEF::assembly::arm::OPCODE::CLZ) + .value("CMNri", LIEF::assembly::arm::OPCODE::CMNri) + .value("CMNzrr", LIEF::assembly::arm::OPCODE::CMNzrr) + .value("CMNzrsi", LIEF::assembly::arm::OPCODE::CMNzrsi) + .value("CMNzrsr", LIEF::assembly::arm::OPCODE::CMNzrsr) + .value("CMPri", LIEF::assembly::arm::OPCODE::CMPri) + .value("CMPrr", LIEF::assembly::arm::OPCODE::CMPrr) + .value("CMPrsi", LIEF::assembly::arm::OPCODE::CMPrsi) + .value("CMPrsr", LIEF::assembly::arm::OPCODE::CMPrsr) + .value("CPS1p", LIEF::assembly::arm::OPCODE::CPS1p) + .value("CPS2p", LIEF::assembly::arm::OPCODE::CPS2p) + .value("CPS3p", LIEF::assembly::arm::OPCODE::CPS3p) + .value("CRC32B", LIEF::assembly::arm::OPCODE::CRC32B) + .value("CRC32CB", LIEF::assembly::arm::OPCODE::CRC32CB) + .value("CRC32CH", LIEF::assembly::arm::OPCODE::CRC32CH) + .value("CRC32CW", LIEF::assembly::arm::OPCODE::CRC32CW) + .value("CRC32H", LIEF::assembly::arm::OPCODE::CRC32H) + .value("CRC32W", LIEF::assembly::arm::OPCODE::CRC32W) + .value("DBG", LIEF::assembly::arm::OPCODE::DBG) + .value("DMB", LIEF::assembly::arm::OPCODE::DMB) + .value("DSB", LIEF::assembly::arm::OPCODE::DSB) + .value("EORri", LIEF::assembly::arm::OPCODE::EORri) + .value("EORrr", LIEF::assembly::arm::OPCODE::EORrr) + .value("EORrsi", LIEF::assembly::arm::OPCODE::EORrsi) + .value("EORrsr", LIEF::assembly::arm::OPCODE::EORrsr); + opcodes.value("ERET", LIEF::assembly::arm::OPCODE::ERET) + .value("FCONSTD", LIEF::assembly::arm::OPCODE::FCONSTD) + .value("FCONSTH", LIEF::assembly::arm::OPCODE::FCONSTH) + .value("FCONSTS", LIEF::assembly::arm::OPCODE::FCONSTS) + .value("FLDMXDB_UPD", LIEF::assembly::arm::OPCODE::FLDMXDB_UPD) + .value("FLDMXIA", LIEF::assembly::arm::OPCODE::FLDMXIA) + .value("FLDMXIA_UPD", LIEF::assembly::arm::OPCODE::FLDMXIA_UPD) + .value("FMSTAT", LIEF::assembly::arm::OPCODE::FMSTAT) + .value("FSTMXDB_UPD", LIEF::assembly::arm::OPCODE::FSTMXDB_UPD) + .value("FSTMXIA", LIEF::assembly::arm::OPCODE::FSTMXIA) + .value("FSTMXIA_UPD", LIEF::assembly::arm::OPCODE::FSTMXIA_UPD) + .value("HINT", LIEF::assembly::arm::OPCODE::HINT) + .value("HLT", LIEF::assembly::arm::OPCODE::HLT) + .value("HVC", LIEF::assembly::arm::OPCODE::HVC) + .value("ISB", LIEF::assembly::arm::OPCODE::ISB) + .value("LDA", LIEF::assembly::arm::OPCODE::LDA) + .value("LDAB", LIEF::assembly::arm::OPCODE::LDAB) + .value("LDAEX", LIEF::assembly::arm::OPCODE::LDAEX) + .value("LDAEXB", LIEF::assembly::arm::OPCODE::LDAEXB) + .value("LDAEXD", LIEF::assembly::arm::OPCODE::LDAEXD) + .value("LDAEXH", LIEF::assembly::arm::OPCODE::LDAEXH) + .value("LDAH", LIEF::assembly::arm::OPCODE::LDAH) + .value("LDC2L_OFFSET", LIEF::assembly::arm::OPCODE::LDC2L_OFFSET) + .value("LDC2L_OPTION", LIEF::assembly::arm::OPCODE::LDC2L_OPTION) + .value("LDC2L_POST", LIEF::assembly::arm::OPCODE::LDC2L_POST) + .value("LDC2L_PRE", LIEF::assembly::arm::OPCODE::LDC2L_PRE) + .value("LDC2_OFFSET", LIEF::assembly::arm::OPCODE::LDC2_OFFSET) + .value("LDC2_OPTION", LIEF::assembly::arm::OPCODE::LDC2_OPTION) + .value("LDC2_POST", LIEF::assembly::arm::OPCODE::LDC2_POST) + .value("LDC2_PRE", LIEF::assembly::arm::OPCODE::LDC2_PRE) + .value("LDCL_OFFSET", LIEF::assembly::arm::OPCODE::LDCL_OFFSET) + .value("LDCL_OPTION", LIEF::assembly::arm::OPCODE::LDCL_OPTION) + .value("LDCL_POST", LIEF::assembly::arm::OPCODE::LDCL_POST) + .value("LDCL_PRE", LIEF::assembly::arm::OPCODE::LDCL_PRE) + .value("LDC_OFFSET", LIEF::assembly::arm::OPCODE::LDC_OFFSET) + .value("LDC_OPTION", LIEF::assembly::arm::OPCODE::LDC_OPTION) + .value("LDC_POST", LIEF::assembly::arm::OPCODE::LDC_POST) + .value("LDC_PRE", LIEF::assembly::arm::OPCODE::LDC_PRE) + .value("LDMDA", LIEF::assembly::arm::OPCODE::LDMDA) + .value("LDMDA_UPD", LIEF::assembly::arm::OPCODE::LDMDA_UPD) + .value("LDMDB", LIEF::assembly::arm::OPCODE::LDMDB) + .value("LDMDB_UPD", LIEF::assembly::arm::OPCODE::LDMDB_UPD) + .value("LDMIA", LIEF::assembly::arm::OPCODE::LDMIA) + .value("LDMIA_UPD", LIEF::assembly::arm::OPCODE::LDMIA_UPD) + .value("LDMIB", LIEF::assembly::arm::OPCODE::LDMIB) + .value("LDMIB_UPD", LIEF::assembly::arm::OPCODE::LDMIB_UPD) + .value("LDRBT_POST_IMM", LIEF::assembly::arm::OPCODE::LDRBT_POST_IMM) + .value("LDRBT_POST_REG", LIEF::assembly::arm::OPCODE::LDRBT_POST_REG) + .value("LDRB_POST_IMM", LIEF::assembly::arm::OPCODE::LDRB_POST_IMM) + .value("LDRB_POST_REG", LIEF::assembly::arm::OPCODE::LDRB_POST_REG) + .value("LDRB_PRE_IMM", LIEF::assembly::arm::OPCODE::LDRB_PRE_IMM) + .value("LDRB_PRE_REG", LIEF::assembly::arm::OPCODE::LDRB_PRE_REG) + .value("LDRBi12", LIEF::assembly::arm::OPCODE::LDRBi12) + .value("LDRBrs", LIEF::assembly::arm::OPCODE::LDRBrs) + .value("LDRD", LIEF::assembly::arm::OPCODE::LDRD) + .value("LDRD_POST", LIEF::assembly::arm::OPCODE::LDRD_POST) + .value("LDRD_PRE", LIEF::assembly::arm::OPCODE::LDRD_PRE) + .value("LDREX", LIEF::assembly::arm::OPCODE::LDREX) + .value("LDREXB", LIEF::assembly::arm::OPCODE::LDREXB) + .value("LDREXD", LIEF::assembly::arm::OPCODE::LDREXD) + .value("LDREXH", LIEF::assembly::arm::OPCODE::LDREXH) + .value("LDRH", LIEF::assembly::arm::OPCODE::LDRH) + .value("LDRHTi", LIEF::assembly::arm::OPCODE::LDRHTi) + .value("LDRHTr", LIEF::assembly::arm::OPCODE::LDRHTr) + .value("LDRH_POST", LIEF::assembly::arm::OPCODE::LDRH_POST) + .value("LDRH_PRE", LIEF::assembly::arm::OPCODE::LDRH_PRE) + .value("LDRSB", LIEF::assembly::arm::OPCODE::LDRSB) + .value("LDRSBTi", LIEF::assembly::arm::OPCODE::LDRSBTi) + .value("LDRSBTr", LIEF::assembly::arm::OPCODE::LDRSBTr) + .value("LDRSB_POST", LIEF::assembly::arm::OPCODE::LDRSB_POST) + .value("LDRSB_PRE", LIEF::assembly::arm::OPCODE::LDRSB_PRE) + .value("LDRSH", LIEF::assembly::arm::OPCODE::LDRSH) + .value("LDRSHTi", LIEF::assembly::arm::OPCODE::LDRSHTi) + .value("LDRSHTr", LIEF::assembly::arm::OPCODE::LDRSHTr) + .value("LDRSH_POST", LIEF::assembly::arm::OPCODE::LDRSH_POST) + .value("LDRSH_PRE", LIEF::assembly::arm::OPCODE::LDRSH_PRE) + .value("LDRT_POST_IMM", LIEF::assembly::arm::OPCODE::LDRT_POST_IMM) + .value("LDRT_POST_REG", LIEF::assembly::arm::OPCODE::LDRT_POST_REG) + .value("LDR_POST_IMM", LIEF::assembly::arm::OPCODE::LDR_POST_IMM) + .value("LDR_POST_REG", LIEF::assembly::arm::OPCODE::LDR_POST_REG) + .value("LDR_PRE_IMM", LIEF::assembly::arm::OPCODE::LDR_PRE_IMM) + .value("LDR_PRE_REG", LIEF::assembly::arm::OPCODE::LDR_PRE_REG) + .value("LDRcp", LIEF::assembly::arm::OPCODE::LDRcp) + .value("LDRi12", LIEF::assembly::arm::OPCODE::LDRi12) + .value("LDRrs", LIEF::assembly::arm::OPCODE::LDRrs) + .value("MCR", LIEF::assembly::arm::OPCODE::MCR) + .value("MCR2", LIEF::assembly::arm::OPCODE::MCR2) + .value("MCRR", LIEF::assembly::arm::OPCODE::MCRR) + .value("MCRR2", LIEF::assembly::arm::OPCODE::MCRR2) + .value("MLA", LIEF::assembly::arm::OPCODE::MLA) + .value("MLS", LIEF::assembly::arm::OPCODE::MLS) + .value("MOVPCLR", LIEF::assembly::arm::OPCODE::MOVPCLR) + .value("MOVTi16", LIEF::assembly::arm::OPCODE::MOVTi16) + .value("MOVi", LIEF::assembly::arm::OPCODE::MOVi) + .value("MOVi16", LIEF::assembly::arm::OPCODE::MOVi16) + .value("MOVr", LIEF::assembly::arm::OPCODE::MOVr) + .value("MOVr_TC", LIEF::assembly::arm::OPCODE::MOVr_TC) + .value("MOVsi", LIEF::assembly::arm::OPCODE::MOVsi) + .value("MOVsr", LIEF::assembly::arm::OPCODE::MOVsr) + .value("MRC", LIEF::assembly::arm::OPCODE::MRC) + .value("MRC2", LIEF::assembly::arm::OPCODE::MRC2) + .value("MRRC", LIEF::assembly::arm::OPCODE::MRRC) + .value("MRRC2", LIEF::assembly::arm::OPCODE::MRRC2) + .value("MRS", LIEF::assembly::arm::OPCODE::MRS) + .value("MRSbanked", LIEF::assembly::arm::OPCODE::MRSbanked) + .value("MRSsys", LIEF::assembly::arm::OPCODE::MRSsys) + .value("MSR", LIEF::assembly::arm::OPCODE::MSR) + .value("MSRbanked", LIEF::assembly::arm::OPCODE::MSRbanked) + .value("MSRi", LIEF::assembly::arm::OPCODE::MSRi) + .value("MUL", LIEF::assembly::arm::OPCODE::MUL) + .value("MVE_ASRLi", LIEF::assembly::arm::OPCODE::MVE_ASRLi) + .value("MVE_ASRLr", LIEF::assembly::arm::OPCODE::MVE_ASRLr) + .value("MVE_DLSTP_16", LIEF::assembly::arm::OPCODE::MVE_DLSTP_16) + .value("MVE_DLSTP_32", LIEF::assembly::arm::OPCODE::MVE_DLSTP_32) + .value("MVE_DLSTP_64", LIEF::assembly::arm::OPCODE::MVE_DLSTP_64) + .value("MVE_DLSTP_8", LIEF::assembly::arm::OPCODE::MVE_DLSTP_8) + .value("MVE_LCTP", LIEF::assembly::arm::OPCODE::MVE_LCTP) + .value("MVE_LETP", LIEF::assembly::arm::OPCODE::MVE_LETP) + .value("MVE_LSLLi", LIEF::assembly::arm::OPCODE::MVE_LSLLi) + .value("MVE_LSLLr", LIEF::assembly::arm::OPCODE::MVE_LSLLr) + .value("MVE_LSRL", LIEF::assembly::arm::OPCODE::MVE_LSRL) + .value("MVE_SQRSHR", LIEF::assembly::arm::OPCODE::MVE_SQRSHR) + .value("MVE_SQRSHRL", LIEF::assembly::arm::OPCODE::MVE_SQRSHRL) + .value("MVE_SQSHL", LIEF::assembly::arm::OPCODE::MVE_SQSHL) + .value("MVE_SQSHLL", LIEF::assembly::arm::OPCODE::MVE_SQSHLL) + .value("MVE_SRSHR", LIEF::assembly::arm::OPCODE::MVE_SRSHR) + .value("MVE_SRSHRL", LIEF::assembly::arm::OPCODE::MVE_SRSHRL) + .value("MVE_UQRSHL", LIEF::assembly::arm::OPCODE::MVE_UQRSHL) + .value("MVE_UQRSHLL", LIEF::assembly::arm::OPCODE::MVE_UQRSHLL) + .value("MVE_UQSHL", LIEF::assembly::arm::OPCODE::MVE_UQSHL) + .value("MVE_UQSHLL", LIEF::assembly::arm::OPCODE::MVE_UQSHLL) + .value("MVE_URSHR", LIEF::assembly::arm::OPCODE::MVE_URSHR) + .value("MVE_URSHRL", LIEF::assembly::arm::OPCODE::MVE_URSHRL) + .value("MVE_VABAVs16", LIEF::assembly::arm::OPCODE::MVE_VABAVs16) + .value("MVE_VABAVs32", LIEF::assembly::arm::OPCODE::MVE_VABAVs32) + .value("MVE_VABAVs8", LIEF::assembly::arm::OPCODE::MVE_VABAVs8) + .value("MVE_VABAVu16", LIEF::assembly::arm::OPCODE::MVE_VABAVu16) + .value("MVE_VABAVu32", LIEF::assembly::arm::OPCODE::MVE_VABAVu32) + .value("MVE_VABAVu8", LIEF::assembly::arm::OPCODE::MVE_VABAVu8) + .value("MVE_VABDf16", LIEF::assembly::arm::OPCODE::MVE_VABDf16) + .value("MVE_VABDf32", LIEF::assembly::arm::OPCODE::MVE_VABDf32) + .value("MVE_VABDs16", LIEF::assembly::arm::OPCODE::MVE_VABDs16) + .value("MVE_VABDs32", LIEF::assembly::arm::OPCODE::MVE_VABDs32) + .value("MVE_VABDs8", LIEF::assembly::arm::OPCODE::MVE_VABDs8) + .value("MVE_VABDu16", LIEF::assembly::arm::OPCODE::MVE_VABDu16) + .value("MVE_VABDu32", LIEF::assembly::arm::OPCODE::MVE_VABDu32) + .value("MVE_VABDu8", LIEF::assembly::arm::OPCODE::MVE_VABDu8) + .value("MVE_VABSf16", LIEF::assembly::arm::OPCODE::MVE_VABSf16) + .value("MVE_VABSf32", LIEF::assembly::arm::OPCODE::MVE_VABSf32) + .value("MVE_VABSs16", LIEF::assembly::arm::OPCODE::MVE_VABSs16) + .value("MVE_VABSs32", LIEF::assembly::arm::OPCODE::MVE_VABSs32) + .value("MVE_VABSs8", LIEF::assembly::arm::OPCODE::MVE_VABSs8) + .value("MVE_VADC", LIEF::assembly::arm::OPCODE::MVE_VADC) + .value("MVE_VADCI", LIEF::assembly::arm::OPCODE::MVE_VADCI) + .value("MVE_VADDLVs32acc", LIEF::assembly::arm::OPCODE::MVE_VADDLVs32acc) + .value("MVE_VADDLVs32no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDLVs32no_acc) + .value("MVE_VADDLVu32acc", LIEF::assembly::arm::OPCODE::MVE_VADDLVu32acc) + .value("MVE_VADDLVu32no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDLVu32no_acc) + .value("MVE_VADDVs16acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs16acc) + .value("MVE_VADDVs16no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs16no_acc) + .value("MVE_VADDVs32acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs32acc) + .value("MVE_VADDVs32no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs32no_acc) + .value("MVE_VADDVs8acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs8acc) + .value("MVE_VADDVs8no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVs8no_acc) + .value("MVE_VADDVu16acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu16acc) + .value("MVE_VADDVu16no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu16no_acc) + .value("MVE_VADDVu32acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu32acc) + .value("MVE_VADDVu32no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu32no_acc) + .value("MVE_VADDVu8acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu8acc) + .value("MVE_VADDVu8no_acc", LIEF::assembly::arm::OPCODE::MVE_VADDVu8no_acc) + .value("MVE_VADD_qr_f16", LIEF::assembly::arm::OPCODE::MVE_VADD_qr_f16) + .value("MVE_VADD_qr_f32", LIEF::assembly::arm::OPCODE::MVE_VADD_qr_f32) + .value("MVE_VADD_qr_i16", LIEF::assembly::arm::OPCODE::MVE_VADD_qr_i16) + .value("MVE_VADD_qr_i32", LIEF::assembly::arm::OPCODE::MVE_VADD_qr_i32) + .value("MVE_VADD_qr_i8", LIEF::assembly::arm::OPCODE::MVE_VADD_qr_i8) + .value("MVE_VADDf16", LIEF::assembly::arm::OPCODE::MVE_VADDf16) + .value("MVE_VADDf32", LIEF::assembly::arm::OPCODE::MVE_VADDf32) + .value("MVE_VADDi16", LIEF::assembly::arm::OPCODE::MVE_VADDi16) + .value("MVE_VADDi32", LIEF::assembly::arm::OPCODE::MVE_VADDi32) + .value("MVE_VADDi8", LIEF::assembly::arm::OPCODE::MVE_VADDi8) + .value("MVE_VAND", LIEF::assembly::arm::OPCODE::MVE_VAND) + .value("MVE_VBIC", LIEF::assembly::arm::OPCODE::MVE_VBIC) + .value("MVE_VBICimmi16", LIEF::assembly::arm::OPCODE::MVE_VBICimmi16) + .value("MVE_VBICimmi32", LIEF::assembly::arm::OPCODE::MVE_VBICimmi32) + .value("MVE_VBRSR16", LIEF::assembly::arm::OPCODE::MVE_VBRSR16) + .value("MVE_VBRSR32", LIEF::assembly::arm::OPCODE::MVE_VBRSR32) + .value("MVE_VBRSR8", LIEF::assembly::arm::OPCODE::MVE_VBRSR8) + .value("MVE_VCADDf16", LIEF::assembly::arm::OPCODE::MVE_VCADDf16) + .value("MVE_VCADDf32", LIEF::assembly::arm::OPCODE::MVE_VCADDf32) + .value("MVE_VCADDi16", LIEF::assembly::arm::OPCODE::MVE_VCADDi16) + .value("MVE_VCADDi32", LIEF::assembly::arm::OPCODE::MVE_VCADDi32) + .value("MVE_VCADDi8", LIEF::assembly::arm::OPCODE::MVE_VCADDi8) + .value("MVE_VCLSs16", LIEF::assembly::arm::OPCODE::MVE_VCLSs16) + .value("MVE_VCLSs32", LIEF::assembly::arm::OPCODE::MVE_VCLSs32) + .value("MVE_VCLSs8", LIEF::assembly::arm::OPCODE::MVE_VCLSs8) + .value("MVE_VCLZs16", LIEF::assembly::arm::OPCODE::MVE_VCLZs16) + .value("MVE_VCLZs32", LIEF::assembly::arm::OPCODE::MVE_VCLZs32) + .value("MVE_VCLZs8", LIEF::assembly::arm::OPCODE::MVE_VCLZs8) + .value("MVE_VCMLAf16", LIEF::assembly::arm::OPCODE::MVE_VCMLAf16) + .value("MVE_VCMLAf32", LIEF::assembly::arm::OPCODE::MVE_VCMLAf32) + .value("MVE_VCMPf16", LIEF::assembly::arm::OPCODE::MVE_VCMPf16) + .value("MVE_VCMPf16r", LIEF::assembly::arm::OPCODE::MVE_VCMPf16r) + .value("MVE_VCMPf32", LIEF::assembly::arm::OPCODE::MVE_VCMPf32) + .value("MVE_VCMPf32r", LIEF::assembly::arm::OPCODE::MVE_VCMPf32r) + .value("MVE_VCMPi16", LIEF::assembly::arm::OPCODE::MVE_VCMPi16) + .value("MVE_VCMPi16r", LIEF::assembly::arm::OPCODE::MVE_VCMPi16r) + .value("MVE_VCMPi32", LIEF::assembly::arm::OPCODE::MVE_VCMPi32) + .value("MVE_VCMPi32r", LIEF::assembly::arm::OPCODE::MVE_VCMPi32r) + .value("MVE_VCMPi8", LIEF::assembly::arm::OPCODE::MVE_VCMPi8) + .value("MVE_VCMPi8r", LIEF::assembly::arm::OPCODE::MVE_VCMPi8r) + .value("MVE_VCMPs16", LIEF::assembly::arm::OPCODE::MVE_VCMPs16) + .value("MVE_VCMPs16r", LIEF::assembly::arm::OPCODE::MVE_VCMPs16r) + .value("MVE_VCMPs32", LIEF::assembly::arm::OPCODE::MVE_VCMPs32) + .value("MVE_VCMPs32r", LIEF::assembly::arm::OPCODE::MVE_VCMPs32r) + .value("MVE_VCMPs8", LIEF::assembly::arm::OPCODE::MVE_VCMPs8) + .value("MVE_VCMPs8r", LIEF::assembly::arm::OPCODE::MVE_VCMPs8r) + .value("MVE_VCMPu16", LIEF::assembly::arm::OPCODE::MVE_VCMPu16) + .value("MVE_VCMPu16r", LIEF::assembly::arm::OPCODE::MVE_VCMPu16r) + .value("MVE_VCMPu32", LIEF::assembly::arm::OPCODE::MVE_VCMPu32) + .value("MVE_VCMPu32r", LIEF::assembly::arm::OPCODE::MVE_VCMPu32r) + .value("MVE_VCMPu8", LIEF::assembly::arm::OPCODE::MVE_VCMPu8) + .value("MVE_VCMPu8r", LIEF::assembly::arm::OPCODE::MVE_VCMPu8r) + .value("MVE_VCMULf16", LIEF::assembly::arm::OPCODE::MVE_VCMULf16) + .value("MVE_VCMULf32", LIEF::assembly::arm::OPCODE::MVE_VCMULf32) + .value("MVE_VCTP16", LIEF::assembly::arm::OPCODE::MVE_VCTP16) + .value("MVE_VCTP32", LIEF::assembly::arm::OPCODE::MVE_VCTP32) + .value("MVE_VCTP64", LIEF::assembly::arm::OPCODE::MVE_VCTP64) + .value("MVE_VCTP8", LIEF::assembly::arm::OPCODE::MVE_VCTP8) + .value("MVE_VCVTf16f32bh", LIEF::assembly::arm::OPCODE::MVE_VCVTf16f32bh) + .value("MVE_VCVTf16f32th", LIEF::assembly::arm::OPCODE::MVE_VCVTf16f32th) + .value("MVE_VCVTf16s16_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTf16s16_fix) + .value("MVE_VCVTf16s16n", LIEF::assembly::arm::OPCODE::MVE_VCVTf16s16n) + .value("MVE_VCVTf16u16_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTf16u16_fix) + .value("MVE_VCVTf16u16n", LIEF::assembly::arm::OPCODE::MVE_VCVTf16u16n) + .value("MVE_VCVTf32f16bh", LIEF::assembly::arm::OPCODE::MVE_VCVTf32f16bh) + .value("MVE_VCVTf32f16th", LIEF::assembly::arm::OPCODE::MVE_VCVTf32f16th) + .value("MVE_VCVTf32s32_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTf32s32_fix) + .value("MVE_VCVTf32s32n", LIEF::assembly::arm::OPCODE::MVE_VCVTf32s32n) + .value("MVE_VCVTf32u32_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTf32u32_fix) + .value("MVE_VCVTf32u32n", LIEF::assembly::arm::OPCODE::MVE_VCVTf32u32n) + .value("MVE_VCVTs16f16_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16_fix) + .value("MVE_VCVTs16f16a", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16a) + .value("MVE_VCVTs16f16m", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16m) + .value("MVE_VCVTs16f16n", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16n) + .value("MVE_VCVTs16f16p", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16p) + .value("MVE_VCVTs16f16z", LIEF::assembly::arm::OPCODE::MVE_VCVTs16f16z) + .value("MVE_VCVTs32f32_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32_fix) + .value("MVE_VCVTs32f32a", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32a) + .value("MVE_VCVTs32f32m", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32m) + .value("MVE_VCVTs32f32n", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32n) + .value("MVE_VCVTs32f32p", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32p) + .value("MVE_VCVTs32f32z", LIEF::assembly::arm::OPCODE::MVE_VCVTs32f32z) + .value("MVE_VCVTu16f16_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16_fix) + .value("MVE_VCVTu16f16a", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16a) + .value("MVE_VCVTu16f16m", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16m) + .value("MVE_VCVTu16f16n", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16n) + .value("MVE_VCVTu16f16p", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16p) + .value("MVE_VCVTu16f16z", LIEF::assembly::arm::OPCODE::MVE_VCVTu16f16z) + .value("MVE_VCVTu32f32_fix", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32_fix) + .value("MVE_VCVTu32f32a", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32a) + .value("MVE_VCVTu32f32m", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32m) + .value("MVE_VCVTu32f32n", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32n) + .value("MVE_VCVTu32f32p", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32p) + .value("MVE_VCVTu32f32z", LIEF::assembly::arm::OPCODE::MVE_VCVTu32f32z) + .value("MVE_VDDUPu16", LIEF::assembly::arm::OPCODE::MVE_VDDUPu16) + .value("MVE_VDDUPu32", LIEF::assembly::arm::OPCODE::MVE_VDDUPu32) + .value("MVE_VDDUPu8", LIEF::assembly::arm::OPCODE::MVE_VDDUPu8) + .value("MVE_VDUP16", LIEF::assembly::arm::OPCODE::MVE_VDUP16) + .value("MVE_VDUP32", LIEF::assembly::arm::OPCODE::MVE_VDUP32) + .value("MVE_VDUP8", LIEF::assembly::arm::OPCODE::MVE_VDUP8) + .value("MVE_VDWDUPu16", LIEF::assembly::arm::OPCODE::MVE_VDWDUPu16) + .value("MVE_VDWDUPu32", LIEF::assembly::arm::OPCODE::MVE_VDWDUPu32) + .value("MVE_VDWDUPu8", LIEF::assembly::arm::OPCODE::MVE_VDWDUPu8) + .value("MVE_VEOR", LIEF::assembly::arm::OPCODE::MVE_VEOR) + .value("MVE_VFMA_qr_Sf16", LIEF::assembly::arm::OPCODE::MVE_VFMA_qr_Sf16) + .value("MVE_VFMA_qr_Sf32", LIEF::assembly::arm::OPCODE::MVE_VFMA_qr_Sf32) + .value("MVE_VFMA_qr_f16", LIEF::assembly::arm::OPCODE::MVE_VFMA_qr_f16) + .value("MVE_VFMA_qr_f32", LIEF::assembly::arm::OPCODE::MVE_VFMA_qr_f32) + .value("MVE_VFMAf16", LIEF::assembly::arm::OPCODE::MVE_VFMAf16) + .value("MVE_VFMAf32", LIEF::assembly::arm::OPCODE::MVE_VFMAf32) + .value("MVE_VFMSf16", LIEF::assembly::arm::OPCODE::MVE_VFMSf16) + .value("MVE_VFMSf32", LIEF::assembly::arm::OPCODE::MVE_VFMSf32) + .value("MVE_VHADD_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_s16) + .value("MVE_VHADD_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_s32) + .value("MVE_VHADD_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_s8) + .value("MVE_VHADD_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u16) + .value("MVE_VHADD_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u32) + .value("MVE_VHADD_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u8) + .value("MVE_VHADDs16", LIEF::assembly::arm::OPCODE::MVE_VHADDs16) + .value("MVE_VHADDs32", LIEF::assembly::arm::OPCODE::MVE_VHADDs32) + .value("MVE_VHADDs8", LIEF::assembly::arm::OPCODE::MVE_VHADDs8) + .value("MVE_VHADDu16", LIEF::assembly::arm::OPCODE::MVE_VHADDu16) + .value("MVE_VHADDu32", LIEF::assembly::arm::OPCODE::MVE_VHADDu32) + .value("MVE_VHADDu8", LIEF::assembly::arm::OPCODE::MVE_VHADDu8) + .value("MVE_VHCADDs16", LIEF::assembly::arm::OPCODE::MVE_VHCADDs16) + .value("MVE_VHCADDs32", LIEF::assembly::arm::OPCODE::MVE_VHCADDs32) + .value("MVE_VHCADDs8", LIEF::assembly::arm::OPCODE::MVE_VHCADDs8) + .value("MVE_VHSUB_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s16) + .value("MVE_VHSUB_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s32) + .value("MVE_VHSUB_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s8); + opcodes.value("MVE_VHSUB_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u16) + .value("MVE_VHSUB_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u32) + .value("MVE_VHSUB_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u8) + .value("MVE_VHSUBs16", LIEF::assembly::arm::OPCODE::MVE_VHSUBs16) + .value("MVE_VHSUBs32", LIEF::assembly::arm::OPCODE::MVE_VHSUBs32) + .value("MVE_VHSUBs8", LIEF::assembly::arm::OPCODE::MVE_VHSUBs8) + .value("MVE_VHSUBu16", LIEF::assembly::arm::OPCODE::MVE_VHSUBu16) + .value("MVE_VHSUBu32", LIEF::assembly::arm::OPCODE::MVE_VHSUBu32) + .value("MVE_VHSUBu8", LIEF::assembly::arm::OPCODE::MVE_VHSUBu8) + .value("MVE_VIDUPu16", LIEF::assembly::arm::OPCODE::MVE_VIDUPu16) + .value("MVE_VIDUPu32", LIEF::assembly::arm::OPCODE::MVE_VIDUPu32) + .value("MVE_VIDUPu8", LIEF::assembly::arm::OPCODE::MVE_VIDUPu8) + .value("MVE_VIWDUPu16", LIEF::assembly::arm::OPCODE::MVE_VIWDUPu16) + .value("MVE_VIWDUPu32", LIEF::assembly::arm::OPCODE::MVE_VIWDUPu32) + .value("MVE_VIWDUPu8", LIEF::assembly::arm::OPCODE::MVE_VIWDUPu8) + .value("MVE_VLD20_16", LIEF::assembly::arm::OPCODE::MVE_VLD20_16) + .value("MVE_VLD20_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD20_16_wb) + .value("MVE_VLD20_32", LIEF::assembly::arm::OPCODE::MVE_VLD20_32) + .value("MVE_VLD20_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD20_32_wb) + .value("MVE_VLD20_8", LIEF::assembly::arm::OPCODE::MVE_VLD20_8) + .value("MVE_VLD20_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD20_8_wb) + .value("MVE_VLD21_16", LIEF::assembly::arm::OPCODE::MVE_VLD21_16) + .value("MVE_VLD21_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD21_16_wb) + .value("MVE_VLD21_32", LIEF::assembly::arm::OPCODE::MVE_VLD21_32) + .value("MVE_VLD21_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD21_32_wb) + .value("MVE_VLD21_8", LIEF::assembly::arm::OPCODE::MVE_VLD21_8) + .value("MVE_VLD21_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD21_8_wb) + .value("MVE_VLD40_16", LIEF::assembly::arm::OPCODE::MVE_VLD40_16) + .value("MVE_VLD40_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD40_16_wb) + .value("MVE_VLD40_32", LIEF::assembly::arm::OPCODE::MVE_VLD40_32) + .value("MVE_VLD40_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD40_32_wb) + .value("MVE_VLD40_8", LIEF::assembly::arm::OPCODE::MVE_VLD40_8) + .value("MVE_VLD40_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD40_8_wb) + .value("MVE_VLD41_16", LIEF::assembly::arm::OPCODE::MVE_VLD41_16) + .value("MVE_VLD41_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD41_16_wb) + .value("MVE_VLD41_32", LIEF::assembly::arm::OPCODE::MVE_VLD41_32) + .value("MVE_VLD41_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD41_32_wb) + .value("MVE_VLD41_8", LIEF::assembly::arm::OPCODE::MVE_VLD41_8) + .value("MVE_VLD41_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD41_8_wb) + .value("MVE_VLD42_16", LIEF::assembly::arm::OPCODE::MVE_VLD42_16) + .value("MVE_VLD42_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD42_16_wb) + .value("MVE_VLD42_32", LIEF::assembly::arm::OPCODE::MVE_VLD42_32) + .value("MVE_VLD42_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD42_32_wb) + .value("MVE_VLD42_8", LIEF::assembly::arm::OPCODE::MVE_VLD42_8) + .value("MVE_VLD42_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD42_8_wb) + .value("MVE_VLD43_16", LIEF::assembly::arm::OPCODE::MVE_VLD43_16) + .value("MVE_VLD43_16_wb", LIEF::assembly::arm::OPCODE::MVE_VLD43_16_wb) + .value("MVE_VLD43_32", LIEF::assembly::arm::OPCODE::MVE_VLD43_32) + .value("MVE_VLD43_32_wb", LIEF::assembly::arm::OPCODE::MVE_VLD43_32_wb) + .value("MVE_VLD43_8", LIEF::assembly::arm::OPCODE::MVE_VLD43_8) + .value("MVE_VLD43_8_wb", LIEF::assembly::arm::OPCODE::MVE_VLD43_8_wb) + .value("MVE_VLDRBS16", LIEF::assembly::arm::OPCODE::MVE_VLDRBS16) + .value("MVE_VLDRBS16_post", LIEF::assembly::arm::OPCODE::MVE_VLDRBS16_post) + .value("MVE_VLDRBS16_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRBS16_pre) + .value("MVE_VLDRBS16_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRBS16_rq) + .value("MVE_VLDRBS32", LIEF::assembly::arm::OPCODE::MVE_VLDRBS32) + .value("MVE_VLDRBS32_post", LIEF::assembly::arm::OPCODE::MVE_VLDRBS32_post) + .value("MVE_VLDRBS32_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRBS32_pre) + .value("MVE_VLDRBS32_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRBS32_rq) + .value("MVE_VLDRBU16", LIEF::assembly::arm::OPCODE::MVE_VLDRBU16) + .value("MVE_VLDRBU16_post", LIEF::assembly::arm::OPCODE::MVE_VLDRBU16_post) + .value("MVE_VLDRBU16_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRBU16_pre) + .value("MVE_VLDRBU16_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRBU16_rq) + .value("MVE_VLDRBU32", LIEF::assembly::arm::OPCODE::MVE_VLDRBU32) + .value("MVE_VLDRBU32_post", LIEF::assembly::arm::OPCODE::MVE_VLDRBU32_post) + .value("MVE_VLDRBU32_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRBU32_pre) + .value("MVE_VLDRBU32_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRBU32_rq) + .value("MVE_VLDRBU8", LIEF::assembly::arm::OPCODE::MVE_VLDRBU8) + .value("MVE_VLDRBU8_post", LIEF::assembly::arm::OPCODE::MVE_VLDRBU8_post) + .value("MVE_VLDRBU8_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRBU8_pre) + .value("MVE_VLDRBU8_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRBU8_rq) + .value("MVE_VLDRDU64_qi", LIEF::assembly::arm::OPCODE::MVE_VLDRDU64_qi) + .value("MVE_VLDRDU64_qi_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRDU64_qi_pre) + .value("MVE_VLDRDU64_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRDU64_rq) + .value("MVE_VLDRDU64_rq_u", LIEF::assembly::arm::OPCODE::MVE_VLDRDU64_rq_u) + .value("MVE_VLDRHS32", LIEF::assembly::arm::OPCODE::MVE_VLDRHS32) + .value("MVE_VLDRHS32_post", LIEF::assembly::arm::OPCODE::MVE_VLDRHS32_post) + .value("MVE_VLDRHS32_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRHS32_pre) + .value("MVE_VLDRHS32_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRHS32_rq) + .value("MVE_VLDRHS32_rq_u", LIEF::assembly::arm::OPCODE::MVE_VLDRHS32_rq_u) + .value("MVE_VLDRHU16", LIEF::assembly::arm::OPCODE::MVE_VLDRHU16) + .value("MVE_VLDRHU16_post", LIEF::assembly::arm::OPCODE::MVE_VLDRHU16_post) + .value("MVE_VLDRHU16_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRHU16_pre) + .value("MVE_VLDRHU16_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRHU16_rq) + .value("MVE_VLDRHU16_rq_u", LIEF::assembly::arm::OPCODE::MVE_VLDRHU16_rq_u) + .value("MVE_VLDRHU32", LIEF::assembly::arm::OPCODE::MVE_VLDRHU32) + .value("MVE_VLDRHU32_post", LIEF::assembly::arm::OPCODE::MVE_VLDRHU32_post) + .value("MVE_VLDRHU32_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRHU32_pre) + .value("MVE_VLDRHU32_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRHU32_rq) + .value("MVE_VLDRHU32_rq_u", LIEF::assembly::arm::OPCODE::MVE_VLDRHU32_rq_u) + .value("MVE_VLDRWU32", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32) + .value("MVE_VLDRWU32_post", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_post) + .value("MVE_VLDRWU32_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_pre) + .value("MVE_VLDRWU32_qi", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_qi) + .value("MVE_VLDRWU32_qi_pre", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_qi_pre) + .value("MVE_VLDRWU32_rq", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_rq) + .value("MVE_VLDRWU32_rq_u", LIEF::assembly::arm::OPCODE::MVE_VLDRWU32_rq_u) + .value("MVE_VMAXAVs16", LIEF::assembly::arm::OPCODE::MVE_VMAXAVs16) + .value("MVE_VMAXAVs32", LIEF::assembly::arm::OPCODE::MVE_VMAXAVs32) + .value("MVE_VMAXAVs8", LIEF::assembly::arm::OPCODE::MVE_VMAXAVs8) + .value("MVE_VMAXAs16", LIEF::assembly::arm::OPCODE::MVE_VMAXAs16) + .value("MVE_VMAXAs32", LIEF::assembly::arm::OPCODE::MVE_VMAXAs32) + .value("MVE_VMAXAs8", LIEF::assembly::arm::OPCODE::MVE_VMAXAs8) + .value("MVE_VMAXNMAVf16", LIEF::assembly::arm::OPCODE::MVE_VMAXNMAVf16) + .value("MVE_VMAXNMAVf32", LIEF::assembly::arm::OPCODE::MVE_VMAXNMAVf32) + .value("MVE_VMAXNMAf16", LIEF::assembly::arm::OPCODE::MVE_VMAXNMAf16) + .value("MVE_VMAXNMAf32", LIEF::assembly::arm::OPCODE::MVE_VMAXNMAf32) + .value("MVE_VMAXNMVf16", LIEF::assembly::arm::OPCODE::MVE_VMAXNMVf16) + .value("MVE_VMAXNMVf32", LIEF::assembly::arm::OPCODE::MVE_VMAXNMVf32) + .value("MVE_VMAXNMf16", LIEF::assembly::arm::OPCODE::MVE_VMAXNMf16) + .value("MVE_VMAXNMf32", LIEF::assembly::arm::OPCODE::MVE_VMAXNMf32) + .value("MVE_VMAXVs16", LIEF::assembly::arm::OPCODE::MVE_VMAXVs16) + .value("MVE_VMAXVs32", LIEF::assembly::arm::OPCODE::MVE_VMAXVs32) + .value("MVE_VMAXVs8", LIEF::assembly::arm::OPCODE::MVE_VMAXVs8) + .value("MVE_VMAXVu16", LIEF::assembly::arm::OPCODE::MVE_VMAXVu16) + .value("MVE_VMAXVu32", LIEF::assembly::arm::OPCODE::MVE_VMAXVu32) + .value("MVE_VMAXVu8", LIEF::assembly::arm::OPCODE::MVE_VMAXVu8) + .value("MVE_VMAXs16", LIEF::assembly::arm::OPCODE::MVE_VMAXs16) + .value("MVE_VMAXs32", LIEF::assembly::arm::OPCODE::MVE_VMAXs32) + .value("MVE_VMAXs8", LIEF::assembly::arm::OPCODE::MVE_VMAXs8) + .value("MVE_VMAXu16", LIEF::assembly::arm::OPCODE::MVE_VMAXu16) + .value("MVE_VMAXu32", LIEF::assembly::arm::OPCODE::MVE_VMAXu32) + .value("MVE_VMAXu8", LIEF::assembly::arm::OPCODE::MVE_VMAXu8) + .value("MVE_VMINAVs16", LIEF::assembly::arm::OPCODE::MVE_VMINAVs16) + .value("MVE_VMINAVs32", LIEF::assembly::arm::OPCODE::MVE_VMINAVs32) + .value("MVE_VMINAVs8", LIEF::assembly::arm::OPCODE::MVE_VMINAVs8) + .value("MVE_VMINAs16", LIEF::assembly::arm::OPCODE::MVE_VMINAs16) + .value("MVE_VMINAs32", LIEF::assembly::arm::OPCODE::MVE_VMINAs32) + .value("MVE_VMINAs8", LIEF::assembly::arm::OPCODE::MVE_VMINAs8) + .value("MVE_VMINNMAVf16", LIEF::assembly::arm::OPCODE::MVE_VMINNMAVf16) + .value("MVE_VMINNMAVf32", LIEF::assembly::arm::OPCODE::MVE_VMINNMAVf32) + .value("MVE_VMINNMAf16", LIEF::assembly::arm::OPCODE::MVE_VMINNMAf16) + .value("MVE_VMINNMAf32", LIEF::assembly::arm::OPCODE::MVE_VMINNMAf32) + .value("MVE_VMINNMVf16", LIEF::assembly::arm::OPCODE::MVE_VMINNMVf16) + .value("MVE_VMINNMVf32", LIEF::assembly::arm::OPCODE::MVE_VMINNMVf32) + .value("MVE_VMINNMf16", LIEF::assembly::arm::OPCODE::MVE_VMINNMf16) + .value("MVE_VMINNMf32", LIEF::assembly::arm::OPCODE::MVE_VMINNMf32) + .value("MVE_VMINVs16", LIEF::assembly::arm::OPCODE::MVE_VMINVs16) + .value("MVE_VMINVs32", LIEF::assembly::arm::OPCODE::MVE_VMINVs32) + .value("MVE_VMINVs8", LIEF::assembly::arm::OPCODE::MVE_VMINVs8) + .value("MVE_VMINVu16", LIEF::assembly::arm::OPCODE::MVE_VMINVu16) + .value("MVE_VMINVu32", LIEF::assembly::arm::OPCODE::MVE_VMINVu32) + .value("MVE_VMINVu8", LIEF::assembly::arm::OPCODE::MVE_VMINVu8) + .value("MVE_VMINs16", LIEF::assembly::arm::OPCODE::MVE_VMINs16) + .value("MVE_VMINs32", LIEF::assembly::arm::OPCODE::MVE_VMINs32) + .value("MVE_VMINs8", LIEF::assembly::arm::OPCODE::MVE_VMINs8) + .value("MVE_VMINu16", LIEF::assembly::arm::OPCODE::MVE_VMINu16) + .value("MVE_VMINu32", LIEF::assembly::arm::OPCODE::MVE_VMINu32) + .value("MVE_VMINu8", LIEF::assembly::arm::OPCODE::MVE_VMINu8) + .value("MVE_VMLADAVas16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVas16) + .value("MVE_VMLADAVas32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVas32) + .value("MVE_VMLADAVas8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVas8) + .value("MVE_VMLADAVau16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVau16) + .value("MVE_VMLADAVau32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVau32) + .value("MVE_VMLADAVau8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVau8) + .value("MVE_VMLADAVaxs16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVaxs16) + .value("MVE_VMLADAVaxs32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVaxs32) + .value("MVE_VMLADAVaxs8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVaxs8) + .value("MVE_VMLADAVs16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVs16) + .value("MVE_VMLADAVs32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVs32) + .value("MVE_VMLADAVs8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVs8) + .value("MVE_VMLADAVu16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVu16) + .value("MVE_VMLADAVu32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVu32) + .value("MVE_VMLADAVu8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVu8) + .value("MVE_VMLADAVxs16", LIEF::assembly::arm::OPCODE::MVE_VMLADAVxs16) + .value("MVE_VMLADAVxs32", LIEF::assembly::arm::OPCODE::MVE_VMLADAVxs32) + .value("MVE_VMLADAVxs8", LIEF::assembly::arm::OPCODE::MVE_VMLADAVxs8) + .value("MVE_VMLALDAVas16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVas16) + .value("MVE_VMLALDAVas32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVas32) + .value("MVE_VMLALDAVau16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVau16) + .value("MVE_VMLALDAVau32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVau32) + .value("MVE_VMLALDAVaxs16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVaxs16) + .value("MVE_VMLALDAVaxs32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVaxs32) + .value("MVE_VMLALDAVs16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVs16) + .value("MVE_VMLALDAVs32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVs32) + .value("MVE_VMLALDAVu16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVu16) + .value("MVE_VMLALDAVu32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVu32) + .value("MVE_VMLALDAVxs16", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVxs16) + .value("MVE_VMLALDAVxs32", LIEF::assembly::arm::OPCODE::MVE_VMLALDAVxs32) + .value("MVE_VMLAS_qr_i16", LIEF::assembly::arm::OPCODE::MVE_VMLAS_qr_i16) + .value("MVE_VMLAS_qr_i32", LIEF::assembly::arm::OPCODE::MVE_VMLAS_qr_i32) + .value("MVE_VMLAS_qr_i8", LIEF::assembly::arm::OPCODE::MVE_VMLAS_qr_i8) + .value("MVE_VMLA_qr_i16", LIEF::assembly::arm::OPCODE::MVE_VMLA_qr_i16) + .value("MVE_VMLA_qr_i32", LIEF::assembly::arm::OPCODE::MVE_VMLA_qr_i32) + .value("MVE_VMLA_qr_i8", LIEF::assembly::arm::OPCODE::MVE_VMLA_qr_i8) + .value("MVE_VMLSDAVas16", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVas16) + .value("MVE_VMLSDAVas32", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVas32) + .value("MVE_VMLSDAVas8", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVas8) + .value("MVE_VMLSDAVaxs16", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVaxs16) + .value("MVE_VMLSDAVaxs32", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVaxs32) + .value("MVE_VMLSDAVaxs8", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVaxs8) + .value("MVE_VMLSDAVs16", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVs16) + .value("MVE_VMLSDAVs32", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVs32) + .value("MVE_VMLSDAVs8", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVs8) + .value("MVE_VMLSDAVxs16", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVxs16) + .value("MVE_VMLSDAVxs32", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVxs32) + .value("MVE_VMLSDAVxs8", LIEF::assembly::arm::OPCODE::MVE_VMLSDAVxs8) + .value("MVE_VMLSLDAVas16", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVas16) + .value("MVE_VMLSLDAVas32", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVas32) + .value("MVE_VMLSLDAVaxs16", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVaxs16) + .value("MVE_VMLSLDAVaxs32", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVaxs32) + .value("MVE_VMLSLDAVs16", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVs16) + .value("MVE_VMLSLDAVs32", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVs32) + .value("MVE_VMLSLDAVxs16", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVxs16) + .value("MVE_VMLSLDAVxs32", LIEF::assembly::arm::OPCODE::MVE_VMLSLDAVxs32) + .value("MVE_VMOVLs16bh", LIEF::assembly::arm::OPCODE::MVE_VMOVLs16bh) + .value("MVE_VMOVLs16th", LIEF::assembly::arm::OPCODE::MVE_VMOVLs16th) + .value("MVE_VMOVLs8bh", LIEF::assembly::arm::OPCODE::MVE_VMOVLs8bh) + .value("MVE_VMOVLs8th", LIEF::assembly::arm::OPCODE::MVE_VMOVLs8th) + .value("MVE_VMOVLu16bh", LIEF::assembly::arm::OPCODE::MVE_VMOVLu16bh) + .value("MVE_VMOVLu16th", LIEF::assembly::arm::OPCODE::MVE_VMOVLu16th) + .value("MVE_VMOVLu8bh", LIEF::assembly::arm::OPCODE::MVE_VMOVLu8bh) + .value("MVE_VMOVLu8th", LIEF::assembly::arm::OPCODE::MVE_VMOVLu8th) + .value("MVE_VMOVNi16bh", LIEF::assembly::arm::OPCODE::MVE_VMOVNi16bh) + .value("MVE_VMOVNi16th", LIEF::assembly::arm::OPCODE::MVE_VMOVNi16th) + .value("MVE_VMOVNi32bh", LIEF::assembly::arm::OPCODE::MVE_VMOVNi32bh) + .value("MVE_VMOVNi32th", LIEF::assembly::arm::OPCODE::MVE_VMOVNi32th) + .value("MVE_VMOV_from_lane_32", LIEF::assembly::arm::OPCODE::MVE_VMOV_from_lane_32) + .value("MVE_VMOV_from_lane_s16", LIEF::assembly::arm::OPCODE::MVE_VMOV_from_lane_s16) + .value("MVE_VMOV_from_lane_s8", LIEF::assembly::arm::OPCODE::MVE_VMOV_from_lane_s8) + .value("MVE_VMOV_from_lane_u16", LIEF::assembly::arm::OPCODE::MVE_VMOV_from_lane_u16) + .value("MVE_VMOV_from_lane_u8", LIEF::assembly::arm::OPCODE::MVE_VMOV_from_lane_u8) + .value("MVE_VMOV_q_rr", LIEF::assembly::arm::OPCODE::MVE_VMOV_q_rr) + .value("MVE_VMOV_rr_q", LIEF::assembly::arm::OPCODE::MVE_VMOV_rr_q) + .value("MVE_VMOV_to_lane_16", LIEF::assembly::arm::OPCODE::MVE_VMOV_to_lane_16) + .value("MVE_VMOV_to_lane_32", LIEF::assembly::arm::OPCODE::MVE_VMOV_to_lane_32) + .value("MVE_VMOV_to_lane_8", LIEF::assembly::arm::OPCODE::MVE_VMOV_to_lane_8) + .value("MVE_VMOVimmf32", LIEF::assembly::arm::OPCODE::MVE_VMOVimmf32) + .value("MVE_VMOVimmi16", LIEF::assembly::arm::OPCODE::MVE_VMOVimmi16) + .value("MVE_VMOVimmi32", LIEF::assembly::arm::OPCODE::MVE_VMOVimmi32) + .value("MVE_VMOVimmi64", LIEF::assembly::arm::OPCODE::MVE_VMOVimmi64) + .value("MVE_VMOVimmi8", LIEF::assembly::arm::OPCODE::MVE_VMOVimmi8) + .value("MVE_VMULHs16", LIEF::assembly::arm::OPCODE::MVE_VMULHs16) + .value("MVE_VMULHs32", LIEF::assembly::arm::OPCODE::MVE_VMULHs32) + .value("MVE_VMULHs8", LIEF::assembly::arm::OPCODE::MVE_VMULHs8) + .value("MVE_VMULHu16", LIEF::assembly::arm::OPCODE::MVE_VMULHu16) + .value("MVE_VMULHu32", LIEF::assembly::arm::OPCODE::MVE_VMULHu32) + .value("MVE_VMULHu8", LIEF::assembly::arm::OPCODE::MVE_VMULHu8) + .value("MVE_VMULLBp16", LIEF::assembly::arm::OPCODE::MVE_VMULLBp16) + .value("MVE_VMULLBp8", LIEF::assembly::arm::OPCODE::MVE_VMULLBp8) + .value("MVE_VMULLBs16", LIEF::assembly::arm::OPCODE::MVE_VMULLBs16) + .value("MVE_VMULLBs32", LIEF::assembly::arm::OPCODE::MVE_VMULLBs32) + .value("MVE_VMULLBs8", LIEF::assembly::arm::OPCODE::MVE_VMULLBs8) + .value("MVE_VMULLBu16", LIEF::assembly::arm::OPCODE::MVE_VMULLBu16) + .value("MVE_VMULLBu32", LIEF::assembly::arm::OPCODE::MVE_VMULLBu32) + .value("MVE_VMULLBu8", LIEF::assembly::arm::OPCODE::MVE_VMULLBu8) + .value("MVE_VMULLTp16", LIEF::assembly::arm::OPCODE::MVE_VMULLTp16) + .value("MVE_VMULLTp8", LIEF::assembly::arm::OPCODE::MVE_VMULLTp8) + .value("MVE_VMULLTs16", LIEF::assembly::arm::OPCODE::MVE_VMULLTs16) + .value("MVE_VMULLTs32", LIEF::assembly::arm::OPCODE::MVE_VMULLTs32) + .value("MVE_VMULLTs8", LIEF::assembly::arm::OPCODE::MVE_VMULLTs8) + .value("MVE_VMULLTu16", LIEF::assembly::arm::OPCODE::MVE_VMULLTu16) + .value("MVE_VMULLTu32", LIEF::assembly::arm::OPCODE::MVE_VMULLTu32) + .value("MVE_VMULLTu8", LIEF::assembly::arm::OPCODE::MVE_VMULLTu8) + .value("MVE_VMUL_qr_f16", LIEF::assembly::arm::OPCODE::MVE_VMUL_qr_f16) + .value("MVE_VMUL_qr_f32", LIEF::assembly::arm::OPCODE::MVE_VMUL_qr_f32) + .value("MVE_VMUL_qr_i16", LIEF::assembly::arm::OPCODE::MVE_VMUL_qr_i16) + .value("MVE_VMUL_qr_i32", LIEF::assembly::arm::OPCODE::MVE_VMUL_qr_i32) + .value("MVE_VMUL_qr_i8", LIEF::assembly::arm::OPCODE::MVE_VMUL_qr_i8) + .value("MVE_VMULf16", LIEF::assembly::arm::OPCODE::MVE_VMULf16) + .value("MVE_VMULf32", LIEF::assembly::arm::OPCODE::MVE_VMULf32) + .value("MVE_VMULi16", LIEF::assembly::arm::OPCODE::MVE_VMULi16) + .value("MVE_VMULi32", LIEF::assembly::arm::OPCODE::MVE_VMULi32) + .value("MVE_VMULi8", LIEF::assembly::arm::OPCODE::MVE_VMULi8) + .value("MVE_VMVN", LIEF::assembly::arm::OPCODE::MVE_VMVN) + .value("MVE_VMVNimmi16", LIEF::assembly::arm::OPCODE::MVE_VMVNimmi16) + .value("MVE_VMVNimmi32", LIEF::assembly::arm::OPCODE::MVE_VMVNimmi32) + .value("MVE_VNEGf16", LIEF::assembly::arm::OPCODE::MVE_VNEGf16) + .value("MVE_VNEGf32", LIEF::assembly::arm::OPCODE::MVE_VNEGf32) + .value("MVE_VNEGs16", LIEF::assembly::arm::OPCODE::MVE_VNEGs16) + .value("MVE_VNEGs32", LIEF::assembly::arm::OPCODE::MVE_VNEGs32) + .value("MVE_VNEGs8", LIEF::assembly::arm::OPCODE::MVE_VNEGs8) + .value("MVE_VORN", LIEF::assembly::arm::OPCODE::MVE_VORN) + .value("MVE_VORR", LIEF::assembly::arm::OPCODE::MVE_VORR) + .value("MVE_VORRimmi16", LIEF::assembly::arm::OPCODE::MVE_VORRimmi16) + .value("MVE_VORRimmi32", LIEF::assembly::arm::OPCODE::MVE_VORRimmi32) + .value("MVE_VPNOT", LIEF::assembly::arm::OPCODE::MVE_VPNOT) + .value("MVE_VPSEL", LIEF::assembly::arm::OPCODE::MVE_VPSEL) + .value("MVE_VPST", LIEF::assembly::arm::OPCODE::MVE_VPST) + .value("MVE_VPTv16i8", LIEF::assembly::arm::OPCODE::MVE_VPTv16i8) + .value("MVE_VPTv16i8r", LIEF::assembly::arm::OPCODE::MVE_VPTv16i8r) + .value("MVE_VPTv16s8", LIEF::assembly::arm::OPCODE::MVE_VPTv16s8) + .value("MVE_VPTv16s8r", LIEF::assembly::arm::OPCODE::MVE_VPTv16s8r) + .value("MVE_VPTv16u8", LIEF::assembly::arm::OPCODE::MVE_VPTv16u8) + .value("MVE_VPTv16u8r", LIEF::assembly::arm::OPCODE::MVE_VPTv16u8r) + .value("MVE_VPTv4f32", LIEF::assembly::arm::OPCODE::MVE_VPTv4f32) + .value("MVE_VPTv4f32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4f32r) + .value("MVE_VPTv4i32", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32) + .value("MVE_VPTv4i32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32r) + .value("MVE_VPTv4s32", LIEF::assembly::arm::OPCODE::MVE_VPTv4s32) + .value("MVE_VPTv4s32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4s32r) + .value("MVE_VPTv4u32", LIEF::assembly::arm::OPCODE::MVE_VPTv4u32) + .value("MVE_VPTv4u32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4u32r) + .value("MVE_VPTv8f16", LIEF::assembly::arm::OPCODE::MVE_VPTv8f16) + .value("MVE_VPTv8f16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8f16r) + .value("MVE_VPTv8i16", LIEF::assembly::arm::OPCODE::MVE_VPTv8i16) + .value("MVE_VPTv8i16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8i16r) + .value("MVE_VPTv8s16", LIEF::assembly::arm::OPCODE::MVE_VPTv8s16) + .value("MVE_VPTv8s16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8s16r) + .value("MVE_VPTv8u16", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16); + opcodes.value("MVE_VPTv8u16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16r) + .value("MVE_VQABSs16", LIEF::assembly::arm::OPCODE::MVE_VQABSs16) + .value("MVE_VQABSs32", LIEF::assembly::arm::OPCODE::MVE_VQABSs32) + .value("MVE_VQABSs8", LIEF::assembly::arm::OPCODE::MVE_VQABSs8) + .value("MVE_VQADD_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_s16) + .value("MVE_VQADD_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_s32) + .value("MVE_VQADD_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_s8) + .value("MVE_VQADD_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_u16) + .value("MVE_VQADD_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_u32) + .value("MVE_VQADD_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VQADD_qr_u8) + .value("MVE_VQADDs16", LIEF::assembly::arm::OPCODE::MVE_VQADDs16) + .value("MVE_VQADDs32", LIEF::assembly::arm::OPCODE::MVE_VQADDs32) + .value("MVE_VQADDs8", LIEF::assembly::arm::OPCODE::MVE_VQADDs8) + .value("MVE_VQADDu16", LIEF::assembly::arm::OPCODE::MVE_VQADDu16) + .value("MVE_VQADDu32", LIEF::assembly::arm::OPCODE::MVE_VQADDu32) + .value("MVE_VQADDu8", LIEF::assembly::arm::OPCODE::MVE_VQADDu8) + .value("MVE_VQDMLADHXs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHXs16) + .value("MVE_VQDMLADHXs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHXs32) + .value("MVE_VQDMLADHXs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHXs8) + .value("MVE_VQDMLADHs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHs16) + .value("MVE_VQDMLADHs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHs32) + .value("MVE_VQDMLADHs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLADHs8) + .value("MVE_VQDMLAH_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLAH_qrs16) + .value("MVE_VQDMLAH_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLAH_qrs32) + .value("MVE_VQDMLAH_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLAH_qrs8) + .value("MVE_VQDMLASH_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLASH_qrs16) + .value("MVE_VQDMLASH_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLASH_qrs32) + .value("MVE_VQDMLASH_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLASH_qrs8) + .value("MVE_VQDMLSDHXs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHXs16) + .value("MVE_VQDMLSDHXs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHXs32) + .value("MVE_VQDMLSDHXs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHXs8) + .value("MVE_VQDMLSDHs16", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHs16) + .value("MVE_VQDMLSDHs32", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHs32) + .value("MVE_VQDMLSDHs8", LIEF::assembly::arm::OPCODE::MVE_VQDMLSDHs8) + .value("MVE_VQDMULH_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VQDMULH_qr_s16) + .value("MVE_VQDMULH_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VQDMULH_qr_s32) + .value("MVE_VQDMULH_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VQDMULH_qr_s8) + .value("MVE_VQDMULHi16", LIEF::assembly::arm::OPCODE::MVE_VQDMULHi16) + .value("MVE_VQDMULHi32", LIEF::assembly::arm::OPCODE::MVE_VQDMULHi32) + .value("MVE_VQDMULHi8", LIEF::assembly::arm::OPCODE::MVE_VQDMULHi8) + .value("MVE_VQDMULL_qr_s16bh", LIEF::assembly::arm::OPCODE::MVE_VQDMULL_qr_s16bh) + .value("MVE_VQDMULL_qr_s16th", LIEF::assembly::arm::OPCODE::MVE_VQDMULL_qr_s16th) + .value("MVE_VQDMULL_qr_s32bh", LIEF::assembly::arm::OPCODE::MVE_VQDMULL_qr_s32bh) + .value("MVE_VQDMULL_qr_s32th", LIEF::assembly::arm::OPCODE::MVE_VQDMULL_qr_s32th) + .value("MVE_VQDMULLs16bh", LIEF::assembly::arm::OPCODE::MVE_VQDMULLs16bh) + .value("MVE_VQDMULLs16th", LIEF::assembly::arm::OPCODE::MVE_VQDMULLs16th) + .value("MVE_VQDMULLs32bh", LIEF::assembly::arm::OPCODE::MVE_VQDMULLs32bh) + .value("MVE_VQDMULLs32th", LIEF::assembly::arm::OPCODE::MVE_VQDMULLs32th) + .value("MVE_VQMOVNs16bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVNs16bh) + .value("MVE_VQMOVNs16th", LIEF::assembly::arm::OPCODE::MVE_VQMOVNs16th) + .value("MVE_VQMOVNs32bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVNs32bh) + .value("MVE_VQMOVNs32th", LIEF::assembly::arm::OPCODE::MVE_VQMOVNs32th) + .value("MVE_VQMOVNu16bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVNu16bh) + .value("MVE_VQMOVNu16th", LIEF::assembly::arm::OPCODE::MVE_VQMOVNu16th) + .value("MVE_VQMOVNu32bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVNu32bh) + .value("MVE_VQMOVNu32th", LIEF::assembly::arm::OPCODE::MVE_VQMOVNu32th) + .value("MVE_VQMOVUNs16bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVUNs16bh) + .value("MVE_VQMOVUNs16th", LIEF::assembly::arm::OPCODE::MVE_VQMOVUNs16th) + .value("MVE_VQMOVUNs32bh", LIEF::assembly::arm::OPCODE::MVE_VQMOVUNs32bh) + .value("MVE_VQMOVUNs32th", LIEF::assembly::arm::OPCODE::MVE_VQMOVUNs32th) + .value("MVE_VQNEGs16", LIEF::assembly::arm::OPCODE::MVE_VQNEGs16) + .value("MVE_VQNEGs32", LIEF::assembly::arm::OPCODE::MVE_VQNEGs32) + .value("MVE_VQNEGs8", LIEF::assembly::arm::OPCODE::MVE_VQNEGs8) + .value("MVE_VQRDMLADHXs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHXs16) + .value("MVE_VQRDMLADHXs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHXs32) + .value("MVE_VQRDMLADHXs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHXs8) + .value("MVE_VQRDMLADHs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHs16) + .value("MVE_VQRDMLADHs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHs32) + .value("MVE_VQRDMLADHs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLADHs8) + .value("MVE_VQRDMLAH_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLAH_qrs16) + .value("MVE_VQRDMLAH_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLAH_qrs32) + .value("MVE_VQRDMLAH_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLAH_qrs8) + .value("MVE_VQRDMLASH_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLASH_qrs16) + .value("MVE_VQRDMLASH_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLASH_qrs32) + .value("MVE_VQRDMLASH_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLASH_qrs8) + .value("MVE_VQRDMLSDHXs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHXs16) + .value("MVE_VQRDMLSDHXs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHXs32) + .value("MVE_VQRDMLSDHXs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHXs8) + .value("MVE_VQRDMLSDHs16", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHs16) + .value("MVE_VQRDMLSDHs32", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHs32) + .value("MVE_VQRDMLSDHs8", LIEF::assembly::arm::OPCODE::MVE_VQRDMLSDHs8) + .value("MVE_VQRDMULH_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VQRDMULH_qr_s16) + .value("MVE_VQRDMULH_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VQRDMULH_qr_s32) + .value("MVE_VQRDMULH_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VQRDMULH_qr_s8) + .value("MVE_VQRDMULHi16", LIEF::assembly::arm::OPCODE::MVE_VQRDMULHi16) + .value("MVE_VQRDMULHi32", LIEF::assembly::arm::OPCODE::MVE_VQRDMULHi32) + .value("MVE_VQRDMULHi8", LIEF::assembly::arm::OPCODE::MVE_VQRDMULHi8) + .value("MVE_VQRSHL_by_vecs16", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecs16) + .value("MVE_VQRSHL_by_vecs32", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecs32) + .value("MVE_VQRSHL_by_vecs8", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecs8) + .value("MVE_VQRSHL_by_vecu16", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecu16) + .value("MVE_VQRSHL_by_vecu32", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecu32) + .value("MVE_VQRSHL_by_vecu8", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_by_vecu8) + .value("MVE_VQRSHL_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qrs16) + .value("MVE_VQRSHL_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qrs32) + .value("MVE_VQRSHL_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qrs8) + .value("MVE_VQRSHL_qru16", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qru16) + .value("MVE_VQRSHL_qru32", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qru32) + .value("MVE_VQRSHL_qru8", LIEF::assembly::arm::OPCODE::MVE_VQRSHL_qru8) + .value("MVE_VQRSHRNbhs16", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNbhs16) + .value("MVE_VQRSHRNbhs32", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNbhs32) + .value("MVE_VQRSHRNbhu16", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNbhu16) + .value("MVE_VQRSHRNbhu32", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNbhu32) + .value("MVE_VQRSHRNths16", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNths16) + .value("MVE_VQRSHRNths32", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNths32) + .value("MVE_VQRSHRNthu16", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNthu16) + .value("MVE_VQRSHRNthu32", LIEF::assembly::arm::OPCODE::MVE_VQRSHRNthu32) + .value("MVE_VQRSHRUNs16bh", LIEF::assembly::arm::OPCODE::MVE_VQRSHRUNs16bh) + .value("MVE_VQRSHRUNs16th", LIEF::assembly::arm::OPCODE::MVE_VQRSHRUNs16th) + .value("MVE_VQRSHRUNs32bh", LIEF::assembly::arm::OPCODE::MVE_VQRSHRUNs32bh) + .value("MVE_VQRSHRUNs32th", LIEF::assembly::arm::OPCODE::MVE_VQRSHRUNs32th) + .value("MVE_VQSHLU_imms16", LIEF::assembly::arm::OPCODE::MVE_VQSHLU_imms16) + .value("MVE_VQSHLU_imms32", LIEF::assembly::arm::OPCODE::MVE_VQSHLU_imms32) + .value("MVE_VQSHLU_imms8", LIEF::assembly::arm::OPCODE::MVE_VQSHLU_imms8) + .value("MVE_VQSHL_by_vecs16", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecs16) + .value("MVE_VQSHL_by_vecs32", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecs32) + .value("MVE_VQSHL_by_vecs8", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecs8) + .value("MVE_VQSHL_by_vecu16", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecu16) + .value("MVE_VQSHL_by_vecu32", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecu32) + .value("MVE_VQSHL_by_vecu8", LIEF::assembly::arm::OPCODE::MVE_VQSHL_by_vecu8) + .value("MVE_VQSHL_qrs16", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qrs16) + .value("MVE_VQSHL_qrs32", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qrs32) + .value("MVE_VQSHL_qrs8", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qrs8) + .value("MVE_VQSHL_qru16", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qru16) + .value("MVE_VQSHL_qru32", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qru32) + .value("MVE_VQSHL_qru8", LIEF::assembly::arm::OPCODE::MVE_VQSHL_qru8) + .value("MVE_VQSHLimms16", LIEF::assembly::arm::OPCODE::MVE_VQSHLimms16) + .value("MVE_VQSHLimms32", LIEF::assembly::arm::OPCODE::MVE_VQSHLimms32) + .value("MVE_VQSHLimms8", LIEF::assembly::arm::OPCODE::MVE_VQSHLimms8) + .value("MVE_VQSHLimmu16", LIEF::assembly::arm::OPCODE::MVE_VQSHLimmu16) + .value("MVE_VQSHLimmu32", LIEF::assembly::arm::OPCODE::MVE_VQSHLimmu32) + .value("MVE_VQSHLimmu8", LIEF::assembly::arm::OPCODE::MVE_VQSHLimmu8) + .value("MVE_VQSHRNbhs16", LIEF::assembly::arm::OPCODE::MVE_VQSHRNbhs16) + .value("MVE_VQSHRNbhs32", LIEF::assembly::arm::OPCODE::MVE_VQSHRNbhs32) + .value("MVE_VQSHRNbhu16", LIEF::assembly::arm::OPCODE::MVE_VQSHRNbhu16) + .value("MVE_VQSHRNbhu32", LIEF::assembly::arm::OPCODE::MVE_VQSHRNbhu32) + .value("MVE_VQSHRNths16", LIEF::assembly::arm::OPCODE::MVE_VQSHRNths16) + .value("MVE_VQSHRNths32", LIEF::assembly::arm::OPCODE::MVE_VQSHRNths32) + .value("MVE_VQSHRNthu16", LIEF::assembly::arm::OPCODE::MVE_VQSHRNthu16) + .value("MVE_VQSHRNthu32", LIEF::assembly::arm::OPCODE::MVE_VQSHRNthu32) + .value("MVE_VQSHRUNs16bh", LIEF::assembly::arm::OPCODE::MVE_VQSHRUNs16bh) + .value("MVE_VQSHRUNs16th", LIEF::assembly::arm::OPCODE::MVE_VQSHRUNs16th) + .value("MVE_VQSHRUNs32bh", LIEF::assembly::arm::OPCODE::MVE_VQSHRUNs32bh) + .value("MVE_VQSHRUNs32th", LIEF::assembly::arm::OPCODE::MVE_VQSHRUNs32th) + .value("MVE_VQSUB_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_s16) + .value("MVE_VQSUB_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_s32) + .value("MVE_VQSUB_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_s8) + .value("MVE_VQSUB_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_u16) + .value("MVE_VQSUB_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_u32) + .value("MVE_VQSUB_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VQSUB_qr_u8) + .value("MVE_VQSUBs16", LIEF::assembly::arm::OPCODE::MVE_VQSUBs16) + .value("MVE_VQSUBs32", LIEF::assembly::arm::OPCODE::MVE_VQSUBs32) + .value("MVE_VQSUBs8", LIEF::assembly::arm::OPCODE::MVE_VQSUBs8) + .value("MVE_VQSUBu16", LIEF::assembly::arm::OPCODE::MVE_VQSUBu16) + .value("MVE_VQSUBu32", LIEF::assembly::arm::OPCODE::MVE_VQSUBu32) + .value("MVE_VQSUBu8", LIEF::assembly::arm::OPCODE::MVE_VQSUBu8) + .value("MVE_VREV16_8", LIEF::assembly::arm::OPCODE::MVE_VREV16_8) + .value("MVE_VREV32_16", LIEF::assembly::arm::OPCODE::MVE_VREV32_16) + .value("MVE_VREV32_8", LIEF::assembly::arm::OPCODE::MVE_VREV32_8) + .value("MVE_VREV64_16", LIEF::assembly::arm::OPCODE::MVE_VREV64_16) + .value("MVE_VREV64_32", LIEF::assembly::arm::OPCODE::MVE_VREV64_32) + .value("MVE_VREV64_8", LIEF::assembly::arm::OPCODE::MVE_VREV64_8) + .value("MVE_VRHADDs16", LIEF::assembly::arm::OPCODE::MVE_VRHADDs16) + .value("MVE_VRHADDs32", LIEF::assembly::arm::OPCODE::MVE_VRHADDs32) + .value("MVE_VRHADDs8", LIEF::assembly::arm::OPCODE::MVE_VRHADDs8) + .value("MVE_VRHADDu16", LIEF::assembly::arm::OPCODE::MVE_VRHADDu16) + .value("MVE_VRHADDu32", LIEF::assembly::arm::OPCODE::MVE_VRHADDu32) + .value("MVE_VRHADDu8", LIEF::assembly::arm::OPCODE::MVE_VRHADDu8) + .value("MVE_VRINTf16A", LIEF::assembly::arm::OPCODE::MVE_VRINTf16A) + .value("MVE_VRINTf16M", LIEF::assembly::arm::OPCODE::MVE_VRINTf16M) + .value("MVE_VRINTf16N", LIEF::assembly::arm::OPCODE::MVE_VRINTf16N) + .value("MVE_VRINTf16P", LIEF::assembly::arm::OPCODE::MVE_VRINTf16P) + .value("MVE_VRINTf16X", LIEF::assembly::arm::OPCODE::MVE_VRINTf16X) + .value("MVE_VRINTf16Z", LIEF::assembly::arm::OPCODE::MVE_VRINTf16Z) + .value("MVE_VRINTf32A", LIEF::assembly::arm::OPCODE::MVE_VRINTf32A) + .value("MVE_VRINTf32M", LIEF::assembly::arm::OPCODE::MVE_VRINTf32M) + .value("MVE_VRINTf32N", LIEF::assembly::arm::OPCODE::MVE_VRINTf32N) + .value("MVE_VRINTf32P", LIEF::assembly::arm::OPCODE::MVE_VRINTf32P) + .value("MVE_VRINTf32X", LIEF::assembly::arm::OPCODE::MVE_VRINTf32X) + .value("MVE_VRINTf32Z", LIEF::assembly::arm::OPCODE::MVE_VRINTf32Z) + .value("MVE_VRMLALDAVHas32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHas32) + .value("MVE_VRMLALDAVHau32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHau32) + .value("MVE_VRMLALDAVHaxs32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHaxs32) + .value("MVE_VRMLALDAVHs32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHs32) + .value("MVE_VRMLALDAVHu32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHu32) + .value("MVE_VRMLALDAVHxs32", LIEF::assembly::arm::OPCODE::MVE_VRMLALDAVHxs32) + .value("MVE_VRMLSLDAVHas32", LIEF::assembly::arm::OPCODE::MVE_VRMLSLDAVHas32) + .value("MVE_VRMLSLDAVHaxs32", LIEF::assembly::arm::OPCODE::MVE_VRMLSLDAVHaxs32) + .value("MVE_VRMLSLDAVHs32", LIEF::assembly::arm::OPCODE::MVE_VRMLSLDAVHs32) + .value("MVE_VRMLSLDAVHxs32", LIEF::assembly::arm::OPCODE::MVE_VRMLSLDAVHxs32) + .value("MVE_VRMULHs16", LIEF::assembly::arm::OPCODE::MVE_VRMULHs16) + .value("MVE_VRMULHs32", LIEF::assembly::arm::OPCODE::MVE_VRMULHs32) + .value("MVE_VRMULHs8", LIEF::assembly::arm::OPCODE::MVE_VRMULHs8) + .value("MVE_VRMULHu16", LIEF::assembly::arm::OPCODE::MVE_VRMULHu16) + .value("MVE_VRMULHu32", LIEF::assembly::arm::OPCODE::MVE_VRMULHu32) + .value("MVE_VRMULHu8", LIEF::assembly::arm::OPCODE::MVE_VRMULHu8) + .value("MVE_VRSHL_by_vecs16", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecs16) + .value("MVE_VRSHL_by_vecs32", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecs32) + .value("MVE_VRSHL_by_vecs8", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecs8) + .value("MVE_VRSHL_by_vecu16", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecu16) + .value("MVE_VRSHL_by_vecu32", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecu32) + .value("MVE_VRSHL_by_vecu8", LIEF::assembly::arm::OPCODE::MVE_VRSHL_by_vecu8) + .value("MVE_VRSHL_qrs16", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qrs16) + .value("MVE_VRSHL_qrs32", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qrs32) + .value("MVE_VRSHL_qrs8", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qrs8) + .value("MVE_VRSHL_qru16", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qru16) + .value("MVE_VRSHL_qru32", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qru32) + .value("MVE_VRSHL_qru8", LIEF::assembly::arm::OPCODE::MVE_VRSHL_qru8) + .value("MVE_VRSHRNi16bh", LIEF::assembly::arm::OPCODE::MVE_VRSHRNi16bh) + .value("MVE_VRSHRNi16th", LIEF::assembly::arm::OPCODE::MVE_VRSHRNi16th) + .value("MVE_VRSHRNi32bh", LIEF::assembly::arm::OPCODE::MVE_VRSHRNi32bh) + .value("MVE_VRSHRNi32th", LIEF::assembly::arm::OPCODE::MVE_VRSHRNi32th) + .value("MVE_VRSHR_imms16", LIEF::assembly::arm::OPCODE::MVE_VRSHR_imms16) + .value("MVE_VRSHR_imms32", LIEF::assembly::arm::OPCODE::MVE_VRSHR_imms32) + .value("MVE_VRSHR_imms8", LIEF::assembly::arm::OPCODE::MVE_VRSHR_imms8) + .value("MVE_VRSHR_immu16", LIEF::assembly::arm::OPCODE::MVE_VRSHR_immu16) + .value("MVE_VRSHR_immu32", LIEF::assembly::arm::OPCODE::MVE_VRSHR_immu32) + .value("MVE_VRSHR_immu8", LIEF::assembly::arm::OPCODE::MVE_VRSHR_immu8) + .value("MVE_VSBC", LIEF::assembly::arm::OPCODE::MVE_VSBC) + .value("MVE_VSBCI", LIEF::assembly::arm::OPCODE::MVE_VSBCI) + .value("MVE_VSHLC", LIEF::assembly::arm::OPCODE::MVE_VSHLC) + .value("MVE_VSHLL_imms16bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_imms16bh) + .value("MVE_VSHLL_imms16th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_imms16th) + .value("MVE_VSHLL_imms8bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_imms8bh) + .value("MVE_VSHLL_imms8th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_imms8th) + .value("MVE_VSHLL_immu16bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_immu16bh) + .value("MVE_VSHLL_immu16th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_immu16th) + .value("MVE_VSHLL_immu8bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_immu8bh) + .value("MVE_VSHLL_immu8th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_immu8th) + .value("MVE_VSHLL_lws16bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lws16bh) + .value("MVE_VSHLL_lws16th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lws16th) + .value("MVE_VSHLL_lws8bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lws8bh) + .value("MVE_VSHLL_lws8th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lws8th) + .value("MVE_VSHLL_lwu16bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lwu16bh) + .value("MVE_VSHLL_lwu16th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lwu16th) + .value("MVE_VSHLL_lwu8bh", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lwu8bh) + .value("MVE_VSHLL_lwu8th", LIEF::assembly::arm::OPCODE::MVE_VSHLL_lwu8th) + .value("MVE_VSHL_by_vecs16", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecs16) + .value("MVE_VSHL_by_vecs32", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecs32) + .value("MVE_VSHL_by_vecs8", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecs8) + .value("MVE_VSHL_by_vecu16", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecu16) + .value("MVE_VSHL_by_vecu32", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecu32) + .value("MVE_VSHL_by_vecu8", LIEF::assembly::arm::OPCODE::MVE_VSHL_by_vecu8) + .value("MVE_VSHL_immi16", LIEF::assembly::arm::OPCODE::MVE_VSHL_immi16) + .value("MVE_VSHL_immi32", LIEF::assembly::arm::OPCODE::MVE_VSHL_immi32) + .value("MVE_VSHL_immi8", LIEF::assembly::arm::OPCODE::MVE_VSHL_immi8) + .value("MVE_VSHL_qrs16", LIEF::assembly::arm::OPCODE::MVE_VSHL_qrs16) + .value("MVE_VSHL_qrs32", LIEF::assembly::arm::OPCODE::MVE_VSHL_qrs32) + .value("MVE_VSHL_qrs8", LIEF::assembly::arm::OPCODE::MVE_VSHL_qrs8) + .value("MVE_VSHL_qru16", LIEF::assembly::arm::OPCODE::MVE_VSHL_qru16) + .value("MVE_VSHL_qru32", LIEF::assembly::arm::OPCODE::MVE_VSHL_qru32) + .value("MVE_VSHL_qru8", LIEF::assembly::arm::OPCODE::MVE_VSHL_qru8) + .value("MVE_VSHRNi16bh", LIEF::assembly::arm::OPCODE::MVE_VSHRNi16bh) + .value("MVE_VSHRNi16th", LIEF::assembly::arm::OPCODE::MVE_VSHRNi16th) + .value("MVE_VSHRNi32bh", LIEF::assembly::arm::OPCODE::MVE_VSHRNi32bh) + .value("MVE_VSHRNi32th", LIEF::assembly::arm::OPCODE::MVE_VSHRNi32th) + .value("MVE_VSHR_imms16", LIEF::assembly::arm::OPCODE::MVE_VSHR_imms16) + .value("MVE_VSHR_imms32", LIEF::assembly::arm::OPCODE::MVE_VSHR_imms32) + .value("MVE_VSHR_imms8", LIEF::assembly::arm::OPCODE::MVE_VSHR_imms8) + .value("MVE_VSHR_immu16", LIEF::assembly::arm::OPCODE::MVE_VSHR_immu16) + .value("MVE_VSHR_immu32", LIEF::assembly::arm::OPCODE::MVE_VSHR_immu32) + .value("MVE_VSHR_immu8", LIEF::assembly::arm::OPCODE::MVE_VSHR_immu8) + .value("MVE_VSLIimm16", LIEF::assembly::arm::OPCODE::MVE_VSLIimm16) + .value("MVE_VSLIimm32", LIEF::assembly::arm::OPCODE::MVE_VSLIimm32) + .value("MVE_VSLIimm8", LIEF::assembly::arm::OPCODE::MVE_VSLIimm8) + .value("MVE_VSRIimm16", LIEF::assembly::arm::OPCODE::MVE_VSRIimm16) + .value("MVE_VSRIimm32", LIEF::assembly::arm::OPCODE::MVE_VSRIimm32) + .value("MVE_VSRIimm8", LIEF::assembly::arm::OPCODE::MVE_VSRIimm8) + .value("MVE_VST20_16", LIEF::assembly::arm::OPCODE::MVE_VST20_16) + .value("MVE_VST20_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST20_16_wb) + .value("MVE_VST20_32", LIEF::assembly::arm::OPCODE::MVE_VST20_32) + .value("MVE_VST20_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST20_32_wb) + .value("MVE_VST20_8", LIEF::assembly::arm::OPCODE::MVE_VST20_8) + .value("MVE_VST20_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST20_8_wb) + .value("MVE_VST21_16", LIEF::assembly::arm::OPCODE::MVE_VST21_16) + .value("MVE_VST21_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST21_16_wb) + .value("MVE_VST21_32", LIEF::assembly::arm::OPCODE::MVE_VST21_32) + .value("MVE_VST21_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST21_32_wb) + .value("MVE_VST21_8", LIEF::assembly::arm::OPCODE::MVE_VST21_8) + .value("MVE_VST21_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST21_8_wb) + .value("MVE_VST40_16", LIEF::assembly::arm::OPCODE::MVE_VST40_16) + .value("MVE_VST40_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST40_16_wb) + .value("MVE_VST40_32", LIEF::assembly::arm::OPCODE::MVE_VST40_32) + .value("MVE_VST40_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST40_32_wb) + .value("MVE_VST40_8", LIEF::assembly::arm::OPCODE::MVE_VST40_8) + .value("MVE_VST40_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST40_8_wb) + .value("MVE_VST41_16", LIEF::assembly::arm::OPCODE::MVE_VST41_16) + .value("MVE_VST41_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_16_wb) + .value("MVE_VST41_32", LIEF::assembly::arm::OPCODE::MVE_VST41_32) + .value("MVE_VST41_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_32_wb) + .value("MVE_VST41_8", LIEF::assembly::arm::OPCODE::MVE_VST41_8) + .value("MVE_VST41_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_8_wb) + .value("MVE_VST42_16", LIEF::assembly::arm::OPCODE::MVE_VST42_16) + .value("MVE_VST42_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST42_16_wb) + .value("MVE_VST42_32", LIEF::assembly::arm::OPCODE::MVE_VST42_32) + .value("MVE_VST42_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST42_32_wb) + .value("MVE_VST42_8", LIEF::assembly::arm::OPCODE::MVE_VST42_8) + .value("MVE_VST42_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST42_8_wb) + .value("MVE_VST43_16", LIEF::assembly::arm::OPCODE::MVE_VST43_16) + .value("MVE_VST43_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_16_wb); + opcodes.value("MVE_VST43_32", LIEF::assembly::arm::OPCODE::MVE_VST43_32) + .value("MVE_VST43_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_32_wb) + .value("MVE_VST43_8", LIEF::assembly::arm::OPCODE::MVE_VST43_8) + .value("MVE_VST43_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_8_wb) + .value("MVE_VSTRB16", LIEF::assembly::arm::OPCODE::MVE_VSTRB16) + .value("MVE_VSTRB16_post", LIEF::assembly::arm::OPCODE::MVE_VSTRB16_post) + .value("MVE_VSTRB16_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRB16_pre) + .value("MVE_VSTRB16_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRB16_rq) + .value("MVE_VSTRB32", LIEF::assembly::arm::OPCODE::MVE_VSTRB32) + .value("MVE_VSTRB32_post", LIEF::assembly::arm::OPCODE::MVE_VSTRB32_post) + .value("MVE_VSTRB32_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRB32_pre) + .value("MVE_VSTRB32_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRB32_rq) + .value("MVE_VSTRB8_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRB8_rq) + .value("MVE_VSTRBU8", LIEF::assembly::arm::OPCODE::MVE_VSTRBU8) + .value("MVE_VSTRBU8_post", LIEF::assembly::arm::OPCODE::MVE_VSTRBU8_post) + .value("MVE_VSTRBU8_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRBU8_pre) + .value("MVE_VSTRD64_qi", LIEF::assembly::arm::OPCODE::MVE_VSTRD64_qi) + .value("MVE_VSTRD64_qi_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRD64_qi_pre) + .value("MVE_VSTRD64_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRD64_rq) + .value("MVE_VSTRD64_rq_u", LIEF::assembly::arm::OPCODE::MVE_VSTRD64_rq_u) + .value("MVE_VSTRH16_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRH16_rq) + .value("MVE_VSTRH16_rq_u", LIEF::assembly::arm::OPCODE::MVE_VSTRH16_rq_u) + .value("MVE_VSTRH32", LIEF::assembly::arm::OPCODE::MVE_VSTRH32) + .value("MVE_VSTRH32_post", LIEF::assembly::arm::OPCODE::MVE_VSTRH32_post) + .value("MVE_VSTRH32_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRH32_pre) + .value("MVE_VSTRH32_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRH32_rq) + .value("MVE_VSTRH32_rq_u", LIEF::assembly::arm::OPCODE::MVE_VSTRH32_rq_u) + .value("MVE_VSTRHU16", LIEF::assembly::arm::OPCODE::MVE_VSTRHU16) + .value("MVE_VSTRHU16_post", LIEF::assembly::arm::OPCODE::MVE_VSTRHU16_post) + .value("MVE_VSTRHU16_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRHU16_pre) + .value("MVE_VSTRW32_qi", LIEF::assembly::arm::OPCODE::MVE_VSTRW32_qi) + .value("MVE_VSTRW32_qi_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRW32_qi_pre) + .value("MVE_VSTRW32_rq", LIEF::assembly::arm::OPCODE::MVE_VSTRW32_rq) + .value("MVE_VSTRW32_rq_u", LIEF::assembly::arm::OPCODE::MVE_VSTRW32_rq_u) + .value("MVE_VSTRWU32", LIEF::assembly::arm::OPCODE::MVE_VSTRWU32) + .value("MVE_VSTRWU32_post", LIEF::assembly::arm::OPCODE::MVE_VSTRWU32_post) + .value("MVE_VSTRWU32_pre", LIEF::assembly::arm::OPCODE::MVE_VSTRWU32_pre) + .value("MVE_VSUB_qr_f16", LIEF::assembly::arm::OPCODE::MVE_VSUB_qr_f16) + .value("MVE_VSUB_qr_f32", LIEF::assembly::arm::OPCODE::MVE_VSUB_qr_f32) + .value("MVE_VSUB_qr_i16", LIEF::assembly::arm::OPCODE::MVE_VSUB_qr_i16) + .value("MVE_VSUB_qr_i32", LIEF::assembly::arm::OPCODE::MVE_VSUB_qr_i32) + .value("MVE_VSUB_qr_i8", LIEF::assembly::arm::OPCODE::MVE_VSUB_qr_i8) + .value("MVE_VSUBf16", LIEF::assembly::arm::OPCODE::MVE_VSUBf16) + .value("MVE_VSUBf32", LIEF::assembly::arm::OPCODE::MVE_VSUBf32) + .value("MVE_VSUBi16", LIEF::assembly::arm::OPCODE::MVE_VSUBi16) + .value("MVE_VSUBi32", LIEF::assembly::arm::OPCODE::MVE_VSUBi32) + .value("MVE_VSUBi8", LIEF::assembly::arm::OPCODE::MVE_VSUBi8) + .value("MVE_WLSTP_16", LIEF::assembly::arm::OPCODE::MVE_WLSTP_16) + .value("MVE_WLSTP_32", LIEF::assembly::arm::OPCODE::MVE_WLSTP_32) + .value("MVE_WLSTP_64", LIEF::assembly::arm::OPCODE::MVE_WLSTP_64) + .value("MVE_WLSTP_8", LIEF::assembly::arm::OPCODE::MVE_WLSTP_8) + .value("MVNi", LIEF::assembly::arm::OPCODE::MVNi) + .value("MVNr", LIEF::assembly::arm::OPCODE::MVNr) + .value("MVNsi", LIEF::assembly::arm::OPCODE::MVNsi) + .value("MVNsr", LIEF::assembly::arm::OPCODE::MVNsr) + .value("NEON_VMAXNMNDf", LIEF::assembly::arm::OPCODE::NEON_VMAXNMNDf) + .value("NEON_VMAXNMNDh", LIEF::assembly::arm::OPCODE::NEON_VMAXNMNDh) + .value("NEON_VMAXNMNQf", LIEF::assembly::arm::OPCODE::NEON_VMAXNMNQf) + .value("NEON_VMAXNMNQh", LIEF::assembly::arm::OPCODE::NEON_VMAXNMNQh) + .value("NEON_VMINNMNDf", LIEF::assembly::arm::OPCODE::NEON_VMINNMNDf) + .value("NEON_VMINNMNDh", LIEF::assembly::arm::OPCODE::NEON_VMINNMNDh) + .value("NEON_VMINNMNQf", LIEF::assembly::arm::OPCODE::NEON_VMINNMNQf) + .value("NEON_VMINNMNQh", LIEF::assembly::arm::OPCODE::NEON_VMINNMNQh) + .value("ORRri", LIEF::assembly::arm::OPCODE::ORRri) + .value("ORRrr", LIEF::assembly::arm::OPCODE::ORRrr) + .value("ORRrsi", LIEF::assembly::arm::OPCODE::ORRrsi) + .value("ORRrsr", LIEF::assembly::arm::OPCODE::ORRrsr) + .value("PKHBT", LIEF::assembly::arm::OPCODE::PKHBT) + .value("PKHTB", LIEF::assembly::arm::OPCODE::PKHTB) + .value("PLDWi12", LIEF::assembly::arm::OPCODE::PLDWi12) + .value("PLDWrs", LIEF::assembly::arm::OPCODE::PLDWrs) + .value("PLDi12", LIEF::assembly::arm::OPCODE::PLDi12) + .value("PLDrs", LIEF::assembly::arm::OPCODE::PLDrs) + .value("PLIi12", LIEF::assembly::arm::OPCODE::PLIi12) + .value("PLIrs", LIEF::assembly::arm::OPCODE::PLIrs) + .value("QADD", LIEF::assembly::arm::OPCODE::QADD) + .value("QADD16", LIEF::assembly::arm::OPCODE::QADD16) + .value("QADD8", LIEF::assembly::arm::OPCODE::QADD8) + .value("QASX", LIEF::assembly::arm::OPCODE::QASX) + .value("QDADD", LIEF::assembly::arm::OPCODE::QDADD) + .value("QDSUB", LIEF::assembly::arm::OPCODE::QDSUB) + .value("QSAX", LIEF::assembly::arm::OPCODE::QSAX) + .value("QSUB", LIEF::assembly::arm::OPCODE::QSUB) + .value("QSUB16", LIEF::assembly::arm::OPCODE::QSUB16) + .value("QSUB8", LIEF::assembly::arm::OPCODE::QSUB8) + .value("RBIT", LIEF::assembly::arm::OPCODE::RBIT) + .value("REV", LIEF::assembly::arm::OPCODE::REV) + .value("REV16", LIEF::assembly::arm::OPCODE::REV16) + .value("REVSH", LIEF::assembly::arm::OPCODE::REVSH) + .value("RFEDA", LIEF::assembly::arm::OPCODE::RFEDA) + .value("RFEDA_UPD", LIEF::assembly::arm::OPCODE::RFEDA_UPD) + .value("RFEDB", LIEF::assembly::arm::OPCODE::RFEDB) + .value("RFEDB_UPD", LIEF::assembly::arm::OPCODE::RFEDB_UPD) + .value("RFEIA", LIEF::assembly::arm::OPCODE::RFEIA) + .value("RFEIA_UPD", LIEF::assembly::arm::OPCODE::RFEIA_UPD) + .value("RFEIB", LIEF::assembly::arm::OPCODE::RFEIB) + .value("RFEIB_UPD", LIEF::assembly::arm::OPCODE::RFEIB_UPD) + .value("RSBri", LIEF::assembly::arm::OPCODE::RSBri) + .value("RSBrr", LIEF::assembly::arm::OPCODE::RSBrr) + .value("RSBrsi", LIEF::assembly::arm::OPCODE::RSBrsi) + .value("RSBrsr", LIEF::assembly::arm::OPCODE::RSBrsr) + .value("RSCri", LIEF::assembly::arm::OPCODE::RSCri) + .value("RSCrr", LIEF::assembly::arm::OPCODE::RSCrr) + .value("RSCrsi", LIEF::assembly::arm::OPCODE::RSCrsi) + .value("RSCrsr", LIEF::assembly::arm::OPCODE::RSCrsr) + .value("SADD16", LIEF::assembly::arm::OPCODE::SADD16) + .value("SADD8", LIEF::assembly::arm::OPCODE::SADD8) + .value("SASX", LIEF::assembly::arm::OPCODE::SASX) + .value("SB", LIEF::assembly::arm::OPCODE::SB) + .value("SBCri", LIEF::assembly::arm::OPCODE::SBCri) + .value("SBCrr", LIEF::assembly::arm::OPCODE::SBCrr) + .value("SBCrsi", LIEF::assembly::arm::OPCODE::SBCrsi) + .value("SBCrsr", LIEF::assembly::arm::OPCODE::SBCrsr) + .value("SBFX", LIEF::assembly::arm::OPCODE::SBFX) + .value("SDIV", LIEF::assembly::arm::OPCODE::SDIV) + .value("SEL", LIEF::assembly::arm::OPCODE::SEL) + .value("SETEND", LIEF::assembly::arm::OPCODE::SETEND) + .value("SETPAN", LIEF::assembly::arm::OPCODE::SETPAN) + .value("SHA1C", LIEF::assembly::arm::OPCODE::SHA1C) + .value("SHA1H", LIEF::assembly::arm::OPCODE::SHA1H) + .value("SHA1M", LIEF::assembly::arm::OPCODE::SHA1M) + .value("SHA1P", LIEF::assembly::arm::OPCODE::SHA1P) + .value("SHA1SU0", LIEF::assembly::arm::OPCODE::SHA1SU0) + .value("SHA1SU1", LIEF::assembly::arm::OPCODE::SHA1SU1) + .value("SHA256H", LIEF::assembly::arm::OPCODE::SHA256H) + .value("SHA256H2", LIEF::assembly::arm::OPCODE::SHA256H2) + .value("SHA256SU0", LIEF::assembly::arm::OPCODE::SHA256SU0) + .value("SHA256SU1", LIEF::assembly::arm::OPCODE::SHA256SU1) + .value("SHADD16", LIEF::assembly::arm::OPCODE::SHADD16) + .value("SHADD8", LIEF::assembly::arm::OPCODE::SHADD8) + .value("SHASX", LIEF::assembly::arm::OPCODE::SHASX) + .value("SHSAX", LIEF::assembly::arm::OPCODE::SHSAX) + .value("SHSUB16", LIEF::assembly::arm::OPCODE::SHSUB16) + .value("SHSUB8", LIEF::assembly::arm::OPCODE::SHSUB8) + .value("SMC", LIEF::assembly::arm::OPCODE::SMC) + .value("SMLABB", LIEF::assembly::arm::OPCODE::SMLABB) + .value("SMLABT", LIEF::assembly::arm::OPCODE::SMLABT) + .value("SMLAD", LIEF::assembly::arm::OPCODE::SMLAD) + .value("SMLADX", LIEF::assembly::arm::OPCODE::SMLADX) + .value("SMLAL", LIEF::assembly::arm::OPCODE::SMLAL) + .value("SMLALBB", LIEF::assembly::arm::OPCODE::SMLALBB) + .value("SMLALBT", LIEF::assembly::arm::OPCODE::SMLALBT) + .value("SMLALD", LIEF::assembly::arm::OPCODE::SMLALD) + .value("SMLALDX", LIEF::assembly::arm::OPCODE::SMLALDX) + .value("SMLALTB", LIEF::assembly::arm::OPCODE::SMLALTB) + .value("SMLALTT", LIEF::assembly::arm::OPCODE::SMLALTT) + .value("SMLATB", LIEF::assembly::arm::OPCODE::SMLATB) + .value("SMLATT", LIEF::assembly::arm::OPCODE::SMLATT) + .value("SMLAWB", LIEF::assembly::arm::OPCODE::SMLAWB) + .value("SMLAWT", LIEF::assembly::arm::OPCODE::SMLAWT) + .value("SMLSD", LIEF::assembly::arm::OPCODE::SMLSD) + .value("SMLSDX", LIEF::assembly::arm::OPCODE::SMLSDX) + .value("SMLSLD", LIEF::assembly::arm::OPCODE::SMLSLD) + .value("SMLSLDX", LIEF::assembly::arm::OPCODE::SMLSLDX) + .value("SMMLA", LIEF::assembly::arm::OPCODE::SMMLA) + .value("SMMLAR", LIEF::assembly::arm::OPCODE::SMMLAR) + .value("SMMLS", LIEF::assembly::arm::OPCODE::SMMLS) + .value("SMMLSR", LIEF::assembly::arm::OPCODE::SMMLSR) + .value("SMMUL", LIEF::assembly::arm::OPCODE::SMMUL) + .value("SMMULR", LIEF::assembly::arm::OPCODE::SMMULR) + .value("SMUAD", LIEF::assembly::arm::OPCODE::SMUAD) + .value("SMUADX", LIEF::assembly::arm::OPCODE::SMUADX) + .value("SMULBB", LIEF::assembly::arm::OPCODE::SMULBB) + .value("SMULBT", LIEF::assembly::arm::OPCODE::SMULBT) + .value("SMULL", LIEF::assembly::arm::OPCODE::SMULL) + .value("SMULTB", LIEF::assembly::arm::OPCODE::SMULTB) + .value("SMULTT", LIEF::assembly::arm::OPCODE::SMULTT) + .value("SMULWB", LIEF::assembly::arm::OPCODE::SMULWB) + .value("SMULWT", LIEF::assembly::arm::OPCODE::SMULWT) + .value("SMUSD", LIEF::assembly::arm::OPCODE::SMUSD) + .value("SMUSDX", LIEF::assembly::arm::OPCODE::SMUSDX) + .value("SRSDA", LIEF::assembly::arm::OPCODE::SRSDA) + .value("SRSDA_UPD", LIEF::assembly::arm::OPCODE::SRSDA_UPD) + .value("SRSDB", LIEF::assembly::arm::OPCODE::SRSDB) + .value("SRSDB_UPD", LIEF::assembly::arm::OPCODE::SRSDB_UPD) + .value("SRSIA", LIEF::assembly::arm::OPCODE::SRSIA) + .value("SRSIA_UPD", LIEF::assembly::arm::OPCODE::SRSIA_UPD) + .value("SRSIB", LIEF::assembly::arm::OPCODE::SRSIB) + .value("SRSIB_UPD", LIEF::assembly::arm::OPCODE::SRSIB_UPD) + .value("SSAT", LIEF::assembly::arm::OPCODE::SSAT) + .value("SSAT16", LIEF::assembly::arm::OPCODE::SSAT16) + .value("SSAX", LIEF::assembly::arm::OPCODE::SSAX) + .value("SSUB16", LIEF::assembly::arm::OPCODE::SSUB16) + .value("SSUB8", LIEF::assembly::arm::OPCODE::SSUB8) + .value("STC2L_OFFSET", LIEF::assembly::arm::OPCODE::STC2L_OFFSET) + .value("STC2L_OPTION", LIEF::assembly::arm::OPCODE::STC2L_OPTION) + .value("STC2L_POST", LIEF::assembly::arm::OPCODE::STC2L_POST) + .value("STC2L_PRE", LIEF::assembly::arm::OPCODE::STC2L_PRE) + .value("STC2_OFFSET", LIEF::assembly::arm::OPCODE::STC2_OFFSET) + .value("STC2_OPTION", LIEF::assembly::arm::OPCODE::STC2_OPTION) + .value("STC2_POST", LIEF::assembly::arm::OPCODE::STC2_POST) + .value("STC2_PRE", LIEF::assembly::arm::OPCODE::STC2_PRE) + .value("STCL_OFFSET", LIEF::assembly::arm::OPCODE::STCL_OFFSET) + .value("STCL_OPTION", LIEF::assembly::arm::OPCODE::STCL_OPTION) + .value("STCL_POST", LIEF::assembly::arm::OPCODE::STCL_POST) + .value("STCL_PRE", LIEF::assembly::arm::OPCODE::STCL_PRE) + .value("STC_OFFSET", LIEF::assembly::arm::OPCODE::STC_OFFSET) + .value("STC_OPTION", LIEF::assembly::arm::OPCODE::STC_OPTION) + .value("STC_POST", LIEF::assembly::arm::OPCODE::STC_POST) + .value("STC_PRE", LIEF::assembly::arm::OPCODE::STC_PRE) + .value("STL", LIEF::assembly::arm::OPCODE::STL) + .value("STLB", LIEF::assembly::arm::OPCODE::STLB) + .value("STLEX", LIEF::assembly::arm::OPCODE::STLEX) + .value("STLEXB", LIEF::assembly::arm::OPCODE::STLEXB) + .value("STLEXD", LIEF::assembly::arm::OPCODE::STLEXD) + .value("STLEXH", LIEF::assembly::arm::OPCODE::STLEXH) + .value("STLH", LIEF::assembly::arm::OPCODE::STLH) + .value("STMDA", LIEF::assembly::arm::OPCODE::STMDA) + .value("STMDA_UPD", LIEF::assembly::arm::OPCODE::STMDA_UPD) + .value("STMDB", LIEF::assembly::arm::OPCODE::STMDB) + .value("STMDB_UPD", LIEF::assembly::arm::OPCODE::STMDB_UPD) + .value("STMIA", LIEF::assembly::arm::OPCODE::STMIA) + .value("STMIA_UPD", LIEF::assembly::arm::OPCODE::STMIA_UPD) + .value("STMIB", LIEF::assembly::arm::OPCODE::STMIB) + .value("STMIB_UPD", LIEF::assembly::arm::OPCODE::STMIB_UPD) + .value("STRBT_POST_IMM", LIEF::assembly::arm::OPCODE::STRBT_POST_IMM) + .value("STRBT_POST_REG", LIEF::assembly::arm::OPCODE::STRBT_POST_REG) + .value("STRB_POST_IMM", LIEF::assembly::arm::OPCODE::STRB_POST_IMM) + .value("STRB_POST_REG", LIEF::assembly::arm::OPCODE::STRB_POST_REG) + .value("STRB_PRE_IMM", LIEF::assembly::arm::OPCODE::STRB_PRE_IMM) + .value("STRB_PRE_REG", LIEF::assembly::arm::OPCODE::STRB_PRE_REG) + .value("STRBi12", LIEF::assembly::arm::OPCODE::STRBi12) + .value("STRBrs", LIEF::assembly::arm::OPCODE::STRBrs) + .value("STRD", LIEF::assembly::arm::OPCODE::STRD) + .value("STRD_POST", LIEF::assembly::arm::OPCODE::STRD_POST) + .value("STRD_PRE", LIEF::assembly::arm::OPCODE::STRD_PRE) + .value("STREX", LIEF::assembly::arm::OPCODE::STREX) + .value("STREXB", LIEF::assembly::arm::OPCODE::STREXB) + .value("STREXD", LIEF::assembly::arm::OPCODE::STREXD) + .value("STREXH", LIEF::assembly::arm::OPCODE::STREXH) + .value("STRH", LIEF::assembly::arm::OPCODE::STRH) + .value("STRHTi", LIEF::assembly::arm::OPCODE::STRHTi) + .value("STRHTr", LIEF::assembly::arm::OPCODE::STRHTr) + .value("STRH_POST", LIEF::assembly::arm::OPCODE::STRH_POST) + .value("STRH_PRE", LIEF::assembly::arm::OPCODE::STRH_PRE) + .value("STRT_POST_IMM", LIEF::assembly::arm::OPCODE::STRT_POST_IMM) + .value("STRT_POST_REG", LIEF::assembly::arm::OPCODE::STRT_POST_REG) + .value("STR_POST_IMM", LIEF::assembly::arm::OPCODE::STR_POST_IMM) + .value("STR_POST_REG", LIEF::assembly::arm::OPCODE::STR_POST_REG) + .value("STR_PRE_IMM", LIEF::assembly::arm::OPCODE::STR_PRE_IMM) + .value("STR_PRE_REG", LIEF::assembly::arm::OPCODE::STR_PRE_REG) + .value("STRi12", LIEF::assembly::arm::OPCODE::STRi12) + .value("STRrs", LIEF::assembly::arm::OPCODE::STRrs) + .value("SUBri", LIEF::assembly::arm::OPCODE::SUBri) + .value("SUBrr", LIEF::assembly::arm::OPCODE::SUBrr) + .value("SUBrsi", LIEF::assembly::arm::OPCODE::SUBrsi) + .value("SUBrsr", LIEF::assembly::arm::OPCODE::SUBrsr) + .value("SVC", LIEF::assembly::arm::OPCODE::SVC) + .value("SWP", LIEF::assembly::arm::OPCODE::SWP) + .value("SWPB", LIEF::assembly::arm::OPCODE::SWPB) + .value("SXTAB", LIEF::assembly::arm::OPCODE::SXTAB) + .value("SXTAB16", LIEF::assembly::arm::OPCODE::SXTAB16) + .value("SXTAH", LIEF::assembly::arm::OPCODE::SXTAH) + .value("SXTB", LIEF::assembly::arm::OPCODE::SXTB) + .value("SXTB16", LIEF::assembly::arm::OPCODE::SXTB16) + .value("SXTH", LIEF::assembly::arm::OPCODE::SXTH) + .value("TEQri", LIEF::assembly::arm::OPCODE::TEQri) + .value("TEQrr", LIEF::assembly::arm::OPCODE::TEQrr) + .value("TEQrsi", LIEF::assembly::arm::OPCODE::TEQrsi) + .value("TEQrsr", LIEF::assembly::arm::OPCODE::TEQrsr) + .value("TRAP", LIEF::assembly::arm::OPCODE::TRAP) + .value("TSB", LIEF::assembly::arm::OPCODE::TSB) + .value("TSTri", LIEF::assembly::arm::OPCODE::TSTri) + .value("TSTrr", LIEF::assembly::arm::OPCODE::TSTrr) + .value("TSTrsi", LIEF::assembly::arm::OPCODE::TSTrsi) + .value("TSTrsr", LIEF::assembly::arm::OPCODE::TSTrsr) + .value("UADD16", LIEF::assembly::arm::OPCODE::UADD16) + .value("UADD8", LIEF::assembly::arm::OPCODE::UADD8) + .value("UASX", LIEF::assembly::arm::OPCODE::UASX) + .value("UBFX", LIEF::assembly::arm::OPCODE::UBFX) + .value("UDF", LIEF::assembly::arm::OPCODE::UDF) + .value("UDIV", LIEF::assembly::arm::OPCODE::UDIV) + .value("UHADD16", LIEF::assembly::arm::OPCODE::UHADD16) + .value("UHADD8", LIEF::assembly::arm::OPCODE::UHADD8) + .value("UHASX", LIEF::assembly::arm::OPCODE::UHASX) + .value("UHSAX", LIEF::assembly::arm::OPCODE::UHSAX) + .value("UHSUB16", LIEF::assembly::arm::OPCODE::UHSUB16) + .value("UHSUB8", LIEF::assembly::arm::OPCODE::UHSUB8) + .value("UMAAL", LIEF::assembly::arm::OPCODE::UMAAL) + .value("UMLAL", LIEF::assembly::arm::OPCODE::UMLAL) + .value("UMULL", LIEF::assembly::arm::OPCODE::UMULL) + .value("UQADD16", LIEF::assembly::arm::OPCODE::UQADD16) + .value("UQADD8", LIEF::assembly::arm::OPCODE::UQADD8) + .value("UQASX", LIEF::assembly::arm::OPCODE::UQASX) + .value("UQSAX", LIEF::assembly::arm::OPCODE::UQSAX) + .value("UQSUB16", LIEF::assembly::arm::OPCODE::UQSUB16) + .value("UQSUB8", LIEF::assembly::arm::OPCODE::UQSUB8) + .value("USAD8", LIEF::assembly::arm::OPCODE::USAD8) + .value("USADA8", LIEF::assembly::arm::OPCODE::USADA8) + .value("USAT", LIEF::assembly::arm::OPCODE::USAT) + .value("USAT16", LIEF::assembly::arm::OPCODE::USAT16) + .value("USAX", LIEF::assembly::arm::OPCODE::USAX) + .value("USUB16", LIEF::assembly::arm::OPCODE::USUB16) + .value("USUB8", LIEF::assembly::arm::OPCODE::USUB8) + .value("UXTAB", LIEF::assembly::arm::OPCODE::UXTAB) + .value("UXTAB16", LIEF::assembly::arm::OPCODE::UXTAB16) + .value("UXTAH", LIEF::assembly::arm::OPCODE::UXTAH) + .value("UXTB", LIEF::assembly::arm::OPCODE::UXTB) + .value("UXTB16", LIEF::assembly::arm::OPCODE::UXTB16) + .value("UXTH", LIEF::assembly::arm::OPCODE::UXTH); + opcodes.value("VABALsv2i64", LIEF::assembly::arm::OPCODE::VABALsv2i64) + .value("VABALsv4i32", LIEF::assembly::arm::OPCODE::VABALsv4i32) + .value("VABALsv8i16", LIEF::assembly::arm::OPCODE::VABALsv8i16) + .value("VABALuv2i64", LIEF::assembly::arm::OPCODE::VABALuv2i64) + .value("VABALuv4i32", LIEF::assembly::arm::OPCODE::VABALuv4i32) + .value("VABALuv8i16", LIEF::assembly::arm::OPCODE::VABALuv8i16) + .value("VABAsv16i8", LIEF::assembly::arm::OPCODE::VABAsv16i8) + .value("VABAsv2i32", LIEF::assembly::arm::OPCODE::VABAsv2i32) + .value("VABAsv4i16", LIEF::assembly::arm::OPCODE::VABAsv4i16) + .value("VABAsv4i32", LIEF::assembly::arm::OPCODE::VABAsv4i32) + .value("VABAsv8i16", LIEF::assembly::arm::OPCODE::VABAsv8i16) + .value("VABAsv8i8", LIEF::assembly::arm::OPCODE::VABAsv8i8) + .value("VABAuv16i8", LIEF::assembly::arm::OPCODE::VABAuv16i8) + .value("VABAuv2i32", LIEF::assembly::arm::OPCODE::VABAuv2i32) + .value("VABAuv4i16", LIEF::assembly::arm::OPCODE::VABAuv4i16) + .value("VABAuv4i32", LIEF::assembly::arm::OPCODE::VABAuv4i32) + .value("VABAuv8i16", LIEF::assembly::arm::OPCODE::VABAuv8i16) + .value("VABAuv8i8", LIEF::assembly::arm::OPCODE::VABAuv8i8) + .value("VABDLsv2i64", LIEF::assembly::arm::OPCODE::VABDLsv2i64) + .value("VABDLsv4i32", LIEF::assembly::arm::OPCODE::VABDLsv4i32) + .value("VABDLsv8i16", LIEF::assembly::arm::OPCODE::VABDLsv8i16) + .value("VABDLuv2i64", LIEF::assembly::arm::OPCODE::VABDLuv2i64) + .value("VABDLuv4i32", LIEF::assembly::arm::OPCODE::VABDLuv4i32) + .value("VABDLuv8i16", LIEF::assembly::arm::OPCODE::VABDLuv8i16) + .value("VABDfd", LIEF::assembly::arm::OPCODE::VABDfd) + .value("VABDfq", LIEF::assembly::arm::OPCODE::VABDfq) + .value("VABDhd", LIEF::assembly::arm::OPCODE::VABDhd) + .value("VABDhq", LIEF::assembly::arm::OPCODE::VABDhq) + .value("VABDsv16i8", LIEF::assembly::arm::OPCODE::VABDsv16i8) + .value("VABDsv2i32", LIEF::assembly::arm::OPCODE::VABDsv2i32) + .value("VABDsv4i16", LIEF::assembly::arm::OPCODE::VABDsv4i16) + .value("VABDsv4i32", LIEF::assembly::arm::OPCODE::VABDsv4i32) + .value("VABDsv8i16", LIEF::assembly::arm::OPCODE::VABDsv8i16) + .value("VABDsv8i8", LIEF::assembly::arm::OPCODE::VABDsv8i8) + .value("VABDuv16i8", LIEF::assembly::arm::OPCODE::VABDuv16i8) + .value("VABDuv2i32", LIEF::assembly::arm::OPCODE::VABDuv2i32) + .value("VABDuv4i16", LIEF::assembly::arm::OPCODE::VABDuv4i16) + .value("VABDuv4i32", LIEF::assembly::arm::OPCODE::VABDuv4i32) + .value("VABDuv8i16", LIEF::assembly::arm::OPCODE::VABDuv8i16) + .value("VABDuv8i8", LIEF::assembly::arm::OPCODE::VABDuv8i8) + .value("VABSD", LIEF::assembly::arm::OPCODE::VABSD) + .value("VABSH", LIEF::assembly::arm::OPCODE::VABSH) + .value("VABSS", LIEF::assembly::arm::OPCODE::VABSS) + .value("VABSfd", LIEF::assembly::arm::OPCODE::VABSfd) + .value("VABSfq", LIEF::assembly::arm::OPCODE::VABSfq) + .value("VABShd", LIEF::assembly::arm::OPCODE::VABShd) + .value("VABShq", LIEF::assembly::arm::OPCODE::VABShq) + .value("VABSv16i8", LIEF::assembly::arm::OPCODE::VABSv16i8) + .value("VABSv2i32", LIEF::assembly::arm::OPCODE::VABSv2i32) + .value("VABSv4i16", LIEF::assembly::arm::OPCODE::VABSv4i16) + .value("VABSv4i32", LIEF::assembly::arm::OPCODE::VABSv4i32) + .value("VABSv8i16", LIEF::assembly::arm::OPCODE::VABSv8i16) + .value("VABSv8i8", LIEF::assembly::arm::OPCODE::VABSv8i8) + .value("VACGEfd", LIEF::assembly::arm::OPCODE::VACGEfd) + .value("VACGEfq", LIEF::assembly::arm::OPCODE::VACGEfq) + .value("VACGEhd", LIEF::assembly::arm::OPCODE::VACGEhd) + .value("VACGEhq", LIEF::assembly::arm::OPCODE::VACGEhq) + .value("VACGTfd", LIEF::assembly::arm::OPCODE::VACGTfd) + .value("VACGTfq", LIEF::assembly::arm::OPCODE::VACGTfq) + .value("VACGThd", LIEF::assembly::arm::OPCODE::VACGThd) + .value("VACGThq", LIEF::assembly::arm::OPCODE::VACGThq) + .value("VADDD", LIEF::assembly::arm::OPCODE::VADDD) + .value("VADDH", LIEF::assembly::arm::OPCODE::VADDH) + .value("VADDHNv2i32", LIEF::assembly::arm::OPCODE::VADDHNv2i32) + .value("VADDHNv4i16", LIEF::assembly::arm::OPCODE::VADDHNv4i16) + .value("VADDHNv8i8", LIEF::assembly::arm::OPCODE::VADDHNv8i8) + .value("VADDLsv2i64", LIEF::assembly::arm::OPCODE::VADDLsv2i64) + .value("VADDLsv4i32", LIEF::assembly::arm::OPCODE::VADDLsv4i32) + .value("VADDLsv8i16", LIEF::assembly::arm::OPCODE::VADDLsv8i16) + .value("VADDLuv2i64", LIEF::assembly::arm::OPCODE::VADDLuv2i64) + .value("VADDLuv4i32", LIEF::assembly::arm::OPCODE::VADDLuv4i32) + .value("VADDLuv8i16", LIEF::assembly::arm::OPCODE::VADDLuv8i16) + .value("VADDS", LIEF::assembly::arm::OPCODE::VADDS) + .value("VADDWsv2i64", LIEF::assembly::arm::OPCODE::VADDWsv2i64) + .value("VADDWsv4i32", LIEF::assembly::arm::OPCODE::VADDWsv4i32) + .value("VADDWsv8i16", LIEF::assembly::arm::OPCODE::VADDWsv8i16) + .value("VADDWuv2i64", LIEF::assembly::arm::OPCODE::VADDWuv2i64) + .value("VADDWuv4i32", LIEF::assembly::arm::OPCODE::VADDWuv4i32) + .value("VADDWuv8i16", LIEF::assembly::arm::OPCODE::VADDWuv8i16) + .value("VADDfd", LIEF::assembly::arm::OPCODE::VADDfd) + .value("VADDfq", LIEF::assembly::arm::OPCODE::VADDfq) + .value("VADDhd", LIEF::assembly::arm::OPCODE::VADDhd) + .value("VADDhq", LIEF::assembly::arm::OPCODE::VADDhq) + .value("VADDv16i8", LIEF::assembly::arm::OPCODE::VADDv16i8) + .value("VADDv1i64", LIEF::assembly::arm::OPCODE::VADDv1i64) + .value("VADDv2i32", LIEF::assembly::arm::OPCODE::VADDv2i32) + .value("VADDv2i64", LIEF::assembly::arm::OPCODE::VADDv2i64) + .value("VADDv4i16", LIEF::assembly::arm::OPCODE::VADDv4i16) + .value("VADDv4i32", LIEF::assembly::arm::OPCODE::VADDv4i32) + .value("VADDv8i16", LIEF::assembly::arm::OPCODE::VADDv8i16) + .value("VADDv8i8", LIEF::assembly::arm::OPCODE::VADDv8i8) + .value("VANDd", LIEF::assembly::arm::OPCODE::VANDd) + .value("VANDq", LIEF::assembly::arm::OPCODE::VANDq) + .value("VBF16MALBQ", LIEF::assembly::arm::OPCODE::VBF16MALBQ) + .value("VBF16MALBQI", LIEF::assembly::arm::OPCODE::VBF16MALBQI) + .value("VBF16MALTQ", LIEF::assembly::arm::OPCODE::VBF16MALTQ) + .value("VBF16MALTQI", LIEF::assembly::arm::OPCODE::VBF16MALTQI) + .value("VBICd", LIEF::assembly::arm::OPCODE::VBICd) + .value("VBICiv2i32", LIEF::assembly::arm::OPCODE::VBICiv2i32) + .value("VBICiv4i16", LIEF::assembly::arm::OPCODE::VBICiv4i16) + .value("VBICiv4i32", LIEF::assembly::arm::OPCODE::VBICiv4i32) + .value("VBICiv8i16", LIEF::assembly::arm::OPCODE::VBICiv8i16) + .value("VBICq", LIEF::assembly::arm::OPCODE::VBICq) + .value("VBIFd", LIEF::assembly::arm::OPCODE::VBIFd) + .value("VBIFq", LIEF::assembly::arm::OPCODE::VBIFq) + .value("VBITd", LIEF::assembly::arm::OPCODE::VBITd) + .value("VBITq", LIEF::assembly::arm::OPCODE::VBITq) + .value("VBSLd", LIEF::assembly::arm::OPCODE::VBSLd) + .value("VBSLq", LIEF::assembly::arm::OPCODE::VBSLq) + .value("VBSPd", LIEF::assembly::arm::OPCODE::VBSPd) + .value("VBSPq", LIEF::assembly::arm::OPCODE::VBSPq) + .value("VCADDv2f32", LIEF::assembly::arm::OPCODE::VCADDv2f32) + .value("VCADDv4f16", LIEF::assembly::arm::OPCODE::VCADDv4f16) + .value("VCADDv4f32", LIEF::assembly::arm::OPCODE::VCADDv4f32) + .value("VCADDv8f16", LIEF::assembly::arm::OPCODE::VCADDv8f16) + .value("VCEQfd", LIEF::assembly::arm::OPCODE::VCEQfd) + .value("VCEQfq", LIEF::assembly::arm::OPCODE::VCEQfq) + .value("VCEQhd", LIEF::assembly::arm::OPCODE::VCEQhd) + .value("VCEQhq", LIEF::assembly::arm::OPCODE::VCEQhq) + .value("VCEQv16i8", LIEF::assembly::arm::OPCODE::VCEQv16i8) + .value("VCEQv2i32", LIEF::assembly::arm::OPCODE::VCEQv2i32) + .value("VCEQv4i16", LIEF::assembly::arm::OPCODE::VCEQv4i16) + .value("VCEQv4i32", LIEF::assembly::arm::OPCODE::VCEQv4i32) + .value("VCEQv8i16", LIEF::assembly::arm::OPCODE::VCEQv8i16) + .value("VCEQv8i8", LIEF::assembly::arm::OPCODE::VCEQv8i8) + .value("VCEQzv16i8", LIEF::assembly::arm::OPCODE::VCEQzv16i8) + .value("VCEQzv2f32", LIEF::assembly::arm::OPCODE::VCEQzv2f32) + .value("VCEQzv2i32", LIEF::assembly::arm::OPCODE::VCEQzv2i32) + .value("VCEQzv4f16", LIEF::assembly::arm::OPCODE::VCEQzv4f16) + .value("VCEQzv4f32", LIEF::assembly::arm::OPCODE::VCEQzv4f32) + .value("VCEQzv4i16", LIEF::assembly::arm::OPCODE::VCEQzv4i16) + .value("VCEQzv4i32", LIEF::assembly::arm::OPCODE::VCEQzv4i32) + .value("VCEQzv8f16", LIEF::assembly::arm::OPCODE::VCEQzv8f16) + .value("VCEQzv8i16", LIEF::assembly::arm::OPCODE::VCEQzv8i16) + .value("VCEQzv8i8", LIEF::assembly::arm::OPCODE::VCEQzv8i8) + .value("VCGEfd", LIEF::assembly::arm::OPCODE::VCGEfd) + .value("VCGEfq", LIEF::assembly::arm::OPCODE::VCGEfq) + .value("VCGEhd", LIEF::assembly::arm::OPCODE::VCGEhd) + .value("VCGEhq", LIEF::assembly::arm::OPCODE::VCGEhq) + .value("VCGEsv16i8", LIEF::assembly::arm::OPCODE::VCGEsv16i8) + .value("VCGEsv2i32", LIEF::assembly::arm::OPCODE::VCGEsv2i32) + .value("VCGEsv4i16", LIEF::assembly::arm::OPCODE::VCGEsv4i16) + .value("VCGEsv4i32", LIEF::assembly::arm::OPCODE::VCGEsv4i32) + .value("VCGEsv8i16", LIEF::assembly::arm::OPCODE::VCGEsv8i16) + .value("VCGEsv8i8", LIEF::assembly::arm::OPCODE::VCGEsv8i8) + .value("VCGEuv16i8", LIEF::assembly::arm::OPCODE::VCGEuv16i8) + .value("VCGEuv2i32", LIEF::assembly::arm::OPCODE::VCGEuv2i32) + .value("VCGEuv4i16", LIEF::assembly::arm::OPCODE::VCGEuv4i16) + .value("VCGEuv4i32", LIEF::assembly::arm::OPCODE::VCGEuv4i32) + .value("VCGEuv8i16", LIEF::assembly::arm::OPCODE::VCGEuv8i16) + .value("VCGEuv8i8", LIEF::assembly::arm::OPCODE::VCGEuv8i8) + .value("VCGEzv16i8", LIEF::assembly::arm::OPCODE::VCGEzv16i8) + .value("VCGEzv2f32", LIEF::assembly::arm::OPCODE::VCGEzv2f32) + .value("VCGEzv2i32", LIEF::assembly::arm::OPCODE::VCGEzv2i32) + .value("VCGEzv4f16", LIEF::assembly::arm::OPCODE::VCGEzv4f16) + .value("VCGEzv4f32", LIEF::assembly::arm::OPCODE::VCGEzv4f32) + .value("VCGEzv4i16", LIEF::assembly::arm::OPCODE::VCGEzv4i16) + .value("VCGEzv4i32", LIEF::assembly::arm::OPCODE::VCGEzv4i32) + .value("VCGEzv8f16", LIEF::assembly::arm::OPCODE::VCGEzv8f16) + .value("VCGEzv8i16", LIEF::assembly::arm::OPCODE::VCGEzv8i16) + .value("VCGEzv8i8", LIEF::assembly::arm::OPCODE::VCGEzv8i8) + .value("VCGTfd", LIEF::assembly::arm::OPCODE::VCGTfd) + .value("VCGTfq", LIEF::assembly::arm::OPCODE::VCGTfq) + .value("VCGThd", LIEF::assembly::arm::OPCODE::VCGThd) + .value("VCGThq", LIEF::assembly::arm::OPCODE::VCGThq) + .value("VCGTsv16i8", LIEF::assembly::arm::OPCODE::VCGTsv16i8) + .value("VCGTsv2i32", LIEF::assembly::arm::OPCODE::VCGTsv2i32) + .value("VCGTsv4i16", LIEF::assembly::arm::OPCODE::VCGTsv4i16) + .value("VCGTsv4i32", LIEF::assembly::arm::OPCODE::VCGTsv4i32) + .value("VCGTsv8i16", LIEF::assembly::arm::OPCODE::VCGTsv8i16) + .value("VCGTsv8i8", LIEF::assembly::arm::OPCODE::VCGTsv8i8) + .value("VCGTuv16i8", LIEF::assembly::arm::OPCODE::VCGTuv16i8) + .value("VCGTuv2i32", LIEF::assembly::arm::OPCODE::VCGTuv2i32) + .value("VCGTuv4i16", LIEF::assembly::arm::OPCODE::VCGTuv4i16) + .value("VCGTuv4i32", LIEF::assembly::arm::OPCODE::VCGTuv4i32) + .value("VCGTuv8i16", LIEF::assembly::arm::OPCODE::VCGTuv8i16) + .value("VCGTuv8i8", LIEF::assembly::arm::OPCODE::VCGTuv8i8) + .value("VCGTzv16i8", LIEF::assembly::arm::OPCODE::VCGTzv16i8) + .value("VCGTzv2f32", LIEF::assembly::arm::OPCODE::VCGTzv2f32) + .value("VCGTzv2i32", LIEF::assembly::arm::OPCODE::VCGTzv2i32) + .value("VCGTzv4f16", LIEF::assembly::arm::OPCODE::VCGTzv4f16) + .value("VCGTzv4f32", LIEF::assembly::arm::OPCODE::VCGTzv4f32) + .value("VCGTzv4i16", LIEF::assembly::arm::OPCODE::VCGTzv4i16) + .value("VCGTzv4i32", LIEF::assembly::arm::OPCODE::VCGTzv4i32) + .value("VCGTzv8f16", LIEF::assembly::arm::OPCODE::VCGTzv8f16) + .value("VCGTzv8i16", LIEF::assembly::arm::OPCODE::VCGTzv8i16) + .value("VCGTzv8i8", LIEF::assembly::arm::OPCODE::VCGTzv8i8) + .value("VCLEzv16i8", LIEF::assembly::arm::OPCODE::VCLEzv16i8) + .value("VCLEzv2f32", LIEF::assembly::arm::OPCODE::VCLEzv2f32) + .value("VCLEzv2i32", LIEF::assembly::arm::OPCODE::VCLEzv2i32) + .value("VCLEzv4f16", LIEF::assembly::arm::OPCODE::VCLEzv4f16) + .value("VCLEzv4f32", LIEF::assembly::arm::OPCODE::VCLEzv4f32) + .value("VCLEzv4i16", LIEF::assembly::arm::OPCODE::VCLEzv4i16) + .value("VCLEzv4i32", LIEF::assembly::arm::OPCODE::VCLEzv4i32) + .value("VCLEzv8f16", LIEF::assembly::arm::OPCODE::VCLEzv8f16) + .value("VCLEzv8i16", LIEF::assembly::arm::OPCODE::VCLEzv8i16) + .value("VCLEzv8i8", LIEF::assembly::arm::OPCODE::VCLEzv8i8) + .value("VCLSv16i8", LIEF::assembly::arm::OPCODE::VCLSv16i8) + .value("VCLSv2i32", LIEF::assembly::arm::OPCODE::VCLSv2i32) + .value("VCLSv4i16", LIEF::assembly::arm::OPCODE::VCLSv4i16) + .value("VCLSv4i32", LIEF::assembly::arm::OPCODE::VCLSv4i32) + .value("VCLSv8i16", LIEF::assembly::arm::OPCODE::VCLSv8i16) + .value("VCLSv8i8", LIEF::assembly::arm::OPCODE::VCLSv8i8) + .value("VCLTzv16i8", LIEF::assembly::arm::OPCODE::VCLTzv16i8) + .value("VCLTzv2f32", LIEF::assembly::arm::OPCODE::VCLTzv2f32) + .value("VCLTzv2i32", LIEF::assembly::arm::OPCODE::VCLTzv2i32) + .value("VCLTzv4f16", LIEF::assembly::arm::OPCODE::VCLTzv4f16) + .value("VCLTzv4f32", LIEF::assembly::arm::OPCODE::VCLTzv4f32) + .value("VCLTzv4i16", LIEF::assembly::arm::OPCODE::VCLTzv4i16) + .value("VCLTzv4i32", LIEF::assembly::arm::OPCODE::VCLTzv4i32) + .value("VCLTzv8f16", LIEF::assembly::arm::OPCODE::VCLTzv8f16) + .value("VCLTzv8i16", LIEF::assembly::arm::OPCODE::VCLTzv8i16) + .value("VCLTzv8i8", LIEF::assembly::arm::OPCODE::VCLTzv8i8) + .value("VCLZv16i8", LIEF::assembly::arm::OPCODE::VCLZv16i8) + .value("VCLZv2i32", LIEF::assembly::arm::OPCODE::VCLZv2i32) + .value("VCLZv4i16", LIEF::assembly::arm::OPCODE::VCLZv4i16) + .value("VCLZv4i32", LIEF::assembly::arm::OPCODE::VCLZv4i32) + .value("VCLZv8i16", LIEF::assembly::arm::OPCODE::VCLZv8i16) + .value("VCLZv8i8", LIEF::assembly::arm::OPCODE::VCLZv8i8) + .value("VCMLAv2f32", LIEF::assembly::arm::OPCODE::VCMLAv2f32) + .value("VCMLAv2f32_indexed", LIEF::assembly::arm::OPCODE::VCMLAv2f32_indexed) + .value("VCMLAv4f16", LIEF::assembly::arm::OPCODE::VCMLAv4f16) + .value("VCMLAv4f16_indexed", LIEF::assembly::arm::OPCODE::VCMLAv4f16_indexed) + .value("VCMLAv4f32", LIEF::assembly::arm::OPCODE::VCMLAv4f32) + .value("VCMLAv4f32_indexed", LIEF::assembly::arm::OPCODE::VCMLAv4f32_indexed) + .value("VCMLAv8f16", LIEF::assembly::arm::OPCODE::VCMLAv8f16) + .value("VCMLAv8f16_indexed", LIEF::assembly::arm::OPCODE::VCMLAv8f16_indexed) + .value("VCMPD", LIEF::assembly::arm::OPCODE::VCMPD) + .value("VCMPED", LIEF::assembly::arm::OPCODE::VCMPED) + .value("VCMPEH", LIEF::assembly::arm::OPCODE::VCMPEH) + .value("VCMPES", LIEF::assembly::arm::OPCODE::VCMPES) + .value("VCMPEZD", LIEF::assembly::arm::OPCODE::VCMPEZD) + .value("VCMPEZH", LIEF::assembly::arm::OPCODE::VCMPEZH) + .value("VCMPEZS", LIEF::assembly::arm::OPCODE::VCMPEZS) + .value("VCMPH", LIEF::assembly::arm::OPCODE::VCMPH) + .value("VCMPS", LIEF::assembly::arm::OPCODE::VCMPS) + .value("VCMPZD", LIEF::assembly::arm::OPCODE::VCMPZD) + .value("VCMPZH", LIEF::assembly::arm::OPCODE::VCMPZH) + .value("VCMPZS", LIEF::assembly::arm::OPCODE::VCMPZS) + .value("VCNTd", LIEF::assembly::arm::OPCODE::VCNTd) + .value("VCNTq", LIEF::assembly::arm::OPCODE::VCNTq) + .value("VCVTANSDf", LIEF::assembly::arm::OPCODE::VCVTANSDf) + .value("VCVTANSDh", LIEF::assembly::arm::OPCODE::VCVTANSDh) + .value("VCVTANSQf", LIEF::assembly::arm::OPCODE::VCVTANSQf) + .value("VCVTANSQh", LIEF::assembly::arm::OPCODE::VCVTANSQh) + .value("VCVTANUDf", LIEF::assembly::arm::OPCODE::VCVTANUDf) + .value("VCVTANUDh", LIEF::assembly::arm::OPCODE::VCVTANUDh) + .value("VCVTANUQf", LIEF::assembly::arm::OPCODE::VCVTANUQf) + .value("VCVTANUQh", LIEF::assembly::arm::OPCODE::VCVTANUQh) + .value("VCVTASD", LIEF::assembly::arm::OPCODE::VCVTASD) + .value("VCVTASH", LIEF::assembly::arm::OPCODE::VCVTASH) + .value("VCVTASS", LIEF::assembly::arm::OPCODE::VCVTASS) + .value("VCVTAUD", LIEF::assembly::arm::OPCODE::VCVTAUD) + .value("VCVTAUH", LIEF::assembly::arm::OPCODE::VCVTAUH) + .value("VCVTAUS", LIEF::assembly::arm::OPCODE::VCVTAUS) + .value("VCVTBDH", LIEF::assembly::arm::OPCODE::VCVTBDH) + .value("VCVTBHD", LIEF::assembly::arm::OPCODE::VCVTBHD) + .value("VCVTBHS", LIEF::assembly::arm::OPCODE::VCVTBHS) + .value("VCVTBSH", LIEF::assembly::arm::OPCODE::VCVTBSH) + .value("VCVTDS", LIEF::assembly::arm::OPCODE::VCVTDS) + .value("VCVTMNSDf", LIEF::assembly::arm::OPCODE::VCVTMNSDf) + .value("VCVTMNSDh", LIEF::assembly::arm::OPCODE::VCVTMNSDh) + .value("VCVTMNSQf", LIEF::assembly::arm::OPCODE::VCVTMNSQf) + .value("VCVTMNSQh", LIEF::assembly::arm::OPCODE::VCVTMNSQh) + .value("VCVTMNUDf", LIEF::assembly::arm::OPCODE::VCVTMNUDf) + .value("VCVTMNUDh", LIEF::assembly::arm::OPCODE::VCVTMNUDh) + .value("VCVTMNUQf", LIEF::assembly::arm::OPCODE::VCVTMNUQf) + .value("VCVTMNUQh", LIEF::assembly::arm::OPCODE::VCVTMNUQh) + .value("VCVTMSD", LIEF::assembly::arm::OPCODE::VCVTMSD) + .value("VCVTMSH", LIEF::assembly::arm::OPCODE::VCVTMSH) + .value("VCVTMSS", LIEF::assembly::arm::OPCODE::VCVTMSS) + .value("VCVTMUD", LIEF::assembly::arm::OPCODE::VCVTMUD) + .value("VCVTMUH", LIEF::assembly::arm::OPCODE::VCVTMUH) + .value("VCVTMUS", LIEF::assembly::arm::OPCODE::VCVTMUS) + .value("VCVTNNSDf", LIEF::assembly::arm::OPCODE::VCVTNNSDf) + .value("VCVTNNSDh", LIEF::assembly::arm::OPCODE::VCVTNNSDh) + .value("VCVTNNSQf", LIEF::assembly::arm::OPCODE::VCVTNNSQf) + .value("VCVTNNSQh", LIEF::assembly::arm::OPCODE::VCVTNNSQh) + .value("VCVTNNUDf", LIEF::assembly::arm::OPCODE::VCVTNNUDf) + .value("VCVTNNUDh", LIEF::assembly::arm::OPCODE::VCVTNNUDh) + .value("VCVTNNUQf", LIEF::assembly::arm::OPCODE::VCVTNNUQf) + .value("VCVTNNUQh", LIEF::assembly::arm::OPCODE::VCVTNNUQh) + .value("VCVTNSD", LIEF::assembly::arm::OPCODE::VCVTNSD) + .value("VCVTNSH", LIEF::assembly::arm::OPCODE::VCVTNSH) + .value("VCVTNSS", LIEF::assembly::arm::OPCODE::VCVTNSS) + .value("VCVTNUD", LIEF::assembly::arm::OPCODE::VCVTNUD) + .value("VCVTNUH", LIEF::assembly::arm::OPCODE::VCVTNUH) + .value("VCVTNUS", LIEF::assembly::arm::OPCODE::VCVTNUS) + .value("VCVTPNSDf", LIEF::assembly::arm::OPCODE::VCVTPNSDf) + .value("VCVTPNSDh", LIEF::assembly::arm::OPCODE::VCVTPNSDh) + .value("VCVTPNSQf", LIEF::assembly::arm::OPCODE::VCVTPNSQf) + .value("VCVTPNSQh", LIEF::assembly::arm::OPCODE::VCVTPNSQh) + .value("VCVTPNUDf", LIEF::assembly::arm::OPCODE::VCVTPNUDf) + .value("VCVTPNUDh", LIEF::assembly::arm::OPCODE::VCVTPNUDh) + .value("VCVTPNUQf", LIEF::assembly::arm::OPCODE::VCVTPNUQf) + .value("VCVTPNUQh", LIEF::assembly::arm::OPCODE::VCVTPNUQh) + .value("VCVTPSD", LIEF::assembly::arm::OPCODE::VCVTPSD) + .value("VCVTPSH", LIEF::assembly::arm::OPCODE::VCVTPSH) + .value("VCVTPSS", LIEF::assembly::arm::OPCODE::VCVTPSS) + .value("VCVTPUD", LIEF::assembly::arm::OPCODE::VCVTPUD); + opcodes.value("VCVTPUH", LIEF::assembly::arm::OPCODE::VCVTPUH) + .value("VCVTPUS", LIEF::assembly::arm::OPCODE::VCVTPUS) + .value("VCVTSD", LIEF::assembly::arm::OPCODE::VCVTSD) + .value("VCVTTDH", LIEF::assembly::arm::OPCODE::VCVTTDH) + .value("VCVTTHD", LIEF::assembly::arm::OPCODE::VCVTTHD) + .value("VCVTTHS", LIEF::assembly::arm::OPCODE::VCVTTHS) + .value("VCVTTSH", LIEF::assembly::arm::OPCODE::VCVTTSH) + .value("VCVTf2h", LIEF::assembly::arm::OPCODE::VCVTf2h) + .value("VCVTf2sd", LIEF::assembly::arm::OPCODE::VCVTf2sd) + .value("VCVTf2sq", LIEF::assembly::arm::OPCODE::VCVTf2sq) + .value("VCVTf2ud", LIEF::assembly::arm::OPCODE::VCVTf2ud) + .value("VCVTf2uq", LIEF::assembly::arm::OPCODE::VCVTf2uq) + .value("VCVTf2xsd", LIEF::assembly::arm::OPCODE::VCVTf2xsd) + .value("VCVTf2xsq", LIEF::assembly::arm::OPCODE::VCVTf2xsq) + .value("VCVTf2xud", LIEF::assembly::arm::OPCODE::VCVTf2xud) + .value("VCVTf2xuq", LIEF::assembly::arm::OPCODE::VCVTf2xuq) + .value("VCVTh2f", LIEF::assembly::arm::OPCODE::VCVTh2f) + .value("VCVTh2sd", LIEF::assembly::arm::OPCODE::VCVTh2sd) + .value("VCVTh2sq", LIEF::assembly::arm::OPCODE::VCVTh2sq) + .value("VCVTh2ud", LIEF::assembly::arm::OPCODE::VCVTh2ud) + .value("VCVTh2uq", LIEF::assembly::arm::OPCODE::VCVTh2uq) + .value("VCVTh2xsd", LIEF::assembly::arm::OPCODE::VCVTh2xsd) + .value("VCVTh2xsq", LIEF::assembly::arm::OPCODE::VCVTh2xsq) + .value("VCVTh2xud", LIEF::assembly::arm::OPCODE::VCVTh2xud) + .value("VCVTh2xuq", LIEF::assembly::arm::OPCODE::VCVTh2xuq) + .value("VCVTs2fd", LIEF::assembly::arm::OPCODE::VCVTs2fd) + .value("VCVTs2fq", LIEF::assembly::arm::OPCODE::VCVTs2fq) + .value("VCVTs2hd", LIEF::assembly::arm::OPCODE::VCVTs2hd) + .value("VCVTs2hq", LIEF::assembly::arm::OPCODE::VCVTs2hq) + .value("VCVTu2fd", LIEF::assembly::arm::OPCODE::VCVTu2fd) + .value("VCVTu2fq", LIEF::assembly::arm::OPCODE::VCVTu2fq) + .value("VCVTu2hd", LIEF::assembly::arm::OPCODE::VCVTu2hd) + .value("VCVTu2hq", LIEF::assembly::arm::OPCODE::VCVTu2hq) + .value("VCVTxs2fd", LIEF::assembly::arm::OPCODE::VCVTxs2fd) + .value("VCVTxs2fq", LIEF::assembly::arm::OPCODE::VCVTxs2fq) + .value("VCVTxs2hd", LIEF::assembly::arm::OPCODE::VCVTxs2hd) + .value("VCVTxs2hq", LIEF::assembly::arm::OPCODE::VCVTxs2hq) + .value("VCVTxu2fd", LIEF::assembly::arm::OPCODE::VCVTxu2fd) + .value("VCVTxu2fq", LIEF::assembly::arm::OPCODE::VCVTxu2fq) + .value("VCVTxu2hd", LIEF::assembly::arm::OPCODE::VCVTxu2hd) + .value("VCVTxu2hq", LIEF::assembly::arm::OPCODE::VCVTxu2hq) + .value("VDIVD", LIEF::assembly::arm::OPCODE::VDIVD) + .value("VDIVH", LIEF::assembly::arm::OPCODE::VDIVH) + .value("VDIVS", LIEF::assembly::arm::OPCODE::VDIVS) + .value("VDUP16d", LIEF::assembly::arm::OPCODE::VDUP16d) + .value("VDUP16q", LIEF::assembly::arm::OPCODE::VDUP16q) + .value("VDUP32d", LIEF::assembly::arm::OPCODE::VDUP32d) + .value("VDUP32q", LIEF::assembly::arm::OPCODE::VDUP32q) + .value("VDUP8d", LIEF::assembly::arm::OPCODE::VDUP8d) + .value("VDUP8q", LIEF::assembly::arm::OPCODE::VDUP8q) + .value("VDUPLN16d", LIEF::assembly::arm::OPCODE::VDUPLN16d) + .value("VDUPLN16q", LIEF::assembly::arm::OPCODE::VDUPLN16q) + .value("VDUPLN32d", LIEF::assembly::arm::OPCODE::VDUPLN32d) + .value("VDUPLN32q", LIEF::assembly::arm::OPCODE::VDUPLN32q) + .value("VDUPLN8d", LIEF::assembly::arm::OPCODE::VDUPLN8d) + .value("VDUPLN8q", LIEF::assembly::arm::OPCODE::VDUPLN8q) + .value("VEORd", LIEF::assembly::arm::OPCODE::VEORd) + .value("VEORq", LIEF::assembly::arm::OPCODE::VEORq) + .value("VEXTd16", LIEF::assembly::arm::OPCODE::VEXTd16) + .value("VEXTd32", LIEF::assembly::arm::OPCODE::VEXTd32) + .value("VEXTd8", LIEF::assembly::arm::OPCODE::VEXTd8) + .value("VEXTq16", LIEF::assembly::arm::OPCODE::VEXTq16) + .value("VEXTq32", LIEF::assembly::arm::OPCODE::VEXTq32) + .value("VEXTq64", LIEF::assembly::arm::OPCODE::VEXTq64) + .value("VEXTq8", LIEF::assembly::arm::OPCODE::VEXTq8) + .value("VFMAD", LIEF::assembly::arm::OPCODE::VFMAD) + .value("VFMAH", LIEF::assembly::arm::OPCODE::VFMAH) + .value("VFMALD", LIEF::assembly::arm::OPCODE::VFMALD) + .value("VFMALDI", LIEF::assembly::arm::OPCODE::VFMALDI) + .value("VFMALQ", LIEF::assembly::arm::OPCODE::VFMALQ) + .value("VFMALQI", LIEF::assembly::arm::OPCODE::VFMALQI) + .value("VFMAS", LIEF::assembly::arm::OPCODE::VFMAS) + .value("VFMAfd", LIEF::assembly::arm::OPCODE::VFMAfd) + .value("VFMAfq", LIEF::assembly::arm::OPCODE::VFMAfq) + .value("VFMAhd", LIEF::assembly::arm::OPCODE::VFMAhd) + .value("VFMAhq", LIEF::assembly::arm::OPCODE::VFMAhq) + .value("VFMSD", LIEF::assembly::arm::OPCODE::VFMSD) + .value("VFMSH", LIEF::assembly::arm::OPCODE::VFMSH) + .value("VFMSLD", LIEF::assembly::arm::OPCODE::VFMSLD) + .value("VFMSLDI", LIEF::assembly::arm::OPCODE::VFMSLDI) + .value("VFMSLQ", LIEF::assembly::arm::OPCODE::VFMSLQ) + .value("VFMSLQI", LIEF::assembly::arm::OPCODE::VFMSLQI) + .value("VFMSS", LIEF::assembly::arm::OPCODE::VFMSS) + .value("VFMSfd", LIEF::assembly::arm::OPCODE::VFMSfd) + .value("VFMSfq", LIEF::assembly::arm::OPCODE::VFMSfq) + .value("VFMShd", LIEF::assembly::arm::OPCODE::VFMShd) + .value("VFMShq", LIEF::assembly::arm::OPCODE::VFMShq) + .value("VFNMAD", LIEF::assembly::arm::OPCODE::VFNMAD) + .value("VFNMAH", LIEF::assembly::arm::OPCODE::VFNMAH) + .value("VFNMAS", LIEF::assembly::arm::OPCODE::VFNMAS) + .value("VFNMSD", LIEF::assembly::arm::OPCODE::VFNMSD) + .value("VFNMSH", LIEF::assembly::arm::OPCODE::VFNMSH) + .value("VFNMSS", LIEF::assembly::arm::OPCODE::VFNMSS) + .value("VFP_VMAXNMD", LIEF::assembly::arm::OPCODE::VFP_VMAXNMD) + .value("VFP_VMAXNMH", LIEF::assembly::arm::OPCODE::VFP_VMAXNMH) + .value("VFP_VMAXNMS", LIEF::assembly::arm::OPCODE::VFP_VMAXNMS) + .value("VFP_VMINNMD", LIEF::assembly::arm::OPCODE::VFP_VMINNMD) + .value("VFP_VMINNMH", LIEF::assembly::arm::OPCODE::VFP_VMINNMH) + .value("VFP_VMINNMS", LIEF::assembly::arm::OPCODE::VFP_VMINNMS) + .value("VGETLNi32", LIEF::assembly::arm::OPCODE::VGETLNi32) + .value("VGETLNs16", LIEF::assembly::arm::OPCODE::VGETLNs16) + .value("VGETLNs8", LIEF::assembly::arm::OPCODE::VGETLNs8) + .value("VGETLNu16", LIEF::assembly::arm::OPCODE::VGETLNu16) + .value("VGETLNu8", LIEF::assembly::arm::OPCODE::VGETLNu8) + .value("VHADDsv16i8", LIEF::assembly::arm::OPCODE::VHADDsv16i8) + .value("VHADDsv2i32", LIEF::assembly::arm::OPCODE::VHADDsv2i32) + .value("VHADDsv4i16", LIEF::assembly::arm::OPCODE::VHADDsv4i16) + .value("VHADDsv4i32", LIEF::assembly::arm::OPCODE::VHADDsv4i32) + .value("VHADDsv8i16", LIEF::assembly::arm::OPCODE::VHADDsv8i16) + .value("VHADDsv8i8", LIEF::assembly::arm::OPCODE::VHADDsv8i8) + .value("VHADDuv16i8", LIEF::assembly::arm::OPCODE::VHADDuv16i8) + .value("VHADDuv2i32", LIEF::assembly::arm::OPCODE::VHADDuv2i32) + .value("VHADDuv4i16", LIEF::assembly::arm::OPCODE::VHADDuv4i16) + .value("VHADDuv4i32", LIEF::assembly::arm::OPCODE::VHADDuv4i32) + .value("VHADDuv8i16", LIEF::assembly::arm::OPCODE::VHADDuv8i16) + .value("VHADDuv8i8", LIEF::assembly::arm::OPCODE::VHADDuv8i8) + .value("VHSUBsv16i8", LIEF::assembly::arm::OPCODE::VHSUBsv16i8) + .value("VHSUBsv2i32", LIEF::assembly::arm::OPCODE::VHSUBsv2i32) + .value("VHSUBsv4i16", LIEF::assembly::arm::OPCODE::VHSUBsv4i16) + .value("VHSUBsv4i32", LIEF::assembly::arm::OPCODE::VHSUBsv4i32) + .value("VHSUBsv8i16", LIEF::assembly::arm::OPCODE::VHSUBsv8i16) + .value("VHSUBsv8i8", LIEF::assembly::arm::OPCODE::VHSUBsv8i8) + .value("VHSUBuv16i8", LIEF::assembly::arm::OPCODE::VHSUBuv16i8) + .value("VHSUBuv2i32", LIEF::assembly::arm::OPCODE::VHSUBuv2i32) + .value("VHSUBuv4i16", LIEF::assembly::arm::OPCODE::VHSUBuv4i16) + .value("VHSUBuv4i32", LIEF::assembly::arm::OPCODE::VHSUBuv4i32) + .value("VHSUBuv8i16", LIEF::assembly::arm::OPCODE::VHSUBuv8i16) + .value("VHSUBuv8i8", LIEF::assembly::arm::OPCODE::VHSUBuv8i8) + .value("VINSH", LIEF::assembly::arm::OPCODE::VINSH) + .value("VJCVT", LIEF::assembly::arm::OPCODE::VJCVT) + .value("VLD1DUPd16", LIEF::assembly::arm::OPCODE::VLD1DUPd16) + .value("VLD1DUPd16wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPd16wb_fixed) + .value("VLD1DUPd16wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPd16wb_register) + .value("VLD1DUPd32", LIEF::assembly::arm::OPCODE::VLD1DUPd32) + .value("VLD1DUPd32wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPd32wb_fixed) + .value("VLD1DUPd32wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPd32wb_register) + .value("VLD1DUPd8", LIEF::assembly::arm::OPCODE::VLD1DUPd8) + .value("VLD1DUPd8wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPd8wb_fixed) + .value("VLD1DUPd8wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPd8wb_register) + .value("VLD1DUPq16", LIEF::assembly::arm::OPCODE::VLD1DUPq16) + .value("VLD1DUPq16wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPq16wb_fixed) + .value("VLD1DUPq16wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPq16wb_register) + .value("VLD1DUPq32", LIEF::assembly::arm::OPCODE::VLD1DUPq32) + .value("VLD1DUPq32wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPq32wb_fixed) + .value("VLD1DUPq32wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPq32wb_register) + .value("VLD1DUPq8", LIEF::assembly::arm::OPCODE::VLD1DUPq8) + .value("VLD1DUPq8wb_fixed", LIEF::assembly::arm::OPCODE::VLD1DUPq8wb_fixed) + .value("VLD1DUPq8wb_register", LIEF::assembly::arm::OPCODE::VLD1DUPq8wb_register) + .value("VLD1LNd16", LIEF::assembly::arm::OPCODE::VLD1LNd16) + .value("VLD1LNd16_UPD", LIEF::assembly::arm::OPCODE::VLD1LNd16_UPD) + .value("VLD1LNd32", LIEF::assembly::arm::OPCODE::VLD1LNd32) + .value("VLD1LNd32_UPD", LIEF::assembly::arm::OPCODE::VLD1LNd32_UPD) + .value("VLD1LNd8", LIEF::assembly::arm::OPCODE::VLD1LNd8) + .value("VLD1LNd8_UPD", LIEF::assembly::arm::OPCODE::VLD1LNd8_UPD) + .value("VLD1LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD1LNq16Pseudo) + .value("VLD1LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1LNq16Pseudo_UPD) + .value("VLD1LNq32Pseudo", LIEF::assembly::arm::OPCODE::VLD1LNq32Pseudo) + .value("VLD1LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1LNq32Pseudo_UPD) + .value("VLD1LNq8Pseudo", LIEF::assembly::arm::OPCODE::VLD1LNq8Pseudo) + .value("VLD1LNq8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1LNq8Pseudo_UPD) + .value("VLD1d16", LIEF::assembly::arm::OPCODE::VLD1d16) + .value("VLD1d16Q", LIEF::assembly::arm::OPCODE::VLD1d16Q) + .value("VLD1d16QPseudo", LIEF::assembly::arm::OPCODE::VLD1d16QPseudo) + .value("VLD1d16QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d16QPseudoWB_fixed) + .value("VLD1d16QPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d16QPseudoWB_register) + .value("VLD1d16Qwb_fixed", LIEF::assembly::arm::OPCODE::VLD1d16Qwb_fixed) + .value("VLD1d16Qwb_register", LIEF::assembly::arm::OPCODE::VLD1d16Qwb_register) + .value("VLD1d16T", LIEF::assembly::arm::OPCODE::VLD1d16T) + .value("VLD1d16TPseudo", LIEF::assembly::arm::OPCODE::VLD1d16TPseudo) + .value("VLD1d16TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d16TPseudoWB_fixed) + .value("VLD1d16TPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d16TPseudoWB_register) + .value("VLD1d16Twb_fixed", LIEF::assembly::arm::OPCODE::VLD1d16Twb_fixed) + .value("VLD1d16Twb_register", LIEF::assembly::arm::OPCODE::VLD1d16Twb_register) + .value("VLD1d16wb_fixed", LIEF::assembly::arm::OPCODE::VLD1d16wb_fixed) + .value("VLD1d16wb_register", LIEF::assembly::arm::OPCODE::VLD1d16wb_register) + .value("VLD1d32", LIEF::assembly::arm::OPCODE::VLD1d32) + .value("VLD1d32Q", LIEF::assembly::arm::OPCODE::VLD1d32Q) + .value("VLD1d32QPseudo", LIEF::assembly::arm::OPCODE::VLD1d32QPseudo) + .value("VLD1d32QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d32QPseudoWB_fixed) + .value("VLD1d32QPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d32QPseudoWB_register) + .value("VLD1d32Qwb_fixed", LIEF::assembly::arm::OPCODE::VLD1d32Qwb_fixed) + .value("VLD1d32Qwb_register", LIEF::assembly::arm::OPCODE::VLD1d32Qwb_register) + .value("VLD1d32T", LIEF::assembly::arm::OPCODE::VLD1d32T) + .value("VLD1d32TPseudo", LIEF::assembly::arm::OPCODE::VLD1d32TPseudo) + .value("VLD1d32TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d32TPseudoWB_fixed) + .value("VLD1d32TPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d32TPseudoWB_register) + .value("VLD1d32Twb_fixed", LIEF::assembly::arm::OPCODE::VLD1d32Twb_fixed) + .value("VLD1d32Twb_register", LIEF::assembly::arm::OPCODE::VLD1d32Twb_register) + .value("VLD1d32wb_fixed", LIEF::assembly::arm::OPCODE::VLD1d32wb_fixed) + .value("VLD1d32wb_register", LIEF::assembly::arm::OPCODE::VLD1d32wb_register) + .value("VLD1d64", LIEF::assembly::arm::OPCODE::VLD1d64) + .value("VLD1d64Q", LIEF::assembly::arm::OPCODE::VLD1d64Q) + .value("VLD1d64QPseudo", LIEF::assembly::arm::OPCODE::VLD1d64QPseudo) + .value("VLD1d64QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d64QPseudoWB_fixed) + .value("VLD1d64QPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d64QPseudoWB_register) + .value("VLD1d64Qwb_fixed", LIEF::assembly::arm::OPCODE::VLD1d64Qwb_fixed) + .value("VLD1d64Qwb_register", LIEF::assembly::arm::OPCODE::VLD1d64Qwb_register) + .value("VLD1d64T", LIEF::assembly::arm::OPCODE::VLD1d64T) + .value("VLD1d64TPseudo", LIEF::assembly::arm::OPCODE::VLD1d64TPseudo) + .value("VLD1d64TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d64TPseudoWB_fixed) + .value("VLD1d64TPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d64TPseudoWB_register) + .value("VLD1d64Twb_fixed", LIEF::assembly::arm::OPCODE::VLD1d64Twb_fixed) + .value("VLD1d64Twb_register", LIEF::assembly::arm::OPCODE::VLD1d64Twb_register) + .value("VLD1d64wb_fixed", LIEF::assembly::arm::OPCODE::VLD1d64wb_fixed) + .value("VLD1d64wb_register", LIEF::assembly::arm::OPCODE::VLD1d64wb_register) + .value("VLD1d8", LIEF::assembly::arm::OPCODE::VLD1d8) + .value("VLD1d8Q", LIEF::assembly::arm::OPCODE::VLD1d8Q) + .value("VLD1d8QPseudo", LIEF::assembly::arm::OPCODE::VLD1d8QPseudo) + .value("VLD1d8QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d8QPseudoWB_fixed) + .value("VLD1d8QPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d8QPseudoWB_register) + .value("VLD1d8Qwb_fixed", LIEF::assembly::arm::OPCODE::VLD1d8Qwb_fixed) + .value("VLD1d8Qwb_register", LIEF::assembly::arm::OPCODE::VLD1d8Qwb_register) + .value("VLD1d8T", LIEF::assembly::arm::OPCODE::VLD1d8T) + .value("VLD1d8TPseudo", LIEF::assembly::arm::OPCODE::VLD1d8TPseudo) + .value("VLD1d8TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD1d8TPseudoWB_fixed) + .value("VLD1d8TPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD1d8TPseudoWB_register) + .value("VLD1d8Twb_fixed", LIEF::assembly::arm::OPCODE::VLD1d8Twb_fixed) + .value("VLD1d8Twb_register", LIEF::assembly::arm::OPCODE::VLD1d8Twb_register) + .value("VLD1d8wb_fixed", LIEF::assembly::arm::OPCODE::VLD1d8wb_fixed) + .value("VLD1d8wb_register", LIEF::assembly::arm::OPCODE::VLD1d8wb_register) + .value("VLD1q16", LIEF::assembly::arm::OPCODE::VLD1q16) + .value("VLD1q16HighQPseudo", LIEF::assembly::arm::OPCODE::VLD1q16HighQPseudo) + .value("VLD1q16HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q16HighQPseudo_UPD) + .value("VLD1q16HighTPseudo", LIEF::assembly::arm::OPCODE::VLD1q16HighTPseudo) + .value("VLD1q16HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q16HighTPseudo_UPD) + .value("VLD1q16LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q16LowQPseudo_UPD) + .value("VLD1q16LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q16LowTPseudo_UPD) + .value("VLD1q16wb_fixed", LIEF::assembly::arm::OPCODE::VLD1q16wb_fixed) + .value("VLD1q16wb_register", LIEF::assembly::arm::OPCODE::VLD1q16wb_register) + .value("VLD1q32", LIEF::assembly::arm::OPCODE::VLD1q32) + .value("VLD1q32HighQPseudo", LIEF::assembly::arm::OPCODE::VLD1q32HighQPseudo) + .value("VLD1q32HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q32HighQPseudo_UPD) + .value("VLD1q32HighTPseudo", LIEF::assembly::arm::OPCODE::VLD1q32HighTPseudo) + .value("VLD1q32HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q32HighTPseudo_UPD) + .value("VLD1q32LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q32LowQPseudo_UPD) + .value("VLD1q32LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q32LowTPseudo_UPD) + .value("VLD1q32wb_fixed", LIEF::assembly::arm::OPCODE::VLD1q32wb_fixed) + .value("VLD1q32wb_register", LIEF::assembly::arm::OPCODE::VLD1q32wb_register) + .value("VLD1q64", LIEF::assembly::arm::OPCODE::VLD1q64) + .value("VLD1q64HighQPseudo", LIEF::assembly::arm::OPCODE::VLD1q64HighQPseudo) + .value("VLD1q64HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q64HighQPseudo_UPD) + .value("VLD1q64HighTPseudo", LIEF::assembly::arm::OPCODE::VLD1q64HighTPseudo) + .value("VLD1q64HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q64HighTPseudo_UPD) + .value("VLD1q64LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q64LowQPseudo_UPD) + .value("VLD1q64LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q64LowTPseudo_UPD) + .value("VLD1q64wb_fixed", LIEF::assembly::arm::OPCODE::VLD1q64wb_fixed) + .value("VLD1q64wb_register", LIEF::assembly::arm::OPCODE::VLD1q64wb_register) + .value("VLD1q8", LIEF::assembly::arm::OPCODE::VLD1q8) + .value("VLD1q8HighQPseudo", LIEF::assembly::arm::OPCODE::VLD1q8HighQPseudo) + .value("VLD1q8HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q8HighQPseudo_UPD) + .value("VLD1q8HighTPseudo", LIEF::assembly::arm::OPCODE::VLD1q8HighTPseudo) + .value("VLD1q8HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q8HighTPseudo_UPD) + .value("VLD1q8LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q8LowQPseudo_UPD) + .value("VLD1q8LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD1q8LowTPseudo_UPD) + .value("VLD1q8wb_fixed", LIEF::assembly::arm::OPCODE::VLD1q8wb_fixed) + .value("VLD1q8wb_register", LIEF::assembly::arm::OPCODE::VLD1q8wb_register) + .value("VLD2DUPd16", LIEF::assembly::arm::OPCODE::VLD2DUPd16) + .value("VLD2DUPd16wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd16wb_fixed) + .value("VLD2DUPd16wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd16wb_register) + .value("VLD2DUPd16x2", LIEF::assembly::arm::OPCODE::VLD2DUPd16x2) + .value("VLD2DUPd16x2wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd16x2wb_fixed) + .value("VLD2DUPd16x2wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd16x2wb_register) + .value("VLD2DUPd32", LIEF::assembly::arm::OPCODE::VLD2DUPd32) + .value("VLD2DUPd32wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd32wb_fixed) + .value("VLD2DUPd32wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd32wb_register) + .value("VLD2DUPd32x2", LIEF::assembly::arm::OPCODE::VLD2DUPd32x2) + .value("VLD2DUPd32x2wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd32x2wb_fixed) + .value("VLD2DUPd32x2wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd32x2wb_register) + .value("VLD2DUPd8", LIEF::assembly::arm::OPCODE::VLD2DUPd8) + .value("VLD2DUPd8wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd8wb_fixed) + .value("VLD2DUPd8wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd8wb_register) + .value("VLD2DUPd8x2", LIEF::assembly::arm::OPCODE::VLD2DUPd8x2) + .value("VLD2DUPd8x2wb_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPd8x2wb_fixed) + .value("VLD2DUPd8x2wb_register", LIEF::assembly::arm::OPCODE::VLD2DUPd8x2wb_register) + .value("VLD2DUPq16EvenPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq16EvenPseudo) + .value("VLD2DUPq16OddPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq16OddPseudo) + .value("VLD2DUPq16OddPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPq16OddPseudoWB_fixed) + .value("VLD2DUPq16OddPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2DUPq16OddPseudoWB_register) + .value("VLD2DUPq32EvenPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq32EvenPseudo) + .value("VLD2DUPq32OddPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq32OddPseudo) + .value("VLD2DUPq32OddPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPq32OddPseudoWB_fixed) + .value("VLD2DUPq32OddPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2DUPq32OddPseudoWB_register) + .value("VLD2DUPq8EvenPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq8EvenPseudo) + .value("VLD2DUPq8OddPseudo", LIEF::assembly::arm::OPCODE::VLD2DUPq8OddPseudo) + .value("VLD2DUPq8OddPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPq8OddPseudoWB_fixed) + .value("VLD2DUPq8OddPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2DUPq8OddPseudoWB_register) + .value("VLD2LNd16", LIEF::assembly::arm::OPCODE::VLD2LNd16) + .value("VLD2LNd16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo) + .value("VLD2LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo_UPD) + .value("VLD2LNd16_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd16_UPD) + .value("VLD2LNd32", LIEF::assembly::arm::OPCODE::VLD2LNd32) + .value("VLD2LNd32Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd32Pseudo) + .value("VLD2LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd32Pseudo_UPD) + .value("VLD2LNd32_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd32_UPD) + .value("VLD2LNd8", LIEF::assembly::arm::OPCODE::VLD2LNd8) + .value("VLD2LNd8Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd8Pseudo) + .value("VLD2LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd8Pseudo_UPD) + .value("VLD2LNd8_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd8_UPD) + .value("VLD2LNq16", LIEF::assembly::arm::OPCODE::VLD2LNq16) + .value("VLD2LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo); + opcodes.value("VLD2LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo_UPD) + .value("VLD2LNq16_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq16_UPD) + .value("VLD2LNq32", LIEF::assembly::arm::OPCODE::VLD2LNq32) + .value("VLD2LNq32Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNq32Pseudo) + .value("VLD2LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq32Pseudo_UPD) + .value("VLD2LNq32_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq32_UPD) + .value("VLD2b16", LIEF::assembly::arm::OPCODE::VLD2b16) + .value("VLD2b16wb_fixed", LIEF::assembly::arm::OPCODE::VLD2b16wb_fixed) + .value("VLD2b16wb_register", LIEF::assembly::arm::OPCODE::VLD2b16wb_register) + .value("VLD2b32", LIEF::assembly::arm::OPCODE::VLD2b32) + .value("VLD2b32wb_fixed", LIEF::assembly::arm::OPCODE::VLD2b32wb_fixed) + .value("VLD2b32wb_register", LIEF::assembly::arm::OPCODE::VLD2b32wb_register) + .value("VLD2b8", LIEF::assembly::arm::OPCODE::VLD2b8) + .value("VLD2b8wb_fixed", LIEF::assembly::arm::OPCODE::VLD2b8wb_fixed) + .value("VLD2b8wb_register", LIEF::assembly::arm::OPCODE::VLD2b8wb_register) + .value("VLD2d16", LIEF::assembly::arm::OPCODE::VLD2d16) + .value("VLD2d16wb_fixed", LIEF::assembly::arm::OPCODE::VLD2d16wb_fixed) + .value("VLD2d16wb_register", LIEF::assembly::arm::OPCODE::VLD2d16wb_register) + .value("VLD2d32", LIEF::assembly::arm::OPCODE::VLD2d32) + .value("VLD2d32wb_fixed", LIEF::assembly::arm::OPCODE::VLD2d32wb_fixed) + .value("VLD2d32wb_register", LIEF::assembly::arm::OPCODE::VLD2d32wb_register) + .value("VLD2d8", LIEF::assembly::arm::OPCODE::VLD2d8) + .value("VLD2d8wb_fixed", LIEF::assembly::arm::OPCODE::VLD2d8wb_fixed) + .value("VLD2d8wb_register", LIEF::assembly::arm::OPCODE::VLD2d8wb_register) + .value("VLD2q16", LIEF::assembly::arm::OPCODE::VLD2q16) + .value("VLD2q16Pseudo", LIEF::assembly::arm::OPCODE::VLD2q16Pseudo) + .value("VLD2q16PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2q16PseudoWB_fixed) + .value("VLD2q16PseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2q16PseudoWB_register) + .value("VLD2q16wb_fixed", LIEF::assembly::arm::OPCODE::VLD2q16wb_fixed) + .value("VLD2q16wb_register", LIEF::assembly::arm::OPCODE::VLD2q16wb_register) + .value("VLD2q32", LIEF::assembly::arm::OPCODE::VLD2q32) + .value("VLD2q32Pseudo", LIEF::assembly::arm::OPCODE::VLD2q32Pseudo) + .value("VLD2q32PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2q32PseudoWB_fixed) + .value("VLD2q32PseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2q32PseudoWB_register) + .value("VLD2q32wb_fixed", LIEF::assembly::arm::OPCODE::VLD2q32wb_fixed) + .value("VLD2q32wb_register", LIEF::assembly::arm::OPCODE::VLD2q32wb_register) + .value("VLD2q8", LIEF::assembly::arm::OPCODE::VLD2q8) + .value("VLD2q8Pseudo", LIEF::assembly::arm::OPCODE::VLD2q8Pseudo) + .value("VLD2q8PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2q8PseudoWB_fixed) + .value("VLD2q8PseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2q8PseudoWB_register) + .value("VLD2q8wb_fixed", LIEF::assembly::arm::OPCODE::VLD2q8wb_fixed) + .value("VLD2q8wb_register", LIEF::assembly::arm::OPCODE::VLD2q8wb_register) + .value("VLD3DUPd16", LIEF::assembly::arm::OPCODE::VLD3DUPd16) + .value("VLD3DUPd16Pseudo", LIEF::assembly::arm::OPCODE::VLD3DUPd16Pseudo) + .value("VLD3DUPd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd16Pseudo_UPD) + .value("VLD3DUPd16_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd16_UPD) + .value("VLD3DUPd32", LIEF::assembly::arm::OPCODE::VLD3DUPd32) + .value("VLD3DUPd32Pseudo", LIEF::assembly::arm::OPCODE::VLD3DUPd32Pseudo) + .value("VLD3DUPd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd32Pseudo_UPD) + .value("VLD3DUPd32_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd32_UPD) + .value("VLD3DUPd8", LIEF::assembly::arm::OPCODE::VLD3DUPd8) + .value("VLD3DUPd8Pseudo", LIEF::assembly::arm::OPCODE::VLD3DUPd8Pseudo) + .value("VLD3DUPd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd8Pseudo_UPD) + .value("VLD3DUPd8_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPd8_UPD) + .value("VLD3DUPq16", LIEF::assembly::arm::OPCODE::VLD3DUPq16) + .value("VLD3DUPq16EvenPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq16EvenPseudo) + .value("VLD3DUPq16OddPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq16OddPseudo) + .value("VLD3DUPq16OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq16OddPseudo_UPD) + .value("VLD3DUPq16_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq16_UPD) + .value("VLD3DUPq32", LIEF::assembly::arm::OPCODE::VLD3DUPq32) + .value("VLD3DUPq32EvenPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq32EvenPseudo) + .value("VLD3DUPq32OddPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq32OddPseudo) + .value("VLD3DUPq32OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq32OddPseudo_UPD) + .value("VLD3DUPq32_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq32_UPD) + .value("VLD3DUPq8", LIEF::assembly::arm::OPCODE::VLD3DUPq8) + .value("VLD3DUPq8EvenPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq8EvenPseudo) + .value("VLD3DUPq8OddPseudo", LIEF::assembly::arm::OPCODE::VLD3DUPq8OddPseudo) + .value("VLD3DUPq8OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq8OddPseudo_UPD) + .value("VLD3DUPq8_UPD", LIEF::assembly::arm::OPCODE::VLD3DUPq8_UPD) + .value("VLD3LNd16", LIEF::assembly::arm::OPCODE::VLD3LNd16) + .value("VLD3LNd16Pseudo", LIEF::assembly::arm::OPCODE::VLD3LNd16Pseudo) + .value("VLD3LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd16Pseudo_UPD) + .value("VLD3LNd16_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd16_UPD) + .value("VLD3LNd32", LIEF::assembly::arm::OPCODE::VLD3LNd32) + .value("VLD3LNd32Pseudo", LIEF::assembly::arm::OPCODE::VLD3LNd32Pseudo) + .value("VLD3LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd32Pseudo_UPD) + .value("VLD3LNd32_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd32_UPD) + .value("VLD3LNd8", LIEF::assembly::arm::OPCODE::VLD3LNd8) + .value("VLD3LNd8Pseudo", LIEF::assembly::arm::OPCODE::VLD3LNd8Pseudo) + .value("VLD3LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd8Pseudo_UPD) + .value("VLD3LNd8_UPD", LIEF::assembly::arm::OPCODE::VLD3LNd8_UPD) + .value("VLD3LNq16", LIEF::assembly::arm::OPCODE::VLD3LNq16) + .value("VLD3LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD3LNq16Pseudo) + .value("VLD3LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3LNq16Pseudo_UPD) + .value("VLD3LNq16_UPD", LIEF::assembly::arm::OPCODE::VLD3LNq16_UPD) + .value("VLD3LNq32", LIEF::assembly::arm::OPCODE::VLD3LNq32) + .value("VLD3LNq32Pseudo", LIEF::assembly::arm::OPCODE::VLD3LNq32Pseudo) + .value("VLD3LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3LNq32Pseudo_UPD) + .value("VLD3LNq32_UPD", LIEF::assembly::arm::OPCODE::VLD3LNq32_UPD) + .value("VLD3d16", LIEF::assembly::arm::OPCODE::VLD3d16) + .value("VLD3d16Pseudo", LIEF::assembly::arm::OPCODE::VLD3d16Pseudo) + .value("VLD3d16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3d16Pseudo_UPD) + .value("VLD3d16_UPD", LIEF::assembly::arm::OPCODE::VLD3d16_UPD) + .value("VLD3d32", LIEF::assembly::arm::OPCODE::VLD3d32) + .value("VLD3d32Pseudo", LIEF::assembly::arm::OPCODE::VLD3d32Pseudo) + .value("VLD3d32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3d32Pseudo_UPD) + .value("VLD3d32_UPD", LIEF::assembly::arm::OPCODE::VLD3d32_UPD) + .value("VLD3d8", LIEF::assembly::arm::OPCODE::VLD3d8) + .value("VLD3d8Pseudo", LIEF::assembly::arm::OPCODE::VLD3d8Pseudo) + .value("VLD3d8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3d8Pseudo_UPD) + .value("VLD3d8_UPD", LIEF::assembly::arm::OPCODE::VLD3d8_UPD) + .value("VLD3q16", LIEF::assembly::arm::OPCODE::VLD3q16) + .value("VLD3q16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q16Pseudo_UPD) + .value("VLD3q16_UPD", LIEF::assembly::arm::OPCODE::VLD3q16_UPD) + .value("VLD3q16oddPseudo", LIEF::assembly::arm::OPCODE::VLD3q16oddPseudo) + .value("VLD3q16oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q16oddPseudo_UPD) + .value("VLD3q32", LIEF::assembly::arm::OPCODE::VLD3q32) + .value("VLD3q32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q32Pseudo_UPD) + .value("VLD3q32_UPD", LIEF::assembly::arm::OPCODE::VLD3q32_UPD) + .value("VLD3q32oddPseudo", LIEF::assembly::arm::OPCODE::VLD3q32oddPseudo) + .value("VLD3q32oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q32oddPseudo_UPD) + .value("VLD3q8", LIEF::assembly::arm::OPCODE::VLD3q8) + .value("VLD3q8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q8Pseudo_UPD) + .value("VLD3q8_UPD", LIEF::assembly::arm::OPCODE::VLD3q8_UPD) + .value("VLD3q8oddPseudo", LIEF::assembly::arm::OPCODE::VLD3q8oddPseudo) + .value("VLD3q8oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD3q8oddPseudo_UPD) + .value("VLD4DUPd16", LIEF::assembly::arm::OPCODE::VLD4DUPd16) + .value("VLD4DUPd16Pseudo", LIEF::assembly::arm::OPCODE::VLD4DUPd16Pseudo) + .value("VLD4DUPd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd16Pseudo_UPD) + .value("VLD4DUPd16_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd16_UPD) + .value("VLD4DUPd32", LIEF::assembly::arm::OPCODE::VLD4DUPd32) + .value("VLD4DUPd32Pseudo", LIEF::assembly::arm::OPCODE::VLD4DUPd32Pseudo) + .value("VLD4DUPd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd32Pseudo_UPD) + .value("VLD4DUPd32_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd32_UPD) + .value("VLD4DUPd8", LIEF::assembly::arm::OPCODE::VLD4DUPd8) + .value("VLD4DUPd8Pseudo", LIEF::assembly::arm::OPCODE::VLD4DUPd8Pseudo) + .value("VLD4DUPd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd8Pseudo_UPD) + .value("VLD4DUPd8_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPd8_UPD) + .value("VLD4DUPq16", LIEF::assembly::arm::OPCODE::VLD4DUPq16) + .value("VLD4DUPq16EvenPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq16EvenPseudo) + .value("VLD4DUPq16OddPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq16OddPseudo) + .value("VLD4DUPq16OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq16OddPseudo_UPD) + .value("VLD4DUPq16_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq16_UPD) + .value("VLD4DUPq32", LIEF::assembly::arm::OPCODE::VLD4DUPq32) + .value("VLD4DUPq32EvenPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq32EvenPseudo) + .value("VLD4DUPq32OddPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq32OddPseudo) + .value("VLD4DUPq32OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq32OddPseudo_UPD) + .value("VLD4DUPq32_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq32_UPD) + .value("VLD4DUPq8", LIEF::assembly::arm::OPCODE::VLD4DUPq8) + .value("VLD4DUPq8EvenPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq8EvenPseudo) + .value("VLD4DUPq8OddPseudo", LIEF::assembly::arm::OPCODE::VLD4DUPq8OddPseudo) + .value("VLD4DUPq8OddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq8OddPseudo_UPD) + .value("VLD4DUPq8_UPD", LIEF::assembly::arm::OPCODE::VLD4DUPq8_UPD) + .value("VLD4LNd16", LIEF::assembly::arm::OPCODE::VLD4LNd16) + .value("VLD4LNd16Pseudo", LIEF::assembly::arm::OPCODE::VLD4LNd16Pseudo) + .value("VLD4LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd16Pseudo_UPD) + .value("VLD4LNd16_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd16_UPD) + .value("VLD4LNd32", LIEF::assembly::arm::OPCODE::VLD4LNd32) + .value("VLD4LNd32Pseudo", LIEF::assembly::arm::OPCODE::VLD4LNd32Pseudo) + .value("VLD4LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd32Pseudo_UPD) + .value("VLD4LNd32_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd32_UPD) + .value("VLD4LNd8", LIEF::assembly::arm::OPCODE::VLD4LNd8) + .value("VLD4LNd8Pseudo", LIEF::assembly::arm::OPCODE::VLD4LNd8Pseudo) + .value("VLD4LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd8Pseudo_UPD) + .value("VLD4LNd8_UPD", LIEF::assembly::arm::OPCODE::VLD4LNd8_UPD) + .value("VLD4LNq16", LIEF::assembly::arm::OPCODE::VLD4LNq16) + .value("VLD4LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD4LNq16Pseudo) + .value("VLD4LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4LNq16Pseudo_UPD) + .value("VLD4LNq16_UPD", LIEF::assembly::arm::OPCODE::VLD4LNq16_UPD) + .value("VLD4LNq32", LIEF::assembly::arm::OPCODE::VLD4LNq32) + .value("VLD4LNq32Pseudo", LIEF::assembly::arm::OPCODE::VLD4LNq32Pseudo) + .value("VLD4LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4LNq32Pseudo_UPD) + .value("VLD4LNq32_UPD", LIEF::assembly::arm::OPCODE::VLD4LNq32_UPD) + .value("VLD4d16", LIEF::assembly::arm::OPCODE::VLD4d16) + .value("VLD4d16Pseudo", LIEF::assembly::arm::OPCODE::VLD4d16Pseudo) + .value("VLD4d16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4d16Pseudo_UPD) + .value("VLD4d16_UPD", LIEF::assembly::arm::OPCODE::VLD4d16_UPD) + .value("VLD4d32", LIEF::assembly::arm::OPCODE::VLD4d32) + .value("VLD4d32Pseudo", LIEF::assembly::arm::OPCODE::VLD4d32Pseudo) + .value("VLD4d32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4d32Pseudo_UPD) + .value("VLD4d32_UPD", LIEF::assembly::arm::OPCODE::VLD4d32_UPD) + .value("VLD4d8", LIEF::assembly::arm::OPCODE::VLD4d8) + .value("VLD4d8Pseudo", LIEF::assembly::arm::OPCODE::VLD4d8Pseudo) + .value("VLD4d8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4d8Pseudo_UPD) + .value("VLD4d8_UPD", LIEF::assembly::arm::OPCODE::VLD4d8_UPD) + .value("VLD4q16", LIEF::assembly::arm::OPCODE::VLD4q16) + .value("VLD4q16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q16Pseudo_UPD) + .value("VLD4q16_UPD", LIEF::assembly::arm::OPCODE::VLD4q16_UPD) + .value("VLD4q16oddPseudo", LIEF::assembly::arm::OPCODE::VLD4q16oddPseudo) + .value("VLD4q16oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q16oddPseudo_UPD) + .value("VLD4q32", LIEF::assembly::arm::OPCODE::VLD4q32) + .value("VLD4q32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q32Pseudo_UPD) + .value("VLD4q32_UPD", LIEF::assembly::arm::OPCODE::VLD4q32_UPD) + .value("VLD4q32oddPseudo", LIEF::assembly::arm::OPCODE::VLD4q32oddPseudo) + .value("VLD4q32oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q32oddPseudo_UPD) + .value("VLD4q8", LIEF::assembly::arm::OPCODE::VLD4q8) + .value("VLD4q8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q8Pseudo_UPD) + .value("VLD4q8_UPD", LIEF::assembly::arm::OPCODE::VLD4q8_UPD) + .value("VLD4q8oddPseudo", LIEF::assembly::arm::OPCODE::VLD4q8oddPseudo) + .value("VLD4q8oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VLD4q8oddPseudo_UPD) + .value("VLDMDDB_UPD", LIEF::assembly::arm::OPCODE::VLDMDDB_UPD) + .value("VLDMDIA", LIEF::assembly::arm::OPCODE::VLDMDIA) + .value("VLDMDIA_UPD", LIEF::assembly::arm::OPCODE::VLDMDIA_UPD) + .value("VLDMQIA", LIEF::assembly::arm::OPCODE::VLDMQIA) + .value("VLDMSDB_UPD", LIEF::assembly::arm::OPCODE::VLDMSDB_UPD) + .value("VLDMSIA", LIEF::assembly::arm::OPCODE::VLDMSIA) + .value("VLDMSIA_UPD", LIEF::assembly::arm::OPCODE::VLDMSIA_UPD) + .value("VLDRD", LIEF::assembly::arm::OPCODE::VLDRD) + .value("VLDRH", LIEF::assembly::arm::OPCODE::VLDRH) + .value("VLDRS", LIEF::assembly::arm::OPCODE::VLDRS) + .value("VLDR_FPCXTNS_off", LIEF::assembly::arm::OPCODE::VLDR_FPCXTNS_off) + .value("VLDR_FPCXTNS_post", LIEF::assembly::arm::OPCODE::VLDR_FPCXTNS_post) + .value("VLDR_FPCXTNS_pre", LIEF::assembly::arm::OPCODE::VLDR_FPCXTNS_pre) + .value("VLDR_FPCXTS_off", LIEF::assembly::arm::OPCODE::VLDR_FPCXTS_off) + .value("VLDR_FPCXTS_post", LIEF::assembly::arm::OPCODE::VLDR_FPCXTS_post) + .value("VLDR_FPCXTS_pre", LIEF::assembly::arm::OPCODE::VLDR_FPCXTS_pre) + .value("VLDR_FPSCR_NZCVQC_off", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_NZCVQC_off) + .value("VLDR_FPSCR_NZCVQC_post", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_NZCVQC_post) + .value("VLDR_FPSCR_NZCVQC_pre", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_NZCVQC_pre) + .value("VLDR_FPSCR_off", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_off) + .value("VLDR_FPSCR_post", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_post) + .value("VLDR_FPSCR_pre", LIEF::assembly::arm::OPCODE::VLDR_FPSCR_pre) + .value("VLDR_P0_off", LIEF::assembly::arm::OPCODE::VLDR_P0_off) + .value("VLDR_P0_post", LIEF::assembly::arm::OPCODE::VLDR_P0_post) + .value("VLDR_P0_pre", LIEF::assembly::arm::OPCODE::VLDR_P0_pre) + .value("VLDR_VPR_off", LIEF::assembly::arm::OPCODE::VLDR_VPR_off) + .value("VLDR_VPR_post", LIEF::assembly::arm::OPCODE::VLDR_VPR_post) + .value("VLDR_VPR_pre", LIEF::assembly::arm::OPCODE::VLDR_VPR_pre) + .value("VLLDM", LIEF::assembly::arm::OPCODE::VLLDM) + .value("VLLDM_T2", LIEF::assembly::arm::OPCODE::VLLDM_T2) + .value("VLSTM", LIEF::assembly::arm::OPCODE::VLSTM) + .value("VLSTM_T2", LIEF::assembly::arm::OPCODE::VLSTM_T2) + .value("VMAXfd", LIEF::assembly::arm::OPCODE::VMAXfd) + .value("VMAXfq", LIEF::assembly::arm::OPCODE::VMAXfq) + .value("VMAXhd", LIEF::assembly::arm::OPCODE::VMAXhd) + .value("VMAXhq", LIEF::assembly::arm::OPCODE::VMAXhq) + .value("VMAXsv16i8", LIEF::assembly::arm::OPCODE::VMAXsv16i8) + .value("VMAXsv2i32", LIEF::assembly::arm::OPCODE::VMAXsv2i32) + .value("VMAXsv4i16", LIEF::assembly::arm::OPCODE::VMAXsv4i16) + .value("VMAXsv4i32", LIEF::assembly::arm::OPCODE::VMAXsv4i32) + .value("VMAXsv8i16", LIEF::assembly::arm::OPCODE::VMAXsv8i16) + .value("VMAXsv8i8", LIEF::assembly::arm::OPCODE::VMAXsv8i8) + .value("VMAXuv16i8", LIEF::assembly::arm::OPCODE::VMAXuv16i8) + .value("VMAXuv2i32", LIEF::assembly::arm::OPCODE::VMAXuv2i32) + .value("VMAXuv4i16", LIEF::assembly::arm::OPCODE::VMAXuv4i16) + .value("VMAXuv4i32", LIEF::assembly::arm::OPCODE::VMAXuv4i32) + .value("VMAXuv8i16", LIEF::assembly::arm::OPCODE::VMAXuv8i16) + .value("VMAXuv8i8", LIEF::assembly::arm::OPCODE::VMAXuv8i8) + .value("VMINfd", LIEF::assembly::arm::OPCODE::VMINfd) + .value("VMINfq", LIEF::assembly::arm::OPCODE::VMINfq) + .value("VMINhd", LIEF::assembly::arm::OPCODE::VMINhd) + .value("VMINhq", LIEF::assembly::arm::OPCODE::VMINhq) + .value("VMINsv16i8", LIEF::assembly::arm::OPCODE::VMINsv16i8) + .value("VMINsv2i32", LIEF::assembly::arm::OPCODE::VMINsv2i32) + .value("VMINsv4i16", LIEF::assembly::arm::OPCODE::VMINsv4i16) + .value("VMINsv4i32", LIEF::assembly::arm::OPCODE::VMINsv4i32) + .value("VMINsv8i16", LIEF::assembly::arm::OPCODE::VMINsv8i16) + .value("VMINsv8i8", LIEF::assembly::arm::OPCODE::VMINsv8i8) + .value("VMINuv16i8", LIEF::assembly::arm::OPCODE::VMINuv16i8) + .value("VMINuv2i32", LIEF::assembly::arm::OPCODE::VMINuv2i32) + .value("VMINuv4i16", LIEF::assembly::arm::OPCODE::VMINuv4i16) + .value("VMINuv4i32", LIEF::assembly::arm::OPCODE::VMINuv4i32) + .value("VMINuv8i16", LIEF::assembly::arm::OPCODE::VMINuv8i16) + .value("VMINuv8i8", LIEF::assembly::arm::OPCODE::VMINuv8i8) + .value("VMLAD", LIEF::assembly::arm::OPCODE::VMLAD) + .value("VMLAH", LIEF::assembly::arm::OPCODE::VMLAH) + .value("VMLALslsv2i32", LIEF::assembly::arm::OPCODE::VMLALslsv2i32) + .value("VMLALslsv4i16", LIEF::assembly::arm::OPCODE::VMLALslsv4i16) + .value("VMLALsluv2i32", LIEF::assembly::arm::OPCODE::VMLALsluv2i32) + .value("VMLALsluv4i16", LIEF::assembly::arm::OPCODE::VMLALsluv4i16) + .value("VMLALsv2i64", LIEF::assembly::arm::OPCODE::VMLALsv2i64) + .value("VMLALsv4i32", LIEF::assembly::arm::OPCODE::VMLALsv4i32) + .value("VMLALsv8i16", LIEF::assembly::arm::OPCODE::VMLALsv8i16) + .value("VMLALuv2i64", LIEF::assembly::arm::OPCODE::VMLALuv2i64) + .value("VMLALuv4i32", LIEF::assembly::arm::OPCODE::VMLALuv4i32) + .value("VMLALuv8i16", LIEF::assembly::arm::OPCODE::VMLALuv8i16) + .value("VMLAS", LIEF::assembly::arm::OPCODE::VMLAS) + .value("VMLAfd", LIEF::assembly::arm::OPCODE::VMLAfd) + .value("VMLAfq", LIEF::assembly::arm::OPCODE::VMLAfq) + .value("VMLAhd", LIEF::assembly::arm::OPCODE::VMLAhd) + .value("VMLAhq", LIEF::assembly::arm::OPCODE::VMLAhq) + .value("VMLAslfd", LIEF::assembly::arm::OPCODE::VMLAslfd) + .value("VMLAslfq", LIEF::assembly::arm::OPCODE::VMLAslfq) + .value("VMLAslhd", LIEF::assembly::arm::OPCODE::VMLAslhd) + .value("VMLAslhq", LIEF::assembly::arm::OPCODE::VMLAslhq) + .value("VMLAslv2i32", LIEF::assembly::arm::OPCODE::VMLAslv2i32) + .value("VMLAslv4i16", LIEF::assembly::arm::OPCODE::VMLAslv4i16) + .value("VMLAslv4i32", LIEF::assembly::arm::OPCODE::VMLAslv4i32) + .value("VMLAslv8i16", LIEF::assembly::arm::OPCODE::VMLAslv8i16) + .value("VMLAv16i8", LIEF::assembly::arm::OPCODE::VMLAv16i8) + .value("VMLAv2i32", LIEF::assembly::arm::OPCODE::VMLAv2i32) + .value("VMLAv4i16", LIEF::assembly::arm::OPCODE::VMLAv4i16) + .value("VMLAv4i32", LIEF::assembly::arm::OPCODE::VMLAv4i32) + .value("VMLAv8i16", LIEF::assembly::arm::OPCODE::VMLAv8i16) + .value("VMLAv8i8", LIEF::assembly::arm::OPCODE::VMLAv8i8) + .value("VMLSD", LIEF::assembly::arm::OPCODE::VMLSD) + .value("VMLSH", LIEF::assembly::arm::OPCODE::VMLSH) + .value("VMLSLslsv2i32", LIEF::assembly::arm::OPCODE::VMLSLslsv2i32) + .value("VMLSLslsv4i16", LIEF::assembly::arm::OPCODE::VMLSLslsv4i16) + .value("VMLSLsluv2i32", LIEF::assembly::arm::OPCODE::VMLSLsluv2i32) + .value("VMLSLsluv4i16", LIEF::assembly::arm::OPCODE::VMLSLsluv4i16) + .value("VMLSLsv2i64", LIEF::assembly::arm::OPCODE::VMLSLsv2i64) + .value("VMLSLsv4i32", LIEF::assembly::arm::OPCODE::VMLSLsv4i32) + .value("VMLSLsv8i16", LIEF::assembly::arm::OPCODE::VMLSLsv8i16) + .value("VMLSLuv2i64", LIEF::assembly::arm::OPCODE::VMLSLuv2i64) + .value("VMLSLuv4i32", LIEF::assembly::arm::OPCODE::VMLSLuv4i32) + .value("VMLSLuv8i16", LIEF::assembly::arm::OPCODE::VMLSLuv8i16) + .value("VMLSS", LIEF::assembly::arm::OPCODE::VMLSS) + .value("VMLSfd", LIEF::assembly::arm::OPCODE::VMLSfd) + .value("VMLSfq", LIEF::assembly::arm::OPCODE::VMLSfq); + opcodes.value("VMLShd", LIEF::assembly::arm::OPCODE::VMLShd) + .value("VMLShq", LIEF::assembly::arm::OPCODE::VMLShq) + .value("VMLSslfd", LIEF::assembly::arm::OPCODE::VMLSslfd) + .value("VMLSslfq", LIEF::assembly::arm::OPCODE::VMLSslfq) + .value("VMLSslhd", LIEF::assembly::arm::OPCODE::VMLSslhd) + .value("VMLSslhq", LIEF::assembly::arm::OPCODE::VMLSslhq) + .value("VMLSslv2i32", LIEF::assembly::arm::OPCODE::VMLSslv2i32) + .value("VMLSslv4i16", LIEF::assembly::arm::OPCODE::VMLSslv4i16) + .value("VMLSslv4i32", LIEF::assembly::arm::OPCODE::VMLSslv4i32) + .value("VMLSslv8i16", LIEF::assembly::arm::OPCODE::VMLSslv8i16) + .value("VMLSv16i8", LIEF::assembly::arm::OPCODE::VMLSv16i8) + .value("VMLSv2i32", LIEF::assembly::arm::OPCODE::VMLSv2i32) + .value("VMLSv4i16", LIEF::assembly::arm::OPCODE::VMLSv4i16) + .value("VMLSv4i32", LIEF::assembly::arm::OPCODE::VMLSv4i32) + .value("VMLSv8i16", LIEF::assembly::arm::OPCODE::VMLSv8i16) + .value("VMLSv8i8", LIEF::assembly::arm::OPCODE::VMLSv8i8) + .value("VMMLA", LIEF::assembly::arm::OPCODE::VMMLA) + .value("VMOVD", LIEF::assembly::arm::OPCODE::VMOVD) + .value("VMOVDRR", LIEF::assembly::arm::OPCODE::VMOVDRR) + .value("VMOVH", LIEF::assembly::arm::OPCODE::VMOVH) + .value("VMOVHR", LIEF::assembly::arm::OPCODE::VMOVHR) + .value("VMOVLsv2i64", LIEF::assembly::arm::OPCODE::VMOVLsv2i64) + .value("VMOVLsv4i32", LIEF::assembly::arm::OPCODE::VMOVLsv4i32) + .value("VMOVLsv8i16", LIEF::assembly::arm::OPCODE::VMOVLsv8i16) + .value("VMOVLuv2i64", LIEF::assembly::arm::OPCODE::VMOVLuv2i64) + .value("VMOVLuv4i32", LIEF::assembly::arm::OPCODE::VMOVLuv4i32) + .value("VMOVLuv8i16", LIEF::assembly::arm::OPCODE::VMOVLuv8i16) + .value("VMOVNv2i32", LIEF::assembly::arm::OPCODE::VMOVNv2i32) + .value("VMOVNv4i16", LIEF::assembly::arm::OPCODE::VMOVNv4i16) + .value("VMOVNv8i8", LIEF::assembly::arm::OPCODE::VMOVNv8i8) + .value("VMOVRH", LIEF::assembly::arm::OPCODE::VMOVRH) + .value("VMOVRRD", LIEF::assembly::arm::OPCODE::VMOVRRD) + .value("VMOVRRS", LIEF::assembly::arm::OPCODE::VMOVRRS) + .value("VMOVRS", LIEF::assembly::arm::OPCODE::VMOVRS) + .value("VMOVS", LIEF::assembly::arm::OPCODE::VMOVS) + .value("VMOVSR", LIEF::assembly::arm::OPCODE::VMOVSR) + .value("VMOVSRR", LIEF::assembly::arm::OPCODE::VMOVSRR) + .value("VMOVv16i8", LIEF::assembly::arm::OPCODE::VMOVv16i8) + .value("VMOVv1i64", LIEF::assembly::arm::OPCODE::VMOVv1i64) + .value("VMOVv2f32", LIEF::assembly::arm::OPCODE::VMOVv2f32) + .value("VMOVv2i32", LIEF::assembly::arm::OPCODE::VMOVv2i32) + .value("VMOVv2i64", LIEF::assembly::arm::OPCODE::VMOVv2i64) + .value("VMOVv4f32", LIEF::assembly::arm::OPCODE::VMOVv4f32) + .value("VMOVv4i16", LIEF::assembly::arm::OPCODE::VMOVv4i16) + .value("VMOVv4i32", LIEF::assembly::arm::OPCODE::VMOVv4i32) + .value("VMOVv8i16", LIEF::assembly::arm::OPCODE::VMOVv8i16) + .value("VMOVv8i8", LIEF::assembly::arm::OPCODE::VMOVv8i8) + .value("VMRS", LIEF::assembly::arm::OPCODE::VMRS) + .value("VMRS_FPCXTNS", LIEF::assembly::arm::OPCODE::VMRS_FPCXTNS) + .value("VMRS_FPCXTS", LIEF::assembly::arm::OPCODE::VMRS_FPCXTS) + .value("VMRS_FPEXC", LIEF::assembly::arm::OPCODE::VMRS_FPEXC) + .value("VMRS_FPINST", LIEF::assembly::arm::OPCODE::VMRS_FPINST) + .value("VMRS_FPINST2", LIEF::assembly::arm::OPCODE::VMRS_FPINST2) + .value("VMRS_FPSCR_NZCVQC", LIEF::assembly::arm::OPCODE::VMRS_FPSCR_NZCVQC) + .value("VMRS_FPSID", LIEF::assembly::arm::OPCODE::VMRS_FPSID) + .value("VMRS_MVFR0", LIEF::assembly::arm::OPCODE::VMRS_MVFR0) + .value("VMRS_MVFR1", LIEF::assembly::arm::OPCODE::VMRS_MVFR1) + .value("VMRS_MVFR2", LIEF::assembly::arm::OPCODE::VMRS_MVFR2) + .value("VMRS_P0", LIEF::assembly::arm::OPCODE::VMRS_P0) + .value("VMRS_VPR", LIEF::assembly::arm::OPCODE::VMRS_VPR) + .value("VMSR", LIEF::assembly::arm::OPCODE::VMSR) + .value("VMSR_FPCXTNS", LIEF::assembly::arm::OPCODE::VMSR_FPCXTNS) + .value("VMSR_FPCXTS", LIEF::assembly::arm::OPCODE::VMSR_FPCXTS) + .value("VMSR_FPEXC", LIEF::assembly::arm::OPCODE::VMSR_FPEXC) + .value("VMSR_FPINST", LIEF::assembly::arm::OPCODE::VMSR_FPINST) + .value("VMSR_FPINST2", LIEF::assembly::arm::OPCODE::VMSR_FPINST2) + .value("VMSR_FPSCR_NZCVQC", LIEF::assembly::arm::OPCODE::VMSR_FPSCR_NZCVQC) + .value("VMSR_FPSID", LIEF::assembly::arm::OPCODE::VMSR_FPSID) + .value("VMSR_P0", LIEF::assembly::arm::OPCODE::VMSR_P0) + .value("VMSR_VPR", LIEF::assembly::arm::OPCODE::VMSR_VPR) + .value("VMULD", LIEF::assembly::arm::OPCODE::VMULD) + .value("VMULH", LIEF::assembly::arm::OPCODE::VMULH) + .value("VMULLp64", LIEF::assembly::arm::OPCODE::VMULLp64) + .value("VMULLp8", LIEF::assembly::arm::OPCODE::VMULLp8) + .value("VMULLslsv2i32", LIEF::assembly::arm::OPCODE::VMULLslsv2i32) + .value("VMULLslsv4i16", LIEF::assembly::arm::OPCODE::VMULLslsv4i16) + .value("VMULLsluv2i32", LIEF::assembly::arm::OPCODE::VMULLsluv2i32) + .value("VMULLsluv4i16", LIEF::assembly::arm::OPCODE::VMULLsluv4i16) + .value("VMULLsv2i64", LIEF::assembly::arm::OPCODE::VMULLsv2i64) + .value("VMULLsv4i32", LIEF::assembly::arm::OPCODE::VMULLsv4i32) + .value("VMULLsv8i16", LIEF::assembly::arm::OPCODE::VMULLsv8i16) + .value("VMULLuv2i64", LIEF::assembly::arm::OPCODE::VMULLuv2i64) + .value("VMULLuv4i32", LIEF::assembly::arm::OPCODE::VMULLuv4i32) + .value("VMULLuv8i16", LIEF::assembly::arm::OPCODE::VMULLuv8i16) + .value("VMULS", LIEF::assembly::arm::OPCODE::VMULS) + .value("VMULfd", LIEF::assembly::arm::OPCODE::VMULfd) + .value("VMULfq", LIEF::assembly::arm::OPCODE::VMULfq) + .value("VMULhd", LIEF::assembly::arm::OPCODE::VMULhd) + .value("VMULhq", LIEF::assembly::arm::OPCODE::VMULhq) + .value("VMULpd", LIEF::assembly::arm::OPCODE::VMULpd) + .value("VMULpq", LIEF::assembly::arm::OPCODE::VMULpq) + .value("VMULslfd", LIEF::assembly::arm::OPCODE::VMULslfd) + .value("VMULslfq", LIEF::assembly::arm::OPCODE::VMULslfq) + .value("VMULslhd", LIEF::assembly::arm::OPCODE::VMULslhd) + .value("VMULslhq", LIEF::assembly::arm::OPCODE::VMULslhq) + .value("VMULslv2i32", LIEF::assembly::arm::OPCODE::VMULslv2i32) + .value("VMULslv4i16", LIEF::assembly::arm::OPCODE::VMULslv4i16) + .value("VMULslv4i32", LIEF::assembly::arm::OPCODE::VMULslv4i32) + .value("VMULslv8i16", LIEF::assembly::arm::OPCODE::VMULslv8i16) + .value("VMULv16i8", LIEF::assembly::arm::OPCODE::VMULv16i8) + .value("VMULv2i32", LIEF::assembly::arm::OPCODE::VMULv2i32) + .value("VMULv4i16", LIEF::assembly::arm::OPCODE::VMULv4i16) + .value("VMULv4i32", LIEF::assembly::arm::OPCODE::VMULv4i32) + .value("VMULv8i16", LIEF::assembly::arm::OPCODE::VMULv8i16) + .value("VMULv8i8", LIEF::assembly::arm::OPCODE::VMULv8i8) + .value("VMVNd", LIEF::assembly::arm::OPCODE::VMVNd) + .value("VMVNq", LIEF::assembly::arm::OPCODE::VMVNq) + .value("VMVNv2i32", LIEF::assembly::arm::OPCODE::VMVNv2i32) + .value("VMVNv4i16", LIEF::assembly::arm::OPCODE::VMVNv4i16) + .value("VMVNv4i32", LIEF::assembly::arm::OPCODE::VMVNv4i32) + .value("VMVNv8i16", LIEF::assembly::arm::OPCODE::VMVNv8i16) + .value("VNEGD", LIEF::assembly::arm::OPCODE::VNEGD) + .value("VNEGH", LIEF::assembly::arm::OPCODE::VNEGH) + .value("VNEGS", LIEF::assembly::arm::OPCODE::VNEGS) + .value("VNEGf32q", LIEF::assembly::arm::OPCODE::VNEGf32q) + .value("VNEGfd", LIEF::assembly::arm::OPCODE::VNEGfd) + .value("VNEGhd", LIEF::assembly::arm::OPCODE::VNEGhd) + .value("VNEGhq", LIEF::assembly::arm::OPCODE::VNEGhq) + .value("VNEGs16d", LIEF::assembly::arm::OPCODE::VNEGs16d) + .value("VNEGs16q", LIEF::assembly::arm::OPCODE::VNEGs16q) + .value("VNEGs32d", LIEF::assembly::arm::OPCODE::VNEGs32d) + .value("VNEGs32q", LIEF::assembly::arm::OPCODE::VNEGs32q) + .value("VNEGs8d", LIEF::assembly::arm::OPCODE::VNEGs8d) + .value("VNEGs8q", LIEF::assembly::arm::OPCODE::VNEGs8q) + .value("VNMLAD", LIEF::assembly::arm::OPCODE::VNMLAD) + .value("VNMLAH", LIEF::assembly::arm::OPCODE::VNMLAH) + .value("VNMLAS", LIEF::assembly::arm::OPCODE::VNMLAS) + .value("VNMLSD", LIEF::assembly::arm::OPCODE::VNMLSD) + .value("VNMLSH", LIEF::assembly::arm::OPCODE::VNMLSH) + .value("VNMLSS", LIEF::assembly::arm::OPCODE::VNMLSS) + .value("VNMULD", LIEF::assembly::arm::OPCODE::VNMULD) + .value("VNMULH", LIEF::assembly::arm::OPCODE::VNMULH) + .value("VNMULS", LIEF::assembly::arm::OPCODE::VNMULS) + .value("VORNd", LIEF::assembly::arm::OPCODE::VORNd) + .value("VORNq", LIEF::assembly::arm::OPCODE::VORNq) + .value("VORRd", LIEF::assembly::arm::OPCODE::VORRd) + .value("VORRiv2i32", LIEF::assembly::arm::OPCODE::VORRiv2i32) + .value("VORRiv4i16", LIEF::assembly::arm::OPCODE::VORRiv4i16) + .value("VORRiv4i32", LIEF::assembly::arm::OPCODE::VORRiv4i32) + .value("VORRiv8i16", LIEF::assembly::arm::OPCODE::VORRiv8i16) + .value("VORRq", LIEF::assembly::arm::OPCODE::VORRq) + .value("VPADALsv16i8", LIEF::assembly::arm::OPCODE::VPADALsv16i8) + .value("VPADALsv2i32", LIEF::assembly::arm::OPCODE::VPADALsv2i32) + .value("VPADALsv4i16", LIEF::assembly::arm::OPCODE::VPADALsv4i16) + .value("VPADALsv4i32", LIEF::assembly::arm::OPCODE::VPADALsv4i32) + .value("VPADALsv8i16", LIEF::assembly::arm::OPCODE::VPADALsv8i16) + .value("VPADALsv8i8", LIEF::assembly::arm::OPCODE::VPADALsv8i8) + .value("VPADALuv16i8", LIEF::assembly::arm::OPCODE::VPADALuv16i8) + .value("VPADALuv2i32", LIEF::assembly::arm::OPCODE::VPADALuv2i32) + .value("VPADALuv4i16", LIEF::assembly::arm::OPCODE::VPADALuv4i16) + .value("VPADALuv4i32", LIEF::assembly::arm::OPCODE::VPADALuv4i32) + .value("VPADALuv8i16", LIEF::assembly::arm::OPCODE::VPADALuv8i16) + .value("VPADALuv8i8", LIEF::assembly::arm::OPCODE::VPADALuv8i8) + .value("VPADDLsv16i8", LIEF::assembly::arm::OPCODE::VPADDLsv16i8) + .value("VPADDLsv2i32", LIEF::assembly::arm::OPCODE::VPADDLsv2i32) + .value("VPADDLsv4i16", LIEF::assembly::arm::OPCODE::VPADDLsv4i16) + .value("VPADDLsv4i32", LIEF::assembly::arm::OPCODE::VPADDLsv4i32) + .value("VPADDLsv8i16", LIEF::assembly::arm::OPCODE::VPADDLsv8i16) + .value("VPADDLsv8i8", LIEF::assembly::arm::OPCODE::VPADDLsv8i8) + .value("VPADDLuv16i8", LIEF::assembly::arm::OPCODE::VPADDLuv16i8) + .value("VPADDLuv2i32", LIEF::assembly::arm::OPCODE::VPADDLuv2i32) + .value("VPADDLuv4i16", LIEF::assembly::arm::OPCODE::VPADDLuv4i16) + .value("VPADDLuv4i32", LIEF::assembly::arm::OPCODE::VPADDLuv4i32) + .value("VPADDLuv8i16", LIEF::assembly::arm::OPCODE::VPADDLuv8i16) + .value("VPADDLuv8i8", LIEF::assembly::arm::OPCODE::VPADDLuv8i8) + .value("VPADDf", LIEF::assembly::arm::OPCODE::VPADDf) + .value("VPADDh", LIEF::assembly::arm::OPCODE::VPADDh) + .value("VPADDi16", LIEF::assembly::arm::OPCODE::VPADDi16) + .value("VPADDi32", LIEF::assembly::arm::OPCODE::VPADDi32) + .value("VPADDi8", LIEF::assembly::arm::OPCODE::VPADDi8) + .value("VPMAXf", LIEF::assembly::arm::OPCODE::VPMAXf) + .value("VPMAXh", LIEF::assembly::arm::OPCODE::VPMAXh) + .value("VPMAXs16", LIEF::assembly::arm::OPCODE::VPMAXs16) + .value("VPMAXs32", LIEF::assembly::arm::OPCODE::VPMAXs32) + .value("VPMAXs8", LIEF::assembly::arm::OPCODE::VPMAXs8) + .value("VPMAXu16", LIEF::assembly::arm::OPCODE::VPMAXu16) + .value("VPMAXu32", LIEF::assembly::arm::OPCODE::VPMAXu32) + .value("VPMAXu8", LIEF::assembly::arm::OPCODE::VPMAXu8) + .value("VPMINf", LIEF::assembly::arm::OPCODE::VPMINf) + .value("VPMINh", LIEF::assembly::arm::OPCODE::VPMINh) + .value("VPMINs16", LIEF::assembly::arm::OPCODE::VPMINs16) + .value("VPMINs32", LIEF::assembly::arm::OPCODE::VPMINs32) + .value("VPMINs8", LIEF::assembly::arm::OPCODE::VPMINs8) + .value("VPMINu16", LIEF::assembly::arm::OPCODE::VPMINu16) + .value("VPMINu32", LIEF::assembly::arm::OPCODE::VPMINu32) + .value("VPMINu8", LIEF::assembly::arm::OPCODE::VPMINu8) + .value("VQABSv16i8", LIEF::assembly::arm::OPCODE::VQABSv16i8) + .value("VQABSv2i32", LIEF::assembly::arm::OPCODE::VQABSv2i32) + .value("VQABSv4i16", LIEF::assembly::arm::OPCODE::VQABSv4i16) + .value("VQABSv4i32", LIEF::assembly::arm::OPCODE::VQABSv4i32) + .value("VQABSv8i16", LIEF::assembly::arm::OPCODE::VQABSv8i16) + .value("VQABSv8i8", LIEF::assembly::arm::OPCODE::VQABSv8i8) + .value("VQADDsv16i8", LIEF::assembly::arm::OPCODE::VQADDsv16i8) + .value("VQADDsv1i64", LIEF::assembly::arm::OPCODE::VQADDsv1i64) + .value("VQADDsv2i32", LIEF::assembly::arm::OPCODE::VQADDsv2i32) + .value("VQADDsv2i64", LIEF::assembly::arm::OPCODE::VQADDsv2i64) + .value("VQADDsv4i16", LIEF::assembly::arm::OPCODE::VQADDsv4i16) + .value("VQADDsv4i32", LIEF::assembly::arm::OPCODE::VQADDsv4i32) + .value("VQADDsv8i16", LIEF::assembly::arm::OPCODE::VQADDsv8i16) + .value("VQADDsv8i8", LIEF::assembly::arm::OPCODE::VQADDsv8i8) + .value("VQADDuv16i8", LIEF::assembly::arm::OPCODE::VQADDuv16i8) + .value("VQADDuv1i64", LIEF::assembly::arm::OPCODE::VQADDuv1i64) + .value("VQADDuv2i32", LIEF::assembly::arm::OPCODE::VQADDuv2i32) + .value("VQADDuv2i64", LIEF::assembly::arm::OPCODE::VQADDuv2i64) + .value("VQADDuv4i16", LIEF::assembly::arm::OPCODE::VQADDuv4i16) + .value("VQADDuv4i32", LIEF::assembly::arm::OPCODE::VQADDuv4i32) + .value("VQADDuv8i16", LIEF::assembly::arm::OPCODE::VQADDuv8i16) + .value("VQADDuv8i8", LIEF::assembly::arm::OPCODE::VQADDuv8i8) + .value("VQDMLALslv2i32", LIEF::assembly::arm::OPCODE::VQDMLALslv2i32) + .value("VQDMLALslv4i16", LIEF::assembly::arm::OPCODE::VQDMLALslv4i16) + .value("VQDMLALv2i64", LIEF::assembly::arm::OPCODE::VQDMLALv2i64) + .value("VQDMLALv4i32", LIEF::assembly::arm::OPCODE::VQDMLALv4i32) + .value("VQDMLSLslv2i32", LIEF::assembly::arm::OPCODE::VQDMLSLslv2i32) + .value("VQDMLSLslv4i16", LIEF::assembly::arm::OPCODE::VQDMLSLslv4i16) + .value("VQDMLSLv2i64", LIEF::assembly::arm::OPCODE::VQDMLSLv2i64) + .value("VQDMLSLv4i32", LIEF::assembly::arm::OPCODE::VQDMLSLv4i32) + .value("VQDMULHslv2i32", LIEF::assembly::arm::OPCODE::VQDMULHslv2i32) + .value("VQDMULHslv4i16", LIEF::assembly::arm::OPCODE::VQDMULHslv4i16) + .value("VQDMULHslv4i32", LIEF::assembly::arm::OPCODE::VQDMULHslv4i32) + .value("VQDMULHslv8i16", LIEF::assembly::arm::OPCODE::VQDMULHslv8i16) + .value("VQDMULHv2i32", LIEF::assembly::arm::OPCODE::VQDMULHv2i32) + .value("VQDMULHv4i16", LIEF::assembly::arm::OPCODE::VQDMULHv4i16) + .value("VQDMULHv4i32", LIEF::assembly::arm::OPCODE::VQDMULHv4i32) + .value("VQDMULHv8i16", LIEF::assembly::arm::OPCODE::VQDMULHv8i16) + .value("VQDMULLslv2i32", LIEF::assembly::arm::OPCODE::VQDMULLslv2i32) + .value("VQDMULLslv4i16", LIEF::assembly::arm::OPCODE::VQDMULLslv4i16) + .value("VQDMULLv2i64", LIEF::assembly::arm::OPCODE::VQDMULLv2i64) + .value("VQDMULLv4i32", LIEF::assembly::arm::OPCODE::VQDMULLv4i32) + .value("VQMOVNsuv2i32", LIEF::assembly::arm::OPCODE::VQMOVNsuv2i32) + .value("VQMOVNsuv4i16", LIEF::assembly::arm::OPCODE::VQMOVNsuv4i16) + .value("VQMOVNsuv8i8", LIEF::assembly::arm::OPCODE::VQMOVNsuv8i8) + .value("VQMOVNsv2i32", LIEF::assembly::arm::OPCODE::VQMOVNsv2i32) + .value("VQMOVNsv4i16", LIEF::assembly::arm::OPCODE::VQMOVNsv4i16) + .value("VQMOVNsv8i8", LIEF::assembly::arm::OPCODE::VQMOVNsv8i8) + .value("VQMOVNuv2i32", LIEF::assembly::arm::OPCODE::VQMOVNuv2i32) + .value("VQMOVNuv4i16", LIEF::assembly::arm::OPCODE::VQMOVNuv4i16) + .value("VQMOVNuv8i8", LIEF::assembly::arm::OPCODE::VQMOVNuv8i8) + .value("VQNEGv16i8", LIEF::assembly::arm::OPCODE::VQNEGv16i8) + .value("VQNEGv2i32", LIEF::assembly::arm::OPCODE::VQNEGv2i32) + .value("VQNEGv4i16", LIEF::assembly::arm::OPCODE::VQNEGv4i16) + .value("VQNEGv4i32", LIEF::assembly::arm::OPCODE::VQNEGv4i32) + .value("VQNEGv8i16", LIEF::assembly::arm::OPCODE::VQNEGv8i16) + .value("VQNEGv8i8", LIEF::assembly::arm::OPCODE::VQNEGv8i8) + .value("VQRDMLAHslv2i32", LIEF::assembly::arm::OPCODE::VQRDMLAHslv2i32) + .value("VQRDMLAHslv4i16", LIEF::assembly::arm::OPCODE::VQRDMLAHslv4i16) + .value("VQRDMLAHslv4i32", LIEF::assembly::arm::OPCODE::VQRDMLAHslv4i32) + .value("VQRDMLAHslv8i16", LIEF::assembly::arm::OPCODE::VQRDMLAHslv8i16) + .value("VQRDMLAHv2i32", LIEF::assembly::arm::OPCODE::VQRDMLAHv2i32) + .value("VQRDMLAHv4i16", LIEF::assembly::arm::OPCODE::VQRDMLAHv4i16) + .value("VQRDMLAHv4i32", LIEF::assembly::arm::OPCODE::VQRDMLAHv4i32) + .value("VQRDMLAHv8i16", LIEF::assembly::arm::OPCODE::VQRDMLAHv8i16) + .value("VQRDMLSHslv2i32", LIEF::assembly::arm::OPCODE::VQRDMLSHslv2i32) + .value("VQRDMLSHslv4i16", LIEF::assembly::arm::OPCODE::VQRDMLSHslv4i16) + .value("VQRDMLSHslv4i32", LIEF::assembly::arm::OPCODE::VQRDMLSHslv4i32) + .value("VQRDMLSHslv8i16", LIEF::assembly::arm::OPCODE::VQRDMLSHslv8i16) + .value("VQRDMLSHv2i32", LIEF::assembly::arm::OPCODE::VQRDMLSHv2i32) + .value("VQRDMLSHv4i16", LIEF::assembly::arm::OPCODE::VQRDMLSHv4i16) + .value("VQRDMLSHv4i32", LIEF::assembly::arm::OPCODE::VQRDMLSHv4i32) + .value("VQRDMLSHv8i16", LIEF::assembly::arm::OPCODE::VQRDMLSHv8i16) + .value("VQRDMULHslv2i32", LIEF::assembly::arm::OPCODE::VQRDMULHslv2i32) + .value("VQRDMULHslv4i16", LIEF::assembly::arm::OPCODE::VQRDMULHslv4i16) + .value("VQRDMULHslv4i32", LIEF::assembly::arm::OPCODE::VQRDMULHslv4i32) + .value("VQRDMULHslv8i16", LIEF::assembly::arm::OPCODE::VQRDMULHslv8i16) + .value("VQRDMULHv2i32", LIEF::assembly::arm::OPCODE::VQRDMULHv2i32) + .value("VQRDMULHv4i16", LIEF::assembly::arm::OPCODE::VQRDMULHv4i16) + .value("VQRDMULHv4i32", LIEF::assembly::arm::OPCODE::VQRDMULHv4i32) + .value("VQRDMULHv8i16", LIEF::assembly::arm::OPCODE::VQRDMULHv8i16) + .value("VQRSHLsv16i8", LIEF::assembly::arm::OPCODE::VQRSHLsv16i8) + .value("VQRSHLsv1i64", LIEF::assembly::arm::OPCODE::VQRSHLsv1i64) + .value("VQRSHLsv2i32", LIEF::assembly::arm::OPCODE::VQRSHLsv2i32) + .value("VQRSHLsv2i64", LIEF::assembly::arm::OPCODE::VQRSHLsv2i64) + .value("VQRSHLsv4i16", LIEF::assembly::arm::OPCODE::VQRSHLsv4i16) + .value("VQRSHLsv4i32", LIEF::assembly::arm::OPCODE::VQRSHLsv4i32) + .value("VQRSHLsv8i16", LIEF::assembly::arm::OPCODE::VQRSHLsv8i16) + .value("VQRSHLsv8i8", LIEF::assembly::arm::OPCODE::VQRSHLsv8i8) + .value("VQRSHLuv16i8", LIEF::assembly::arm::OPCODE::VQRSHLuv16i8) + .value("VQRSHLuv1i64", LIEF::assembly::arm::OPCODE::VQRSHLuv1i64) + .value("VQRSHLuv2i32", LIEF::assembly::arm::OPCODE::VQRSHLuv2i32) + .value("VQRSHLuv2i64", LIEF::assembly::arm::OPCODE::VQRSHLuv2i64) + .value("VQRSHLuv4i16", LIEF::assembly::arm::OPCODE::VQRSHLuv4i16) + .value("VQRSHLuv4i32", LIEF::assembly::arm::OPCODE::VQRSHLuv4i32) + .value("VQRSHLuv8i16", LIEF::assembly::arm::OPCODE::VQRSHLuv8i16) + .value("VQRSHLuv8i8", LIEF::assembly::arm::OPCODE::VQRSHLuv8i8) + .value("VQRSHRNsv2i32", LIEF::assembly::arm::OPCODE::VQRSHRNsv2i32) + .value("VQRSHRNsv4i16", LIEF::assembly::arm::OPCODE::VQRSHRNsv4i16) + .value("VQRSHRNsv8i8", LIEF::assembly::arm::OPCODE::VQRSHRNsv8i8) + .value("VQRSHRNuv2i32", LIEF::assembly::arm::OPCODE::VQRSHRNuv2i32) + .value("VQRSHRNuv4i16", LIEF::assembly::arm::OPCODE::VQRSHRNuv4i16) + .value("VQRSHRNuv8i8", LIEF::assembly::arm::OPCODE::VQRSHRNuv8i8) + .value("VQRSHRUNv2i32", LIEF::assembly::arm::OPCODE::VQRSHRUNv2i32) + .value("VQRSHRUNv4i16", LIEF::assembly::arm::OPCODE::VQRSHRUNv4i16) + .value("VQRSHRUNv8i8", LIEF::assembly::arm::OPCODE::VQRSHRUNv8i8) + .value("VQSHLsiv16i8", LIEF::assembly::arm::OPCODE::VQSHLsiv16i8) + .value("VQSHLsiv1i64", LIEF::assembly::arm::OPCODE::VQSHLsiv1i64) + .value("VQSHLsiv2i32", LIEF::assembly::arm::OPCODE::VQSHLsiv2i32) + .value("VQSHLsiv2i64", LIEF::assembly::arm::OPCODE::VQSHLsiv2i64) + .value("VQSHLsiv4i16", LIEF::assembly::arm::OPCODE::VQSHLsiv4i16) + .value("VQSHLsiv4i32", LIEF::assembly::arm::OPCODE::VQSHLsiv4i32) + .value("VQSHLsiv8i16", LIEF::assembly::arm::OPCODE::VQSHLsiv8i16) + .value("VQSHLsiv8i8", LIEF::assembly::arm::OPCODE::VQSHLsiv8i8); + opcodes.value("VQSHLsuv16i8", LIEF::assembly::arm::OPCODE::VQSHLsuv16i8) + .value("VQSHLsuv1i64", LIEF::assembly::arm::OPCODE::VQSHLsuv1i64) + .value("VQSHLsuv2i32", LIEF::assembly::arm::OPCODE::VQSHLsuv2i32) + .value("VQSHLsuv2i64", LIEF::assembly::arm::OPCODE::VQSHLsuv2i64) + .value("VQSHLsuv4i16", LIEF::assembly::arm::OPCODE::VQSHLsuv4i16) + .value("VQSHLsuv4i32", LIEF::assembly::arm::OPCODE::VQSHLsuv4i32) + .value("VQSHLsuv8i16", LIEF::assembly::arm::OPCODE::VQSHLsuv8i16) + .value("VQSHLsuv8i8", LIEF::assembly::arm::OPCODE::VQSHLsuv8i8) + .value("VQSHLsv16i8", LIEF::assembly::arm::OPCODE::VQSHLsv16i8) + .value("VQSHLsv1i64", LIEF::assembly::arm::OPCODE::VQSHLsv1i64) + .value("VQSHLsv2i32", LIEF::assembly::arm::OPCODE::VQSHLsv2i32) + .value("VQSHLsv2i64", LIEF::assembly::arm::OPCODE::VQSHLsv2i64) + .value("VQSHLsv4i16", LIEF::assembly::arm::OPCODE::VQSHLsv4i16) + .value("VQSHLsv4i32", LIEF::assembly::arm::OPCODE::VQSHLsv4i32) + .value("VQSHLsv8i16", LIEF::assembly::arm::OPCODE::VQSHLsv8i16) + .value("VQSHLsv8i8", LIEF::assembly::arm::OPCODE::VQSHLsv8i8) + .value("VQSHLuiv16i8", LIEF::assembly::arm::OPCODE::VQSHLuiv16i8) + .value("VQSHLuiv1i64", LIEF::assembly::arm::OPCODE::VQSHLuiv1i64) + .value("VQSHLuiv2i32", LIEF::assembly::arm::OPCODE::VQSHLuiv2i32) + .value("VQSHLuiv2i64", LIEF::assembly::arm::OPCODE::VQSHLuiv2i64) + .value("VQSHLuiv4i16", LIEF::assembly::arm::OPCODE::VQSHLuiv4i16) + .value("VQSHLuiv4i32", LIEF::assembly::arm::OPCODE::VQSHLuiv4i32) + .value("VQSHLuiv8i16", LIEF::assembly::arm::OPCODE::VQSHLuiv8i16) + .value("VQSHLuiv8i8", LIEF::assembly::arm::OPCODE::VQSHLuiv8i8) + .value("VQSHLuv16i8", LIEF::assembly::arm::OPCODE::VQSHLuv16i8) + .value("VQSHLuv1i64", LIEF::assembly::arm::OPCODE::VQSHLuv1i64) + .value("VQSHLuv2i32", LIEF::assembly::arm::OPCODE::VQSHLuv2i32) + .value("VQSHLuv2i64", LIEF::assembly::arm::OPCODE::VQSHLuv2i64) + .value("VQSHLuv4i16", LIEF::assembly::arm::OPCODE::VQSHLuv4i16) + .value("VQSHLuv4i32", LIEF::assembly::arm::OPCODE::VQSHLuv4i32) + .value("VQSHLuv8i16", LIEF::assembly::arm::OPCODE::VQSHLuv8i16) + .value("VQSHLuv8i8", LIEF::assembly::arm::OPCODE::VQSHLuv8i8) + .value("VQSHRNsv2i32", LIEF::assembly::arm::OPCODE::VQSHRNsv2i32) + .value("VQSHRNsv4i16", LIEF::assembly::arm::OPCODE::VQSHRNsv4i16) + .value("VQSHRNsv8i8", LIEF::assembly::arm::OPCODE::VQSHRNsv8i8) + .value("VQSHRNuv2i32", LIEF::assembly::arm::OPCODE::VQSHRNuv2i32) + .value("VQSHRNuv4i16", LIEF::assembly::arm::OPCODE::VQSHRNuv4i16) + .value("VQSHRNuv8i8", LIEF::assembly::arm::OPCODE::VQSHRNuv8i8) + .value("VQSHRUNv2i32", LIEF::assembly::arm::OPCODE::VQSHRUNv2i32) + .value("VQSHRUNv4i16", LIEF::assembly::arm::OPCODE::VQSHRUNv4i16) + .value("VQSHRUNv8i8", LIEF::assembly::arm::OPCODE::VQSHRUNv8i8) + .value("VQSUBsv16i8", LIEF::assembly::arm::OPCODE::VQSUBsv16i8) + .value("VQSUBsv1i64", LIEF::assembly::arm::OPCODE::VQSUBsv1i64) + .value("VQSUBsv2i32", LIEF::assembly::arm::OPCODE::VQSUBsv2i32) + .value("VQSUBsv2i64", LIEF::assembly::arm::OPCODE::VQSUBsv2i64) + .value("VQSUBsv4i16", LIEF::assembly::arm::OPCODE::VQSUBsv4i16) + .value("VQSUBsv4i32", LIEF::assembly::arm::OPCODE::VQSUBsv4i32) + .value("VQSUBsv8i16", LIEF::assembly::arm::OPCODE::VQSUBsv8i16) + .value("VQSUBsv8i8", LIEF::assembly::arm::OPCODE::VQSUBsv8i8) + .value("VQSUBuv16i8", LIEF::assembly::arm::OPCODE::VQSUBuv16i8) + .value("VQSUBuv1i64", LIEF::assembly::arm::OPCODE::VQSUBuv1i64) + .value("VQSUBuv2i32", LIEF::assembly::arm::OPCODE::VQSUBuv2i32) + .value("VQSUBuv2i64", LIEF::assembly::arm::OPCODE::VQSUBuv2i64) + .value("VQSUBuv4i16", LIEF::assembly::arm::OPCODE::VQSUBuv4i16) + .value("VQSUBuv4i32", LIEF::assembly::arm::OPCODE::VQSUBuv4i32) + .value("VQSUBuv8i16", LIEF::assembly::arm::OPCODE::VQSUBuv8i16) + .value("VQSUBuv8i8", LIEF::assembly::arm::OPCODE::VQSUBuv8i8) + .value("VRADDHNv2i32", LIEF::assembly::arm::OPCODE::VRADDHNv2i32) + .value("VRADDHNv4i16", LIEF::assembly::arm::OPCODE::VRADDHNv4i16) + .value("VRADDHNv8i8", LIEF::assembly::arm::OPCODE::VRADDHNv8i8) + .value("VRECPEd", LIEF::assembly::arm::OPCODE::VRECPEd) + .value("VRECPEfd", LIEF::assembly::arm::OPCODE::VRECPEfd) + .value("VRECPEfq", LIEF::assembly::arm::OPCODE::VRECPEfq) + .value("VRECPEhd", LIEF::assembly::arm::OPCODE::VRECPEhd) + .value("VRECPEhq", LIEF::assembly::arm::OPCODE::VRECPEhq) + .value("VRECPEq", LIEF::assembly::arm::OPCODE::VRECPEq) + .value("VRECPSfd", LIEF::assembly::arm::OPCODE::VRECPSfd) + .value("VRECPSfq", LIEF::assembly::arm::OPCODE::VRECPSfq) + .value("VRECPShd", LIEF::assembly::arm::OPCODE::VRECPShd) + .value("VRECPShq", LIEF::assembly::arm::OPCODE::VRECPShq) + .value("VREV16d8", LIEF::assembly::arm::OPCODE::VREV16d8) + .value("VREV16q8", LIEF::assembly::arm::OPCODE::VREV16q8) + .value("VREV32d16", LIEF::assembly::arm::OPCODE::VREV32d16) + .value("VREV32d8", LIEF::assembly::arm::OPCODE::VREV32d8) + .value("VREV32q16", LIEF::assembly::arm::OPCODE::VREV32q16) + .value("VREV32q8", LIEF::assembly::arm::OPCODE::VREV32q8) + .value("VREV64d16", LIEF::assembly::arm::OPCODE::VREV64d16) + .value("VREV64d32", LIEF::assembly::arm::OPCODE::VREV64d32) + .value("VREV64d8", LIEF::assembly::arm::OPCODE::VREV64d8) + .value("VREV64q16", LIEF::assembly::arm::OPCODE::VREV64q16) + .value("VREV64q32", LIEF::assembly::arm::OPCODE::VREV64q32) + .value("VREV64q8", LIEF::assembly::arm::OPCODE::VREV64q8) + .value("VRHADDsv16i8", LIEF::assembly::arm::OPCODE::VRHADDsv16i8) + .value("VRHADDsv2i32", LIEF::assembly::arm::OPCODE::VRHADDsv2i32) + .value("VRHADDsv4i16", LIEF::assembly::arm::OPCODE::VRHADDsv4i16) + .value("VRHADDsv4i32", LIEF::assembly::arm::OPCODE::VRHADDsv4i32) + .value("VRHADDsv8i16", LIEF::assembly::arm::OPCODE::VRHADDsv8i16) + .value("VRHADDsv8i8", LIEF::assembly::arm::OPCODE::VRHADDsv8i8) + .value("VRHADDuv16i8", LIEF::assembly::arm::OPCODE::VRHADDuv16i8) + .value("VRHADDuv2i32", LIEF::assembly::arm::OPCODE::VRHADDuv2i32) + .value("VRHADDuv4i16", LIEF::assembly::arm::OPCODE::VRHADDuv4i16) + .value("VRHADDuv4i32", LIEF::assembly::arm::OPCODE::VRHADDuv4i32) + .value("VRHADDuv8i16", LIEF::assembly::arm::OPCODE::VRHADDuv8i16) + .value("VRHADDuv8i8", LIEF::assembly::arm::OPCODE::VRHADDuv8i8) + .value("VRINTAD", LIEF::assembly::arm::OPCODE::VRINTAD) + .value("VRINTAH", LIEF::assembly::arm::OPCODE::VRINTAH) + .value("VRINTANDf", LIEF::assembly::arm::OPCODE::VRINTANDf) + .value("VRINTANDh", LIEF::assembly::arm::OPCODE::VRINTANDh) + .value("VRINTANQf", LIEF::assembly::arm::OPCODE::VRINTANQf) + .value("VRINTANQh", LIEF::assembly::arm::OPCODE::VRINTANQh) + .value("VRINTAS", LIEF::assembly::arm::OPCODE::VRINTAS) + .value("VRINTMD", LIEF::assembly::arm::OPCODE::VRINTMD) + .value("VRINTMH", LIEF::assembly::arm::OPCODE::VRINTMH) + .value("VRINTMNDf", LIEF::assembly::arm::OPCODE::VRINTMNDf) + .value("VRINTMNDh", LIEF::assembly::arm::OPCODE::VRINTMNDh) + .value("VRINTMNQf", LIEF::assembly::arm::OPCODE::VRINTMNQf) + .value("VRINTMNQh", LIEF::assembly::arm::OPCODE::VRINTMNQh) + .value("VRINTMS", LIEF::assembly::arm::OPCODE::VRINTMS) + .value("VRINTND", LIEF::assembly::arm::OPCODE::VRINTND) + .value("VRINTNH", LIEF::assembly::arm::OPCODE::VRINTNH) + .value("VRINTNNDf", LIEF::assembly::arm::OPCODE::VRINTNNDf) + .value("VRINTNNDh", LIEF::assembly::arm::OPCODE::VRINTNNDh) + .value("VRINTNNQf", LIEF::assembly::arm::OPCODE::VRINTNNQf) + .value("VRINTNNQh", LIEF::assembly::arm::OPCODE::VRINTNNQh) + .value("VRINTNS", LIEF::assembly::arm::OPCODE::VRINTNS) + .value("VRINTPD", LIEF::assembly::arm::OPCODE::VRINTPD) + .value("VRINTPH", LIEF::assembly::arm::OPCODE::VRINTPH) + .value("VRINTPNDf", LIEF::assembly::arm::OPCODE::VRINTPNDf) + .value("VRINTPNDh", LIEF::assembly::arm::OPCODE::VRINTPNDh) + .value("VRINTPNQf", LIEF::assembly::arm::OPCODE::VRINTPNQf) + .value("VRINTPNQh", LIEF::assembly::arm::OPCODE::VRINTPNQh) + .value("VRINTPS", LIEF::assembly::arm::OPCODE::VRINTPS) + .value("VRINTRD", LIEF::assembly::arm::OPCODE::VRINTRD) + .value("VRINTRH", LIEF::assembly::arm::OPCODE::VRINTRH) + .value("VRINTRS", LIEF::assembly::arm::OPCODE::VRINTRS) + .value("VRINTXD", LIEF::assembly::arm::OPCODE::VRINTXD) + .value("VRINTXH", LIEF::assembly::arm::OPCODE::VRINTXH) + .value("VRINTXNDf", LIEF::assembly::arm::OPCODE::VRINTXNDf) + .value("VRINTXNDh", LIEF::assembly::arm::OPCODE::VRINTXNDh) + .value("VRINTXNQf", LIEF::assembly::arm::OPCODE::VRINTXNQf) + .value("VRINTXNQh", LIEF::assembly::arm::OPCODE::VRINTXNQh) + .value("VRINTXS", LIEF::assembly::arm::OPCODE::VRINTXS) + .value("VRINTZD", LIEF::assembly::arm::OPCODE::VRINTZD) + .value("VRINTZH", LIEF::assembly::arm::OPCODE::VRINTZH) + .value("VRINTZNDf", LIEF::assembly::arm::OPCODE::VRINTZNDf) + .value("VRINTZNDh", LIEF::assembly::arm::OPCODE::VRINTZNDh) + .value("VRINTZNQf", LIEF::assembly::arm::OPCODE::VRINTZNQf) + .value("VRINTZNQh", LIEF::assembly::arm::OPCODE::VRINTZNQh) + .value("VRINTZS", LIEF::assembly::arm::OPCODE::VRINTZS) + .value("VRSHLsv16i8", LIEF::assembly::arm::OPCODE::VRSHLsv16i8) + .value("VRSHLsv1i64", LIEF::assembly::arm::OPCODE::VRSHLsv1i64) + .value("VRSHLsv2i32", LIEF::assembly::arm::OPCODE::VRSHLsv2i32) + .value("VRSHLsv2i64", LIEF::assembly::arm::OPCODE::VRSHLsv2i64) + .value("VRSHLsv4i16", LIEF::assembly::arm::OPCODE::VRSHLsv4i16) + .value("VRSHLsv4i32", LIEF::assembly::arm::OPCODE::VRSHLsv4i32) + .value("VRSHLsv8i16", LIEF::assembly::arm::OPCODE::VRSHLsv8i16) + .value("VRSHLsv8i8", LIEF::assembly::arm::OPCODE::VRSHLsv8i8) + .value("VRSHLuv16i8", LIEF::assembly::arm::OPCODE::VRSHLuv16i8) + .value("VRSHLuv1i64", LIEF::assembly::arm::OPCODE::VRSHLuv1i64) + .value("VRSHLuv2i32", LIEF::assembly::arm::OPCODE::VRSHLuv2i32) + .value("VRSHLuv2i64", LIEF::assembly::arm::OPCODE::VRSHLuv2i64) + .value("VRSHLuv4i16", LIEF::assembly::arm::OPCODE::VRSHLuv4i16) + .value("VRSHLuv4i32", LIEF::assembly::arm::OPCODE::VRSHLuv4i32) + .value("VRSHLuv8i16", LIEF::assembly::arm::OPCODE::VRSHLuv8i16) + .value("VRSHLuv8i8", LIEF::assembly::arm::OPCODE::VRSHLuv8i8) + .value("VRSHRNv2i32", LIEF::assembly::arm::OPCODE::VRSHRNv2i32) + .value("VRSHRNv4i16", LIEF::assembly::arm::OPCODE::VRSHRNv4i16) + .value("VRSHRNv8i8", LIEF::assembly::arm::OPCODE::VRSHRNv8i8) + .value("VRSHRsv16i8", LIEF::assembly::arm::OPCODE::VRSHRsv16i8) + .value("VRSHRsv1i64", LIEF::assembly::arm::OPCODE::VRSHRsv1i64) + .value("VRSHRsv2i32", LIEF::assembly::arm::OPCODE::VRSHRsv2i32) + .value("VRSHRsv2i64", LIEF::assembly::arm::OPCODE::VRSHRsv2i64) + .value("VRSHRsv4i16", LIEF::assembly::arm::OPCODE::VRSHRsv4i16) + .value("VRSHRsv4i32", LIEF::assembly::arm::OPCODE::VRSHRsv4i32) + .value("VRSHRsv8i16", LIEF::assembly::arm::OPCODE::VRSHRsv8i16) + .value("VRSHRsv8i8", LIEF::assembly::arm::OPCODE::VRSHRsv8i8) + .value("VRSHRuv16i8", LIEF::assembly::arm::OPCODE::VRSHRuv16i8) + .value("VRSHRuv1i64", LIEF::assembly::arm::OPCODE::VRSHRuv1i64) + .value("VRSHRuv2i32", LIEF::assembly::arm::OPCODE::VRSHRuv2i32) + .value("VRSHRuv2i64", LIEF::assembly::arm::OPCODE::VRSHRuv2i64) + .value("VRSHRuv4i16", LIEF::assembly::arm::OPCODE::VRSHRuv4i16) + .value("VRSHRuv4i32", LIEF::assembly::arm::OPCODE::VRSHRuv4i32) + .value("VRSHRuv8i16", LIEF::assembly::arm::OPCODE::VRSHRuv8i16) + .value("VRSHRuv8i8", LIEF::assembly::arm::OPCODE::VRSHRuv8i8) + .value("VRSQRTEd", LIEF::assembly::arm::OPCODE::VRSQRTEd) + .value("VRSQRTEfd", LIEF::assembly::arm::OPCODE::VRSQRTEfd) + .value("VRSQRTEfq", LIEF::assembly::arm::OPCODE::VRSQRTEfq) + .value("VRSQRTEhd", LIEF::assembly::arm::OPCODE::VRSQRTEhd) + .value("VRSQRTEhq", LIEF::assembly::arm::OPCODE::VRSQRTEhq) + .value("VRSQRTEq", LIEF::assembly::arm::OPCODE::VRSQRTEq) + .value("VRSQRTSfd", LIEF::assembly::arm::OPCODE::VRSQRTSfd) + .value("VRSQRTSfq", LIEF::assembly::arm::OPCODE::VRSQRTSfq) + .value("VRSQRTShd", LIEF::assembly::arm::OPCODE::VRSQRTShd) + .value("VRSQRTShq", LIEF::assembly::arm::OPCODE::VRSQRTShq) + .value("VRSRAsv16i8", LIEF::assembly::arm::OPCODE::VRSRAsv16i8) + .value("VRSRAsv1i64", LIEF::assembly::arm::OPCODE::VRSRAsv1i64) + .value("VRSRAsv2i32", LIEF::assembly::arm::OPCODE::VRSRAsv2i32) + .value("VRSRAsv2i64", LIEF::assembly::arm::OPCODE::VRSRAsv2i64) + .value("VRSRAsv4i16", LIEF::assembly::arm::OPCODE::VRSRAsv4i16) + .value("VRSRAsv4i32", LIEF::assembly::arm::OPCODE::VRSRAsv4i32) + .value("VRSRAsv8i16", LIEF::assembly::arm::OPCODE::VRSRAsv8i16) + .value("VRSRAsv8i8", LIEF::assembly::arm::OPCODE::VRSRAsv8i8) + .value("VRSRAuv16i8", LIEF::assembly::arm::OPCODE::VRSRAuv16i8) + .value("VRSRAuv1i64", LIEF::assembly::arm::OPCODE::VRSRAuv1i64) + .value("VRSRAuv2i32", LIEF::assembly::arm::OPCODE::VRSRAuv2i32) + .value("VRSRAuv2i64", LIEF::assembly::arm::OPCODE::VRSRAuv2i64) + .value("VRSRAuv4i16", LIEF::assembly::arm::OPCODE::VRSRAuv4i16) + .value("VRSRAuv4i32", LIEF::assembly::arm::OPCODE::VRSRAuv4i32) + .value("VRSRAuv8i16", LIEF::assembly::arm::OPCODE::VRSRAuv8i16) + .value("VRSRAuv8i8", LIEF::assembly::arm::OPCODE::VRSRAuv8i8) + .value("VRSUBHNv2i32", LIEF::assembly::arm::OPCODE::VRSUBHNv2i32) + .value("VRSUBHNv4i16", LIEF::assembly::arm::OPCODE::VRSUBHNv4i16) + .value("VRSUBHNv8i8", LIEF::assembly::arm::OPCODE::VRSUBHNv8i8) + .value("VSCCLRMD", LIEF::assembly::arm::OPCODE::VSCCLRMD) + .value("VSCCLRMS", LIEF::assembly::arm::OPCODE::VSCCLRMS) + .value("VSDOTD", LIEF::assembly::arm::OPCODE::VSDOTD) + .value("VSDOTDI", LIEF::assembly::arm::OPCODE::VSDOTDI) + .value("VSDOTQ", LIEF::assembly::arm::OPCODE::VSDOTQ) + .value("VSDOTQI", LIEF::assembly::arm::OPCODE::VSDOTQI) + .value("VSELEQD", LIEF::assembly::arm::OPCODE::VSELEQD) + .value("VSELEQH", LIEF::assembly::arm::OPCODE::VSELEQH) + .value("VSELEQS", LIEF::assembly::arm::OPCODE::VSELEQS) + .value("VSELGED", LIEF::assembly::arm::OPCODE::VSELGED) + .value("VSELGEH", LIEF::assembly::arm::OPCODE::VSELGEH) + .value("VSELGES", LIEF::assembly::arm::OPCODE::VSELGES) + .value("VSELGTD", LIEF::assembly::arm::OPCODE::VSELGTD) + .value("VSELGTH", LIEF::assembly::arm::OPCODE::VSELGTH) + .value("VSELGTS", LIEF::assembly::arm::OPCODE::VSELGTS) + .value("VSELVSD", LIEF::assembly::arm::OPCODE::VSELVSD) + .value("VSELVSH", LIEF::assembly::arm::OPCODE::VSELVSH) + .value("VSELVSS", LIEF::assembly::arm::OPCODE::VSELVSS) + .value("VSETLNi16", LIEF::assembly::arm::OPCODE::VSETLNi16) + .value("VSETLNi32", LIEF::assembly::arm::OPCODE::VSETLNi32) + .value("VSETLNi8", LIEF::assembly::arm::OPCODE::VSETLNi8) + .value("VSHLLi16", LIEF::assembly::arm::OPCODE::VSHLLi16) + .value("VSHLLi32", LIEF::assembly::arm::OPCODE::VSHLLi32) + .value("VSHLLi8", LIEF::assembly::arm::OPCODE::VSHLLi8) + .value("VSHLLsv2i64", LIEF::assembly::arm::OPCODE::VSHLLsv2i64) + .value("VSHLLsv4i32", LIEF::assembly::arm::OPCODE::VSHLLsv4i32) + .value("VSHLLsv8i16", LIEF::assembly::arm::OPCODE::VSHLLsv8i16) + .value("VSHLLuv2i64", LIEF::assembly::arm::OPCODE::VSHLLuv2i64) + .value("VSHLLuv4i32", LIEF::assembly::arm::OPCODE::VSHLLuv4i32) + .value("VSHLLuv8i16", LIEF::assembly::arm::OPCODE::VSHLLuv8i16) + .value("VSHLiv16i8", LIEF::assembly::arm::OPCODE::VSHLiv16i8) + .value("VSHLiv1i64", LIEF::assembly::arm::OPCODE::VSHLiv1i64) + .value("VSHLiv2i32", LIEF::assembly::arm::OPCODE::VSHLiv2i32) + .value("VSHLiv2i64", LIEF::assembly::arm::OPCODE::VSHLiv2i64) + .value("VSHLiv4i16", LIEF::assembly::arm::OPCODE::VSHLiv4i16) + .value("VSHLiv4i32", LIEF::assembly::arm::OPCODE::VSHLiv4i32) + .value("VSHLiv8i16", LIEF::assembly::arm::OPCODE::VSHLiv8i16) + .value("VSHLiv8i8", LIEF::assembly::arm::OPCODE::VSHLiv8i8) + .value("VSHLsv16i8", LIEF::assembly::arm::OPCODE::VSHLsv16i8) + .value("VSHLsv1i64", LIEF::assembly::arm::OPCODE::VSHLsv1i64) + .value("VSHLsv2i32", LIEF::assembly::arm::OPCODE::VSHLsv2i32) + .value("VSHLsv2i64", LIEF::assembly::arm::OPCODE::VSHLsv2i64) + .value("VSHLsv4i16", LIEF::assembly::arm::OPCODE::VSHLsv4i16) + .value("VSHLsv4i32", LIEF::assembly::arm::OPCODE::VSHLsv4i32) + .value("VSHLsv8i16", LIEF::assembly::arm::OPCODE::VSHLsv8i16) + .value("VSHLsv8i8", LIEF::assembly::arm::OPCODE::VSHLsv8i8) + .value("VSHLuv16i8", LIEF::assembly::arm::OPCODE::VSHLuv16i8) + .value("VSHLuv1i64", LIEF::assembly::arm::OPCODE::VSHLuv1i64) + .value("VSHLuv2i32", LIEF::assembly::arm::OPCODE::VSHLuv2i32) + .value("VSHLuv2i64", LIEF::assembly::arm::OPCODE::VSHLuv2i64) + .value("VSHLuv4i16", LIEF::assembly::arm::OPCODE::VSHLuv4i16) + .value("VSHLuv4i32", LIEF::assembly::arm::OPCODE::VSHLuv4i32) + .value("VSHLuv8i16", LIEF::assembly::arm::OPCODE::VSHLuv8i16) + .value("VSHLuv8i8", LIEF::assembly::arm::OPCODE::VSHLuv8i8) + .value("VSHRNv2i32", LIEF::assembly::arm::OPCODE::VSHRNv2i32) + .value("VSHRNv4i16", LIEF::assembly::arm::OPCODE::VSHRNv4i16) + .value("VSHRNv8i8", LIEF::assembly::arm::OPCODE::VSHRNv8i8) + .value("VSHRsv16i8", LIEF::assembly::arm::OPCODE::VSHRsv16i8) + .value("VSHRsv1i64", LIEF::assembly::arm::OPCODE::VSHRsv1i64) + .value("VSHRsv2i32", LIEF::assembly::arm::OPCODE::VSHRsv2i32) + .value("VSHRsv2i64", LIEF::assembly::arm::OPCODE::VSHRsv2i64) + .value("VSHRsv4i16", LIEF::assembly::arm::OPCODE::VSHRsv4i16) + .value("VSHRsv4i32", LIEF::assembly::arm::OPCODE::VSHRsv4i32) + .value("VSHRsv8i16", LIEF::assembly::arm::OPCODE::VSHRsv8i16) + .value("VSHRsv8i8", LIEF::assembly::arm::OPCODE::VSHRsv8i8) + .value("VSHRuv16i8", LIEF::assembly::arm::OPCODE::VSHRuv16i8) + .value("VSHRuv1i64", LIEF::assembly::arm::OPCODE::VSHRuv1i64) + .value("VSHRuv2i32", LIEF::assembly::arm::OPCODE::VSHRuv2i32) + .value("VSHRuv2i64", LIEF::assembly::arm::OPCODE::VSHRuv2i64) + .value("VSHRuv4i16", LIEF::assembly::arm::OPCODE::VSHRuv4i16) + .value("VSHRuv4i32", LIEF::assembly::arm::OPCODE::VSHRuv4i32) + .value("VSHRuv8i16", LIEF::assembly::arm::OPCODE::VSHRuv8i16) + .value("VSHRuv8i8", LIEF::assembly::arm::OPCODE::VSHRuv8i8) + .value("VSHTOD", LIEF::assembly::arm::OPCODE::VSHTOD) + .value("VSHTOH", LIEF::assembly::arm::OPCODE::VSHTOH) + .value("VSHTOS", LIEF::assembly::arm::OPCODE::VSHTOS) + .value("VSITOD", LIEF::assembly::arm::OPCODE::VSITOD) + .value("VSITOH", LIEF::assembly::arm::OPCODE::VSITOH) + .value("VSITOS", LIEF::assembly::arm::OPCODE::VSITOS) + .value("VSLIv16i8", LIEF::assembly::arm::OPCODE::VSLIv16i8) + .value("VSLIv1i64", LIEF::assembly::arm::OPCODE::VSLIv1i64) + .value("VSLIv2i32", LIEF::assembly::arm::OPCODE::VSLIv2i32) + .value("VSLIv2i64", LIEF::assembly::arm::OPCODE::VSLIv2i64) + .value("VSLIv4i16", LIEF::assembly::arm::OPCODE::VSLIv4i16) + .value("VSLIv4i32", LIEF::assembly::arm::OPCODE::VSLIv4i32) + .value("VSLIv8i16", LIEF::assembly::arm::OPCODE::VSLIv8i16) + .value("VSLIv8i8", LIEF::assembly::arm::OPCODE::VSLIv8i8) + .value("VSLTOD", LIEF::assembly::arm::OPCODE::VSLTOD) + .value("VSLTOH", LIEF::assembly::arm::OPCODE::VSLTOH) + .value("VSLTOS", LIEF::assembly::arm::OPCODE::VSLTOS) + .value("VSMMLA", LIEF::assembly::arm::OPCODE::VSMMLA) + .value("VSQRTD", LIEF::assembly::arm::OPCODE::VSQRTD) + .value("VSQRTH", LIEF::assembly::arm::OPCODE::VSQRTH) + .value("VSQRTS", LIEF::assembly::arm::OPCODE::VSQRTS) + .value("VSRAsv16i8", LIEF::assembly::arm::OPCODE::VSRAsv16i8) + .value("VSRAsv1i64", LIEF::assembly::arm::OPCODE::VSRAsv1i64) + .value("VSRAsv2i32", LIEF::assembly::arm::OPCODE::VSRAsv2i32); + opcodes.value("VSRAsv2i64", LIEF::assembly::arm::OPCODE::VSRAsv2i64) + .value("VSRAsv4i16", LIEF::assembly::arm::OPCODE::VSRAsv4i16) + .value("VSRAsv4i32", LIEF::assembly::arm::OPCODE::VSRAsv4i32) + .value("VSRAsv8i16", LIEF::assembly::arm::OPCODE::VSRAsv8i16) + .value("VSRAsv8i8", LIEF::assembly::arm::OPCODE::VSRAsv8i8) + .value("VSRAuv16i8", LIEF::assembly::arm::OPCODE::VSRAuv16i8) + .value("VSRAuv1i64", LIEF::assembly::arm::OPCODE::VSRAuv1i64) + .value("VSRAuv2i32", LIEF::assembly::arm::OPCODE::VSRAuv2i32) + .value("VSRAuv2i64", LIEF::assembly::arm::OPCODE::VSRAuv2i64) + .value("VSRAuv4i16", LIEF::assembly::arm::OPCODE::VSRAuv4i16) + .value("VSRAuv4i32", LIEF::assembly::arm::OPCODE::VSRAuv4i32) + .value("VSRAuv8i16", LIEF::assembly::arm::OPCODE::VSRAuv8i16) + .value("VSRAuv8i8", LIEF::assembly::arm::OPCODE::VSRAuv8i8) + .value("VSRIv16i8", LIEF::assembly::arm::OPCODE::VSRIv16i8) + .value("VSRIv1i64", LIEF::assembly::arm::OPCODE::VSRIv1i64) + .value("VSRIv2i32", LIEF::assembly::arm::OPCODE::VSRIv2i32) + .value("VSRIv2i64", LIEF::assembly::arm::OPCODE::VSRIv2i64) + .value("VSRIv4i16", LIEF::assembly::arm::OPCODE::VSRIv4i16) + .value("VSRIv4i32", LIEF::assembly::arm::OPCODE::VSRIv4i32) + .value("VSRIv8i16", LIEF::assembly::arm::OPCODE::VSRIv8i16) + .value("VSRIv8i8", LIEF::assembly::arm::OPCODE::VSRIv8i8) + .value("VST1LNd16", LIEF::assembly::arm::OPCODE::VST1LNd16) + .value("VST1LNd16_UPD", LIEF::assembly::arm::OPCODE::VST1LNd16_UPD) + .value("VST1LNd32", LIEF::assembly::arm::OPCODE::VST1LNd32) + .value("VST1LNd32_UPD", LIEF::assembly::arm::OPCODE::VST1LNd32_UPD) + .value("VST1LNd8", LIEF::assembly::arm::OPCODE::VST1LNd8) + .value("VST1LNd8_UPD", LIEF::assembly::arm::OPCODE::VST1LNd8_UPD) + .value("VST1LNq16Pseudo", LIEF::assembly::arm::OPCODE::VST1LNq16Pseudo) + .value("VST1LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST1LNq16Pseudo_UPD) + .value("VST1LNq32Pseudo", LIEF::assembly::arm::OPCODE::VST1LNq32Pseudo) + .value("VST1LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST1LNq32Pseudo_UPD) + .value("VST1LNq8Pseudo", LIEF::assembly::arm::OPCODE::VST1LNq8Pseudo) + .value("VST1LNq8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST1LNq8Pseudo_UPD) + .value("VST1d16", LIEF::assembly::arm::OPCODE::VST1d16) + .value("VST1d16Q", LIEF::assembly::arm::OPCODE::VST1d16Q) + .value("VST1d16QPseudo", LIEF::assembly::arm::OPCODE::VST1d16QPseudo) + .value("VST1d16QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d16QPseudoWB_fixed) + .value("VST1d16QPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d16QPseudoWB_register) + .value("VST1d16Qwb_fixed", LIEF::assembly::arm::OPCODE::VST1d16Qwb_fixed) + .value("VST1d16Qwb_register", LIEF::assembly::arm::OPCODE::VST1d16Qwb_register) + .value("VST1d16T", LIEF::assembly::arm::OPCODE::VST1d16T) + .value("VST1d16TPseudo", LIEF::assembly::arm::OPCODE::VST1d16TPseudo) + .value("VST1d16TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d16TPseudoWB_fixed) + .value("VST1d16TPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d16TPseudoWB_register) + .value("VST1d16Twb_fixed", LIEF::assembly::arm::OPCODE::VST1d16Twb_fixed) + .value("VST1d16Twb_register", LIEF::assembly::arm::OPCODE::VST1d16Twb_register) + .value("VST1d16wb_fixed", LIEF::assembly::arm::OPCODE::VST1d16wb_fixed) + .value("VST1d16wb_register", LIEF::assembly::arm::OPCODE::VST1d16wb_register) + .value("VST1d32", LIEF::assembly::arm::OPCODE::VST1d32) + .value("VST1d32Q", LIEF::assembly::arm::OPCODE::VST1d32Q) + .value("VST1d32QPseudo", LIEF::assembly::arm::OPCODE::VST1d32QPseudo) + .value("VST1d32QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d32QPseudoWB_fixed) + .value("VST1d32QPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d32QPseudoWB_register) + .value("VST1d32Qwb_fixed", LIEF::assembly::arm::OPCODE::VST1d32Qwb_fixed) + .value("VST1d32Qwb_register", LIEF::assembly::arm::OPCODE::VST1d32Qwb_register) + .value("VST1d32T", LIEF::assembly::arm::OPCODE::VST1d32T) + .value("VST1d32TPseudo", LIEF::assembly::arm::OPCODE::VST1d32TPseudo) + .value("VST1d32TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d32TPseudoWB_fixed) + .value("VST1d32TPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d32TPseudoWB_register) + .value("VST1d32Twb_fixed", LIEF::assembly::arm::OPCODE::VST1d32Twb_fixed) + .value("VST1d32Twb_register", LIEF::assembly::arm::OPCODE::VST1d32Twb_register) + .value("VST1d32wb_fixed", LIEF::assembly::arm::OPCODE::VST1d32wb_fixed) + .value("VST1d32wb_register", LIEF::assembly::arm::OPCODE::VST1d32wb_register) + .value("VST1d64", LIEF::assembly::arm::OPCODE::VST1d64) + .value("VST1d64Q", LIEF::assembly::arm::OPCODE::VST1d64Q) + .value("VST1d64QPseudo", LIEF::assembly::arm::OPCODE::VST1d64QPseudo) + .value("VST1d64QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d64QPseudoWB_fixed) + .value("VST1d64QPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d64QPseudoWB_register) + .value("VST1d64Qwb_fixed", LIEF::assembly::arm::OPCODE::VST1d64Qwb_fixed) + .value("VST1d64Qwb_register", LIEF::assembly::arm::OPCODE::VST1d64Qwb_register) + .value("VST1d64T", LIEF::assembly::arm::OPCODE::VST1d64T) + .value("VST1d64TPseudo", LIEF::assembly::arm::OPCODE::VST1d64TPseudo) + .value("VST1d64TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d64TPseudoWB_fixed) + .value("VST1d64TPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d64TPseudoWB_register) + .value("VST1d64Twb_fixed", LIEF::assembly::arm::OPCODE::VST1d64Twb_fixed) + .value("VST1d64Twb_register", LIEF::assembly::arm::OPCODE::VST1d64Twb_register) + .value("VST1d64wb_fixed", LIEF::assembly::arm::OPCODE::VST1d64wb_fixed) + .value("VST1d64wb_register", LIEF::assembly::arm::OPCODE::VST1d64wb_register) + .value("VST1d8", LIEF::assembly::arm::OPCODE::VST1d8) + .value("VST1d8Q", LIEF::assembly::arm::OPCODE::VST1d8Q) + .value("VST1d8QPseudo", LIEF::assembly::arm::OPCODE::VST1d8QPseudo) + .value("VST1d8QPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d8QPseudoWB_fixed) + .value("VST1d8QPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d8QPseudoWB_register) + .value("VST1d8Qwb_fixed", LIEF::assembly::arm::OPCODE::VST1d8Qwb_fixed) + .value("VST1d8Qwb_register", LIEF::assembly::arm::OPCODE::VST1d8Qwb_register) + .value("VST1d8T", LIEF::assembly::arm::OPCODE::VST1d8T) + .value("VST1d8TPseudo", LIEF::assembly::arm::OPCODE::VST1d8TPseudo) + .value("VST1d8TPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST1d8TPseudoWB_fixed) + .value("VST1d8TPseudoWB_register", LIEF::assembly::arm::OPCODE::VST1d8TPseudoWB_register) + .value("VST1d8Twb_fixed", LIEF::assembly::arm::OPCODE::VST1d8Twb_fixed) + .value("VST1d8Twb_register", LIEF::assembly::arm::OPCODE::VST1d8Twb_register) + .value("VST1d8wb_fixed", LIEF::assembly::arm::OPCODE::VST1d8wb_fixed) + .value("VST1d8wb_register", LIEF::assembly::arm::OPCODE::VST1d8wb_register) + .value("VST1q16", LIEF::assembly::arm::OPCODE::VST1q16) + .value("VST1q16HighQPseudo", LIEF::assembly::arm::OPCODE::VST1q16HighQPseudo) + .value("VST1q16HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q16HighQPseudo_UPD) + .value("VST1q16HighTPseudo", LIEF::assembly::arm::OPCODE::VST1q16HighTPseudo) + .value("VST1q16HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q16HighTPseudo_UPD) + .value("VST1q16LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q16LowQPseudo_UPD) + .value("VST1q16LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q16LowTPseudo_UPD) + .value("VST1q16wb_fixed", LIEF::assembly::arm::OPCODE::VST1q16wb_fixed) + .value("VST1q16wb_register", LIEF::assembly::arm::OPCODE::VST1q16wb_register) + .value("VST1q32", LIEF::assembly::arm::OPCODE::VST1q32) + .value("VST1q32HighQPseudo", LIEF::assembly::arm::OPCODE::VST1q32HighQPseudo) + .value("VST1q32HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q32HighQPseudo_UPD) + .value("VST1q32HighTPseudo", LIEF::assembly::arm::OPCODE::VST1q32HighTPseudo) + .value("VST1q32HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q32HighTPseudo_UPD) + .value("VST1q32LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q32LowQPseudo_UPD) + .value("VST1q32LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q32LowTPseudo_UPD) + .value("VST1q32wb_fixed", LIEF::assembly::arm::OPCODE::VST1q32wb_fixed) + .value("VST1q32wb_register", LIEF::assembly::arm::OPCODE::VST1q32wb_register) + .value("VST1q64", LIEF::assembly::arm::OPCODE::VST1q64) + .value("VST1q64HighQPseudo", LIEF::assembly::arm::OPCODE::VST1q64HighQPseudo) + .value("VST1q64HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q64HighQPseudo_UPD) + .value("VST1q64HighTPseudo", LIEF::assembly::arm::OPCODE::VST1q64HighTPseudo) + .value("VST1q64HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q64HighTPseudo_UPD) + .value("VST1q64LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q64LowQPseudo_UPD) + .value("VST1q64LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q64LowTPseudo_UPD) + .value("VST1q64wb_fixed", LIEF::assembly::arm::OPCODE::VST1q64wb_fixed) + .value("VST1q64wb_register", LIEF::assembly::arm::OPCODE::VST1q64wb_register) + .value("VST1q8", LIEF::assembly::arm::OPCODE::VST1q8) + .value("VST1q8HighQPseudo", LIEF::assembly::arm::OPCODE::VST1q8HighQPseudo) + .value("VST1q8HighQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q8HighQPseudo_UPD) + .value("VST1q8HighTPseudo", LIEF::assembly::arm::OPCODE::VST1q8HighTPseudo) + .value("VST1q8HighTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q8HighTPseudo_UPD) + .value("VST1q8LowQPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q8LowQPseudo_UPD) + .value("VST1q8LowTPseudo_UPD", LIEF::assembly::arm::OPCODE::VST1q8LowTPseudo_UPD) + .value("VST1q8wb_fixed", LIEF::assembly::arm::OPCODE::VST1q8wb_fixed) + .value("VST1q8wb_register", LIEF::assembly::arm::OPCODE::VST1q8wb_register) + .value("VST2LNd16", LIEF::assembly::arm::OPCODE::VST2LNd16) + .value("VST2LNd16Pseudo", LIEF::assembly::arm::OPCODE::VST2LNd16Pseudo) + .value("VST2LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST2LNd16Pseudo_UPD) + .value("VST2LNd16_UPD", LIEF::assembly::arm::OPCODE::VST2LNd16_UPD) + .value("VST2LNd32", LIEF::assembly::arm::OPCODE::VST2LNd32) + .value("VST2LNd32Pseudo", LIEF::assembly::arm::OPCODE::VST2LNd32Pseudo) + .value("VST2LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST2LNd32Pseudo_UPD) + .value("VST2LNd32_UPD", LIEF::assembly::arm::OPCODE::VST2LNd32_UPD) + .value("VST2LNd8", LIEF::assembly::arm::OPCODE::VST2LNd8) + .value("VST2LNd8Pseudo", LIEF::assembly::arm::OPCODE::VST2LNd8Pseudo) + .value("VST2LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST2LNd8Pseudo_UPD) + .value("VST2LNd8_UPD", LIEF::assembly::arm::OPCODE::VST2LNd8_UPD) + .value("VST2LNq16", LIEF::assembly::arm::OPCODE::VST2LNq16) + .value("VST2LNq16Pseudo", LIEF::assembly::arm::OPCODE::VST2LNq16Pseudo) + .value("VST2LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST2LNq16Pseudo_UPD) + .value("VST2LNq16_UPD", LIEF::assembly::arm::OPCODE::VST2LNq16_UPD) + .value("VST2LNq32", LIEF::assembly::arm::OPCODE::VST2LNq32) + .value("VST2LNq32Pseudo", LIEF::assembly::arm::OPCODE::VST2LNq32Pseudo) + .value("VST2LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST2LNq32Pseudo_UPD) + .value("VST2LNq32_UPD", LIEF::assembly::arm::OPCODE::VST2LNq32_UPD) + .value("VST2b16", LIEF::assembly::arm::OPCODE::VST2b16) + .value("VST2b16wb_fixed", LIEF::assembly::arm::OPCODE::VST2b16wb_fixed) + .value("VST2b16wb_register", LIEF::assembly::arm::OPCODE::VST2b16wb_register) + .value("VST2b32", LIEF::assembly::arm::OPCODE::VST2b32) + .value("VST2b32wb_fixed", LIEF::assembly::arm::OPCODE::VST2b32wb_fixed) + .value("VST2b32wb_register", LIEF::assembly::arm::OPCODE::VST2b32wb_register) + .value("VST2b8", LIEF::assembly::arm::OPCODE::VST2b8) + .value("VST2b8wb_fixed", LIEF::assembly::arm::OPCODE::VST2b8wb_fixed) + .value("VST2b8wb_register", LIEF::assembly::arm::OPCODE::VST2b8wb_register) + .value("VST2d16", LIEF::assembly::arm::OPCODE::VST2d16) + .value("VST2d16wb_fixed", LIEF::assembly::arm::OPCODE::VST2d16wb_fixed) + .value("VST2d16wb_register", LIEF::assembly::arm::OPCODE::VST2d16wb_register) + .value("VST2d32", LIEF::assembly::arm::OPCODE::VST2d32) + .value("VST2d32wb_fixed", LIEF::assembly::arm::OPCODE::VST2d32wb_fixed) + .value("VST2d32wb_register", LIEF::assembly::arm::OPCODE::VST2d32wb_register) + .value("VST2d8", LIEF::assembly::arm::OPCODE::VST2d8) + .value("VST2d8wb_fixed", LIEF::assembly::arm::OPCODE::VST2d8wb_fixed) + .value("VST2d8wb_register", LIEF::assembly::arm::OPCODE::VST2d8wb_register) + .value("VST2q16", LIEF::assembly::arm::OPCODE::VST2q16) + .value("VST2q16Pseudo", LIEF::assembly::arm::OPCODE::VST2q16Pseudo) + .value("VST2q16PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST2q16PseudoWB_fixed) + .value("VST2q16PseudoWB_register", LIEF::assembly::arm::OPCODE::VST2q16PseudoWB_register) + .value("VST2q16wb_fixed", LIEF::assembly::arm::OPCODE::VST2q16wb_fixed) + .value("VST2q16wb_register", LIEF::assembly::arm::OPCODE::VST2q16wb_register) + .value("VST2q32", LIEF::assembly::arm::OPCODE::VST2q32) + .value("VST2q32Pseudo", LIEF::assembly::arm::OPCODE::VST2q32Pseudo) + .value("VST2q32PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST2q32PseudoWB_fixed) + .value("VST2q32PseudoWB_register", LIEF::assembly::arm::OPCODE::VST2q32PseudoWB_register) + .value("VST2q32wb_fixed", LIEF::assembly::arm::OPCODE::VST2q32wb_fixed) + .value("VST2q32wb_register", LIEF::assembly::arm::OPCODE::VST2q32wb_register) + .value("VST2q8", LIEF::assembly::arm::OPCODE::VST2q8) + .value("VST2q8Pseudo", LIEF::assembly::arm::OPCODE::VST2q8Pseudo) + .value("VST2q8PseudoWB_fixed", LIEF::assembly::arm::OPCODE::VST2q8PseudoWB_fixed) + .value("VST2q8PseudoWB_register", LIEF::assembly::arm::OPCODE::VST2q8PseudoWB_register) + .value("VST2q8wb_fixed", LIEF::assembly::arm::OPCODE::VST2q8wb_fixed) + .value("VST2q8wb_register", LIEF::assembly::arm::OPCODE::VST2q8wb_register) + .value("VST3LNd16", LIEF::assembly::arm::OPCODE::VST3LNd16) + .value("VST3LNd16Pseudo", LIEF::assembly::arm::OPCODE::VST3LNd16Pseudo) + .value("VST3LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3LNd16Pseudo_UPD) + .value("VST3LNd16_UPD", LIEF::assembly::arm::OPCODE::VST3LNd16_UPD) + .value("VST3LNd32", LIEF::assembly::arm::OPCODE::VST3LNd32) + .value("VST3LNd32Pseudo", LIEF::assembly::arm::OPCODE::VST3LNd32Pseudo) + .value("VST3LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3LNd32Pseudo_UPD) + .value("VST3LNd32_UPD", LIEF::assembly::arm::OPCODE::VST3LNd32_UPD) + .value("VST3LNd8", LIEF::assembly::arm::OPCODE::VST3LNd8) + .value("VST3LNd8Pseudo", LIEF::assembly::arm::OPCODE::VST3LNd8Pseudo) + .value("VST3LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3LNd8Pseudo_UPD) + .value("VST3LNd8_UPD", LIEF::assembly::arm::OPCODE::VST3LNd8_UPD) + .value("VST3LNq16", LIEF::assembly::arm::OPCODE::VST3LNq16) + .value("VST3LNq16Pseudo", LIEF::assembly::arm::OPCODE::VST3LNq16Pseudo) + .value("VST3LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3LNq16Pseudo_UPD) + .value("VST3LNq16_UPD", LIEF::assembly::arm::OPCODE::VST3LNq16_UPD) + .value("VST3LNq32", LIEF::assembly::arm::OPCODE::VST3LNq32) + .value("VST3LNq32Pseudo", LIEF::assembly::arm::OPCODE::VST3LNq32Pseudo) + .value("VST3LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3LNq32Pseudo_UPD) + .value("VST3LNq32_UPD", LIEF::assembly::arm::OPCODE::VST3LNq32_UPD) + .value("VST3d16", LIEF::assembly::arm::OPCODE::VST3d16) + .value("VST3d16Pseudo", LIEF::assembly::arm::OPCODE::VST3d16Pseudo) + .value("VST3d16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3d16Pseudo_UPD) + .value("VST3d16_UPD", LIEF::assembly::arm::OPCODE::VST3d16_UPD) + .value("VST3d32", LIEF::assembly::arm::OPCODE::VST3d32) + .value("VST3d32Pseudo", LIEF::assembly::arm::OPCODE::VST3d32Pseudo) + .value("VST3d32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3d32Pseudo_UPD) + .value("VST3d32_UPD", LIEF::assembly::arm::OPCODE::VST3d32_UPD) + .value("VST3d8", LIEF::assembly::arm::OPCODE::VST3d8) + .value("VST3d8Pseudo", LIEF::assembly::arm::OPCODE::VST3d8Pseudo) + .value("VST3d8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3d8Pseudo_UPD) + .value("VST3d8_UPD", LIEF::assembly::arm::OPCODE::VST3d8_UPD) + .value("VST3q16", LIEF::assembly::arm::OPCODE::VST3q16) + .value("VST3q16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q16Pseudo_UPD) + .value("VST3q16_UPD", LIEF::assembly::arm::OPCODE::VST3q16_UPD) + .value("VST3q16oddPseudo", LIEF::assembly::arm::OPCODE::VST3q16oddPseudo) + .value("VST3q16oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q16oddPseudo_UPD) + .value("VST3q32", LIEF::assembly::arm::OPCODE::VST3q32) + .value("VST3q32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q32Pseudo_UPD) + .value("VST3q32_UPD", LIEF::assembly::arm::OPCODE::VST3q32_UPD) + .value("VST3q32oddPseudo", LIEF::assembly::arm::OPCODE::VST3q32oddPseudo) + .value("VST3q32oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q32oddPseudo_UPD) + .value("VST3q8", LIEF::assembly::arm::OPCODE::VST3q8) + .value("VST3q8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q8Pseudo_UPD) + .value("VST3q8_UPD", LIEF::assembly::arm::OPCODE::VST3q8_UPD) + .value("VST3q8oddPseudo", LIEF::assembly::arm::OPCODE::VST3q8oddPseudo) + .value("VST3q8oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST3q8oddPseudo_UPD) + .value("VST4LNd16", LIEF::assembly::arm::OPCODE::VST4LNd16) + .value("VST4LNd16Pseudo", LIEF::assembly::arm::OPCODE::VST4LNd16Pseudo) + .value("VST4LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4LNd16Pseudo_UPD) + .value("VST4LNd16_UPD", LIEF::assembly::arm::OPCODE::VST4LNd16_UPD) + .value("VST4LNd32", LIEF::assembly::arm::OPCODE::VST4LNd32) + .value("VST4LNd32Pseudo", LIEF::assembly::arm::OPCODE::VST4LNd32Pseudo) + .value("VST4LNd32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4LNd32Pseudo_UPD) + .value("VST4LNd32_UPD", LIEF::assembly::arm::OPCODE::VST4LNd32_UPD) + .value("VST4LNd8", LIEF::assembly::arm::OPCODE::VST4LNd8) + .value("VST4LNd8Pseudo", LIEF::assembly::arm::OPCODE::VST4LNd8Pseudo) + .value("VST4LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4LNd8Pseudo_UPD) + .value("VST4LNd8_UPD", LIEF::assembly::arm::OPCODE::VST4LNd8_UPD) + .value("VST4LNq16", LIEF::assembly::arm::OPCODE::VST4LNq16) + .value("VST4LNq16Pseudo", LIEF::assembly::arm::OPCODE::VST4LNq16Pseudo) + .value("VST4LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4LNq16Pseudo_UPD) + .value("VST4LNq16_UPD", LIEF::assembly::arm::OPCODE::VST4LNq16_UPD) + .value("VST4LNq32", LIEF::assembly::arm::OPCODE::VST4LNq32) + .value("VST4LNq32Pseudo", LIEF::assembly::arm::OPCODE::VST4LNq32Pseudo) + .value("VST4LNq32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4LNq32Pseudo_UPD) + .value("VST4LNq32_UPD", LIEF::assembly::arm::OPCODE::VST4LNq32_UPD) + .value("VST4d16", LIEF::assembly::arm::OPCODE::VST4d16) + .value("VST4d16Pseudo", LIEF::assembly::arm::OPCODE::VST4d16Pseudo) + .value("VST4d16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4d16Pseudo_UPD) + .value("VST4d16_UPD", LIEF::assembly::arm::OPCODE::VST4d16_UPD) + .value("VST4d32", LIEF::assembly::arm::OPCODE::VST4d32) + .value("VST4d32Pseudo", LIEF::assembly::arm::OPCODE::VST4d32Pseudo) + .value("VST4d32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4d32Pseudo_UPD) + .value("VST4d32_UPD", LIEF::assembly::arm::OPCODE::VST4d32_UPD) + .value("VST4d8", LIEF::assembly::arm::OPCODE::VST4d8) + .value("VST4d8Pseudo", LIEF::assembly::arm::OPCODE::VST4d8Pseudo) + .value("VST4d8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4d8Pseudo_UPD) + .value("VST4d8_UPD", LIEF::assembly::arm::OPCODE::VST4d8_UPD) + .value("VST4q16", LIEF::assembly::arm::OPCODE::VST4q16) + .value("VST4q16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q16Pseudo_UPD) + .value("VST4q16_UPD", LIEF::assembly::arm::OPCODE::VST4q16_UPD) + .value("VST4q16oddPseudo", LIEF::assembly::arm::OPCODE::VST4q16oddPseudo) + .value("VST4q16oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q16oddPseudo_UPD) + .value("VST4q32", LIEF::assembly::arm::OPCODE::VST4q32) + .value("VST4q32Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q32Pseudo_UPD) + .value("VST4q32_UPD", LIEF::assembly::arm::OPCODE::VST4q32_UPD) + .value("VST4q32oddPseudo", LIEF::assembly::arm::OPCODE::VST4q32oddPseudo) + .value("VST4q32oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q32oddPseudo_UPD) + .value("VST4q8", LIEF::assembly::arm::OPCODE::VST4q8) + .value("VST4q8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q8Pseudo_UPD) + .value("VST4q8_UPD", LIEF::assembly::arm::OPCODE::VST4q8_UPD) + .value("VST4q8oddPseudo", LIEF::assembly::arm::OPCODE::VST4q8oddPseudo) + .value("VST4q8oddPseudo_UPD", LIEF::assembly::arm::OPCODE::VST4q8oddPseudo_UPD) + .value("VSTMDDB_UPD", LIEF::assembly::arm::OPCODE::VSTMDDB_UPD) + .value("VSTMDIA", LIEF::assembly::arm::OPCODE::VSTMDIA) + .value("VSTMDIA_UPD", LIEF::assembly::arm::OPCODE::VSTMDIA_UPD) + .value("VSTMQIA", LIEF::assembly::arm::OPCODE::VSTMQIA) + .value("VSTMSDB_UPD", LIEF::assembly::arm::OPCODE::VSTMSDB_UPD) + .value("VSTMSIA", LIEF::assembly::arm::OPCODE::VSTMSIA) + .value("VSTMSIA_UPD", LIEF::assembly::arm::OPCODE::VSTMSIA_UPD) + .value("VSTRD", LIEF::assembly::arm::OPCODE::VSTRD) + .value("VSTRH", LIEF::assembly::arm::OPCODE::VSTRH) + .value("VSTRS", LIEF::assembly::arm::OPCODE::VSTRS) + .value("VSTR_FPCXTNS_off", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_off) + .value("VSTR_FPCXTNS_post", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_post) + .value("VSTR_FPCXTNS_pre", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_pre) + .value("VSTR_FPCXTS_off", LIEF::assembly::arm::OPCODE::VSTR_FPCXTS_off) + .value("VSTR_FPCXTS_post", LIEF::assembly::arm::OPCODE::VSTR_FPCXTS_post) + .value("VSTR_FPCXTS_pre", LIEF::assembly::arm::OPCODE::VSTR_FPCXTS_pre) + .value("VSTR_FPSCR_NZCVQC_off", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_NZCVQC_off) + .value("VSTR_FPSCR_NZCVQC_post", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_NZCVQC_post) + .value("VSTR_FPSCR_NZCVQC_pre", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_NZCVQC_pre) + .value("VSTR_FPSCR_off", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_off) + .value("VSTR_FPSCR_post", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_post); + opcodes.value("VSTR_FPSCR_pre", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_pre) + .value("VSTR_P0_off", LIEF::assembly::arm::OPCODE::VSTR_P0_off) + .value("VSTR_P0_post", LIEF::assembly::arm::OPCODE::VSTR_P0_post) + .value("VSTR_P0_pre", LIEF::assembly::arm::OPCODE::VSTR_P0_pre) + .value("VSTR_VPR_off", LIEF::assembly::arm::OPCODE::VSTR_VPR_off) + .value("VSTR_VPR_post", LIEF::assembly::arm::OPCODE::VSTR_VPR_post) + .value("VSTR_VPR_pre", LIEF::assembly::arm::OPCODE::VSTR_VPR_pre) + .value("VSUBD", LIEF::assembly::arm::OPCODE::VSUBD) + .value("VSUBH", LIEF::assembly::arm::OPCODE::VSUBH) + .value("VSUBHNv2i32", LIEF::assembly::arm::OPCODE::VSUBHNv2i32) + .value("VSUBHNv4i16", LIEF::assembly::arm::OPCODE::VSUBHNv4i16) + .value("VSUBHNv8i8", LIEF::assembly::arm::OPCODE::VSUBHNv8i8) + .value("VSUBLsv2i64", LIEF::assembly::arm::OPCODE::VSUBLsv2i64) + .value("VSUBLsv4i32", LIEF::assembly::arm::OPCODE::VSUBLsv4i32) + .value("VSUBLsv8i16", LIEF::assembly::arm::OPCODE::VSUBLsv8i16) + .value("VSUBLuv2i64", LIEF::assembly::arm::OPCODE::VSUBLuv2i64) + .value("VSUBLuv4i32", LIEF::assembly::arm::OPCODE::VSUBLuv4i32) + .value("VSUBLuv8i16", LIEF::assembly::arm::OPCODE::VSUBLuv8i16) + .value("VSUBS", LIEF::assembly::arm::OPCODE::VSUBS) + .value("VSUBWsv2i64", LIEF::assembly::arm::OPCODE::VSUBWsv2i64) + .value("VSUBWsv4i32", LIEF::assembly::arm::OPCODE::VSUBWsv4i32) + .value("VSUBWsv8i16", LIEF::assembly::arm::OPCODE::VSUBWsv8i16) + .value("VSUBWuv2i64", LIEF::assembly::arm::OPCODE::VSUBWuv2i64) + .value("VSUBWuv4i32", LIEF::assembly::arm::OPCODE::VSUBWuv4i32) + .value("VSUBWuv8i16", LIEF::assembly::arm::OPCODE::VSUBWuv8i16) + .value("VSUBfd", LIEF::assembly::arm::OPCODE::VSUBfd) + .value("VSUBfq", LIEF::assembly::arm::OPCODE::VSUBfq) + .value("VSUBhd", LIEF::assembly::arm::OPCODE::VSUBhd) + .value("VSUBhq", LIEF::assembly::arm::OPCODE::VSUBhq) + .value("VSUBv16i8", LIEF::assembly::arm::OPCODE::VSUBv16i8) + .value("VSUBv1i64", LIEF::assembly::arm::OPCODE::VSUBv1i64) + .value("VSUBv2i32", LIEF::assembly::arm::OPCODE::VSUBv2i32) + .value("VSUBv2i64", LIEF::assembly::arm::OPCODE::VSUBv2i64) + .value("VSUBv4i16", LIEF::assembly::arm::OPCODE::VSUBv4i16) + .value("VSUBv4i32", LIEF::assembly::arm::OPCODE::VSUBv4i32) + .value("VSUBv8i16", LIEF::assembly::arm::OPCODE::VSUBv8i16) + .value("VSUBv8i8", LIEF::assembly::arm::OPCODE::VSUBv8i8) + .value("VSUDOTDI", LIEF::assembly::arm::OPCODE::VSUDOTDI) + .value("VSUDOTQI", LIEF::assembly::arm::OPCODE::VSUDOTQI) + .value("VSWPd", LIEF::assembly::arm::OPCODE::VSWPd) + .value("VSWPq", LIEF::assembly::arm::OPCODE::VSWPq) + .value("VTBL1", LIEF::assembly::arm::OPCODE::VTBL1) + .value("VTBL2", LIEF::assembly::arm::OPCODE::VTBL2) + .value("VTBL3", LIEF::assembly::arm::OPCODE::VTBL3) + .value("VTBL3Pseudo", LIEF::assembly::arm::OPCODE::VTBL3Pseudo) + .value("VTBL4", LIEF::assembly::arm::OPCODE::VTBL4) + .value("VTBL4Pseudo", LIEF::assembly::arm::OPCODE::VTBL4Pseudo) + .value("VTBX1", LIEF::assembly::arm::OPCODE::VTBX1) + .value("VTBX2", LIEF::assembly::arm::OPCODE::VTBX2) + .value("VTBX3", LIEF::assembly::arm::OPCODE::VTBX3) + .value("VTBX3Pseudo", LIEF::assembly::arm::OPCODE::VTBX3Pseudo) + .value("VTBX4", LIEF::assembly::arm::OPCODE::VTBX4) + .value("VTBX4Pseudo", LIEF::assembly::arm::OPCODE::VTBX4Pseudo) + .value("VTOSHD", LIEF::assembly::arm::OPCODE::VTOSHD) + .value("VTOSHH", LIEF::assembly::arm::OPCODE::VTOSHH) + .value("VTOSHS", LIEF::assembly::arm::OPCODE::VTOSHS) + .value("VTOSIRD", LIEF::assembly::arm::OPCODE::VTOSIRD) + .value("VTOSIRH", LIEF::assembly::arm::OPCODE::VTOSIRH) + .value("VTOSIRS", LIEF::assembly::arm::OPCODE::VTOSIRS) + .value("VTOSIZD", LIEF::assembly::arm::OPCODE::VTOSIZD) + .value("VTOSIZH", LIEF::assembly::arm::OPCODE::VTOSIZH) + .value("VTOSIZS", LIEF::assembly::arm::OPCODE::VTOSIZS) + .value("VTOSLD", LIEF::assembly::arm::OPCODE::VTOSLD) + .value("VTOSLH", LIEF::assembly::arm::OPCODE::VTOSLH) + .value("VTOSLS", LIEF::assembly::arm::OPCODE::VTOSLS) + .value("VTOUHD", LIEF::assembly::arm::OPCODE::VTOUHD) + .value("VTOUHH", LIEF::assembly::arm::OPCODE::VTOUHH) + .value("VTOUHS", LIEF::assembly::arm::OPCODE::VTOUHS) + .value("VTOUIRD", LIEF::assembly::arm::OPCODE::VTOUIRD) + .value("VTOUIRH", LIEF::assembly::arm::OPCODE::VTOUIRH) + .value("VTOUIRS", LIEF::assembly::arm::OPCODE::VTOUIRS) + .value("VTOUIZD", LIEF::assembly::arm::OPCODE::VTOUIZD) + .value("VTOUIZH", LIEF::assembly::arm::OPCODE::VTOUIZH) + .value("VTOUIZS", LIEF::assembly::arm::OPCODE::VTOUIZS) + .value("VTOULD", LIEF::assembly::arm::OPCODE::VTOULD) + .value("VTOULH", LIEF::assembly::arm::OPCODE::VTOULH) + .value("VTOULS", LIEF::assembly::arm::OPCODE::VTOULS) + .value("VTRNd16", LIEF::assembly::arm::OPCODE::VTRNd16) + .value("VTRNd32", LIEF::assembly::arm::OPCODE::VTRNd32) + .value("VTRNd8", LIEF::assembly::arm::OPCODE::VTRNd8) + .value("VTRNq16", LIEF::assembly::arm::OPCODE::VTRNq16) + .value("VTRNq32", LIEF::assembly::arm::OPCODE::VTRNq32) + .value("VTRNq8", LIEF::assembly::arm::OPCODE::VTRNq8) + .value("VTSTv16i8", LIEF::assembly::arm::OPCODE::VTSTv16i8) + .value("VTSTv2i32", LIEF::assembly::arm::OPCODE::VTSTv2i32) + .value("VTSTv4i16", LIEF::assembly::arm::OPCODE::VTSTv4i16) + .value("VTSTv4i32", LIEF::assembly::arm::OPCODE::VTSTv4i32) + .value("VTSTv8i16", LIEF::assembly::arm::OPCODE::VTSTv8i16) + .value("VTSTv8i8", LIEF::assembly::arm::OPCODE::VTSTv8i8) + .value("VUDOTD", LIEF::assembly::arm::OPCODE::VUDOTD) + .value("VUDOTDI", LIEF::assembly::arm::OPCODE::VUDOTDI) + .value("VUDOTQ", LIEF::assembly::arm::OPCODE::VUDOTQ) + .value("VUDOTQI", LIEF::assembly::arm::OPCODE::VUDOTQI) + .value("VUHTOD", LIEF::assembly::arm::OPCODE::VUHTOD) + .value("VUHTOH", LIEF::assembly::arm::OPCODE::VUHTOH) + .value("VUHTOS", LIEF::assembly::arm::OPCODE::VUHTOS) + .value("VUITOD", LIEF::assembly::arm::OPCODE::VUITOD) + .value("VUITOH", LIEF::assembly::arm::OPCODE::VUITOH) + .value("VUITOS", LIEF::assembly::arm::OPCODE::VUITOS) + .value("VULTOD", LIEF::assembly::arm::OPCODE::VULTOD) + .value("VULTOH", LIEF::assembly::arm::OPCODE::VULTOH) + .value("VULTOS", LIEF::assembly::arm::OPCODE::VULTOS) + .value("VUMMLA", LIEF::assembly::arm::OPCODE::VUMMLA) + .value("VUSDOTD", LIEF::assembly::arm::OPCODE::VUSDOTD) + .value("VUSDOTDI", LIEF::assembly::arm::OPCODE::VUSDOTDI) + .value("VUSDOTQ", LIEF::assembly::arm::OPCODE::VUSDOTQ) + .value("VUSDOTQI", LIEF::assembly::arm::OPCODE::VUSDOTQI) + .value("VUSMMLA", LIEF::assembly::arm::OPCODE::VUSMMLA) + .value("VUZPd16", LIEF::assembly::arm::OPCODE::VUZPd16) + .value("VUZPd8", LIEF::assembly::arm::OPCODE::VUZPd8) + .value("VUZPq16", LIEF::assembly::arm::OPCODE::VUZPq16) + .value("VUZPq32", LIEF::assembly::arm::OPCODE::VUZPq32) + .value("VUZPq8", LIEF::assembly::arm::OPCODE::VUZPq8) + .value("VZIPd16", LIEF::assembly::arm::OPCODE::VZIPd16) + .value("VZIPd8", LIEF::assembly::arm::OPCODE::VZIPd8) + .value("VZIPq16", LIEF::assembly::arm::OPCODE::VZIPq16) + .value("VZIPq32", LIEF::assembly::arm::OPCODE::VZIPq32) + .value("VZIPq8", LIEF::assembly::arm::OPCODE::VZIPq8) + .value("sysLDMDA", LIEF::assembly::arm::OPCODE::sysLDMDA) + .value("sysLDMDA_UPD", LIEF::assembly::arm::OPCODE::sysLDMDA_UPD) + .value("sysLDMDB", LIEF::assembly::arm::OPCODE::sysLDMDB) + .value("sysLDMDB_UPD", LIEF::assembly::arm::OPCODE::sysLDMDB_UPD) + .value("sysLDMIA", LIEF::assembly::arm::OPCODE::sysLDMIA) + .value("sysLDMIA_UPD", LIEF::assembly::arm::OPCODE::sysLDMIA_UPD) + .value("sysLDMIB", LIEF::assembly::arm::OPCODE::sysLDMIB) + .value("sysLDMIB_UPD", LIEF::assembly::arm::OPCODE::sysLDMIB_UPD) + .value("sysSTMDA", LIEF::assembly::arm::OPCODE::sysSTMDA) + .value("sysSTMDA_UPD", LIEF::assembly::arm::OPCODE::sysSTMDA_UPD) + .value("sysSTMDB", LIEF::assembly::arm::OPCODE::sysSTMDB) + .value("sysSTMDB_UPD", LIEF::assembly::arm::OPCODE::sysSTMDB_UPD) + .value("sysSTMIA", LIEF::assembly::arm::OPCODE::sysSTMIA) + .value("sysSTMIA_UPD", LIEF::assembly::arm::OPCODE::sysSTMIA_UPD) + .value("sysSTMIB", LIEF::assembly::arm::OPCODE::sysSTMIB) + .value("sysSTMIB_UPD", LIEF::assembly::arm::OPCODE::sysSTMIB_UPD) + .value("t2ADCri", LIEF::assembly::arm::OPCODE::t2ADCri) + .value("t2ADCrr", LIEF::assembly::arm::OPCODE::t2ADCrr) + .value("t2ADCrs", LIEF::assembly::arm::OPCODE::t2ADCrs) + .value("t2ADDri", LIEF::assembly::arm::OPCODE::t2ADDri) + .value("t2ADDri12", LIEF::assembly::arm::OPCODE::t2ADDri12) + .value("t2ADDrr", LIEF::assembly::arm::OPCODE::t2ADDrr) + .value("t2ADDrs", LIEF::assembly::arm::OPCODE::t2ADDrs) + .value("t2ADDspImm", LIEF::assembly::arm::OPCODE::t2ADDspImm) + .value("t2ADDspImm12", LIEF::assembly::arm::OPCODE::t2ADDspImm12) + .value("t2ADR", LIEF::assembly::arm::OPCODE::t2ADR) + .value("t2ANDri", LIEF::assembly::arm::OPCODE::t2ANDri) + .value("t2ANDrr", LIEF::assembly::arm::OPCODE::t2ANDrr) + .value("t2ANDrs", LIEF::assembly::arm::OPCODE::t2ANDrs) + .value("t2ASRri", LIEF::assembly::arm::OPCODE::t2ASRri) + .value("t2ASRrr", LIEF::assembly::arm::OPCODE::t2ASRrr) + .value("t2ASRs1", LIEF::assembly::arm::OPCODE::t2ASRs1) + .value("t2AUT", LIEF::assembly::arm::OPCODE::t2AUT) + .value("t2AUTG", LIEF::assembly::arm::OPCODE::t2AUTG) + .value("t2B", LIEF::assembly::arm::OPCODE::t2B) + .value("t2BFC", LIEF::assembly::arm::OPCODE::t2BFC) + .value("t2BFI", LIEF::assembly::arm::OPCODE::t2BFI) + .value("t2BFLi", LIEF::assembly::arm::OPCODE::t2BFLi) + .value("t2BFLr", LIEF::assembly::arm::OPCODE::t2BFLr) + .value("t2BFi", LIEF::assembly::arm::OPCODE::t2BFi) + .value("t2BFic", LIEF::assembly::arm::OPCODE::t2BFic) + .value("t2BFr", LIEF::assembly::arm::OPCODE::t2BFr) + .value("t2BICri", LIEF::assembly::arm::OPCODE::t2BICri) + .value("t2BICrr", LIEF::assembly::arm::OPCODE::t2BICrr) + .value("t2BICrs", LIEF::assembly::arm::OPCODE::t2BICrs) + .value("t2BTI", LIEF::assembly::arm::OPCODE::t2BTI) + .value("t2BXAUT", LIEF::assembly::arm::OPCODE::t2BXAUT) + .value("t2BXJ", LIEF::assembly::arm::OPCODE::t2BXJ) + .value("t2Bcc", LIEF::assembly::arm::OPCODE::t2Bcc) + .value("t2CDP", LIEF::assembly::arm::OPCODE::t2CDP) + .value("t2CDP2", LIEF::assembly::arm::OPCODE::t2CDP2) + .value("t2CLREX", LIEF::assembly::arm::OPCODE::t2CLREX) + .value("t2CLRM", LIEF::assembly::arm::OPCODE::t2CLRM) + .value("t2CLZ", LIEF::assembly::arm::OPCODE::t2CLZ) + .value("t2CMNri", LIEF::assembly::arm::OPCODE::t2CMNri) + .value("t2CMNzrr", LIEF::assembly::arm::OPCODE::t2CMNzrr) + .value("t2CMNzrs", LIEF::assembly::arm::OPCODE::t2CMNzrs) + .value("t2CMPri", LIEF::assembly::arm::OPCODE::t2CMPri) + .value("t2CMPrr", LIEF::assembly::arm::OPCODE::t2CMPrr) + .value("t2CMPrs", LIEF::assembly::arm::OPCODE::t2CMPrs) + .value("t2CPS1p", LIEF::assembly::arm::OPCODE::t2CPS1p) + .value("t2CPS2p", LIEF::assembly::arm::OPCODE::t2CPS2p) + .value("t2CPS3p", LIEF::assembly::arm::OPCODE::t2CPS3p) + .value("t2CRC32B", LIEF::assembly::arm::OPCODE::t2CRC32B) + .value("t2CRC32CB", LIEF::assembly::arm::OPCODE::t2CRC32CB) + .value("t2CRC32CH", LIEF::assembly::arm::OPCODE::t2CRC32CH) + .value("t2CRC32CW", LIEF::assembly::arm::OPCODE::t2CRC32CW) + .value("t2CRC32H", LIEF::assembly::arm::OPCODE::t2CRC32H) + .value("t2CRC32W", LIEF::assembly::arm::OPCODE::t2CRC32W) + .value("t2CSEL", LIEF::assembly::arm::OPCODE::t2CSEL) + .value("t2CSINC", LIEF::assembly::arm::OPCODE::t2CSINC) + .value("t2CSINV", LIEF::assembly::arm::OPCODE::t2CSINV) + .value("t2CSNEG", LIEF::assembly::arm::OPCODE::t2CSNEG) + .value("t2DBG", LIEF::assembly::arm::OPCODE::t2DBG) + .value("t2DCPS1", LIEF::assembly::arm::OPCODE::t2DCPS1) + .value("t2DCPS2", LIEF::assembly::arm::OPCODE::t2DCPS2) + .value("t2DCPS3", LIEF::assembly::arm::OPCODE::t2DCPS3) + .value("t2DLS", LIEF::assembly::arm::OPCODE::t2DLS) + .value("t2DMB", LIEF::assembly::arm::OPCODE::t2DMB) + .value("t2DSB", LIEF::assembly::arm::OPCODE::t2DSB) + .value("t2EORri", LIEF::assembly::arm::OPCODE::t2EORri) + .value("t2EORrr", LIEF::assembly::arm::OPCODE::t2EORrr) + .value("t2EORrs", LIEF::assembly::arm::OPCODE::t2EORrs) + .value("t2HINT", LIEF::assembly::arm::OPCODE::t2HINT) + .value("t2HVC", LIEF::assembly::arm::OPCODE::t2HVC) + .value("t2ISB", LIEF::assembly::arm::OPCODE::t2ISB) + .value("t2IT", LIEF::assembly::arm::OPCODE::t2IT) + .value("t2Int_eh_sjlj_setjmp", LIEF::assembly::arm::OPCODE::t2Int_eh_sjlj_setjmp) + .value("t2Int_eh_sjlj_setjmp_nofp", LIEF::assembly::arm::OPCODE::t2Int_eh_sjlj_setjmp_nofp) + .value("t2LDA", LIEF::assembly::arm::OPCODE::t2LDA) + .value("t2LDAB", LIEF::assembly::arm::OPCODE::t2LDAB) + .value("t2LDAEX", LIEF::assembly::arm::OPCODE::t2LDAEX) + .value("t2LDAEXB", LIEF::assembly::arm::OPCODE::t2LDAEXB) + .value("t2LDAEXD", LIEF::assembly::arm::OPCODE::t2LDAEXD) + .value("t2LDAEXH", LIEF::assembly::arm::OPCODE::t2LDAEXH) + .value("t2LDAH", LIEF::assembly::arm::OPCODE::t2LDAH) + .value("t2LDC2L_OFFSET", LIEF::assembly::arm::OPCODE::t2LDC2L_OFFSET) + .value("t2LDC2L_OPTION", LIEF::assembly::arm::OPCODE::t2LDC2L_OPTION) + .value("t2LDC2L_POST", LIEF::assembly::arm::OPCODE::t2LDC2L_POST) + .value("t2LDC2L_PRE", LIEF::assembly::arm::OPCODE::t2LDC2L_PRE) + .value("t2LDC2_OFFSET", LIEF::assembly::arm::OPCODE::t2LDC2_OFFSET) + .value("t2LDC2_OPTION", LIEF::assembly::arm::OPCODE::t2LDC2_OPTION) + .value("t2LDC2_POST", LIEF::assembly::arm::OPCODE::t2LDC2_POST) + .value("t2LDC2_PRE", LIEF::assembly::arm::OPCODE::t2LDC2_PRE) + .value("t2LDCL_OFFSET", LIEF::assembly::arm::OPCODE::t2LDCL_OFFSET) + .value("t2LDCL_OPTION", LIEF::assembly::arm::OPCODE::t2LDCL_OPTION) + .value("t2LDCL_POST", LIEF::assembly::arm::OPCODE::t2LDCL_POST) + .value("t2LDCL_PRE", LIEF::assembly::arm::OPCODE::t2LDCL_PRE) + .value("t2LDC_OFFSET", LIEF::assembly::arm::OPCODE::t2LDC_OFFSET) + .value("t2LDC_OPTION", LIEF::assembly::arm::OPCODE::t2LDC_OPTION) + .value("t2LDC_POST", LIEF::assembly::arm::OPCODE::t2LDC_POST) + .value("t2LDC_PRE", LIEF::assembly::arm::OPCODE::t2LDC_PRE) + .value("t2LDMDB", LIEF::assembly::arm::OPCODE::t2LDMDB) + .value("t2LDMDB_UPD", LIEF::assembly::arm::OPCODE::t2LDMDB_UPD) + .value("t2LDMIA", LIEF::assembly::arm::OPCODE::t2LDMIA) + .value("t2LDMIA_UPD", LIEF::assembly::arm::OPCODE::t2LDMIA_UPD) + .value("t2LDRBT", LIEF::assembly::arm::OPCODE::t2LDRBT) + .value("t2LDRB_POST", LIEF::assembly::arm::OPCODE::t2LDRB_POST) + .value("t2LDRB_PRE", LIEF::assembly::arm::OPCODE::t2LDRB_PRE) + .value("t2LDRBi12", LIEF::assembly::arm::OPCODE::t2LDRBi12) + .value("t2LDRBi8", LIEF::assembly::arm::OPCODE::t2LDRBi8) + .value("t2LDRBpci", LIEF::assembly::arm::OPCODE::t2LDRBpci) + .value("t2LDRBs", LIEF::assembly::arm::OPCODE::t2LDRBs) + .value("t2LDRD_POST", LIEF::assembly::arm::OPCODE::t2LDRD_POST) + .value("t2LDRD_PRE", LIEF::assembly::arm::OPCODE::t2LDRD_PRE) + .value("t2LDRDi8", LIEF::assembly::arm::OPCODE::t2LDRDi8) + .value("t2LDREX", LIEF::assembly::arm::OPCODE::t2LDREX) + .value("t2LDREXB", LIEF::assembly::arm::OPCODE::t2LDREXB) + .value("t2LDREXD", LIEF::assembly::arm::OPCODE::t2LDREXD) + .value("t2LDREXH", LIEF::assembly::arm::OPCODE::t2LDREXH) + .value("t2LDRHT", LIEF::assembly::arm::OPCODE::t2LDRHT) + .value("t2LDRH_POST", LIEF::assembly::arm::OPCODE::t2LDRH_POST) + .value("t2LDRH_PRE", LIEF::assembly::arm::OPCODE::t2LDRH_PRE) + .value("t2LDRHi12", LIEF::assembly::arm::OPCODE::t2LDRHi12) + .value("t2LDRHi8", LIEF::assembly::arm::OPCODE::t2LDRHi8) + .value("t2LDRHpci", LIEF::assembly::arm::OPCODE::t2LDRHpci) + .value("t2LDRHs", LIEF::assembly::arm::OPCODE::t2LDRHs) + .value("t2LDRSBT", LIEF::assembly::arm::OPCODE::t2LDRSBT) + .value("t2LDRSB_POST", LIEF::assembly::arm::OPCODE::t2LDRSB_POST) + .value("t2LDRSB_PRE", LIEF::assembly::arm::OPCODE::t2LDRSB_PRE) + .value("t2LDRSBi12", LIEF::assembly::arm::OPCODE::t2LDRSBi12) + .value("t2LDRSBi8", LIEF::assembly::arm::OPCODE::t2LDRSBi8) + .value("t2LDRSBpci", LIEF::assembly::arm::OPCODE::t2LDRSBpci) + .value("t2LDRSBs", LIEF::assembly::arm::OPCODE::t2LDRSBs) + .value("t2LDRSHT", LIEF::assembly::arm::OPCODE::t2LDRSHT) + .value("t2LDRSH_POST", LIEF::assembly::arm::OPCODE::t2LDRSH_POST) + .value("t2LDRSH_PRE", LIEF::assembly::arm::OPCODE::t2LDRSH_PRE) + .value("t2LDRSHi12", LIEF::assembly::arm::OPCODE::t2LDRSHi12) + .value("t2LDRSHi8", LIEF::assembly::arm::OPCODE::t2LDRSHi8) + .value("t2LDRSHpci", LIEF::assembly::arm::OPCODE::t2LDRSHpci) + .value("t2LDRSHs", LIEF::assembly::arm::OPCODE::t2LDRSHs) + .value("t2LDRT", LIEF::assembly::arm::OPCODE::t2LDRT) + .value("t2LDR_POST", LIEF::assembly::arm::OPCODE::t2LDR_POST) + .value("t2LDR_PRE", LIEF::assembly::arm::OPCODE::t2LDR_PRE) + .value("t2LDRi12", LIEF::assembly::arm::OPCODE::t2LDRi12) + .value("t2LDRi8", LIEF::assembly::arm::OPCODE::t2LDRi8) + .value("t2LDRpci", LIEF::assembly::arm::OPCODE::t2LDRpci) + .value("t2LDRs", LIEF::assembly::arm::OPCODE::t2LDRs) + .value("t2LE", LIEF::assembly::arm::OPCODE::t2LE) + .value("t2LEUpdate", LIEF::assembly::arm::OPCODE::t2LEUpdate) + .value("t2LSLri", LIEF::assembly::arm::OPCODE::t2LSLri) + .value("t2LSLrr", LIEF::assembly::arm::OPCODE::t2LSLrr) + .value("t2LSRri", LIEF::assembly::arm::OPCODE::t2LSRri) + .value("t2LSRrr", LIEF::assembly::arm::OPCODE::t2LSRrr) + .value("t2LSRs1", LIEF::assembly::arm::OPCODE::t2LSRs1) + .value("t2MCR", LIEF::assembly::arm::OPCODE::t2MCR) + .value("t2MCR2", LIEF::assembly::arm::OPCODE::t2MCR2) + .value("t2MCRR", LIEF::assembly::arm::OPCODE::t2MCRR) + .value("t2MCRR2", LIEF::assembly::arm::OPCODE::t2MCRR2) + .value("t2MLA", LIEF::assembly::arm::OPCODE::t2MLA) + .value("t2MLS", LIEF::assembly::arm::OPCODE::t2MLS) + .value("t2MOVTi16", LIEF::assembly::arm::OPCODE::t2MOVTi16) + .value("t2MOVi", LIEF::assembly::arm::OPCODE::t2MOVi) + .value("t2MOVi16", LIEF::assembly::arm::OPCODE::t2MOVi16) + .value("t2MOVr", LIEF::assembly::arm::OPCODE::t2MOVr) + .value("t2MRC", LIEF::assembly::arm::OPCODE::t2MRC) + .value("t2MRC2", LIEF::assembly::arm::OPCODE::t2MRC2) + .value("t2MRRC", LIEF::assembly::arm::OPCODE::t2MRRC) + .value("t2MRRC2", LIEF::assembly::arm::OPCODE::t2MRRC2) + .value("t2MRS_AR", LIEF::assembly::arm::OPCODE::t2MRS_AR) + .value("t2MRS_M", LIEF::assembly::arm::OPCODE::t2MRS_M) + .value("t2MRSbanked", LIEF::assembly::arm::OPCODE::t2MRSbanked); + opcodes.value("t2MRSsys_AR", LIEF::assembly::arm::OPCODE::t2MRSsys_AR) + .value("t2MSR_AR", LIEF::assembly::arm::OPCODE::t2MSR_AR) + .value("t2MSR_M", LIEF::assembly::arm::OPCODE::t2MSR_M) + .value("t2MSRbanked", LIEF::assembly::arm::OPCODE::t2MSRbanked) + .value("t2MUL", LIEF::assembly::arm::OPCODE::t2MUL) + .value("t2MVNi", LIEF::assembly::arm::OPCODE::t2MVNi) + .value("t2MVNr", LIEF::assembly::arm::OPCODE::t2MVNr) + .value("t2MVNs", LIEF::assembly::arm::OPCODE::t2MVNs) + .value("t2ORNri", LIEF::assembly::arm::OPCODE::t2ORNri) + .value("t2ORNrr", LIEF::assembly::arm::OPCODE::t2ORNrr) + .value("t2ORNrs", LIEF::assembly::arm::OPCODE::t2ORNrs) + .value("t2ORRri", LIEF::assembly::arm::OPCODE::t2ORRri) + .value("t2ORRrr", LIEF::assembly::arm::OPCODE::t2ORRrr) + .value("t2ORRrs", LIEF::assembly::arm::OPCODE::t2ORRrs) + .value("t2PAC", LIEF::assembly::arm::OPCODE::t2PAC) + .value("t2PACBTI", LIEF::assembly::arm::OPCODE::t2PACBTI) + .value("t2PACG", LIEF::assembly::arm::OPCODE::t2PACG) + .value("t2PKHBT", LIEF::assembly::arm::OPCODE::t2PKHBT) + .value("t2PKHTB", LIEF::assembly::arm::OPCODE::t2PKHTB) + .value("t2PLDWi12", LIEF::assembly::arm::OPCODE::t2PLDWi12) + .value("t2PLDWi8", LIEF::assembly::arm::OPCODE::t2PLDWi8) + .value("t2PLDWs", LIEF::assembly::arm::OPCODE::t2PLDWs) + .value("t2PLDi12", LIEF::assembly::arm::OPCODE::t2PLDi12) + .value("t2PLDi8", LIEF::assembly::arm::OPCODE::t2PLDi8) + .value("t2PLDpci", LIEF::assembly::arm::OPCODE::t2PLDpci) + .value("t2PLDs", LIEF::assembly::arm::OPCODE::t2PLDs) + .value("t2PLIi12", LIEF::assembly::arm::OPCODE::t2PLIi12) + .value("t2PLIi8", LIEF::assembly::arm::OPCODE::t2PLIi8) + .value("t2PLIpci", LIEF::assembly::arm::OPCODE::t2PLIpci) + .value("t2PLIs", LIEF::assembly::arm::OPCODE::t2PLIs) + .value("t2QADD", LIEF::assembly::arm::OPCODE::t2QADD) + .value("t2QADD16", LIEF::assembly::arm::OPCODE::t2QADD16) + .value("t2QADD8", LIEF::assembly::arm::OPCODE::t2QADD8) + .value("t2QASX", LIEF::assembly::arm::OPCODE::t2QASX) + .value("t2QDADD", LIEF::assembly::arm::OPCODE::t2QDADD) + .value("t2QDSUB", LIEF::assembly::arm::OPCODE::t2QDSUB) + .value("t2QSAX", LIEF::assembly::arm::OPCODE::t2QSAX) + .value("t2QSUB", LIEF::assembly::arm::OPCODE::t2QSUB) + .value("t2QSUB16", LIEF::assembly::arm::OPCODE::t2QSUB16) + .value("t2QSUB8", LIEF::assembly::arm::OPCODE::t2QSUB8) + .value("t2RBIT", LIEF::assembly::arm::OPCODE::t2RBIT) + .value("t2REV", LIEF::assembly::arm::OPCODE::t2REV) + .value("t2REV16", LIEF::assembly::arm::OPCODE::t2REV16) + .value("t2REVSH", LIEF::assembly::arm::OPCODE::t2REVSH) + .value("t2RFEDB", LIEF::assembly::arm::OPCODE::t2RFEDB) + .value("t2RFEDBW", LIEF::assembly::arm::OPCODE::t2RFEDBW) + .value("t2RFEIA", LIEF::assembly::arm::OPCODE::t2RFEIA) + .value("t2RFEIAW", LIEF::assembly::arm::OPCODE::t2RFEIAW) + .value("t2RORri", LIEF::assembly::arm::OPCODE::t2RORri) + .value("t2RORrr", LIEF::assembly::arm::OPCODE::t2RORrr) + .value("t2RRX", LIEF::assembly::arm::OPCODE::t2RRX) + .value("t2RSBri", LIEF::assembly::arm::OPCODE::t2RSBri) + .value("t2RSBrr", LIEF::assembly::arm::OPCODE::t2RSBrr) + .value("t2RSBrs", LIEF::assembly::arm::OPCODE::t2RSBrs) + .value("t2SADD16", LIEF::assembly::arm::OPCODE::t2SADD16) + .value("t2SADD8", LIEF::assembly::arm::OPCODE::t2SADD8) + .value("t2SASX", LIEF::assembly::arm::OPCODE::t2SASX) + .value("t2SB", LIEF::assembly::arm::OPCODE::t2SB) + .value("t2SBCri", LIEF::assembly::arm::OPCODE::t2SBCri) + .value("t2SBCrr", LIEF::assembly::arm::OPCODE::t2SBCrr) + .value("t2SBCrs", LIEF::assembly::arm::OPCODE::t2SBCrs) + .value("t2SBFX", LIEF::assembly::arm::OPCODE::t2SBFX) + .value("t2SDIV", LIEF::assembly::arm::OPCODE::t2SDIV) + .value("t2SEL", LIEF::assembly::arm::OPCODE::t2SEL) + .value("t2SETPAN", LIEF::assembly::arm::OPCODE::t2SETPAN) + .value("t2SG", LIEF::assembly::arm::OPCODE::t2SG) + .value("t2SHADD16", LIEF::assembly::arm::OPCODE::t2SHADD16) + .value("t2SHADD8", LIEF::assembly::arm::OPCODE::t2SHADD8) + .value("t2SHASX", LIEF::assembly::arm::OPCODE::t2SHASX) + .value("t2SHSAX", LIEF::assembly::arm::OPCODE::t2SHSAX) + .value("t2SHSUB16", LIEF::assembly::arm::OPCODE::t2SHSUB16) + .value("t2SHSUB8", LIEF::assembly::arm::OPCODE::t2SHSUB8) + .value("t2SMC", LIEF::assembly::arm::OPCODE::t2SMC) + .value("t2SMLABB", LIEF::assembly::arm::OPCODE::t2SMLABB) + .value("t2SMLABT", LIEF::assembly::arm::OPCODE::t2SMLABT) + .value("t2SMLAD", LIEF::assembly::arm::OPCODE::t2SMLAD) + .value("t2SMLADX", LIEF::assembly::arm::OPCODE::t2SMLADX) + .value("t2SMLAL", LIEF::assembly::arm::OPCODE::t2SMLAL) + .value("t2SMLALBB", LIEF::assembly::arm::OPCODE::t2SMLALBB) + .value("t2SMLALBT", LIEF::assembly::arm::OPCODE::t2SMLALBT) + .value("t2SMLALD", LIEF::assembly::arm::OPCODE::t2SMLALD) + .value("t2SMLALDX", LIEF::assembly::arm::OPCODE::t2SMLALDX) + .value("t2SMLALTB", LIEF::assembly::arm::OPCODE::t2SMLALTB) + .value("t2SMLALTT", LIEF::assembly::arm::OPCODE::t2SMLALTT) + .value("t2SMLATB", LIEF::assembly::arm::OPCODE::t2SMLATB) + .value("t2SMLATT", LIEF::assembly::arm::OPCODE::t2SMLATT) + .value("t2SMLAWB", LIEF::assembly::arm::OPCODE::t2SMLAWB) + .value("t2SMLAWT", LIEF::assembly::arm::OPCODE::t2SMLAWT) + .value("t2SMLSD", LIEF::assembly::arm::OPCODE::t2SMLSD) + .value("t2SMLSDX", LIEF::assembly::arm::OPCODE::t2SMLSDX) + .value("t2SMLSLD", LIEF::assembly::arm::OPCODE::t2SMLSLD) + .value("t2SMLSLDX", LIEF::assembly::arm::OPCODE::t2SMLSLDX) + .value("t2SMMLA", LIEF::assembly::arm::OPCODE::t2SMMLA) + .value("t2SMMLAR", LIEF::assembly::arm::OPCODE::t2SMMLAR) + .value("t2SMMLS", LIEF::assembly::arm::OPCODE::t2SMMLS) + .value("t2SMMLSR", LIEF::assembly::arm::OPCODE::t2SMMLSR) + .value("t2SMMUL", LIEF::assembly::arm::OPCODE::t2SMMUL) + .value("t2SMMULR", LIEF::assembly::arm::OPCODE::t2SMMULR) + .value("t2SMUAD", LIEF::assembly::arm::OPCODE::t2SMUAD) + .value("t2SMUADX", LIEF::assembly::arm::OPCODE::t2SMUADX) + .value("t2SMULBB", LIEF::assembly::arm::OPCODE::t2SMULBB) + .value("t2SMULBT", LIEF::assembly::arm::OPCODE::t2SMULBT) + .value("t2SMULL", LIEF::assembly::arm::OPCODE::t2SMULL) + .value("t2SMULTB", LIEF::assembly::arm::OPCODE::t2SMULTB) + .value("t2SMULTT", LIEF::assembly::arm::OPCODE::t2SMULTT) + .value("t2SMULWB", LIEF::assembly::arm::OPCODE::t2SMULWB) + .value("t2SMULWT", LIEF::assembly::arm::OPCODE::t2SMULWT) + .value("t2SMUSD", LIEF::assembly::arm::OPCODE::t2SMUSD) + .value("t2SMUSDX", LIEF::assembly::arm::OPCODE::t2SMUSDX) + .value("t2SRSDB", LIEF::assembly::arm::OPCODE::t2SRSDB) + .value("t2SRSDB_UPD", LIEF::assembly::arm::OPCODE::t2SRSDB_UPD) + .value("t2SRSIA", LIEF::assembly::arm::OPCODE::t2SRSIA) + .value("t2SRSIA_UPD", LIEF::assembly::arm::OPCODE::t2SRSIA_UPD) + .value("t2SSAT", LIEF::assembly::arm::OPCODE::t2SSAT) + .value("t2SSAT16", LIEF::assembly::arm::OPCODE::t2SSAT16) + .value("t2SSAX", LIEF::assembly::arm::OPCODE::t2SSAX) + .value("t2SSUB16", LIEF::assembly::arm::OPCODE::t2SSUB16) + .value("t2SSUB8", LIEF::assembly::arm::OPCODE::t2SSUB8) + .value("t2STC2L_OFFSET", LIEF::assembly::arm::OPCODE::t2STC2L_OFFSET) + .value("t2STC2L_OPTION", LIEF::assembly::arm::OPCODE::t2STC2L_OPTION) + .value("t2STC2L_POST", LIEF::assembly::arm::OPCODE::t2STC2L_POST) + .value("t2STC2L_PRE", LIEF::assembly::arm::OPCODE::t2STC2L_PRE) + .value("t2STC2_OFFSET", LIEF::assembly::arm::OPCODE::t2STC2_OFFSET) + .value("t2STC2_OPTION", LIEF::assembly::arm::OPCODE::t2STC2_OPTION) + .value("t2STC2_POST", LIEF::assembly::arm::OPCODE::t2STC2_POST) + .value("t2STC2_PRE", LIEF::assembly::arm::OPCODE::t2STC2_PRE) + .value("t2STCL_OFFSET", LIEF::assembly::arm::OPCODE::t2STCL_OFFSET) + .value("t2STCL_OPTION", LIEF::assembly::arm::OPCODE::t2STCL_OPTION) + .value("t2STCL_POST", LIEF::assembly::arm::OPCODE::t2STCL_POST) + .value("t2STCL_PRE", LIEF::assembly::arm::OPCODE::t2STCL_PRE) + .value("t2STC_OFFSET", LIEF::assembly::arm::OPCODE::t2STC_OFFSET) + .value("t2STC_OPTION", LIEF::assembly::arm::OPCODE::t2STC_OPTION) + .value("t2STC_POST", LIEF::assembly::arm::OPCODE::t2STC_POST) + .value("t2STC_PRE", LIEF::assembly::arm::OPCODE::t2STC_PRE) + .value("t2STL", LIEF::assembly::arm::OPCODE::t2STL) + .value("t2STLB", LIEF::assembly::arm::OPCODE::t2STLB) + .value("t2STLEX", LIEF::assembly::arm::OPCODE::t2STLEX) + .value("t2STLEXB", LIEF::assembly::arm::OPCODE::t2STLEXB) + .value("t2STLEXD", LIEF::assembly::arm::OPCODE::t2STLEXD) + .value("t2STLEXH", LIEF::assembly::arm::OPCODE::t2STLEXH) + .value("t2STLH", LIEF::assembly::arm::OPCODE::t2STLH) + .value("t2STMDB", LIEF::assembly::arm::OPCODE::t2STMDB) + .value("t2STMDB_UPD", LIEF::assembly::arm::OPCODE::t2STMDB_UPD) + .value("t2STMIA", LIEF::assembly::arm::OPCODE::t2STMIA) + .value("t2STMIA_UPD", LIEF::assembly::arm::OPCODE::t2STMIA_UPD) + .value("t2STRBT", LIEF::assembly::arm::OPCODE::t2STRBT) + .value("t2STRB_POST", LIEF::assembly::arm::OPCODE::t2STRB_POST) + .value("t2STRB_PRE", LIEF::assembly::arm::OPCODE::t2STRB_PRE) + .value("t2STRBi12", LIEF::assembly::arm::OPCODE::t2STRBi12) + .value("t2STRBi8", LIEF::assembly::arm::OPCODE::t2STRBi8) + .value("t2STRBs", LIEF::assembly::arm::OPCODE::t2STRBs) + .value("t2STRD_POST", LIEF::assembly::arm::OPCODE::t2STRD_POST) + .value("t2STRD_PRE", LIEF::assembly::arm::OPCODE::t2STRD_PRE) + .value("t2STRDi8", LIEF::assembly::arm::OPCODE::t2STRDi8) + .value("t2STREX", LIEF::assembly::arm::OPCODE::t2STREX) + .value("t2STREXB", LIEF::assembly::arm::OPCODE::t2STREXB) + .value("t2STREXD", LIEF::assembly::arm::OPCODE::t2STREXD) + .value("t2STREXH", LIEF::assembly::arm::OPCODE::t2STREXH) + .value("t2STRHT", LIEF::assembly::arm::OPCODE::t2STRHT) + .value("t2STRH_POST", LIEF::assembly::arm::OPCODE::t2STRH_POST) + .value("t2STRH_PRE", LIEF::assembly::arm::OPCODE::t2STRH_PRE) + .value("t2STRHi12", LIEF::assembly::arm::OPCODE::t2STRHi12) + .value("t2STRHi8", LIEF::assembly::arm::OPCODE::t2STRHi8) + .value("t2STRHs", LIEF::assembly::arm::OPCODE::t2STRHs) + .value("t2STRT", LIEF::assembly::arm::OPCODE::t2STRT) + .value("t2STR_POST", LIEF::assembly::arm::OPCODE::t2STR_POST) + .value("t2STR_PRE", LIEF::assembly::arm::OPCODE::t2STR_PRE) + .value("t2STRi12", LIEF::assembly::arm::OPCODE::t2STRi12) + .value("t2STRi8", LIEF::assembly::arm::OPCODE::t2STRi8) + .value("t2STRs", LIEF::assembly::arm::OPCODE::t2STRs) + .value("t2SUBS_PC_LR", LIEF::assembly::arm::OPCODE::t2SUBS_PC_LR) + .value("t2SUBri", LIEF::assembly::arm::OPCODE::t2SUBri) + .value("t2SUBri12", LIEF::assembly::arm::OPCODE::t2SUBri12) + .value("t2SUBrr", LIEF::assembly::arm::OPCODE::t2SUBrr) + .value("t2SUBrs", LIEF::assembly::arm::OPCODE::t2SUBrs) + .value("t2SUBspImm", LIEF::assembly::arm::OPCODE::t2SUBspImm) + .value("t2SUBspImm12", LIEF::assembly::arm::OPCODE::t2SUBspImm12) + .value("t2SXTAB", LIEF::assembly::arm::OPCODE::t2SXTAB) + .value("t2SXTAB16", LIEF::assembly::arm::OPCODE::t2SXTAB16) + .value("t2SXTAH", LIEF::assembly::arm::OPCODE::t2SXTAH) + .value("t2SXTB", LIEF::assembly::arm::OPCODE::t2SXTB) + .value("t2SXTB16", LIEF::assembly::arm::OPCODE::t2SXTB16) + .value("t2SXTH", LIEF::assembly::arm::OPCODE::t2SXTH) + .value("t2TBB", LIEF::assembly::arm::OPCODE::t2TBB) + .value("t2TBH", LIEF::assembly::arm::OPCODE::t2TBH) + .value("t2TEQri", LIEF::assembly::arm::OPCODE::t2TEQri) + .value("t2TEQrr", LIEF::assembly::arm::OPCODE::t2TEQrr) + .value("t2TEQrs", LIEF::assembly::arm::OPCODE::t2TEQrs) + .value("t2TSB", LIEF::assembly::arm::OPCODE::t2TSB) + .value("t2TSTri", LIEF::assembly::arm::OPCODE::t2TSTri) + .value("t2TSTrr", LIEF::assembly::arm::OPCODE::t2TSTrr) + .value("t2TSTrs", LIEF::assembly::arm::OPCODE::t2TSTrs) + .value("t2TT", LIEF::assembly::arm::OPCODE::t2TT) + .value("t2TTA", LIEF::assembly::arm::OPCODE::t2TTA) + .value("t2TTAT", LIEF::assembly::arm::OPCODE::t2TTAT) + .value("t2TTT", LIEF::assembly::arm::OPCODE::t2TTT) + .value("t2UADD16", LIEF::assembly::arm::OPCODE::t2UADD16) + .value("t2UADD8", LIEF::assembly::arm::OPCODE::t2UADD8) + .value("t2UASX", LIEF::assembly::arm::OPCODE::t2UASX) + .value("t2UBFX", LIEF::assembly::arm::OPCODE::t2UBFX) + .value("t2UDF", LIEF::assembly::arm::OPCODE::t2UDF) + .value("t2UDIV", LIEF::assembly::arm::OPCODE::t2UDIV) + .value("t2UHADD16", LIEF::assembly::arm::OPCODE::t2UHADD16) + .value("t2UHADD8", LIEF::assembly::arm::OPCODE::t2UHADD8) + .value("t2UHASX", LIEF::assembly::arm::OPCODE::t2UHASX) + .value("t2UHSAX", LIEF::assembly::arm::OPCODE::t2UHSAX) + .value("t2UHSUB16", LIEF::assembly::arm::OPCODE::t2UHSUB16) + .value("t2UHSUB8", LIEF::assembly::arm::OPCODE::t2UHSUB8) + .value("t2UMAAL", LIEF::assembly::arm::OPCODE::t2UMAAL) + .value("t2UMLAL", LIEF::assembly::arm::OPCODE::t2UMLAL) + .value("t2UMULL", LIEF::assembly::arm::OPCODE::t2UMULL) + .value("t2UQADD16", LIEF::assembly::arm::OPCODE::t2UQADD16) + .value("t2UQADD8", LIEF::assembly::arm::OPCODE::t2UQADD8) + .value("t2UQASX", LIEF::assembly::arm::OPCODE::t2UQASX) + .value("t2UQSAX", LIEF::assembly::arm::OPCODE::t2UQSAX) + .value("t2UQSUB16", LIEF::assembly::arm::OPCODE::t2UQSUB16) + .value("t2UQSUB8", LIEF::assembly::arm::OPCODE::t2UQSUB8) + .value("t2USAD8", LIEF::assembly::arm::OPCODE::t2USAD8) + .value("t2USADA8", LIEF::assembly::arm::OPCODE::t2USADA8) + .value("t2USAT", LIEF::assembly::arm::OPCODE::t2USAT) + .value("t2USAT16", LIEF::assembly::arm::OPCODE::t2USAT16) + .value("t2USAX", LIEF::assembly::arm::OPCODE::t2USAX) + .value("t2USUB16", LIEF::assembly::arm::OPCODE::t2USUB16) + .value("t2USUB8", LIEF::assembly::arm::OPCODE::t2USUB8) + .value("t2UXTAB", LIEF::assembly::arm::OPCODE::t2UXTAB) + .value("t2UXTAB16", LIEF::assembly::arm::OPCODE::t2UXTAB16) + .value("t2UXTAH", LIEF::assembly::arm::OPCODE::t2UXTAH) + .value("t2UXTB", LIEF::assembly::arm::OPCODE::t2UXTB) + .value("t2UXTB16", LIEF::assembly::arm::OPCODE::t2UXTB16) + .value("t2UXTH", LIEF::assembly::arm::OPCODE::t2UXTH) + .value("t2WLS", LIEF::assembly::arm::OPCODE::t2WLS) + .value("tADC", LIEF::assembly::arm::OPCODE::tADC) + .value("tADDhirr", LIEF::assembly::arm::OPCODE::tADDhirr) + .value("tADDi3", LIEF::assembly::arm::OPCODE::tADDi3) + .value("tADDi8", LIEF::assembly::arm::OPCODE::tADDi8) + .value("tADDrSP", LIEF::assembly::arm::OPCODE::tADDrSP) + .value("tADDrSPi", LIEF::assembly::arm::OPCODE::tADDrSPi) + .value("tADDrr", LIEF::assembly::arm::OPCODE::tADDrr) + .value("tADDspi", LIEF::assembly::arm::OPCODE::tADDspi) + .value("tADDspr", LIEF::assembly::arm::OPCODE::tADDspr) + .value("tADR", LIEF::assembly::arm::OPCODE::tADR) + .value("tAND", LIEF::assembly::arm::OPCODE::tAND) + .value("tASRri", LIEF::assembly::arm::OPCODE::tASRri) + .value("tASRrr", LIEF::assembly::arm::OPCODE::tASRrr) + .value("tB", LIEF::assembly::arm::OPCODE::tB) + .value("tBIC", LIEF::assembly::arm::OPCODE::tBIC) + .value("tBKPT", LIEF::assembly::arm::OPCODE::tBKPT) + .value("tBL", LIEF::assembly::arm::OPCODE::tBL) + .value("tBLXNSr", LIEF::assembly::arm::OPCODE::tBLXNSr) + .value("tBLXi", LIEF::assembly::arm::OPCODE::tBLXi) + .value("tBLXr", LIEF::assembly::arm::OPCODE::tBLXr) + .value("tBX", LIEF::assembly::arm::OPCODE::tBX) + .value("tBXNS", LIEF::assembly::arm::OPCODE::tBXNS) + .value("tBcc", LIEF::assembly::arm::OPCODE::tBcc) + .value("tCBNZ", LIEF::assembly::arm::OPCODE::tCBNZ) + .value("tCBZ", LIEF::assembly::arm::OPCODE::tCBZ) + .value("tCMNz", LIEF::assembly::arm::OPCODE::tCMNz) + .value("tCMPhir", LIEF::assembly::arm::OPCODE::tCMPhir) + .value("tCMPi8", LIEF::assembly::arm::OPCODE::tCMPi8) + .value("tCMPr", LIEF::assembly::arm::OPCODE::tCMPr) + .value("tCPS", LIEF::assembly::arm::OPCODE::tCPS) + .value("tEOR", LIEF::assembly::arm::OPCODE::tEOR) + .value("tHINT", LIEF::assembly::arm::OPCODE::tHINT) + .value("tHLT", LIEF::assembly::arm::OPCODE::tHLT) + .value("tInt_WIN_eh_sjlj_longjmp", LIEF::assembly::arm::OPCODE::tInt_WIN_eh_sjlj_longjmp) + .value("tInt_eh_sjlj_longjmp", LIEF::assembly::arm::OPCODE::tInt_eh_sjlj_longjmp) + .value("tInt_eh_sjlj_setjmp", LIEF::assembly::arm::OPCODE::tInt_eh_sjlj_setjmp) + .value("tLDMIA", LIEF::assembly::arm::OPCODE::tLDMIA) + .value("tLDRBi", LIEF::assembly::arm::OPCODE::tLDRBi) + .value("tLDRBr", LIEF::assembly::arm::OPCODE::tLDRBr) + .value("tLDRHi", LIEF::assembly::arm::OPCODE::tLDRHi) + .value("tLDRHr", LIEF::assembly::arm::OPCODE::tLDRHr) + .value("tLDRSB", LIEF::assembly::arm::OPCODE::tLDRSB) + .value("tLDRSH", LIEF::assembly::arm::OPCODE::tLDRSH) + .value("tLDRi", LIEF::assembly::arm::OPCODE::tLDRi) + .value("tLDRpci", LIEF::assembly::arm::OPCODE::tLDRpci) + .value("tLDRr", LIEF::assembly::arm::OPCODE::tLDRr) + .value("tLDRspi", LIEF::assembly::arm::OPCODE::tLDRspi) + .value("tLSLri", LIEF::assembly::arm::OPCODE::tLSLri) + .value("tLSLrr", LIEF::assembly::arm::OPCODE::tLSLrr) + .value("tLSRri", LIEF::assembly::arm::OPCODE::tLSRri) + .value("tLSRrr", LIEF::assembly::arm::OPCODE::tLSRrr) + .value("tMOVSr", LIEF::assembly::arm::OPCODE::tMOVSr) + .value("tMOVi8", LIEF::assembly::arm::OPCODE::tMOVi8) + .value("tMOVr", LIEF::assembly::arm::OPCODE::tMOVr) + .value("tMUL", LIEF::assembly::arm::OPCODE::tMUL) + .value("tMVN", LIEF::assembly::arm::OPCODE::tMVN) + .value("tORR", LIEF::assembly::arm::OPCODE::tORR) + .value("tPICADD", LIEF::assembly::arm::OPCODE::tPICADD) + .value("tPOP", LIEF::assembly::arm::OPCODE::tPOP) + .value("tPUSH", LIEF::assembly::arm::OPCODE::tPUSH) + .value("tREV", LIEF::assembly::arm::OPCODE::tREV) + .value("tREV16", LIEF::assembly::arm::OPCODE::tREV16) + .value("tREVSH", LIEF::assembly::arm::OPCODE::tREVSH) + .value("tROR", LIEF::assembly::arm::OPCODE::tROR) + .value("tRSB", LIEF::assembly::arm::OPCODE::tRSB) + .value("tSBC", LIEF::assembly::arm::OPCODE::tSBC) + .value("tSETEND", LIEF::assembly::arm::OPCODE::tSETEND) + .value("tSTMIA_UPD", LIEF::assembly::arm::OPCODE::tSTMIA_UPD) + .value("tSTRBi", LIEF::assembly::arm::OPCODE::tSTRBi); + opcodes.value("tSTRBr", LIEF::assembly::arm::OPCODE::tSTRBr) + .value("tSTRHi", LIEF::assembly::arm::OPCODE::tSTRHi) + .value("tSTRHr", LIEF::assembly::arm::OPCODE::tSTRHr) + .value("tSTRi", LIEF::assembly::arm::OPCODE::tSTRi) + .value("tSTRr", LIEF::assembly::arm::OPCODE::tSTRr) + .value("tSTRspi", LIEF::assembly::arm::OPCODE::tSTRspi) + .value("tSUBi3", LIEF::assembly::arm::OPCODE::tSUBi3) + .value("tSUBi8", LIEF::assembly::arm::OPCODE::tSUBi8) + .value("tSUBrr", LIEF::assembly::arm::OPCODE::tSUBrr) + .value("tSUBspi", LIEF::assembly::arm::OPCODE::tSUBspi) + .value("tSVC", LIEF::assembly::arm::OPCODE::tSVC) + .value("tSXTB", LIEF::assembly::arm::OPCODE::tSXTB) + .value("tSXTH", LIEF::assembly::arm::OPCODE::tSXTH) + .value("tTRAP", LIEF::assembly::arm::OPCODE::tTRAP) + .value("tTST", LIEF::assembly::arm::OPCODE::tTST) + .value("tUDF", LIEF::assembly::arm::OPCODE::tUDF) + .value("tUXTB", LIEF::assembly::arm::OPCODE::tUXTB) + .value("tUXTH", LIEF::assembly::arm::OPCODE::tUXTH) + .value("t__brkdiv0", LIEF::assembly::arm::OPCODE::t__brkdiv0) + .value("INSTRUCTION_LIST_END", LIEF::assembly::arm::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/arm/pyRegister.cpp b/vendor/lief/api/python/src/asm/arm/pyRegister.cpp new file mode 100644 index 0000000..3fed4e4 --- /dev/null +++ b/vendor/lief/api/python/src/asm/arm/pyRegister.cpp @@ -0,0 +1,309 @@ +#include "asm/arm/init.hpp" + +#include "LIEF/asm/arm/registers.hpp" + +namespace LIEF::assembly::arm::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::arm::REG::NoRegister) + .value("APSR", LIEF::assembly::arm::REG::APSR) + .value("APSR_NZCV", LIEF::assembly::arm::REG::APSR_NZCV) + .value("CPSR", LIEF::assembly::arm::REG::CPSR) + .value("FPCXTNS", LIEF::assembly::arm::REG::FPCXTNS) + .value("FPCXTS", LIEF::assembly::arm::REG::FPCXTS) + .value("FPEXC", LIEF::assembly::arm::REG::FPEXC) + .value("FPINST", LIEF::assembly::arm::REG::FPINST) + .value("FPSCR", LIEF::assembly::arm::REG::FPSCR) + .value("FPSCR_NZCV", LIEF::assembly::arm::REG::FPSCR_NZCV) + .value("FPSCR_NZCVQC", LIEF::assembly::arm::REG::FPSCR_NZCVQC) + .value("FPSCR_RM", LIEF::assembly::arm::REG::FPSCR_RM) + .value("FPSID", LIEF::assembly::arm::REG::FPSID) + .value("ITSTATE", LIEF::assembly::arm::REG::ITSTATE) + .value("LR", LIEF::assembly::arm::REG::LR) + .value("PC", LIEF::assembly::arm::REG::PC) + .value("RA_AUTH_CODE", LIEF::assembly::arm::REG::RA_AUTH_CODE) + .value("SP", LIEF::assembly::arm::REG::SP) + .value("SPSR", LIEF::assembly::arm::REG::SPSR) + .value("VPR", LIEF::assembly::arm::REG::VPR) + .value("ZR", LIEF::assembly::arm::REG::ZR) + .value("D0", LIEF::assembly::arm::REG::D0) + .value("D1", LIEF::assembly::arm::REG::D1) + .value("D2", LIEF::assembly::arm::REG::D2) + .value("D3", LIEF::assembly::arm::REG::D3) + .value("D4", LIEF::assembly::arm::REG::D4) + .value("D5", LIEF::assembly::arm::REG::D5) + .value("D6", LIEF::assembly::arm::REG::D6) + .value("D7", LIEF::assembly::arm::REG::D7) + .value("D8", LIEF::assembly::arm::REG::D8) + .value("D9", LIEF::assembly::arm::REG::D9) + .value("D10", LIEF::assembly::arm::REG::D10) + .value("D11", LIEF::assembly::arm::REG::D11) + .value("D12", LIEF::assembly::arm::REG::D12) + .value("D13", LIEF::assembly::arm::REG::D13) + .value("D14", LIEF::assembly::arm::REG::D14) + .value("D15", LIEF::assembly::arm::REG::D15) + .value("D16", LIEF::assembly::arm::REG::D16) + .value("D17", LIEF::assembly::arm::REG::D17) + .value("D18", LIEF::assembly::arm::REG::D18) + .value("D19", LIEF::assembly::arm::REG::D19) + .value("D20", LIEF::assembly::arm::REG::D20) + .value("D21", LIEF::assembly::arm::REG::D21) + .value("D22", LIEF::assembly::arm::REG::D22) + .value("D23", LIEF::assembly::arm::REG::D23) + .value("D24", LIEF::assembly::arm::REG::D24) + .value("D25", LIEF::assembly::arm::REG::D25) + .value("D26", LIEF::assembly::arm::REG::D26) + .value("D27", LIEF::assembly::arm::REG::D27) + .value("D28", LIEF::assembly::arm::REG::D28) + .value("D29", LIEF::assembly::arm::REG::D29) + .value("D30", LIEF::assembly::arm::REG::D30) + .value("D31", LIEF::assembly::arm::REG::D31) + .value("FPINST2", LIEF::assembly::arm::REG::FPINST2) + .value("MVFR0", LIEF::assembly::arm::REG::MVFR0) + .value("MVFR1", LIEF::assembly::arm::REG::MVFR1) + .value("MVFR2", LIEF::assembly::arm::REG::MVFR2) + .value("P0", LIEF::assembly::arm::REG::P0) + .value("Q0", LIEF::assembly::arm::REG::Q0) + .value("Q1", LIEF::assembly::arm::REG::Q1) + .value("Q2", LIEF::assembly::arm::REG::Q2) + .value("Q3", LIEF::assembly::arm::REG::Q3) + .value("Q4", LIEF::assembly::arm::REG::Q4) + .value("Q5", LIEF::assembly::arm::REG::Q5) + .value("Q6", LIEF::assembly::arm::REG::Q6) + .value("Q7", LIEF::assembly::arm::REG::Q7) + .value("Q8", LIEF::assembly::arm::REG::Q8) + .value("Q9", LIEF::assembly::arm::REG::Q9) + .value("Q10", LIEF::assembly::arm::REG::Q10) + .value("Q11", LIEF::assembly::arm::REG::Q11) + .value("Q12", LIEF::assembly::arm::REG::Q12) + .value("Q13", LIEF::assembly::arm::REG::Q13) + .value("Q14", LIEF::assembly::arm::REG::Q14) + .value("Q15", LIEF::assembly::arm::REG::Q15) + .value("R0", LIEF::assembly::arm::REG::R0) + .value("R1", LIEF::assembly::arm::REG::R1) + .value("R2", LIEF::assembly::arm::REG::R2) + .value("R3", LIEF::assembly::arm::REG::R3) + .value("R4", LIEF::assembly::arm::REG::R4) + .value("R5", LIEF::assembly::arm::REG::R5) + .value("R6", LIEF::assembly::arm::REG::R6) + .value("R7", LIEF::assembly::arm::REG::R7) + .value("R8", LIEF::assembly::arm::REG::R8) + .value("R9", LIEF::assembly::arm::REG::R9) + .value("R10", LIEF::assembly::arm::REG::R10) + .value("R11", LIEF::assembly::arm::REG::R11) + .value("R12", LIEF::assembly::arm::REG::R12) + .value("S0", LIEF::assembly::arm::REG::S0) + .value("S1", LIEF::assembly::arm::REG::S1) + .value("S2", LIEF::assembly::arm::REG::S2) + .value("S3", LIEF::assembly::arm::REG::S3) + .value("S4", LIEF::assembly::arm::REG::S4) + .value("S5", LIEF::assembly::arm::REG::S5) + .value("S6", LIEF::assembly::arm::REG::S6) + .value("S7", LIEF::assembly::arm::REG::S7) + .value("S8", LIEF::assembly::arm::REG::S8) + .value("S9", LIEF::assembly::arm::REG::S9) + .value("S10", LIEF::assembly::arm::REG::S10) + .value("S11", LIEF::assembly::arm::REG::S11) + .value("S12", LIEF::assembly::arm::REG::S12) + .value("S13", LIEF::assembly::arm::REG::S13) + .value("S14", LIEF::assembly::arm::REG::S14) + .value("S15", LIEF::assembly::arm::REG::S15) + .value("S16", LIEF::assembly::arm::REG::S16) + .value("S17", LIEF::assembly::arm::REG::S17) + .value("S18", LIEF::assembly::arm::REG::S18) + .value("S19", LIEF::assembly::arm::REG::S19) + .value("S20", LIEF::assembly::arm::REG::S20) + .value("S21", LIEF::assembly::arm::REG::S21) + .value("S22", LIEF::assembly::arm::REG::S22) + .value("S23", LIEF::assembly::arm::REG::S23) + .value("S24", LIEF::assembly::arm::REG::S24) + .value("S25", LIEF::assembly::arm::REG::S25) + .value("S26", LIEF::assembly::arm::REG::S26) + .value("S27", LIEF::assembly::arm::REG::S27) + .value("S28", LIEF::assembly::arm::REG::S28) + .value("S29", LIEF::assembly::arm::REG::S29) + .value("S30", LIEF::assembly::arm::REG::S30) + .value("S31", LIEF::assembly::arm::REG::S31) + .value("D0_D2", LIEF::assembly::arm::REG::D0_D2) + .value("D1_D3", LIEF::assembly::arm::REG::D1_D3) + .value("D2_D4", LIEF::assembly::arm::REG::D2_D4) + .value("D3_D5", LIEF::assembly::arm::REG::D3_D5) + .value("D4_D6", LIEF::assembly::arm::REG::D4_D6) + .value("D5_D7", LIEF::assembly::arm::REG::D5_D7) + .value("D6_D8", LIEF::assembly::arm::REG::D6_D8) + .value("D7_D9", LIEF::assembly::arm::REG::D7_D9) + .value("D8_D10", LIEF::assembly::arm::REG::D8_D10) + .value("D9_D11", LIEF::assembly::arm::REG::D9_D11) + .value("D10_D12", LIEF::assembly::arm::REG::D10_D12) + .value("D11_D13", LIEF::assembly::arm::REG::D11_D13) + .value("D12_D14", LIEF::assembly::arm::REG::D12_D14) + .value("D13_D15", LIEF::assembly::arm::REG::D13_D15) + .value("D14_D16", LIEF::assembly::arm::REG::D14_D16) + .value("D15_D17", LIEF::assembly::arm::REG::D15_D17) + .value("D16_D18", LIEF::assembly::arm::REG::D16_D18) + .value("D17_D19", LIEF::assembly::arm::REG::D17_D19) + .value("D18_D20", LIEF::assembly::arm::REG::D18_D20) + .value("D19_D21", LIEF::assembly::arm::REG::D19_D21) + .value("D20_D22", LIEF::assembly::arm::REG::D20_D22) + .value("D21_D23", LIEF::assembly::arm::REG::D21_D23) + .value("D22_D24", LIEF::assembly::arm::REG::D22_D24) + .value("D23_D25", LIEF::assembly::arm::REG::D23_D25) + .value("D24_D26", LIEF::assembly::arm::REG::D24_D26) + .value("D25_D27", LIEF::assembly::arm::REG::D25_D27) + .value("D26_D28", LIEF::assembly::arm::REG::D26_D28) + .value("D27_D29", LIEF::assembly::arm::REG::D27_D29) + .value("D28_D30", LIEF::assembly::arm::REG::D28_D30) + .value("D29_D31", LIEF::assembly::arm::REG::D29_D31) + .value("Q0_Q1", LIEF::assembly::arm::REG::Q0_Q1) + .value("Q1_Q2", LIEF::assembly::arm::REG::Q1_Q2) + .value("Q2_Q3", LIEF::assembly::arm::REG::Q2_Q3) + .value("Q3_Q4", LIEF::assembly::arm::REG::Q3_Q4) + .value("Q4_Q5", LIEF::assembly::arm::REG::Q4_Q5) + .value("Q5_Q6", LIEF::assembly::arm::REG::Q5_Q6) + .value("Q6_Q7", LIEF::assembly::arm::REG::Q6_Q7) + .value("Q7_Q8", LIEF::assembly::arm::REG::Q7_Q8) + .value("Q8_Q9", LIEF::assembly::arm::REG::Q8_Q9) + .value("Q9_Q10", LIEF::assembly::arm::REG::Q9_Q10) + .value("Q10_Q11", LIEF::assembly::arm::REG::Q10_Q11) + .value("Q11_Q12", LIEF::assembly::arm::REG::Q11_Q12) + .value("Q12_Q13", LIEF::assembly::arm::REG::Q12_Q13) + .value("Q13_Q14", LIEF::assembly::arm::REG::Q13_Q14) + .value("Q14_Q15", LIEF::assembly::arm::REG::Q14_Q15) + .value("Q0_Q1_Q2_Q3", LIEF::assembly::arm::REG::Q0_Q1_Q2_Q3) + .value("Q1_Q2_Q3_Q4", LIEF::assembly::arm::REG::Q1_Q2_Q3_Q4) + .value("Q2_Q3_Q4_Q5", LIEF::assembly::arm::REG::Q2_Q3_Q4_Q5) + .value("Q3_Q4_Q5_Q6", LIEF::assembly::arm::REG::Q3_Q4_Q5_Q6) + .value("Q4_Q5_Q6_Q7", LIEF::assembly::arm::REG::Q4_Q5_Q6_Q7) + .value("Q5_Q6_Q7_Q8", LIEF::assembly::arm::REG::Q5_Q6_Q7_Q8) + .value("Q6_Q7_Q8_Q9", LIEF::assembly::arm::REG::Q6_Q7_Q8_Q9) + .value("Q7_Q8_Q9_Q10", LIEF::assembly::arm::REG::Q7_Q8_Q9_Q10) + .value("Q8_Q9_Q10_Q11", LIEF::assembly::arm::REG::Q8_Q9_Q10_Q11) + .value("Q9_Q10_Q11_Q12", LIEF::assembly::arm::REG::Q9_Q10_Q11_Q12) + .value("Q10_Q11_Q12_Q13", LIEF::assembly::arm::REG::Q10_Q11_Q12_Q13) + .value("Q11_Q12_Q13_Q14", LIEF::assembly::arm::REG::Q11_Q12_Q13_Q14) + .value("Q12_Q13_Q14_Q15", LIEF::assembly::arm::REG::Q12_Q13_Q14_Q15) + .value("R0_R1", LIEF::assembly::arm::REG::R0_R1) + .value("R2_R3", LIEF::assembly::arm::REG::R2_R3) + .value("R4_R5", LIEF::assembly::arm::REG::R4_R5) + .value("R6_R7", LIEF::assembly::arm::REG::R6_R7) + .value("R8_R9", LIEF::assembly::arm::REG::R8_R9) + .value("R10_R11", LIEF::assembly::arm::REG::R10_R11) + .value("R12_SP", LIEF::assembly::arm::REG::R12_SP) + .value("D0_D1_D2", LIEF::assembly::arm::REG::D0_D1_D2) + .value("D1_D2_D3", LIEF::assembly::arm::REG::D1_D2_D3) + .value("D2_D3_D4", LIEF::assembly::arm::REG::D2_D3_D4) + .value("D3_D4_D5", LIEF::assembly::arm::REG::D3_D4_D5) + .value("D4_D5_D6", LIEF::assembly::arm::REG::D4_D5_D6) + .value("D5_D6_D7", LIEF::assembly::arm::REG::D5_D6_D7) + .value("D6_D7_D8", LIEF::assembly::arm::REG::D6_D7_D8) + .value("D7_D8_D9", LIEF::assembly::arm::REG::D7_D8_D9) + .value("D8_D9_D10", LIEF::assembly::arm::REG::D8_D9_D10) + .value("D9_D10_D11", LIEF::assembly::arm::REG::D9_D10_D11) + .value("D10_D11_D12", LIEF::assembly::arm::REG::D10_D11_D12) + .value("D11_D12_D13", LIEF::assembly::arm::REG::D11_D12_D13) + .value("D12_D13_D14", LIEF::assembly::arm::REG::D12_D13_D14) + .value("D13_D14_D15", LIEF::assembly::arm::REG::D13_D14_D15) + .value("D14_D15_D16", LIEF::assembly::arm::REG::D14_D15_D16) + .value("D15_D16_D17", LIEF::assembly::arm::REG::D15_D16_D17) + .value("D16_D17_D18", LIEF::assembly::arm::REG::D16_D17_D18) + .value("D17_D18_D19", LIEF::assembly::arm::REG::D17_D18_D19) + .value("D18_D19_D20", LIEF::assembly::arm::REG::D18_D19_D20) + .value("D19_D20_D21", LIEF::assembly::arm::REG::D19_D20_D21) + .value("D20_D21_D22", LIEF::assembly::arm::REG::D20_D21_D22) + .value("D21_D22_D23", LIEF::assembly::arm::REG::D21_D22_D23) + .value("D22_D23_D24", LIEF::assembly::arm::REG::D22_D23_D24) + .value("D23_D24_D25", LIEF::assembly::arm::REG::D23_D24_D25) + .value("D24_D25_D26", LIEF::assembly::arm::REG::D24_D25_D26) + .value("D25_D26_D27", LIEF::assembly::arm::REG::D25_D26_D27) + .value("D26_D27_D28", LIEF::assembly::arm::REG::D26_D27_D28) + .value("D27_D28_D29", LIEF::assembly::arm::REG::D27_D28_D29) + .value("D28_D29_D30", LIEF::assembly::arm::REG::D28_D29_D30) + .value("D29_D30_D31", LIEF::assembly::arm::REG::D29_D30_D31) + .value("D0_D2_D4", LIEF::assembly::arm::REG::D0_D2_D4) + .value("D1_D3_D5", LIEF::assembly::arm::REG::D1_D3_D5) + .value("D2_D4_D6", LIEF::assembly::arm::REG::D2_D4_D6) + .value("D3_D5_D7", LIEF::assembly::arm::REG::D3_D5_D7) + .value("D4_D6_D8", LIEF::assembly::arm::REG::D4_D6_D8) + .value("D5_D7_D9", LIEF::assembly::arm::REG::D5_D7_D9) + .value("D6_D8_D10", LIEF::assembly::arm::REG::D6_D8_D10) + .value("D7_D9_D11", LIEF::assembly::arm::REG::D7_D9_D11) + .value("D8_D10_D12", LIEF::assembly::arm::REG::D8_D10_D12) + .value("D9_D11_D13", LIEF::assembly::arm::REG::D9_D11_D13) + .value("D10_D12_D14", LIEF::assembly::arm::REG::D10_D12_D14) + .value("D11_D13_D15", LIEF::assembly::arm::REG::D11_D13_D15) + .value("D12_D14_D16", LIEF::assembly::arm::REG::D12_D14_D16) + .value("D13_D15_D17", LIEF::assembly::arm::REG::D13_D15_D17) + .value("D14_D16_D18", LIEF::assembly::arm::REG::D14_D16_D18) + .value("D15_D17_D19", LIEF::assembly::arm::REG::D15_D17_D19) + .value("D16_D18_D20", LIEF::assembly::arm::REG::D16_D18_D20) + .value("D17_D19_D21", LIEF::assembly::arm::REG::D17_D19_D21) + .value("D18_D20_D22", LIEF::assembly::arm::REG::D18_D20_D22) + .value("D19_D21_D23", LIEF::assembly::arm::REG::D19_D21_D23) + .value("D20_D22_D24", LIEF::assembly::arm::REG::D20_D22_D24) + .value("D21_D23_D25", LIEF::assembly::arm::REG::D21_D23_D25) + .value("D22_D24_D26", LIEF::assembly::arm::REG::D22_D24_D26) + .value("D23_D25_D27", LIEF::assembly::arm::REG::D23_D25_D27) + .value("D24_D26_D28", LIEF::assembly::arm::REG::D24_D26_D28) + .value("D25_D27_D29", LIEF::assembly::arm::REG::D25_D27_D29) + .value("D26_D28_D30", LIEF::assembly::arm::REG::D26_D28_D30) + .value("D27_D29_D31", LIEF::assembly::arm::REG::D27_D29_D31) + .value("D0_D2_D4_D6", LIEF::assembly::arm::REG::D0_D2_D4_D6) + .value("D1_D3_D5_D7", LIEF::assembly::arm::REG::D1_D3_D5_D7) + .value("D2_D4_D6_D8", LIEF::assembly::arm::REG::D2_D4_D6_D8) + .value("D3_D5_D7_D9", LIEF::assembly::arm::REG::D3_D5_D7_D9) + .value("D4_D6_D8_D10", LIEF::assembly::arm::REG::D4_D6_D8_D10) + .value("D5_D7_D9_D11", LIEF::assembly::arm::REG::D5_D7_D9_D11) + .value("D6_D8_D10_D12", LIEF::assembly::arm::REG::D6_D8_D10_D12) + .value("D7_D9_D11_D13", LIEF::assembly::arm::REG::D7_D9_D11_D13) + .value("D8_D10_D12_D14", LIEF::assembly::arm::REG::D8_D10_D12_D14) + .value("D9_D11_D13_D15", LIEF::assembly::arm::REG::D9_D11_D13_D15) + .value("D10_D12_D14_D16", LIEF::assembly::arm::REG::D10_D12_D14_D16) + .value("D11_D13_D15_D17", LIEF::assembly::arm::REG::D11_D13_D15_D17) + .value("D12_D14_D16_D18", LIEF::assembly::arm::REG::D12_D14_D16_D18) + .value("D13_D15_D17_D19", LIEF::assembly::arm::REG::D13_D15_D17_D19) + .value("D14_D16_D18_D20", LIEF::assembly::arm::REG::D14_D16_D18_D20) + .value("D15_D17_D19_D21", LIEF::assembly::arm::REG::D15_D17_D19_D21) + .value("D16_D18_D20_D22", LIEF::assembly::arm::REG::D16_D18_D20_D22) + .value("D17_D19_D21_D23", LIEF::assembly::arm::REG::D17_D19_D21_D23) + .value("D18_D20_D22_D24", LIEF::assembly::arm::REG::D18_D20_D22_D24) + .value("D19_D21_D23_D25", LIEF::assembly::arm::REG::D19_D21_D23_D25) + .value("D20_D22_D24_D26", LIEF::assembly::arm::REG::D20_D22_D24_D26) + .value("D21_D23_D25_D27", LIEF::assembly::arm::REG::D21_D23_D25_D27) + .value("D22_D24_D26_D28", LIEF::assembly::arm::REG::D22_D24_D26_D28) + .value("D23_D25_D27_D29", LIEF::assembly::arm::REG::D23_D25_D27_D29) + .value("D24_D26_D28_D30", LIEF::assembly::arm::REG::D24_D26_D28_D30) + .value("D25_D27_D29_D31", LIEF::assembly::arm::REG::D25_D27_D29_D31) + .value("D1_D2", LIEF::assembly::arm::REG::D1_D2) + .value("D3_D4", LIEF::assembly::arm::REG::D3_D4) + .value("D5_D6", LIEF::assembly::arm::REG::D5_D6) + .value("D7_D8", LIEF::assembly::arm::REG::D7_D8) + .value("D9_D10", LIEF::assembly::arm::REG::D9_D10) + .value("D11_D12", LIEF::assembly::arm::REG::D11_D12) + .value("D13_D14", LIEF::assembly::arm::REG::D13_D14) + .value("D15_D16", LIEF::assembly::arm::REG::D15_D16) + .value("D17_D18", LIEF::assembly::arm::REG::D17_D18) + .value("D19_D20", LIEF::assembly::arm::REG::D19_D20) + .value("D21_D22", LIEF::assembly::arm::REG::D21_D22) + .value("D23_D24", LIEF::assembly::arm::REG::D23_D24) + .value("D25_D26", LIEF::assembly::arm::REG::D25_D26) + .value("D27_D28", LIEF::assembly::arm::REG::D27_D28) + .value("D29_D30", LIEF::assembly::arm::REG::D29_D30) + .value("D1_D2_D3_D4", LIEF::assembly::arm::REG::D1_D2_D3_D4) + .value("D3_D4_D5_D6", LIEF::assembly::arm::REG::D3_D4_D5_D6) + .value("D5_D6_D7_D8", LIEF::assembly::arm::REG::D5_D6_D7_D8) + .value("D7_D8_D9_D10", LIEF::assembly::arm::REG::D7_D8_D9_D10) + .value("D9_D10_D11_D12", LIEF::assembly::arm::REG::D9_D10_D11_D12) + .value("D11_D12_D13_D14", LIEF::assembly::arm::REG::D11_D12_D13_D14) + .value("D13_D14_D15_D16", LIEF::assembly::arm::REG::D13_D14_D15_D16) + .value("D15_D16_D17_D18", LIEF::assembly::arm::REG::D15_D16_D17_D18) + .value("D17_D18_D19_D20", LIEF::assembly::arm::REG::D17_D18_D19_D20) + .value("D19_D20_D21_D22", LIEF::assembly::arm::REG::D19_D20_D21_D22) + .value("D21_D22_D23_D24", LIEF::assembly::arm::REG::D21_D22_D23_D24) + .value("D23_D24_D25_D26", LIEF::assembly::arm::REG::D23_D24_D25_D26) + .value("D25_D26_D27_D28", LIEF::assembly::arm::REG::D25_D26_D27_D28) + .value("D27_D28_D29_D30", LIEF::assembly::arm::REG::D27_D28_D29_D30) + .value("NUM_TARGET_REGS", LIEF::assembly::arm::REG::NUM_TARGET_REGS) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/CMakeLists.txt b/vendor/lief/api/python/src/asm/ebpf/CMakeLists.txt new file mode 100644 index 0000000..c5e4e70 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyOperand.cpp + pyRegister.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/ebpf/init.cpp b/vendor/lief/api/python/src/asm/ebpf/init.cpp new file mode 100644 index 0000000..8679d80 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/init.cpp @@ -0,0 +1,18 @@ +#include "asm/ebpf/init.hpp" +namespace LIEF::assembly::ebpf { +enum class OPCODE; +enum class REG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::ebpf::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("ebpf"); + + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/init.hpp b/vendor/lief/api/python/src/asm/ebpf/init.hpp new file mode 100644 index 0000000..ebb6bf8 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_EBPF_INIT_H +#define PY_LIEF_ASM_EBPF_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::ebpf::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/ebpf/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/ebpf/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/ebpf/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/ebpf/operands/pyImmediate.cpp new file mode 100644 index 0000000..13d849a --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/operands/pyImmediate.cpp @@ -0,0 +1,29 @@ +#include "asm/ebpf/init.hpp" +#include "LIEF/asm/ebpf/operands/Immediate.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + + For instance: + + .. code-block:: text + + r1 = 8 + | + +---> Immediate(8) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/ebpf/operands/pyMemory.cpp new file mode 100644 index 0000000..86f2076 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/operands/pyMemory.cpp @@ -0,0 +1,40 @@ +#include "asm/ebpf/init.hpp" +#include "LIEF/asm/ebpf/operands/Memory.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + .. code-block:: text + + *(u64 *)(r1 + 8) = r2 + | | + | +-----> Displacement: 8 + | + +----------> Base: r1 + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("base", "displacement"); + + obj + .def_prop_ro("base", &operands::Memory::base, + R"doc( + The base register. + + For ``*(u64 *)(r1 + 8)`` it would return ``r1``. + )doc"_doc + ) + .def_prop_ro("displacement", &operands::Memory::displacement, + R"doc( + The displacement value. + + For ``*(u64 *)(r1 + 8)`` it would return ``8``. + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/ebpf/operands/pyPCRelative.cpp new file mode 100644 index 0000000..85d7109 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/operands/pyPCRelative.cpp @@ -0,0 +1,30 @@ +#include "asm/ebpf/init.hpp" +#include "LIEF/asm/ebpf/operands/PCRelative.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a PC-relative operand. + + .. code-block:: text + + if r1 == 0 goto +5 + | + v + PC Relative operand + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &ebpf::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``pc`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/ebpf/operands/pyRegister.cpp new file mode 100644 index 0000000..9446351 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/operands/pyRegister.cpp @@ -0,0 +1,33 @@ +#include "asm/ebpf/init.hpp" +#include "LIEF/asm/ebpf/operands/Register.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + For instance: + + .. code-block:: text + + r0 = r1 + | | + | +---------> Register(r1) + | + +--------------> Register(r0) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &ebpf::operands::Register::value, + R"doc( + The effective :class:`lief.assembly.ebpf.REG` wrapped by this operand + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/pyInstruction.cpp b/vendor/lief/api/python/src/asm/ebpf/pyInstruction.cpp new file mode 100644 index 0000000..dd05c82 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/pyInstruction.cpp @@ -0,0 +1,34 @@ +#include "LIEF/asm/ebpf/Instruction.hpp" +#include "LIEF/asm/ebpf/Operand.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include "asm/ebpf/init.hpp" + +#include + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents an eBPF instruction)doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("operands", [] (const ebpf::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/pyOpcode.cpp b/vendor/lief/api/python/src/asm/ebpf/pyOpcode.cpp new file mode 100644 index 0000000..0822918 --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/pyOpcode.cpp @@ -0,0 +1,535 @@ +#include "asm/ebpf/init.hpp" + +#include "LIEF/asm/ebpf/opcodes.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::ebpf::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::ebpf::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::ebpf::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::ebpf::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::ebpf::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::ebpf::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::ebpf::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::ebpf::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::ebpf::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::ebpf::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::ebpf::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::ebpf::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::ebpf::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::ebpf::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::ebpf::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::ebpf::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::ebpf::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::ebpf::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::ebpf::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::ebpf::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::ebpf::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::ebpf::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::ebpf::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::ebpf::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::ebpf::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::ebpf::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::ebpf::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::ebpf::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::ebpf::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::ebpf::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::ebpf::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::ebpf::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::ebpf::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::ebpf::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::ebpf::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::ebpf::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::ebpf::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::ebpf::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::ebpf::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::ebpf::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::ebpf::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::ebpf::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::ebpf::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::ebpf::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::ebpf::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::ebpf::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::ebpf::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::ebpf::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::ebpf::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::ebpf::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::ebpf::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::ebpf::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::ebpf::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::ebpf::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::ebpf::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::ebpf::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::ebpf::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::ebpf::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::ebpf::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::ebpf::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::ebpf::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::ebpf::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::ebpf::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::ebpf::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::ebpf::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::ebpf::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::ebpf::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::ebpf::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::ebpf::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::ebpf::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::ebpf::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::ebpf::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::ebpf::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::ebpf::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::ebpf::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::ebpf::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::ebpf::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::ebpf::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::ebpf::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::ebpf::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::ebpf::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::ebpf::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::ebpf::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::ebpf::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::ebpf::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::ebpf::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::ebpf::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::ebpf::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::ebpf::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::ebpf::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::ebpf::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::ebpf::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::ebpf::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::ebpf::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::ebpf::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::ebpf::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::ebpf::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::ebpf::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::ebpf::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::ebpf::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::ebpf::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::ebpf::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::ebpf::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::ebpf::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::ebpf::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::ebpf::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::ebpf::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::ebpf::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::ebpf::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::ebpf::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::ebpf::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::ebpf::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::ebpf::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::ebpf::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::ebpf::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::ebpf::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::ebpf::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::ebpf::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::ebpf::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::ebpf::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::ebpf::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::ebpf::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::ebpf::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::ebpf::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::ebpf::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::ebpf::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::ebpf::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::ebpf::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::ebpf::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::ebpf::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::ebpf::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::ebpf::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::ebpf::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::ebpf::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::ebpf::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::ebpf::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::ebpf::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::ebpf::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::ebpf::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::ebpf::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::ebpf::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::ebpf::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::ebpf::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::ebpf::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::ebpf::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::ebpf::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::ebpf::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::ebpf::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::ebpf::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::ebpf::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::ebpf::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::ebpf::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::ebpf::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::ebpf::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::ebpf::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::ebpf::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::ebpf::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::ebpf::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::ebpf::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::ebpf::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::ebpf::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::ebpf::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::ebpf::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::ebpf::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::ebpf::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::ebpf::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::ebpf::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::ebpf::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::ebpf::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::ebpf::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::ebpf::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::ebpf::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::ebpf::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::ebpf::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::ebpf::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::ebpf::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::ebpf::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::ebpf::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::ebpf::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::ebpf::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::ebpf::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::ebpf::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::ebpf::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::ebpf::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::ebpf::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::ebpf::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::ebpf::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::ebpf::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::ebpf::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::ebpf::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::ebpf::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::ebpf::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::ebpf::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::ebpf::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::ebpf::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::ebpf::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::ebpf::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::ebpf::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::ebpf::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::ebpf::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::ebpf::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::ebpf::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::ebpf::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::ebpf::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::ebpf::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::ebpf::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::ebpf::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::ebpf::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::ebpf::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::ebpf::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::ebpf::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::ebpf::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::ebpf::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::ebpf::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::ebpf::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::ebpf::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::ebpf::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::ebpf::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::ebpf::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::ebpf::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::ebpf::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::ebpf::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::ebpf::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::ebpf::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::ebpf::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::ebpf::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::ebpf::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::ebpf::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::ebpf::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::ebpf::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::ebpf::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::ebpf::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::ebpf::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::ebpf::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::ebpf::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::ebpf::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::ebpf::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::ebpf::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::ebpf::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::ebpf::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::ebpf::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::ebpf::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::ebpf::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::ebpf::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::ebpf::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::ebpf::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::ebpf::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::ebpf::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::ebpf::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::ebpf::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::ebpf::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::ebpf::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::ebpf::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::ebpf::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::ebpf::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::ebpf::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::ebpf::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::ebpf::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::ebpf::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::ebpf::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::ebpf::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::ebpf::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::ebpf::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::ebpf::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::ebpf::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::ebpf::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::ebpf::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::ebpf::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::ebpf::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::ebpf::OPCODE::G_UBFX) + .value("ADJCALLSTACKDOWN", LIEF::assembly::ebpf::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::ebpf::OPCODE::ADJCALLSTACKUP) + .value("FI_ri", LIEF::assembly::ebpf::OPCODE::FI_ri) + .value("LDIMM64", LIEF::assembly::ebpf::OPCODE::LDIMM64) + .value("MEMCPY", LIEF::assembly::ebpf::OPCODE::MEMCPY) + .value("Select", LIEF::assembly::ebpf::OPCODE::Select) + .value("Select_32", LIEF::assembly::ebpf::OPCODE::Select_32) + .value("Select_32_64", LIEF::assembly::ebpf::OPCODE::Select_32_64) + .value("Select_64_32", LIEF::assembly::ebpf::OPCODE::Select_64_32) + .value("Select_Ri", LIEF::assembly::ebpf::OPCODE::Select_Ri) + .value("Select_Ri_32", LIEF::assembly::ebpf::OPCODE::Select_Ri_32) + .value("Select_Ri_32_64", LIEF::assembly::ebpf::OPCODE::Select_Ri_32_64) + .value("Select_Ri_64_32", LIEF::assembly::ebpf::OPCODE::Select_Ri_64_32) + .value("ADDR_SPACE_CAST", LIEF::assembly::ebpf::OPCODE::ADDR_SPACE_CAST) + .value("ADD_ri", LIEF::assembly::ebpf::OPCODE::ADD_ri) + .value("ADD_ri_32", LIEF::assembly::ebpf::OPCODE::ADD_ri_32) + .value("ADD_rr", LIEF::assembly::ebpf::OPCODE::ADD_rr) + .value("ADD_rr_32", LIEF::assembly::ebpf::OPCODE::ADD_rr_32) + .value("AND_ri", LIEF::assembly::ebpf::OPCODE::AND_ri) + .value("AND_ri_32", LIEF::assembly::ebpf::OPCODE::AND_ri_32) + .value("AND_rr", LIEF::assembly::ebpf::OPCODE::AND_rr) + .value("AND_rr_32", LIEF::assembly::ebpf::OPCODE::AND_rr_32) + .value("BE16", LIEF::assembly::ebpf::OPCODE::BE16) + .value("BE32", LIEF::assembly::ebpf::OPCODE::BE32) + .value("BE64", LIEF::assembly::ebpf::OPCODE::BE64) + .value("BSWAP16", LIEF::assembly::ebpf::OPCODE::BSWAP16) + .value("BSWAP32", LIEF::assembly::ebpf::OPCODE::BSWAP32) + .value("BSWAP64", LIEF::assembly::ebpf::OPCODE::BSWAP64) + .value("CMPXCHGD", LIEF::assembly::ebpf::OPCODE::CMPXCHGD) + .value("CMPXCHGW32", LIEF::assembly::ebpf::OPCODE::CMPXCHGW32) + .value("CORE_LD32", LIEF::assembly::ebpf::OPCODE::CORE_LD32) + .value("CORE_LD64", LIEF::assembly::ebpf::OPCODE::CORE_LD64) + .value("CORE_SHIFT", LIEF::assembly::ebpf::OPCODE::CORE_SHIFT) + .value("CORE_ST", LIEF::assembly::ebpf::OPCODE::CORE_ST) + .value("DIV_ri", LIEF::assembly::ebpf::OPCODE::DIV_ri) + .value("DIV_ri_32", LIEF::assembly::ebpf::OPCODE::DIV_ri_32) + .value("DIV_rr", LIEF::assembly::ebpf::OPCODE::DIV_rr) + .value("DIV_rr_32", LIEF::assembly::ebpf::OPCODE::DIV_rr_32) + .value("JAL", LIEF::assembly::ebpf::OPCODE::JAL) + .value("JALX", LIEF::assembly::ebpf::OPCODE::JALX) + .value("JCOND", LIEF::assembly::ebpf::OPCODE::JCOND) + .value("JEQ_ri", LIEF::assembly::ebpf::OPCODE::JEQ_ri) + .value("JEQ_ri_32", LIEF::assembly::ebpf::OPCODE::JEQ_ri_32) + .value("JEQ_rr", LIEF::assembly::ebpf::OPCODE::JEQ_rr) + .value("JEQ_rr_32", LIEF::assembly::ebpf::OPCODE::JEQ_rr_32) + .value("JMP", LIEF::assembly::ebpf::OPCODE::JMP) + .value("JMPL", LIEF::assembly::ebpf::OPCODE::JMPL) + .value("JNE_ri", LIEF::assembly::ebpf::OPCODE::JNE_ri) + .value("JNE_ri_32", LIEF::assembly::ebpf::OPCODE::JNE_ri_32) + .value("JNE_rr", LIEF::assembly::ebpf::OPCODE::JNE_rr) + .value("JNE_rr_32", LIEF::assembly::ebpf::OPCODE::JNE_rr_32) + .value("JSET_ri", LIEF::assembly::ebpf::OPCODE::JSET_ri) + .value("JSET_ri_32", LIEF::assembly::ebpf::OPCODE::JSET_ri_32) + .value("JSET_rr", LIEF::assembly::ebpf::OPCODE::JSET_rr) + .value("JSET_rr_32", LIEF::assembly::ebpf::OPCODE::JSET_rr_32) + .value("JSGE_ri", LIEF::assembly::ebpf::OPCODE::JSGE_ri) + .value("JSGE_ri_32", LIEF::assembly::ebpf::OPCODE::JSGE_ri_32) + .value("JSGE_rr", LIEF::assembly::ebpf::OPCODE::JSGE_rr) + .value("JSGE_rr_32", LIEF::assembly::ebpf::OPCODE::JSGE_rr_32) + .value("JSGT_ri", LIEF::assembly::ebpf::OPCODE::JSGT_ri) + .value("JSGT_ri_32", LIEF::assembly::ebpf::OPCODE::JSGT_ri_32) + .value("JSGT_rr", LIEF::assembly::ebpf::OPCODE::JSGT_rr) + .value("JSGT_rr_32", LIEF::assembly::ebpf::OPCODE::JSGT_rr_32) + .value("JSLE_ri", LIEF::assembly::ebpf::OPCODE::JSLE_ri) + .value("JSLE_ri_32", LIEF::assembly::ebpf::OPCODE::JSLE_ri_32) + .value("JSLE_rr", LIEF::assembly::ebpf::OPCODE::JSLE_rr) + .value("JSLE_rr_32", LIEF::assembly::ebpf::OPCODE::JSLE_rr_32) + .value("JSLT_ri", LIEF::assembly::ebpf::OPCODE::JSLT_ri) + .value("JSLT_ri_32", LIEF::assembly::ebpf::OPCODE::JSLT_ri_32) + .value("JSLT_rr", LIEF::assembly::ebpf::OPCODE::JSLT_rr) + .value("JSLT_rr_32", LIEF::assembly::ebpf::OPCODE::JSLT_rr_32) + .value("JUGE_ri", LIEF::assembly::ebpf::OPCODE::JUGE_ri) + .value("JUGE_ri_32", LIEF::assembly::ebpf::OPCODE::JUGE_ri_32) + .value("JUGE_rr", LIEF::assembly::ebpf::OPCODE::JUGE_rr) + .value("JUGE_rr_32", LIEF::assembly::ebpf::OPCODE::JUGE_rr_32) + .value("JUGT_ri", LIEF::assembly::ebpf::OPCODE::JUGT_ri) + .value("JUGT_ri_32", LIEF::assembly::ebpf::OPCODE::JUGT_ri_32) + .value("JUGT_rr", LIEF::assembly::ebpf::OPCODE::JUGT_rr) + .value("JUGT_rr_32", LIEF::assembly::ebpf::OPCODE::JUGT_rr_32) + .value("JULE_ri", LIEF::assembly::ebpf::OPCODE::JULE_ri) + .value("JULE_ri_32", LIEF::assembly::ebpf::OPCODE::JULE_ri_32) + .value("JULE_rr", LIEF::assembly::ebpf::OPCODE::JULE_rr) + .value("JULE_rr_32", LIEF::assembly::ebpf::OPCODE::JULE_rr_32) + .value("JULT_ri", LIEF::assembly::ebpf::OPCODE::JULT_ri) + .value("JULT_ri_32", LIEF::assembly::ebpf::OPCODE::JULT_ri_32) + .value("JULT_rr", LIEF::assembly::ebpf::OPCODE::JULT_rr) + .value("JULT_rr_32", LIEF::assembly::ebpf::OPCODE::JULT_rr_32) + .value("JX", LIEF::assembly::ebpf::OPCODE::JX) + .value("LDB", LIEF::assembly::ebpf::OPCODE::LDB) + .value("LDB32", LIEF::assembly::ebpf::OPCODE::LDB32) + .value("LDBACQ32", LIEF::assembly::ebpf::OPCODE::LDBACQ32) + .value("LDBSX", LIEF::assembly::ebpf::OPCODE::LDBSX) + .value("LDD", LIEF::assembly::ebpf::OPCODE::LDD) + .value("LDDACQ", LIEF::assembly::ebpf::OPCODE::LDDACQ) + .value("LDH", LIEF::assembly::ebpf::OPCODE::LDH) + .value("LDH32", LIEF::assembly::ebpf::OPCODE::LDH32) + .value("LDHACQ32", LIEF::assembly::ebpf::OPCODE::LDHACQ32) + .value("LDHSX", LIEF::assembly::ebpf::OPCODE::LDHSX) + .value("LDW", LIEF::assembly::ebpf::OPCODE::LDW) + .value("LDW32", LIEF::assembly::ebpf::OPCODE::LDW32) + .value("LDWACQ32", LIEF::assembly::ebpf::OPCODE::LDWACQ32) + .value("LDWSX", LIEF::assembly::ebpf::OPCODE::LDWSX) + .value("LD_ABS_B", LIEF::assembly::ebpf::OPCODE::LD_ABS_B) + .value("LD_ABS_H", LIEF::assembly::ebpf::OPCODE::LD_ABS_H) + .value("LD_ABS_W", LIEF::assembly::ebpf::OPCODE::LD_ABS_W) + .value("LD_IND_B", LIEF::assembly::ebpf::OPCODE::LD_IND_B) + .value("LD_IND_H", LIEF::assembly::ebpf::OPCODE::LD_IND_H) + .value("LD_IND_W", LIEF::assembly::ebpf::OPCODE::LD_IND_W) + .value("LD_imm64", LIEF::assembly::ebpf::OPCODE::LD_imm64) + .value("LD_pseudo", LIEF::assembly::ebpf::OPCODE::LD_pseudo) + .value("LE16", LIEF::assembly::ebpf::OPCODE::LE16) + .value("LE32", LIEF::assembly::ebpf::OPCODE::LE32) + .value("LE64", LIEF::assembly::ebpf::OPCODE::LE64) + .value("MOD_ri", LIEF::assembly::ebpf::OPCODE::MOD_ri) + .value("MOD_ri_32", LIEF::assembly::ebpf::OPCODE::MOD_ri_32) + .value("MOD_rr", LIEF::assembly::ebpf::OPCODE::MOD_rr) + .value("MOD_rr_32", LIEF::assembly::ebpf::OPCODE::MOD_rr_32) + .value("MOVSX_rr_16", LIEF::assembly::ebpf::OPCODE::MOVSX_rr_16) + .value("MOVSX_rr_32", LIEF::assembly::ebpf::OPCODE::MOVSX_rr_32) + .value("MOVSX_rr_32_16", LIEF::assembly::ebpf::OPCODE::MOVSX_rr_32_16) + .value("MOVSX_rr_32_8", LIEF::assembly::ebpf::OPCODE::MOVSX_rr_32_8) + .value("MOVSX_rr_8", LIEF::assembly::ebpf::OPCODE::MOVSX_rr_8) + .value("MOV_32_64", LIEF::assembly::ebpf::OPCODE::MOV_32_64) + .value("MOV_ri", LIEF::assembly::ebpf::OPCODE::MOV_ri) + .value("MOV_ri_32", LIEF::assembly::ebpf::OPCODE::MOV_ri_32) + .value("MOV_rr", LIEF::assembly::ebpf::OPCODE::MOV_rr) + .value("MOV_rr_32", LIEF::assembly::ebpf::OPCODE::MOV_rr_32) + .value("MUL_ri", LIEF::assembly::ebpf::OPCODE::MUL_ri) + .value("MUL_ri_32", LIEF::assembly::ebpf::OPCODE::MUL_ri_32) + .value("MUL_rr", LIEF::assembly::ebpf::OPCODE::MUL_rr) + .value("MUL_rr_32", LIEF::assembly::ebpf::OPCODE::MUL_rr_32) + .value("NEG_32", LIEF::assembly::ebpf::OPCODE::NEG_32) + .value("NEG_64", LIEF::assembly::ebpf::OPCODE::NEG_64) + .value("NOP", LIEF::assembly::ebpf::OPCODE::NOP) + .value("OR_ri", LIEF::assembly::ebpf::OPCODE::OR_ri) + .value("OR_ri_32", LIEF::assembly::ebpf::OPCODE::OR_ri_32) + .value("OR_rr", LIEF::assembly::ebpf::OPCODE::OR_rr) + .value("OR_rr_32", LIEF::assembly::ebpf::OPCODE::OR_rr_32) + .value("RET", LIEF::assembly::ebpf::OPCODE::RET) + .value("SDIV_ri", LIEF::assembly::ebpf::OPCODE::SDIV_ri) + .value("SDIV_ri_32", LIEF::assembly::ebpf::OPCODE::SDIV_ri_32) + .value("SDIV_rr", LIEF::assembly::ebpf::OPCODE::SDIV_rr) + .value("SDIV_rr_32", LIEF::assembly::ebpf::OPCODE::SDIV_rr_32) + .value("SLL_ri", LIEF::assembly::ebpf::OPCODE::SLL_ri) + .value("SLL_ri_32", LIEF::assembly::ebpf::OPCODE::SLL_ri_32) + .value("SLL_rr", LIEF::assembly::ebpf::OPCODE::SLL_rr) + .value("SLL_rr_32", LIEF::assembly::ebpf::OPCODE::SLL_rr_32) + .value("SMOD_ri", LIEF::assembly::ebpf::OPCODE::SMOD_ri) + .value("SMOD_ri_32", LIEF::assembly::ebpf::OPCODE::SMOD_ri_32) + .value("SMOD_rr", LIEF::assembly::ebpf::OPCODE::SMOD_rr) + .value("SMOD_rr_32", LIEF::assembly::ebpf::OPCODE::SMOD_rr_32) + .value("SRA_ri", LIEF::assembly::ebpf::OPCODE::SRA_ri) + .value("SRA_ri_32", LIEF::assembly::ebpf::OPCODE::SRA_ri_32) + .value("SRA_rr", LIEF::assembly::ebpf::OPCODE::SRA_rr) + .value("SRA_rr_32", LIEF::assembly::ebpf::OPCODE::SRA_rr_32) + .value("SRL_ri", LIEF::assembly::ebpf::OPCODE::SRL_ri) + .value("SRL_ri_32", LIEF::assembly::ebpf::OPCODE::SRL_ri_32) + .value("SRL_rr", LIEF::assembly::ebpf::OPCODE::SRL_rr) + .value("SRL_rr_32", LIEF::assembly::ebpf::OPCODE::SRL_rr_32) + .value("STB", LIEF::assembly::ebpf::OPCODE::STB) + .value("STB32", LIEF::assembly::ebpf::OPCODE::STB32) + .value("STBREL32", LIEF::assembly::ebpf::OPCODE::STBREL32) + .value("STB_imm", LIEF::assembly::ebpf::OPCODE::STB_imm) + .value("STD", LIEF::assembly::ebpf::OPCODE::STD) + .value("STDREL", LIEF::assembly::ebpf::OPCODE::STDREL) + .value("STD_imm", LIEF::assembly::ebpf::OPCODE::STD_imm) + .value("STH", LIEF::assembly::ebpf::OPCODE::STH) + .value("STH32", LIEF::assembly::ebpf::OPCODE::STH32) + .value("STHREL32", LIEF::assembly::ebpf::OPCODE::STHREL32) + .value("STH_imm", LIEF::assembly::ebpf::OPCODE::STH_imm) + .value("STW", LIEF::assembly::ebpf::OPCODE::STW) + .value("STW32", LIEF::assembly::ebpf::OPCODE::STW32) + .value("STWREL32", LIEF::assembly::ebpf::OPCODE::STWREL32) + .value("STW_imm", LIEF::assembly::ebpf::OPCODE::STW_imm) + .value("SUB_ri", LIEF::assembly::ebpf::OPCODE::SUB_ri) + .value("SUB_ri_32", LIEF::assembly::ebpf::OPCODE::SUB_ri_32) + .value("SUB_rr", LIEF::assembly::ebpf::OPCODE::SUB_rr) + .value("SUB_rr_32", LIEF::assembly::ebpf::OPCODE::SUB_rr_32) + .value("XADDD", LIEF::assembly::ebpf::OPCODE::XADDD) + .value("XADDW", LIEF::assembly::ebpf::OPCODE::XADDW) + .value("XADDW32", LIEF::assembly::ebpf::OPCODE::XADDW32) + .value("XANDD", LIEF::assembly::ebpf::OPCODE::XANDD) + .value("XANDW32", LIEF::assembly::ebpf::OPCODE::XANDW32) + .value("XCHGD", LIEF::assembly::ebpf::OPCODE::XCHGD) + .value("XCHGW32", LIEF::assembly::ebpf::OPCODE::XCHGW32) + .value("XFADDD", LIEF::assembly::ebpf::OPCODE::XFADDD) + .value("XFADDW32", LIEF::assembly::ebpf::OPCODE::XFADDW32) + .value("XFANDD", LIEF::assembly::ebpf::OPCODE::XFANDD) + .value("XFANDW32", LIEF::assembly::ebpf::OPCODE::XFANDW32) + .value("XFORD", LIEF::assembly::ebpf::OPCODE::XFORD) + .value("XFORW32", LIEF::assembly::ebpf::OPCODE::XFORW32) + .value("XFXORD", LIEF::assembly::ebpf::OPCODE::XFXORD) + .value("XFXORW32", LIEF::assembly::ebpf::OPCODE::XFXORW32) + .value("XORD", LIEF::assembly::ebpf::OPCODE::XORD) + .value("XORW32", LIEF::assembly::ebpf::OPCODE::XORW32) + .value("XOR_ri", LIEF::assembly::ebpf::OPCODE::XOR_ri) + .value("XOR_ri_32", LIEF::assembly::ebpf::OPCODE::XOR_ri_32) + .value("XOR_rr", LIEF::assembly::ebpf::OPCODE::XOR_rr) + .value("XOR_rr_32", LIEF::assembly::ebpf::OPCODE::XOR_rr_32) + .value("XXORD", LIEF::assembly::ebpf::OPCODE::XXORD) + .value("XXORW32", LIEF::assembly::ebpf::OPCODE::XXORW32) + .value("INSTRUCTION_LIST_END", LIEF::assembly::ebpf::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/pyOperand.cpp b/vendor/lief/api/python/src/asm/ebpf/pyOperand.cpp new file mode 100644 index 0000000..7b84bea --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/ebpf/Operand.hpp" + +#include "asm/ebpf/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::ebpf::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for an eBPF instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(ebpf::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/ebpf/pyRegister.cpp b/vendor/lief/api/python/src/asm/ebpf/pyRegister.cpp new file mode 100644 index 0000000..daa43ca --- /dev/null +++ b/vendor/lief/api/python/src/asm/ebpf/pyRegister.cpp @@ -0,0 +1,37 @@ +#include "asm/ebpf/init.hpp" + +#include "LIEF/asm/ebpf/registers.hpp" + +namespace LIEF::assembly::ebpf::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::ebpf::REG::NoRegister) + .value("R0", LIEF::assembly::ebpf::REG::R0) + .value("R1", LIEF::assembly::ebpf::REG::R1) + .value("R2", LIEF::assembly::ebpf::REG::R2) + .value("R3", LIEF::assembly::ebpf::REG::R3) + .value("R4", LIEF::assembly::ebpf::REG::R4) + .value("R5", LIEF::assembly::ebpf::REG::R5) + .value("R6", LIEF::assembly::ebpf::REG::R6) + .value("R7", LIEF::assembly::ebpf::REG::R7) + .value("R8", LIEF::assembly::ebpf::REG::R8) + .value("R9", LIEF::assembly::ebpf::REG::R9) + .value("R10", LIEF::assembly::ebpf::REG::R10) + .value("R11", LIEF::assembly::ebpf::REG::R11) + .value("W0", LIEF::assembly::ebpf::REG::W0) + .value("W1", LIEF::assembly::ebpf::REG::W1) + .value("W2", LIEF::assembly::ebpf::REG::W2) + .value("W3", LIEF::assembly::ebpf::REG::W3) + .value("W4", LIEF::assembly::ebpf::REG::W4) + .value("W5", LIEF::assembly::ebpf::REG::W5) + .value("W6", LIEF::assembly::ebpf::REG::W6) + .value("W7", LIEF::assembly::ebpf::REG::W7) + .value("W8", LIEF::assembly::ebpf::REG::W8) + .value("W9", LIEF::assembly::ebpf::REG::W9) + .value("W10", LIEF::assembly::ebpf::REG::W10) + .value("W11", LIEF::assembly::ebpf::REG::W11) + .value("NUM_TARGET_REGS", LIEF::assembly::ebpf::REG::NUM_TARGET_REGS) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/init.cpp b/vendor/lief/api/python/src/asm/init.cpp new file mode 100644 index 0000000..766069e --- /dev/null +++ b/vendor/lief/api/python/src/asm/init.cpp @@ -0,0 +1,34 @@ +#include "asm/init.hpp" +#include "asm/pyAssembly.hpp" + +#include "asm/aarch64/init.hpp" +#include "asm/x86/init.hpp" +#include "asm/riscv/init.hpp" +#include "asm/mips/init.hpp" +#include "asm/powerpc/init.hpp" +#include "asm/arm/init.hpp" +#include "asm/ebpf/init.hpp" + +namespace LIEF::assembly { +class Engine; +class Instruction; +class AssemblerConfig; +} + +namespace LIEF::assembly::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("assembly"); + + create(mod); + create(mod); + create(mod); + + aarch64::py::init(mod); + x86::py::init(mod); + arm::py::init(mod); + ebpf::py::init(mod); + powerpc::py::init(mod); + mips::py::init(mod); + riscv::py::init(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/init.hpp b/vendor/lief/api/python/src/asm/init.hpp new file mode 100644 index 0000000..960266a --- /dev/null +++ b/vendor/lief/api/python/src/asm/init.hpp @@ -0,0 +1,8 @@ +#ifndef PY_LIEF_ASM_INIT_H +#define PY_LIEF_ASM_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/asm/mips/CMakeLists.txt b/vendor/lief/api/python/src/asm/mips/CMakeLists.txt new file mode 100644 index 0000000..c5e4e70 --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyOperand.cpp + pyRegister.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/mips/init.cpp b/vendor/lief/api/python/src/asm/mips/init.cpp new file mode 100644 index 0000000..62945cd --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/init.cpp @@ -0,0 +1,18 @@ +#include "asm/mips/init.hpp" +namespace LIEF::assembly::mips { +enum class OPCODE; +enum class REG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::mips::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("mips"); + + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/mips/init.hpp b/vendor/lief/api/python/src/asm/mips/init.hpp new file mode 100644 index 0000000..78c9983 --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_MIPS_INIT_H +#define PY_LIEF_ASM_MIPS_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::mips::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/mips/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/mips/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/mips/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/mips/operands/pyImmediate.cpp new file mode 100644 index 0000000..5dbbd03 --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/operands/pyImmediate.cpp @@ -0,0 +1,29 @@ +#include "asm/mips/init.hpp" +#include "LIEF/asm/mips/operands/Immediate.hpp" + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + + For instance: + + .. code-block:: text + + addiu $4, $5, 8 + | + +---> Immediate(8) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/mips/operands/pyMemory.cpp new file mode 100644 index 0000000..1af1a8b --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/operands/pyMemory.cpp @@ -0,0 +1,78 @@ +#include + +#include "asm/mips/init.hpp" +#include "LIEF/asm/mips/operands/Memory.hpp" + +namespace nanobind::detail { +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::assembly::mips::operands::Memory::offset_t, + const_name("Optional[Union[lief.assembly.mips.REG, int]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::assembly::mips::operands::Memory::offset_t val, + rv_policy, cleanup_list *) noexcept + { + using namespace LIEF::assembly::mips; + using namespace LIEF::assembly::mips::operands; + switch (val.type) { + case Memory::offset_t::TYPE::REG: + return make_caster::from_cpp(val.reg, rv_policy::copy, + /*cleanup_list*/nullptr); + + case Memory::offset_t::TYPE::DISP: + return make_caster::from_cpp(val.displacement, rv_policy::copy, + /*cleanup_list*/nullptr); + case Memory::offset_t::TYPE::NONE: + return nb::none(); + } + return nb::none(); + } +}; +} + + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + .. code-block:: text + + lw $4, 8($5) ldxc1 $f2, $4($7) + | | | | | | + +------+ | +---+ +-------+ | +-----+ + | | | | | | + v v v v v v + Reg Disp Base Reg Index Base + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("base", "offset"); + + obj + .def_prop_ro("base", &operands::Memory::base, + R"doc( + The base register. + + For ``lw $4, 8($5)`` it would return ``$5``. + )doc"_doc + ) + .def_prop_ro("offset", &operands::Memory::offset, + R"doc( + The addressing offset. + + It can be either: + + - A register (e.g. ``ldxc1 $f2, $4($7)``) + - A displacement (e.g. ``lw $4, 8($5)``) + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/mips/operands/pyPCRelative.cpp new file mode 100644 index 0000000..ec7848b --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/operands/pyPCRelative.cpp @@ -0,0 +1,30 @@ +#include "asm/mips/init.hpp" +#include "LIEF/asm/mips/operands/PCRelative.hpp" + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a PC-relative operand. + + .. code-block:: text + + bal 0x100 + | + v + PC Relative operand + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &mips::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``pc`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/mips/operands/pyRegister.cpp new file mode 100644 index 0000000..b7c445d --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/operands/pyRegister.cpp @@ -0,0 +1,33 @@ +#include "asm/mips/init.hpp" +#include "LIEF/asm/mips/operands/Register.hpp" + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + For instance: + + .. code-block:: text + + move $4, $5 + | | + | +---------> Register($5) + | + +-------------> Register($4) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &mips::operands::Register::value, + R"doc( + The effective :class:`lief.assembly.mips.REG` wrapped by this operand + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/pyInstruction.cpp b/vendor/lief/api/python/src/asm/mips/pyInstruction.cpp new file mode 100644 index 0000000..37f104f --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/pyInstruction.cpp @@ -0,0 +1,34 @@ +#include "LIEF/asm/mips/Instruction.hpp" +#include "LIEF/asm/mips/Operand.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include "asm/mips/init.hpp" + +#include + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents a Mips instruction (including mips64, mips32))doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("operands", [] (const mips::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/pyOpcode.cpp b/vendor/lief/api/python/src/asm/mips/pyOpcode.cpp new file mode 100644 index 0000000..a51c9f5 --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/pyOpcode.cpp @@ -0,0 +1,2932 @@ +#include "asm/mips/init.hpp" + +#include "LIEF/asm/mips/opcodes.hpp" + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::mips::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::mips::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::mips::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::mips::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::mips::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::mips::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::mips::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::mips::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::mips::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::mips::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::mips::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::mips::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::mips::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::mips::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::mips::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::mips::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::mips::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::mips::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::mips::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::mips::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::mips::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::mips::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::mips::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::mips::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::mips::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::mips::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::mips::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::mips::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::mips::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::mips::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::mips::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::mips::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::mips::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::mips::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::mips::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::mips::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::mips::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::mips::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::mips::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::mips::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::mips::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::mips::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::mips::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::mips::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::mips::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::mips::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::mips::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::mips::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::mips::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::mips::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::mips::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::mips::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::mips::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::mips::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::mips::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::mips::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::mips::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::mips::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::mips::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::mips::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::mips::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::mips::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::mips::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::mips::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::mips::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::mips::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::mips::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::mips::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::mips::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::mips::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::mips::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::mips::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::mips::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::mips::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::mips::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::mips::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::mips::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::mips::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::mips::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::mips::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::mips::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::mips::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::mips::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::mips::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::mips::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::mips::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::mips::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::mips::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::mips::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::mips::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::mips::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::mips::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::mips::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::mips::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::mips::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::mips::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::mips::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::mips::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::mips::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::mips::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::mips::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::mips::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::mips::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::mips::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::mips::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::mips::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::mips::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::mips::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::mips::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::mips::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::mips::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::mips::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::mips::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::mips::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::mips::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::mips::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::mips::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::mips::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::mips::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::mips::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::mips::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::mips::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::mips::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::mips::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::mips::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::mips::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::mips::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::mips::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::mips::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::mips::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::mips::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::mips::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::mips::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::mips::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::mips::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::mips::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::mips::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::mips::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::mips::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::mips::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::mips::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::mips::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::mips::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::mips::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::mips::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::mips::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::mips::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::mips::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::mips::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::mips::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::mips::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::mips::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::mips::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::mips::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::mips::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::mips::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::mips::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::mips::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::mips::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::mips::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::mips::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::mips::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::mips::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::mips::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::mips::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::mips::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::mips::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::mips::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::mips::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::mips::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::mips::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::mips::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::mips::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::mips::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::mips::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::mips::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::mips::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::mips::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::mips::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::mips::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::mips::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::mips::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::mips::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::mips::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::mips::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::mips::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::mips::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::mips::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::mips::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::mips::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::mips::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::mips::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::mips::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::mips::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::mips::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::mips::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::mips::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::mips::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::mips::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::mips::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::mips::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::mips::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::mips::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::mips::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::mips::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::mips::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::mips::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::mips::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::mips::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::mips::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::mips::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::mips::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::mips::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::mips::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::mips::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::mips::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::mips::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::mips::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::mips::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::mips::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::mips::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::mips::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::mips::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::mips::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::mips::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::mips::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::mips::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::mips::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::mips::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::mips::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::mips::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::mips::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::mips::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::mips::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::mips::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::mips::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::mips::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::mips::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::mips::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::mips::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::mips::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::mips::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::mips::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::mips::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::mips::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::mips::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::mips::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::mips::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::mips::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::mips::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::mips::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::mips::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::mips::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::mips::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::mips::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::mips::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::mips::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::mips::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::mips::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::mips::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::mips::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::mips::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::mips::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::mips::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::mips::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::mips::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::mips::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::mips::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::mips::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::mips::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::mips::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::mips::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::mips::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::mips::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::mips::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::mips::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::mips::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::mips::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::mips::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::mips::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::mips::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::mips::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::mips::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::mips::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::mips::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::mips::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::mips::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::mips::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::mips::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::mips::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::mips::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::mips::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::mips::OPCODE::G_UBFX) + .value("ABSMacro", LIEF::assembly::mips::OPCODE::ABSMacro) + .value("ADJCALLSTACKDOWN", LIEF::assembly::mips::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::mips::OPCODE::ADJCALLSTACKUP) + .value("AND_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::AND_V_D_PSEUDO) + .value("AND_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::AND_V_H_PSEUDO) + .value("AND_V_W_PSEUDO", LIEF::assembly::mips::OPCODE::AND_V_W_PSEUDO) + .value("ATOMIC_CMP_SWAP_I16", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I16) + .value("ATOMIC_CMP_SWAP_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I16_POSTRA) + .value("ATOMIC_CMP_SWAP_I32", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I32) + .value("ATOMIC_CMP_SWAP_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I32_POSTRA) + .value("ATOMIC_CMP_SWAP_I64", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I64) + .value("ATOMIC_CMP_SWAP_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I64_POSTRA) + .value("ATOMIC_CMP_SWAP_I8", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I8) + .value("ATOMIC_CMP_SWAP_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_CMP_SWAP_I8_POSTRA) + .value("ATOMIC_LOAD_ADD_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I16) + .value("ATOMIC_LOAD_ADD_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I16_POSTRA) + .value("ATOMIC_LOAD_ADD_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I32) + .value("ATOMIC_LOAD_ADD_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I32_POSTRA) + .value("ATOMIC_LOAD_ADD_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I64) + .value("ATOMIC_LOAD_ADD_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I64_POSTRA) + .value("ATOMIC_LOAD_ADD_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I8) + .value("ATOMIC_LOAD_ADD_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_ADD_I8_POSTRA) + .value("ATOMIC_LOAD_AND_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I16) + .value("ATOMIC_LOAD_AND_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I16_POSTRA) + .value("ATOMIC_LOAD_AND_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I32) + .value("ATOMIC_LOAD_AND_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I32_POSTRA) + .value("ATOMIC_LOAD_AND_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I64) + .value("ATOMIC_LOAD_AND_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I64_POSTRA) + .value("ATOMIC_LOAD_AND_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I8) + .value("ATOMIC_LOAD_AND_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_AND_I8_POSTRA) + .value("ATOMIC_LOAD_MAX_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I16) + .value("ATOMIC_LOAD_MAX_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I16_POSTRA) + .value("ATOMIC_LOAD_MAX_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I32) + .value("ATOMIC_LOAD_MAX_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I32_POSTRA) + .value("ATOMIC_LOAD_MAX_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I64) + .value("ATOMIC_LOAD_MAX_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I64_POSTRA) + .value("ATOMIC_LOAD_MAX_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I8) + .value("ATOMIC_LOAD_MAX_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MAX_I8_POSTRA) + .value("ATOMIC_LOAD_MIN_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I16) + .value("ATOMIC_LOAD_MIN_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I16_POSTRA) + .value("ATOMIC_LOAD_MIN_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I32) + .value("ATOMIC_LOAD_MIN_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I32_POSTRA) + .value("ATOMIC_LOAD_MIN_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I64) + .value("ATOMIC_LOAD_MIN_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I64_POSTRA) + .value("ATOMIC_LOAD_MIN_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I8) + .value("ATOMIC_LOAD_MIN_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_MIN_I8_POSTRA) + .value("ATOMIC_LOAD_NAND_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I16) + .value("ATOMIC_LOAD_NAND_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I16_POSTRA) + .value("ATOMIC_LOAD_NAND_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I32) + .value("ATOMIC_LOAD_NAND_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I32_POSTRA) + .value("ATOMIC_LOAD_NAND_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I64) + .value("ATOMIC_LOAD_NAND_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I64_POSTRA) + .value("ATOMIC_LOAD_NAND_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I8) + .value("ATOMIC_LOAD_NAND_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_NAND_I8_POSTRA) + .value("ATOMIC_LOAD_OR_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I16) + .value("ATOMIC_LOAD_OR_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I16_POSTRA) + .value("ATOMIC_LOAD_OR_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I32) + .value("ATOMIC_LOAD_OR_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I32_POSTRA) + .value("ATOMIC_LOAD_OR_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I64) + .value("ATOMIC_LOAD_OR_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I64_POSTRA) + .value("ATOMIC_LOAD_OR_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I8) + .value("ATOMIC_LOAD_OR_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_OR_I8_POSTRA) + .value("ATOMIC_LOAD_SUB_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I16) + .value("ATOMIC_LOAD_SUB_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I16_POSTRA) + .value("ATOMIC_LOAD_SUB_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I32) + .value("ATOMIC_LOAD_SUB_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I32_POSTRA) + .value("ATOMIC_LOAD_SUB_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I64) + .value("ATOMIC_LOAD_SUB_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I64_POSTRA) + .value("ATOMIC_LOAD_SUB_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I8) + .value("ATOMIC_LOAD_SUB_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_SUB_I8_POSTRA) + .value("ATOMIC_LOAD_UMAX_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I16) + .value("ATOMIC_LOAD_UMAX_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I16_POSTRA) + .value("ATOMIC_LOAD_UMAX_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I32) + .value("ATOMIC_LOAD_UMAX_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I32_POSTRA) + .value("ATOMIC_LOAD_UMAX_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I64) + .value("ATOMIC_LOAD_UMAX_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I64_POSTRA) + .value("ATOMIC_LOAD_UMAX_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I8) + .value("ATOMIC_LOAD_UMAX_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMAX_I8_POSTRA) + .value("ATOMIC_LOAD_UMIN_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I16) + .value("ATOMIC_LOAD_UMIN_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I16_POSTRA) + .value("ATOMIC_LOAD_UMIN_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I32) + .value("ATOMIC_LOAD_UMIN_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I32_POSTRA) + .value("ATOMIC_LOAD_UMIN_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I64) + .value("ATOMIC_LOAD_UMIN_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I64_POSTRA) + .value("ATOMIC_LOAD_UMIN_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I8) + .value("ATOMIC_LOAD_UMIN_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_UMIN_I8_POSTRA) + .value("ATOMIC_LOAD_XOR_I16", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I16) + .value("ATOMIC_LOAD_XOR_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I16_POSTRA) + .value("ATOMIC_LOAD_XOR_I32", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I32) + .value("ATOMIC_LOAD_XOR_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I32_POSTRA) + .value("ATOMIC_LOAD_XOR_I64", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I64) + .value("ATOMIC_LOAD_XOR_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I64_POSTRA) + .value("ATOMIC_LOAD_XOR_I8", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I8) + .value("ATOMIC_LOAD_XOR_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_LOAD_XOR_I8_POSTRA) + .value("ATOMIC_SWAP_I16", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I16) + .value("ATOMIC_SWAP_I16_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I16_POSTRA) + .value("ATOMIC_SWAP_I32", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I32) + .value("ATOMIC_SWAP_I32_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I32_POSTRA) + .value("ATOMIC_SWAP_I64", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I64) + .value("ATOMIC_SWAP_I64_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I64_POSTRA) + .value("ATOMIC_SWAP_I8", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I8) + .value("ATOMIC_SWAP_I8_POSTRA", LIEF::assembly::mips::OPCODE::ATOMIC_SWAP_I8_POSTRA) + .value("B", LIEF::assembly::mips::OPCODE::B) + .value("BAL_BR", LIEF::assembly::mips::OPCODE::BAL_BR) + .value("BAL_BR_MM", LIEF::assembly::mips::OPCODE::BAL_BR_MM) + .value("BEQLImmMacro", LIEF::assembly::mips::OPCODE::BEQLImmMacro) + .value("BGE", LIEF::assembly::mips::OPCODE::BGE) + .value("BGEImmMacro", LIEF::assembly::mips::OPCODE::BGEImmMacro) + .value("BGEL", LIEF::assembly::mips::OPCODE::BGEL) + .value("BGELImmMacro", LIEF::assembly::mips::OPCODE::BGELImmMacro) + .value("BGEU", LIEF::assembly::mips::OPCODE::BGEU) + .value("BGEUImmMacro", LIEF::assembly::mips::OPCODE::BGEUImmMacro) + .value("BGEUL", LIEF::assembly::mips::OPCODE::BGEUL) + .value("BGEULImmMacro", LIEF::assembly::mips::OPCODE::BGEULImmMacro) + .value("BGT", LIEF::assembly::mips::OPCODE::BGT) + .value("BGTImmMacro", LIEF::assembly::mips::OPCODE::BGTImmMacro) + .value("BGTL", LIEF::assembly::mips::OPCODE::BGTL) + .value("BGTLImmMacro", LIEF::assembly::mips::OPCODE::BGTLImmMacro) + .value("BGTU", LIEF::assembly::mips::OPCODE::BGTU) + .value("BGTUImmMacro", LIEF::assembly::mips::OPCODE::BGTUImmMacro) + .value("BGTUL", LIEF::assembly::mips::OPCODE::BGTUL) + .value("BGTULImmMacro", LIEF::assembly::mips::OPCODE::BGTULImmMacro) + .value("BLE", LIEF::assembly::mips::OPCODE::BLE) + .value("BLEImmMacro", LIEF::assembly::mips::OPCODE::BLEImmMacro) + .value("BLEL", LIEF::assembly::mips::OPCODE::BLEL) + .value("BLELImmMacro", LIEF::assembly::mips::OPCODE::BLELImmMacro) + .value("BLEU", LIEF::assembly::mips::OPCODE::BLEU) + .value("BLEUImmMacro", LIEF::assembly::mips::OPCODE::BLEUImmMacro) + .value("BLEUL", LIEF::assembly::mips::OPCODE::BLEUL) + .value("BLEULImmMacro", LIEF::assembly::mips::OPCODE::BLEULImmMacro) + .value("BLT", LIEF::assembly::mips::OPCODE::BLT) + .value("BLTImmMacro", LIEF::assembly::mips::OPCODE::BLTImmMacro) + .value("BLTL", LIEF::assembly::mips::OPCODE::BLTL) + .value("BLTLImmMacro", LIEF::assembly::mips::OPCODE::BLTLImmMacro) + .value("BLTU", LIEF::assembly::mips::OPCODE::BLTU) + .value("BLTUImmMacro", LIEF::assembly::mips::OPCODE::BLTUImmMacro) + .value("BLTUL", LIEF::assembly::mips::OPCODE::BLTUL) + .value("BLTULImmMacro", LIEF::assembly::mips::OPCODE::BLTULImmMacro) + .value("BNELImmMacro", LIEF::assembly::mips::OPCODE::BNELImmMacro) + .value("BPOSGE32_PSEUDO", LIEF::assembly::mips::OPCODE::BPOSGE32_PSEUDO) + .value("BSEL_D_PSEUDO", LIEF::assembly::mips::OPCODE::BSEL_D_PSEUDO) + .value("BSEL_FD_PSEUDO", LIEF::assembly::mips::OPCODE::BSEL_FD_PSEUDO) + .value("BSEL_FW_PSEUDO", LIEF::assembly::mips::OPCODE::BSEL_FW_PSEUDO) + .value("BSEL_H_PSEUDO", LIEF::assembly::mips::OPCODE::BSEL_H_PSEUDO) + .value("BSEL_W_PSEUDO", LIEF::assembly::mips::OPCODE::BSEL_W_PSEUDO) + .value("B_MM", LIEF::assembly::mips::OPCODE::B_MM) + .value("B_MMR6_Pseudo", LIEF::assembly::mips::OPCODE::B_MMR6_Pseudo) + .value("B_MM_Pseudo", LIEF::assembly::mips::OPCODE::B_MM_Pseudo) + .value("BeqImm", LIEF::assembly::mips::OPCODE::BeqImm) + .value("BneImm", LIEF::assembly::mips::OPCODE::BneImm) + .value("BteqzT8CmpX16", LIEF::assembly::mips::OPCODE::BteqzT8CmpX16) + .value("BteqzT8CmpiX16", LIEF::assembly::mips::OPCODE::BteqzT8CmpiX16) + .value("BteqzT8SltX16", LIEF::assembly::mips::OPCODE::BteqzT8SltX16) + .value("BteqzT8SltiX16", LIEF::assembly::mips::OPCODE::BteqzT8SltiX16) + .value("BteqzT8SltiuX16", LIEF::assembly::mips::OPCODE::BteqzT8SltiuX16) + .value("BteqzT8SltuX16", LIEF::assembly::mips::OPCODE::BteqzT8SltuX16) + .value("BtnezT8CmpX16", LIEF::assembly::mips::OPCODE::BtnezT8CmpX16) + .value("BtnezT8CmpiX16", LIEF::assembly::mips::OPCODE::BtnezT8CmpiX16) + .value("BtnezT8SltX16", LIEF::assembly::mips::OPCODE::BtnezT8SltX16) + .value("BtnezT8SltiX16", LIEF::assembly::mips::OPCODE::BtnezT8SltiX16) + .value("BtnezT8SltiuX16", LIEF::assembly::mips::OPCODE::BtnezT8SltiuX16) + .value("BtnezT8SltuX16", LIEF::assembly::mips::OPCODE::BtnezT8SltuX16) + .value("BuildPairF64", LIEF::assembly::mips::OPCODE::BuildPairF64) + .value("BuildPairF64_64", LIEF::assembly::mips::OPCODE::BuildPairF64_64) + .value("CFTC1", LIEF::assembly::mips::OPCODE::CFTC1) + .value("CONSTPOOL_ENTRY", LIEF::assembly::mips::OPCODE::CONSTPOOL_ENTRY) + .value("COPY_FD_PSEUDO", LIEF::assembly::mips::OPCODE::COPY_FD_PSEUDO) + .value("COPY_FW_PSEUDO", LIEF::assembly::mips::OPCODE::COPY_FW_PSEUDO) + .value("CTTC1", LIEF::assembly::mips::OPCODE::CTTC1) + .value("Constant32", LIEF::assembly::mips::OPCODE::Constant32) + .value("DMULImmMacro", LIEF::assembly::mips::OPCODE::DMULImmMacro) + .value("DMULMacro", LIEF::assembly::mips::OPCODE::DMULMacro) + .value("DMULOMacro", LIEF::assembly::mips::OPCODE::DMULOMacro) + .value("DMULOUMacro", LIEF::assembly::mips::OPCODE::DMULOUMacro) + .value("DROL", LIEF::assembly::mips::OPCODE::DROL) + .value("DROLImm", LIEF::assembly::mips::OPCODE::DROLImm) + .value("DROR", LIEF::assembly::mips::OPCODE::DROR) + .value("DRORImm", LIEF::assembly::mips::OPCODE::DRORImm) + .value("DSDivIMacro", LIEF::assembly::mips::OPCODE::DSDivIMacro) + .value("DSDivMacro", LIEF::assembly::mips::OPCODE::DSDivMacro) + .value("DSRemIMacro", LIEF::assembly::mips::OPCODE::DSRemIMacro) + .value("DSRemMacro", LIEF::assembly::mips::OPCODE::DSRemMacro) + .value("DUDivIMacro", LIEF::assembly::mips::OPCODE::DUDivIMacro) + .value("DUDivMacro", LIEF::assembly::mips::OPCODE::DUDivMacro) + .value("DURemIMacro", LIEF::assembly::mips::OPCODE::DURemIMacro) + .value("DURemMacro", LIEF::assembly::mips::OPCODE::DURemMacro) + .value("ERet", LIEF::assembly::mips::OPCODE::ERet) + .value("ExtractElementF64", LIEF::assembly::mips::OPCODE::ExtractElementF64) + .value("ExtractElementF64_64", LIEF::assembly::mips::OPCODE::ExtractElementF64_64) + .value("FABS_D", LIEF::assembly::mips::OPCODE::FABS_D) + .value("FABS_W", LIEF::assembly::mips::OPCODE::FABS_W) + .value("FEXP2_D_1_PSEUDO", LIEF::assembly::mips::OPCODE::FEXP2_D_1_PSEUDO) + .value("FEXP2_W_1_PSEUDO", LIEF::assembly::mips::OPCODE::FEXP2_W_1_PSEUDO) + .value("FILL_FD_PSEUDO", LIEF::assembly::mips::OPCODE::FILL_FD_PSEUDO) + .value("FILL_FW_PSEUDO", LIEF::assembly::mips::OPCODE::FILL_FW_PSEUDO) + .value("GotPrologue16", LIEF::assembly::mips::OPCODE::GotPrologue16) + .value("INSERT_B_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_B_VIDX64_PSEUDO) + .value("INSERT_B_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_B_VIDX_PSEUDO) + .value("INSERT_D_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_D_VIDX64_PSEUDO) + .value("INSERT_D_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_D_VIDX_PSEUDO) + .value("INSERT_FD_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FD_PSEUDO) + .value("INSERT_FD_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FD_VIDX64_PSEUDO) + .value("INSERT_FD_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FD_VIDX_PSEUDO) + .value("INSERT_FW_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FW_PSEUDO) + .value("INSERT_FW_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FW_VIDX64_PSEUDO) + .value("INSERT_FW_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_FW_VIDX_PSEUDO) + .value("INSERT_H_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_H_VIDX64_PSEUDO) + .value("INSERT_H_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_H_VIDX_PSEUDO) + .value("INSERT_W_VIDX64_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_W_VIDX64_PSEUDO) + .value("INSERT_W_VIDX_PSEUDO", LIEF::assembly::mips::OPCODE::INSERT_W_VIDX_PSEUDO) + .value("JALR64Pseudo", LIEF::assembly::mips::OPCODE::JALR64Pseudo) + .value("JALRHB64Pseudo", LIEF::assembly::mips::OPCODE::JALRHB64Pseudo) + .value("JALRHBPseudo", LIEF::assembly::mips::OPCODE::JALRHBPseudo) + .value("JALRPseudo", LIEF::assembly::mips::OPCODE::JALRPseudo) + .value("JAL_MMR6", LIEF::assembly::mips::OPCODE::JAL_MMR6) + .value("JalOneReg", LIEF::assembly::mips::OPCODE::JalOneReg) + .value("JalTwoReg", LIEF::assembly::mips::OPCODE::JalTwoReg) + .value("LDMacro", LIEF::assembly::mips::OPCODE::LDMacro) + .value("LDR_D", LIEF::assembly::mips::OPCODE::LDR_D) + .value("LDR_W", LIEF::assembly::mips::OPCODE::LDR_W) + .value("LD_F16", LIEF::assembly::mips::OPCODE::LD_F16) + .value("LOAD_ACC128", LIEF::assembly::mips::OPCODE::LOAD_ACC128) + .value("LOAD_ACC64", LIEF::assembly::mips::OPCODE::LOAD_ACC64) + .value("LOAD_ACC64DSP", LIEF::assembly::mips::OPCODE::LOAD_ACC64DSP) + .value("LOAD_CCOND_DSP", LIEF::assembly::mips::OPCODE::LOAD_CCOND_DSP) + .value("LONG_BRANCH_ADDiu", LIEF::assembly::mips::OPCODE::LONG_BRANCH_ADDiu) + .value("LONG_BRANCH_ADDiu2Op", LIEF::assembly::mips::OPCODE::LONG_BRANCH_ADDiu2Op) + .value("LONG_BRANCH_DADDiu", LIEF::assembly::mips::OPCODE::LONG_BRANCH_DADDiu) + .value("LONG_BRANCH_DADDiu2Op", LIEF::assembly::mips::OPCODE::LONG_BRANCH_DADDiu2Op) + .value("LONG_BRANCH_LUi", LIEF::assembly::mips::OPCODE::LONG_BRANCH_LUi) + .value("LONG_BRANCH_LUi2Op", LIEF::assembly::mips::OPCODE::LONG_BRANCH_LUi2Op) + .value("LONG_BRANCH_LUi2Op_64", LIEF::assembly::mips::OPCODE::LONG_BRANCH_LUi2Op_64) + .value("LWM_MM", LIEF::assembly::mips::OPCODE::LWM_MM) + .value("LoadAddrImm32", LIEF::assembly::mips::OPCODE::LoadAddrImm32) + .value("LoadAddrImm64", LIEF::assembly::mips::OPCODE::LoadAddrImm64) + .value("LoadAddrReg32", LIEF::assembly::mips::OPCODE::LoadAddrReg32) + .value("LoadAddrReg64", LIEF::assembly::mips::OPCODE::LoadAddrReg64) + .value("LoadImm32", LIEF::assembly::mips::OPCODE::LoadImm32) + .value("LoadImm64", LIEF::assembly::mips::OPCODE::LoadImm64) + .value("LoadImmDoubleFGR", LIEF::assembly::mips::OPCODE::LoadImmDoubleFGR) + .value("LoadImmDoubleFGR_32", LIEF::assembly::mips::OPCODE::LoadImmDoubleFGR_32) + .value("LoadImmDoubleGPR", LIEF::assembly::mips::OPCODE::LoadImmDoubleGPR) + .value("LoadImmSingleFGR", LIEF::assembly::mips::OPCODE::LoadImmSingleFGR) + .value("LoadImmSingleGPR", LIEF::assembly::mips::OPCODE::LoadImmSingleGPR) + .value("LwConstant32", LIEF::assembly::mips::OPCODE::LwConstant32) + .value("MFTACX", LIEF::assembly::mips::OPCODE::MFTACX) + .value("MFTC0", LIEF::assembly::mips::OPCODE::MFTC0) + .value("MFTC1", LIEF::assembly::mips::OPCODE::MFTC1) + .value("MFTDSP", LIEF::assembly::mips::OPCODE::MFTDSP) + .value("MFTGPR", LIEF::assembly::mips::OPCODE::MFTGPR) + .value("MFTHC1", LIEF::assembly::mips::OPCODE::MFTHC1) + .value("MFTHI", LIEF::assembly::mips::OPCODE::MFTHI) + .value("MFTLO", LIEF::assembly::mips::OPCODE::MFTLO) + .value("MIPSeh_return32", LIEF::assembly::mips::OPCODE::MIPSeh_return32) + .value("MIPSeh_return64", LIEF::assembly::mips::OPCODE::MIPSeh_return64) + .value("MSA_FP_EXTEND_D_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_EXTEND_D_PSEUDO) + .value("MSA_FP_EXTEND_W_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_EXTEND_W_PSEUDO) + .value("MSA_FP_ROUND_D_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_ROUND_D_PSEUDO) + .value("MSA_FP_ROUND_W_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_ROUND_W_PSEUDO) + .value("MTTACX", LIEF::assembly::mips::OPCODE::MTTACX) + .value("MTTC0", LIEF::assembly::mips::OPCODE::MTTC0) + .value("MTTC1", LIEF::assembly::mips::OPCODE::MTTC1) + .value("MTTDSP", LIEF::assembly::mips::OPCODE::MTTDSP) + .value("MTTGPR", LIEF::assembly::mips::OPCODE::MTTGPR) + .value("MTTHC1", LIEF::assembly::mips::OPCODE::MTTHC1) + .value("MTTHI", LIEF::assembly::mips::OPCODE::MTTHI) + .value("MTTLO", LIEF::assembly::mips::OPCODE::MTTLO) + .value("MULImmMacro", LIEF::assembly::mips::OPCODE::MULImmMacro) + .value("MULOMacro", LIEF::assembly::mips::OPCODE::MULOMacro) + .value("MULOUMacro", LIEF::assembly::mips::OPCODE::MULOUMacro) + .value("MultRxRy16", LIEF::assembly::mips::OPCODE::MultRxRy16) + .value("MultRxRyRz16", LIEF::assembly::mips::OPCODE::MultRxRyRz16) + .value("MultuRxRy16", LIEF::assembly::mips::OPCODE::MultuRxRy16) + .value("MultuRxRyRz16", LIEF::assembly::mips::OPCODE::MultuRxRyRz16) + .value("NOP", LIEF::assembly::mips::OPCODE::NOP) + .value("NORImm", LIEF::assembly::mips::OPCODE::NORImm) + .value("NORImm64", LIEF::assembly::mips::OPCODE::NORImm64) + .value("NOR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_D_PSEUDO); + opcodes.value("NOR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_H_PSEUDO) + .value("NOR_V_W_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_W_PSEUDO) + .value("OR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::OR_V_D_PSEUDO) + .value("OR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::OR_V_H_PSEUDO) + .value("OR_V_W_PSEUDO", LIEF::assembly::mips::OPCODE::OR_V_W_PSEUDO) + .value("PseudoCMPU_EQ_QB", LIEF::assembly::mips::OPCODE::PseudoCMPU_EQ_QB) + .value("PseudoCMPU_LE_QB", LIEF::assembly::mips::OPCODE::PseudoCMPU_LE_QB) + .value("PseudoCMPU_LT_QB", LIEF::assembly::mips::OPCODE::PseudoCMPU_LT_QB) + .value("PseudoCMP_EQ_PH", LIEF::assembly::mips::OPCODE::PseudoCMP_EQ_PH) + .value("PseudoCMP_LE_PH", LIEF::assembly::mips::OPCODE::PseudoCMP_LE_PH) + .value("PseudoCMP_LT_PH", LIEF::assembly::mips::OPCODE::PseudoCMP_LT_PH) + .value("PseudoCVT_D32_W", LIEF::assembly::mips::OPCODE::PseudoCVT_D32_W) + .value("PseudoCVT_D64_L", LIEF::assembly::mips::OPCODE::PseudoCVT_D64_L) + .value("PseudoCVT_D64_W", LIEF::assembly::mips::OPCODE::PseudoCVT_D64_W) + .value("PseudoCVT_S_L", LIEF::assembly::mips::OPCODE::PseudoCVT_S_L) + .value("PseudoCVT_S_W", LIEF::assembly::mips::OPCODE::PseudoCVT_S_W) + .value("PseudoDMULT", LIEF::assembly::mips::OPCODE::PseudoDMULT) + .value("PseudoDMULTu", LIEF::assembly::mips::OPCODE::PseudoDMULTu) + .value("PseudoDSDIV", LIEF::assembly::mips::OPCODE::PseudoDSDIV) + .value("PseudoDUDIV", LIEF::assembly::mips::OPCODE::PseudoDUDIV) + .value("PseudoD_SELECT_I", LIEF::assembly::mips::OPCODE::PseudoD_SELECT_I) + .value("PseudoD_SELECT_I64", LIEF::assembly::mips::OPCODE::PseudoD_SELECT_I64) + .value("PseudoIndirectBranch", LIEF::assembly::mips::OPCODE::PseudoIndirectBranch) + .value("PseudoIndirectBranch64", LIEF::assembly::mips::OPCODE::PseudoIndirectBranch64) + .value("PseudoIndirectBranch64R6", LIEF::assembly::mips::OPCODE::PseudoIndirectBranch64R6) + .value("PseudoIndirectBranchR6", LIEF::assembly::mips::OPCODE::PseudoIndirectBranchR6) + .value("PseudoIndirectBranch_MM", LIEF::assembly::mips::OPCODE::PseudoIndirectBranch_MM) + .value("PseudoIndirectBranch_MMR6", LIEF::assembly::mips::OPCODE::PseudoIndirectBranch_MMR6) + .value("PseudoIndirectHazardBranch", LIEF::assembly::mips::OPCODE::PseudoIndirectHazardBranch) + .value("PseudoIndirectHazardBranch64", LIEF::assembly::mips::OPCODE::PseudoIndirectHazardBranch64) + .value("PseudoIndrectHazardBranch64R6", LIEF::assembly::mips::OPCODE::PseudoIndrectHazardBranch64R6) + .value("PseudoIndrectHazardBranchR6", LIEF::assembly::mips::OPCODE::PseudoIndrectHazardBranchR6) + .value("PseudoMADD", LIEF::assembly::mips::OPCODE::PseudoMADD) + .value("PseudoMADDU", LIEF::assembly::mips::OPCODE::PseudoMADDU) + .value("PseudoMADDU_MM", LIEF::assembly::mips::OPCODE::PseudoMADDU_MM) + .value("PseudoMADD_MM", LIEF::assembly::mips::OPCODE::PseudoMADD_MM) + .value("PseudoMFHI", LIEF::assembly::mips::OPCODE::PseudoMFHI) + .value("PseudoMFHI64", LIEF::assembly::mips::OPCODE::PseudoMFHI64) + .value("PseudoMFHI_MM", LIEF::assembly::mips::OPCODE::PseudoMFHI_MM) + .value("PseudoMFLO", LIEF::assembly::mips::OPCODE::PseudoMFLO) + .value("PseudoMFLO64", LIEF::assembly::mips::OPCODE::PseudoMFLO64) + .value("PseudoMFLO_MM", LIEF::assembly::mips::OPCODE::PseudoMFLO_MM) + .value("PseudoMSUB", LIEF::assembly::mips::OPCODE::PseudoMSUB) + .value("PseudoMSUBU", LIEF::assembly::mips::OPCODE::PseudoMSUBU) + .value("PseudoMSUBU_MM", LIEF::assembly::mips::OPCODE::PseudoMSUBU_MM) + .value("PseudoMSUB_MM", LIEF::assembly::mips::OPCODE::PseudoMSUB_MM) + .value("PseudoMTLOHI", LIEF::assembly::mips::OPCODE::PseudoMTLOHI) + .value("PseudoMTLOHI64", LIEF::assembly::mips::OPCODE::PseudoMTLOHI64) + .value("PseudoMTLOHI_DSP", LIEF::assembly::mips::OPCODE::PseudoMTLOHI_DSP) + .value("PseudoMTLOHI_MM", LIEF::assembly::mips::OPCODE::PseudoMTLOHI_MM) + .value("PseudoMULT", LIEF::assembly::mips::OPCODE::PseudoMULT) + .value("PseudoMULT_MM", LIEF::assembly::mips::OPCODE::PseudoMULT_MM) + .value("PseudoMULTu", LIEF::assembly::mips::OPCODE::PseudoMULTu) + .value("PseudoMULTu_MM", LIEF::assembly::mips::OPCODE::PseudoMULTu_MM) + .value("PseudoPICK_PH", LIEF::assembly::mips::OPCODE::PseudoPICK_PH) + .value("PseudoPICK_QB", LIEF::assembly::mips::OPCODE::PseudoPICK_QB) + .value("PseudoReturn", LIEF::assembly::mips::OPCODE::PseudoReturn) + .value("PseudoReturn64", LIEF::assembly::mips::OPCODE::PseudoReturn64) + .value("PseudoSDIV", LIEF::assembly::mips::OPCODE::PseudoSDIV) + .value("PseudoSELECTFP_F_D32", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_F_D32) + .value("PseudoSELECTFP_F_D64", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_F_D64) + .value("PseudoSELECTFP_F_I", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_F_I) + .value("PseudoSELECTFP_F_I64", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_F_I64) + .value("PseudoSELECTFP_F_S", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_F_S) + .value("PseudoSELECTFP_T_D32", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_T_D32) + .value("PseudoSELECTFP_T_D64", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_T_D64) + .value("PseudoSELECTFP_T_I", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_T_I) + .value("PseudoSELECTFP_T_I64", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_T_I64) + .value("PseudoSELECTFP_T_S", LIEF::assembly::mips::OPCODE::PseudoSELECTFP_T_S) + .value("PseudoSELECT_D32", LIEF::assembly::mips::OPCODE::PseudoSELECT_D32) + .value("PseudoSELECT_D64", LIEF::assembly::mips::OPCODE::PseudoSELECT_D64) + .value("PseudoSELECT_I", LIEF::assembly::mips::OPCODE::PseudoSELECT_I) + .value("PseudoSELECT_I64", LIEF::assembly::mips::OPCODE::PseudoSELECT_I64) + .value("PseudoSELECT_S", LIEF::assembly::mips::OPCODE::PseudoSELECT_S) + .value("PseudoTRUNC_W_D", LIEF::assembly::mips::OPCODE::PseudoTRUNC_W_D) + .value("PseudoTRUNC_W_D32", LIEF::assembly::mips::OPCODE::PseudoTRUNC_W_D32) + .value("PseudoTRUNC_W_S", LIEF::assembly::mips::OPCODE::PseudoTRUNC_W_S) + .value("PseudoUDIV", LIEF::assembly::mips::OPCODE::PseudoUDIV) + .value("ROL", LIEF::assembly::mips::OPCODE::ROL) + .value("ROLImm", LIEF::assembly::mips::OPCODE::ROLImm) + .value("ROR", LIEF::assembly::mips::OPCODE::ROR) + .value("RORImm", LIEF::assembly::mips::OPCODE::RORImm) + .value("RetRA", LIEF::assembly::mips::OPCODE::RetRA) + .value("RetRA16", LIEF::assembly::mips::OPCODE::RetRA16) + .value("SDC1_M1", LIEF::assembly::mips::OPCODE::SDC1_M1) + .value("SDIV_MM_Pseudo", LIEF::assembly::mips::OPCODE::SDIV_MM_Pseudo) + .value("SDMacro", LIEF::assembly::mips::OPCODE::SDMacro) + .value("SDivIMacro", LIEF::assembly::mips::OPCODE::SDivIMacro) + .value("SDivMacro", LIEF::assembly::mips::OPCODE::SDivMacro) + .value("SEQIMacro", LIEF::assembly::mips::OPCODE::SEQIMacro) + .value("SEQMacro", LIEF::assembly::mips::OPCODE::SEQMacro) + .value("SGE", LIEF::assembly::mips::OPCODE::SGE) + .value("SGEImm", LIEF::assembly::mips::OPCODE::SGEImm) + .value("SGEImm64", LIEF::assembly::mips::OPCODE::SGEImm64) + .value("SGEU", LIEF::assembly::mips::OPCODE::SGEU) + .value("SGEUImm", LIEF::assembly::mips::OPCODE::SGEUImm) + .value("SGEUImm64", LIEF::assembly::mips::OPCODE::SGEUImm64) + .value("SGTImm", LIEF::assembly::mips::OPCODE::SGTImm) + .value("SGTImm64", LIEF::assembly::mips::OPCODE::SGTImm64) + .value("SGTUImm", LIEF::assembly::mips::OPCODE::SGTUImm) + .value("SGTUImm64", LIEF::assembly::mips::OPCODE::SGTUImm64) + .value("SLE", LIEF::assembly::mips::OPCODE::SLE) + .value("SLEImm", LIEF::assembly::mips::OPCODE::SLEImm) + .value("SLEImm64", LIEF::assembly::mips::OPCODE::SLEImm64) + .value("SLEU", LIEF::assembly::mips::OPCODE::SLEU) + .value("SLEUImm", LIEF::assembly::mips::OPCODE::SLEUImm) + .value("SLEUImm64", LIEF::assembly::mips::OPCODE::SLEUImm64) + .value("SLTImm64", LIEF::assembly::mips::OPCODE::SLTImm64) + .value("SLTUImm64", LIEF::assembly::mips::OPCODE::SLTUImm64) + .value("SNEIMacro", LIEF::assembly::mips::OPCODE::SNEIMacro) + .value("SNEMacro", LIEF::assembly::mips::OPCODE::SNEMacro) + .value("SNZ_B_PSEUDO", LIEF::assembly::mips::OPCODE::SNZ_B_PSEUDO) + .value("SNZ_D_PSEUDO", LIEF::assembly::mips::OPCODE::SNZ_D_PSEUDO) + .value("SNZ_H_PSEUDO", LIEF::assembly::mips::OPCODE::SNZ_H_PSEUDO) + .value("SNZ_V_PSEUDO", LIEF::assembly::mips::OPCODE::SNZ_V_PSEUDO) + .value("SNZ_W_PSEUDO", LIEF::assembly::mips::OPCODE::SNZ_W_PSEUDO) + .value("SRemIMacro", LIEF::assembly::mips::OPCODE::SRemIMacro) + .value("SRemMacro", LIEF::assembly::mips::OPCODE::SRemMacro) + .value("STORE_ACC128", LIEF::assembly::mips::OPCODE::STORE_ACC128) + .value("STORE_ACC64", LIEF::assembly::mips::OPCODE::STORE_ACC64) + .value("STORE_ACC64DSP", LIEF::assembly::mips::OPCODE::STORE_ACC64DSP) + .value("STORE_CCOND_DSP", LIEF::assembly::mips::OPCODE::STORE_CCOND_DSP) + .value("STR_D", LIEF::assembly::mips::OPCODE::STR_D) + .value("STR_W", LIEF::assembly::mips::OPCODE::STR_W) + .value("ST_F16", LIEF::assembly::mips::OPCODE::ST_F16) + .value("SWM_MM", LIEF::assembly::mips::OPCODE::SWM_MM) + .value("SZ_B_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_B_PSEUDO) + .value("SZ_D_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_D_PSEUDO) + .value("SZ_H_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_H_PSEUDO) + .value("SZ_V_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_V_PSEUDO) + .value("SZ_W_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_W_PSEUDO) + .value("SaaAddr", LIEF::assembly::mips::OPCODE::SaaAddr) + .value("SaadAddr", LIEF::assembly::mips::OPCODE::SaadAddr) + .value("SelBeqZ", LIEF::assembly::mips::OPCODE::SelBeqZ) + .value("SelBneZ", LIEF::assembly::mips::OPCODE::SelBneZ) + .value("SelTBteqZCmp", LIEF::assembly::mips::OPCODE::SelTBteqZCmp) + .value("SelTBteqZCmpi", LIEF::assembly::mips::OPCODE::SelTBteqZCmpi) + .value("SelTBteqZSlt", LIEF::assembly::mips::OPCODE::SelTBteqZSlt) + .value("SelTBteqZSlti", LIEF::assembly::mips::OPCODE::SelTBteqZSlti) + .value("SelTBteqZSltiu", LIEF::assembly::mips::OPCODE::SelTBteqZSltiu) + .value("SelTBteqZSltu", LIEF::assembly::mips::OPCODE::SelTBteqZSltu) + .value("SelTBtneZCmp", LIEF::assembly::mips::OPCODE::SelTBtneZCmp) + .value("SelTBtneZCmpi", LIEF::assembly::mips::OPCODE::SelTBtneZCmpi) + .value("SelTBtneZSlt", LIEF::assembly::mips::OPCODE::SelTBtneZSlt) + .value("SelTBtneZSlti", LIEF::assembly::mips::OPCODE::SelTBtneZSlti) + .value("SelTBtneZSltiu", LIEF::assembly::mips::OPCODE::SelTBtneZSltiu) + .value("SelTBtneZSltu", LIEF::assembly::mips::OPCODE::SelTBtneZSltu) + .value("SltCCRxRy16", LIEF::assembly::mips::OPCODE::SltCCRxRy16) + .value("SltiCCRxImmX16", LIEF::assembly::mips::OPCODE::SltiCCRxImmX16) + .value("SltiuCCRxImmX16", LIEF::assembly::mips::OPCODE::SltiuCCRxImmX16) + .value("SltuCCRxRy16", LIEF::assembly::mips::OPCODE::SltuCCRxRy16) + .value("SltuRxRyRz16", LIEF::assembly::mips::OPCODE::SltuRxRyRz16) + .value("TAILCALL", LIEF::assembly::mips::OPCODE::TAILCALL) + .value("TAILCALL64R6REG", LIEF::assembly::mips::OPCODE::TAILCALL64R6REG) + .value("TAILCALLHB64R6REG", LIEF::assembly::mips::OPCODE::TAILCALLHB64R6REG) + .value("TAILCALLHBR6REG", LIEF::assembly::mips::OPCODE::TAILCALLHBR6REG) + .value("TAILCALLR6REG", LIEF::assembly::mips::OPCODE::TAILCALLR6REG) + .value("TAILCALLREG", LIEF::assembly::mips::OPCODE::TAILCALLREG) + .value("TAILCALLREG64", LIEF::assembly::mips::OPCODE::TAILCALLREG64) + .value("TAILCALLREGHB", LIEF::assembly::mips::OPCODE::TAILCALLREGHB) + .value("TAILCALLREGHB64", LIEF::assembly::mips::OPCODE::TAILCALLREGHB64) + .value("TAILCALLREG_MM", LIEF::assembly::mips::OPCODE::TAILCALLREG_MM) + .value("TAILCALLREG_MMR6", LIEF::assembly::mips::OPCODE::TAILCALLREG_MMR6) + .value("TAILCALL_MM", LIEF::assembly::mips::OPCODE::TAILCALL_MM) + .value("TAILCALL_MMR6", LIEF::assembly::mips::OPCODE::TAILCALL_MMR6) + .value("TRAP", LIEF::assembly::mips::OPCODE::TRAP) + .value("TRAP_MM", LIEF::assembly::mips::OPCODE::TRAP_MM) + .value("UDIV_MM_Pseudo", LIEF::assembly::mips::OPCODE::UDIV_MM_Pseudo) + .value("UDivIMacro", LIEF::assembly::mips::OPCODE::UDivIMacro) + .value("UDivMacro", LIEF::assembly::mips::OPCODE::UDivMacro) + .value("URemIMacro", LIEF::assembly::mips::OPCODE::URemIMacro) + .value("URemMacro", LIEF::assembly::mips::OPCODE::URemMacro) + .value("Ulh", LIEF::assembly::mips::OPCODE::Ulh) + .value("Ulhu", LIEF::assembly::mips::OPCODE::Ulhu) + .value("Ulw", LIEF::assembly::mips::OPCODE::Ulw) + .value("Ush", LIEF::assembly::mips::OPCODE::Ush) + .value("Usw", LIEF::assembly::mips::OPCODE::Usw) + .value("XOR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::XOR_V_D_PSEUDO) + .value("XOR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::XOR_V_H_PSEUDO) + .value("XOR_V_W_PSEUDO", LIEF::assembly::mips::OPCODE::XOR_V_W_PSEUDO) + .value("ABSQ_S_PH", LIEF::assembly::mips::OPCODE::ABSQ_S_PH) + .value("ABSQ_S_PH_MM", LIEF::assembly::mips::OPCODE::ABSQ_S_PH_MM) + .value("ABSQ_S_QB", LIEF::assembly::mips::OPCODE::ABSQ_S_QB) + .value("ABSQ_S_QB_MMR2", LIEF::assembly::mips::OPCODE::ABSQ_S_QB_MMR2) + .value("ABSQ_S_W", LIEF::assembly::mips::OPCODE::ABSQ_S_W) + .value("ABSQ_S_W_MM", LIEF::assembly::mips::OPCODE::ABSQ_S_W_MM) + .value("ADD", LIEF::assembly::mips::OPCODE::ADD) + .value("ADDIUPC", LIEF::assembly::mips::OPCODE::ADDIUPC) + .value("ADDIUPC_MM", LIEF::assembly::mips::OPCODE::ADDIUPC_MM) + .value("ADDIUPC_MMR6", LIEF::assembly::mips::OPCODE::ADDIUPC_MMR6) + .value("ADDIUR1SP_MM", LIEF::assembly::mips::OPCODE::ADDIUR1SP_MM) + .value("ADDIUR2_MM", LIEF::assembly::mips::OPCODE::ADDIUR2_MM) + .value("ADDIUS5_MM", LIEF::assembly::mips::OPCODE::ADDIUS5_MM) + .value("ADDIUSP_MM", LIEF::assembly::mips::OPCODE::ADDIUSP_MM) + .value("ADDIU_MMR6", LIEF::assembly::mips::OPCODE::ADDIU_MMR6) + .value("ADDQH_PH", LIEF::assembly::mips::OPCODE::ADDQH_PH) + .value("ADDQH_PH_MMR2", LIEF::assembly::mips::OPCODE::ADDQH_PH_MMR2) + .value("ADDQH_R_PH", LIEF::assembly::mips::OPCODE::ADDQH_R_PH) + .value("ADDQH_R_PH_MMR2", LIEF::assembly::mips::OPCODE::ADDQH_R_PH_MMR2) + .value("ADDQH_R_W", LIEF::assembly::mips::OPCODE::ADDQH_R_W) + .value("ADDQH_R_W_MMR2", LIEF::assembly::mips::OPCODE::ADDQH_R_W_MMR2) + .value("ADDQH_W", LIEF::assembly::mips::OPCODE::ADDQH_W) + .value("ADDQH_W_MMR2", LIEF::assembly::mips::OPCODE::ADDQH_W_MMR2) + .value("ADDQ_PH", LIEF::assembly::mips::OPCODE::ADDQ_PH) + .value("ADDQ_PH_MM", LIEF::assembly::mips::OPCODE::ADDQ_PH_MM) + .value("ADDQ_S_PH", LIEF::assembly::mips::OPCODE::ADDQ_S_PH) + .value("ADDQ_S_PH_MM", LIEF::assembly::mips::OPCODE::ADDQ_S_PH_MM) + .value("ADDQ_S_W", LIEF::assembly::mips::OPCODE::ADDQ_S_W) + .value("ADDQ_S_W_MM", LIEF::assembly::mips::OPCODE::ADDQ_S_W_MM) + .value("ADDR_PS64", LIEF::assembly::mips::OPCODE::ADDR_PS64) + .value("ADDSC", LIEF::assembly::mips::OPCODE::ADDSC) + .value("ADDSC_MM", LIEF::assembly::mips::OPCODE::ADDSC_MM) + .value("ADDS_A_B", LIEF::assembly::mips::OPCODE::ADDS_A_B) + .value("ADDS_A_D", LIEF::assembly::mips::OPCODE::ADDS_A_D) + .value("ADDS_A_H", LIEF::assembly::mips::OPCODE::ADDS_A_H) + .value("ADDS_A_W", LIEF::assembly::mips::OPCODE::ADDS_A_W) + .value("ADDS_S_B", LIEF::assembly::mips::OPCODE::ADDS_S_B) + .value("ADDS_S_D", LIEF::assembly::mips::OPCODE::ADDS_S_D) + .value("ADDS_S_H", LIEF::assembly::mips::OPCODE::ADDS_S_H) + .value("ADDS_S_W", LIEF::assembly::mips::OPCODE::ADDS_S_W) + .value("ADDS_U_B", LIEF::assembly::mips::OPCODE::ADDS_U_B) + .value("ADDS_U_D", LIEF::assembly::mips::OPCODE::ADDS_U_D) + .value("ADDS_U_H", LIEF::assembly::mips::OPCODE::ADDS_U_H) + .value("ADDS_U_W", LIEF::assembly::mips::OPCODE::ADDS_U_W) + .value("ADDU16_MM", LIEF::assembly::mips::OPCODE::ADDU16_MM) + .value("ADDU16_MMR6", LIEF::assembly::mips::OPCODE::ADDU16_MMR6) + .value("ADDUH_QB", LIEF::assembly::mips::OPCODE::ADDUH_QB) + .value("ADDUH_QB_MMR2", LIEF::assembly::mips::OPCODE::ADDUH_QB_MMR2) + .value("ADDUH_R_QB", LIEF::assembly::mips::OPCODE::ADDUH_R_QB) + .value("ADDUH_R_QB_MMR2", LIEF::assembly::mips::OPCODE::ADDUH_R_QB_MMR2) + .value("ADDU_MMR6", LIEF::assembly::mips::OPCODE::ADDU_MMR6) + .value("ADDU_PH", LIEF::assembly::mips::OPCODE::ADDU_PH) + .value("ADDU_PH_MMR2", LIEF::assembly::mips::OPCODE::ADDU_PH_MMR2) + .value("ADDU_QB", LIEF::assembly::mips::OPCODE::ADDU_QB) + .value("ADDU_QB_MM", LIEF::assembly::mips::OPCODE::ADDU_QB_MM) + .value("ADDU_S_PH", LIEF::assembly::mips::OPCODE::ADDU_S_PH) + .value("ADDU_S_PH_MMR2", LIEF::assembly::mips::OPCODE::ADDU_S_PH_MMR2) + .value("ADDU_S_QB", LIEF::assembly::mips::OPCODE::ADDU_S_QB) + .value("ADDU_S_QB_MM", LIEF::assembly::mips::OPCODE::ADDU_S_QB_MM) + .value("ADDVI_B", LIEF::assembly::mips::OPCODE::ADDVI_B) + .value("ADDVI_D", LIEF::assembly::mips::OPCODE::ADDVI_D) + .value("ADDVI_H", LIEF::assembly::mips::OPCODE::ADDVI_H) + .value("ADDVI_W", LIEF::assembly::mips::OPCODE::ADDVI_W) + .value("ADDV_B", LIEF::assembly::mips::OPCODE::ADDV_B) + .value("ADDV_D", LIEF::assembly::mips::OPCODE::ADDV_D) + .value("ADDV_H", LIEF::assembly::mips::OPCODE::ADDV_H) + .value("ADDV_W", LIEF::assembly::mips::OPCODE::ADDV_W) + .value("ADDWC", LIEF::assembly::mips::OPCODE::ADDWC) + .value("ADDWC_MM", LIEF::assembly::mips::OPCODE::ADDWC_MM) + .value("ADD_A_B", LIEF::assembly::mips::OPCODE::ADD_A_B) + .value("ADD_A_D", LIEF::assembly::mips::OPCODE::ADD_A_D) + .value("ADD_A_H", LIEF::assembly::mips::OPCODE::ADD_A_H) + .value("ADD_A_W", LIEF::assembly::mips::OPCODE::ADD_A_W) + .value("ADD_MM", LIEF::assembly::mips::OPCODE::ADD_MM) + .value("ADD_MMR6", LIEF::assembly::mips::OPCODE::ADD_MMR6) + .value("ADDi", LIEF::assembly::mips::OPCODE::ADDi) + .value("ADDi_MM", LIEF::assembly::mips::OPCODE::ADDi_MM) + .value("ADDiu", LIEF::assembly::mips::OPCODE::ADDiu) + .value("ADDiu_MM", LIEF::assembly::mips::OPCODE::ADDiu_MM) + .value("ADDu", LIEF::assembly::mips::OPCODE::ADDu) + .value("ADDu_MM", LIEF::assembly::mips::OPCODE::ADDu_MM) + .value("ALIGN", LIEF::assembly::mips::OPCODE::ALIGN) + .value("ALIGN_MMR6", LIEF::assembly::mips::OPCODE::ALIGN_MMR6) + .value("ALUIPC", LIEF::assembly::mips::OPCODE::ALUIPC) + .value("ALUIPC_MMR6", LIEF::assembly::mips::OPCODE::ALUIPC_MMR6) + .value("AND", LIEF::assembly::mips::OPCODE::AND) + .value("AND16_MM", LIEF::assembly::mips::OPCODE::AND16_MM) + .value("AND16_MMR6", LIEF::assembly::mips::OPCODE::AND16_MMR6) + .value("AND64", LIEF::assembly::mips::OPCODE::AND64) + .value("ANDI16_MM", LIEF::assembly::mips::OPCODE::ANDI16_MM) + .value("ANDI16_MMR6", LIEF::assembly::mips::OPCODE::ANDI16_MMR6) + .value("ANDI_B", LIEF::assembly::mips::OPCODE::ANDI_B) + .value("ANDI_MMR6", LIEF::assembly::mips::OPCODE::ANDI_MMR6) + .value("AND_MM", LIEF::assembly::mips::OPCODE::AND_MM) + .value("AND_MMR6", LIEF::assembly::mips::OPCODE::AND_MMR6) + .value("AND_V", LIEF::assembly::mips::OPCODE::AND_V) + .value("ANDi", LIEF::assembly::mips::OPCODE::ANDi) + .value("ANDi64", LIEF::assembly::mips::OPCODE::ANDi64) + .value("ANDi_MM", LIEF::assembly::mips::OPCODE::ANDi_MM) + .value("APPEND", LIEF::assembly::mips::OPCODE::APPEND) + .value("APPEND_MMR2", LIEF::assembly::mips::OPCODE::APPEND_MMR2) + .value("ASUB_S_B", LIEF::assembly::mips::OPCODE::ASUB_S_B) + .value("ASUB_S_D", LIEF::assembly::mips::OPCODE::ASUB_S_D) + .value("ASUB_S_H", LIEF::assembly::mips::OPCODE::ASUB_S_H) + .value("ASUB_S_W", LIEF::assembly::mips::OPCODE::ASUB_S_W) + .value("ASUB_U_B", LIEF::assembly::mips::OPCODE::ASUB_U_B) + .value("ASUB_U_D", LIEF::assembly::mips::OPCODE::ASUB_U_D) + .value("ASUB_U_H", LIEF::assembly::mips::OPCODE::ASUB_U_H) + .value("ASUB_U_W", LIEF::assembly::mips::OPCODE::ASUB_U_W) + .value("AUI", LIEF::assembly::mips::OPCODE::AUI) + .value("AUIPC", LIEF::assembly::mips::OPCODE::AUIPC) + .value("AUIPC_MMR6", LIEF::assembly::mips::OPCODE::AUIPC_MMR6) + .value("AUI_MMR6", LIEF::assembly::mips::OPCODE::AUI_MMR6) + .value("AVER_S_B", LIEF::assembly::mips::OPCODE::AVER_S_B) + .value("AVER_S_D", LIEF::assembly::mips::OPCODE::AVER_S_D) + .value("AVER_S_H", LIEF::assembly::mips::OPCODE::AVER_S_H) + .value("AVER_S_W", LIEF::assembly::mips::OPCODE::AVER_S_W) + .value("AVER_U_B", LIEF::assembly::mips::OPCODE::AVER_U_B) + .value("AVER_U_D", LIEF::assembly::mips::OPCODE::AVER_U_D) + .value("AVER_U_H", LIEF::assembly::mips::OPCODE::AVER_U_H); + opcodes.value("AVER_U_W", LIEF::assembly::mips::OPCODE::AVER_U_W) + .value("AVE_S_B", LIEF::assembly::mips::OPCODE::AVE_S_B) + .value("AVE_S_D", LIEF::assembly::mips::OPCODE::AVE_S_D) + .value("AVE_S_H", LIEF::assembly::mips::OPCODE::AVE_S_H) + .value("AVE_S_W", LIEF::assembly::mips::OPCODE::AVE_S_W) + .value("AVE_U_B", LIEF::assembly::mips::OPCODE::AVE_U_B) + .value("AVE_U_D", LIEF::assembly::mips::OPCODE::AVE_U_D) + .value("AVE_U_H", LIEF::assembly::mips::OPCODE::AVE_U_H) + .value("AVE_U_W", LIEF::assembly::mips::OPCODE::AVE_U_W) + .value("AddiuRxImmX16", LIEF::assembly::mips::OPCODE::AddiuRxImmX16) + .value("AddiuRxPcImmX16", LIEF::assembly::mips::OPCODE::AddiuRxPcImmX16) + .value("AddiuRxRxImm16", LIEF::assembly::mips::OPCODE::AddiuRxRxImm16) + .value("AddiuRxRxImmX16", LIEF::assembly::mips::OPCODE::AddiuRxRxImmX16) + .value("AddiuRxRyOffMemX16", LIEF::assembly::mips::OPCODE::AddiuRxRyOffMemX16) + .value("AddiuSpImm16", LIEF::assembly::mips::OPCODE::AddiuSpImm16) + .value("AddiuSpImmX16", LIEF::assembly::mips::OPCODE::AddiuSpImmX16) + .value("AdduRxRyRz16", LIEF::assembly::mips::OPCODE::AdduRxRyRz16) + .value("AndRxRxRy16", LIEF::assembly::mips::OPCODE::AndRxRxRy16) + .value("B16_MM", LIEF::assembly::mips::OPCODE::B16_MM) + .value("BADDu", LIEF::assembly::mips::OPCODE::BADDu) + .value("BAL", LIEF::assembly::mips::OPCODE::BAL) + .value("BALC", LIEF::assembly::mips::OPCODE::BALC) + .value("BALC_MMR6", LIEF::assembly::mips::OPCODE::BALC_MMR6) + .value("BALIGN", LIEF::assembly::mips::OPCODE::BALIGN) + .value("BALIGN_MMR2", LIEF::assembly::mips::OPCODE::BALIGN_MMR2) + .value("BBIT0", LIEF::assembly::mips::OPCODE::BBIT0) + .value("BBIT032", LIEF::assembly::mips::OPCODE::BBIT032) + .value("BBIT1", LIEF::assembly::mips::OPCODE::BBIT1) + .value("BBIT132", LIEF::assembly::mips::OPCODE::BBIT132) + .value("BC", LIEF::assembly::mips::OPCODE::BC) + .value("BC16_MMR6", LIEF::assembly::mips::OPCODE::BC16_MMR6) + .value("BC1EQZ", LIEF::assembly::mips::OPCODE::BC1EQZ) + .value("BC1EQZC_MMR6", LIEF::assembly::mips::OPCODE::BC1EQZC_MMR6) + .value("BC1F", LIEF::assembly::mips::OPCODE::BC1F) + .value("BC1FL", LIEF::assembly::mips::OPCODE::BC1FL) + .value("BC1F_MM", LIEF::assembly::mips::OPCODE::BC1F_MM) + .value("BC1NEZ", LIEF::assembly::mips::OPCODE::BC1NEZ) + .value("BC1NEZC_MMR6", LIEF::assembly::mips::OPCODE::BC1NEZC_MMR6) + .value("BC1T", LIEF::assembly::mips::OPCODE::BC1T) + .value("BC1TL", LIEF::assembly::mips::OPCODE::BC1TL) + .value("BC1T_MM", LIEF::assembly::mips::OPCODE::BC1T_MM) + .value("BC2EQZ", LIEF::assembly::mips::OPCODE::BC2EQZ) + .value("BC2EQZC_MMR6", LIEF::assembly::mips::OPCODE::BC2EQZC_MMR6) + .value("BC2NEZ", LIEF::assembly::mips::OPCODE::BC2NEZ) + .value("BC2NEZC_MMR6", LIEF::assembly::mips::OPCODE::BC2NEZC_MMR6) + .value("BCLRI_B", LIEF::assembly::mips::OPCODE::BCLRI_B) + .value("BCLRI_D", LIEF::assembly::mips::OPCODE::BCLRI_D) + .value("BCLRI_H", LIEF::assembly::mips::OPCODE::BCLRI_H) + .value("BCLRI_W", LIEF::assembly::mips::OPCODE::BCLRI_W) + .value("BCLR_B", LIEF::assembly::mips::OPCODE::BCLR_B) + .value("BCLR_D", LIEF::assembly::mips::OPCODE::BCLR_D) + .value("BCLR_H", LIEF::assembly::mips::OPCODE::BCLR_H) + .value("BCLR_W", LIEF::assembly::mips::OPCODE::BCLR_W) + .value("BC_MMR6", LIEF::assembly::mips::OPCODE::BC_MMR6) + .value("BEQ", LIEF::assembly::mips::OPCODE::BEQ) + .value("BEQ64", LIEF::assembly::mips::OPCODE::BEQ64) + .value("BEQC", LIEF::assembly::mips::OPCODE::BEQC) + .value("BEQC64", LIEF::assembly::mips::OPCODE::BEQC64) + .value("BEQC_MMR6", LIEF::assembly::mips::OPCODE::BEQC_MMR6) + .value("BEQL", LIEF::assembly::mips::OPCODE::BEQL) + .value("BEQZ16_MM", LIEF::assembly::mips::OPCODE::BEQZ16_MM) + .value("BEQZALC", LIEF::assembly::mips::OPCODE::BEQZALC) + .value("BEQZALC_MMR6", LIEF::assembly::mips::OPCODE::BEQZALC_MMR6) + .value("BEQZC", LIEF::assembly::mips::OPCODE::BEQZC) + .value("BEQZC16_MMR6", LIEF::assembly::mips::OPCODE::BEQZC16_MMR6) + .value("BEQZC64", LIEF::assembly::mips::OPCODE::BEQZC64) + .value("BEQZC_MM", LIEF::assembly::mips::OPCODE::BEQZC_MM) + .value("BEQZC_MMR6", LIEF::assembly::mips::OPCODE::BEQZC_MMR6) + .value("BEQ_MM", LIEF::assembly::mips::OPCODE::BEQ_MM) + .value("BGEC", LIEF::assembly::mips::OPCODE::BGEC) + .value("BGEC64", LIEF::assembly::mips::OPCODE::BGEC64) + .value("BGEC_MMR6", LIEF::assembly::mips::OPCODE::BGEC_MMR6) + .value("BGEUC", LIEF::assembly::mips::OPCODE::BGEUC) + .value("BGEUC64", LIEF::assembly::mips::OPCODE::BGEUC64) + .value("BGEUC_MMR6", LIEF::assembly::mips::OPCODE::BGEUC_MMR6) + .value("BGEZ", LIEF::assembly::mips::OPCODE::BGEZ) + .value("BGEZ64", LIEF::assembly::mips::OPCODE::BGEZ64) + .value("BGEZAL", LIEF::assembly::mips::OPCODE::BGEZAL) + .value("BGEZALC", LIEF::assembly::mips::OPCODE::BGEZALC) + .value("BGEZALC_MMR6", LIEF::assembly::mips::OPCODE::BGEZALC_MMR6) + .value("BGEZALL", LIEF::assembly::mips::OPCODE::BGEZALL) + .value("BGEZALS_MM", LIEF::assembly::mips::OPCODE::BGEZALS_MM) + .value("BGEZAL_MM", LIEF::assembly::mips::OPCODE::BGEZAL_MM) + .value("BGEZC", LIEF::assembly::mips::OPCODE::BGEZC) + .value("BGEZC64", LIEF::assembly::mips::OPCODE::BGEZC64) + .value("BGEZC_MMR6", LIEF::assembly::mips::OPCODE::BGEZC_MMR6) + .value("BGEZL", LIEF::assembly::mips::OPCODE::BGEZL) + .value("BGEZ_MM", LIEF::assembly::mips::OPCODE::BGEZ_MM) + .value("BGTZ", LIEF::assembly::mips::OPCODE::BGTZ) + .value("BGTZ64", LIEF::assembly::mips::OPCODE::BGTZ64) + .value("BGTZALC", LIEF::assembly::mips::OPCODE::BGTZALC) + .value("BGTZALC_MMR6", LIEF::assembly::mips::OPCODE::BGTZALC_MMR6) + .value("BGTZC", LIEF::assembly::mips::OPCODE::BGTZC) + .value("BGTZC64", LIEF::assembly::mips::OPCODE::BGTZC64) + .value("BGTZC_MMR6", LIEF::assembly::mips::OPCODE::BGTZC_MMR6) + .value("BGTZL", LIEF::assembly::mips::OPCODE::BGTZL) + .value("BGTZ_MM", LIEF::assembly::mips::OPCODE::BGTZ_MM) + .value("BINSLI_B", LIEF::assembly::mips::OPCODE::BINSLI_B) + .value("BINSLI_D", LIEF::assembly::mips::OPCODE::BINSLI_D) + .value("BINSLI_H", LIEF::assembly::mips::OPCODE::BINSLI_H) + .value("BINSLI_W", LIEF::assembly::mips::OPCODE::BINSLI_W) + .value("BINSL_B", LIEF::assembly::mips::OPCODE::BINSL_B) + .value("BINSL_D", LIEF::assembly::mips::OPCODE::BINSL_D) + .value("BINSL_H", LIEF::assembly::mips::OPCODE::BINSL_H) + .value("BINSL_W", LIEF::assembly::mips::OPCODE::BINSL_W) + .value("BINSRI_B", LIEF::assembly::mips::OPCODE::BINSRI_B) + .value("BINSRI_D", LIEF::assembly::mips::OPCODE::BINSRI_D) + .value("BINSRI_H", LIEF::assembly::mips::OPCODE::BINSRI_H) + .value("BINSRI_W", LIEF::assembly::mips::OPCODE::BINSRI_W) + .value("BINSR_B", LIEF::assembly::mips::OPCODE::BINSR_B) + .value("BINSR_D", LIEF::assembly::mips::OPCODE::BINSR_D) + .value("BINSR_H", LIEF::assembly::mips::OPCODE::BINSR_H) + .value("BINSR_W", LIEF::assembly::mips::OPCODE::BINSR_W) + .value("BITREV", LIEF::assembly::mips::OPCODE::BITREV) + .value("BITREV_MM", LIEF::assembly::mips::OPCODE::BITREV_MM) + .value("BITSWAP", LIEF::assembly::mips::OPCODE::BITSWAP) + .value("BITSWAP_MMR6", LIEF::assembly::mips::OPCODE::BITSWAP_MMR6) + .value("BLEZ", LIEF::assembly::mips::OPCODE::BLEZ) + .value("BLEZ64", LIEF::assembly::mips::OPCODE::BLEZ64) + .value("BLEZALC", LIEF::assembly::mips::OPCODE::BLEZALC) + .value("BLEZALC_MMR6", LIEF::assembly::mips::OPCODE::BLEZALC_MMR6) + .value("BLEZC", LIEF::assembly::mips::OPCODE::BLEZC) + .value("BLEZC64", LIEF::assembly::mips::OPCODE::BLEZC64) + .value("BLEZC_MMR6", LIEF::assembly::mips::OPCODE::BLEZC_MMR6) + .value("BLEZL", LIEF::assembly::mips::OPCODE::BLEZL) + .value("BLEZ_MM", LIEF::assembly::mips::OPCODE::BLEZ_MM) + .value("BLTC", LIEF::assembly::mips::OPCODE::BLTC) + .value("BLTC64", LIEF::assembly::mips::OPCODE::BLTC64) + .value("BLTC_MMR6", LIEF::assembly::mips::OPCODE::BLTC_MMR6) + .value("BLTUC", LIEF::assembly::mips::OPCODE::BLTUC) + .value("BLTUC64", LIEF::assembly::mips::OPCODE::BLTUC64) + .value("BLTUC_MMR6", LIEF::assembly::mips::OPCODE::BLTUC_MMR6) + .value("BLTZ", LIEF::assembly::mips::OPCODE::BLTZ) + .value("BLTZ64", LIEF::assembly::mips::OPCODE::BLTZ64) + .value("BLTZAL", LIEF::assembly::mips::OPCODE::BLTZAL) + .value("BLTZALC", LIEF::assembly::mips::OPCODE::BLTZALC) + .value("BLTZALC_MMR6", LIEF::assembly::mips::OPCODE::BLTZALC_MMR6) + .value("BLTZALL", LIEF::assembly::mips::OPCODE::BLTZALL) + .value("BLTZALS_MM", LIEF::assembly::mips::OPCODE::BLTZALS_MM) + .value("BLTZAL_MM", LIEF::assembly::mips::OPCODE::BLTZAL_MM) + .value("BLTZC", LIEF::assembly::mips::OPCODE::BLTZC) + .value("BLTZC64", LIEF::assembly::mips::OPCODE::BLTZC64) + .value("BLTZC_MMR6", LIEF::assembly::mips::OPCODE::BLTZC_MMR6) + .value("BLTZL", LIEF::assembly::mips::OPCODE::BLTZL) + .value("BLTZ_MM", LIEF::assembly::mips::OPCODE::BLTZ_MM) + .value("BMNZI_B", LIEF::assembly::mips::OPCODE::BMNZI_B) + .value("BMNZ_V", LIEF::assembly::mips::OPCODE::BMNZ_V) + .value("BMZI_B", LIEF::assembly::mips::OPCODE::BMZI_B) + .value("BMZ_V", LIEF::assembly::mips::OPCODE::BMZ_V) + .value("BNE", LIEF::assembly::mips::OPCODE::BNE) + .value("BNE64", LIEF::assembly::mips::OPCODE::BNE64) + .value("BNEC", LIEF::assembly::mips::OPCODE::BNEC) + .value("BNEC64", LIEF::assembly::mips::OPCODE::BNEC64) + .value("BNEC_MMR6", LIEF::assembly::mips::OPCODE::BNEC_MMR6) + .value("BNEGI_B", LIEF::assembly::mips::OPCODE::BNEGI_B) + .value("BNEGI_D", LIEF::assembly::mips::OPCODE::BNEGI_D) + .value("BNEGI_H", LIEF::assembly::mips::OPCODE::BNEGI_H) + .value("BNEGI_W", LIEF::assembly::mips::OPCODE::BNEGI_W) + .value("BNEG_B", LIEF::assembly::mips::OPCODE::BNEG_B) + .value("BNEG_D", LIEF::assembly::mips::OPCODE::BNEG_D) + .value("BNEG_H", LIEF::assembly::mips::OPCODE::BNEG_H) + .value("BNEG_W", LIEF::assembly::mips::OPCODE::BNEG_W) + .value("BNEL", LIEF::assembly::mips::OPCODE::BNEL) + .value("BNEZ16_MM", LIEF::assembly::mips::OPCODE::BNEZ16_MM) + .value("BNEZALC", LIEF::assembly::mips::OPCODE::BNEZALC) + .value("BNEZALC_MMR6", LIEF::assembly::mips::OPCODE::BNEZALC_MMR6) + .value("BNEZC", LIEF::assembly::mips::OPCODE::BNEZC) + .value("BNEZC16_MMR6", LIEF::assembly::mips::OPCODE::BNEZC16_MMR6) + .value("BNEZC64", LIEF::assembly::mips::OPCODE::BNEZC64) + .value("BNEZC_MM", LIEF::assembly::mips::OPCODE::BNEZC_MM) + .value("BNEZC_MMR6", LIEF::assembly::mips::OPCODE::BNEZC_MMR6) + .value("BNE_MM", LIEF::assembly::mips::OPCODE::BNE_MM) + .value("BNVC", LIEF::assembly::mips::OPCODE::BNVC) + .value("BNVC_MMR6", LIEF::assembly::mips::OPCODE::BNVC_MMR6) + .value("BNZ_B", LIEF::assembly::mips::OPCODE::BNZ_B) + .value("BNZ_D", LIEF::assembly::mips::OPCODE::BNZ_D) + .value("BNZ_H", LIEF::assembly::mips::OPCODE::BNZ_H) + .value("BNZ_V", LIEF::assembly::mips::OPCODE::BNZ_V) + .value("BNZ_W", LIEF::assembly::mips::OPCODE::BNZ_W) + .value("BOVC", LIEF::assembly::mips::OPCODE::BOVC) + .value("BOVC_MMR6", LIEF::assembly::mips::OPCODE::BOVC_MMR6) + .value("BPOSGE32", LIEF::assembly::mips::OPCODE::BPOSGE32) + .value("BPOSGE32C_MMR3", LIEF::assembly::mips::OPCODE::BPOSGE32C_MMR3) + .value("BPOSGE32_MM", LIEF::assembly::mips::OPCODE::BPOSGE32_MM) + .value("BREAK", LIEF::assembly::mips::OPCODE::BREAK) + .value("BREAK16_MM", LIEF::assembly::mips::OPCODE::BREAK16_MM) + .value("BREAK16_MMR6", LIEF::assembly::mips::OPCODE::BREAK16_MMR6) + .value("BREAK_MM", LIEF::assembly::mips::OPCODE::BREAK_MM) + .value("BREAK_MMR6", LIEF::assembly::mips::OPCODE::BREAK_MMR6) + .value("BSELI_B", LIEF::assembly::mips::OPCODE::BSELI_B) + .value("BSEL_V", LIEF::assembly::mips::OPCODE::BSEL_V) + .value("BSETI_B", LIEF::assembly::mips::OPCODE::BSETI_B) + .value("BSETI_D", LIEF::assembly::mips::OPCODE::BSETI_D) + .value("BSETI_H", LIEF::assembly::mips::OPCODE::BSETI_H) + .value("BSETI_W", LIEF::assembly::mips::OPCODE::BSETI_W) + .value("BSET_B", LIEF::assembly::mips::OPCODE::BSET_B) + .value("BSET_D", LIEF::assembly::mips::OPCODE::BSET_D) + .value("BSET_H", LIEF::assembly::mips::OPCODE::BSET_H) + .value("BSET_W", LIEF::assembly::mips::OPCODE::BSET_W) + .value("BZ_B", LIEF::assembly::mips::OPCODE::BZ_B) + .value("BZ_D", LIEF::assembly::mips::OPCODE::BZ_D) + .value("BZ_H", LIEF::assembly::mips::OPCODE::BZ_H) + .value("BZ_V", LIEF::assembly::mips::OPCODE::BZ_V) + .value("BZ_W", LIEF::assembly::mips::OPCODE::BZ_W) + .value("BeqzRxImm16", LIEF::assembly::mips::OPCODE::BeqzRxImm16) + .value("BeqzRxImmX16", LIEF::assembly::mips::OPCODE::BeqzRxImmX16) + .value("Bimm16", LIEF::assembly::mips::OPCODE::Bimm16) + .value("BimmX16", LIEF::assembly::mips::OPCODE::BimmX16) + .value("BnezRxImm16", LIEF::assembly::mips::OPCODE::BnezRxImm16) + .value("BnezRxImmX16", LIEF::assembly::mips::OPCODE::BnezRxImmX16) + .value("Break16", LIEF::assembly::mips::OPCODE::Break16) + .value("Bteqz16", LIEF::assembly::mips::OPCODE::Bteqz16) + .value("BteqzX16", LIEF::assembly::mips::OPCODE::BteqzX16) + .value("Btnez16", LIEF::assembly::mips::OPCODE::Btnez16) + .value("BtnezX16", LIEF::assembly::mips::OPCODE::BtnezX16) + .value("CACHE", LIEF::assembly::mips::OPCODE::CACHE) + .value("CACHEE", LIEF::assembly::mips::OPCODE::CACHEE) + .value("CACHEE_MM", LIEF::assembly::mips::OPCODE::CACHEE_MM) + .value("CACHE_MM", LIEF::assembly::mips::OPCODE::CACHE_MM) + .value("CACHE_MMR6", LIEF::assembly::mips::OPCODE::CACHE_MMR6) + .value("CACHE_R6", LIEF::assembly::mips::OPCODE::CACHE_R6) + .value("CEIL_L_D64", LIEF::assembly::mips::OPCODE::CEIL_L_D64) + .value("CEIL_L_D_MMR6", LIEF::assembly::mips::OPCODE::CEIL_L_D_MMR6) + .value("CEIL_L_S", LIEF::assembly::mips::OPCODE::CEIL_L_S) + .value("CEIL_L_S_MMR6", LIEF::assembly::mips::OPCODE::CEIL_L_S_MMR6) + .value("CEIL_W_D32", LIEF::assembly::mips::OPCODE::CEIL_W_D32) + .value("CEIL_W_D64", LIEF::assembly::mips::OPCODE::CEIL_W_D64) + .value("CEIL_W_D_MMR6", LIEF::assembly::mips::OPCODE::CEIL_W_D_MMR6) + .value("CEIL_W_MM", LIEF::assembly::mips::OPCODE::CEIL_W_MM) + .value("CEIL_W_S", LIEF::assembly::mips::OPCODE::CEIL_W_S) + .value("CEIL_W_S_MM", LIEF::assembly::mips::OPCODE::CEIL_W_S_MM) + .value("CEIL_W_S_MMR6", LIEF::assembly::mips::OPCODE::CEIL_W_S_MMR6) + .value("CEQI_B", LIEF::assembly::mips::OPCODE::CEQI_B) + .value("CEQI_D", LIEF::assembly::mips::OPCODE::CEQI_D) + .value("CEQI_H", LIEF::assembly::mips::OPCODE::CEQI_H) + .value("CEQI_W", LIEF::assembly::mips::OPCODE::CEQI_W) + .value("CEQ_B", LIEF::assembly::mips::OPCODE::CEQ_B) + .value("CEQ_D", LIEF::assembly::mips::OPCODE::CEQ_D) + .value("CEQ_H", LIEF::assembly::mips::OPCODE::CEQ_H) + .value("CEQ_W", LIEF::assembly::mips::OPCODE::CEQ_W) + .value("CFC1", LIEF::assembly::mips::OPCODE::CFC1) + .value("CFC1_MM", LIEF::assembly::mips::OPCODE::CFC1_MM) + .value("CFC2_MM", LIEF::assembly::mips::OPCODE::CFC2_MM) + .value("CFCMSA", LIEF::assembly::mips::OPCODE::CFCMSA) + .value("CINS", LIEF::assembly::mips::OPCODE::CINS) + .value("CINS32", LIEF::assembly::mips::OPCODE::CINS32) + .value("CINS64_32", LIEF::assembly::mips::OPCODE::CINS64_32) + .value("CINS_i32", LIEF::assembly::mips::OPCODE::CINS_i32) + .value("CLASS_D", LIEF::assembly::mips::OPCODE::CLASS_D) + .value("CLASS_D_MMR6", LIEF::assembly::mips::OPCODE::CLASS_D_MMR6) + .value("CLASS_S", LIEF::assembly::mips::OPCODE::CLASS_S) + .value("CLASS_S_MMR6", LIEF::assembly::mips::OPCODE::CLASS_S_MMR6) + .value("CLEI_S_B", LIEF::assembly::mips::OPCODE::CLEI_S_B) + .value("CLEI_S_D", LIEF::assembly::mips::OPCODE::CLEI_S_D) + .value("CLEI_S_H", LIEF::assembly::mips::OPCODE::CLEI_S_H) + .value("CLEI_S_W", LIEF::assembly::mips::OPCODE::CLEI_S_W) + .value("CLEI_U_B", LIEF::assembly::mips::OPCODE::CLEI_U_B) + .value("CLEI_U_D", LIEF::assembly::mips::OPCODE::CLEI_U_D) + .value("CLEI_U_H", LIEF::assembly::mips::OPCODE::CLEI_U_H) + .value("CLEI_U_W", LIEF::assembly::mips::OPCODE::CLEI_U_W) + .value("CLE_S_B", LIEF::assembly::mips::OPCODE::CLE_S_B) + .value("CLE_S_D", LIEF::assembly::mips::OPCODE::CLE_S_D) + .value("CLE_S_H", LIEF::assembly::mips::OPCODE::CLE_S_H) + .value("CLE_S_W", LIEF::assembly::mips::OPCODE::CLE_S_W) + .value("CLE_U_B", LIEF::assembly::mips::OPCODE::CLE_U_B) + .value("CLE_U_D", LIEF::assembly::mips::OPCODE::CLE_U_D) + .value("CLE_U_H", LIEF::assembly::mips::OPCODE::CLE_U_H) + .value("CLE_U_W", LIEF::assembly::mips::OPCODE::CLE_U_W) + .value("CLO", LIEF::assembly::mips::OPCODE::CLO) + .value("CLO_MM", LIEF::assembly::mips::OPCODE::CLO_MM) + .value("CLO_MMR6", LIEF::assembly::mips::OPCODE::CLO_MMR6) + .value("CLO_R6", LIEF::assembly::mips::OPCODE::CLO_R6) + .value("CLTI_S_B", LIEF::assembly::mips::OPCODE::CLTI_S_B) + .value("CLTI_S_D", LIEF::assembly::mips::OPCODE::CLTI_S_D) + .value("CLTI_S_H", LIEF::assembly::mips::OPCODE::CLTI_S_H) + .value("CLTI_S_W", LIEF::assembly::mips::OPCODE::CLTI_S_W) + .value("CLTI_U_B", LIEF::assembly::mips::OPCODE::CLTI_U_B) + .value("CLTI_U_D", LIEF::assembly::mips::OPCODE::CLTI_U_D) + .value("CLTI_U_H", LIEF::assembly::mips::OPCODE::CLTI_U_H) + .value("CLTI_U_W", LIEF::assembly::mips::OPCODE::CLTI_U_W) + .value("CLT_S_B", LIEF::assembly::mips::OPCODE::CLT_S_B) + .value("CLT_S_D", LIEF::assembly::mips::OPCODE::CLT_S_D) + .value("CLT_S_H", LIEF::assembly::mips::OPCODE::CLT_S_H) + .value("CLT_S_W", LIEF::assembly::mips::OPCODE::CLT_S_W) + .value("CLT_U_B", LIEF::assembly::mips::OPCODE::CLT_U_B) + .value("CLT_U_D", LIEF::assembly::mips::OPCODE::CLT_U_D) + .value("CLT_U_H", LIEF::assembly::mips::OPCODE::CLT_U_H) + .value("CLT_U_W", LIEF::assembly::mips::OPCODE::CLT_U_W) + .value("CLZ", LIEF::assembly::mips::OPCODE::CLZ) + .value("CLZ_MM", LIEF::assembly::mips::OPCODE::CLZ_MM) + .value("CLZ_MMR6", LIEF::assembly::mips::OPCODE::CLZ_MMR6) + .value("CLZ_R6", LIEF::assembly::mips::OPCODE::CLZ_R6) + .value("CMPGDU_EQ_QB", LIEF::assembly::mips::OPCODE::CMPGDU_EQ_QB) + .value("CMPGDU_EQ_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_EQ_QB_MMR2) + .value("CMPGDU_LE_QB", LIEF::assembly::mips::OPCODE::CMPGDU_LE_QB) + .value("CMPGDU_LE_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_LE_QB_MMR2) + .value("CMPGDU_LT_QB", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB) + .value("CMPGDU_LT_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB_MMR2) + .value("CMPGU_EQ_QB", LIEF::assembly::mips::OPCODE::CMPGU_EQ_QB) + .value("CMPGU_EQ_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_EQ_QB_MM); + opcodes.value("CMPGU_LE_QB", LIEF::assembly::mips::OPCODE::CMPGU_LE_QB) + .value("CMPGU_LE_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_LE_QB_MM) + .value("CMPGU_LT_QB", LIEF::assembly::mips::OPCODE::CMPGU_LT_QB) + .value("CMPGU_LT_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_LT_QB_MM) + .value("CMPU_EQ_QB", LIEF::assembly::mips::OPCODE::CMPU_EQ_QB) + .value("CMPU_EQ_QB_MM", LIEF::assembly::mips::OPCODE::CMPU_EQ_QB_MM) + .value("CMPU_LE_QB", LIEF::assembly::mips::OPCODE::CMPU_LE_QB) + .value("CMPU_LE_QB_MM", LIEF::assembly::mips::OPCODE::CMPU_LE_QB_MM) + .value("CMPU_LT_QB", LIEF::assembly::mips::OPCODE::CMPU_LT_QB) + .value("CMPU_LT_QB_MM", LIEF::assembly::mips::OPCODE::CMPU_LT_QB_MM) + .value("CMP_AF_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_AF_D_MMR6) + .value("CMP_AF_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_AF_S_MMR6) + .value("CMP_EQ_D", LIEF::assembly::mips::OPCODE::CMP_EQ_D) + .value("CMP_EQ_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_EQ_D_MMR6) + .value("CMP_EQ_PH", LIEF::assembly::mips::OPCODE::CMP_EQ_PH) + .value("CMP_EQ_PH_MM", LIEF::assembly::mips::OPCODE::CMP_EQ_PH_MM) + .value("CMP_EQ_S", LIEF::assembly::mips::OPCODE::CMP_EQ_S) + .value("CMP_EQ_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_EQ_S_MMR6) + .value("CMP_F_D", LIEF::assembly::mips::OPCODE::CMP_F_D) + .value("CMP_F_S", LIEF::assembly::mips::OPCODE::CMP_F_S) + .value("CMP_LE_D", LIEF::assembly::mips::OPCODE::CMP_LE_D) + .value("CMP_LE_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_LE_D_MMR6) + .value("CMP_LE_PH", LIEF::assembly::mips::OPCODE::CMP_LE_PH) + .value("CMP_LE_PH_MM", LIEF::assembly::mips::OPCODE::CMP_LE_PH_MM) + .value("CMP_LE_S", LIEF::assembly::mips::OPCODE::CMP_LE_S) + .value("CMP_LE_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_LE_S_MMR6) + .value("CMP_LT_D", LIEF::assembly::mips::OPCODE::CMP_LT_D) + .value("CMP_LT_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_LT_D_MMR6) + .value("CMP_LT_PH", LIEF::assembly::mips::OPCODE::CMP_LT_PH) + .value("CMP_LT_PH_MM", LIEF::assembly::mips::OPCODE::CMP_LT_PH_MM) + .value("CMP_LT_S", LIEF::assembly::mips::OPCODE::CMP_LT_S) + .value("CMP_LT_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_LT_S_MMR6) + .value("CMP_SAF_D", LIEF::assembly::mips::OPCODE::CMP_SAF_D) + .value("CMP_SAF_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SAF_D_MMR6) + .value("CMP_SAF_S", LIEF::assembly::mips::OPCODE::CMP_SAF_S) + .value("CMP_SAF_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SAF_S_MMR6) + .value("CMP_SEQ_D", LIEF::assembly::mips::OPCODE::CMP_SEQ_D) + .value("CMP_SEQ_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SEQ_D_MMR6) + .value("CMP_SEQ_S", LIEF::assembly::mips::OPCODE::CMP_SEQ_S) + .value("CMP_SEQ_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SEQ_S_MMR6) + .value("CMP_SLE_D", LIEF::assembly::mips::OPCODE::CMP_SLE_D) + .value("CMP_SLE_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SLE_D_MMR6) + .value("CMP_SLE_S", LIEF::assembly::mips::OPCODE::CMP_SLE_S) + .value("CMP_SLE_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SLE_S_MMR6) + .value("CMP_SLT_D", LIEF::assembly::mips::OPCODE::CMP_SLT_D) + .value("CMP_SLT_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SLT_D_MMR6) + .value("CMP_SLT_S", LIEF::assembly::mips::OPCODE::CMP_SLT_S) + .value("CMP_SLT_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SLT_S_MMR6) + .value("CMP_SUEQ_D", LIEF::assembly::mips::OPCODE::CMP_SUEQ_D) + .value("CMP_SUEQ_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SUEQ_D_MMR6) + .value("CMP_SUEQ_S", LIEF::assembly::mips::OPCODE::CMP_SUEQ_S) + .value("CMP_SUEQ_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SUEQ_S_MMR6) + .value("CMP_SULE_D", LIEF::assembly::mips::OPCODE::CMP_SULE_D) + .value("CMP_SULE_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SULE_D_MMR6) + .value("CMP_SULE_S", LIEF::assembly::mips::OPCODE::CMP_SULE_S) + .value("CMP_SULE_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SULE_S_MMR6) + .value("CMP_SULT_D", LIEF::assembly::mips::OPCODE::CMP_SULT_D) + .value("CMP_SULT_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SULT_D_MMR6) + .value("CMP_SULT_S", LIEF::assembly::mips::OPCODE::CMP_SULT_S) + .value("CMP_SULT_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SULT_S_MMR6) + .value("CMP_SUN_D", LIEF::assembly::mips::OPCODE::CMP_SUN_D) + .value("CMP_SUN_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_SUN_D_MMR6) + .value("CMP_SUN_S", LIEF::assembly::mips::OPCODE::CMP_SUN_S) + .value("CMP_SUN_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_SUN_S_MMR6) + .value("CMP_UEQ_D", LIEF::assembly::mips::OPCODE::CMP_UEQ_D) + .value("CMP_UEQ_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_UEQ_D_MMR6) + .value("CMP_UEQ_S", LIEF::assembly::mips::OPCODE::CMP_UEQ_S) + .value("CMP_UEQ_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_UEQ_S_MMR6) + .value("CMP_ULE_D", LIEF::assembly::mips::OPCODE::CMP_ULE_D) + .value("CMP_ULE_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_ULE_D_MMR6) + .value("CMP_ULE_S", LIEF::assembly::mips::OPCODE::CMP_ULE_S) + .value("CMP_ULE_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_ULE_S_MMR6) + .value("CMP_ULT_D", LIEF::assembly::mips::OPCODE::CMP_ULT_D) + .value("CMP_ULT_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_ULT_D_MMR6) + .value("CMP_ULT_S", LIEF::assembly::mips::OPCODE::CMP_ULT_S) + .value("CMP_ULT_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_ULT_S_MMR6) + .value("CMP_UN_D", LIEF::assembly::mips::OPCODE::CMP_UN_D) + .value("CMP_UN_D_MMR6", LIEF::assembly::mips::OPCODE::CMP_UN_D_MMR6) + .value("CMP_UN_S", LIEF::assembly::mips::OPCODE::CMP_UN_S) + .value("CMP_UN_S_MMR6", LIEF::assembly::mips::OPCODE::CMP_UN_S_MMR6) + .value("COPY_S_B", LIEF::assembly::mips::OPCODE::COPY_S_B) + .value("COPY_S_D", LIEF::assembly::mips::OPCODE::COPY_S_D) + .value("COPY_S_H", LIEF::assembly::mips::OPCODE::COPY_S_H) + .value("COPY_S_W", LIEF::assembly::mips::OPCODE::COPY_S_W) + .value("COPY_U_B", LIEF::assembly::mips::OPCODE::COPY_U_B) + .value("COPY_U_H", LIEF::assembly::mips::OPCODE::COPY_U_H) + .value("COPY_U_W", LIEF::assembly::mips::OPCODE::COPY_U_W) + .value("CRC32B", LIEF::assembly::mips::OPCODE::CRC32B) + .value("CRC32CB", LIEF::assembly::mips::OPCODE::CRC32CB) + .value("CRC32CD", LIEF::assembly::mips::OPCODE::CRC32CD) + .value("CRC32CH", LIEF::assembly::mips::OPCODE::CRC32CH) + .value("CRC32CW", LIEF::assembly::mips::OPCODE::CRC32CW) + .value("CRC32D", LIEF::assembly::mips::OPCODE::CRC32D) + .value("CRC32H", LIEF::assembly::mips::OPCODE::CRC32H) + .value("CRC32W", LIEF::assembly::mips::OPCODE::CRC32W) + .value("CTC1", LIEF::assembly::mips::OPCODE::CTC1) + .value("CTC1_MM", LIEF::assembly::mips::OPCODE::CTC1_MM) + .value("CTC2_MM", LIEF::assembly::mips::OPCODE::CTC2_MM) + .value("CTCMSA", LIEF::assembly::mips::OPCODE::CTCMSA) + .value("CVT_D32_S", LIEF::assembly::mips::OPCODE::CVT_D32_S) + .value("CVT_D32_S_MM", LIEF::assembly::mips::OPCODE::CVT_D32_S_MM) + .value("CVT_D32_W", LIEF::assembly::mips::OPCODE::CVT_D32_W) + .value("CVT_D32_W_MM", LIEF::assembly::mips::OPCODE::CVT_D32_W_MM) + .value("CVT_D64_L", LIEF::assembly::mips::OPCODE::CVT_D64_L) + .value("CVT_D64_S", LIEF::assembly::mips::OPCODE::CVT_D64_S) + .value("CVT_D64_S_MM", LIEF::assembly::mips::OPCODE::CVT_D64_S_MM) + .value("CVT_D64_W", LIEF::assembly::mips::OPCODE::CVT_D64_W) + .value("CVT_D64_W_MM", LIEF::assembly::mips::OPCODE::CVT_D64_W_MM) + .value("CVT_D_L_MMR6", LIEF::assembly::mips::OPCODE::CVT_D_L_MMR6) + .value("CVT_L_D64", LIEF::assembly::mips::OPCODE::CVT_L_D64) + .value("CVT_L_D64_MM", LIEF::assembly::mips::OPCODE::CVT_L_D64_MM) + .value("CVT_L_D_MMR6", LIEF::assembly::mips::OPCODE::CVT_L_D_MMR6) + .value("CVT_L_S", LIEF::assembly::mips::OPCODE::CVT_L_S) + .value("CVT_L_S_MM", LIEF::assembly::mips::OPCODE::CVT_L_S_MM) + .value("CVT_L_S_MMR6", LIEF::assembly::mips::OPCODE::CVT_L_S_MMR6) + .value("CVT_PS_PW64", LIEF::assembly::mips::OPCODE::CVT_PS_PW64) + .value("CVT_PS_S64", LIEF::assembly::mips::OPCODE::CVT_PS_S64) + .value("CVT_PW_PS64", LIEF::assembly::mips::OPCODE::CVT_PW_PS64) + .value("CVT_S_D32", LIEF::assembly::mips::OPCODE::CVT_S_D32) + .value("CVT_S_D32_MM", LIEF::assembly::mips::OPCODE::CVT_S_D32_MM) + .value("CVT_S_D64", LIEF::assembly::mips::OPCODE::CVT_S_D64) + .value("CVT_S_D64_MM", LIEF::assembly::mips::OPCODE::CVT_S_D64_MM) + .value("CVT_S_L", LIEF::assembly::mips::OPCODE::CVT_S_L) + .value("CVT_S_L_MMR6", LIEF::assembly::mips::OPCODE::CVT_S_L_MMR6) + .value("CVT_S_PL64", LIEF::assembly::mips::OPCODE::CVT_S_PL64) + .value("CVT_S_PU64", LIEF::assembly::mips::OPCODE::CVT_S_PU64) + .value("CVT_S_W", LIEF::assembly::mips::OPCODE::CVT_S_W) + .value("CVT_S_W_MM", LIEF::assembly::mips::OPCODE::CVT_S_W_MM) + .value("CVT_S_W_MMR6", LIEF::assembly::mips::OPCODE::CVT_S_W_MMR6) + .value("CVT_W_D32", LIEF::assembly::mips::OPCODE::CVT_W_D32) + .value("CVT_W_D32_MM", LIEF::assembly::mips::OPCODE::CVT_W_D32_MM) + .value("CVT_W_D64", LIEF::assembly::mips::OPCODE::CVT_W_D64) + .value("CVT_W_D64_MM", LIEF::assembly::mips::OPCODE::CVT_W_D64_MM) + .value("CVT_W_S", LIEF::assembly::mips::OPCODE::CVT_W_S) + .value("CVT_W_S_MM", LIEF::assembly::mips::OPCODE::CVT_W_S_MM) + .value("CVT_W_S_MMR6", LIEF::assembly::mips::OPCODE::CVT_W_S_MMR6) + .value("C_EQ_D32", LIEF::assembly::mips::OPCODE::C_EQ_D32) + .value("C_EQ_D32_MM", LIEF::assembly::mips::OPCODE::C_EQ_D32_MM) + .value("C_EQ_D64", LIEF::assembly::mips::OPCODE::C_EQ_D64) + .value("C_EQ_D64_MM", LIEF::assembly::mips::OPCODE::C_EQ_D64_MM) + .value("C_EQ_S", LIEF::assembly::mips::OPCODE::C_EQ_S) + .value("C_EQ_S_MM", LIEF::assembly::mips::OPCODE::C_EQ_S_MM) + .value("C_F_D32", LIEF::assembly::mips::OPCODE::C_F_D32) + .value("C_F_D32_MM", LIEF::assembly::mips::OPCODE::C_F_D32_MM) + .value("C_F_D64", LIEF::assembly::mips::OPCODE::C_F_D64) + .value("C_F_D64_MM", LIEF::assembly::mips::OPCODE::C_F_D64_MM) + .value("C_F_S", LIEF::assembly::mips::OPCODE::C_F_S) + .value("C_F_S_MM", LIEF::assembly::mips::OPCODE::C_F_S_MM) + .value("C_LE_D32", LIEF::assembly::mips::OPCODE::C_LE_D32) + .value("C_LE_D32_MM", LIEF::assembly::mips::OPCODE::C_LE_D32_MM) + .value("C_LE_D64", LIEF::assembly::mips::OPCODE::C_LE_D64) + .value("C_LE_D64_MM", LIEF::assembly::mips::OPCODE::C_LE_D64_MM) + .value("C_LE_S", LIEF::assembly::mips::OPCODE::C_LE_S) + .value("C_LE_S_MM", LIEF::assembly::mips::OPCODE::C_LE_S_MM) + .value("C_LT_D32", LIEF::assembly::mips::OPCODE::C_LT_D32) + .value("C_LT_D32_MM", LIEF::assembly::mips::OPCODE::C_LT_D32_MM) + .value("C_LT_D64", LIEF::assembly::mips::OPCODE::C_LT_D64) + .value("C_LT_D64_MM", LIEF::assembly::mips::OPCODE::C_LT_D64_MM) + .value("C_LT_S", LIEF::assembly::mips::OPCODE::C_LT_S) + .value("C_LT_S_MM", LIEF::assembly::mips::OPCODE::C_LT_S_MM) + .value("C_NGE_D32", LIEF::assembly::mips::OPCODE::C_NGE_D32) + .value("C_NGE_D32_MM", LIEF::assembly::mips::OPCODE::C_NGE_D32_MM) + .value("C_NGE_D64", LIEF::assembly::mips::OPCODE::C_NGE_D64) + .value("C_NGE_D64_MM", LIEF::assembly::mips::OPCODE::C_NGE_D64_MM) + .value("C_NGE_S", LIEF::assembly::mips::OPCODE::C_NGE_S) + .value("C_NGE_S_MM", LIEF::assembly::mips::OPCODE::C_NGE_S_MM) + .value("C_NGLE_D32", LIEF::assembly::mips::OPCODE::C_NGLE_D32) + .value("C_NGLE_D32_MM", LIEF::assembly::mips::OPCODE::C_NGLE_D32_MM) + .value("C_NGLE_D64", LIEF::assembly::mips::OPCODE::C_NGLE_D64) + .value("C_NGLE_D64_MM", LIEF::assembly::mips::OPCODE::C_NGLE_D64_MM) + .value("C_NGLE_S", LIEF::assembly::mips::OPCODE::C_NGLE_S) + .value("C_NGLE_S_MM", LIEF::assembly::mips::OPCODE::C_NGLE_S_MM) + .value("C_NGL_D32", LIEF::assembly::mips::OPCODE::C_NGL_D32) + .value("C_NGL_D32_MM", LIEF::assembly::mips::OPCODE::C_NGL_D32_MM) + .value("C_NGL_D64", LIEF::assembly::mips::OPCODE::C_NGL_D64) + .value("C_NGL_D64_MM", LIEF::assembly::mips::OPCODE::C_NGL_D64_MM) + .value("C_NGL_S", LIEF::assembly::mips::OPCODE::C_NGL_S) + .value("C_NGL_S_MM", LIEF::assembly::mips::OPCODE::C_NGL_S_MM) + .value("C_NGT_D32", LIEF::assembly::mips::OPCODE::C_NGT_D32) + .value("C_NGT_D32_MM", LIEF::assembly::mips::OPCODE::C_NGT_D32_MM) + .value("C_NGT_D64", LIEF::assembly::mips::OPCODE::C_NGT_D64) + .value("C_NGT_D64_MM", LIEF::assembly::mips::OPCODE::C_NGT_D64_MM) + .value("C_NGT_S", LIEF::assembly::mips::OPCODE::C_NGT_S) + .value("C_NGT_S_MM", LIEF::assembly::mips::OPCODE::C_NGT_S_MM) + .value("C_OLE_D32", LIEF::assembly::mips::OPCODE::C_OLE_D32) + .value("C_OLE_D32_MM", LIEF::assembly::mips::OPCODE::C_OLE_D32_MM) + .value("C_OLE_D64", LIEF::assembly::mips::OPCODE::C_OLE_D64) + .value("C_OLE_D64_MM", LIEF::assembly::mips::OPCODE::C_OLE_D64_MM) + .value("C_OLE_S", LIEF::assembly::mips::OPCODE::C_OLE_S) + .value("C_OLE_S_MM", LIEF::assembly::mips::OPCODE::C_OLE_S_MM) + .value("C_OLT_D32", LIEF::assembly::mips::OPCODE::C_OLT_D32) + .value("C_OLT_D32_MM", LIEF::assembly::mips::OPCODE::C_OLT_D32_MM) + .value("C_OLT_D64", LIEF::assembly::mips::OPCODE::C_OLT_D64) + .value("C_OLT_D64_MM", LIEF::assembly::mips::OPCODE::C_OLT_D64_MM) + .value("C_OLT_S", LIEF::assembly::mips::OPCODE::C_OLT_S) + .value("C_OLT_S_MM", LIEF::assembly::mips::OPCODE::C_OLT_S_MM) + .value("C_SEQ_D32", LIEF::assembly::mips::OPCODE::C_SEQ_D32) + .value("C_SEQ_D32_MM", LIEF::assembly::mips::OPCODE::C_SEQ_D32_MM) + .value("C_SEQ_D64", LIEF::assembly::mips::OPCODE::C_SEQ_D64) + .value("C_SEQ_D64_MM", LIEF::assembly::mips::OPCODE::C_SEQ_D64_MM) + .value("C_SEQ_S", LIEF::assembly::mips::OPCODE::C_SEQ_S) + .value("C_SEQ_S_MM", LIEF::assembly::mips::OPCODE::C_SEQ_S_MM) + .value("C_SF_D32", LIEF::assembly::mips::OPCODE::C_SF_D32) + .value("C_SF_D32_MM", LIEF::assembly::mips::OPCODE::C_SF_D32_MM) + .value("C_SF_D64", LIEF::assembly::mips::OPCODE::C_SF_D64) + .value("C_SF_D64_MM", LIEF::assembly::mips::OPCODE::C_SF_D64_MM) + .value("C_SF_S", LIEF::assembly::mips::OPCODE::C_SF_S) + .value("C_SF_S_MM", LIEF::assembly::mips::OPCODE::C_SF_S_MM) + .value("C_UEQ_D32", LIEF::assembly::mips::OPCODE::C_UEQ_D32) + .value("C_UEQ_D32_MM", LIEF::assembly::mips::OPCODE::C_UEQ_D32_MM) + .value("C_UEQ_D64", LIEF::assembly::mips::OPCODE::C_UEQ_D64) + .value("C_UEQ_D64_MM", LIEF::assembly::mips::OPCODE::C_UEQ_D64_MM) + .value("C_UEQ_S", LIEF::assembly::mips::OPCODE::C_UEQ_S) + .value("C_UEQ_S_MM", LIEF::assembly::mips::OPCODE::C_UEQ_S_MM) + .value("C_ULE_D32", LIEF::assembly::mips::OPCODE::C_ULE_D32) + .value("C_ULE_D32_MM", LIEF::assembly::mips::OPCODE::C_ULE_D32_MM) + .value("C_ULE_D64", LIEF::assembly::mips::OPCODE::C_ULE_D64) + .value("C_ULE_D64_MM", LIEF::assembly::mips::OPCODE::C_ULE_D64_MM) + .value("C_ULE_S", LIEF::assembly::mips::OPCODE::C_ULE_S) + .value("C_ULE_S_MM", LIEF::assembly::mips::OPCODE::C_ULE_S_MM) + .value("C_ULT_D32", LIEF::assembly::mips::OPCODE::C_ULT_D32) + .value("C_ULT_D32_MM", LIEF::assembly::mips::OPCODE::C_ULT_D32_MM) + .value("C_ULT_D64", LIEF::assembly::mips::OPCODE::C_ULT_D64) + .value("C_ULT_D64_MM", LIEF::assembly::mips::OPCODE::C_ULT_D64_MM) + .value("C_ULT_S", LIEF::assembly::mips::OPCODE::C_ULT_S) + .value("C_ULT_S_MM", LIEF::assembly::mips::OPCODE::C_ULT_S_MM) + .value("C_UN_D32", LIEF::assembly::mips::OPCODE::C_UN_D32) + .value("C_UN_D32_MM", LIEF::assembly::mips::OPCODE::C_UN_D32_MM) + .value("C_UN_D64", LIEF::assembly::mips::OPCODE::C_UN_D64) + .value("C_UN_D64_MM", LIEF::assembly::mips::OPCODE::C_UN_D64_MM) + .value("C_UN_S", LIEF::assembly::mips::OPCODE::C_UN_S) + .value("C_UN_S_MM", LIEF::assembly::mips::OPCODE::C_UN_S_MM) + .value("CmpRxRy16", LIEF::assembly::mips::OPCODE::CmpRxRy16) + .value("CmpiRxImm16", LIEF::assembly::mips::OPCODE::CmpiRxImm16) + .value("CmpiRxImmX16", LIEF::assembly::mips::OPCODE::CmpiRxImmX16) + .value("DADD", LIEF::assembly::mips::OPCODE::DADD) + .value("DADDi", LIEF::assembly::mips::OPCODE::DADDi) + .value("DADDiu", LIEF::assembly::mips::OPCODE::DADDiu) + .value("DADDu", LIEF::assembly::mips::OPCODE::DADDu) + .value("DAHI", LIEF::assembly::mips::OPCODE::DAHI) + .value("DALIGN", LIEF::assembly::mips::OPCODE::DALIGN) + .value("DATI", LIEF::assembly::mips::OPCODE::DATI) + .value("DAUI", LIEF::assembly::mips::OPCODE::DAUI) + .value("DBITSWAP", LIEF::assembly::mips::OPCODE::DBITSWAP) + .value("DCLO", LIEF::assembly::mips::OPCODE::DCLO) + .value("DCLO_R6", LIEF::assembly::mips::OPCODE::DCLO_R6) + .value("DCLZ", LIEF::assembly::mips::OPCODE::DCLZ) + .value("DCLZ_R6", LIEF::assembly::mips::OPCODE::DCLZ_R6) + .value("DDIV", LIEF::assembly::mips::OPCODE::DDIV) + .value("DDIVU", LIEF::assembly::mips::OPCODE::DDIVU) + .value("DERET", LIEF::assembly::mips::OPCODE::DERET) + .value("DERET_MM", LIEF::assembly::mips::OPCODE::DERET_MM) + .value("DERET_MMR6", LIEF::assembly::mips::OPCODE::DERET_MMR6) + .value("DEXT", LIEF::assembly::mips::OPCODE::DEXT) + .value("DEXT64_32", LIEF::assembly::mips::OPCODE::DEXT64_32) + .value("DEXTM", LIEF::assembly::mips::OPCODE::DEXTM) + .value("DEXTU", LIEF::assembly::mips::OPCODE::DEXTU) + .value("DI", LIEF::assembly::mips::OPCODE::DI) + .value("DINS", LIEF::assembly::mips::OPCODE::DINS) + .value("DINSM", LIEF::assembly::mips::OPCODE::DINSM) + .value("DINSU", LIEF::assembly::mips::OPCODE::DINSU) + .value("DIV", LIEF::assembly::mips::OPCODE::DIV) + .value("DIVU", LIEF::assembly::mips::OPCODE::DIVU) + .value("DIVU_MMR6", LIEF::assembly::mips::OPCODE::DIVU_MMR6) + .value("DIV_MMR6", LIEF::assembly::mips::OPCODE::DIV_MMR6) + .value("DIV_S_B", LIEF::assembly::mips::OPCODE::DIV_S_B) + .value("DIV_S_D", LIEF::assembly::mips::OPCODE::DIV_S_D) + .value("DIV_S_H", LIEF::assembly::mips::OPCODE::DIV_S_H) + .value("DIV_S_W", LIEF::assembly::mips::OPCODE::DIV_S_W) + .value("DIV_U_B", LIEF::assembly::mips::OPCODE::DIV_U_B) + .value("DIV_U_D", LIEF::assembly::mips::OPCODE::DIV_U_D) + .value("DIV_U_H", LIEF::assembly::mips::OPCODE::DIV_U_H) + .value("DIV_U_W", LIEF::assembly::mips::OPCODE::DIV_U_W) + .value("DI_MM", LIEF::assembly::mips::OPCODE::DI_MM) + .value("DI_MMR6", LIEF::assembly::mips::OPCODE::DI_MMR6) + .value("DLSA", LIEF::assembly::mips::OPCODE::DLSA) + .value("DLSA_R6", LIEF::assembly::mips::OPCODE::DLSA_R6) + .value("DMFC0", LIEF::assembly::mips::OPCODE::DMFC0) + .value("DMFC1", LIEF::assembly::mips::OPCODE::DMFC1) + .value("DMFC2", LIEF::assembly::mips::OPCODE::DMFC2) + .value("DMFC2_OCTEON", LIEF::assembly::mips::OPCODE::DMFC2_OCTEON) + .value("DMFGC0", LIEF::assembly::mips::OPCODE::DMFGC0) + .value("DMOD", LIEF::assembly::mips::OPCODE::DMOD) + .value("DMODU", LIEF::assembly::mips::OPCODE::DMODU) + .value("DMT", LIEF::assembly::mips::OPCODE::DMT) + .value("DMTC0", LIEF::assembly::mips::OPCODE::DMTC0) + .value("DMTC1", LIEF::assembly::mips::OPCODE::DMTC1) + .value("DMTC2", LIEF::assembly::mips::OPCODE::DMTC2) + .value("DMTC2_OCTEON", LIEF::assembly::mips::OPCODE::DMTC2_OCTEON) + .value("DMTGC0", LIEF::assembly::mips::OPCODE::DMTGC0) + .value("DMUH", LIEF::assembly::mips::OPCODE::DMUH) + .value("DMUHU", LIEF::assembly::mips::OPCODE::DMUHU) + .value("DMUL", LIEF::assembly::mips::OPCODE::DMUL) + .value("DMULT", LIEF::assembly::mips::OPCODE::DMULT) + .value("DMULTu", LIEF::assembly::mips::OPCODE::DMULTu) + .value("DMULU", LIEF::assembly::mips::OPCODE::DMULU) + .value("DMUL_R6", LIEF::assembly::mips::OPCODE::DMUL_R6) + .value("DOTP_S_D", LIEF::assembly::mips::OPCODE::DOTP_S_D) + .value("DOTP_S_H", LIEF::assembly::mips::OPCODE::DOTP_S_H) + .value("DOTP_S_W", LIEF::assembly::mips::OPCODE::DOTP_S_W); + opcodes.value("DOTP_U_D", LIEF::assembly::mips::OPCODE::DOTP_U_D) + .value("DOTP_U_H", LIEF::assembly::mips::OPCODE::DOTP_U_H) + .value("DOTP_U_W", LIEF::assembly::mips::OPCODE::DOTP_U_W) + .value("DPADD_S_D", LIEF::assembly::mips::OPCODE::DPADD_S_D) + .value("DPADD_S_H", LIEF::assembly::mips::OPCODE::DPADD_S_H) + .value("DPADD_S_W", LIEF::assembly::mips::OPCODE::DPADD_S_W) + .value("DPADD_U_D", LIEF::assembly::mips::OPCODE::DPADD_U_D) + .value("DPADD_U_H", LIEF::assembly::mips::OPCODE::DPADD_U_H) + .value("DPADD_U_W", LIEF::assembly::mips::OPCODE::DPADD_U_W) + .value("DPAQX_SA_W_PH", LIEF::assembly::mips::OPCODE::DPAQX_SA_W_PH) + .value("DPAQX_SA_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPAQX_SA_W_PH_MMR2) + .value("DPAQX_S_W_PH", LIEF::assembly::mips::OPCODE::DPAQX_S_W_PH) + .value("DPAQX_S_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPAQX_S_W_PH_MMR2) + .value("DPAQ_SA_L_W", LIEF::assembly::mips::OPCODE::DPAQ_SA_L_W) + .value("DPAQ_SA_L_W_MM", LIEF::assembly::mips::OPCODE::DPAQ_SA_L_W_MM) + .value("DPAQ_S_W_PH", LIEF::assembly::mips::OPCODE::DPAQ_S_W_PH) + .value("DPAQ_S_W_PH_MM", LIEF::assembly::mips::OPCODE::DPAQ_S_W_PH_MM) + .value("DPAU_H_QBL", LIEF::assembly::mips::OPCODE::DPAU_H_QBL) + .value("DPAU_H_QBL_MM", LIEF::assembly::mips::OPCODE::DPAU_H_QBL_MM) + .value("DPAU_H_QBR", LIEF::assembly::mips::OPCODE::DPAU_H_QBR) + .value("DPAU_H_QBR_MM", LIEF::assembly::mips::OPCODE::DPAU_H_QBR_MM) + .value("DPAX_W_PH", LIEF::assembly::mips::OPCODE::DPAX_W_PH) + .value("DPAX_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPAX_W_PH_MMR2) + .value("DPA_W_PH", LIEF::assembly::mips::OPCODE::DPA_W_PH) + .value("DPA_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPA_W_PH_MMR2) + .value("DPOP", LIEF::assembly::mips::OPCODE::DPOP) + .value("DPSQX_SA_W_PH", LIEF::assembly::mips::OPCODE::DPSQX_SA_W_PH) + .value("DPSQX_SA_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPSQX_SA_W_PH_MMR2) + .value("DPSQX_S_W_PH", LIEF::assembly::mips::OPCODE::DPSQX_S_W_PH) + .value("DPSQX_S_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPSQX_S_W_PH_MMR2) + .value("DPSQ_SA_L_W", LIEF::assembly::mips::OPCODE::DPSQ_SA_L_W) + .value("DPSQ_SA_L_W_MM", LIEF::assembly::mips::OPCODE::DPSQ_SA_L_W_MM) + .value("DPSQ_S_W_PH", LIEF::assembly::mips::OPCODE::DPSQ_S_W_PH) + .value("DPSQ_S_W_PH_MM", LIEF::assembly::mips::OPCODE::DPSQ_S_W_PH_MM) + .value("DPSUB_S_D", LIEF::assembly::mips::OPCODE::DPSUB_S_D) + .value("DPSUB_S_H", LIEF::assembly::mips::OPCODE::DPSUB_S_H) + .value("DPSUB_S_W", LIEF::assembly::mips::OPCODE::DPSUB_S_W) + .value("DPSUB_U_D", LIEF::assembly::mips::OPCODE::DPSUB_U_D) + .value("DPSUB_U_H", LIEF::assembly::mips::OPCODE::DPSUB_U_H) + .value("DPSUB_U_W", LIEF::assembly::mips::OPCODE::DPSUB_U_W) + .value("DPSU_H_QBL", LIEF::assembly::mips::OPCODE::DPSU_H_QBL) + .value("DPSU_H_QBL_MM", LIEF::assembly::mips::OPCODE::DPSU_H_QBL_MM) + .value("DPSU_H_QBR", LIEF::assembly::mips::OPCODE::DPSU_H_QBR) + .value("DPSU_H_QBR_MM", LIEF::assembly::mips::OPCODE::DPSU_H_QBR_MM) + .value("DPSX_W_PH", LIEF::assembly::mips::OPCODE::DPSX_W_PH) + .value("DPSX_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPSX_W_PH_MMR2) + .value("DPS_W_PH", LIEF::assembly::mips::OPCODE::DPS_W_PH) + .value("DPS_W_PH_MMR2", LIEF::assembly::mips::OPCODE::DPS_W_PH_MMR2) + .value("DROTR", LIEF::assembly::mips::OPCODE::DROTR) + .value("DROTR32", LIEF::assembly::mips::OPCODE::DROTR32) + .value("DROTRV", LIEF::assembly::mips::OPCODE::DROTRV) + .value("DSBH", LIEF::assembly::mips::OPCODE::DSBH) + .value("DSDIV", LIEF::assembly::mips::OPCODE::DSDIV) + .value("DSHD", LIEF::assembly::mips::OPCODE::DSHD) + .value("DSLL", LIEF::assembly::mips::OPCODE::DSLL) + .value("DSLL32", LIEF::assembly::mips::OPCODE::DSLL32) + .value("DSLL64_32", LIEF::assembly::mips::OPCODE::DSLL64_32) + .value("DSLLV", LIEF::assembly::mips::OPCODE::DSLLV) + .value("DSRA", LIEF::assembly::mips::OPCODE::DSRA) + .value("DSRA32", LIEF::assembly::mips::OPCODE::DSRA32) + .value("DSRAV", LIEF::assembly::mips::OPCODE::DSRAV) + .value("DSRL", LIEF::assembly::mips::OPCODE::DSRL) + .value("DSRL32", LIEF::assembly::mips::OPCODE::DSRL32) + .value("DSRLV", LIEF::assembly::mips::OPCODE::DSRLV) + .value("DSUB", LIEF::assembly::mips::OPCODE::DSUB) + .value("DSUBu", LIEF::assembly::mips::OPCODE::DSUBu) + .value("DUDIV", LIEF::assembly::mips::OPCODE::DUDIV) + .value("DVP", LIEF::assembly::mips::OPCODE::DVP) + .value("DVPE", LIEF::assembly::mips::OPCODE::DVPE) + .value("DVP_MMR6", LIEF::assembly::mips::OPCODE::DVP_MMR6) + .value("DivRxRy16", LIEF::assembly::mips::OPCODE::DivRxRy16) + .value("DivuRxRy16", LIEF::assembly::mips::OPCODE::DivuRxRy16) + .value("EHB", LIEF::assembly::mips::OPCODE::EHB) + .value("EHB_MM", LIEF::assembly::mips::OPCODE::EHB_MM) + .value("EHB_MMR6", LIEF::assembly::mips::OPCODE::EHB_MMR6) + .value("EI", LIEF::assembly::mips::OPCODE::EI) + .value("EI_MM", LIEF::assembly::mips::OPCODE::EI_MM) + .value("EI_MMR6", LIEF::assembly::mips::OPCODE::EI_MMR6) + .value("EMT", LIEF::assembly::mips::OPCODE::EMT) + .value("ERET", LIEF::assembly::mips::OPCODE::ERET) + .value("ERETNC", LIEF::assembly::mips::OPCODE::ERETNC) + .value("ERETNC_MMR6", LIEF::assembly::mips::OPCODE::ERETNC_MMR6) + .value("ERET_MM", LIEF::assembly::mips::OPCODE::ERET_MM) + .value("ERET_MMR6", LIEF::assembly::mips::OPCODE::ERET_MMR6) + .value("EVP", LIEF::assembly::mips::OPCODE::EVP) + .value("EVPE", LIEF::assembly::mips::OPCODE::EVPE) + .value("EVP_MMR6", LIEF::assembly::mips::OPCODE::EVP_MMR6) + .value("EXT", LIEF::assembly::mips::OPCODE::EXT) + .value("EXTP", LIEF::assembly::mips::OPCODE::EXTP) + .value("EXTPDP", LIEF::assembly::mips::OPCODE::EXTPDP) + .value("EXTPDPV", LIEF::assembly::mips::OPCODE::EXTPDPV) + .value("EXTPDPV_MM", LIEF::assembly::mips::OPCODE::EXTPDPV_MM) + .value("EXTPDP_MM", LIEF::assembly::mips::OPCODE::EXTPDP_MM) + .value("EXTPV", LIEF::assembly::mips::OPCODE::EXTPV) + .value("EXTPV_MM", LIEF::assembly::mips::OPCODE::EXTPV_MM) + .value("EXTP_MM", LIEF::assembly::mips::OPCODE::EXTP_MM) + .value("EXTRV_RS_W", LIEF::assembly::mips::OPCODE::EXTRV_RS_W) + .value("EXTRV_RS_W_MM", LIEF::assembly::mips::OPCODE::EXTRV_RS_W_MM) + .value("EXTRV_R_W", LIEF::assembly::mips::OPCODE::EXTRV_R_W) + .value("EXTRV_R_W_MM", LIEF::assembly::mips::OPCODE::EXTRV_R_W_MM) + .value("EXTRV_S_H", LIEF::assembly::mips::OPCODE::EXTRV_S_H) + .value("EXTRV_S_H_MM", LIEF::assembly::mips::OPCODE::EXTRV_S_H_MM) + .value("EXTRV_W", LIEF::assembly::mips::OPCODE::EXTRV_W) + .value("EXTRV_W_MM", LIEF::assembly::mips::OPCODE::EXTRV_W_MM) + .value("EXTR_RS_W", LIEF::assembly::mips::OPCODE::EXTR_RS_W) + .value("EXTR_RS_W_MM", LIEF::assembly::mips::OPCODE::EXTR_RS_W_MM) + .value("EXTR_R_W", LIEF::assembly::mips::OPCODE::EXTR_R_W) + .value("EXTR_R_W_MM", LIEF::assembly::mips::OPCODE::EXTR_R_W_MM) + .value("EXTR_S_H", LIEF::assembly::mips::OPCODE::EXTR_S_H) + .value("EXTR_S_H_MM", LIEF::assembly::mips::OPCODE::EXTR_S_H_MM) + .value("EXTR_W", LIEF::assembly::mips::OPCODE::EXTR_W) + .value("EXTR_W_MM", LIEF::assembly::mips::OPCODE::EXTR_W_MM) + .value("EXTS", LIEF::assembly::mips::OPCODE::EXTS) + .value("EXTS32", LIEF::assembly::mips::OPCODE::EXTS32) + .value("EXT_MM", LIEF::assembly::mips::OPCODE::EXT_MM) + .value("EXT_MMR6", LIEF::assembly::mips::OPCODE::EXT_MMR6) + .value("FABS_D32", LIEF::assembly::mips::OPCODE::FABS_D32) + .value("FABS_D32_MM", LIEF::assembly::mips::OPCODE::FABS_D32_MM) + .value("FABS_D64", LIEF::assembly::mips::OPCODE::FABS_D64) + .value("FABS_D64_MM", LIEF::assembly::mips::OPCODE::FABS_D64_MM) + .value("FABS_S", LIEF::assembly::mips::OPCODE::FABS_S) + .value("FABS_S_MM", LIEF::assembly::mips::OPCODE::FABS_S_MM) + .value("FADD_D", LIEF::assembly::mips::OPCODE::FADD_D) + .value("FADD_D32", LIEF::assembly::mips::OPCODE::FADD_D32) + .value("FADD_D32_MM", LIEF::assembly::mips::OPCODE::FADD_D32_MM) + .value("FADD_D64", LIEF::assembly::mips::OPCODE::FADD_D64) + .value("FADD_D64_MM", LIEF::assembly::mips::OPCODE::FADD_D64_MM) + .value("FADD_PS64", LIEF::assembly::mips::OPCODE::FADD_PS64) + .value("FADD_S", LIEF::assembly::mips::OPCODE::FADD_S) + .value("FADD_S_MM", LIEF::assembly::mips::OPCODE::FADD_S_MM) + .value("FADD_S_MMR6", LIEF::assembly::mips::OPCODE::FADD_S_MMR6) + .value("FADD_W", LIEF::assembly::mips::OPCODE::FADD_W) + .value("FCAF_D", LIEF::assembly::mips::OPCODE::FCAF_D) + .value("FCAF_W", LIEF::assembly::mips::OPCODE::FCAF_W) + .value("FCEQ_D", LIEF::assembly::mips::OPCODE::FCEQ_D) + .value("FCEQ_W", LIEF::assembly::mips::OPCODE::FCEQ_W) + .value("FCLASS_D", LIEF::assembly::mips::OPCODE::FCLASS_D) + .value("FCLASS_W", LIEF::assembly::mips::OPCODE::FCLASS_W) + .value("FCLE_D", LIEF::assembly::mips::OPCODE::FCLE_D) + .value("FCLE_W", LIEF::assembly::mips::OPCODE::FCLE_W) + .value("FCLT_D", LIEF::assembly::mips::OPCODE::FCLT_D) + .value("FCLT_W", LIEF::assembly::mips::OPCODE::FCLT_W) + .value("FCMP_D32", LIEF::assembly::mips::OPCODE::FCMP_D32) + .value("FCMP_D32_MM", LIEF::assembly::mips::OPCODE::FCMP_D32_MM) + .value("FCMP_D64", LIEF::assembly::mips::OPCODE::FCMP_D64) + .value("FCMP_S32", LIEF::assembly::mips::OPCODE::FCMP_S32) + .value("FCMP_S32_MM", LIEF::assembly::mips::OPCODE::FCMP_S32_MM) + .value("FCNE_D", LIEF::assembly::mips::OPCODE::FCNE_D) + .value("FCNE_W", LIEF::assembly::mips::OPCODE::FCNE_W) + .value("FCOR_D", LIEF::assembly::mips::OPCODE::FCOR_D) + .value("FCOR_W", LIEF::assembly::mips::OPCODE::FCOR_W) + .value("FCUEQ_D", LIEF::assembly::mips::OPCODE::FCUEQ_D) + .value("FCUEQ_W", LIEF::assembly::mips::OPCODE::FCUEQ_W) + .value("FCULE_D", LIEF::assembly::mips::OPCODE::FCULE_D) + .value("FCULE_W", LIEF::assembly::mips::OPCODE::FCULE_W) + .value("FCULT_D", LIEF::assembly::mips::OPCODE::FCULT_D) + .value("FCULT_W", LIEF::assembly::mips::OPCODE::FCULT_W) + .value("FCUNE_D", LIEF::assembly::mips::OPCODE::FCUNE_D) + .value("FCUNE_W", LIEF::assembly::mips::OPCODE::FCUNE_W) + .value("FCUN_D", LIEF::assembly::mips::OPCODE::FCUN_D) + .value("FCUN_W", LIEF::assembly::mips::OPCODE::FCUN_W) + .value("FDIV_D", LIEF::assembly::mips::OPCODE::FDIV_D) + .value("FDIV_D32", LIEF::assembly::mips::OPCODE::FDIV_D32) + .value("FDIV_D32_MM", LIEF::assembly::mips::OPCODE::FDIV_D32_MM) + .value("FDIV_D64", LIEF::assembly::mips::OPCODE::FDIV_D64) + .value("FDIV_D64_MM", LIEF::assembly::mips::OPCODE::FDIV_D64_MM) + .value("FDIV_S", LIEF::assembly::mips::OPCODE::FDIV_S) + .value("FDIV_S_MM", LIEF::assembly::mips::OPCODE::FDIV_S_MM) + .value("FDIV_S_MMR6", LIEF::assembly::mips::OPCODE::FDIV_S_MMR6) + .value("FDIV_W", LIEF::assembly::mips::OPCODE::FDIV_W) + .value("FEXDO_H", LIEF::assembly::mips::OPCODE::FEXDO_H) + .value("FEXDO_W", LIEF::assembly::mips::OPCODE::FEXDO_W) + .value("FEXP2_D", LIEF::assembly::mips::OPCODE::FEXP2_D) + .value("FEXP2_W", LIEF::assembly::mips::OPCODE::FEXP2_W) + .value("FEXUPL_D", LIEF::assembly::mips::OPCODE::FEXUPL_D) + .value("FEXUPL_W", LIEF::assembly::mips::OPCODE::FEXUPL_W) + .value("FEXUPR_D", LIEF::assembly::mips::OPCODE::FEXUPR_D) + .value("FEXUPR_W", LIEF::assembly::mips::OPCODE::FEXUPR_W) + .value("FFINT_S_D", LIEF::assembly::mips::OPCODE::FFINT_S_D) + .value("FFINT_S_W", LIEF::assembly::mips::OPCODE::FFINT_S_W) + .value("FFINT_U_D", LIEF::assembly::mips::OPCODE::FFINT_U_D) + .value("FFINT_U_W", LIEF::assembly::mips::OPCODE::FFINT_U_W) + .value("FFQL_D", LIEF::assembly::mips::OPCODE::FFQL_D) + .value("FFQL_W", LIEF::assembly::mips::OPCODE::FFQL_W) + .value("FFQR_D", LIEF::assembly::mips::OPCODE::FFQR_D) + .value("FFQR_W", LIEF::assembly::mips::OPCODE::FFQR_W) + .value("FILL_B", LIEF::assembly::mips::OPCODE::FILL_B) + .value("FILL_D", LIEF::assembly::mips::OPCODE::FILL_D) + .value("FILL_H", LIEF::assembly::mips::OPCODE::FILL_H) + .value("FILL_W", LIEF::assembly::mips::OPCODE::FILL_W) + .value("FLOG2_D", LIEF::assembly::mips::OPCODE::FLOG2_D) + .value("FLOG2_W", LIEF::assembly::mips::OPCODE::FLOG2_W) + .value("FLOOR_L_D64", LIEF::assembly::mips::OPCODE::FLOOR_L_D64) + .value("FLOOR_L_D_MMR6", LIEF::assembly::mips::OPCODE::FLOOR_L_D_MMR6) + .value("FLOOR_L_S", LIEF::assembly::mips::OPCODE::FLOOR_L_S) + .value("FLOOR_L_S_MMR6", LIEF::assembly::mips::OPCODE::FLOOR_L_S_MMR6) + .value("FLOOR_W_D32", LIEF::assembly::mips::OPCODE::FLOOR_W_D32) + .value("FLOOR_W_D64", LIEF::assembly::mips::OPCODE::FLOOR_W_D64) + .value("FLOOR_W_D_MMR6", LIEF::assembly::mips::OPCODE::FLOOR_W_D_MMR6) + .value("FLOOR_W_MM", LIEF::assembly::mips::OPCODE::FLOOR_W_MM) + .value("FLOOR_W_S", LIEF::assembly::mips::OPCODE::FLOOR_W_S) + .value("FLOOR_W_S_MM", LIEF::assembly::mips::OPCODE::FLOOR_W_S_MM) + .value("FLOOR_W_S_MMR6", LIEF::assembly::mips::OPCODE::FLOOR_W_S_MMR6) + .value("FMADD_D", LIEF::assembly::mips::OPCODE::FMADD_D) + .value("FMADD_W", LIEF::assembly::mips::OPCODE::FMADD_W) + .value("FMAX_A_D", LIEF::assembly::mips::OPCODE::FMAX_A_D) + .value("FMAX_A_W", LIEF::assembly::mips::OPCODE::FMAX_A_W) + .value("FMAX_D", LIEF::assembly::mips::OPCODE::FMAX_D) + .value("FMAX_W", LIEF::assembly::mips::OPCODE::FMAX_W) + .value("FMIN_A_D", LIEF::assembly::mips::OPCODE::FMIN_A_D) + .value("FMIN_A_W", LIEF::assembly::mips::OPCODE::FMIN_A_W) + .value("FMIN_D", LIEF::assembly::mips::OPCODE::FMIN_D) + .value("FMIN_W", LIEF::assembly::mips::OPCODE::FMIN_W) + .value("FMOV_D32", LIEF::assembly::mips::OPCODE::FMOV_D32) + .value("FMOV_D32_MM", LIEF::assembly::mips::OPCODE::FMOV_D32_MM) + .value("FMOV_D64", LIEF::assembly::mips::OPCODE::FMOV_D64) + .value("FMOV_D64_MM", LIEF::assembly::mips::OPCODE::FMOV_D64_MM) + .value("FMOV_D_MMR6", LIEF::assembly::mips::OPCODE::FMOV_D_MMR6) + .value("FMOV_S", LIEF::assembly::mips::OPCODE::FMOV_S) + .value("FMOV_S_MM", LIEF::assembly::mips::OPCODE::FMOV_S_MM) + .value("FMOV_S_MMR6", LIEF::assembly::mips::OPCODE::FMOV_S_MMR6) + .value("FMSUB_D", LIEF::assembly::mips::OPCODE::FMSUB_D) + .value("FMSUB_W", LIEF::assembly::mips::OPCODE::FMSUB_W) + .value("FMUL_D", LIEF::assembly::mips::OPCODE::FMUL_D) + .value("FMUL_D32", LIEF::assembly::mips::OPCODE::FMUL_D32) + .value("FMUL_D32_MM", LIEF::assembly::mips::OPCODE::FMUL_D32_MM) + .value("FMUL_D64", LIEF::assembly::mips::OPCODE::FMUL_D64) + .value("FMUL_D64_MM", LIEF::assembly::mips::OPCODE::FMUL_D64_MM) + .value("FMUL_PS64", LIEF::assembly::mips::OPCODE::FMUL_PS64) + .value("FMUL_S", LIEF::assembly::mips::OPCODE::FMUL_S) + .value("FMUL_S_MM", LIEF::assembly::mips::OPCODE::FMUL_S_MM) + .value("FMUL_S_MMR6", LIEF::assembly::mips::OPCODE::FMUL_S_MMR6) + .value("FMUL_W", LIEF::assembly::mips::OPCODE::FMUL_W) + .value("FNEG_D32", LIEF::assembly::mips::OPCODE::FNEG_D32) + .value("FNEG_D32_MM", LIEF::assembly::mips::OPCODE::FNEG_D32_MM) + .value("FNEG_D64", LIEF::assembly::mips::OPCODE::FNEG_D64) + .value("FNEG_D64_MM", LIEF::assembly::mips::OPCODE::FNEG_D64_MM) + .value("FNEG_S", LIEF::assembly::mips::OPCODE::FNEG_S) + .value("FNEG_S_MM", LIEF::assembly::mips::OPCODE::FNEG_S_MM) + .value("FNEG_S_MMR6", LIEF::assembly::mips::OPCODE::FNEG_S_MMR6) + .value("FORK", LIEF::assembly::mips::OPCODE::FORK) + .value("FRCP_D", LIEF::assembly::mips::OPCODE::FRCP_D) + .value("FRCP_W", LIEF::assembly::mips::OPCODE::FRCP_W) + .value("FRINT_D", LIEF::assembly::mips::OPCODE::FRINT_D) + .value("FRINT_W", LIEF::assembly::mips::OPCODE::FRINT_W) + .value("FRSQRT_D", LIEF::assembly::mips::OPCODE::FRSQRT_D) + .value("FRSQRT_W", LIEF::assembly::mips::OPCODE::FRSQRT_W) + .value("FSAF_D", LIEF::assembly::mips::OPCODE::FSAF_D) + .value("FSAF_W", LIEF::assembly::mips::OPCODE::FSAF_W) + .value("FSEQ_D", LIEF::assembly::mips::OPCODE::FSEQ_D) + .value("FSEQ_W", LIEF::assembly::mips::OPCODE::FSEQ_W) + .value("FSLE_D", LIEF::assembly::mips::OPCODE::FSLE_D) + .value("FSLE_W", LIEF::assembly::mips::OPCODE::FSLE_W) + .value("FSLT_D", LIEF::assembly::mips::OPCODE::FSLT_D) + .value("FSLT_W", LIEF::assembly::mips::OPCODE::FSLT_W) + .value("FSNE_D", LIEF::assembly::mips::OPCODE::FSNE_D) + .value("FSNE_W", LIEF::assembly::mips::OPCODE::FSNE_W) + .value("FSOR_D", LIEF::assembly::mips::OPCODE::FSOR_D) + .value("FSOR_W", LIEF::assembly::mips::OPCODE::FSOR_W) + .value("FSQRT_D", LIEF::assembly::mips::OPCODE::FSQRT_D) + .value("FSQRT_D32", LIEF::assembly::mips::OPCODE::FSQRT_D32) + .value("FSQRT_D32_MM", LIEF::assembly::mips::OPCODE::FSQRT_D32_MM) + .value("FSQRT_D64", LIEF::assembly::mips::OPCODE::FSQRT_D64) + .value("FSQRT_D64_MM", LIEF::assembly::mips::OPCODE::FSQRT_D64_MM) + .value("FSQRT_S", LIEF::assembly::mips::OPCODE::FSQRT_S) + .value("FSQRT_S_MM", LIEF::assembly::mips::OPCODE::FSQRT_S_MM) + .value("FSQRT_W", LIEF::assembly::mips::OPCODE::FSQRT_W) + .value("FSUB_D", LIEF::assembly::mips::OPCODE::FSUB_D) + .value("FSUB_D32", LIEF::assembly::mips::OPCODE::FSUB_D32) + .value("FSUB_D32_MM", LIEF::assembly::mips::OPCODE::FSUB_D32_MM) + .value("FSUB_D64", LIEF::assembly::mips::OPCODE::FSUB_D64) + .value("FSUB_D64_MM", LIEF::assembly::mips::OPCODE::FSUB_D64_MM) + .value("FSUB_PS64", LIEF::assembly::mips::OPCODE::FSUB_PS64) + .value("FSUB_S", LIEF::assembly::mips::OPCODE::FSUB_S) + .value("FSUB_S_MM", LIEF::assembly::mips::OPCODE::FSUB_S_MM) + .value("FSUB_S_MMR6", LIEF::assembly::mips::OPCODE::FSUB_S_MMR6) + .value("FSUB_W", LIEF::assembly::mips::OPCODE::FSUB_W) + .value("FSUEQ_D", LIEF::assembly::mips::OPCODE::FSUEQ_D) + .value("FSUEQ_W", LIEF::assembly::mips::OPCODE::FSUEQ_W) + .value("FSULE_D", LIEF::assembly::mips::OPCODE::FSULE_D) + .value("FSULE_W", LIEF::assembly::mips::OPCODE::FSULE_W) + .value("FSULT_D", LIEF::assembly::mips::OPCODE::FSULT_D) + .value("FSULT_W", LIEF::assembly::mips::OPCODE::FSULT_W) + .value("FSUNE_D", LIEF::assembly::mips::OPCODE::FSUNE_D) + .value("FSUNE_W", LIEF::assembly::mips::OPCODE::FSUNE_W) + .value("FSUN_D", LIEF::assembly::mips::OPCODE::FSUN_D) + .value("FSUN_W", LIEF::assembly::mips::OPCODE::FSUN_W) + .value("FTINT_S_D", LIEF::assembly::mips::OPCODE::FTINT_S_D) + .value("FTINT_S_W", LIEF::assembly::mips::OPCODE::FTINT_S_W) + .value("FTINT_U_D", LIEF::assembly::mips::OPCODE::FTINT_U_D) + .value("FTINT_U_W", LIEF::assembly::mips::OPCODE::FTINT_U_W) + .value("FTQ_H", LIEF::assembly::mips::OPCODE::FTQ_H) + .value("FTQ_W", LIEF::assembly::mips::OPCODE::FTQ_W) + .value("FTRUNC_S_D", LIEF::assembly::mips::OPCODE::FTRUNC_S_D) + .value("FTRUNC_S_W", LIEF::assembly::mips::OPCODE::FTRUNC_S_W) + .value("FTRUNC_U_D", LIEF::assembly::mips::OPCODE::FTRUNC_U_D) + .value("FTRUNC_U_W", LIEF::assembly::mips::OPCODE::FTRUNC_U_W) + .value("GINVI", LIEF::assembly::mips::OPCODE::GINVI) + .value("GINVI_MMR6", LIEF::assembly::mips::OPCODE::GINVI_MMR6) + .value("GINVT", LIEF::assembly::mips::OPCODE::GINVT); + opcodes.value("GINVT_MMR6", LIEF::assembly::mips::OPCODE::GINVT_MMR6) + .value("HADD_S_D", LIEF::assembly::mips::OPCODE::HADD_S_D) + .value("HADD_S_H", LIEF::assembly::mips::OPCODE::HADD_S_H) + .value("HADD_S_W", LIEF::assembly::mips::OPCODE::HADD_S_W) + .value("HADD_U_D", LIEF::assembly::mips::OPCODE::HADD_U_D) + .value("HADD_U_H", LIEF::assembly::mips::OPCODE::HADD_U_H) + .value("HADD_U_W", LIEF::assembly::mips::OPCODE::HADD_U_W) + .value("HSUB_S_D", LIEF::assembly::mips::OPCODE::HSUB_S_D) + .value("HSUB_S_H", LIEF::assembly::mips::OPCODE::HSUB_S_H) + .value("HSUB_S_W", LIEF::assembly::mips::OPCODE::HSUB_S_W) + .value("HSUB_U_D", LIEF::assembly::mips::OPCODE::HSUB_U_D) + .value("HSUB_U_H", LIEF::assembly::mips::OPCODE::HSUB_U_H) + .value("HSUB_U_W", LIEF::assembly::mips::OPCODE::HSUB_U_W) + .value("HYPCALL", LIEF::assembly::mips::OPCODE::HYPCALL) + .value("HYPCALL_MM", LIEF::assembly::mips::OPCODE::HYPCALL_MM) + .value("ILVEV_B", LIEF::assembly::mips::OPCODE::ILVEV_B) + .value("ILVEV_D", LIEF::assembly::mips::OPCODE::ILVEV_D) + .value("ILVEV_H", LIEF::assembly::mips::OPCODE::ILVEV_H) + .value("ILVEV_W", LIEF::assembly::mips::OPCODE::ILVEV_W) + .value("ILVL_B", LIEF::assembly::mips::OPCODE::ILVL_B) + .value("ILVL_D", LIEF::assembly::mips::OPCODE::ILVL_D) + .value("ILVL_H", LIEF::assembly::mips::OPCODE::ILVL_H) + .value("ILVL_W", LIEF::assembly::mips::OPCODE::ILVL_W) + .value("ILVOD_B", LIEF::assembly::mips::OPCODE::ILVOD_B) + .value("ILVOD_D", LIEF::assembly::mips::OPCODE::ILVOD_D) + .value("ILVOD_H", LIEF::assembly::mips::OPCODE::ILVOD_H) + .value("ILVOD_W", LIEF::assembly::mips::OPCODE::ILVOD_W) + .value("ILVR_B", LIEF::assembly::mips::OPCODE::ILVR_B) + .value("ILVR_D", LIEF::assembly::mips::OPCODE::ILVR_D) + .value("ILVR_H", LIEF::assembly::mips::OPCODE::ILVR_H) + .value("ILVR_W", LIEF::assembly::mips::OPCODE::ILVR_W) + .value("INS", LIEF::assembly::mips::OPCODE::INS) + .value("INSERT_B", LIEF::assembly::mips::OPCODE::INSERT_B) + .value("INSERT_D", LIEF::assembly::mips::OPCODE::INSERT_D) + .value("INSERT_H", LIEF::assembly::mips::OPCODE::INSERT_H) + .value("INSERT_W", LIEF::assembly::mips::OPCODE::INSERT_W) + .value("INSV", LIEF::assembly::mips::OPCODE::INSV) + .value("INSVE_B", LIEF::assembly::mips::OPCODE::INSVE_B) + .value("INSVE_D", LIEF::assembly::mips::OPCODE::INSVE_D) + .value("INSVE_H", LIEF::assembly::mips::OPCODE::INSVE_H) + .value("INSVE_W", LIEF::assembly::mips::OPCODE::INSVE_W) + .value("INSV_MM", LIEF::assembly::mips::OPCODE::INSV_MM) + .value("INS_MM", LIEF::assembly::mips::OPCODE::INS_MM) + .value("INS_MMR6", LIEF::assembly::mips::OPCODE::INS_MMR6) + .value("J", LIEF::assembly::mips::OPCODE::J) + .value("JAL", LIEF::assembly::mips::OPCODE::JAL) + .value("JALR", LIEF::assembly::mips::OPCODE::JALR) + .value("JALR16_MM", LIEF::assembly::mips::OPCODE::JALR16_MM) + .value("JALR64", LIEF::assembly::mips::OPCODE::JALR64) + .value("JALRC16_MMR6", LIEF::assembly::mips::OPCODE::JALRC16_MMR6) + .value("JALRC_HB_MMR6", LIEF::assembly::mips::OPCODE::JALRC_HB_MMR6) + .value("JALRC_MMR6", LIEF::assembly::mips::OPCODE::JALRC_MMR6) + .value("JALRS16_MM", LIEF::assembly::mips::OPCODE::JALRS16_MM) + .value("JALRS_MM", LIEF::assembly::mips::OPCODE::JALRS_MM) + .value("JALR_HB", LIEF::assembly::mips::OPCODE::JALR_HB) + .value("JALR_HB64", LIEF::assembly::mips::OPCODE::JALR_HB64) + .value("JALR_MM", LIEF::assembly::mips::OPCODE::JALR_MM) + .value("JALS_MM", LIEF::assembly::mips::OPCODE::JALS_MM) + .value("JALX", LIEF::assembly::mips::OPCODE::JALX) + .value("JALX_MM", LIEF::assembly::mips::OPCODE::JALX_MM) + .value("JAL_MM", LIEF::assembly::mips::OPCODE::JAL_MM) + .value("JIALC", LIEF::assembly::mips::OPCODE::JIALC) + .value("JIALC64", LIEF::assembly::mips::OPCODE::JIALC64) + .value("JIALC_MMR6", LIEF::assembly::mips::OPCODE::JIALC_MMR6) + .value("JIC", LIEF::assembly::mips::OPCODE::JIC) + .value("JIC64", LIEF::assembly::mips::OPCODE::JIC64) + .value("JIC_MMR6", LIEF::assembly::mips::OPCODE::JIC_MMR6) + .value("JR", LIEF::assembly::mips::OPCODE::JR) + .value("JR16_MM", LIEF::assembly::mips::OPCODE::JR16_MM) + .value("JR64", LIEF::assembly::mips::OPCODE::JR64) + .value("JRADDIUSP", LIEF::assembly::mips::OPCODE::JRADDIUSP) + .value("JRC16_MM", LIEF::assembly::mips::OPCODE::JRC16_MM) + .value("JRC16_MMR6", LIEF::assembly::mips::OPCODE::JRC16_MMR6) + .value("JRCADDIUSP_MMR6", LIEF::assembly::mips::OPCODE::JRCADDIUSP_MMR6) + .value("JR_HB", LIEF::assembly::mips::OPCODE::JR_HB) + .value("JR_HB64", LIEF::assembly::mips::OPCODE::JR_HB64) + .value("JR_HB64_R6", LIEF::assembly::mips::OPCODE::JR_HB64_R6) + .value("JR_HB_R6", LIEF::assembly::mips::OPCODE::JR_HB_R6) + .value("JR_MM", LIEF::assembly::mips::OPCODE::JR_MM) + .value("J_MM", LIEF::assembly::mips::OPCODE::J_MM) + .value("Jal16", LIEF::assembly::mips::OPCODE::Jal16) + .value("JalB16", LIEF::assembly::mips::OPCODE::JalB16) + .value("JrRa16", LIEF::assembly::mips::OPCODE::JrRa16) + .value("JrcRa16", LIEF::assembly::mips::OPCODE::JrcRa16) + .value("JrcRx16", LIEF::assembly::mips::OPCODE::JrcRx16) + .value("JumpLinkReg16", LIEF::assembly::mips::OPCODE::JumpLinkReg16) + .value("LB", LIEF::assembly::mips::OPCODE::LB) + .value("LB64", LIEF::assembly::mips::OPCODE::LB64) + .value("LBE", LIEF::assembly::mips::OPCODE::LBE) + .value("LBE_MM", LIEF::assembly::mips::OPCODE::LBE_MM) + .value("LBU16_MM", LIEF::assembly::mips::OPCODE::LBU16_MM) + .value("LBUX", LIEF::assembly::mips::OPCODE::LBUX) + .value("LBUX_MM", LIEF::assembly::mips::OPCODE::LBUX_MM) + .value("LBU_MMR6", LIEF::assembly::mips::OPCODE::LBU_MMR6) + .value("LB_MM", LIEF::assembly::mips::OPCODE::LB_MM) + .value("LB_MMR6", LIEF::assembly::mips::OPCODE::LB_MMR6) + .value("LBu", LIEF::assembly::mips::OPCODE::LBu) + .value("LBu64", LIEF::assembly::mips::OPCODE::LBu64) + .value("LBuE", LIEF::assembly::mips::OPCODE::LBuE) + .value("LBuE_MM", LIEF::assembly::mips::OPCODE::LBuE_MM) + .value("LBu_MM", LIEF::assembly::mips::OPCODE::LBu_MM) + .value("LD", LIEF::assembly::mips::OPCODE::LD) + .value("LDC1", LIEF::assembly::mips::OPCODE::LDC1) + .value("LDC164", LIEF::assembly::mips::OPCODE::LDC164) + .value("LDC1_D64_MMR6", LIEF::assembly::mips::OPCODE::LDC1_D64_MMR6) + .value("LDC1_MM_D32", LIEF::assembly::mips::OPCODE::LDC1_MM_D32) + .value("LDC1_MM_D64", LIEF::assembly::mips::OPCODE::LDC1_MM_D64) + .value("LDC2", LIEF::assembly::mips::OPCODE::LDC2) + .value("LDC2_MMR6", LIEF::assembly::mips::OPCODE::LDC2_MMR6) + .value("LDC2_R6", LIEF::assembly::mips::OPCODE::LDC2_R6) + .value("LDC3", LIEF::assembly::mips::OPCODE::LDC3) + .value("LDI_B", LIEF::assembly::mips::OPCODE::LDI_B) + .value("LDI_D", LIEF::assembly::mips::OPCODE::LDI_D) + .value("LDI_H", LIEF::assembly::mips::OPCODE::LDI_H) + .value("LDI_W", LIEF::assembly::mips::OPCODE::LDI_W) + .value("LDL", LIEF::assembly::mips::OPCODE::LDL) + .value("LDPC", LIEF::assembly::mips::OPCODE::LDPC) + .value("LDR", LIEF::assembly::mips::OPCODE::LDR) + .value("LDXC1", LIEF::assembly::mips::OPCODE::LDXC1) + .value("LDXC164", LIEF::assembly::mips::OPCODE::LDXC164) + .value("LD_B", LIEF::assembly::mips::OPCODE::LD_B) + .value("LD_D", LIEF::assembly::mips::OPCODE::LD_D) + .value("LD_H", LIEF::assembly::mips::OPCODE::LD_H) + .value("LD_W", LIEF::assembly::mips::OPCODE::LD_W) + .value("LEA_ADDiu", LIEF::assembly::mips::OPCODE::LEA_ADDiu) + .value("LEA_ADDiu64", LIEF::assembly::mips::OPCODE::LEA_ADDiu64) + .value("LEA_ADDiu_MM", LIEF::assembly::mips::OPCODE::LEA_ADDiu_MM) + .value("LH", LIEF::assembly::mips::OPCODE::LH) + .value("LH64", LIEF::assembly::mips::OPCODE::LH64) + .value("LHE", LIEF::assembly::mips::OPCODE::LHE) + .value("LHE_MM", LIEF::assembly::mips::OPCODE::LHE_MM) + .value("LHU16_MM", LIEF::assembly::mips::OPCODE::LHU16_MM) + .value("LHX", LIEF::assembly::mips::OPCODE::LHX) + .value("LHX_MM", LIEF::assembly::mips::OPCODE::LHX_MM) + .value("LH_MM", LIEF::assembly::mips::OPCODE::LH_MM) + .value("LHu", LIEF::assembly::mips::OPCODE::LHu) + .value("LHu64", LIEF::assembly::mips::OPCODE::LHu64) + .value("LHuE", LIEF::assembly::mips::OPCODE::LHuE) + .value("LHuE_MM", LIEF::assembly::mips::OPCODE::LHuE_MM) + .value("LHu_MM", LIEF::assembly::mips::OPCODE::LHu_MM) + .value("LI16_MM", LIEF::assembly::mips::OPCODE::LI16_MM) + .value("LI16_MMR6", LIEF::assembly::mips::OPCODE::LI16_MMR6) + .value("LL", LIEF::assembly::mips::OPCODE::LL) + .value("LL64", LIEF::assembly::mips::OPCODE::LL64) + .value("LL64_R6", LIEF::assembly::mips::OPCODE::LL64_R6) + .value("LLD", LIEF::assembly::mips::OPCODE::LLD) + .value("LLD_R6", LIEF::assembly::mips::OPCODE::LLD_R6) + .value("LLE", LIEF::assembly::mips::OPCODE::LLE) + .value("LLE_MM", LIEF::assembly::mips::OPCODE::LLE_MM) + .value("LL_MM", LIEF::assembly::mips::OPCODE::LL_MM) + .value("LL_MMR6", LIEF::assembly::mips::OPCODE::LL_MMR6) + .value("LL_R6", LIEF::assembly::mips::OPCODE::LL_R6) + .value("LSA", LIEF::assembly::mips::OPCODE::LSA) + .value("LSA_MMR6", LIEF::assembly::mips::OPCODE::LSA_MMR6) + .value("LSA_R6", LIEF::assembly::mips::OPCODE::LSA_R6) + .value("LUI_MMR6", LIEF::assembly::mips::OPCODE::LUI_MMR6) + .value("LUXC1", LIEF::assembly::mips::OPCODE::LUXC1) + .value("LUXC164", LIEF::assembly::mips::OPCODE::LUXC164) + .value("LUXC1_MM", LIEF::assembly::mips::OPCODE::LUXC1_MM) + .value("LUi", LIEF::assembly::mips::OPCODE::LUi) + .value("LUi64", LIEF::assembly::mips::OPCODE::LUi64) + .value("LUi_MM", LIEF::assembly::mips::OPCODE::LUi_MM) + .value("LW", LIEF::assembly::mips::OPCODE::LW) + .value("LW16_MM", LIEF::assembly::mips::OPCODE::LW16_MM) + .value("LW64", LIEF::assembly::mips::OPCODE::LW64) + .value("LWC1", LIEF::assembly::mips::OPCODE::LWC1) + .value("LWC1_MM", LIEF::assembly::mips::OPCODE::LWC1_MM) + .value("LWC2", LIEF::assembly::mips::OPCODE::LWC2) + .value("LWC2_MMR6", LIEF::assembly::mips::OPCODE::LWC2_MMR6) + .value("LWC2_R6", LIEF::assembly::mips::OPCODE::LWC2_R6) + .value("LWC3", LIEF::assembly::mips::OPCODE::LWC3) + .value("LWDSP", LIEF::assembly::mips::OPCODE::LWDSP) + .value("LWDSP_MM", LIEF::assembly::mips::OPCODE::LWDSP_MM) + .value("LWE", LIEF::assembly::mips::OPCODE::LWE) + .value("LWE_MM", LIEF::assembly::mips::OPCODE::LWE_MM) + .value("LWGP_MM", LIEF::assembly::mips::OPCODE::LWGP_MM) + .value("LWL", LIEF::assembly::mips::OPCODE::LWL) + .value("LWL64", LIEF::assembly::mips::OPCODE::LWL64) + .value("LWLE", LIEF::assembly::mips::OPCODE::LWLE) + .value("LWLE_MM", LIEF::assembly::mips::OPCODE::LWLE_MM) + .value("LWL_MM", LIEF::assembly::mips::OPCODE::LWL_MM) + .value("LWM16_MM", LIEF::assembly::mips::OPCODE::LWM16_MM) + .value("LWM16_MMR6", LIEF::assembly::mips::OPCODE::LWM16_MMR6) + .value("LWM32_MM", LIEF::assembly::mips::OPCODE::LWM32_MM) + .value("LWPC", LIEF::assembly::mips::OPCODE::LWPC) + .value("LWPC_MMR6", LIEF::assembly::mips::OPCODE::LWPC_MMR6) + .value("LWP_MM", LIEF::assembly::mips::OPCODE::LWP_MM) + .value("LWR", LIEF::assembly::mips::OPCODE::LWR) + .value("LWR64", LIEF::assembly::mips::OPCODE::LWR64) + .value("LWRE", LIEF::assembly::mips::OPCODE::LWRE) + .value("LWRE_MM", LIEF::assembly::mips::OPCODE::LWRE_MM) + .value("LWR_MM", LIEF::assembly::mips::OPCODE::LWR_MM) + .value("LWSP_MM", LIEF::assembly::mips::OPCODE::LWSP_MM) + .value("LWUPC", LIEF::assembly::mips::OPCODE::LWUPC) + .value("LWU_MM", LIEF::assembly::mips::OPCODE::LWU_MM) + .value("LWX", LIEF::assembly::mips::OPCODE::LWX) + .value("LWXC1", LIEF::assembly::mips::OPCODE::LWXC1) + .value("LWXC1_MM", LIEF::assembly::mips::OPCODE::LWXC1_MM) + .value("LWXS_MM", LIEF::assembly::mips::OPCODE::LWXS_MM) + .value("LWX_MM", LIEF::assembly::mips::OPCODE::LWX_MM) + .value("LW_MM", LIEF::assembly::mips::OPCODE::LW_MM) + .value("LW_MMR6", LIEF::assembly::mips::OPCODE::LW_MMR6) + .value("LWu", LIEF::assembly::mips::OPCODE::LWu) + .value("LbRxRyOffMemX16", LIEF::assembly::mips::OPCODE::LbRxRyOffMemX16) + .value("LbuRxRyOffMemX16", LIEF::assembly::mips::OPCODE::LbuRxRyOffMemX16) + .value("LhRxRyOffMemX16", LIEF::assembly::mips::OPCODE::LhRxRyOffMemX16) + .value("LhuRxRyOffMemX16", LIEF::assembly::mips::OPCODE::LhuRxRyOffMemX16) + .value("LiRxImm16", LIEF::assembly::mips::OPCODE::LiRxImm16) + .value("LiRxImmAlignX16", LIEF::assembly::mips::OPCODE::LiRxImmAlignX16) + .value("LiRxImmX16", LIEF::assembly::mips::OPCODE::LiRxImmX16) + .value("LwRxPcTcp16", LIEF::assembly::mips::OPCODE::LwRxPcTcp16) + .value("LwRxPcTcpX16", LIEF::assembly::mips::OPCODE::LwRxPcTcpX16) + .value("LwRxRyOffMemX16", LIEF::assembly::mips::OPCODE::LwRxRyOffMemX16) + .value("LwRxSpImmX16", LIEF::assembly::mips::OPCODE::LwRxSpImmX16) + .value("MADD", LIEF::assembly::mips::OPCODE::MADD) + .value("MADDF_D", LIEF::assembly::mips::OPCODE::MADDF_D) + .value("MADDF_D_MMR6", LIEF::assembly::mips::OPCODE::MADDF_D_MMR6) + .value("MADDF_S", LIEF::assembly::mips::OPCODE::MADDF_S) + .value("MADDF_S_MMR6", LIEF::assembly::mips::OPCODE::MADDF_S_MMR6) + .value("MADDR_Q_H", LIEF::assembly::mips::OPCODE::MADDR_Q_H) + .value("MADDR_Q_W", LIEF::assembly::mips::OPCODE::MADDR_Q_W) + .value("MADDU", LIEF::assembly::mips::OPCODE::MADDU) + .value("MADDU_DSP", LIEF::assembly::mips::OPCODE::MADDU_DSP) + .value("MADDU_DSP_MM", LIEF::assembly::mips::OPCODE::MADDU_DSP_MM) + .value("MADDU_MM", LIEF::assembly::mips::OPCODE::MADDU_MM) + .value("MADDV_B", LIEF::assembly::mips::OPCODE::MADDV_B) + .value("MADDV_D", LIEF::assembly::mips::OPCODE::MADDV_D) + .value("MADDV_H", LIEF::assembly::mips::OPCODE::MADDV_H) + .value("MADDV_W", LIEF::assembly::mips::OPCODE::MADDV_W) + .value("MADD_D32", LIEF::assembly::mips::OPCODE::MADD_D32) + .value("MADD_D32_MM", LIEF::assembly::mips::OPCODE::MADD_D32_MM) + .value("MADD_D64", LIEF::assembly::mips::OPCODE::MADD_D64) + .value("MADD_DSP", LIEF::assembly::mips::OPCODE::MADD_DSP) + .value("MADD_DSP_MM", LIEF::assembly::mips::OPCODE::MADD_DSP_MM) + .value("MADD_MM", LIEF::assembly::mips::OPCODE::MADD_MM) + .value("MADD_Q_H", LIEF::assembly::mips::OPCODE::MADD_Q_H) + .value("MADD_Q_W", LIEF::assembly::mips::OPCODE::MADD_Q_W) + .value("MADD_S", LIEF::assembly::mips::OPCODE::MADD_S) + .value("MADD_S_MM", LIEF::assembly::mips::OPCODE::MADD_S_MM) + .value("MAQ_SA_W_PHL", LIEF::assembly::mips::OPCODE::MAQ_SA_W_PHL) + .value("MAQ_SA_W_PHL_MM", LIEF::assembly::mips::OPCODE::MAQ_SA_W_PHL_MM) + .value("MAQ_SA_W_PHR", LIEF::assembly::mips::OPCODE::MAQ_SA_W_PHR) + .value("MAQ_SA_W_PHR_MM", LIEF::assembly::mips::OPCODE::MAQ_SA_W_PHR_MM) + .value("MAQ_S_W_PHL", LIEF::assembly::mips::OPCODE::MAQ_S_W_PHL) + .value("MAQ_S_W_PHL_MM", LIEF::assembly::mips::OPCODE::MAQ_S_W_PHL_MM) + .value("MAQ_S_W_PHR", LIEF::assembly::mips::OPCODE::MAQ_S_W_PHR) + .value("MAQ_S_W_PHR_MM", LIEF::assembly::mips::OPCODE::MAQ_S_W_PHR_MM) + .value("MAXA_D", LIEF::assembly::mips::OPCODE::MAXA_D) + .value("MAXA_D_MMR6", LIEF::assembly::mips::OPCODE::MAXA_D_MMR6) + .value("MAXA_S", LIEF::assembly::mips::OPCODE::MAXA_S) + .value("MAXA_S_MMR6", LIEF::assembly::mips::OPCODE::MAXA_S_MMR6) + .value("MAXI_S_B", LIEF::assembly::mips::OPCODE::MAXI_S_B) + .value("MAXI_S_D", LIEF::assembly::mips::OPCODE::MAXI_S_D) + .value("MAXI_S_H", LIEF::assembly::mips::OPCODE::MAXI_S_H) + .value("MAXI_S_W", LIEF::assembly::mips::OPCODE::MAXI_S_W) + .value("MAXI_U_B", LIEF::assembly::mips::OPCODE::MAXI_U_B) + .value("MAXI_U_D", LIEF::assembly::mips::OPCODE::MAXI_U_D) + .value("MAXI_U_H", LIEF::assembly::mips::OPCODE::MAXI_U_H) + .value("MAXI_U_W", LIEF::assembly::mips::OPCODE::MAXI_U_W) + .value("MAX_A_B", LIEF::assembly::mips::OPCODE::MAX_A_B) + .value("MAX_A_D", LIEF::assembly::mips::OPCODE::MAX_A_D) + .value("MAX_A_H", LIEF::assembly::mips::OPCODE::MAX_A_H) + .value("MAX_A_W", LIEF::assembly::mips::OPCODE::MAX_A_W) + .value("MAX_D", LIEF::assembly::mips::OPCODE::MAX_D) + .value("MAX_D_MMR6", LIEF::assembly::mips::OPCODE::MAX_D_MMR6) + .value("MAX_S", LIEF::assembly::mips::OPCODE::MAX_S) + .value("MAX_S_B", LIEF::assembly::mips::OPCODE::MAX_S_B) + .value("MAX_S_D", LIEF::assembly::mips::OPCODE::MAX_S_D) + .value("MAX_S_H", LIEF::assembly::mips::OPCODE::MAX_S_H) + .value("MAX_S_MMR6", LIEF::assembly::mips::OPCODE::MAX_S_MMR6) + .value("MAX_S_W", LIEF::assembly::mips::OPCODE::MAX_S_W) + .value("MAX_U_B", LIEF::assembly::mips::OPCODE::MAX_U_B) + .value("MAX_U_D", LIEF::assembly::mips::OPCODE::MAX_U_D) + .value("MAX_U_H", LIEF::assembly::mips::OPCODE::MAX_U_H) + .value("MAX_U_W", LIEF::assembly::mips::OPCODE::MAX_U_W) + .value("MFC0", LIEF::assembly::mips::OPCODE::MFC0) + .value("MFC0_MMR6", LIEF::assembly::mips::OPCODE::MFC0_MMR6) + .value("MFC1", LIEF::assembly::mips::OPCODE::MFC1) + .value("MFC1_D64", LIEF::assembly::mips::OPCODE::MFC1_D64) + .value("MFC1_MM", LIEF::assembly::mips::OPCODE::MFC1_MM) + .value("MFC1_MMR6", LIEF::assembly::mips::OPCODE::MFC1_MMR6) + .value("MFC2", LIEF::assembly::mips::OPCODE::MFC2) + .value("MFC2_MMR6", LIEF::assembly::mips::OPCODE::MFC2_MMR6) + .value("MFGC0", LIEF::assembly::mips::OPCODE::MFGC0) + .value("MFGC0_MM", LIEF::assembly::mips::OPCODE::MFGC0_MM) + .value("MFHC0_MMR6", LIEF::assembly::mips::OPCODE::MFHC0_MMR6) + .value("MFHC1_D32", LIEF::assembly::mips::OPCODE::MFHC1_D32) + .value("MFHC1_D32_MM", LIEF::assembly::mips::OPCODE::MFHC1_D32_MM) + .value("MFHC1_D64", LIEF::assembly::mips::OPCODE::MFHC1_D64) + .value("MFHC1_D64_MM", LIEF::assembly::mips::OPCODE::MFHC1_D64_MM) + .value("MFHC2_MMR6", LIEF::assembly::mips::OPCODE::MFHC2_MMR6) + .value("MFHGC0", LIEF::assembly::mips::OPCODE::MFHGC0) + .value("MFHGC0_MM", LIEF::assembly::mips::OPCODE::MFHGC0_MM) + .value("MFHI", LIEF::assembly::mips::OPCODE::MFHI) + .value("MFHI16_MM", LIEF::assembly::mips::OPCODE::MFHI16_MM) + .value("MFHI64", LIEF::assembly::mips::OPCODE::MFHI64) + .value("MFHI_DSP", LIEF::assembly::mips::OPCODE::MFHI_DSP) + .value("MFHI_DSP_MM", LIEF::assembly::mips::OPCODE::MFHI_DSP_MM) + .value("MFHI_MM", LIEF::assembly::mips::OPCODE::MFHI_MM) + .value("MFLO", LIEF::assembly::mips::OPCODE::MFLO); + opcodes.value("MFLO16_MM", LIEF::assembly::mips::OPCODE::MFLO16_MM) + .value("MFLO64", LIEF::assembly::mips::OPCODE::MFLO64) + .value("MFLO_DSP", LIEF::assembly::mips::OPCODE::MFLO_DSP) + .value("MFLO_DSP_MM", LIEF::assembly::mips::OPCODE::MFLO_DSP_MM) + .value("MFLO_MM", LIEF::assembly::mips::OPCODE::MFLO_MM) + .value("MFTR", LIEF::assembly::mips::OPCODE::MFTR) + .value("MINA_D", LIEF::assembly::mips::OPCODE::MINA_D) + .value("MINA_D_MMR6", LIEF::assembly::mips::OPCODE::MINA_D_MMR6) + .value("MINA_S", LIEF::assembly::mips::OPCODE::MINA_S) + .value("MINA_S_MMR6", LIEF::assembly::mips::OPCODE::MINA_S_MMR6) + .value("MINI_S_B", LIEF::assembly::mips::OPCODE::MINI_S_B) + .value("MINI_S_D", LIEF::assembly::mips::OPCODE::MINI_S_D) + .value("MINI_S_H", LIEF::assembly::mips::OPCODE::MINI_S_H) + .value("MINI_S_W", LIEF::assembly::mips::OPCODE::MINI_S_W) + .value("MINI_U_B", LIEF::assembly::mips::OPCODE::MINI_U_B) + .value("MINI_U_D", LIEF::assembly::mips::OPCODE::MINI_U_D) + .value("MINI_U_H", LIEF::assembly::mips::OPCODE::MINI_U_H) + .value("MINI_U_W", LIEF::assembly::mips::OPCODE::MINI_U_W) + .value("MIN_A_B", LIEF::assembly::mips::OPCODE::MIN_A_B) + .value("MIN_A_D", LIEF::assembly::mips::OPCODE::MIN_A_D) + .value("MIN_A_H", LIEF::assembly::mips::OPCODE::MIN_A_H) + .value("MIN_A_W", LIEF::assembly::mips::OPCODE::MIN_A_W) + .value("MIN_D", LIEF::assembly::mips::OPCODE::MIN_D) + .value("MIN_D_MMR6", LIEF::assembly::mips::OPCODE::MIN_D_MMR6) + .value("MIN_S", LIEF::assembly::mips::OPCODE::MIN_S) + .value("MIN_S_B", LIEF::assembly::mips::OPCODE::MIN_S_B) + .value("MIN_S_D", LIEF::assembly::mips::OPCODE::MIN_S_D) + .value("MIN_S_H", LIEF::assembly::mips::OPCODE::MIN_S_H) + .value("MIN_S_MMR6", LIEF::assembly::mips::OPCODE::MIN_S_MMR6) + .value("MIN_S_W", LIEF::assembly::mips::OPCODE::MIN_S_W) + .value("MIN_U_B", LIEF::assembly::mips::OPCODE::MIN_U_B) + .value("MIN_U_D", LIEF::assembly::mips::OPCODE::MIN_U_D) + .value("MIN_U_H", LIEF::assembly::mips::OPCODE::MIN_U_H) + .value("MIN_U_W", LIEF::assembly::mips::OPCODE::MIN_U_W) + .value("MOD", LIEF::assembly::mips::OPCODE::MOD) + .value("MODSUB", LIEF::assembly::mips::OPCODE::MODSUB) + .value("MODSUB_MM", LIEF::assembly::mips::OPCODE::MODSUB_MM) + .value("MODU", LIEF::assembly::mips::OPCODE::MODU) + .value("MODU_MMR6", LIEF::assembly::mips::OPCODE::MODU_MMR6) + .value("MOD_MMR6", LIEF::assembly::mips::OPCODE::MOD_MMR6) + .value("MOD_S_B", LIEF::assembly::mips::OPCODE::MOD_S_B) + .value("MOD_S_D", LIEF::assembly::mips::OPCODE::MOD_S_D) + .value("MOD_S_H", LIEF::assembly::mips::OPCODE::MOD_S_H) + .value("MOD_S_W", LIEF::assembly::mips::OPCODE::MOD_S_W) + .value("MOD_U_B", LIEF::assembly::mips::OPCODE::MOD_U_B) + .value("MOD_U_D", LIEF::assembly::mips::OPCODE::MOD_U_D) + .value("MOD_U_H", LIEF::assembly::mips::OPCODE::MOD_U_H) + .value("MOD_U_W", LIEF::assembly::mips::OPCODE::MOD_U_W) + .value("MOVE16_MM", LIEF::assembly::mips::OPCODE::MOVE16_MM) + .value("MOVE16_MMR6", LIEF::assembly::mips::OPCODE::MOVE16_MMR6) + .value("MOVEP_MM", LIEF::assembly::mips::OPCODE::MOVEP_MM) + .value("MOVEP_MMR6", LIEF::assembly::mips::OPCODE::MOVEP_MMR6) + .value("MOVE_V", LIEF::assembly::mips::OPCODE::MOVE_V) + .value("MOVF_D32", LIEF::assembly::mips::OPCODE::MOVF_D32) + .value("MOVF_D32_MM", LIEF::assembly::mips::OPCODE::MOVF_D32_MM) + .value("MOVF_D64", LIEF::assembly::mips::OPCODE::MOVF_D64) + .value("MOVF_I", LIEF::assembly::mips::OPCODE::MOVF_I) + .value("MOVF_I64", LIEF::assembly::mips::OPCODE::MOVF_I64) + .value("MOVF_I_MM", LIEF::assembly::mips::OPCODE::MOVF_I_MM) + .value("MOVF_S", LIEF::assembly::mips::OPCODE::MOVF_S) + .value("MOVF_S_MM", LIEF::assembly::mips::OPCODE::MOVF_S_MM) + .value("MOVN_I64_D64", LIEF::assembly::mips::OPCODE::MOVN_I64_D64) + .value("MOVN_I64_I", LIEF::assembly::mips::OPCODE::MOVN_I64_I) + .value("MOVN_I64_I64", LIEF::assembly::mips::OPCODE::MOVN_I64_I64) + .value("MOVN_I64_S", LIEF::assembly::mips::OPCODE::MOVN_I64_S) + .value("MOVN_I_D32", LIEF::assembly::mips::OPCODE::MOVN_I_D32) + .value("MOVN_I_D32_MM", LIEF::assembly::mips::OPCODE::MOVN_I_D32_MM) + .value("MOVN_I_D64", LIEF::assembly::mips::OPCODE::MOVN_I_D64) + .value("MOVN_I_I", LIEF::assembly::mips::OPCODE::MOVN_I_I) + .value("MOVN_I_I64", LIEF::assembly::mips::OPCODE::MOVN_I_I64) + .value("MOVN_I_MM", LIEF::assembly::mips::OPCODE::MOVN_I_MM) + .value("MOVN_I_S", LIEF::assembly::mips::OPCODE::MOVN_I_S) + .value("MOVN_I_S_MM", LIEF::assembly::mips::OPCODE::MOVN_I_S_MM) + .value("MOVT_D32", LIEF::assembly::mips::OPCODE::MOVT_D32) + .value("MOVT_D32_MM", LIEF::assembly::mips::OPCODE::MOVT_D32_MM) + .value("MOVT_D64", LIEF::assembly::mips::OPCODE::MOVT_D64) + .value("MOVT_I", LIEF::assembly::mips::OPCODE::MOVT_I) + .value("MOVT_I64", LIEF::assembly::mips::OPCODE::MOVT_I64) + .value("MOVT_I_MM", LIEF::assembly::mips::OPCODE::MOVT_I_MM) + .value("MOVT_S", LIEF::assembly::mips::OPCODE::MOVT_S) + .value("MOVT_S_MM", LIEF::assembly::mips::OPCODE::MOVT_S_MM) + .value("MOVZ_I64_D64", LIEF::assembly::mips::OPCODE::MOVZ_I64_D64) + .value("MOVZ_I64_I", LIEF::assembly::mips::OPCODE::MOVZ_I64_I) + .value("MOVZ_I64_I64", LIEF::assembly::mips::OPCODE::MOVZ_I64_I64) + .value("MOVZ_I64_S", LIEF::assembly::mips::OPCODE::MOVZ_I64_S) + .value("MOVZ_I_D32", LIEF::assembly::mips::OPCODE::MOVZ_I_D32) + .value("MOVZ_I_D32_MM", LIEF::assembly::mips::OPCODE::MOVZ_I_D32_MM) + .value("MOVZ_I_D64", LIEF::assembly::mips::OPCODE::MOVZ_I_D64) + .value("MOVZ_I_I", LIEF::assembly::mips::OPCODE::MOVZ_I_I) + .value("MOVZ_I_I64", LIEF::assembly::mips::OPCODE::MOVZ_I_I64) + .value("MOVZ_I_MM", LIEF::assembly::mips::OPCODE::MOVZ_I_MM) + .value("MOVZ_I_S", LIEF::assembly::mips::OPCODE::MOVZ_I_S) + .value("MOVZ_I_S_MM", LIEF::assembly::mips::OPCODE::MOVZ_I_S_MM) + .value("MSUB", LIEF::assembly::mips::OPCODE::MSUB) + .value("MSUBF_D", LIEF::assembly::mips::OPCODE::MSUBF_D) + .value("MSUBF_D_MMR6", LIEF::assembly::mips::OPCODE::MSUBF_D_MMR6) + .value("MSUBF_S", LIEF::assembly::mips::OPCODE::MSUBF_S) + .value("MSUBF_S_MMR6", LIEF::assembly::mips::OPCODE::MSUBF_S_MMR6) + .value("MSUBR_Q_H", LIEF::assembly::mips::OPCODE::MSUBR_Q_H) + .value("MSUBR_Q_W", LIEF::assembly::mips::OPCODE::MSUBR_Q_W) + .value("MSUBU", LIEF::assembly::mips::OPCODE::MSUBU) + .value("MSUBU_DSP", LIEF::assembly::mips::OPCODE::MSUBU_DSP) + .value("MSUBU_DSP_MM", LIEF::assembly::mips::OPCODE::MSUBU_DSP_MM) + .value("MSUBU_MM", LIEF::assembly::mips::OPCODE::MSUBU_MM) + .value("MSUBV_B", LIEF::assembly::mips::OPCODE::MSUBV_B) + .value("MSUBV_D", LIEF::assembly::mips::OPCODE::MSUBV_D) + .value("MSUBV_H", LIEF::assembly::mips::OPCODE::MSUBV_H) + .value("MSUBV_W", LIEF::assembly::mips::OPCODE::MSUBV_W) + .value("MSUB_D32", LIEF::assembly::mips::OPCODE::MSUB_D32) + .value("MSUB_D32_MM", LIEF::assembly::mips::OPCODE::MSUB_D32_MM) + .value("MSUB_D64", LIEF::assembly::mips::OPCODE::MSUB_D64) + .value("MSUB_DSP", LIEF::assembly::mips::OPCODE::MSUB_DSP) + .value("MSUB_DSP_MM", LIEF::assembly::mips::OPCODE::MSUB_DSP_MM) + .value("MSUB_MM", LIEF::assembly::mips::OPCODE::MSUB_MM) + .value("MSUB_Q_H", LIEF::assembly::mips::OPCODE::MSUB_Q_H) + .value("MSUB_Q_W", LIEF::assembly::mips::OPCODE::MSUB_Q_W) + .value("MSUB_S", LIEF::assembly::mips::OPCODE::MSUB_S) + .value("MSUB_S_MM", LIEF::assembly::mips::OPCODE::MSUB_S_MM) + .value("MTC0", LIEF::assembly::mips::OPCODE::MTC0) + .value("MTC0_MMR6", LIEF::assembly::mips::OPCODE::MTC0_MMR6) + .value("MTC1", LIEF::assembly::mips::OPCODE::MTC1) + .value("MTC1_D64", LIEF::assembly::mips::OPCODE::MTC1_D64) + .value("MTC1_D64_MM", LIEF::assembly::mips::OPCODE::MTC1_D64_MM) + .value("MTC1_MM", LIEF::assembly::mips::OPCODE::MTC1_MM) + .value("MTC1_MMR6", LIEF::assembly::mips::OPCODE::MTC1_MMR6) + .value("MTC2", LIEF::assembly::mips::OPCODE::MTC2) + .value("MTC2_MMR6", LIEF::assembly::mips::OPCODE::MTC2_MMR6) + .value("MTGC0", LIEF::assembly::mips::OPCODE::MTGC0) + .value("MTGC0_MM", LIEF::assembly::mips::OPCODE::MTGC0_MM) + .value("MTHC0_MMR6", LIEF::assembly::mips::OPCODE::MTHC0_MMR6) + .value("MTHC1_D32", LIEF::assembly::mips::OPCODE::MTHC1_D32) + .value("MTHC1_D32_MM", LIEF::assembly::mips::OPCODE::MTHC1_D32_MM) + .value("MTHC1_D64", LIEF::assembly::mips::OPCODE::MTHC1_D64) + .value("MTHC1_D64_MM", LIEF::assembly::mips::OPCODE::MTHC1_D64_MM) + .value("MTHC2_MMR6", LIEF::assembly::mips::OPCODE::MTHC2_MMR6) + .value("MTHGC0", LIEF::assembly::mips::OPCODE::MTHGC0) + .value("MTHGC0_MM", LIEF::assembly::mips::OPCODE::MTHGC0_MM) + .value("MTHI", LIEF::assembly::mips::OPCODE::MTHI) + .value("MTHI64", LIEF::assembly::mips::OPCODE::MTHI64) + .value("MTHI_DSP", LIEF::assembly::mips::OPCODE::MTHI_DSP) + .value("MTHI_DSP_MM", LIEF::assembly::mips::OPCODE::MTHI_DSP_MM) + .value("MTHI_MM", LIEF::assembly::mips::OPCODE::MTHI_MM) + .value("MTHLIP", LIEF::assembly::mips::OPCODE::MTHLIP) + .value("MTHLIP_MM", LIEF::assembly::mips::OPCODE::MTHLIP_MM) + .value("MTLO", LIEF::assembly::mips::OPCODE::MTLO) + .value("MTLO64", LIEF::assembly::mips::OPCODE::MTLO64) + .value("MTLO_DSP", LIEF::assembly::mips::OPCODE::MTLO_DSP) + .value("MTLO_DSP_MM", LIEF::assembly::mips::OPCODE::MTLO_DSP_MM) + .value("MTLO_MM", LIEF::assembly::mips::OPCODE::MTLO_MM) + .value("MTM0", LIEF::assembly::mips::OPCODE::MTM0) + .value("MTM1", LIEF::assembly::mips::OPCODE::MTM1) + .value("MTM2", LIEF::assembly::mips::OPCODE::MTM2) + .value("MTP0", LIEF::assembly::mips::OPCODE::MTP0) + .value("MTP1", LIEF::assembly::mips::OPCODE::MTP1) + .value("MTP2", LIEF::assembly::mips::OPCODE::MTP2) + .value("MTTR", LIEF::assembly::mips::OPCODE::MTTR) + .value("MUH", LIEF::assembly::mips::OPCODE::MUH) + .value("MUHU", LIEF::assembly::mips::OPCODE::MUHU) + .value("MUHU_MMR6", LIEF::assembly::mips::OPCODE::MUHU_MMR6) + .value("MUH_MMR6", LIEF::assembly::mips::OPCODE::MUH_MMR6) + .value("MUL", LIEF::assembly::mips::OPCODE::MUL) + .value("MULEQ_S_W_PHL", LIEF::assembly::mips::OPCODE::MULEQ_S_W_PHL) + .value("MULEQ_S_W_PHL_MM", LIEF::assembly::mips::OPCODE::MULEQ_S_W_PHL_MM) + .value("MULEQ_S_W_PHR", LIEF::assembly::mips::OPCODE::MULEQ_S_W_PHR) + .value("MULEQ_S_W_PHR_MM", LIEF::assembly::mips::OPCODE::MULEQ_S_W_PHR_MM) + .value("MULEU_S_PH_QBL", LIEF::assembly::mips::OPCODE::MULEU_S_PH_QBL) + .value("MULEU_S_PH_QBL_MM", LIEF::assembly::mips::OPCODE::MULEU_S_PH_QBL_MM) + .value("MULEU_S_PH_QBR", LIEF::assembly::mips::OPCODE::MULEU_S_PH_QBR) + .value("MULEU_S_PH_QBR_MM", LIEF::assembly::mips::OPCODE::MULEU_S_PH_QBR_MM) + .value("MULQ_RS_PH", LIEF::assembly::mips::OPCODE::MULQ_RS_PH) + .value("MULQ_RS_PH_MM", LIEF::assembly::mips::OPCODE::MULQ_RS_PH_MM) + .value("MULQ_RS_W", LIEF::assembly::mips::OPCODE::MULQ_RS_W) + .value("MULQ_RS_W_MMR2", LIEF::assembly::mips::OPCODE::MULQ_RS_W_MMR2) + .value("MULQ_S_PH", LIEF::assembly::mips::OPCODE::MULQ_S_PH) + .value("MULQ_S_PH_MMR2", LIEF::assembly::mips::OPCODE::MULQ_S_PH_MMR2) + .value("MULQ_S_W", LIEF::assembly::mips::OPCODE::MULQ_S_W) + .value("MULQ_S_W_MMR2", LIEF::assembly::mips::OPCODE::MULQ_S_W_MMR2) + .value("MULR_PS64", LIEF::assembly::mips::OPCODE::MULR_PS64) + .value("MULR_Q_H", LIEF::assembly::mips::OPCODE::MULR_Q_H) + .value("MULR_Q_W", LIEF::assembly::mips::OPCODE::MULR_Q_W) + .value("MULSAQ_S_W_PH", LIEF::assembly::mips::OPCODE::MULSAQ_S_W_PH) + .value("MULSAQ_S_W_PH_MM", LIEF::assembly::mips::OPCODE::MULSAQ_S_W_PH_MM) + .value("MULSA_W_PH", LIEF::assembly::mips::OPCODE::MULSA_W_PH) + .value("MULSA_W_PH_MMR2", LIEF::assembly::mips::OPCODE::MULSA_W_PH_MMR2) + .value("MULT", LIEF::assembly::mips::OPCODE::MULT) + .value("MULTU_DSP", LIEF::assembly::mips::OPCODE::MULTU_DSP) + .value("MULTU_DSP_MM", LIEF::assembly::mips::OPCODE::MULTU_DSP_MM) + .value("MULT_DSP", LIEF::assembly::mips::OPCODE::MULT_DSP) + .value("MULT_DSP_MM", LIEF::assembly::mips::OPCODE::MULT_DSP_MM) + .value("MULT_MM", LIEF::assembly::mips::OPCODE::MULT_MM) + .value("MULTu", LIEF::assembly::mips::OPCODE::MULTu) + .value("MULTu_MM", LIEF::assembly::mips::OPCODE::MULTu_MM) + .value("MULU", LIEF::assembly::mips::OPCODE::MULU) + .value("MULU_MMR6", LIEF::assembly::mips::OPCODE::MULU_MMR6) + .value("MULV_B", LIEF::assembly::mips::OPCODE::MULV_B) + .value("MULV_D", LIEF::assembly::mips::OPCODE::MULV_D) + .value("MULV_H", LIEF::assembly::mips::OPCODE::MULV_H) + .value("MULV_W", LIEF::assembly::mips::OPCODE::MULV_W) + .value("MUL_MM", LIEF::assembly::mips::OPCODE::MUL_MM) + .value("MUL_MMR6", LIEF::assembly::mips::OPCODE::MUL_MMR6) + .value("MUL_PH", LIEF::assembly::mips::OPCODE::MUL_PH) + .value("MUL_PH_MMR2", LIEF::assembly::mips::OPCODE::MUL_PH_MMR2) + .value("MUL_Q_H", LIEF::assembly::mips::OPCODE::MUL_Q_H) + .value("MUL_Q_W", LIEF::assembly::mips::OPCODE::MUL_Q_W) + .value("MUL_R6", LIEF::assembly::mips::OPCODE::MUL_R6) + .value("MUL_S_PH", LIEF::assembly::mips::OPCODE::MUL_S_PH) + .value("MUL_S_PH_MMR2", LIEF::assembly::mips::OPCODE::MUL_S_PH_MMR2) + .value("Mfhi16", LIEF::assembly::mips::OPCODE::Mfhi16) + .value("Mflo16", LIEF::assembly::mips::OPCODE::Mflo16) + .value("Move32R16", LIEF::assembly::mips::OPCODE::Move32R16) + .value("MoveR3216", LIEF::assembly::mips::OPCODE::MoveR3216) + .value("NAL", LIEF::assembly::mips::OPCODE::NAL) + .value("NLOC_B", LIEF::assembly::mips::OPCODE::NLOC_B) + .value("NLOC_D", LIEF::assembly::mips::OPCODE::NLOC_D) + .value("NLOC_H", LIEF::assembly::mips::OPCODE::NLOC_H) + .value("NLOC_W", LIEF::assembly::mips::OPCODE::NLOC_W) + .value("NLZC_B", LIEF::assembly::mips::OPCODE::NLZC_B) + .value("NLZC_D", LIEF::assembly::mips::OPCODE::NLZC_D) + .value("NLZC_H", LIEF::assembly::mips::OPCODE::NLZC_H) + .value("NLZC_W", LIEF::assembly::mips::OPCODE::NLZC_W) + .value("NMADD_D32", LIEF::assembly::mips::OPCODE::NMADD_D32) + .value("NMADD_D32_MM", LIEF::assembly::mips::OPCODE::NMADD_D32_MM) + .value("NMADD_D64", LIEF::assembly::mips::OPCODE::NMADD_D64) + .value("NMADD_S", LIEF::assembly::mips::OPCODE::NMADD_S) + .value("NMADD_S_MM", LIEF::assembly::mips::OPCODE::NMADD_S_MM) + .value("NMSUB_D32", LIEF::assembly::mips::OPCODE::NMSUB_D32) + .value("NMSUB_D32_MM", LIEF::assembly::mips::OPCODE::NMSUB_D32_MM) + .value("NMSUB_D64", LIEF::assembly::mips::OPCODE::NMSUB_D64) + .value("NMSUB_S", LIEF::assembly::mips::OPCODE::NMSUB_S) + .value("NMSUB_S_MM", LIEF::assembly::mips::OPCODE::NMSUB_S_MM) + .value("NOR", LIEF::assembly::mips::OPCODE::NOR) + .value("NOR64", LIEF::assembly::mips::OPCODE::NOR64) + .value("NORI_B", LIEF::assembly::mips::OPCODE::NORI_B) + .value("NOR_MM", LIEF::assembly::mips::OPCODE::NOR_MM) + .value("NOR_MMR6", LIEF::assembly::mips::OPCODE::NOR_MMR6) + .value("NOR_V", LIEF::assembly::mips::OPCODE::NOR_V) + .value("NOT16_MM", LIEF::assembly::mips::OPCODE::NOT16_MM) + .value("NOT16_MMR6", LIEF::assembly::mips::OPCODE::NOT16_MMR6) + .value("NegRxRy16", LIEF::assembly::mips::OPCODE::NegRxRy16) + .value("NotRxRy16", LIEF::assembly::mips::OPCODE::NotRxRy16) + .value("OR", LIEF::assembly::mips::OPCODE::OR) + .value("OR16_MM", LIEF::assembly::mips::OPCODE::OR16_MM) + .value("OR16_MMR6", LIEF::assembly::mips::OPCODE::OR16_MMR6) + .value("OR64", LIEF::assembly::mips::OPCODE::OR64) + .value("ORI_B", LIEF::assembly::mips::OPCODE::ORI_B) + .value("ORI_MMR6", LIEF::assembly::mips::OPCODE::ORI_MMR6) + .value("OR_MM", LIEF::assembly::mips::OPCODE::OR_MM) + .value("OR_MMR6", LIEF::assembly::mips::OPCODE::OR_MMR6) + .value("OR_V", LIEF::assembly::mips::OPCODE::OR_V) + .value("ORi", LIEF::assembly::mips::OPCODE::ORi) + .value("ORi64", LIEF::assembly::mips::OPCODE::ORi64) + .value("ORi_MM", LIEF::assembly::mips::OPCODE::ORi_MM) + .value("OrRxRxRy16", LIEF::assembly::mips::OPCODE::OrRxRxRy16) + .value("PACKRL_PH", LIEF::assembly::mips::OPCODE::PACKRL_PH) + .value("PACKRL_PH_MM", LIEF::assembly::mips::OPCODE::PACKRL_PH_MM) + .value("PAUSE", LIEF::assembly::mips::OPCODE::PAUSE) + .value("PAUSE_MM", LIEF::assembly::mips::OPCODE::PAUSE_MM) + .value("PAUSE_MMR6", LIEF::assembly::mips::OPCODE::PAUSE_MMR6) + .value("PCKEV_B", LIEF::assembly::mips::OPCODE::PCKEV_B) + .value("PCKEV_D", LIEF::assembly::mips::OPCODE::PCKEV_D) + .value("PCKEV_H", LIEF::assembly::mips::OPCODE::PCKEV_H) + .value("PCKEV_W", LIEF::assembly::mips::OPCODE::PCKEV_W) + .value("PCKOD_B", LIEF::assembly::mips::OPCODE::PCKOD_B) + .value("PCKOD_D", LIEF::assembly::mips::OPCODE::PCKOD_D) + .value("PCKOD_H", LIEF::assembly::mips::OPCODE::PCKOD_H) + .value("PCKOD_W", LIEF::assembly::mips::OPCODE::PCKOD_W) + .value("PCNT_B", LIEF::assembly::mips::OPCODE::PCNT_B) + .value("PCNT_D", LIEF::assembly::mips::OPCODE::PCNT_D) + .value("PCNT_H", LIEF::assembly::mips::OPCODE::PCNT_H) + .value("PCNT_W", LIEF::assembly::mips::OPCODE::PCNT_W) + .value("PICK_PH", LIEF::assembly::mips::OPCODE::PICK_PH) + .value("PICK_PH_MM", LIEF::assembly::mips::OPCODE::PICK_PH_MM) + .value("PICK_QB", LIEF::assembly::mips::OPCODE::PICK_QB) + .value("PICK_QB_MM", LIEF::assembly::mips::OPCODE::PICK_QB_MM) + .value("PLL_PS64", LIEF::assembly::mips::OPCODE::PLL_PS64) + .value("PLU_PS64", LIEF::assembly::mips::OPCODE::PLU_PS64) + .value("POP", LIEF::assembly::mips::OPCODE::POP) + .value("PRECEQU_PH_QBL", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBL) + .value("PRECEQU_PH_QBLA", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBLA) + .value("PRECEQU_PH_QBLA_MM", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBLA_MM) + .value("PRECEQU_PH_QBL_MM", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBL_MM) + .value("PRECEQU_PH_QBR", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBR) + .value("PRECEQU_PH_QBRA", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBRA) + .value("PRECEQU_PH_QBRA_MM", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBRA_MM) + .value("PRECEQU_PH_QBR_MM", LIEF::assembly::mips::OPCODE::PRECEQU_PH_QBR_MM) + .value("PRECEQ_W_PHL", LIEF::assembly::mips::OPCODE::PRECEQ_W_PHL) + .value("PRECEQ_W_PHL_MM", LIEF::assembly::mips::OPCODE::PRECEQ_W_PHL_MM) + .value("PRECEQ_W_PHR", LIEF::assembly::mips::OPCODE::PRECEQ_W_PHR) + .value("PRECEQ_W_PHR_MM", LIEF::assembly::mips::OPCODE::PRECEQ_W_PHR_MM) + .value("PRECEU_PH_QBL", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBL) + .value("PRECEU_PH_QBLA", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBLA) + .value("PRECEU_PH_QBLA_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBLA_MM) + .value("PRECEU_PH_QBL_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBL_MM) + .value("PRECEU_PH_QBR", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBR) + .value("PRECEU_PH_QBRA", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBRA) + .value("PRECEU_PH_QBRA_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBRA_MM) + .value("PRECEU_PH_QBR_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBR_MM) + .value("PRECRQU_S_QB_PH", LIEF::assembly::mips::OPCODE::PRECRQU_S_QB_PH) + .value("PRECRQU_S_QB_PH_MM", LIEF::assembly::mips::OPCODE::PRECRQU_S_QB_PH_MM) + .value("PRECRQ_PH_W", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W); + opcodes.value("PRECRQ_PH_W_MM", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W_MM) + .value("PRECRQ_QB_PH", LIEF::assembly::mips::OPCODE::PRECRQ_QB_PH) + .value("PRECRQ_QB_PH_MM", LIEF::assembly::mips::OPCODE::PRECRQ_QB_PH_MM) + .value("PRECRQ_RS_PH_W", LIEF::assembly::mips::OPCODE::PRECRQ_RS_PH_W) + .value("PRECRQ_RS_PH_W_MM", LIEF::assembly::mips::OPCODE::PRECRQ_RS_PH_W_MM) + .value("PRECR_QB_PH", LIEF::assembly::mips::OPCODE::PRECR_QB_PH) + .value("PRECR_QB_PH_MMR2", LIEF::assembly::mips::OPCODE::PRECR_QB_PH_MMR2) + .value("PRECR_SRA_PH_W", LIEF::assembly::mips::OPCODE::PRECR_SRA_PH_W) + .value("PRECR_SRA_PH_W_MMR2", LIEF::assembly::mips::OPCODE::PRECR_SRA_PH_W_MMR2) + .value("PRECR_SRA_R_PH_W", LIEF::assembly::mips::OPCODE::PRECR_SRA_R_PH_W) + .value("PRECR_SRA_R_PH_W_MMR2", LIEF::assembly::mips::OPCODE::PRECR_SRA_R_PH_W_MMR2) + .value("PREF", LIEF::assembly::mips::OPCODE::PREF) + .value("PREFE", LIEF::assembly::mips::OPCODE::PREFE) + .value("PREFE_MM", LIEF::assembly::mips::OPCODE::PREFE_MM) + .value("PREFX_MM", LIEF::assembly::mips::OPCODE::PREFX_MM) + .value("PREF_MM", LIEF::assembly::mips::OPCODE::PREF_MM) + .value("PREF_MMR6", LIEF::assembly::mips::OPCODE::PREF_MMR6) + .value("PREF_R6", LIEF::assembly::mips::OPCODE::PREF_R6) + .value("PREPEND", LIEF::assembly::mips::OPCODE::PREPEND) + .value("PREPEND_MMR2", LIEF::assembly::mips::OPCODE::PREPEND_MMR2) + .value("PUL_PS64", LIEF::assembly::mips::OPCODE::PUL_PS64) + .value("PUU_PS64", LIEF::assembly::mips::OPCODE::PUU_PS64) + .value("RADDU_W_QB", LIEF::assembly::mips::OPCODE::RADDU_W_QB) + .value("RADDU_W_QB_MM", LIEF::assembly::mips::OPCODE::RADDU_W_QB_MM) + .value("RDDSP", LIEF::assembly::mips::OPCODE::RDDSP) + .value("RDDSP_MM", LIEF::assembly::mips::OPCODE::RDDSP_MM) + .value("RDHWR", LIEF::assembly::mips::OPCODE::RDHWR) + .value("RDHWR64", LIEF::assembly::mips::OPCODE::RDHWR64) + .value("RDHWR_MM", LIEF::assembly::mips::OPCODE::RDHWR_MM) + .value("RDHWR_MMR6", LIEF::assembly::mips::OPCODE::RDHWR_MMR6) + .value("RDPGPR_MMR6", LIEF::assembly::mips::OPCODE::RDPGPR_MMR6) + .value("RECIP_D32", LIEF::assembly::mips::OPCODE::RECIP_D32) + .value("RECIP_D32_MM", LIEF::assembly::mips::OPCODE::RECIP_D32_MM) + .value("RECIP_D64", LIEF::assembly::mips::OPCODE::RECIP_D64) + .value("RECIP_D64_MM", LIEF::assembly::mips::OPCODE::RECIP_D64_MM) + .value("RECIP_S", LIEF::assembly::mips::OPCODE::RECIP_S) + .value("RECIP_S_MM", LIEF::assembly::mips::OPCODE::RECIP_S_MM) + .value("REPLV_PH", LIEF::assembly::mips::OPCODE::REPLV_PH) + .value("REPLV_PH_MM", LIEF::assembly::mips::OPCODE::REPLV_PH_MM) + .value("REPLV_QB", LIEF::assembly::mips::OPCODE::REPLV_QB) + .value("REPLV_QB_MM", LIEF::assembly::mips::OPCODE::REPLV_QB_MM) + .value("REPL_PH", LIEF::assembly::mips::OPCODE::REPL_PH) + .value("REPL_PH_MM", LIEF::assembly::mips::OPCODE::REPL_PH_MM) + .value("REPL_QB", LIEF::assembly::mips::OPCODE::REPL_QB) + .value("REPL_QB_MM", LIEF::assembly::mips::OPCODE::REPL_QB_MM) + .value("RINT_D", LIEF::assembly::mips::OPCODE::RINT_D) + .value("RINT_D_MMR6", LIEF::assembly::mips::OPCODE::RINT_D_MMR6) + .value("RINT_S", LIEF::assembly::mips::OPCODE::RINT_S) + .value("RINT_S_MMR6", LIEF::assembly::mips::OPCODE::RINT_S_MMR6) + .value("ROTR", LIEF::assembly::mips::OPCODE::ROTR) + .value("ROTRV", LIEF::assembly::mips::OPCODE::ROTRV) + .value("ROTRV_MM", LIEF::assembly::mips::OPCODE::ROTRV_MM) + .value("ROTR_MM", LIEF::assembly::mips::OPCODE::ROTR_MM) + .value("ROUND_L_D64", LIEF::assembly::mips::OPCODE::ROUND_L_D64) + .value("ROUND_L_D_MMR6", LIEF::assembly::mips::OPCODE::ROUND_L_D_MMR6) + .value("ROUND_L_S", LIEF::assembly::mips::OPCODE::ROUND_L_S) + .value("ROUND_L_S_MMR6", LIEF::assembly::mips::OPCODE::ROUND_L_S_MMR6) + .value("ROUND_W_D32", LIEF::assembly::mips::OPCODE::ROUND_W_D32) + .value("ROUND_W_D64", LIEF::assembly::mips::OPCODE::ROUND_W_D64) + .value("ROUND_W_D_MMR6", LIEF::assembly::mips::OPCODE::ROUND_W_D_MMR6) + .value("ROUND_W_MM", LIEF::assembly::mips::OPCODE::ROUND_W_MM) + .value("ROUND_W_S", LIEF::assembly::mips::OPCODE::ROUND_W_S) + .value("ROUND_W_S_MM", LIEF::assembly::mips::OPCODE::ROUND_W_S_MM) + .value("ROUND_W_S_MMR6", LIEF::assembly::mips::OPCODE::ROUND_W_S_MMR6) + .value("RSQRT_D32", LIEF::assembly::mips::OPCODE::RSQRT_D32) + .value("RSQRT_D32_MM", LIEF::assembly::mips::OPCODE::RSQRT_D32_MM) + .value("RSQRT_D64", LIEF::assembly::mips::OPCODE::RSQRT_D64) + .value("RSQRT_D64_MM", LIEF::assembly::mips::OPCODE::RSQRT_D64_MM) + .value("RSQRT_S", LIEF::assembly::mips::OPCODE::RSQRT_S) + .value("RSQRT_S_MM", LIEF::assembly::mips::OPCODE::RSQRT_S_MM) + .value("Restore16", LIEF::assembly::mips::OPCODE::Restore16) + .value("RestoreX16", LIEF::assembly::mips::OPCODE::RestoreX16) + .value("SAA", LIEF::assembly::mips::OPCODE::SAA) + .value("SAAD", LIEF::assembly::mips::OPCODE::SAAD) + .value("SAT_S_B", LIEF::assembly::mips::OPCODE::SAT_S_B) + .value("SAT_S_D", LIEF::assembly::mips::OPCODE::SAT_S_D) + .value("SAT_S_H", LIEF::assembly::mips::OPCODE::SAT_S_H) + .value("SAT_S_W", LIEF::assembly::mips::OPCODE::SAT_S_W) + .value("SAT_U_B", LIEF::assembly::mips::OPCODE::SAT_U_B) + .value("SAT_U_D", LIEF::assembly::mips::OPCODE::SAT_U_D) + .value("SAT_U_H", LIEF::assembly::mips::OPCODE::SAT_U_H) + .value("SAT_U_W", LIEF::assembly::mips::OPCODE::SAT_U_W) + .value("SB", LIEF::assembly::mips::OPCODE::SB) + .value("SB16_MM", LIEF::assembly::mips::OPCODE::SB16_MM) + .value("SB16_MMR6", LIEF::assembly::mips::OPCODE::SB16_MMR6) + .value("SB64", LIEF::assembly::mips::OPCODE::SB64) + .value("SBE", LIEF::assembly::mips::OPCODE::SBE) + .value("SBE_MM", LIEF::assembly::mips::OPCODE::SBE_MM) + .value("SB_MM", LIEF::assembly::mips::OPCODE::SB_MM) + .value("SB_MMR6", LIEF::assembly::mips::OPCODE::SB_MMR6) + .value("SC", LIEF::assembly::mips::OPCODE::SC) + .value("SC64", LIEF::assembly::mips::OPCODE::SC64) + .value("SC64_R6", LIEF::assembly::mips::OPCODE::SC64_R6) + .value("SCD", LIEF::assembly::mips::OPCODE::SCD) + .value("SCD_R6", LIEF::assembly::mips::OPCODE::SCD_R6) + .value("SCE", LIEF::assembly::mips::OPCODE::SCE) + .value("SCE_MM", LIEF::assembly::mips::OPCODE::SCE_MM) + .value("SC_MM", LIEF::assembly::mips::OPCODE::SC_MM) + .value("SC_MMR6", LIEF::assembly::mips::OPCODE::SC_MMR6) + .value("SC_R6", LIEF::assembly::mips::OPCODE::SC_R6) + .value("SD", LIEF::assembly::mips::OPCODE::SD) + .value("SDBBP", LIEF::assembly::mips::OPCODE::SDBBP) + .value("SDBBP16_MM", LIEF::assembly::mips::OPCODE::SDBBP16_MM) + .value("SDBBP16_MMR6", LIEF::assembly::mips::OPCODE::SDBBP16_MMR6) + .value("SDBBP_MM", LIEF::assembly::mips::OPCODE::SDBBP_MM) + .value("SDBBP_MMR6", LIEF::assembly::mips::OPCODE::SDBBP_MMR6) + .value("SDBBP_R6", LIEF::assembly::mips::OPCODE::SDBBP_R6) + .value("SDC1", LIEF::assembly::mips::OPCODE::SDC1) + .value("SDC164", LIEF::assembly::mips::OPCODE::SDC164) + .value("SDC1_D64_MMR6", LIEF::assembly::mips::OPCODE::SDC1_D64_MMR6) + .value("SDC1_MM_D32", LIEF::assembly::mips::OPCODE::SDC1_MM_D32) + .value("SDC1_MM_D64", LIEF::assembly::mips::OPCODE::SDC1_MM_D64) + .value("SDC2", LIEF::assembly::mips::OPCODE::SDC2) + .value("SDC2_MMR6", LIEF::assembly::mips::OPCODE::SDC2_MMR6) + .value("SDC2_R6", LIEF::assembly::mips::OPCODE::SDC2_R6) + .value("SDC3", LIEF::assembly::mips::OPCODE::SDC3) + .value("SDIV", LIEF::assembly::mips::OPCODE::SDIV) + .value("SDIV_MM", LIEF::assembly::mips::OPCODE::SDIV_MM) + .value("SDL", LIEF::assembly::mips::OPCODE::SDL) + .value("SDR", LIEF::assembly::mips::OPCODE::SDR) + .value("SDXC1", LIEF::assembly::mips::OPCODE::SDXC1) + .value("SDXC164", LIEF::assembly::mips::OPCODE::SDXC164) + .value("SEB", LIEF::assembly::mips::OPCODE::SEB) + .value("SEB64", LIEF::assembly::mips::OPCODE::SEB64) + .value("SEB_MM", LIEF::assembly::mips::OPCODE::SEB_MM) + .value("SEH", LIEF::assembly::mips::OPCODE::SEH) + .value("SEH64", LIEF::assembly::mips::OPCODE::SEH64) + .value("SEH_MM", LIEF::assembly::mips::OPCODE::SEH_MM) + .value("SELEQZ", LIEF::assembly::mips::OPCODE::SELEQZ) + .value("SELEQZ64", LIEF::assembly::mips::OPCODE::SELEQZ64) + .value("SELEQZ_D", LIEF::assembly::mips::OPCODE::SELEQZ_D) + .value("SELEQZ_D_MMR6", LIEF::assembly::mips::OPCODE::SELEQZ_D_MMR6) + .value("SELEQZ_MMR6", LIEF::assembly::mips::OPCODE::SELEQZ_MMR6) + .value("SELEQZ_S", LIEF::assembly::mips::OPCODE::SELEQZ_S) + .value("SELEQZ_S_MMR6", LIEF::assembly::mips::OPCODE::SELEQZ_S_MMR6) + .value("SELNEZ", LIEF::assembly::mips::OPCODE::SELNEZ) + .value("SELNEZ64", LIEF::assembly::mips::OPCODE::SELNEZ64) + .value("SELNEZ_D", LIEF::assembly::mips::OPCODE::SELNEZ_D) + .value("SELNEZ_D_MMR6", LIEF::assembly::mips::OPCODE::SELNEZ_D_MMR6) + .value("SELNEZ_MMR6", LIEF::assembly::mips::OPCODE::SELNEZ_MMR6) + .value("SELNEZ_S", LIEF::assembly::mips::OPCODE::SELNEZ_S) + .value("SELNEZ_S_MMR6", LIEF::assembly::mips::OPCODE::SELNEZ_S_MMR6) + .value("SEL_D", LIEF::assembly::mips::OPCODE::SEL_D) + .value("SEL_D_MMR6", LIEF::assembly::mips::OPCODE::SEL_D_MMR6) + .value("SEL_S", LIEF::assembly::mips::OPCODE::SEL_S) + .value("SEL_S_MMR6", LIEF::assembly::mips::OPCODE::SEL_S_MMR6) + .value("SEQ", LIEF::assembly::mips::OPCODE::SEQ) + .value("SEQi", LIEF::assembly::mips::OPCODE::SEQi) + .value("SH", LIEF::assembly::mips::OPCODE::SH) + .value("SH16_MM", LIEF::assembly::mips::OPCODE::SH16_MM) + .value("SH16_MMR6", LIEF::assembly::mips::OPCODE::SH16_MMR6) + .value("SH64", LIEF::assembly::mips::OPCODE::SH64) + .value("SHE", LIEF::assembly::mips::OPCODE::SHE) + .value("SHE_MM", LIEF::assembly::mips::OPCODE::SHE_MM) + .value("SHF_B", LIEF::assembly::mips::OPCODE::SHF_B) + .value("SHF_H", LIEF::assembly::mips::OPCODE::SHF_H) + .value("SHF_W", LIEF::assembly::mips::OPCODE::SHF_W) + .value("SHILO", LIEF::assembly::mips::OPCODE::SHILO) + .value("SHILOV", LIEF::assembly::mips::OPCODE::SHILOV) + .value("SHILOV_MM", LIEF::assembly::mips::OPCODE::SHILOV_MM) + .value("SHILO_MM", LIEF::assembly::mips::OPCODE::SHILO_MM) + .value("SHLLV_PH", LIEF::assembly::mips::OPCODE::SHLLV_PH) + .value("SHLLV_PH_MM", LIEF::assembly::mips::OPCODE::SHLLV_PH_MM) + .value("SHLLV_QB", LIEF::assembly::mips::OPCODE::SHLLV_QB) + .value("SHLLV_QB_MM", LIEF::assembly::mips::OPCODE::SHLLV_QB_MM) + .value("SHLLV_S_PH", LIEF::assembly::mips::OPCODE::SHLLV_S_PH) + .value("SHLLV_S_PH_MM", LIEF::assembly::mips::OPCODE::SHLLV_S_PH_MM) + .value("SHLLV_S_W", LIEF::assembly::mips::OPCODE::SHLLV_S_W) + .value("SHLLV_S_W_MM", LIEF::assembly::mips::OPCODE::SHLLV_S_W_MM) + .value("SHLL_PH", LIEF::assembly::mips::OPCODE::SHLL_PH) + .value("SHLL_PH_MM", LIEF::assembly::mips::OPCODE::SHLL_PH_MM) + .value("SHLL_QB", LIEF::assembly::mips::OPCODE::SHLL_QB) + .value("SHLL_QB_MM", LIEF::assembly::mips::OPCODE::SHLL_QB_MM) + .value("SHLL_S_PH", LIEF::assembly::mips::OPCODE::SHLL_S_PH) + .value("SHLL_S_PH_MM", LIEF::assembly::mips::OPCODE::SHLL_S_PH_MM) + .value("SHLL_S_W", LIEF::assembly::mips::OPCODE::SHLL_S_W) + .value("SHLL_S_W_MM", LIEF::assembly::mips::OPCODE::SHLL_S_W_MM) + .value("SHRAV_PH", LIEF::assembly::mips::OPCODE::SHRAV_PH) + .value("SHRAV_PH_MM", LIEF::assembly::mips::OPCODE::SHRAV_PH_MM) + .value("SHRAV_QB", LIEF::assembly::mips::OPCODE::SHRAV_QB) + .value("SHRAV_QB_MMR2", LIEF::assembly::mips::OPCODE::SHRAV_QB_MMR2) + .value("SHRAV_R_PH", LIEF::assembly::mips::OPCODE::SHRAV_R_PH) + .value("SHRAV_R_PH_MM", LIEF::assembly::mips::OPCODE::SHRAV_R_PH_MM) + .value("SHRAV_R_QB", LIEF::assembly::mips::OPCODE::SHRAV_R_QB) + .value("SHRAV_R_QB_MMR2", LIEF::assembly::mips::OPCODE::SHRAV_R_QB_MMR2) + .value("SHRAV_R_W", LIEF::assembly::mips::OPCODE::SHRAV_R_W) + .value("SHRAV_R_W_MM", LIEF::assembly::mips::OPCODE::SHRAV_R_W_MM) + .value("SHRA_PH", LIEF::assembly::mips::OPCODE::SHRA_PH) + .value("SHRA_PH_MM", LIEF::assembly::mips::OPCODE::SHRA_PH_MM) + .value("SHRA_QB", LIEF::assembly::mips::OPCODE::SHRA_QB) + .value("SHRA_QB_MMR2", LIEF::assembly::mips::OPCODE::SHRA_QB_MMR2) + .value("SHRA_R_PH", LIEF::assembly::mips::OPCODE::SHRA_R_PH) + .value("SHRA_R_PH_MM", LIEF::assembly::mips::OPCODE::SHRA_R_PH_MM) + .value("SHRA_R_QB", LIEF::assembly::mips::OPCODE::SHRA_R_QB) + .value("SHRA_R_QB_MMR2", LIEF::assembly::mips::OPCODE::SHRA_R_QB_MMR2) + .value("SHRA_R_W", LIEF::assembly::mips::OPCODE::SHRA_R_W) + .value("SHRA_R_W_MM", LIEF::assembly::mips::OPCODE::SHRA_R_W_MM) + .value("SHRLV_PH", LIEF::assembly::mips::OPCODE::SHRLV_PH) + .value("SHRLV_PH_MMR2", LIEF::assembly::mips::OPCODE::SHRLV_PH_MMR2) + .value("SHRLV_QB", LIEF::assembly::mips::OPCODE::SHRLV_QB) + .value("SHRLV_QB_MM", LIEF::assembly::mips::OPCODE::SHRLV_QB_MM) + .value("SHRL_PH", LIEF::assembly::mips::OPCODE::SHRL_PH) + .value("SHRL_PH_MMR2", LIEF::assembly::mips::OPCODE::SHRL_PH_MMR2) + .value("SHRL_QB", LIEF::assembly::mips::OPCODE::SHRL_QB) + .value("SHRL_QB_MM", LIEF::assembly::mips::OPCODE::SHRL_QB_MM) + .value("SH_MM", LIEF::assembly::mips::OPCODE::SH_MM) + .value("SH_MMR6", LIEF::assembly::mips::OPCODE::SH_MMR6) + .value("SIGRIE", LIEF::assembly::mips::OPCODE::SIGRIE) + .value("SIGRIE_MMR6", LIEF::assembly::mips::OPCODE::SIGRIE_MMR6) + .value("SLDI_B", LIEF::assembly::mips::OPCODE::SLDI_B) + .value("SLDI_D", LIEF::assembly::mips::OPCODE::SLDI_D) + .value("SLDI_H", LIEF::assembly::mips::OPCODE::SLDI_H) + .value("SLDI_W", LIEF::assembly::mips::OPCODE::SLDI_W) + .value("SLD_B", LIEF::assembly::mips::OPCODE::SLD_B) + .value("SLD_D", LIEF::assembly::mips::OPCODE::SLD_D) + .value("SLD_H", LIEF::assembly::mips::OPCODE::SLD_H) + .value("SLD_W", LIEF::assembly::mips::OPCODE::SLD_W) + .value("SLL", LIEF::assembly::mips::OPCODE::SLL) + .value("SLL16_MM", LIEF::assembly::mips::OPCODE::SLL16_MM) + .value("SLL16_MMR6", LIEF::assembly::mips::OPCODE::SLL16_MMR6) + .value("SLL64_32", LIEF::assembly::mips::OPCODE::SLL64_32) + .value("SLL64_64", LIEF::assembly::mips::OPCODE::SLL64_64) + .value("SLLI_B", LIEF::assembly::mips::OPCODE::SLLI_B) + .value("SLLI_D", LIEF::assembly::mips::OPCODE::SLLI_D) + .value("SLLI_H", LIEF::assembly::mips::OPCODE::SLLI_H) + .value("SLLI_W", LIEF::assembly::mips::OPCODE::SLLI_W) + .value("SLLV", LIEF::assembly::mips::OPCODE::SLLV) + .value("SLLV_MM", LIEF::assembly::mips::OPCODE::SLLV_MM) + .value("SLL_B", LIEF::assembly::mips::OPCODE::SLL_B) + .value("SLL_D", LIEF::assembly::mips::OPCODE::SLL_D) + .value("SLL_H", LIEF::assembly::mips::OPCODE::SLL_H) + .value("SLL_MM", LIEF::assembly::mips::OPCODE::SLL_MM) + .value("SLL_MMR6", LIEF::assembly::mips::OPCODE::SLL_MMR6) + .value("SLL_W", LIEF::assembly::mips::OPCODE::SLL_W) + .value("SLT", LIEF::assembly::mips::OPCODE::SLT) + .value("SLT64", LIEF::assembly::mips::OPCODE::SLT64) + .value("SLT_MM", LIEF::assembly::mips::OPCODE::SLT_MM) + .value("SLTi", LIEF::assembly::mips::OPCODE::SLTi) + .value("SLTi64", LIEF::assembly::mips::OPCODE::SLTi64) + .value("SLTi_MM", LIEF::assembly::mips::OPCODE::SLTi_MM) + .value("SLTiu", LIEF::assembly::mips::OPCODE::SLTiu) + .value("SLTiu64", LIEF::assembly::mips::OPCODE::SLTiu64) + .value("SLTiu_MM", LIEF::assembly::mips::OPCODE::SLTiu_MM) + .value("SLTu", LIEF::assembly::mips::OPCODE::SLTu) + .value("SLTu64", LIEF::assembly::mips::OPCODE::SLTu64) + .value("SLTu_MM", LIEF::assembly::mips::OPCODE::SLTu_MM) + .value("SNE", LIEF::assembly::mips::OPCODE::SNE) + .value("SNEi", LIEF::assembly::mips::OPCODE::SNEi) + .value("SPLATI_B", LIEF::assembly::mips::OPCODE::SPLATI_B) + .value("SPLATI_D", LIEF::assembly::mips::OPCODE::SPLATI_D) + .value("SPLATI_H", LIEF::assembly::mips::OPCODE::SPLATI_H) + .value("SPLATI_W", LIEF::assembly::mips::OPCODE::SPLATI_W) + .value("SPLAT_B", LIEF::assembly::mips::OPCODE::SPLAT_B) + .value("SPLAT_D", LIEF::assembly::mips::OPCODE::SPLAT_D) + .value("SPLAT_H", LIEF::assembly::mips::OPCODE::SPLAT_H) + .value("SPLAT_W", LIEF::assembly::mips::OPCODE::SPLAT_W) + .value("SRA", LIEF::assembly::mips::OPCODE::SRA) + .value("SRAI_B", LIEF::assembly::mips::OPCODE::SRAI_B) + .value("SRAI_D", LIEF::assembly::mips::OPCODE::SRAI_D) + .value("SRAI_H", LIEF::assembly::mips::OPCODE::SRAI_H) + .value("SRAI_W", LIEF::assembly::mips::OPCODE::SRAI_W) + .value("SRARI_B", LIEF::assembly::mips::OPCODE::SRARI_B) + .value("SRARI_D", LIEF::assembly::mips::OPCODE::SRARI_D) + .value("SRARI_H", LIEF::assembly::mips::OPCODE::SRARI_H) + .value("SRARI_W", LIEF::assembly::mips::OPCODE::SRARI_W) + .value("SRAR_B", LIEF::assembly::mips::OPCODE::SRAR_B) + .value("SRAR_D", LIEF::assembly::mips::OPCODE::SRAR_D) + .value("SRAR_H", LIEF::assembly::mips::OPCODE::SRAR_H) + .value("SRAR_W", LIEF::assembly::mips::OPCODE::SRAR_W) + .value("SRAV", LIEF::assembly::mips::OPCODE::SRAV) + .value("SRAV_MM", LIEF::assembly::mips::OPCODE::SRAV_MM) + .value("SRA_B", LIEF::assembly::mips::OPCODE::SRA_B) + .value("SRA_D", LIEF::assembly::mips::OPCODE::SRA_D) + .value("SRA_H", LIEF::assembly::mips::OPCODE::SRA_H) + .value("SRA_MM", LIEF::assembly::mips::OPCODE::SRA_MM) + .value("SRA_W", LIEF::assembly::mips::OPCODE::SRA_W) + .value("SRL", LIEF::assembly::mips::OPCODE::SRL) + .value("SRL16_MM", LIEF::assembly::mips::OPCODE::SRL16_MM) + .value("SRL16_MMR6", LIEF::assembly::mips::OPCODE::SRL16_MMR6) + .value("SRLI_B", LIEF::assembly::mips::OPCODE::SRLI_B) + .value("SRLI_D", LIEF::assembly::mips::OPCODE::SRLI_D) + .value("SRLI_H", LIEF::assembly::mips::OPCODE::SRLI_H) + .value("SRLI_W", LIEF::assembly::mips::OPCODE::SRLI_W) + .value("SRLRI_B", LIEF::assembly::mips::OPCODE::SRLRI_B) + .value("SRLRI_D", LIEF::assembly::mips::OPCODE::SRLRI_D) + .value("SRLRI_H", LIEF::assembly::mips::OPCODE::SRLRI_H) + .value("SRLRI_W", LIEF::assembly::mips::OPCODE::SRLRI_W) + .value("SRLR_B", LIEF::assembly::mips::OPCODE::SRLR_B) + .value("SRLR_D", LIEF::assembly::mips::OPCODE::SRLR_D) + .value("SRLR_H", LIEF::assembly::mips::OPCODE::SRLR_H) + .value("SRLR_W", LIEF::assembly::mips::OPCODE::SRLR_W) + .value("SRLV", LIEF::assembly::mips::OPCODE::SRLV) + .value("SRLV_MM", LIEF::assembly::mips::OPCODE::SRLV_MM) + .value("SRL_B", LIEF::assembly::mips::OPCODE::SRL_B) + .value("SRL_D", LIEF::assembly::mips::OPCODE::SRL_D) + .value("SRL_H", LIEF::assembly::mips::OPCODE::SRL_H) + .value("SRL_MM", LIEF::assembly::mips::OPCODE::SRL_MM) + .value("SRL_W", LIEF::assembly::mips::OPCODE::SRL_W) + .value("SSNOP", LIEF::assembly::mips::OPCODE::SSNOP) + .value("SSNOP_MM", LIEF::assembly::mips::OPCODE::SSNOP_MM); + opcodes.value("SSNOP_MMR6", LIEF::assembly::mips::OPCODE::SSNOP_MMR6) + .value("ST_B", LIEF::assembly::mips::OPCODE::ST_B) + .value("ST_D", LIEF::assembly::mips::OPCODE::ST_D) + .value("ST_H", LIEF::assembly::mips::OPCODE::ST_H) + .value("ST_W", LIEF::assembly::mips::OPCODE::ST_W) + .value("SUB", LIEF::assembly::mips::OPCODE::SUB) + .value("SUBQH_PH", LIEF::assembly::mips::OPCODE::SUBQH_PH) + .value("SUBQH_PH_MMR2", LIEF::assembly::mips::OPCODE::SUBQH_PH_MMR2) + .value("SUBQH_R_PH", LIEF::assembly::mips::OPCODE::SUBQH_R_PH) + .value("SUBQH_R_PH_MMR2", LIEF::assembly::mips::OPCODE::SUBQH_R_PH_MMR2) + .value("SUBQH_R_W", LIEF::assembly::mips::OPCODE::SUBQH_R_W) + .value("SUBQH_R_W_MMR2", LIEF::assembly::mips::OPCODE::SUBQH_R_W_MMR2) + .value("SUBQH_W", LIEF::assembly::mips::OPCODE::SUBQH_W) + .value("SUBQH_W_MMR2", LIEF::assembly::mips::OPCODE::SUBQH_W_MMR2) + .value("SUBQ_PH", LIEF::assembly::mips::OPCODE::SUBQ_PH) + .value("SUBQ_PH_MM", LIEF::assembly::mips::OPCODE::SUBQ_PH_MM) + .value("SUBQ_S_PH", LIEF::assembly::mips::OPCODE::SUBQ_S_PH) + .value("SUBQ_S_PH_MM", LIEF::assembly::mips::OPCODE::SUBQ_S_PH_MM) + .value("SUBQ_S_W", LIEF::assembly::mips::OPCODE::SUBQ_S_W) + .value("SUBQ_S_W_MM", LIEF::assembly::mips::OPCODE::SUBQ_S_W_MM) + .value("SUBSUS_U_B", LIEF::assembly::mips::OPCODE::SUBSUS_U_B) + .value("SUBSUS_U_D", LIEF::assembly::mips::OPCODE::SUBSUS_U_D) + .value("SUBSUS_U_H", LIEF::assembly::mips::OPCODE::SUBSUS_U_H) + .value("SUBSUS_U_W", LIEF::assembly::mips::OPCODE::SUBSUS_U_W) + .value("SUBSUU_S_B", LIEF::assembly::mips::OPCODE::SUBSUU_S_B) + .value("SUBSUU_S_D", LIEF::assembly::mips::OPCODE::SUBSUU_S_D) + .value("SUBSUU_S_H", LIEF::assembly::mips::OPCODE::SUBSUU_S_H) + .value("SUBSUU_S_W", LIEF::assembly::mips::OPCODE::SUBSUU_S_W) + .value("SUBS_S_B", LIEF::assembly::mips::OPCODE::SUBS_S_B) + .value("SUBS_S_D", LIEF::assembly::mips::OPCODE::SUBS_S_D) + .value("SUBS_S_H", LIEF::assembly::mips::OPCODE::SUBS_S_H) + .value("SUBS_S_W", LIEF::assembly::mips::OPCODE::SUBS_S_W) + .value("SUBS_U_B", LIEF::assembly::mips::OPCODE::SUBS_U_B) + .value("SUBS_U_D", LIEF::assembly::mips::OPCODE::SUBS_U_D) + .value("SUBS_U_H", LIEF::assembly::mips::OPCODE::SUBS_U_H) + .value("SUBS_U_W", LIEF::assembly::mips::OPCODE::SUBS_U_W) + .value("SUBU16_MM", LIEF::assembly::mips::OPCODE::SUBU16_MM) + .value("SUBU16_MMR6", LIEF::assembly::mips::OPCODE::SUBU16_MMR6) + .value("SUBUH_QB", LIEF::assembly::mips::OPCODE::SUBUH_QB) + .value("SUBUH_QB_MMR2", LIEF::assembly::mips::OPCODE::SUBUH_QB_MMR2) + .value("SUBUH_R_QB", LIEF::assembly::mips::OPCODE::SUBUH_R_QB) + .value("SUBUH_R_QB_MMR2", LIEF::assembly::mips::OPCODE::SUBUH_R_QB_MMR2) + .value("SUBU_MMR6", LIEF::assembly::mips::OPCODE::SUBU_MMR6) + .value("SUBU_PH", LIEF::assembly::mips::OPCODE::SUBU_PH) + .value("SUBU_PH_MMR2", LIEF::assembly::mips::OPCODE::SUBU_PH_MMR2) + .value("SUBU_QB", LIEF::assembly::mips::OPCODE::SUBU_QB) + .value("SUBU_QB_MM", LIEF::assembly::mips::OPCODE::SUBU_QB_MM) + .value("SUBU_S_PH", LIEF::assembly::mips::OPCODE::SUBU_S_PH) + .value("SUBU_S_PH_MMR2", LIEF::assembly::mips::OPCODE::SUBU_S_PH_MMR2) + .value("SUBU_S_QB", LIEF::assembly::mips::OPCODE::SUBU_S_QB) + .value("SUBU_S_QB_MM", LIEF::assembly::mips::OPCODE::SUBU_S_QB_MM) + .value("SUBVI_B", LIEF::assembly::mips::OPCODE::SUBVI_B) + .value("SUBVI_D", LIEF::assembly::mips::OPCODE::SUBVI_D) + .value("SUBVI_H", LIEF::assembly::mips::OPCODE::SUBVI_H) + .value("SUBVI_W", LIEF::assembly::mips::OPCODE::SUBVI_W) + .value("SUBV_B", LIEF::assembly::mips::OPCODE::SUBV_B) + .value("SUBV_D", LIEF::assembly::mips::OPCODE::SUBV_D) + .value("SUBV_H", LIEF::assembly::mips::OPCODE::SUBV_H) + .value("SUBV_W", LIEF::assembly::mips::OPCODE::SUBV_W) + .value("SUB_MM", LIEF::assembly::mips::OPCODE::SUB_MM) + .value("SUB_MMR6", LIEF::assembly::mips::OPCODE::SUB_MMR6) + .value("SUBu", LIEF::assembly::mips::OPCODE::SUBu) + .value("SUBu_MM", LIEF::assembly::mips::OPCODE::SUBu_MM) + .value("SUXC1", LIEF::assembly::mips::OPCODE::SUXC1) + .value("SUXC164", LIEF::assembly::mips::OPCODE::SUXC164) + .value("SUXC1_MM", LIEF::assembly::mips::OPCODE::SUXC1_MM) + .value("SW", LIEF::assembly::mips::OPCODE::SW) + .value("SW16_MM", LIEF::assembly::mips::OPCODE::SW16_MM) + .value("SW16_MMR6", LIEF::assembly::mips::OPCODE::SW16_MMR6) + .value("SW64", LIEF::assembly::mips::OPCODE::SW64) + .value("SWC1", LIEF::assembly::mips::OPCODE::SWC1) + .value("SWC1_MM", LIEF::assembly::mips::OPCODE::SWC1_MM) + .value("SWC2", LIEF::assembly::mips::OPCODE::SWC2) + .value("SWC2_MMR6", LIEF::assembly::mips::OPCODE::SWC2_MMR6) + .value("SWC2_R6", LIEF::assembly::mips::OPCODE::SWC2_R6) + .value("SWC3", LIEF::assembly::mips::OPCODE::SWC3) + .value("SWDSP", LIEF::assembly::mips::OPCODE::SWDSP) + .value("SWDSP_MM", LIEF::assembly::mips::OPCODE::SWDSP_MM) + .value("SWE", LIEF::assembly::mips::OPCODE::SWE) + .value("SWE_MM", LIEF::assembly::mips::OPCODE::SWE_MM) + .value("SWL", LIEF::assembly::mips::OPCODE::SWL) + .value("SWL64", LIEF::assembly::mips::OPCODE::SWL64) + .value("SWLE", LIEF::assembly::mips::OPCODE::SWLE) + .value("SWLE_MM", LIEF::assembly::mips::OPCODE::SWLE_MM) + .value("SWL_MM", LIEF::assembly::mips::OPCODE::SWL_MM) + .value("SWM16_MM", LIEF::assembly::mips::OPCODE::SWM16_MM) + .value("SWM16_MMR6", LIEF::assembly::mips::OPCODE::SWM16_MMR6) + .value("SWM32_MM", LIEF::assembly::mips::OPCODE::SWM32_MM) + .value("SWP_MM", LIEF::assembly::mips::OPCODE::SWP_MM) + .value("SWR", LIEF::assembly::mips::OPCODE::SWR) + .value("SWR64", LIEF::assembly::mips::OPCODE::SWR64) + .value("SWRE", LIEF::assembly::mips::OPCODE::SWRE) + .value("SWRE_MM", LIEF::assembly::mips::OPCODE::SWRE_MM) + .value("SWR_MM", LIEF::assembly::mips::OPCODE::SWR_MM) + .value("SWSP_MM", LIEF::assembly::mips::OPCODE::SWSP_MM) + .value("SWSP_MMR6", LIEF::assembly::mips::OPCODE::SWSP_MMR6) + .value("SWXC1", LIEF::assembly::mips::OPCODE::SWXC1) + .value("SWXC1_MM", LIEF::assembly::mips::OPCODE::SWXC1_MM) + .value("SW_MM", LIEF::assembly::mips::OPCODE::SW_MM) + .value("SW_MMR6", LIEF::assembly::mips::OPCODE::SW_MMR6) + .value("SYNC", LIEF::assembly::mips::OPCODE::SYNC) + .value("SYNCI", LIEF::assembly::mips::OPCODE::SYNCI) + .value("SYNCI_MM", LIEF::assembly::mips::OPCODE::SYNCI_MM) + .value("SYNCI_MMR6", LIEF::assembly::mips::OPCODE::SYNCI_MMR6) + .value("SYNC_MM", LIEF::assembly::mips::OPCODE::SYNC_MM) + .value("SYNC_MMR6", LIEF::assembly::mips::OPCODE::SYNC_MMR6) + .value("SYSCALL", LIEF::assembly::mips::OPCODE::SYSCALL) + .value("SYSCALL_MM", LIEF::assembly::mips::OPCODE::SYSCALL_MM) + .value("Save16", LIEF::assembly::mips::OPCODE::Save16) + .value("SaveX16", LIEF::assembly::mips::OPCODE::SaveX16) + .value("SbRxRyOffMemX16", LIEF::assembly::mips::OPCODE::SbRxRyOffMemX16) + .value("SebRx16", LIEF::assembly::mips::OPCODE::SebRx16) + .value("SehRx16", LIEF::assembly::mips::OPCODE::SehRx16) + .value("ShRxRyOffMemX16", LIEF::assembly::mips::OPCODE::ShRxRyOffMemX16) + .value("SllX16", LIEF::assembly::mips::OPCODE::SllX16) + .value("SllvRxRy16", LIEF::assembly::mips::OPCODE::SllvRxRy16) + .value("SltRxRy16", LIEF::assembly::mips::OPCODE::SltRxRy16) + .value("SltiRxImm16", LIEF::assembly::mips::OPCODE::SltiRxImm16) + .value("SltiRxImmX16", LIEF::assembly::mips::OPCODE::SltiRxImmX16) + .value("SltiuRxImm16", LIEF::assembly::mips::OPCODE::SltiuRxImm16) + .value("SltiuRxImmX16", LIEF::assembly::mips::OPCODE::SltiuRxImmX16) + .value("SltuRxRy16", LIEF::assembly::mips::OPCODE::SltuRxRy16) + .value("SraX16", LIEF::assembly::mips::OPCODE::SraX16) + .value("SravRxRy16", LIEF::assembly::mips::OPCODE::SravRxRy16) + .value("SrlX16", LIEF::assembly::mips::OPCODE::SrlX16) + .value("SrlvRxRy16", LIEF::assembly::mips::OPCODE::SrlvRxRy16) + .value("SubuRxRyRz16", LIEF::assembly::mips::OPCODE::SubuRxRyRz16) + .value("SwRxRyOffMemX16", LIEF::assembly::mips::OPCODE::SwRxRyOffMemX16) + .value("SwRxSpImmX16", LIEF::assembly::mips::OPCODE::SwRxSpImmX16) + .value("TEQ", LIEF::assembly::mips::OPCODE::TEQ) + .value("TEQI", LIEF::assembly::mips::OPCODE::TEQI) + .value("TEQI_MM", LIEF::assembly::mips::OPCODE::TEQI_MM) + .value("TEQ_MM", LIEF::assembly::mips::OPCODE::TEQ_MM) + .value("TGE", LIEF::assembly::mips::OPCODE::TGE) + .value("TGEI", LIEF::assembly::mips::OPCODE::TGEI) + .value("TGEIU", LIEF::assembly::mips::OPCODE::TGEIU) + .value("TGEIU_MM", LIEF::assembly::mips::OPCODE::TGEIU_MM) + .value("TGEI_MM", LIEF::assembly::mips::OPCODE::TGEI_MM) + .value("TGEU", LIEF::assembly::mips::OPCODE::TGEU) + .value("TGEU_MM", LIEF::assembly::mips::OPCODE::TGEU_MM) + .value("TGE_MM", LIEF::assembly::mips::OPCODE::TGE_MM) + .value("TLBGINV", LIEF::assembly::mips::OPCODE::TLBGINV) + .value("TLBGINVF", LIEF::assembly::mips::OPCODE::TLBGINVF) + .value("TLBGINVF_MM", LIEF::assembly::mips::OPCODE::TLBGINVF_MM) + .value("TLBGINV_MM", LIEF::assembly::mips::OPCODE::TLBGINV_MM) + .value("TLBGP", LIEF::assembly::mips::OPCODE::TLBGP) + .value("TLBGP_MM", LIEF::assembly::mips::OPCODE::TLBGP_MM) + .value("TLBGR", LIEF::assembly::mips::OPCODE::TLBGR) + .value("TLBGR_MM", LIEF::assembly::mips::OPCODE::TLBGR_MM) + .value("TLBGWI", LIEF::assembly::mips::OPCODE::TLBGWI) + .value("TLBGWI_MM", LIEF::assembly::mips::OPCODE::TLBGWI_MM) + .value("TLBGWR", LIEF::assembly::mips::OPCODE::TLBGWR) + .value("TLBGWR_MM", LIEF::assembly::mips::OPCODE::TLBGWR_MM) + .value("TLBINV", LIEF::assembly::mips::OPCODE::TLBINV) + .value("TLBINVF", LIEF::assembly::mips::OPCODE::TLBINVF) + .value("TLBINVF_MMR6", LIEF::assembly::mips::OPCODE::TLBINVF_MMR6) + .value("TLBINV_MMR6", LIEF::assembly::mips::OPCODE::TLBINV_MMR6) + .value("TLBP", LIEF::assembly::mips::OPCODE::TLBP) + .value("TLBP_MM", LIEF::assembly::mips::OPCODE::TLBP_MM) + .value("TLBR", LIEF::assembly::mips::OPCODE::TLBR) + .value("TLBR_MM", LIEF::assembly::mips::OPCODE::TLBR_MM) + .value("TLBWI", LIEF::assembly::mips::OPCODE::TLBWI) + .value("TLBWI_MM", LIEF::assembly::mips::OPCODE::TLBWI_MM) + .value("TLBWR", LIEF::assembly::mips::OPCODE::TLBWR) + .value("TLBWR_MM", LIEF::assembly::mips::OPCODE::TLBWR_MM) + .value("TLT", LIEF::assembly::mips::OPCODE::TLT) + .value("TLTI", LIEF::assembly::mips::OPCODE::TLTI) + .value("TLTIU_MM", LIEF::assembly::mips::OPCODE::TLTIU_MM) + .value("TLTI_MM", LIEF::assembly::mips::OPCODE::TLTI_MM) + .value("TLTU", LIEF::assembly::mips::OPCODE::TLTU) + .value("TLTU_MM", LIEF::assembly::mips::OPCODE::TLTU_MM) + .value("TLT_MM", LIEF::assembly::mips::OPCODE::TLT_MM) + .value("TNE", LIEF::assembly::mips::OPCODE::TNE) + .value("TNEI", LIEF::assembly::mips::OPCODE::TNEI) + .value("TNEI_MM", LIEF::assembly::mips::OPCODE::TNEI_MM) + .value("TNE_MM", LIEF::assembly::mips::OPCODE::TNE_MM) + .value("TRUNC_L_D64", LIEF::assembly::mips::OPCODE::TRUNC_L_D64) + .value("TRUNC_L_D_MMR6", LIEF::assembly::mips::OPCODE::TRUNC_L_D_MMR6) + .value("TRUNC_L_S", LIEF::assembly::mips::OPCODE::TRUNC_L_S) + .value("TRUNC_L_S_MMR6", LIEF::assembly::mips::OPCODE::TRUNC_L_S_MMR6) + .value("TRUNC_W_D32", LIEF::assembly::mips::OPCODE::TRUNC_W_D32) + .value("TRUNC_W_D64", LIEF::assembly::mips::OPCODE::TRUNC_W_D64) + .value("TRUNC_W_D_MMR6", LIEF::assembly::mips::OPCODE::TRUNC_W_D_MMR6) + .value("TRUNC_W_MM", LIEF::assembly::mips::OPCODE::TRUNC_W_MM) + .value("TRUNC_W_S", LIEF::assembly::mips::OPCODE::TRUNC_W_S) + .value("TRUNC_W_S_MM", LIEF::assembly::mips::OPCODE::TRUNC_W_S_MM) + .value("TRUNC_W_S_MMR6", LIEF::assembly::mips::OPCODE::TRUNC_W_S_MMR6) + .value("TTLTIU", LIEF::assembly::mips::OPCODE::TTLTIU) + .value("UDIV", LIEF::assembly::mips::OPCODE::UDIV) + .value("UDIV_MM", LIEF::assembly::mips::OPCODE::UDIV_MM) + .value("V3MULU", LIEF::assembly::mips::OPCODE::V3MULU) + .value("VMM0", LIEF::assembly::mips::OPCODE::VMM0) + .value("VMULU", LIEF::assembly::mips::OPCODE::VMULU) + .value("VSHF_B", LIEF::assembly::mips::OPCODE::VSHF_B) + .value("VSHF_D", LIEF::assembly::mips::OPCODE::VSHF_D) + .value("VSHF_H", LIEF::assembly::mips::OPCODE::VSHF_H) + .value("VSHF_W", LIEF::assembly::mips::OPCODE::VSHF_W) + .value("WAIT", LIEF::assembly::mips::OPCODE::WAIT) + .value("WAIT_MM", LIEF::assembly::mips::OPCODE::WAIT_MM) + .value("WAIT_MMR6", LIEF::assembly::mips::OPCODE::WAIT_MMR6) + .value("WRDSP", LIEF::assembly::mips::OPCODE::WRDSP) + .value("WRDSP_MM", LIEF::assembly::mips::OPCODE::WRDSP_MM) + .value("WRPGPR_MMR6", LIEF::assembly::mips::OPCODE::WRPGPR_MMR6) + .value("WSBH", LIEF::assembly::mips::OPCODE::WSBH) + .value("WSBH_MM", LIEF::assembly::mips::OPCODE::WSBH_MM) + .value("WSBH_MMR6", LIEF::assembly::mips::OPCODE::WSBH_MMR6) + .value("XOR", LIEF::assembly::mips::OPCODE::XOR) + .value("XOR16_MM", LIEF::assembly::mips::OPCODE::XOR16_MM) + .value("XOR16_MMR6", LIEF::assembly::mips::OPCODE::XOR16_MMR6) + .value("XOR64", LIEF::assembly::mips::OPCODE::XOR64) + .value("XORI_B", LIEF::assembly::mips::OPCODE::XORI_B) + .value("XORI_MMR6", LIEF::assembly::mips::OPCODE::XORI_MMR6) + .value("XOR_MM", LIEF::assembly::mips::OPCODE::XOR_MM) + .value("XOR_MMR6", LIEF::assembly::mips::OPCODE::XOR_MMR6) + .value("XOR_V", LIEF::assembly::mips::OPCODE::XOR_V) + .value("XORi", LIEF::assembly::mips::OPCODE::XORi) + .value("XORi64", LIEF::assembly::mips::OPCODE::XORi64) + .value("XORi_MM", LIEF::assembly::mips::OPCODE::XORi_MM) + .value("XorRxRxRy16", LIEF::assembly::mips::OPCODE::XorRxRxRy16) + .value("YIELD", LIEF::assembly::mips::OPCODE::YIELD) + .value("INSTRUCTION_LIST_END", LIEF::assembly::mips::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/mips/pyOperand.cpp b/vendor/lief/api/python/src/asm/mips/pyOperand.cpp new file mode 100644 index 0000000..54ea2df --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/mips/Operand.hpp" + +#include "asm/mips/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::mips::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for a Mips instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(mips::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/mips/pyRegister.cpp b/vendor/lief/api/python/src/asm/mips/pyRegister.cpp new file mode 100644 index 0000000..ea2805b --- /dev/null +++ b/vendor/lief/api/python/src/asm/mips/pyRegister.cpp @@ -0,0 +1,454 @@ +#include "asm/mips/init.hpp" + +#include "LIEF/asm/mips/registers.hpp" + +namespace LIEF::assembly::mips::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::mips::REG::NoRegister) + .value("AT", LIEF::assembly::mips::REG::AT) + .value("DSPCCond", LIEF::assembly::mips::REG::DSPCCond) + .value("DSPCarry", LIEF::assembly::mips::REG::DSPCarry) + .value("DSPEFI", LIEF::assembly::mips::REG::DSPEFI) + .value("DSPOutFlag", LIEF::assembly::mips::REG::DSPOutFlag) + .value("DSPPos", LIEF::assembly::mips::REG::DSPPos) + .value("DSPSCount", LIEF::assembly::mips::REG::DSPSCount) + .value("FP", LIEF::assembly::mips::REG::FP) + .value("GP", LIEF::assembly::mips::REG::GP) + .value("MSAAccess", LIEF::assembly::mips::REG::MSAAccess) + .value("MSACSR", LIEF::assembly::mips::REG::MSACSR) + .value("MSAIR", LIEF::assembly::mips::REG::MSAIR) + .value("MSAMap", LIEF::assembly::mips::REG::MSAMap) + .value("MSAModify", LIEF::assembly::mips::REG::MSAModify) + .value("MSARequest", LIEF::assembly::mips::REG::MSARequest) + .value("MSASave", LIEF::assembly::mips::REG::MSASave) + .value("MSAUnmap", LIEF::assembly::mips::REG::MSAUnmap) + .value("PC", LIEF::assembly::mips::REG::PC) + .value("RA", LIEF::assembly::mips::REG::RA) + .value("SP", LIEF::assembly::mips::REG::SP) + .value("ZERO", LIEF::assembly::mips::REG::ZERO) + .value("A0", LIEF::assembly::mips::REG::A0) + .value("A1", LIEF::assembly::mips::REG::A1) + .value("A2", LIEF::assembly::mips::REG::A2) + .value("A3", LIEF::assembly::mips::REG::A3) + .value("AC0", LIEF::assembly::mips::REG::AC0) + .value("AC1", LIEF::assembly::mips::REG::AC1) + .value("AC2", LIEF::assembly::mips::REG::AC2) + .value("AC3", LIEF::assembly::mips::REG::AC3) + .value("AT_64", LIEF::assembly::mips::REG::AT_64) + .value("COP00", LIEF::assembly::mips::REG::COP00) + .value("COP01", LIEF::assembly::mips::REG::COP01) + .value("COP02", LIEF::assembly::mips::REG::COP02) + .value("COP03", LIEF::assembly::mips::REG::COP03) + .value("COP04", LIEF::assembly::mips::REG::COP04) + .value("COP05", LIEF::assembly::mips::REG::COP05) + .value("COP06", LIEF::assembly::mips::REG::COP06) + .value("COP07", LIEF::assembly::mips::REG::COP07) + .value("COP08", LIEF::assembly::mips::REG::COP08) + .value("COP09", LIEF::assembly::mips::REG::COP09) + .value("COP20", LIEF::assembly::mips::REG::COP20) + .value("COP21", LIEF::assembly::mips::REG::COP21) + .value("COP22", LIEF::assembly::mips::REG::COP22) + .value("COP23", LIEF::assembly::mips::REG::COP23) + .value("COP24", LIEF::assembly::mips::REG::COP24) + .value("COP25", LIEF::assembly::mips::REG::COP25) + .value("COP26", LIEF::assembly::mips::REG::COP26) + .value("COP27", LIEF::assembly::mips::REG::COP27) + .value("COP28", LIEF::assembly::mips::REG::COP28) + .value("COP29", LIEF::assembly::mips::REG::COP29) + .value("COP30", LIEF::assembly::mips::REG::COP30) + .value("COP31", LIEF::assembly::mips::REG::COP31) + .value("COP32", LIEF::assembly::mips::REG::COP32) + .value("COP33", LIEF::assembly::mips::REG::COP33) + .value("COP34", LIEF::assembly::mips::REG::COP34) + .value("COP35", LIEF::assembly::mips::REG::COP35) + .value("COP36", LIEF::assembly::mips::REG::COP36) + .value("COP37", LIEF::assembly::mips::REG::COP37) + .value("COP38", LIEF::assembly::mips::REG::COP38) + .value("COP39", LIEF::assembly::mips::REG::COP39) + .value("COP010", LIEF::assembly::mips::REG::COP010) + .value("COP011", LIEF::assembly::mips::REG::COP011) + .value("COP012", LIEF::assembly::mips::REG::COP012) + .value("COP013", LIEF::assembly::mips::REG::COP013) + .value("COP014", LIEF::assembly::mips::REG::COP014) + .value("COP015", LIEF::assembly::mips::REG::COP015) + .value("COP016", LIEF::assembly::mips::REG::COP016) + .value("COP017", LIEF::assembly::mips::REG::COP017) + .value("COP018", LIEF::assembly::mips::REG::COP018) + .value("COP019", LIEF::assembly::mips::REG::COP019) + .value("COP020", LIEF::assembly::mips::REG::COP020) + .value("COP021", LIEF::assembly::mips::REG::COP021) + .value("COP022", LIEF::assembly::mips::REG::COP022) + .value("COP023", LIEF::assembly::mips::REG::COP023) + .value("COP024", LIEF::assembly::mips::REG::COP024) + .value("COP025", LIEF::assembly::mips::REG::COP025) + .value("COP026", LIEF::assembly::mips::REG::COP026) + .value("COP027", LIEF::assembly::mips::REG::COP027) + .value("COP028", LIEF::assembly::mips::REG::COP028) + .value("COP029", LIEF::assembly::mips::REG::COP029) + .value("COP030", LIEF::assembly::mips::REG::COP030) + .value("COP031", LIEF::assembly::mips::REG::COP031) + .value("COP210", LIEF::assembly::mips::REG::COP210) + .value("COP211", LIEF::assembly::mips::REG::COP211) + .value("COP212", LIEF::assembly::mips::REG::COP212) + .value("COP213", LIEF::assembly::mips::REG::COP213) + .value("COP214", LIEF::assembly::mips::REG::COP214) + .value("COP215", LIEF::assembly::mips::REG::COP215) + .value("COP216", LIEF::assembly::mips::REG::COP216) + .value("COP217", LIEF::assembly::mips::REG::COP217) + .value("COP218", LIEF::assembly::mips::REG::COP218) + .value("COP219", LIEF::assembly::mips::REG::COP219) + .value("COP220", LIEF::assembly::mips::REG::COP220) + .value("COP221", LIEF::assembly::mips::REG::COP221) + .value("COP222", LIEF::assembly::mips::REG::COP222) + .value("COP223", LIEF::assembly::mips::REG::COP223) + .value("COP224", LIEF::assembly::mips::REG::COP224) + .value("COP225", LIEF::assembly::mips::REG::COP225) + .value("COP226", LIEF::assembly::mips::REG::COP226) + .value("COP227", LIEF::assembly::mips::REG::COP227) + .value("COP228", LIEF::assembly::mips::REG::COP228) + .value("COP229", LIEF::assembly::mips::REG::COP229) + .value("COP230", LIEF::assembly::mips::REG::COP230) + .value("COP231", LIEF::assembly::mips::REG::COP231) + .value("COP310", LIEF::assembly::mips::REG::COP310) + .value("COP311", LIEF::assembly::mips::REG::COP311) + .value("COP312", LIEF::assembly::mips::REG::COP312) + .value("COP313", LIEF::assembly::mips::REG::COP313) + .value("COP314", LIEF::assembly::mips::REG::COP314) + .value("COP315", LIEF::assembly::mips::REG::COP315) + .value("COP316", LIEF::assembly::mips::REG::COP316) + .value("COP317", LIEF::assembly::mips::REG::COP317) + .value("COP318", LIEF::assembly::mips::REG::COP318) + .value("COP319", LIEF::assembly::mips::REG::COP319) + .value("COP320", LIEF::assembly::mips::REG::COP320) + .value("COP321", LIEF::assembly::mips::REG::COP321) + .value("COP322", LIEF::assembly::mips::REG::COP322) + .value("COP323", LIEF::assembly::mips::REG::COP323) + .value("COP324", LIEF::assembly::mips::REG::COP324) + .value("COP325", LIEF::assembly::mips::REG::COP325) + .value("COP326", LIEF::assembly::mips::REG::COP326) + .value("COP327", LIEF::assembly::mips::REG::COP327) + .value("COP328", LIEF::assembly::mips::REG::COP328) + .value("COP329", LIEF::assembly::mips::REG::COP329) + .value("COP330", LIEF::assembly::mips::REG::COP330) + .value("COP331", LIEF::assembly::mips::REG::COP331) + .value("D0", LIEF::assembly::mips::REG::D0) + .value("D1", LIEF::assembly::mips::REG::D1) + .value("D2", LIEF::assembly::mips::REG::D2) + .value("D3", LIEF::assembly::mips::REG::D3) + .value("D4", LIEF::assembly::mips::REG::D4) + .value("D5", LIEF::assembly::mips::REG::D5) + .value("D6", LIEF::assembly::mips::REG::D6) + .value("D7", LIEF::assembly::mips::REG::D7) + .value("D8", LIEF::assembly::mips::REG::D8) + .value("D9", LIEF::assembly::mips::REG::D9) + .value("D10", LIEF::assembly::mips::REG::D10) + .value("D11", LIEF::assembly::mips::REG::D11) + .value("D12", LIEF::assembly::mips::REG::D12) + .value("D13", LIEF::assembly::mips::REG::D13) + .value("D14", LIEF::assembly::mips::REG::D14) + .value("D15", LIEF::assembly::mips::REG::D15) + .value("DSPOutFlag20", LIEF::assembly::mips::REG::DSPOutFlag20) + .value("DSPOutFlag21", LIEF::assembly::mips::REG::DSPOutFlag21) + .value("DSPOutFlag22", LIEF::assembly::mips::REG::DSPOutFlag22) + .value("DSPOutFlag23", LIEF::assembly::mips::REG::DSPOutFlag23) + .value("F0", LIEF::assembly::mips::REG::F0) + .value("F1", LIEF::assembly::mips::REG::F1) + .value("F2", LIEF::assembly::mips::REG::F2) + .value("F3", LIEF::assembly::mips::REG::F3) + .value("F4", LIEF::assembly::mips::REG::F4) + .value("F5", LIEF::assembly::mips::REG::F5) + .value("F6", LIEF::assembly::mips::REG::F6) + .value("F7", LIEF::assembly::mips::REG::F7) + .value("F8", LIEF::assembly::mips::REG::F8) + .value("F9", LIEF::assembly::mips::REG::F9) + .value("F10", LIEF::assembly::mips::REG::F10) + .value("F11", LIEF::assembly::mips::REG::F11) + .value("F12", LIEF::assembly::mips::REG::F12) + .value("F13", LIEF::assembly::mips::REG::F13) + .value("F14", LIEF::assembly::mips::REG::F14) + .value("F15", LIEF::assembly::mips::REG::F15) + .value("F16", LIEF::assembly::mips::REG::F16) + .value("F17", LIEF::assembly::mips::REG::F17) + .value("F18", LIEF::assembly::mips::REG::F18) + .value("F19", LIEF::assembly::mips::REG::F19) + .value("F20", LIEF::assembly::mips::REG::F20) + .value("F21", LIEF::assembly::mips::REG::F21) + .value("F22", LIEF::assembly::mips::REG::F22) + .value("F23", LIEF::assembly::mips::REG::F23) + .value("F24", LIEF::assembly::mips::REG::F24) + .value("F25", LIEF::assembly::mips::REG::F25) + .value("F26", LIEF::assembly::mips::REG::F26) + .value("F27", LIEF::assembly::mips::REG::F27) + .value("F28", LIEF::assembly::mips::REG::F28) + .value("F29", LIEF::assembly::mips::REG::F29) + .value("F30", LIEF::assembly::mips::REG::F30) + .value("F31", LIEF::assembly::mips::REG::F31) + .value("FCC0", LIEF::assembly::mips::REG::FCC0) + .value("FCC1", LIEF::assembly::mips::REG::FCC1) + .value("FCC2", LIEF::assembly::mips::REG::FCC2) + .value("FCC3", LIEF::assembly::mips::REG::FCC3) + .value("FCC4", LIEF::assembly::mips::REG::FCC4) + .value("FCC5", LIEF::assembly::mips::REG::FCC5) + .value("FCC6", LIEF::assembly::mips::REG::FCC6) + .value("FCC7", LIEF::assembly::mips::REG::FCC7) + .value("FCR0", LIEF::assembly::mips::REG::FCR0) + .value("FCR1", LIEF::assembly::mips::REG::FCR1) + .value("FCR2", LIEF::assembly::mips::REG::FCR2) + .value("FCR3", LIEF::assembly::mips::REG::FCR3) + .value("FCR4", LIEF::assembly::mips::REG::FCR4) + .value("FCR5", LIEF::assembly::mips::REG::FCR5) + .value("FCR6", LIEF::assembly::mips::REG::FCR6) + .value("FCR7", LIEF::assembly::mips::REG::FCR7) + .value("FCR8", LIEF::assembly::mips::REG::FCR8) + .value("FCR9", LIEF::assembly::mips::REG::FCR9) + .value("FCR10", LIEF::assembly::mips::REG::FCR10) + .value("FCR11", LIEF::assembly::mips::REG::FCR11) + .value("FCR12", LIEF::assembly::mips::REG::FCR12) + .value("FCR13", LIEF::assembly::mips::REG::FCR13) + .value("FCR14", LIEF::assembly::mips::REG::FCR14) + .value("FCR15", LIEF::assembly::mips::REG::FCR15) + .value("FCR16", LIEF::assembly::mips::REG::FCR16) + .value("FCR17", LIEF::assembly::mips::REG::FCR17) + .value("FCR18", LIEF::assembly::mips::REG::FCR18) + .value("FCR19", LIEF::assembly::mips::REG::FCR19) + .value("FCR20", LIEF::assembly::mips::REG::FCR20) + .value("FCR21", LIEF::assembly::mips::REG::FCR21) + .value("FCR22", LIEF::assembly::mips::REG::FCR22) + .value("FCR23", LIEF::assembly::mips::REG::FCR23) + .value("FCR24", LIEF::assembly::mips::REG::FCR24) + .value("FCR25", LIEF::assembly::mips::REG::FCR25) + .value("FCR26", LIEF::assembly::mips::REG::FCR26) + .value("FCR27", LIEF::assembly::mips::REG::FCR27) + .value("FCR28", LIEF::assembly::mips::REG::FCR28) + .value("FCR29", LIEF::assembly::mips::REG::FCR29) + .value("FCR30", LIEF::assembly::mips::REG::FCR30) + .value("FCR31", LIEF::assembly::mips::REG::FCR31) + .value("FP_64", LIEF::assembly::mips::REG::FP_64) + .value("F_HI0", LIEF::assembly::mips::REG::F_HI0) + .value("F_HI1", LIEF::assembly::mips::REG::F_HI1) + .value("F_HI2", LIEF::assembly::mips::REG::F_HI2) + .value("F_HI3", LIEF::assembly::mips::REG::F_HI3) + .value("F_HI4", LIEF::assembly::mips::REG::F_HI4) + .value("F_HI5", LIEF::assembly::mips::REG::F_HI5) + .value("F_HI6", LIEF::assembly::mips::REG::F_HI6) + .value("F_HI7", LIEF::assembly::mips::REG::F_HI7) + .value("F_HI8", LIEF::assembly::mips::REG::F_HI8) + .value("F_HI9", LIEF::assembly::mips::REG::F_HI9) + .value("F_HI10", LIEF::assembly::mips::REG::F_HI10) + .value("F_HI11", LIEF::assembly::mips::REG::F_HI11) + .value("F_HI12", LIEF::assembly::mips::REG::F_HI12) + .value("F_HI13", LIEF::assembly::mips::REG::F_HI13) + .value("F_HI14", LIEF::assembly::mips::REG::F_HI14) + .value("F_HI15", LIEF::assembly::mips::REG::F_HI15) + .value("F_HI16", LIEF::assembly::mips::REG::F_HI16) + .value("F_HI17", LIEF::assembly::mips::REG::F_HI17) + .value("F_HI18", LIEF::assembly::mips::REG::F_HI18) + .value("F_HI19", LIEF::assembly::mips::REG::F_HI19) + .value("F_HI20", LIEF::assembly::mips::REG::F_HI20) + .value("F_HI21", LIEF::assembly::mips::REG::F_HI21) + .value("F_HI22", LIEF::assembly::mips::REG::F_HI22) + .value("F_HI23", LIEF::assembly::mips::REG::F_HI23) + .value("F_HI24", LIEF::assembly::mips::REG::F_HI24) + .value("F_HI25", LIEF::assembly::mips::REG::F_HI25) + .value("F_HI26", LIEF::assembly::mips::REG::F_HI26) + .value("F_HI27", LIEF::assembly::mips::REG::F_HI27) + .value("F_HI28", LIEF::assembly::mips::REG::F_HI28) + .value("F_HI29", LIEF::assembly::mips::REG::F_HI29) + .value("F_HI30", LIEF::assembly::mips::REG::F_HI30) + .value("F_HI31", LIEF::assembly::mips::REG::F_HI31) + .value("GP_64", LIEF::assembly::mips::REG::GP_64) + .value("HI0", LIEF::assembly::mips::REG::HI0) + .value("HI1", LIEF::assembly::mips::REG::HI1) + .value("HI2", LIEF::assembly::mips::REG::HI2) + .value("HI3", LIEF::assembly::mips::REG::HI3) + .value("HWR0", LIEF::assembly::mips::REG::HWR0) + .value("HWR1", LIEF::assembly::mips::REG::HWR1) + .value("HWR2", LIEF::assembly::mips::REG::HWR2) + .value("HWR3", LIEF::assembly::mips::REG::HWR3) + .value("HWR4", LIEF::assembly::mips::REG::HWR4) + .value("HWR5", LIEF::assembly::mips::REG::HWR5) + .value("HWR6", LIEF::assembly::mips::REG::HWR6) + .value("HWR7", LIEF::assembly::mips::REG::HWR7) + .value("HWR8", LIEF::assembly::mips::REG::HWR8) + .value("HWR9", LIEF::assembly::mips::REG::HWR9) + .value("HWR10", LIEF::assembly::mips::REG::HWR10) + .value("HWR11", LIEF::assembly::mips::REG::HWR11) + .value("HWR12", LIEF::assembly::mips::REG::HWR12) + .value("HWR13", LIEF::assembly::mips::REG::HWR13) + .value("HWR14", LIEF::assembly::mips::REG::HWR14) + .value("HWR15", LIEF::assembly::mips::REG::HWR15) + .value("HWR16", LIEF::assembly::mips::REG::HWR16) + .value("HWR17", LIEF::assembly::mips::REG::HWR17) + .value("HWR18", LIEF::assembly::mips::REG::HWR18) + .value("HWR19", LIEF::assembly::mips::REG::HWR19) + .value("HWR20", LIEF::assembly::mips::REG::HWR20) + .value("HWR21", LIEF::assembly::mips::REG::HWR21) + .value("HWR22", LIEF::assembly::mips::REG::HWR22) + .value("HWR23", LIEF::assembly::mips::REG::HWR23) + .value("HWR24", LIEF::assembly::mips::REG::HWR24) + .value("HWR25", LIEF::assembly::mips::REG::HWR25) + .value("HWR26", LIEF::assembly::mips::REG::HWR26) + .value("HWR27", LIEF::assembly::mips::REG::HWR27) + .value("HWR28", LIEF::assembly::mips::REG::HWR28) + .value("HWR29", LIEF::assembly::mips::REG::HWR29) + .value("HWR30", LIEF::assembly::mips::REG::HWR30) + .value("HWR31", LIEF::assembly::mips::REG::HWR31) + .value("K0", LIEF::assembly::mips::REG::K0) + .value("K1", LIEF::assembly::mips::REG::K1) + .value("LO0", LIEF::assembly::mips::REG::LO0) + .value("LO1", LIEF::assembly::mips::REG::LO1) + .value("LO2", LIEF::assembly::mips::REG::LO2) + .value("LO3", LIEF::assembly::mips::REG::LO3) + .value("MPL0", LIEF::assembly::mips::REG::MPL0) + .value("MPL1", LIEF::assembly::mips::REG::MPL1) + .value("MPL2", LIEF::assembly::mips::REG::MPL2) + .value("MSA8", LIEF::assembly::mips::REG::MSA8) + .value("MSA9", LIEF::assembly::mips::REG::MSA9); + reg.value("MSA10", LIEF::assembly::mips::REG::MSA10) + .value("MSA11", LIEF::assembly::mips::REG::MSA11) + .value("MSA12", LIEF::assembly::mips::REG::MSA12) + .value("MSA13", LIEF::assembly::mips::REG::MSA13) + .value("MSA14", LIEF::assembly::mips::REG::MSA14) + .value("MSA15", LIEF::assembly::mips::REG::MSA15) + .value("MSA16", LIEF::assembly::mips::REG::MSA16) + .value("MSA17", LIEF::assembly::mips::REG::MSA17) + .value("MSA18", LIEF::assembly::mips::REG::MSA18) + .value("MSA19", LIEF::assembly::mips::REG::MSA19) + .value("MSA20", LIEF::assembly::mips::REG::MSA20) + .value("MSA21", LIEF::assembly::mips::REG::MSA21) + .value("MSA22", LIEF::assembly::mips::REG::MSA22) + .value("MSA23", LIEF::assembly::mips::REG::MSA23) + .value("MSA24", LIEF::assembly::mips::REG::MSA24) + .value("MSA25", LIEF::assembly::mips::REG::MSA25) + .value("MSA26", LIEF::assembly::mips::REG::MSA26) + .value("MSA27", LIEF::assembly::mips::REG::MSA27) + .value("MSA28", LIEF::assembly::mips::REG::MSA28) + .value("MSA29", LIEF::assembly::mips::REG::MSA29) + .value("MSA30", LIEF::assembly::mips::REG::MSA30) + .value("MSA31", LIEF::assembly::mips::REG::MSA31) + .value("P0", LIEF::assembly::mips::REG::P0) + .value("P1", LIEF::assembly::mips::REG::P1) + .value("P2", LIEF::assembly::mips::REG::P2) + .value("RA_64", LIEF::assembly::mips::REG::RA_64) + .value("S0", LIEF::assembly::mips::REG::S0) + .value("S1", LIEF::assembly::mips::REG::S1) + .value("S2", LIEF::assembly::mips::REG::S2) + .value("S3", LIEF::assembly::mips::REG::S3) + .value("S4", LIEF::assembly::mips::REG::S4) + .value("S5", LIEF::assembly::mips::REG::S5) + .value("S6", LIEF::assembly::mips::REG::S6) + .value("S7", LIEF::assembly::mips::REG::S7) + .value("SP_64", LIEF::assembly::mips::REG::SP_64) + .value("T0", LIEF::assembly::mips::REG::T0) + .value("T1", LIEF::assembly::mips::REG::T1) + .value("T2", LIEF::assembly::mips::REG::T2) + .value("T3", LIEF::assembly::mips::REG::T3) + .value("T4", LIEF::assembly::mips::REG::T4) + .value("T5", LIEF::assembly::mips::REG::T5) + .value("T6", LIEF::assembly::mips::REG::T6) + .value("T7", LIEF::assembly::mips::REG::T7) + .value("T8", LIEF::assembly::mips::REG::T8) + .value("T9", LIEF::assembly::mips::REG::T9) + .value("V0", LIEF::assembly::mips::REG::V0) + .value("V1", LIEF::assembly::mips::REG::V1) + .value("W0", LIEF::assembly::mips::REG::W0) + .value("W1", LIEF::assembly::mips::REG::W1) + .value("W2", LIEF::assembly::mips::REG::W2) + .value("W3", LIEF::assembly::mips::REG::W3) + .value("W4", LIEF::assembly::mips::REG::W4) + .value("W5", LIEF::assembly::mips::REG::W5) + .value("W6", LIEF::assembly::mips::REG::W6) + .value("W7", LIEF::assembly::mips::REG::W7) + .value("W8", LIEF::assembly::mips::REG::W8) + .value("W9", LIEF::assembly::mips::REG::W9) + .value("W10", LIEF::assembly::mips::REG::W10) + .value("W11", LIEF::assembly::mips::REG::W11) + .value("W12", LIEF::assembly::mips::REG::W12) + .value("W13", LIEF::assembly::mips::REG::W13) + .value("W14", LIEF::assembly::mips::REG::W14) + .value("W15", LIEF::assembly::mips::REG::W15) + .value("W16", LIEF::assembly::mips::REG::W16) + .value("W17", LIEF::assembly::mips::REG::W17) + .value("W18", LIEF::assembly::mips::REG::W18) + .value("W19", LIEF::assembly::mips::REG::W19) + .value("W20", LIEF::assembly::mips::REG::W20) + .value("W21", LIEF::assembly::mips::REG::W21) + .value("W22", LIEF::assembly::mips::REG::W22) + .value("W23", LIEF::assembly::mips::REG::W23) + .value("W24", LIEF::assembly::mips::REG::W24) + .value("W25", LIEF::assembly::mips::REG::W25) + .value("W26", LIEF::assembly::mips::REG::W26) + .value("W27", LIEF::assembly::mips::REG::W27) + .value("W28", LIEF::assembly::mips::REG::W28) + .value("W29", LIEF::assembly::mips::REG::W29) + .value("W30", LIEF::assembly::mips::REG::W30) + .value("W31", LIEF::assembly::mips::REG::W31) + .value("ZERO_64", LIEF::assembly::mips::REG::ZERO_64) + .value("A0_64", LIEF::assembly::mips::REG::A0_64) + .value("A1_64", LIEF::assembly::mips::REG::A1_64) + .value("A2_64", LIEF::assembly::mips::REG::A2_64) + .value("A3_64", LIEF::assembly::mips::REG::A3_64) + .value("AC0_64", LIEF::assembly::mips::REG::AC0_64) + .value("D0_64", LIEF::assembly::mips::REG::D0_64) + .value("D1_64", LIEF::assembly::mips::REG::D1_64) + .value("D2_64", LIEF::assembly::mips::REG::D2_64) + .value("D3_64", LIEF::assembly::mips::REG::D3_64) + .value("D4_64", LIEF::assembly::mips::REG::D4_64) + .value("D5_64", LIEF::assembly::mips::REG::D5_64) + .value("D6_64", LIEF::assembly::mips::REG::D6_64) + .value("D7_64", LIEF::assembly::mips::REG::D7_64) + .value("D8_64", LIEF::assembly::mips::REG::D8_64) + .value("D9_64", LIEF::assembly::mips::REG::D9_64) + .value("D10_64", LIEF::assembly::mips::REG::D10_64) + .value("D11_64", LIEF::assembly::mips::REG::D11_64) + .value("D12_64", LIEF::assembly::mips::REG::D12_64) + .value("D13_64", LIEF::assembly::mips::REG::D13_64) + .value("D14_64", LIEF::assembly::mips::REG::D14_64) + .value("D15_64", LIEF::assembly::mips::REG::D15_64) + .value("D16_64", LIEF::assembly::mips::REG::D16_64) + .value("D17_64", LIEF::assembly::mips::REG::D17_64) + .value("D18_64", LIEF::assembly::mips::REG::D18_64) + .value("D19_64", LIEF::assembly::mips::REG::D19_64) + .value("D20_64", LIEF::assembly::mips::REG::D20_64) + .value("D21_64", LIEF::assembly::mips::REG::D21_64) + .value("D22_64", LIEF::assembly::mips::REG::D22_64) + .value("D23_64", LIEF::assembly::mips::REG::D23_64) + .value("D24_64", LIEF::assembly::mips::REG::D24_64) + .value("D25_64", LIEF::assembly::mips::REG::D25_64) + .value("D26_64", LIEF::assembly::mips::REG::D26_64) + .value("D27_64", LIEF::assembly::mips::REG::D27_64) + .value("D28_64", LIEF::assembly::mips::REG::D28_64) + .value("D29_64", LIEF::assembly::mips::REG::D29_64) + .value("D30_64", LIEF::assembly::mips::REG::D30_64) + .value("D31_64", LIEF::assembly::mips::REG::D31_64) + .value("DSPOutFlag16_19", LIEF::assembly::mips::REG::DSPOutFlag16_19) + .value("HI0_64", LIEF::assembly::mips::REG::HI0_64) + .value("K0_64", LIEF::assembly::mips::REG::K0_64) + .value("K1_64", LIEF::assembly::mips::REG::K1_64) + .value("LO0_64", LIEF::assembly::mips::REG::LO0_64) + .value("S0_64", LIEF::assembly::mips::REG::S0_64) + .value("S1_64", LIEF::assembly::mips::REG::S1_64) + .value("S2_64", LIEF::assembly::mips::REG::S2_64) + .value("S3_64", LIEF::assembly::mips::REG::S3_64) + .value("S4_64", LIEF::assembly::mips::REG::S4_64) + .value("S5_64", LIEF::assembly::mips::REG::S5_64) + .value("S6_64", LIEF::assembly::mips::REG::S6_64) + .value("S7_64", LIEF::assembly::mips::REG::S7_64) + .value("T0_64", LIEF::assembly::mips::REG::T0_64) + .value("T1_64", LIEF::assembly::mips::REG::T1_64) + .value("T2_64", LIEF::assembly::mips::REG::T2_64) + .value("T3_64", LIEF::assembly::mips::REG::T3_64) + .value("T4_64", LIEF::assembly::mips::REG::T4_64) + .value("T5_64", LIEF::assembly::mips::REG::T5_64) + .value("T6_64", LIEF::assembly::mips::REG::T6_64) + .value("T7_64", LIEF::assembly::mips::REG::T7_64) + .value("T8_64", LIEF::assembly::mips::REG::T8_64) + .value("T9_64", LIEF::assembly::mips::REG::T9_64) + .value("V0_64", LIEF::assembly::mips::REG::V0_64) + .value("V1_64", LIEF::assembly::mips::REG::V1_64) + .value("NUM_TARGET_REGS", LIEF::assembly::mips::REG::NUM_TARGET_REGS) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/CMakeLists.txt b/vendor/lief/api/python/src/asm/powerpc/CMakeLists.txt new file mode 100644 index 0000000..c5e4e70 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyOperand.cpp + pyRegister.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/powerpc/init.cpp b/vendor/lief/api/python/src/asm/powerpc/init.cpp new file mode 100644 index 0000000..7c735fe --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/init.cpp @@ -0,0 +1,18 @@ +#include "asm/powerpc/init.hpp" +namespace LIEF::assembly::powerpc { +enum class OPCODE; +enum class REG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::powerpc::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("powerpc"); + + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/init.hpp b/vendor/lief/api/python/src/asm/powerpc/init.hpp new file mode 100644 index 0000000..ffa3eed --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_POWERPC_INIT_H +#define PY_LIEF_ASM_POWERPC_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::powerpc::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/powerpc/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/powerpc/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/powerpc/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/powerpc/operands/pyImmediate.cpp new file mode 100644 index 0000000..f7e8f57 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/operands/pyImmediate.cpp @@ -0,0 +1,29 @@ +#include "asm/powerpc/init.hpp" +#include "LIEF/asm/powerpc/operands/Immediate.hpp" + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + + For instance: + + .. code-block:: text + + li 3, 8 + | + +---> Immediate(8) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/powerpc/operands/pyMemory.cpp new file mode 100644 index 0000000..0612b79 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/operands/pyMemory.cpp @@ -0,0 +1,78 @@ +#include + +#include "asm/powerpc/init.hpp" +#include "LIEF/asm/powerpc/operands/Memory.hpp" + +namespace nanobind::detail { +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::assembly::powerpc::operands::Memory::offset_t, + const_name("Optional[Union[lief.assembly.powerpc.REG, int]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::assembly::powerpc::operands::Memory::offset_t val, + rv_policy, cleanup_list *) noexcept + { + using namespace LIEF::assembly::powerpc; + using namespace LIEF::assembly::powerpc::operands; + switch (val.type) { + case Memory::offset_t::TYPE::REG: + return make_caster::from_cpp(val.reg, rv_policy::copy, + /*cleanup_list*/nullptr); + + case Memory::offset_t::TYPE::DISP: + return make_caster::from_cpp(val.displacement, rv_policy::copy, + /*cleanup_list*/nullptr); + case Memory::offset_t::TYPE::NONE: + return nb::none(); + } + return nb::none(); + } +}; +} + + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + .. code-block:: text + + lwz 3, 8(4) lwzx 3, 4, 5 + | | | | | + +------+ +---+ +------+ | +---+ + | | | | | + v v v v v + Disp Base Reg Base Index + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("base", "offset"); + + obj + .def_prop_ro("base", &operands::Memory::base, + R"doc( + The base register. + + For ``lwz 3, 8(4)`` it would return ``4``. + )doc"_doc + ) + .def_prop_ro("offset", &operands::Memory::offset, + R"doc( + The addressing offset. + + It can be either: + + - An index register (e.g. ``lwzx 3, 4, 5``) + - A displacement (e.g. ``lwz 3, 8(4)``) + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/powerpc/operands/pyPCRelative.cpp new file mode 100644 index 0000000..45d8ecf --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/operands/pyPCRelative.cpp @@ -0,0 +1,30 @@ +#include "asm/powerpc/init.hpp" +#include "LIEF/asm/powerpc/operands/PCRelative.hpp" + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a PC-relative operand. + + .. code-block:: text + + bl 0x100 + | + v + PC Relative operand + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &powerpc::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``pc`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/powerpc/operands/pyRegister.cpp new file mode 100644 index 0000000..786f33d --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/operands/pyRegister.cpp @@ -0,0 +1,33 @@ +#include "asm/powerpc/init.hpp" +#include "LIEF/asm/powerpc/operands/Register.hpp" + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + For instance: + + .. code-block:: text + + add 3, 4, 5 + | | | + | | +---------> Register(5) + | +------------> Register(4) + +---------------> Register(3) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &powerpc::operands::Register::value, + R"doc( + The effective :class:`lief.assembly.powerpc.REG` wrapped by this operand + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/pyInstruction.cpp b/vendor/lief/api/python/src/asm/powerpc/pyInstruction.cpp new file mode 100644 index 0000000..eb16cf7 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/pyInstruction.cpp @@ -0,0 +1,34 @@ +#include "LIEF/asm/powerpc/Instruction.hpp" +#include "LIEF/asm/powerpc/Operand.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include "asm/powerpc/init.hpp" + +#include + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents a PowerPC (ppc64/ppc32) instruction)doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("operands", [] (const powerpc::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/pyOpcode.cpp b/vendor/lief/api/python/src/asm/powerpc/pyOpcode.cpp new file mode 100644 index 0000000..a811f65 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/pyOpcode.cpp @@ -0,0 +1,3008 @@ +#include "asm/powerpc/init.hpp" + +#include "LIEF/asm/powerpc/opcodes.hpp" + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::powerpc::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::powerpc::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::powerpc::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::powerpc::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::powerpc::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::powerpc::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::powerpc::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::powerpc::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::powerpc::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::powerpc::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::powerpc::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::powerpc::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::powerpc::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::powerpc::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::powerpc::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::powerpc::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::powerpc::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::powerpc::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::powerpc::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::powerpc::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::powerpc::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::powerpc::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::powerpc::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::powerpc::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::powerpc::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::powerpc::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::powerpc::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::powerpc::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::powerpc::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::powerpc::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::powerpc::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::powerpc::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::powerpc::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::powerpc::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::powerpc::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::powerpc::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::powerpc::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::powerpc::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::powerpc::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::powerpc::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::powerpc::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::powerpc::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::powerpc::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::powerpc::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::powerpc::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::powerpc::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::powerpc::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::powerpc::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::powerpc::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::powerpc::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::powerpc::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::powerpc::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::powerpc::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::powerpc::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::powerpc::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::powerpc::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::powerpc::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::powerpc::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::powerpc::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::powerpc::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::powerpc::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::powerpc::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::powerpc::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::powerpc::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::powerpc::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::powerpc::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::powerpc::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::powerpc::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::powerpc::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::powerpc::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::powerpc::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::powerpc::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::powerpc::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::powerpc::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::powerpc::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::powerpc::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::powerpc::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::powerpc::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::powerpc::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::powerpc::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::powerpc::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::powerpc::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::powerpc::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::powerpc::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::powerpc::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::powerpc::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::powerpc::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::powerpc::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::powerpc::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::powerpc::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::powerpc::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::powerpc::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::powerpc::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::powerpc::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::powerpc::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::powerpc::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::powerpc::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::powerpc::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::powerpc::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::powerpc::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::powerpc::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::powerpc::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::powerpc::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::powerpc::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::powerpc::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::powerpc::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::powerpc::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::powerpc::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::powerpc::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::powerpc::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::powerpc::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::powerpc::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::powerpc::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::powerpc::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::powerpc::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::powerpc::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::powerpc::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::powerpc::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::powerpc::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::powerpc::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::powerpc::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::powerpc::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::powerpc::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::powerpc::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::powerpc::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::powerpc::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::powerpc::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::powerpc::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::powerpc::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::powerpc::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::powerpc::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::powerpc::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::powerpc::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::powerpc::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::powerpc::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::powerpc::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::powerpc::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::powerpc::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::powerpc::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::powerpc::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::powerpc::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::powerpc::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::powerpc::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::powerpc::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::powerpc::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::powerpc::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::powerpc::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::powerpc::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::powerpc::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::powerpc::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::powerpc::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::powerpc::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::powerpc::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::powerpc::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::powerpc::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::powerpc::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::powerpc::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::powerpc::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::powerpc::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::powerpc::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::powerpc::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::powerpc::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::powerpc::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::powerpc::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::powerpc::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::powerpc::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::powerpc::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::powerpc::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::powerpc::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::powerpc::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::powerpc::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::powerpc::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::powerpc::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::powerpc::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::powerpc::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::powerpc::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::powerpc::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::powerpc::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::powerpc::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::powerpc::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::powerpc::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::powerpc::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::powerpc::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::powerpc::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::powerpc::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::powerpc::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::powerpc::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::powerpc::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::powerpc::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::powerpc::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::powerpc::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::powerpc::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::powerpc::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::powerpc::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::powerpc::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::powerpc::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::powerpc::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::powerpc::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::powerpc::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::powerpc::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::powerpc::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::powerpc::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::powerpc::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::powerpc::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::powerpc::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::powerpc::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::powerpc::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::powerpc::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::powerpc::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::powerpc::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::powerpc::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::powerpc::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::powerpc::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::powerpc::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::powerpc::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::powerpc::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::powerpc::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::powerpc::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::powerpc::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::powerpc::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::powerpc::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::powerpc::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::powerpc::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::powerpc::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::powerpc::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::powerpc::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::powerpc::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::powerpc::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::powerpc::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::powerpc::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::powerpc::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::powerpc::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::powerpc::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::powerpc::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::powerpc::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::powerpc::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::powerpc::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::powerpc::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::powerpc::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::powerpc::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::powerpc::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::powerpc::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::powerpc::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::powerpc::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::powerpc::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::powerpc::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::powerpc::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::powerpc::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::powerpc::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::powerpc::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::powerpc::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::powerpc::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::powerpc::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::powerpc::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::powerpc::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::powerpc::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::powerpc::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::powerpc::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::powerpc::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::powerpc::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::powerpc::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::powerpc::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::powerpc::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::powerpc::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::powerpc::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::powerpc::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::powerpc::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::powerpc::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::powerpc::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::powerpc::OPCODE::G_UBFX) + .value("ATOMIC_CMP_SWAP_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I128) + .value("ATOMIC_LOAD_ADD_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I128) + .value("ATOMIC_LOAD_AND_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I128) + .value("ATOMIC_LOAD_NAND_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I128) + .value("ATOMIC_LOAD_OR_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I128) + .value("ATOMIC_LOAD_SUB_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I128) + .value("ATOMIC_LOAD_XOR_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I128) + .value("ATOMIC_SWAP_I128", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I128) + .value("BUILD_QUADWORD", LIEF::assembly::powerpc::OPCODE::BUILD_QUADWORD) + .value("BUILD_UACC", LIEF::assembly::powerpc::OPCODE::BUILD_UACC) + .value("CFENCE", LIEF::assembly::powerpc::OPCODE::CFENCE) + .value("CFENCE8", LIEF::assembly::powerpc::OPCODE::CFENCE8) + .value("CLRLSLDI", LIEF::assembly::powerpc::OPCODE::CLRLSLDI) + .value("CLRLSLDI_rec", LIEF::assembly::powerpc::OPCODE::CLRLSLDI_rec) + .value("CLRLSLWI", LIEF::assembly::powerpc::OPCODE::CLRLSLWI) + .value("CLRLSLWI_rec", LIEF::assembly::powerpc::OPCODE::CLRLSLWI_rec) + .value("CLRRDI", LIEF::assembly::powerpc::OPCODE::CLRRDI) + .value("CLRRDI_rec", LIEF::assembly::powerpc::OPCODE::CLRRDI_rec) + .value("CLRRWI", LIEF::assembly::powerpc::OPCODE::CLRRWI) + .value("CLRRWI_rec", LIEF::assembly::powerpc::OPCODE::CLRRWI_rec) + .value("DCBFL", LIEF::assembly::powerpc::OPCODE::DCBFL) + .value("DCBFLP", LIEF::assembly::powerpc::OPCODE::DCBFLP) + .value("DCBFPS", LIEF::assembly::powerpc::OPCODE::DCBFPS) + .value("DCBFx", LIEF::assembly::powerpc::OPCODE::DCBFx) + .value("DCBSTPS", LIEF::assembly::powerpc::OPCODE::DCBSTPS) + .value("DCBTCT", LIEF::assembly::powerpc::OPCODE::DCBTCT) + .value("DCBTDS", LIEF::assembly::powerpc::OPCODE::DCBTDS) + .value("DCBTSTCT", LIEF::assembly::powerpc::OPCODE::DCBTSTCT) + .value("DCBTSTDS", LIEF::assembly::powerpc::OPCODE::DCBTSTDS) + .value("DCBTSTT", LIEF::assembly::powerpc::OPCODE::DCBTSTT) + .value("DCBTSTx", LIEF::assembly::powerpc::OPCODE::DCBTSTx) + .value("DCBTT", LIEF::assembly::powerpc::OPCODE::DCBTT) + .value("DCBTx", LIEF::assembly::powerpc::OPCODE::DCBTx) + .value("DFLOADf32", LIEF::assembly::powerpc::OPCODE::DFLOADf32) + .value("DFLOADf64", LIEF::assembly::powerpc::OPCODE::DFLOADf64) + .value("DFSTOREf32", LIEF::assembly::powerpc::OPCODE::DFSTOREf32) + .value("DFSTOREf64", LIEF::assembly::powerpc::OPCODE::DFSTOREf64) + .value("EXTLDI", LIEF::assembly::powerpc::OPCODE::EXTLDI) + .value("EXTLDI_rec", LIEF::assembly::powerpc::OPCODE::EXTLDI_rec) + .value("EXTLWI", LIEF::assembly::powerpc::OPCODE::EXTLWI) + .value("EXTLWI_rec", LIEF::assembly::powerpc::OPCODE::EXTLWI_rec) + .value("EXTRDI", LIEF::assembly::powerpc::OPCODE::EXTRDI) + .value("EXTRDI_rec", LIEF::assembly::powerpc::OPCODE::EXTRDI_rec) + .value("EXTRWI", LIEF::assembly::powerpc::OPCODE::EXTRWI) + .value("EXTRWI_rec", LIEF::assembly::powerpc::OPCODE::EXTRWI_rec) + .value("INSLWI", LIEF::assembly::powerpc::OPCODE::INSLWI) + .value("INSLWI_rec", LIEF::assembly::powerpc::OPCODE::INSLWI_rec) + .value("INSRDI", LIEF::assembly::powerpc::OPCODE::INSRDI) + .value("INSRDI_rec", LIEF::assembly::powerpc::OPCODE::INSRDI_rec) + .value("INSRWI", LIEF::assembly::powerpc::OPCODE::INSRWI) + .value("INSRWI_rec", LIEF::assembly::powerpc::OPCODE::INSRWI_rec) + .value("KILL_PAIR", LIEF::assembly::powerpc::OPCODE::KILL_PAIR) + .value("LAx", LIEF::assembly::powerpc::OPCODE::LAx) + .value("LIWAX", LIEF::assembly::powerpc::OPCODE::LIWAX) + .value("LIWZX", LIEF::assembly::powerpc::OPCODE::LIWZX) + .value("PPCLdFixedAddr", LIEF::assembly::powerpc::OPCODE::PPCLdFixedAddr) + .value("PSUBI", LIEF::assembly::powerpc::OPCODE::PSUBI) + .value("RLWIMIbm", LIEF::assembly::powerpc::OPCODE::RLWIMIbm) + .value("RLWIMIbm_rec", LIEF::assembly::powerpc::OPCODE::RLWIMIbm_rec) + .value("RLWINMbm", LIEF::assembly::powerpc::OPCODE::RLWINMbm) + .value("RLWINMbm_rec", LIEF::assembly::powerpc::OPCODE::RLWINMbm_rec) + .value("RLWNMbm", LIEF::assembly::powerpc::OPCODE::RLWNMbm) + .value("RLWNMbm_rec", LIEF::assembly::powerpc::OPCODE::RLWNMbm_rec) + .value("ROTRDI", LIEF::assembly::powerpc::OPCODE::ROTRDI) + .value("ROTRDI_rec", LIEF::assembly::powerpc::OPCODE::ROTRDI_rec) + .value("ROTRWI", LIEF::assembly::powerpc::OPCODE::ROTRWI) + .value("ROTRWI_rec", LIEF::assembly::powerpc::OPCODE::ROTRWI_rec) + .value("SLDI", LIEF::assembly::powerpc::OPCODE::SLDI) + .value("SLDI_rec", LIEF::assembly::powerpc::OPCODE::SLDI_rec) + .value("SLWI", LIEF::assembly::powerpc::OPCODE::SLWI) + .value("SLWI_rec", LIEF::assembly::powerpc::OPCODE::SLWI_rec) + .value("SPILLTOVSR_LD", LIEF::assembly::powerpc::OPCODE::SPILLTOVSR_LD) + .value("SPILLTOVSR_LDX", LIEF::assembly::powerpc::OPCODE::SPILLTOVSR_LDX) + .value("SPILLTOVSR_ST", LIEF::assembly::powerpc::OPCODE::SPILLTOVSR_ST) + .value("SPILLTOVSR_STX", LIEF::assembly::powerpc::OPCODE::SPILLTOVSR_STX) + .value("SRDI", LIEF::assembly::powerpc::OPCODE::SRDI) + .value("SRDI_rec", LIEF::assembly::powerpc::OPCODE::SRDI_rec) + .value("SRWI", LIEF::assembly::powerpc::OPCODE::SRWI) + .value("SRWI_rec", LIEF::assembly::powerpc::OPCODE::SRWI_rec) + .value("STIWX", LIEF::assembly::powerpc::OPCODE::STIWX) + .value("SUBI", LIEF::assembly::powerpc::OPCODE::SUBI) + .value("SUBIC", LIEF::assembly::powerpc::OPCODE::SUBIC) + .value("SUBIC_rec", LIEF::assembly::powerpc::OPCODE::SUBIC_rec) + .value("SUBIS", LIEF::assembly::powerpc::OPCODE::SUBIS) + .value("SUBPCIS", LIEF::assembly::powerpc::OPCODE::SUBPCIS) + .value("XFLOADf32", LIEF::assembly::powerpc::OPCODE::XFLOADf32) + .value("XFLOADf64", LIEF::assembly::powerpc::OPCODE::XFLOADf64) + .value("XFSTOREf32", LIEF::assembly::powerpc::OPCODE::XFSTOREf32) + .value("XFSTOREf64", LIEF::assembly::powerpc::OPCODE::XFSTOREf64) + .value("ADD4", LIEF::assembly::powerpc::OPCODE::ADD4) + .value("ADD4O", LIEF::assembly::powerpc::OPCODE::ADD4O) + .value("ADD4O_rec", LIEF::assembly::powerpc::OPCODE::ADD4O_rec) + .value("ADD4TLS", LIEF::assembly::powerpc::OPCODE::ADD4TLS) + .value("ADD4_rec", LIEF::assembly::powerpc::OPCODE::ADD4_rec) + .value("ADD8", LIEF::assembly::powerpc::OPCODE::ADD8) + .value("ADD8O", LIEF::assembly::powerpc::OPCODE::ADD8O) + .value("ADD8O_rec", LIEF::assembly::powerpc::OPCODE::ADD8O_rec) + .value("ADD8TLS", LIEF::assembly::powerpc::OPCODE::ADD8TLS) + .value("ADD8TLS_", LIEF::assembly::powerpc::OPCODE::ADD8TLS_) + .value("ADD8_rec", LIEF::assembly::powerpc::OPCODE::ADD8_rec) + .value("ADDC", LIEF::assembly::powerpc::OPCODE::ADDC) + .value("ADDC8", LIEF::assembly::powerpc::OPCODE::ADDC8) + .value("ADDC8O", LIEF::assembly::powerpc::OPCODE::ADDC8O) + .value("ADDC8O_rec", LIEF::assembly::powerpc::OPCODE::ADDC8O_rec) + .value("ADDC8_rec", LIEF::assembly::powerpc::OPCODE::ADDC8_rec) + .value("ADDCO", LIEF::assembly::powerpc::OPCODE::ADDCO) + .value("ADDCO_rec", LIEF::assembly::powerpc::OPCODE::ADDCO_rec) + .value("ADDC_rec", LIEF::assembly::powerpc::OPCODE::ADDC_rec) + .value("ADDE", LIEF::assembly::powerpc::OPCODE::ADDE) + .value("ADDE8", LIEF::assembly::powerpc::OPCODE::ADDE8) + .value("ADDE8O", LIEF::assembly::powerpc::OPCODE::ADDE8O) + .value("ADDE8O_rec", LIEF::assembly::powerpc::OPCODE::ADDE8O_rec) + .value("ADDE8_rec", LIEF::assembly::powerpc::OPCODE::ADDE8_rec) + .value("ADDEO", LIEF::assembly::powerpc::OPCODE::ADDEO) + .value("ADDEO_rec", LIEF::assembly::powerpc::OPCODE::ADDEO_rec) + .value("ADDEX", LIEF::assembly::powerpc::OPCODE::ADDEX) + .value("ADDEX8", LIEF::assembly::powerpc::OPCODE::ADDEX8) + .value("ADDE_rec", LIEF::assembly::powerpc::OPCODE::ADDE_rec) + .value("ADDG6S", LIEF::assembly::powerpc::OPCODE::ADDG6S) + .value("ADDG6S8", LIEF::assembly::powerpc::OPCODE::ADDG6S8) + .value("ADDI", LIEF::assembly::powerpc::OPCODE::ADDI) + .value("ADDI8", LIEF::assembly::powerpc::OPCODE::ADDI8) + .value("ADDIC", LIEF::assembly::powerpc::OPCODE::ADDIC) + .value("ADDIC8", LIEF::assembly::powerpc::OPCODE::ADDIC8) + .value("ADDIC_rec", LIEF::assembly::powerpc::OPCODE::ADDIC_rec) + .value("ADDIS", LIEF::assembly::powerpc::OPCODE::ADDIS) + .value("ADDIS8", LIEF::assembly::powerpc::OPCODE::ADDIS8) + .value("ADDISdtprelHA", LIEF::assembly::powerpc::OPCODE::ADDISdtprelHA) + .value("ADDISdtprelHA32", LIEF::assembly::powerpc::OPCODE::ADDISdtprelHA32) + .value("ADDISgotTprelHA", LIEF::assembly::powerpc::OPCODE::ADDISgotTprelHA) + .value("ADDIStlsgdHA", LIEF::assembly::powerpc::OPCODE::ADDIStlsgdHA) + .value("ADDIStlsldHA", LIEF::assembly::powerpc::OPCODE::ADDIStlsldHA) + .value("ADDIStocHA", LIEF::assembly::powerpc::OPCODE::ADDIStocHA) + .value("ADDIStocHA8", LIEF::assembly::powerpc::OPCODE::ADDIStocHA8) + .value("ADDIdtprelL", LIEF::assembly::powerpc::OPCODE::ADDIdtprelL) + .value("ADDIdtprelL32", LIEF::assembly::powerpc::OPCODE::ADDIdtprelL32) + .value("ADDItlsgdL", LIEF::assembly::powerpc::OPCODE::ADDItlsgdL) + .value("ADDItlsgdL32", LIEF::assembly::powerpc::OPCODE::ADDItlsgdL32) + .value("ADDItlsgdLADDR", LIEF::assembly::powerpc::OPCODE::ADDItlsgdLADDR) + .value("ADDItlsgdLADDR32", LIEF::assembly::powerpc::OPCODE::ADDItlsgdLADDR32) + .value("ADDItlsldL", LIEF::assembly::powerpc::OPCODE::ADDItlsldL) + .value("ADDItlsldL32", LIEF::assembly::powerpc::OPCODE::ADDItlsldL32) + .value("ADDItlsldLADDR", LIEF::assembly::powerpc::OPCODE::ADDItlsldLADDR) + .value("ADDItlsldLADDR32", LIEF::assembly::powerpc::OPCODE::ADDItlsldLADDR32) + .value("ADDItoc", LIEF::assembly::powerpc::OPCODE::ADDItoc) + .value("ADDItoc8", LIEF::assembly::powerpc::OPCODE::ADDItoc8) + .value("ADDItocL", LIEF::assembly::powerpc::OPCODE::ADDItocL) + .value("ADDItocL8", LIEF::assembly::powerpc::OPCODE::ADDItocL8) + .value("ADDME", LIEF::assembly::powerpc::OPCODE::ADDME) + .value("ADDME8", LIEF::assembly::powerpc::OPCODE::ADDME8) + .value("ADDME8O", LIEF::assembly::powerpc::OPCODE::ADDME8O) + .value("ADDME8O_rec", LIEF::assembly::powerpc::OPCODE::ADDME8O_rec) + .value("ADDME8_rec", LIEF::assembly::powerpc::OPCODE::ADDME8_rec) + .value("ADDMEO", LIEF::assembly::powerpc::OPCODE::ADDMEO) + .value("ADDMEO_rec", LIEF::assembly::powerpc::OPCODE::ADDMEO_rec) + .value("ADDME_rec", LIEF::assembly::powerpc::OPCODE::ADDME_rec) + .value("ADDPCIS", LIEF::assembly::powerpc::OPCODE::ADDPCIS) + .value("ADDZE", LIEF::assembly::powerpc::OPCODE::ADDZE) + .value("ADDZE8", LIEF::assembly::powerpc::OPCODE::ADDZE8) + .value("ADDZE8O", LIEF::assembly::powerpc::OPCODE::ADDZE8O) + .value("ADDZE8O_rec", LIEF::assembly::powerpc::OPCODE::ADDZE8O_rec) + .value("ADDZE8_rec", LIEF::assembly::powerpc::OPCODE::ADDZE8_rec) + .value("ADDZEO", LIEF::assembly::powerpc::OPCODE::ADDZEO) + .value("ADDZEO_rec", LIEF::assembly::powerpc::OPCODE::ADDZEO_rec) + .value("ADDZE_rec", LIEF::assembly::powerpc::OPCODE::ADDZE_rec) + .value("ADJCALLSTACKDOWN", LIEF::assembly::powerpc::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::powerpc::OPCODE::ADJCALLSTACKUP) + .value("AND", LIEF::assembly::powerpc::OPCODE::AND) + .value("AND8", LIEF::assembly::powerpc::OPCODE::AND8) + .value("AND8_rec", LIEF::assembly::powerpc::OPCODE::AND8_rec) + .value("ANDC", LIEF::assembly::powerpc::OPCODE::ANDC) + .value("ANDC8", LIEF::assembly::powerpc::OPCODE::ANDC8) + .value("ANDC8_rec", LIEF::assembly::powerpc::OPCODE::ANDC8_rec) + .value("ANDC_rec", LIEF::assembly::powerpc::OPCODE::ANDC_rec) + .value("ANDI8_rec", LIEF::assembly::powerpc::OPCODE::ANDI8_rec) + .value("ANDIS8_rec", LIEF::assembly::powerpc::OPCODE::ANDIS8_rec) + .value("ANDIS_rec", LIEF::assembly::powerpc::OPCODE::ANDIS_rec) + .value("ANDI_rec", LIEF::assembly::powerpc::OPCODE::ANDI_rec) + .value("ANDI_rec_1_EQ_BIT", LIEF::assembly::powerpc::OPCODE::ANDI_rec_1_EQ_BIT) + .value("ANDI_rec_1_EQ_BIT8", LIEF::assembly::powerpc::OPCODE::ANDI_rec_1_EQ_BIT8) + .value("ANDI_rec_1_GT_BIT", LIEF::assembly::powerpc::OPCODE::ANDI_rec_1_GT_BIT) + .value("ANDI_rec_1_GT_BIT8", LIEF::assembly::powerpc::OPCODE::ANDI_rec_1_GT_BIT8) + .value("AND_rec", LIEF::assembly::powerpc::OPCODE::AND_rec) + .value("ATOMIC_CMP_SWAP_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I16) + .value("ATOMIC_CMP_SWAP_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I32) + .value("ATOMIC_CMP_SWAP_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I64) + .value("ATOMIC_CMP_SWAP_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I8) + .value("ATOMIC_LOAD_ADD_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I16) + .value("ATOMIC_LOAD_ADD_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I32) + .value("ATOMIC_LOAD_ADD_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I64) + .value("ATOMIC_LOAD_ADD_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I8) + .value("ATOMIC_LOAD_AND_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I16) + .value("ATOMIC_LOAD_AND_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I32) + .value("ATOMIC_LOAD_AND_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I64) + .value("ATOMIC_LOAD_AND_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I8) + .value("ATOMIC_LOAD_MAX_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I16) + .value("ATOMIC_LOAD_MAX_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I32) + .value("ATOMIC_LOAD_MAX_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I64) + .value("ATOMIC_LOAD_MAX_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I8) + .value("ATOMIC_LOAD_MIN_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I16) + .value("ATOMIC_LOAD_MIN_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I32) + .value("ATOMIC_LOAD_MIN_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I64) + .value("ATOMIC_LOAD_MIN_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I8) + .value("ATOMIC_LOAD_NAND_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I16) + .value("ATOMIC_LOAD_NAND_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I32) + .value("ATOMIC_LOAD_NAND_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I64) + .value("ATOMIC_LOAD_NAND_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I8) + .value("ATOMIC_LOAD_OR_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I16) + .value("ATOMIC_LOAD_OR_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I32) + .value("ATOMIC_LOAD_OR_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I64) + .value("ATOMIC_LOAD_OR_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I8) + .value("ATOMIC_LOAD_SUB_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I16) + .value("ATOMIC_LOAD_SUB_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I32) + .value("ATOMIC_LOAD_SUB_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I64) + .value("ATOMIC_LOAD_SUB_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I8) + .value("ATOMIC_LOAD_UMAX_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I16) + .value("ATOMIC_LOAD_UMAX_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I32) + .value("ATOMIC_LOAD_UMAX_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I64) + .value("ATOMIC_LOAD_UMAX_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I8) + .value("ATOMIC_LOAD_UMIN_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I16) + .value("ATOMIC_LOAD_UMIN_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I32) + .value("ATOMIC_LOAD_UMIN_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I64) + .value("ATOMIC_LOAD_UMIN_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I8) + .value("ATOMIC_LOAD_XOR_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I16) + .value("ATOMIC_LOAD_XOR_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I32) + .value("ATOMIC_LOAD_XOR_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I64) + .value("ATOMIC_LOAD_XOR_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I8) + .value("ATOMIC_SWAP_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I16) + .value("ATOMIC_SWAP_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I32) + .value("ATOMIC_SWAP_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I64) + .value("ATOMIC_SWAP_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I8) + .value("ATTN", LIEF::assembly::powerpc::OPCODE::ATTN) + .value("B", LIEF::assembly::powerpc::OPCODE::B) + .value("BA", LIEF::assembly::powerpc::OPCODE::BA) + .value("BC", LIEF::assembly::powerpc::OPCODE::BC) + .value("BCC", LIEF::assembly::powerpc::OPCODE::BCC) + .value("BCCA", LIEF::assembly::powerpc::OPCODE::BCCA) + .value("BCCCTR", LIEF::assembly::powerpc::OPCODE::BCCCTR) + .value("BCCCTR8", LIEF::assembly::powerpc::OPCODE::BCCCTR8) + .value("BCCCTRL", LIEF::assembly::powerpc::OPCODE::BCCCTRL) + .value("BCCCTRL8", LIEF::assembly::powerpc::OPCODE::BCCCTRL8) + .value("BCCL", LIEF::assembly::powerpc::OPCODE::BCCL) + .value("BCCLA", LIEF::assembly::powerpc::OPCODE::BCCLA) + .value("BCCLR", LIEF::assembly::powerpc::OPCODE::BCCLR) + .value("BCCLRL", LIEF::assembly::powerpc::OPCODE::BCCLRL) + .value("BCCTR", LIEF::assembly::powerpc::OPCODE::BCCTR) + .value("BCCTR8", LIEF::assembly::powerpc::OPCODE::BCCTR8) + .value("BCCTR8n", LIEF::assembly::powerpc::OPCODE::BCCTR8n) + .value("BCCTRL", LIEF::assembly::powerpc::OPCODE::BCCTRL) + .value("BCCTRL8", LIEF::assembly::powerpc::OPCODE::BCCTRL8) + .value("BCCTRL8n", LIEF::assembly::powerpc::OPCODE::BCCTRL8n) + .value("BCCTRLn", LIEF::assembly::powerpc::OPCODE::BCCTRLn) + .value("BCCTRn", LIEF::assembly::powerpc::OPCODE::BCCTRn) + .value("BCDADD_rec", LIEF::assembly::powerpc::OPCODE::BCDADD_rec) + .value("BCDCFN_rec", LIEF::assembly::powerpc::OPCODE::BCDCFN_rec) + .value("BCDCFSQ_rec", LIEF::assembly::powerpc::OPCODE::BCDCFSQ_rec) + .value("BCDCFZ_rec", LIEF::assembly::powerpc::OPCODE::BCDCFZ_rec) + .value("BCDCPSGN_rec", LIEF::assembly::powerpc::OPCODE::BCDCPSGN_rec) + .value("BCDCTN_rec", LIEF::assembly::powerpc::OPCODE::BCDCTN_rec) + .value("BCDCTSQ_rec", LIEF::assembly::powerpc::OPCODE::BCDCTSQ_rec) + .value("BCDCTZ_rec", LIEF::assembly::powerpc::OPCODE::BCDCTZ_rec) + .value("BCDSETSGN_rec", LIEF::assembly::powerpc::OPCODE::BCDSETSGN_rec) + .value("BCDSR_rec", LIEF::assembly::powerpc::OPCODE::BCDSR_rec) + .value("BCDSUB_rec", LIEF::assembly::powerpc::OPCODE::BCDSUB_rec) + .value("BCDS_rec", LIEF::assembly::powerpc::OPCODE::BCDS_rec) + .value("BCDTRUNC_rec", LIEF::assembly::powerpc::OPCODE::BCDTRUNC_rec) + .value("BCDUS_rec", LIEF::assembly::powerpc::OPCODE::BCDUS_rec) + .value("BCDUTRUNC_rec", LIEF::assembly::powerpc::OPCODE::BCDUTRUNC_rec) + .value("BCL", LIEF::assembly::powerpc::OPCODE::BCL) + .value("BCLR", LIEF::assembly::powerpc::OPCODE::BCLR) + .value("BCLRL", LIEF::assembly::powerpc::OPCODE::BCLRL) + .value("BCLRLn", LIEF::assembly::powerpc::OPCODE::BCLRLn) + .value("BCLRn", LIEF::assembly::powerpc::OPCODE::BCLRn) + .value("BCLalways", LIEF::assembly::powerpc::OPCODE::BCLalways) + .value("BCLn", LIEF::assembly::powerpc::OPCODE::BCLn) + .value("BCTR", LIEF::assembly::powerpc::OPCODE::BCTR) + .value("BCTR8", LIEF::assembly::powerpc::OPCODE::BCTR8) + .value("BCTRL", LIEF::assembly::powerpc::OPCODE::BCTRL); + opcodes.value("BCTRL8", LIEF::assembly::powerpc::OPCODE::BCTRL8) + .value("BCTRL8_LDinto_toc", LIEF::assembly::powerpc::OPCODE::BCTRL8_LDinto_toc) + .value("BCTRL8_LDinto_toc_RM", LIEF::assembly::powerpc::OPCODE::BCTRL8_LDinto_toc_RM) + .value("BCTRL8_RM", LIEF::assembly::powerpc::OPCODE::BCTRL8_RM) + .value("BCTRL_LWZinto_toc", LIEF::assembly::powerpc::OPCODE::BCTRL_LWZinto_toc) + .value("BCTRL_LWZinto_toc_RM", LIEF::assembly::powerpc::OPCODE::BCTRL_LWZinto_toc_RM) + .value("BCTRL_RM", LIEF::assembly::powerpc::OPCODE::BCTRL_RM) + .value("BCn", LIEF::assembly::powerpc::OPCODE::BCn) + .value("BDNZ", LIEF::assembly::powerpc::OPCODE::BDNZ) + .value("BDNZ8", LIEF::assembly::powerpc::OPCODE::BDNZ8) + .value("BDNZA", LIEF::assembly::powerpc::OPCODE::BDNZA) + .value("BDNZAm", LIEF::assembly::powerpc::OPCODE::BDNZAm) + .value("BDNZAp", LIEF::assembly::powerpc::OPCODE::BDNZAp) + .value("BDNZL", LIEF::assembly::powerpc::OPCODE::BDNZL) + .value("BDNZLA", LIEF::assembly::powerpc::OPCODE::BDNZLA) + .value("BDNZLAm", LIEF::assembly::powerpc::OPCODE::BDNZLAm) + .value("BDNZLAp", LIEF::assembly::powerpc::OPCODE::BDNZLAp) + .value("BDNZLR", LIEF::assembly::powerpc::OPCODE::BDNZLR) + .value("BDNZLR8", LIEF::assembly::powerpc::OPCODE::BDNZLR8) + .value("BDNZLRL", LIEF::assembly::powerpc::OPCODE::BDNZLRL) + .value("BDNZLRLm", LIEF::assembly::powerpc::OPCODE::BDNZLRLm) + .value("BDNZLRLp", LIEF::assembly::powerpc::OPCODE::BDNZLRLp) + .value("BDNZLRm", LIEF::assembly::powerpc::OPCODE::BDNZLRm) + .value("BDNZLRp", LIEF::assembly::powerpc::OPCODE::BDNZLRp) + .value("BDNZLm", LIEF::assembly::powerpc::OPCODE::BDNZLm) + .value("BDNZLp", LIEF::assembly::powerpc::OPCODE::BDNZLp) + .value("BDNZm", LIEF::assembly::powerpc::OPCODE::BDNZm) + .value("BDNZp", LIEF::assembly::powerpc::OPCODE::BDNZp) + .value("BDZ", LIEF::assembly::powerpc::OPCODE::BDZ) + .value("BDZ8", LIEF::assembly::powerpc::OPCODE::BDZ8) + .value("BDZA", LIEF::assembly::powerpc::OPCODE::BDZA) + .value("BDZAm", LIEF::assembly::powerpc::OPCODE::BDZAm) + .value("BDZAp", LIEF::assembly::powerpc::OPCODE::BDZAp) + .value("BDZL", LIEF::assembly::powerpc::OPCODE::BDZL) + .value("BDZLA", LIEF::assembly::powerpc::OPCODE::BDZLA) + .value("BDZLAm", LIEF::assembly::powerpc::OPCODE::BDZLAm) + .value("BDZLAp", LIEF::assembly::powerpc::OPCODE::BDZLAp) + .value("BDZLR", LIEF::assembly::powerpc::OPCODE::BDZLR) + .value("BDZLR8", LIEF::assembly::powerpc::OPCODE::BDZLR8) + .value("BDZLRL", LIEF::assembly::powerpc::OPCODE::BDZLRL) + .value("BDZLRLm", LIEF::assembly::powerpc::OPCODE::BDZLRLm) + .value("BDZLRLp", LIEF::assembly::powerpc::OPCODE::BDZLRLp) + .value("BDZLRm", LIEF::assembly::powerpc::OPCODE::BDZLRm) + .value("BDZLRp", LIEF::assembly::powerpc::OPCODE::BDZLRp) + .value("BDZLm", LIEF::assembly::powerpc::OPCODE::BDZLm) + .value("BDZLp", LIEF::assembly::powerpc::OPCODE::BDZLp) + .value("BDZm", LIEF::assembly::powerpc::OPCODE::BDZm) + .value("BDZp", LIEF::assembly::powerpc::OPCODE::BDZp) + .value("BL", LIEF::assembly::powerpc::OPCODE::BL) + .value("BL8", LIEF::assembly::powerpc::OPCODE::BL8) + .value("BL8_NOP", LIEF::assembly::powerpc::OPCODE::BL8_NOP) + .value("BL8_NOP_RM", LIEF::assembly::powerpc::OPCODE::BL8_NOP_RM) + .value("BL8_NOP_TLS", LIEF::assembly::powerpc::OPCODE::BL8_NOP_TLS) + .value("BL8_NOTOC", LIEF::assembly::powerpc::OPCODE::BL8_NOTOC) + .value("BL8_NOTOC_RM", LIEF::assembly::powerpc::OPCODE::BL8_NOTOC_RM) + .value("BL8_NOTOC_TLS", LIEF::assembly::powerpc::OPCODE::BL8_NOTOC_TLS) + .value("BL8_RM", LIEF::assembly::powerpc::OPCODE::BL8_RM) + .value("BL8_TLS", LIEF::assembly::powerpc::OPCODE::BL8_TLS) + .value("BL8_TLS_", LIEF::assembly::powerpc::OPCODE::BL8_TLS_) + .value("BLA", LIEF::assembly::powerpc::OPCODE::BLA) + .value("BLA8", LIEF::assembly::powerpc::OPCODE::BLA8) + .value("BLA8_NOP", LIEF::assembly::powerpc::OPCODE::BLA8_NOP) + .value("BLA8_NOP_RM", LIEF::assembly::powerpc::OPCODE::BLA8_NOP_RM) + .value("BLA8_RM", LIEF::assembly::powerpc::OPCODE::BLA8_RM) + .value("BLA_RM", LIEF::assembly::powerpc::OPCODE::BLA_RM) + .value("BLR", LIEF::assembly::powerpc::OPCODE::BLR) + .value("BLR8", LIEF::assembly::powerpc::OPCODE::BLR8) + .value("BLRL", LIEF::assembly::powerpc::OPCODE::BLRL) + .value("BL_NOP", LIEF::assembly::powerpc::OPCODE::BL_NOP) + .value("BL_NOP_RM", LIEF::assembly::powerpc::OPCODE::BL_NOP_RM) + .value("BL_RM", LIEF::assembly::powerpc::OPCODE::BL_RM) + .value("BL_TLS", LIEF::assembly::powerpc::OPCODE::BL_TLS) + .value("BPERMD", LIEF::assembly::powerpc::OPCODE::BPERMD) + .value("BRD", LIEF::assembly::powerpc::OPCODE::BRD) + .value("BRH", LIEF::assembly::powerpc::OPCODE::BRH) + .value("BRH8", LIEF::assembly::powerpc::OPCODE::BRH8) + .value("BRINC", LIEF::assembly::powerpc::OPCODE::BRINC) + .value("BRW", LIEF::assembly::powerpc::OPCODE::BRW) + .value("BRW8", LIEF::assembly::powerpc::OPCODE::BRW8) + .value("CBCDTD", LIEF::assembly::powerpc::OPCODE::CBCDTD) + .value("CBCDTD8", LIEF::assembly::powerpc::OPCODE::CBCDTD8) + .value("CDTBCD", LIEF::assembly::powerpc::OPCODE::CDTBCD) + .value("CDTBCD8", LIEF::assembly::powerpc::OPCODE::CDTBCD8) + .value("CFUGED", LIEF::assembly::powerpc::OPCODE::CFUGED) + .value("CLRBHRB", LIEF::assembly::powerpc::OPCODE::CLRBHRB) + .value("CMPB", LIEF::assembly::powerpc::OPCODE::CMPB) + .value("CMPB8", LIEF::assembly::powerpc::OPCODE::CMPB8) + .value("CMPD", LIEF::assembly::powerpc::OPCODE::CMPD) + .value("CMPDI", LIEF::assembly::powerpc::OPCODE::CMPDI) + .value("CMPEQB", LIEF::assembly::powerpc::OPCODE::CMPEQB) + .value("CMPLD", LIEF::assembly::powerpc::OPCODE::CMPLD) + .value("CMPLDI", LIEF::assembly::powerpc::OPCODE::CMPLDI) + .value("CMPLW", LIEF::assembly::powerpc::OPCODE::CMPLW) + .value("CMPLWI", LIEF::assembly::powerpc::OPCODE::CMPLWI) + .value("CMPRB", LIEF::assembly::powerpc::OPCODE::CMPRB) + .value("CMPRB8", LIEF::assembly::powerpc::OPCODE::CMPRB8) + .value("CMPW", LIEF::assembly::powerpc::OPCODE::CMPW) + .value("CMPWI", LIEF::assembly::powerpc::OPCODE::CMPWI) + .value("CNTLZD", LIEF::assembly::powerpc::OPCODE::CNTLZD) + .value("CNTLZDM", LIEF::assembly::powerpc::OPCODE::CNTLZDM) + .value("CNTLZD_rec", LIEF::assembly::powerpc::OPCODE::CNTLZD_rec) + .value("CNTLZW", LIEF::assembly::powerpc::OPCODE::CNTLZW) + .value("CNTLZW8", LIEF::assembly::powerpc::OPCODE::CNTLZW8) + .value("CNTLZW8_rec", LIEF::assembly::powerpc::OPCODE::CNTLZW8_rec) + .value("CNTLZW_rec", LIEF::assembly::powerpc::OPCODE::CNTLZW_rec) + .value("CNTTZD", LIEF::assembly::powerpc::OPCODE::CNTTZD) + .value("CNTTZDM", LIEF::assembly::powerpc::OPCODE::CNTTZDM) + .value("CNTTZD_rec", LIEF::assembly::powerpc::OPCODE::CNTTZD_rec) + .value("CNTTZW", LIEF::assembly::powerpc::OPCODE::CNTTZW) + .value("CNTTZW8", LIEF::assembly::powerpc::OPCODE::CNTTZW8) + .value("CNTTZW8_rec", LIEF::assembly::powerpc::OPCODE::CNTTZW8_rec) + .value("CNTTZW_rec", LIEF::assembly::powerpc::OPCODE::CNTTZW_rec) + .value("CP_ABORT", LIEF::assembly::powerpc::OPCODE::CP_ABORT) + .value("CP_COPY", LIEF::assembly::powerpc::OPCODE::CP_COPY) + .value("CP_COPY8", LIEF::assembly::powerpc::OPCODE::CP_COPY8) + .value("CP_PASTE8_rec", LIEF::assembly::powerpc::OPCODE::CP_PASTE8_rec) + .value("CP_PASTE_rec", LIEF::assembly::powerpc::OPCODE::CP_PASTE_rec) + .value("CR6SET", LIEF::assembly::powerpc::OPCODE::CR6SET) + .value("CR6UNSET", LIEF::assembly::powerpc::OPCODE::CR6UNSET) + .value("CRAND", LIEF::assembly::powerpc::OPCODE::CRAND) + .value("CRANDC", LIEF::assembly::powerpc::OPCODE::CRANDC) + .value("CREQV", LIEF::assembly::powerpc::OPCODE::CREQV) + .value("CRNAND", LIEF::assembly::powerpc::OPCODE::CRNAND) + .value("CRNOR", LIEF::assembly::powerpc::OPCODE::CRNOR) + .value("CRNOT", LIEF::assembly::powerpc::OPCODE::CRNOT) + .value("CROR", LIEF::assembly::powerpc::OPCODE::CROR) + .value("CRORC", LIEF::assembly::powerpc::OPCODE::CRORC) + .value("CRSET", LIEF::assembly::powerpc::OPCODE::CRSET) + .value("CRUNSET", LIEF::assembly::powerpc::OPCODE::CRUNSET) + .value("CRXOR", LIEF::assembly::powerpc::OPCODE::CRXOR) + .value("CTRL_DEP", LIEF::assembly::powerpc::OPCODE::CTRL_DEP) + .value("DADD", LIEF::assembly::powerpc::OPCODE::DADD) + .value("DADDQ", LIEF::assembly::powerpc::OPCODE::DADDQ) + .value("DADDQ_rec", LIEF::assembly::powerpc::OPCODE::DADDQ_rec) + .value("DADD_rec", LIEF::assembly::powerpc::OPCODE::DADD_rec) + .value("DARN", LIEF::assembly::powerpc::OPCODE::DARN) + .value("DCBA", LIEF::assembly::powerpc::OPCODE::DCBA) + .value("DCBF", LIEF::assembly::powerpc::OPCODE::DCBF) + .value("DCBFEP", LIEF::assembly::powerpc::OPCODE::DCBFEP) + .value("DCBI", LIEF::assembly::powerpc::OPCODE::DCBI) + .value("DCBST", LIEF::assembly::powerpc::OPCODE::DCBST) + .value("DCBSTEP", LIEF::assembly::powerpc::OPCODE::DCBSTEP) + .value("DCBT", LIEF::assembly::powerpc::OPCODE::DCBT) + .value("DCBTEP", LIEF::assembly::powerpc::OPCODE::DCBTEP) + .value("DCBTST", LIEF::assembly::powerpc::OPCODE::DCBTST) + .value("DCBTSTEP", LIEF::assembly::powerpc::OPCODE::DCBTSTEP) + .value("DCBZ", LIEF::assembly::powerpc::OPCODE::DCBZ) + .value("DCBZEP", LIEF::assembly::powerpc::OPCODE::DCBZEP) + .value("DCBZL", LIEF::assembly::powerpc::OPCODE::DCBZL) + .value("DCBZLEP", LIEF::assembly::powerpc::OPCODE::DCBZLEP) + .value("DCCCI", LIEF::assembly::powerpc::OPCODE::DCCCI) + .value("DCFFIX", LIEF::assembly::powerpc::OPCODE::DCFFIX) + .value("DCFFIXQ", LIEF::assembly::powerpc::OPCODE::DCFFIXQ) + .value("DCFFIXQQ", LIEF::assembly::powerpc::OPCODE::DCFFIXQQ) + .value("DCFFIXQ_rec", LIEF::assembly::powerpc::OPCODE::DCFFIXQ_rec) + .value("DCFFIX_rec", LIEF::assembly::powerpc::OPCODE::DCFFIX_rec) + .value("DCMPO", LIEF::assembly::powerpc::OPCODE::DCMPO) + .value("DCMPOQ", LIEF::assembly::powerpc::OPCODE::DCMPOQ) + .value("DCMPU", LIEF::assembly::powerpc::OPCODE::DCMPU) + .value("DCMPUQ", LIEF::assembly::powerpc::OPCODE::DCMPUQ) + .value("DCTDP", LIEF::assembly::powerpc::OPCODE::DCTDP) + .value("DCTDP_rec", LIEF::assembly::powerpc::OPCODE::DCTDP_rec) + .value("DCTFIX", LIEF::assembly::powerpc::OPCODE::DCTFIX) + .value("DCTFIXQ", LIEF::assembly::powerpc::OPCODE::DCTFIXQ) + .value("DCTFIXQQ", LIEF::assembly::powerpc::OPCODE::DCTFIXQQ) + .value("DCTFIXQ_rec", LIEF::assembly::powerpc::OPCODE::DCTFIXQ_rec) + .value("DCTFIX_rec", LIEF::assembly::powerpc::OPCODE::DCTFIX_rec) + .value("DCTQPQ", LIEF::assembly::powerpc::OPCODE::DCTQPQ) + .value("DCTQPQ_rec", LIEF::assembly::powerpc::OPCODE::DCTQPQ_rec) + .value("DDEDPD", LIEF::assembly::powerpc::OPCODE::DDEDPD) + .value("DDEDPDQ", LIEF::assembly::powerpc::OPCODE::DDEDPDQ) + .value("DDEDPDQ_rec", LIEF::assembly::powerpc::OPCODE::DDEDPDQ_rec) + .value("DDEDPD_rec", LIEF::assembly::powerpc::OPCODE::DDEDPD_rec) + .value("DDIV", LIEF::assembly::powerpc::OPCODE::DDIV) + .value("DDIVQ", LIEF::assembly::powerpc::OPCODE::DDIVQ) + .value("DDIVQ_rec", LIEF::assembly::powerpc::OPCODE::DDIVQ_rec) + .value("DDIV_rec", LIEF::assembly::powerpc::OPCODE::DDIV_rec) + .value("DENBCD", LIEF::assembly::powerpc::OPCODE::DENBCD) + .value("DENBCDQ", LIEF::assembly::powerpc::OPCODE::DENBCDQ) + .value("DENBCDQ_rec", LIEF::assembly::powerpc::OPCODE::DENBCDQ_rec) + .value("DENBCD_rec", LIEF::assembly::powerpc::OPCODE::DENBCD_rec) + .value("DIEX", LIEF::assembly::powerpc::OPCODE::DIEX) + .value("DIEXQ", LIEF::assembly::powerpc::OPCODE::DIEXQ) + .value("DIEXQ_rec", LIEF::assembly::powerpc::OPCODE::DIEXQ_rec) + .value("DIEX_rec", LIEF::assembly::powerpc::OPCODE::DIEX_rec) + .value("DIVD", LIEF::assembly::powerpc::OPCODE::DIVD) + .value("DIVDE", LIEF::assembly::powerpc::OPCODE::DIVDE) + .value("DIVDEO", LIEF::assembly::powerpc::OPCODE::DIVDEO) + .value("DIVDEO_rec", LIEF::assembly::powerpc::OPCODE::DIVDEO_rec) + .value("DIVDEU", LIEF::assembly::powerpc::OPCODE::DIVDEU) + .value("DIVDEUO", LIEF::assembly::powerpc::OPCODE::DIVDEUO) + .value("DIVDEUO_rec", LIEF::assembly::powerpc::OPCODE::DIVDEUO_rec) + .value("DIVDEU_rec", LIEF::assembly::powerpc::OPCODE::DIVDEU_rec) + .value("DIVDE_rec", LIEF::assembly::powerpc::OPCODE::DIVDE_rec) + .value("DIVDO", LIEF::assembly::powerpc::OPCODE::DIVDO) + .value("DIVDO_rec", LIEF::assembly::powerpc::OPCODE::DIVDO_rec) + .value("DIVDU", LIEF::assembly::powerpc::OPCODE::DIVDU) + .value("DIVDUO", LIEF::assembly::powerpc::OPCODE::DIVDUO) + .value("DIVDUO_rec", LIEF::assembly::powerpc::OPCODE::DIVDUO_rec) + .value("DIVDU_rec", LIEF::assembly::powerpc::OPCODE::DIVDU_rec) + .value("DIVD_rec", LIEF::assembly::powerpc::OPCODE::DIVD_rec) + .value("DIVW", LIEF::assembly::powerpc::OPCODE::DIVW) + .value("DIVWE", LIEF::assembly::powerpc::OPCODE::DIVWE) + .value("DIVWEO", LIEF::assembly::powerpc::OPCODE::DIVWEO) + .value("DIVWEO_rec", LIEF::assembly::powerpc::OPCODE::DIVWEO_rec) + .value("DIVWEU", LIEF::assembly::powerpc::OPCODE::DIVWEU) + .value("DIVWEUO", LIEF::assembly::powerpc::OPCODE::DIVWEUO) + .value("DIVWEUO_rec", LIEF::assembly::powerpc::OPCODE::DIVWEUO_rec) + .value("DIVWEU_rec", LIEF::assembly::powerpc::OPCODE::DIVWEU_rec) + .value("DIVWE_rec", LIEF::assembly::powerpc::OPCODE::DIVWE_rec) + .value("DIVWO", LIEF::assembly::powerpc::OPCODE::DIVWO) + .value("DIVWO_rec", LIEF::assembly::powerpc::OPCODE::DIVWO_rec) + .value("DIVWU", LIEF::assembly::powerpc::OPCODE::DIVWU) + .value("DIVWUO", LIEF::assembly::powerpc::OPCODE::DIVWUO) + .value("DIVWUO_rec", LIEF::assembly::powerpc::OPCODE::DIVWUO_rec) + .value("DIVWU_rec", LIEF::assembly::powerpc::OPCODE::DIVWU_rec) + .value("DIVW_rec", LIEF::assembly::powerpc::OPCODE::DIVW_rec) + .value("DMMR", LIEF::assembly::powerpc::OPCODE::DMMR) + .value("DMSETDMRZ", LIEF::assembly::powerpc::OPCODE::DMSETDMRZ) + .value("DMSHA2HASH", LIEF::assembly::powerpc::OPCODE::DMSHA2HASH) + .value("DMSHA3HASH", LIEF::assembly::powerpc::OPCODE::DMSHA3HASH) + .value("DMUL", LIEF::assembly::powerpc::OPCODE::DMUL) + .value("DMULQ", LIEF::assembly::powerpc::OPCODE::DMULQ) + .value("DMULQ_rec", LIEF::assembly::powerpc::OPCODE::DMULQ_rec) + .value("DMUL_rec", LIEF::assembly::powerpc::OPCODE::DMUL_rec) + .value("DMXOR", LIEF::assembly::powerpc::OPCODE::DMXOR) + .value("DMXVBF16GERX2", LIEF::assembly::powerpc::OPCODE::DMXVBF16GERX2) + .value("DMXVBF16GERX2NN", LIEF::assembly::powerpc::OPCODE::DMXVBF16GERX2NN) + .value("DMXVBF16GERX2NP", LIEF::assembly::powerpc::OPCODE::DMXVBF16GERX2NP) + .value("DMXVBF16GERX2PN", LIEF::assembly::powerpc::OPCODE::DMXVBF16GERX2PN) + .value("DMXVBF16GERX2PP", LIEF::assembly::powerpc::OPCODE::DMXVBF16GERX2PP) + .value("DMXVF16GERX2", LIEF::assembly::powerpc::OPCODE::DMXVF16GERX2) + .value("DMXVF16GERX2NN", LIEF::assembly::powerpc::OPCODE::DMXVF16GERX2NN) + .value("DMXVF16GERX2NP", LIEF::assembly::powerpc::OPCODE::DMXVF16GERX2NP) + .value("DMXVF16GERX2PN", LIEF::assembly::powerpc::OPCODE::DMXVF16GERX2PN) + .value("DMXVF16GERX2PP", LIEF::assembly::powerpc::OPCODE::DMXVF16GERX2PP) + .value("DMXVI8GERX4", LIEF::assembly::powerpc::OPCODE::DMXVI8GERX4) + .value("DMXVI8GERX4PP", LIEF::assembly::powerpc::OPCODE::DMXVI8GERX4PP) + .value("DMXVI8GERX4SPP", LIEF::assembly::powerpc::OPCODE::DMXVI8GERX4SPP) + .value("DMXXEXTFDMR256", LIEF::assembly::powerpc::OPCODE::DMXXEXTFDMR256) + .value("DMXXEXTFDMR512", LIEF::assembly::powerpc::OPCODE::DMXXEXTFDMR512) + .value("DMXXEXTFDMR512_HI", LIEF::assembly::powerpc::OPCODE::DMXXEXTFDMR512_HI) + .value("DMXXINSTDMR256", LIEF::assembly::powerpc::OPCODE::DMXXINSTDMR256) + .value("DMXXINSTDMR512", LIEF::assembly::powerpc::OPCODE::DMXXINSTDMR512) + .value("DMXXINSTDMR512_HI", LIEF::assembly::powerpc::OPCODE::DMXXINSTDMR512_HI) + .value("DMXXSETACCZ", LIEF::assembly::powerpc::OPCODE::DMXXSETACCZ) + .value("DMXXSHAPAD", LIEF::assembly::powerpc::OPCODE::DMXXSHAPAD) + .value("DQUA", LIEF::assembly::powerpc::OPCODE::DQUA) + .value("DQUAI", LIEF::assembly::powerpc::OPCODE::DQUAI) + .value("DQUAIQ", LIEF::assembly::powerpc::OPCODE::DQUAIQ) + .value("DQUAIQ_rec", LIEF::assembly::powerpc::OPCODE::DQUAIQ_rec) + .value("DQUAI_rec", LIEF::assembly::powerpc::OPCODE::DQUAI_rec) + .value("DQUAQ", LIEF::assembly::powerpc::OPCODE::DQUAQ) + .value("DQUAQ_rec", LIEF::assembly::powerpc::OPCODE::DQUAQ_rec) + .value("DQUA_rec", LIEF::assembly::powerpc::OPCODE::DQUA_rec) + .value("DRDPQ", LIEF::assembly::powerpc::OPCODE::DRDPQ) + .value("DRDPQ_rec", LIEF::assembly::powerpc::OPCODE::DRDPQ_rec) + .value("DRINTN", LIEF::assembly::powerpc::OPCODE::DRINTN) + .value("DRINTNQ", LIEF::assembly::powerpc::OPCODE::DRINTNQ) + .value("DRINTNQ_rec", LIEF::assembly::powerpc::OPCODE::DRINTNQ_rec) + .value("DRINTN_rec", LIEF::assembly::powerpc::OPCODE::DRINTN_rec) + .value("DRINTX", LIEF::assembly::powerpc::OPCODE::DRINTX) + .value("DRINTXQ", LIEF::assembly::powerpc::OPCODE::DRINTXQ) + .value("DRINTXQ_rec", LIEF::assembly::powerpc::OPCODE::DRINTXQ_rec) + .value("DRINTX_rec", LIEF::assembly::powerpc::OPCODE::DRINTX_rec) + .value("DRRND", LIEF::assembly::powerpc::OPCODE::DRRND) + .value("DRRNDQ", LIEF::assembly::powerpc::OPCODE::DRRNDQ) + .value("DRRNDQ_rec", LIEF::assembly::powerpc::OPCODE::DRRNDQ_rec) + .value("DRRND_rec", LIEF::assembly::powerpc::OPCODE::DRRND_rec) + .value("DRSP", LIEF::assembly::powerpc::OPCODE::DRSP) + .value("DRSP_rec", LIEF::assembly::powerpc::OPCODE::DRSP_rec) + .value("DSCLI", LIEF::assembly::powerpc::OPCODE::DSCLI) + .value("DSCLIQ", LIEF::assembly::powerpc::OPCODE::DSCLIQ) + .value("DSCLIQ_rec", LIEF::assembly::powerpc::OPCODE::DSCLIQ_rec) + .value("DSCLI_rec", LIEF::assembly::powerpc::OPCODE::DSCLI_rec) + .value("DSCRI", LIEF::assembly::powerpc::OPCODE::DSCRI) + .value("DSCRIQ", LIEF::assembly::powerpc::OPCODE::DSCRIQ) + .value("DSCRIQ_rec", LIEF::assembly::powerpc::OPCODE::DSCRIQ_rec) + .value("DSCRI_rec", LIEF::assembly::powerpc::OPCODE::DSCRI_rec) + .value("DSS", LIEF::assembly::powerpc::OPCODE::DSS) + .value("DSSALL", LIEF::assembly::powerpc::OPCODE::DSSALL) + .value("DST", LIEF::assembly::powerpc::OPCODE::DST) + .value("DST64", LIEF::assembly::powerpc::OPCODE::DST64) + .value("DSTST", LIEF::assembly::powerpc::OPCODE::DSTST) + .value("DSTST64", LIEF::assembly::powerpc::OPCODE::DSTST64) + .value("DSTSTT", LIEF::assembly::powerpc::OPCODE::DSTSTT) + .value("DSTSTT64", LIEF::assembly::powerpc::OPCODE::DSTSTT64) + .value("DSTT", LIEF::assembly::powerpc::OPCODE::DSTT) + .value("DSTT64", LIEF::assembly::powerpc::OPCODE::DSTT64) + .value("DSUB", LIEF::assembly::powerpc::OPCODE::DSUB) + .value("DSUBQ", LIEF::assembly::powerpc::OPCODE::DSUBQ) + .value("DSUBQ_rec", LIEF::assembly::powerpc::OPCODE::DSUBQ_rec) + .value("DSUB_rec", LIEF::assembly::powerpc::OPCODE::DSUB_rec) + .value("DTSTDC", LIEF::assembly::powerpc::OPCODE::DTSTDC) + .value("DTSTDCQ", LIEF::assembly::powerpc::OPCODE::DTSTDCQ) + .value("DTSTDG", LIEF::assembly::powerpc::OPCODE::DTSTDG) + .value("DTSTDGQ", LIEF::assembly::powerpc::OPCODE::DTSTDGQ) + .value("DTSTEX", LIEF::assembly::powerpc::OPCODE::DTSTEX) + .value("DTSTEXQ", LIEF::assembly::powerpc::OPCODE::DTSTEXQ) + .value("DTSTSF", LIEF::assembly::powerpc::OPCODE::DTSTSF); + opcodes.value("DTSTSFI", LIEF::assembly::powerpc::OPCODE::DTSTSFI) + .value("DTSTSFIQ", LIEF::assembly::powerpc::OPCODE::DTSTSFIQ) + .value("DTSTSFQ", LIEF::assembly::powerpc::OPCODE::DTSTSFQ) + .value("DXEX", LIEF::assembly::powerpc::OPCODE::DXEX) + .value("DXEXQ", LIEF::assembly::powerpc::OPCODE::DXEXQ) + .value("DXEXQ_rec", LIEF::assembly::powerpc::OPCODE::DXEXQ_rec) + .value("DXEX_rec", LIEF::assembly::powerpc::OPCODE::DXEX_rec) + .value("DYNALLOC", LIEF::assembly::powerpc::OPCODE::DYNALLOC) + .value("DYNALLOC8", LIEF::assembly::powerpc::OPCODE::DYNALLOC8) + .value("DYNAREAOFFSET", LIEF::assembly::powerpc::OPCODE::DYNAREAOFFSET) + .value("DYNAREAOFFSET8", LIEF::assembly::powerpc::OPCODE::DYNAREAOFFSET8) + .value("DecreaseCTR8loop", LIEF::assembly::powerpc::OPCODE::DecreaseCTR8loop) + .value("DecreaseCTRloop", LIEF::assembly::powerpc::OPCODE::DecreaseCTRloop) + .value("EFDABS", LIEF::assembly::powerpc::OPCODE::EFDABS) + .value("EFDADD", LIEF::assembly::powerpc::OPCODE::EFDADD) + .value("EFDCFS", LIEF::assembly::powerpc::OPCODE::EFDCFS) + .value("EFDCFSF", LIEF::assembly::powerpc::OPCODE::EFDCFSF) + .value("EFDCFSI", LIEF::assembly::powerpc::OPCODE::EFDCFSI) + .value("EFDCFSID", LIEF::assembly::powerpc::OPCODE::EFDCFSID) + .value("EFDCFUF", LIEF::assembly::powerpc::OPCODE::EFDCFUF) + .value("EFDCFUI", LIEF::assembly::powerpc::OPCODE::EFDCFUI) + .value("EFDCFUID", LIEF::assembly::powerpc::OPCODE::EFDCFUID) + .value("EFDCMPEQ", LIEF::assembly::powerpc::OPCODE::EFDCMPEQ) + .value("EFDCMPGT", LIEF::assembly::powerpc::OPCODE::EFDCMPGT) + .value("EFDCMPLT", LIEF::assembly::powerpc::OPCODE::EFDCMPLT) + .value("EFDCTSF", LIEF::assembly::powerpc::OPCODE::EFDCTSF) + .value("EFDCTSI", LIEF::assembly::powerpc::OPCODE::EFDCTSI) + .value("EFDCTSIDZ", LIEF::assembly::powerpc::OPCODE::EFDCTSIDZ) + .value("EFDCTSIZ", LIEF::assembly::powerpc::OPCODE::EFDCTSIZ) + .value("EFDCTUF", LIEF::assembly::powerpc::OPCODE::EFDCTUF) + .value("EFDCTUI", LIEF::assembly::powerpc::OPCODE::EFDCTUI) + .value("EFDCTUIDZ", LIEF::assembly::powerpc::OPCODE::EFDCTUIDZ) + .value("EFDCTUIZ", LIEF::assembly::powerpc::OPCODE::EFDCTUIZ) + .value("EFDDIV", LIEF::assembly::powerpc::OPCODE::EFDDIV) + .value("EFDMUL", LIEF::assembly::powerpc::OPCODE::EFDMUL) + .value("EFDNABS", LIEF::assembly::powerpc::OPCODE::EFDNABS) + .value("EFDNEG", LIEF::assembly::powerpc::OPCODE::EFDNEG) + .value("EFDSUB", LIEF::assembly::powerpc::OPCODE::EFDSUB) + .value("EFDTSTEQ", LIEF::assembly::powerpc::OPCODE::EFDTSTEQ) + .value("EFDTSTGT", LIEF::assembly::powerpc::OPCODE::EFDTSTGT) + .value("EFDTSTLT", LIEF::assembly::powerpc::OPCODE::EFDTSTLT) + .value("EFSABS", LIEF::assembly::powerpc::OPCODE::EFSABS) + .value("EFSADD", LIEF::assembly::powerpc::OPCODE::EFSADD) + .value("EFSCFD", LIEF::assembly::powerpc::OPCODE::EFSCFD) + .value("EFSCFSF", LIEF::assembly::powerpc::OPCODE::EFSCFSF) + .value("EFSCFSI", LIEF::assembly::powerpc::OPCODE::EFSCFSI) + .value("EFSCFUF", LIEF::assembly::powerpc::OPCODE::EFSCFUF) + .value("EFSCFUI", LIEF::assembly::powerpc::OPCODE::EFSCFUI) + .value("EFSCMPEQ", LIEF::assembly::powerpc::OPCODE::EFSCMPEQ) + .value("EFSCMPGT", LIEF::assembly::powerpc::OPCODE::EFSCMPGT) + .value("EFSCMPLT", LIEF::assembly::powerpc::OPCODE::EFSCMPLT) + .value("EFSCTSF", LIEF::assembly::powerpc::OPCODE::EFSCTSF) + .value("EFSCTSI", LIEF::assembly::powerpc::OPCODE::EFSCTSI) + .value("EFSCTSIZ", LIEF::assembly::powerpc::OPCODE::EFSCTSIZ) + .value("EFSCTUF", LIEF::assembly::powerpc::OPCODE::EFSCTUF) + .value("EFSCTUI", LIEF::assembly::powerpc::OPCODE::EFSCTUI) + .value("EFSCTUIZ", LIEF::assembly::powerpc::OPCODE::EFSCTUIZ) + .value("EFSDIV", LIEF::assembly::powerpc::OPCODE::EFSDIV) + .value("EFSMUL", LIEF::assembly::powerpc::OPCODE::EFSMUL) + .value("EFSNABS", LIEF::assembly::powerpc::OPCODE::EFSNABS) + .value("EFSNEG", LIEF::assembly::powerpc::OPCODE::EFSNEG) + .value("EFSSUB", LIEF::assembly::powerpc::OPCODE::EFSSUB) + .value("EFSTSTEQ", LIEF::assembly::powerpc::OPCODE::EFSTSTEQ) + .value("EFSTSTGT", LIEF::assembly::powerpc::OPCODE::EFSTSTGT) + .value("EFSTSTLT", LIEF::assembly::powerpc::OPCODE::EFSTSTLT) + .value("EH_SjLj_LongJmp32", LIEF::assembly::powerpc::OPCODE::EH_SjLj_LongJmp32) + .value("EH_SjLj_LongJmp64", LIEF::assembly::powerpc::OPCODE::EH_SjLj_LongJmp64) + .value("EH_SjLj_SetJmp32", LIEF::assembly::powerpc::OPCODE::EH_SjLj_SetJmp32) + .value("EH_SjLj_SetJmp64", LIEF::assembly::powerpc::OPCODE::EH_SjLj_SetJmp64) + .value("EH_SjLj_Setup", LIEF::assembly::powerpc::OPCODE::EH_SjLj_Setup) + .value("EQV", LIEF::assembly::powerpc::OPCODE::EQV) + .value("EQV8", LIEF::assembly::powerpc::OPCODE::EQV8) + .value("EQV8_rec", LIEF::assembly::powerpc::OPCODE::EQV8_rec) + .value("EQV_rec", LIEF::assembly::powerpc::OPCODE::EQV_rec) + .value("EVABS", LIEF::assembly::powerpc::OPCODE::EVABS) + .value("EVADDIW", LIEF::assembly::powerpc::OPCODE::EVADDIW) + .value("EVADDSMIAAW", LIEF::assembly::powerpc::OPCODE::EVADDSMIAAW) + .value("EVADDSSIAAW", LIEF::assembly::powerpc::OPCODE::EVADDSSIAAW) + .value("EVADDUMIAAW", LIEF::assembly::powerpc::OPCODE::EVADDUMIAAW) + .value("EVADDUSIAAW", LIEF::assembly::powerpc::OPCODE::EVADDUSIAAW) + .value("EVADDW", LIEF::assembly::powerpc::OPCODE::EVADDW) + .value("EVAND", LIEF::assembly::powerpc::OPCODE::EVAND) + .value("EVANDC", LIEF::assembly::powerpc::OPCODE::EVANDC) + .value("EVCMPEQ", LIEF::assembly::powerpc::OPCODE::EVCMPEQ) + .value("EVCMPGTS", LIEF::assembly::powerpc::OPCODE::EVCMPGTS) + .value("EVCMPGTU", LIEF::assembly::powerpc::OPCODE::EVCMPGTU) + .value("EVCMPLTS", LIEF::assembly::powerpc::OPCODE::EVCMPLTS) + .value("EVCMPLTU", LIEF::assembly::powerpc::OPCODE::EVCMPLTU) + .value("EVCNTLSW", LIEF::assembly::powerpc::OPCODE::EVCNTLSW) + .value("EVCNTLZW", LIEF::assembly::powerpc::OPCODE::EVCNTLZW) + .value("EVDIVWS", LIEF::assembly::powerpc::OPCODE::EVDIVWS) + .value("EVDIVWU", LIEF::assembly::powerpc::OPCODE::EVDIVWU) + .value("EVEQV", LIEF::assembly::powerpc::OPCODE::EVEQV) + .value("EVEXTSB", LIEF::assembly::powerpc::OPCODE::EVEXTSB) + .value("EVEXTSH", LIEF::assembly::powerpc::OPCODE::EVEXTSH) + .value("EVFSABS", LIEF::assembly::powerpc::OPCODE::EVFSABS) + .value("EVFSADD", LIEF::assembly::powerpc::OPCODE::EVFSADD) + .value("EVFSCFSF", LIEF::assembly::powerpc::OPCODE::EVFSCFSF) + .value("EVFSCFSI", LIEF::assembly::powerpc::OPCODE::EVFSCFSI) + .value("EVFSCFUF", LIEF::assembly::powerpc::OPCODE::EVFSCFUF) + .value("EVFSCFUI", LIEF::assembly::powerpc::OPCODE::EVFSCFUI) + .value("EVFSCMPEQ", LIEF::assembly::powerpc::OPCODE::EVFSCMPEQ) + .value("EVFSCMPGT", LIEF::assembly::powerpc::OPCODE::EVFSCMPGT) + .value("EVFSCMPLT", LIEF::assembly::powerpc::OPCODE::EVFSCMPLT) + .value("EVFSCTSF", LIEF::assembly::powerpc::OPCODE::EVFSCTSF) + .value("EVFSCTSI", LIEF::assembly::powerpc::OPCODE::EVFSCTSI) + .value("EVFSCTSIZ", LIEF::assembly::powerpc::OPCODE::EVFSCTSIZ) + .value("EVFSCTUF", LIEF::assembly::powerpc::OPCODE::EVFSCTUF) + .value("EVFSCTUI", LIEF::assembly::powerpc::OPCODE::EVFSCTUI) + .value("EVFSCTUIZ", LIEF::assembly::powerpc::OPCODE::EVFSCTUIZ) + .value("EVFSDIV", LIEF::assembly::powerpc::OPCODE::EVFSDIV) + .value("EVFSMUL", LIEF::assembly::powerpc::OPCODE::EVFSMUL) + .value("EVFSNABS", LIEF::assembly::powerpc::OPCODE::EVFSNABS) + .value("EVFSNEG", LIEF::assembly::powerpc::OPCODE::EVFSNEG) + .value("EVFSSUB", LIEF::assembly::powerpc::OPCODE::EVFSSUB) + .value("EVFSTSTEQ", LIEF::assembly::powerpc::OPCODE::EVFSTSTEQ) + .value("EVFSTSTGT", LIEF::assembly::powerpc::OPCODE::EVFSTSTGT) + .value("EVFSTSTLT", LIEF::assembly::powerpc::OPCODE::EVFSTSTLT) + .value("EVLDD", LIEF::assembly::powerpc::OPCODE::EVLDD) + .value("EVLDDX", LIEF::assembly::powerpc::OPCODE::EVLDDX) + .value("EVLDH", LIEF::assembly::powerpc::OPCODE::EVLDH) + .value("EVLDHX", LIEF::assembly::powerpc::OPCODE::EVLDHX) + .value("EVLDW", LIEF::assembly::powerpc::OPCODE::EVLDW) + .value("EVLDWX", LIEF::assembly::powerpc::OPCODE::EVLDWX) + .value("EVLHHESPLAT", LIEF::assembly::powerpc::OPCODE::EVLHHESPLAT) + .value("EVLHHESPLATX", LIEF::assembly::powerpc::OPCODE::EVLHHESPLATX) + .value("EVLHHOSSPLAT", LIEF::assembly::powerpc::OPCODE::EVLHHOSSPLAT) + .value("EVLHHOSSPLATX", LIEF::assembly::powerpc::OPCODE::EVLHHOSSPLATX) + .value("EVLHHOUSPLAT", LIEF::assembly::powerpc::OPCODE::EVLHHOUSPLAT) + .value("EVLHHOUSPLATX", LIEF::assembly::powerpc::OPCODE::EVLHHOUSPLATX) + .value("EVLWHE", LIEF::assembly::powerpc::OPCODE::EVLWHE) + .value("EVLWHEX", LIEF::assembly::powerpc::OPCODE::EVLWHEX) + .value("EVLWHOS", LIEF::assembly::powerpc::OPCODE::EVLWHOS) + .value("EVLWHOSX", LIEF::assembly::powerpc::OPCODE::EVLWHOSX) + .value("EVLWHOU", LIEF::assembly::powerpc::OPCODE::EVLWHOU) + .value("EVLWHOUX", LIEF::assembly::powerpc::OPCODE::EVLWHOUX) + .value("EVLWHSPLAT", LIEF::assembly::powerpc::OPCODE::EVLWHSPLAT) + .value("EVLWHSPLATX", LIEF::assembly::powerpc::OPCODE::EVLWHSPLATX) + .value("EVLWWSPLAT", LIEF::assembly::powerpc::OPCODE::EVLWWSPLAT) + .value("EVLWWSPLATX", LIEF::assembly::powerpc::OPCODE::EVLWWSPLATX) + .value("EVMERGEHI", LIEF::assembly::powerpc::OPCODE::EVMERGEHI) + .value("EVMERGEHILO", LIEF::assembly::powerpc::OPCODE::EVMERGEHILO) + .value("EVMERGELO", LIEF::assembly::powerpc::OPCODE::EVMERGELO) + .value("EVMERGELOHI", LIEF::assembly::powerpc::OPCODE::EVMERGELOHI) + .value("EVMHEGSMFAA", LIEF::assembly::powerpc::OPCODE::EVMHEGSMFAA) + .value("EVMHEGSMFAN", LIEF::assembly::powerpc::OPCODE::EVMHEGSMFAN) + .value("EVMHEGSMIAA", LIEF::assembly::powerpc::OPCODE::EVMHEGSMIAA) + .value("EVMHEGSMIAN", LIEF::assembly::powerpc::OPCODE::EVMHEGSMIAN) + .value("EVMHEGUMIAA", LIEF::assembly::powerpc::OPCODE::EVMHEGUMIAA) + .value("EVMHEGUMIAN", LIEF::assembly::powerpc::OPCODE::EVMHEGUMIAN) + .value("EVMHESMF", LIEF::assembly::powerpc::OPCODE::EVMHESMF) + .value("EVMHESMFA", LIEF::assembly::powerpc::OPCODE::EVMHESMFA) + .value("EVMHESMFAAW", LIEF::assembly::powerpc::OPCODE::EVMHESMFAAW) + .value("EVMHESMFANW", LIEF::assembly::powerpc::OPCODE::EVMHESMFANW) + .value("EVMHESMI", LIEF::assembly::powerpc::OPCODE::EVMHESMI) + .value("EVMHESMIA", LIEF::assembly::powerpc::OPCODE::EVMHESMIA) + .value("EVMHESMIAAW", LIEF::assembly::powerpc::OPCODE::EVMHESMIAAW) + .value("EVMHESMIANW", LIEF::assembly::powerpc::OPCODE::EVMHESMIANW) + .value("EVMHESSF", LIEF::assembly::powerpc::OPCODE::EVMHESSF) + .value("EVMHESSFA", LIEF::assembly::powerpc::OPCODE::EVMHESSFA) + .value("EVMHESSFAAW", LIEF::assembly::powerpc::OPCODE::EVMHESSFAAW) + .value("EVMHESSFANW", LIEF::assembly::powerpc::OPCODE::EVMHESSFANW) + .value("EVMHESSIAAW", LIEF::assembly::powerpc::OPCODE::EVMHESSIAAW) + .value("EVMHESSIANW", LIEF::assembly::powerpc::OPCODE::EVMHESSIANW) + .value("EVMHEUMI", LIEF::assembly::powerpc::OPCODE::EVMHEUMI) + .value("EVMHEUMIA", LIEF::assembly::powerpc::OPCODE::EVMHEUMIA) + .value("EVMHEUMIAAW", LIEF::assembly::powerpc::OPCODE::EVMHEUMIAAW) + .value("EVMHEUMIANW", LIEF::assembly::powerpc::OPCODE::EVMHEUMIANW) + .value("EVMHEUSIAAW", LIEF::assembly::powerpc::OPCODE::EVMHEUSIAAW) + .value("EVMHEUSIANW", LIEF::assembly::powerpc::OPCODE::EVMHEUSIANW) + .value("EVMHOGSMFAA", LIEF::assembly::powerpc::OPCODE::EVMHOGSMFAA) + .value("EVMHOGSMFAN", LIEF::assembly::powerpc::OPCODE::EVMHOGSMFAN) + .value("EVMHOGSMIAA", LIEF::assembly::powerpc::OPCODE::EVMHOGSMIAA) + .value("EVMHOGSMIAN", LIEF::assembly::powerpc::OPCODE::EVMHOGSMIAN) + .value("EVMHOGUMIAA", LIEF::assembly::powerpc::OPCODE::EVMHOGUMIAA) + .value("EVMHOGUMIAN", LIEF::assembly::powerpc::OPCODE::EVMHOGUMIAN) + .value("EVMHOSMF", LIEF::assembly::powerpc::OPCODE::EVMHOSMF) + .value("EVMHOSMFA", LIEF::assembly::powerpc::OPCODE::EVMHOSMFA) + .value("EVMHOSMFAAW", LIEF::assembly::powerpc::OPCODE::EVMHOSMFAAW) + .value("EVMHOSMFANW", LIEF::assembly::powerpc::OPCODE::EVMHOSMFANW) + .value("EVMHOSMI", LIEF::assembly::powerpc::OPCODE::EVMHOSMI) + .value("EVMHOSMIA", LIEF::assembly::powerpc::OPCODE::EVMHOSMIA) + .value("EVMHOSMIAAW", LIEF::assembly::powerpc::OPCODE::EVMHOSMIAAW) + .value("EVMHOSMIANW", LIEF::assembly::powerpc::OPCODE::EVMHOSMIANW) + .value("EVMHOSSF", LIEF::assembly::powerpc::OPCODE::EVMHOSSF) + .value("EVMHOSSFA", LIEF::assembly::powerpc::OPCODE::EVMHOSSFA) + .value("EVMHOSSFAAW", LIEF::assembly::powerpc::OPCODE::EVMHOSSFAAW) + .value("EVMHOSSFANW", LIEF::assembly::powerpc::OPCODE::EVMHOSSFANW) + .value("EVMHOSSIAAW", LIEF::assembly::powerpc::OPCODE::EVMHOSSIAAW) + .value("EVMHOSSIANW", LIEF::assembly::powerpc::OPCODE::EVMHOSSIANW) + .value("EVMHOUMI", LIEF::assembly::powerpc::OPCODE::EVMHOUMI) + .value("EVMHOUMIA", LIEF::assembly::powerpc::OPCODE::EVMHOUMIA) + .value("EVMHOUMIAAW", LIEF::assembly::powerpc::OPCODE::EVMHOUMIAAW) + .value("EVMHOUMIANW", LIEF::assembly::powerpc::OPCODE::EVMHOUMIANW) + .value("EVMHOUSIAAW", LIEF::assembly::powerpc::OPCODE::EVMHOUSIAAW) + .value("EVMHOUSIANW", LIEF::assembly::powerpc::OPCODE::EVMHOUSIANW) + .value("EVMRA", LIEF::assembly::powerpc::OPCODE::EVMRA) + .value("EVMWHSMF", LIEF::assembly::powerpc::OPCODE::EVMWHSMF) + .value("EVMWHSMFA", LIEF::assembly::powerpc::OPCODE::EVMWHSMFA) + .value("EVMWHSMI", LIEF::assembly::powerpc::OPCODE::EVMWHSMI) + .value("EVMWHSMIA", LIEF::assembly::powerpc::OPCODE::EVMWHSMIA) + .value("EVMWHSSF", LIEF::assembly::powerpc::OPCODE::EVMWHSSF) + .value("EVMWHSSFA", LIEF::assembly::powerpc::OPCODE::EVMWHSSFA) + .value("EVMWHUMI", LIEF::assembly::powerpc::OPCODE::EVMWHUMI) + .value("EVMWHUMIA", LIEF::assembly::powerpc::OPCODE::EVMWHUMIA) + .value("EVMWLSMIAAW", LIEF::assembly::powerpc::OPCODE::EVMWLSMIAAW) + .value("EVMWLSMIANW", LIEF::assembly::powerpc::OPCODE::EVMWLSMIANW) + .value("EVMWLSSIAAW", LIEF::assembly::powerpc::OPCODE::EVMWLSSIAAW) + .value("EVMWLSSIANW", LIEF::assembly::powerpc::OPCODE::EVMWLSSIANW) + .value("EVMWLUMI", LIEF::assembly::powerpc::OPCODE::EVMWLUMI) + .value("EVMWLUMIA", LIEF::assembly::powerpc::OPCODE::EVMWLUMIA) + .value("EVMWLUMIAAW", LIEF::assembly::powerpc::OPCODE::EVMWLUMIAAW) + .value("EVMWLUMIANW", LIEF::assembly::powerpc::OPCODE::EVMWLUMIANW) + .value("EVMWLUSIAAW", LIEF::assembly::powerpc::OPCODE::EVMWLUSIAAW) + .value("EVMWLUSIANW", LIEF::assembly::powerpc::OPCODE::EVMWLUSIANW) + .value("EVMWSMF", LIEF::assembly::powerpc::OPCODE::EVMWSMF) + .value("EVMWSMFA", LIEF::assembly::powerpc::OPCODE::EVMWSMFA) + .value("EVMWSMFAA", LIEF::assembly::powerpc::OPCODE::EVMWSMFAA) + .value("EVMWSMFAN", LIEF::assembly::powerpc::OPCODE::EVMWSMFAN) + .value("EVMWSMI", LIEF::assembly::powerpc::OPCODE::EVMWSMI) + .value("EVMWSMIA", LIEF::assembly::powerpc::OPCODE::EVMWSMIA) + .value("EVMWSMIAA", LIEF::assembly::powerpc::OPCODE::EVMWSMIAA) + .value("EVMWSMIAN", LIEF::assembly::powerpc::OPCODE::EVMWSMIAN) + .value("EVMWSSF", LIEF::assembly::powerpc::OPCODE::EVMWSSF) + .value("EVMWSSFA", LIEF::assembly::powerpc::OPCODE::EVMWSSFA) + .value("EVMWSSFAA", LIEF::assembly::powerpc::OPCODE::EVMWSSFAA) + .value("EVMWSSFAN", LIEF::assembly::powerpc::OPCODE::EVMWSSFAN) + .value("EVMWUMI", LIEF::assembly::powerpc::OPCODE::EVMWUMI) + .value("EVMWUMIA", LIEF::assembly::powerpc::OPCODE::EVMWUMIA) + .value("EVMWUMIAA", LIEF::assembly::powerpc::OPCODE::EVMWUMIAA) + .value("EVMWUMIAN", LIEF::assembly::powerpc::OPCODE::EVMWUMIAN) + .value("EVNAND", LIEF::assembly::powerpc::OPCODE::EVNAND) + .value("EVNEG", LIEF::assembly::powerpc::OPCODE::EVNEG) + .value("EVNOR", LIEF::assembly::powerpc::OPCODE::EVNOR) + .value("EVOR", LIEF::assembly::powerpc::OPCODE::EVOR) + .value("EVORC", LIEF::assembly::powerpc::OPCODE::EVORC) + .value("EVRLW", LIEF::assembly::powerpc::OPCODE::EVRLW) + .value("EVRLWI", LIEF::assembly::powerpc::OPCODE::EVRLWI) + .value("EVRNDW", LIEF::assembly::powerpc::OPCODE::EVRNDW) + .value("EVSEL", LIEF::assembly::powerpc::OPCODE::EVSEL) + .value("EVSLW", LIEF::assembly::powerpc::OPCODE::EVSLW) + .value("EVSLWI", LIEF::assembly::powerpc::OPCODE::EVSLWI) + .value("EVSPLATFI", LIEF::assembly::powerpc::OPCODE::EVSPLATFI) + .value("EVSPLATI", LIEF::assembly::powerpc::OPCODE::EVSPLATI) + .value("EVSRWIS", LIEF::assembly::powerpc::OPCODE::EVSRWIS) + .value("EVSRWIU", LIEF::assembly::powerpc::OPCODE::EVSRWIU) + .value("EVSRWS", LIEF::assembly::powerpc::OPCODE::EVSRWS) + .value("EVSRWU", LIEF::assembly::powerpc::OPCODE::EVSRWU) + .value("EVSTDD", LIEF::assembly::powerpc::OPCODE::EVSTDD) + .value("EVSTDDX", LIEF::assembly::powerpc::OPCODE::EVSTDDX) + .value("EVSTDH", LIEF::assembly::powerpc::OPCODE::EVSTDH) + .value("EVSTDHX", LIEF::assembly::powerpc::OPCODE::EVSTDHX) + .value("EVSTDW", LIEF::assembly::powerpc::OPCODE::EVSTDW) + .value("EVSTDWX", LIEF::assembly::powerpc::OPCODE::EVSTDWX) + .value("EVSTWHE", LIEF::assembly::powerpc::OPCODE::EVSTWHE) + .value("EVSTWHEX", LIEF::assembly::powerpc::OPCODE::EVSTWHEX) + .value("EVSTWHO", LIEF::assembly::powerpc::OPCODE::EVSTWHO) + .value("EVSTWHOX", LIEF::assembly::powerpc::OPCODE::EVSTWHOX) + .value("EVSTWWE", LIEF::assembly::powerpc::OPCODE::EVSTWWE) + .value("EVSTWWEX", LIEF::assembly::powerpc::OPCODE::EVSTWWEX) + .value("EVSTWWO", LIEF::assembly::powerpc::OPCODE::EVSTWWO) + .value("EVSTWWOX", LIEF::assembly::powerpc::OPCODE::EVSTWWOX) + .value("EVSUBFSMIAAW", LIEF::assembly::powerpc::OPCODE::EVSUBFSMIAAW) + .value("EVSUBFSSIAAW", LIEF::assembly::powerpc::OPCODE::EVSUBFSSIAAW) + .value("EVSUBFUMIAAW", LIEF::assembly::powerpc::OPCODE::EVSUBFUMIAAW) + .value("EVSUBFUSIAAW", LIEF::assembly::powerpc::OPCODE::EVSUBFUSIAAW) + .value("EVSUBFW", LIEF::assembly::powerpc::OPCODE::EVSUBFW) + .value("EVSUBIFW", LIEF::assembly::powerpc::OPCODE::EVSUBIFW) + .value("EVXOR", LIEF::assembly::powerpc::OPCODE::EVXOR) + .value("EXTSB", LIEF::assembly::powerpc::OPCODE::EXTSB) + .value("EXTSB8", LIEF::assembly::powerpc::OPCODE::EXTSB8) + .value("EXTSB8_32_64", LIEF::assembly::powerpc::OPCODE::EXTSB8_32_64) + .value("EXTSB8_rec", LIEF::assembly::powerpc::OPCODE::EXTSB8_rec) + .value("EXTSB_rec", LIEF::assembly::powerpc::OPCODE::EXTSB_rec) + .value("EXTSH", LIEF::assembly::powerpc::OPCODE::EXTSH) + .value("EXTSH8", LIEF::assembly::powerpc::OPCODE::EXTSH8) + .value("EXTSH8_32_64", LIEF::assembly::powerpc::OPCODE::EXTSH8_32_64) + .value("EXTSH8_rec", LIEF::assembly::powerpc::OPCODE::EXTSH8_rec) + .value("EXTSH_rec", LIEF::assembly::powerpc::OPCODE::EXTSH_rec) + .value("EXTSW", LIEF::assembly::powerpc::OPCODE::EXTSW) + .value("EXTSWSLI", LIEF::assembly::powerpc::OPCODE::EXTSWSLI) + .value("EXTSWSLI_32_64", LIEF::assembly::powerpc::OPCODE::EXTSWSLI_32_64) + .value("EXTSWSLI_32_64_rec", LIEF::assembly::powerpc::OPCODE::EXTSWSLI_32_64_rec) + .value("EXTSWSLI_rec", LIEF::assembly::powerpc::OPCODE::EXTSWSLI_rec) + .value("EXTSW_32", LIEF::assembly::powerpc::OPCODE::EXTSW_32) + .value("EXTSW_32_64", LIEF::assembly::powerpc::OPCODE::EXTSW_32_64) + .value("EXTSW_32_64_rec", LIEF::assembly::powerpc::OPCODE::EXTSW_32_64_rec) + .value("EXTSW_rec", LIEF::assembly::powerpc::OPCODE::EXTSW_rec) + .value("EnforceIEIO", LIEF::assembly::powerpc::OPCODE::EnforceIEIO) + .value("FABSD", LIEF::assembly::powerpc::OPCODE::FABSD) + .value("FABSD_rec", LIEF::assembly::powerpc::OPCODE::FABSD_rec) + .value("FABSS", LIEF::assembly::powerpc::OPCODE::FABSS) + .value("FABSS_rec", LIEF::assembly::powerpc::OPCODE::FABSS_rec) + .value("FADD", LIEF::assembly::powerpc::OPCODE::FADD) + .value("FADDS", LIEF::assembly::powerpc::OPCODE::FADDS) + .value("FADDS_rec", LIEF::assembly::powerpc::OPCODE::FADDS_rec) + .value("FADD_rec", LIEF::assembly::powerpc::OPCODE::FADD_rec) + .value("FADDrtz", LIEF::assembly::powerpc::OPCODE::FADDrtz) + .value("FCFID", LIEF::assembly::powerpc::OPCODE::FCFID) + .value("FCFIDS", LIEF::assembly::powerpc::OPCODE::FCFIDS); + opcodes.value("FCFIDS_rec", LIEF::assembly::powerpc::OPCODE::FCFIDS_rec) + .value("FCFIDU", LIEF::assembly::powerpc::OPCODE::FCFIDU) + .value("FCFIDUS", LIEF::assembly::powerpc::OPCODE::FCFIDUS) + .value("FCFIDUS_rec", LIEF::assembly::powerpc::OPCODE::FCFIDUS_rec) + .value("FCFIDU_rec", LIEF::assembly::powerpc::OPCODE::FCFIDU_rec) + .value("FCFID_rec", LIEF::assembly::powerpc::OPCODE::FCFID_rec) + .value("FCMPOD", LIEF::assembly::powerpc::OPCODE::FCMPOD) + .value("FCMPOS", LIEF::assembly::powerpc::OPCODE::FCMPOS) + .value("FCMPUD", LIEF::assembly::powerpc::OPCODE::FCMPUD) + .value("FCMPUS", LIEF::assembly::powerpc::OPCODE::FCMPUS) + .value("FCPSGND", LIEF::assembly::powerpc::OPCODE::FCPSGND) + .value("FCPSGND_rec", LIEF::assembly::powerpc::OPCODE::FCPSGND_rec) + .value("FCPSGNS", LIEF::assembly::powerpc::OPCODE::FCPSGNS) + .value("FCPSGNS_rec", LIEF::assembly::powerpc::OPCODE::FCPSGNS_rec) + .value("FCTID", LIEF::assembly::powerpc::OPCODE::FCTID) + .value("FCTIDU", LIEF::assembly::powerpc::OPCODE::FCTIDU) + .value("FCTIDUZ", LIEF::assembly::powerpc::OPCODE::FCTIDUZ) + .value("FCTIDUZ_rec", LIEF::assembly::powerpc::OPCODE::FCTIDUZ_rec) + .value("FCTIDU_rec", LIEF::assembly::powerpc::OPCODE::FCTIDU_rec) + .value("FCTIDZ", LIEF::assembly::powerpc::OPCODE::FCTIDZ) + .value("FCTIDZ_rec", LIEF::assembly::powerpc::OPCODE::FCTIDZ_rec) + .value("FCTID_rec", LIEF::assembly::powerpc::OPCODE::FCTID_rec) + .value("FCTIW", LIEF::assembly::powerpc::OPCODE::FCTIW) + .value("FCTIWU", LIEF::assembly::powerpc::OPCODE::FCTIWU) + .value("FCTIWUZ", LIEF::assembly::powerpc::OPCODE::FCTIWUZ) + .value("FCTIWUZ_rec", LIEF::assembly::powerpc::OPCODE::FCTIWUZ_rec) + .value("FCTIWU_rec", LIEF::assembly::powerpc::OPCODE::FCTIWU_rec) + .value("FCTIWZ", LIEF::assembly::powerpc::OPCODE::FCTIWZ) + .value("FCTIWZ_rec", LIEF::assembly::powerpc::OPCODE::FCTIWZ_rec) + .value("FCTIW_rec", LIEF::assembly::powerpc::OPCODE::FCTIW_rec) + .value("FDIV", LIEF::assembly::powerpc::OPCODE::FDIV) + .value("FDIVS", LIEF::assembly::powerpc::OPCODE::FDIVS) + .value("FDIVS_rec", LIEF::assembly::powerpc::OPCODE::FDIVS_rec) + .value("FDIV_rec", LIEF::assembly::powerpc::OPCODE::FDIV_rec) + .value("FENCE", LIEF::assembly::powerpc::OPCODE::FENCE) + .value("FMADD", LIEF::assembly::powerpc::OPCODE::FMADD) + .value("FMADDS", LIEF::assembly::powerpc::OPCODE::FMADDS) + .value("FMADDS_rec", LIEF::assembly::powerpc::OPCODE::FMADDS_rec) + .value("FMADD_rec", LIEF::assembly::powerpc::OPCODE::FMADD_rec) + .value("FMR", LIEF::assembly::powerpc::OPCODE::FMR) + .value("FMR_rec", LIEF::assembly::powerpc::OPCODE::FMR_rec) + .value("FMSUB", LIEF::assembly::powerpc::OPCODE::FMSUB) + .value("FMSUBS", LIEF::assembly::powerpc::OPCODE::FMSUBS) + .value("FMSUBS_rec", LIEF::assembly::powerpc::OPCODE::FMSUBS_rec) + .value("FMSUB_rec", LIEF::assembly::powerpc::OPCODE::FMSUB_rec) + .value("FMUL", LIEF::assembly::powerpc::OPCODE::FMUL) + .value("FMULS", LIEF::assembly::powerpc::OPCODE::FMULS) + .value("FMULS_rec", LIEF::assembly::powerpc::OPCODE::FMULS_rec) + .value("FMUL_rec", LIEF::assembly::powerpc::OPCODE::FMUL_rec) + .value("FNABSD", LIEF::assembly::powerpc::OPCODE::FNABSD) + .value("FNABSD_rec", LIEF::assembly::powerpc::OPCODE::FNABSD_rec) + .value("FNABSS", LIEF::assembly::powerpc::OPCODE::FNABSS) + .value("FNABSS_rec", LIEF::assembly::powerpc::OPCODE::FNABSS_rec) + .value("FNEGD", LIEF::assembly::powerpc::OPCODE::FNEGD) + .value("FNEGD_rec", LIEF::assembly::powerpc::OPCODE::FNEGD_rec) + .value("FNEGS", LIEF::assembly::powerpc::OPCODE::FNEGS) + .value("FNEGS_rec", LIEF::assembly::powerpc::OPCODE::FNEGS_rec) + .value("FNMADD", LIEF::assembly::powerpc::OPCODE::FNMADD) + .value("FNMADDS", LIEF::assembly::powerpc::OPCODE::FNMADDS) + .value("FNMADDS_rec", LIEF::assembly::powerpc::OPCODE::FNMADDS_rec) + .value("FNMADD_rec", LIEF::assembly::powerpc::OPCODE::FNMADD_rec) + .value("FNMSUB", LIEF::assembly::powerpc::OPCODE::FNMSUB) + .value("FNMSUBS", LIEF::assembly::powerpc::OPCODE::FNMSUBS) + .value("FNMSUBS_rec", LIEF::assembly::powerpc::OPCODE::FNMSUBS_rec) + .value("FNMSUB_rec", LIEF::assembly::powerpc::OPCODE::FNMSUB_rec) + .value("FRE", LIEF::assembly::powerpc::OPCODE::FRE) + .value("FRES", LIEF::assembly::powerpc::OPCODE::FRES) + .value("FRES_rec", LIEF::assembly::powerpc::OPCODE::FRES_rec) + .value("FRE_rec", LIEF::assembly::powerpc::OPCODE::FRE_rec) + .value("FRIMD", LIEF::assembly::powerpc::OPCODE::FRIMD) + .value("FRIMD_rec", LIEF::assembly::powerpc::OPCODE::FRIMD_rec) + .value("FRIMS", LIEF::assembly::powerpc::OPCODE::FRIMS) + .value("FRIMS_rec", LIEF::assembly::powerpc::OPCODE::FRIMS_rec) + .value("FRIND", LIEF::assembly::powerpc::OPCODE::FRIND) + .value("FRIND_rec", LIEF::assembly::powerpc::OPCODE::FRIND_rec) + .value("FRINS", LIEF::assembly::powerpc::OPCODE::FRINS) + .value("FRINS_rec", LIEF::assembly::powerpc::OPCODE::FRINS_rec) + .value("FRIPD", LIEF::assembly::powerpc::OPCODE::FRIPD) + .value("FRIPD_rec", LIEF::assembly::powerpc::OPCODE::FRIPD_rec) + .value("FRIPS", LIEF::assembly::powerpc::OPCODE::FRIPS) + .value("FRIPS_rec", LIEF::assembly::powerpc::OPCODE::FRIPS_rec) + .value("FRIZD", LIEF::assembly::powerpc::OPCODE::FRIZD) + .value("FRIZD_rec", LIEF::assembly::powerpc::OPCODE::FRIZD_rec) + .value("FRIZS", LIEF::assembly::powerpc::OPCODE::FRIZS) + .value("FRIZS_rec", LIEF::assembly::powerpc::OPCODE::FRIZS_rec) + .value("FRSP", LIEF::assembly::powerpc::OPCODE::FRSP) + .value("FRSP_rec", LIEF::assembly::powerpc::OPCODE::FRSP_rec) + .value("FRSQRTE", LIEF::assembly::powerpc::OPCODE::FRSQRTE) + .value("FRSQRTES", LIEF::assembly::powerpc::OPCODE::FRSQRTES) + .value("FRSQRTES_rec", LIEF::assembly::powerpc::OPCODE::FRSQRTES_rec) + .value("FRSQRTE_rec", LIEF::assembly::powerpc::OPCODE::FRSQRTE_rec) + .value("FSELD", LIEF::assembly::powerpc::OPCODE::FSELD) + .value("FSELD_rec", LIEF::assembly::powerpc::OPCODE::FSELD_rec) + .value("FSELS", LIEF::assembly::powerpc::OPCODE::FSELS) + .value("FSELS_rec", LIEF::assembly::powerpc::OPCODE::FSELS_rec) + .value("FSQRT", LIEF::assembly::powerpc::OPCODE::FSQRT) + .value("FSQRTS", LIEF::assembly::powerpc::OPCODE::FSQRTS) + .value("FSQRTS_rec", LIEF::assembly::powerpc::OPCODE::FSQRTS_rec) + .value("FSQRT_rec", LIEF::assembly::powerpc::OPCODE::FSQRT_rec) + .value("FSUB", LIEF::assembly::powerpc::OPCODE::FSUB) + .value("FSUBS", LIEF::assembly::powerpc::OPCODE::FSUBS) + .value("FSUBS_rec", LIEF::assembly::powerpc::OPCODE::FSUBS_rec) + .value("FSUB_rec", LIEF::assembly::powerpc::OPCODE::FSUB_rec) + .value("FTDIV", LIEF::assembly::powerpc::OPCODE::FTDIV) + .value("FTSQRT", LIEF::assembly::powerpc::OPCODE::FTSQRT) + .value("GETtlsADDR", LIEF::assembly::powerpc::OPCODE::GETtlsADDR) + .value("GETtlsADDR32", LIEF::assembly::powerpc::OPCODE::GETtlsADDR32) + .value("GETtlsADDR32AIX", LIEF::assembly::powerpc::OPCODE::GETtlsADDR32AIX) + .value("GETtlsADDR64AIX", LIEF::assembly::powerpc::OPCODE::GETtlsADDR64AIX) + .value("GETtlsADDRPCREL", LIEF::assembly::powerpc::OPCODE::GETtlsADDRPCREL) + .value("GETtlsMOD32AIX", LIEF::assembly::powerpc::OPCODE::GETtlsMOD32AIX) + .value("GETtlsMOD64AIX", LIEF::assembly::powerpc::OPCODE::GETtlsMOD64AIX) + .value("GETtlsTpointer32AIX", LIEF::assembly::powerpc::OPCODE::GETtlsTpointer32AIX) + .value("GETtlsldADDR", LIEF::assembly::powerpc::OPCODE::GETtlsldADDR) + .value("GETtlsldADDR32", LIEF::assembly::powerpc::OPCODE::GETtlsldADDR32) + .value("GETtlsldADDRPCREL", LIEF::assembly::powerpc::OPCODE::GETtlsldADDRPCREL) + .value("HASHCHK", LIEF::assembly::powerpc::OPCODE::HASHCHK) + .value("HASHCHK8", LIEF::assembly::powerpc::OPCODE::HASHCHK8) + .value("HASHCHKP", LIEF::assembly::powerpc::OPCODE::HASHCHKP) + .value("HASHCHKP8", LIEF::assembly::powerpc::OPCODE::HASHCHKP8) + .value("HASHST", LIEF::assembly::powerpc::OPCODE::HASHST) + .value("HASHST8", LIEF::assembly::powerpc::OPCODE::HASHST8) + .value("HASHSTP", LIEF::assembly::powerpc::OPCODE::HASHSTP) + .value("HASHSTP8", LIEF::assembly::powerpc::OPCODE::HASHSTP8) + .value("HRFID", LIEF::assembly::powerpc::OPCODE::HRFID) + .value("ICBI", LIEF::assembly::powerpc::OPCODE::ICBI) + .value("ICBIEP", LIEF::assembly::powerpc::OPCODE::ICBIEP) + .value("ICBLC", LIEF::assembly::powerpc::OPCODE::ICBLC) + .value("ICBLQ", LIEF::assembly::powerpc::OPCODE::ICBLQ) + .value("ICBT", LIEF::assembly::powerpc::OPCODE::ICBT) + .value("ICBTLS", LIEF::assembly::powerpc::OPCODE::ICBTLS) + .value("ICCCI", LIEF::assembly::powerpc::OPCODE::ICCCI) + .value("ISEL", LIEF::assembly::powerpc::OPCODE::ISEL) + .value("ISEL8", LIEF::assembly::powerpc::OPCODE::ISEL8) + .value("ISYNC", LIEF::assembly::powerpc::OPCODE::ISYNC) + .value("LA", LIEF::assembly::powerpc::OPCODE::LA) + .value("LA8", LIEF::assembly::powerpc::OPCODE::LA8) + .value("LBARX", LIEF::assembly::powerpc::OPCODE::LBARX) + .value("LBARXL", LIEF::assembly::powerpc::OPCODE::LBARXL) + .value("LBEPX", LIEF::assembly::powerpc::OPCODE::LBEPX) + .value("LBZ", LIEF::assembly::powerpc::OPCODE::LBZ) + .value("LBZ8", LIEF::assembly::powerpc::OPCODE::LBZ8) + .value("LBZCIX", LIEF::assembly::powerpc::OPCODE::LBZCIX) + .value("LBZU", LIEF::assembly::powerpc::OPCODE::LBZU) + .value("LBZU8", LIEF::assembly::powerpc::OPCODE::LBZU8) + .value("LBZUX", LIEF::assembly::powerpc::OPCODE::LBZUX) + .value("LBZUX8", LIEF::assembly::powerpc::OPCODE::LBZUX8) + .value("LBZX", LIEF::assembly::powerpc::OPCODE::LBZX) + .value("LBZX8", LIEF::assembly::powerpc::OPCODE::LBZX8) + .value("LBZXTLS", LIEF::assembly::powerpc::OPCODE::LBZXTLS) + .value("LBZXTLS_", LIEF::assembly::powerpc::OPCODE::LBZXTLS_) + .value("LBZXTLS_32", LIEF::assembly::powerpc::OPCODE::LBZXTLS_32) + .value("LD", LIEF::assembly::powerpc::OPCODE::LD) + .value("LDARX", LIEF::assembly::powerpc::OPCODE::LDARX) + .value("LDARXL", LIEF::assembly::powerpc::OPCODE::LDARXL) + .value("LDAT", LIEF::assembly::powerpc::OPCODE::LDAT) + .value("LDAT_PSEUDO", LIEF::assembly::powerpc::OPCODE::LDAT_PSEUDO) + .value("LDBRX", LIEF::assembly::powerpc::OPCODE::LDBRX) + .value("LDCIX", LIEF::assembly::powerpc::OPCODE::LDCIX) + .value("LDU", LIEF::assembly::powerpc::OPCODE::LDU) + .value("LDUX", LIEF::assembly::powerpc::OPCODE::LDUX) + .value("LDX", LIEF::assembly::powerpc::OPCODE::LDX) + .value("LDXTLS", LIEF::assembly::powerpc::OPCODE::LDXTLS) + .value("LDXTLS_", LIEF::assembly::powerpc::OPCODE::LDXTLS_) + .value("LDgotTprelL", LIEF::assembly::powerpc::OPCODE::LDgotTprelL) + .value("LDgotTprelL32", LIEF::assembly::powerpc::OPCODE::LDgotTprelL32) + .value("LDtoc", LIEF::assembly::powerpc::OPCODE::LDtoc) + .value("LDtocBA", LIEF::assembly::powerpc::OPCODE::LDtocBA) + .value("LDtocCPT", LIEF::assembly::powerpc::OPCODE::LDtocCPT) + .value("LDtocJTI", LIEF::assembly::powerpc::OPCODE::LDtocJTI) + .value("LDtocL", LIEF::assembly::powerpc::OPCODE::LDtocL) + .value("LFD", LIEF::assembly::powerpc::OPCODE::LFD) + .value("LFDEPX", LIEF::assembly::powerpc::OPCODE::LFDEPX) + .value("LFDU", LIEF::assembly::powerpc::OPCODE::LFDU) + .value("LFDUX", LIEF::assembly::powerpc::OPCODE::LFDUX) + .value("LFDX", LIEF::assembly::powerpc::OPCODE::LFDX) + .value("LFDXTLS", LIEF::assembly::powerpc::OPCODE::LFDXTLS) + .value("LFDXTLS_", LIEF::assembly::powerpc::OPCODE::LFDXTLS_) + .value("LFIWAX", LIEF::assembly::powerpc::OPCODE::LFIWAX) + .value("LFIWZX", LIEF::assembly::powerpc::OPCODE::LFIWZX) + .value("LFS", LIEF::assembly::powerpc::OPCODE::LFS) + .value("LFSU", LIEF::assembly::powerpc::OPCODE::LFSU) + .value("LFSUX", LIEF::assembly::powerpc::OPCODE::LFSUX) + .value("LFSX", LIEF::assembly::powerpc::OPCODE::LFSX) + .value("LFSXTLS", LIEF::assembly::powerpc::OPCODE::LFSXTLS) + .value("LFSXTLS_", LIEF::assembly::powerpc::OPCODE::LFSXTLS_) + .value("LHA", LIEF::assembly::powerpc::OPCODE::LHA) + .value("LHA8", LIEF::assembly::powerpc::OPCODE::LHA8) + .value("LHARX", LIEF::assembly::powerpc::OPCODE::LHARX) + .value("LHARXL", LIEF::assembly::powerpc::OPCODE::LHARXL) + .value("LHAU", LIEF::assembly::powerpc::OPCODE::LHAU) + .value("LHAU8", LIEF::assembly::powerpc::OPCODE::LHAU8) + .value("LHAUX", LIEF::assembly::powerpc::OPCODE::LHAUX) + .value("LHAUX8", LIEF::assembly::powerpc::OPCODE::LHAUX8) + .value("LHAX", LIEF::assembly::powerpc::OPCODE::LHAX) + .value("LHAX8", LIEF::assembly::powerpc::OPCODE::LHAX8) + .value("LHAXTLS", LIEF::assembly::powerpc::OPCODE::LHAXTLS) + .value("LHAXTLS_", LIEF::assembly::powerpc::OPCODE::LHAXTLS_) + .value("LHAXTLS_32", LIEF::assembly::powerpc::OPCODE::LHAXTLS_32) + .value("LHBRX", LIEF::assembly::powerpc::OPCODE::LHBRX) + .value("LHBRX8", LIEF::assembly::powerpc::OPCODE::LHBRX8) + .value("LHEPX", LIEF::assembly::powerpc::OPCODE::LHEPX) + .value("LHZ", LIEF::assembly::powerpc::OPCODE::LHZ) + .value("LHZ8", LIEF::assembly::powerpc::OPCODE::LHZ8) + .value("LHZCIX", LIEF::assembly::powerpc::OPCODE::LHZCIX) + .value("LHZU", LIEF::assembly::powerpc::OPCODE::LHZU) + .value("LHZU8", LIEF::assembly::powerpc::OPCODE::LHZU8) + .value("LHZUX", LIEF::assembly::powerpc::OPCODE::LHZUX) + .value("LHZUX8", LIEF::assembly::powerpc::OPCODE::LHZUX8) + .value("LHZX", LIEF::assembly::powerpc::OPCODE::LHZX) + .value("LHZX8", LIEF::assembly::powerpc::OPCODE::LHZX8) + .value("LHZXTLS", LIEF::assembly::powerpc::OPCODE::LHZXTLS) + .value("LHZXTLS_", LIEF::assembly::powerpc::OPCODE::LHZXTLS_) + .value("LHZXTLS_32", LIEF::assembly::powerpc::OPCODE::LHZXTLS_32) + .value("LI", LIEF::assembly::powerpc::OPCODE::LI) + .value("LI8", LIEF::assembly::powerpc::OPCODE::LI8) + .value("LIS", LIEF::assembly::powerpc::OPCODE::LIS) + .value("LIS8", LIEF::assembly::powerpc::OPCODE::LIS8) + .value("LMW", LIEF::assembly::powerpc::OPCODE::LMW) + .value("LQ", LIEF::assembly::powerpc::OPCODE::LQ) + .value("LQARX", LIEF::assembly::powerpc::OPCODE::LQARX) + .value("LQARXL", LIEF::assembly::powerpc::OPCODE::LQARXL) + .value("LQX_PSEUDO", LIEF::assembly::powerpc::OPCODE::LQX_PSEUDO) + .value("LSWI", LIEF::assembly::powerpc::OPCODE::LSWI) + .value("LVEBX", LIEF::assembly::powerpc::OPCODE::LVEBX) + .value("LVEHX", LIEF::assembly::powerpc::OPCODE::LVEHX) + .value("LVEWX", LIEF::assembly::powerpc::OPCODE::LVEWX) + .value("LVSL", LIEF::assembly::powerpc::OPCODE::LVSL) + .value("LVSR", LIEF::assembly::powerpc::OPCODE::LVSR) + .value("LVX", LIEF::assembly::powerpc::OPCODE::LVX) + .value("LVXL", LIEF::assembly::powerpc::OPCODE::LVXL) + .value("LWA", LIEF::assembly::powerpc::OPCODE::LWA) + .value("LWARX", LIEF::assembly::powerpc::OPCODE::LWARX) + .value("LWARXL", LIEF::assembly::powerpc::OPCODE::LWARXL) + .value("LWAT", LIEF::assembly::powerpc::OPCODE::LWAT) + .value("LWAT_PSEUDO", LIEF::assembly::powerpc::OPCODE::LWAT_PSEUDO) + .value("LWAUX", LIEF::assembly::powerpc::OPCODE::LWAUX) + .value("LWAX", LIEF::assembly::powerpc::OPCODE::LWAX) + .value("LWAXTLS", LIEF::assembly::powerpc::OPCODE::LWAXTLS) + .value("LWAXTLS_", LIEF::assembly::powerpc::OPCODE::LWAXTLS_) + .value("LWAXTLS_32", LIEF::assembly::powerpc::OPCODE::LWAXTLS_32) + .value("LWAX_32", LIEF::assembly::powerpc::OPCODE::LWAX_32) + .value("LWA_32", LIEF::assembly::powerpc::OPCODE::LWA_32) + .value("LWBRX", LIEF::assembly::powerpc::OPCODE::LWBRX) + .value("LWBRX8", LIEF::assembly::powerpc::OPCODE::LWBRX8) + .value("LWEPX", LIEF::assembly::powerpc::OPCODE::LWEPX) + .value("LWZ", LIEF::assembly::powerpc::OPCODE::LWZ) + .value("LWZ8", LIEF::assembly::powerpc::OPCODE::LWZ8) + .value("LWZCIX", LIEF::assembly::powerpc::OPCODE::LWZCIX) + .value("LWZU", LIEF::assembly::powerpc::OPCODE::LWZU) + .value("LWZU8", LIEF::assembly::powerpc::OPCODE::LWZU8) + .value("LWZUX", LIEF::assembly::powerpc::OPCODE::LWZUX) + .value("LWZUX8", LIEF::assembly::powerpc::OPCODE::LWZUX8) + .value("LWZX", LIEF::assembly::powerpc::OPCODE::LWZX) + .value("LWZX8", LIEF::assembly::powerpc::OPCODE::LWZX8) + .value("LWZXTLS", LIEF::assembly::powerpc::OPCODE::LWZXTLS) + .value("LWZXTLS_", LIEF::assembly::powerpc::OPCODE::LWZXTLS_) + .value("LWZXTLS_32", LIEF::assembly::powerpc::OPCODE::LWZXTLS_32) + .value("LWZtoc", LIEF::assembly::powerpc::OPCODE::LWZtoc) + .value("LWZtocL", LIEF::assembly::powerpc::OPCODE::LWZtocL) + .value("LXSD", LIEF::assembly::powerpc::OPCODE::LXSD) + .value("LXSDX", LIEF::assembly::powerpc::OPCODE::LXSDX) + .value("LXSIBZX", LIEF::assembly::powerpc::OPCODE::LXSIBZX) + .value("LXSIHZX", LIEF::assembly::powerpc::OPCODE::LXSIHZX) + .value("LXSIWAX", LIEF::assembly::powerpc::OPCODE::LXSIWAX) + .value("LXSIWZX", LIEF::assembly::powerpc::OPCODE::LXSIWZX) + .value("LXSSP", LIEF::assembly::powerpc::OPCODE::LXSSP) + .value("LXSSPX", LIEF::assembly::powerpc::OPCODE::LXSSPX) + .value("LXV", LIEF::assembly::powerpc::OPCODE::LXV) + .value("LXVB16X", LIEF::assembly::powerpc::OPCODE::LXVB16X) + .value("LXVD2X", LIEF::assembly::powerpc::OPCODE::LXVD2X) + .value("LXVDSX", LIEF::assembly::powerpc::OPCODE::LXVDSX) + .value("LXVH8X", LIEF::assembly::powerpc::OPCODE::LXVH8X) + .value("LXVKQ", LIEF::assembly::powerpc::OPCODE::LXVKQ) + .value("LXVL", LIEF::assembly::powerpc::OPCODE::LXVL) + .value("LXVLL", LIEF::assembly::powerpc::OPCODE::LXVLL) + .value("LXVP", LIEF::assembly::powerpc::OPCODE::LXVP) + .value("LXVPB32X", LIEF::assembly::powerpc::OPCODE::LXVPB32X) + .value("LXVPRL", LIEF::assembly::powerpc::OPCODE::LXVPRL) + .value("LXVPRLL", LIEF::assembly::powerpc::OPCODE::LXVPRLL) + .value("LXVPX", LIEF::assembly::powerpc::OPCODE::LXVPX) + .value("LXVRBX", LIEF::assembly::powerpc::OPCODE::LXVRBX) + .value("LXVRDX", LIEF::assembly::powerpc::OPCODE::LXVRDX) + .value("LXVRHX", LIEF::assembly::powerpc::OPCODE::LXVRHX) + .value("LXVRL", LIEF::assembly::powerpc::OPCODE::LXVRL) + .value("LXVRLL", LIEF::assembly::powerpc::OPCODE::LXVRLL) + .value("LXVRWX", LIEF::assembly::powerpc::OPCODE::LXVRWX) + .value("LXVW4X", LIEF::assembly::powerpc::OPCODE::LXVW4X) + .value("LXVWSX", LIEF::assembly::powerpc::OPCODE::LXVWSX) + .value("LXVX", LIEF::assembly::powerpc::OPCODE::LXVX) + .value("MADDHD", LIEF::assembly::powerpc::OPCODE::MADDHD) + .value("MADDHDU", LIEF::assembly::powerpc::OPCODE::MADDHDU) + .value("MADDLD", LIEF::assembly::powerpc::OPCODE::MADDLD) + .value("MADDLD8", LIEF::assembly::powerpc::OPCODE::MADDLD8) + .value("MBAR", LIEF::assembly::powerpc::OPCODE::MBAR) + .value("MCRF", LIEF::assembly::powerpc::OPCODE::MCRF) + .value("MCRFS", LIEF::assembly::powerpc::OPCODE::MCRFS) + .value("MCRXRX", LIEF::assembly::powerpc::OPCODE::MCRXRX) + .value("MFBHRBE", LIEF::assembly::powerpc::OPCODE::MFBHRBE) + .value("MFCR", LIEF::assembly::powerpc::OPCODE::MFCR); + opcodes.value("MFCR8", LIEF::assembly::powerpc::OPCODE::MFCR8) + .value("MFCTR", LIEF::assembly::powerpc::OPCODE::MFCTR) + .value("MFCTR8", LIEF::assembly::powerpc::OPCODE::MFCTR8) + .value("MFDCR", LIEF::assembly::powerpc::OPCODE::MFDCR) + .value("MFFS", LIEF::assembly::powerpc::OPCODE::MFFS) + .value("MFFSCDRN", LIEF::assembly::powerpc::OPCODE::MFFSCDRN) + .value("MFFSCDRNI", LIEF::assembly::powerpc::OPCODE::MFFSCDRNI) + .value("MFFSCE", LIEF::assembly::powerpc::OPCODE::MFFSCE) + .value("MFFSCRN", LIEF::assembly::powerpc::OPCODE::MFFSCRN) + .value("MFFSCRNI", LIEF::assembly::powerpc::OPCODE::MFFSCRNI) + .value("MFFSL", LIEF::assembly::powerpc::OPCODE::MFFSL) + .value("MFFS_rec", LIEF::assembly::powerpc::OPCODE::MFFS_rec) + .value("MFLR", LIEF::assembly::powerpc::OPCODE::MFLR) + .value("MFLR8", LIEF::assembly::powerpc::OPCODE::MFLR8) + .value("MFMSR", LIEF::assembly::powerpc::OPCODE::MFMSR) + .value("MFOCRF", LIEF::assembly::powerpc::OPCODE::MFOCRF) + .value("MFOCRF8", LIEF::assembly::powerpc::OPCODE::MFOCRF8) + .value("MFPMR", LIEF::assembly::powerpc::OPCODE::MFPMR) + .value("MFSPR", LIEF::assembly::powerpc::OPCODE::MFSPR) + .value("MFSPR8", LIEF::assembly::powerpc::OPCODE::MFSPR8) + .value("MFSR", LIEF::assembly::powerpc::OPCODE::MFSR) + .value("MFSRIN", LIEF::assembly::powerpc::OPCODE::MFSRIN) + .value("MFTB", LIEF::assembly::powerpc::OPCODE::MFTB) + .value("MFTB8", LIEF::assembly::powerpc::OPCODE::MFTB8) + .value("MFUDSCR", LIEF::assembly::powerpc::OPCODE::MFUDSCR) + .value("MFVRD", LIEF::assembly::powerpc::OPCODE::MFVRD) + .value("MFVRSAVE", LIEF::assembly::powerpc::OPCODE::MFVRSAVE) + .value("MFVRSAVEv", LIEF::assembly::powerpc::OPCODE::MFVRSAVEv) + .value("MFVRWZ", LIEF::assembly::powerpc::OPCODE::MFVRWZ) + .value("MFVSCR", LIEF::assembly::powerpc::OPCODE::MFVSCR) + .value("MFVSRD", LIEF::assembly::powerpc::OPCODE::MFVSRD) + .value("MFVSRLD", LIEF::assembly::powerpc::OPCODE::MFVSRLD) + .value("MFVSRWZ", LIEF::assembly::powerpc::OPCODE::MFVSRWZ) + .value("MODSD", LIEF::assembly::powerpc::OPCODE::MODSD) + .value("MODSW", LIEF::assembly::powerpc::OPCODE::MODSW) + .value("MODUD", LIEF::assembly::powerpc::OPCODE::MODUD) + .value("MODUW", LIEF::assembly::powerpc::OPCODE::MODUW) + .value("MSGSYNC", LIEF::assembly::powerpc::OPCODE::MSGSYNC) + .value("MSYNC", LIEF::assembly::powerpc::OPCODE::MSYNC) + .value("MTCRF", LIEF::assembly::powerpc::OPCODE::MTCRF) + .value("MTCRF8", LIEF::assembly::powerpc::OPCODE::MTCRF8) + .value("MTCTR", LIEF::assembly::powerpc::OPCODE::MTCTR) + .value("MTCTR8", LIEF::assembly::powerpc::OPCODE::MTCTR8) + .value("MTCTR8loop", LIEF::assembly::powerpc::OPCODE::MTCTR8loop) + .value("MTCTRloop", LIEF::assembly::powerpc::OPCODE::MTCTRloop) + .value("MTDCR", LIEF::assembly::powerpc::OPCODE::MTDCR) + .value("MTFSB0", LIEF::assembly::powerpc::OPCODE::MTFSB0) + .value("MTFSB1", LIEF::assembly::powerpc::OPCODE::MTFSB1) + .value("MTFSF", LIEF::assembly::powerpc::OPCODE::MTFSF) + .value("MTFSFI", LIEF::assembly::powerpc::OPCODE::MTFSFI) + .value("MTFSFI_rec", LIEF::assembly::powerpc::OPCODE::MTFSFI_rec) + .value("MTFSFIb", LIEF::assembly::powerpc::OPCODE::MTFSFIb) + .value("MTFSF_rec", LIEF::assembly::powerpc::OPCODE::MTFSF_rec) + .value("MTFSFb", LIEF::assembly::powerpc::OPCODE::MTFSFb) + .value("MTLPL", LIEF::assembly::powerpc::OPCODE::MTLPL) + .value("MTLPL8", LIEF::assembly::powerpc::OPCODE::MTLPL8) + .value("MTLR", LIEF::assembly::powerpc::OPCODE::MTLR) + .value("MTLR8", LIEF::assembly::powerpc::OPCODE::MTLR8) + .value("MTMSR", LIEF::assembly::powerpc::OPCODE::MTMSR) + .value("MTMSRD", LIEF::assembly::powerpc::OPCODE::MTMSRD) + .value("MTOCRF", LIEF::assembly::powerpc::OPCODE::MTOCRF) + .value("MTOCRF8", LIEF::assembly::powerpc::OPCODE::MTOCRF8) + .value("MTPMR", LIEF::assembly::powerpc::OPCODE::MTPMR) + .value("MTSPR", LIEF::assembly::powerpc::OPCODE::MTSPR) + .value("MTSPR8", LIEF::assembly::powerpc::OPCODE::MTSPR8) + .value("MTSR", LIEF::assembly::powerpc::OPCODE::MTSR) + .value("MTSRIN", LIEF::assembly::powerpc::OPCODE::MTSRIN) + .value("MTUDSCR", LIEF::assembly::powerpc::OPCODE::MTUDSCR) + .value("MTVRD", LIEF::assembly::powerpc::OPCODE::MTVRD) + .value("MTVRSAVE", LIEF::assembly::powerpc::OPCODE::MTVRSAVE) + .value("MTVRSAVEv", LIEF::assembly::powerpc::OPCODE::MTVRSAVEv) + .value("MTVRWA", LIEF::assembly::powerpc::OPCODE::MTVRWA) + .value("MTVRWZ", LIEF::assembly::powerpc::OPCODE::MTVRWZ) + .value("MTVSCR", LIEF::assembly::powerpc::OPCODE::MTVSCR) + .value("MTVSRBM", LIEF::assembly::powerpc::OPCODE::MTVSRBM) + .value("MTVSRBMI", LIEF::assembly::powerpc::OPCODE::MTVSRBMI) + .value("MTVSRD", LIEF::assembly::powerpc::OPCODE::MTVSRD) + .value("MTVSRDD", LIEF::assembly::powerpc::OPCODE::MTVSRDD) + .value("MTVSRDM", LIEF::assembly::powerpc::OPCODE::MTVSRDM) + .value("MTVSRHM", LIEF::assembly::powerpc::OPCODE::MTVSRHM) + .value("MTVSRQM", LIEF::assembly::powerpc::OPCODE::MTVSRQM) + .value("MTVSRWA", LIEF::assembly::powerpc::OPCODE::MTVSRWA) + .value("MTVSRWM", LIEF::assembly::powerpc::OPCODE::MTVSRWM) + .value("MTVSRWS", LIEF::assembly::powerpc::OPCODE::MTVSRWS) + .value("MTVSRWZ", LIEF::assembly::powerpc::OPCODE::MTVSRWZ) + .value("MULHD", LIEF::assembly::powerpc::OPCODE::MULHD) + .value("MULHDU", LIEF::assembly::powerpc::OPCODE::MULHDU) + .value("MULHDU_rec", LIEF::assembly::powerpc::OPCODE::MULHDU_rec) + .value("MULHD_rec", LIEF::assembly::powerpc::OPCODE::MULHD_rec) + .value("MULHW", LIEF::assembly::powerpc::OPCODE::MULHW) + .value("MULHWU", LIEF::assembly::powerpc::OPCODE::MULHWU) + .value("MULHWU_rec", LIEF::assembly::powerpc::OPCODE::MULHWU_rec) + .value("MULHW_rec", LIEF::assembly::powerpc::OPCODE::MULHW_rec) + .value("MULLD", LIEF::assembly::powerpc::OPCODE::MULLD) + .value("MULLDO", LIEF::assembly::powerpc::OPCODE::MULLDO) + .value("MULLDO_rec", LIEF::assembly::powerpc::OPCODE::MULLDO_rec) + .value("MULLD_rec", LIEF::assembly::powerpc::OPCODE::MULLD_rec) + .value("MULLI", LIEF::assembly::powerpc::OPCODE::MULLI) + .value("MULLI8", LIEF::assembly::powerpc::OPCODE::MULLI8) + .value("MULLW", LIEF::assembly::powerpc::OPCODE::MULLW) + .value("MULLWO", LIEF::assembly::powerpc::OPCODE::MULLWO) + .value("MULLWO_rec", LIEF::assembly::powerpc::OPCODE::MULLWO_rec) + .value("MULLW_rec", LIEF::assembly::powerpc::OPCODE::MULLW_rec) + .value("MoveGOTtoLR", LIEF::assembly::powerpc::OPCODE::MoveGOTtoLR) + .value("MovePCtoLR", LIEF::assembly::powerpc::OPCODE::MovePCtoLR) + .value("MovePCtoLR8", LIEF::assembly::powerpc::OPCODE::MovePCtoLR8) + .value("NAND", LIEF::assembly::powerpc::OPCODE::NAND) + .value("NAND8", LIEF::assembly::powerpc::OPCODE::NAND8) + .value("NAND8_rec", LIEF::assembly::powerpc::OPCODE::NAND8_rec) + .value("NAND_rec", LIEF::assembly::powerpc::OPCODE::NAND_rec) + .value("NAP", LIEF::assembly::powerpc::OPCODE::NAP) + .value("NEG", LIEF::assembly::powerpc::OPCODE::NEG) + .value("NEG8", LIEF::assembly::powerpc::OPCODE::NEG8) + .value("NEG8O", LIEF::assembly::powerpc::OPCODE::NEG8O) + .value("NEG8O_rec", LIEF::assembly::powerpc::OPCODE::NEG8O_rec) + .value("NEG8_rec", LIEF::assembly::powerpc::OPCODE::NEG8_rec) + .value("NEGO", LIEF::assembly::powerpc::OPCODE::NEGO) + .value("NEGO_rec", LIEF::assembly::powerpc::OPCODE::NEGO_rec) + .value("NEG_rec", LIEF::assembly::powerpc::OPCODE::NEG_rec) + .value("NOP", LIEF::assembly::powerpc::OPCODE::NOP) + .value("NOP_GT_PWR6", LIEF::assembly::powerpc::OPCODE::NOP_GT_PWR6) + .value("NOP_GT_PWR7", LIEF::assembly::powerpc::OPCODE::NOP_GT_PWR7) + .value("NOR", LIEF::assembly::powerpc::OPCODE::NOR) + .value("NOR8", LIEF::assembly::powerpc::OPCODE::NOR8) + .value("NOR8_rec", LIEF::assembly::powerpc::OPCODE::NOR8_rec) + .value("NOR_rec", LIEF::assembly::powerpc::OPCODE::NOR_rec) + .value("OR", LIEF::assembly::powerpc::OPCODE::OR) + .value("OR8", LIEF::assembly::powerpc::OPCODE::OR8) + .value("OR8_rec", LIEF::assembly::powerpc::OPCODE::OR8_rec) + .value("ORC", LIEF::assembly::powerpc::OPCODE::ORC) + .value("ORC8", LIEF::assembly::powerpc::OPCODE::ORC8) + .value("ORC8_rec", LIEF::assembly::powerpc::OPCODE::ORC8_rec) + .value("ORC_rec", LIEF::assembly::powerpc::OPCODE::ORC_rec) + .value("ORI", LIEF::assembly::powerpc::OPCODE::ORI) + .value("ORI8", LIEF::assembly::powerpc::OPCODE::ORI8) + .value("ORIS", LIEF::assembly::powerpc::OPCODE::ORIS) + .value("ORIS8", LIEF::assembly::powerpc::OPCODE::ORIS8) + .value("OR_rec", LIEF::assembly::powerpc::OPCODE::OR_rec) + .value("PADDI", LIEF::assembly::powerpc::OPCODE::PADDI) + .value("PADDI8", LIEF::assembly::powerpc::OPCODE::PADDI8) + .value("PADDI8pc", LIEF::assembly::powerpc::OPCODE::PADDI8pc) + .value("PADDIS", LIEF::assembly::powerpc::OPCODE::PADDIS) + .value("PADDIS8", LIEF::assembly::powerpc::OPCODE::PADDIS8) + .value("PADDIS8pc", LIEF::assembly::powerpc::OPCODE::PADDIS8pc) + .value("PADDISpc", LIEF::assembly::powerpc::OPCODE::PADDISpc) + .value("PADDIdtprel", LIEF::assembly::powerpc::OPCODE::PADDIdtprel) + .value("PADDIpc", LIEF::assembly::powerpc::OPCODE::PADDIpc) + .value("PDEPD", LIEF::assembly::powerpc::OPCODE::PDEPD) + .value("PEXTD", LIEF::assembly::powerpc::OPCODE::PEXTD) + .value("PLA", LIEF::assembly::powerpc::OPCODE::PLA) + .value("PLA8", LIEF::assembly::powerpc::OPCODE::PLA8) + .value("PLA8pc", LIEF::assembly::powerpc::OPCODE::PLA8pc) + .value("PLApc", LIEF::assembly::powerpc::OPCODE::PLApc) + .value("PLBZ", LIEF::assembly::powerpc::OPCODE::PLBZ) + .value("PLBZ8", LIEF::assembly::powerpc::OPCODE::PLBZ8) + .value("PLBZ8nopc", LIEF::assembly::powerpc::OPCODE::PLBZ8nopc) + .value("PLBZ8onlypc", LIEF::assembly::powerpc::OPCODE::PLBZ8onlypc) + .value("PLBZ8pc", LIEF::assembly::powerpc::OPCODE::PLBZ8pc) + .value("PLBZnopc", LIEF::assembly::powerpc::OPCODE::PLBZnopc) + .value("PLBZonlypc", LIEF::assembly::powerpc::OPCODE::PLBZonlypc) + .value("PLBZpc", LIEF::assembly::powerpc::OPCODE::PLBZpc) + .value("PLD", LIEF::assembly::powerpc::OPCODE::PLD) + .value("PLDnopc", LIEF::assembly::powerpc::OPCODE::PLDnopc) + .value("PLDonlypc", LIEF::assembly::powerpc::OPCODE::PLDonlypc) + .value("PLDpc", LIEF::assembly::powerpc::OPCODE::PLDpc) + .value("PLFD", LIEF::assembly::powerpc::OPCODE::PLFD) + .value("PLFDnopc", LIEF::assembly::powerpc::OPCODE::PLFDnopc) + .value("PLFDonlypc", LIEF::assembly::powerpc::OPCODE::PLFDonlypc) + .value("PLFDpc", LIEF::assembly::powerpc::OPCODE::PLFDpc) + .value("PLFS", LIEF::assembly::powerpc::OPCODE::PLFS) + .value("PLFSnopc", LIEF::assembly::powerpc::OPCODE::PLFSnopc) + .value("PLFSonlypc", LIEF::assembly::powerpc::OPCODE::PLFSonlypc) + .value("PLFSpc", LIEF::assembly::powerpc::OPCODE::PLFSpc) + .value("PLHA", LIEF::assembly::powerpc::OPCODE::PLHA) + .value("PLHA8", LIEF::assembly::powerpc::OPCODE::PLHA8) + .value("PLHA8nopc", LIEF::assembly::powerpc::OPCODE::PLHA8nopc) + .value("PLHA8onlypc", LIEF::assembly::powerpc::OPCODE::PLHA8onlypc) + .value("PLHA8pc", LIEF::assembly::powerpc::OPCODE::PLHA8pc) + .value("PLHAnopc", LIEF::assembly::powerpc::OPCODE::PLHAnopc) + .value("PLHAonlypc", LIEF::assembly::powerpc::OPCODE::PLHAonlypc) + .value("PLHApc", LIEF::assembly::powerpc::OPCODE::PLHApc) + .value("PLHZ", LIEF::assembly::powerpc::OPCODE::PLHZ) + .value("PLHZ8", LIEF::assembly::powerpc::OPCODE::PLHZ8) + .value("PLHZ8nopc", LIEF::assembly::powerpc::OPCODE::PLHZ8nopc) + .value("PLHZ8onlypc", LIEF::assembly::powerpc::OPCODE::PLHZ8onlypc) + .value("PLHZ8pc", LIEF::assembly::powerpc::OPCODE::PLHZ8pc) + .value("PLHZnopc", LIEF::assembly::powerpc::OPCODE::PLHZnopc) + .value("PLHZonlypc", LIEF::assembly::powerpc::OPCODE::PLHZonlypc) + .value("PLHZpc", LIEF::assembly::powerpc::OPCODE::PLHZpc) + .value("PLI", LIEF::assembly::powerpc::OPCODE::PLI) + .value("PLI8", LIEF::assembly::powerpc::OPCODE::PLI8) + .value("PLWA", LIEF::assembly::powerpc::OPCODE::PLWA) + .value("PLWA8", LIEF::assembly::powerpc::OPCODE::PLWA8) + .value("PLWA8nopc", LIEF::assembly::powerpc::OPCODE::PLWA8nopc) + .value("PLWA8onlypc", LIEF::assembly::powerpc::OPCODE::PLWA8onlypc) + .value("PLWA8pc", LIEF::assembly::powerpc::OPCODE::PLWA8pc) + .value("PLWAnopc", LIEF::assembly::powerpc::OPCODE::PLWAnopc) + .value("PLWAonlypc", LIEF::assembly::powerpc::OPCODE::PLWAonlypc) + .value("PLWApc", LIEF::assembly::powerpc::OPCODE::PLWApc) + .value("PLWZ", LIEF::assembly::powerpc::OPCODE::PLWZ) + .value("PLWZ8", LIEF::assembly::powerpc::OPCODE::PLWZ8) + .value("PLWZ8nopc", LIEF::assembly::powerpc::OPCODE::PLWZ8nopc) + .value("PLWZ8onlypc", LIEF::assembly::powerpc::OPCODE::PLWZ8onlypc) + .value("PLWZ8pc", LIEF::assembly::powerpc::OPCODE::PLWZ8pc) + .value("PLWZnopc", LIEF::assembly::powerpc::OPCODE::PLWZnopc) + .value("PLWZonlypc", LIEF::assembly::powerpc::OPCODE::PLWZonlypc) + .value("PLWZpc", LIEF::assembly::powerpc::OPCODE::PLWZpc) + .value("PLXSD", LIEF::assembly::powerpc::OPCODE::PLXSD) + .value("PLXSDnopc", LIEF::assembly::powerpc::OPCODE::PLXSDnopc) + .value("PLXSDonlypc", LIEF::assembly::powerpc::OPCODE::PLXSDonlypc) + .value("PLXSDpc", LIEF::assembly::powerpc::OPCODE::PLXSDpc) + .value("PLXSSP", LIEF::assembly::powerpc::OPCODE::PLXSSP) + .value("PLXSSPnopc", LIEF::assembly::powerpc::OPCODE::PLXSSPnopc) + .value("PLXSSPonlypc", LIEF::assembly::powerpc::OPCODE::PLXSSPonlypc) + .value("PLXSSPpc", LIEF::assembly::powerpc::OPCODE::PLXSSPpc) + .value("PLXV", LIEF::assembly::powerpc::OPCODE::PLXV) + .value("PLXVP", LIEF::assembly::powerpc::OPCODE::PLXVP) + .value("PLXVPnopc", LIEF::assembly::powerpc::OPCODE::PLXVPnopc) + .value("PLXVPonlypc", LIEF::assembly::powerpc::OPCODE::PLXVPonlypc) + .value("PLXVPpc", LIEF::assembly::powerpc::OPCODE::PLXVPpc) + .value("PLXVnopc", LIEF::assembly::powerpc::OPCODE::PLXVnopc) + .value("PLXVonlypc", LIEF::assembly::powerpc::OPCODE::PLXVonlypc) + .value("PLXVpc", LIEF::assembly::powerpc::OPCODE::PLXVpc) + .value("PMDMXVBF16GERX2", LIEF::assembly::powerpc::OPCODE::PMDMXVBF16GERX2) + .value("PMDMXVBF16GERX2NN", LIEF::assembly::powerpc::OPCODE::PMDMXVBF16GERX2NN) + .value("PMDMXVBF16GERX2NP", LIEF::assembly::powerpc::OPCODE::PMDMXVBF16GERX2NP) + .value("PMDMXVBF16GERX2PN", LIEF::assembly::powerpc::OPCODE::PMDMXVBF16GERX2PN) + .value("PMDMXVBF16GERX2PP", LIEF::assembly::powerpc::OPCODE::PMDMXVBF16GERX2PP) + .value("PMDMXVF16GERX2", LIEF::assembly::powerpc::OPCODE::PMDMXVF16GERX2) + .value("PMDMXVF16GERX2NN", LIEF::assembly::powerpc::OPCODE::PMDMXVF16GERX2NN) + .value("PMDMXVF16GERX2NP", LIEF::assembly::powerpc::OPCODE::PMDMXVF16GERX2NP) + .value("PMDMXVF16GERX2PN", LIEF::assembly::powerpc::OPCODE::PMDMXVF16GERX2PN) + .value("PMDMXVF16GERX2PP", LIEF::assembly::powerpc::OPCODE::PMDMXVF16GERX2PP) + .value("PMDMXVI8GERX4", LIEF::assembly::powerpc::OPCODE::PMDMXVI8GERX4) + .value("PMDMXVI8GERX4PP", LIEF::assembly::powerpc::OPCODE::PMDMXVI8GERX4PP) + .value("PMDMXVI8GERX4SPP", LIEF::assembly::powerpc::OPCODE::PMDMXVI8GERX4SPP) + .value("PMXVBF16GER2", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2) + .value("PMXVBF16GER2NN", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2NN) + .value("PMXVBF16GER2NP", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2NP) + .value("PMXVBF16GER2PN", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2PN) + .value("PMXVBF16GER2PP", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2PP) + .value("PMXVBF16GER2W", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2W) + .value("PMXVBF16GER2WNN", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2WNN) + .value("PMXVBF16GER2WNP", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2WNP) + .value("PMXVBF16GER2WPN", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2WPN) + .value("PMXVBF16GER2WPP", LIEF::assembly::powerpc::OPCODE::PMXVBF16GER2WPP) + .value("PMXVF16GER2", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2) + .value("PMXVF16GER2NN", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2NN) + .value("PMXVF16GER2NP", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2NP) + .value("PMXVF16GER2PN", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2PN) + .value("PMXVF16GER2PP", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2PP) + .value("PMXVF16GER2W", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2W) + .value("PMXVF16GER2WNN", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2WNN) + .value("PMXVF16GER2WNP", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2WNP) + .value("PMXVF16GER2WPN", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2WPN) + .value("PMXVF16GER2WPP", LIEF::assembly::powerpc::OPCODE::PMXVF16GER2WPP) + .value("PMXVF32GER", LIEF::assembly::powerpc::OPCODE::PMXVF32GER) + .value("PMXVF32GERNN", LIEF::assembly::powerpc::OPCODE::PMXVF32GERNN) + .value("PMXVF32GERNP", LIEF::assembly::powerpc::OPCODE::PMXVF32GERNP) + .value("PMXVF32GERPN", LIEF::assembly::powerpc::OPCODE::PMXVF32GERPN) + .value("PMXVF32GERPP", LIEF::assembly::powerpc::OPCODE::PMXVF32GERPP) + .value("PMXVF32GERW", LIEF::assembly::powerpc::OPCODE::PMXVF32GERW) + .value("PMXVF32GERWNN", LIEF::assembly::powerpc::OPCODE::PMXVF32GERWNN) + .value("PMXVF32GERWNP", LIEF::assembly::powerpc::OPCODE::PMXVF32GERWNP) + .value("PMXVF32GERWPN", LIEF::assembly::powerpc::OPCODE::PMXVF32GERWPN) + .value("PMXVF32GERWPP", LIEF::assembly::powerpc::OPCODE::PMXVF32GERWPP) + .value("PMXVF64GER", LIEF::assembly::powerpc::OPCODE::PMXVF64GER) + .value("PMXVF64GERNN", LIEF::assembly::powerpc::OPCODE::PMXVF64GERNN) + .value("PMXVF64GERNP", LIEF::assembly::powerpc::OPCODE::PMXVF64GERNP) + .value("PMXVF64GERPN", LIEF::assembly::powerpc::OPCODE::PMXVF64GERPN) + .value("PMXVF64GERPP", LIEF::assembly::powerpc::OPCODE::PMXVF64GERPP) + .value("PMXVF64GERW", LIEF::assembly::powerpc::OPCODE::PMXVF64GERW) + .value("PMXVF64GERWNN", LIEF::assembly::powerpc::OPCODE::PMXVF64GERWNN) + .value("PMXVF64GERWNP", LIEF::assembly::powerpc::OPCODE::PMXVF64GERWNP) + .value("PMXVF64GERWPN", LIEF::assembly::powerpc::OPCODE::PMXVF64GERWPN) + .value("PMXVF64GERWPP", LIEF::assembly::powerpc::OPCODE::PMXVF64GERWPP) + .value("PMXVI16GER2", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2) + .value("PMXVI16GER2PP", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2PP) + .value("PMXVI16GER2S", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2S) + .value("PMXVI16GER2SPP", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2SPP) + .value("PMXVI16GER2SW", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2SW) + .value("PMXVI16GER2SWPP", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2SWPP) + .value("PMXVI16GER2W", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2W) + .value("PMXVI16GER2WPP", LIEF::assembly::powerpc::OPCODE::PMXVI16GER2WPP) + .value("PMXVI4GER8", LIEF::assembly::powerpc::OPCODE::PMXVI4GER8) + .value("PMXVI4GER8PP", LIEF::assembly::powerpc::OPCODE::PMXVI4GER8PP) + .value("PMXVI4GER8W", LIEF::assembly::powerpc::OPCODE::PMXVI4GER8W) + .value("PMXVI4GER8WPP", LIEF::assembly::powerpc::OPCODE::PMXVI4GER8WPP) + .value("PMXVI8GER4", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4) + .value("PMXVI8GER4PP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4PP) + .value("PMXVI8GER4SPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4SPP) + .value("PMXVI8GER4W", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4W) + .value("PMXVI8GER4WPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4WPP) + .value("PMXVI8GER4WSPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4WSPP) + .value("POPCNTB", LIEF::assembly::powerpc::OPCODE::POPCNTB) + .value("POPCNTB8", LIEF::assembly::powerpc::OPCODE::POPCNTB8) + .value("POPCNTD", LIEF::assembly::powerpc::OPCODE::POPCNTD) + .value("POPCNTW", LIEF::assembly::powerpc::OPCODE::POPCNTW) + .value("PPC32GOT", LIEF::assembly::powerpc::OPCODE::PPC32GOT) + .value("PPC32PICGOT", LIEF::assembly::powerpc::OPCODE::PPC32PICGOT); + opcodes.value("PREPARE_PROBED_ALLOCA_32", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_32) + .value("PREPARE_PROBED_ALLOCA_64", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_64) + .value("PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32) + .value("PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64) + .value("PROBED_ALLOCA_32", LIEF::assembly::powerpc::OPCODE::PROBED_ALLOCA_32) + .value("PROBED_ALLOCA_64", LIEF::assembly::powerpc::OPCODE::PROBED_ALLOCA_64) + .value("PROBED_STACKALLOC_32", LIEF::assembly::powerpc::OPCODE::PROBED_STACKALLOC_32) + .value("PROBED_STACKALLOC_64", LIEF::assembly::powerpc::OPCODE::PROBED_STACKALLOC_64) + .value("PSTB", LIEF::assembly::powerpc::OPCODE::PSTB) + .value("PSTB8", LIEF::assembly::powerpc::OPCODE::PSTB8) + .value("PSTB8nopc", LIEF::assembly::powerpc::OPCODE::PSTB8nopc) + .value("PSTB8onlypc", LIEF::assembly::powerpc::OPCODE::PSTB8onlypc) + .value("PSTB8pc", LIEF::assembly::powerpc::OPCODE::PSTB8pc) + .value("PSTBnopc", LIEF::assembly::powerpc::OPCODE::PSTBnopc) + .value("PSTBonlypc", LIEF::assembly::powerpc::OPCODE::PSTBonlypc) + .value("PSTBpc", LIEF::assembly::powerpc::OPCODE::PSTBpc) + .value("PSTD", LIEF::assembly::powerpc::OPCODE::PSTD) + .value("PSTDnopc", LIEF::assembly::powerpc::OPCODE::PSTDnopc) + .value("PSTDonlypc", LIEF::assembly::powerpc::OPCODE::PSTDonlypc) + .value("PSTDpc", LIEF::assembly::powerpc::OPCODE::PSTDpc) + .value("PSTFD", LIEF::assembly::powerpc::OPCODE::PSTFD) + .value("PSTFDnopc", LIEF::assembly::powerpc::OPCODE::PSTFDnopc) + .value("PSTFDonlypc", LIEF::assembly::powerpc::OPCODE::PSTFDonlypc) + .value("PSTFDpc", LIEF::assembly::powerpc::OPCODE::PSTFDpc) + .value("PSTFS", LIEF::assembly::powerpc::OPCODE::PSTFS) + .value("PSTFSnopc", LIEF::assembly::powerpc::OPCODE::PSTFSnopc) + .value("PSTFSonlypc", LIEF::assembly::powerpc::OPCODE::PSTFSonlypc) + .value("PSTFSpc", LIEF::assembly::powerpc::OPCODE::PSTFSpc) + .value("PSTH", LIEF::assembly::powerpc::OPCODE::PSTH) + .value("PSTH8", LIEF::assembly::powerpc::OPCODE::PSTH8) + .value("PSTH8nopc", LIEF::assembly::powerpc::OPCODE::PSTH8nopc) + .value("PSTH8onlypc", LIEF::assembly::powerpc::OPCODE::PSTH8onlypc) + .value("PSTH8pc", LIEF::assembly::powerpc::OPCODE::PSTH8pc) + .value("PSTHnopc", LIEF::assembly::powerpc::OPCODE::PSTHnopc) + .value("PSTHonlypc", LIEF::assembly::powerpc::OPCODE::PSTHonlypc) + .value("PSTHpc", LIEF::assembly::powerpc::OPCODE::PSTHpc) + .value("PSTW", LIEF::assembly::powerpc::OPCODE::PSTW) + .value("PSTW8", LIEF::assembly::powerpc::OPCODE::PSTW8) + .value("PSTW8nopc", LIEF::assembly::powerpc::OPCODE::PSTW8nopc) + .value("PSTW8onlypc", LIEF::assembly::powerpc::OPCODE::PSTW8onlypc) + .value("PSTW8pc", LIEF::assembly::powerpc::OPCODE::PSTW8pc) + .value("PSTWnopc", LIEF::assembly::powerpc::OPCODE::PSTWnopc) + .value("PSTWonlypc", LIEF::assembly::powerpc::OPCODE::PSTWonlypc) + .value("PSTWpc", LIEF::assembly::powerpc::OPCODE::PSTWpc) + .value("PSTXSD", LIEF::assembly::powerpc::OPCODE::PSTXSD) + .value("PSTXSDnopc", LIEF::assembly::powerpc::OPCODE::PSTXSDnopc) + .value("PSTXSDonlypc", LIEF::assembly::powerpc::OPCODE::PSTXSDonlypc) + .value("PSTXSDpc", LIEF::assembly::powerpc::OPCODE::PSTXSDpc) + .value("PSTXSSP", LIEF::assembly::powerpc::OPCODE::PSTXSSP) + .value("PSTXSSPnopc", LIEF::assembly::powerpc::OPCODE::PSTXSSPnopc) + .value("PSTXSSPonlypc", LIEF::assembly::powerpc::OPCODE::PSTXSSPonlypc) + .value("PSTXSSPpc", LIEF::assembly::powerpc::OPCODE::PSTXSSPpc) + .value("PSTXV", LIEF::assembly::powerpc::OPCODE::PSTXV) + .value("PSTXVP", LIEF::assembly::powerpc::OPCODE::PSTXVP) + .value("PSTXVPnopc", LIEF::assembly::powerpc::OPCODE::PSTXVPnopc) + .value("PSTXVPonlypc", LIEF::assembly::powerpc::OPCODE::PSTXVPonlypc) + .value("PSTXVPpc", LIEF::assembly::powerpc::OPCODE::PSTXVPpc) + .value("PSTXVnopc", LIEF::assembly::powerpc::OPCODE::PSTXVnopc) + .value("PSTXVonlypc", LIEF::assembly::powerpc::OPCODE::PSTXVonlypc) + .value("PSTXVpc", LIEF::assembly::powerpc::OPCODE::PSTXVpc) + .value("PTESYNCIO", LIEF::assembly::powerpc::OPCODE::PTESYNCIO) + .value("PseudoEIEIO", LIEF::assembly::powerpc::OPCODE::PseudoEIEIO) + .value("RESTORE_ACC", LIEF::assembly::powerpc::OPCODE::RESTORE_ACC) + .value("RESTORE_CR", LIEF::assembly::powerpc::OPCODE::RESTORE_CR) + .value("RESTORE_CRBIT", LIEF::assembly::powerpc::OPCODE::RESTORE_CRBIT) + .value("RESTORE_DMR", LIEF::assembly::powerpc::OPCODE::RESTORE_DMR) + .value("RESTORE_DMRP", LIEF::assembly::powerpc::OPCODE::RESTORE_DMRP) + .value("RESTORE_QUADWORD", LIEF::assembly::powerpc::OPCODE::RESTORE_QUADWORD) + .value("RESTORE_UACC", LIEF::assembly::powerpc::OPCODE::RESTORE_UACC) + .value("RESTORE_WACC", LIEF::assembly::powerpc::OPCODE::RESTORE_WACC) + .value("RFCI", LIEF::assembly::powerpc::OPCODE::RFCI) + .value("RFDI", LIEF::assembly::powerpc::OPCODE::RFDI) + .value("RFEBB", LIEF::assembly::powerpc::OPCODE::RFEBB) + .value("RFI", LIEF::assembly::powerpc::OPCODE::RFI) + .value("RFID", LIEF::assembly::powerpc::OPCODE::RFID) + .value("RFMCI", LIEF::assembly::powerpc::OPCODE::RFMCI) + .value("RLDCL", LIEF::assembly::powerpc::OPCODE::RLDCL) + .value("RLDCL_rec", LIEF::assembly::powerpc::OPCODE::RLDCL_rec) + .value("RLDCR", LIEF::assembly::powerpc::OPCODE::RLDCR) + .value("RLDCR_rec", LIEF::assembly::powerpc::OPCODE::RLDCR_rec) + .value("RLDIC", LIEF::assembly::powerpc::OPCODE::RLDIC) + .value("RLDICL", LIEF::assembly::powerpc::OPCODE::RLDICL) + .value("RLDICL_32", LIEF::assembly::powerpc::OPCODE::RLDICL_32) + .value("RLDICL_32_64", LIEF::assembly::powerpc::OPCODE::RLDICL_32_64) + .value("RLDICL_32_rec", LIEF::assembly::powerpc::OPCODE::RLDICL_32_rec) + .value("RLDICL_rec", LIEF::assembly::powerpc::OPCODE::RLDICL_rec) + .value("RLDICR", LIEF::assembly::powerpc::OPCODE::RLDICR) + .value("RLDICR_32", LIEF::assembly::powerpc::OPCODE::RLDICR_32) + .value("RLDICR_rec", LIEF::assembly::powerpc::OPCODE::RLDICR_rec) + .value("RLDIC_rec", LIEF::assembly::powerpc::OPCODE::RLDIC_rec) + .value("RLDIMI", LIEF::assembly::powerpc::OPCODE::RLDIMI) + .value("RLDIMI_rec", LIEF::assembly::powerpc::OPCODE::RLDIMI_rec) + .value("RLWIMI", LIEF::assembly::powerpc::OPCODE::RLWIMI) + .value("RLWIMI8", LIEF::assembly::powerpc::OPCODE::RLWIMI8) + .value("RLWIMI8_rec", LIEF::assembly::powerpc::OPCODE::RLWIMI8_rec) + .value("RLWIMI_rec", LIEF::assembly::powerpc::OPCODE::RLWIMI_rec) + .value("RLWINM", LIEF::assembly::powerpc::OPCODE::RLWINM) + .value("RLWINM8", LIEF::assembly::powerpc::OPCODE::RLWINM8) + .value("RLWINM8_rec", LIEF::assembly::powerpc::OPCODE::RLWINM8_rec) + .value("RLWINM_rec", LIEF::assembly::powerpc::OPCODE::RLWINM_rec) + .value("RLWNM", LIEF::assembly::powerpc::OPCODE::RLWNM) + .value("RLWNM8", LIEF::assembly::powerpc::OPCODE::RLWNM8) + .value("RLWNM8_rec", LIEF::assembly::powerpc::OPCODE::RLWNM8_rec) + .value("RLWNM_rec", LIEF::assembly::powerpc::OPCODE::RLWNM_rec) + .value("ReadTB", LIEF::assembly::powerpc::OPCODE::ReadTB) + .value("SC", LIEF::assembly::powerpc::OPCODE::SC) + .value("SCV", LIEF::assembly::powerpc::OPCODE::SCV) + .value("SELECT_CC_F16", LIEF::assembly::powerpc::OPCODE::SELECT_CC_F16) + .value("SELECT_CC_F4", LIEF::assembly::powerpc::OPCODE::SELECT_CC_F4) + .value("SELECT_CC_F8", LIEF::assembly::powerpc::OPCODE::SELECT_CC_F8) + .value("SELECT_CC_I4", LIEF::assembly::powerpc::OPCODE::SELECT_CC_I4) + .value("SELECT_CC_I8", LIEF::assembly::powerpc::OPCODE::SELECT_CC_I8) + .value("SELECT_CC_SPE", LIEF::assembly::powerpc::OPCODE::SELECT_CC_SPE) + .value("SELECT_CC_SPE4", LIEF::assembly::powerpc::OPCODE::SELECT_CC_SPE4) + .value("SELECT_CC_VRRC", LIEF::assembly::powerpc::OPCODE::SELECT_CC_VRRC) + .value("SELECT_CC_VSFRC", LIEF::assembly::powerpc::OPCODE::SELECT_CC_VSFRC) + .value("SELECT_CC_VSRC", LIEF::assembly::powerpc::OPCODE::SELECT_CC_VSRC) + .value("SELECT_CC_VSSRC", LIEF::assembly::powerpc::OPCODE::SELECT_CC_VSSRC) + .value("SELECT_F16", LIEF::assembly::powerpc::OPCODE::SELECT_F16) + .value("SELECT_F4", LIEF::assembly::powerpc::OPCODE::SELECT_F4) + .value("SELECT_F8", LIEF::assembly::powerpc::OPCODE::SELECT_F8) + .value("SELECT_I4", LIEF::assembly::powerpc::OPCODE::SELECT_I4) + .value("SELECT_I8", LIEF::assembly::powerpc::OPCODE::SELECT_I8) + .value("SELECT_SPE", LIEF::assembly::powerpc::OPCODE::SELECT_SPE) + .value("SELECT_SPE4", LIEF::assembly::powerpc::OPCODE::SELECT_SPE4) + .value("SELECT_VRRC", LIEF::assembly::powerpc::OPCODE::SELECT_VRRC) + .value("SELECT_VSFRC", LIEF::assembly::powerpc::OPCODE::SELECT_VSFRC) + .value("SELECT_VSRC", LIEF::assembly::powerpc::OPCODE::SELECT_VSRC) + .value("SELECT_VSSRC", LIEF::assembly::powerpc::OPCODE::SELECT_VSSRC) + .value("SETB", LIEF::assembly::powerpc::OPCODE::SETB) + .value("SETB8", LIEF::assembly::powerpc::OPCODE::SETB8) + .value("SETBC", LIEF::assembly::powerpc::OPCODE::SETBC) + .value("SETBC8", LIEF::assembly::powerpc::OPCODE::SETBC8) + .value("SETBCR", LIEF::assembly::powerpc::OPCODE::SETBCR) + .value("SETBCR8", LIEF::assembly::powerpc::OPCODE::SETBCR8) + .value("SETFLM", LIEF::assembly::powerpc::OPCODE::SETFLM) + .value("SETNBC", LIEF::assembly::powerpc::OPCODE::SETNBC) + .value("SETNBC8", LIEF::assembly::powerpc::OPCODE::SETNBC8) + .value("SETNBCR", LIEF::assembly::powerpc::OPCODE::SETNBCR) + .value("SETNBCR8", LIEF::assembly::powerpc::OPCODE::SETNBCR8) + .value("SETRND", LIEF::assembly::powerpc::OPCODE::SETRND) + .value("SETRNDi", LIEF::assembly::powerpc::OPCODE::SETRNDi) + .value("SLBFEE_rec", LIEF::assembly::powerpc::OPCODE::SLBFEE_rec) + .value("SLBIA", LIEF::assembly::powerpc::OPCODE::SLBIA) + .value("SLBIE", LIEF::assembly::powerpc::OPCODE::SLBIE) + .value("SLBIEG", LIEF::assembly::powerpc::OPCODE::SLBIEG) + .value("SLBMFEE", LIEF::assembly::powerpc::OPCODE::SLBMFEE) + .value("SLBMFEV", LIEF::assembly::powerpc::OPCODE::SLBMFEV) + .value("SLBMTE", LIEF::assembly::powerpc::OPCODE::SLBMTE) + .value("SLBSYNC", LIEF::assembly::powerpc::OPCODE::SLBSYNC) + .value("SLD", LIEF::assembly::powerpc::OPCODE::SLD) + .value("SLD_rec", LIEF::assembly::powerpc::OPCODE::SLD_rec) + .value("SLW", LIEF::assembly::powerpc::OPCODE::SLW) + .value("SLW8", LIEF::assembly::powerpc::OPCODE::SLW8) + .value("SLW8_rec", LIEF::assembly::powerpc::OPCODE::SLW8_rec) + .value("SLW_rec", LIEF::assembly::powerpc::OPCODE::SLW_rec) + .value("SPELWZ", LIEF::assembly::powerpc::OPCODE::SPELWZ) + .value("SPELWZX", LIEF::assembly::powerpc::OPCODE::SPELWZX) + .value("SPESTW", LIEF::assembly::powerpc::OPCODE::SPESTW) + .value("SPESTWX", LIEF::assembly::powerpc::OPCODE::SPESTWX) + .value("SPILL_ACC", LIEF::assembly::powerpc::OPCODE::SPILL_ACC) + .value("SPILL_CR", LIEF::assembly::powerpc::OPCODE::SPILL_CR) + .value("SPILL_CRBIT", LIEF::assembly::powerpc::OPCODE::SPILL_CRBIT) + .value("SPILL_DMR", LIEF::assembly::powerpc::OPCODE::SPILL_DMR) + .value("SPILL_DMRP", LIEF::assembly::powerpc::OPCODE::SPILL_DMRP) + .value("SPILL_QUADWORD", LIEF::assembly::powerpc::OPCODE::SPILL_QUADWORD) + .value("SPILL_UACC", LIEF::assembly::powerpc::OPCODE::SPILL_UACC) + .value("SPILL_WACC", LIEF::assembly::powerpc::OPCODE::SPILL_WACC) + .value("SPLIT_QUADWORD", LIEF::assembly::powerpc::OPCODE::SPLIT_QUADWORD) + .value("SRAD", LIEF::assembly::powerpc::OPCODE::SRAD) + .value("SRADI", LIEF::assembly::powerpc::OPCODE::SRADI) + .value("SRADI_32", LIEF::assembly::powerpc::OPCODE::SRADI_32) + .value("SRADI_rec", LIEF::assembly::powerpc::OPCODE::SRADI_rec) + .value("SRAD_rec", LIEF::assembly::powerpc::OPCODE::SRAD_rec) + .value("SRAW", LIEF::assembly::powerpc::OPCODE::SRAW) + .value("SRAW8", LIEF::assembly::powerpc::OPCODE::SRAW8) + .value("SRAW8_rec", LIEF::assembly::powerpc::OPCODE::SRAW8_rec) + .value("SRAWI", LIEF::assembly::powerpc::OPCODE::SRAWI) + .value("SRAWI8", LIEF::assembly::powerpc::OPCODE::SRAWI8) + .value("SRAWI8_rec", LIEF::assembly::powerpc::OPCODE::SRAWI8_rec) + .value("SRAWI_rec", LIEF::assembly::powerpc::OPCODE::SRAWI_rec) + .value("SRAW_rec", LIEF::assembly::powerpc::OPCODE::SRAW_rec) + .value("SRD", LIEF::assembly::powerpc::OPCODE::SRD) + .value("SRD_rec", LIEF::assembly::powerpc::OPCODE::SRD_rec) + .value("SRW", LIEF::assembly::powerpc::OPCODE::SRW) + .value("SRW8", LIEF::assembly::powerpc::OPCODE::SRW8) + .value("SRW8_rec", LIEF::assembly::powerpc::OPCODE::SRW8_rec) + .value("SRW_rec", LIEF::assembly::powerpc::OPCODE::SRW_rec) + .value("STB", LIEF::assembly::powerpc::OPCODE::STB) + .value("STB8", LIEF::assembly::powerpc::OPCODE::STB8) + .value("STBCIX", LIEF::assembly::powerpc::OPCODE::STBCIX) + .value("STBCX", LIEF::assembly::powerpc::OPCODE::STBCX) + .value("STBEPX", LIEF::assembly::powerpc::OPCODE::STBEPX) + .value("STBU", LIEF::assembly::powerpc::OPCODE::STBU) + .value("STBU8", LIEF::assembly::powerpc::OPCODE::STBU8) + .value("STBUX", LIEF::assembly::powerpc::OPCODE::STBUX) + .value("STBUX8", LIEF::assembly::powerpc::OPCODE::STBUX8) + .value("STBX", LIEF::assembly::powerpc::OPCODE::STBX) + .value("STBX8", LIEF::assembly::powerpc::OPCODE::STBX8) + .value("STBXTLS", LIEF::assembly::powerpc::OPCODE::STBXTLS) + .value("STBXTLS_", LIEF::assembly::powerpc::OPCODE::STBXTLS_) + .value("STBXTLS_32", LIEF::assembly::powerpc::OPCODE::STBXTLS_32) + .value("STD", LIEF::assembly::powerpc::OPCODE::STD) + .value("STDAT", LIEF::assembly::powerpc::OPCODE::STDAT) + .value("STDBRX", LIEF::assembly::powerpc::OPCODE::STDBRX) + .value("STDCIX", LIEF::assembly::powerpc::OPCODE::STDCIX) + .value("STDCX", LIEF::assembly::powerpc::OPCODE::STDCX) + .value("STDU", LIEF::assembly::powerpc::OPCODE::STDU) + .value("STDUX", LIEF::assembly::powerpc::OPCODE::STDUX) + .value("STDX", LIEF::assembly::powerpc::OPCODE::STDX) + .value("STDXTLS", LIEF::assembly::powerpc::OPCODE::STDXTLS) + .value("STDXTLS_", LIEF::assembly::powerpc::OPCODE::STDXTLS_) + .value("STFD", LIEF::assembly::powerpc::OPCODE::STFD) + .value("STFDEPX", LIEF::assembly::powerpc::OPCODE::STFDEPX) + .value("STFDU", LIEF::assembly::powerpc::OPCODE::STFDU) + .value("STFDUX", LIEF::assembly::powerpc::OPCODE::STFDUX) + .value("STFDX", LIEF::assembly::powerpc::OPCODE::STFDX) + .value("STFDXTLS", LIEF::assembly::powerpc::OPCODE::STFDXTLS) + .value("STFDXTLS_", LIEF::assembly::powerpc::OPCODE::STFDXTLS_) + .value("STFIWX", LIEF::assembly::powerpc::OPCODE::STFIWX) + .value("STFS", LIEF::assembly::powerpc::OPCODE::STFS) + .value("STFSU", LIEF::assembly::powerpc::OPCODE::STFSU) + .value("STFSUX", LIEF::assembly::powerpc::OPCODE::STFSUX) + .value("STFSX", LIEF::assembly::powerpc::OPCODE::STFSX) + .value("STFSXTLS", LIEF::assembly::powerpc::OPCODE::STFSXTLS) + .value("STFSXTLS_", LIEF::assembly::powerpc::OPCODE::STFSXTLS_) + .value("STH", LIEF::assembly::powerpc::OPCODE::STH) + .value("STH8", LIEF::assembly::powerpc::OPCODE::STH8) + .value("STHBRX", LIEF::assembly::powerpc::OPCODE::STHBRX) + .value("STHCIX", LIEF::assembly::powerpc::OPCODE::STHCIX) + .value("STHCX", LIEF::assembly::powerpc::OPCODE::STHCX) + .value("STHEPX", LIEF::assembly::powerpc::OPCODE::STHEPX) + .value("STHU", LIEF::assembly::powerpc::OPCODE::STHU) + .value("STHU8", LIEF::assembly::powerpc::OPCODE::STHU8) + .value("STHUX", LIEF::assembly::powerpc::OPCODE::STHUX) + .value("STHUX8", LIEF::assembly::powerpc::OPCODE::STHUX8) + .value("STHX", LIEF::assembly::powerpc::OPCODE::STHX) + .value("STHX8", LIEF::assembly::powerpc::OPCODE::STHX8) + .value("STHXTLS", LIEF::assembly::powerpc::OPCODE::STHXTLS) + .value("STHXTLS_", LIEF::assembly::powerpc::OPCODE::STHXTLS_) + .value("STHXTLS_32", LIEF::assembly::powerpc::OPCODE::STHXTLS_32) + .value("STMW", LIEF::assembly::powerpc::OPCODE::STMW) + .value("STOP", LIEF::assembly::powerpc::OPCODE::STOP) + .value("STQ", LIEF::assembly::powerpc::OPCODE::STQ) + .value("STQCX", LIEF::assembly::powerpc::OPCODE::STQCX) + .value("STQX_PSEUDO", LIEF::assembly::powerpc::OPCODE::STQX_PSEUDO) + .value("STSWI", LIEF::assembly::powerpc::OPCODE::STSWI) + .value("STVEBX", LIEF::assembly::powerpc::OPCODE::STVEBX) + .value("STVEHX", LIEF::assembly::powerpc::OPCODE::STVEHX) + .value("STVEWX", LIEF::assembly::powerpc::OPCODE::STVEWX) + .value("STVX", LIEF::assembly::powerpc::OPCODE::STVX) + .value("STVXL", LIEF::assembly::powerpc::OPCODE::STVXL) + .value("STW", LIEF::assembly::powerpc::OPCODE::STW) + .value("STW8", LIEF::assembly::powerpc::OPCODE::STW8) + .value("STWAT", LIEF::assembly::powerpc::OPCODE::STWAT) + .value("STWBRX", LIEF::assembly::powerpc::OPCODE::STWBRX) + .value("STWCIX", LIEF::assembly::powerpc::OPCODE::STWCIX) + .value("STWCX", LIEF::assembly::powerpc::OPCODE::STWCX) + .value("STWEPX", LIEF::assembly::powerpc::OPCODE::STWEPX) + .value("STWU", LIEF::assembly::powerpc::OPCODE::STWU) + .value("STWU8", LIEF::assembly::powerpc::OPCODE::STWU8) + .value("STWUX", LIEF::assembly::powerpc::OPCODE::STWUX) + .value("STWUX8", LIEF::assembly::powerpc::OPCODE::STWUX8) + .value("STWX", LIEF::assembly::powerpc::OPCODE::STWX) + .value("STWX8", LIEF::assembly::powerpc::OPCODE::STWX8) + .value("STWXTLS", LIEF::assembly::powerpc::OPCODE::STWXTLS) + .value("STWXTLS_", LIEF::assembly::powerpc::OPCODE::STWXTLS_) + .value("STWXTLS_32", LIEF::assembly::powerpc::OPCODE::STWXTLS_32) + .value("STXSD", LIEF::assembly::powerpc::OPCODE::STXSD) + .value("STXSDX", LIEF::assembly::powerpc::OPCODE::STXSDX) + .value("STXSIBX", LIEF::assembly::powerpc::OPCODE::STXSIBX) + .value("STXSIBXv", LIEF::assembly::powerpc::OPCODE::STXSIBXv) + .value("STXSIHX", LIEF::assembly::powerpc::OPCODE::STXSIHX) + .value("STXSIHXv", LIEF::assembly::powerpc::OPCODE::STXSIHXv) + .value("STXSIWX", LIEF::assembly::powerpc::OPCODE::STXSIWX) + .value("STXSSP", LIEF::assembly::powerpc::OPCODE::STXSSP) + .value("STXSSPX", LIEF::assembly::powerpc::OPCODE::STXSSPX) + .value("STXV", LIEF::assembly::powerpc::OPCODE::STXV) + .value("STXVB16X", LIEF::assembly::powerpc::OPCODE::STXVB16X) + .value("STXVD2X", LIEF::assembly::powerpc::OPCODE::STXVD2X) + .value("STXVH8X", LIEF::assembly::powerpc::OPCODE::STXVH8X) + .value("STXVL", LIEF::assembly::powerpc::OPCODE::STXVL) + .value("STXVLL", LIEF::assembly::powerpc::OPCODE::STXVLL) + .value("STXVP", LIEF::assembly::powerpc::OPCODE::STXVP) + .value("STXVPB32X", LIEF::assembly::powerpc::OPCODE::STXVPB32X) + .value("STXVPRL", LIEF::assembly::powerpc::OPCODE::STXVPRL) + .value("STXVPRLL", LIEF::assembly::powerpc::OPCODE::STXVPRLL) + .value("STXVPX", LIEF::assembly::powerpc::OPCODE::STXVPX) + .value("STXVRBX", LIEF::assembly::powerpc::OPCODE::STXVRBX) + .value("STXVRDX", LIEF::assembly::powerpc::OPCODE::STXVRDX) + .value("STXVRHX", LIEF::assembly::powerpc::OPCODE::STXVRHX) + .value("STXVRL", LIEF::assembly::powerpc::OPCODE::STXVRL) + .value("STXVRLL", LIEF::assembly::powerpc::OPCODE::STXVRLL) + .value("STXVRWX", LIEF::assembly::powerpc::OPCODE::STXVRWX) + .value("STXVW4X", LIEF::assembly::powerpc::OPCODE::STXVW4X) + .value("STXVX", LIEF::assembly::powerpc::OPCODE::STXVX) + .value("SUBF", LIEF::assembly::powerpc::OPCODE::SUBF) + .value("SUBF8", LIEF::assembly::powerpc::OPCODE::SUBF8) + .value("SUBF8O", LIEF::assembly::powerpc::OPCODE::SUBF8O) + .value("SUBF8O_rec", LIEF::assembly::powerpc::OPCODE::SUBF8O_rec); + opcodes.value("SUBF8_rec", LIEF::assembly::powerpc::OPCODE::SUBF8_rec) + .value("SUBFC", LIEF::assembly::powerpc::OPCODE::SUBFC) + .value("SUBFC8", LIEF::assembly::powerpc::OPCODE::SUBFC8) + .value("SUBFC8O", LIEF::assembly::powerpc::OPCODE::SUBFC8O) + .value("SUBFC8O_rec", LIEF::assembly::powerpc::OPCODE::SUBFC8O_rec) + .value("SUBFC8_rec", LIEF::assembly::powerpc::OPCODE::SUBFC8_rec) + .value("SUBFCO", LIEF::assembly::powerpc::OPCODE::SUBFCO) + .value("SUBFCO_rec", LIEF::assembly::powerpc::OPCODE::SUBFCO_rec) + .value("SUBFC_rec", LIEF::assembly::powerpc::OPCODE::SUBFC_rec) + .value("SUBFE", LIEF::assembly::powerpc::OPCODE::SUBFE) + .value("SUBFE8", LIEF::assembly::powerpc::OPCODE::SUBFE8) + .value("SUBFE8O", LIEF::assembly::powerpc::OPCODE::SUBFE8O) + .value("SUBFE8O_rec", LIEF::assembly::powerpc::OPCODE::SUBFE8O_rec) + .value("SUBFE8_rec", LIEF::assembly::powerpc::OPCODE::SUBFE8_rec) + .value("SUBFEO", LIEF::assembly::powerpc::OPCODE::SUBFEO) + .value("SUBFEO_rec", LIEF::assembly::powerpc::OPCODE::SUBFEO_rec) + .value("SUBFE_rec", LIEF::assembly::powerpc::OPCODE::SUBFE_rec) + .value("SUBFIC", LIEF::assembly::powerpc::OPCODE::SUBFIC) + .value("SUBFIC8", LIEF::assembly::powerpc::OPCODE::SUBFIC8) + .value("SUBFME", LIEF::assembly::powerpc::OPCODE::SUBFME) + .value("SUBFME8", LIEF::assembly::powerpc::OPCODE::SUBFME8) + .value("SUBFME8O", LIEF::assembly::powerpc::OPCODE::SUBFME8O) + .value("SUBFME8O_rec", LIEF::assembly::powerpc::OPCODE::SUBFME8O_rec) + .value("SUBFME8_rec", LIEF::assembly::powerpc::OPCODE::SUBFME8_rec) + .value("SUBFMEO", LIEF::assembly::powerpc::OPCODE::SUBFMEO) + .value("SUBFMEO_rec", LIEF::assembly::powerpc::OPCODE::SUBFMEO_rec) + .value("SUBFME_rec", LIEF::assembly::powerpc::OPCODE::SUBFME_rec) + .value("SUBFO", LIEF::assembly::powerpc::OPCODE::SUBFO) + .value("SUBFO_rec", LIEF::assembly::powerpc::OPCODE::SUBFO_rec) + .value("SUBFUS", LIEF::assembly::powerpc::OPCODE::SUBFUS) + .value("SUBFUS_rec", LIEF::assembly::powerpc::OPCODE::SUBFUS_rec) + .value("SUBFZE", LIEF::assembly::powerpc::OPCODE::SUBFZE) + .value("SUBFZE8", LIEF::assembly::powerpc::OPCODE::SUBFZE8) + .value("SUBFZE8O", LIEF::assembly::powerpc::OPCODE::SUBFZE8O) + .value("SUBFZE8O_rec", LIEF::assembly::powerpc::OPCODE::SUBFZE8O_rec) + .value("SUBFZE8_rec", LIEF::assembly::powerpc::OPCODE::SUBFZE8_rec) + .value("SUBFZEO", LIEF::assembly::powerpc::OPCODE::SUBFZEO) + .value("SUBFZEO_rec", LIEF::assembly::powerpc::OPCODE::SUBFZEO_rec) + .value("SUBFZE_rec", LIEF::assembly::powerpc::OPCODE::SUBFZE_rec) + .value("SUBF_rec", LIEF::assembly::powerpc::OPCODE::SUBF_rec) + .value("SYNC", LIEF::assembly::powerpc::OPCODE::SYNC) + .value("SYNCP10", LIEF::assembly::powerpc::OPCODE::SYNCP10) + .value("TABORT", LIEF::assembly::powerpc::OPCODE::TABORT) + .value("TABORTDC", LIEF::assembly::powerpc::OPCODE::TABORTDC) + .value("TABORTDCI", LIEF::assembly::powerpc::OPCODE::TABORTDCI) + .value("TABORTWC", LIEF::assembly::powerpc::OPCODE::TABORTWC) + .value("TABORTWCI", LIEF::assembly::powerpc::OPCODE::TABORTWCI) + .value("TAILB", LIEF::assembly::powerpc::OPCODE::TAILB) + .value("TAILB8", LIEF::assembly::powerpc::OPCODE::TAILB8) + .value("TAILBA", LIEF::assembly::powerpc::OPCODE::TAILBA) + .value("TAILBA8", LIEF::assembly::powerpc::OPCODE::TAILBA8) + .value("TAILBCTR", LIEF::assembly::powerpc::OPCODE::TAILBCTR) + .value("TAILBCTR8", LIEF::assembly::powerpc::OPCODE::TAILBCTR8) + .value("TBEGIN", LIEF::assembly::powerpc::OPCODE::TBEGIN) + .value("TBEGIN_RET", LIEF::assembly::powerpc::OPCODE::TBEGIN_RET) + .value("TCHECK", LIEF::assembly::powerpc::OPCODE::TCHECK) + .value("TCHECK_RET", LIEF::assembly::powerpc::OPCODE::TCHECK_RET) + .value("TCRETURNai", LIEF::assembly::powerpc::OPCODE::TCRETURNai) + .value("TCRETURNai8", LIEF::assembly::powerpc::OPCODE::TCRETURNai8) + .value("TCRETURNdi", LIEF::assembly::powerpc::OPCODE::TCRETURNdi) + .value("TCRETURNdi8", LIEF::assembly::powerpc::OPCODE::TCRETURNdi8) + .value("TCRETURNri", LIEF::assembly::powerpc::OPCODE::TCRETURNri) + .value("TCRETURNri8", LIEF::assembly::powerpc::OPCODE::TCRETURNri8) + .value("TD", LIEF::assembly::powerpc::OPCODE::TD) + .value("TDI", LIEF::assembly::powerpc::OPCODE::TDI) + .value("TEND", LIEF::assembly::powerpc::OPCODE::TEND) + .value("TLBIA", LIEF::assembly::powerpc::OPCODE::TLBIA) + .value("TLBIE", LIEF::assembly::powerpc::OPCODE::TLBIE) + .value("TLBIE8P9", LIEF::assembly::powerpc::OPCODE::TLBIE8P9) + .value("TLBIEIO", LIEF::assembly::powerpc::OPCODE::TLBIEIO) + .value("TLBIEL", LIEF::assembly::powerpc::OPCODE::TLBIEL) + .value("TLBIEP", LIEF::assembly::powerpc::OPCODE::TLBIEP) + .value("TLBIEP8", LIEF::assembly::powerpc::OPCODE::TLBIEP8) + .value("TLBIEP9", LIEF::assembly::powerpc::OPCODE::TLBIEP9) + .value("TLBILX", LIEF::assembly::powerpc::OPCODE::TLBILX) + .value("TLBIVAX", LIEF::assembly::powerpc::OPCODE::TLBIVAX) + .value("TLBLD", LIEF::assembly::powerpc::OPCODE::TLBLD) + .value("TLBLI", LIEF::assembly::powerpc::OPCODE::TLBLI) + .value("TLBRE", LIEF::assembly::powerpc::OPCODE::TLBRE) + .value("TLBRE2", LIEF::assembly::powerpc::OPCODE::TLBRE2) + .value("TLBSX", LIEF::assembly::powerpc::OPCODE::TLBSX) + .value("TLBSX2", LIEF::assembly::powerpc::OPCODE::TLBSX2) + .value("TLBSX2D", LIEF::assembly::powerpc::OPCODE::TLBSX2D) + .value("TLBSYNC", LIEF::assembly::powerpc::OPCODE::TLBSYNC) + .value("TLBSYNCIO", LIEF::assembly::powerpc::OPCODE::TLBSYNCIO) + .value("TLBWE", LIEF::assembly::powerpc::OPCODE::TLBWE) + .value("TLBWE2", LIEF::assembly::powerpc::OPCODE::TLBWE2) + .value("TLSGDAIX", LIEF::assembly::powerpc::OPCODE::TLSGDAIX) + .value("TLSGDAIX8", LIEF::assembly::powerpc::OPCODE::TLSGDAIX8) + .value("TLSLDAIX", LIEF::assembly::powerpc::OPCODE::TLSLDAIX) + .value("TLSLDAIX8", LIEF::assembly::powerpc::OPCODE::TLSLDAIX8) + .value("TRAP", LIEF::assembly::powerpc::OPCODE::TRAP) + .value("TRECHKPT", LIEF::assembly::powerpc::OPCODE::TRECHKPT) + .value("TRECLAIM", LIEF::assembly::powerpc::OPCODE::TRECLAIM) + .value("TSR", LIEF::assembly::powerpc::OPCODE::TSR) + .value("TW", LIEF::assembly::powerpc::OPCODE::TW) + .value("TWI", LIEF::assembly::powerpc::OPCODE::TWI) + .value("UNENCODED_NOP", LIEF::assembly::powerpc::OPCODE::UNENCODED_NOP) + .value("UpdateGBR", LIEF::assembly::powerpc::OPCODE::UpdateGBR) + .value("VABSDUB", LIEF::assembly::powerpc::OPCODE::VABSDUB) + .value("VABSDUH", LIEF::assembly::powerpc::OPCODE::VABSDUH) + .value("VABSDUW", LIEF::assembly::powerpc::OPCODE::VABSDUW) + .value("VADDCUQ", LIEF::assembly::powerpc::OPCODE::VADDCUQ) + .value("VADDCUW", LIEF::assembly::powerpc::OPCODE::VADDCUW) + .value("VADDECUQ", LIEF::assembly::powerpc::OPCODE::VADDECUQ) + .value("VADDEUQM", LIEF::assembly::powerpc::OPCODE::VADDEUQM) + .value("VADDFP", LIEF::assembly::powerpc::OPCODE::VADDFP) + .value("VADDSBS", LIEF::assembly::powerpc::OPCODE::VADDSBS) + .value("VADDSHS", LIEF::assembly::powerpc::OPCODE::VADDSHS) + .value("VADDSWS", LIEF::assembly::powerpc::OPCODE::VADDSWS) + .value("VADDUBM", LIEF::assembly::powerpc::OPCODE::VADDUBM) + .value("VADDUBS", LIEF::assembly::powerpc::OPCODE::VADDUBS) + .value("VADDUDM", LIEF::assembly::powerpc::OPCODE::VADDUDM) + .value("VADDUHM", LIEF::assembly::powerpc::OPCODE::VADDUHM) + .value("VADDUHS", LIEF::assembly::powerpc::OPCODE::VADDUHS) + .value("VADDUQM", LIEF::assembly::powerpc::OPCODE::VADDUQM) + .value("VADDUWM", LIEF::assembly::powerpc::OPCODE::VADDUWM) + .value("VADDUWS", LIEF::assembly::powerpc::OPCODE::VADDUWS) + .value("VAND", LIEF::assembly::powerpc::OPCODE::VAND) + .value("VANDC", LIEF::assembly::powerpc::OPCODE::VANDC) + .value("VAVGSB", LIEF::assembly::powerpc::OPCODE::VAVGSB) + .value("VAVGSH", LIEF::assembly::powerpc::OPCODE::VAVGSH) + .value("VAVGSW", LIEF::assembly::powerpc::OPCODE::VAVGSW) + .value("VAVGUB", LIEF::assembly::powerpc::OPCODE::VAVGUB) + .value("VAVGUH", LIEF::assembly::powerpc::OPCODE::VAVGUH) + .value("VAVGUW", LIEF::assembly::powerpc::OPCODE::VAVGUW) + .value("VBPERMD", LIEF::assembly::powerpc::OPCODE::VBPERMD) + .value("VBPERMQ", LIEF::assembly::powerpc::OPCODE::VBPERMQ) + .value("VCFSX", LIEF::assembly::powerpc::OPCODE::VCFSX) + .value("VCFSX_0", LIEF::assembly::powerpc::OPCODE::VCFSX_0) + .value("VCFUGED", LIEF::assembly::powerpc::OPCODE::VCFUGED) + .value("VCFUX", LIEF::assembly::powerpc::OPCODE::VCFUX) + .value("VCFUX_0", LIEF::assembly::powerpc::OPCODE::VCFUX_0) + .value("VCIPHER", LIEF::assembly::powerpc::OPCODE::VCIPHER) + .value("VCIPHERLAST", LIEF::assembly::powerpc::OPCODE::VCIPHERLAST) + .value("VCLRLB", LIEF::assembly::powerpc::OPCODE::VCLRLB) + .value("VCLRRB", LIEF::assembly::powerpc::OPCODE::VCLRRB) + .value("VCLZB", LIEF::assembly::powerpc::OPCODE::VCLZB) + .value("VCLZD", LIEF::assembly::powerpc::OPCODE::VCLZD) + .value("VCLZDM", LIEF::assembly::powerpc::OPCODE::VCLZDM) + .value("VCLZH", LIEF::assembly::powerpc::OPCODE::VCLZH) + .value("VCLZLSBB", LIEF::assembly::powerpc::OPCODE::VCLZLSBB) + .value("VCLZW", LIEF::assembly::powerpc::OPCODE::VCLZW) + .value("VCMPBFP", LIEF::assembly::powerpc::OPCODE::VCMPBFP) + .value("VCMPBFP_rec", LIEF::assembly::powerpc::OPCODE::VCMPBFP_rec) + .value("VCMPEQFP", LIEF::assembly::powerpc::OPCODE::VCMPEQFP) + .value("VCMPEQFP_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQFP_rec) + .value("VCMPEQUB", LIEF::assembly::powerpc::OPCODE::VCMPEQUB) + .value("VCMPEQUB_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQUB_rec) + .value("VCMPEQUD", LIEF::assembly::powerpc::OPCODE::VCMPEQUD) + .value("VCMPEQUD_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQUD_rec) + .value("VCMPEQUH", LIEF::assembly::powerpc::OPCODE::VCMPEQUH) + .value("VCMPEQUH_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQUH_rec) + .value("VCMPEQUQ", LIEF::assembly::powerpc::OPCODE::VCMPEQUQ) + .value("VCMPEQUQ_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQUQ_rec) + .value("VCMPEQUW", LIEF::assembly::powerpc::OPCODE::VCMPEQUW) + .value("VCMPEQUW_rec", LIEF::assembly::powerpc::OPCODE::VCMPEQUW_rec) + .value("VCMPGEFP", LIEF::assembly::powerpc::OPCODE::VCMPGEFP) + .value("VCMPGEFP_rec", LIEF::assembly::powerpc::OPCODE::VCMPGEFP_rec) + .value("VCMPGTFP", LIEF::assembly::powerpc::OPCODE::VCMPGTFP) + .value("VCMPGTFP_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTFP_rec) + .value("VCMPGTSB", LIEF::assembly::powerpc::OPCODE::VCMPGTSB) + .value("VCMPGTSB_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTSB_rec) + .value("VCMPGTSD", LIEF::assembly::powerpc::OPCODE::VCMPGTSD) + .value("VCMPGTSD_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTSD_rec) + .value("VCMPGTSH", LIEF::assembly::powerpc::OPCODE::VCMPGTSH) + .value("VCMPGTSH_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTSH_rec) + .value("VCMPGTSQ", LIEF::assembly::powerpc::OPCODE::VCMPGTSQ) + .value("VCMPGTSQ_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTSQ_rec) + .value("VCMPGTSW", LIEF::assembly::powerpc::OPCODE::VCMPGTSW) + .value("VCMPGTSW_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTSW_rec) + .value("VCMPGTUB", LIEF::assembly::powerpc::OPCODE::VCMPGTUB) + .value("VCMPGTUB_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTUB_rec) + .value("VCMPGTUD", LIEF::assembly::powerpc::OPCODE::VCMPGTUD) + .value("VCMPGTUD_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTUD_rec) + .value("VCMPGTUH", LIEF::assembly::powerpc::OPCODE::VCMPGTUH) + .value("VCMPGTUH_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTUH_rec) + .value("VCMPGTUQ", LIEF::assembly::powerpc::OPCODE::VCMPGTUQ) + .value("VCMPGTUQ_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTUQ_rec) + .value("VCMPGTUW", LIEF::assembly::powerpc::OPCODE::VCMPGTUW) + .value("VCMPGTUW_rec", LIEF::assembly::powerpc::OPCODE::VCMPGTUW_rec) + .value("VCMPNEB", LIEF::assembly::powerpc::OPCODE::VCMPNEB) + .value("VCMPNEB_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEB_rec) + .value("VCMPNEH", LIEF::assembly::powerpc::OPCODE::VCMPNEH) + .value("VCMPNEH_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEH_rec) + .value("VCMPNEW", LIEF::assembly::powerpc::OPCODE::VCMPNEW) + .value("VCMPNEW_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEW_rec) + .value("VCMPNEZB", LIEF::assembly::powerpc::OPCODE::VCMPNEZB) + .value("VCMPNEZB_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEZB_rec) + .value("VCMPNEZH", LIEF::assembly::powerpc::OPCODE::VCMPNEZH) + .value("VCMPNEZH_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEZH_rec) + .value("VCMPNEZW", LIEF::assembly::powerpc::OPCODE::VCMPNEZW) + .value("VCMPNEZW_rec", LIEF::assembly::powerpc::OPCODE::VCMPNEZW_rec) + .value("VCMPSQ", LIEF::assembly::powerpc::OPCODE::VCMPSQ) + .value("VCMPUQ", LIEF::assembly::powerpc::OPCODE::VCMPUQ) + .value("VCNTMBB", LIEF::assembly::powerpc::OPCODE::VCNTMBB) + .value("VCNTMBD", LIEF::assembly::powerpc::OPCODE::VCNTMBD) + .value("VCNTMBH", LIEF::assembly::powerpc::OPCODE::VCNTMBH) + .value("VCNTMBW", LIEF::assembly::powerpc::OPCODE::VCNTMBW) + .value("VCTSXS", LIEF::assembly::powerpc::OPCODE::VCTSXS) + .value("VCTSXS_0", LIEF::assembly::powerpc::OPCODE::VCTSXS_0) + .value("VCTUXS", LIEF::assembly::powerpc::OPCODE::VCTUXS) + .value("VCTUXS_0", LIEF::assembly::powerpc::OPCODE::VCTUXS_0) + .value("VCTZB", LIEF::assembly::powerpc::OPCODE::VCTZB) + .value("VCTZD", LIEF::assembly::powerpc::OPCODE::VCTZD) + .value("VCTZDM", LIEF::assembly::powerpc::OPCODE::VCTZDM) + .value("VCTZH", LIEF::assembly::powerpc::OPCODE::VCTZH) + .value("VCTZLSBB", LIEF::assembly::powerpc::OPCODE::VCTZLSBB) + .value("VCTZW", LIEF::assembly::powerpc::OPCODE::VCTZW) + .value("VDIVESD", LIEF::assembly::powerpc::OPCODE::VDIVESD) + .value("VDIVESQ", LIEF::assembly::powerpc::OPCODE::VDIVESQ) + .value("VDIVESW", LIEF::assembly::powerpc::OPCODE::VDIVESW) + .value("VDIVEUD", LIEF::assembly::powerpc::OPCODE::VDIVEUD) + .value("VDIVEUQ", LIEF::assembly::powerpc::OPCODE::VDIVEUQ) + .value("VDIVEUW", LIEF::assembly::powerpc::OPCODE::VDIVEUW) + .value("VDIVSD", LIEF::assembly::powerpc::OPCODE::VDIVSD) + .value("VDIVSQ", LIEF::assembly::powerpc::OPCODE::VDIVSQ) + .value("VDIVSW", LIEF::assembly::powerpc::OPCODE::VDIVSW) + .value("VDIVUD", LIEF::assembly::powerpc::OPCODE::VDIVUD) + .value("VDIVUQ", LIEF::assembly::powerpc::OPCODE::VDIVUQ) + .value("VDIVUW", LIEF::assembly::powerpc::OPCODE::VDIVUW) + .value("VEQV", LIEF::assembly::powerpc::OPCODE::VEQV) + .value("VEXPANDBM", LIEF::assembly::powerpc::OPCODE::VEXPANDBM) + .value("VEXPANDDM", LIEF::assembly::powerpc::OPCODE::VEXPANDDM) + .value("VEXPANDHM", LIEF::assembly::powerpc::OPCODE::VEXPANDHM) + .value("VEXPANDQM", LIEF::assembly::powerpc::OPCODE::VEXPANDQM) + .value("VEXPANDWM", LIEF::assembly::powerpc::OPCODE::VEXPANDWM) + .value("VEXPTEFP", LIEF::assembly::powerpc::OPCODE::VEXPTEFP) + .value("VEXTDDVLX", LIEF::assembly::powerpc::OPCODE::VEXTDDVLX) + .value("VEXTDDVRX", LIEF::assembly::powerpc::OPCODE::VEXTDDVRX) + .value("VEXTDUBVLX", LIEF::assembly::powerpc::OPCODE::VEXTDUBVLX) + .value("VEXTDUBVRX", LIEF::assembly::powerpc::OPCODE::VEXTDUBVRX) + .value("VEXTDUHVLX", LIEF::assembly::powerpc::OPCODE::VEXTDUHVLX) + .value("VEXTDUHVRX", LIEF::assembly::powerpc::OPCODE::VEXTDUHVRX) + .value("VEXTDUWVLX", LIEF::assembly::powerpc::OPCODE::VEXTDUWVLX) + .value("VEXTDUWVRX", LIEF::assembly::powerpc::OPCODE::VEXTDUWVRX) + .value("VEXTRACTBM", LIEF::assembly::powerpc::OPCODE::VEXTRACTBM) + .value("VEXTRACTD", LIEF::assembly::powerpc::OPCODE::VEXTRACTD) + .value("VEXTRACTDM", LIEF::assembly::powerpc::OPCODE::VEXTRACTDM) + .value("VEXTRACTHM", LIEF::assembly::powerpc::OPCODE::VEXTRACTHM) + .value("VEXTRACTQM", LIEF::assembly::powerpc::OPCODE::VEXTRACTQM) + .value("VEXTRACTUB", LIEF::assembly::powerpc::OPCODE::VEXTRACTUB) + .value("VEXTRACTUH", LIEF::assembly::powerpc::OPCODE::VEXTRACTUH) + .value("VEXTRACTUW", LIEF::assembly::powerpc::OPCODE::VEXTRACTUW) + .value("VEXTRACTWM", LIEF::assembly::powerpc::OPCODE::VEXTRACTWM) + .value("VEXTSB2D", LIEF::assembly::powerpc::OPCODE::VEXTSB2D) + .value("VEXTSB2Ds", LIEF::assembly::powerpc::OPCODE::VEXTSB2Ds) + .value("VEXTSB2W", LIEF::assembly::powerpc::OPCODE::VEXTSB2W) + .value("VEXTSB2Ws", LIEF::assembly::powerpc::OPCODE::VEXTSB2Ws) + .value("VEXTSD2Q", LIEF::assembly::powerpc::OPCODE::VEXTSD2Q) + .value("VEXTSH2D", LIEF::assembly::powerpc::OPCODE::VEXTSH2D) + .value("VEXTSH2Ds", LIEF::assembly::powerpc::OPCODE::VEXTSH2Ds) + .value("VEXTSH2W", LIEF::assembly::powerpc::OPCODE::VEXTSH2W) + .value("VEXTSH2Ws", LIEF::assembly::powerpc::OPCODE::VEXTSH2Ws) + .value("VEXTSW2D", LIEF::assembly::powerpc::OPCODE::VEXTSW2D) + .value("VEXTSW2Ds", LIEF::assembly::powerpc::OPCODE::VEXTSW2Ds) + .value("VEXTUBLX", LIEF::assembly::powerpc::OPCODE::VEXTUBLX) + .value("VEXTUBRX", LIEF::assembly::powerpc::OPCODE::VEXTUBRX) + .value("VEXTUHLX", LIEF::assembly::powerpc::OPCODE::VEXTUHLX) + .value("VEXTUHRX", LIEF::assembly::powerpc::OPCODE::VEXTUHRX) + .value("VEXTUWLX", LIEF::assembly::powerpc::OPCODE::VEXTUWLX) + .value("VEXTUWRX", LIEF::assembly::powerpc::OPCODE::VEXTUWRX) + .value("VGBBD", LIEF::assembly::powerpc::OPCODE::VGBBD) + .value("VGNB", LIEF::assembly::powerpc::OPCODE::VGNB) + .value("VINSBLX", LIEF::assembly::powerpc::OPCODE::VINSBLX) + .value("VINSBRX", LIEF::assembly::powerpc::OPCODE::VINSBRX) + .value("VINSBVLX", LIEF::assembly::powerpc::OPCODE::VINSBVLX) + .value("VINSBVRX", LIEF::assembly::powerpc::OPCODE::VINSBVRX) + .value("VINSD", LIEF::assembly::powerpc::OPCODE::VINSD) + .value("VINSDLX", LIEF::assembly::powerpc::OPCODE::VINSDLX) + .value("VINSDRX", LIEF::assembly::powerpc::OPCODE::VINSDRX) + .value("VINSERTB", LIEF::assembly::powerpc::OPCODE::VINSERTB) + .value("VINSERTD", LIEF::assembly::powerpc::OPCODE::VINSERTD) + .value("VINSERTH", LIEF::assembly::powerpc::OPCODE::VINSERTH) + .value("VINSERTW", LIEF::assembly::powerpc::OPCODE::VINSERTW) + .value("VINSHLX", LIEF::assembly::powerpc::OPCODE::VINSHLX) + .value("VINSHRX", LIEF::assembly::powerpc::OPCODE::VINSHRX) + .value("VINSHVLX", LIEF::assembly::powerpc::OPCODE::VINSHVLX) + .value("VINSHVRX", LIEF::assembly::powerpc::OPCODE::VINSHVRX) + .value("VINSW", LIEF::assembly::powerpc::OPCODE::VINSW) + .value("VINSWLX", LIEF::assembly::powerpc::OPCODE::VINSWLX) + .value("VINSWRX", LIEF::assembly::powerpc::OPCODE::VINSWRX) + .value("VINSWVLX", LIEF::assembly::powerpc::OPCODE::VINSWVLX) + .value("VINSWVRX", LIEF::assembly::powerpc::OPCODE::VINSWVRX) + .value("VLOGEFP", LIEF::assembly::powerpc::OPCODE::VLOGEFP) + .value("VMADDFP", LIEF::assembly::powerpc::OPCODE::VMADDFP) + .value("VMAXFP", LIEF::assembly::powerpc::OPCODE::VMAXFP) + .value("VMAXSB", LIEF::assembly::powerpc::OPCODE::VMAXSB) + .value("VMAXSD", LIEF::assembly::powerpc::OPCODE::VMAXSD) + .value("VMAXSH", LIEF::assembly::powerpc::OPCODE::VMAXSH) + .value("VMAXSW", LIEF::assembly::powerpc::OPCODE::VMAXSW) + .value("VMAXUB", LIEF::assembly::powerpc::OPCODE::VMAXUB) + .value("VMAXUD", LIEF::assembly::powerpc::OPCODE::VMAXUD) + .value("VMAXUH", LIEF::assembly::powerpc::OPCODE::VMAXUH) + .value("VMAXUW", LIEF::assembly::powerpc::OPCODE::VMAXUW) + .value("VMHADDSHS", LIEF::assembly::powerpc::OPCODE::VMHADDSHS) + .value("VMHRADDSHS", LIEF::assembly::powerpc::OPCODE::VMHRADDSHS) + .value("VMINFP", LIEF::assembly::powerpc::OPCODE::VMINFP) + .value("VMINSB", LIEF::assembly::powerpc::OPCODE::VMINSB) + .value("VMINSD", LIEF::assembly::powerpc::OPCODE::VMINSD); + opcodes.value("VMINSH", LIEF::assembly::powerpc::OPCODE::VMINSH) + .value("VMINSW", LIEF::assembly::powerpc::OPCODE::VMINSW) + .value("VMINUB", LIEF::assembly::powerpc::OPCODE::VMINUB) + .value("VMINUD", LIEF::assembly::powerpc::OPCODE::VMINUD) + .value("VMINUH", LIEF::assembly::powerpc::OPCODE::VMINUH) + .value("VMINUW", LIEF::assembly::powerpc::OPCODE::VMINUW) + .value("VMLADDUHM", LIEF::assembly::powerpc::OPCODE::VMLADDUHM) + .value("VMODSD", LIEF::assembly::powerpc::OPCODE::VMODSD) + .value("VMODSQ", LIEF::assembly::powerpc::OPCODE::VMODSQ) + .value("VMODSW", LIEF::assembly::powerpc::OPCODE::VMODSW) + .value("VMODUD", LIEF::assembly::powerpc::OPCODE::VMODUD) + .value("VMODUQ", LIEF::assembly::powerpc::OPCODE::VMODUQ) + .value("VMODUW", LIEF::assembly::powerpc::OPCODE::VMODUW) + .value("VMRGEW", LIEF::assembly::powerpc::OPCODE::VMRGEW) + .value("VMRGHB", LIEF::assembly::powerpc::OPCODE::VMRGHB) + .value("VMRGHH", LIEF::assembly::powerpc::OPCODE::VMRGHH) + .value("VMRGHW", LIEF::assembly::powerpc::OPCODE::VMRGHW) + .value("VMRGLB", LIEF::assembly::powerpc::OPCODE::VMRGLB) + .value("VMRGLH", LIEF::assembly::powerpc::OPCODE::VMRGLH) + .value("VMRGLW", LIEF::assembly::powerpc::OPCODE::VMRGLW) + .value("VMRGOW", LIEF::assembly::powerpc::OPCODE::VMRGOW) + .value("VMSUMCUD", LIEF::assembly::powerpc::OPCODE::VMSUMCUD) + .value("VMSUMMBM", LIEF::assembly::powerpc::OPCODE::VMSUMMBM) + .value("VMSUMSHM", LIEF::assembly::powerpc::OPCODE::VMSUMSHM) + .value("VMSUMSHS", LIEF::assembly::powerpc::OPCODE::VMSUMSHS) + .value("VMSUMUBM", LIEF::assembly::powerpc::OPCODE::VMSUMUBM) + .value("VMSUMUDM", LIEF::assembly::powerpc::OPCODE::VMSUMUDM) + .value("VMSUMUHM", LIEF::assembly::powerpc::OPCODE::VMSUMUHM) + .value("VMSUMUHS", LIEF::assembly::powerpc::OPCODE::VMSUMUHS) + .value("VMUL10CUQ", LIEF::assembly::powerpc::OPCODE::VMUL10CUQ) + .value("VMUL10ECUQ", LIEF::assembly::powerpc::OPCODE::VMUL10ECUQ) + .value("VMUL10EUQ", LIEF::assembly::powerpc::OPCODE::VMUL10EUQ) + .value("VMUL10UQ", LIEF::assembly::powerpc::OPCODE::VMUL10UQ) + .value("VMULESB", LIEF::assembly::powerpc::OPCODE::VMULESB) + .value("VMULESD", LIEF::assembly::powerpc::OPCODE::VMULESD) + .value("VMULESH", LIEF::assembly::powerpc::OPCODE::VMULESH) + .value("VMULESW", LIEF::assembly::powerpc::OPCODE::VMULESW) + .value("VMULEUB", LIEF::assembly::powerpc::OPCODE::VMULEUB) + .value("VMULEUD", LIEF::assembly::powerpc::OPCODE::VMULEUD) + .value("VMULEUH", LIEF::assembly::powerpc::OPCODE::VMULEUH) + .value("VMULEUW", LIEF::assembly::powerpc::OPCODE::VMULEUW) + .value("VMULHSD", LIEF::assembly::powerpc::OPCODE::VMULHSD) + .value("VMULHSW", LIEF::assembly::powerpc::OPCODE::VMULHSW) + .value("VMULHUD", LIEF::assembly::powerpc::OPCODE::VMULHUD) + .value("VMULHUW", LIEF::assembly::powerpc::OPCODE::VMULHUW) + .value("VMULLD", LIEF::assembly::powerpc::OPCODE::VMULLD) + .value("VMULOSB", LIEF::assembly::powerpc::OPCODE::VMULOSB) + .value("VMULOSD", LIEF::assembly::powerpc::OPCODE::VMULOSD) + .value("VMULOSH", LIEF::assembly::powerpc::OPCODE::VMULOSH) + .value("VMULOSW", LIEF::assembly::powerpc::OPCODE::VMULOSW) + .value("VMULOUB", LIEF::assembly::powerpc::OPCODE::VMULOUB) + .value("VMULOUD", LIEF::assembly::powerpc::OPCODE::VMULOUD) + .value("VMULOUH", LIEF::assembly::powerpc::OPCODE::VMULOUH) + .value("VMULOUW", LIEF::assembly::powerpc::OPCODE::VMULOUW) + .value("VMULUWM", LIEF::assembly::powerpc::OPCODE::VMULUWM) + .value("VNAND", LIEF::assembly::powerpc::OPCODE::VNAND) + .value("VNCIPHER", LIEF::assembly::powerpc::OPCODE::VNCIPHER) + .value("VNCIPHERLAST", LIEF::assembly::powerpc::OPCODE::VNCIPHERLAST) + .value("VNEGD", LIEF::assembly::powerpc::OPCODE::VNEGD) + .value("VNEGW", LIEF::assembly::powerpc::OPCODE::VNEGW) + .value("VNMSUBFP", LIEF::assembly::powerpc::OPCODE::VNMSUBFP) + .value("VNOR", LIEF::assembly::powerpc::OPCODE::VNOR) + .value("VOR", LIEF::assembly::powerpc::OPCODE::VOR) + .value("VORC", LIEF::assembly::powerpc::OPCODE::VORC) + .value("VPDEPD", LIEF::assembly::powerpc::OPCODE::VPDEPD) + .value("VPERM", LIEF::assembly::powerpc::OPCODE::VPERM) + .value("VPERMR", LIEF::assembly::powerpc::OPCODE::VPERMR) + .value("VPERMXOR", LIEF::assembly::powerpc::OPCODE::VPERMXOR) + .value("VPEXTD", LIEF::assembly::powerpc::OPCODE::VPEXTD) + .value("VPKPX", LIEF::assembly::powerpc::OPCODE::VPKPX) + .value("VPKSDSS", LIEF::assembly::powerpc::OPCODE::VPKSDSS) + .value("VPKSDUS", LIEF::assembly::powerpc::OPCODE::VPKSDUS) + .value("VPKSHSS", LIEF::assembly::powerpc::OPCODE::VPKSHSS) + .value("VPKSHUS", LIEF::assembly::powerpc::OPCODE::VPKSHUS) + .value("VPKSWSS", LIEF::assembly::powerpc::OPCODE::VPKSWSS) + .value("VPKSWUS", LIEF::assembly::powerpc::OPCODE::VPKSWUS) + .value("VPKUDUM", LIEF::assembly::powerpc::OPCODE::VPKUDUM) + .value("VPKUDUS", LIEF::assembly::powerpc::OPCODE::VPKUDUS) + .value("VPKUHUM", LIEF::assembly::powerpc::OPCODE::VPKUHUM) + .value("VPKUHUS", LIEF::assembly::powerpc::OPCODE::VPKUHUS) + .value("VPKUWUM", LIEF::assembly::powerpc::OPCODE::VPKUWUM) + .value("VPKUWUS", LIEF::assembly::powerpc::OPCODE::VPKUWUS) + .value("VPMSUMB", LIEF::assembly::powerpc::OPCODE::VPMSUMB) + .value("VPMSUMD", LIEF::assembly::powerpc::OPCODE::VPMSUMD) + .value("VPMSUMH", LIEF::assembly::powerpc::OPCODE::VPMSUMH) + .value("VPMSUMW", LIEF::assembly::powerpc::OPCODE::VPMSUMW) + .value("VPOPCNTB", LIEF::assembly::powerpc::OPCODE::VPOPCNTB) + .value("VPOPCNTD", LIEF::assembly::powerpc::OPCODE::VPOPCNTD) + .value("VPOPCNTH", LIEF::assembly::powerpc::OPCODE::VPOPCNTH) + .value("VPOPCNTW", LIEF::assembly::powerpc::OPCODE::VPOPCNTW) + .value("VPRTYBD", LIEF::assembly::powerpc::OPCODE::VPRTYBD) + .value("VPRTYBQ", LIEF::assembly::powerpc::OPCODE::VPRTYBQ) + .value("VPRTYBW", LIEF::assembly::powerpc::OPCODE::VPRTYBW) + .value("VREFP", LIEF::assembly::powerpc::OPCODE::VREFP) + .value("VRFIM", LIEF::assembly::powerpc::OPCODE::VRFIM) + .value("VRFIN", LIEF::assembly::powerpc::OPCODE::VRFIN) + .value("VRFIP", LIEF::assembly::powerpc::OPCODE::VRFIP) + .value("VRFIZ", LIEF::assembly::powerpc::OPCODE::VRFIZ) + .value("VRLB", LIEF::assembly::powerpc::OPCODE::VRLB) + .value("VRLD", LIEF::assembly::powerpc::OPCODE::VRLD) + .value("VRLDMI", LIEF::assembly::powerpc::OPCODE::VRLDMI) + .value("VRLDNM", LIEF::assembly::powerpc::OPCODE::VRLDNM) + .value("VRLH", LIEF::assembly::powerpc::OPCODE::VRLH) + .value("VRLQ", LIEF::assembly::powerpc::OPCODE::VRLQ) + .value("VRLQMI", LIEF::assembly::powerpc::OPCODE::VRLQMI) + .value("VRLQNM", LIEF::assembly::powerpc::OPCODE::VRLQNM) + .value("VRLW", LIEF::assembly::powerpc::OPCODE::VRLW) + .value("VRLWMI", LIEF::assembly::powerpc::OPCODE::VRLWMI) + .value("VRLWNM", LIEF::assembly::powerpc::OPCODE::VRLWNM) + .value("VRSQRTEFP", LIEF::assembly::powerpc::OPCODE::VRSQRTEFP) + .value("VSBOX", LIEF::assembly::powerpc::OPCODE::VSBOX) + .value("VSEL", LIEF::assembly::powerpc::OPCODE::VSEL) + .value("VSHASIGMAD", LIEF::assembly::powerpc::OPCODE::VSHASIGMAD) + .value("VSHASIGMAW", LIEF::assembly::powerpc::OPCODE::VSHASIGMAW) + .value("VSL", LIEF::assembly::powerpc::OPCODE::VSL) + .value("VSLB", LIEF::assembly::powerpc::OPCODE::VSLB) + .value("VSLD", LIEF::assembly::powerpc::OPCODE::VSLD) + .value("VSLDBI", LIEF::assembly::powerpc::OPCODE::VSLDBI) + .value("VSLDOI", LIEF::assembly::powerpc::OPCODE::VSLDOI) + .value("VSLH", LIEF::assembly::powerpc::OPCODE::VSLH) + .value("VSLO", LIEF::assembly::powerpc::OPCODE::VSLO) + .value("VSLQ", LIEF::assembly::powerpc::OPCODE::VSLQ) + .value("VSLV", LIEF::assembly::powerpc::OPCODE::VSLV) + .value("VSLW", LIEF::assembly::powerpc::OPCODE::VSLW) + .value("VSPLTB", LIEF::assembly::powerpc::OPCODE::VSPLTB) + .value("VSPLTBs", LIEF::assembly::powerpc::OPCODE::VSPLTBs) + .value("VSPLTH", LIEF::assembly::powerpc::OPCODE::VSPLTH) + .value("VSPLTHs", LIEF::assembly::powerpc::OPCODE::VSPLTHs) + .value("VSPLTISB", LIEF::assembly::powerpc::OPCODE::VSPLTISB) + .value("VSPLTISH", LIEF::assembly::powerpc::OPCODE::VSPLTISH) + .value("VSPLTISW", LIEF::assembly::powerpc::OPCODE::VSPLTISW) + .value("VSPLTW", LIEF::assembly::powerpc::OPCODE::VSPLTW) + .value("VSR", LIEF::assembly::powerpc::OPCODE::VSR) + .value("VSRAB", LIEF::assembly::powerpc::OPCODE::VSRAB) + .value("VSRAD", LIEF::assembly::powerpc::OPCODE::VSRAD) + .value("VSRAH", LIEF::assembly::powerpc::OPCODE::VSRAH) + .value("VSRAQ", LIEF::assembly::powerpc::OPCODE::VSRAQ) + .value("VSRAW", LIEF::assembly::powerpc::OPCODE::VSRAW) + .value("VSRB", LIEF::assembly::powerpc::OPCODE::VSRB) + .value("VSRD", LIEF::assembly::powerpc::OPCODE::VSRD) + .value("VSRDBI", LIEF::assembly::powerpc::OPCODE::VSRDBI) + .value("VSRH", LIEF::assembly::powerpc::OPCODE::VSRH) + .value("VSRO", LIEF::assembly::powerpc::OPCODE::VSRO) + .value("VSRQ", LIEF::assembly::powerpc::OPCODE::VSRQ) + .value("VSRV", LIEF::assembly::powerpc::OPCODE::VSRV) + .value("VSRW", LIEF::assembly::powerpc::OPCODE::VSRW) + .value("VSTRIBL", LIEF::assembly::powerpc::OPCODE::VSTRIBL) + .value("VSTRIBL_rec", LIEF::assembly::powerpc::OPCODE::VSTRIBL_rec) + .value("VSTRIBR", LIEF::assembly::powerpc::OPCODE::VSTRIBR) + .value("VSTRIBR_rec", LIEF::assembly::powerpc::OPCODE::VSTRIBR_rec) + .value("VSTRIHL", LIEF::assembly::powerpc::OPCODE::VSTRIHL) + .value("VSTRIHL_rec", LIEF::assembly::powerpc::OPCODE::VSTRIHL_rec) + .value("VSTRIHR", LIEF::assembly::powerpc::OPCODE::VSTRIHR) + .value("VSTRIHR_rec", LIEF::assembly::powerpc::OPCODE::VSTRIHR_rec) + .value("VSUBCUQ", LIEF::assembly::powerpc::OPCODE::VSUBCUQ) + .value("VSUBCUW", LIEF::assembly::powerpc::OPCODE::VSUBCUW) + .value("VSUBECUQ", LIEF::assembly::powerpc::OPCODE::VSUBECUQ) + .value("VSUBEUQM", LIEF::assembly::powerpc::OPCODE::VSUBEUQM) + .value("VSUBFP", LIEF::assembly::powerpc::OPCODE::VSUBFP) + .value("VSUBSBS", LIEF::assembly::powerpc::OPCODE::VSUBSBS) + .value("VSUBSHS", LIEF::assembly::powerpc::OPCODE::VSUBSHS) + .value("VSUBSWS", LIEF::assembly::powerpc::OPCODE::VSUBSWS) + .value("VSUBUBM", LIEF::assembly::powerpc::OPCODE::VSUBUBM) + .value("VSUBUBS", LIEF::assembly::powerpc::OPCODE::VSUBUBS) + .value("VSUBUDM", LIEF::assembly::powerpc::OPCODE::VSUBUDM) + .value("VSUBUHM", LIEF::assembly::powerpc::OPCODE::VSUBUHM) + .value("VSUBUHS", LIEF::assembly::powerpc::OPCODE::VSUBUHS) + .value("VSUBUQM", LIEF::assembly::powerpc::OPCODE::VSUBUQM) + .value("VSUBUWM", LIEF::assembly::powerpc::OPCODE::VSUBUWM) + .value("VSUBUWS", LIEF::assembly::powerpc::OPCODE::VSUBUWS) + .value("VSUM2SWS", LIEF::assembly::powerpc::OPCODE::VSUM2SWS) + .value("VSUM4SBS", LIEF::assembly::powerpc::OPCODE::VSUM4SBS) + .value("VSUM4SHS", LIEF::assembly::powerpc::OPCODE::VSUM4SHS) + .value("VSUM4UBS", LIEF::assembly::powerpc::OPCODE::VSUM4UBS) + .value("VSUMSWS", LIEF::assembly::powerpc::OPCODE::VSUMSWS) + .value("VUCMPRHB", LIEF::assembly::powerpc::OPCODE::VUCMPRHB) + .value("VUCMPRHH", LIEF::assembly::powerpc::OPCODE::VUCMPRHH) + .value("VUCMPRHN", LIEF::assembly::powerpc::OPCODE::VUCMPRHN) + .value("VUCMPRLB", LIEF::assembly::powerpc::OPCODE::VUCMPRLB) + .value("VUCMPRLH", LIEF::assembly::powerpc::OPCODE::VUCMPRLH) + .value("VUCMPRLN", LIEF::assembly::powerpc::OPCODE::VUCMPRLN) + .value("VUPKHPX", LIEF::assembly::powerpc::OPCODE::VUPKHPX) + .value("VUPKHSB", LIEF::assembly::powerpc::OPCODE::VUPKHSB) + .value("VUPKHSH", LIEF::assembly::powerpc::OPCODE::VUPKHSH) + .value("VUPKHSNTOB", LIEF::assembly::powerpc::OPCODE::VUPKHSNTOB) + .value("VUPKHSW", LIEF::assembly::powerpc::OPCODE::VUPKHSW) + .value("VUPKINT4TOBF16", LIEF::assembly::powerpc::OPCODE::VUPKINT4TOBF16) + .value("VUPKINT4TOFP32", LIEF::assembly::powerpc::OPCODE::VUPKINT4TOFP32) + .value("VUPKINT8TOBF16", LIEF::assembly::powerpc::OPCODE::VUPKINT8TOBF16) + .value("VUPKINT8TOFP32", LIEF::assembly::powerpc::OPCODE::VUPKINT8TOFP32) + .value("VUPKLPX", LIEF::assembly::powerpc::OPCODE::VUPKLPX) + .value("VUPKLSB", LIEF::assembly::powerpc::OPCODE::VUPKLSB) + .value("VUPKLSH", LIEF::assembly::powerpc::OPCODE::VUPKLSH) + .value("VUPKLSNTOB", LIEF::assembly::powerpc::OPCODE::VUPKLSNTOB) + .value("VUPKLSW", LIEF::assembly::powerpc::OPCODE::VUPKLSW) + .value("VXOR", LIEF::assembly::powerpc::OPCODE::VXOR) + .value("V_SET0", LIEF::assembly::powerpc::OPCODE::V_SET0) + .value("V_SET0B", LIEF::assembly::powerpc::OPCODE::V_SET0B) + .value("V_SET0H", LIEF::assembly::powerpc::OPCODE::V_SET0H) + .value("V_SETALLONES", LIEF::assembly::powerpc::OPCODE::V_SETALLONES) + .value("V_SETALLONESB", LIEF::assembly::powerpc::OPCODE::V_SETALLONESB) + .value("V_SETALLONESH", LIEF::assembly::powerpc::OPCODE::V_SETALLONESH) + .value("WAIT", LIEF::assembly::powerpc::OPCODE::WAIT) + .value("WAITP10", LIEF::assembly::powerpc::OPCODE::WAITP10) + .value("WRTEE", LIEF::assembly::powerpc::OPCODE::WRTEE) + .value("WRTEEI", LIEF::assembly::powerpc::OPCODE::WRTEEI) + .value("XOR", LIEF::assembly::powerpc::OPCODE::XOR) + .value("XOR8", LIEF::assembly::powerpc::OPCODE::XOR8) + .value("XOR8_rec", LIEF::assembly::powerpc::OPCODE::XOR8_rec) + .value("XORI", LIEF::assembly::powerpc::OPCODE::XORI) + .value("XORI8", LIEF::assembly::powerpc::OPCODE::XORI8) + .value("XORIS", LIEF::assembly::powerpc::OPCODE::XORIS) + .value("XORIS8", LIEF::assembly::powerpc::OPCODE::XORIS8) + .value("XOR_rec", LIEF::assembly::powerpc::OPCODE::XOR_rec) + .value("XSABSDP", LIEF::assembly::powerpc::OPCODE::XSABSDP) + .value("XSABSQP", LIEF::assembly::powerpc::OPCODE::XSABSQP) + .value("XSADDADDSUQM", LIEF::assembly::powerpc::OPCODE::XSADDADDSUQM) + .value("XSADDADDUQM", LIEF::assembly::powerpc::OPCODE::XSADDADDUQM) + .value("XSADDDP", LIEF::assembly::powerpc::OPCODE::XSADDDP) + .value("XSADDQP", LIEF::assembly::powerpc::OPCODE::XSADDQP) + .value("XSADDQPO", LIEF::assembly::powerpc::OPCODE::XSADDQPO) + .value("XSADDSP", LIEF::assembly::powerpc::OPCODE::XSADDSP) + .value("XSADDSUBSUQM", LIEF::assembly::powerpc::OPCODE::XSADDSUBSUQM) + .value("XSADDSUBUQM", LIEF::assembly::powerpc::OPCODE::XSADDSUBUQM) + .value("XSCMPEQDP", LIEF::assembly::powerpc::OPCODE::XSCMPEQDP) + .value("XSCMPEQQP", LIEF::assembly::powerpc::OPCODE::XSCMPEQQP) + .value("XSCMPEXPDP", LIEF::assembly::powerpc::OPCODE::XSCMPEXPDP) + .value("XSCMPEXPQP", LIEF::assembly::powerpc::OPCODE::XSCMPEXPQP) + .value("XSCMPGEDP", LIEF::assembly::powerpc::OPCODE::XSCMPGEDP) + .value("XSCMPGEQP", LIEF::assembly::powerpc::OPCODE::XSCMPGEQP) + .value("XSCMPGTDP", LIEF::assembly::powerpc::OPCODE::XSCMPGTDP) + .value("XSCMPGTQP", LIEF::assembly::powerpc::OPCODE::XSCMPGTQP) + .value("XSCMPODP", LIEF::assembly::powerpc::OPCODE::XSCMPODP) + .value("XSCMPOQP", LIEF::assembly::powerpc::OPCODE::XSCMPOQP) + .value("XSCMPUDP", LIEF::assembly::powerpc::OPCODE::XSCMPUDP) + .value("XSCMPUQP", LIEF::assembly::powerpc::OPCODE::XSCMPUQP) + .value("XSCPSGNDP", LIEF::assembly::powerpc::OPCODE::XSCPSGNDP) + .value("XSCPSGNQP", LIEF::assembly::powerpc::OPCODE::XSCPSGNQP) + .value("XSCVDPHP", LIEF::assembly::powerpc::OPCODE::XSCVDPHP) + .value("XSCVDPQP", LIEF::assembly::powerpc::OPCODE::XSCVDPQP) + .value("XSCVDPSP", LIEF::assembly::powerpc::OPCODE::XSCVDPSP) + .value("XSCVDPSPN", LIEF::assembly::powerpc::OPCODE::XSCVDPSPN) + .value("XSCVDPSXDS", LIEF::assembly::powerpc::OPCODE::XSCVDPSXDS) + .value("XSCVDPSXDSs", LIEF::assembly::powerpc::OPCODE::XSCVDPSXDSs) + .value("XSCVDPSXWS", LIEF::assembly::powerpc::OPCODE::XSCVDPSXWS) + .value("XSCVDPSXWSs", LIEF::assembly::powerpc::OPCODE::XSCVDPSXWSs) + .value("XSCVDPUXDS", LIEF::assembly::powerpc::OPCODE::XSCVDPUXDS) + .value("XSCVDPUXDSs", LIEF::assembly::powerpc::OPCODE::XSCVDPUXDSs) + .value("XSCVDPUXWS", LIEF::assembly::powerpc::OPCODE::XSCVDPUXWS) + .value("XSCVDPUXWSs", LIEF::assembly::powerpc::OPCODE::XSCVDPUXWSs) + .value("XSCVHPDP", LIEF::assembly::powerpc::OPCODE::XSCVHPDP) + .value("XSCVQPDP", LIEF::assembly::powerpc::OPCODE::XSCVQPDP) + .value("XSCVQPDPO", LIEF::assembly::powerpc::OPCODE::XSCVQPDPO) + .value("XSCVQPSDZ", LIEF::assembly::powerpc::OPCODE::XSCVQPSDZ) + .value("XSCVQPSQZ", LIEF::assembly::powerpc::OPCODE::XSCVQPSQZ) + .value("XSCVQPSWZ", LIEF::assembly::powerpc::OPCODE::XSCVQPSWZ) + .value("XSCVQPUDZ", LIEF::assembly::powerpc::OPCODE::XSCVQPUDZ) + .value("XSCVQPUQZ", LIEF::assembly::powerpc::OPCODE::XSCVQPUQZ) + .value("XSCVQPUWZ", LIEF::assembly::powerpc::OPCODE::XSCVQPUWZ) + .value("XSCVSDQP", LIEF::assembly::powerpc::OPCODE::XSCVSDQP) + .value("XSCVSPDP", LIEF::assembly::powerpc::OPCODE::XSCVSPDP) + .value("XSCVSPDPN", LIEF::assembly::powerpc::OPCODE::XSCVSPDPN) + .value("XSCVSQQP", LIEF::assembly::powerpc::OPCODE::XSCVSQQP) + .value("XSCVSXDDP", LIEF::assembly::powerpc::OPCODE::XSCVSXDDP) + .value("XSCVSXDSP", LIEF::assembly::powerpc::OPCODE::XSCVSXDSP) + .value("XSCVUDQP", LIEF::assembly::powerpc::OPCODE::XSCVUDQP) + .value("XSCVUQQP", LIEF::assembly::powerpc::OPCODE::XSCVUQQP) + .value("XSCVUXDDP", LIEF::assembly::powerpc::OPCODE::XSCVUXDDP) + .value("XSCVUXDSP", LIEF::assembly::powerpc::OPCODE::XSCVUXDSP) + .value("XSDIVDP", LIEF::assembly::powerpc::OPCODE::XSDIVDP) + .value("XSDIVQP", LIEF::assembly::powerpc::OPCODE::XSDIVQP) + .value("XSDIVQPO", LIEF::assembly::powerpc::OPCODE::XSDIVQPO) + .value("XSDIVSP", LIEF::assembly::powerpc::OPCODE::XSDIVSP) + .value("XSIEXPDP", LIEF::assembly::powerpc::OPCODE::XSIEXPDP) + .value("XSIEXPQP", LIEF::assembly::powerpc::OPCODE::XSIEXPQP) + .value("XSMADDADP", LIEF::assembly::powerpc::OPCODE::XSMADDADP) + .value("XSMADDASP", LIEF::assembly::powerpc::OPCODE::XSMADDASP) + .value("XSMADDMDP", LIEF::assembly::powerpc::OPCODE::XSMADDMDP) + .value("XSMADDMSP", LIEF::assembly::powerpc::OPCODE::XSMADDMSP) + .value("XSMADDQP", LIEF::assembly::powerpc::OPCODE::XSMADDQP) + .value("XSMADDQPO", LIEF::assembly::powerpc::OPCODE::XSMADDQPO) + .value("XSMAXCDP", LIEF::assembly::powerpc::OPCODE::XSMAXCDP) + .value("XSMAXCQP", LIEF::assembly::powerpc::OPCODE::XSMAXCQP) + .value("XSMAXDP", LIEF::assembly::powerpc::OPCODE::XSMAXDP) + .value("XSMAXJDP", LIEF::assembly::powerpc::OPCODE::XSMAXJDP) + .value("XSMERGE2T1UQM", LIEF::assembly::powerpc::OPCODE::XSMERGE2T1UQM) + .value("XSMERGE2T2UQM", LIEF::assembly::powerpc::OPCODE::XSMERGE2T2UQM) + .value("XSMERGE2T3UQM", LIEF::assembly::powerpc::OPCODE::XSMERGE2T3UQM) + .value("XSMERGE3T1UQM", LIEF::assembly::powerpc::OPCODE::XSMERGE3T1UQM) + .value("XSMINCDP", LIEF::assembly::powerpc::OPCODE::XSMINCDP) + .value("XSMINCQP", LIEF::assembly::powerpc::OPCODE::XSMINCQP) + .value("XSMINDP", LIEF::assembly::powerpc::OPCODE::XSMINDP) + .value("XSMINJDP", LIEF::assembly::powerpc::OPCODE::XSMINJDP) + .value("XSMSUBADP", LIEF::assembly::powerpc::OPCODE::XSMSUBADP) + .value("XSMSUBASP", LIEF::assembly::powerpc::OPCODE::XSMSUBASP) + .value("XSMSUBMDP", LIEF::assembly::powerpc::OPCODE::XSMSUBMDP) + .value("XSMSUBMSP", LIEF::assembly::powerpc::OPCODE::XSMSUBMSP) + .value("XSMSUBQP", LIEF::assembly::powerpc::OPCODE::XSMSUBQP) + .value("XSMSUBQPO", LIEF::assembly::powerpc::OPCODE::XSMSUBQPO) + .value("XSMULDP", LIEF::assembly::powerpc::OPCODE::XSMULDP); + opcodes.value("XSMULQP", LIEF::assembly::powerpc::OPCODE::XSMULQP) + .value("XSMULQPO", LIEF::assembly::powerpc::OPCODE::XSMULQPO) + .value("XSMULSP", LIEF::assembly::powerpc::OPCODE::XSMULSP) + .value("XSNABSDP", LIEF::assembly::powerpc::OPCODE::XSNABSDP) + .value("XSNABSDPs", LIEF::assembly::powerpc::OPCODE::XSNABSDPs) + .value("XSNABSQP", LIEF::assembly::powerpc::OPCODE::XSNABSQP) + .value("XSNEGDP", LIEF::assembly::powerpc::OPCODE::XSNEGDP) + .value("XSNEGQP", LIEF::assembly::powerpc::OPCODE::XSNEGQP) + .value("XSNMADDADP", LIEF::assembly::powerpc::OPCODE::XSNMADDADP) + .value("XSNMADDASP", LIEF::assembly::powerpc::OPCODE::XSNMADDASP) + .value("XSNMADDMDP", LIEF::assembly::powerpc::OPCODE::XSNMADDMDP) + .value("XSNMADDMSP", LIEF::assembly::powerpc::OPCODE::XSNMADDMSP) + .value("XSNMADDQP", LIEF::assembly::powerpc::OPCODE::XSNMADDQP) + .value("XSNMADDQPO", LIEF::assembly::powerpc::OPCODE::XSNMADDQPO) + .value("XSNMSUBADP", LIEF::assembly::powerpc::OPCODE::XSNMSUBADP) + .value("XSNMSUBASP", LIEF::assembly::powerpc::OPCODE::XSNMSUBASP) + .value("XSNMSUBMDP", LIEF::assembly::powerpc::OPCODE::XSNMSUBMDP) + .value("XSNMSUBMSP", LIEF::assembly::powerpc::OPCODE::XSNMSUBMSP) + .value("XSNMSUBQP", LIEF::assembly::powerpc::OPCODE::XSNMSUBQP) + .value("XSNMSUBQPO", LIEF::assembly::powerpc::OPCODE::XSNMSUBQPO) + .value("XSRDPI", LIEF::assembly::powerpc::OPCODE::XSRDPI) + .value("XSRDPIC", LIEF::assembly::powerpc::OPCODE::XSRDPIC) + .value("XSRDPIM", LIEF::assembly::powerpc::OPCODE::XSRDPIM) + .value("XSRDPIP", LIEF::assembly::powerpc::OPCODE::XSRDPIP) + .value("XSRDPIZ", LIEF::assembly::powerpc::OPCODE::XSRDPIZ) + .value("XSREBASE2T1UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE2T1UQM) + .value("XSREBASE2T2UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE2T2UQM) + .value("XSREBASE2T3UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE2T3UQM) + .value("XSREBASE2T4UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE2T4UQM) + .value("XSREBASE3T1UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE3T1UQM) + .value("XSREBASE3T2UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE3T2UQM) + .value("XSREBASE3T3UQM", LIEF::assembly::powerpc::OPCODE::XSREBASE3T3UQM) + .value("XSREDP", LIEF::assembly::powerpc::OPCODE::XSREDP) + .value("XSRESP", LIEF::assembly::powerpc::OPCODE::XSRESP) + .value("XSRQPI", LIEF::assembly::powerpc::OPCODE::XSRQPI) + .value("XSRQPIX", LIEF::assembly::powerpc::OPCODE::XSRQPIX) + .value("XSRQPXP", LIEF::assembly::powerpc::OPCODE::XSRQPXP) + .value("XSRSP", LIEF::assembly::powerpc::OPCODE::XSRSP) + .value("XSRSQRTEDP", LIEF::assembly::powerpc::OPCODE::XSRSQRTEDP) + .value("XSRSQRTESP", LIEF::assembly::powerpc::OPCODE::XSRSQRTESP) + .value("XSSQRTDP", LIEF::assembly::powerpc::OPCODE::XSSQRTDP) + .value("XSSQRTQP", LIEF::assembly::powerpc::OPCODE::XSSQRTQP) + .value("XSSQRTQPO", LIEF::assembly::powerpc::OPCODE::XSSQRTQPO) + .value("XSSQRTSP", LIEF::assembly::powerpc::OPCODE::XSSQRTSP) + .value("XSSUBDP", LIEF::assembly::powerpc::OPCODE::XSSUBDP) + .value("XSSUBQP", LIEF::assembly::powerpc::OPCODE::XSSUBQP) + .value("XSSUBQPO", LIEF::assembly::powerpc::OPCODE::XSSUBQPO) + .value("XSSUBSP", LIEF::assembly::powerpc::OPCODE::XSSUBSP) + .value("XSTDIVDP", LIEF::assembly::powerpc::OPCODE::XSTDIVDP) + .value("XSTSQRTDP", LIEF::assembly::powerpc::OPCODE::XSTSQRTDP) + .value("XSTSTDCDP", LIEF::assembly::powerpc::OPCODE::XSTSTDCDP) + .value("XSTSTDCQP", LIEF::assembly::powerpc::OPCODE::XSTSTDCQP) + .value("XSTSTDCSP", LIEF::assembly::powerpc::OPCODE::XSTSTDCSP) + .value("XSXEXPDP", LIEF::assembly::powerpc::OPCODE::XSXEXPDP) + .value("XSXEXPQP", LIEF::assembly::powerpc::OPCODE::XSXEXPQP) + .value("XSXSIGDP", LIEF::assembly::powerpc::OPCODE::XSXSIGDP) + .value("XSXSIGQP", LIEF::assembly::powerpc::OPCODE::XSXSIGQP) + .value("XVABSDP", LIEF::assembly::powerpc::OPCODE::XVABSDP) + .value("XVABSSP", LIEF::assembly::powerpc::OPCODE::XVABSSP) + .value("XVADDDP", LIEF::assembly::powerpc::OPCODE::XVADDDP) + .value("XVADDSP", LIEF::assembly::powerpc::OPCODE::XVADDSP) + .value("XVADDUHM", LIEF::assembly::powerpc::OPCODE::XVADDUHM) + .value("XVADDUWM", LIEF::assembly::powerpc::OPCODE::XVADDUWM) + .value("XVBF16GER2", LIEF::assembly::powerpc::OPCODE::XVBF16GER2) + .value("XVBF16GER2NN", LIEF::assembly::powerpc::OPCODE::XVBF16GER2NN) + .value("XVBF16GER2NP", LIEF::assembly::powerpc::OPCODE::XVBF16GER2NP) + .value("XVBF16GER2PN", LIEF::assembly::powerpc::OPCODE::XVBF16GER2PN) + .value("XVBF16GER2PP", LIEF::assembly::powerpc::OPCODE::XVBF16GER2PP) + .value("XVBF16GER2W", LIEF::assembly::powerpc::OPCODE::XVBF16GER2W) + .value("XVBF16GER2WNN", LIEF::assembly::powerpc::OPCODE::XVBF16GER2WNN) + .value("XVBF16GER2WNP", LIEF::assembly::powerpc::OPCODE::XVBF16GER2WNP) + .value("XVBF16GER2WPN", LIEF::assembly::powerpc::OPCODE::XVBF16GER2WPN) + .value("XVBF16GER2WPP", LIEF::assembly::powerpc::OPCODE::XVBF16GER2WPP) + .value("XVCMPEQDP", LIEF::assembly::powerpc::OPCODE::XVCMPEQDP) + .value("XVCMPEQDP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPEQDP_rec) + .value("XVCMPEQSP", LIEF::assembly::powerpc::OPCODE::XVCMPEQSP) + .value("XVCMPEQSP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPEQSP_rec) + .value("XVCMPGEDP", LIEF::assembly::powerpc::OPCODE::XVCMPGEDP) + .value("XVCMPGEDP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPGEDP_rec) + .value("XVCMPGESP", LIEF::assembly::powerpc::OPCODE::XVCMPGESP) + .value("XVCMPGESP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPGESP_rec) + .value("XVCMPGTDP", LIEF::assembly::powerpc::OPCODE::XVCMPGTDP) + .value("XVCMPGTDP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPGTDP_rec) + .value("XVCMPGTSP", LIEF::assembly::powerpc::OPCODE::XVCMPGTSP) + .value("XVCMPGTSP_rec", LIEF::assembly::powerpc::OPCODE::XVCMPGTSP_rec) + .value("XVCPSGNDP", LIEF::assembly::powerpc::OPCODE::XVCPSGNDP) + .value("XVCPSGNSP", LIEF::assembly::powerpc::OPCODE::XVCPSGNSP) + .value("XVCVBF16SPN", LIEF::assembly::powerpc::OPCODE::XVCVBF16SPN) + .value("XVCVDPSP", LIEF::assembly::powerpc::OPCODE::XVCVDPSP) + .value("XVCVDPSXDS", LIEF::assembly::powerpc::OPCODE::XVCVDPSXDS) + .value("XVCVDPSXWS", LIEF::assembly::powerpc::OPCODE::XVCVDPSXWS) + .value("XVCVDPUXDS", LIEF::assembly::powerpc::OPCODE::XVCVDPUXDS) + .value("XVCVDPUXWS", LIEF::assembly::powerpc::OPCODE::XVCVDPUXWS) + .value("XVCVHPSP", LIEF::assembly::powerpc::OPCODE::XVCVHPSP) + .value("XVCVSPBF16", LIEF::assembly::powerpc::OPCODE::XVCVSPBF16) + .value("XVCVSPDP", LIEF::assembly::powerpc::OPCODE::XVCVSPDP) + .value("XVCVSPHP", LIEF::assembly::powerpc::OPCODE::XVCVSPHP) + .value("XVCVSPSXDS", LIEF::assembly::powerpc::OPCODE::XVCVSPSXDS) + .value("XVCVSPSXWS", LIEF::assembly::powerpc::OPCODE::XVCVSPSXWS) + .value("XVCVSPUXDS", LIEF::assembly::powerpc::OPCODE::XVCVSPUXDS) + .value("XVCVSPUXWS", LIEF::assembly::powerpc::OPCODE::XVCVSPUXWS) + .value("XVCVSXDDP", LIEF::assembly::powerpc::OPCODE::XVCVSXDDP) + .value("XVCVSXDSP", LIEF::assembly::powerpc::OPCODE::XVCVSXDSP) + .value("XVCVSXWDP", LIEF::assembly::powerpc::OPCODE::XVCVSXWDP) + .value("XVCVSXWSP", LIEF::assembly::powerpc::OPCODE::XVCVSXWSP) + .value("XVCVUXDDP", LIEF::assembly::powerpc::OPCODE::XVCVUXDDP) + .value("XVCVUXDSP", LIEF::assembly::powerpc::OPCODE::XVCVUXDSP) + .value("XVCVUXWDP", LIEF::assembly::powerpc::OPCODE::XVCVUXWDP) + .value("XVCVUXWSP", LIEF::assembly::powerpc::OPCODE::XVCVUXWSP) + .value("XVDIVDP", LIEF::assembly::powerpc::OPCODE::XVDIVDP) + .value("XVDIVSP", LIEF::assembly::powerpc::OPCODE::XVDIVSP) + .value("XVF16GER2", LIEF::assembly::powerpc::OPCODE::XVF16GER2) + .value("XVF16GER2NN", LIEF::assembly::powerpc::OPCODE::XVF16GER2NN) + .value("XVF16GER2NP", LIEF::assembly::powerpc::OPCODE::XVF16GER2NP) + .value("XVF16GER2PN", LIEF::assembly::powerpc::OPCODE::XVF16GER2PN) + .value("XVF16GER2PP", LIEF::assembly::powerpc::OPCODE::XVF16GER2PP) + .value("XVF16GER2W", LIEF::assembly::powerpc::OPCODE::XVF16GER2W) + .value("XVF16GER2WNN", LIEF::assembly::powerpc::OPCODE::XVF16GER2WNN) + .value("XVF16GER2WNP", LIEF::assembly::powerpc::OPCODE::XVF16GER2WNP) + .value("XVF16GER2WPN", LIEF::assembly::powerpc::OPCODE::XVF16GER2WPN) + .value("XVF16GER2WPP", LIEF::assembly::powerpc::OPCODE::XVF16GER2WPP) + .value("XVF32GER", LIEF::assembly::powerpc::OPCODE::XVF32GER) + .value("XVF32GERNN", LIEF::assembly::powerpc::OPCODE::XVF32GERNN) + .value("XVF32GERNP", LIEF::assembly::powerpc::OPCODE::XVF32GERNP) + .value("XVF32GERPN", LIEF::assembly::powerpc::OPCODE::XVF32GERPN) + .value("XVF32GERPP", LIEF::assembly::powerpc::OPCODE::XVF32GERPP) + .value("XVF32GERW", LIEF::assembly::powerpc::OPCODE::XVF32GERW) + .value("XVF32GERWNN", LIEF::assembly::powerpc::OPCODE::XVF32GERWNN) + .value("XVF32GERWNP", LIEF::assembly::powerpc::OPCODE::XVF32GERWNP) + .value("XVF32GERWPN", LIEF::assembly::powerpc::OPCODE::XVF32GERWPN) + .value("XVF32GERWPP", LIEF::assembly::powerpc::OPCODE::XVF32GERWPP) + .value("XVF64GER", LIEF::assembly::powerpc::OPCODE::XVF64GER) + .value("XVF64GERNN", LIEF::assembly::powerpc::OPCODE::XVF64GERNN) + .value("XVF64GERNP", LIEF::assembly::powerpc::OPCODE::XVF64GERNP) + .value("XVF64GERPN", LIEF::assembly::powerpc::OPCODE::XVF64GERPN) + .value("XVF64GERPP", LIEF::assembly::powerpc::OPCODE::XVF64GERPP) + .value("XVF64GERW", LIEF::assembly::powerpc::OPCODE::XVF64GERW) + .value("XVF64GERWNN", LIEF::assembly::powerpc::OPCODE::XVF64GERWNN) + .value("XVF64GERWNP", LIEF::assembly::powerpc::OPCODE::XVF64GERWNP) + .value("XVF64GERWPN", LIEF::assembly::powerpc::OPCODE::XVF64GERWPN) + .value("XVF64GERWPP", LIEF::assembly::powerpc::OPCODE::XVF64GERWPP) + .value("XVI16GER2", LIEF::assembly::powerpc::OPCODE::XVI16GER2) + .value("XVI16GER2PP", LIEF::assembly::powerpc::OPCODE::XVI16GER2PP) + .value("XVI16GER2S", LIEF::assembly::powerpc::OPCODE::XVI16GER2S) + .value("XVI16GER2SPP", LIEF::assembly::powerpc::OPCODE::XVI16GER2SPP) + .value("XVI16GER2SW", LIEF::assembly::powerpc::OPCODE::XVI16GER2SW) + .value("XVI16GER2SWPP", LIEF::assembly::powerpc::OPCODE::XVI16GER2SWPP) + .value("XVI16GER2W", LIEF::assembly::powerpc::OPCODE::XVI16GER2W) + .value("XVI16GER2WPP", LIEF::assembly::powerpc::OPCODE::XVI16GER2WPP) + .value("XVI4GER8", LIEF::assembly::powerpc::OPCODE::XVI4GER8) + .value("XVI4GER8PP", LIEF::assembly::powerpc::OPCODE::XVI4GER8PP) + .value("XVI4GER8W", LIEF::assembly::powerpc::OPCODE::XVI4GER8W) + .value("XVI4GER8WPP", LIEF::assembly::powerpc::OPCODE::XVI4GER8WPP) + .value("XVI8GER4", LIEF::assembly::powerpc::OPCODE::XVI8GER4) + .value("XVI8GER4PP", LIEF::assembly::powerpc::OPCODE::XVI8GER4PP) + .value("XVI8GER4SPP", LIEF::assembly::powerpc::OPCODE::XVI8GER4SPP) + .value("XVI8GER4W", LIEF::assembly::powerpc::OPCODE::XVI8GER4W) + .value("XVI8GER4WPP", LIEF::assembly::powerpc::OPCODE::XVI8GER4WPP) + .value("XVI8GER4WSPP", LIEF::assembly::powerpc::OPCODE::XVI8GER4WSPP) + .value("XVIEXPDP", LIEF::assembly::powerpc::OPCODE::XVIEXPDP) + .value("XVIEXPSP", LIEF::assembly::powerpc::OPCODE::XVIEXPSP) + .value("XVMADDADP", LIEF::assembly::powerpc::OPCODE::XVMADDADP) + .value("XVMADDASP", LIEF::assembly::powerpc::OPCODE::XVMADDASP) + .value("XVMADDMDP", LIEF::assembly::powerpc::OPCODE::XVMADDMDP) + .value("XVMADDMSP", LIEF::assembly::powerpc::OPCODE::XVMADDMSP) + .value("XVMAXDP", LIEF::assembly::powerpc::OPCODE::XVMAXDP) + .value("XVMAXSP", LIEF::assembly::powerpc::OPCODE::XVMAXSP) + .value("XVMINDP", LIEF::assembly::powerpc::OPCODE::XVMINDP) + .value("XVMINSP", LIEF::assembly::powerpc::OPCODE::XVMINSP) + .value("XVMSUBADP", LIEF::assembly::powerpc::OPCODE::XVMSUBADP) + .value("XVMSUBASP", LIEF::assembly::powerpc::OPCODE::XVMSUBASP) + .value("XVMSUBMDP", LIEF::assembly::powerpc::OPCODE::XVMSUBMDP) + .value("XVMSUBMSP", LIEF::assembly::powerpc::OPCODE::XVMSUBMSP) + .value("XVMULDP", LIEF::assembly::powerpc::OPCODE::XVMULDP) + .value("XVMULHSH", LIEF::assembly::powerpc::OPCODE::XVMULHSH) + .value("XVMULHSW", LIEF::assembly::powerpc::OPCODE::XVMULHSW) + .value("XVMULHUH", LIEF::assembly::powerpc::OPCODE::XVMULHUH) + .value("XVMULHUW", LIEF::assembly::powerpc::OPCODE::XVMULHUW) + .value("XVMULSP", LIEF::assembly::powerpc::OPCODE::XVMULSP) + .value("XVMULUHM", LIEF::assembly::powerpc::OPCODE::XVMULUHM) + .value("XVMULUWM", LIEF::assembly::powerpc::OPCODE::XVMULUWM) + .value("XVNABSDP", LIEF::assembly::powerpc::OPCODE::XVNABSDP) + .value("XVNABSSP", LIEF::assembly::powerpc::OPCODE::XVNABSSP) + .value("XVNEGDP", LIEF::assembly::powerpc::OPCODE::XVNEGDP) + .value("XVNEGSP", LIEF::assembly::powerpc::OPCODE::XVNEGSP) + .value("XVNMADDADP", LIEF::assembly::powerpc::OPCODE::XVNMADDADP) + .value("XVNMADDASP", LIEF::assembly::powerpc::OPCODE::XVNMADDASP) + .value("XVNMADDMDP", LIEF::assembly::powerpc::OPCODE::XVNMADDMDP) + .value("XVNMADDMSP", LIEF::assembly::powerpc::OPCODE::XVNMADDMSP) + .value("XVNMSUBADP", LIEF::assembly::powerpc::OPCODE::XVNMSUBADP) + .value("XVNMSUBASP", LIEF::assembly::powerpc::OPCODE::XVNMSUBASP) + .value("XVNMSUBMDP", LIEF::assembly::powerpc::OPCODE::XVNMSUBMDP) + .value("XVNMSUBMSP", LIEF::assembly::powerpc::OPCODE::XVNMSUBMSP) + .value("XVRDPI", LIEF::assembly::powerpc::OPCODE::XVRDPI) + .value("XVRDPIC", LIEF::assembly::powerpc::OPCODE::XVRDPIC) + .value("XVRDPIM", LIEF::assembly::powerpc::OPCODE::XVRDPIM) + .value("XVRDPIP", LIEF::assembly::powerpc::OPCODE::XVRDPIP) + .value("XVRDPIZ", LIEF::assembly::powerpc::OPCODE::XVRDPIZ) + .value("XVREDP", LIEF::assembly::powerpc::OPCODE::XVREDP) + .value("XVRESP", LIEF::assembly::powerpc::OPCODE::XVRESP) + .value("XVRLW", LIEF::assembly::powerpc::OPCODE::XVRLW) + .value("XVRSPI", LIEF::assembly::powerpc::OPCODE::XVRSPI) + .value("XVRSPIC", LIEF::assembly::powerpc::OPCODE::XVRSPIC) + .value("XVRSPIM", LIEF::assembly::powerpc::OPCODE::XVRSPIM) + .value("XVRSPIP", LIEF::assembly::powerpc::OPCODE::XVRSPIP) + .value("XVRSPIZ", LIEF::assembly::powerpc::OPCODE::XVRSPIZ) + .value("XVRSQRTEDP", LIEF::assembly::powerpc::OPCODE::XVRSQRTEDP) + .value("XVRSQRTESP", LIEF::assembly::powerpc::OPCODE::XVRSQRTESP) + .value("XVSQRTDP", LIEF::assembly::powerpc::OPCODE::XVSQRTDP) + .value("XVSQRTSP", LIEF::assembly::powerpc::OPCODE::XVSQRTSP) + .value("XVSUBDP", LIEF::assembly::powerpc::OPCODE::XVSUBDP) + .value("XVSUBSP", LIEF::assembly::powerpc::OPCODE::XVSUBSP) + .value("XVSUBUHM", LIEF::assembly::powerpc::OPCODE::XVSUBUHM) + .value("XVSUBUWM", LIEF::assembly::powerpc::OPCODE::XVSUBUWM) + .value("XVTDIVDP", LIEF::assembly::powerpc::OPCODE::XVTDIVDP) + .value("XVTDIVSP", LIEF::assembly::powerpc::OPCODE::XVTDIVSP) + .value("XVTLSBB", LIEF::assembly::powerpc::OPCODE::XVTLSBB) + .value("XVTSQRTDP", LIEF::assembly::powerpc::OPCODE::XVTSQRTDP) + .value("XVTSQRTSP", LIEF::assembly::powerpc::OPCODE::XVTSQRTSP) + .value("XVTSTDCDP", LIEF::assembly::powerpc::OPCODE::XVTSTDCDP) + .value("XVTSTDCSP", LIEF::assembly::powerpc::OPCODE::XVTSTDCSP) + .value("XVXEXPDP", LIEF::assembly::powerpc::OPCODE::XVXEXPDP) + .value("XVXEXPSP", LIEF::assembly::powerpc::OPCODE::XVXEXPSP) + .value("XVXSIGDP", LIEF::assembly::powerpc::OPCODE::XVXSIGDP) + .value("XVXSIGSP", LIEF::assembly::powerpc::OPCODE::XVXSIGSP) + .value("XXAESDECP", LIEF::assembly::powerpc::OPCODE::XXAESDECP) + .value("XXAESENCP", LIEF::assembly::powerpc::OPCODE::XXAESENCP) + .value("XXAESGENLKP", LIEF::assembly::powerpc::OPCODE::XXAESGENLKP) + .value("XXBLENDVB", LIEF::assembly::powerpc::OPCODE::XXBLENDVB) + .value("XXBLENDVD", LIEF::assembly::powerpc::OPCODE::XXBLENDVD) + .value("XXBLENDVH", LIEF::assembly::powerpc::OPCODE::XXBLENDVH) + .value("XXBLENDVW", LIEF::assembly::powerpc::OPCODE::XXBLENDVW) + .value("XXBRD", LIEF::assembly::powerpc::OPCODE::XXBRD) + .value("XXBRH", LIEF::assembly::powerpc::OPCODE::XXBRH) + .value("XXBRQ", LIEF::assembly::powerpc::OPCODE::XXBRQ) + .value("XXBRW", LIEF::assembly::powerpc::OPCODE::XXBRW) + .value("XXEVAL", LIEF::assembly::powerpc::OPCODE::XXEVAL) + .value("XXEXTRACTUW", LIEF::assembly::powerpc::OPCODE::XXEXTRACTUW) + .value("XXGENPCVBM", LIEF::assembly::powerpc::OPCODE::XXGENPCVBM) + .value("XXGENPCVDM", LIEF::assembly::powerpc::OPCODE::XXGENPCVDM) + .value("XXGENPCVHM", LIEF::assembly::powerpc::OPCODE::XXGENPCVHM) + .value("XXGENPCVWM", LIEF::assembly::powerpc::OPCODE::XXGENPCVWM) + .value("XXGFMUL128", LIEF::assembly::powerpc::OPCODE::XXGFMUL128) + .value("XXINSERTW", LIEF::assembly::powerpc::OPCODE::XXINSERTW) + .value("XXLAND", LIEF::assembly::powerpc::OPCODE::XXLAND) + .value("XXLANDC", LIEF::assembly::powerpc::OPCODE::XXLANDC) + .value("XXLEQV", LIEF::assembly::powerpc::OPCODE::XXLEQV) + .value("XXLEQVOnes", LIEF::assembly::powerpc::OPCODE::XXLEQVOnes) + .value("XXLNAND", LIEF::assembly::powerpc::OPCODE::XXLNAND) + .value("XXLNOR", LIEF::assembly::powerpc::OPCODE::XXLNOR) + .value("XXLOR", LIEF::assembly::powerpc::OPCODE::XXLOR) + .value("XXLORC", LIEF::assembly::powerpc::OPCODE::XXLORC) + .value("XXLORf", LIEF::assembly::powerpc::OPCODE::XXLORf) + .value("XXLXOR", LIEF::assembly::powerpc::OPCODE::XXLXOR) + .value("XXLXORdpz", LIEF::assembly::powerpc::OPCODE::XXLXORdpz) + .value("XXLXORspz", LIEF::assembly::powerpc::OPCODE::XXLXORspz) + .value("XXLXORz", LIEF::assembly::powerpc::OPCODE::XXLXORz) + .value("XXMFACC", LIEF::assembly::powerpc::OPCODE::XXMFACC) + .value("XXMFACCW", LIEF::assembly::powerpc::OPCODE::XXMFACCW) + .value("XXMRGHW", LIEF::assembly::powerpc::OPCODE::XXMRGHW) + .value("XXMRGLW", LIEF::assembly::powerpc::OPCODE::XXMRGLW) + .value("XXMTACC", LIEF::assembly::powerpc::OPCODE::XXMTACC) + .value("XXMTACCW", LIEF::assembly::powerpc::OPCODE::XXMTACCW) + .value("XXMULMUL", LIEF::assembly::powerpc::OPCODE::XXMULMUL) + .value("XXMULMULHIADD", LIEF::assembly::powerpc::OPCODE::XXMULMULHIADD) + .value("XXMULMULLOADD", LIEF::assembly::powerpc::OPCODE::XXMULMULLOADD) + .value("XXPERM", LIEF::assembly::powerpc::OPCODE::XXPERM) + .value("XXPERMDI", LIEF::assembly::powerpc::OPCODE::XXPERMDI) + .value("XXPERMDIs", LIEF::assembly::powerpc::OPCODE::XXPERMDIs) + .value("XXPERMR", LIEF::assembly::powerpc::OPCODE::XXPERMR) + .value("XXPERMX", LIEF::assembly::powerpc::OPCODE::XXPERMX) + .value("XXSEL", LIEF::assembly::powerpc::OPCODE::XXSEL) + .value("XXSETACCZ", LIEF::assembly::powerpc::OPCODE::XXSETACCZ) + .value("XXSLDWI", LIEF::assembly::powerpc::OPCODE::XXSLDWI) + .value("XXSLDWIs", LIEF::assembly::powerpc::OPCODE::XXSLDWIs) + .value("XXSPLTI32DX", LIEF::assembly::powerpc::OPCODE::XXSPLTI32DX) + .value("XXSPLTIB", LIEF::assembly::powerpc::OPCODE::XXSPLTIB) + .value("XXSPLTIDP", LIEF::assembly::powerpc::OPCODE::XXSPLTIDP) + .value("XXSPLTIW", LIEF::assembly::powerpc::OPCODE::XXSPLTIW) + .value("XXSPLTW", LIEF::assembly::powerpc::OPCODE::XXSPLTW) + .value("XXSPLTWs", LIEF::assembly::powerpc::OPCODE::XXSPLTWs) + .value("XXSSUMUDM", LIEF::assembly::powerpc::OPCODE::XXSSUMUDM) + .value("XXSSUMUDMC", LIEF::assembly::powerpc::OPCODE::XXSSUMUDMC) + .value("XXSSUMUDMCEXT", LIEF::assembly::powerpc::OPCODE::XXSSUMUDMCEXT) + .value("gBC", LIEF::assembly::powerpc::OPCODE::gBC) + .value("gBCA", LIEF::assembly::powerpc::OPCODE::gBCA) + .value("gBCAat", LIEF::assembly::powerpc::OPCODE::gBCAat) + .value("gBCCTR", LIEF::assembly::powerpc::OPCODE::gBCCTR) + .value("gBCCTRL", LIEF::assembly::powerpc::OPCODE::gBCCTRL) + .value("gBCL", LIEF::assembly::powerpc::OPCODE::gBCL) + .value("gBCLA", LIEF::assembly::powerpc::OPCODE::gBCLA) + .value("gBCLAat", LIEF::assembly::powerpc::OPCODE::gBCLAat) + .value("gBCLR", LIEF::assembly::powerpc::OPCODE::gBCLR) + .value("gBCLRL", LIEF::assembly::powerpc::OPCODE::gBCLRL) + .value("gBCLat", LIEF::assembly::powerpc::OPCODE::gBCLat) + .value("gBCat", LIEF::assembly::powerpc::OPCODE::gBCat) + .value("INSTRUCTION_LIST_END", LIEF::assembly::powerpc::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/pyOperand.cpp b/vendor/lief/api/python/src/asm/powerpc/pyOperand.cpp new file mode 100644 index 0000000..74cdbb1 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/powerpc/Operand.hpp" + +#include "asm/powerpc/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::powerpc::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for a PowerPC instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(powerpc::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/powerpc/pyRegister.cpp b/vendor/lief/api/python/src/asm/powerpc/pyRegister.cpp new file mode 100644 index 0000000..c67bca5 --- /dev/null +++ b/vendor/lief/api/python/src/asm/powerpc/pyRegister.cpp @@ -0,0 +1,624 @@ +#include "asm/powerpc/init.hpp" + +#include "LIEF/asm/powerpc/registers.hpp" + +namespace LIEF::assembly::powerpc::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::powerpc::REG::NoRegister) + .value("BP", LIEF::assembly::powerpc::REG::BP) + .value("CARRY", LIEF::assembly::powerpc::REG::CARRY) + .value("CTR", LIEF::assembly::powerpc::REG::CTR) + .value("FP", LIEF::assembly::powerpc::REG::FP) + .value("LR", LIEF::assembly::powerpc::REG::LR) + .value("RM", LIEF::assembly::powerpc::REG::RM) + .value("SPEFSCR", LIEF::assembly::powerpc::REG::SPEFSCR) + .value("VRSAVE", LIEF::assembly::powerpc::REG::VRSAVE) + .value("XER", LIEF::assembly::powerpc::REG::XER) + .value("ZERO", LIEF::assembly::powerpc::REG::ZERO) + .value("ACC0", LIEF::assembly::powerpc::REG::ACC0) + .value("ACC1", LIEF::assembly::powerpc::REG::ACC1) + .value("ACC2", LIEF::assembly::powerpc::REG::ACC2) + .value("ACC3", LIEF::assembly::powerpc::REG::ACC3) + .value("ACC4", LIEF::assembly::powerpc::REG::ACC4) + .value("ACC5", LIEF::assembly::powerpc::REG::ACC5) + .value("ACC6", LIEF::assembly::powerpc::REG::ACC6) + .value("ACC7", LIEF::assembly::powerpc::REG::ACC7) + .value("BP8", LIEF::assembly::powerpc::REG::BP8) + .value("CR0", LIEF::assembly::powerpc::REG::CR0) + .value("CR1", LIEF::assembly::powerpc::REG::CR1) + .value("CR2", LIEF::assembly::powerpc::REG::CR2) + .value("CR3", LIEF::assembly::powerpc::REG::CR3) + .value("CR4", LIEF::assembly::powerpc::REG::CR4) + .value("CR5", LIEF::assembly::powerpc::REG::CR5) + .value("CR6", LIEF::assembly::powerpc::REG::CR6) + .value("CR7", LIEF::assembly::powerpc::REG::CR7) + .value("CTR8", LIEF::assembly::powerpc::REG::CTR8) + .value("DMR0", LIEF::assembly::powerpc::REG::DMR0) + .value("DMR1", LIEF::assembly::powerpc::REG::DMR1) + .value("DMR2", LIEF::assembly::powerpc::REG::DMR2) + .value("DMR3", LIEF::assembly::powerpc::REG::DMR3) + .value("DMR4", LIEF::assembly::powerpc::REG::DMR4) + .value("DMR5", LIEF::assembly::powerpc::REG::DMR5) + .value("DMR6", LIEF::assembly::powerpc::REG::DMR6) + .value("DMR7", LIEF::assembly::powerpc::REG::DMR7) + .value("DMRROW0", LIEF::assembly::powerpc::REG::DMRROW0) + .value("DMRROW1", LIEF::assembly::powerpc::REG::DMRROW1) + .value("DMRROW2", LIEF::assembly::powerpc::REG::DMRROW2) + .value("DMRROW3", LIEF::assembly::powerpc::REG::DMRROW3) + .value("DMRROW4", LIEF::assembly::powerpc::REG::DMRROW4) + .value("DMRROW5", LIEF::assembly::powerpc::REG::DMRROW5) + .value("DMRROW6", LIEF::assembly::powerpc::REG::DMRROW6) + .value("DMRROW7", LIEF::assembly::powerpc::REG::DMRROW7) + .value("DMRROW8", LIEF::assembly::powerpc::REG::DMRROW8) + .value("DMRROW9", LIEF::assembly::powerpc::REG::DMRROW9) + .value("DMRROW10", LIEF::assembly::powerpc::REG::DMRROW10) + .value("DMRROW11", LIEF::assembly::powerpc::REG::DMRROW11) + .value("DMRROW12", LIEF::assembly::powerpc::REG::DMRROW12) + .value("DMRROW13", LIEF::assembly::powerpc::REG::DMRROW13) + .value("DMRROW14", LIEF::assembly::powerpc::REG::DMRROW14) + .value("DMRROW15", LIEF::assembly::powerpc::REG::DMRROW15) + .value("DMRROW16", LIEF::assembly::powerpc::REG::DMRROW16) + .value("DMRROW17", LIEF::assembly::powerpc::REG::DMRROW17) + .value("DMRROW18", LIEF::assembly::powerpc::REG::DMRROW18) + .value("DMRROW19", LIEF::assembly::powerpc::REG::DMRROW19) + .value("DMRROW20", LIEF::assembly::powerpc::REG::DMRROW20) + .value("DMRROW21", LIEF::assembly::powerpc::REG::DMRROW21) + .value("DMRROW22", LIEF::assembly::powerpc::REG::DMRROW22) + .value("DMRROW23", LIEF::assembly::powerpc::REG::DMRROW23) + .value("DMRROW24", LIEF::assembly::powerpc::REG::DMRROW24) + .value("DMRROW25", LIEF::assembly::powerpc::REG::DMRROW25) + .value("DMRROW26", LIEF::assembly::powerpc::REG::DMRROW26) + .value("DMRROW27", LIEF::assembly::powerpc::REG::DMRROW27) + .value("DMRROW28", LIEF::assembly::powerpc::REG::DMRROW28) + .value("DMRROW29", LIEF::assembly::powerpc::REG::DMRROW29) + .value("DMRROW30", LIEF::assembly::powerpc::REG::DMRROW30) + .value("DMRROW31", LIEF::assembly::powerpc::REG::DMRROW31) + .value("DMRROW32", LIEF::assembly::powerpc::REG::DMRROW32) + .value("DMRROW33", LIEF::assembly::powerpc::REG::DMRROW33) + .value("DMRROW34", LIEF::assembly::powerpc::REG::DMRROW34) + .value("DMRROW35", LIEF::assembly::powerpc::REG::DMRROW35) + .value("DMRROW36", LIEF::assembly::powerpc::REG::DMRROW36) + .value("DMRROW37", LIEF::assembly::powerpc::REG::DMRROW37) + .value("DMRROW38", LIEF::assembly::powerpc::REG::DMRROW38) + .value("DMRROW39", LIEF::assembly::powerpc::REG::DMRROW39) + .value("DMRROW40", LIEF::assembly::powerpc::REG::DMRROW40) + .value("DMRROW41", LIEF::assembly::powerpc::REG::DMRROW41) + .value("DMRROW42", LIEF::assembly::powerpc::REG::DMRROW42) + .value("DMRROW43", LIEF::assembly::powerpc::REG::DMRROW43) + .value("DMRROW44", LIEF::assembly::powerpc::REG::DMRROW44) + .value("DMRROW45", LIEF::assembly::powerpc::REG::DMRROW45) + .value("DMRROW46", LIEF::assembly::powerpc::REG::DMRROW46) + .value("DMRROW47", LIEF::assembly::powerpc::REG::DMRROW47) + .value("DMRROW48", LIEF::assembly::powerpc::REG::DMRROW48) + .value("DMRROW49", LIEF::assembly::powerpc::REG::DMRROW49) + .value("DMRROW50", LIEF::assembly::powerpc::REG::DMRROW50) + .value("DMRROW51", LIEF::assembly::powerpc::REG::DMRROW51) + .value("DMRROW52", LIEF::assembly::powerpc::REG::DMRROW52) + .value("DMRROW53", LIEF::assembly::powerpc::REG::DMRROW53) + .value("DMRROW54", LIEF::assembly::powerpc::REG::DMRROW54) + .value("DMRROW55", LIEF::assembly::powerpc::REG::DMRROW55) + .value("DMRROW56", LIEF::assembly::powerpc::REG::DMRROW56) + .value("DMRROW57", LIEF::assembly::powerpc::REG::DMRROW57) + .value("DMRROW58", LIEF::assembly::powerpc::REG::DMRROW58) + .value("DMRROW59", LIEF::assembly::powerpc::REG::DMRROW59) + .value("DMRROW60", LIEF::assembly::powerpc::REG::DMRROW60) + .value("DMRROW61", LIEF::assembly::powerpc::REG::DMRROW61) + .value("DMRROW62", LIEF::assembly::powerpc::REG::DMRROW62) + .value("DMRROW63", LIEF::assembly::powerpc::REG::DMRROW63) + .value("DMRROWp0", LIEF::assembly::powerpc::REG::DMRROWp0) + .value("DMRROWp1", LIEF::assembly::powerpc::REG::DMRROWp1) + .value("DMRROWp2", LIEF::assembly::powerpc::REG::DMRROWp2) + .value("DMRROWp3", LIEF::assembly::powerpc::REG::DMRROWp3) + .value("DMRROWp4", LIEF::assembly::powerpc::REG::DMRROWp4) + .value("DMRROWp5", LIEF::assembly::powerpc::REG::DMRROWp5) + .value("DMRROWp6", LIEF::assembly::powerpc::REG::DMRROWp6) + .value("DMRROWp7", LIEF::assembly::powerpc::REG::DMRROWp7) + .value("DMRROWp8", LIEF::assembly::powerpc::REG::DMRROWp8) + .value("DMRROWp9", LIEF::assembly::powerpc::REG::DMRROWp9) + .value("DMRROWp10", LIEF::assembly::powerpc::REG::DMRROWp10) + .value("DMRROWp11", LIEF::assembly::powerpc::REG::DMRROWp11) + .value("DMRROWp12", LIEF::assembly::powerpc::REG::DMRROWp12) + .value("DMRROWp13", LIEF::assembly::powerpc::REG::DMRROWp13) + .value("DMRROWp14", LIEF::assembly::powerpc::REG::DMRROWp14) + .value("DMRROWp15", LIEF::assembly::powerpc::REG::DMRROWp15) + .value("DMRROWp16", LIEF::assembly::powerpc::REG::DMRROWp16) + .value("DMRROWp17", LIEF::assembly::powerpc::REG::DMRROWp17) + .value("DMRROWp18", LIEF::assembly::powerpc::REG::DMRROWp18) + .value("DMRROWp19", LIEF::assembly::powerpc::REG::DMRROWp19) + .value("DMRROWp20", LIEF::assembly::powerpc::REG::DMRROWp20) + .value("DMRROWp21", LIEF::assembly::powerpc::REG::DMRROWp21) + .value("DMRROWp22", LIEF::assembly::powerpc::REG::DMRROWp22) + .value("DMRROWp23", LIEF::assembly::powerpc::REG::DMRROWp23) + .value("DMRROWp24", LIEF::assembly::powerpc::REG::DMRROWp24) + .value("DMRROWp25", LIEF::assembly::powerpc::REG::DMRROWp25) + .value("DMRROWp26", LIEF::assembly::powerpc::REG::DMRROWp26) + .value("DMRROWp27", LIEF::assembly::powerpc::REG::DMRROWp27) + .value("DMRROWp28", LIEF::assembly::powerpc::REG::DMRROWp28) + .value("DMRROWp29", LIEF::assembly::powerpc::REG::DMRROWp29) + .value("DMRROWp30", LIEF::assembly::powerpc::REG::DMRROWp30) + .value("DMRROWp31", LIEF::assembly::powerpc::REG::DMRROWp31) + .value("DMRp0", LIEF::assembly::powerpc::REG::DMRp0) + .value("DMRp1", LIEF::assembly::powerpc::REG::DMRp1) + .value("DMRp2", LIEF::assembly::powerpc::REG::DMRp2) + .value("DMRp3", LIEF::assembly::powerpc::REG::DMRp3) + .value("F0", LIEF::assembly::powerpc::REG::F0) + .value("F1", LIEF::assembly::powerpc::REG::F1) + .value("F2", LIEF::assembly::powerpc::REG::F2) + .value("F3", LIEF::assembly::powerpc::REG::F3) + .value("F4", LIEF::assembly::powerpc::REG::F4) + .value("F5", LIEF::assembly::powerpc::REG::F5) + .value("F6", LIEF::assembly::powerpc::REG::F6) + .value("F7", LIEF::assembly::powerpc::REG::F7) + .value("F8", LIEF::assembly::powerpc::REG::F8) + .value("F9", LIEF::assembly::powerpc::REG::F9) + .value("F10", LIEF::assembly::powerpc::REG::F10) + .value("F11", LIEF::assembly::powerpc::REG::F11) + .value("F12", LIEF::assembly::powerpc::REG::F12) + .value("F13", LIEF::assembly::powerpc::REG::F13) + .value("F14", LIEF::assembly::powerpc::REG::F14) + .value("F15", LIEF::assembly::powerpc::REG::F15) + .value("F16", LIEF::assembly::powerpc::REG::F16) + .value("F17", LIEF::assembly::powerpc::REG::F17) + .value("F18", LIEF::assembly::powerpc::REG::F18) + .value("F19", LIEF::assembly::powerpc::REG::F19) + .value("F20", LIEF::assembly::powerpc::REG::F20) + .value("F21", LIEF::assembly::powerpc::REG::F21) + .value("F22", LIEF::assembly::powerpc::REG::F22) + .value("F23", LIEF::assembly::powerpc::REG::F23) + .value("F24", LIEF::assembly::powerpc::REG::F24) + .value("F25", LIEF::assembly::powerpc::REG::F25) + .value("F26", LIEF::assembly::powerpc::REG::F26) + .value("F27", LIEF::assembly::powerpc::REG::F27) + .value("F28", LIEF::assembly::powerpc::REG::F28) + .value("F29", LIEF::assembly::powerpc::REG::F29) + .value("F30", LIEF::assembly::powerpc::REG::F30) + .value("F31", LIEF::assembly::powerpc::REG::F31) + .value("FH0", LIEF::assembly::powerpc::REG::FH0) + .value("FH1", LIEF::assembly::powerpc::REG::FH1) + .value("FH2", LIEF::assembly::powerpc::REG::FH2) + .value("FH3", LIEF::assembly::powerpc::REG::FH3) + .value("FH4", LIEF::assembly::powerpc::REG::FH4) + .value("FH5", LIEF::assembly::powerpc::REG::FH5) + .value("FH6", LIEF::assembly::powerpc::REG::FH6) + .value("FH7", LIEF::assembly::powerpc::REG::FH7) + .value("FH8", LIEF::assembly::powerpc::REG::FH8) + .value("FH9", LIEF::assembly::powerpc::REG::FH9) + .value("FH10", LIEF::assembly::powerpc::REG::FH10) + .value("FH11", LIEF::assembly::powerpc::REG::FH11) + .value("FH12", LIEF::assembly::powerpc::REG::FH12) + .value("FH13", LIEF::assembly::powerpc::REG::FH13) + .value("FH14", LIEF::assembly::powerpc::REG::FH14) + .value("FH15", LIEF::assembly::powerpc::REG::FH15) + .value("FH16", LIEF::assembly::powerpc::REG::FH16) + .value("FH17", LIEF::assembly::powerpc::REG::FH17) + .value("FH18", LIEF::assembly::powerpc::REG::FH18) + .value("FH19", LIEF::assembly::powerpc::REG::FH19) + .value("FH20", LIEF::assembly::powerpc::REG::FH20) + .value("FH21", LIEF::assembly::powerpc::REG::FH21) + .value("FH22", LIEF::assembly::powerpc::REG::FH22) + .value("FH23", LIEF::assembly::powerpc::REG::FH23) + .value("FH24", LIEF::assembly::powerpc::REG::FH24) + .value("FH25", LIEF::assembly::powerpc::REG::FH25) + .value("FH26", LIEF::assembly::powerpc::REG::FH26) + .value("FH27", LIEF::assembly::powerpc::REG::FH27) + .value("FH28", LIEF::assembly::powerpc::REG::FH28) + .value("FH29", LIEF::assembly::powerpc::REG::FH29) + .value("FH30", LIEF::assembly::powerpc::REG::FH30) + .value("FH31", LIEF::assembly::powerpc::REG::FH31) + .value("FP8", LIEF::assembly::powerpc::REG::FP8) + .value("Fpair0", LIEF::assembly::powerpc::REG::Fpair0) + .value("Fpair2", LIEF::assembly::powerpc::REG::Fpair2) + .value("Fpair4", LIEF::assembly::powerpc::REG::Fpair4) + .value("Fpair6", LIEF::assembly::powerpc::REG::Fpair6) + .value("Fpair8", LIEF::assembly::powerpc::REG::Fpair8) + .value("Fpair10", LIEF::assembly::powerpc::REG::Fpair10) + .value("Fpair12", LIEF::assembly::powerpc::REG::Fpair12) + .value("Fpair14", LIEF::assembly::powerpc::REG::Fpair14) + .value("Fpair16", LIEF::assembly::powerpc::REG::Fpair16) + .value("Fpair18", LIEF::assembly::powerpc::REG::Fpair18) + .value("Fpair20", LIEF::assembly::powerpc::REG::Fpair20) + .value("Fpair22", LIEF::assembly::powerpc::REG::Fpair22) + .value("Fpair24", LIEF::assembly::powerpc::REG::Fpair24) + .value("Fpair26", LIEF::assembly::powerpc::REG::Fpair26) + .value("Fpair28", LIEF::assembly::powerpc::REG::Fpair28) + .value("Fpair30", LIEF::assembly::powerpc::REG::Fpair30) + .value("H0", LIEF::assembly::powerpc::REG::H0) + .value("H1", LIEF::assembly::powerpc::REG::H1) + .value("H2", LIEF::assembly::powerpc::REG::H2) + .value("H3", LIEF::assembly::powerpc::REG::H3) + .value("H4", LIEF::assembly::powerpc::REG::H4) + .value("H5", LIEF::assembly::powerpc::REG::H5) + .value("H6", LIEF::assembly::powerpc::REG::H6) + .value("H7", LIEF::assembly::powerpc::REG::H7) + .value("H8", LIEF::assembly::powerpc::REG::H8) + .value("H9", LIEF::assembly::powerpc::REG::H9) + .value("H10", LIEF::assembly::powerpc::REG::H10) + .value("H11", LIEF::assembly::powerpc::REG::H11) + .value("H12", LIEF::assembly::powerpc::REG::H12) + .value("H13", LIEF::assembly::powerpc::REG::H13) + .value("H14", LIEF::assembly::powerpc::REG::H14) + .value("H15", LIEF::assembly::powerpc::REG::H15) + .value("H16", LIEF::assembly::powerpc::REG::H16) + .value("H17", LIEF::assembly::powerpc::REG::H17) + .value("H18", LIEF::assembly::powerpc::REG::H18) + .value("H19", LIEF::assembly::powerpc::REG::H19) + .value("H20", LIEF::assembly::powerpc::REG::H20) + .value("H21", LIEF::assembly::powerpc::REG::H21) + .value("H22", LIEF::assembly::powerpc::REG::H22) + .value("H23", LIEF::assembly::powerpc::REG::H23) + .value("H24", LIEF::assembly::powerpc::REG::H24) + .value("H25", LIEF::assembly::powerpc::REG::H25) + .value("H26", LIEF::assembly::powerpc::REG::H26) + .value("H27", LIEF::assembly::powerpc::REG::H27) + .value("H28", LIEF::assembly::powerpc::REG::H28) + .value("H29", LIEF::assembly::powerpc::REG::H29) + .value("H30", LIEF::assembly::powerpc::REG::H30) + .value("H31", LIEF::assembly::powerpc::REG::H31) + .value("LR8", LIEF::assembly::powerpc::REG::LR8) + .value("R0", LIEF::assembly::powerpc::REG::R0) + .value("R1", LIEF::assembly::powerpc::REG::R1) + .value("R2", LIEF::assembly::powerpc::REG::R2) + .value("R3", LIEF::assembly::powerpc::REG::R3) + .value("R4", LIEF::assembly::powerpc::REG::R4) + .value("R5", LIEF::assembly::powerpc::REG::R5) + .value("R6", LIEF::assembly::powerpc::REG::R6) + .value("R7", LIEF::assembly::powerpc::REG::R7) + .value("R8", LIEF::assembly::powerpc::REG::R8) + .value("R9", LIEF::assembly::powerpc::REG::R9) + .value("R10", LIEF::assembly::powerpc::REG::R10) + .value("R11", LIEF::assembly::powerpc::REG::R11) + .value("R12", LIEF::assembly::powerpc::REG::R12) + .value("R13", LIEF::assembly::powerpc::REG::R13) + .value("R14", LIEF::assembly::powerpc::REG::R14) + .value("R15", LIEF::assembly::powerpc::REG::R15) + .value("R16", LIEF::assembly::powerpc::REG::R16) + .value("R17", LIEF::assembly::powerpc::REG::R17) + .value("R18", LIEF::assembly::powerpc::REG::R18) + .value("R19", LIEF::assembly::powerpc::REG::R19) + .value("R20", LIEF::assembly::powerpc::REG::R20) + .value("R21", LIEF::assembly::powerpc::REG::R21) + .value("R22", LIEF::assembly::powerpc::REG::R22) + .value("R23", LIEF::assembly::powerpc::REG::R23) + .value("R24", LIEF::assembly::powerpc::REG::R24) + .value("R25", LIEF::assembly::powerpc::REG::R25) + .value("R26", LIEF::assembly::powerpc::REG::R26) + .value("R27", LIEF::assembly::powerpc::REG::R27) + .value("R28", LIEF::assembly::powerpc::REG::R28) + .value("R29", LIEF::assembly::powerpc::REG::R29) + .value("R30", LIEF::assembly::powerpc::REG::R30) + .value("R31", LIEF::assembly::powerpc::REG::R31) + .value("S0", LIEF::assembly::powerpc::REG::S0) + .value("S1", LIEF::assembly::powerpc::REG::S1) + .value("S2", LIEF::assembly::powerpc::REG::S2) + .value("S3", LIEF::assembly::powerpc::REG::S3) + .value("S4", LIEF::assembly::powerpc::REG::S4) + .value("S5", LIEF::assembly::powerpc::REG::S5) + .value("S6", LIEF::assembly::powerpc::REG::S6) + .value("S7", LIEF::assembly::powerpc::REG::S7) + .value("S8", LIEF::assembly::powerpc::REG::S8) + .value("S9", LIEF::assembly::powerpc::REG::S9) + .value("S10", LIEF::assembly::powerpc::REG::S10) + .value("S11", LIEF::assembly::powerpc::REG::S11) + .value("S12", LIEF::assembly::powerpc::REG::S12) + .value("S13", LIEF::assembly::powerpc::REG::S13) + .value("S14", LIEF::assembly::powerpc::REG::S14) + .value("S15", LIEF::assembly::powerpc::REG::S15) + .value("S16", LIEF::assembly::powerpc::REG::S16); + reg.value("S17", LIEF::assembly::powerpc::REG::S17) + .value("S18", LIEF::assembly::powerpc::REG::S18) + .value("S19", LIEF::assembly::powerpc::REG::S19) + .value("S20", LIEF::assembly::powerpc::REG::S20) + .value("S21", LIEF::assembly::powerpc::REG::S21) + .value("S22", LIEF::assembly::powerpc::REG::S22) + .value("S23", LIEF::assembly::powerpc::REG::S23) + .value("S24", LIEF::assembly::powerpc::REG::S24) + .value("S25", LIEF::assembly::powerpc::REG::S25) + .value("S26", LIEF::assembly::powerpc::REG::S26) + .value("S27", LIEF::assembly::powerpc::REG::S27) + .value("S28", LIEF::assembly::powerpc::REG::S28) + .value("S29", LIEF::assembly::powerpc::REG::S29) + .value("S30", LIEF::assembly::powerpc::REG::S30) + .value("S31", LIEF::assembly::powerpc::REG::S31) + .value("UACC0", LIEF::assembly::powerpc::REG::UACC0) + .value("UACC1", LIEF::assembly::powerpc::REG::UACC1) + .value("UACC2", LIEF::assembly::powerpc::REG::UACC2) + .value("UACC3", LIEF::assembly::powerpc::REG::UACC3) + .value("UACC4", LIEF::assembly::powerpc::REG::UACC4) + .value("UACC5", LIEF::assembly::powerpc::REG::UACC5) + .value("UACC6", LIEF::assembly::powerpc::REG::UACC6) + .value("UACC7", LIEF::assembly::powerpc::REG::UACC7) + .value("V0", LIEF::assembly::powerpc::REG::V0) + .value("V1", LIEF::assembly::powerpc::REG::V1) + .value("V2", LIEF::assembly::powerpc::REG::V2) + .value("V3", LIEF::assembly::powerpc::REG::V3) + .value("V4", LIEF::assembly::powerpc::REG::V4) + .value("V5", LIEF::assembly::powerpc::REG::V5) + .value("V6", LIEF::assembly::powerpc::REG::V6) + .value("V7", LIEF::assembly::powerpc::REG::V7) + .value("V8", LIEF::assembly::powerpc::REG::V8) + .value("V9", LIEF::assembly::powerpc::REG::V9) + .value("V10", LIEF::assembly::powerpc::REG::V10) + .value("V11", LIEF::assembly::powerpc::REG::V11) + .value("V12", LIEF::assembly::powerpc::REG::V12) + .value("V13", LIEF::assembly::powerpc::REG::V13) + .value("V14", LIEF::assembly::powerpc::REG::V14) + .value("V15", LIEF::assembly::powerpc::REG::V15) + .value("V16", LIEF::assembly::powerpc::REG::V16) + .value("V17", LIEF::assembly::powerpc::REG::V17) + .value("V18", LIEF::assembly::powerpc::REG::V18) + .value("V19", LIEF::assembly::powerpc::REG::V19) + .value("V20", LIEF::assembly::powerpc::REG::V20) + .value("V21", LIEF::assembly::powerpc::REG::V21) + .value("V22", LIEF::assembly::powerpc::REG::V22) + .value("V23", LIEF::assembly::powerpc::REG::V23) + .value("V24", LIEF::assembly::powerpc::REG::V24) + .value("V25", LIEF::assembly::powerpc::REG::V25) + .value("V26", LIEF::assembly::powerpc::REG::V26) + .value("V27", LIEF::assembly::powerpc::REG::V27) + .value("V28", LIEF::assembly::powerpc::REG::V28) + .value("V29", LIEF::assembly::powerpc::REG::V29) + .value("V30", LIEF::assembly::powerpc::REG::V30) + .value("V31", LIEF::assembly::powerpc::REG::V31) + .value("VF0", LIEF::assembly::powerpc::REG::VF0) + .value("VF1", LIEF::assembly::powerpc::REG::VF1) + .value("VF2", LIEF::assembly::powerpc::REG::VF2) + .value("VF3", LIEF::assembly::powerpc::REG::VF3) + .value("VF4", LIEF::assembly::powerpc::REG::VF4) + .value("VF5", LIEF::assembly::powerpc::REG::VF5) + .value("VF6", LIEF::assembly::powerpc::REG::VF6) + .value("VF7", LIEF::assembly::powerpc::REG::VF7) + .value("VF8", LIEF::assembly::powerpc::REG::VF8) + .value("VF9", LIEF::assembly::powerpc::REG::VF9) + .value("VF10", LIEF::assembly::powerpc::REG::VF10) + .value("VF11", LIEF::assembly::powerpc::REG::VF11) + .value("VF12", LIEF::assembly::powerpc::REG::VF12) + .value("VF13", LIEF::assembly::powerpc::REG::VF13) + .value("VF14", LIEF::assembly::powerpc::REG::VF14) + .value("VF15", LIEF::assembly::powerpc::REG::VF15) + .value("VF16", LIEF::assembly::powerpc::REG::VF16) + .value("VF17", LIEF::assembly::powerpc::REG::VF17) + .value("VF18", LIEF::assembly::powerpc::REG::VF18) + .value("VF19", LIEF::assembly::powerpc::REG::VF19) + .value("VF20", LIEF::assembly::powerpc::REG::VF20) + .value("VF21", LIEF::assembly::powerpc::REG::VF21) + .value("VF22", LIEF::assembly::powerpc::REG::VF22) + .value("VF23", LIEF::assembly::powerpc::REG::VF23) + .value("VF24", LIEF::assembly::powerpc::REG::VF24) + .value("VF25", LIEF::assembly::powerpc::REG::VF25) + .value("VF26", LIEF::assembly::powerpc::REG::VF26) + .value("VF27", LIEF::assembly::powerpc::REG::VF27) + .value("VF28", LIEF::assembly::powerpc::REG::VF28) + .value("VF29", LIEF::assembly::powerpc::REG::VF29) + .value("VF30", LIEF::assembly::powerpc::REG::VF30) + .value("VF31", LIEF::assembly::powerpc::REG::VF31) + .value("VFH0", LIEF::assembly::powerpc::REG::VFH0) + .value("VFH1", LIEF::assembly::powerpc::REG::VFH1) + .value("VFH2", LIEF::assembly::powerpc::REG::VFH2) + .value("VFH3", LIEF::assembly::powerpc::REG::VFH3) + .value("VFH4", LIEF::assembly::powerpc::REG::VFH4) + .value("VFH5", LIEF::assembly::powerpc::REG::VFH5) + .value("VFH6", LIEF::assembly::powerpc::REG::VFH6) + .value("VFH7", LIEF::assembly::powerpc::REG::VFH7) + .value("VFH8", LIEF::assembly::powerpc::REG::VFH8) + .value("VFH9", LIEF::assembly::powerpc::REG::VFH9) + .value("VFH10", LIEF::assembly::powerpc::REG::VFH10) + .value("VFH11", LIEF::assembly::powerpc::REG::VFH11) + .value("VFH12", LIEF::assembly::powerpc::REG::VFH12) + .value("VFH13", LIEF::assembly::powerpc::REG::VFH13) + .value("VFH14", LIEF::assembly::powerpc::REG::VFH14) + .value("VFH15", LIEF::assembly::powerpc::REG::VFH15) + .value("VFH16", LIEF::assembly::powerpc::REG::VFH16) + .value("VFH17", LIEF::assembly::powerpc::REG::VFH17) + .value("VFH18", LIEF::assembly::powerpc::REG::VFH18) + .value("VFH19", LIEF::assembly::powerpc::REG::VFH19) + .value("VFH20", LIEF::assembly::powerpc::REG::VFH20) + .value("VFH21", LIEF::assembly::powerpc::REG::VFH21) + .value("VFH22", LIEF::assembly::powerpc::REG::VFH22) + .value("VFH23", LIEF::assembly::powerpc::REG::VFH23) + .value("VFH24", LIEF::assembly::powerpc::REG::VFH24) + .value("VFH25", LIEF::assembly::powerpc::REG::VFH25) + .value("VFH26", LIEF::assembly::powerpc::REG::VFH26) + .value("VFH27", LIEF::assembly::powerpc::REG::VFH27) + .value("VFH28", LIEF::assembly::powerpc::REG::VFH28) + .value("VFH29", LIEF::assembly::powerpc::REG::VFH29) + .value("VFH30", LIEF::assembly::powerpc::REG::VFH30) + .value("VFH31", LIEF::assembly::powerpc::REG::VFH31) + .value("VSL0", LIEF::assembly::powerpc::REG::VSL0) + .value("VSL1", LIEF::assembly::powerpc::REG::VSL1) + .value("VSL2", LIEF::assembly::powerpc::REG::VSL2) + .value("VSL3", LIEF::assembly::powerpc::REG::VSL3) + .value("VSL4", LIEF::assembly::powerpc::REG::VSL4) + .value("VSL5", LIEF::assembly::powerpc::REG::VSL5) + .value("VSL6", LIEF::assembly::powerpc::REG::VSL6) + .value("VSL7", LIEF::assembly::powerpc::REG::VSL7) + .value("VSL8", LIEF::assembly::powerpc::REG::VSL8) + .value("VSL9", LIEF::assembly::powerpc::REG::VSL9) + .value("VSL10", LIEF::assembly::powerpc::REG::VSL10) + .value("VSL11", LIEF::assembly::powerpc::REG::VSL11) + .value("VSL12", LIEF::assembly::powerpc::REG::VSL12) + .value("VSL13", LIEF::assembly::powerpc::REG::VSL13) + .value("VSL14", LIEF::assembly::powerpc::REG::VSL14) + .value("VSL15", LIEF::assembly::powerpc::REG::VSL15) + .value("VSL16", LIEF::assembly::powerpc::REG::VSL16) + .value("VSL17", LIEF::assembly::powerpc::REG::VSL17) + .value("VSL18", LIEF::assembly::powerpc::REG::VSL18) + .value("VSL19", LIEF::assembly::powerpc::REG::VSL19) + .value("VSL20", LIEF::assembly::powerpc::REG::VSL20) + .value("VSL21", LIEF::assembly::powerpc::REG::VSL21) + .value("VSL22", LIEF::assembly::powerpc::REG::VSL22) + .value("VSL23", LIEF::assembly::powerpc::REG::VSL23) + .value("VSL24", LIEF::assembly::powerpc::REG::VSL24) + .value("VSL25", LIEF::assembly::powerpc::REG::VSL25) + .value("VSL26", LIEF::assembly::powerpc::REG::VSL26) + .value("VSL27", LIEF::assembly::powerpc::REG::VSL27) + .value("VSL28", LIEF::assembly::powerpc::REG::VSL28) + .value("VSL29", LIEF::assembly::powerpc::REG::VSL29) + .value("VSL30", LIEF::assembly::powerpc::REG::VSL30) + .value("VSL31", LIEF::assembly::powerpc::REG::VSL31) + .value("VSRp0", LIEF::assembly::powerpc::REG::VSRp0) + .value("VSRp1", LIEF::assembly::powerpc::REG::VSRp1) + .value("VSRp2", LIEF::assembly::powerpc::REG::VSRp2) + .value("VSRp3", LIEF::assembly::powerpc::REG::VSRp3) + .value("VSRp4", LIEF::assembly::powerpc::REG::VSRp4) + .value("VSRp5", LIEF::assembly::powerpc::REG::VSRp5) + .value("VSRp6", LIEF::assembly::powerpc::REG::VSRp6) + .value("VSRp7", LIEF::assembly::powerpc::REG::VSRp7) + .value("VSRp8", LIEF::assembly::powerpc::REG::VSRp8) + .value("VSRp9", LIEF::assembly::powerpc::REG::VSRp9) + .value("VSRp10", LIEF::assembly::powerpc::REG::VSRp10) + .value("VSRp11", LIEF::assembly::powerpc::REG::VSRp11) + .value("VSRp12", LIEF::assembly::powerpc::REG::VSRp12) + .value("VSRp13", LIEF::assembly::powerpc::REG::VSRp13) + .value("VSRp14", LIEF::assembly::powerpc::REG::VSRp14) + .value("VSRp15", LIEF::assembly::powerpc::REG::VSRp15) + .value("VSRp16", LIEF::assembly::powerpc::REG::VSRp16) + .value("VSRp17", LIEF::assembly::powerpc::REG::VSRp17) + .value("VSRp18", LIEF::assembly::powerpc::REG::VSRp18) + .value("VSRp19", LIEF::assembly::powerpc::REG::VSRp19) + .value("VSRp20", LIEF::assembly::powerpc::REG::VSRp20) + .value("VSRp21", LIEF::assembly::powerpc::REG::VSRp21) + .value("VSRp22", LIEF::assembly::powerpc::REG::VSRp22) + .value("VSRp23", LIEF::assembly::powerpc::REG::VSRp23) + .value("VSRp24", LIEF::assembly::powerpc::REG::VSRp24) + .value("VSRp25", LIEF::assembly::powerpc::REG::VSRp25) + .value("VSRp26", LIEF::assembly::powerpc::REG::VSRp26) + .value("VSRp27", LIEF::assembly::powerpc::REG::VSRp27) + .value("VSRp28", LIEF::assembly::powerpc::REG::VSRp28) + .value("VSRp29", LIEF::assembly::powerpc::REG::VSRp29) + .value("VSRp30", LIEF::assembly::powerpc::REG::VSRp30) + .value("VSRp31", LIEF::assembly::powerpc::REG::VSRp31) + .value("VSX32", LIEF::assembly::powerpc::REG::VSX32) + .value("VSX33", LIEF::assembly::powerpc::REG::VSX33) + .value("VSX34", LIEF::assembly::powerpc::REG::VSX34) + .value("VSX35", LIEF::assembly::powerpc::REG::VSX35) + .value("VSX36", LIEF::assembly::powerpc::REG::VSX36) + .value("VSX37", LIEF::assembly::powerpc::REG::VSX37) + .value("VSX38", LIEF::assembly::powerpc::REG::VSX38) + .value("VSX39", LIEF::assembly::powerpc::REG::VSX39) + .value("VSX40", LIEF::assembly::powerpc::REG::VSX40) + .value("VSX41", LIEF::assembly::powerpc::REG::VSX41) + .value("VSX42", LIEF::assembly::powerpc::REG::VSX42) + .value("VSX43", LIEF::assembly::powerpc::REG::VSX43) + .value("VSX44", LIEF::assembly::powerpc::REG::VSX44) + .value("VSX45", LIEF::assembly::powerpc::REG::VSX45) + .value("VSX46", LIEF::assembly::powerpc::REG::VSX46) + .value("VSX47", LIEF::assembly::powerpc::REG::VSX47) + .value("VSX48", LIEF::assembly::powerpc::REG::VSX48) + .value("VSX49", LIEF::assembly::powerpc::REG::VSX49) + .value("VSX50", LIEF::assembly::powerpc::REG::VSX50) + .value("VSX51", LIEF::assembly::powerpc::REG::VSX51) + .value("VSX52", LIEF::assembly::powerpc::REG::VSX52) + .value("VSX53", LIEF::assembly::powerpc::REG::VSX53) + .value("VSX54", LIEF::assembly::powerpc::REG::VSX54) + .value("VSX55", LIEF::assembly::powerpc::REG::VSX55) + .value("VSX56", LIEF::assembly::powerpc::REG::VSX56) + .value("VSX57", LIEF::assembly::powerpc::REG::VSX57) + .value("VSX58", LIEF::assembly::powerpc::REG::VSX58) + .value("VSX59", LIEF::assembly::powerpc::REG::VSX59) + .value("VSX60", LIEF::assembly::powerpc::REG::VSX60) + .value("VSX61", LIEF::assembly::powerpc::REG::VSX61) + .value("VSX62", LIEF::assembly::powerpc::REG::VSX62) + .value("VSX63", LIEF::assembly::powerpc::REG::VSX63) + .value("WACC0", LIEF::assembly::powerpc::REG::WACC0) + .value("WACC1", LIEF::assembly::powerpc::REG::WACC1) + .value("WACC2", LIEF::assembly::powerpc::REG::WACC2) + .value("WACC3", LIEF::assembly::powerpc::REG::WACC3) + .value("WACC4", LIEF::assembly::powerpc::REG::WACC4) + .value("WACC5", LIEF::assembly::powerpc::REG::WACC5) + .value("WACC6", LIEF::assembly::powerpc::REG::WACC6) + .value("WACC7", LIEF::assembly::powerpc::REG::WACC7) + .value("WACC_HI0", LIEF::assembly::powerpc::REG::WACC_HI0) + .value("WACC_HI1", LIEF::assembly::powerpc::REG::WACC_HI1) + .value("WACC_HI2", LIEF::assembly::powerpc::REG::WACC_HI2) + .value("WACC_HI3", LIEF::assembly::powerpc::REG::WACC_HI3) + .value("WACC_HI4", LIEF::assembly::powerpc::REG::WACC_HI4) + .value("WACC_HI5", LIEF::assembly::powerpc::REG::WACC_HI5) + .value("WACC_HI6", LIEF::assembly::powerpc::REG::WACC_HI6) + .value("WACC_HI7", LIEF::assembly::powerpc::REG::WACC_HI7) + .value("X0", LIEF::assembly::powerpc::REG::X0) + .value("X1", LIEF::assembly::powerpc::REG::X1) + .value("X2", LIEF::assembly::powerpc::REG::X2) + .value("X3", LIEF::assembly::powerpc::REG::X3) + .value("X4", LIEF::assembly::powerpc::REG::X4) + .value("X5", LIEF::assembly::powerpc::REG::X5) + .value("X6", LIEF::assembly::powerpc::REG::X6) + .value("X7", LIEF::assembly::powerpc::REG::X7) + .value("X8", LIEF::assembly::powerpc::REG::X8) + .value("X9", LIEF::assembly::powerpc::REG::X9) + .value("X10", LIEF::assembly::powerpc::REG::X10) + .value("X11", LIEF::assembly::powerpc::REG::X11) + .value("X12", LIEF::assembly::powerpc::REG::X12) + .value("X13", LIEF::assembly::powerpc::REG::X13) + .value("X14", LIEF::assembly::powerpc::REG::X14) + .value("X15", LIEF::assembly::powerpc::REG::X15) + .value("X16", LIEF::assembly::powerpc::REG::X16) + .value("X17", LIEF::assembly::powerpc::REG::X17) + .value("X18", LIEF::assembly::powerpc::REG::X18) + .value("X19", LIEF::assembly::powerpc::REG::X19) + .value("X20", LIEF::assembly::powerpc::REG::X20) + .value("X21", LIEF::assembly::powerpc::REG::X21) + .value("X22", LIEF::assembly::powerpc::REG::X22) + .value("X23", LIEF::assembly::powerpc::REG::X23) + .value("X24", LIEF::assembly::powerpc::REG::X24) + .value("X25", LIEF::assembly::powerpc::REG::X25) + .value("X26", LIEF::assembly::powerpc::REG::X26) + .value("X27", LIEF::assembly::powerpc::REG::X27) + .value("X28", LIEF::assembly::powerpc::REG::X28) + .value("X29", LIEF::assembly::powerpc::REG::X29) + .value("X30", LIEF::assembly::powerpc::REG::X30) + .value("X31", LIEF::assembly::powerpc::REG::X31) + .value("ZERO8", LIEF::assembly::powerpc::REG::ZERO8) + .value("CR0EQ", LIEF::assembly::powerpc::REG::CR0EQ) + .value("CR1EQ", LIEF::assembly::powerpc::REG::CR1EQ) + .value("CR2EQ", LIEF::assembly::powerpc::REG::CR2EQ) + .value("CR3EQ", LIEF::assembly::powerpc::REG::CR3EQ) + .value("CR4EQ", LIEF::assembly::powerpc::REG::CR4EQ) + .value("CR5EQ", LIEF::assembly::powerpc::REG::CR5EQ) + .value("CR6EQ", LIEF::assembly::powerpc::REG::CR6EQ) + .value("CR7EQ", LIEF::assembly::powerpc::REG::CR7EQ) + .value("CR0GT", LIEF::assembly::powerpc::REG::CR0GT) + .value("CR1GT", LIEF::assembly::powerpc::REG::CR1GT) + .value("CR2GT", LIEF::assembly::powerpc::REG::CR2GT) + .value("CR3GT", LIEF::assembly::powerpc::REG::CR3GT) + .value("CR4GT", LIEF::assembly::powerpc::REG::CR4GT) + .value("CR5GT", LIEF::assembly::powerpc::REG::CR5GT) + .value("CR6GT", LIEF::assembly::powerpc::REG::CR6GT) + .value("CR7GT", LIEF::assembly::powerpc::REG::CR7GT) + .value("CR0LT", LIEF::assembly::powerpc::REG::CR0LT) + .value("CR1LT", LIEF::assembly::powerpc::REG::CR1LT) + .value("CR2LT", LIEF::assembly::powerpc::REG::CR2LT) + .value("CR3LT", LIEF::assembly::powerpc::REG::CR3LT) + .value("CR4LT", LIEF::assembly::powerpc::REG::CR4LT) + .value("CR5LT", LIEF::assembly::powerpc::REG::CR5LT) + .value("CR6LT", LIEF::assembly::powerpc::REG::CR6LT) + .value("CR7LT", LIEF::assembly::powerpc::REG::CR7LT) + .value("CR0UN", LIEF::assembly::powerpc::REG::CR0UN) + .value("CR1UN", LIEF::assembly::powerpc::REG::CR1UN) + .value("CR2UN", LIEF::assembly::powerpc::REG::CR2UN) + .value("CR3UN", LIEF::assembly::powerpc::REG::CR3UN) + .value("CR4UN", LIEF::assembly::powerpc::REG::CR4UN) + .value("CR5UN", LIEF::assembly::powerpc::REG::CR5UN) + .value("CR6UN", LIEF::assembly::powerpc::REG::CR6UN) + .value("CR7UN", LIEF::assembly::powerpc::REG::CR7UN) + .value("G8p0", LIEF::assembly::powerpc::REG::G8p0) + .value("G8p1", LIEF::assembly::powerpc::REG::G8p1) + .value("G8p2", LIEF::assembly::powerpc::REG::G8p2) + .value("G8p3", LIEF::assembly::powerpc::REG::G8p3); + reg.value("G8p4", LIEF::assembly::powerpc::REG::G8p4) + .value("G8p5", LIEF::assembly::powerpc::REG::G8p5) + .value("G8p6", LIEF::assembly::powerpc::REG::G8p6) + .value("G8p7", LIEF::assembly::powerpc::REG::G8p7) + .value("G8p8", LIEF::assembly::powerpc::REG::G8p8) + .value("G8p9", LIEF::assembly::powerpc::REG::G8p9) + .value("G8p10", LIEF::assembly::powerpc::REG::G8p10) + .value("G8p11", LIEF::assembly::powerpc::REG::G8p11) + .value("G8p12", LIEF::assembly::powerpc::REG::G8p12) + .value("G8p13", LIEF::assembly::powerpc::REG::G8p13) + .value("G8p14", LIEF::assembly::powerpc::REG::G8p14) + .value("G8p15", LIEF::assembly::powerpc::REG::G8p15) + .value("NUM_TARGET_REGS", LIEF::assembly::powerpc::REG::NUM_TARGET_REGS) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/pyAssemblerConfig.cpp b/vendor/lief/api/python/src/asm/pyAssemblerConfig.cpp new file mode 100644 index 0000000..f2d9a24 --- /dev/null +++ b/vendor/lief/api/python/src/asm/pyAssemblerConfig.cpp @@ -0,0 +1,77 @@ +#include "LIEF/asm/AssemblerConfig.hpp" +#include "asm/pyAssembly.hpp" + +#include +#include +#include + +namespace LIEF::assembly::py { + +class PyAssemblerConfig : public assembly::AssemblerConfig { + public: + NB_TRAMPOLINE(assembly::AssemblerConfig); + + std::optional resolve_symbol(const std::string& name) override { + NB_OVERRIDE(resolve_symbol, name); + } + + ~PyAssemblerConfig() override = default; +}; + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "AssemblerConfig", + R"doc( + This class exposes the different elements that can be configured to assemble + code. + )doc"_doc + ); + + nb::enum_(obj, "DIALECT", + "The different supported dialects"_doc + ) + .value("DEFAULT_DIALECT", assembly::AssemblerConfig::DIALECT::DEFAULT_DIALECT) + .value("X86_INTEL", assembly::AssemblerConfig::DIALECT::X86_INTEL, + "Intel syntax"_doc) + .value("X86_ATT", assembly::AssemblerConfig::DIALECT::X86_ATT, + "AT&T syntax"_doc) + ; + + obj + .def(nb::init<>()) + .def_static("default_config", &assembly::AssemblerConfig::default_config, + "Default configuration"_doc + ) + .def_rw("dialect", &assembly::AssemblerConfig::dialect, + "The dialect of the input assembly code"_doc + ) + .def("resolve_symbol", &assembly::AssemblerConfig::resolve_symbol, + R"doc( + This function aims to be overloaded in order to resolve symbols used + in the assembly listing. + + For instance, given this assembly code: + + .. code-block:: text + + 0x1000: mov rdi, rbx + 0x1003: call _my_function + + The function ``_my_function`` will remain undefined unless we return its + address in :meth:`~.resolve_symbol`: + + .. code-block:: python + + class MyConfig(lief.assembly.AssemblerConfig): + def __init__(self): + super().__init__() # This is important + + @override + def resolve_symbol(self, name: str) -> int | None: + if name == '_my_function': + return 0x4000 + return None # Or super().resolve_symbol(name) + )doc"_doc, "name"_a) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/pyAssembly.hpp b/vendor/lief/api/python/src/asm/pyAssembly.hpp new file mode 100644 index 0000000..2c0ccf6 --- /dev/null +++ b/vendor/lief/api/python/src/asm/pyAssembly.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_H +#define PY_LIEF_ASM_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::py { + +namespace assembly = LIEF::assembly; + +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/asm/pyEngine.cpp b/vendor/lief/api/python/src/asm/pyEngine.cpp new file mode 100644 index 0000000..2f71ab3 --- /dev/null +++ b/vendor/lief/api/python/src/asm/pyEngine.cpp @@ -0,0 +1,16 @@ +#include "LIEF/asm/Engine.hpp" +#include "asm/pyAssembly.hpp" + +#include +#include + +namespace LIEF::assembly::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Engine", + R"doc( + This class interfaces the assembler/disassembler support + )doc"_doc + ); +} +} diff --git a/vendor/lief/api/python/src/asm/pyInstruction.cpp b/vendor/lief/api/python/src/asm/pyInstruction.cpp new file mode 100644 index 0000000..b0b4412 --- /dev/null +++ b/vendor/lief/api/python/src/asm/pyInstruction.cpp @@ -0,0 +1,153 @@ +#include +#include +#include "pyLIEF.hpp" +#include "pyErr.hpp" +#include "enums_wrapper.hpp" +#include "LIEF/asm/Instruction.hpp" +#include "asm/pyAssembly.hpp" + +#include +#include + +#include "nanobind/utils.hpp" + +namespace LIEF::assembly::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc( + This class represents an assembly instruction + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("mnemonic"); + + enum_(obj, "MemoryAccess", nb::is_flag()) + .value("NONE", Instruction::MemoryAccess::NONE) + .value("READ", Instruction::MemoryAccess::READ) + .value("WRITE", Instruction::MemoryAccess::WRITE); + + obj + .def_prop_ro("address", &Instruction::address, + R"doc(Address of the instruction)doc"_doc + ) + + .def_prop_ro("size", &Instruction::size, + R"doc(Size of the instruction in bytes)doc"_doc + ) + + .def_prop_ro("mnemonic", &Instruction::mnemonic, + R"doc(Instruction mnemonic (e.g. ``br``))doc"_doc + ) + + .def("to_string", &Instruction::to_string, + "with_address"_a = true, + R"doc(Representation of the current instruction in a pretty assembly way)doc"_doc + ) + + .def_prop_ro("raw", [] (const Instruction& inst) { + return nb::to_bytes(inst.raw()); + }, R"doc(Raw bytes of the current instruction)doc"_doc + ) + + .def_prop_ro("is_call", &Instruction::is_call, + R"doc(True if the instruction is a call)doc"_doc + ) + + .def_prop_ro("is_terminator", &Instruction::is_terminator, + R"doc(True if the instruction marks the end of a basic block)doc"_doc + ) + + .def_prop_ro("is_branch", &Instruction::is_branch, + R"doc(True if the instruction is a branch)doc"_doc + ) + + .def_prop_ro("is_syscall", &Instruction::is_syscall, + R"doc(True if the instruction is a syscall)doc"_doc + ) + + .def_prop_ro("is_memory_access", &Instruction::is_memory_access, + R"doc(True if the instruction performs a memory access)doc"_doc + ) + + .def_prop_ro("is_move_reg", &Instruction::is_move_reg, + R"doc(True if the instruction is a register to register move.)doc"_doc + ) + + .def_prop_ro("is_add", &Instruction::is_add, + R"doc(True if the instruction performs an arithmetic addition.)doc"_doc + ) + + .def_prop_ro("is_trap", &Instruction::is_trap, + R"doc( + True if the instruction is a trap. + + - On ``x86/x86-64`` this includes the ``ud1/ud2`` instructions + - On ``AArch64`` this includes the ``brk/udf`` instructions + )doc"_doc + ) + + .def_prop_ro("is_barrier", &Instruction::is_barrier, + R"doc( + True if the instruction prevents executing the instruction + that immediately follows the current. This includes return + or unconditional branch instructions + )doc"_doc + ) + + .def_prop_ro("is_return", &Instruction::is_return, + R"doc(True if the instruction is a return)doc"_doc + ) + + .def_prop_ro("is_indirect_branch", &Instruction::is_indirect_branch, + R"doc( + True if the instruction is an indirect branch. + + This includes instructions that branch through a register (e.g. + ``jmp rax``, ``br x1``). + )doc"_doc) + + .def_prop_ro("is_conditional_branch", &Instruction::is_conditional_branch, + R"doc( + True if the instruction is **conditionally** jumping to the next + instruction **or** an instruction into some other basic block. + )doc"_doc + ) + + .def_prop_ro("is_unconditional_branch", &Instruction::is_unconditional_branch, + R"doc( + True if the instruction is jumping (**unconditionally**) to some other + basic block. + )doc"_doc + ) + + .def_prop_ro("is_compare", &Instruction::is_compare, + R"doc(True if the instruction is a comparison)doc"_doc + ) + + .def_prop_ro("is_move_immediate", &Instruction::is_move_immediate, + R"doc(True if the instruction is moving an immediate)doc"_doc + ) + + .def_prop_ro("is_bitcast", &Instruction::is_bitcast, + R"doc(True if the instruction is doing a bitcast)doc"_doc + ) + + .def_prop_ro("memory_access", &Instruction::memory_access, + R"doc(Memory access flags)doc"_doc + ) + + .def_prop_ro("branch_target", + [] (Instruction& self) { + return LIEF::py::error_or(&Instruction::branch_target, self); + }, + R"doc( + Given a :attr:`~.Instruction.is_branch` instruction, try to evaluate the + address of the destination. + )doc"_doc + ) + + LIEF_DEFAULT_STR(Instruction) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/CMakeLists.txt b/vendor/lief/api/python/src/asm/riscv/CMakeLists.txt new file mode 100644 index 0000000..c5e4e70 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyOperand.cpp + pyRegister.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/riscv/init.cpp b/vendor/lief/api/python/src/asm/riscv/init.cpp new file mode 100644 index 0000000..348a6f6 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/init.cpp @@ -0,0 +1,20 @@ +#include "asm/riscv/init.hpp" +namespace LIEF::assembly::riscv { +enum class OPCODE; +enum class REG; +enum class SYSREG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::riscv::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("riscv"); + + create(mod); + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/init.hpp b/vendor/lief/api/python/src/asm/riscv/init.hpp new file mode 100644 index 0000000..650af08 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_RISCV_INIT_H +#define PY_LIEF_ASM_RISCV_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::riscv::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/riscv/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/riscv/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/riscv/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/riscv/operands/pyImmediate.cpp new file mode 100644 index 0000000..d00b592 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/operands/pyImmediate.cpp @@ -0,0 +1,29 @@ +#include "asm/riscv/init.hpp" +#include "LIEF/asm/riscv/operands/Immediate.hpp" + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + + For instance: + + .. code-block:: text + + addi a0, a1, 8 + | + +---> Immediate(8) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/riscv/operands/pyMemory.cpp new file mode 100644 index 0000000..065e6c2 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/operands/pyMemory.cpp @@ -0,0 +1,40 @@ +#include "asm/riscv/init.hpp" +#include "LIEF/asm/riscv/operands/Memory.hpp" + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + .. code-block:: text + + lw a0, 8(sp) + | | + | +----> Base: sp + | + +-------> Displacement: 8 + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("base", "displacement"); + + obj + .def_prop_ro("base", &operands::Memory::base, + R"doc( + The base register. + + For ``lw a0, 8(sp)`` it would return ``sp``. + )doc"_doc + ) + .def_prop_ro("displacement", &operands::Memory::displacement, + R"doc( + The displacement value. + + For ``lw a0, 8(sp)`` it would return ``8``. + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/riscv/operands/pyPCRelative.cpp new file mode 100644 index 0000000..2d9c4e4 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/operands/pyPCRelative.cpp @@ -0,0 +1,30 @@ +#include "asm/riscv/init.hpp" +#include "LIEF/asm/riscv/operands/PCRelative.hpp" + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a PC-relative operand. + + .. code-block:: text + + auipc a0, 0x1 + | + v + PC Relative operand + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &riscv::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``pc`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/riscv/operands/pyRegister.cpp new file mode 100644 index 0000000..8832eef --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/operands/pyRegister.cpp @@ -0,0 +1,68 @@ +#include + +#include "asm/riscv/init.hpp" +#include "LIEF/asm/riscv/operands/Register.hpp" + +namespace nanobind::detail { +template<> +struct type_caster { + NB_TYPE_CASTER(LIEF::assembly::riscv::operands::Register::reg_t, + const_name("Optional[Union[lief.assembly.riscv.REG, lief.assembly.riscv.SYSREG]]")); + + bool from_python(handle, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::assembly::riscv::operands::Register::reg_t val, + rv_policy, cleanup_list *) noexcept + { + using namespace LIEF::assembly::riscv; + using namespace LIEF::assembly::riscv::operands; + switch (val.type) { + case Register::reg_t::TYPE::REG: + return make_caster::from_cpp(val.reg, rv_policy::copy, + /*cleanup_list*/nullptr); + + case Register::reg_t::TYPE::SYSREG: + return make_caster::from_cpp(val.sysreg, rv_policy::copy, + /*cleanup_list*/nullptr); + case Register::reg_t::TYPE::NONE: + return nb::none(); + } + return nb::none(); + } +}; +} + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + .. code-block:: text + + csrr a0, mstatus + | | + +------+ +-------+ + | | + v v + REG SYSREG + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Register::value, + R"doc( + The effective register as either: a :class:`lief.assembly.riscv.REG` or + a :class:`lief.assembly.riscv.SYSREG`. + )doc"_doc + ) + ; + + +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/pyInstruction.cpp b/vendor/lief/api/python/src/asm/riscv/pyInstruction.cpp new file mode 100644 index 0000000..e767f05 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/pyInstruction.cpp @@ -0,0 +1,34 @@ +#include "LIEF/asm/riscv/Instruction.hpp" +#include "LIEF/asm/riscv/Operand.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include "asm/riscv/init.hpp" + +#include + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents a RISC-V (32 or 64 bit) instruction)doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("operands", [] (const riscv::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/pyOpcode.cpp b/vendor/lief/api/python/src/asm/riscv/pyOpcode.cpp new file mode 100644 index 0000000..3f520fb --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/pyOpcode.cpp @@ -0,0 +1,16233 @@ +#include "asm/riscv/init.hpp" + +#include "LIEF/asm/riscv/opcodes.hpp" + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::riscv::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::riscv::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::riscv::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::riscv::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::riscv::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::riscv::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::riscv::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::riscv::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::riscv::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::riscv::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::riscv::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::riscv::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::riscv::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::riscv::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::riscv::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::riscv::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::riscv::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::riscv::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::riscv::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::riscv::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::riscv::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::riscv::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::riscv::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::riscv::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::riscv::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::riscv::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::riscv::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::riscv::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::riscv::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::riscv::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::riscv::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::riscv::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::riscv::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::riscv::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::riscv::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::riscv::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::riscv::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::riscv::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::riscv::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::riscv::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::riscv::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::riscv::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::riscv::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::riscv::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::riscv::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::riscv::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::riscv::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::riscv::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::riscv::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::riscv::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::riscv::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::riscv::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::riscv::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::riscv::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::riscv::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::riscv::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::riscv::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::riscv::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::riscv::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::riscv::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::riscv::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::riscv::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::riscv::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::riscv::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::riscv::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::riscv::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::riscv::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::riscv::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::riscv::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::riscv::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::riscv::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::riscv::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::riscv::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::riscv::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::riscv::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::riscv::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::riscv::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::riscv::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::riscv::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::riscv::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::riscv::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::riscv::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::riscv::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::riscv::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::riscv::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::riscv::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::riscv::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::riscv::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::riscv::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::riscv::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::riscv::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::riscv::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::riscv::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::riscv::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::riscv::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::riscv::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::riscv::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::riscv::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::riscv::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::riscv::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::riscv::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::riscv::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::riscv::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::riscv::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::riscv::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::riscv::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::riscv::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::riscv::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::riscv::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::riscv::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::riscv::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::riscv::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::riscv::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::riscv::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::riscv::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::riscv::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::riscv::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::riscv::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::riscv::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::riscv::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::riscv::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::riscv::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::riscv::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::riscv::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::riscv::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::riscv::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::riscv::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::riscv::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::riscv::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::riscv::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::riscv::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::riscv::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::riscv::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::riscv::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::riscv::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::riscv::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::riscv::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::riscv::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::riscv::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::riscv::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::riscv::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::riscv::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::riscv::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::riscv::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::riscv::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::riscv::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::riscv::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::riscv::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::riscv::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::riscv::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::riscv::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::riscv::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::riscv::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::riscv::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::riscv::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::riscv::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::riscv::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::riscv::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::riscv::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::riscv::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::riscv::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::riscv::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::riscv::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::riscv::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::riscv::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::riscv::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::riscv::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::riscv::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::riscv::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::riscv::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::riscv::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::riscv::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::riscv::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::riscv::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::riscv::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::riscv::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::riscv::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::riscv::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::riscv::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::riscv::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::riscv::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::riscv::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::riscv::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::riscv::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::riscv::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::riscv::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::riscv::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::riscv::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::riscv::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::riscv::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::riscv::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::riscv::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::riscv::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::riscv::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::riscv::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::riscv::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::riscv::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::riscv::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::riscv::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::riscv::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::riscv::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::riscv::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::riscv::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::riscv::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::riscv::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::riscv::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::riscv::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::riscv::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::riscv::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::riscv::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::riscv::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::riscv::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::riscv::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::riscv::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::riscv::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::riscv::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::riscv::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::riscv::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::riscv::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::riscv::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::riscv::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::riscv::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::riscv::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::riscv::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::riscv::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::riscv::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::riscv::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::riscv::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::riscv::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::riscv::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::riscv::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::riscv::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::riscv::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::riscv::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::riscv::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::riscv::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::riscv::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::riscv::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::riscv::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::riscv::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::riscv::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::riscv::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::riscv::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::riscv::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::riscv::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::riscv::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::riscv::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::riscv::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::riscv::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::riscv::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::riscv::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::riscv::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::riscv::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::riscv::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::riscv::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::riscv::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::riscv::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::riscv::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::riscv::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::riscv::OPCODE::G_UBFX) + .value("ADJCALLSTACKDOWN", LIEF::assembly::riscv::OPCODE::ADJCALLSTACKDOWN) + .value("ADJCALLSTACKUP", LIEF::assembly::riscv::OPCODE::ADJCALLSTACKUP) + .value("BuildPairF64Pseudo", LIEF::assembly::riscv::OPCODE::BuildPairF64Pseudo) + .value("ClearFCSR", LIEF::assembly::riscv::OPCODE::ClearFCSR) + .value("ClearFCSRImm", LIEF::assembly::riscv::OPCODE::ClearFCSRImm) + .value("G_CLZW", LIEF::assembly::riscv::OPCODE::G_CLZW) + .value("G_CTZW", LIEF::assembly::riscv::OPCODE::G_CTZW) + .value("G_DIVUW", LIEF::assembly::riscv::OPCODE::G_DIVUW) + .value("G_DIVW", LIEF::assembly::riscv::OPCODE::G_DIVW) + .value("G_FCLASS", LIEF::assembly::riscv::OPCODE::G_FCLASS) + .value("G_FCVT_WU_RV64", LIEF::assembly::riscv::OPCODE::G_FCVT_WU_RV64) + .value("G_FCVT_W_RV64", LIEF::assembly::riscv::OPCODE::G_FCVT_W_RV64) + .value("G_READ_VLENB", LIEF::assembly::riscv::OPCODE::G_READ_VLENB) + .value("G_REMUW", LIEF::assembly::riscv::OPCODE::G_REMUW) + .value("G_ROLW", LIEF::assembly::riscv::OPCODE::G_ROLW) + .value("G_RORW", LIEF::assembly::riscv::OPCODE::G_RORW) + .value("G_SLLW", LIEF::assembly::riscv::OPCODE::G_SLLW) + .value("G_SPLAT_VECTOR_SPLIT_I64_VL", LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR_SPLIT_I64_VL) + .value("G_SRAW", LIEF::assembly::riscv::OPCODE::G_SRAW) + .value("G_SRLW", LIEF::assembly::riscv::OPCODE::G_SRLW) + .value("G_VMCLR_VL", LIEF::assembly::riscv::OPCODE::G_VMCLR_VL) + .value("G_VMSET_VL", LIEF::assembly::riscv::OPCODE::G_VMSET_VL) + .value("G_VMV_V_V_VL", LIEF::assembly::riscv::OPCODE::G_VMV_V_V_VL) + .value("G_VSLIDEDOWN_VL", LIEF::assembly::riscv::OPCODE::G_VSLIDEDOWN_VL) + .value("G_VSLIDEUP_VL", LIEF::assembly::riscv::OPCODE::G_VSLIDEUP_VL) + .value("HWASAN_CHECK_MEMACCESS_SHORTGRANULES", LIEF::assembly::riscv::OPCODE::HWASAN_CHECK_MEMACCESS_SHORTGRANULES) + .value("KCFI_CHECK", LIEF::assembly::riscv::OPCODE::KCFI_CHECK) + .value("PROBED_STACKALLOC", LIEF::assembly::riscv::OPCODE::PROBED_STACKALLOC) + .value("PROBED_STACKALLOC_DYN", LIEF::assembly::riscv::OPCODE::PROBED_STACKALLOC_DYN) + .value("PROBED_STACKALLOC_RVV", LIEF::assembly::riscv::OPCODE::PROBED_STACKALLOC_RVV) + .value("PseudoAddTPRel", LIEF::assembly::riscv::OPCODE::PseudoAddTPRel) + .value("PseudoAtomicLoadAdd32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadAdd32) + .value("PseudoAtomicLoadAdd64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadAdd64) + .value("PseudoAtomicLoadAnd32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadAnd32) + .value("PseudoAtomicLoadAnd64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadAnd64) + .value("PseudoAtomicLoadMax32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadMax32) + .value("PseudoAtomicLoadMax64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadMax64) + .value("PseudoAtomicLoadMin32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadMin32) + .value("PseudoAtomicLoadMin64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadMin64) + .value("PseudoAtomicLoadNand32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand32) + .value("PseudoAtomicLoadNand64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand64) + .value("PseudoAtomicLoadOr32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadOr32) + .value("PseudoAtomicLoadOr64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadOr64) + .value("PseudoAtomicLoadSub32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadSub32) + .value("PseudoAtomicLoadSub64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadSub64) + .value("PseudoAtomicLoadUMax32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadUMax32) + .value("PseudoAtomicLoadUMax64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadUMax64) + .value("PseudoAtomicLoadUMin32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadUMin32) + .value("PseudoAtomicLoadUMin64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadUMin64) + .value("PseudoAtomicLoadXor32", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadXor32) + .value("PseudoAtomicLoadXor64", LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadXor64) + .value("PseudoAtomicSwap32", LIEF::assembly::riscv::OPCODE::PseudoAtomicSwap32) + .value("PseudoAtomicSwap64", LIEF::assembly::riscv::OPCODE::PseudoAtomicSwap64) + .value("PseudoBR", LIEF::assembly::riscv::OPCODE::PseudoBR) + .value("PseudoBRIND", LIEF::assembly::riscv::OPCODE::PseudoBRIND) + .value("PseudoBRINDNonX7", LIEF::assembly::riscv::OPCODE::PseudoBRINDNonX7) + .value("PseudoBRINDX7", LIEF::assembly::riscv::OPCODE::PseudoBRINDX7) + .value("PseudoCALL", LIEF::assembly::riscv::OPCODE::PseudoCALL) + .value("PseudoCALLIndirect", LIEF::assembly::riscv::OPCODE::PseudoCALLIndirect) + .value("PseudoCALLIndirectNonX7", LIEF::assembly::riscv::OPCODE::PseudoCALLIndirectNonX7) + .value("PseudoCALLIndirectX7", LIEF::assembly::riscv::OPCODE::PseudoCALLIndirectX7) + .value("PseudoCALLReg", LIEF::assembly::riscv::OPCODE::PseudoCALLReg) + .value("PseudoCCADD", LIEF::assembly::riscv::OPCODE::PseudoCCADD) + .value("PseudoCCADDI", LIEF::assembly::riscv::OPCODE::PseudoCCADDI) + .value("PseudoCCADDIW", LIEF::assembly::riscv::OPCODE::PseudoCCADDIW) + .value("PseudoCCADDW", LIEF::assembly::riscv::OPCODE::PseudoCCADDW) + .value("PseudoCCAND", LIEF::assembly::riscv::OPCODE::PseudoCCAND) + .value("PseudoCCANDI", LIEF::assembly::riscv::OPCODE::PseudoCCANDI) + .value("PseudoCCANDN", LIEF::assembly::riscv::OPCODE::PseudoCCANDN) + .value("PseudoCCLB", LIEF::assembly::riscv::OPCODE::PseudoCCLB) + .value("PseudoCCLBU", LIEF::assembly::riscv::OPCODE::PseudoCCLBU) + .value("PseudoCCLD", LIEF::assembly::riscv::OPCODE::PseudoCCLD) + .value("PseudoCCLH", LIEF::assembly::riscv::OPCODE::PseudoCCLH) + .value("PseudoCCLHU", LIEF::assembly::riscv::OPCODE::PseudoCCLHU) + .value("PseudoCCLUI", LIEF::assembly::riscv::OPCODE::PseudoCCLUI) + .value("PseudoCCLW", LIEF::assembly::riscv::OPCODE::PseudoCCLW) + .value("PseudoCCLWU", LIEF::assembly::riscv::OPCODE::PseudoCCLWU) + .value("PseudoCCMAX", LIEF::assembly::riscv::OPCODE::PseudoCCMAX) + .value("PseudoCCMAXU", LIEF::assembly::riscv::OPCODE::PseudoCCMAXU) + .value("PseudoCCMIN", LIEF::assembly::riscv::OPCODE::PseudoCCMIN) + .value("PseudoCCMINU", LIEF::assembly::riscv::OPCODE::PseudoCCMINU) + .value("PseudoCCMOVGPR", LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPR) + .value("PseudoCCMOVGPRNoX0", LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPRNoX0) + .value("PseudoCCMUL", LIEF::assembly::riscv::OPCODE::PseudoCCMUL) + .value("PseudoCCNDS_BFOS", LIEF::assembly::riscv::OPCODE::PseudoCCNDS_BFOS) + .value("PseudoCCNDS_BFOZ", LIEF::assembly::riscv::OPCODE::PseudoCCNDS_BFOZ) + .value("PseudoCCOR", LIEF::assembly::riscv::OPCODE::PseudoCCOR) + .value("PseudoCCORI", LIEF::assembly::riscv::OPCODE::PseudoCCORI) + .value("PseudoCCORN", LIEF::assembly::riscv::OPCODE::PseudoCCORN) + .value("PseudoCCQC_E_LB", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LB) + .value("PseudoCCQC_E_LBU", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LBU) + .value("PseudoCCQC_E_LH", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LH) + .value("PseudoCCQC_E_LHU", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LHU) + .value("PseudoCCQC_E_LI", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LI) + .value("PseudoCCQC_E_LW", LIEF::assembly::riscv::OPCODE::PseudoCCQC_E_LW) + .value("PseudoCCQC_LI", LIEF::assembly::riscv::OPCODE::PseudoCCQC_LI) + .value("PseudoCCSLL", LIEF::assembly::riscv::OPCODE::PseudoCCSLL) + .value("PseudoCCSLLI", LIEF::assembly::riscv::OPCODE::PseudoCCSLLI) + .value("PseudoCCSLLIW", LIEF::assembly::riscv::OPCODE::PseudoCCSLLIW) + .value("PseudoCCSLLW", LIEF::assembly::riscv::OPCODE::PseudoCCSLLW) + .value("PseudoCCSRA", LIEF::assembly::riscv::OPCODE::PseudoCCSRA) + .value("PseudoCCSRAI", LIEF::assembly::riscv::OPCODE::PseudoCCSRAI) + .value("PseudoCCSRAIW", LIEF::assembly::riscv::OPCODE::PseudoCCSRAIW) + .value("PseudoCCSRAW", LIEF::assembly::riscv::OPCODE::PseudoCCSRAW) + .value("PseudoCCSRL", LIEF::assembly::riscv::OPCODE::PseudoCCSRL) + .value("PseudoCCSRLI", LIEF::assembly::riscv::OPCODE::PseudoCCSRLI) + .value("PseudoCCSRLIW", LIEF::assembly::riscv::OPCODE::PseudoCCSRLIW) + .value("PseudoCCSRLW", LIEF::assembly::riscv::OPCODE::PseudoCCSRLW) + .value("PseudoCCSUB", LIEF::assembly::riscv::OPCODE::PseudoCCSUB) + .value("PseudoCCSUBW", LIEF::assembly::riscv::OPCODE::PseudoCCSUBW) + .value("PseudoCCXNOR", LIEF::assembly::riscv::OPCODE::PseudoCCXNOR) + .value("PseudoCCXOR", LIEF::assembly::riscv::OPCODE::PseudoCCXOR) + .value("PseudoCCXORI", LIEF::assembly::riscv::OPCODE::PseudoCCXORI) + .value("PseudoCV_ELW", LIEF::assembly::riscv::OPCODE::PseudoCV_ELW) + .value("PseudoC_ADDI_NOP", LIEF::assembly::riscv::OPCODE::PseudoC_ADDI_NOP) + .value("PseudoCmpXchg32", LIEF::assembly::riscv::OPCODE::PseudoCmpXchg32) + .value("PseudoCmpXchg64", LIEF::assembly::riscv::OPCODE::PseudoCmpXchg64) + .value("PseudoFLD", LIEF::assembly::riscv::OPCODE::PseudoFLD) + .value("PseudoFLH", LIEF::assembly::riscv::OPCODE::PseudoFLH) + .value("PseudoFLQ", LIEF::assembly::riscv::OPCODE::PseudoFLQ) + .value("PseudoFLW", LIEF::assembly::riscv::OPCODE::PseudoFLW) + .value("PseudoFROUND_D", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D) + .value("PseudoFROUND_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_IN32X) + .value("PseudoFROUND_D_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_INX) + .value("PseudoFROUND_H", LIEF::assembly::riscv::OPCODE::PseudoFROUND_H) + .value("PseudoFROUND_H_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_H_INX) + .value("PseudoFROUND_S", LIEF::assembly::riscv::OPCODE::PseudoFROUND_S) + .value("PseudoFROUND_S_INX", LIEF::assembly::riscv::OPCODE::PseudoFROUND_S_INX) + .value("PseudoFSD", LIEF::assembly::riscv::OPCODE::PseudoFSD) + .value("PseudoFSH", LIEF::assembly::riscv::OPCODE::PseudoFSH) + .value("PseudoFSQ", LIEF::assembly::riscv::OPCODE::PseudoFSQ) + .value("PseudoFSW", LIEF::assembly::riscv::OPCODE::PseudoFSW) + .value("PseudoJump", LIEF::assembly::riscv::OPCODE::PseudoJump) + .value("PseudoLA", LIEF::assembly::riscv::OPCODE::PseudoLA) + .value("PseudoLAImm", LIEF::assembly::riscv::OPCODE::PseudoLAImm) + .value("PseudoLA_TLSDESC", LIEF::assembly::riscv::OPCODE::PseudoLA_TLSDESC) + .value("PseudoLA_TLS_GD", LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_GD) + .value("PseudoLA_TLS_IE", LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_IE) + .value("PseudoLB", LIEF::assembly::riscv::OPCODE::PseudoLB) + .value("PseudoLBU", LIEF::assembly::riscv::OPCODE::PseudoLBU) + .value("PseudoLD", LIEF::assembly::riscv::OPCODE::PseudoLD) + .value("PseudoLD_RV32", LIEF::assembly::riscv::OPCODE::PseudoLD_RV32) + .value("PseudoLD_RV32_OPT", LIEF::assembly::riscv::OPCODE::PseudoLD_RV32_OPT) + .value("PseudoLGA", LIEF::assembly::riscv::OPCODE::PseudoLGA) + .value("PseudoLH", LIEF::assembly::riscv::OPCODE::PseudoLH) + .value("PseudoLHU", LIEF::assembly::riscv::OPCODE::PseudoLHU) + .value("PseudoLI", LIEF::assembly::riscv::OPCODE::PseudoLI) + .value("PseudoLLA", LIEF::assembly::riscv::OPCODE::PseudoLLA) + .value("PseudoLLAImm", LIEF::assembly::riscv::OPCODE::PseudoLLAImm) + .value("PseudoLW", LIEF::assembly::riscv::OPCODE::PseudoLW) + .value("PseudoLWU", LIEF::assembly::riscv::OPCODE::PseudoLWU) + .value("PseudoLongBEQ", LIEF::assembly::riscv::OPCODE::PseudoLongBEQ) + .value("PseudoLongBEQI", LIEF::assembly::riscv::OPCODE::PseudoLongBEQI) + .value("PseudoLongBGE", LIEF::assembly::riscv::OPCODE::PseudoLongBGE) + .value("PseudoLongBGEU", LIEF::assembly::riscv::OPCODE::PseudoLongBGEU) + .value("PseudoLongBLT", LIEF::assembly::riscv::OPCODE::PseudoLongBLT) + .value("PseudoLongBLTU", LIEF::assembly::riscv::OPCODE::PseudoLongBLTU) + .value("PseudoLongBNE", LIEF::assembly::riscv::OPCODE::PseudoLongBNE) + .value("PseudoLongBNEI", LIEF::assembly::riscv::OPCODE::PseudoLongBNEI) + .value("PseudoLongQC_BEQI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BEQI) + .value("PseudoLongQC_BGEI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BGEI) + .value("PseudoLongQC_BGEUI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BGEUI) + .value("PseudoLongQC_BLTI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BLTI) + .value("PseudoLongQC_BLTUI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BLTUI) + .value("PseudoLongQC_BNEI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_BNEI) + .value("PseudoLongQC_E_BEQI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BEQI) + .value("PseudoLongQC_E_BGEI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BGEI) + .value("PseudoLongQC_E_BGEUI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BGEUI) + .value("PseudoLongQC_E_BLTI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BLTI) + .value("PseudoLongQC_E_BLTUI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BLTUI) + .value("PseudoLongQC_E_BNEI", LIEF::assembly::riscv::OPCODE::PseudoLongQC_E_BNEI) + .value("PseudoMOP_C_SSPUSH", LIEF::assembly::riscv::OPCODE::PseudoMOP_C_SSPUSH) + .value("PseudoMOP_SSPOPCHK", LIEF::assembly::riscv::OPCODE::PseudoMOP_SSPOPCHK) + .value("PseudoMOP_SSPUSH", LIEF::assembly::riscv::OPCODE::PseudoMOP_SSPUSH) + .value("PseudoMV_FPR16INX", LIEF::assembly::riscv::OPCODE::PseudoMV_FPR16INX) + .value("PseudoMV_FPR32INX", LIEF::assembly::riscv::OPCODE::PseudoMV_FPR32INX) + .value("PseudoMaskedAtomicLoadAdd32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadAdd32) + .value("PseudoMaskedAtomicLoadMax32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMax32) + .value("PseudoMaskedAtomicLoadMin32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMin32) + .value("PseudoMaskedAtomicLoadNand32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadNand32) + .value("PseudoMaskedAtomicLoadSub32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadSub32) + .value("PseudoMaskedAtomicLoadUMax32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMax32) + .value("PseudoMaskedAtomicLoadUMin32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMin32) + .value("PseudoMaskedAtomicSwap32", LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicSwap32) + .value("PseudoMaskedCmpXchg32", LIEF::assembly::riscv::OPCODE::PseudoMaskedCmpXchg32) + .value("PseudoMovAddr", LIEF::assembly::riscv::OPCODE::PseudoMovAddr) + .value("PseudoMovImm", LIEF::assembly::riscv::OPCODE::PseudoMovImm) + .value("PseudoNDS_VD4DOTSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M1) + .value("PseudoNDS_VD4DOTSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M1_MASK) + .value("PseudoNDS_VD4DOTSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M2) + .value("PseudoNDS_VD4DOTSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M2_MASK) + .value("PseudoNDS_VD4DOTSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M4) + .value("PseudoNDS_VD4DOTSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M4_MASK) + .value("PseudoNDS_VD4DOTSU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M8) + .value("PseudoNDS_VD4DOTSU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_M8_MASK) + .value("PseudoNDS_VD4DOTSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_MF2) + .value("PseudoNDS_VD4DOTSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTSU_VV_MF2_MASK) + .value("PseudoNDS_VD4DOTS_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M1) + .value("PseudoNDS_VD4DOTS_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M1_MASK) + .value("PseudoNDS_VD4DOTS_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M2) + .value("PseudoNDS_VD4DOTS_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M2_MASK) + .value("PseudoNDS_VD4DOTS_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M4) + .value("PseudoNDS_VD4DOTS_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M4_MASK) + .value("PseudoNDS_VD4DOTS_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M8) + .value("PseudoNDS_VD4DOTS_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_M8_MASK) + .value("PseudoNDS_VD4DOTS_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_MF2) + .value("PseudoNDS_VD4DOTS_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTS_VV_MF2_MASK) + .value("PseudoNDS_VD4DOTU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M1) + .value("PseudoNDS_VD4DOTU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M1_MASK) + .value("PseudoNDS_VD4DOTU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M2) + .value("PseudoNDS_VD4DOTU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M2_MASK) + .value("PseudoNDS_VD4DOTU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M4) + .value("PseudoNDS_VD4DOTU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M4_MASK) + .value("PseudoNDS_VD4DOTU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M8) + .value("PseudoNDS_VD4DOTU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_M8_MASK) + .value("PseudoNDS_VD4DOTU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_MF2) + .value("PseudoNDS_VD4DOTU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VD4DOTU_VV_MF2_MASK) + .value("PseudoNDS_VFNCVT_BF16_S_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFNCVT_BF16_S_M1) + .value("PseudoNDS_VFNCVT_BF16_S_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFNCVT_BF16_S_M2) + .value("PseudoNDS_VFNCVT_BF16_S_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFNCVT_BF16_S_M4) + .value("PseudoNDS_VFNCVT_BF16_S_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFNCVT_BF16_S_MF2) + .value("PseudoNDS_VFNCVT_BF16_S_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFNCVT_BF16_S_MF4) + .value("PseudoNDS_VFPMADB_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M1) + .value("PseudoNDS_VFPMADB_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M1_MASK) + .value("PseudoNDS_VFPMADB_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M2) + .value("PseudoNDS_VFPMADB_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M2_MASK) + .value("PseudoNDS_VFPMADB_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M4) + .value("PseudoNDS_VFPMADB_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M4_MASK) + .value("PseudoNDS_VFPMADB_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M8) + .value("PseudoNDS_VFPMADB_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_M8_MASK) + .value("PseudoNDS_VFPMADB_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_MF2) + .value("PseudoNDS_VFPMADB_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_MF2_MASK) + .value("PseudoNDS_VFPMADB_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_MF4) + .value("PseudoNDS_VFPMADB_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADB_VFPR16_MF4_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M1) + .value("PseudoNDS_VFPMADT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M1_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M2) + .value("PseudoNDS_VFPMADT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M2_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M4) + .value("PseudoNDS_VFPMADT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M4_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M8) + .value("PseudoNDS_VFPMADT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_M8_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_MF2) + .value("PseudoNDS_VFPMADT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_MF2_MASK) + .value("PseudoNDS_VFPMADT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_MF4) + .value("PseudoNDS_VFPMADT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFPMADT_VFPR16_MF4_MASK) + .value("PseudoNDS_VFWCVT_S_BF16_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFWCVT_S_BF16_M1) + .value("PseudoNDS_VFWCVT_S_BF16_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFWCVT_S_BF16_M2) + .value("PseudoNDS_VFWCVT_S_BF16_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFWCVT_S_BF16_M4) + .value("PseudoNDS_VFWCVT_S_BF16_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFWCVT_S_BF16_MF2) + .value("PseudoNDS_VFWCVT_S_BF16_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VFWCVT_S_BF16_MF4) + .value("PseudoNDS_VLN8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M1) + .value("PseudoNDS_VLN8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M1_MASK) + .value("PseudoNDS_VLN8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M2) + .value("PseudoNDS_VLN8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M2_MASK) + .value("PseudoNDS_VLN8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M4) + .value("PseudoNDS_VLN8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M4_MASK) + .value("PseudoNDS_VLN8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M8) + .value("PseudoNDS_VLN8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_M8_MASK) + .value("PseudoNDS_VLN8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF2) + .value("PseudoNDS_VLN8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF2_MASK) + .value("PseudoNDS_VLN8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF4) + .value("PseudoNDS_VLN8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF4_MASK) + .value("PseudoNDS_VLN8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF8) + .value("PseudoNDS_VLN8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLN8_V_MF8_MASK) + .value("PseudoNDS_VLNU8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M1) + .value("PseudoNDS_VLNU8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M1_MASK) + .value("PseudoNDS_VLNU8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M2) + .value("PseudoNDS_VLNU8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M2_MASK) + .value("PseudoNDS_VLNU8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M4) + .value("PseudoNDS_VLNU8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M4_MASK) + .value("PseudoNDS_VLNU8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M8) + .value("PseudoNDS_VLNU8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_M8_MASK) + .value("PseudoNDS_VLNU8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF2) + .value("PseudoNDS_VLNU8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF2_MASK) + .value("PseudoNDS_VLNU8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF4) + .value("PseudoNDS_VLNU8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF4_MASK) + .value("PseudoNDS_VLNU8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF8); + opcodes.value("PseudoNDS_VLNU8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoNDS_VLNU8_V_MF8_MASK) + .value("PseudoQC_E_LB", LIEF::assembly::riscv::OPCODE::PseudoQC_E_LB) + .value("PseudoQC_E_LBU", LIEF::assembly::riscv::OPCODE::PseudoQC_E_LBU) + .value("PseudoQC_E_LH", LIEF::assembly::riscv::OPCODE::PseudoQC_E_LH) + .value("PseudoQC_E_LHU", LIEF::assembly::riscv::OPCODE::PseudoQC_E_LHU) + .value("PseudoQC_E_LW", LIEF::assembly::riscv::OPCODE::PseudoQC_E_LW) + .value("PseudoQC_E_SB", LIEF::assembly::riscv::OPCODE::PseudoQC_E_SB) + .value("PseudoQC_E_SH", LIEF::assembly::riscv::OPCODE::PseudoQC_E_SH) + .value("PseudoQC_E_SW", LIEF::assembly::riscv::OPCODE::PseudoQC_E_SW) + .value("PseudoQuietFLE_D", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D) + .value("PseudoQuietFLE_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_IN32X) + .value("PseudoQuietFLE_D_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_INX) + .value("PseudoQuietFLE_H", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H) + .value("PseudoQuietFLE_H_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H_INX) + .value("PseudoQuietFLE_S", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S) + .value("PseudoQuietFLE_S_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S_INX) + .value("PseudoQuietFLT_D", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D) + .value("PseudoQuietFLT_D_IN32X", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_IN32X) + .value("PseudoQuietFLT_D_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_INX) + .value("PseudoQuietFLT_H", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H) + .value("PseudoQuietFLT_H_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H_INX) + .value("PseudoQuietFLT_S", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S) + .value("PseudoQuietFLT_S_INX", LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S_INX) + .value("PseudoRET", LIEF::assembly::riscv::OPCODE::PseudoRET) + .value("PseudoRI_VEXTRACT_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_M1) + .value("PseudoRI_VEXTRACT_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_M2) + .value("PseudoRI_VEXTRACT_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_M4) + .value("PseudoRI_VEXTRACT_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_M8) + .value("PseudoRI_VEXTRACT_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_MF2) + .value("PseudoRI_VEXTRACT_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_MF4) + .value("PseudoRI_VEXTRACT_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VEXTRACT_MF8) + .value("PseudoRI_VINSERT_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_M1) + .value("PseudoRI_VINSERT_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_M2) + .value("PseudoRI_VINSERT_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_M4) + .value("PseudoRI_VINSERT_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_M8) + .value("PseudoRI_VINSERT_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_MF2) + .value("PseudoRI_VINSERT_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_MF4) + .value("PseudoRI_VINSERT_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VINSERT_MF8) + .value("PseudoRI_VUNZIP2A_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M1) + .value("PseudoRI_VUNZIP2A_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M1_MASK) + .value("PseudoRI_VUNZIP2A_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M2) + .value("PseudoRI_VUNZIP2A_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M2_MASK) + .value("PseudoRI_VUNZIP2A_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M4) + .value("PseudoRI_VUNZIP2A_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M4_MASK) + .value("PseudoRI_VUNZIP2A_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M8) + .value("PseudoRI_VUNZIP2A_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_M8_MASK) + .value("PseudoRI_VUNZIP2A_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF2) + .value("PseudoRI_VUNZIP2A_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF2_MASK) + .value("PseudoRI_VUNZIP2A_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF4) + .value("PseudoRI_VUNZIP2A_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF4_MASK) + .value("PseudoRI_VUNZIP2A_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF8) + .value("PseudoRI_VUNZIP2A_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2A_VV_MF8_MASK) + .value("PseudoRI_VUNZIP2B_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M1) + .value("PseudoRI_VUNZIP2B_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M1_MASK) + .value("PseudoRI_VUNZIP2B_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M2) + .value("PseudoRI_VUNZIP2B_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M2_MASK) + .value("PseudoRI_VUNZIP2B_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M4) + .value("PseudoRI_VUNZIP2B_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M4_MASK) + .value("PseudoRI_VUNZIP2B_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M8) + .value("PseudoRI_VUNZIP2B_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_M8_MASK) + .value("PseudoRI_VUNZIP2B_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF2) + .value("PseudoRI_VUNZIP2B_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF2_MASK) + .value("PseudoRI_VUNZIP2B_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF4) + .value("PseudoRI_VUNZIP2B_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF4_MASK) + .value("PseudoRI_VUNZIP2B_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF8) + .value("PseudoRI_VUNZIP2B_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VUNZIP2B_VV_MF8_MASK) + .value("PseudoRI_VZIP2A_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M1) + .value("PseudoRI_VZIP2A_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M1_MASK) + .value("PseudoRI_VZIP2A_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M2) + .value("PseudoRI_VZIP2A_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M2_MASK) + .value("PseudoRI_VZIP2A_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M4) + .value("PseudoRI_VZIP2A_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M4_MASK) + .value("PseudoRI_VZIP2A_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M8) + .value("PseudoRI_VZIP2A_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_M8_MASK) + .value("PseudoRI_VZIP2A_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF2) + .value("PseudoRI_VZIP2A_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF2_MASK) + .value("PseudoRI_VZIP2A_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF4) + .value("PseudoRI_VZIP2A_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF4_MASK) + .value("PseudoRI_VZIP2A_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF8) + .value("PseudoRI_VZIP2A_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2A_VV_MF8_MASK) + .value("PseudoRI_VZIP2B_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M1) + .value("PseudoRI_VZIP2B_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M1_MASK) + .value("PseudoRI_VZIP2B_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M2) + .value("PseudoRI_VZIP2B_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M2_MASK) + .value("PseudoRI_VZIP2B_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M4) + .value("PseudoRI_VZIP2B_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M4_MASK) + .value("PseudoRI_VZIP2B_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M8) + .value("PseudoRI_VZIP2B_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_M8_MASK) + .value("PseudoRI_VZIP2B_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF2) + .value("PseudoRI_VZIP2B_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF2_MASK) + .value("PseudoRI_VZIP2B_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF4) + .value("PseudoRI_VZIP2B_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF4_MASK) + .value("PseudoRI_VZIP2B_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF8) + .value("PseudoRI_VZIP2B_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIP2B_VV_MF8_MASK) + .value("PseudoRI_VZIPEVEN_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M1) + .value("PseudoRI_VZIPEVEN_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M1_MASK) + .value("PseudoRI_VZIPEVEN_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M2) + .value("PseudoRI_VZIPEVEN_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M2_MASK) + .value("PseudoRI_VZIPEVEN_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M4) + .value("PseudoRI_VZIPEVEN_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M4_MASK) + .value("PseudoRI_VZIPEVEN_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M8) + .value("PseudoRI_VZIPEVEN_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_M8_MASK) + .value("PseudoRI_VZIPEVEN_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF2) + .value("PseudoRI_VZIPEVEN_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF2_MASK) + .value("PseudoRI_VZIPEVEN_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF4) + .value("PseudoRI_VZIPEVEN_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF4_MASK) + .value("PseudoRI_VZIPEVEN_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF8) + .value("PseudoRI_VZIPEVEN_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPEVEN_VV_MF8_MASK) + .value("PseudoRI_VZIPODD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M1) + .value("PseudoRI_VZIPODD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M1_MASK) + .value("PseudoRI_VZIPODD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M2) + .value("PseudoRI_VZIPODD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M2_MASK) + .value("PseudoRI_VZIPODD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M4) + .value("PseudoRI_VZIPODD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M4_MASK) + .value("PseudoRI_VZIPODD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M8) + .value("PseudoRI_VZIPODD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_M8_MASK) + .value("PseudoRI_VZIPODD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF2) + .value("PseudoRI_VZIPODD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF2_MASK) + .value("PseudoRI_VZIPODD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF4) + .value("PseudoRI_VZIPODD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF4_MASK) + .value("PseudoRI_VZIPODD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF8) + .value("PseudoRI_VZIPODD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoRI_VZIPODD_VV_MF8_MASK) + .value("PseudoRV32ZdinxLD", LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxLD) + .value("PseudoRV32ZdinxSD", LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxSD) + .value("PseudoReadVL", LIEF::assembly::riscv::OPCODE::PseudoReadVL) + .value("PseudoReadVLENB", LIEF::assembly::riscv::OPCODE::PseudoReadVLENB) + .value("PseudoReadVLENBViaVSETVLIX0", LIEF::assembly::riscv::OPCODE::PseudoReadVLENBViaVSETVLIX0) + .value("PseudoSB", LIEF::assembly::riscv::OPCODE::PseudoSB) + .value("PseudoSD", LIEF::assembly::riscv::OPCODE::PseudoSD) + .value("PseudoSD_RV32", LIEF::assembly::riscv::OPCODE::PseudoSD_RV32) + .value("PseudoSD_RV32_OPT", LIEF::assembly::riscv::OPCODE::PseudoSD_RV32_OPT) + .value("PseudoSEXT_B", LIEF::assembly::riscv::OPCODE::PseudoSEXT_B) + .value("PseudoSEXT_H", LIEF::assembly::riscv::OPCODE::PseudoSEXT_H) + .value("PseudoSF_MM_E4M3_E4M3", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_E4M3_E4M3) + .value("PseudoSF_MM_E4M3_E5M2", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_E4M3_E5M2) + .value("PseudoSF_MM_E5M2_E4M3", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_E5M2_E4M3) + .value("PseudoSF_MM_E5M2_E5M2", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_E5M2_E5M2) + .value("PseudoSF_MM_F_F", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_F_F) + .value("PseudoSF_MM_F_F_ALT", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_F_F_ALT) + .value("PseudoSF_MM_S_S", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_S_S) + .value("PseudoSF_MM_S_U", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_S_U) + .value("PseudoSF_MM_U_S", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_U_S) + .value("PseudoSF_MM_U_U", LIEF::assembly::riscv::OPCODE::PseudoSF_MM_U_U) + .value("PseudoSF_VC_FPR16VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_M1) + .value("PseudoSF_VC_FPR16VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_M2) + .value("PseudoSF_VC_FPR16VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_M4) + .value("PseudoSF_VC_FPR16VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_M8) + .value("PseudoSF_VC_FPR16VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_MF2) + .value("PseudoSF_VC_FPR16VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VV_SE_MF4) + .value("PseudoSF_VC_FPR16VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_M1) + .value("PseudoSF_VC_FPR16VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_M2) + .value("PseudoSF_VC_FPR16VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_M4) + .value("PseudoSF_VC_FPR16VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_M8) + .value("PseudoSF_VC_FPR16VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_MF2) + .value("PseudoSF_VC_FPR16VW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16VW_SE_MF4) + .value("PseudoSF_VC_FPR16V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_M1) + .value("PseudoSF_VC_FPR16V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_M2) + .value("PseudoSF_VC_FPR16V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_M4) + .value("PseudoSF_VC_FPR16V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_M8) + .value("PseudoSF_VC_FPR16V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_MF2) + .value("PseudoSF_VC_FPR16V_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR16V_SE_MF4) + .value("PseudoSF_VC_FPR32VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VV_SE_M1) + .value("PseudoSF_VC_FPR32VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VV_SE_M2) + .value("PseudoSF_VC_FPR32VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VV_SE_M4) + .value("PseudoSF_VC_FPR32VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VV_SE_M8) + .value("PseudoSF_VC_FPR32VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VV_SE_MF2) + .value("PseudoSF_VC_FPR32VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VW_SE_M1) + .value("PseudoSF_VC_FPR32VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VW_SE_M2) + .value("PseudoSF_VC_FPR32VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VW_SE_M4) + .value("PseudoSF_VC_FPR32VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VW_SE_M8) + .value("PseudoSF_VC_FPR32VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32VW_SE_MF2) + .value("PseudoSF_VC_FPR32V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32V_SE_M1) + .value("PseudoSF_VC_FPR32V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32V_SE_M2) + .value("PseudoSF_VC_FPR32V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32V_SE_M4) + .value("PseudoSF_VC_FPR32V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32V_SE_M8) + .value("PseudoSF_VC_FPR32V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR32V_SE_MF2) + .value("PseudoSF_VC_FPR64VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64VV_SE_M1) + .value("PseudoSF_VC_FPR64VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64VV_SE_M2) + .value("PseudoSF_VC_FPR64VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64VV_SE_M4) + .value("PseudoSF_VC_FPR64VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64VV_SE_M8) + .value("PseudoSF_VC_FPR64V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64V_SE_M1) + .value("PseudoSF_VC_FPR64V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64V_SE_M2) + .value("PseudoSF_VC_FPR64V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64V_SE_M4) + .value("PseudoSF_VC_FPR64V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_FPR64V_SE_M8) + .value("PseudoSF_VC_IVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_M1) + .value("PseudoSF_VC_IVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_M2) + .value("PseudoSF_VC_IVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_M4) + .value("PseudoSF_VC_IVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_M8) + .value("PseudoSF_VC_IVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_MF2) + .value("PseudoSF_VC_IVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_MF4) + .value("PseudoSF_VC_IVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVV_SE_MF8) + .value("PseudoSF_VC_IVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_M1) + .value("PseudoSF_VC_IVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_M2) + .value("PseudoSF_VC_IVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_M4) + .value("PseudoSF_VC_IVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_MF2) + .value("PseudoSF_VC_IVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_MF4) + .value("PseudoSF_VC_IVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IVW_SE_MF8) + .value("PseudoSF_VC_IV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_M1) + .value("PseudoSF_VC_IV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_M2) + .value("PseudoSF_VC_IV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_M4) + .value("PseudoSF_VC_IV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_M8) + .value("PseudoSF_VC_IV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_MF2) + .value("PseudoSF_VC_IV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_MF4) + .value("PseudoSF_VC_IV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_IV_SE_MF8) + .value("PseudoSF_VC_I_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_M1) + .value("PseudoSF_VC_I_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_M2) + .value("PseudoSF_VC_I_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_M4) + .value("PseudoSF_VC_I_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_M8) + .value("PseudoSF_VC_I_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_MF2) + .value("PseudoSF_VC_I_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_MF4) + .value("PseudoSF_VC_I_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_I_SE_MF8) + .value("PseudoSF_VC_VVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_M1) + .value("PseudoSF_VC_VVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_M2) + .value("PseudoSF_VC_VVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_M4) + .value("PseudoSF_VC_VVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_M8) + .value("PseudoSF_VC_VVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_MF2) + .value("PseudoSF_VC_VVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_MF4) + .value("PseudoSF_VC_VVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVV_SE_MF8) + .value("PseudoSF_VC_VVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_M1) + .value("PseudoSF_VC_VVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_M2) + .value("PseudoSF_VC_VVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_M4) + .value("PseudoSF_VC_VVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_MF2) + .value("PseudoSF_VC_VVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_MF4) + .value("PseudoSF_VC_VVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VVW_SE_MF8) + .value("PseudoSF_VC_VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_M1) + .value("PseudoSF_VC_VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_M2) + .value("PseudoSF_VC_VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_M4) + .value("PseudoSF_VC_VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_M8) + .value("PseudoSF_VC_VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_MF2) + .value("PseudoSF_VC_VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_MF4) + .value("PseudoSF_VC_VV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_VV_SE_MF8) + .value("PseudoSF_VC_V_FPR16VV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_M1) + .value("PseudoSF_VC_V_FPR16VV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_M2) + .value("PseudoSF_VC_V_FPR16VV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_M4) + .value("PseudoSF_VC_V_FPR16VV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_M8) + .value("PseudoSF_VC_V_FPR16VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_MF2) + .value("PseudoSF_VC_V_FPR16VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_MF4) + .value("PseudoSF_VC_V_FPR16VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_M1) + .value("PseudoSF_VC_V_FPR16VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_M2) + .value("PseudoSF_VC_V_FPR16VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_M4) + .value("PseudoSF_VC_V_FPR16VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_M8) + .value("PseudoSF_VC_V_FPR16VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_MF2) + .value("PseudoSF_VC_V_FPR16VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VV_SE_MF4) + .value("PseudoSF_VC_V_FPR16VW_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_M1) + .value("PseudoSF_VC_V_FPR16VW_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_M2) + .value("PseudoSF_VC_V_FPR16VW_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_M4) + .value("PseudoSF_VC_V_FPR16VW_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_M8) + .value("PseudoSF_VC_V_FPR16VW_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_MF2) + .value("PseudoSF_VC_V_FPR16VW_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_MF4) + .value("PseudoSF_VC_V_FPR16VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_M1) + .value("PseudoSF_VC_V_FPR16VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_M2) + .value("PseudoSF_VC_V_FPR16VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_M4) + .value("PseudoSF_VC_V_FPR16VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_M8) + .value("PseudoSF_VC_V_FPR16VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_MF2) + .value("PseudoSF_VC_V_FPR16VW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16VW_SE_MF4) + .value("PseudoSF_VC_V_FPR16V_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_M1) + .value("PseudoSF_VC_V_FPR16V_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_M2) + .value("PseudoSF_VC_V_FPR16V_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_M4) + .value("PseudoSF_VC_V_FPR16V_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_M8) + .value("PseudoSF_VC_V_FPR16V_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_MF2) + .value("PseudoSF_VC_V_FPR16V_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_MF4) + .value("PseudoSF_VC_V_FPR16V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_M1) + .value("PseudoSF_VC_V_FPR16V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_M2) + .value("PseudoSF_VC_V_FPR16V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_M4) + .value("PseudoSF_VC_V_FPR16V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_M8) + .value("PseudoSF_VC_V_FPR16V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_MF2) + .value("PseudoSF_VC_V_FPR16V_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR16V_SE_MF4) + .value("PseudoSF_VC_V_FPR32VV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_M1) + .value("PseudoSF_VC_V_FPR32VV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_M2) + .value("PseudoSF_VC_V_FPR32VV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_M4) + .value("PseudoSF_VC_V_FPR32VV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_M8) + .value("PseudoSF_VC_V_FPR32VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_MF2) + .value("PseudoSF_VC_V_FPR32VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_SE_M1) + .value("PseudoSF_VC_V_FPR32VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_SE_M2) + .value("PseudoSF_VC_V_FPR32VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_SE_M4) + .value("PseudoSF_VC_V_FPR32VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_SE_M8) + .value("PseudoSF_VC_V_FPR32VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VV_SE_MF2) + .value("PseudoSF_VC_V_FPR32VW_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_M1) + .value("PseudoSF_VC_V_FPR32VW_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_M2) + .value("PseudoSF_VC_V_FPR32VW_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_M4) + .value("PseudoSF_VC_V_FPR32VW_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_M8) + .value("PseudoSF_VC_V_FPR32VW_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_MF2) + .value("PseudoSF_VC_V_FPR32VW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_SE_M1) + .value("PseudoSF_VC_V_FPR32VW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_SE_M2) + .value("PseudoSF_VC_V_FPR32VW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_SE_M4) + .value("PseudoSF_VC_V_FPR32VW_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_SE_M8) + .value("PseudoSF_VC_V_FPR32VW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32VW_SE_MF2) + .value("PseudoSF_VC_V_FPR32V_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_M1) + .value("PseudoSF_VC_V_FPR32V_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_M2) + .value("PseudoSF_VC_V_FPR32V_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_M4) + .value("PseudoSF_VC_V_FPR32V_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_M8) + .value("PseudoSF_VC_V_FPR32V_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_MF2) + .value("PseudoSF_VC_V_FPR32V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_SE_M1) + .value("PseudoSF_VC_V_FPR32V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_SE_M2) + .value("PseudoSF_VC_V_FPR32V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_SE_M4) + .value("PseudoSF_VC_V_FPR32V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_SE_M8) + .value("PseudoSF_VC_V_FPR32V_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR32V_SE_MF2) + .value("PseudoSF_VC_V_FPR64VV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_M1) + .value("PseudoSF_VC_V_FPR64VV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_M2) + .value("PseudoSF_VC_V_FPR64VV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_M4); + opcodes.value("PseudoSF_VC_V_FPR64VV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_M8) + .value("PseudoSF_VC_V_FPR64VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_SE_M1) + .value("PseudoSF_VC_V_FPR64VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_SE_M2) + .value("PseudoSF_VC_V_FPR64VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_SE_M4) + .value("PseudoSF_VC_V_FPR64VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64VV_SE_M8) + .value("PseudoSF_VC_V_FPR64V_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_M1) + .value("PseudoSF_VC_V_FPR64V_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_M2) + .value("PseudoSF_VC_V_FPR64V_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_M4) + .value("PseudoSF_VC_V_FPR64V_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_M8) + .value("PseudoSF_VC_V_FPR64V_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_SE_M1) + .value("PseudoSF_VC_V_FPR64V_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_SE_M2) + .value("PseudoSF_VC_V_FPR64V_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_SE_M4) + .value("PseudoSF_VC_V_FPR64V_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_FPR64V_SE_M8) + .value("PseudoSF_VC_V_IVV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_M1) + .value("PseudoSF_VC_V_IVV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_M2) + .value("PseudoSF_VC_V_IVV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_M4) + .value("PseudoSF_VC_V_IVV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_M8) + .value("PseudoSF_VC_V_IVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_MF2) + .value("PseudoSF_VC_V_IVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_MF4) + .value("PseudoSF_VC_V_IVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_MF8) + .value("PseudoSF_VC_V_IVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_M1) + .value("PseudoSF_VC_V_IVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_M2) + .value("PseudoSF_VC_V_IVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_M4) + .value("PseudoSF_VC_V_IVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_M8) + .value("PseudoSF_VC_V_IVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_MF2) + .value("PseudoSF_VC_V_IVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_MF4) + .value("PseudoSF_VC_V_IVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVV_SE_MF8) + .value("PseudoSF_VC_V_IVW_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_M1) + .value("PseudoSF_VC_V_IVW_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_M2) + .value("PseudoSF_VC_V_IVW_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_M4) + .value("PseudoSF_VC_V_IVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_MF2) + .value("PseudoSF_VC_V_IVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_MF4) + .value("PseudoSF_VC_V_IVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_MF8) + .value("PseudoSF_VC_V_IVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_M1) + .value("PseudoSF_VC_V_IVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_M2) + .value("PseudoSF_VC_V_IVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_M4) + .value("PseudoSF_VC_V_IVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_MF2) + .value("PseudoSF_VC_V_IVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_MF4) + .value("PseudoSF_VC_V_IVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IVW_SE_MF8) + .value("PseudoSF_VC_V_IV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_M1) + .value("PseudoSF_VC_V_IV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_M2) + .value("PseudoSF_VC_V_IV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_M4) + .value("PseudoSF_VC_V_IV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_M8) + .value("PseudoSF_VC_V_IV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_MF2) + .value("PseudoSF_VC_V_IV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_MF4) + .value("PseudoSF_VC_V_IV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_MF8) + .value("PseudoSF_VC_V_IV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_M1) + .value("PseudoSF_VC_V_IV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_M2) + .value("PseudoSF_VC_V_IV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_M4) + .value("PseudoSF_VC_V_IV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_M8) + .value("PseudoSF_VC_V_IV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_MF2) + .value("PseudoSF_VC_V_IV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_MF4) + .value("PseudoSF_VC_V_IV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_IV_SE_MF8) + .value("PseudoSF_VC_V_I_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_M1) + .value("PseudoSF_VC_V_I_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_M2) + .value("PseudoSF_VC_V_I_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_M4) + .value("PseudoSF_VC_V_I_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_M8) + .value("PseudoSF_VC_V_I_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_MF2) + .value("PseudoSF_VC_V_I_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_MF4) + .value("PseudoSF_VC_V_I_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_MF8) + .value("PseudoSF_VC_V_I_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_M1) + .value("PseudoSF_VC_V_I_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_M2) + .value("PseudoSF_VC_V_I_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_M4) + .value("PseudoSF_VC_V_I_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_M8) + .value("PseudoSF_VC_V_I_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_MF2) + .value("PseudoSF_VC_V_I_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_MF4) + .value("PseudoSF_VC_V_I_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_I_SE_MF8) + .value("PseudoSF_VC_V_VVV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_M1) + .value("PseudoSF_VC_V_VVV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_M2) + .value("PseudoSF_VC_V_VVV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_M4) + .value("PseudoSF_VC_V_VVV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_M8) + .value("PseudoSF_VC_V_VVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_MF2) + .value("PseudoSF_VC_V_VVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_MF4) + .value("PseudoSF_VC_V_VVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_MF8) + .value("PseudoSF_VC_V_VVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_M1) + .value("PseudoSF_VC_V_VVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_M2) + .value("PseudoSF_VC_V_VVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_M4) + .value("PseudoSF_VC_V_VVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_M8) + .value("PseudoSF_VC_V_VVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_MF2) + .value("PseudoSF_VC_V_VVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_MF4) + .value("PseudoSF_VC_V_VVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVV_SE_MF8) + .value("PseudoSF_VC_V_VVW_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_M1) + .value("PseudoSF_VC_V_VVW_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_M2) + .value("PseudoSF_VC_V_VVW_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_M4) + .value("PseudoSF_VC_V_VVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_MF2) + .value("PseudoSF_VC_V_VVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_MF4) + .value("PseudoSF_VC_V_VVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_MF8) + .value("PseudoSF_VC_V_VVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_M1) + .value("PseudoSF_VC_V_VVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_M2) + .value("PseudoSF_VC_V_VVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_M4) + .value("PseudoSF_VC_V_VVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_MF2) + .value("PseudoSF_VC_V_VVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_MF4) + .value("PseudoSF_VC_V_VVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VVW_SE_MF8) + .value("PseudoSF_VC_V_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_M1) + .value("PseudoSF_VC_V_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_M2) + .value("PseudoSF_VC_V_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_M4) + .value("PseudoSF_VC_V_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_M8) + .value("PseudoSF_VC_V_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_MF2) + .value("PseudoSF_VC_V_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_MF4) + .value("PseudoSF_VC_V_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_MF8) + .value("PseudoSF_VC_V_VV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_M1) + .value("PseudoSF_VC_V_VV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_M2) + .value("PseudoSF_VC_V_VV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_M4) + .value("PseudoSF_VC_V_VV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_M8) + .value("PseudoSF_VC_V_VV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_MF2) + .value("PseudoSF_VC_V_VV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_MF4) + .value("PseudoSF_VC_V_VV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_VV_SE_MF8) + .value("PseudoSF_VC_V_XVV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_M1) + .value("PseudoSF_VC_V_XVV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_M2) + .value("PseudoSF_VC_V_XVV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_M4) + .value("PseudoSF_VC_V_XVV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_M8) + .value("PseudoSF_VC_V_XVV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_MF2) + .value("PseudoSF_VC_V_XVV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_MF4) + .value("PseudoSF_VC_V_XVV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_MF8) + .value("PseudoSF_VC_V_XVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_M1) + .value("PseudoSF_VC_V_XVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_M2) + .value("PseudoSF_VC_V_XVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_M4) + .value("PseudoSF_VC_V_XVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_M8) + .value("PseudoSF_VC_V_XVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_MF2) + .value("PseudoSF_VC_V_XVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_MF4) + .value("PseudoSF_VC_V_XVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVV_SE_MF8) + .value("PseudoSF_VC_V_XVW_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_M1) + .value("PseudoSF_VC_V_XVW_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_M2) + .value("PseudoSF_VC_V_XVW_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_M4) + .value("PseudoSF_VC_V_XVW_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_MF2) + .value("PseudoSF_VC_V_XVW_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_MF4) + .value("PseudoSF_VC_V_XVW_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_MF8) + .value("PseudoSF_VC_V_XVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_M1) + .value("PseudoSF_VC_V_XVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_M2) + .value("PseudoSF_VC_V_XVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_M4) + .value("PseudoSF_VC_V_XVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_MF2) + .value("PseudoSF_VC_V_XVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_MF4) + .value("PseudoSF_VC_V_XVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XVW_SE_MF8) + .value("PseudoSF_VC_V_XV_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_M1) + .value("PseudoSF_VC_V_XV_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_M2) + .value("PseudoSF_VC_V_XV_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_M4) + .value("PseudoSF_VC_V_XV_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_M8) + .value("PseudoSF_VC_V_XV_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_MF2) + .value("PseudoSF_VC_V_XV_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_MF4) + .value("PseudoSF_VC_V_XV_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_MF8) + .value("PseudoSF_VC_V_XV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_M1) + .value("PseudoSF_VC_V_XV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_M2) + .value("PseudoSF_VC_V_XV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_M4) + .value("PseudoSF_VC_V_XV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_M8) + .value("PseudoSF_VC_V_XV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_MF2) + .value("PseudoSF_VC_V_XV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_MF4) + .value("PseudoSF_VC_V_XV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_XV_SE_MF8) + .value("PseudoSF_VC_V_X_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_M1) + .value("PseudoSF_VC_V_X_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_M2) + .value("PseudoSF_VC_V_X_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_M4) + .value("PseudoSF_VC_V_X_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_M8) + .value("PseudoSF_VC_V_X_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_MF2) + .value("PseudoSF_VC_V_X_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_MF4) + .value("PseudoSF_VC_V_X_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_MF8) + .value("PseudoSF_VC_V_X_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_M1) + .value("PseudoSF_VC_V_X_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_M2) + .value("PseudoSF_VC_V_X_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_M4) + .value("PseudoSF_VC_V_X_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_M8) + .value("PseudoSF_VC_V_X_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_MF2) + .value("PseudoSF_VC_V_X_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_MF4) + .value("PseudoSF_VC_V_X_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_V_X_SE_MF8) + .value("PseudoSF_VC_XVV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_M1) + .value("PseudoSF_VC_XVV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_M2) + .value("PseudoSF_VC_XVV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_M4) + .value("PseudoSF_VC_XVV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_M8) + .value("PseudoSF_VC_XVV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_MF2) + .value("PseudoSF_VC_XVV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_MF4) + .value("PseudoSF_VC_XVV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVV_SE_MF8) + .value("PseudoSF_VC_XVW_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_M1) + .value("PseudoSF_VC_XVW_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_M2) + .value("PseudoSF_VC_XVW_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_M4) + .value("PseudoSF_VC_XVW_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_MF2) + .value("PseudoSF_VC_XVW_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_MF4) + .value("PseudoSF_VC_XVW_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XVW_SE_MF8) + .value("PseudoSF_VC_XV_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_M1) + .value("PseudoSF_VC_XV_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_M2) + .value("PseudoSF_VC_XV_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_M4) + .value("PseudoSF_VC_XV_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_M8) + .value("PseudoSF_VC_XV_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_MF2) + .value("PseudoSF_VC_XV_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_MF4) + .value("PseudoSF_VC_XV_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_XV_SE_MF8) + .value("PseudoSF_VC_X_SE_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_M1) + .value("PseudoSF_VC_X_SE_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_M2) + .value("PseudoSF_VC_X_SE_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_M4) + .value("PseudoSF_VC_X_SE_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_M8) + .value("PseudoSF_VC_X_SE_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_MF2) + .value("PseudoSF_VC_X_SE_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_MF4) + .value("PseudoSF_VC_X_SE_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VC_X_SE_MF8) + .value("PseudoSF_VFEXPA_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E16) + .value("PseudoSF_VFEXPA_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E16_MASK) + .value("PseudoSF_VFEXPA_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E32) + .value("PseudoSF_VFEXPA_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E32_MASK) + .value("PseudoSF_VFEXPA_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E64) + .value("PseudoSF_VFEXPA_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M1_E64_MASK) + .value("PseudoSF_VFEXPA_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E16) + .value("PseudoSF_VFEXPA_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E16_MASK) + .value("PseudoSF_VFEXPA_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E32) + .value("PseudoSF_VFEXPA_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E32_MASK) + .value("PseudoSF_VFEXPA_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E64) + .value("PseudoSF_VFEXPA_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M2_E64_MASK) + .value("PseudoSF_VFEXPA_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E16) + .value("PseudoSF_VFEXPA_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E16_MASK) + .value("PseudoSF_VFEXPA_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E32) + .value("PseudoSF_VFEXPA_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E32_MASK) + .value("PseudoSF_VFEXPA_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E64) + .value("PseudoSF_VFEXPA_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M4_E64_MASK) + .value("PseudoSF_VFEXPA_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E16) + .value("PseudoSF_VFEXPA_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E16_MASK) + .value("PseudoSF_VFEXPA_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E32) + .value("PseudoSF_VFEXPA_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E32_MASK) + .value("PseudoSF_VFEXPA_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E64) + .value("PseudoSF_VFEXPA_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_M8_E64_MASK) + .value("PseudoSF_VFEXPA_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF2_E16) + .value("PseudoSF_VFEXPA_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF2_E16_MASK) + .value("PseudoSF_VFEXPA_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF2_E32) + .value("PseudoSF_VFEXPA_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF2_E32_MASK) + .value("PseudoSF_VFEXPA_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF4_E16) + .value("PseudoSF_VFEXPA_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXPA_V_MF4_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M1_E16) + .value("PseudoSF_VFEXP_ALT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M1_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M2_E16) + .value("PseudoSF_VFEXP_ALT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M2_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M4_E16) + .value("PseudoSF_VFEXP_ALT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M4_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M8_E16) + .value("PseudoSF_VFEXP_ALT_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_M8_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_MF2_E16) + .value("PseudoSF_VFEXP_ALT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_MF2_E16_MASK) + .value("PseudoSF_VFEXP_ALT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_MF4_E16) + .value("PseudoSF_VFEXP_ALT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_ALT_V_MF4_E16_MASK) + .value("PseudoSF_VFEXP_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M1_E16) + .value("PseudoSF_VFEXP_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M1_E16_MASK) + .value("PseudoSF_VFEXP_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M1_E32) + .value("PseudoSF_VFEXP_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M1_E32_MASK) + .value("PseudoSF_VFEXP_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M2_E16) + .value("PseudoSF_VFEXP_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M2_E16_MASK) + .value("PseudoSF_VFEXP_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M2_E32) + .value("PseudoSF_VFEXP_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M2_E32_MASK) + .value("PseudoSF_VFEXP_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M4_E16) + .value("PseudoSF_VFEXP_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M4_E16_MASK) + .value("PseudoSF_VFEXP_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M4_E32) + .value("PseudoSF_VFEXP_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M4_E32_MASK) + .value("PseudoSF_VFEXP_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M8_E16) + .value("PseudoSF_VFEXP_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M8_E16_MASK) + .value("PseudoSF_VFEXP_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M8_E32) + .value("PseudoSF_VFEXP_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_M8_E32_MASK) + .value("PseudoSF_VFEXP_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF2_E16) + .value("PseudoSF_VFEXP_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF2_E16_MASK) + .value("PseudoSF_VFEXP_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF2_E32) + .value("PseudoSF_VFEXP_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF2_E32_MASK) + .value("PseudoSF_VFEXP_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF4_E16) + .value("PseudoSF_VFEXP_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFEXP_V_MF4_E16_MASK) + .value("PseudoSF_VFNRCLIP_XU_F_QF_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_M1) + .value("PseudoSF_VFNRCLIP_XU_F_QF_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_M1_MASK) + .value("PseudoSF_VFNRCLIP_XU_F_QF_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_M2) + .value("PseudoSF_VFNRCLIP_XU_F_QF_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_M2_MASK) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF2) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF2_MASK) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF4) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF4_MASK) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF8) + .value("PseudoSF_VFNRCLIP_XU_F_QF_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_XU_F_QF_MF8_MASK) + .value("PseudoSF_VFNRCLIP_X_F_QF_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_M1) + .value("PseudoSF_VFNRCLIP_X_F_QF_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_M1_MASK) + .value("PseudoSF_VFNRCLIP_X_F_QF_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_M2) + .value("PseudoSF_VFNRCLIP_X_F_QF_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_M2_MASK) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF2) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF2_MASK) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF4) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF4_MASK) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF8", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF8) + .value("PseudoSF_VFNRCLIP_X_F_QF_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoSF_VFNRCLIP_X_F_QF_MF8_MASK) + .value("PseudoSF_VFWMACC_4x4x4_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VFWMACC_4x4x4_M1) + .value("PseudoSF_VFWMACC_4x4x4_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFWMACC_4x4x4_M2) + .value("PseudoSF_VFWMACC_4x4x4_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VFWMACC_4x4x4_M4) + .value("PseudoSF_VFWMACC_4x4x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VFWMACC_4x4x4_MF2) + .value("PseudoSF_VFWMACC_4x4x4_MF4", LIEF::assembly::riscv::OPCODE::PseudoSF_VFWMACC_4x4x4_MF4) + .value("PseudoSF_VLTE16", LIEF::assembly::riscv::OPCODE::PseudoSF_VLTE16) + .value("PseudoSF_VLTE32", LIEF::assembly::riscv::OPCODE::PseudoSF_VLTE32) + .value("PseudoSF_VLTE64", LIEF::assembly::riscv::OPCODE::PseudoSF_VLTE64) + .value("PseudoSF_VLTE8", LIEF::assembly::riscv::OPCODE::PseudoSF_VLTE8) + .value("PseudoSF_VQMACCSU_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_2x8x2_M1) + .value("PseudoSF_VQMACCSU_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_2x8x2_M2) + .value("PseudoSF_VQMACCSU_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_2x8x2_M4) + .value("PseudoSF_VQMACCSU_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_2x8x2_M8) + .value("PseudoSF_VQMACCSU_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_4x8x4_M1) + .value("PseudoSF_VQMACCSU_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_4x8x4_M2) + .value("PseudoSF_VQMACCSU_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_4x8x4_M4) + .value("PseudoSF_VQMACCSU_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCSU_4x8x4_MF2) + .value("PseudoSF_VQMACCUS_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_2x8x2_M1) + .value("PseudoSF_VQMACCUS_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_2x8x2_M2) + .value("PseudoSF_VQMACCUS_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_2x8x2_M4) + .value("PseudoSF_VQMACCUS_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_2x8x2_M8) + .value("PseudoSF_VQMACCUS_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_4x8x4_M1) + .value("PseudoSF_VQMACCUS_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_4x8x4_M2) + .value("PseudoSF_VQMACCUS_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_4x8x4_M4) + .value("PseudoSF_VQMACCUS_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCUS_4x8x4_MF2) + .value("PseudoSF_VQMACCU_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_2x8x2_M1) + .value("PseudoSF_VQMACCU_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_2x8x2_M2) + .value("PseudoSF_VQMACCU_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_2x8x2_M4); + opcodes.value("PseudoSF_VQMACCU_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_2x8x2_M8) + .value("PseudoSF_VQMACCU_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_4x8x4_M1) + .value("PseudoSF_VQMACCU_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_4x8x4_M2) + .value("PseudoSF_VQMACCU_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_4x8x4_M4) + .value("PseudoSF_VQMACCU_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACCU_4x8x4_MF2) + .value("PseudoSF_VQMACC_2x8x2_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_2x8x2_M1) + .value("PseudoSF_VQMACC_2x8x2_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_2x8x2_M2) + .value("PseudoSF_VQMACC_2x8x2_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_2x8x2_M4) + .value("PseudoSF_VQMACC_2x8x2_M8", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_2x8x2_M8) + .value("PseudoSF_VQMACC_4x8x4_M1", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_4x8x4_M1) + .value("PseudoSF_VQMACC_4x8x4_M2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_4x8x4_M2) + .value("PseudoSF_VQMACC_4x8x4_M4", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_4x8x4_M4) + .value("PseudoSF_VQMACC_4x8x4_MF2", LIEF::assembly::riscv::OPCODE::PseudoSF_VQMACC_4x8x4_MF2) + .value("PseudoSF_VSETTK", LIEF::assembly::riscv::OPCODE::PseudoSF_VSETTK) + .value("PseudoSF_VSETTM", LIEF::assembly::riscv::OPCODE::PseudoSF_VSETTM) + .value("PseudoSF_VSETTNT", LIEF::assembly::riscv::OPCODE::PseudoSF_VSETTNT) + .value("PseudoSF_VSETTNTX0", LIEF::assembly::riscv::OPCODE::PseudoSF_VSETTNTX0) + .value("PseudoSF_VSETTNTX0X0", LIEF::assembly::riscv::OPCODE::PseudoSF_VSETTNTX0X0) + .value("PseudoSF_VSTE16", LIEF::assembly::riscv::OPCODE::PseudoSF_VSTE16) + .value("PseudoSF_VSTE32", LIEF::assembly::riscv::OPCODE::PseudoSF_VSTE32) + .value("PseudoSF_VSTE64", LIEF::assembly::riscv::OPCODE::PseudoSF_VSTE64) + .value("PseudoSF_VSTE8", LIEF::assembly::riscv::OPCODE::PseudoSF_VSTE8) + .value("PseudoSF_VTDISCARD", LIEF::assembly::riscv::OPCODE::PseudoSF_VTDISCARD) + .value("PseudoSF_VTMV_T_V", LIEF::assembly::riscv::OPCODE::PseudoSF_VTMV_T_V) + .value("PseudoSF_VTMV_V_T", LIEF::assembly::riscv::OPCODE::PseudoSF_VTMV_V_T) + .value("PseudoSF_VTZERO_T", LIEF::assembly::riscv::OPCODE::PseudoSF_VTZERO_T) + .value("PseudoSH", LIEF::assembly::riscv::OPCODE::PseudoSH) + .value("PseudoSW", LIEF::assembly::riscv::OPCODE::PseudoSW) + .value("PseudoTAIL", LIEF::assembly::riscv::OPCODE::PseudoTAIL) + .value("PseudoTAILIndirect", LIEF::assembly::riscv::OPCODE::PseudoTAILIndirect) + .value("PseudoTAILIndirectNonX7", LIEF::assembly::riscv::OPCODE::PseudoTAILIndirectNonX7) + .value("PseudoTAILIndirectX7", LIEF::assembly::riscv::OPCODE::PseudoTAILIndirectX7) + .value("PseudoTH_VMAQASU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M1) + .value("PseudoTH_VMAQASU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M1_MASK) + .value("PseudoTH_VMAQASU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M2) + .value("PseudoTH_VMAQASU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M2_MASK) + .value("PseudoTH_VMAQASU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M4) + .value("PseudoTH_VMAQASU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M4_MASK) + .value("PseudoTH_VMAQASU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M8) + .value("PseudoTH_VMAQASU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_M8_MASK) + .value("PseudoTH_VMAQASU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_MF2) + .value("PseudoTH_VMAQASU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VV_MF2_MASK) + .value("PseudoTH_VMAQASU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M1) + .value("PseudoTH_VMAQASU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M1_MASK) + .value("PseudoTH_VMAQASU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M2) + .value("PseudoTH_VMAQASU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M2_MASK) + .value("PseudoTH_VMAQASU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M4) + .value("PseudoTH_VMAQASU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M4_MASK) + .value("PseudoTH_VMAQASU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M8) + .value("PseudoTH_VMAQASU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_M8_MASK) + .value("PseudoTH_VMAQASU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_MF2) + .value("PseudoTH_VMAQASU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQASU_VX_MF2_MASK) + .value("PseudoTH_VMAQAUS_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M1) + .value("PseudoTH_VMAQAUS_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M1_MASK) + .value("PseudoTH_VMAQAUS_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M2) + .value("PseudoTH_VMAQAUS_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M2_MASK) + .value("PseudoTH_VMAQAUS_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M4) + .value("PseudoTH_VMAQAUS_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M4_MASK) + .value("PseudoTH_VMAQAUS_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M8) + .value("PseudoTH_VMAQAUS_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_M8_MASK) + .value("PseudoTH_VMAQAUS_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_MF2) + .value("PseudoTH_VMAQAUS_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAUS_VX_MF2_MASK) + .value("PseudoTH_VMAQAU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M1) + .value("PseudoTH_VMAQAU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M1_MASK) + .value("PseudoTH_VMAQAU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M2) + .value("PseudoTH_VMAQAU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M2_MASK) + .value("PseudoTH_VMAQAU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M4) + .value("PseudoTH_VMAQAU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M4_MASK) + .value("PseudoTH_VMAQAU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M8) + .value("PseudoTH_VMAQAU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_M8_MASK) + .value("PseudoTH_VMAQAU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_MF2) + .value("PseudoTH_VMAQAU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VV_MF2_MASK) + .value("PseudoTH_VMAQAU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M1) + .value("PseudoTH_VMAQAU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M1_MASK) + .value("PseudoTH_VMAQAU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M2) + .value("PseudoTH_VMAQAU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M2_MASK) + .value("PseudoTH_VMAQAU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M4) + .value("PseudoTH_VMAQAU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M4_MASK) + .value("PseudoTH_VMAQAU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M8) + .value("PseudoTH_VMAQAU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_M8_MASK) + .value("PseudoTH_VMAQAU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_MF2) + .value("PseudoTH_VMAQAU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQAU_VX_MF2_MASK) + .value("PseudoTH_VMAQA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M1) + .value("PseudoTH_VMAQA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M1_MASK) + .value("PseudoTH_VMAQA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M2) + .value("PseudoTH_VMAQA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M2_MASK) + .value("PseudoTH_VMAQA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M4) + .value("PseudoTH_VMAQA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M4_MASK) + .value("PseudoTH_VMAQA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M8) + .value("PseudoTH_VMAQA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_M8_MASK) + .value("PseudoTH_VMAQA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_MF2) + .value("PseudoTH_VMAQA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VV_MF2_MASK) + .value("PseudoTH_VMAQA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M1) + .value("PseudoTH_VMAQA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M1_MASK) + .value("PseudoTH_VMAQA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M2) + .value("PseudoTH_VMAQA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M2_MASK) + .value("PseudoTH_VMAQA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M4) + .value("PseudoTH_VMAQA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M4_MASK) + .value("PseudoTH_VMAQA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M8) + .value("PseudoTH_VMAQA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_M8_MASK) + .value("PseudoTH_VMAQA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_MF2) + .value("PseudoTH_VMAQA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoTH_VMAQA_VX_MF2_MASK) + .value("PseudoTLSDESCCall", LIEF::assembly::riscv::OPCODE::PseudoTLSDESCCall) + .value("PseudoVAADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1) + .value("PseudoVAADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1_MASK) + .value("PseudoVAADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2) + .value("PseudoVAADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2_MASK) + .value("PseudoVAADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4) + .value("PseudoVAADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4_MASK) + .value("PseudoVAADDU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8) + .value("PseudoVAADDU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8_MASK) + .value("PseudoVAADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2) + .value("PseudoVAADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2_MASK) + .value("PseudoVAADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4) + .value("PseudoVAADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4_MASK) + .value("PseudoVAADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8) + .value("PseudoVAADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8_MASK) + .value("PseudoVAADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1) + .value("PseudoVAADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1_MASK) + .value("PseudoVAADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2) + .value("PseudoVAADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2_MASK) + .value("PseudoVAADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4) + .value("PseudoVAADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4_MASK) + .value("PseudoVAADDU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8) + .value("PseudoVAADDU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8_MASK) + .value("PseudoVAADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2) + .value("PseudoVAADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2_MASK) + .value("PseudoVAADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4) + .value("PseudoVAADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4_MASK) + .value("PseudoVAADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8) + .value("PseudoVAADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8_MASK) + .value("PseudoVAADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1) + .value("PseudoVAADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1_MASK) + .value("PseudoVAADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2) + .value("PseudoVAADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2_MASK) + .value("PseudoVAADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4) + .value("PseudoVAADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4_MASK) + .value("PseudoVAADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8) + .value("PseudoVAADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8_MASK) + .value("PseudoVAADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2) + .value("PseudoVAADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2_MASK) + .value("PseudoVAADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4) + .value("PseudoVAADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4_MASK) + .value("PseudoVAADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8) + .value("PseudoVAADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8_MASK) + .value("PseudoVAADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1) + .value("PseudoVAADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1_MASK) + .value("PseudoVAADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2) + .value("PseudoVAADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2_MASK) + .value("PseudoVAADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4) + .value("PseudoVAADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4_MASK) + .value("PseudoVAADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8) + .value("PseudoVAADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8_MASK) + .value("PseudoVAADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2) + .value("PseudoVAADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2_MASK) + .value("PseudoVAADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4) + .value("PseudoVAADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4_MASK) + .value("PseudoVAADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8) + .value("PseudoVAADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8_MASK) + .value("PseudoVADC_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M1) + .value("PseudoVADC_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M2) + .value("PseudoVADC_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M4) + .value("PseudoVADC_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M8) + .value("PseudoVADC_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF2) + .value("PseudoVADC_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF4) + .value("PseudoVADC_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF8) + .value("PseudoVADC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M1) + .value("PseudoVADC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M2) + .value("PseudoVADC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M4) + .value("PseudoVADC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M8) + .value("PseudoVADC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF2) + .value("PseudoVADC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF4) + .value("PseudoVADC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF8) + .value("PseudoVADC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M1) + .value("PseudoVADC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M2) + .value("PseudoVADC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M4) + .value("PseudoVADC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M8) + .value("PseudoVADC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF2) + .value("PseudoVADC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF4) + .value("PseudoVADC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF8) + .value("PseudoVADD_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1) + .value("PseudoVADD_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1_MASK) + .value("PseudoVADD_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2) + .value("PseudoVADD_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2_MASK) + .value("PseudoVADD_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4) + .value("PseudoVADD_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4_MASK) + .value("PseudoVADD_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8) + .value("PseudoVADD_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8_MASK) + .value("PseudoVADD_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2) + .value("PseudoVADD_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2_MASK) + .value("PseudoVADD_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4) + .value("PseudoVADD_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4_MASK) + .value("PseudoVADD_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8) + .value("PseudoVADD_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8_MASK) + .value("PseudoVADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1) + .value("PseudoVADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1_MASK) + .value("PseudoVADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2) + .value("PseudoVADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2_MASK) + .value("PseudoVADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4) + .value("PseudoVADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4_MASK) + .value("PseudoVADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8) + .value("PseudoVADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8_MASK) + .value("PseudoVADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2) + .value("PseudoVADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2_MASK) + .value("PseudoVADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4) + .value("PseudoVADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4_MASK) + .value("PseudoVADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8) + .value("PseudoVADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8_MASK) + .value("PseudoVADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1) + .value("PseudoVADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1_MASK) + .value("PseudoVADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2) + .value("PseudoVADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2_MASK) + .value("PseudoVADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4) + .value("PseudoVADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4_MASK) + .value("PseudoVADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8) + .value("PseudoVADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8_MASK) + .value("PseudoVADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2) + .value("PseudoVADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2_MASK) + .value("PseudoVADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4) + .value("PseudoVADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4_MASK) + .value("PseudoVADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8) + .value("PseudoVADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8_MASK) + .value("PseudoVAESDF_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_M1) + .value("PseudoVAESDF_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF2) + .value("PseudoVAESDF_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF4) + .value("PseudoVAESDF_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF8) + .value("PseudoVAESDF_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M1) + .value("PseudoVAESDF_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M2) + .value("PseudoVAESDF_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF2) + .value("PseudoVAESDF_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF4) + .value("PseudoVAESDF_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF8) + .value("PseudoVAESDF_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M1) + .value("PseudoVAESDF_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M2) + .value("PseudoVAESDF_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M4) + .value("PseudoVAESDF_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF2) + .value("PseudoVAESDF_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF4) + .value("PseudoVAESDF_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF8) + .value("PseudoVAESDF_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M1) + .value("PseudoVAESDF_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M2) + .value("PseudoVAESDF_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M4) + .value("PseudoVAESDF_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF2) + .value("PseudoVAESDF_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF4) + .value("PseudoVAESDF_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF8) + .value("PseudoVAESDF_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF2) + .value("PseudoVAESDF_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF4) + .value("PseudoVAESDF_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF8) + .value("PseudoVAESDF_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M1) + .value("PseudoVAESDF_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M2) + .value("PseudoVAESDF_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M4) + .value("PseudoVAESDF_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M8) + .value("PseudoVAESDF_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_MF2) + .value("PseudoVAESDM_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_M1) + .value("PseudoVAESDM_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF2) + .value("PseudoVAESDM_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF4) + .value("PseudoVAESDM_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF8) + .value("PseudoVAESDM_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M1) + .value("PseudoVAESDM_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M2) + .value("PseudoVAESDM_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF2) + .value("PseudoVAESDM_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF4) + .value("PseudoVAESDM_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF8) + .value("PseudoVAESDM_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M1) + .value("PseudoVAESDM_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M2) + .value("PseudoVAESDM_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M4) + .value("PseudoVAESDM_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF2) + .value("PseudoVAESDM_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF4) + .value("PseudoVAESDM_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF8) + .value("PseudoVAESDM_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M1) + .value("PseudoVAESDM_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M2) + .value("PseudoVAESDM_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M4) + .value("PseudoVAESDM_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF2) + .value("PseudoVAESDM_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF4) + .value("PseudoVAESDM_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF8) + .value("PseudoVAESDM_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF2) + .value("PseudoVAESDM_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF4) + .value("PseudoVAESDM_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF8) + .value("PseudoVAESDM_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M1) + .value("PseudoVAESDM_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M2) + .value("PseudoVAESDM_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M4) + .value("PseudoVAESDM_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M8) + .value("PseudoVAESDM_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_MF2) + .value("PseudoVAESEF_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_M1) + .value("PseudoVAESEF_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF2) + .value("PseudoVAESEF_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF4) + .value("PseudoVAESEF_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF8) + .value("PseudoVAESEF_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M1) + .value("PseudoVAESEF_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M2) + .value("PseudoVAESEF_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF2) + .value("PseudoVAESEF_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF4) + .value("PseudoVAESEF_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF8) + .value("PseudoVAESEF_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M1) + .value("PseudoVAESEF_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M2) + .value("PseudoVAESEF_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M4) + .value("PseudoVAESEF_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF2) + .value("PseudoVAESEF_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF4) + .value("PseudoVAESEF_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF8) + .value("PseudoVAESEF_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M1) + .value("PseudoVAESEF_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M2) + .value("PseudoVAESEF_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M4) + .value("PseudoVAESEF_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF2) + .value("PseudoVAESEF_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF4); + opcodes.value("PseudoVAESEF_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF8) + .value("PseudoVAESEF_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF2) + .value("PseudoVAESEF_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF4) + .value("PseudoVAESEF_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF8) + .value("PseudoVAESEF_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M1) + .value("PseudoVAESEF_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M2) + .value("PseudoVAESEF_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M4) + .value("PseudoVAESEF_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M8) + .value("PseudoVAESEF_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_MF2) + .value("PseudoVAESEM_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_M1) + .value("PseudoVAESEM_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF2) + .value("PseudoVAESEM_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF4) + .value("PseudoVAESEM_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF8) + .value("PseudoVAESEM_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M1) + .value("PseudoVAESEM_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M2) + .value("PseudoVAESEM_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF2) + .value("PseudoVAESEM_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF4) + .value("PseudoVAESEM_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF8) + .value("PseudoVAESEM_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M1) + .value("PseudoVAESEM_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M2) + .value("PseudoVAESEM_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M4) + .value("PseudoVAESEM_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF2) + .value("PseudoVAESEM_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF4) + .value("PseudoVAESEM_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF8) + .value("PseudoVAESEM_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M1) + .value("PseudoVAESEM_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M2) + .value("PseudoVAESEM_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M4) + .value("PseudoVAESEM_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF2) + .value("PseudoVAESEM_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF4) + .value("PseudoVAESEM_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF8) + .value("PseudoVAESEM_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF2) + .value("PseudoVAESEM_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF4) + .value("PseudoVAESEM_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF8) + .value("PseudoVAESEM_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M1) + .value("PseudoVAESEM_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M2) + .value("PseudoVAESEM_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M4) + .value("PseudoVAESEM_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M8) + .value("PseudoVAESEM_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_MF2) + .value("PseudoVAESKF1_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M1) + .value("PseudoVAESKF1_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M2) + .value("PseudoVAESKF1_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M4) + .value("PseudoVAESKF1_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M8) + .value("PseudoVAESKF1_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_MF2) + .value("PseudoVAESKF2_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M1) + .value("PseudoVAESKF2_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M2) + .value("PseudoVAESKF2_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M4) + .value("PseudoVAESKF2_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M8) + .value("PseudoVAESKF2_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_MF2) + .value("PseudoVAESZ_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_M1) + .value("PseudoVAESZ_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF2) + .value("PseudoVAESZ_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF4) + .value("PseudoVAESZ_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF8) + .value("PseudoVAESZ_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M1) + .value("PseudoVAESZ_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M2) + .value("PseudoVAESZ_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF2) + .value("PseudoVAESZ_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF4) + .value("PseudoVAESZ_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF8) + .value("PseudoVAESZ_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M1) + .value("PseudoVAESZ_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M2) + .value("PseudoVAESZ_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M4) + .value("PseudoVAESZ_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF2) + .value("PseudoVAESZ_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF4) + .value("PseudoVAESZ_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF8) + .value("PseudoVAESZ_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M1) + .value("PseudoVAESZ_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M2) + .value("PseudoVAESZ_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M4) + .value("PseudoVAESZ_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF2) + .value("PseudoVAESZ_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF4) + .value("PseudoVAESZ_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF8) + .value("PseudoVAESZ_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF2) + .value("PseudoVAESZ_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF4) + .value("PseudoVAESZ_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF8) + .value("PseudoVANDN_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1) + .value("PseudoVANDN_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1_MASK) + .value("PseudoVANDN_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2) + .value("PseudoVANDN_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2_MASK) + .value("PseudoVANDN_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4) + .value("PseudoVANDN_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4_MASK) + .value("PseudoVANDN_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8) + .value("PseudoVANDN_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8_MASK) + .value("PseudoVANDN_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2) + .value("PseudoVANDN_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2_MASK) + .value("PseudoVANDN_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4) + .value("PseudoVANDN_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4_MASK) + .value("PseudoVANDN_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8) + .value("PseudoVANDN_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8_MASK) + .value("PseudoVANDN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1) + .value("PseudoVANDN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1_MASK) + .value("PseudoVANDN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2) + .value("PseudoVANDN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2_MASK) + .value("PseudoVANDN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4) + .value("PseudoVANDN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4_MASK) + .value("PseudoVANDN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8) + .value("PseudoVANDN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8_MASK) + .value("PseudoVANDN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2) + .value("PseudoVANDN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2_MASK) + .value("PseudoVANDN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4) + .value("PseudoVANDN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4_MASK) + .value("PseudoVANDN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8) + .value("PseudoVANDN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8_MASK) + .value("PseudoVAND_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1) + .value("PseudoVAND_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1_MASK) + .value("PseudoVAND_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2) + .value("PseudoVAND_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2_MASK) + .value("PseudoVAND_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4) + .value("PseudoVAND_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4_MASK) + .value("PseudoVAND_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8) + .value("PseudoVAND_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8_MASK) + .value("PseudoVAND_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2) + .value("PseudoVAND_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2_MASK) + .value("PseudoVAND_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4) + .value("PseudoVAND_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4_MASK) + .value("PseudoVAND_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8) + .value("PseudoVAND_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8_MASK) + .value("PseudoVAND_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1) + .value("PseudoVAND_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1_MASK) + .value("PseudoVAND_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2) + .value("PseudoVAND_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2_MASK) + .value("PseudoVAND_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4) + .value("PseudoVAND_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4_MASK) + .value("PseudoVAND_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8) + .value("PseudoVAND_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8_MASK) + .value("PseudoVAND_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2) + .value("PseudoVAND_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2_MASK) + .value("PseudoVAND_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4) + .value("PseudoVAND_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4_MASK) + .value("PseudoVAND_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8) + .value("PseudoVAND_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8_MASK) + .value("PseudoVAND_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1) + .value("PseudoVAND_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1_MASK) + .value("PseudoVAND_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2) + .value("PseudoVAND_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2_MASK) + .value("PseudoVAND_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4) + .value("PseudoVAND_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4_MASK) + .value("PseudoVAND_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8) + .value("PseudoVAND_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8_MASK) + .value("PseudoVAND_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2) + .value("PseudoVAND_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2_MASK) + .value("PseudoVAND_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4) + .value("PseudoVAND_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4_MASK) + .value("PseudoVAND_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8) + .value("PseudoVAND_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8_MASK) + .value("PseudoVASUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1) + .value("PseudoVASUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1_MASK) + .value("PseudoVASUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2) + .value("PseudoVASUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2_MASK) + .value("PseudoVASUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4) + .value("PseudoVASUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4_MASK) + .value("PseudoVASUBU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8) + .value("PseudoVASUBU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8_MASK) + .value("PseudoVASUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2) + .value("PseudoVASUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2_MASK) + .value("PseudoVASUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4) + .value("PseudoVASUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4_MASK) + .value("PseudoVASUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8) + .value("PseudoVASUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8_MASK) + .value("PseudoVASUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1) + .value("PseudoVASUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1_MASK) + .value("PseudoVASUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2) + .value("PseudoVASUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2_MASK) + .value("PseudoVASUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4) + .value("PseudoVASUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4_MASK) + .value("PseudoVASUBU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8) + .value("PseudoVASUBU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8_MASK) + .value("PseudoVASUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2) + .value("PseudoVASUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2_MASK) + .value("PseudoVASUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4) + .value("PseudoVASUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4_MASK) + .value("PseudoVASUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8) + .value("PseudoVASUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8_MASK) + .value("PseudoVASUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1) + .value("PseudoVASUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1_MASK) + .value("PseudoVASUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2) + .value("PseudoVASUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2_MASK) + .value("PseudoVASUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4) + .value("PseudoVASUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4_MASK) + .value("PseudoVASUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8) + .value("PseudoVASUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8_MASK) + .value("PseudoVASUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2) + .value("PseudoVASUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2_MASK) + .value("PseudoVASUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4) + .value("PseudoVASUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4_MASK) + .value("PseudoVASUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8) + .value("PseudoVASUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8_MASK) + .value("PseudoVASUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1) + .value("PseudoVASUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1_MASK) + .value("PseudoVASUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2) + .value("PseudoVASUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2_MASK) + .value("PseudoVASUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4) + .value("PseudoVASUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4_MASK) + .value("PseudoVASUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8) + .value("PseudoVASUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8_MASK) + .value("PseudoVASUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2) + .value("PseudoVASUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2_MASK) + .value("PseudoVASUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4) + .value("PseudoVASUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4_MASK) + .value("PseudoVASUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8) + .value("PseudoVASUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8_MASK) + .value("PseudoVBREV8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1) + .value("PseudoVBREV8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1_MASK) + .value("PseudoVBREV8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2) + .value("PseudoVBREV8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2_MASK) + .value("PseudoVBREV8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4) + .value("PseudoVBREV8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4_MASK) + .value("PseudoVBREV8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8) + .value("PseudoVBREV8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8_MASK) + .value("PseudoVBREV8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2) + .value("PseudoVBREV8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2_MASK) + .value("PseudoVBREV8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4) + .value("PseudoVBREV8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4_MASK) + .value("PseudoVBREV8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8) + .value("PseudoVBREV8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8_MASK) + .value("PseudoVBREV_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1) + .value("PseudoVBREV_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1_MASK) + .value("PseudoVBREV_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2) + .value("PseudoVBREV_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2_MASK) + .value("PseudoVBREV_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4) + .value("PseudoVBREV_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4_MASK) + .value("PseudoVBREV_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8) + .value("PseudoVBREV_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8_MASK) + .value("PseudoVBREV_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2) + .value("PseudoVBREV_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2_MASK) + .value("PseudoVBREV_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4) + .value("PseudoVBREV_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4_MASK) + .value("PseudoVBREV_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8) + .value("PseudoVBREV_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8_MASK) + .value("PseudoVCLMULH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1) + .value("PseudoVCLMULH_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1_MASK) + .value("PseudoVCLMULH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2) + .value("PseudoVCLMULH_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2_MASK) + .value("PseudoVCLMULH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4) + .value("PseudoVCLMULH_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4_MASK) + .value("PseudoVCLMULH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8) + .value("PseudoVCLMULH_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8_MASK) + .value("PseudoVCLMULH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2) + .value("PseudoVCLMULH_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2_MASK) + .value("PseudoVCLMULH_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4) + .value("PseudoVCLMULH_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4_MASK) + .value("PseudoVCLMULH_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8) + .value("PseudoVCLMULH_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8_MASK) + .value("PseudoVCLMULH_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1) + .value("PseudoVCLMULH_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1_MASK) + .value("PseudoVCLMULH_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2) + .value("PseudoVCLMULH_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2_MASK) + .value("PseudoVCLMULH_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4) + .value("PseudoVCLMULH_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4_MASK) + .value("PseudoVCLMULH_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8) + .value("PseudoVCLMULH_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8_MASK) + .value("PseudoVCLMULH_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2) + .value("PseudoVCLMULH_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2_MASK) + .value("PseudoVCLMULH_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4) + .value("PseudoVCLMULH_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4_MASK) + .value("PseudoVCLMULH_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8) + .value("PseudoVCLMULH_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8_MASK) + .value("PseudoVCLMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1) + .value("PseudoVCLMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1_MASK) + .value("PseudoVCLMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2) + .value("PseudoVCLMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2_MASK) + .value("PseudoVCLMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4) + .value("PseudoVCLMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4_MASK) + .value("PseudoVCLMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8) + .value("PseudoVCLMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8_MASK) + .value("PseudoVCLMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2) + .value("PseudoVCLMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2_MASK) + .value("PseudoVCLMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4) + .value("PseudoVCLMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4_MASK) + .value("PseudoVCLMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8) + .value("PseudoVCLMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8_MASK) + .value("PseudoVCLMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1) + .value("PseudoVCLMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1_MASK) + .value("PseudoVCLMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2) + .value("PseudoVCLMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2_MASK) + .value("PseudoVCLMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4) + .value("PseudoVCLMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4_MASK) + .value("PseudoVCLMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8) + .value("PseudoVCLMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8_MASK) + .value("PseudoVCLMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2) + .value("PseudoVCLMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2_MASK) + .value("PseudoVCLMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4) + .value("PseudoVCLMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4_MASK) + .value("PseudoVCLMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8) + .value("PseudoVCLMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8_MASK) + .value("PseudoVCLZ_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1) + .value("PseudoVCLZ_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1_MASK) + .value("PseudoVCLZ_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2) + .value("PseudoVCLZ_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2_MASK) + .value("PseudoVCLZ_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4) + .value("PseudoVCLZ_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4_MASK) + .value("PseudoVCLZ_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8) + .value("PseudoVCLZ_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8_MASK) + .value("PseudoVCLZ_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2) + .value("PseudoVCLZ_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2_MASK) + .value("PseudoVCLZ_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4) + .value("PseudoVCLZ_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4_MASK) + .value("PseudoVCLZ_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8) + .value("PseudoVCLZ_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8_MASK) + .value("PseudoVCOMPRESS_VM_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E16) + .value("PseudoVCOMPRESS_VM_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E32) + .value("PseudoVCOMPRESS_VM_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E64) + .value("PseudoVCOMPRESS_VM_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E8); + opcodes.value("PseudoVCOMPRESS_VM_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E16) + .value("PseudoVCOMPRESS_VM_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E32) + .value("PseudoVCOMPRESS_VM_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E64) + .value("PseudoVCOMPRESS_VM_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E8) + .value("PseudoVCOMPRESS_VM_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E16) + .value("PseudoVCOMPRESS_VM_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E32) + .value("PseudoVCOMPRESS_VM_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E64) + .value("PseudoVCOMPRESS_VM_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E8) + .value("PseudoVCOMPRESS_VM_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E16) + .value("PseudoVCOMPRESS_VM_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E32) + .value("PseudoVCOMPRESS_VM_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E64) + .value("PseudoVCOMPRESS_VM_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E8) + .value("PseudoVCOMPRESS_VM_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E16) + .value("PseudoVCOMPRESS_VM_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E32) + .value("PseudoVCOMPRESS_VM_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E8) + .value("PseudoVCOMPRESS_VM_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E16) + .value("PseudoVCOMPRESS_VM_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E8) + .value("PseudoVCOMPRESS_VM_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF8_E8) + .value("PseudoVCPOP_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1) + .value("PseudoVCPOP_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16) + .value("PseudoVCPOP_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16_MASK) + .value("PseudoVCPOP_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1_MASK) + .value("PseudoVCPOP_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2) + .value("PseudoVCPOP_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2_MASK) + .value("PseudoVCPOP_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32) + .value("PseudoVCPOP_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32_MASK) + .value("PseudoVCPOP_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4) + .value("PseudoVCPOP_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4_MASK) + .value("PseudoVCPOP_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64) + .value("PseudoVCPOP_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64_MASK) + .value("PseudoVCPOP_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8) + .value("PseudoVCPOP_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8_MASK) + .value("PseudoVCPOP_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1) + .value("PseudoVCPOP_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1_MASK) + .value("PseudoVCPOP_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2) + .value("PseudoVCPOP_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2_MASK) + .value("PseudoVCPOP_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4) + .value("PseudoVCPOP_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4_MASK) + .value("PseudoVCPOP_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8) + .value("PseudoVCPOP_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8_MASK) + .value("PseudoVCPOP_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2) + .value("PseudoVCPOP_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2_MASK) + .value("PseudoVCPOP_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4) + .value("PseudoVCPOP_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4_MASK) + .value("PseudoVCPOP_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8) + .value("PseudoVCPOP_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8_MASK) + .value("PseudoVCTZ_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1) + .value("PseudoVCTZ_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1_MASK) + .value("PseudoVCTZ_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2) + .value("PseudoVCTZ_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2_MASK) + .value("PseudoVCTZ_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4) + .value("PseudoVCTZ_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4_MASK) + .value("PseudoVCTZ_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8) + .value("PseudoVCTZ_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8_MASK) + .value("PseudoVCTZ_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2) + .value("PseudoVCTZ_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2_MASK) + .value("PseudoVCTZ_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4) + .value("PseudoVCTZ_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4_MASK) + .value("PseudoVCTZ_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8) + .value("PseudoVCTZ_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8_MASK) + .value("PseudoVDIVU_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16) + .value("PseudoVDIVU_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16_MASK) + .value("PseudoVDIVU_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32) + .value("PseudoVDIVU_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32_MASK) + .value("PseudoVDIVU_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64) + .value("PseudoVDIVU_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64_MASK) + .value("PseudoVDIVU_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8) + .value("PseudoVDIVU_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8_MASK) + .value("PseudoVDIVU_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16) + .value("PseudoVDIVU_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16_MASK) + .value("PseudoVDIVU_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32) + .value("PseudoVDIVU_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32_MASK) + .value("PseudoVDIVU_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64) + .value("PseudoVDIVU_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64_MASK) + .value("PseudoVDIVU_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8) + .value("PseudoVDIVU_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8_MASK) + .value("PseudoVDIVU_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16) + .value("PseudoVDIVU_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16_MASK) + .value("PseudoVDIVU_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32) + .value("PseudoVDIVU_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32_MASK) + .value("PseudoVDIVU_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64) + .value("PseudoVDIVU_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64_MASK) + .value("PseudoVDIVU_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8) + .value("PseudoVDIVU_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8_MASK) + .value("PseudoVDIVU_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16) + .value("PseudoVDIVU_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16_MASK) + .value("PseudoVDIVU_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32) + .value("PseudoVDIVU_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32_MASK) + .value("PseudoVDIVU_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64) + .value("PseudoVDIVU_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64_MASK) + .value("PseudoVDIVU_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8) + .value("PseudoVDIVU_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8_MASK) + .value("PseudoVDIVU_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16) + .value("PseudoVDIVU_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16_MASK) + .value("PseudoVDIVU_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32) + .value("PseudoVDIVU_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32_MASK) + .value("PseudoVDIVU_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8) + .value("PseudoVDIVU_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8_MASK) + .value("PseudoVDIVU_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16) + .value("PseudoVDIVU_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16_MASK) + .value("PseudoVDIVU_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8) + .value("PseudoVDIVU_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8_MASK) + .value("PseudoVDIVU_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8) + .value("PseudoVDIVU_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8_MASK) + .value("PseudoVDIVU_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16) + .value("PseudoVDIVU_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16_MASK) + .value("PseudoVDIVU_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32) + .value("PseudoVDIVU_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32_MASK) + .value("PseudoVDIVU_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64) + .value("PseudoVDIVU_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64_MASK) + .value("PseudoVDIVU_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8) + .value("PseudoVDIVU_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8_MASK) + .value("PseudoVDIVU_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16) + .value("PseudoVDIVU_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16_MASK) + .value("PseudoVDIVU_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32) + .value("PseudoVDIVU_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32_MASK) + .value("PseudoVDIVU_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64) + .value("PseudoVDIVU_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64_MASK) + .value("PseudoVDIVU_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8) + .value("PseudoVDIVU_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8_MASK) + .value("PseudoVDIVU_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16) + .value("PseudoVDIVU_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16_MASK) + .value("PseudoVDIVU_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32) + .value("PseudoVDIVU_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32_MASK) + .value("PseudoVDIVU_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64) + .value("PseudoVDIVU_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64_MASK) + .value("PseudoVDIVU_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8) + .value("PseudoVDIVU_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8_MASK) + .value("PseudoVDIVU_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16) + .value("PseudoVDIVU_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16_MASK) + .value("PseudoVDIVU_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32) + .value("PseudoVDIVU_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32_MASK) + .value("PseudoVDIVU_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64) + .value("PseudoVDIVU_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64_MASK) + .value("PseudoVDIVU_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8) + .value("PseudoVDIVU_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8_MASK) + .value("PseudoVDIVU_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16) + .value("PseudoVDIVU_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16_MASK) + .value("PseudoVDIVU_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32) + .value("PseudoVDIVU_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32_MASK) + .value("PseudoVDIVU_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8) + .value("PseudoVDIVU_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8_MASK) + .value("PseudoVDIVU_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16) + .value("PseudoVDIVU_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16_MASK) + .value("PseudoVDIVU_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8) + .value("PseudoVDIVU_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8_MASK) + .value("PseudoVDIVU_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8) + .value("PseudoVDIVU_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8_MASK) + .value("PseudoVDIV_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16) + .value("PseudoVDIV_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16_MASK) + .value("PseudoVDIV_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32) + .value("PseudoVDIV_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32_MASK) + .value("PseudoVDIV_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64) + .value("PseudoVDIV_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64_MASK) + .value("PseudoVDIV_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8) + .value("PseudoVDIV_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8_MASK) + .value("PseudoVDIV_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16) + .value("PseudoVDIV_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16_MASK) + .value("PseudoVDIV_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32) + .value("PseudoVDIV_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32_MASK) + .value("PseudoVDIV_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64) + .value("PseudoVDIV_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64_MASK) + .value("PseudoVDIV_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8) + .value("PseudoVDIV_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8_MASK) + .value("PseudoVDIV_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16) + .value("PseudoVDIV_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16_MASK) + .value("PseudoVDIV_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32) + .value("PseudoVDIV_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32_MASK) + .value("PseudoVDIV_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64) + .value("PseudoVDIV_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64_MASK) + .value("PseudoVDIV_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8) + .value("PseudoVDIV_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8_MASK) + .value("PseudoVDIV_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16) + .value("PseudoVDIV_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16_MASK) + .value("PseudoVDIV_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32) + .value("PseudoVDIV_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32_MASK) + .value("PseudoVDIV_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64) + .value("PseudoVDIV_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64_MASK) + .value("PseudoVDIV_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8) + .value("PseudoVDIV_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8_MASK) + .value("PseudoVDIV_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16) + .value("PseudoVDIV_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16_MASK) + .value("PseudoVDIV_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32) + .value("PseudoVDIV_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32_MASK) + .value("PseudoVDIV_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8) + .value("PseudoVDIV_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8_MASK) + .value("PseudoVDIV_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16) + .value("PseudoVDIV_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16_MASK) + .value("PseudoVDIV_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8) + .value("PseudoVDIV_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8_MASK) + .value("PseudoVDIV_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8) + .value("PseudoVDIV_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8_MASK) + .value("PseudoVDIV_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16) + .value("PseudoVDIV_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16_MASK) + .value("PseudoVDIV_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32) + .value("PseudoVDIV_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32_MASK) + .value("PseudoVDIV_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64) + .value("PseudoVDIV_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64_MASK) + .value("PseudoVDIV_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8) + .value("PseudoVDIV_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8_MASK) + .value("PseudoVDIV_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16) + .value("PseudoVDIV_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16_MASK) + .value("PseudoVDIV_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32) + .value("PseudoVDIV_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32_MASK) + .value("PseudoVDIV_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64) + .value("PseudoVDIV_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64_MASK) + .value("PseudoVDIV_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8) + .value("PseudoVDIV_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8_MASK) + .value("PseudoVDIV_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16) + .value("PseudoVDIV_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16_MASK) + .value("PseudoVDIV_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32) + .value("PseudoVDIV_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32_MASK) + .value("PseudoVDIV_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64) + .value("PseudoVDIV_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64_MASK) + .value("PseudoVDIV_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8) + .value("PseudoVDIV_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8_MASK) + .value("PseudoVDIV_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16) + .value("PseudoVDIV_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16_MASK) + .value("PseudoVDIV_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32) + .value("PseudoVDIV_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32_MASK) + .value("PseudoVDIV_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64) + .value("PseudoVDIV_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64_MASK) + .value("PseudoVDIV_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8) + .value("PseudoVDIV_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8_MASK) + .value("PseudoVDIV_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16) + .value("PseudoVDIV_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16_MASK) + .value("PseudoVDIV_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32) + .value("PseudoVDIV_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32_MASK) + .value("PseudoVDIV_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8) + .value("PseudoVDIV_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8_MASK) + .value("PseudoVDIV_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16) + .value("PseudoVDIV_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16_MASK) + .value("PseudoVDIV_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8) + .value("PseudoVDIV_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8_MASK) + .value("PseudoVDIV_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8) + .value("PseudoVDIV_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8_MASK) + .value("PseudoVFADD_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M1_E16) + .value("PseudoVFADD_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFADD_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M2_E16) + .value("PseudoVFADD_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFADD_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M4_E16) + .value("PseudoVFADD_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFADD_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M8_E16) + .value("PseudoVFADD_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFADD_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_MF2_E16) + .value("PseudoVFADD_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFADD_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_MF4_E16) + .value("PseudoVFADD_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFADD_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M1_E16) + .value("PseudoVFADD_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M1_E16_MASK) + .value("PseudoVFADD_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M2_E16) + .value("PseudoVFADD_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M2_E16_MASK) + .value("PseudoVFADD_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M4_E16) + .value("PseudoVFADD_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M4_E16_MASK) + .value("PseudoVFADD_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M8_E16) + .value("PseudoVFADD_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_M8_E16_MASK) + .value("PseudoVFADD_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_MF2_E16) + .value("PseudoVFADD_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_MF2_E16_MASK) + .value("PseudoVFADD_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_MF4_E16) + .value("PseudoVFADD_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_ALT_VV_MF4_E16_MASK) + .value("PseudoVFADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16) + .value("PseudoVFADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16_MASK) + .value("PseudoVFADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16) + .value("PseudoVFADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16_MASK) + .value("PseudoVFADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16) + .value("PseudoVFADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16_MASK) + .value("PseudoVFADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16) + .value("PseudoVFADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16_MASK) + .value("PseudoVFADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16) + .value("PseudoVFADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16_MASK) + .value("PseudoVFADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16) + .value("PseudoVFADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16_MASK) + .value("PseudoVFADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32) + .value("PseudoVFADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32_MASK) + .value("PseudoVFADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32) + .value("PseudoVFADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32_MASK) + .value("PseudoVFADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32) + .value("PseudoVFADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32_MASK) + .value("PseudoVFADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32) + .value("PseudoVFADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32_MASK) + .value("PseudoVFADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32) + .value("PseudoVFADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32_MASK) + .value("PseudoVFADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64) + .value("PseudoVFADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64_MASK) + .value("PseudoVFADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64) + .value("PseudoVFADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64_MASK) + .value("PseudoVFADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64) + .value("PseudoVFADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64_MASK) + .value("PseudoVFADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64) + .value("PseudoVFADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64_MASK) + .value("PseudoVFADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16) + .value("PseudoVFADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16_MASK) + .value("PseudoVFADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32) + .value("PseudoVFADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32_MASK) + .value("PseudoVFADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64) + .value("PseudoVFADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64_MASK) + .value("PseudoVFADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16) + .value("PseudoVFADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16_MASK) + .value("PseudoVFADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32) + .value("PseudoVFADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32_MASK); + opcodes.value("PseudoVFADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64) + .value("PseudoVFADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64_MASK) + .value("PseudoVFADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16) + .value("PseudoVFADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16_MASK) + .value("PseudoVFADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32) + .value("PseudoVFADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32_MASK) + .value("PseudoVFADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64) + .value("PseudoVFADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64_MASK) + .value("PseudoVFADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16) + .value("PseudoVFADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16_MASK) + .value("PseudoVFADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32) + .value("PseudoVFADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32_MASK) + .value("PseudoVFADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64) + .value("PseudoVFADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64_MASK) + .value("PseudoVFADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16) + .value("PseudoVFADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16_MASK) + .value("PseudoVFADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32) + .value("PseudoVFADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32_MASK) + .value("PseudoVFADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16) + .value("PseudoVFADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16_MASK) + .value("PseudoVFCLASS_ALT_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M1) + .value("PseudoVFCLASS_ALT_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M1_MASK) + .value("PseudoVFCLASS_ALT_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M2) + .value("PseudoVFCLASS_ALT_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M2_MASK) + .value("PseudoVFCLASS_ALT_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M4) + .value("PseudoVFCLASS_ALT_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M4_MASK) + .value("PseudoVFCLASS_ALT_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M8) + .value("PseudoVFCLASS_ALT_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_M8_MASK) + .value("PseudoVFCLASS_ALT_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_MF2) + .value("PseudoVFCLASS_ALT_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_MF2_MASK) + .value("PseudoVFCLASS_ALT_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_MF4) + .value("PseudoVFCLASS_ALT_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_ALT_V_MF4_MASK) + .value("PseudoVFCLASS_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1) + .value("PseudoVFCLASS_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1_MASK) + .value("PseudoVFCLASS_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2) + .value("PseudoVFCLASS_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2_MASK) + .value("PseudoVFCLASS_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4) + .value("PseudoVFCLASS_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4_MASK) + .value("PseudoVFCLASS_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8) + .value("PseudoVFCLASS_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8_MASK) + .value("PseudoVFCLASS_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2) + .value("PseudoVFCLASS_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2_MASK) + .value("PseudoVFCLASS_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4) + .value("PseudoVFCLASS_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4_MASK) + .value("PseudoVFCVT_F_XU_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16) + .value("PseudoVFCVT_F_XU_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16_MASK) + .value("PseudoVFCVT_F_XU_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32) + .value("PseudoVFCVT_F_XU_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32_MASK) + .value("PseudoVFCVT_F_XU_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64) + .value("PseudoVFCVT_F_XU_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64_MASK) + .value("PseudoVFCVT_F_XU_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16) + .value("PseudoVFCVT_F_XU_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16_MASK) + .value("PseudoVFCVT_F_XU_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32) + .value("PseudoVFCVT_F_XU_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32_MASK) + .value("PseudoVFCVT_F_XU_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64) + .value("PseudoVFCVT_F_XU_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64_MASK) + .value("PseudoVFCVT_F_XU_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16) + .value("PseudoVFCVT_F_XU_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16_MASK) + .value("PseudoVFCVT_F_XU_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32) + .value("PseudoVFCVT_F_XU_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32_MASK) + .value("PseudoVFCVT_F_XU_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64) + .value("PseudoVFCVT_F_XU_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64_MASK) + .value("PseudoVFCVT_F_XU_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16) + .value("PseudoVFCVT_F_XU_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16_MASK) + .value("PseudoVFCVT_F_XU_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32) + .value("PseudoVFCVT_F_XU_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32_MASK) + .value("PseudoVFCVT_F_XU_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64) + .value("PseudoVFCVT_F_XU_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64_MASK) + .value("PseudoVFCVT_F_XU_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16) + .value("PseudoVFCVT_F_XU_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16_MASK) + .value("PseudoVFCVT_F_XU_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32) + .value("PseudoVFCVT_F_XU_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32_MASK) + .value("PseudoVFCVT_F_XU_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16) + .value("PseudoVFCVT_F_XU_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16_MASK) + .value("PseudoVFCVT_F_X_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16) + .value("PseudoVFCVT_F_X_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16_MASK) + .value("PseudoVFCVT_F_X_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32) + .value("PseudoVFCVT_F_X_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32_MASK) + .value("PseudoVFCVT_F_X_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64) + .value("PseudoVFCVT_F_X_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64_MASK) + .value("PseudoVFCVT_F_X_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16) + .value("PseudoVFCVT_F_X_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16_MASK) + .value("PseudoVFCVT_F_X_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32) + .value("PseudoVFCVT_F_X_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32_MASK) + .value("PseudoVFCVT_F_X_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64) + .value("PseudoVFCVT_F_X_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64_MASK) + .value("PseudoVFCVT_F_X_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16) + .value("PseudoVFCVT_F_X_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16_MASK) + .value("PseudoVFCVT_F_X_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32) + .value("PseudoVFCVT_F_X_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32_MASK) + .value("PseudoVFCVT_F_X_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64) + .value("PseudoVFCVT_F_X_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64_MASK) + .value("PseudoVFCVT_F_X_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16) + .value("PseudoVFCVT_F_X_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16_MASK) + .value("PseudoVFCVT_F_X_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32) + .value("PseudoVFCVT_F_X_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32_MASK) + .value("PseudoVFCVT_F_X_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64) + .value("PseudoVFCVT_F_X_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64_MASK) + .value("PseudoVFCVT_F_X_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16) + .value("PseudoVFCVT_F_X_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16_MASK) + .value("PseudoVFCVT_F_X_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32) + .value("PseudoVFCVT_F_X_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32_MASK) + .value("PseudoVFCVT_F_X_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16) + .value("PseudoVFCVT_F_X_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1) + .value("PseudoVFCVT_RTZ_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2) + .value("PseudoVFCVT_RTZ_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4) + .value("PseudoVFCVT_RTZ_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8) + .value("PseudoVFCVT_RTZ_XU_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2) + .value("PseudoVFCVT_RTZ_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK) + .value("PseudoVFCVT_RTZ_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4) + .value("PseudoVFCVT_RTZ_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1) + .value("PseudoVFCVT_RTZ_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2) + .value("PseudoVFCVT_RTZ_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4) + .value("PseudoVFCVT_RTZ_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8) + .value("PseudoVFCVT_RTZ_X_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2) + .value("PseudoVFCVT_RTZ_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2_MASK) + .value("PseudoVFCVT_RTZ_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4) + .value("PseudoVFCVT_RTZ_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4_MASK) + .value("PseudoVFCVT_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1) + .value("PseudoVFCVT_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1_MASK) + .value("PseudoVFCVT_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2) + .value("PseudoVFCVT_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2_MASK) + .value("PseudoVFCVT_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4) + .value("PseudoVFCVT_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4_MASK) + .value("PseudoVFCVT_XU_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8) + .value("PseudoVFCVT_XU_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8_MASK) + .value("PseudoVFCVT_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2) + .value("PseudoVFCVT_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2_MASK) + .value("PseudoVFCVT_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4) + .value("PseudoVFCVT_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4_MASK) + .value("PseudoVFCVT_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1) + .value("PseudoVFCVT_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1_MASK) + .value("PseudoVFCVT_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2) + .value("PseudoVFCVT_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2_MASK) + .value("PseudoVFCVT_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4) + .value("PseudoVFCVT_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4_MASK) + .value("PseudoVFCVT_X_F_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8) + .value("PseudoVFCVT_X_F_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8_MASK) + .value("PseudoVFCVT_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2) + .value("PseudoVFCVT_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2_MASK) + .value("PseudoVFCVT_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4) + .value("PseudoVFCVT_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4_MASK) + .value("PseudoVFDIV_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16) + .value("PseudoVFDIV_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16_MASK) + .value("PseudoVFDIV_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16) + .value("PseudoVFDIV_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16_MASK) + .value("PseudoVFDIV_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16) + .value("PseudoVFDIV_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16_MASK) + .value("PseudoVFDIV_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16) + .value("PseudoVFDIV_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16_MASK) + .value("PseudoVFDIV_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16) + .value("PseudoVFDIV_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16_MASK) + .value("PseudoVFDIV_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16) + .value("PseudoVFDIV_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16_MASK) + .value("PseudoVFDIV_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32) + .value("PseudoVFDIV_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32_MASK) + .value("PseudoVFDIV_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32) + .value("PseudoVFDIV_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32_MASK) + .value("PseudoVFDIV_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32) + .value("PseudoVFDIV_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32_MASK) + .value("PseudoVFDIV_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32) + .value("PseudoVFDIV_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32_MASK) + .value("PseudoVFDIV_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32) + .value("PseudoVFDIV_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32_MASK) + .value("PseudoVFDIV_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64) + .value("PseudoVFDIV_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64_MASK) + .value("PseudoVFDIV_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64) + .value("PseudoVFDIV_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64_MASK) + .value("PseudoVFDIV_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64) + .value("PseudoVFDIV_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64_MASK) + .value("PseudoVFDIV_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64) + .value("PseudoVFDIV_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64_MASK) + .value("PseudoVFDIV_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16) + .value("PseudoVFDIV_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16_MASK) + .value("PseudoVFDIV_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32) + .value("PseudoVFDIV_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32_MASK) + .value("PseudoVFDIV_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64) + .value("PseudoVFDIV_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64_MASK) + .value("PseudoVFDIV_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16) + .value("PseudoVFDIV_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16_MASK) + .value("PseudoVFDIV_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32) + .value("PseudoVFDIV_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32_MASK) + .value("PseudoVFDIV_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64) + .value("PseudoVFDIV_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64_MASK) + .value("PseudoVFDIV_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16) + .value("PseudoVFDIV_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16_MASK) + .value("PseudoVFDIV_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32) + .value("PseudoVFDIV_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32_MASK) + .value("PseudoVFDIV_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64) + .value("PseudoVFDIV_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64_MASK) + .value("PseudoVFDIV_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16) + .value("PseudoVFDIV_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16_MASK) + .value("PseudoVFDIV_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32) + .value("PseudoVFDIV_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32_MASK) + .value("PseudoVFDIV_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64) + .value("PseudoVFDIV_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64_MASK) + .value("PseudoVFDIV_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16) + .value("PseudoVFDIV_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16_MASK) + .value("PseudoVFDIV_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32) + .value("PseudoVFDIV_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32_MASK) + .value("PseudoVFDIV_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16) + .value("PseudoVFDIV_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16_MASK) + .value("PseudoVFIRST_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1) + .value("PseudoVFIRST_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16) + .value("PseudoVFIRST_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16_MASK) + .value("PseudoVFIRST_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1_MASK) + .value("PseudoVFIRST_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2) + .value("PseudoVFIRST_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2_MASK) + .value("PseudoVFIRST_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32) + .value("PseudoVFIRST_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32_MASK) + .value("PseudoVFIRST_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4) + .value("PseudoVFIRST_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4_MASK) + .value("PseudoVFIRST_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64) + .value("PseudoVFIRST_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64_MASK) + .value("PseudoVFIRST_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8) + .value("PseudoVFIRST_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8_MASK) + .value("PseudoVFMACC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M1_E16) + .value("PseudoVFMACC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMACC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M2_E16) + .value("PseudoVFMACC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMACC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M4_E16) + .value("PseudoVFMACC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMACC_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M8_E16) + .value("PseudoVFMACC_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMACC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_MF2_E16) + .value("PseudoVFMACC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMACC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_MF4_E16) + .value("PseudoVFMACC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMACC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M1_E16) + .value("PseudoVFMACC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M1_E16_MASK) + .value("PseudoVFMACC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M2_E16) + .value("PseudoVFMACC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M2_E16_MASK) + .value("PseudoVFMACC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M4_E16) + .value("PseudoVFMACC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M4_E16_MASK) + .value("PseudoVFMACC_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M8_E16) + .value("PseudoVFMACC_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_M8_E16_MASK) + .value("PseudoVFMACC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_MF2_E16) + .value("PseudoVFMACC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMACC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_MF4_E16) + .value("PseudoVFMACC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16) + .value("PseudoVFMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16_MASK) + .value("PseudoVFMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16) + .value("PseudoVFMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16_MASK) + .value("PseudoVFMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16) + .value("PseudoVFMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16_MASK) + .value("PseudoVFMACC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16) + .value("PseudoVFMACC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16_MASK) + .value("PseudoVFMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16) + .value("PseudoVFMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16_MASK) + .value("PseudoVFMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16) + .value("PseudoVFMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16_MASK) + .value("PseudoVFMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32) + .value("PseudoVFMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32_MASK) + .value("PseudoVFMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32) + .value("PseudoVFMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32_MASK) + .value("PseudoVFMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32) + .value("PseudoVFMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32_MASK) + .value("PseudoVFMACC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32) + .value("PseudoVFMACC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32_MASK) + .value("PseudoVFMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32) + .value("PseudoVFMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32_MASK) + .value("PseudoVFMACC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64) + .value("PseudoVFMACC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64_MASK) + .value("PseudoVFMACC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64) + .value("PseudoVFMACC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64_MASK) + .value("PseudoVFMACC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64) + .value("PseudoVFMACC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64_MASK) + .value("PseudoVFMACC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64) + .value("PseudoVFMACC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64_MASK) + .value("PseudoVFMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16) + .value("PseudoVFMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16_MASK) + .value("PseudoVFMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32) + .value("PseudoVFMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32_MASK) + .value("PseudoVFMACC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64) + .value("PseudoVFMACC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64_MASK) + .value("PseudoVFMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16) + .value("PseudoVFMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16_MASK) + .value("PseudoVFMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32) + .value("PseudoVFMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32_MASK) + .value("PseudoVFMACC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64) + .value("PseudoVFMACC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64_MASK) + .value("PseudoVFMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16) + .value("PseudoVFMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16_MASK) + .value("PseudoVFMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32) + .value("PseudoVFMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32_MASK) + .value("PseudoVFMACC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64) + .value("PseudoVFMACC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64_MASK) + .value("PseudoVFMACC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16) + .value("PseudoVFMACC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16_MASK); + opcodes.value("PseudoVFMACC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32) + .value("PseudoVFMACC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32_MASK) + .value("PseudoVFMACC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64) + .value("PseudoVFMACC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64_MASK) + .value("PseudoVFMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16) + .value("PseudoVFMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16_MASK) + .value("PseudoVFMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32) + .value("PseudoVFMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32_MASK) + .value("PseudoVFMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16) + .value("PseudoVFMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M1_E16) + .value("PseudoVFMADD_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M2_E16) + .value("PseudoVFMADD_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M4_E16) + .value("PseudoVFMADD_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M8_E16) + .value("PseudoVFMADD_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_MF2_E16) + .value("PseudoVFMADD_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMADD_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_MF4_E16) + .value("PseudoVFMADD_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMADD_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M1_E16) + .value("PseudoVFMADD_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M1_E16_MASK) + .value("PseudoVFMADD_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M2_E16) + .value("PseudoVFMADD_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M2_E16_MASK) + .value("PseudoVFMADD_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M4_E16) + .value("PseudoVFMADD_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M4_E16_MASK) + .value("PseudoVFMADD_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M8_E16) + .value("PseudoVFMADD_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_M8_E16_MASK) + .value("PseudoVFMADD_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_MF2_E16) + .value("PseudoVFMADD_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMADD_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_MF4_E16) + .value("PseudoVFMADD_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16) + .value("PseudoVFMADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16_MASK) + .value("PseudoVFMADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16) + .value("PseudoVFMADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16_MASK) + .value("PseudoVFMADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16) + .value("PseudoVFMADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16_MASK) + .value("PseudoVFMADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16) + .value("PseudoVFMADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16_MASK) + .value("PseudoVFMADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16) + .value("PseudoVFMADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16_MASK) + .value("PseudoVFMADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16) + .value("PseudoVFMADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16_MASK) + .value("PseudoVFMADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32) + .value("PseudoVFMADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32_MASK) + .value("PseudoVFMADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32) + .value("PseudoVFMADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32_MASK) + .value("PseudoVFMADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32) + .value("PseudoVFMADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32_MASK) + .value("PseudoVFMADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32) + .value("PseudoVFMADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32_MASK) + .value("PseudoVFMADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32) + .value("PseudoVFMADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32_MASK) + .value("PseudoVFMADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64) + .value("PseudoVFMADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64_MASK) + .value("PseudoVFMADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64) + .value("PseudoVFMADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64_MASK) + .value("PseudoVFMADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64) + .value("PseudoVFMADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64_MASK) + .value("PseudoVFMADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64) + .value("PseudoVFMADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64_MASK) + .value("PseudoVFMADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16) + .value("PseudoVFMADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16_MASK) + .value("PseudoVFMADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32) + .value("PseudoVFMADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32_MASK) + .value("PseudoVFMADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64) + .value("PseudoVFMADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64_MASK) + .value("PseudoVFMADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16) + .value("PseudoVFMADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16_MASK) + .value("PseudoVFMADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32) + .value("PseudoVFMADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32_MASK) + .value("PseudoVFMADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64) + .value("PseudoVFMADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64_MASK) + .value("PseudoVFMADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16) + .value("PseudoVFMADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16_MASK) + .value("PseudoVFMADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32) + .value("PseudoVFMADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32_MASK) + .value("PseudoVFMADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64) + .value("PseudoVFMADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64_MASK) + .value("PseudoVFMADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16) + .value("PseudoVFMADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16_MASK) + .value("PseudoVFMADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32) + .value("PseudoVFMADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32_MASK) + .value("PseudoVFMADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64) + .value("PseudoVFMADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64_MASK) + .value("PseudoVFMADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16) + .value("PseudoVFMADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16_MASK) + .value("PseudoVFMADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32) + .value("PseudoVFMADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32_MASK) + .value("PseudoVFMADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16) + .value("PseudoVFMADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M1_E16) + .value("PseudoVFMAX_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M2_E16) + .value("PseudoVFMAX_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M4_E16) + .value("PseudoVFMAX_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M8_E16) + .value("PseudoVFMAX_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_MF2_E16) + .value("PseudoVFMAX_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMAX_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_MF4_E16) + .value("PseudoVFMAX_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMAX_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M1_E16) + .value("PseudoVFMAX_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M1_E16_MASK) + .value("PseudoVFMAX_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M2_E16) + .value("PseudoVFMAX_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M2_E16_MASK) + .value("PseudoVFMAX_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M4_E16) + .value("PseudoVFMAX_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M4_E16_MASK) + .value("PseudoVFMAX_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M8_E16) + .value("PseudoVFMAX_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_M8_E16_MASK) + .value("PseudoVFMAX_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_MF2_E16) + .value("PseudoVFMAX_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMAX_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_MF4_E16) + .value("PseudoVFMAX_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMAX_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16) + .value("PseudoVFMAX_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16_MASK) + .value("PseudoVFMAX_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16) + .value("PseudoVFMAX_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16_MASK) + .value("PseudoVFMAX_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16) + .value("PseudoVFMAX_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16_MASK) + .value("PseudoVFMAX_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16) + .value("PseudoVFMAX_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16_MASK) + .value("PseudoVFMAX_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16) + .value("PseudoVFMAX_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16_MASK) + .value("PseudoVFMAX_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16) + .value("PseudoVFMAX_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16_MASK) + .value("PseudoVFMAX_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32) + .value("PseudoVFMAX_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32_MASK) + .value("PseudoVFMAX_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32) + .value("PseudoVFMAX_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32_MASK) + .value("PseudoVFMAX_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32) + .value("PseudoVFMAX_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32_MASK) + .value("PseudoVFMAX_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32) + .value("PseudoVFMAX_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32_MASK) + .value("PseudoVFMAX_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32) + .value("PseudoVFMAX_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32_MASK) + .value("PseudoVFMAX_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64) + .value("PseudoVFMAX_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64_MASK) + .value("PseudoVFMAX_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64) + .value("PseudoVFMAX_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64_MASK) + .value("PseudoVFMAX_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64) + .value("PseudoVFMAX_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64_MASK) + .value("PseudoVFMAX_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64) + .value("PseudoVFMAX_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64_MASK) + .value("PseudoVFMAX_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16) + .value("PseudoVFMAX_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16_MASK) + .value("PseudoVFMAX_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32) + .value("PseudoVFMAX_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32_MASK) + .value("PseudoVFMAX_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64) + .value("PseudoVFMAX_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64_MASK) + .value("PseudoVFMAX_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16) + .value("PseudoVFMAX_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16_MASK) + .value("PseudoVFMAX_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32) + .value("PseudoVFMAX_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32_MASK) + .value("PseudoVFMAX_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64) + .value("PseudoVFMAX_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64_MASK) + .value("PseudoVFMAX_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16) + .value("PseudoVFMAX_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16_MASK) + .value("PseudoVFMAX_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32) + .value("PseudoVFMAX_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32_MASK) + .value("PseudoVFMAX_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64) + .value("PseudoVFMAX_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64_MASK) + .value("PseudoVFMAX_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16) + .value("PseudoVFMAX_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16_MASK) + .value("PseudoVFMAX_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32) + .value("PseudoVFMAX_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32_MASK) + .value("PseudoVFMAX_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64) + .value("PseudoVFMAX_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64_MASK) + .value("PseudoVFMAX_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16) + .value("PseudoVFMAX_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16_MASK) + .value("PseudoVFMAX_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32) + .value("PseudoVFMAX_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32_MASK) + .value("PseudoVFMAX_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16) + .value("PseudoVFMAX_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16_MASK) + .value("PseudoVFMERGE_ALT_VFPR16M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_M1) + .value("PseudoVFMERGE_ALT_VFPR16M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_M2) + .value("PseudoVFMERGE_ALT_VFPR16M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_M4) + .value("PseudoVFMERGE_ALT_VFPR16M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_M8) + .value("PseudoVFMERGE_ALT_VFPR16M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_MF2) + .value("PseudoVFMERGE_ALT_VFPR16M_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR16M_MF4) + .value("PseudoVFMERGE_ALT_VFPR32M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR32M_M1) + .value("PseudoVFMERGE_ALT_VFPR32M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR32M_M2) + .value("PseudoVFMERGE_ALT_VFPR32M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR32M_M4) + .value("PseudoVFMERGE_ALT_VFPR32M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR32M_M8) + .value("PseudoVFMERGE_ALT_VFPR32M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR32M_MF2) + .value("PseudoVFMERGE_ALT_VFPR64M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR64M_M1) + .value("PseudoVFMERGE_ALT_VFPR64M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR64M_M2) + .value("PseudoVFMERGE_ALT_VFPR64M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR64M_M4) + .value("PseudoVFMERGE_ALT_VFPR64M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_ALT_VFPR64M_M8) + .value("PseudoVFMERGE_VFPR16M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M1) + .value("PseudoVFMERGE_VFPR16M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M2) + .value("PseudoVFMERGE_VFPR16M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M4) + .value("PseudoVFMERGE_VFPR16M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M8) + .value("PseudoVFMERGE_VFPR16M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF2) + .value("PseudoVFMERGE_VFPR16M_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF4) + .value("PseudoVFMERGE_VFPR32M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M1) + .value("PseudoVFMERGE_VFPR32M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M2) + .value("PseudoVFMERGE_VFPR32M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M4) + .value("PseudoVFMERGE_VFPR32M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M8) + .value("PseudoVFMERGE_VFPR32M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_MF2) + .value("PseudoVFMERGE_VFPR64M_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M1) + .value("PseudoVFMERGE_VFPR64M_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M2) + .value("PseudoVFMERGE_VFPR64M_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M4) + .value("PseudoVFMERGE_VFPR64M_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M8) + .value("PseudoVFMIN_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M1_E16) + .value("PseudoVFMIN_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMIN_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M2_E16) + .value("PseudoVFMIN_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMIN_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M4_E16) + .value("PseudoVFMIN_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMIN_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M8_E16) + .value("PseudoVFMIN_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMIN_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_MF2_E16) + .value("PseudoVFMIN_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMIN_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_MF4_E16) + .value("PseudoVFMIN_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMIN_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M1_E16) + .value("PseudoVFMIN_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M1_E16_MASK) + .value("PseudoVFMIN_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M2_E16) + .value("PseudoVFMIN_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M2_E16_MASK) + .value("PseudoVFMIN_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M4_E16) + .value("PseudoVFMIN_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M4_E16_MASK) + .value("PseudoVFMIN_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M8_E16) + .value("PseudoVFMIN_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_M8_E16_MASK) + .value("PseudoVFMIN_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_MF2_E16) + .value("PseudoVFMIN_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMIN_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_MF4_E16) + .value("PseudoVFMIN_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMIN_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16) + .value("PseudoVFMIN_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16_MASK) + .value("PseudoVFMIN_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16) + .value("PseudoVFMIN_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16_MASK) + .value("PseudoVFMIN_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16) + .value("PseudoVFMIN_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16_MASK) + .value("PseudoVFMIN_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16) + .value("PseudoVFMIN_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16_MASK) + .value("PseudoVFMIN_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16) + .value("PseudoVFMIN_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16_MASK) + .value("PseudoVFMIN_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16) + .value("PseudoVFMIN_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16_MASK) + .value("PseudoVFMIN_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32) + .value("PseudoVFMIN_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32_MASK) + .value("PseudoVFMIN_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32) + .value("PseudoVFMIN_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32_MASK) + .value("PseudoVFMIN_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32) + .value("PseudoVFMIN_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32_MASK) + .value("PseudoVFMIN_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32) + .value("PseudoVFMIN_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32_MASK) + .value("PseudoVFMIN_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32) + .value("PseudoVFMIN_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32_MASK) + .value("PseudoVFMIN_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64) + .value("PseudoVFMIN_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64_MASK) + .value("PseudoVFMIN_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64) + .value("PseudoVFMIN_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64_MASK) + .value("PseudoVFMIN_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64) + .value("PseudoVFMIN_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64_MASK) + .value("PseudoVFMIN_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64) + .value("PseudoVFMIN_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64_MASK) + .value("PseudoVFMIN_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16) + .value("PseudoVFMIN_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16_MASK) + .value("PseudoVFMIN_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32) + .value("PseudoVFMIN_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32_MASK) + .value("PseudoVFMIN_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64) + .value("PseudoVFMIN_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64_MASK) + .value("PseudoVFMIN_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16) + .value("PseudoVFMIN_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16_MASK) + .value("PseudoVFMIN_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32) + .value("PseudoVFMIN_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32_MASK) + .value("PseudoVFMIN_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64) + .value("PseudoVFMIN_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64_MASK) + .value("PseudoVFMIN_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16) + .value("PseudoVFMIN_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16_MASK) + .value("PseudoVFMIN_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32) + .value("PseudoVFMIN_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32_MASK) + .value("PseudoVFMIN_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64) + .value("PseudoVFMIN_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64_MASK) + .value("PseudoVFMIN_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16) + .value("PseudoVFMIN_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16_MASK) + .value("PseudoVFMIN_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32) + .value("PseudoVFMIN_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32_MASK) + .value("PseudoVFMIN_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64) + .value("PseudoVFMIN_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64_MASK) + .value("PseudoVFMIN_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16) + .value("PseudoVFMIN_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16_MASK) + .value("PseudoVFMIN_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32) + .value("PseudoVFMIN_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32_MASK) + .value("PseudoVFMIN_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16) + .value("PseudoVFMIN_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16_MASK) + .value("PseudoVFMSAC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M1_E16) + .value("PseudoVFMSAC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMSAC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M2_E16) + .value("PseudoVFMSAC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMSAC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M4_E16) + .value("PseudoVFMSAC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMSAC_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M8_E16) + .value("PseudoVFMSAC_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_M8_E16_MASK); + opcodes.value("PseudoVFMSAC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_MF2_E16) + .value("PseudoVFMSAC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMSAC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_MF4_E16) + .value("PseudoVFMSAC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M1_E16) + .value("PseudoVFMSAC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M1_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M2_E16) + .value("PseudoVFMSAC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M2_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M4_E16) + .value("PseudoVFMSAC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M4_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M8_E16) + .value("PseudoVFMSAC_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_M8_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_MF2_E16) + .value("PseudoVFMSAC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMSAC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_MF4_E16) + .value("PseudoVFMSAC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16) + .value("PseudoVFMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16_MASK) + .value("PseudoVFMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16) + .value("PseudoVFMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16_MASK) + .value("PseudoVFMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16) + .value("PseudoVFMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16_MASK) + .value("PseudoVFMSAC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16) + .value("PseudoVFMSAC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16_MASK) + .value("PseudoVFMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16) + .value("PseudoVFMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16_MASK) + .value("PseudoVFMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16) + .value("PseudoVFMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16_MASK) + .value("PseudoVFMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32) + .value("PseudoVFMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32_MASK) + .value("PseudoVFMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32) + .value("PseudoVFMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32_MASK) + .value("PseudoVFMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32) + .value("PseudoVFMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32_MASK) + .value("PseudoVFMSAC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32) + .value("PseudoVFMSAC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32_MASK) + .value("PseudoVFMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32) + .value("PseudoVFMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32_MASK) + .value("PseudoVFMSAC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64) + .value("PseudoVFMSAC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64_MASK) + .value("PseudoVFMSAC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64) + .value("PseudoVFMSAC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64_MASK) + .value("PseudoVFMSAC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64) + .value("PseudoVFMSAC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64_MASK) + .value("PseudoVFMSAC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64) + .value("PseudoVFMSAC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64_MASK) + .value("PseudoVFMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16) + .value("PseudoVFMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16_MASK) + .value("PseudoVFMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32) + .value("PseudoVFMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32_MASK) + .value("PseudoVFMSAC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64) + .value("PseudoVFMSAC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64_MASK) + .value("PseudoVFMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16) + .value("PseudoVFMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16_MASK) + .value("PseudoVFMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32) + .value("PseudoVFMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32_MASK) + .value("PseudoVFMSAC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64) + .value("PseudoVFMSAC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64_MASK) + .value("PseudoVFMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16) + .value("PseudoVFMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16_MASK) + .value("PseudoVFMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32) + .value("PseudoVFMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32_MASK) + .value("PseudoVFMSAC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64) + .value("PseudoVFMSAC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64_MASK) + .value("PseudoVFMSAC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16) + .value("PseudoVFMSAC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16_MASK) + .value("PseudoVFMSAC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32) + .value("PseudoVFMSAC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32_MASK) + .value("PseudoVFMSAC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64) + .value("PseudoVFMSAC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64_MASK) + .value("PseudoVFMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16) + .value("PseudoVFMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16_MASK) + .value("PseudoVFMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32) + .value("PseudoVFMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32_MASK) + .value("PseudoVFMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16) + .value("PseudoVFMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M1_E16) + .value("PseudoVFMSUB_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M2_E16) + .value("PseudoVFMSUB_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M4_E16) + .value("PseudoVFMSUB_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M8_E16) + .value("PseudoVFMSUB_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_MF2_E16) + .value("PseudoVFMSUB_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMSUB_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_MF4_E16) + .value("PseudoVFMSUB_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M1_E16) + .value("PseudoVFMSUB_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M1_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M2_E16) + .value("PseudoVFMSUB_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M2_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M4_E16) + .value("PseudoVFMSUB_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M4_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M8_E16) + .value("PseudoVFMSUB_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_M8_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_MF2_E16) + .value("PseudoVFMSUB_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMSUB_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_MF4_E16) + .value("PseudoVFMSUB_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16) + .value("PseudoVFMSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16_MASK) + .value("PseudoVFMSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16) + .value("PseudoVFMSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16_MASK) + .value("PseudoVFMSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16) + .value("PseudoVFMSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16_MASK) + .value("PseudoVFMSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16) + .value("PseudoVFMSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16_MASK) + .value("PseudoVFMSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16) + .value("PseudoVFMSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16_MASK) + .value("PseudoVFMSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16) + .value("PseudoVFMSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16_MASK) + .value("PseudoVFMSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32) + .value("PseudoVFMSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32_MASK) + .value("PseudoVFMSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32) + .value("PseudoVFMSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32_MASK) + .value("PseudoVFMSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32) + .value("PseudoVFMSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32_MASK) + .value("PseudoVFMSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32) + .value("PseudoVFMSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32_MASK) + .value("PseudoVFMSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32) + .value("PseudoVFMSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32_MASK) + .value("PseudoVFMSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64) + .value("PseudoVFMSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64_MASK) + .value("PseudoVFMSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64) + .value("PseudoVFMSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64_MASK) + .value("PseudoVFMSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64) + .value("PseudoVFMSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64_MASK) + .value("PseudoVFMSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64) + .value("PseudoVFMSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64_MASK) + .value("PseudoVFMSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16) + .value("PseudoVFMSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16_MASK) + .value("PseudoVFMSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32) + .value("PseudoVFMSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32_MASK) + .value("PseudoVFMSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64) + .value("PseudoVFMSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64_MASK) + .value("PseudoVFMSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16) + .value("PseudoVFMSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16_MASK) + .value("PseudoVFMSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32) + .value("PseudoVFMSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32_MASK) + .value("PseudoVFMSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64) + .value("PseudoVFMSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64_MASK) + .value("PseudoVFMSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16) + .value("PseudoVFMSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16_MASK) + .value("PseudoVFMSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32) + .value("PseudoVFMSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32_MASK) + .value("PseudoVFMSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64) + .value("PseudoVFMSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64_MASK) + .value("PseudoVFMSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16) + .value("PseudoVFMSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16_MASK) + .value("PseudoVFMSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32) + .value("PseudoVFMSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32_MASK) + .value("PseudoVFMSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64) + .value("PseudoVFMSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64_MASK) + .value("PseudoVFMSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16) + .value("PseudoVFMSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16_MASK) + .value("PseudoVFMSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32) + .value("PseudoVFMSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32_MASK) + .value("PseudoVFMSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16) + .value("PseudoVFMSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M1_E16) + .value("PseudoVFMUL_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M2_E16) + .value("PseudoVFMUL_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M4_E16) + .value("PseudoVFMUL_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M8_E16) + .value("PseudoVFMUL_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_MF2_E16) + .value("PseudoVFMUL_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFMUL_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_MF4_E16) + .value("PseudoVFMUL_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFMUL_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M1_E16) + .value("PseudoVFMUL_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M1_E16_MASK) + .value("PseudoVFMUL_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M2_E16) + .value("PseudoVFMUL_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M2_E16_MASK) + .value("PseudoVFMUL_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M4_E16) + .value("PseudoVFMUL_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M4_E16_MASK) + .value("PseudoVFMUL_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M8_E16) + .value("PseudoVFMUL_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_M8_E16_MASK) + .value("PseudoVFMUL_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_MF2_E16) + .value("PseudoVFMUL_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_MF2_E16_MASK) + .value("PseudoVFMUL_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_MF4_E16) + .value("PseudoVFMUL_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_ALT_VV_MF4_E16_MASK) + .value("PseudoVFMUL_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16) + .value("PseudoVFMUL_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16_MASK) + .value("PseudoVFMUL_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16) + .value("PseudoVFMUL_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16_MASK) + .value("PseudoVFMUL_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16) + .value("PseudoVFMUL_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16_MASK) + .value("PseudoVFMUL_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16) + .value("PseudoVFMUL_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16_MASK) + .value("PseudoVFMUL_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16) + .value("PseudoVFMUL_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16_MASK) + .value("PseudoVFMUL_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16) + .value("PseudoVFMUL_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16_MASK) + .value("PseudoVFMUL_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32) + .value("PseudoVFMUL_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32_MASK) + .value("PseudoVFMUL_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32) + .value("PseudoVFMUL_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32_MASK) + .value("PseudoVFMUL_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32) + .value("PseudoVFMUL_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32_MASK) + .value("PseudoVFMUL_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32) + .value("PseudoVFMUL_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32_MASK) + .value("PseudoVFMUL_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32) + .value("PseudoVFMUL_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32_MASK) + .value("PseudoVFMUL_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64) + .value("PseudoVFMUL_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64_MASK) + .value("PseudoVFMUL_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64) + .value("PseudoVFMUL_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64_MASK) + .value("PseudoVFMUL_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64) + .value("PseudoVFMUL_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64_MASK) + .value("PseudoVFMUL_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64) + .value("PseudoVFMUL_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64_MASK) + .value("PseudoVFMUL_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16) + .value("PseudoVFMUL_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16_MASK) + .value("PseudoVFMUL_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32) + .value("PseudoVFMUL_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32_MASK) + .value("PseudoVFMUL_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64) + .value("PseudoVFMUL_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64_MASK) + .value("PseudoVFMUL_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16) + .value("PseudoVFMUL_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16_MASK) + .value("PseudoVFMUL_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32) + .value("PseudoVFMUL_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32_MASK) + .value("PseudoVFMUL_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64) + .value("PseudoVFMUL_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64_MASK) + .value("PseudoVFMUL_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16) + .value("PseudoVFMUL_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16_MASK) + .value("PseudoVFMUL_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32) + .value("PseudoVFMUL_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32_MASK) + .value("PseudoVFMUL_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64) + .value("PseudoVFMUL_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64_MASK) + .value("PseudoVFMUL_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16) + .value("PseudoVFMUL_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16_MASK) + .value("PseudoVFMUL_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32) + .value("PseudoVFMUL_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32_MASK) + .value("PseudoVFMUL_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64) + .value("PseudoVFMUL_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64_MASK) + .value("PseudoVFMUL_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16) + .value("PseudoVFMUL_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16_MASK) + .value("PseudoVFMUL_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32) + .value("PseudoVFMUL_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32_MASK) + .value("PseudoVFMUL_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16) + .value("PseudoVFMUL_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16_MASK) + .value("PseudoVFMV_FPR16_S", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S) + .value("PseudoVFMV_FPR16_S_ALT", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_ALT) + .value("PseudoVFMV_FPR32_S", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S) + .value("PseudoVFMV_FPR64_S", LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S) + .value("PseudoVFMV_S_FPR16", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16) + .value("PseudoVFMV_S_FPR16_ALT", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_ALT) + .value("PseudoVFMV_S_FPR32", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32) + .value("PseudoVFMV_S_FPR64", LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64) + .value("PseudoVFMV_V_ALT_FPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_M1) + .value("PseudoVFMV_V_ALT_FPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_M2) + .value("PseudoVFMV_V_ALT_FPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_M4) + .value("PseudoVFMV_V_ALT_FPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_M8) + .value("PseudoVFMV_V_ALT_FPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_MF2) + .value("PseudoVFMV_V_ALT_FPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR16_MF4) + .value("PseudoVFMV_V_ALT_FPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR32_M1) + .value("PseudoVFMV_V_ALT_FPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR32_M2) + .value("PseudoVFMV_V_ALT_FPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR32_M4) + .value("PseudoVFMV_V_ALT_FPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR32_M8) + .value("PseudoVFMV_V_ALT_FPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR32_MF2) + .value("PseudoVFMV_V_ALT_FPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR64_M1) + .value("PseudoVFMV_V_ALT_FPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR64_M2) + .value("PseudoVFMV_V_ALT_FPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR64_M4) + .value("PseudoVFMV_V_ALT_FPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_ALT_FPR64_M8) + .value("PseudoVFMV_V_FPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M1) + .value("PseudoVFMV_V_FPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M2) + .value("PseudoVFMV_V_FPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M4) + .value("PseudoVFMV_V_FPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M8) + .value("PseudoVFMV_V_FPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF2) + .value("PseudoVFMV_V_FPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF4) + .value("PseudoVFMV_V_FPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M1) + .value("PseudoVFMV_V_FPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M2) + .value("PseudoVFMV_V_FPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M4) + .value("PseudoVFMV_V_FPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M8) + .value("PseudoVFMV_V_FPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_MF2) + .value("PseudoVFMV_V_FPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M1) + .value("PseudoVFMV_V_FPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M2) + .value("PseudoVFMV_V_FPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M4) + .value("PseudoVFMV_V_FPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M1_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M1_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M2_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M2_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M4_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_M4_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8) + .value("PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16) + .value("PseudoVFNCVTBF16_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32) + .value("PseudoVFNCVTBF16_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E8) + .value("PseudoVFNCVTBF16_F_F_W_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E8_MASK); + opcodes.value("PseudoVFNCVTBF16_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16) + .value("PseudoVFNCVTBF16_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32) + .value("PseudoVFNCVTBF16_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E8) + .value("PseudoVFNCVTBF16_F_F_W_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16) + .value("PseudoVFNCVTBF16_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32) + .value("PseudoVFNCVTBF16_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK) + .value("PseudoVFNCVTBF16_F_F_W_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E8) + .value("PseudoVFNCVTBF16_F_F_W_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E8) + .value("PseudoVFNCVTBF16_F_F_W_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16) + .value("PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E8) + .value("PseudoVFNCVTBF16_F_F_W_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E8_MASK) + .value("PseudoVFNCVTBF16_F_F_W_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF8_E8) + .value("PseudoVFNCVTBF16_F_F_W_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF8_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M1_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M1_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M2_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M2_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M4_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_M4_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8_MASK) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8) + .value("PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_Q_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_M1_E8) + .value("PseudoVFNCVT_F_F_ALT_Q_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_M1_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_Q_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_M2_E8) + .value("PseudoVFNCVT_F_F_ALT_Q_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_M2_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_Q_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF2_E8) + .value("PseudoVFNCVT_F_F_ALT_Q_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF2_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_Q_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF4_E8) + .value("PseudoVFNCVT_F_F_ALT_Q_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF4_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_Q_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF8_E8) + .value("PseudoVFNCVT_F_F_ALT_Q_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_Q_MF8_E8_MASK) + .value("PseudoVFNCVT_F_F_ALT_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M1_E16) + .value("PseudoVFNCVT_F_F_ALT_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M1_E16_MASK) + .value("PseudoVFNCVT_F_F_ALT_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M2_E16) + .value("PseudoVFNCVT_F_F_ALT_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M2_E16_MASK) + .value("PseudoVFNCVT_F_F_ALT_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M4_E16) + .value("PseudoVFNCVT_F_F_ALT_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_M4_E16_MASK) + .value("PseudoVFNCVT_F_F_ALT_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_MF2_E16) + .value("PseudoVFNCVT_F_F_ALT_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_MF2_E16_MASK) + .value("PseudoVFNCVT_F_F_ALT_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_MF4_E16) + .value("PseudoVFNCVT_F_F_ALT_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_ALT_W_MF4_E16_MASK) + .value("PseudoVFNCVT_F_F_Q_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_M1_E8) + .value("PseudoVFNCVT_F_F_Q_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_M1_E8_MASK) + .value("PseudoVFNCVT_F_F_Q_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_M2_E8) + .value("PseudoVFNCVT_F_F_Q_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_M2_E8_MASK) + .value("PseudoVFNCVT_F_F_Q_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF2_E8) + .value("PseudoVFNCVT_F_F_Q_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF2_E8_MASK) + .value("PseudoVFNCVT_F_F_Q_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF4_E8) + .value("PseudoVFNCVT_F_F_Q_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF4_E8_MASK) + .value("PseudoVFNCVT_F_F_Q_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF8_E8) + .value("PseudoVFNCVT_F_F_Q_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_Q_MF8_E8_MASK) + .value("PseudoVFNCVT_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16) + .value("PseudoVFNCVT_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16_MASK) + .value("PseudoVFNCVT_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32) + .value("PseudoVFNCVT_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32_MASK) + .value("PseudoVFNCVT_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16) + .value("PseudoVFNCVT_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16_MASK) + .value("PseudoVFNCVT_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32) + .value("PseudoVFNCVT_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32_MASK) + .value("PseudoVFNCVT_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16) + .value("PseudoVFNCVT_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16_MASK) + .value("PseudoVFNCVT_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32) + .value("PseudoVFNCVT_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32_MASK) + .value("PseudoVFNCVT_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16) + .value("PseudoVFNCVT_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16_MASK) + .value("PseudoVFNCVT_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32) + .value("PseudoVFNCVT_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32_MASK) + .value("PseudoVFNCVT_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16) + .value("PseudoVFNCVT_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16_MASK) + .value("PseudoVFNCVT_F_XU_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16) + .value("PseudoVFNCVT_F_XU_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16_MASK) + .value("PseudoVFNCVT_F_XU_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32) + .value("PseudoVFNCVT_F_XU_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32_MASK) + .value("PseudoVFNCVT_F_XU_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16) + .value("PseudoVFNCVT_F_XU_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16_MASK) + .value("PseudoVFNCVT_F_XU_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32) + .value("PseudoVFNCVT_F_XU_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32_MASK) + .value("PseudoVFNCVT_F_XU_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16) + .value("PseudoVFNCVT_F_XU_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16_MASK) + .value("PseudoVFNCVT_F_XU_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32) + .value("PseudoVFNCVT_F_XU_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32_MASK) + .value("PseudoVFNCVT_F_XU_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16) + .value("PseudoVFNCVT_F_XU_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16_MASK) + .value("PseudoVFNCVT_F_XU_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32) + .value("PseudoVFNCVT_F_XU_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32_MASK) + .value("PseudoVFNCVT_F_XU_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16) + .value("PseudoVFNCVT_F_XU_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16_MASK) + .value("PseudoVFNCVT_F_X_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16) + .value("PseudoVFNCVT_F_X_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16_MASK) + .value("PseudoVFNCVT_F_X_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32) + .value("PseudoVFNCVT_F_X_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32_MASK) + .value("PseudoVFNCVT_F_X_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16) + .value("PseudoVFNCVT_F_X_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16_MASK) + .value("PseudoVFNCVT_F_X_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32) + .value("PseudoVFNCVT_F_X_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32_MASK) + .value("PseudoVFNCVT_F_X_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16) + .value("PseudoVFNCVT_F_X_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16_MASK) + .value("PseudoVFNCVT_F_X_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32) + .value("PseudoVFNCVT_F_X_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32_MASK) + .value("PseudoVFNCVT_F_X_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16) + .value("PseudoVFNCVT_F_X_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16_MASK) + .value("PseudoVFNCVT_F_X_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32) + .value("PseudoVFNCVT_F_X_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32_MASK) + .value("PseudoVFNCVT_F_X_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16) + .value("PseudoVFNCVT_F_X_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16) + .value("PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16) + .value("PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32) + .value("PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16) + .value("PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32) + .value("PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16) + .value("PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32) + .value("PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16) + .value("PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32) + .value("PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK) + .value("PseudoVFNCVT_ROD_F_F_W_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16) + .value("PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M1) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M1_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M2) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M2_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M4) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_M4_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8) + .value("PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1) + .value("PseudoVFNCVT_RTZ_XU_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2) + .value("PseudoVFNCVT_RTZ_XU_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4) + .value("PseudoVFNCVT_RTZ_XU_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8) + .value("PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M1) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M1_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M2) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M2_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M4) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_M4_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF2) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF2_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF4) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF4_MASK) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF8) + .value("PseudoVFNCVT_RTZ_X_F_ALT_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_ALT_W_MF8_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1) + .value("PseudoVFNCVT_RTZ_X_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2) + .value("PseudoVFNCVT_RTZ_X_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4) + .value("PseudoVFNCVT_RTZ_X_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2) + .value("PseudoVFNCVT_RTZ_X_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4) + .value("PseudoVFNCVT_RTZ_X_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK) + .value("PseudoVFNCVT_RTZ_X_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8) + .value("PseudoVFNCVT_RTZ_X_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8) + .value("PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_Q_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_M1_E8) + .value("PseudoVFNCVT_SAT_F_F_Q_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_M1_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_Q_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_M2_E8) + .value("PseudoVFNCVT_SAT_F_F_Q_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_M2_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_Q_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF2_E8) + .value("PseudoVFNCVT_SAT_F_F_Q_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF2_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_Q_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF4_E8) + .value("PseudoVFNCVT_SAT_F_F_Q_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF4_E8_MASK) + .value("PseudoVFNCVT_SAT_F_F_Q_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF8_E8) + .value("PseudoVFNCVT_SAT_F_F_Q_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_SAT_F_F_Q_MF8_E8_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M1) + .value("PseudoVFNCVT_XU_F_ALT_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M1_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M2) + .value("PseudoVFNCVT_XU_F_ALT_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M2_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M4) + .value("PseudoVFNCVT_XU_F_ALT_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_M4_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF2) + .value("PseudoVFNCVT_XU_F_ALT_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF2_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF4) + .value("PseudoVFNCVT_XU_F_ALT_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF4_MASK) + .value("PseudoVFNCVT_XU_F_ALT_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF8) + .value("PseudoVFNCVT_XU_F_ALT_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_ALT_W_MF8_MASK) + .value("PseudoVFNCVT_XU_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1) + .value("PseudoVFNCVT_XU_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1_MASK) + .value("PseudoVFNCVT_XU_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2) + .value("PseudoVFNCVT_XU_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2_MASK) + .value("PseudoVFNCVT_XU_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4) + .value("PseudoVFNCVT_XU_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4_MASK) + .value("PseudoVFNCVT_XU_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2) + .value("PseudoVFNCVT_XU_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2_MASK) + .value("PseudoVFNCVT_XU_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4) + .value("PseudoVFNCVT_XU_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4_MASK) + .value("PseudoVFNCVT_XU_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8) + .value("PseudoVFNCVT_XU_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M1) + .value("PseudoVFNCVT_X_F_ALT_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M1_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M2) + .value("PseudoVFNCVT_X_F_ALT_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M2_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M4) + .value("PseudoVFNCVT_X_F_ALT_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_M4_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF2) + .value("PseudoVFNCVT_X_F_ALT_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF2_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF4) + .value("PseudoVFNCVT_X_F_ALT_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF4_MASK) + .value("PseudoVFNCVT_X_F_ALT_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF8) + .value("PseudoVFNCVT_X_F_ALT_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_ALT_W_MF8_MASK) + .value("PseudoVFNCVT_X_F_W_M1", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1) + .value("PseudoVFNCVT_X_F_W_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1_MASK) + .value("PseudoVFNCVT_X_F_W_M2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2) + .value("PseudoVFNCVT_X_F_W_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2_MASK) + .value("PseudoVFNCVT_X_F_W_M4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4) + .value("PseudoVFNCVT_X_F_W_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4_MASK) + .value("PseudoVFNCVT_X_F_W_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2) + .value("PseudoVFNCVT_X_F_W_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2_MASK) + .value("PseudoVFNCVT_X_F_W_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4) + .value("PseudoVFNCVT_X_F_W_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4_MASK) + .value("PseudoVFNCVT_X_F_W_MF8", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8) + .value("PseudoVFNCVT_X_F_W_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M1_E16) + .value("PseudoVFNMACC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M2_E16) + .value("PseudoVFNMACC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M4_E16) + .value("PseudoVFNMACC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M8_E16) + .value("PseudoVFNMACC_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_MF2_E16) + .value("PseudoVFNMACC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMACC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_MF4_E16) + .value("PseudoVFNMACC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M1_E16) + .value("PseudoVFNMACC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M1_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M2_E16) + .value("PseudoVFNMACC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M2_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M4_E16) + .value("PseudoVFNMACC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M4_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M8_E16) + .value("PseudoVFNMACC_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_M8_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_MF2_E16) + .value("PseudoVFNMACC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFNMACC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_MF4_E16) + .value("PseudoVFNMACC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_ALT_VV_MF4_E16_MASK); + opcodes.value("PseudoVFNMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16) + .value("PseudoVFNMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16_MASK) + .value("PseudoVFNMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16) + .value("PseudoVFNMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16_MASK) + .value("PseudoVFNMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16) + .value("PseudoVFNMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16_MASK) + .value("PseudoVFNMACC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16) + .value("PseudoVFNMACC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16_MASK) + .value("PseudoVFNMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16) + .value("PseudoVFNMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16) + .value("PseudoVFNMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32) + .value("PseudoVFNMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32_MASK) + .value("PseudoVFNMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32) + .value("PseudoVFNMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32_MASK) + .value("PseudoVFNMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32) + .value("PseudoVFNMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32_MASK) + .value("PseudoVFNMACC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32) + .value("PseudoVFNMACC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32_MASK) + .value("PseudoVFNMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32) + .value("PseudoVFNMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32_MASK) + .value("PseudoVFNMACC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64) + .value("PseudoVFNMACC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64_MASK) + .value("PseudoVFNMACC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64) + .value("PseudoVFNMACC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64_MASK) + .value("PseudoVFNMACC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64) + .value("PseudoVFNMACC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64_MASK) + .value("PseudoVFNMACC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64) + .value("PseudoVFNMACC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64_MASK) + .value("PseudoVFNMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16) + .value("PseudoVFNMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16_MASK) + .value("PseudoVFNMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32) + .value("PseudoVFNMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32_MASK) + .value("PseudoVFNMACC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64) + .value("PseudoVFNMACC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64_MASK) + .value("PseudoVFNMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16) + .value("PseudoVFNMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16_MASK) + .value("PseudoVFNMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32) + .value("PseudoVFNMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32_MASK) + .value("PseudoVFNMACC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64) + .value("PseudoVFNMACC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64_MASK) + .value("PseudoVFNMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16) + .value("PseudoVFNMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16_MASK) + .value("PseudoVFNMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32) + .value("PseudoVFNMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32_MASK) + .value("PseudoVFNMACC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64) + .value("PseudoVFNMACC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64_MASK) + .value("PseudoVFNMACC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16) + .value("PseudoVFNMACC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16_MASK) + .value("PseudoVFNMACC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32) + .value("PseudoVFNMACC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32_MASK) + .value("PseudoVFNMACC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64) + .value("PseudoVFNMACC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64_MASK) + .value("PseudoVFNMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16) + .value("PseudoVFNMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16_MASK) + .value("PseudoVFNMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32) + .value("PseudoVFNMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32_MASK) + .value("PseudoVFNMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16) + .value("PseudoVFNMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M1_E16) + .value("PseudoVFNMADD_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M2_E16) + .value("PseudoVFNMADD_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M4_E16) + .value("PseudoVFNMADD_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M8_E16) + .value("PseudoVFNMADD_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_MF2_E16) + .value("PseudoVFNMADD_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMADD_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_MF4_E16) + .value("PseudoVFNMADD_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M1_E16) + .value("PseudoVFNMADD_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M1_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M2_E16) + .value("PseudoVFNMADD_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M2_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M4_E16) + .value("PseudoVFNMADD_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M4_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M8_E16) + .value("PseudoVFNMADD_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_M8_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_MF2_E16) + .value("PseudoVFNMADD_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_MF2_E16_MASK) + .value("PseudoVFNMADD_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_MF4_E16) + .value("PseudoVFNMADD_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_ALT_VV_MF4_E16_MASK) + .value("PseudoVFNMADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16) + .value("PseudoVFNMADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16_MASK) + .value("PseudoVFNMADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16) + .value("PseudoVFNMADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16_MASK) + .value("PseudoVFNMADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16) + .value("PseudoVFNMADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16_MASK) + .value("PseudoVFNMADD_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16) + .value("PseudoVFNMADD_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16_MASK) + .value("PseudoVFNMADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16) + .value("PseudoVFNMADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16) + .value("PseudoVFNMADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32) + .value("PseudoVFNMADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32_MASK) + .value("PseudoVFNMADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32) + .value("PseudoVFNMADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32_MASK) + .value("PseudoVFNMADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32) + .value("PseudoVFNMADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32_MASK) + .value("PseudoVFNMADD_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32) + .value("PseudoVFNMADD_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32_MASK) + .value("PseudoVFNMADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32) + .value("PseudoVFNMADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32_MASK) + .value("PseudoVFNMADD_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64) + .value("PseudoVFNMADD_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64_MASK) + .value("PseudoVFNMADD_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64) + .value("PseudoVFNMADD_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64_MASK) + .value("PseudoVFNMADD_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64) + .value("PseudoVFNMADD_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64_MASK) + .value("PseudoVFNMADD_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64) + .value("PseudoVFNMADD_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64_MASK) + .value("PseudoVFNMADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16) + .value("PseudoVFNMADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16_MASK) + .value("PseudoVFNMADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32) + .value("PseudoVFNMADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32_MASK) + .value("PseudoVFNMADD_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64) + .value("PseudoVFNMADD_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64_MASK) + .value("PseudoVFNMADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16) + .value("PseudoVFNMADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16_MASK) + .value("PseudoVFNMADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32) + .value("PseudoVFNMADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32_MASK) + .value("PseudoVFNMADD_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64) + .value("PseudoVFNMADD_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64_MASK) + .value("PseudoVFNMADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16) + .value("PseudoVFNMADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16_MASK) + .value("PseudoVFNMADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32) + .value("PseudoVFNMADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32_MASK) + .value("PseudoVFNMADD_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64) + .value("PseudoVFNMADD_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64_MASK) + .value("PseudoVFNMADD_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16) + .value("PseudoVFNMADD_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16_MASK) + .value("PseudoVFNMADD_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32) + .value("PseudoVFNMADD_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32_MASK) + .value("PseudoVFNMADD_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64) + .value("PseudoVFNMADD_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64_MASK) + .value("PseudoVFNMADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16) + .value("PseudoVFNMADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16_MASK) + .value("PseudoVFNMADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32) + .value("PseudoVFNMADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32_MASK) + .value("PseudoVFNMADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16) + .value("PseudoVFNMADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M1_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M2_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M4_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M8_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_MF2_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMSAC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_MF4_E16) + .value("PseudoVFNMSAC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M1_E16) + .value("PseudoVFNMSAC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M1_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M2_E16) + .value("PseudoVFNMSAC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M2_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M4_E16) + .value("PseudoVFNMSAC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M4_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M8_E16) + .value("PseudoVFNMSAC_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_M8_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_MF2_E16) + .value("PseudoVFNMSAC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFNMSAC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_MF4_E16) + .value("PseudoVFNMSAC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16) + .value("PseudoVFNMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16) + .value("PseudoVFNMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16) + .value("PseudoVFNMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16) + .value("PseudoVFNMSAC_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16) + .value("PseudoVFNMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16) + .value("PseudoVFNMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32) + .value("PseudoVFNMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32_MASK) + .value("PseudoVFNMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32) + .value("PseudoVFNMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32_MASK) + .value("PseudoVFNMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32) + .value("PseudoVFNMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32_MASK) + .value("PseudoVFNMSAC_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32) + .value("PseudoVFNMSAC_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32_MASK) + .value("PseudoVFNMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32) + .value("PseudoVFNMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32_MASK) + .value("PseudoVFNMSAC_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64) + .value("PseudoVFNMSAC_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64_MASK) + .value("PseudoVFNMSAC_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64) + .value("PseudoVFNMSAC_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64_MASK) + .value("PseudoVFNMSAC_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64) + .value("PseudoVFNMSAC_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64_MASK) + .value("PseudoVFNMSAC_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64) + .value("PseudoVFNMSAC_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64_MASK) + .value("PseudoVFNMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16) + .value("PseudoVFNMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16_MASK) + .value("PseudoVFNMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32) + .value("PseudoVFNMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32_MASK) + .value("PseudoVFNMSAC_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64) + .value("PseudoVFNMSAC_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64_MASK) + .value("PseudoVFNMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16) + .value("PseudoVFNMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16_MASK) + .value("PseudoVFNMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32) + .value("PseudoVFNMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32_MASK) + .value("PseudoVFNMSAC_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64) + .value("PseudoVFNMSAC_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64_MASK) + .value("PseudoVFNMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16) + .value("PseudoVFNMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16_MASK) + .value("PseudoVFNMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32) + .value("PseudoVFNMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32_MASK) + .value("PseudoVFNMSAC_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64) + .value("PseudoVFNMSAC_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64_MASK) + .value("PseudoVFNMSAC_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16) + .value("PseudoVFNMSAC_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16_MASK) + .value("PseudoVFNMSAC_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32) + .value("PseudoVFNMSAC_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32_MASK) + .value("PseudoVFNMSAC_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64) + .value("PseudoVFNMSAC_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64_MASK) + .value("PseudoVFNMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16) + .value("PseudoVFNMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16_MASK) + .value("PseudoVFNMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32) + .value("PseudoVFNMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32_MASK) + .value("PseudoVFNMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16) + .value("PseudoVFNMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M1_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M2_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M4_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M8_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_MF2_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMSUB_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_MF4_E16) + .value("PseudoVFNMSUB_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M1_E16) + .value("PseudoVFNMSUB_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M1_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M2_E16) + .value("PseudoVFNMSUB_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M2_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M4_E16) + .value("PseudoVFNMSUB_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M4_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M8_E16) + .value("PseudoVFNMSUB_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_M8_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_MF2_E16) + .value("PseudoVFNMSUB_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_MF2_E16_MASK) + .value("PseudoVFNMSUB_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_MF4_E16) + .value("PseudoVFNMSUB_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_ALT_VV_MF4_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16) + .value("PseudoVFNMSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16) + .value("PseudoVFNMSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16) + .value("PseudoVFNMSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16) + .value("PseudoVFNMSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16) + .value("PseudoVFNMSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16_MASK) + .value("PseudoVFNMSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16) + .value("PseudoVFNMSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16_MASK) + .value("PseudoVFNMSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32) + .value("PseudoVFNMSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32_MASK) + .value("PseudoVFNMSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32) + .value("PseudoVFNMSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32_MASK) + .value("PseudoVFNMSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32) + .value("PseudoVFNMSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32_MASK) + .value("PseudoVFNMSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32) + .value("PseudoVFNMSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32_MASK) + .value("PseudoVFNMSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32) + .value("PseudoVFNMSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32_MASK) + .value("PseudoVFNMSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64) + .value("PseudoVFNMSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64_MASK) + .value("PseudoVFNMSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64) + .value("PseudoVFNMSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64_MASK) + .value("PseudoVFNMSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64) + .value("PseudoVFNMSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64_MASK) + .value("PseudoVFNMSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64) + .value("PseudoVFNMSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64_MASK) + .value("PseudoVFNMSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16) + .value("PseudoVFNMSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16_MASK) + .value("PseudoVFNMSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32) + .value("PseudoVFNMSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32_MASK) + .value("PseudoVFNMSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64) + .value("PseudoVFNMSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64_MASK) + .value("PseudoVFNMSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16) + .value("PseudoVFNMSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16_MASK) + .value("PseudoVFNMSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32) + .value("PseudoVFNMSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32_MASK) + .value("PseudoVFNMSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64) + .value("PseudoVFNMSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64_MASK) + .value("PseudoVFNMSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16) + .value("PseudoVFNMSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16_MASK) + .value("PseudoVFNMSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32) + .value("PseudoVFNMSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32_MASK) + .value("PseudoVFNMSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64) + .value("PseudoVFNMSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64_MASK); + opcodes.value("PseudoVFNMSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16) + .value("PseudoVFNMSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16_MASK) + .value("PseudoVFNMSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32) + .value("PseudoVFNMSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32_MASK) + .value("PseudoVFNMSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64) + .value("PseudoVFNMSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64_MASK) + .value("PseudoVFNMSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16) + .value("PseudoVFNMSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16_MASK) + .value("PseudoVFNMSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32) + .value("PseudoVFNMSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32_MASK) + .value("PseudoVFNMSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16) + .value("PseudoVFNMSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16_MASK) + .value("PseudoVFRDIV_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16) + .value("PseudoVFRDIV_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16_MASK) + .value("PseudoVFRDIV_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16) + .value("PseudoVFRDIV_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16_MASK) + .value("PseudoVFRDIV_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16) + .value("PseudoVFRDIV_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16_MASK) + .value("PseudoVFRDIV_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16) + .value("PseudoVFRDIV_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16_MASK) + .value("PseudoVFRDIV_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16) + .value("PseudoVFRDIV_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16_MASK) + .value("PseudoVFRDIV_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16) + .value("PseudoVFRDIV_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16_MASK) + .value("PseudoVFRDIV_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32) + .value("PseudoVFRDIV_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32_MASK) + .value("PseudoVFRDIV_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32) + .value("PseudoVFRDIV_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32_MASK) + .value("PseudoVFRDIV_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32) + .value("PseudoVFRDIV_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32_MASK) + .value("PseudoVFRDIV_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32) + .value("PseudoVFRDIV_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32_MASK) + .value("PseudoVFRDIV_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32) + .value("PseudoVFRDIV_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32_MASK) + .value("PseudoVFRDIV_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64) + .value("PseudoVFRDIV_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64_MASK) + .value("PseudoVFRDIV_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64) + .value("PseudoVFRDIV_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64_MASK) + .value("PseudoVFRDIV_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64) + .value("PseudoVFRDIV_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64_MASK) + .value("PseudoVFRDIV_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64) + .value("PseudoVFRDIV_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64_MASK) + .value("PseudoVFREC7_ALT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M1_E16) + .value("PseudoVFREC7_ALT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M1_E16_MASK) + .value("PseudoVFREC7_ALT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M2_E16) + .value("PseudoVFREC7_ALT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M2_E16_MASK) + .value("PseudoVFREC7_ALT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M4_E16) + .value("PseudoVFREC7_ALT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M4_E16_MASK) + .value("PseudoVFREC7_ALT_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M8_E16) + .value("PseudoVFREC7_ALT_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_M8_E16_MASK) + .value("PseudoVFREC7_ALT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_MF2_E16) + .value("PseudoVFREC7_ALT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_MF2_E16_MASK) + .value("PseudoVFREC7_ALT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_MF4_E16) + .value("PseudoVFREC7_ALT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_ALT_V_MF4_E16_MASK) + .value("PseudoVFREC7_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16) + .value("PseudoVFREC7_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16_MASK) + .value("PseudoVFREC7_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32) + .value("PseudoVFREC7_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32_MASK) + .value("PseudoVFREC7_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64) + .value("PseudoVFREC7_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64_MASK) + .value("PseudoVFREC7_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16) + .value("PseudoVFREC7_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16_MASK) + .value("PseudoVFREC7_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32) + .value("PseudoVFREC7_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32_MASK) + .value("PseudoVFREC7_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64) + .value("PseudoVFREC7_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64_MASK) + .value("PseudoVFREC7_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16) + .value("PseudoVFREC7_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16_MASK) + .value("PseudoVFREC7_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32) + .value("PseudoVFREC7_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32_MASK) + .value("PseudoVFREC7_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64) + .value("PseudoVFREC7_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64_MASK) + .value("PseudoVFREC7_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16) + .value("PseudoVFREC7_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16_MASK) + .value("PseudoVFREC7_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32) + .value("PseudoVFREC7_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32_MASK) + .value("PseudoVFREC7_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64) + .value("PseudoVFREC7_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64_MASK) + .value("PseudoVFREC7_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16) + .value("PseudoVFREC7_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16_MASK) + .value("PseudoVFREC7_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32) + .value("PseudoVFREC7_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32_MASK) + .value("PseudoVFREC7_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16) + .value("PseudoVFREC7_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16_MASK) + .value("PseudoVFREDMAX_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16) + .value("PseudoVFREDMAX_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16_MASK) + .value("PseudoVFREDMAX_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32) + .value("PseudoVFREDMAX_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32_MASK) + .value("PseudoVFREDMAX_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64) + .value("PseudoVFREDMAX_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64_MASK) + .value("PseudoVFREDMAX_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16) + .value("PseudoVFREDMAX_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16_MASK) + .value("PseudoVFREDMAX_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32) + .value("PseudoVFREDMAX_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32_MASK) + .value("PseudoVFREDMAX_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64) + .value("PseudoVFREDMAX_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64_MASK) + .value("PseudoVFREDMAX_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16) + .value("PseudoVFREDMAX_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16_MASK) + .value("PseudoVFREDMAX_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32) + .value("PseudoVFREDMAX_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32_MASK) + .value("PseudoVFREDMAX_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64) + .value("PseudoVFREDMAX_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64_MASK) + .value("PseudoVFREDMAX_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16) + .value("PseudoVFREDMAX_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16_MASK) + .value("PseudoVFREDMAX_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32) + .value("PseudoVFREDMAX_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32_MASK) + .value("PseudoVFREDMAX_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64) + .value("PseudoVFREDMAX_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64_MASK) + .value("PseudoVFREDMAX_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16) + .value("PseudoVFREDMAX_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16_MASK) + .value("PseudoVFREDMAX_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32) + .value("PseudoVFREDMAX_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32_MASK) + .value("PseudoVFREDMAX_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16) + .value("PseudoVFREDMAX_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16_MASK) + .value("PseudoVFREDMIN_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16) + .value("PseudoVFREDMIN_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16_MASK) + .value("PseudoVFREDMIN_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32) + .value("PseudoVFREDMIN_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32_MASK) + .value("PseudoVFREDMIN_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64) + .value("PseudoVFREDMIN_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64_MASK) + .value("PseudoVFREDMIN_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16) + .value("PseudoVFREDMIN_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16_MASK) + .value("PseudoVFREDMIN_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32) + .value("PseudoVFREDMIN_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32_MASK) + .value("PseudoVFREDMIN_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64) + .value("PseudoVFREDMIN_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64_MASK) + .value("PseudoVFREDMIN_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16) + .value("PseudoVFREDMIN_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16_MASK) + .value("PseudoVFREDMIN_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32) + .value("PseudoVFREDMIN_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32_MASK) + .value("PseudoVFREDMIN_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64) + .value("PseudoVFREDMIN_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64_MASK) + .value("PseudoVFREDMIN_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16) + .value("PseudoVFREDMIN_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16_MASK) + .value("PseudoVFREDMIN_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32) + .value("PseudoVFREDMIN_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32_MASK) + .value("PseudoVFREDMIN_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64) + .value("PseudoVFREDMIN_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64_MASK) + .value("PseudoVFREDMIN_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16) + .value("PseudoVFREDMIN_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16_MASK) + .value("PseudoVFREDMIN_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32) + .value("PseudoVFREDMIN_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32_MASK) + .value("PseudoVFREDMIN_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16) + .value("PseudoVFREDMIN_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16_MASK) + .value("PseudoVFREDOSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16) + .value("PseudoVFREDOSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16_MASK) + .value("PseudoVFREDOSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32) + .value("PseudoVFREDOSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32_MASK) + .value("PseudoVFREDOSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64) + .value("PseudoVFREDOSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64_MASK) + .value("PseudoVFREDOSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16) + .value("PseudoVFREDOSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16_MASK) + .value("PseudoVFREDOSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32) + .value("PseudoVFREDOSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32_MASK) + .value("PseudoVFREDOSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64) + .value("PseudoVFREDOSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64_MASK) + .value("PseudoVFREDOSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16) + .value("PseudoVFREDOSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16_MASK) + .value("PseudoVFREDOSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32) + .value("PseudoVFREDOSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32_MASK) + .value("PseudoVFREDOSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64) + .value("PseudoVFREDOSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64_MASK) + .value("PseudoVFREDOSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16) + .value("PseudoVFREDOSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16_MASK) + .value("PseudoVFREDOSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32) + .value("PseudoVFREDOSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32_MASK) + .value("PseudoVFREDOSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64) + .value("PseudoVFREDOSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64_MASK) + .value("PseudoVFREDOSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16) + .value("PseudoVFREDOSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16_MASK) + .value("PseudoVFREDOSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32) + .value("PseudoVFREDOSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32_MASK) + .value("PseudoVFREDOSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16) + .value("PseudoVFREDOSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16_MASK) + .value("PseudoVFREDUSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16) + .value("PseudoVFREDUSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16_MASK) + .value("PseudoVFREDUSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32) + .value("PseudoVFREDUSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32_MASK) + .value("PseudoVFREDUSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64) + .value("PseudoVFREDUSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64_MASK) + .value("PseudoVFREDUSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16) + .value("PseudoVFREDUSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16_MASK) + .value("PseudoVFREDUSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32) + .value("PseudoVFREDUSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32_MASK) + .value("PseudoVFREDUSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64) + .value("PseudoVFREDUSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64_MASK) + .value("PseudoVFREDUSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16) + .value("PseudoVFREDUSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16_MASK) + .value("PseudoVFREDUSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32) + .value("PseudoVFREDUSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32_MASK) + .value("PseudoVFREDUSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64) + .value("PseudoVFREDUSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64_MASK) + .value("PseudoVFREDUSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16) + .value("PseudoVFREDUSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16_MASK) + .value("PseudoVFREDUSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32) + .value("PseudoVFREDUSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32_MASK) + .value("PseudoVFREDUSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64) + .value("PseudoVFREDUSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64_MASK) + .value("PseudoVFREDUSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16) + .value("PseudoVFREDUSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16_MASK) + .value("PseudoVFREDUSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32) + .value("PseudoVFREDUSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32_MASK) + .value("PseudoVFREDUSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16) + .value("PseudoVFREDUSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M1_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M2_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M4_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M8_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF2_MASK) + .value("PseudoVFROUND_NOEXCEPT_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF4_MASK) + .value("PseudoVFRSQRT7_ALT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M1_E16) + .value("PseudoVFRSQRT7_ALT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M1_E16_MASK) + .value("PseudoVFRSQRT7_ALT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M2_E16) + .value("PseudoVFRSQRT7_ALT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M2_E16_MASK) + .value("PseudoVFRSQRT7_ALT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M4_E16) + .value("PseudoVFRSQRT7_ALT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M4_E16_MASK) + .value("PseudoVFRSQRT7_ALT_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M8_E16) + .value("PseudoVFRSQRT7_ALT_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_M8_E16_MASK) + .value("PseudoVFRSQRT7_ALT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_MF2_E16) + .value("PseudoVFRSQRT7_ALT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_MF2_E16_MASK) + .value("PseudoVFRSQRT7_ALT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_MF4_E16) + .value("PseudoVFRSQRT7_ALT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_ALT_V_MF4_E16_MASK) + .value("PseudoVFRSQRT7_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16) + .value("PseudoVFRSQRT7_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16_MASK) + .value("PseudoVFRSQRT7_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32) + .value("PseudoVFRSQRT7_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32_MASK) + .value("PseudoVFRSQRT7_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64) + .value("PseudoVFRSQRT7_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64_MASK) + .value("PseudoVFRSQRT7_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16) + .value("PseudoVFRSQRT7_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16_MASK) + .value("PseudoVFRSQRT7_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32) + .value("PseudoVFRSQRT7_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32_MASK) + .value("PseudoVFRSQRT7_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64) + .value("PseudoVFRSQRT7_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64_MASK) + .value("PseudoVFRSQRT7_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16) + .value("PseudoVFRSQRT7_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16_MASK) + .value("PseudoVFRSQRT7_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32) + .value("PseudoVFRSQRT7_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32_MASK) + .value("PseudoVFRSQRT7_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64) + .value("PseudoVFRSQRT7_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64_MASK) + .value("PseudoVFRSQRT7_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16) + .value("PseudoVFRSQRT7_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16_MASK) + .value("PseudoVFRSQRT7_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32) + .value("PseudoVFRSQRT7_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32_MASK) + .value("PseudoVFRSQRT7_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64) + .value("PseudoVFRSQRT7_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64_MASK) + .value("PseudoVFRSQRT7_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16) + .value("PseudoVFRSQRT7_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16_MASK) + .value("PseudoVFRSQRT7_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32) + .value("PseudoVFRSQRT7_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32_MASK) + .value("PseudoVFRSQRT7_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16) + .value("PseudoVFRSQRT7_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M1_E16) + .value("PseudoVFRSUB_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M2_E16) + .value("PseudoVFRSUB_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M4_E16) + .value("PseudoVFRSUB_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M8_E16) + .value("PseudoVFRSUB_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_MF2_E16) + .value("PseudoVFRSUB_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFRSUB_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_MF4_E16) + .value("PseudoVFRSUB_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFRSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16) + .value("PseudoVFRSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16_MASK) + .value("PseudoVFRSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16) + .value("PseudoVFRSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16_MASK) + .value("PseudoVFRSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16) + .value("PseudoVFRSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16_MASK) + .value("PseudoVFRSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16) + .value("PseudoVFRSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16_MASK) + .value("PseudoVFRSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16) + .value("PseudoVFRSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16_MASK) + .value("PseudoVFRSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16) + .value("PseudoVFRSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16_MASK) + .value("PseudoVFRSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32) + .value("PseudoVFRSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32_MASK) + .value("PseudoVFRSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32) + .value("PseudoVFRSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32_MASK) + .value("PseudoVFRSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32) + .value("PseudoVFRSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32_MASK) + .value("PseudoVFRSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32) + .value("PseudoVFRSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32_MASK) + .value("PseudoVFRSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32) + .value("PseudoVFRSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32_MASK) + .value("PseudoVFRSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64) + .value("PseudoVFRSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64_MASK) + .value("PseudoVFRSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64) + .value("PseudoVFRSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64_MASK) + .value("PseudoVFRSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64) + .value("PseudoVFRSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64_MASK) + .value("PseudoVFRSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64) + .value("PseudoVFRSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64_MASK) + .value("PseudoVFSGNJN_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M1_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJN_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M2_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJN_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M4_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M4_E16_MASK); + opcodes.value("PseudoVFSGNJN_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M8_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJN_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_MF2_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJN_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_MF4_E16) + .value("PseudoVFSGNJN_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M1_E16) + .value("PseudoVFSGNJN_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M1_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M2_E16) + .value("PseudoVFSGNJN_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M2_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M4_E16) + .value("PseudoVFSGNJN_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M4_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M8_E16) + .value("PseudoVFSGNJN_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_M8_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_MF2_E16) + .value("PseudoVFSGNJN_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_MF2_E16_MASK) + .value("PseudoVFSGNJN_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_MF4_E16) + .value("PseudoVFSGNJN_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_ALT_VV_MF4_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16) + .value("PseudoVFSGNJN_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16) + .value("PseudoVFSGNJN_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16) + .value("PseudoVFSGNJN_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16) + .value("PseudoVFSGNJN_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16) + .value("PseudoVFSGNJN_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJN_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16) + .value("PseudoVFSGNJN_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJN_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32) + .value("PseudoVFSGNJN_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32_MASK) + .value("PseudoVFSGNJN_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32) + .value("PseudoVFSGNJN_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32_MASK) + .value("PseudoVFSGNJN_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32) + .value("PseudoVFSGNJN_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32_MASK) + .value("PseudoVFSGNJN_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32) + .value("PseudoVFSGNJN_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32_MASK) + .value("PseudoVFSGNJN_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32) + .value("PseudoVFSGNJN_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32_MASK) + .value("PseudoVFSGNJN_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64) + .value("PseudoVFSGNJN_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64_MASK) + .value("PseudoVFSGNJN_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64) + .value("PseudoVFSGNJN_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64_MASK) + .value("PseudoVFSGNJN_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64) + .value("PseudoVFSGNJN_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64_MASK) + .value("PseudoVFSGNJN_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64) + .value("PseudoVFSGNJN_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64_MASK) + .value("PseudoVFSGNJN_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16) + .value("PseudoVFSGNJN_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16_MASK) + .value("PseudoVFSGNJN_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32) + .value("PseudoVFSGNJN_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32_MASK) + .value("PseudoVFSGNJN_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64) + .value("PseudoVFSGNJN_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64_MASK) + .value("PseudoVFSGNJN_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16) + .value("PseudoVFSGNJN_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16_MASK) + .value("PseudoVFSGNJN_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32) + .value("PseudoVFSGNJN_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32_MASK) + .value("PseudoVFSGNJN_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64) + .value("PseudoVFSGNJN_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64_MASK) + .value("PseudoVFSGNJN_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16) + .value("PseudoVFSGNJN_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16_MASK) + .value("PseudoVFSGNJN_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32) + .value("PseudoVFSGNJN_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32_MASK) + .value("PseudoVFSGNJN_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64) + .value("PseudoVFSGNJN_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64_MASK) + .value("PseudoVFSGNJN_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16) + .value("PseudoVFSGNJN_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16_MASK) + .value("PseudoVFSGNJN_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32) + .value("PseudoVFSGNJN_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32_MASK) + .value("PseudoVFSGNJN_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64) + .value("PseudoVFSGNJN_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64_MASK) + .value("PseudoVFSGNJN_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16) + .value("PseudoVFSGNJN_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16_MASK) + .value("PseudoVFSGNJN_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32) + .value("PseudoVFSGNJN_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32_MASK) + .value("PseudoVFSGNJN_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16) + .value("PseudoVFSGNJN_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M1_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M2_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M4_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M8_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_MF2_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJX_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_MF4_E16) + .value("PseudoVFSGNJX_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M1_E16) + .value("PseudoVFSGNJX_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M1_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M2_E16) + .value("PseudoVFSGNJX_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M2_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M4_E16) + .value("PseudoVFSGNJX_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M4_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M8_E16) + .value("PseudoVFSGNJX_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_M8_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_MF2_E16) + .value("PseudoVFSGNJX_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_MF2_E16_MASK) + .value("PseudoVFSGNJX_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_MF4_E16) + .value("PseudoVFSGNJX_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_ALT_VV_MF4_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16) + .value("PseudoVFSGNJX_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16) + .value("PseudoVFSGNJX_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16) + .value("PseudoVFSGNJX_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16) + .value("PseudoVFSGNJX_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16) + .value("PseudoVFSGNJX_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJX_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16) + .value("PseudoVFSGNJX_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJX_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32) + .value("PseudoVFSGNJX_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32_MASK) + .value("PseudoVFSGNJX_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32) + .value("PseudoVFSGNJX_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32_MASK) + .value("PseudoVFSGNJX_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32) + .value("PseudoVFSGNJX_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32_MASK) + .value("PseudoVFSGNJX_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32) + .value("PseudoVFSGNJX_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32_MASK) + .value("PseudoVFSGNJX_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32) + .value("PseudoVFSGNJX_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32_MASK) + .value("PseudoVFSGNJX_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64) + .value("PseudoVFSGNJX_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64_MASK) + .value("PseudoVFSGNJX_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64) + .value("PseudoVFSGNJX_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64_MASK) + .value("PseudoVFSGNJX_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64) + .value("PseudoVFSGNJX_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64_MASK) + .value("PseudoVFSGNJX_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64) + .value("PseudoVFSGNJX_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64_MASK) + .value("PseudoVFSGNJX_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16) + .value("PseudoVFSGNJX_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16_MASK) + .value("PseudoVFSGNJX_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32) + .value("PseudoVFSGNJX_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32_MASK) + .value("PseudoVFSGNJX_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64) + .value("PseudoVFSGNJX_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64_MASK) + .value("PseudoVFSGNJX_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16) + .value("PseudoVFSGNJX_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16_MASK) + .value("PseudoVFSGNJX_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32) + .value("PseudoVFSGNJX_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32_MASK) + .value("PseudoVFSGNJX_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64) + .value("PseudoVFSGNJX_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64_MASK) + .value("PseudoVFSGNJX_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16) + .value("PseudoVFSGNJX_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16_MASK) + .value("PseudoVFSGNJX_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32) + .value("PseudoVFSGNJX_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32_MASK) + .value("PseudoVFSGNJX_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64) + .value("PseudoVFSGNJX_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64_MASK) + .value("PseudoVFSGNJX_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16) + .value("PseudoVFSGNJX_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16_MASK) + .value("PseudoVFSGNJX_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32) + .value("PseudoVFSGNJX_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32_MASK) + .value("PseudoVFSGNJX_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64) + .value("PseudoVFSGNJX_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64_MASK) + .value("PseudoVFSGNJX_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16) + .value("PseudoVFSGNJX_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16_MASK) + .value("PseudoVFSGNJX_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32) + .value("PseudoVFSGNJX_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32_MASK) + .value("PseudoVFSGNJX_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16) + .value("PseudoVFSGNJX_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M1_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M2_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M4_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M8_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_MF2_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJ_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_MF4_E16) + .value("PseudoVFSGNJ_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M1_E16) + .value("PseudoVFSGNJ_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M1_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M2_E16) + .value("PseudoVFSGNJ_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M2_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M4_E16) + .value("PseudoVFSGNJ_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M4_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M8_E16) + .value("PseudoVFSGNJ_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_M8_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_MF2_E16) + .value("PseudoVFSGNJ_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_MF2_E16_MASK) + .value("PseudoVFSGNJ_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_MF4_E16) + .value("PseudoVFSGNJ_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_ALT_VV_MF4_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16) + .value("PseudoVFSGNJ_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16) + .value("PseudoVFSGNJ_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16) + .value("PseudoVFSGNJ_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16) + .value("PseudoVFSGNJ_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16) + .value("PseudoVFSGNJ_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16_MASK) + .value("PseudoVFSGNJ_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16) + .value("PseudoVFSGNJ_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16_MASK) + .value("PseudoVFSGNJ_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32) + .value("PseudoVFSGNJ_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32_MASK) + .value("PseudoVFSGNJ_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32) + .value("PseudoVFSGNJ_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32_MASK) + .value("PseudoVFSGNJ_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32) + .value("PseudoVFSGNJ_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32_MASK) + .value("PseudoVFSGNJ_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32) + .value("PseudoVFSGNJ_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32_MASK) + .value("PseudoVFSGNJ_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32) + .value("PseudoVFSGNJ_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32_MASK) + .value("PseudoVFSGNJ_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64) + .value("PseudoVFSGNJ_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64_MASK) + .value("PseudoVFSGNJ_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64) + .value("PseudoVFSGNJ_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64_MASK) + .value("PseudoVFSGNJ_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64) + .value("PseudoVFSGNJ_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64_MASK) + .value("PseudoVFSGNJ_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64) + .value("PseudoVFSGNJ_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64_MASK) + .value("PseudoVFSGNJ_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16) + .value("PseudoVFSGNJ_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16_MASK) + .value("PseudoVFSGNJ_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32) + .value("PseudoVFSGNJ_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32_MASK) + .value("PseudoVFSGNJ_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64) + .value("PseudoVFSGNJ_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64_MASK) + .value("PseudoVFSGNJ_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16) + .value("PseudoVFSGNJ_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16_MASK) + .value("PseudoVFSGNJ_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32) + .value("PseudoVFSGNJ_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32_MASK) + .value("PseudoVFSGNJ_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64) + .value("PseudoVFSGNJ_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64_MASK) + .value("PseudoVFSGNJ_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16) + .value("PseudoVFSGNJ_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16_MASK) + .value("PseudoVFSGNJ_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32) + .value("PseudoVFSGNJ_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32_MASK) + .value("PseudoVFSGNJ_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64) + .value("PseudoVFSGNJ_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64_MASK) + .value("PseudoVFSGNJ_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16) + .value("PseudoVFSGNJ_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16_MASK) + .value("PseudoVFSGNJ_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32) + .value("PseudoVFSGNJ_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32_MASK) + .value("PseudoVFSGNJ_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64) + .value("PseudoVFSGNJ_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64_MASK) + .value("PseudoVFSGNJ_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16) + .value("PseudoVFSGNJ_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16_MASK) + .value("PseudoVFSGNJ_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32) + .value("PseudoVFSGNJ_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32_MASK) + .value("PseudoVFSGNJ_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16) + .value("PseudoVFSGNJ_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M1) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M1_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M2) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M2_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M4) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M4_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M8) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_M8_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M1) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M1_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M2) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M2_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M4) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M4_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M8) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_M8_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M1) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M1_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M2) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M2_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M4) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M4_MASK) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M8) + .value("PseudoVFSLIDE1DOWN_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_ALT_VFPR64_M8_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1) + .value("PseudoVFSLIDE1DOWN_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2) + .value("PseudoVFSLIDE1DOWN_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4) + .value("PseudoVFSLIDE1DOWN_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8) + .value("PseudoVFSLIDE1DOWN_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2) + .value("PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4) + .value("PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1) + .value("PseudoVFSLIDE1DOWN_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2) + .value("PseudoVFSLIDE1DOWN_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4) + .value("PseudoVFSLIDE1DOWN_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8) + .value("PseudoVFSLIDE1DOWN_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2) + .value("PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1) + .value("PseudoVFSLIDE1DOWN_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK); + opcodes.value("PseudoVFSLIDE1DOWN_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2) + .value("PseudoVFSLIDE1DOWN_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4) + .value("PseudoVFSLIDE1DOWN_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK) + .value("PseudoVFSLIDE1DOWN_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8) + .value("PseudoVFSLIDE1DOWN_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M1) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M1_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M2) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M2_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M4) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M4_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M8) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_M8_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_MF2) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_MF2_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_MF4) + .value("PseudoVFSLIDE1UP_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR16_MF4_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M1) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M1_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M2) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M2_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M4) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M4_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M8) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_M8_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_MF2) + .value("PseudoVFSLIDE1UP_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR32_MF2_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M1) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M1_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M2) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M2_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M4) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M4_MASK) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M8) + .value("PseudoVFSLIDE1UP_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_ALT_VFPR64_M8_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1) + .value("PseudoVFSLIDE1UP_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2) + .value("PseudoVFSLIDE1UP_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4) + .value("PseudoVFSLIDE1UP_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8) + .value("PseudoVFSLIDE1UP_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2) + .value("PseudoVFSLIDE1UP_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2_MASK) + .value("PseudoVFSLIDE1UP_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4) + .value("PseudoVFSLIDE1UP_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4_MASK) + .value("PseudoVFSLIDE1UP_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1) + .value("PseudoVFSLIDE1UP_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1_MASK) + .value("PseudoVFSLIDE1UP_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2) + .value("PseudoVFSLIDE1UP_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2_MASK) + .value("PseudoVFSLIDE1UP_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4) + .value("PseudoVFSLIDE1UP_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4_MASK) + .value("PseudoVFSLIDE1UP_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8) + .value("PseudoVFSLIDE1UP_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8_MASK) + .value("PseudoVFSLIDE1UP_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2) + .value("PseudoVFSLIDE1UP_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2_MASK) + .value("PseudoVFSLIDE1UP_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1) + .value("PseudoVFSLIDE1UP_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1_MASK) + .value("PseudoVFSLIDE1UP_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2) + .value("PseudoVFSLIDE1UP_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2_MASK) + .value("PseudoVFSLIDE1UP_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4) + .value("PseudoVFSLIDE1UP_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4_MASK) + .value("PseudoVFSLIDE1UP_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8) + .value("PseudoVFSLIDE1UP_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8_MASK) + .value("PseudoVFSQRT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16) + .value("PseudoVFSQRT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16_MASK) + .value("PseudoVFSQRT_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32) + .value("PseudoVFSQRT_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32_MASK) + .value("PseudoVFSQRT_V_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64) + .value("PseudoVFSQRT_V_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64_MASK) + .value("PseudoVFSQRT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16) + .value("PseudoVFSQRT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16_MASK) + .value("PseudoVFSQRT_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32) + .value("PseudoVFSQRT_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32_MASK) + .value("PseudoVFSQRT_V_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64) + .value("PseudoVFSQRT_V_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64_MASK) + .value("PseudoVFSQRT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16) + .value("PseudoVFSQRT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16_MASK) + .value("PseudoVFSQRT_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32) + .value("PseudoVFSQRT_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32_MASK) + .value("PseudoVFSQRT_V_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64) + .value("PseudoVFSQRT_V_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64_MASK) + .value("PseudoVFSQRT_V_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16) + .value("PseudoVFSQRT_V_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16_MASK) + .value("PseudoVFSQRT_V_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32) + .value("PseudoVFSQRT_V_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32_MASK) + .value("PseudoVFSQRT_V_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64) + .value("PseudoVFSQRT_V_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64_MASK) + .value("PseudoVFSQRT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16) + .value("PseudoVFSQRT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16_MASK) + .value("PseudoVFSQRT_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32) + .value("PseudoVFSQRT_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32_MASK) + .value("PseudoVFSQRT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16) + .value("PseudoVFSQRT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M1_E16) + .value("PseudoVFSUB_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M2_E16) + .value("PseudoVFSUB_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M4_E16) + .value("PseudoVFSUB_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M8_E16) + .value("PseudoVFSUB_ALT_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_M8_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_MF2_E16) + .value("PseudoVFSUB_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFSUB_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_MF4_E16) + .value("PseudoVFSUB_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFSUB_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M1_E16) + .value("PseudoVFSUB_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M1_E16_MASK) + .value("PseudoVFSUB_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M2_E16) + .value("PseudoVFSUB_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M2_E16_MASK) + .value("PseudoVFSUB_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M4_E16) + .value("PseudoVFSUB_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M4_E16_MASK) + .value("PseudoVFSUB_ALT_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M8_E16) + .value("PseudoVFSUB_ALT_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_M8_E16_MASK) + .value("PseudoVFSUB_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_MF2_E16) + .value("PseudoVFSUB_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_MF2_E16_MASK) + .value("PseudoVFSUB_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_MF4_E16) + .value("PseudoVFSUB_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_ALT_VV_MF4_E16_MASK) + .value("PseudoVFSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16) + .value("PseudoVFSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16_MASK) + .value("PseudoVFSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16) + .value("PseudoVFSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16_MASK) + .value("PseudoVFSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16) + .value("PseudoVFSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16_MASK) + .value("PseudoVFSUB_VFPR16_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16) + .value("PseudoVFSUB_VFPR16_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16_MASK) + .value("PseudoVFSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16) + .value("PseudoVFSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16_MASK) + .value("PseudoVFSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16) + .value("PseudoVFSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16_MASK) + .value("PseudoVFSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32) + .value("PseudoVFSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32_MASK) + .value("PseudoVFSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32) + .value("PseudoVFSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32_MASK) + .value("PseudoVFSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32) + .value("PseudoVFSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32_MASK) + .value("PseudoVFSUB_VFPR32_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32) + .value("PseudoVFSUB_VFPR32_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32_MASK) + .value("PseudoVFSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32) + .value("PseudoVFSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32_MASK) + .value("PseudoVFSUB_VFPR64_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64) + .value("PseudoVFSUB_VFPR64_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64_MASK) + .value("PseudoVFSUB_VFPR64_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64) + .value("PseudoVFSUB_VFPR64_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64_MASK) + .value("PseudoVFSUB_VFPR64_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64) + .value("PseudoVFSUB_VFPR64_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64_MASK) + .value("PseudoVFSUB_VFPR64_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64) + .value("PseudoVFSUB_VFPR64_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64_MASK) + .value("PseudoVFSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16) + .value("PseudoVFSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16_MASK) + .value("PseudoVFSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32) + .value("PseudoVFSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32_MASK) + .value("PseudoVFSUB_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64) + .value("PseudoVFSUB_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64_MASK) + .value("PseudoVFSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16) + .value("PseudoVFSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16_MASK) + .value("PseudoVFSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32) + .value("PseudoVFSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32_MASK) + .value("PseudoVFSUB_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64) + .value("PseudoVFSUB_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64_MASK) + .value("PseudoVFSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16) + .value("PseudoVFSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16_MASK) + .value("PseudoVFSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32) + .value("PseudoVFSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32_MASK) + .value("PseudoVFSUB_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64) + .value("PseudoVFSUB_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64_MASK) + .value("PseudoVFSUB_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16) + .value("PseudoVFSUB_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16_MASK) + .value("PseudoVFSUB_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32) + .value("PseudoVFSUB_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32_MASK) + .value("PseudoVFSUB_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64) + .value("PseudoVFSUB_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64_MASK) + .value("PseudoVFSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16) + .value("PseudoVFSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16_MASK) + .value("PseudoVFSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32) + .value("PseudoVFSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32_MASK) + .value("PseudoVFSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16) + .value("PseudoVFSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16_MASK) + .value("PseudoVFWADD_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M1_E16) + .value("PseudoVFWADD_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWADD_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M2_E16) + .value("PseudoVFWADD_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWADD_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M4_E16) + .value("PseudoVFWADD_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWADD_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_MF2_E16) + .value("PseudoVFWADD_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWADD_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_MF4_E16) + .value("PseudoVFWADD_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWADD_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M1_E16) + .value("PseudoVFWADD_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M1_E16_MASK) + .value("PseudoVFWADD_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M2_E16) + .value("PseudoVFWADD_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M2_E16_MASK) + .value("PseudoVFWADD_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M4_E16) + .value("PseudoVFWADD_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_M4_E16_MASK) + .value("PseudoVFWADD_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_MF2_E16) + .value("PseudoVFWADD_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWADD_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_MF4_E16) + .value("PseudoVFWADD_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWADD_ALT_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M1_E16) + .value("PseudoVFWADD_ALT_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M1_E16_MASK) + .value("PseudoVFWADD_ALT_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M2_E16) + .value("PseudoVFWADD_ALT_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M2_E16_MASK) + .value("PseudoVFWADD_ALT_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M4_E16) + .value("PseudoVFWADD_ALT_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_M4_E16_MASK) + .value("PseudoVFWADD_ALT_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_MF2_E16) + .value("PseudoVFWADD_ALT_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_MF2_E16_MASK) + .value("PseudoVFWADD_ALT_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_MF4_E16) + .value("PseudoVFWADD_ALT_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WFPR16_MF4_E16_MASK) + .value("PseudoVFWADD_ALT_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M1_E16) + .value("PseudoVFWADD_ALT_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M1_E16_MASK) + .value("PseudoVFWADD_ALT_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M1_E16_MASK_TIED) + .value("PseudoVFWADD_ALT_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M1_E16_TIED) + .value("PseudoVFWADD_ALT_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M2_E16) + .value("PseudoVFWADD_ALT_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M2_E16_MASK) + .value("PseudoVFWADD_ALT_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M2_E16_MASK_TIED) + .value("PseudoVFWADD_ALT_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M2_E16_TIED) + .value("PseudoVFWADD_ALT_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M4_E16) + .value("PseudoVFWADD_ALT_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M4_E16_MASK) + .value("PseudoVFWADD_ALT_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M4_E16_MASK_TIED) + .value("PseudoVFWADD_ALT_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_M4_E16_TIED) + .value("PseudoVFWADD_ALT_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF2_E16) + .value("PseudoVFWADD_ALT_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF2_E16_MASK) + .value("PseudoVFWADD_ALT_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF2_E16_MASK_TIED) + .value("PseudoVFWADD_ALT_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF2_E16_TIED) + .value("PseudoVFWADD_ALT_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF4_E16) + .value("PseudoVFWADD_ALT_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF4_E16_MASK) + .value("PseudoVFWADD_ALT_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF4_E16_MASK_TIED) + .value("PseudoVFWADD_ALT_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_ALT_WV_MF4_E16_TIED) + .value("PseudoVFWADD_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16) + .value("PseudoVFWADD_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16_MASK) + .value("PseudoVFWADD_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16) + .value("PseudoVFWADD_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16_MASK) + .value("PseudoVFWADD_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16) + .value("PseudoVFWADD_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16_MASK) + .value("PseudoVFWADD_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16) + .value("PseudoVFWADD_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16_MASK) + .value("PseudoVFWADD_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16) + .value("PseudoVFWADD_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16_MASK) + .value("PseudoVFWADD_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32) + .value("PseudoVFWADD_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32_MASK) + .value("PseudoVFWADD_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32) + .value("PseudoVFWADD_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32_MASK) + .value("PseudoVFWADD_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32) + .value("PseudoVFWADD_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32_MASK) + .value("PseudoVFWADD_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32) + .value("PseudoVFWADD_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32_MASK) + .value("PseudoVFWADD_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16) + .value("PseudoVFWADD_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16_MASK) + .value("PseudoVFWADD_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32) + .value("PseudoVFWADD_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32_MASK) + .value("PseudoVFWADD_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16) + .value("PseudoVFWADD_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16_MASK) + .value("PseudoVFWADD_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32) + .value("PseudoVFWADD_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32_MASK) + .value("PseudoVFWADD_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16) + .value("PseudoVFWADD_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16_MASK) + .value("PseudoVFWADD_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32) + .value("PseudoVFWADD_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32_MASK) + .value("PseudoVFWADD_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16) + .value("PseudoVFWADD_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16_MASK) + .value("PseudoVFWADD_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32) + .value("PseudoVFWADD_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32_MASK) + .value("PseudoVFWADD_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16) + .value("PseudoVFWADD_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16_MASK) + .value("PseudoVFWADD_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16) + .value("PseudoVFWADD_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16_MASK) + .value("PseudoVFWADD_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16) + .value("PseudoVFWADD_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16_MASK) + .value("PseudoVFWADD_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16) + .value("PseudoVFWADD_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16_MASK) + .value("PseudoVFWADD_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16) + .value("PseudoVFWADD_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16_MASK) + .value("PseudoVFWADD_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16) + .value("PseudoVFWADD_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16_MASK) + .value("PseudoVFWADD_WFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32) + .value("PseudoVFWADD_WFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32_MASK) + .value("PseudoVFWADD_WFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32) + .value("PseudoVFWADD_WFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32_MASK) + .value("PseudoVFWADD_WFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32) + .value("PseudoVFWADD_WFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32_MASK) + .value("PseudoVFWADD_WFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32) + .value("PseudoVFWADD_WFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32_MASK) + .value("PseudoVFWADD_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16) + .value("PseudoVFWADD_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK) + .value("PseudoVFWADD_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK_TIED) + .value("PseudoVFWADD_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_TIED) + .value("PseudoVFWADD_WV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32) + .value("PseudoVFWADD_WV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK) + .value("PseudoVFWADD_WV_M1_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK_TIED) + .value("PseudoVFWADD_WV_M1_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_TIED) + .value("PseudoVFWADD_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16) + .value("PseudoVFWADD_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK) + .value("PseudoVFWADD_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK_TIED) + .value("PseudoVFWADD_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_TIED) + .value("PseudoVFWADD_WV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32) + .value("PseudoVFWADD_WV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK) + .value("PseudoVFWADD_WV_M2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK_TIED) + .value("PseudoVFWADD_WV_M2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_TIED); + opcodes.value("PseudoVFWADD_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16) + .value("PseudoVFWADD_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK) + .value("PseudoVFWADD_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK_TIED) + .value("PseudoVFWADD_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_TIED) + .value("PseudoVFWADD_WV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32) + .value("PseudoVFWADD_WV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK) + .value("PseudoVFWADD_WV_M4_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK_TIED) + .value("PseudoVFWADD_WV_M4_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_TIED) + .value("PseudoVFWADD_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16) + .value("PseudoVFWADD_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK) + .value("PseudoVFWADD_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK_TIED) + .value("PseudoVFWADD_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_TIED) + .value("PseudoVFWADD_WV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32) + .value("PseudoVFWADD_WV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK) + .value("PseudoVFWADD_WV_MF2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK_TIED) + .value("PseudoVFWADD_WV_MF2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_TIED) + .value("PseudoVFWADD_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16) + .value("PseudoVFWADD_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK) + .value("PseudoVFWADD_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK_TIED) + .value("PseudoVFWADD_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_TIED) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M1_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M1_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M2_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M2_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M4_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_M4_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8) + .value("PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16) + .value("PseudoVFWCVTBF16_F_F_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32) + .value("PseudoVFWCVTBF16_F_F_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E8) + .value("PseudoVFWCVTBF16_F_F_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16) + .value("PseudoVFWCVTBF16_F_F_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32) + .value("PseudoVFWCVTBF16_F_F_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E8) + .value("PseudoVFWCVTBF16_F_F_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16) + .value("PseudoVFWCVTBF16_F_F_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32) + .value("PseudoVFWCVTBF16_F_F_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK) + .value("PseudoVFWCVTBF16_F_F_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E8) + .value("PseudoVFWCVTBF16_F_F_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E8) + .value("PseudoVFWCVTBF16_F_F_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16) + .value("PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E8) + .value("PseudoVFWCVTBF16_F_F_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E8_MASK) + .value("PseudoVFWCVTBF16_F_F_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF8_E8) + .value("PseudoVFWCVTBF16_F_F_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF8_E8_MASK) + .value("PseudoVFWCVT_F_F_ALT_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M1_E16) + .value("PseudoVFWCVT_F_F_ALT_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M1_E16_MASK) + .value("PseudoVFWCVT_F_F_ALT_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M2_E16) + .value("PseudoVFWCVT_F_F_ALT_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M2_E16_MASK) + .value("PseudoVFWCVT_F_F_ALT_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M4_E16) + .value("PseudoVFWCVT_F_F_ALT_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_M4_E16_MASK) + .value("PseudoVFWCVT_F_F_ALT_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_MF2_E16) + .value("PseudoVFWCVT_F_F_ALT_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_MF2_E16_MASK) + .value("PseudoVFWCVT_F_F_ALT_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_MF4_E16) + .value("PseudoVFWCVT_F_F_ALT_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_ALT_V_MF4_E16_MASK) + .value("PseudoVFWCVT_F_F_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16) + .value("PseudoVFWCVT_F_F_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16_MASK) + .value("PseudoVFWCVT_F_F_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32) + .value("PseudoVFWCVT_F_F_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32_MASK) + .value("PseudoVFWCVT_F_F_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16) + .value("PseudoVFWCVT_F_F_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16_MASK) + .value("PseudoVFWCVT_F_F_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32) + .value("PseudoVFWCVT_F_F_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32_MASK) + .value("PseudoVFWCVT_F_F_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16) + .value("PseudoVFWCVT_F_F_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16_MASK) + .value("PseudoVFWCVT_F_F_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32) + .value("PseudoVFWCVT_F_F_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32_MASK) + .value("PseudoVFWCVT_F_F_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16) + .value("PseudoVFWCVT_F_F_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16_MASK) + .value("PseudoVFWCVT_F_F_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32) + .value("PseudoVFWCVT_F_F_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32_MASK) + .value("PseudoVFWCVT_F_F_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16) + .value("PseudoVFWCVT_F_F_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M1_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M1_E8_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M2_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M2_E8_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M4_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_M4_E8_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF2_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF2_E8_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF4_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF4_E8_MASK) + .value("PseudoVFWCVT_F_XU_ALT_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF8_E8) + .value("PseudoVFWCVT_F_XU_ALT_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_ALT_V_MF8_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16) + .value("PseudoVFWCVT_F_XU_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16_MASK) + .value("PseudoVFWCVT_F_XU_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32) + .value("PseudoVFWCVT_F_XU_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32_MASK) + .value("PseudoVFWCVT_F_XU_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8) + .value("PseudoVFWCVT_F_XU_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16) + .value("PseudoVFWCVT_F_XU_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16_MASK) + .value("PseudoVFWCVT_F_XU_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32) + .value("PseudoVFWCVT_F_XU_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32_MASK) + .value("PseudoVFWCVT_F_XU_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8) + .value("PseudoVFWCVT_F_XU_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16) + .value("PseudoVFWCVT_F_XU_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16_MASK) + .value("PseudoVFWCVT_F_XU_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32) + .value("PseudoVFWCVT_F_XU_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32_MASK) + .value("PseudoVFWCVT_F_XU_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8) + .value("PseudoVFWCVT_F_XU_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16) + .value("PseudoVFWCVT_F_XU_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16_MASK) + .value("PseudoVFWCVT_F_XU_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32) + .value("PseudoVFWCVT_F_XU_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32_MASK) + .value("PseudoVFWCVT_F_XU_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8) + .value("PseudoVFWCVT_F_XU_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16) + .value("PseudoVFWCVT_F_XU_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16_MASK) + .value("PseudoVFWCVT_F_XU_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8) + .value("PseudoVFWCVT_F_XU_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8_MASK) + .value("PseudoVFWCVT_F_XU_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8) + .value("PseudoVFWCVT_F_XU_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M1_E8) + .value("PseudoVFWCVT_F_X_ALT_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M1_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M2_E8) + .value("PseudoVFWCVT_F_X_ALT_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M2_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M4_E8) + .value("PseudoVFWCVT_F_X_ALT_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_M4_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF2_E8) + .value("PseudoVFWCVT_F_X_ALT_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF2_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF4_E8) + .value("PseudoVFWCVT_F_X_ALT_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF4_E8_MASK) + .value("PseudoVFWCVT_F_X_ALT_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF8_E8) + .value("PseudoVFWCVT_F_X_ALT_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_ALT_V_MF8_E8_MASK) + .value("PseudoVFWCVT_F_X_V_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16) + .value("PseudoVFWCVT_F_X_V_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16_MASK) + .value("PseudoVFWCVT_F_X_V_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32) + .value("PseudoVFWCVT_F_X_V_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32_MASK) + .value("PseudoVFWCVT_F_X_V_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8) + .value("PseudoVFWCVT_F_X_V_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8_MASK) + .value("PseudoVFWCVT_F_X_V_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16) + .value("PseudoVFWCVT_F_X_V_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16_MASK) + .value("PseudoVFWCVT_F_X_V_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32) + .value("PseudoVFWCVT_F_X_V_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32_MASK) + .value("PseudoVFWCVT_F_X_V_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8) + .value("PseudoVFWCVT_F_X_V_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8_MASK) + .value("PseudoVFWCVT_F_X_V_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16) + .value("PseudoVFWCVT_F_X_V_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16_MASK) + .value("PseudoVFWCVT_F_X_V_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32) + .value("PseudoVFWCVT_F_X_V_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32_MASK) + .value("PseudoVFWCVT_F_X_V_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8) + .value("PseudoVFWCVT_F_X_V_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8_MASK) + .value("PseudoVFWCVT_F_X_V_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16) + .value("PseudoVFWCVT_F_X_V_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16_MASK) + .value("PseudoVFWCVT_F_X_V_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32) + .value("PseudoVFWCVT_F_X_V_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32_MASK) + .value("PseudoVFWCVT_F_X_V_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8) + .value("PseudoVFWCVT_F_X_V_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8_MASK) + .value("PseudoVFWCVT_F_X_V_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16) + .value("PseudoVFWCVT_F_X_V_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16_MASK) + .value("PseudoVFWCVT_F_X_V_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8) + .value("PseudoVFWCVT_F_X_V_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8_MASK) + .value("PseudoVFWCVT_F_X_V_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8) + .value("PseudoVFWCVT_F_X_V_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8_MASK) + .value("PseudoVFWCVT_RTZ_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1) + .value("PseudoVFWCVT_RTZ_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK) + .value("PseudoVFWCVT_RTZ_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2) + .value("PseudoVFWCVT_RTZ_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK) + .value("PseudoVFWCVT_RTZ_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4) + .value("PseudoVFWCVT_RTZ_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK) + .value("PseudoVFWCVT_RTZ_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2) + .value("PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK) + .value("PseudoVFWCVT_RTZ_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4) + .value("PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK) + .value("PseudoVFWCVT_RTZ_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1) + .value("PseudoVFWCVT_RTZ_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1_MASK) + .value("PseudoVFWCVT_RTZ_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2) + .value("PseudoVFWCVT_RTZ_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2_MASK) + .value("PseudoVFWCVT_RTZ_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4) + .value("PseudoVFWCVT_RTZ_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4_MASK) + .value("PseudoVFWCVT_RTZ_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2) + .value("PseudoVFWCVT_RTZ_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK) + .value("PseudoVFWCVT_RTZ_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4) + .value("PseudoVFWCVT_RTZ_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK) + .value("PseudoVFWCVT_XU_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1) + .value("PseudoVFWCVT_XU_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1_MASK) + .value("PseudoVFWCVT_XU_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2) + .value("PseudoVFWCVT_XU_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2_MASK) + .value("PseudoVFWCVT_XU_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4) + .value("PseudoVFWCVT_XU_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4_MASK) + .value("PseudoVFWCVT_XU_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2) + .value("PseudoVFWCVT_XU_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2_MASK) + .value("PseudoVFWCVT_XU_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4) + .value("PseudoVFWCVT_XU_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4_MASK) + .value("PseudoVFWCVT_X_F_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1) + .value("PseudoVFWCVT_X_F_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1_MASK) + .value("PseudoVFWCVT_X_F_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2) + .value("PseudoVFWCVT_X_F_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2_MASK) + .value("PseudoVFWCVT_X_F_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4) + .value("PseudoVFWCVT_X_F_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4_MASK) + .value("PseudoVFWCVT_X_F_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2) + .value("PseudoVFWCVT_X_F_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2_MASK) + .value("PseudoVFWCVT_X_F_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4) + .value("PseudoVFWCVT_X_F_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4_MASK) + .value("PseudoVFWMACCBF16_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16) + .value("PseudoVFWMACCBF16_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK) + .value("PseudoVFWMACCBF16_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16) + .value("PseudoVFWMACCBF16_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK) + .value("PseudoVFWMACCBF16_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16) + .value("PseudoVFWMACCBF16_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK) + .value("PseudoVFWMACCBF16_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16) + .value("PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMACCBF16_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16) + .value("PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMACCBF16_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16) + .value("PseudoVFWMACCBF16_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16_MASK) + .value("PseudoVFWMACCBF16_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32) + .value("PseudoVFWMACCBF16_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32_MASK) + .value("PseudoVFWMACCBF16_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16) + .value("PseudoVFWMACCBF16_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16_MASK) + .value("PseudoVFWMACCBF16_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32) + .value("PseudoVFWMACCBF16_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32_MASK) + .value("PseudoVFWMACCBF16_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16) + .value("PseudoVFWMACCBF16_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16_MASK) + .value("PseudoVFWMACCBF16_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32) + .value("PseudoVFWMACCBF16_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32_MASK) + .value("PseudoVFWMACCBF16_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16) + .value("PseudoVFWMACCBF16_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16_MASK) + .value("PseudoVFWMACCBF16_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32) + .value("PseudoVFWMACCBF16_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32_MASK) + .value("PseudoVFWMACCBF16_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16) + .value("PseudoVFWMACCBF16_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16_MASK) + .value("PseudoVFWMACC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M1_E16) + .value("PseudoVFWMACC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWMACC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M2_E16) + .value("PseudoVFWMACC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWMACC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M4_E16) + .value("PseudoVFWMACC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWMACC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_MF2_E16) + .value("PseudoVFWMACC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMACC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_MF4_E16) + .value("PseudoVFWMACC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMACC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M1_E16) + .value("PseudoVFWMACC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M1_E16_MASK) + .value("PseudoVFWMACC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M2_E16) + .value("PseudoVFWMACC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M2_E16_MASK) + .value("PseudoVFWMACC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M4_E16) + .value("PseudoVFWMACC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_M4_E16_MASK) + .value("PseudoVFWMACC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_MF2_E16) + .value("PseudoVFWMACC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWMACC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_MF4_E16) + .value("PseudoVFWMACC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16) + .value("PseudoVFWMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16_MASK) + .value("PseudoVFWMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16) + .value("PseudoVFWMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16_MASK) + .value("PseudoVFWMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16) + .value("PseudoVFWMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16_MASK) + .value("PseudoVFWMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16) + .value("PseudoVFWMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16) + .value("PseudoVFWMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32) + .value("PseudoVFWMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32_MASK) + .value("PseudoVFWMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32) + .value("PseudoVFWMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32_MASK) + .value("PseudoVFWMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32) + .value("PseudoVFWMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32_MASK) + .value("PseudoVFWMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32) + .value("PseudoVFWMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32_MASK) + .value("PseudoVFWMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16) + .value("PseudoVFWMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16_MASK) + .value("PseudoVFWMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32) + .value("PseudoVFWMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32_MASK) + .value("PseudoVFWMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16) + .value("PseudoVFWMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16_MASK) + .value("PseudoVFWMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32) + .value("PseudoVFWMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32_MASK) + .value("PseudoVFWMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16) + .value("PseudoVFWMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16_MASK) + .value("PseudoVFWMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32) + .value("PseudoVFWMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32_MASK) + .value("PseudoVFWMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16) + .value("PseudoVFWMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16_MASK) + .value("PseudoVFWMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32) + .value("PseudoVFWMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32_MASK) + .value("PseudoVFWMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16) + .value("PseudoVFWMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16_MASK) + .value("PseudoVFWMSAC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M1_E16) + .value("PseudoVFWMSAC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M1_E16_MASK); + opcodes.value("PseudoVFWMSAC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M2_E16) + .value("PseudoVFWMSAC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWMSAC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M4_E16) + .value("PseudoVFWMSAC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWMSAC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_MF2_E16) + .value("PseudoVFWMSAC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMSAC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_MF4_E16) + .value("PseudoVFWMSAC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMSAC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M1_E16) + .value("PseudoVFWMSAC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M1_E16_MASK) + .value("PseudoVFWMSAC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M2_E16) + .value("PseudoVFWMSAC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M2_E16_MASK) + .value("PseudoVFWMSAC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M4_E16) + .value("PseudoVFWMSAC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_M4_E16_MASK) + .value("PseudoVFWMSAC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_MF2_E16) + .value("PseudoVFWMSAC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWMSAC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_MF4_E16) + .value("PseudoVFWMSAC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16) + .value("PseudoVFWMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16_MASK) + .value("PseudoVFWMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16) + .value("PseudoVFWMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16_MASK) + .value("PseudoVFWMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16) + .value("PseudoVFWMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16_MASK) + .value("PseudoVFWMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16) + .value("PseudoVFWMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16) + .value("PseudoVFWMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32) + .value("PseudoVFWMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32_MASK) + .value("PseudoVFWMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32) + .value("PseudoVFWMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32_MASK) + .value("PseudoVFWMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32) + .value("PseudoVFWMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32_MASK) + .value("PseudoVFWMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32) + .value("PseudoVFWMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32_MASK) + .value("PseudoVFWMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16) + .value("PseudoVFWMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16_MASK) + .value("PseudoVFWMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32) + .value("PseudoVFWMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32_MASK) + .value("PseudoVFWMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16) + .value("PseudoVFWMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16_MASK) + .value("PseudoVFWMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32) + .value("PseudoVFWMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32_MASK) + .value("PseudoVFWMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16) + .value("PseudoVFWMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16_MASK) + .value("PseudoVFWMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32) + .value("PseudoVFWMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32_MASK) + .value("PseudoVFWMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16) + .value("PseudoVFWMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16_MASK) + .value("PseudoVFWMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32) + .value("PseudoVFWMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32_MASK) + .value("PseudoVFWMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16) + .value("PseudoVFWMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16_MASK) + .value("PseudoVFWMUL_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M1_E16) + .value("PseudoVFWMUL_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWMUL_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M2_E16) + .value("PseudoVFWMUL_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWMUL_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M4_E16) + .value("PseudoVFWMUL_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWMUL_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_MF2_E16) + .value("PseudoVFWMUL_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMUL_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_MF4_E16) + .value("PseudoVFWMUL_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMUL_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M1_E16) + .value("PseudoVFWMUL_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M1_E16_MASK) + .value("PseudoVFWMUL_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M2_E16) + .value("PseudoVFWMUL_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M2_E16_MASK) + .value("PseudoVFWMUL_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M4_E16) + .value("PseudoVFWMUL_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_M4_E16_MASK) + .value("PseudoVFWMUL_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_MF2_E16) + .value("PseudoVFWMUL_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWMUL_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_MF4_E16) + .value("PseudoVFWMUL_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWMUL_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16) + .value("PseudoVFWMUL_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16_MASK) + .value("PseudoVFWMUL_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16) + .value("PseudoVFWMUL_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16_MASK) + .value("PseudoVFWMUL_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16) + .value("PseudoVFWMUL_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16_MASK) + .value("PseudoVFWMUL_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16) + .value("PseudoVFWMUL_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16_MASK) + .value("PseudoVFWMUL_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16) + .value("PseudoVFWMUL_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16_MASK) + .value("PseudoVFWMUL_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32) + .value("PseudoVFWMUL_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32_MASK) + .value("PseudoVFWMUL_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32) + .value("PseudoVFWMUL_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32_MASK) + .value("PseudoVFWMUL_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32) + .value("PseudoVFWMUL_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32_MASK) + .value("PseudoVFWMUL_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32) + .value("PseudoVFWMUL_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32_MASK) + .value("PseudoVFWMUL_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16) + .value("PseudoVFWMUL_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16_MASK) + .value("PseudoVFWMUL_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32) + .value("PseudoVFWMUL_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32_MASK) + .value("PseudoVFWMUL_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16) + .value("PseudoVFWMUL_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16_MASK) + .value("PseudoVFWMUL_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32) + .value("PseudoVFWMUL_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32_MASK) + .value("PseudoVFWMUL_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16) + .value("PseudoVFWMUL_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16_MASK) + .value("PseudoVFWMUL_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32) + .value("PseudoVFWMUL_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32_MASK) + .value("PseudoVFWMUL_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16) + .value("PseudoVFWMUL_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16_MASK) + .value("PseudoVFWMUL_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32) + .value("PseudoVFWMUL_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32_MASK) + .value("PseudoVFWMUL_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16) + .value("PseudoVFWMUL_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16_MASK) + .value("PseudoVFWNMACC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M1_E16) + .value("PseudoVFWNMACC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWNMACC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M2_E16) + .value("PseudoVFWNMACC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWNMACC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M4_E16) + .value("PseudoVFWNMACC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWNMACC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_MF2_E16) + .value("PseudoVFWNMACC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWNMACC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_MF4_E16) + .value("PseudoVFWNMACC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWNMACC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M1_E16) + .value("PseudoVFWNMACC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M1_E16_MASK) + .value("PseudoVFWNMACC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M2_E16) + .value("PseudoVFWNMACC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M2_E16_MASK) + .value("PseudoVFWNMACC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M4_E16) + .value("PseudoVFWNMACC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_M4_E16_MASK) + .value("PseudoVFWNMACC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_MF2_E16) + .value("PseudoVFWNMACC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWNMACC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_MF4_E16) + .value("PseudoVFWNMACC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWNMACC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16) + .value("PseudoVFWNMACC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16_MASK) + .value("PseudoVFWNMACC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16) + .value("PseudoVFWNMACC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16_MASK) + .value("PseudoVFWNMACC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16) + .value("PseudoVFWNMACC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16_MASK) + .value("PseudoVFWNMACC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16) + .value("PseudoVFWNMACC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16_MASK) + .value("PseudoVFWNMACC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16) + .value("PseudoVFWNMACC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16_MASK) + .value("PseudoVFWNMACC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32) + .value("PseudoVFWNMACC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32_MASK) + .value("PseudoVFWNMACC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32) + .value("PseudoVFWNMACC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32_MASK) + .value("PseudoVFWNMACC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32) + .value("PseudoVFWNMACC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32_MASK) + .value("PseudoVFWNMACC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32) + .value("PseudoVFWNMACC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32_MASK) + .value("PseudoVFWNMACC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16) + .value("PseudoVFWNMACC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16_MASK) + .value("PseudoVFWNMACC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32) + .value("PseudoVFWNMACC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32_MASK) + .value("PseudoVFWNMACC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16) + .value("PseudoVFWNMACC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16_MASK) + .value("PseudoVFWNMACC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32) + .value("PseudoVFWNMACC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32_MASK) + .value("PseudoVFWNMACC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16) + .value("PseudoVFWNMACC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16_MASK) + .value("PseudoVFWNMACC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32) + .value("PseudoVFWNMACC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32_MASK) + .value("PseudoVFWNMACC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16) + .value("PseudoVFWNMACC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16_MASK) + .value("PseudoVFWNMACC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32) + .value("PseudoVFWNMACC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32_MASK) + .value("PseudoVFWNMACC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16) + .value("PseudoVFWNMACC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M1_E16) + .value("PseudoVFWNMSAC_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M2_E16) + .value("PseudoVFWNMSAC_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M4_E16) + .value("PseudoVFWNMSAC_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_MF2_E16) + .value("PseudoVFWNMSAC_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_MF4_E16) + .value("PseudoVFWNMSAC_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M1_E16) + .value("PseudoVFWNMSAC_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M1_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M2_E16) + .value("PseudoVFWNMSAC_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M2_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M4_E16) + .value("PseudoVFWNMSAC_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_M4_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_MF2_E16) + .value("PseudoVFWNMSAC_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWNMSAC_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_MF4_E16) + .value("PseudoVFWNMSAC_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWNMSAC_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16) + .value("PseudoVFWNMSAC_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16_MASK) + .value("PseudoVFWNMSAC_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16) + .value("PseudoVFWNMSAC_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16_MASK) + .value("PseudoVFWNMSAC_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16) + .value("PseudoVFWNMSAC_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16_MASK) + .value("PseudoVFWNMSAC_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16) + .value("PseudoVFWNMSAC_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK) + .value("PseudoVFWNMSAC_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16) + .value("PseudoVFWNMSAC_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK) + .value("PseudoVFWNMSAC_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32) + .value("PseudoVFWNMSAC_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32_MASK) + .value("PseudoVFWNMSAC_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32) + .value("PseudoVFWNMSAC_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32_MASK) + .value("PseudoVFWNMSAC_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32) + .value("PseudoVFWNMSAC_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32_MASK) + .value("PseudoVFWNMSAC_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32) + .value("PseudoVFWNMSAC_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK) + .value("PseudoVFWNMSAC_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16) + .value("PseudoVFWNMSAC_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16_MASK) + .value("PseudoVFWNMSAC_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32) + .value("PseudoVFWNMSAC_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32_MASK) + .value("PseudoVFWNMSAC_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16) + .value("PseudoVFWNMSAC_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16_MASK) + .value("PseudoVFWNMSAC_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32) + .value("PseudoVFWNMSAC_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32_MASK) + .value("PseudoVFWNMSAC_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16) + .value("PseudoVFWNMSAC_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16_MASK) + .value("PseudoVFWNMSAC_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32) + .value("PseudoVFWNMSAC_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32_MASK) + .value("PseudoVFWNMSAC_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16) + .value("PseudoVFWNMSAC_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16_MASK) + .value("PseudoVFWNMSAC_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32) + .value("PseudoVFWNMSAC_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32_MASK) + .value("PseudoVFWNMSAC_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16) + .value("PseudoVFWNMSAC_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16_MASK) + .value("PseudoVFWREDOSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16) + .value("PseudoVFWREDOSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16_MASK) + .value("PseudoVFWREDOSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32) + .value("PseudoVFWREDOSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32_MASK) + .value("PseudoVFWREDOSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16) + .value("PseudoVFWREDOSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16_MASK) + .value("PseudoVFWREDOSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32) + .value("PseudoVFWREDOSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32_MASK) + .value("PseudoVFWREDOSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16) + .value("PseudoVFWREDOSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16_MASK) + .value("PseudoVFWREDOSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32) + .value("PseudoVFWREDOSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32_MASK) + .value("PseudoVFWREDOSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16) + .value("PseudoVFWREDOSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16_MASK) + .value("PseudoVFWREDOSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32) + .value("PseudoVFWREDOSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32_MASK) + .value("PseudoVFWREDOSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16) + .value("PseudoVFWREDOSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16_MASK) + .value("PseudoVFWREDOSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32) + .value("PseudoVFWREDOSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32_MASK) + .value("PseudoVFWREDOSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16) + .value("PseudoVFWREDOSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16_MASK) + .value("PseudoVFWREDUSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16) + .value("PseudoVFWREDUSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16_MASK) + .value("PseudoVFWREDUSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32) + .value("PseudoVFWREDUSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32_MASK) + .value("PseudoVFWREDUSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16) + .value("PseudoVFWREDUSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16_MASK) + .value("PseudoVFWREDUSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32) + .value("PseudoVFWREDUSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32_MASK) + .value("PseudoVFWREDUSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16) + .value("PseudoVFWREDUSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16_MASK) + .value("PseudoVFWREDUSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32) + .value("PseudoVFWREDUSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32_MASK) + .value("PseudoVFWREDUSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16) + .value("PseudoVFWREDUSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16_MASK) + .value("PseudoVFWREDUSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32) + .value("PseudoVFWREDUSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32_MASK) + .value("PseudoVFWREDUSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16) + .value("PseudoVFWREDUSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16_MASK) + .value("PseudoVFWREDUSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32) + .value("PseudoVFWREDUSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32_MASK) + .value("PseudoVFWREDUSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16) + .value("PseudoVFWREDUSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16_MASK) + .value("PseudoVFWSUB_ALT_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M1_E16) + .value("PseudoVFWSUB_ALT_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M1_E16_MASK) + .value("PseudoVFWSUB_ALT_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M2_E16) + .value("PseudoVFWSUB_ALT_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M2_E16_MASK) + .value("PseudoVFWSUB_ALT_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M4_E16) + .value("PseudoVFWSUB_ALT_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_M4_E16_MASK) + .value("PseudoVFWSUB_ALT_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_MF2_E16) + .value("PseudoVFWSUB_ALT_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_MF2_E16_MASK) + .value("PseudoVFWSUB_ALT_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_MF4_E16) + .value("PseudoVFWSUB_ALT_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VFPR16_MF4_E16_MASK) + .value("PseudoVFWSUB_ALT_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M1_E16) + .value("PseudoVFWSUB_ALT_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M1_E16_MASK) + .value("PseudoVFWSUB_ALT_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M2_E16) + .value("PseudoVFWSUB_ALT_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M2_E16_MASK) + .value("PseudoVFWSUB_ALT_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M4_E16) + .value("PseudoVFWSUB_ALT_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_M4_E16_MASK) + .value("PseudoVFWSUB_ALT_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_MF2_E16) + .value("PseudoVFWSUB_ALT_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_MF2_E16_MASK) + .value("PseudoVFWSUB_ALT_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_MF4_E16) + .value("PseudoVFWSUB_ALT_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_VV_MF4_E16_MASK) + .value("PseudoVFWSUB_ALT_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M1_E16) + .value("PseudoVFWSUB_ALT_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M1_E16_MASK) + .value("PseudoVFWSUB_ALT_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M2_E16) + .value("PseudoVFWSUB_ALT_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M2_E16_MASK) + .value("PseudoVFWSUB_ALT_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M4_E16) + .value("PseudoVFWSUB_ALT_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_M4_E16_MASK) + .value("PseudoVFWSUB_ALT_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_MF2_E16) + .value("PseudoVFWSUB_ALT_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_MF2_E16_MASK) + .value("PseudoVFWSUB_ALT_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_MF4_E16) + .value("PseudoVFWSUB_ALT_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WFPR16_MF4_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M1_E16) + .value("PseudoVFWSUB_ALT_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M1_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M1_E16_MASK_TIED) + .value("PseudoVFWSUB_ALT_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M1_E16_TIED); + opcodes.value("PseudoVFWSUB_ALT_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M2_E16) + .value("PseudoVFWSUB_ALT_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M2_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M2_E16_MASK_TIED) + .value("PseudoVFWSUB_ALT_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M2_E16_TIED) + .value("PseudoVFWSUB_ALT_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M4_E16) + .value("PseudoVFWSUB_ALT_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M4_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M4_E16_MASK_TIED) + .value("PseudoVFWSUB_ALT_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_M4_E16_TIED) + .value("PseudoVFWSUB_ALT_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF2_E16) + .value("PseudoVFWSUB_ALT_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF2_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF2_E16_MASK_TIED) + .value("PseudoVFWSUB_ALT_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF2_E16_TIED) + .value("PseudoVFWSUB_ALT_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF4_E16) + .value("PseudoVFWSUB_ALT_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF4_E16_MASK) + .value("PseudoVFWSUB_ALT_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF4_E16_MASK_TIED) + .value("PseudoVFWSUB_ALT_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_ALT_WV_MF4_E16_TIED) + .value("PseudoVFWSUB_VFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16) + .value("PseudoVFWSUB_VFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16_MASK) + .value("PseudoVFWSUB_VFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16) + .value("PseudoVFWSUB_VFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16_MASK) + .value("PseudoVFWSUB_VFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16) + .value("PseudoVFWSUB_VFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16_MASK) + .value("PseudoVFWSUB_VFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16) + .value("PseudoVFWSUB_VFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16_MASK) + .value("PseudoVFWSUB_VFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16) + .value("PseudoVFWSUB_VFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16_MASK) + .value("PseudoVFWSUB_VFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32) + .value("PseudoVFWSUB_VFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32_MASK) + .value("PseudoVFWSUB_VFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32) + .value("PseudoVFWSUB_VFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32_MASK) + .value("PseudoVFWSUB_VFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32) + .value("PseudoVFWSUB_VFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32_MASK) + .value("PseudoVFWSUB_VFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32) + .value("PseudoVFWSUB_VFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32_MASK) + .value("PseudoVFWSUB_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16) + .value("PseudoVFWSUB_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16_MASK) + .value("PseudoVFWSUB_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32) + .value("PseudoVFWSUB_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32_MASK) + .value("PseudoVFWSUB_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16) + .value("PseudoVFWSUB_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16_MASK) + .value("PseudoVFWSUB_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32) + .value("PseudoVFWSUB_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32_MASK) + .value("PseudoVFWSUB_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16) + .value("PseudoVFWSUB_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16_MASK) + .value("PseudoVFWSUB_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32) + .value("PseudoVFWSUB_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32_MASK) + .value("PseudoVFWSUB_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16) + .value("PseudoVFWSUB_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16_MASK) + .value("PseudoVFWSUB_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32) + .value("PseudoVFWSUB_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32_MASK) + .value("PseudoVFWSUB_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16) + .value("PseudoVFWSUB_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16_MASK) + .value("PseudoVFWSUB_WFPR16_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16) + .value("PseudoVFWSUB_WFPR16_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16_MASK) + .value("PseudoVFWSUB_WFPR16_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16) + .value("PseudoVFWSUB_WFPR16_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16_MASK) + .value("PseudoVFWSUB_WFPR16_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16) + .value("PseudoVFWSUB_WFPR16_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16_MASK) + .value("PseudoVFWSUB_WFPR16_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16) + .value("PseudoVFWSUB_WFPR16_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16_MASK) + .value("PseudoVFWSUB_WFPR16_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16) + .value("PseudoVFWSUB_WFPR16_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16_MASK) + .value("PseudoVFWSUB_WFPR32_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32) + .value("PseudoVFWSUB_WFPR32_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32_MASK) + .value("PseudoVFWSUB_WFPR32_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32) + .value("PseudoVFWSUB_WFPR32_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32_MASK) + .value("PseudoVFWSUB_WFPR32_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32) + .value("PseudoVFWSUB_WFPR32_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32_MASK) + .value("PseudoVFWSUB_WFPR32_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32) + .value("PseudoVFWSUB_WFPR32_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32_MASK) + .value("PseudoVFWSUB_WV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16) + .value("PseudoVFWSUB_WV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK) + .value("PseudoVFWSUB_WV_M1_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK_TIED) + .value("PseudoVFWSUB_WV_M1_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_TIED) + .value("PseudoVFWSUB_WV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32) + .value("PseudoVFWSUB_WV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK) + .value("PseudoVFWSUB_WV_M1_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK_TIED) + .value("PseudoVFWSUB_WV_M1_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_TIED) + .value("PseudoVFWSUB_WV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16) + .value("PseudoVFWSUB_WV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK) + .value("PseudoVFWSUB_WV_M2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK_TIED) + .value("PseudoVFWSUB_WV_M2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_TIED) + .value("PseudoVFWSUB_WV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32) + .value("PseudoVFWSUB_WV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK) + .value("PseudoVFWSUB_WV_M2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK_TIED) + .value("PseudoVFWSUB_WV_M2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_TIED) + .value("PseudoVFWSUB_WV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16) + .value("PseudoVFWSUB_WV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK) + .value("PseudoVFWSUB_WV_M4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK_TIED) + .value("PseudoVFWSUB_WV_M4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_TIED) + .value("PseudoVFWSUB_WV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32) + .value("PseudoVFWSUB_WV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK) + .value("PseudoVFWSUB_WV_M4_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK_TIED) + .value("PseudoVFWSUB_WV_M4_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_TIED) + .value("PseudoVFWSUB_WV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16) + .value("PseudoVFWSUB_WV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK) + .value("PseudoVFWSUB_WV_MF2_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK_TIED) + .value("PseudoVFWSUB_WV_MF2_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_TIED) + .value("PseudoVFWSUB_WV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32) + .value("PseudoVFWSUB_WV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK) + .value("PseudoVFWSUB_WV_MF2_E32_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK_TIED) + .value("PseudoVFWSUB_WV_MF2_E32_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_TIED) + .value("PseudoVFWSUB_WV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16) + .value("PseudoVFWSUB_WV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK) + .value("PseudoVFWSUB_WV_MF4_E16_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK_TIED) + .value("PseudoVFWSUB_WV_MF4_E16_TIED", LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_TIED) + .value("PseudoVGHSH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M1) + .value("PseudoVGHSH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M2) + .value("PseudoVGHSH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M4) + .value("PseudoVGHSH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M8) + .value("PseudoVGHSH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_MF2) + .value("PseudoVGMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M1) + .value("PseudoVGMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M2) + .value("PseudoVGMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M4) + .value("PseudoVGMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M8) + .value("PseudoVGMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_MF2) + .value("PseudoVID_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1) + .value("PseudoVID_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1_MASK) + .value("PseudoVID_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2) + .value("PseudoVID_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2_MASK) + .value("PseudoVID_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4) + .value("PseudoVID_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4_MASK) + .value("PseudoVID_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8) + .value("PseudoVID_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8_MASK) + .value("PseudoVID_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2) + .value("PseudoVID_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2_MASK) + .value("PseudoVID_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4) + .value("PseudoVID_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4_MASK) + .value("PseudoVID_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8) + .value("PseudoVID_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8_MASK) + .value("PseudoVIOTA_M_M1", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1) + .value("PseudoVIOTA_M_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1_MASK) + .value("PseudoVIOTA_M_M2", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2) + .value("PseudoVIOTA_M_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2_MASK) + .value("PseudoVIOTA_M_M4", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4) + .value("PseudoVIOTA_M_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4_MASK) + .value("PseudoVIOTA_M_M8", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8) + .value("PseudoVIOTA_M_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8_MASK) + .value("PseudoVIOTA_M_MF2", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2) + .value("PseudoVIOTA_M_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2_MASK) + .value("PseudoVIOTA_M_MF4", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4) + .value("PseudoVIOTA_M_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4_MASK) + .value("PseudoVIOTA_M_MF8", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8) + .value("PseudoVIOTA_M_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8_MASK) + .value("PseudoVLE16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1) + .value("PseudoVLE16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1_MASK) + .value("PseudoVLE16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2) + .value("PseudoVLE16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2_MASK) + .value("PseudoVLE16FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4) + .value("PseudoVLE16FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4_MASK) + .value("PseudoVLE16FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8) + .value("PseudoVLE16FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8_MASK) + .value("PseudoVLE16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2) + .value("PseudoVLE16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2_MASK) + .value("PseudoVLE16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4) + .value("PseudoVLE16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4_MASK) + .value("PseudoVLE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1) + .value("PseudoVLE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1_MASK) + .value("PseudoVLE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2) + .value("PseudoVLE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2_MASK) + .value("PseudoVLE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4) + .value("PseudoVLE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4_MASK) + .value("PseudoVLE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8) + .value("PseudoVLE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8_MASK) + .value("PseudoVLE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2) + .value("PseudoVLE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2_MASK) + .value("PseudoVLE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4) + .value("PseudoVLE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4_MASK) + .value("PseudoVLE32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1) + .value("PseudoVLE32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1_MASK) + .value("PseudoVLE32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2) + .value("PseudoVLE32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2_MASK) + .value("PseudoVLE32FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4) + .value("PseudoVLE32FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4_MASK) + .value("PseudoVLE32FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8) + .value("PseudoVLE32FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8_MASK) + .value("PseudoVLE32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2) + .value("PseudoVLE32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2_MASK) + .value("PseudoVLE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1) + .value("PseudoVLE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1_MASK) + .value("PseudoVLE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2) + .value("PseudoVLE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2_MASK) + .value("PseudoVLE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4) + .value("PseudoVLE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4_MASK) + .value("PseudoVLE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8) + .value("PseudoVLE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8_MASK) + .value("PseudoVLE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2) + .value("PseudoVLE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2_MASK) + .value("PseudoVLE64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1) + .value("PseudoVLE64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1_MASK) + .value("PseudoVLE64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2) + .value("PseudoVLE64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2_MASK) + .value("PseudoVLE64FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4) + .value("PseudoVLE64FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4_MASK) + .value("PseudoVLE64FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8) + .value("PseudoVLE64FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8_MASK) + .value("PseudoVLE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1) + .value("PseudoVLE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1_MASK) + .value("PseudoVLE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2) + .value("PseudoVLE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2_MASK) + .value("PseudoVLE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4) + .value("PseudoVLE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4_MASK) + .value("PseudoVLE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8) + .value("PseudoVLE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8_MASK) + .value("PseudoVLE8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1) + .value("PseudoVLE8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1_MASK) + .value("PseudoVLE8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2) + .value("PseudoVLE8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2_MASK) + .value("PseudoVLE8FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4) + .value("PseudoVLE8FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4_MASK) + .value("PseudoVLE8FF_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8) + .value("PseudoVLE8FF_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8_MASK) + .value("PseudoVLE8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2) + .value("PseudoVLE8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2_MASK) + .value("PseudoVLE8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4) + .value("PseudoVLE8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4_MASK) + .value("PseudoVLE8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8) + .value("PseudoVLE8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8_MASK) + .value("PseudoVLE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1) + .value("PseudoVLE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1_MASK) + .value("PseudoVLE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2) + .value("PseudoVLE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2_MASK) + .value("PseudoVLE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4) + .value("PseudoVLE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4_MASK) + .value("PseudoVLE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8) + .value("PseudoVLE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8_MASK) + .value("PseudoVLE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2) + .value("PseudoVLE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2_MASK) + .value("PseudoVLE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4) + .value("PseudoVLE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4_MASK) + .value("PseudoVLE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8) + .value("PseudoVLE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8_MASK) + .value("PseudoVLM_V_B1", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B1) + .value("PseudoVLM_V_B16", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B16) + .value("PseudoVLM_V_B2", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B2) + .value("PseudoVLM_V_B32", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B32) + .value("PseudoVLM_V_B4", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B4) + .value("PseudoVLM_V_B64", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B64) + .value("PseudoVLM_V_B8", LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B8) + .value("PseudoVLOXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1) + .value("PseudoVLOXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1_MASK) + .value("PseudoVLOXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2) + .value("PseudoVLOXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2_MASK) + .value("PseudoVLOXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4) + .value("PseudoVLOXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4_MASK) + .value("PseudoVLOXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2) + .value("PseudoVLOXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2_MASK) + .value("PseudoVLOXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1) + .value("PseudoVLOXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1_MASK) + .value("PseudoVLOXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2) + .value("PseudoVLOXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2_MASK) + .value("PseudoVLOXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4) + .value("PseudoVLOXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4_MASK) + .value("PseudoVLOXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8) + .value("PseudoVLOXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8_MASK) + .value("PseudoVLOXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2) + .value("PseudoVLOXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2_MASK) + .value("PseudoVLOXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4) + .value("PseudoVLOXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4_MASK) + .value("PseudoVLOXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8) + .value("PseudoVLOXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8_MASK) + .value("PseudoVLOXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4) + .value("PseudoVLOXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4_MASK) + .value("PseudoVLOXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8) + .value("PseudoVLOXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8_MASK) + .value("PseudoVLOXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1) + .value("PseudoVLOXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1_MASK) + .value("PseudoVLOXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2) + .value("PseudoVLOXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2_MASK) + .value("PseudoVLOXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2) + .value("PseudoVLOXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2_MASK) + .value("PseudoVLOXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4) + .value("PseudoVLOXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4_MASK) + .value("PseudoVLOXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1) + .value("PseudoVLOXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1_MASK) + .value("PseudoVLOXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2) + .value("PseudoVLOXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2_MASK) + .value("PseudoVLOXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4) + .value("PseudoVLOXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4_MASK) + .value("PseudoVLOXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8) + .value("PseudoVLOXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8_MASK) + .value("PseudoVLOXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1) + .value("PseudoVLOXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1_MASK) + .value("PseudoVLOXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2) + .value("PseudoVLOXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2_MASK) + .value("PseudoVLOXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2) + .value("PseudoVLOXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2_MASK) + .value("PseudoVLOXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4) + .value("PseudoVLOXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4_MASK) + .value("PseudoVLOXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1) + .value("PseudoVLOXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1_MASK) + .value("PseudoVLOXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2) + .value("PseudoVLOXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2_MASK) + .value("PseudoVLOXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4) + .value("PseudoVLOXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4_MASK) + .value("PseudoVLOXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2) + .value("PseudoVLOXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2_MASK) + .value("PseudoVLOXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1) + .value("PseudoVLOXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1_MASK) + .value("PseudoVLOXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2); + opcodes.value("PseudoVLOXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2_MASK) + .value("PseudoVLOXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4) + .value("PseudoVLOXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4_MASK) + .value("PseudoVLOXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8) + .value("PseudoVLOXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8_MASK) + .value("PseudoVLOXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2) + .value("PseudoVLOXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2_MASK) + .value("PseudoVLOXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4) + .value("PseudoVLOXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4_MASK) + .value("PseudoVLOXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8) + .value("PseudoVLOXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8_MASK) + .value("PseudoVLOXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1) + .value("PseudoVLOXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1_MASK) + .value("PseudoVLOXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2) + .value("PseudoVLOXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2_MASK) + .value("PseudoVLOXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4) + .value("PseudoVLOXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4_MASK) + .value("PseudoVLOXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8) + .value("PseudoVLOXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8_MASK) + .value("PseudoVLOXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1) + .value("PseudoVLOXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1_MASK) + .value("PseudoVLOXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2) + .value("PseudoVLOXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2_MASK) + .value("PseudoVLOXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4) + .value("PseudoVLOXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4_MASK) + .value("PseudoVLOXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8) + .value("PseudoVLOXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8_MASK) + .value("PseudoVLOXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1) + .value("PseudoVLOXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1_MASK) + .value("PseudoVLOXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2) + .value("PseudoVLOXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2_MASK) + .value("PseudoVLOXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2) + .value("PseudoVLOXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2_MASK) + .value("PseudoVLOXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4) + .value("PseudoVLOXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4_MASK) + .value("PseudoVLOXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1) + .value("PseudoVLOXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1_MASK) + .value("PseudoVLOXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2) + .value("PseudoVLOXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2_MASK) + .value("PseudoVLOXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4) + .value("PseudoVLOXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4_MASK) + .value("PseudoVLOXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2) + .value("PseudoVLOXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2_MASK) + .value("PseudoVLOXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1) + .value("PseudoVLOXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1_MASK) + .value("PseudoVLOXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2) + .value("PseudoVLOXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2_MASK) + .value("PseudoVLOXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4) + .value("PseudoVLOXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4_MASK) + .value("PseudoVLOXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8) + .value("PseudoVLOXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8_MASK) + .value("PseudoVLOXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1) + .value("PseudoVLOXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1_MASK) + .value("PseudoVLOXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2) + .value("PseudoVLOXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2_MASK) + .value("PseudoVLOXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4) + .value("PseudoVLOXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4_MASK) + .value("PseudoVLOXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8) + .value("PseudoVLOXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8_MASK) + .value("PseudoVLOXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2) + .value("PseudoVLOXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2_MASK) + .value("PseudoVLOXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4) + .value("PseudoVLOXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4_MASK) + .value("PseudoVLOXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8) + .value("PseudoVLOXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8_MASK) + .value("PseudoVLOXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4) + .value("PseudoVLOXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4_MASK) + .value("PseudoVLOXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8) + .value("PseudoVLOXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8_MASK) + .value("PseudoVLOXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8) + .value("PseudoVLOXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8_MASK) + .value("PseudoVLOXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1) + .value("PseudoVLOXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1_MASK) + .value("PseudoVLOXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2) + .value("PseudoVLOXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2_MASK) + .value("PseudoVLOXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4) + .value("PseudoVLOXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4_MASK) + .value("PseudoVLOXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2) + .value("PseudoVLOXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2_MASK) + .value("PseudoVLOXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1) + .value("PseudoVLOXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1_MASK) + .value("PseudoVLOXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2) + .value("PseudoVLOXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2_MASK) + .value("PseudoVLOXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2) + .value("PseudoVLOXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2_MASK) + .value("PseudoVLOXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4) + .value("PseudoVLOXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4_MASK) + .value("PseudoVLOXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1) + .value("PseudoVLOXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1_MASK) + .value("PseudoVLOXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2) + .value("PseudoVLOXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2_MASK) + .value("PseudoVLOXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4) + .value("PseudoVLOXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4_MASK) + .value("PseudoVLOXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8) + .value("PseudoVLOXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1) + .value("PseudoVLOXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2) + .value("PseudoVLOXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2_MASK) + .value("PseudoVLOXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4) + .value("PseudoVLOXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4_MASK) + .value("PseudoVLOXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2) + .value("PseudoVLOXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1) + .value("PseudoVLOXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2) + .value("PseudoVLOXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2_MASK) + .value("PseudoVLOXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4) + .value("PseudoVLOXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4_MASK) + .value("PseudoVLOXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2) + .value("PseudoVLOXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2_MASK) + .value("PseudoVLOXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4) + .value("PseudoVLOXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4_MASK) + .value("PseudoVLOXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4) + .value("PseudoVLOXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4_MASK) + .value("PseudoVLOXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1) + .value("PseudoVLOXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2) + .value("PseudoVLOXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2_MASK) + .value("PseudoVLOXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2) + .value("PseudoVLOXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4) + .value("PseudoVLOXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1) + .value("PseudoVLOXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2) + .value("PseudoVLOXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4) + .value("PseudoVLOXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8) + .value("PseudoVLOXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1) + .value("PseudoVLOXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2) + .value("PseudoVLOXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2_MASK) + .value("PseudoVLOXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2) + .value("PseudoVLOXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4) + .value("PseudoVLOXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1) + .value("PseudoVLOXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2) + .value("PseudoVLOXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2_MASK) + .value("PseudoVLOXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4) + .value("PseudoVLOXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4_MASK) + .value("PseudoVLOXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2) + .value("PseudoVLOXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1) + .value("PseudoVLOXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2) + .value("PseudoVLOXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2_MASK) + .value("PseudoVLOXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4) + .value("PseudoVLOXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4_MASK) + .value("PseudoVLOXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2) + .value("PseudoVLOXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2_MASK) + .value("PseudoVLOXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4) + .value("PseudoVLOXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4_MASK) + .value("PseudoVLOXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1) + .value("PseudoVLOXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2) + .value("PseudoVLOXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4) + .value("PseudoVLOXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8) + .value("PseudoVLOXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1) + .value("PseudoVLOXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2) + .value("PseudoVLOXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4) + .value("PseudoVLOXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8) + .value("PseudoVLOXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1) + .value("PseudoVLOXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2) + .value("PseudoVLOXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2_MASK) + .value("PseudoVLOXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2) + .value("PseudoVLOXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4) + .value("PseudoVLOXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1) + .value("PseudoVLOXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2) + .value("PseudoVLOXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2_MASK) + .value("PseudoVLOXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4) + .value("PseudoVLOXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4_MASK) + .value("PseudoVLOXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2) + .value("PseudoVLOXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1) + .value("PseudoVLOXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2) + .value("PseudoVLOXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2_MASK) + .value("PseudoVLOXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4) + .value("PseudoVLOXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4_MASK) + .value("PseudoVLOXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1) + .value("PseudoVLOXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2) + .value("PseudoVLOXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2_MASK) + .value("PseudoVLOXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4) + .value("PseudoVLOXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4_MASK) + .value("PseudoVLOXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2) + .value("PseudoVLOXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2_MASK) + .value("PseudoVLOXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4) + .value("PseudoVLOXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4_MASK) + .value("PseudoVLOXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4) + .value("PseudoVLOXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4_MASK) + .value("PseudoVLOXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1) + .value("PseudoVLOXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2) + .value("PseudoVLOXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2_MASK) + .value("PseudoVLOXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4) + .value("PseudoVLOXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4_MASK) + .value("PseudoVLOXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2) + .value("PseudoVLOXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1) + .value("PseudoVLOXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2) + .value("PseudoVLOXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2_MASK) + .value("PseudoVLOXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2) + .value("PseudoVLOXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4) + .value("PseudoVLOXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1) + .value("PseudoVLOXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2) + .value("PseudoVLOXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4) + .value("PseudoVLOXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8) + .value("PseudoVLOXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1) + .value("PseudoVLOXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2) + .value("PseudoVLOXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2_MASK) + .value("PseudoVLOXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2) + .value("PseudoVLOXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1) + .value("PseudoVLOXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2) + .value("PseudoVLOXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2_MASK) + .value("PseudoVLOXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2) + .value("PseudoVLOXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2_MASK) + .value("PseudoVLOXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1) + .value("PseudoVLOXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2) + .value("PseudoVLOXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2_MASK) + .value("PseudoVLOXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2) + .value("PseudoVLOXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4) + .value("PseudoVLOXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1) + .value("PseudoVLOXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2) + .value("PseudoVLOXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4) + .value("PseudoVLOXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8) + .value("PseudoVLOXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1) + .value("PseudoVLOXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2) + .value("PseudoVLOXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2_MASK) + .value("PseudoVLOXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2) + .value("PseudoVLOXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4) + .value("PseudoVLOXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1) + .value("PseudoVLOXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2) + .value("PseudoVLOXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2_MASK) + .value("PseudoVLOXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2) + .value("PseudoVLOXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1) + .value("PseudoVLOXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2) + .value("PseudoVLOXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2_MASK) + .value("PseudoVLOXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2) + .value("PseudoVLOXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2_MASK) + .value("PseudoVLOXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1) + .value("PseudoVLOXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2) + .value("PseudoVLOXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4) + .value("PseudoVLOXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8) + .value("PseudoVLOXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1) + .value("PseudoVLOXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2) + .value("PseudoVLOXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4) + .value("PseudoVLOXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8) + .value("PseudoVLOXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1) + .value("PseudoVLOXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2) + .value("PseudoVLOXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2_MASK) + .value("PseudoVLOXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2); + opcodes.value("PseudoVLOXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4) + .value("PseudoVLOXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1) + .value("PseudoVLOXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2) + .value("PseudoVLOXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2_MASK) + .value("PseudoVLOXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2) + .value("PseudoVLOXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1) + .value("PseudoVLOXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2) + .value("PseudoVLOXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2_MASK) + .value("PseudoVLOXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1) + .value("PseudoVLOXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2) + .value("PseudoVLOXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2_MASK) + .value("PseudoVLOXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2) + .value("PseudoVLOXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1) + .value("PseudoVLOXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2) + .value("PseudoVLOXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2) + .value("PseudoVLOXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1) + .value("PseudoVLOXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2) + .value("PseudoVLOXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2) + .value("PseudoVLOXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4) + .value("PseudoVLOXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1) + .value("PseudoVLOXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2) + .value("PseudoVLOXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4) + .value("PseudoVLOXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8) + .value("PseudoVLOXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1) + .value("PseudoVLOXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2) + .value("PseudoVLOXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2_MASK) + .value("PseudoVLOXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2) + .value("PseudoVLOXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1) + .value("PseudoVLOXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2) + .value("PseudoVLOXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2_MASK) + .value("PseudoVLOXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2) + .value("PseudoVLOXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2_MASK) + .value("PseudoVLOXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1) + .value("PseudoVLOXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2) + .value("PseudoVLOXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2_MASK) + .value("PseudoVLOXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2) + .value("PseudoVLOXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4) + .value("PseudoVLOXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1) + .value("PseudoVLOXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2) + .value("PseudoVLOXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4) + .value("PseudoVLOXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8) + .value("PseudoVLOXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1) + .value("PseudoVLOXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2) + .value("PseudoVLOXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2_MASK) + .value("PseudoVLOXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2) + .value("PseudoVLOXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4) + .value("PseudoVLOXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1) + .value("PseudoVLOXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2) + .value("PseudoVLOXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2_MASK) + .value("PseudoVLOXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2) + .value("PseudoVLOXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1) + .value("PseudoVLOXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2) + .value("PseudoVLOXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2_MASK) + .value("PseudoVLOXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2) + .value("PseudoVLOXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2_MASK) + .value("PseudoVLOXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1) + .value("PseudoVLOXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2) + .value("PseudoVLOXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4) + .value("PseudoVLOXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8) + .value("PseudoVLOXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1) + .value("PseudoVLOXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2) + .value("PseudoVLOXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4) + .value("PseudoVLOXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8) + .value("PseudoVLOXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1) + .value("PseudoVLOXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2) + .value("PseudoVLOXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2_MASK) + .value("PseudoVLOXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2) + .value("PseudoVLOXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4) + .value("PseudoVLOXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1) + .value("PseudoVLOXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2) + .value("PseudoVLOXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2_MASK) + .value("PseudoVLOXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2) + .value("PseudoVLOXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1) + .value("PseudoVLOXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2) + .value("PseudoVLOXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2_MASK) + .value("PseudoVLOXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1) + .value("PseudoVLOXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2) + .value("PseudoVLOXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2_MASK) + .value("PseudoVLOXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2) + .value("PseudoVLOXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1) + .value("PseudoVLOXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2) + .value("PseudoVLOXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2) + .value("PseudoVLOXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1) + .value("PseudoVLOXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2) + .value("PseudoVLOXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2) + .value("PseudoVLOXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4) + .value("PseudoVLOXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1) + .value("PseudoVLOXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2) + .value("PseudoVLOXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4) + .value("PseudoVLOXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8) + .value("PseudoVLOXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1) + .value("PseudoVLOXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2) + .value("PseudoVLOXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1) + .value("PseudoVLOXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1) + .value("PseudoVLOXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2) + .value("PseudoVLOXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4) + .value("PseudoVLOXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1) + .value("PseudoVLOXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2) + .value("PseudoVLOXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4) + .value("PseudoVLOXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8) + .value("PseudoVLOXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1) + .value("PseudoVLOXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2) + .value("PseudoVLOXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4) + .value("PseudoVLOXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1) + .value("PseudoVLOXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2) + .value("PseudoVLOXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1) + .value("PseudoVLOXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1) + .value("PseudoVLOXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2) + .value("PseudoVLOXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4) + .value("PseudoVLOXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8) + .value("PseudoVLOXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1) + .value("PseudoVLOXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2) + .value("PseudoVLOXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4) + .value("PseudoVLOXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8) + .value("PseudoVLOXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1) + .value("PseudoVLOXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2) + .value("PseudoVLOXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4) + .value("PseudoVLOXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1) + .value("PseudoVLOXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2) + .value("PseudoVLOXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1) + .value("PseudoVLOXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1) + .value("PseudoVLOXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1) + .value("PseudoVLOXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2) + .value("PseudoVLOXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1) + .value("PseudoVLOXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2) + .value("PseudoVLOXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4) + .value("PseudoVLOXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1) + .value("PseudoVLOXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2) + .value("PseudoVLOXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4) + .value("PseudoVLOXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8) + .value("PseudoVLOXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1) + .value("PseudoVLOXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2) + .value("PseudoVLOXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1) + .value("PseudoVLOXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1) + .value("PseudoVLOXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2) + .value("PseudoVLOXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4) + .value("PseudoVLOXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1) + .value("PseudoVLOXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2) + .value("PseudoVLOXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4) + .value("PseudoVLOXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8) + .value("PseudoVLOXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1) + .value("PseudoVLOXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2) + .value("PseudoVLOXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4) + .value("PseudoVLOXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1) + .value("PseudoVLOXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2) + .value("PseudoVLOXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1) + .value("PseudoVLOXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1) + .value("PseudoVLOXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2) + .value("PseudoVLOXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4) + .value("PseudoVLOXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8) + .value("PseudoVLOXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1) + .value("PseudoVLOXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2) + .value("PseudoVLOXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4) + .value("PseudoVLOXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8) + .value("PseudoVLOXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1) + .value("PseudoVLOXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2) + .value("PseudoVLOXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4) + .value("PseudoVLOXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1) + .value("PseudoVLOXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2) + .value("PseudoVLOXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1) + .value("PseudoVLOXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1) + .value("PseudoVLOXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1) + .value("PseudoVLOXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2) + .value("PseudoVLOXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1) + .value("PseudoVLOXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2); + opcodes.value("PseudoVLOXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4) + .value("PseudoVLOXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1) + .value("PseudoVLOXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2) + .value("PseudoVLOXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4) + .value("PseudoVLOXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8) + .value("PseudoVLOXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1) + .value("PseudoVLOXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2) + .value("PseudoVLOXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1) + .value("PseudoVLOXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1) + .value("PseudoVLOXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2) + .value("PseudoVLOXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4) + .value("PseudoVLOXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1) + .value("PseudoVLOXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2) + .value("PseudoVLOXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4) + .value("PseudoVLOXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8) + .value("PseudoVLOXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1) + .value("PseudoVLOXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2) + .value("PseudoVLOXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4) + .value("PseudoVLOXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1) + .value("PseudoVLOXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2) + .value("PseudoVLOXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1) + .value("PseudoVLOXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1) + .value("PseudoVLOXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2) + .value("PseudoVLOXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4) + .value("PseudoVLOXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8) + .value("PseudoVLOXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1) + .value("PseudoVLOXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2) + .value("PseudoVLOXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4) + .value("PseudoVLOXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8) + .value("PseudoVLOXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1) + .value("PseudoVLOXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2) + .value("PseudoVLOXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4) + .value("PseudoVLOXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1) + .value("PseudoVLOXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2) + .value("PseudoVLOXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1) + .value("PseudoVLOXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1) + .value("PseudoVLOXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1) + .value("PseudoVLOXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2) + .value("PseudoVLOXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1) + .value("PseudoVLOXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2) + .value("PseudoVLOXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4) + .value("PseudoVLOXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1) + .value("PseudoVLOXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2) + .value("PseudoVLOXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4) + .value("PseudoVLOXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8) + .value("PseudoVLOXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK) + .value("PseudoVLOXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1) + .value("PseudoVLOXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1_MASK) + .value("PseudoVLOXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2) + .value("PseudoVLOXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2_MASK) + .value("PseudoVLOXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1) + .value("PseudoVLOXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1_MASK) + .value("PseudoVLOXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1) + .value("PseudoVLOXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1_MASK) + .value("PseudoVLOXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2) + .value("PseudoVLOXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4) + .value("PseudoVLOXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1) + .value("PseudoVLOXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1_MASK) + .value("PseudoVLOXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2) + .value("PseudoVLOXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4) + .value("PseudoVLOXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8) + .value("PseudoVLOXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK) + .value("PseudoVLOXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1) + .value("PseudoVLOXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1_MASK) + .value("PseudoVLOXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2) + .value("PseudoVLOXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2_MASK) + .value("PseudoVLOXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4) + .value("PseudoVLOXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4_MASK) + .value("PseudoVLOXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1) + .value("PseudoVLOXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1_MASK) + .value("PseudoVLOXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2) + .value("PseudoVLOXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2_MASK) + .value("PseudoVLOXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1) + .value("PseudoVLOXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1_MASK) + .value("PseudoVLOXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1) + .value("PseudoVLOXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1_MASK) + .value("PseudoVLOXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2) + .value("PseudoVLOXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4) + .value("PseudoVLOXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK) + .value("PseudoVLOXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8) + .value("PseudoVLOXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK) + .value("PseudoVLOXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1) + .value("PseudoVLOXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1_MASK) + .value("PseudoVLOXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2) + .value("PseudoVLOXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2_MASK) + .value("PseudoVLOXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4) + .value("PseudoVLOXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4_MASK) + .value("PseudoVLOXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8) + .value("PseudoVLOXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8_MASK) + .value("PseudoVLOXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1) + .value("PseudoVLOXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1_MASK) + .value("PseudoVLOXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2) + .value("PseudoVLOXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2_MASK) + .value("PseudoVLOXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4) + .value("PseudoVLOXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4_MASK) + .value("PseudoVLOXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1) + .value("PseudoVLOXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1_MASK) + .value("PseudoVLOXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2) + .value("PseudoVLOXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2_MASK) + .value("PseudoVLOXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1) + .value("PseudoVLOXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1_MASK) + .value("PseudoVLOXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1) + .value("PseudoVLOXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1_MASK) + .value("PseudoVLOXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1) + .value("PseudoVLOXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1_MASK) + .value("PseudoVLOXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2) + .value("PseudoVLOXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK) + .value("PseudoVLOXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1) + .value("PseudoVLOXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1_MASK) + .value("PseudoVLOXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2) + .value("PseudoVLOXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK) + .value("PseudoVLOXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4) + .value("PseudoVLOXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK) + .value("PseudoVLOXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1) + .value("PseudoVLOXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1_MASK) + .value("PseudoVLOXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2) + .value("PseudoVLOXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK) + .value("PseudoVLOXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4) + .value("PseudoVLOXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK) + .value("PseudoVLOXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8) + .value("PseudoVLOXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK) + .value("PseudoVLSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1) + .value("PseudoVLSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1_MASK) + .value("PseudoVLSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2) + .value("PseudoVLSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2_MASK) + .value("PseudoVLSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4) + .value("PseudoVLSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4_MASK) + .value("PseudoVLSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8) + .value("PseudoVLSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8_MASK) + .value("PseudoVLSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2) + .value("PseudoVLSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2_MASK) + .value("PseudoVLSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4) + .value("PseudoVLSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4_MASK) + .value("PseudoVLSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1) + .value("PseudoVLSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1_MASK) + .value("PseudoVLSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2) + .value("PseudoVLSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2_MASK) + .value("PseudoVLSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4) + .value("PseudoVLSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4_MASK) + .value("PseudoVLSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8) + .value("PseudoVLSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8_MASK) + .value("PseudoVLSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2) + .value("PseudoVLSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2_MASK) + .value("PseudoVLSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1) + .value("PseudoVLSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1_MASK) + .value("PseudoVLSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2) + .value("PseudoVLSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2_MASK) + .value("PseudoVLSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4) + .value("PseudoVLSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4_MASK) + .value("PseudoVLSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8) + .value("PseudoVLSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8_MASK) + .value("PseudoVLSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1) + .value("PseudoVLSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1_MASK) + .value("PseudoVLSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2) + .value("PseudoVLSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2_MASK) + .value("PseudoVLSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4) + .value("PseudoVLSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4_MASK) + .value("PseudoVLSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8) + .value("PseudoVLSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8_MASK) + .value("PseudoVLSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2) + .value("PseudoVLSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2_MASK) + .value("PseudoVLSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4) + .value("PseudoVLSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4_MASK) + .value("PseudoVLSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8) + .value("PseudoVLSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8_MASK) + .value("PseudoVLSEG2E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1) + .value("PseudoVLSEG2E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1_MASK) + .value("PseudoVLSEG2E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2) + .value("PseudoVLSEG2E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2_MASK) + .value("PseudoVLSEG2E16FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4) + .value("PseudoVLSEG2E16FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4_MASK) + .value("PseudoVLSEG2E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2) + .value("PseudoVLSEG2E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2_MASK) + .value("PseudoVLSEG2E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4) + .value("PseudoVLSEG2E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4_MASK) + .value("PseudoVLSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1) + .value("PseudoVLSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1_MASK) + .value("PseudoVLSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2) + .value("PseudoVLSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2_MASK) + .value("PseudoVLSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4) + .value("PseudoVLSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4_MASK) + .value("PseudoVLSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2) + .value("PseudoVLSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2_MASK) + .value("PseudoVLSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4) + .value("PseudoVLSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4_MASK) + .value("PseudoVLSEG2E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1) + .value("PseudoVLSEG2E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1_MASK) + .value("PseudoVLSEG2E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2) + .value("PseudoVLSEG2E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2_MASK) + .value("PseudoVLSEG2E32FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4) + .value("PseudoVLSEG2E32FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4_MASK) + .value("PseudoVLSEG2E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2) + .value("PseudoVLSEG2E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2_MASK) + .value("PseudoVLSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1) + .value("PseudoVLSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1_MASK) + .value("PseudoVLSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2) + .value("PseudoVLSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2_MASK) + .value("PseudoVLSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4) + .value("PseudoVLSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4_MASK) + .value("PseudoVLSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2) + .value("PseudoVLSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2_MASK) + .value("PseudoVLSEG2E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1) + .value("PseudoVLSEG2E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1_MASK) + .value("PseudoVLSEG2E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2) + .value("PseudoVLSEG2E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2_MASK) + .value("PseudoVLSEG2E64FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4) + .value("PseudoVLSEG2E64FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4_MASK) + .value("PseudoVLSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1) + .value("PseudoVLSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1_MASK) + .value("PseudoVLSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2) + .value("PseudoVLSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2_MASK) + .value("PseudoVLSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4) + .value("PseudoVLSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4_MASK) + .value("PseudoVLSEG2E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1) + .value("PseudoVLSEG2E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1_MASK) + .value("PseudoVLSEG2E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2) + .value("PseudoVLSEG2E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2_MASK) + .value("PseudoVLSEG2E8FF_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4) + .value("PseudoVLSEG2E8FF_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4_MASK) + .value("PseudoVLSEG2E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2) + .value("PseudoVLSEG2E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2_MASK) + .value("PseudoVLSEG2E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4) + .value("PseudoVLSEG2E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4_MASK) + .value("PseudoVLSEG2E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8) + .value("PseudoVLSEG2E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8_MASK) + .value("PseudoVLSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1) + .value("PseudoVLSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1_MASK) + .value("PseudoVLSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2) + .value("PseudoVLSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2_MASK) + .value("PseudoVLSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4) + .value("PseudoVLSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4_MASK) + .value("PseudoVLSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2) + .value("PseudoVLSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2_MASK) + .value("PseudoVLSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4) + .value("PseudoVLSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4_MASK) + .value("PseudoVLSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8) + .value("PseudoVLSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8_MASK) + .value("PseudoVLSEG3E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1) + .value("PseudoVLSEG3E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1_MASK) + .value("PseudoVLSEG3E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2) + .value("PseudoVLSEG3E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2_MASK) + .value("PseudoVLSEG3E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2) + .value("PseudoVLSEG3E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2_MASK) + .value("PseudoVLSEG3E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4) + .value("PseudoVLSEG3E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4_MASK) + .value("PseudoVLSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1) + .value("PseudoVLSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1_MASK) + .value("PseudoVLSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2) + .value("PseudoVLSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2_MASK) + .value("PseudoVLSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2); + opcodes.value("PseudoVLSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2_MASK) + .value("PseudoVLSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4) + .value("PseudoVLSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4_MASK) + .value("PseudoVLSEG3E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1) + .value("PseudoVLSEG3E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1_MASK) + .value("PseudoVLSEG3E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2) + .value("PseudoVLSEG3E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2_MASK) + .value("PseudoVLSEG3E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2) + .value("PseudoVLSEG3E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2_MASK) + .value("PseudoVLSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1) + .value("PseudoVLSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1_MASK) + .value("PseudoVLSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2) + .value("PseudoVLSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2_MASK) + .value("PseudoVLSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2) + .value("PseudoVLSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2_MASK) + .value("PseudoVLSEG3E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1) + .value("PseudoVLSEG3E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1_MASK) + .value("PseudoVLSEG3E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2) + .value("PseudoVLSEG3E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2_MASK) + .value("PseudoVLSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1) + .value("PseudoVLSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1_MASK) + .value("PseudoVLSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2) + .value("PseudoVLSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2_MASK) + .value("PseudoVLSEG3E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1) + .value("PseudoVLSEG3E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1_MASK) + .value("PseudoVLSEG3E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2) + .value("PseudoVLSEG3E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2_MASK) + .value("PseudoVLSEG3E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2) + .value("PseudoVLSEG3E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2_MASK) + .value("PseudoVLSEG3E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4) + .value("PseudoVLSEG3E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4_MASK) + .value("PseudoVLSEG3E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8) + .value("PseudoVLSEG3E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8_MASK) + .value("PseudoVLSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1) + .value("PseudoVLSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1_MASK) + .value("PseudoVLSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2) + .value("PseudoVLSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2_MASK) + .value("PseudoVLSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2) + .value("PseudoVLSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2_MASK) + .value("PseudoVLSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4) + .value("PseudoVLSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4_MASK) + .value("PseudoVLSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8) + .value("PseudoVLSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8_MASK) + .value("PseudoVLSEG4E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1) + .value("PseudoVLSEG4E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1_MASK) + .value("PseudoVLSEG4E16FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2) + .value("PseudoVLSEG4E16FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2_MASK) + .value("PseudoVLSEG4E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2) + .value("PseudoVLSEG4E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2_MASK) + .value("PseudoVLSEG4E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4) + .value("PseudoVLSEG4E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4_MASK) + .value("PseudoVLSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1) + .value("PseudoVLSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1_MASK) + .value("PseudoVLSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2) + .value("PseudoVLSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2_MASK) + .value("PseudoVLSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2) + .value("PseudoVLSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2_MASK) + .value("PseudoVLSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4) + .value("PseudoVLSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4_MASK) + .value("PseudoVLSEG4E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1) + .value("PseudoVLSEG4E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1_MASK) + .value("PseudoVLSEG4E32FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2) + .value("PseudoVLSEG4E32FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2_MASK) + .value("PseudoVLSEG4E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2) + .value("PseudoVLSEG4E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2_MASK) + .value("PseudoVLSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1) + .value("PseudoVLSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1_MASK) + .value("PseudoVLSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2) + .value("PseudoVLSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2_MASK) + .value("PseudoVLSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2) + .value("PseudoVLSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2_MASK) + .value("PseudoVLSEG4E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1) + .value("PseudoVLSEG4E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1_MASK) + .value("PseudoVLSEG4E64FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2) + .value("PseudoVLSEG4E64FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2_MASK) + .value("PseudoVLSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1) + .value("PseudoVLSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1_MASK) + .value("PseudoVLSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2) + .value("PseudoVLSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2_MASK) + .value("PseudoVLSEG4E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1) + .value("PseudoVLSEG4E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1_MASK) + .value("PseudoVLSEG4E8FF_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2) + .value("PseudoVLSEG4E8FF_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2_MASK) + .value("PseudoVLSEG4E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2) + .value("PseudoVLSEG4E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2_MASK) + .value("PseudoVLSEG4E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4) + .value("PseudoVLSEG4E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4_MASK) + .value("PseudoVLSEG4E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8) + .value("PseudoVLSEG4E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8_MASK) + .value("PseudoVLSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1) + .value("PseudoVLSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1_MASK) + .value("PseudoVLSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2) + .value("PseudoVLSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2_MASK) + .value("PseudoVLSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2) + .value("PseudoVLSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2_MASK) + .value("PseudoVLSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4) + .value("PseudoVLSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4_MASK) + .value("PseudoVLSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8) + .value("PseudoVLSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8_MASK) + .value("PseudoVLSEG5E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1) + .value("PseudoVLSEG5E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1_MASK) + .value("PseudoVLSEG5E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2) + .value("PseudoVLSEG5E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2_MASK) + .value("PseudoVLSEG5E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4) + .value("PseudoVLSEG5E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4_MASK) + .value("PseudoVLSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1) + .value("PseudoVLSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1_MASK) + .value("PseudoVLSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2) + .value("PseudoVLSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2_MASK) + .value("PseudoVLSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4) + .value("PseudoVLSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4_MASK) + .value("PseudoVLSEG5E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1) + .value("PseudoVLSEG5E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1_MASK) + .value("PseudoVLSEG5E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2) + .value("PseudoVLSEG5E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2_MASK) + .value("PseudoVLSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1) + .value("PseudoVLSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1_MASK) + .value("PseudoVLSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2) + .value("PseudoVLSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2_MASK) + .value("PseudoVLSEG5E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1) + .value("PseudoVLSEG5E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1_MASK) + .value("PseudoVLSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1) + .value("PseudoVLSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1_MASK) + .value("PseudoVLSEG5E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1) + .value("PseudoVLSEG5E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1_MASK) + .value("PseudoVLSEG5E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2) + .value("PseudoVLSEG5E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2_MASK) + .value("PseudoVLSEG5E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4) + .value("PseudoVLSEG5E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4_MASK) + .value("PseudoVLSEG5E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8) + .value("PseudoVLSEG5E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8_MASK) + .value("PseudoVLSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1) + .value("PseudoVLSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1_MASK) + .value("PseudoVLSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2) + .value("PseudoVLSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2_MASK) + .value("PseudoVLSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4) + .value("PseudoVLSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4_MASK) + .value("PseudoVLSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8) + .value("PseudoVLSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8_MASK) + .value("PseudoVLSEG6E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1) + .value("PseudoVLSEG6E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1_MASK) + .value("PseudoVLSEG6E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2) + .value("PseudoVLSEG6E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2_MASK) + .value("PseudoVLSEG6E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4) + .value("PseudoVLSEG6E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4_MASK) + .value("PseudoVLSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1) + .value("PseudoVLSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1_MASK) + .value("PseudoVLSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2) + .value("PseudoVLSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2_MASK) + .value("PseudoVLSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4) + .value("PseudoVLSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4_MASK) + .value("PseudoVLSEG6E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1) + .value("PseudoVLSEG6E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1_MASK) + .value("PseudoVLSEG6E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2) + .value("PseudoVLSEG6E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2_MASK) + .value("PseudoVLSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1) + .value("PseudoVLSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1_MASK) + .value("PseudoVLSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2) + .value("PseudoVLSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2_MASK) + .value("PseudoVLSEG6E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1) + .value("PseudoVLSEG6E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1_MASK) + .value("PseudoVLSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1) + .value("PseudoVLSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1_MASK) + .value("PseudoVLSEG6E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1) + .value("PseudoVLSEG6E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1_MASK) + .value("PseudoVLSEG6E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2) + .value("PseudoVLSEG6E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2_MASK) + .value("PseudoVLSEG6E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4) + .value("PseudoVLSEG6E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4_MASK) + .value("PseudoVLSEG6E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8) + .value("PseudoVLSEG6E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8_MASK) + .value("PseudoVLSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1) + .value("PseudoVLSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1_MASK) + .value("PseudoVLSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2) + .value("PseudoVLSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2_MASK) + .value("PseudoVLSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4) + .value("PseudoVLSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4_MASK) + .value("PseudoVLSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8) + .value("PseudoVLSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8_MASK) + .value("PseudoVLSEG7E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1) + .value("PseudoVLSEG7E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1_MASK) + .value("PseudoVLSEG7E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2) + .value("PseudoVLSEG7E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2_MASK) + .value("PseudoVLSEG7E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4) + .value("PseudoVLSEG7E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4_MASK) + .value("PseudoVLSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1) + .value("PseudoVLSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1_MASK) + .value("PseudoVLSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2) + .value("PseudoVLSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2_MASK) + .value("PseudoVLSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4) + .value("PseudoVLSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4_MASK) + .value("PseudoVLSEG7E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1) + .value("PseudoVLSEG7E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1_MASK) + .value("PseudoVLSEG7E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2) + .value("PseudoVLSEG7E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2_MASK) + .value("PseudoVLSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1) + .value("PseudoVLSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1_MASK) + .value("PseudoVLSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2) + .value("PseudoVLSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2_MASK) + .value("PseudoVLSEG7E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1) + .value("PseudoVLSEG7E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1_MASK) + .value("PseudoVLSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1) + .value("PseudoVLSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1_MASK) + .value("PseudoVLSEG7E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1) + .value("PseudoVLSEG7E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1_MASK) + .value("PseudoVLSEG7E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2) + .value("PseudoVLSEG7E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2_MASK) + .value("PseudoVLSEG7E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4) + .value("PseudoVLSEG7E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4_MASK) + .value("PseudoVLSEG7E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8) + .value("PseudoVLSEG7E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8_MASK) + .value("PseudoVLSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1) + .value("PseudoVLSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1_MASK) + .value("PseudoVLSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2) + .value("PseudoVLSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2_MASK) + .value("PseudoVLSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4) + .value("PseudoVLSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4_MASK) + .value("PseudoVLSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8) + .value("PseudoVLSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8_MASK) + .value("PseudoVLSEG8E16FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1) + .value("PseudoVLSEG8E16FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1_MASK) + .value("PseudoVLSEG8E16FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2) + .value("PseudoVLSEG8E16FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2_MASK) + .value("PseudoVLSEG8E16FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4) + .value("PseudoVLSEG8E16FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4_MASK) + .value("PseudoVLSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1) + .value("PseudoVLSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1_MASK) + .value("PseudoVLSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2) + .value("PseudoVLSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2_MASK) + .value("PseudoVLSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4) + .value("PseudoVLSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4_MASK) + .value("PseudoVLSEG8E32FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1) + .value("PseudoVLSEG8E32FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1_MASK) + .value("PseudoVLSEG8E32FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2) + .value("PseudoVLSEG8E32FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2_MASK) + .value("PseudoVLSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1) + .value("PseudoVLSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1_MASK) + .value("PseudoVLSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2) + .value("PseudoVLSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2_MASK) + .value("PseudoVLSEG8E64FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1) + .value("PseudoVLSEG8E64FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1_MASK) + .value("PseudoVLSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1) + .value("PseudoVLSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1_MASK) + .value("PseudoVLSEG8E8FF_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1) + .value("PseudoVLSEG8E8FF_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1_MASK) + .value("PseudoVLSEG8E8FF_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2) + .value("PseudoVLSEG8E8FF_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2_MASK) + .value("PseudoVLSEG8E8FF_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4) + .value("PseudoVLSEG8E8FF_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4_MASK) + .value("PseudoVLSEG8E8FF_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8) + .value("PseudoVLSEG8E8FF_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8_MASK) + .value("PseudoVLSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1) + .value("PseudoVLSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1_MASK) + .value("PseudoVLSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2) + .value("PseudoVLSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2_MASK) + .value("PseudoVLSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4) + .value("PseudoVLSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4_MASK) + .value("PseudoVLSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8) + .value("PseudoVLSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8_MASK) + .value("PseudoVLSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1) + .value("PseudoVLSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1_MASK) + .value("PseudoVLSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2) + .value("PseudoVLSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2_MASK) + .value("PseudoVLSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4) + .value("PseudoVLSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4_MASK) + .value("PseudoVLSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2) + .value("PseudoVLSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2_MASK) + .value("PseudoVLSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4) + .value("PseudoVLSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4_MASK) + .value("PseudoVLSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1) + .value("PseudoVLSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1_MASK) + .value("PseudoVLSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2) + .value("PseudoVLSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2_MASK) + .value("PseudoVLSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4) + .value("PseudoVLSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4_MASK) + .value("PseudoVLSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2) + .value("PseudoVLSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2_MASK) + .value("PseudoVLSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1) + .value("PseudoVLSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1_MASK) + .value("PseudoVLSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2) + .value("PseudoVLSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2_MASK) + .value("PseudoVLSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4) + .value("PseudoVLSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4_MASK) + .value("PseudoVLSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1) + .value("PseudoVLSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1_MASK) + .value("PseudoVLSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2) + .value("PseudoVLSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2_MASK) + .value("PseudoVLSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4) + .value("PseudoVLSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4_MASK) + .value("PseudoVLSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2) + .value("PseudoVLSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2_MASK) + .value("PseudoVLSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4) + .value("PseudoVLSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4_MASK) + .value("PseudoVLSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8) + .value("PseudoVLSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8_MASK) + .value("PseudoVLSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1) + .value("PseudoVLSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1_MASK) + .value("PseudoVLSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2) + .value("PseudoVLSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2_MASK) + .value("PseudoVLSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2); + opcodes.value("PseudoVLSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2_MASK) + .value("PseudoVLSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4) + .value("PseudoVLSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4_MASK) + .value("PseudoVLSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1) + .value("PseudoVLSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1_MASK) + .value("PseudoVLSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2) + .value("PseudoVLSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2_MASK) + .value("PseudoVLSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2) + .value("PseudoVLSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2_MASK) + .value("PseudoVLSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1) + .value("PseudoVLSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1_MASK) + .value("PseudoVLSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2) + .value("PseudoVLSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2_MASK) + .value("PseudoVLSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1) + .value("PseudoVLSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1_MASK) + .value("PseudoVLSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2) + .value("PseudoVLSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2_MASK) + .value("PseudoVLSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2) + .value("PseudoVLSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2_MASK) + .value("PseudoVLSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4) + .value("PseudoVLSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4_MASK) + .value("PseudoVLSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8) + .value("PseudoVLSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8_MASK) + .value("PseudoVLSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1) + .value("PseudoVLSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1_MASK) + .value("PseudoVLSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2) + .value("PseudoVLSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2_MASK) + .value("PseudoVLSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2) + .value("PseudoVLSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2_MASK) + .value("PseudoVLSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4) + .value("PseudoVLSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4_MASK) + .value("PseudoVLSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1) + .value("PseudoVLSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1_MASK) + .value("PseudoVLSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2) + .value("PseudoVLSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2_MASK) + .value("PseudoVLSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2) + .value("PseudoVLSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2_MASK) + .value("PseudoVLSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1) + .value("PseudoVLSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1_MASK) + .value("PseudoVLSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2) + .value("PseudoVLSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2_MASK) + .value("PseudoVLSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1) + .value("PseudoVLSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1_MASK) + .value("PseudoVLSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2) + .value("PseudoVLSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2_MASK) + .value("PseudoVLSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2) + .value("PseudoVLSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2_MASK) + .value("PseudoVLSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4) + .value("PseudoVLSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4_MASK) + .value("PseudoVLSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8) + .value("PseudoVLSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8_MASK) + .value("PseudoVLSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1) + .value("PseudoVLSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1_MASK) + .value("PseudoVLSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2) + .value("PseudoVLSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2_MASK) + .value("PseudoVLSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4) + .value("PseudoVLSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4_MASK) + .value("PseudoVLSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1) + .value("PseudoVLSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1_MASK) + .value("PseudoVLSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2) + .value("PseudoVLSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2_MASK) + .value("PseudoVLSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1) + .value("PseudoVLSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1_MASK) + .value("PseudoVLSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1) + .value("PseudoVLSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1_MASK) + .value("PseudoVLSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2) + .value("PseudoVLSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2_MASK) + .value("PseudoVLSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4) + .value("PseudoVLSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4_MASK) + .value("PseudoVLSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8) + .value("PseudoVLSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8_MASK) + .value("PseudoVLSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1) + .value("PseudoVLSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1_MASK) + .value("PseudoVLSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2) + .value("PseudoVLSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2_MASK) + .value("PseudoVLSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4) + .value("PseudoVLSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4_MASK) + .value("PseudoVLSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1) + .value("PseudoVLSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1_MASK) + .value("PseudoVLSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2) + .value("PseudoVLSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2_MASK) + .value("PseudoVLSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1) + .value("PseudoVLSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1_MASK) + .value("PseudoVLSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1) + .value("PseudoVLSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1_MASK) + .value("PseudoVLSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2) + .value("PseudoVLSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2_MASK) + .value("PseudoVLSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4) + .value("PseudoVLSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4_MASK) + .value("PseudoVLSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8) + .value("PseudoVLSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8_MASK) + .value("PseudoVLSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1) + .value("PseudoVLSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1_MASK) + .value("PseudoVLSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2) + .value("PseudoVLSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2_MASK) + .value("PseudoVLSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4) + .value("PseudoVLSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4_MASK) + .value("PseudoVLSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1) + .value("PseudoVLSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1_MASK) + .value("PseudoVLSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2) + .value("PseudoVLSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2_MASK) + .value("PseudoVLSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1) + .value("PseudoVLSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1_MASK) + .value("PseudoVLSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1) + .value("PseudoVLSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1_MASK) + .value("PseudoVLSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2) + .value("PseudoVLSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2_MASK) + .value("PseudoVLSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4) + .value("PseudoVLSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4_MASK) + .value("PseudoVLSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8) + .value("PseudoVLSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8_MASK) + .value("PseudoVLSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1) + .value("PseudoVLSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1_MASK) + .value("PseudoVLSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2) + .value("PseudoVLSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2_MASK) + .value("PseudoVLSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4) + .value("PseudoVLSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4_MASK) + .value("PseudoVLSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1) + .value("PseudoVLSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1_MASK) + .value("PseudoVLSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2) + .value("PseudoVLSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2_MASK) + .value("PseudoVLSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1) + .value("PseudoVLSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1_MASK) + .value("PseudoVLSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1) + .value("PseudoVLSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1_MASK) + .value("PseudoVLSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2) + .value("PseudoVLSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2_MASK) + .value("PseudoVLSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4) + .value("PseudoVLSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4_MASK) + .value("PseudoVLSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8) + .value("PseudoVLSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8_MASK) + .value("PseudoVLUXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1) + .value("PseudoVLUXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1_MASK) + .value("PseudoVLUXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2) + .value("PseudoVLUXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2_MASK) + .value("PseudoVLUXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4) + .value("PseudoVLUXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4_MASK) + .value("PseudoVLUXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2) + .value("PseudoVLUXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2_MASK) + .value("PseudoVLUXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1) + .value("PseudoVLUXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1_MASK) + .value("PseudoVLUXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2) + .value("PseudoVLUXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2_MASK) + .value("PseudoVLUXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4) + .value("PseudoVLUXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4_MASK) + .value("PseudoVLUXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8) + .value("PseudoVLUXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8_MASK) + .value("PseudoVLUXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2) + .value("PseudoVLUXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2_MASK) + .value("PseudoVLUXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4) + .value("PseudoVLUXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4_MASK) + .value("PseudoVLUXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8) + .value("PseudoVLUXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8_MASK) + .value("PseudoVLUXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4) + .value("PseudoVLUXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4_MASK) + .value("PseudoVLUXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8) + .value("PseudoVLUXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8_MASK) + .value("PseudoVLUXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1) + .value("PseudoVLUXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1_MASK) + .value("PseudoVLUXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2) + .value("PseudoVLUXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2_MASK) + .value("PseudoVLUXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2) + .value("PseudoVLUXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2_MASK) + .value("PseudoVLUXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4) + .value("PseudoVLUXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4_MASK) + .value("PseudoVLUXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1) + .value("PseudoVLUXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1_MASK) + .value("PseudoVLUXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2) + .value("PseudoVLUXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2_MASK) + .value("PseudoVLUXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4) + .value("PseudoVLUXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4_MASK) + .value("PseudoVLUXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8) + .value("PseudoVLUXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8_MASK) + .value("PseudoVLUXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1) + .value("PseudoVLUXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1_MASK) + .value("PseudoVLUXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2) + .value("PseudoVLUXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2_MASK) + .value("PseudoVLUXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2) + .value("PseudoVLUXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2_MASK) + .value("PseudoVLUXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4) + .value("PseudoVLUXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4_MASK) + .value("PseudoVLUXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1) + .value("PseudoVLUXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1_MASK) + .value("PseudoVLUXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2) + .value("PseudoVLUXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2_MASK) + .value("PseudoVLUXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4) + .value("PseudoVLUXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4_MASK) + .value("PseudoVLUXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2) + .value("PseudoVLUXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2_MASK) + .value("PseudoVLUXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1) + .value("PseudoVLUXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1_MASK) + .value("PseudoVLUXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2) + .value("PseudoVLUXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2_MASK) + .value("PseudoVLUXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4) + .value("PseudoVLUXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4_MASK) + .value("PseudoVLUXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8) + .value("PseudoVLUXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8_MASK) + .value("PseudoVLUXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2) + .value("PseudoVLUXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2_MASK) + .value("PseudoVLUXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4) + .value("PseudoVLUXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4_MASK) + .value("PseudoVLUXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8) + .value("PseudoVLUXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8_MASK) + .value("PseudoVLUXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1) + .value("PseudoVLUXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1_MASK) + .value("PseudoVLUXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2) + .value("PseudoVLUXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2_MASK) + .value("PseudoVLUXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4) + .value("PseudoVLUXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4_MASK) + .value("PseudoVLUXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8) + .value("PseudoVLUXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8_MASK) + .value("PseudoVLUXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1) + .value("PseudoVLUXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1_MASK) + .value("PseudoVLUXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2) + .value("PseudoVLUXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2_MASK) + .value("PseudoVLUXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4) + .value("PseudoVLUXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4_MASK) + .value("PseudoVLUXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8) + .value("PseudoVLUXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8_MASK) + .value("PseudoVLUXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1) + .value("PseudoVLUXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1_MASK) + .value("PseudoVLUXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2) + .value("PseudoVLUXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2_MASK) + .value("PseudoVLUXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2) + .value("PseudoVLUXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2_MASK) + .value("PseudoVLUXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4) + .value("PseudoVLUXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4_MASK) + .value("PseudoVLUXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1) + .value("PseudoVLUXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1_MASK) + .value("PseudoVLUXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2) + .value("PseudoVLUXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2_MASK) + .value("PseudoVLUXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4) + .value("PseudoVLUXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4_MASK) + .value("PseudoVLUXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2) + .value("PseudoVLUXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2_MASK) + .value("PseudoVLUXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1) + .value("PseudoVLUXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1_MASK) + .value("PseudoVLUXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2) + .value("PseudoVLUXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2_MASK) + .value("PseudoVLUXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4) + .value("PseudoVLUXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4_MASK) + .value("PseudoVLUXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8) + .value("PseudoVLUXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8_MASK) + .value("PseudoVLUXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1) + .value("PseudoVLUXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1_MASK) + .value("PseudoVLUXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2) + .value("PseudoVLUXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2_MASK) + .value("PseudoVLUXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4) + .value("PseudoVLUXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4_MASK) + .value("PseudoVLUXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8) + .value("PseudoVLUXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8_MASK) + .value("PseudoVLUXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2) + .value("PseudoVLUXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2_MASK) + .value("PseudoVLUXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4) + .value("PseudoVLUXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4_MASK) + .value("PseudoVLUXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8) + .value("PseudoVLUXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8_MASK) + .value("PseudoVLUXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4) + .value("PseudoVLUXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4_MASK) + .value("PseudoVLUXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8) + .value("PseudoVLUXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8_MASK) + .value("PseudoVLUXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8) + .value("PseudoVLUXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8_MASK) + .value("PseudoVLUXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1) + .value("PseudoVLUXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1_MASK) + .value("PseudoVLUXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2) + .value("PseudoVLUXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2_MASK) + .value("PseudoVLUXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4) + .value("PseudoVLUXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4_MASK) + .value("PseudoVLUXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2) + .value("PseudoVLUXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2_MASK) + .value("PseudoVLUXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1) + .value("PseudoVLUXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1_MASK) + .value("PseudoVLUXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2) + .value("PseudoVLUXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2_MASK) + .value("PseudoVLUXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2) + .value("PseudoVLUXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2_MASK) + .value("PseudoVLUXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4) + .value("PseudoVLUXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4_MASK) + .value("PseudoVLUXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1) + .value("PseudoVLUXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1_MASK) + .value("PseudoVLUXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2) + .value("PseudoVLUXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2_MASK) + .value("PseudoVLUXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4) + .value("PseudoVLUXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4_MASK) + .value("PseudoVLUXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8) + .value("PseudoVLUXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1) + .value("PseudoVLUXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2) + .value("PseudoVLUXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2_MASK) + .value("PseudoVLUXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4) + .value("PseudoVLUXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4_MASK) + .value("PseudoVLUXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2) + .value("PseudoVLUXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1) + .value("PseudoVLUXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2) + .value("PseudoVLUXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2_MASK) + .value("PseudoVLUXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4); + opcodes.value("PseudoVLUXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4_MASK) + .value("PseudoVLUXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2) + .value("PseudoVLUXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2_MASK) + .value("PseudoVLUXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4) + .value("PseudoVLUXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4_MASK) + .value("PseudoVLUXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4) + .value("PseudoVLUXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4_MASK) + .value("PseudoVLUXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1) + .value("PseudoVLUXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2) + .value("PseudoVLUXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2_MASK) + .value("PseudoVLUXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2) + .value("PseudoVLUXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4) + .value("PseudoVLUXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1) + .value("PseudoVLUXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2) + .value("PseudoVLUXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4) + .value("PseudoVLUXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8) + .value("PseudoVLUXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1) + .value("PseudoVLUXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2) + .value("PseudoVLUXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2_MASK) + .value("PseudoVLUXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2) + .value("PseudoVLUXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4) + .value("PseudoVLUXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1) + .value("PseudoVLUXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2) + .value("PseudoVLUXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2_MASK) + .value("PseudoVLUXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4) + .value("PseudoVLUXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4_MASK) + .value("PseudoVLUXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2) + .value("PseudoVLUXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1) + .value("PseudoVLUXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2) + .value("PseudoVLUXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2_MASK) + .value("PseudoVLUXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4) + .value("PseudoVLUXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4_MASK) + .value("PseudoVLUXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2) + .value("PseudoVLUXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2_MASK) + .value("PseudoVLUXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4) + .value("PseudoVLUXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4_MASK) + .value("PseudoVLUXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1) + .value("PseudoVLUXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2) + .value("PseudoVLUXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4) + .value("PseudoVLUXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8) + .value("PseudoVLUXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1) + .value("PseudoVLUXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2) + .value("PseudoVLUXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4) + .value("PseudoVLUXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8) + .value("PseudoVLUXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1) + .value("PseudoVLUXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2) + .value("PseudoVLUXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2_MASK) + .value("PseudoVLUXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2) + .value("PseudoVLUXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4) + .value("PseudoVLUXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1) + .value("PseudoVLUXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2) + .value("PseudoVLUXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2_MASK) + .value("PseudoVLUXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4) + .value("PseudoVLUXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4_MASK) + .value("PseudoVLUXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2) + .value("PseudoVLUXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1) + .value("PseudoVLUXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2) + .value("PseudoVLUXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2_MASK) + .value("PseudoVLUXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4) + .value("PseudoVLUXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4_MASK) + .value("PseudoVLUXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1) + .value("PseudoVLUXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2) + .value("PseudoVLUXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2_MASK) + .value("PseudoVLUXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4) + .value("PseudoVLUXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4_MASK) + .value("PseudoVLUXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2) + .value("PseudoVLUXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2_MASK) + .value("PseudoVLUXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4) + .value("PseudoVLUXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4_MASK) + .value("PseudoVLUXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4) + .value("PseudoVLUXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4_MASK) + .value("PseudoVLUXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1) + .value("PseudoVLUXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2) + .value("PseudoVLUXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2_MASK) + .value("PseudoVLUXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4) + .value("PseudoVLUXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4_MASK) + .value("PseudoVLUXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2) + .value("PseudoVLUXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1) + .value("PseudoVLUXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2) + .value("PseudoVLUXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2_MASK) + .value("PseudoVLUXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2) + .value("PseudoVLUXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4) + .value("PseudoVLUXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1) + .value("PseudoVLUXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2) + .value("PseudoVLUXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4) + .value("PseudoVLUXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8) + .value("PseudoVLUXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1) + .value("PseudoVLUXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2) + .value("PseudoVLUXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2_MASK) + .value("PseudoVLUXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2) + .value("PseudoVLUXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1) + .value("PseudoVLUXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2) + .value("PseudoVLUXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2_MASK) + .value("PseudoVLUXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2) + .value("PseudoVLUXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2_MASK) + .value("PseudoVLUXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1) + .value("PseudoVLUXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2) + .value("PseudoVLUXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2_MASK) + .value("PseudoVLUXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2) + .value("PseudoVLUXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4) + .value("PseudoVLUXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1) + .value("PseudoVLUXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2) + .value("PseudoVLUXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4) + .value("PseudoVLUXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8) + .value("PseudoVLUXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1) + .value("PseudoVLUXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2) + .value("PseudoVLUXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2_MASK) + .value("PseudoVLUXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2) + .value("PseudoVLUXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4) + .value("PseudoVLUXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1) + .value("PseudoVLUXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2) + .value("PseudoVLUXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2_MASK) + .value("PseudoVLUXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2) + .value("PseudoVLUXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1) + .value("PseudoVLUXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2) + .value("PseudoVLUXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2_MASK) + .value("PseudoVLUXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2) + .value("PseudoVLUXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2_MASK) + .value("PseudoVLUXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1) + .value("PseudoVLUXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2) + .value("PseudoVLUXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4) + .value("PseudoVLUXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8) + .value("PseudoVLUXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1) + .value("PseudoVLUXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2) + .value("PseudoVLUXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4) + .value("PseudoVLUXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8) + .value("PseudoVLUXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1) + .value("PseudoVLUXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2) + .value("PseudoVLUXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2_MASK) + .value("PseudoVLUXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2) + .value("PseudoVLUXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4) + .value("PseudoVLUXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1) + .value("PseudoVLUXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2) + .value("PseudoVLUXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2_MASK) + .value("PseudoVLUXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2) + .value("PseudoVLUXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1) + .value("PseudoVLUXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2) + .value("PseudoVLUXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2_MASK) + .value("PseudoVLUXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1) + .value("PseudoVLUXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2) + .value("PseudoVLUXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2_MASK) + .value("PseudoVLUXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2) + .value("PseudoVLUXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1) + .value("PseudoVLUXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2) + .value("PseudoVLUXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2) + .value("PseudoVLUXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1) + .value("PseudoVLUXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2) + .value("PseudoVLUXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2) + .value("PseudoVLUXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4) + .value("PseudoVLUXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1) + .value("PseudoVLUXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2) + .value("PseudoVLUXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4) + .value("PseudoVLUXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8) + .value("PseudoVLUXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1) + .value("PseudoVLUXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2) + .value("PseudoVLUXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2_MASK) + .value("PseudoVLUXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2) + .value("PseudoVLUXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1) + .value("PseudoVLUXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2) + .value("PseudoVLUXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2_MASK) + .value("PseudoVLUXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2) + .value("PseudoVLUXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2_MASK) + .value("PseudoVLUXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1) + .value("PseudoVLUXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2) + .value("PseudoVLUXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2_MASK) + .value("PseudoVLUXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2) + .value("PseudoVLUXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4) + .value("PseudoVLUXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1) + .value("PseudoVLUXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2) + .value("PseudoVLUXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4) + .value("PseudoVLUXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8) + .value("PseudoVLUXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1) + .value("PseudoVLUXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2) + .value("PseudoVLUXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2_MASK) + .value("PseudoVLUXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2) + .value("PseudoVLUXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4) + .value("PseudoVLUXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1) + .value("PseudoVLUXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2) + .value("PseudoVLUXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2_MASK) + .value("PseudoVLUXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2) + .value("PseudoVLUXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1) + .value("PseudoVLUXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2) + .value("PseudoVLUXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2_MASK) + .value("PseudoVLUXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2) + .value("PseudoVLUXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2_MASK) + .value("PseudoVLUXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1) + .value("PseudoVLUXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2) + .value("PseudoVLUXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4) + .value("PseudoVLUXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8) + .value("PseudoVLUXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1) + .value("PseudoVLUXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2) + .value("PseudoVLUXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4) + .value("PseudoVLUXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8) + .value("PseudoVLUXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1) + .value("PseudoVLUXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2); + opcodes.value("PseudoVLUXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2_MASK) + .value("PseudoVLUXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2) + .value("PseudoVLUXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4) + .value("PseudoVLUXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1) + .value("PseudoVLUXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2) + .value("PseudoVLUXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2_MASK) + .value("PseudoVLUXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2) + .value("PseudoVLUXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1) + .value("PseudoVLUXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2) + .value("PseudoVLUXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2_MASK) + .value("PseudoVLUXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1) + .value("PseudoVLUXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2) + .value("PseudoVLUXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2_MASK) + .value("PseudoVLUXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2) + .value("PseudoVLUXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1) + .value("PseudoVLUXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2) + .value("PseudoVLUXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2) + .value("PseudoVLUXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1) + .value("PseudoVLUXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2) + .value("PseudoVLUXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2) + .value("PseudoVLUXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4) + .value("PseudoVLUXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1) + .value("PseudoVLUXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2) + .value("PseudoVLUXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4) + .value("PseudoVLUXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8) + .value("PseudoVLUXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1) + .value("PseudoVLUXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2) + .value("PseudoVLUXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1) + .value("PseudoVLUXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1) + .value("PseudoVLUXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2) + .value("PseudoVLUXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4) + .value("PseudoVLUXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1) + .value("PseudoVLUXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2) + .value("PseudoVLUXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4) + .value("PseudoVLUXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8) + .value("PseudoVLUXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1) + .value("PseudoVLUXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2) + .value("PseudoVLUXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4) + .value("PseudoVLUXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1) + .value("PseudoVLUXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2) + .value("PseudoVLUXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1) + .value("PseudoVLUXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1) + .value("PseudoVLUXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2) + .value("PseudoVLUXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4) + .value("PseudoVLUXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8) + .value("PseudoVLUXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1) + .value("PseudoVLUXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2) + .value("PseudoVLUXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4) + .value("PseudoVLUXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8) + .value("PseudoVLUXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1) + .value("PseudoVLUXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2) + .value("PseudoVLUXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4) + .value("PseudoVLUXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1) + .value("PseudoVLUXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2) + .value("PseudoVLUXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1) + .value("PseudoVLUXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1) + .value("PseudoVLUXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1) + .value("PseudoVLUXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2) + .value("PseudoVLUXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1) + .value("PseudoVLUXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2) + .value("PseudoVLUXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4) + .value("PseudoVLUXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1) + .value("PseudoVLUXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2) + .value("PseudoVLUXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4) + .value("PseudoVLUXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8) + .value("PseudoVLUXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1) + .value("PseudoVLUXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2) + .value("PseudoVLUXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1) + .value("PseudoVLUXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1) + .value("PseudoVLUXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2) + .value("PseudoVLUXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4) + .value("PseudoVLUXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1) + .value("PseudoVLUXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2) + .value("PseudoVLUXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4) + .value("PseudoVLUXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8) + .value("PseudoVLUXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1) + .value("PseudoVLUXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2) + .value("PseudoVLUXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4) + .value("PseudoVLUXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1) + .value("PseudoVLUXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2) + .value("PseudoVLUXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1) + .value("PseudoVLUXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1) + .value("PseudoVLUXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2) + .value("PseudoVLUXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4) + .value("PseudoVLUXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8) + .value("PseudoVLUXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1) + .value("PseudoVLUXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2) + .value("PseudoVLUXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4) + .value("PseudoVLUXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8) + .value("PseudoVLUXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1) + .value("PseudoVLUXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2) + .value("PseudoVLUXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4) + .value("PseudoVLUXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1) + .value("PseudoVLUXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2) + .value("PseudoVLUXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1) + .value("PseudoVLUXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1) + .value("PseudoVLUXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1) + .value("PseudoVLUXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2) + .value("PseudoVLUXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1) + .value("PseudoVLUXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2) + .value("PseudoVLUXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4) + .value("PseudoVLUXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1) + .value("PseudoVLUXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2) + .value("PseudoVLUXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4) + .value("PseudoVLUXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8) + .value("PseudoVLUXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1) + .value("PseudoVLUXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2) + .value("PseudoVLUXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1) + .value("PseudoVLUXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1) + .value("PseudoVLUXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2) + .value("PseudoVLUXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4) + .value("PseudoVLUXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1) + .value("PseudoVLUXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2) + .value("PseudoVLUXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4) + .value("PseudoVLUXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8) + .value("PseudoVLUXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1) + .value("PseudoVLUXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2) + .value("PseudoVLUXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4) + .value("PseudoVLUXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1) + .value("PseudoVLUXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2) + .value("PseudoVLUXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1) + .value("PseudoVLUXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1) + .value("PseudoVLUXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2) + .value("PseudoVLUXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4) + .value("PseudoVLUXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8) + .value("PseudoVLUXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1) + .value("PseudoVLUXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2) + .value("PseudoVLUXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4) + .value("PseudoVLUXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8) + .value("PseudoVLUXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1) + .value("PseudoVLUXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2) + .value("PseudoVLUXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4) + .value("PseudoVLUXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1) + .value("PseudoVLUXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2) + .value("PseudoVLUXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1) + .value("PseudoVLUXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1) + .value("PseudoVLUXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1) + .value("PseudoVLUXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2) + .value("PseudoVLUXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1) + .value("PseudoVLUXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2) + .value("PseudoVLUXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4) + .value("PseudoVLUXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1) + .value("PseudoVLUXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2) + .value("PseudoVLUXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4) + .value("PseudoVLUXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8) + .value("PseudoVLUXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK) + .value("PseudoVLUXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1) + .value("PseudoVLUXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1_MASK) + .value("PseudoVLUXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2) + .value("PseudoVLUXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2_MASK) + .value("PseudoVLUXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1) + .value("PseudoVLUXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1_MASK) + .value("PseudoVLUXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1) + .value("PseudoVLUXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1_MASK) + .value("PseudoVLUXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2) + .value("PseudoVLUXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4) + .value("PseudoVLUXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1) + .value("PseudoVLUXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1_MASK) + .value("PseudoVLUXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2) + .value("PseudoVLUXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4); + opcodes.value("PseudoVLUXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8) + .value("PseudoVLUXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK) + .value("PseudoVLUXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1) + .value("PseudoVLUXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1_MASK) + .value("PseudoVLUXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2) + .value("PseudoVLUXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2_MASK) + .value("PseudoVLUXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4) + .value("PseudoVLUXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4_MASK) + .value("PseudoVLUXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1) + .value("PseudoVLUXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1_MASK) + .value("PseudoVLUXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2) + .value("PseudoVLUXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2_MASK) + .value("PseudoVLUXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1) + .value("PseudoVLUXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1_MASK) + .value("PseudoVLUXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1) + .value("PseudoVLUXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1_MASK) + .value("PseudoVLUXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2) + .value("PseudoVLUXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4) + .value("PseudoVLUXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK) + .value("PseudoVLUXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8) + .value("PseudoVLUXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK) + .value("PseudoVLUXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1) + .value("PseudoVLUXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1_MASK) + .value("PseudoVLUXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2) + .value("PseudoVLUXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2_MASK) + .value("PseudoVLUXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4) + .value("PseudoVLUXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4_MASK) + .value("PseudoVLUXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8) + .value("PseudoVLUXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8_MASK) + .value("PseudoVLUXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1) + .value("PseudoVLUXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1_MASK) + .value("PseudoVLUXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2) + .value("PseudoVLUXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2_MASK) + .value("PseudoVLUXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4) + .value("PseudoVLUXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4_MASK) + .value("PseudoVLUXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1) + .value("PseudoVLUXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1_MASK) + .value("PseudoVLUXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2) + .value("PseudoVLUXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2_MASK) + .value("PseudoVLUXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1) + .value("PseudoVLUXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1_MASK) + .value("PseudoVLUXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1) + .value("PseudoVLUXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1_MASK) + .value("PseudoVLUXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1) + .value("PseudoVLUXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1_MASK) + .value("PseudoVLUXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2) + .value("PseudoVLUXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK) + .value("PseudoVLUXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1) + .value("PseudoVLUXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1_MASK) + .value("PseudoVLUXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2) + .value("PseudoVLUXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK) + .value("PseudoVLUXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4) + .value("PseudoVLUXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK) + .value("PseudoVLUXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1) + .value("PseudoVLUXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1_MASK) + .value("PseudoVLUXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2) + .value("PseudoVLUXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK) + .value("PseudoVLUXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4) + .value("PseudoVLUXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK) + .value("PseudoVLUXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8) + .value("PseudoVLUXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK) + .value("PseudoVMACC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1) + .value("PseudoVMACC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1_MASK) + .value("PseudoVMACC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2) + .value("PseudoVMACC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2_MASK) + .value("PseudoVMACC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4) + .value("PseudoVMACC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4_MASK) + .value("PseudoVMACC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8) + .value("PseudoVMACC_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8_MASK) + .value("PseudoVMACC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2) + .value("PseudoVMACC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2_MASK) + .value("PseudoVMACC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4) + .value("PseudoVMACC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4_MASK) + .value("PseudoVMACC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8) + .value("PseudoVMACC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8_MASK) + .value("PseudoVMACC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1) + .value("PseudoVMACC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1_MASK) + .value("PseudoVMACC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2) + .value("PseudoVMACC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2_MASK) + .value("PseudoVMACC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4) + .value("PseudoVMACC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4_MASK) + .value("PseudoVMACC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8) + .value("PseudoVMACC_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8_MASK) + .value("PseudoVMACC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2) + .value("PseudoVMACC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2_MASK) + .value("PseudoVMACC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4) + .value("PseudoVMACC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4_MASK) + .value("PseudoVMACC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8) + .value("PseudoVMACC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8_MASK) + .value("PseudoVMADC_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M1) + .value("PseudoVMADC_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M2) + .value("PseudoVMADC_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M4) + .value("PseudoVMADC_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M8) + .value("PseudoVMADC_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF2) + .value("PseudoVMADC_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF4) + .value("PseudoVMADC_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF8) + .value("PseudoVMADC_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M1) + .value("PseudoVMADC_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M2) + .value("PseudoVMADC_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M4) + .value("PseudoVMADC_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M8) + .value("PseudoVMADC_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF2) + .value("PseudoVMADC_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF4) + .value("PseudoVMADC_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF8) + .value("PseudoVMADC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M1) + .value("PseudoVMADC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M2) + .value("PseudoVMADC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M4) + .value("PseudoVMADC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M8) + .value("PseudoVMADC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF2) + .value("PseudoVMADC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF4) + .value("PseudoVMADC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF8) + .value("PseudoVMADC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M1) + .value("PseudoVMADC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M2) + .value("PseudoVMADC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M4) + .value("PseudoVMADC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M8) + .value("PseudoVMADC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF2) + .value("PseudoVMADC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF4) + .value("PseudoVMADC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF8) + .value("PseudoVMADC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M1) + .value("PseudoVMADC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M2) + .value("PseudoVMADC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M4) + .value("PseudoVMADC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M8) + .value("PseudoVMADC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF2) + .value("PseudoVMADC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF4) + .value("PseudoVMADC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF8) + .value("PseudoVMADC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M1) + .value("PseudoVMADC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M2) + .value("PseudoVMADC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M4) + .value("PseudoVMADC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M8) + .value("PseudoVMADC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF2) + .value("PseudoVMADC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF4) + .value("PseudoVMADC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF8) + .value("PseudoVMADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1) + .value("PseudoVMADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1_MASK) + .value("PseudoVMADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2) + .value("PseudoVMADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2_MASK) + .value("PseudoVMADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4) + .value("PseudoVMADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4_MASK) + .value("PseudoVMADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8) + .value("PseudoVMADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8_MASK) + .value("PseudoVMADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2) + .value("PseudoVMADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2_MASK) + .value("PseudoVMADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4) + .value("PseudoVMADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4_MASK) + .value("PseudoVMADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8) + .value("PseudoVMADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8_MASK) + .value("PseudoVMADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1) + .value("PseudoVMADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1_MASK) + .value("PseudoVMADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2) + .value("PseudoVMADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2_MASK) + .value("PseudoVMADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4) + .value("PseudoVMADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4_MASK) + .value("PseudoVMADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8) + .value("PseudoVMADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8_MASK) + .value("PseudoVMADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2) + .value("PseudoVMADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2_MASK) + .value("PseudoVMADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4) + .value("PseudoVMADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4_MASK) + .value("PseudoVMADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8) + .value("PseudoVMADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8_MASK) + .value("PseudoVMANDN_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B1) + .value("PseudoVMANDN_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B16) + .value("PseudoVMANDN_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B2) + .value("PseudoVMANDN_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B32) + .value("PseudoVMANDN_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B4) + .value("PseudoVMANDN_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B64) + .value("PseudoVMANDN_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_B8) + .value("PseudoVMAND_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B1) + .value("PseudoVMAND_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B16) + .value("PseudoVMAND_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B2) + .value("PseudoVMAND_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B32) + .value("PseudoVMAND_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B4) + .value("PseudoVMAND_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B64) + .value("PseudoVMAND_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_B8) + .value("PseudoVMAXU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1) + .value("PseudoVMAXU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1_MASK) + .value("PseudoVMAXU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2) + .value("PseudoVMAXU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2_MASK) + .value("PseudoVMAXU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4) + .value("PseudoVMAXU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4_MASK) + .value("PseudoVMAXU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8) + .value("PseudoVMAXU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8_MASK) + .value("PseudoVMAXU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2) + .value("PseudoVMAXU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2_MASK) + .value("PseudoVMAXU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4) + .value("PseudoVMAXU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4_MASK) + .value("PseudoVMAXU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8) + .value("PseudoVMAXU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8_MASK) + .value("PseudoVMAXU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1) + .value("PseudoVMAXU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1_MASK) + .value("PseudoVMAXU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2) + .value("PseudoVMAXU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2_MASK) + .value("PseudoVMAXU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4) + .value("PseudoVMAXU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4_MASK) + .value("PseudoVMAXU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8) + .value("PseudoVMAXU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8_MASK) + .value("PseudoVMAXU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2) + .value("PseudoVMAXU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2_MASK) + .value("PseudoVMAXU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4) + .value("PseudoVMAXU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4_MASK) + .value("PseudoVMAXU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8) + .value("PseudoVMAXU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8_MASK) + .value("PseudoVMAX_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1) + .value("PseudoVMAX_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1_MASK) + .value("PseudoVMAX_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2) + .value("PseudoVMAX_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2_MASK) + .value("PseudoVMAX_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4) + .value("PseudoVMAX_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4_MASK) + .value("PseudoVMAX_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8) + .value("PseudoVMAX_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8_MASK) + .value("PseudoVMAX_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2) + .value("PseudoVMAX_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2_MASK) + .value("PseudoVMAX_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4) + .value("PseudoVMAX_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4_MASK) + .value("PseudoVMAX_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8) + .value("PseudoVMAX_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8_MASK) + .value("PseudoVMAX_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1) + .value("PseudoVMAX_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1_MASK) + .value("PseudoVMAX_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2) + .value("PseudoVMAX_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2_MASK) + .value("PseudoVMAX_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4) + .value("PseudoVMAX_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4_MASK) + .value("PseudoVMAX_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8) + .value("PseudoVMAX_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8_MASK) + .value("PseudoVMAX_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2) + .value("PseudoVMAX_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2_MASK) + .value("PseudoVMAX_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4) + .value("PseudoVMAX_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4_MASK) + .value("PseudoVMAX_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8) + .value("PseudoVMAX_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8_MASK) + .value("PseudoVMCLR_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B1) + .value("PseudoVMCLR_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B16) + .value("PseudoVMCLR_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B2) + .value("PseudoVMCLR_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B32) + .value("PseudoVMCLR_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B4) + .value("PseudoVMCLR_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B64) + .value("PseudoVMCLR_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B8) + .value("PseudoVMERGE_VIM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M1) + .value("PseudoVMERGE_VIM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M2) + .value("PseudoVMERGE_VIM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M4) + .value("PseudoVMERGE_VIM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M8) + .value("PseudoVMERGE_VIM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF2) + .value("PseudoVMERGE_VIM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF4) + .value("PseudoVMERGE_VIM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF8) + .value("PseudoVMERGE_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M1) + .value("PseudoVMERGE_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M2) + .value("PseudoVMERGE_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M4) + .value("PseudoVMERGE_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M8) + .value("PseudoVMERGE_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF2) + .value("PseudoVMERGE_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF4) + .value("PseudoVMERGE_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF8) + .value("PseudoVMERGE_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M1) + .value("PseudoVMERGE_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M2) + .value("PseudoVMERGE_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M4) + .value("PseudoVMERGE_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M8) + .value("PseudoVMERGE_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF2) + .value("PseudoVMERGE_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF4) + .value("PseudoVMERGE_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF8) + .value("PseudoVMFEQ_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M1) + .value("PseudoVMFEQ_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M1_MASK) + .value("PseudoVMFEQ_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M2) + .value("PseudoVMFEQ_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M2_MASK) + .value("PseudoVMFEQ_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M4) + .value("PseudoVMFEQ_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M4_MASK) + .value("PseudoVMFEQ_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M8) + .value("PseudoVMFEQ_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_M8_MASK) + .value("PseudoVMFEQ_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_MF2) + .value("PseudoVMFEQ_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFEQ_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_MF4) + .value("PseudoVMFEQ_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFEQ_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M1) + .value("PseudoVMFEQ_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M1_MASK) + .value("PseudoVMFEQ_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M2) + .value("PseudoVMFEQ_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M2_MASK) + .value("PseudoVMFEQ_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M4) + .value("PseudoVMFEQ_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M4_MASK) + .value("PseudoVMFEQ_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M8) + .value("PseudoVMFEQ_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_M8_MASK) + .value("PseudoVMFEQ_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_MF2) + .value("PseudoVMFEQ_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFEQ_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M1) + .value("PseudoVMFEQ_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M1_MASK) + .value("PseudoVMFEQ_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M2) + .value("PseudoVMFEQ_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M2_MASK) + .value("PseudoVMFEQ_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M4) + .value("PseudoVMFEQ_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M4_MASK) + .value("PseudoVMFEQ_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M8) + .value("PseudoVMFEQ_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VFPR64_M8_MASK) + .value("PseudoVMFEQ_ALT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M1) + .value("PseudoVMFEQ_ALT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M1_MASK) + .value("PseudoVMFEQ_ALT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M2) + .value("PseudoVMFEQ_ALT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M2_MASK) + .value("PseudoVMFEQ_ALT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M4) + .value("PseudoVMFEQ_ALT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M4_MASK) + .value("PseudoVMFEQ_ALT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M8) + .value("PseudoVMFEQ_ALT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_M8_MASK) + .value("PseudoVMFEQ_ALT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_MF2) + .value("PseudoVMFEQ_ALT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_MF2_MASK) + .value("PseudoVMFEQ_ALT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_MF4); + opcodes.value("PseudoVMFEQ_ALT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_ALT_VV_MF4_MASK) + .value("PseudoVMFEQ_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1) + .value("PseudoVMFEQ_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1_MASK) + .value("PseudoVMFEQ_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2) + .value("PseudoVMFEQ_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2_MASK) + .value("PseudoVMFEQ_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4) + .value("PseudoVMFEQ_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4_MASK) + .value("PseudoVMFEQ_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8) + .value("PseudoVMFEQ_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8_MASK) + .value("PseudoVMFEQ_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2) + .value("PseudoVMFEQ_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2_MASK) + .value("PseudoVMFEQ_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4) + .value("PseudoVMFEQ_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4_MASK) + .value("PseudoVMFEQ_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1) + .value("PseudoVMFEQ_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1_MASK) + .value("PseudoVMFEQ_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2) + .value("PseudoVMFEQ_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2_MASK) + .value("PseudoVMFEQ_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4) + .value("PseudoVMFEQ_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4_MASK) + .value("PseudoVMFEQ_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8) + .value("PseudoVMFEQ_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8_MASK) + .value("PseudoVMFEQ_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2) + .value("PseudoVMFEQ_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2_MASK) + .value("PseudoVMFEQ_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1) + .value("PseudoVMFEQ_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1_MASK) + .value("PseudoVMFEQ_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2) + .value("PseudoVMFEQ_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2_MASK) + .value("PseudoVMFEQ_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4) + .value("PseudoVMFEQ_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4_MASK) + .value("PseudoVMFEQ_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8) + .value("PseudoVMFEQ_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8_MASK) + .value("PseudoVMFEQ_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1) + .value("PseudoVMFEQ_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1_MASK) + .value("PseudoVMFEQ_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2) + .value("PseudoVMFEQ_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2_MASK) + .value("PseudoVMFEQ_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4) + .value("PseudoVMFEQ_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4_MASK) + .value("PseudoVMFEQ_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8) + .value("PseudoVMFEQ_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8_MASK) + .value("PseudoVMFEQ_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2) + .value("PseudoVMFEQ_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2_MASK) + .value("PseudoVMFEQ_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4) + .value("PseudoVMFEQ_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4_MASK) + .value("PseudoVMFGE_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M1) + .value("PseudoVMFGE_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M1_MASK) + .value("PseudoVMFGE_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M2) + .value("PseudoVMFGE_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M2_MASK) + .value("PseudoVMFGE_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M4) + .value("PseudoVMFGE_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M4_MASK) + .value("PseudoVMFGE_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M8) + .value("PseudoVMFGE_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_M8_MASK) + .value("PseudoVMFGE_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_MF2) + .value("PseudoVMFGE_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFGE_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_MF4) + .value("PseudoVMFGE_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFGE_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M1) + .value("PseudoVMFGE_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M1_MASK) + .value("PseudoVMFGE_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M2) + .value("PseudoVMFGE_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M2_MASK) + .value("PseudoVMFGE_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M4) + .value("PseudoVMFGE_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M4_MASK) + .value("PseudoVMFGE_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M8) + .value("PseudoVMFGE_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_M8_MASK) + .value("PseudoVMFGE_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_MF2) + .value("PseudoVMFGE_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFGE_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M1) + .value("PseudoVMFGE_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M1_MASK) + .value("PseudoVMFGE_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M2) + .value("PseudoVMFGE_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M2_MASK) + .value("PseudoVMFGE_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M4) + .value("PseudoVMFGE_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M4_MASK) + .value("PseudoVMFGE_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M8) + .value("PseudoVMFGE_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_ALT_VFPR64_M8_MASK) + .value("PseudoVMFGE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1) + .value("PseudoVMFGE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1_MASK) + .value("PseudoVMFGE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2) + .value("PseudoVMFGE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2_MASK) + .value("PseudoVMFGE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4) + .value("PseudoVMFGE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4_MASK) + .value("PseudoVMFGE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8) + .value("PseudoVMFGE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8_MASK) + .value("PseudoVMFGE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2) + .value("PseudoVMFGE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2_MASK) + .value("PseudoVMFGE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4) + .value("PseudoVMFGE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4_MASK) + .value("PseudoVMFGE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1) + .value("PseudoVMFGE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1_MASK) + .value("PseudoVMFGE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2) + .value("PseudoVMFGE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2_MASK) + .value("PseudoVMFGE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4) + .value("PseudoVMFGE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4_MASK) + .value("PseudoVMFGE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8) + .value("PseudoVMFGE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8_MASK) + .value("PseudoVMFGE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2) + .value("PseudoVMFGE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2_MASK) + .value("PseudoVMFGE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1) + .value("PseudoVMFGE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1_MASK) + .value("PseudoVMFGE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2) + .value("PseudoVMFGE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2_MASK) + .value("PseudoVMFGE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4) + .value("PseudoVMFGE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4_MASK) + .value("PseudoVMFGE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8) + .value("PseudoVMFGE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8_MASK) + .value("PseudoVMFGT_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M1) + .value("PseudoVMFGT_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M1_MASK) + .value("PseudoVMFGT_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M2) + .value("PseudoVMFGT_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M2_MASK) + .value("PseudoVMFGT_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M4) + .value("PseudoVMFGT_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M4_MASK) + .value("PseudoVMFGT_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M8) + .value("PseudoVMFGT_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_M8_MASK) + .value("PseudoVMFGT_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_MF2) + .value("PseudoVMFGT_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFGT_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_MF4) + .value("PseudoVMFGT_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFGT_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M1) + .value("PseudoVMFGT_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M1_MASK) + .value("PseudoVMFGT_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M2) + .value("PseudoVMFGT_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M2_MASK) + .value("PseudoVMFGT_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M4) + .value("PseudoVMFGT_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M4_MASK) + .value("PseudoVMFGT_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M8) + .value("PseudoVMFGT_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_M8_MASK) + .value("PseudoVMFGT_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_MF2) + .value("PseudoVMFGT_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFGT_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M1) + .value("PseudoVMFGT_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M1_MASK) + .value("PseudoVMFGT_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M2) + .value("PseudoVMFGT_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M2_MASK) + .value("PseudoVMFGT_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M4) + .value("PseudoVMFGT_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M4_MASK) + .value("PseudoVMFGT_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M8) + .value("PseudoVMFGT_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_ALT_VFPR64_M8_MASK) + .value("PseudoVMFGT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1) + .value("PseudoVMFGT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1_MASK) + .value("PseudoVMFGT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2) + .value("PseudoVMFGT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2_MASK) + .value("PseudoVMFGT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4) + .value("PseudoVMFGT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4_MASK) + .value("PseudoVMFGT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8) + .value("PseudoVMFGT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8_MASK) + .value("PseudoVMFGT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2) + .value("PseudoVMFGT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2_MASK) + .value("PseudoVMFGT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4) + .value("PseudoVMFGT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4_MASK) + .value("PseudoVMFGT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1) + .value("PseudoVMFGT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1_MASK) + .value("PseudoVMFGT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2) + .value("PseudoVMFGT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2_MASK) + .value("PseudoVMFGT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4) + .value("PseudoVMFGT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4_MASK) + .value("PseudoVMFGT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8) + .value("PseudoVMFGT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8_MASK) + .value("PseudoVMFGT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2) + .value("PseudoVMFGT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2_MASK) + .value("PseudoVMFGT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1) + .value("PseudoVMFGT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1_MASK) + .value("PseudoVMFGT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2) + .value("PseudoVMFGT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2_MASK) + .value("PseudoVMFGT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4) + .value("PseudoVMFGT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4_MASK) + .value("PseudoVMFGT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8) + .value("PseudoVMFGT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8_MASK) + .value("PseudoVMFLE_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M1) + .value("PseudoVMFLE_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M1_MASK) + .value("PseudoVMFLE_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M2) + .value("PseudoVMFLE_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M2_MASK) + .value("PseudoVMFLE_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M4) + .value("PseudoVMFLE_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M4_MASK) + .value("PseudoVMFLE_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M8) + .value("PseudoVMFLE_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_M8_MASK) + .value("PseudoVMFLE_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_MF2) + .value("PseudoVMFLE_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFLE_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_MF4) + .value("PseudoVMFLE_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFLE_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M1) + .value("PseudoVMFLE_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M1_MASK) + .value("PseudoVMFLE_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M2) + .value("PseudoVMFLE_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M2_MASK) + .value("PseudoVMFLE_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M4) + .value("PseudoVMFLE_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M4_MASK) + .value("PseudoVMFLE_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M8) + .value("PseudoVMFLE_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_M8_MASK) + .value("PseudoVMFLE_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_MF2) + .value("PseudoVMFLE_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFLE_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M1) + .value("PseudoVMFLE_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M1_MASK) + .value("PseudoVMFLE_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M2) + .value("PseudoVMFLE_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M2_MASK) + .value("PseudoVMFLE_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M4) + .value("PseudoVMFLE_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M4_MASK) + .value("PseudoVMFLE_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M8) + .value("PseudoVMFLE_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VFPR64_M8_MASK) + .value("PseudoVMFLE_ALT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M1) + .value("PseudoVMFLE_ALT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M1_MASK) + .value("PseudoVMFLE_ALT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M2) + .value("PseudoVMFLE_ALT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M2_MASK) + .value("PseudoVMFLE_ALT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M4) + .value("PseudoVMFLE_ALT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M4_MASK) + .value("PseudoVMFLE_ALT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M8) + .value("PseudoVMFLE_ALT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_M8_MASK) + .value("PseudoVMFLE_ALT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_MF2) + .value("PseudoVMFLE_ALT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_MF2_MASK) + .value("PseudoVMFLE_ALT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_MF4) + .value("PseudoVMFLE_ALT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_ALT_VV_MF4_MASK) + .value("PseudoVMFLE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1) + .value("PseudoVMFLE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1_MASK) + .value("PseudoVMFLE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2) + .value("PseudoVMFLE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2_MASK) + .value("PseudoVMFLE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4) + .value("PseudoVMFLE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4_MASK) + .value("PseudoVMFLE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8) + .value("PseudoVMFLE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8_MASK) + .value("PseudoVMFLE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2) + .value("PseudoVMFLE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2_MASK) + .value("PseudoVMFLE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4) + .value("PseudoVMFLE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4_MASK) + .value("PseudoVMFLE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1) + .value("PseudoVMFLE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1_MASK) + .value("PseudoVMFLE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2) + .value("PseudoVMFLE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2_MASK) + .value("PseudoVMFLE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4) + .value("PseudoVMFLE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4_MASK) + .value("PseudoVMFLE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8) + .value("PseudoVMFLE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8_MASK) + .value("PseudoVMFLE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2) + .value("PseudoVMFLE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2_MASK) + .value("PseudoVMFLE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1) + .value("PseudoVMFLE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1_MASK) + .value("PseudoVMFLE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2) + .value("PseudoVMFLE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2_MASK) + .value("PseudoVMFLE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4) + .value("PseudoVMFLE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4_MASK) + .value("PseudoVMFLE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8) + .value("PseudoVMFLE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8_MASK) + .value("PseudoVMFLE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1) + .value("PseudoVMFLE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1_MASK) + .value("PseudoVMFLE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2) + .value("PseudoVMFLE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2_MASK) + .value("PseudoVMFLE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4) + .value("PseudoVMFLE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4_MASK) + .value("PseudoVMFLE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8) + .value("PseudoVMFLE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8_MASK) + .value("PseudoVMFLE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2) + .value("PseudoVMFLE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2_MASK) + .value("PseudoVMFLE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4) + .value("PseudoVMFLE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4_MASK) + .value("PseudoVMFLT_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M1) + .value("PseudoVMFLT_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M1_MASK) + .value("PseudoVMFLT_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M2) + .value("PseudoVMFLT_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M2_MASK) + .value("PseudoVMFLT_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M4) + .value("PseudoVMFLT_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M4_MASK) + .value("PseudoVMFLT_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M8) + .value("PseudoVMFLT_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_M8_MASK) + .value("PseudoVMFLT_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_MF2) + .value("PseudoVMFLT_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFLT_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_MF4) + .value("PseudoVMFLT_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFLT_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M1) + .value("PseudoVMFLT_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M1_MASK) + .value("PseudoVMFLT_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M2) + .value("PseudoVMFLT_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M2_MASK) + .value("PseudoVMFLT_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M4) + .value("PseudoVMFLT_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M4_MASK) + .value("PseudoVMFLT_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M8) + .value("PseudoVMFLT_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_M8_MASK) + .value("PseudoVMFLT_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_MF2) + .value("PseudoVMFLT_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFLT_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M1) + .value("PseudoVMFLT_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M1_MASK) + .value("PseudoVMFLT_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M2) + .value("PseudoVMFLT_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M2_MASK) + .value("PseudoVMFLT_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M4) + .value("PseudoVMFLT_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M4_MASK) + .value("PseudoVMFLT_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M8) + .value("PseudoVMFLT_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VFPR64_M8_MASK) + .value("PseudoVMFLT_ALT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M1) + .value("PseudoVMFLT_ALT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M1_MASK) + .value("PseudoVMFLT_ALT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M2) + .value("PseudoVMFLT_ALT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M2_MASK) + .value("PseudoVMFLT_ALT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M4) + .value("PseudoVMFLT_ALT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M4_MASK) + .value("PseudoVMFLT_ALT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M8) + .value("PseudoVMFLT_ALT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_M8_MASK) + .value("PseudoVMFLT_ALT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_MF2) + .value("PseudoVMFLT_ALT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_MF2_MASK) + .value("PseudoVMFLT_ALT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_MF4) + .value("PseudoVMFLT_ALT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_ALT_VV_MF4_MASK) + .value("PseudoVMFLT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1) + .value("PseudoVMFLT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1_MASK) + .value("PseudoVMFLT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2) + .value("PseudoVMFLT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2_MASK) + .value("PseudoVMFLT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4) + .value("PseudoVMFLT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4_MASK) + .value("PseudoVMFLT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8) + .value("PseudoVMFLT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8_MASK) + .value("PseudoVMFLT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2) + .value("PseudoVMFLT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2_MASK) + .value("PseudoVMFLT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4); + opcodes.value("PseudoVMFLT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4_MASK) + .value("PseudoVMFLT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1) + .value("PseudoVMFLT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1_MASK) + .value("PseudoVMFLT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2) + .value("PseudoVMFLT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2_MASK) + .value("PseudoVMFLT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4) + .value("PseudoVMFLT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4_MASK) + .value("PseudoVMFLT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8) + .value("PseudoVMFLT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8_MASK) + .value("PseudoVMFLT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2) + .value("PseudoVMFLT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2_MASK) + .value("PseudoVMFLT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1) + .value("PseudoVMFLT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1_MASK) + .value("PseudoVMFLT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2) + .value("PseudoVMFLT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2_MASK) + .value("PseudoVMFLT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4) + .value("PseudoVMFLT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4_MASK) + .value("PseudoVMFLT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8) + .value("PseudoVMFLT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8_MASK) + .value("PseudoVMFLT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1) + .value("PseudoVMFLT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1_MASK) + .value("PseudoVMFLT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2) + .value("PseudoVMFLT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2_MASK) + .value("PseudoVMFLT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4) + .value("PseudoVMFLT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4_MASK) + .value("PseudoVMFLT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8) + .value("PseudoVMFLT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8_MASK) + .value("PseudoVMFLT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2) + .value("PseudoVMFLT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2_MASK) + .value("PseudoVMFLT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4) + .value("PseudoVMFLT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4_MASK) + .value("PseudoVMFNE_ALT_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M1) + .value("PseudoVMFNE_ALT_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M1_MASK) + .value("PseudoVMFNE_ALT_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M2) + .value("PseudoVMFNE_ALT_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M2_MASK) + .value("PseudoVMFNE_ALT_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M4) + .value("PseudoVMFNE_ALT_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M4_MASK) + .value("PseudoVMFNE_ALT_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M8) + .value("PseudoVMFNE_ALT_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_M8_MASK) + .value("PseudoVMFNE_ALT_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_MF2) + .value("PseudoVMFNE_ALT_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_MF2_MASK) + .value("PseudoVMFNE_ALT_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_MF4) + .value("PseudoVMFNE_ALT_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR16_MF4_MASK) + .value("PseudoVMFNE_ALT_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M1) + .value("PseudoVMFNE_ALT_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M1_MASK) + .value("PseudoVMFNE_ALT_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M2) + .value("PseudoVMFNE_ALT_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M2_MASK) + .value("PseudoVMFNE_ALT_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M4) + .value("PseudoVMFNE_ALT_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M4_MASK) + .value("PseudoVMFNE_ALT_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M8) + .value("PseudoVMFNE_ALT_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_M8_MASK) + .value("PseudoVMFNE_ALT_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_MF2) + .value("PseudoVMFNE_ALT_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR32_MF2_MASK) + .value("PseudoVMFNE_ALT_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M1) + .value("PseudoVMFNE_ALT_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M1_MASK) + .value("PseudoVMFNE_ALT_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M2) + .value("PseudoVMFNE_ALT_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M2_MASK) + .value("PseudoVMFNE_ALT_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M4) + .value("PseudoVMFNE_ALT_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M4_MASK) + .value("PseudoVMFNE_ALT_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M8) + .value("PseudoVMFNE_ALT_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VFPR64_M8_MASK) + .value("PseudoVMFNE_ALT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M1) + .value("PseudoVMFNE_ALT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M1_MASK) + .value("PseudoVMFNE_ALT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M2) + .value("PseudoVMFNE_ALT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M2_MASK) + .value("PseudoVMFNE_ALT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M4) + .value("PseudoVMFNE_ALT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M4_MASK) + .value("PseudoVMFNE_ALT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M8) + .value("PseudoVMFNE_ALT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_M8_MASK) + .value("PseudoVMFNE_ALT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_MF2) + .value("PseudoVMFNE_ALT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_MF2_MASK) + .value("PseudoVMFNE_ALT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_MF4) + .value("PseudoVMFNE_ALT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_ALT_VV_MF4_MASK) + .value("PseudoVMFNE_VFPR16_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1) + .value("PseudoVMFNE_VFPR16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1_MASK) + .value("PseudoVMFNE_VFPR16_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2) + .value("PseudoVMFNE_VFPR16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2_MASK) + .value("PseudoVMFNE_VFPR16_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4) + .value("PseudoVMFNE_VFPR16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4_MASK) + .value("PseudoVMFNE_VFPR16_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8) + .value("PseudoVMFNE_VFPR16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8_MASK) + .value("PseudoVMFNE_VFPR16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2) + .value("PseudoVMFNE_VFPR16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2_MASK) + .value("PseudoVMFNE_VFPR16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4) + .value("PseudoVMFNE_VFPR16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4_MASK) + .value("PseudoVMFNE_VFPR32_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1) + .value("PseudoVMFNE_VFPR32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1_MASK) + .value("PseudoVMFNE_VFPR32_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2) + .value("PseudoVMFNE_VFPR32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2_MASK) + .value("PseudoVMFNE_VFPR32_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4) + .value("PseudoVMFNE_VFPR32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4_MASK) + .value("PseudoVMFNE_VFPR32_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8) + .value("PseudoVMFNE_VFPR32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8_MASK) + .value("PseudoVMFNE_VFPR32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2) + .value("PseudoVMFNE_VFPR32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2_MASK) + .value("PseudoVMFNE_VFPR64_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1) + .value("PseudoVMFNE_VFPR64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1_MASK) + .value("PseudoVMFNE_VFPR64_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2) + .value("PseudoVMFNE_VFPR64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2_MASK) + .value("PseudoVMFNE_VFPR64_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4) + .value("PseudoVMFNE_VFPR64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4_MASK) + .value("PseudoVMFNE_VFPR64_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8) + .value("PseudoVMFNE_VFPR64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8_MASK) + .value("PseudoVMFNE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1) + .value("PseudoVMFNE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1_MASK) + .value("PseudoVMFNE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2) + .value("PseudoVMFNE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2_MASK) + .value("PseudoVMFNE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4) + .value("PseudoVMFNE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4_MASK) + .value("PseudoVMFNE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8) + .value("PseudoVMFNE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8_MASK) + .value("PseudoVMFNE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2) + .value("PseudoVMFNE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2_MASK) + .value("PseudoVMFNE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4) + .value("PseudoVMFNE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4_MASK) + .value("PseudoVMINU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1) + .value("PseudoVMINU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1_MASK) + .value("PseudoVMINU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2) + .value("PseudoVMINU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2_MASK) + .value("PseudoVMINU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4) + .value("PseudoVMINU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4_MASK) + .value("PseudoVMINU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8) + .value("PseudoVMINU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8_MASK) + .value("PseudoVMINU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2) + .value("PseudoVMINU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2_MASK) + .value("PseudoVMINU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4) + .value("PseudoVMINU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4_MASK) + .value("PseudoVMINU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8) + .value("PseudoVMINU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8_MASK) + .value("PseudoVMINU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1) + .value("PseudoVMINU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1_MASK) + .value("PseudoVMINU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2) + .value("PseudoVMINU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2_MASK) + .value("PseudoVMINU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4) + .value("PseudoVMINU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4_MASK) + .value("PseudoVMINU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8) + .value("PseudoVMINU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8_MASK) + .value("PseudoVMINU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2) + .value("PseudoVMINU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2_MASK) + .value("PseudoVMINU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4) + .value("PseudoVMINU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4_MASK) + .value("PseudoVMINU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8) + .value("PseudoVMINU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8_MASK) + .value("PseudoVMIN_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1) + .value("PseudoVMIN_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1_MASK) + .value("PseudoVMIN_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2) + .value("PseudoVMIN_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2_MASK) + .value("PseudoVMIN_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4) + .value("PseudoVMIN_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4_MASK) + .value("PseudoVMIN_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8) + .value("PseudoVMIN_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8_MASK) + .value("PseudoVMIN_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2) + .value("PseudoVMIN_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2_MASK) + .value("PseudoVMIN_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4) + .value("PseudoVMIN_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4_MASK) + .value("PseudoVMIN_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8) + .value("PseudoVMIN_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8_MASK) + .value("PseudoVMIN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1) + .value("PseudoVMIN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1_MASK) + .value("PseudoVMIN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2) + .value("PseudoVMIN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2_MASK) + .value("PseudoVMIN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4) + .value("PseudoVMIN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4_MASK) + .value("PseudoVMIN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8) + .value("PseudoVMIN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8_MASK) + .value("PseudoVMIN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2) + .value("PseudoVMIN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2_MASK) + .value("PseudoVMIN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4) + .value("PseudoVMIN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4_MASK) + .value("PseudoVMIN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8) + .value("PseudoVMIN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8_MASK) + .value("PseudoVMNAND_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B1) + .value("PseudoVMNAND_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B16) + .value("PseudoVMNAND_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B2) + .value("PseudoVMNAND_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B32) + .value("PseudoVMNAND_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B4) + .value("PseudoVMNAND_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B64) + .value("PseudoVMNAND_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_B8) + .value("PseudoVMNOR_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B1) + .value("PseudoVMNOR_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B16) + .value("PseudoVMNOR_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B2) + .value("PseudoVMNOR_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B32) + .value("PseudoVMNOR_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B4) + .value("PseudoVMNOR_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B64) + .value("PseudoVMNOR_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_B8) + .value("PseudoVMORN_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B1) + .value("PseudoVMORN_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B16) + .value("PseudoVMORN_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B2) + .value("PseudoVMORN_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B32) + .value("PseudoVMORN_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B4) + .value("PseudoVMORN_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B64) + .value("PseudoVMORN_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_B8) + .value("PseudoVMOR_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B1) + .value("PseudoVMOR_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B16) + .value("PseudoVMOR_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B2) + .value("PseudoVMOR_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B32) + .value("PseudoVMOR_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B4) + .value("PseudoVMOR_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B64) + .value("PseudoVMOR_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_B8) + .value("PseudoVMSBC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M1) + .value("PseudoVMSBC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M2) + .value("PseudoVMSBC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M4) + .value("PseudoVMSBC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M8) + .value("PseudoVMSBC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF2) + .value("PseudoVMSBC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF4) + .value("PseudoVMSBC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF8) + .value("PseudoVMSBC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M1) + .value("PseudoVMSBC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M2) + .value("PseudoVMSBC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M4) + .value("PseudoVMSBC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M8) + .value("PseudoVMSBC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF2) + .value("PseudoVMSBC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF4) + .value("PseudoVMSBC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF8) + .value("PseudoVMSBC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M1) + .value("PseudoVMSBC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M2) + .value("PseudoVMSBC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M4) + .value("PseudoVMSBC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M8) + .value("PseudoVMSBC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF2) + .value("PseudoVMSBC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF4) + .value("PseudoVMSBC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF8) + .value("PseudoVMSBC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M1) + .value("PseudoVMSBC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M2) + .value("PseudoVMSBC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M4) + .value("PseudoVMSBC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M8) + .value("PseudoVMSBC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF2) + .value("PseudoVMSBC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF4) + .value("PseudoVMSBC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF8) + .value("PseudoVMSBF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1) + .value("PseudoVMSBF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16) + .value("PseudoVMSBF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16_MASK) + .value("PseudoVMSBF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1_MASK) + .value("PseudoVMSBF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2) + .value("PseudoVMSBF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2_MASK) + .value("PseudoVMSBF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32) + .value("PseudoVMSBF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32_MASK) + .value("PseudoVMSBF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4) + .value("PseudoVMSBF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4_MASK) + .value("PseudoVMSBF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64) + .value("PseudoVMSBF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64_MASK) + .value("PseudoVMSBF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8) + .value("PseudoVMSBF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8_MASK) + .value("PseudoVMSEQ_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1) + .value("PseudoVMSEQ_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1_MASK) + .value("PseudoVMSEQ_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2) + .value("PseudoVMSEQ_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2_MASK) + .value("PseudoVMSEQ_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4) + .value("PseudoVMSEQ_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4_MASK) + .value("PseudoVMSEQ_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8) + .value("PseudoVMSEQ_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8_MASK) + .value("PseudoVMSEQ_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2) + .value("PseudoVMSEQ_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2_MASK) + .value("PseudoVMSEQ_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4) + .value("PseudoVMSEQ_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4_MASK) + .value("PseudoVMSEQ_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8) + .value("PseudoVMSEQ_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8_MASK) + .value("PseudoVMSEQ_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1) + .value("PseudoVMSEQ_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1_MASK) + .value("PseudoVMSEQ_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2) + .value("PseudoVMSEQ_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2_MASK) + .value("PseudoVMSEQ_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4) + .value("PseudoVMSEQ_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4_MASK) + .value("PseudoVMSEQ_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8) + .value("PseudoVMSEQ_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8_MASK) + .value("PseudoVMSEQ_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2) + .value("PseudoVMSEQ_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2_MASK) + .value("PseudoVMSEQ_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4) + .value("PseudoVMSEQ_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4_MASK) + .value("PseudoVMSEQ_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8) + .value("PseudoVMSEQ_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8_MASK) + .value("PseudoVMSEQ_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1) + .value("PseudoVMSEQ_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1_MASK) + .value("PseudoVMSEQ_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2) + .value("PseudoVMSEQ_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2_MASK) + .value("PseudoVMSEQ_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4) + .value("PseudoVMSEQ_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4_MASK) + .value("PseudoVMSEQ_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8) + .value("PseudoVMSEQ_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8_MASK) + .value("PseudoVMSEQ_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2) + .value("PseudoVMSEQ_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2_MASK) + .value("PseudoVMSEQ_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4) + .value("PseudoVMSEQ_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4_MASK) + .value("PseudoVMSEQ_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8) + .value("PseudoVMSEQ_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8_MASK) + .value("PseudoVMSET_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B1) + .value("PseudoVMSET_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B16) + .value("PseudoVMSET_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B2) + .value("PseudoVMSET_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B32) + .value("PseudoVMSET_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B4) + .value("PseudoVMSET_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B64) + .value("PseudoVMSET_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B8) + .value("PseudoVMSGEU_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VI) + .value("PseudoVMSGEU_VX", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX) + .value("PseudoVMSGEU_VX_M", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M) + .value("PseudoVMSGEU_VX_M_T", LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M_T) + .value("PseudoVMSGE_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VI) + .value("PseudoVMSGE_VX", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX) + .value("PseudoVMSGE_VX_M", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M) + .value("PseudoVMSGE_VX_M_T", LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M_T) + .value("PseudoVMSGTU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1) + .value("PseudoVMSGTU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1_MASK); + opcodes.value("PseudoVMSGTU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2) + .value("PseudoVMSGTU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2_MASK) + .value("PseudoVMSGTU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4) + .value("PseudoVMSGTU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4_MASK) + .value("PseudoVMSGTU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8) + .value("PseudoVMSGTU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8_MASK) + .value("PseudoVMSGTU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2) + .value("PseudoVMSGTU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2_MASK) + .value("PseudoVMSGTU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4) + .value("PseudoVMSGTU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4_MASK) + .value("PseudoVMSGTU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8) + .value("PseudoVMSGTU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8_MASK) + .value("PseudoVMSGTU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1) + .value("PseudoVMSGTU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1_MASK) + .value("PseudoVMSGTU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2) + .value("PseudoVMSGTU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2_MASK) + .value("PseudoVMSGTU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4) + .value("PseudoVMSGTU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4_MASK) + .value("PseudoVMSGTU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8) + .value("PseudoVMSGTU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8_MASK) + .value("PseudoVMSGTU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2) + .value("PseudoVMSGTU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2_MASK) + .value("PseudoVMSGTU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4) + .value("PseudoVMSGTU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4_MASK) + .value("PseudoVMSGTU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8) + .value("PseudoVMSGTU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8_MASK) + .value("PseudoVMSGT_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1) + .value("PseudoVMSGT_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1_MASK) + .value("PseudoVMSGT_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2) + .value("PseudoVMSGT_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2_MASK) + .value("PseudoVMSGT_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4) + .value("PseudoVMSGT_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4_MASK) + .value("PseudoVMSGT_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8) + .value("PseudoVMSGT_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8_MASK) + .value("PseudoVMSGT_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2) + .value("PseudoVMSGT_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2_MASK) + .value("PseudoVMSGT_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4) + .value("PseudoVMSGT_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4_MASK) + .value("PseudoVMSGT_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8) + .value("PseudoVMSGT_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8_MASK) + .value("PseudoVMSGT_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1) + .value("PseudoVMSGT_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1_MASK) + .value("PseudoVMSGT_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2) + .value("PseudoVMSGT_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2_MASK) + .value("PseudoVMSGT_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4) + .value("PseudoVMSGT_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4_MASK) + .value("PseudoVMSGT_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8) + .value("PseudoVMSGT_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8_MASK) + .value("PseudoVMSGT_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2) + .value("PseudoVMSGT_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2_MASK) + .value("PseudoVMSGT_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4) + .value("PseudoVMSGT_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4_MASK) + .value("PseudoVMSGT_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8) + .value("PseudoVMSGT_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8_MASK) + .value("PseudoVMSIF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1) + .value("PseudoVMSIF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16) + .value("PseudoVMSIF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16_MASK) + .value("PseudoVMSIF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1_MASK) + .value("PseudoVMSIF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2) + .value("PseudoVMSIF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2_MASK) + .value("PseudoVMSIF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32) + .value("PseudoVMSIF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32_MASK) + .value("PseudoVMSIF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4) + .value("PseudoVMSIF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4_MASK) + .value("PseudoVMSIF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64) + .value("PseudoVMSIF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64_MASK) + .value("PseudoVMSIF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8) + .value("PseudoVMSIF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8_MASK) + .value("PseudoVMSLEU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1) + .value("PseudoVMSLEU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1_MASK) + .value("PseudoVMSLEU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2) + .value("PseudoVMSLEU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2_MASK) + .value("PseudoVMSLEU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4) + .value("PseudoVMSLEU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4_MASK) + .value("PseudoVMSLEU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8) + .value("PseudoVMSLEU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8_MASK) + .value("PseudoVMSLEU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2) + .value("PseudoVMSLEU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2_MASK) + .value("PseudoVMSLEU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4) + .value("PseudoVMSLEU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4_MASK) + .value("PseudoVMSLEU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8) + .value("PseudoVMSLEU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8_MASK) + .value("PseudoVMSLEU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1) + .value("PseudoVMSLEU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1_MASK) + .value("PseudoVMSLEU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2) + .value("PseudoVMSLEU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2_MASK) + .value("PseudoVMSLEU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4) + .value("PseudoVMSLEU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4_MASK) + .value("PseudoVMSLEU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8) + .value("PseudoVMSLEU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8_MASK) + .value("PseudoVMSLEU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2) + .value("PseudoVMSLEU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2_MASK) + .value("PseudoVMSLEU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4) + .value("PseudoVMSLEU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4_MASK) + .value("PseudoVMSLEU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8) + .value("PseudoVMSLEU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8_MASK) + .value("PseudoVMSLEU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1) + .value("PseudoVMSLEU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1_MASK) + .value("PseudoVMSLEU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2) + .value("PseudoVMSLEU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2_MASK) + .value("PseudoVMSLEU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4) + .value("PseudoVMSLEU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4_MASK) + .value("PseudoVMSLEU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8) + .value("PseudoVMSLEU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8_MASK) + .value("PseudoVMSLEU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2) + .value("PseudoVMSLEU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2_MASK) + .value("PseudoVMSLEU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4) + .value("PseudoVMSLEU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4_MASK) + .value("PseudoVMSLEU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8) + .value("PseudoVMSLEU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8_MASK) + .value("PseudoVMSLE_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1) + .value("PseudoVMSLE_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1_MASK) + .value("PseudoVMSLE_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2) + .value("PseudoVMSLE_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2_MASK) + .value("PseudoVMSLE_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4) + .value("PseudoVMSLE_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4_MASK) + .value("PseudoVMSLE_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8) + .value("PseudoVMSLE_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8_MASK) + .value("PseudoVMSLE_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2) + .value("PseudoVMSLE_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2_MASK) + .value("PseudoVMSLE_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4) + .value("PseudoVMSLE_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4_MASK) + .value("PseudoVMSLE_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8) + .value("PseudoVMSLE_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8_MASK) + .value("PseudoVMSLE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1) + .value("PseudoVMSLE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1_MASK) + .value("PseudoVMSLE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2) + .value("PseudoVMSLE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2_MASK) + .value("PseudoVMSLE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4) + .value("PseudoVMSLE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4_MASK) + .value("PseudoVMSLE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8) + .value("PseudoVMSLE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8_MASK) + .value("PseudoVMSLE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2) + .value("PseudoVMSLE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2_MASK) + .value("PseudoVMSLE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4) + .value("PseudoVMSLE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4_MASK) + .value("PseudoVMSLE_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8) + .value("PseudoVMSLE_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8_MASK) + .value("PseudoVMSLE_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1) + .value("PseudoVMSLE_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1_MASK) + .value("PseudoVMSLE_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2) + .value("PseudoVMSLE_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2_MASK) + .value("PseudoVMSLE_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4) + .value("PseudoVMSLE_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4_MASK) + .value("PseudoVMSLE_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8) + .value("PseudoVMSLE_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8_MASK) + .value("PseudoVMSLE_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2) + .value("PseudoVMSLE_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2_MASK) + .value("PseudoVMSLE_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4) + .value("PseudoVMSLE_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4_MASK) + .value("PseudoVMSLE_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8) + .value("PseudoVMSLE_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8_MASK) + .value("PseudoVMSLTU_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VI) + .value("PseudoVMSLTU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1) + .value("PseudoVMSLTU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1_MASK) + .value("PseudoVMSLTU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2) + .value("PseudoVMSLTU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2_MASK) + .value("PseudoVMSLTU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4) + .value("PseudoVMSLTU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4_MASK) + .value("PseudoVMSLTU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8) + .value("PseudoVMSLTU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8_MASK) + .value("PseudoVMSLTU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2) + .value("PseudoVMSLTU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2_MASK) + .value("PseudoVMSLTU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4) + .value("PseudoVMSLTU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4_MASK) + .value("PseudoVMSLTU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8) + .value("PseudoVMSLTU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8_MASK) + .value("PseudoVMSLTU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1) + .value("PseudoVMSLTU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1_MASK) + .value("PseudoVMSLTU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2) + .value("PseudoVMSLTU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2_MASK) + .value("PseudoVMSLTU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4) + .value("PseudoVMSLTU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4_MASK) + .value("PseudoVMSLTU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8) + .value("PseudoVMSLTU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8_MASK) + .value("PseudoVMSLTU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2) + .value("PseudoVMSLTU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2_MASK) + .value("PseudoVMSLTU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4) + .value("PseudoVMSLTU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4_MASK) + .value("PseudoVMSLTU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8) + .value("PseudoVMSLTU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8_MASK) + .value("PseudoVMSLT_VI", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VI) + .value("PseudoVMSLT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1) + .value("PseudoVMSLT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1_MASK) + .value("PseudoVMSLT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2) + .value("PseudoVMSLT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2_MASK) + .value("PseudoVMSLT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4) + .value("PseudoVMSLT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4_MASK) + .value("PseudoVMSLT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8) + .value("PseudoVMSLT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8_MASK) + .value("PseudoVMSLT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2) + .value("PseudoVMSLT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2_MASK) + .value("PseudoVMSLT_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4) + .value("PseudoVMSLT_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4_MASK) + .value("PseudoVMSLT_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8) + .value("PseudoVMSLT_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8_MASK) + .value("PseudoVMSLT_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1) + .value("PseudoVMSLT_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1_MASK) + .value("PseudoVMSLT_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2) + .value("PseudoVMSLT_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2_MASK) + .value("PseudoVMSLT_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4) + .value("PseudoVMSLT_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4_MASK) + .value("PseudoVMSLT_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8) + .value("PseudoVMSLT_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8_MASK) + .value("PseudoVMSLT_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2) + .value("PseudoVMSLT_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2_MASK) + .value("PseudoVMSLT_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4) + .value("PseudoVMSLT_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4_MASK) + .value("PseudoVMSLT_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8) + .value("PseudoVMSLT_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8_MASK) + .value("PseudoVMSNE_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1) + .value("PseudoVMSNE_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1_MASK) + .value("PseudoVMSNE_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2) + .value("PseudoVMSNE_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2_MASK) + .value("PseudoVMSNE_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4) + .value("PseudoVMSNE_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4_MASK) + .value("PseudoVMSNE_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8) + .value("PseudoVMSNE_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8_MASK) + .value("PseudoVMSNE_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2) + .value("PseudoVMSNE_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2_MASK) + .value("PseudoVMSNE_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4) + .value("PseudoVMSNE_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4_MASK) + .value("PseudoVMSNE_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8) + .value("PseudoVMSNE_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8_MASK) + .value("PseudoVMSNE_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1) + .value("PseudoVMSNE_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1_MASK) + .value("PseudoVMSNE_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2) + .value("PseudoVMSNE_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2_MASK) + .value("PseudoVMSNE_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4) + .value("PseudoVMSNE_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4_MASK) + .value("PseudoVMSNE_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8) + .value("PseudoVMSNE_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8_MASK) + .value("PseudoVMSNE_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2) + .value("PseudoVMSNE_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2_MASK) + .value("PseudoVMSNE_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4) + .value("PseudoVMSNE_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4_MASK) + .value("PseudoVMSNE_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8) + .value("PseudoVMSNE_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8_MASK) + .value("PseudoVMSNE_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1) + .value("PseudoVMSNE_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1_MASK) + .value("PseudoVMSNE_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2) + .value("PseudoVMSNE_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2_MASK) + .value("PseudoVMSNE_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4) + .value("PseudoVMSNE_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4_MASK) + .value("PseudoVMSNE_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8) + .value("PseudoVMSNE_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8_MASK) + .value("PseudoVMSNE_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2) + .value("PseudoVMSNE_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2_MASK) + .value("PseudoVMSNE_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4) + .value("PseudoVMSNE_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4_MASK) + .value("PseudoVMSNE_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8) + .value("PseudoVMSNE_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8_MASK) + .value("PseudoVMSOF_M_B1", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1) + .value("PseudoVMSOF_M_B16", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16) + .value("PseudoVMSOF_M_B16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16_MASK) + .value("PseudoVMSOF_M_B1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1_MASK) + .value("PseudoVMSOF_M_B2", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2) + .value("PseudoVMSOF_M_B2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2_MASK) + .value("PseudoVMSOF_M_B32", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32) + .value("PseudoVMSOF_M_B32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32_MASK) + .value("PseudoVMSOF_M_B4", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4) + .value("PseudoVMSOF_M_B4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4_MASK) + .value("PseudoVMSOF_M_B64", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64) + .value("PseudoVMSOF_M_B64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64_MASK) + .value("PseudoVMSOF_M_B8", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8) + .value("PseudoVMSOF_M_B8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8_MASK) + .value("PseudoVMULHSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1) + .value("PseudoVMULHSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1_MASK) + .value("PseudoVMULHSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2) + .value("PseudoVMULHSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2_MASK) + .value("PseudoVMULHSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4) + .value("PseudoVMULHSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4_MASK) + .value("PseudoVMULHSU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8) + .value("PseudoVMULHSU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8_MASK) + .value("PseudoVMULHSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2) + .value("PseudoVMULHSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2_MASK) + .value("PseudoVMULHSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4) + .value("PseudoVMULHSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4_MASK) + .value("PseudoVMULHSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8) + .value("PseudoVMULHSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8_MASK) + .value("PseudoVMULHSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1) + .value("PseudoVMULHSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1_MASK) + .value("PseudoVMULHSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2) + .value("PseudoVMULHSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2_MASK) + .value("PseudoVMULHSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4) + .value("PseudoVMULHSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4_MASK) + .value("PseudoVMULHSU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8) + .value("PseudoVMULHSU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8_MASK) + .value("PseudoVMULHSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2) + .value("PseudoVMULHSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2_MASK) + .value("PseudoVMULHSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4) + .value("PseudoVMULHSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4_MASK) + .value("PseudoVMULHSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8) + .value("PseudoVMULHSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8_MASK) + .value("PseudoVMULHU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1) + .value("PseudoVMULHU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1_MASK) + .value("PseudoVMULHU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2) + .value("PseudoVMULHU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2_MASK) + .value("PseudoVMULHU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4) + .value("PseudoVMULHU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4_MASK); + opcodes.value("PseudoVMULHU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8) + .value("PseudoVMULHU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8_MASK) + .value("PseudoVMULHU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2) + .value("PseudoVMULHU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2_MASK) + .value("PseudoVMULHU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4) + .value("PseudoVMULHU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4_MASK) + .value("PseudoVMULHU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8) + .value("PseudoVMULHU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8_MASK) + .value("PseudoVMULHU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1) + .value("PseudoVMULHU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1_MASK) + .value("PseudoVMULHU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2) + .value("PseudoVMULHU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2_MASK) + .value("PseudoVMULHU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4) + .value("PseudoVMULHU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4_MASK) + .value("PseudoVMULHU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8) + .value("PseudoVMULHU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8_MASK) + .value("PseudoVMULHU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2) + .value("PseudoVMULHU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2_MASK) + .value("PseudoVMULHU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4) + .value("PseudoVMULHU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4_MASK) + .value("PseudoVMULHU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8) + .value("PseudoVMULHU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8_MASK) + .value("PseudoVMULH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1) + .value("PseudoVMULH_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1_MASK) + .value("PseudoVMULH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2) + .value("PseudoVMULH_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2_MASK) + .value("PseudoVMULH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4) + .value("PseudoVMULH_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4_MASK) + .value("PseudoVMULH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8) + .value("PseudoVMULH_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8_MASK) + .value("PseudoVMULH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2) + .value("PseudoVMULH_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2_MASK) + .value("PseudoVMULH_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4) + .value("PseudoVMULH_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4_MASK) + .value("PseudoVMULH_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8) + .value("PseudoVMULH_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8_MASK) + .value("PseudoVMULH_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1) + .value("PseudoVMULH_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1_MASK) + .value("PseudoVMULH_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2) + .value("PseudoVMULH_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2_MASK) + .value("PseudoVMULH_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4) + .value("PseudoVMULH_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4_MASK) + .value("PseudoVMULH_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8) + .value("PseudoVMULH_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8_MASK) + .value("PseudoVMULH_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2) + .value("PseudoVMULH_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2_MASK) + .value("PseudoVMULH_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4) + .value("PseudoVMULH_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4_MASK) + .value("PseudoVMULH_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8) + .value("PseudoVMULH_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8_MASK) + .value("PseudoVMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1) + .value("PseudoVMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1_MASK) + .value("PseudoVMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2) + .value("PseudoVMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2_MASK) + .value("PseudoVMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4) + .value("PseudoVMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4_MASK) + .value("PseudoVMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8) + .value("PseudoVMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8_MASK) + .value("PseudoVMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2) + .value("PseudoVMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2_MASK) + .value("PseudoVMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4) + .value("PseudoVMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4_MASK) + .value("PseudoVMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8) + .value("PseudoVMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8_MASK) + .value("PseudoVMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1) + .value("PseudoVMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1_MASK) + .value("PseudoVMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2) + .value("PseudoVMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2_MASK) + .value("PseudoVMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4) + .value("PseudoVMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4_MASK) + .value("PseudoVMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8) + .value("PseudoVMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8_MASK) + .value("PseudoVMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2) + .value("PseudoVMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2_MASK) + .value("PseudoVMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4) + .value("PseudoVMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4_MASK) + .value("PseudoVMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8) + .value("PseudoVMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8_MASK) + .value("PseudoVMV_S_X", LIEF::assembly::riscv::OPCODE::PseudoVMV_S_X) + .value("PseudoVMV_V_I_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M1) + .value("PseudoVMV_V_I_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M2) + .value("PseudoVMV_V_I_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M4) + .value("PseudoVMV_V_I_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M8) + .value("PseudoVMV_V_I_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF2) + .value("PseudoVMV_V_I_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF4) + .value("PseudoVMV_V_I_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF8) + .value("PseudoVMV_V_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M1) + .value("PseudoVMV_V_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M2) + .value("PseudoVMV_V_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M4) + .value("PseudoVMV_V_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M8) + .value("PseudoVMV_V_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF2) + .value("PseudoVMV_V_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF4) + .value("PseudoVMV_V_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF8) + .value("PseudoVMV_V_X_M1", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M1) + .value("PseudoVMV_V_X_M2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M2) + .value("PseudoVMV_V_X_M4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M4) + .value("PseudoVMV_V_X_M8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M8) + .value("PseudoVMV_V_X_MF2", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF2) + .value("PseudoVMV_V_X_MF4", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF4) + .value("PseudoVMV_V_X_MF8", LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF8) + .value("PseudoVMV_X_S", LIEF::assembly::riscv::OPCODE::PseudoVMV_X_S) + .value("PseudoVMXNOR_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B1) + .value("PseudoVMXNOR_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B16) + .value("PseudoVMXNOR_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B2) + .value("PseudoVMXNOR_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B32) + .value("PseudoVMXNOR_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B4) + .value("PseudoVMXNOR_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B64) + .value("PseudoVMXNOR_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_B8) + .value("PseudoVMXOR_MM_B1", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B1) + .value("PseudoVMXOR_MM_B16", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B16) + .value("PseudoVMXOR_MM_B2", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B2) + .value("PseudoVMXOR_MM_B32", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B32) + .value("PseudoVMXOR_MM_B4", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B4) + .value("PseudoVMXOR_MM_B64", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B64) + .value("PseudoVMXOR_MM_B8", LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_B8) + .value("PseudoVNCLIPU_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1) + .value("PseudoVNCLIPU_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1_MASK) + .value("PseudoVNCLIPU_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2) + .value("PseudoVNCLIPU_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2_MASK) + .value("PseudoVNCLIPU_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4) + .value("PseudoVNCLIPU_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4_MASK) + .value("PseudoVNCLIPU_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2) + .value("PseudoVNCLIPU_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2_MASK) + .value("PseudoVNCLIPU_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4) + .value("PseudoVNCLIPU_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4_MASK) + .value("PseudoVNCLIPU_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8) + .value("PseudoVNCLIPU_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8_MASK) + .value("PseudoVNCLIPU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1) + .value("PseudoVNCLIPU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1_MASK) + .value("PseudoVNCLIPU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2) + .value("PseudoVNCLIPU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2_MASK) + .value("PseudoVNCLIPU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4) + .value("PseudoVNCLIPU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4_MASK) + .value("PseudoVNCLIPU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2) + .value("PseudoVNCLIPU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2_MASK) + .value("PseudoVNCLIPU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4) + .value("PseudoVNCLIPU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4_MASK) + .value("PseudoVNCLIPU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8) + .value("PseudoVNCLIPU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8_MASK) + .value("PseudoVNCLIPU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1) + .value("PseudoVNCLIPU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1_MASK) + .value("PseudoVNCLIPU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2) + .value("PseudoVNCLIPU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2_MASK) + .value("PseudoVNCLIPU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4) + .value("PseudoVNCLIPU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4_MASK) + .value("PseudoVNCLIPU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2) + .value("PseudoVNCLIPU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2_MASK) + .value("PseudoVNCLIPU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4) + .value("PseudoVNCLIPU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4_MASK) + .value("PseudoVNCLIPU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8) + .value("PseudoVNCLIPU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8_MASK) + .value("PseudoVNCLIP_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1) + .value("PseudoVNCLIP_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1_MASK) + .value("PseudoVNCLIP_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2) + .value("PseudoVNCLIP_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2_MASK) + .value("PseudoVNCLIP_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4) + .value("PseudoVNCLIP_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4_MASK) + .value("PseudoVNCLIP_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2) + .value("PseudoVNCLIP_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2_MASK) + .value("PseudoVNCLIP_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4) + .value("PseudoVNCLIP_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4_MASK) + .value("PseudoVNCLIP_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8) + .value("PseudoVNCLIP_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8_MASK) + .value("PseudoVNCLIP_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1) + .value("PseudoVNCLIP_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1_MASK) + .value("PseudoVNCLIP_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2) + .value("PseudoVNCLIP_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2_MASK) + .value("PseudoVNCLIP_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4) + .value("PseudoVNCLIP_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4_MASK) + .value("PseudoVNCLIP_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2) + .value("PseudoVNCLIP_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2_MASK) + .value("PseudoVNCLIP_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4) + .value("PseudoVNCLIP_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4_MASK) + .value("PseudoVNCLIP_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8) + .value("PseudoVNCLIP_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8_MASK) + .value("PseudoVNCLIP_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1) + .value("PseudoVNCLIP_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1_MASK) + .value("PseudoVNCLIP_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2) + .value("PseudoVNCLIP_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2_MASK) + .value("PseudoVNCLIP_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4) + .value("PseudoVNCLIP_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4_MASK) + .value("PseudoVNCLIP_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2) + .value("PseudoVNCLIP_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2_MASK) + .value("PseudoVNCLIP_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4) + .value("PseudoVNCLIP_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4_MASK) + .value("PseudoVNCLIP_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8) + .value("PseudoVNCLIP_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8_MASK) + .value("PseudoVNMSAC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1) + .value("PseudoVNMSAC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1_MASK) + .value("PseudoVNMSAC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2) + .value("PseudoVNMSAC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2_MASK) + .value("PseudoVNMSAC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4) + .value("PseudoVNMSAC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4_MASK) + .value("PseudoVNMSAC_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8) + .value("PseudoVNMSAC_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8_MASK) + .value("PseudoVNMSAC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2) + .value("PseudoVNMSAC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2_MASK) + .value("PseudoVNMSAC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4) + .value("PseudoVNMSAC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4_MASK) + .value("PseudoVNMSAC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8) + .value("PseudoVNMSAC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8_MASK) + .value("PseudoVNMSAC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1) + .value("PseudoVNMSAC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1_MASK) + .value("PseudoVNMSAC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2) + .value("PseudoVNMSAC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2_MASK) + .value("PseudoVNMSAC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4) + .value("PseudoVNMSAC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4_MASK) + .value("PseudoVNMSAC_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8) + .value("PseudoVNMSAC_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8_MASK) + .value("PseudoVNMSAC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2) + .value("PseudoVNMSAC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2_MASK) + .value("PseudoVNMSAC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4) + .value("PseudoVNMSAC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4_MASK) + .value("PseudoVNMSAC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8) + .value("PseudoVNMSAC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8_MASK) + .value("PseudoVNMSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1) + .value("PseudoVNMSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1_MASK) + .value("PseudoVNMSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2) + .value("PseudoVNMSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2_MASK) + .value("PseudoVNMSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4) + .value("PseudoVNMSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4_MASK) + .value("PseudoVNMSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8) + .value("PseudoVNMSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8_MASK) + .value("PseudoVNMSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2) + .value("PseudoVNMSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2_MASK) + .value("PseudoVNMSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4) + .value("PseudoVNMSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4_MASK) + .value("PseudoVNMSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8) + .value("PseudoVNMSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8_MASK) + .value("PseudoVNMSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1) + .value("PseudoVNMSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1_MASK) + .value("PseudoVNMSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2) + .value("PseudoVNMSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2_MASK) + .value("PseudoVNMSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4) + .value("PseudoVNMSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4_MASK) + .value("PseudoVNMSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8) + .value("PseudoVNMSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8_MASK) + .value("PseudoVNMSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2) + .value("PseudoVNMSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2_MASK) + .value("PseudoVNMSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4) + .value("PseudoVNMSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4_MASK) + .value("PseudoVNMSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8) + .value("PseudoVNMSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8_MASK) + .value("PseudoVNSRA_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1) + .value("PseudoVNSRA_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1_MASK) + .value("PseudoVNSRA_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2) + .value("PseudoVNSRA_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2_MASK) + .value("PseudoVNSRA_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4) + .value("PseudoVNSRA_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4_MASK) + .value("PseudoVNSRA_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2) + .value("PseudoVNSRA_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2_MASK) + .value("PseudoVNSRA_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4) + .value("PseudoVNSRA_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4_MASK) + .value("PseudoVNSRA_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8) + .value("PseudoVNSRA_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8_MASK) + .value("PseudoVNSRA_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1) + .value("PseudoVNSRA_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1_MASK) + .value("PseudoVNSRA_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2) + .value("PseudoVNSRA_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2_MASK) + .value("PseudoVNSRA_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4) + .value("PseudoVNSRA_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4_MASK) + .value("PseudoVNSRA_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2) + .value("PseudoVNSRA_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2_MASK) + .value("PseudoVNSRA_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4) + .value("PseudoVNSRA_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4_MASK) + .value("PseudoVNSRA_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8) + .value("PseudoVNSRA_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8_MASK) + .value("PseudoVNSRA_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1) + .value("PseudoVNSRA_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1_MASK) + .value("PseudoVNSRA_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2) + .value("PseudoVNSRA_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2_MASK) + .value("PseudoVNSRA_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4) + .value("PseudoVNSRA_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4_MASK) + .value("PseudoVNSRA_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2) + .value("PseudoVNSRA_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2_MASK) + .value("PseudoVNSRA_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4) + .value("PseudoVNSRA_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4_MASK) + .value("PseudoVNSRA_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8) + .value("PseudoVNSRA_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8_MASK) + .value("PseudoVNSRL_WI_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1) + .value("PseudoVNSRL_WI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1_MASK) + .value("PseudoVNSRL_WI_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2) + .value("PseudoVNSRL_WI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2_MASK) + .value("PseudoVNSRL_WI_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4) + .value("PseudoVNSRL_WI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4_MASK) + .value("PseudoVNSRL_WI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2) + .value("PseudoVNSRL_WI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2_MASK) + .value("PseudoVNSRL_WI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4) + .value("PseudoVNSRL_WI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4_MASK) + .value("PseudoVNSRL_WI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8) + .value("PseudoVNSRL_WI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8_MASK) + .value("PseudoVNSRL_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1) + .value("PseudoVNSRL_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1_MASK) + .value("PseudoVNSRL_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2) + .value("PseudoVNSRL_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2_MASK) + .value("PseudoVNSRL_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4) + .value("PseudoVNSRL_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4_MASK) + .value("PseudoVNSRL_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2) + .value("PseudoVNSRL_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2_MASK) + .value("PseudoVNSRL_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4); + opcodes.value("PseudoVNSRL_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4_MASK) + .value("PseudoVNSRL_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8) + .value("PseudoVNSRL_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8_MASK) + .value("PseudoVNSRL_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1) + .value("PseudoVNSRL_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1_MASK) + .value("PseudoVNSRL_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2) + .value("PseudoVNSRL_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2_MASK) + .value("PseudoVNSRL_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4) + .value("PseudoVNSRL_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4_MASK) + .value("PseudoVNSRL_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2) + .value("PseudoVNSRL_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2_MASK) + .value("PseudoVNSRL_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4) + .value("PseudoVNSRL_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4_MASK) + .value("PseudoVNSRL_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8) + .value("PseudoVNSRL_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8_MASK) + .value("PseudoVOR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1) + .value("PseudoVOR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1_MASK) + .value("PseudoVOR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2) + .value("PseudoVOR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2_MASK) + .value("PseudoVOR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4) + .value("PseudoVOR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4_MASK) + .value("PseudoVOR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8) + .value("PseudoVOR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8_MASK) + .value("PseudoVOR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2) + .value("PseudoVOR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2_MASK) + .value("PseudoVOR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4) + .value("PseudoVOR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4_MASK) + .value("PseudoVOR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8) + .value("PseudoVOR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8_MASK) + .value("PseudoVOR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1) + .value("PseudoVOR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1_MASK) + .value("PseudoVOR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2) + .value("PseudoVOR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2_MASK) + .value("PseudoVOR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4) + .value("PseudoVOR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4_MASK) + .value("PseudoVOR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8) + .value("PseudoVOR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8_MASK) + .value("PseudoVOR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2) + .value("PseudoVOR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2_MASK) + .value("PseudoVOR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4) + .value("PseudoVOR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4_MASK) + .value("PseudoVOR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8) + .value("PseudoVOR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8_MASK) + .value("PseudoVOR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1) + .value("PseudoVOR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1_MASK) + .value("PseudoVOR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2) + .value("PseudoVOR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2_MASK) + .value("PseudoVOR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4) + .value("PseudoVOR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4_MASK) + .value("PseudoVOR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8) + .value("PseudoVOR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8_MASK) + .value("PseudoVOR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2) + .value("PseudoVOR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2_MASK) + .value("PseudoVOR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4) + .value("PseudoVOR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4_MASK) + .value("PseudoVOR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8) + .value("PseudoVOR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8_MASK) + .value("PseudoVQDOTSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M1) + .value("PseudoVQDOTSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M1_MASK) + .value("PseudoVQDOTSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M2) + .value("PseudoVQDOTSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M2_MASK) + .value("PseudoVQDOTSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M4) + .value("PseudoVQDOTSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M4_MASK) + .value("PseudoVQDOTSU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M8) + .value("PseudoVQDOTSU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_M8_MASK) + .value("PseudoVQDOTSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_MF2) + .value("PseudoVQDOTSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VV_MF2_MASK) + .value("PseudoVQDOTSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M1) + .value("PseudoVQDOTSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M1_MASK) + .value("PseudoVQDOTSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M2) + .value("PseudoVQDOTSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M2_MASK) + .value("PseudoVQDOTSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M4) + .value("PseudoVQDOTSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M4_MASK) + .value("PseudoVQDOTSU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M8) + .value("PseudoVQDOTSU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_M8_MASK) + .value("PseudoVQDOTSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_MF2) + .value("PseudoVQDOTSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTSU_VX_MF2_MASK) + .value("PseudoVQDOTUS_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M1) + .value("PseudoVQDOTUS_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M1_MASK) + .value("PseudoVQDOTUS_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M2) + .value("PseudoVQDOTUS_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M2_MASK) + .value("PseudoVQDOTUS_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M4) + .value("PseudoVQDOTUS_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M4_MASK) + .value("PseudoVQDOTUS_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M8) + .value("PseudoVQDOTUS_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_M8_MASK) + .value("PseudoVQDOTUS_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_MF2) + .value("PseudoVQDOTUS_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTUS_VX_MF2_MASK) + .value("PseudoVQDOTU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M1) + .value("PseudoVQDOTU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M1_MASK) + .value("PseudoVQDOTU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M2) + .value("PseudoVQDOTU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M2_MASK) + .value("PseudoVQDOTU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M4) + .value("PseudoVQDOTU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M4_MASK) + .value("PseudoVQDOTU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M8) + .value("PseudoVQDOTU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_M8_MASK) + .value("PseudoVQDOTU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_MF2) + .value("PseudoVQDOTU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VV_MF2_MASK) + .value("PseudoVQDOTU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M1) + .value("PseudoVQDOTU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M1_MASK) + .value("PseudoVQDOTU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M2) + .value("PseudoVQDOTU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M2_MASK) + .value("PseudoVQDOTU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M4) + .value("PseudoVQDOTU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M4_MASK) + .value("PseudoVQDOTU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M8) + .value("PseudoVQDOTU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_M8_MASK) + .value("PseudoVQDOTU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_MF2) + .value("PseudoVQDOTU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOTU_VX_MF2_MASK) + .value("PseudoVQDOT_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M1) + .value("PseudoVQDOT_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M1_MASK) + .value("PseudoVQDOT_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M2) + .value("PseudoVQDOT_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M2_MASK) + .value("PseudoVQDOT_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M4) + .value("PseudoVQDOT_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M4_MASK) + .value("PseudoVQDOT_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M8) + .value("PseudoVQDOT_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_M8_MASK) + .value("PseudoVQDOT_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_MF2) + .value("PseudoVQDOT_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VV_MF2_MASK) + .value("PseudoVQDOT_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M1) + .value("PseudoVQDOT_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M1_MASK) + .value("PseudoVQDOT_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M2) + .value("PseudoVQDOT_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M2_MASK) + .value("PseudoVQDOT_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M4) + .value("PseudoVQDOT_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M4_MASK) + .value("PseudoVQDOT_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M8) + .value("PseudoVQDOT_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_M8_MASK) + .value("PseudoVQDOT_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_MF2) + .value("PseudoVQDOT_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVQDOT_VX_MF2_MASK) + .value("PseudoVREDAND_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16) + .value("PseudoVREDAND_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16_MASK) + .value("PseudoVREDAND_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32) + .value("PseudoVREDAND_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32_MASK) + .value("PseudoVREDAND_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64) + .value("PseudoVREDAND_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64_MASK) + .value("PseudoVREDAND_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8) + .value("PseudoVREDAND_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8_MASK) + .value("PseudoVREDAND_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16) + .value("PseudoVREDAND_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16_MASK) + .value("PseudoVREDAND_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32) + .value("PseudoVREDAND_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32_MASK) + .value("PseudoVREDAND_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64) + .value("PseudoVREDAND_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64_MASK) + .value("PseudoVREDAND_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8) + .value("PseudoVREDAND_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8_MASK) + .value("PseudoVREDAND_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16) + .value("PseudoVREDAND_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16_MASK) + .value("PseudoVREDAND_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32) + .value("PseudoVREDAND_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32_MASK) + .value("PseudoVREDAND_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64) + .value("PseudoVREDAND_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64_MASK) + .value("PseudoVREDAND_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8) + .value("PseudoVREDAND_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8_MASK) + .value("PseudoVREDAND_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16) + .value("PseudoVREDAND_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16_MASK) + .value("PseudoVREDAND_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32) + .value("PseudoVREDAND_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32_MASK) + .value("PseudoVREDAND_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64) + .value("PseudoVREDAND_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64_MASK) + .value("PseudoVREDAND_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8) + .value("PseudoVREDAND_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8_MASK) + .value("PseudoVREDAND_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16) + .value("PseudoVREDAND_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16_MASK) + .value("PseudoVREDAND_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32) + .value("PseudoVREDAND_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32_MASK) + .value("PseudoVREDAND_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8) + .value("PseudoVREDAND_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8_MASK) + .value("PseudoVREDAND_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16) + .value("PseudoVREDAND_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16_MASK) + .value("PseudoVREDAND_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8) + .value("PseudoVREDAND_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8_MASK) + .value("PseudoVREDAND_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8) + .value("PseudoVREDAND_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8_MASK) + .value("PseudoVREDMAXU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16) + .value("PseudoVREDMAXU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16_MASK) + .value("PseudoVREDMAXU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32) + .value("PseudoVREDMAXU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32_MASK) + .value("PseudoVREDMAXU_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64) + .value("PseudoVREDMAXU_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64_MASK) + .value("PseudoVREDMAXU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8) + .value("PseudoVREDMAXU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8_MASK) + .value("PseudoVREDMAXU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16) + .value("PseudoVREDMAXU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16_MASK) + .value("PseudoVREDMAXU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32) + .value("PseudoVREDMAXU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32_MASK) + .value("PseudoVREDMAXU_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64) + .value("PseudoVREDMAXU_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64_MASK) + .value("PseudoVREDMAXU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8) + .value("PseudoVREDMAXU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8_MASK) + .value("PseudoVREDMAXU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16) + .value("PseudoVREDMAXU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16_MASK) + .value("PseudoVREDMAXU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32) + .value("PseudoVREDMAXU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32_MASK) + .value("PseudoVREDMAXU_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64) + .value("PseudoVREDMAXU_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64_MASK) + .value("PseudoVREDMAXU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8) + .value("PseudoVREDMAXU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8_MASK) + .value("PseudoVREDMAXU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16) + .value("PseudoVREDMAXU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16_MASK) + .value("PseudoVREDMAXU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32) + .value("PseudoVREDMAXU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32_MASK) + .value("PseudoVREDMAXU_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64) + .value("PseudoVREDMAXU_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64_MASK) + .value("PseudoVREDMAXU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8) + .value("PseudoVREDMAXU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8_MASK) + .value("PseudoVREDMAXU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16) + .value("PseudoVREDMAXU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16_MASK) + .value("PseudoVREDMAXU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32) + .value("PseudoVREDMAXU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32_MASK) + .value("PseudoVREDMAXU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8) + .value("PseudoVREDMAXU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8_MASK) + .value("PseudoVREDMAXU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16) + .value("PseudoVREDMAXU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16_MASK) + .value("PseudoVREDMAXU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8) + .value("PseudoVREDMAXU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8_MASK) + .value("PseudoVREDMAXU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8) + .value("PseudoVREDMAXU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8_MASK) + .value("PseudoVREDMAX_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16) + .value("PseudoVREDMAX_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16_MASK) + .value("PseudoVREDMAX_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32) + .value("PseudoVREDMAX_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32_MASK) + .value("PseudoVREDMAX_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64) + .value("PseudoVREDMAX_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64_MASK) + .value("PseudoVREDMAX_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8) + .value("PseudoVREDMAX_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8_MASK) + .value("PseudoVREDMAX_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16) + .value("PseudoVREDMAX_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16_MASK) + .value("PseudoVREDMAX_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32) + .value("PseudoVREDMAX_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32_MASK) + .value("PseudoVREDMAX_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64) + .value("PseudoVREDMAX_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64_MASK) + .value("PseudoVREDMAX_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8) + .value("PseudoVREDMAX_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8_MASK) + .value("PseudoVREDMAX_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16) + .value("PseudoVREDMAX_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16_MASK) + .value("PseudoVREDMAX_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32) + .value("PseudoVREDMAX_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32_MASK) + .value("PseudoVREDMAX_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64) + .value("PseudoVREDMAX_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64_MASK) + .value("PseudoVREDMAX_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8) + .value("PseudoVREDMAX_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8_MASK) + .value("PseudoVREDMAX_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16) + .value("PseudoVREDMAX_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16_MASK) + .value("PseudoVREDMAX_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32) + .value("PseudoVREDMAX_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32_MASK) + .value("PseudoVREDMAX_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64) + .value("PseudoVREDMAX_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64_MASK) + .value("PseudoVREDMAX_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8) + .value("PseudoVREDMAX_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8_MASK) + .value("PseudoVREDMAX_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16) + .value("PseudoVREDMAX_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16_MASK) + .value("PseudoVREDMAX_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32) + .value("PseudoVREDMAX_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32_MASK) + .value("PseudoVREDMAX_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8) + .value("PseudoVREDMAX_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8_MASK) + .value("PseudoVREDMAX_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16) + .value("PseudoVREDMAX_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16_MASK) + .value("PseudoVREDMAX_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8) + .value("PseudoVREDMAX_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8_MASK) + .value("PseudoVREDMAX_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8) + .value("PseudoVREDMAX_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8_MASK) + .value("PseudoVREDMINU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16) + .value("PseudoVREDMINU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16_MASK) + .value("PseudoVREDMINU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32) + .value("PseudoVREDMINU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32_MASK) + .value("PseudoVREDMINU_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64) + .value("PseudoVREDMINU_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64_MASK) + .value("PseudoVREDMINU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8) + .value("PseudoVREDMINU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8_MASK) + .value("PseudoVREDMINU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16) + .value("PseudoVREDMINU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16_MASK) + .value("PseudoVREDMINU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32) + .value("PseudoVREDMINU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32_MASK) + .value("PseudoVREDMINU_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64) + .value("PseudoVREDMINU_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64_MASK) + .value("PseudoVREDMINU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8) + .value("PseudoVREDMINU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8_MASK) + .value("PseudoVREDMINU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16) + .value("PseudoVREDMINU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16_MASK) + .value("PseudoVREDMINU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32) + .value("PseudoVREDMINU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32_MASK) + .value("PseudoVREDMINU_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64) + .value("PseudoVREDMINU_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64_MASK) + .value("PseudoVREDMINU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8) + .value("PseudoVREDMINU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8_MASK) + .value("PseudoVREDMINU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16) + .value("PseudoVREDMINU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16_MASK) + .value("PseudoVREDMINU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32) + .value("PseudoVREDMINU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32_MASK) + .value("PseudoVREDMINU_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64) + .value("PseudoVREDMINU_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64_MASK) + .value("PseudoVREDMINU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8) + .value("PseudoVREDMINU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8_MASK) + .value("PseudoVREDMINU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16) + .value("PseudoVREDMINU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16_MASK) + .value("PseudoVREDMINU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32) + .value("PseudoVREDMINU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32_MASK) + .value("PseudoVREDMINU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8) + .value("PseudoVREDMINU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8_MASK) + .value("PseudoVREDMINU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16) + .value("PseudoVREDMINU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16_MASK) + .value("PseudoVREDMINU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8); + opcodes.value("PseudoVREDMINU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8_MASK) + .value("PseudoVREDMINU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8) + .value("PseudoVREDMINU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8_MASK) + .value("PseudoVREDMIN_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16) + .value("PseudoVREDMIN_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16_MASK) + .value("PseudoVREDMIN_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32) + .value("PseudoVREDMIN_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32_MASK) + .value("PseudoVREDMIN_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64) + .value("PseudoVREDMIN_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64_MASK) + .value("PseudoVREDMIN_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8) + .value("PseudoVREDMIN_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8_MASK) + .value("PseudoVREDMIN_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16) + .value("PseudoVREDMIN_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16_MASK) + .value("PseudoVREDMIN_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32) + .value("PseudoVREDMIN_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32_MASK) + .value("PseudoVREDMIN_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64) + .value("PseudoVREDMIN_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64_MASK) + .value("PseudoVREDMIN_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8) + .value("PseudoVREDMIN_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8_MASK) + .value("PseudoVREDMIN_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16) + .value("PseudoVREDMIN_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16_MASK) + .value("PseudoVREDMIN_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32) + .value("PseudoVREDMIN_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32_MASK) + .value("PseudoVREDMIN_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64) + .value("PseudoVREDMIN_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64_MASK) + .value("PseudoVREDMIN_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8) + .value("PseudoVREDMIN_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8_MASK) + .value("PseudoVREDMIN_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16) + .value("PseudoVREDMIN_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16_MASK) + .value("PseudoVREDMIN_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32) + .value("PseudoVREDMIN_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32_MASK) + .value("PseudoVREDMIN_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64) + .value("PseudoVREDMIN_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64_MASK) + .value("PseudoVREDMIN_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8) + .value("PseudoVREDMIN_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8_MASK) + .value("PseudoVREDMIN_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16) + .value("PseudoVREDMIN_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16_MASK) + .value("PseudoVREDMIN_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32) + .value("PseudoVREDMIN_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32_MASK) + .value("PseudoVREDMIN_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8) + .value("PseudoVREDMIN_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8_MASK) + .value("PseudoVREDMIN_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16) + .value("PseudoVREDMIN_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16_MASK) + .value("PseudoVREDMIN_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8) + .value("PseudoVREDMIN_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8_MASK) + .value("PseudoVREDMIN_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8) + .value("PseudoVREDMIN_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8_MASK) + .value("PseudoVREDOR_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16) + .value("PseudoVREDOR_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16_MASK) + .value("PseudoVREDOR_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32) + .value("PseudoVREDOR_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32_MASK) + .value("PseudoVREDOR_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64) + .value("PseudoVREDOR_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64_MASK) + .value("PseudoVREDOR_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8) + .value("PseudoVREDOR_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8_MASK) + .value("PseudoVREDOR_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16) + .value("PseudoVREDOR_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16_MASK) + .value("PseudoVREDOR_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32) + .value("PseudoVREDOR_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32_MASK) + .value("PseudoVREDOR_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64) + .value("PseudoVREDOR_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64_MASK) + .value("PseudoVREDOR_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8) + .value("PseudoVREDOR_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8_MASK) + .value("PseudoVREDOR_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16) + .value("PseudoVREDOR_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16_MASK) + .value("PseudoVREDOR_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32) + .value("PseudoVREDOR_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32_MASK) + .value("PseudoVREDOR_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64) + .value("PseudoVREDOR_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64_MASK) + .value("PseudoVREDOR_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8) + .value("PseudoVREDOR_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8_MASK) + .value("PseudoVREDOR_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16) + .value("PseudoVREDOR_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16_MASK) + .value("PseudoVREDOR_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32) + .value("PseudoVREDOR_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32_MASK) + .value("PseudoVREDOR_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64) + .value("PseudoVREDOR_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64_MASK) + .value("PseudoVREDOR_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8) + .value("PseudoVREDOR_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8_MASK) + .value("PseudoVREDOR_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16) + .value("PseudoVREDOR_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16_MASK) + .value("PseudoVREDOR_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32) + .value("PseudoVREDOR_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32_MASK) + .value("PseudoVREDOR_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8) + .value("PseudoVREDOR_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8_MASK) + .value("PseudoVREDOR_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16) + .value("PseudoVREDOR_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16_MASK) + .value("PseudoVREDOR_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8) + .value("PseudoVREDOR_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8_MASK) + .value("PseudoVREDOR_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8) + .value("PseudoVREDOR_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8_MASK) + .value("PseudoVREDSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16) + .value("PseudoVREDSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16_MASK) + .value("PseudoVREDSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32) + .value("PseudoVREDSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32_MASK) + .value("PseudoVREDSUM_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64) + .value("PseudoVREDSUM_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64_MASK) + .value("PseudoVREDSUM_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8) + .value("PseudoVREDSUM_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8_MASK) + .value("PseudoVREDSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16) + .value("PseudoVREDSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16_MASK) + .value("PseudoVREDSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32) + .value("PseudoVREDSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32_MASK) + .value("PseudoVREDSUM_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64) + .value("PseudoVREDSUM_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64_MASK) + .value("PseudoVREDSUM_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8) + .value("PseudoVREDSUM_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8_MASK) + .value("PseudoVREDSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16) + .value("PseudoVREDSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16_MASK) + .value("PseudoVREDSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32) + .value("PseudoVREDSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32_MASK) + .value("PseudoVREDSUM_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64) + .value("PseudoVREDSUM_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64_MASK) + .value("PseudoVREDSUM_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8) + .value("PseudoVREDSUM_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8_MASK) + .value("PseudoVREDSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16) + .value("PseudoVREDSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16_MASK) + .value("PseudoVREDSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32) + .value("PseudoVREDSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32_MASK) + .value("PseudoVREDSUM_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64) + .value("PseudoVREDSUM_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64_MASK) + .value("PseudoVREDSUM_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8) + .value("PseudoVREDSUM_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8_MASK) + .value("PseudoVREDSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16) + .value("PseudoVREDSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16_MASK) + .value("PseudoVREDSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32) + .value("PseudoVREDSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32_MASK) + .value("PseudoVREDSUM_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8) + .value("PseudoVREDSUM_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8_MASK) + .value("PseudoVREDSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16) + .value("PseudoVREDSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16_MASK) + .value("PseudoVREDSUM_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8) + .value("PseudoVREDSUM_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8_MASK) + .value("PseudoVREDSUM_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8) + .value("PseudoVREDSUM_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8_MASK) + .value("PseudoVREDXOR_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16) + .value("PseudoVREDXOR_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16_MASK) + .value("PseudoVREDXOR_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32) + .value("PseudoVREDXOR_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32_MASK) + .value("PseudoVREDXOR_VS_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64) + .value("PseudoVREDXOR_VS_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64_MASK) + .value("PseudoVREDXOR_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8) + .value("PseudoVREDXOR_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8_MASK) + .value("PseudoVREDXOR_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16) + .value("PseudoVREDXOR_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16_MASK) + .value("PseudoVREDXOR_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32) + .value("PseudoVREDXOR_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32_MASK) + .value("PseudoVREDXOR_VS_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64) + .value("PseudoVREDXOR_VS_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64_MASK) + .value("PseudoVREDXOR_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8) + .value("PseudoVREDXOR_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8_MASK) + .value("PseudoVREDXOR_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16) + .value("PseudoVREDXOR_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16_MASK) + .value("PseudoVREDXOR_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32) + .value("PseudoVREDXOR_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32_MASK) + .value("PseudoVREDXOR_VS_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64) + .value("PseudoVREDXOR_VS_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64_MASK) + .value("PseudoVREDXOR_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8) + .value("PseudoVREDXOR_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8_MASK) + .value("PseudoVREDXOR_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16) + .value("PseudoVREDXOR_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16_MASK) + .value("PseudoVREDXOR_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32) + .value("PseudoVREDXOR_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32_MASK) + .value("PseudoVREDXOR_VS_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64) + .value("PseudoVREDXOR_VS_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64_MASK) + .value("PseudoVREDXOR_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8) + .value("PseudoVREDXOR_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8_MASK) + .value("PseudoVREDXOR_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16) + .value("PseudoVREDXOR_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16_MASK) + .value("PseudoVREDXOR_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32) + .value("PseudoVREDXOR_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32_MASK) + .value("PseudoVREDXOR_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8) + .value("PseudoVREDXOR_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8_MASK) + .value("PseudoVREDXOR_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16) + .value("PseudoVREDXOR_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16_MASK) + .value("PseudoVREDXOR_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8) + .value("PseudoVREDXOR_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8_MASK) + .value("PseudoVREDXOR_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8) + .value("PseudoVREDXOR_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8_MASK) + .value("PseudoVRELOAD2_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M1) + .value("PseudoVRELOAD2_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M2) + .value("PseudoVRELOAD2_M4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M4) + .value("PseudoVRELOAD2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF2) + .value("PseudoVRELOAD2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF4) + .value("PseudoVRELOAD2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF8) + .value("PseudoVRELOAD3_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M1) + .value("PseudoVRELOAD3_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M2) + .value("PseudoVRELOAD3_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF2) + .value("PseudoVRELOAD3_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF4) + .value("PseudoVRELOAD3_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF8) + .value("PseudoVRELOAD4_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M1) + .value("PseudoVRELOAD4_M2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M2) + .value("PseudoVRELOAD4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF2) + .value("PseudoVRELOAD4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF4) + .value("PseudoVRELOAD4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF8) + .value("PseudoVRELOAD5_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_M1) + .value("PseudoVRELOAD5_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF2) + .value("PseudoVRELOAD5_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF4) + .value("PseudoVRELOAD5_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF8) + .value("PseudoVRELOAD6_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_M1) + .value("PseudoVRELOAD6_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF2) + .value("PseudoVRELOAD6_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF4) + .value("PseudoVRELOAD6_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF8) + .value("PseudoVRELOAD7_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_M1) + .value("PseudoVRELOAD7_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF2) + .value("PseudoVRELOAD7_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF4) + .value("PseudoVRELOAD7_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF8) + .value("PseudoVRELOAD8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_M1) + .value("PseudoVRELOAD8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF2) + .value("PseudoVRELOAD8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF4) + .value("PseudoVRELOAD8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF8) + .value("PseudoVREMU_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16) + .value("PseudoVREMU_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16_MASK) + .value("PseudoVREMU_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32) + .value("PseudoVREMU_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32_MASK) + .value("PseudoVREMU_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64) + .value("PseudoVREMU_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64_MASK) + .value("PseudoVREMU_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8) + .value("PseudoVREMU_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8_MASK) + .value("PseudoVREMU_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16) + .value("PseudoVREMU_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16_MASK) + .value("PseudoVREMU_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32) + .value("PseudoVREMU_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32_MASK) + .value("PseudoVREMU_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64) + .value("PseudoVREMU_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64_MASK) + .value("PseudoVREMU_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8) + .value("PseudoVREMU_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8_MASK) + .value("PseudoVREMU_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16) + .value("PseudoVREMU_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16_MASK) + .value("PseudoVREMU_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32) + .value("PseudoVREMU_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32_MASK) + .value("PseudoVREMU_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64) + .value("PseudoVREMU_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64_MASK) + .value("PseudoVREMU_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8) + .value("PseudoVREMU_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8_MASK) + .value("PseudoVREMU_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16) + .value("PseudoVREMU_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16_MASK) + .value("PseudoVREMU_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32) + .value("PseudoVREMU_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32_MASK) + .value("PseudoVREMU_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64) + .value("PseudoVREMU_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64_MASK) + .value("PseudoVREMU_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8) + .value("PseudoVREMU_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8_MASK) + .value("PseudoVREMU_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16) + .value("PseudoVREMU_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16_MASK) + .value("PseudoVREMU_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32) + .value("PseudoVREMU_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32_MASK) + .value("PseudoVREMU_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8) + .value("PseudoVREMU_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8_MASK) + .value("PseudoVREMU_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16) + .value("PseudoVREMU_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16_MASK) + .value("PseudoVREMU_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8) + .value("PseudoVREMU_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8_MASK) + .value("PseudoVREMU_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8) + .value("PseudoVREMU_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8_MASK) + .value("PseudoVREMU_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16) + .value("PseudoVREMU_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16_MASK) + .value("PseudoVREMU_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32) + .value("PseudoVREMU_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32_MASK) + .value("PseudoVREMU_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64) + .value("PseudoVREMU_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64_MASK) + .value("PseudoVREMU_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8) + .value("PseudoVREMU_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8_MASK) + .value("PseudoVREMU_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16) + .value("PseudoVREMU_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16_MASK) + .value("PseudoVREMU_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32) + .value("PseudoVREMU_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32_MASK) + .value("PseudoVREMU_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64) + .value("PseudoVREMU_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64_MASK) + .value("PseudoVREMU_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8) + .value("PseudoVREMU_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8_MASK) + .value("PseudoVREMU_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16) + .value("PseudoVREMU_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16_MASK) + .value("PseudoVREMU_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32) + .value("PseudoVREMU_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32_MASK) + .value("PseudoVREMU_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64) + .value("PseudoVREMU_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64_MASK) + .value("PseudoVREMU_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8) + .value("PseudoVREMU_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8_MASK) + .value("PseudoVREMU_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16) + .value("PseudoVREMU_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16_MASK) + .value("PseudoVREMU_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32) + .value("PseudoVREMU_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32_MASK) + .value("PseudoVREMU_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64) + .value("PseudoVREMU_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64_MASK) + .value("PseudoVREMU_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8) + .value("PseudoVREMU_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8_MASK) + .value("PseudoVREMU_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16) + .value("PseudoVREMU_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16_MASK) + .value("PseudoVREMU_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32) + .value("PseudoVREMU_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32_MASK) + .value("PseudoVREMU_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8) + .value("PseudoVREMU_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8_MASK) + .value("PseudoVREMU_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16) + .value("PseudoVREMU_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16_MASK) + .value("PseudoVREMU_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8) + .value("PseudoVREMU_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8_MASK) + .value("PseudoVREMU_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8) + .value("PseudoVREMU_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8_MASK) + .value("PseudoVREM_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16); + opcodes.value("PseudoVREM_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16_MASK) + .value("PseudoVREM_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32) + .value("PseudoVREM_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32_MASK) + .value("PseudoVREM_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64) + .value("PseudoVREM_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64_MASK) + .value("PseudoVREM_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8) + .value("PseudoVREM_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8_MASK) + .value("PseudoVREM_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16) + .value("PseudoVREM_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16_MASK) + .value("PseudoVREM_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32) + .value("PseudoVREM_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32_MASK) + .value("PseudoVREM_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64) + .value("PseudoVREM_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64_MASK) + .value("PseudoVREM_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8) + .value("PseudoVREM_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8_MASK) + .value("PseudoVREM_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16) + .value("PseudoVREM_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16_MASK) + .value("PseudoVREM_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32) + .value("PseudoVREM_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32_MASK) + .value("PseudoVREM_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64) + .value("PseudoVREM_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64_MASK) + .value("PseudoVREM_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8) + .value("PseudoVREM_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8_MASK) + .value("PseudoVREM_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16) + .value("PseudoVREM_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16_MASK) + .value("PseudoVREM_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32) + .value("PseudoVREM_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32_MASK) + .value("PseudoVREM_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64) + .value("PseudoVREM_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64_MASK) + .value("PseudoVREM_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8) + .value("PseudoVREM_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8_MASK) + .value("PseudoVREM_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16) + .value("PseudoVREM_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16_MASK) + .value("PseudoVREM_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32) + .value("PseudoVREM_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32_MASK) + .value("PseudoVREM_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8) + .value("PseudoVREM_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8_MASK) + .value("PseudoVREM_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16) + .value("PseudoVREM_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16_MASK) + .value("PseudoVREM_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8) + .value("PseudoVREM_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8_MASK) + .value("PseudoVREM_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8) + .value("PseudoVREM_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8_MASK) + .value("PseudoVREM_VX_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16) + .value("PseudoVREM_VX_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16_MASK) + .value("PseudoVREM_VX_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32) + .value("PseudoVREM_VX_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32_MASK) + .value("PseudoVREM_VX_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64) + .value("PseudoVREM_VX_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64_MASK) + .value("PseudoVREM_VX_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8) + .value("PseudoVREM_VX_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8_MASK) + .value("PseudoVREM_VX_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16) + .value("PseudoVREM_VX_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16_MASK) + .value("PseudoVREM_VX_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32) + .value("PseudoVREM_VX_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32_MASK) + .value("PseudoVREM_VX_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64) + .value("PseudoVREM_VX_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64_MASK) + .value("PseudoVREM_VX_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8) + .value("PseudoVREM_VX_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8_MASK) + .value("PseudoVREM_VX_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16) + .value("PseudoVREM_VX_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16_MASK) + .value("PseudoVREM_VX_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32) + .value("PseudoVREM_VX_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32_MASK) + .value("PseudoVREM_VX_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64) + .value("PseudoVREM_VX_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64_MASK) + .value("PseudoVREM_VX_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8) + .value("PseudoVREM_VX_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8_MASK) + .value("PseudoVREM_VX_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16) + .value("PseudoVREM_VX_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16_MASK) + .value("PseudoVREM_VX_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32) + .value("PseudoVREM_VX_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32_MASK) + .value("PseudoVREM_VX_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64) + .value("PseudoVREM_VX_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64_MASK) + .value("PseudoVREM_VX_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8) + .value("PseudoVREM_VX_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8_MASK) + .value("PseudoVREM_VX_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16) + .value("PseudoVREM_VX_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16_MASK) + .value("PseudoVREM_VX_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32) + .value("PseudoVREM_VX_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32_MASK) + .value("PseudoVREM_VX_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8) + .value("PseudoVREM_VX_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8_MASK) + .value("PseudoVREM_VX_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16) + .value("PseudoVREM_VX_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16_MASK) + .value("PseudoVREM_VX_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8) + .value("PseudoVREM_VX_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8_MASK) + .value("PseudoVREM_VX_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8) + .value("PseudoVREM_VX_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8_MASK) + .value("PseudoVREV8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1) + .value("PseudoVREV8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1_MASK) + .value("PseudoVREV8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2) + .value("PseudoVREV8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2_MASK) + .value("PseudoVREV8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4) + .value("PseudoVREV8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4_MASK) + .value("PseudoVREV8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8) + .value("PseudoVREV8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8_MASK) + .value("PseudoVREV8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2) + .value("PseudoVREV8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2_MASK) + .value("PseudoVREV8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4) + .value("PseudoVREV8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4_MASK) + .value("PseudoVREV8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8) + .value("PseudoVREV8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1) + .value("PseudoVRGATHEREI16_VV_M1_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2) + .value("PseudoVRGATHEREI16_VV_M1_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2) + .value("PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4) + .value("PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1) + .value("PseudoVRGATHEREI16_VV_M1_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2) + .value("PseudoVRGATHEREI16_VV_M1_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2) + .value("PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E32_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4) + .value("PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1) + .value("PseudoVRGATHEREI16_VV_M1_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2) + .value("PseudoVRGATHEREI16_VV_M1_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E64_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2) + .value("PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E64_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4) + .value("PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1) + .value("PseudoVRGATHEREI16_VV_M1_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2) + .value("PseudoVRGATHEREI16_VV_M1_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2) + .value("PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M1_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4) + .value("PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1) + .value("PseudoVRGATHEREI16_VV_M2_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2) + .value("PseudoVRGATHEREI16_VV_M2_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4) + .value("PseudoVRGATHEREI16_VV_M2_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2) + .value("PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1) + .value("PseudoVRGATHEREI16_VV_M2_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2) + .value("PseudoVRGATHEREI16_VV_M2_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4) + .value("PseudoVRGATHEREI16_VV_M2_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2) + .value("PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1) + .value("PseudoVRGATHEREI16_VV_M2_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2) + .value("PseudoVRGATHEREI16_VV_M2_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4) + .value("PseudoVRGATHEREI16_VV_M2_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E64_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2) + .value("PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1) + .value("PseudoVRGATHEREI16_VV_M2_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2) + .value("PseudoVRGATHEREI16_VV_M2_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4) + .value("PseudoVRGATHEREI16_VV_M2_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M2_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2) + .value("PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1) + .value("PseudoVRGATHEREI16_VV_M4_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2) + .value("PseudoVRGATHEREI16_VV_M4_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4) + .value("PseudoVRGATHEREI16_VV_M4_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E16_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8) + .value("PseudoVRGATHEREI16_VV_M4_E16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1) + .value("PseudoVRGATHEREI16_VV_M4_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2) + .value("PseudoVRGATHEREI16_VV_M4_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4) + .value("PseudoVRGATHEREI16_VV_M4_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E32_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8) + .value("PseudoVRGATHEREI16_VV_M4_E32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E64_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1) + .value("PseudoVRGATHEREI16_VV_M4_E64_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2) + .value("PseudoVRGATHEREI16_VV_M4_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4) + .value("PseudoVRGATHEREI16_VV_M4_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E64_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8) + .value("PseudoVRGATHEREI16_VV_M4_E64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1) + .value("PseudoVRGATHEREI16_VV_M4_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2) + .value("PseudoVRGATHEREI16_VV_M4_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4) + .value("PseudoVRGATHEREI16_VV_M4_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M4_E8_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8) + .value("PseudoVRGATHEREI16_VV_M4_E8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E16_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2) + .value("PseudoVRGATHEREI16_VV_M8_E16_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E16_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4) + .value("PseudoVRGATHEREI16_VV_M8_E16_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E16_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8) + .value("PseudoVRGATHEREI16_VV_M8_E16_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E32_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2) + .value("PseudoVRGATHEREI16_VV_M8_E32_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E32_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4) + .value("PseudoVRGATHEREI16_VV_M8_E32_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E32_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8) + .value("PseudoVRGATHEREI16_VV_M8_E32_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E64_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2) + .value("PseudoVRGATHEREI16_VV_M8_E64_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E64_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4) + .value("PseudoVRGATHEREI16_VV_M8_E64_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E64_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8) + .value("PseudoVRGATHEREI16_VV_M8_E64_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E8_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2) + .value("PseudoVRGATHEREI16_VV_M8_E8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E8_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4) + .value("PseudoVRGATHEREI16_VV_M8_E8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK) + .value("PseudoVRGATHEREI16_VV_M8_E8_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8) + .value("PseudoVRGATHEREI16_VV_M8_E8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E16_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1) + .value("PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8) + .value("PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E32_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1) + .value("PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8) + .value("PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E8_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1) + .value("PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8) + .value("PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8) + .value("PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8) + .value("PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK) + .value("PseudoVRGATHEREI16_VV_MF8_E8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4) + .value("PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK) + .value("PseudoVRGATHEREI16_VV_MF8_E8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8) + .value("PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK) + .value("PseudoVRGATHER_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1) + .value("PseudoVRGATHER_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1_MASK) + .value("PseudoVRGATHER_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2) + .value("PseudoVRGATHER_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2_MASK) + .value("PseudoVRGATHER_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4) + .value("PseudoVRGATHER_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4_MASK) + .value("PseudoVRGATHER_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8) + .value("PseudoVRGATHER_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8_MASK) + .value("PseudoVRGATHER_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2) + .value("PseudoVRGATHER_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2_MASK) + .value("PseudoVRGATHER_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4) + .value("PseudoVRGATHER_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4_MASK) + .value("PseudoVRGATHER_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8) + .value("PseudoVRGATHER_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8_MASK) + .value("PseudoVRGATHER_VV_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16) + .value("PseudoVRGATHER_VV_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16_MASK) + .value("PseudoVRGATHER_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32) + .value("PseudoVRGATHER_VV_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32_MASK) + .value("PseudoVRGATHER_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64) + .value("PseudoVRGATHER_VV_M1_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64_MASK) + .value("PseudoVRGATHER_VV_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8) + .value("PseudoVRGATHER_VV_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8_MASK) + .value("PseudoVRGATHER_VV_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16) + .value("PseudoVRGATHER_VV_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16_MASK) + .value("PseudoVRGATHER_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32) + .value("PseudoVRGATHER_VV_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32_MASK) + .value("PseudoVRGATHER_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64) + .value("PseudoVRGATHER_VV_M2_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64_MASK) + .value("PseudoVRGATHER_VV_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8) + .value("PseudoVRGATHER_VV_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8_MASK) + .value("PseudoVRGATHER_VV_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16) + .value("PseudoVRGATHER_VV_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16_MASK) + .value("PseudoVRGATHER_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32) + .value("PseudoVRGATHER_VV_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32_MASK) + .value("PseudoVRGATHER_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64) + .value("PseudoVRGATHER_VV_M4_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64_MASK) + .value("PseudoVRGATHER_VV_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8) + .value("PseudoVRGATHER_VV_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8_MASK) + .value("PseudoVRGATHER_VV_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16); + opcodes.value("PseudoVRGATHER_VV_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16_MASK) + .value("PseudoVRGATHER_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32) + .value("PseudoVRGATHER_VV_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32_MASK) + .value("PseudoVRGATHER_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64) + .value("PseudoVRGATHER_VV_M8_E64_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64_MASK) + .value("PseudoVRGATHER_VV_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8) + .value("PseudoVRGATHER_VV_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8_MASK) + .value("PseudoVRGATHER_VV_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16) + .value("PseudoVRGATHER_VV_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16_MASK) + .value("PseudoVRGATHER_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32) + .value("PseudoVRGATHER_VV_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32_MASK) + .value("PseudoVRGATHER_VV_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8) + .value("PseudoVRGATHER_VV_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8_MASK) + .value("PseudoVRGATHER_VV_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16) + .value("PseudoVRGATHER_VV_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16_MASK) + .value("PseudoVRGATHER_VV_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8) + .value("PseudoVRGATHER_VV_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8_MASK) + .value("PseudoVRGATHER_VV_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8) + .value("PseudoVRGATHER_VV_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8_MASK) + .value("PseudoVRGATHER_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1) + .value("PseudoVRGATHER_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1_MASK) + .value("PseudoVRGATHER_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2) + .value("PseudoVRGATHER_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2_MASK) + .value("PseudoVRGATHER_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4) + .value("PseudoVRGATHER_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4_MASK) + .value("PseudoVRGATHER_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8) + .value("PseudoVRGATHER_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8_MASK) + .value("PseudoVRGATHER_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2) + .value("PseudoVRGATHER_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2_MASK) + .value("PseudoVRGATHER_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4) + .value("PseudoVRGATHER_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4_MASK) + .value("PseudoVRGATHER_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8) + .value("PseudoVRGATHER_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8_MASK) + .value("PseudoVROL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1) + .value("PseudoVROL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1_MASK) + .value("PseudoVROL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2) + .value("PseudoVROL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2_MASK) + .value("PseudoVROL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4) + .value("PseudoVROL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4_MASK) + .value("PseudoVROL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8) + .value("PseudoVROL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8_MASK) + .value("PseudoVROL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2) + .value("PseudoVROL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2_MASK) + .value("PseudoVROL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4) + .value("PseudoVROL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4_MASK) + .value("PseudoVROL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8) + .value("PseudoVROL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8_MASK) + .value("PseudoVROL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1) + .value("PseudoVROL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1_MASK) + .value("PseudoVROL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2) + .value("PseudoVROL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2_MASK) + .value("PseudoVROL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4) + .value("PseudoVROL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4_MASK) + .value("PseudoVROL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8) + .value("PseudoVROL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8_MASK) + .value("PseudoVROL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2) + .value("PseudoVROL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2_MASK) + .value("PseudoVROL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4) + .value("PseudoVROL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4_MASK) + .value("PseudoVROL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8) + .value("PseudoVROL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8_MASK) + .value("PseudoVROR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1) + .value("PseudoVROR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1_MASK) + .value("PseudoVROR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2) + .value("PseudoVROR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2_MASK) + .value("PseudoVROR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4) + .value("PseudoVROR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4_MASK) + .value("PseudoVROR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8) + .value("PseudoVROR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8_MASK) + .value("PseudoVROR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2) + .value("PseudoVROR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2_MASK) + .value("PseudoVROR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4) + .value("PseudoVROR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4_MASK) + .value("PseudoVROR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8) + .value("PseudoVROR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8_MASK) + .value("PseudoVROR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1) + .value("PseudoVROR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1_MASK) + .value("PseudoVROR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2) + .value("PseudoVROR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2_MASK) + .value("PseudoVROR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4) + .value("PseudoVROR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4_MASK) + .value("PseudoVROR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8) + .value("PseudoVROR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8_MASK) + .value("PseudoVROR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2) + .value("PseudoVROR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2_MASK) + .value("PseudoVROR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4) + .value("PseudoVROR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4_MASK) + .value("PseudoVROR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8) + .value("PseudoVROR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8_MASK) + .value("PseudoVROR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1) + .value("PseudoVROR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1_MASK) + .value("PseudoVROR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2) + .value("PseudoVROR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2_MASK) + .value("PseudoVROR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4) + .value("PseudoVROR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4_MASK) + .value("PseudoVROR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8) + .value("PseudoVROR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8_MASK) + .value("PseudoVROR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2) + .value("PseudoVROR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2_MASK) + .value("PseudoVROR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4) + .value("PseudoVROR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4_MASK) + .value("PseudoVROR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8) + .value("PseudoVROR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8_MASK) + .value("PseudoVRSUB_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1) + .value("PseudoVRSUB_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1_MASK) + .value("PseudoVRSUB_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2) + .value("PseudoVRSUB_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2_MASK) + .value("PseudoVRSUB_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4) + .value("PseudoVRSUB_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4_MASK) + .value("PseudoVRSUB_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8) + .value("PseudoVRSUB_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8_MASK) + .value("PseudoVRSUB_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2) + .value("PseudoVRSUB_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2_MASK) + .value("PseudoVRSUB_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4) + .value("PseudoVRSUB_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4_MASK) + .value("PseudoVRSUB_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8) + .value("PseudoVRSUB_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8_MASK) + .value("PseudoVRSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1) + .value("PseudoVRSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1_MASK) + .value("PseudoVRSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2) + .value("PseudoVRSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2_MASK) + .value("PseudoVRSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4) + .value("PseudoVRSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4_MASK) + .value("PseudoVRSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8) + .value("PseudoVRSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8_MASK) + .value("PseudoVRSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2) + .value("PseudoVRSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2_MASK) + .value("PseudoVRSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4) + .value("PseudoVRSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4_MASK) + .value("PseudoVRSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8) + .value("PseudoVRSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8_MASK) + .value("PseudoVSADDU_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1) + .value("PseudoVSADDU_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1_MASK) + .value("PseudoVSADDU_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2) + .value("PseudoVSADDU_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2_MASK) + .value("PseudoVSADDU_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4) + .value("PseudoVSADDU_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4_MASK) + .value("PseudoVSADDU_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8) + .value("PseudoVSADDU_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8_MASK) + .value("PseudoVSADDU_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2) + .value("PseudoVSADDU_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2_MASK) + .value("PseudoVSADDU_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4) + .value("PseudoVSADDU_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4_MASK) + .value("PseudoVSADDU_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8) + .value("PseudoVSADDU_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8_MASK) + .value("PseudoVSADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1) + .value("PseudoVSADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1_MASK) + .value("PseudoVSADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2) + .value("PseudoVSADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2_MASK) + .value("PseudoVSADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4) + .value("PseudoVSADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4_MASK) + .value("PseudoVSADDU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8) + .value("PseudoVSADDU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8_MASK) + .value("PseudoVSADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2) + .value("PseudoVSADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2_MASK) + .value("PseudoVSADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4) + .value("PseudoVSADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4_MASK) + .value("PseudoVSADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8) + .value("PseudoVSADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8_MASK) + .value("PseudoVSADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1) + .value("PseudoVSADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1_MASK) + .value("PseudoVSADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2) + .value("PseudoVSADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2_MASK) + .value("PseudoVSADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4) + .value("PseudoVSADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4_MASK) + .value("PseudoVSADDU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8) + .value("PseudoVSADDU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8_MASK) + .value("PseudoVSADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2) + .value("PseudoVSADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2_MASK) + .value("PseudoVSADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4) + .value("PseudoVSADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4_MASK) + .value("PseudoVSADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8) + .value("PseudoVSADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8_MASK) + .value("PseudoVSADD_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1) + .value("PseudoVSADD_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1_MASK) + .value("PseudoVSADD_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2) + .value("PseudoVSADD_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2_MASK) + .value("PseudoVSADD_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4) + .value("PseudoVSADD_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4_MASK) + .value("PseudoVSADD_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8) + .value("PseudoVSADD_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8_MASK) + .value("PseudoVSADD_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2) + .value("PseudoVSADD_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2_MASK) + .value("PseudoVSADD_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4) + .value("PseudoVSADD_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4_MASK) + .value("PseudoVSADD_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8) + .value("PseudoVSADD_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8_MASK) + .value("PseudoVSADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1) + .value("PseudoVSADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1_MASK) + .value("PseudoVSADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2) + .value("PseudoVSADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2_MASK) + .value("PseudoVSADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4) + .value("PseudoVSADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4_MASK) + .value("PseudoVSADD_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8) + .value("PseudoVSADD_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8_MASK) + .value("PseudoVSADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2) + .value("PseudoVSADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2_MASK) + .value("PseudoVSADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4) + .value("PseudoVSADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4_MASK) + .value("PseudoVSADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8) + .value("PseudoVSADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8_MASK) + .value("PseudoVSADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1) + .value("PseudoVSADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1_MASK) + .value("PseudoVSADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2) + .value("PseudoVSADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2_MASK) + .value("PseudoVSADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4) + .value("PseudoVSADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4_MASK) + .value("PseudoVSADD_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8) + .value("PseudoVSADD_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8_MASK) + .value("PseudoVSADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2) + .value("PseudoVSADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2_MASK) + .value("PseudoVSADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4) + .value("PseudoVSADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4_MASK) + .value("PseudoVSADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8) + .value("PseudoVSADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8_MASK) + .value("PseudoVSBC_VVM_M1", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M1) + .value("PseudoVSBC_VVM_M2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M2) + .value("PseudoVSBC_VVM_M4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M4) + .value("PseudoVSBC_VVM_M8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M8) + .value("PseudoVSBC_VVM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF2) + .value("PseudoVSBC_VVM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF4) + .value("PseudoVSBC_VVM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF8) + .value("PseudoVSBC_VXM_M1", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M1) + .value("PseudoVSBC_VXM_M2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M2) + .value("PseudoVSBC_VXM_M4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M4) + .value("PseudoVSBC_VXM_M8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M8) + .value("PseudoVSBC_VXM_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF2) + .value("PseudoVSBC_VXM_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF4) + .value("PseudoVSBC_VXM_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF8) + .value("PseudoVSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1) + .value("PseudoVSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1_MASK) + .value("PseudoVSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2) + .value("PseudoVSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2_MASK) + .value("PseudoVSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4) + .value("PseudoVSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4_MASK) + .value("PseudoVSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8) + .value("PseudoVSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8_MASK) + .value("PseudoVSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2) + .value("PseudoVSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2_MASK) + .value("PseudoVSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4) + .value("PseudoVSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4_MASK) + .value("PseudoVSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1) + .value("PseudoVSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1_MASK) + .value("PseudoVSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2) + .value("PseudoVSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2_MASK) + .value("PseudoVSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4) + .value("PseudoVSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4_MASK) + .value("PseudoVSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8) + .value("PseudoVSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8_MASK) + .value("PseudoVSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2) + .value("PseudoVSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2_MASK) + .value("PseudoVSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1) + .value("PseudoVSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1_MASK) + .value("PseudoVSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2) + .value("PseudoVSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2_MASK) + .value("PseudoVSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4) + .value("PseudoVSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4_MASK) + .value("PseudoVSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8) + .value("PseudoVSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8_MASK) + .value("PseudoVSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1) + .value("PseudoVSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1_MASK) + .value("PseudoVSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2) + .value("PseudoVSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2_MASK) + .value("PseudoVSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4) + .value("PseudoVSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4_MASK) + .value("PseudoVSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8) + .value("PseudoVSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8_MASK) + .value("PseudoVSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2) + .value("PseudoVSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2_MASK) + .value("PseudoVSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4) + .value("PseudoVSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4_MASK) + .value("PseudoVSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8) + .value("PseudoVSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8_MASK) + .value("PseudoVSETIVLI", LIEF::assembly::riscv::OPCODE::PseudoVSETIVLI) + .value("PseudoVSETVLI", LIEF::assembly::riscv::OPCODE::PseudoVSETVLI) + .value("PseudoVSETVLIX0", LIEF::assembly::riscv::OPCODE::PseudoVSETVLIX0) + .value("PseudoVSETVLIX0X0", LIEF::assembly::riscv::OPCODE::PseudoVSETVLIX0X0) + .value("PseudoVSEXT_VF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1) + .value("PseudoVSEXT_VF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1_MASK) + .value("PseudoVSEXT_VF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2) + .value("PseudoVSEXT_VF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2_MASK) + .value("PseudoVSEXT_VF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4) + .value("PseudoVSEXT_VF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4_MASK) + .value("PseudoVSEXT_VF2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8) + .value("PseudoVSEXT_VF2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8_MASK) + .value("PseudoVSEXT_VF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2) + .value("PseudoVSEXT_VF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2_MASK) + .value("PseudoVSEXT_VF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4) + .value("PseudoVSEXT_VF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4_MASK) + .value("PseudoVSEXT_VF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1) + .value("PseudoVSEXT_VF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1_MASK) + .value("PseudoVSEXT_VF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2) + .value("PseudoVSEXT_VF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2_MASK) + .value("PseudoVSEXT_VF4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4) + .value("PseudoVSEXT_VF4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4_MASK) + .value("PseudoVSEXT_VF4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8) + .value("PseudoVSEXT_VF4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8_MASK) + .value("PseudoVSEXT_VF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2) + .value("PseudoVSEXT_VF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2_MASK) + .value("PseudoVSEXT_VF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1); + opcodes.value("PseudoVSEXT_VF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1_MASK) + .value("PseudoVSEXT_VF8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2) + .value("PseudoVSEXT_VF8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2_MASK) + .value("PseudoVSEXT_VF8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4) + .value("PseudoVSEXT_VF8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4_MASK) + .value("PseudoVSEXT_VF8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8) + .value("PseudoVSEXT_VF8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8_MASK) + .value("PseudoVSHA2CH_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M1) + .value("PseudoVSHA2CH_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M2) + .value("PseudoVSHA2CH_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M4) + .value("PseudoVSHA2CH_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M8) + .value("PseudoVSHA2CH_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_MF2) + .value("PseudoVSHA2CL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M1) + .value("PseudoVSHA2CL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M2) + .value("PseudoVSHA2CL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M4) + .value("PseudoVSHA2CL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M8) + .value("PseudoVSHA2CL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_MF2) + .value("PseudoVSHA2MS_VV_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M1_E32) + .value("PseudoVSHA2MS_VV_M1_E64", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M1_E64) + .value("PseudoVSHA2MS_VV_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M2_E32) + .value("PseudoVSHA2MS_VV_M2_E64", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M2_E64) + .value("PseudoVSHA2MS_VV_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M4_E32) + .value("PseudoVSHA2MS_VV_M4_E64", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M4_E64) + .value("PseudoVSHA2MS_VV_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M8_E32) + .value("PseudoVSHA2MS_VV_M8_E64", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M8_E64) + .value("PseudoVSHA2MS_VV_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_MF2_E32) + .value("PseudoVSLIDE1DOWN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1) + .value("PseudoVSLIDE1DOWN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1_MASK) + .value("PseudoVSLIDE1DOWN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2) + .value("PseudoVSLIDE1DOWN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2_MASK) + .value("PseudoVSLIDE1DOWN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4) + .value("PseudoVSLIDE1DOWN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4_MASK) + .value("PseudoVSLIDE1DOWN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8) + .value("PseudoVSLIDE1DOWN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8_MASK) + .value("PseudoVSLIDE1DOWN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2) + .value("PseudoVSLIDE1DOWN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2_MASK) + .value("PseudoVSLIDE1DOWN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4) + .value("PseudoVSLIDE1DOWN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4_MASK) + .value("PseudoVSLIDE1DOWN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8) + .value("PseudoVSLIDE1DOWN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8_MASK) + .value("PseudoVSLIDE1UP_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1) + .value("PseudoVSLIDE1UP_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1_MASK) + .value("PseudoVSLIDE1UP_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2) + .value("PseudoVSLIDE1UP_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2_MASK) + .value("PseudoVSLIDE1UP_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4) + .value("PseudoVSLIDE1UP_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4_MASK) + .value("PseudoVSLIDE1UP_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8) + .value("PseudoVSLIDE1UP_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8_MASK) + .value("PseudoVSLIDE1UP_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2) + .value("PseudoVSLIDE1UP_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2_MASK) + .value("PseudoVSLIDE1UP_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4) + .value("PseudoVSLIDE1UP_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4_MASK) + .value("PseudoVSLIDE1UP_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8) + .value("PseudoVSLIDE1UP_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8_MASK) + .value("PseudoVSLIDEDOWN_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1) + .value("PseudoVSLIDEDOWN_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1_MASK) + .value("PseudoVSLIDEDOWN_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2) + .value("PseudoVSLIDEDOWN_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2_MASK) + .value("PseudoVSLIDEDOWN_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4) + .value("PseudoVSLIDEDOWN_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4_MASK) + .value("PseudoVSLIDEDOWN_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8) + .value("PseudoVSLIDEDOWN_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8_MASK) + .value("PseudoVSLIDEDOWN_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2) + .value("PseudoVSLIDEDOWN_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2_MASK) + .value("PseudoVSLIDEDOWN_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4) + .value("PseudoVSLIDEDOWN_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4_MASK) + .value("PseudoVSLIDEDOWN_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8) + .value("PseudoVSLIDEDOWN_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8_MASK) + .value("PseudoVSLIDEDOWN_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1) + .value("PseudoVSLIDEDOWN_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1_MASK) + .value("PseudoVSLIDEDOWN_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2) + .value("PseudoVSLIDEDOWN_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2_MASK) + .value("PseudoVSLIDEDOWN_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4) + .value("PseudoVSLIDEDOWN_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4_MASK) + .value("PseudoVSLIDEDOWN_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8) + .value("PseudoVSLIDEDOWN_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8_MASK) + .value("PseudoVSLIDEDOWN_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2) + .value("PseudoVSLIDEDOWN_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2_MASK) + .value("PseudoVSLIDEDOWN_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4) + .value("PseudoVSLIDEDOWN_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4_MASK) + .value("PseudoVSLIDEDOWN_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8) + .value("PseudoVSLIDEDOWN_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8_MASK) + .value("PseudoVSLIDEUP_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1) + .value("PseudoVSLIDEUP_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1_MASK) + .value("PseudoVSLIDEUP_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2) + .value("PseudoVSLIDEUP_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2_MASK) + .value("PseudoVSLIDEUP_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4) + .value("PseudoVSLIDEUP_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4_MASK) + .value("PseudoVSLIDEUP_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8) + .value("PseudoVSLIDEUP_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8_MASK) + .value("PseudoVSLIDEUP_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2) + .value("PseudoVSLIDEUP_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2_MASK) + .value("PseudoVSLIDEUP_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4) + .value("PseudoVSLIDEUP_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4_MASK) + .value("PseudoVSLIDEUP_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8) + .value("PseudoVSLIDEUP_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8_MASK) + .value("PseudoVSLIDEUP_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1) + .value("PseudoVSLIDEUP_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1_MASK) + .value("PseudoVSLIDEUP_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2) + .value("PseudoVSLIDEUP_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2_MASK) + .value("PseudoVSLIDEUP_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4) + .value("PseudoVSLIDEUP_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4_MASK) + .value("PseudoVSLIDEUP_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8) + .value("PseudoVSLIDEUP_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8_MASK) + .value("PseudoVSLIDEUP_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2) + .value("PseudoVSLIDEUP_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2_MASK) + .value("PseudoVSLIDEUP_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4) + .value("PseudoVSLIDEUP_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4_MASK) + .value("PseudoVSLIDEUP_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8) + .value("PseudoVSLIDEUP_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8_MASK) + .value("PseudoVSLL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1) + .value("PseudoVSLL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1_MASK) + .value("PseudoVSLL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2) + .value("PseudoVSLL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2_MASK) + .value("PseudoVSLL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4) + .value("PseudoVSLL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4_MASK) + .value("PseudoVSLL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8) + .value("PseudoVSLL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8_MASK) + .value("PseudoVSLL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2) + .value("PseudoVSLL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2_MASK) + .value("PseudoVSLL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4) + .value("PseudoVSLL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4_MASK) + .value("PseudoVSLL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8) + .value("PseudoVSLL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8_MASK) + .value("PseudoVSLL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1) + .value("PseudoVSLL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1_MASK) + .value("PseudoVSLL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2) + .value("PseudoVSLL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2_MASK) + .value("PseudoVSLL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4) + .value("PseudoVSLL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4_MASK) + .value("PseudoVSLL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8) + .value("PseudoVSLL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8_MASK) + .value("PseudoVSLL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2) + .value("PseudoVSLL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2_MASK) + .value("PseudoVSLL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4) + .value("PseudoVSLL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4_MASK) + .value("PseudoVSLL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8) + .value("PseudoVSLL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8_MASK) + .value("PseudoVSLL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1) + .value("PseudoVSLL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1_MASK) + .value("PseudoVSLL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2) + .value("PseudoVSLL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2_MASK) + .value("PseudoVSLL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4) + .value("PseudoVSLL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4_MASK) + .value("PseudoVSLL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8) + .value("PseudoVSLL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8_MASK) + .value("PseudoVSLL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2) + .value("PseudoVSLL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2_MASK) + .value("PseudoVSLL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4) + .value("PseudoVSLL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4_MASK) + .value("PseudoVSLL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8) + .value("PseudoVSLL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8_MASK) + .value("PseudoVSM3C_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M1) + .value("PseudoVSM3C_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M2) + .value("PseudoVSM3C_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M4) + .value("PseudoVSM3C_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M8) + .value("PseudoVSM3C_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_MF2) + .value("PseudoVSM3ME_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M1) + .value("PseudoVSM3ME_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M2) + .value("PseudoVSM3ME_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M4) + .value("PseudoVSM3ME_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M8) + .value("PseudoVSM3ME_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_MF2) + .value("PseudoVSM4K_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M1) + .value("PseudoVSM4K_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M2) + .value("PseudoVSM4K_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M4) + .value("PseudoVSM4K_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M8) + .value("PseudoVSM4K_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_MF2) + .value("PseudoVSM4R_VS_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_M1) + .value("PseudoVSM4R_VS_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF2) + .value("PseudoVSM4R_VS_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF4) + .value("PseudoVSM4R_VS_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF8) + .value("PseudoVSM4R_VS_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M1) + .value("PseudoVSM4R_VS_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M2) + .value("PseudoVSM4R_VS_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF2) + .value("PseudoVSM4R_VS_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF4) + .value("PseudoVSM4R_VS_M2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF8) + .value("PseudoVSM4R_VS_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M1) + .value("PseudoVSM4R_VS_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M2) + .value("PseudoVSM4R_VS_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M4) + .value("PseudoVSM4R_VS_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF2) + .value("PseudoVSM4R_VS_M4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF4) + .value("PseudoVSM4R_VS_M4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF8) + .value("PseudoVSM4R_VS_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M1) + .value("PseudoVSM4R_VS_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M2) + .value("PseudoVSM4R_VS_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M4) + .value("PseudoVSM4R_VS_M8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF2) + .value("PseudoVSM4R_VS_M8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF4) + .value("PseudoVSM4R_VS_M8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF8) + .value("PseudoVSM4R_VS_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF2) + .value("PseudoVSM4R_VS_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF4) + .value("PseudoVSM4R_VS_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF8) + .value("PseudoVSM4R_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M1) + .value("PseudoVSM4R_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M2) + .value("PseudoVSM4R_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M4) + .value("PseudoVSM4R_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M8) + .value("PseudoVSM4R_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_MF2) + .value("PseudoVSMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1) + .value("PseudoVSMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1_MASK) + .value("PseudoVSMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2) + .value("PseudoVSMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2_MASK) + .value("PseudoVSMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4) + .value("PseudoVSMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4_MASK) + .value("PseudoVSMUL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8) + .value("PseudoVSMUL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8_MASK) + .value("PseudoVSMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2) + .value("PseudoVSMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2_MASK) + .value("PseudoVSMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4) + .value("PseudoVSMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4_MASK) + .value("PseudoVSMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8) + .value("PseudoVSMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8_MASK) + .value("PseudoVSMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1) + .value("PseudoVSMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1_MASK) + .value("PseudoVSMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2) + .value("PseudoVSMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2_MASK) + .value("PseudoVSMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4) + .value("PseudoVSMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4_MASK) + .value("PseudoVSMUL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8) + .value("PseudoVSMUL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8_MASK) + .value("PseudoVSMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2) + .value("PseudoVSMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2_MASK) + .value("PseudoVSMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4) + .value("PseudoVSMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4_MASK) + .value("PseudoVSMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8) + .value("PseudoVSMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8_MASK) + .value("PseudoVSM_V_B1", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B1) + .value("PseudoVSM_V_B16", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B16) + .value("PseudoVSM_V_B2", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B2) + .value("PseudoVSM_V_B32", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B32) + .value("PseudoVSM_V_B4", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B4) + .value("PseudoVSM_V_B64", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B64) + .value("PseudoVSM_V_B8", LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B8) + .value("PseudoVSOXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1) + .value("PseudoVSOXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1_MASK) + .value("PseudoVSOXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2) + .value("PseudoVSOXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2_MASK) + .value("PseudoVSOXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4) + .value("PseudoVSOXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4_MASK) + .value("PseudoVSOXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2) + .value("PseudoVSOXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2_MASK) + .value("PseudoVSOXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1) + .value("PseudoVSOXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1_MASK) + .value("PseudoVSOXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2) + .value("PseudoVSOXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2_MASK) + .value("PseudoVSOXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4) + .value("PseudoVSOXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4_MASK) + .value("PseudoVSOXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8) + .value("PseudoVSOXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8_MASK) + .value("PseudoVSOXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2) + .value("PseudoVSOXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2_MASK) + .value("PseudoVSOXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4) + .value("PseudoVSOXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4_MASK) + .value("PseudoVSOXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8) + .value("PseudoVSOXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8_MASK) + .value("PseudoVSOXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4) + .value("PseudoVSOXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4_MASK) + .value("PseudoVSOXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8) + .value("PseudoVSOXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8_MASK) + .value("PseudoVSOXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1) + .value("PseudoVSOXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1_MASK) + .value("PseudoVSOXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2) + .value("PseudoVSOXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2_MASK) + .value("PseudoVSOXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2) + .value("PseudoVSOXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2_MASK) + .value("PseudoVSOXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4) + .value("PseudoVSOXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4_MASK) + .value("PseudoVSOXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1) + .value("PseudoVSOXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1_MASK) + .value("PseudoVSOXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2) + .value("PseudoVSOXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2_MASK) + .value("PseudoVSOXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4) + .value("PseudoVSOXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4_MASK) + .value("PseudoVSOXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8) + .value("PseudoVSOXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8_MASK) + .value("PseudoVSOXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1) + .value("PseudoVSOXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1_MASK) + .value("PseudoVSOXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2) + .value("PseudoVSOXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2_MASK) + .value("PseudoVSOXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2) + .value("PseudoVSOXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2_MASK) + .value("PseudoVSOXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4) + .value("PseudoVSOXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4_MASK) + .value("PseudoVSOXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1) + .value("PseudoVSOXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1_MASK) + .value("PseudoVSOXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2) + .value("PseudoVSOXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2_MASK) + .value("PseudoVSOXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4) + .value("PseudoVSOXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4_MASK) + .value("PseudoVSOXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2) + .value("PseudoVSOXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2_MASK) + .value("PseudoVSOXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1) + .value("PseudoVSOXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1_MASK) + .value("PseudoVSOXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2) + .value("PseudoVSOXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2_MASK) + .value("PseudoVSOXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4) + .value("PseudoVSOXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4_MASK) + .value("PseudoVSOXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8) + .value("PseudoVSOXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8_MASK) + .value("PseudoVSOXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2) + .value("PseudoVSOXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2_MASK) + .value("PseudoVSOXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4); + opcodes.value("PseudoVSOXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4_MASK) + .value("PseudoVSOXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8) + .value("PseudoVSOXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8_MASK) + .value("PseudoVSOXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1) + .value("PseudoVSOXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1_MASK) + .value("PseudoVSOXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2) + .value("PseudoVSOXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2_MASK) + .value("PseudoVSOXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4) + .value("PseudoVSOXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4_MASK) + .value("PseudoVSOXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8) + .value("PseudoVSOXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8_MASK) + .value("PseudoVSOXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1) + .value("PseudoVSOXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1_MASK) + .value("PseudoVSOXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2) + .value("PseudoVSOXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2_MASK) + .value("PseudoVSOXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4) + .value("PseudoVSOXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4_MASK) + .value("PseudoVSOXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8) + .value("PseudoVSOXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8_MASK) + .value("PseudoVSOXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1) + .value("PseudoVSOXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1_MASK) + .value("PseudoVSOXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2) + .value("PseudoVSOXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2_MASK) + .value("PseudoVSOXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2) + .value("PseudoVSOXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2_MASK) + .value("PseudoVSOXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4) + .value("PseudoVSOXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4_MASK) + .value("PseudoVSOXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1) + .value("PseudoVSOXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1_MASK) + .value("PseudoVSOXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2) + .value("PseudoVSOXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2_MASK) + .value("PseudoVSOXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4) + .value("PseudoVSOXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4_MASK) + .value("PseudoVSOXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2) + .value("PseudoVSOXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2_MASK) + .value("PseudoVSOXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1) + .value("PseudoVSOXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1_MASK) + .value("PseudoVSOXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2) + .value("PseudoVSOXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2_MASK) + .value("PseudoVSOXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4) + .value("PseudoVSOXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4_MASK) + .value("PseudoVSOXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8) + .value("PseudoVSOXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8_MASK) + .value("PseudoVSOXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1) + .value("PseudoVSOXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1_MASK) + .value("PseudoVSOXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2) + .value("PseudoVSOXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2_MASK) + .value("PseudoVSOXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4) + .value("PseudoVSOXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4_MASK) + .value("PseudoVSOXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8) + .value("PseudoVSOXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8_MASK) + .value("PseudoVSOXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2) + .value("PseudoVSOXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2_MASK) + .value("PseudoVSOXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4) + .value("PseudoVSOXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4_MASK) + .value("PseudoVSOXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8) + .value("PseudoVSOXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8_MASK) + .value("PseudoVSOXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4) + .value("PseudoVSOXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4_MASK) + .value("PseudoVSOXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8) + .value("PseudoVSOXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8_MASK) + .value("PseudoVSOXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8) + .value("PseudoVSOXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8_MASK) + .value("PseudoVSOXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1) + .value("PseudoVSOXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1_MASK) + .value("PseudoVSOXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2) + .value("PseudoVSOXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2_MASK) + .value("PseudoVSOXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4) + .value("PseudoVSOXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4_MASK) + .value("PseudoVSOXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2) + .value("PseudoVSOXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2_MASK) + .value("PseudoVSOXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1) + .value("PseudoVSOXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1_MASK) + .value("PseudoVSOXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2) + .value("PseudoVSOXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2_MASK) + .value("PseudoVSOXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2) + .value("PseudoVSOXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2_MASK) + .value("PseudoVSOXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4) + .value("PseudoVSOXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4_MASK) + .value("PseudoVSOXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1) + .value("PseudoVSOXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1_MASK) + .value("PseudoVSOXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2) + .value("PseudoVSOXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2_MASK) + .value("PseudoVSOXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4) + .value("PseudoVSOXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4_MASK) + .value("PseudoVSOXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8) + .value("PseudoVSOXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1) + .value("PseudoVSOXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2) + .value("PseudoVSOXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2_MASK) + .value("PseudoVSOXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4) + .value("PseudoVSOXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4_MASK) + .value("PseudoVSOXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2) + .value("PseudoVSOXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1) + .value("PseudoVSOXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2) + .value("PseudoVSOXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2_MASK) + .value("PseudoVSOXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4) + .value("PseudoVSOXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4_MASK) + .value("PseudoVSOXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2) + .value("PseudoVSOXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2_MASK) + .value("PseudoVSOXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4) + .value("PseudoVSOXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4_MASK) + .value("PseudoVSOXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4) + .value("PseudoVSOXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4_MASK) + .value("PseudoVSOXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1) + .value("PseudoVSOXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2) + .value("PseudoVSOXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2_MASK) + .value("PseudoVSOXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2) + .value("PseudoVSOXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4) + .value("PseudoVSOXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1) + .value("PseudoVSOXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2) + .value("PseudoVSOXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4) + .value("PseudoVSOXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8) + .value("PseudoVSOXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1) + .value("PseudoVSOXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2) + .value("PseudoVSOXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2_MASK) + .value("PseudoVSOXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2) + .value("PseudoVSOXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4) + .value("PseudoVSOXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1) + .value("PseudoVSOXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2) + .value("PseudoVSOXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2_MASK) + .value("PseudoVSOXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4) + .value("PseudoVSOXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4_MASK) + .value("PseudoVSOXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2) + .value("PseudoVSOXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1) + .value("PseudoVSOXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2) + .value("PseudoVSOXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2_MASK) + .value("PseudoVSOXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4) + .value("PseudoVSOXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4_MASK) + .value("PseudoVSOXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2) + .value("PseudoVSOXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2_MASK) + .value("PseudoVSOXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4) + .value("PseudoVSOXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4_MASK) + .value("PseudoVSOXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1) + .value("PseudoVSOXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2) + .value("PseudoVSOXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4) + .value("PseudoVSOXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8) + .value("PseudoVSOXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1) + .value("PseudoVSOXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2) + .value("PseudoVSOXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4) + .value("PseudoVSOXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8) + .value("PseudoVSOXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1) + .value("PseudoVSOXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2) + .value("PseudoVSOXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2_MASK) + .value("PseudoVSOXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2) + .value("PseudoVSOXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4) + .value("PseudoVSOXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1) + .value("PseudoVSOXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2) + .value("PseudoVSOXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2_MASK) + .value("PseudoVSOXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4) + .value("PseudoVSOXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4_MASK) + .value("PseudoVSOXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2) + .value("PseudoVSOXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1) + .value("PseudoVSOXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2) + .value("PseudoVSOXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2_MASK) + .value("PseudoVSOXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4) + .value("PseudoVSOXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4_MASK) + .value("PseudoVSOXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1) + .value("PseudoVSOXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2) + .value("PseudoVSOXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2_MASK) + .value("PseudoVSOXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4) + .value("PseudoVSOXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4_MASK) + .value("PseudoVSOXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2) + .value("PseudoVSOXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2_MASK) + .value("PseudoVSOXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4) + .value("PseudoVSOXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4_MASK) + .value("PseudoVSOXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4) + .value("PseudoVSOXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4_MASK) + .value("PseudoVSOXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1) + .value("PseudoVSOXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2) + .value("PseudoVSOXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2_MASK) + .value("PseudoVSOXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4) + .value("PseudoVSOXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4_MASK) + .value("PseudoVSOXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2) + .value("PseudoVSOXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1) + .value("PseudoVSOXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2) + .value("PseudoVSOXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2_MASK) + .value("PseudoVSOXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2) + .value("PseudoVSOXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4) + .value("PseudoVSOXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1) + .value("PseudoVSOXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2) + .value("PseudoVSOXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4) + .value("PseudoVSOXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8) + .value("PseudoVSOXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1) + .value("PseudoVSOXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2) + .value("PseudoVSOXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2_MASK) + .value("PseudoVSOXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2) + .value("PseudoVSOXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1) + .value("PseudoVSOXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2) + .value("PseudoVSOXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2_MASK) + .value("PseudoVSOXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2) + .value("PseudoVSOXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2_MASK) + .value("PseudoVSOXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1) + .value("PseudoVSOXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2) + .value("PseudoVSOXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2_MASK) + .value("PseudoVSOXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2) + .value("PseudoVSOXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4) + .value("PseudoVSOXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1) + .value("PseudoVSOXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2) + .value("PseudoVSOXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4) + .value("PseudoVSOXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8) + .value("PseudoVSOXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1) + .value("PseudoVSOXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2) + .value("PseudoVSOXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2_MASK) + .value("PseudoVSOXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2) + .value("PseudoVSOXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4) + .value("PseudoVSOXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1) + .value("PseudoVSOXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2) + .value("PseudoVSOXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2_MASK) + .value("PseudoVSOXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2) + .value("PseudoVSOXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1) + .value("PseudoVSOXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2) + .value("PseudoVSOXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2_MASK) + .value("PseudoVSOXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2) + .value("PseudoVSOXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2_MASK) + .value("PseudoVSOXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1) + .value("PseudoVSOXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2) + .value("PseudoVSOXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4) + .value("PseudoVSOXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8) + .value("PseudoVSOXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1) + .value("PseudoVSOXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2) + .value("PseudoVSOXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4) + .value("PseudoVSOXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8) + .value("PseudoVSOXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1) + .value("PseudoVSOXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2) + .value("PseudoVSOXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2_MASK) + .value("PseudoVSOXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2) + .value("PseudoVSOXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4) + .value("PseudoVSOXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1) + .value("PseudoVSOXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2) + .value("PseudoVSOXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2_MASK) + .value("PseudoVSOXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2); + opcodes.value("PseudoVSOXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1) + .value("PseudoVSOXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2) + .value("PseudoVSOXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2_MASK) + .value("PseudoVSOXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1) + .value("PseudoVSOXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2) + .value("PseudoVSOXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2_MASK) + .value("PseudoVSOXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2) + .value("PseudoVSOXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1) + .value("PseudoVSOXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2) + .value("PseudoVSOXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2) + .value("PseudoVSOXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1) + .value("PseudoVSOXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2) + .value("PseudoVSOXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2) + .value("PseudoVSOXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4) + .value("PseudoVSOXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1) + .value("PseudoVSOXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2) + .value("PseudoVSOXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4) + .value("PseudoVSOXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8) + .value("PseudoVSOXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1) + .value("PseudoVSOXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2) + .value("PseudoVSOXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2_MASK) + .value("PseudoVSOXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2) + .value("PseudoVSOXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1) + .value("PseudoVSOXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2) + .value("PseudoVSOXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2_MASK) + .value("PseudoVSOXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2) + .value("PseudoVSOXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2_MASK) + .value("PseudoVSOXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1) + .value("PseudoVSOXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2) + .value("PseudoVSOXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2_MASK) + .value("PseudoVSOXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2) + .value("PseudoVSOXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4) + .value("PseudoVSOXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1) + .value("PseudoVSOXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2) + .value("PseudoVSOXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4) + .value("PseudoVSOXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8) + .value("PseudoVSOXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1) + .value("PseudoVSOXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2) + .value("PseudoVSOXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2_MASK) + .value("PseudoVSOXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2) + .value("PseudoVSOXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4) + .value("PseudoVSOXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1) + .value("PseudoVSOXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2) + .value("PseudoVSOXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2_MASK) + .value("PseudoVSOXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2) + .value("PseudoVSOXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1) + .value("PseudoVSOXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2) + .value("PseudoVSOXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2_MASK) + .value("PseudoVSOXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2) + .value("PseudoVSOXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2_MASK) + .value("PseudoVSOXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1) + .value("PseudoVSOXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2) + .value("PseudoVSOXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4) + .value("PseudoVSOXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8) + .value("PseudoVSOXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1) + .value("PseudoVSOXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2) + .value("PseudoVSOXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4) + .value("PseudoVSOXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8) + .value("PseudoVSOXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1) + .value("PseudoVSOXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2) + .value("PseudoVSOXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2_MASK) + .value("PseudoVSOXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2) + .value("PseudoVSOXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4) + .value("PseudoVSOXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1) + .value("PseudoVSOXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2) + .value("PseudoVSOXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2_MASK) + .value("PseudoVSOXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2) + .value("PseudoVSOXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1) + .value("PseudoVSOXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2) + .value("PseudoVSOXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2_MASK) + .value("PseudoVSOXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1) + .value("PseudoVSOXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2) + .value("PseudoVSOXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2_MASK) + .value("PseudoVSOXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2) + .value("PseudoVSOXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1) + .value("PseudoVSOXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2) + .value("PseudoVSOXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2) + .value("PseudoVSOXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1) + .value("PseudoVSOXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2) + .value("PseudoVSOXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2) + .value("PseudoVSOXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4) + .value("PseudoVSOXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1) + .value("PseudoVSOXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2) + .value("PseudoVSOXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4) + .value("PseudoVSOXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8) + .value("PseudoVSOXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1) + .value("PseudoVSOXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2) + .value("PseudoVSOXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1) + .value("PseudoVSOXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1) + .value("PseudoVSOXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2) + .value("PseudoVSOXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4) + .value("PseudoVSOXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1) + .value("PseudoVSOXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2) + .value("PseudoVSOXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4) + .value("PseudoVSOXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8) + .value("PseudoVSOXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1) + .value("PseudoVSOXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2) + .value("PseudoVSOXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4) + .value("PseudoVSOXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1) + .value("PseudoVSOXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2) + .value("PseudoVSOXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1) + .value("PseudoVSOXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1) + .value("PseudoVSOXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2) + .value("PseudoVSOXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4) + .value("PseudoVSOXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8) + .value("PseudoVSOXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1) + .value("PseudoVSOXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2) + .value("PseudoVSOXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4) + .value("PseudoVSOXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8) + .value("PseudoVSOXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1) + .value("PseudoVSOXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2) + .value("PseudoVSOXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4) + .value("PseudoVSOXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1) + .value("PseudoVSOXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2) + .value("PseudoVSOXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1) + .value("PseudoVSOXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1) + .value("PseudoVSOXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1) + .value("PseudoVSOXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2) + .value("PseudoVSOXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1) + .value("PseudoVSOXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2) + .value("PseudoVSOXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4) + .value("PseudoVSOXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1) + .value("PseudoVSOXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2) + .value("PseudoVSOXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4) + .value("PseudoVSOXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8) + .value("PseudoVSOXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1) + .value("PseudoVSOXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2) + .value("PseudoVSOXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1) + .value("PseudoVSOXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1) + .value("PseudoVSOXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2) + .value("PseudoVSOXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4) + .value("PseudoVSOXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1) + .value("PseudoVSOXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2) + .value("PseudoVSOXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4) + .value("PseudoVSOXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8) + .value("PseudoVSOXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1) + .value("PseudoVSOXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2) + .value("PseudoVSOXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4) + .value("PseudoVSOXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1) + .value("PseudoVSOXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2) + .value("PseudoVSOXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1) + .value("PseudoVSOXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1) + .value("PseudoVSOXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2) + .value("PseudoVSOXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4) + .value("PseudoVSOXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8) + .value("PseudoVSOXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1) + .value("PseudoVSOXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2) + .value("PseudoVSOXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4) + .value("PseudoVSOXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8) + .value("PseudoVSOXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1) + .value("PseudoVSOXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2) + .value("PseudoVSOXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4) + .value("PseudoVSOXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1) + .value("PseudoVSOXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2) + .value("PseudoVSOXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1) + .value("PseudoVSOXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1) + .value("PseudoVSOXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1) + .value("PseudoVSOXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2) + .value("PseudoVSOXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1) + .value("PseudoVSOXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2) + .value("PseudoVSOXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4) + .value("PseudoVSOXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1) + .value("PseudoVSOXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2) + .value("PseudoVSOXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4); + opcodes.value("PseudoVSOXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8) + .value("PseudoVSOXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1) + .value("PseudoVSOXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2) + .value("PseudoVSOXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1) + .value("PseudoVSOXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1) + .value("PseudoVSOXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2) + .value("PseudoVSOXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4) + .value("PseudoVSOXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1) + .value("PseudoVSOXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2) + .value("PseudoVSOXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4) + .value("PseudoVSOXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8) + .value("PseudoVSOXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1) + .value("PseudoVSOXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2) + .value("PseudoVSOXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4) + .value("PseudoVSOXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1) + .value("PseudoVSOXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2) + .value("PseudoVSOXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1) + .value("PseudoVSOXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1) + .value("PseudoVSOXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2) + .value("PseudoVSOXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4) + .value("PseudoVSOXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8) + .value("PseudoVSOXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1) + .value("PseudoVSOXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2) + .value("PseudoVSOXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4) + .value("PseudoVSOXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8) + .value("PseudoVSOXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1) + .value("PseudoVSOXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2) + .value("PseudoVSOXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4) + .value("PseudoVSOXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1) + .value("PseudoVSOXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2) + .value("PseudoVSOXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1) + .value("PseudoVSOXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1) + .value("PseudoVSOXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1) + .value("PseudoVSOXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2) + .value("PseudoVSOXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1) + .value("PseudoVSOXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2) + .value("PseudoVSOXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4) + .value("PseudoVSOXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1) + .value("PseudoVSOXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2) + .value("PseudoVSOXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4) + .value("PseudoVSOXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8) + .value("PseudoVSOXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK) + .value("PseudoVSOXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1) + .value("PseudoVSOXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1_MASK) + .value("PseudoVSOXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2) + .value("PseudoVSOXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2_MASK) + .value("PseudoVSOXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1) + .value("PseudoVSOXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1_MASK) + .value("PseudoVSOXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1) + .value("PseudoVSOXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1_MASK) + .value("PseudoVSOXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2) + .value("PseudoVSOXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4) + .value("PseudoVSOXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1) + .value("PseudoVSOXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1_MASK) + .value("PseudoVSOXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2) + .value("PseudoVSOXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4) + .value("PseudoVSOXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8) + .value("PseudoVSOXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK) + .value("PseudoVSOXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1) + .value("PseudoVSOXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1_MASK) + .value("PseudoVSOXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2) + .value("PseudoVSOXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2_MASK) + .value("PseudoVSOXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4) + .value("PseudoVSOXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4_MASK) + .value("PseudoVSOXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1) + .value("PseudoVSOXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1_MASK) + .value("PseudoVSOXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2) + .value("PseudoVSOXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2_MASK) + .value("PseudoVSOXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1) + .value("PseudoVSOXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1_MASK) + .value("PseudoVSOXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1) + .value("PseudoVSOXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1_MASK) + .value("PseudoVSOXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2) + .value("PseudoVSOXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4) + .value("PseudoVSOXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK) + .value("PseudoVSOXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8) + .value("PseudoVSOXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK) + .value("PseudoVSOXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1) + .value("PseudoVSOXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1_MASK) + .value("PseudoVSOXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2) + .value("PseudoVSOXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2_MASK) + .value("PseudoVSOXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4) + .value("PseudoVSOXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4_MASK) + .value("PseudoVSOXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8) + .value("PseudoVSOXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8_MASK) + .value("PseudoVSOXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1) + .value("PseudoVSOXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1_MASK) + .value("PseudoVSOXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2) + .value("PseudoVSOXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2_MASK) + .value("PseudoVSOXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4) + .value("PseudoVSOXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4_MASK) + .value("PseudoVSOXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1) + .value("PseudoVSOXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1_MASK) + .value("PseudoVSOXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2) + .value("PseudoVSOXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2_MASK) + .value("PseudoVSOXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1) + .value("PseudoVSOXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1_MASK) + .value("PseudoVSOXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1) + .value("PseudoVSOXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1_MASK) + .value("PseudoVSOXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1) + .value("PseudoVSOXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1_MASK) + .value("PseudoVSOXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2) + .value("PseudoVSOXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK) + .value("PseudoVSOXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1) + .value("PseudoVSOXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1_MASK) + .value("PseudoVSOXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2) + .value("PseudoVSOXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK) + .value("PseudoVSOXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4) + .value("PseudoVSOXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK) + .value("PseudoVSOXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1) + .value("PseudoVSOXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1_MASK) + .value("PseudoVSOXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2) + .value("PseudoVSOXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK) + .value("PseudoVSOXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4) + .value("PseudoVSOXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK) + .value("PseudoVSOXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8) + .value("PseudoVSOXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK) + .value("PseudoVSPILL2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M1) + .value("PseudoVSPILL2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M2) + .value("PseudoVSPILL2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M4) + .value("PseudoVSPILL2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF2) + .value("PseudoVSPILL2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF4) + .value("PseudoVSPILL2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF8) + .value("PseudoVSPILL3_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M1) + .value("PseudoVSPILL3_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M2) + .value("PseudoVSPILL3_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF2) + .value("PseudoVSPILL3_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF4) + .value("PseudoVSPILL3_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF8) + .value("PseudoVSPILL4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M1) + .value("PseudoVSPILL4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M2) + .value("PseudoVSPILL4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF2) + .value("PseudoVSPILL4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF4) + .value("PseudoVSPILL4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF8) + .value("PseudoVSPILL5_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_M1) + .value("PseudoVSPILL5_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF2) + .value("PseudoVSPILL5_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF4) + .value("PseudoVSPILL5_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF8) + .value("PseudoVSPILL6_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_M1) + .value("PseudoVSPILL6_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF2) + .value("PseudoVSPILL6_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF4) + .value("PseudoVSPILL6_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF8) + .value("PseudoVSPILL7_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_M1) + .value("PseudoVSPILL7_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF2) + .value("PseudoVSPILL7_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF4) + .value("PseudoVSPILL7_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF8) + .value("PseudoVSPILL8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_M1) + .value("PseudoVSPILL8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF2) + .value("PseudoVSPILL8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF4) + .value("PseudoVSPILL8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF8) + .value("PseudoVSRA_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1) + .value("PseudoVSRA_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1_MASK) + .value("PseudoVSRA_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2) + .value("PseudoVSRA_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2_MASK) + .value("PseudoVSRA_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4) + .value("PseudoVSRA_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4_MASK) + .value("PseudoVSRA_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8) + .value("PseudoVSRA_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8_MASK) + .value("PseudoVSRA_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2) + .value("PseudoVSRA_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2_MASK) + .value("PseudoVSRA_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4) + .value("PseudoVSRA_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4_MASK) + .value("PseudoVSRA_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8) + .value("PseudoVSRA_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8_MASK) + .value("PseudoVSRA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1) + .value("PseudoVSRA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1_MASK) + .value("PseudoVSRA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2) + .value("PseudoVSRA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2_MASK) + .value("PseudoVSRA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4) + .value("PseudoVSRA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4_MASK) + .value("PseudoVSRA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8) + .value("PseudoVSRA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8_MASK) + .value("PseudoVSRA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2) + .value("PseudoVSRA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2_MASK) + .value("PseudoVSRA_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4) + .value("PseudoVSRA_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4_MASK) + .value("PseudoVSRA_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8) + .value("PseudoVSRA_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8_MASK) + .value("PseudoVSRA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1) + .value("PseudoVSRA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1_MASK) + .value("PseudoVSRA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2) + .value("PseudoVSRA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2_MASK) + .value("PseudoVSRA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4) + .value("PseudoVSRA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4_MASK) + .value("PseudoVSRA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8) + .value("PseudoVSRA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8_MASK) + .value("PseudoVSRA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2) + .value("PseudoVSRA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2_MASK) + .value("PseudoVSRA_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4) + .value("PseudoVSRA_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4_MASK) + .value("PseudoVSRA_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8) + .value("PseudoVSRA_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8_MASK) + .value("PseudoVSRL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1) + .value("PseudoVSRL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1_MASK) + .value("PseudoVSRL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2) + .value("PseudoVSRL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2_MASK) + .value("PseudoVSRL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4) + .value("PseudoVSRL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4_MASK) + .value("PseudoVSRL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8) + .value("PseudoVSRL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8_MASK) + .value("PseudoVSRL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2) + .value("PseudoVSRL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2_MASK) + .value("PseudoVSRL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4) + .value("PseudoVSRL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4_MASK) + .value("PseudoVSRL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8) + .value("PseudoVSRL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8_MASK) + .value("PseudoVSRL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1) + .value("PseudoVSRL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1_MASK) + .value("PseudoVSRL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2) + .value("PseudoVSRL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2_MASK) + .value("PseudoVSRL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4) + .value("PseudoVSRL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4_MASK) + .value("PseudoVSRL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8) + .value("PseudoVSRL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8_MASK) + .value("PseudoVSRL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2) + .value("PseudoVSRL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2_MASK) + .value("PseudoVSRL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4) + .value("PseudoVSRL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4_MASK) + .value("PseudoVSRL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8) + .value("PseudoVSRL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8_MASK) + .value("PseudoVSRL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1) + .value("PseudoVSRL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1_MASK) + .value("PseudoVSRL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2) + .value("PseudoVSRL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2_MASK) + .value("PseudoVSRL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4) + .value("PseudoVSRL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4_MASK) + .value("PseudoVSRL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8) + .value("PseudoVSRL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8_MASK) + .value("PseudoVSRL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2) + .value("PseudoVSRL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2_MASK) + .value("PseudoVSRL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4) + .value("PseudoVSRL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4_MASK) + .value("PseudoVSRL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8) + .value("PseudoVSRL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8_MASK) + .value("PseudoVSSE16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1) + .value("PseudoVSSE16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1_MASK) + .value("PseudoVSSE16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2) + .value("PseudoVSSE16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2_MASK) + .value("PseudoVSSE16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4) + .value("PseudoVSSE16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4_MASK) + .value("PseudoVSSE16_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8) + .value("PseudoVSSE16_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8_MASK) + .value("PseudoVSSE16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2) + .value("PseudoVSSE16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2_MASK) + .value("PseudoVSSE16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4) + .value("PseudoVSSE16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4_MASK) + .value("PseudoVSSE32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1) + .value("PseudoVSSE32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1_MASK) + .value("PseudoVSSE32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2) + .value("PseudoVSSE32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2_MASK) + .value("PseudoVSSE32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4) + .value("PseudoVSSE32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4_MASK) + .value("PseudoVSSE32_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8) + .value("PseudoVSSE32_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8_MASK) + .value("PseudoVSSE32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2); + opcodes.value("PseudoVSSE32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2_MASK) + .value("PseudoVSSE64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1) + .value("PseudoVSSE64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1_MASK) + .value("PseudoVSSE64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2) + .value("PseudoVSSE64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2_MASK) + .value("PseudoVSSE64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4) + .value("PseudoVSSE64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4_MASK) + .value("PseudoVSSE64_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8) + .value("PseudoVSSE64_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8_MASK) + .value("PseudoVSSE8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1) + .value("PseudoVSSE8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1_MASK) + .value("PseudoVSSE8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2) + .value("PseudoVSSE8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2_MASK) + .value("PseudoVSSE8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4) + .value("PseudoVSSE8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4_MASK) + .value("PseudoVSSE8_V_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8) + .value("PseudoVSSE8_V_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8_MASK) + .value("PseudoVSSE8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2) + .value("PseudoVSSE8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2_MASK) + .value("PseudoVSSE8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4) + .value("PseudoVSSE8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4_MASK) + .value("PseudoVSSE8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8) + .value("PseudoVSSE8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8_MASK) + .value("PseudoVSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1) + .value("PseudoVSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1_MASK) + .value("PseudoVSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2) + .value("PseudoVSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2_MASK) + .value("PseudoVSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4) + .value("PseudoVSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4_MASK) + .value("PseudoVSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2) + .value("PseudoVSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2_MASK) + .value("PseudoVSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4) + .value("PseudoVSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4_MASK) + .value("PseudoVSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1) + .value("PseudoVSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1_MASK) + .value("PseudoVSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2) + .value("PseudoVSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2_MASK) + .value("PseudoVSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4) + .value("PseudoVSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4_MASK) + .value("PseudoVSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2) + .value("PseudoVSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2_MASK) + .value("PseudoVSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1) + .value("PseudoVSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1_MASK) + .value("PseudoVSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2) + .value("PseudoVSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2_MASK) + .value("PseudoVSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4) + .value("PseudoVSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4_MASK) + .value("PseudoVSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1) + .value("PseudoVSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1_MASK) + .value("PseudoVSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2) + .value("PseudoVSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2_MASK) + .value("PseudoVSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4) + .value("PseudoVSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4_MASK) + .value("PseudoVSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2) + .value("PseudoVSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2_MASK) + .value("PseudoVSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4) + .value("PseudoVSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4_MASK) + .value("PseudoVSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8) + .value("PseudoVSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8_MASK) + .value("PseudoVSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1) + .value("PseudoVSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1_MASK) + .value("PseudoVSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2) + .value("PseudoVSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2_MASK) + .value("PseudoVSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2) + .value("PseudoVSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2_MASK) + .value("PseudoVSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4) + .value("PseudoVSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4_MASK) + .value("PseudoVSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1) + .value("PseudoVSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1_MASK) + .value("PseudoVSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2) + .value("PseudoVSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2_MASK) + .value("PseudoVSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2) + .value("PseudoVSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2_MASK) + .value("PseudoVSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1) + .value("PseudoVSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1_MASK) + .value("PseudoVSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2) + .value("PseudoVSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2_MASK) + .value("PseudoVSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1) + .value("PseudoVSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1_MASK) + .value("PseudoVSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2) + .value("PseudoVSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2_MASK) + .value("PseudoVSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2) + .value("PseudoVSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2_MASK) + .value("PseudoVSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4) + .value("PseudoVSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4_MASK) + .value("PseudoVSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8) + .value("PseudoVSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8_MASK) + .value("PseudoVSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1) + .value("PseudoVSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1_MASK) + .value("PseudoVSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2) + .value("PseudoVSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2_MASK) + .value("PseudoVSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2) + .value("PseudoVSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2_MASK) + .value("PseudoVSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4) + .value("PseudoVSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4_MASK) + .value("PseudoVSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1) + .value("PseudoVSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1_MASK) + .value("PseudoVSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2) + .value("PseudoVSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2_MASK) + .value("PseudoVSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2) + .value("PseudoVSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2_MASK) + .value("PseudoVSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1) + .value("PseudoVSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1_MASK) + .value("PseudoVSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2) + .value("PseudoVSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2_MASK) + .value("PseudoVSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1) + .value("PseudoVSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1_MASK) + .value("PseudoVSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2) + .value("PseudoVSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2_MASK) + .value("PseudoVSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2) + .value("PseudoVSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2_MASK) + .value("PseudoVSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4) + .value("PseudoVSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4_MASK) + .value("PseudoVSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8) + .value("PseudoVSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8_MASK) + .value("PseudoVSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1) + .value("PseudoVSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1_MASK) + .value("PseudoVSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2) + .value("PseudoVSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2_MASK) + .value("PseudoVSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4) + .value("PseudoVSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4_MASK) + .value("PseudoVSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1) + .value("PseudoVSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1_MASK) + .value("PseudoVSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2) + .value("PseudoVSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2_MASK) + .value("PseudoVSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1) + .value("PseudoVSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1_MASK) + .value("PseudoVSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1) + .value("PseudoVSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1_MASK) + .value("PseudoVSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2) + .value("PseudoVSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2_MASK) + .value("PseudoVSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4) + .value("PseudoVSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4_MASK) + .value("PseudoVSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8) + .value("PseudoVSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8_MASK) + .value("PseudoVSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1) + .value("PseudoVSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1_MASK) + .value("PseudoVSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2) + .value("PseudoVSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2_MASK) + .value("PseudoVSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4) + .value("PseudoVSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4_MASK) + .value("PseudoVSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1) + .value("PseudoVSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1_MASK) + .value("PseudoVSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2) + .value("PseudoVSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2_MASK) + .value("PseudoVSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1) + .value("PseudoVSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1_MASK) + .value("PseudoVSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1) + .value("PseudoVSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1_MASK) + .value("PseudoVSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2) + .value("PseudoVSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2_MASK) + .value("PseudoVSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4) + .value("PseudoVSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4_MASK) + .value("PseudoVSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8) + .value("PseudoVSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8_MASK) + .value("PseudoVSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1) + .value("PseudoVSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1_MASK) + .value("PseudoVSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2) + .value("PseudoVSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2_MASK) + .value("PseudoVSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4) + .value("PseudoVSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4_MASK) + .value("PseudoVSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1) + .value("PseudoVSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1_MASK) + .value("PseudoVSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2) + .value("PseudoVSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2_MASK) + .value("PseudoVSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1) + .value("PseudoVSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1_MASK) + .value("PseudoVSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1) + .value("PseudoVSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1_MASK) + .value("PseudoVSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2) + .value("PseudoVSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2_MASK) + .value("PseudoVSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4) + .value("PseudoVSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4_MASK) + .value("PseudoVSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8) + .value("PseudoVSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8_MASK) + .value("PseudoVSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1) + .value("PseudoVSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1_MASK) + .value("PseudoVSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2) + .value("PseudoVSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2_MASK) + .value("PseudoVSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4) + .value("PseudoVSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4_MASK) + .value("PseudoVSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1) + .value("PseudoVSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1_MASK) + .value("PseudoVSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2) + .value("PseudoVSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2_MASK) + .value("PseudoVSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1) + .value("PseudoVSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1_MASK) + .value("PseudoVSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1) + .value("PseudoVSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1_MASK) + .value("PseudoVSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2) + .value("PseudoVSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2_MASK) + .value("PseudoVSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4) + .value("PseudoVSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4_MASK) + .value("PseudoVSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8) + .value("PseudoVSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8_MASK) + .value("PseudoVSSRA_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1) + .value("PseudoVSSRA_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1_MASK) + .value("PseudoVSSRA_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2) + .value("PseudoVSSRA_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2_MASK) + .value("PseudoVSSRA_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4) + .value("PseudoVSSRA_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4_MASK) + .value("PseudoVSSRA_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8) + .value("PseudoVSSRA_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8_MASK) + .value("PseudoVSSRA_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2) + .value("PseudoVSSRA_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2_MASK) + .value("PseudoVSSRA_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4) + .value("PseudoVSSRA_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4_MASK) + .value("PseudoVSSRA_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8) + .value("PseudoVSSRA_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8_MASK) + .value("PseudoVSSRA_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1) + .value("PseudoVSSRA_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1_MASK) + .value("PseudoVSSRA_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2) + .value("PseudoVSSRA_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2_MASK) + .value("PseudoVSSRA_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4) + .value("PseudoVSSRA_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4_MASK) + .value("PseudoVSSRA_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8) + .value("PseudoVSSRA_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8_MASK) + .value("PseudoVSSRA_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2) + .value("PseudoVSSRA_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2_MASK) + .value("PseudoVSSRA_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4) + .value("PseudoVSSRA_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4_MASK) + .value("PseudoVSSRA_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8) + .value("PseudoVSSRA_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8_MASK) + .value("PseudoVSSRA_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1) + .value("PseudoVSSRA_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1_MASK) + .value("PseudoVSSRA_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2) + .value("PseudoVSSRA_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2_MASK) + .value("PseudoVSSRA_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4) + .value("PseudoVSSRA_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4_MASK) + .value("PseudoVSSRA_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8) + .value("PseudoVSSRA_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8_MASK) + .value("PseudoVSSRA_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2) + .value("PseudoVSSRA_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2_MASK) + .value("PseudoVSSRA_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4) + .value("PseudoVSSRA_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4_MASK) + .value("PseudoVSSRA_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8) + .value("PseudoVSSRA_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8_MASK) + .value("PseudoVSSRL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1) + .value("PseudoVSSRL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1_MASK) + .value("PseudoVSSRL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2) + .value("PseudoVSSRL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2_MASK) + .value("PseudoVSSRL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4) + .value("PseudoVSSRL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4_MASK) + .value("PseudoVSSRL_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8) + .value("PseudoVSSRL_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8_MASK) + .value("PseudoVSSRL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2) + .value("PseudoVSSRL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2_MASK) + .value("PseudoVSSRL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4) + .value("PseudoVSSRL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4_MASK) + .value("PseudoVSSRL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8) + .value("PseudoVSSRL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8_MASK) + .value("PseudoVSSRL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1) + .value("PseudoVSSRL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1_MASK) + .value("PseudoVSSRL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2) + .value("PseudoVSSRL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2_MASK) + .value("PseudoVSSRL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4) + .value("PseudoVSSRL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4_MASK) + .value("PseudoVSSRL_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8) + .value("PseudoVSSRL_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8_MASK) + .value("PseudoVSSRL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2) + .value("PseudoVSSRL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2_MASK) + .value("PseudoVSSRL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4) + .value("PseudoVSSRL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4_MASK) + .value("PseudoVSSRL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8) + .value("PseudoVSSRL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8_MASK) + .value("PseudoVSSRL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1) + .value("PseudoVSSRL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1_MASK) + .value("PseudoVSSRL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2) + .value("PseudoVSSRL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2_MASK) + .value("PseudoVSSRL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4) + .value("PseudoVSSRL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4_MASK) + .value("PseudoVSSRL_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8) + .value("PseudoVSSRL_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8_MASK) + .value("PseudoVSSRL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2) + .value("PseudoVSSRL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2_MASK) + .value("PseudoVSSRL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4) + .value("PseudoVSSRL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4_MASK) + .value("PseudoVSSRL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8) + .value("PseudoVSSRL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8_MASK) + .value("PseudoVSSSEG2E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1) + .value("PseudoVSSSEG2E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1_MASK) + .value("PseudoVSSSEG2E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2) + .value("PseudoVSSSEG2E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2_MASK) + .value("PseudoVSSSEG2E16_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4) + .value("PseudoVSSSEG2E16_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4_MASK) + .value("PseudoVSSSEG2E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2) + .value("PseudoVSSSEG2E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2_MASK) + .value("PseudoVSSSEG2E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4) + .value("PseudoVSSSEG2E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4_MASK) + .value("PseudoVSSSEG2E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1) + .value("PseudoVSSSEG2E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1_MASK) + .value("PseudoVSSSEG2E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2) + .value("PseudoVSSSEG2E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2_MASK) + .value("PseudoVSSSEG2E32_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4) + .value("PseudoVSSSEG2E32_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4_MASK) + .value("PseudoVSSSEG2E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2) + .value("PseudoVSSSEG2E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2_MASK) + .value("PseudoVSSSEG2E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1) + .value("PseudoVSSSEG2E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1_MASK) + .value("PseudoVSSSEG2E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2); + opcodes.value("PseudoVSSSEG2E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2_MASK) + .value("PseudoVSSSEG2E64_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4) + .value("PseudoVSSSEG2E64_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4_MASK) + .value("PseudoVSSSEG2E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1) + .value("PseudoVSSSEG2E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1_MASK) + .value("PseudoVSSSEG2E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2) + .value("PseudoVSSSEG2E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2_MASK) + .value("PseudoVSSSEG2E8_V_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4) + .value("PseudoVSSSEG2E8_V_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4_MASK) + .value("PseudoVSSSEG2E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2) + .value("PseudoVSSSEG2E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2_MASK) + .value("PseudoVSSSEG2E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4) + .value("PseudoVSSSEG2E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4_MASK) + .value("PseudoVSSSEG2E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8) + .value("PseudoVSSSEG2E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8_MASK) + .value("PseudoVSSSEG3E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1) + .value("PseudoVSSSEG3E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1_MASK) + .value("PseudoVSSSEG3E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2) + .value("PseudoVSSSEG3E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2_MASK) + .value("PseudoVSSSEG3E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2) + .value("PseudoVSSSEG3E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2_MASK) + .value("PseudoVSSSEG3E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4) + .value("PseudoVSSSEG3E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4_MASK) + .value("PseudoVSSSEG3E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1) + .value("PseudoVSSSEG3E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1_MASK) + .value("PseudoVSSSEG3E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2) + .value("PseudoVSSSEG3E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2_MASK) + .value("PseudoVSSSEG3E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2) + .value("PseudoVSSSEG3E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2_MASK) + .value("PseudoVSSSEG3E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1) + .value("PseudoVSSSEG3E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1_MASK) + .value("PseudoVSSSEG3E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2) + .value("PseudoVSSSEG3E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2_MASK) + .value("PseudoVSSSEG3E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1) + .value("PseudoVSSSEG3E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1_MASK) + .value("PseudoVSSSEG3E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2) + .value("PseudoVSSSEG3E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2_MASK) + .value("PseudoVSSSEG3E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2) + .value("PseudoVSSSEG3E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2_MASK) + .value("PseudoVSSSEG3E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4) + .value("PseudoVSSSEG3E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4_MASK) + .value("PseudoVSSSEG3E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8) + .value("PseudoVSSSEG3E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8_MASK) + .value("PseudoVSSSEG4E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1) + .value("PseudoVSSSEG4E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1_MASK) + .value("PseudoVSSSEG4E16_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2) + .value("PseudoVSSSEG4E16_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2_MASK) + .value("PseudoVSSSEG4E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2) + .value("PseudoVSSSEG4E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2_MASK) + .value("PseudoVSSSEG4E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4) + .value("PseudoVSSSEG4E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4_MASK) + .value("PseudoVSSSEG4E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1) + .value("PseudoVSSSEG4E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1_MASK) + .value("PseudoVSSSEG4E32_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2) + .value("PseudoVSSSEG4E32_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2_MASK) + .value("PseudoVSSSEG4E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2) + .value("PseudoVSSSEG4E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2_MASK) + .value("PseudoVSSSEG4E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1) + .value("PseudoVSSSEG4E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1_MASK) + .value("PseudoVSSSEG4E64_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2) + .value("PseudoVSSSEG4E64_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2_MASK) + .value("PseudoVSSSEG4E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1) + .value("PseudoVSSSEG4E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1_MASK) + .value("PseudoVSSSEG4E8_V_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2) + .value("PseudoVSSSEG4E8_V_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2_MASK) + .value("PseudoVSSSEG4E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2) + .value("PseudoVSSSEG4E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2_MASK) + .value("PseudoVSSSEG4E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4) + .value("PseudoVSSSEG4E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4_MASK) + .value("PseudoVSSSEG4E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8) + .value("PseudoVSSSEG4E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8_MASK) + .value("PseudoVSSSEG5E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1) + .value("PseudoVSSSEG5E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1_MASK) + .value("PseudoVSSSEG5E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2) + .value("PseudoVSSSEG5E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2_MASK) + .value("PseudoVSSSEG5E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4) + .value("PseudoVSSSEG5E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4_MASK) + .value("PseudoVSSSEG5E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1) + .value("PseudoVSSSEG5E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1_MASK) + .value("PseudoVSSSEG5E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2) + .value("PseudoVSSSEG5E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2_MASK) + .value("PseudoVSSSEG5E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1) + .value("PseudoVSSSEG5E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1_MASK) + .value("PseudoVSSSEG5E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1) + .value("PseudoVSSSEG5E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1_MASK) + .value("PseudoVSSSEG5E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2) + .value("PseudoVSSSEG5E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2_MASK) + .value("PseudoVSSSEG5E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4) + .value("PseudoVSSSEG5E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4_MASK) + .value("PseudoVSSSEG5E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8) + .value("PseudoVSSSEG5E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8_MASK) + .value("PseudoVSSSEG6E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1) + .value("PseudoVSSSEG6E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1_MASK) + .value("PseudoVSSSEG6E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2) + .value("PseudoVSSSEG6E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2_MASK) + .value("PseudoVSSSEG6E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4) + .value("PseudoVSSSEG6E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4_MASK) + .value("PseudoVSSSEG6E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1) + .value("PseudoVSSSEG6E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1_MASK) + .value("PseudoVSSSEG6E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2) + .value("PseudoVSSSEG6E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2_MASK) + .value("PseudoVSSSEG6E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1) + .value("PseudoVSSSEG6E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1_MASK) + .value("PseudoVSSSEG6E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1) + .value("PseudoVSSSEG6E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1_MASK) + .value("PseudoVSSSEG6E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2) + .value("PseudoVSSSEG6E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2_MASK) + .value("PseudoVSSSEG6E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4) + .value("PseudoVSSSEG6E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4_MASK) + .value("PseudoVSSSEG6E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8) + .value("PseudoVSSSEG6E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8_MASK) + .value("PseudoVSSSEG7E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1) + .value("PseudoVSSSEG7E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1_MASK) + .value("PseudoVSSSEG7E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2) + .value("PseudoVSSSEG7E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2_MASK) + .value("PseudoVSSSEG7E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4) + .value("PseudoVSSSEG7E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4_MASK) + .value("PseudoVSSSEG7E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1) + .value("PseudoVSSSEG7E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1_MASK) + .value("PseudoVSSSEG7E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2) + .value("PseudoVSSSEG7E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2_MASK) + .value("PseudoVSSSEG7E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1) + .value("PseudoVSSSEG7E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1_MASK) + .value("PseudoVSSSEG7E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1) + .value("PseudoVSSSEG7E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1_MASK) + .value("PseudoVSSSEG7E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2) + .value("PseudoVSSSEG7E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2_MASK) + .value("PseudoVSSSEG7E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4) + .value("PseudoVSSSEG7E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4_MASK) + .value("PseudoVSSSEG7E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8) + .value("PseudoVSSSEG7E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8_MASK) + .value("PseudoVSSSEG8E16_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1) + .value("PseudoVSSSEG8E16_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1_MASK) + .value("PseudoVSSSEG8E16_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2) + .value("PseudoVSSSEG8E16_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2_MASK) + .value("PseudoVSSSEG8E16_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4) + .value("PseudoVSSSEG8E16_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4_MASK) + .value("PseudoVSSSEG8E32_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1) + .value("PseudoVSSSEG8E32_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1_MASK) + .value("PseudoVSSSEG8E32_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2) + .value("PseudoVSSSEG8E32_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2_MASK) + .value("PseudoVSSSEG8E64_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1) + .value("PseudoVSSSEG8E64_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1_MASK) + .value("PseudoVSSSEG8E8_V_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1) + .value("PseudoVSSSEG8E8_V_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1_MASK) + .value("PseudoVSSSEG8E8_V_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2) + .value("PseudoVSSSEG8E8_V_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2_MASK) + .value("PseudoVSSSEG8E8_V_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4) + .value("PseudoVSSSEG8E8_V_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4_MASK) + .value("PseudoVSSSEG8E8_V_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8) + .value("PseudoVSSSEG8E8_V_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8_MASK) + .value("PseudoVSSUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1) + .value("PseudoVSSUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1_MASK) + .value("PseudoVSSUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2) + .value("PseudoVSSUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2_MASK) + .value("PseudoVSSUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4) + .value("PseudoVSSUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4_MASK) + .value("PseudoVSSUBU_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8) + .value("PseudoVSSUBU_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8_MASK) + .value("PseudoVSSUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2) + .value("PseudoVSSUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2_MASK) + .value("PseudoVSSUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4) + .value("PseudoVSSUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4_MASK) + .value("PseudoVSSUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8) + .value("PseudoVSSUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8_MASK) + .value("PseudoVSSUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1) + .value("PseudoVSSUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1_MASK) + .value("PseudoVSSUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2) + .value("PseudoVSSUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2_MASK) + .value("PseudoVSSUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4) + .value("PseudoVSSUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4_MASK) + .value("PseudoVSSUBU_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8) + .value("PseudoVSSUBU_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8_MASK) + .value("PseudoVSSUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2) + .value("PseudoVSSUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2_MASK) + .value("PseudoVSSUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4) + .value("PseudoVSSUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4_MASK) + .value("PseudoVSSUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8) + .value("PseudoVSSUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8_MASK) + .value("PseudoVSSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1) + .value("PseudoVSSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1_MASK) + .value("PseudoVSSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2) + .value("PseudoVSSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2_MASK) + .value("PseudoVSSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4) + .value("PseudoVSSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4_MASK) + .value("PseudoVSSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8) + .value("PseudoVSSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8_MASK) + .value("PseudoVSSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2) + .value("PseudoVSSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2_MASK) + .value("PseudoVSSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4) + .value("PseudoVSSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4_MASK) + .value("PseudoVSSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8) + .value("PseudoVSSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8_MASK) + .value("PseudoVSSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1) + .value("PseudoVSSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1_MASK) + .value("PseudoVSSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2) + .value("PseudoVSSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2_MASK) + .value("PseudoVSSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4) + .value("PseudoVSSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4_MASK) + .value("PseudoVSSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8) + .value("PseudoVSSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8_MASK) + .value("PseudoVSSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2) + .value("PseudoVSSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2_MASK) + .value("PseudoVSSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4) + .value("PseudoVSSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4_MASK) + .value("PseudoVSSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8) + .value("PseudoVSSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8_MASK) + .value("PseudoVSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1) + .value("PseudoVSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1_MASK) + .value("PseudoVSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2) + .value("PseudoVSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2_MASK) + .value("PseudoVSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4) + .value("PseudoVSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4_MASK) + .value("PseudoVSUB_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8) + .value("PseudoVSUB_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8_MASK) + .value("PseudoVSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2) + .value("PseudoVSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2_MASK) + .value("PseudoVSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4) + .value("PseudoVSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4_MASK) + .value("PseudoVSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8) + .value("PseudoVSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8_MASK) + .value("PseudoVSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1) + .value("PseudoVSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1_MASK) + .value("PseudoVSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2) + .value("PseudoVSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2_MASK) + .value("PseudoVSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4) + .value("PseudoVSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4_MASK) + .value("PseudoVSUB_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8) + .value("PseudoVSUB_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8_MASK) + .value("PseudoVSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2) + .value("PseudoVSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2_MASK) + .value("PseudoVSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4) + .value("PseudoVSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4_MASK) + .value("PseudoVSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8) + .value("PseudoVSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8_MASK) + .value("PseudoVSUXEI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1) + .value("PseudoVSUXEI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1_MASK) + .value("PseudoVSUXEI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2) + .value("PseudoVSUXEI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2_MASK) + .value("PseudoVSUXEI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4) + .value("PseudoVSUXEI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4_MASK) + .value("PseudoVSUXEI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2) + .value("PseudoVSUXEI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2_MASK) + .value("PseudoVSUXEI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1) + .value("PseudoVSUXEI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1_MASK) + .value("PseudoVSUXEI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2) + .value("PseudoVSUXEI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2_MASK) + .value("PseudoVSUXEI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4) + .value("PseudoVSUXEI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4_MASK) + .value("PseudoVSUXEI16_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8) + .value("PseudoVSUXEI16_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8_MASK) + .value("PseudoVSUXEI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2) + .value("PseudoVSUXEI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2_MASK) + .value("PseudoVSUXEI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4) + .value("PseudoVSUXEI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4_MASK) + .value("PseudoVSUXEI16_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8) + .value("PseudoVSUXEI16_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8_MASK) + .value("PseudoVSUXEI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4) + .value("PseudoVSUXEI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4_MASK) + .value("PseudoVSUXEI16_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8) + .value("PseudoVSUXEI16_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8_MASK) + .value("PseudoVSUXEI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1) + .value("PseudoVSUXEI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1_MASK) + .value("PseudoVSUXEI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2) + .value("PseudoVSUXEI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2_MASK) + .value("PseudoVSUXEI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2) + .value("PseudoVSUXEI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2_MASK) + .value("PseudoVSUXEI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4) + .value("PseudoVSUXEI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4_MASK) + .value("PseudoVSUXEI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1) + .value("PseudoVSUXEI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1_MASK) + .value("PseudoVSUXEI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2) + .value("PseudoVSUXEI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2_MASK) + .value("PseudoVSUXEI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4) + .value("PseudoVSUXEI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4_MASK) + .value("PseudoVSUXEI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8) + .value("PseudoVSUXEI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8_MASK) + .value("PseudoVSUXEI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1) + .value("PseudoVSUXEI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1_MASK) + .value("PseudoVSUXEI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2) + .value("PseudoVSUXEI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2_MASK) + .value("PseudoVSUXEI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2) + .value("PseudoVSUXEI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2_MASK) + .value("PseudoVSUXEI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4) + .value("PseudoVSUXEI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4_MASK) + .value("PseudoVSUXEI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1) + .value("PseudoVSUXEI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1_MASK) + .value("PseudoVSUXEI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2) + .value("PseudoVSUXEI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2_MASK) + .value("PseudoVSUXEI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4) + .value("PseudoVSUXEI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4_MASK) + .value("PseudoVSUXEI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2) + .value("PseudoVSUXEI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2_MASK) + .value("PseudoVSUXEI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1) + .value("PseudoVSUXEI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1_MASK) + .value("PseudoVSUXEI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2) + .value("PseudoVSUXEI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2_MASK) + .value("PseudoVSUXEI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4) + .value("PseudoVSUXEI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4_MASK) + .value("PseudoVSUXEI32_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8); + opcodes.value("PseudoVSUXEI32_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8_MASK) + .value("PseudoVSUXEI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2) + .value("PseudoVSUXEI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2_MASK) + .value("PseudoVSUXEI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4) + .value("PseudoVSUXEI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4_MASK) + .value("PseudoVSUXEI32_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8) + .value("PseudoVSUXEI32_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8_MASK) + .value("PseudoVSUXEI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1) + .value("PseudoVSUXEI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1_MASK) + .value("PseudoVSUXEI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2) + .value("PseudoVSUXEI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2_MASK) + .value("PseudoVSUXEI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4) + .value("PseudoVSUXEI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4_MASK) + .value("PseudoVSUXEI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8) + .value("PseudoVSUXEI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8_MASK) + .value("PseudoVSUXEI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1) + .value("PseudoVSUXEI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1_MASK) + .value("PseudoVSUXEI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2) + .value("PseudoVSUXEI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2_MASK) + .value("PseudoVSUXEI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4) + .value("PseudoVSUXEI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4_MASK) + .value("PseudoVSUXEI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8) + .value("PseudoVSUXEI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8_MASK) + .value("PseudoVSUXEI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1) + .value("PseudoVSUXEI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1_MASK) + .value("PseudoVSUXEI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2) + .value("PseudoVSUXEI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2_MASK) + .value("PseudoVSUXEI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2) + .value("PseudoVSUXEI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2_MASK) + .value("PseudoVSUXEI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4) + .value("PseudoVSUXEI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4_MASK) + .value("PseudoVSUXEI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1) + .value("PseudoVSUXEI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1_MASK) + .value("PseudoVSUXEI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2) + .value("PseudoVSUXEI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2_MASK) + .value("PseudoVSUXEI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4) + .value("PseudoVSUXEI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4_MASK) + .value("PseudoVSUXEI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2) + .value("PseudoVSUXEI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2_MASK) + .value("PseudoVSUXEI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1) + .value("PseudoVSUXEI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1_MASK) + .value("PseudoVSUXEI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2) + .value("PseudoVSUXEI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2_MASK) + .value("PseudoVSUXEI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4) + .value("PseudoVSUXEI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4_MASK) + .value("PseudoVSUXEI64_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8) + .value("PseudoVSUXEI64_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8_MASK) + .value("PseudoVSUXEI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1) + .value("PseudoVSUXEI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1_MASK) + .value("PseudoVSUXEI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2) + .value("PseudoVSUXEI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2_MASK) + .value("PseudoVSUXEI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4) + .value("PseudoVSUXEI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4_MASK) + .value("PseudoVSUXEI8_V_M1_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8) + .value("PseudoVSUXEI8_V_M1_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8_MASK) + .value("PseudoVSUXEI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2) + .value("PseudoVSUXEI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2_MASK) + .value("PseudoVSUXEI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4) + .value("PseudoVSUXEI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4_MASK) + .value("PseudoVSUXEI8_V_M2_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8) + .value("PseudoVSUXEI8_V_M2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8_MASK) + .value("PseudoVSUXEI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4) + .value("PseudoVSUXEI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4_MASK) + .value("PseudoVSUXEI8_V_M4_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8) + .value("PseudoVSUXEI8_V_M4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8_MASK) + .value("PseudoVSUXEI8_V_M8_M8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8) + .value("PseudoVSUXEI8_V_M8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8_MASK) + .value("PseudoVSUXEI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1) + .value("PseudoVSUXEI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1_MASK) + .value("PseudoVSUXEI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2) + .value("PseudoVSUXEI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2_MASK) + .value("PseudoVSUXEI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4) + .value("PseudoVSUXEI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4_MASK) + .value("PseudoVSUXEI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2) + .value("PseudoVSUXEI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2_MASK) + .value("PseudoVSUXEI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1) + .value("PseudoVSUXEI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1_MASK) + .value("PseudoVSUXEI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2) + .value("PseudoVSUXEI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2_MASK) + .value("PseudoVSUXEI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2) + .value("PseudoVSUXEI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2_MASK) + .value("PseudoVSUXEI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4) + .value("PseudoVSUXEI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4_MASK) + .value("PseudoVSUXEI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1) + .value("PseudoVSUXEI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1_MASK) + .value("PseudoVSUXEI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2) + .value("PseudoVSUXEI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2_MASK) + .value("PseudoVSUXEI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4) + .value("PseudoVSUXEI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4_MASK) + .value("PseudoVSUXEI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8) + .value("PseudoVSUXEI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG2EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1) + .value("PseudoVSUXSEG2EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG2EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2) + .value("PseudoVSUXSEG2EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2_MASK) + .value("PseudoVSUXSEG2EI16_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4) + .value("PseudoVSUXSEG2EI16_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4_MASK) + .value("PseudoVSUXSEG2EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2) + .value("PseudoVSUXSEG2EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG2EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1) + .value("PseudoVSUXSEG2EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG2EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2) + .value("PseudoVSUXSEG2EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2_MASK) + .value("PseudoVSUXSEG2EI16_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4) + .value("PseudoVSUXSEG2EI16_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4_MASK) + .value("PseudoVSUXSEG2EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2) + .value("PseudoVSUXSEG2EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2_MASK) + .value("PseudoVSUXSEG2EI16_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4) + .value("PseudoVSUXSEG2EI16_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4_MASK) + .value("PseudoVSUXSEG2EI16_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4) + .value("PseudoVSUXSEG2EI16_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4_MASK) + .value("PseudoVSUXSEG2EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1) + .value("PseudoVSUXSEG2EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG2EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2) + .value("PseudoVSUXSEG2EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2_MASK) + .value("PseudoVSUXSEG2EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2) + .value("PseudoVSUXSEG2EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG2EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4) + .value("PseudoVSUXSEG2EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG2EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1) + .value("PseudoVSUXSEG2EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG2EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2) + .value("PseudoVSUXSEG2EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG2EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4) + .value("PseudoVSUXSEG2EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG2EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8) + .value("PseudoVSUXSEG2EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG2EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1) + .value("PseudoVSUXSEG2EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG2EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2) + .value("PseudoVSUXSEG2EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2_MASK) + .value("PseudoVSUXSEG2EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2) + .value("PseudoVSUXSEG2EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG2EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4) + .value("PseudoVSUXSEG2EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG2EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1) + .value("PseudoVSUXSEG2EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG2EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2) + .value("PseudoVSUXSEG2EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2_MASK) + .value("PseudoVSUXSEG2EI32_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4) + .value("PseudoVSUXSEG2EI32_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4_MASK) + .value("PseudoVSUXSEG2EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2) + .value("PseudoVSUXSEG2EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG2EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1) + .value("PseudoVSUXSEG2EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG2EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2) + .value("PseudoVSUXSEG2EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2_MASK) + .value("PseudoVSUXSEG2EI32_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4) + .value("PseudoVSUXSEG2EI32_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4_MASK) + .value("PseudoVSUXSEG2EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2) + .value("PseudoVSUXSEG2EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2_MASK) + .value("PseudoVSUXSEG2EI32_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4) + .value("PseudoVSUXSEG2EI32_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4_MASK) + .value("PseudoVSUXSEG2EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1) + .value("PseudoVSUXSEG2EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG2EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2) + .value("PseudoVSUXSEG2EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG2EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4) + .value("PseudoVSUXSEG2EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG2EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8) + .value("PseudoVSUXSEG2EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG2EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1) + .value("PseudoVSUXSEG2EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG2EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2) + .value("PseudoVSUXSEG2EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG2EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4) + .value("PseudoVSUXSEG2EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG2EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8) + .value("PseudoVSUXSEG2EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG2EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1) + .value("PseudoVSUXSEG2EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG2EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2) + .value("PseudoVSUXSEG2EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2_MASK) + .value("PseudoVSUXSEG2EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2) + .value("PseudoVSUXSEG2EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG2EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4) + .value("PseudoVSUXSEG2EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG2EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1) + .value("PseudoVSUXSEG2EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG2EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2) + .value("PseudoVSUXSEG2EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2_MASK) + .value("PseudoVSUXSEG2EI64_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4) + .value("PseudoVSUXSEG2EI64_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4_MASK) + .value("PseudoVSUXSEG2EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2) + .value("PseudoVSUXSEG2EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG2EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1) + .value("PseudoVSUXSEG2EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG2EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2) + .value("PseudoVSUXSEG2EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2_MASK) + .value("PseudoVSUXSEG2EI64_V_M8_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4) + .value("PseudoVSUXSEG2EI64_V_M8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4_MASK) + .value("PseudoVSUXSEG2EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1) + .value("PseudoVSUXSEG2EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG2EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2) + .value("PseudoVSUXSEG2EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2_MASK) + .value("PseudoVSUXSEG2EI8_V_M1_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4) + .value("PseudoVSUXSEG2EI8_V_M1_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4_MASK) + .value("PseudoVSUXSEG2EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2) + .value("PseudoVSUXSEG2EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2_MASK) + .value("PseudoVSUXSEG2EI8_V_M2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4) + .value("PseudoVSUXSEG2EI8_V_M2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4_MASK) + .value("PseudoVSUXSEG2EI8_V_M4_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4) + .value("PseudoVSUXSEG2EI8_V_M4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4_MASK) + .value("PseudoVSUXSEG2EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1) + .value("PseudoVSUXSEG2EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG2EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2) + .value("PseudoVSUXSEG2EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2_MASK) + .value("PseudoVSUXSEG2EI8_V_MF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4) + .value("PseudoVSUXSEG2EI8_V_MF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4_MASK) + .value("PseudoVSUXSEG2EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2) + .value("PseudoVSUXSEG2EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG2EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1) + .value("PseudoVSUXSEG2EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG2EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2) + .value("PseudoVSUXSEG2EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2_MASK) + .value("PseudoVSUXSEG2EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2) + .value("PseudoVSUXSEG2EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG2EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4) + .value("PseudoVSUXSEG2EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG2EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1) + .value("PseudoVSUXSEG2EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG2EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2) + .value("PseudoVSUXSEG2EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG2EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4) + .value("PseudoVSUXSEG2EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG2EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8) + .value("PseudoVSUXSEG2EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG3EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1) + .value("PseudoVSUXSEG3EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG3EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2) + .value("PseudoVSUXSEG3EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2_MASK) + .value("PseudoVSUXSEG3EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2) + .value("PseudoVSUXSEG3EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG3EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1) + .value("PseudoVSUXSEG3EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG3EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2) + .value("PseudoVSUXSEG3EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2_MASK) + .value("PseudoVSUXSEG3EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2) + .value("PseudoVSUXSEG3EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2_MASK) + .value("PseudoVSUXSEG3EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1) + .value("PseudoVSUXSEG3EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG3EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2) + .value("PseudoVSUXSEG3EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2_MASK) + .value("PseudoVSUXSEG3EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2) + .value("PseudoVSUXSEG3EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG3EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4) + .value("PseudoVSUXSEG3EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG3EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1) + .value("PseudoVSUXSEG3EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG3EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2) + .value("PseudoVSUXSEG3EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG3EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4) + .value("PseudoVSUXSEG3EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG3EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8) + .value("PseudoVSUXSEG3EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG3EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1) + .value("PseudoVSUXSEG3EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG3EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2) + .value("PseudoVSUXSEG3EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2_MASK) + .value("PseudoVSUXSEG3EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2) + .value("PseudoVSUXSEG3EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG3EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4) + .value("PseudoVSUXSEG3EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG3EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1) + .value("PseudoVSUXSEG3EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG3EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2) + .value("PseudoVSUXSEG3EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2_MASK) + .value("PseudoVSUXSEG3EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2) + .value("PseudoVSUXSEG3EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG3EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1) + .value("PseudoVSUXSEG3EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG3EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2) + .value("PseudoVSUXSEG3EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2_MASK) + .value("PseudoVSUXSEG3EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2) + .value("PseudoVSUXSEG3EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2_MASK) + .value("PseudoVSUXSEG3EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1) + .value("PseudoVSUXSEG3EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG3EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2) + .value("PseudoVSUXSEG3EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG3EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4) + .value("PseudoVSUXSEG3EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG3EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8) + .value("PseudoVSUXSEG3EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG3EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1) + .value("PseudoVSUXSEG3EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG3EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2) + .value("PseudoVSUXSEG3EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG3EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4) + .value("PseudoVSUXSEG3EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG3EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8) + .value("PseudoVSUXSEG3EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG3EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1) + .value("PseudoVSUXSEG3EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG3EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2) + .value("PseudoVSUXSEG3EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2_MASK) + .value("PseudoVSUXSEG3EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2) + .value("PseudoVSUXSEG3EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG3EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4) + .value("PseudoVSUXSEG3EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG3EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1); + opcodes.value("PseudoVSUXSEG3EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG3EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2) + .value("PseudoVSUXSEG3EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2_MASK) + .value("PseudoVSUXSEG3EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2) + .value("PseudoVSUXSEG3EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG3EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1) + .value("PseudoVSUXSEG3EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG3EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2) + .value("PseudoVSUXSEG3EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2_MASK) + .value("PseudoVSUXSEG3EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1) + .value("PseudoVSUXSEG3EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG3EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2) + .value("PseudoVSUXSEG3EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2_MASK) + .value("PseudoVSUXSEG3EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2) + .value("PseudoVSUXSEG3EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1) + .value("PseudoVSUXSEG3EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG3EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2) + .value("PseudoVSUXSEG3EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2) + .value("PseudoVSUXSEG3EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1) + .value("PseudoVSUXSEG3EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG3EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2) + .value("PseudoVSUXSEG3EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2) + .value("PseudoVSUXSEG3EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4) + .value("PseudoVSUXSEG3EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG3EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1) + .value("PseudoVSUXSEG3EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG3EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2) + .value("PseudoVSUXSEG3EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG3EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4) + .value("PseudoVSUXSEG3EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG3EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8) + .value("PseudoVSUXSEG3EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG4EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1) + .value("PseudoVSUXSEG4EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG4EI16_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2) + .value("PseudoVSUXSEG4EI16_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2_MASK) + .value("PseudoVSUXSEG4EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2) + .value("PseudoVSUXSEG4EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG4EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1) + .value("PseudoVSUXSEG4EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG4EI16_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2) + .value("PseudoVSUXSEG4EI16_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2_MASK) + .value("PseudoVSUXSEG4EI16_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2) + .value("PseudoVSUXSEG4EI16_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2_MASK) + .value("PseudoVSUXSEG4EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1) + .value("PseudoVSUXSEG4EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG4EI16_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2) + .value("PseudoVSUXSEG4EI16_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2_MASK) + .value("PseudoVSUXSEG4EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2) + .value("PseudoVSUXSEG4EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG4EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4) + .value("PseudoVSUXSEG4EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG4EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1) + .value("PseudoVSUXSEG4EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG4EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2) + .value("PseudoVSUXSEG4EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG4EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4) + .value("PseudoVSUXSEG4EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG4EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8) + .value("PseudoVSUXSEG4EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG4EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1) + .value("PseudoVSUXSEG4EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG4EI32_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2) + .value("PseudoVSUXSEG4EI32_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2_MASK) + .value("PseudoVSUXSEG4EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2) + .value("PseudoVSUXSEG4EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG4EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4) + .value("PseudoVSUXSEG4EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG4EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1) + .value("PseudoVSUXSEG4EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG4EI32_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2) + .value("PseudoVSUXSEG4EI32_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2_MASK) + .value("PseudoVSUXSEG4EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2) + .value("PseudoVSUXSEG4EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG4EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1) + .value("PseudoVSUXSEG4EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG4EI32_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2) + .value("PseudoVSUXSEG4EI32_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2_MASK) + .value("PseudoVSUXSEG4EI32_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2) + .value("PseudoVSUXSEG4EI32_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2_MASK) + .value("PseudoVSUXSEG4EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1) + .value("PseudoVSUXSEG4EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG4EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2) + .value("PseudoVSUXSEG4EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG4EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4) + .value("PseudoVSUXSEG4EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG4EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8) + .value("PseudoVSUXSEG4EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG4EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1) + .value("PseudoVSUXSEG4EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG4EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2) + .value("PseudoVSUXSEG4EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG4EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4) + .value("PseudoVSUXSEG4EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG4EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8) + .value("PseudoVSUXSEG4EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG4EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1) + .value("PseudoVSUXSEG4EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG4EI64_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2) + .value("PseudoVSUXSEG4EI64_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2_MASK) + .value("PseudoVSUXSEG4EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2) + .value("PseudoVSUXSEG4EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG4EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4) + .value("PseudoVSUXSEG4EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG4EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1) + .value("PseudoVSUXSEG4EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG4EI64_V_M4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2) + .value("PseudoVSUXSEG4EI64_V_M4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2_MASK) + .value("PseudoVSUXSEG4EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2) + .value("PseudoVSUXSEG4EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG4EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1) + .value("PseudoVSUXSEG4EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG4EI64_V_M8_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2) + .value("PseudoVSUXSEG4EI64_V_M8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2_MASK) + .value("PseudoVSUXSEG4EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1) + .value("PseudoVSUXSEG4EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG4EI8_V_M1_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2) + .value("PseudoVSUXSEG4EI8_V_M1_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2_MASK) + .value("PseudoVSUXSEG4EI8_V_M2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2) + .value("PseudoVSUXSEG4EI8_V_M2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1) + .value("PseudoVSUXSEG4EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG4EI8_V_MF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2) + .value("PseudoVSUXSEG4EI8_V_MF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2) + .value("PseudoVSUXSEG4EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1) + .value("PseudoVSUXSEG4EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG4EI8_V_MF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2) + .value("PseudoVSUXSEG4EI8_V_MF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2) + .value("PseudoVSUXSEG4EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4) + .value("PseudoVSUXSEG4EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG4EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1) + .value("PseudoVSUXSEG4EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG4EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2) + .value("PseudoVSUXSEG4EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG4EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4) + .value("PseudoVSUXSEG4EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG4EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8) + .value("PseudoVSUXSEG4EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG5EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1) + .value("PseudoVSUXSEG5EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG5EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2) + .value("PseudoVSUXSEG5EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG5EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1) + .value("PseudoVSUXSEG5EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG5EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1) + .value("PseudoVSUXSEG5EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG5EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2) + .value("PseudoVSUXSEG5EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG5EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4) + .value("PseudoVSUXSEG5EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG5EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1) + .value("PseudoVSUXSEG5EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG5EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2) + .value("PseudoVSUXSEG5EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG5EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4) + .value("PseudoVSUXSEG5EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG5EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8) + .value("PseudoVSUXSEG5EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG5EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1) + .value("PseudoVSUXSEG5EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG5EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2) + .value("PseudoVSUXSEG5EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG5EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4) + .value("PseudoVSUXSEG5EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG5EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1) + .value("PseudoVSUXSEG5EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG5EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2) + .value("PseudoVSUXSEG5EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG5EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1) + .value("PseudoVSUXSEG5EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG5EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1) + .value("PseudoVSUXSEG5EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG5EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2) + .value("PseudoVSUXSEG5EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG5EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4) + .value("PseudoVSUXSEG5EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG5EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8) + .value("PseudoVSUXSEG5EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG5EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1) + .value("PseudoVSUXSEG5EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG5EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2) + .value("PseudoVSUXSEG5EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG5EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4) + .value("PseudoVSUXSEG5EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG5EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8) + .value("PseudoVSUXSEG5EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG5EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1) + .value("PseudoVSUXSEG5EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG5EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2) + .value("PseudoVSUXSEG5EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG5EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4) + .value("PseudoVSUXSEG5EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG5EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1) + .value("PseudoVSUXSEG5EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG5EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2) + .value("PseudoVSUXSEG5EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG5EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1) + .value("PseudoVSUXSEG5EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG5EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1) + .value("PseudoVSUXSEG5EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG5EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1) + .value("PseudoVSUXSEG5EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG5EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2) + .value("PseudoVSUXSEG5EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG5EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1) + .value("PseudoVSUXSEG5EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG5EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2) + .value("PseudoVSUXSEG5EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG5EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4) + .value("PseudoVSUXSEG5EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG5EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1) + .value("PseudoVSUXSEG5EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG5EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2) + .value("PseudoVSUXSEG5EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG5EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4) + .value("PseudoVSUXSEG5EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG5EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8) + .value("PseudoVSUXSEG5EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG6EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1) + .value("PseudoVSUXSEG6EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG6EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2) + .value("PseudoVSUXSEG6EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG6EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1) + .value("PseudoVSUXSEG6EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG6EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1) + .value("PseudoVSUXSEG6EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG6EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2) + .value("PseudoVSUXSEG6EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG6EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4) + .value("PseudoVSUXSEG6EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG6EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1) + .value("PseudoVSUXSEG6EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG6EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2) + .value("PseudoVSUXSEG6EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG6EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4) + .value("PseudoVSUXSEG6EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG6EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8) + .value("PseudoVSUXSEG6EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG6EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1) + .value("PseudoVSUXSEG6EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG6EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2) + .value("PseudoVSUXSEG6EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG6EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4) + .value("PseudoVSUXSEG6EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG6EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1) + .value("PseudoVSUXSEG6EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG6EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2) + .value("PseudoVSUXSEG6EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG6EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1) + .value("PseudoVSUXSEG6EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG6EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1) + .value("PseudoVSUXSEG6EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG6EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2) + .value("PseudoVSUXSEG6EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG6EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4) + .value("PseudoVSUXSEG6EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG6EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8) + .value("PseudoVSUXSEG6EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG6EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1) + .value("PseudoVSUXSEG6EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG6EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2) + .value("PseudoVSUXSEG6EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG6EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4) + .value("PseudoVSUXSEG6EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG6EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8) + .value("PseudoVSUXSEG6EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG6EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1) + .value("PseudoVSUXSEG6EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG6EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2) + .value("PseudoVSUXSEG6EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG6EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4) + .value("PseudoVSUXSEG6EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG6EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1) + .value("PseudoVSUXSEG6EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG6EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2) + .value("PseudoVSUXSEG6EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG6EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1) + .value("PseudoVSUXSEG6EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG6EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1) + .value("PseudoVSUXSEG6EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG6EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1) + .value("PseudoVSUXSEG6EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG6EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2) + .value("PseudoVSUXSEG6EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG6EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1) + .value("PseudoVSUXSEG6EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG6EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2) + .value("PseudoVSUXSEG6EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG6EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4) + .value("PseudoVSUXSEG6EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG6EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1); + opcodes.value("PseudoVSUXSEG6EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG6EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2) + .value("PseudoVSUXSEG6EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG6EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4) + .value("PseudoVSUXSEG6EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG6EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8) + .value("PseudoVSUXSEG6EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG7EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1) + .value("PseudoVSUXSEG7EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG7EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2) + .value("PseudoVSUXSEG7EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG7EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1) + .value("PseudoVSUXSEG7EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG7EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1) + .value("PseudoVSUXSEG7EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG7EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2) + .value("PseudoVSUXSEG7EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG7EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4) + .value("PseudoVSUXSEG7EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG7EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1) + .value("PseudoVSUXSEG7EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG7EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2) + .value("PseudoVSUXSEG7EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG7EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4) + .value("PseudoVSUXSEG7EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG7EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8) + .value("PseudoVSUXSEG7EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG7EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1) + .value("PseudoVSUXSEG7EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG7EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2) + .value("PseudoVSUXSEG7EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG7EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4) + .value("PseudoVSUXSEG7EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG7EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1) + .value("PseudoVSUXSEG7EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG7EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2) + .value("PseudoVSUXSEG7EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG7EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1) + .value("PseudoVSUXSEG7EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG7EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1) + .value("PseudoVSUXSEG7EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG7EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2) + .value("PseudoVSUXSEG7EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG7EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4) + .value("PseudoVSUXSEG7EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG7EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8) + .value("PseudoVSUXSEG7EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG7EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1) + .value("PseudoVSUXSEG7EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG7EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2) + .value("PseudoVSUXSEG7EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG7EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4) + .value("PseudoVSUXSEG7EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG7EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8) + .value("PseudoVSUXSEG7EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG7EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1) + .value("PseudoVSUXSEG7EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG7EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2) + .value("PseudoVSUXSEG7EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG7EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4) + .value("PseudoVSUXSEG7EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG7EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1) + .value("PseudoVSUXSEG7EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG7EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2) + .value("PseudoVSUXSEG7EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG7EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1) + .value("PseudoVSUXSEG7EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG7EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1) + .value("PseudoVSUXSEG7EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG7EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1) + .value("PseudoVSUXSEG7EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG7EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2) + .value("PseudoVSUXSEG7EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG7EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1) + .value("PseudoVSUXSEG7EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG7EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2) + .value("PseudoVSUXSEG7EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG7EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4) + .value("PseudoVSUXSEG7EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG7EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1) + .value("PseudoVSUXSEG7EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG7EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2) + .value("PseudoVSUXSEG7EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG7EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4) + .value("PseudoVSUXSEG7EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG7EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8) + .value("PseudoVSUXSEG7EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK) + .value("PseudoVSUXSEG8EI16_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1) + .value("PseudoVSUXSEG8EI16_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1_MASK) + .value("PseudoVSUXSEG8EI16_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2) + .value("PseudoVSUXSEG8EI16_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2_MASK) + .value("PseudoVSUXSEG8EI16_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1) + .value("PseudoVSUXSEG8EI16_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1_MASK) + .value("PseudoVSUXSEG8EI16_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1) + .value("PseudoVSUXSEG8EI16_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1_MASK) + .value("PseudoVSUXSEG8EI16_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2) + .value("PseudoVSUXSEG8EI16_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG8EI16_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4) + .value("PseudoVSUXSEG8EI16_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG8EI16_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1) + .value("PseudoVSUXSEG8EI16_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1_MASK) + .value("PseudoVSUXSEG8EI16_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2) + .value("PseudoVSUXSEG8EI16_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG8EI16_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4) + .value("PseudoVSUXSEG8EI16_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG8EI16_V_MF4_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8) + .value("PseudoVSUXSEG8EI16_V_MF4_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK) + .value("PseudoVSUXSEG8EI32_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1) + .value("PseudoVSUXSEG8EI32_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1_MASK) + .value("PseudoVSUXSEG8EI32_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2) + .value("PseudoVSUXSEG8EI32_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2_MASK) + .value("PseudoVSUXSEG8EI32_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4) + .value("PseudoVSUXSEG8EI32_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4_MASK) + .value("PseudoVSUXSEG8EI32_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1) + .value("PseudoVSUXSEG8EI32_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1_MASK) + .value("PseudoVSUXSEG8EI32_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2) + .value("PseudoVSUXSEG8EI32_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2_MASK) + .value("PseudoVSUXSEG8EI32_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1) + .value("PseudoVSUXSEG8EI32_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1_MASK) + .value("PseudoVSUXSEG8EI32_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1) + .value("PseudoVSUXSEG8EI32_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1_MASK) + .value("PseudoVSUXSEG8EI32_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2) + .value("PseudoVSUXSEG8EI32_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG8EI32_V_MF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4) + .value("PseudoVSUXSEG8EI32_V_MF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK) + .value("PseudoVSUXSEG8EI32_V_MF2_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8) + .value("PseudoVSUXSEG8EI32_V_MF2_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK) + .value("PseudoVSUXSEG8EI64_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1) + .value("PseudoVSUXSEG8EI64_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1_MASK) + .value("PseudoVSUXSEG8EI64_V_M1_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2) + .value("PseudoVSUXSEG8EI64_V_M1_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2_MASK) + .value("PseudoVSUXSEG8EI64_V_M1_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4) + .value("PseudoVSUXSEG8EI64_V_M1_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4_MASK) + .value("PseudoVSUXSEG8EI64_V_M1_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8) + .value("PseudoVSUXSEG8EI64_V_M1_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8_MASK) + .value("PseudoVSUXSEG8EI64_V_M2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1) + .value("PseudoVSUXSEG8EI64_V_M2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1_MASK) + .value("PseudoVSUXSEG8EI64_V_M2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2) + .value("PseudoVSUXSEG8EI64_V_M2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2_MASK) + .value("PseudoVSUXSEG8EI64_V_M2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4) + .value("PseudoVSUXSEG8EI64_V_M2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4_MASK) + .value("PseudoVSUXSEG8EI64_V_M4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1) + .value("PseudoVSUXSEG8EI64_V_M4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1_MASK) + .value("PseudoVSUXSEG8EI64_V_M4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2) + .value("PseudoVSUXSEG8EI64_V_M4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2_MASK) + .value("PseudoVSUXSEG8EI64_V_M8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1) + .value("PseudoVSUXSEG8EI64_V_M8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1_MASK) + .value("PseudoVSUXSEG8EI8_V_M1_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1) + .value("PseudoVSUXSEG8EI8_V_M1_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1_MASK) + .value("PseudoVSUXSEG8EI8_V_MF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1) + .value("PseudoVSUXSEG8EI8_V_MF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1_MASK) + .value("PseudoVSUXSEG8EI8_V_MF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2) + .value("PseudoVSUXSEG8EI8_V_MF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK) + .value("PseudoVSUXSEG8EI8_V_MF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1) + .value("PseudoVSUXSEG8EI8_V_MF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1_MASK) + .value("PseudoVSUXSEG8EI8_V_MF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2) + .value("PseudoVSUXSEG8EI8_V_MF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK) + .value("PseudoVSUXSEG8EI8_V_MF4_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4) + .value("PseudoVSUXSEG8EI8_V_MF4_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK) + .value("PseudoVSUXSEG8EI8_V_MF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1) + .value("PseudoVSUXSEG8EI8_V_MF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1_MASK) + .value("PseudoVSUXSEG8EI8_V_MF8_MF2", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2) + .value("PseudoVSUXSEG8EI8_V_MF8_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK) + .value("PseudoVSUXSEG8EI8_V_MF8_MF4", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4) + .value("PseudoVSUXSEG8EI8_V_MF8_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK) + .value("PseudoVSUXSEG8EI8_V_MF8_MF8", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8) + .value("PseudoVSUXSEG8EI8_V_MF8_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK) + .value("PseudoVWADDU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1) + .value("PseudoVWADDU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1_MASK) + .value("PseudoVWADDU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2) + .value("PseudoVWADDU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2_MASK) + .value("PseudoVWADDU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4) + .value("PseudoVWADDU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4_MASK) + .value("PseudoVWADDU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2) + .value("PseudoVWADDU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2_MASK) + .value("PseudoVWADDU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4) + .value("PseudoVWADDU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4_MASK) + .value("PseudoVWADDU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8) + .value("PseudoVWADDU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8_MASK) + .value("PseudoVWADDU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1) + .value("PseudoVWADDU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1_MASK) + .value("PseudoVWADDU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2) + .value("PseudoVWADDU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2_MASK) + .value("PseudoVWADDU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4) + .value("PseudoVWADDU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4_MASK) + .value("PseudoVWADDU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2) + .value("PseudoVWADDU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2_MASK) + .value("PseudoVWADDU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4) + .value("PseudoVWADDU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4_MASK) + .value("PseudoVWADDU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8) + .value("PseudoVWADDU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8_MASK) + .value("PseudoVWADDU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1) + .value("PseudoVWADDU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK) + .value("PseudoVWADDU_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK_TIED) + .value("PseudoVWADDU_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_TIED) + .value("PseudoVWADDU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2) + .value("PseudoVWADDU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK) + .value("PseudoVWADDU_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK_TIED) + .value("PseudoVWADDU_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_TIED) + .value("PseudoVWADDU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4) + .value("PseudoVWADDU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK) + .value("PseudoVWADDU_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK_TIED) + .value("PseudoVWADDU_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_TIED) + .value("PseudoVWADDU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2) + .value("PseudoVWADDU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK) + .value("PseudoVWADDU_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK_TIED) + .value("PseudoVWADDU_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_TIED) + .value("PseudoVWADDU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4) + .value("PseudoVWADDU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK) + .value("PseudoVWADDU_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK_TIED) + .value("PseudoVWADDU_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_TIED) + .value("PseudoVWADDU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8) + .value("PseudoVWADDU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK) + .value("PseudoVWADDU_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK_TIED) + .value("PseudoVWADDU_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_TIED) + .value("PseudoVWADDU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1) + .value("PseudoVWADDU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1_MASK) + .value("PseudoVWADDU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2) + .value("PseudoVWADDU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2_MASK) + .value("PseudoVWADDU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4) + .value("PseudoVWADDU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4_MASK) + .value("PseudoVWADDU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2) + .value("PseudoVWADDU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2_MASK) + .value("PseudoVWADDU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4) + .value("PseudoVWADDU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4_MASK) + .value("PseudoVWADDU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8) + .value("PseudoVWADDU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8_MASK) + .value("PseudoVWADD_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1) + .value("PseudoVWADD_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1_MASK) + .value("PseudoVWADD_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2) + .value("PseudoVWADD_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2_MASK) + .value("PseudoVWADD_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4) + .value("PseudoVWADD_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4_MASK) + .value("PseudoVWADD_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2) + .value("PseudoVWADD_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2_MASK) + .value("PseudoVWADD_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4) + .value("PseudoVWADD_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4_MASK) + .value("PseudoVWADD_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8) + .value("PseudoVWADD_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8_MASK) + .value("PseudoVWADD_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1) + .value("PseudoVWADD_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1_MASK) + .value("PseudoVWADD_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2) + .value("PseudoVWADD_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2_MASK) + .value("PseudoVWADD_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4) + .value("PseudoVWADD_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4_MASK) + .value("PseudoVWADD_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2) + .value("PseudoVWADD_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2_MASK) + .value("PseudoVWADD_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4) + .value("PseudoVWADD_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4_MASK) + .value("PseudoVWADD_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8) + .value("PseudoVWADD_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8_MASK) + .value("PseudoVWADD_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1) + .value("PseudoVWADD_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK) + .value("PseudoVWADD_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK_TIED) + .value("PseudoVWADD_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_TIED) + .value("PseudoVWADD_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2) + .value("PseudoVWADD_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK) + .value("PseudoVWADD_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK_TIED) + .value("PseudoVWADD_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_TIED) + .value("PseudoVWADD_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4) + .value("PseudoVWADD_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK) + .value("PseudoVWADD_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK_TIED) + .value("PseudoVWADD_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_TIED) + .value("PseudoVWADD_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2) + .value("PseudoVWADD_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK) + .value("PseudoVWADD_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK_TIED) + .value("PseudoVWADD_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_TIED) + .value("PseudoVWADD_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4) + .value("PseudoVWADD_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK) + .value("PseudoVWADD_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK_TIED) + .value("PseudoVWADD_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_TIED) + .value("PseudoVWADD_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8) + .value("PseudoVWADD_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK) + .value("PseudoVWADD_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK_TIED) + .value("PseudoVWADD_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_TIED) + .value("PseudoVWADD_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1) + .value("PseudoVWADD_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1_MASK) + .value("PseudoVWADD_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2) + .value("PseudoVWADD_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2_MASK) + .value("PseudoVWADD_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4) + .value("PseudoVWADD_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4_MASK) + .value("PseudoVWADD_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2) + .value("PseudoVWADD_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2_MASK) + .value("PseudoVWADD_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4) + .value("PseudoVWADD_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4_MASK) + .value("PseudoVWADD_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8) + .value("PseudoVWADD_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8_MASK) + .value("PseudoVWMACCSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1) + .value("PseudoVWMACCSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1_MASK) + .value("PseudoVWMACCSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2) + .value("PseudoVWMACCSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2_MASK) + .value("PseudoVWMACCSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4) + .value("PseudoVWMACCSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4_MASK) + .value("PseudoVWMACCSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2) + .value("PseudoVWMACCSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2_MASK) + .value("PseudoVWMACCSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4) + .value("PseudoVWMACCSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4_MASK) + .value("PseudoVWMACCSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8) + .value("PseudoVWMACCSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8_MASK) + .value("PseudoVWMACCSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1); + opcodes.value("PseudoVWMACCSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1_MASK) + .value("PseudoVWMACCSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2) + .value("PseudoVWMACCSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2_MASK) + .value("PseudoVWMACCSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4) + .value("PseudoVWMACCSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4_MASK) + .value("PseudoVWMACCSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2) + .value("PseudoVWMACCSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2_MASK) + .value("PseudoVWMACCSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4) + .value("PseudoVWMACCSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4_MASK) + .value("PseudoVWMACCSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8) + .value("PseudoVWMACCSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8_MASK) + .value("PseudoVWMACCUS_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1) + .value("PseudoVWMACCUS_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1_MASK) + .value("PseudoVWMACCUS_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2) + .value("PseudoVWMACCUS_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2_MASK) + .value("PseudoVWMACCUS_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4) + .value("PseudoVWMACCUS_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4_MASK) + .value("PseudoVWMACCUS_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2) + .value("PseudoVWMACCUS_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2_MASK) + .value("PseudoVWMACCUS_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4) + .value("PseudoVWMACCUS_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4_MASK) + .value("PseudoVWMACCUS_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8) + .value("PseudoVWMACCUS_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8_MASK) + .value("PseudoVWMACCU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1) + .value("PseudoVWMACCU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1_MASK) + .value("PseudoVWMACCU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2) + .value("PseudoVWMACCU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2_MASK) + .value("PseudoVWMACCU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4) + .value("PseudoVWMACCU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4_MASK) + .value("PseudoVWMACCU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2) + .value("PseudoVWMACCU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2_MASK) + .value("PseudoVWMACCU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4) + .value("PseudoVWMACCU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4_MASK) + .value("PseudoVWMACCU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8) + .value("PseudoVWMACCU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8_MASK) + .value("PseudoVWMACCU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1) + .value("PseudoVWMACCU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1_MASK) + .value("PseudoVWMACCU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2) + .value("PseudoVWMACCU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2_MASK) + .value("PseudoVWMACCU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4) + .value("PseudoVWMACCU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4_MASK) + .value("PseudoVWMACCU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2) + .value("PseudoVWMACCU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2_MASK) + .value("PseudoVWMACCU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4) + .value("PseudoVWMACCU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4_MASK) + .value("PseudoVWMACCU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8) + .value("PseudoVWMACCU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8_MASK) + .value("PseudoVWMACC_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1) + .value("PseudoVWMACC_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1_MASK) + .value("PseudoVWMACC_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2) + .value("PseudoVWMACC_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2_MASK) + .value("PseudoVWMACC_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4) + .value("PseudoVWMACC_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4_MASK) + .value("PseudoVWMACC_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2) + .value("PseudoVWMACC_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2_MASK) + .value("PseudoVWMACC_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4) + .value("PseudoVWMACC_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4_MASK) + .value("PseudoVWMACC_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8) + .value("PseudoVWMACC_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8_MASK) + .value("PseudoVWMACC_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1) + .value("PseudoVWMACC_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1_MASK) + .value("PseudoVWMACC_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2) + .value("PseudoVWMACC_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2_MASK) + .value("PseudoVWMACC_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4) + .value("PseudoVWMACC_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4_MASK) + .value("PseudoVWMACC_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2) + .value("PseudoVWMACC_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2_MASK) + .value("PseudoVWMACC_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4) + .value("PseudoVWMACC_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4_MASK) + .value("PseudoVWMACC_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8) + .value("PseudoVWMACC_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8_MASK) + .value("PseudoVWMULSU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1) + .value("PseudoVWMULSU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1_MASK) + .value("PseudoVWMULSU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2) + .value("PseudoVWMULSU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2_MASK) + .value("PseudoVWMULSU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4) + .value("PseudoVWMULSU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4_MASK) + .value("PseudoVWMULSU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2) + .value("PseudoVWMULSU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2_MASK) + .value("PseudoVWMULSU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4) + .value("PseudoVWMULSU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4_MASK) + .value("PseudoVWMULSU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8) + .value("PseudoVWMULSU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8_MASK) + .value("PseudoVWMULSU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1) + .value("PseudoVWMULSU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1_MASK) + .value("PseudoVWMULSU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2) + .value("PseudoVWMULSU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2_MASK) + .value("PseudoVWMULSU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4) + .value("PseudoVWMULSU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4_MASK) + .value("PseudoVWMULSU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2) + .value("PseudoVWMULSU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2_MASK) + .value("PseudoVWMULSU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4) + .value("PseudoVWMULSU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4_MASK) + .value("PseudoVWMULSU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8) + .value("PseudoVWMULSU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8_MASK) + .value("PseudoVWMULU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1) + .value("PseudoVWMULU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1_MASK) + .value("PseudoVWMULU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2) + .value("PseudoVWMULU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2_MASK) + .value("PseudoVWMULU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4) + .value("PseudoVWMULU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4_MASK) + .value("PseudoVWMULU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2) + .value("PseudoVWMULU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2_MASK) + .value("PseudoVWMULU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4) + .value("PseudoVWMULU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4_MASK) + .value("PseudoVWMULU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8) + .value("PseudoVWMULU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8_MASK) + .value("PseudoVWMULU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1) + .value("PseudoVWMULU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1_MASK) + .value("PseudoVWMULU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2) + .value("PseudoVWMULU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2_MASK) + .value("PseudoVWMULU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4) + .value("PseudoVWMULU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4_MASK) + .value("PseudoVWMULU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2) + .value("PseudoVWMULU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2_MASK) + .value("PseudoVWMULU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4) + .value("PseudoVWMULU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4_MASK) + .value("PseudoVWMULU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8) + .value("PseudoVWMULU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8_MASK) + .value("PseudoVWMUL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1) + .value("PseudoVWMUL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1_MASK) + .value("PseudoVWMUL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2) + .value("PseudoVWMUL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2_MASK) + .value("PseudoVWMUL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4) + .value("PseudoVWMUL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4_MASK) + .value("PseudoVWMUL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2) + .value("PseudoVWMUL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2_MASK) + .value("PseudoVWMUL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4) + .value("PseudoVWMUL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4_MASK) + .value("PseudoVWMUL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8) + .value("PseudoVWMUL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8_MASK) + .value("PseudoVWMUL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1) + .value("PseudoVWMUL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1_MASK) + .value("PseudoVWMUL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2) + .value("PseudoVWMUL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2_MASK) + .value("PseudoVWMUL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4) + .value("PseudoVWMUL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4_MASK) + .value("PseudoVWMUL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2) + .value("PseudoVWMUL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2_MASK) + .value("PseudoVWMUL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4) + .value("PseudoVWMUL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4_MASK) + .value("PseudoVWMUL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8) + .value("PseudoVWMUL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8_MASK) + .value("PseudoVWREDSUMU_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16) + .value("PseudoVWREDSUMU_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16_MASK) + .value("PseudoVWREDSUMU_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32) + .value("PseudoVWREDSUMU_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32_MASK) + .value("PseudoVWREDSUMU_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8) + .value("PseudoVWREDSUMU_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8_MASK) + .value("PseudoVWREDSUMU_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16) + .value("PseudoVWREDSUMU_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16_MASK) + .value("PseudoVWREDSUMU_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32) + .value("PseudoVWREDSUMU_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32_MASK) + .value("PseudoVWREDSUMU_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8) + .value("PseudoVWREDSUMU_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8_MASK) + .value("PseudoVWREDSUMU_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16) + .value("PseudoVWREDSUMU_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16_MASK) + .value("PseudoVWREDSUMU_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32) + .value("PseudoVWREDSUMU_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32_MASK) + .value("PseudoVWREDSUMU_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8) + .value("PseudoVWREDSUMU_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8_MASK) + .value("PseudoVWREDSUMU_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16) + .value("PseudoVWREDSUMU_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16_MASK) + .value("PseudoVWREDSUMU_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32) + .value("PseudoVWREDSUMU_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32_MASK) + .value("PseudoVWREDSUMU_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8) + .value("PseudoVWREDSUMU_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8_MASK) + .value("PseudoVWREDSUMU_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16) + .value("PseudoVWREDSUMU_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16_MASK) + .value("PseudoVWREDSUMU_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32) + .value("PseudoVWREDSUMU_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32_MASK) + .value("PseudoVWREDSUMU_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8) + .value("PseudoVWREDSUMU_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8_MASK) + .value("PseudoVWREDSUMU_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16) + .value("PseudoVWREDSUMU_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16_MASK) + .value("PseudoVWREDSUMU_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8) + .value("PseudoVWREDSUMU_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8_MASK) + .value("PseudoVWREDSUMU_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8) + .value("PseudoVWREDSUMU_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8_MASK) + .value("PseudoVWREDSUM_VS_M1_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16) + .value("PseudoVWREDSUM_VS_M1_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16_MASK) + .value("PseudoVWREDSUM_VS_M1_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32) + .value("PseudoVWREDSUM_VS_M1_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32_MASK) + .value("PseudoVWREDSUM_VS_M1_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8) + .value("PseudoVWREDSUM_VS_M1_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8_MASK) + .value("PseudoVWREDSUM_VS_M2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16) + .value("PseudoVWREDSUM_VS_M2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16_MASK) + .value("PseudoVWREDSUM_VS_M2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32) + .value("PseudoVWREDSUM_VS_M2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32_MASK) + .value("PseudoVWREDSUM_VS_M2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8) + .value("PseudoVWREDSUM_VS_M2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8_MASK) + .value("PseudoVWREDSUM_VS_M4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16) + .value("PseudoVWREDSUM_VS_M4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16_MASK) + .value("PseudoVWREDSUM_VS_M4_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32) + .value("PseudoVWREDSUM_VS_M4_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32_MASK) + .value("PseudoVWREDSUM_VS_M4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8) + .value("PseudoVWREDSUM_VS_M4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8_MASK) + .value("PseudoVWREDSUM_VS_M8_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16) + .value("PseudoVWREDSUM_VS_M8_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16_MASK) + .value("PseudoVWREDSUM_VS_M8_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32) + .value("PseudoVWREDSUM_VS_M8_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32_MASK) + .value("PseudoVWREDSUM_VS_M8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8) + .value("PseudoVWREDSUM_VS_M8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8_MASK) + .value("PseudoVWREDSUM_VS_MF2_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16) + .value("PseudoVWREDSUM_VS_MF2_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16_MASK) + .value("PseudoVWREDSUM_VS_MF2_E32", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32) + .value("PseudoVWREDSUM_VS_MF2_E32_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32_MASK) + .value("PseudoVWREDSUM_VS_MF2_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8) + .value("PseudoVWREDSUM_VS_MF2_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8_MASK) + .value("PseudoVWREDSUM_VS_MF4_E16", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16) + .value("PseudoVWREDSUM_VS_MF4_E16_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16_MASK) + .value("PseudoVWREDSUM_VS_MF4_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8) + .value("PseudoVWREDSUM_VS_MF4_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8_MASK) + .value("PseudoVWREDSUM_VS_MF8_E8", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8) + .value("PseudoVWREDSUM_VS_MF8_E8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8_MASK) + .value("PseudoVWSLL_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1) + .value("PseudoVWSLL_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1_MASK) + .value("PseudoVWSLL_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2) + .value("PseudoVWSLL_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2_MASK) + .value("PseudoVWSLL_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4) + .value("PseudoVWSLL_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4_MASK) + .value("PseudoVWSLL_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2) + .value("PseudoVWSLL_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2_MASK) + .value("PseudoVWSLL_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4) + .value("PseudoVWSLL_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4_MASK) + .value("PseudoVWSLL_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8) + .value("PseudoVWSLL_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8_MASK) + .value("PseudoVWSLL_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1) + .value("PseudoVWSLL_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1_MASK) + .value("PseudoVWSLL_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2) + .value("PseudoVWSLL_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2_MASK) + .value("PseudoVWSLL_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4) + .value("PseudoVWSLL_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4_MASK) + .value("PseudoVWSLL_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2) + .value("PseudoVWSLL_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2_MASK) + .value("PseudoVWSLL_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4) + .value("PseudoVWSLL_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4_MASK) + .value("PseudoVWSLL_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8) + .value("PseudoVWSLL_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8_MASK) + .value("PseudoVWSLL_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1) + .value("PseudoVWSLL_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1_MASK) + .value("PseudoVWSLL_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2) + .value("PseudoVWSLL_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2_MASK) + .value("PseudoVWSLL_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4) + .value("PseudoVWSLL_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4_MASK) + .value("PseudoVWSLL_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2) + .value("PseudoVWSLL_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2_MASK) + .value("PseudoVWSLL_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4) + .value("PseudoVWSLL_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4_MASK) + .value("PseudoVWSLL_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8) + .value("PseudoVWSLL_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8_MASK) + .value("PseudoVWSUBU_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1) + .value("PseudoVWSUBU_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1_MASK) + .value("PseudoVWSUBU_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2) + .value("PseudoVWSUBU_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2_MASK) + .value("PseudoVWSUBU_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4) + .value("PseudoVWSUBU_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4_MASK) + .value("PseudoVWSUBU_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2) + .value("PseudoVWSUBU_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2_MASK) + .value("PseudoVWSUBU_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4) + .value("PseudoVWSUBU_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4_MASK) + .value("PseudoVWSUBU_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8) + .value("PseudoVWSUBU_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8_MASK) + .value("PseudoVWSUBU_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1) + .value("PseudoVWSUBU_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1_MASK) + .value("PseudoVWSUBU_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2) + .value("PseudoVWSUBU_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2_MASK) + .value("PseudoVWSUBU_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4) + .value("PseudoVWSUBU_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4_MASK) + .value("PseudoVWSUBU_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2) + .value("PseudoVWSUBU_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2_MASK) + .value("PseudoVWSUBU_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4) + .value("PseudoVWSUBU_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4_MASK) + .value("PseudoVWSUBU_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8) + .value("PseudoVWSUBU_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8_MASK) + .value("PseudoVWSUBU_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1) + .value("PseudoVWSUBU_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK) + .value("PseudoVWSUBU_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK_TIED) + .value("PseudoVWSUBU_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_TIED) + .value("PseudoVWSUBU_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2) + .value("PseudoVWSUBU_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK) + .value("PseudoVWSUBU_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK_TIED) + .value("PseudoVWSUBU_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_TIED) + .value("PseudoVWSUBU_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4) + .value("PseudoVWSUBU_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK) + .value("PseudoVWSUBU_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK_TIED) + .value("PseudoVWSUBU_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_TIED) + .value("PseudoVWSUBU_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2) + .value("PseudoVWSUBU_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK) + .value("PseudoVWSUBU_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK_TIED) + .value("PseudoVWSUBU_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_TIED) + .value("PseudoVWSUBU_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4) + .value("PseudoVWSUBU_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK) + .value("PseudoVWSUBU_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK_TIED) + .value("PseudoVWSUBU_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_TIED) + .value("PseudoVWSUBU_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8) + .value("PseudoVWSUBU_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK) + .value("PseudoVWSUBU_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK_TIED) + .value("PseudoVWSUBU_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_TIED) + .value("PseudoVWSUBU_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1); + opcodes.value("PseudoVWSUBU_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1_MASK) + .value("PseudoVWSUBU_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2) + .value("PseudoVWSUBU_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2_MASK) + .value("PseudoVWSUBU_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4) + .value("PseudoVWSUBU_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4_MASK) + .value("PseudoVWSUBU_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2) + .value("PseudoVWSUBU_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2_MASK) + .value("PseudoVWSUBU_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4) + .value("PseudoVWSUBU_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4_MASK) + .value("PseudoVWSUBU_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8) + .value("PseudoVWSUBU_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8_MASK) + .value("PseudoVWSUB_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1) + .value("PseudoVWSUB_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1_MASK) + .value("PseudoVWSUB_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2) + .value("PseudoVWSUB_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2_MASK) + .value("PseudoVWSUB_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4) + .value("PseudoVWSUB_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4_MASK) + .value("PseudoVWSUB_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2) + .value("PseudoVWSUB_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2_MASK) + .value("PseudoVWSUB_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4) + .value("PseudoVWSUB_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4_MASK) + .value("PseudoVWSUB_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8) + .value("PseudoVWSUB_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8_MASK) + .value("PseudoVWSUB_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1) + .value("PseudoVWSUB_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1_MASK) + .value("PseudoVWSUB_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2) + .value("PseudoVWSUB_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2_MASK) + .value("PseudoVWSUB_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4) + .value("PseudoVWSUB_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4_MASK) + .value("PseudoVWSUB_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2) + .value("PseudoVWSUB_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2_MASK) + .value("PseudoVWSUB_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4) + .value("PseudoVWSUB_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4_MASK) + .value("PseudoVWSUB_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8) + .value("PseudoVWSUB_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8_MASK) + .value("PseudoVWSUB_WV_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1) + .value("PseudoVWSUB_WV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK) + .value("PseudoVWSUB_WV_M1_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK_TIED) + .value("PseudoVWSUB_WV_M1_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_TIED) + .value("PseudoVWSUB_WV_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2) + .value("PseudoVWSUB_WV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK) + .value("PseudoVWSUB_WV_M2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK_TIED) + .value("PseudoVWSUB_WV_M2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_TIED) + .value("PseudoVWSUB_WV_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4) + .value("PseudoVWSUB_WV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK) + .value("PseudoVWSUB_WV_M4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK_TIED) + .value("PseudoVWSUB_WV_M4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_TIED) + .value("PseudoVWSUB_WV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2) + .value("PseudoVWSUB_WV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK) + .value("PseudoVWSUB_WV_MF2_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK_TIED) + .value("PseudoVWSUB_WV_MF2_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_TIED) + .value("PseudoVWSUB_WV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4) + .value("PseudoVWSUB_WV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK) + .value("PseudoVWSUB_WV_MF4_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK_TIED) + .value("PseudoVWSUB_WV_MF4_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_TIED) + .value("PseudoVWSUB_WV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8) + .value("PseudoVWSUB_WV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK) + .value("PseudoVWSUB_WV_MF8_MASK_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK_TIED) + .value("PseudoVWSUB_WV_MF8_TIED", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_TIED) + .value("PseudoVWSUB_WX_M1", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1) + .value("PseudoVWSUB_WX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1_MASK) + .value("PseudoVWSUB_WX_M2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2) + .value("PseudoVWSUB_WX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2_MASK) + .value("PseudoVWSUB_WX_M4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4) + .value("PseudoVWSUB_WX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4_MASK) + .value("PseudoVWSUB_WX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2) + .value("PseudoVWSUB_WX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2_MASK) + .value("PseudoVWSUB_WX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4) + .value("PseudoVWSUB_WX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4_MASK) + .value("PseudoVWSUB_WX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8) + .value("PseudoVWSUB_WX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8_MASK) + .value("PseudoVXOR_VI_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1) + .value("PseudoVXOR_VI_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1_MASK) + .value("PseudoVXOR_VI_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2) + .value("PseudoVXOR_VI_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2_MASK) + .value("PseudoVXOR_VI_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4) + .value("PseudoVXOR_VI_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4_MASK) + .value("PseudoVXOR_VI_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8) + .value("PseudoVXOR_VI_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8_MASK) + .value("PseudoVXOR_VI_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2) + .value("PseudoVXOR_VI_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2_MASK) + .value("PseudoVXOR_VI_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4) + .value("PseudoVXOR_VI_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4_MASK) + .value("PseudoVXOR_VI_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8) + .value("PseudoVXOR_VI_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8_MASK) + .value("PseudoVXOR_VV_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1) + .value("PseudoVXOR_VV_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1_MASK) + .value("PseudoVXOR_VV_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2) + .value("PseudoVXOR_VV_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2_MASK) + .value("PseudoVXOR_VV_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4) + .value("PseudoVXOR_VV_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4_MASK) + .value("PseudoVXOR_VV_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8) + .value("PseudoVXOR_VV_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8_MASK) + .value("PseudoVXOR_VV_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2) + .value("PseudoVXOR_VV_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2_MASK) + .value("PseudoVXOR_VV_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4) + .value("PseudoVXOR_VV_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4_MASK) + .value("PseudoVXOR_VV_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8) + .value("PseudoVXOR_VV_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8_MASK) + .value("PseudoVXOR_VX_M1", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1) + .value("PseudoVXOR_VX_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1_MASK) + .value("PseudoVXOR_VX_M2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2) + .value("PseudoVXOR_VX_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2_MASK) + .value("PseudoVXOR_VX_M4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4) + .value("PseudoVXOR_VX_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4_MASK) + .value("PseudoVXOR_VX_M8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8) + .value("PseudoVXOR_VX_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8_MASK) + .value("PseudoVXOR_VX_MF2", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2) + .value("PseudoVXOR_VX_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2_MASK) + .value("PseudoVXOR_VX_MF4", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4) + .value("PseudoVXOR_VX_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4_MASK) + .value("PseudoVXOR_VX_MF8", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8) + .value("PseudoVXOR_VX_MF8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8_MASK) + .value("PseudoVZEXT_VF2_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1) + .value("PseudoVZEXT_VF2_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1_MASK) + .value("PseudoVZEXT_VF2_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2) + .value("PseudoVZEXT_VF2_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2_MASK) + .value("PseudoVZEXT_VF2_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4) + .value("PseudoVZEXT_VF2_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4_MASK) + .value("PseudoVZEXT_VF2_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8) + .value("PseudoVZEXT_VF2_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8_MASK) + .value("PseudoVZEXT_VF2_MF2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2) + .value("PseudoVZEXT_VF2_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2_MASK) + .value("PseudoVZEXT_VF2_MF4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4) + .value("PseudoVZEXT_VF2_MF4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4_MASK) + .value("PseudoVZEXT_VF4_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1) + .value("PseudoVZEXT_VF4_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1_MASK) + .value("PseudoVZEXT_VF4_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2) + .value("PseudoVZEXT_VF4_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2_MASK) + .value("PseudoVZEXT_VF4_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4) + .value("PseudoVZEXT_VF4_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4_MASK) + .value("PseudoVZEXT_VF4_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8) + .value("PseudoVZEXT_VF4_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8_MASK) + .value("PseudoVZEXT_VF4_MF2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2) + .value("PseudoVZEXT_VF4_MF2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2_MASK) + .value("PseudoVZEXT_VF8_M1", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1) + .value("PseudoVZEXT_VF8_M1_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1_MASK) + .value("PseudoVZEXT_VF8_M2", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2) + .value("PseudoVZEXT_VF8_M2_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2_MASK) + .value("PseudoVZEXT_VF8_M4", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4) + .value("PseudoVZEXT_VF8_M4_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4_MASK) + .value("PseudoVZEXT_VF8_M8", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8) + .value("PseudoVZEXT_VF8_M8_MASK", LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8_MASK) + .value("PseudoZEXT_H", LIEF::assembly::riscv::OPCODE::PseudoZEXT_H) + .value("PseudoZEXT_W", LIEF::assembly::riscv::OPCODE::PseudoZEXT_W) + .value("ReadCounterWide", LIEF::assembly::riscv::OPCODE::ReadCounterWide) + .value("ReadFCSR", LIEF::assembly::riscv::OPCODE::ReadFCSR) + .value("ReadFFLAGS", LIEF::assembly::riscv::OPCODE::ReadFFLAGS) + .value("ReadFRM", LIEF::assembly::riscv::OPCODE::ReadFRM) + .value("Select_FPR16INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR16INX_Using_CC_GPR) + .value("Select_FPR16_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR16_Using_CC_GPR) + .value("Select_FPR32INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR32INX_Using_CC_GPR) + .value("Select_FPR32_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR32_Using_CC_GPR) + .value("Select_FPR64IN32X_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64IN32X_Using_CC_GPR) + .value("Select_FPR64INX_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64INX_Using_CC_GPR) + .value("Select_FPR64_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_FPR64_Using_CC_GPR) + .value("Select_GPRNoX0_Using_CC_SImm16NonZero_QC", LIEF::assembly::riscv::OPCODE::Select_GPRNoX0_Using_CC_SImm16NonZero_QC) + .value("Select_GPRNoX0_Using_CC_SImm5NonZero_QC", LIEF::assembly::riscv::OPCODE::Select_GPRNoX0_Using_CC_SImm5NonZero_QC) + .value("Select_GPRNoX0_Using_CC_UImm16NonZero_QC", LIEF::assembly::riscv::OPCODE::Select_GPRNoX0_Using_CC_UImm16NonZero_QC) + .value("Select_GPRNoX0_Using_CC_UImm5NonZero_QC", LIEF::assembly::riscv::OPCODE::Select_GPRNoX0_Using_CC_UImm5NonZero_QC) + .value("Select_GPR_Using_CC_GPR", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_GPR) + .value("Select_GPR_Using_CC_Imm5_Zibi", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_Imm5_Zibi) + .value("Select_GPR_Using_CC_SImm5_CV", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_SImm5_CV) + .value("Select_GPR_Using_CC_UImm7_NDS", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_UImm7_NDS) + .value("Select_GPR_Using_CC_UImmLog2XLen_NDS", LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_UImmLog2XLen_NDS) + .value("SetFCSR", LIEF::assembly::riscv::OPCODE::SetFCSR) + .value("SetFCSRImm", LIEF::assembly::riscv::OPCODE::SetFCSRImm) + .value("SplitF64Pseudo", LIEF::assembly::riscv::OPCODE::SplitF64Pseudo) + .value("SwapFRMImm", LIEF::assembly::riscv::OPCODE::SwapFRMImm) + .value("WriteFCSR", LIEF::assembly::riscv::OPCODE::WriteFCSR) + .value("WriteFCSRImm", LIEF::assembly::riscv::OPCODE::WriteFCSRImm) + .value("WriteFFLAGS", LIEF::assembly::riscv::OPCODE::WriteFFLAGS) + .value("WriteFRM", LIEF::assembly::riscv::OPCODE::WriteFRM) + .value("WriteFRMImm", LIEF::assembly::riscv::OPCODE::WriteFRMImm) + .value("WriteVXRMImm", LIEF::assembly::riscv::OPCODE::WriteVXRMImm) + .value("AADD", LIEF::assembly::riscv::OPCODE::AADD) + .value("AADDU", LIEF::assembly::riscv::OPCODE::AADDU) + .value("ABS", LIEF::assembly::riscv::OPCODE::ABS) + .value("ABSW", LIEF::assembly::riscv::OPCODE::ABSW) + .value("ADD", LIEF::assembly::riscv::OPCODE::ADD) + .value("ADDD", LIEF::assembly::riscv::OPCODE::ADDD) + .value("ADDI", LIEF::assembly::riscv::OPCODE::ADDI) + .value("ADDIW", LIEF::assembly::riscv::OPCODE::ADDIW) + .value("ADDW", LIEF::assembly::riscv::OPCODE::ADDW) + .value("ADD_UW", LIEF::assembly::riscv::OPCODE::ADD_UW) + .value("AES32DSI", LIEF::assembly::riscv::OPCODE::AES32DSI) + .value("AES32DSMI", LIEF::assembly::riscv::OPCODE::AES32DSMI) + .value("AES32ESI", LIEF::assembly::riscv::OPCODE::AES32ESI) + .value("AES32ESMI", LIEF::assembly::riscv::OPCODE::AES32ESMI) + .value("AES64DS", LIEF::assembly::riscv::OPCODE::AES64DS) + .value("AES64DSM", LIEF::assembly::riscv::OPCODE::AES64DSM) + .value("AES64ES", LIEF::assembly::riscv::OPCODE::AES64ES) + .value("AES64ESM", LIEF::assembly::riscv::OPCODE::AES64ESM) + .value("AES64IM", LIEF::assembly::riscv::OPCODE::AES64IM) + .value("AES64KS1I", LIEF::assembly::riscv::OPCODE::AES64KS1I) + .value("AES64KS2", LIEF::assembly::riscv::OPCODE::AES64KS2) + .value("AMOADD_B", LIEF::assembly::riscv::OPCODE::AMOADD_B) + .value("AMOADD_B_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_B_AQ) + .value("AMOADD_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOADD_B_AQRL) + .value("AMOADD_B_RL", LIEF::assembly::riscv::OPCODE::AMOADD_B_RL) + .value("AMOADD_D", LIEF::assembly::riscv::OPCODE::AMOADD_D) + .value("AMOADD_D_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_D_AQ) + .value("AMOADD_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOADD_D_AQRL) + .value("AMOADD_D_RL", LIEF::assembly::riscv::OPCODE::AMOADD_D_RL) + .value("AMOADD_H", LIEF::assembly::riscv::OPCODE::AMOADD_H) + .value("AMOADD_H_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_H_AQ) + .value("AMOADD_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOADD_H_AQRL) + .value("AMOADD_H_RL", LIEF::assembly::riscv::OPCODE::AMOADD_H_RL) + .value("AMOADD_W", LIEF::assembly::riscv::OPCODE::AMOADD_W) + .value("AMOADD_W_AQ", LIEF::assembly::riscv::OPCODE::AMOADD_W_AQ) + .value("AMOADD_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOADD_W_AQRL) + .value("AMOADD_W_RL", LIEF::assembly::riscv::OPCODE::AMOADD_W_RL) + .value("AMOAND_B", LIEF::assembly::riscv::OPCODE::AMOAND_B) + .value("AMOAND_B_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_B_AQ) + .value("AMOAND_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOAND_B_AQRL) + .value("AMOAND_B_RL", LIEF::assembly::riscv::OPCODE::AMOAND_B_RL) + .value("AMOAND_D", LIEF::assembly::riscv::OPCODE::AMOAND_D) + .value("AMOAND_D_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_D_AQ) + .value("AMOAND_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOAND_D_AQRL) + .value("AMOAND_D_RL", LIEF::assembly::riscv::OPCODE::AMOAND_D_RL) + .value("AMOAND_H", LIEF::assembly::riscv::OPCODE::AMOAND_H) + .value("AMOAND_H_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_H_AQ) + .value("AMOAND_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOAND_H_AQRL) + .value("AMOAND_H_RL", LIEF::assembly::riscv::OPCODE::AMOAND_H_RL) + .value("AMOAND_W", LIEF::assembly::riscv::OPCODE::AMOAND_W) + .value("AMOAND_W_AQ", LIEF::assembly::riscv::OPCODE::AMOAND_W_AQ) + .value("AMOAND_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOAND_W_AQRL) + .value("AMOAND_W_RL", LIEF::assembly::riscv::OPCODE::AMOAND_W_RL) + .value("AMOCAS_B", LIEF::assembly::riscv::OPCODE::AMOCAS_B) + .value("AMOCAS_B_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQ) + .value("AMOCAS_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQRL) + .value("AMOCAS_B_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_B_RL) + .value("AMOCAS_D_RV32", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32) + .value("AMOCAS_D_RV32_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQ) + .value("AMOCAS_D_RV32_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQRL) + .value("AMOCAS_D_RV32_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_RL) + .value("AMOCAS_D_RV64", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64) + .value("AMOCAS_D_RV64_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQ) + .value("AMOCAS_D_RV64_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQRL) + .value("AMOCAS_D_RV64_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_RL) + .value("AMOCAS_H", LIEF::assembly::riscv::OPCODE::AMOCAS_H) + .value("AMOCAS_H_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQ) + .value("AMOCAS_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQRL) + .value("AMOCAS_H_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_H_RL) + .value("AMOCAS_Q", LIEF::assembly::riscv::OPCODE::AMOCAS_Q) + .value("AMOCAS_Q_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQ) + .value("AMOCAS_Q_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQRL) + .value("AMOCAS_Q_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_Q_RL) + .value("AMOCAS_W", LIEF::assembly::riscv::OPCODE::AMOCAS_W) + .value("AMOCAS_W_AQ", LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQ) + .value("AMOCAS_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQRL) + .value("AMOCAS_W_RL", LIEF::assembly::riscv::OPCODE::AMOCAS_W_RL) + .value("AMOMAXU_B", LIEF::assembly::riscv::OPCODE::AMOMAXU_B) + .value("AMOMAXU_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQ) + .value("AMOMAXU_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQRL) + .value("AMOMAXU_B_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_B_RL) + .value("AMOMAXU_D", LIEF::assembly::riscv::OPCODE::AMOMAXU_D) + .value("AMOMAXU_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQ) + .value("AMOMAXU_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQRL) + .value("AMOMAXU_D_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_D_RL) + .value("AMOMAXU_H", LIEF::assembly::riscv::OPCODE::AMOMAXU_H) + .value("AMOMAXU_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQ) + .value("AMOMAXU_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQRL) + .value("AMOMAXU_H_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_H_RL) + .value("AMOMAXU_W", LIEF::assembly::riscv::OPCODE::AMOMAXU_W) + .value("AMOMAXU_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQ) + .value("AMOMAXU_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQRL) + .value("AMOMAXU_W_RL", LIEF::assembly::riscv::OPCODE::AMOMAXU_W_RL) + .value("AMOMAX_B", LIEF::assembly::riscv::OPCODE::AMOMAX_B) + .value("AMOMAX_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQ) + .value("AMOMAX_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQRL) + .value("AMOMAX_B_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_B_RL) + .value("AMOMAX_D", LIEF::assembly::riscv::OPCODE::AMOMAX_D) + .value("AMOMAX_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQ) + .value("AMOMAX_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQRL) + .value("AMOMAX_D_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_D_RL) + .value("AMOMAX_H", LIEF::assembly::riscv::OPCODE::AMOMAX_H) + .value("AMOMAX_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQ) + .value("AMOMAX_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQRL) + .value("AMOMAX_H_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_H_RL) + .value("AMOMAX_W", LIEF::assembly::riscv::OPCODE::AMOMAX_W) + .value("AMOMAX_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQ) + .value("AMOMAX_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQRL) + .value("AMOMAX_W_RL", LIEF::assembly::riscv::OPCODE::AMOMAX_W_RL) + .value("AMOMINU_B", LIEF::assembly::riscv::OPCODE::AMOMINU_B) + .value("AMOMINU_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQ) + .value("AMOMINU_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQRL) + .value("AMOMINU_B_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_B_RL) + .value("AMOMINU_D", LIEF::assembly::riscv::OPCODE::AMOMINU_D) + .value("AMOMINU_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQ) + .value("AMOMINU_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQRL) + .value("AMOMINU_D_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_D_RL) + .value("AMOMINU_H", LIEF::assembly::riscv::OPCODE::AMOMINU_H) + .value("AMOMINU_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQ) + .value("AMOMINU_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQRL) + .value("AMOMINU_H_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_H_RL) + .value("AMOMINU_W", LIEF::assembly::riscv::OPCODE::AMOMINU_W) + .value("AMOMINU_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQ) + .value("AMOMINU_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQRL) + .value("AMOMINU_W_RL", LIEF::assembly::riscv::OPCODE::AMOMINU_W_RL); + opcodes.value("AMOMIN_B", LIEF::assembly::riscv::OPCODE::AMOMIN_B) + .value("AMOMIN_B_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQ) + .value("AMOMIN_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQRL) + .value("AMOMIN_B_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_B_RL) + .value("AMOMIN_D", LIEF::assembly::riscv::OPCODE::AMOMIN_D) + .value("AMOMIN_D_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQ) + .value("AMOMIN_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQRL) + .value("AMOMIN_D_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_D_RL) + .value("AMOMIN_H", LIEF::assembly::riscv::OPCODE::AMOMIN_H) + .value("AMOMIN_H_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQ) + .value("AMOMIN_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQRL) + .value("AMOMIN_H_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_H_RL) + .value("AMOMIN_W", LIEF::assembly::riscv::OPCODE::AMOMIN_W) + .value("AMOMIN_W_AQ", LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQ) + .value("AMOMIN_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQRL) + .value("AMOMIN_W_RL", LIEF::assembly::riscv::OPCODE::AMOMIN_W_RL) + .value("AMOOR_B", LIEF::assembly::riscv::OPCODE::AMOOR_B) + .value("AMOOR_B_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_B_AQ) + .value("AMOOR_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOOR_B_AQRL) + .value("AMOOR_B_RL", LIEF::assembly::riscv::OPCODE::AMOOR_B_RL) + .value("AMOOR_D", LIEF::assembly::riscv::OPCODE::AMOOR_D) + .value("AMOOR_D_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_D_AQ) + .value("AMOOR_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOOR_D_AQRL) + .value("AMOOR_D_RL", LIEF::assembly::riscv::OPCODE::AMOOR_D_RL) + .value("AMOOR_H", LIEF::assembly::riscv::OPCODE::AMOOR_H) + .value("AMOOR_H_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_H_AQ) + .value("AMOOR_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOOR_H_AQRL) + .value("AMOOR_H_RL", LIEF::assembly::riscv::OPCODE::AMOOR_H_RL) + .value("AMOOR_W", LIEF::assembly::riscv::OPCODE::AMOOR_W) + .value("AMOOR_W_AQ", LIEF::assembly::riscv::OPCODE::AMOOR_W_AQ) + .value("AMOOR_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOOR_W_AQRL) + .value("AMOOR_W_RL", LIEF::assembly::riscv::OPCODE::AMOOR_W_RL) + .value("AMOSWAP_B", LIEF::assembly::riscv::OPCODE::AMOSWAP_B) + .value("AMOSWAP_B_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQ) + .value("AMOSWAP_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQRL) + .value("AMOSWAP_B_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_B_RL) + .value("AMOSWAP_D", LIEF::assembly::riscv::OPCODE::AMOSWAP_D) + .value("AMOSWAP_D_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQ) + .value("AMOSWAP_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQRL) + .value("AMOSWAP_D_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_D_RL) + .value("AMOSWAP_H", LIEF::assembly::riscv::OPCODE::AMOSWAP_H) + .value("AMOSWAP_H_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQ) + .value("AMOSWAP_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQRL) + .value("AMOSWAP_H_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_H_RL) + .value("AMOSWAP_W", LIEF::assembly::riscv::OPCODE::AMOSWAP_W) + .value("AMOSWAP_W_AQ", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQ) + .value("AMOSWAP_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQRL) + .value("AMOSWAP_W_RL", LIEF::assembly::riscv::OPCODE::AMOSWAP_W_RL) + .value("AMOXOR_B", LIEF::assembly::riscv::OPCODE::AMOXOR_B) + .value("AMOXOR_B_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQ) + .value("AMOXOR_B_AQRL", LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQRL) + .value("AMOXOR_B_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_B_RL) + .value("AMOXOR_D", LIEF::assembly::riscv::OPCODE::AMOXOR_D) + .value("AMOXOR_D_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQ) + .value("AMOXOR_D_AQRL", LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQRL) + .value("AMOXOR_D_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_D_RL) + .value("AMOXOR_H", LIEF::assembly::riscv::OPCODE::AMOXOR_H) + .value("AMOXOR_H_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQ) + .value("AMOXOR_H_AQRL", LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQRL) + .value("AMOXOR_H_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_H_RL) + .value("AMOXOR_W", LIEF::assembly::riscv::OPCODE::AMOXOR_W) + .value("AMOXOR_W_AQ", LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQ) + .value("AMOXOR_W_AQRL", LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQRL) + .value("AMOXOR_W_RL", LIEF::assembly::riscv::OPCODE::AMOXOR_W_RL) + .value("AND", LIEF::assembly::riscv::OPCODE::AND) + .value("ANDI", LIEF::assembly::riscv::OPCODE::ANDI) + .value("ANDN", LIEF::assembly::riscv::OPCODE::ANDN) + .value("ASUB", LIEF::assembly::riscv::OPCODE::ASUB) + .value("ASUBU", LIEF::assembly::riscv::OPCODE::ASUBU) + .value("AUIPC", LIEF::assembly::riscv::OPCODE::AUIPC) + .value("BCLR", LIEF::assembly::riscv::OPCODE::BCLR) + .value("BCLRI", LIEF::assembly::riscv::OPCODE::BCLRI) + .value("BEQ", LIEF::assembly::riscv::OPCODE::BEQ) + .value("BEQI", LIEF::assembly::riscv::OPCODE::BEQI) + .value("BEXT", LIEF::assembly::riscv::OPCODE::BEXT) + .value("BEXTI", LIEF::assembly::riscv::OPCODE::BEXTI) + .value("BGE", LIEF::assembly::riscv::OPCODE::BGE) + .value("BGEU", LIEF::assembly::riscv::OPCODE::BGEU) + .value("BINV", LIEF::assembly::riscv::OPCODE::BINV) + .value("BINVI", LIEF::assembly::riscv::OPCODE::BINVI) + .value("BLT", LIEF::assembly::riscv::OPCODE::BLT) + .value("BLTU", LIEF::assembly::riscv::OPCODE::BLTU) + .value("BNE", LIEF::assembly::riscv::OPCODE::BNE) + .value("BNEI", LIEF::assembly::riscv::OPCODE::BNEI) + .value("BREV8", LIEF::assembly::riscv::OPCODE::BREV8) + .value("BSET", LIEF::assembly::riscv::OPCODE::BSET) + .value("BSETI", LIEF::assembly::riscv::OPCODE::BSETI) + .value("CBO_CLEAN", LIEF::assembly::riscv::OPCODE::CBO_CLEAN) + .value("CBO_FLUSH", LIEF::assembly::riscv::OPCODE::CBO_FLUSH) + .value("CBO_INVAL", LIEF::assembly::riscv::OPCODE::CBO_INVAL) + .value("CBO_ZERO", LIEF::assembly::riscv::OPCODE::CBO_ZERO) + .value("CLMUL", LIEF::assembly::riscv::OPCODE::CLMUL) + .value("CLMULH", LIEF::assembly::riscv::OPCODE::CLMULH) + .value("CLMULR", LIEF::assembly::riscv::OPCODE::CLMULR) + .value("CLS", LIEF::assembly::riscv::OPCODE::CLS) + .value("CLSW", LIEF::assembly::riscv::OPCODE::CLSW) + .value("CLZ", LIEF::assembly::riscv::OPCODE::CLZ) + .value("CLZW", LIEF::assembly::riscv::OPCODE::CLZW) + .value("CM_JALT", LIEF::assembly::riscv::OPCODE::CM_JALT) + .value("CM_JT", LIEF::assembly::riscv::OPCODE::CM_JT) + .value("CM_MVA01S", LIEF::assembly::riscv::OPCODE::CM_MVA01S) + .value("CM_MVSA01", LIEF::assembly::riscv::OPCODE::CM_MVSA01) + .value("CM_POP", LIEF::assembly::riscv::OPCODE::CM_POP) + .value("CM_POPRET", LIEF::assembly::riscv::OPCODE::CM_POPRET) + .value("CM_POPRETZ", LIEF::assembly::riscv::OPCODE::CM_POPRETZ) + .value("CM_PUSH", LIEF::assembly::riscv::OPCODE::CM_PUSH) + .value("CPOP", LIEF::assembly::riscv::OPCODE::CPOP) + .value("CPOPW", LIEF::assembly::riscv::OPCODE::CPOPW) + .value("CSRRC", LIEF::assembly::riscv::OPCODE::CSRRC) + .value("CSRRCI", LIEF::assembly::riscv::OPCODE::CSRRCI) + .value("CSRRS", LIEF::assembly::riscv::OPCODE::CSRRS) + .value("CSRRSI", LIEF::assembly::riscv::OPCODE::CSRRSI) + .value("CSRRW", LIEF::assembly::riscv::OPCODE::CSRRW) + .value("CSRRWI", LIEF::assembly::riscv::OPCODE::CSRRWI) + .value("CTZ", LIEF::assembly::riscv::OPCODE::CTZ) + .value("CTZW", LIEF::assembly::riscv::OPCODE::CTZW) + .value("CV_ABS", LIEF::assembly::riscv::OPCODE::CV_ABS) + .value("CV_ABS_B", LIEF::assembly::riscv::OPCODE::CV_ABS_B) + .value("CV_ABS_H", LIEF::assembly::riscv::OPCODE::CV_ABS_H) + .value("CV_ADDN", LIEF::assembly::riscv::OPCODE::CV_ADDN) + .value("CV_ADDNR", LIEF::assembly::riscv::OPCODE::CV_ADDNR) + .value("CV_ADDRN", LIEF::assembly::riscv::OPCODE::CV_ADDRN) + .value("CV_ADDRNR", LIEF::assembly::riscv::OPCODE::CV_ADDRNR) + .value("CV_ADDUN", LIEF::assembly::riscv::OPCODE::CV_ADDUN) + .value("CV_ADDUNR", LIEF::assembly::riscv::OPCODE::CV_ADDUNR) + .value("CV_ADDURN", LIEF::assembly::riscv::OPCODE::CV_ADDURN) + .value("CV_ADDURNR", LIEF::assembly::riscv::OPCODE::CV_ADDURNR) + .value("CV_ADD_B", LIEF::assembly::riscv::OPCODE::CV_ADD_B) + .value("CV_ADD_DIV2", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV2) + .value("CV_ADD_DIV4", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV4) + .value("CV_ADD_DIV8", LIEF::assembly::riscv::OPCODE::CV_ADD_DIV8) + .value("CV_ADD_H", LIEF::assembly::riscv::OPCODE::CV_ADD_H) + .value("CV_ADD_SCI_B", LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_B) + .value("CV_ADD_SCI_H", LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_H) + .value("CV_ADD_SC_B", LIEF::assembly::riscv::OPCODE::CV_ADD_SC_B) + .value("CV_ADD_SC_H", LIEF::assembly::riscv::OPCODE::CV_ADD_SC_H) + .value("CV_AND_B", LIEF::assembly::riscv::OPCODE::CV_AND_B) + .value("CV_AND_H", LIEF::assembly::riscv::OPCODE::CV_AND_H) + .value("CV_AND_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AND_SCI_B) + .value("CV_AND_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AND_SCI_H) + .value("CV_AND_SC_B", LIEF::assembly::riscv::OPCODE::CV_AND_SC_B) + .value("CV_AND_SC_H", LIEF::assembly::riscv::OPCODE::CV_AND_SC_H) + .value("CV_AVGU_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_B) + .value("CV_AVGU_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_H) + .value("CV_AVGU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_B) + .value("CV_AVGU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_H) + .value("CV_AVGU_SC_B", LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_B) + .value("CV_AVGU_SC_H", LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_H) + .value("CV_AVG_B", LIEF::assembly::riscv::OPCODE::CV_AVG_B) + .value("CV_AVG_H", LIEF::assembly::riscv::OPCODE::CV_AVG_H) + .value("CV_AVG_SCI_B", LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_B) + .value("CV_AVG_SCI_H", LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_H) + .value("CV_AVG_SC_B", LIEF::assembly::riscv::OPCODE::CV_AVG_SC_B) + .value("CV_AVG_SC_H", LIEF::assembly::riscv::OPCODE::CV_AVG_SC_H) + .value("CV_BCLR", LIEF::assembly::riscv::OPCODE::CV_BCLR) + .value("CV_BCLRR", LIEF::assembly::riscv::OPCODE::CV_BCLRR) + .value("CV_BEQIMM", LIEF::assembly::riscv::OPCODE::CV_BEQIMM) + .value("CV_BITREV", LIEF::assembly::riscv::OPCODE::CV_BITREV) + .value("CV_BNEIMM", LIEF::assembly::riscv::OPCODE::CV_BNEIMM) + .value("CV_BSET", LIEF::assembly::riscv::OPCODE::CV_BSET) + .value("CV_BSETR", LIEF::assembly::riscv::OPCODE::CV_BSETR) + .value("CV_CLB", LIEF::assembly::riscv::OPCODE::CV_CLB) + .value("CV_CLIP", LIEF::assembly::riscv::OPCODE::CV_CLIP) + .value("CV_CLIPR", LIEF::assembly::riscv::OPCODE::CV_CLIPR) + .value("CV_CLIPU", LIEF::assembly::riscv::OPCODE::CV_CLIPU) + .value("CV_CLIPUR", LIEF::assembly::riscv::OPCODE::CV_CLIPUR) + .value("CV_CMPEQ_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_B) + .value("CV_CMPEQ_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_H) + .value("CV_CMPEQ_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_B) + .value("CV_CMPEQ_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_H) + .value("CV_CMPEQ_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_B) + .value("CV_CMPEQ_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_H) + .value("CV_CMPGEU_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_B) + .value("CV_CMPGEU_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_H) + .value("CV_CMPGEU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_B) + .value("CV_CMPGEU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_H) + .value("CV_CMPGEU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_B) + .value("CV_CMPGEU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_H) + .value("CV_CMPGE_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_B) + .value("CV_CMPGE_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_H) + .value("CV_CMPGE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_B) + .value("CV_CMPGE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_H) + .value("CV_CMPGE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_B) + .value("CV_CMPGE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_H) + .value("CV_CMPGTU_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_B) + .value("CV_CMPGTU_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_H) + .value("CV_CMPGTU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_B) + .value("CV_CMPGTU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_H) + .value("CV_CMPGTU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_B) + .value("CV_CMPGTU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_H) + .value("CV_CMPGT_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_B) + .value("CV_CMPGT_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_H) + .value("CV_CMPGT_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_B) + .value("CV_CMPGT_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_H) + .value("CV_CMPGT_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_B) + .value("CV_CMPGT_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_H) + .value("CV_CMPLEU_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_B) + .value("CV_CMPLEU_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_H) + .value("CV_CMPLEU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_B) + .value("CV_CMPLEU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_H) + .value("CV_CMPLEU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_B) + .value("CV_CMPLEU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_H) + .value("CV_CMPLE_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_B) + .value("CV_CMPLE_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_H) + .value("CV_CMPLE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_B) + .value("CV_CMPLE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_H) + .value("CV_CMPLE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_B) + .value("CV_CMPLE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_H) + .value("CV_CMPLTU_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_B) + .value("CV_CMPLTU_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_H) + .value("CV_CMPLTU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_B) + .value("CV_CMPLTU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_H) + .value("CV_CMPLTU_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_B) + .value("CV_CMPLTU_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_H) + .value("CV_CMPLT_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_B) + .value("CV_CMPLT_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_H) + .value("CV_CMPLT_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_B) + .value("CV_CMPLT_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_H) + .value("CV_CMPLT_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_B) + .value("CV_CMPLT_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_H) + .value("CV_CMPNE_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_B) + .value("CV_CMPNE_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_H) + .value("CV_CMPNE_SCI_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_B) + .value("CV_CMPNE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_H) + .value("CV_CMPNE_SC_B", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_B) + .value("CV_CMPNE_SC_H", LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_H) + .value("CV_CNT", LIEF::assembly::riscv::OPCODE::CV_CNT) + .value("CV_CPLXCONJ", LIEF::assembly::riscv::OPCODE::CV_CPLXCONJ) + .value("CV_CPLXMUL_I", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I) + .value("CV_CPLXMUL_I_DIV2", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV2) + .value("CV_CPLXMUL_I_DIV4", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV4) + .value("CV_CPLXMUL_I_DIV8", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV8) + .value("CV_CPLXMUL_R", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R) + .value("CV_CPLXMUL_R_DIV2", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV2) + .value("CV_CPLXMUL_R_DIV4", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV4) + .value("CV_CPLXMUL_R_DIV8", LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV8) + .value("CV_DOTSP_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_B) + .value("CV_DOTSP_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_H) + .value("CV_DOTSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_B) + .value("CV_DOTSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_H) + .value("CV_DOTSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_B) + .value("CV_DOTSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_H) + .value("CV_DOTUP_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_B) + .value("CV_DOTUP_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_H) + .value("CV_DOTUP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_B) + .value("CV_DOTUP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_H) + .value("CV_DOTUP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_B) + .value("CV_DOTUP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_H) + .value("CV_DOTUSP_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_B) + .value("CV_DOTUSP_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_H) + .value("CV_DOTUSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_B) + .value("CV_DOTUSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_H) + .value("CV_DOTUSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_B) + .value("CV_DOTUSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_H) + .value("CV_ELW", LIEF::assembly::riscv::OPCODE::CV_ELW) + .value("CV_EXTBS", LIEF::assembly::riscv::OPCODE::CV_EXTBS) + .value("CV_EXTBZ", LIEF::assembly::riscv::OPCODE::CV_EXTBZ) + .value("CV_EXTHS", LIEF::assembly::riscv::OPCODE::CV_EXTHS) + .value("CV_EXTHZ", LIEF::assembly::riscv::OPCODE::CV_EXTHZ) + .value("CV_EXTRACT", LIEF::assembly::riscv::OPCODE::CV_EXTRACT) + .value("CV_EXTRACTR", LIEF::assembly::riscv::OPCODE::CV_EXTRACTR) + .value("CV_EXTRACTU", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU) + .value("CV_EXTRACTUR", LIEF::assembly::riscv::OPCODE::CV_EXTRACTUR) + .value("CV_EXTRACTU_B", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_B) + .value("CV_EXTRACTU_H", LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_H) + .value("CV_EXTRACT_B", LIEF::assembly::riscv::OPCODE::CV_EXTRACT_B) + .value("CV_EXTRACT_H", LIEF::assembly::riscv::OPCODE::CV_EXTRACT_H) + .value("CV_FF1", LIEF::assembly::riscv::OPCODE::CV_FF1) + .value("CV_FL1", LIEF::assembly::riscv::OPCODE::CV_FL1) + .value("CV_INSERT", LIEF::assembly::riscv::OPCODE::CV_INSERT) + .value("CV_INSERTR", LIEF::assembly::riscv::OPCODE::CV_INSERTR) + .value("CV_INSERT_B", LIEF::assembly::riscv::OPCODE::CV_INSERT_B) + .value("CV_INSERT_H", LIEF::assembly::riscv::OPCODE::CV_INSERT_H) + .value("CV_LBU_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LBU_ri_inc) + .value("CV_LBU_rr", LIEF::assembly::riscv::OPCODE::CV_LBU_rr) + .value("CV_LBU_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LBU_rr_inc) + .value("CV_LB_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LB_ri_inc) + .value("CV_LB_rr", LIEF::assembly::riscv::OPCODE::CV_LB_rr) + .value("CV_LB_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LB_rr_inc) + .value("CV_LHU_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LHU_ri_inc) + .value("CV_LHU_rr", LIEF::assembly::riscv::OPCODE::CV_LHU_rr) + .value("CV_LHU_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LHU_rr_inc) + .value("CV_LH_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LH_ri_inc) + .value("CV_LH_rr", LIEF::assembly::riscv::OPCODE::CV_LH_rr) + .value("CV_LH_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LH_rr_inc) + .value("CV_LW_ri_inc", LIEF::assembly::riscv::OPCODE::CV_LW_ri_inc) + .value("CV_LW_rr", LIEF::assembly::riscv::OPCODE::CV_LW_rr) + .value("CV_LW_rr_inc", LIEF::assembly::riscv::OPCODE::CV_LW_rr_inc) + .value("CV_MAC", LIEF::assembly::riscv::OPCODE::CV_MAC) + .value("CV_MACHHSN", LIEF::assembly::riscv::OPCODE::CV_MACHHSN) + .value("CV_MACHHSRN", LIEF::assembly::riscv::OPCODE::CV_MACHHSRN) + .value("CV_MACHHUN", LIEF::assembly::riscv::OPCODE::CV_MACHHUN) + .value("CV_MACHHURN", LIEF::assembly::riscv::OPCODE::CV_MACHHURN) + .value("CV_MACSN", LIEF::assembly::riscv::OPCODE::CV_MACSN) + .value("CV_MACSRN", LIEF::assembly::riscv::OPCODE::CV_MACSRN) + .value("CV_MACUN", LIEF::assembly::riscv::OPCODE::CV_MACUN) + .value("CV_MACURN", LIEF::assembly::riscv::OPCODE::CV_MACURN) + .value("CV_MAX", LIEF::assembly::riscv::OPCODE::CV_MAX) + .value("CV_MAXU", LIEF::assembly::riscv::OPCODE::CV_MAXU) + .value("CV_MAXU_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_B); + opcodes.value("CV_MAXU_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_H) + .value("CV_MAXU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_B) + .value("CV_MAXU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_H) + .value("CV_MAXU_SC_B", LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_B) + .value("CV_MAXU_SC_H", LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_H) + .value("CV_MAX_B", LIEF::assembly::riscv::OPCODE::CV_MAX_B) + .value("CV_MAX_H", LIEF::assembly::riscv::OPCODE::CV_MAX_H) + .value("CV_MAX_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_B) + .value("CV_MAX_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_H) + .value("CV_MAX_SC_B", LIEF::assembly::riscv::OPCODE::CV_MAX_SC_B) + .value("CV_MAX_SC_H", LIEF::assembly::riscv::OPCODE::CV_MAX_SC_H) + .value("CV_MIN", LIEF::assembly::riscv::OPCODE::CV_MIN) + .value("CV_MINU", LIEF::assembly::riscv::OPCODE::CV_MINU) + .value("CV_MINU_B", LIEF::assembly::riscv::OPCODE::CV_MINU_B) + .value("CV_MINU_H", LIEF::assembly::riscv::OPCODE::CV_MINU_H) + .value("CV_MINU_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_B) + .value("CV_MINU_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_H) + .value("CV_MINU_SC_B", LIEF::assembly::riscv::OPCODE::CV_MINU_SC_B) + .value("CV_MINU_SC_H", LIEF::assembly::riscv::OPCODE::CV_MINU_SC_H) + .value("CV_MIN_B", LIEF::assembly::riscv::OPCODE::CV_MIN_B) + .value("CV_MIN_H", LIEF::assembly::riscv::OPCODE::CV_MIN_H) + .value("CV_MIN_SCI_B", LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_B) + .value("CV_MIN_SCI_H", LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_H) + .value("CV_MIN_SC_B", LIEF::assembly::riscv::OPCODE::CV_MIN_SC_B) + .value("CV_MIN_SC_H", LIEF::assembly::riscv::OPCODE::CV_MIN_SC_H) + .value("CV_MSU", LIEF::assembly::riscv::OPCODE::CV_MSU) + .value("CV_MULHHSN", LIEF::assembly::riscv::OPCODE::CV_MULHHSN) + .value("CV_MULHHSRN", LIEF::assembly::riscv::OPCODE::CV_MULHHSRN) + .value("CV_MULHHUN", LIEF::assembly::riscv::OPCODE::CV_MULHHUN) + .value("CV_MULHHURN", LIEF::assembly::riscv::OPCODE::CV_MULHHURN) + .value("CV_MULSN", LIEF::assembly::riscv::OPCODE::CV_MULSN) + .value("CV_MULSRN", LIEF::assembly::riscv::OPCODE::CV_MULSRN) + .value("CV_MULUN", LIEF::assembly::riscv::OPCODE::CV_MULUN) + .value("CV_MULURN", LIEF::assembly::riscv::OPCODE::CV_MULURN) + .value("CV_OR_B", LIEF::assembly::riscv::OPCODE::CV_OR_B) + .value("CV_OR_H", LIEF::assembly::riscv::OPCODE::CV_OR_H) + .value("CV_OR_SCI_B", LIEF::assembly::riscv::OPCODE::CV_OR_SCI_B) + .value("CV_OR_SCI_H", LIEF::assembly::riscv::OPCODE::CV_OR_SCI_H) + .value("CV_OR_SC_B", LIEF::assembly::riscv::OPCODE::CV_OR_SC_B) + .value("CV_OR_SC_H", LIEF::assembly::riscv::OPCODE::CV_OR_SC_H) + .value("CV_PACK", LIEF::assembly::riscv::OPCODE::CV_PACK) + .value("CV_PACKHI_B", LIEF::assembly::riscv::OPCODE::CV_PACKHI_B) + .value("CV_PACKLO_B", LIEF::assembly::riscv::OPCODE::CV_PACKLO_B) + .value("CV_PACK_H", LIEF::assembly::riscv::OPCODE::CV_PACK_H) + .value("CV_ROR", LIEF::assembly::riscv::OPCODE::CV_ROR) + .value("CV_SB_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SB_ri_inc) + .value("CV_SB_rr", LIEF::assembly::riscv::OPCODE::CV_SB_rr) + .value("CV_SB_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SB_rr_inc) + .value("CV_SDOTSP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_B) + .value("CV_SDOTSP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_H) + .value("CV_SDOTSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_B) + .value("CV_SDOTSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_H) + .value("CV_SDOTSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_B) + .value("CV_SDOTSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_H) + .value("CV_SDOTUP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_B) + .value("CV_SDOTUP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_H) + .value("CV_SDOTUP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_B) + .value("CV_SDOTUP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_H) + .value("CV_SDOTUP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_B) + .value("CV_SDOTUP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_H) + .value("CV_SDOTUSP_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_B) + .value("CV_SDOTUSP_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_H) + .value("CV_SDOTUSP_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_B) + .value("CV_SDOTUSP_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_H) + .value("CV_SDOTUSP_SC_B", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_B) + .value("CV_SDOTUSP_SC_H", LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_H) + .value("CV_SHUFFLE2_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_B) + .value("CV_SHUFFLE2_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_H) + .value("CV_SHUFFLEI0_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI0_SCI_B) + .value("CV_SHUFFLEI1_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI1_SCI_B) + .value("CV_SHUFFLEI2_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI2_SCI_B) + .value("CV_SHUFFLEI3_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI3_SCI_B) + .value("CV_SHUFFLE_B", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_B) + .value("CV_SHUFFLE_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_H) + .value("CV_SHUFFLE_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_SCI_H) + .value("CV_SH_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SH_ri_inc) + .value("CV_SH_rr", LIEF::assembly::riscv::OPCODE::CV_SH_rr) + .value("CV_SH_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SH_rr_inc) + .value("CV_SLE", LIEF::assembly::riscv::OPCODE::CV_SLE) + .value("CV_SLEU", LIEF::assembly::riscv::OPCODE::CV_SLEU) + .value("CV_SLL_B", LIEF::assembly::riscv::OPCODE::CV_SLL_B) + .value("CV_SLL_H", LIEF::assembly::riscv::OPCODE::CV_SLL_H) + .value("CV_SLL_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_B) + .value("CV_SLL_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_H) + .value("CV_SLL_SC_B", LIEF::assembly::riscv::OPCODE::CV_SLL_SC_B) + .value("CV_SLL_SC_H", LIEF::assembly::riscv::OPCODE::CV_SLL_SC_H) + .value("CV_SRA_B", LIEF::assembly::riscv::OPCODE::CV_SRA_B) + .value("CV_SRA_H", LIEF::assembly::riscv::OPCODE::CV_SRA_H) + .value("CV_SRA_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_B) + .value("CV_SRA_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_H) + .value("CV_SRA_SC_B", LIEF::assembly::riscv::OPCODE::CV_SRA_SC_B) + .value("CV_SRA_SC_H", LIEF::assembly::riscv::OPCODE::CV_SRA_SC_H) + .value("CV_SRL_B", LIEF::assembly::riscv::OPCODE::CV_SRL_B) + .value("CV_SRL_H", LIEF::assembly::riscv::OPCODE::CV_SRL_H) + .value("CV_SRL_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_B) + .value("CV_SRL_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_H) + .value("CV_SRL_SC_B", LIEF::assembly::riscv::OPCODE::CV_SRL_SC_B) + .value("CV_SRL_SC_H", LIEF::assembly::riscv::OPCODE::CV_SRL_SC_H) + .value("CV_SUBN", LIEF::assembly::riscv::OPCODE::CV_SUBN) + .value("CV_SUBNR", LIEF::assembly::riscv::OPCODE::CV_SUBNR) + .value("CV_SUBRN", LIEF::assembly::riscv::OPCODE::CV_SUBRN) + .value("CV_SUBRNR", LIEF::assembly::riscv::OPCODE::CV_SUBRNR) + .value("CV_SUBROTMJ", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ) + .value("CV_SUBROTMJ_DIV2", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV2) + .value("CV_SUBROTMJ_DIV4", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV4) + .value("CV_SUBROTMJ_DIV8", LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV8) + .value("CV_SUBUN", LIEF::assembly::riscv::OPCODE::CV_SUBUN) + .value("CV_SUBUNR", LIEF::assembly::riscv::OPCODE::CV_SUBUNR) + .value("CV_SUBURN", LIEF::assembly::riscv::OPCODE::CV_SUBURN) + .value("CV_SUBURNR", LIEF::assembly::riscv::OPCODE::CV_SUBURNR) + .value("CV_SUB_B", LIEF::assembly::riscv::OPCODE::CV_SUB_B) + .value("CV_SUB_DIV2", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV2) + .value("CV_SUB_DIV4", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV4) + .value("CV_SUB_DIV8", LIEF::assembly::riscv::OPCODE::CV_SUB_DIV8) + .value("CV_SUB_H", LIEF::assembly::riscv::OPCODE::CV_SUB_H) + .value("CV_SUB_SCI_B", LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_B) + .value("CV_SUB_SCI_H", LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_H) + .value("CV_SUB_SC_B", LIEF::assembly::riscv::OPCODE::CV_SUB_SC_B) + .value("CV_SUB_SC_H", LIEF::assembly::riscv::OPCODE::CV_SUB_SC_H) + .value("CV_SW_ri_inc", LIEF::assembly::riscv::OPCODE::CV_SW_ri_inc) + .value("CV_SW_rr", LIEF::assembly::riscv::OPCODE::CV_SW_rr) + .value("CV_SW_rr_inc", LIEF::assembly::riscv::OPCODE::CV_SW_rr_inc) + .value("CV_XOR_B", LIEF::assembly::riscv::OPCODE::CV_XOR_B) + .value("CV_XOR_H", LIEF::assembly::riscv::OPCODE::CV_XOR_H) + .value("CV_XOR_SCI_B", LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_B) + .value("CV_XOR_SCI_H", LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_H) + .value("CV_XOR_SC_B", LIEF::assembly::riscv::OPCODE::CV_XOR_SC_B) + .value("CV_XOR_SC_H", LIEF::assembly::riscv::OPCODE::CV_XOR_SC_H) + .value("CZERO_EQZ", LIEF::assembly::riscv::OPCODE::CZERO_EQZ) + .value("CZERO_NEZ", LIEF::assembly::riscv::OPCODE::CZERO_NEZ) + .value("C_ADD", LIEF::assembly::riscv::OPCODE::C_ADD) + .value("C_ADDI", LIEF::assembly::riscv::OPCODE::C_ADDI) + .value("C_ADDI16SP", LIEF::assembly::riscv::OPCODE::C_ADDI16SP) + .value("C_ADDI4SPN", LIEF::assembly::riscv::OPCODE::C_ADDI4SPN) + .value("C_ADDIW", LIEF::assembly::riscv::OPCODE::C_ADDIW) + .value("C_ADDW", LIEF::assembly::riscv::OPCODE::C_ADDW) + .value("C_AND", LIEF::assembly::riscv::OPCODE::C_AND) + .value("C_ANDI", LIEF::assembly::riscv::OPCODE::C_ANDI) + .value("C_BEQZ", LIEF::assembly::riscv::OPCODE::C_BEQZ) + .value("C_BNEZ", LIEF::assembly::riscv::OPCODE::C_BNEZ) + .value("C_EBREAK", LIEF::assembly::riscv::OPCODE::C_EBREAK) + .value("C_FLD", LIEF::assembly::riscv::OPCODE::C_FLD) + .value("C_FLDSP", LIEF::assembly::riscv::OPCODE::C_FLDSP) + .value("C_FLW", LIEF::assembly::riscv::OPCODE::C_FLW) + .value("C_FLWSP", LIEF::assembly::riscv::OPCODE::C_FLWSP) + .value("C_FSD", LIEF::assembly::riscv::OPCODE::C_FSD) + .value("C_FSDSP", LIEF::assembly::riscv::OPCODE::C_FSDSP) + .value("C_FSW", LIEF::assembly::riscv::OPCODE::C_FSW) + .value("C_FSWSP", LIEF::assembly::riscv::OPCODE::C_FSWSP) + .value("C_J", LIEF::assembly::riscv::OPCODE::C_J) + .value("C_JAL", LIEF::assembly::riscv::OPCODE::C_JAL) + .value("C_JALR", LIEF::assembly::riscv::OPCODE::C_JALR) + .value("C_JR", LIEF::assembly::riscv::OPCODE::C_JR) + .value("C_LBU", LIEF::assembly::riscv::OPCODE::C_LBU) + .value("C_LD", LIEF::assembly::riscv::OPCODE::C_LD) + .value("C_LDSP", LIEF::assembly::riscv::OPCODE::C_LDSP) + .value("C_LDSP_RV32", LIEF::assembly::riscv::OPCODE::C_LDSP_RV32) + .value("C_LD_RV32", LIEF::assembly::riscv::OPCODE::C_LD_RV32) + .value("C_LH", LIEF::assembly::riscv::OPCODE::C_LH) + .value("C_LHU", LIEF::assembly::riscv::OPCODE::C_LHU) + .value("C_LH_INX", LIEF::assembly::riscv::OPCODE::C_LH_INX) + .value("C_LI", LIEF::assembly::riscv::OPCODE::C_LI) + .value("C_LUI", LIEF::assembly::riscv::OPCODE::C_LUI) + .value("C_LW", LIEF::assembly::riscv::OPCODE::C_LW) + .value("C_LWSP", LIEF::assembly::riscv::OPCODE::C_LWSP) + .value("C_LWSP_INX", LIEF::assembly::riscv::OPCODE::C_LWSP_INX) + .value("C_LW_INX", LIEF::assembly::riscv::OPCODE::C_LW_INX) + .value("C_MOP_1", LIEF::assembly::riscv::OPCODE::C_MOP_1) + .value("C_MOP_11", LIEF::assembly::riscv::OPCODE::C_MOP_11) + .value("C_MOP_13", LIEF::assembly::riscv::OPCODE::C_MOP_13) + .value("C_MOP_15", LIEF::assembly::riscv::OPCODE::C_MOP_15) + .value("C_MOP_3", LIEF::assembly::riscv::OPCODE::C_MOP_3) + .value("C_MOP_5", LIEF::assembly::riscv::OPCODE::C_MOP_5) + .value("C_MOP_7", LIEF::assembly::riscv::OPCODE::C_MOP_7) + .value("C_MOP_9", LIEF::assembly::riscv::OPCODE::C_MOP_9) + .value("C_MUL", LIEF::assembly::riscv::OPCODE::C_MUL) + .value("C_MV", LIEF::assembly::riscv::OPCODE::C_MV) + .value("C_NOP", LIEF::assembly::riscv::OPCODE::C_NOP) + .value("C_NOP_HINT", LIEF::assembly::riscv::OPCODE::C_NOP_HINT) + .value("C_NOT", LIEF::assembly::riscv::OPCODE::C_NOT) + .value("C_OR", LIEF::assembly::riscv::OPCODE::C_OR) + .value("C_SB", LIEF::assembly::riscv::OPCODE::C_SB) + .value("C_SD", LIEF::assembly::riscv::OPCODE::C_SD) + .value("C_SDSP", LIEF::assembly::riscv::OPCODE::C_SDSP) + .value("C_SDSP_RV32", LIEF::assembly::riscv::OPCODE::C_SDSP_RV32) + .value("C_SD_RV32", LIEF::assembly::riscv::OPCODE::C_SD_RV32) + .value("C_SEXT_B", LIEF::assembly::riscv::OPCODE::C_SEXT_B) + .value("C_SEXT_H", LIEF::assembly::riscv::OPCODE::C_SEXT_H) + .value("C_SH", LIEF::assembly::riscv::OPCODE::C_SH) + .value("C_SH_INX", LIEF::assembly::riscv::OPCODE::C_SH_INX) + .value("C_SLLI", LIEF::assembly::riscv::OPCODE::C_SLLI) + .value("C_SRAI", LIEF::assembly::riscv::OPCODE::C_SRAI) + .value("C_SRLI", LIEF::assembly::riscv::OPCODE::C_SRLI) + .value("C_SSPOPCHK", LIEF::assembly::riscv::OPCODE::C_SSPOPCHK) + .value("C_SSPUSH", LIEF::assembly::riscv::OPCODE::C_SSPUSH) + .value("C_SUB", LIEF::assembly::riscv::OPCODE::C_SUB) + .value("C_SUBW", LIEF::assembly::riscv::OPCODE::C_SUBW) + .value("C_SW", LIEF::assembly::riscv::OPCODE::C_SW) + .value("C_SWSP", LIEF::assembly::riscv::OPCODE::C_SWSP) + .value("C_SWSP_INX", LIEF::assembly::riscv::OPCODE::C_SWSP_INX) + .value("C_SW_INX", LIEF::assembly::riscv::OPCODE::C_SW_INX) + .value("C_UNIMP", LIEF::assembly::riscv::OPCODE::C_UNIMP) + .value("C_XOR", LIEF::assembly::riscv::OPCODE::C_XOR) + .value("C_ZEXT_B", LIEF::assembly::riscv::OPCODE::C_ZEXT_B) + .value("C_ZEXT_H", LIEF::assembly::riscv::OPCODE::C_ZEXT_H) + .value("C_ZEXT_W", LIEF::assembly::riscv::OPCODE::C_ZEXT_W) + .value("DIV", LIEF::assembly::riscv::OPCODE::DIV) + .value("DIVU", LIEF::assembly::riscv::OPCODE::DIVU) + .value("DIVUW", LIEF::assembly::riscv::OPCODE::DIVUW) + .value("DIVW", LIEF::assembly::riscv::OPCODE::DIVW) + .value("DRET", LIEF::assembly::riscv::OPCODE::DRET) + .value("EBREAK", LIEF::assembly::riscv::OPCODE::EBREAK) + .value("ECALL", LIEF::assembly::riscv::OPCODE::ECALL) + .value("FADD_D", LIEF::assembly::riscv::OPCODE::FADD_D) + .value("FADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FADD_D_IN32X) + .value("FADD_D_INX", LIEF::assembly::riscv::OPCODE::FADD_D_INX) + .value("FADD_H", LIEF::assembly::riscv::OPCODE::FADD_H) + .value("FADD_H_INX", LIEF::assembly::riscv::OPCODE::FADD_H_INX) + .value("FADD_Q", LIEF::assembly::riscv::OPCODE::FADD_Q) + .value("FADD_S", LIEF::assembly::riscv::OPCODE::FADD_S) + .value("FADD_S_INX", LIEF::assembly::riscv::OPCODE::FADD_S_INX) + .value("FCLASS_D", LIEF::assembly::riscv::OPCODE::FCLASS_D) + .value("FCLASS_D_IN32X", LIEF::assembly::riscv::OPCODE::FCLASS_D_IN32X) + .value("FCLASS_D_INX", LIEF::assembly::riscv::OPCODE::FCLASS_D_INX) + .value("FCLASS_H", LIEF::assembly::riscv::OPCODE::FCLASS_H) + .value("FCLASS_H_INX", LIEF::assembly::riscv::OPCODE::FCLASS_H_INX) + .value("FCLASS_Q", LIEF::assembly::riscv::OPCODE::FCLASS_Q) + .value("FCLASS_S", LIEF::assembly::riscv::OPCODE::FCLASS_S) + .value("FCLASS_S_INX", LIEF::assembly::riscv::OPCODE::FCLASS_S_INX) + .value("FCVTMOD_W_D", LIEF::assembly::riscv::OPCODE::FCVTMOD_W_D) + .value("FCVT_BF16_S", LIEF::assembly::riscv::OPCODE::FCVT_BF16_S) + .value("FCVT_D_H", LIEF::assembly::riscv::OPCODE::FCVT_D_H) + .value("FCVT_D_H_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_H_IN32X) + .value("FCVT_D_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_H_INX) + .value("FCVT_D_L", LIEF::assembly::riscv::OPCODE::FCVT_D_L) + .value("FCVT_D_LU", LIEF::assembly::riscv::OPCODE::FCVT_D_LU) + .value("FCVT_D_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_LU_INX) + .value("FCVT_D_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_L_INX) + .value("FCVT_D_Q", LIEF::assembly::riscv::OPCODE::FCVT_D_Q) + .value("FCVT_D_S", LIEF::assembly::riscv::OPCODE::FCVT_D_S) + .value("FCVT_D_S_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_S_IN32X) + .value("FCVT_D_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_S_INX) + .value("FCVT_D_W", LIEF::assembly::riscv::OPCODE::FCVT_D_W) + .value("FCVT_D_WU", LIEF::assembly::riscv::OPCODE::FCVT_D_WU) + .value("FCVT_D_WU_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_WU_IN32X) + .value("FCVT_D_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_WU_INX) + .value("FCVT_D_W_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_D_W_IN32X) + .value("FCVT_D_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_D_W_INX) + .value("FCVT_H_D", LIEF::assembly::riscv::OPCODE::FCVT_H_D) + .value("FCVT_H_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_H_D_IN32X) + .value("FCVT_H_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_D_INX) + .value("FCVT_H_L", LIEF::assembly::riscv::OPCODE::FCVT_H_L) + .value("FCVT_H_LU", LIEF::assembly::riscv::OPCODE::FCVT_H_LU) + .value("FCVT_H_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_LU_INX) + .value("FCVT_H_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_L_INX) + .value("FCVT_H_S", LIEF::assembly::riscv::OPCODE::FCVT_H_S) + .value("FCVT_H_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_S_INX) + .value("FCVT_H_W", LIEF::assembly::riscv::OPCODE::FCVT_H_W) + .value("FCVT_H_WU", LIEF::assembly::riscv::OPCODE::FCVT_H_WU) + .value("FCVT_H_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_WU_INX) + .value("FCVT_H_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_H_W_INX) + .value("FCVT_LU_D", LIEF::assembly::riscv::OPCODE::FCVT_LU_D) + .value("FCVT_LU_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_D_INX) + .value("FCVT_LU_H", LIEF::assembly::riscv::OPCODE::FCVT_LU_H) + .value("FCVT_LU_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_H_INX) + .value("FCVT_LU_Q", LIEF::assembly::riscv::OPCODE::FCVT_LU_Q) + .value("FCVT_LU_S", LIEF::assembly::riscv::OPCODE::FCVT_LU_S) + .value("FCVT_LU_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_LU_S_INX) + .value("FCVT_L_D", LIEF::assembly::riscv::OPCODE::FCVT_L_D) + .value("FCVT_L_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_D_INX) + .value("FCVT_L_H", LIEF::assembly::riscv::OPCODE::FCVT_L_H) + .value("FCVT_L_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_H_INX) + .value("FCVT_L_Q", LIEF::assembly::riscv::OPCODE::FCVT_L_Q) + .value("FCVT_L_S", LIEF::assembly::riscv::OPCODE::FCVT_L_S) + .value("FCVT_L_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_L_S_INX) + .value("FCVT_Q_D", LIEF::assembly::riscv::OPCODE::FCVT_Q_D) + .value("FCVT_Q_L", LIEF::assembly::riscv::OPCODE::FCVT_Q_L) + .value("FCVT_Q_LU", LIEF::assembly::riscv::OPCODE::FCVT_Q_LU) + .value("FCVT_Q_S", LIEF::assembly::riscv::OPCODE::FCVT_Q_S) + .value("FCVT_Q_W", LIEF::assembly::riscv::OPCODE::FCVT_Q_W) + .value("FCVT_Q_WU", LIEF::assembly::riscv::OPCODE::FCVT_Q_WU) + .value("FCVT_S_BF16", LIEF::assembly::riscv::OPCODE::FCVT_S_BF16) + .value("FCVT_S_D", LIEF::assembly::riscv::OPCODE::FCVT_S_D) + .value("FCVT_S_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_S_D_IN32X) + .value("FCVT_S_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_D_INX) + .value("FCVT_S_H", LIEF::assembly::riscv::OPCODE::FCVT_S_H) + .value("FCVT_S_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_H_INX) + .value("FCVT_S_L", LIEF::assembly::riscv::OPCODE::FCVT_S_L) + .value("FCVT_S_LU", LIEF::assembly::riscv::OPCODE::FCVT_S_LU) + .value("FCVT_S_LU_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_LU_INX) + .value("FCVT_S_L_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_L_INX) + .value("FCVT_S_Q", LIEF::assembly::riscv::OPCODE::FCVT_S_Q) + .value("FCVT_S_W", LIEF::assembly::riscv::OPCODE::FCVT_S_W) + .value("FCVT_S_WU", LIEF::assembly::riscv::OPCODE::FCVT_S_WU) + .value("FCVT_S_WU_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_WU_INX) + .value("FCVT_S_W_INX", LIEF::assembly::riscv::OPCODE::FCVT_S_W_INX) + .value("FCVT_WU_D", LIEF::assembly::riscv::OPCODE::FCVT_WU_D) + .value("FCVT_WU_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_WU_D_IN32X) + .value("FCVT_WU_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_D_INX) + .value("FCVT_WU_H", LIEF::assembly::riscv::OPCODE::FCVT_WU_H); + opcodes.value("FCVT_WU_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_H_INX) + .value("FCVT_WU_Q", LIEF::assembly::riscv::OPCODE::FCVT_WU_Q) + .value("FCVT_WU_S", LIEF::assembly::riscv::OPCODE::FCVT_WU_S) + .value("FCVT_WU_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_WU_S_INX) + .value("FCVT_W_D", LIEF::assembly::riscv::OPCODE::FCVT_W_D) + .value("FCVT_W_D_IN32X", LIEF::assembly::riscv::OPCODE::FCVT_W_D_IN32X) + .value("FCVT_W_D_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_D_INX) + .value("FCVT_W_H", LIEF::assembly::riscv::OPCODE::FCVT_W_H) + .value("FCVT_W_H_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_H_INX) + .value("FCVT_W_Q", LIEF::assembly::riscv::OPCODE::FCVT_W_Q) + .value("FCVT_W_S", LIEF::assembly::riscv::OPCODE::FCVT_W_S) + .value("FCVT_W_S_INX", LIEF::assembly::riscv::OPCODE::FCVT_W_S_INX) + .value("FDIV_D", LIEF::assembly::riscv::OPCODE::FDIV_D) + .value("FDIV_D_IN32X", LIEF::assembly::riscv::OPCODE::FDIV_D_IN32X) + .value("FDIV_D_INX", LIEF::assembly::riscv::OPCODE::FDIV_D_INX) + .value("FDIV_H", LIEF::assembly::riscv::OPCODE::FDIV_H) + .value("FDIV_H_INX", LIEF::assembly::riscv::OPCODE::FDIV_H_INX) + .value("FDIV_Q", LIEF::assembly::riscv::OPCODE::FDIV_Q) + .value("FDIV_S", LIEF::assembly::riscv::OPCODE::FDIV_S) + .value("FDIV_S_INX", LIEF::assembly::riscv::OPCODE::FDIV_S_INX) + .value("FENCE", LIEF::assembly::riscv::OPCODE::FENCE) + .value("FENCE_I", LIEF::assembly::riscv::OPCODE::FENCE_I) + .value("FENCE_TSO", LIEF::assembly::riscv::OPCODE::FENCE_TSO) + .value("FEQ_D", LIEF::assembly::riscv::OPCODE::FEQ_D) + .value("FEQ_D_IN32X", LIEF::assembly::riscv::OPCODE::FEQ_D_IN32X) + .value("FEQ_D_INX", LIEF::assembly::riscv::OPCODE::FEQ_D_INX) + .value("FEQ_H", LIEF::assembly::riscv::OPCODE::FEQ_H) + .value("FEQ_H_INX", LIEF::assembly::riscv::OPCODE::FEQ_H_INX) + .value("FEQ_Q", LIEF::assembly::riscv::OPCODE::FEQ_Q) + .value("FEQ_S", LIEF::assembly::riscv::OPCODE::FEQ_S) + .value("FEQ_S_INX", LIEF::assembly::riscv::OPCODE::FEQ_S_INX) + .value("FLD", LIEF::assembly::riscv::OPCODE::FLD) + .value("FLEQ_D", LIEF::assembly::riscv::OPCODE::FLEQ_D) + .value("FLEQ_H", LIEF::assembly::riscv::OPCODE::FLEQ_H) + .value("FLEQ_Q", LIEF::assembly::riscv::OPCODE::FLEQ_Q) + .value("FLEQ_S", LIEF::assembly::riscv::OPCODE::FLEQ_S) + .value("FLE_D", LIEF::assembly::riscv::OPCODE::FLE_D) + .value("FLE_D_IN32X", LIEF::assembly::riscv::OPCODE::FLE_D_IN32X) + .value("FLE_D_INX", LIEF::assembly::riscv::OPCODE::FLE_D_INX) + .value("FLE_H", LIEF::assembly::riscv::OPCODE::FLE_H) + .value("FLE_H_INX", LIEF::assembly::riscv::OPCODE::FLE_H_INX) + .value("FLE_Q", LIEF::assembly::riscv::OPCODE::FLE_Q) + .value("FLE_S", LIEF::assembly::riscv::OPCODE::FLE_S) + .value("FLE_S_INX", LIEF::assembly::riscv::OPCODE::FLE_S_INX) + .value("FLH", LIEF::assembly::riscv::OPCODE::FLH) + .value("FLI_D", LIEF::assembly::riscv::OPCODE::FLI_D) + .value("FLI_H", LIEF::assembly::riscv::OPCODE::FLI_H) + .value("FLI_Q", LIEF::assembly::riscv::OPCODE::FLI_Q) + .value("FLI_S", LIEF::assembly::riscv::OPCODE::FLI_S) + .value("FLQ", LIEF::assembly::riscv::OPCODE::FLQ) + .value("FLTQ_D", LIEF::assembly::riscv::OPCODE::FLTQ_D) + .value("FLTQ_H", LIEF::assembly::riscv::OPCODE::FLTQ_H) + .value("FLTQ_Q", LIEF::assembly::riscv::OPCODE::FLTQ_Q) + .value("FLTQ_S", LIEF::assembly::riscv::OPCODE::FLTQ_S) + .value("FLT_D", LIEF::assembly::riscv::OPCODE::FLT_D) + .value("FLT_D_IN32X", LIEF::assembly::riscv::OPCODE::FLT_D_IN32X) + .value("FLT_D_INX", LIEF::assembly::riscv::OPCODE::FLT_D_INX) + .value("FLT_H", LIEF::assembly::riscv::OPCODE::FLT_H) + .value("FLT_H_INX", LIEF::assembly::riscv::OPCODE::FLT_H_INX) + .value("FLT_Q", LIEF::assembly::riscv::OPCODE::FLT_Q) + .value("FLT_S", LIEF::assembly::riscv::OPCODE::FLT_S) + .value("FLT_S_INX", LIEF::assembly::riscv::OPCODE::FLT_S_INX) + .value("FLW", LIEF::assembly::riscv::OPCODE::FLW) + .value("FMADD_D", LIEF::assembly::riscv::OPCODE::FMADD_D) + .value("FMADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FMADD_D_IN32X) + .value("FMADD_D_INX", LIEF::assembly::riscv::OPCODE::FMADD_D_INX) + .value("FMADD_H", LIEF::assembly::riscv::OPCODE::FMADD_H) + .value("FMADD_H_INX", LIEF::assembly::riscv::OPCODE::FMADD_H_INX) + .value("FMADD_Q", LIEF::assembly::riscv::OPCODE::FMADD_Q) + .value("FMADD_S", LIEF::assembly::riscv::OPCODE::FMADD_S) + .value("FMADD_S_INX", LIEF::assembly::riscv::OPCODE::FMADD_S_INX) + .value("FMAXM_D", LIEF::assembly::riscv::OPCODE::FMAXM_D) + .value("FMAXM_H", LIEF::assembly::riscv::OPCODE::FMAXM_H) + .value("FMAXM_Q", LIEF::assembly::riscv::OPCODE::FMAXM_Q) + .value("FMAXM_S", LIEF::assembly::riscv::OPCODE::FMAXM_S) + .value("FMAX_D", LIEF::assembly::riscv::OPCODE::FMAX_D) + .value("FMAX_D_IN32X", LIEF::assembly::riscv::OPCODE::FMAX_D_IN32X) + .value("FMAX_D_INX", LIEF::assembly::riscv::OPCODE::FMAX_D_INX) + .value("FMAX_H", LIEF::assembly::riscv::OPCODE::FMAX_H) + .value("FMAX_H_INX", LIEF::assembly::riscv::OPCODE::FMAX_H_INX) + .value("FMAX_Q", LIEF::assembly::riscv::OPCODE::FMAX_Q) + .value("FMAX_S", LIEF::assembly::riscv::OPCODE::FMAX_S) + .value("FMAX_S_INX", LIEF::assembly::riscv::OPCODE::FMAX_S_INX) + .value("FMINM_D", LIEF::assembly::riscv::OPCODE::FMINM_D) + .value("FMINM_H", LIEF::assembly::riscv::OPCODE::FMINM_H) + .value("FMINM_Q", LIEF::assembly::riscv::OPCODE::FMINM_Q) + .value("FMINM_S", LIEF::assembly::riscv::OPCODE::FMINM_S) + .value("FMIN_D", LIEF::assembly::riscv::OPCODE::FMIN_D) + .value("FMIN_D_IN32X", LIEF::assembly::riscv::OPCODE::FMIN_D_IN32X) + .value("FMIN_D_INX", LIEF::assembly::riscv::OPCODE::FMIN_D_INX) + .value("FMIN_H", LIEF::assembly::riscv::OPCODE::FMIN_H) + .value("FMIN_H_INX", LIEF::assembly::riscv::OPCODE::FMIN_H_INX) + .value("FMIN_Q", LIEF::assembly::riscv::OPCODE::FMIN_Q) + .value("FMIN_S", LIEF::assembly::riscv::OPCODE::FMIN_S) + .value("FMIN_S_INX", LIEF::assembly::riscv::OPCODE::FMIN_S_INX) + .value("FMSUB_D", LIEF::assembly::riscv::OPCODE::FMSUB_D) + .value("FMSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FMSUB_D_IN32X) + .value("FMSUB_D_INX", LIEF::assembly::riscv::OPCODE::FMSUB_D_INX) + .value("FMSUB_H", LIEF::assembly::riscv::OPCODE::FMSUB_H) + .value("FMSUB_H_INX", LIEF::assembly::riscv::OPCODE::FMSUB_H_INX) + .value("FMSUB_Q", LIEF::assembly::riscv::OPCODE::FMSUB_Q) + .value("FMSUB_S", LIEF::assembly::riscv::OPCODE::FMSUB_S) + .value("FMSUB_S_INX", LIEF::assembly::riscv::OPCODE::FMSUB_S_INX) + .value("FMUL_D", LIEF::assembly::riscv::OPCODE::FMUL_D) + .value("FMUL_D_IN32X", LIEF::assembly::riscv::OPCODE::FMUL_D_IN32X) + .value("FMUL_D_INX", LIEF::assembly::riscv::OPCODE::FMUL_D_INX) + .value("FMUL_H", LIEF::assembly::riscv::OPCODE::FMUL_H) + .value("FMUL_H_INX", LIEF::assembly::riscv::OPCODE::FMUL_H_INX) + .value("FMUL_Q", LIEF::assembly::riscv::OPCODE::FMUL_Q) + .value("FMUL_S", LIEF::assembly::riscv::OPCODE::FMUL_S) + .value("FMUL_S_INX", LIEF::assembly::riscv::OPCODE::FMUL_S_INX) + .value("FMVH_X_D", LIEF::assembly::riscv::OPCODE::FMVH_X_D) + .value("FMVH_X_Q", LIEF::assembly::riscv::OPCODE::FMVH_X_Q) + .value("FMVP_D_X", LIEF::assembly::riscv::OPCODE::FMVP_D_X) + .value("FMVP_Q_X", LIEF::assembly::riscv::OPCODE::FMVP_Q_X) + .value("FMV_D_X", LIEF::assembly::riscv::OPCODE::FMV_D_X) + .value("FMV_H_X", LIEF::assembly::riscv::OPCODE::FMV_H_X) + .value("FMV_W_X", LIEF::assembly::riscv::OPCODE::FMV_W_X) + .value("FMV_X_D", LIEF::assembly::riscv::OPCODE::FMV_X_D) + .value("FMV_X_H", LIEF::assembly::riscv::OPCODE::FMV_X_H) + .value("FMV_X_W", LIEF::assembly::riscv::OPCODE::FMV_X_W) + .value("FMV_X_W_FPR64", LIEF::assembly::riscv::OPCODE::FMV_X_W_FPR64) + .value("FNMADD_D", LIEF::assembly::riscv::OPCODE::FNMADD_D) + .value("FNMADD_D_IN32X", LIEF::assembly::riscv::OPCODE::FNMADD_D_IN32X) + .value("FNMADD_D_INX", LIEF::assembly::riscv::OPCODE::FNMADD_D_INX) + .value("FNMADD_H", LIEF::assembly::riscv::OPCODE::FNMADD_H) + .value("FNMADD_H_INX", LIEF::assembly::riscv::OPCODE::FNMADD_H_INX) + .value("FNMADD_Q", LIEF::assembly::riscv::OPCODE::FNMADD_Q) + .value("FNMADD_S", LIEF::assembly::riscv::OPCODE::FNMADD_S) + .value("FNMADD_S_INX", LIEF::assembly::riscv::OPCODE::FNMADD_S_INX) + .value("FNMSUB_D", LIEF::assembly::riscv::OPCODE::FNMSUB_D) + .value("FNMSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FNMSUB_D_IN32X) + .value("FNMSUB_D_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_D_INX) + .value("FNMSUB_H", LIEF::assembly::riscv::OPCODE::FNMSUB_H) + .value("FNMSUB_H_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_H_INX) + .value("FNMSUB_Q", LIEF::assembly::riscv::OPCODE::FNMSUB_Q) + .value("FNMSUB_S", LIEF::assembly::riscv::OPCODE::FNMSUB_S) + .value("FNMSUB_S_INX", LIEF::assembly::riscv::OPCODE::FNMSUB_S_INX) + .value("FROUNDNX_D", LIEF::assembly::riscv::OPCODE::FROUNDNX_D) + .value("FROUNDNX_H", LIEF::assembly::riscv::OPCODE::FROUNDNX_H) + .value("FROUNDNX_Q", LIEF::assembly::riscv::OPCODE::FROUNDNX_Q) + .value("FROUNDNX_S", LIEF::assembly::riscv::OPCODE::FROUNDNX_S) + .value("FROUND_D", LIEF::assembly::riscv::OPCODE::FROUND_D) + .value("FROUND_H", LIEF::assembly::riscv::OPCODE::FROUND_H) + .value("FROUND_Q", LIEF::assembly::riscv::OPCODE::FROUND_Q) + .value("FROUND_S", LIEF::assembly::riscv::OPCODE::FROUND_S) + .value("FSD", LIEF::assembly::riscv::OPCODE::FSD) + .value("FSGNJN_D", LIEF::assembly::riscv::OPCODE::FSGNJN_D) + .value("FSGNJN_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJN_D_IN32X) + .value("FSGNJN_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_D_INX) + .value("FSGNJN_H", LIEF::assembly::riscv::OPCODE::FSGNJN_H) + .value("FSGNJN_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_H_INX) + .value("FSGNJN_Q", LIEF::assembly::riscv::OPCODE::FSGNJN_Q) + .value("FSGNJN_S", LIEF::assembly::riscv::OPCODE::FSGNJN_S) + .value("FSGNJN_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJN_S_INX) + .value("FSGNJX_D", LIEF::assembly::riscv::OPCODE::FSGNJX_D) + .value("FSGNJX_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJX_D_IN32X) + .value("FSGNJX_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_D_INX) + .value("FSGNJX_H", LIEF::assembly::riscv::OPCODE::FSGNJX_H) + .value("FSGNJX_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_H_INX) + .value("FSGNJX_Q", LIEF::assembly::riscv::OPCODE::FSGNJX_Q) + .value("FSGNJX_S", LIEF::assembly::riscv::OPCODE::FSGNJX_S) + .value("FSGNJX_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJX_S_INX) + .value("FSGNJ_D", LIEF::assembly::riscv::OPCODE::FSGNJ_D) + .value("FSGNJ_D_IN32X", LIEF::assembly::riscv::OPCODE::FSGNJ_D_IN32X) + .value("FSGNJ_D_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_D_INX) + .value("FSGNJ_H", LIEF::assembly::riscv::OPCODE::FSGNJ_H) + .value("FSGNJ_H_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_H_INX) + .value("FSGNJ_Q", LIEF::assembly::riscv::OPCODE::FSGNJ_Q) + .value("FSGNJ_S", LIEF::assembly::riscv::OPCODE::FSGNJ_S) + .value("FSGNJ_S_INX", LIEF::assembly::riscv::OPCODE::FSGNJ_S_INX) + .value("FSH", LIEF::assembly::riscv::OPCODE::FSH) + .value("FSQ", LIEF::assembly::riscv::OPCODE::FSQ) + .value("FSQRT_D", LIEF::assembly::riscv::OPCODE::FSQRT_D) + .value("FSQRT_D_IN32X", LIEF::assembly::riscv::OPCODE::FSQRT_D_IN32X) + .value("FSQRT_D_INX", LIEF::assembly::riscv::OPCODE::FSQRT_D_INX) + .value("FSQRT_H", LIEF::assembly::riscv::OPCODE::FSQRT_H) + .value("FSQRT_H_INX", LIEF::assembly::riscv::OPCODE::FSQRT_H_INX) + .value("FSQRT_Q", LIEF::assembly::riscv::OPCODE::FSQRT_Q) + .value("FSQRT_S", LIEF::assembly::riscv::OPCODE::FSQRT_S) + .value("FSQRT_S_INX", LIEF::assembly::riscv::OPCODE::FSQRT_S_INX) + .value("FSUB_D", LIEF::assembly::riscv::OPCODE::FSUB_D) + .value("FSUB_D_IN32X", LIEF::assembly::riscv::OPCODE::FSUB_D_IN32X) + .value("FSUB_D_INX", LIEF::assembly::riscv::OPCODE::FSUB_D_INX) + .value("FSUB_H", LIEF::assembly::riscv::OPCODE::FSUB_H) + .value("FSUB_H_INX", LIEF::assembly::riscv::OPCODE::FSUB_H_INX) + .value("FSUB_Q", LIEF::assembly::riscv::OPCODE::FSUB_Q) + .value("FSUB_S", LIEF::assembly::riscv::OPCODE::FSUB_S) + .value("FSUB_S_INX", LIEF::assembly::riscv::OPCODE::FSUB_S_INX) + .value("FSW", LIEF::assembly::riscv::OPCODE::FSW) + .value("HFENCE_GVMA", LIEF::assembly::riscv::OPCODE::HFENCE_GVMA) + .value("HFENCE_VVMA", LIEF::assembly::riscv::OPCODE::HFENCE_VVMA) + .value("HINVAL_GVMA", LIEF::assembly::riscv::OPCODE::HINVAL_GVMA) + .value("HINVAL_VVMA", LIEF::assembly::riscv::OPCODE::HINVAL_VVMA) + .value("HLVX_HU", LIEF::assembly::riscv::OPCODE::HLVX_HU) + .value("HLVX_WU", LIEF::assembly::riscv::OPCODE::HLVX_WU) + .value("HLV_B", LIEF::assembly::riscv::OPCODE::HLV_B) + .value("HLV_BU", LIEF::assembly::riscv::OPCODE::HLV_BU) + .value("HLV_D", LIEF::assembly::riscv::OPCODE::HLV_D) + .value("HLV_H", LIEF::assembly::riscv::OPCODE::HLV_H) + .value("HLV_HU", LIEF::assembly::riscv::OPCODE::HLV_HU) + .value("HLV_W", LIEF::assembly::riscv::OPCODE::HLV_W) + .value("HLV_WU", LIEF::assembly::riscv::OPCODE::HLV_WU) + .value("HSV_B", LIEF::assembly::riscv::OPCODE::HSV_B) + .value("HSV_D", LIEF::assembly::riscv::OPCODE::HSV_D) + .value("HSV_H", LIEF::assembly::riscv::OPCODE::HSV_H) + .value("HSV_W", LIEF::assembly::riscv::OPCODE::HSV_W) + .value("Insn16", LIEF::assembly::riscv::OPCODE::Insn16) + .value("Insn32", LIEF::assembly::riscv::OPCODE::Insn32) + .value("Insn48", LIEF::assembly::riscv::OPCODE::Insn48) + .value("Insn64", LIEF::assembly::riscv::OPCODE::Insn64) + .value("InsnB", LIEF::assembly::riscv::OPCODE::InsnB) + .value("InsnCA", LIEF::assembly::riscv::OPCODE::InsnCA) + .value("InsnCB", LIEF::assembly::riscv::OPCODE::InsnCB) + .value("InsnCI", LIEF::assembly::riscv::OPCODE::InsnCI) + .value("InsnCIW", LIEF::assembly::riscv::OPCODE::InsnCIW) + .value("InsnCJ", LIEF::assembly::riscv::OPCODE::InsnCJ) + .value("InsnCL", LIEF::assembly::riscv::OPCODE::InsnCL) + .value("InsnCR", LIEF::assembly::riscv::OPCODE::InsnCR) + .value("InsnCS", LIEF::assembly::riscv::OPCODE::InsnCS) + .value("InsnCSS", LIEF::assembly::riscv::OPCODE::InsnCSS) + .value("InsnI", LIEF::assembly::riscv::OPCODE::InsnI) + .value("InsnI_Mem", LIEF::assembly::riscv::OPCODE::InsnI_Mem) + .value("InsnJ", LIEF::assembly::riscv::OPCODE::InsnJ) + .value("InsnQC_EAI", LIEF::assembly::riscv::OPCODE::InsnQC_EAI) + .value("InsnQC_EB", LIEF::assembly::riscv::OPCODE::InsnQC_EB) + .value("InsnQC_EI", LIEF::assembly::riscv::OPCODE::InsnQC_EI) + .value("InsnQC_EI_Mem", LIEF::assembly::riscv::OPCODE::InsnQC_EI_Mem) + .value("InsnQC_EJ", LIEF::assembly::riscv::OPCODE::InsnQC_EJ) + .value("InsnQC_ES", LIEF::assembly::riscv::OPCODE::InsnQC_ES) + .value("InsnR", LIEF::assembly::riscv::OPCODE::InsnR) + .value("InsnR4", LIEF::assembly::riscv::OPCODE::InsnR4) + .value("InsnS", LIEF::assembly::riscv::OPCODE::InsnS) + .value("InsnU", LIEF::assembly::riscv::OPCODE::InsnU) + .value("JAL", LIEF::assembly::riscv::OPCODE::JAL) + .value("JALR", LIEF::assembly::riscv::OPCODE::JALR) + .value("LB", LIEF::assembly::riscv::OPCODE::LB) + .value("LBU", LIEF::assembly::riscv::OPCODE::LBU) + .value("LB_AQ", LIEF::assembly::riscv::OPCODE::LB_AQ) + .value("LB_AQRL", LIEF::assembly::riscv::OPCODE::LB_AQRL) + .value("LD", LIEF::assembly::riscv::OPCODE::LD) + .value("LD_AQ", LIEF::assembly::riscv::OPCODE::LD_AQ) + .value("LD_AQRL", LIEF::assembly::riscv::OPCODE::LD_AQRL) + .value("LD_RV32", LIEF::assembly::riscv::OPCODE::LD_RV32) + .value("LH", LIEF::assembly::riscv::OPCODE::LH) + .value("LHU", LIEF::assembly::riscv::OPCODE::LHU) + .value("LH_AQ", LIEF::assembly::riscv::OPCODE::LH_AQ) + .value("LH_AQRL", LIEF::assembly::riscv::OPCODE::LH_AQRL) + .value("LH_INX", LIEF::assembly::riscv::OPCODE::LH_INX) + .value("LR_D", LIEF::assembly::riscv::OPCODE::LR_D) + .value("LR_D_AQ", LIEF::assembly::riscv::OPCODE::LR_D_AQ) + .value("LR_D_AQRL", LIEF::assembly::riscv::OPCODE::LR_D_AQRL) + .value("LR_D_RL", LIEF::assembly::riscv::OPCODE::LR_D_RL) + .value("LR_W", LIEF::assembly::riscv::OPCODE::LR_W) + .value("LR_W_AQ", LIEF::assembly::riscv::OPCODE::LR_W_AQ) + .value("LR_W_AQRL", LIEF::assembly::riscv::OPCODE::LR_W_AQRL) + .value("LR_W_RL", LIEF::assembly::riscv::OPCODE::LR_W_RL) + .value("LUI", LIEF::assembly::riscv::OPCODE::LUI) + .value("LW", LIEF::assembly::riscv::OPCODE::LW) + .value("LWU", LIEF::assembly::riscv::OPCODE::LWU) + .value("LW_AQ", LIEF::assembly::riscv::OPCODE::LW_AQ) + .value("LW_AQRL", LIEF::assembly::riscv::OPCODE::LW_AQRL) + .value("LW_INX", LIEF::assembly::riscv::OPCODE::LW_INX) + .value("MACCSU_H00", LIEF::assembly::riscv::OPCODE::MACCSU_H00) + .value("MACCSU_H11", LIEF::assembly::riscv::OPCODE::MACCSU_H11) + .value("MACCSU_W00", LIEF::assembly::riscv::OPCODE::MACCSU_W00) + .value("MACCSU_W11", LIEF::assembly::riscv::OPCODE::MACCSU_W11) + .value("MACCU_H00", LIEF::assembly::riscv::OPCODE::MACCU_H00) + .value("MACCU_H01", LIEF::assembly::riscv::OPCODE::MACCU_H01) + .value("MACCU_H11", LIEF::assembly::riscv::OPCODE::MACCU_H11) + .value("MACCU_W00", LIEF::assembly::riscv::OPCODE::MACCU_W00) + .value("MACCU_W01", LIEF::assembly::riscv::OPCODE::MACCU_W01) + .value("MACCU_W11", LIEF::assembly::riscv::OPCODE::MACCU_W11) + .value("MACC_H00", LIEF::assembly::riscv::OPCODE::MACC_H00) + .value("MACC_H01", LIEF::assembly::riscv::OPCODE::MACC_H01) + .value("MACC_H11", LIEF::assembly::riscv::OPCODE::MACC_H11) + .value("MACC_W00", LIEF::assembly::riscv::OPCODE::MACC_W00) + .value("MACC_W01", LIEF::assembly::riscv::OPCODE::MACC_W01) + .value("MACC_W11", LIEF::assembly::riscv::OPCODE::MACC_W11) + .value("MAX", LIEF::assembly::riscv::OPCODE::MAX) + .value("MAXU", LIEF::assembly::riscv::OPCODE::MAXU) + .value("MERGE", LIEF::assembly::riscv::OPCODE::MERGE) + .value("MHACC", LIEF::assembly::riscv::OPCODE::MHACC) + .value("MHACCSU", LIEF::assembly::riscv::OPCODE::MHACCSU) + .value("MHACCSU_H0", LIEF::assembly::riscv::OPCODE::MHACCSU_H0) + .value("MHACCSU_H1", LIEF::assembly::riscv::OPCODE::MHACCSU_H1) + .value("MHACCU", LIEF::assembly::riscv::OPCODE::MHACCU) + .value("MHACC_H0", LIEF::assembly::riscv::OPCODE::MHACC_H0) + .value("MHACC_H1", LIEF::assembly::riscv::OPCODE::MHACC_H1) + .value("MHRACC", LIEF::assembly::riscv::OPCODE::MHRACC) + .value("MHRACCSU", LIEF::assembly::riscv::OPCODE::MHRACCSU) + .value("MHRACCU", LIEF::assembly::riscv::OPCODE::MHRACCU) + .value("MIN", LIEF::assembly::riscv::OPCODE::MIN) + .value("MINU", LIEF::assembly::riscv::OPCODE::MINU) + .value("MIPS_CCMOV", LIEF::assembly::riscv::OPCODE::MIPS_CCMOV) + .value("MIPS_EHB", LIEF::assembly::riscv::OPCODE::MIPS_EHB) + .value("MIPS_IHB", LIEF::assembly::riscv::OPCODE::MIPS_IHB) + .value("MIPS_LDP", LIEF::assembly::riscv::OPCODE::MIPS_LDP) + .value("MIPS_LWP", LIEF::assembly::riscv::OPCODE::MIPS_LWP) + .value("MIPS_PAUSE", LIEF::assembly::riscv::OPCODE::MIPS_PAUSE); + opcodes.value("MIPS_PREF", LIEF::assembly::riscv::OPCODE::MIPS_PREF) + .value("MIPS_SDP", LIEF::assembly::riscv::OPCODE::MIPS_SDP) + .value("MIPS_SWP", LIEF::assembly::riscv::OPCODE::MIPS_SWP) + .value("MNRET", LIEF::assembly::riscv::OPCODE::MNRET) + .value("MOP_RR_0", LIEF::assembly::riscv::OPCODE::MOP_RR_0) + .value("MOP_RR_1", LIEF::assembly::riscv::OPCODE::MOP_RR_1) + .value("MOP_RR_2", LIEF::assembly::riscv::OPCODE::MOP_RR_2) + .value("MOP_RR_3", LIEF::assembly::riscv::OPCODE::MOP_RR_3) + .value("MOP_RR_4", LIEF::assembly::riscv::OPCODE::MOP_RR_4) + .value("MOP_RR_5", LIEF::assembly::riscv::OPCODE::MOP_RR_5) + .value("MOP_RR_6", LIEF::assembly::riscv::OPCODE::MOP_RR_6) + .value("MOP_RR_7", LIEF::assembly::riscv::OPCODE::MOP_RR_7) + .value("MOP_R_0", LIEF::assembly::riscv::OPCODE::MOP_R_0) + .value("MOP_R_1", LIEF::assembly::riscv::OPCODE::MOP_R_1) + .value("MOP_R_10", LIEF::assembly::riscv::OPCODE::MOP_R_10) + .value("MOP_R_11", LIEF::assembly::riscv::OPCODE::MOP_R_11) + .value("MOP_R_12", LIEF::assembly::riscv::OPCODE::MOP_R_12) + .value("MOP_R_13", LIEF::assembly::riscv::OPCODE::MOP_R_13) + .value("MOP_R_14", LIEF::assembly::riscv::OPCODE::MOP_R_14) + .value("MOP_R_15", LIEF::assembly::riscv::OPCODE::MOP_R_15) + .value("MOP_R_16", LIEF::assembly::riscv::OPCODE::MOP_R_16) + .value("MOP_R_17", LIEF::assembly::riscv::OPCODE::MOP_R_17) + .value("MOP_R_18", LIEF::assembly::riscv::OPCODE::MOP_R_18) + .value("MOP_R_19", LIEF::assembly::riscv::OPCODE::MOP_R_19) + .value("MOP_R_2", LIEF::assembly::riscv::OPCODE::MOP_R_2) + .value("MOP_R_20", LIEF::assembly::riscv::OPCODE::MOP_R_20) + .value("MOP_R_21", LIEF::assembly::riscv::OPCODE::MOP_R_21) + .value("MOP_R_22", LIEF::assembly::riscv::OPCODE::MOP_R_22) + .value("MOP_R_23", LIEF::assembly::riscv::OPCODE::MOP_R_23) + .value("MOP_R_24", LIEF::assembly::riscv::OPCODE::MOP_R_24) + .value("MOP_R_25", LIEF::assembly::riscv::OPCODE::MOP_R_25) + .value("MOP_R_26", LIEF::assembly::riscv::OPCODE::MOP_R_26) + .value("MOP_R_27", LIEF::assembly::riscv::OPCODE::MOP_R_27) + .value("MOP_R_28", LIEF::assembly::riscv::OPCODE::MOP_R_28) + .value("MOP_R_29", LIEF::assembly::riscv::OPCODE::MOP_R_29) + .value("MOP_R_3", LIEF::assembly::riscv::OPCODE::MOP_R_3) + .value("MOP_R_30", LIEF::assembly::riscv::OPCODE::MOP_R_30) + .value("MOP_R_31", LIEF::assembly::riscv::OPCODE::MOP_R_31) + .value("MOP_R_4", LIEF::assembly::riscv::OPCODE::MOP_R_4) + .value("MOP_R_5", LIEF::assembly::riscv::OPCODE::MOP_R_5) + .value("MOP_R_6", LIEF::assembly::riscv::OPCODE::MOP_R_6) + .value("MOP_R_7", LIEF::assembly::riscv::OPCODE::MOP_R_7) + .value("MOP_R_8", LIEF::assembly::riscv::OPCODE::MOP_R_8) + .value("MOP_R_9", LIEF::assembly::riscv::OPCODE::MOP_R_9) + .value("MQACC_H00", LIEF::assembly::riscv::OPCODE::MQACC_H00) + .value("MQACC_H01", LIEF::assembly::riscv::OPCODE::MQACC_H01) + .value("MQACC_H11", LIEF::assembly::riscv::OPCODE::MQACC_H11) + .value("MQACC_W00", LIEF::assembly::riscv::OPCODE::MQACC_W00) + .value("MQACC_W01", LIEF::assembly::riscv::OPCODE::MQACC_W01) + .value("MQACC_W11", LIEF::assembly::riscv::OPCODE::MQACC_W11) + .value("MQRACC_H00", LIEF::assembly::riscv::OPCODE::MQRACC_H00) + .value("MQRACC_H01", LIEF::assembly::riscv::OPCODE::MQRACC_H01) + .value("MQRACC_H11", LIEF::assembly::riscv::OPCODE::MQRACC_H11) + .value("MQRACC_W00", LIEF::assembly::riscv::OPCODE::MQRACC_W00) + .value("MQRACC_W01", LIEF::assembly::riscv::OPCODE::MQRACC_W01) + .value("MQRACC_W11", LIEF::assembly::riscv::OPCODE::MQRACC_W11) + .value("MRET", LIEF::assembly::riscv::OPCODE::MRET) + .value("MSEQ", LIEF::assembly::riscv::OPCODE::MSEQ) + .value("MSLT", LIEF::assembly::riscv::OPCODE::MSLT) + .value("MSLTU", LIEF::assembly::riscv::OPCODE::MSLTU) + .value("MUL", LIEF::assembly::riscv::OPCODE::MUL) + .value("MULH", LIEF::assembly::riscv::OPCODE::MULH) + .value("MULHR", LIEF::assembly::riscv::OPCODE::MULHR) + .value("MULHRSU", LIEF::assembly::riscv::OPCODE::MULHRSU) + .value("MULHRU", LIEF::assembly::riscv::OPCODE::MULHRU) + .value("MULHSU", LIEF::assembly::riscv::OPCODE::MULHSU) + .value("MULHSU_H0", LIEF::assembly::riscv::OPCODE::MULHSU_H0) + .value("MULHSU_H1", LIEF::assembly::riscv::OPCODE::MULHSU_H1) + .value("MULHU", LIEF::assembly::riscv::OPCODE::MULHU) + .value("MULH_H0", LIEF::assembly::riscv::OPCODE::MULH_H0) + .value("MULH_H1", LIEF::assembly::riscv::OPCODE::MULH_H1) + .value("MULQ", LIEF::assembly::riscv::OPCODE::MULQ) + .value("MULQR", LIEF::assembly::riscv::OPCODE::MULQR) + .value("MULSU_H00", LIEF::assembly::riscv::OPCODE::MULSU_H00) + .value("MULSU_H11", LIEF::assembly::riscv::OPCODE::MULSU_H11) + .value("MULSU_W00", LIEF::assembly::riscv::OPCODE::MULSU_W00) + .value("MULSU_W11", LIEF::assembly::riscv::OPCODE::MULSU_W11) + .value("MULU_H00", LIEF::assembly::riscv::OPCODE::MULU_H00) + .value("MULU_H01", LIEF::assembly::riscv::OPCODE::MULU_H01) + .value("MULU_H11", LIEF::assembly::riscv::OPCODE::MULU_H11) + .value("MULU_W00", LIEF::assembly::riscv::OPCODE::MULU_W00) + .value("MULU_W01", LIEF::assembly::riscv::OPCODE::MULU_W01) + .value("MULU_W11", LIEF::assembly::riscv::OPCODE::MULU_W11) + .value("MULW", LIEF::assembly::riscv::OPCODE::MULW) + .value("MUL_H00", LIEF::assembly::riscv::OPCODE::MUL_H00) + .value("MUL_H01", LIEF::assembly::riscv::OPCODE::MUL_H01) + .value("MUL_H11", LIEF::assembly::riscv::OPCODE::MUL_H11) + .value("MUL_W00", LIEF::assembly::riscv::OPCODE::MUL_W00) + .value("MUL_W01", LIEF::assembly::riscv::OPCODE::MUL_W01) + .value("MUL_W11", LIEF::assembly::riscv::OPCODE::MUL_W11) + .value("MVM", LIEF::assembly::riscv::OPCODE::MVM) + .value("MVMN", LIEF::assembly::riscv::OPCODE::MVMN) + .value("NCLIP", LIEF::assembly::riscv::OPCODE::NCLIP) + .value("NCLIPI", LIEF::assembly::riscv::OPCODE::NCLIPI) + .value("NCLIPIU", LIEF::assembly::riscv::OPCODE::NCLIPIU) + .value("NCLIPR", LIEF::assembly::riscv::OPCODE::NCLIPR) + .value("NCLIPRI", LIEF::assembly::riscv::OPCODE::NCLIPRI) + .value("NCLIPRIU", LIEF::assembly::riscv::OPCODE::NCLIPRIU) + .value("NCLIPRU", LIEF::assembly::riscv::OPCODE::NCLIPRU) + .value("NCLIPU", LIEF::assembly::riscv::OPCODE::NCLIPU) + .value("NDS_ADDIGP", LIEF::assembly::riscv::OPCODE::NDS_ADDIGP) + .value("NDS_BBC", LIEF::assembly::riscv::OPCODE::NDS_BBC) + .value("NDS_BBS", LIEF::assembly::riscv::OPCODE::NDS_BBS) + .value("NDS_BEQC", LIEF::assembly::riscv::OPCODE::NDS_BEQC) + .value("NDS_BFOS", LIEF::assembly::riscv::OPCODE::NDS_BFOS) + .value("NDS_BFOZ", LIEF::assembly::riscv::OPCODE::NDS_BFOZ) + .value("NDS_BNEC", LIEF::assembly::riscv::OPCODE::NDS_BNEC) + .value("NDS_FCVT_BF16_S", LIEF::assembly::riscv::OPCODE::NDS_FCVT_BF16_S) + .value("NDS_FCVT_S_BF16", LIEF::assembly::riscv::OPCODE::NDS_FCVT_S_BF16) + .value("NDS_FFB", LIEF::assembly::riscv::OPCODE::NDS_FFB) + .value("NDS_FFMISM", LIEF::assembly::riscv::OPCODE::NDS_FFMISM) + .value("NDS_FFZMISM", LIEF::assembly::riscv::OPCODE::NDS_FFZMISM) + .value("NDS_FLMISM", LIEF::assembly::riscv::OPCODE::NDS_FLMISM) + .value("NDS_FMV_BF16_X", LIEF::assembly::riscv::OPCODE::NDS_FMV_BF16_X) + .value("NDS_FMV_X_BF16", LIEF::assembly::riscv::OPCODE::NDS_FMV_X_BF16) + .value("NDS_LBGP", LIEF::assembly::riscv::OPCODE::NDS_LBGP) + .value("NDS_LBUGP", LIEF::assembly::riscv::OPCODE::NDS_LBUGP) + .value("NDS_LDGP", LIEF::assembly::riscv::OPCODE::NDS_LDGP) + .value("NDS_LEA_B_ZE", LIEF::assembly::riscv::OPCODE::NDS_LEA_B_ZE) + .value("NDS_LEA_D", LIEF::assembly::riscv::OPCODE::NDS_LEA_D) + .value("NDS_LEA_D_ZE", LIEF::assembly::riscv::OPCODE::NDS_LEA_D_ZE) + .value("NDS_LEA_H", LIEF::assembly::riscv::OPCODE::NDS_LEA_H) + .value("NDS_LEA_H_ZE", LIEF::assembly::riscv::OPCODE::NDS_LEA_H_ZE) + .value("NDS_LEA_W", LIEF::assembly::riscv::OPCODE::NDS_LEA_W) + .value("NDS_LEA_W_ZE", LIEF::assembly::riscv::OPCODE::NDS_LEA_W_ZE) + .value("NDS_LHGP", LIEF::assembly::riscv::OPCODE::NDS_LHGP) + .value("NDS_LHUGP", LIEF::assembly::riscv::OPCODE::NDS_LHUGP) + .value("NDS_LWGP", LIEF::assembly::riscv::OPCODE::NDS_LWGP) + .value("NDS_LWUGP", LIEF::assembly::riscv::OPCODE::NDS_LWUGP) + .value("NDS_SBGP", LIEF::assembly::riscv::OPCODE::NDS_SBGP) + .value("NDS_SDGP", LIEF::assembly::riscv::OPCODE::NDS_SDGP) + .value("NDS_SHGP", LIEF::assembly::riscv::OPCODE::NDS_SHGP) + .value("NDS_SWGP", LIEF::assembly::riscv::OPCODE::NDS_SWGP) + .value("NDS_VD4DOTSU_VV", LIEF::assembly::riscv::OPCODE::NDS_VD4DOTSU_VV) + .value("NDS_VD4DOTS_VV", LIEF::assembly::riscv::OPCODE::NDS_VD4DOTS_VV) + .value("NDS_VD4DOTU_VV", LIEF::assembly::riscv::OPCODE::NDS_VD4DOTU_VV) + .value("NDS_VFNCVT_BF16_S", LIEF::assembly::riscv::OPCODE::NDS_VFNCVT_BF16_S) + .value("NDS_VFPMADB_VF", LIEF::assembly::riscv::OPCODE::NDS_VFPMADB_VF) + .value("NDS_VFPMADT_VF", LIEF::assembly::riscv::OPCODE::NDS_VFPMADT_VF) + .value("NDS_VFWCVT_F_B", LIEF::assembly::riscv::OPCODE::NDS_VFWCVT_F_B) + .value("NDS_VFWCVT_F_BU", LIEF::assembly::riscv::OPCODE::NDS_VFWCVT_F_BU) + .value("NDS_VFWCVT_F_N", LIEF::assembly::riscv::OPCODE::NDS_VFWCVT_F_N) + .value("NDS_VFWCVT_F_NU", LIEF::assembly::riscv::OPCODE::NDS_VFWCVT_F_NU) + .value("NDS_VFWCVT_S_BF16", LIEF::assembly::riscv::OPCODE::NDS_VFWCVT_S_BF16) + .value("NDS_VLE4_V", LIEF::assembly::riscv::OPCODE::NDS_VLE4_V) + .value("NDS_VLN8_V", LIEF::assembly::riscv::OPCODE::NDS_VLN8_V) + .value("NDS_VLNU8_V", LIEF::assembly::riscv::OPCODE::NDS_VLNU8_V) + .value("NSARI", LIEF::assembly::riscv::OPCODE::NSARI) + .value("NSRA", LIEF::assembly::riscv::OPCODE::NSRA) + .value("NSRAI", LIEF::assembly::riscv::OPCODE::NSRAI) + .value("NSRAR", LIEF::assembly::riscv::OPCODE::NSRAR) + .value("NSRL", LIEF::assembly::riscv::OPCODE::NSRL) + .value("NSRLI", LIEF::assembly::riscv::OPCODE::NSRLI) + .value("OR", LIEF::assembly::riscv::OPCODE::OR) + .value("ORC_B", LIEF::assembly::riscv::OPCODE::ORC_B) + .value("ORI", LIEF::assembly::riscv::OPCODE::ORI) + .value("ORN", LIEF::assembly::riscv::OPCODE::ORN) + .value("PAADDU_B", LIEF::assembly::riscv::OPCODE::PAADDU_B) + .value("PAADDU_DB", LIEF::assembly::riscv::OPCODE::PAADDU_DB) + .value("PAADDU_DH", LIEF::assembly::riscv::OPCODE::PAADDU_DH) + .value("PAADDU_DW", LIEF::assembly::riscv::OPCODE::PAADDU_DW) + .value("PAADDU_H", LIEF::assembly::riscv::OPCODE::PAADDU_H) + .value("PAADDU_W", LIEF::assembly::riscv::OPCODE::PAADDU_W) + .value("PAADD_B", LIEF::assembly::riscv::OPCODE::PAADD_B) + .value("PAADD_DB", LIEF::assembly::riscv::OPCODE::PAADD_DB) + .value("PAADD_DH", LIEF::assembly::riscv::OPCODE::PAADD_DH) + .value("PAADD_DW", LIEF::assembly::riscv::OPCODE::PAADD_DW) + .value("PAADD_H", LIEF::assembly::riscv::OPCODE::PAADD_H) + .value("PAADD_W", LIEF::assembly::riscv::OPCODE::PAADD_W) + .value("PAAS_HX", LIEF::assembly::riscv::OPCODE::PAAS_HX) + .value("PAAS_WX", LIEF::assembly::riscv::OPCODE::PAAS_WX) + .value("PAAX_DHX", LIEF::assembly::riscv::OPCODE::PAAX_DHX) + .value("PABDSUMAU_B", LIEF::assembly::riscv::OPCODE::PABDSUMAU_B) + .value("PABDSUMU_B", LIEF::assembly::riscv::OPCODE::PABDSUMU_B) + .value("PABDU_B", LIEF::assembly::riscv::OPCODE::PABDU_B) + .value("PABDU_DB", LIEF::assembly::riscv::OPCODE::PABDU_DB) + .value("PABDU_DH", LIEF::assembly::riscv::OPCODE::PABDU_DH) + .value("PABDU_H", LIEF::assembly::riscv::OPCODE::PABDU_H) + .value("PABD_B", LIEF::assembly::riscv::OPCODE::PABD_B) + .value("PABD_DB", LIEF::assembly::riscv::OPCODE::PABD_DB) + .value("PABD_DH", LIEF::assembly::riscv::OPCODE::PABD_DH) + .value("PABD_H", LIEF::assembly::riscv::OPCODE::PABD_H) + .value("PACK", LIEF::assembly::riscv::OPCODE::PACK) + .value("PACKH", LIEF::assembly::riscv::OPCODE::PACKH) + .value("PACKW", LIEF::assembly::riscv::OPCODE::PACKW) + .value("PADD_B", LIEF::assembly::riscv::OPCODE::PADD_B) + .value("PADD_BS", LIEF::assembly::riscv::OPCODE::PADD_BS) + .value("PADD_DB", LIEF::assembly::riscv::OPCODE::PADD_DB) + .value("PADD_DBS", LIEF::assembly::riscv::OPCODE::PADD_DBS) + .value("PADD_DH", LIEF::assembly::riscv::OPCODE::PADD_DH) + .value("PADD_DHS", LIEF::assembly::riscv::OPCODE::PADD_DHS) + .value("PADD_DW", LIEF::assembly::riscv::OPCODE::PADD_DW) + .value("PADD_DWS", LIEF::assembly::riscv::OPCODE::PADD_DWS) + .value("PADD_H", LIEF::assembly::riscv::OPCODE::PADD_H) + .value("PADD_HS", LIEF::assembly::riscv::OPCODE::PADD_HS) + .value("PADD_W", LIEF::assembly::riscv::OPCODE::PADD_W) + .value("PADD_WS", LIEF::assembly::riscv::OPCODE::PADD_WS) + .value("PASA_DHX", LIEF::assembly::riscv::OPCODE::PASA_DHX) + .value("PASA_HX", LIEF::assembly::riscv::OPCODE::PASA_HX) + .value("PASA_WX", LIEF::assembly::riscv::OPCODE::PASA_WX) + .value("PASUBU_B", LIEF::assembly::riscv::OPCODE::PASUBU_B) + .value("PASUBU_DB", LIEF::assembly::riscv::OPCODE::PASUBU_DB) + .value("PASUBU_DH", LIEF::assembly::riscv::OPCODE::PASUBU_DH) + .value("PASUBU_DW", LIEF::assembly::riscv::OPCODE::PASUBU_DW) + .value("PASUBU_H", LIEF::assembly::riscv::OPCODE::PASUBU_H) + .value("PASUBU_W", LIEF::assembly::riscv::OPCODE::PASUBU_W) + .value("PASUB_B", LIEF::assembly::riscv::OPCODE::PASUB_B) + .value("PASUB_DB", LIEF::assembly::riscv::OPCODE::PASUB_DB) + .value("PASUB_DH", LIEF::assembly::riscv::OPCODE::PASUB_DH) + .value("PASUB_DW", LIEF::assembly::riscv::OPCODE::PASUB_DW) + .value("PASUB_H", LIEF::assembly::riscv::OPCODE::PASUB_H) + .value("PASUB_W", LIEF::assembly::riscv::OPCODE::PASUB_W) + .value("PAS_DHX", LIEF::assembly::riscv::OPCODE::PAS_DHX) + .value("PAS_HX", LIEF::assembly::riscv::OPCODE::PAS_HX) + .value("PAS_WX", LIEF::assembly::riscv::OPCODE::PAS_WX) + .value("PLI_B", LIEF::assembly::riscv::OPCODE::PLI_B) + .value("PLI_DB", LIEF::assembly::riscv::OPCODE::PLI_DB) + .value("PLI_DH", LIEF::assembly::riscv::OPCODE::PLI_DH) + .value("PLI_H", LIEF::assembly::riscv::OPCODE::PLI_H) + .value("PLI_W", LIEF::assembly::riscv::OPCODE::PLI_W) + .value("PLUI_DH", LIEF::assembly::riscv::OPCODE::PLUI_DH) + .value("PLUI_H", LIEF::assembly::riscv::OPCODE::PLUI_H) + .value("PLUI_W", LIEF::assembly::riscv::OPCODE::PLUI_W) + .value("PM2ADDASU_H", LIEF::assembly::riscv::OPCODE::PM2ADDASU_H) + .value("PM2ADDASU_W", LIEF::assembly::riscv::OPCODE::PM2ADDASU_W) + .value("PM2ADDAU_H", LIEF::assembly::riscv::OPCODE::PM2ADDAU_H) + .value("PM2ADDAU_W", LIEF::assembly::riscv::OPCODE::PM2ADDAU_W) + .value("PM2ADDA_H", LIEF::assembly::riscv::OPCODE::PM2ADDA_H) + .value("PM2ADDA_HX", LIEF::assembly::riscv::OPCODE::PM2ADDA_HX) + .value("PM2ADDA_W", LIEF::assembly::riscv::OPCODE::PM2ADDA_W) + .value("PM2ADDA_WX", LIEF::assembly::riscv::OPCODE::PM2ADDA_WX) + .value("PM2ADDSU_H", LIEF::assembly::riscv::OPCODE::PM2ADDSU_H) + .value("PM2ADDSU_W", LIEF::assembly::riscv::OPCODE::PM2ADDSU_W) + .value("PM2ADDU_H", LIEF::assembly::riscv::OPCODE::PM2ADDU_H) + .value("PM2ADDU_W", LIEF::assembly::riscv::OPCODE::PM2ADDU_W) + .value("PM2ADD_H", LIEF::assembly::riscv::OPCODE::PM2ADD_H) + .value("PM2ADD_HX", LIEF::assembly::riscv::OPCODE::PM2ADD_HX) + .value("PM2ADD_W", LIEF::assembly::riscv::OPCODE::PM2ADD_W) + .value("PM2ADD_WX", LIEF::assembly::riscv::OPCODE::PM2ADD_WX) + .value("PM2SADD_H", LIEF::assembly::riscv::OPCODE::PM2SADD_H) + .value("PM2SADD_HX", LIEF::assembly::riscv::OPCODE::PM2SADD_HX) + .value("PM2SUBA_H", LIEF::assembly::riscv::OPCODE::PM2SUBA_H) + .value("PM2SUBA_HX", LIEF::assembly::riscv::OPCODE::PM2SUBA_HX) + .value("PM2SUBA_W", LIEF::assembly::riscv::OPCODE::PM2SUBA_W) + .value("PM2SUBA_WX", LIEF::assembly::riscv::OPCODE::PM2SUBA_WX) + .value("PM2SUB_H", LIEF::assembly::riscv::OPCODE::PM2SUB_H) + .value("PM2SUB_HX", LIEF::assembly::riscv::OPCODE::PM2SUB_HX) + .value("PM2SUB_W", LIEF::assembly::riscv::OPCODE::PM2SUB_W) + .value("PM2SUB_WX", LIEF::assembly::riscv::OPCODE::PM2SUB_WX) + .value("PM2WADDASU_H", LIEF::assembly::riscv::OPCODE::PM2WADDASU_H) + .value("PM2WADDAU_H", LIEF::assembly::riscv::OPCODE::PM2WADDAU_H) + .value("PM2WADDA_H", LIEF::assembly::riscv::OPCODE::PM2WADDA_H) + .value("PM2WADDA_HX", LIEF::assembly::riscv::OPCODE::PM2WADDA_HX) + .value("PM2WADDSU_H", LIEF::assembly::riscv::OPCODE::PM2WADDSU_H) + .value("PM2WADDU_H", LIEF::assembly::riscv::OPCODE::PM2WADDU_H) + .value("PM2WADD_H", LIEF::assembly::riscv::OPCODE::PM2WADD_H) + .value("PM2WADD_HX", LIEF::assembly::riscv::OPCODE::PM2WADD_HX) + .value("PM2WSUBA_H", LIEF::assembly::riscv::OPCODE::PM2WSUBA_H) + .value("PM2WSUBA_HX", LIEF::assembly::riscv::OPCODE::PM2WSUBA_HX) + .value("PM2WSUB_H", LIEF::assembly::riscv::OPCODE::PM2WSUB_H) + .value("PM2WSUB_HX", LIEF::assembly::riscv::OPCODE::PM2WSUB_HX) + .value("PM4ADDASU_B", LIEF::assembly::riscv::OPCODE::PM4ADDASU_B) + .value("PM4ADDASU_H", LIEF::assembly::riscv::OPCODE::PM4ADDASU_H) + .value("PM4ADDAU_B", LIEF::assembly::riscv::OPCODE::PM4ADDAU_B) + .value("PM4ADDAU_H", LIEF::assembly::riscv::OPCODE::PM4ADDAU_H) + .value("PM4ADDA_B", LIEF::assembly::riscv::OPCODE::PM4ADDA_B) + .value("PM4ADDA_H", LIEF::assembly::riscv::OPCODE::PM4ADDA_H) + .value("PM4ADDSU_B", LIEF::assembly::riscv::OPCODE::PM4ADDSU_B) + .value("PM4ADDSU_H", LIEF::assembly::riscv::OPCODE::PM4ADDSU_H) + .value("PM4ADDU_B", LIEF::assembly::riscv::OPCODE::PM4ADDU_B) + .value("PM4ADDU_H", LIEF::assembly::riscv::OPCODE::PM4ADDU_H) + .value("PM4ADD_B", LIEF::assembly::riscv::OPCODE::PM4ADD_B) + .value("PM4ADD_H", LIEF::assembly::riscv::OPCODE::PM4ADD_H) + .value("PMACCSU_W_H00", LIEF::assembly::riscv::OPCODE::PMACCSU_W_H00) + .value("PMACCSU_W_H11", LIEF::assembly::riscv::OPCODE::PMACCSU_W_H11) + .value("PMACCU_W_H00", LIEF::assembly::riscv::OPCODE::PMACCU_W_H00) + .value("PMACCU_W_H01", LIEF::assembly::riscv::OPCODE::PMACCU_W_H01) + .value("PMACCU_W_H11", LIEF::assembly::riscv::OPCODE::PMACCU_W_H11) + .value("PMACC_W_H00", LIEF::assembly::riscv::OPCODE::PMACC_W_H00) + .value("PMACC_W_H01", LIEF::assembly::riscv::OPCODE::PMACC_W_H01) + .value("PMACC_W_H11", LIEF::assembly::riscv::OPCODE::PMACC_W_H11) + .value("PMAXU_B", LIEF::assembly::riscv::OPCODE::PMAXU_B) + .value("PMAXU_DB", LIEF::assembly::riscv::OPCODE::PMAXU_DB) + .value("PMAXU_DH", LIEF::assembly::riscv::OPCODE::PMAXU_DH) + .value("PMAXU_DW", LIEF::assembly::riscv::OPCODE::PMAXU_DW) + .value("PMAXU_H", LIEF::assembly::riscv::OPCODE::PMAXU_H) + .value("PMAXU_W", LIEF::assembly::riscv::OPCODE::PMAXU_W) + .value("PMAX_B", LIEF::assembly::riscv::OPCODE::PMAX_B) + .value("PMAX_DB", LIEF::assembly::riscv::OPCODE::PMAX_DB) + .value("PMAX_DH", LIEF::assembly::riscv::OPCODE::PMAX_DH) + .value("PMAX_DW", LIEF::assembly::riscv::OPCODE::PMAX_DW) + .value("PMAX_H", LIEF::assembly::riscv::OPCODE::PMAX_H) + .value("PMAX_W", LIEF::assembly::riscv::OPCODE::PMAX_W) + .value("PMHACCSU_H", LIEF::assembly::riscv::OPCODE::PMHACCSU_H) + .value("PMHACCSU_H_B0", LIEF::assembly::riscv::OPCODE::PMHACCSU_H_B0) + .value("PMHACCSU_H_B1", LIEF::assembly::riscv::OPCODE::PMHACCSU_H_B1) + .value("PMHACCSU_W", LIEF::assembly::riscv::OPCODE::PMHACCSU_W) + .value("PMHACCSU_W_H0", LIEF::assembly::riscv::OPCODE::PMHACCSU_W_H0) + .value("PMHACCSU_W_H1", LIEF::assembly::riscv::OPCODE::PMHACCSU_W_H1) + .value("PMHACCU_H", LIEF::assembly::riscv::OPCODE::PMHACCU_H); + opcodes.value("PMHACCU_W", LIEF::assembly::riscv::OPCODE::PMHACCU_W) + .value("PMHACC_H", LIEF::assembly::riscv::OPCODE::PMHACC_H) + .value("PMHACC_H_B0", LIEF::assembly::riscv::OPCODE::PMHACC_H_B0) + .value("PMHACC_H_B1", LIEF::assembly::riscv::OPCODE::PMHACC_H_B1) + .value("PMHACC_W", LIEF::assembly::riscv::OPCODE::PMHACC_W) + .value("PMHACC_W_H0", LIEF::assembly::riscv::OPCODE::PMHACC_W_H0) + .value("PMHACC_W_H1", LIEF::assembly::riscv::OPCODE::PMHACC_W_H1) + .value("PMHRACCSU_H", LIEF::assembly::riscv::OPCODE::PMHRACCSU_H) + .value("PMHRACCSU_W", LIEF::assembly::riscv::OPCODE::PMHRACCSU_W) + .value("PMHRACCU_H", LIEF::assembly::riscv::OPCODE::PMHRACCU_H) + .value("PMHRACCU_W", LIEF::assembly::riscv::OPCODE::PMHRACCU_W) + .value("PMHRACC_H", LIEF::assembly::riscv::OPCODE::PMHRACC_H) + .value("PMHRACC_W", LIEF::assembly::riscv::OPCODE::PMHRACC_W) + .value("PMINU_B", LIEF::assembly::riscv::OPCODE::PMINU_B) + .value("PMINU_DB", LIEF::assembly::riscv::OPCODE::PMINU_DB) + .value("PMINU_DH", LIEF::assembly::riscv::OPCODE::PMINU_DH) + .value("PMINU_DW", LIEF::assembly::riscv::OPCODE::PMINU_DW) + .value("PMINU_H", LIEF::assembly::riscv::OPCODE::PMINU_H) + .value("PMINU_W", LIEF::assembly::riscv::OPCODE::PMINU_W) + .value("PMIN_B", LIEF::assembly::riscv::OPCODE::PMIN_B) + .value("PMIN_DB", LIEF::assembly::riscv::OPCODE::PMIN_DB) + .value("PMIN_DH", LIEF::assembly::riscv::OPCODE::PMIN_DH) + .value("PMIN_DW", LIEF::assembly::riscv::OPCODE::PMIN_DW) + .value("PMIN_H", LIEF::assembly::riscv::OPCODE::PMIN_H) + .value("PMIN_W", LIEF::assembly::riscv::OPCODE::PMIN_W) + .value("PMQ2ADDA_H", LIEF::assembly::riscv::OPCODE::PMQ2ADDA_H) + .value("PMQ2ADDA_W", LIEF::assembly::riscv::OPCODE::PMQ2ADDA_W) + .value("PMQ2ADD_H", LIEF::assembly::riscv::OPCODE::PMQ2ADD_H) + .value("PMQ2ADD_W", LIEF::assembly::riscv::OPCODE::PMQ2ADD_W) + .value("PMQACC_W_H00", LIEF::assembly::riscv::OPCODE::PMQACC_W_H00) + .value("PMQACC_W_H01", LIEF::assembly::riscv::OPCODE::PMQACC_W_H01) + .value("PMQACC_W_H11", LIEF::assembly::riscv::OPCODE::PMQACC_W_H11) + .value("PMQR2ADDA_H", LIEF::assembly::riscv::OPCODE::PMQR2ADDA_H) + .value("PMQR2ADDA_W", LIEF::assembly::riscv::OPCODE::PMQR2ADDA_W) + .value("PMQR2ADD_H", LIEF::assembly::riscv::OPCODE::PMQR2ADD_H) + .value("PMQR2ADD_W", LIEF::assembly::riscv::OPCODE::PMQR2ADD_W) + .value("PMQRACC_W_H00", LIEF::assembly::riscv::OPCODE::PMQRACC_W_H00) + .value("PMQRACC_W_H01", LIEF::assembly::riscv::OPCODE::PMQRACC_W_H01) + .value("PMQRACC_W_H11", LIEF::assembly::riscv::OPCODE::PMQRACC_W_H11) + .value("PMQRWACC", LIEF::assembly::riscv::OPCODE::PMQRWACC) + .value("PMQRWACC_H", LIEF::assembly::riscv::OPCODE::PMQRWACC_H) + .value("PMQWACC", LIEF::assembly::riscv::OPCODE::PMQWACC) + .value("PMQWACC_H", LIEF::assembly::riscv::OPCODE::PMQWACC_H) + .value("PMSEQ_B", LIEF::assembly::riscv::OPCODE::PMSEQ_B) + .value("PMSEQ_DB", LIEF::assembly::riscv::OPCODE::PMSEQ_DB) + .value("PMSEQ_DH", LIEF::assembly::riscv::OPCODE::PMSEQ_DH) + .value("PMSEQ_DW", LIEF::assembly::riscv::OPCODE::PMSEQ_DW) + .value("PMSEQ_H", LIEF::assembly::riscv::OPCODE::PMSEQ_H) + .value("PMSEQ_W", LIEF::assembly::riscv::OPCODE::PMSEQ_W) + .value("PMSLTU_B", LIEF::assembly::riscv::OPCODE::PMSLTU_B) + .value("PMSLTU_DB", LIEF::assembly::riscv::OPCODE::PMSLTU_DB) + .value("PMSLTU_DH", LIEF::assembly::riscv::OPCODE::PMSLTU_DH) + .value("PMSLTU_DW", LIEF::assembly::riscv::OPCODE::PMSLTU_DW) + .value("PMSLTU_H", LIEF::assembly::riscv::OPCODE::PMSLTU_H) + .value("PMSLTU_W", LIEF::assembly::riscv::OPCODE::PMSLTU_W) + .value("PMSLT_B", LIEF::assembly::riscv::OPCODE::PMSLT_B) + .value("PMSLT_DB", LIEF::assembly::riscv::OPCODE::PMSLT_DB) + .value("PMSLT_DH", LIEF::assembly::riscv::OPCODE::PMSLT_DH) + .value("PMSLT_DW", LIEF::assembly::riscv::OPCODE::PMSLT_DW) + .value("PMSLT_H", LIEF::assembly::riscv::OPCODE::PMSLT_H) + .value("PMSLT_W", LIEF::assembly::riscv::OPCODE::PMSLT_W) + .value("PMULHRSU_H", LIEF::assembly::riscv::OPCODE::PMULHRSU_H) + .value("PMULHRSU_W", LIEF::assembly::riscv::OPCODE::PMULHRSU_W) + .value("PMULHRU_H", LIEF::assembly::riscv::OPCODE::PMULHRU_H) + .value("PMULHRU_W", LIEF::assembly::riscv::OPCODE::PMULHRU_W) + .value("PMULHR_H", LIEF::assembly::riscv::OPCODE::PMULHR_H) + .value("PMULHR_W", LIEF::assembly::riscv::OPCODE::PMULHR_W) + .value("PMULHSU_H", LIEF::assembly::riscv::OPCODE::PMULHSU_H) + .value("PMULHSU_H_B0", LIEF::assembly::riscv::OPCODE::PMULHSU_H_B0) + .value("PMULHSU_H_B1", LIEF::assembly::riscv::OPCODE::PMULHSU_H_B1) + .value("PMULHSU_W", LIEF::assembly::riscv::OPCODE::PMULHSU_W) + .value("PMULHSU_W_H0", LIEF::assembly::riscv::OPCODE::PMULHSU_W_H0) + .value("PMULHSU_W_H1", LIEF::assembly::riscv::OPCODE::PMULHSU_W_H1) + .value("PMULHU_H", LIEF::assembly::riscv::OPCODE::PMULHU_H) + .value("PMULHU_W", LIEF::assembly::riscv::OPCODE::PMULHU_W) + .value("PMULH_H", LIEF::assembly::riscv::OPCODE::PMULH_H) + .value("PMULH_H_B0", LIEF::assembly::riscv::OPCODE::PMULH_H_B0) + .value("PMULH_H_B1", LIEF::assembly::riscv::OPCODE::PMULH_H_B1) + .value("PMULH_W", LIEF::assembly::riscv::OPCODE::PMULH_W) + .value("PMULH_W_H0", LIEF::assembly::riscv::OPCODE::PMULH_W_H0) + .value("PMULH_W_H1", LIEF::assembly::riscv::OPCODE::PMULH_W_H1) + .value("PMULQR_H", LIEF::assembly::riscv::OPCODE::PMULQR_H) + .value("PMULQR_W", LIEF::assembly::riscv::OPCODE::PMULQR_W) + .value("PMULQ_H", LIEF::assembly::riscv::OPCODE::PMULQ_H) + .value("PMULQ_W", LIEF::assembly::riscv::OPCODE::PMULQ_W) + .value("PMULSU_H_B00", LIEF::assembly::riscv::OPCODE::PMULSU_H_B00) + .value("PMULSU_H_B11", LIEF::assembly::riscv::OPCODE::PMULSU_H_B11) + .value("PMULSU_W_H00", LIEF::assembly::riscv::OPCODE::PMULSU_W_H00) + .value("PMULSU_W_H11", LIEF::assembly::riscv::OPCODE::PMULSU_W_H11) + .value("PMULU_H_B00", LIEF::assembly::riscv::OPCODE::PMULU_H_B00) + .value("PMULU_H_B01", LIEF::assembly::riscv::OPCODE::PMULU_H_B01) + .value("PMULU_H_B11", LIEF::assembly::riscv::OPCODE::PMULU_H_B11) + .value("PMULU_W_H00", LIEF::assembly::riscv::OPCODE::PMULU_W_H00) + .value("PMULU_W_H01", LIEF::assembly::riscv::OPCODE::PMULU_W_H01) + .value("PMULU_W_H11", LIEF::assembly::riscv::OPCODE::PMULU_W_H11) + .value("PMUL_H_B00", LIEF::assembly::riscv::OPCODE::PMUL_H_B00) + .value("PMUL_H_B01", LIEF::assembly::riscv::OPCODE::PMUL_H_B01) + .value("PMUL_H_B11", LIEF::assembly::riscv::OPCODE::PMUL_H_B11) + .value("PMUL_W_H00", LIEF::assembly::riscv::OPCODE::PMUL_W_H00) + .value("PMUL_W_H01", LIEF::assembly::riscv::OPCODE::PMUL_W_H01) + .value("PMUL_W_H11", LIEF::assembly::riscv::OPCODE::PMUL_W_H11) + .value("PNCLIPIU_B", LIEF::assembly::riscv::OPCODE::PNCLIPIU_B) + .value("PNCLIPIU_H", LIEF::assembly::riscv::OPCODE::PNCLIPIU_H) + .value("PNCLIPI_B", LIEF::assembly::riscv::OPCODE::PNCLIPI_B) + .value("PNCLIPI_H", LIEF::assembly::riscv::OPCODE::PNCLIPI_H) + .value("PNCLIPRIU_B", LIEF::assembly::riscv::OPCODE::PNCLIPRIU_B) + .value("PNCLIPRIU_H", LIEF::assembly::riscv::OPCODE::PNCLIPRIU_H) + .value("PNCLIPRI_B", LIEF::assembly::riscv::OPCODE::PNCLIPRI_B) + .value("PNCLIPRI_H", LIEF::assembly::riscv::OPCODE::PNCLIPRI_H) + .value("PNCLIPRU_BS", LIEF::assembly::riscv::OPCODE::PNCLIPRU_BS) + .value("PNCLIPRU_HS", LIEF::assembly::riscv::OPCODE::PNCLIPRU_HS) + .value("PNCLIPR_BS", LIEF::assembly::riscv::OPCODE::PNCLIPR_BS) + .value("PNCLIPR_HS", LIEF::assembly::riscv::OPCODE::PNCLIPR_HS) + .value("PNCLIPU_BS", LIEF::assembly::riscv::OPCODE::PNCLIPU_BS) + .value("PNCLIPU_HS", LIEF::assembly::riscv::OPCODE::PNCLIPU_HS) + .value("PNCLIP_BS", LIEF::assembly::riscv::OPCODE::PNCLIP_BS) + .value("PNCLIP_HS", LIEF::assembly::riscv::OPCODE::PNCLIP_HS) + .value("PNSARI_B", LIEF::assembly::riscv::OPCODE::PNSARI_B) + .value("PNSARI_H", LIEF::assembly::riscv::OPCODE::PNSARI_H) + .value("PNSRAI_B", LIEF::assembly::riscv::OPCODE::PNSRAI_B) + .value("PNSRAI_H", LIEF::assembly::riscv::OPCODE::PNSRAI_H) + .value("PNSRAR_BS", LIEF::assembly::riscv::OPCODE::PNSRAR_BS) + .value("PNSRAR_HS", LIEF::assembly::riscv::OPCODE::PNSRAR_HS) + .value("PNSRA_BS", LIEF::assembly::riscv::OPCODE::PNSRA_BS) + .value("PNSRA_HS", LIEF::assembly::riscv::OPCODE::PNSRA_HS) + .value("PNSRLI_B", LIEF::assembly::riscv::OPCODE::PNSRLI_B) + .value("PNSRLI_H", LIEF::assembly::riscv::OPCODE::PNSRLI_H) + .value("PNSRL_BS", LIEF::assembly::riscv::OPCODE::PNSRL_BS) + .value("PNSRL_HS", LIEF::assembly::riscv::OPCODE::PNSRL_HS) + .value("PPAIREO_B", LIEF::assembly::riscv::OPCODE::PPAIREO_B) + .value("PPAIREO_DB", LIEF::assembly::riscv::OPCODE::PPAIREO_DB) + .value("PPAIREO_DH", LIEF::assembly::riscv::OPCODE::PPAIREO_DH) + .value("PPAIREO_H", LIEF::assembly::riscv::OPCODE::PPAIREO_H) + .value("PPAIREO_W", LIEF::assembly::riscv::OPCODE::PPAIREO_W) + .value("PPAIRE_B", LIEF::assembly::riscv::OPCODE::PPAIRE_B) + .value("PPAIRE_DB", LIEF::assembly::riscv::OPCODE::PPAIRE_DB) + .value("PPAIRE_DH", LIEF::assembly::riscv::OPCODE::PPAIRE_DH) + .value("PPAIRE_H", LIEF::assembly::riscv::OPCODE::PPAIRE_H) + .value("PPAIROE_B", LIEF::assembly::riscv::OPCODE::PPAIROE_B) + .value("PPAIROE_DB", LIEF::assembly::riscv::OPCODE::PPAIROE_DB) + .value("PPAIROE_DH", LIEF::assembly::riscv::OPCODE::PPAIROE_DH) + .value("PPAIROE_H", LIEF::assembly::riscv::OPCODE::PPAIROE_H) + .value("PPAIROE_W", LIEF::assembly::riscv::OPCODE::PPAIROE_W) + .value("PPAIRO_B", LIEF::assembly::riscv::OPCODE::PPAIRO_B) + .value("PPAIRO_DB", LIEF::assembly::riscv::OPCODE::PPAIRO_DB) + .value("PPAIRO_DH", LIEF::assembly::riscv::OPCODE::PPAIRO_DH) + .value("PPAIRO_H", LIEF::assembly::riscv::OPCODE::PPAIRO_H) + .value("PPAIRO_W", LIEF::assembly::riscv::OPCODE::PPAIRO_W) + .value("PREDSUMU_BS", LIEF::assembly::riscv::OPCODE::PREDSUMU_BS) + .value("PREDSUMU_DBS", LIEF::assembly::riscv::OPCODE::PREDSUMU_DBS) + .value("PREDSUMU_DHS", LIEF::assembly::riscv::OPCODE::PREDSUMU_DHS) + .value("PREDSUMU_HS", LIEF::assembly::riscv::OPCODE::PREDSUMU_HS) + .value("PREDSUMU_WS", LIEF::assembly::riscv::OPCODE::PREDSUMU_WS) + .value("PREDSUM_BS", LIEF::assembly::riscv::OPCODE::PREDSUM_BS) + .value("PREDSUM_DBS", LIEF::assembly::riscv::OPCODE::PREDSUM_DBS) + .value("PREDSUM_DHS", LIEF::assembly::riscv::OPCODE::PREDSUM_DHS) + .value("PREDSUM_HS", LIEF::assembly::riscv::OPCODE::PREDSUM_HS) + .value("PREDSUM_WS", LIEF::assembly::riscv::OPCODE::PREDSUM_WS) + .value("PREFETCH_I", LIEF::assembly::riscv::OPCODE::PREFETCH_I) + .value("PREFETCH_R", LIEF::assembly::riscv::OPCODE::PREFETCH_R) + .value("PREFETCH_W", LIEF::assembly::riscv::OPCODE::PREFETCH_W) + .value("PSABS_B", LIEF::assembly::riscv::OPCODE::PSABS_B) + .value("PSABS_DB", LIEF::assembly::riscv::OPCODE::PSABS_DB) + .value("PSABS_DH", LIEF::assembly::riscv::OPCODE::PSABS_DH) + .value("PSABS_H", LIEF::assembly::riscv::OPCODE::PSABS_H) + .value("PSADDU_B", LIEF::assembly::riscv::OPCODE::PSADDU_B) + .value("PSADDU_DB", LIEF::assembly::riscv::OPCODE::PSADDU_DB) + .value("PSADDU_DH", LIEF::assembly::riscv::OPCODE::PSADDU_DH) + .value("PSADDU_DW", LIEF::assembly::riscv::OPCODE::PSADDU_DW) + .value("PSADDU_H", LIEF::assembly::riscv::OPCODE::PSADDU_H) + .value("PSADDU_W", LIEF::assembly::riscv::OPCODE::PSADDU_W) + .value("PSADD_B", LIEF::assembly::riscv::OPCODE::PSADD_B) + .value("PSADD_DB", LIEF::assembly::riscv::OPCODE::PSADD_DB) + .value("PSADD_DH", LIEF::assembly::riscv::OPCODE::PSADD_DH) + .value("PSADD_DW", LIEF::assembly::riscv::OPCODE::PSADD_DW) + .value("PSADD_H", LIEF::assembly::riscv::OPCODE::PSADD_H) + .value("PSADD_W", LIEF::assembly::riscv::OPCODE::PSADD_W) + .value("PSAS_DHX", LIEF::assembly::riscv::OPCODE::PSAS_DHX) + .value("PSAS_HX", LIEF::assembly::riscv::OPCODE::PSAS_HX) + .value("PSAS_WX", LIEF::assembly::riscv::OPCODE::PSAS_WX) + .value("PSATI_DH", LIEF::assembly::riscv::OPCODE::PSATI_DH) + .value("PSATI_DW", LIEF::assembly::riscv::OPCODE::PSATI_DW) + .value("PSATI_H", LIEF::assembly::riscv::OPCODE::PSATI_H) + .value("PSATI_W", LIEF::assembly::riscv::OPCODE::PSATI_W) + .value("PSA_DHX", LIEF::assembly::riscv::OPCODE::PSA_DHX) + .value("PSA_HX", LIEF::assembly::riscv::OPCODE::PSA_HX) + .value("PSA_WX", LIEF::assembly::riscv::OPCODE::PSA_WX) + .value("PSEXT_DH_B", LIEF::assembly::riscv::OPCODE::PSEXT_DH_B) + .value("PSEXT_DW_B", LIEF::assembly::riscv::OPCODE::PSEXT_DW_B) + .value("PSEXT_DW_H", LIEF::assembly::riscv::OPCODE::PSEXT_DW_H) + .value("PSEXT_H_B", LIEF::assembly::riscv::OPCODE::PSEXT_H_B) + .value("PSEXT_W_B", LIEF::assembly::riscv::OPCODE::PSEXT_W_B) + .value("PSEXT_W_H", LIEF::assembly::riscv::OPCODE::PSEXT_W_H) + .value("PSH1ADD_DH", LIEF::assembly::riscv::OPCODE::PSH1ADD_DH) + .value("PSH1ADD_DW", LIEF::assembly::riscv::OPCODE::PSH1ADD_DW) + .value("PSH1ADD_H", LIEF::assembly::riscv::OPCODE::PSH1ADD_H) + .value("PSH1ADD_W", LIEF::assembly::riscv::OPCODE::PSH1ADD_W) + .value("PSLLI_B", LIEF::assembly::riscv::OPCODE::PSLLI_B) + .value("PSLLI_DB", LIEF::assembly::riscv::OPCODE::PSLLI_DB) + .value("PSLLI_DH", LIEF::assembly::riscv::OPCODE::PSLLI_DH) + .value("PSLLI_DW", LIEF::assembly::riscv::OPCODE::PSLLI_DW) + .value("PSLLI_H", LIEF::assembly::riscv::OPCODE::PSLLI_H) + .value("PSLLI_W", LIEF::assembly::riscv::OPCODE::PSLLI_W) + .value("PSLL_BS", LIEF::assembly::riscv::OPCODE::PSLL_BS) + .value("PSLL_DBS", LIEF::assembly::riscv::OPCODE::PSLL_DBS) + .value("PSLL_DHS", LIEF::assembly::riscv::OPCODE::PSLL_DHS) + .value("PSLL_DWS", LIEF::assembly::riscv::OPCODE::PSLL_DWS) + .value("PSLL_HS", LIEF::assembly::riscv::OPCODE::PSLL_HS) + .value("PSLL_WS", LIEF::assembly::riscv::OPCODE::PSLL_WS) + .value("PSRAI_B", LIEF::assembly::riscv::OPCODE::PSRAI_B) + .value("PSRAI_DB", LIEF::assembly::riscv::OPCODE::PSRAI_DB) + .value("PSRAI_DH", LIEF::assembly::riscv::OPCODE::PSRAI_DH) + .value("PSRAI_DW", LIEF::assembly::riscv::OPCODE::PSRAI_DW) + .value("PSRAI_H", LIEF::assembly::riscv::OPCODE::PSRAI_H) + .value("PSRAI_W", LIEF::assembly::riscv::OPCODE::PSRAI_W) + .value("PSRARI_DH", LIEF::assembly::riscv::OPCODE::PSRARI_DH) + .value("PSRARI_DW", LIEF::assembly::riscv::OPCODE::PSRARI_DW) + .value("PSRARI_H", LIEF::assembly::riscv::OPCODE::PSRARI_H) + .value("PSRARI_W", LIEF::assembly::riscv::OPCODE::PSRARI_W) + .value("PSRA_BS", LIEF::assembly::riscv::OPCODE::PSRA_BS) + .value("PSRA_DBS", LIEF::assembly::riscv::OPCODE::PSRA_DBS) + .value("PSRA_DHS", LIEF::assembly::riscv::OPCODE::PSRA_DHS) + .value("PSRA_DWS", LIEF::assembly::riscv::OPCODE::PSRA_DWS) + .value("PSRA_HS", LIEF::assembly::riscv::OPCODE::PSRA_HS) + .value("PSRA_WS", LIEF::assembly::riscv::OPCODE::PSRA_WS) + .value("PSRLI_B", LIEF::assembly::riscv::OPCODE::PSRLI_B) + .value("PSRLI_DB", LIEF::assembly::riscv::OPCODE::PSRLI_DB) + .value("PSRLI_DH", LIEF::assembly::riscv::OPCODE::PSRLI_DH) + .value("PSRLI_DW", LIEF::assembly::riscv::OPCODE::PSRLI_DW) + .value("PSRLI_H", LIEF::assembly::riscv::OPCODE::PSRLI_H) + .value("PSRLI_W", LIEF::assembly::riscv::OPCODE::PSRLI_W) + .value("PSRL_BS", LIEF::assembly::riscv::OPCODE::PSRL_BS) + .value("PSRL_DBS", LIEF::assembly::riscv::OPCODE::PSRL_DBS) + .value("PSRL_DHS", LIEF::assembly::riscv::OPCODE::PSRL_DHS) + .value("PSRL_DWS", LIEF::assembly::riscv::OPCODE::PSRL_DWS) + .value("PSRL_HS", LIEF::assembly::riscv::OPCODE::PSRL_HS) + .value("PSRL_WS", LIEF::assembly::riscv::OPCODE::PSRL_WS) + .value("PSSA_DHX", LIEF::assembly::riscv::OPCODE::PSSA_DHX) + .value("PSSA_HX", LIEF::assembly::riscv::OPCODE::PSSA_HX) + .value("PSSA_WX", LIEF::assembly::riscv::OPCODE::PSSA_WX) + .value("PSSH1SADD_DH", LIEF::assembly::riscv::OPCODE::PSSH1SADD_DH) + .value("PSSH1SADD_DW", LIEF::assembly::riscv::OPCODE::PSSH1SADD_DW) + .value("PSSH1SADD_H", LIEF::assembly::riscv::OPCODE::PSSH1SADD_H) + .value("PSSH1SADD_W", LIEF::assembly::riscv::OPCODE::PSSH1SADD_W) + .value("PSSHAR_DHS", LIEF::assembly::riscv::OPCODE::PSSHAR_DHS) + .value("PSSHAR_DWS", LIEF::assembly::riscv::OPCODE::PSSHAR_DWS) + .value("PSSHAR_HS", LIEF::assembly::riscv::OPCODE::PSSHAR_HS) + .value("PSSHAR_WS", LIEF::assembly::riscv::OPCODE::PSSHAR_WS) + .value("PSSHA_DHS", LIEF::assembly::riscv::OPCODE::PSSHA_DHS) + .value("PSSHA_DWS", LIEF::assembly::riscv::OPCODE::PSSHA_DWS) + .value("PSSHA_HS", LIEF::assembly::riscv::OPCODE::PSSHA_HS) + .value("PSSHA_WS", LIEF::assembly::riscv::OPCODE::PSSHA_WS) + .value("PSSLAI_DH", LIEF::assembly::riscv::OPCODE::PSSLAI_DH) + .value("PSSLAI_DW", LIEF::assembly::riscv::OPCODE::PSSLAI_DW) + .value("PSSLAI_H", LIEF::assembly::riscv::OPCODE::PSSLAI_H) + .value("PSSLAI_W", LIEF::assembly::riscv::OPCODE::PSSLAI_W) + .value("PSSUBU_B", LIEF::assembly::riscv::OPCODE::PSSUBU_B) + .value("PSSUBU_DB", LIEF::assembly::riscv::OPCODE::PSSUBU_DB) + .value("PSSUBU_DH", LIEF::assembly::riscv::OPCODE::PSSUBU_DH) + .value("PSSUBU_DW", LIEF::assembly::riscv::OPCODE::PSSUBU_DW) + .value("PSSUBU_H", LIEF::assembly::riscv::OPCODE::PSSUBU_H) + .value("PSSUBU_W", LIEF::assembly::riscv::OPCODE::PSSUBU_W) + .value("PSSUB_B", LIEF::assembly::riscv::OPCODE::PSSUB_B) + .value("PSSUB_DB", LIEF::assembly::riscv::OPCODE::PSSUB_DB) + .value("PSSUB_DH", LIEF::assembly::riscv::OPCODE::PSSUB_DH) + .value("PSSUB_DW", LIEF::assembly::riscv::OPCODE::PSSUB_DW) + .value("PSSUB_H", LIEF::assembly::riscv::OPCODE::PSSUB_H) + .value("PSSUB_W", LIEF::assembly::riscv::OPCODE::PSSUB_W) + .value("PSUB_B", LIEF::assembly::riscv::OPCODE::PSUB_B) + .value("PSUB_DB", LIEF::assembly::riscv::OPCODE::PSUB_DB) + .value("PSUB_DH", LIEF::assembly::riscv::OPCODE::PSUB_DH) + .value("PSUB_DW", LIEF::assembly::riscv::OPCODE::PSUB_DW) + .value("PSUB_H", LIEF::assembly::riscv::OPCODE::PSUB_H) + .value("PSUB_W", LIEF::assembly::riscv::OPCODE::PSUB_W) + .value("PUSATI_DH", LIEF::assembly::riscv::OPCODE::PUSATI_DH) + .value("PUSATI_DW", LIEF::assembly::riscv::OPCODE::PUSATI_DW) + .value("PUSATI_H", LIEF::assembly::riscv::OPCODE::PUSATI_H) + .value("PUSATI_W", LIEF::assembly::riscv::OPCODE::PUSATI_W) + .value("PWADDAU_B", LIEF::assembly::riscv::OPCODE::PWADDAU_B) + .value("PWADDAU_H", LIEF::assembly::riscv::OPCODE::PWADDAU_H) + .value("PWADDA_B", LIEF::assembly::riscv::OPCODE::PWADDA_B) + .value("PWADDA_H", LIEF::assembly::riscv::OPCODE::PWADDA_H) + .value("PWADDU_B", LIEF::assembly::riscv::OPCODE::PWADDU_B) + .value("PWADDU_H", LIEF::assembly::riscv::OPCODE::PWADDU_H) + .value("PWADD_B", LIEF::assembly::riscv::OPCODE::PWADD_B) + .value("PWADD_H", LIEF::assembly::riscv::OPCODE::PWADD_H) + .value("PWMACCSU_H", LIEF::assembly::riscv::OPCODE::PWMACCSU_H) + .value("PWMACCU_H", LIEF::assembly::riscv::OPCODE::PWMACCU_H) + .value("PWMACC_H", LIEF::assembly::riscv::OPCODE::PWMACC_H) + .value("PWMULSU_B", LIEF::assembly::riscv::OPCODE::PWMULSU_B) + .value("PWMULSU_H", LIEF::assembly::riscv::OPCODE::PWMULSU_H) + .value("PWMULU_B", LIEF::assembly::riscv::OPCODE::PWMULU_B) + .value("PWMULU_H", LIEF::assembly::riscv::OPCODE::PWMULU_H) + .value("PWMUL_B", LIEF::assembly::riscv::OPCODE::PWMUL_B) + .value("PWMUL_H", LIEF::assembly::riscv::OPCODE::PWMUL_H) + .value("PWSLAI_B", LIEF::assembly::riscv::OPCODE::PWSLAI_B) + .value("PWSLAI_H", LIEF::assembly::riscv::OPCODE::PWSLAI_H) + .value("PWSLA_BS", LIEF::assembly::riscv::OPCODE::PWSLA_BS) + .value("PWSLA_HS", LIEF::assembly::riscv::OPCODE::PWSLA_HS) + .value("PWSLLI_B", LIEF::assembly::riscv::OPCODE::PWSLLI_B); + opcodes.value("PWSLLI_H", LIEF::assembly::riscv::OPCODE::PWSLLI_H) + .value("PWSLL_BS", LIEF::assembly::riscv::OPCODE::PWSLL_BS) + .value("PWSLL_HS", LIEF::assembly::riscv::OPCODE::PWSLL_HS) + .value("PWSUBAU_B", LIEF::assembly::riscv::OPCODE::PWSUBAU_B) + .value("PWSUBAU_H", LIEF::assembly::riscv::OPCODE::PWSUBAU_H) + .value("PWSUBA_B", LIEF::assembly::riscv::OPCODE::PWSUBA_B) + .value("PWSUBA_H", LIEF::assembly::riscv::OPCODE::PWSUBA_H) + .value("PWSUBU_B", LIEF::assembly::riscv::OPCODE::PWSUBU_B) + .value("PWSUBU_H", LIEF::assembly::riscv::OPCODE::PWSUBU_H) + .value("PWSUB_B", LIEF::assembly::riscv::OPCODE::PWSUB_B) + .value("PWSUB_H", LIEF::assembly::riscv::OPCODE::PWSUB_H) + .value("QC_ADDSAT", LIEF::assembly::riscv::OPCODE::QC_ADDSAT) + .value("QC_ADDUSAT", LIEF::assembly::riscv::OPCODE::QC_ADDUSAT) + .value("QC_BEQI", LIEF::assembly::riscv::OPCODE::QC_BEQI) + .value("QC_BGEI", LIEF::assembly::riscv::OPCODE::QC_BGEI) + .value("QC_BGEUI", LIEF::assembly::riscv::OPCODE::QC_BGEUI) + .value("QC_BLTI", LIEF::assembly::riscv::OPCODE::QC_BLTI) + .value("QC_BLTUI", LIEF::assembly::riscv::OPCODE::QC_BLTUI) + .value("QC_BNEI", LIEF::assembly::riscv::OPCODE::QC_BNEI) + .value("QC_BREV32", LIEF::assembly::riscv::OPCODE::QC_BREV32) + .value("QC_CLO", LIEF::assembly::riscv::OPCODE::QC_CLO) + .value("QC_CLRINTI", LIEF::assembly::riscv::OPCODE::QC_CLRINTI) + .value("QC_CM_MVA01S", LIEF::assembly::riscv::OPCODE::QC_CM_MVA01S) + .value("QC_CM_MVSA01", LIEF::assembly::riscv::OPCODE::QC_CM_MVSA01) + .value("QC_CM_POP", LIEF::assembly::riscv::OPCODE::QC_CM_POP) + .value("QC_CM_POPRET", LIEF::assembly::riscv::OPCODE::QC_CM_POPRET) + .value("QC_CM_POPRETZ", LIEF::assembly::riscv::OPCODE::QC_CM_POPRETZ) + .value("QC_CM_PUSH", LIEF::assembly::riscv::OPCODE::QC_CM_PUSH) + .value("QC_CM_PUSHFP", LIEF::assembly::riscv::OPCODE::QC_CM_PUSHFP) + .value("QC_COMPRESS2", LIEF::assembly::riscv::OPCODE::QC_COMPRESS2) + .value("QC_COMPRESS3", LIEF::assembly::riscv::OPCODE::QC_COMPRESS3) + .value("QC_CSRRWR", LIEF::assembly::riscv::OPCODE::QC_CSRRWR) + .value("QC_CSRRWRI", LIEF::assembly::riscv::OPCODE::QC_CSRRWRI) + .value("QC_CTO", LIEF::assembly::riscv::OPCODE::QC_CTO) + .value("QC_C_BEXTI", LIEF::assembly::riscv::OPCODE::QC_C_BEXTI) + .value("QC_C_BSETI", LIEF::assembly::riscv::OPCODE::QC_C_BSETI) + .value("QC_C_CLRINT", LIEF::assembly::riscv::OPCODE::QC_C_CLRINT) + .value("QC_C_DI", LIEF::assembly::riscv::OPCODE::QC_C_DI) + .value("QC_C_DIR", LIEF::assembly::riscv::OPCODE::QC_C_DIR) + .value("QC_C_EI", LIEF::assembly::riscv::OPCODE::QC_C_EI) + .value("QC_C_EIR", LIEF::assembly::riscv::OPCODE::QC_C_EIR) + .value("QC_C_EXTU", LIEF::assembly::riscv::OPCODE::QC_C_EXTU) + .value("QC_C_MIENTER", LIEF::assembly::riscv::OPCODE::QC_C_MIENTER) + .value("QC_C_MIENTER_NEST", LIEF::assembly::riscv::OPCODE::QC_C_MIENTER_NEST) + .value("QC_C_MILEAVERET", LIEF::assembly::riscv::OPCODE::QC_C_MILEAVERET) + .value("QC_C_MNRET", LIEF::assembly::riscv::OPCODE::QC_C_MNRET) + .value("QC_C_MRET", LIEF::assembly::riscv::OPCODE::QC_C_MRET) + .value("QC_C_MULIADD", LIEF::assembly::riscv::OPCODE::QC_C_MULIADD) + .value("QC_C_MVEQZ", LIEF::assembly::riscv::OPCODE::QC_C_MVEQZ) + .value("QC_C_SETINT", LIEF::assembly::riscv::OPCODE::QC_C_SETINT) + .value("QC_C_SYNC", LIEF::assembly::riscv::OPCODE::QC_C_SYNC) + .value("QC_C_SYNCR", LIEF::assembly::riscv::OPCODE::QC_C_SYNCR) + .value("QC_C_SYNCWF", LIEF::assembly::riscv::OPCODE::QC_C_SYNCWF) + .value("QC_C_SYNCWL", LIEF::assembly::riscv::OPCODE::QC_C_SYNCWL) + .value("QC_EXPAND2", LIEF::assembly::riscv::OPCODE::QC_EXPAND2) + .value("QC_EXPAND3", LIEF::assembly::riscv::OPCODE::QC_EXPAND3) + .value("QC_EXT", LIEF::assembly::riscv::OPCODE::QC_EXT) + .value("QC_EXTD", LIEF::assembly::riscv::OPCODE::QC_EXTD) + .value("QC_EXTDPR", LIEF::assembly::riscv::OPCODE::QC_EXTDPR) + .value("QC_EXTDPRH", LIEF::assembly::riscv::OPCODE::QC_EXTDPRH) + .value("QC_EXTDR", LIEF::assembly::riscv::OPCODE::QC_EXTDR) + .value("QC_EXTDU", LIEF::assembly::riscv::OPCODE::QC_EXTDU) + .value("QC_EXTDUPR", LIEF::assembly::riscv::OPCODE::QC_EXTDUPR) + .value("QC_EXTDUPRH", LIEF::assembly::riscv::OPCODE::QC_EXTDUPRH) + .value("QC_EXTDUR", LIEF::assembly::riscv::OPCODE::QC_EXTDUR) + .value("QC_EXTU", LIEF::assembly::riscv::OPCODE::QC_EXTU) + .value("QC_E_ADDAI", LIEF::assembly::riscv::OPCODE::QC_E_ADDAI) + .value("QC_E_ADDI", LIEF::assembly::riscv::OPCODE::QC_E_ADDI) + .value("QC_E_ANDAI", LIEF::assembly::riscv::OPCODE::QC_E_ANDAI) + .value("QC_E_ANDI", LIEF::assembly::riscv::OPCODE::QC_E_ANDI) + .value("QC_E_BEQI", LIEF::assembly::riscv::OPCODE::QC_E_BEQI) + .value("QC_E_BGEI", LIEF::assembly::riscv::OPCODE::QC_E_BGEI) + .value("QC_E_BGEUI", LIEF::assembly::riscv::OPCODE::QC_E_BGEUI) + .value("QC_E_BLTI", LIEF::assembly::riscv::OPCODE::QC_E_BLTI) + .value("QC_E_BLTUI", LIEF::assembly::riscv::OPCODE::QC_E_BLTUI) + .value("QC_E_BNEI", LIEF::assembly::riscv::OPCODE::QC_E_BNEI) + .value("QC_E_J", LIEF::assembly::riscv::OPCODE::QC_E_J) + .value("QC_E_JAL", LIEF::assembly::riscv::OPCODE::QC_E_JAL) + .value("QC_E_LB", LIEF::assembly::riscv::OPCODE::QC_E_LB) + .value("QC_E_LBU", LIEF::assembly::riscv::OPCODE::QC_E_LBU) + .value("QC_E_LH", LIEF::assembly::riscv::OPCODE::QC_E_LH) + .value("QC_E_LHU", LIEF::assembly::riscv::OPCODE::QC_E_LHU) + .value("QC_E_LI", LIEF::assembly::riscv::OPCODE::QC_E_LI) + .value("QC_E_LW", LIEF::assembly::riscv::OPCODE::QC_E_LW) + .value("QC_E_ORAI", LIEF::assembly::riscv::OPCODE::QC_E_ORAI) + .value("QC_E_ORI", LIEF::assembly::riscv::OPCODE::QC_E_ORI) + .value("QC_E_SB", LIEF::assembly::riscv::OPCODE::QC_E_SB) + .value("QC_E_SH", LIEF::assembly::riscv::OPCODE::QC_E_SH) + .value("QC_E_SW", LIEF::assembly::riscv::OPCODE::QC_E_SW) + .value("QC_E_XORAI", LIEF::assembly::riscv::OPCODE::QC_E_XORAI) + .value("QC_E_XORI", LIEF::assembly::riscv::OPCODE::QC_E_XORI) + .value("QC_INSB", LIEF::assembly::riscv::OPCODE::QC_INSB) + .value("QC_INSBH", LIEF::assembly::riscv::OPCODE::QC_INSBH) + .value("QC_INSBHR", LIEF::assembly::riscv::OPCODE::QC_INSBHR) + .value("QC_INSBI", LIEF::assembly::riscv::OPCODE::QC_INSBI) + .value("QC_INSBPR", LIEF::assembly::riscv::OPCODE::QC_INSBPR) + .value("QC_INSBPRH", LIEF::assembly::riscv::OPCODE::QC_INSBPRH) + .value("QC_INSBR", LIEF::assembly::riscv::OPCODE::QC_INSBR) + .value("QC_INSBRI", LIEF::assembly::riscv::OPCODE::QC_INSBRI) + .value("QC_INW", LIEF::assembly::riscv::OPCODE::QC_INW) + .value("QC_LI", LIEF::assembly::riscv::OPCODE::QC_LI) + .value("QC_LIEQ", LIEF::assembly::riscv::OPCODE::QC_LIEQ) + .value("QC_LIEQI", LIEF::assembly::riscv::OPCODE::QC_LIEQI) + .value("QC_LIGE", LIEF::assembly::riscv::OPCODE::QC_LIGE) + .value("QC_LIGEI", LIEF::assembly::riscv::OPCODE::QC_LIGEI) + .value("QC_LIGEU", LIEF::assembly::riscv::OPCODE::QC_LIGEU) + .value("QC_LIGEUI", LIEF::assembly::riscv::OPCODE::QC_LIGEUI) + .value("QC_LILT", LIEF::assembly::riscv::OPCODE::QC_LILT) + .value("QC_LILTI", LIEF::assembly::riscv::OPCODE::QC_LILTI) + .value("QC_LILTU", LIEF::assembly::riscv::OPCODE::QC_LILTU) + .value("QC_LILTUI", LIEF::assembly::riscv::OPCODE::QC_LILTUI) + .value("QC_LINE", LIEF::assembly::riscv::OPCODE::QC_LINE) + .value("QC_LINEI", LIEF::assembly::riscv::OPCODE::QC_LINEI) + .value("QC_LRB", LIEF::assembly::riscv::OPCODE::QC_LRB) + .value("QC_LRBU", LIEF::assembly::riscv::OPCODE::QC_LRBU) + .value("QC_LRH", LIEF::assembly::riscv::OPCODE::QC_LRH) + .value("QC_LRHU", LIEF::assembly::riscv::OPCODE::QC_LRHU) + .value("QC_LRW", LIEF::assembly::riscv::OPCODE::QC_LRW) + .value("QC_LWM", LIEF::assembly::riscv::OPCODE::QC_LWM) + .value("QC_LWMI", LIEF::assembly::riscv::OPCODE::QC_LWMI) + .value("QC_MULIADD", LIEF::assembly::riscv::OPCODE::QC_MULIADD) + .value("QC_MVEQ", LIEF::assembly::riscv::OPCODE::QC_MVEQ) + .value("QC_MVEQI", LIEF::assembly::riscv::OPCODE::QC_MVEQI) + .value("QC_MVGE", LIEF::assembly::riscv::OPCODE::QC_MVGE) + .value("QC_MVGEI", LIEF::assembly::riscv::OPCODE::QC_MVGEI) + .value("QC_MVGEU", LIEF::assembly::riscv::OPCODE::QC_MVGEU) + .value("QC_MVGEUI", LIEF::assembly::riscv::OPCODE::QC_MVGEUI) + .value("QC_MVLT", LIEF::assembly::riscv::OPCODE::QC_MVLT) + .value("QC_MVLTI", LIEF::assembly::riscv::OPCODE::QC_MVLTI) + .value("QC_MVLTU", LIEF::assembly::riscv::OPCODE::QC_MVLTU) + .value("QC_MVLTUI", LIEF::assembly::riscv::OPCODE::QC_MVLTUI) + .value("QC_MVNE", LIEF::assembly::riscv::OPCODE::QC_MVNE) + .value("QC_MVNEI", LIEF::assembly::riscv::OPCODE::QC_MVNEI) + .value("QC_NORM", LIEF::assembly::riscv::OPCODE::QC_NORM) + .value("QC_NORMEU", LIEF::assembly::riscv::OPCODE::QC_NORMEU) + .value("QC_NORMU", LIEF::assembly::riscv::OPCODE::QC_NORMU) + .value("QC_OUTW", LIEF::assembly::riscv::OPCODE::QC_OUTW) + .value("QC_PPUTCI", LIEF::assembly::riscv::OPCODE::QC_PPUTCI) + .value("QC_SELECTEQI", LIEF::assembly::riscv::OPCODE::QC_SELECTEQI) + .value("QC_SELECTIEQ", LIEF::assembly::riscv::OPCODE::QC_SELECTIEQ) + .value("QC_SELECTIEQI", LIEF::assembly::riscv::OPCODE::QC_SELECTIEQI) + .value("QC_SELECTIIEQ", LIEF::assembly::riscv::OPCODE::QC_SELECTIIEQ) + .value("QC_SELECTIINE", LIEF::assembly::riscv::OPCODE::QC_SELECTIINE) + .value("QC_SELECTINE", LIEF::assembly::riscv::OPCODE::QC_SELECTINE) + .value("QC_SELECTINEI", LIEF::assembly::riscv::OPCODE::QC_SELECTINEI) + .value("QC_SELECTNEI", LIEF::assembly::riscv::OPCODE::QC_SELECTNEI) + .value("QC_SETINTI", LIEF::assembly::riscv::OPCODE::QC_SETINTI) + .value("QC_SETWM", LIEF::assembly::riscv::OPCODE::QC_SETWM) + .value("QC_SETWMI", LIEF::assembly::riscv::OPCODE::QC_SETWMI) + .value("QC_SHLADD", LIEF::assembly::riscv::OPCODE::QC_SHLADD) + .value("QC_SHLSAT", LIEF::assembly::riscv::OPCODE::QC_SHLSAT) + .value("QC_SHLUSAT", LIEF::assembly::riscv::OPCODE::QC_SHLUSAT) + .value("QC_SRB", LIEF::assembly::riscv::OPCODE::QC_SRB) + .value("QC_SRH", LIEF::assembly::riscv::OPCODE::QC_SRH) + .value("QC_SRW", LIEF::assembly::riscv::OPCODE::QC_SRW) + .value("QC_SUBSAT", LIEF::assembly::riscv::OPCODE::QC_SUBSAT) + .value("QC_SUBUSAT", LIEF::assembly::riscv::OPCODE::QC_SUBUSAT) + .value("QC_SWM", LIEF::assembly::riscv::OPCODE::QC_SWM) + .value("QC_SWMI", LIEF::assembly::riscv::OPCODE::QC_SWMI) + .value("QC_SYNC", LIEF::assembly::riscv::OPCODE::QC_SYNC) + .value("QC_SYNCR", LIEF::assembly::riscv::OPCODE::QC_SYNCR) + .value("QC_SYNCWF", LIEF::assembly::riscv::OPCODE::QC_SYNCWF) + .value("QC_SYNCWL", LIEF::assembly::riscv::OPCODE::QC_SYNCWL) + .value("QC_WRAP", LIEF::assembly::riscv::OPCODE::QC_WRAP) + .value("QC_WRAPI", LIEF::assembly::riscv::OPCODE::QC_WRAPI) + .value("QK_C_LBU", LIEF::assembly::riscv::OPCODE::QK_C_LBU) + .value("QK_C_LBUSP", LIEF::assembly::riscv::OPCODE::QK_C_LBUSP) + .value("QK_C_LHU", LIEF::assembly::riscv::OPCODE::QK_C_LHU) + .value("QK_C_LHUSP", LIEF::assembly::riscv::OPCODE::QK_C_LHUSP) + .value("QK_C_SB", LIEF::assembly::riscv::OPCODE::QK_C_SB) + .value("QK_C_SBSP", LIEF::assembly::riscv::OPCODE::QK_C_SBSP) + .value("QK_C_SH", LIEF::assembly::riscv::OPCODE::QK_C_SH) + .value("QK_C_SHSP", LIEF::assembly::riscv::OPCODE::QK_C_SHSP) + .value("REM", LIEF::assembly::riscv::OPCODE::REM) + .value("REMU", LIEF::assembly::riscv::OPCODE::REMU) + .value("REMUW", LIEF::assembly::riscv::OPCODE::REMUW) + .value("REMW", LIEF::assembly::riscv::OPCODE::REMW) + .value("REV16", LIEF::assembly::riscv::OPCODE::REV16) + .value("REV8_RV32", LIEF::assembly::riscv::OPCODE::REV8_RV32) + .value("REV8_RV64", LIEF::assembly::riscv::OPCODE::REV8_RV64) + .value("REV_RV32", LIEF::assembly::riscv::OPCODE::REV_RV32) + .value("REV_RV64", LIEF::assembly::riscv::OPCODE::REV_RV64) + .value("RI_VEXTRACT", LIEF::assembly::riscv::OPCODE::RI_VEXTRACT) + .value("RI_VINSERT", LIEF::assembly::riscv::OPCODE::RI_VINSERT) + .value("RI_VUNZIP2A_VV", LIEF::assembly::riscv::OPCODE::RI_VUNZIP2A_VV) + .value("RI_VUNZIP2B_VV", LIEF::assembly::riscv::OPCODE::RI_VUNZIP2B_VV) + .value("RI_VZERO", LIEF::assembly::riscv::OPCODE::RI_VZERO) + .value("RI_VZIP2A_VV", LIEF::assembly::riscv::OPCODE::RI_VZIP2A_VV) + .value("RI_VZIP2B_VV", LIEF::assembly::riscv::OPCODE::RI_VZIP2B_VV) + .value("RI_VZIPEVEN_VV", LIEF::assembly::riscv::OPCODE::RI_VZIPEVEN_VV) + .value("RI_VZIPODD_VV", LIEF::assembly::riscv::OPCODE::RI_VZIPODD_VV) + .value("ROL", LIEF::assembly::riscv::OPCODE::ROL) + .value("ROLW", LIEF::assembly::riscv::OPCODE::ROLW) + .value("ROR", LIEF::assembly::riscv::OPCODE::ROR) + .value("RORI", LIEF::assembly::riscv::OPCODE::RORI) + .value("RORIW", LIEF::assembly::riscv::OPCODE::RORIW) + .value("RORW", LIEF::assembly::riscv::OPCODE::RORW) + .value("SADD", LIEF::assembly::riscv::OPCODE::SADD) + .value("SADDU", LIEF::assembly::riscv::OPCODE::SADDU) + .value("SATI_RV32", LIEF::assembly::riscv::OPCODE::SATI_RV32) + .value("SATI_RV64", LIEF::assembly::riscv::OPCODE::SATI_RV64) + .value("SB", LIEF::assembly::riscv::OPCODE::SB) + .value("SB_AQRL", LIEF::assembly::riscv::OPCODE::SB_AQRL) + .value("SB_RL", LIEF::assembly::riscv::OPCODE::SB_RL) + .value("SCTRCLR", LIEF::assembly::riscv::OPCODE::SCTRCLR) + .value("SC_D", LIEF::assembly::riscv::OPCODE::SC_D) + .value("SC_D_AQ", LIEF::assembly::riscv::OPCODE::SC_D_AQ) + .value("SC_D_AQRL", LIEF::assembly::riscv::OPCODE::SC_D_AQRL) + .value("SC_D_RL", LIEF::assembly::riscv::OPCODE::SC_D_RL) + .value("SC_W", LIEF::assembly::riscv::OPCODE::SC_W) + .value("SC_W_AQ", LIEF::assembly::riscv::OPCODE::SC_W_AQ) + .value("SC_W_AQRL", LIEF::assembly::riscv::OPCODE::SC_W_AQRL) + .value("SC_W_RL", LIEF::assembly::riscv::OPCODE::SC_W_RL) + .value("SD", LIEF::assembly::riscv::OPCODE::SD) + .value("SD_AQRL", LIEF::assembly::riscv::OPCODE::SD_AQRL) + .value("SD_RL", LIEF::assembly::riscv::OPCODE::SD_RL) + .value("SD_RV32", LIEF::assembly::riscv::OPCODE::SD_RV32) + .value("SEXT_B", LIEF::assembly::riscv::OPCODE::SEXT_B) + .value("SEXT_H", LIEF::assembly::riscv::OPCODE::SEXT_H) + .value("SFENCE_INVAL_IR", LIEF::assembly::riscv::OPCODE::SFENCE_INVAL_IR) + .value("SFENCE_VMA", LIEF::assembly::riscv::OPCODE::SFENCE_VMA) + .value("SFENCE_W_INVAL", LIEF::assembly::riscv::OPCODE::SFENCE_W_INVAL) + .value("SF_CDISCARD_D_L1", LIEF::assembly::riscv::OPCODE::SF_CDISCARD_D_L1) + .value("SF_CEASE", LIEF::assembly::riscv::OPCODE::SF_CEASE) + .value("SF_CFLUSH_D_L1", LIEF::assembly::riscv::OPCODE::SF_CFLUSH_D_L1) + .value("SF_MM_E4M3_E4M3", LIEF::assembly::riscv::OPCODE::SF_MM_E4M3_E4M3) + .value("SF_MM_E4M3_E5M2", LIEF::assembly::riscv::OPCODE::SF_MM_E4M3_E5M2) + .value("SF_MM_E5M2_E4M3", LIEF::assembly::riscv::OPCODE::SF_MM_E5M2_E4M3) + .value("SF_MM_E5M2_E5M2", LIEF::assembly::riscv::OPCODE::SF_MM_E5M2_E5M2) + .value("SF_MM_F_F", LIEF::assembly::riscv::OPCODE::SF_MM_F_F) + .value("SF_MM_S_S", LIEF::assembly::riscv::OPCODE::SF_MM_S_S) + .value("SF_MM_S_U", LIEF::assembly::riscv::OPCODE::SF_MM_S_U) + .value("SF_MM_U_S", LIEF::assembly::riscv::OPCODE::SF_MM_U_S) + .value("SF_MM_U_U", LIEF::assembly::riscv::OPCODE::SF_MM_U_U) + .value("SF_VC_FV", LIEF::assembly::riscv::OPCODE::SF_VC_FV) + .value("SF_VC_FVV", LIEF::assembly::riscv::OPCODE::SF_VC_FVV) + .value("SF_VC_FVW", LIEF::assembly::riscv::OPCODE::SF_VC_FVW) + .value("SF_VC_I", LIEF::assembly::riscv::OPCODE::SF_VC_I) + .value("SF_VC_IV", LIEF::assembly::riscv::OPCODE::SF_VC_IV) + .value("SF_VC_IVV", LIEF::assembly::riscv::OPCODE::SF_VC_IVV) + .value("SF_VC_IVW", LIEF::assembly::riscv::OPCODE::SF_VC_IVW) + .value("SF_VC_VV", LIEF::assembly::riscv::OPCODE::SF_VC_VV) + .value("SF_VC_VVV", LIEF::assembly::riscv::OPCODE::SF_VC_VVV) + .value("SF_VC_VVW", LIEF::assembly::riscv::OPCODE::SF_VC_VVW) + .value("SF_VC_V_FV", LIEF::assembly::riscv::OPCODE::SF_VC_V_FV) + .value("SF_VC_V_FVV", LIEF::assembly::riscv::OPCODE::SF_VC_V_FVV) + .value("SF_VC_V_FVW", LIEF::assembly::riscv::OPCODE::SF_VC_V_FVW) + .value("SF_VC_V_I", LIEF::assembly::riscv::OPCODE::SF_VC_V_I) + .value("SF_VC_V_IV", LIEF::assembly::riscv::OPCODE::SF_VC_V_IV) + .value("SF_VC_V_IVV", LIEF::assembly::riscv::OPCODE::SF_VC_V_IVV) + .value("SF_VC_V_IVW", LIEF::assembly::riscv::OPCODE::SF_VC_V_IVW) + .value("SF_VC_V_VV", LIEF::assembly::riscv::OPCODE::SF_VC_V_VV) + .value("SF_VC_V_VVV", LIEF::assembly::riscv::OPCODE::SF_VC_V_VVV) + .value("SF_VC_V_VVW", LIEF::assembly::riscv::OPCODE::SF_VC_V_VVW) + .value("SF_VC_V_X", LIEF::assembly::riscv::OPCODE::SF_VC_V_X) + .value("SF_VC_V_XV", LIEF::assembly::riscv::OPCODE::SF_VC_V_XV) + .value("SF_VC_V_XVV", LIEF::assembly::riscv::OPCODE::SF_VC_V_XVV) + .value("SF_VC_V_XVW", LIEF::assembly::riscv::OPCODE::SF_VC_V_XVW) + .value("SF_VC_X", LIEF::assembly::riscv::OPCODE::SF_VC_X) + .value("SF_VC_XV", LIEF::assembly::riscv::OPCODE::SF_VC_XV) + .value("SF_VC_XVV", LIEF::assembly::riscv::OPCODE::SF_VC_XVV) + .value("SF_VC_XVW", LIEF::assembly::riscv::OPCODE::SF_VC_XVW) + .value("SF_VFEXPA_V", LIEF::assembly::riscv::OPCODE::SF_VFEXPA_V) + .value("SF_VFEXP_V", LIEF::assembly::riscv::OPCODE::SF_VFEXP_V) + .value("SF_VFNRCLIP_XU_F_QF", LIEF::assembly::riscv::OPCODE::SF_VFNRCLIP_XU_F_QF) + .value("SF_VFNRCLIP_X_F_QF", LIEF::assembly::riscv::OPCODE::SF_VFNRCLIP_X_F_QF) + .value("SF_VFWMACC_4x4x4", LIEF::assembly::riscv::OPCODE::SF_VFWMACC_4x4x4) + .value("SF_VLTE16", LIEF::assembly::riscv::OPCODE::SF_VLTE16) + .value("SF_VLTE32", LIEF::assembly::riscv::OPCODE::SF_VLTE32) + .value("SF_VLTE64", LIEF::assembly::riscv::OPCODE::SF_VLTE64) + .value("SF_VLTE8", LIEF::assembly::riscv::OPCODE::SF_VLTE8) + .value("SF_VQMACCSU_2x8x2", LIEF::assembly::riscv::OPCODE::SF_VQMACCSU_2x8x2) + .value("SF_VQMACCSU_4x8x4", LIEF::assembly::riscv::OPCODE::SF_VQMACCSU_4x8x4) + .value("SF_VQMACCUS_2x8x2", LIEF::assembly::riscv::OPCODE::SF_VQMACCUS_2x8x2) + .value("SF_VQMACCUS_4x8x4", LIEF::assembly::riscv::OPCODE::SF_VQMACCUS_4x8x4) + .value("SF_VQMACCU_2x8x2", LIEF::assembly::riscv::OPCODE::SF_VQMACCU_2x8x2) + .value("SF_VQMACCU_4x8x4", LIEF::assembly::riscv::OPCODE::SF_VQMACCU_4x8x4) + .value("SF_VQMACC_2x8x2", LIEF::assembly::riscv::OPCODE::SF_VQMACC_2x8x2) + .value("SF_VQMACC_4x8x4", LIEF::assembly::riscv::OPCODE::SF_VQMACC_4x8x4) + .value("SF_VSETTK", LIEF::assembly::riscv::OPCODE::SF_VSETTK) + .value("SF_VSETTM", LIEF::assembly::riscv::OPCODE::SF_VSETTM) + .value("SF_VSETTN", LIEF::assembly::riscv::OPCODE::SF_VSETTN) + .value("SF_VSTE16", LIEF::assembly::riscv::OPCODE::SF_VSTE16) + .value("SF_VSTE32", LIEF::assembly::riscv::OPCODE::SF_VSTE32) + .value("SF_VSTE64", LIEF::assembly::riscv::OPCODE::SF_VSTE64) + .value("SF_VSTE8", LIEF::assembly::riscv::OPCODE::SF_VSTE8) + .value("SF_VTDISCARD", LIEF::assembly::riscv::OPCODE::SF_VTDISCARD) + .value("SF_VTMV_T_V", LIEF::assembly::riscv::OPCODE::SF_VTMV_T_V) + .value("SF_VTMV_V_T", LIEF::assembly::riscv::OPCODE::SF_VTMV_V_T) + .value("SF_VTZERO_T", LIEF::assembly::riscv::OPCODE::SF_VTZERO_T) + .value("SH", LIEF::assembly::riscv::OPCODE::SH) + .value("SH1ADD", LIEF::assembly::riscv::OPCODE::SH1ADD) + .value("SH1ADD_UW", LIEF::assembly::riscv::OPCODE::SH1ADD_UW) + .value("SH2ADD", LIEF::assembly::riscv::OPCODE::SH2ADD) + .value("SH2ADD_UW", LIEF::assembly::riscv::OPCODE::SH2ADD_UW) + .value("SH3ADD", LIEF::assembly::riscv::OPCODE::SH3ADD) + .value("SH3ADD_UW", LIEF::assembly::riscv::OPCODE::SH3ADD_UW) + .value("SHA", LIEF::assembly::riscv::OPCODE::SHA) + .value("SHA256SIG0", LIEF::assembly::riscv::OPCODE::SHA256SIG0) + .value("SHA256SIG1", LIEF::assembly::riscv::OPCODE::SHA256SIG1); + opcodes.value("SHA256SUM0", LIEF::assembly::riscv::OPCODE::SHA256SUM0) + .value("SHA256SUM1", LIEF::assembly::riscv::OPCODE::SHA256SUM1) + .value("SHA512SIG0", LIEF::assembly::riscv::OPCODE::SHA512SIG0) + .value("SHA512SIG0H", LIEF::assembly::riscv::OPCODE::SHA512SIG0H) + .value("SHA512SIG0L", LIEF::assembly::riscv::OPCODE::SHA512SIG0L) + .value("SHA512SIG1", LIEF::assembly::riscv::OPCODE::SHA512SIG1) + .value("SHA512SIG1H", LIEF::assembly::riscv::OPCODE::SHA512SIG1H) + .value("SHA512SIG1L", LIEF::assembly::riscv::OPCODE::SHA512SIG1L) + .value("SHA512SUM0", LIEF::assembly::riscv::OPCODE::SHA512SUM0) + .value("SHA512SUM0R", LIEF::assembly::riscv::OPCODE::SHA512SUM0R) + .value("SHA512SUM1", LIEF::assembly::riscv::OPCODE::SHA512SUM1) + .value("SHA512SUM1R", LIEF::assembly::riscv::OPCODE::SHA512SUM1R) + .value("SHAR", LIEF::assembly::riscv::OPCODE::SHAR) + .value("SH_AQRL", LIEF::assembly::riscv::OPCODE::SH_AQRL) + .value("SH_INX", LIEF::assembly::riscv::OPCODE::SH_INX) + .value("SH_RL", LIEF::assembly::riscv::OPCODE::SH_RL) + .value("SINVAL_VMA", LIEF::assembly::riscv::OPCODE::SINVAL_VMA) + .value("SLL", LIEF::assembly::riscv::OPCODE::SLL) + .value("SLLI", LIEF::assembly::riscv::OPCODE::SLLI) + .value("SLLIW", LIEF::assembly::riscv::OPCODE::SLLIW) + .value("SLLI_UW", LIEF::assembly::riscv::OPCODE::SLLI_UW) + .value("SLLW", LIEF::assembly::riscv::OPCODE::SLLW) + .value("SLT", LIEF::assembly::riscv::OPCODE::SLT) + .value("SLTI", LIEF::assembly::riscv::OPCODE::SLTI) + .value("SLTIU", LIEF::assembly::riscv::OPCODE::SLTIU) + .value("SLTU", LIEF::assembly::riscv::OPCODE::SLTU) + .value("SLX", LIEF::assembly::riscv::OPCODE::SLX) + .value("SM3P0", LIEF::assembly::riscv::OPCODE::SM3P0) + .value("SM3P1", LIEF::assembly::riscv::OPCODE::SM3P1) + .value("SM4ED", LIEF::assembly::riscv::OPCODE::SM4ED) + .value("SM4KS", LIEF::assembly::riscv::OPCODE::SM4KS) + .value("SMT_VMADOT", LIEF::assembly::riscv::OPCODE::SMT_VMADOT) + .value("SMT_VMADOT1", LIEF::assembly::riscv::OPCODE::SMT_VMADOT1) + .value("SMT_VMADOT1SU", LIEF::assembly::riscv::OPCODE::SMT_VMADOT1SU) + .value("SMT_VMADOT1U", LIEF::assembly::riscv::OPCODE::SMT_VMADOT1U) + .value("SMT_VMADOT1US", LIEF::assembly::riscv::OPCODE::SMT_VMADOT1US) + .value("SMT_VMADOT2", LIEF::assembly::riscv::OPCODE::SMT_VMADOT2) + .value("SMT_VMADOT2SU", LIEF::assembly::riscv::OPCODE::SMT_VMADOT2SU) + .value("SMT_VMADOT2U", LIEF::assembly::riscv::OPCODE::SMT_VMADOT2U) + .value("SMT_VMADOT2US", LIEF::assembly::riscv::OPCODE::SMT_VMADOT2US) + .value("SMT_VMADOT3", LIEF::assembly::riscv::OPCODE::SMT_VMADOT3) + .value("SMT_VMADOT3SU", LIEF::assembly::riscv::OPCODE::SMT_VMADOT3SU) + .value("SMT_VMADOT3U", LIEF::assembly::riscv::OPCODE::SMT_VMADOT3U) + .value("SMT_VMADOT3US", LIEF::assembly::riscv::OPCODE::SMT_VMADOT3US) + .value("SMT_VMADOTSU", LIEF::assembly::riscv::OPCODE::SMT_VMADOTSU) + .value("SMT_VMADOTU", LIEF::assembly::riscv::OPCODE::SMT_VMADOTU) + .value("SMT_VMADOTUS", LIEF::assembly::riscv::OPCODE::SMT_VMADOTUS) + .value("SRA", LIEF::assembly::riscv::OPCODE::SRA) + .value("SRAI", LIEF::assembly::riscv::OPCODE::SRAI) + .value("SRAIW", LIEF::assembly::riscv::OPCODE::SRAIW) + .value("SRARI_RV32", LIEF::assembly::riscv::OPCODE::SRARI_RV32) + .value("SRARI_RV64", LIEF::assembly::riscv::OPCODE::SRARI_RV64) + .value("SRAW", LIEF::assembly::riscv::OPCODE::SRAW) + .value("SRET", LIEF::assembly::riscv::OPCODE::SRET) + .value("SRL", LIEF::assembly::riscv::OPCODE::SRL) + .value("SRLI", LIEF::assembly::riscv::OPCODE::SRLI) + .value("SRLIW", LIEF::assembly::riscv::OPCODE::SRLIW) + .value("SRLW", LIEF::assembly::riscv::OPCODE::SRLW) + .value("SRX", LIEF::assembly::riscv::OPCODE::SRX) + .value("SSAMOSWAP_D", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D) + .value("SSAMOSWAP_D_AQ", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQ) + .value("SSAMOSWAP_D_AQRL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQRL) + .value("SSAMOSWAP_D_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_RL) + .value("SSAMOSWAP_W", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W) + .value("SSAMOSWAP_W_AQ", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQ) + .value("SSAMOSWAP_W_AQRL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQRL) + .value("SSAMOSWAP_W_RL", LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_RL) + .value("SSH1SADD", LIEF::assembly::riscv::OPCODE::SSH1SADD) + .value("SSHA", LIEF::assembly::riscv::OPCODE::SSHA) + .value("SSHAR", LIEF::assembly::riscv::OPCODE::SSHAR) + .value("SSLAI", LIEF::assembly::riscv::OPCODE::SSLAI) + .value("SSPOPCHK", LIEF::assembly::riscv::OPCODE::SSPOPCHK) + .value("SSPUSH", LIEF::assembly::riscv::OPCODE::SSPUSH) + .value("SSRDP", LIEF::assembly::riscv::OPCODE::SSRDP) + .value("SSUB", LIEF::assembly::riscv::OPCODE::SSUB) + .value("SSUBU", LIEF::assembly::riscv::OPCODE::SSUBU) + .value("SUB", LIEF::assembly::riscv::OPCODE::SUB) + .value("SUBD", LIEF::assembly::riscv::OPCODE::SUBD) + .value("SUBW", LIEF::assembly::riscv::OPCODE::SUBW) + .value("SW", LIEF::assembly::riscv::OPCODE::SW) + .value("SW_AQRL", LIEF::assembly::riscv::OPCODE::SW_AQRL) + .value("SW_INX", LIEF::assembly::riscv::OPCODE::SW_INX) + .value("SW_RL", LIEF::assembly::riscv::OPCODE::SW_RL) + .value("TH_ADDSL", LIEF::assembly::riscv::OPCODE::TH_ADDSL) + .value("TH_DCACHE_CALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CALL) + .value("TH_DCACHE_CIALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIALL) + .value("TH_DCACHE_CIPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIPA) + .value("TH_DCACHE_CISW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CISW) + .value("TH_DCACHE_CIVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIVA) + .value("TH_DCACHE_CPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPA) + .value("TH_DCACHE_CPAL1", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPAL1) + .value("TH_DCACHE_CSW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CSW) + .value("TH_DCACHE_CVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVA) + .value("TH_DCACHE_CVAL1", LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVAL1) + .value("TH_DCACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IALL) + .value("TH_DCACHE_IPA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IPA) + .value("TH_DCACHE_ISW", LIEF::assembly::riscv::OPCODE::TH_DCACHE_ISW) + .value("TH_DCACHE_IVA", LIEF::assembly::riscv::OPCODE::TH_DCACHE_IVA) + .value("TH_EXT", LIEF::assembly::riscv::OPCODE::TH_EXT) + .value("TH_EXTU", LIEF::assembly::riscv::OPCODE::TH_EXTU) + .value("TH_FF0", LIEF::assembly::riscv::OPCODE::TH_FF0) + .value("TH_FF1", LIEF::assembly::riscv::OPCODE::TH_FF1) + .value("TH_FLRD", LIEF::assembly::riscv::OPCODE::TH_FLRD) + .value("TH_FLRW", LIEF::assembly::riscv::OPCODE::TH_FLRW) + .value("TH_FLURD", LIEF::assembly::riscv::OPCODE::TH_FLURD) + .value("TH_FLURW", LIEF::assembly::riscv::OPCODE::TH_FLURW) + .value("TH_FSRD", LIEF::assembly::riscv::OPCODE::TH_FSRD) + .value("TH_FSRW", LIEF::assembly::riscv::OPCODE::TH_FSRW) + .value("TH_FSURD", LIEF::assembly::riscv::OPCODE::TH_FSURD) + .value("TH_FSURW", LIEF::assembly::riscv::OPCODE::TH_FSURW) + .value("TH_ICACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALL) + .value("TH_ICACHE_IALLS", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALLS) + .value("TH_ICACHE_IPA", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IPA) + .value("TH_ICACHE_IVA", LIEF::assembly::riscv::OPCODE::TH_ICACHE_IVA) + .value("TH_L2CACHE_CALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CALL) + .value("TH_L2CACHE_CIALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CIALL) + .value("TH_L2CACHE_IALL", LIEF::assembly::riscv::OPCODE::TH_L2CACHE_IALL) + .value("TH_LBIA", LIEF::assembly::riscv::OPCODE::TH_LBIA) + .value("TH_LBIB", LIEF::assembly::riscv::OPCODE::TH_LBIB) + .value("TH_LBUIA", LIEF::assembly::riscv::OPCODE::TH_LBUIA) + .value("TH_LBUIB", LIEF::assembly::riscv::OPCODE::TH_LBUIB) + .value("TH_LDD", LIEF::assembly::riscv::OPCODE::TH_LDD) + .value("TH_LDIA", LIEF::assembly::riscv::OPCODE::TH_LDIA) + .value("TH_LDIB", LIEF::assembly::riscv::OPCODE::TH_LDIB) + .value("TH_LHIA", LIEF::assembly::riscv::OPCODE::TH_LHIA) + .value("TH_LHIB", LIEF::assembly::riscv::OPCODE::TH_LHIB) + .value("TH_LHUIA", LIEF::assembly::riscv::OPCODE::TH_LHUIA) + .value("TH_LHUIB", LIEF::assembly::riscv::OPCODE::TH_LHUIB) + .value("TH_LRB", LIEF::assembly::riscv::OPCODE::TH_LRB) + .value("TH_LRBU", LIEF::assembly::riscv::OPCODE::TH_LRBU) + .value("TH_LRD", LIEF::assembly::riscv::OPCODE::TH_LRD) + .value("TH_LRH", LIEF::assembly::riscv::OPCODE::TH_LRH) + .value("TH_LRHU", LIEF::assembly::riscv::OPCODE::TH_LRHU) + .value("TH_LRW", LIEF::assembly::riscv::OPCODE::TH_LRW) + .value("TH_LRWU", LIEF::assembly::riscv::OPCODE::TH_LRWU) + .value("TH_LURB", LIEF::assembly::riscv::OPCODE::TH_LURB) + .value("TH_LURBU", LIEF::assembly::riscv::OPCODE::TH_LURBU) + .value("TH_LURD", LIEF::assembly::riscv::OPCODE::TH_LURD) + .value("TH_LURH", LIEF::assembly::riscv::OPCODE::TH_LURH) + .value("TH_LURHU", LIEF::assembly::riscv::OPCODE::TH_LURHU) + .value("TH_LURW", LIEF::assembly::riscv::OPCODE::TH_LURW) + .value("TH_LURWU", LIEF::assembly::riscv::OPCODE::TH_LURWU) + .value("TH_LWD", LIEF::assembly::riscv::OPCODE::TH_LWD) + .value("TH_LWIA", LIEF::assembly::riscv::OPCODE::TH_LWIA) + .value("TH_LWIB", LIEF::assembly::riscv::OPCODE::TH_LWIB) + .value("TH_LWUD", LIEF::assembly::riscv::OPCODE::TH_LWUD) + .value("TH_LWUIA", LIEF::assembly::riscv::OPCODE::TH_LWUIA) + .value("TH_LWUIB", LIEF::assembly::riscv::OPCODE::TH_LWUIB) + .value("TH_MULA", LIEF::assembly::riscv::OPCODE::TH_MULA) + .value("TH_MULAH", LIEF::assembly::riscv::OPCODE::TH_MULAH) + .value("TH_MULAW", LIEF::assembly::riscv::OPCODE::TH_MULAW) + .value("TH_MULS", LIEF::assembly::riscv::OPCODE::TH_MULS) + .value("TH_MULSH", LIEF::assembly::riscv::OPCODE::TH_MULSH) + .value("TH_MULSW", LIEF::assembly::riscv::OPCODE::TH_MULSW) + .value("TH_MVEQZ", LIEF::assembly::riscv::OPCODE::TH_MVEQZ) + .value("TH_MVNEZ", LIEF::assembly::riscv::OPCODE::TH_MVNEZ) + .value("TH_REV", LIEF::assembly::riscv::OPCODE::TH_REV) + .value("TH_REVW", LIEF::assembly::riscv::OPCODE::TH_REVW) + .value("TH_SBIA", LIEF::assembly::riscv::OPCODE::TH_SBIA) + .value("TH_SBIB", LIEF::assembly::riscv::OPCODE::TH_SBIB) + .value("TH_SDD", LIEF::assembly::riscv::OPCODE::TH_SDD) + .value("TH_SDIA", LIEF::assembly::riscv::OPCODE::TH_SDIA) + .value("TH_SDIB", LIEF::assembly::riscv::OPCODE::TH_SDIB) + .value("TH_SFENCE_VMAS", LIEF::assembly::riscv::OPCODE::TH_SFENCE_VMAS) + .value("TH_SHIA", LIEF::assembly::riscv::OPCODE::TH_SHIA) + .value("TH_SHIB", LIEF::assembly::riscv::OPCODE::TH_SHIB) + .value("TH_SRB", LIEF::assembly::riscv::OPCODE::TH_SRB) + .value("TH_SRD", LIEF::assembly::riscv::OPCODE::TH_SRD) + .value("TH_SRH", LIEF::assembly::riscv::OPCODE::TH_SRH) + .value("TH_SRRI", LIEF::assembly::riscv::OPCODE::TH_SRRI) + .value("TH_SRRIW", LIEF::assembly::riscv::OPCODE::TH_SRRIW) + .value("TH_SRW", LIEF::assembly::riscv::OPCODE::TH_SRW) + .value("TH_SURB", LIEF::assembly::riscv::OPCODE::TH_SURB) + .value("TH_SURD", LIEF::assembly::riscv::OPCODE::TH_SURD) + .value("TH_SURH", LIEF::assembly::riscv::OPCODE::TH_SURH) + .value("TH_SURW", LIEF::assembly::riscv::OPCODE::TH_SURW) + .value("TH_SWD", LIEF::assembly::riscv::OPCODE::TH_SWD) + .value("TH_SWIA", LIEF::assembly::riscv::OPCODE::TH_SWIA) + .value("TH_SWIB", LIEF::assembly::riscv::OPCODE::TH_SWIB) + .value("TH_SYNC", LIEF::assembly::riscv::OPCODE::TH_SYNC) + .value("TH_SYNC_I", LIEF::assembly::riscv::OPCODE::TH_SYNC_I) + .value("TH_SYNC_IS", LIEF::assembly::riscv::OPCODE::TH_SYNC_IS) + .value("TH_SYNC_S", LIEF::assembly::riscv::OPCODE::TH_SYNC_S) + .value("TH_TST", LIEF::assembly::riscv::OPCODE::TH_TST) + .value("TH_TSTNBZ", LIEF::assembly::riscv::OPCODE::TH_TSTNBZ) + .value("TH_VMAQASU_VV", LIEF::assembly::riscv::OPCODE::TH_VMAQASU_VV) + .value("TH_VMAQASU_VX", LIEF::assembly::riscv::OPCODE::TH_VMAQASU_VX) + .value("TH_VMAQAUS_VX", LIEF::assembly::riscv::OPCODE::TH_VMAQAUS_VX) + .value("TH_VMAQAU_VV", LIEF::assembly::riscv::OPCODE::TH_VMAQAU_VV) + .value("TH_VMAQAU_VX", LIEF::assembly::riscv::OPCODE::TH_VMAQAU_VX) + .value("TH_VMAQA_VV", LIEF::assembly::riscv::OPCODE::TH_VMAQA_VV) + .value("TH_VMAQA_VX", LIEF::assembly::riscv::OPCODE::TH_VMAQA_VX) + .value("UNIMP", LIEF::assembly::riscv::OPCODE::UNIMP) + .value("UNZIP16HP", LIEF::assembly::riscv::OPCODE::UNZIP16HP) + .value("UNZIP16P", LIEF::assembly::riscv::OPCODE::UNZIP16P) + .value("UNZIP8HP", LIEF::assembly::riscv::OPCODE::UNZIP8HP) + .value("UNZIP8P", LIEF::assembly::riscv::OPCODE::UNZIP8P) + .value("UNZIP_RV32", LIEF::assembly::riscv::OPCODE::UNZIP_RV32) + .value("USATI_RV32", LIEF::assembly::riscv::OPCODE::USATI_RV32) + .value("USATI_RV64", LIEF::assembly::riscv::OPCODE::USATI_RV64) + .value("VAADDU_VV", LIEF::assembly::riscv::OPCODE::VAADDU_VV) + .value("VAADDU_VX", LIEF::assembly::riscv::OPCODE::VAADDU_VX) + .value("VAADD_VV", LIEF::assembly::riscv::OPCODE::VAADD_VV) + .value("VAADD_VX", LIEF::assembly::riscv::OPCODE::VAADD_VX) + .value("VADC_VIM", LIEF::assembly::riscv::OPCODE::VADC_VIM) + .value("VADC_VVM", LIEF::assembly::riscv::OPCODE::VADC_VVM) + .value("VADC_VXM", LIEF::assembly::riscv::OPCODE::VADC_VXM) + .value("VADD_VI", LIEF::assembly::riscv::OPCODE::VADD_VI) + .value("VADD_VV", LIEF::assembly::riscv::OPCODE::VADD_VV) + .value("VADD_VX", LIEF::assembly::riscv::OPCODE::VADD_VX) + .value("VAESDF_VS", LIEF::assembly::riscv::OPCODE::VAESDF_VS) + .value("VAESDF_VV", LIEF::assembly::riscv::OPCODE::VAESDF_VV) + .value("VAESDM_VS", LIEF::assembly::riscv::OPCODE::VAESDM_VS) + .value("VAESDM_VV", LIEF::assembly::riscv::OPCODE::VAESDM_VV) + .value("VAESEF_VS", LIEF::assembly::riscv::OPCODE::VAESEF_VS) + .value("VAESEF_VV", LIEF::assembly::riscv::OPCODE::VAESEF_VV) + .value("VAESEM_VS", LIEF::assembly::riscv::OPCODE::VAESEM_VS) + .value("VAESEM_VV", LIEF::assembly::riscv::OPCODE::VAESEM_VV) + .value("VAESKF1_VI", LIEF::assembly::riscv::OPCODE::VAESKF1_VI) + .value("VAESKF2_VI", LIEF::assembly::riscv::OPCODE::VAESKF2_VI) + .value("VAESZ_VS", LIEF::assembly::riscv::OPCODE::VAESZ_VS) + .value("VANDN_VV", LIEF::assembly::riscv::OPCODE::VANDN_VV) + .value("VANDN_VX", LIEF::assembly::riscv::OPCODE::VANDN_VX) + .value("VAND_VI", LIEF::assembly::riscv::OPCODE::VAND_VI) + .value("VAND_VV", LIEF::assembly::riscv::OPCODE::VAND_VV) + .value("VAND_VX", LIEF::assembly::riscv::OPCODE::VAND_VX) + .value("VASUBU_VV", LIEF::assembly::riscv::OPCODE::VASUBU_VV) + .value("VASUBU_VX", LIEF::assembly::riscv::OPCODE::VASUBU_VX) + .value("VASUB_VV", LIEF::assembly::riscv::OPCODE::VASUB_VV) + .value("VASUB_VX", LIEF::assembly::riscv::OPCODE::VASUB_VX) + .value("VBREV8_V", LIEF::assembly::riscv::OPCODE::VBREV8_V) + .value("VBREV_V", LIEF::assembly::riscv::OPCODE::VBREV_V) + .value("VCLMULH_VV", LIEF::assembly::riscv::OPCODE::VCLMULH_VV) + .value("VCLMULH_VX", LIEF::assembly::riscv::OPCODE::VCLMULH_VX) + .value("VCLMUL_VV", LIEF::assembly::riscv::OPCODE::VCLMUL_VV) + .value("VCLMUL_VX", LIEF::assembly::riscv::OPCODE::VCLMUL_VX) + .value("VCLZ_V", LIEF::assembly::riscv::OPCODE::VCLZ_V) + .value("VCOMPRESS_VM", LIEF::assembly::riscv::OPCODE::VCOMPRESS_VM) + .value("VCPOP_M", LIEF::assembly::riscv::OPCODE::VCPOP_M) + .value("VCPOP_V", LIEF::assembly::riscv::OPCODE::VCPOP_V) + .value("VCTZ_V", LIEF::assembly::riscv::OPCODE::VCTZ_V) + .value("VDIVU_VV", LIEF::assembly::riscv::OPCODE::VDIVU_VV) + .value("VDIVU_VX", LIEF::assembly::riscv::OPCODE::VDIVU_VX) + .value("VDIV_VV", LIEF::assembly::riscv::OPCODE::VDIV_VV) + .value("VDIV_VX", LIEF::assembly::riscv::OPCODE::VDIV_VX) + .value("VFADD_VF", LIEF::assembly::riscv::OPCODE::VFADD_VF) + .value("VFADD_VV", LIEF::assembly::riscv::OPCODE::VFADD_VV) + .value("VFCLASS_V", LIEF::assembly::riscv::OPCODE::VFCLASS_V) + .value("VFCVT_F_XU_V", LIEF::assembly::riscv::OPCODE::VFCVT_F_XU_V) + .value("VFCVT_F_X_V", LIEF::assembly::riscv::OPCODE::VFCVT_F_X_V) + .value("VFCVT_RTZ_XU_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_XU_F_V) + .value("VFCVT_RTZ_X_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_X_F_V) + .value("VFCVT_XU_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_XU_F_V) + .value("VFCVT_X_F_V", LIEF::assembly::riscv::OPCODE::VFCVT_X_F_V) + .value("VFDIV_VF", LIEF::assembly::riscv::OPCODE::VFDIV_VF) + .value("VFDIV_VV", LIEF::assembly::riscv::OPCODE::VFDIV_VV) + .value("VFIRST_M", LIEF::assembly::riscv::OPCODE::VFIRST_M) + .value("VFMACC_VF", LIEF::assembly::riscv::OPCODE::VFMACC_VF) + .value("VFMACC_VV", LIEF::assembly::riscv::OPCODE::VFMACC_VV) + .value("VFMADD_VF", LIEF::assembly::riscv::OPCODE::VFMADD_VF) + .value("VFMADD_VV", LIEF::assembly::riscv::OPCODE::VFMADD_VV) + .value("VFMAX_VF", LIEF::assembly::riscv::OPCODE::VFMAX_VF) + .value("VFMAX_VV", LIEF::assembly::riscv::OPCODE::VFMAX_VV) + .value("VFMERGE_VFM", LIEF::assembly::riscv::OPCODE::VFMERGE_VFM) + .value("VFMIN_VF", LIEF::assembly::riscv::OPCODE::VFMIN_VF) + .value("VFMIN_VV", LIEF::assembly::riscv::OPCODE::VFMIN_VV) + .value("VFMSAC_VF", LIEF::assembly::riscv::OPCODE::VFMSAC_VF) + .value("VFMSAC_VV", LIEF::assembly::riscv::OPCODE::VFMSAC_VV) + .value("VFMSUB_VF", LIEF::assembly::riscv::OPCODE::VFMSUB_VF) + .value("VFMSUB_VV", LIEF::assembly::riscv::OPCODE::VFMSUB_VV) + .value("VFMUL_VF", LIEF::assembly::riscv::OPCODE::VFMUL_VF) + .value("VFMUL_VV", LIEF::assembly::riscv::OPCODE::VFMUL_VV) + .value("VFMV_F_S", LIEF::assembly::riscv::OPCODE::VFMV_F_S) + .value("VFMV_S_F", LIEF::assembly::riscv::OPCODE::VFMV_S_F) + .value("VFMV_V_F", LIEF::assembly::riscv::OPCODE::VFMV_V_F) + .value("VFNCVTBF16_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVTBF16_F_F_W) + .value("VFNCVTBF16_SAT_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVTBF16_SAT_F_F_W) + .value("VFNCVT_F_F_Q", LIEF::assembly::riscv::OPCODE::VFNCVT_F_F_Q) + .value("VFNCVT_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_F_W) + .value("VFNCVT_F_XU_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_XU_W) + .value("VFNCVT_F_X_W", LIEF::assembly::riscv::OPCODE::VFNCVT_F_X_W) + .value("VFNCVT_ROD_F_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_ROD_F_F_W) + .value("VFNCVT_RTZ_XU_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_XU_F_W) + .value("VFNCVT_RTZ_X_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_X_F_W) + .value("VFNCVT_SAT_F_F_Q", LIEF::assembly::riscv::OPCODE::VFNCVT_SAT_F_F_Q) + .value("VFNCVT_XU_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_XU_F_W) + .value("VFNCVT_X_F_W", LIEF::assembly::riscv::OPCODE::VFNCVT_X_F_W) + .value("VFNMACC_VF", LIEF::assembly::riscv::OPCODE::VFNMACC_VF) + .value("VFNMACC_VV", LIEF::assembly::riscv::OPCODE::VFNMACC_VV) + .value("VFNMADD_VF", LIEF::assembly::riscv::OPCODE::VFNMADD_VF) + .value("VFNMADD_VV", LIEF::assembly::riscv::OPCODE::VFNMADD_VV) + .value("VFNMSAC_VF", LIEF::assembly::riscv::OPCODE::VFNMSAC_VF) + .value("VFNMSAC_VV", LIEF::assembly::riscv::OPCODE::VFNMSAC_VV) + .value("VFNMSUB_VF", LIEF::assembly::riscv::OPCODE::VFNMSUB_VF) + .value("VFNMSUB_VV", LIEF::assembly::riscv::OPCODE::VFNMSUB_VV) + .value("VFRDIV_VF", LIEF::assembly::riscv::OPCODE::VFRDIV_VF) + .value("VFREC7_V", LIEF::assembly::riscv::OPCODE::VFREC7_V) + .value("VFREDMAX_VS", LIEF::assembly::riscv::OPCODE::VFREDMAX_VS) + .value("VFREDMIN_VS", LIEF::assembly::riscv::OPCODE::VFREDMIN_VS) + .value("VFREDOSUM_VS", LIEF::assembly::riscv::OPCODE::VFREDOSUM_VS); + opcodes.value("VFREDUSUM_VS", LIEF::assembly::riscv::OPCODE::VFREDUSUM_VS) + .value("VFRSQRT7_V", LIEF::assembly::riscv::OPCODE::VFRSQRT7_V) + .value("VFRSUB_VF", LIEF::assembly::riscv::OPCODE::VFRSUB_VF) + .value("VFSGNJN_VF", LIEF::assembly::riscv::OPCODE::VFSGNJN_VF) + .value("VFSGNJN_VV", LIEF::assembly::riscv::OPCODE::VFSGNJN_VV) + .value("VFSGNJX_VF", LIEF::assembly::riscv::OPCODE::VFSGNJX_VF) + .value("VFSGNJX_VV", LIEF::assembly::riscv::OPCODE::VFSGNJX_VV) + .value("VFSGNJ_VF", LIEF::assembly::riscv::OPCODE::VFSGNJ_VF) + .value("VFSGNJ_VV", LIEF::assembly::riscv::OPCODE::VFSGNJ_VV) + .value("VFSLIDE1DOWN_VF", LIEF::assembly::riscv::OPCODE::VFSLIDE1DOWN_VF) + .value("VFSLIDE1UP_VF", LIEF::assembly::riscv::OPCODE::VFSLIDE1UP_VF) + .value("VFSQRT_V", LIEF::assembly::riscv::OPCODE::VFSQRT_V) + .value("VFSUB_VF", LIEF::assembly::riscv::OPCODE::VFSUB_VF) + .value("VFSUB_VV", LIEF::assembly::riscv::OPCODE::VFSUB_VV) + .value("VFWADD_VF", LIEF::assembly::riscv::OPCODE::VFWADD_VF) + .value("VFWADD_VV", LIEF::assembly::riscv::OPCODE::VFWADD_VV) + .value("VFWADD_WF", LIEF::assembly::riscv::OPCODE::VFWADD_WF) + .value("VFWADD_WV", LIEF::assembly::riscv::OPCODE::VFWADD_WV) + .value("VFWCVTBF16_F_F_V", LIEF::assembly::riscv::OPCODE::VFWCVTBF16_F_F_V) + .value("VFWCVT_F_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_F_V) + .value("VFWCVT_F_XU_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_XU_V) + .value("VFWCVT_F_X_V", LIEF::assembly::riscv::OPCODE::VFWCVT_F_X_V) + .value("VFWCVT_RTZ_XU_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_XU_F_V) + .value("VFWCVT_RTZ_X_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_X_F_V) + .value("VFWCVT_XU_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_XU_F_V) + .value("VFWCVT_X_F_V", LIEF::assembly::riscv::OPCODE::VFWCVT_X_F_V) + .value("VFWMACCBF16_VF", LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VF) + .value("VFWMACCBF16_VV", LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VV) + .value("VFWMACC_VF", LIEF::assembly::riscv::OPCODE::VFWMACC_VF) + .value("VFWMACC_VV", LIEF::assembly::riscv::OPCODE::VFWMACC_VV) + .value("VFWMSAC_VF", LIEF::assembly::riscv::OPCODE::VFWMSAC_VF) + .value("VFWMSAC_VV", LIEF::assembly::riscv::OPCODE::VFWMSAC_VV) + .value("VFWMUL_VF", LIEF::assembly::riscv::OPCODE::VFWMUL_VF) + .value("VFWMUL_VV", LIEF::assembly::riscv::OPCODE::VFWMUL_VV) + .value("VFWNMACC_VF", LIEF::assembly::riscv::OPCODE::VFWNMACC_VF) + .value("VFWNMACC_VV", LIEF::assembly::riscv::OPCODE::VFWNMACC_VV) + .value("VFWNMSAC_VF", LIEF::assembly::riscv::OPCODE::VFWNMSAC_VF) + .value("VFWNMSAC_VV", LIEF::assembly::riscv::OPCODE::VFWNMSAC_VV) + .value("VFWREDOSUM_VS", LIEF::assembly::riscv::OPCODE::VFWREDOSUM_VS) + .value("VFWREDUSUM_VS", LIEF::assembly::riscv::OPCODE::VFWREDUSUM_VS) + .value("VFWSUB_VF", LIEF::assembly::riscv::OPCODE::VFWSUB_VF) + .value("VFWSUB_VV", LIEF::assembly::riscv::OPCODE::VFWSUB_VV) + .value("VFWSUB_WF", LIEF::assembly::riscv::OPCODE::VFWSUB_WF) + .value("VFWSUB_WV", LIEF::assembly::riscv::OPCODE::VFWSUB_WV) + .value("VGHSH_VS", LIEF::assembly::riscv::OPCODE::VGHSH_VS) + .value("VGHSH_VV", LIEF::assembly::riscv::OPCODE::VGHSH_VV) + .value("VGMUL_VS", LIEF::assembly::riscv::OPCODE::VGMUL_VS) + .value("VGMUL_VV", LIEF::assembly::riscv::OPCODE::VGMUL_VV) + .value("VID_V", LIEF::assembly::riscv::OPCODE::VID_V) + .value("VIOTA_M", LIEF::assembly::riscv::OPCODE::VIOTA_M) + .value("VL1RE16_V", LIEF::assembly::riscv::OPCODE::VL1RE16_V) + .value("VL1RE32_V", LIEF::assembly::riscv::OPCODE::VL1RE32_V) + .value("VL1RE64_V", LIEF::assembly::riscv::OPCODE::VL1RE64_V) + .value("VL1RE8_V", LIEF::assembly::riscv::OPCODE::VL1RE8_V) + .value("VL2RE16_V", LIEF::assembly::riscv::OPCODE::VL2RE16_V) + .value("VL2RE32_V", LIEF::assembly::riscv::OPCODE::VL2RE32_V) + .value("VL2RE64_V", LIEF::assembly::riscv::OPCODE::VL2RE64_V) + .value("VL2RE8_V", LIEF::assembly::riscv::OPCODE::VL2RE8_V) + .value("VL4RE16_V", LIEF::assembly::riscv::OPCODE::VL4RE16_V) + .value("VL4RE32_V", LIEF::assembly::riscv::OPCODE::VL4RE32_V) + .value("VL4RE64_V", LIEF::assembly::riscv::OPCODE::VL4RE64_V) + .value("VL4RE8_V", LIEF::assembly::riscv::OPCODE::VL4RE8_V) + .value("VL8RE16_V", LIEF::assembly::riscv::OPCODE::VL8RE16_V) + .value("VL8RE32_V", LIEF::assembly::riscv::OPCODE::VL8RE32_V) + .value("VL8RE64_V", LIEF::assembly::riscv::OPCODE::VL8RE64_V) + .value("VL8RE8_V", LIEF::assembly::riscv::OPCODE::VL8RE8_V) + .value("VLE16FF_V", LIEF::assembly::riscv::OPCODE::VLE16FF_V) + .value("VLE16_V", LIEF::assembly::riscv::OPCODE::VLE16_V) + .value("VLE32FF_V", LIEF::assembly::riscv::OPCODE::VLE32FF_V) + .value("VLE32_V", LIEF::assembly::riscv::OPCODE::VLE32_V) + .value("VLE64FF_V", LIEF::assembly::riscv::OPCODE::VLE64FF_V) + .value("VLE64_V", LIEF::assembly::riscv::OPCODE::VLE64_V) + .value("VLE8FF_V", LIEF::assembly::riscv::OPCODE::VLE8FF_V) + .value("VLE8_V", LIEF::assembly::riscv::OPCODE::VLE8_V) + .value("VLM_V", LIEF::assembly::riscv::OPCODE::VLM_V) + .value("VLOXEI16_V", LIEF::assembly::riscv::OPCODE::VLOXEI16_V) + .value("VLOXEI32_V", LIEF::assembly::riscv::OPCODE::VLOXEI32_V) + .value("VLOXEI64_V", LIEF::assembly::riscv::OPCODE::VLOXEI64_V) + .value("VLOXEI8_V", LIEF::assembly::riscv::OPCODE::VLOXEI8_V) + .value("VLOXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI16_V) + .value("VLOXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI32_V) + .value("VLOXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI64_V) + .value("VLOXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG2EI8_V) + .value("VLOXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI16_V) + .value("VLOXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI32_V) + .value("VLOXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI64_V) + .value("VLOXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG3EI8_V) + .value("VLOXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI16_V) + .value("VLOXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI32_V) + .value("VLOXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI64_V) + .value("VLOXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG4EI8_V) + .value("VLOXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI16_V) + .value("VLOXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI32_V) + .value("VLOXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI64_V) + .value("VLOXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG5EI8_V) + .value("VLOXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI16_V) + .value("VLOXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI32_V) + .value("VLOXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI64_V) + .value("VLOXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG6EI8_V) + .value("VLOXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI16_V) + .value("VLOXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI32_V) + .value("VLOXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI64_V) + .value("VLOXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG7EI8_V) + .value("VLOXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI16_V) + .value("VLOXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI32_V) + .value("VLOXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI64_V) + .value("VLOXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VLOXSEG8EI8_V) + .value("VLSE16_V", LIEF::assembly::riscv::OPCODE::VLSE16_V) + .value("VLSE32_V", LIEF::assembly::riscv::OPCODE::VLSE32_V) + .value("VLSE64_V", LIEF::assembly::riscv::OPCODE::VLSE64_V) + .value("VLSE8_V", LIEF::assembly::riscv::OPCODE::VLSE8_V) + .value("VLSEG2E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E16FF_V) + .value("VLSEG2E16_V", LIEF::assembly::riscv::OPCODE::VLSEG2E16_V) + .value("VLSEG2E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E32FF_V) + .value("VLSEG2E32_V", LIEF::assembly::riscv::OPCODE::VLSEG2E32_V) + .value("VLSEG2E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E64FF_V) + .value("VLSEG2E64_V", LIEF::assembly::riscv::OPCODE::VLSEG2E64_V) + .value("VLSEG2E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG2E8FF_V) + .value("VLSEG2E8_V", LIEF::assembly::riscv::OPCODE::VLSEG2E8_V) + .value("VLSEG3E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E16FF_V) + .value("VLSEG3E16_V", LIEF::assembly::riscv::OPCODE::VLSEG3E16_V) + .value("VLSEG3E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E32FF_V) + .value("VLSEG3E32_V", LIEF::assembly::riscv::OPCODE::VLSEG3E32_V) + .value("VLSEG3E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E64FF_V) + .value("VLSEG3E64_V", LIEF::assembly::riscv::OPCODE::VLSEG3E64_V) + .value("VLSEG3E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG3E8FF_V) + .value("VLSEG3E8_V", LIEF::assembly::riscv::OPCODE::VLSEG3E8_V) + .value("VLSEG4E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E16FF_V) + .value("VLSEG4E16_V", LIEF::assembly::riscv::OPCODE::VLSEG4E16_V) + .value("VLSEG4E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E32FF_V) + .value("VLSEG4E32_V", LIEF::assembly::riscv::OPCODE::VLSEG4E32_V) + .value("VLSEG4E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E64FF_V) + .value("VLSEG4E64_V", LIEF::assembly::riscv::OPCODE::VLSEG4E64_V) + .value("VLSEG4E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG4E8FF_V) + .value("VLSEG4E8_V", LIEF::assembly::riscv::OPCODE::VLSEG4E8_V) + .value("VLSEG5E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E16FF_V) + .value("VLSEG5E16_V", LIEF::assembly::riscv::OPCODE::VLSEG5E16_V) + .value("VLSEG5E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E32FF_V) + .value("VLSEG5E32_V", LIEF::assembly::riscv::OPCODE::VLSEG5E32_V) + .value("VLSEG5E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E64FF_V) + .value("VLSEG5E64_V", LIEF::assembly::riscv::OPCODE::VLSEG5E64_V) + .value("VLSEG5E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG5E8FF_V) + .value("VLSEG5E8_V", LIEF::assembly::riscv::OPCODE::VLSEG5E8_V) + .value("VLSEG6E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E16FF_V) + .value("VLSEG6E16_V", LIEF::assembly::riscv::OPCODE::VLSEG6E16_V) + .value("VLSEG6E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E32FF_V) + .value("VLSEG6E32_V", LIEF::assembly::riscv::OPCODE::VLSEG6E32_V) + .value("VLSEG6E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E64FF_V) + .value("VLSEG6E64_V", LIEF::assembly::riscv::OPCODE::VLSEG6E64_V) + .value("VLSEG6E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG6E8FF_V) + .value("VLSEG6E8_V", LIEF::assembly::riscv::OPCODE::VLSEG6E8_V) + .value("VLSEG7E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E16FF_V) + .value("VLSEG7E16_V", LIEF::assembly::riscv::OPCODE::VLSEG7E16_V) + .value("VLSEG7E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E32FF_V) + .value("VLSEG7E32_V", LIEF::assembly::riscv::OPCODE::VLSEG7E32_V) + .value("VLSEG7E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E64FF_V) + .value("VLSEG7E64_V", LIEF::assembly::riscv::OPCODE::VLSEG7E64_V) + .value("VLSEG7E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG7E8FF_V) + .value("VLSEG7E8_V", LIEF::assembly::riscv::OPCODE::VLSEG7E8_V) + .value("VLSEG8E16FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E16FF_V) + .value("VLSEG8E16_V", LIEF::assembly::riscv::OPCODE::VLSEG8E16_V) + .value("VLSEG8E32FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E32FF_V) + .value("VLSEG8E32_V", LIEF::assembly::riscv::OPCODE::VLSEG8E32_V) + .value("VLSEG8E64FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E64FF_V) + .value("VLSEG8E64_V", LIEF::assembly::riscv::OPCODE::VLSEG8E64_V) + .value("VLSEG8E8FF_V", LIEF::assembly::riscv::OPCODE::VLSEG8E8FF_V) + .value("VLSEG8E8_V", LIEF::assembly::riscv::OPCODE::VLSEG8E8_V) + .value("VLSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E16_V) + .value("VLSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E32_V) + .value("VLSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E64_V) + .value("VLSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG2E8_V) + .value("VLSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E16_V) + .value("VLSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E32_V) + .value("VLSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E64_V) + .value("VLSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG3E8_V) + .value("VLSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E16_V) + .value("VLSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E32_V) + .value("VLSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E64_V) + .value("VLSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG4E8_V) + .value("VLSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E16_V) + .value("VLSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E32_V) + .value("VLSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E64_V) + .value("VLSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG5E8_V) + .value("VLSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E16_V) + .value("VLSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E32_V) + .value("VLSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E64_V) + .value("VLSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG6E8_V) + .value("VLSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E16_V) + .value("VLSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E32_V) + .value("VLSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E64_V) + .value("VLSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG7E8_V) + .value("VLSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E16_V) + .value("VLSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E32_V) + .value("VLSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E64_V) + .value("VLSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VLSSEG8E8_V) + .value("VLUXEI16_V", LIEF::assembly::riscv::OPCODE::VLUXEI16_V) + .value("VLUXEI32_V", LIEF::assembly::riscv::OPCODE::VLUXEI32_V) + .value("VLUXEI64_V", LIEF::assembly::riscv::OPCODE::VLUXEI64_V) + .value("VLUXEI8_V", LIEF::assembly::riscv::OPCODE::VLUXEI8_V) + .value("VLUXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI16_V) + .value("VLUXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI32_V) + .value("VLUXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI64_V) + .value("VLUXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG2EI8_V) + .value("VLUXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI16_V) + .value("VLUXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI32_V) + .value("VLUXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI64_V) + .value("VLUXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG3EI8_V) + .value("VLUXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI16_V) + .value("VLUXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI32_V) + .value("VLUXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI64_V) + .value("VLUXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG4EI8_V) + .value("VLUXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI16_V) + .value("VLUXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI32_V) + .value("VLUXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI64_V) + .value("VLUXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG5EI8_V) + .value("VLUXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI16_V) + .value("VLUXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI32_V) + .value("VLUXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI64_V) + .value("VLUXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG6EI8_V) + .value("VLUXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI16_V) + .value("VLUXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI32_V) + .value("VLUXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI64_V) + .value("VLUXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG7EI8_V) + .value("VLUXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI16_V) + .value("VLUXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI32_V) + .value("VLUXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI64_V) + .value("VLUXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VLUXSEG8EI8_V) + .value("VMACC_VV", LIEF::assembly::riscv::OPCODE::VMACC_VV) + .value("VMACC_VX", LIEF::assembly::riscv::OPCODE::VMACC_VX) + .value("VMADC_VI", LIEF::assembly::riscv::OPCODE::VMADC_VI) + .value("VMADC_VIM", LIEF::assembly::riscv::OPCODE::VMADC_VIM) + .value("VMADC_VV", LIEF::assembly::riscv::OPCODE::VMADC_VV) + .value("VMADC_VVM", LIEF::assembly::riscv::OPCODE::VMADC_VVM) + .value("VMADC_VX", LIEF::assembly::riscv::OPCODE::VMADC_VX) + .value("VMADC_VXM", LIEF::assembly::riscv::OPCODE::VMADC_VXM) + .value("VMADD_VV", LIEF::assembly::riscv::OPCODE::VMADD_VV) + .value("VMADD_VX", LIEF::assembly::riscv::OPCODE::VMADD_VX) + .value("VMANDN_MM", LIEF::assembly::riscv::OPCODE::VMANDN_MM) + .value("VMAND_MM", LIEF::assembly::riscv::OPCODE::VMAND_MM) + .value("VMAXU_VV", LIEF::assembly::riscv::OPCODE::VMAXU_VV) + .value("VMAXU_VX", LIEF::assembly::riscv::OPCODE::VMAXU_VX) + .value("VMAX_VV", LIEF::assembly::riscv::OPCODE::VMAX_VV) + .value("VMAX_VX", LIEF::assembly::riscv::OPCODE::VMAX_VX) + .value("VMERGE_VIM", LIEF::assembly::riscv::OPCODE::VMERGE_VIM) + .value("VMERGE_VVM", LIEF::assembly::riscv::OPCODE::VMERGE_VVM) + .value("VMERGE_VXM", LIEF::assembly::riscv::OPCODE::VMERGE_VXM) + .value("VMFEQ_VF", LIEF::assembly::riscv::OPCODE::VMFEQ_VF) + .value("VMFEQ_VV", LIEF::assembly::riscv::OPCODE::VMFEQ_VV) + .value("VMFGE_VF", LIEF::assembly::riscv::OPCODE::VMFGE_VF) + .value("VMFGT_VF", LIEF::assembly::riscv::OPCODE::VMFGT_VF) + .value("VMFLE_VF", LIEF::assembly::riscv::OPCODE::VMFLE_VF) + .value("VMFLE_VV", LIEF::assembly::riscv::OPCODE::VMFLE_VV) + .value("VMFLT_VF", LIEF::assembly::riscv::OPCODE::VMFLT_VF) + .value("VMFLT_VV", LIEF::assembly::riscv::OPCODE::VMFLT_VV) + .value("VMFNE_VF", LIEF::assembly::riscv::OPCODE::VMFNE_VF) + .value("VMFNE_VV", LIEF::assembly::riscv::OPCODE::VMFNE_VV) + .value("VMINU_VV", LIEF::assembly::riscv::OPCODE::VMINU_VV) + .value("VMINU_VX", LIEF::assembly::riscv::OPCODE::VMINU_VX) + .value("VMIN_VV", LIEF::assembly::riscv::OPCODE::VMIN_VV) + .value("VMIN_VX", LIEF::assembly::riscv::OPCODE::VMIN_VX) + .value("VMNAND_MM", LIEF::assembly::riscv::OPCODE::VMNAND_MM) + .value("VMNOR_MM", LIEF::assembly::riscv::OPCODE::VMNOR_MM) + .value("VMORN_MM", LIEF::assembly::riscv::OPCODE::VMORN_MM) + .value("VMOR_MM", LIEF::assembly::riscv::OPCODE::VMOR_MM) + .value("VMSBC_VV", LIEF::assembly::riscv::OPCODE::VMSBC_VV) + .value("VMSBC_VVM", LIEF::assembly::riscv::OPCODE::VMSBC_VVM) + .value("VMSBC_VX", LIEF::assembly::riscv::OPCODE::VMSBC_VX) + .value("VMSBC_VXM", LIEF::assembly::riscv::OPCODE::VMSBC_VXM) + .value("VMSBF_M", LIEF::assembly::riscv::OPCODE::VMSBF_M) + .value("VMSEQ_VI", LIEF::assembly::riscv::OPCODE::VMSEQ_VI) + .value("VMSEQ_VV", LIEF::assembly::riscv::OPCODE::VMSEQ_VV) + .value("VMSEQ_VX", LIEF::assembly::riscv::OPCODE::VMSEQ_VX) + .value("VMSGTU_VI", LIEF::assembly::riscv::OPCODE::VMSGTU_VI) + .value("VMSGTU_VX", LIEF::assembly::riscv::OPCODE::VMSGTU_VX) + .value("VMSGT_VI", LIEF::assembly::riscv::OPCODE::VMSGT_VI) + .value("VMSGT_VX", LIEF::assembly::riscv::OPCODE::VMSGT_VX) + .value("VMSIF_M", LIEF::assembly::riscv::OPCODE::VMSIF_M) + .value("VMSLEU_VI", LIEF::assembly::riscv::OPCODE::VMSLEU_VI) + .value("VMSLEU_VV", LIEF::assembly::riscv::OPCODE::VMSLEU_VV) + .value("VMSLEU_VX", LIEF::assembly::riscv::OPCODE::VMSLEU_VX) + .value("VMSLE_VI", LIEF::assembly::riscv::OPCODE::VMSLE_VI) + .value("VMSLE_VV", LIEF::assembly::riscv::OPCODE::VMSLE_VV) + .value("VMSLE_VX", LIEF::assembly::riscv::OPCODE::VMSLE_VX) + .value("VMSLTU_VV", LIEF::assembly::riscv::OPCODE::VMSLTU_VV) + .value("VMSLTU_VX", LIEF::assembly::riscv::OPCODE::VMSLTU_VX) + .value("VMSLT_VV", LIEF::assembly::riscv::OPCODE::VMSLT_VV) + .value("VMSLT_VX", LIEF::assembly::riscv::OPCODE::VMSLT_VX) + .value("VMSNE_VI", LIEF::assembly::riscv::OPCODE::VMSNE_VI) + .value("VMSNE_VV", LIEF::assembly::riscv::OPCODE::VMSNE_VV) + .value("VMSNE_VX", LIEF::assembly::riscv::OPCODE::VMSNE_VX) + .value("VMSOF_M", LIEF::assembly::riscv::OPCODE::VMSOF_M) + .value("VMULHSU_VV", LIEF::assembly::riscv::OPCODE::VMULHSU_VV) + .value("VMULHSU_VX", LIEF::assembly::riscv::OPCODE::VMULHSU_VX) + .value("VMULHU_VV", LIEF::assembly::riscv::OPCODE::VMULHU_VV) + .value("VMULHU_VX", LIEF::assembly::riscv::OPCODE::VMULHU_VX) + .value("VMULH_VV", LIEF::assembly::riscv::OPCODE::VMULH_VV) + .value("VMULH_VX", LIEF::assembly::riscv::OPCODE::VMULH_VX) + .value("VMUL_VV", LIEF::assembly::riscv::OPCODE::VMUL_VV) + .value("VMUL_VX", LIEF::assembly::riscv::OPCODE::VMUL_VX) + .value("VMV1R_V", LIEF::assembly::riscv::OPCODE::VMV1R_V); + opcodes.value("VMV2R_V", LIEF::assembly::riscv::OPCODE::VMV2R_V) + .value("VMV4R_V", LIEF::assembly::riscv::OPCODE::VMV4R_V) + .value("VMV8R_V", LIEF::assembly::riscv::OPCODE::VMV8R_V) + .value("VMV_S_X", LIEF::assembly::riscv::OPCODE::VMV_S_X) + .value("VMV_V_I", LIEF::assembly::riscv::OPCODE::VMV_V_I) + .value("VMV_V_V", LIEF::assembly::riscv::OPCODE::VMV_V_V) + .value("VMV_V_X", LIEF::assembly::riscv::OPCODE::VMV_V_X) + .value("VMV_X_S", LIEF::assembly::riscv::OPCODE::VMV_X_S) + .value("VMXNOR_MM", LIEF::assembly::riscv::OPCODE::VMXNOR_MM) + .value("VMXOR_MM", LIEF::assembly::riscv::OPCODE::VMXOR_MM) + .value("VNCLIPU_WI", LIEF::assembly::riscv::OPCODE::VNCLIPU_WI) + .value("VNCLIPU_WV", LIEF::assembly::riscv::OPCODE::VNCLIPU_WV) + .value("VNCLIPU_WX", LIEF::assembly::riscv::OPCODE::VNCLIPU_WX) + .value("VNCLIP_WI", LIEF::assembly::riscv::OPCODE::VNCLIP_WI) + .value("VNCLIP_WV", LIEF::assembly::riscv::OPCODE::VNCLIP_WV) + .value("VNCLIP_WX", LIEF::assembly::riscv::OPCODE::VNCLIP_WX) + .value("VNMSAC_VV", LIEF::assembly::riscv::OPCODE::VNMSAC_VV) + .value("VNMSAC_VX", LIEF::assembly::riscv::OPCODE::VNMSAC_VX) + .value("VNMSUB_VV", LIEF::assembly::riscv::OPCODE::VNMSUB_VV) + .value("VNMSUB_VX", LIEF::assembly::riscv::OPCODE::VNMSUB_VX) + .value("VNSRA_WI", LIEF::assembly::riscv::OPCODE::VNSRA_WI) + .value("VNSRA_WV", LIEF::assembly::riscv::OPCODE::VNSRA_WV) + .value("VNSRA_WX", LIEF::assembly::riscv::OPCODE::VNSRA_WX) + .value("VNSRL_WI", LIEF::assembly::riscv::OPCODE::VNSRL_WI) + .value("VNSRL_WV", LIEF::assembly::riscv::OPCODE::VNSRL_WV) + .value("VNSRL_WX", LIEF::assembly::riscv::OPCODE::VNSRL_WX) + .value("VOR_VI", LIEF::assembly::riscv::OPCODE::VOR_VI) + .value("VOR_VV", LIEF::assembly::riscv::OPCODE::VOR_VV) + .value("VOR_VX", LIEF::assembly::riscv::OPCODE::VOR_VX) + .value("VQDOTSU_VV", LIEF::assembly::riscv::OPCODE::VQDOTSU_VV) + .value("VQDOTSU_VX", LIEF::assembly::riscv::OPCODE::VQDOTSU_VX) + .value("VQDOTUS_VX", LIEF::assembly::riscv::OPCODE::VQDOTUS_VX) + .value("VQDOTU_VV", LIEF::assembly::riscv::OPCODE::VQDOTU_VV) + .value("VQDOTU_VX", LIEF::assembly::riscv::OPCODE::VQDOTU_VX) + .value("VQDOT_VV", LIEF::assembly::riscv::OPCODE::VQDOT_VV) + .value("VQDOT_VX", LIEF::assembly::riscv::OPCODE::VQDOT_VX) + .value("VREDAND_VS", LIEF::assembly::riscv::OPCODE::VREDAND_VS) + .value("VREDMAXU_VS", LIEF::assembly::riscv::OPCODE::VREDMAXU_VS) + .value("VREDMAX_VS", LIEF::assembly::riscv::OPCODE::VREDMAX_VS) + .value("VREDMINU_VS", LIEF::assembly::riscv::OPCODE::VREDMINU_VS) + .value("VREDMIN_VS", LIEF::assembly::riscv::OPCODE::VREDMIN_VS) + .value("VREDOR_VS", LIEF::assembly::riscv::OPCODE::VREDOR_VS) + .value("VREDSUM_VS", LIEF::assembly::riscv::OPCODE::VREDSUM_VS) + .value("VREDXOR_VS", LIEF::assembly::riscv::OPCODE::VREDXOR_VS) + .value("VREMU_VV", LIEF::assembly::riscv::OPCODE::VREMU_VV) + .value("VREMU_VX", LIEF::assembly::riscv::OPCODE::VREMU_VX) + .value("VREM_VV", LIEF::assembly::riscv::OPCODE::VREM_VV) + .value("VREM_VX", LIEF::assembly::riscv::OPCODE::VREM_VX) + .value("VREV8_V", LIEF::assembly::riscv::OPCODE::VREV8_V) + .value("VRGATHEREI16_VV", LIEF::assembly::riscv::OPCODE::VRGATHEREI16_VV) + .value("VRGATHER_VI", LIEF::assembly::riscv::OPCODE::VRGATHER_VI) + .value("VRGATHER_VV", LIEF::assembly::riscv::OPCODE::VRGATHER_VV) + .value("VRGATHER_VX", LIEF::assembly::riscv::OPCODE::VRGATHER_VX) + .value("VROL_VV", LIEF::assembly::riscv::OPCODE::VROL_VV) + .value("VROL_VX", LIEF::assembly::riscv::OPCODE::VROL_VX) + .value("VROR_VI", LIEF::assembly::riscv::OPCODE::VROR_VI) + .value("VROR_VV", LIEF::assembly::riscv::OPCODE::VROR_VV) + .value("VROR_VX", LIEF::assembly::riscv::OPCODE::VROR_VX) + .value("VRSUB_VI", LIEF::assembly::riscv::OPCODE::VRSUB_VI) + .value("VRSUB_VX", LIEF::assembly::riscv::OPCODE::VRSUB_VX) + .value("VS1R_V", LIEF::assembly::riscv::OPCODE::VS1R_V) + .value("VS2R_V", LIEF::assembly::riscv::OPCODE::VS2R_V) + .value("VS4R_V", LIEF::assembly::riscv::OPCODE::VS4R_V) + .value("VS8R_V", LIEF::assembly::riscv::OPCODE::VS8R_V) + .value("VSADDU_VI", LIEF::assembly::riscv::OPCODE::VSADDU_VI) + .value("VSADDU_VV", LIEF::assembly::riscv::OPCODE::VSADDU_VV) + .value("VSADDU_VX", LIEF::assembly::riscv::OPCODE::VSADDU_VX) + .value("VSADD_VI", LIEF::assembly::riscv::OPCODE::VSADD_VI) + .value("VSADD_VV", LIEF::assembly::riscv::OPCODE::VSADD_VV) + .value("VSADD_VX", LIEF::assembly::riscv::OPCODE::VSADD_VX) + .value("VSBC_VVM", LIEF::assembly::riscv::OPCODE::VSBC_VVM) + .value("VSBC_VXM", LIEF::assembly::riscv::OPCODE::VSBC_VXM) + .value("VSE16_V", LIEF::assembly::riscv::OPCODE::VSE16_V) + .value("VSE32_V", LIEF::assembly::riscv::OPCODE::VSE32_V) + .value("VSE64_V", LIEF::assembly::riscv::OPCODE::VSE64_V) + .value("VSE8_V", LIEF::assembly::riscv::OPCODE::VSE8_V) + .value("VSETIVLI", LIEF::assembly::riscv::OPCODE::VSETIVLI) + .value("VSETVL", LIEF::assembly::riscv::OPCODE::VSETVL) + .value("VSETVLI", LIEF::assembly::riscv::OPCODE::VSETVLI) + .value("VSEXT_VF2", LIEF::assembly::riscv::OPCODE::VSEXT_VF2) + .value("VSEXT_VF4", LIEF::assembly::riscv::OPCODE::VSEXT_VF4) + .value("VSEXT_VF8", LIEF::assembly::riscv::OPCODE::VSEXT_VF8) + .value("VSHA2CH_VV", LIEF::assembly::riscv::OPCODE::VSHA2CH_VV) + .value("VSHA2CL_VV", LIEF::assembly::riscv::OPCODE::VSHA2CL_VV) + .value("VSHA2MS_VV", LIEF::assembly::riscv::OPCODE::VSHA2MS_VV) + .value("VSLIDE1DOWN_VX", LIEF::assembly::riscv::OPCODE::VSLIDE1DOWN_VX) + .value("VSLIDE1UP_VX", LIEF::assembly::riscv::OPCODE::VSLIDE1UP_VX) + .value("VSLIDEDOWN_VI", LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VI) + .value("VSLIDEDOWN_VX", LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VX) + .value("VSLIDEUP_VI", LIEF::assembly::riscv::OPCODE::VSLIDEUP_VI) + .value("VSLIDEUP_VX", LIEF::assembly::riscv::OPCODE::VSLIDEUP_VX) + .value("VSLL_VI", LIEF::assembly::riscv::OPCODE::VSLL_VI) + .value("VSLL_VV", LIEF::assembly::riscv::OPCODE::VSLL_VV) + .value("VSLL_VX", LIEF::assembly::riscv::OPCODE::VSLL_VX) + .value("VSM3C_VI", LIEF::assembly::riscv::OPCODE::VSM3C_VI) + .value("VSM3ME_VV", LIEF::assembly::riscv::OPCODE::VSM3ME_VV) + .value("VSM4K_VI", LIEF::assembly::riscv::OPCODE::VSM4K_VI) + .value("VSM4R_VS", LIEF::assembly::riscv::OPCODE::VSM4R_VS) + .value("VSM4R_VV", LIEF::assembly::riscv::OPCODE::VSM4R_VV) + .value("VSMUL_VV", LIEF::assembly::riscv::OPCODE::VSMUL_VV) + .value("VSMUL_VX", LIEF::assembly::riscv::OPCODE::VSMUL_VX) + .value("VSM_V", LIEF::assembly::riscv::OPCODE::VSM_V) + .value("VSOXEI16_V", LIEF::assembly::riscv::OPCODE::VSOXEI16_V) + .value("VSOXEI32_V", LIEF::assembly::riscv::OPCODE::VSOXEI32_V) + .value("VSOXEI64_V", LIEF::assembly::riscv::OPCODE::VSOXEI64_V) + .value("VSOXEI8_V", LIEF::assembly::riscv::OPCODE::VSOXEI8_V) + .value("VSOXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI16_V) + .value("VSOXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI32_V) + .value("VSOXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI64_V) + .value("VSOXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG2EI8_V) + .value("VSOXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI16_V) + .value("VSOXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI32_V) + .value("VSOXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI64_V) + .value("VSOXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG3EI8_V) + .value("VSOXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI16_V) + .value("VSOXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI32_V) + .value("VSOXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI64_V) + .value("VSOXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG4EI8_V) + .value("VSOXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI16_V) + .value("VSOXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI32_V) + .value("VSOXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI64_V) + .value("VSOXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG5EI8_V) + .value("VSOXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI16_V) + .value("VSOXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI32_V) + .value("VSOXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI64_V) + .value("VSOXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG6EI8_V) + .value("VSOXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI16_V) + .value("VSOXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI32_V) + .value("VSOXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI64_V) + .value("VSOXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG7EI8_V) + .value("VSOXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI16_V) + .value("VSOXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI32_V) + .value("VSOXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI64_V) + .value("VSOXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VSOXSEG8EI8_V) + .value("VSRA_VI", LIEF::assembly::riscv::OPCODE::VSRA_VI) + .value("VSRA_VV", LIEF::assembly::riscv::OPCODE::VSRA_VV) + .value("VSRA_VX", LIEF::assembly::riscv::OPCODE::VSRA_VX) + .value("VSRL_VI", LIEF::assembly::riscv::OPCODE::VSRL_VI) + .value("VSRL_VV", LIEF::assembly::riscv::OPCODE::VSRL_VV) + .value("VSRL_VX", LIEF::assembly::riscv::OPCODE::VSRL_VX) + .value("VSSE16_V", LIEF::assembly::riscv::OPCODE::VSSE16_V) + .value("VSSE32_V", LIEF::assembly::riscv::OPCODE::VSSE32_V) + .value("VSSE64_V", LIEF::assembly::riscv::OPCODE::VSSE64_V) + .value("VSSE8_V", LIEF::assembly::riscv::OPCODE::VSSE8_V) + .value("VSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VSSEG2E16_V) + .value("VSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VSSEG2E32_V) + .value("VSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VSSEG2E64_V) + .value("VSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VSSEG2E8_V) + .value("VSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VSSEG3E16_V) + .value("VSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VSSEG3E32_V) + .value("VSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VSSEG3E64_V) + .value("VSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VSSEG3E8_V) + .value("VSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VSSEG4E16_V) + .value("VSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VSSEG4E32_V) + .value("VSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VSSEG4E64_V) + .value("VSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VSSEG4E8_V) + .value("VSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VSSEG5E16_V) + .value("VSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VSSEG5E32_V) + .value("VSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VSSEG5E64_V) + .value("VSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VSSEG5E8_V) + .value("VSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VSSEG6E16_V) + .value("VSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VSSEG6E32_V) + .value("VSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VSSEG6E64_V) + .value("VSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VSSEG6E8_V) + .value("VSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VSSEG7E16_V) + .value("VSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VSSEG7E32_V) + .value("VSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VSSEG7E64_V) + .value("VSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VSSEG7E8_V) + .value("VSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VSSEG8E16_V) + .value("VSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VSSEG8E32_V) + .value("VSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VSSEG8E64_V) + .value("VSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VSSEG8E8_V) + .value("VSSRA_VI", LIEF::assembly::riscv::OPCODE::VSSRA_VI) + .value("VSSRA_VV", LIEF::assembly::riscv::OPCODE::VSSRA_VV) + .value("VSSRA_VX", LIEF::assembly::riscv::OPCODE::VSSRA_VX) + .value("VSSRL_VI", LIEF::assembly::riscv::OPCODE::VSSRL_VI) + .value("VSSRL_VV", LIEF::assembly::riscv::OPCODE::VSSRL_VV) + .value("VSSRL_VX", LIEF::assembly::riscv::OPCODE::VSSRL_VX) + .value("VSSSEG2E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E16_V) + .value("VSSSEG2E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E32_V) + .value("VSSSEG2E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E64_V) + .value("VSSSEG2E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG2E8_V) + .value("VSSSEG3E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E16_V) + .value("VSSSEG3E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E32_V) + .value("VSSSEG3E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E64_V) + .value("VSSSEG3E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG3E8_V) + .value("VSSSEG4E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E16_V) + .value("VSSSEG4E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E32_V) + .value("VSSSEG4E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E64_V) + .value("VSSSEG4E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG4E8_V) + .value("VSSSEG5E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E16_V) + .value("VSSSEG5E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E32_V) + .value("VSSSEG5E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E64_V) + .value("VSSSEG5E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG5E8_V) + .value("VSSSEG6E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E16_V) + .value("VSSSEG6E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E32_V) + .value("VSSSEG6E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E64_V) + .value("VSSSEG6E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG6E8_V) + .value("VSSSEG7E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E16_V) + .value("VSSSEG7E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E32_V) + .value("VSSSEG7E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E64_V) + .value("VSSSEG7E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG7E8_V) + .value("VSSSEG8E16_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E16_V) + .value("VSSSEG8E32_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E32_V) + .value("VSSSEG8E64_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E64_V) + .value("VSSSEG8E8_V", LIEF::assembly::riscv::OPCODE::VSSSEG8E8_V) + .value("VSSUBU_VV", LIEF::assembly::riscv::OPCODE::VSSUBU_VV) + .value("VSSUBU_VX", LIEF::assembly::riscv::OPCODE::VSSUBU_VX) + .value("VSSUB_VV", LIEF::assembly::riscv::OPCODE::VSSUB_VV) + .value("VSSUB_VX", LIEF::assembly::riscv::OPCODE::VSSUB_VX) + .value("VSUB_VV", LIEF::assembly::riscv::OPCODE::VSUB_VV) + .value("VSUB_VX", LIEF::assembly::riscv::OPCODE::VSUB_VX) + .value("VSUXEI16_V", LIEF::assembly::riscv::OPCODE::VSUXEI16_V) + .value("VSUXEI32_V", LIEF::assembly::riscv::OPCODE::VSUXEI32_V) + .value("VSUXEI64_V", LIEF::assembly::riscv::OPCODE::VSUXEI64_V) + .value("VSUXEI8_V", LIEF::assembly::riscv::OPCODE::VSUXEI8_V) + .value("VSUXSEG2EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI16_V) + .value("VSUXSEG2EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI32_V) + .value("VSUXSEG2EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI64_V) + .value("VSUXSEG2EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG2EI8_V) + .value("VSUXSEG3EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI16_V) + .value("VSUXSEG3EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI32_V) + .value("VSUXSEG3EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI64_V) + .value("VSUXSEG3EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG3EI8_V) + .value("VSUXSEG4EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI16_V) + .value("VSUXSEG4EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI32_V) + .value("VSUXSEG4EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI64_V) + .value("VSUXSEG4EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG4EI8_V) + .value("VSUXSEG5EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI16_V) + .value("VSUXSEG5EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI32_V) + .value("VSUXSEG5EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI64_V) + .value("VSUXSEG5EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG5EI8_V) + .value("VSUXSEG6EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI16_V) + .value("VSUXSEG6EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI32_V) + .value("VSUXSEG6EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI64_V) + .value("VSUXSEG6EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG6EI8_V) + .value("VSUXSEG7EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI16_V) + .value("VSUXSEG7EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI32_V) + .value("VSUXSEG7EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI64_V) + .value("VSUXSEG7EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG7EI8_V) + .value("VSUXSEG8EI16_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI16_V) + .value("VSUXSEG8EI32_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI32_V) + .value("VSUXSEG8EI64_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI64_V) + .value("VSUXSEG8EI8_V", LIEF::assembly::riscv::OPCODE::VSUXSEG8EI8_V) + .value("VT_MASKC", LIEF::assembly::riscv::OPCODE::VT_MASKC) + .value("VT_MASKCN", LIEF::assembly::riscv::OPCODE::VT_MASKCN) + .value("VWADDU_VV", LIEF::assembly::riscv::OPCODE::VWADDU_VV) + .value("VWADDU_VX", LIEF::assembly::riscv::OPCODE::VWADDU_VX) + .value("VWADDU_WV", LIEF::assembly::riscv::OPCODE::VWADDU_WV) + .value("VWADDU_WX", LIEF::assembly::riscv::OPCODE::VWADDU_WX) + .value("VWADD_VV", LIEF::assembly::riscv::OPCODE::VWADD_VV) + .value("VWADD_VX", LIEF::assembly::riscv::OPCODE::VWADD_VX) + .value("VWADD_WV", LIEF::assembly::riscv::OPCODE::VWADD_WV) + .value("VWADD_WX", LIEF::assembly::riscv::OPCODE::VWADD_WX) + .value("VWMACCSU_VV", LIEF::assembly::riscv::OPCODE::VWMACCSU_VV) + .value("VWMACCSU_VX", LIEF::assembly::riscv::OPCODE::VWMACCSU_VX) + .value("VWMACCUS_VX", LIEF::assembly::riscv::OPCODE::VWMACCUS_VX) + .value("VWMACCU_VV", LIEF::assembly::riscv::OPCODE::VWMACCU_VV) + .value("VWMACCU_VX", LIEF::assembly::riscv::OPCODE::VWMACCU_VX) + .value("VWMACC_VV", LIEF::assembly::riscv::OPCODE::VWMACC_VV) + .value("VWMACC_VX", LIEF::assembly::riscv::OPCODE::VWMACC_VX) + .value("VWMULSU_VV", LIEF::assembly::riscv::OPCODE::VWMULSU_VV) + .value("VWMULSU_VX", LIEF::assembly::riscv::OPCODE::VWMULSU_VX) + .value("VWMULU_VV", LIEF::assembly::riscv::OPCODE::VWMULU_VV) + .value("VWMULU_VX", LIEF::assembly::riscv::OPCODE::VWMULU_VX) + .value("VWMUL_VV", LIEF::assembly::riscv::OPCODE::VWMUL_VV) + .value("VWMUL_VX", LIEF::assembly::riscv::OPCODE::VWMUL_VX) + .value("VWREDSUMU_VS", LIEF::assembly::riscv::OPCODE::VWREDSUMU_VS) + .value("VWREDSUM_VS", LIEF::assembly::riscv::OPCODE::VWREDSUM_VS) + .value("VWSLL_VI", LIEF::assembly::riscv::OPCODE::VWSLL_VI) + .value("VWSLL_VV", LIEF::assembly::riscv::OPCODE::VWSLL_VV) + .value("VWSLL_VX", LIEF::assembly::riscv::OPCODE::VWSLL_VX) + .value("VWSUBU_VV", LIEF::assembly::riscv::OPCODE::VWSUBU_VV) + .value("VWSUBU_VX", LIEF::assembly::riscv::OPCODE::VWSUBU_VX) + .value("VWSUBU_WV", LIEF::assembly::riscv::OPCODE::VWSUBU_WV) + .value("VWSUBU_WX", LIEF::assembly::riscv::OPCODE::VWSUBU_WX) + .value("VWSUB_VV", LIEF::assembly::riscv::OPCODE::VWSUB_VV) + .value("VWSUB_VX", LIEF::assembly::riscv::OPCODE::VWSUB_VX) + .value("VWSUB_WV", LIEF::assembly::riscv::OPCODE::VWSUB_WV) + .value("VWSUB_WX", LIEF::assembly::riscv::OPCODE::VWSUB_WX) + .value("VXOR_VI", LIEF::assembly::riscv::OPCODE::VXOR_VI) + .value("VXOR_VV", LIEF::assembly::riscv::OPCODE::VXOR_VV) + .value("VXOR_VX", LIEF::assembly::riscv::OPCODE::VXOR_VX) + .value("VZEXT_VF2", LIEF::assembly::riscv::OPCODE::VZEXT_VF2) + .value("VZEXT_VF4", LIEF::assembly::riscv::OPCODE::VZEXT_VF4) + .value("VZEXT_VF8", LIEF::assembly::riscv::OPCODE::VZEXT_VF8) + .value("WADD", LIEF::assembly::riscv::OPCODE::WADD) + .value("WADDA", LIEF::assembly::riscv::OPCODE::WADDA) + .value("WADDAU", LIEF::assembly::riscv::OPCODE::WADDAU) + .value("WADDU", LIEF::assembly::riscv::OPCODE::WADDU) + .value("WFI", LIEF::assembly::riscv::OPCODE::WFI) + .value("WMACC", LIEF::assembly::riscv::OPCODE::WMACC) + .value("WMACCSU", LIEF::assembly::riscv::OPCODE::WMACCSU) + .value("WMACCU", LIEF::assembly::riscv::OPCODE::WMACCU) + .value("WMUL", LIEF::assembly::riscv::OPCODE::WMUL) + .value("WMULSU", LIEF::assembly::riscv::OPCODE::WMULSU) + .value("WMULU", LIEF::assembly::riscv::OPCODE::WMULU) + .value("WRS_NTO", LIEF::assembly::riscv::OPCODE::WRS_NTO) + .value("WRS_STO", LIEF::assembly::riscv::OPCODE::WRS_STO) + .value("WSLA", LIEF::assembly::riscv::OPCODE::WSLA); + opcodes.value("WSLAI", LIEF::assembly::riscv::OPCODE::WSLAI) + .value("WSLL", LIEF::assembly::riscv::OPCODE::WSLL) + .value("WSLLI", LIEF::assembly::riscv::OPCODE::WSLLI) + .value("WSUB", LIEF::assembly::riscv::OPCODE::WSUB) + .value("WSUBA", LIEF::assembly::riscv::OPCODE::WSUBA) + .value("WSUBAU", LIEF::assembly::riscv::OPCODE::WSUBAU) + .value("WSUBU", LIEF::assembly::riscv::OPCODE::WSUBU) + .value("WZIP16P", LIEF::assembly::riscv::OPCODE::WZIP16P) + .value("WZIP8P", LIEF::assembly::riscv::OPCODE::WZIP8P) + .value("XNOR", LIEF::assembly::riscv::OPCODE::XNOR) + .value("XOR", LIEF::assembly::riscv::OPCODE::XOR) + .value("XORI", LIEF::assembly::riscv::OPCODE::XORI) + .value("XPERM4", LIEF::assembly::riscv::OPCODE::XPERM4) + .value("XPERM8", LIEF::assembly::riscv::OPCODE::XPERM8) + .value("ZEXT_H_RV32", LIEF::assembly::riscv::OPCODE::ZEXT_H_RV32) + .value("ZEXT_H_RV64", LIEF::assembly::riscv::OPCODE::ZEXT_H_RV64) + .value("ZIP16HP", LIEF::assembly::riscv::OPCODE::ZIP16HP) + .value("ZIP16P", LIEF::assembly::riscv::OPCODE::ZIP16P) + .value("ZIP8HP", LIEF::assembly::riscv::OPCODE::ZIP8HP) + .value("ZIP8P", LIEF::assembly::riscv::OPCODE::ZIP8P) + .value("ZIP_RV32", LIEF::assembly::riscv::OPCODE::ZIP_RV32) + .value("INSTRUCTION_LIST_END", LIEF::assembly::riscv::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/pyOperand.cpp b/vendor/lief/api/python/src/asm/riscv/pyOperand.cpp new file mode 100644 index 0000000..235ffec --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/riscv/Operand.hpp" + +#include "asm/riscv/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::riscv::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for a RISC-V instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(riscv::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/riscv/pyRegister.cpp b/vendor/lief/api/python/src/asm/riscv/pyRegister.cpp new file mode 100644 index 0000000..ec4b801 --- /dev/null +++ b/vendor/lief/api/python/src/asm/riscv/pyRegister.cpp @@ -0,0 +1,1105 @@ +#include "asm/riscv/init.hpp" + +#include "LIEF/asm/riscv/registers.hpp" + +namespace LIEF::assembly::riscv::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::riscv::REG::NoRegister) + .value("FCSR", LIEF::assembly::riscv::REG::FCSR) + .value("FFLAGS", LIEF::assembly::riscv::REG::FFLAGS) + .value("FRM", LIEF::assembly::riscv::REG::FRM) + .value("SF_VCIX_STATE", LIEF::assembly::riscv::REG::SF_VCIX_STATE) + .value("SSP", LIEF::assembly::riscv::REG::SSP) + .value("VL", LIEF::assembly::riscv::REG::VL) + .value("VLENB", LIEF::assembly::riscv::REG::VLENB) + .value("VTYPE", LIEF::assembly::riscv::REG::VTYPE) + .value("VXRM", LIEF::assembly::riscv::REG::VXRM) + .value("VXSAT", LIEF::assembly::riscv::REG::VXSAT) + .value("DUMMY_REG_PAIR_WITH_X0", LIEF::assembly::riscv::REG::DUMMY_REG_PAIR_WITH_X0) + .value("T0", LIEF::assembly::riscv::REG::T0) + .value("T1", LIEF::assembly::riscv::REG::T1) + .value("T2", LIEF::assembly::riscv::REG::T2) + .value("T3", LIEF::assembly::riscv::REG::T3) + .value("T4", LIEF::assembly::riscv::REG::T4) + .value("T5", LIEF::assembly::riscv::REG::T5) + .value("T6", LIEF::assembly::riscv::REG::T6) + .value("T7", LIEF::assembly::riscv::REG::T7) + .value("T8", LIEF::assembly::riscv::REG::T8) + .value("T9", LIEF::assembly::riscv::REG::T9) + .value("T10", LIEF::assembly::riscv::REG::T10) + .value("T11", LIEF::assembly::riscv::REG::T11) + .value("T12", LIEF::assembly::riscv::REG::T12) + .value("T13", LIEF::assembly::riscv::REG::T13) + .value("T14", LIEF::assembly::riscv::REG::T14) + .value("T15", LIEF::assembly::riscv::REG::T15) + .value("V0", LIEF::assembly::riscv::REG::V0) + .value("V1", LIEF::assembly::riscv::REG::V1) + .value("V2", LIEF::assembly::riscv::REG::V2) + .value("V3", LIEF::assembly::riscv::REG::V3) + .value("V4", LIEF::assembly::riscv::REG::V4) + .value("V5", LIEF::assembly::riscv::REG::V5) + .value("V6", LIEF::assembly::riscv::REG::V6) + .value("V7", LIEF::assembly::riscv::REG::V7) + .value("V8", LIEF::assembly::riscv::REG::V8) + .value("V9", LIEF::assembly::riscv::REG::V9) + .value("V10", LIEF::assembly::riscv::REG::V10) + .value("V11", LIEF::assembly::riscv::REG::V11) + .value("V12", LIEF::assembly::riscv::REG::V12) + .value("V13", LIEF::assembly::riscv::REG::V13) + .value("V14", LIEF::assembly::riscv::REG::V14) + .value("V15", LIEF::assembly::riscv::REG::V15) + .value("V16", LIEF::assembly::riscv::REG::V16) + .value("V17", LIEF::assembly::riscv::REG::V17) + .value("V18", LIEF::assembly::riscv::REG::V18) + .value("V19", LIEF::assembly::riscv::REG::V19) + .value("V20", LIEF::assembly::riscv::REG::V20) + .value("V21", LIEF::assembly::riscv::REG::V21) + .value("V22", LIEF::assembly::riscv::REG::V22) + .value("V23", LIEF::assembly::riscv::REG::V23) + .value("V24", LIEF::assembly::riscv::REG::V24) + .value("V25", LIEF::assembly::riscv::REG::V25) + .value("V26", LIEF::assembly::riscv::REG::V26) + .value("V27", LIEF::assembly::riscv::REG::V27) + .value("V28", LIEF::assembly::riscv::REG::V28) + .value("V29", LIEF::assembly::riscv::REG::V29) + .value("V30", LIEF::assembly::riscv::REG::V30) + .value("V31", LIEF::assembly::riscv::REG::V31) + .value("X0", LIEF::assembly::riscv::REG::X0) + .value("X1", LIEF::assembly::riscv::REG::X1) + .value("X2", LIEF::assembly::riscv::REG::X2) + .value("X3", LIEF::assembly::riscv::REG::X3) + .value("X4", LIEF::assembly::riscv::REG::X4) + .value("X5", LIEF::assembly::riscv::REG::X5) + .value("X6", LIEF::assembly::riscv::REG::X6) + .value("X7", LIEF::assembly::riscv::REG::X7) + .value("X8", LIEF::assembly::riscv::REG::X8) + .value("X9", LIEF::assembly::riscv::REG::X9) + .value("X10", LIEF::assembly::riscv::REG::X10) + .value("X11", LIEF::assembly::riscv::REG::X11) + .value("X12", LIEF::assembly::riscv::REG::X12) + .value("X13", LIEF::assembly::riscv::REG::X13) + .value("X14", LIEF::assembly::riscv::REG::X14) + .value("X15", LIEF::assembly::riscv::REG::X15) + .value("X16", LIEF::assembly::riscv::REG::X16) + .value("X17", LIEF::assembly::riscv::REG::X17) + .value("X18", LIEF::assembly::riscv::REG::X18) + .value("X19", LIEF::assembly::riscv::REG::X19) + .value("X20", LIEF::assembly::riscv::REG::X20) + .value("X21", LIEF::assembly::riscv::REG::X21) + .value("X22", LIEF::assembly::riscv::REG::X22) + .value("X23", LIEF::assembly::riscv::REG::X23) + .value("X24", LIEF::assembly::riscv::REG::X24) + .value("X25", LIEF::assembly::riscv::REG::X25) + .value("X26", LIEF::assembly::riscv::REG::X26) + .value("X27", LIEF::assembly::riscv::REG::X27) + .value("X28", LIEF::assembly::riscv::REG::X28) + .value("X29", LIEF::assembly::riscv::REG::X29) + .value("X30", LIEF::assembly::riscv::REG::X30) + .value("X31", LIEF::assembly::riscv::REG::X31) + .value("F0_D", LIEF::assembly::riscv::REG::F0_D) + .value("F1_D", LIEF::assembly::riscv::REG::F1_D) + .value("F2_D", LIEF::assembly::riscv::REG::F2_D) + .value("F3_D", LIEF::assembly::riscv::REG::F3_D) + .value("F4_D", LIEF::assembly::riscv::REG::F4_D) + .value("F5_D", LIEF::assembly::riscv::REG::F5_D) + .value("F6_D", LIEF::assembly::riscv::REG::F6_D) + .value("F7_D", LIEF::assembly::riscv::REG::F7_D) + .value("F8_D", LIEF::assembly::riscv::REG::F8_D) + .value("F9_D", LIEF::assembly::riscv::REG::F9_D) + .value("F10_D", LIEF::assembly::riscv::REG::F10_D) + .value("F11_D", LIEF::assembly::riscv::REG::F11_D) + .value("F12_D", LIEF::assembly::riscv::REG::F12_D) + .value("F13_D", LIEF::assembly::riscv::REG::F13_D) + .value("F14_D", LIEF::assembly::riscv::REG::F14_D) + .value("F15_D", LIEF::assembly::riscv::REG::F15_D) + .value("F16_D", LIEF::assembly::riscv::REG::F16_D) + .value("F17_D", LIEF::assembly::riscv::REG::F17_D) + .value("F18_D", LIEF::assembly::riscv::REG::F18_D) + .value("F19_D", LIEF::assembly::riscv::REG::F19_D) + .value("F20_D", LIEF::assembly::riscv::REG::F20_D) + .value("F21_D", LIEF::assembly::riscv::REG::F21_D) + .value("F22_D", LIEF::assembly::riscv::REG::F22_D) + .value("F23_D", LIEF::assembly::riscv::REG::F23_D) + .value("F24_D", LIEF::assembly::riscv::REG::F24_D) + .value("F25_D", LIEF::assembly::riscv::REG::F25_D) + .value("F26_D", LIEF::assembly::riscv::REG::F26_D) + .value("F27_D", LIEF::assembly::riscv::REG::F27_D) + .value("F28_D", LIEF::assembly::riscv::REG::F28_D) + .value("F29_D", LIEF::assembly::riscv::REG::F29_D) + .value("F30_D", LIEF::assembly::riscv::REG::F30_D) + .value("F31_D", LIEF::assembly::riscv::REG::F31_D) + .value("F0_F", LIEF::assembly::riscv::REG::F0_F) + .value("F1_F", LIEF::assembly::riscv::REG::F1_F) + .value("F2_F", LIEF::assembly::riscv::REG::F2_F) + .value("F3_F", LIEF::assembly::riscv::REG::F3_F) + .value("F4_F", LIEF::assembly::riscv::REG::F4_F) + .value("F5_F", LIEF::assembly::riscv::REG::F5_F) + .value("F6_F", LIEF::assembly::riscv::REG::F6_F) + .value("F7_F", LIEF::assembly::riscv::REG::F7_F) + .value("F8_F", LIEF::assembly::riscv::REG::F8_F) + .value("F9_F", LIEF::assembly::riscv::REG::F9_F) + .value("F10_F", LIEF::assembly::riscv::REG::F10_F) + .value("F11_F", LIEF::assembly::riscv::REG::F11_F) + .value("F12_F", LIEF::assembly::riscv::REG::F12_F) + .value("F13_F", LIEF::assembly::riscv::REG::F13_F) + .value("F14_F", LIEF::assembly::riscv::REG::F14_F) + .value("F15_F", LIEF::assembly::riscv::REG::F15_F) + .value("F16_F", LIEF::assembly::riscv::REG::F16_F) + .value("F17_F", LIEF::assembly::riscv::REG::F17_F) + .value("F18_F", LIEF::assembly::riscv::REG::F18_F) + .value("F19_F", LIEF::assembly::riscv::REG::F19_F) + .value("F20_F", LIEF::assembly::riscv::REG::F20_F) + .value("F21_F", LIEF::assembly::riscv::REG::F21_F) + .value("F22_F", LIEF::assembly::riscv::REG::F22_F) + .value("F23_F", LIEF::assembly::riscv::REG::F23_F) + .value("F24_F", LIEF::assembly::riscv::REG::F24_F) + .value("F25_F", LIEF::assembly::riscv::REG::F25_F) + .value("F26_F", LIEF::assembly::riscv::REG::F26_F) + .value("F27_F", LIEF::assembly::riscv::REG::F27_F) + .value("F28_F", LIEF::assembly::riscv::REG::F28_F) + .value("F29_F", LIEF::assembly::riscv::REG::F29_F) + .value("F30_F", LIEF::assembly::riscv::REG::F30_F) + .value("F31_F", LIEF::assembly::riscv::REG::F31_F) + .value("F0_H", LIEF::assembly::riscv::REG::F0_H) + .value("F1_H", LIEF::assembly::riscv::REG::F1_H) + .value("F2_H", LIEF::assembly::riscv::REG::F2_H) + .value("F3_H", LIEF::assembly::riscv::REG::F3_H) + .value("F4_H", LIEF::assembly::riscv::REG::F4_H) + .value("F5_H", LIEF::assembly::riscv::REG::F5_H) + .value("F6_H", LIEF::assembly::riscv::REG::F6_H) + .value("F7_H", LIEF::assembly::riscv::REG::F7_H) + .value("F8_H", LIEF::assembly::riscv::REG::F8_H) + .value("F9_H", LIEF::assembly::riscv::REG::F9_H) + .value("F10_H", LIEF::assembly::riscv::REG::F10_H) + .value("F11_H", LIEF::assembly::riscv::REG::F11_H) + .value("F12_H", LIEF::assembly::riscv::REG::F12_H) + .value("F13_H", LIEF::assembly::riscv::REG::F13_H) + .value("F14_H", LIEF::assembly::riscv::REG::F14_H) + .value("F15_H", LIEF::assembly::riscv::REG::F15_H) + .value("F16_H", LIEF::assembly::riscv::REG::F16_H) + .value("F17_H", LIEF::assembly::riscv::REG::F17_H) + .value("F18_H", LIEF::assembly::riscv::REG::F18_H) + .value("F19_H", LIEF::assembly::riscv::REG::F19_H) + .value("F20_H", LIEF::assembly::riscv::REG::F20_H) + .value("F21_H", LIEF::assembly::riscv::REG::F21_H) + .value("F22_H", LIEF::assembly::riscv::REG::F22_H) + .value("F23_H", LIEF::assembly::riscv::REG::F23_H) + .value("F24_H", LIEF::assembly::riscv::REG::F24_H) + .value("F25_H", LIEF::assembly::riscv::REG::F25_H) + .value("F26_H", LIEF::assembly::riscv::REG::F26_H) + .value("F27_H", LIEF::assembly::riscv::REG::F27_H) + .value("F28_H", LIEF::assembly::riscv::REG::F28_H) + .value("F29_H", LIEF::assembly::riscv::REG::F29_H) + .value("F30_H", LIEF::assembly::riscv::REG::F30_H) + .value("F31_H", LIEF::assembly::riscv::REG::F31_H) + .value("F0_Q", LIEF::assembly::riscv::REG::F0_Q) + .value("F1_Q", LIEF::assembly::riscv::REG::F1_Q) + .value("F2_Q", LIEF::assembly::riscv::REG::F2_Q) + .value("F3_Q", LIEF::assembly::riscv::REG::F3_Q) + .value("F4_Q", LIEF::assembly::riscv::REG::F4_Q) + .value("F5_Q", LIEF::assembly::riscv::REG::F5_Q) + .value("F6_Q", LIEF::assembly::riscv::REG::F6_Q) + .value("F7_Q", LIEF::assembly::riscv::REG::F7_Q) + .value("F8_Q", LIEF::assembly::riscv::REG::F8_Q) + .value("F9_Q", LIEF::assembly::riscv::REG::F9_Q) + .value("F10_Q", LIEF::assembly::riscv::REG::F10_Q) + .value("F11_Q", LIEF::assembly::riscv::REG::F11_Q) + .value("F12_Q", LIEF::assembly::riscv::REG::F12_Q) + .value("F13_Q", LIEF::assembly::riscv::REG::F13_Q) + .value("F14_Q", LIEF::assembly::riscv::REG::F14_Q) + .value("F15_Q", LIEF::assembly::riscv::REG::F15_Q) + .value("F16_Q", LIEF::assembly::riscv::REG::F16_Q) + .value("F17_Q", LIEF::assembly::riscv::REG::F17_Q) + .value("F18_Q", LIEF::assembly::riscv::REG::F18_Q) + .value("F19_Q", LIEF::assembly::riscv::REG::F19_Q) + .value("F20_Q", LIEF::assembly::riscv::REG::F20_Q) + .value("F21_Q", LIEF::assembly::riscv::REG::F21_Q) + .value("F22_Q", LIEF::assembly::riscv::REG::F22_Q) + .value("F23_Q", LIEF::assembly::riscv::REG::F23_Q) + .value("F24_Q", LIEF::assembly::riscv::REG::F24_Q) + .value("F25_Q", LIEF::assembly::riscv::REG::F25_Q) + .value("F26_Q", LIEF::assembly::riscv::REG::F26_Q) + .value("F27_Q", LIEF::assembly::riscv::REG::F27_Q) + .value("F28_Q", LIEF::assembly::riscv::REG::F28_Q) + .value("F29_Q", LIEF::assembly::riscv::REG::F29_Q) + .value("F30_Q", LIEF::assembly::riscv::REG::F30_Q) + .value("F31_Q", LIEF::assembly::riscv::REG::F31_Q) + .value("X0_H", LIEF::assembly::riscv::REG::X0_H) + .value("X1_H", LIEF::assembly::riscv::REG::X1_H) + .value("X2_H", LIEF::assembly::riscv::REG::X2_H) + .value("X3_H", LIEF::assembly::riscv::REG::X3_H) + .value("X4_H", LIEF::assembly::riscv::REG::X4_H) + .value("X5_H", LIEF::assembly::riscv::REG::X5_H) + .value("X6_H", LIEF::assembly::riscv::REG::X6_H) + .value("X7_H", LIEF::assembly::riscv::REG::X7_H) + .value("X8_H", LIEF::assembly::riscv::REG::X8_H) + .value("X9_H", LIEF::assembly::riscv::REG::X9_H) + .value("X10_H", LIEF::assembly::riscv::REG::X10_H) + .value("X11_H", LIEF::assembly::riscv::REG::X11_H) + .value("X12_H", LIEF::assembly::riscv::REG::X12_H) + .value("X13_H", LIEF::assembly::riscv::REG::X13_H) + .value("X14_H", LIEF::assembly::riscv::REG::X14_H) + .value("X15_H", LIEF::assembly::riscv::REG::X15_H) + .value("X16_H", LIEF::assembly::riscv::REG::X16_H) + .value("X17_H", LIEF::assembly::riscv::REG::X17_H) + .value("X18_H", LIEF::assembly::riscv::REG::X18_H) + .value("X19_H", LIEF::assembly::riscv::REG::X19_H) + .value("X20_H", LIEF::assembly::riscv::REG::X20_H) + .value("X21_H", LIEF::assembly::riscv::REG::X21_H) + .value("X22_H", LIEF::assembly::riscv::REG::X22_H) + .value("X23_H", LIEF::assembly::riscv::REG::X23_H) + .value("X24_H", LIEF::assembly::riscv::REG::X24_H) + .value("X25_H", LIEF::assembly::riscv::REG::X25_H) + .value("X26_H", LIEF::assembly::riscv::REG::X26_H) + .value("X27_H", LIEF::assembly::riscv::REG::X27_H) + .value("X28_H", LIEF::assembly::riscv::REG::X28_H) + .value("X29_H", LIEF::assembly::riscv::REG::X29_H) + .value("X30_H", LIEF::assembly::riscv::REG::X30_H) + .value("X31_H", LIEF::assembly::riscv::REG::X31_H) + .value("X0_Pair", LIEF::assembly::riscv::REG::X0_Pair) + .value("X0_W", LIEF::assembly::riscv::REG::X0_W) + .value("X1_W", LIEF::assembly::riscv::REG::X1_W) + .value("X2_W", LIEF::assembly::riscv::REG::X2_W) + .value("X3_W", LIEF::assembly::riscv::REG::X3_W) + .value("X4_W", LIEF::assembly::riscv::REG::X4_W) + .value("X5_W", LIEF::assembly::riscv::REG::X5_W) + .value("X6_W", LIEF::assembly::riscv::REG::X6_W) + .value("X7_W", LIEF::assembly::riscv::REG::X7_W) + .value("X8_W", LIEF::assembly::riscv::REG::X8_W) + .value("X9_W", LIEF::assembly::riscv::REG::X9_W) + .value("X10_W", LIEF::assembly::riscv::REG::X10_W) + .value("X11_W", LIEF::assembly::riscv::REG::X11_W) + .value("X12_W", LIEF::assembly::riscv::REG::X12_W) + .value("X13_W", LIEF::assembly::riscv::REG::X13_W) + .value("X14_W", LIEF::assembly::riscv::REG::X14_W) + .value("X15_W", LIEF::assembly::riscv::REG::X15_W) + .value("X16_W", LIEF::assembly::riscv::REG::X16_W) + .value("X17_W", LIEF::assembly::riscv::REG::X17_W) + .value("X18_W", LIEF::assembly::riscv::REG::X18_W) + .value("X19_W", LIEF::assembly::riscv::REG::X19_W) + .value("X20_W", LIEF::assembly::riscv::REG::X20_W) + .value("X21_W", LIEF::assembly::riscv::REG::X21_W) + .value("X22_W", LIEF::assembly::riscv::REG::X22_W) + .value("X23_W", LIEF::assembly::riscv::REG::X23_W) + .value("X24_W", LIEF::assembly::riscv::REG::X24_W) + .value("X25_W", LIEF::assembly::riscv::REG::X25_W) + .value("X26_W", LIEF::assembly::riscv::REG::X26_W) + .value("X27_W", LIEF::assembly::riscv::REG::X27_W) + .value("X28_W", LIEF::assembly::riscv::REG::X28_W) + .value("X29_W", LIEF::assembly::riscv::REG::X29_W) + .value("X30_W", LIEF::assembly::riscv::REG::X30_W) + .value("X31_W", LIEF::assembly::riscv::REG::X31_W) + .value("V0M2", LIEF::assembly::riscv::REG::V0M2) + .value("V0M4", LIEF::assembly::riscv::REG::V0M4) + .value("V0M8", LIEF::assembly::riscv::REG::V0M8) + .value("V2M2", LIEF::assembly::riscv::REG::V2M2) + .value("V4M2", LIEF::assembly::riscv::REG::V4M2) + .value("V4M4", LIEF::assembly::riscv::REG::V4M4) + .value("V6M2", LIEF::assembly::riscv::REG::V6M2) + .value("V8M2", LIEF::assembly::riscv::REG::V8M2) + .value("V8M4", LIEF::assembly::riscv::REG::V8M4) + .value("V8M8", LIEF::assembly::riscv::REG::V8M8) + .value("V10M2", LIEF::assembly::riscv::REG::V10M2) + .value("V12M2", LIEF::assembly::riscv::REG::V12M2) + .value("V12M4", LIEF::assembly::riscv::REG::V12M4) + .value("V14M2", LIEF::assembly::riscv::REG::V14M2) + .value("V16M2", LIEF::assembly::riscv::REG::V16M2); + reg.value("V16M4", LIEF::assembly::riscv::REG::V16M4) + .value("V16M8", LIEF::assembly::riscv::REG::V16M8) + .value("V18M2", LIEF::assembly::riscv::REG::V18M2) + .value("V20M2", LIEF::assembly::riscv::REG::V20M2) + .value("V20M4", LIEF::assembly::riscv::REG::V20M4) + .value("V22M2", LIEF::assembly::riscv::REG::V22M2) + .value("V24M2", LIEF::assembly::riscv::REG::V24M2) + .value("V24M4", LIEF::assembly::riscv::REG::V24M4) + .value("V24M8", LIEF::assembly::riscv::REG::V24M8) + .value("V26M2", LIEF::assembly::riscv::REG::V26M2) + .value("V28M2", LIEF::assembly::riscv::REG::V28M2) + .value("V28M4", LIEF::assembly::riscv::REG::V28M4) + .value("V30M2", LIEF::assembly::riscv::REG::V30M2) + .value("X2_X3", LIEF::assembly::riscv::REG::X2_X3) + .value("X4_X5", LIEF::assembly::riscv::REG::X4_X5) + .value("X6_X7", LIEF::assembly::riscv::REG::X6_X7) + .value("X8_X9", LIEF::assembly::riscv::REG::X8_X9) + .value("X10_X11", LIEF::assembly::riscv::REG::X10_X11) + .value("X12_X13", LIEF::assembly::riscv::REG::X12_X13) + .value("X14_X15", LIEF::assembly::riscv::REG::X14_X15) + .value("X16_X17", LIEF::assembly::riscv::REG::X16_X17) + .value("X18_X19", LIEF::assembly::riscv::REG::X18_X19) + .value("X20_X21", LIEF::assembly::riscv::REG::X20_X21) + .value("X22_X23", LIEF::assembly::riscv::REG::X22_X23) + .value("X24_X25", LIEF::assembly::riscv::REG::X24_X25) + .value("X26_X27", LIEF::assembly::riscv::REG::X26_X27) + .value("X28_X29", LIEF::assembly::riscv::REG::X28_X29) + .value("X30_X31", LIEF::assembly::riscv::REG::X30_X31) + .value("V1_V2", LIEF::assembly::riscv::REG::V1_V2) + .value("V2_V3", LIEF::assembly::riscv::REG::V2_V3) + .value("V3_V4", LIEF::assembly::riscv::REG::V3_V4) + .value("V4_V5", LIEF::assembly::riscv::REG::V4_V5) + .value("V5_V6", LIEF::assembly::riscv::REG::V5_V6) + .value("V6_V7", LIEF::assembly::riscv::REG::V6_V7) + .value("V7_V8", LIEF::assembly::riscv::REG::V7_V8) + .value("V8_V9", LIEF::assembly::riscv::REG::V8_V9) + .value("V9_V10", LIEF::assembly::riscv::REG::V9_V10) + .value("V10_V11", LIEF::assembly::riscv::REG::V10_V11) + .value("V11_V12", LIEF::assembly::riscv::REG::V11_V12) + .value("V12_V13", LIEF::assembly::riscv::REG::V12_V13) + .value("V13_V14", LIEF::assembly::riscv::REG::V13_V14) + .value("V14_V15", LIEF::assembly::riscv::REG::V14_V15) + .value("V15_V16", LIEF::assembly::riscv::REG::V15_V16) + .value("V16_V17", LIEF::assembly::riscv::REG::V16_V17) + .value("V17_V18", LIEF::assembly::riscv::REG::V17_V18) + .value("V18_V19", LIEF::assembly::riscv::REG::V18_V19) + .value("V19_V20", LIEF::assembly::riscv::REG::V19_V20) + .value("V20_V21", LIEF::assembly::riscv::REG::V20_V21) + .value("V21_V22", LIEF::assembly::riscv::REG::V21_V22) + .value("V22_V23", LIEF::assembly::riscv::REG::V22_V23) + .value("V23_V24", LIEF::assembly::riscv::REG::V23_V24) + .value("V24_V25", LIEF::assembly::riscv::REG::V24_V25) + .value("V25_V26", LIEF::assembly::riscv::REG::V25_V26) + .value("V26_V27", LIEF::assembly::riscv::REG::V26_V27) + .value("V27_V28", LIEF::assembly::riscv::REG::V27_V28) + .value("V28_V29", LIEF::assembly::riscv::REG::V28_V29) + .value("V29_V30", LIEF::assembly::riscv::REG::V29_V30) + .value("V30_V31", LIEF::assembly::riscv::REG::V30_V31) + .value("V0_V1", LIEF::assembly::riscv::REG::V0_V1) + .value("V2M2_V4M2", LIEF::assembly::riscv::REG::V2M2_V4M2) + .value("V4M2_V6M2", LIEF::assembly::riscv::REG::V4M2_V6M2) + .value("V6M2_V8M2", LIEF::assembly::riscv::REG::V6M2_V8M2) + .value("V8M2_V10M2", LIEF::assembly::riscv::REG::V8M2_V10M2) + .value("V10M2_V12M2", LIEF::assembly::riscv::REG::V10M2_V12M2) + .value("V12M2_V14M2", LIEF::assembly::riscv::REG::V12M2_V14M2) + .value("V14M2_V16M2", LIEF::assembly::riscv::REG::V14M2_V16M2) + .value("V16M2_V18M2", LIEF::assembly::riscv::REG::V16M2_V18M2) + .value("V18M2_V20M2", LIEF::assembly::riscv::REG::V18M2_V20M2) + .value("V20M2_V22M2", LIEF::assembly::riscv::REG::V20M2_V22M2) + .value("V22M2_V24M2", LIEF::assembly::riscv::REG::V22M2_V24M2) + .value("V24M2_V26M2", LIEF::assembly::riscv::REG::V24M2_V26M2) + .value("V26M2_V28M2", LIEF::assembly::riscv::REG::V26M2_V28M2) + .value("V28M2_V30M2", LIEF::assembly::riscv::REG::V28M2_V30M2) + .value("V0M2_V2M2", LIEF::assembly::riscv::REG::V0M2_V2M2) + .value("V4M4_V8M4", LIEF::assembly::riscv::REG::V4M4_V8M4) + .value("V8M4_V12M4", LIEF::assembly::riscv::REG::V8M4_V12M4) + .value("V12M4_V16M4", LIEF::assembly::riscv::REG::V12M4_V16M4) + .value("V16M4_V20M4", LIEF::assembly::riscv::REG::V16M4_V20M4) + .value("V20M4_V24M4", LIEF::assembly::riscv::REG::V20M4_V24M4) + .value("V24M4_V28M4", LIEF::assembly::riscv::REG::V24M4_V28M4) + .value("V0M4_V4M4", LIEF::assembly::riscv::REG::V0M4_V4M4) + .value("V1_V2_V3", LIEF::assembly::riscv::REG::V1_V2_V3) + .value("V2_V3_V4", LIEF::assembly::riscv::REG::V2_V3_V4) + .value("V3_V4_V5", LIEF::assembly::riscv::REG::V3_V4_V5) + .value("V4_V5_V6", LIEF::assembly::riscv::REG::V4_V5_V6) + .value("V5_V6_V7", LIEF::assembly::riscv::REG::V5_V6_V7) + .value("V6_V7_V8", LIEF::assembly::riscv::REG::V6_V7_V8) + .value("V7_V8_V9", LIEF::assembly::riscv::REG::V7_V8_V9) + .value("V8_V9_V10", LIEF::assembly::riscv::REG::V8_V9_V10) + .value("V9_V10_V11", LIEF::assembly::riscv::REG::V9_V10_V11) + .value("V10_V11_V12", LIEF::assembly::riscv::REG::V10_V11_V12) + .value("V11_V12_V13", LIEF::assembly::riscv::REG::V11_V12_V13) + .value("V12_V13_V14", LIEF::assembly::riscv::REG::V12_V13_V14) + .value("V13_V14_V15", LIEF::assembly::riscv::REG::V13_V14_V15) + .value("V14_V15_V16", LIEF::assembly::riscv::REG::V14_V15_V16) + .value("V15_V16_V17", LIEF::assembly::riscv::REG::V15_V16_V17) + .value("V16_V17_V18", LIEF::assembly::riscv::REG::V16_V17_V18) + .value("V17_V18_V19", LIEF::assembly::riscv::REG::V17_V18_V19) + .value("V18_V19_V20", LIEF::assembly::riscv::REG::V18_V19_V20) + .value("V19_V20_V21", LIEF::assembly::riscv::REG::V19_V20_V21) + .value("V20_V21_V22", LIEF::assembly::riscv::REG::V20_V21_V22) + .value("V21_V22_V23", LIEF::assembly::riscv::REG::V21_V22_V23) + .value("V22_V23_V24", LIEF::assembly::riscv::REG::V22_V23_V24) + .value("V23_V24_V25", LIEF::assembly::riscv::REG::V23_V24_V25) + .value("V24_V25_V26", LIEF::assembly::riscv::REG::V24_V25_V26) + .value("V25_V26_V27", LIEF::assembly::riscv::REG::V25_V26_V27) + .value("V26_V27_V28", LIEF::assembly::riscv::REG::V26_V27_V28) + .value("V27_V28_V29", LIEF::assembly::riscv::REG::V27_V28_V29) + .value("V28_V29_V30", LIEF::assembly::riscv::REG::V28_V29_V30) + .value("V29_V30_V31", LIEF::assembly::riscv::REG::V29_V30_V31) + .value("V0_V1_V2", LIEF::assembly::riscv::REG::V0_V1_V2) + .value("V2M2_V4M2_V6M2", LIEF::assembly::riscv::REG::V2M2_V4M2_V6M2) + .value("V4M2_V6M2_V8M2", LIEF::assembly::riscv::REG::V4M2_V6M2_V8M2) + .value("V6M2_V8M2_V10M2", LIEF::assembly::riscv::REG::V6M2_V8M2_V10M2) + .value("V8M2_V10M2_V12M2", LIEF::assembly::riscv::REG::V8M2_V10M2_V12M2) + .value("V10M2_V12M2_V14M2", LIEF::assembly::riscv::REG::V10M2_V12M2_V14M2) + .value("V12M2_V14M2_V16M2", LIEF::assembly::riscv::REG::V12M2_V14M2_V16M2) + .value("V14M2_V16M2_V18M2", LIEF::assembly::riscv::REG::V14M2_V16M2_V18M2) + .value("V16M2_V18M2_V20M2", LIEF::assembly::riscv::REG::V16M2_V18M2_V20M2) + .value("V18M2_V20M2_V22M2", LIEF::assembly::riscv::REG::V18M2_V20M2_V22M2) + .value("V20M2_V22M2_V24M2", LIEF::assembly::riscv::REG::V20M2_V22M2_V24M2) + .value("V22M2_V24M2_V26M2", LIEF::assembly::riscv::REG::V22M2_V24M2_V26M2) + .value("V24M2_V26M2_V28M2", LIEF::assembly::riscv::REG::V24M2_V26M2_V28M2) + .value("V26M2_V28M2_V30M2", LIEF::assembly::riscv::REG::V26M2_V28M2_V30M2) + .value("V0M2_V2M2_V4M2", LIEF::assembly::riscv::REG::V0M2_V2M2_V4M2) + .value("V1_V2_V3_V4", LIEF::assembly::riscv::REG::V1_V2_V3_V4) + .value("V2_V3_V4_V5", LIEF::assembly::riscv::REG::V2_V3_V4_V5) + .value("V3_V4_V5_V6", LIEF::assembly::riscv::REG::V3_V4_V5_V6) + .value("V4_V5_V6_V7", LIEF::assembly::riscv::REG::V4_V5_V6_V7) + .value("V5_V6_V7_V8", LIEF::assembly::riscv::REG::V5_V6_V7_V8) + .value("V6_V7_V8_V9", LIEF::assembly::riscv::REG::V6_V7_V8_V9) + .value("V7_V8_V9_V10", LIEF::assembly::riscv::REG::V7_V8_V9_V10) + .value("V8_V9_V10_V11", LIEF::assembly::riscv::REG::V8_V9_V10_V11) + .value("V9_V10_V11_V12", LIEF::assembly::riscv::REG::V9_V10_V11_V12) + .value("V10_V11_V12_V13", LIEF::assembly::riscv::REG::V10_V11_V12_V13) + .value("V11_V12_V13_V14", LIEF::assembly::riscv::REG::V11_V12_V13_V14) + .value("V12_V13_V14_V15", LIEF::assembly::riscv::REG::V12_V13_V14_V15) + .value("V13_V14_V15_V16", LIEF::assembly::riscv::REG::V13_V14_V15_V16) + .value("V14_V15_V16_V17", LIEF::assembly::riscv::REG::V14_V15_V16_V17) + .value("V15_V16_V17_V18", LIEF::assembly::riscv::REG::V15_V16_V17_V18) + .value("V16_V17_V18_V19", LIEF::assembly::riscv::REG::V16_V17_V18_V19) + .value("V17_V18_V19_V20", LIEF::assembly::riscv::REG::V17_V18_V19_V20) + .value("V18_V19_V20_V21", LIEF::assembly::riscv::REG::V18_V19_V20_V21) + .value("V19_V20_V21_V22", LIEF::assembly::riscv::REG::V19_V20_V21_V22) + .value("V20_V21_V22_V23", LIEF::assembly::riscv::REG::V20_V21_V22_V23) + .value("V21_V22_V23_V24", LIEF::assembly::riscv::REG::V21_V22_V23_V24) + .value("V22_V23_V24_V25", LIEF::assembly::riscv::REG::V22_V23_V24_V25) + .value("V23_V24_V25_V26", LIEF::assembly::riscv::REG::V23_V24_V25_V26) + .value("V24_V25_V26_V27", LIEF::assembly::riscv::REG::V24_V25_V26_V27) + .value("V25_V26_V27_V28", LIEF::assembly::riscv::REG::V25_V26_V27_V28) + .value("V26_V27_V28_V29", LIEF::assembly::riscv::REG::V26_V27_V28_V29) + .value("V27_V28_V29_V30", LIEF::assembly::riscv::REG::V27_V28_V29_V30) + .value("V28_V29_V30_V31", LIEF::assembly::riscv::REG::V28_V29_V30_V31) + .value("V0_V1_V2_V3", LIEF::assembly::riscv::REG::V0_V1_V2_V3) + .value("V2M2_V4M2_V6M2_V8M2", LIEF::assembly::riscv::REG::V2M2_V4M2_V6M2_V8M2) + .value("V4M2_V6M2_V8M2_V10M2", LIEF::assembly::riscv::REG::V4M2_V6M2_V8M2_V10M2) + .value("V6M2_V8M2_V10M2_V12M2", LIEF::assembly::riscv::REG::V6M2_V8M2_V10M2_V12M2) + .value("V8M2_V10M2_V12M2_V14M2", LIEF::assembly::riscv::REG::V8M2_V10M2_V12M2_V14M2) + .value("V10M2_V12M2_V14M2_V16M2", LIEF::assembly::riscv::REG::V10M2_V12M2_V14M2_V16M2) + .value("V12M2_V14M2_V16M2_V18M2", LIEF::assembly::riscv::REG::V12M2_V14M2_V16M2_V18M2) + .value("V14M2_V16M2_V18M2_V20M2", LIEF::assembly::riscv::REG::V14M2_V16M2_V18M2_V20M2) + .value("V16M2_V18M2_V20M2_V22M2", LIEF::assembly::riscv::REG::V16M2_V18M2_V20M2_V22M2) + .value("V18M2_V20M2_V22M2_V24M2", LIEF::assembly::riscv::REG::V18M2_V20M2_V22M2_V24M2) + .value("V20M2_V22M2_V24M2_V26M2", LIEF::assembly::riscv::REG::V20M2_V22M2_V24M2_V26M2) + .value("V22M2_V24M2_V26M2_V28M2", LIEF::assembly::riscv::REG::V22M2_V24M2_V26M2_V28M2) + .value("V24M2_V26M2_V28M2_V30M2", LIEF::assembly::riscv::REG::V24M2_V26M2_V28M2_V30M2) + .value("V0M2_V2M2_V4M2_V6M2", LIEF::assembly::riscv::REG::V0M2_V2M2_V4M2_V6M2) + .value("V1_V2_V3_V4_V5", LIEF::assembly::riscv::REG::V1_V2_V3_V4_V5) + .value("V2_V3_V4_V5_V6", LIEF::assembly::riscv::REG::V2_V3_V4_V5_V6) + .value("V3_V4_V5_V6_V7", LIEF::assembly::riscv::REG::V3_V4_V5_V6_V7) + .value("V4_V5_V6_V7_V8", LIEF::assembly::riscv::REG::V4_V5_V6_V7_V8) + .value("V5_V6_V7_V8_V9", LIEF::assembly::riscv::REG::V5_V6_V7_V8_V9) + .value("V6_V7_V8_V9_V10", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10) + .value("V7_V8_V9_V10_V11", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11) + .value("V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V8_V9_V10_V11_V12) + .value("V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V9_V10_V11_V12_V13) + .value("V10_V11_V12_V13_V14", LIEF::assembly::riscv::REG::V10_V11_V12_V13_V14) + .value("V11_V12_V13_V14_V15", LIEF::assembly::riscv::REG::V11_V12_V13_V14_V15) + .value("V12_V13_V14_V15_V16", LIEF::assembly::riscv::REG::V12_V13_V14_V15_V16) + .value("V13_V14_V15_V16_V17", LIEF::assembly::riscv::REG::V13_V14_V15_V16_V17) + .value("V14_V15_V16_V17_V18", LIEF::assembly::riscv::REG::V14_V15_V16_V17_V18) + .value("V15_V16_V17_V18_V19", LIEF::assembly::riscv::REG::V15_V16_V17_V18_V19) + .value("V16_V17_V18_V19_V20", LIEF::assembly::riscv::REG::V16_V17_V18_V19_V20) + .value("V17_V18_V19_V20_V21", LIEF::assembly::riscv::REG::V17_V18_V19_V20_V21) + .value("V18_V19_V20_V21_V22", LIEF::assembly::riscv::REG::V18_V19_V20_V21_V22) + .value("V19_V20_V21_V22_V23", LIEF::assembly::riscv::REG::V19_V20_V21_V22_V23) + .value("V20_V21_V22_V23_V24", LIEF::assembly::riscv::REG::V20_V21_V22_V23_V24) + .value("V21_V22_V23_V24_V25", LIEF::assembly::riscv::REG::V21_V22_V23_V24_V25) + .value("V22_V23_V24_V25_V26", LIEF::assembly::riscv::REG::V22_V23_V24_V25_V26) + .value("V23_V24_V25_V26_V27", LIEF::assembly::riscv::REG::V23_V24_V25_V26_V27) + .value("V24_V25_V26_V27_V28", LIEF::assembly::riscv::REG::V24_V25_V26_V27_V28) + .value("V25_V26_V27_V28_V29", LIEF::assembly::riscv::REG::V25_V26_V27_V28_V29) + .value("V26_V27_V28_V29_V30", LIEF::assembly::riscv::REG::V26_V27_V28_V29_V30) + .value("V27_V28_V29_V30_V31", LIEF::assembly::riscv::REG::V27_V28_V29_V30_V31) + .value("V0_V1_V2_V3_V4", LIEF::assembly::riscv::REG::V0_V1_V2_V3_V4) + .value("V1_V2_V3_V4_V5_V6", LIEF::assembly::riscv::REG::V1_V2_V3_V4_V5_V6) + .value("V2_V3_V4_V5_V6_V7", LIEF::assembly::riscv::REG::V2_V3_V4_V5_V6_V7) + .value("V3_V4_V5_V6_V7_V8", LIEF::assembly::riscv::REG::V3_V4_V5_V6_V7_V8) + .value("V4_V5_V6_V7_V8_V9", LIEF::assembly::riscv::REG::V4_V5_V6_V7_V8_V9) + .value("V5_V6_V7_V8_V9_V10", LIEF::assembly::riscv::REG::V5_V6_V7_V8_V9_V10) + .value("V6_V7_V8_V9_V10_V11", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10_V11) + .value("V7_V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11_V12) + .value("V8_V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V8_V9_V10_V11_V12_V13) + .value("V9_V10_V11_V12_V13_V14", LIEF::assembly::riscv::REG::V9_V10_V11_V12_V13_V14) + .value("V10_V11_V12_V13_V14_V15", LIEF::assembly::riscv::REG::V10_V11_V12_V13_V14_V15) + .value("V11_V12_V13_V14_V15_V16", LIEF::assembly::riscv::REG::V11_V12_V13_V14_V15_V16) + .value("V12_V13_V14_V15_V16_V17", LIEF::assembly::riscv::REG::V12_V13_V14_V15_V16_V17) + .value("V13_V14_V15_V16_V17_V18", LIEF::assembly::riscv::REG::V13_V14_V15_V16_V17_V18) + .value("V14_V15_V16_V17_V18_V19", LIEF::assembly::riscv::REG::V14_V15_V16_V17_V18_V19) + .value("V15_V16_V17_V18_V19_V20", LIEF::assembly::riscv::REG::V15_V16_V17_V18_V19_V20) + .value("V16_V17_V18_V19_V20_V21", LIEF::assembly::riscv::REG::V16_V17_V18_V19_V20_V21) + .value("V17_V18_V19_V20_V21_V22", LIEF::assembly::riscv::REG::V17_V18_V19_V20_V21_V22) + .value("V18_V19_V20_V21_V22_V23", LIEF::assembly::riscv::REG::V18_V19_V20_V21_V22_V23) + .value("V19_V20_V21_V22_V23_V24", LIEF::assembly::riscv::REG::V19_V20_V21_V22_V23_V24) + .value("V20_V21_V22_V23_V24_V25", LIEF::assembly::riscv::REG::V20_V21_V22_V23_V24_V25) + .value("V21_V22_V23_V24_V25_V26", LIEF::assembly::riscv::REG::V21_V22_V23_V24_V25_V26) + .value("V22_V23_V24_V25_V26_V27", LIEF::assembly::riscv::REG::V22_V23_V24_V25_V26_V27) + .value("V23_V24_V25_V26_V27_V28", LIEF::assembly::riscv::REG::V23_V24_V25_V26_V27_V28) + .value("V24_V25_V26_V27_V28_V29", LIEF::assembly::riscv::REG::V24_V25_V26_V27_V28_V29) + .value("V25_V26_V27_V28_V29_V30", LIEF::assembly::riscv::REG::V25_V26_V27_V28_V29_V30) + .value("V26_V27_V28_V29_V30_V31", LIEF::assembly::riscv::REG::V26_V27_V28_V29_V30_V31) + .value("V0_V1_V2_V3_V4_V5", LIEF::assembly::riscv::REG::V0_V1_V2_V3_V4_V5) + .value("V1_V2_V3_V4_V5_V6_V7", LIEF::assembly::riscv::REG::V1_V2_V3_V4_V5_V6_V7) + .value("V2_V3_V4_V5_V6_V7_V8", LIEF::assembly::riscv::REG::V2_V3_V4_V5_V6_V7_V8) + .value("V3_V4_V5_V6_V7_V8_V9", LIEF::assembly::riscv::REG::V3_V4_V5_V6_V7_V8_V9) + .value("V4_V5_V6_V7_V8_V9_V10", LIEF::assembly::riscv::REG::V4_V5_V6_V7_V8_V9_V10) + .value("V5_V6_V7_V8_V9_V10_V11", LIEF::assembly::riscv::REG::V5_V6_V7_V8_V9_V10_V11) + .value("V6_V7_V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10_V11_V12) + .value("V7_V8_V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11_V12_V13) + .value("V8_V9_V10_V11_V12_V13_V14", LIEF::assembly::riscv::REG::V8_V9_V10_V11_V12_V13_V14) + .value("V9_V10_V11_V12_V13_V14_V15", LIEF::assembly::riscv::REG::V9_V10_V11_V12_V13_V14_V15) + .value("V10_V11_V12_V13_V14_V15_V16", LIEF::assembly::riscv::REG::V10_V11_V12_V13_V14_V15_V16) + .value("V11_V12_V13_V14_V15_V16_V17", LIEF::assembly::riscv::REG::V11_V12_V13_V14_V15_V16_V17) + .value("V12_V13_V14_V15_V16_V17_V18", LIEF::assembly::riscv::REG::V12_V13_V14_V15_V16_V17_V18) + .value("V13_V14_V15_V16_V17_V18_V19", LIEF::assembly::riscv::REG::V13_V14_V15_V16_V17_V18_V19) + .value("V14_V15_V16_V17_V18_V19_V20", LIEF::assembly::riscv::REG::V14_V15_V16_V17_V18_V19_V20) + .value("V15_V16_V17_V18_V19_V20_V21", LIEF::assembly::riscv::REG::V15_V16_V17_V18_V19_V20_V21) + .value("V16_V17_V18_V19_V20_V21_V22", LIEF::assembly::riscv::REG::V16_V17_V18_V19_V20_V21_V22) + .value("V17_V18_V19_V20_V21_V22_V23", LIEF::assembly::riscv::REG::V17_V18_V19_V20_V21_V22_V23) + .value("V18_V19_V20_V21_V22_V23_V24", LIEF::assembly::riscv::REG::V18_V19_V20_V21_V22_V23_V24) + .value("V19_V20_V21_V22_V23_V24_V25", LIEF::assembly::riscv::REG::V19_V20_V21_V22_V23_V24_V25) + .value("V20_V21_V22_V23_V24_V25_V26", LIEF::assembly::riscv::REG::V20_V21_V22_V23_V24_V25_V26) + .value("V21_V22_V23_V24_V25_V26_V27", LIEF::assembly::riscv::REG::V21_V22_V23_V24_V25_V26_V27) + .value("V22_V23_V24_V25_V26_V27_V28", LIEF::assembly::riscv::REG::V22_V23_V24_V25_V26_V27_V28) + .value("V23_V24_V25_V26_V27_V28_V29", LIEF::assembly::riscv::REG::V23_V24_V25_V26_V27_V28_V29) + .value("V24_V25_V26_V27_V28_V29_V30", LIEF::assembly::riscv::REG::V24_V25_V26_V27_V28_V29_V30) + .value("V25_V26_V27_V28_V29_V30_V31", LIEF::assembly::riscv::REG::V25_V26_V27_V28_V29_V30_V31) + .value("V0_V1_V2_V3_V4_V5_V6", LIEF::assembly::riscv::REG::V0_V1_V2_V3_V4_V5_V6) + .value("V1_V2_V3_V4_V5_V6_V7_V8", LIEF::assembly::riscv::REG::V1_V2_V3_V4_V5_V6_V7_V8) + .value("V2_V3_V4_V5_V6_V7_V8_V9", LIEF::assembly::riscv::REG::V2_V3_V4_V5_V6_V7_V8_V9) + .value("V3_V4_V5_V6_V7_V8_V9_V10", LIEF::assembly::riscv::REG::V3_V4_V5_V6_V7_V8_V9_V10) + .value("V4_V5_V6_V7_V8_V9_V10_V11", LIEF::assembly::riscv::REG::V4_V5_V6_V7_V8_V9_V10_V11) + .value("V5_V6_V7_V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V5_V6_V7_V8_V9_V10_V11_V12) + .value("V6_V7_V8_V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10_V11_V12_V13) + .value("V7_V8_V9_V10_V11_V12_V13_V14", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11_V12_V13_V14) + .value("V8_V9_V10_V11_V12_V13_V14_V15", LIEF::assembly::riscv::REG::V8_V9_V10_V11_V12_V13_V14_V15) + .value("V9_V10_V11_V12_V13_V14_V15_V16", LIEF::assembly::riscv::REG::V9_V10_V11_V12_V13_V14_V15_V16) + .value("V10_V11_V12_V13_V14_V15_V16_V17", LIEF::assembly::riscv::REG::V10_V11_V12_V13_V14_V15_V16_V17) + .value("V11_V12_V13_V14_V15_V16_V17_V18", LIEF::assembly::riscv::REG::V11_V12_V13_V14_V15_V16_V17_V18) + .value("V12_V13_V14_V15_V16_V17_V18_V19", LIEF::assembly::riscv::REG::V12_V13_V14_V15_V16_V17_V18_V19) + .value("V13_V14_V15_V16_V17_V18_V19_V20", LIEF::assembly::riscv::REG::V13_V14_V15_V16_V17_V18_V19_V20) + .value("V14_V15_V16_V17_V18_V19_V20_V21", LIEF::assembly::riscv::REG::V14_V15_V16_V17_V18_V19_V20_V21) + .value("V15_V16_V17_V18_V19_V20_V21_V22", LIEF::assembly::riscv::REG::V15_V16_V17_V18_V19_V20_V21_V22) + .value("V16_V17_V18_V19_V20_V21_V22_V23", LIEF::assembly::riscv::REG::V16_V17_V18_V19_V20_V21_V22_V23) + .value("V17_V18_V19_V20_V21_V22_V23_V24", LIEF::assembly::riscv::REG::V17_V18_V19_V20_V21_V22_V23_V24) + .value("V18_V19_V20_V21_V22_V23_V24_V25", LIEF::assembly::riscv::REG::V18_V19_V20_V21_V22_V23_V24_V25) + .value("V19_V20_V21_V22_V23_V24_V25_V26", LIEF::assembly::riscv::REG::V19_V20_V21_V22_V23_V24_V25_V26) + .value("V20_V21_V22_V23_V24_V25_V26_V27", LIEF::assembly::riscv::REG::V20_V21_V22_V23_V24_V25_V26_V27) + .value("V21_V22_V23_V24_V25_V26_V27_V28", LIEF::assembly::riscv::REG::V21_V22_V23_V24_V25_V26_V27_V28) + .value("V22_V23_V24_V25_V26_V27_V28_V29", LIEF::assembly::riscv::REG::V22_V23_V24_V25_V26_V27_V28_V29) + .value("V23_V24_V25_V26_V27_V28_V29_V30", LIEF::assembly::riscv::REG::V23_V24_V25_V26_V27_V28_V29_V30) + .value("V24_V25_V26_V27_V28_V29_V30_V31", LIEF::assembly::riscv::REG::V24_V25_V26_V27_V28_V29_V30_V31) + .value("V0_V1_V2_V3_V4_V5_V6_V7", LIEF::assembly::riscv::REG::V0_V1_V2_V3_V4_V5_V6_V7) + .value("NUM_TARGET_REGS", LIEF::assembly::riscv::REG::NUM_TARGET_REGS) + ; +} + +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "SYSREG"); + reg.value("fflags", LIEF::assembly::riscv::SYSREG::fflags) + .value("frm", LIEF::assembly::riscv::SYSREG::frm) + .value("fcsr", LIEF::assembly::riscv::SYSREG::fcsr) + .value("vstart", LIEF::assembly::riscv::SYSREG::vstart) + .value("vxsat", LIEF::assembly::riscv::SYSREG::vxsat) + .value("vxrm", LIEF::assembly::riscv::SYSREG::vxrm) + .value("vcsr", LIEF::assembly::riscv::SYSREG::vcsr) + .value("ssp", LIEF::assembly::riscv::SYSREG::ssp) + .value("seed", LIEF::assembly::riscv::SYSREG::seed) + .value("jvt", LIEF::assembly::riscv::SYSREG::jvt) + .value("sstatus", LIEF::assembly::riscv::SYSREG::sstatus) + .value("sie", LIEF::assembly::riscv::SYSREG::sie) + .value("stvec", LIEF::assembly::riscv::SYSREG::stvec) + .value("scounteren", LIEF::assembly::riscv::SYSREG::scounteren) + .value("sf_stvt", LIEF::assembly::riscv::SYSREG::sf_stvt) + .value("senvcfg", LIEF::assembly::riscv::SYSREG::senvcfg) + .value("sstateen0", LIEF::assembly::riscv::SYSREG::sstateen0) + .value("sstateen1", LIEF::assembly::riscv::SYSREG::sstateen1) + .value("sstateen2", LIEF::assembly::riscv::SYSREG::sstateen2) + .value("sstateen3", LIEF::assembly::riscv::SYSREG::sstateen3) + .value("sieh", LIEF::assembly::riscv::SYSREG::sieh) + .value("scountinhibit", LIEF::assembly::riscv::SYSREG::scountinhibit) + .value("sscratch", LIEF::assembly::riscv::SYSREG::sscratch) + .value("sepc", LIEF::assembly::riscv::SYSREG::sepc) + .value("scause", LIEF::assembly::riscv::SYSREG::scause) + .value("sbadaddr", LIEF::assembly::riscv::SYSREG::sbadaddr) + .value("sip", LIEF::assembly::riscv::SYSREG::sip) + .value("sf_snxti", LIEF::assembly::riscv::SYSREG::sf_snxti) + .value("sf_sintstatus", LIEF::assembly::riscv::SYSREG::sf_sintstatus) + .value("sf_sscratchcsw", LIEF::assembly::riscv::SYSREG::sf_sscratchcsw) + .value("sf_sscratchcswl", LIEF::assembly::riscv::SYSREG::sf_sscratchcswl) + .value("stimecmp", LIEF::assembly::riscv::SYSREG::stimecmp) + .value("sctrctl", LIEF::assembly::riscv::SYSREG::sctrctl) + .value("sctrstatus", LIEF::assembly::riscv::SYSREG::sctrstatus) + .value("siselect", LIEF::assembly::riscv::SYSREG::siselect) + .value("sireg", LIEF::assembly::riscv::SYSREG::sireg) + .value("sireg2", LIEF::assembly::riscv::SYSREG::sireg2) + .value("sireg3", LIEF::assembly::riscv::SYSREG::sireg3) + .value("siph", LIEF::assembly::riscv::SYSREG::siph) + .value("sireg4", LIEF::assembly::riscv::SYSREG::sireg4) + .value("sireg5", LIEF::assembly::riscv::SYSREG::sireg5) + .value("sireg6", LIEF::assembly::riscv::SYSREG::sireg6) + .value("stopei", LIEF::assembly::riscv::SYSREG::stopei) + .value("stimecmph", LIEF::assembly::riscv::SYSREG::stimecmph) + .value("sctrdepth", LIEF::assembly::riscv::SYSREG::sctrdepth) + .value("satp", LIEF::assembly::riscv::SYSREG::satp) + .value("srmcfg", LIEF::assembly::riscv::SYSREG::srmcfg) + .value("vsstatus", LIEF::assembly::riscv::SYSREG::vsstatus) + .value("vsie", LIEF::assembly::riscv::SYSREG::vsie) + .value("vstvec", LIEF::assembly::riscv::SYSREG::vstvec) + .value("vsieh", LIEF::assembly::riscv::SYSREG::vsieh) + .value("vsscratch", LIEF::assembly::riscv::SYSREG::vsscratch) + .value("vsepc", LIEF::assembly::riscv::SYSREG::vsepc) + .value("vscause", LIEF::assembly::riscv::SYSREG::vscause) + .value("vstval", LIEF::assembly::riscv::SYSREG::vstval) + .value("vsip", LIEF::assembly::riscv::SYSREG::vsip) + .value("vstimecmp", LIEF::assembly::riscv::SYSREG::vstimecmp) + .value("vsctrctl", LIEF::assembly::riscv::SYSREG::vsctrctl) + .value("vsiselect", LIEF::assembly::riscv::SYSREG::vsiselect) + .value("vsireg", LIEF::assembly::riscv::SYSREG::vsireg) + .value("vsireg2", LIEF::assembly::riscv::SYSREG::vsireg2) + .value("vsireg3", LIEF::assembly::riscv::SYSREG::vsireg3) + .value("vsiph", LIEF::assembly::riscv::SYSREG::vsiph) + .value("vsireg4", LIEF::assembly::riscv::SYSREG::vsireg4) + .value("vsireg5", LIEF::assembly::riscv::SYSREG::vsireg5) + .value("vsireg6", LIEF::assembly::riscv::SYSREG::vsireg6) + .value("vstopei", LIEF::assembly::riscv::SYSREG::vstopei) + .value("vstimecmph", LIEF::assembly::riscv::SYSREG::vstimecmph) + .value("vsatp", LIEF::assembly::riscv::SYSREG::vsatp) + .value("mstatus", LIEF::assembly::riscv::SYSREG::mstatus) + .value("misa", LIEF::assembly::riscv::SYSREG::misa) + .value("medeleg", LIEF::assembly::riscv::SYSREG::medeleg) + .value("mideleg", LIEF::assembly::riscv::SYSREG::mideleg) + .value("mie", LIEF::assembly::riscv::SYSREG::mie) + .value("mtvec", LIEF::assembly::riscv::SYSREG::mtvec) + .value("mcounteren", LIEF::assembly::riscv::SYSREG::mcounteren) + .value("sf_mtvt", LIEF::assembly::riscv::SYSREG::sf_mtvt) + .value("mvien", LIEF::assembly::riscv::SYSREG::mvien) + .value("mvip", LIEF::assembly::riscv::SYSREG::mvip) + .value("menvcfg", LIEF::assembly::riscv::SYSREG::menvcfg) + .value("mstateen0", LIEF::assembly::riscv::SYSREG::mstateen0) + .value("mstateen1", LIEF::assembly::riscv::SYSREG::mstateen1) + .value("mstateen2", LIEF::assembly::riscv::SYSREG::mstateen2) + .value("mstateen3", LIEF::assembly::riscv::SYSREG::mstateen3) + .value("mstatush", LIEF::assembly::riscv::SYSREG::mstatush) + .value("medelegh", LIEF::assembly::riscv::SYSREG::medelegh) + .value("midelegh", LIEF::assembly::riscv::SYSREG::midelegh) + .value("mieh", LIEF::assembly::riscv::SYSREG::mieh) + .value("mvienh", LIEF::assembly::riscv::SYSREG::mvienh) + .value("mviph", LIEF::assembly::riscv::SYSREG::mviph) + .value("menvcfgh", LIEF::assembly::riscv::SYSREG::menvcfgh) + .value("mstateen0h", LIEF::assembly::riscv::SYSREG::mstateen0h) + .value("mstateen1h", LIEF::assembly::riscv::SYSREG::mstateen1h) + .value("mstateen2h", LIEF::assembly::riscv::SYSREG::mstateen2h) + .value("mstateen3h", LIEF::assembly::riscv::SYSREG::mstateen3h) + .value("mcountinhibit", LIEF::assembly::riscv::SYSREG::mcountinhibit) + .value("mcyclecfg", LIEF::assembly::riscv::SYSREG::mcyclecfg) + .value("minstretcfg", LIEF::assembly::riscv::SYSREG::minstretcfg) + .value("mhpmevent3", LIEF::assembly::riscv::SYSREG::mhpmevent3) + .value("mhpmevent4", LIEF::assembly::riscv::SYSREG::mhpmevent4) + .value("mhpmevent5", LIEF::assembly::riscv::SYSREG::mhpmevent5) + .value("mhpmevent6", LIEF::assembly::riscv::SYSREG::mhpmevent6) + .value("mhpmevent7", LIEF::assembly::riscv::SYSREG::mhpmevent7) + .value("mhpmevent8", LIEF::assembly::riscv::SYSREG::mhpmevent8) + .value("mhpmevent9", LIEF::assembly::riscv::SYSREG::mhpmevent9) + .value("mhpmevent10", LIEF::assembly::riscv::SYSREG::mhpmevent10) + .value("mhpmevent11", LIEF::assembly::riscv::SYSREG::mhpmevent11) + .value("mhpmevent12", LIEF::assembly::riscv::SYSREG::mhpmevent12) + .value("mhpmevent13", LIEF::assembly::riscv::SYSREG::mhpmevent13) + .value("mhpmevent14", LIEF::assembly::riscv::SYSREG::mhpmevent14) + .value("mhpmevent15", LIEF::assembly::riscv::SYSREG::mhpmevent15) + .value("mhpmevent16", LIEF::assembly::riscv::SYSREG::mhpmevent16) + .value("mhpmevent17", LIEF::assembly::riscv::SYSREG::mhpmevent17) + .value("mhpmevent18", LIEF::assembly::riscv::SYSREG::mhpmevent18) + .value("mhpmevent19", LIEF::assembly::riscv::SYSREG::mhpmevent19) + .value("mhpmevent20", LIEF::assembly::riscv::SYSREG::mhpmevent20) + .value("mhpmevent21", LIEF::assembly::riscv::SYSREG::mhpmevent21) + .value("mhpmevent22", LIEF::assembly::riscv::SYSREG::mhpmevent22) + .value("mhpmevent23", LIEF::assembly::riscv::SYSREG::mhpmevent23) + .value("mhpmevent24", LIEF::assembly::riscv::SYSREG::mhpmevent24) + .value("mhpmevent25", LIEF::assembly::riscv::SYSREG::mhpmevent25) + .value("mhpmevent26", LIEF::assembly::riscv::SYSREG::mhpmevent26) + .value("mhpmevent27", LIEF::assembly::riscv::SYSREG::mhpmevent27) + .value("mhpmevent28", LIEF::assembly::riscv::SYSREG::mhpmevent28) + .value("mhpmevent29", LIEF::assembly::riscv::SYSREG::mhpmevent29) + .value("mhpmevent30", LIEF::assembly::riscv::SYSREG::mhpmevent30) + .value("mhpmevent31", LIEF::assembly::riscv::SYSREG::mhpmevent31) + .value("mscratch", LIEF::assembly::riscv::SYSREG::mscratch) + .value("mepc", LIEF::assembly::riscv::SYSREG::mepc) + .value("mcause", LIEF::assembly::riscv::SYSREG::mcause) + .value("mbadaddr", LIEF::assembly::riscv::SYSREG::mbadaddr) + .value("mip", LIEF::assembly::riscv::SYSREG::mip) + .value("sf_mnxti", LIEF::assembly::riscv::SYSREG::sf_mnxti) + .value("sf_mintstatus", LIEF::assembly::riscv::SYSREG::sf_mintstatus) + .value("sf_mscratchcsw", LIEF::assembly::riscv::SYSREG::sf_mscratchcsw) + .value("sf_mscratchcswl", LIEF::assembly::riscv::SYSREG::sf_mscratchcswl) + .value("mtinst", LIEF::assembly::riscv::SYSREG::mtinst) + .value("mtval2", LIEF::assembly::riscv::SYSREG::mtval2) + .value("mctrctl", LIEF::assembly::riscv::SYSREG::mctrctl) + .value("miselect", LIEF::assembly::riscv::SYSREG::miselect) + .value("mireg", LIEF::assembly::riscv::SYSREG::mireg) + .value("mireg2", LIEF::assembly::riscv::SYSREG::mireg2) + .value("mireg3", LIEF::assembly::riscv::SYSREG::mireg3) + .value("miph", LIEF::assembly::riscv::SYSREG::miph) + .value("mireg4", LIEF::assembly::riscv::SYSREG::mireg4) + .value("mireg5", LIEF::assembly::riscv::SYSREG::mireg5) + .value("mireg6", LIEF::assembly::riscv::SYSREG::mireg6) + .value("mtopei", LIEF::assembly::riscv::SYSREG::mtopei) + .value("pmpcfg0", LIEF::assembly::riscv::SYSREG::pmpcfg0) + .value("pmpcfg1", LIEF::assembly::riscv::SYSREG::pmpcfg1) + .value("pmpcfg2", LIEF::assembly::riscv::SYSREG::pmpcfg2) + .value("pmpcfg3", LIEF::assembly::riscv::SYSREG::pmpcfg3) + .value("pmpcfg4", LIEF::assembly::riscv::SYSREG::pmpcfg4) + .value("pmpcfg5", LIEF::assembly::riscv::SYSREG::pmpcfg5) + .value("pmpcfg6", LIEF::assembly::riscv::SYSREG::pmpcfg6) + .value("pmpcfg7", LIEF::assembly::riscv::SYSREG::pmpcfg7) + .value("pmpcfg8", LIEF::assembly::riscv::SYSREG::pmpcfg8) + .value("pmpcfg9", LIEF::assembly::riscv::SYSREG::pmpcfg9) + .value("pmpcfg10", LIEF::assembly::riscv::SYSREG::pmpcfg10) + .value("pmpcfg11", LIEF::assembly::riscv::SYSREG::pmpcfg11) + .value("pmpcfg12", LIEF::assembly::riscv::SYSREG::pmpcfg12) + .value("pmpcfg13", LIEF::assembly::riscv::SYSREG::pmpcfg13) + .value("pmpcfg14", LIEF::assembly::riscv::SYSREG::pmpcfg14) + .value("pmpcfg15", LIEF::assembly::riscv::SYSREG::pmpcfg15) + .value("pmpaddr0", LIEF::assembly::riscv::SYSREG::pmpaddr0) + .value("pmpaddr1", LIEF::assembly::riscv::SYSREG::pmpaddr1) + .value("pmpaddr2", LIEF::assembly::riscv::SYSREG::pmpaddr2) + .value("pmpaddr3", LIEF::assembly::riscv::SYSREG::pmpaddr3) + .value("pmpaddr4", LIEF::assembly::riscv::SYSREG::pmpaddr4) + .value("pmpaddr5", LIEF::assembly::riscv::SYSREG::pmpaddr5) + .value("pmpaddr6", LIEF::assembly::riscv::SYSREG::pmpaddr6) + .value("pmpaddr7", LIEF::assembly::riscv::SYSREG::pmpaddr7) + .value("pmpaddr8", LIEF::assembly::riscv::SYSREG::pmpaddr8) + .value("pmpaddr9", LIEF::assembly::riscv::SYSREG::pmpaddr9) + .value("pmpaddr10", LIEF::assembly::riscv::SYSREG::pmpaddr10) + .value("pmpaddr11", LIEF::assembly::riscv::SYSREG::pmpaddr11) + .value("pmpaddr12", LIEF::assembly::riscv::SYSREG::pmpaddr12) + .value("pmpaddr13", LIEF::assembly::riscv::SYSREG::pmpaddr13) + .value("pmpaddr14", LIEF::assembly::riscv::SYSREG::pmpaddr14) + .value("pmpaddr15", LIEF::assembly::riscv::SYSREG::pmpaddr15) + .value("pmpaddr16", LIEF::assembly::riscv::SYSREG::pmpaddr16) + .value("pmpaddr17", LIEF::assembly::riscv::SYSREG::pmpaddr17) + .value("pmpaddr18", LIEF::assembly::riscv::SYSREG::pmpaddr18) + .value("pmpaddr19", LIEF::assembly::riscv::SYSREG::pmpaddr19) + .value("pmpaddr20", LIEF::assembly::riscv::SYSREG::pmpaddr20) + .value("pmpaddr21", LIEF::assembly::riscv::SYSREG::pmpaddr21) + .value("pmpaddr22", LIEF::assembly::riscv::SYSREG::pmpaddr22) + .value("pmpaddr23", LIEF::assembly::riscv::SYSREG::pmpaddr23) + .value("pmpaddr24", LIEF::assembly::riscv::SYSREG::pmpaddr24) + .value("pmpaddr25", LIEF::assembly::riscv::SYSREG::pmpaddr25) + .value("pmpaddr26", LIEF::assembly::riscv::SYSREG::pmpaddr26) + .value("pmpaddr27", LIEF::assembly::riscv::SYSREG::pmpaddr27) + .value("pmpaddr28", LIEF::assembly::riscv::SYSREG::pmpaddr28) + .value("pmpaddr29", LIEF::assembly::riscv::SYSREG::pmpaddr29) + .value("pmpaddr30", LIEF::assembly::riscv::SYSREG::pmpaddr30) + .value("pmpaddr31", LIEF::assembly::riscv::SYSREG::pmpaddr31) + .value("pmpaddr32", LIEF::assembly::riscv::SYSREG::pmpaddr32) + .value("pmpaddr33", LIEF::assembly::riscv::SYSREG::pmpaddr33) + .value("pmpaddr34", LIEF::assembly::riscv::SYSREG::pmpaddr34) + .value("pmpaddr35", LIEF::assembly::riscv::SYSREG::pmpaddr35) + .value("pmpaddr36", LIEF::assembly::riscv::SYSREG::pmpaddr36) + .value("pmpaddr37", LIEF::assembly::riscv::SYSREG::pmpaddr37) + .value("pmpaddr38", LIEF::assembly::riscv::SYSREG::pmpaddr38) + .value("pmpaddr39", LIEF::assembly::riscv::SYSREG::pmpaddr39) + .value("pmpaddr40", LIEF::assembly::riscv::SYSREG::pmpaddr40) + .value("pmpaddr41", LIEF::assembly::riscv::SYSREG::pmpaddr41) + .value("pmpaddr42", LIEF::assembly::riscv::SYSREG::pmpaddr42) + .value("pmpaddr43", LIEF::assembly::riscv::SYSREG::pmpaddr43) + .value("pmpaddr44", LIEF::assembly::riscv::SYSREG::pmpaddr44) + .value("pmpaddr45", LIEF::assembly::riscv::SYSREG::pmpaddr45) + .value("pmpaddr46", LIEF::assembly::riscv::SYSREG::pmpaddr46) + .value("pmpaddr47", LIEF::assembly::riscv::SYSREG::pmpaddr47) + .value("pmpaddr48", LIEF::assembly::riscv::SYSREG::pmpaddr48) + .value("pmpaddr49", LIEF::assembly::riscv::SYSREG::pmpaddr49) + .value("pmpaddr50", LIEF::assembly::riscv::SYSREG::pmpaddr50) + .value("pmpaddr51", LIEF::assembly::riscv::SYSREG::pmpaddr51) + .value("pmpaddr52", LIEF::assembly::riscv::SYSREG::pmpaddr52) + .value("pmpaddr53", LIEF::assembly::riscv::SYSREG::pmpaddr53) + .value("pmpaddr54", LIEF::assembly::riscv::SYSREG::pmpaddr54) + .value("pmpaddr55", LIEF::assembly::riscv::SYSREG::pmpaddr55) + .value("pmpaddr56", LIEF::assembly::riscv::SYSREG::pmpaddr56) + .value("pmpaddr57", LIEF::assembly::riscv::SYSREG::pmpaddr57) + .value("pmpaddr58", LIEF::assembly::riscv::SYSREG::pmpaddr58) + .value("pmpaddr59", LIEF::assembly::riscv::SYSREG::pmpaddr59) + .value("pmpaddr60", LIEF::assembly::riscv::SYSREG::pmpaddr60) + .value("pmpaddr61", LIEF::assembly::riscv::SYSREG::pmpaddr61) + .value("pmpaddr62", LIEF::assembly::riscv::SYSREG::pmpaddr62) + .value("pmpaddr63", LIEF::assembly::riscv::SYSREG::pmpaddr63) + .value("scontext", LIEF::assembly::riscv::SYSREG::scontext) + .value("hstatus", LIEF::assembly::riscv::SYSREG::hstatus) + .value("hedeleg", LIEF::assembly::riscv::SYSREG::hedeleg) + .value("hideleg", LIEF::assembly::riscv::SYSREG::hideleg) + .value("hie", LIEF::assembly::riscv::SYSREG::hie) + .value("htimedelta", LIEF::assembly::riscv::SYSREG::htimedelta) + .value("hcounteren", LIEF::assembly::riscv::SYSREG::hcounteren) + .value("hgeie", LIEF::assembly::riscv::SYSREG::hgeie) + .value("hvien", LIEF::assembly::riscv::SYSREG::hvien) + .value("hvictl", LIEF::assembly::riscv::SYSREG::hvictl) + .value("henvcfg", LIEF::assembly::riscv::SYSREG::henvcfg) + .value("hstateen0", LIEF::assembly::riscv::SYSREG::hstateen0) + .value("hstateen1", LIEF::assembly::riscv::SYSREG::hstateen1) + .value("hstateen2", LIEF::assembly::riscv::SYSREG::hstateen2) + .value("hstateen3", LIEF::assembly::riscv::SYSREG::hstateen3) + .value("hedelegh", LIEF::assembly::riscv::SYSREG::hedelegh) + .value("hidelegh", LIEF::assembly::riscv::SYSREG::hidelegh) + .value("htimedeltah", LIEF::assembly::riscv::SYSREG::htimedeltah) + .value("hvienh", LIEF::assembly::riscv::SYSREG::hvienh) + .value("henvcfgh", LIEF::assembly::riscv::SYSREG::henvcfgh) + .value("hstateen0h", LIEF::assembly::riscv::SYSREG::hstateen0h) + .value("hstateen1h", LIEF::assembly::riscv::SYSREG::hstateen1h) + .value("hstateen2h", LIEF::assembly::riscv::SYSREG::hstateen2h) + .value("hstateen3h", LIEF::assembly::riscv::SYSREG::hstateen3h) + .value("htval", LIEF::assembly::riscv::SYSREG::htval) + .value("hip", LIEF::assembly::riscv::SYSREG::hip) + .value("hvip", LIEF::assembly::riscv::SYSREG::hvip) + .value("hviprio1", LIEF::assembly::riscv::SYSREG::hviprio1) + .value("hviprio2", LIEF::assembly::riscv::SYSREG::hviprio2) + .value("htinst", LIEF::assembly::riscv::SYSREG::htinst) + .value("hviph", LIEF::assembly::riscv::SYSREG::hviph) + .value("hviprio1h", LIEF::assembly::riscv::SYSREG::hviprio1h) + .value("hviprio2h", LIEF::assembly::riscv::SYSREG::hviprio2h) + .value("hgatp", LIEF::assembly::riscv::SYSREG::hgatp) + .value("hcontext", LIEF::assembly::riscv::SYSREG::hcontext) + .value("mcyclecfgh", LIEF::assembly::riscv::SYSREG::mcyclecfgh) + .value("minstretcfgh", LIEF::assembly::riscv::SYSREG::minstretcfgh) + .value("mhpmevent3h", LIEF::assembly::riscv::SYSREG::mhpmevent3h) + .value("mhpmevent4h", LIEF::assembly::riscv::SYSREG::mhpmevent4h) + .value("mhpmevent5h", LIEF::assembly::riscv::SYSREG::mhpmevent5h) + .value("mhpmevent6h", LIEF::assembly::riscv::SYSREG::mhpmevent6h) + .value("mhpmevent7h", LIEF::assembly::riscv::SYSREG::mhpmevent7h) + .value("mhpmevent8h", LIEF::assembly::riscv::SYSREG::mhpmevent8h) + .value("mhpmevent9h", LIEF::assembly::riscv::SYSREG::mhpmevent9h) + .value("mhpmevent10h", LIEF::assembly::riscv::SYSREG::mhpmevent10h) + .value("mhpmevent11h", LIEF::assembly::riscv::SYSREG::mhpmevent11h) + .value("mhpmevent12h", LIEF::assembly::riscv::SYSREG::mhpmevent12h) + .value("mhpmevent13h", LIEF::assembly::riscv::SYSREG::mhpmevent13h) + .value("mhpmevent14h", LIEF::assembly::riscv::SYSREG::mhpmevent14h) + .value("mhpmevent15h", LIEF::assembly::riscv::SYSREG::mhpmevent15h) + .value("mhpmevent16h", LIEF::assembly::riscv::SYSREG::mhpmevent16h) + .value("mhpmevent17h", LIEF::assembly::riscv::SYSREG::mhpmevent17h) + .value("mhpmevent18h", LIEF::assembly::riscv::SYSREG::mhpmevent18h) + .value("mhpmevent19h", LIEF::assembly::riscv::SYSREG::mhpmevent19h) + .value("mhpmevent20h", LIEF::assembly::riscv::SYSREG::mhpmevent20h) + .value("mhpmevent21h", LIEF::assembly::riscv::SYSREG::mhpmevent21h) + .value("mhpmevent22h", LIEF::assembly::riscv::SYSREG::mhpmevent22h) + .value("mhpmevent23h", LIEF::assembly::riscv::SYSREG::mhpmevent23h) + .value("mhpmevent24h", LIEF::assembly::riscv::SYSREG::mhpmevent24h) + .value("mhpmevent25h", LIEF::assembly::riscv::SYSREG::mhpmevent25h) + .value("mhpmevent26h", LIEF::assembly::riscv::SYSREG::mhpmevent26h) + .value("mhpmevent27h", LIEF::assembly::riscv::SYSREG::mhpmevent27h) + .value("mhpmevent28h", LIEF::assembly::riscv::SYSREG::mhpmevent28h) + .value("mhpmevent29h", LIEF::assembly::riscv::SYSREG::mhpmevent29h) + .value("mhpmevent30h", LIEF::assembly::riscv::SYSREG::mhpmevent30h) + .value("mhpmevent31h", LIEF::assembly::riscv::SYSREG::mhpmevent31h) + .value("mnscratch", LIEF::assembly::riscv::SYSREG::mnscratch) + .value("mnepc", LIEF::assembly::riscv::SYSREG::mnepc) + .value("mncause", LIEF::assembly::riscv::SYSREG::mncause) + .value("mnstatus", LIEF::assembly::riscv::SYSREG::mnstatus) + .value("mseccfg", LIEF::assembly::riscv::SYSREG::mseccfg) + .value("mseccfgh", LIEF::assembly::riscv::SYSREG::mseccfgh); + reg.value("tselect", LIEF::assembly::riscv::SYSREG::tselect) + .value("etrigger", LIEF::assembly::riscv::SYSREG::etrigger) + .value("tdata2", LIEF::assembly::riscv::SYSREG::tdata2) + .value("tdata3", LIEF::assembly::riscv::SYSREG::tdata3) + .value("tinfo", LIEF::assembly::riscv::SYSREG::tinfo) + .value("tcontrol", LIEF::assembly::riscv::SYSREG::tcontrol) + .value("mcontext", LIEF::assembly::riscv::SYSREG::mcontext) + .value("mscontext", LIEF::assembly::riscv::SYSREG::mscontext) + .value("dcsr", LIEF::assembly::riscv::SYSREG::dcsr) + .value("dpc", LIEF::assembly::riscv::SYSREG::dpc) + .value("dscratch", LIEF::assembly::riscv::SYSREG::dscratch) + .value("dscratch1", LIEF::assembly::riscv::SYSREG::dscratch1) + .value("qc_mmcr", LIEF::assembly::riscv::SYSREG::qc_mmcr) + .value("qc_mntvec", LIEF::assembly::riscv::SYSREG::qc_mntvec) + .value("qc_mstktopaddr", LIEF::assembly::riscv::SYSREG::qc_mstktopaddr) + .value("qc_mstkbottomaddr", LIEF::assembly::riscv::SYSREG::qc_mstkbottomaddr) + .value("qc_mthreadptr", LIEF::assembly::riscv::SYSREG::qc_mthreadptr) + .value("qc_mcause", LIEF::assembly::riscv::SYSREG::qc_mcause) + .value("qc_mwpstartaddr0", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr0) + .value("qc_mwpstartaddr1", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr1) + .value("qc_mwpstartaddr2", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr2) + .value("qc_mwpstartaddr3", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr3) + .value("qc_mwpendaddr0", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr0) + .value("qc_mwpendaddr1", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr1) + .value("qc_mwpendaddr2", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr2) + .value("qc_mwpendaddr3", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr3) + .value("qc_mclicip0", LIEF::assembly::riscv::SYSREG::qc_mclicip0) + .value("qc_mclicip1", LIEF::assembly::riscv::SYSREG::qc_mclicip1) + .value("qc_mclicip2", LIEF::assembly::riscv::SYSREG::qc_mclicip2) + .value("qc_mclicip3", LIEF::assembly::riscv::SYSREG::qc_mclicip3) + .value("qc_mclicip4", LIEF::assembly::riscv::SYSREG::qc_mclicip4) + .value("qc_mclicip5", LIEF::assembly::riscv::SYSREG::qc_mclicip5) + .value("qc_mclicip6", LIEF::assembly::riscv::SYSREG::qc_mclicip6) + .value("qc_mclicip7", LIEF::assembly::riscv::SYSREG::qc_mclicip7) + .value("qc_mclicie0", LIEF::assembly::riscv::SYSREG::qc_mclicie0) + .value("qc_mclicie1", LIEF::assembly::riscv::SYSREG::qc_mclicie1) + .value("qc_mclicie2", LIEF::assembly::riscv::SYSREG::qc_mclicie2) + .value("qc_mclicie3", LIEF::assembly::riscv::SYSREG::qc_mclicie3) + .value("qc_mclicie4", LIEF::assembly::riscv::SYSREG::qc_mclicie4) + .value("qc_mclicie5", LIEF::assembly::riscv::SYSREG::qc_mclicie5) + .value("qc_mclicie6", LIEF::assembly::riscv::SYSREG::qc_mclicie6) + .value("qc_mclicie7", LIEF::assembly::riscv::SYSREG::qc_mclicie7) + .value("mcycle", LIEF::assembly::riscv::SYSREG::mcycle) + .value("minstret", LIEF::assembly::riscv::SYSREG::minstret) + .value("mhpmcounter3", LIEF::assembly::riscv::SYSREG::mhpmcounter3) + .value("mhpmcounter4", LIEF::assembly::riscv::SYSREG::mhpmcounter4) + .value("mhpmcounter5", LIEF::assembly::riscv::SYSREG::mhpmcounter5) + .value("mhpmcounter6", LIEF::assembly::riscv::SYSREG::mhpmcounter6) + .value("mhpmcounter7", LIEF::assembly::riscv::SYSREG::mhpmcounter7) + .value("mhpmcounter8", LIEF::assembly::riscv::SYSREG::mhpmcounter8) + .value("mhpmcounter9", LIEF::assembly::riscv::SYSREG::mhpmcounter9) + .value("mhpmcounter10", LIEF::assembly::riscv::SYSREG::mhpmcounter10) + .value("mhpmcounter11", LIEF::assembly::riscv::SYSREG::mhpmcounter11) + .value("mhpmcounter12", LIEF::assembly::riscv::SYSREG::mhpmcounter12) + .value("mhpmcounter13", LIEF::assembly::riscv::SYSREG::mhpmcounter13) + .value("mhpmcounter14", LIEF::assembly::riscv::SYSREG::mhpmcounter14) + .value("mhpmcounter15", LIEF::assembly::riscv::SYSREG::mhpmcounter15) + .value("mhpmcounter16", LIEF::assembly::riscv::SYSREG::mhpmcounter16) + .value("mhpmcounter17", LIEF::assembly::riscv::SYSREG::mhpmcounter17) + .value("mhpmcounter18", LIEF::assembly::riscv::SYSREG::mhpmcounter18) + .value("mhpmcounter19", LIEF::assembly::riscv::SYSREG::mhpmcounter19) + .value("mhpmcounter20", LIEF::assembly::riscv::SYSREG::mhpmcounter20) + .value("mhpmcounter21", LIEF::assembly::riscv::SYSREG::mhpmcounter21) + .value("mhpmcounter22", LIEF::assembly::riscv::SYSREG::mhpmcounter22) + .value("mhpmcounter23", LIEF::assembly::riscv::SYSREG::mhpmcounter23) + .value("mhpmcounter24", LIEF::assembly::riscv::SYSREG::mhpmcounter24) + .value("mhpmcounter25", LIEF::assembly::riscv::SYSREG::mhpmcounter25) + .value("mhpmcounter26", LIEF::assembly::riscv::SYSREG::mhpmcounter26) + .value("mhpmcounter27", LIEF::assembly::riscv::SYSREG::mhpmcounter27) + .value("mhpmcounter28", LIEF::assembly::riscv::SYSREG::mhpmcounter28) + .value("mhpmcounter29", LIEF::assembly::riscv::SYSREG::mhpmcounter29) + .value("mhpmcounter30", LIEF::assembly::riscv::SYSREG::mhpmcounter30) + .value("mhpmcounter31", LIEF::assembly::riscv::SYSREG::mhpmcounter31) + .value("mcycleh", LIEF::assembly::riscv::SYSREG::mcycleh) + .value("minstreth", LIEF::assembly::riscv::SYSREG::minstreth) + .value("mhpmcounter3h", LIEF::assembly::riscv::SYSREG::mhpmcounter3h) + .value("mhpmcounter4h", LIEF::assembly::riscv::SYSREG::mhpmcounter4h) + .value("mhpmcounter5h", LIEF::assembly::riscv::SYSREG::mhpmcounter5h) + .value("mhpmcounter6h", LIEF::assembly::riscv::SYSREG::mhpmcounter6h) + .value("mhpmcounter7h", LIEF::assembly::riscv::SYSREG::mhpmcounter7h) + .value("mhpmcounter8h", LIEF::assembly::riscv::SYSREG::mhpmcounter8h) + .value("mhpmcounter9h", LIEF::assembly::riscv::SYSREG::mhpmcounter9h) + .value("mhpmcounter10h", LIEF::assembly::riscv::SYSREG::mhpmcounter10h) + .value("mhpmcounter11h", LIEF::assembly::riscv::SYSREG::mhpmcounter11h) + .value("mhpmcounter12h", LIEF::assembly::riscv::SYSREG::mhpmcounter12h) + .value("mhpmcounter13h", LIEF::assembly::riscv::SYSREG::mhpmcounter13h) + .value("mhpmcounter14h", LIEF::assembly::riscv::SYSREG::mhpmcounter14h) + .value("mhpmcounter15h", LIEF::assembly::riscv::SYSREG::mhpmcounter15h) + .value("mhpmcounter16h", LIEF::assembly::riscv::SYSREG::mhpmcounter16h) + .value("mhpmcounter17h", LIEF::assembly::riscv::SYSREG::mhpmcounter17h) + .value("mhpmcounter18h", LIEF::assembly::riscv::SYSREG::mhpmcounter18h) + .value("mhpmcounter19h", LIEF::assembly::riscv::SYSREG::mhpmcounter19h) + .value("mhpmcounter20h", LIEF::assembly::riscv::SYSREG::mhpmcounter20h) + .value("mhpmcounter21h", LIEF::assembly::riscv::SYSREG::mhpmcounter21h) + .value("mhpmcounter22h", LIEF::assembly::riscv::SYSREG::mhpmcounter22h) + .value("mhpmcounter23h", LIEF::assembly::riscv::SYSREG::mhpmcounter23h) + .value("mhpmcounter24h", LIEF::assembly::riscv::SYSREG::mhpmcounter24h) + .value("mhpmcounter25h", LIEF::assembly::riscv::SYSREG::mhpmcounter25h) + .value("mhpmcounter26h", LIEF::assembly::riscv::SYSREG::mhpmcounter26h) + .value("mhpmcounter27h", LIEF::assembly::riscv::SYSREG::mhpmcounter27h) + .value("mhpmcounter28h", LIEF::assembly::riscv::SYSREG::mhpmcounter28h) + .value("mhpmcounter29h", LIEF::assembly::riscv::SYSREG::mhpmcounter29h) + .value("mhpmcounter30h", LIEF::assembly::riscv::SYSREG::mhpmcounter30h) + .value("mhpmcounter31h", LIEF::assembly::riscv::SYSREG::mhpmcounter31h) + .value("qc_mclicilvl00", LIEF::assembly::riscv::SYSREG::qc_mclicilvl00) + .value("qc_mclicilvl01", LIEF::assembly::riscv::SYSREG::qc_mclicilvl01) + .value("qc_mclicilvl02", LIEF::assembly::riscv::SYSREG::qc_mclicilvl02) + .value("qc_mclicilvl03", LIEF::assembly::riscv::SYSREG::qc_mclicilvl03) + .value("qc_mclicilvl04", LIEF::assembly::riscv::SYSREG::qc_mclicilvl04) + .value("qc_mclicilvl05", LIEF::assembly::riscv::SYSREG::qc_mclicilvl05) + .value("qc_mclicilvl06", LIEF::assembly::riscv::SYSREG::qc_mclicilvl06) + .value("qc_mclicilvl07", LIEF::assembly::riscv::SYSREG::qc_mclicilvl07) + .value("qc_mclicilvl08", LIEF::assembly::riscv::SYSREG::qc_mclicilvl08) + .value("qc_mclicilvl09", LIEF::assembly::riscv::SYSREG::qc_mclicilvl09) + .value("qc_mclicilvl10", LIEF::assembly::riscv::SYSREG::qc_mclicilvl10) + .value("qc_mclicilvl11", LIEF::assembly::riscv::SYSREG::qc_mclicilvl11) + .value("qc_mclicilvl12", LIEF::assembly::riscv::SYSREG::qc_mclicilvl12) + .value("qc_mclicilvl13", LIEF::assembly::riscv::SYSREG::qc_mclicilvl13) + .value("qc_mclicilvl14", LIEF::assembly::riscv::SYSREG::qc_mclicilvl14) + .value("qc_mclicilvl15", LIEF::assembly::riscv::SYSREG::qc_mclicilvl15) + .value("qc_mclicilvl16", LIEF::assembly::riscv::SYSREG::qc_mclicilvl16) + .value("qc_mclicilvl17", LIEF::assembly::riscv::SYSREG::qc_mclicilvl17) + .value("qc_mclicilvl18", LIEF::assembly::riscv::SYSREG::qc_mclicilvl18) + .value("qc_mclicilvl19", LIEF::assembly::riscv::SYSREG::qc_mclicilvl19) + .value("qc_mclicilvl20", LIEF::assembly::riscv::SYSREG::qc_mclicilvl20) + .value("qc_mclicilvl21", LIEF::assembly::riscv::SYSREG::qc_mclicilvl21) + .value("qc_mclicilvl22", LIEF::assembly::riscv::SYSREG::qc_mclicilvl22) + .value("qc_mclicilvl23", LIEF::assembly::riscv::SYSREG::qc_mclicilvl23) + .value("qc_mclicilvl24", LIEF::assembly::riscv::SYSREG::qc_mclicilvl24) + .value("qc_mclicilvl25", LIEF::assembly::riscv::SYSREG::qc_mclicilvl25) + .value("qc_mclicilvl26", LIEF::assembly::riscv::SYSREG::qc_mclicilvl26) + .value("qc_mclicilvl27", LIEF::assembly::riscv::SYSREG::qc_mclicilvl27) + .value("qc_mclicilvl28", LIEF::assembly::riscv::SYSREG::qc_mclicilvl28) + .value("qc_mclicilvl29", LIEF::assembly::riscv::SYSREG::qc_mclicilvl29) + .value("qc_mclicilvl30", LIEF::assembly::riscv::SYSREG::qc_mclicilvl30) + .value("qc_mclicilvl31", LIEF::assembly::riscv::SYSREG::qc_mclicilvl31) + .value("cycle", LIEF::assembly::riscv::SYSREG::cycle) + .value("time", LIEF::assembly::riscv::SYSREG::time) + .value("instret", LIEF::assembly::riscv::SYSREG::instret) + .value("hpmcounter3", LIEF::assembly::riscv::SYSREG::hpmcounter3) + .value("hpmcounter4", LIEF::assembly::riscv::SYSREG::hpmcounter4) + .value("hpmcounter5", LIEF::assembly::riscv::SYSREG::hpmcounter5) + .value("hpmcounter6", LIEF::assembly::riscv::SYSREG::hpmcounter6) + .value("hpmcounter7", LIEF::assembly::riscv::SYSREG::hpmcounter7) + .value("hpmcounter8", LIEF::assembly::riscv::SYSREG::hpmcounter8) + .value("hpmcounter9", LIEF::assembly::riscv::SYSREG::hpmcounter9) + .value("hpmcounter10", LIEF::assembly::riscv::SYSREG::hpmcounter10) + .value("hpmcounter11", LIEF::assembly::riscv::SYSREG::hpmcounter11) + .value("hpmcounter12", LIEF::assembly::riscv::SYSREG::hpmcounter12) + .value("hpmcounter13", LIEF::assembly::riscv::SYSREG::hpmcounter13) + .value("hpmcounter14", LIEF::assembly::riscv::SYSREG::hpmcounter14) + .value("hpmcounter15", LIEF::assembly::riscv::SYSREG::hpmcounter15) + .value("hpmcounter16", LIEF::assembly::riscv::SYSREG::hpmcounter16) + .value("hpmcounter17", LIEF::assembly::riscv::SYSREG::hpmcounter17) + .value("hpmcounter18", LIEF::assembly::riscv::SYSREG::hpmcounter18) + .value("hpmcounter19", LIEF::assembly::riscv::SYSREG::hpmcounter19) + .value("hpmcounter20", LIEF::assembly::riscv::SYSREG::hpmcounter20) + .value("hpmcounter21", LIEF::assembly::riscv::SYSREG::hpmcounter21) + .value("hpmcounter22", LIEF::assembly::riscv::SYSREG::hpmcounter22) + .value("hpmcounter23", LIEF::assembly::riscv::SYSREG::hpmcounter23) + .value("hpmcounter24", LIEF::assembly::riscv::SYSREG::hpmcounter24) + .value("hpmcounter25", LIEF::assembly::riscv::SYSREG::hpmcounter25) + .value("hpmcounter26", LIEF::assembly::riscv::SYSREG::hpmcounter26) + .value("hpmcounter27", LIEF::assembly::riscv::SYSREG::hpmcounter27) + .value("hpmcounter28", LIEF::assembly::riscv::SYSREG::hpmcounter28) + .value("hpmcounter29", LIEF::assembly::riscv::SYSREG::hpmcounter29) + .value("hpmcounter30", LIEF::assembly::riscv::SYSREG::hpmcounter30) + .value("hpmcounter31", LIEF::assembly::riscv::SYSREG::hpmcounter31) + .value("vl", LIEF::assembly::riscv::SYSREG::vl) + .value("vtype", LIEF::assembly::riscv::SYSREG::vtype) + .value("vlenb", LIEF::assembly::riscv::SYSREG::vlenb) + .value("cycleh", LIEF::assembly::riscv::SYSREG::cycleh) + .value("timeh", LIEF::assembly::riscv::SYSREG::timeh) + .value("instreth", LIEF::assembly::riscv::SYSREG::instreth) + .value("hpmcounter3h", LIEF::assembly::riscv::SYSREG::hpmcounter3h) + .value("hpmcounter4h", LIEF::assembly::riscv::SYSREG::hpmcounter4h) + .value("hpmcounter5h", LIEF::assembly::riscv::SYSREG::hpmcounter5h) + .value("hpmcounter6h", LIEF::assembly::riscv::SYSREG::hpmcounter6h) + .value("hpmcounter7h", LIEF::assembly::riscv::SYSREG::hpmcounter7h) + .value("hpmcounter8h", LIEF::assembly::riscv::SYSREG::hpmcounter8h) + .value("hpmcounter9h", LIEF::assembly::riscv::SYSREG::hpmcounter9h) + .value("hpmcounter10h", LIEF::assembly::riscv::SYSREG::hpmcounter10h) + .value("hpmcounter11h", LIEF::assembly::riscv::SYSREG::hpmcounter11h) + .value("hpmcounter12h", LIEF::assembly::riscv::SYSREG::hpmcounter12h) + .value("hpmcounter13h", LIEF::assembly::riscv::SYSREG::hpmcounter13h) + .value("hpmcounter14h", LIEF::assembly::riscv::SYSREG::hpmcounter14h) + .value("hpmcounter15h", LIEF::assembly::riscv::SYSREG::hpmcounter15h) + .value("hpmcounter16h", LIEF::assembly::riscv::SYSREG::hpmcounter16h) + .value("hpmcounter17h", LIEF::assembly::riscv::SYSREG::hpmcounter17h) + .value("hpmcounter18h", LIEF::assembly::riscv::SYSREG::hpmcounter18h) + .value("hpmcounter19h", LIEF::assembly::riscv::SYSREG::hpmcounter19h) + .value("hpmcounter20h", LIEF::assembly::riscv::SYSREG::hpmcounter20h) + .value("hpmcounter21h", LIEF::assembly::riscv::SYSREG::hpmcounter21h) + .value("hpmcounter22h", LIEF::assembly::riscv::SYSREG::hpmcounter22h) + .value("hpmcounter23h", LIEF::assembly::riscv::SYSREG::hpmcounter23h) + .value("hpmcounter24h", LIEF::assembly::riscv::SYSREG::hpmcounter24h) + .value("hpmcounter25h", LIEF::assembly::riscv::SYSREG::hpmcounter25h) + .value("hpmcounter26h", LIEF::assembly::riscv::SYSREG::hpmcounter26h) + .value("hpmcounter27h", LIEF::assembly::riscv::SYSREG::hpmcounter27h) + .value("hpmcounter28h", LIEF::assembly::riscv::SYSREG::hpmcounter28h) + .value("hpmcounter29h", LIEF::assembly::riscv::SYSREG::hpmcounter29h) + .value("hpmcounter30h", LIEF::assembly::riscv::SYSREG::hpmcounter30h) + .value("hpmcounter31h", LIEF::assembly::riscv::SYSREG::hpmcounter31h) + .value("scountovf", LIEF::assembly::riscv::SYSREG::scountovf) + .value("stopi", LIEF::assembly::riscv::SYSREG::stopi) + .value("hgeip", LIEF::assembly::riscv::SYSREG::hgeip) + .value("vstopi", LIEF::assembly::riscv::SYSREG::vstopi) + .value("mvendorid", LIEF::assembly::riscv::SYSREG::mvendorid) + .value("marchid", LIEF::assembly::riscv::SYSREG::marchid) + .value("mimpid", LIEF::assembly::riscv::SYSREG::mimpid) + .value("mhartid", LIEF::assembly::riscv::SYSREG::mhartid) + .value("mconfigptr", LIEF::assembly::riscv::SYSREG::mconfigptr) + .value("mtopi", LIEF::assembly::riscv::SYSREG::mtopi) + .value("NUM_TARGET_SYSREGS", LIEF::assembly::riscv::SYSREG::NUM_TARGET_SYSREGS) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/CMakeLists.txt b/vendor/lief/api/python/src/asm/x86/CMakeLists.txt new file mode 100644 index 0000000..fa287c6 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyInstruction.cpp + pyOpcode.cpp + pyRegister.cpp + pyOperand.cpp +) + +add_subdirectory(operands) diff --git a/vendor/lief/api/python/src/asm/x86/init.cpp b/vendor/lief/api/python/src/asm/x86/init.cpp new file mode 100644 index 0000000..5c007eb --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/init.cpp @@ -0,0 +1,18 @@ +#include "asm/x86/init.hpp" +namespace LIEF::assembly::x86 { +enum class OPCODE; +enum class REG; +class Instruction; +class Operand; +} + +namespace LIEF::assembly::x86::py { +void init(nb::module_& m) { + nb::module_ mod = m.def_submodule("x86"); + + create(mod); + create(mod); + create(mod); + create(mod); +} +} diff --git a/vendor/lief/api/python/src/asm/x86/init.hpp b/vendor/lief/api/python/src/asm/x86/init.hpp new file mode 100644 index 0000000..915ff30 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/init.hpp @@ -0,0 +1,12 @@ +#ifndef PY_LIEF_ASM_X86_INIT_H +#define PY_LIEF_ASM_X86_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::assembly::x86::py { +void init(nb::module_& m); + +template +void create(nb::module_&); + +} +#endif diff --git a/vendor/lief/api/python/src/asm/x86/operands/CMakeLists.txt b/vendor/lief/api/python/src/asm/x86/operands/CMakeLists.txt new file mode 100644 index 0000000..d7bf965 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/operands/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + pyImmediate.cpp + pyRegister.cpp + pyMemory.cpp + pyPCRelative.cpp +) diff --git a/vendor/lief/api/python/src/asm/x86/operands/pyImmediate.cpp b/vendor/lief/api/python/src/asm/x86/operands/pyImmediate.cpp new file mode 100644 index 0000000..2164f79 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/operands/pyImmediate.cpp @@ -0,0 +1,29 @@ +#include "asm/x86/init.hpp" +#include "LIEF/asm/x86/operands/Immediate.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Immediate", + R"doc( + This class represents an immediate operand (i.e. a constant) + + For instance: + + .. code-block:: text + + mov edi, 1; + | + +---> Immediate(1) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &operands::Immediate::value, + R"doc(The constant value wrapped by this operand)doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/operands/pyMemory.cpp b/vendor/lief/api/python/src/asm/x86/operands/pyMemory.cpp new file mode 100644 index 0000000..0e56578 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/operands/pyMemory.cpp @@ -0,0 +1,71 @@ +#include "asm/x86/init.hpp" +#include "LIEF/asm/x86/operands/Memory.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class represents a memory operand. + + For instance: + + .. code-block:: text + + movq xmm3, qword ptr [rip + 823864]; + + | + | + Memory + | + +-----------+-----------+ + | | | + Base: rip Scale: 1 Displacement: 823864 + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("base", "scaled_register", "segment_register", "scale", "displacement"); + + obj + .def_prop_ro("base", &x86::operands::Memory::base, + R"doc( + The base register. + + For ``lea rdx, [rip + 244634]`` it would return ``rip`` + )doc"_doc + ) + + .def_prop_ro("scaled_register", &x86::operands::Memory::scaled_register, + R"doc( + The scaled register. + + For ``mov rdi, qword ptr [r13 + 8*r14]`` it would return ``r14`` + )doc"_doc + ) + + .def_prop_ro("segment_register", &x86::operands::Memory::segment_register, + R"doc( + The segment register associated with the memory operation. + + For ``mov eax, dword ptr gs:[0]`` it would return ``gs`` + )doc"_doc + ) + + .def_prop_ro("scale", &x86::operands::Memory::scale, + R"doc( + The scale value associated with the :attr:`~.scaled_register`: + + For ``mov rdi, qword ptr [r13 + 8*r14]`` it would return ``8`` + )doc"_doc + ) + + .def_prop_ro("displacement", &x86::operands::Memory::displacement, + R"doc( + The displacement value. + + For ``call qword ptr [rip + 248779]`` it would return ``248779`` + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/operands/pyPCRelative.cpp b/vendor/lief/api/python/src/asm/x86/operands/pyPCRelative.cpp new file mode 100644 index 0000000..fcb3427 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/operands/pyPCRelative.cpp @@ -0,0 +1,31 @@ +#include "asm/x86/init.hpp" +#include "LIEF/asm/x86/operands/PCRelative.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "PCRelative", + R"doc( + This class represents a RIP/EIP-relative operand. + + For instance: + + .. code-block:: text + + jmp 67633; + | + +----------> PCRelative(67633) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &x86::operands::PCRelative::value, + R"doc( + The effective value that is relative to the current ``rip/eip`` register + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/operands/pyRegister.cpp b/vendor/lief/api/python/src/asm/x86/operands/pyRegister.cpp new file mode 100644 index 0000000..9a68cb1 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/operands/pyRegister.cpp @@ -0,0 +1,33 @@ +#include "asm/x86/init.hpp" +#include "LIEF/asm/x86/operands/Register.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Register", + R"doc( + This class represents a register operand. + + For instance: + + .. code-block:: text + + mov r15d, edi + | | + | +---------> Register(EDI) + | + +---------------> Register(R15D) + )doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("value"); + + obj + .def_prop_ro("value", &x86::operands::Register::value, + R"doc( + The effective :class:`lief.assembly.x86.REG` wrapped by this operand + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/pyInstruction.cpp b/vendor/lief/api/python/src/asm/x86/pyInstruction.cpp new file mode 100644 index 0000000..48b6da9 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/pyInstruction.cpp @@ -0,0 +1,58 @@ +#include "LIEF/asm/x86/Instruction.hpp" +#include "LIEF/asm/x86/Operand.hpp" + +#include "asm/x86/init.hpp" +#include "pyOwningIterator.hpp" + +#include + +#include + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Instruction", + R"doc(This class represents a x86/x86-64 instruction)doc"_doc + ); + + obj.attr("__match_args__") = nb::make_tuple("opcode", "operands"); + + obj + .def_prop_ro("operands", [] (const x86::Instruction& self) { + auto ops = LIEF::py::owning_range(self.operands()); + return nb::make_iterator( + nb::type(), "operands_it", ops + ); + }, nb::keep_alive<0, 1>(), + R"doc(Iterator over the operands of the current instruction)doc"_doc + ) + .def_prop_ro("opcode", &Instruction::opcode, + R"doc(The instruction opcode as defined in LLVM)doc"_doc + ) + .def_prop_ro("has_lock_prefix", &Instruction::has_lock_prefix, + R"doc(True if this instruction has a ``LOCK`` prefix)doc"_doc + ) + .def_prop_ro("is_lockable", &Instruction::is_lockable, + R"doc(True if the ``LOCK`` prefix is architecturally valid on this instruction)doc"_doc + ) + .def_prop_ro("is_atomic", &Instruction::is_atomic, + R"doc(True if this instruction executes as an atomic read-modify-write)doc"_doc + ) + .def("lock", &Instruction::lock, + R"doc( + Re-encoded copy of this instruction with a ``LOCK`` prefix added. + + If the instruction already has a ``LOCK`` prefix, it returns a plain copy. + )doc"_doc + ) + .def("unlock", &Instruction::unlock, + R"doc( + Re-encoded copy of this instruction with the ``LOCK`` prefix removed. + + If the instruction does not have a ``LOCK`` prefix, it returns a plain + copy or ``None`` if the ``LOCK`` semantic can't be removed. + )doc"_doc + ) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/pyOpcode.cpp b/vendor/lief/api/python/src/asm/x86/pyOpcode.cpp new file mode 100644 index 0000000..9d0ec09 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/pyOpcode.cpp @@ -0,0 +1,22307 @@ +#include "asm/x86/init.hpp" + +#include "LIEF/asm/x86/opcodes.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::enum_ opcodes(m, "OPCODE"); + opcodes.value("PHI", LIEF::assembly::x86::OPCODE::PHI) + .value("INLINEASM", LIEF::assembly::x86::OPCODE::INLINEASM) + .value("INLINEASM_BR", LIEF::assembly::x86::OPCODE::INLINEASM_BR) + .value("CFI_INSTRUCTION", LIEF::assembly::x86::OPCODE::CFI_INSTRUCTION) + .value("EH_LABEL", LIEF::assembly::x86::OPCODE::EH_LABEL) + .value("GC_LABEL", LIEF::assembly::x86::OPCODE::GC_LABEL) + .value("ANNOTATION_LABEL", LIEF::assembly::x86::OPCODE::ANNOTATION_LABEL) + .value("KILL", LIEF::assembly::x86::OPCODE::KILL) + .value("EXTRACT_SUBREG", LIEF::assembly::x86::OPCODE::EXTRACT_SUBREG) + .value("INSERT_SUBREG", LIEF::assembly::x86::OPCODE::INSERT_SUBREG) + .value("IMPLICIT_DEF", LIEF::assembly::x86::OPCODE::IMPLICIT_DEF) + .value("INIT_UNDEF", LIEF::assembly::x86::OPCODE::INIT_UNDEF) + .value("SUBREG_TO_REG", LIEF::assembly::x86::OPCODE::SUBREG_TO_REG) + .value("COPY_TO_REGCLASS", LIEF::assembly::x86::OPCODE::COPY_TO_REGCLASS) + .value("DBG_VALUE", LIEF::assembly::x86::OPCODE::DBG_VALUE) + .value("DBG_VALUE_LIST", LIEF::assembly::x86::OPCODE::DBG_VALUE_LIST) + .value("DBG_INSTR_REF", LIEF::assembly::x86::OPCODE::DBG_INSTR_REF) + .value("DBG_PHI", LIEF::assembly::x86::OPCODE::DBG_PHI) + .value("DBG_LABEL", LIEF::assembly::x86::OPCODE::DBG_LABEL) + .value("REG_SEQUENCE", LIEF::assembly::x86::OPCODE::REG_SEQUENCE) + .value("COPY", LIEF::assembly::x86::OPCODE::COPY) + .value("COPY_LANEMASK", LIEF::assembly::x86::OPCODE::COPY_LANEMASK) + .value("BUNDLE", LIEF::assembly::x86::OPCODE::BUNDLE) + .value("LIFETIME_START", LIEF::assembly::x86::OPCODE::LIFETIME_START) + .value("LIFETIME_END", LIEF::assembly::x86::OPCODE::LIFETIME_END) + .value("PSEUDO_PROBE", LIEF::assembly::x86::OPCODE::PSEUDO_PROBE) + .value("ARITH_FENCE", LIEF::assembly::x86::OPCODE::ARITH_FENCE) + .value("STACKMAP", LIEF::assembly::x86::OPCODE::STACKMAP) + .value("FENTRY_CALL", LIEF::assembly::x86::OPCODE::FENTRY_CALL) + .value("PATCHPOINT", LIEF::assembly::x86::OPCODE::PATCHPOINT) + .value("LOAD_STACK_GUARD", LIEF::assembly::x86::OPCODE::LOAD_STACK_GUARD) + .value("PREALLOCATED_SETUP", LIEF::assembly::x86::OPCODE::PREALLOCATED_SETUP) + .value("PREALLOCATED_ARG", LIEF::assembly::x86::OPCODE::PREALLOCATED_ARG) + .value("STATEPOINT", LIEF::assembly::x86::OPCODE::STATEPOINT) + .value("LOCAL_ESCAPE", LIEF::assembly::x86::OPCODE::LOCAL_ESCAPE) + .value("FAULTING_OP", LIEF::assembly::x86::OPCODE::FAULTING_OP) + .value("PATCHABLE_OP", LIEF::assembly::x86::OPCODE::PATCHABLE_OP) + .value("PATCHABLE_FUNCTION_ENTER", LIEF::assembly::x86::OPCODE::PATCHABLE_FUNCTION_ENTER) + .value("PATCHABLE_RET", LIEF::assembly::x86::OPCODE::PATCHABLE_RET) + .value("PATCHABLE_FUNCTION_EXIT", LIEF::assembly::x86::OPCODE::PATCHABLE_FUNCTION_EXIT) + .value("PATCHABLE_TAIL_CALL", LIEF::assembly::x86::OPCODE::PATCHABLE_TAIL_CALL) + .value("PATCHABLE_EVENT_CALL", LIEF::assembly::x86::OPCODE::PATCHABLE_EVENT_CALL) + .value("PATCHABLE_TYPED_EVENT_CALL", LIEF::assembly::x86::OPCODE::PATCHABLE_TYPED_EVENT_CALL) + .value("ICALL_BRANCH_FUNNEL", LIEF::assembly::x86::OPCODE::ICALL_BRANCH_FUNNEL) + .value("FAKE_USE", LIEF::assembly::x86::OPCODE::FAKE_USE) + .value("MEMBARRIER", LIEF::assembly::x86::OPCODE::MEMBARRIER) + .value("JUMP_TABLE_DEBUG_INFO", LIEF::assembly::x86::OPCODE::JUMP_TABLE_DEBUG_INFO) + .value("RELOC_NONE", LIEF::assembly::x86::OPCODE::RELOC_NONE) + .value("CONVERGENCECTRL_ENTRY", LIEF::assembly::x86::OPCODE::CONVERGENCECTRL_ENTRY) + .value("CONVERGENCECTRL_ANCHOR", LIEF::assembly::x86::OPCODE::CONVERGENCECTRL_ANCHOR) + .value("CONVERGENCECTRL_LOOP", LIEF::assembly::x86::OPCODE::CONVERGENCECTRL_LOOP) + .value("CONVERGENCECTRL_GLUE", LIEF::assembly::x86::OPCODE::CONVERGENCECTRL_GLUE) + .value("G_ASSERT_SEXT", LIEF::assembly::x86::OPCODE::G_ASSERT_SEXT) + .value("G_ASSERT_ZEXT", LIEF::assembly::x86::OPCODE::G_ASSERT_ZEXT) + .value("G_ASSERT_ALIGN", LIEF::assembly::x86::OPCODE::G_ASSERT_ALIGN) + .value("G_ADD", LIEF::assembly::x86::OPCODE::G_ADD) + .value("G_SUB", LIEF::assembly::x86::OPCODE::G_SUB) + .value("G_MUL", LIEF::assembly::x86::OPCODE::G_MUL) + .value("G_SDIV", LIEF::assembly::x86::OPCODE::G_SDIV) + .value("G_UDIV", LIEF::assembly::x86::OPCODE::G_UDIV) + .value("G_SREM", LIEF::assembly::x86::OPCODE::G_SREM) + .value("G_UREM", LIEF::assembly::x86::OPCODE::G_UREM) + .value("G_SDIVREM", LIEF::assembly::x86::OPCODE::G_SDIVREM) + .value("G_UDIVREM", LIEF::assembly::x86::OPCODE::G_UDIVREM) + .value("G_AND", LIEF::assembly::x86::OPCODE::G_AND) + .value("G_OR", LIEF::assembly::x86::OPCODE::G_OR) + .value("G_XOR", LIEF::assembly::x86::OPCODE::G_XOR) + .value("G_ABDS", LIEF::assembly::x86::OPCODE::G_ABDS) + .value("G_ABDU", LIEF::assembly::x86::OPCODE::G_ABDU) + .value("G_UAVGFLOOR", LIEF::assembly::x86::OPCODE::G_UAVGFLOOR) + .value("G_UAVGCEIL", LIEF::assembly::x86::OPCODE::G_UAVGCEIL) + .value("G_SAVGFLOOR", LIEF::assembly::x86::OPCODE::G_SAVGFLOOR) + .value("G_SAVGCEIL", LIEF::assembly::x86::OPCODE::G_SAVGCEIL) + .value("G_IMPLICIT_DEF", LIEF::assembly::x86::OPCODE::G_IMPLICIT_DEF) + .value("G_PHI", LIEF::assembly::x86::OPCODE::G_PHI) + .value("G_FRAME_INDEX", LIEF::assembly::x86::OPCODE::G_FRAME_INDEX) + .value("G_GLOBAL_VALUE", LIEF::assembly::x86::OPCODE::G_GLOBAL_VALUE) + .value("G_PTRAUTH_GLOBAL_VALUE", LIEF::assembly::x86::OPCODE::G_PTRAUTH_GLOBAL_VALUE) + .value("G_CONSTANT_POOL", LIEF::assembly::x86::OPCODE::G_CONSTANT_POOL) + .value("G_EXTRACT", LIEF::assembly::x86::OPCODE::G_EXTRACT) + .value("G_UNMERGE_VALUES", LIEF::assembly::x86::OPCODE::G_UNMERGE_VALUES) + .value("G_INSERT", LIEF::assembly::x86::OPCODE::G_INSERT) + .value("G_MERGE_VALUES", LIEF::assembly::x86::OPCODE::G_MERGE_VALUES) + .value("G_BUILD_VECTOR", LIEF::assembly::x86::OPCODE::G_BUILD_VECTOR) + .value("G_BUILD_VECTOR_TRUNC", LIEF::assembly::x86::OPCODE::G_BUILD_VECTOR_TRUNC) + .value("G_CONCAT_VECTORS", LIEF::assembly::x86::OPCODE::G_CONCAT_VECTORS) + .value("G_PTRTOINT", LIEF::assembly::x86::OPCODE::G_PTRTOINT) + .value("G_INTTOPTR", LIEF::assembly::x86::OPCODE::G_INTTOPTR) + .value("G_BITCAST", LIEF::assembly::x86::OPCODE::G_BITCAST) + .value("G_FREEZE", LIEF::assembly::x86::OPCODE::G_FREEZE) + .value("G_CONSTANT_FOLD_BARRIER", LIEF::assembly::x86::OPCODE::G_CONSTANT_FOLD_BARRIER) + .value("G_INTRINSIC_FPTRUNC_ROUND", LIEF::assembly::x86::OPCODE::G_INTRINSIC_FPTRUNC_ROUND) + .value("G_INTRINSIC_TRUNC", LIEF::assembly::x86::OPCODE::G_INTRINSIC_TRUNC) + .value("G_INTRINSIC_ROUND", LIEF::assembly::x86::OPCODE::G_INTRINSIC_ROUND) + .value("G_INTRINSIC_LRINT", LIEF::assembly::x86::OPCODE::G_INTRINSIC_LRINT) + .value("G_INTRINSIC_LLRINT", LIEF::assembly::x86::OPCODE::G_INTRINSIC_LLRINT) + .value("G_INTRINSIC_ROUNDEVEN", LIEF::assembly::x86::OPCODE::G_INTRINSIC_ROUNDEVEN) + .value("G_READCYCLECOUNTER", LIEF::assembly::x86::OPCODE::G_READCYCLECOUNTER) + .value("G_READSTEADYCOUNTER", LIEF::assembly::x86::OPCODE::G_READSTEADYCOUNTER) + .value("G_LOAD", LIEF::assembly::x86::OPCODE::G_LOAD) + .value("G_SEXTLOAD", LIEF::assembly::x86::OPCODE::G_SEXTLOAD) + .value("G_ZEXTLOAD", LIEF::assembly::x86::OPCODE::G_ZEXTLOAD) + .value("G_INDEXED_LOAD", LIEF::assembly::x86::OPCODE::G_INDEXED_LOAD) + .value("G_INDEXED_SEXTLOAD", LIEF::assembly::x86::OPCODE::G_INDEXED_SEXTLOAD) + .value("G_INDEXED_ZEXTLOAD", LIEF::assembly::x86::OPCODE::G_INDEXED_ZEXTLOAD) + .value("G_STORE", LIEF::assembly::x86::OPCODE::G_STORE) + .value("G_INDEXED_STORE", LIEF::assembly::x86::OPCODE::G_INDEXED_STORE) + .value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::x86::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS) + .value("G_ATOMIC_CMPXCHG", LIEF::assembly::x86::OPCODE::G_ATOMIC_CMPXCHG) + .value("G_ATOMICRMW_XCHG", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_XCHG) + .value("G_ATOMICRMW_ADD", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_ADD) + .value("G_ATOMICRMW_SUB", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_SUB) + .value("G_ATOMICRMW_AND", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_AND) + .value("G_ATOMICRMW_NAND", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_NAND) + .value("G_ATOMICRMW_OR", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_OR) + .value("G_ATOMICRMW_XOR", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_XOR) + .value("G_ATOMICRMW_MAX", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_MAX) + .value("G_ATOMICRMW_MIN", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_MIN) + .value("G_ATOMICRMW_UMAX", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_UMAX) + .value("G_ATOMICRMW_UMIN", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_UMIN) + .value("G_ATOMICRMW_FADD", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FADD) + .value("G_ATOMICRMW_FSUB", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FSUB) + .value("G_ATOMICRMW_FMAX", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FMAX) + .value("G_ATOMICRMW_FMIN", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FMIN) + .value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FMAXIMUM) + .value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_FMINIMUM) + .value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_UINC_WRAP) + .value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_UDEC_WRAP) + .value("G_ATOMICRMW_USUB_COND", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_USUB_COND) + .value("G_ATOMICRMW_USUB_SAT", LIEF::assembly::x86::OPCODE::G_ATOMICRMW_USUB_SAT) + .value("G_FENCE", LIEF::assembly::x86::OPCODE::G_FENCE) + .value("G_PREFETCH", LIEF::assembly::x86::OPCODE::G_PREFETCH) + .value("G_BRCOND", LIEF::assembly::x86::OPCODE::G_BRCOND) + .value("G_BRINDIRECT", LIEF::assembly::x86::OPCODE::G_BRINDIRECT) + .value("G_INVOKE_REGION_START", LIEF::assembly::x86::OPCODE::G_INVOKE_REGION_START) + .value("G_INTRINSIC", LIEF::assembly::x86::OPCODE::G_INTRINSIC) + .value("G_INTRINSIC_W_SIDE_EFFECTS", LIEF::assembly::x86::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS) + .value("G_INTRINSIC_CONVERGENT", LIEF::assembly::x86::OPCODE::G_INTRINSIC_CONVERGENT) + .value("G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS", LIEF::assembly::x86::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) + .value("G_ANYEXT", LIEF::assembly::x86::OPCODE::G_ANYEXT) + .value("G_TRUNC", LIEF::assembly::x86::OPCODE::G_TRUNC) + .value("G_TRUNC_SSAT_S", LIEF::assembly::x86::OPCODE::G_TRUNC_SSAT_S) + .value("G_TRUNC_SSAT_U", LIEF::assembly::x86::OPCODE::G_TRUNC_SSAT_U) + .value("G_TRUNC_USAT_U", LIEF::assembly::x86::OPCODE::G_TRUNC_USAT_U) + .value("G_CONSTANT", LIEF::assembly::x86::OPCODE::G_CONSTANT) + .value("G_FCONSTANT", LIEF::assembly::x86::OPCODE::G_FCONSTANT) + .value("G_VASTART", LIEF::assembly::x86::OPCODE::G_VASTART) + .value("G_VAARG", LIEF::assembly::x86::OPCODE::G_VAARG) + .value("G_SEXT", LIEF::assembly::x86::OPCODE::G_SEXT) + .value("G_SEXT_INREG", LIEF::assembly::x86::OPCODE::G_SEXT_INREG) + .value("G_ZEXT", LIEF::assembly::x86::OPCODE::G_ZEXT) + .value("G_SHL", LIEF::assembly::x86::OPCODE::G_SHL) + .value("G_LSHR", LIEF::assembly::x86::OPCODE::G_LSHR) + .value("G_ASHR", LIEF::assembly::x86::OPCODE::G_ASHR) + .value("G_FSHL", LIEF::assembly::x86::OPCODE::G_FSHL) + .value("G_FSHR", LIEF::assembly::x86::OPCODE::G_FSHR) + .value("G_ROTR", LIEF::assembly::x86::OPCODE::G_ROTR) + .value("G_ROTL", LIEF::assembly::x86::OPCODE::G_ROTL) + .value("G_ICMP", LIEF::assembly::x86::OPCODE::G_ICMP) + .value("G_FCMP", LIEF::assembly::x86::OPCODE::G_FCMP) + .value("G_SCMP", LIEF::assembly::x86::OPCODE::G_SCMP) + .value("G_UCMP", LIEF::assembly::x86::OPCODE::G_UCMP) + .value("G_SELECT", LIEF::assembly::x86::OPCODE::G_SELECT) + .value("G_UADDO", LIEF::assembly::x86::OPCODE::G_UADDO) + .value("G_UADDE", LIEF::assembly::x86::OPCODE::G_UADDE) + .value("G_USUBO", LIEF::assembly::x86::OPCODE::G_USUBO) + .value("G_USUBE", LIEF::assembly::x86::OPCODE::G_USUBE) + .value("G_SADDO", LIEF::assembly::x86::OPCODE::G_SADDO) + .value("G_SADDE", LIEF::assembly::x86::OPCODE::G_SADDE) + .value("G_SSUBO", LIEF::assembly::x86::OPCODE::G_SSUBO) + .value("G_SSUBE", LIEF::assembly::x86::OPCODE::G_SSUBE) + .value("G_UMULO", LIEF::assembly::x86::OPCODE::G_UMULO) + .value("G_SMULO", LIEF::assembly::x86::OPCODE::G_SMULO) + .value("G_UMULH", LIEF::assembly::x86::OPCODE::G_UMULH) + .value("G_SMULH", LIEF::assembly::x86::OPCODE::G_SMULH) + .value("G_UADDSAT", LIEF::assembly::x86::OPCODE::G_UADDSAT) + .value("G_SADDSAT", LIEF::assembly::x86::OPCODE::G_SADDSAT) + .value("G_USUBSAT", LIEF::assembly::x86::OPCODE::G_USUBSAT) + .value("G_SSUBSAT", LIEF::assembly::x86::OPCODE::G_SSUBSAT) + .value("G_USHLSAT", LIEF::assembly::x86::OPCODE::G_USHLSAT) + .value("G_SSHLSAT", LIEF::assembly::x86::OPCODE::G_SSHLSAT) + .value("G_SMULFIX", LIEF::assembly::x86::OPCODE::G_SMULFIX) + .value("G_UMULFIX", LIEF::assembly::x86::OPCODE::G_UMULFIX) + .value("G_SMULFIXSAT", LIEF::assembly::x86::OPCODE::G_SMULFIXSAT) + .value("G_UMULFIXSAT", LIEF::assembly::x86::OPCODE::G_UMULFIXSAT) + .value("G_SDIVFIX", LIEF::assembly::x86::OPCODE::G_SDIVFIX) + .value("G_UDIVFIX", LIEF::assembly::x86::OPCODE::G_UDIVFIX) + .value("G_SDIVFIXSAT", LIEF::assembly::x86::OPCODE::G_SDIVFIXSAT) + .value("G_UDIVFIXSAT", LIEF::assembly::x86::OPCODE::G_UDIVFIXSAT) + .value("G_FADD", LIEF::assembly::x86::OPCODE::G_FADD) + .value("G_FSUB", LIEF::assembly::x86::OPCODE::G_FSUB) + .value("G_FMUL", LIEF::assembly::x86::OPCODE::G_FMUL) + .value("G_FMA", LIEF::assembly::x86::OPCODE::G_FMA) + .value("G_FMAD", LIEF::assembly::x86::OPCODE::G_FMAD) + .value("G_FDIV", LIEF::assembly::x86::OPCODE::G_FDIV) + .value("G_FREM", LIEF::assembly::x86::OPCODE::G_FREM) + .value("G_FMODF", LIEF::assembly::x86::OPCODE::G_FMODF) + .value("G_FPOW", LIEF::assembly::x86::OPCODE::G_FPOW) + .value("G_FPOWI", LIEF::assembly::x86::OPCODE::G_FPOWI) + .value("G_FEXP", LIEF::assembly::x86::OPCODE::G_FEXP) + .value("G_FEXP2", LIEF::assembly::x86::OPCODE::G_FEXP2) + .value("G_FEXP10", LIEF::assembly::x86::OPCODE::G_FEXP10) + .value("G_FLOG", LIEF::assembly::x86::OPCODE::G_FLOG) + .value("G_FLOG2", LIEF::assembly::x86::OPCODE::G_FLOG2) + .value("G_FLOG10", LIEF::assembly::x86::OPCODE::G_FLOG10) + .value("G_FLDEXP", LIEF::assembly::x86::OPCODE::G_FLDEXP) + .value("G_FFREXP", LIEF::assembly::x86::OPCODE::G_FFREXP) + .value("G_FNEG", LIEF::assembly::x86::OPCODE::G_FNEG) + .value("G_FPEXT", LIEF::assembly::x86::OPCODE::G_FPEXT) + .value("G_FPTRUNC", LIEF::assembly::x86::OPCODE::G_FPTRUNC) + .value("G_FPTOSI", LIEF::assembly::x86::OPCODE::G_FPTOSI) + .value("G_FPTOUI", LIEF::assembly::x86::OPCODE::G_FPTOUI) + .value("G_SITOFP", LIEF::assembly::x86::OPCODE::G_SITOFP) + .value("G_UITOFP", LIEF::assembly::x86::OPCODE::G_UITOFP) + .value("G_FPTOSI_SAT", LIEF::assembly::x86::OPCODE::G_FPTOSI_SAT) + .value("G_FPTOUI_SAT", LIEF::assembly::x86::OPCODE::G_FPTOUI_SAT) + .value("G_FABS", LIEF::assembly::x86::OPCODE::G_FABS) + .value("G_FCOPYSIGN", LIEF::assembly::x86::OPCODE::G_FCOPYSIGN) + .value("G_IS_FPCLASS", LIEF::assembly::x86::OPCODE::G_IS_FPCLASS) + .value("G_FCANONICALIZE", LIEF::assembly::x86::OPCODE::G_FCANONICALIZE) + .value("G_FMINNUM", LIEF::assembly::x86::OPCODE::G_FMINNUM) + .value("G_FMAXNUM", LIEF::assembly::x86::OPCODE::G_FMAXNUM) + .value("G_FMINNUM_IEEE", LIEF::assembly::x86::OPCODE::G_FMINNUM_IEEE) + .value("G_FMAXNUM_IEEE", LIEF::assembly::x86::OPCODE::G_FMAXNUM_IEEE) + .value("G_FMINIMUM", LIEF::assembly::x86::OPCODE::G_FMINIMUM) + .value("G_FMAXIMUM", LIEF::assembly::x86::OPCODE::G_FMAXIMUM) + .value("G_FMINIMUMNUM", LIEF::assembly::x86::OPCODE::G_FMINIMUMNUM) + .value("G_FMAXIMUMNUM", LIEF::assembly::x86::OPCODE::G_FMAXIMUMNUM) + .value("G_GET_FPENV", LIEF::assembly::x86::OPCODE::G_GET_FPENV) + .value("G_SET_FPENV", LIEF::assembly::x86::OPCODE::G_SET_FPENV) + .value("G_RESET_FPENV", LIEF::assembly::x86::OPCODE::G_RESET_FPENV) + .value("G_GET_FPMODE", LIEF::assembly::x86::OPCODE::G_GET_FPMODE) + .value("G_SET_FPMODE", LIEF::assembly::x86::OPCODE::G_SET_FPMODE) + .value("G_RESET_FPMODE", LIEF::assembly::x86::OPCODE::G_RESET_FPMODE) + .value("G_GET_ROUNDING", LIEF::assembly::x86::OPCODE::G_GET_ROUNDING) + .value("G_SET_ROUNDING", LIEF::assembly::x86::OPCODE::G_SET_ROUNDING) + .value("G_PTR_ADD", LIEF::assembly::x86::OPCODE::G_PTR_ADD) + .value("G_PTRMASK", LIEF::assembly::x86::OPCODE::G_PTRMASK) + .value("G_SMIN", LIEF::assembly::x86::OPCODE::G_SMIN) + .value("G_SMAX", LIEF::assembly::x86::OPCODE::G_SMAX) + .value("G_UMIN", LIEF::assembly::x86::OPCODE::G_UMIN) + .value("G_UMAX", LIEF::assembly::x86::OPCODE::G_UMAX) + .value("G_ABS", LIEF::assembly::x86::OPCODE::G_ABS) + .value("G_LROUND", LIEF::assembly::x86::OPCODE::G_LROUND) + .value("G_LLROUND", LIEF::assembly::x86::OPCODE::G_LLROUND) + .value("G_BR", LIEF::assembly::x86::OPCODE::G_BR) + .value("G_BRJT", LIEF::assembly::x86::OPCODE::G_BRJT) + .value("G_VSCALE", LIEF::assembly::x86::OPCODE::G_VSCALE) + .value("G_INSERT_SUBVECTOR", LIEF::assembly::x86::OPCODE::G_INSERT_SUBVECTOR) + .value("G_EXTRACT_SUBVECTOR", LIEF::assembly::x86::OPCODE::G_EXTRACT_SUBVECTOR) + .value("G_INSERT_VECTOR_ELT", LIEF::assembly::x86::OPCODE::G_INSERT_VECTOR_ELT) + .value("G_EXTRACT_VECTOR_ELT", LIEF::assembly::x86::OPCODE::G_EXTRACT_VECTOR_ELT) + .value("G_SHUFFLE_VECTOR", LIEF::assembly::x86::OPCODE::G_SHUFFLE_VECTOR) + .value("G_SPLAT_VECTOR", LIEF::assembly::x86::OPCODE::G_SPLAT_VECTOR) + .value("G_STEP_VECTOR", LIEF::assembly::x86::OPCODE::G_STEP_VECTOR) + .value("G_VECTOR_COMPRESS", LIEF::assembly::x86::OPCODE::G_VECTOR_COMPRESS) + .value("G_CTTZ", LIEF::assembly::x86::OPCODE::G_CTTZ) + .value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::x86::OPCODE::G_CTTZ_ZERO_UNDEF) + .value("G_CTLZ", LIEF::assembly::x86::OPCODE::G_CTLZ) + .value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::x86::OPCODE::G_CTLZ_ZERO_UNDEF) + .value("G_CTPOP", LIEF::assembly::x86::OPCODE::G_CTPOP) + .value("G_BSWAP", LIEF::assembly::x86::OPCODE::G_BSWAP) + .value("G_BITREVERSE", LIEF::assembly::x86::OPCODE::G_BITREVERSE) + .value("G_FCEIL", LIEF::assembly::x86::OPCODE::G_FCEIL) + .value("G_FCOS", LIEF::assembly::x86::OPCODE::G_FCOS) + .value("G_FSIN", LIEF::assembly::x86::OPCODE::G_FSIN) + .value("G_FSINCOS", LIEF::assembly::x86::OPCODE::G_FSINCOS) + .value("G_FTAN", LIEF::assembly::x86::OPCODE::G_FTAN) + .value("G_FACOS", LIEF::assembly::x86::OPCODE::G_FACOS) + .value("G_FASIN", LIEF::assembly::x86::OPCODE::G_FASIN) + .value("G_FATAN", LIEF::assembly::x86::OPCODE::G_FATAN) + .value("G_FATAN2", LIEF::assembly::x86::OPCODE::G_FATAN2) + .value("G_FCOSH", LIEF::assembly::x86::OPCODE::G_FCOSH) + .value("G_FSINH", LIEF::assembly::x86::OPCODE::G_FSINH) + .value("G_FTANH", LIEF::assembly::x86::OPCODE::G_FTANH) + .value("G_FSQRT", LIEF::assembly::x86::OPCODE::G_FSQRT) + .value("G_FFLOOR", LIEF::assembly::x86::OPCODE::G_FFLOOR) + .value("G_FRINT", LIEF::assembly::x86::OPCODE::G_FRINT) + .value("G_FNEARBYINT", LIEF::assembly::x86::OPCODE::G_FNEARBYINT) + .value("G_ADDRSPACE_CAST", LIEF::assembly::x86::OPCODE::G_ADDRSPACE_CAST) + .value("G_BLOCK_ADDR", LIEF::assembly::x86::OPCODE::G_BLOCK_ADDR) + .value("G_JUMP_TABLE", LIEF::assembly::x86::OPCODE::G_JUMP_TABLE) + .value("G_DYN_STACKALLOC", LIEF::assembly::x86::OPCODE::G_DYN_STACKALLOC) + .value("G_STACKSAVE", LIEF::assembly::x86::OPCODE::G_STACKSAVE) + .value("G_STACKRESTORE", LIEF::assembly::x86::OPCODE::G_STACKRESTORE) + .value("G_STRICT_FADD", LIEF::assembly::x86::OPCODE::G_STRICT_FADD) + .value("G_STRICT_FSUB", LIEF::assembly::x86::OPCODE::G_STRICT_FSUB) + .value("G_STRICT_FMUL", LIEF::assembly::x86::OPCODE::G_STRICT_FMUL) + .value("G_STRICT_FDIV", LIEF::assembly::x86::OPCODE::G_STRICT_FDIV) + .value("G_STRICT_FREM", LIEF::assembly::x86::OPCODE::G_STRICT_FREM) + .value("G_STRICT_FMA", LIEF::assembly::x86::OPCODE::G_STRICT_FMA) + .value("G_STRICT_FSQRT", LIEF::assembly::x86::OPCODE::G_STRICT_FSQRT) + .value("G_STRICT_FLDEXP", LIEF::assembly::x86::OPCODE::G_STRICT_FLDEXP) + .value("G_READ_REGISTER", LIEF::assembly::x86::OPCODE::G_READ_REGISTER) + .value("G_WRITE_REGISTER", LIEF::assembly::x86::OPCODE::G_WRITE_REGISTER) + .value("G_MEMCPY", LIEF::assembly::x86::OPCODE::G_MEMCPY) + .value("G_MEMCPY_INLINE", LIEF::assembly::x86::OPCODE::G_MEMCPY_INLINE) + .value("G_MEMMOVE", LIEF::assembly::x86::OPCODE::G_MEMMOVE) + .value("G_MEMSET", LIEF::assembly::x86::OPCODE::G_MEMSET) + .value("G_BZERO", LIEF::assembly::x86::OPCODE::G_BZERO); + opcodes.value("G_TRAP", LIEF::assembly::x86::OPCODE::G_TRAP) + .value("G_DEBUGTRAP", LIEF::assembly::x86::OPCODE::G_DEBUGTRAP) + .value("G_UBSANTRAP", LIEF::assembly::x86::OPCODE::G_UBSANTRAP) + .value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::x86::OPCODE::G_VECREDUCE_SEQ_FADD) + .value("G_VECREDUCE_SEQ_FMUL", LIEF::assembly::x86::OPCODE::G_VECREDUCE_SEQ_FMUL) + .value("G_VECREDUCE_FADD", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FADD) + .value("G_VECREDUCE_FMUL", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FMUL) + .value("G_VECREDUCE_FMAX", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FMAX) + .value("G_VECREDUCE_FMIN", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FMIN) + .value("G_VECREDUCE_FMAXIMUM", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FMAXIMUM) + .value("G_VECREDUCE_FMINIMUM", LIEF::assembly::x86::OPCODE::G_VECREDUCE_FMINIMUM) + .value("G_VECREDUCE_ADD", LIEF::assembly::x86::OPCODE::G_VECREDUCE_ADD) + .value("G_VECREDUCE_MUL", LIEF::assembly::x86::OPCODE::G_VECREDUCE_MUL) + .value("G_VECREDUCE_AND", LIEF::assembly::x86::OPCODE::G_VECREDUCE_AND) + .value("G_VECREDUCE_OR", LIEF::assembly::x86::OPCODE::G_VECREDUCE_OR) + .value("G_VECREDUCE_XOR", LIEF::assembly::x86::OPCODE::G_VECREDUCE_XOR) + .value("G_VECREDUCE_SMAX", LIEF::assembly::x86::OPCODE::G_VECREDUCE_SMAX) + .value("G_VECREDUCE_SMIN", LIEF::assembly::x86::OPCODE::G_VECREDUCE_SMIN) + .value("G_VECREDUCE_UMAX", LIEF::assembly::x86::OPCODE::G_VECREDUCE_UMAX) + .value("G_VECREDUCE_UMIN", LIEF::assembly::x86::OPCODE::G_VECREDUCE_UMIN) + .value("G_SBFX", LIEF::assembly::x86::OPCODE::G_SBFX) + .value("G_UBFX", LIEF::assembly::x86::OPCODE::G_UBFX) + .value("ADD16ri_DB", LIEF::assembly::x86::OPCODE::ADD16ri_DB) + .value("ADD16rr_DB", LIEF::assembly::x86::OPCODE::ADD16rr_DB) + .value("ADD32ri_DB", LIEF::assembly::x86::OPCODE::ADD32ri_DB) + .value("ADD32rr_DB", LIEF::assembly::x86::OPCODE::ADD32rr_DB) + .value("ADD64ri32_DB", LIEF::assembly::x86::OPCODE::ADD64ri32_DB) + .value("ADD64rr_DB", LIEF::assembly::x86::OPCODE::ADD64rr_DB) + .value("ADD8ri_DB", LIEF::assembly::x86::OPCODE::ADD8ri_DB) + .value("ADD8rr_DB", LIEF::assembly::x86::OPCODE::ADD8rr_DB) + .value("AVX1_SETALLONES", LIEF::assembly::x86::OPCODE::AVX1_SETALLONES) + .value("AVX2_SETALLONES", LIEF::assembly::x86::OPCODE::AVX2_SETALLONES) + .value("AVX512_128_SET0", LIEF::assembly::x86::OPCODE::AVX512_128_SET0) + .value("AVX512_128_SETALLONES", LIEF::assembly::x86::OPCODE::AVX512_128_SETALLONES) + .value("AVX512_256_SET0", LIEF::assembly::x86::OPCODE::AVX512_256_SET0) + .value("AVX512_256_SETALLONES", LIEF::assembly::x86::OPCODE::AVX512_256_SETALLONES) + .value("AVX512_512_SET0", LIEF::assembly::x86::OPCODE::AVX512_512_SET0) + .value("AVX512_512_SETALLONES", LIEF::assembly::x86::OPCODE::AVX512_512_SETALLONES) + .value("AVX512_512_SEXT_MASK_32", LIEF::assembly::x86::OPCODE::AVX512_512_SEXT_MASK_32) + .value("AVX512_512_SEXT_MASK_64", LIEF::assembly::x86::OPCODE::AVX512_512_SEXT_MASK_64) + .value("AVX512_FsFLD0F128", LIEF::assembly::x86::OPCODE::AVX512_FsFLD0F128) + .value("AVX512_FsFLD0SD", LIEF::assembly::x86::OPCODE::AVX512_FsFLD0SD) + .value("AVX512_FsFLD0SH", LIEF::assembly::x86::OPCODE::AVX512_FsFLD0SH) + .value("AVX512_FsFLD0SS", LIEF::assembly::x86::OPCODE::AVX512_FsFLD0SS) + .value("AVX_SET0", LIEF::assembly::x86::OPCODE::AVX_SET0) + .value("CALL64m_RVMARKER", LIEF::assembly::x86::OPCODE::CALL64m_RVMARKER) + .value("CALL64pcrel32_RVMARKER", LIEF::assembly::x86::OPCODE::CALL64pcrel32_RVMARKER) + .value("CALL64r_ImpCall", LIEF::assembly::x86::OPCODE::CALL64r_ImpCall) + .value("CALL64r_RVMARKER", LIEF::assembly::x86::OPCODE::CALL64r_RVMARKER) + .value("FsFLD0F128", LIEF::assembly::x86::OPCODE::FsFLD0F128) + .value("FsFLD0SD", LIEF::assembly::x86::OPCODE::FsFLD0SD) + .value("FsFLD0SH", LIEF::assembly::x86::OPCODE::FsFLD0SH) + .value("FsFLD0SS", LIEF::assembly::x86::OPCODE::FsFLD0SS) + .value("G_FILD", LIEF::assembly::x86::OPCODE::G_FILD) + .value("G_FIST", LIEF::assembly::x86::OPCODE::G_FIST) + .value("G_FLDCW16", LIEF::assembly::x86::OPCODE::G_FLDCW16) + .value("G_FNSTCW16", LIEF::assembly::x86::OPCODE::G_FNSTCW16) + .value("INDIRECT_THUNK_CALL32", LIEF::assembly::x86::OPCODE::INDIRECT_THUNK_CALL32) + .value("INDIRECT_THUNK_CALL64", LIEF::assembly::x86::OPCODE::INDIRECT_THUNK_CALL64) + .value("INDIRECT_THUNK_TCRETURN32", LIEF::assembly::x86::OPCODE::INDIRECT_THUNK_TCRETURN32) + .value("INDIRECT_THUNK_TCRETURN64", LIEF::assembly::x86::OPCODE::INDIRECT_THUNK_TCRETURN64) + .value("KSET0B", LIEF::assembly::x86::OPCODE::KSET0B) + .value("KSET0D", LIEF::assembly::x86::OPCODE::KSET0D) + .value("KSET0Q", LIEF::assembly::x86::OPCODE::KSET0Q) + .value("KSET0W", LIEF::assembly::x86::OPCODE::KSET0W) + .value("KSET1B", LIEF::assembly::x86::OPCODE::KSET1B) + .value("KSET1D", LIEF::assembly::x86::OPCODE::KSET1D) + .value("KSET1Q", LIEF::assembly::x86::OPCODE::KSET1Q) + .value("KSET1W", LIEF::assembly::x86::OPCODE::KSET1W) + .value("LCMPXCHG16B_NO_RBX", LIEF::assembly::x86::OPCODE::LCMPXCHG16B_NO_RBX) + .value("LCMPXCHG16B_SAVE_RBX", LIEF::assembly::x86::OPCODE::LCMPXCHG16B_SAVE_RBX) + .value("MMX_SET0", LIEF::assembly::x86::OPCODE::MMX_SET0) + .value("MORESTACK_RET", LIEF::assembly::x86::OPCODE::MORESTACK_RET) + .value("MORESTACK_RET_RESTORE_R10", LIEF::assembly::x86::OPCODE::MORESTACK_RET_RESTORE_R10) + .value("MOV32ImmSExti8", LIEF::assembly::x86::OPCODE::MOV32ImmSExti8) + .value("MOV32r0", LIEF::assembly::x86::OPCODE::MOV32r0) + .value("MOV32r1", LIEF::assembly::x86::OPCODE::MOV32r1) + .value("MOV32r_1", LIEF::assembly::x86::OPCODE::MOV32r_1) + .value("MOV32ri64", LIEF::assembly::x86::OPCODE::MOV32ri64) + .value("MOV64ImmSExti8", LIEF::assembly::x86::OPCODE::MOV64ImmSExti8) + .value("MOVSHPmr", LIEF::assembly::x86::OPCODE::MOVSHPmr) + .value("MOVSHPrm", LIEF::assembly::x86::OPCODE::MOVSHPrm) + .value("MWAITX", LIEF::assembly::x86::OPCODE::MWAITX) + .value("MWAITX_SAVE_RBX", LIEF::assembly::x86::OPCODE::MWAITX_SAVE_RBX) + .value("PLDTILECFGV", LIEF::assembly::x86::OPCODE::PLDTILECFGV) + .value("PLEA32r", LIEF::assembly::x86::OPCODE::PLEA32r) + .value("PLEA64r", LIEF::assembly::x86::OPCODE::PLEA64r) + .value("PTDPBF16PSV", LIEF::assembly::x86::OPCODE::PTDPBF16PSV) + .value("PTDPBSSDV", LIEF::assembly::x86::OPCODE::PTDPBSSDV) + .value("PTDPBSUDV", LIEF::assembly::x86::OPCODE::PTDPBSUDV) + .value("PTDPBUSDV", LIEF::assembly::x86::OPCODE::PTDPBUSDV) + .value("PTDPBUUDV", LIEF::assembly::x86::OPCODE::PTDPBUUDV) + .value("PTDPFP16PSV", LIEF::assembly::x86::OPCODE::PTDPFP16PSV) + .value("PTILELOADDRST1V", LIEF::assembly::x86::OPCODE::PTILELOADDRST1V) + .value("PTILELOADDRSV", LIEF::assembly::x86::OPCODE::PTILELOADDRSV) + .value("PTILELOADDT1V", LIEF::assembly::x86::OPCODE::PTILELOADDT1V) + .value("PTILELOADDV", LIEF::assembly::x86::OPCODE::PTILELOADDV) + .value("PTILESTOREDV", LIEF::assembly::x86::OPCODE::PTILESTOREDV) + .value("PTILEZEROV", LIEF::assembly::x86::OPCODE::PTILEZEROV) + .value("RDFLAGS32", LIEF::assembly::x86::OPCODE::RDFLAGS32) + .value("RDFLAGS64", LIEF::assembly::x86::OPCODE::RDFLAGS64) + .value("SEH_BeginEpilogue", LIEF::assembly::x86::OPCODE::SEH_BeginEpilogue) + .value("SEH_EndEpilogue", LIEF::assembly::x86::OPCODE::SEH_EndEpilogue) + .value("SEH_EndPrologue", LIEF::assembly::x86::OPCODE::SEH_EndPrologue) + .value("SEH_PushFrame", LIEF::assembly::x86::OPCODE::SEH_PushFrame) + .value("SEH_PushReg", LIEF::assembly::x86::OPCODE::SEH_PushReg) + .value("SEH_SaveReg", LIEF::assembly::x86::OPCODE::SEH_SaveReg) + .value("SEH_SaveXMM", LIEF::assembly::x86::OPCODE::SEH_SaveXMM) + .value("SEH_SetFrame", LIEF::assembly::x86::OPCODE::SEH_SetFrame) + .value("SEH_StackAlign", LIEF::assembly::x86::OPCODE::SEH_StackAlign) + .value("SEH_StackAlloc", LIEF::assembly::x86::OPCODE::SEH_StackAlloc) + .value("SEH_UnwindV2Start", LIEF::assembly::x86::OPCODE::SEH_UnwindV2Start) + .value("SEH_UnwindVersion", LIEF::assembly::x86::OPCODE::SEH_UnwindVersion) + .value("SETB_C32r", LIEF::assembly::x86::OPCODE::SETB_C32r) + .value("SETB_C64r", LIEF::assembly::x86::OPCODE::SETB_C64r) + .value("SHLDROT32ri", LIEF::assembly::x86::OPCODE::SHLDROT32ri) + .value("SHLDROT64ri", LIEF::assembly::x86::OPCODE::SHLDROT64ri) + .value("SHRDROT32ri", LIEF::assembly::x86::OPCODE::SHRDROT32ri) + .value("SHRDROT64ri", LIEF::assembly::x86::OPCODE::SHRDROT64ri) + .value("VMOVAPSZ128mr_NOVLX", LIEF::assembly::x86::OPCODE::VMOVAPSZ128mr_NOVLX) + .value("VMOVAPSZ128rm_NOVLX", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rm_NOVLX) + .value("VMOVAPSZ256mr_NOVLX", LIEF::assembly::x86::OPCODE::VMOVAPSZ256mr_NOVLX) + .value("VMOVAPSZ256rm_NOVLX", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rm_NOVLX) + .value("VMOVUPSZ128mr_NOVLX", LIEF::assembly::x86::OPCODE::VMOVUPSZ128mr_NOVLX) + .value("VMOVUPSZ128rm_NOVLX", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rm_NOVLX) + .value("VMOVUPSZ256mr_NOVLX", LIEF::assembly::x86::OPCODE::VMOVUPSZ256mr_NOVLX) + .value("VMOVUPSZ256rm_NOVLX", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rm_NOVLX) + .value("V_SET0", LIEF::assembly::x86::OPCODE::V_SET0) + .value("V_SETALLONES", LIEF::assembly::x86::OPCODE::V_SETALLONES) + .value("WRFLAGS32", LIEF::assembly::x86::OPCODE::WRFLAGS32) + .value("WRFLAGS64", LIEF::assembly::x86::OPCODE::WRFLAGS64) + .value("XABORT_DEF", LIEF::assembly::x86::OPCODE::XABORT_DEF) + .value("XOR32_FP", LIEF::assembly::x86::OPCODE::XOR32_FP) + .value("XOR64_FP", LIEF::assembly::x86::OPCODE::XOR64_FP) + .value("AAA", LIEF::assembly::x86::OPCODE::AAA) + .value("AAD8i8", LIEF::assembly::x86::OPCODE::AAD8i8) + .value("AADD32mr", LIEF::assembly::x86::OPCODE::AADD32mr) + .value("AADD32mr_EVEX", LIEF::assembly::x86::OPCODE::AADD32mr_EVEX) + .value("AADD64mr", LIEF::assembly::x86::OPCODE::AADD64mr) + .value("AADD64mr_EVEX", LIEF::assembly::x86::OPCODE::AADD64mr_EVEX) + .value("AAM8i8", LIEF::assembly::x86::OPCODE::AAM8i8) + .value("AAND32mr", LIEF::assembly::x86::OPCODE::AAND32mr) + .value("AAND32mr_EVEX", LIEF::assembly::x86::OPCODE::AAND32mr_EVEX) + .value("AAND64mr", LIEF::assembly::x86::OPCODE::AAND64mr) + .value("AAND64mr_EVEX", LIEF::assembly::x86::OPCODE::AAND64mr_EVEX) + .value("AAS", LIEF::assembly::x86::OPCODE::AAS) + .value("ABS_F", LIEF::assembly::x86::OPCODE::ABS_F) + .value("ABS_Fp32", LIEF::assembly::x86::OPCODE::ABS_Fp32) + .value("ABS_Fp64", LIEF::assembly::x86::OPCODE::ABS_Fp64) + .value("ABS_Fp80", LIEF::assembly::x86::OPCODE::ABS_Fp80) + .value("ADC16i16", LIEF::assembly::x86::OPCODE::ADC16i16) + .value("ADC16mi", LIEF::assembly::x86::OPCODE::ADC16mi) + .value("ADC16mi8", LIEF::assembly::x86::OPCODE::ADC16mi8) + .value("ADC16mi8_EVEX", LIEF::assembly::x86::OPCODE::ADC16mi8_EVEX) + .value("ADC16mi8_ND", LIEF::assembly::x86::OPCODE::ADC16mi8_ND) + .value("ADC16mi_EVEX", LIEF::assembly::x86::OPCODE::ADC16mi_EVEX) + .value("ADC16mi_ND", LIEF::assembly::x86::OPCODE::ADC16mi_ND) + .value("ADC16mr", LIEF::assembly::x86::OPCODE::ADC16mr) + .value("ADC16mr_EVEX", LIEF::assembly::x86::OPCODE::ADC16mr_EVEX) + .value("ADC16mr_ND", LIEF::assembly::x86::OPCODE::ADC16mr_ND) + .value("ADC16ri", LIEF::assembly::x86::OPCODE::ADC16ri) + .value("ADC16ri8", LIEF::assembly::x86::OPCODE::ADC16ri8) + .value("ADC16ri8_EVEX", LIEF::assembly::x86::OPCODE::ADC16ri8_EVEX) + .value("ADC16ri8_ND", LIEF::assembly::x86::OPCODE::ADC16ri8_ND) + .value("ADC16ri_EVEX", LIEF::assembly::x86::OPCODE::ADC16ri_EVEX) + .value("ADC16ri_ND", LIEF::assembly::x86::OPCODE::ADC16ri_ND) + .value("ADC16rm", LIEF::assembly::x86::OPCODE::ADC16rm) + .value("ADC16rm_EVEX", LIEF::assembly::x86::OPCODE::ADC16rm_EVEX) + .value("ADC16rm_ND", LIEF::assembly::x86::OPCODE::ADC16rm_ND) + .value("ADC16rr", LIEF::assembly::x86::OPCODE::ADC16rr) + .value("ADC16rr_EVEX", LIEF::assembly::x86::OPCODE::ADC16rr_EVEX) + .value("ADC16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADC16rr_EVEX_REV) + .value("ADC16rr_ND", LIEF::assembly::x86::OPCODE::ADC16rr_ND) + .value("ADC16rr_ND_REV", LIEF::assembly::x86::OPCODE::ADC16rr_ND_REV) + .value("ADC16rr_REV", LIEF::assembly::x86::OPCODE::ADC16rr_REV) + .value("ADC32i32", LIEF::assembly::x86::OPCODE::ADC32i32) + .value("ADC32mi", LIEF::assembly::x86::OPCODE::ADC32mi) + .value("ADC32mi8", LIEF::assembly::x86::OPCODE::ADC32mi8) + .value("ADC32mi8_EVEX", LIEF::assembly::x86::OPCODE::ADC32mi8_EVEX) + .value("ADC32mi8_ND", LIEF::assembly::x86::OPCODE::ADC32mi8_ND) + .value("ADC32mi_EVEX", LIEF::assembly::x86::OPCODE::ADC32mi_EVEX) + .value("ADC32mi_ND", LIEF::assembly::x86::OPCODE::ADC32mi_ND) + .value("ADC32mr", LIEF::assembly::x86::OPCODE::ADC32mr) + .value("ADC32mr_EVEX", LIEF::assembly::x86::OPCODE::ADC32mr_EVEX) + .value("ADC32mr_ND", LIEF::assembly::x86::OPCODE::ADC32mr_ND) + .value("ADC32ri", LIEF::assembly::x86::OPCODE::ADC32ri) + .value("ADC32ri8", LIEF::assembly::x86::OPCODE::ADC32ri8) + .value("ADC32ri8_EVEX", LIEF::assembly::x86::OPCODE::ADC32ri8_EVEX) + .value("ADC32ri8_ND", LIEF::assembly::x86::OPCODE::ADC32ri8_ND) + .value("ADC32ri_EVEX", LIEF::assembly::x86::OPCODE::ADC32ri_EVEX) + .value("ADC32ri_ND", LIEF::assembly::x86::OPCODE::ADC32ri_ND) + .value("ADC32rm", LIEF::assembly::x86::OPCODE::ADC32rm) + .value("ADC32rm_EVEX", LIEF::assembly::x86::OPCODE::ADC32rm_EVEX) + .value("ADC32rm_ND", LIEF::assembly::x86::OPCODE::ADC32rm_ND) + .value("ADC32rr", LIEF::assembly::x86::OPCODE::ADC32rr) + .value("ADC32rr_EVEX", LIEF::assembly::x86::OPCODE::ADC32rr_EVEX) + .value("ADC32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADC32rr_EVEX_REV) + .value("ADC32rr_ND", LIEF::assembly::x86::OPCODE::ADC32rr_ND) + .value("ADC32rr_ND_REV", LIEF::assembly::x86::OPCODE::ADC32rr_ND_REV) + .value("ADC32rr_REV", LIEF::assembly::x86::OPCODE::ADC32rr_REV) + .value("ADC64i32", LIEF::assembly::x86::OPCODE::ADC64i32) + .value("ADC64mi32", LIEF::assembly::x86::OPCODE::ADC64mi32) + .value("ADC64mi32_EVEX", LIEF::assembly::x86::OPCODE::ADC64mi32_EVEX) + .value("ADC64mi32_ND", LIEF::assembly::x86::OPCODE::ADC64mi32_ND) + .value("ADC64mi8", LIEF::assembly::x86::OPCODE::ADC64mi8) + .value("ADC64mi8_EVEX", LIEF::assembly::x86::OPCODE::ADC64mi8_EVEX) + .value("ADC64mi8_ND", LIEF::assembly::x86::OPCODE::ADC64mi8_ND) + .value("ADC64mr", LIEF::assembly::x86::OPCODE::ADC64mr) + .value("ADC64mr_EVEX", LIEF::assembly::x86::OPCODE::ADC64mr_EVEX) + .value("ADC64mr_ND", LIEF::assembly::x86::OPCODE::ADC64mr_ND) + .value("ADC64ri32", LIEF::assembly::x86::OPCODE::ADC64ri32) + .value("ADC64ri32_EVEX", LIEF::assembly::x86::OPCODE::ADC64ri32_EVEX) + .value("ADC64ri32_ND", LIEF::assembly::x86::OPCODE::ADC64ri32_ND) + .value("ADC64ri8", LIEF::assembly::x86::OPCODE::ADC64ri8) + .value("ADC64ri8_EVEX", LIEF::assembly::x86::OPCODE::ADC64ri8_EVEX) + .value("ADC64ri8_ND", LIEF::assembly::x86::OPCODE::ADC64ri8_ND) + .value("ADC64rm", LIEF::assembly::x86::OPCODE::ADC64rm) + .value("ADC64rm_EVEX", LIEF::assembly::x86::OPCODE::ADC64rm_EVEX) + .value("ADC64rm_ND", LIEF::assembly::x86::OPCODE::ADC64rm_ND) + .value("ADC64rr", LIEF::assembly::x86::OPCODE::ADC64rr) + .value("ADC64rr_EVEX", LIEF::assembly::x86::OPCODE::ADC64rr_EVEX) + .value("ADC64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADC64rr_EVEX_REV) + .value("ADC64rr_ND", LIEF::assembly::x86::OPCODE::ADC64rr_ND) + .value("ADC64rr_ND_REV", LIEF::assembly::x86::OPCODE::ADC64rr_ND_REV) + .value("ADC64rr_REV", LIEF::assembly::x86::OPCODE::ADC64rr_REV) + .value("ADC8i8", LIEF::assembly::x86::OPCODE::ADC8i8) + .value("ADC8mi", LIEF::assembly::x86::OPCODE::ADC8mi) + .value("ADC8mi8", LIEF::assembly::x86::OPCODE::ADC8mi8) + .value("ADC8mi_EVEX", LIEF::assembly::x86::OPCODE::ADC8mi_EVEX) + .value("ADC8mi_ND", LIEF::assembly::x86::OPCODE::ADC8mi_ND) + .value("ADC8mr", LIEF::assembly::x86::OPCODE::ADC8mr) + .value("ADC8mr_EVEX", LIEF::assembly::x86::OPCODE::ADC8mr_EVEX) + .value("ADC8mr_ND", LIEF::assembly::x86::OPCODE::ADC8mr_ND) + .value("ADC8ri", LIEF::assembly::x86::OPCODE::ADC8ri) + .value("ADC8ri8", LIEF::assembly::x86::OPCODE::ADC8ri8) + .value("ADC8ri_EVEX", LIEF::assembly::x86::OPCODE::ADC8ri_EVEX) + .value("ADC8ri_ND", LIEF::assembly::x86::OPCODE::ADC8ri_ND) + .value("ADC8rm", LIEF::assembly::x86::OPCODE::ADC8rm) + .value("ADC8rm_EVEX", LIEF::assembly::x86::OPCODE::ADC8rm_EVEX) + .value("ADC8rm_ND", LIEF::assembly::x86::OPCODE::ADC8rm_ND) + .value("ADC8rr", LIEF::assembly::x86::OPCODE::ADC8rr) + .value("ADC8rr_EVEX", LIEF::assembly::x86::OPCODE::ADC8rr_EVEX) + .value("ADC8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADC8rr_EVEX_REV) + .value("ADC8rr_ND", LIEF::assembly::x86::OPCODE::ADC8rr_ND) + .value("ADC8rr_ND_REV", LIEF::assembly::x86::OPCODE::ADC8rr_ND_REV) + .value("ADC8rr_REV", LIEF::assembly::x86::OPCODE::ADC8rr_REV) + .value("ADCX32rm", LIEF::assembly::x86::OPCODE::ADCX32rm) + .value("ADCX32rm_EVEX", LIEF::assembly::x86::OPCODE::ADCX32rm_EVEX) + .value("ADCX32rm_ND", LIEF::assembly::x86::OPCODE::ADCX32rm_ND) + .value("ADCX32rr", LIEF::assembly::x86::OPCODE::ADCX32rr) + .value("ADCX32rr_EVEX", LIEF::assembly::x86::OPCODE::ADCX32rr_EVEX) + .value("ADCX32rr_ND", LIEF::assembly::x86::OPCODE::ADCX32rr_ND) + .value("ADCX64rm", LIEF::assembly::x86::OPCODE::ADCX64rm) + .value("ADCX64rm_EVEX", LIEF::assembly::x86::OPCODE::ADCX64rm_EVEX) + .value("ADCX64rm_ND", LIEF::assembly::x86::OPCODE::ADCX64rm_ND) + .value("ADCX64rr", LIEF::assembly::x86::OPCODE::ADCX64rr) + .value("ADCX64rr_EVEX", LIEF::assembly::x86::OPCODE::ADCX64rr_EVEX) + .value("ADCX64rr_ND", LIEF::assembly::x86::OPCODE::ADCX64rr_ND) + .value("ADD16i16", LIEF::assembly::x86::OPCODE::ADD16i16) + .value("ADD16mi", LIEF::assembly::x86::OPCODE::ADD16mi) + .value("ADD16mi8", LIEF::assembly::x86::OPCODE::ADD16mi8) + .value("ADD16mi8_EVEX", LIEF::assembly::x86::OPCODE::ADD16mi8_EVEX) + .value("ADD16mi8_ND", LIEF::assembly::x86::OPCODE::ADD16mi8_ND) + .value("ADD16mi8_NF", LIEF::assembly::x86::OPCODE::ADD16mi8_NF) + .value("ADD16mi8_NF_ND", LIEF::assembly::x86::OPCODE::ADD16mi8_NF_ND) + .value("ADD16mi_EVEX", LIEF::assembly::x86::OPCODE::ADD16mi_EVEX) + .value("ADD16mi_ND", LIEF::assembly::x86::OPCODE::ADD16mi_ND) + .value("ADD16mi_NF", LIEF::assembly::x86::OPCODE::ADD16mi_NF) + .value("ADD16mi_NF_ND", LIEF::assembly::x86::OPCODE::ADD16mi_NF_ND) + .value("ADD16mr", LIEF::assembly::x86::OPCODE::ADD16mr) + .value("ADD16mr_EVEX", LIEF::assembly::x86::OPCODE::ADD16mr_EVEX) + .value("ADD16mr_ND", LIEF::assembly::x86::OPCODE::ADD16mr_ND) + .value("ADD16mr_NF", LIEF::assembly::x86::OPCODE::ADD16mr_NF) + .value("ADD16mr_NF_ND", LIEF::assembly::x86::OPCODE::ADD16mr_NF_ND) + .value("ADD16ri", LIEF::assembly::x86::OPCODE::ADD16ri) + .value("ADD16ri8", LIEF::assembly::x86::OPCODE::ADD16ri8) + .value("ADD16ri8_EVEX", LIEF::assembly::x86::OPCODE::ADD16ri8_EVEX) + .value("ADD16ri8_ND", LIEF::assembly::x86::OPCODE::ADD16ri8_ND) + .value("ADD16ri8_NF", LIEF::assembly::x86::OPCODE::ADD16ri8_NF) + .value("ADD16ri8_NF_ND", LIEF::assembly::x86::OPCODE::ADD16ri8_NF_ND) + .value("ADD16ri_EVEX", LIEF::assembly::x86::OPCODE::ADD16ri_EVEX) + .value("ADD16ri_ND", LIEF::assembly::x86::OPCODE::ADD16ri_ND) + .value("ADD16ri_NF", LIEF::assembly::x86::OPCODE::ADD16ri_NF) + .value("ADD16ri_NF_ND", LIEF::assembly::x86::OPCODE::ADD16ri_NF_ND) + .value("ADD16rm", LIEF::assembly::x86::OPCODE::ADD16rm) + .value("ADD16rm_EVEX", LIEF::assembly::x86::OPCODE::ADD16rm_EVEX) + .value("ADD16rm_ND", LIEF::assembly::x86::OPCODE::ADD16rm_ND) + .value("ADD16rm_NF", LIEF::assembly::x86::OPCODE::ADD16rm_NF) + .value("ADD16rm_NF_ND", LIEF::assembly::x86::OPCODE::ADD16rm_NF_ND) + .value("ADD16rr", LIEF::assembly::x86::OPCODE::ADD16rr) + .value("ADD16rr_EVEX", LIEF::assembly::x86::OPCODE::ADD16rr_EVEX) + .value("ADD16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADD16rr_EVEX_REV) + .value("ADD16rr_ND", LIEF::assembly::x86::OPCODE::ADD16rr_ND) + .value("ADD16rr_ND_REV", LIEF::assembly::x86::OPCODE::ADD16rr_ND_REV) + .value("ADD16rr_NF", LIEF::assembly::x86::OPCODE::ADD16rr_NF) + .value("ADD16rr_NF_ND", LIEF::assembly::x86::OPCODE::ADD16rr_NF_ND) + .value("ADD16rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::ADD16rr_NF_ND_REV) + .value("ADD16rr_NF_REV", LIEF::assembly::x86::OPCODE::ADD16rr_NF_REV) + .value("ADD16rr_REV", LIEF::assembly::x86::OPCODE::ADD16rr_REV) + .value("ADD32i32", LIEF::assembly::x86::OPCODE::ADD32i32); + opcodes.value("ADD32mi", LIEF::assembly::x86::OPCODE::ADD32mi) + .value("ADD32mi8", LIEF::assembly::x86::OPCODE::ADD32mi8) + .value("ADD32mi8_EVEX", LIEF::assembly::x86::OPCODE::ADD32mi8_EVEX) + .value("ADD32mi8_ND", LIEF::assembly::x86::OPCODE::ADD32mi8_ND) + .value("ADD32mi8_NF", LIEF::assembly::x86::OPCODE::ADD32mi8_NF) + .value("ADD32mi8_NF_ND", LIEF::assembly::x86::OPCODE::ADD32mi8_NF_ND) + .value("ADD32mi_EVEX", LIEF::assembly::x86::OPCODE::ADD32mi_EVEX) + .value("ADD32mi_ND", LIEF::assembly::x86::OPCODE::ADD32mi_ND) + .value("ADD32mi_NF", LIEF::assembly::x86::OPCODE::ADD32mi_NF) + .value("ADD32mi_NF_ND", LIEF::assembly::x86::OPCODE::ADD32mi_NF_ND) + .value("ADD32mr", LIEF::assembly::x86::OPCODE::ADD32mr) + .value("ADD32mr_EVEX", LIEF::assembly::x86::OPCODE::ADD32mr_EVEX) + .value("ADD32mr_ND", LIEF::assembly::x86::OPCODE::ADD32mr_ND) + .value("ADD32mr_NF", LIEF::assembly::x86::OPCODE::ADD32mr_NF) + .value("ADD32mr_NF_ND", LIEF::assembly::x86::OPCODE::ADD32mr_NF_ND) + .value("ADD32ri", LIEF::assembly::x86::OPCODE::ADD32ri) + .value("ADD32ri8", LIEF::assembly::x86::OPCODE::ADD32ri8) + .value("ADD32ri8_EVEX", LIEF::assembly::x86::OPCODE::ADD32ri8_EVEX) + .value("ADD32ri8_ND", LIEF::assembly::x86::OPCODE::ADD32ri8_ND) + .value("ADD32ri8_NF", LIEF::assembly::x86::OPCODE::ADD32ri8_NF) + .value("ADD32ri8_NF_ND", LIEF::assembly::x86::OPCODE::ADD32ri8_NF_ND) + .value("ADD32ri_EVEX", LIEF::assembly::x86::OPCODE::ADD32ri_EVEX) + .value("ADD32ri_ND", LIEF::assembly::x86::OPCODE::ADD32ri_ND) + .value("ADD32ri_NF", LIEF::assembly::x86::OPCODE::ADD32ri_NF) + .value("ADD32ri_NF_ND", LIEF::assembly::x86::OPCODE::ADD32ri_NF_ND) + .value("ADD32rm", LIEF::assembly::x86::OPCODE::ADD32rm) + .value("ADD32rm_EVEX", LIEF::assembly::x86::OPCODE::ADD32rm_EVEX) + .value("ADD32rm_ND", LIEF::assembly::x86::OPCODE::ADD32rm_ND) + .value("ADD32rm_NF", LIEF::assembly::x86::OPCODE::ADD32rm_NF) + .value("ADD32rm_NF_ND", LIEF::assembly::x86::OPCODE::ADD32rm_NF_ND) + .value("ADD32rr", LIEF::assembly::x86::OPCODE::ADD32rr) + .value("ADD32rr_EVEX", LIEF::assembly::x86::OPCODE::ADD32rr_EVEX) + .value("ADD32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADD32rr_EVEX_REV) + .value("ADD32rr_ND", LIEF::assembly::x86::OPCODE::ADD32rr_ND) + .value("ADD32rr_ND_REV", LIEF::assembly::x86::OPCODE::ADD32rr_ND_REV) + .value("ADD32rr_NF", LIEF::assembly::x86::OPCODE::ADD32rr_NF) + .value("ADD32rr_NF_ND", LIEF::assembly::x86::OPCODE::ADD32rr_NF_ND) + .value("ADD32rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::ADD32rr_NF_ND_REV) + .value("ADD32rr_NF_REV", LIEF::assembly::x86::OPCODE::ADD32rr_NF_REV) + .value("ADD32rr_REV", LIEF::assembly::x86::OPCODE::ADD32rr_REV) + .value("ADD64i32", LIEF::assembly::x86::OPCODE::ADD64i32) + .value("ADD64mi32", LIEF::assembly::x86::OPCODE::ADD64mi32) + .value("ADD64mi32_EVEX", LIEF::assembly::x86::OPCODE::ADD64mi32_EVEX) + .value("ADD64mi32_ND", LIEF::assembly::x86::OPCODE::ADD64mi32_ND) + .value("ADD64mi32_NF", LIEF::assembly::x86::OPCODE::ADD64mi32_NF) + .value("ADD64mi32_NF_ND", LIEF::assembly::x86::OPCODE::ADD64mi32_NF_ND) + .value("ADD64mi8", LIEF::assembly::x86::OPCODE::ADD64mi8) + .value("ADD64mi8_EVEX", LIEF::assembly::x86::OPCODE::ADD64mi8_EVEX) + .value("ADD64mi8_ND", LIEF::assembly::x86::OPCODE::ADD64mi8_ND) + .value("ADD64mi8_NF", LIEF::assembly::x86::OPCODE::ADD64mi8_NF) + .value("ADD64mi8_NF_ND", LIEF::assembly::x86::OPCODE::ADD64mi8_NF_ND) + .value("ADD64mr", LIEF::assembly::x86::OPCODE::ADD64mr) + .value("ADD64mr_EVEX", LIEF::assembly::x86::OPCODE::ADD64mr_EVEX) + .value("ADD64mr_ND", LIEF::assembly::x86::OPCODE::ADD64mr_ND) + .value("ADD64mr_NF", LIEF::assembly::x86::OPCODE::ADD64mr_NF) + .value("ADD64mr_NF_ND", LIEF::assembly::x86::OPCODE::ADD64mr_NF_ND) + .value("ADD64ri32", LIEF::assembly::x86::OPCODE::ADD64ri32) + .value("ADD64ri32_EVEX", LIEF::assembly::x86::OPCODE::ADD64ri32_EVEX) + .value("ADD64ri32_ND", LIEF::assembly::x86::OPCODE::ADD64ri32_ND) + .value("ADD64ri32_NF", LIEF::assembly::x86::OPCODE::ADD64ri32_NF) + .value("ADD64ri32_NF_ND", LIEF::assembly::x86::OPCODE::ADD64ri32_NF_ND) + .value("ADD64ri8", LIEF::assembly::x86::OPCODE::ADD64ri8) + .value("ADD64ri8_EVEX", LIEF::assembly::x86::OPCODE::ADD64ri8_EVEX) + .value("ADD64ri8_ND", LIEF::assembly::x86::OPCODE::ADD64ri8_ND) + .value("ADD64ri8_NF", LIEF::assembly::x86::OPCODE::ADD64ri8_NF) + .value("ADD64ri8_NF_ND", LIEF::assembly::x86::OPCODE::ADD64ri8_NF_ND) + .value("ADD64rm", LIEF::assembly::x86::OPCODE::ADD64rm) + .value("ADD64rm_EVEX", LIEF::assembly::x86::OPCODE::ADD64rm_EVEX) + .value("ADD64rm_ND", LIEF::assembly::x86::OPCODE::ADD64rm_ND) + .value("ADD64rm_NF", LIEF::assembly::x86::OPCODE::ADD64rm_NF) + .value("ADD64rm_NF_ND", LIEF::assembly::x86::OPCODE::ADD64rm_NF_ND) + .value("ADD64rr", LIEF::assembly::x86::OPCODE::ADD64rr) + .value("ADD64rr_EVEX", LIEF::assembly::x86::OPCODE::ADD64rr_EVEX) + .value("ADD64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADD64rr_EVEX_REV) + .value("ADD64rr_ND", LIEF::assembly::x86::OPCODE::ADD64rr_ND) + .value("ADD64rr_ND_REV", LIEF::assembly::x86::OPCODE::ADD64rr_ND_REV) + .value("ADD64rr_NF", LIEF::assembly::x86::OPCODE::ADD64rr_NF) + .value("ADD64rr_NF_ND", LIEF::assembly::x86::OPCODE::ADD64rr_NF_ND) + .value("ADD64rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::ADD64rr_NF_ND_REV) + .value("ADD64rr_NF_REV", LIEF::assembly::x86::OPCODE::ADD64rr_NF_REV) + .value("ADD64rr_REV", LIEF::assembly::x86::OPCODE::ADD64rr_REV) + .value("ADD8i8", LIEF::assembly::x86::OPCODE::ADD8i8) + .value("ADD8mi", LIEF::assembly::x86::OPCODE::ADD8mi) + .value("ADD8mi8", LIEF::assembly::x86::OPCODE::ADD8mi8) + .value("ADD8mi_EVEX", LIEF::assembly::x86::OPCODE::ADD8mi_EVEX) + .value("ADD8mi_ND", LIEF::assembly::x86::OPCODE::ADD8mi_ND) + .value("ADD8mi_NF", LIEF::assembly::x86::OPCODE::ADD8mi_NF) + .value("ADD8mi_NF_ND", LIEF::assembly::x86::OPCODE::ADD8mi_NF_ND) + .value("ADD8mr", LIEF::assembly::x86::OPCODE::ADD8mr) + .value("ADD8mr_EVEX", LIEF::assembly::x86::OPCODE::ADD8mr_EVEX) + .value("ADD8mr_ND", LIEF::assembly::x86::OPCODE::ADD8mr_ND) + .value("ADD8mr_NF", LIEF::assembly::x86::OPCODE::ADD8mr_NF) + .value("ADD8mr_NF_ND", LIEF::assembly::x86::OPCODE::ADD8mr_NF_ND) + .value("ADD8ri", LIEF::assembly::x86::OPCODE::ADD8ri) + .value("ADD8ri8", LIEF::assembly::x86::OPCODE::ADD8ri8) + .value("ADD8ri_EVEX", LIEF::assembly::x86::OPCODE::ADD8ri_EVEX) + .value("ADD8ri_ND", LIEF::assembly::x86::OPCODE::ADD8ri_ND) + .value("ADD8ri_NF", LIEF::assembly::x86::OPCODE::ADD8ri_NF) + .value("ADD8ri_NF_ND", LIEF::assembly::x86::OPCODE::ADD8ri_NF_ND) + .value("ADD8rm", LIEF::assembly::x86::OPCODE::ADD8rm) + .value("ADD8rm_EVEX", LIEF::assembly::x86::OPCODE::ADD8rm_EVEX) + .value("ADD8rm_ND", LIEF::assembly::x86::OPCODE::ADD8rm_ND) + .value("ADD8rm_NF", LIEF::assembly::x86::OPCODE::ADD8rm_NF) + .value("ADD8rm_NF_ND", LIEF::assembly::x86::OPCODE::ADD8rm_NF_ND) + .value("ADD8rr", LIEF::assembly::x86::OPCODE::ADD8rr) + .value("ADD8rr_EVEX", LIEF::assembly::x86::OPCODE::ADD8rr_EVEX) + .value("ADD8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::ADD8rr_EVEX_REV) + .value("ADD8rr_ND", LIEF::assembly::x86::OPCODE::ADD8rr_ND) + .value("ADD8rr_ND_REV", LIEF::assembly::x86::OPCODE::ADD8rr_ND_REV) + .value("ADD8rr_NF", LIEF::assembly::x86::OPCODE::ADD8rr_NF) + .value("ADD8rr_NF_ND", LIEF::assembly::x86::OPCODE::ADD8rr_NF_ND) + .value("ADD8rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::ADD8rr_NF_ND_REV) + .value("ADD8rr_NF_REV", LIEF::assembly::x86::OPCODE::ADD8rr_NF_REV) + .value("ADD8rr_REV", LIEF::assembly::x86::OPCODE::ADD8rr_REV) + .value("ADDPDrm", LIEF::assembly::x86::OPCODE::ADDPDrm) + .value("ADDPDrr", LIEF::assembly::x86::OPCODE::ADDPDrr) + .value("ADDPSrm", LIEF::assembly::x86::OPCODE::ADDPSrm) + .value("ADDPSrr", LIEF::assembly::x86::OPCODE::ADDPSrr) + .value("ADDR16_PREFIX", LIEF::assembly::x86::OPCODE::ADDR16_PREFIX) + .value("ADDR32_PREFIX", LIEF::assembly::x86::OPCODE::ADDR32_PREFIX) + .value("ADDSDrm", LIEF::assembly::x86::OPCODE::ADDSDrm) + .value("ADDSDrm_Int", LIEF::assembly::x86::OPCODE::ADDSDrm_Int) + .value("ADDSDrr", LIEF::assembly::x86::OPCODE::ADDSDrr) + .value("ADDSDrr_Int", LIEF::assembly::x86::OPCODE::ADDSDrr_Int) + .value("ADDSSrm", LIEF::assembly::x86::OPCODE::ADDSSrm) + .value("ADDSSrm_Int", LIEF::assembly::x86::OPCODE::ADDSSrm_Int) + .value("ADDSSrr", LIEF::assembly::x86::OPCODE::ADDSSrr) + .value("ADDSSrr_Int", LIEF::assembly::x86::OPCODE::ADDSSrr_Int) + .value("ADDSUBPDrm", LIEF::assembly::x86::OPCODE::ADDSUBPDrm) + .value("ADDSUBPDrr", LIEF::assembly::x86::OPCODE::ADDSUBPDrr) + .value("ADDSUBPSrm", LIEF::assembly::x86::OPCODE::ADDSUBPSrm) + .value("ADDSUBPSrr", LIEF::assembly::x86::OPCODE::ADDSUBPSrr) + .value("ADD_F32m", LIEF::assembly::x86::OPCODE::ADD_F32m) + .value("ADD_F64m", LIEF::assembly::x86::OPCODE::ADD_F64m) + .value("ADD_FI16m", LIEF::assembly::x86::OPCODE::ADD_FI16m) + .value("ADD_FI32m", LIEF::assembly::x86::OPCODE::ADD_FI32m) + .value("ADD_FPrST0", LIEF::assembly::x86::OPCODE::ADD_FPrST0) + .value("ADD_FST0r", LIEF::assembly::x86::OPCODE::ADD_FST0r) + .value("ADD_Fp32", LIEF::assembly::x86::OPCODE::ADD_Fp32) + .value("ADD_Fp32m", LIEF::assembly::x86::OPCODE::ADD_Fp32m) + .value("ADD_Fp64", LIEF::assembly::x86::OPCODE::ADD_Fp64) + .value("ADD_Fp64m", LIEF::assembly::x86::OPCODE::ADD_Fp64m) + .value("ADD_Fp64m32", LIEF::assembly::x86::OPCODE::ADD_Fp64m32) + .value("ADD_Fp80", LIEF::assembly::x86::OPCODE::ADD_Fp80) + .value("ADD_Fp80m32", LIEF::assembly::x86::OPCODE::ADD_Fp80m32) + .value("ADD_Fp80m64", LIEF::assembly::x86::OPCODE::ADD_Fp80m64) + .value("ADD_FpI16m32", LIEF::assembly::x86::OPCODE::ADD_FpI16m32) + .value("ADD_FpI16m64", LIEF::assembly::x86::OPCODE::ADD_FpI16m64) + .value("ADD_FpI16m80", LIEF::assembly::x86::OPCODE::ADD_FpI16m80) + .value("ADD_FpI32m32", LIEF::assembly::x86::OPCODE::ADD_FpI32m32) + .value("ADD_FpI32m64", LIEF::assembly::x86::OPCODE::ADD_FpI32m64) + .value("ADD_FpI32m80", LIEF::assembly::x86::OPCODE::ADD_FpI32m80) + .value("ADD_FrST0", LIEF::assembly::x86::OPCODE::ADD_FrST0) + .value("ADJCALLSTACKDOWN32", LIEF::assembly::x86::OPCODE::ADJCALLSTACKDOWN32) + .value("ADJCALLSTACKDOWN64", LIEF::assembly::x86::OPCODE::ADJCALLSTACKDOWN64) + .value("ADJCALLSTACKUP32", LIEF::assembly::x86::OPCODE::ADJCALLSTACKUP32) + .value("ADJCALLSTACKUP64", LIEF::assembly::x86::OPCODE::ADJCALLSTACKUP64) + .value("ADOX32rm", LIEF::assembly::x86::OPCODE::ADOX32rm) + .value("ADOX32rm_EVEX", LIEF::assembly::x86::OPCODE::ADOX32rm_EVEX) + .value("ADOX32rm_ND", LIEF::assembly::x86::OPCODE::ADOX32rm_ND) + .value("ADOX32rr", LIEF::assembly::x86::OPCODE::ADOX32rr) + .value("ADOX32rr_EVEX", LIEF::assembly::x86::OPCODE::ADOX32rr_EVEX) + .value("ADOX32rr_ND", LIEF::assembly::x86::OPCODE::ADOX32rr_ND) + .value("ADOX64rm", LIEF::assembly::x86::OPCODE::ADOX64rm) + .value("ADOX64rm_EVEX", LIEF::assembly::x86::OPCODE::ADOX64rm_EVEX) + .value("ADOX64rm_ND", LIEF::assembly::x86::OPCODE::ADOX64rm_ND) + .value("ADOX64rr", LIEF::assembly::x86::OPCODE::ADOX64rr) + .value("ADOX64rr_EVEX", LIEF::assembly::x86::OPCODE::ADOX64rr_EVEX) + .value("ADOX64rr_ND", LIEF::assembly::x86::OPCODE::ADOX64rr_ND) + .value("AESDEC128KL", LIEF::assembly::x86::OPCODE::AESDEC128KL) + .value("AESDEC256KL", LIEF::assembly::x86::OPCODE::AESDEC256KL) + .value("AESDECLASTrm", LIEF::assembly::x86::OPCODE::AESDECLASTrm) + .value("AESDECLASTrr", LIEF::assembly::x86::OPCODE::AESDECLASTrr) + .value("AESDECWIDE128KL", LIEF::assembly::x86::OPCODE::AESDECWIDE128KL) + .value("AESDECWIDE256KL", LIEF::assembly::x86::OPCODE::AESDECWIDE256KL) + .value("AESDECrm", LIEF::assembly::x86::OPCODE::AESDECrm) + .value("AESDECrr", LIEF::assembly::x86::OPCODE::AESDECrr) + .value("AESENC128KL", LIEF::assembly::x86::OPCODE::AESENC128KL) + .value("AESENC256KL", LIEF::assembly::x86::OPCODE::AESENC256KL) + .value("AESENCLASTrm", LIEF::assembly::x86::OPCODE::AESENCLASTrm) + .value("AESENCLASTrr", LIEF::assembly::x86::OPCODE::AESENCLASTrr) + .value("AESENCWIDE128KL", LIEF::assembly::x86::OPCODE::AESENCWIDE128KL) + .value("AESENCWIDE256KL", LIEF::assembly::x86::OPCODE::AESENCWIDE256KL) + .value("AESENCrm", LIEF::assembly::x86::OPCODE::AESENCrm) + .value("AESENCrr", LIEF::assembly::x86::OPCODE::AESENCrr) + .value("AESIMCrm", LIEF::assembly::x86::OPCODE::AESIMCrm) + .value("AESIMCrr", LIEF::assembly::x86::OPCODE::AESIMCrr) + .value("AESKEYGENASSISTrmi", LIEF::assembly::x86::OPCODE::AESKEYGENASSISTrmi) + .value("AESKEYGENASSISTrri", LIEF::assembly::x86::OPCODE::AESKEYGENASSISTrri) + .value("AND16i16", LIEF::assembly::x86::OPCODE::AND16i16) + .value("AND16mi", LIEF::assembly::x86::OPCODE::AND16mi) + .value("AND16mi8", LIEF::assembly::x86::OPCODE::AND16mi8) + .value("AND16mi8_EVEX", LIEF::assembly::x86::OPCODE::AND16mi8_EVEX) + .value("AND16mi8_ND", LIEF::assembly::x86::OPCODE::AND16mi8_ND) + .value("AND16mi8_NF", LIEF::assembly::x86::OPCODE::AND16mi8_NF) + .value("AND16mi8_NF_ND", LIEF::assembly::x86::OPCODE::AND16mi8_NF_ND) + .value("AND16mi_EVEX", LIEF::assembly::x86::OPCODE::AND16mi_EVEX) + .value("AND16mi_ND", LIEF::assembly::x86::OPCODE::AND16mi_ND) + .value("AND16mi_NF", LIEF::assembly::x86::OPCODE::AND16mi_NF) + .value("AND16mi_NF_ND", LIEF::assembly::x86::OPCODE::AND16mi_NF_ND) + .value("AND16mr", LIEF::assembly::x86::OPCODE::AND16mr) + .value("AND16mr_EVEX", LIEF::assembly::x86::OPCODE::AND16mr_EVEX) + .value("AND16mr_ND", LIEF::assembly::x86::OPCODE::AND16mr_ND) + .value("AND16mr_NF", LIEF::assembly::x86::OPCODE::AND16mr_NF) + .value("AND16mr_NF_ND", LIEF::assembly::x86::OPCODE::AND16mr_NF_ND) + .value("AND16ri", LIEF::assembly::x86::OPCODE::AND16ri) + .value("AND16ri8", LIEF::assembly::x86::OPCODE::AND16ri8) + .value("AND16ri8_EVEX", LIEF::assembly::x86::OPCODE::AND16ri8_EVEX) + .value("AND16ri8_ND", LIEF::assembly::x86::OPCODE::AND16ri8_ND) + .value("AND16ri8_NF", LIEF::assembly::x86::OPCODE::AND16ri8_NF) + .value("AND16ri8_NF_ND", LIEF::assembly::x86::OPCODE::AND16ri8_NF_ND) + .value("AND16ri_EVEX", LIEF::assembly::x86::OPCODE::AND16ri_EVEX) + .value("AND16ri_ND", LIEF::assembly::x86::OPCODE::AND16ri_ND) + .value("AND16ri_NF", LIEF::assembly::x86::OPCODE::AND16ri_NF) + .value("AND16ri_NF_ND", LIEF::assembly::x86::OPCODE::AND16ri_NF_ND) + .value("AND16rm", LIEF::assembly::x86::OPCODE::AND16rm) + .value("AND16rm_EVEX", LIEF::assembly::x86::OPCODE::AND16rm_EVEX) + .value("AND16rm_ND", LIEF::assembly::x86::OPCODE::AND16rm_ND) + .value("AND16rm_NF", LIEF::assembly::x86::OPCODE::AND16rm_NF) + .value("AND16rm_NF_ND", LIEF::assembly::x86::OPCODE::AND16rm_NF_ND) + .value("AND16rr", LIEF::assembly::x86::OPCODE::AND16rr) + .value("AND16rr_EVEX", LIEF::assembly::x86::OPCODE::AND16rr_EVEX) + .value("AND16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::AND16rr_EVEX_REV) + .value("AND16rr_ND", LIEF::assembly::x86::OPCODE::AND16rr_ND) + .value("AND16rr_ND_REV", LIEF::assembly::x86::OPCODE::AND16rr_ND_REV) + .value("AND16rr_NF", LIEF::assembly::x86::OPCODE::AND16rr_NF) + .value("AND16rr_NF_ND", LIEF::assembly::x86::OPCODE::AND16rr_NF_ND) + .value("AND16rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::AND16rr_NF_ND_REV) + .value("AND16rr_NF_REV", LIEF::assembly::x86::OPCODE::AND16rr_NF_REV) + .value("AND16rr_REV", LIEF::assembly::x86::OPCODE::AND16rr_REV) + .value("AND32i32", LIEF::assembly::x86::OPCODE::AND32i32) + .value("AND32mi", LIEF::assembly::x86::OPCODE::AND32mi) + .value("AND32mi8", LIEF::assembly::x86::OPCODE::AND32mi8) + .value("AND32mi8_EVEX", LIEF::assembly::x86::OPCODE::AND32mi8_EVEX) + .value("AND32mi8_ND", LIEF::assembly::x86::OPCODE::AND32mi8_ND) + .value("AND32mi8_NF", LIEF::assembly::x86::OPCODE::AND32mi8_NF) + .value("AND32mi8_NF_ND", LIEF::assembly::x86::OPCODE::AND32mi8_NF_ND) + .value("AND32mi_EVEX", LIEF::assembly::x86::OPCODE::AND32mi_EVEX) + .value("AND32mi_ND", LIEF::assembly::x86::OPCODE::AND32mi_ND) + .value("AND32mi_NF", LIEF::assembly::x86::OPCODE::AND32mi_NF) + .value("AND32mi_NF_ND", LIEF::assembly::x86::OPCODE::AND32mi_NF_ND) + .value("AND32mr", LIEF::assembly::x86::OPCODE::AND32mr) + .value("AND32mr_EVEX", LIEF::assembly::x86::OPCODE::AND32mr_EVEX) + .value("AND32mr_ND", LIEF::assembly::x86::OPCODE::AND32mr_ND) + .value("AND32mr_NF", LIEF::assembly::x86::OPCODE::AND32mr_NF) + .value("AND32mr_NF_ND", LIEF::assembly::x86::OPCODE::AND32mr_NF_ND) + .value("AND32ri", LIEF::assembly::x86::OPCODE::AND32ri) + .value("AND32ri8", LIEF::assembly::x86::OPCODE::AND32ri8) + .value("AND32ri8_EVEX", LIEF::assembly::x86::OPCODE::AND32ri8_EVEX) + .value("AND32ri8_ND", LIEF::assembly::x86::OPCODE::AND32ri8_ND) + .value("AND32ri8_NF", LIEF::assembly::x86::OPCODE::AND32ri8_NF) + .value("AND32ri8_NF_ND", LIEF::assembly::x86::OPCODE::AND32ri8_NF_ND) + .value("AND32ri_EVEX", LIEF::assembly::x86::OPCODE::AND32ri_EVEX) + .value("AND32ri_ND", LIEF::assembly::x86::OPCODE::AND32ri_ND) + .value("AND32ri_NF", LIEF::assembly::x86::OPCODE::AND32ri_NF) + .value("AND32ri_NF_ND", LIEF::assembly::x86::OPCODE::AND32ri_NF_ND) + .value("AND32rm", LIEF::assembly::x86::OPCODE::AND32rm) + .value("AND32rm_EVEX", LIEF::assembly::x86::OPCODE::AND32rm_EVEX) + .value("AND32rm_ND", LIEF::assembly::x86::OPCODE::AND32rm_ND) + .value("AND32rm_NF", LIEF::assembly::x86::OPCODE::AND32rm_NF) + .value("AND32rm_NF_ND", LIEF::assembly::x86::OPCODE::AND32rm_NF_ND) + .value("AND32rr", LIEF::assembly::x86::OPCODE::AND32rr) + .value("AND32rr_EVEX", LIEF::assembly::x86::OPCODE::AND32rr_EVEX) + .value("AND32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::AND32rr_EVEX_REV) + .value("AND32rr_ND", LIEF::assembly::x86::OPCODE::AND32rr_ND) + .value("AND32rr_ND_REV", LIEF::assembly::x86::OPCODE::AND32rr_ND_REV) + .value("AND32rr_NF", LIEF::assembly::x86::OPCODE::AND32rr_NF) + .value("AND32rr_NF_ND", LIEF::assembly::x86::OPCODE::AND32rr_NF_ND) + .value("AND32rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::AND32rr_NF_ND_REV) + .value("AND32rr_NF_REV", LIEF::assembly::x86::OPCODE::AND32rr_NF_REV) + .value("AND32rr_REV", LIEF::assembly::x86::OPCODE::AND32rr_REV) + .value("AND64i32", LIEF::assembly::x86::OPCODE::AND64i32) + .value("AND64mi32", LIEF::assembly::x86::OPCODE::AND64mi32) + .value("AND64mi32_EVEX", LIEF::assembly::x86::OPCODE::AND64mi32_EVEX) + .value("AND64mi32_ND", LIEF::assembly::x86::OPCODE::AND64mi32_ND) + .value("AND64mi32_NF", LIEF::assembly::x86::OPCODE::AND64mi32_NF) + .value("AND64mi32_NF_ND", LIEF::assembly::x86::OPCODE::AND64mi32_NF_ND) + .value("AND64mi8", LIEF::assembly::x86::OPCODE::AND64mi8) + .value("AND64mi8_EVEX", LIEF::assembly::x86::OPCODE::AND64mi8_EVEX) + .value("AND64mi8_ND", LIEF::assembly::x86::OPCODE::AND64mi8_ND) + .value("AND64mi8_NF", LIEF::assembly::x86::OPCODE::AND64mi8_NF) + .value("AND64mi8_NF_ND", LIEF::assembly::x86::OPCODE::AND64mi8_NF_ND) + .value("AND64mr", LIEF::assembly::x86::OPCODE::AND64mr) + .value("AND64mr_EVEX", LIEF::assembly::x86::OPCODE::AND64mr_EVEX) + .value("AND64mr_ND", LIEF::assembly::x86::OPCODE::AND64mr_ND) + .value("AND64mr_NF", LIEF::assembly::x86::OPCODE::AND64mr_NF) + .value("AND64mr_NF_ND", LIEF::assembly::x86::OPCODE::AND64mr_NF_ND) + .value("AND64ri32", LIEF::assembly::x86::OPCODE::AND64ri32) + .value("AND64ri32_EVEX", LIEF::assembly::x86::OPCODE::AND64ri32_EVEX) + .value("AND64ri32_ND", LIEF::assembly::x86::OPCODE::AND64ri32_ND) + .value("AND64ri32_NF", LIEF::assembly::x86::OPCODE::AND64ri32_NF) + .value("AND64ri32_NF_ND", LIEF::assembly::x86::OPCODE::AND64ri32_NF_ND) + .value("AND64ri8", LIEF::assembly::x86::OPCODE::AND64ri8) + .value("AND64ri8_EVEX", LIEF::assembly::x86::OPCODE::AND64ri8_EVEX) + .value("AND64ri8_ND", LIEF::assembly::x86::OPCODE::AND64ri8_ND) + .value("AND64ri8_NF", LIEF::assembly::x86::OPCODE::AND64ri8_NF) + .value("AND64ri8_NF_ND", LIEF::assembly::x86::OPCODE::AND64ri8_NF_ND) + .value("AND64rm", LIEF::assembly::x86::OPCODE::AND64rm) + .value("AND64rm_EVEX", LIEF::assembly::x86::OPCODE::AND64rm_EVEX) + .value("AND64rm_ND", LIEF::assembly::x86::OPCODE::AND64rm_ND); + opcodes.value("AND64rm_NF", LIEF::assembly::x86::OPCODE::AND64rm_NF) + .value("AND64rm_NF_ND", LIEF::assembly::x86::OPCODE::AND64rm_NF_ND) + .value("AND64rr", LIEF::assembly::x86::OPCODE::AND64rr) + .value("AND64rr_EVEX", LIEF::assembly::x86::OPCODE::AND64rr_EVEX) + .value("AND64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::AND64rr_EVEX_REV) + .value("AND64rr_ND", LIEF::assembly::x86::OPCODE::AND64rr_ND) + .value("AND64rr_ND_REV", LIEF::assembly::x86::OPCODE::AND64rr_ND_REV) + .value("AND64rr_NF", LIEF::assembly::x86::OPCODE::AND64rr_NF) + .value("AND64rr_NF_ND", LIEF::assembly::x86::OPCODE::AND64rr_NF_ND) + .value("AND64rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::AND64rr_NF_ND_REV) + .value("AND64rr_NF_REV", LIEF::assembly::x86::OPCODE::AND64rr_NF_REV) + .value("AND64rr_REV", LIEF::assembly::x86::OPCODE::AND64rr_REV) + .value("AND8i8", LIEF::assembly::x86::OPCODE::AND8i8) + .value("AND8mi", LIEF::assembly::x86::OPCODE::AND8mi) + .value("AND8mi8", LIEF::assembly::x86::OPCODE::AND8mi8) + .value("AND8mi_EVEX", LIEF::assembly::x86::OPCODE::AND8mi_EVEX) + .value("AND8mi_ND", LIEF::assembly::x86::OPCODE::AND8mi_ND) + .value("AND8mi_NF", LIEF::assembly::x86::OPCODE::AND8mi_NF) + .value("AND8mi_NF_ND", LIEF::assembly::x86::OPCODE::AND8mi_NF_ND) + .value("AND8mr", LIEF::assembly::x86::OPCODE::AND8mr) + .value("AND8mr_EVEX", LIEF::assembly::x86::OPCODE::AND8mr_EVEX) + .value("AND8mr_ND", LIEF::assembly::x86::OPCODE::AND8mr_ND) + .value("AND8mr_NF", LIEF::assembly::x86::OPCODE::AND8mr_NF) + .value("AND8mr_NF_ND", LIEF::assembly::x86::OPCODE::AND8mr_NF_ND) + .value("AND8ri", LIEF::assembly::x86::OPCODE::AND8ri) + .value("AND8ri8", LIEF::assembly::x86::OPCODE::AND8ri8) + .value("AND8ri_EVEX", LIEF::assembly::x86::OPCODE::AND8ri_EVEX) + .value("AND8ri_ND", LIEF::assembly::x86::OPCODE::AND8ri_ND) + .value("AND8ri_NF", LIEF::assembly::x86::OPCODE::AND8ri_NF) + .value("AND8ri_NF_ND", LIEF::assembly::x86::OPCODE::AND8ri_NF_ND) + .value("AND8rm", LIEF::assembly::x86::OPCODE::AND8rm) + .value("AND8rm_EVEX", LIEF::assembly::x86::OPCODE::AND8rm_EVEX) + .value("AND8rm_ND", LIEF::assembly::x86::OPCODE::AND8rm_ND) + .value("AND8rm_NF", LIEF::assembly::x86::OPCODE::AND8rm_NF) + .value("AND8rm_NF_ND", LIEF::assembly::x86::OPCODE::AND8rm_NF_ND) + .value("AND8rr", LIEF::assembly::x86::OPCODE::AND8rr) + .value("AND8rr_EVEX", LIEF::assembly::x86::OPCODE::AND8rr_EVEX) + .value("AND8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::AND8rr_EVEX_REV) + .value("AND8rr_ND", LIEF::assembly::x86::OPCODE::AND8rr_ND) + .value("AND8rr_ND_REV", LIEF::assembly::x86::OPCODE::AND8rr_ND_REV) + .value("AND8rr_NF", LIEF::assembly::x86::OPCODE::AND8rr_NF) + .value("AND8rr_NF_ND", LIEF::assembly::x86::OPCODE::AND8rr_NF_ND) + .value("AND8rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::AND8rr_NF_ND_REV) + .value("AND8rr_NF_REV", LIEF::assembly::x86::OPCODE::AND8rr_NF_REV) + .value("AND8rr_REV", LIEF::assembly::x86::OPCODE::AND8rr_REV) + .value("ANDN32rm", LIEF::assembly::x86::OPCODE::ANDN32rm) + .value("ANDN32rm_EVEX", LIEF::assembly::x86::OPCODE::ANDN32rm_EVEX) + .value("ANDN32rm_NF", LIEF::assembly::x86::OPCODE::ANDN32rm_NF) + .value("ANDN32rr", LIEF::assembly::x86::OPCODE::ANDN32rr) + .value("ANDN32rr_EVEX", LIEF::assembly::x86::OPCODE::ANDN32rr_EVEX) + .value("ANDN32rr_NF", LIEF::assembly::x86::OPCODE::ANDN32rr_NF) + .value("ANDN64rm", LIEF::assembly::x86::OPCODE::ANDN64rm) + .value("ANDN64rm_EVEX", LIEF::assembly::x86::OPCODE::ANDN64rm_EVEX) + .value("ANDN64rm_NF", LIEF::assembly::x86::OPCODE::ANDN64rm_NF) + .value("ANDN64rr", LIEF::assembly::x86::OPCODE::ANDN64rr) + .value("ANDN64rr_EVEX", LIEF::assembly::x86::OPCODE::ANDN64rr_EVEX) + .value("ANDN64rr_NF", LIEF::assembly::x86::OPCODE::ANDN64rr_NF) + .value("ANDNPDrm", LIEF::assembly::x86::OPCODE::ANDNPDrm) + .value("ANDNPDrr", LIEF::assembly::x86::OPCODE::ANDNPDrr) + .value("ANDNPSrm", LIEF::assembly::x86::OPCODE::ANDNPSrm) + .value("ANDNPSrr", LIEF::assembly::x86::OPCODE::ANDNPSrr) + .value("ANDPDrm", LIEF::assembly::x86::OPCODE::ANDPDrm) + .value("ANDPDrr", LIEF::assembly::x86::OPCODE::ANDPDrr) + .value("ANDPSrm", LIEF::assembly::x86::OPCODE::ANDPSrm) + .value("ANDPSrr", LIEF::assembly::x86::OPCODE::ANDPSrr) + .value("AOR32mr", LIEF::assembly::x86::OPCODE::AOR32mr) + .value("AOR32mr_EVEX", LIEF::assembly::x86::OPCODE::AOR32mr_EVEX) + .value("AOR64mr", LIEF::assembly::x86::OPCODE::AOR64mr) + .value("AOR64mr_EVEX", LIEF::assembly::x86::OPCODE::AOR64mr_EVEX) + .value("ARPL16mr", LIEF::assembly::x86::OPCODE::ARPL16mr) + .value("ARPL16rr", LIEF::assembly::x86::OPCODE::ARPL16rr) + .value("ASAN_CHECK_MEMACCESS", LIEF::assembly::x86::OPCODE::ASAN_CHECK_MEMACCESS) + .value("AXOR32mr", LIEF::assembly::x86::OPCODE::AXOR32mr) + .value("AXOR32mr_EVEX", LIEF::assembly::x86::OPCODE::AXOR32mr_EVEX) + .value("AXOR64mr", LIEF::assembly::x86::OPCODE::AXOR64mr) + .value("AXOR64mr_EVEX", LIEF::assembly::x86::OPCODE::AXOR64mr_EVEX) + .value("BEXTR32rm", LIEF::assembly::x86::OPCODE::BEXTR32rm) + .value("BEXTR32rm_EVEX", LIEF::assembly::x86::OPCODE::BEXTR32rm_EVEX) + .value("BEXTR32rm_NF", LIEF::assembly::x86::OPCODE::BEXTR32rm_NF) + .value("BEXTR32rr", LIEF::assembly::x86::OPCODE::BEXTR32rr) + .value("BEXTR32rr_EVEX", LIEF::assembly::x86::OPCODE::BEXTR32rr_EVEX) + .value("BEXTR32rr_NF", LIEF::assembly::x86::OPCODE::BEXTR32rr_NF) + .value("BEXTR64rm", LIEF::assembly::x86::OPCODE::BEXTR64rm) + .value("BEXTR64rm_EVEX", LIEF::assembly::x86::OPCODE::BEXTR64rm_EVEX) + .value("BEXTR64rm_NF", LIEF::assembly::x86::OPCODE::BEXTR64rm_NF) + .value("BEXTR64rr", LIEF::assembly::x86::OPCODE::BEXTR64rr) + .value("BEXTR64rr_EVEX", LIEF::assembly::x86::OPCODE::BEXTR64rr_EVEX) + .value("BEXTR64rr_NF", LIEF::assembly::x86::OPCODE::BEXTR64rr_NF) + .value("BEXTRI32mi", LIEF::assembly::x86::OPCODE::BEXTRI32mi) + .value("BEXTRI32ri", LIEF::assembly::x86::OPCODE::BEXTRI32ri) + .value("BEXTRI64mi", LIEF::assembly::x86::OPCODE::BEXTRI64mi) + .value("BEXTRI64ri", LIEF::assembly::x86::OPCODE::BEXTRI64ri) + .value("BLCFILL32rm", LIEF::assembly::x86::OPCODE::BLCFILL32rm) + .value("BLCFILL32rr", LIEF::assembly::x86::OPCODE::BLCFILL32rr) + .value("BLCFILL64rm", LIEF::assembly::x86::OPCODE::BLCFILL64rm) + .value("BLCFILL64rr", LIEF::assembly::x86::OPCODE::BLCFILL64rr) + .value("BLCI32rm", LIEF::assembly::x86::OPCODE::BLCI32rm) + .value("BLCI32rr", LIEF::assembly::x86::OPCODE::BLCI32rr) + .value("BLCI64rm", LIEF::assembly::x86::OPCODE::BLCI64rm) + .value("BLCI64rr", LIEF::assembly::x86::OPCODE::BLCI64rr) + .value("BLCIC32rm", LIEF::assembly::x86::OPCODE::BLCIC32rm) + .value("BLCIC32rr", LIEF::assembly::x86::OPCODE::BLCIC32rr) + .value("BLCIC64rm", LIEF::assembly::x86::OPCODE::BLCIC64rm) + .value("BLCIC64rr", LIEF::assembly::x86::OPCODE::BLCIC64rr) + .value("BLCMSK32rm", LIEF::assembly::x86::OPCODE::BLCMSK32rm) + .value("BLCMSK32rr", LIEF::assembly::x86::OPCODE::BLCMSK32rr) + .value("BLCMSK64rm", LIEF::assembly::x86::OPCODE::BLCMSK64rm) + .value("BLCMSK64rr", LIEF::assembly::x86::OPCODE::BLCMSK64rr) + .value("BLCS32rm", LIEF::assembly::x86::OPCODE::BLCS32rm) + .value("BLCS32rr", LIEF::assembly::x86::OPCODE::BLCS32rr) + .value("BLCS64rm", LIEF::assembly::x86::OPCODE::BLCS64rm) + .value("BLCS64rr", LIEF::assembly::x86::OPCODE::BLCS64rr) + .value("BLENDPDrmi", LIEF::assembly::x86::OPCODE::BLENDPDrmi) + .value("BLENDPDrri", LIEF::assembly::x86::OPCODE::BLENDPDrri) + .value("BLENDPSrmi", LIEF::assembly::x86::OPCODE::BLENDPSrmi) + .value("BLENDPSrri", LIEF::assembly::x86::OPCODE::BLENDPSrri) + .value("BLENDVPDrm0", LIEF::assembly::x86::OPCODE::BLENDVPDrm0) + .value("BLENDVPDrr0", LIEF::assembly::x86::OPCODE::BLENDVPDrr0) + .value("BLENDVPSrm0", LIEF::assembly::x86::OPCODE::BLENDVPSrm0) + .value("BLENDVPSrr0", LIEF::assembly::x86::OPCODE::BLENDVPSrr0) + .value("BLSFILL32rm", LIEF::assembly::x86::OPCODE::BLSFILL32rm) + .value("BLSFILL32rr", LIEF::assembly::x86::OPCODE::BLSFILL32rr) + .value("BLSFILL64rm", LIEF::assembly::x86::OPCODE::BLSFILL64rm) + .value("BLSFILL64rr", LIEF::assembly::x86::OPCODE::BLSFILL64rr) + .value("BLSI32rm", LIEF::assembly::x86::OPCODE::BLSI32rm) + .value("BLSI32rm_EVEX", LIEF::assembly::x86::OPCODE::BLSI32rm_EVEX) + .value("BLSI32rm_NF", LIEF::assembly::x86::OPCODE::BLSI32rm_NF) + .value("BLSI32rr", LIEF::assembly::x86::OPCODE::BLSI32rr) + .value("BLSI32rr_EVEX", LIEF::assembly::x86::OPCODE::BLSI32rr_EVEX) + .value("BLSI32rr_NF", LIEF::assembly::x86::OPCODE::BLSI32rr_NF) + .value("BLSI64rm", LIEF::assembly::x86::OPCODE::BLSI64rm) + .value("BLSI64rm_EVEX", LIEF::assembly::x86::OPCODE::BLSI64rm_EVEX) + .value("BLSI64rm_NF", LIEF::assembly::x86::OPCODE::BLSI64rm_NF) + .value("BLSI64rr", LIEF::assembly::x86::OPCODE::BLSI64rr) + .value("BLSI64rr_EVEX", LIEF::assembly::x86::OPCODE::BLSI64rr_EVEX) + .value("BLSI64rr_NF", LIEF::assembly::x86::OPCODE::BLSI64rr_NF) + .value("BLSIC32rm", LIEF::assembly::x86::OPCODE::BLSIC32rm) + .value("BLSIC32rr", LIEF::assembly::x86::OPCODE::BLSIC32rr) + .value("BLSIC64rm", LIEF::assembly::x86::OPCODE::BLSIC64rm) + .value("BLSIC64rr", LIEF::assembly::x86::OPCODE::BLSIC64rr) + .value("BLSMSK32rm", LIEF::assembly::x86::OPCODE::BLSMSK32rm) + .value("BLSMSK32rm_EVEX", LIEF::assembly::x86::OPCODE::BLSMSK32rm_EVEX) + .value("BLSMSK32rm_NF", LIEF::assembly::x86::OPCODE::BLSMSK32rm_NF) + .value("BLSMSK32rr", LIEF::assembly::x86::OPCODE::BLSMSK32rr) + .value("BLSMSK32rr_EVEX", LIEF::assembly::x86::OPCODE::BLSMSK32rr_EVEX) + .value("BLSMSK32rr_NF", LIEF::assembly::x86::OPCODE::BLSMSK32rr_NF) + .value("BLSMSK64rm", LIEF::assembly::x86::OPCODE::BLSMSK64rm) + .value("BLSMSK64rm_EVEX", LIEF::assembly::x86::OPCODE::BLSMSK64rm_EVEX) + .value("BLSMSK64rm_NF", LIEF::assembly::x86::OPCODE::BLSMSK64rm_NF) + .value("BLSMSK64rr", LIEF::assembly::x86::OPCODE::BLSMSK64rr) + .value("BLSMSK64rr_EVEX", LIEF::assembly::x86::OPCODE::BLSMSK64rr_EVEX) + .value("BLSMSK64rr_NF", LIEF::assembly::x86::OPCODE::BLSMSK64rr_NF) + .value("BLSR32rm", LIEF::assembly::x86::OPCODE::BLSR32rm) + .value("BLSR32rm_EVEX", LIEF::assembly::x86::OPCODE::BLSR32rm_EVEX) + .value("BLSR32rm_NF", LIEF::assembly::x86::OPCODE::BLSR32rm_NF) + .value("BLSR32rr", LIEF::assembly::x86::OPCODE::BLSR32rr) + .value("BLSR32rr_EVEX", LIEF::assembly::x86::OPCODE::BLSR32rr_EVEX) + .value("BLSR32rr_NF", LIEF::assembly::x86::OPCODE::BLSR32rr_NF) + .value("BLSR64rm", LIEF::assembly::x86::OPCODE::BLSR64rm) + .value("BLSR64rm_EVEX", LIEF::assembly::x86::OPCODE::BLSR64rm_EVEX) + .value("BLSR64rm_NF", LIEF::assembly::x86::OPCODE::BLSR64rm_NF) + .value("BLSR64rr", LIEF::assembly::x86::OPCODE::BLSR64rr) + .value("BLSR64rr_EVEX", LIEF::assembly::x86::OPCODE::BLSR64rr_EVEX) + .value("BLSR64rr_NF", LIEF::assembly::x86::OPCODE::BLSR64rr_NF) + .value("BOUNDS16rm", LIEF::assembly::x86::OPCODE::BOUNDS16rm) + .value("BOUNDS32rm", LIEF::assembly::x86::OPCODE::BOUNDS32rm) + .value("BSF16rm", LIEF::assembly::x86::OPCODE::BSF16rm) + .value("BSF16rr", LIEF::assembly::x86::OPCODE::BSF16rr) + .value("BSF32rm", LIEF::assembly::x86::OPCODE::BSF32rm) + .value("BSF32rr", LIEF::assembly::x86::OPCODE::BSF32rr) + .value("BSF64rm", LIEF::assembly::x86::OPCODE::BSF64rm) + .value("BSF64rr", LIEF::assembly::x86::OPCODE::BSF64rr) + .value("BSR16rm", LIEF::assembly::x86::OPCODE::BSR16rm) + .value("BSR16rr", LIEF::assembly::x86::OPCODE::BSR16rr) + .value("BSR32rm", LIEF::assembly::x86::OPCODE::BSR32rm) + .value("BSR32rr", LIEF::assembly::x86::OPCODE::BSR32rr) + .value("BSR64rm", LIEF::assembly::x86::OPCODE::BSR64rm) + .value("BSR64rr", LIEF::assembly::x86::OPCODE::BSR64rr) + .value("BSWAP16r_BAD", LIEF::assembly::x86::OPCODE::BSWAP16r_BAD) + .value("BSWAP32r", LIEF::assembly::x86::OPCODE::BSWAP32r) + .value("BSWAP64r", LIEF::assembly::x86::OPCODE::BSWAP64r) + .value("BT16mi8", LIEF::assembly::x86::OPCODE::BT16mi8) + .value("BT16mr", LIEF::assembly::x86::OPCODE::BT16mr) + .value("BT16ri8", LIEF::assembly::x86::OPCODE::BT16ri8) + .value("BT16rr", LIEF::assembly::x86::OPCODE::BT16rr) + .value("BT32mi8", LIEF::assembly::x86::OPCODE::BT32mi8) + .value("BT32mr", LIEF::assembly::x86::OPCODE::BT32mr) + .value("BT32ri8", LIEF::assembly::x86::OPCODE::BT32ri8) + .value("BT32rr", LIEF::assembly::x86::OPCODE::BT32rr) + .value("BT64mi8", LIEF::assembly::x86::OPCODE::BT64mi8) + .value("BT64mr", LIEF::assembly::x86::OPCODE::BT64mr) + .value("BT64ri8", LIEF::assembly::x86::OPCODE::BT64ri8) + .value("BT64rr", LIEF::assembly::x86::OPCODE::BT64rr) + .value("BTC16mi8", LIEF::assembly::x86::OPCODE::BTC16mi8) + .value("BTC16mr", LIEF::assembly::x86::OPCODE::BTC16mr) + .value("BTC16ri8", LIEF::assembly::x86::OPCODE::BTC16ri8) + .value("BTC16rr", LIEF::assembly::x86::OPCODE::BTC16rr) + .value("BTC32mi8", LIEF::assembly::x86::OPCODE::BTC32mi8) + .value("BTC32mr", LIEF::assembly::x86::OPCODE::BTC32mr) + .value("BTC32ri8", LIEF::assembly::x86::OPCODE::BTC32ri8) + .value("BTC32rr", LIEF::assembly::x86::OPCODE::BTC32rr) + .value("BTC64mi8", LIEF::assembly::x86::OPCODE::BTC64mi8) + .value("BTC64mr", LIEF::assembly::x86::OPCODE::BTC64mr) + .value("BTC64ri8", LIEF::assembly::x86::OPCODE::BTC64ri8) + .value("BTC64rr", LIEF::assembly::x86::OPCODE::BTC64rr) + .value("BTR16mi8", LIEF::assembly::x86::OPCODE::BTR16mi8) + .value("BTR16mr", LIEF::assembly::x86::OPCODE::BTR16mr) + .value("BTR16ri8", LIEF::assembly::x86::OPCODE::BTR16ri8) + .value("BTR16rr", LIEF::assembly::x86::OPCODE::BTR16rr) + .value("BTR32mi8", LIEF::assembly::x86::OPCODE::BTR32mi8) + .value("BTR32mr", LIEF::assembly::x86::OPCODE::BTR32mr) + .value("BTR32ri8", LIEF::assembly::x86::OPCODE::BTR32ri8) + .value("BTR32rr", LIEF::assembly::x86::OPCODE::BTR32rr) + .value("BTR64mi8", LIEF::assembly::x86::OPCODE::BTR64mi8) + .value("BTR64mr", LIEF::assembly::x86::OPCODE::BTR64mr) + .value("BTR64ri8", LIEF::assembly::x86::OPCODE::BTR64ri8) + .value("BTR64rr", LIEF::assembly::x86::OPCODE::BTR64rr) + .value("BTS16mi8", LIEF::assembly::x86::OPCODE::BTS16mi8) + .value("BTS16mr", LIEF::assembly::x86::OPCODE::BTS16mr) + .value("BTS16ri8", LIEF::assembly::x86::OPCODE::BTS16ri8) + .value("BTS16rr", LIEF::assembly::x86::OPCODE::BTS16rr) + .value("BTS32mi8", LIEF::assembly::x86::OPCODE::BTS32mi8) + .value("BTS32mr", LIEF::assembly::x86::OPCODE::BTS32mr) + .value("BTS32ri8", LIEF::assembly::x86::OPCODE::BTS32ri8) + .value("BTS32rr", LIEF::assembly::x86::OPCODE::BTS32rr) + .value("BTS64mi8", LIEF::assembly::x86::OPCODE::BTS64mi8) + .value("BTS64mr", LIEF::assembly::x86::OPCODE::BTS64mr) + .value("BTS64ri8", LIEF::assembly::x86::OPCODE::BTS64ri8) + .value("BTS64rr", LIEF::assembly::x86::OPCODE::BTS64rr) + .value("BZHI32rm", LIEF::assembly::x86::OPCODE::BZHI32rm) + .value("BZHI32rm_EVEX", LIEF::assembly::x86::OPCODE::BZHI32rm_EVEX) + .value("BZHI32rm_NF", LIEF::assembly::x86::OPCODE::BZHI32rm_NF) + .value("BZHI32rr", LIEF::assembly::x86::OPCODE::BZHI32rr) + .value("BZHI32rr_EVEX", LIEF::assembly::x86::OPCODE::BZHI32rr_EVEX) + .value("BZHI32rr_NF", LIEF::assembly::x86::OPCODE::BZHI32rr_NF) + .value("BZHI64rm", LIEF::assembly::x86::OPCODE::BZHI64rm) + .value("BZHI64rm_EVEX", LIEF::assembly::x86::OPCODE::BZHI64rm_EVEX) + .value("BZHI64rm_NF", LIEF::assembly::x86::OPCODE::BZHI64rm_NF) + .value("BZHI64rr", LIEF::assembly::x86::OPCODE::BZHI64rr) + .value("BZHI64rr_EVEX", LIEF::assembly::x86::OPCODE::BZHI64rr_EVEX) + .value("BZHI64rr_NF", LIEF::assembly::x86::OPCODE::BZHI64rr_NF) + .value("CALL16m", LIEF::assembly::x86::OPCODE::CALL16m) + .value("CALL16m_NT", LIEF::assembly::x86::OPCODE::CALL16m_NT) + .value("CALL16r", LIEF::assembly::x86::OPCODE::CALL16r) + .value("CALL16r_NT", LIEF::assembly::x86::OPCODE::CALL16r_NT) + .value("CALL32m", LIEF::assembly::x86::OPCODE::CALL32m) + .value("CALL32m_NT", LIEF::assembly::x86::OPCODE::CALL32m_NT) + .value("CALL32r", LIEF::assembly::x86::OPCODE::CALL32r) + .value("CALL32r_NT", LIEF::assembly::x86::OPCODE::CALL32r_NT) + .value("CALL64m", LIEF::assembly::x86::OPCODE::CALL64m) + .value("CALL64m_NT", LIEF::assembly::x86::OPCODE::CALL64m_NT) + .value("CALL64pcrel32", LIEF::assembly::x86::OPCODE::CALL64pcrel32) + .value("CALL64r", LIEF::assembly::x86::OPCODE::CALL64r) + .value("CALL64r_NT", LIEF::assembly::x86::OPCODE::CALL64r_NT) + .value("CALLpcrel16", LIEF::assembly::x86::OPCODE::CALLpcrel16) + .value("CALLpcrel32", LIEF::assembly::x86::OPCODE::CALLpcrel32) + .value("CATCHRET", LIEF::assembly::x86::OPCODE::CATCHRET) + .value("CBW", LIEF::assembly::x86::OPCODE::CBW) + .value("CCMP16mi", LIEF::assembly::x86::OPCODE::CCMP16mi) + .value("CCMP16mi8", LIEF::assembly::x86::OPCODE::CCMP16mi8) + .value("CCMP16mr", LIEF::assembly::x86::OPCODE::CCMP16mr) + .value("CCMP16ri", LIEF::assembly::x86::OPCODE::CCMP16ri) + .value("CCMP16ri8", LIEF::assembly::x86::OPCODE::CCMP16ri8) + .value("CCMP16rm", LIEF::assembly::x86::OPCODE::CCMP16rm) + .value("CCMP16rr", LIEF::assembly::x86::OPCODE::CCMP16rr) + .value("CCMP16rr_REV", LIEF::assembly::x86::OPCODE::CCMP16rr_REV) + .value("CCMP32mi", LIEF::assembly::x86::OPCODE::CCMP32mi) + .value("CCMP32mi8", LIEF::assembly::x86::OPCODE::CCMP32mi8) + .value("CCMP32mr", LIEF::assembly::x86::OPCODE::CCMP32mr) + .value("CCMP32ri", LIEF::assembly::x86::OPCODE::CCMP32ri) + .value("CCMP32ri8", LIEF::assembly::x86::OPCODE::CCMP32ri8) + .value("CCMP32rm", LIEF::assembly::x86::OPCODE::CCMP32rm) + .value("CCMP32rr", LIEF::assembly::x86::OPCODE::CCMP32rr) + .value("CCMP32rr_REV", LIEF::assembly::x86::OPCODE::CCMP32rr_REV) + .value("CCMP64mi32", LIEF::assembly::x86::OPCODE::CCMP64mi32) + .value("CCMP64mi8", LIEF::assembly::x86::OPCODE::CCMP64mi8) + .value("CCMP64mr", LIEF::assembly::x86::OPCODE::CCMP64mr) + .value("CCMP64ri32", LIEF::assembly::x86::OPCODE::CCMP64ri32) + .value("CCMP64ri8", LIEF::assembly::x86::OPCODE::CCMP64ri8) + .value("CCMP64rm", LIEF::assembly::x86::OPCODE::CCMP64rm) + .value("CCMP64rr", LIEF::assembly::x86::OPCODE::CCMP64rr) + .value("CCMP64rr_REV", LIEF::assembly::x86::OPCODE::CCMP64rr_REV) + .value("CCMP8mi", LIEF::assembly::x86::OPCODE::CCMP8mi) + .value("CCMP8mr", LIEF::assembly::x86::OPCODE::CCMP8mr) + .value("CCMP8ri", LIEF::assembly::x86::OPCODE::CCMP8ri) + .value("CCMP8rm", LIEF::assembly::x86::OPCODE::CCMP8rm) + .value("CCMP8rr", LIEF::assembly::x86::OPCODE::CCMP8rr) + .value("CCMP8rr_REV", LIEF::assembly::x86::OPCODE::CCMP8rr_REV) + .value("CDQ", LIEF::assembly::x86::OPCODE::CDQ) + .value("CDQE", LIEF::assembly::x86::OPCODE::CDQE) + .value("CFCMOV16mr", LIEF::assembly::x86::OPCODE::CFCMOV16mr) + .value("CFCMOV16rm", LIEF::assembly::x86::OPCODE::CFCMOV16rm) + .value("CFCMOV16rm_ND", LIEF::assembly::x86::OPCODE::CFCMOV16rm_ND) + .value("CFCMOV16rr", LIEF::assembly::x86::OPCODE::CFCMOV16rr) + .value("CFCMOV16rr_ND", LIEF::assembly::x86::OPCODE::CFCMOV16rr_ND) + .value("CFCMOV16rr_REV", LIEF::assembly::x86::OPCODE::CFCMOV16rr_REV) + .value("CFCMOV32mr", LIEF::assembly::x86::OPCODE::CFCMOV32mr) + .value("CFCMOV32rm", LIEF::assembly::x86::OPCODE::CFCMOV32rm) + .value("CFCMOV32rm_ND", LIEF::assembly::x86::OPCODE::CFCMOV32rm_ND) + .value("CFCMOV32rr", LIEF::assembly::x86::OPCODE::CFCMOV32rr); + opcodes.value("CFCMOV32rr_ND", LIEF::assembly::x86::OPCODE::CFCMOV32rr_ND) + .value("CFCMOV32rr_REV", LIEF::assembly::x86::OPCODE::CFCMOV32rr_REV) + .value("CFCMOV64mr", LIEF::assembly::x86::OPCODE::CFCMOV64mr) + .value("CFCMOV64rm", LIEF::assembly::x86::OPCODE::CFCMOV64rm) + .value("CFCMOV64rm_ND", LIEF::assembly::x86::OPCODE::CFCMOV64rm_ND) + .value("CFCMOV64rr", LIEF::assembly::x86::OPCODE::CFCMOV64rr) + .value("CFCMOV64rr_ND", LIEF::assembly::x86::OPCODE::CFCMOV64rr_ND) + .value("CFCMOV64rr_REV", LIEF::assembly::x86::OPCODE::CFCMOV64rr_REV) + .value("CHS_F", LIEF::assembly::x86::OPCODE::CHS_F) + .value("CHS_Fp32", LIEF::assembly::x86::OPCODE::CHS_Fp32) + .value("CHS_Fp64", LIEF::assembly::x86::OPCODE::CHS_Fp64) + .value("CHS_Fp80", LIEF::assembly::x86::OPCODE::CHS_Fp80) + .value("CLAC", LIEF::assembly::x86::OPCODE::CLAC) + .value("CLC", LIEF::assembly::x86::OPCODE::CLC) + .value("CLD", LIEF::assembly::x86::OPCODE::CLD) + .value("CLDEMOTE", LIEF::assembly::x86::OPCODE::CLDEMOTE) + .value("CLEANUPRET", LIEF::assembly::x86::OPCODE::CLEANUPRET) + .value("CLFLUSH", LIEF::assembly::x86::OPCODE::CLFLUSH) + .value("CLFLUSHOPT", LIEF::assembly::x86::OPCODE::CLFLUSHOPT) + .value("CLGI", LIEF::assembly::x86::OPCODE::CLGI) + .value("CLI", LIEF::assembly::x86::OPCODE::CLI) + .value("CLRSSBSY", LIEF::assembly::x86::OPCODE::CLRSSBSY) + .value("CLTS", LIEF::assembly::x86::OPCODE::CLTS) + .value("CLUI", LIEF::assembly::x86::OPCODE::CLUI) + .value("CLWB", LIEF::assembly::x86::OPCODE::CLWB) + .value("CLZERO32r", LIEF::assembly::x86::OPCODE::CLZERO32r) + .value("CLZERO64r", LIEF::assembly::x86::OPCODE::CLZERO64r) + .value("CMC", LIEF::assembly::x86::OPCODE::CMC) + .value("CMOV16rm", LIEF::assembly::x86::OPCODE::CMOV16rm) + .value("CMOV16rm_ND", LIEF::assembly::x86::OPCODE::CMOV16rm_ND) + .value("CMOV16rr", LIEF::assembly::x86::OPCODE::CMOV16rr) + .value("CMOV16rr_ND", LIEF::assembly::x86::OPCODE::CMOV16rr_ND) + .value("CMOV32rm", LIEF::assembly::x86::OPCODE::CMOV32rm) + .value("CMOV32rm_ND", LIEF::assembly::x86::OPCODE::CMOV32rm_ND) + .value("CMOV32rr", LIEF::assembly::x86::OPCODE::CMOV32rr) + .value("CMOV32rr_ND", LIEF::assembly::x86::OPCODE::CMOV32rr_ND) + .value("CMOV64rm", LIEF::assembly::x86::OPCODE::CMOV64rm) + .value("CMOV64rm_ND", LIEF::assembly::x86::OPCODE::CMOV64rm_ND) + .value("CMOV64rr", LIEF::assembly::x86::OPCODE::CMOV64rr) + .value("CMOV64rr_ND", LIEF::assembly::x86::OPCODE::CMOV64rr_ND) + .value("CMOVBE_F", LIEF::assembly::x86::OPCODE::CMOVBE_F) + .value("CMOVBE_Fp32", LIEF::assembly::x86::OPCODE::CMOVBE_Fp32) + .value("CMOVBE_Fp64", LIEF::assembly::x86::OPCODE::CMOVBE_Fp64) + .value("CMOVBE_Fp80", LIEF::assembly::x86::OPCODE::CMOVBE_Fp80) + .value("CMOVB_F", LIEF::assembly::x86::OPCODE::CMOVB_F) + .value("CMOVB_Fp32", LIEF::assembly::x86::OPCODE::CMOVB_Fp32) + .value("CMOVB_Fp64", LIEF::assembly::x86::OPCODE::CMOVB_Fp64) + .value("CMOVB_Fp80", LIEF::assembly::x86::OPCODE::CMOVB_Fp80) + .value("CMOVE_F", LIEF::assembly::x86::OPCODE::CMOVE_F) + .value("CMOVE_Fp32", LIEF::assembly::x86::OPCODE::CMOVE_Fp32) + .value("CMOVE_Fp64", LIEF::assembly::x86::OPCODE::CMOVE_Fp64) + .value("CMOVE_Fp80", LIEF::assembly::x86::OPCODE::CMOVE_Fp80) + .value("CMOVNBE_F", LIEF::assembly::x86::OPCODE::CMOVNBE_F) + .value("CMOVNBE_Fp32", LIEF::assembly::x86::OPCODE::CMOVNBE_Fp32) + .value("CMOVNBE_Fp64", LIEF::assembly::x86::OPCODE::CMOVNBE_Fp64) + .value("CMOVNBE_Fp80", LIEF::assembly::x86::OPCODE::CMOVNBE_Fp80) + .value("CMOVNB_F", LIEF::assembly::x86::OPCODE::CMOVNB_F) + .value("CMOVNB_Fp32", LIEF::assembly::x86::OPCODE::CMOVNB_Fp32) + .value("CMOVNB_Fp64", LIEF::assembly::x86::OPCODE::CMOVNB_Fp64) + .value("CMOVNB_Fp80", LIEF::assembly::x86::OPCODE::CMOVNB_Fp80) + .value("CMOVNE_F", LIEF::assembly::x86::OPCODE::CMOVNE_F) + .value("CMOVNE_Fp32", LIEF::assembly::x86::OPCODE::CMOVNE_Fp32) + .value("CMOVNE_Fp64", LIEF::assembly::x86::OPCODE::CMOVNE_Fp64) + .value("CMOVNE_Fp80", LIEF::assembly::x86::OPCODE::CMOVNE_Fp80) + .value("CMOVNP_F", LIEF::assembly::x86::OPCODE::CMOVNP_F) + .value("CMOVNP_Fp32", LIEF::assembly::x86::OPCODE::CMOVNP_Fp32) + .value("CMOVNP_Fp64", LIEF::assembly::x86::OPCODE::CMOVNP_Fp64) + .value("CMOVNP_Fp80", LIEF::assembly::x86::OPCODE::CMOVNP_Fp80) + .value("CMOVP_F", LIEF::assembly::x86::OPCODE::CMOVP_F) + .value("CMOVP_Fp32", LIEF::assembly::x86::OPCODE::CMOVP_Fp32) + .value("CMOVP_Fp64", LIEF::assembly::x86::OPCODE::CMOVP_Fp64) + .value("CMOVP_Fp80", LIEF::assembly::x86::OPCODE::CMOVP_Fp80) + .value("CMOV_FR16", LIEF::assembly::x86::OPCODE::CMOV_FR16) + .value("CMOV_FR16X", LIEF::assembly::x86::OPCODE::CMOV_FR16X) + .value("CMOV_FR32", LIEF::assembly::x86::OPCODE::CMOV_FR32) + .value("CMOV_FR32X", LIEF::assembly::x86::OPCODE::CMOV_FR32X) + .value("CMOV_FR64", LIEF::assembly::x86::OPCODE::CMOV_FR64) + .value("CMOV_FR64X", LIEF::assembly::x86::OPCODE::CMOV_FR64X) + .value("CMOV_GR16", LIEF::assembly::x86::OPCODE::CMOV_GR16) + .value("CMOV_GR32", LIEF::assembly::x86::OPCODE::CMOV_GR32) + .value("CMOV_GR8", LIEF::assembly::x86::OPCODE::CMOV_GR8) + .value("CMOV_RFP32", LIEF::assembly::x86::OPCODE::CMOV_RFP32) + .value("CMOV_RFP64", LIEF::assembly::x86::OPCODE::CMOV_RFP64) + .value("CMOV_RFP80", LIEF::assembly::x86::OPCODE::CMOV_RFP80) + .value("CMOV_VK1", LIEF::assembly::x86::OPCODE::CMOV_VK1) + .value("CMOV_VK16", LIEF::assembly::x86::OPCODE::CMOV_VK16) + .value("CMOV_VK2", LIEF::assembly::x86::OPCODE::CMOV_VK2) + .value("CMOV_VK32", LIEF::assembly::x86::OPCODE::CMOV_VK32) + .value("CMOV_VK4", LIEF::assembly::x86::OPCODE::CMOV_VK4) + .value("CMOV_VK64", LIEF::assembly::x86::OPCODE::CMOV_VK64) + .value("CMOV_VK8", LIEF::assembly::x86::OPCODE::CMOV_VK8) + .value("CMOV_VR128", LIEF::assembly::x86::OPCODE::CMOV_VR128) + .value("CMOV_VR128X", LIEF::assembly::x86::OPCODE::CMOV_VR128X) + .value("CMOV_VR256", LIEF::assembly::x86::OPCODE::CMOV_VR256) + .value("CMOV_VR256X", LIEF::assembly::x86::OPCODE::CMOV_VR256X) + .value("CMOV_VR512", LIEF::assembly::x86::OPCODE::CMOV_VR512) + .value("CMOV_VR64", LIEF::assembly::x86::OPCODE::CMOV_VR64) + .value("CMP16i16", LIEF::assembly::x86::OPCODE::CMP16i16) + .value("CMP16mi", LIEF::assembly::x86::OPCODE::CMP16mi) + .value("CMP16mi8", LIEF::assembly::x86::OPCODE::CMP16mi8) + .value("CMP16mr", LIEF::assembly::x86::OPCODE::CMP16mr) + .value("CMP16ri", LIEF::assembly::x86::OPCODE::CMP16ri) + .value("CMP16ri8", LIEF::assembly::x86::OPCODE::CMP16ri8) + .value("CMP16rm", LIEF::assembly::x86::OPCODE::CMP16rm) + .value("CMP16rr", LIEF::assembly::x86::OPCODE::CMP16rr) + .value("CMP16rr_REV", LIEF::assembly::x86::OPCODE::CMP16rr_REV) + .value("CMP32i32", LIEF::assembly::x86::OPCODE::CMP32i32) + .value("CMP32mi", LIEF::assembly::x86::OPCODE::CMP32mi) + .value("CMP32mi8", LIEF::assembly::x86::OPCODE::CMP32mi8) + .value("CMP32mr", LIEF::assembly::x86::OPCODE::CMP32mr) + .value("CMP32ri", LIEF::assembly::x86::OPCODE::CMP32ri) + .value("CMP32ri8", LIEF::assembly::x86::OPCODE::CMP32ri8) + .value("CMP32rm", LIEF::assembly::x86::OPCODE::CMP32rm) + .value("CMP32rr", LIEF::assembly::x86::OPCODE::CMP32rr) + .value("CMP32rr_REV", LIEF::assembly::x86::OPCODE::CMP32rr_REV) + .value("CMP64i32", LIEF::assembly::x86::OPCODE::CMP64i32) + .value("CMP64mi32", LIEF::assembly::x86::OPCODE::CMP64mi32) + .value("CMP64mi8", LIEF::assembly::x86::OPCODE::CMP64mi8) + .value("CMP64mr", LIEF::assembly::x86::OPCODE::CMP64mr) + .value("CMP64ri32", LIEF::assembly::x86::OPCODE::CMP64ri32) + .value("CMP64ri8", LIEF::assembly::x86::OPCODE::CMP64ri8) + .value("CMP64rm", LIEF::assembly::x86::OPCODE::CMP64rm) + .value("CMP64rr", LIEF::assembly::x86::OPCODE::CMP64rr) + .value("CMP64rr_REV", LIEF::assembly::x86::OPCODE::CMP64rr_REV) + .value("CMP8i8", LIEF::assembly::x86::OPCODE::CMP8i8) + .value("CMP8mi", LIEF::assembly::x86::OPCODE::CMP8mi) + .value("CMP8mi8", LIEF::assembly::x86::OPCODE::CMP8mi8) + .value("CMP8mr", LIEF::assembly::x86::OPCODE::CMP8mr) + .value("CMP8ri", LIEF::assembly::x86::OPCODE::CMP8ri) + .value("CMP8ri8", LIEF::assembly::x86::OPCODE::CMP8ri8) + .value("CMP8rm", LIEF::assembly::x86::OPCODE::CMP8rm) + .value("CMP8rr", LIEF::assembly::x86::OPCODE::CMP8rr) + .value("CMP8rr_REV", LIEF::assembly::x86::OPCODE::CMP8rr_REV) + .value("CMPCCXADDmr32", LIEF::assembly::x86::OPCODE::CMPCCXADDmr32) + .value("CMPCCXADDmr32_EVEX", LIEF::assembly::x86::OPCODE::CMPCCXADDmr32_EVEX) + .value("CMPCCXADDmr64", LIEF::assembly::x86::OPCODE::CMPCCXADDmr64) + .value("CMPCCXADDmr64_EVEX", LIEF::assembly::x86::OPCODE::CMPCCXADDmr64_EVEX) + .value("CMPPDrmi", LIEF::assembly::x86::OPCODE::CMPPDrmi) + .value("CMPPDrri", LIEF::assembly::x86::OPCODE::CMPPDrri) + .value("CMPPSrmi", LIEF::assembly::x86::OPCODE::CMPPSrmi) + .value("CMPPSrri", LIEF::assembly::x86::OPCODE::CMPPSrri) + .value("CMPSB", LIEF::assembly::x86::OPCODE::CMPSB) + .value("CMPSDrmi", LIEF::assembly::x86::OPCODE::CMPSDrmi) + .value("CMPSDrmi_Int", LIEF::assembly::x86::OPCODE::CMPSDrmi_Int) + .value("CMPSDrri", LIEF::assembly::x86::OPCODE::CMPSDrri) + .value("CMPSDrri_Int", LIEF::assembly::x86::OPCODE::CMPSDrri_Int) + .value("CMPSL", LIEF::assembly::x86::OPCODE::CMPSL) + .value("CMPSQ", LIEF::assembly::x86::OPCODE::CMPSQ) + .value("CMPSSrmi", LIEF::assembly::x86::OPCODE::CMPSSrmi) + .value("CMPSSrmi_Int", LIEF::assembly::x86::OPCODE::CMPSSrmi_Int) + .value("CMPSSrri", LIEF::assembly::x86::OPCODE::CMPSSrri) + .value("CMPSSrri_Int", LIEF::assembly::x86::OPCODE::CMPSSrri_Int) + .value("CMPSW", LIEF::assembly::x86::OPCODE::CMPSW) + .value("CMPXCHG16B", LIEF::assembly::x86::OPCODE::CMPXCHG16B) + .value("CMPXCHG16rm", LIEF::assembly::x86::OPCODE::CMPXCHG16rm) + .value("CMPXCHG16rr", LIEF::assembly::x86::OPCODE::CMPXCHG16rr) + .value("CMPXCHG32rm", LIEF::assembly::x86::OPCODE::CMPXCHG32rm) + .value("CMPXCHG32rr", LIEF::assembly::x86::OPCODE::CMPXCHG32rr) + .value("CMPXCHG64rm", LIEF::assembly::x86::OPCODE::CMPXCHG64rm) + .value("CMPXCHG64rr", LIEF::assembly::x86::OPCODE::CMPXCHG64rr) + .value("CMPXCHG8B", LIEF::assembly::x86::OPCODE::CMPXCHG8B) + .value("CMPXCHG8rm", LIEF::assembly::x86::OPCODE::CMPXCHG8rm) + .value("CMPXCHG8rr", LIEF::assembly::x86::OPCODE::CMPXCHG8rr) + .value("COMISDrm", LIEF::assembly::x86::OPCODE::COMISDrm) + .value("COMISDrm_Int", LIEF::assembly::x86::OPCODE::COMISDrm_Int) + .value("COMISDrr", LIEF::assembly::x86::OPCODE::COMISDrr) + .value("COMISDrr_Int", LIEF::assembly::x86::OPCODE::COMISDrr_Int) + .value("COMISSrm", LIEF::assembly::x86::OPCODE::COMISSrm) + .value("COMISSrm_Int", LIEF::assembly::x86::OPCODE::COMISSrm_Int) + .value("COMISSrr", LIEF::assembly::x86::OPCODE::COMISSrr) + .value("COMISSrr_Int", LIEF::assembly::x86::OPCODE::COMISSrr_Int) + .value("COMP_FST0r", LIEF::assembly::x86::OPCODE::COMP_FST0r) + .value("COM_FIPr", LIEF::assembly::x86::OPCODE::COM_FIPr) + .value("COM_FIr", LIEF::assembly::x86::OPCODE::COM_FIr) + .value("COM_FST0r", LIEF::assembly::x86::OPCODE::COM_FST0r) + .value("COM_FpIr32", LIEF::assembly::x86::OPCODE::COM_FpIr32) + .value("COM_FpIr64", LIEF::assembly::x86::OPCODE::COM_FpIr64) + .value("COM_FpIr80", LIEF::assembly::x86::OPCODE::COM_FpIr80) + .value("COM_Fpr32", LIEF::assembly::x86::OPCODE::COM_Fpr32) + .value("COM_Fpr64", LIEF::assembly::x86::OPCODE::COM_Fpr64) + .value("COM_Fpr80", LIEF::assembly::x86::OPCODE::COM_Fpr80) + .value("CPUID", LIEF::assembly::x86::OPCODE::CPUID) + .value("CQO", LIEF::assembly::x86::OPCODE::CQO) + .value("CRC32r32m16", LIEF::assembly::x86::OPCODE::CRC32r32m16) + .value("CRC32r32m16_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32m16_EVEX) + .value("CRC32r32m32", LIEF::assembly::x86::OPCODE::CRC32r32m32) + .value("CRC32r32m32_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32m32_EVEX) + .value("CRC32r32m8", LIEF::assembly::x86::OPCODE::CRC32r32m8) + .value("CRC32r32m8_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32m8_EVEX) + .value("CRC32r32r16", LIEF::assembly::x86::OPCODE::CRC32r32r16) + .value("CRC32r32r16_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32r16_EVEX) + .value("CRC32r32r32", LIEF::assembly::x86::OPCODE::CRC32r32r32) + .value("CRC32r32r32_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32r32_EVEX) + .value("CRC32r32r8", LIEF::assembly::x86::OPCODE::CRC32r32r8) + .value("CRC32r32r8_EVEX", LIEF::assembly::x86::OPCODE::CRC32r32r8_EVEX) + .value("CRC32r64m64", LIEF::assembly::x86::OPCODE::CRC32r64m64) + .value("CRC32r64m64_EVEX", LIEF::assembly::x86::OPCODE::CRC32r64m64_EVEX) + .value("CRC32r64m8", LIEF::assembly::x86::OPCODE::CRC32r64m8) + .value("CRC32r64m8_EVEX", LIEF::assembly::x86::OPCODE::CRC32r64m8_EVEX) + .value("CRC32r64r64", LIEF::assembly::x86::OPCODE::CRC32r64r64) + .value("CRC32r64r64_EVEX", LIEF::assembly::x86::OPCODE::CRC32r64r64_EVEX) + .value("CRC32r64r8", LIEF::assembly::x86::OPCODE::CRC32r64r8) + .value("CRC32r64r8_EVEX", LIEF::assembly::x86::OPCODE::CRC32r64r8_EVEX) + .value("CS_PREFIX", LIEF::assembly::x86::OPCODE::CS_PREFIX) + .value("CTEST16mi", LIEF::assembly::x86::OPCODE::CTEST16mi) + .value("CTEST16mr", LIEF::assembly::x86::OPCODE::CTEST16mr) + .value("CTEST16ri", LIEF::assembly::x86::OPCODE::CTEST16ri) + .value("CTEST16rr", LIEF::assembly::x86::OPCODE::CTEST16rr) + .value("CTEST32mi", LIEF::assembly::x86::OPCODE::CTEST32mi) + .value("CTEST32mr", LIEF::assembly::x86::OPCODE::CTEST32mr) + .value("CTEST32ri", LIEF::assembly::x86::OPCODE::CTEST32ri) + .value("CTEST32rr", LIEF::assembly::x86::OPCODE::CTEST32rr) + .value("CTEST64mi32", LIEF::assembly::x86::OPCODE::CTEST64mi32) + .value("CTEST64mr", LIEF::assembly::x86::OPCODE::CTEST64mr) + .value("CTEST64ri32", LIEF::assembly::x86::OPCODE::CTEST64ri32) + .value("CTEST64rr", LIEF::assembly::x86::OPCODE::CTEST64rr) + .value("CTEST8mi", LIEF::assembly::x86::OPCODE::CTEST8mi) + .value("CTEST8mr", LIEF::assembly::x86::OPCODE::CTEST8mr) + .value("CTEST8ri", LIEF::assembly::x86::OPCODE::CTEST8ri) + .value("CTEST8rr", LIEF::assembly::x86::OPCODE::CTEST8rr) + .value("CVTDQ2PDrm", LIEF::assembly::x86::OPCODE::CVTDQ2PDrm) + .value("CVTDQ2PDrr", LIEF::assembly::x86::OPCODE::CVTDQ2PDrr) + .value("CVTDQ2PSrm", LIEF::assembly::x86::OPCODE::CVTDQ2PSrm) + .value("CVTDQ2PSrr", LIEF::assembly::x86::OPCODE::CVTDQ2PSrr) + .value("CVTPD2DQrm", LIEF::assembly::x86::OPCODE::CVTPD2DQrm) + .value("CVTPD2DQrr", LIEF::assembly::x86::OPCODE::CVTPD2DQrr) + .value("CVTPD2PSrm", LIEF::assembly::x86::OPCODE::CVTPD2PSrm) + .value("CVTPD2PSrr", LIEF::assembly::x86::OPCODE::CVTPD2PSrr) + .value("CVTPS2DQrm", LIEF::assembly::x86::OPCODE::CVTPS2DQrm) + .value("CVTPS2DQrr", LIEF::assembly::x86::OPCODE::CVTPS2DQrr) + .value("CVTPS2PDrm", LIEF::assembly::x86::OPCODE::CVTPS2PDrm) + .value("CVTPS2PDrr", LIEF::assembly::x86::OPCODE::CVTPS2PDrr) + .value("CVTSD2SI64rm", LIEF::assembly::x86::OPCODE::CVTSD2SI64rm) + .value("CVTSD2SI64rm_Int", LIEF::assembly::x86::OPCODE::CVTSD2SI64rm_Int) + .value("CVTSD2SI64rr", LIEF::assembly::x86::OPCODE::CVTSD2SI64rr) + .value("CVTSD2SI64rr_Int", LIEF::assembly::x86::OPCODE::CVTSD2SI64rr_Int) + .value("CVTSD2SIrm", LIEF::assembly::x86::OPCODE::CVTSD2SIrm) + .value("CVTSD2SIrm_Int", LIEF::assembly::x86::OPCODE::CVTSD2SIrm_Int) + .value("CVTSD2SIrr", LIEF::assembly::x86::OPCODE::CVTSD2SIrr) + .value("CVTSD2SIrr_Int", LIEF::assembly::x86::OPCODE::CVTSD2SIrr_Int) + .value("CVTSD2SSrm", LIEF::assembly::x86::OPCODE::CVTSD2SSrm) + .value("CVTSD2SSrm_Int", LIEF::assembly::x86::OPCODE::CVTSD2SSrm_Int) + .value("CVTSD2SSrr", LIEF::assembly::x86::OPCODE::CVTSD2SSrr) + .value("CVTSD2SSrr_Int", LIEF::assembly::x86::OPCODE::CVTSD2SSrr_Int) + .value("CVTSI2SDrm", LIEF::assembly::x86::OPCODE::CVTSI2SDrm) + .value("CVTSI2SDrm_Int", LIEF::assembly::x86::OPCODE::CVTSI2SDrm_Int) + .value("CVTSI2SDrr", LIEF::assembly::x86::OPCODE::CVTSI2SDrr) + .value("CVTSI2SDrr_Int", LIEF::assembly::x86::OPCODE::CVTSI2SDrr_Int) + .value("CVTSI2SSrm", LIEF::assembly::x86::OPCODE::CVTSI2SSrm) + .value("CVTSI2SSrm_Int", LIEF::assembly::x86::OPCODE::CVTSI2SSrm_Int) + .value("CVTSI2SSrr", LIEF::assembly::x86::OPCODE::CVTSI2SSrr) + .value("CVTSI2SSrr_Int", LIEF::assembly::x86::OPCODE::CVTSI2SSrr_Int) + .value("CVTSI642SDrm", LIEF::assembly::x86::OPCODE::CVTSI642SDrm) + .value("CVTSI642SDrm_Int", LIEF::assembly::x86::OPCODE::CVTSI642SDrm_Int) + .value("CVTSI642SDrr", LIEF::assembly::x86::OPCODE::CVTSI642SDrr) + .value("CVTSI642SDrr_Int", LIEF::assembly::x86::OPCODE::CVTSI642SDrr_Int) + .value("CVTSI642SSrm", LIEF::assembly::x86::OPCODE::CVTSI642SSrm) + .value("CVTSI642SSrm_Int", LIEF::assembly::x86::OPCODE::CVTSI642SSrm_Int) + .value("CVTSI642SSrr", LIEF::assembly::x86::OPCODE::CVTSI642SSrr) + .value("CVTSI642SSrr_Int", LIEF::assembly::x86::OPCODE::CVTSI642SSrr_Int) + .value("CVTSS2SDrm", LIEF::assembly::x86::OPCODE::CVTSS2SDrm) + .value("CVTSS2SDrm_Int", LIEF::assembly::x86::OPCODE::CVTSS2SDrm_Int) + .value("CVTSS2SDrr", LIEF::assembly::x86::OPCODE::CVTSS2SDrr) + .value("CVTSS2SDrr_Int", LIEF::assembly::x86::OPCODE::CVTSS2SDrr_Int) + .value("CVTSS2SI64rm", LIEF::assembly::x86::OPCODE::CVTSS2SI64rm) + .value("CVTSS2SI64rm_Int", LIEF::assembly::x86::OPCODE::CVTSS2SI64rm_Int) + .value("CVTSS2SI64rr", LIEF::assembly::x86::OPCODE::CVTSS2SI64rr) + .value("CVTSS2SI64rr_Int", LIEF::assembly::x86::OPCODE::CVTSS2SI64rr_Int) + .value("CVTSS2SIrm", LIEF::assembly::x86::OPCODE::CVTSS2SIrm) + .value("CVTSS2SIrm_Int", LIEF::assembly::x86::OPCODE::CVTSS2SIrm_Int) + .value("CVTSS2SIrr", LIEF::assembly::x86::OPCODE::CVTSS2SIrr) + .value("CVTSS2SIrr_Int", LIEF::assembly::x86::OPCODE::CVTSS2SIrr_Int) + .value("CVTTPD2DQrm", LIEF::assembly::x86::OPCODE::CVTTPD2DQrm) + .value("CVTTPD2DQrr", LIEF::assembly::x86::OPCODE::CVTTPD2DQrr) + .value("CVTTPS2DQrm", LIEF::assembly::x86::OPCODE::CVTTPS2DQrm) + .value("CVTTPS2DQrr", LIEF::assembly::x86::OPCODE::CVTTPS2DQrr) + .value("CVTTSD2SI64rm", LIEF::assembly::x86::OPCODE::CVTTSD2SI64rm) + .value("CVTTSD2SI64rm_Int", LIEF::assembly::x86::OPCODE::CVTTSD2SI64rm_Int) + .value("CVTTSD2SI64rr", LIEF::assembly::x86::OPCODE::CVTTSD2SI64rr) + .value("CVTTSD2SI64rr_Int", LIEF::assembly::x86::OPCODE::CVTTSD2SI64rr_Int) + .value("CVTTSD2SIrm", LIEF::assembly::x86::OPCODE::CVTTSD2SIrm) + .value("CVTTSD2SIrm_Int", LIEF::assembly::x86::OPCODE::CVTTSD2SIrm_Int) + .value("CVTTSD2SIrr", LIEF::assembly::x86::OPCODE::CVTTSD2SIrr) + .value("CVTTSD2SIrr_Int", LIEF::assembly::x86::OPCODE::CVTTSD2SIrr_Int) + .value("CVTTSS2SI64rm", LIEF::assembly::x86::OPCODE::CVTTSS2SI64rm) + .value("CVTTSS2SI64rm_Int", LIEF::assembly::x86::OPCODE::CVTTSS2SI64rm_Int) + .value("CVTTSS2SI64rr", LIEF::assembly::x86::OPCODE::CVTTSS2SI64rr) + .value("CVTTSS2SI64rr_Int", LIEF::assembly::x86::OPCODE::CVTTSS2SI64rr_Int) + .value("CVTTSS2SIrm", LIEF::assembly::x86::OPCODE::CVTTSS2SIrm) + .value("CVTTSS2SIrm_Int", LIEF::assembly::x86::OPCODE::CVTTSS2SIrm_Int) + .value("CVTTSS2SIrr", LIEF::assembly::x86::OPCODE::CVTTSS2SIrr) + .value("CVTTSS2SIrr_Int", LIEF::assembly::x86::OPCODE::CVTTSS2SIrr_Int) + .value("CWD", LIEF::assembly::x86::OPCODE::CWD) + .value("CWDE", LIEF::assembly::x86::OPCODE::CWDE) + .value("DAA", LIEF::assembly::x86::OPCODE::DAA) + .value("DAS", LIEF::assembly::x86::OPCODE::DAS) + .value("DATA16_PREFIX", LIEF::assembly::x86::OPCODE::DATA16_PREFIX) + .value("DEC16m", LIEF::assembly::x86::OPCODE::DEC16m) + .value("DEC16m_EVEX", LIEF::assembly::x86::OPCODE::DEC16m_EVEX) + .value("DEC16m_ND", LIEF::assembly::x86::OPCODE::DEC16m_ND); + opcodes.value("DEC16m_NF", LIEF::assembly::x86::OPCODE::DEC16m_NF) + .value("DEC16m_NF_ND", LIEF::assembly::x86::OPCODE::DEC16m_NF_ND) + .value("DEC16r", LIEF::assembly::x86::OPCODE::DEC16r) + .value("DEC16r_EVEX", LIEF::assembly::x86::OPCODE::DEC16r_EVEX) + .value("DEC16r_ND", LIEF::assembly::x86::OPCODE::DEC16r_ND) + .value("DEC16r_NF", LIEF::assembly::x86::OPCODE::DEC16r_NF) + .value("DEC16r_NF_ND", LIEF::assembly::x86::OPCODE::DEC16r_NF_ND) + .value("DEC16r_alt", LIEF::assembly::x86::OPCODE::DEC16r_alt) + .value("DEC32m", LIEF::assembly::x86::OPCODE::DEC32m) + .value("DEC32m_EVEX", LIEF::assembly::x86::OPCODE::DEC32m_EVEX) + .value("DEC32m_ND", LIEF::assembly::x86::OPCODE::DEC32m_ND) + .value("DEC32m_NF", LIEF::assembly::x86::OPCODE::DEC32m_NF) + .value("DEC32m_NF_ND", LIEF::assembly::x86::OPCODE::DEC32m_NF_ND) + .value("DEC32r", LIEF::assembly::x86::OPCODE::DEC32r) + .value("DEC32r_EVEX", LIEF::assembly::x86::OPCODE::DEC32r_EVEX) + .value("DEC32r_ND", LIEF::assembly::x86::OPCODE::DEC32r_ND) + .value("DEC32r_NF", LIEF::assembly::x86::OPCODE::DEC32r_NF) + .value("DEC32r_NF_ND", LIEF::assembly::x86::OPCODE::DEC32r_NF_ND) + .value("DEC32r_alt", LIEF::assembly::x86::OPCODE::DEC32r_alt) + .value("DEC64m", LIEF::assembly::x86::OPCODE::DEC64m) + .value("DEC64m_EVEX", LIEF::assembly::x86::OPCODE::DEC64m_EVEX) + .value("DEC64m_ND", LIEF::assembly::x86::OPCODE::DEC64m_ND) + .value("DEC64m_NF", LIEF::assembly::x86::OPCODE::DEC64m_NF) + .value("DEC64m_NF_ND", LIEF::assembly::x86::OPCODE::DEC64m_NF_ND) + .value("DEC64r", LIEF::assembly::x86::OPCODE::DEC64r) + .value("DEC64r_EVEX", LIEF::assembly::x86::OPCODE::DEC64r_EVEX) + .value("DEC64r_ND", LIEF::assembly::x86::OPCODE::DEC64r_ND) + .value("DEC64r_NF", LIEF::assembly::x86::OPCODE::DEC64r_NF) + .value("DEC64r_NF_ND", LIEF::assembly::x86::OPCODE::DEC64r_NF_ND) + .value("DEC8m", LIEF::assembly::x86::OPCODE::DEC8m) + .value("DEC8m_EVEX", LIEF::assembly::x86::OPCODE::DEC8m_EVEX) + .value("DEC8m_ND", LIEF::assembly::x86::OPCODE::DEC8m_ND) + .value("DEC8m_NF", LIEF::assembly::x86::OPCODE::DEC8m_NF) + .value("DEC8m_NF_ND", LIEF::assembly::x86::OPCODE::DEC8m_NF_ND) + .value("DEC8r", LIEF::assembly::x86::OPCODE::DEC8r) + .value("DEC8r_EVEX", LIEF::assembly::x86::OPCODE::DEC8r_EVEX) + .value("DEC8r_ND", LIEF::assembly::x86::OPCODE::DEC8r_ND) + .value("DEC8r_NF", LIEF::assembly::x86::OPCODE::DEC8r_NF) + .value("DEC8r_NF_ND", LIEF::assembly::x86::OPCODE::DEC8r_NF_ND) + .value("DIV16m", LIEF::assembly::x86::OPCODE::DIV16m) + .value("DIV16m_EVEX", LIEF::assembly::x86::OPCODE::DIV16m_EVEX) + .value("DIV16m_NF", LIEF::assembly::x86::OPCODE::DIV16m_NF) + .value("DIV16r", LIEF::assembly::x86::OPCODE::DIV16r) + .value("DIV16r_EVEX", LIEF::assembly::x86::OPCODE::DIV16r_EVEX) + .value("DIV16r_NF", LIEF::assembly::x86::OPCODE::DIV16r_NF) + .value("DIV32m", LIEF::assembly::x86::OPCODE::DIV32m) + .value("DIV32m_EVEX", LIEF::assembly::x86::OPCODE::DIV32m_EVEX) + .value("DIV32m_NF", LIEF::assembly::x86::OPCODE::DIV32m_NF) + .value("DIV32r", LIEF::assembly::x86::OPCODE::DIV32r) + .value("DIV32r_EVEX", LIEF::assembly::x86::OPCODE::DIV32r_EVEX) + .value("DIV32r_NF", LIEF::assembly::x86::OPCODE::DIV32r_NF) + .value("DIV64m", LIEF::assembly::x86::OPCODE::DIV64m) + .value("DIV64m_EVEX", LIEF::assembly::x86::OPCODE::DIV64m_EVEX) + .value("DIV64m_NF", LIEF::assembly::x86::OPCODE::DIV64m_NF) + .value("DIV64r", LIEF::assembly::x86::OPCODE::DIV64r) + .value("DIV64r_EVEX", LIEF::assembly::x86::OPCODE::DIV64r_EVEX) + .value("DIV64r_NF", LIEF::assembly::x86::OPCODE::DIV64r_NF) + .value("DIV8m", LIEF::assembly::x86::OPCODE::DIV8m) + .value("DIV8m_EVEX", LIEF::assembly::x86::OPCODE::DIV8m_EVEX) + .value("DIV8m_NF", LIEF::assembly::x86::OPCODE::DIV8m_NF) + .value("DIV8r", LIEF::assembly::x86::OPCODE::DIV8r) + .value("DIV8r_EVEX", LIEF::assembly::x86::OPCODE::DIV8r_EVEX) + .value("DIV8r_NF", LIEF::assembly::x86::OPCODE::DIV8r_NF) + .value("DIVPDrm", LIEF::assembly::x86::OPCODE::DIVPDrm) + .value("DIVPDrr", LIEF::assembly::x86::OPCODE::DIVPDrr) + .value("DIVPSrm", LIEF::assembly::x86::OPCODE::DIVPSrm) + .value("DIVPSrr", LIEF::assembly::x86::OPCODE::DIVPSrr) + .value("DIVR_F32m", LIEF::assembly::x86::OPCODE::DIVR_F32m) + .value("DIVR_F64m", LIEF::assembly::x86::OPCODE::DIVR_F64m) + .value("DIVR_FI16m", LIEF::assembly::x86::OPCODE::DIVR_FI16m) + .value("DIVR_FI32m", LIEF::assembly::x86::OPCODE::DIVR_FI32m) + .value("DIVR_FPrST0", LIEF::assembly::x86::OPCODE::DIVR_FPrST0) + .value("DIVR_FST0r", LIEF::assembly::x86::OPCODE::DIVR_FST0r) + .value("DIVR_Fp32m", LIEF::assembly::x86::OPCODE::DIVR_Fp32m) + .value("DIVR_Fp64m", LIEF::assembly::x86::OPCODE::DIVR_Fp64m) + .value("DIVR_Fp64m32", LIEF::assembly::x86::OPCODE::DIVR_Fp64m32) + .value("DIVR_Fp80m32", LIEF::assembly::x86::OPCODE::DIVR_Fp80m32) + .value("DIVR_Fp80m64", LIEF::assembly::x86::OPCODE::DIVR_Fp80m64) + .value("DIVR_FpI16m32", LIEF::assembly::x86::OPCODE::DIVR_FpI16m32) + .value("DIVR_FpI16m64", LIEF::assembly::x86::OPCODE::DIVR_FpI16m64) + .value("DIVR_FpI16m80", LIEF::assembly::x86::OPCODE::DIVR_FpI16m80) + .value("DIVR_FpI32m32", LIEF::assembly::x86::OPCODE::DIVR_FpI32m32) + .value("DIVR_FpI32m64", LIEF::assembly::x86::OPCODE::DIVR_FpI32m64) + .value("DIVR_FpI32m80", LIEF::assembly::x86::OPCODE::DIVR_FpI32m80) + .value("DIVR_FrST0", LIEF::assembly::x86::OPCODE::DIVR_FrST0) + .value("DIVSDrm", LIEF::assembly::x86::OPCODE::DIVSDrm) + .value("DIVSDrm_Int", LIEF::assembly::x86::OPCODE::DIVSDrm_Int) + .value("DIVSDrr", LIEF::assembly::x86::OPCODE::DIVSDrr) + .value("DIVSDrr_Int", LIEF::assembly::x86::OPCODE::DIVSDrr_Int) + .value("DIVSSrm", LIEF::assembly::x86::OPCODE::DIVSSrm) + .value("DIVSSrm_Int", LIEF::assembly::x86::OPCODE::DIVSSrm_Int) + .value("DIVSSrr", LIEF::assembly::x86::OPCODE::DIVSSrr) + .value("DIVSSrr_Int", LIEF::assembly::x86::OPCODE::DIVSSrr_Int) + .value("DIV_F32m", LIEF::assembly::x86::OPCODE::DIV_F32m) + .value("DIV_F64m", LIEF::assembly::x86::OPCODE::DIV_F64m) + .value("DIV_FI16m", LIEF::assembly::x86::OPCODE::DIV_FI16m) + .value("DIV_FI32m", LIEF::assembly::x86::OPCODE::DIV_FI32m) + .value("DIV_FPrST0", LIEF::assembly::x86::OPCODE::DIV_FPrST0) + .value("DIV_FST0r", LIEF::assembly::x86::OPCODE::DIV_FST0r) + .value("DIV_Fp32", LIEF::assembly::x86::OPCODE::DIV_Fp32) + .value("DIV_Fp32m", LIEF::assembly::x86::OPCODE::DIV_Fp32m) + .value("DIV_Fp64", LIEF::assembly::x86::OPCODE::DIV_Fp64) + .value("DIV_Fp64m", LIEF::assembly::x86::OPCODE::DIV_Fp64m) + .value("DIV_Fp64m32", LIEF::assembly::x86::OPCODE::DIV_Fp64m32) + .value("DIV_Fp80", LIEF::assembly::x86::OPCODE::DIV_Fp80) + .value("DIV_Fp80m32", LIEF::assembly::x86::OPCODE::DIV_Fp80m32) + .value("DIV_Fp80m64", LIEF::assembly::x86::OPCODE::DIV_Fp80m64) + .value("DIV_FpI16m32", LIEF::assembly::x86::OPCODE::DIV_FpI16m32) + .value("DIV_FpI16m64", LIEF::assembly::x86::OPCODE::DIV_FpI16m64) + .value("DIV_FpI16m80", LIEF::assembly::x86::OPCODE::DIV_FpI16m80) + .value("DIV_FpI32m32", LIEF::assembly::x86::OPCODE::DIV_FpI32m32) + .value("DIV_FpI32m64", LIEF::assembly::x86::OPCODE::DIV_FpI32m64) + .value("DIV_FpI32m80", LIEF::assembly::x86::OPCODE::DIV_FpI32m80) + .value("DIV_FrST0", LIEF::assembly::x86::OPCODE::DIV_FrST0) + .value("DPPDrmi", LIEF::assembly::x86::OPCODE::DPPDrmi) + .value("DPPDrri", LIEF::assembly::x86::OPCODE::DPPDrri) + .value("DPPSrmi", LIEF::assembly::x86::OPCODE::DPPSrmi) + .value("DPPSrri", LIEF::assembly::x86::OPCODE::DPPSrri) + .value("DS_PREFIX", LIEF::assembly::x86::OPCODE::DS_PREFIX) + .value("DYN_ALLOCA_32", LIEF::assembly::x86::OPCODE::DYN_ALLOCA_32) + .value("DYN_ALLOCA_64", LIEF::assembly::x86::OPCODE::DYN_ALLOCA_64) + .value("EH_RETURN", LIEF::assembly::x86::OPCODE::EH_RETURN) + .value("EH_RETURN64", LIEF::assembly::x86::OPCODE::EH_RETURN64) + .value("EH_SjLj_LongJmp32", LIEF::assembly::x86::OPCODE::EH_SjLj_LongJmp32) + .value("EH_SjLj_LongJmp64", LIEF::assembly::x86::OPCODE::EH_SjLj_LongJmp64) + .value("EH_SjLj_SetJmp32", LIEF::assembly::x86::OPCODE::EH_SjLj_SetJmp32) + .value("EH_SjLj_SetJmp64", LIEF::assembly::x86::OPCODE::EH_SjLj_SetJmp64) + .value("EH_SjLj_Setup", LIEF::assembly::x86::OPCODE::EH_SjLj_Setup) + .value("ENCLS", LIEF::assembly::x86::OPCODE::ENCLS) + .value("ENCLU", LIEF::assembly::x86::OPCODE::ENCLU) + .value("ENCLV", LIEF::assembly::x86::OPCODE::ENCLV) + .value("ENCODEKEY128", LIEF::assembly::x86::OPCODE::ENCODEKEY128) + .value("ENCODEKEY256", LIEF::assembly::x86::OPCODE::ENCODEKEY256) + .value("ENDBR32", LIEF::assembly::x86::OPCODE::ENDBR32) + .value("ENDBR64", LIEF::assembly::x86::OPCODE::ENDBR64) + .value("ENQCMD16", LIEF::assembly::x86::OPCODE::ENQCMD16) + .value("ENQCMD32", LIEF::assembly::x86::OPCODE::ENQCMD32) + .value("ENQCMD32_EVEX", LIEF::assembly::x86::OPCODE::ENQCMD32_EVEX) + .value("ENQCMD64", LIEF::assembly::x86::OPCODE::ENQCMD64) + .value("ENQCMD64_EVEX", LIEF::assembly::x86::OPCODE::ENQCMD64_EVEX) + .value("ENQCMDS16", LIEF::assembly::x86::OPCODE::ENQCMDS16) + .value("ENQCMDS32", LIEF::assembly::x86::OPCODE::ENQCMDS32) + .value("ENQCMDS32_EVEX", LIEF::assembly::x86::OPCODE::ENQCMDS32_EVEX) + .value("ENQCMDS64", LIEF::assembly::x86::OPCODE::ENQCMDS64) + .value("ENQCMDS64_EVEX", LIEF::assembly::x86::OPCODE::ENQCMDS64_EVEX) + .value("ENTER", LIEF::assembly::x86::OPCODE::ENTER) + .value("ERETS", LIEF::assembly::x86::OPCODE::ERETS) + .value("ERETU", LIEF::assembly::x86::OPCODE::ERETU) + .value("ES_PREFIX", LIEF::assembly::x86::OPCODE::ES_PREFIX) + .value("EXTRACTPSmri", LIEF::assembly::x86::OPCODE::EXTRACTPSmri) + .value("EXTRACTPSrri", LIEF::assembly::x86::OPCODE::EXTRACTPSrri) + .value("EXTRQ", LIEF::assembly::x86::OPCODE::EXTRQ) + .value("EXTRQI", LIEF::assembly::x86::OPCODE::EXTRQI) + .value("F2XM1", LIEF::assembly::x86::OPCODE::F2XM1) + .value("FARCALL16i", LIEF::assembly::x86::OPCODE::FARCALL16i) + .value("FARCALL16m", LIEF::assembly::x86::OPCODE::FARCALL16m) + .value("FARCALL32i", LIEF::assembly::x86::OPCODE::FARCALL32i) + .value("FARCALL32m", LIEF::assembly::x86::OPCODE::FARCALL32m) + .value("FARCALL64m", LIEF::assembly::x86::OPCODE::FARCALL64m) + .value("FARJMP16i", LIEF::assembly::x86::OPCODE::FARJMP16i) + .value("FARJMP16m", LIEF::assembly::x86::OPCODE::FARJMP16m) + .value("FARJMP32i", LIEF::assembly::x86::OPCODE::FARJMP32i) + .value("FARJMP32m", LIEF::assembly::x86::OPCODE::FARJMP32m) + .value("FARJMP64m", LIEF::assembly::x86::OPCODE::FARJMP64m) + .value("FBLDm", LIEF::assembly::x86::OPCODE::FBLDm) + .value("FBSTPm", LIEF::assembly::x86::OPCODE::FBSTPm) + .value("FCOM32m", LIEF::assembly::x86::OPCODE::FCOM32m) + .value("FCOM64m", LIEF::assembly::x86::OPCODE::FCOM64m) + .value("FCOMP32m", LIEF::assembly::x86::OPCODE::FCOMP32m) + .value("FCOMP64m", LIEF::assembly::x86::OPCODE::FCOMP64m) + .value("FCOMPP", LIEF::assembly::x86::OPCODE::FCOMPP) + .value("FCOS", LIEF::assembly::x86::OPCODE::FCOS) + .value("FDECSTP", LIEF::assembly::x86::OPCODE::FDECSTP) + .value("FEMMS", LIEF::assembly::x86::OPCODE::FEMMS) + .value("FFREE", LIEF::assembly::x86::OPCODE::FFREE) + .value("FFREEP", LIEF::assembly::x86::OPCODE::FFREEP) + .value("FICOM16m", LIEF::assembly::x86::OPCODE::FICOM16m) + .value("FICOM32m", LIEF::assembly::x86::OPCODE::FICOM32m) + .value("FICOMP16m", LIEF::assembly::x86::OPCODE::FICOMP16m) + .value("FICOMP32m", LIEF::assembly::x86::OPCODE::FICOMP32m) + .value("FINCSTP", LIEF::assembly::x86::OPCODE::FINCSTP) + .value("FLDCW16m", LIEF::assembly::x86::OPCODE::FLDCW16m) + .value("FLDENVm", LIEF::assembly::x86::OPCODE::FLDENVm) + .value("FLDL2E", LIEF::assembly::x86::OPCODE::FLDL2E) + .value("FLDL2T", LIEF::assembly::x86::OPCODE::FLDL2T) + .value("FLDLG2", LIEF::assembly::x86::OPCODE::FLDLG2) + .value("FLDLN2", LIEF::assembly::x86::OPCODE::FLDLN2) + .value("FLDPI", LIEF::assembly::x86::OPCODE::FLDPI) + .value("FNCLEX", LIEF::assembly::x86::OPCODE::FNCLEX) + .value("FNINIT", LIEF::assembly::x86::OPCODE::FNINIT) + .value("FNOP", LIEF::assembly::x86::OPCODE::FNOP) + .value("FNSTCW16m", LIEF::assembly::x86::OPCODE::FNSTCW16m) + .value("FNSTSW16r", LIEF::assembly::x86::OPCODE::FNSTSW16r) + .value("FNSTSWm", LIEF::assembly::x86::OPCODE::FNSTSWm) + .value("FP32_TO_INT16_IN_MEM", LIEF::assembly::x86::OPCODE::FP32_TO_INT16_IN_MEM) + .value("FP32_TO_INT32_IN_MEM", LIEF::assembly::x86::OPCODE::FP32_TO_INT32_IN_MEM) + .value("FP32_TO_INT64_IN_MEM", LIEF::assembly::x86::OPCODE::FP32_TO_INT64_IN_MEM) + .value("FP64_TO_INT16_IN_MEM", LIEF::assembly::x86::OPCODE::FP64_TO_INT16_IN_MEM) + .value("FP64_TO_INT32_IN_MEM", LIEF::assembly::x86::OPCODE::FP64_TO_INT32_IN_MEM) + .value("FP64_TO_INT64_IN_MEM", LIEF::assembly::x86::OPCODE::FP64_TO_INT64_IN_MEM) + .value("FP80_ADDm32", LIEF::assembly::x86::OPCODE::FP80_ADDm32) + .value("FP80_ADDr", LIEF::assembly::x86::OPCODE::FP80_ADDr) + .value("FP80_TO_INT16_IN_MEM", LIEF::assembly::x86::OPCODE::FP80_TO_INT16_IN_MEM) + .value("FP80_TO_INT32_IN_MEM", LIEF::assembly::x86::OPCODE::FP80_TO_INT32_IN_MEM) + .value("FP80_TO_INT64_IN_MEM", LIEF::assembly::x86::OPCODE::FP80_TO_INT64_IN_MEM) + .value("FPATAN", LIEF::assembly::x86::OPCODE::FPATAN) + .value("FPREM", LIEF::assembly::x86::OPCODE::FPREM) + .value("FPREM1", LIEF::assembly::x86::OPCODE::FPREM1) + .value("FPTAN", LIEF::assembly::x86::OPCODE::FPTAN) + .value("FRNDINT", LIEF::assembly::x86::OPCODE::FRNDINT) + .value("FRSTORm", LIEF::assembly::x86::OPCODE::FRSTORm) + .value("FSAVEm", LIEF::assembly::x86::OPCODE::FSAVEm) + .value("FSCALE_", LIEF::assembly::x86::OPCODE::FSCALE_) + .value("FSIN", LIEF::assembly::x86::OPCODE::FSIN) + .value("FSINCOS", LIEF::assembly::x86::OPCODE::FSINCOS) + .value("FSTENVm", LIEF::assembly::x86::OPCODE::FSTENVm) + .value("FS_PREFIX", LIEF::assembly::x86::OPCODE::FS_PREFIX) + .value("FXRSTOR", LIEF::assembly::x86::OPCODE::FXRSTOR) + .value("FXRSTOR64", LIEF::assembly::x86::OPCODE::FXRSTOR64) + .value("FXSAVE", LIEF::assembly::x86::OPCODE::FXSAVE) + .value("FXSAVE64", LIEF::assembly::x86::OPCODE::FXSAVE64) + .value("FXTRACT", LIEF::assembly::x86::OPCODE::FXTRACT) + .value("FYL2X", LIEF::assembly::x86::OPCODE::FYL2X) + .value("FYL2XP1", LIEF::assembly::x86::OPCODE::FYL2XP1) + .value("GETSEC", LIEF::assembly::x86::OPCODE::GETSEC) + .value("GF2P8AFFINEINVQBrmi", LIEF::assembly::x86::OPCODE::GF2P8AFFINEINVQBrmi) + .value("GF2P8AFFINEINVQBrri", LIEF::assembly::x86::OPCODE::GF2P8AFFINEINVQBrri) + .value("GF2P8AFFINEQBrmi", LIEF::assembly::x86::OPCODE::GF2P8AFFINEQBrmi) + .value("GF2P8AFFINEQBrri", LIEF::assembly::x86::OPCODE::GF2P8AFFINEQBrri) + .value("GF2P8MULBrm", LIEF::assembly::x86::OPCODE::GF2P8MULBrm) + .value("GF2P8MULBrr", LIEF::assembly::x86::OPCODE::GF2P8MULBrr) + .value("GS_PREFIX", LIEF::assembly::x86::OPCODE::GS_PREFIX) + .value("HADDPDrm", LIEF::assembly::x86::OPCODE::HADDPDrm) + .value("HADDPDrr", LIEF::assembly::x86::OPCODE::HADDPDrr) + .value("HADDPSrm", LIEF::assembly::x86::OPCODE::HADDPSrm) + .value("HADDPSrr", LIEF::assembly::x86::OPCODE::HADDPSrr) + .value("HLT", LIEF::assembly::x86::OPCODE::HLT) + .value("HRESET", LIEF::assembly::x86::OPCODE::HRESET) + .value("HSUBPDrm", LIEF::assembly::x86::OPCODE::HSUBPDrm) + .value("HSUBPDrr", LIEF::assembly::x86::OPCODE::HSUBPDrr) + .value("HSUBPSrm", LIEF::assembly::x86::OPCODE::HSUBPSrm) + .value("HSUBPSrr", LIEF::assembly::x86::OPCODE::HSUBPSrr) + .value("IDIV16m", LIEF::assembly::x86::OPCODE::IDIV16m) + .value("IDIV16m_EVEX", LIEF::assembly::x86::OPCODE::IDIV16m_EVEX) + .value("IDIV16m_NF", LIEF::assembly::x86::OPCODE::IDIV16m_NF) + .value("IDIV16r", LIEF::assembly::x86::OPCODE::IDIV16r) + .value("IDIV16r_EVEX", LIEF::assembly::x86::OPCODE::IDIV16r_EVEX) + .value("IDIV16r_NF", LIEF::assembly::x86::OPCODE::IDIV16r_NF) + .value("IDIV32m", LIEF::assembly::x86::OPCODE::IDIV32m) + .value("IDIV32m_EVEX", LIEF::assembly::x86::OPCODE::IDIV32m_EVEX) + .value("IDIV32m_NF", LIEF::assembly::x86::OPCODE::IDIV32m_NF) + .value("IDIV32r", LIEF::assembly::x86::OPCODE::IDIV32r) + .value("IDIV32r_EVEX", LIEF::assembly::x86::OPCODE::IDIV32r_EVEX) + .value("IDIV32r_NF", LIEF::assembly::x86::OPCODE::IDIV32r_NF) + .value("IDIV64m", LIEF::assembly::x86::OPCODE::IDIV64m) + .value("IDIV64m_EVEX", LIEF::assembly::x86::OPCODE::IDIV64m_EVEX) + .value("IDIV64m_NF", LIEF::assembly::x86::OPCODE::IDIV64m_NF) + .value("IDIV64r", LIEF::assembly::x86::OPCODE::IDIV64r) + .value("IDIV64r_EVEX", LIEF::assembly::x86::OPCODE::IDIV64r_EVEX) + .value("IDIV64r_NF", LIEF::assembly::x86::OPCODE::IDIV64r_NF) + .value("IDIV8m", LIEF::assembly::x86::OPCODE::IDIV8m) + .value("IDIV8m_EVEX", LIEF::assembly::x86::OPCODE::IDIV8m_EVEX) + .value("IDIV8m_NF", LIEF::assembly::x86::OPCODE::IDIV8m_NF) + .value("IDIV8r", LIEF::assembly::x86::OPCODE::IDIV8r) + .value("IDIV8r_EVEX", LIEF::assembly::x86::OPCODE::IDIV8r_EVEX) + .value("IDIV8r_NF", LIEF::assembly::x86::OPCODE::IDIV8r_NF) + .value("ILD_F16m", LIEF::assembly::x86::OPCODE::ILD_F16m) + .value("ILD_F32m", LIEF::assembly::x86::OPCODE::ILD_F32m) + .value("ILD_F64m", LIEF::assembly::x86::OPCODE::ILD_F64m) + .value("ILD_Fp16m32", LIEF::assembly::x86::OPCODE::ILD_Fp16m32) + .value("ILD_Fp16m64", LIEF::assembly::x86::OPCODE::ILD_Fp16m64) + .value("ILD_Fp16m80", LIEF::assembly::x86::OPCODE::ILD_Fp16m80) + .value("ILD_Fp32m32", LIEF::assembly::x86::OPCODE::ILD_Fp32m32) + .value("ILD_Fp32m64", LIEF::assembly::x86::OPCODE::ILD_Fp32m64) + .value("ILD_Fp32m80", LIEF::assembly::x86::OPCODE::ILD_Fp32m80) + .value("ILD_Fp64m32", LIEF::assembly::x86::OPCODE::ILD_Fp64m32) + .value("ILD_Fp64m64", LIEF::assembly::x86::OPCODE::ILD_Fp64m64) + .value("ILD_Fp64m80", LIEF::assembly::x86::OPCODE::ILD_Fp64m80) + .value("IMUL16m", LIEF::assembly::x86::OPCODE::IMUL16m) + .value("IMUL16m_EVEX", LIEF::assembly::x86::OPCODE::IMUL16m_EVEX) + .value("IMUL16m_NF", LIEF::assembly::x86::OPCODE::IMUL16m_NF) + .value("IMUL16r", LIEF::assembly::x86::OPCODE::IMUL16r) + .value("IMUL16r_EVEX", LIEF::assembly::x86::OPCODE::IMUL16r_EVEX) + .value("IMUL16r_NF", LIEF::assembly::x86::OPCODE::IMUL16r_NF) + .value("IMUL16rm", LIEF::assembly::x86::OPCODE::IMUL16rm) + .value("IMUL16rm_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rm_EVEX) + .value("IMUL16rm_ND", LIEF::assembly::x86::OPCODE::IMUL16rm_ND) + .value("IMUL16rm_NF", LIEF::assembly::x86::OPCODE::IMUL16rm_NF) + .value("IMUL16rm_NF_ND", LIEF::assembly::x86::OPCODE::IMUL16rm_NF_ND) + .value("IMUL16rmi", LIEF::assembly::x86::OPCODE::IMUL16rmi) + .value("IMUL16rmi8", LIEF::assembly::x86::OPCODE::IMUL16rmi8) + .value("IMUL16rmi8_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rmi8_EVEX) + .value("IMUL16rmi8_NF", LIEF::assembly::x86::OPCODE::IMUL16rmi8_NF) + .value("IMUL16rmi_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rmi_EVEX) + .value("IMUL16rmi_NF", LIEF::assembly::x86::OPCODE::IMUL16rmi_NF) + .value("IMUL16rr", LIEF::assembly::x86::OPCODE::IMUL16rr) + .value("IMUL16rr_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rr_EVEX) + .value("IMUL16rr_ND", LIEF::assembly::x86::OPCODE::IMUL16rr_ND) + .value("IMUL16rr_NF", LIEF::assembly::x86::OPCODE::IMUL16rr_NF) + .value("IMUL16rr_NF_ND", LIEF::assembly::x86::OPCODE::IMUL16rr_NF_ND); + opcodes.value("IMUL16rri", LIEF::assembly::x86::OPCODE::IMUL16rri) + .value("IMUL16rri8", LIEF::assembly::x86::OPCODE::IMUL16rri8) + .value("IMUL16rri8_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rri8_EVEX) + .value("IMUL16rri8_NF", LIEF::assembly::x86::OPCODE::IMUL16rri8_NF) + .value("IMUL16rri_EVEX", LIEF::assembly::x86::OPCODE::IMUL16rri_EVEX) + .value("IMUL16rri_NF", LIEF::assembly::x86::OPCODE::IMUL16rri_NF) + .value("IMUL32m", LIEF::assembly::x86::OPCODE::IMUL32m) + .value("IMUL32m_EVEX", LIEF::assembly::x86::OPCODE::IMUL32m_EVEX) + .value("IMUL32m_NF", LIEF::assembly::x86::OPCODE::IMUL32m_NF) + .value("IMUL32r", LIEF::assembly::x86::OPCODE::IMUL32r) + .value("IMUL32r_EVEX", LIEF::assembly::x86::OPCODE::IMUL32r_EVEX) + .value("IMUL32r_NF", LIEF::assembly::x86::OPCODE::IMUL32r_NF) + .value("IMUL32rm", LIEF::assembly::x86::OPCODE::IMUL32rm) + .value("IMUL32rm_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rm_EVEX) + .value("IMUL32rm_ND", LIEF::assembly::x86::OPCODE::IMUL32rm_ND) + .value("IMUL32rm_NF", LIEF::assembly::x86::OPCODE::IMUL32rm_NF) + .value("IMUL32rm_NF_ND", LIEF::assembly::x86::OPCODE::IMUL32rm_NF_ND) + .value("IMUL32rmi", LIEF::assembly::x86::OPCODE::IMUL32rmi) + .value("IMUL32rmi8", LIEF::assembly::x86::OPCODE::IMUL32rmi8) + .value("IMUL32rmi8_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rmi8_EVEX) + .value("IMUL32rmi8_NF", LIEF::assembly::x86::OPCODE::IMUL32rmi8_NF) + .value("IMUL32rmi_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rmi_EVEX) + .value("IMUL32rmi_NF", LIEF::assembly::x86::OPCODE::IMUL32rmi_NF) + .value("IMUL32rr", LIEF::assembly::x86::OPCODE::IMUL32rr) + .value("IMUL32rr_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rr_EVEX) + .value("IMUL32rr_ND", LIEF::assembly::x86::OPCODE::IMUL32rr_ND) + .value("IMUL32rr_NF", LIEF::assembly::x86::OPCODE::IMUL32rr_NF) + .value("IMUL32rr_NF_ND", LIEF::assembly::x86::OPCODE::IMUL32rr_NF_ND) + .value("IMUL32rri", LIEF::assembly::x86::OPCODE::IMUL32rri) + .value("IMUL32rri8", LIEF::assembly::x86::OPCODE::IMUL32rri8) + .value("IMUL32rri8_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rri8_EVEX) + .value("IMUL32rri8_NF", LIEF::assembly::x86::OPCODE::IMUL32rri8_NF) + .value("IMUL32rri_EVEX", LIEF::assembly::x86::OPCODE::IMUL32rri_EVEX) + .value("IMUL32rri_NF", LIEF::assembly::x86::OPCODE::IMUL32rri_NF) + .value("IMUL64m", LIEF::assembly::x86::OPCODE::IMUL64m) + .value("IMUL64m_EVEX", LIEF::assembly::x86::OPCODE::IMUL64m_EVEX) + .value("IMUL64m_NF", LIEF::assembly::x86::OPCODE::IMUL64m_NF) + .value("IMUL64r", LIEF::assembly::x86::OPCODE::IMUL64r) + .value("IMUL64r_EVEX", LIEF::assembly::x86::OPCODE::IMUL64r_EVEX) + .value("IMUL64r_NF", LIEF::assembly::x86::OPCODE::IMUL64r_NF) + .value("IMUL64rm", LIEF::assembly::x86::OPCODE::IMUL64rm) + .value("IMUL64rm_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rm_EVEX) + .value("IMUL64rm_ND", LIEF::assembly::x86::OPCODE::IMUL64rm_ND) + .value("IMUL64rm_NF", LIEF::assembly::x86::OPCODE::IMUL64rm_NF) + .value("IMUL64rm_NF_ND", LIEF::assembly::x86::OPCODE::IMUL64rm_NF_ND) + .value("IMUL64rmi32", LIEF::assembly::x86::OPCODE::IMUL64rmi32) + .value("IMUL64rmi32_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rmi32_EVEX) + .value("IMUL64rmi32_NF", LIEF::assembly::x86::OPCODE::IMUL64rmi32_NF) + .value("IMUL64rmi8", LIEF::assembly::x86::OPCODE::IMUL64rmi8) + .value("IMUL64rmi8_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rmi8_EVEX) + .value("IMUL64rmi8_NF", LIEF::assembly::x86::OPCODE::IMUL64rmi8_NF) + .value("IMUL64rr", LIEF::assembly::x86::OPCODE::IMUL64rr) + .value("IMUL64rr_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rr_EVEX) + .value("IMUL64rr_ND", LIEF::assembly::x86::OPCODE::IMUL64rr_ND) + .value("IMUL64rr_NF", LIEF::assembly::x86::OPCODE::IMUL64rr_NF) + .value("IMUL64rr_NF_ND", LIEF::assembly::x86::OPCODE::IMUL64rr_NF_ND) + .value("IMUL64rri32", LIEF::assembly::x86::OPCODE::IMUL64rri32) + .value("IMUL64rri32_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rri32_EVEX) + .value("IMUL64rri32_NF", LIEF::assembly::x86::OPCODE::IMUL64rri32_NF) + .value("IMUL64rri8", LIEF::assembly::x86::OPCODE::IMUL64rri8) + .value("IMUL64rri8_EVEX", LIEF::assembly::x86::OPCODE::IMUL64rri8_EVEX) + .value("IMUL64rri8_NF", LIEF::assembly::x86::OPCODE::IMUL64rri8_NF) + .value("IMUL8m", LIEF::assembly::x86::OPCODE::IMUL8m) + .value("IMUL8m_EVEX", LIEF::assembly::x86::OPCODE::IMUL8m_EVEX) + .value("IMUL8m_NF", LIEF::assembly::x86::OPCODE::IMUL8m_NF) + .value("IMUL8r", LIEF::assembly::x86::OPCODE::IMUL8r) + .value("IMUL8r_EVEX", LIEF::assembly::x86::OPCODE::IMUL8r_EVEX) + .value("IMUL8r_NF", LIEF::assembly::x86::OPCODE::IMUL8r_NF) + .value("IMULZU16rmi", LIEF::assembly::x86::OPCODE::IMULZU16rmi) + .value("IMULZU16rmi8", LIEF::assembly::x86::OPCODE::IMULZU16rmi8) + .value("IMULZU16rri", LIEF::assembly::x86::OPCODE::IMULZU16rri) + .value("IMULZU16rri8", LIEF::assembly::x86::OPCODE::IMULZU16rri8) + .value("IMULZU32rmi", LIEF::assembly::x86::OPCODE::IMULZU32rmi) + .value("IMULZU32rmi8", LIEF::assembly::x86::OPCODE::IMULZU32rmi8) + .value("IMULZU32rri", LIEF::assembly::x86::OPCODE::IMULZU32rri) + .value("IMULZU32rri8", LIEF::assembly::x86::OPCODE::IMULZU32rri8) + .value("IMULZU64rmi32", LIEF::assembly::x86::OPCODE::IMULZU64rmi32) + .value("IMULZU64rmi8", LIEF::assembly::x86::OPCODE::IMULZU64rmi8) + .value("IMULZU64rri32", LIEF::assembly::x86::OPCODE::IMULZU64rri32) + .value("IMULZU64rri8", LIEF::assembly::x86::OPCODE::IMULZU64rri8) + .value("IN16ri", LIEF::assembly::x86::OPCODE::IN16ri) + .value("IN16rr", LIEF::assembly::x86::OPCODE::IN16rr) + .value("IN32ri", LIEF::assembly::x86::OPCODE::IN32ri) + .value("IN32rr", LIEF::assembly::x86::OPCODE::IN32rr) + .value("IN8ri", LIEF::assembly::x86::OPCODE::IN8ri) + .value("IN8rr", LIEF::assembly::x86::OPCODE::IN8rr) + .value("INC16m", LIEF::assembly::x86::OPCODE::INC16m) + .value("INC16m_EVEX", LIEF::assembly::x86::OPCODE::INC16m_EVEX) + .value("INC16m_ND", LIEF::assembly::x86::OPCODE::INC16m_ND) + .value("INC16m_NF", LIEF::assembly::x86::OPCODE::INC16m_NF) + .value("INC16m_NF_ND", LIEF::assembly::x86::OPCODE::INC16m_NF_ND) + .value("INC16r", LIEF::assembly::x86::OPCODE::INC16r) + .value("INC16r_EVEX", LIEF::assembly::x86::OPCODE::INC16r_EVEX) + .value("INC16r_ND", LIEF::assembly::x86::OPCODE::INC16r_ND) + .value("INC16r_NF", LIEF::assembly::x86::OPCODE::INC16r_NF) + .value("INC16r_NF_ND", LIEF::assembly::x86::OPCODE::INC16r_NF_ND) + .value("INC16r_alt", LIEF::assembly::x86::OPCODE::INC16r_alt) + .value("INC32m", LIEF::assembly::x86::OPCODE::INC32m) + .value("INC32m_EVEX", LIEF::assembly::x86::OPCODE::INC32m_EVEX) + .value("INC32m_ND", LIEF::assembly::x86::OPCODE::INC32m_ND) + .value("INC32m_NF", LIEF::assembly::x86::OPCODE::INC32m_NF) + .value("INC32m_NF_ND", LIEF::assembly::x86::OPCODE::INC32m_NF_ND) + .value("INC32r", LIEF::assembly::x86::OPCODE::INC32r) + .value("INC32r_EVEX", LIEF::assembly::x86::OPCODE::INC32r_EVEX) + .value("INC32r_ND", LIEF::assembly::x86::OPCODE::INC32r_ND) + .value("INC32r_NF", LIEF::assembly::x86::OPCODE::INC32r_NF) + .value("INC32r_NF_ND", LIEF::assembly::x86::OPCODE::INC32r_NF_ND) + .value("INC32r_alt", LIEF::assembly::x86::OPCODE::INC32r_alt) + .value("INC64m", LIEF::assembly::x86::OPCODE::INC64m) + .value("INC64m_EVEX", LIEF::assembly::x86::OPCODE::INC64m_EVEX) + .value("INC64m_ND", LIEF::assembly::x86::OPCODE::INC64m_ND) + .value("INC64m_NF", LIEF::assembly::x86::OPCODE::INC64m_NF) + .value("INC64m_NF_ND", LIEF::assembly::x86::OPCODE::INC64m_NF_ND) + .value("INC64r", LIEF::assembly::x86::OPCODE::INC64r) + .value("INC64r_EVEX", LIEF::assembly::x86::OPCODE::INC64r_EVEX) + .value("INC64r_ND", LIEF::assembly::x86::OPCODE::INC64r_ND) + .value("INC64r_NF", LIEF::assembly::x86::OPCODE::INC64r_NF) + .value("INC64r_NF_ND", LIEF::assembly::x86::OPCODE::INC64r_NF_ND) + .value("INC8m", LIEF::assembly::x86::OPCODE::INC8m) + .value("INC8m_EVEX", LIEF::assembly::x86::OPCODE::INC8m_EVEX) + .value("INC8m_ND", LIEF::assembly::x86::OPCODE::INC8m_ND) + .value("INC8m_NF", LIEF::assembly::x86::OPCODE::INC8m_NF) + .value("INC8m_NF_ND", LIEF::assembly::x86::OPCODE::INC8m_NF_ND) + .value("INC8r", LIEF::assembly::x86::OPCODE::INC8r) + .value("INC8r_EVEX", LIEF::assembly::x86::OPCODE::INC8r_EVEX) + .value("INC8r_ND", LIEF::assembly::x86::OPCODE::INC8r_ND) + .value("INC8r_NF", LIEF::assembly::x86::OPCODE::INC8r_NF) + .value("INC8r_NF_ND", LIEF::assembly::x86::OPCODE::INC8r_NF_ND) + .value("INCSSPD", LIEF::assembly::x86::OPCODE::INCSSPD) + .value("INCSSPQ", LIEF::assembly::x86::OPCODE::INCSSPQ) + .value("INSB", LIEF::assembly::x86::OPCODE::INSB) + .value("INSERTPSrmi", LIEF::assembly::x86::OPCODE::INSERTPSrmi) + .value("INSERTPSrri", LIEF::assembly::x86::OPCODE::INSERTPSrri) + .value("INSERTQ", LIEF::assembly::x86::OPCODE::INSERTQ) + .value("INSERTQI", LIEF::assembly::x86::OPCODE::INSERTQI) + .value("INSL", LIEF::assembly::x86::OPCODE::INSL) + .value("INSW", LIEF::assembly::x86::OPCODE::INSW) + .value("INT", LIEF::assembly::x86::OPCODE::INT) + .value("INT3", LIEF::assembly::x86::OPCODE::INT3) + .value("INTO", LIEF::assembly::x86::OPCODE::INTO) + .value("INVD", LIEF::assembly::x86::OPCODE::INVD) + .value("INVEPT32", LIEF::assembly::x86::OPCODE::INVEPT32) + .value("INVEPT64", LIEF::assembly::x86::OPCODE::INVEPT64) + .value("INVEPT64_EVEX", LIEF::assembly::x86::OPCODE::INVEPT64_EVEX) + .value("INVLPG", LIEF::assembly::x86::OPCODE::INVLPG) + .value("INVLPGA32", LIEF::assembly::x86::OPCODE::INVLPGA32) + .value("INVLPGA64", LIEF::assembly::x86::OPCODE::INVLPGA64) + .value("INVLPGB32", LIEF::assembly::x86::OPCODE::INVLPGB32) + .value("INVLPGB64", LIEF::assembly::x86::OPCODE::INVLPGB64) + .value("INVPCID32", LIEF::assembly::x86::OPCODE::INVPCID32) + .value("INVPCID64", LIEF::assembly::x86::OPCODE::INVPCID64) + .value("INVPCID64_EVEX", LIEF::assembly::x86::OPCODE::INVPCID64_EVEX) + .value("INVVPID32", LIEF::assembly::x86::OPCODE::INVVPID32) + .value("INVVPID64", LIEF::assembly::x86::OPCODE::INVVPID64) + .value("INVVPID64_EVEX", LIEF::assembly::x86::OPCODE::INVVPID64_EVEX) + .value("IRET", LIEF::assembly::x86::OPCODE::IRET) + .value("IRET16", LIEF::assembly::x86::OPCODE::IRET16) + .value("IRET32", LIEF::assembly::x86::OPCODE::IRET32) + .value("IRET64", LIEF::assembly::x86::OPCODE::IRET64) + .value("ISTT_FP16m", LIEF::assembly::x86::OPCODE::ISTT_FP16m) + .value("ISTT_FP32m", LIEF::assembly::x86::OPCODE::ISTT_FP32m) + .value("ISTT_FP64m", LIEF::assembly::x86::OPCODE::ISTT_FP64m) + .value("ISTT_Fp16m32", LIEF::assembly::x86::OPCODE::ISTT_Fp16m32) + .value("ISTT_Fp16m64", LIEF::assembly::x86::OPCODE::ISTT_Fp16m64) + .value("ISTT_Fp16m80", LIEF::assembly::x86::OPCODE::ISTT_Fp16m80) + .value("ISTT_Fp32m32", LIEF::assembly::x86::OPCODE::ISTT_Fp32m32) + .value("ISTT_Fp32m64", LIEF::assembly::x86::OPCODE::ISTT_Fp32m64) + .value("ISTT_Fp32m80", LIEF::assembly::x86::OPCODE::ISTT_Fp32m80) + .value("ISTT_Fp64m32", LIEF::assembly::x86::OPCODE::ISTT_Fp64m32) + .value("ISTT_Fp64m64", LIEF::assembly::x86::OPCODE::ISTT_Fp64m64) + .value("ISTT_Fp64m80", LIEF::assembly::x86::OPCODE::ISTT_Fp64m80) + .value("IST_F16m", LIEF::assembly::x86::OPCODE::IST_F16m) + .value("IST_F32m", LIEF::assembly::x86::OPCODE::IST_F32m) + .value("IST_FP16m", LIEF::assembly::x86::OPCODE::IST_FP16m) + .value("IST_FP32m", LIEF::assembly::x86::OPCODE::IST_FP32m) + .value("IST_FP64m", LIEF::assembly::x86::OPCODE::IST_FP64m) + .value("IST_Fp16m32", LIEF::assembly::x86::OPCODE::IST_Fp16m32) + .value("IST_Fp16m64", LIEF::assembly::x86::OPCODE::IST_Fp16m64) + .value("IST_Fp16m80", LIEF::assembly::x86::OPCODE::IST_Fp16m80) + .value("IST_Fp32m32", LIEF::assembly::x86::OPCODE::IST_Fp32m32) + .value("IST_Fp32m64", LIEF::assembly::x86::OPCODE::IST_Fp32m64) + .value("IST_Fp32m80", LIEF::assembly::x86::OPCODE::IST_Fp32m80) + .value("IST_Fp64m32", LIEF::assembly::x86::OPCODE::IST_Fp64m32) + .value("IST_Fp64m64", LIEF::assembly::x86::OPCODE::IST_Fp64m64) + .value("IST_Fp64m80", LIEF::assembly::x86::OPCODE::IST_Fp64m80) + .value("Int_eh_sjlj_setup_dispatch", LIEF::assembly::x86::OPCODE::Int_eh_sjlj_setup_dispatch) + .value("JCC_1", LIEF::assembly::x86::OPCODE::JCC_1) + .value("JCC_2", LIEF::assembly::x86::OPCODE::JCC_2) + .value("JCC_4", LIEF::assembly::x86::OPCODE::JCC_4) + .value("JCXZ", LIEF::assembly::x86::OPCODE::JCXZ) + .value("JECXZ", LIEF::assembly::x86::OPCODE::JECXZ) + .value("JMP16m", LIEF::assembly::x86::OPCODE::JMP16m) + .value("JMP16m_NT", LIEF::assembly::x86::OPCODE::JMP16m_NT) + .value("JMP16r", LIEF::assembly::x86::OPCODE::JMP16r) + .value("JMP16r_NT", LIEF::assembly::x86::OPCODE::JMP16r_NT) + .value("JMP32m", LIEF::assembly::x86::OPCODE::JMP32m) + .value("JMP32m_NT", LIEF::assembly::x86::OPCODE::JMP32m_NT) + .value("JMP32r", LIEF::assembly::x86::OPCODE::JMP32r) + .value("JMP32r_NT", LIEF::assembly::x86::OPCODE::JMP32r_NT) + .value("JMP64m", LIEF::assembly::x86::OPCODE::JMP64m) + .value("JMP64m_NT", LIEF::assembly::x86::OPCODE::JMP64m_NT) + .value("JMP64m_REX", LIEF::assembly::x86::OPCODE::JMP64m_REX) + .value("JMP64r", LIEF::assembly::x86::OPCODE::JMP64r) + .value("JMP64r_NT", LIEF::assembly::x86::OPCODE::JMP64r_NT) + .value("JMP64r_REX", LIEF::assembly::x86::OPCODE::JMP64r_REX) + .value("JMPABS64i", LIEF::assembly::x86::OPCODE::JMPABS64i) + .value("JMP_1", LIEF::assembly::x86::OPCODE::JMP_1) + .value("JMP_2", LIEF::assembly::x86::OPCODE::JMP_2) + .value("JMP_4", LIEF::assembly::x86::OPCODE::JMP_4) + .value("JRCXZ", LIEF::assembly::x86::OPCODE::JRCXZ) + .value("KADDBkk", LIEF::assembly::x86::OPCODE::KADDBkk) + .value("KADDDkk", LIEF::assembly::x86::OPCODE::KADDDkk) + .value("KADDQkk", LIEF::assembly::x86::OPCODE::KADDQkk) + .value("KADDWkk", LIEF::assembly::x86::OPCODE::KADDWkk) + .value("KANDBkk", LIEF::assembly::x86::OPCODE::KANDBkk) + .value("KANDDkk", LIEF::assembly::x86::OPCODE::KANDDkk) + .value("KANDNBkk", LIEF::assembly::x86::OPCODE::KANDNBkk) + .value("KANDNDkk", LIEF::assembly::x86::OPCODE::KANDNDkk) + .value("KANDNQkk", LIEF::assembly::x86::OPCODE::KANDNQkk) + .value("KANDNWkk", LIEF::assembly::x86::OPCODE::KANDNWkk) + .value("KANDQkk", LIEF::assembly::x86::OPCODE::KANDQkk) + .value("KANDWkk", LIEF::assembly::x86::OPCODE::KANDWkk) + .value("KCFI_CHECK", LIEF::assembly::x86::OPCODE::KCFI_CHECK) + .value("KMOVBkk", LIEF::assembly::x86::OPCODE::KMOVBkk) + .value("KMOVBkk_EVEX", LIEF::assembly::x86::OPCODE::KMOVBkk_EVEX) + .value("KMOVBkm", LIEF::assembly::x86::OPCODE::KMOVBkm) + .value("KMOVBkm_EVEX", LIEF::assembly::x86::OPCODE::KMOVBkm_EVEX) + .value("KMOVBkr", LIEF::assembly::x86::OPCODE::KMOVBkr) + .value("KMOVBkr_EVEX", LIEF::assembly::x86::OPCODE::KMOVBkr_EVEX) + .value("KMOVBmk", LIEF::assembly::x86::OPCODE::KMOVBmk) + .value("KMOVBmk_EVEX", LIEF::assembly::x86::OPCODE::KMOVBmk_EVEX) + .value("KMOVBrk", LIEF::assembly::x86::OPCODE::KMOVBrk) + .value("KMOVBrk_EVEX", LIEF::assembly::x86::OPCODE::KMOVBrk_EVEX) + .value("KMOVDkk", LIEF::assembly::x86::OPCODE::KMOVDkk) + .value("KMOVDkk_EVEX", LIEF::assembly::x86::OPCODE::KMOVDkk_EVEX) + .value("KMOVDkm", LIEF::assembly::x86::OPCODE::KMOVDkm) + .value("KMOVDkm_EVEX", LIEF::assembly::x86::OPCODE::KMOVDkm_EVEX) + .value("KMOVDkr", LIEF::assembly::x86::OPCODE::KMOVDkr) + .value("KMOVDkr_EVEX", LIEF::assembly::x86::OPCODE::KMOVDkr_EVEX) + .value("KMOVDmk", LIEF::assembly::x86::OPCODE::KMOVDmk) + .value("KMOVDmk_EVEX", LIEF::assembly::x86::OPCODE::KMOVDmk_EVEX) + .value("KMOVDrk", LIEF::assembly::x86::OPCODE::KMOVDrk) + .value("KMOVDrk_EVEX", LIEF::assembly::x86::OPCODE::KMOVDrk_EVEX) + .value("KMOVQkk", LIEF::assembly::x86::OPCODE::KMOVQkk) + .value("KMOVQkk_EVEX", LIEF::assembly::x86::OPCODE::KMOVQkk_EVEX) + .value("KMOVQkm", LIEF::assembly::x86::OPCODE::KMOVQkm) + .value("KMOVQkm_EVEX", LIEF::assembly::x86::OPCODE::KMOVQkm_EVEX) + .value("KMOVQkr", LIEF::assembly::x86::OPCODE::KMOVQkr) + .value("KMOVQkr_EVEX", LIEF::assembly::x86::OPCODE::KMOVQkr_EVEX) + .value("KMOVQmk", LIEF::assembly::x86::OPCODE::KMOVQmk) + .value("KMOVQmk_EVEX", LIEF::assembly::x86::OPCODE::KMOVQmk_EVEX) + .value("KMOVQrk", LIEF::assembly::x86::OPCODE::KMOVQrk) + .value("KMOVQrk_EVEX", LIEF::assembly::x86::OPCODE::KMOVQrk_EVEX) + .value("KMOVWkk", LIEF::assembly::x86::OPCODE::KMOVWkk) + .value("KMOVWkk_EVEX", LIEF::assembly::x86::OPCODE::KMOVWkk_EVEX) + .value("KMOVWkm", LIEF::assembly::x86::OPCODE::KMOVWkm) + .value("KMOVWkm_EVEX", LIEF::assembly::x86::OPCODE::KMOVWkm_EVEX) + .value("KMOVWkr", LIEF::assembly::x86::OPCODE::KMOVWkr) + .value("KMOVWkr_EVEX", LIEF::assembly::x86::OPCODE::KMOVWkr_EVEX) + .value("KMOVWmk", LIEF::assembly::x86::OPCODE::KMOVWmk) + .value("KMOVWmk_EVEX", LIEF::assembly::x86::OPCODE::KMOVWmk_EVEX) + .value("KMOVWrk", LIEF::assembly::x86::OPCODE::KMOVWrk) + .value("KMOVWrk_EVEX", LIEF::assembly::x86::OPCODE::KMOVWrk_EVEX) + .value("KNOTBkk", LIEF::assembly::x86::OPCODE::KNOTBkk) + .value("KNOTDkk", LIEF::assembly::x86::OPCODE::KNOTDkk) + .value("KNOTQkk", LIEF::assembly::x86::OPCODE::KNOTQkk) + .value("KNOTWkk", LIEF::assembly::x86::OPCODE::KNOTWkk) + .value("KORBkk", LIEF::assembly::x86::OPCODE::KORBkk) + .value("KORDkk", LIEF::assembly::x86::OPCODE::KORDkk) + .value("KORQkk", LIEF::assembly::x86::OPCODE::KORQkk) + .value("KORTESTBkk", LIEF::assembly::x86::OPCODE::KORTESTBkk) + .value("KORTESTDkk", LIEF::assembly::x86::OPCODE::KORTESTDkk) + .value("KORTESTQkk", LIEF::assembly::x86::OPCODE::KORTESTQkk) + .value("KORTESTWkk", LIEF::assembly::x86::OPCODE::KORTESTWkk) + .value("KORWkk", LIEF::assembly::x86::OPCODE::KORWkk) + .value("KSHIFTLBki", LIEF::assembly::x86::OPCODE::KSHIFTLBki) + .value("KSHIFTLDki", LIEF::assembly::x86::OPCODE::KSHIFTLDki) + .value("KSHIFTLQki", LIEF::assembly::x86::OPCODE::KSHIFTLQki) + .value("KSHIFTLWki", LIEF::assembly::x86::OPCODE::KSHIFTLWki) + .value("KSHIFTRBki", LIEF::assembly::x86::OPCODE::KSHIFTRBki) + .value("KSHIFTRDki", LIEF::assembly::x86::OPCODE::KSHIFTRDki) + .value("KSHIFTRQki", LIEF::assembly::x86::OPCODE::KSHIFTRQki) + .value("KSHIFTRWki", LIEF::assembly::x86::OPCODE::KSHIFTRWki) + .value("KTESTBkk", LIEF::assembly::x86::OPCODE::KTESTBkk) + .value("KTESTDkk", LIEF::assembly::x86::OPCODE::KTESTDkk) + .value("KTESTQkk", LIEF::assembly::x86::OPCODE::KTESTQkk) + .value("KTESTWkk", LIEF::assembly::x86::OPCODE::KTESTWkk) + .value("KUNPCKBWkk", LIEF::assembly::x86::OPCODE::KUNPCKBWkk) + .value("KUNPCKDQkk", LIEF::assembly::x86::OPCODE::KUNPCKDQkk) + .value("KUNPCKWDkk", LIEF::assembly::x86::OPCODE::KUNPCKWDkk) + .value("KXNORBkk", LIEF::assembly::x86::OPCODE::KXNORBkk) + .value("KXNORDkk", LIEF::assembly::x86::OPCODE::KXNORDkk) + .value("KXNORQkk", LIEF::assembly::x86::OPCODE::KXNORQkk) + .value("KXNORWkk", LIEF::assembly::x86::OPCODE::KXNORWkk) + .value("KXORBkk", LIEF::assembly::x86::OPCODE::KXORBkk) + .value("KXORDkk", LIEF::assembly::x86::OPCODE::KXORDkk) + .value("KXORQkk", LIEF::assembly::x86::OPCODE::KXORQkk) + .value("KXORWkk", LIEF::assembly::x86::OPCODE::KXORWkk) + .value("LAHF", LIEF::assembly::x86::OPCODE::LAHF) + .value("LAR16rm", LIEF::assembly::x86::OPCODE::LAR16rm); + opcodes.value("LAR16rr", LIEF::assembly::x86::OPCODE::LAR16rr) + .value("LAR32rm", LIEF::assembly::x86::OPCODE::LAR32rm) + .value("LAR32rr", LIEF::assembly::x86::OPCODE::LAR32rr) + .value("LAR64rm", LIEF::assembly::x86::OPCODE::LAR64rm) + .value("LAR64rr", LIEF::assembly::x86::OPCODE::LAR64rr) + .value("LCMPXCHG16", LIEF::assembly::x86::OPCODE::LCMPXCHG16) + .value("LCMPXCHG16B", LIEF::assembly::x86::OPCODE::LCMPXCHG16B) + .value("LCMPXCHG32", LIEF::assembly::x86::OPCODE::LCMPXCHG32) + .value("LCMPXCHG64", LIEF::assembly::x86::OPCODE::LCMPXCHG64) + .value("LCMPXCHG8", LIEF::assembly::x86::OPCODE::LCMPXCHG8) + .value("LCMPXCHG8B", LIEF::assembly::x86::OPCODE::LCMPXCHG8B) + .value("LDDQUrm", LIEF::assembly::x86::OPCODE::LDDQUrm) + .value("LDMXCSR", LIEF::assembly::x86::OPCODE::LDMXCSR) + .value("LDS16rm", LIEF::assembly::x86::OPCODE::LDS16rm) + .value("LDS32rm", LIEF::assembly::x86::OPCODE::LDS32rm) + .value("LDTILECFG", LIEF::assembly::x86::OPCODE::LDTILECFG) + .value("LDTILECFG_EVEX", LIEF::assembly::x86::OPCODE::LDTILECFG_EVEX) + .value("LD_F0", LIEF::assembly::x86::OPCODE::LD_F0) + .value("LD_F1", LIEF::assembly::x86::OPCODE::LD_F1) + .value("LD_F32m", LIEF::assembly::x86::OPCODE::LD_F32m) + .value("LD_F64m", LIEF::assembly::x86::OPCODE::LD_F64m) + .value("LD_F80m", LIEF::assembly::x86::OPCODE::LD_F80m) + .value("LD_Fp032", LIEF::assembly::x86::OPCODE::LD_Fp032) + .value("LD_Fp064", LIEF::assembly::x86::OPCODE::LD_Fp064) + .value("LD_Fp080", LIEF::assembly::x86::OPCODE::LD_Fp080) + .value("LD_Fp132", LIEF::assembly::x86::OPCODE::LD_Fp132) + .value("LD_Fp164", LIEF::assembly::x86::OPCODE::LD_Fp164) + .value("LD_Fp180", LIEF::assembly::x86::OPCODE::LD_Fp180) + .value("LD_Fp32m", LIEF::assembly::x86::OPCODE::LD_Fp32m) + .value("LD_Fp32m64", LIEF::assembly::x86::OPCODE::LD_Fp32m64) + .value("LD_Fp32m80", LIEF::assembly::x86::OPCODE::LD_Fp32m80) + .value("LD_Fp64m", LIEF::assembly::x86::OPCODE::LD_Fp64m) + .value("LD_Fp64m80", LIEF::assembly::x86::OPCODE::LD_Fp64m80) + .value("LD_Fp80m", LIEF::assembly::x86::OPCODE::LD_Fp80m) + .value("LD_Frr", LIEF::assembly::x86::OPCODE::LD_Frr) + .value("LEA16r", LIEF::assembly::x86::OPCODE::LEA16r) + .value("LEA32r", LIEF::assembly::x86::OPCODE::LEA32r) + .value("LEA64_16r", LIEF::assembly::x86::OPCODE::LEA64_16r) + .value("LEA64_32r", LIEF::assembly::x86::OPCODE::LEA64_32r) + .value("LEA64_8r", LIEF::assembly::x86::OPCODE::LEA64_8r) + .value("LEA64r", LIEF::assembly::x86::OPCODE::LEA64r) + .value("LEAVE", LIEF::assembly::x86::OPCODE::LEAVE) + .value("LEAVE64", LIEF::assembly::x86::OPCODE::LEAVE64) + .value("LES16rm", LIEF::assembly::x86::OPCODE::LES16rm) + .value("LES32rm", LIEF::assembly::x86::OPCODE::LES32rm) + .value("LFENCE", LIEF::assembly::x86::OPCODE::LFENCE) + .value("LFS16rm", LIEF::assembly::x86::OPCODE::LFS16rm) + .value("LFS32rm", LIEF::assembly::x86::OPCODE::LFS32rm) + .value("LFS64rm", LIEF::assembly::x86::OPCODE::LFS64rm) + .value("LGDT16m", LIEF::assembly::x86::OPCODE::LGDT16m) + .value("LGDT32m", LIEF::assembly::x86::OPCODE::LGDT32m) + .value("LGDT64m", LIEF::assembly::x86::OPCODE::LGDT64m) + .value("LGS16rm", LIEF::assembly::x86::OPCODE::LGS16rm) + .value("LGS32rm", LIEF::assembly::x86::OPCODE::LGS32rm) + .value("LGS64rm", LIEF::assembly::x86::OPCODE::LGS64rm) + .value("LIDT16m", LIEF::assembly::x86::OPCODE::LIDT16m) + .value("LIDT32m", LIEF::assembly::x86::OPCODE::LIDT32m) + .value("LIDT64m", LIEF::assembly::x86::OPCODE::LIDT64m) + .value("LKGS16m", LIEF::assembly::x86::OPCODE::LKGS16m) + .value("LKGS16r", LIEF::assembly::x86::OPCODE::LKGS16r) + .value("LLDT16m", LIEF::assembly::x86::OPCODE::LLDT16m) + .value("LLDT16r", LIEF::assembly::x86::OPCODE::LLDT16r) + .value("LLWPCB", LIEF::assembly::x86::OPCODE::LLWPCB) + .value("LLWPCB64", LIEF::assembly::x86::OPCODE::LLWPCB64) + .value("LMSW16m", LIEF::assembly::x86::OPCODE::LMSW16m) + .value("LMSW16r", LIEF::assembly::x86::OPCODE::LMSW16r) + .value("LOADIWKEY", LIEF::assembly::x86::OPCODE::LOADIWKEY) + .value("LOCK_ADD16mi", LIEF::assembly::x86::OPCODE::LOCK_ADD16mi) + .value("LOCK_ADD16mi8", LIEF::assembly::x86::OPCODE::LOCK_ADD16mi8) + .value("LOCK_ADD16mr", LIEF::assembly::x86::OPCODE::LOCK_ADD16mr) + .value("LOCK_ADD32mi", LIEF::assembly::x86::OPCODE::LOCK_ADD32mi) + .value("LOCK_ADD32mi8", LIEF::assembly::x86::OPCODE::LOCK_ADD32mi8) + .value("LOCK_ADD32mr", LIEF::assembly::x86::OPCODE::LOCK_ADD32mr) + .value("LOCK_ADD64mi32", LIEF::assembly::x86::OPCODE::LOCK_ADD64mi32) + .value("LOCK_ADD64mi8", LIEF::assembly::x86::OPCODE::LOCK_ADD64mi8) + .value("LOCK_ADD64mr", LIEF::assembly::x86::OPCODE::LOCK_ADD64mr) + .value("LOCK_ADD8mi", LIEF::assembly::x86::OPCODE::LOCK_ADD8mi) + .value("LOCK_ADD8mr", LIEF::assembly::x86::OPCODE::LOCK_ADD8mr) + .value("LOCK_AND16mi", LIEF::assembly::x86::OPCODE::LOCK_AND16mi) + .value("LOCK_AND16mi8", LIEF::assembly::x86::OPCODE::LOCK_AND16mi8) + .value("LOCK_AND16mr", LIEF::assembly::x86::OPCODE::LOCK_AND16mr) + .value("LOCK_AND32mi", LIEF::assembly::x86::OPCODE::LOCK_AND32mi) + .value("LOCK_AND32mi8", LIEF::assembly::x86::OPCODE::LOCK_AND32mi8) + .value("LOCK_AND32mr", LIEF::assembly::x86::OPCODE::LOCK_AND32mr) + .value("LOCK_AND64mi32", LIEF::assembly::x86::OPCODE::LOCK_AND64mi32) + .value("LOCK_AND64mi8", LIEF::assembly::x86::OPCODE::LOCK_AND64mi8) + .value("LOCK_AND64mr", LIEF::assembly::x86::OPCODE::LOCK_AND64mr) + .value("LOCK_AND8mi", LIEF::assembly::x86::OPCODE::LOCK_AND8mi) + .value("LOCK_AND8mr", LIEF::assembly::x86::OPCODE::LOCK_AND8mr) + .value("LOCK_BTC16m", LIEF::assembly::x86::OPCODE::LOCK_BTC16m) + .value("LOCK_BTC32m", LIEF::assembly::x86::OPCODE::LOCK_BTC32m) + .value("LOCK_BTC64m", LIEF::assembly::x86::OPCODE::LOCK_BTC64m) + .value("LOCK_BTC_RM16rm", LIEF::assembly::x86::OPCODE::LOCK_BTC_RM16rm) + .value("LOCK_BTC_RM32rm", LIEF::assembly::x86::OPCODE::LOCK_BTC_RM32rm) + .value("LOCK_BTC_RM64rm", LIEF::assembly::x86::OPCODE::LOCK_BTC_RM64rm) + .value("LOCK_BTR16m", LIEF::assembly::x86::OPCODE::LOCK_BTR16m) + .value("LOCK_BTR32m", LIEF::assembly::x86::OPCODE::LOCK_BTR32m) + .value("LOCK_BTR64m", LIEF::assembly::x86::OPCODE::LOCK_BTR64m) + .value("LOCK_BTR_RM16rm", LIEF::assembly::x86::OPCODE::LOCK_BTR_RM16rm) + .value("LOCK_BTR_RM32rm", LIEF::assembly::x86::OPCODE::LOCK_BTR_RM32rm) + .value("LOCK_BTR_RM64rm", LIEF::assembly::x86::OPCODE::LOCK_BTR_RM64rm) + .value("LOCK_BTS16m", LIEF::assembly::x86::OPCODE::LOCK_BTS16m) + .value("LOCK_BTS32m", LIEF::assembly::x86::OPCODE::LOCK_BTS32m) + .value("LOCK_BTS64m", LIEF::assembly::x86::OPCODE::LOCK_BTS64m) + .value("LOCK_BTS_RM16rm", LIEF::assembly::x86::OPCODE::LOCK_BTS_RM16rm) + .value("LOCK_BTS_RM32rm", LIEF::assembly::x86::OPCODE::LOCK_BTS_RM32rm) + .value("LOCK_BTS_RM64rm", LIEF::assembly::x86::OPCODE::LOCK_BTS_RM64rm) + .value("LOCK_DEC16m", LIEF::assembly::x86::OPCODE::LOCK_DEC16m) + .value("LOCK_DEC32m", LIEF::assembly::x86::OPCODE::LOCK_DEC32m) + .value("LOCK_DEC64m", LIEF::assembly::x86::OPCODE::LOCK_DEC64m) + .value("LOCK_DEC8m", LIEF::assembly::x86::OPCODE::LOCK_DEC8m) + .value("LOCK_INC16m", LIEF::assembly::x86::OPCODE::LOCK_INC16m) + .value("LOCK_INC32m", LIEF::assembly::x86::OPCODE::LOCK_INC32m) + .value("LOCK_INC64m", LIEF::assembly::x86::OPCODE::LOCK_INC64m) + .value("LOCK_INC8m", LIEF::assembly::x86::OPCODE::LOCK_INC8m) + .value("LOCK_OR16mi", LIEF::assembly::x86::OPCODE::LOCK_OR16mi) + .value("LOCK_OR16mi8", LIEF::assembly::x86::OPCODE::LOCK_OR16mi8) + .value("LOCK_OR16mr", LIEF::assembly::x86::OPCODE::LOCK_OR16mr) + .value("LOCK_OR32mi", LIEF::assembly::x86::OPCODE::LOCK_OR32mi) + .value("LOCK_OR32mi8", LIEF::assembly::x86::OPCODE::LOCK_OR32mi8) + .value("LOCK_OR32mr", LIEF::assembly::x86::OPCODE::LOCK_OR32mr) + .value("LOCK_OR64mi32", LIEF::assembly::x86::OPCODE::LOCK_OR64mi32) + .value("LOCK_OR64mi8", LIEF::assembly::x86::OPCODE::LOCK_OR64mi8) + .value("LOCK_OR64mr", LIEF::assembly::x86::OPCODE::LOCK_OR64mr) + .value("LOCK_OR8mi", LIEF::assembly::x86::OPCODE::LOCK_OR8mi) + .value("LOCK_OR8mr", LIEF::assembly::x86::OPCODE::LOCK_OR8mr) + .value("LOCK_PREFIX", LIEF::assembly::x86::OPCODE::LOCK_PREFIX) + .value("LOCK_SUB16mi", LIEF::assembly::x86::OPCODE::LOCK_SUB16mi) + .value("LOCK_SUB16mi8", LIEF::assembly::x86::OPCODE::LOCK_SUB16mi8) + .value("LOCK_SUB16mr", LIEF::assembly::x86::OPCODE::LOCK_SUB16mr) + .value("LOCK_SUB32mi", LIEF::assembly::x86::OPCODE::LOCK_SUB32mi) + .value("LOCK_SUB32mi8", LIEF::assembly::x86::OPCODE::LOCK_SUB32mi8) + .value("LOCK_SUB32mr", LIEF::assembly::x86::OPCODE::LOCK_SUB32mr) + .value("LOCK_SUB64mi32", LIEF::assembly::x86::OPCODE::LOCK_SUB64mi32) + .value("LOCK_SUB64mi8", LIEF::assembly::x86::OPCODE::LOCK_SUB64mi8) + .value("LOCK_SUB64mr", LIEF::assembly::x86::OPCODE::LOCK_SUB64mr) + .value("LOCK_SUB8mi", LIEF::assembly::x86::OPCODE::LOCK_SUB8mi) + .value("LOCK_SUB8mr", LIEF::assembly::x86::OPCODE::LOCK_SUB8mr) + .value("LOCK_XOR16mi", LIEF::assembly::x86::OPCODE::LOCK_XOR16mi) + .value("LOCK_XOR16mi8", LIEF::assembly::x86::OPCODE::LOCK_XOR16mi8) + .value("LOCK_XOR16mr", LIEF::assembly::x86::OPCODE::LOCK_XOR16mr) + .value("LOCK_XOR32mi", LIEF::assembly::x86::OPCODE::LOCK_XOR32mi) + .value("LOCK_XOR32mi8", LIEF::assembly::x86::OPCODE::LOCK_XOR32mi8) + .value("LOCK_XOR32mr", LIEF::assembly::x86::OPCODE::LOCK_XOR32mr) + .value("LOCK_XOR64mi32", LIEF::assembly::x86::OPCODE::LOCK_XOR64mi32) + .value("LOCK_XOR64mi8", LIEF::assembly::x86::OPCODE::LOCK_XOR64mi8) + .value("LOCK_XOR64mr", LIEF::assembly::x86::OPCODE::LOCK_XOR64mr) + .value("LOCK_XOR8mi", LIEF::assembly::x86::OPCODE::LOCK_XOR8mi) + .value("LOCK_XOR8mr", LIEF::assembly::x86::OPCODE::LOCK_XOR8mr) + .value("LODSB", LIEF::assembly::x86::OPCODE::LODSB) + .value("LODSL", LIEF::assembly::x86::OPCODE::LODSL) + .value("LODSQ", LIEF::assembly::x86::OPCODE::LODSQ) + .value("LODSW", LIEF::assembly::x86::OPCODE::LODSW) + .value("LOOP", LIEF::assembly::x86::OPCODE::LOOP) + .value("LOOPE", LIEF::assembly::x86::OPCODE::LOOPE) + .value("LOOPNE", LIEF::assembly::x86::OPCODE::LOOPNE) + .value("LRET16", LIEF::assembly::x86::OPCODE::LRET16) + .value("LRET32", LIEF::assembly::x86::OPCODE::LRET32) + .value("LRET64", LIEF::assembly::x86::OPCODE::LRET64) + .value("LRETI16", LIEF::assembly::x86::OPCODE::LRETI16) + .value("LRETI32", LIEF::assembly::x86::OPCODE::LRETI32) + .value("LRETI64", LIEF::assembly::x86::OPCODE::LRETI64) + .value("LSL16rm", LIEF::assembly::x86::OPCODE::LSL16rm) + .value("LSL16rr", LIEF::assembly::x86::OPCODE::LSL16rr) + .value("LSL32rm", LIEF::assembly::x86::OPCODE::LSL32rm) + .value("LSL32rr", LIEF::assembly::x86::OPCODE::LSL32rr) + .value("LSL64rm", LIEF::assembly::x86::OPCODE::LSL64rm) + .value("LSL64rr", LIEF::assembly::x86::OPCODE::LSL64rr) + .value("LSS16rm", LIEF::assembly::x86::OPCODE::LSS16rm) + .value("LSS32rm", LIEF::assembly::x86::OPCODE::LSS32rm) + .value("LSS64rm", LIEF::assembly::x86::OPCODE::LSS64rm) + .value("LTRm", LIEF::assembly::x86::OPCODE::LTRm) + .value("LTRr", LIEF::assembly::x86::OPCODE::LTRr) + .value("LWPINS32rmi", LIEF::assembly::x86::OPCODE::LWPINS32rmi) + .value("LWPINS32rri", LIEF::assembly::x86::OPCODE::LWPINS32rri) + .value("LWPINS64rmi", LIEF::assembly::x86::OPCODE::LWPINS64rmi) + .value("LWPINS64rri", LIEF::assembly::x86::OPCODE::LWPINS64rri) + .value("LWPVAL32rmi", LIEF::assembly::x86::OPCODE::LWPVAL32rmi) + .value("LWPVAL32rri", LIEF::assembly::x86::OPCODE::LWPVAL32rri) + .value("LWPVAL64rmi", LIEF::assembly::x86::OPCODE::LWPVAL64rmi) + .value("LWPVAL64rri", LIEF::assembly::x86::OPCODE::LWPVAL64rri) + .value("LXADD16", LIEF::assembly::x86::OPCODE::LXADD16) + .value("LXADD32", LIEF::assembly::x86::OPCODE::LXADD32) + .value("LXADD64", LIEF::assembly::x86::OPCODE::LXADD64) + .value("LXADD8", LIEF::assembly::x86::OPCODE::LXADD8) + .value("LZCNT16rm", LIEF::assembly::x86::OPCODE::LZCNT16rm) + .value("LZCNT16rm_EVEX", LIEF::assembly::x86::OPCODE::LZCNT16rm_EVEX) + .value("LZCNT16rm_NF", LIEF::assembly::x86::OPCODE::LZCNT16rm_NF) + .value("LZCNT16rr", LIEF::assembly::x86::OPCODE::LZCNT16rr) + .value("LZCNT16rr_EVEX", LIEF::assembly::x86::OPCODE::LZCNT16rr_EVEX) + .value("LZCNT16rr_NF", LIEF::assembly::x86::OPCODE::LZCNT16rr_NF) + .value("LZCNT32rm", LIEF::assembly::x86::OPCODE::LZCNT32rm) + .value("LZCNT32rm_EVEX", LIEF::assembly::x86::OPCODE::LZCNT32rm_EVEX) + .value("LZCNT32rm_NF", LIEF::assembly::x86::OPCODE::LZCNT32rm_NF) + .value("LZCNT32rr", LIEF::assembly::x86::OPCODE::LZCNT32rr) + .value("LZCNT32rr_EVEX", LIEF::assembly::x86::OPCODE::LZCNT32rr_EVEX) + .value("LZCNT32rr_NF", LIEF::assembly::x86::OPCODE::LZCNT32rr_NF) + .value("LZCNT64rm", LIEF::assembly::x86::OPCODE::LZCNT64rm) + .value("LZCNT64rm_EVEX", LIEF::assembly::x86::OPCODE::LZCNT64rm_EVEX) + .value("LZCNT64rm_NF", LIEF::assembly::x86::OPCODE::LZCNT64rm_NF) + .value("LZCNT64rr", LIEF::assembly::x86::OPCODE::LZCNT64rr) + .value("LZCNT64rr_EVEX", LIEF::assembly::x86::OPCODE::LZCNT64rr_EVEX) + .value("LZCNT64rr_NF", LIEF::assembly::x86::OPCODE::LZCNT64rr_NF) + .value("MASKMOVDQU", LIEF::assembly::x86::OPCODE::MASKMOVDQU) + .value("MASKMOVDQU64", LIEF::assembly::x86::OPCODE::MASKMOVDQU64) + .value("MASKPAIR16LOAD", LIEF::assembly::x86::OPCODE::MASKPAIR16LOAD) + .value("MASKPAIR16STORE", LIEF::assembly::x86::OPCODE::MASKPAIR16STORE) + .value("MAXCPDrm", LIEF::assembly::x86::OPCODE::MAXCPDrm) + .value("MAXCPDrr", LIEF::assembly::x86::OPCODE::MAXCPDrr) + .value("MAXCPSrm", LIEF::assembly::x86::OPCODE::MAXCPSrm) + .value("MAXCPSrr", LIEF::assembly::x86::OPCODE::MAXCPSrr) + .value("MAXCSDrm", LIEF::assembly::x86::OPCODE::MAXCSDrm) + .value("MAXCSDrr", LIEF::assembly::x86::OPCODE::MAXCSDrr) + .value("MAXCSSrm", LIEF::assembly::x86::OPCODE::MAXCSSrm) + .value("MAXCSSrr", LIEF::assembly::x86::OPCODE::MAXCSSrr) + .value("MAXPDrm", LIEF::assembly::x86::OPCODE::MAXPDrm) + .value("MAXPDrr", LIEF::assembly::x86::OPCODE::MAXPDrr) + .value("MAXPSrm", LIEF::assembly::x86::OPCODE::MAXPSrm) + .value("MAXPSrr", LIEF::assembly::x86::OPCODE::MAXPSrr) + .value("MAXSDrm", LIEF::assembly::x86::OPCODE::MAXSDrm) + .value("MAXSDrm_Int", LIEF::assembly::x86::OPCODE::MAXSDrm_Int) + .value("MAXSDrr", LIEF::assembly::x86::OPCODE::MAXSDrr) + .value("MAXSDrr_Int", LIEF::assembly::x86::OPCODE::MAXSDrr_Int) + .value("MAXSSrm", LIEF::assembly::x86::OPCODE::MAXSSrm) + .value("MAXSSrm_Int", LIEF::assembly::x86::OPCODE::MAXSSrm_Int) + .value("MAXSSrr", LIEF::assembly::x86::OPCODE::MAXSSrr) + .value("MAXSSrr_Int", LIEF::assembly::x86::OPCODE::MAXSSrr_Int) + .value("MFENCE", LIEF::assembly::x86::OPCODE::MFENCE) + .value("MINCPDrm", LIEF::assembly::x86::OPCODE::MINCPDrm) + .value("MINCPDrr", LIEF::assembly::x86::OPCODE::MINCPDrr) + .value("MINCPSrm", LIEF::assembly::x86::OPCODE::MINCPSrm) + .value("MINCPSrr", LIEF::assembly::x86::OPCODE::MINCPSrr) + .value("MINCSDrm", LIEF::assembly::x86::OPCODE::MINCSDrm) + .value("MINCSDrr", LIEF::assembly::x86::OPCODE::MINCSDrr) + .value("MINCSSrm", LIEF::assembly::x86::OPCODE::MINCSSrm) + .value("MINCSSrr", LIEF::assembly::x86::OPCODE::MINCSSrr) + .value("MINPDrm", LIEF::assembly::x86::OPCODE::MINPDrm) + .value("MINPDrr", LIEF::assembly::x86::OPCODE::MINPDrr) + .value("MINPSrm", LIEF::assembly::x86::OPCODE::MINPSrm) + .value("MINPSrr", LIEF::assembly::x86::OPCODE::MINPSrr) + .value("MINSDrm", LIEF::assembly::x86::OPCODE::MINSDrm) + .value("MINSDrm_Int", LIEF::assembly::x86::OPCODE::MINSDrm_Int) + .value("MINSDrr", LIEF::assembly::x86::OPCODE::MINSDrr) + .value("MINSDrr_Int", LIEF::assembly::x86::OPCODE::MINSDrr_Int) + .value("MINSSrm", LIEF::assembly::x86::OPCODE::MINSSrm) + .value("MINSSrm_Int", LIEF::assembly::x86::OPCODE::MINSSrm_Int) + .value("MINSSrr", LIEF::assembly::x86::OPCODE::MINSSrr) + .value("MINSSrr_Int", LIEF::assembly::x86::OPCODE::MINSSrr_Int) + .value("MMX_CVTPD2PIrm", LIEF::assembly::x86::OPCODE::MMX_CVTPD2PIrm) + .value("MMX_CVTPD2PIrr", LIEF::assembly::x86::OPCODE::MMX_CVTPD2PIrr) + .value("MMX_CVTPI2PDrm", LIEF::assembly::x86::OPCODE::MMX_CVTPI2PDrm) + .value("MMX_CVTPI2PDrr", LIEF::assembly::x86::OPCODE::MMX_CVTPI2PDrr) + .value("MMX_CVTPI2PSrm", LIEF::assembly::x86::OPCODE::MMX_CVTPI2PSrm) + .value("MMX_CVTPI2PSrr", LIEF::assembly::x86::OPCODE::MMX_CVTPI2PSrr) + .value("MMX_CVTPS2PIrm", LIEF::assembly::x86::OPCODE::MMX_CVTPS2PIrm) + .value("MMX_CVTPS2PIrr", LIEF::assembly::x86::OPCODE::MMX_CVTPS2PIrr) + .value("MMX_CVTTPD2PIrm", LIEF::assembly::x86::OPCODE::MMX_CVTTPD2PIrm) + .value("MMX_CVTTPD2PIrr", LIEF::assembly::x86::OPCODE::MMX_CVTTPD2PIrr) + .value("MMX_CVTTPS2PIrm", LIEF::assembly::x86::OPCODE::MMX_CVTTPS2PIrm) + .value("MMX_CVTTPS2PIrr", LIEF::assembly::x86::OPCODE::MMX_CVTTPS2PIrr) + .value("MMX_EMMS", LIEF::assembly::x86::OPCODE::MMX_EMMS) + .value("MMX_MASKMOVQ", LIEF::assembly::x86::OPCODE::MMX_MASKMOVQ) + .value("MMX_MASKMOVQ64", LIEF::assembly::x86::OPCODE::MMX_MASKMOVQ64) + .value("MMX_MOVD64from64mr", LIEF::assembly::x86::OPCODE::MMX_MOVD64from64mr) + .value("MMX_MOVD64from64rr", LIEF::assembly::x86::OPCODE::MMX_MOVD64from64rr) + .value("MMX_MOVD64grr", LIEF::assembly::x86::OPCODE::MMX_MOVD64grr) + .value("MMX_MOVD64mr", LIEF::assembly::x86::OPCODE::MMX_MOVD64mr) + .value("MMX_MOVD64rm", LIEF::assembly::x86::OPCODE::MMX_MOVD64rm) + .value("MMX_MOVD64rr", LIEF::assembly::x86::OPCODE::MMX_MOVD64rr) + .value("MMX_MOVD64to64rm", LIEF::assembly::x86::OPCODE::MMX_MOVD64to64rm) + .value("MMX_MOVD64to64rr", LIEF::assembly::x86::OPCODE::MMX_MOVD64to64rr) + .value("MMX_MOVDQ2Qrr", LIEF::assembly::x86::OPCODE::MMX_MOVDQ2Qrr) + .value("MMX_MOVFR642Qrr", LIEF::assembly::x86::OPCODE::MMX_MOVFR642Qrr) + .value("MMX_MOVNTQmr", LIEF::assembly::x86::OPCODE::MMX_MOVNTQmr) + .value("MMX_MOVQ2DQrr", LIEF::assembly::x86::OPCODE::MMX_MOVQ2DQrr) + .value("MMX_MOVQ2FR64rr", LIEF::assembly::x86::OPCODE::MMX_MOVQ2FR64rr) + .value("MMX_MOVQ64mr", LIEF::assembly::x86::OPCODE::MMX_MOVQ64mr) + .value("MMX_MOVQ64rm", LIEF::assembly::x86::OPCODE::MMX_MOVQ64rm) + .value("MMX_MOVQ64rr", LIEF::assembly::x86::OPCODE::MMX_MOVQ64rr) + .value("MMX_MOVQ64rr_REV", LIEF::assembly::x86::OPCODE::MMX_MOVQ64rr_REV) + .value("MMX_PABSBrm", LIEF::assembly::x86::OPCODE::MMX_PABSBrm) + .value("MMX_PABSBrr", LIEF::assembly::x86::OPCODE::MMX_PABSBrr) + .value("MMX_PABSDrm", LIEF::assembly::x86::OPCODE::MMX_PABSDrm) + .value("MMX_PABSDrr", LIEF::assembly::x86::OPCODE::MMX_PABSDrr) + .value("MMX_PABSWrm", LIEF::assembly::x86::OPCODE::MMX_PABSWrm) + .value("MMX_PABSWrr", LIEF::assembly::x86::OPCODE::MMX_PABSWrr) + .value("MMX_PACKSSDWrm", LIEF::assembly::x86::OPCODE::MMX_PACKSSDWrm) + .value("MMX_PACKSSDWrr", LIEF::assembly::x86::OPCODE::MMX_PACKSSDWrr) + .value("MMX_PACKSSWBrm", LIEF::assembly::x86::OPCODE::MMX_PACKSSWBrm) + .value("MMX_PACKSSWBrr", LIEF::assembly::x86::OPCODE::MMX_PACKSSWBrr) + .value("MMX_PACKUSWBrm", LIEF::assembly::x86::OPCODE::MMX_PACKUSWBrm) + .value("MMX_PACKUSWBrr", LIEF::assembly::x86::OPCODE::MMX_PACKUSWBrr) + .value("MMX_PADDBrm", LIEF::assembly::x86::OPCODE::MMX_PADDBrm) + .value("MMX_PADDBrr", LIEF::assembly::x86::OPCODE::MMX_PADDBrr) + .value("MMX_PADDDrm", LIEF::assembly::x86::OPCODE::MMX_PADDDrm) + .value("MMX_PADDDrr", LIEF::assembly::x86::OPCODE::MMX_PADDDrr) + .value("MMX_PADDQrm", LIEF::assembly::x86::OPCODE::MMX_PADDQrm) + .value("MMX_PADDQrr", LIEF::assembly::x86::OPCODE::MMX_PADDQrr) + .value("MMX_PADDSBrm", LIEF::assembly::x86::OPCODE::MMX_PADDSBrm) + .value("MMX_PADDSBrr", LIEF::assembly::x86::OPCODE::MMX_PADDSBrr); + opcodes.value("MMX_PADDSWrm", LIEF::assembly::x86::OPCODE::MMX_PADDSWrm) + .value("MMX_PADDSWrr", LIEF::assembly::x86::OPCODE::MMX_PADDSWrr) + .value("MMX_PADDUSBrm", LIEF::assembly::x86::OPCODE::MMX_PADDUSBrm) + .value("MMX_PADDUSBrr", LIEF::assembly::x86::OPCODE::MMX_PADDUSBrr) + .value("MMX_PADDUSWrm", LIEF::assembly::x86::OPCODE::MMX_PADDUSWrm) + .value("MMX_PADDUSWrr", LIEF::assembly::x86::OPCODE::MMX_PADDUSWrr) + .value("MMX_PADDWrm", LIEF::assembly::x86::OPCODE::MMX_PADDWrm) + .value("MMX_PADDWrr", LIEF::assembly::x86::OPCODE::MMX_PADDWrr) + .value("MMX_PALIGNRrmi", LIEF::assembly::x86::OPCODE::MMX_PALIGNRrmi) + .value("MMX_PALIGNRrri", LIEF::assembly::x86::OPCODE::MMX_PALIGNRrri) + .value("MMX_PANDNrm", LIEF::assembly::x86::OPCODE::MMX_PANDNrm) + .value("MMX_PANDNrr", LIEF::assembly::x86::OPCODE::MMX_PANDNrr) + .value("MMX_PANDrm", LIEF::assembly::x86::OPCODE::MMX_PANDrm) + .value("MMX_PANDrr", LIEF::assembly::x86::OPCODE::MMX_PANDrr) + .value("MMX_PAVGBrm", LIEF::assembly::x86::OPCODE::MMX_PAVGBrm) + .value("MMX_PAVGBrr", LIEF::assembly::x86::OPCODE::MMX_PAVGBrr) + .value("MMX_PAVGWrm", LIEF::assembly::x86::OPCODE::MMX_PAVGWrm) + .value("MMX_PAVGWrr", LIEF::assembly::x86::OPCODE::MMX_PAVGWrr) + .value("MMX_PCMPEQBrm", LIEF::assembly::x86::OPCODE::MMX_PCMPEQBrm) + .value("MMX_PCMPEQBrr", LIEF::assembly::x86::OPCODE::MMX_PCMPEQBrr) + .value("MMX_PCMPEQDrm", LIEF::assembly::x86::OPCODE::MMX_PCMPEQDrm) + .value("MMX_PCMPEQDrr", LIEF::assembly::x86::OPCODE::MMX_PCMPEQDrr) + .value("MMX_PCMPEQWrm", LIEF::assembly::x86::OPCODE::MMX_PCMPEQWrm) + .value("MMX_PCMPEQWrr", LIEF::assembly::x86::OPCODE::MMX_PCMPEQWrr) + .value("MMX_PCMPGTBrm", LIEF::assembly::x86::OPCODE::MMX_PCMPGTBrm) + .value("MMX_PCMPGTBrr", LIEF::assembly::x86::OPCODE::MMX_PCMPGTBrr) + .value("MMX_PCMPGTDrm", LIEF::assembly::x86::OPCODE::MMX_PCMPGTDrm) + .value("MMX_PCMPGTDrr", LIEF::assembly::x86::OPCODE::MMX_PCMPGTDrr) + .value("MMX_PCMPGTWrm", LIEF::assembly::x86::OPCODE::MMX_PCMPGTWrm) + .value("MMX_PCMPGTWrr", LIEF::assembly::x86::OPCODE::MMX_PCMPGTWrr) + .value("MMX_PEXTRWrri", LIEF::assembly::x86::OPCODE::MMX_PEXTRWrri) + .value("MMX_PHADDDrm", LIEF::assembly::x86::OPCODE::MMX_PHADDDrm) + .value("MMX_PHADDDrr", LIEF::assembly::x86::OPCODE::MMX_PHADDDrr) + .value("MMX_PHADDSWrm", LIEF::assembly::x86::OPCODE::MMX_PHADDSWrm) + .value("MMX_PHADDSWrr", LIEF::assembly::x86::OPCODE::MMX_PHADDSWrr) + .value("MMX_PHADDWrm", LIEF::assembly::x86::OPCODE::MMX_PHADDWrm) + .value("MMX_PHADDWrr", LIEF::assembly::x86::OPCODE::MMX_PHADDWrr) + .value("MMX_PHSUBDrm", LIEF::assembly::x86::OPCODE::MMX_PHSUBDrm) + .value("MMX_PHSUBDrr", LIEF::assembly::x86::OPCODE::MMX_PHSUBDrr) + .value("MMX_PHSUBSWrm", LIEF::assembly::x86::OPCODE::MMX_PHSUBSWrm) + .value("MMX_PHSUBSWrr", LIEF::assembly::x86::OPCODE::MMX_PHSUBSWrr) + .value("MMX_PHSUBWrm", LIEF::assembly::x86::OPCODE::MMX_PHSUBWrm) + .value("MMX_PHSUBWrr", LIEF::assembly::x86::OPCODE::MMX_PHSUBWrr) + .value("MMX_PINSRWrmi", LIEF::assembly::x86::OPCODE::MMX_PINSRWrmi) + .value("MMX_PINSRWrri", LIEF::assembly::x86::OPCODE::MMX_PINSRWrri) + .value("MMX_PMADDUBSWrm", LIEF::assembly::x86::OPCODE::MMX_PMADDUBSWrm) + .value("MMX_PMADDUBSWrr", LIEF::assembly::x86::OPCODE::MMX_PMADDUBSWrr) + .value("MMX_PMADDWDrm", LIEF::assembly::x86::OPCODE::MMX_PMADDWDrm) + .value("MMX_PMADDWDrr", LIEF::assembly::x86::OPCODE::MMX_PMADDWDrr) + .value("MMX_PMAXSWrm", LIEF::assembly::x86::OPCODE::MMX_PMAXSWrm) + .value("MMX_PMAXSWrr", LIEF::assembly::x86::OPCODE::MMX_PMAXSWrr) + .value("MMX_PMAXUBrm", LIEF::assembly::x86::OPCODE::MMX_PMAXUBrm) + .value("MMX_PMAXUBrr", LIEF::assembly::x86::OPCODE::MMX_PMAXUBrr) + .value("MMX_PMINSWrm", LIEF::assembly::x86::OPCODE::MMX_PMINSWrm) + .value("MMX_PMINSWrr", LIEF::assembly::x86::OPCODE::MMX_PMINSWrr) + .value("MMX_PMINUBrm", LIEF::assembly::x86::OPCODE::MMX_PMINUBrm) + .value("MMX_PMINUBrr", LIEF::assembly::x86::OPCODE::MMX_PMINUBrr) + .value("MMX_PMOVMSKBrr", LIEF::assembly::x86::OPCODE::MMX_PMOVMSKBrr) + .value("MMX_PMULHRSWrm", LIEF::assembly::x86::OPCODE::MMX_PMULHRSWrm) + .value("MMX_PMULHRSWrr", LIEF::assembly::x86::OPCODE::MMX_PMULHRSWrr) + .value("MMX_PMULHUWrm", LIEF::assembly::x86::OPCODE::MMX_PMULHUWrm) + .value("MMX_PMULHUWrr", LIEF::assembly::x86::OPCODE::MMX_PMULHUWrr) + .value("MMX_PMULHWrm", LIEF::assembly::x86::OPCODE::MMX_PMULHWrm) + .value("MMX_PMULHWrr", LIEF::assembly::x86::OPCODE::MMX_PMULHWrr) + .value("MMX_PMULLWrm", LIEF::assembly::x86::OPCODE::MMX_PMULLWrm) + .value("MMX_PMULLWrr", LIEF::assembly::x86::OPCODE::MMX_PMULLWrr) + .value("MMX_PMULUDQrm", LIEF::assembly::x86::OPCODE::MMX_PMULUDQrm) + .value("MMX_PMULUDQrr", LIEF::assembly::x86::OPCODE::MMX_PMULUDQrr) + .value("MMX_PORrm", LIEF::assembly::x86::OPCODE::MMX_PORrm) + .value("MMX_PORrr", LIEF::assembly::x86::OPCODE::MMX_PORrr) + .value("MMX_PSADBWrm", LIEF::assembly::x86::OPCODE::MMX_PSADBWrm) + .value("MMX_PSADBWrr", LIEF::assembly::x86::OPCODE::MMX_PSADBWrr) + .value("MMX_PSHUFBrm", LIEF::assembly::x86::OPCODE::MMX_PSHUFBrm) + .value("MMX_PSHUFBrr", LIEF::assembly::x86::OPCODE::MMX_PSHUFBrr) + .value("MMX_PSHUFWmi", LIEF::assembly::x86::OPCODE::MMX_PSHUFWmi) + .value("MMX_PSHUFWri", LIEF::assembly::x86::OPCODE::MMX_PSHUFWri) + .value("MMX_PSIGNBrm", LIEF::assembly::x86::OPCODE::MMX_PSIGNBrm) + .value("MMX_PSIGNBrr", LIEF::assembly::x86::OPCODE::MMX_PSIGNBrr) + .value("MMX_PSIGNDrm", LIEF::assembly::x86::OPCODE::MMX_PSIGNDrm) + .value("MMX_PSIGNDrr", LIEF::assembly::x86::OPCODE::MMX_PSIGNDrr) + .value("MMX_PSIGNWrm", LIEF::assembly::x86::OPCODE::MMX_PSIGNWrm) + .value("MMX_PSIGNWrr", LIEF::assembly::x86::OPCODE::MMX_PSIGNWrr) + .value("MMX_PSLLDri", LIEF::assembly::x86::OPCODE::MMX_PSLLDri) + .value("MMX_PSLLDrm", LIEF::assembly::x86::OPCODE::MMX_PSLLDrm) + .value("MMX_PSLLDrr", LIEF::assembly::x86::OPCODE::MMX_PSLLDrr) + .value("MMX_PSLLQri", LIEF::assembly::x86::OPCODE::MMX_PSLLQri) + .value("MMX_PSLLQrm", LIEF::assembly::x86::OPCODE::MMX_PSLLQrm) + .value("MMX_PSLLQrr", LIEF::assembly::x86::OPCODE::MMX_PSLLQrr) + .value("MMX_PSLLWri", LIEF::assembly::x86::OPCODE::MMX_PSLLWri) + .value("MMX_PSLLWrm", LIEF::assembly::x86::OPCODE::MMX_PSLLWrm) + .value("MMX_PSLLWrr", LIEF::assembly::x86::OPCODE::MMX_PSLLWrr) + .value("MMX_PSRADri", LIEF::assembly::x86::OPCODE::MMX_PSRADri) + .value("MMX_PSRADrm", LIEF::assembly::x86::OPCODE::MMX_PSRADrm) + .value("MMX_PSRADrr", LIEF::assembly::x86::OPCODE::MMX_PSRADrr) + .value("MMX_PSRAWri", LIEF::assembly::x86::OPCODE::MMX_PSRAWri) + .value("MMX_PSRAWrm", LIEF::assembly::x86::OPCODE::MMX_PSRAWrm) + .value("MMX_PSRAWrr", LIEF::assembly::x86::OPCODE::MMX_PSRAWrr) + .value("MMX_PSRLDri", LIEF::assembly::x86::OPCODE::MMX_PSRLDri) + .value("MMX_PSRLDrm", LIEF::assembly::x86::OPCODE::MMX_PSRLDrm) + .value("MMX_PSRLDrr", LIEF::assembly::x86::OPCODE::MMX_PSRLDrr) + .value("MMX_PSRLQri", LIEF::assembly::x86::OPCODE::MMX_PSRLQri) + .value("MMX_PSRLQrm", LIEF::assembly::x86::OPCODE::MMX_PSRLQrm) + .value("MMX_PSRLQrr", LIEF::assembly::x86::OPCODE::MMX_PSRLQrr) + .value("MMX_PSRLWri", LIEF::assembly::x86::OPCODE::MMX_PSRLWri) + .value("MMX_PSRLWrm", LIEF::assembly::x86::OPCODE::MMX_PSRLWrm) + .value("MMX_PSRLWrr", LIEF::assembly::x86::OPCODE::MMX_PSRLWrr) + .value("MMX_PSUBBrm", LIEF::assembly::x86::OPCODE::MMX_PSUBBrm) + .value("MMX_PSUBBrr", LIEF::assembly::x86::OPCODE::MMX_PSUBBrr) + .value("MMX_PSUBDrm", LIEF::assembly::x86::OPCODE::MMX_PSUBDrm) + .value("MMX_PSUBDrr", LIEF::assembly::x86::OPCODE::MMX_PSUBDrr) + .value("MMX_PSUBQrm", LIEF::assembly::x86::OPCODE::MMX_PSUBQrm) + .value("MMX_PSUBQrr", LIEF::assembly::x86::OPCODE::MMX_PSUBQrr) + .value("MMX_PSUBSBrm", LIEF::assembly::x86::OPCODE::MMX_PSUBSBrm) + .value("MMX_PSUBSBrr", LIEF::assembly::x86::OPCODE::MMX_PSUBSBrr) + .value("MMX_PSUBSWrm", LIEF::assembly::x86::OPCODE::MMX_PSUBSWrm) + .value("MMX_PSUBSWrr", LIEF::assembly::x86::OPCODE::MMX_PSUBSWrr) + .value("MMX_PSUBUSBrm", LIEF::assembly::x86::OPCODE::MMX_PSUBUSBrm) + .value("MMX_PSUBUSBrr", LIEF::assembly::x86::OPCODE::MMX_PSUBUSBrr) + .value("MMX_PSUBUSWrm", LIEF::assembly::x86::OPCODE::MMX_PSUBUSWrm) + .value("MMX_PSUBUSWrr", LIEF::assembly::x86::OPCODE::MMX_PSUBUSWrr) + .value("MMX_PSUBWrm", LIEF::assembly::x86::OPCODE::MMX_PSUBWrm) + .value("MMX_PSUBWrr", LIEF::assembly::x86::OPCODE::MMX_PSUBWrr) + .value("MMX_PUNPCKHBWrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHBWrm) + .value("MMX_PUNPCKHBWrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHBWrr) + .value("MMX_PUNPCKHDQrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHDQrm) + .value("MMX_PUNPCKHDQrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHDQrr) + .value("MMX_PUNPCKHWDrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHWDrm) + .value("MMX_PUNPCKHWDrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKHWDrr) + .value("MMX_PUNPCKLBWrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLBWrm) + .value("MMX_PUNPCKLBWrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLBWrr) + .value("MMX_PUNPCKLDQrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLDQrm) + .value("MMX_PUNPCKLDQrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLDQrr) + .value("MMX_PUNPCKLWDrm", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLWDrm) + .value("MMX_PUNPCKLWDrr", LIEF::assembly::x86::OPCODE::MMX_PUNPCKLWDrr) + .value("MMX_PXORrm", LIEF::assembly::x86::OPCODE::MMX_PXORrm) + .value("MMX_PXORrr", LIEF::assembly::x86::OPCODE::MMX_PXORrr) + .value("MONITOR32rrr", LIEF::assembly::x86::OPCODE::MONITOR32rrr) + .value("MONITOR64rrr", LIEF::assembly::x86::OPCODE::MONITOR64rrr) + .value("MONITORX32rrr", LIEF::assembly::x86::OPCODE::MONITORX32rrr) + .value("MONITORX64rrr", LIEF::assembly::x86::OPCODE::MONITORX64rrr) + .value("MONTMUL", LIEF::assembly::x86::OPCODE::MONTMUL) + .value("MOV16ao16", LIEF::assembly::x86::OPCODE::MOV16ao16) + .value("MOV16ao32", LIEF::assembly::x86::OPCODE::MOV16ao32) + .value("MOV16ao64", LIEF::assembly::x86::OPCODE::MOV16ao64) + .value("MOV16mi", LIEF::assembly::x86::OPCODE::MOV16mi) + .value("MOV16mr", LIEF::assembly::x86::OPCODE::MOV16mr) + .value("MOV16ms", LIEF::assembly::x86::OPCODE::MOV16ms) + .value("MOV16o16a", LIEF::assembly::x86::OPCODE::MOV16o16a) + .value("MOV16o32a", LIEF::assembly::x86::OPCODE::MOV16o32a) + .value("MOV16o64a", LIEF::assembly::x86::OPCODE::MOV16o64a) + .value("MOV16ri", LIEF::assembly::x86::OPCODE::MOV16ri) + .value("MOV16ri_alt", LIEF::assembly::x86::OPCODE::MOV16ri_alt) + .value("MOV16rm", LIEF::assembly::x86::OPCODE::MOV16rm) + .value("MOV16rr", LIEF::assembly::x86::OPCODE::MOV16rr) + .value("MOV16rr_REV", LIEF::assembly::x86::OPCODE::MOV16rr_REV) + .value("MOV16rs", LIEF::assembly::x86::OPCODE::MOV16rs) + .value("MOV16sm", LIEF::assembly::x86::OPCODE::MOV16sm) + .value("MOV16sr", LIEF::assembly::x86::OPCODE::MOV16sr) + .value("MOV32ao16", LIEF::assembly::x86::OPCODE::MOV32ao16) + .value("MOV32ao32", LIEF::assembly::x86::OPCODE::MOV32ao32) + .value("MOV32ao64", LIEF::assembly::x86::OPCODE::MOV32ao64) + .value("MOV32cr", LIEF::assembly::x86::OPCODE::MOV32cr) + .value("MOV32dr", LIEF::assembly::x86::OPCODE::MOV32dr) + .value("MOV32mi", LIEF::assembly::x86::OPCODE::MOV32mi) + .value("MOV32mr", LIEF::assembly::x86::OPCODE::MOV32mr) + .value("MOV32o16a", LIEF::assembly::x86::OPCODE::MOV32o16a) + .value("MOV32o32a", LIEF::assembly::x86::OPCODE::MOV32o32a) + .value("MOV32o64a", LIEF::assembly::x86::OPCODE::MOV32o64a) + .value("MOV32rc", LIEF::assembly::x86::OPCODE::MOV32rc) + .value("MOV32rd", LIEF::assembly::x86::OPCODE::MOV32rd) + .value("MOV32ri", LIEF::assembly::x86::OPCODE::MOV32ri) + .value("MOV32ri_alt", LIEF::assembly::x86::OPCODE::MOV32ri_alt) + .value("MOV32rm", LIEF::assembly::x86::OPCODE::MOV32rm) + .value("MOV32rr", LIEF::assembly::x86::OPCODE::MOV32rr) + .value("MOV32rr_REV", LIEF::assembly::x86::OPCODE::MOV32rr_REV) + .value("MOV32rs", LIEF::assembly::x86::OPCODE::MOV32rs) + .value("MOV32sr", LIEF::assembly::x86::OPCODE::MOV32sr) + .value("MOV64ao32", LIEF::assembly::x86::OPCODE::MOV64ao32) + .value("MOV64ao64", LIEF::assembly::x86::OPCODE::MOV64ao64) + .value("MOV64cr", LIEF::assembly::x86::OPCODE::MOV64cr) + .value("MOV64dr", LIEF::assembly::x86::OPCODE::MOV64dr) + .value("MOV64mi32", LIEF::assembly::x86::OPCODE::MOV64mi32) + .value("MOV64mr", LIEF::assembly::x86::OPCODE::MOV64mr) + .value("MOV64o32a", LIEF::assembly::x86::OPCODE::MOV64o32a) + .value("MOV64o64a", LIEF::assembly::x86::OPCODE::MOV64o64a) + .value("MOV64rc", LIEF::assembly::x86::OPCODE::MOV64rc) + .value("MOV64rd", LIEF::assembly::x86::OPCODE::MOV64rd) + .value("MOV64ri", LIEF::assembly::x86::OPCODE::MOV64ri) + .value("MOV64ri32", LIEF::assembly::x86::OPCODE::MOV64ri32) + .value("MOV64rm", LIEF::assembly::x86::OPCODE::MOV64rm) + .value("MOV64rr", LIEF::assembly::x86::OPCODE::MOV64rr) + .value("MOV64rr_REV", LIEF::assembly::x86::OPCODE::MOV64rr_REV) + .value("MOV64rs", LIEF::assembly::x86::OPCODE::MOV64rs) + .value("MOV64sr", LIEF::assembly::x86::OPCODE::MOV64sr) + .value("MOV64toPQIrm", LIEF::assembly::x86::OPCODE::MOV64toPQIrm) + .value("MOV64toPQIrr", LIEF::assembly::x86::OPCODE::MOV64toPQIrr) + .value("MOV64toSDrr", LIEF::assembly::x86::OPCODE::MOV64toSDrr) + .value("MOV8ao16", LIEF::assembly::x86::OPCODE::MOV8ao16) + .value("MOV8ao32", LIEF::assembly::x86::OPCODE::MOV8ao32) + .value("MOV8ao64", LIEF::assembly::x86::OPCODE::MOV8ao64) + .value("MOV8mi", LIEF::assembly::x86::OPCODE::MOV8mi) + .value("MOV8mr", LIEF::assembly::x86::OPCODE::MOV8mr) + .value("MOV8mr_NOREX", LIEF::assembly::x86::OPCODE::MOV8mr_NOREX) + .value("MOV8o16a", LIEF::assembly::x86::OPCODE::MOV8o16a) + .value("MOV8o32a", LIEF::assembly::x86::OPCODE::MOV8o32a) + .value("MOV8o64a", LIEF::assembly::x86::OPCODE::MOV8o64a) + .value("MOV8ri", LIEF::assembly::x86::OPCODE::MOV8ri) + .value("MOV8ri_alt", LIEF::assembly::x86::OPCODE::MOV8ri_alt) + .value("MOV8rm", LIEF::assembly::x86::OPCODE::MOV8rm) + .value("MOV8rm_NOREX", LIEF::assembly::x86::OPCODE::MOV8rm_NOREX) + .value("MOV8rr", LIEF::assembly::x86::OPCODE::MOV8rr) + .value("MOV8rr_NOREX", LIEF::assembly::x86::OPCODE::MOV8rr_NOREX) + .value("MOV8rr_REV", LIEF::assembly::x86::OPCODE::MOV8rr_REV) + .value("MOVAPDmr", LIEF::assembly::x86::OPCODE::MOVAPDmr) + .value("MOVAPDrm", LIEF::assembly::x86::OPCODE::MOVAPDrm) + .value("MOVAPDrr", LIEF::assembly::x86::OPCODE::MOVAPDrr) + .value("MOVAPDrr_REV", LIEF::assembly::x86::OPCODE::MOVAPDrr_REV) + .value("MOVAPSmr", LIEF::assembly::x86::OPCODE::MOVAPSmr) + .value("MOVAPSrm", LIEF::assembly::x86::OPCODE::MOVAPSrm) + .value("MOVAPSrr", LIEF::assembly::x86::OPCODE::MOVAPSrr) + .value("MOVAPSrr_REV", LIEF::assembly::x86::OPCODE::MOVAPSrr_REV) + .value("MOVBE16mr", LIEF::assembly::x86::OPCODE::MOVBE16mr) + .value("MOVBE16mr_EVEX", LIEF::assembly::x86::OPCODE::MOVBE16mr_EVEX) + .value("MOVBE16rm", LIEF::assembly::x86::OPCODE::MOVBE16rm) + .value("MOVBE16rm_EVEX", LIEF::assembly::x86::OPCODE::MOVBE16rm_EVEX) + .value("MOVBE16rr", LIEF::assembly::x86::OPCODE::MOVBE16rr) + .value("MOVBE16rr_REV", LIEF::assembly::x86::OPCODE::MOVBE16rr_REV) + .value("MOVBE32mr", LIEF::assembly::x86::OPCODE::MOVBE32mr) + .value("MOVBE32mr_EVEX", LIEF::assembly::x86::OPCODE::MOVBE32mr_EVEX) + .value("MOVBE32rm", LIEF::assembly::x86::OPCODE::MOVBE32rm) + .value("MOVBE32rm_EVEX", LIEF::assembly::x86::OPCODE::MOVBE32rm_EVEX) + .value("MOVBE32rr", LIEF::assembly::x86::OPCODE::MOVBE32rr) + .value("MOVBE32rr_REV", LIEF::assembly::x86::OPCODE::MOVBE32rr_REV) + .value("MOVBE64mr", LIEF::assembly::x86::OPCODE::MOVBE64mr) + .value("MOVBE64mr_EVEX", LIEF::assembly::x86::OPCODE::MOVBE64mr_EVEX) + .value("MOVBE64rm", LIEF::assembly::x86::OPCODE::MOVBE64rm) + .value("MOVBE64rm_EVEX", LIEF::assembly::x86::OPCODE::MOVBE64rm_EVEX) + .value("MOVBE64rr", LIEF::assembly::x86::OPCODE::MOVBE64rr) + .value("MOVBE64rr_REV", LIEF::assembly::x86::OPCODE::MOVBE64rr_REV) + .value("MOVDDUPrm", LIEF::assembly::x86::OPCODE::MOVDDUPrm) + .value("MOVDDUPrr", LIEF::assembly::x86::OPCODE::MOVDDUPrr) + .value("MOVDI2PDIrm", LIEF::assembly::x86::OPCODE::MOVDI2PDIrm) + .value("MOVDI2PDIrr", LIEF::assembly::x86::OPCODE::MOVDI2PDIrr) + .value("MOVDI2SSrr", LIEF::assembly::x86::OPCODE::MOVDI2SSrr) + .value("MOVDIR64B16", LIEF::assembly::x86::OPCODE::MOVDIR64B16) + .value("MOVDIR64B32", LIEF::assembly::x86::OPCODE::MOVDIR64B32) + .value("MOVDIR64B32_EVEX", LIEF::assembly::x86::OPCODE::MOVDIR64B32_EVEX) + .value("MOVDIR64B64", LIEF::assembly::x86::OPCODE::MOVDIR64B64) + .value("MOVDIR64B64_EVEX", LIEF::assembly::x86::OPCODE::MOVDIR64B64_EVEX) + .value("MOVDIRI32", LIEF::assembly::x86::OPCODE::MOVDIRI32) + .value("MOVDIRI32_EVEX", LIEF::assembly::x86::OPCODE::MOVDIRI32_EVEX) + .value("MOVDIRI64", LIEF::assembly::x86::OPCODE::MOVDIRI64) + .value("MOVDIRI64_EVEX", LIEF::assembly::x86::OPCODE::MOVDIRI64_EVEX) + .value("MOVDQAmr", LIEF::assembly::x86::OPCODE::MOVDQAmr) + .value("MOVDQArm", LIEF::assembly::x86::OPCODE::MOVDQArm) + .value("MOVDQArr", LIEF::assembly::x86::OPCODE::MOVDQArr) + .value("MOVDQArr_REV", LIEF::assembly::x86::OPCODE::MOVDQArr_REV) + .value("MOVDQUmr", LIEF::assembly::x86::OPCODE::MOVDQUmr) + .value("MOVDQUrm", LIEF::assembly::x86::OPCODE::MOVDQUrm) + .value("MOVDQUrr", LIEF::assembly::x86::OPCODE::MOVDQUrr) + .value("MOVDQUrr_REV", LIEF::assembly::x86::OPCODE::MOVDQUrr_REV) + .value("MOVHLPSrr", LIEF::assembly::x86::OPCODE::MOVHLPSrr) + .value("MOVHPDmr", LIEF::assembly::x86::OPCODE::MOVHPDmr) + .value("MOVHPDrm", LIEF::assembly::x86::OPCODE::MOVHPDrm) + .value("MOVHPSmr", LIEF::assembly::x86::OPCODE::MOVHPSmr) + .value("MOVHPSrm", LIEF::assembly::x86::OPCODE::MOVHPSrm) + .value("MOVLHPSrr", LIEF::assembly::x86::OPCODE::MOVLHPSrr) + .value("MOVLPDmr", LIEF::assembly::x86::OPCODE::MOVLPDmr) + .value("MOVLPDrm", LIEF::assembly::x86::OPCODE::MOVLPDrm) + .value("MOVLPSmr", LIEF::assembly::x86::OPCODE::MOVLPSmr) + .value("MOVLPSrm", LIEF::assembly::x86::OPCODE::MOVLPSrm) + .value("MOVMSKPDrr", LIEF::assembly::x86::OPCODE::MOVMSKPDrr) + .value("MOVMSKPSrr", LIEF::assembly::x86::OPCODE::MOVMSKPSrr) + .value("MOVNTDQArm", LIEF::assembly::x86::OPCODE::MOVNTDQArm) + .value("MOVNTDQmr", LIEF::assembly::x86::OPCODE::MOVNTDQmr) + .value("MOVNTI_64mr", LIEF::assembly::x86::OPCODE::MOVNTI_64mr) + .value("MOVNTImr", LIEF::assembly::x86::OPCODE::MOVNTImr) + .value("MOVNTPDmr", LIEF::assembly::x86::OPCODE::MOVNTPDmr) + .value("MOVNTPSmr", LIEF::assembly::x86::OPCODE::MOVNTPSmr) + .value("MOVNTSD", LIEF::assembly::x86::OPCODE::MOVNTSD) + .value("MOVNTSS", LIEF::assembly::x86::OPCODE::MOVNTSS) + .value("MOVPC32r", LIEF::assembly::x86::OPCODE::MOVPC32r) + .value("MOVPDI2DImr", LIEF::assembly::x86::OPCODE::MOVPDI2DImr) + .value("MOVPDI2DIrr", LIEF::assembly::x86::OPCODE::MOVPDI2DIrr) + .value("MOVPQI2QImr", LIEF::assembly::x86::OPCODE::MOVPQI2QImr) + .value("MOVPQI2QIrr", LIEF::assembly::x86::OPCODE::MOVPQI2QIrr) + .value("MOVPQIto64mr", LIEF::assembly::x86::OPCODE::MOVPQIto64mr) + .value("MOVPQIto64rr", LIEF::assembly::x86::OPCODE::MOVPQIto64rr) + .value("MOVQI2PQIrm", LIEF::assembly::x86::OPCODE::MOVQI2PQIrm) + .value("MOVRS16rm", LIEF::assembly::x86::OPCODE::MOVRS16rm) + .value("MOVRS16rm_EVEX", LIEF::assembly::x86::OPCODE::MOVRS16rm_EVEX) + .value("MOVRS32rm", LIEF::assembly::x86::OPCODE::MOVRS32rm) + .value("MOVRS32rm_EVEX", LIEF::assembly::x86::OPCODE::MOVRS32rm_EVEX) + .value("MOVRS64rm", LIEF::assembly::x86::OPCODE::MOVRS64rm) + .value("MOVRS64rm_EVEX", LIEF::assembly::x86::OPCODE::MOVRS64rm_EVEX) + .value("MOVRS8rm", LIEF::assembly::x86::OPCODE::MOVRS8rm) + .value("MOVRS8rm_EVEX", LIEF::assembly::x86::OPCODE::MOVRS8rm_EVEX) + .value("MOVSB", LIEF::assembly::x86::OPCODE::MOVSB) + .value("MOVSDmr", LIEF::assembly::x86::OPCODE::MOVSDmr) + .value("MOVSDrm", LIEF::assembly::x86::OPCODE::MOVSDrm); + opcodes.value("MOVSDrm_alt", LIEF::assembly::x86::OPCODE::MOVSDrm_alt) + .value("MOVSDrr", LIEF::assembly::x86::OPCODE::MOVSDrr) + .value("MOVSDrr_REV", LIEF::assembly::x86::OPCODE::MOVSDrr_REV) + .value("MOVSDto64rr", LIEF::assembly::x86::OPCODE::MOVSDto64rr) + .value("MOVSHDUPrm", LIEF::assembly::x86::OPCODE::MOVSHDUPrm) + .value("MOVSHDUPrr", LIEF::assembly::x86::OPCODE::MOVSHDUPrr) + .value("MOVSL", LIEF::assembly::x86::OPCODE::MOVSL) + .value("MOVSLDUPrm", LIEF::assembly::x86::OPCODE::MOVSLDUPrm) + .value("MOVSLDUPrr", LIEF::assembly::x86::OPCODE::MOVSLDUPrr) + .value("MOVSQ", LIEF::assembly::x86::OPCODE::MOVSQ) + .value("MOVSS2DIrr", LIEF::assembly::x86::OPCODE::MOVSS2DIrr) + .value("MOVSSmr", LIEF::assembly::x86::OPCODE::MOVSSmr) + .value("MOVSSrm", LIEF::assembly::x86::OPCODE::MOVSSrm) + .value("MOVSSrm_alt", LIEF::assembly::x86::OPCODE::MOVSSrm_alt) + .value("MOVSSrr", LIEF::assembly::x86::OPCODE::MOVSSrr) + .value("MOVSSrr_REV", LIEF::assembly::x86::OPCODE::MOVSSrr_REV) + .value("MOVSW", LIEF::assembly::x86::OPCODE::MOVSW) + .value("MOVSX16rm16", LIEF::assembly::x86::OPCODE::MOVSX16rm16) + .value("MOVSX16rm32", LIEF::assembly::x86::OPCODE::MOVSX16rm32) + .value("MOVSX16rm8", LIEF::assembly::x86::OPCODE::MOVSX16rm8) + .value("MOVSX16rr16", LIEF::assembly::x86::OPCODE::MOVSX16rr16) + .value("MOVSX16rr32", LIEF::assembly::x86::OPCODE::MOVSX16rr32) + .value("MOVSX16rr8", LIEF::assembly::x86::OPCODE::MOVSX16rr8) + .value("MOVSX32rm16", LIEF::assembly::x86::OPCODE::MOVSX32rm16) + .value("MOVSX32rm32", LIEF::assembly::x86::OPCODE::MOVSX32rm32) + .value("MOVSX32rm8", LIEF::assembly::x86::OPCODE::MOVSX32rm8) + .value("MOVSX32rm8_NOREX", LIEF::assembly::x86::OPCODE::MOVSX32rm8_NOREX) + .value("MOVSX32rr16", LIEF::assembly::x86::OPCODE::MOVSX32rr16) + .value("MOVSX32rr32", LIEF::assembly::x86::OPCODE::MOVSX32rr32) + .value("MOVSX32rr8", LIEF::assembly::x86::OPCODE::MOVSX32rr8) + .value("MOVSX32rr8_NOREX", LIEF::assembly::x86::OPCODE::MOVSX32rr8_NOREX) + .value("MOVSX64rm16", LIEF::assembly::x86::OPCODE::MOVSX64rm16) + .value("MOVSX64rm32", LIEF::assembly::x86::OPCODE::MOVSX64rm32) + .value("MOVSX64rm8", LIEF::assembly::x86::OPCODE::MOVSX64rm8) + .value("MOVSX64rr16", LIEF::assembly::x86::OPCODE::MOVSX64rr16) + .value("MOVSX64rr32", LIEF::assembly::x86::OPCODE::MOVSX64rr32) + .value("MOVSX64rr8", LIEF::assembly::x86::OPCODE::MOVSX64rr8) + .value("MOVUPDmr", LIEF::assembly::x86::OPCODE::MOVUPDmr) + .value("MOVUPDrm", LIEF::assembly::x86::OPCODE::MOVUPDrm) + .value("MOVUPDrr", LIEF::assembly::x86::OPCODE::MOVUPDrr) + .value("MOVUPDrr_REV", LIEF::assembly::x86::OPCODE::MOVUPDrr_REV) + .value("MOVUPSmr", LIEF::assembly::x86::OPCODE::MOVUPSmr) + .value("MOVUPSrm", LIEF::assembly::x86::OPCODE::MOVUPSrm) + .value("MOVUPSrr", LIEF::assembly::x86::OPCODE::MOVUPSrr) + .value("MOVUPSrr_REV", LIEF::assembly::x86::OPCODE::MOVUPSrr_REV) + .value("MOVZPQILo2PQIrr", LIEF::assembly::x86::OPCODE::MOVZPQILo2PQIrr) + .value("MOVZX16rm16", LIEF::assembly::x86::OPCODE::MOVZX16rm16) + .value("MOVZX16rm8", LIEF::assembly::x86::OPCODE::MOVZX16rm8) + .value("MOVZX16rr16", LIEF::assembly::x86::OPCODE::MOVZX16rr16) + .value("MOVZX16rr8", LIEF::assembly::x86::OPCODE::MOVZX16rr8) + .value("MOVZX32rm16", LIEF::assembly::x86::OPCODE::MOVZX32rm16) + .value("MOVZX32rm8", LIEF::assembly::x86::OPCODE::MOVZX32rm8) + .value("MOVZX32rm8_NOREX", LIEF::assembly::x86::OPCODE::MOVZX32rm8_NOREX) + .value("MOVZX32rr16", LIEF::assembly::x86::OPCODE::MOVZX32rr16) + .value("MOVZX32rr8", LIEF::assembly::x86::OPCODE::MOVZX32rr8) + .value("MOVZX32rr8_NOREX", LIEF::assembly::x86::OPCODE::MOVZX32rr8_NOREX) + .value("MOVZX64rm16", LIEF::assembly::x86::OPCODE::MOVZX64rm16) + .value("MOVZX64rm8", LIEF::assembly::x86::OPCODE::MOVZX64rm8) + .value("MOVZX64rr16", LIEF::assembly::x86::OPCODE::MOVZX64rr16) + .value("MOVZX64rr8", LIEF::assembly::x86::OPCODE::MOVZX64rr8) + .value("MPSADBWrmi", LIEF::assembly::x86::OPCODE::MPSADBWrmi) + .value("MPSADBWrri", LIEF::assembly::x86::OPCODE::MPSADBWrri) + .value("MUL16m", LIEF::assembly::x86::OPCODE::MUL16m) + .value("MUL16m_EVEX", LIEF::assembly::x86::OPCODE::MUL16m_EVEX) + .value("MUL16m_NF", LIEF::assembly::x86::OPCODE::MUL16m_NF) + .value("MUL16r", LIEF::assembly::x86::OPCODE::MUL16r) + .value("MUL16r_EVEX", LIEF::assembly::x86::OPCODE::MUL16r_EVEX) + .value("MUL16r_NF", LIEF::assembly::x86::OPCODE::MUL16r_NF) + .value("MUL32m", LIEF::assembly::x86::OPCODE::MUL32m) + .value("MUL32m_EVEX", LIEF::assembly::x86::OPCODE::MUL32m_EVEX) + .value("MUL32m_NF", LIEF::assembly::x86::OPCODE::MUL32m_NF) + .value("MUL32r", LIEF::assembly::x86::OPCODE::MUL32r) + .value("MUL32r_EVEX", LIEF::assembly::x86::OPCODE::MUL32r_EVEX) + .value("MUL32r_NF", LIEF::assembly::x86::OPCODE::MUL32r_NF) + .value("MUL64m", LIEF::assembly::x86::OPCODE::MUL64m) + .value("MUL64m_EVEX", LIEF::assembly::x86::OPCODE::MUL64m_EVEX) + .value("MUL64m_NF", LIEF::assembly::x86::OPCODE::MUL64m_NF) + .value("MUL64r", LIEF::assembly::x86::OPCODE::MUL64r) + .value("MUL64r_EVEX", LIEF::assembly::x86::OPCODE::MUL64r_EVEX) + .value("MUL64r_NF", LIEF::assembly::x86::OPCODE::MUL64r_NF) + .value("MUL8m", LIEF::assembly::x86::OPCODE::MUL8m) + .value("MUL8m_EVEX", LIEF::assembly::x86::OPCODE::MUL8m_EVEX) + .value("MUL8m_NF", LIEF::assembly::x86::OPCODE::MUL8m_NF) + .value("MUL8r", LIEF::assembly::x86::OPCODE::MUL8r) + .value("MUL8r_EVEX", LIEF::assembly::x86::OPCODE::MUL8r_EVEX) + .value("MUL8r_NF", LIEF::assembly::x86::OPCODE::MUL8r_NF) + .value("MULPDrm", LIEF::assembly::x86::OPCODE::MULPDrm) + .value("MULPDrr", LIEF::assembly::x86::OPCODE::MULPDrr) + .value("MULPSrm", LIEF::assembly::x86::OPCODE::MULPSrm) + .value("MULPSrr", LIEF::assembly::x86::OPCODE::MULPSrr) + .value("MULSDrm", LIEF::assembly::x86::OPCODE::MULSDrm) + .value("MULSDrm_Int", LIEF::assembly::x86::OPCODE::MULSDrm_Int) + .value("MULSDrr", LIEF::assembly::x86::OPCODE::MULSDrr) + .value("MULSDrr_Int", LIEF::assembly::x86::OPCODE::MULSDrr_Int) + .value("MULSSrm", LIEF::assembly::x86::OPCODE::MULSSrm) + .value("MULSSrm_Int", LIEF::assembly::x86::OPCODE::MULSSrm_Int) + .value("MULSSrr", LIEF::assembly::x86::OPCODE::MULSSrr) + .value("MULSSrr_Int", LIEF::assembly::x86::OPCODE::MULSSrr_Int) + .value("MULX32Hrm", LIEF::assembly::x86::OPCODE::MULX32Hrm) + .value("MULX32Hrr", LIEF::assembly::x86::OPCODE::MULX32Hrr) + .value("MULX32rm", LIEF::assembly::x86::OPCODE::MULX32rm) + .value("MULX32rm_EVEX", LIEF::assembly::x86::OPCODE::MULX32rm_EVEX) + .value("MULX32rr", LIEF::assembly::x86::OPCODE::MULX32rr) + .value("MULX32rr_EVEX", LIEF::assembly::x86::OPCODE::MULX32rr_EVEX) + .value("MULX64Hrm", LIEF::assembly::x86::OPCODE::MULX64Hrm) + .value("MULX64Hrr", LIEF::assembly::x86::OPCODE::MULX64Hrr) + .value("MULX64rm", LIEF::assembly::x86::OPCODE::MULX64rm) + .value("MULX64rm_EVEX", LIEF::assembly::x86::OPCODE::MULX64rm_EVEX) + .value("MULX64rr", LIEF::assembly::x86::OPCODE::MULX64rr) + .value("MULX64rr_EVEX", LIEF::assembly::x86::OPCODE::MULX64rr_EVEX) + .value("MUL_F32m", LIEF::assembly::x86::OPCODE::MUL_F32m) + .value("MUL_F64m", LIEF::assembly::x86::OPCODE::MUL_F64m) + .value("MUL_FI16m", LIEF::assembly::x86::OPCODE::MUL_FI16m) + .value("MUL_FI32m", LIEF::assembly::x86::OPCODE::MUL_FI32m) + .value("MUL_FPrST0", LIEF::assembly::x86::OPCODE::MUL_FPrST0) + .value("MUL_FST0r", LIEF::assembly::x86::OPCODE::MUL_FST0r) + .value("MUL_Fp32", LIEF::assembly::x86::OPCODE::MUL_Fp32) + .value("MUL_Fp32m", LIEF::assembly::x86::OPCODE::MUL_Fp32m) + .value("MUL_Fp64", LIEF::assembly::x86::OPCODE::MUL_Fp64) + .value("MUL_Fp64m", LIEF::assembly::x86::OPCODE::MUL_Fp64m) + .value("MUL_Fp64m32", LIEF::assembly::x86::OPCODE::MUL_Fp64m32) + .value("MUL_Fp80", LIEF::assembly::x86::OPCODE::MUL_Fp80) + .value("MUL_Fp80m32", LIEF::assembly::x86::OPCODE::MUL_Fp80m32) + .value("MUL_Fp80m64", LIEF::assembly::x86::OPCODE::MUL_Fp80m64) + .value("MUL_FpI16m32", LIEF::assembly::x86::OPCODE::MUL_FpI16m32) + .value("MUL_FpI16m64", LIEF::assembly::x86::OPCODE::MUL_FpI16m64) + .value("MUL_FpI16m80", LIEF::assembly::x86::OPCODE::MUL_FpI16m80) + .value("MUL_FpI32m32", LIEF::assembly::x86::OPCODE::MUL_FpI32m32) + .value("MUL_FpI32m64", LIEF::assembly::x86::OPCODE::MUL_FpI32m64) + .value("MUL_FpI32m80", LIEF::assembly::x86::OPCODE::MUL_FpI32m80) + .value("MUL_FrST0", LIEF::assembly::x86::OPCODE::MUL_FrST0) + .value("MWAITXrrr", LIEF::assembly::x86::OPCODE::MWAITXrrr) + .value("MWAITrr", LIEF::assembly::x86::OPCODE::MWAITrr) + .value("NEG16m", LIEF::assembly::x86::OPCODE::NEG16m) + .value("NEG16m_EVEX", LIEF::assembly::x86::OPCODE::NEG16m_EVEX) + .value("NEG16m_ND", LIEF::assembly::x86::OPCODE::NEG16m_ND) + .value("NEG16m_NF", LIEF::assembly::x86::OPCODE::NEG16m_NF) + .value("NEG16m_NF_ND", LIEF::assembly::x86::OPCODE::NEG16m_NF_ND) + .value("NEG16r", LIEF::assembly::x86::OPCODE::NEG16r) + .value("NEG16r_EVEX", LIEF::assembly::x86::OPCODE::NEG16r_EVEX) + .value("NEG16r_ND", LIEF::assembly::x86::OPCODE::NEG16r_ND) + .value("NEG16r_NF", LIEF::assembly::x86::OPCODE::NEG16r_NF) + .value("NEG16r_NF_ND", LIEF::assembly::x86::OPCODE::NEG16r_NF_ND) + .value("NEG32m", LIEF::assembly::x86::OPCODE::NEG32m) + .value("NEG32m_EVEX", LIEF::assembly::x86::OPCODE::NEG32m_EVEX) + .value("NEG32m_ND", LIEF::assembly::x86::OPCODE::NEG32m_ND) + .value("NEG32m_NF", LIEF::assembly::x86::OPCODE::NEG32m_NF) + .value("NEG32m_NF_ND", LIEF::assembly::x86::OPCODE::NEG32m_NF_ND) + .value("NEG32r", LIEF::assembly::x86::OPCODE::NEG32r) + .value("NEG32r_EVEX", LIEF::assembly::x86::OPCODE::NEG32r_EVEX) + .value("NEG32r_ND", LIEF::assembly::x86::OPCODE::NEG32r_ND) + .value("NEG32r_NF", LIEF::assembly::x86::OPCODE::NEG32r_NF) + .value("NEG32r_NF_ND", LIEF::assembly::x86::OPCODE::NEG32r_NF_ND) + .value("NEG64m", LIEF::assembly::x86::OPCODE::NEG64m) + .value("NEG64m_EVEX", LIEF::assembly::x86::OPCODE::NEG64m_EVEX) + .value("NEG64m_ND", LIEF::assembly::x86::OPCODE::NEG64m_ND) + .value("NEG64m_NF", LIEF::assembly::x86::OPCODE::NEG64m_NF) + .value("NEG64m_NF_ND", LIEF::assembly::x86::OPCODE::NEG64m_NF_ND) + .value("NEG64r", LIEF::assembly::x86::OPCODE::NEG64r) + .value("NEG64r_EVEX", LIEF::assembly::x86::OPCODE::NEG64r_EVEX) + .value("NEG64r_ND", LIEF::assembly::x86::OPCODE::NEG64r_ND) + .value("NEG64r_NF", LIEF::assembly::x86::OPCODE::NEG64r_NF) + .value("NEG64r_NF_ND", LIEF::assembly::x86::OPCODE::NEG64r_NF_ND) + .value("NEG8m", LIEF::assembly::x86::OPCODE::NEG8m) + .value("NEG8m_EVEX", LIEF::assembly::x86::OPCODE::NEG8m_EVEX) + .value("NEG8m_ND", LIEF::assembly::x86::OPCODE::NEG8m_ND) + .value("NEG8m_NF", LIEF::assembly::x86::OPCODE::NEG8m_NF) + .value("NEG8m_NF_ND", LIEF::assembly::x86::OPCODE::NEG8m_NF_ND) + .value("NEG8r", LIEF::assembly::x86::OPCODE::NEG8r) + .value("NEG8r_EVEX", LIEF::assembly::x86::OPCODE::NEG8r_EVEX) + .value("NEG8r_ND", LIEF::assembly::x86::OPCODE::NEG8r_ND) + .value("NEG8r_NF", LIEF::assembly::x86::OPCODE::NEG8r_NF) + .value("NEG8r_NF_ND", LIEF::assembly::x86::OPCODE::NEG8r_NF_ND) + .value("NOOP", LIEF::assembly::x86::OPCODE::NOOP) + .value("NOOPL", LIEF::assembly::x86::OPCODE::NOOPL) + .value("NOOPLr", LIEF::assembly::x86::OPCODE::NOOPLr) + .value("NOOPQ", LIEF::assembly::x86::OPCODE::NOOPQ) + .value("NOOPQr", LIEF::assembly::x86::OPCODE::NOOPQr) + .value("NOOPW", LIEF::assembly::x86::OPCODE::NOOPW) + .value("NOOPWr", LIEF::assembly::x86::OPCODE::NOOPWr) + .value("NOT16m", LIEF::assembly::x86::OPCODE::NOT16m) + .value("NOT16m_EVEX", LIEF::assembly::x86::OPCODE::NOT16m_EVEX) + .value("NOT16m_ND", LIEF::assembly::x86::OPCODE::NOT16m_ND) + .value("NOT16r", LIEF::assembly::x86::OPCODE::NOT16r) + .value("NOT16r_EVEX", LIEF::assembly::x86::OPCODE::NOT16r_EVEX) + .value("NOT16r_ND", LIEF::assembly::x86::OPCODE::NOT16r_ND) + .value("NOT32m", LIEF::assembly::x86::OPCODE::NOT32m) + .value("NOT32m_EVEX", LIEF::assembly::x86::OPCODE::NOT32m_EVEX) + .value("NOT32m_ND", LIEF::assembly::x86::OPCODE::NOT32m_ND) + .value("NOT32r", LIEF::assembly::x86::OPCODE::NOT32r) + .value("NOT32r_EVEX", LIEF::assembly::x86::OPCODE::NOT32r_EVEX) + .value("NOT32r_ND", LIEF::assembly::x86::OPCODE::NOT32r_ND) + .value("NOT64m", LIEF::assembly::x86::OPCODE::NOT64m) + .value("NOT64m_EVEX", LIEF::assembly::x86::OPCODE::NOT64m_EVEX) + .value("NOT64m_ND", LIEF::assembly::x86::OPCODE::NOT64m_ND) + .value("NOT64r", LIEF::assembly::x86::OPCODE::NOT64r) + .value("NOT64r_EVEX", LIEF::assembly::x86::OPCODE::NOT64r_EVEX) + .value("NOT64r_ND", LIEF::assembly::x86::OPCODE::NOT64r_ND) + .value("NOT8m", LIEF::assembly::x86::OPCODE::NOT8m) + .value("NOT8m_EVEX", LIEF::assembly::x86::OPCODE::NOT8m_EVEX) + .value("NOT8m_ND", LIEF::assembly::x86::OPCODE::NOT8m_ND) + .value("NOT8r", LIEF::assembly::x86::OPCODE::NOT8r) + .value("NOT8r_EVEX", LIEF::assembly::x86::OPCODE::NOT8r_EVEX) + .value("NOT8r_ND", LIEF::assembly::x86::OPCODE::NOT8r_ND) + .value("OR16i16", LIEF::assembly::x86::OPCODE::OR16i16) + .value("OR16mi", LIEF::assembly::x86::OPCODE::OR16mi) + .value("OR16mi8", LIEF::assembly::x86::OPCODE::OR16mi8) + .value("OR16mi8_EVEX", LIEF::assembly::x86::OPCODE::OR16mi8_EVEX) + .value("OR16mi8_ND", LIEF::assembly::x86::OPCODE::OR16mi8_ND) + .value("OR16mi8_NF", LIEF::assembly::x86::OPCODE::OR16mi8_NF) + .value("OR16mi8_NF_ND", LIEF::assembly::x86::OPCODE::OR16mi8_NF_ND) + .value("OR16mi_EVEX", LIEF::assembly::x86::OPCODE::OR16mi_EVEX) + .value("OR16mi_ND", LIEF::assembly::x86::OPCODE::OR16mi_ND) + .value("OR16mi_NF", LIEF::assembly::x86::OPCODE::OR16mi_NF) + .value("OR16mi_NF_ND", LIEF::assembly::x86::OPCODE::OR16mi_NF_ND) + .value("OR16mr", LIEF::assembly::x86::OPCODE::OR16mr) + .value("OR16mr_EVEX", LIEF::assembly::x86::OPCODE::OR16mr_EVEX) + .value("OR16mr_ND", LIEF::assembly::x86::OPCODE::OR16mr_ND) + .value("OR16mr_NF", LIEF::assembly::x86::OPCODE::OR16mr_NF) + .value("OR16mr_NF_ND", LIEF::assembly::x86::OPCODE::OR16mr_NF_ND) + .value("OR16ri", LIEF::assembly::x86::OPCODE::OR16ri) + .value("OR16ri8", LIEF::assembly::x86::OPCODE::OR16ri8) + .value("OR16ri8_EVEX", LIEF::assembly::x86::OPCODE::OR16ri8_EVEX) + .value("OR16ri8_ND", LIEF::assembly::x86::OPCODE::OR16ri8_ND) + .value("OR16ri8_NF", LIEF::assembly::x86::OPCODE::OR16ri8_NF) + .value("OR16ri8_NF_ND", LIEF::assembly::x86::OPCODE::OR16ri8_NF_ND) + .value("OR16ri_EVEX", LIEF::assembly::x86::OPCODE::OR16ri_EVEX) + .value("OR16ri_ND", LIEF::assembly::x86::OPCODE::OR16ri_ND) + .value("OR16ri_NF", LIEF::assembly::x86::OPCODE::OR16ri_NF) + .value("OR16ri_NF_ND", LIEF::assembly::x86::OPCODE::OR16ri_NF_ND) + .value("OR16rm", LIEF::assembly::x86::OPCODE::OR16rm) + .value("OR16rm_EVEX", LIEF::assembly::x86::OPCODE::OR16rm_EVEX) + .value("OR16rm_ND", LIEF::assembly::x86::OPCODE::OR16rm_ND) + .value("OR16rm_NF", LIEF::assembly::x86::OPCODE::OR16rm_NF) + .value("OR16rm_NF_ND", LIEF::assembly::x86::OPCODE::OR16rm_NF_ND) + .value("OR16rr", LIEF::assembly::x86::OPCODE::OR16rr) + .value("OR16rr_EVEX", LIEF::assembly::x86::OPCODE::OR16rr_EVEX) + .value("OR16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::OR16rr_EVEX_REV) + .value("OR16rr_ND", LIEF::assembly::x86::OPCODE::OR16rr_ND) + .value("OR16rr_ND_REV", LIEF::assembly::x86::OPCODE::OR16rr_ND_REV) + .value("OR16rr_NF", LIEF::assembly::x86::OPCODE::OR16rr_NF) + .value("OR16rr_NF_ND", LIEF::assembly::x86::OPCODE::OR16rr_NF_ND) + .value("OR16rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::OR16rr_NF_ND_REV) + .value("OR16rr_NF_REV", LIEF::assembly::x86::OPCODE::OR16rr_NF_REV) + .value("OR16rr_REV", LIEF::assembly::x86::OPCODE::OR16rr_REV) + .value("OR32i32", LIEF::assembly::x86::OPCODE::OR32i32) + .value("OR32mi", LIEF::assembly::x86::OPCODE::OR32mi) + .value("OR32mi8", LIEF::assembly::x86::OPCODE::OR32mi8) + .value("OR32mi8Locked", LIEF::assembly::x86::OPCODE::OR32mi8Locked) + .value("OR32mi8_EVEX", LIEF::assembly::x86::OPCODE::OR32mi8_EVEX) + .value("OR32mi8_ND", LIEF::assembly::x86::OPCODE::OR32mi8_ND) + .value("OR32mi8_NF", LIEF::assembly::x86::OPCODE::OR32mi8_NF) + .value("OR32mi8_NF_ND", LIEF::assembly::x86::OPCODE::OR32mi8_NF_ND) + .value("OR32mi_EVEX", LIEF::assembly::x86::OPCODE::OR32mi_EVEX) + .value("OR32mi_ND", LIEF::assembly::x86::OPCODE::OR32mi_ND) + .value("OR32mi_NF", LIEF::assembly::x86::OPCODE::OR32mi_NF) + .value("OR32mi_NF_ND", LIEF::assembly::x86::OPCODE::OR32mi_NF_ND) + .value("OR32mr", LIEF::assembly::x86::OPCODE::OR32mr) + .value("OR32mr_EVEX", LIEF::assembly::x86::OPCODE::OR32mr_EVEX) + .value("OR32mr_ND", LIEF::assembly::x86::OPCODE::OR32mr_ND) + .value("OR32mr_NF", LIEF::assembly::x86::OPCODE::OR32mr_NF) + .value("OR32mr_NF_ND", LIEF::assembly::x86::OPCODE::OR32mr_NF_ND) + .value("OR32ri", LIEF::assembly::x86::OPCODE::OR32ri) + .value("OR32ri8", LIEF::assembly::x86::OPCODE::OR32ri8) + .value("OR32ri8_EVEX", LIEF::assembly::x86::OPCODE::OR32ri8_EVEX) + .value("OR32ri8_ND", LIEF::assembly::x86::OPCODE::OR32ri8_ND) + .value("OR32ri8_NF", LIEF::assembly::x86::OPCODE::OR32ri8_NF) + .value("OR32ri8_NF_ND", LIEF::assembly::x86::OPCODE::OR32ri8_NF_ND) + .value("OR32ri_EVEX", LIEF::assembly::x86::OPCODE::OR32ri_EVEX) + .value("OR32ri_ND", LIEF::assembly::x86::OPCODE::OR32ri_ND) + .value("OR32ri_NF", LIEF::assembly::x86::OPCODE::OR32ri_NF) + .value("OR32ri_NF_ND", LIEF::assembly::x86::OPCODE::OR32ri_NF_ND) + .value("OR32rm", LIEF::assembly::x86::OPCODE::OR32rm) + .value("OR32rm_EVEX", LIEF::assembly::x86::OPCODE::OR32rm_EVEX) + .value("OR32rm_ND", LIEF::assembly::x86::OPCODE::OR32rm_ND) + .value("OR32rm_NF", LIEF::assembly::x86::OPCODE::OR32rm_NF) + .value("OR32rm_NF_ND", LIEF::assembly::x86::OPCODE::OR32rm_NF_ND) + .value("OR32rr", LIEF::assembly::x86::OPCODE::OR32rr) + .value("OR32rr_EVEX", LIEF::assembly::x86::OPCODE::OR32rr_EVEX) + .value("OR32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::OR32rr_EVEX_REV) + .value("OR32rr_ND", LIEF::assembly::x86::OPCODE::OR32rr_ND) + .value("OR32rr_ND_REV", LIEF::assembly::x86::OPCODE::OR32rr_ND_REV) + .value("OR32rr_NF", LIEF::assembly::x86::OPCODE::OR32rr_NF) + .value("OR32rr_NF_ND", LIEF::assembly::x86::OPCODE::OR32rr_NF_ND) + .value("OR32rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::OR32rr_NF_ND_REV) + .value("OR32rr_NF_REV", LIEF::assembly::x86::OPCODE::OR32rr_NF_REV) + .value("OR32rr_REV", LIEF::assembly::x86::OPCODE::OR32rr_REV) + .value("OR64i32", LIEF::assembly::x86::OPCODE::OR64i32) + .value("OR64mi32", LIEF::assembly::x86::OPCODE::OR64mi32) + .value("OR64mi32_EVEX", LIEF::assembly::x86::OPCODE::OR64mi32_EVEX) + .value("OR64mi32_ND", LIEF::assembly::x86::OPCODE::OR64mi32_ND) + .value("OR64mi32_NF", LIEF::assembly::x86::OPCODE::OR64mi32_NF) + .value("OR64mi32_NF_ND", LIEF::assembly::x86::OPCODE::OR64mi32_NF_ND) + .value("OR64mi8", LIEF::assembly::x86::OPCODE::OR64mi8) + .value("OR64mi8_EVEX", LIEF::assembly::x86::OPCODE::OR64mi8_EVEX) + .value("OR64mi8_ND", LIEF::assembly::x86::OPCODE::OR64mi8_ND) + .value("OR64mi8_NF", LIEF::assembly::x86::OPCODE::OR64mi8_NF) + .value("OR64mi8_NF_ND", LIEF::assembly::x86::OPCODE::OR64mi8_NF_ND) + .value("OR64mr", LIEF::assembly::x86::OPCODE::OR64mr) + .value("OR64mr_EVEX", LIEF::assembly::x86::OPCODE::OR64mr_EVEX); + opcodes.value("OR64mr_ND", LIEF::assembly::x86::OPCODE::OR64mr_ND) + .value("OR64mr_NF", LIEF::assembly::x86::OPCODE::OR64mr_NF) + .value("OR64mr_NF_ND", LIEF::assembly::x86::OPCODE::OR64mr_NF_ND) + .value("OR64ri32", LIEF::assembly::x86::OPCODE::OR64ri32) + .value("OR64ri32_EVEX", LIEF::assembly::x86::OPCODE::OR64ri32_EVEX) + .value("OR64ri32_ND", LIEF::assembly::x86::OPCODE::OR64ri32_ND) + .value("OR64ri32_NF", LIEF::assembly::x86::OPCODE::OR64ri32_NF) + .value("OR64ri32_NF_ND", LIEF::assembly::x86::OPCODE::OR64ri32_NF_ND) + .value("OR64ri8", LIEF::assembly::x86::OPCODE::OR64ri8) + .value("OR64ri8_EVEX", LIEF::assembly::x86::OPCODE::OR64ri8_EVEX) + .value("OR64ri8_ND", LIEF::assembly::x86::OPCODE::OR64ri8_ND) + .value("OR64ri8_NF", LIEF::assembly::x86::OPCODE::OR64ri8_NF) + .value("OR64ri8_NF_ND", LIEF::assembly::x86::OPCODE::OR64ri8_NF_ND) + .value("OR64rm", LIEF::assembly::x86::OPCODE::OR64rm) + .value("OR64rm_EVEX", LIEF::assembly::x86::OPCODE::OR64rm_EVEX) + .value("OR64rm_ND", LIEF::assembly::x86::OPCODE::OR64rm_ND) + .value("OR64rm_NF", LIEF::assembly::x86::OPCODE::OR64rm_NF) + .value("OR64rm_NF_ND", LIEF::assembly::x86::OPCODE::OR64rm_NF_ND) + .value("OR64rr", LIEF::assembly::x86::OPCODE::OR64rr) + .value("OR64rr_EVEX", LIEF::assembly::x86::OPCODE::OR64rr_EVEX) + .value("OR64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::OR64rr_EVEX_REV) + .value("OR64rr_ND", LIEF::assembly::x86::OPCODE::OR64rr_ND) + .value("OR64rr_ND_REV", LIEF::assembly::x86::OPCODE::OR64rr_ND_REV) + .value("OR64rr_NF", LIEF::assembly::x86::OPCODE::OR64rr_NF) + .value("OR64rr_NF_ND", LIEF::assembly::x86::OPCODE::OR64rr_NF_ND) + .value("OR64rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::OR64rr_NF_ND_REV) + .value("OR64rr_NF_REV", LIEF::assembly::x86::OPCODE::OR64rr_NF_REV) + .value("OR64rr_REV", LIEF::assembly::x86::OPCODE::OR64rr_REV) + .value("OR8i8", LIEF::assembly::x86::OPCODE::OR8i8) + .value("OR8mi", LIEF::assembly::x86::OPCODE::OR8mi) + .value("OR8mi8", LIEF::assembly::x86::OPCODE::OR8mi8) + .value("OR8mi_EVEX", LIEF::assembly::x86::OPCODE::OR8mi_EVEX) + .value("OR8mi_ND", LIEF::assembly::x86::OPCODE::OR8mi_ND) + .value("OR8mi_NF", LIEF::assembly::x86::OPCODE::OR8mi_NF) + .value("OR8mi_NF_ND", LIEF::assembly::x86::OPCODE::OR8mi_NF_ND) + .value("OR8mr", LIEF::assembly::x86::OPCODE::OR8mr) + .value("OR8mr_EVEX", LIEF::assembly::x86::OPCODE::OR8mr_EVEX) + .value("OR8mr_ND", LIEF::assembly::x86::OPCODE::OR8mr_ND) + .value("OR8mr_NF", LIEF::assembly::x86::OPCODE::OR8mr_NF) + .value("OR8mr_NF_ND", LIEF::assembly::x86::OPCODE::OR8mr_NF_ND) + .value("OR8ri", LIEF::assembly::x86::OPCODE::OR8ri) + .value("OR8ri8", LIEF::assembly::x86::OPCODE::OR8ri8) + .value("OR8ri_EVEX", LIEF::assembly::x86::OPCODE::OR8ri_EVEX) + .value("OR8ri_ND", LIEF::assembly::x86::OPCODE::OR8ri_ND) + .value("OR8ri_NF", LIEF::assembly::x86::OPCODE::OR8ri_NF) + .value("OR8ri_NF_ND", LIEF::assembly::x86::OPCODE::OR8ri_NF_ND) + .value("OR8rm", LIEF::assembly::x86::OPCODE::OR8rm) + .value("OR8rm_EVEX", LIEF::assembly::x86::OPCODE::OR8rm_EVEX) + .value("OR8rm_ND", LIEF::assembly::x86::OPCODE::OR8rm_ND) + .value("OR8rm_NF", LIEF::assembly::x86::OPCODE::OR8rm_NF) + .value("OR8rm_NF_ND", LIEF::assembly::x86::OPCODE::OR8rm_NF_ND) + .value("OR8rr", LIEF::assembly::x86::OPCODE::OR8rr) + .value("OR8rr_EVEX", LIEF::assembly::x86::OPCODE::OR8rr_EVEX) + .value("OR8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::OR8rr_EVEX_REV) + .value("OR8rr_ND", LIEF::assembly::x86::OPCODE::OR8rr_ND) + .value("OR8rr_ND_REV", LIEF::assembly::x86::OPCODE::OR8rr_ND_REV) + .value("OR8rr_NF", LIEF::assembly::x86::OPCODE::OR8rr_NF) + .value("OR8rr_NF_ND", LIEF::assembly::x86::OPCODE::OR8rr_NF_ND) + .value("OR8rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::OR8rr_NF_ND_REV) + .value("OR8rr_NF_REV", LIEF::assembly::x86::OPCODE::OR8rr_NF_REV) + .value("OR8rr_REV", LIEF::assembly::x86::OPCODE::OR8rr_REV) + .value("ORPDrm", LIEF::assembly::x86::OPCODE::ORPDrm) + .value("ORPDrr", LIEF::assembly::x86::OPCODE::ORPDrr) + .value("ORPSrm", LIEF::assembly::x86::OPCODE::ORPSrm) + .value("ORPSrr", LIEF::assembly::x86::OPCODE::ORPSrr) + .value("OUT16ir", LIEF::assembly::x86::OPCODE::OUT16ir) + .value("OUT16rr", LIEF::assembly::x86::OPCODE::OUT16rr) + .value("OUT32ir", LIEF::assembly::x86::OPCODE::OUT32ir) + .value("OUT32rr", LIEF::assembly::x86::OPCODE::OUT32rr) + .value("OUT8ir", LIEF::assembly::x86::OPCODE::OUT8ir) + .value("OUT8rr", LIEF::assembly::x86::OPCODE::OUT8rr) + .value("OUTSB", LIEF::assembly::x86::OPCODE::OUTSB) + .value("OUTSL", LIEF::assembly::x86::OPCODE::OUTSL) + .value("OUTSW", LIEF::assembly::x86::OPCODE::OUTSW) + .value("PABSBrm", LIEF::assembly::x86::OPCODE::PABSBrm) + .value("PABSBrr", LIEF::assembly::x86::OPCODE::PABSBrr) + .value("PABSDrm", LIEF::assembly::x86::OPCODE::PABSDrm) + .value("PABSDrr", LIEF::assembly::x86::OPCODE::PABSDrr) + .value("PABSWrm", LIEF::assembly::x86::OPCODE::PABSWrm) + .value("PABSWrr", LIEF::assembly::x86::OPCODE::PABSWrr) + .value("PACKSSDWrm", LIEF::assembly::x86::OPCODE::PACKSSDWrm) + .value("PACKSSDWrr", LIEF::assembly::x86::OPCODE::PACKSSDWrr) + .value("PACKSSWBrm", LIEF::assembly::x86::OPCODE::PACKSSWBrm) + .value("PACKSSWBrr", LIEF::assembly::x86::OPCODE::PACKSSWBrr) + .value("PACKUSDWrm", LIEF::assembly::x86::OPCODE::PACKUSDWrm) + .value("PACKUSDWrr", LIEF::assembly::x86::OPCODE::PACKUSDWrr) + .value("PACKUSWBrm", LIEF::assembly::x86::OPCODE::PACKUSWBrm) + .value("PACKUSWBrr", LIEF::assembly::x86::OPCODE::PACKUSWBrr) + .value("PADDBrm", LIEF::assembly::x86::OPCODE::PADDBrm) + .value("PADDBrr", LIEF::assembly::x86::OPCODE::PADDBrr) + .value("PADDDrm", LIEF::assembly::x86::OPCODE::PADDDrm) + .value("PADDDrr", LIEF::assembly::x86::OPCODE::PADDDrr) + .value("PADDQrm", LIEF::assembly::x86::OPCODE::PADDQrm) + .value("PADDQrr", LIEF::assembly::x86::OPCODE::PADDQrr) + .value("PADDSBrm", LIEF::assembly::x86::OPCODE::PADDSBrm) + .value("PADDSBrr", LIEF::assembly::x86::OPCODE::PADDSBrr) + .value("PADDSWrm", LIEF::assembly::x86::OPCODE::PADDSWrm) + .value("PADDSWrr", LIEF::assembly::x86::OPCODE::PADDSWrr) + .value("PADDUSBrm", LIEF::assembly::x86::OPCODE::PADDUSBrm) + .value("PADDUSBrr", LIEF::assembly::x86::OPCODE::PADDUSBrr) + .value("PADDUSWrm", LIEF::assembly::x86::OPCODE::PADDUSWrm) + .value("PADDUSWrr", LIEF::assembly::x86::OPCODE::PADDUSWrr) + .value("PADDWrm", LIEF::assembly::x86::OPCODE::PADDWrm) + .value("PADDWrr", LIEF::assembly::x86::OPCODE::PADDWrr) + .value("PALIGNRrmi", LIEF::assembly::x86::OPCODE::PALIGNRrmi) + .value("PALIGNRrri", LIEF::assembly::x86::OPCODE::PALIGNRrri) + .value("PANDNrm", LIEF::assembly::x86::OPCODE::PANDNrm) + .value("PANDNrr", LIEF::assembly::x86::OPCODE::PANDNrr) + .value("PANDrm", LIEF::assembly::x86::OPCODE::PANDrm) + .value("PANDrr", LIEF::assembly::x86::OPCODE::PANDrr) + .value("PAUSE", LIEF::assembly::x86::OPCODE::PAUSE) + .value("PAVGBrm", LIEF::assembly::x86::OPCODE::PAVGBrm) + .value("PAVGBrr", LIEF::assembly::x86::OPCODE::PAVGBrr) + .value("PAVGUSBrm", LIEF::assembly::x86::OPCODE::PAVGUSBrm) + .value("PAVGUSBrr", LIEF::assembly::x86::OPCODE::PAVGUSBrr) + .value("PAVGWrm", LIEF::assembly::x86::OPCODE::PAVGWrm) + .value("PAVGWrr", LIEF::assembly::x86::OPCODE::PAVGWrr) + .value("PBLENDVBrm0", LIEF::assembly::x86::OPCODE::PBLENDVBrm0) + .value("PBLENDVBrr0", LIEF::assembly::x86::OPCODE::PBLENDVBrr0) + .value("PBLENDWrmi", LIEF::assembly::x86::OPCODE::PBLENDWrmi) + .value("PBLENDWrri", LIEF::assembly::x86::OPCODE::PBLENDWrri) + .value("PBNDKB", LIEF::assembly::x86::OPCODE::PBNDKB) + .value("PCLMULQDQrmi", LIEF::assembly::x86::OPCODE::PCLMULQDQrmi) + .value("PCLMULQDQrri", LIEF::assembly::x86::OPCODE::PCLMULQDQrri) + .value("PCMPEQBrm", LIEF::assembly::x86::OPCODE::PCMPEQBrm) + .value("PCMPEQBrr", LIEF::assembly::x86::OPCODE::PCMPEQBrr) + .value("PCMPEQDrm", LIEF::assembly::x86::OPCODE::PCMPEQDrm) + .value("PCMPEQDrr", LIEF::assembly::x86::OPCODE::PCMPEQDrr) + .value("PCMPEQQrm", LIEF::assembly::x86::OPCODE::PCMPEQQrm) + .value("PCMPEQQrr", LIEF::assembly::x86::OPCODE::PCMPEQQrr) + .value("PCMPEQWrm", LIEF::assembly::x86::OPCODE::PCMPEQWrm) + .value("PCMPEQWrr", LIEF::assembly::x86::OPCODE::PCMPEQWrr) + .value("PCMPESTRIrmi", LIEF::assembly::x86::OPCODE::PCMPESTRIrmi) + .value("PCMPESTRIrri", LIEF::assembly::x86::OPCODE::PCMPESTRIrri) + .value("PCMPESTRMrmi", LIEF::assembly::x86::OPCODE::PCMPESTRMrmi) + .value("PCMPESTRMrri", LIEF::assembly::x86::OPCODE::PCMPESTRMrri) + .value("PCMPGTBrm", LIEF::assembly::x86::OPCODE::PCMPGTBrm) + .value("PCMPGTBrr", LIEF::assembly::x86::OPCODE::PCMPGTBrr) + .value("PCMPGTDrm", LIEF::assembly::x86::OPCODE::PCMPGTDrm) + .value("PCMPGTDrr", LIEF::assembly::x86::OPCODE::PCMPGTDrr) + .value("PCMPGTQrm", LIEF::assembly::x86::OPCODE::PCMPGTQrm) + .value("PCMPGTQrr", LIEF::assembly::x86::OPCODE::PCMPGTQrr) + .value("PCMPGTWrm", LIEF::assembly::x86::OPCODE::PCMPGTWrm) + .value("PCMPGTWrr", LIEF::assembly::x86::OPCODE::PCMPGTWrr) + .value("PCMPISTRIrmi", LIEF::assembly::x86::OPCODE::PCMPISTRIrmi) + .value("PCMPISTRIrri", LIEF::assembly::x86::OPCODE::PCMPISTRIrri) + .value("PCMPISTRMrmi", LIEF::assembly::x86::OPCODE::PCMPISTRMrmi) + .value("PCMPISTRMrri", LIEF::assembly::x86::OPCODE::PCMPISTRMrri) + .value("PCONFIG", LIEF::assembly::x86::OPCODE::PCONFIG) + .value("PDEP32rm", LIEF::assembly::x86::OPCODE::PDEP32rm) + .value("PDEP32rm_EVEX", LIEF::assembly::x86::OPCODE::PDEP32rm_EVEX) + .value("PDEP32rr", LIEF::assembly::x86::OPCODE::PDEP32rr) + .value("PDEP32rr_EVEX", LIEF::assembly::x86::OPCODE::PDEP32rr_EVEX) + .value("PDEP64rm", LIEF::assembly::x86::OPCODE::PDEP64rm) + .value("PDEP64rm_EVEX", LIEF::assembly::x86::OPCODE::PDEP64rm_EVEX) + .value("PDEP64rr", LIEF::assembly::x86::OPCODE::PDEP64rr) + .value("PDEP64rr_EVEX", LIEF::assembly::x86::OPCODE::PDEP64rr_EVEX) + .value("PEXT32rm", LIEF::assembly::x86::OPCODE::PEXT32rm) + .value("PEXT32rm_EVEX", LIEF::assembly::x86::OPCODE::PEXT32rm_EVEX) + .value("PEXT32rr", LIEF::assembly::x86::OPCODE::PEXT32rr) + .value("PEXT32rr_EVEX", LIEF::assembly::x86::OPCODE::PEXT32rr_EVEX) + .value("PEXT64rm", LIEF::assembly::x86::OPCODE::PEXT64rm) + .value("PEXT64rm_EVEX", LIEF::assembly::x86::OPCODE::PEXT64rm_EVEX) + .value("PEXT64rr", LIEF::assembly::x86::OPCODE::PEXT64rr) + .value("PEXT64rr_EVEX", LIEF::assembly::x86::OPCODE::PEXT64rr_EVEX) + .value("PEXTRBmri", LIEF::assembly::x86::OPCODE::PEXTRBmri) + .value("PEXTRBrri", LIEF::assembly::x86::OPCODE::PEXTRBrri) + .value("PEXTRDmri", LIEF::assembly::x86::OPCODE::PEXTRDmri) + .value("PEXTRDrri", LIEF::assembly::x86::OPCODE::PEXTRDrri) + .value("PEXTRQmri", LIEF::assembly::x86::OPCODE::PEXTRQmri) + .value("PEXTRQrri", LIEF::assembly::x86::OPCODE::PEXTRQrri) + .value("PEXTRWmri", LIEF::assembly::x86::OPCODE::PEXTRWmri) + .value("PEXTRWrri", LIEF::assembly::x86::OPCODE::PEXTRWrri) + .value("PEXTRWrri_REV", LIEF::assembly::x86::OPCODE::PEXTRWrri_REV) + .value("PF2IDrm", LIEF::assembly::x86::OPCODE::PF2IDrm) + .value("PF2IDrr", LIEF::assembly::x86::OPCODE::PF2IDrr) + .value("PF2IWrm", LIEF::assembly::x86::OPCODE::PF2IWrm) + .value("PF2IWrr", LIEF::assembly::x86::OPCODE::PF2IWrr) + .value("PFACCrm", LIEF::assembly::x86::OPCODE::PFACCrm) + .value("PFACCrr", LIEF::assembly::x86::OPCODE::PFACCrr) + .value("PFADDrm", LIEF::assembly::x86::OPCODE::PFADDrm) + .value("PFADDrr", LIEF::assembly::x86::OPCODE::PFADDrr) + .value("PFCMPEQrm", LIEF::assembly::x86::OPCODE::PFCMPEQrm) + .value("PFCMPEQrr", LIEF::assembly::x86::OPCODE::PFCMPEQrr) + .value("PFCMPGErm", LIEF::assembly::x86::OPCODE::PFCMPGErm) + .value("PFCMPGErr", LIEF::assembly::x86::OPCODE::PFCMPGErr) + .value("PFCMPGTrm", LIEF::assembly::x86::OPCODE::PFCMPGTrm) + .value("PFCMPGTrr", LIEF::assembly::x86::OPCODE::PFCMPGTrr) + .value("PFMAXrm", LIEF::assembly::x86::OPCODE::PFMAXrm) + .value("PFMAXrr", LIEF::assembly::x86::OPCODE::PFMAXrr) + .value("PFMINrm", LIEF::assembly::x86::OPCODE::PFMINrm) + .value("PFMINrr", LIEF::assembly::x86::OPCODE::PFMINrr) + .value("PFMULrm", LIEF::assembly::x86::OPCODE::PFMULrm) + .value("PFMULrr", LIEF::assembly::x86::OPCODE::PFMULrr) + .value("PFNACCrm", LIEF::assembly::x86::OPCODE::PFNACCrm) + .value("PFNACCrr", LIEF::assembly::x86::OPCODE::PFNACCrr) + .value("PFPNACCrm", LIEF::assembly::x86::OPCODE::PFPNACCrm) + .value("PFPNACCrr", LIEF::assembly::x86::OPCODE::PFPNACCrr) + .value("PFRCPIT1rm", LIEF::assembly::x86::OPCODE::PFRCPIT1rm) + .value("PFRCPIT1rr", LIEF::assembly::x86::OPCODE::PFRCPIT1rr) + .value("PFRCPIT2rm", LIEF::assembly::x86::OPCODE::PFRCPIT2rm) + .value("PFRCPIT2rr", LIEF::assembly::x86::OPCODE::PFRCPIT2rr) + .value("PFRCPrm", LIEF::assembly::x86::OPCODE::PFRCPrm) + .value("PFRCPrr", LIEF::assembly::x86::OPCODE::PFRCPrr) + .value("PFRSQIT1rm", LIEF::assembly::x86::OPCODE::PFRSQIT1rm) + .value("PFRSQIT1rr", LIEF::assembly::x86::OPCODE::PFRSQIT1rr) + .value("PFRSQRTrm", LIEF::assembly::x86::OPCODE::PFRSQRTrm) + .value("PFRSQRTrr", LIEF::assembly::x86::OPCODE::PFRSQRTrr) + .value("PFSUBRrm", LIEF::assembly::x86::OPCODE::PFSUBRrm) + .value("PFSUBRrr", LIEF::assembly::x86::OPCODE::PFSUBRrr) + .value("PFSUBrm", LIEF::assembly::x86::OPCODE::PFSUBrm) + .value("PFSUBrr", LIEF::assembly::x86::OPCODE::PFSUBrr) + .value("PHADDDrm", LIEF::assembly::x86::OPCODE::PHADDDrm) + .value("PHADDDrr", LIEF::assembly::x86::OPCODE::PHADDDrr) + .value("PHADDSWrm", LIEF::assembly::x86::OPCODE::PHADDSWrm) + .value("PHADDSWrr", LIEF::assembly::x86::OPCODE::PHADDSWrr) + .value("PHADDWrm", LIEF::assembly::x86::OPCODE::PHADDWrm) + .value("PHADDWrr", LIEF::assembly::x86::OPCODE::PHADDWrr) + .value("PHMINPOSUWrm", LIEF::assembly::x86::OPCODE::PHMINPOSUWrm) + .value("PHMINPOSUWrr", LIEF::assembly::x86::OPCODE::PHMINPOSUWrr) + .value("PHSUBDrm", LIEF::assembly::x86::OPCODE::PHSUBDrm) + .value("PHSUBDrr", LIEF::assembly::x86::OPCODE::PHSUBDrr) + .value("PHSUBSWrm", LIEF::assembly::x86::OPCODE::PHSUBSWrm) + .value("PHSUBSWrr", LIEF::assembly::x86::OPCODE::PHSUBSWrr) + .value("PHSUBWrm", LIEF::assembly::x86::OPCODE::PHSUBWrm) + .value("PHSUBWrr", LIEF::assembly::x86::OPCODE::PHSUBWrr) + .value("PI2FDrm", LIEF::assembly::x86::OPCODE::PI2FDrm) + .value("PI2FDrr", LIEF::assembly::x86::OPCODE::PI2FDrr) + .value("PI2FWrm", LIEF::assembly::x86::OPCODE::PI2FWrm) + .value("PI2FWrr", LIEF::assembly::x86::OPCODE::PI2FWrr) + .value("PINSRBrmi", LIEF::assembly::x86::OPCODE::PINSRBrmi) + .value("PINSRBrri", LIEF::assembly::x86::OPCODE::PINSRBrri) + .value("PINSRDrmi", LIEF::assembly::x86::OPCODE::PINSRDrmi) + .value("PINSRDrri", LIEF::assembly::x86::OPCODE::PINSRDrri) + .value("PINSRQrmi", LIEF::assembly::x86::OPCODE::PINSRQrmi) + .value("PINSRQrri", LIEF::assembly::x86::OPCODE::PINSRQrri) + .value("PINSRWrmi", LIEF::assembly::x86::OPCODE::PINSRWrmi) + .value("PINSRWrri", LIEF::assembly::x86::OPCODE::PINSRWrri) + .value("PMADDUBSWrm", LIEF::assembly::x86::OPCODE::PMADDUBSWrm) + .value("PMADDUBSWrr", LIEF::assembly::x86::OPCODE::PMADDUBSWrr) + .value("PMADDWDrm", LIEF::assembly::x86::OPCODE::PMADDWDrm) + .value("PMADDWDrr", LIEF::assembly::x86::OPCODE::PMADDWDrr) + .value("PMAXSBrm", LIEF::assembly::x86::OPCODE::PMAXSBrm) + .value("PMAXSBrr", LIEF::assembly::x86::OPCODE::PMAXSBrr) + .value("PMAXSDrm", LIEF::assembly::x86::OPCODE::PMAXSDrm) + .value("PMAXSDrr", LIEF::assembly::x86::OPCODE::PMAXSDrr) + .value("PMAXSWrm", LIEF::assembly::x86::OPCODE::PMAXSWrm) + .value("PMAXSWrr", LIEF::assembly::x86::OPCODE::PMAXSWrr) + .value("PMAXUBrm", LIEF::assembly::x86::OPCODE::PMAXUBrm) + .value("PMAXUBrr", LIEF::assembly::x86::OPCODE::PMAXUBrr) + .value("PMAXUDrm", LIEF::assembly::x86::OPCODE::PMAXUDrm) + .value("PMAXUDrr", LIEF::assembly::x86::OPCODE::PMAXUDrr) + .value("PMAXUWrm", LIEF::assembly::x86::OPCODE::PMAXUWrm) + .value("PMAXUWrr", LIEF::assembly::x86::OPCODE::PMAXUWrr) + .value("PMINSBrm", LIEF::assembly::x86::OPCODE::PMINSBrm) + .value("PMINSBrr", LIEF::assembly::x86::OPCODE::PMINSBrr) + .value("PMINSDrm", LIEF::assembly::x86::OPCODE::PMINSDrm) + .value("PMINSDrr", LIEF::assembly::x86::OPCODE::PMINSDrr) + .value("PMINSWrm", LIEF::assembly::x86::OPCODE::PMINSWrm) + .value("PMINSWrr", LIEF::assembly::x86::OPCODE::PMINSWrr) + .value("PMINUBrm", LIEF::assembly::x86::OPCODE::PMINUBrm) + .value("PMINUBrr", LIEF::assembly::x86::OPCODE::PMINUBrr) + .value("PMINUDrm", LIEF::assembly::x86::OPCODE::PMINUDrm) + .value("PMINUDrr", LIEF::assembly::x86::OPCODE::PMINUDrr) + .value("PMINUWrm", LIEF::assembly::x86::OPCODE::PMINUWrm) + .value("PMINUWrr", LIEF::assembly::x86::OPCODE::PMINUWrr) + .value("PMOVMSKBrr", LIEF::assembly::x86::OPCODE::PMOVMSKBrr) + .value("PMOVSXBDrm", LIEF::assembly::x86::OPCODE::PMOVSXBDrm) + .value("PMOVSXBDrr", LIEF::assembly::x86::OPCODE::PMOVSXBDrr) + .value("PMOVSXBQrm", LIEF::assembly::x86::OPCODE::PMOVSXBQrm) + .value("PMOVSXBQrr", LIEF::assembly::x86::OPCODE::PMOVSXBQrr) + .value("PMOVSXBWrm", LIEF::assembly::x86::OPCODE::PMOVSXBWrm) + .value("PMOVSXBWrr", LIEF::assembly::x86::OPCODE::PMOVSXBWrr) + .value("PMOVSXDQrm", LIEF::assembly::x86::OPCODE::PMOVSXDQrm) + .value("PMOVSXDQrr", LIEF::assembly::x86::OPCODE::PMOVSXDQrr) + .value("PMOVSXWDrm", LIEF::assembly::x86::OPCODE::PMOVSXWDrm) + .value("PMOVSXWDrr", LIEF::assembly::x86::OPCODE::PMOVSXWDrr) + .value("PMOVSXWQrm", LIEF::assembly::x86::OPCODE::PMOVSXWQrm) + .value("PMOVSXWQrr", LIEF::assembly::x86::OPCODE::PMOVSXWQrr) + .value("PMOVZXBDrm", LIEF::assembly::x86::OPCODE::PMOVZXBDrm) + .value("PMOVZXBDrr", LIEF::assembly::x86::OPCODE::PMOVZXBDrr) + .value("PMOVZXBQrm", LIEF::assembly::x86::OPCODE::PMOVZXBQrm) + .value("PMOVZXBQrr", LIEF::assembly::x86::OPCODE::PMOVZXBQrr) + .value("PMOVZXBWrm", LIEF::assembly::x86::OPCODE::PMOVZXBWrm) + .value("PMOVZXBWrr", LIEF::assembly::x86::OPCODE::PMOVZXBWrr) + .value("PMOVZXDQrm", LIEF::assembly::x86::OPCODE::PMOVZXDQrm) + .value("PMOVZXDQrr", LIEF::assembly::x86::OPCODE::PMOVZXDQrr) + .value("PMOVZXWDrm", LIEF::assembly::x86::OPCODE::PMOVZXWDrm) + .value("PMOVZXWDrr", LIEF::assembly::x86::OPCODE::PMOVZXWDrr) + .value("PMOVZXWQrm", LIEF::assembly::x86::OPCODE::PMOVZXWQrm) + .value("PMOVZXWQrr", LIEF::assembly::x86::OPCODE::PMOVZXWQrr) + .value("PMULDQrm", LIEF::assembly::x86::OPCODE::PMULDQrm) + .value("PMULDQrr", LIEF::assembly::x86::OPCODE::PMULDQrr) + .value("PMULHRSWrm", LIEF::assembly::x86::OPCODE::PMULHRSWrm) + .value("PMULHRSWrr", LIEF::assembly::x86::OPCODE::PMULHRSWrr) + .value("PMULHRWrm", LIEF::assembly::x86::OPCODE::PMULHRWrm) + .value("PMULHRWrr", LIEF::assembly::x86::OPCODE::PMULHRWrr) + .value("PMULHUWrm", LIEF::assembly::x86::OPCODE::PMULHUWrm) + .value("PMULHUWrr", LIEF::assembly::x86::OPCODE::PMULHUWrr) + .value("PMULHWrm", LIEF::assembly::x86::OPCODE::PMULHWrm); + opcodes.value("PMULHWrr", LIEF::assembly::x86::OPCODE::PMULHWrr) + .value("PMULLDrm", LIEF::assembly::x86::OPCODE::PMULLDrm) + .value("PMULLDrr", LIEF::assembly::x86::OPCODE::PMULLDrr) + .value("PMULLWrm", LIEF::assembly::x86::OPCODE::PMULLWrm) + .value("PMULLWrr", LIEF::assembly::x86::OPCODE::PMULLWrr) + .value("PMULUDQrm", LIEF::assembly::x86::OPCODE::PMULUDQrm) + .value("PMULUDQrr", LIEF::assembly::x86::OPCODE::PMULUDQrr) + .value("POP16r", LIEF::assembly::x86::OPCODE::POP16r) + .value("POP16rmm", LIEF::assembly::x86::OPCODE::POP16rmm) + .value("POP16rmr", LIEF::assembly::x86::OPCODE::POP16rmr) + .value("POP2", LIEF::assembly::x86::OPCODE::POP2) + .value("POP2P", LIEF::assembly::x86::OPCODE::POP2P) + .value("POP32r", LIEF::assembly::x86::OPCODE::POP32r) + .value("POP32rmm", LIEF::assembly::x86::OPCODE::POP32rmm) + .value("POP32rmr", LIEF::assembly::x86::OPCODE::POP32rmr) + .value("POP64r", LIEF::assembly::x86::OPCODE::POP64r) + .value("POP64rmm", LIEF::assembly::x86::OPCODE::POP64rmm) + .value("POP64rmr", LIEF::assembly::x86::OPCODE::POP64rmr) + .value("POPA16", LIEF::assembly::x86::OPCODE::POPA16) + .value("POPA32", LIEF::assembly::x86::OPCODE::POPA32) + .value("POPCNT16rm", LIEF::assembly::x86::OPCODE::POPCNT16rm) + .value("POPCNT16rm_EVEX", LIEF::assembly::x86::OPCODE::POPCNT16rm_EVEX) + .value("POPCNT16rm_NF", LIEF::assembly::x86::OPCODE::POPCNT16rm_NF) + .value("POPCNT16rr", LIEF::assembly::x86::OPCODE::POPCNT16rr) + .value("POPCNT16rr_EVEX", LIEF::assembly::x86::OPCODE::POPCNT16rr_EVEX) + .value("POPCNT16rr_NF", LIEF::assembly::x86::OPCODE::POPCNT16rr_NF) + .value("POPCNT32rm", LIEF::assembly::x86::OPCODE::POPCNT32rm) + .value("POPCNT32rm_EVEX", LIEF::assembly::x86::OPCODE::POPCNT32rm_EVEX) + .value("POPCNT32rm_NF", LIEF::assembly::x86::OPCODE::POPCNT32rm_NF) + .value("POPCNT32rr", LIEF::assembly::x86::OPCODE::POPCNT32rr) + .value("POPCNT32rr_EVEX", LIEF::assembly::x86::OPCODE::POPCNT32rr_EVEX) + .value("POPCNT32rr_NF", LIEF::assembly::x86::OPCODE::POPCNT32rr_NF) + .value("POPCNT64rm", LIEF::assembly::x86::OPCODE::POPCNT64rm) + .value("POPCNT64rm_EVEX", LIEF::assembly::x86::OPCODE::POPCNT64rm_EVEX) + .value("POPCNT64rm_NF", LIEF::assembly::x86::OPCODE::POPCNT64rm_NF) + .value("POPCNT64rr", LIEF::assembly::x86::OPCODE::POPCNT64rr) + .value("POPCNT64rr_EVEX", LIEF::assembly::x86::OPCODE::POPCNT64rr_EVEX) + .value("POPCNT64rr_NF", LIEF::assembly::x86::OPCODE::POPCNT64rr_NF) + .value("POPDS16", LIEF::assembly::x86::OPCODE::POPDS16) + .value("POPDS32", LIEF::assembly::x86::OPCODE::POPDS32) + .value("POPES16", LIEF::assembly::x86::OPCODE::POPES16) + .value("POPES32", LIEF::assembly::x86::OPCODE::POPES32) + .value("POPF16", LIEF::assembly::x86::OPCODE::POPF16) + .value("POPF32", LIEF::assembly::x86::OPCODE::POPF32) + .value("POPF64", LIEF::assembly::x86::OPCODE::POPF64) + .value("POPFS16", LIEF::assembly::x86::OPCODE::POPFS16) + .value("POPFS32", LIEF::assembly::x86::OPCODE::POPFS32) + .value("POPFS64", LIEF::assembly::x86::OPCODE::POPFS64) + .value("POPGS16", LIEF::assembly::x86::OPCODE::POPGS16) + .value("POPGS32", LIEF::assembly::x86::OPCODE::POPGS32) + .value("POPGS64", LIEF::assembly::x86::OPCODE::POPGS64) + .value("POPP64r", LIEF::assembly::x86::OPCODE::POPP64r) + .value("POPSS16", LIEF::assembly::x86::OPCODE::POPSS16) + .value("POPSS32", LIEF::assembly::x86::OPCODE::POPSS32) + .value("PORrm", LIEF::assembly::x86::OPCODE::PORrm) + .value("PORrr", LIEF::assembly::x86::OPCODE::PORrr) + .value("PREFETCH", LIEF::assembly::x86::OPCODE::PREFETCH) + .value("PREFETCHIT0", LIEF::assembly::x86::OPCODE::PREFETCHIT0) + .value("PREFETCHIT1", LIEF::assembly::x86::OPCODE::PREFETCHIT1) + .value("PREFETCHNTA", LIEF::assembly::x86::OPCODE::PREFETCHNTA) + .value("PREFETCHRST2", LIEF::assembly::x86::OPCODE::PREFETCHRST2) + .value("PREFETCHT0", LIEF::assembly::x86::OPCODE::PREFETCHT0) + .value("PREFETCHT1", LIEF::assembly::x86::OPCODE::PREFETCHT1) + .value("PREFETCHT2", LIEF::assembly::x86::OPCODE::PREFETCHT2) + .value("PREFETCHW", LIEF::assembly::x86::OPCODE::PREFETCHW) + .value("PREFETCHWT1", LIEF::assembly::x86::OPCODE::PREFETCHWT1) + .value("PROBED_ALLOCA_32", LIEF::assembly::x86::OPCODE::PROBED_ALLOCA_32) + .value("PROBED_ALLOCA_64", LIEF::assembly::x86::OPCODE::PROBED_ALLOCA_64) + .value("PSADBWrm", LIEF::assembly::x86::OPCODE::PSADBWrm) + .value("PSADBWrr", LIEF::assembly::x86::OPCODE::PSADBWrr) + .value("PSHUFBrm", LIEF::assembly::x86::OPCODE::PSHUFBrm) + .value("PSHUFBrr", LIEF::assembly::x86::OPCODE::PSHUFBrr) + .value("PSHUFDmi", LIEF::assembly::x86::OPCODE::PSHUFDmi) + .value("PSHUFDri", LIEF::assembly::x86::OPCODE::PSHUFDri) + .value("PSHUFHWmi", LIEF::assembly::x86::OPCODE::PSHUFHWmi) + .value("PSHUFHWri", LIEF::assembly::x86::OPCODE::PSHUFHWri) + .value("PSHUFLWmi", LIEF::assembly::x86::OPCODE::PSHUFLWmi) + .value("PSHUFLWri", LIEF::assembly::x86::OPCODE::PSHUFLWri) + .value("PSIGNBrm", LIEF::assembly::x86::OPCODE::PSIGNBrm) + .value("PSIGNBrr", LIEF::assembly::x86::OPCODE::PSIGNBrr) + .value("PSIGNDrm", LIEF::assembly::x86::OPCODE::PSIGNDrm) + .value("PSIGNDrr", LIEF::assembly::x86::OPCODE::PSIGNDrr) + .value("PSIGNWrm", LIEF::assembly::x86::OPCODE::PSIGNWrm) + .value("PSIGNWrr", LIEF::assembly::x86::OPCODE::PSIGNWrr) + .value("PSLLDQri", LIEF::assembly::x86::OPCODE::PSLLDQri) + .value("PSLLDri", LIEF::assembly::x86::OPCODE::PSLLDri) + .value("PSLLDrm", LIEF::assembly::x86::OPCODE::PSLLDrm) + .value("PSLLDrr", LIEF::assembly::x86::OPCODE::PSLLDrr) + .value("PSLLQri", LIEF::assembly::x86::OPCODE::PSLLQri) + .value("PSLLQrm", LIEF::assembly::x86::OPCODE::PSLLQrm) + .value("PSLLQrr", LIEF::assembly::x86::OPCODE::PSLLQrr) + .value("PSLLWri", LIEF::assembly::x86::OPCODE::PSLLWri) + .value("PSLLWrm", LIEF::assembly::x86::OPCODE::PSLLWrm) + .value("PSLLWrr", LIEF::assembly::x86::OPCODE::PSLLWrr) + .value("PSMASH", LIEF::assembly::x86::OPCODE::PSMASH) + .value("PSRADri", LIEF::assembly::x86::OPCODE::PSRADri) + .value("PSRADrm", LIEF::assembly::x86::OPCODE::PSRADrm) + .value("PSRADrr", LIEF::assembly::x86::OPCODE::PSRADrr) + .value("PSRAWri", LIEF::assembly::x86::OPCODE::PSRAWri) + .value("PSRAWrm", LIEF::assembly::x86::OPCODE::PSRAWrm) + .value("PSRAWrr", LIEF::assembly::x86::OPCODE::PSRAWrr) + .value("PSRLDQri", LIEF::assembly::x86::OPCODE::PSRLDQri) + .value("PSRLDri", LIEF::assembly::x86::OPCODE::PSRLDri) + .value("PSRLDrm", LIEF::assembly::x86::OPCODE::PSRLDrm) + .value("PSRLDrr", LIEF::assembly::x86::OPCODE::PSRLDrr) + .value("PSRLQri", LIEF::assembly::x86::OPCODE::PSRLQri) + .value("PSRLQrm", LIEF::assembly::x86::OPCODE::PSRLQrm) + .value("PSRLQrr", LIEF::assembly::x86::OPCODE::PSRLQrr) + .value("PSRLWri", LIEF::assembly::x86::OPCODE::PSRLWri) + .value("PSRLWrm", LIEF::assembly::x86::OPCODE::PSRLWrm) + .value("PSRLWrr", LIEF::assembly::x86::OPCODE::PSRLWrr) + .value("PSUBBrm", LIEF::assembly::x86::OPCODE::PSUBBrm) + .value("PSUBBrr", LIEF::assembly::x86::OPCODE::PSUBBrr) + .value("PSUBDrm", LIEF::assembly::x86::OPCODE::PSUBDrm) + .value("PSUBDrr", LIEF::assembly::x86::OPCODE::PSUBDrr) + .value("PSUBQrm", LIEF::assembly::x86::OPCODE::PSUBQrm) + .value("PSUBQrr", LIEF::assembly::x86::OPCODE::PSUBQrr) + .value("PSUBSBrm", LIEF::assembly::x86::OPCODE::PSUBSBrm) + .value("PSUBSBrr", LIEF::assembly::x86::OPCODE::PSUBSBrr) + .value("PSUBSWrm", LIEF::assembly::x86::OPCODE::PSUBSWrm) + .value("PSUBSWrr", LIEF::assembly::x86::OPCODE::PSUBSWrr) + .value("PSUBUSBrm", LIEF::assembly::x86::OPCODE::PSUBUSBrm) + .value("PSUBUSBrr", LIEF::assembly::x86::OPCODE::PSUBUSBrr) + .value("PSUBUSWrm", LIEF::assembly::x86::OPCODE::PSUBUSWrm) + .value("PSUBUSWrr", LIEF::assembly::x86::OPCODE::PSUBUSWrr) + .value("PSUBWrm", LIEF::assembly::x86::OPCODE::PSUBWrm) + .value("PSUBWrr", LIEF::assembly::x86::OPCODE::PSUBWrr) + .value("PSWAPDrm", LIEF::assembly::x86::OPCODE::PSWAPDrm) + .value("PSWAPDrr", LIEF::assembly::x86::OPCODE::PSWAPDrr) + .value("PTCMMIMFP16PS", LIEF::assembly::x86::OPCODE::PTCMMIMFP16PS) + .value("PTCMMIMFP16PSV", LIEF::assembly::x86::OPCODE::PTCMMIMFP16PSV) + .value("PTCMMRLFP16PS", LIEF::assembly::x86::OPCODE::PTCMMRLFP16PS) + .value("PTCMMRLFP16PSV", LIEF::assembly::x86::OPCODE::PTCMMRLFP16PSV) + .value("PTCVTROWD2PSrre", LIEF::assembly::x86::OPCODE::PTCVTROWD2PSrre) + .value("PTCVTROWD2PSrreV", LIEF::assembly::x86::OPCODE::PTCVTROWD2PSrreV) + .value("PTCVTROWD2PSrri", LIEF::assembly::x86::OPCODE::PTCVTROWD2PSrri) + .value("PTCVTROWD2PSrriV", LIEF::assembly::x86::OPCODE::PTCVTROWD2PSrriV) + .value("PTCVTROWPS2BF16Hrre", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16Hrre) + .value("PTCVTROWPS2BF16HrreV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16HrreV) + .value("PTCVTROWPS2BF16Hrri", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16Hrri) + .value("PTCVTROWPS2BF16HrriV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16HrriV) + .value("PTCVTROWPS2BF16Lrre", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16Lrre) + .value("PTCVTROWPS2BF16LrreV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16LrreV) + .value("PTCVTROWPS2BF16Lrri", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16Lrri) + .value("PTCVTROWPS2BF16LrriV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2BF16LrriV) + .value("PTCVTROWPS2PHHrre", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHHrre) + .value("PTCVTROWPS2PHHrreV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHHrreV) + .value("PTCVTROWPS2PHHrri", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHHrri) + .value("PTCVTROWPS2PHHrriV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHHrriV) + .value("PTCVTROWPS2PHLrre", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHLrre) + .value("PTCVTROWPS2PHLrreV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHLrreV) + .value("PTCVTROWPS2PHLrri", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHLrri) + .value("PTCVTROWPS2PHLrriV", LIEF::assembly::x86::OPCODE::PTCVTROWPS2PHLrriV) + .value("PTDPBF16PS", LIEF::assembly::x86::OPCODE::PTDPBF16PS) + .value("PTDPBF8PS", LIEF::assembly::x86::OPCODE::PTDPBF8PS) + .value("PTDPBF8PSV", LIEF::assembly::x86::OPCODE::PTDPBF8PSV) + .value("PTDPBHF8PS", LIEF::assembly::x86::OPCODE::PTDPBHF8PS) + .value("PTDPBHF8PSV", LIEF::assembly::x86::OPCODE::PTDPBHF8PSV) + .value("PTDPBSSD", LIEF::assembly::x86::OPCODE::PTDPBSSD) + .value("PTDPBSUD", LIEF::assembly::x86::OPCODE::PTDPBSUD) + .value("PTDPBUSD", LIEF::assembly::x86::OPCODE::PTDPBUSD) + .value("PTDPBUUD", LIEF::assembly::x86::OPCODE::PTDPBUUD) + .value("PTDPFP16PS", LIEF::assembly::x86::OPCODE::PTDPFP16PS) + .value("PTDPHBF8PS", LIEF::assembly::x86::OPCODE::PTDPHBF8PS) + .value("PTDPHBF8PSV", LIEF::assembly::x86::OPCODE::PTDPHBF8PSV) + .value("PTDPHF8PS", LIEF::assembly::x86::OPCODE::PTDPHF8PS) + .value("PTDPHF8PSV", LIEF::assembly::x86::OPCODE::PTDPHF8PSV) + .value("PTESTrm", LIEF::assembly::x86::OPCODE::PTESTrm) + .value("PTESTrr", LIEF::assembly::x86::OPCODE::PTESTrr) + .value("PTILELOADD", LIEF::assembly::x86::OPCODE::PTILELOADD) + .value("PTILELOADDRS", LIEF::assembly::x86::OPCODE::PTILELOADDRS) + .value("PTILELOADDRST1", LIEF::assembly::x86::OPCODE::PTILELOADDRST1) + .value("PTILELOADDT1", LIEF::assembly::x86::OPCODE::PTILELOADDT1) + .value("PTILEMOVROWrre", LIEF::assembly::x86::OPCODE::PTILEMOVROWrre) + .value("PTILEMOVROWrreV", LIEF::assembly::x86::OPCODE::PTILEMOVROWrreV) + .value("PTILEMOVROWrri", LIEF::assembly::x86::OPCODE::PTILEMOVROWrri) + .value("PTILEMOVROWrriV", LIEF::assembly::x86::OPCODE::PTILEMOVROWrriV) + .value("PTILESTORED", LIEF::assembly::x86::OPCODE::PTILESTORED) + .value("PTILEZERO", LIEF::assembly::x86::OPCODE::PTILEZERO) + .value("PTMMULTF32PS", LIEF::assembly::x86::OPCODE::PTMMULTF32PS) + .value("PTMMULTF32PSV", LIEF::assembly::x86::OPCODE::PTMMULTF32PSV) + .value("PTWRITE64m", LIEF::assembly::x86::OPCODE::PTWRITE64m) + .value("PTWRITE64r", LIEF::assembly::x86::OPCODE::PTWRITE64r) + .value("PTWRITEm", LIEF::assembly::x86::OPCODE::PTWRITEm) + .value("PTWRITEr", LIEF::assembly::x86::OPCODE::PTWRITEr) + .value("PUNPCKHBWrm", LIEF::assembly::x86::OPCODE::PUNPCKHBWrm) + .value("PUNPCKHBWrr", LIEF::assembly::x86::OPCODE::PUNPCKHBWrr) + .value("PUNPCKHDQrm", LIEF::assembly::x86::OPCODE::PUNPCKHDQrm) + .value("PUNPCKHDQrr", LIEF::assembly::x86::OPCODE::PUNPCKHDQrr) + .value("PUNPCKHQDQrm", LIEF::assembly::x86::OPCODE::PUNPCKHQDQrm) + .value("PUNPCKHQDQrr", LIEF::assembly::x86::OPCODE::PUNPCKHQDQrr) + .value("PUNPCKHWDrm", LIEF::assembly::x86::OPCODE::PUNPCKHWDrm) + .value("PUNPCKHWDrr", LIEF::assembly::x86::OPCODE::PUNPCKHWDrr) + .value("PUNPCKLBWrm", LIEF::assembly::x86::OPCODE::PUNPCKLBWrm) + .value("PUNPCKLBWrr", LIEF::assembly::x86::OPCODE::PUNPCKLBWrr) + .value("PUNPCKLDQrm", LIEF::assembly::x86::OPCODE::PUNPCKLDQrm) + .value("PUNPCKLDQrr", LIEF::assembly::x86::OPCODE::PUNPCKLDQrr) + .value("PUNPCKLQDQrm", LIEF::assembly::x86::OPCODE::PUNPCKLQDQrm) + .value("PUNPCKLQDQrr", LIEF::assembly::x86::OPCODE::PUNPCKLQDQrr) + .value("PUNPCKLWDrm", LIEF::assembly::x86::OPCODE::PUNPCKLWDrm) + .value("PUNPCKLWDrr", LIEF::assembly::x86::OPCODE::PUNPCKLWDrr) + .value("PUSH16i", LIEF::assembly::x86::OPCODE::PUSH16i) + .value("PUSH16i8", LIEF::assembly::x86::OPCODE::PUSH16i8) + .value("PUSH16r", LIEF::assembly::x86::OPCODE::PUSH16r) + .value("PUSH16rmm", LIEF::assembly::x86::OPCODE::PUSH16rmm) + .value("PUSH16rmr", LIEF::assembly::x86::OPCODE::PUSH16rmr) + .value("PUSH2", LIEF::assembly::x86::OPCODE::PUSH2) + .value("PUSH2P", LIEF::assembly::x86::OPCODE::PUSH2P) + .value("PUSH32i", LIEF::assembly::x86::OPCODE::PUSH32i) + .value("PUSH32i8", LIEF::assembly::x86::OPCODE::PUSH32i8) + .value("PUSH32r", LIEF::assembly::x86::OPCODE::PUSH32r) + .value("PUSH32rmm", LIEF::assembly::x86::OPCODE::PUSH32rmm) + .value("PUSH32rmr", LIEF::assembly::x86::OPCODE::PUSH32rmr) + .value("PUSH64i32", LIEF::assembly::x86::OPCODE::PUSH64i32) + .value("PUSH64i8", LIEF::assembly::x86::OPCODE::PUSH64i8) + .value("PUSH64r", LIEF::assembly::x86::OPCODE::PUSH64r) + .value("PUSH64rmm", LIEF::assembly::x86::OPCODE::PUSH64rmm) + .value("PUSH64rmr", LIEF::assembly::x86::OPCODE::PUSH64rmr) + .value("PUSHA16", LIEF::assembly::x86::OPCODE::PUSHA16) + .value("PUSHA32", LIEF::assembly::x86::OPCODE::PUSHA32) + .value("PUSHCS16", LIEF::assembly::x86::OPCODE::PUSHCS16) + .value("PUSHCS32", LIEF::assembly::x86::OPCODE::PUSHCS32) + .value("PUSHDS16", LIEF::assembly::x86::OPCODE::PUSHDS16) + .value("PUSHDS32", LIEF::assembly::x86::OPCODE::PUSHDS32) + .value("PUSHES16", LIEF::assembly::x86::OPCODE::PUSHES16) + .value("PUSHES32", LIEF::assembly::x86::OPCODE::PUSHES32) + .value("PUSHF16", LIEF::assembly::x86::OPCODE::PUSHF16) + .value("PUSHF32", LIEF::assembly::x86::OPCODE::PUSHF32) + .value("PUSHF64", LIEF::assembly::x86::OPCODE::PUSHF64) + .value("PUSHFS16", LIEF::assembly::x86::OPCODE::PUSHFS16) + .value("PUSHFS32", LIEF::assembly::x86::OPCODE::PUSHFS32) + .value("PUSHFS64", LIEF::assembly::x86::OPCODE::PUSHFS64) + .value("PUSHGS16", LIEF::assembly::x86::OPCODE::PUSHGS16) + .value("PUSHGS32", LIEF::assembly::x86::OPCODE::PUSHGS32) + .value("PUSHGS64", LIEF::assembly::x86::OPCODE::PUSHGS64) + .value("PUSHP64r", LIEF::assembly::x86::OPCODE::PUSHP64r) + .value("PUSHSS16", LIEF::assembly::x86::OPCODE::PUSHSS16) + .value("PUSHSS32", LIEF::assembly::x86::OPCODE::PUSHSS32) + .value("PVALIDATE32", LIEF::assembly::x86::OPCODE::PVALIDATE32) + .value("PVALIDATE64", LIEF::assembly::x86::OPCODE::PVALIDATE64) + .value("PXORrm", LIEF::assembly::x86::OPCODE::PXORrm) + .value("PXORrr", LIEF::assembly::x86::OPCODE::PXORrr) + .value("RCL16m1", LIEF::assembly::x86::OPCODE::RCL16m1) + .value("RCL16m1_EVEX", LIEF::assembly::x86::OPCODE::RCL16m1_EVEX) + .value("RCL16m1_ND", LIEF::assembly::x86::OPCODE::RCL16m1_ND) + .value("RCL16mCL", LIEF::assembly::x86::OPCODE::RCL16mCL) + .value("RCL16mCL_EVEX", LIEF::assembly::x86::OPCODE::RCL16mCL_EVEX) + .value("RCL16mCL_ND", LIEF::assembly::x86::OPCODE::RCL16mCL_ND) + .value("RCL16mi", LIEF::assembly::x86::OPCODE::RCL16mi) + .value("RCL16mi_EVEX", LIEF::assembly::x86::OPCODE::RCL16mi_EVEX) + .value("RCL16mi_ND", LIEF::assembly::x86::OPCODE::RCL16mi_ND) + .value("RCL16r1", LIEF::assembly::x86::OPCODE::RCL16r1) + .value("RCL16r1_EVEX", LIEF::assembly::x86::OPCODE::RCL16r1_EVEX) + .value("RCL16r1_ND", LIEF::assembly::x86::OPCODE::RCL16r1_ND) + .value("RCL16rCL", LIEF::assembly::x86::OPCODE::RCL16rCL) + .value("RCL16rCL_EVEX", LIEF::assembly::x86::OPCODE::RCL16rCL_EVEX) + .value("RCL16rCL_ND", LIEF::assembly::x86::OPCODE::RCL16rCL_ND) + .value("RCL16ri", LIEF::assembly::x86::OPCODE::RCL16ri) + .value("RCL16ri_EVEX", LIEF::assembly::x86::OPCODE::RCL16ri_EVEX) + .value("RCL16ri_ND", LIEF::assembly::x86::OPCODE::RCL16ri_ND) + .value("RCL32m1", LIEF::assembly::x86::OPCODE::RCL32m1) + .value("RCL32m1_EVEX", LIEF::assembly::x86::OPCODE::RCL32m1_EVEX) + .value("RCL32m1_ND", LIEF::assembly::x86::OPCODE::RCL32m1_ND) + .value("RCL32mCL", LIEF::assembly::x86::OPCODE::RCL32mCL) + .value("RCL32mCL_EVEX", LIEF::assembly::x86::OPCODE::RCL32mCL_EVEX) + .value("RCL32mCL_ND", LIEF::assembly::x86::OPCODE::RCL32mCL_ND) + .value("RCL32mi", LIEF::assembly::x86::OPCODE::RCL32mi) + .value("RCL32mi_EVEX", LIEF::assembly::x86::OPCODE::RCL32mi_EVEX) + .value("RCL32mi_ND", LIEF::assembly::x86::OPCODE::RCL32mi_ND) + .value("RCL32r1", LIEF::assembly::x86::OPCODE::RCL32r1) + .value("RCL32r1_EVEX", LIEF::assembly::x86::OPCODE::RCL32r1_EVEX) + .value("RCL32r1_ND", LIEF::assembly::x86::OPCODE::RCL32r1_ND) + .value("RCL32rCL", LIEF::assembly::x86::OPCODE::RCL32rCL) + .value("RCL32rCL_EVEX", LIEF::assembly::x86::OPCODE::RCL32rCL_EVEX) + .value("RCL32rCL_ND", LIEF::assembly::x86::OPCODE::RCL32rCL_ND) + .value("RCL32ri", LIEF::assembly::x86::OPCODE::RCL32ri) + .value("RCL32ri_EVEX", LIEF::assembly::x86::OPCODE::RCL32ri_EVEX) + .value("RCL32ri_ND", LIEF::assembly::x86::OPCODE::RCL32ri_ND) + .value("RCL64m1", LIEF::assembly::x86::OPCODE::RCL64m1) + .value("RCL64m1_EVEX", LIEF::assembly::x86::OPCODE::RCL64m1_EVEX) + .value("RCL64m1_ND", LIEF::assembly::x86::OPCODE::RCL64m1_ND) + .value("RCL64mCL", LIEF::assembly::x86::OPCODE::RCL64mCL) + .value("RCL64mCL_EVEX", LIEF::assembly::x86::OPCODE::RCL64mCL_EVEX) + .value("RCL64mCL_ND", LIEF::assembly::x86::OPCODE::RCL64mCL_ND) + .value("RCL64mi", LIEF::assembly::x86::OPCODE::RCL64mi) + .value("RCL64mi_EVEX", LIEF::assembly::x86::OPCODE::RCL64mi_EVEX) + .value("RCL64mi_ND", LIEF::assembly::x86::OPCODE::RCL64mi_ND) + .value("RCL64r1", LIEF::assembly::x86::OPCODE::RCL64r1) + .value("RCL64r1_EVEX", LIEF::assembly::x86::OPCODE::RCL64r1_EVEX) + .value("RCL64r1_ND", LIEF::assembly::x86::OPCODE::RCL64r1_ND) + .value("RCL64rCL", LIEF::assembly::x86::OPCODE::RCL64rCL) + .value("RCL64rCL_EVEX", LIEF::assembly::x86::OPCODE::RCL64rCL_EVEX) + .value("RCL64rCL_ND", LIEF::assembly::x86::OPCODE::RCL64rCL_ND) + .value("RCL64ri", LIEF::assembly::x86::OPCODE::RCL64ri) + .value("RCL64ri_EVEX", LIEF::assembly::x86::OPCODE::RCL64ri_EVEX) + .value("RCL64ri_ND", LIEF::assembly::x86::OPCODE::RCL64ri_ND) + .value("RCL8m1", LIEF::assembly::x86::OPCODE::RCL8m1) + .value("RCL8m1_EVEX", LIEF::assembly::x86::OPCODE::RCL8m1_EVEX) + .value("RCL8m1_ND", LIEF::assembly::x86::OPCODE::RCL8m1_ND) + .value("RCL8mCL", LIEF::assembly::x86::OPCODE::RCL8mCL); + opcodes.value("RCL8mCL_EVEX", LIEF::assembly::x86::OPCODE::RCL8mCL_EVEX) + .value("RCL8mCL_ND", LIEF::assembly::x86::OPCODE::RCL8mCL_ND) + .value("RCL8mi", LIEF::assembly::x86::OPCODE::RCL8mi) + .value("RCL8mi_EVEX", LIEF::assembly::x86::OPCODE::RCL8mi_EVEX) + .value("RCL8mi_ND", LIEF::assembly::x86::OPCODE::RCL8mi_ND) + .value("RCL8r1", LIEF::assembly::x86::OPCODE::RCL8r1) + .value("RCL8r1_EVEX", LIEF::assembly::x86::OPCODE::RCL8r1_EVEX) + .value("RCL8r1_ND", LIEF::assembly::x86::OPCODE::RCL8r1_ND) + .value("RCL8rCL", LIEF::assembly::x86::OPCODE::RCL8rCL) + .value("RCL8rCL_EVEX", LIEF::assembly::x86::OPCODE::RCL8rCL_EVEX) + .value("RCL8rCL_ND", LIEF::assembly::x86::OPCODE::RCL8rCL_ND) + .value("RCL8ri", LIEF::assembly::x86::OPCODE::RCL8ri) + .value("RCL8ri_EVEX", LIEF::assembly::x86::OPCODE::RCL8ri_EVEX) + .value("RCL8ri_ND", LIEF::assembly::x86::OPCODE::RCL8ri_ND) + .value("RCPPSm", LIEF::assembly::x86::OPCODE::RCPPSm) + .value("RCPPSr", LIEF::assembly::x86::OPCODE::RCPPSr) + .value("RCPSSm", LIEF::assembly::x86::OPCODE::RCPSSm) + .value("RCPSSm_Int", LIEF::assembly::x86::OPCODE::RCPSSm_Int) + .value("RCPSSr", LIEF::assembly::x86::OPCODE::RCPSSr) + .value("RCPSSr_Int", LIEF::assembly::x86::OPCODE::RCPSSr_Int) + .value("RCR16m1", LIEF::assembly::x86::OPCODE::RCR16m1) + .value("RCR16m1_EVEX", LIEF::assembly::x86::OPCODE::RCR16m1_EVEX) + .value("RCR16m1_ND", LIEF::assembly::x86::OPCODE::RCR16m1_ND) + .value("RCR16mCL", LIEF::assembly::x86::OPCODE::RCR16mCL) + .value("RCR16mCL_EVEX", LIEF::assembly::x86::OPCODE::RCR16mCL_EVEX) + .value("RCR16mCL_ND", LIEF::assembly::x86::OPCODE::RCR16mCL_ND) + .value("RCR16mi", LIEF::assembly::x86::OPCODE::RCR16mi) + .value("RCR16mi_EVEX", LIEF::assembly::x86::OPCODE::RCR16mi_EVEX) + .value("RCR16mi_ND", LIEF::assembly::x86::OPCODE::RCR16mi_ND) + .value("RCR16r1", LIEF::assembly::x86::OPCODE::RCR16r1) + .value("RCR16r1_EVEX", LIEF::assembly::x86::OPCODE::RCR16r1_EVEX) + .value("RCR16r1_ND", LIEF::assembly::x86::OPCODE::RCR16r1_ND) + .value("RCR16rCL", LIEF::assembly::x86::OPCODE::RCR16rCL) + .value("RCR16rCL_EVEX", LIEF::assembly::x86::OPCODE::RCR16rCL_EVEX) + .value("RCR16rCL_ND", LIEF::assembly::x86::OPCODE::RCR16rCL_ND) + .value("RCR16ri", LIEF::assembly::x86::OPCODE::RCR16ri) + .value("RCR16ri_EVEX", LIEF::assembly::x86::OPCODE::RCR16ri_EVEX) + .value("RCR16ri_ND", LIEF::assembly::x86::OPCODE::RCR16ri_ND) + .value("RCR32m1", LIEF::assembly::x86::OPCODE::RCR32m1) + .value("RCR32m1_EVEX", LIEF::assembly::x86::OPCODE::RCR32m1_EVEX) + .value("RCR32m1_ND", LIEF::assembly::x86::OPCODE::RCR32m1_ND) + .value("RCR32mCL", LIEF::assembly::x86::OPCODE::RCR32mCL) + .value("RCR32mCL_EVEX", LIEF::assembly::x86::OPCODE::RCR32mCL_EVEX) + .value("RCR32mCL_ND", LIEF::assembly::x86::OPCODE::RCR32mCL_ND) + .value("RCR32mi", LIEF::assembly::x86::OPCODE::RCR32mi) + .value("RCR32mi_EVEX", LIEF::assembly::x86::OPCODE::RCR32mi_EVEX) + .value("RCR32mi_ND", LIEF::assembly::x86::OPCODE::RCR32mi_ND) + .value("RCR32r1", LIEF::assembly::x86::OPCODE::RCR32r1) + .value("RCR32r1_EVEX", LIEF::assembly::x86::OPCODE::RCR32r1_EVEX) + .value("RCR32r1_ND", LIEF::assembly::x86::OPCODE::RCR32r1_ND) + .value("RCR32rCL", LIEF::assembly::x86::OPCODE::RCR32rCL) + .value("RCR32rCL_EVEX", LIEF::assembly::x86::OPCODE::RCR32rCL_EVEX) + .value("RCR32rCL_ND", LIEF::assembly::x86::OPCODE::RCR32rCL_ND) + .value("RCR32ri", LIEF::assembly::x86::OPCODE::RCR32ri) + .value("RCR32ri_EVEX", LIEF::assembly::x86::OPCODE::RCR32ri_EVEX) + .value("RCR32ri_ND", LIEF::assembly::x86::OPCODE::RCR32ri_ND) + .value("RCR64m1", LIEF::assembly::x86::OPCODE::RCR64m1) + .value("RCR64m1_EVEX", LIEF::assembly::x86::OPCODE::RCR64m1_EVEX) + .value("RCR64m1_ND", LIEF::assembly::x86::OPCODE::RCR64m1_ND) + .value("RCR64mCL", LIEF::assembly::x86::OPCODE::RCR64mCL) + .value("RCR64mCL_EVEX", LIEF::assembly::x86::OPCODE::RCR64mCL_EVEX) + .value("RCR64mCL_ND", LIEF::assembly::x86::OPCODE::RCR64mCL_ND) + .value("RCR64mi", LIEF::assembly::x86::OPCODE::RCR64mi) + .value("RCR64mi_EVEX", LIEF::assembly::x86::OPCODE::RCR64mi_EVEX) + .value("RCR64mi_ND", LIEF::assembly::x86::OPCODE::RCR64mi_ND) + .value("RCR64r1", LIEF::assembly::x86::OPCODE::RCR64r1) + .value("RCR64r1_EVEX", LIEF::assembly::x86::OPCODE::RCR64r1_EVEX) + .value("RCR64r1_ND", LIEF::assembly::x86::OPCODE::RCR64r1_ND) + .value("RCR64rCL", LIEF::assembly::x86::OPCODE::RCR64rCL) + .value("RCR64rCL_EVEX", LIEF::assembly::x86::OPCODE::RCR64rCL_EVEX) + .value("RCR64rCL_ND", LIEF::assembly::x86::OPCODE::RCR64rCL_ND) + .value("RCR64ri", LIEF::assembly::x86::OPCODE::RCR64ri) + .value("RCR64ri_EVEX", LIEF::assembly::x86::OPCODE::RCR64ri_EVEX) + .value("RCR64ri_ND", LIEF::assembly::x86::OPCODE::RCR64ri_ND) + .value("RCR8m1", LIEF::assembly::x86::OPCODE::RCR8m1) + .value("RCR8m1_EVEX", LIEF::assembly::x86::OPCODE::RCR8m1_EVEX) + .value("RCR8m1_ND", LIEF::assembly::x86::OPCODE::RCR8m1_ND) + .value("RCR8mCL", LIEF::assembly::x86::OPCODE::RCR8mCL) + .value("RCR8mCL_EVEX", LIEF::assembly::x86::OPCODE::RCR8mCL_EVEX) + .value("RCR8mCL_ND", LIEF::assembly::x86::OPCODE::RCR8mCL_ND) + .value("RCR8mi", LIEF::assembly::x86::OPCODE::RCR8mi) + .value("RCR8mi_EVEX", LIEF::assembly::x86::OPCODE::RCR8mi_EVEX) + .value("RCR8mi_ND", LIEF::assembly::x86::OPCODE::RCR8mi_ND) + .value("RCR8r1", LIEF::assembly::x86::OPCODE::RCR8r1) + .value("RCR8r1_EVEX", LIEF::assembly::x86::OPCODE::RCR8r1_EVEX) + .value("RCR8r1_ND", LIEF::assembly::x86::OPCODE::RCR8r1_ND) + .value("RCR8rCL", LIEF::assembly::x86::OPCODE::RCR8rCL) + .value("RCR8rCL_EVEX", LIEF::assembly::x86::OPCODE::RCR8rCL_EVEX) + .value("RCR8rCL_ND", LIEF::assembly::x86::OPCODE::RCR8rCL_ND) + .value("RCR8ri", LIEF::assembly::x86::OPCODE::RCR8ri) + .value("RCR8ri_EVEX", LIEF::assembly::x86::OPCODE::RCR8ri_EVEX) + .value("RCR8ri_ND", LIEF::assembly::x86::OPCODE::RCR8ri_ND) + .value("RDFSBASE", LIEF::assembly::x86::OPCODE::RDFSBASE) + .value("RDFSBASE64", LIEF::assembly::x86::OPCODE::RDFSBASE64) + .value("RDGSBASE", LIEF::assembly::x86::OPCODE::RDGSBASE) + .value("RDGSBASE64", LIEF::assembly::x86::OPCODE::RDGSBASE64) + .value("RDMSR", LIEF::assembly::x86::OPCODE::RDMSR) + .value("RDMSRLIST", LIEF::assembly::x86::OPCODE::RDMSRLIST) + .value("RDMSRri", LIEF::assembly::x86::OPCODE::RDMSRri) + .value("RDMSRri_EVEX", LIEF::assembly::x86::OPCODE::RDMSRri_EVEX) + .value("RDPID32", LIEF::assembly::x86::OPCODE::RDPID32) + .value("RDPID64", LIEF::assembly::x86::OPCODE::RDPID64) + .value("RDPKRUr", LIEF::assembly::x86::OPCODE::RDPKRUr) + .value("RDPMC", LIEF::assembly::x86::OPCODE::RDPMC) + .value("RDPRU", LIEF::assembly::x86::OPCODE::RDPRU) + .value("RDRAND16r", LIEF::assembly::x86::OPCODE::RDRAND16r) + .value("RDRAND32r", LIEF::assembly::x86::OPCODE::RDRAND32r) + .value("RDRAND64r", LIEF::assembly::x86::OPCODE::RDRAND64r) + .value("RDSEED16r", LIEF::assembly::x86::OPCODE::RDSEED16r) + .value("RDSEED32r", LIEF::assembly::x86::OPCODE::RDSEED32r) + .value("RDSEED64r", LIEF::assembly::x86::OPCODE::RDSEED64r) + .value("RDSSPD", LIEF::assembly::x86::OPCODE::RDSSPD) + .value("RDSSPQ", LIEF::assembly::x86::OPCODE::RDSSPQ) + .value("RDTSC", LIEF::assembly::x86::OPCODE::RDTSC) + .value("RDTSCP", LIEF::assembly::x86::OPCODE::RDTSCP) + .value("REPNE_PREFIX", LIEF::assembly::x86::OPCODE::REPNE_PREFIX) + .value("REP_MOVSB_32", LIEF::assembly::x86::OPCODE::REP_MOVSB_32) + .value("REP_MOVSB_64", LIEF::assembly::x86::OPCODE::REP_MOVSB_64) + .value("REP_MOVSD_32", LIEF::assembly::x86::OPCODE::REP_MOVSD_32) + .value("REP_MOVSD_64", LIEF::assembly::x86::OPCODE::REP_MOVSD_64) + .value("REP_MOVSQ_32", LIEF::assembly::x86::OPCODE::REP_MOVSQ_32) + .value("REP_MOVSQ_64", LIEF::assembly::x86::OPCODE::REP_MOVSQ_64) + .value("REP_MOVSW_32", LIEF::assembly::x86::OPCODE::REP_MOVSW_32) + .value("REP_MOVSW_64", LIEF::assembly::x86::OPCODE::REP_MOVSW_64) + .value("REP_PREFIX", LIEF::assembly::x86::OPCODE::REP_PREFIX) + .value("REP_STOSB_32", LIEF::assembly::x86::OPCODE::REP_STOSB_32) + .value("REP_STOSB_64", LIEF::assembly::x86::OPCODE::REP_STOSB_64) + .value("REP_STOSD_32", LIEF::assembly::x86::OPCODE::REP_STOSD_32) + .value("REP_STOSD_64", LIEF::assembly::x86::OPCODE::REP_STOSD_64) + .value("REP_STOSQ_32", LIEF::assembly::x86::OPCODE::REP_STOSQ_32) + .value("REP_STOSQ_64", LIEF::assembly::x86::OPCODE::REP_STOSQ_64) + .value("REP_STOSW_32", LIEF::assembly::x86::OPCODE::REP_STOSW_32) + .value("REP_STOSW_64", LIEF::assembly::x86::OPCODE::REP_STOSW_64) + .value("RET", LIEF::assembly::x86::OPCODE::RET) + .value("RET16", LIEF::assembly::x86::OPCODE::RET16) + .value("RET32", LIEF::assembly::x86::OPCODE::RET32) + .value("RET64", LIEF::assembly::x86::OPCODE::RET64) + .value("RETI16", LIEF::assembly::x86::OPCODE::RETI16) + .value("RETI32", LIEF::assembly::x86::OPCODE::RETI32) + .value("RETI64", LIEF::assembly::x86::OPCODE::RETI64) + .value("REX64_PREFIX", LIEF::assembly::x86::OPCODE::REX64_PREFIX) + .value("RMPADJUST", LIEF::assembly::x86::OPCODE::RMPADJUST) + .value("RMPQUERY", LIEF::assembly::x86::OPCODE::RMPQUERY) + .value("RMPUPDATE", LIEF::assembly::x86::OPCODE::RMPUPDATE) + .value("ROL16m1", LIEF::assembly::x86::OPCODE::ROL16m1) + .value("ROL16m1_EVEX", LIEF::assembly::x86::OPCODE::ROL16m1_EVEX) + .value("ROL16m1_ND", LIEF::assembly::x86::OPCODE::ROL16m1_ND) + .value("ROL16m1_NF", LIEF::assembly::x86::OPCODE::ROL16m1_NF) + .value("ROL16m1_NF_ND", LIEF::assembly::x86::OPCODE::ROL16m1_NF_ND) + .value("ROL16mCL", LIEF::assembly::x86::OPCODE::ROL16mCL) + .value("ROL16mCL_EVEX", LIEF::assembly::x86::OPCODE::ROL16mCL_EVEX) + .value("ROL16mCL_ND", LIEF::assembly::x86::OPCODE::ROL16mCL_ND) + .value("ROL16mCL_NF", LIEF::assembly::x86::OPCODE::ROL16mCL_NF) + .value("ROL16mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL16mCL_NF_ND) + .value("ROL16mi", LIEF::assembly::x86::OPCODE::ROL16mi) + .value("ROL16mi_EVEX", LIEF::assembly::x86::OPCODE::ROL16mi_EVEX) + .value("ROL16mi_ND", LIEF::assembly::x86::OPCODE::ROL16mi_ND) + .value("ROL16mi_NF", LIEF::assembly::x86::OPCODE::ROL16mi_NF) + .value("ROL16mi_NF_ND", LIEF::assembly::x86::OPCODE::ROL16mi_NF_ND) + .value("ROL16r1", LIEF::assembly::x86::OPCODE::ROL16r1) + .value("ROL16r1_EVEX", LIEF::assembly::x86::OPCODE::ROL16r1_EVEX) + .value("ROL16r1_ND", LIEF::assembly::x86::OPCODE::ROL16r1_ND) + .value("ROL16r1_NF", LIEF::assembly::x86::OPCODE::ROL16r1_NF) + .value("ROL16r1_NF_ND", LIEF::assembly::x86::OPCODE::ROL16r1_NF_ND) + .value("ROL16rCL", LIEF::assembly::x86::OPCODE::ROL16rCL) + .value("ROL16rCL_EVEX", LIEF::assembly::x86::OPCODE::ROL16rCL_EVEX) + .value("ROL16rCL_ND", LIEF::assembly::x86::OPCODE::ROL16rCL_ND) + .value("ROL16rCL_NF", LIEF::assembly::x86::OPCODE::ROL16rCL_NF) + .value("ROL16rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL16rCL_NF_ND) + .value("ROL16ri", LIEF::assembly::x86::OPCODE::ROL16ri) + .value("ROL16ri_EVEX", LIEF::assembly::x86::OPCODE::ROL16ri_EVEX) + .value("ROL16ri_ND", LIEF::assembly::x86::OPCODE::ROL16ri_ND) + .value("ROL16ri_NF", LIEF::assembly::x86::OPCODE::ROL16ri_NF) + .value("ROL16ri_NF_ND", LIEF::assembly::x86::OPCODE::ROL16ri_NF_ND) + .value("ROL32m1", LIEF::assembly::x86::OPCODE::ROL32m1) + .value("ROL32m1_EVEX", LIEF::assembly::x86::OPCODE::ROL32m1_EVEX) + .value("ROL32m1_ND", LIEF::assembly::x86::OPCODE::ROL32m1_ND) + .value("ROL32m1_NF", LIEF::assembly::x86::OPCODE::ROL32m1_NF) + .value("ROL32m1_NF_ND", LIEF::assembly::x86::OPCODE::ROL32m1_NF_ND) + .value("ROL32mCL", LIEF::assembly::x86::OPCODE::ROL32mCL) + .value("ROL32mCL_EVEX", LIEF::assembly::x86::OPCODE::ROL32mCL_EVEX) + .value("ROL32mCL_ND", LIEF::assembly::x86::OPCODE::ROL32mCL_ND) + .value("ROL32mCL_NF", LIEF::assembly::x86::OPCODE::ROL32mCL_NF) + .value("ROL32mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL32mCL_NF_ND) + .value("ROL32mi", LIEF::assembly::x86::OPCODE::ROL32mi) + .value("ROL32mi_EVEX", LIEF::assembly::x86::OPCODE::ROL32mi_EVEX) + .value("ROL32mi_ND", LIEF::assembly::x86::OPCODE::ROL32mi_ND) + .value("ROL32mi_NF", LIEF::assembly::x86::OPCODE::ROL32mi_NF) + .value("ROL32mi_NF_ND", LIEF::assembly::x86::OPCODE::ROL32mi_NF_ND) + .value("ROL32r1", LIEF::assembly::x86::OPCODE::ROL32r1) + .value("ROL32r1_EVEX", LIEF::assembly::x86::OPCODE::ROL32r1_EVEX) + .value("ROL32r1_ND", LIEF::assembly::x86::OPCODE::ROL32r1_ND) + .value("ROL32r1_NF", LIEF::assembly::x86::OPCODE::ROL32r1_NF) + .value("ROL32r1_NF_ND", LIEF::assembly::x86::OPCODE::ROL32r1_NF_ND) + .value("ROL32rCL", LIEF::assembly::x86::OPCODE::ROL32rCL) + .value("ROL32rCL_EVEX", LIEF::assembly::x86::OPCODE::ROL32rCL_EVEX) + .value("ROL32rCL_ND", LIEF::assembly::x86::OPCODE::ROL32rCL_ND) + .value("ROL32rCL_NF", LIEF::assembly::x86::OPCODE::ROL32rCL_NF) + .value("ROL32rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL32rCL_NF_ND) + .value("ROL32ri", LIEF::assembly::x86::OPCODE::ROL32ri) + .value("ROL32ri_EVEX", LIEF::assembly::x86::OPCODE::ROL32ri_EVEX) + .value("ROL32ri_ND", LIEF::assembly::x86::OPCODE::ROL32ri_ND) + .value("ROL32ri_NF", LIEF::assembly::x86::OPCODE::ROL32ri_NF) + .value("ROL32ri_NF_ND", LIEF::assembly::x86::OPCODE::ROL32ri_NF_ND) + .value("ROL64m1", LIEF::assembly::x86::OPCODE::ROL64m1) + .value("ROL64m1_EVEX", LIEF::assembly::x86::OPCODE::ROL64m1_EVEX) + .value("ROL64m1_ND", LIEF::assembly::x86::OPCODE::ROL64m1_ND) + .value("ROL64m1_NF", LIEF::assembly::x86::OPCODE::ROL64m1_NF) + .value("ROL64m1_NF_ND", LIEF::assembly::x86::OPCODE::ROL64m1_NF_ND) + .value("ROL64mCL", LIEF::assembly::x86::OPCODE::ROL64mCL) + .value("ROL64mCL_EVEX", LIEF::assembly::x86::OPCODE::ROL64mCL_EVEX) + .value("ROL64mCL_ND", LIEF::assembly::x86::OPCODE::ROL64mCL_ND) + .value("ROL64mCL_NF", LIEF::assembly::x86::OPCODE::ROL64mCL_NF) + .value("ROL64mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL64mCL_NF_ND) + .value("ROL64mi", LIEF::assembly::x86::OPCODE::ROL64mi) + .value("ROL64mi_EVEX", LIEF::assembly::x86::OPCODE::ROL64mi_EVEX) + .value("ROL64mi_ND", LIEF::assembly::x86::OPCODE::ROL64mi_ND) + .value("ROL64mi_NF", LIEF::assembly::x86::OPCODE::ROL64mi_NF) + .value("ROL64mi_NF_ND", LIEF::assembly::x86::OPCODE::ROL64mi_NF_ND) + .value("ROL64r1", LIEF::assembly::x86::OPCODE::ROL64r1) + .value("ROL64r1_EVEX", LIEF::assembly::x86::OPCODE::ROL64r1_EVEX) + .value("ROL64r1_ND", LIEF::assembly::x86::OPCODE::ROL64r1_ND) + .value("ROL64r1_NF", LIEF::assembly::x86::OPCODE::ROL64r1_NF) + .value("ROL64r1_NF_ND", LIEF::assembly::x86::OPCODE::ROL64r1_NF_ND) + .value("ROL64rCL", LIEF::assembly::x86::OPCODE::ROL64rCL) + .value("ROL64rCL_EVEX", LIEF::assembly::x86::OPCODE::ROL64rCL_EVEX) + .value("ROL64rCL_ND", LIEF::assembly::x86::OPCODE::ROL64rCL_ND) + .value("ROL64rCL_NF", LIEF::assembly::x86::OPCODE::ROL64rCL_NF) + .value("ROL64rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL64rCL_NF_ND) + .value("ROL64ri", LIEF::assembly::x86::OPCODE::ROL64ri) + .value("ROL64ri_EVEX", LIEF::assembly::x86::OPCODE::ROL64ri_EVEX) + .value("ROL64ri_ND", LIEF::assembly::x86::OPCODE::ROL64ri_ND) + .value("ROL64ri_NF", LIEF::assembly::x86::OPCODE::ROL64ri_NF) + .value("ROL64ri_NF_ND", LIEF::assembly::x86::OPCODE::ROL64ri_NF_ND) + .value("ROL8m1", LIEF::assembly::x86::OPCODE::ROL8m1) + .value("ROL8m1_EVEX", LIEF::assembly::x86::OPCODE::ROL8m1_EVEX) + .value("ROL8m1_ND", LIEF::assembly::x86::OPCODE::ROL8m1_ND) + .value("ROL8m1_NF", LIEF::assembly::x86::OPCODE::ROL8m1_NF) + .value("ROL8m1_NF_ND", LIEF::assembly::x86::OPCODE::ROL8m1_NF_ND) + .value("ROL8mCL", LIEF::assembly::x86::OPCODE::ROL8mCL) + .value("ROL8mCL_EVEX", LIEF::assembly::x86::OPCODE::ROL8mCL_EVEX) + .value("ROL8mCL_ND", LIEF::assembly::x86::OPCODE::ROL8mCL_ND) + .value("ROL8mCL_NF", LIEF::assembly::x86::OPCODE::ROL8mCL_NF) + .value("ROL8mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL8mCL_NF_ND) + .value("ROL8mi", LIEF::assembly::x86::OPCODE::ROL8mi) + .value("ROL8mi_EVEX", LIEF::assembly::x86::OPCODE::ROL8mi_EVEX) + .value("ROL8mi_ND", LIEF::assembly::x86::OPCODE::ROL8mi_ND) + .value("ROL8mi_NF", LIEF::assembly::x86::OPCODE::ROL8mi_NF) + .value("ROL8mi_NF_ND", LIEF::assembly::x86::OPCODE::ROL8mi_NF_ND) + .value("ROL8r1", LIEF::assembly::x86::OPCODE::ROL8r1) + .value("ROL8r1_EVEX", LIEF::assembly::x86::OPCODE::ROL8r1_EVEX) + .value("ROL8r1_ND", LIEF::assembly::x86::OPCODE::ROL8r1_ND) + .value("ROL8r1_NF", LIEF::assembly::x86::OPCODE::ROL8r1_NF) + .value("ROL8r1_NF_ND", LIEF::assembly::x86::OPCODE::ROL8r1_NF_ND) + .value("ROL8rCL", LIEF::assembly::x86::OPCODE::ROL8rCL) + .value("ROL8rCL_EVEX", LIEF::assembly::x86::OPCODE::ROL8rCL_EVEX) + .value("ROL8rCL_ND", LIEF::assembly::x86::OPCODE::ROL8rCL_ND) + .value("ROL8rCL_NF", LIEF::assembly::x86::OPCODE::ROL8rCL_NF) + .value("ROL8rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROL8rCL_NF_ND) + .value("ROL8ri", LIEF::assembly::x86::OPCODE::ROL8ri) + .value("ROL8ri_EVEX", LIEF::assembly::x86::OPCODE::ROL8ri_EVEX) + .value("ROL8ri_ND", LIEF::assembly::x86::OPCODE::ROL8ri_ND) + .value("ROL8ri_NF", LIEF::assembly::x86::OPCODE::ROL8ri_NF) + .value("ROL8ri_NF_ND", LIEF::assembly::x86::OPCODE::ROL8ri_NF_ND) + .value("ROR16m1", LIEF::assembly::x86::OPCODE::ROR16m1) + .value("ROR16m1_EVEX", LIEF::assembly::x86::OPCODE::ROR16m1_EVEX) + .value("ROR16m1_ND", LIEF::assembly::x86::OPCODE::ROR16m1_ND) + .value("ROR16m1_NF", LIEF::assembly::x86::OPCODE::ROR16m1_NF) + .value("ROR16m1_NF_ND", LIEF::assembly::x86::OPCODE::ROR16m1_NF_ND) + .value("ROR16mCL", LIEF::assembly::x86::OPCODE::ROR16mCL) + .value("ROR16mCL_EVEX", LIEF::assembly::x86::OPCODE::ROR16mCL_EVEX) + .value("ROR16mCL_ND", LIEF::assembly::x86::OPCODE::ROR16mCL_ND) + .value("ROR16mCL_NF", LIEF::assembly::x86::OPCODE::ROR16mCL_NF) + .value("ROR16mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR16mCL_NF_ND) + .value("ROR16mi", LIEF::assembly::x86::OPCODE::ROR16mi) + .value("ROR16mi_EVEX", LIEF::assembly::x86::OPCODE::ROR16mi_EVEX) + .value("ROR16mi_ND", LIEF::assembly::x86::OPCODE::ROR16mi_ND) + .value("ROR16mi_NF", LIEF::assembly::x86::OPCODE::ROR16mi_NF) + .value("ROR16mi_NF_ND", LIEF::assembly::x86::OPCODE::ROR16mi_NF_ND) + .value("ROR16r1", LIEF::assembly::x86::OPCODE::ROR16r1) + .value("ROR16r1_EVEX", LIEF::assembly::x86::OPCODE::ROR16r1_EVEX) + .value("ROR16r1_ND", LIEF::assembly::x86::OPCODE::ROR16r1_ND) + .value("ROR16r1_NF", LIEF::assembly::x86::OPCODE::ROR16r1_NF) + .value("ROR16r1_NF_ND", LIEF::assembly::x86::OPCODE::ROR16r1_NF_ND) + .value("ROR16rCL", LIEF::assembly::x86::OPCODE::ROR16rCL) + .value("ROR16rCL_EVEX", LIEF::assembly::x86::OPCODE::ROR16rCL_EVEX) + .value("ROR16rCL_ND", LIEF::assembly::x86::OPCODE::ROR16rCL_ND) + .value("ROR16rCL_NF", LIEF::assembly::x86::OPCODE::ROR16rCL_NF) + .value("ROR16rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR16rCL_NF_ND) + .value("ROR16ri", LIEF::assembly::x86::OPCODE::ROR16ri) + .value("ROR16ri_EVEX", LIEF::assembly::x86::OPCODE::ROR16ri_EVEX) + .value("ROR16ri_ND", LIEF::assembly::x86::OPCODE::ROR16ri_ND) + .value("ROR16ri_NF", LIEF::assembly::x86::OPCODE::ROR16ri_NF) + .value("ROR16ri_NF_ND", LIEF::assembly::x86::OPCODE::ROR16ri_NF_ND) + .value("ROR32m1", LIEF::assembly::x86::OPCODE::ROR32m1) + .value("ROR32m1_EVEX", LIEF::assembly::x86::OPCODE::ROR32m1_EVEX) + .value("ROR32m1_ND", LIEF::assembly::x86::OPCODE::ROR32m1_ND) + .value("ROR32m1_NF", LIEF::assembly::x86::OPCODE::ROR32m1_NF) + .value("ROR32m1_NF_ND", LIEF::assembly::x86::OPCODE::ROR32m1_NF_ND) + .value("ROR32mCL", LIEF::assembly::x86::OPCODE::ROR32mCL); + opcodes.value("ROR32mCL_EVEX", LIEF::assembly::x86::OPCODE::ROR32mCL_EVEX) + .value("ROR32mCL_ND", LIEF::assembly::x86::OPCODE::ROR32mCL_ND) + .value("ROR32mCL_NF", LIEF::assembly::x86::OPCODE::ROR32mCL_NF) + .value("ROR32mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR32mCL_NF_ND) + .value("ROR32mi", LIEF::assembly::x86::OPCODE::ROR32mi) + .value("ROR32mi_EVEX", LIEF::assembly::x86::OPCODE::ROR32mi_EVEX) + .value("ROR32mi_ND", LIEF::assembly::x86::OPCODE::ROR32mi_ND) + .value("ROR32mi_NF", LIEF::assembly::x86::OPCODE::ROR32mi_NF) + .value("ROR32mi_NF_ND", LIEF::assembly::x86::OPCODE::ROR32mi_NF_ND) + .value("ROR32r1", LIEF::assembly::x86::OPCODE::ROR32r1) + .value("ROR32r1_EVEX", LIEF::assembly::x86::OPCODE::ROR32r1_EVEX) + .value("ROR32r1_ND", LIEF::assembly::x86::OPCODE::ROR32r1_ND) + .value("ROR32r1_NF", LIEF::assembly::x86::OPCODE::ROR32r1_NF) + .value("ROR32r1_NF_ND", LIEF::assembly::x86::OPCODE::ROR32r1_NF_ND) + .value("ROR32rCL", LIEF::assembly::x86::OPCODE::ROR32rCL) + .value("ROR32rCL_EVEX", LIEF::assembly::x86::OPCODE::ROR32rCL_EVEX) + .value("ROR32rCL_ND", LIEF::assembly::x86::OPCODE::ROR32rCL_ND) + .value("ROR32rCL_NF", LIEF::assembly::x86::OPCODE::ROR32rCL_NF) + .value("ROR32rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR32rCL_NF_ND) + .value("ROR32ri", LIEF::assembly::x86::OPCODE::ROR32ri) + .value("ROR32ri_EVEX", LIEF::assembly::x86::OPCODE::ROR32ri_EVEX) + .value("ROR32ri_ND", LIEF::assembly::x86::OPCODE::ROR32ri_ND) + .value("ROR32ri_NF", LIEF::assembly::x86::OPCODE::ROR32ri_NF) + .value("ROR32ri_NF_ND", LIEF::assembly::x86::OPCODE::ROR32ri_NF_ND) + .value("ROR64m1", LIEF::assembly::x86::OPCODE::ROR64m1) + .value("ROR64m1_EVEX", LIEF::assembly::x86::OPCODE::ROR64m1_EVEX) + .value("ROR64m1_ND", LIEF::assembly::x86::OPCODE::ROR64m1_ND) + .value("ROR64m1_NF", LIEF::assembly::x86::OPCODE::ROR64m1_NF) + .value("ROR64m1_NF_ND", LIEF::assembly::x86::OPCODE::ROR64m1_NF_ND) + .value("ROR64mCL", LIEF::assembly::x86::OPCODE::ROR64mCL) + .value("ROR64mCL_EVEX", LIEF::assembly::x86::OPCODE::ROR64mCL_EVEX) + .value("ROR64mCL_ND", LIEF::assembly::x86::OPCODE::ROR64mCL_ND) + .value("ROR64mCL_NF", LIEF::assembly::x86::OPCODE::ROR64mCL_NF) + .value("ROR64mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR64mCL_NF_ND) + .value("ROR64mi", LIEF::assembly::x86::OPCODE::ROR64mi) + .value("ROR64mi_EVEX", LIEF::assembly::x86::OPCODE::ROR64mi_EVEX) + .value("ROR64mi_ND", LIEF::assembly::x86::OPCODE::ROR64mi_ND) + .value("ROR64mi_NF", LIEF::assembly::x86::OPCODE::ROR64mi_NF) + .value("ROR64mi_NF_ND", LIEF::assembly::x86::OPCODE::ROR64mi_NF_ND) + .value("ROR64r1", LIEF::assembly::x86::OPCODE::ROR64r1) + .value("ROR64r1_EVEX", LIEF::assembly::x86::OPCODE::ROR64r1_EVEX) + .value("ROR64r1_ND", LIEF::assembly::x86::OPCODE::ROR64r1_ND) + .value("ROR64r1_NF", LIEF::assembly::x86::OPCODE::ROR64r1_NF) + .value("ROR64r1_NF_ND", LIEF::assembly::x86::OPCODE::ROR64r1_NF_ND) + .value("ROR64rCL", LIEF::assembly::x86::OPCODE::ROR64rCL) + .value("ROR64rCL_EVEX", LIEF::assembly::x86::OPCODE::ROR64rCL_EVEX) + .value("ROR64rCL_ND", LIEF::assembly::x86::OPCODE::ROR64rCL_ND) + .value("ROR64rCL_NF", LIEF::assembly::x86::OPCODE::ROR64rCL_NF) + .value("ROR64rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR64rCL_NF_ND) + .value("ROR64ri", LIEF::assembly::x86::OPCODE::ROR64ri) + .value("ROR64ri_EVEX", LIEF::assembly::x86::OPCODE::ROR64ri_EVEX) + .value("ROR64ri_ND", LIEF::assembly::x86::OPCODE::ROR64ri_ND) + .value("ROR64ri_NF", LIEF::assembly::x86::OPCODE::ROR64ri_NF) + .value("ROR64ri_NF_ND", LIEF::assembly::x86::OPCODE::ROR64ri_NF_ND) + .value("ROR8m1", LIEF::assembly::x86::OPCODE::ROR8m1) + .value("ROR8m1_EVEX", LIEF::assembly::x86::OPCODE::ROR8m1_EVEX) + .value("ROR8m1_ND", LIEF::assembly::x86::OPCODE::ROR8m1_ND) + .value("ROR8m1_NF", LIEF::assembly::x86::OPCODE::ROR8m1_NF) + .value("ROR8m1_NF_ND", LIEF::assembly::x86::OPCODE::ROR8m1_NF_ND) + .value("ROR8mCL", LIEF::assembly::x86::OPCODE::ROR8mCL) + .value("ROR8mCL_EVEX", LIEF::assembly::x86::OPCODE::ROR8mCL_EVEX) + .value("ROR8mCL_ND", LIEF::assembly::x86::OPCODE::ROR8mCL_ND) + .value("ROR8mCL_NF", LIEF::assembly::x86::OPCODE::ROR8mCL_NF) + .value("ROR8mCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR8mCL_NF_ND) + .value("ROR8mi", LIEF::assembly::x86::OPCODE::ROR8mi) + .value("ROR8mi_EVEX", LIEF::assembly::x86::OPCODE::ROR8mi_EVEX) + .value("ROR8mi_ND", LIEF::assembly::x86::OPCODE::ROR8mi_ND) + .value("ROR8mi_NF", LIEF::assembly::x86::OPCODE::ROR8mi_NF) + .value("ROR8mi_NF_ND", LIEF::assembly::x86::OPCODE::ROR8mi_NF_ND) + .value("ROR8r1", LIEF::assembly::x86::OPCODE::ROR8r1) + .value("ROR8r1_EVEX", LIEF::assembly::x86::OPCODE::ROR8r1_EVEX) + .value("ROR8r1_ND", LIEF::assembly::x86::OPCODE::ROR8r1_ND) + .value("ROR8r1_NF", LIEF::assembly::x86::OPCODE::ROR8r1_NF) + .value("ROR8r1_NF_ND", LIEF::assembly::x86::OPCODE::ROR8r1_NF_ND) + .value("ROR8rCL", LIEF::assembly::x86::OPCODE::ROR8rCL) + .value("ROR8rCL_EVEX", LIEF::assembly::x86::OPCODE::ROR8rCL_EVEX) + .value("ROR8rCL_ND", LIEF::assembly::x86::OPCODE::ROR8rCL_ND) + .value("ROR8rCL_NF", LIEF::assembly::x86::OPCODE::ROR8rCL_NF) + .value("ROR8rCL_NF_ND", LIEF::assembly::x86::OPCODE::ROR8rCL_NF_ND) + .value("ROR8ri", LIEF::assembly::x86::OPCODE::ROR8ri) + .value("ROR8ri_EVEX", LIEF::assembly::x86::OPCODE::ROR8ri_EVEX) + .value("ROR8ri_ND", LIEF::assembly::x86::OPCODE::ROR8ri_ND) + .value("ROR8ri_NF", LIEF::assembly::x86::OPCODE::ROR8ri_NF) + .value("ROR8ri_NF_ND", LIEF::assembly::x86::OPCODE::ROR8ri_NF_ND) + .value("RORX32mi", LIEF::assembly::x86::OPCODE::RORX32mi) + .value("RORX32mi_EVEX", LIEF::assembly::x86::OPCODE::RORX32mi_EVEX) + .value("RORX32ri", LIEF::assembly::x86::OPCODE::RORX32ri) + .value("RORX32ri_EVEX", LIEF::assembly::x86::OPCODE::RORX32ri_EVEX) + .value("RORX64mi", LIEF::assembly::x86::OPCODE::RORX64mi) + .value("RORX64mi_EVEX", LIEF::assembly::x86::OPCODE::RORX64mi_EVEX) + .value("RORX64ri", LIEF::assembly::x86::OPCODE::RORX64ri) + .value("RORX64ri_EVEX", LIEF::assembly::x86::OPCODE::RORX64ri_EVEX) + .value("ROUNDPDmi", LIEF::assembly::x86::OPCODE::ROUNDPDmi) + .value("ROUNDPDri", LIEF::assembly::x86::OPCODE::ROUNDPDri) + .value("ROUNDPSmi", LIEF::assembly::x86::OPCODE::ROUNDPSmi) + .value("ROUNDPSri", LIEF::assembly::x86::OPCODE::ROUNDPSri) + .value("ROUNDSDmi", LIEF::assembly::x86::OPCODE::ROUNDSDmi) + .value("ROUNDSDmi_Int", LIEF::assembly::x86::OPCODE::ROUNDSDmi_Int) + .value("ROUNDSDri", LIEF::assembly::x86::OPCODE::ROUNDSDri) + .value("ROUNDSDri_Int", LIEF::assembly::x86::OPCODE::ROUNDSDri_Int) + .value("ROUNDSSmi", LIEF::assembly::x86::OPCODE::ROUNDSSmi) + .value("ROUNDSSmi_Int", LIEF::assembly::x86::OPCODE::ROUNDSSmi_Int) + .value("ROUNDSSri", LIEF::assembly::x86::OPCODE::ROUNDSSri) + .value("ROUNDSSri_Int", LIEF::assembly::x86::OPCODE::ROUNDSSri_Int) + .value("RSM", LIEF::assembly::x86::OPCODE::RSM) + .value("RSQRTPSm", LIEF::assembly::x86::OPCODE::RSQRTPSm) + .value("RSQRTPSr", LIEF::assembly::x86::OPCODE::RSQRTPSr) + .value("RSQRTSSm", LIEF::assembly::x86::OPCODE::RSQRTSSm) + .value("RSQRTSSm_Int", LIEF::assembly::x86::OPCODE::RSQRTSSm_Int) + .value("RSQRTSSr", LIEF::assembly::x86::OPCODE::RSQRTSSr) + .value("RSQRTSSr_Int", LIEF::assembly::x86::OPCODE::RSQRTSSr_Int) + .value("RSTORSSP", LIEF::assembly::x86::OPCODE::RSTORSSP) + .value("SAHF", LIEF::assembly::x86::OPCODE::SAHF) + .value("SALC", LIEF::assembly::x86::OPCODE::SALC) + .value("SAR16m1", LIEF::assembly::x86::OPCODE::SAR16m1) + .value("SAR16m1_EVEX", LIEF::assembly::x86::OPCODE::SAR16m1_EVEX) + .value("SAR16m1_ND", LIEF::assembly::x86::OPCODE::SAR16m1_ND) + .value("SAR16m1_NF", LIEF::assembly::x86::OPCODE::SAR16m1_NF) + .value("SAR16m1_NF_ND", LIEF::assembly::x86::OPCODE::SAR16m1_NF_ND) + .value("SAR16mCL", LIEF::assembly::x86::OPCODE::SAR16mCL) + .value("SAR16mCL_EVEX", LIEF::assembly::x86::OPCODE::SAR16mCL_EVEX) + .value("SAR16mCL_ND", LIEF::assembly::x86::OPCODE::SAR16mCL_ND) + .value("SAR16mCL_NF", LIEF::assembly::x86::OPCODE::SAR16mCL_NF) + .value("SAR16mCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR16mCL_NF_ND) + .value("SAR16mi", LIEF::assembly::x86::OPCODE::SAR16mi) + .value("SAR16mi_EVEX", LIEF::assembly::x86::OPCODE::SAR16mi_EVEX) + .value("SAR16mi_ND", LIEF::assembly::x86::OPCODE::SAR16mi_ND) + .value("SAR16mi_NF", LIEF::assembly::x86::OPCODE::SAR16mi_NF) + .value("SAR16mi_NF_ND", LIEF::assembly::x86::OPCODE::SAR16mi_NF_ND) + .value("SAR16r1", LIEF::assembly::x86::OPCODE::SAR16r1) + .value("SAR16r1_EVEX", LIEF::assembly::x86::OPCODE::SAR16r1_EVEX) + .value("SAR16r1_ND", LIEF::assembly::x86::OPCODE::SAR16r1_ND) + .value("SAR16r1_NF", LIEF::assembly::x86::OPCODE::SAR16r1_NF) + .value("SAR16r1_NF_ND", LIEF::assembly::x86::OPCODE::SAR16r1_NF_ND) + .value("SAR16rCL", LIEF::assembly::x86::OPCODE::SAR16rCL) + .value("SAR16rCL_EVEX", LIEF::assembly::x86::OPCODE::SAR16rCL_EVEX) + .value("SAR16rCL_ND", LIEF::assembly::x86::OPCODE::SAR16rCL_ND) + .value("SAR16rCL_NF", LIEF::assembly::x86::OPCODE::SAR16rCL_NF) + .value("SAR16rCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR16rCL_NF_ND) + .value("SAR16ri", LIEF::assembly::x86::OPCODE::SAR16ri) + .value("SAR16ri_EVEX", LIEF::assembly::x86::OPCODE::SAR16ri_EVEX) + .value("SAR16ri_ND", LIEF::assembly::x86::OPCODE::SAR16ri_ND) + .value("SAR16ri_NF", LIEF::assembly::x86::OPCODE::SAR16ri_NF) + .value("SAR16ri_NF_ND", LIEF::assembly::x86::OPCODE::SAR16ri_NF_ND) + .value("SAR32m1", LIEF::assembly::x86::OPCODE::SAR32m1) + .value("SAR32m1_EVEX", LIEF::assembly::x86::OPCODE::SAR32m1_EVEX) + .value("SAR32m1_ND", LIEF::assembly::x86::OPCODE::SAR32m1_ND) + .value("SAR32m1_NF", LIEF::assembly::x86::OPCODE::SAR32m1_NF) + .value("SAR32m1_NF_ND", LIEF::assembly::x86::OPCODE::SAR32m1_NF_ND) + .value("SAR32mCL", LIEF::assembly::x86::OPCODE::SAR32mCL) + .value("SAR32mCL_EVEX", LIEF::assembly::x86::OPCODE::SAR32mCL_EVEX) + .value("SAR32mCL_ND", LIEF::assembly::x86::OPCODE::SAR32mCL_ND) + .value("SAR32mCL_NF", LIEF::assembly::x86::OPCODE::SAR32mCL_NF) + .value("SAR32mCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR32mCL_NF_ND) + .value("SAR32mi", LIEF::assembly::x86::OPCODE::SAR32mi) + .value("SAR32mi_EVEX", LIEF::assembly::x86::OPCODE::SAR32mi_EVEX) + .value("SAR32mi_ND", LIEF::assembly::x86::OPCODE::SAR32mi_ND) + .value("SAR32mi_NF", LIEF::assembly::x86::OPCODE::SAR32mi_NF) + .value("SAR32mi_NF_ND", LIEF::assembly::x86::OPCODE::SAR32mi_NF_ND) + .value("SAR32r1", LIEF::assembly::x86::OPCODE::SAR32r1) + .value("SAR32r1_EVEX", LIEF::assembly::x86::OPCODE::SAR32r1_EVEX) + .value("SAR32r1_ND", LIEF::assembly::x86::OPCODE::SAR32r1_ND) + .value("SAR32r1_NF", LIEF::assembly::x86::OPCODE::SAR32r1_NF) + .value("SAR32r1_NF_ND", LIEF::assembly::x86::OPCODE::SAR32r1_NF_ND) + .value("SAR32rCL", LIEF::assembly::x86::OPCODE::SAR32rCL) + .value("SAR32rCL_EVEX", LIEF::assembly::x86::OPCODE::SAR32rCL_EVEX) + .value("SAR32rCL_ND", LIEF::assembly::x86::OPCODE::SAR32rCL_ND) + .value("SAR32rCL_NF", LIEF::assembly::x86::OPCODE::SAR32rCL_NF) + .value("SAR32rCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR32rCL_NF_ND) + .value("SAR32ri", LIEF::assembly::x86::OPCODE::SAR32ri) + .value("SAR32ri_EVEX", LIEF::assembly::x86::OPCODE::SAR32ri_EVEX) + .value("SAR32ri_ND", LIEF::assembly::x86::OPCODE::SAR32ri_ND) + .value("SAR32ri_NF", LIEF::assembly::x86::OPCODE::SAR32ri_NF) + .value("SAR32ri_NF_ND", LIEF::assembly::x86::OPCODE::SAR32ri_NF_ND) + .value("SAR64m1", LIEF::assembly::x86::OPCODE::SAR64m1) + .value("SAR64m1_EVEX", LIEF::assembly::x86::OPCODE::SAR64m1_EVEX) + .value("SAR64m1_ND", LIEF::assembly::x86::OPCODE::SAR64m1_ND) + .value("SAR64m1_NF", LIEF::assembly::x86::OPCODE::SAR64m1_NF) + .value("SAR64m1_NF_ND", LIEF::assembly::x86::OPCODE::SAR64m1_NF_ND) + .value("SAR64mCL", LIEF::assembly::x86::OPCODE::SAR64mCL) + .value("SAR64mCL_EVEX", LIEF::assembly::x86::OPCODE::SAR64mCL_EVEX) + .value("SAR64mCL_ND", LIEF::assembly::x86::OPCODE::SAR64mCL_ND) + .value("SAR64mCL_NF", LIEF::assembly::x86::OPCODE::SAR64mCL_NF) + .value("SAR64mCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR64mCL_NF_ND) + .value("SAR64mi", LIEF::assembly::x86::OPCODE::SAR64mi) + .value("SAR64mi_EVEX", LIEF::assembly::x86::OPCODE::SAR64mi_EVEX) + .value("SAR64mi_ND", LIEF::assembly::x86::OPCODE::SAR64mi_ND) + .value("SAR64mi_NF", LIEF::assembly::x86::OPCODE::SAR64mi_NF) + .value("SAR64mi_NF_ND", LIEF::assembly::x86::OPCODE::SAR64mi_NF_ND) + .value("SAR64r1", LIEF::assembly::x86::OPCODE::SAR64r1) + .value("SAR64r1_EVEX", LIEF::assembly::x86::OPCODE::SAR64r1_EVEX) + .value("SAR64r1_ND", LIEF::assembly::x86::OPCODE::SAR64r1_ND) + .value("SAR64r1_NF", LIEF::assembly::x86::OPCODE::SAR64r1_NF) + .value("SAR64r1_NF_ND", LIEF::assembly::x86::OPCODE::SAR64r1_NF_ND) + .value("SAR64rCL", LIEF::assembly::x86::OPCODE::SAR64rCL) + .value("SAR64rCL_EVEX", LIEF::assembly::x86::OPCODE::SAR64rCL_EVEX) + .value("SAR64rCL_ND", LIEF::assembly::x86::OPCODE::SAR64rCL_ND) + .value("SAR64rCL_NF", LIEF::assembly::x86::OPCODE::SAR64rCL_NF) + .value("SAR64rCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR64rCL_NF_ND) + .value("SAR64ri", LIEF::assembly::x86::OPCODE::SAR64ri) + .value("SAR64ri_EVEX", LIEF::assembly::x86::OPCODE::SAR64ri_EVEX) + .value("SAR64ri_ND", LIEF::assembly::x86::OPCODE::SAR64ri_ND) + .value("SAR64ri_NF", LIEF::assembly::x86::OPCODE::SAR64ri_NF) + .value("SAR64ri_NF_ND", LIEF::assembly::x86::OPCODE::SAR64ri_NF_ND) + .value("SAR8m1", LIEF::assembly::x86::OPCODE::SAR8m1) + .value("SAR8m1_EVEX", LIEF::assembly::x86::OPCODE::SAR8m1_EVEX) + .value("SAR8m1_ND", LIEF::assembly::x86::OPCODE::SAR8m1_ND) + .value("SAR8m1_NF", LIEF::assembly::x86::OPCODE::SAR8m1_NF) + .value("SAR8m1_NF_ND", LIEF::assembly::x86::OPCODE::SAR8m1_NF_ND) + .value("SAR8mCL", LIEF::assembly::x86::OPCODE::SAR8mCL) + .value("SAR8mCL_EVEX", LIEF::assembly::x86::OPCODE::SAR8mCL_EVEX) + .value("SAR8mCL_ND", LIEF::assembly::x86::OPCODE::SAR8mCL_ND) + .value("SAR8mCL_NF", LIEF::assembly::x86::OPCODE::SAR8mCL_NF) + .value("SAR8mCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR8mCL_NF_ND) + .value("SAR8mi", LIEF::assembly::x86::OPCODE::SAR8mi) + .value("SAR8mi_EVEX", LIEF::assembly::x86::OPCODE::SAR8mi_EVEX) + .value("SAR8mi_ND", LIEF::assembly::x86::OPCODE::SAR8mi_ND) + .value("SAR8mi_NF", LIEF::assembly::x86::OPCODE::SAR8mi_NF) + .value("SAR8mi_NF_ND", LIEF::assembly::x86::OPCODE::SAR8mi_NF_ND) + .value("SAR8r1", LIEF::assembly::x86::OPCODE::SAR8r1) + .value("SAR8r1_EVEX", LIEF::assembly::x86::OPCODE::SAR8r1_EVEX) + .value("SAR8r1_ND", LIEF::assembly::x86::OPCODE::SAR8r1_ND) + .value("SAR8r1_NF", LIEF::assembly::x86::OPCODE::SAR8r1_NF) + .value("SAR8r1_NF_ND", LIEF::assembly::x86::OPCODE::SAR8r1_NF_ND) + .value("SAR8rCL", LIEF::assembly::x86::OPCODE::SAR8rCL) + .value("SAR8rCL_EVEX", LIEF::assembly::x86::OPCODE::SAR8rCL_EVEX) + .value("SAR8rCL_ND", LIEF::assembly::x86::OPCODE::SAR8rCL_ND) + .value("SAR8rCL_NF", LIEF::assembly::x86::OPCODE::SAR8rCL_NF) + .value("SAR8rCL_NF_ND", LIEF::assembly::x86::OPCODE::SAR8rCL_NF_ND) + .value("SAR8ri", LIEF::assembly::x86::OPCODE::SAR8ri) + .value("SAR8ri_EVEX", LIEF::assembly::x86::OPCODE::SAR8ri_EVEX) + .value("SAR8ri_ND", LIEF::assembly::x86::OPCODE::SAR8ri_ND) + .value("SAR8ri_NF", LIEF::assembly::x86::OPCODE::SAR8ri_NF) + .value("SAR8ri_NF_ND", LIEF::assembly::x86::OPCODE::SAR8ri_NF_ND) + .value("SARX32rm", LIEF::assembly::x86::OPCODE::SARX32rm) + .value("SARX32rm_EVEX", LIEF::assembly::x86::OPCODE::SARX32rm_EVEX) + .value("SARX32rr", LIEF::assembly::x86::OPCODE::SARX32rr) + .value("SARX32rr_EVEX", LIEF::assembly::x86::OPCODE::SARX32rr_EVEX) + .value("SARX64rm", LIEF::assembly::x86::OPCODE::SARX64rm) + .value("SARX64rm_EVEX", LIEF::assembly::x86::OPCODE::SARX64rm_EVEX) + .value("SARX64rr", LIEF::assembly::x86::OPCODE::SARX64rr) + .value("SARX64rr_EVEX", LIEF::assembly::x86::OPCODE::SARX64rr_EVEX) + .value("SAVEPREVSSP", LIEF::assembly::x86::OPCODE::SAVEPREVSSP) + .value("SBB16i16", LIEF::assembly::x86::OPCODE::SBB16i16) + .value("SBB16mi", LIEF::assembly::x86::OPCODE::SBB16mi) + .value("SBB16mi8", LIEF::assembly::x86::OPCODE::SBB16mi8) + .value("SBB16mi8_EVEX", LIEF::assembly::x86::OPCODE::SBB16mi8_EVEX) + .value("SBB16mi8_ND", LIEF::assembly::x86::OPCODE::SBB16mi8_ND) + .value("SBB16mi_EVEX", LIEF::assembly::x86::OPCODE::SBB16mi_EVEX) + .value("SBB16mi_ND", LIEF::assembly::x86::OPCODE::SBB16mi_ND) + .value("SBB16mr", LIEF::assembly::x86::OPCODE::SBB16mr) + .value("SBB16mr_EVEX", LIEF::assembly::x86::OPCODE::SBB16mr_EVEX) + .value("SBB16mr_ND", LIEF::assembly::x86::OPCODE::SBB16mr_ND) + .value("SBB16ri", LIEF::assembly::x86::OPCODE::SBB16ri) + .value("SBB16ri8", LIEF::assembly::x86::OPCODE::SBB16ri8) + .value("SBB16ri8_EVEX", LIEF::assembly::x86::OPCODE::SBB16ri8_EVEX) + .value("SBB16ri8_ND", LIEF::assembly::x86::OPCODE::SBB16ri8_ND) + .value("SBB16ri_EVEX", LIEF::assembly::x86::OPCODE::SBB16ri_EVEX) + .value("SBB16ri_ND", LIEF::assembly::x86::OPCODE::SBB16ri_ND) + .value("SBB16rm", LIEF::assembly::x86::OPCODE::SBB16rm) + .value("SBB16rm_EVEX", LIEF::assembly::x86::OPCODE::SBB16rm_EVEX) + .value("SBB16rm_ND", LIEF::assembly::x86::OPCODE::SBB16rm_ND) + .value("SBB16rr", LIEF::assembly::x86::OPCODE::SBB16rr) + .value("SBB16rr_EVEX", LIEF::assembly::x86::OPCODE::SBB16rr_EVEX) + .value("SBB16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SBB16rr_EVEX_REV) + .value("SBB16rr_ND", LIEF::assembly::x86::OPCODE::SBB16rr_ND) + .value("SBB16rr_ND_REV", LIEF::assembly::x86::OPCODE::SBB16rr_ND_REV) + .value("SBB16rr_REV", LIEF::assembly::x86::OPCODE::SBB16rr_REV) + .value("SBB32i32", LIEF::assembly::x86::OPCODE::SBB32i32) + .value("SBB32mi", LIEF::assembly::x86::OPCODE::SBB32mi) + .value("SBB32mi8", LIEF::assembly::x86::OPCODE::SBB32mi8) + .value("SBB32mi8_EVEX", LIEF::assembly::x86::OPCODE::SBB32mi8_EVEX) + .value("SBB32mi8_ND", LIEF::assembly::x86::OPCODE::SBB32mi8_ND) + .value("SBB32mi_EVEX", LIEF::assembly::x86::OPCODE::SBB32mi_EVEX) + .value("SBB32mi_ND", LIEF::assembly::x86::OPCODE::SBB32mi_ND) + .value("SBB32mr", LIEF::assembly::x86::OPCODE::SBB32mr) + .value("SBB32mr_EVEX", LIEF::assembly::x86::OPCODE::SBB32mr_EVEX) + .value("SBB32mr_ND", LIEF::assembly::x86::OPCODE::SBB32mr_ND) + .value("SBB32ri", LIEF::assembly::x86::OPCODE::SBB32ri) + .value("SBB32ri8", LIEF::assembly::x86::OPCODE::SBB32ri8) + .value("SBB32ri8_EVEX", LIEF::assembly::x86::OPCODE::SBB32ri8_EVEX) + .value("SBB32ri8_ND", LIEF::assembly::x86::OPCODE::SBB32ri8_ND) + .value("SBB32ri_EVEX", LIEF::assembly::x86::OPCODE::SBB32ri_EVEX) + .value("SBB32ri_ND", LIEF::assembly::x86::OPCODE::SBB32ri_ND) + .value("SBB32rm", LIEF::assembly::x86::OPCODE::SBB32rm) + .value("SBB32rm_EVEX", LIEF::assembly::x86::OPCODE::SBB32rm_EVEX) + .value("SBB32rm_ND", LIEF::assembly::x86::OPCODE::SBB32rm_ND) + .value("SBB32rr", LIEF::assembly::x86::OPCODE::SBB32rr) + .value("SBB32rr_EVEX", LIEF::assembly::x86::OPCODE::SBB32rr_EVEX) + .value("SBB32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SBB32rr_EVEX_REV) + .value("SBB32rr_ND", LIEF::assembly::x86::OPCODE::SBB32rr_ND) + .value("SBB32rr_ND_REV", LIEF::assembly::x86::OPCODE::SBB32rr_ND_REV) + .value("SBB32rr_REV", LIEF::assembly::x86::OPCODE::SBB32rr_REV) + .value("SBB64i32", LIEF::assembly::x86::OPCODE::SBB64i32) + .value("SBB64mi32", LIEF::assembly::x86::OPCODE::SBB64mi32) + .value("SBB64mi32_EVEX", LIEF::assembly::x86::OPCODE::SBB64mi32_EVEX) + .value("SBB64mi32_ND", LIEF::assembly::x86::OPCODE::SBB64mi32_ND) + .value("SBB64mi8", LIEF::assembly::x86::OPCODE::SBB64mi8) + .value("SBB64mi8_EVEX", LIEF::assembly::x86::OPCODE::SBB64mi8_EVEX) + .value("SBB64mi8_ND", LIEF::assembly::x86::OPCODE::SBB64mi8_ND); + opcodes.value("SBB64mr", LIEF::assembly::x86::OPCODE::SBB64mr) + .value("SBB64mr_EVEX", LIEF::assembly::x86::OPCODE::SBB64mr_EVEX) + .value("SBB64mr_ND", LIEF::assembly::x86::OPCODE::SBB64mr_ND) + .value("SBB64ri32", LIEF::assembly::x86::OPCODE::SBB64ri32) + .value("SBB64ri32_EVEX", LIEF::assembly::x86::OPCODE::SBB64ri32_EVEX) + .value("SBB64ri32_ND", LIEF::assembly::x86::OPCODE::SBB64ri32_ND) + .value("SBB64ri8", LIEF::assembly::x86::OPCODE::SBB64ri8) + .value("SBB64ri8_EVEX", LIEF::assembly::x86::OPCODE::SBB64ri8_EVEX) + .value("SBB64ri8_ND", LIEF::assembly::x86::OPCODE::SBB64ri8_ND) + .value("SBB64rm", LIEF::assembly::x86::OPCODE::SBB64rm) + .value("SBB64rm_EVEX", LIEF::assembly::x86::OPCODE::SBB64rm_EVEX) + .value("SBB64rm_ND", LIEF::assembly::x86::OPCODE::SBB64rm_ND) + .value("SBB64rr", LIEF::assembly::x86::OPCODE::SBB64rr) + .value("SBB64rr_EVEX", LIEF::assembly::x86::OPCODE::SBB64rr_EVEX) + .value("SBB64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SBB64rr_EVEX_REV) + .value("SBB64rr_ND", LIEF::assembly::x86::OPCODE::SBB64rr_ND) + .value("SBB64rr_ND_REV", LIEF::assembly::x86::OPCODE::SBB64rr_ND_REV) + .value("SBB64rr_REV", LIEF::assembly::x86::OPCODE::SBB64rr_REV) + .value("SBB8i8", LIEF::assembly::x86::OPCODE::SBB8i8) + .value("SBB8mi", LIEF::assembly::x86::OPCODE::SBB8mi) + .value("SBB8mi8", LIEF::assembly::x86::OPCODE::SBB8mi8) + .value("SBB8mi_EVEX", LIEF::assembly::x86::OPCODE::SBB8mi_EVEX) + .value("SBB8mi_ND", LIEF::assembly::x86::OPCODE::SBB8mi_ND) + .value("SBB8mr", LIEF::assembly::x86::OPCODE::SBB8mr) + .value("SBB8mr_EVEX", LIEF::assembly::x86::OPCODE::SBB8mr_EVEX) + .value("SBB8mr_ND", LIEF::assembly::x86::OPCODE::SBB8mr_ND) + .value("SBB8ri", LIEF::assembly::x86::OPCODE::SBB8ri) + .value("SBB8ri8", LIEF::assembly::x86::OPCODE::SBB8ri8) + .value("SBB8ri_EVEX", LIEF::assembly::x86::OPCODE::SBB8ri_EVEX) + .value("SBB8ri_ND", LIEF::assembly::x86::OPCODE::SBB8ri_ND) + .value("SBB8rm", LIEF::assembly::x86::OPCODE::SBB8rm) + .value("SBB8rm_EVEX", LIEF::assembly::x86::OPCODE::SBB8rm_EVEX) + .value("SBB8rm_ND", LIEF::assembly::x86::OPCODE::SBB8rm_ND) + .value("SBB8rr", LIEF::assembly::x86::OPCODE::SBB8rr) + .value("SBB8rr_EVEX", LIEF::assembly::x86::OPCODE::SBB8rr_EVEX) + .value("SBB8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SBB8rr_EVEX_REV) + .value("SBB8rr_ND", LIEF::assembly::x86::OPCODE::SBB8rr_ND) + .value("SBB8rr_ND_REV", LIEF::assembly::x86::OPCODE::SBB8rr_ND_REV) + .value("SBB8rr_REV", LIEF::assembly::x86::OPCODE::SBB8rr_REV) + .value("SCASB", LIEF::assembly::x86::OPCODE::SCASB) + .value("SCASL", LIEF::assembly::x86::OPCODE::SCASL) + .value("SCASQ", LIEF::assembly::x86::OPCODE::SCASQ) + .value("SCASW", LIEF::assembly::x86::OPCODE::SCASW) + .value("SEAMCALL", LIEF::assembly::x86::OPCODE::SEAMCALL) + .value("SEAMOPS", LIEF::assembly::x86::OPCODE::SEAMOPS) + .value("SEAMRET", LIEF::assembly::x86::OPCODE::SEAMRET) + .value("SEG_ALLOCA_32", LIEF::assembly::x86::OPCODE::SEG_ALLOCA_32) + .value("SEG_ALLOCA_64", LIEF::assembly::x86::OPCODE::SEG_ALLOCA_64) + .value("SENDUIPI", LIEF::assembly::x86::OPCODE::SENDUIPI) + .value("SERIALIZE", LIEF::assembly::x86::OPCODE::SERIALIZE) + .value("SETCCm", LIEF::assembly::x86::OPCODE::SETCCm) + .value("SETCCm_EVEX", LIEF::assembly::x86::OPCODE::SETCCm_EVEX) + .value("SETCCr", LIEF::assembly::x86::OPCODE::SETCCr) + .value("SETCCr_EVEX", LIEF::assembly::x86::OPCODE::SETCCr_EVEX) + .value("SETSSBSY", LIEF::assembly::x86::OPCODE::SETSSBSY) + .value("SETZUCCm", LIEF::assembly::x86::OPCODE::SETZUCCm) + .value("SETZUCCr", LIEF::assembly::x86::OPCODE::SETZUCCr) + .value("SFENCE", LIEF::assembly::x86::OPCODE::SFENCE) + .value("SGDT16m", LIEF::assembly::x86::OPCODE::SGDT16m) + .value("SGDT32m", LIEF::assembly::x86::OPCODE::SGDT32m) + .value("SGDT64m", LIEF::assembly::x86::OPCODE::SGDT64m) + .value("SHA1MSG1rm", LIEF::assembly::x86::OPCODE::SHA1MSG1rm) + .value("SHA1MSG1rr", LIEF::assembly::x86::OPCODE::SHA1MSG1rr) + .value("SHA1MSG2rm", LIEF::assembly::x86::OPCODE::SHA1MSG2rm) + .value("SHA1MSG2rr", LIEF::assembly::x86::OPCODE::SHA1MSG2rr) + .value("SHA1NEXTErm", LIEF::assembly::x86::OPCODE::SHA1NEXTErm) + .value("SHA1NEXTErr", LIEF::assembly::x86::OPCODE::SHA1NEXTErr) + .value("SHA1RNDS4rmi", LIEF::assembly::x86::OPCODE::SHA1RNDS4rmi) + .value("SHA1RNDS4rri", LIEF::assembly::x86::OPCODE::SHA1RNDS4rri) + .value("SHA256MSG1rm", LIEF::assembly::x86::OPCODE::SHA256MSG1rm) + .value("SHA256MSG1rr", LIEF::assembly::x86::OPCODE::SHA256MSG1rr) + .value("SHA256MSG2rm", LIEF::assembly::x86::OPCODE::SHA256MSG2rm) + .value("SHA256MSG2rr", LIEF::assembly::x86::OPCODE::SHA256MSG2rr) + .value("SHA256RNDS2rm", LIEF::assembly::x86::OPCODE::SHA256RNDS2rm) + .value("SHA256RNDS2rr", LIEF::assembly::x86::OPCODE::SHA256RNDS2rr) + .value("SHL16m1", LIEF::assembly::x86::OPCODE::SHL16m1) + .value("SHL16m1_EVEX", LIEF::assembly::x86::OPCODE::SHL16m1_EVEX) + .value("SHL16m1_ND", LIEF::assembly::x86::OPCODE::SHL16m1_ND) + .value("SHL16m1_NF", LIEF::assembly::x86::OPCODE::SHL16m1_NF) + .value("SHL16m1_NF_ND", LIEF::assembly::x86::OPCODE::SHL16m1_NF_ND) + .value("SHL16mCL", LIEF::assembly::x86::OPCODE::SHL16mCL) + .value("SHL16mCL_EVEX", LIEF::assembly::x86::OPCODE::SHL16mCL_EVEX) + .value("SHL16mCL_ND", LIEF::assembly::x86::OPCODE::SHL16mCL_ND) + .value("SHL16mCL_NF", LIEF::assembly::x86::OPCODE::SHL16mCL_NF) + .value("SHL16mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL16mCL_NF_ND) + .value("SHL16mi", LIEF::assembly::x86::OPCODE::SHL16mi) + .value("SHL16mi_EVEX", LIEF::assembly::x86::OPCODE::SHL16mi_EVEX) + .value("SHL16mi_ND", LIEF::assembly::x86::OPCODE::SHL16mi_ND) + .value("SHL16mi_NF", LIEF::assembly::x86::OPCODE::SHL16mi_NF) + .value("SHL16mi_NF_ND", LIEF::assembly::x86::OPCODE::SHL16mi_NF_ND) + .value("SHL16r1", LIEF::assembly::x86::OPCODE::SHL16r1) + .value("SHL16r1_EVEX", LIEF::assembly::x86::OPCODE::SHL16r1_EVEX) + .value("SHL16r1_ND", LIEF::assembly::x86::OPCODE::SHL16r1_ND) + .value("SHL16r1_NF", LIEF::assembly::x86::OPCODE::SHL16r1_NF) + .value("SHL16r1_NF_ND", LIEF::assembly::x86::OPCODE::SHL16r1_NF_ND) + .value("SHL16rCL", LIEF::assembly::x86::OPCODE::SHL16rCL) + .value("SHL16rCL_EVEX", LIEF::assembly::x86::OPCODE::SHL16rCL_EVEX) + .value("SHL16rCL_ND", LIEF::assembly::x86::OPCODE::SHL16rCL_ND) + .value("SHL16rCL_NF", LIEF::assembly::x86::OPCODE::SHL16rCL_NF) + .value("SHL16rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL16rCL_NF_ND) + .value("SHL16ri", LIEF::assembly::x86::OPCODE::SHL16ri) + .value("SHL16ri_EVEX", LIEF::assembly::x86::OPCODE::SHL16ri_EVEX) + .value("SHL16ri_ND", LIEF::assembly::x86::OPCODE::SHL16ri_ND) + .value("SHL16ri_NF", LIEF::assembly::x86::OPCODE::SHL16ri_NF) + .value("SHL16ri_NF_ND", LIEF::assembly::x86::OPCODE::SHL16ri_NF_ND) + .value("SHL32m1", LIEF::assembly::x86::OPCODE::SHL32m1) + .value("SHL32m1_EVEX", LIEF::assembly::x86::OPCODE::SHL32m1_EVEX) + .value("SHL32m1_ND", LIEF::assembly::x86::OPCODE::SHL32m1_ND) + .value("SHL32m1_NF", LIEF::assembly::x86::OPCODE::SHL32m1_NF) + .value("SHL32m1_NF_ND", LIEF::assembly::x86::OPCODE::SHL32m1_NF_ND) + .value("SHL32mCL", LIEF::assembly::x86::OPCODE::SHL32mCL) + .value("SHL32mCL_EVEX", LIEF::assembly::x86::OPCODE::SHL32mCL_EVEX) + .value("SHL32mCL_ND", LIEF::assembly::x86::OPCODE::SHL32mCL_ND) + .value("SHL32mCL_NF", LIEF::assembly::x86::OPCODE::SHL32mCL_NF) + .value("SHL32mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL32mCL_NF_ND) + .value("SHL32mi", LIEF::assembly::x86::OPCODE::SHL32mi) + .value("SHL32mi_EVEX", LIEF::assembly::x86::OPCODE::SHL32mi_EVEX) + .value("SHL32mi_ND", LIEF::assembly::x86::OPCODE::SHL32mi_ND) + .value("SHL32mi_NF", LIEF::assembly::x86::OPCODE::SHL32mi_NF) + .value("SHL32mi_NF_ND", LIEF::assembly::x86::OPCODE::SHL32mi_NF_ND) + .value("SHL32r1", LIEF::assembly::x86::OPCODE::SHL32r1) + .value("SHL32r1_EVEX", LIEF::assembly::x86::OPCODE::SHL32r1_EVEX) + .value("SHL32r1_ND", LIEF::assembly::x86::OPCODE::SHL32r1_ND) + .value("SHL32r1_NF", LIEF::assembly::x86::OPCODE::SHL32r1_NF) + .value("SHL32r1_NF_ND", LIEF::assembly::x86::OPCODE::SHL32r1_NF_ND) + .value("SHL32rCL", LIEF::assembly::x86::OPCODE::SHL32rCL) + .value("SHL32rCL_EVEX", LIEF::assembly::x86::OPCODE::SHL32rCL_EVEX) + .value("SHL32rCL_ND", LIEF::assembly::x86::OPCODE::SHL32rCL_ND) + .value("SHL32rCL_NF", LIEF::assembly::x86::OPCODE::SHL32rCL_NF) + .value("SHL32rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL32rCL_NF_ND) + .value("SHL32ri", LIEF::assembly::x86::OPCODE::SHL32ri) + .value("SHL32ri_EVEX", LIEF::assembly::x86::OPCODE::SHL32ri_EVEX) + .value("SHL32ri_ND", LIEF::assembly::x86::OPCODE::SHL32ri_ND) + .value("SHL32ri_NF", LIEF::assembly::x86::OPCODE::SHL32ri_NF) + .value("SHL32ri_NF_ND", LIEF::assembly::x86::OPCODE::SHL32ri_NF_ND) + .value("SHL64m1", LIEF::assembly::x86::OPCODE::SHL64m1) + .value("SHL64m1_EVEX", LIEF::assembly::x86::OPCODE::SHL64m1_EVEX) + .value("SHL64m1_ND", LIEF::assembly::x86::OPCODE::SHL64m1_ND) + .value("SHL64m1_NF", LIEF::assembly::x86::OPCODE::SHL64m1_NF) + .value("SHL64m1_NF_ND", LIEF::assembly::x86::OPCODE::SHL64m1_NF_ND) + .value("SHL64mCL", LIEF::assembly::x86::OPCODE::SHL64mCL) + .value("SHL64mCL_EVEX", LIEF::assembly::x86::OPCODE::SHL64mCL_EVEX) + .value("SHL64mCL_ND", LIEF::assembly::x86::OPCODE::SHL64mCL_ND) + .value("SHL64mCL_NF", LIEF::assembly::x86::OPCODE::SHL64mCL_NF) + .value("SHL64mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL64mCL_NF_ND) + .value("SHL64mi", LIEF::assembly::x86::OPCODE::SHL64mi) + .value("SHL64mi_EVEX", LIEF::assembly::x86::OPCODE::SHL64mi_EVEX) + .value("SHL64mi_ND", LIEF::assembly::x86::OPCODE::SHL64mi_ND) + .value("SHL64mi_NF", LIEF::assembly::x86::OPCODE::SHL64mi_NF) + .value("SHL64mi_NF_ND", LIEF::assembly::x86::OPCODE::SHL64mi_NF_ND) + .value("SHL64r1", LIEF::assembly::x86::OPCODE::SHL64r1) + .value("SHL64r1_EVEX", LIEF::assembly::x86::OPCODE::SHL64r1_EVEX) + .value("SHL64r1_ND", LIEF::assembly::x86::OPCODE::SHL64r1_ND) + .value("SHL64r1_NF", LIEF::assembly::x86::OPCODE::SHL64r1_NF) + .value("SHL64r1_NF_ND", LIEF::assembly::x86::OPCODE::SHL64r1_NF_ND) + .value("SHL64rCL", LIEF::assembly::x86::OPCODE::SHL64rCL) + .value("SHL64rCL_EVEX", LIEF::assembly::x86::OPCODE::SHL64rCL_EVEX) + .value("SHL64rCL_ND", LIEF::assembly::x86::OPCODE::SHL64rCL_ND) + .value("SHL64rCL_NF", LIEF::assembly::x86::OPCODE::SHL64rCL_NF) + .value("SHL64rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL64rCL_NF_ND) + .value("SHL64ri", LIEF::assembly::x86::OPCODE::SHL64ri) + .value("SHL64ri_EVEX", LIEF::assembly::x86::OPCODE::SHL64ri_EVEX) + .value("SHL64ri_ND", LIEF::assembly::x86::OPCODE::SHL64ri_ND) + .value("SHL64ri_NF", LIEF::assembly::x86::OPCODE::SHL64ri_NF) + .value("SHL64ri_NF_ND", LIEF::assembly::x86::OPCODE::SHL64ri_NF_ND) + .value("SHL8m1", LIEF::assembly::x86::OPCODE::SHL8m1) + .value("SHL8m1_EVEX", LIEF::assembly::x86::OPCODE::SHL8m1_EVEX) + .value("SHL8m1_ND", LIEF::assembly::x86::OPCODE::SHL8m1_ND) + .value("SHL8m1_NF", LIEF::assembly::x86::OPCODE::SHL8m1_NF) + .value("SHL8m1_NF_ND", LIEF::assembly::x86::OPCODE::SHL8m1_NF_ND) + .value("SHL8mCL", LIEF::assembly::x86::OPCODE::SHL8mCL) + .value("SHL8mCL_EVEX", LIEF::assembly::x86::OPCODE::SHL8mCL_EVEX) + .value("SHL8mCL_ND", LIEF::assembly::x86::OPCODE::SHL8mCL_ND) + .value("SHL8mCL_NF", LIEF::assembly::x86::OPCODE::SHL8mCL_NF) + .value("SHL8mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL8mCL_NF_ND) + .value("SHL8mi", LIEF::assembly::x86::OPCODE::SHL8mi) + .value("SHL8mi_EVEX", LIEF::assembly::x86::OPCODE::SHL8mi_EVEX) + .value("SHL8mi_ND", LIEF::assembly::x86::OPCODE::SHL8mi_ND) + .value("SHL8mi_NF", LIEF::assembly::x86::OPCODE::SHL8mi_NF) + .value("SHL8mi_NF_ND", LIEF::assembly::x86::OPCODE::SHL8mi_NF_ND) + .value("SHL8r1", LIEF::assembly::x86::OPCODE::SHL8r1) + .value("SHL8r1_EVEX", LIEF::assembly::x86::OPCODE::SHL8r1_EVEX) + .value("SHL8r1_ND", LIEF::assembly::x86::OPCODE::SHL8r1_ND) + .value("SHL8r1_NF", LIEF::assembly::x86::OPCODE::SHL8r1_NF) + .value("SHL8r1_NF_ND", LIEF::assembly::x86::OPCODE::SHL8r1_NF_ND) + .value("SHL8rCL", LIEF::assembly::x86::OPCODE::SHL8rCL) + .value("SHL8rCL_EVEX", LIEF::assembly::x86::OPCODE::SHL8rCL_EVEX) + .value("SHL8rCL_ND", LIEF::assembly::x86::OPCODE::SHL8rCL_ND) + .value("SHL8rCL_NF", LIEF::assembly::x86::OPCODE::SHL8rCL_NF) + .value("SHL8rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHL8rCL_NF_ND) + .value("SHL8ri", LIEF::assembly::x86::OPCODE::SHL8ri) + .value("SHL8ri_EVEX", LIEF::assembly::x86::OPCODE::SHL8ri_EVEX) + .value("SHL8ri_ND", LIEF::assembly::x86::OPCODE::SHL8ri_ND) + .value("SHL8ri_NF", LIEF::assembly::x86::OPCODE::SHL8ri_NF) + .value("SHL8ri_NF_ND", LIEF::assembly::x86::OPCODE::SHL8ri_NF_ND) + .value("SHLD16mrCL", LIEF::assembly::x86::OPCODE::SHLD16mrCL) + .value("SHLD16mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD16mrCL_EVEX) + .value("SHLD16mrCL_ND", LIEF::assembly::x86::OPCODE::SHLD16mrCL_ND) + .value("SHLD16mrCL_NF", LIEF::assembly::x86::OPCODE::SHLD16mrCL_NF) + .value("SHLD16mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD16mrCL_NF_ND) + .value("SHLD16mri8", LIEF::assembly::x86::OPCODE::SHLD16mri8) + .value("SHLD16mri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD16mri8_EVEX) + .value("SHLD16mri8_ND", LIEF::assembly::x86::OPCODE::SHLD16mri8_ND) + .value("SHLD16mri8_NF", LIEF::assembly::x86::OPCODE::SHLD16mri8_NF) + .value("SHLD16mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD16mri8_NF_ND) + .value("SHLD16rrCL", LIEF::assembly::x86::OPCODE::SHLD16rrCL) + .value("SHLD16rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD16rrCL_EVEX) + .value("SHLD16rrCL_ND", LIEF::assembly::x86::OPCODE::SHLD16rrCL_ND) + .value("SHLD16rrCL_NF", LIEF::assembly::x86::OPCODE::SHLD16rrCL_NF) + .value("SHLD16rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD16rrCL_NF_ND) + .value("SHLD16rri8", LIEF::assembly::x86::OPCODE::SHLD16rri8) + .value("SHLD16rri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD16rri8_EVEX) + .value("SHLD16rri8_ND", LIEF::assembly::x86::OPCODE::SHLD16rri8_ND) + .value("SHLD16rri8_NF", LIEF::assembly::x86::OPCODE::SHLD16rri8_NF) + .value("SHLD16rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD16rri8_NF_ND) + .value("SHLD32mrCL", LIEF::assembly::x86::OPCODE::SHLD32mrCL) + .value("SHLD32mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD32mrCL_EVEX) + .value("SHLD32mrCL_ND", LIEF::assembly::x86::OPCODE::SHLD32mrCL_ND) + .value("SHLD32mrCL_NF", LIEF::assembly::x86::OPCODE::SHLD32mrCL_NF) + .value("SHLD32mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD32mrCL_NF_ND) + .value("SHLD32mri8", LIEF::assembly::x86::OPCODE::SHLD32mri8) + .value("SHLD32mri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD32mri8_EVEX) + .value("SHLD32mri8_ND", LIEF::assembly::x86::OPCODE::SHLD32mri8_ND) + .value("SHLD32mri8_NF", LIEF::assembly::x86::OPCODE::SHLD32mri8_NF) + .value("SHLD32mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD32mri8_NF_ND) + .value("SHLD32rrCL", LIEF::assembly::x86::OPCODE::SHLD32rrCL) + .value("SHLD32rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD32rrCL_EVEX) + .value("SHLD32rrCL_ND", LIEF::assembly::x86::OPCODE::SHLD32rrCL_ND) + .value("SHLD32rrCL_NF", LIEF::assembly::x86::OPCODE::SHLD32rrCL_NF) + .value("SHLD32rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD32rrCL_NF_ND) + .value("SHLD32rri8", LIEF::assembly::x86::OPCODE::SHLD32rri8) + .value("SHLD32rri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD32rri8_EVEX) + .value("SHLD32rri8_ND", LIEF::assembly::x86::OPCODE::SHLD32rri8_ND) + .value("SHLD32rri8_NF", LIEF::assembly::x86::OPCODE::SHLD32rri8_NF) + .value("SHLD32rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD32rri8_NF_ND) + .value("SHLD64mrCL", LIEF::assembly::x86::OPCODE::SHLD64mrCL) + .value("SHLD64mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD64mrCL_EVEX) + .value("SHLD64mrCL_ND", LIEF::assembly::x86::OPCODE::SHLD64mrCL_ND) + .value("SHLD64mrCL_NF", LIEF::assembly::x86::OPCODE::SHLD64mrCL_NF) + .value("SHLD64mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD64mrCL_NF_ND) + .value("SHLD64mri8", LIEF::assembly::x86::OPCODE::SHLD64mri8) + .value("SHLD64mri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD64mri8_EVEX) + .value("SHLD64mri8_ND", LIEF::assembly::x86::OPCODE::SHLD64mri8_ND) + .value("SHLD64mri8_NF", LIEF::assembly::x86::OPCODE::SHLD64mri8_NF) + .value("SHLD64mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD64mri8_NF_ND) + .value("SHLD64rrCL", LIEF::assembly::x86::OPCODE::SHLD64rrCL) + .value("SHLD64rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHLD64rrCL_EVEX) + .value("SHLD64rrCL_ND", LIEF::assembly::x86::OPCODE::SHLD64rrCL_ND) + .value("SHLD64rrCL_NF", LIEF::assembly::x86::OPCODE::SHLD64rrCL_NF) + .value("SHLD64rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHLD64rrCL_NF_ND) + .value("SHLD64rri8", LIEF::assembly::x86::OPCODE::SHLD64rri8) + .value("SHLD64rri8_EVEX", LIEF::assembly::x86::OPCODE::SHLD64rri8_EVEX) + .value("SHLD64rri8_ND", LIEF::assembly::x86::OPCODE::SHLD64rri8_ND) + .value("SHLD64rri8_NF", LIEF::assembly::x86::OPCODE::SHLD64rri8_NF) + .value("SHLD64rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHLD64rri8_NF_ND) + .value("SHLX32rm", LIEF::assembly::x86::OPCODE::SHLX32rm) + .value("SHLX32rm_EVEX", LIEF::assembly::x86::OPCODE::SHLX32rm_EVEX) + .value("SHLX32rr", LIEF::assembly::x86::OPCODE::SHLX32rr) + .value("SHLX32rr_EVEX", LIEF::assembly::x86::OPCODE::SHLX32rr_EVEX) + .value("SHLX64rm", LIEF::assembly::x86::OPCODE::SHLX64rm) + .value("SHLX64rm_EVEX", LIEF::assembly::x86::OPCODE::SHLX64rm_EVEX) + .value("SHLX64rr", LIEF::assembly::x86::OPCODE::SHLX64rr) + .value("SHLX64rr_EVEX", LIEF::assembly::x86::OPCODE::SHLX64rr_EVEX) + .value("SHR16m1", LIEF::assembly::x86::OPCODE::SHR16m1) + .value("SHR16m1_EVEX", LIEF::assembly::x86::OPCODE::SHR16m1_EVEX) + .value("SHR16m1_ND", LIEF::assembly::x86::OPCODE::SHR16m1_ND) + .value("SHR16m1_NF", LIEF::assembly::x86::OPCODE::SHR16m1_NF) + .value("SHR16m1_NF_ND", LIEF::assembly::x86::OPCODE::SHR16m1_NF_ND) + .value("SHR16mCL", LIEF::assembly::x86::OPCODE::SHR16mCL) + .value("SHR16mCL_EVEX", LIEF::assembly::x86::OPCODE::SHR16mCL_EVEX) + .value("SHR16mCL_ND", LIEF::assembly::x86::OPCODE::SHR16mCL_ND) + .value("SHR16mCL_NF", LIEF::assembly::x86::OPCODE::SHR16mCL_NF) + .value("SHR16mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR16mCL_NF_ND) + .value("SHR16mi", LIEF::assembly::x86::OPCODE::SHR16mi) + .value("SHR16mi_EVEX", LIEF::assembly::x86::OPCODE::SHR16mi_EVEX) + .value("SHR16mi_ND", LIEF::assembly::x86::OPCODE::SHR16mi_ND) + .value("SHR16mi_NF", LIEF::assembly::x86::OPCODE::SHR16mi_NF) + .value("SHR16mi_NF_ND", LIEF::assembly::x86::OPCODE::SHR16mi_NF_ND) + .value("SHR16r1", LIEF::assembly::x86::OPCODE::SHR16r1) + .value("SHR16r1_EVEX", LIEF::assembly::x86::OPCODE::SHR16r1_EVEX) + .value("SHR16r1_ND", LIEF::assembly::x86::OPCODE::SHR16r1_ND) + .value("SHR16r1_NF", LIEF::assembly::x86::OPCODE::SHR16r1_NF) + .value("SHR16r1_NF_ND", LIEF::assembly::x86::OPCODE::SHR16r1_NF_ND) + .value("SHR16rCL", LIEF::assembly::x86::OPCODE::SHR16rCL) + .value("SHR16rCL_EVEX", LIEF::assembly::x86::OPCODE::SHR16rCL_EVEX) + .value("SHR16rCL_ND", LIEF::assembly::x86::OPCODE::SHR16rCL_ND) + .value("SHR16rCL_NF", LIEF::assembly::x86::OPCODE::SHR16rCL_NF) + .value("SHR16rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR16rCL_NF_ND) + .value("SHR16ri", LIEF::assembly::x86::OPCODE::SHR16ri) + .value("SHR16ri_EVEX", LIEF::assembly::x86::OPCODE::SHR16ri_EVEX) + .value("SHR16ri_ND", LIEF::assembly::x86::OPCODE::SHR16ri_ND) + .value("SHR16ri_NF", LIEF::assembly::x86::OPCODE::SHR16ri_NF) + .value("SHR16ri_NF_ND", LIEF::assembly::x86::OPCODE::SHR16ri_NF_ND) + .value("SHR32m1", LIEF::assembly::x86::OPCODE::SHR32m1) + .value("SHR32m1_EVEX", LIEF::assembly::x86::OPCODE::SHR32m1_EVEX) + .value("SHR32m1_ND", LIEF::assembly::x86::OPCODE::SHR32m1_ND) + .value("SHR32m1_NF", LIEF::assembly::x86::OPCODE::SHR32m1_NF) + .value("SHR32m1_NF_ND", LIEF::assembly::x86::OPCODE::SHR32m1_NF_ND) + .value("SHR32mCL", LIEF::assembly::x86::OPCODE::SHR32mCL) + .value("SHR32mCL_EVEX", LIEF::assembly::x86::OPCODE::SHR32mCL_EVEX); + opcodes.value("SHR32mCL_ND", LIEF::assembly::x86::OPCODE::SHR32mCL_ND) + .value("SHR32mCL_NF", LIEF::assembly::x86::OPCODE::SHR32mCL_NF) + .value("SHR32mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR32mCL_NF_ND) + .value("SHR32mi", LIEF::assembly::x86::OPCODE::SHR32mi) + .value("SHR32mi_EVEX", LIEF::assembly::x86::OPCODE::SHR32mi_EVEX) + .value("SHR32mi_ND", LIEF::assembly::x86::OPCODE::SHR32mi_ND) + .value("SHR32mi_NF", LIEF::assembly::x86::OPCODE::SHR32mi_NF) + .value("SHR32mi_NF_ND", LIEF::assembly::x86::OPCODE::SHR32mi_NF_ND) + .value("SHR32r1", LIEF::assembly::x86::OPCODE::SHR32r1) + .value("SHR32r1_EVEX", LIEF::assembly::x86::OPCODE::SHR32r1_EVEX) + .value("SHR32r1_ND", LIEF::assembly::x86::OPCODE::SHR32r1_ND) + .value("SHR32r1_NF", LIEF::assembly::x86::OPCODE::SHR32r1_NF) + .value("SHR32r1_NF_ND", LIEF::assembly::x86::OPCODE::SHR32r1_NF_ND) + .value("SHR32rCL", LIEF::assembly::x86::OPCODE::SHR32rCL) + .value("SHR32rCL_EVEX", LIEF::assembly::x86::OPCODE::SHR32rCL_EVEX) + .value("SHR32rCL_ND", LIEF::assembly::x86::OPCODE::SHR32rCL_ND) + .value("SHR32rCL_NF", LIEF::assembly::x86::OPCODE::SHR32rCL_NF) + .value("SHR32rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR32rCL_NF_ND) + .value("SHR32ri", LIEF::assembly::x86::OPCODE::SHR32ri) + .value("SHR32ri_EVEX", LIEF::assembly::x86::OPCODE::SHR32ri_EVEX) + .value("SHR32ri_ND", LIEF::assembly::x86::OPCODE::SHR32ri_ND) + .value("SHR32ri_NF", LIEF::assembly::x86::OPCODE::SHR32ri_NF) + .value("SHR32ri_NF_ND", LIEF::assembly::x86::OPCODE::SHR32ri_NF_ND) + .value("SHR64m1", LIEF::assembly::x86::OPCODE::SHR64m1) + .value("SHR64m1_EVEX", LIEF::assembly::x86::OPCODE::SHR64m1_EVEX) + .value("SHR64m1_ND", LIEF::assembly::x86::OPCODE::SHR64m1_ND) + .value("SHR64m1_NF", LIEF::assembly::x86::OPCODE::SHR64m1_NF) + .value("SHR64m1_NF_ND", LIEF::assembly::x86::OPCODE::SHR64m1_NF_ND) + .value("SHR64mCL", LIEF::assembly::x86::OPCODE::SHR64mCL) + .value("SHR64mCL_EVEX", LIEF::assembly::x86::OPCODE::SHR64mCL_EVEX) + .value("SHR64mCL_ND", LIEF::assembly::x86::OPCODE::SHR64mCL_ND) + .value("SHR64mCL_NF", LIEF::assembly::x86::OPCODE::SHR64mCL_NF) + .value("SHR64mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR64mCL_NF_ND) + .value("SHR64mi", LIEF::assembly::x86::OPCODE::SHR64mi) + .value("SHR64mi_EVEX", LIEF::assembly::x86::OPCODE::SHR64mi_EVEX) + .value("SHR64mi_ND", LIEF::assembly::x86::OPCODE::SHR64mi_ND) + .value("SHR64mi_NF", LIEF::assembly::x86::OPCODE::SHR64mi_NF) + .value("SHR64mi_NF_ND", LIEF::assembly::x86::OPCODE::SHR64mi_NF_ND) + .value("SHR64r1", LIEF::assembly::x86::OPCODE::SHR64r1) + .value("SHR64r1_EVEX", LIEF::assembly::x86::OPCODE::SHR64r1_EVEX) + .value("SHR64r1_ND", LIEF::assembly::x86::OPCODE::SHR64r1_ND) + .value("SHR64r1_NF", LIEF::assembly::x86::OPCODE::SHR64r1_NF) + .value("SHR64r1_NF_ND", LIEF::assembly::x86::OPCODE::SHR64r1_NF_ND) + .value("SHR64rCL", LIEF::assembly::x86::OPCODE::SHR64rCL) + .value("SHR64rCL_EVEX", LIEF::assembly::x86::OPCODE::SHR64rCL_EVEX) + .value("SHR64rCL_ND", LIEF::assembly::x86::OPCODE::SHR64rCL_ND) + .value("SHR64rCL_NF", LIEF::assembly::x86::OPCODE::SHR64rCL_NF) + .value("SHR64rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR64rCL_NF_ND) + .value("SHR64ri", LIEF::assembly::x86::OPCODE::SHR64ri) + .value("SHR64ri_EVEX", LIEF::assembly::x86::OPCODE::SHR64ri_EVEX) + .value("SHR64ri_ND", LIEF::assembly::x86::OPCODE::SHR64ri_ND) + .value("SHR64ri_NF", LIEF::assembly::x86::OPCODE::SHR64ri_NF) + .value("SHR64ri_NF_ND", LIEF::assembly::x86::OPCODE::SHR64ri_NF_ND) + .value("SHR8m1", LIEF::assembly::x86::OPCODE::SHR8m1) + .value("SHR8m1_EVEX", LIEF::assembly::x86::OPCODE::SHR8m1_EVEX) + .value("SHR8m1_ND", LIEF::assembly::x86::OPCODE::SHR8m1_ND) + .value("SHR8m1_NF", LIEF::assembly::x86::OPCODE::SHR8m1_NF) + .value("SHR8m1_NF_ND", LIEF::assembly::x86::OPCODE::SHR8m1_NF_ND) + .value("SHR8mCL", LIEF::assembly::x86::OPCODE::SHR8mCL) + .value("SHR8mCL_EVEX", LIEF::assembly::x86::OPCODE::SHR8mCL_EVEX) + .value("SHR8mCL_ND", LIEF::assembly::x86::OPCODE::SHR8mCL_ND) + .value("SHR8mCL_NF", LIEF::assembly::x86::OPCODE::SHR8mCL_NF) + .value("SHR8mCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR8mCL_NF_ND) + .value("SHR8mi", LIEF::assembly::x86::OPCODE::SHR8mi) + .value("SHR8mi_EVEX", LIEF::assembly::x86::OPCODE::SHR8mi_EVEX) + .value("SHR8mi_ND", LIEF::assembly::x86::OPCODE::SHR8mi_ND) + .value("SHR8mi_NF", LIEF::assembly::x86::OPCODE::SHR8mi_NF) + .value("SHR8mi_NF_ND", LIEF::assembly::x86::OPCODE::SHR8mi_NF_ND) + .value("SHR8r1", LIEF::assembly::x86::OPCODE::SHR8r1) + .value("SHR8r1_EVEX", LIEF::assembly::x86::OPCODE::SHR8r1_EVEX) + .value("SHR8r1_ND", LIEF::assembly::x86::OPCODE::SHR8r1_ND) + .value("SHR8r1_NF", LIEF::assembly::x86::OPCODE::SHR8r1_NF) + .value("SHR8r1_NF_ND", LIEF::assembly::x86::OPCODE::SHR8r1_NF_ND) + .value("SHR8rCL", LIEF::assembly::x86::OPCODE::SHR8rCL) + .value("SHR8rCL_EVEX", LIEF::assembly::x86::OPCODE::SHR8rCL_EVEX) + .value("SHR8rCL_ND", LIEF::assembly::x86::OPCODE::SHR8rCL_ND) + .value("SHR8rCL_NF", LIEF::assembly::x86::OPCODE::SHR8rCL_NF) + .value("SHR8rCL_NF_ND", LIEF::assembly::x86::OPCODE::SHR8rCL_NF_ND) + .value("SHR8ri", LIEF::assembly::x86::OPCODE::SHR8ri) + .value("SHR8ri_EVEX", LIEF::assembly::x86::OPCODE::SHR8ri_EVEX) + .value("SHR8ri_ND", LIEF::assembly::x86::OPCODE::SHR8ri_ND) + .value("SHR8ri_NF", LIEF::assembly::x86::OPCODE::SHR8ri_NF) + .value("SHR8ri_NF_ND", LIEF::assembly::x86::OPCODE::SHR8ri_NF_ND) + .value("SHRD16mrCL", LIEF::assembly::x86::OPCODE::SHRD16mrCL) + .value("SHRD16mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD16mrCL_EVEX) + .value("SHRD16mrCL_ND", LIEF::assembly::x86::OPCODE::SHRD16mrCL_ND) + .value("SHRD16mrCL_NF", LIEF::assembly::x86::OPCODE::SHRD16mrCL_NF) + .value("SHRD16mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD16mrCL_NF_ND) + .value("SHRD16mri8", LIEF::assembly::x86::OPCODE::SHRD16mri8) + .value("SHRD16mri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD16mri8_EVEX) + .value("SHRD16mri8_ND", LIEF::assembly::x86::OPCODE::SHRD16mri8_ND) + .value("SHRD16mri8_NF", LIEF::assembly::x86::OPCODE::SHRD16mri8_NF) + .value("SHRD16mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD16mri8_NF_ND) + .value("SHRD16rrCL", LIEF::assembly::x86::OPCODE::SHRD16rrCL) + .value("SHRD16rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD16rrCL_EVEX) + .value("SHRD16rrCL_ND", LIEF::assembly::x86::OPCODE::SHRD16rrCL_ND) + .value("SHRD16rrCL_NF", LIEF::assembly::x86::OPCODE::SHRD16rrCL_NF) + .value("SHRD16rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD16rrCL_NF_ND) + .value("SHRD16rri8", LIEF::assembly::x86::OPCODE::SHRD16rri8) + .value("SHRD16rri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD16rri8_EVEX) + .value("SHRD16rri8_ND", LIEF::assembly::x86::OPCODE::SHRD16rri8_ND) + .value("SHRD16rri8_NF", LIEF::assembly::x86::OPCODE::SHRD16rri8_NF) + .value("SHRD16rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD16rri8_NF_ND) + .value("SHRD32mrCL", LIEF::assembly::x86::OPCODE::SHRD32mrCL) + .value("SHRD32mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD32mrCL_EVEX) + .value("SHRD32mrCL_ND", LIEF::assembly::x86::OPCODE::SHRD32mrCL_ND) + .value("SHRD32mrCL_NF", LIEF::assembly::x86::OPCODE::SHRD32mrCL_NF) + .value("SHRD32mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD32mrCL_NF_ND) + .value("SHRD32mri8", LIEF::assembly::x86::OPCODE::SHRD32mri8) + .value("SHRD32mri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD32mri8_EVEX) + .value("SHRD32mri8_ND", LIEF::assembly::x86::OPCODE::SHRD32mri8_ND) + .value("SHRD32mri8_NF", LIEF::assembly::x86::OPCODE::SHRD32mri8_NF) + .value("SHRD32mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD32mri8_NF_ND) + .value("SHRD32rrCL", LIEF::assembly::x86::OPCODE::SHRD32rrCL) + .value("SHRD32rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD32rrCL_EVEX) + .value("SHRD32rrCL_ND", LIEF::assembly::x86::OPCODE::SHRD32rrCL_ND) + .value("SHRD32rrCL_NF", LIEF::assembly::x86::OPCODE::SHRD32rrCL_NF) + .value("SHRD32rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD32rrCL_NF_ND) + .value("SHRD32rri8", LIEF::assembly::x86::OPCODE::SHRD32rri8) + .value("SHRD32rri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD32rri8_EVEX) + .value("SHRD32rri8_ND", LIEF::assembly::x86::OPCODE::SHRD32rri8_ND) + .value("SHRD32rri8_NF", LIEF::assembly::x86::OPCODE::SHRD32rri8_NF) + .value("SHRD32rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD32rri8_NF_ND) + .value("SHRD64mrCL", LIEF::assembly::x86::OPCODE::SHRD64mrCL) + .value("SHRD64mrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD64mrCL_EVEX) + .value("SHRD64mrCL_ND", LIEF::assembly::x86::OPCODE::SHRD64mrCL_ND) + .value("SHRD64mrCL_NF", LIEF::assembly::x86::OPCODE::SHRD64mrCL_NF) + .value("SHRD64mrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD64mrCL_NF_ND) + .value("SHRD64mri8", LIEF::assembly::x86::OPCODE::SHRD64mri8) + .value("SHRD64mri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD64mri8_EVEX) + .value("SHRD64mri8_ND", LIEF::assembly::x86::OPCODE::SHRD64mri8_ND) + .value("SHRD64mri8_NF", LIEF::assembly::x86::OPCODE::SHRD64mri8_NF) + .value("SHRD64mri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD64mri8_NF_ND) + .value("SHRD64rrCL", LIEF::assembly::x86::OPCODE::SHRD64rrCL) + .value("SHRD64rrCL_EVEX", LIEF::assembly::x86::OPCODE::SHRD64rrCL_EVEX) + .value("SHRD64rrCL_ND", LIEF::assembly::x86::OPCODE::SHRD64rrCL_ND) + .value("SHRD64rrCL_NF", LIEF::assembly::x86::OPCODE::SHRD64rrCL_NF) + .value("SHRD64rrCL_NF_ND", LIEF::assembly::x86::OPCODE::SHRD64rrCL_NF_ND) + .value("SHRD64rri8", LIEF::assembly::x86::OPCODE::SHRD64rri8) + .value("SHRD64rri8_EVEX", LIEF::assembly::x86::OPCODE::SHRD64rri8_EVEX) + .value("SHRD64rri8_ND", LIEF::assembly::x86::OPCODE::SHRD64rri8_ND) + .value("SHRD64rri8_NF", LIEF::assembly::x86::OPCODE::SHRD64rri8_NF) + .value("SHRD64rri8_NF_ND", LIEF::assembly::x86::OPCODE::SHRD64rri8_NF_ND) + .value("SHRX32rm", LIEF::assembly::x86::OPCODE::SHRX32rm) + .value("SHRX32rm_EVEX", LIEF::assembly::x86::OPCODE::SHRX32rm_EVEX) + .value("SHRX32rr", LIEF::assembly::x86::OPCODE::SHRX32rr) + .value("SHRX32rr_EVEX", LIEF::assembly::x86::OPCODE::SHRX32rr_EVEX) + .value("SHRX64rm", LIEF::assembly::x86::OPCODE::SHRX64rm) + .value("SHRX64rm_EVEX", LIEF::assembly::x86::OPCODE::SHRX64rm_EVEX) + .value("SHRX64rr", LIEF::assembly::x86::OPCODE::SHRX64rr) + .value("SHRX64rr_EVEX", LIEF::assembly::x86::OPCODE::SHRX64rr_EVEX) + .value("SHUFPDrmi", LIEF::assembly::x86::OPCODE::SHUFPDrmi) + .value("SHUFPDrri", LIEF::assembly::x86::OPCODE::SHUFPDrri) + .value("SHUFPSrmi", LIEF::assembly::x86::OPCODE::SHUFPSrmi) + .value("SHUFPSrri", LIEF::assembly::x86::OPCODE::SHUFPSrri) + .value("SIDT16m", LIEF::assembly::x86::OPCODE::SIDT16m) + .value("SIDT32m", LIEF::assembly::x86::OPCODE::SIDT32m) + .value("SIDT64m", LIEF::assembly::x86::OPCODE::SIDT64m) + .value("SKINIT", LIEF::assembly::x86::OPCODE::SKINIT) + .value("SLDT16m", LIEF::assembly::x86::OPCODE::SLDT16m) + .value("SLDT16r", LIEF::assembly::x86::OPCODE::SLDT16r) + .value("SLDT32r", LIEF::assembly::x86::OPCODE::SLDT32r) + .value("SLDT64r", LIEF::assembly::x86::OPCODE::SLDT64r) + .value("SLWPCB", LIEF::assembly::x86::OPCODE::SLWPCB) + .value("SLWPCB64", LIEF::assembly::x86::OPCODE::SLWPCB64) + .value("SMSW16m", LIEF::assembly::x86::OPCODE::SMSW16m) + .value("SMSW16r", LIEF::assembly::x86::OPCODE::SMSW16r) + .value("SMSW32r", LIEF::assembly::x86::OPCODE::SMSW32r) + .value("SMSW64r", LIEF::assembly::x86::OPCODE::SMSW64r) + .value("SQRTPDm", LIEF::assembly::x86::OPCODE::SQRTPDm) + .value("SQRTPDr", LIEF::assembly::x86::OPCODE::SQRTPDr) + .value("SQRTPSm", LIEF::assembly::x86::OPCODE::SQRTPSm) + .value("SQRTPSr", LIEF::assembly::x86::OPCODE::SQRTPSr) + .value("SQRTSDm", LIEF::assembly::x86::OPCODE::SQRTSDm) + .value("SQRTSDm_Int", LIEF::assembly::x86::OPCODE::SQRTSDm_Int) + .value("SQRTSDr", LIEF::assembly::x86::OPCODE::SQRTSDr) + .value("SQRTSDr_Int", LIEF::assembly::x86::OPCODE::SQRTSDr_Int) + .value("SQRTSSm", LIEF::assembly::x86::OPCODE::SQRTSSm) + .value("SQRTSSm_Int", LIEF::assembly::x86::OPCODE::SQRTSSm_Int) + .value("SQRTSSr", LIEF::assembly::x86::OPCODE::SQRTSSr) + .value("SQRTSSr_Int", LIEF::assembly::x86::OPCODE::SQRTSSr_Int) + .value("SQRT_F", LIEF::assembly::x86::OPCODE::SQRT_F) + .value("SQRT_Fp32", LIEF::assembly::x86::OPCODE::SQRT_Fp32) + .value("SQRT_Fp64", LIEF::assembly::x86::OPCODE::SQRT_Fp64) + .value("SQRT_Fp80", LIEF::assembly::x86::OPCODE::SQRT_Fp80) + .value("SS_PREFIX", LIEF::assembly::x86::OPCODE::SS_PREFIX) + .value("STAC", LIEF::assembly::x86::OPCODE::STAC) + .value("STACKALLOC_W_PROBING", LIEF::assembly::x86::OPCODE::STACKALLOC_W_PROBING) + .value("STC", LIEF::assembly::x86::OPCODE::STC) + .value("STD", LIEF::assembly::x86::OPCODE::STD) + .value("STGI", LIEF::assembly::x86::OPCODE::STGI) + .value("STI", LIEF::assembly::x86::OPCODE::STI) + .value("STMXCSR", LIEF::assembly::x86::OPCODE::STMXCSR) + .value("STOSB", LIEF::assembly::x86::OPCODE::STOSB) + .value("STOSL", LIEF::assembly::x86::OPCODE::STOSL) + .value("STOSQ", LIEF::assembly::x86::OPCODE::STOSQ) + .value("STOSW", LIEF::assembly::x86::OPCODE::STOSW) + .value("STR16r", LIEF::assembly::x86::OPCODE::STR16r) + .value("STR32r", LIEF::assembly::x86::OPCODE::STR32r) + .value("STR64r", LIEF::assembly::x86::OPCODE::STR64r) + .value("STRm", LIEF::assembly::x86::OPCODE::STRm) + .value("STTILECFG", LIEF::assembly::x86::OPCODE::STTILECFG) + .value("STTILECFG_EVEX", LIEF::assembly::x86::OPCODE::STTILECFG_EVEX) + .value("STUI", LIEF::assembly::x86::OPCODE::STUI) + .value("ST_F32m", LIEF::assembly::x86::OPCODE::ST_F32m) + .value("ST_F64m", LIEF::assembly::x86::OPCODE::ST_F64m) + .value("ST_FP32m", LIEF::assembly::x86::OPCODE::ST_FP32m) + .value("ST_FP64m", LIEF::assembly::x86::OPCODE::ST_FP64m) + .value("ST_FP80m", LIEF::assembly::x86::OPCODE::ST_FP80m) + .value("ST_FPrr", LIEF::assembly::x86::OPCODE::ST_FPrr) + .value("ST_Fp32m", LIEF::assembly::x86::OPCODE::ST_Fp32m) + .value("ST_Fp64m", LIEF::assembly::x86::OPCODE::ST_Fp64m) + .value("ST_Fp64m32", LIEF::assembly::x86::OPCODE::ST_Fp64m32) + .value("ST_Fp80m32", LIEF::assembly::x86::OPCODE::ST_Fp80m32) + .value("ST_Fp80m64", LIEF::assembly::x86::OPCODE::ST_Fp80m64) + .value("ST_FpP32m", LIEF::assembly::x86::OPCODE::ST_FpP32m) + .value("ST_FpP64m", LIEF::assembly::x86::OPCODE::ST_FpP64m) + .value("ST_FpP64m32", LIEF::assembly::x86::OPCODE::ST_FpP64m32) + .value("ST_FpP80m", LIEF::assembly::x86::OPCODE::ST_FpP80m) + .value("ST_FpP80m32", LIEF::assembly::x86::OPCODE::ST_FpP80m32) + .value("ST_FpP80m64", LIEF::assembly::x86::OPCODE::ST_FpP80m64) + .value("ST_Frr", LIEF::assembly::x86::OPCODE::ST_Frr) + .value("SUB16i16", LIEF::assembly::x86::OPCODE::SUB16i16) + .value("SUB16mi", LIEF::assembly::x86::OPCODE::SUB16mi) + .value("SUB16mi8", LIEF::assembly::x86::OPCODE::SUB16mi8) + .value("SUB16mi8_EVEX", LIEF::assembly::x86::OPCODE::SUB16mi8_EVEX) + .value("SUB16mi8_ND", LIEF::assembly::x86::OPCODE::SUB16mi8_ND) + .value("SUB16mi8_NF", LIEF::assembly::x86::OPCODE::SUB16mi8_NF) + .value("SUB16mi8_NF_ND", LIEF::assembly::x86::OPCODE::SUB16mi8_NF_ND) + .value("SUB16mi_EVEX", LIEF::assembly::x86::OPCODE::SUB16mi_EVEX) + .value("SUB16mi_ND", LIEF::assembly::x86::OPCODE::SUB16mi_ND) + .value("SUB16mi_NF", LIEF::assembly::x86::OPCODE::SUB16mi_NF) + .value("SUB16mi_NF_ND", LIEF::assembly::x86::OPCODE::SUB16mi_NF_ND) + .value("SUB16mr", LIEF::assembly::x86::OPCODE::SUB16mr) + .value("SUB16mr_EVEX", LIEF::assembly::x86::OPCODE::SUB16mr_EVEX) + .value("SUB16mr_ND", LIEF::assembly::x86::OPCODE::SUB16mr_ND) + .value("SUB16mr_NF", LIEF::assembly::x86::OPCODE::SUB16mr_NF) + .value("SUB16mr_NF_ND", LIEF::assembly::x86::OPCODE::SUB16mr_NF_ND) + .value("SUB16ri", LIEF::assembly::x86::OPCODE::SUB16ri) + .value("SUB16ri8", LIEF::assembly::x86::OPCODE::SUB16ri8) + .value("SUB16ri8_EVEX", LIEF::assembly::x86::OPCODE::SUB16ri8_EVEX) + .value("SUB16ri8_ND", LIEF::assembly::x86::OPCODE::SUB16ri8_ND) + .value("SUB16ri8_NF", LIEF::assembly::x86::OPCODE::SUB16ri8_NF) + .value("SUB16ri8_NF_ND", LIEF::assembly::x86::OPCODE::SUB16ri8_NF_ND) + .value("SUB16ri_EVEX", LIEF::assembly::x86::OPCODE::SUB16ri_EVEX) + .value("SUB16ri_ND", LIEF::assembly::x86::OPCODE::SUB16ri_ND) + .value("SUB16ri_NF", LIEF::assembly::x86::OPCODE::SUB16ri_NF) + .value("SUB16ri_NF_ND", LIEF::assembly::x86::OPCODE::SUB16ri_NF_ND) + .value("SUB16rm", LIEF::assembly::x86::OPCODE::SUB16rm) + .value("SUB16rm_EVEX", LIEF::assembly::x86::OPCODE::SUB16rm_EVEX) + .value("SUB16rm_ND", LIEF::assembly::x86::OPCODE::SUB16rm_ND) + .value("SUB16rm_NF", LIEF::assembly::x86::OPCODE::SUB16rm_NF) + .value("SUB16rm_NF_ND", LIEF::assembly::x86::OPCODE::SUB16rm_NF_ND) + .value("SUB16rr", LIEF::assembly::x86::OPCODE::SUB16rr) + .value("SUB16rr_EVEX", LIEF::assembly::x86::OPCODE::SUB16rr_EVEX) + .value("SUB16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SUB16rr_EVEX_REV) + .value("SUB16rr_ND", LIEF::assembly::x86::OPCODE::SUB16rr_ND) + .value("SUB16rr_ND_REV", LIEF::assembly::x86::OPCODE::SUB16rr_ND_REV) + .value("SUB16rr_NF", LIEF::assembly::x86::OPCODE::SUB16rr_NF) + .value("SUB16rr_NF_ND", LIEF::assembly::x86::OPCODE::SUB16rr_NF_ND) + .value("SUB16rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::SUB16rr_NF_ND_REV) + .value("SUB16rr_NF_REV", LIEF::assembly::x86::OPCODE::SUB16rr_NF_REV) + .value("SUB16rr_REV", LIEF::assembly::x86::OPCODE::SUB16rr_REV) + .value("SUB32i32", LIEF::assembly::x86::OPCODE::SUB32i32) + .value("SUB32mi", LIEF::assembly::x86::OPCODE::SUB32mi) + .value("SUB32mi8", LIEF::assembly::x86::OPCODE::SUB32mi8) + .value("SUB32mi8_EVEX", LIEF::assembly::x86::OPCODE::SUB32mi8_EVEX) + .value("SUB32mi8_ND", LIEF::assembly::x86::OPCODE::SUB32mi8_ND) + .value("SUB32mi8_NF", LIEF::assembly::x86::OPCODE::SUB32mi8_NF) + .value("SUB32mi8_NF_ND", LIEF::assembly::x86::OPCODE::SUB32mi8_NF_ND) + .value("SUB32mi_EVEX", LIEF::assembly::x86::OPCODE::SUB32mi_EVEX) + .value("SUB32mi_ND", LIEF::assembly::x86::OPCODE::SUB32mi_ND) + .value("SUB32mi_NF", LIEF::assembly::x86::OPCODE::SUB32mi_NF) + .value("SUB32mi_NF_ND", LIEF::assembly::x86::OPCODE::SUB32mi_NF_ND) + .value("SUB32mr", LIEF::assembly::x86::OPCODE::SUB32mr) + .value("SUB32mr_EVEX", LIEF::assembly::x86::OPCODE::SUB32mr_EVEX) + .value("SUB32mr_ND", LIEF::assembly::x86::OPCODE::SUB32mr_ND) + .value("SUB32mr_NF", LIEF::assembly::x86::OPCODE::SUB32mr_NF) + .value("SUB32mr_NF_ND", LIEF::assembly::x86::OPCODE::SUB32mr_NF_ND) + .value("SUB32ri", LIEF::assembly::x86::OPCODE::SUB32ri) + .value("SUB32ri8", LIEF::assembly::x86::OPCODE::SUB32ri8) + .value("SUB32ri8_EVEX", LIEF::assembly::x86::OPCODE::SUB32ri8_EVEX) + .value("SUB32ri8_ND", LIEF::assembly::x86::OPCODE::SUB32ri8_ND) + .value("SUB32ri8_NF", LIEF::assembly::x86::OPCODE::SUB32ri8_NF) + .value("SUB32ri8_NF_ND", LIEF::assembly::x86::OPCODE::SUB32ri8_NF_ND) + .value("SUB32ri_EVEX", LIEF::assembly::x86::OPCODE::SUB32ri_EVEX) + .value("SUB32ri_ND", LIEF::assembly::x86::OPCODE::SUB32ri_ND) + .value("SUB32ri_NF", LIEF::assembly::x86::OPCODE::SUB32ri_NF) + .value("SUB32ri_NF_ND", LIEF::assembly::x86::OPCODE::SUB32ri_NF_ND) + .value("SUB32rm", LIEF::assembly::x86::OPCODE::SUB32rm) + .value("SUB32rm_EVEX", LIEF::assembly::x86::OPCODE::SUB32rm_EVEX) + .value("SUB32rm_ND", LIEF::assembly::x86::OPCODE::SUB32rm_ND) + .value("SUB32rm_NF", LIEF::assembly::x86::OPCODE::SUB32rm_NF) + .value("SUB32rm_NF_ND", LIEF::assembly::x86::OPCODE::SUB32rm_NF_ND) + .value("SUB32rr", LIEF::assembly::x86::OPCODE::SUB32rr) + .value("SUB32rr_EVEX", LIEF::assembly::x86::OPCODE::SUB32rr_EVEX) + .value("SUB32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SUB32rr_EVEX_REV) + .value("SUB32rr_ND", LIEF::assembly::x86::OPCODE::SUB32rr_ND) + .value("SUB32rr_ND_REV", LIEF::assembly::x86::OPCODE::SUB32rr_ND_REV) + .value("SUB32rr_NF", LIEF::assembly::x86::OPCODE::SUB32rr_NF); + opcodes.value("SUB32rr_NF_ND", LIEF::assembly::x86::OPCODE::SUB32rr_NF_ND) + .value("SUB32rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::SUB32rr_NF_ND_REV) + .value("SUB32rr_NF_REV", LIEF::assembly::x86::OPCODE::SUB32rr_NF_REV) + .value("SUB32rr_REV", LIEF::assembly::x86::OPCODE::SUB32rr_REV) + .value("SUB64i32", LIEF::assembly::x86::OPCODE::SUB64i32) + .value("SUB64mi32", LIEF::assembly::x86::OPCODE::SUB64mi32) + .value("SUB64mi32_EVEX", LIEF::assembly::x86::OPCODE::SUB64mi32_EVEX) + .value("SUB64mi32_ND", LIEF::assembly::x86::OPCODE::SUB64mi32_ND) + .value("SUB64mi32_NF", LIEF::assembly::x86::OPCODE::SUB64mi32_NF) + .value("SUB64mi32_NF_ND", LIEF::assembly::x86::OPCODE::SUB64mi32_NF_ND) + .value("SUB64mi8", LIEF::assembly::x86::OPCODE::SUB64mi8) + .value("SUB64mi8_EVEX", LIEF::assembly::x86::OPCODE::SUB64mi8_EVEX) + .value("SUB64mi8_ND", LIEF::assembly::x86::OPCODE::SUB64mi8_ND) + .value("SUB64mi8_NF", LIEF::assembly::x86::OPCODE::SUB64mi8_NF) + .value("SUB64mi8_NF_ND", LIEF::assembly::x86::OPCODE::SUB64mi8_NF_ND) + .value("SUB64mr", LIEF::assembly::x86::OPCODE::SUB64mr) + .value("SUB64mr_EVEX", LIEF::assembly::x86::OPCODE::SUB64mr_EVEX) + .value("SUB64mr_ND", LIEF::assembly::x86::OPCODE::SUB64mr_ND) + .value("SUB64mr_NF", LIEF::assembly::x86::OPCODE::SUB64mr_NF) + .value("SUB64mr_NF_ND", LIEF::assembly::x86::OPCODE::SUB64mr_NF_ND) + .value("SUB64ri32", LIEF::assembly::x86::OPCODE::SUB64ri32) + .value("SUB64ri32_EVEX", LIEF::assembly::x86::OPCODE::SUB64ri32_EVEX) + .value("SUB64ri32_ND", LIEF::assembly::x86::OPCODE::SUB64ri32_ND) + .value("SUB64ri32_NF", LIEF::assembly::x86::OPCODE::SUB64ri32_NF) + .value("SUB64ri32_NF_ND", LIEF::assembly::x86::OPCODE::SUB64ri32_NF_ND) + .value("SUB64ri8", LIEF::assembly::x86::OPCODE::SUB64ri8) + .value("SUB64ri8_EVEX", LIEF::assembly::x86::OPCODE::SUB64ri8_EVEX) + .value("SUB64ri8_ND", LIEF::assembly::x86::OPCODE::SUB64ri8_ND) + .value("SUB64ri8_NF", LIEF::assembly::x86::OPCODE::SUB64ri8_NF) + .value("SUB64ri8_NF_ND", LIEF::assembly::x86::OPCODE::SUB64ri8_NF_ND) + .value("SUB64rm", LIEF::assembly::x86::OPCODE::SUB64rm) + .value("SUB64rm_EVEX", LIEF::assembly::x86::OPCODE::SUB64rm_EVEX) + .value("SUB64rm_ND", LIEF::assembly::x86::OPCODE::SUB64rm_ND) + .value("SUB64rm_NF", LIEF::assembly::x86::OPCODE::SUB64rm_NF) + .value("SUB64rm_NF_ND", LIEF::assembly::x86::OPCODE::SUB64rm_NF_ND) + .value("SUB64rr", LIEF::assembly::x86::OPCODE::SUB64rr) + .value("SUB64rr_EVEX", LIEF::assembly::x86::OPCODE::SUB64rr_EVEX) + .value("SUB64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SUB64rr_EVEX_REV) + .value("SUB64rr_ND", LIEF::assembly::x86::OPCODE::SUB64rr_ND) + .value("SUB64rr_ND_REV", LIEF::assembly::x86::OPCODE::SUB64rr_ND_REV) + .value("SUB64rr_NF", LIEF::assembly::x86::OPCODE::SUB64rr_NF) + .value("SUB64rr_NF_ND", LIEF::assembly::x86::OPCODE::SUB64rr_NF_ND) + .value("SUB64rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::SUB64rr_NF_ND_REV) + .value("SUB64rr_NF_REV", LIEF::assembly::x86::OPCODE::SUB64rr_NF_REV) + .value("SUB64rr_REV", LIEF::assembly::x86::OPCODE::SUB64rr_REV) + .value("SUB8i8", LIEF::assembly::x86::OPCODE::SUB8i8) + .value("SUB8mi", LIEF::assembly::x86::OPCODE::SUB8mi) + .value("SUB8mi8", LIEF::assembly::x86::OPCODE::SUB8mi8) + .value("SUB8mi_EVEX", LIEF::assembly::x86::OPCODE::SUB8mi_EVEX) + .value("SUB8mi_ND", LIEF::assembly::x86::OPCODE::SUB8mi_ND) + .value("SUB8mi_NF", LIEF::assembly::x86::OPCODE::SUB8mi_NF) + .value("SUB8mi_NF_ND", LIEF::assembly::x86::OPCODE::SUB8mi_NF_ND) + .value("SUB8mr", LIEF::assembly::x86::OPCODE::SUB8mr) + .value("SUB8mr_EVEX", LIEF::assembly::x86::OPCODE::SUB8mr_EVEX) + .value("SUB8mr_ND", LIEF::assembly::x86::OPCODE::SUB8mr_ND) + .value("SUB8mr_NF", LIEF::assembly::x86::OPCODE::SUB8mr_NF) + .value("SUB8mr_NF_ND", LIEF::assembly::x86::OPCODE::SUB8mr_NF_ND) + .value("SUB8ri", LIEF::assembly::x86::OPCODE::SUB8ri) + .value("SUB8ri8", LIEF::assembly::x86::OPCODE::SUB8ri8) + .value("SUB8ri_EVEX", LIEF::assembly::x86::OPCODE::SUB8ri_EVEX) + .value("SUB8ri_ND", LIEF::assembly::x86::OPCODE::SUB8ri_ND) + .value("SUB8ri_NF", LIEF::assembly::x86::OPCODE::SUB8ri_NF) + .value("SUB8ri_NF_ND", LIEF::assembly::x86::OPCODE::SUB8ri_NF_ND) + .value("SUB8rm", LIEF::assembly::x86::OPCODE::SUB8rm) + .value("SUB8rm_EVEX", LIEF::assembly::x86::OPCODE::SUB8rm_EVEX) + .value("SUB8rm_ND", LIEF::assembly::x86::OPCODE::SUB8rm_ND) + .value("SUB8rm_NF", LIEF::assembly::x86::OPCODE::SUB8rm_NF) + .value("SUB8rm_NF_ND", LIEF::assembly::x86::OPCODE::SUB8rm_NF_ND) + .value("SUB8rr", LIEF::assembly::x86::OPCODE::SUB8rr) + .value("SUB8rr_EVEX", LIEF::assembly::x86::OPCODE::SUB8rr_EVEX) + .value("SUB8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::SUB8rr_EVEX_REV) + .value("SUB8rr_ND", LIEF::assembly::x86::OPCODE::SUB8rr_ND) + .value("SUB8rr_ND_REV", LIEF::assembly::x86::OPCODE::SUB8rr_ND_REV) + .value("SUB8rr_NF", LIEF::assembly::x86::OPCODE::SUB8rr_NF) + .value("SUB8rr_NF_ND", LIEF::assembly::x86::OPCODE::SUB8rr_NF_ND) + .value("SUB8rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::SUB8rr_NF_ND_REV) + .value("SUB8rr_NF_REV", LIEF::assembly::x86::OPCODE::SUB8rr_NF_REV) + .value("SUB8rr_REV", LIEF::assembly::x86::OPCODE::SUB8rr_REV) + .value("SUBPDrm", LIEF::assembly::x86::OPCODE::SUBPDrm) + .value("SUBPDrr", LIEF::assembly::x86::OPCODE::SUBPDrr) + .value("SUBPSrm", LIEF::assembly::x86::OPCODE::SUBPSrm) + .value("SUBPSrr", LIEF::assembly::x86::OPCODE::SUBPSrr) + .value("SUBR_F32m", LIEF::assembly::x86::OPCODE::SUBR_F32m) + .value("SUBR_F64m", LIEF::assembly::x86::OPCODE::SUBR_F64m) + .value("SUBR_FI16m", LIEF::assembly::x86::OPCODE::SUBR_FI16m) + .value("SUBR_FI32m", LIEF::assembly::x86::OPCODE::SUBR_FI32m) + .value("SUBR_FPrST0", LIEF::assembly::x86::OPCODE::SUBR_FPrST0) + .value("SUBR_FST0r", LIEF::assembly::x86::OPCODE::SUBR_FST0r) + .value("SUBR_Fp32m", LIEF::assembly::x86::OPCODE::SUBR_Fp32m) + .value("SUBR_Fp64m", LIEF::assembly::x86::OPCODE::SUBR_Fp64m) + .value("SUBR_Fp64m32", LIEF::assembly::x86::OPCODE::SUBR_Fp64m32) + .value("SUBR_Fp80m32", LIEF::assembly::x86::OPCODE::SUBR_Fp80m32) + .value("SUBR_Fp80m64", LIEF::assembly::x86::OPCODE::SUBR_Fp80m64) + .value("SUBR_FpI16m32", LIEF::assembly::x86::OPCODE::SUBR_FpI16m32) + .value("SUBR_FpI16m64", LIEF::assembly::x86::OPCODE::SUBR_FpI16m64) + .value("SUBR_FpI16m80", LIEF::assembly::x86::OPCODE::SUBR_FpI16m80) + .value("SUBR_FpI32m32", LIEF::assembly::x86::OPCODE::SUBR_FpI32m32) + .value("SUBR_FpI32m64", LIEF::assembly::x86::OPCODE::SUBR_FpI32m64) + .value("SUBR_FpI32m80", LIEF::assembly::x86::OPCODE::SUBR_FpI32m80) + .value("SUBR_FrST0", LIEF::assembly::x86::OPCODE::SUBR_FrST0) + .value("SUBSDrm", LIEF::assembly::x86::OPCODE::SUBSDrm) + .value("SUBSDrm_Int", LIEF::assembly::x86::OPCODE::SUBSDrm_Int) + .value("SUBSDrr", LIEF::assembly::x86::OPCODE::SUBSDrr) + .value("SUBSDrr_Int", LIEF::assembly::x86::OPCODE::SUBSDrr_Int) + .value("SUBSSrm", LIEF::assembly::x86::OPCODE::SUBSSrm) + .value("SUBSSrm_Int", LIEF::assembly::x86::OPCODE::SUBSSrm_Int) + .value("SUBSSrr", LIEF::assembly::x86::OPCODE::SUBSSrr) + .value("SUBSSrr_Int", LIEF::assembly::x86::OPCODE::SUBSSrr_Int) + .value("SUB_F32m", LIEF::assembly::x86::OPCODE::SUB_F32m) + .value("SUB_F64m", LIEF::assembly::x86::OPCODE::SUB_F64m) + .value("SUB_FI16m", LIEF::assembly::x86::OPCODE::SUB_FI16m) + .value("SUB_FI32m", LIEF::assembly::x86::OPCODE::SUB_FI32m) + .value("SUB_FPrST0", LIEF::assembly::x86::OPCODE::SUB_FPrST0) + .value("SUB_FST0r", LIEF::assembly::x86::OPCODE::SUB_FST0r) + .value("SUB_Fp32", LIEF::assembly::x86::OPCODE::SUB_Fp32) + .value("SUB_Fp32m", LIEF::assembly::x86::OPCODE::SUB_Fp32m) + .value("SUB_Fp64", LIEF::assembly::x86::OPCODE::SUB_Fp64) + .value("SUB_Fp64m", LIEF::assembly::x86::OPCODE::SUB_Fp64m) + .value("SUB_Fp64m32", LIEF::assembly::x86::OPCODE::SUB_Fp64m32) + .value("SUB_Fp80", LIEF::assembly::x86::OPCODE::SUB_Fp80) + .value("SUB_Fp80m32", LIEF::assembly::x86::OPCODE::SUB_Fp80m32) + .value("SUB_Fp80m64", LIEF::assembly::x86::OPCODE::SUB_Fp80m64) + .value("SUB_FpI16m32", LIEF::assembly::x86::OPCODE::SUB_FpI16m32) + .value("SUB_FpI16m64", LIEF::assembly::x86::OPCODE::SUB_FpI16m64) + .value("SUB_FpI16m80", LIEF::assembly::x86::OPCODE::SUB_FpI16m80) + .value("SUB_FpI32m32", LIEF::assembly::x86::OPCODE::SUB_FpI32m32) + .value("SUB_FpI32m64", LIEF::assembly::x86::OPCODE::SUB_FpI32m64) + .value("SUB_FpI32m80", LIEF::assembly::x86::OPCODE::SUB_FpI32m80) + .value("SUB_FrST0", LIEF::assembly::x86::OPCODE::SUB_FrST0) + .value("SWAPGS", LIEF::assembly::x86::OPCODE::SWAPGS) + .value("SYSCALL", LIEF::assembly::x86::OPCODE::SYSCALL) + .value("SYSENTER", LIEF::assembly::x86::OPCODE::SYSENTER) + .value("SYSEXIT", LIEF::assembly::x86::OPCODE::SYSEXIT) + .value("SYSEXIT64", LIEF::assembly::x86::OPCODE::SYSEXIT64) + .value("SYSRET", LIEF::assembly::x86::OPCODE::SYSRET) + .value("SYSRET64", LIEF::assembly::x86::OPCODE::SYSRET64) + .value("T1MSKC32rm", LIEF::assembly::x86::OPCODE::T1MSKC32rm) + .value("T1MSKC32rr", LIEF::assembly::x86::OPCODE::T1MSKC32rr) + .value("T1MSKC64rm", LIEF::assembly::x86::OPCODE::T1MSKC64rm) + .value("T1MSKC64rr", LIEF::assembly::x86::OPCODE::T1MSKC64rr) + .value("TAILJMPd", LIEF::assembly::x86::OPCODE::TAILJMPd) + .value("TAILJMPd64", LIEF::assembly::x86::OPCODE::TAILJMPd64) + .value("TAILJMPd64_CC", LIEF::assembly::x86::OPCODE::TAILJMPd64_CC) + .value("TAILJMPd_CC", LIEF::assembly::x86::OPCODE::TAILJMPd_CC) + .value("TAILJMPm", LIEF::assembly::x86::OPCODE::TAILJMPm) + .value("TAILJMPm64", LIEF::assembly::x86::OPCODE::TAILJMPm64) + .value("TAILJMPm64_REX", LIEF::assembly::x86::OPCODE::TAILJMPm64_REX) + .value("TAILJMPr", LIEF::assembly::x86::OPCODE::TAILJMPr) + .value("TAILJMPr64", LIEF::assembly::x86::OPCODE::TAILJMPr64) + .value("TAILJMPr64_REX", LIEF::assembly::x86::OPCODE::TAILJMPr64_REX) + .value("TCMMIMFP16PS", LIEF::assembly::x86::OPCODE::TCMMIMFP16PS) + .value("TCMMRLFP16PS", LIEF::assembly::x86::OPCODE::TCMMRLFP16PS) + .value("TCRETURN_HIPE32ri", LIEF::assembly::x86::OPCODE::TCRETURN_HIPE32ri) + .value("TCRETURN_WIN64ri", LIEF::assembly::x86::OPCODE::TCRETURN_WIN64ri) + .value("TCRETURN_WINmi64", LIEF::assembly::x86::OPCODE::TCRETURN_WINmi64) + .value("TCRETURNdi", LIEF::assembly::x86::OPCODE::TCRETURNdi) + .value("TCRETURNdi64", LIEF::assembly::x86::OPCODE::TCRETURNdi64) + .value("TCRETURNdi64cc", LIEF::assembly::x86::OPCODE::TCRETURNdi64cc) + .value("TCRETURNdicc", LIEF::assembly::x86::OPCODE::TCRETURNdicc) + .value("TCRETURNmi", LIEF::assembly::x86::OPCODE::TCRETURNmi) + .value("TCRETURNmi64", LIEF::assembly::x86::OPCODE::TCRETURNmi64) + .value("TCRETURNri", LIEF::assembly::x86::OPCODE::TCRETURNri) + .value("TCRETURNri64", LIEF::assembly::x86::OPCODE::TCRETURNri64) + .value("TCRETURNri64_ImpCall", LIEF::assembly::x86::OPCODE::TCRETURNri64_ImpCall) + .value("TCVTROWD2PSrte", LIEF::assembly::x86::OPCODE::TCVTROWD2PSrte) + .value("TCVTROWD2PSrti", LIEF::assembly::x86::OPCODE::TCVTROWD2PSrti) + .value("TCVTROWPS2BF16Hrte", LIEF::assembly::x86::OPCODE::TCVTROWPS2BF16Hrte) + .value("TCVTROWPS2BF16Hrti", LIEF::assembly::x86::OPCODE::TCVTROWPS2BF16Hrti) + .value("TCVTROWPS2BF16Lrte", LIEF::assembly::x86::OPCODE::TCVTROWPS2BF16Lrte) + .value("TCVTROWPS2BF16Lrti", LIEF::assembly::x86::OPCODE::TCVTROWPS2BF16Lrti) + .value("TCVTROWPS2PHHrte", LIEF::assembly::x86::OPCODE::TCVTROWPS2PHHrte) + .value("TCVTROWPS2PHHrti", LIEF::assembly::x86::OPCODE::TCVTROWPS2PHHrti) + .value("TCVTROWPS2PHLrte", LIEF::assembly::x86::OPCODE::TCVTROWPS2PHLrte) + .value("TCVTROWPS2PHLrti", LIEF::assembly::x86::OPCODE::TCVTROWPS2PHLrti) + .value("TDCALL", LIEF::assembly::x86::OPCODE::TDCALL) + .value("TDPBF16PS", LIEF::assembly::x86::OPCODE::TDPBF16PS) + .value("TDPBF8PS", LIEF::assembly::x86::OPCODE::TDPBF8PS) + .value("TDPBHF8PS", LIEF::assembly::x86::OPCODE::TDPBHF8PS) + .value("TDPBSSD", LIEF::assembly::x86::OPCODE::TDPBSSD) + .value("TDPBSUD", LIEF::assembly::x86::OPCODE::TDPBSUD) + .value("TDPBUSD", LIEF::assembly::x86::OPCODE::TDPBUSD) + .value("TDPBUUD", LIEF::assembly::x86::OPCODE::TDPBUUD) + .value("TDPFP16PS", LIEF::assembly::x86::OPCODE::TDPFP16PS) + .value("TDPHBF8PS", LIEF::assembly::x86::OPCODE::TDPHBF8PS) + .value("TDPHF8PS", LIEF::assembly::x86::OPCODE::TDPHF8PS) + .value("TEST16i16", LIEF::assembly::x86::OPCODE::TEST16i16) + .value("TEST16mi", LIEF::assembly::x86::OPCODE::TEST16mi) + .value("TEST16mr", LIEF::assembly::x86::OPCODE::TEST16mr) + .value("TEST16ri", LIEF::assembly::x86::OPCODE::TEST16ri) + .value("TEST16rr", LIEF::assembly::x86::OPCODE::TEST16rr) + .value("TEST32i32", LIEF::assembly::x86::OPCODE::TEST32i32) + .value("TEST32mi", LIEF::assembly::x86::OPCODE::TEST32mi) + .value("TEST32mr", LIEF::assembly::x86::OPCODE::TEST32mr) + .value("TEST32ri", LIEF::assembly::x86::OPCODE::TEST32ri) + .value("TEST32rr", LIEF::assembly::x86::OPCODE::TEST32rr) + .value("TEST64i32", LIEF::assembly::x86::OPCODE::TEST64i32) + .value("TEST64mi32", LIEF::assembly::x86::OPCODE::TEST64mi32) + .value("TEST64mr", LIEF::assembly::x86::OPCODE::TEST64mr) + .value("TEST64ri32", LIEF::assembly::x86::OPCODE::TEST64ri32) + .value("TEST64rr", LIEF::assembly::x86::OPCODE::TEST64rr) + .value("TEST8i8", LIEF::assembly::x86::OPCODE::TEST8i8) + .value("TEST8mi", LIEF::assembly::x86::OPCODE::TEST8mi) + .value("TEST8mr", LIEF::assembly::x86::OPCODE::TEST8mr) + .value("TEST8ri", LIEF::assembly::x86::OPCODE::TEST8ri) + .value("TEST8rr", LIEF::assembly::x86::OPCODE::TEST8rr) + .value("TESTUI", LIEF::assembly::x86::OPCODE::TESTUI) + .value("TILELOADD", LIEF::assembly::x86::OPCODE::TILELOADD) + .value("TILELOADDRS", LIEF::assembly::x86::OPCODE::TILELOADDRS) + .value("TILELOADDRST1", LIEF::assembly::x86::OPCODE::TILELOADDRST1) + .value("TILELOADDRST1_EVEX", LIEF::assembly::x86::OPCODE::TILELOADDRST1_EVEX) + .value("TILELOADDRS_EVEX", LIEF::assembly::x86::OPCODE::TILELOADDRS_EVEX) + .value("TILELOADDT1", LIEF::assembly::x86::OPCODE::TILELOADDT1) + .value("TILELOADDT1_EVEX", LIEF::assembly::x86::OPCODE::TILELOADDT1_EVEX) + .value("TILELOADD_EVEX", LIEF::assembly::x86::OPCODE::TILELOADD_EVEX) + .value("TILEMOVROWrte", LIEF::assembly::x86::OPCODE::TILEMOVROWrte) + .value("TILEMOVROWrti", LIEF::assembly::x86::OPCODE::TILEMOVROWrti) + .value("TILERELEASE", LIEF::assembly::x86::OPCODE::TILERELEASE) + .value("TILESTORED", LIEF::assembly::x86::OPCODE::TILESTORED) + .value("TILESTORED_EVEX", LIEF::assembly::x86::OPCODE::TILESTORED_EVEX) + .value("TILEZERO", LIEF::assembly::x86::OPCODE::TILEZERO) + .value("TLBSYNC", LIEF::assembly::x86::OPCODE::TLBSYNC) + .value("TLSCall_32", LIEF::assembly::x86::OPCODE::TLSCall_32) + .value("TLSCall_64", LIEF::assembly::x86::OPCODE::TLSCall_64) + .value("TLS_addr32", LIEF::assembly::x86::OPCODE::TLS_addr32) + .value("TLS_addr64", LIEF::assembly::x86::OPCODE::TLS_addr64) + .value("TLS_addrX32", LIEF::assembly::x86::OPCODE::TLS_addrX32) + .value("TLS_base_addr32", LIEF::assembly::x86::OPCODE::TLS_base_addr32) + .value("TLS_base_addr64", LIEF::assembly::x86::OPCODE::TLS_base_addr64) + .value("TLS_base_addrX32", LIEF::assembly::x86::OPCODE::TLS_base_addrX32) + .value("TLS_desc32", LIEF::assembly::x86::OPCODE::TLS_desc32) + .value("TLS_desc64", LIEF::assembly::x86::OPCODE::TLS_desc64) + .value("TMMULTF32PS", LIEF::assembly::x86::OPCODE::TMMULTF32PS) + .value("TPAUSE", LIEF::assembly::x86::OPCODE::TPAUSE) + .value("TRAP", LIEF::assembly::x86::OPCODE::TRAP) + .value("TST_F", LIEF::assembly::x86::OPCODE::TST_F) + .value("TST_Fp32", LIEF::assembly::x86::OPCODE::TST_Fp32) + .value("TST_Fp64", LIEF::assembly::x86::OPCODE::TST_Fp64) + .value("TST_Fp80", LIEF::assembly::x86::OPCODE::TST_Fp80) + .value("TZCNT16rm", LIEF::assembly::x86::OPCODE::TZCNT16rm) + .value("TZCNT16rm_EVEX", LIEF::assembly::x86::OPCODE::TZCNT16rm_EVEX) + .value("TZCNT16rm_NF", LIEF::assembly::x86::OPCODE::TZCNT16rm_NF) + .value("TZCNT16rr", LIEF::assembly::x86::OPCODE::TZCNT16rr) + .value("TZCNT16rr_EVEX", LIEF::assembly::x86::OPCODE::TZCNT16rr_EVEX) + .value("TZCNT16rr_NF", LIEF::assembly::x86::OPCODE::TZCNT16rr_NF) + .value("TZCNT32rm", LIEF::assembly::x86::OPCODE::TZCNT32rm) + .value("TZCNT32rm_EVEX", LIEF::assembly::x86::OPCODE::TZCNT32rm_EVEX) + .value("TZCNT32rm_NF", LIEF::assembly::x86::OPCODE::TZCNT32rm_NF) + .value("TZCNT32rr", LIEF::assembly::x86::OPCODE::TZCNT32rr) + .value("TZCNT32rr_EVEX", LIEF::assembly::x86::OPCODE::TZCNT32rr_EVEX) + .value("TZCNT32rr_NF", LIEF::assembly::x86::OPCODE::TZCNT32rr_NF) + .value("TZCNT64rm", LIEF::assembly::x86::OPCODE::TZCNT64rm) + .value("TZCNT64rm_EVEX", LIEF::assembly::x86::OPCODE::TZCNT64rm_EVEX) + .value("TZCNT64rm_NF", LIEF::assembly::x86::OPCODE::TZCNT64rm_NF) + .value("TZCNT64rr", LIEF::assembly::x86::OPCODE::TZCNT64rr) + .value("TZCNT64rr_EVEX", LIEF::assembly::x86::OPCODE::TZCNT64rr_EVEX) + .value("TZCNT64rr_NF", LIEF::assembly::x86::OPCODE::TZCNT64rr_NF) + .value("TZMSK32rm", LIEF::assembly::x86::OPCODE::TZMSK32rm) + .value("TZMSK32rr", LIEF::assembly::x86::OPCODE::TZMSK32rr) + .value("TZMSK64rm", LIEF::assembly::x86::OPCODE::TZMSK64rm) + .value("TZMSK64rr", LIEF::assembly::x86::OPCODE::TZMSK64rr) + .value("UBSAN_UD1", LIEF::assembly::x86::OPCODE::UBSAN_UD1) + .value("UCOMISDrm", LIEF::assembly::x86::OPCODE::UCOMISDrm) + .value("UCOMISDrm_Int", LIEF::assembly::x86::OPCODE::UCOMISDrm_Int) + .value("UCOMISDrr", LIEF::assembly::x86::OPCODE::UCOMISDrr) + .value("UCOMISDrr_Int", LIEF::assembly::x86::OPCODE::UCOMISDrr_Int) + .value("UCOMISSrm", LIEF::assembly::x86::OPCODE::UCOMISSrm) + .value("UCOMISSrm_Int", LIEF::assembly::x86::OPCODE::UCOMISSrm_Int) + .value("UCOMISSrr", LIEF::assembly::x86::OPCODE::UCOMISSrr) + .value("UCOMISSrr_Int", LIEF::assembly::x86::OPCODE::UCOMISSrr_Int) + .value("UCOM_FIPr", LIEF::assembly::x86::OPCODE::UCOM_FIPr) + .value("UCOM_FIr", LIEF::assembly::x86::OPCODE::UCOM_FIr) + .value("UCOM_FPPr", LIEF::assembly::x86::OPCODE::UCOM_FPPr) + .value("UCOM_FPr", LIEF::assembly::x86::OPCODE::UCOM_FPr) + .value("UCOM_FpIr32", LIEF::assembly::x86::OPCODE::UCOM_FpIr32) + .value("UCOM_FpIr64", LIEF::assembly::x86::OPCODE::UCOM_FpIr64) + .value("UCOM_FpIr80", LIEF::assembly::x86::OPCODE::UCOM_FpIr80) + .value("UCOM_Fpr32", LIEF::assembly::x86::OPCODE::UCOM_Fpr32) + .value("UCOM_Fpr64", LIEF::assembly::x86::OPCODE::UCOM_Fpr64) + .value("UCOM_Fpr80", LIEF::assembly::x86::OPCODE::UCOM_Fpr80) + .value("UCOM_Fr", LIEF::assembly::x86::OPCODE::UCOM_Fr) + .value("UD1Lm", LIEF::assembly::x86::OPCODE::UD1Lm) + .value("UD1Lr", LIEF::assembly::x86::OPCODE::UD1Lr) + .value("UD1Qm", LIEF::assembly::x86::OPCODE::UD1Qm) + .value("UD1Qr", LIEF::assembly::x86::OPCODE::UD1Qr) + .value("UD1Wm", LIEF::assembly::x86::OPCODE::UD1Wm) + .value("UD1Wr", LIEF::assembly::x86::OPCODE::UD1Wr) + .value("UIRET", LIEF::assembly::x86::OPCODE::UIRET) + .value("UMONITOR16", LIEF::assembly::x86::OPCODE::UMONITOR16) + .value("UMONITOR32", LIEF::assembly::x86::OPCODE::UMONITOR32) + .value("UMONITOR64", LIEF::assembly::x86::OPCODE::UMONITOR64) + .value("UMWAIT", LIEF::assembly::x86::OPCODE::UMWAIT) + .value("UNPCKHPDrm", LIEF::assembly::x86::OPCODE::UNPCKHPDrm) + .value("UNPCKHPDrr", LIEF::assembly::x86::OPCODE::UNPCKHPDrr) + .value("UNPCKHPSrm", LIEF::assembly::x86::OPCODE::UNPCKHPSrm) + .value("UNPCKHPSrr", LIEF::assembly::x86::OPCODE::UNPCKHPSrr) + .value("UNPCKLPDrm", LIEF::assembly::x86::OPCODE::UNPCKLPDrm) + .value("UNPCKLPDrr", LIEF::assembly::x86::OPCODE::UNPCKLPDrr) + .value("UNPCKLPSrm", LIEF::assembly::x86::OPCODE::UNPCKLPSrm) + .value("UNPCKLPSrr", LIEF::assembly::x86::OPCODE::UNPCKLPSrr) + .value("URDMSRri", LIEF::assembly::x86::OPCODE::URDMSRri); + opcodes.value("URDMSRri_EVEX", LIEF::assembly::x86::OPCODE::URDMSRri_EVEX) + .value("URDMSRrr", LIEF::assembly::x86::OPCODE::URDMSRrr) + .value("URDMSRrr_EVEX", LIEF::assembly::x86::OPCODE::URDMSRrr_EVEX) + .value("UWRMSRir", LIEF::assembly::x86::OPCODE::UWRMSRir) + .value("UWRMSRir_EVEX", LIEF::assembly::x86::OPCODE::UWRMSRir_EVEX) + .value("UWRMSRrr", LIEF::assembly::x86::OPCODE::UWRMSRrr) + .value("UWRMSRrr_EVEX", LIEF::assembly::x86::OPCODE::UWRMSRrr_EVEX) + .value("V4FMADDPSrm", LIEF::assembly::x86::OPCODE::V4FMADDPSrm) + .value("V4FMADDPSrmk", LIEF::assembly::x86::OPCODE::V4FMADDPSrmk) + .value("V4FMADDPSrmkz", LIEF::assembly::x86::OPCODE::V4FMADDPSrmkz) + .value("V4FMADDSSrm", LIEF::assembly::x86::OPCODE::V4FMADDSSrm) + .value("V4FMADDSSrmk", LIEF::assembly::x86::OPCODE::V4FMADDSSrmk) + .value("V4FMADDSSrmkz", LIEF::assembly::x86::OPCODE::V4FMADDSSrmkz) + .value("V4FNMADDPSrm", LIEF::assembly::x86::OPCODE::V4FNMADDPSrm) + .value("V4FNMADDPSrmk", LIEF::assembly::x86::OPCODE::V4FNMADDPSrmk) + .value("V4FNMADDPSrmkz", LIEF::assembly::x86::OPCODE::V4FNMADDPSrmkz) + .value("V4FNMADDSSrm", LIEF::assembly::x86::OPCODE::V4FNMADDSSrm) + .value("V4FNMADDSSrmk", LIEF::assembly::x86::OPCODE::V4FNMADDSSrmk) + .value("V4FNMADDSSrmkz", LIEF::assembly::x86::OPCODE::V4FNMADDSSrmkz) + .value("VAARG_64", LIEF::assembly::x86::OPCODE::VAARG_64) + .value("VAARG_X32", LIEF::assembly::x86::OPCODE::VAARG_X32) + .value("VADDBF16Z128rm", LIEF::assembly::x86::OPCODE::VADDBF16Z128rm) + .value("VADDBF16Z128rmb", LIEF::assembly::x86::OPCODE::VADDBF16Z128rmb) + .value("VADDBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VADDBF16Z128rmbk) + .value("VADDBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VADDBF16Z128rmbkz) + .value("VADDBF16Z128rmk", LIEF::assembly::x86::OPCODE::VADDBF16Z128rmk) + .value("VADDBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VADDBF16Z128rmkz) + .value("VADDBF16Z128rr", LIEF::assembly::x86::OPCODE::VADDBF16Z128rr) + .value("VADDBF16Z128rrk", LIEF::assembly::x86::OPCODE::VADDBF16Z128rrk) + .value("VADDBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VADDBF16Z128rrkz) + .value("VADDBF16Z256rm", LIEF::assembly::x86::OPCODE::VADDBF16Z256rm) + .value("VADDBF16Z256rmb", LIEF::assembly::x86::OPCODE::VADDBF16Z256rmb) + .value("VADDBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VADDBF16Z256rmbk) + .value("VADDBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VADDBF16Z256rmbkz) + .value("VADDBF16Z256rmk", LIEF::assembly::x86::OPCODE::VADDBF16Z256rmk) + .value("VADDBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VADDBF16Z256rmkz) + .value("VADDBF16Z256rr", LIEF::assembly::x86::OPCODE::VADDBF16Z256rr) + .value("VADDBF16Z256rrk", LIEF::assembly::x86::OPCODE::VADDBF16Z256rrk) + .value("VADDBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VADDBF16Z256rrkz) + .value("VADDBF16Zrm", LIEF::assembly::x86::OPCODE::VADDBF16Zrm) + .value("VADDBF16Zrmb", LIEF::assembly::x86::OPCODE::VADDBF16Zrmb) + .value("VADDBF16Zrmbk", LIEF::assembly::x86::OPCODE::VADDBF16Zrmbk) + .value("VADDBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VADDBF16Zrmbkz) + .value("VADDBF16Zrmk", LIEF::assembly::x86::OPCODE::VADDBF16Zrmk) + .value("VADDBF16Zrmkz", LIEF::assembly::x86::OPCODE::VADDBF16Zrmkz) + .value("VADDBF16Zrr", LIEF::assembly::x86::OPCODE::VADDBF16Zrr) + .value("VADDBF16Zrrk", LIEF::assembly::x86::OPCODE::VADDBF16Zrrk) + .value("VADDBF16Zrrkz", LIEF::assembly::x86::OPCODE::VADDBF16Zrrkz) + .value("VADDPDYrm", LIEF::assembly::x86::OPCODE::VADDPDYrm) + .value("VADDPDYrr", LIEF::assembly::x86::OPCODE::VADDPDYrr) + .value("VADDPDZ128rm", LIEF::assembly::x86::OPCODE::VADDPDZ128rm) + .value("VADDPDZ128rmb", LIEF::assembly::x86::OPCODE::VADDPDZ128rmb) + .value("VADDPDZ128rmbk", LIEF::assembly::x86::OPCODE::VADDPDZ128rmbk) + .value("VADDPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VADDPDZ128rmbkz) + .value("VADDPDZ128rmk", LIEF::assembly::x86::OPCODE::VADDPDZ128rmk) + .value("VADDPDZ128rmkz", LIEF::assembly::x86::OPCODE::VADDPDZ128rmkz) + .value("VADDPDZ128rr", LIEF::assembly::x86::OPCODE::VADDPDZ128rr) + .value("VADDPDZ128rrk", LIEF::assembly::x86::OPCODE::VADDPDZ128rrk) + .value("VADDPDZ128rrkz", LIEF::assembly::x86::OPCODE::VADDPDZ128rrkz) + .value("VADDPDZ256rm", LIEF::assembly::x86::OPCODE::VADDPDZ256rm) + .value("VADDPDZ256rmb", LIEF::assembly::x86::OPCODE::VADDPDZ256rmb) + .value("VADDPDZ256rmbk", LIEF::assembly::x86::OPCODE::VADDPDZ256rmbk) + .value("VADDPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VADDPDZ256rmbkz) + .value("VADDPDZ256rmk", LIEF::assembly::x86::OPCODE::VADDPDZ256rmk) + .value("VADDPDZ256rmkz", LIEF::assembly::x86::OPCODE::VADDPDZ256rmkz) + .value("VADDPDZ256rr", LIEF::assembly::x86::OPCODE::VADDPDZ256rr) + .value("VADDPDZ256rrk", LIEF::assembly::x86::OPCODE::VADDPDZ256rrk) + .value("VADDPDZ256rrkz", LIEF::assembly::x86::OPCODE::VADDPDZ256rrkz) + .value("VADDPDZrm", LIEF::assembly::x86::OPCODE::VADDPDZrm) + .value("VADDPDZrmb", LIEF::assembly::x86::OPCODE::VADDPDZrmb) + .value("VADDPDZrmbk", LIEF::assembly::x86::OPCODE::VADDPDZrmbk) + .value("VADDPDZrmbkz", LIEF::assembly::x86::OPCODE::VADDPDZrmbkz) + .value("VADDPDZrmk", LIEF::assembly::x86::OPCODE::VADDPDZrmk) + .value("VADDPDZrmkz", LIEF::assembly::x86::OPCODE::VADDPDZrmkz) + .value("VADDPDZrr", LIEF::assembly::x86::OPCODE::VADDPDZrr) + .value("VADDPDZrrb", LIEF::assembly::x86::OPCODE::VADDPDZrrb) + .value("VADDPDZrrbk", LIEF::assembly::x86::OPCODE::VADDPDZrrbk) + .value("VADDPDZrrbkz", LIEF::assembly::x86::OPCODE::VADDPDZrrbkz) + .value("VADDPDZrrk", LIEF::assembly::x86::OPCODE::VADDPDZrrk) + .value("VADDPDZrrkz", LIEF::assembly::x86::OPCODE::VADDPDZrrkz) + .value("VADDPDrm", LIEF::assembly::x86::OPCODE::VADDPDrm) + .value("VADDPDrr", LIEF::assembly::x86::OPCODE::VADDPDrr) + .value("VADDPHZ128rm", LIEF::assembly::x86::OPCODE::VADDPHZ128rm) + .value("VADDPHZ128rmb", LIEF::assembly::x86::OPCODE::VADDPHZ128rmb) + .value("VADDPHZ128rmbk", LIEF::assembly::x86::OPCODE::VADDPHZ128rmbk) + .value("VADDPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VADDPHZ128rmbkz) + .value("VADDPHZ128rmk", LIEF::assembly::x86::OPCODE::VADDPHZ128rmk) + .value("VADDPHZ128rmkz", LIEF::assembly::x86::OPCODE::VADDPHZ128rmkz) + .value("VADDPHZ128rr", LIEF::assembly::x86::OPCODE::VADDPHZ128rr) + .value("VADDPHZ128rrk", LIEF::assembly::x86::OPCODE::VADDPHZ128rrk) + .value("VADDPHZ128rrkz", LIEF::assembly::x86::OPCODE::VADDPHZ128rrkz) + .value("VADDPHZ256rm", LIEF::assembly::x86::OPCODE::VADDPHZ256rm) + .value("VADDPHZ256rmb", LIEF::assembly::x86::OPCODE::VADDPHZ256rmb) + .value("VADDPHZ256rmbk", LIEF::assembly::x86::OPCODE::VADDPHZ256rmbk) + .value("VADDPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VADDPHZ256rmbkz) + .value("VADDPHZ256rmk", LIEF::assembly::x86::OPCODE::VADDPHZ256rmk) + .value("VADDPHZ256rmkz", LIEF::assembly::x86::OPCODE::VADDPHZ256rmkz) + .value("VADDPHZ256rr", LIEF::assembly::x86::OPCODE::VADDPHZ256rr) + .value("VADDPHZ256rrk", LIEF::assembly::x86::OPCODE::VADDPHZ256rrk) + .value("VADDPHZ256rrkz", LIEF::assembly::x86::OPCODE::VADDPHZ256rrkz) + .value("VADDPHZrm", LIEF::assembly::x86::OPCODE::VADDPHZrm) + .value("VADDPHZrmb", LIEF::assembly::x86::OPCODE::VADDPHZrmb) + .value("VADDPHZrmbk", LIEF::assembly::x86::OPCODE::VADDPHZrmbk) + .value("VADDPHZrmbkz", LIEF::assembly::x86::OPCODE::VADDPHZrmbkz) + .value("VADDPHZrmk", LIEF::assembly::x86::OPCODE::VADDPHZrmk) + .value("VADDPHZrmkz", LIEF::assembly::x86::OPCODE::VADDPHZrmkz) + .value("VADDPHZrr", LIEF::assembly::x86::OPCODE::VADDPHZrr) + .value("VADDPHZrrb", LIEF::assembly::x86::OPCODE::VADDPHZrrb) + .value("VADDPHZrrbk", LIEF::assembly::x86::OPCODE::VADDPHZrrbk) + .value("VADDPHZrrbkz", LIEF::assembly::x86::OPCODE::VADDPHZrrbkz) + .value("VADDPHZrrk", LIEF::assembly::x86::OPCODE::VADDPHZrrk) + .value("VADDPHZrrkz", LIEF::assembly::x86::OPCODE::VADDPHZrrkz) + .value("VADDPSYrm", LIEF::assembly::x86::OPCODE::VADDPSYrm) + .value("VADDPSYrr", LIEF::assembly::x86::OPCODE::VADDPSYrr) + .value("VADDPSZ128rm", LIEF::assembly::x86::OPCODE::VADDPSZ128rm) + .value("VADDPSZ128rmb", LIEF::assembly::x86::OPCODE::VADDPSZ128rmb) + .value("VADDPSZ128rmbk", LIEF::assembly::x86::OPCODE::VADDPSZ128rmbk) + .value("VADDPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VADDPSZ128rmbkz) + .value("VADDPSZ128rmk", LIEF::assembly::x86::OPCODE::VADDPSZ128rmk) + .value("VADDPSZ128rmkz", LIEF::assembly::x86::OPCODE::VADDPSZ128rmkz) + .value("VADDPSZ128rr", LIEF::assembly::x86::OPCODE::VADDPSZ128rr) + .value("VADDPSZ128rrk", LIEF::assembly::x86::OPCODE::VADDPSZ128rrk) + .value("VADDPSZ128rrkz", LIEF::assembly::x86::OPCODE::VADDPSZ128rrkz) + .value("VADDPSZ256rm", LIEF::assembly::x86::OPCODE::VADDPSZ256rm) + .value("VADDPSZ256rmb", LIEF::assembly::x86::OPCODE::VADDPSZ256rmb) + .value("VADDPSZ256rmbk", LIEF::assembly::x86::OPCODE::VADDPSZ256rmbk) + .value("VADDPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VADDPSZ256rmbkz) + .value("VADDPSZ256rmk", LIEF::assembly::x86::OPCODE::VADDPSZ256rmk) + .value("VADDPSZ256rmkz", LIEF::assembly::x86::OPCODE::VADDPSZ256rmkz) + .value("VADDPSZ256rr", LIEF::assembly::x86::OPCODE::VADDPSZ256rr) + .value("VADDPSZ256rrk", LIEF::assembly::x86::OPCODE::VADDPSZ256rrk) + .value("VADDPSZ256rrkz", LIEF::assembly::x86::OPCODE::VADDPSZ256rrkz) + .value("VADDPSZrm", LIEF::assembly::x86::OPCODE::VADDPSZrm) + .value("VADDPSZrmb", LIEF::assembly::x86::OPCODE::VADDPSZrmb) + .value("VADDPSZrmbk", LIEF::assembly::x86::OPCODE::VADDPSZrmbk) + .value("VADDPSZrmbkz", LIEF::assembly::x86::OPCODE::VADDPSZrmbkz) + .value("VADDPSZrmk", LIEF::assembly::x86::OPCODE::VADDPSZrmk) + .value("VADDPSZrmkz", LIEF::assembly::x86::OPCODE::VADDPSZrmkz) + .value("VADDPSZrr", LIEF::assembly::x86::OPCODE::VADDPSZrr) + .value("VADDPSZrrb", LIEF::assembly::x86::OPCODE::VADDPSZrrb) + .value("VADDPSZrrbk", LIEF::assembly::x86::OPCODE::VADDPSZrrbk) + .value("VADDPSZrrbkz", LIEF::assembly::x86::OPCODE::VADDPSZrrbkz) + .value("VADDPSZrrk", LIEF::assembly::x86::OPCODE::VADDPSZrrk) + .value("VADDPSZrrkz", LIEF::assembly::x86::OPCODE::VADDPSZrrkz) + .value("VADDPSrm", LIEF::assembly::x86::OPCODE::VADDPSrm) + .value("VADDPSrr", LIEF::assembly::x86::OPCODE::VADDPSrr) + .value("VADDSDZrm", LIEF::assembly::x86::OPCODE::VADDSDZrm) + .value("VADDSDZrm_Int", LIEF::assembly::x86::OPCODE::VADDSDZrm_Int) + .value("VADDSDZrmk_Int", LIEF::assembly::x86::OPCODE::VADDSDZrmk_Int) + .value("VADDSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VADDSDZrmkz_Int) + .value("VADDSDZrr", LIEF::assembly::x86::OPCODE::VADDSDZrr) + .value("VADDSDZrr_Int", LIEF::assembly::x86::OPCODE::VADDSDZrr_Int) + .value("VADDSDZrrb_Int", LIEF::assembly::x86::OPCODE::VADDSDZrrb_Int) + .value("VADDSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VADDSDZrrbk_Int) + .value("VADDSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VADDSDZrrbkz_Int) + .value("VADDSDZrrk_Int", LIEF::assembly::x86::OPCODE::VADDSDZrrk_Int) + .value("VADDSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VADDSDZrrkz_Int) + .value("VADDSDrm", LIEF::assembly::x86::OPCODE::VADDSDrm) + .value("VADDSDrm_Int", LIEF::assembly::x86::OPCODE::VADDSDrm_Int) + .value("VADDSDrr", LIEF::assembly::x86::OPCODE::VADDSDrr) + .value("VADDSDrr_Int", LIEF::assembly::x86::OPCODE::VADDSDrr_Int) + .value("VADDSHZrm", LIEF::assembly::x86::OPCODE::VADDSHZrm) + .value("VADDSHZrm_Int", LIEF::assembly::x86::OPCODE::VADDSHZrm_Int) + .value("VADDSHZrmk_Int", LIEF::assembly::x86::OPCODE::VADDSHZrmk_Int) + .value("VADDSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VADDSHZrmkz_Int) + .value("VADDSHZrr", LIEF::assembly::x86::OPCODE::VADDSHZrr) + .value("VADDSHZrr_Int", LIEF::assembly::x86::OPCODE::VADDSHZrr_Int) + .value("VADDSHZrrb_Int", LIEF::assembly::x86::OPCODE::VADDSHZrrb_Int) + .value("VADDSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VADDSHZrrbk_Int) + .value("VADDSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VADDSHZrrbkz_Int) + .value("VADDSHZrrk_Int", LIEF::assembly::x86::OPCODE::VADDSHZrrk_Int) + .value("VADDSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VADDSHZrrkz_Int) + .value("VADDSSZrm", LIEF::assembly::x86::OPCODE::VADDSSZrm) + .value("VADDSSZrm_Int", LIEF::assembly::x86::OPCODE::VADDSSZrm_Int) + .value("VADDSSZrmk_Int", LIEF::assembly::x86::OPCODE::VADDSSZrmk_Int) + .value("VADDSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VADDSSZrmkz_Int) + .value("VADDSSZrr", LIEF::assembly::x86::OPCODE::VADDSSZrr) + .value("VADDSSZrr_Int", LIEF::assembly::x86::OPCODE::VADDSSZrr_Int) + .value("VADDSSZrrb_Int", LIEF::assembly::x86::OPCODE::VADDSSZrrb_Int) + .value("VADDSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VADDSSZrrbk_Int) + .value("VADDSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VADDSSZrrbkz_Int) + .value("VADDSSZrrk_Int", LIEF::assembly::x86::OPCODE::VADDSSZrrk_Int) + .value("VADDSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VADDSSZrrkz_Int) + .value("VADDSSrm", LIEF::assembly::x86::OPCODE::VADDSSrm) + .value("VADDSSrm_Int", LIEF::assembly::x86::OPCODE::VADDSSrm_Int) + .value("VADDSSrr", LIEF::assembly::x86::OPCODE::VADDSSrr) + .value("VADDSSrr_Int", LIEF::assembly::x86::OPCODE::VADDSSrr_Int) + .value("VADDSUBPDYrm", LIEF::assembly::x86::OPCODE::VADDSUBPDYrm) + .value("VADDSUBPDYrr", LIEF::assembly::x86::OPCODE::VADDSUBPDYrr) + .value("VADDSUBPDrm", LIEF::assembly::x86::OPCODE::VADDSUBPDrm) + .value("VADDSUBPDrr", LIEF::assembly::x86::OPCODE::VADDSUBPDrr) + .value("VADDSUBPSYrm", LIEF::assembly::x86::OPCODE::VADDSUBPSYrm) + .value("VADDSUBPSYrr", LIEF::assembly::x86::OPCODE::VADDSUBPSYrr) + .value("VADDSUBPSrm", LIEF::assembly::x86::OPCODE::VADDSUBPSrm) + .value("VADDSUBPSrr", LIEF::assembly::x86::OPCODE::VADDSUBPSrr) + .value("VAESDECLASTYrm", LIEF::assembly::x86::OPCODE::VAESDECLASTYrm) + .value("VAESDECLASTYrr", LIEF::assembly::x86::OPCODE::VAESDECLASTYrr) + .value("VAESDECLASTZ128rm", LIEF::assembly::x86::OPCODE::VAESDECLASTZ128rm) + .value("VAESDECLASTZ128rr", LIEF::assembly::x86::OPCODE::VAESDECLASTZ128rr) + .value("VAESDECLASTZ256rm", LIEF::assembly::x86::OPCODE::VAESDECLASTZ256rm) + .value("VAESDECLASTZ256rr", LIEF::assembly::x86::OPCODE::VAESDECLASTZ256rr) + .value("VAESDECLASTZrm", LIEF::assembly::x86::OPCODE::VAESDECLASTZrm) + .value("VAESDECLASTZrr", LIEF::assembly::x86::OPCODE::VAESDECLASTZrr) + .value("VAESDECLASTrm", LIEF::assembly::x86::OPCODE::VAESDECLASTrm) + .value("VAESDECLASTrr", LIEF::assembly::x86::OPCODE::VAESDECLASTrr) + .value("VAESDECYrm", LIEF::assembly::x86::OPCODE::VAESDECYrm) + .value("VAESDECYrr", LIEF::assembly::x86::OPCODE::VAESDECYrr) + .value("VAESDECZ128rm", LIEF::assembly::x86::OPCODE::VAESDECZ128rm) + .value("VAESDECZ128rr", LIEF::assembly::x86::OPCODE::VAESDECZ128rr) + .value("VAESDECZ256rm", LIEF::assembly::x86::OPCODE::VAESDECZ256rm) + .value("VAESDECZ256rr", LIEF::assembly::x86::OPCODE::VAESDECZ256rr) + .value("VAESDECZrm", LIEF::assembly::x86::OPCODE::VAESDECZrm) + .value("VAESDECZrr", LIEF::assembly::x86::OPCODE::VAESDECZrr) + .value("VAESDECrm", LIEF::assembly::x86::OPCODE::VAESDECrm) + .value("VAESDECrr", LIEF::assembly::x86::OPCODE::VAESDECrr) + .value("VAESENCLASTYrm", LIEF::assembly::x86::OPCODE::VAESENCLASTYrm) + .value("VAESENCLASTYrr", LIEF::assembly::x86::OPCODE::VAESENCLASTYrr) + .value("VAESENCLASTZ128rm", LIEF::assembly::x86::OPCODE::VAESENCLASTZ128rm) + .value("VAESENCLASTZ128rr", LIEF::assembly::x86::OPCODE::VAESENCLASTZ128rr) + .value("VAESENCLASTZ256rm", LIEF::assembly::x86::OPCODE::VAESENCLASTZ256rm) + .value("VAESENCLASTZ256rr", LIEF::assembly::x86::OPCODE::VAESENCLASTZ256rr) + .value("VAESENCLASTZrm", LIEF::assembly::x86::OPCODE::VAESENCLASTZrm) + .value("VAESENCLASTZrr", LIEF::assembly::x86::OPCODE::VAESENCLASTZrr) + .value("VAESENCLASTrm", LIEF::assembly::x86::OPCODE::VAESENCLASTrm) + .value("VAESENCLASTrr", LIEF::assembly::x86::OPCODE::VAESENCLASTrr) + .value("VAESENCYrm", LIEF::assembly::x86::OPCODE::VAESENCYrm) + .value("VAESENCYrr", LIEF::assembly::x86::OPCODE::VAESENCYrr) + .value("VAESENCZ128rm", LIEF::assembly::x86::OPCODE::VAESENCZ128rm) + .value("VAESENCZ128rr", LIEF::assembly::x86::OPCODE::VAESENCZ128rr) + .value("VAESENCZ256rm", LIEF::assembly::x86::OPCODE::VAESENCZ256rm) + .value("VAESENCZ256rr", LIEF::assembly::x86::OPCODE::VAESENCZ256rr) + .value("VAESENCZrm", LIEF::assembly::x86::OPCODE::VAESENCZrm) + .value("VAESENCZrr", LIEF::assembly::x86::OPCODE::VAESENCZrr) + .value("VAESENCrm", LIEF::assembly::x86::OPCODE::VAESENCrm) + .value("VAESENCrr", LIEF::assembly::x86::OPCODE::VAESENCrr) + .value("VAESIMCrm", LIEF::assembly::x86::OPCODE::VAESIMCrm) + .value("VAESIMCrr", LIEF::assembly::x86::OPCODE::VAESIMCrr) + .value("VAESKEYGENASSISTrmi", LIEF::assembly::x86::OPCODE::VAESKEYGENASSISTrmi) + .value("VAESKEYGENASSISTrri", LIEF::assembly::x86::OPCODE::VAESKEYGENASSISTrri) + .value("VALIGNDZ128rmbi", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmbi) + .value("VALIGNDZ128rmbik", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmbik) + .value("VALIGNDZ128rmbikz", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmbikz) + .value("VALIGNDZ128rmi", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmi) + .value("VALIGNDZ128rmik", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmik) + .value("VALIGNDZ128rmikz", LIEF::assembly::x86::OPCODE::VALIGNDZ128rmikz) + .value("VALIGNDZ128rri", LIEF::assembly::x86::OPCODE::VALIGNDZ128rri) + .value("VALIGNDZ128rrik", LIEF::assembly::x86::OPCODE::VALIGNDZ128rrik) + .value("VALIGNDZ128rrikz", LIEF::assembly::x86::OPCODE::VALIGNDZ128rrikz) + .value("VALIGNDZ256rmbi", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmbi) + .value("VALIGNDZ256rmbik", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmbik) + .value("VALIGNDZ256rmbikz", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmbikz) + .value("VALIGNDZ256rmi", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmi) + .value("VALIGNDZ256rmik", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmik) + .value("VALIGNDZ256rmikz", LIEF::assembly::x86::OPCODE::VALIGNDZ256rmikz) + .value("VALIGNDZ256rri", LIEF::assembly::x86::OPCODE::VALIGNDZ256rri) + .value("VALIGNDZ256rrik", LIEF::assembly::x86::OPCODE::VALIGNDZ256rrik) + .value("VALIGNDZ256rrikz", LIEF::assembly::x86::OPCODE::VALIGNDZ256rrikz) + .value("VALIGNDZrmbi", LIEF::assembly::x86::OPCODE::VALIGNDZrmbi) + .value("VALIGNDZrmbik", LIEF::assembly::x86::OPCODE::VALIGNDZrmbik) + .value("VALIGNDZrmbikz", LIEF::assembly::x86::OPCODE::VALIGNDZrmbikz) + .value("VALIGNDZrmi", LIEF::assembly::x86::OPCODE::VALIGNDZrmi) + .value("VALIGNDZrmik", LIEF::assembly::x86::OPCODE::VALIGNDZrmik) + .value("VALIGNDZrmikz", LIEF::assembly::x86::OPCODE::VALIGNDZrmikz) + .value("VALIGNDZrri", LIEF::assembly::x86::OPCODE::VALIGNDZrri) + .value("VALIGNDZrrik", LIEF::assembly::x86::OPCODE::VALIGNDZrrik) + .value("VALIGNDZrrikz", LIEF::assembly::x86::OPCODE::VALIGNDZrrikz) + .value("VALIGNQZ128rmbi", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmbi) + .value("VALIGNQZ128rmbik", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmbik) + .value("VALIGNQZ128rmbikz", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmbikz) + .value("VALIGNQZ128rmi", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmi) + .value("VALIGNQZ128rmik", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmik) + .value("VALIGNQZ128rmikz", LIEF::assembly::x86::OPCODE::VALIGNQZ128rmikz) + .value("VALIGNQZ128rri", LIEF::assembly::x86::OPCODE::VALIGNQZ128rri) + .value("VALIGNQZ128rrik", LIEF::assembly::x86::OPCODE::VALIGNQZ128rrik) + .value("VALIGNQZ128rrikz", LIEF::assembly::x86::OPCODE::VALIGNQZ128rrikz) + .value("VALIGNQZ256rmbi", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmbi) + .value("VALIGNQZ256rmbik", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmbik) + .value("VALIGNQZ256rmbikz", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmbikz) + .value("VALIGNQZ256rmi", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmi) + .value("VALIGNQZ256rmik", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmik) + .value("VALIGNQZ256rmikz", LIEF::assembly::x86::OPCODE::VALIGNQZ256rmikz) + .value("VALIGNQZ256rri", LIEF::assembly::x86::OPCODE::VALIGNQZ256rri) + .value("VALIGNQZ256rrik", LIEF::assembly::x86::OPCODE::VALIGNQZ256rrik) + .value("VALIGNQZ256rrikz", LIEF::assembly::x86::OPCODE::VALIGNQZ256rrikz) + .value("VALIGNQZrmbi", LIEF::assembly::x86::OPCODE::VALIGNQZrmbi) + .value("VALIGNQZrmbik", LIEF::assembly::x86::OPCODE::VALIGNQZrmbik) + .value("VALIGNQZrmbikz", LIEF::assembly::x86::OPCODE::VALIGNQZrmbikz) + .value("VALIGNQZrmi", LIEF::assembly::x86::OPCODE::VALIGNQZrmi) + .value("VALIGNQZrmik", LIEF::assembly::x86::OPCODE::VALIGNQZrmik) + .value("VALIGNQZrmikz", LIEF::assembly::x86::OPCODE::VALIGNQZrmikz) + .value("VALIGNQZrri", LIEF::assembly::x86::OPCODE::VALIGNQZrri) + .value("VALIGNQZrrik", LIEF::assembly::x86::OPCODE::VALIGNQZrrik) + .value("VALIGNQZrrikz", LIEF::assembly::x86::OPCODE::VALIGNQZrrikz) + .value("VANDNPDYrm", LIEF::assembly::x86::OPCODE::VANDNPDYrm) + .value("VANDNPDYrr", LIEF::assembly::x86::OPCODE::VANDNPDYrr) + .value("VANDNPDZ128rm", LIEF::assembly::x86::OPCODE::VANDNPDZ128rm) + .value("VANDNPDZ128rmb", LIEF::assembly::x86::OPCODE::VANDNPDZ128rmb) + .value("VANDNPDZ128rmbk", LIEF::assembly::x86::OPCODE::VANDNPDZ128rmbk) + .value("VANDNPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VANDNPDZ128rmbkz) + .value("VANDNPDZ128rmk", LIEF::assembly::x86::OPCODE::VANDNPDZ128rmk); + opcodes.value("VANDNPDZ128rmkz", LIEF::assembly::x86::OPCODE::VANDNPDZ128rmkz) + .value("VANDNPDZ128rr", LIEF::assembly::x86::OPCODE::VANDNPDZ128rr) + .value("VANDNPDZ128rrk", LIEF::assembly::x86::OPCODE::VANDNPDZ128rrk) + .value("VANDNPDZ128rrkz", LIEF::assembly::x86::OPCODE::VANDNPDZ128rrkz) + .value("VANDNPDZ256rm", LIEF::assembly::x86::OPCODE::VANDNPDZ256rm) + .value("VANDNPDZ256rmb", LIEF::assembly::x86::OPCODE::VANDNPDZ256rmb) + .value("VANDNPDZ256rmbk", LIEF::assembly::x86::OPCODE::VANDNPDZ256rmbk) + .value("VANDNPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VANDNPDZ256rmbkz) + .value("VANDNPDZ256rmk", LIEF::assembly::x86::OPCODE::VANDNPDZ256rmk) + .value("VANDNPDZ256rmkz", LIEF::assembly::x86::OPCODE::VANDNPDZ256rmkz) + .value("VANDNPDZ256rr", LIEF::assembly::x86::OPCODE::VANDNPDZ256rr) + .value("VANDNPDZ256rrk", LIEF::assembly::x86::OPCODE::VANDNPDZ256rrk) + .value("VANDNPDZ256rrkz", LIEF::assembly::x86::OPCODE::VANDNPDZ256rrkz) + .value("VANDNPDZrm", LIEF::assembly::x86::OPCODE::VANDNPDZrm) + .value("VANDNPDZrmb", LIEF::assembly::x86::OPCODE::VANDNPDZrmb) + .value("VANDNPDZrmbk", LIEF::assembly::x86::OPCODE::VANDNPDZrmbk) + .value("VANDNPDZrmbkz", LIEF::assembly::x86::OPCODE::VANDNPDZrmbkz) + .value("VANDNPDZrmk", LIEF::assembly::x86::OPCODE::VANDNPDZrmk) + .value("VANDNPDZrmkz", LIEF::assembly::x86::OPCODE::VANDNPDZrmkz) + .value("VANDNPDZrr", LIEF::assembly::x86::OPCODE::VANDNPDZrr) + .value("VANDNPDZrrk", LIEF::assembly::x86::OPCODE::VANDNPDZrrk) + .value("VANDNPDZrrkz", LIEF::assembly::x86::OPCODE::VANDNPDZrrkz) + .value("VANDNPDrm", LIEF::assembly::x86::OPCODE::VANDNPDrm) + .value("VANDNPDrr", LIEF::assembly::x86::OPCODE::VANDNPDrr) + .value("VANDNPSYrm", LIEF::assembly::x86::OPCODE::VANDNPSYrm) + .value("VANDNPSYrr", LIEF::assembly::x86::OPCODE::VANDNPSYrr) + .value("VANDNPSZ128rm", LIEF::assembly::x86::OPCODE::VANDNPSZ128rm) + .value("VANDNPSZ128rmb", LIEF::assembly::x86::OPCODE::VANDNPSZ128rmb) + .value("VANDNPSZ128rmbk", LIEF::assembly::x86::OPCODE::VANDNPSZ128rmbk) + .value("VANDNPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VANDNPSZ128rmbkz) + .value("VANDNPSZ128rmk", LIEF::assembly::x86::OPCODE::VANDNPSZ128rmk) + .value("VANDNPSZ128rmkz", LIEF::assembly::x86::OPCODE::VANDNPSZ128rmkz) + .value("VANDNPSZ128rr", LIEF::assembly::x86::OPCODE::VANDNPSZ128rr) + .value("VANDNPSZ128rrk", LIEF::assembly::x86::OPCODE::VANDNPSZ128rrk) + .value("VANDNPSZ128rrkz", LIEF::assembly::x86::OPCODE::VANDNPSZ128rrkz) + .value("VANDNPSZ256rm", LIEF::assembly::x86::OPCODE::VANDNPSZ256rm) + .value("VANDNPSZ256rmb", LIEF::assembly::x86::OPCODE::VANDNPSZ256rmb) + .value("VANDNPSZ256rmbk", LIEF::assembly::x86::OPCODE::VANDNPSZ256rmbk) + .value("VANDNPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VANDNPSZ256rmbkz) + .value("VANDNPSZ256rmk", LIEF::assembly::x86::OPCODE::VANDNPSZ256rmk) + .value("VANDNPSZ256rmkz", LIEF::assembly::x86::OPCODE::VANDNPSZ256rmkz) + .value("VANDNPSZ256rr", LIEF::assembly::x86::OPCODE::VANDNPSZ256rr) + .value("VANDNPSZ256rrk", LIEF::assembly::x86::OPCODE::VANDNPSZ256rrk) + .value("VANDNPSZ256rrkz", LIEF::assembly::x86::OPCODE::VANDNPSZ256rrkz) + .value("VANDNPSZrm", LIEF::assembly::x86::OPCODE::VANDNPSZrm) + .value("VANDNPSZrmb", LIEF::assembly::x86::OPCODE::VANDNPSZrmb) + .value("VANDNPSZrmbk", LIEF::assembly::x86::OPCODE::VANDNPSZrmbk) + .value("VANDNPSZrmbkz", LIEF::assembly::x86::OPCODE::VANDNPSZrmbkz) + .value("VANDNPSZrmk", LIEF::assembly::x86::OPCODE::VANDNPSZrmk) + .value("VANDNPSZrmkz", LIEF::assembly::x86::OPCODE::VANDNPSZrmkz) + .value("VANDNPSZrr", LIEF::assembly::x86::OPCODE::VANDNPSZrr) + .value("VANDNPSZrrk", LIEF::assembly::x86::OPCODE::VANDNPSZrrk) + .value("VANDNPSZrrkz", LIEF::assembly::x86::OPCODE::VANDNPSZrrkz) + .value("VANDNPSrm", LIEF::assembly::x86::OPCODE::VANDNPSrm) + .value("VANDNPSrr", LIEF::assembly::x86::OPCODE::VANDNPSrr) + .value("VANDPDYrm", LIEF::assembly::x86::OPCODE::VANDPDYrm) + .value("VANDPDYrr", LIEF::assembly::x86::OPCODE::VANDPDYrr) + .value("VANDPDZ128rm", LIEF::assembly::x86::OPCODE::VANDPDZ128rm) + .value("VANDPDZ128rmb", LIEF::assembly::x86::OPCODE::VANDPDZ128rmb) + .value("VANDPDZ128rmbk", LIEF::assembly::x86::OPCODE::VANDPDZ128rmbk) + .value("VANDPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VANDPDZ128rmbkz) + .value("VANDPDZ128rmk", LIEF::assembly::x86::OPCODE::VANDPDZ128rmk) + .value("VANDPDZ128rmkz", LIEF::assembly::x86::OPCODE::VANDPDZ128rmkz) + .value("VANDPDZ128rr", LIEF::assembly::x86::OPCODE::VANDPDZ128rr) + .value("VANDPDZ128rrk", LIEF::assembly::x86::OPCODE::VANDPDZ128rrk) + .value("VANDPDZ128rrkz", LIEF::assembly::x86::OPCODE::VANDPDZ128rrkz) + .value("VANDPDZ256rm", LIEF::assembly::x86::OPCODE::VANDPDZ256rm) + .value("VANDPDZ256rmb", LIEF::assembly::x86::OPCODE::VANDPDZ256rmb) + .value("VANDPDZ256rmbk", LIEF::assembly::x86::OPCODE::VANDPDZ256rmbk) + .value("VANDPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VANDPDZ256rmbkz) + .value("VANDPDZ256rmk", LIEF::assembly::x86::OPCODE::VANDPDZ256rmk) + .value("VANDPDZ256rmkz", LIEF::assembly::x86::OPCODE::VANDPDZ256rmkz) + .value("VANDPDZ256rr", LIEF::assembly::x86::OPCODE::VANDPDZ256rr) + .value("VANDPDZ256rrk", LIEF::assembly::x86::OPCODE::VANDPDZ256rrk) + .value("VANDPDZ256rrkz", LIEF::assembly::x86::OPCODE::VANDPDZ256rrkz) + .value("VANDPDZrm", LIEF::assembly::x86::OPCODE::VANDPDZrm) + .value("VANDPDZrmb", LIEF::assembly::x86::OPCODE::VANDPDZrmb) + .value("VANDPDZrmbk", LIEF::assembly::x86::OPCODE::VANDPDZrmbk) + .value("VANDPDZrmbkz", LIEF::assembly::x86::OPCODE::VANDPDZrmbkz) + .value("VANDPDZrmk", LIEF::assembly::x86::OPCODE::VANDPDZrmk) + .value("VANDPDZrmkz", LIEF::assembly::x86::OPCODE::VANDPDZrmkz) + .value("VANDPDZrr", LIEF::assembly::x86::OPCODE::VANDPDZrr) + .value("VANDPDZrrk", LIEF::assembly::x86::OPCODE::VANDPDZrrk) + .value("VANDPDZrrkz", LIEF::assembly::x86::OPCODE::VANDPDZrrkz) + .value("VANDPDrm", LIEF::assembly::x86::OPCODE::VANDPDrm) + .value("VANDPDrr", LIEF::assembly::x86::OPCODE::VANDPDrr) + .value("VANDPSYrm", LIEF::assembly::x86::OPCODE::VANDPSYrm) + .value("VANDPSYrr", LIEF::assembly::x86::OPCODE::VANDPSYrr) + .value("VANDPSZ128rm", LIEF::assembly::x86::OPCODE::VANDPSZ128rm) + .value("VANDPSZ128rmb", LIEF::assembly::x86::OPCODE::VANDPSZ128rmb) + .value("VANDPSZ128rmbk", LIEF::assembly::x86::OPCODE::VANDPSZ128rmbk) + .value("VANDPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VANDPSZ128rmbkz) + .value("VANDPSZ128rmk", LIEF::assembly::x86::OPCODE::VANDPSZ128rmk) + .value("VANDPSZ128rmkz", LIEF::assembly::x86::OPCODE::VANDPSZ128rmkz) + .value("VANDPSZ128rr", LIEF::assembly::x86::OPCODE::VANDPSZ128rr) + .value("VANDPSZ128rrk", LIEF::assembly::x86::OPCODE::VANDPSZ128rrk) + .value("VANDPSZ128rrkz", LIEF::assembly::x86::OPCODE::VANDPSZ128rrkz) + .value("VANDPSZ256rm", LIEF::assembly::x86::OPCODE::VANDPSZ256rm) + .value("VANDPSZ256rmb", LIEF::assembly::x86::OPCODE::VANDPSZ256rmb) + .value("VANDPSZ256rmbk", LIEF::assembly::x86::OPCODE::VANDPSZ256rmbk) + .value("VANDPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VANDPSZ256rmbkz) + .value("VANDPSZ256rmk", LIEF::assembly::x86::OPCODE::VANDPSZ256rmk) + .value("VANDPSZ256rmkz", LIEF::assembly::x86::OPCODE::VANDPSZ256rmkz) + .value("VANDPSZ256rr", LIEF::assembly::x86::OPCODE::VANDPSZ256rr) + .value("VANDPSZ256rrk", LIEF::assembly::x86::OPCODE::VANDPSZ256rrk) + .value("VANDPSZ256rrkz", LIEF::assembly::x86::OPCODE::VANDPSZ256rrkz) + .value("VANDPSZrm", LIEF::assembly::x86::OPCODE::VANDPSZrm) + .value("VANDPSZrmb", LIEF::assembly::x86::OPCODE::VANDPSZrmb) + .value("VANDPSZrmbk", LIEF::assembly::x86::OPCODE::VANDPSZrmbk) + .value("VANDPSZrmbkz", LIEF::assembly::x86::OPCODE::VANDPSZrmbkz) + .value("VANDPSZrmk", LIEF::assembly::x86::OPCODE::VANDPSZrmk) + .value("VANDPSZrmkz", LIEF::assembly::x86::OPCODE::VANDPSZrmkz) + .value("VANDPSZrr", LIEF::assembly::x86::OPCODE::VANDPSZrr) + .value("VANDPSZrrk", LIEF::assembly::x86::OPCODE::VANDPSZrrk) + .value("VANDPSZrrkz", LIEF::assembly::x86::OPCODE::VANDPSZrrkz) + .value("VANDPSrm", LIEF::assembly::x86::OPCODE::VANDPSrm) + .value("VANDPSrr", LIEF::assembly::x86::OPCODE::VANDPSrr) + .value("VASTART_SAVE_XMM_REGS", LIEF::assembly::x86::OPCODE::VASTART_SAVE_XMM_REGS) + .value("VBCSTNEBF162PSYrm", LIEF::assembly::x86::OPCODE::VBCSTNEBF162PSYrm) + .value("VBCSTNEBF162PSrm", LIEF::assembly::x86::OPCODE::VBCSTNEBF162PSrm) + .value("VBCSTNESH2PSYrm", LIEF::assembly::x86::OPCODE::VBCSTNESH2PSYrm) + .value("VBCSTNESH2PSrm", LIEF::assembly::x86::OPCODE::VBCSTNESH2PSrm) + .value("VBLENDMPDZ128rm", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rm) + .value("VBLENDMPDZ128rmb", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rmb) + .value("VBLENDMPDZ128rmbk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rmbk) + .value("VBLENDMPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rmbkz) + .value("VBLENDMPDZ128rmk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rmk) + .value("VBLENDMPDZ128rmkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rmkz) + .value("VBLENDMPDZ128rr", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rr) + .value("VBLENDMPDZ128rrk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rrk) + .value("VBLENDMPDZ128rrkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ128rrkz) + .value("VBLENDMPDZ256rm", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rm) + .value("VBLENDMPDZ256rmb", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rmb) + .value("VBLENDMPDZ256rmbk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rmbk) + .value("VBLENDMPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rmbkz) + .value("VBLENDMPDZ256rmk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rmk) + .value("VBLENDMPDZ256rmkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rmkz) + .value("VBLENDMPDZ256rr", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rr) + .value("VBLENDMPDZ256rrk", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rrk) + .value("VBLENDMPDZ256rrkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZ256rrkz) + .value("VBLENDMPDZrm", LIEF::assembly::x86::OPCODE::VBLENDMPDZrm) + .value("VBLENDMPDZrmb", LIEF::assembly::x86::OPCODE::VBLENDMPDZrmb) + .value("VBLENDMPDZrmbk", LIEF::assembly::x86::OPCODE::VBLENDMPDZrmbk) + .value("VBLENDMPDZrmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZrmbkz) + .value("VBLENDMPDZrmk", LIEF::assembly::x86::OPCODE::VBLENDMPDZrmk) + .value("VBLENDMPDZrmkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZrmkz) + .value("VBLENDMPDZrr", LIEF::assembly::x86::OPCODE::VBLENDMPDZrr) + .value("VBLENDMPDZrrk", LIEF::assembly::x86::OPCODE::VBLENDMPDZrrk) + .value("VBLENDMPDZrrkz", LIEF::assembly::x86::OPCODE::VBLENDMPDZrrkz) + .value("VBLENDMPSZ128rm", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rm) + .value("VBLENDMPSZ128rmb", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rmb) + .value("VBLENDMPSZ128rmbk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rmbk) + .value("VBLENDMPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rmbkz) + .value("VBLENDMPSZ128rmk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rmk) + .value("VBLENDMPSZ128rmkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rmkz) + .value("VBLENDMPSZ128rr", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rr) + .value("VBLENDMPSZ128rrk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rrk) + .value("VBLENDMPSZ128rrkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ128rrkz) + .value("VBLENDMPSZ256rm", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rm) + .value("VBLENDMPSZ256rmb", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rmb) + .value("VBLENDMPSZ256rmbk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rmbk) + .value("VBLENDMPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rmbkz) + .value("VBLENDMPSZ256rmk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rmk) + .value("VBLENDMPSZ256rmkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rmkz) + .value("VBLENDMPSZ256rr", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rr) + .value("VBLENDMPSZ256rrk", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rrk) + .value("VBLENDMPSZ256rrkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZ256rrkz) + .value("VBLENDMPSZrm", LIEF::assembly::x86::OPCODE::VBLENDMPSZrm) + .value("VBLENDMPSZrmb", LIEF::assembly::x86::OPCODE::VBLENDMPSZrmb) + .value("VBLENDMPSZrmbk", LIEF::assembly::x86::OPCODE::VBLENDMPSZrmbk) + .value("VBLENDMPSZrmbkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZrmbkz) + .value("VBLENDMPSZrmk", LIEF::assembly::x86::OPCODE::VBLENDMPSZrmk) + .value("VBLENDMPSZrmkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZrmkz) + .value("VBLENDMPSZrr", LIEF::assembly::x86::OPCODE::VBLENDMPSZrr) + .value("VBLENDMPSZrrk", LIEF::assembly::x86::OPCODE::VBLENDMPSZrrk) + .value("VBLENDMPSZrrkz", LIEF::assembly::x86::OPCODE::VBLENDMPSZrrkz) + .value("VBLENDPDYrmi", LIEF::assembly::x86::OPCODE::VBLENDPDYrmi) + .value("VBLENDPDYrri", LIEF::assembly::x86::OPCODE::VBLENDPDYrri) + .value("VBLENDPDrmi", LIEF::assembly::x86::OPCODE::VBLENDPDrmi) + .value("VBLENDPDrri", LIEF::assembly::x86::OPCODE::VBLENDPDrri) + .value("VBLENDPSYrmi", LIEF::assembly::x86::OPCODE::VBLENDPSYrmi) + .value("VBLENDPSYrri", LIEF::assembly::x86::OPCODE::VBLENDPSYrri) + .value("VBLENDPSrmi", LIEF::assembly::x86::OPCODE::VBLENDPSrmi) + .value("VBLENDPSrri", LIEF::assembly::x86::OPCODE::VBLENDPSrri) + .value("VBLENDVPDYrmr", LIEF::assembly::x86::OPCODE::VBLENDVPDYrmr) + .value("VBLENDVPDYrrr", LIEF::assembly::x86::OPCODE::VBLENDVPDYrrr) + .value("VBLENDVPDrmr", LIEF::assembly::x86::OPCODE::VBLENDVPDrmr) + .value("VBLENDVPDrrr", LIEF::assembly::x86::OPCODE::VBLENDVPDrrr) + .value("VBLENDVPSYrmr", LIEF::assembly::x86::OPCODE::VBLENDVPSYrmr) + .value("VBLENDVPSYrrr", LIEF::assembly::x86::OPCODE::VBLENDVPSYrrr) + .value("VBLENDVPSrmr", LIEF::assembly::x86::OPCODE::VBLENDVPSrmr) + .value("VBLENDVPSrrr", LIEF::assembly::x86::OPCODE::VBLENDVPSrrr) + .value("VBROADCASTF128rm", LIEF::assembly::x86::OPCODE::VBROADCASTF128rm) + .value("VBROADCASTF32X2Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rm) + .value("VBROADCASTF32X2Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rmk) + .value("VBROADCASTF32X2Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rmkz) + .value("VBROADCASTF32X2Z256rr", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rr) + .value("VBROADCASTF32X2Z256rrk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rrk) + .value("VBROADCASTF32X2Z256rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Z256rrkz) + .value("VBROADCASTF32X2Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrm) + .value("VBROADCASTF32X2Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrmk) + .value("VBROADCASTF32X2Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrmkz) + .value("VBROADCASTF32X2Zrr", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrr) + .value("VBROADCASTF32X2Zrrk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrrk) + .value("VBROADCASTF32X2Zrrkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X2Zrrkz) + .value("VBROADCASTF32X4Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Z256rm) + .value("VBROADCASTF32X4Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Z256rmk) + .value("VBROADCASTF32X4Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Z256rmkz) + .value("VBROADCASTF32X4Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Zrm) + .value("VBROADCASTF32X4Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Zrmk) + .value("VBROADCASTF32X4Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X4Zrmkz) + .value("VBROADCASTF32X8Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTF32X8Zrm) + .value("VBROADCASTF32X8Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTF32X8Zrmk) + .value("VBROADCASTF32X8Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF32X8Zrmkz) + .value("VBROADCASTF64X2Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Z256rm) + .value("VBROADCASTF64X2Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Z256rmk) + .value("VBROADCASTF64X2Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Z256rmkz) + .value("VBROADCASTF64X2Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Zrm) + .value("VBROADCASTF64X2Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Zrmk) + .value("VBROADCASTF64X2Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF64X2Zrmkz) + .value("VBROADCASTF64X4Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTF64X4Zrm) + .value("VBROADCASTF64X4Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTF64X4Zrmk) + .value("VBROADCASTF64X4Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTF64X4Zrmkz) + .value("VBROADCASTI128rm", LIEF::assembly::x86::OPCODE::VBROADCASTI128rm) + .value("VBROADCASTI32X2Z128rm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rm) + .value("VBROADCASTI32X2Z128rmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rmk) + .value("VBROADCASTI32X2Z128rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rmkz) + .value("VBROADCASTI32X2Z128rr", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rr) + .value("VBROADCASTI32X2Z128rrk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rrk) + .value("VBROADCASTI32X2Z128rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z128rrkz) + .value("VBROADCASTI32X2Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rm) + .value("VBROADCASTI32X2Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rmk) + .value("VBROADCASTI32X2Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rmkz) + .value("VBROADCASTI32X2Z256rr", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rr) + .value("VBROADCASTI32X2Z256rrk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rrk) + .value("VBROADCASTI32X2Z256rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Z256rrkz) + .value("VBROADCASTI32X2Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrm) + .value("VBROADCASTI32X2Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrmk) + .value("VBROADCASTI32X2Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrmkz) + .value("VBROADCASTI32X2Zrr", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrr) + .value("VBROADCASTI32X2Zrrk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrrk) + .value("VBROADCASTI32X2Zrrkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X2Zrrkz) + .value("VBROADCASTI32X4Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Z256rm) + .value("VBROADCASTI32X4Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Z256rmk) + .value("VBROADCASTI32X4Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Z256rmkz) + .value("VBROADCASTI32X4Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Zrm) + .value("VBROADCASTI32X4Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Zrmk) + .value("VBROADCASTI32X4Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X4Zrmkz) + .value("VBROADCASTI32X8Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTI32X8Zrm) + .value("VBROADCASTI32X8Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTI32X8Zrmk) + .value("VBROADCASTI32X8Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI32X8Zrmkz) + .value("VBROADCASTI64X2Z256rm", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Z256rm) + .value("VBROADCASTI64X2Z256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Z256rmk) + .value("VBROADCASTI64X2Z256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Z256rmkz) + .value("VBROADCASTI64X2Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Zrm) + .value("VBROADCASTI64X2Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Zrmk) + .value("VBROADCASTI64X2Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI64X2Zrmkz) + .value("VBROADCASTI64X4Zrm", LIEF::assembly::x86::OPCODE::VBROADCASTI64X4Zrm) + .value("VBROADCASTI64X4Zrmk", LIEF::assembly::x86::OPCODE::VBROADCASTI64X4Zrmk) + .value("VBROADCASTI64X4Zrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTI64X4Zrmkz) + .value("VBROADCASTSDYrm", LIEF::assembly::x86::OPCODE::VBROADCASTSDYrm) + .value("VBROADCASTSDYrr", LIEF::assembly::x86::OPCODE::VBROADCASTSDYrr) + .value("VBROADCASTSDZ256rm", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rm) + .value("VBROADCASTSDZ256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rmk) + .value("VBROADCASTSDZ256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rmkz) + .value("VBROADCASTSDZ256rr", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rr) + .value("VBROADCASTSDZ256rrk", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rrk) + .value("VBROADCASTSDZ256rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTSDZ256rrkz) + .value("VBROADCASTSDZrm", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrm) + .value("VBROADCASTSDZrmk", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrmk) + .value("VBROADCASTSDZrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrmkz) + .value("VBROADCASTSDZrr", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrr) + .value("VBROADCASTSDZrrk", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrrk) + .value("VBROADCASTSDZrrkz", LIEF::assembly::x86::OPCODE::VBROADCASTSDZrrkz) + .value("VBROADCASTSSYrm", LIEF::assembly::x86::OPCODE::VBROADCASTSSYrm) + .value("VBROADCASTSSYrr", LIEF::assembly::x86::OPCODE::VBROADCASTSSYrr) + .value("VBROADCASTSSZ128rm", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rm) + .value("VBROADCASTSSZ128rmk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rmk) + .value("VBROADCASTSSZ128rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rmkz) + .value("VBROADCASTSSZ128rr", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rr) + .value("VBROADCASTSSZ128rrk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rrk) + .value("VBROADCASTSSZ128rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ128rrkz) + .value("VBROADCASTSSZ256rm", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rm) + .value("VBROADCASTSSZ256rmk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rmk) + .value("VBROADCASTSSZ256rmkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rmkz) + .value("VBROADCASTSSZ256rr", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rr) + .value("VBROADCASTSSZ256rrk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rrk) + .value("VBROADCASTSSZ256rrkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZ256rrkz) + .value("VBROADCASTSSZrm", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrm) + .value("VBROADCASTSSZrmk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrmk) + .value("VBROADCASTSSZrmkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrmkz) + .value("VBROADCASTSSZrr", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrr) + .value("VBROADCASTSSZrrk", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrrk) + .value("VBROADCASTSSZrrkz", LIEF::assembly::x86::OPCODE::VBROADCASTSSZrrkz) + .value("VBROADCASTSSrm", LIEF::assembly::x86::OPCODE::VBROADCASTSSrm) + .value("VBROADCASTSSrr", LIEF::assembly::x86::OPCODE::VBROADCASTSSrr) + .value("VCMPBF16Z128rmbi", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rmbi) + .value("VCMPBF16Z128rmbik", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rmbik) + .value("VCMPBF16Z128rmi", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rmi) + .value("VCMPBF16Z128rmik", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rmik); + opcodes.value("VCMPBF16Z128rri", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rri) + .value("VCMPBF16Z128rrik", LIEF::assembly::x86::OPCODE::VCMPBF16Z128rrik) + .value("VCMPBF16Z256rmbi", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rmbi) + .value("VCMPBF16Z256rmbik", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rmbik) + .value("VCMPBF16Z256rmi", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rmi) + .value("VCMPBF16Z256rmik", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rmik) + .value("VCMPBF16Z256rri", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rri) + .value("VCMPBF16Z256rrik", LIEF::assembly::x86::OPCODE::VCMPBF16Z256rrik) + .value("VCMPBF16Zrmbi", LIEF::assembly::x86::OPCODE::VCMPBF16Zrmbi) + .value("VCMPBF16Zrmbik", LIEF::assembly::x86::OPCODE::VCMPBF16Zrmbik) + .value("VCMPBF16Zrmi", LIEF::assembly::x86::OPCODE::VCMPBF16Zrmi) + .value("VCMPBF16Zrmik", LIEF::assembly::x86::OPCODE::VCMPBF16Zrmik) + .value("VCMPBF16Zrri", LIEF::assembly::x86::OPCODE::VCMPBF16Zrri) + .value("VCMPBF16Zrrik", LIEF::assembly::x86::OPCODE::VCMPBF16Zrrik) + .value("VCMPPDYrmi", LIEF::assembly::x86::OPCODE::VCMPPDYrmi) + .value("VCMPPDYrri", LIEF::assembly::x86::OPCODE::VCMPPDYrri) + .value("VCMPPDZ128rmbi", LIEF::assembly::x86::OPCODE::VCMPPDZ128rmbi) + .value("VCMPPDZ128rmbik", LIEF::assembly::x86::OPCODE::VCMPPDZ128rmbik) + .value("VCMPPDZ128rmi", LIEF::assembly::x86::OPCODE::VCMPPDZ128rmi) + .value("VCMPPDZ128rmik", LIEF::assembly::x86::OPCODE::VCMPPDZ128rmik) + .value("VCMPPDZ128rri", LIEF::assembly::x86::OPCODE::VCMPPDZ128rri) + .value("VCMPPDZ128rrik", LIEF::assembly::x86::OPCODE::VCMPPDZ128rrik) + .value("VCMPPDZ256rmbi", LIEF::assembly::x86::OPCODE::VCMPPDZ256rmbi) + .value("VCMPPDZ256rmbik", LIEF::assembly::x86::OPCODE::VCMPPDZ256rmbik) + .value("VCMPPDZ256rmi", LIEF::assembly::x86::OPCODE::VCMPPDZ256rmi) + .value("VCMPPDZ256rmik", LIEF::assembly::x86::OPCODE::VCMPPDZ256rmik) + .value("VCMPPDZ256rri", LIEF::assembly::x86::OPCODE::VCMPPDZ256rri) + .value("VCMPPDZ256rrik", LIEF::assembly::x86::OPCODE::VCMPPDZ256rrik) + .value("VCMPPDZrmbi", LIEF::assembly::x86::OPCODE::VCMPPDZrmbi) + .value("VCMPPDZrmbik", LIEF::assembly::x86::OPCODE::VCMPPDZrmbik) + .value("VCMPPDZrmi", LIEF::assembly::x86::OPCODE::VCMPPDZrmi) + .value("VCMPPDZrmik", LIEF::assembly::x86::OPCODE::VCMPPDZrmik) + .value("VCMPPDZrri", LIEF::assembly::x86::OPCODE::VCMPPDZrri) + .value("VCMPPDZrrib", LIEF::assembly::x86::OPCODE::VCMPPDZrrib) + .value("VCMPPDZrribk", LIEF::assembly::x86::OPCODE::VCMPPDZrribk) + .value("VCMPPDZrrik", LIEF::assembly::x86::OPCODE::VCMPPDZrrik) + .value("VCMPPDrmi", LIEF::assembly::x86::OPCODE::VCMPPDrmi) + .value("VCMPPDrri", LIEF::assembly::x86::OPCODE::VCMPPDrri) + .value("VCMPPHZ128rmbi", LIEF::assembly::x86::OPCODE::VCMPPHZ128rmbi) + .value("VCMPPHZ128rmbik", LIEF::assembly::x86::OPCODE::VCMPPHZ128rmbik) + .value("VCMPPHZ128rmi", LIEF::assembly::x86::OPCODE::VCMPPHZ128rmi) + .value("VCMPPHZ128rmik", LIEF::assembly::x86::OPCODE::VCMPPHZ128rmik) + .value("VCMPPHZ128rri", LIEF::assembly::x86::OPCODE::VCMPPHZ128rri) + .value("VCMPPHZ128rrik", LIEF::assembly::x86::OPCODE::VCMPPHZ128rrik) + .value("VCMPPHZ256rmbi", LIEF::assembly::x86::OPCODE::VCMPPHZ256rmbi) + .value("VCMPPHZ256rmbik", LIEF::assembly::x86::OPCODE::VCMPPHZ256rmbik) + .value("VCMPPHZ256rmi", LIEF::assembly::x86::OPCODE::VCMPPHZ256rmi) + .value("VCMPPHZ256rmik", LIEF::assembly::x86::OPCODE::VCMPPHZ256rmik) + .value("VCMPPHZ256rri", LIEF::assembly::x86::OPCODE::VCMPPHZ256rri) + .value("VCMPPHZ256rrik", LIEF::assembly::x86::OPCODE::VCMPPHZ256rrik) + .value("VCMPPHZrmbi", LIEF::assembly::x86::OPCODE::VCMPPHZrmbi) + .value("VCMPPHZrmbik", LIEF::assembly::x86::OPCODE::VCMPPHZrmbik) + .value("VCMPPHZrmi", LIEF::assembly::x86::OPCODE::VCMPPHZrmi) + .value("VCMPPHZrmik", LIEF::assembly::x86::OPCODE::VCMPPHZrmik) + .value("VCMPPHZrri", LIEF::assembly::x86::OPCODE::VCMPPHZrri) + .value("VCMPPHZrrib", LIEF::assembly::x86::OPCODE::VCMPPHZrrib) + .value("VCMPPHZrribk", LIEF::assembly::x86::OPCODE::VCMPPHZrribk) + .value("VCMPPHZrrik", LIEF::assembly::x86::OPCODE::VCMPPHZrrik) + .value("VCMPPSYrmi", LIEF::assembly::x86::OPCODE::VCMPPSYrmi) + .value("VCMPPSYrri", LIEF::assembly::x86::OPCODE::VCMPPSYrri) + .value("VCMPPSZ128rmbi", LIEF::assembly::x86::OPCODE::VCMPPSZ128rmbi) + .value("VCMPPSZ128rmbik", LIEF::assembly::x86::OPCODE::VCMPPSZ128rmbik) + .value("VCMPPSZ128rmi", LIEF::assembly::x86::OPCODE::VCMPPSZ128rmi) + .value("VCMPPSZ128rmik", LIEF::assembly::x86::OPCODE::VCMPPSZ128rmik) + .value("VCMPPSZ128rri", LIEF::assembly::x86::OPCODE::VCMPPSZ128rri) + .value("VCMPPSZ128rrik", LIEF::assembly::x86::OPCODE::VCMPPSZ128rrik) + .value("VCMPPSZ256rmbi", LIEF::assembly::x86::OPCODE::VCMPPSZ256rmbi) + .value("VCMPPSZ256rmbik", LIEF::assembly::x86::OPCODE::VCMPPSZ256rmbik) + .value("VCMPPSZ256rmi", LIEF::assembly::x86::OPCODE::VCMPPSZ256rmi) + .value("VCMPPSZ256rmik", LIEF::assembly::x86::OPCODE::VCMPPSZ256rmik) + .value("VCMPPSZ256rri", LIEF::assembly::x86::OPCODE::VCMPPSZ256rri) + .value("VCMPPSZ256rrik", LIEF::assembly::x86::OPCODE::VCMPPSZ256rrik) + .value("VCMPPSZrmbi", LIEF::assembly::x86::OPCODE::VCMPPSZrmbi) + .value("VCMPPSZrmbik", LIEF::assembly::x86::OPCODE::VCMPPSZrmbik) + .value("VCMPPSZrmi", LIEF::assembly::x86::OPCODE::VCMPPSZrmi) + .value("VCMPPSZrmik", LIEF::assembly::x86::OPCODE::VCMPPSZrmik) + .value("VCMPPSZrri", LIEF::assembly::x86::OPCODE::VCMPPSZrri) + .value("VCMPPSZrrib", LIEF::assembly::x86::OPCODE::VCMPPSZrrib) + .value("VCMPPSZrribk", LIEF::assembly::x86::OPCODE::VCMPPSZrribk) + .value("VCMPPSZrrik", LIEF::assembly::x86::OPCODE::VCMPPSZrrik) + .value("VCMPPSrmi", LIEF::assembly::x86::OPCODE::VCMPPSrmi) + .value("VCMPPSrri", LIEF::assembly::x86::OPCODE::VCMPPSrri) + .value("VCMPSDZrmi", LIEF::assembly::x86::OPCODE::VCMPSDZrmi) + .value("VCMPSDZrmi_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrmi_Int) + .value("VCMPSDZrmik_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrmik_Int) + .value("VCMPSDZrri", LIEF::assembly::x86::OPCODE::VCMPSDZrri) + .value("VCMPSDZrri_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrri_Int) + .value("VCMPSDZrrib_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrrib_Int) + .value("VCMPSDZrribk_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrribk_Int) + .value("VCMPSDZrrik_Int", LIEF::assembly::x86::OPCODE::VCMPSDZrrik_Int) + .value("VCMPSDrmi", LIEF::assembly::x86::OPCODE::VCMPSDrmi) + .value("VCMPSDrmi_Int", LIEF::assembly::x86::OPCODE::VCMPSDrmi_Int) + .value("VCMPSDrri", LIEF::assembly::x86::OPCODE::VCMPSDrri) + .value("VCMPSDrri_Int", LIEF::assembly::x86::OPCODE::VCMPSDrri_Int) + .value("VCMPSHZrmi", LIEF::assembly::x86::OPCODE::VCMPSHZrmi) + .value("VCMPSHZrmi_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrmi_Int) + .value("VCMPSHZrmik_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrmik_Int) + .value("VCMPSHZrri", LIEF::assembly::x86::OPCODE::VCMPSHZrri) + .value("VCMPSHZrri_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrri_Int) + .value("VCMPSHZrrib_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrrib_Int) + .value("VCMPSHZrribk_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrribk_Int) + .value("VCMPSHZrrik_Int", LIEF::assembly::x86::OPCODE::VCMPSHZrrik_Int) + .value("VCMPSSZrmi", LIEF::assembly::x86::OPCODE::VCMPSSZrmi) + .value("VCMPSSZrmi_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrmi_Int) + .value("VCMPSSZrmik_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrmik_Int) + .value("VCMPSSZrri", LIEF::assembly::x86::OPCODE::VCMPSSZrri) + .value("VCMPSSZrri_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrri_Int) + .value("VCMPSSZrrib_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrrib_Int) + .value("VCMPSSZrribk_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrribk_Int) + .value("VCMPSSZrrik_Int", LIEF::assembly::x86::OPCODE::VCMPSSZrrik_Int) + .value("VCMPSSrmi", LIEF::assembly::x86::OPCODE::VCMPSSrmi) + .value("VCMPSSrmi_Int", LIEF::assembly::x86::OPCODE::VCMPSSrmi_Int) + .value("VCMPSSrri", LIEF::assembly::x86::OPCODE::VCMPSSrri) + .value("VCMPSSrri_Int", LIEF::assembly::x86::OPCODE::VCMPSSrri_Int) + .value("VCOMISBF16Zrm", LIEF::assembly::x86::OPCODE::VCOMISBF16Zrm) + .value("VCOMISBF16Zrm_Int", LIEF::assembly::x86::OPCODE::VCOMISBF16Zrm_Int) + .value("VCOMISBF16Zrr", LIEF::assembly::x86::OPCODE::VCOMISBF16Zrr) + .value("VCOMISBF16Zrr_Int", LIEF::assembly::x86::OPCODE::VCOMISBF16Zrr_Int) + .value("VCOMISDZrm", LIEF::assembly::x86::OPCODE::VCOMISDZrm) + .value("VCOMISDZrm_Int", LIEF::assembly::x86::OPCODE::VCOMISDZrm_Int) + .value("VCOMISDZrr", LIEF::assembly::x86::OPCODE::VCOMISDZrr) + .value("VCOMISDZrr_Int", LIEF::assembly::x86::OPCODE::VCOMISDZrr_Int) + .value("VCOMISDZrrb", LIEF::assembly::x86::OPCODE::VCOMISDZrrb) + .value("VCOMISDrm", LIEF::assembly::x86::OPCODE::VCOMISDrm) + .value("VCOMISDrm_Int", LIEF::assembly::x86::OPCODE::VCOMISDrm_Int) + .value("VCOMISDrr", LIEF::assembly::x86::OPCODE::VCOMISDrr) + .value("VCOMISDrr_Int", LIEF::assembly::x86::OPCODE::VCOMISDrr_Int) + .value("VCOMISHZrm", LIEF::assembly::x86::OPCODE::VCOMISHZrm) + .value("VCOMISHZrm_Int", LIEF::assembly::x86::OPCODE::VCOMISHZrm_Int) + .value("VCOMISHZrr", LIEF::assembly::x86::OPCODE::VCOMISHZrr) + .value("VCOMISHZrr_Int", LIEF::assembly::x86::OPCODE::VCOMISHZrr_Int) + .value("VCOMISHZrrb", LIEF::assembly::x86::OPCODE::VCOMISHZrrb) + .value("VCOMISSZrm", LIEF::assembly::x86::OPCODE::VCOMISSZrm) + .value("VCOMISSZrm_Int", LIEF::assembly::x86::OPCODE::VCOMISSZrm_Int) + .value("VCOMISSZrr", LIEF::assembly::x86::OPCODE::VCOMISSZrr) + .value("VCOMISSZrr_Int", LIEF::assembly::x86::OPCODE::VCOMISSZrr_Int) + .value("VCOMISSZrrb", LIEF::assembly::x86::OPCODE::VCOMISSZrrb) + .value("VCOMISSrm", LIEF::assembly::x86::OPCODE::VCOMISSrm) + .value("VCOMISSrm_Int", LIEF::assembly::x86::OPCODE::VCOMISSrm_Int) + .value("VCOMISSrr", LIEF::assembly::x86::OPCODE::VCOMISSrr) + .value("VCOMISSrr_Int", LIEF::assembly::x86::OPCODE::VCOMISSrr_Int) + .value("VCOMPRESSPDZ128mr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ128mr) + .value("VCOMPRESSPDZ128mrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ128mrk) + .value("VCOMPRESSPDZ128rr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ128rr) + .value("VCOMPRESSPDZ128rrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ128rrk) + .value("VCOMPRESSPDZ128rrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ128rrkz) + .value("VCOMPRESSPDZ256mr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ256mr) + .value("VCOMPRESSPDZ256mrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ256mrk) + .value("VCOMPRESSPDZ256rr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ256rr) + .value("VCOMPRESSPDZ256rrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ256rrk) + .value("VCOMPRESSPDZ256rrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZ256rrkz) + .value("VCOMPRESSPDZmr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZmr) + .value("VCOMPRESSPDZmrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZmrk) + .value("VCOMPRESSPDZrr", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZrr) + .value("VCOMPRESSPDZrrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZrrk) + .value("VCOMPRESSPDZrrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPDZrrkz) + .value("VCOMPRESSPSZ128mr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ128mr) + .value("VCOMPRESSPSZ128mrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ128mrk) + .value("VCOMPRESSPSZ128rr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ128rr) + .value("VCOMPRESSPSZ128rrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ128rrk) + .value("VCOMPRESSPSZ128rrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ128rrkz) + .value("VCOMPRESSPSZ256mr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ256mr) + .value("VCOMPRESSPSZ256mrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ256mrk) + .value("VCOMPRESSPSZ256rr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ256rr) + .value("VCOMPRESSPSZ256rrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ256rrk) + .value("VCOMPRESSPSZ256rrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZ256rrkz) + .value("VCOMPRESSPSZmr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZmr) + .value("VCOMPRESSPSZmrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZmrk) + .value("VCOMPRESSPSZrr", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZrr) + .value("VCOMPRESSPSZrrk", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZrrk) + .value("VCOMPRESSPSZrrkz", LIEF::assembly::x86::OPCODE::VCOMPRESSPSZrrkz) + .value("VCOMXSDZrm_Int", LIEF::assembly::x86::OPCODE::VCOMXSDZrm_Int) + .value("VCOMXSDZrr_Int", LIEF::assembly::x86::OPCODE::VCOMXSDZrr_Int) + .value("VCOMXSDZrrb_Int", LIEF::assembly::x86::OPCODE::VCOMXSDZrrb_Int) + .value("VCOMXSHZrm_Int", LIEF::assembly::x86::OPCODE::VCOMXSHZrm_Int) + .value("VCOMXSHZrr_Int", LIEF::assembly::x86::OPCODE::VCOMXSHZrr_Int) + .value("VCOMXSHZrrb_Int", LIEF::assembly::x86::OPCODE::VCOMXSHZrrb_Int) + .value("VCOMXSSZrm_Int", LIEF::assembly::x86::OPCODE::VCOMXSSZrm_Int) + .value("VCOMXSSZrr_Int", LIEF::assembly::x86::OPCODE::VCOMXSSZrr_Int) + .value("VCOMXSSZrrb_Int", LIEF::assembly::x86::OPCODE::VCOMXSSZrrb_Int) + .value("VCVT2PH2BF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rm) + .value("VCVT2PH2BF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rmb) + .value("VCVT2PH2BF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rmbk) + .value("VCVT2PH2BF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rmbkz) + .value("VCVT2PH2BF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rmk) + .value("VCVT2PH2BF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rmkz) + .value("VCVT2PH2BF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rr) + .value("VCVT2PH2BF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rrk) + .value("VCVT2PH2BF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ128rrkz) + .value("VCVT2PH2BF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rm) + .value("VCVT2PH2BF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rmb) + .value("VCVT2PH2BF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rmbk) + .value("VCVT2PH2BF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rmbkz) + .value("VCVT2PH2BF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rmk) + .value("VCVT2PH2BF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rmkz) + .value("VCVT2PH2BF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rr) + .value("VCVT2PH2BF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rrk) + .value("VCVT2PH2BF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZ256rrkz) + .value("VCVT2PH2BF8SZrm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrm) + .value("VCVT2PH2BF8SZrmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrmb) + .value("VCVT2PH2BF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrmbk) + .value("VCVT2PH2BF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrmbkz) + .value("VCVT2PH2BF8SZrmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrmk) + .value("VCVT2PH2BF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrmkz) + .value("VCVT2PH2BF8SZrr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrr) + .value("VCVT2PH2BF8SZrrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrrk) + .value("VCVT2PH2BF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8SZrrkz) + .value("VCVT2PH2BF8Z128rm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rm) + .value("VCVT2PH2BF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rmb) + .value("VCVT2PH2BF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rmbk) + .value("VCVT2PH2BF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rmbkz) + .value("VCVT2PH2BF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rmk) + .value("VCVT2PH2BF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rmkz) + .value("VCVT2PH2BF8Z128rr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rr) + .value("VCVT2PH2BF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rrk) + .value("VCVT2PH2BF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z128rrkz) + .value("VCVT2PH2BF8Z256rm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rm) + .value("VCVT2PH2BF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rmb) + .value("VCVT2PH2BF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rmbk) + .value("VCVT2PH2BF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rmbkz) + .value("VCVT2PH2BF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rmk) + .value("VCVT2PH2BF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rmkz) + .value("VCVT2PH2BF8Z256rr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rr) + .value("VCVT2PH2BF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rrk) + .value("VCVT2PH2BF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Z256rrkz) + .value("VCVT2PH2BF8Zrm", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrm) + .value("VCVT2PH2BF8Zrmb", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrmb) + .value("VCVT2PH2BF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrmbk) + .value("VCVT2PH2BF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrmbkz) + .value("VCVT2PH2BF8Zrmk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrmk) + .value("VCVT2PH2BF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrmkz) + .value("VCVT2PH2BF8Zrr", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrr) + .value("VCVT2PH2BF8Zrrk", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrrk) + .value("VCVT2PH2BF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2BF8Zrrkz) + .value("VCVT2PH2HF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rm) + .value("VCVT2PH2HF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rmb) + .value("VCVT2PH2HF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rmbk) + .value("VCVT2PH2HF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rmbkz) + .value("VCVT2PH2HF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rmk) + .value("VCVT2PH2HF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rmkz) + .value("VCVT2PH2HF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rr) + .value("VCVT2PH2HF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rrk) + .value("VCVT2PH2HF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ128rrkz) + .value("VCVT2PH2HF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rm) + .value("VCVT2PH2HF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rmb) + .value("VCVT2PH2HF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rmbk) + .value("VCVT2PH2HF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rmbkz) + .value("VCVT2PH2HF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rmk) + .value("VCVT2PH2HF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rmkz) + .value("VCVT2PH2HF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rr) + .value("VCVT2PH2HF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rrk) + .value("VCVT2PH2HF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZ256rrkz) + .value("VCVT2PH2HF8SZrm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrm) + .value("VCVT2PH2HF8SZrmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrmb) + .value("VCVT2PH2HF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrmbk) + .value("VCVT2PH2HF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrmbkz) + .value("VCVT2PH2HF8SZrmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrmk) + .value("VCVT2PH2HF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrmkz) + .value("VCVT2PH2HF8SZrr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrr) + .value("VCVT2PH2HF8SZrrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrrk) + .value("VCVT2PH2HF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8SZrrkz) + .value("VCVT2PH2HF8Z128rm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rm) + .value("VCVT2PH2HF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rmb) + .value("VCVT2PH2HF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rmbk) + .value("VCVT2PH2HF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rmbkz) + .value("VCVT2PH2HF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rmk) + .value("VCVT2PH2HF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rmkz) + .value("VCVT2PH2HF8Z128rr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rr) + .value("VCVT2PH2HF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rrk) + .value("VCVT2PH2HF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z128rrkz) + .value("VCVT2PH2HF8Z256rm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rm) + .value("VCVT2PH2HF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rmb) + .value("VCVT2PH2HF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rmbk) + .value("VCVT2PH2HF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rmbkz) + .value("VCVT2PH2HF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rmk) + .value("VCVT2PH2HF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rmkz) + .value("VCVT2PH2HF8Z256rr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rr) + .value("VCVT2PH2HF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rrk) + .value("VCVT2PH2HF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Z256rrkz) + .value("VCVT2PH2HF8Zrm", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrm) + .value("VCVT2PH2HF8Zrmb", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrmb) + .value("VCVT2PH2HF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrmbk) + .value("VCVT2PH2HF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrmbkz) + .value("VCVT2PH2HF8Zrmk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrmk) + .value("VCVT2PH2HF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrmkz) + .value("VCVT2PH2HF8Zrr", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrr) + .value("VCVT2PH2HF8Zrrk", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrrk) + .value("VCVT2PH2HF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVT2PH2HF8Zrrkz) + .value("VCVT2PS2PHXZ128rm", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rm) + .value("VCVT2PS2PHXZ128rmb", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rmb) + .value("VCVT2PS2PHXZ128rmbk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rmbk) + .value("VCVT2PS2PHXZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rmbkz) + .value("VCVT2PS2PHXZ128rmk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rmk) + .value("VCVT2PS2PHXZ128rmkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rmkz) + .value("VCVT2PS2PHXZ128rr", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rr) + .value("VCVT2PS2PHXZ128rrk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rrk) + .value("VCVT2PS2PHXZ128rrkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ128rrkz) + .value("VCVT2PS2PHXZ256rm", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rm) + .value("VCVT2PS2PHXZ256rmb", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rmb) + .value("VCVT2PS2PHXZ256rmbk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rmbk); + opcodes.value("VCVT2PS2PHXZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rmbkz) + .value("VCVT2PS2PHXZ256rmk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rmk) + .value("VCVT2PS2PHXZ256rmkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rmkz) + .value("VCVT2PS2PHXZ256rr", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rr) + .value("VCVT2PS2PHXZ256rrk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rrk) + .value("VCVT2PS2PHXZ256rrkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZ256rrkz) + .value("VCVT2PS2PHXZrm", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrm) + .value("VCVT2PS2PHXZrmb", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrmb) + .value("VCVT2PS2PHXZrmbk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrmbk) + .value("VCVT2PS2PHXZrmbkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrmbkz) + .value("VCVT2PS2PHXZrmk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrmk) + .value("VCVT2PS2PHXZrmkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrmkz) + .value("VCVT2PS2PHXZrr", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrr) + .value("VCVT2PS2PHXZrrb", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrrb) + .value("VCVT2PS2PHXZrrbk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrrbk) + .value("VCVT2PS2PHXZrrbkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrrbkz) + .value("VCVT2PS2PHXZrrk", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrrk) + .value("VCVT2PS2PHXZrrkz", LIEF::assembly::x86::OPCODE::VCVT2PS2PHXZrrkz) + .value("VCVTBF162IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rm) + .value("VCVTBF162IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rmb) + .value("VCVTBF162IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rmbk) + .value("VCVTBF162IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rmbkz) + .value("VCVTBF162IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rmk) + .value("VCVTBF162IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rmkz) + .value("VCVTBF162IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rr) + .value("VCVTBF162IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rrk) + .value("VCVTBF162IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ128rrkz) + .value("VCVTBF162IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rm) + .value("VCVTBF162IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rmb) + .value("VCVTBF162IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rmbk) + .value("VCVTBF162IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rmbkz) + .value("VCVTBF162IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rmk) + .value("VCVTBF162IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rmkz) + .value("VCVTBF162IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rr) + .value("VCVTBF162IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rrk) + .value("VCVTBF162IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZ256rrkz) + .value("VCVTBF162IBSZrm", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrm) + .value("VCVTBF162IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrmb) + .value("VCVTBF162IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrmbk) + .value("VCVTBF162IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrmbkz) + .value("VCVTBF162IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrmk) + .value("VCVTBF162IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrmkz) + .value("VCVTBF162IBSZrr", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrr) + .value("VCVTBF162IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrrk) + .value("VCVTBF162IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IBSZrrkz) + .value("VCVTBF162IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rm) + .value("VCVTBF162IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rmb) + .value("VCVTBF162IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rmbk) + .value("VCVTBF162IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rmbkz) + .value("VCVTBF162IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rmk) + .value("VCVTBF162IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rmkz) + .value("VCVTBF162IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rr) + .value("VCVTBF162IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rrk) + .value("VCVTBF162IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ128rrkz) + .value("VCVTBF162IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rm) + .value("VCVTBF162IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rmb) + .value("VCVTBF162IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rmbk) + .value("VCVTBF162IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rmbkz) + .value("VCVTBF162IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rmk) + .value("VCVTBF162IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rmkz) + .value("VCVTBF162IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rr) + .value("VCVTBF162IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rrk) + .value("VCVTBF162IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZ256rrkz) + .value("VCVTBF162IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrm) + .value("VCVTBF162IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrmb) + .value("VCVTBF162IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrmbk) + .value("VCVTBF162IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrmbkz) + .value("VCVTBF162IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrmk) + .value("VCVTBF162IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrmkz) + .value("VCVTBF162IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrr) + .value("VCVTBF162IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrrk) + .value("VCVTBF162IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTBF162IUBSZrrkz) + .value("VCVTBIASPH2BF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rm) + .value("VCVTBIASPH2BF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rmb) + .value("VCVTBIASPH2BF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rmbk) + .value("VCVTBIASPH2BF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rmbkz) + .value("VCVTBIASPH2BF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rmk) + .value("VCVTBIASPH2BF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rmkz) + .value("VCVTBIASPH2BF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rr) + .value("VCVTBIASPH2BF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rrk) + .value("VCVTBIASPH2BF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ128rrkz) + .value("VCVTBIASPH2BF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rm) + .value("VCVTBIASPH2BF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rmb) + .value("VCVTBIASPH2BF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rmbk) + .value("VCVTBIASPH2BF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rmbkz) + .value("VCVTBIASPH2BF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rmk) + .value("VCVTBIASPH2BF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rmkz) + .value("VCVTBIASPH2BF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rr) + .value("VCVTBIASPH2BF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rrk) + .value("VCVTBIASPH2BF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZ256rrkz) + .value("VCVTBIASPH2BF8SZrm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrm) + .value("VCVTBIASPH2BF8SZrmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrmb) + .value("VCVTBIASPH2BF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrmbk) + .value("VCVTBIASPH2BF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrmbkz) + .value("VCVTBIASPH2BF8SZrmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrmk) + .value("VCVTBIASPH2BF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrmkz) + .value("VCVTBIASPH2BF8SZrr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrr) + .value("VCVTBIASPH2BF8SZrrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrrk) + .value("VCVTBIASPH2BF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8SZrrkz) + .value("VCVTBIASPH2BF8Z128rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rm) + .value("VCVTBIASPH2BF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rmb) + .value("VCVTBIASPH2BF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rmbk) + .value("VCVTBIASPH2BF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rmbkz) + .value("VCVTBIASPH2BF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rmk) + .value("VCVTBIASPH2BF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rmkz) + .value("VCVTBIASPH2BF8Z128rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rr) + .value("VCVTBIASPH2BF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rrk) + .value("VCVTBIASPH2BF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z128rrkz) + .value("VCVTBIASPH2BF8Z256rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rm) + .value("VCVTBIASPH2BF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rmb) + .value("VCVTBIASPH2BF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rmbk) + .value("VCVTBIASPH2BF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rmbkz) + .value("VCVTBIASPH2BF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rmk) + .value("VCVTBIASPH2BF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rmkz) + .value("VCVTBIASPH2BF8Z256rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rr) + .value("VCVTBIASPH2BF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rrk) + .value("VCVTBIASPH2BF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Z256rrkz) + .value("VCVTBIASPH2BF8Zrm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrm) + .value("VCVTBIASPH2BF8Zrmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrmb) + .value("VCVTBIASPH2BF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrmbk) + .value("VCVTBIASPH2BF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrmbkz) + .value("VCVTBIASPH2BF8Zrmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrmk) + .value("VCVTBIASPH2BF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrmkz) + .value("VCVTBIASPH2BF8Zrr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrr) + .value("VCVTBIASPH2BF8Zrrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrrk) + .value("VCVTBIASPH2BF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2BF8Zrrkz) + .value("VCVTBIASPH2HF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rm) + .value("VCVTBIASPH2HF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rmb) + .value("VCVTBIASPH2HF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rmbk) + .value("VCVTBIASPH2HF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rmbkz) + .value("VCVTBIASPH2HF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rmk) + .value("VCVTBIASPH2HF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rmkz) + .value("VCVTBIASPH2HF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rr) + .value("VCVTBIASPH2HF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rrk) + .value("VCVTBIASPH2HF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ128rrkz) + .value("VCVTBIASPH2HF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rm) + .value("VCVTBIASPH2HF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rmb) + .value("VCVTBIASPH2HF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rmbk) + .value("VCVTBIASPH2HF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rmbkz) + .value("VCVTBIASPH2HF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rmk) + .value("VCVTBIASPH2HF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rmkz) + .value("VCVTBIASPH2HF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rr) + .value("VCVTBIASPH2HF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rrk) + .value("VCVTBIASPH2HF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZ256rrkz) + .value("VCVTBIASPH2HF8SZrm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrm) + .value("VCVTBIASPH2HF8SZrmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrmb) + .value("VCVTBIASPH2HF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrmbk) + .value("VCVTBIASPH2HF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrmbkz) + .value("VCVTBIASPH2HF8SZrmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrmk) + .value("VCVTBIASPH2HF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrmkz) + .value("VCVTBIASPH2HF8SZrr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrr) + .value("VCVTBIASPH2HF8SZrrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrrk) + .value("VCVTBIASPH2HF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8SZrrkz) + .value("VCVTBIASPH2HF8Z128rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rm) + .value("VCVTBIASPH2HF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rmb) + .value("VCVTBIASPH2HF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rmbk) + .value("VCVTBIASPH2HF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rmbkz) + .value("VCVTBIASPH2HF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rmk) + .value("VCVTBIASPH2HF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rmkz) + .value("VCVTBIASPH2HF8Z128rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rr) + .value("VCVTBIASPH2HF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rrk) + .value("VCVTBIASPH2HF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z128rrkz) + .value("VCVTBIASPH2HF8Z256rm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rm) + .value("VCVTBIASPH2HF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rmb) + .value("VCVTBIASPH2HF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rmbk) + .value("VCVTBIASPH2HF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rmbkz) + .value("VCVTBIASPH2HF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rmk) + .value("VCVTBIASPH2HF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rmkz) + .value("VCVTBIASPH2HF8Z256rr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rr) + .value("VCVTBIASPH2HF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rrk) + .value("VCVTBIASPH2HF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Z256rrkz) + .value("VCVTBIASPH2HF8Zrm", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrm) + .value("VCVTBIASPH2HF8Zrmb", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrmb) + .value("VCVTBIASPH2HF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrmbk) + .value("VCVTBIASPH2HF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrmbkz) + .value("VCVTBIASPH2HF8Zrmk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrmk) + .value("VCVTBIASPH2HF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrmkz) + .value("VCVTBIASPH2HF8Zrr", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrr) + .value("VCVTBIASPH2HF8Zrrk", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrrk) + .value("VCVTBIASPH2HF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVTBIASPH2HF8Zrrkz) + .value("VCVTDQ2PDYrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PDYrm) + .value("VCVTDQ2PDYrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PDYrr) + .value("VCVTDQ2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rm) + .value("VCVTDQ2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rmb) + .value("VCVTDQ2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rmbk) + .value("VCVTDQ2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rmbkz) + .value("VCVTDQ2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rmk) + .value("VCVTDQ2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rmkz) + .value("VCVTDQ2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rr) + .value("VCVTDQ2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rrk) + .value("VCVTDQ2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ128rrkz) + .value("VCVTDQ2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rm) + .value("VCVTDQ2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rmb) + .value("VCVTDQ2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rmbk) + .value("VCVTDQ2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rmbkz) + .value("VCVTDQ2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rmk) + .value("VCVTDQ2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rmkz) + .value("VCVTDQ2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rr) + .value("VCVTDQ2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rrk) + .value("VCVTDQ2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZ256rrkz) + .value("VCVTDQ2PDZrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrm) + .value("VCVTDQ2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrmb) + .value("VCVTDQ2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrmbk) + .value("VCVTDQ2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrmbkz) + .value("VCVTDQ2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrmk) + .value("VCVTDQ2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrmkz) + .value("VCVTDQ2PDZrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrr) + .value("VCVTDQ2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrrk) + .value("VCVTDQ2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PDZrrkz) + .value("VCVTDQ2PDrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PDrm) + .value("VCVTDQ2PDrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PDrr) + .value("VCVTDQ2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rm) + .value("VCVTDQ2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rmb) + .value("VCVTDQ2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rmbk) + .value("VCVTDQ2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rmbkz) + .value("VCVTDQ2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rmk) + .value("VCVTDQ2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rmkz) + .value("VCVTDQ2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rr) + .value("VCVTDQ2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rrk) + .value("VCVTDQ2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ128rrkz) + .value("VCVTDQ2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rm) + .value("VCVTDQ2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rmb) + .value("VCVTDQ2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rmbk) + .value("VCVTDQ2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rmbkz) + .value("VCVTDQ2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rmk) + .value("VCVTDQ2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rmkz) + .value("VCVTDQ2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rr) + .value("VCVTDQ2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rrk) + .value("VCVTDQ2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZ256rrkz) + .value("VCVTDQ2PHZrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrm) + .value("VCVTDQ2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrmb) + .value("VCVTDQ2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrmbk) + .value("VCVTDQ2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrmbkz) + .value("VCVTDQ2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrmk) + .value("VCVTDQ2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrmkz) + .value("VCVTDQ2PHZrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrr) + .value("VCVTDQ2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrrb) + .value("VCVTDQ2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrrbk) + .value("VCVTDQ2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrrbkz) + .value("VCVTDQ2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrrk) + .value("VCVTDQ2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PHZrrkz) + .value("VCVTDQ2PSYrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PSYrm) + .value("VCVTDQ2PSYrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PSYrr) + .value("VCVTDQ2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rm) + .value("VCVTDQ2PSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rmb) + .value("VCVTDQ2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rmbk) + .value("VCVTDQ2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rmbkz) + .value("VCVTDQ2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rmk) + .value("VCVTDQ2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rmkz) + .value("VCVTDQ2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rr) + .value("VCVTDQ2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rrk) + .value("VCVTDQ2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ128rrkz) + .value("VCVTDQ2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rm) + .value("VCVTDQ2PSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rmb) + .value("VCVTDQ2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rmbk) + .value("VCVTDQ2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rmbkz) + .value("VCVTDQ2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rmk) + .value("VCVTDQ2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rmkz) + .value("VCVTDQ2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rr) + .value("VCVTDQ2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rrk) + .value("VCVTDQ2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZ256rrkz) + .value("VCVTDQ2PSZrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrm) + .value("VCVTDQ2PSZrmb", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrmb) + .value("VCVTDQ2PSZrmbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrmbk) + .value("VCVTDQ2PSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrmbkz) + .value("VCVTDQ2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrmk) + .value("VCVTDQ2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrmkz) + .value("VCVTDQ2PSZrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrr) + .value("VCVTDQ2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrrb) + .value("VCVTDQ2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrrbk) + .value("VCVTDQ2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrrbkz) + .value("VCVTDQ2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrrk) + .value("VCVTDQ2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTDQ2PSZrrkz) + .value("VCVTDQ2PSrm", LIEF::assembly::x86::OPCODE::VCVTDQ2PSrm) + .value("VCVTDQ2PSrr", LIEF::assembly::x86::OPCODE::VCVTDQ2PSrr) + .value("VCVTHF82PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rm) + .value("VCVTHF82PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rmk) + .value("VCVTHF82PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rmkz) + .value("VCVTHF82PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rr) + .value("VCVTHF82PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rrk) + .value("VCVTHF82PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ128rrkz) + .value("VCVTHF82PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rm) + .value("VCVTHF82PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rmk) + .value("VCVTHF82PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rmkz) + .value("VCVTHF82PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rr) + .value("VCVTHF82PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rrk) + .value("VCVTHF82PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZ256rrkz) + .value("VCVTHF82PHZrm", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrm) + .value("VCVTHF82PHZrmk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrmk) + .value("VCVTHF82PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrmkz) + .value("VCVTHF82PHZrr", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrr) + .value("VCVTHF82PHZrrk", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrrk) + .value("VCVTHF82PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTHF82PHZrrkz) + .value("VCVTNE2PS2BF16Z128rm", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rm) + .value("VCVTNE2PS2BF16Z128rmb", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rmb) + .value("VCVTNE2PS2BF16Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rmbk) + .value("VCVTNE2PS2BF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rmbkz) + .value("VCVTNE2PS2BF16Z128rmk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rmk) + .value("VCVTNE2PS2BF16Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rmkz) + .value("VCVTNE2PS2BF16Z128rr", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rr); + opcodes.value("VCVTNE2PS2BF16Z128rrk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rrk) + .value("VCVTNE2PS2BF16Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z128rrkz) + .value("VCVTNE2PS2BF16Z256rm", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rm) + .value("VCVTNE2PS2BF16Z256rmb", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rmb) + .value("VCVTNE2PS2BF16Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rmbk) + .value("VCVTNE2PS2BF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rmbkz) + .value("VCVTNE2PS2BF16Z256rmk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rmk) + .value("VCVTNE2PS2BF16Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rmkz) + .value("VCVTNE2PS2BF16Z256rr", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rr) + .value("VCVTNE2PS2BF16Z256rrk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rrk) + .value("VCVTNE2PS2BF16Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Z256rrkz) + .value("VCVTNE2PS2BF16Zrm", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrm) + .value("VCVTNE2PS2BF16Zrmb", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrmb) + .value("VCVTNE2PS2BF16Zrmbk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrmbk) + .value("VCVTNE2PS2BF16Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrmbkz) + .value("VCVTNE2PS2BF16Zrmk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrmk) + .value("VCVTNE2PS2BF16Zrmkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrmkz) + .value("VCVTNE2PS2BF16Zrr", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrr) + .value("VCVTNE2PS2BF16Zrrk", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrrk) + .value("VCVTNE2PS2BF16Zrrkz", LIEF::assembly::x86::OPCODE::VCVTNE2PS2BF16Zrrkz) + .value("VCVTNEEBF162PSYrm", LIEF::assembly::x86::OPCODE::VCVTNEEBF162PSYrm) + .value("VCVTNEEBF162PSrm", LIEF::assembly::x86::OPCODE::VCVTNEEBF162PSrm) + .value("VCVTNEEPH2PSYrm", LIEF::assembly::x86::OPCODE::VCVTNEEPH2PSYrm) + .value("VCVTNEEPH2PSrm", LIEF::assembly::x86::OPCODE::VCVTNEEPH2PSrm) + .value("VCVTNEOBF162PSYrm", LIEF::assembly::x86::OPCODE::VCVTNEOBF162PSYrm) + .value("VCVTNEOBF162PSrm", LIEF::assembly::x86::OPCODE::VCVTNEOBF162PSrm) + .value("VCVTNEOPH2PSYrm", LIEF::assembly::x86::OPCODE::VCVTNEOPH2PSYrm) + .value("VCVTNEOPH2PSrm", LIEF::assembly::x86::OPCODE::VCVTNEOPH2PSrm) + .value("VCVTNEPS2BF16Yrm", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Yrm) + .value("VCVTNEPS2BF16Yrr", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Yrr) + .value("VCVTNEPS2BF16Z128rm", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rm) + .value("VCVTNEPS2BF16Z128rmb", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rmb) + .value("VCVTNEPS2BF16Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rmbk) + .value("VCVTNEPS2BF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rmbkz) + .value("VCVTNEPS2BF16Z128rmk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rmk) + .value("VCVTNEPS2BF16Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rmkz) + .value("VCVTNEPS2BF16Z128rr", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rr) + .value("VCVTNEPS2BF16Z128rrk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rrk) + .value("VCVTNEPS2BF16Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z128rrkz) + .value("VCVTNEPS2BF16Z256rm", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rm) + .value("VCVTNEPS2BF16Z256rmb", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rmb) + .value("VCVTNEPS2BF16Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rmbk) + .value("VCVTNEPS2BF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rmbkz) + .value("VCVTNEPS2BF16Z256rmk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rmk) + .value("VCVTNEPS2BF16Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rmkz) + .value("VCVTNEPS2BF16Z256rr", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rr) + .value("VCVTNEPS2BF16Z256rrk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rrk) + .value("VCVTNEPS2BF16Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Z256rrkz) + .value("VCVTNEPS2BF16Zrm", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrm) + .value("VCVTNEPS2BF16Zrmb", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrmb) + .value("VCVTNEPS2BF16Zrmbk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrmbk) + .value("VCVTNEPS2BF16Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrmbkz) + .value("VCVTNEPS2BF16Zrmk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrmk) + .value("VCVTNEPS2BF16Zrmkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrmkz) + .value("VCVTNEPS2BF16Zrr", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrr) + .value("VCVTNEPS2BF16Zrrk", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrrk) + .value("VCVTNEPS2BF16Zrrkz", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16Zrrkz) + .value("VCVTNEPS2BF16rm", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16rm) + .value("VCVTNEPS2BF16rr", LIEF::assembly::x86::OPCODE::VCVTNEPS2BF16rr) + .value("VCVTPD2DQYrm", LIEF::assembly::x86::OPCODE::VCVTPD2DQYrm) + .value("VCVTPD2DQYrr", LIEF::assembly::x86::OPCODE::VCVTPD2DQYrr) + .value("VCVTPD2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rm) + .value("VCVTPD2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rmb) + .value("VCVTPD2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rmbk) + .value("VCVTPD2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rmbkz) + .value("VCVTPD2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rmk) + .value("VCVTPD2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rmkz) + .value("VCVTPD2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rr) + .value("VCVTPD2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rrk) + .value("VCVTPD2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ128rrkz) + .value("VCVTPD2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rm) + .value("VCVTPD2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rmb) + .value("VCVTPD2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rmbk) + .value("VCVTPD2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rmbkz) + .value("VCVTPD2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rmk) + .value("VCVTPD2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rmkz) + .value("VCVTPD2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rr) + .value("VCVTPD2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rrk) + .value("VCVTPD2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZ256rrkz) + .value("VCVTPD2DQZrm", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrm) + .value("VCVTPD2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrmb) + .value("VCVTPD2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrmbk) + .value("VCVTPD2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrmbkz) + .value("VCVTPD2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrmk) + .value("VCVTPD2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrmkz) + .value("VCVTPD2DQZrr", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrr) + .value("VCVTPD2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrrb) + .value("VCVTPD2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrrbk) + .value("VCVTPD2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrrbkz) + .value("VCVTPD2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrrk) + .value("VCVTPD2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2DQZrrkz) + .value("VCVTPD2DQrm", LIEF::assembly::x86::OPCODE::VCVTPD2DQrm) + .value("VCVTPD2DQrr", LIEF::assembly::x86::OPCODE::VCVTPD2DQrr) + .value("VCVTPD2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rm) + .value("VCVTPD2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rmb) + .value("VCVTPD2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rmbk) + .value("VCVTPD2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rmbkz) + .value("VCVTPD2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rmk) + .value("VCVTPD2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rmkz) + .value("VCVTPD2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rr) + .value("VCVTPD2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rrk) + .value("VCVTPD2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ128rrkz) + .value("VCVTPD2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rm) + .value("VCVTPD2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rmb) + .value("VCVTPD2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rmbk) + .value("VCVTPD2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rmbkz) + .value("VCVTPD2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rmk) + .value("VCVTPD2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rmkz) + .value("VCVTPD2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rr) + .value("VCVTPD2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rrk) + .value("VCVTPD2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZ256rrkz) + .value("VCVTPD2PHZrm", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrm) + .value("VCVTPD2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrmb) + .value("VCVTPD2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrmbk) + .value("VCVTPD2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrmbkz) + .value("VCVTPD2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrmk) + .value("VCVTPD2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrmkz) + .value("VCVTPD2PHZrr", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrr) + .value("VCVTPD2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrrb) + .value("VCVTPD2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrrbk) + .value("VCVTPD2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrrbkz) + .value("VCVTPD2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrrk) + .value("VCVTPD2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PHZrrkz) + .value("VCVTPD2PSYrm", LIEF::assembly::x86::OPCODE::VCVTPD2PSYrm) + .value("VCVTPD2PSYrr", LIEF::assembly::x86::OPCODE::VCVTPD2PSYrr) + .value("VCVTPD2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rm) + .value("VCVTPD2PSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rmb) + .value("VCVTPD2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rmbk) + .value("VCVTPD2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rmbkz) + .value("VCVTPD2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rmk) + .value("VCVTPD2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rmkz) + .value("VCVTPD2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rr) + .value("VCVTPD2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rrk) + .value("VCVTPD2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ128rrkz) + .value("VCVTPD2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rm) + .value("VCVTPD2PSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rmb) + .value("VCVTPD2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rmbk) + .value("VCVTPD2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rmbkz) + .value("VCVTPD2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rmk) + .value("VCVTPD2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rmkz) + .value("VCVTPD2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rr) + .value("VCVTPD2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rrk) + .value("VCVTPD2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZ256rrkz) + .value("VCVTPD2PSZrm", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrm) + .value("VCVTPD2PSZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrmb) + .value("VCVTPD2PSZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrmbk) + .value("VCVTPD2PSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrmbkz) + .value("VCVTPD2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrmk) + .value("VCVTPD2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrmkz) + .value("VCVTPD2PSZrr", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrr) + .value("VCVTPD2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrrb) + .value("VCVTPD2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrrbk) + .value("VCVTPD2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrrbkz) + .value("VCVTPD2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrrk) + .value("VCVTPD2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2PSZrrkz) + .value("VCVTPD2PSrm", LIEF::assembly::x86::OPCODE::VCVTPD2PSrm) + .value("VCVTPD2PSrr", LIEF::assembly::x86::OPCODE::VCVTPD2PSrr) + .value("VCVTPD2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rm) + .value("VCVTPD2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rmb) + .value("VCVTPD2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rmbk) + .value("VCVTPD2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rmbkz) + .value("VCVTPD2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rmk) + .value("VCVTPD2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rmkz) + .value("VCVTPD2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rr) + .value("VCVTPD2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rrk) + .value("VCVTPD2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ128rrkz) + .value("VCVTPD2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rm) + .value("VCVTPD2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rmb) + .value("VCVTPD2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rmbk) + .value("VCVTPD2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rmbkz) + .value("VCVTPD2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rmk) + .value("VCVTPD2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rmkz) + .value("VCVTPD2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rr) + .value("VCVTPD2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rrk) + .value("VCVTPD2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZ256rrkz) + .value("VCVTPD2QQZrm", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrm) + .value("VCVTPD2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrmb) + .value("VCVTPD2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrmbk) + .value("VCVTPD2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrmbkz) + .value("VCVTPD2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrmk) + .value("VCVTPD2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrmkz) + .value("VCVTPD2QQZrr", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrr) + .value("VCVTPD2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrrb) + .value("VCVTPD2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrrbk) + .value("VCVTPD2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrrbkz) + .value("VCVTPD2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrrk) + .value("VCVTPD2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2QQZrrkz) + .value("VCVTPD2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rm) + .value("VCVTPD2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rmb) + .value("VCVTPD2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rmbk) + .value("VCVTPD2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rmbkz) + .value("VCVTPD2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rmk) + .value("VCVTPD2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rmkz) + .value("VCVTPD2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rr) + .value("VCVTPD2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rrk) + .value("VCVTPD2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ128rrkz) + .value("VCVTPD2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rm) + .value("VCVTPD2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rmb) + .value("VCVTPD2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rmbk) + .value("VCVTPD2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rmbkz) + .value("VCVTPD2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rmk) + .value("VCVTPD2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rmkz) + .value("VCVTPD2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rr) + .value("VCVTPD2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rrk) + .value("VCVTPD2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZ256rrkz) + .value("VCVTPD2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrm) + .value("VCVTPD2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrmb) + .value("VCVTPD2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrmbk) + .value("VCVTPD2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrmbkz) + .value("VCVTPD2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrmk) + .value("VCVTPD2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrmkz) + .value("VCVTPD2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrr) + .value("VCVTPD2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrrb) + .value("VCVTPD2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrrbk) + .value("VCVTPD2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrrbkz) + .value("VCVTPD2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrrk) + .value("VCVTPD2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UDQZrrkz) + .value("VCVTPD2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rm) + .value("VCVTPD2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rmb) + .value("VCVTPD2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rmbk) + .value("VCVTPD2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rmbkz) + .value("VCVTPD2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rmk) + .value("VCVTPD2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rmkz) + .value("VCVTPD2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rr) + .value("VCVTPD2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rrk) + .value("VCVTPD2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ128rrkz) + .value("VCVTPD2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rm) + .value("VCVTPD2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rmb) + .value("VCVTPD2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rmbk) + .value("VCVTPD2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rmbkz) + .value("VCVTPD2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rmk) + .value("VCVTPD2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rmkz) + .value("VCVTPD2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rr) + .value("VCVTPD2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rrk) + .value("VCVTPD2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZ256rrkz) + .value("VCVTPD2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrm) + .value("VCVTPD2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrmb) + .value("VCVTPD2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrmbk) + .value("VCVTPD2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrmbkz) + .value("VCVTPD2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrmk) + .value("VCVTPD2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrmkz) + .value("VCVTPD2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrr) + .value("VCVTPD2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrrb) + .value("VCVTPD2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrrbk) + .value("VCVTPD2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrrbkz) + .value("VCVTPD2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrrk) + .value("VCVTPD2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPD2UQQZrrkz) + .value("VCVTPH2BF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rm) + .value("VCVTPH2BF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rmb) + .value("VCVTPH2BF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rmbk) + .value("VCVTPH2BF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rmbkz) + .value("VCVTPH2BF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rmk) + .value("VCVTPH2BF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rmkz) + .value("VCVTPH2BF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rr) + .value("VCVTPH2BF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rrk) + .value("VCVTPH2BF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ128rrkz) + .value("VCVTPH2BF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rm) + .value("VCVTPH2BF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rmb) + .value("VCVTPH2BF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rmbk) + .value("VCVTPH2BF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rmbkz) + .value("VCVTPH2BF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rmk) + .value("VCVTPH2BF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rmkz) + .value("VCVTPH2BF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rr) + .value("VCVTPH2BF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rrk) + .value("VCVTPH2BF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZ256rrkz) + .value("VCVTPH2BF8SZrm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrm) + .value("VCVTPH2BF8SZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrmb) + .value("VCVTPH2BF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrmbk) + .value("VCVTPH2BF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrmbkz) + .value("VCVTPH2BF8SZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrmk) + .value("VCVTPH2BF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrmkz) + .value("VCVTPH2BF8SZrr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrr) + .value("VCVTPH2BF8SZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrrk) + .value("VCVTPH2BF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8SZrrkz) + .value("VCVTPH2BF8Z128rm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rm) + .value("VCVTPH2BF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rmb) + .value("VCVTPH2BF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rmbk) + .value("VCVTPH2BF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rmbkz) + .value("VCVTPH2BF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rmk) + .value("VCVTPH2BF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rmkz) + .value("VCVTPH2BF8Z128rr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rr) + .value("VCVTPH2BF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rrk) + .value("VCVTPH2BF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z128rrkz) + .value("VCVTPH2BF8Z256rm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rm) + .value("VCVTPH2BF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rmb) + .value("VCVTPH2BF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rmbk) + .value("VCVTPH2BF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rmbkz) + .value("VCVTPH2BF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rmk) + .value("VCVTPH2BF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rmkz) + .value("VCVTPH2BF8Z256rr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rr) + .value("VCVTPH2BF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rrk) + .value("VCVTPH2BF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Z256rrkz) + .value("VCVTPH2BF8Zrm", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrm) + .value("VCVTPH2BF8Zrmb", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrmb) + .value("VCVTPH2BF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrmbk) + .value("VCVTPH2BF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrmbkz) + .value("VCVTPH2BF8Zrmk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrmk) + .value("VCVTPH2BF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrmkz) + .value("VCVTPH2BF8Zrr", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrr) + .value("VCVTPH2BF8Zrrk", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrrk); + opcodes.value("VCVTPH2BF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2BF8Zrrkz) + .value("VCVTPH2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rm) + .value("VCVTPH2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rmb) + .value("VCVTPH2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rmbk) + .value("VCVTPH2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rmbkz) + .value("VCVTPH2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rmk) + .value("VCVTPH2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rmkz) + .value("VCVTPH2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rr) + .value("VCVTPH2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rrk) + .value("VCVTPH2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ128rrkz) + .value("VCVTPH2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rm) + .value("VCVTPH2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rmb) + .value("VCVTPH2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rmbk) + .value("VCVTPH2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rmbkz) + .value("VCVTPH2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rmk) + .value("VCVTPH2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rmkz) + .value("VCVTPH2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rr) + .value("VCVTPH2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rrk) + .value("VCVTPH2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZ256rrkz) + .value("VCVTPH2DQZrm", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrm) + .value("VCVTPH2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrmb) + .value("VCVTPH2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrmbk) + .value("VCVTPH2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrmbkz) + .value("VCVTPH2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrmk) + .value("VCVTPH2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrmkz) + .value("VCVTPH2DQZrr", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrr) + .value("VCVTPH2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrrb) + .value("VCVTPH2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrrbk) + .value("VCVTPH2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrrbkz) + .value("VCVTPH2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrrk) + .value("VCVTPH2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2DQZrrkz) + .value("VCVTPH2HF8SZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rm) + .value("VCVTPH2HF8SZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rmb) + .value("VCVTPH2HF8SZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rmbk) + .value("VCVTPH2HF8SZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rmbkz) + .value("VCVTPH2HF8SZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rmk) + .value("VCVTPH2HF8SZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rmkz) + .value("VCVTPH2HF8SZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rr) + .value("VCVTPH2HF8SZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rrk) + .value("VCVTPH2HF8SZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ128rrkz) + .value("VCVTPH2HF8SZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rm) + .value("VCVTPH2HF8SZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rmb) + .value("VCVTPH2HF8SZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rmbk) + .value("VCVTPH2HF8SZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rmbkz) + .value("VCVTPH2HF8SZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rmk) + .value("VCVTPH2HF8SZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rmkz) + .value("VCVTPH2HF8SZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rr) + .value("VCVTPH2HF8SZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rrk) + .value("VCVTPH2HF8SZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZ256rrkz) + .value("VCVTPH2HF8SZrm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrm) + .value("VCVTPH2HF8SZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrmb) + .value("VCVTPH2HF8SZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrmbk) + .value("VCVTPH2HF8SZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrmbkz) + .value("VCVTPH2HF8SZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrmk) + .value("VCVTPH2HF8SZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrmkz) + .value("VCVTPH2HF8SZrr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrr) + .value("VCVTPH2HF8SZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrrk) + .value("VCVTPH2HF8SZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8SZrrkz) + .value("VCVTPH2HF8Z128rm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rm) + .value("VCVTPH2HF8Z128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rmb) + .value("VCVTPH2HF8Z128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rmbk) + .value("VCVTPH2HF8Z128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rmbkz) + .value("VCVTPH2HF8Z128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rmk) + .value("VCVTPH2HF8Z128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rmkz) + .value("VCVTPH2HF8Z128rr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rr) + .value("VCVTPH2HF8Z128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rrk) + .value("VCVTPH2HF8Z128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z128rrkz) + .value("VCVTPH2HF8Z256rm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rm) + .value("VCVTPH2HF8Z256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rmb) + .value("VCVTPH2HF8Z256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rmbk) + .value("VCVTPH2HF8Z256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rmbkz) + .value("VCVTPH2HF8Z256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rmk) + .value("VCVTPH2HF8Z256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rmkz) + .value("VCVTPH2HF8Z256rr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rr) + .value("VCVTPH2HF8Z256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rrk) + .value("VCVTPH2HF8Z256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Z256rrkz) + .value("VCVTPH2HF8Zrm", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrm) + .value("VCVTPH2HF8Zrmb", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrmb) + .value("VCVTPH2HF8Zrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrmbk) + .value("VCVTPH2HF8Zrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrmbkz) + .value("VCVTPH2HF8Zrmk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrmk) + .value("VCVTPH2HF8Zrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrmkz) + .value("VCVTPH2HF8Zrr", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrr) + .value("VCVTPH2HF8Zrrk", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrrk) + .value("VCVTPH2HF8Zrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2HF8Zrrkz) + .value("VCVTPH2IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rm) + .value("VCVTPH2IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rmb) + .value("VCVTPH2IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rmbk) + .value("VCVTPH2IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rmbkz) + .value("VCVTPH2IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rmk) + .value("VCVTPH2IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rmkz) + .value("VCVTPH2IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rr) + .value("VCVTPH2IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rrk) + .value("VCVTPH2IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ128rrkz) + .value("VCVTPH2IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rm) + .value("VCVTPH2IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rmb) + .value("VCVTPH2IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rmbk) + .value("VCVTPH2IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rmbkz) + .value("VCVTPH2IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rmk) + .value("VCVTPH2IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rmkz) + .value("VCVTPH2IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rr) + .value("VCVTPH2IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rrk) + .value("VCVTPH2IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZ256rrkz) + .value("VCVTPH2IBSZrm", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrm) + .value("VCVTPH2IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrmb) + .value("VCVTPH2IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrmbk) + .value("VCVTPH2IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrmbkz) + .value("VCVTPH2IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrmk) + .value("VCVTPH2IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrmkz) + .value("VCVTPH2IBSZrr", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrr) + .value("VCVTPH2IBSZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrrb) + .value("VCVTPH2IBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrrbk) + .value("VCVTPH2IBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrrbkz) + .value("VCVTPH2IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrrk) + .value("VCVTPH2IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IBSZrrkz) + .value("VCVTPH2IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rm) + .value("VCVTPH2IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rmb) + .value("VCVTPH2IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rmbk) + .value("VCVTPH2IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rmbkz) + .value("VCVTPH2IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rmk) + .value("VCVTPH2IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rmkz) + .value("VCVTPH2IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rr) + .value("VCVTPH2IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rrk) + .value("VCVTPH2IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ128rrkz) + .value("VCVTPH2IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rm) + .value("VCVTPH2IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rmb) + .value("VCVTPH2IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rmbk) + .value("VCVTPH2IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rmbkz) + .value("VCVTPH2IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rmk) + .value("VCVTPH2IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rmkz) + .value("VCVTPH2IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rr) + .value("VCVTPH2IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rrk) + .value("VCVTPH2IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZ256rrkz) + .value("VCVTPH2IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrm) + .value("VCVTPH2IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrmb) + .value("VCVTPH2IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrmbk) + .value("VCVTPH2IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrmbkz) + .value("VCVTPH2IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrmk) + .value("VCVTPH2IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrmkz) + .value("VCVTPH2IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrr) + .value("VCVTPH2IUBSZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrrb) + .value("VCVTPH2IUBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrrbk) + .value("VCVTPH2IUBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrrbkz) + .value("VCVTPH2IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrrk) + .value("VCVTPH2IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2IUBSZrrkz) + .value("VCVTPH2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rm) + .value("VCVTPH2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rmb) + .value("VCVTPH2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rmbk) + .value("VCVTPH2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rmbkz) + .value("VCVTPH2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rmk) + .value("VCVTPH2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rmkz) + .value("VCVTPH2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rr) + .value("VCVTPH2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rrk) + .value("VCVTPH2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ128rrkz) + .value("VCVTPH2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rm) + .value("VCVTPH2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rmb) + .value("VCVTPH2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rmbk) + .value("VCVTPH2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rmbkz) + .value("VCVTPH2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rmk) + .value("VCVTPH2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rmkz) + .value("VCVTPH2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rr) + .value("VCVTPH2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rrk) + .value("VCVTPH2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZ256rrkz) + .value("VCVTPH2PDZrm", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrm) + .value("VCVTPH2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrmb) + .value("VCVTPH2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrmbk) + .value("VCVTPH2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrmbkz) + .value("VCVTPH2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrmk) + .value("VCVTPH2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrmkz) + .value("VCVTPH2PDZrr", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrr) + .value("VCVTPH2PDZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrrb) + .value("VCVTPH2PDZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrrbk) + .value("VCVTPH2PDZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrrbkz) + .value("VCVTPH2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrrk) + .value("VCVTPH2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PDZrrkz) + .value("VCVTPH2PSXZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rm) + .value("VCVTPH2PSXZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rmb) + .value("VCVTPH2PSXZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rmbk) + .value("VCVTPH2PSXZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rmbkz) + .value("VCVTPH2PSXZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rmk) + .value("VCVTPH2PSXZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rmkz) + .value("VCVTPH2PSXZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rr) + .value("VCVTPH2PSXZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rrk) + .value("VCVTPH2PSXZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ128rrkz) + .value("VCVTPH2PSXZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rm) + .value("VCVTPH2PSXZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rmb) + .value("VCVTPH2PSXZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rmbk) + .value("VCVTPH2PSXZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rmbkz) + .value("VCVTPH2PSXZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rmk) + .value("VCVTPH2PSXZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rmkz) + .value("VCVTPH2PSXZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rr) + .value("VCVTPH2PSXZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rrk) + .value("VCVTPH2PSXZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZ256rrkz) + .value("VCVTPH2PSXZrm", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrm) + .value("VCVTPH2PSXZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrmb) + .value("VCVTPH2PSXZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrmbk) + .value("VCVTPH2PSXZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrmbkz) + .value("VCVTPH2PSXZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrmk) + .value("VCVTPH2PSXZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrmkz) + .value("VCVTPH2PSXZrr", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrr) + .value("VCVTPH2PSXZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrrb) + .value("VCVTPH2PSXZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrrbk) + .value("VCVTPH2PSXZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrrbkz) + .value("VCVTPH2PSXZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrrk) + .value("VCVTPH2PSXZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSXZrrkz) + .value("VCVTPH2PSYrm", LIEF::assembly::x86::OPCODE::VCVTPH2PSYrm) + .value("VCVTPH2PSYrr", LIEF::assembly::x86::OPCODE::VCVTPH2PSYrr) + .value("VCVTPH2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rm) + .value("VCVTPH2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rmk) + .value("VCVTPH2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rmkz) + .value("VCVTPH2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rr) + .value("VCVTPH2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rrk) + .value("VCVTPH2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ128rrkz) + .value("VCVTPH2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rm) + .value("VCVTPH2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rmk) + .value("VCVTPH2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rmkz) + .value("VCVTPH2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rr) + .value("VCVTPH2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rrk) + .value("VCVTPH2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZ256rrkz) + .value("VCVTPH2PSZrm", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrm) + .value("VCVTPH2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrmk) + .value("VCVTPH2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrmkz) + .value("VCVTPH2PSZrr", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrr) + .value("VCVTPH2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrrb) + .value("VCVTPH2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrrbk) + .value("VCVTPH2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrrbkz) + .value("VCVTPH2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrrk) + .value("VCVTPH2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2PSZrrkz) + .value("VCVTPH2PSrm", LIEF::assembly::x86::OPCODE::VCVTPH2PSrm) + .value("VCVTPH2PSrr", LIEF::assembly::x86::OPCODE::VCVTPH2PSrr) + .value("VCVTPH2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rm) + .value("VCVTPH2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rmb) + .value("VCVTPH2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rmbk) + .value("VCVTPH2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rmbkz) + .value("VCVTPH2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rmk) + .value("VCVTPH2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rmkz) + .value("VCVTPH2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rr) + .value("VCVTPH2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rrk) + .value("VCVTPH2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ128rrkz) + .value("VCVTPH2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rm) + .value("VCVTPH2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rmb) + .value("VCVTPH2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rmbk) + .value("VCVTPH2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rmbkz) + .value("VCVTPH2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rmk) + .value("VCVTPH2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rmkz) + .value("VCVTPH2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rr) + .value("VCVTPH2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rrk) + .value("VCVTPH2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZ256rrkz) + .value("VCVTPH2QQZrm", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrm) + .value("VCVTPH2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrmb) + .value("VCVTPH2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrmbk) + .value("VCVTPH2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrmbkz) + .value("VCVTPH2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrmk) + .value("VCVTPH2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrmkz) + .value("VCVTPH2QQZrr", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrr) + .value("VCVTPH2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrrb) + .value("VCVTPH2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrrbk) + .value("VCVTPH2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrrbkz) + .value("VCVTPH2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrrk) + .value("VCVTPH2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2QQZrrkz) + .value("VCVTPH2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rm) + .value("VCVTPH2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rmb) + .value("VCVTPH2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rmbk) + .value("VCVTPH2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rmbkz) + .value("VCVTPH2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rmk) + .value("VCVTPH2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rmkz) + .value("VCVTPH2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rr) + .value("VCVTPH2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rrk) + .value("VCVTPH2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ128rrkz) + .value("VCVTPH2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rm) + .value("VCVTPH2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rmb) + .value("VCVTPH2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rmbk) + .value("VCVTPH2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rmbkz) + .value("VCVTPH2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rmk) + .value("VCVTPH2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rmkz) + .value("VCVTPH2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rr) + .value("VCVTPH2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rrk) + .value("VCVTPH2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZ256rrkz) + .value("VCVTPH2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrm) + .value("VCVTPH2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrmb) + .value("VCVTPH2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrmbk) + .value("VCVTPH2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrmbkz) + .value("VCVTPH2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrmk) + .value("VCVTPH2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrmkz) + .value("VCVTPH2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrr) + .value("VCVTPH2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrrb) + .value("VCVTPH2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrrbk) + .value("VCVTPH2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrrbkz) + .value("VCVTPH2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrrk) + .value("VCVTPH2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UDQZrrkz) + .value("VCVTPH2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rm) + .value("VCVTPH2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rmb) + .value("VCVTPH2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rmbk) + .value("VCVTPH2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rmbkz) + .value("VCVTPH2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rmk) + .value("VCVTPH2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rmkz) + .value("VCVTPH2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rr) + .value("VCVTPH2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rrk) + .value("VCVTPH2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ128rrkz) + .value("VCVTPH2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rm); + opcodes.value("VCVTPH2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rmb) + .value("VCVTPH2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rmbk) + .value("VCVTPH2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rmbkz) + .value("VCVTPH2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rmk) + .value("VCVTPH2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rmkz) + .value("VCVTPH2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rr) + .value("VCVTPH2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rrk) + .value("VCVTPH2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZ256rrkz) + .value("VCVTPH2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrm) + .value("VCVTPH2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrmb) + .value("VCVTPH2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrmbk) + .value("VCVTPH2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrmbkz) + .value("VCVTPH2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrmk) + .value("VCVTPH2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrmkz) + .value("VCVTPH2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrr) + .value("VCVTPH2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrrb) + .value("VCVTPH2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrrbk) + .value("VCVTPH2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrrbkz) + .value("VCVTPH2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrrk) + .value("VCVTPH2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UQQZrrkz) + .value("VCVTPH2UWZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rm) + .value("VCVTPH2UWZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rmb) + .value("VCVTPH2UWZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rmbk) + .value("VCVTPH2UWZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rmbkz) + .value("VCVTPH2UWZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rmk) + .value("VCVTPH2UWZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rmkz) + .value("VCVTPH2UWZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rr) + .value("VCVTPH2UWZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rrk) + .value("VCVTPH2UWZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ128rrkz) + .value("VCVTPH2UWZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rm) + .value("VCVTPH2UWZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rmb) + .value("VCVTPH2UWZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rmbk) + .value("VCVTPH2UWZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rmbkz) + .value("VCVTPH2UWZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rmk) + .value("VCVTPH2UWZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rmkz) + .value("VCVTPH2UWZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rr) + .value("VCVTPH2UWZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rrk) + .value("VCVTPH2UWZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZ256rrkz) + .value("VCVTPH2UWZrm", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrm) + .value("VCVTPH2UWZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrmb) + .value("VCVTPH2UWZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrmbk) + .value("VCVTPH2UWZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrmbkz) + .value("VCVTPH2UWZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrmk) + .value("VCVTPH2UWZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrmkz) + .value("VCVTPH2UWZrr", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrr) + .value("VCVTPH2UWZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrrb) + .value("VCVTPH2UWZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrrbk) + .value("VCVTPH2UWZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrrbkz) + .value("VCVTPH2UWZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrrk) + .value("VCVTPH2UWZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2UWZrrkz) + .value("VCVTPH2WZ128rm", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rm) + .value("VCVTPH2WZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rmb) + .value("VCVTPH2WZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rmbk) + .value("VCVTPH2WZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rmbkz) + .value("VCVTPH2WZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rmk) + .value("VCVTPH2WZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rmkz) + .value("VCVTPH2WZ128rr", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rr) + .value("VCVTPH2WZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rrk) + .value("VCVTPH2WZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ128rrkz) + .value("VCVTPH2WZ256rm", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rm) + .value("VCVTPH2WZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rmb) + .value("VCVTPH2WZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rmbk) + .value("VCVTPH2WZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rmbkz) + .value("VCVTPH2WZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rmk) + .value("VCVTPH2WZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rmkz) + .value("VCVTPH2WZ256rr", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rr) + .value("VCVTPH2WZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rrk) + .value("VCVTPH2WZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZ256rrkz) + .value("VCVTPH2WZrm", LIEF::assembly::x86::OPCODE::VCVTPH2WZrm) + .value("VCVTPH2WZrmb", LIEF::assembly::x86::OPCODE::VCVTPH2WZrmb) + .value("VCVTPH2WZrmbk", LIEF::assembly::x86::OPCODE::VCVTPH2WZrmbk) + .value("VCVTPH2WZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZrmbkz) + .value("VCVTPH2WZrmk", LIEF::assembly::x86::OPCODE::VCVTPH2WZrmk) + .value("VCVTPH2WZrmkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZrmkz) + .value("VCVTPH2WZrr", LIEF::assembly::x86::OPCODE::VCVTPH2WZrr) + .value("VCVTPH2WZrrb", LIEF::assembly::x86::OPCODE::VCVTPH2WZrrb) + .value("VCVTPH2WZrrbk", LIEF::assembly::x86::OPCODE::VCVTPH2WZrrbk) + .value("VCVTPH2WZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZrrbkz) + .value("VCVTPH2WZrrk", LIEF::assembly::x86::OPCODE::VCVTPH2WZrrk) + .value("VCVTPH2WZrrkz", LIEF::assembly::x86::OPCODE::VCVTPH2WZrrkz) + .value("VCVTPS2DQYrm", LIEF::assembly::x86::OPCODE::VCVTPS2DQYrm) + .value("VCVTPS2DQYrr", LIEF::assembly::x86::OPCODE::VCVTPS2DQYrr) + .value("VCVTPS2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rm) + .value("VCVTPS2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rmb) + .value("VCVTPS2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rmbk) + .value("VCVTPS2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rmbkz) + .value("VCVTPS2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rmk) + .value("VCVTPS2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rmkz) + .value("VCVTPS2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rr) + .value("VCVTPS2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rrk) + .value("VCVTPS2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ128rrkz) + .value("VCVTPS2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rm) + .value("VCVTPS2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rmb) + .value("VCVTPS2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rmbk) + .value("VCVTPS2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rmbkz) + .value("VCVTPS2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rmk) + .value("VCVTPS2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rmkz) + .value("VCVTPS2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rr) + .value("VCVTPS2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rrk) + .value("VCVTPS2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZ256rrkz) + .value("VCVTPS2DQZrm", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrm) + .value("VCVTPS2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrmb) + .value("VCVTPS2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrmbk) + .value("VCVTPS2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrmbkz) + .value("VCVTPS2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrmk) + .value("VCVTPS2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrmkz) + .value("VCVTPS2DQZrr", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrr) + .value("VCVTPS2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrrb) + .value("VCVTPS2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrrbk) + .value("VCVTPS2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrrbkz) + .value("VCVTPS2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrrk) + .value("VCVTPS2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2DQZrrkz) + .value("VCVTPS2DQrm", LIEF::assembly::x86::OPCODE::VCVTPS2DQrm) + .value("VCVTPS2DQrr", LIEF::assembly::x86::OPCODE::VCVTPS2DQrr) + .value("VCVTPS2IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rm) + .value("VCVTPS2IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rmb) + .value("VCVTPS2IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rmbk) + .value("VCVTPS2IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rmbkz) + .value("VCVTPS2IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rmk) + .value("VCVTPS2IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rmkz) + .value("VCVTPS2IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rr) + .value("VCVTPS2IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rrk) + .value("VCVTPS2IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ128rrkz) + .value("VCVTPS2IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rm) + .value("VCVTPS2IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rmb) + .value("VCVTPS2IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rmbk) + .value("VCVTPS2IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rmbkz) + .value("VCVTPS2IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rmk) + .value("VCVTPS2IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rmkz) + .value("VCVTPS2IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rr) + .value("VCVTPS2IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rrk) + .value("VCVTPS2IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZ256rrkz) + .value("VCVTPS2IBSZrm", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrm) + .value("VCVTPS2IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrmb) + .value("VCVTPS2IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrmbk) + .value("VCVTPS2IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrmbkz) + .value("VCVTPS2IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrmk) + .value("VCVTPS2IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrmkz) + .value("VCVTPS2IBSZrr", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrr) + .value("VCVTPS2IBSZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrrb) + .value("VCVTPS2IBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrrbk) + .value("VCVTPS2IBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrrbkz) + .value("VCVTPS2IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrrk) + .value("VCVTPS2IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IBSZrrkz) + .value("VCVTPS2IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rm) + .value("VCVTPS2IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rmb) + .value("VCVTPS2IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rmbk) + .value("VCVTPS2IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rmbkz) + .value("VCVTPS2IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rmk) + .value("VCVTPS2IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rmkz) + .value("VCVTPS2IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rr) + .value("VCVTPS2IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rrk) + .value("VCVTPS2IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ128rrkz) + .value("VCVTPS2IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rm) + .value("VCVTPS2IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rmb) + .value("VCVTPS2IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rmbk) + .value("VCVTPS2IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rmbkz) + .value("VCVTPS2IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rmk) + .value("VCVTPS2IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rmkz) + .value("VCVTPS2IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rr) + .value("VCVTPS2IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rrk) + .value("VCVTPS2IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZ256rrkz) + .value("VCVTPS2IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrm) + .value("VCVTPS2IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrmb) + .value("VCVTPS2IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrmbk) + .value("VCVTPS2IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrmbkz) + .value("VCVTPS2IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrmk) + .value("VCVTPS2IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrmkz) + .value("VCVTPS2IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrr) + .value("VCVTPS2IUBSZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrrb) + .value("VCVTPS2IUBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrrbk) + .value("VCVTPS2IUBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrrbkz) + .value("VCVTPS2IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrrk) + .value("VCVTPS2IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2IUBSZrrkz) + .value("VCVTPS2PDYrm", LIEF::assembly::x86::OPCODE::VCVTPS2PDYrm) + .value("VCVTPS2PDYrr", LIEF::assembly::x86::OPCODE::VCVTPS2PDYrr) + .value("VCVTPS2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rm) + .value("VCVTPS2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rmb) + .value("VCVTPS2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rmbk) + .value("VCVTPS2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rmbkz) + .value("VCVTPS2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rmk) + .value("VCVTPS2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rmkz) + .value("VCVTPS2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rr) + .value("VCVTPS2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rrk) + .value("VCVTPS2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ128rrkz) + .value("VCVTPS2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rm) + .value("VCVTPS2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rmb) + .value("VCVTPS2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rmbk) + .value("VCVTPS2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rmbkz) + .value("VCVTPS2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rmk) + .value("VCVTPS2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rmkz) + .value("VCVTPS2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rr) + .value("VCVTPS2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rrk) + .value("VCVTPS2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZ256rrkz) + .value("VCVTPS2PDZrm", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrm) + .value("VCVTPS2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrmb) + .value("VCVTPS2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrmbk) + .value("VCVTPS2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrmbkz) + .value("VCVTPS2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrmk) + .value("VCVTPS2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrmkz) + .value("VCVTPS2PDZrr", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrr) + .value("VCVTPS2PDZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrrb) + .value("VCVTPS2PDZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrrbk) + .value("VCVTPS2PDZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrrbkz) + .value("VCVTPS2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrrk) + .value("VCVTPS2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PDZrrkz) + .value("VCVTPS2PDrm", LIEF::assembly::x86::OPCODE::VCVTPS2PDrm) + .value("VCVTPS2PDrr", LIEF::assembly::x86::OPCODE::VCVTPS2PDrr) + .value("VCVTPS2PHXZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rm) + .value("VCVTPS2PHXZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rmb) + .value("VCVTPS2PHXZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rmbk) + .value("VCVTPS2PHXZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rmbkz) + .value("VCVTPS2PHXZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rmk) + .value("VCVTPS2PHXZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rmkz) + .value("VCVTPS2PHXZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rr) + .value("VCVTPS2PHXZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rrk) + .value("VCVTPS2PHXZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ128rrkz) + .value("VCVTPS2PHXZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rm) + .value("VCVTPS2PHXZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rmb) + .value("VCVTPS2PHXZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rmbk) + .value("VCVTPS2PHXZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rmbkz) + .value("VCVTPS2PHXZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rmk) + .value("VCVTPS2PHXZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rmkz) + .value("VCVTPS2PHXZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rr) + .value("VCVTPS2PHXZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rrk) + .value("VCVTPS2PHXZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZ256rrkz) + .value("VCVTPS2PHXZrm", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrm) + .value("VCVTPS2PHXZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrmb) + .value("VCVTPS2PHXZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrmbk) + .value("VCVTPS2PHXZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrmbkz) + .value("VCVTPS2PHXZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrmk) + .value("VCVTPS2PHXZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrmkz) + .value("VCVTPS2PHXZrr", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrr) + .value("VCVTPS2PHXZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrrb) + .value("VCVTPS2PHXZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrrbk) + .value("VCVTPS2PHXZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrrbkz) + .value("VCVTPS2PHXZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrrk) + .value("VCVTPS2PHXZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHXZrrkz) + .value("VCVTPS2PHYmr", LIEF::assembly::x86::OPCODE::VCVTPS2PHYmr) + .value("VCVTPS2PHYrr", LIEF::assembly::x86::OPCODE::VCVTPS2PHYrr) + .value("VCVTPS2PHZ128mr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ128mr) + .value("VCVTPS2PHZ128mrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ128mrk) + .value("VCVTPS2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ128rr) + .value("VCVTPS2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ128rrk) + .value("VCVTPS2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ128rrkz) + .value("VCVTPS2PHZ256mr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ256mr) + .value("VCVTPS2PHZ256mrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ256mrk) + .value("VCVTPS2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ256rr) + .value("VCVTPS2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ256rrk) + .value("VCVTPS2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHZ256rrkz) + .value("VCVTPS2PHZmr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZmr) + .value("VCVTPS2PHZmrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZmrk) + .value("VCVTPS2PHZrr", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrr) + .value("VCVTPS2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrrb) + .value("VCVTPS2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrrbk) + .value("VCVTPS2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrrbkz) + .value("VCVTPS2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrrk) + .value("VCVTPS2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2PHZrrkz) + .value("VCVTPS2PHmr", LIEF::assembly::x86::OPCODE::VCVTPS2PHmr) + .value("VCVTPS2PHrr", LIEF::assembly::x86::OPCODE::VCVTPS2PHrr) + .value("VCVTPS2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rm) + .value("VCVTPS2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rmb) + .value("VCVTPS2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rmbk) + .value("VCVTPS2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rmbkz) + .value("VCVTPS2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rmk) + .value("VCVTPS2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rmkz) + .value("VCVTPS2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rr) + .value("VCVTPS2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rrk) + .value("VCVTPS2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ128rrkz) + .value("VCVTPS2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rm) + .value("VCVTPS2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rmb) + .value("VCVTPS2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rmbk) + .value("VCVTPS2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rmbkz) + .value("VCVTPS2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rmk) + .value("VCVTPS2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rmkz) + .value("VCVTPS2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rr) + .value("VCVTPS2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rrk) + .value("VCVTPS2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZ256rrkz) + .value("VCVTPS2QQZrm", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrm) + .value("VCVTPS2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrmb) + .value("VCVTPS2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrmbk) + .value("VCVTPS2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrmbkz) + .value("VCVTPS2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrmk) + .value("VCVTPS2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrmkz) + .value("VCVTPS2QQZrr", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrr) + .value("VCVTPS2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrrb) + .value("VCVTPS2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrrbk) + .value("VCVTPS2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrrbkz) + .value("VCVTPS2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrrk) + .value("VCVTPS2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2QQZrrkz) + .value("VCVTPS2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rm) + .value("VCVTPS2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rmb) + .value("VCVTPS2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rmbk) + .value("VCVTPS2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rmbkz) + .value("VCVTPS2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rmk) + .value("VCVTPS2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rmkz) + .value("VCVTPS2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rr) + .value("VCVTPS2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rrk) + .value("VCVTPS2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ128rrkz) + .value("VCVTPS2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rm); + opcodes.value("VCVTPS2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rmb) + .value("VCVTPS2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rmbk) + .value("VCVTPS2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rmbkz) + .value("VCVTPS2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rmk) + .value("VCVTPS2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rmkz) + .value("VCVTPS2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rr) + .value("VCVTPS2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rrk) + .value("VCVTPS2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZ256rrkz) + .value("VCVTPS2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrm) + .value("VCVTPS2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrmb) + .value("VCVTPS2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrmbk) + .value("VCVTPS2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrmbkz) + .value("VCVTPS2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrmk) + .value("VCVTPS2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrmkz) + .value("VCVTPS2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrr) + .value("VCVTPS2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrrb) + .value("VCVTPS2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrrbk) + .value("VCVTPS2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrrbkz) + .value("VCVTPS2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrrk) + .value("VCVTPS2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UDQZrrkz) + .value("VCVTPS2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rm) + .value("VCVTPS2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rmb) + .value("VCVTPS2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rmbk) + .value("VCVTPS2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rmbkz) + .value("VCVTPS2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rmk) + .value("VCVTPS2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rmkz) + .value("VCVTPS2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rr) + .value("VCVTPS2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rrk) + .value("VCVTPS2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ128rrkz) + .value("VCVTPS2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rm) + .value("VCVTPS2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rmb) + .value("VCVTPS2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rmbk) + .value("VCVTPS2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rmbkz) + .value("VCVTPS2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rmk) + .value("VCVTPS2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rmkz) + .value("VCVTPS2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rr) + .value("VCVTPS2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rrk) + .value("VCVTPS2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZ256rrkz) + .value("VCVTPS2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrm) + .value("VCVTPS2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrmb) + .value("VCVTPS2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrmbk) + .value("VCVTPS2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrmbkz) + .value("VCVTPS2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrmk) + .value("VCVTPS2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrmkz) + .value("VCVTPS2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrr) + .value("VCVTPS2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrrb) + .value("VCVTPS2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrrbk) + .value("VCVTPS2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrrbkz) + .value("VCVTPS2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrrk) + .value("VCVTPS2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTPS2UQQZrrkz) + .value("VCVTQQ2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rm) + .value("VCVTQQ2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rmb) + .value("VCVTQQ2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rmbk) + .value("VCVTQQ2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rmbkz) + .value("VCVTQQ2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rmk) + .value("VCVTQQ2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rmkz) + .value("VCVTQQ2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rr) + .value("VCVTQQ2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rrk) + .value("VCVTQQ2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ128rrkz) + .value("VCVTQQ2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rm) + .value("VCVTQQ2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rmb) + .value("VCVTQQ2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rmbk) + .value("VCVTQQ2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rmbkz) + .value("VCVTQQ2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rmk) + .value("VCVTQQ2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rmkz) + .value("VCVTQQ2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rr) + .value("VCVTQQ2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rrk) + .value("VCVTQQ2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZ256rrkz) + .value("VCVTQQ2PDZrm", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrm) + .value("VCVTQQ2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrmb) + .value("VCVTQQ2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrmbk) + .value("VCVTQQ2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrmbkz) + .value("VCVTQQ2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrmk) + .value("VCVTQQ2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrmkz) + .value("VCVTQQ2PDZrr", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrr) + .value("VCVTQQ2PDZrrb", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrrb) + .value("VCVTQQ2PDZrrbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrrbk) + .value("VCVTQQ2PDZrrbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrrbkz) + .value("VCVTQQ2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrrk) + .value("VCVTQQ2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PDZrrkz) + .value("VCVTQQ2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rm) + .value("VCVTQQ2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rmb) + .value("VCVTQQ2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rmbk) + .value("VCVTQQ2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rmbkz) + .value("VCVTQQ2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rmk) + .value("VCVTQQ2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rmkz) + .value("VCVTQQ2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rr) + .value("VCVTQQ2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rrk) + .value("VCVTQQ2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ128rrkz) + .value("VCVTQQ2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rm) + .value("VCVTQQ2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rmb) + .value("VCVTQQ2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rmbk) + .value("VCVTQQ2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rmbkz) + .value("VCVTQQ2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rmk) + .value("VCVTQQ2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rmkz) + .value("VCVTQQ2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rr) + .value("VCVTQQ2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rrk) + .value("VCVTQQ2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZ256rrkz) + .value("VCVTQQ2PHZrm", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrm) + .value("VCVTQQ2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrmb) + .value("VCVTQQ2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrmbk) + .value("VCVTQQ2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrmbkz) + .value("VCVTQQ2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrmk) + .value("VCVTQQ2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrmkz) + .value("VCVTQQ2PHZrr", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrr) + .value("VCVTQQ2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrrb) + .value("VCVTQQ2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrrbk) + .value("VCVTQQ2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrrbkz) + .value("VCVTQQ2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrrk) + .value("VCVTQQ2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PHZrrkz) + .value("VCVTQQ2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rm) + .value("VCVTQQ2PSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rmb) + .value("VCVTQQ2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rmbk) + .value("VCVTQQ2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rmbkz) + .value("VCVTQQ2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rmk) + .value("VCVTQQ2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rmkz) + .value("VCVTQQ2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rr) + .value("VCVTQQ2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rrk) + .value("VCVTQQ2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ128rrkz) + .value("VCVTQQ2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rm) + .value("VCVTQQ2PSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rmb) + .value("VCVTQQ2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rmbk) + .value("VCVTQQ2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rmbkz) + .value("VCVTQQ2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rmk) + .value("VCVTQQ2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rmkz) + .value("VCVTQQ2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rr) + .value("VCVTQQ2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rrk) + .value("VCVTQQ2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZ256rrkz) + .value("VCVTQQ2PSZrm", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrm) + .value("VCVTQQ2PSZrmb", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrmb) + .value("VCVTQQ2PSZrmbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrmbk) + .value("VCVTQQ2PSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrmbkz) + .value("VCVTQQ2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrmk) + .value("VCVTQQ2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrmkz) + .value("VCVTQQ2PSZrr", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrr) + .value("VCVTQQ2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrrb) + .value("VCVTQQ2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrrbk) + .value("VCVTQQ2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrrbkz) + .value("VCVTQQ2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrrk) + .value("VCVTQQ2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTQQ2PSZrrkz) + .value("VCVTSD2SHZrm", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrm) + .value("VCVTSD2SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrm_Int) + .value("VCVTSD2SHZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrmk_Int) + .value("VCVTSD2SHZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrmkz_Int) + .value("VCVTSD2SHZrr", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrr) + .value("VCVTSD2SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrr_Int) + .value("VCVTSD2SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrrb_Int) + .value("VCVTSD2SHZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrrbk_Int) + .value("VCVTSD2SHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrrbkz_Int) + .value("VCVTSD2SHZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrrk_Int) + .value("VCVTSD2SHZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SHZrrkz_Int) + .value("VCVTSD2SI64Zrm", LIEF::assembly::x86::OPCODE::VCVTSD2SI64Zrm) + .value("VCVTSD2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SI64Zrm_Int) + .value("VCVTSD2SI64Zrr", LIEF::assembly::x86::OPCODE::VCVTSD2SI64Zrr) + .value("VCVTSD2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SI64Zrr_Int) + .value("VCVTSD2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SI64Zrrb_Int) + .value("VCVTSD2SI64rm", LIEF::assembly::x86::OPCODE::VCVTSD2SI64rm) + .value("VCVTSD2SI64rm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SI64rm_Int) + .value("VCVTSD2SI64rr", LIEF::assembly::x86::OPCODE::VCVTSD2SI64rr) + .value("VCVTSD2SI64rr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SI64rr_Int) + .value("VCVTSD2SIZrm", LIEF::assembly::x86::OPCODE::VCVTSD2SIZrm) + .value("VCVTSD2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SIZrm_Int) + .value("VCVTSD2SIZrr", LIEF::assembly::x86::OPCODE::VCVTSD2SIZrr) + .value("VCVTSD2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SIZrr_Int) + .value("VCVTSD2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SIZrrb_Int) + .value("VCVTSD2SIrm", LIEF::assembly::x86::OPCODE::VCVTSD2SIrm) + .value("VCVTSD2SIrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SIrm_Int) + .value("VCVTSD2SIrr", LIEF::assembly::x86::OPCODE::VCVTSD2SIrr) + .value("VCVTSD2SIrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SIrr_Int) + .value("VCVTSD2SSZrm", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrm) + .value("VCVTSD2SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrm_Int) + .value("VCVTSD2SSZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrmk_Int) + .value("VCVTSD2SSZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrmkz_Int) + .value("VCVTSD2SSZrr", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrr) + .value("VCVTSD2SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrr_Int) + .value("VCVTSD2SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrrb_Int) + .value("VCVTSD2SSZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrrbk_Int) + .value("VCVTSD2SSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrrbkz_Int) + .value("VCVTSD2SSZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrrk_Int) + .value("VCVTSD2SSZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSZrrkz_Int) + .value("VCVTSD2SSrm", LIEF::assembly::x86::OPCODE::VCVTSD2SSrm) + .value("VCVTSD2SSrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSrm_Int) + .value("VCVTSD2SSrr", LIEF::assembly::x86::OPCODE::VCVTSD2SSrr) + .value("VCVTSD2SSrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2SSrr_Int) + .value("VCVTSD2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USI64Zrm_Int) + .value("VCVTSD2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USI64Zrr_Int) + .value("VCVTSD2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USI64Zrrb_Int) + .value("VCVTSD2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USIZrm_Int) + .value("VCVTSD2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USIZrr_Int) + .value("VCVTSD2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSD2USIZrrb_Int) + .value("VCVTSH2SDZrm", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrm) + .value("VCVTSH2SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrm_Int) + .value("VCVTSH2SDZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrmk_Int) + .value("VCVTSH2SDZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrmkz_Int) + .value("VCVTSH2SDZrr", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrr) + .value("VCVTSH2SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrr_Int) + .value("VCVTSH2SDZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrrb_Int) + .value("VCVTSH2SDZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrrbk_Int) + .value("VCVTSH2SDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrrbkz_Int) + .value("VCVTSH2SDZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrrk_Int) + .value("VCVTSH2SDZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SDZrrkz_Int) + .value("VCVTSH2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SI64Zrm_Int) + .value("VCVTSH2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SI64Zrr_Int) + .value("VCVTSH2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SI64Zrrb_Int) + .value("VCVTSH2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SIZrm_Int) + .value("VCVTSH2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SIZrr_Int) + .value("VCVTSH2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SIZrrb_Int) + .value("VCVTSH2SSZrm", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrm) + .value("VCVTSH2SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrm_Int) + .value("VCVTSH2SSZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrmk_Int) + .value("VCVTSH2SSZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrmkz_Int) + .value("VCVTSH2SSZrr", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrr) + .value("VCVTSH2SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrr_Int) + .value("VCVTSH2SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrrb_Int) + .value("VCVTSH2SSZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrrbk_Int) + .value("VCVTSH2SSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrrbkz_Int) + .value("VCVTSH2SSZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrrk_Int) + .value("VCVTSH2SSZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSH2SSZrrkz_Int) + .value("VCVTSH2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USI64Zrm_Int) + .value("VCVTSH2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USI64Zrr_Int) + .value("VCVTSH2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USI64Zrrb_Int) + .value("VCVTSH2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USIZrm_Int) + .value("VCVTSH2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USIZrr_Int) + .value("VCVTSH2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSH2USIZrrb_Int) + .value("VCVTSI2SDZrm", LIEF::assembly::x86::OPCODE::VCVTSI2SDZrm) + .value("VCVTSI2SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SDZrm_Int) + .value("VCVTSI2SDZrr", LIEF::assembly::x86::OPCODE::VCVTSI2SDZrr) + .value("VCVTSI2SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SDZrr_Int) + .value("VCVTSI2SDrm", LIEF::assembly::x86::OPCODE::VCVTSI2SDrm) + .value("VCVTSI2SDrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SDrm_Int) + .value("VCVTSI2SDrr", LIEF::assembly::x86::OPCODE::VCVTSI2SDrr) + .value("VCVTSI2SDrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SDrr_Int) + .value("VCVTSI2SHZrm", LIEF::assembly::x86::OPCODE::VCVTSI2SHZrm) + .value("VCVTSI2SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SHZrm_Int) + .value("VCVTSI2SHZrr", LIEF::assembly::x86::OPCODE::VCVTSI2SHZrr) + .value("VCVTSI2SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SHZrr_Int) + .value("VCVTSI2SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SHZrrb_Int) + .value("VCVTSI2SSZrm", LIEF::assembly::x86::OPCODE::VCVTSI2SSZrm) + .value("VCVTSI2SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SSZrm_Int) + .value("VCVTSI2SSZrr", LIEF::assembly::x86::OPCODE::VCVTSI2SSZrr) + .value("VCVTSI2SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SSZrr_Int) + .value("VCVTSI2SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SSZrrb_Int) + .value("VCVTSI2SSrm", LIEF::assembly::x86::OPCODE::VCVTSI2SSrm) + .value("VCVTSI2SSrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SSrm_Int) + .value("VCVTSI2SSrr", LIEF::assembly::x86::OPCODE::VCVTSI2SSrr) + .value("VCVTSI2SSrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI2SSrr_Int) + .value("VCVTSI642SDZrm", LIEF::assembly::x86::OPCODE::VCVTSI642SDZrm) + .value("VCVTSI642SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SDZrm_Int) + .value("VCVTSI642SDZrr", LIEF::assembly::x86::OPCODE::VCVTSI642SDZrr) + .value("VCVTSI642SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SDZrr_Int) + .value("VCVTSI642SDZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SDZrrb_Int) + .value("VCVTSI642SDrm", LIEF::assembly::x86::OPCODE::VCVTSI642SDrm) + .value("VCVTSI642SDrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SDrm_Int) + .value("VCVTSI642SDrr", LIEF::assembly::x86::OPCODE::VCVTSI642SDrr) + .value("VCVTSI642SDrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SDrr_Int) + .value("VCVTSI642SHZrm", LIEF::assembly::x86::OPCODE::VCVTSI642SHZrm) + .value("VCVTSI642SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SHZrm_Int) + .value("VCVTSI642SHZrr", LIEF::assembly::x86::OPCODE::VCVTSI642SHZrr) + .value("VCVTSI642SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SHZrr_Int) + .value("VCVTSI642SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SHZrrb_Int) + .value("VCVTSI642SSZrm", LIEF::assembly::x86::OPCODE::VCVTSI642SSZrm) + .value("VCVTSI642SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SSZrm_Int) + .value("VCVTSI642SSZrr", LIEF::assembly::x86::OPCODE::VCVTSI642SSZrr) + .value("VCVTSI642SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SSZrr_Int) + .value("VCVTSI642SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SSZrrb_Int) + .value("VCVTSI642SSrm", LIEF::assembly::x86::OPCODE::VCVTSI642SSrm) + .value("VCVTSI642SSrm_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SSrm_Int) + .value("VCVTSI642SSrr", LIEF::assembly::x86::OPCODE::VCVTSI642SSrr) + .value("VCVTSI642SSrr_Int", LIEF::assembly::x86::OPCODE::VCVTSI642SSrr_Int) + .value("VCVTSS2SDZrm", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrm) + .value("VCVTSS2SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrm_Int) + .value("VCVTSS2SDZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrmk_Int) + .value("VCVTSS2SDZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrmkz_Int) + .value("VCVTSS2SDZrr", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrr) + .value("VCVTSS2SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrr_Int) + .value("VCVTSS2SDZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrrb_Int) + .value("VCVTSS2SDZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrrbk_Int) + .value("VCVTSS2SDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrrbkz_Int) + .value("VCVTSS2SDZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrrk_Int) + .value("VCVTSS2SDZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDZrrkz_Int) + .value("VCVTSS2SDrm", LIEF::assembly::x86::OPCODE::VCVTSS2SDrm) + .value("VCVTSS2SDrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDrm_Int) + .value("VCVTSS2SDrr", LIEF::assembly::x86::OPCODE::VCVTSS2SDrr) + .value("VCVTSS2SDrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SDrr_Int) + .value("VCVTSS2SHZrm", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrm) + .value("VCVTSS2SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrm_Int) + .value("VCVTSS2SHZrmk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrmk_Int) + .value("VCVTSS2SHZrmkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrmkz_Int) + .value("VCVTSS2SHZrr", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrr) + .value("VCVTSS2SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrr_Int) + .value("VCVTSS2SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrrb_Int) + .value("VCVTSS2SHZrrbk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrrbk_Int) + .value("VCVTSS2SHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrrbkz_Int) + .value("VCVTSS2SHZrrk_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrrk_Int) + .value("VCVTSS2SHZrrkz_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SHZrrkz_Int) + .value("VCVTSS2SI64Zrm", LIEF::assembly::x86::OPCODE::VCVTSS2SI64Zrm) + .value("VCVTSS2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SI64Zrm_Int) + .value("VCVTSS2SI64Zrr", LIEF::assembly::x86::OPCODE::VCVTSS2SI64Zrr) + .value("VCVTSS2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SI64Zrr_Int) + .value("VCVTSS2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SI64Zrrb_Int); + opcodes.value("VCVTSS2SI64rm", LIEF::assembly::x86::OPCODE::VCVTSS2SI64rm) + .value("VCVTSS2SI64rm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SI64rm_Int) + .value("VCVTSS2SI64rr", LIEF::assembly::x86::OPCODE::VCVTSS2SI64rr) + .value("VCVTSS2SI64rr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SI64rr_Int) + .value("VCVTSS2SIZrm", LIEF::assembly::x86::OPCODE::VCVTSS2SIZrm) + .value("VCVTSS2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SIZrm_Int) + .value("VCVTSS2SIZrr", LIEF::assembly::x86::OPCODE::VCVTSS2SIZrr) + .value("VCVTSS2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SIZrr_Int) + .value("VCVTSS2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SIZrrb_Int) + .value("VCVTSS2SIrm", LIEF::assembly::x86::OPCODE::VCVTSS2SIrm) + .value("VCVTSS2SIrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SIrm_Int) + .value("VCVTSS2SIrr", LIEF::assembly::x86::OPCODE::VCVTSS2SIrr) + .value("VCVTSS2SIrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2SIrr_Int) + .value("VCVTSS2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USI64Zrm_Int) + .value("VCVTSS2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USI64Zrr_Int) + .value("VCVTSS2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USI64Zrrb_Int) + .value("VCVTSS2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USIZrm_Int) + .value("VCVTSS2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USIZrr_Int) + .value("VCVTSS2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTSS2USIZrrb_Int) + .value("VCVTTBF162IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rm) + .value("VCVTTBF162IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rmb) + .value("VCVTTBF162IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rmbk) + .value("VCVTTBF162IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rmbkz) + .value("VCVTTBF162IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rmk) + .value("VCVTTBF162IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rmkz) + .value("VCVTTBF162IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rr) + .value("VCVTTBF162IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rrk) + .value("VCVTTBF162IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ128rrkz) + .value("VCVTTBF162IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rm) + .value("VCVTTBF162IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rmb) + .value("VCVTTBF162IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rmbk) + .value("VCVTTBF162IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rmbkz) + .value("VCVTTBF162IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rmk) + .value("VCVTTBF162IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rmkz) + .value("VCVTTBF162IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rr) + .value("VCVTTBF162IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rrk) + .value("VCVTTBF162IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZ256rrkz) + .value("VCVTTBF162IBSZrm", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrm) + .value("VCVTTBF162IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrmb) + .value("VCVTTBF162IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrmbk) + .value("VCVTTBF162IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrmbkz) + .value("VCVTTBF162IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrmk) + .value("VCVTTBF162IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrmkz) + .value("VCVTTBF162IBSZrr", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrr) + .value("VCVTTBF162IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrrk) + .value("VCVTTBF162IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IBSZrrkz) + .value("VCVTTBF162IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rm) + .value("VCVTTBF162IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rmb) + .value("VCVTTBF162IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rmbk) + .value("VCVTTBF162IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rmbkz) + .value("VCVTTBF162IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rmk) + .value("VCVTTBF162IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rmkz) + .value("VCVTTBF162IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rr) + .value("VCVTTBF162IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rrk) + .value("VCVTTBF162IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ128rrkz) + .value("VCVTTBF162IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rm) + .value("VCVTTBF162IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rmb) + .value("VCVTTBF162IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rmbk) + .value("VCVTTBF162IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rmbkz) + .value("VCVTTBF162IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rmk) + .value("VCVTTBF162IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rmkz) + .value("VCVTTBF162IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rr) + .value("VCVTTBF162IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rrk) + .value("VCVTTBF162IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZ256rrkz) + .value("VCVTTBF162IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrm) + .value("VCVTTBF162IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrmb) + .value("VCVTTBF162IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrmbk) + .value("VCVTTBF162IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrmbkz) + .value("VCVTTBF162IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrmk) + .value("VCVTTBF162IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrmkz) + .value("VCVTTBF162IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrr) + .value("VCVTTBF162IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrrk) + .value("VCVTTBF162IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTBF162IUBSZrrkz) + .value("VCVTTPD2DQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rm) + .value("VCVTTPD2DQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rmb) + .value("VCVTTPD2DQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rmbk) + .value("VCVTTPD2DQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rmbkz) + .value("VCVTTPD2DQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rmk) + .value("VCVTTPD2DQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rmkz) + .value("VCVTTPD2DQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rr) + .value("VCVTTPD2DQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rrk) + .value("VCVTTPD2DQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ128rrkz) + .value("VCVTTPD2DQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rm) + .value("VCVTTPD2DQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rmb) + .value("VCVTTPD2DQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rmbk) + .value("VCVTTPD2DQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rmbkz) + .value("VCVTTPD2DQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rmk) + .value("VCVTTPD2DQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rmkz) + .value("VCVTTPD2DQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rr) + .value("VCVTTPD2DQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rrb) + .value("VCVTTPD2DQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rrbk) + .value("VCVTTPD2DQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rrbkz) + .value("VCVTTPD2DQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rrk) + .value("VCVTTPD2DQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZ256rrkz) + .value("VCVTTPD2DQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrm) + .value("VCVTTPD2DQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrmb) + .value("VCVTTPD2DQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrmbk) + .value("VCVTTPD2DQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrmbkz) + .value("VCVTTPD2DQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrmk) + .value("VCVTTPD2DQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrmkz) + .value("VCVTTPD2DQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrr) + .value("VCVTTPD2DQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrrb) + .value("VCVTTPD2DQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrrbk) + .value("VCVTTPD2DQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrrbkz) + .value("VCVTTPD2DQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrrk) + .value("VCVTTPD2DQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQSZrrkz) + .value("VCVTTPD2DQYrm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQYrm) + .value("VCVTTPD2DQYrr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQYrr) + .value("VCVTTPD2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rm) + .value("VCVTTPD2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rmb) + .value("VCVTTPD2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rmbk) + .value("VCVTTPD2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rmbkz) + .value("VCVTTPD2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rmk) + .value("VCVTTPD2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rmkz) + .value("VCVTTPD2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rr) + .value("VCVTTPD2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rrk) + .value("VCVTTPD2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ128rrkz) + .value("VCVTTPD2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rm) + .value("VCVTTPD2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rmb) + .value("VCVTTPD2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rmbk) + .value("VCVTTPD2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rmbkz) + .value("VCVTTPD2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rmk) + .value("VCVTTPD2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rmkz) + .value("VCVTTPD2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rr) + .value("VCVTTPD2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rrk) + .value("VCVTTPD2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZ256rrkz) + .value("VCVTTPD2DQZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrm) + .value("VCVTTPD2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrmb) + .value("VCVTTPD2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrmbk) + .value("VCVTTPD2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrmbkz) + .value("VCVTTPD2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrmk) + .value("VCVTTPD2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrmkz) + .value("VCVTTPD2DQZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrr) + .value("VCVTTPD2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrrb) + .value("VCVTTPD2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrrbk) + .value("VCVTTPD2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrrbkz) + .value("VCVTTPD2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrrk) + .value("VCVTTPD2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2DQZrrkz) + .value("VCVTTPD2DQrm", LIEF::assembly::x86::OPCODE::VCVTTPD2DQrm) + .value("VCVTTPD2DQrr", LIEF::assembly::x86::OPCODE::VCVTTPD2DQrr) + .value("VCVTTPD2QQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rm) + .value("VCVTTPD2QQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rmb) + .value("VCVTTPD2QQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rmbk) + .value("VCVTTPD2QQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rmbkz) + .value("VCVTTPD2QQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rmk) + .value("VCVTTPD2QQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rmkz) + .value("VCVTTPD2QQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rr) + .value("VCVTTPD2QQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rrk) + .value("VCVTTPD2QQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ128rrkz) + .value("VCVTTPD2QQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rm) + .value("VCVTTPD2QQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rmb) + .value("VCVTTPD2QQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rmbk) + .value("VCVTTPD2QQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rmbkz) + .value("VCVTTPD2QQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rmk) + .value("VCVTTPD2QQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rmkz) + .value("VCVTTPD2QQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rr) + .value("VCVTTPD2QQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rrb) + .value("VCVTTPD2QQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rrbk) + .value("VCVTTPD2QQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rrbkz) + .value("VCVTTPD2QQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rrk) + .value("VCVTTPD2QQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZ256rrkz) + .value("VCVTTPD2QQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrm) + .value("VCVTTPD2QQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrmb) + .value("VCVTTPD2QQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrmbk) + .value("VCVTTPD2QQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrmbkz) + .value("VCVTTPD2QQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrmk) + .value("VCVTTPD2QQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrmkz) + .value("VCVTTPD2QQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrr) + .value("VCVTTPD2QQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrrb) + .value("VCVTTPD2QQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrrbk) + .value("VCVTTPD2QQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrrbkz) + .value("VCVTTPD2QQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrrk) + .value("VCVTTPD2QQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQSZrrkz) + .value("VCVTTPD2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rm) + .value("VCVTTPD2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rmb) + .value("VCVTTPD2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rmbk) + .value("VCVTTPD2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rmbkz) + .value("VCVTTPD2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rmk) + .value("VCVTTPD2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rmkz) + .value("VCVTTPD2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rr) + .value("VCVTTPD2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rrk) + .value("VCVTTPD2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ128rrkz) + .value("VCVTTPD2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rm) + .value("VCVTTPD2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rmb) + .value("VCVTTPD2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rmbk) + .value("VCVTTPD2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rmbkz) + .value("VCVTTPD2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rmk) + .value("VCVTTPD2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rmkz) + .value("VCVTTPD2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rr) + .value("VCVTTPD2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rrk) + .value("VCVTTPD2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZ256rrkz) + .value("VCVTTPD2QQZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrm) + .value("VCVTTPD2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrmb) + .value("VCVTTPD2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrmbk) + .value("VCVTTPD2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrmbkz) + .value("VCVTTPD2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrmk) + .value("VCVTTPD2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrmkz) + .value("VCVTTPD2QQZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrr) + .value("VCVTTPD2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrrb) + .value("VCVTTPD2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrrbk) + .value("VCVTTPD2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrrbkz) + .value("VCVTTPD2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrrk) + .value("VCVTTPD2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2QQZrrkz) + .value("VCVTTPD2UDQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rm) + .value("VCVTTPD2UDQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rmb) + .value("VCVTTPD2UDQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rmbk) + .value("VCVTTPD2UDQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rmbkz) + .value("VCVTTPD2UDQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rmk) + .value("VCVTTPD2UDQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rmkz) + .value("VCVTTPD2UDQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rr) + .value("VCVTTPD2UDQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rrk) + .value("VCVTTPD2UDQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ128rrkz) + .value("VCVTTPD2UDQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rm) + .value("VCVTTPD2UDQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rmb) + .value("VCVTTPD2UDQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rmbk) + .value("VCVTTPD2UDQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rmbkz) + .value("VCVTTPD2UDQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rmk) + .value("VCVTTPD2UDQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rmkz) + .value("VCVTTPD2UDQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rr) + .value("VCVTTPD2UDQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rrb) + .value("VCVTTPD2UDQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rrbk) + .value("VCVTTPD2UDQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rrbkz) + .value("VCVTTPD2UDQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rrk) + .value("VCVTTPD2UDQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZ256rrkz) + .value("VCVTTPD2UDQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrm) + .value("VCVTTPD2UDQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrmb) + .value("VCVTTPD2UDQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrmbk) + .value("VCVTTPD2UDQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrmbkz) + .value("VCVTTPD2UDQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrmk) + .value("VCVTTPD2UDQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrmkz) + .value("VCVTTPD2UDQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrr) + .value("VCVTTPD2UDQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrrb) + .value("VCVTTPD2UDQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrrbk) + .value("VCVTTPD2UDQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrrbkz) + .value("VCVTTPD2UDQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrrk) + .value("VCVTTPD2UDQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQSZrrkz) + .value("VCVTTPD2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rm) + .value("VCVTTPD2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rmb) + .value("VCVTTPD2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rmbk) + .value("VCVTTPD2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rmbkz) + .value("VCVTTPD2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rmk) + .value("VCVTTPD2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rmkz) + .value("VCVTTPD2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rr) + .value("VCVTTPD2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rrk) + .value("VCVTTPD2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ128rrkz) + .value("VCVTTPD2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rm) + .value("VCVTTPD2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rmb) + .value("VCVTTPD2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rmbk) + .value("VCVTTPD2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rmbkz) + .value("VCVTTPD2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rmk) + .value("VCVTTPD2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rmkz) + .value("VCVTTPD2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rr) + .value("VCVTTPD2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rrk) + .value("VCVTTPD2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZ256rrkz) + .value("VCVTTPD2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrm) + .value("VCVTTPD2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrmb) + .value("VCVTTPD2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrmbk) + .value("VCVTTPD2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrmbkz) + .value("VCVTTPD2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrmk) + .value("VCVTTPD2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrmkz) + .value("VCVTTPD2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrr) + .value("VCVTTPD2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrrb) + .value("VCVTTPD2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrrbk) + .value("VCVTTPD2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrrbkz) + .value("VCVTTPD2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrrk) + .value("VCVTTPD2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UDQZrrkz) + .value("VCVTTPD2UQQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rm) + .value("VCVTTPD2UQQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rmb) + .value("VCVTTPD2UQQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rmbk) + .value("VCVTTPD2UQQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rmbkz) + .value("VCVTTPD2UQQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rmk) + .value("VCVTTPD2UQQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rmkz) + .value("VCVTTPD2UQQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rr) + .value("VCVTTPD2UQQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rrk) + .value("VCVTTPD2UQQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ128rrkz) + .value("VCVTTPD2UQQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rm) + .value("VCVTTPD2UQQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rmb) + .value("VCVTTPD2UQQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rmbk) + .value("VCVTTPD2UQQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rmbkz) + .value("VCVTTPD2UQQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rmk) + .value("VCVTTPD2UQQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rmkz) + .value("VCVTTPD2UQQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rr) + .value("VCVTTPD2UQQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rrb) + .value("VCVTTPD2UQQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rrbk) + .value("VCVTTPD2UQQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rrbkz) + .value("VCVTTPD2UQQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rrk) + .value("VCVTTPD2UQQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZ256rrkz) + .value("VCVTTPD2UQQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrm) + .value("VCVTTPD2UQQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrmb) + .value("VCVTTPD2UQQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrmbk) + .value("VCVTTPD2UQQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrmbkz) + .value("VCVTTPD2UQQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrmk) + .value("VCVTTPD2UQQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrmkz) + .value("VCVTTPD2UQQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrr) + .value("VCVTTPD2UQQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrrb) + .value("VCVTTPD2UQQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrrbk) + .value("VCVTTPD2UQQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrrbkz) + .value("VCVTTPD2UQQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrrk) + .value("VCVTTPD2UQQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQSZrrkz) + .value("VCVTTPD2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rm); + opcodes.value("VCVTTPD2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rmb) + .value("VCVTTPD2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rmbk) + .value("VCVTTPD2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rmbkz) + .value("VCVTTPD2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rmk) + .value("VCVTTPD2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rmkz) + .value("VCVTTPD2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rr) + .value("VCVTTPD2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rrk) + .value("VCVTTPD2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ128rrkz) + .value("VCVTTPD2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rm) + .value("VCVTTPD2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rmb) + .value("VCVTTPD2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rmbk) + .value("VCVTTPD2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rmbkz) + .value("VCVTTPD2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rmk) + .value("VCVTTPD2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rmkz) + .value("VCVTTPD2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rr) + .value("VCVTTPD2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rrk) + .value("VCVTTPD2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZ256rrkz) + .value("VCVTTPD2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrm) + .value("VCVTTPD2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrmb) + .value("VCVTTPD2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrmbk) + .value("VCVTTPD2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrmbkz) + .value("VCVTTPD2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrmk) + .value("VCVTTPD2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrmkz) + .value("VCVTTPD2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrr) + .value("VCVTTPD2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrrb) + .value("VCVTTPD2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrrbk) + .value("VCVTTPD2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrrbkz) + .value("VCVTTPD2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrrk) + .value("VCVTTPD2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPD2UQQZrrkz) + .value("VCVTTPH2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rm) + .value("VCVTTPH2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rmb) + .value("VCVTTPH2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rmbk) + .value("VCVTTPH2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rmbkz) + .value("VCVTTPH2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rmk) + .value("VCVTTPH2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rmkz) + .value("VCVTTPH2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rr) + .value("VCVTTPH2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rrk) + .value("VCVTTPH2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ128rrkz) + .value("VCVTTPH2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rm) + .value("VCVTTPH2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rmb) + .value("VCVTTPH2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rmbk) + .value("VCVTTPH2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rmbkz) + .value("VCVTTPH2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rmk) + .value("VCVTTPH2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rmkz) + .value("VCVTTPH2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rr) + .value("VCVTTPH2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rrk) + .value("VCVTTPH2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZ256rrkz) + .value("VCVTTPH2DQZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrm) + .value("VCVTTPH2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrmb) + .value("VCVTTPH2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrmbk) + .value("VCVTTPH2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrmbkz) + .value("VCVTTPH2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrmk) + .value("VCVTTPH2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrmkz) + .value("VCVTTPH2DQZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrr) + .value("VCVTTPH2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrrb) + .value("VCVTTPH2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrrbk) + .value("VCVTTPH2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrrbkz) + .value("VCVTTPH2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrrk) + .value("VCVTTPH2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2DQZrrkz) + .value("VCVTTPH2IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rm) + .value("VCVTTPH2IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rmb) + .value("VCVTTPH2IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rmbk) + .value("VCVTTPH2IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rmbkz) + .value("VCVTTPH2IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rmk) + .value("VCVTTPH2IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rmkz) + .value("VCVTTPH2IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rr) + .value("VCVTTPH2IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rrk) + .value("VCVTTPH2IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ128rrkz) + .value("VCVTTPH2IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rm) + .value("VCVTTPH2IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rmb) + .value("VCVTTPH2IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rmbk) + .value("VCVTTPH2IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rmbkz) + .value("VCVTTPH2IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rmk) + .value("VCVTTPH2IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rmkz) + .value("VCVTTPH2IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rr) + .value("VCVTTPH2IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rrk) + .value("VCVTTPH2IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZ256rrkz) + .value("VCVTTPH2IBSZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrm) + .value("VCVTTPH2IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrmb) + .value("VCVTTPH2IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrmbk) + .value("VCVTTPH2IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrmbkz) + .value("VCVTTPH2IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrmk) + .value("VCVTTPH2IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrmkz) + .value("VCVTTPH2IBSZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrr) + .value("VCVTTPH2IBSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrrb) + .value("VCVTTPH2IBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrrbk) + .value("VCVTTPH2IBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrrbkz) + .value("VCVTTPH2IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrrk) + .value("VCVTTPH2IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IBSZrrkz) + .value("VCVTTPH2IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rm) + .value("VCVTTPH2IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rmb) + .value("VCVTTPH2IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rmbk) + .value("VCVTTPH2IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rmbkz) + .value("VCVTTPH2IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rmk) + .value("VCVTTPH2IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rmkz) + .value("VCVTTPH2IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rr) + .value("VCVTTPH2IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rrk) + .value("VCVTTPH2IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ128rrkz) + .value("VCVTTPH2IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rm) + .value("VCVTTPH2IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rmb) + .value("VCVTTPH2IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rmbk) + .value("VCVTTPH2IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rmbkz) + .value("VCVTTPH2IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rmk) + .value("VCVTTPH2IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rmkz) + .value("VCVTTPH2IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rr) + .value("VCVTTPH2IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rrk) + .value("VCVTTPH2IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZ256rrkz) + .value("VCVTTPH2IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrm) + .value("VCVTTPH2IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrmb) + .value("VCVTTPH2IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrmbk) + .value("VCVTTPH2IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrmbkz) + .value("VCVTTPH2IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrmk) + .value("VCVTTPH2IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrmkz) + .value("VCVTTPH2IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrr) + .value("VCVTTPH2IUBSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrrb) + .value("VCVTTPH2IUBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrrbk) + .value("VCVTTPH2IUBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrrbkz) + .value("VCVTTPH2IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrrk) + .value("VCVTTPH2IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2IUBSZrrkz) + .value("VCVTTPH2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rm) + .value("VCVTTPH2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rmb) + .value("VCVTTPH2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rmbk) + .value("VCVTTPH2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rmbkz) + .value("VCVTTPH2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rmk) + .value("VCVTTPH2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rmkz) + .value("VCVTTPH2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rr) + .value("VCVTTPH2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rrk) + .value("VCVTTPH2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ128rrkz) + .value("VCVTTPH2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rm) + .value("VCVTTPH2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rmb) + .value("VCVTTPH2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rmbk) + .value("VCVTTPH2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rmbkz) + .value("VCVTTPH2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rmk) + .value("VCVTTPH2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rmkz) + .value("VCVTTPH2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rr) + .value("VCVTTPH2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rrk) + .value("VCVTTPH2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZ256rrkz) + .value("VCVTTPH2QQZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrm) + .value("VCVTTPH2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrmb) + .value("VCVTTPH2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrmbk) + .value("VCVTTPH2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrmbkz) + .value("VCVTTPH2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrmk) + .value("VCVTTPH2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrmkz) + .value("VCVTTPH2QQZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrr) + .value("VCVTTPH2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrrb) + .value("VCVTTPH2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrrbk) + .value("VCVTTPH2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrrbkz) + .value("VCVTTPH2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrrk) + .value("VCVTTPH2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2QQZrrkz) + .value("VCVTTPH2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rm) + .value("VCVTTPH2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rmb) + .value("VCVTTPH2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rmbk) + .value("VCVTTPH2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rmbkz) + .value("VCVTTPH2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rmk) + .value("VCVTTPH2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rmkz) + .value("VCVTTPH2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rr) + .value("VCVTTPH2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rrk) + .value("VCVTTPH2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ128rrkz) + .value("VCVTTPH2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rm) + .value("VCVTTPH2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rmb) + .value("VCVTTPH2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rmbk) + .value("VCVTTPH2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rmbkz) + .value("VCVTTPH2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rmk) + .value("VCVTTPH2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rmkz) + .value("VCVTTPH2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rr) + .value("VCVTTPH2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rrk) + .value("VCVTTPH2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZ256rrkz) + .value("VCVTTPH2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrm) + .value("VCVTTPH2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrmb) + .value("VCVTTPH2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrmbk) + .value("VCVTTPH2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrmbkz) + .value("VCVTTPH2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrmk) + .value("VCVTTPH2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrmkz) + .value("VCVTTPH2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrr) + .value("VCVTTPH2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrrb) + .value("VCVTTPH2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrrbk) + .value("VCVTTPH2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrrbkz) + .value("VCVTTPH2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrrk) + .value("VCVTTPH2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UDQZrrkz) + .value("VCVTTPH2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rm) + .value("VCVTTPH2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rmb) + .value("VCVTTPH2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rmbk) + .value("VCVTTPH2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rmbkz) + .value("VCVTTPH2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rmk) + .value("VCVTTPH2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rmkz) + .value("VCVTTPH2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rr) + .value("VCVTTPH2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rrk) + .value("VCVTTPH2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ128rrkz) + .value("VCVTTPH2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rm) + .value("VCVTTPH2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rmb) + .value("VCVTTPH2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rmbk) + .value("VCVTTPH2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rmbkz) + .value("VCVTTPH2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rmk) + .value("VCVTTPH2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rmkz) + .value("VCVTTPH2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rr) + .value("VCVTTPH2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rrk) + .value("VCVTTPH2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZ256rrkz) + .value("VCVTTPH2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrm) + .value("VCVTTPH2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrmb) + .value("VCVTTPH2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrmbk) + .value("VCVTTPH2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrmbkz) + .value("VCVTTPH2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrmk) + .value("VCVTTPH2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrmkz) + .value("VCVTTPH2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrr) + .value("VCVTTPH2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrrb) + .value("VCVTTPH2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrrbk) + .value("VCVTTPH2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrrbkz) + .value("VCVTTPH2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrrk) + .value("VCVTTPH2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UQQZrrkz) + .value("VCVTTPH2UWZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rm) + .value("VCVTTPH2UWZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rmb) + .value("VCVTTPH2UWZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rmbk) + .value("VCVTTPH2UWZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rmbkz) + .value("VCVTTPH2UWZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rmk) + .value("VCVTTPH2UWZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rmkz) + .value("VCVTTPH2UWZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rr) + .value("VCVTTPH2UWZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rrk) + .value("VCVTTPH2UWZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ128rrkz) + .value("VCVTTPH2UWZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rm) + .value("VCVTTPH2UWZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rmb) + .value("VCVTTPH2UWZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rmbk) + .value("VCVTTPH2UWZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rmbkz) + .value("VCVTTPH2UWZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rmk) + .value("VCVTTPH2UWZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rmkz) + .value("VCVTTPH2UWZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rr) + .value("VCVTTPH2UWZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rrk) + .value("VCVTTPH2UWZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZ256rrkz) + .value("VCVTTPH2UWZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrm) + .value("VCVTTPH2UWZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrmb) + .value("VCVTTPH2UWZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrmbk) + .value("VCVTTPH2UWZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrmbkz) + .value("VCVTTPH2UWZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrmk) + .value("VCVTTPH2UWZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrmkz) + .value("VCVTTPH2UWZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrr) + .value("VCVTTPH2UWZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrrb) + .value("VCVTTPH2UWZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrrbk) + .value("VCVTTPH2UWZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrrbkz) + .value("VCVTTPH2UWZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrrk) + .value("VCVTTPH2UWZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2UWZrrkz) + .value("VCVTTPH2WZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rm) + .value("VCVTTPH2WZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rmb) + .value("VCVTTPH2WZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rmbk) + .value("VCVTTPH2WZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rmbkz) + .value("VCVTTPH2WZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rmk) + .value("VCVTTPH2WZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rmkz) + .value("VCVTTPH2WZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rr) + .value("VCVTTPH2WZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rrk) + .value("VCVTTPH2WZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ128rrkz) + .value("VCVTTPH2WZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rm) + .value("VCVTTPH2WZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rmb) + .value("VCVTTPH2WZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rmbk) + .value("VCVTTPH2WZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rmbkz) + .value("VCVTTPH2WZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rmk) + .value("VCVTTPH2WZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rmkz) + .value("VCVTTPH2WZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rr) + .value("VCVTTPH2WZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rrk) + .value("VCVTTPH2WZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZ256rrkz) + .value("VCVTTPH2WZrm", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrm) + .value("VCVTTPH2WZrmb", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrmb) + .value("VCVTTPH2WZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrmbk) + .value("VCVTTPH2WZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrmbkz) + .value("VCVTTPH2WZrmk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrmk) + .value("VCVTTPH2WZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrmkz) + .value("VCVTTPH2WZrr", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrr) + .value("VCVTTPH2WZrrb", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrrb) + .value("VCVTTPH2WZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrrbk) + .value("VCVTTPH2WZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrrbkz) + .value("VCVTTPH2WZrrk", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrrk) + .value("VCVTTPH2WZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPH2WZrrkz) + .value("VCVTTPS2DQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rm) + .value("VCVTTPS2DQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rmb) + .value("VCVTTPS2DQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rmbk) + .value("VCVTTPS2DQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rmbkz) + .value("VCVTTPS2DQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rmk) + .value("VCVTTPS2DQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rmkz) + .value("VCVTTPS2DQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rr) + .value("VCVTTPS2DQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rrk) + .value("VCVTTPS2DQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ128rrkz) + .value("VCVTTPS2DQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rm) + .value("VCVTTPS2DQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rmb) + .value("VCVTTPS2DQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rmbk) + .value("VCVTTPS2DQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rmbkz) + .value("VCVTTPS2DQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rmk) + .value("VCVTTPS2DQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rmkz) + .value("VCVTTPS2DQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rr) + .value("VCVTTPS2DQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rrk) + .value("VCVTTPS2DQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZ256rrkz) + .value("VCVTTPS2DQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrm) + .value("VCVTTPS2DQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrmb) + .value("VCVTTPS2DQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrmbk) + .value("VCVTTPS2DQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrmbkz) + .value("VCVTTPS2DQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrmk) + .value("VCVTTPS2DQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrmkz) + .value("VCVTTPS2DQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrr) + .value("VCVTTPS2DQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrrb) + .value("VCVTTPS2DQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrrbk) + .value("VCVTTPS2DQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrrbkz) + .value("VCVTTPS2DQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrrk) + .value("VCVTTPS2DQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQSZrrkz) + .value("VCVTTPS2DQYrm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQYrm); + opcodes.value("VCVTTPS2DQYrr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQYrr) + .value("VCVTTPS2DQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rm) + .value("VCVTTPS2DQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rmb) + .value("VCVTTPS2DQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rmbk) + .value("VCVTTPS2DQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rmbkz) + .value("VCVTTPS2DQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rmk) + .value("VCVTTPS2DQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rmkz) + .value("VCVTTPS2DQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rr) + .value("VCVTTPS2DQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rrk) + .value("VCVTTPS2DQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ128rrkz) + .value("VCVTTPS2DQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rm) + .value("VCVTTPS2DQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rmb) + .value("VCVTTPS2DQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rmbk) + .value("VCVTTPS2DQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rmbkz) + .value("VCVTTPS2DQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rmk) + .value("VCVTTPS2DQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rmkz) + .value("VCVTTPS2DQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rr) + .value("VCVTTPS2DQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rrk) + .value("VCVTTPS2DQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZ256rrkz) + .value("VCVTTPS2DQZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrm) + .value("VCVTTPS2DQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrmb) + .value("VCVTTPS2DQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrmbk) + .value("VCVTTPS2DQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrmbkz) + .value("VCVTTPS2DQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrmk) + .value("VCVTTPS2DQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrmkz) + .value("VCVTTPS2DQZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrr) + .value("VCVTTPS2DQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrrb) + .value("VCVTTPS2DQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrrbk) + .value("VCVTTPS2DQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrrbkz) + .value("VCVTTPS2DQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrrk) + .value("VCVTTPS2DQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2DQZrrkz) + .value("VCVTTPS2DQrm", LIEF::assembly::x86::OPCODE::VCVTTPS2DQrm) + .value("VCVTTPS2DQrr", LIEF::assembly::x86::OPCODE::VCVTTPS2DQrr) + .value("VCVTTPS2IBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rm) + .value("VCVTTPS2IBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rmb) + .value("VCVTTPS2IBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rmbk) + .value("VCVTTPS2IBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rmbkz) + .value("VCVTTPS2IBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rmk) + .value("VCVTTPS2IBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rmkz) + .value("VCVTTPS2IBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rr) + .value("VCVTTPS2IBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rrk) + .value("VCVTTPS2IBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ128rrkz) + .value("VCVTTPS2IBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rm) + .value("VCVTTPS2IBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rmb) + .value("VCVTTPS2IBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rmbk) + .value("VCVTTPS2IBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rmbkz) + .value("VCVTTPS2IBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rmk) + .value("VCVTTPS2IBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rmkz) + .value("VCVTTPS2IBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rr) + .value("VCVTTPS2IBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rrk) + .value("VCVTTPS2IBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZ256rrkz) + .value("VCVTTPS2IBSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrm) + .value("VCVTTPS2IBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrmb) + .value("VCVTTPS2IBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrmbk) + .value("VCVTTPS2IBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrmbkz) + .value("VCVTTPS2IBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrmk) + .value("VCVTTPS2IBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrmkz) + .value("VCVTTPS2IBSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrr) + .value("VCVTTPS2IBSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrrb) + .value("VCVTTPS2IBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrrbk) + .value("VCVTTPS2IBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrrbkz) + .value("VCVTTPS2IBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrrk) + .value("VCVTTPS2IBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IBSZrrkz) + .value("VCVTTPS2IUBSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rm) + .value("VCVTTPS2IUBSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rmb) + .value("VCVTTPS2IUBSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rmbk) + .value("VCVTTPS2IUBSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rmbkz) + .value("VCVTTPS2IUBSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rmk) + .value("VCVTTPS2IUBSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rmkz) + .value("VCVTTPS2IUBSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rr) + .value("VCVTTPS2IUBSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rrk) + .value("VCVTTPS2IUBSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ128rrkz) + .value("VCVTTPS2IUBSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rm) + .value("VCVTTPS2IUBSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rmb) + .value("VCVTTPS2IUBSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rmbk) + .value("VCVTTPS2IUBSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rmbkz) + .value("VCVTTPS2IUBSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rmk) + .value("VCVTTPS2IUBSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rmkz) + .value("VCVTTPS2IUBSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rr) + .value("VCVTTPS2IUBSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rrk) + .value("VCVTTPS2IUBSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZ256rrkz) + .value("VCVTTPS2IUBSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrm) + .value("VCVTTPS2IUBSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrmb) + .value("VCVTTPS2IUBSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrmbk) + .value("VCVTTPS2IUBSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrmbkz) + .value("VCVTTPS2IUBSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrmk) + .value("VCVTTPS2IUBSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrmkz) + .value("VCVTTPS2IUBSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrr) + .value("VCVTTPS2IUBSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrrb) + .value("VCVTTPS2IUBSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrrbk) + .value("VCVTTPS2IUBSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrrbkz) + .value("VCVTTPS2IUBSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrrk) + .value("VCVTTPS2IUBSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2IUBSZrrkz) + .value("VCVTTPS2QQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rm) + .value("VCVTTPS2QQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rmb) + .value("VCVTTPS2QQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rmbk) + .value("VCVTTPS2QQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rmbkz) + .value("VCVTTPS2QQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rmk) + .value("VCVTTPS2QQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rmkz) + .value("VCVTTPS2QQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rr) + .value("VCVTTPS2QQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rrk) + .value("VCVTTPS2QQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ128rrkz) + .value("VCVTTPS2QQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rm) + .value("VCVTTPS2QQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rmb) + .value("VCVTTPS2QQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rmbk) + .value("VCVTTPS2QQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rmbkz) + .value("VCVTTPS2QQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rmk) + .value("VCVTTPS2QQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rmkz) + .value("VCVTTPS2QQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rr) + .value("VCVTTPS2QQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rrb) + .value("VCVTTPS2QQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rrbk) + .value("VCVTTPS2QQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rrbkz) + .value("VCVTTPS2QQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rrk) + .value("VCVTTPS2QQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZ256rrkz) + .value("VCVTTPS2QQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrm) + .value("VCVTTPS2QQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrmb) + .value("VCVTTPS2QQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrmbk) + .value("VCVTTPS2QQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrmbkz) + .value("VCVTTPS2QQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrmk) + .value("VCVTTPS2QQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrmkz) + .value("VCVTTPS2QQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrr) + .value("VCVTTPS2QQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrrb) + .value("VCVTTPS2QQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrrbk) + .value("VCVTTPS2QQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrrbkz) + .value("VCVTTPS2QQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrrk) + .value("VCVTTPS2QQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQSZrrkz) + .value("VCVTTPS2QQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rm) + .value("VCVTTPS2QQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rmb) + .value("VCVTTPS2QQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rmbk) + .value("VCVTTPS2QQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rmbkz) + .value("VCVTTPS2QQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rmk) + .value("VCVTTPS2QQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rmkz) + .value("VCVTTPS2QQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rr) + .value("VCVTTPS2QQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rrk) + .value("VCVTTPS2QQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ128rrkz) + .value("VCVTTPS2QQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rm) + .value("VCVTTPS2QQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rmb) + .value("VCVTTPS2QQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rmbk) + .value("VCVTTPS2QQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rmbkz) + .value("VCVTTPS2QQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rmk) + .value("VCVTTPS2QQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rmkz) + .value("VCVTTPS2QQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rr) + .value("VCVTTPS2QQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rrk) + .value("VCVTTPS2QQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZ256rrkz) + .value("VCVTTPS2QQZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrm) + .value("VCVTTPS2QQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrmb) + .value("VCVTTPS2QQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrmbk) + .value("VCVTTPS2QQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrmbkz) + .value("VCVTTPS2QQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrmk) + .value("VCVTTPS2QQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrmkz) + .value("VCVTTPS2QQZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrr) + .value("VCVTTPS2QQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrrb) + .value("VCVTTPS2QQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrrbk) + .value("VCVTTPS2QQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrrbkz) + .value("VCVTTPS2QQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrrk) + .value("VCVTTPS2QQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2QQZrrkz) + .value("VCVTTPS2UDQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rm) + .value("VCVTTPS2UDQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rmb) + .value("VCVTTPS2UDQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rmbk) + .value("VCVTTPS2UDQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rmbkz) + .value("VCVTTPS2UDQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rmk) + .value("VCVTTPS2UDQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rmkz) + .value("VCVTTPS2UDQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rr) + .value("VCVTTPS2UDQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rrk) + .value("VCVTTPS2UDQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ128rrkz) + .value("VCVTTPS2UDQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rm) + .value("VCVTTPS2UDQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rmb) + .value("VCVTTPS2UDQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rmbk) + .value("VCVTTPS2UDQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rmbkz) + .value("VCVTTPS2UDQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rmk) + .value("VCVTTPS2UDQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rmkz) + .value("VCVTTPS2UDQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rr) + .value("VCVTTPS2UDQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rrk) + .value("VCVTTPS2UDQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZ256rrkz) + .value("VCVTTPS2UDQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrm) + .value("VCVTTPS2UDQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrmb) + .value("VCVTTPS2UDQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrmbk) + .value("VCVTTPS2UDQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrmbkz) + .value("VCVTTPS2UDQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrmk) + .value("VCVTTPS2UDQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrmkz) + .value("VCVTTPS2UDQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrr) + .value("VCVTTPS2UDQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrrb) + .value("VCVTTPS2UDQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrrbk) + .value("VCVTTPS2UDQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrrbkz) + .value("VCVTTPS2UDQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrrk) + .value("VCVTTPS2UDQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQSZrrkz) + .value("VCVTTPS2UDQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rm) + .value("VCVTTPS2UDQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rmb) + .value("VCVTTPS2UDQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rmbk) + .value("VCVTTPS2UDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rmbkz) + .value("VCVTTPS2UDQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rmk) + .value("VCVTTPS2UDQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rmkz) + .value("VCVTTPS2UDQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rr) + .value("VCVTTPS2UDQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rrk) + .value("VCVTTPS2UDQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ128rrkz) + .value("VCVTTPS2UDQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rm) + .value("VCVTTPS2UDQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rmb) + .value("VCVTTPS2UDQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rmbk) + .value("VCVTTPS2UDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rmbkz) + .value("VCVTTPS2UDQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rmk) + .value("VCVTTPS2UDQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rmkz) + .value("VCVTTPS2UDQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rr) + .value("VCVTTPS2UDQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rrk) + .value("VCVTTPS2UDQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZ256rrkz) + .value("VCVTTPS2UDQZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrm) + .value("VCVTTPS2UDQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrmb) + .value("VCVTTPS2UDQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrmbk) + .value("VCVTTPS2UDQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrmbkz) + .value("VCVTTPS2UDQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrmk) + .value("VCVTTPS2UDQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrmkz) + .value("VCVTTPS2UDQZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrr) + .value("VCVTTPS2UDQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrrb) + .value("VCVTTPS2UDQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrrbk) + .value("VCVTTPS2UDQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrrbkz) + .value("VCVTTPS2UDQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrrk) + .value("VCVTTPS2UDQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UDQZrrkz) + .value("VCVTTPS2UQQSZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rm) + .value("VCVTTPS2UQQSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rmb) + .value("VCVTTPS2UQQSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rmbk) + .value("VCVTTPS2UQQSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rmbkz) + .value("VCVTTPS2UQQSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rmk) + .value("VCVTTPS2UQQSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rmkz) + .value("VCVTTPS2UQQSZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rr) + .value("VCVTTPS2UQQSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rrk) + .value("VCVTTPS2UQQSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ128rrkz) + .value("VCVTTPS2UQQSZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rm) + .value("VCVTTPS2UQQSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rmb) + .value("VCVTTPS2UQQSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rmbk) + .value("VCVTTPS2UQQSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rmbkz) + .value("VCVTTPS2UQQSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rmk) + .value("VCVTTPS2UQQSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rmkz) + .value("VCVTTPS2UQQSZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rr) + .value("VCVTTPS2UQQSZ256rrb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rrb) + .value("VCVTTPS2UQQSZ256rrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rrbk) + .value("VCVTTPS2UQQSZ256rrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rrbkz) + .value("VCVTTPS2UQQSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rrk) + .value("VCVTTPS2UQQSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZ256rrkz) + .value("VCVTTPS2UQQSZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrm) + .value("VCVTTPS2UQQSZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrmb) + .value("VCVTTPS2UQQSZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrmbk) + .value("VCVTTPS2UQQSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrmbkz) + .value("VCVTTPS2UQQSZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrmk) + .value("VCVTTPS2UQQSZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrmkz) + .value("VCVTTPS2UQQSZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrr) + .value("VCVTTPS2UQQSZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrrb) + .value("VCVTTPS2UQQSZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrrbk) + .value("VCVTTPS2UQQSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrrbkz) + .value("VCVTTPS2UQQSZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrrk) + .value("VCVTTPS2UQQSZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQSZrrkz) + .value("VCVTTPS2UQQZ128rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rm) + .value("VCVTTPS2UQQZ128rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rmb) + .value("VCVTTPS2UQQZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rmbk) + .value("VCVTTPS2UQQZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rmbkz) + .value("VCVTTPS2UQQZ128rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rmk) + .value("VCVTTPS2UQQZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rmkz) + .value("VCVTTPS2UQQZ128rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rr) + .value("VCVTTPS2UQQZ128rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rrk) + .value("VCVTTPS2UQQZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ128rrkz) + .value("VCVTTPS2UQQZ256rm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rm) + .value("VCVTTPS2UQQZ256rmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rmb) + .value("VCVTTPS2UQQZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rmbk) + .value("VCVTTPS2UQQZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rmbkz) + .value("VCVTTPS2UQQZ256rmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rmk) + .value("VCVTTPS2UQQZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rmkz) + .value("VCVTTPS2UQQZ256rr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rr) + .value("VCVTTPS2UQQZ256rrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rrk) + .value("VCVTTPS2UQQZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZ256rrkz) + .value("VCVTTPS2UQQZrm", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrm) + .value("VCVTTPS2UQQZrmb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrmb) + .value("VCVTTPS2UQQZrmbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrmbk) + .value("VCVTTPS2UQQZrmbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrmbkz) + .value("VCVTTPS2UQQZrmk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrmk) + .value("VCVTTPS2UQQZrmkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrmkz) + .value("VCVTTPS2UQQZrr", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrr) + .value("VCVTTPS2UQQZrrb", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrrb) + .value("VCVTTPS2UQQZrrbk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrrbk) + .value("VCVTTPS2UQQZrrbkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrrbkz) + .value("VCVTTPS2UQQZrrk", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrrk) + .value("VCVTTPS2UQQZrrkz", LIEF::assembly::x86::OPCODE::VCVTTPS2UQQZrrkz) + .value("VCVTTSD2SI64Srm", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Srm) + .value("VCVTTSD2SI64Srm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Srm_Int) + .value("VCVTTSD2SI64Srr", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Srr) + .value("VCVTTSD2SI64Srr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Srr_Int) + .value("VCVTTSD2SI64Srrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Srrb_Int) + .value("VCVTTSD2SI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Zrm) + .value("VCVTTSD2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Zrm_Int) + .value("VCVTTSD2SI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Zrr) + .value("VCVTTSD2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Zrr_Int) + .value("VCVTTSD2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64Zrrb_Int) + .value("VCVTTSD2SI64rm", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64rm) + .value("VCVTTSD2SI64rm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64rm_Int) + .value("VCVTTSD2SI64rr", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64rr) + .value("VCVTTSD2SI64rr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SI64rr_Int) + .value("VCVTTSD2SISrm", LIEF::assembly::x86::OPCODE::VCVTTSD2SISrm) + .value("VCVTTSD2SISrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SISrm_Int) + .value("VCVTTSD2SISrr", LIEF::assembly::x86::OPCODE::VCVTTSD2SISrr) + .value("VCVTTSD2SISrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SISrr_Int) + .value("VCVTTSD2SISrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SISrrb_Int) + .value("VCVTTSD2SIZrm", LIEF::assembly::x86::OPCODE::VCVTTSD2SIZrm) + .value("VCVTTSD2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SIZrm_Int); + opcodes.value("VCVTTSD2SIZrr", LIEF::assembly::x86::OPCODE::VCVTTSD2SIZrr) + .value("VCVTTSD2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SIZrr_Int) + .value("VCVTTSD2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SIZrrb_Int) + .value("VCVTTSD2SIrm", LIEF::assembly::x86::OPCODE::VCVTTSD2SIrm) + .value("VCVTTSD2SIrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SIrm_Int) + .value("VCVTTSD2SIrr", LIEF::assembly::x86::OPCODE::VCVTTSD2SIrr) + .value("VCVTTSD2SIrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2SIrr_Int) + .value("VCVTTSD2USI64Srm", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Srm) + .value("VCVTTSD2USI64Srm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Srm_Int) + .value("VCVTTSD2USI64Srr", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Srr) + .value("VCVTTSD2USI64Srr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Srr_Int) + .value("VCVTTSD2USI64Srrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Srrb_Int) + .value("VCVTTSD2USI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Zrm) + .value("VCVTTSD2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Zrm_Int) + .value("VCVTTSD2USI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Zrr) + .value("VCVTTSD2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Zrr_Int) + .value("VCVTTSD2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USI64Zrrb_Int) + .value("VCVTTSD2USISrm", LIEF::assembly::x86::OPCODE::VCVTTSD2USISrm) + .value("VCVTTSD2USISrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USISrm_Int) + .value("VCVTTSD2USISrr", LIEF::assembly::x86::OPCODE::VCVTTSD2USISrr) + .value("VCVTTSD2USISrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USISrr_Int) + .value("VCVTTSD2USISrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USISrrb_Int) + .value("VCVTTSD2USIZrm", LIEF::assembly::x86::OPCODE::VCVTTSD2USIZrm) + .value("VCVTTSD2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USIZrm_Int) + .value("VCVTTSD2USIZrr", LIEF::assembly::x86::OPCODE::VCVTTSD2USIZrr) + .value("VCVTTSD2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USIZrr_Int) + .value("VCVTTSD2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSD2USIZrrb_Int) + .value("VCVTTSH2SI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSH2SI64Zrm) + .value("VCVTTSH2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SI64Zrm_Int) + .value("VCVTTSH2SI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSH2SI64Zrr) + .value("VCVTTSH2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SI64Zrr_Int) + .value("VCVTTSH2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SI64Zrrb_Int) + .value("VCVTTSH2SIZrm", LIEF::assembly::x86::OPCODE::VCVTTSH2SIZrm) + .value("VCVTTSH2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SIZrm_Int) + .value("VCVTTSH2SIZrr", LIEF::assembly::x86::OPCODE::VCVTTSH2SIZrr) + .value("VCVTTSH2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SIZrr_Int) + .value("VCVTTSH2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2SIZrrb_Int) + .value("VCVTTSH2USI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSH2USI64Zrm) + .value("VCVTTSH2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USI64Zrm_Int) + .value("VCVTTSH2USI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSH2USI64Zrr) + .value("VCVTTSH2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USI64Zrr_Int) + .value("VCVTTSH2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USI64Zrrb_Int) + .value("VCVTTSH2USIZrm", LIEF::assembly::x86::OPCODE::VCVTTSH2USIZrm) + .value("VCVTTSH2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USIZrm_Int) + .value("VCVTTSH2USIZrr", LIEF::assembly::x86::OPCODE::VCVTTSH2USIZrr) + .value("VCVTTSH2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USIZrr_Int) + .value("VCVTTSH2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSH2USIZrrb_Int) + .value("VCVTTSS2SI64Srm", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Srm) + .value("VCVTTSS2SI64Srm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Srm_Int) + .value("VCVTTSS2SI64Srr", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Srr) + .value("VCVTTSS2SI64Srr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Srr_Int) + .value("VCVTTSS2SI64Srrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Srrb_Int) + .value("VCVTTSS2SI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Zrm) + .value("VCVTTSS2SI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Zrm_Int) + .value("VCVTTSS2SI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Zrr) + .value("VCVTTSS2SI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Zrr_Int) + .value("VCVTTSS2SI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64Zrrb_Int) + .value("VCVTTSS2SI64rm", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64rm) + .value("VCVTTSS2SI64rm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64rm_Int) + .value("VCVTTSS2SI64rr", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64rr) + .value("VCVTTSS2SI64rr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SI64rr_Int) + .value("VCVTTSS2SISrm", LIEF::assembly::x86::OPCODE::VCVTTSS2SISrm) + .value("VCVTTSS2SISrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SISrm_Int) + .value("VCVTTSS2SISrr", LIEF::assembly::x86::OPCODE::VCVTTSS2SISrr) + .value("VCVTTSS2SISrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SISrr_Int) + .value("VCVTTSS2SISrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SISrrb_Int) + .value("VCVTTSS2SIZrm", LIEF::assembly::x86::OPCODE::VCVTTSS2SIZrm) + .value("VCVTTSS2SIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SIZrm_Int) + .value("VCVTTSS2SIZrr", LIEF::assembly::x86::OPCODE::VCVTTSS2SIZrr) + .value("VCVTTSS2SIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SIZrr_Int) + .value("VCVTTSS2SIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SIZrrb_Int) + .value("VCVTTSS2SIrm", LIEF::assembly::x86::OPCODE::VCVTTSS2SIrm) + .value("VCVTTSS2SIrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SIrm_Int) + .value("VCVTTSS2SIrr", LIEF::assembly::x86::OPCODE::VCVTTSS2SIrr) + .value("VCVTTSS2SIrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2SIrr_Int) + .value("VCVTTSS2USI64Srm", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Srm) + .value("VCVTTSS2USI64Srm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Srm_Int) + .value("VCVTTSS2USI64Srr", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Srr) + .value("VCVTTSS2USI64Srr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Srr_Int) + .value("VCVTTSS2USI64Srrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Srrb_Int) + .value("VCVTTSS2USI64Zrm", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Zrm) + .value("VCVTTSS2USI64Zrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Zrm_Int) + .value("VCVTTSS2USI64Zrr", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Zrr) + .value("VCVTTSS2USI64Zrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Zrr_Int) + .value("VCVTTSS2USI64Zrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USI64Zrrb_Int) + .value("VCVTTSS2USISrm", LIEF::assembly::x86::OPCODE::VCVTTSS2USISrm) + .value("VCVTTSS2USISrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USISrm_Int) + .value("VCVTTSS2USISrr", LIEF::assembly::x86::OPCODE::VCVTTSS2USISrr) + .value("VCVTTSS2USISrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USISrr_Int) + .value("VCVTTSS2USISrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USISrrb_Int) + .value("VCVTTSS2USIZrm", LIEF::assembly::x86::OPCODE::VCVTTSS2USIZrm) + .value("VCVTTSS2USIZrm_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USIZrm_Int) + .value("VCVTTSS2USIZrr", LIEF::assembly::x86::OPCODE::VCVTTSS2USIZrr) + .value("VCVTTSS2USIZrr_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USIZrr_Int) + .value("VCVTTSS2USIZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTTSS2USIZrrb_Int) + .value("VCVTUDQ2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rm) + .value("VCVTUDQ2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rmb) + .value("VCVTUDQ2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rmbk) + .value("VCVTUDQ2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rmbkz) + .value("VCVTUDQ2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rmk) + .value("VCVTUDQ2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rmkz) + .value("VCVTUDQ2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rr) + .value("VCVTUDQ2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rrk) + .value("VCVTUDQ2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ128rrkz) + .value("VCVTUDQ2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rm) + .value("VCVTUDQ2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rmb) + .value("VCVTUDQ2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rmbk) + .value("VCVTUDQ2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rmbkz) + .value("VCVTUDQ2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rmk) + .value("VCVTUDQ2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rmkz) + .value("VCVTUDQ2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rr) + .value("VCVTUDQ2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rrk) + .value("VCVTUDQ2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZ256rrkz) + .value("VCVTUDQ2PDZrm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrm) + .value("VCVTUDQ2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrmb) + .value("VCVTUDQ2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrmbk) + .value("VCVTUDQ2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrmbkz) + .value("VCVTUDQ2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrmk) + .value("VCVTUDQ2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrmkz) + .value("VCVTUDQ2PDZrr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrr) + .value("VCVTUDQ2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrrk) + .value("VCVTUDQ2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PDZrrkz) + .value("VCVTUDQ2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rm) + .value("VCVTUDQ2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rmb) + .value("VCVTUDQ2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rmbk) + .value("VCVTUDQ2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rmbkz) + .value("VCVTUDQ2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rmk) + .value("VCVTUDQ2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rmkz) + .value("VCVTUDQ2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rr) + .value("VCVTUDQ2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rrk) + .value("VCVTUDQ2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ128rrkz) + .value("VCVTUDQ2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rm) + .value("VCVTUDQ2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rmb) + .value("VCVTUDQ2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rmbk) + .value("VCVTUDQ2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rmbkz) + .value("VCVTUDQ2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rmk) + .value("VCVTUDQ2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rmkz) + .value("VCVTUDQ2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rr) + .value("VCVTUDQ2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rrk) + .value("VCVTUDQ2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZ256rrkz) + .value("VCVTUDQ2PHZrm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrm) + .value("VCVTUDQ2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrmb) + .value("VCVTUDQ2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrmbk) + .value("VCVTUDQ2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrmbkz) + .value("VCVTUDQ2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrmk) + .value("VCVTUDQ2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrmkz) + .value("VCVTUDQ2PHZrr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrr) + .value("VCVTUDQ2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrrb) + .value("VCVTUDQ2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrrbk) + .value("VCVTUDQ2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrrbkz) + .value("VCVTUDQ2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrrk) + .value("VCVTUDQ2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PHZrrkz) + .value("VCVTUDQ2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rm) + .value("VCVTUDQ2PSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rmb) + .value("VCVTUDQ2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rmbk) + .value("VCVTUDQ2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rmbkz) + .value("VCVTUDQ2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rmk) + .value("VCVTUDQ2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rmkz) + .value("VCVTUDQ2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rr) + .value("VCVTUDQ2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rrk) + .value("VCVTUDQ2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ128rrkz) + .value("VCVTUDQ2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rm) + .value("VCVTUDQ2PSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rmb) + .value("VCVTUDQ2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rmbk) + .value("VCVTUDQ2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rmbkz) + .value("VCVTUDQ2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rmk) + .value("VCVTUDQ2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rmkz) + .value("VCVTUDQ2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rr) + .value("VCVTUDQ2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rrk) + .value("VCVTUDQ2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZ256rrkz) + .value("VCVTUDQ2PSZrm", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrm) + .value("VCVTUDQ2PSZrmb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrmb) + .value("VCVTUDQ2PSZrmbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrmbk) + .value("VCVTUDQ2PSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrmbkz) + .value("VCVTUDQ2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrmk) + .value("VCVTUDQ2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrmkz) + .value("VCVTUDQ2PSZrr", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrr) + .value("VCVTUDQ2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrrb) + .value("VCVTUDQ2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrrbk) + .value("VCVTUDQ2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrrbkz) + .value("VCVTUDQ2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrrk) + .value("VCVTUDQ2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTUDQ2PSZrrkz) + .value("VCVTUQQ2PDZ128rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rm) + .value("VCVTUQQ2PDZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rmb) + .value("VCVTUQQ2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rmbk) + .value("VCVTUQQ2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rmbkz) + .value("VCVTUQQ2PDZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rmk) + .value("VCVTUQQ2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rmkz) + .value("VCVTUQQ2PDZ128rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rr) + .value("VCVTUQQ2PDZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rrk) + .value("VCVTUQQ2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ128rrkz) + .value("VCVTUQQ2PDZ256rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rm) + .value("VCVTUQQ2PDZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rmb) + .value("VCVTUQQ2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rmbk) + .value("VCVTUQQ2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rmbkz) + .value("VCVTUQQ2PDZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rmk) + .value("VCVTUQQ2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rmkz) + .value("VCVTUQQ2PDZ256rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rr) + .value("VCVTUQQ2PDZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rrk) + .value("VCVTUQQ2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZ256rrkz) + .value("VCVTUQQ2PDZrm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrm) + .value("VCVTUQQ2PDZrmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrmb) + .value("VCVTUQQ2PDZrmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrmbk) + .value("VCVTUQQ2PDZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrmbkz) + .value("VCVTUQQ2PDZrmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrmk) + .value("VCVTUQQ2PDZrmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrmkz) + .value("VCVTUQQ2PDZrr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrr) + .value("VCVTUQQ2PDZrrb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrrb) + .value("VCVTUQQ2PDZrrbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrrbk) + .value("VCVTUQQ2PDZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrrbkz) + .value("VCVTUQQ2PDZrrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrrk) + .value("VCVTUQQ2PDZrrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PDZrrkz) + .value("VCVTUQQ2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rm) + .value("VCVTUQQ2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rmb) + .value("VCVTUQQ2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rmbk) + .value("VCVTUQQ2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rmbkz) + .value("VCVTUQQ2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rmk) + .value("VCVTUQQ2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rmkz) + .value("VCVTUQQ2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rr) + .value("VCVTUQQ2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rrk) + .value("VCVTUQQ2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ128rrkz) + .value("VCVTUQQ2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rm) + .value("VCVTUQQ2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rmb) + .value("VCVTUQQ2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rmbk) + .value("VCVTUQQ2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rmbkz) + .value("VCVTUQQ2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rmk) + .value("VCVTUQQ2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rmkz) + .value("VCVTUQQ2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rr) + .value("VCVTUQQ2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rrk) + .value("VCVTUQQ2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZ256rrkz) + .value("VCVTUQQ2PHZrm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrm) + .value("VCVTUQQ2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrmb) + .value("VCVTUQQ2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrmbk) + .value("VCVTUQQ2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrmbkz) + .value("VCVTUQQ2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrmk) + .value("VCVTUQQ2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrmkz) + .value("VCVTUQQ2PHZrr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrr) + .value("VCVTUQQ2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrrb) + .value("VCVTUQQ2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrrbk) + .value("VCVTUQQ2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrrbkz) + .value("VCVTUQQ2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrrk) + .value("VCVTUQQ2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PHZrrkz) + .value("VCVTUQQ2PSZ128rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rm) + .value("VCVTUQQ2PSZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rmb) + .value("VCVTUQQ2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rmbk) + .value("VCVTUQQ2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rmbkz) + .value("VCVTUQQ2PSZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rmk) + .value("VCVTUQQ2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rmkz) + .value("VCVTUQQ2PSZ128rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rr) + .value("VCVTUQQ2PSZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rrk) + .value("VCVTUQQ2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ128rrkz) + .value("VCVTUQQ2PSZ256rm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rm) + .value("VCVTUQQ2PSZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rmb) + .value("VCVTUQQ2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rmbk) + .value("VCVTUQQ2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rmbkz) + .value("VCVTUQQ2PSZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rmk) + .value("VCVTUQQ2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rmkz) + .value("VCVTUQQ2PSZ256rr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rr) + .value("VCVTUQQ2PSZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rrk) + .value("VCVTUQQ2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZ256rrkz) + .value("VCVTUQQ2PSZrm", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrm) + .value("VCVTUQQ2PSZrmb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrmb) + .value("VCVTUQQ2PSZrmbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrmbk) + .value("VCVTUQQ2PSZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrmbkz) + .value("VCVTUQQ2PSZrmk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrmk) + .value("VCVTUQQ2PSZrmkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrmkz) + .value("VCVTUQQ2PSZrr", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrr) + .value("VCVTUQQ2PSZrrb", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrrb) + .value("VCVTUQQ2PSZrrbk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrrbk) + .value("VCVTUQQ2PSZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrrbkz) + .value("VCVTUQQ2PSZrrk", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrrk) + .value("VCVTUQQ2PSZrrkz", LIEF::assembly::x86::OPCODE::VCVTUQQ2PSZrrkz) + .value("VCVTUSI2SDZrm", LIEF::assembly::x86::OPCODE::VCVTUSI2SDZrm) + .value("VCVTUSI2SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SDZrm_Int) + .value("VCVTUSI2SDZrr", LIEF::assembly::x86::OPCODE::VCVTUSI2SDZrr) + .value("VCVTUSI2SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SDZrr_Int) + .value("VCVTUSI2SHZrm", LIEF::assembly::x86::OPCODE::VCVTUSI2SHZrm) + .value("VCVTUSI2SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SHZrm_Int) + .value("VCVTUSI2SHZrr", LIEF::assembly::x86::OPCODE::VCVTUSI2SHZrr) + .value("VCVTUSI2SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SHZrr_Int) + .value("VCVTUSI2SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SHZrrb_Int) + .value("VCVTUSI2SSZrm", LIEF::assembly::x86::OPCODE::VCVTUSI2SSZrm) + .value("VCVTUSI2SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SSZrm_Int) + .value("VCVTUSI2SSZrr", LIEF::assembly::x86::OPCODE::VCVTUSI2SSZrr) + .value("VCVTUSI2SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SSZrr_Int) + .value("VCVTUSI2SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTUSI2SSZrrb_Int) + .value("VCVTUSI642SDZrm", LIEF::assembly::x86::OPCODE::VCVTUSI642SDZrm) + .value("VCVTUSI642SDZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SDZrm_Int) + .value("VCVTUSI642SDZrr", LIEF::assembly::x86::OPCODE::VCVTUSI642SDZrr) + .value("VCVTUSI642SDZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SDZrr_Int) + .value("VCVTUSI642SDZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SDZrrb_Int) + .value("VCVTUSI642SHZrm", LIEF::assembly::x86::OPCODE::VCVTUSI642SHZrm) + .value("VCVTUSI642SHZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SHZrm_Int) + .value("VCVTUSI642SHZrr", LIEF::assembly::x86::OPCODE::VCVTUSI642SHZrr) + .value("VCVTUSI642SHZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SHZrr_Int) + .value("VCVTUSI642SHZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SHZrrb_Int) + .value("VCVTUSI642SSZrm", LIEF::assembly::x86::OPCODE::VCVTUSI642SSZrm) + .value("VCVTUSI642SSZrm_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SSZrm_Int) + .value("VCVTUSI642SSZrr", LIEF::assembly::x86::OPCODE::VCVTUSI642SSZrr) + .value("VCVTUSI642SSZrr_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SSZrr_Int); + opcodes.value("VCVTUSI642SSZrrb_Int", LIEF::assembly::x86::OPCODE::VCVTUSI642SSZrrb_Int) + .value("VCVTUW2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rm) + .value("VCVTUW2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rmb) + .value("VCVTUW2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rmbk) + .value("VCVTUW2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rmbkz) + .value("VCVTUW2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rmk) + .value("VCVTUW2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rmkz) + .value("VCVTUW2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rr) + .value("VCVTUW2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rrk) + .value("VCVTUW2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ128rrkz) + .value("VCVTUW2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rm) + .value("VCVTUW2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rmb) + .value("VCVTUW2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rmbk) + .value("VCVTUW2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rmbkz) + .value("VCVTUW2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rmk) + .value("VCVTUW2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rmkz) + .value("VCVTUW2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rr) + .value("VCVTUW2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rrk) + .value("VCVTUW2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZ256rrkz) + .value("VCVTUW2PHZrm", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrm) + .value("VCVTUW2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrmb) + .value("VCVTUW2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrmbk) + .value("VCVTUW2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrmbkz) + .value("VCVTUW2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrmk) + .value("VCVTUW2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrmkz) + .value("VCVTUW2PHZrr", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrr) + .value("VCVTUW2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrrb) + .value("VCVTUW2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrrbk) + .value("VCVTUW2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrrbkz) + .value("VCVTUW2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrrk) + .value("VCVTUW2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTUW2PHZrrkz) + .value("VCVTW2PHZ128rm", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rm) + .value("VCVTW2PHZ128rmb", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rmb) + .value("VCVTW2PHZ128rmbk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rmbk) + .value("VCVTW2PHZ128rmbkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rmbkz) + .value("VCVTW2PHZ128rmk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rmk) + .value("VCVTW2PHZ128rmkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rmkz) + .value("VCVTW2PHZ128rr", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rr) + .value("VCVTW2PHZ128rrk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rrk) + .value("VCVTW2PHZ128rrkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ128rrkz) + .value("VCVTW2PHZ256rm", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rm) + .value("VCVTW2PHZ256rmb", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rmb) + .value("VCVTW2PHZ256rmbk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rmbk) + .value("VCVTW2PHZ256rmbkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rmbkz) + .value("VCVTW2PHZ256rmk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rmk) + .value("VCVTW2PHZ256rmkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rmkz) + .value("VCVTW2PHZ256rr", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rr) + .value("VCVTW2PHZ256rrk", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rrk) + .value("VCVTW2PHZ256rrkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZ256rrkz) + .value("VCVTW2PHZrm", LIEF::assembly::x86::OPCODE::VCVTW2PHZrm) + .value("VCVTW2PHZrmb", LIEF::assembly::x86::OPCODE::VCVTW2PHZrmb) + .value("VCVTW2PHZrmbk", LIEF::assembly::x86::OPCODE::VCVTW2PHZrmbk) + .value("VCVTW2PHZrmbkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZrmbkz) + .value("VCVTW2PHZrmk", LIEF::assembly::x86::OPCODE::VCVTW2PHZrmk) + .value("VCVTW2PHZrmkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZrmkz) + .value("VCVTW2PHZrr", LIEF::assembly::x86::OPCODE::VCVTW2PHZrr) + .value("VCVTW2PHZrrb", LIEF::assembly::x86::OPCODE::VCVTW2PHZrrb) + .value("VCVTW2PHZrrbk", LIEF::assembly::x86::OPCODE::VCVTW2PHZrrbk) + .value("VCVTW2PHZrrbkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZrrbkz) + .value("VCVTW2PHZrrk", LIEF::assembly::x86::OPCODE::VCVTW2PHZrrk) + .value("VCVTW2PHZrrkz", LIEF::assembly::x86::OPCODE::VCVTW2PHZrrkz) + .value("VDBPSADBWZ128rmi", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rmi) + .value("VDBPSADBWZ128rmik", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rmik) + .value("VDBPSADBWZ128rmikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rmikz) + .value("VDBPSADBWZ128rri", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rri) + .value("VDBPSADBWZ128rrik", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rrik) + .value("VDBPSADBWZ128rrikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZ128rrikz) + .value("VDBPSADBWZ256rmi", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rmi) + .value("VDBPSADBWZ256rmik", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rmik) + .value("VDBPSADBWZ256rmikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rmikz) + .value("VDBPSADBWZ256rri", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rri) + .value("VDBPSADBWZ256rrik", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rrik) + .value("VDBPSADBWZ256rrikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZ256rrikz) + .value("VDBPSADBWZrmi", LIEF::assembly::x86::OPCODE::VDBPSADBWZrmi) + .value("VDBPSADBWZrmik", LIEF::assembly::x86::OPCODE::VDBPSADBWZrmik) + .value("VDBPSADBWZrmikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZrmikz) + .value("VDBPSADBWZrri", LIEF::assembly::x86::OPCODE::VDBPSADBWZrri) + .value("VDBPSADBWZrrik", LIEF::assembly::x86::OPCODE::VDBPSADBWZrrik) + .value("VDBPSADBWZrrikz", LIEF::assembly::x86::OPCODE::VDBPSADBWZrrikz) + .value("VDIVBF16Z128rm", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rm) + .value("VDIVBF16Z128rmb", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rmb) + .value("VDIVBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rmbk) + .value("VDIVBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rmbkz) + .value("VDIVBF16Z128rmk", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rmk) + .value("VDIVBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rmkz) + .value("VDIVBF16Z128rr", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rr) + .value("VDIVBF16Z128rrk", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rrk) + .value("VDIVBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z128rrkz) + .value("VDIVBF16Z256rm", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rm) + .value("VDIVBF16Z256rmb", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rmb) + .value("VDIVBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rmbk) + .value("VDIVBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rmbkz) + .value("VDIVBF16Z256rmk", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rmk) + .value("VDIVBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rmkz) + .value("VDIVBF16Z256rr", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rr) + .value("VDIVBF16Z256rrk", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rrk) + .value("VDIVBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VDIVBF16Z256rrkz) + .value("VDIVBF16Zrm", LIEF::assembly::x86::OPCODE::VDIVBF16Zrm) + .value("VDIVBF16Zrmb", LIEF::assembly::x86::OPCODE::VDIVBF16Zrmb) + .value("VDIVBF16Zrmbk", LIEF::assembly::x86::OPCODE::VDIVBF16Zrmbk) + .value("VDIVBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VDIVBF16Zrmbkz) + .value("VDIVBF16Zrmk", LIEF::assembly::x86::OPCODE::VDIVBF16Zrmk) + .value("VDIVBF16Zrmkz", LIEF::assembly::x86::OPCODE::VDIVBF16Zrmkz) + .value("VDIVBF16Zrr", LIEF::assembly::x86::OPCODE::VDIVBF16Zrr) + .value("VDIVBF16Zrrk", LIEF::assembly::x86::OPCODE::VDIVBF16Zrrk) + .value("VDIVBF16Zrrkz", LIEF::assembly::x86::OPCODE::VDIVBF16Zrrkz) + .value("VDIVPDYrm", LIEF::assembly::x86::OPCODE::VDIVPDYrm) + .value("VDIVPDYrr", LIEF::assembly::x86::OPCODE::VDIVPDYrr) + .value("VDIVPDZ128rm", LIEF::assembly::x86::OPCODE::VDIVPDZ128rm) + .value("VDIVPDZ128rmb", LIEF::assembly::x86::OPCODE::VDIVPDZ128rmb) + .value("VDIVPDZ128rmbk", LIEF::assembly::x86::OPCODE::VDIVPDZ128rmbk) + .value("VDIVPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VDIVPDZ128rmbkz) + .value("VDIVPDZ128rmk", LIEF::assembly::x86::OPCODE::VDIVPDZ128rmk) + .value("VDIVPDZ128rmkz", LIEF::assembly::x86::OPCODE::VDIVPDZ128rmkz) + .value("VDIVPDZ128rr", LIEF::assembly::x86::OPCODE::VDIVPDZ128rr) + .value("VDIVPDZ128rrk", LIEF::assembly::x86::OPCODE::VDIVPDZ128rrk) + .value("VDIVPDZ128rrkz", LIEF::assembly::x86::OPCODE::VDIVPDZ128rrkz) + .value("VDIVPDZ256rm", LIEF::assembly::x86::OPCODE::VDIVPDZ256rm) + .value("VDIVPDZ256rmb", LIEF::assembly::x86::OPCODE::VDIVPDZ256rmb) + .value("VDIVPDZ256rmbk", LIEF::assembly::x86::OPCODE::VDIVPDZ256rmbk) + .value("VDIVPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VDIVPDZ256rmbkz) + .value("VDIVPDZ256rmk", LIEF::assembly::x86::OPCODE::VDIVPDZ256rmk) + .value("VDIVPDZ256rmkz", LIEF::assembly::x86::OPCODE::VDIVPDZ256rmkz) + .value("VDIVPDZ256rr", LIEF::assembly::x86::OPCODE::VDIVPDZ256rr) + .value("VDIVPDZ256rrk", LIEF::assembly::x86::OPCODE::VDIVPDZ256rrk) + .value("VDIVPDZ256rrkz", LIEF::assembly::x86::OPCODE::VDIVPDZ256rrkz) + .value("VDIVPDZrm", LIEF::assembly::x86::OPCODE::VDIVPDZrm) + .value("VDIVPDZrmb", LIEF::assembly::x86::OPCODE::VDIVPDZrmb) + .value("VDIVPDZrmbk", LIEF::assembly::x86::OPCODE::VDIVPDZrmbk) + .value("VDIVPDZrmbkz", LIEF::assembly::x86::OPCODE::VDIVPDZrmbkz) + .value("VDIVPDZrmk", LIEF::assembly::x86::OPCODE::VDIVPDZrmk) + .value("VDIVPDZrmkz", LIEF::assembly::x86::OPCODE::VDIVPDZrmkz) + .value("VDIVPDZrr", LIEF::assembly::x86::OPCODE::VDIVPDZrr) + .value("VDIVPDZrrb", LIEF::assembly::x86::OPCODE::VDIVPDZrrb) + .value("VDIVPDZrrbk", LIEF::assembly::x86::OPCODE::VDIVPDZrrbk) + .value("VDIVPDZrrbkz", LIEF::assembly::x86::OPCODE::VDIVPDZrrbkz) + .value("VDIVPDZrrk", LIEF::assembly::x86::OPCODE::VDIVPDZrrk) + .value("VDIVPDZrrkz", LIEF::assembly::x86::OPCODE::VDIVPDZrrkz) + .value("VDIVPDrm", LIEF::assembly::x86::OPCODE::VDIVPDrm) + .value("VDIVPDrr", LIEF::assembly::x86::OPCODE::VDIVPDrr) + .value("VDIVPHZ128rm", LIEF::assembly::x86::OPCODE::VDIVPHZ128rm) + .value("VDIVPHZ128rmb", LIEF::assembly::x86::OPCODE::VDIVPHZ128rmb) + .value("VDIVPHZ128rmbk", LIEF::assembly::x86::OPCODE::VDIVPHZ128rmbk) + .value("VDIVPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VDIVPHZ128rmbkz) + .value("VDIVPHZ128rmk", LIEF::assembly::x86::OPCODE::VDIVPHZ128rmk) + .value("VDIVPHZ128rmkz", LIEF::assembly::x86::OPCODE::VDIVPHZ128rmkz) + .value("VDIVPHZ128rr", LIEF::assembly::x86::OPCODE::VDIVPHZ128rr) + .value("VDIVPHZ128rrk", LIEF::assembly::x86::OPCODE::VDIVPHZ128rrk) + .value("VDIVPHZ128rrkz", LIEF::assembly::x86::OPCODE::VDIVPHZ128rrkz) + .value("VDIVPHZ256rm", LIEF::assembly::x86::OPCODE::VDIVPHZ256rm) + .value("VDIVPHZ256rmb", LIEF::assembly::x86::OPCODE::VDIVPHZ256rmb) + .value("VDIVPHZ256rmbk", LIEF::assembly::x86::OPCODE::VDIVPHZ256rmbk) + .value("VDIVPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VDIVPHZ256rmbkz) + .value("VDIVPHZ256rmk", LIEF::assembly::x86::OPCODE::VDIVPHZ256rmk) + .value("VDIVPHZ256rmkz", LIEF::assembly::x86::OPCODE::VDIVPHZ256rmkz) + .value("VDIVPHZ256rr", LIEF::assembly::x86::OPCODE::VDIVPHZ256rr) + .value("VDIVPHZ256rrk", LIEF::assembly::x86::OPCODE::VDIVPHZ256rrk) + .value("VDIVPHZ256rrkz", LIEF::assembly::x86::OPCODE::VDIVPHZ256rrkz) + .value("VDIVPHZrm", LIEF::assembly::x86::OPCODE::VDIVPHZrm) + .value("VDIVPHZrmb", LIEF::assembly::x86::OPCODE::VDIVPHZrmb) + .value("VDIVPHZrmbk", LIEF::assembly::x86::OPCODE::VDIVPHZrmbk) + .value("VDIVPHZrmbkz", LIEF::assembly::x86::OPCODE::VDIVPHZrmbkz) + .value("VDIVPHZrmk", LIEF::assembly::x86::OPCODE::VDIVPHZrmk) + .value("VDIVPHZrmkz", LIEF::assembly::x86::OPCODE::VDIVPHZrmkz) + .value("VDIVPHZrr", LIEF::assembly::x86::OPCODE::VDIVPHZrr) + .value("VDIVPHZrrb", LIEF::assembly::x86::OPCODE::VDIVPHZrrb) + .value("VDIVPHZrrbk", LIEF::assembly::x86::OPCODE::VDIVPHZrrbk) + .value("VDIVPHZrrbkz", LIEF::assembly::x86::OPCODE::VDIVPHZrrbkz) + .value("VDIVPHZrrk", LIEF::assembly::x86::OPCODE::VDIVPHZrrk) + .value("VDIVPHZrrkz", LIEF::assembly::x86::OPCODE::VDIVPHZrrkz) + .value("VDIVPSYrm", LIEF::assembly::x86::OPCODE::VDIVPSYrm) + .value("VDIVPSYrr", LIEF::assembly::x86::OPCODE::VDIVPSYrr) + .value("VDIVPSZ128rm", LIEF::assembly::x86::OPCODE::VDIVPSZ128rm) + .value("VDIVPSZ128rmb", LIEF::assembly::x86::OPCODE::VDIVPSZ128rmb) + .value("VDIVPSZ128rmbk", LIEF::assembly::x86::OPCODE::VDIVPSZ128rmbk) + .value("VDIVPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VDIVPSZ128rmbkz) + .value("VDIVPSZ128rmk", LIEF::assembly::x86::OPCODE::VDIVPSZ128rmk) + .value("VDIVPSZ128rmkz", LIEF::assembly::x86::OPCODE::VDIVPSZ128rmkz) + .value("VDIVPSZ128rr", LIEF::assembly::x86::OPCODE::VDIVPSZ128rr) + .value("VDIVPSZ128rrk", LIEF::assembly::x86::OPCODE::VDIVPSZ128rrk) + .value("VDIVPSZ128rrkz", LIEF::assembly::x86::OPCODE::VDIVPSZ128rrkz) + .value("VDIVPSZ256rm", LIEF::assembly::x86::OPCODE::VDIVPSZ256rm) + .value("VDIVPSZ256rmb", LIEF::assembly::x86::OPCODE::VDIVPSZ256rmb) + .value("VDIVPSZ256rmbk", LIEF::assembly::x86::OPCODE::VDIVPSZ256rmbk) + .value("VDIVPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VDIVPSZ256rmbkz) + .value("VDIVPSZ256rmk", LIEF::assembly::x86::OPCODE::VDIVPSZ256rmk) + .value("VDIVPSZ256rmkz", LIEF::assembly::x86::OPCODE::VDIVPSZ256rmkz) + .value("VDIVPSZ256rr", LIEF::assembly::x86::OPCODE::VDIVPSZ256rr) + .value("VDIVPSZ256rrk", LIEF::assembly::x86::OPCODE::VDIVPSZ256rrk) + .value("VDIVPSZ256rrkz", LIEF::assembly::x86::OPCODE::VDIVPSZ256rrkz) + .value("VDIVPSZrm", LIEF::assembly::x86::OPCODE::VDIVPSZrm) + .value("VDIVPSZrmb", LIEF::assembly::x86::OPCODE::VDIVPSZrmb) + .value("VDIVPSZrmbk", LIEF::assembly::x86::OPCODE::VDIVPSZrmbk) + .value("VDIVPSZrmbkz", LIEF::assembly::x86::OPCODE::VDIVPSZrmbkz) + .value("VDIVPSZrmk", LIEF::assembly::x86::OPCODE::VDIVPSZrmk) + .value("VDIVPSZrmkz", LIEF::assembly::x86::OPCODE::VDIVPSZrmkz) + .value("VDIVPSZrr", LIEF::assembly::x86::OPCODE::VDIVPSZrr) + .value("VDIVPSZrrb", LIEF::assembly::x86::OPCODE::VDIVPSZrrb) + .value("VDIVPSZrrbk", LIEF::assembly::x86::OPCODE::VDIVPSZrrbk) + .value("VDIVPSZrrbkz", LIEF::assembly::x86::OPCODE::VDIVPSZrrbkz) + .value("VDIVPSZrrk", LIEF::assembly::x86::OPCODE::VDIVPSZrrk) + .value("VDIVPSZrrkz", LIEF::assembly::x86::OPCODE::VDIVPSZrrkz) + .value("VDIVPSrm", LIEF::assembly::x86::OPCODE::VDIVPSrm) + .value("VDIVPSrr", LIEF::assembly::x86::OPCODE::VDIVPSrr) + .value("VDIVSDZrm", LIEF::assembly::x86::OPCODE::VDIVSDZrm) + .value("VDIVSDZrm_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrm_Int) + .value("VDIVSDZrmk_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrmk_Int) + .value("VDIVSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrmkz_Int) + .value("VDIVSDZrr", LIEF::assembly::x86::OPCODE::VDIVSDZrr) + .value("VDIVSDZrr_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrr_Int) + .value("VDIVSDZrrb_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrrb_Int) + .value("VDIVSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrrbk_Int) + .value("VDIVSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrrbkz_Int) + .value("VDIVSDZrrk_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrrk_Int) + .value("VDIVSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VDIVSDZrrkz_Int) + .value("VDIVSDrm", LIEF::assembly::x86::OPCODE::VDIVSDrm) + .value("VDIVSDrm_Int", LIEF::assembly::x86::OPCODE::VDIVSDrm_Int) + .value("VDIVSDrr", LIEF::assembly::x86::OPCODE::VDIVSDrr) + .value("VDIVSDrr_Int", LIEF::assembly::x86::OPCODE::VDIVSDrr_Int) + .value("VDIVSHZrm", LIEF::assembly::x86::OPCODE::VDIVSHZrm) + .value("VDIVSHZrm_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrm_Int) + .value("VDIVSHZrmk_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrmk_Int) + .value("VDIVSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrmkz_Int) + .value("VDIVSHZrr", LIEF::assembly::x86::OPCODE::VDIVSHZrr) + .value("VDIVSHZrr_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrr_Int) + .value("VDIVSHZrrb_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrrb_Int) + .value("VDIVSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrrbk_Int) + .value("VDIVSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrrbkz_Int) + .value("VDIVSHZrrk_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrrk_Int) + .value("VDIVSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VDIVSHZrrkz_Int) + .value("VDIVSSZrm", LIEF::assembly::x86::OPCODE::VDIVSSZrm) + .value("VDIVSSZrm_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrm_Int) + .value("VDIVSSZrmk_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrmk_Int) + .value("VDIVSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrmkz_Int) + .value("VDIVSSZrr", LIEF::assembly::x86::OPCODE::VDIVSSZrr) + .value("VDIVSSZrr_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrr_Int) + .value("VDIVSSZrrb_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrrb_Int) + .value("VDIVSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrrbk_Int) + .value("VDIVSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrrbkz_Int) + .value("VDIVSSZrrk_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrrk_Int) + .value("VDIVSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VDIVSSZrrkz_Int) + .value("VDIVSSrm", LIEF::assembly::x86::OPCODE::VDIVSSrm) + .value("VDIVSSrm_Int", LIEF::assembly::x86::OPCODE::VDIVSSrm_Int) + .value("VDIVSSrr", LIEF::assembly::x86::OPCODE::VDIVSSrr) + .value("VDIVSSrr_Int", LIEF::assembly::x86::OPCODE::VDIVSSrr_Int) + .value("VDPBF16PSZ128m", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128m) + .value("VDPBF16PSZ128mb", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128mb) + .value("VDPBF16PSZ128mbk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128mbk) + .value("VDPBF16PSZ128mbkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128mbkz) + .value("VDPBF16PSZ128mk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128mk) + .value("VDPBF16PSZ128mkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128mkz) + .value("VDPBF16PSZ128r", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128r) + .value("VDPBF16PSZ128rk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128rk) + .value("VDPBF16PSZ128rkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ128rkz) + .value("VDPBF16PSZ256m", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256m) + .value("VDPBF16PSZ256mb", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256mb) + .value("VDPBF16PSZ256mbk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256mbk) + .value("VDPBF16PSZ256mbkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256mbkz) + .value("VDPBF16PSZ256mk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256mk) + .value("VDPBF16PSZ256mkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256mkz) + .value("VDPBF16PSZ256r", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256r) + .value("VDPBF16PSZ256rk", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256rk) + .value("VDPBF16PSZ256rkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZ256rkz) + .value("VDPBF16PSZm", LIEF::assembly::x86::OPCODE::VDPBF16PSZm) + .value("VDPBF16PSZmb", LIEF::assembly::x86::OPCODE::VDPBF16PSZmb) + .value("VDPBF16PSZmbk", LIEF::assembly::x86::OPCODE::VDPBF16PSZmbk) + .value("VDPBF16PSZmbkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZmbkz) + .value("VDPBF16PSZmk", LIEF::assembly::x86::OPCODE::VDPBF16PSZmk) + .value("VDPBF16PSZmkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZmkz) + .value("VDPBF16PSZr", LIEF::assembly::x86::OPCODE::VDPBF16PSZr) + .value("VDPBF16PSZrk", LIEF::assembly::x86::OPCODE::VDPBF16PSZrk) + .value("VDPBF16PSZrkz", LIEF::assembly::x86::OPCODE::VDPBF16PSZrkz) + .value("VDPPDrmi", LIEF::assembly::x86::OPCODE::VDPPDrmi) + .value("VDPPDrri", LIEF::assembly::x86::OPCODE::VDPPDrri) + .value("VDPPHPSZ128m", LIEF::assembly::x86::OPCODE::VDPPHPSZ128m) + .value("VDPPHPSZ128mb", LIEF::assembly::x86::OPCODE::VDPPHPSZ128mb) + .value("VDPPHPSZ128mbk", LIEF::assembly::x86::OPCODE::VDPPHPSZ128mbk) + .value("VDPPHPSZ128mbkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ128mbkz) + .value("VDPPHPSZ128mk", LIEF::assembly::x86::OPCODE::VDPPHPSZ128mk) + .value("VDPPHPSZ128mkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ128mkz) + .value("VDPPHPSZ128r", LIEF::assembly::x86::OPCODE::VDPPHPSZ128r) + .value("VDPPHPSZ128rk", LIEF::assembly::x86::OPCODE::VDPPHPSZ128rk) + .value("VDPPHPSZ128rkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ128rkz) + .value("VDPPHPSZ256m", LIEF::assembly::x86::OPCODE::VDPPHPSZ256m) + .value("VDPPHPSZ256mb", LIEF::assembly::x86::OPCODE::VDPPHPSZ256mb) + .value("VDPPHPSZ256mbk", LIEF::assembly::x86::OPCODE::VDPPHPSZ256mbk) + .value("VDPPHPSZ256mbkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ256mbkz) + .value("VDPPHPSZ256mk", LIEF::assembly::x86::OPCODE::VDPPHPSZ256mk) + .value("VDPPHPSZ256mkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ256mkz) + .value("VDPPHPSZ256r", LIEF::assembly::x86::OPCODE::VDPPHPSZ256r) + .value("VDPPHPSZ256rk", LIEF::assembly::x86::OPCODE::VDPPHPSZ256rk) + .value("VDPPHPSZ256rkz", LIEF::assembly::x86::OPCODE::VDPPHPSZ256rkz) + .value("VDPPHPSZm", LIEF::assembly::x86::OPCODE::VDPPHPSZm) + .value("VDPPHPSZmb", LIEF::assembly::x86::OPCODE::VDPPHPSZmb) + .value("VDPPHPSZmbk", LIEF::assembly::x86::OPCODE::VDPPHPSZmbk) + .value("VDPPHPSZmbkz", LIEF::assembly::x86::OPCODE::VDPPHPSZmbkz) + .value("VDPPHPSZmk", LIEF::assembly::x86::OPCODE::VDPPHPSZmk) + .value("VDPPHPSZmkz", LIEF::assembly::x86::OPCODE::VDPPHPSZmkz) + .value("VDPPHPSZr", LIEF::assembly::x86::OPCODE::VDPPHPSZr) + .value("VDPPHPSZrk", LIEF::assembly::x86::OPCODE::VDPPHPSZrk); + opcodes.value("VDPPHPSZrkz", LIEF::assembly::x86::OPCODE::VDPPHPSZrkz) + .value("VDPPSYrmi", LIEF::assembly::x86::OPCODE::VDPPSYrmi) + .value("VDPPSYrri", LIEF::assembly::x86::OPCODE::VDPPSYrri) + .value("VDPPSrmi", LIEF::assembly::x86::OPCODE::VDPPSrmi) + .value("VDPPSrri", LIEF::assembly::x86::OPCODE::VDPPSrri) + .value("VERRm", LIEF::assembly::x86::OPCODE::VERRm) + .value("VERRr", LIEF::assembly::x86::OPCODE::VERRr) + .value("VERWm", LIEF::assembly::x86::OPCODE::VERWm) + .value("VERWr", LIEF::assembly::x86::OPCODE::VERWr) + .value("VEXP2PDZm", LIEF::assembly::x86::OPCODE::VEXP2PDZm) + .value("VEXP2PDZmb", LIEF::assembly::x86::OPCODE::VEXP2PDZmb) + .value("VEXP2PDZmbk", LIEF::assembly::x86::OPCODE::VEXP2PDZmbk) + .value("VEXP2PDZmbkz", LIEF::assembly::x86::OPCODE::VEXP2PDZmbkz) + .value("VEXP2PDZmk", LIEF::assembly::x86::OPCODE::VEXP2PDZmk) + .value("VEXP2PDZmkz", LIEF::assembly::x86::OPCODE::VEXP2PDZmkz) + .value("VEXP2PDZr", LIEF::assembly::x86::OPCODE::VEXP2PDZr) + .value("VEXP2PDZrb", LIEF::assembly::x86::OPCODE::VEXP2PDZrb) + .value("VEXP2PDZrbk", LIEF::assembly::x86::OPCODE::VEXP2PDZrbk) + .value("VEXP2PDZrbkz", LIEF::assembly::x86::OPCODE::VEXP2PDZrbkz) + .value("VEXP2PDZrk", LIEF::assembly::x86::OPCODE::VEXP2PDZrk) + .value("VEXP2PDZrkz", LIEF::assembly::x86::OPCODE::VEXP2PDZrkz) + .value("VEXP2PSZm", LIEF::assembly::x86::OPCODE::VEXP2PSZm) + .value("VEXP2PSZmb", LIEF::assembly::x86::OPCODE::VEXP2PSZmb) + .value("VEXP2PSZmbk", LIEF::assembly::x86::OPCODE::VEXP2PSZmbk) + .value("VEXP2PSZmbkz", LIEF::assembly::x86::OPCODE::VEXP2PSZmbkz) + .value("VEXP2PSZmk", LIEF::assembly::x86::OPCODE::VEXP2PSZmk) + .value("VEXP2PSZmkz", LIEF::assembly::x86::OPCODE::VEXP2PSZmkz) + .value("VEXP2PSZr", LIEF::assembly::x86::OPCODE::VEXP2PSZr) + .value("VEXP2PSZrb", LIEF::assembly::x86::OPCODE::VEXP2PSZrb) + .value("VEXP2PSZrbk", LIEF::assembly::x86::OPCODE::VEXP2PSZrbk) + .value("VEXP2PSZrbkz", LIEF::assembly::x86::OPCODE::VEXP2PSZrbkz) + .value("VEXP2PSZrk", LIEF::assembly::x86::OPCODE::VEXP2PSZrk) + .value("VEXP2PSZrkz", LIEF::assembly::x86::OPCODE::VEXP2PSZrkz) + .value("VEXPANDPDZ128rm", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rm) + .value("VEXPANDPDZ128rmk", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rmk) + .value("VEXPANDPDZ128rmkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rmkz) + .value("VEXPANDPDZ128rr", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rr) + .value("VEXPANDPDZ128rrk", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rrk) + .value("VEXPANDPDZ128rrkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZ128rrkz) + .value("VEXPANDPDZ256rm", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rm) + .value("VEXPANDPDZ256rmk", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rmk) + .value("VEXPANDPDZ256rmkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rmkz) + .value("VEXPANDPDZ256rr", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rr) + .value("VEXPANDPDZ256rrk", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rrk) + .value("VEXPANDPDZ256rrkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZ256rrkz) + .value("VEXPANDPDZrm", LIEF::assembly::x86::OPCODE::VEXPANDPDZrm) + .value("VEXPANDPDZrmk", LIEF::assembly::x86::OPCODE::VEXPANDPDZrmk) + .value("VEXPANDPDZrmkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZrmkz) + .value("VEXPANDPDZrr", LIEF::assembly::x86::OPCODE::VEXPANDPDZrr) + .value("VEXPANDPDZrrk", LIEF::assembly::x86::OPCODE::VEXPANDPDZrrk) + .value("VEXPANDPDZrrkz", LIEF::assembly::x86::OPCODE::VEXPANDPDZrrkz) + .value("VEXPANDPSZ128rm", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rm) + .value("VEXPANDPSZ128rmk", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rmk) + .value("VEXPANDPSZ128rmkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rmkz) + .value("VEXPANDPSZ128rr", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rr) + .value("VEXPANDPSZ128rrk", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rrk) + .value("VEXPANDPSZ128rrkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZ128rrkz) + .value("VEXPANDPSZ256rm", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rm) + .value("VEXPANDPSZ256rmk", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rmk) + .value("VEXPANDPSZ256rmkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rmkz) + .value("VEXPANDPSZ256rr", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rr) + .value("VEXPANDPSZ256rrk", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rrk) + .value("VEXPANDPSZ256rrkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZ256rrkz) + .value("VEXPANDPSZrm", LIEF::assembly::x86::OPCODE::VEXPANDPSZrm) + .value("VEXPANDPSZrmk", LIEF::assembly::x86::OPCODE::VEXPANDPSZrmk) + .value("VEXPANDPSZrmkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZrmkz) + .value("VEXPANDPSZrr", LIEF::assembly::x86::OPCODE::VEXPANDPSZrr) + .value("VEXPANDPSZrrk", LIEF::assembly::x86::OPCODE::VEXPANDPSZrrk) + .value("VEXPANDPSZrrkz", LIEF::assembly::x86::OPCODE::VEXPANDPSZrrkz) + .value("VEXTRACTF128mri", LIEF::assembly::x86::OPCODE::VEXTRACTF128mri) + .value("VEXTRACTF128rri", LIEF::assembly::x86::OPCODE::VEXTRACTF128rri) + .value("VEXTRACTF32X4Z256mri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Z256mri) + .value("VEXTRACTF32X4Z256mrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Z256mrik) + .value("VEXTRACTF32X4Z256rri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Z256rri) + .value("VEXTRACTF32X4Z256rrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Z256rrik) + .value("VEXTRACTF32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Z256rrikz) + .value("VEXTRACTF32X4Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Zmri) + .value("VEXTRACTF32X4Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Zmrik) + .value("VEXTRACTF32X4Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Zrri) + .value("VEXTRACTF32X4Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Zrrik) + .value("VEXTRACTF32X4Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF32X4Zrrikz) + .value("VEXTRACTF32X8Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X8Zmri) + .value("VEXTRACTF32X8Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X8Zmrik) + .value("VEXTRACTF32X8Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTF32X8Zrri) + .value("VEXTRACTF32X8Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTF32X8Zrrik) + .value("VEXTRACTF32X8Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF32X8Zrrikz) + .value("VEXTRACTF64X2Z256mri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Z256mri) + .value("VEXTRACTF64X2Z256mrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Z256mrik) + .value("VEXTRACTF64X2Z256rri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Z256rri) + .value("VEXTRACTF64X2Z256rrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Z256rrik) + .value("VEXTRACTF64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Z256rrikz) + .value("VEXTRACTF64X2Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Zmri) + .value("VEXTRACTF64X2Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Zmrik) + .value("VEXTRACTF64X2Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Zrri) + .value("VEXTRACTF64X2Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Zrrik) + .value("VEXTRACTF64X2Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF64X2Zrrikz) + .value("VEXTRACTF64X4Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X4Zmri) + .value("VEXTRACTF64X4Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X4Zmrik) + .value("VEXTRACTF64X4Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTF64X4Zrri) + .value("VEXTRACTF64X4Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTF64X4Zrrik) + .value("VEXTRACTF64X4Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTF64X4Zrrikz) + .value("VEXTRACTI128mri", LIEF::assembly::x86::OPCODE::VEXTRACTI128mri) + .value("VEXTRACTI128rri", LIEF::assembly::x86::OPCODE::VEXTRACTI128rri) + .value("VEXTRACTI32X4Z256mri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Z256mri) + .value("VEXTRACTI32X4Z256mrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Z256mrik) + .value("VEXTRACTI32X4Z256rri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Z256rri) + .value("VEXTRACTI32X4Z256rrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Z256rrik) + .value("VEXTRACTI32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Z256rrikz) + .value("VEXTRACTI32X4Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Zmri) + .value("VEXTRACTI32X4Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Zmrik) + .value("VEXTRACTI32X4Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Zrri) + .value("VEXTRACTI32X4Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Zrrik) + .value("VEXTRACTI32X4Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI32X4Zrrikz) + .value("VEXTRACTI32X8Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X8Zmri) + .value("VEXTRACTI32X8Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X8Zmrik) + .value("VEXTRACTI32X8Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTI32X8Zrri) + .value("VEXTRACTI32X8Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTI32X8Zrrik) + .value("VEXTRACTI32X8Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI32X8Zrrikz) + .value("VEXTRACTI64X2Z256mri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Z256mri) + .value("VEXTRACTI64X2Z256mrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Z256mrik) + .value("VEXTRACTI64X2Z256rri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Z256rri) + .value("VEXTRACTI64X2Z256rrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Z256rrik) + .value("VEXTRACTI64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Z256rrikz) + .value("VEXTRACTI64X2Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Zmri) + .value("VEXTRACTI64X2Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Zmrik) + .value("VEXTRACTI64X2Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Zrri) + .value("VEXTRACTI64X2Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Zrrik) + .value("VEXTRACTI64X2Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI64X2Zrrikz) + .value("VEXTRACTI64X4Zmri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X4Zmri) + .value("VEXTRACTI64X4Zmrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X4Zmrik) + .value("VEXTRACTI64X4Zrri", LIEF::assembly::x86::OPCODE::VEXTRACTI64X4Zrri) + .value("VEXTRACTI64X4Zrrik", LIEF::assembly::x86::OPCODE::VEXTRACTI64X4Zrrik) + .value("VEXTRACTI64X4Zrrikz", LIEF::assembly::x86::OPCODE::VEXTRACTI64X4Zrrikz) + .value("VEXTRACTPSZmri", LIEF::assembly::x86::OPCODE::VEXTRACTPSZmri) + .value("VEXTRACTPSZrri", LIEF::assembly::x86::OPCODE::VEXTRACTPSZrri) + .value("VEXTRACTPSmri", LIEF::assembly::x86::OPCODE::VEXTRACTPSmri) + .value("VEXTRACTPSrri", LIEF::assembly::x86::OPCODE::VEXTRACTPSrri) + .value("VFCMADDCPHZ128m", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128m) + .value("VFCMADDCPHZ128mb", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128mb) + .value("VFCMADDCPHZ128mbk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128mbk) + .value("VFCMADDCPHZ128mbkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128mbkz) + .value("VFCMADDCPHZ128mk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128mk) + .value("VFCMADDCPHZ128mkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128mkz) + .value("VFCMADDCPHZ128r", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128r) + .value("VFCMADDCPHZ128rk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128rk) + .value("VFCMADDCPHZ128rkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ128rkz) + .value("VFCMADDCPHZ256m", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256m) + .value("VFCMADDCPHZ256mb", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256mb) + .value("VFCMADDCPHZ256mbk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256mbk) + .value("VFCMADDCPHZ256mbkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256mbkz) + .value("VFCMADDCPHZ256mk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256mk) + .value("VFCMADDCPHZ256mkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256mkz) + .value("VFCMADDCPHZ256r", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256r) + .value("VFCMADDCPHZ256rk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256rk) + .value("VFCMADDCPHZ256rkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZ256rkz) + .value("VFCMADDCPHZm", LIEF::assembly::x86::OPCODE::VFCMADDCPHZm) + .value("VFCMADDCPHZmb", LIEF::assembly::x86::OPCODE::VFCMADDCPHZmb) + .value("VFCMADDCPHZmbk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZmbk) + .value("VFCMADDCPHZmbkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZmbkz) + .value("VFCMADDCPHZmk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZmk) + .value("VFCMADDCPHZmkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZmkz) + .value("VFCMADDCPHZr", LIEF::assembly::x86::OPCODE::VFCMADDCPHZr) + .value("VFCMADDCPHZrb", LIEF::assembly::x86::OPCODE::VFCMADDCPHZrb) + .value("VFCMADDCPHZrbk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZrbk) + .value("VFCMADDCPHZrbkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZrbkz) + .value("VFCMADDCPHZrk", LIEF::assembly::x86::OPCODE::VFCMADDCPHZrk) + .value("VFCMADDCPHZrkz", LIEF::assembly::x86::OPCODE::VFCMADDCPHZrkz) + .value("VFCMADDCSHZm", LIEF::assembly::x86::OPCODE::VFCMADDCSHZm) + .value("VFCMADDCSHZmk", LIEF::assembly::x86::OPCODE::VFCMADDCSHZmk) + .value("VFCMADDCSHZmkz", LIEF::assembly::x86::OPCODE::VFCMADDCSHZmkz) + .value("VFCMADDCSHZr", LIEF::assembly::x86::OPCODE::VFCMADDCSHZr) + .value("VFCMADDCSHZrb", LIEF::assembly::x86::OPCODE::VFCMADDCSHZrb) + .value("VFCMADDCSHZrbk", LIEF::assembly::x86::OPCODE::VFCMADDCSHZrbk) + .value("VFCMADDCSHZrbkz", LIEF::assembly::x86::OPCODE::VFCMADDCSHZrbkz) + .value("VFCMADDCSHZrk", LIEF::assembly::x86::OPCODE::VFCMADDCSHZrk) + .value("VFCMADDCSHZrkz", LIEF::assembly::x86::OPCODE::VFCMADDCSHZrkz) + .value("VFCMULCPHZ128rm", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rm) + .value("VFCMULCPHZ128rmb", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rmb) + .value("VFCMULCPHZ128rmbk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rmbk) + .value("VFCMULCPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rmbkz) + .value("VFCMULCPHZ128rmk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rmk) + .value("VFCMULCPHZ128rmkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rmkz) + .value("VFCMULCPHZ128rr", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rr) + .value("VFCMULCPHZ128rrk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rrk) + .value("VFCMULCPHZ128rrkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ128rrkz) + .value("VFCMULCPHZ256rm", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rm) + .value("VFCMULCPHZ256rmb", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rmb) + .value("VFCMULCPHZ256rmbk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rmbk) + .value("VFCMULCPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rmbkz) + .value("VFCMULCPHZ256rmk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rmk) + .value("VFCMULCPHZ256rmkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rmkz) + .value("VFCMULCPHZ256rr", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rr) + .value("VFCMULCPHZ256rrk", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rrk) + .value("VFCMULCPHZ256rrkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZ256rrkz) + .value("VFCMULCPHZrm", LIEF::assembly::x86::OPCODE::VFCMULCPHZrm) + .value("VFCMULCPHZrmb", LIEF::assembly::x86::OPCODE::VFCMULCPHZrmb) + .value("VFCMULCPHZrmbk", LIEF::assembly::x86::OPCODE::VFCMULCPHZrmbk) + .value("VFCMULCPHZrmbkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZrmbkz) + .value("VFCMULCPHZrmk", LIEF::assembly::x86::OPCODE::VFCMULCPHZrmk) + .value("VFCMULCPHZrmkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZrmkz) + .value("VFCMULCPHZrr", LIEF::assembly::x86::OPCODE::VFCMULCPHZrr) + .value("VFCMULCPHZrrb", LIEF::assembly::x86::OPCODE::VFCMULCPHZrrb) + .value("VFCMULCPHZrrbk", LIEF::assembly::x86::OPCODE::VFCMULCPHZrrbk) + .value("VFCMULCPHZrrbkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZrrbkz) + .value("VFCMULCPHZrrk", LIEF::assembly::x86::OPCODE::VFCMULCPHZrrk) + .value("VFCMULCPHZrrkz", LIEF::assembly::x86::OPCODE::VFCMULCPHZrrkz) + .value("VFCMULCSHZrm", LIEF::assembly::x86::OPCODE::VFCMULCSHZrm) + .value("VFCMULCSHZrmk", LIEF::assembly::x86::OPCODE::VFCMULCSHZrmk) + .value("VFCMULCSHZrmkz", LIEF::assembly::x86::OPCODE::VFCMULCSHZrmkz) + .value("VFCMULCSHZrr", LIEF::assembly::x86::OPCODE::VFCMULCSHZrr) + .value("VFCMULCSHZrrb", LIEF::assembly::x86::OPCODE::VFCMULCSHZrrb) + .value("VFCMULCSHZrrbk", LIEF::assembly::x86::OPCODE::VFCMULCSHZrrbk) + .value("VFCMULCSHZrrbkz", LIEF::assembly::x86::OPCODE::VFCMULCSHZrrbkz) + .value("VFCMULCSHZrrk", LIEF::assembly::x86::OPCODE::VFCMULCSHZrrk) + .value("VFCMULCSHZrrkz", LIEF::assembly::x86::OPCODE::VFCMULCSHZrrkz) + .value("VFIXUPIMMPDZ128rmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmbi) + .value("VFIXUPIMMPDZ128rmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmbik) + .value("VFIXUPIMMPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmbikz) + .value("VFIXUPIMMPDZ128rmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmi) + .value("VFIXUPIMMPDZ128rmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmik) + .value("VFIXUPIMMPDZ128rmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rmikz) + .value("VFIXUPIMMPDZ128rri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rri) + .value("VFIXUPIMMPDZ128rrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rrik) + .value("VFIXUPIMMPDZ128rrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ128rrikz) + .value("VFIXUPIMMPDZ256rmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmbi) + .value("VFIXUPIMMPDZ256rmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmbik) + .value("VFIXUPIMMPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmbikz) + .value("VFIXUPIMMPDZ256rmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmi) + .value("VFIXUPIMMPDZ256rmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmik) + .value("VFIXUPIMMPDZ256rmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rmikz) + .value("VFIXUPIMMPDZ256rri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rri) + .value("VFIXUPIMMPDZ256rrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rrik) + .value("VFIXUPIMMPDZ256rrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZ256rrikz) + .value("VFIXUPIMMPDZrmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmbi) + .value("VFIXUPIMMPDZrmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmbik) + .value("VFIXUPIMMPDZrmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmbikz) + .value("VFIXUPIMMPDZrmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmi) + .value("VFIXUPIMMPDZrmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmik) + .value("VFIXUPIMMPDZrmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrmikz) + .value("VFIXUPIMMPDZrri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrri) + .value("VFIXUPIMMPDZrrib", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrrib) + .value("VFIXUPIMMPDZrribk", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrribk) + .value("VFIXUPIMMPDZrribkz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrribkz) + .value("VFIXUPIMMPDZrrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrrik) + .value("VFIXUPIMMPDZrrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPDZrrikz) + .value("VFIXUPIMMPSZ128rmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmbi) + .value("VFIXUPIMMPSZ128rmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmbik) + .value("VFIXUPIMMPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmbikz) + .value("VFIXUPIMMPSZ128rmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmi) + .value("VFIXUPIMMPSZ128rmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmik) + .value("VFIXUPIMMPSZ128rmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rmikz) + .value("VFIXUPIMMPSZ128rri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rri) + .value("VFIXUPIMMPSZ128rrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rrik) + .value("VFIXUPIMMPSZ128rrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ128rrikz) + .value("VFIXUPIMMPSZ256rmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmbi) + .value("VFIXUPIMMPSZ256rmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmbik) + .value("VFIXUPIMMPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmbikz) + .value("VFIXUPIMMPSZ256rmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmi) + .value("VFIXUPIMMPSZ256rmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmik) + .value("VFIXUPIMMPSZ256rmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rmikz) + .value("VFIXUPIMMPSZ256rri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rri) + .value("VFIXUPIMMPSZ256rrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rrik) + .value("VFIXUPIMMPSZ256rrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZ256rrikz) + .value("VFIXUPIMMPSZrmbi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmbi) + .value("VFIXUPIMMPSZrmbik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmbik) + .value("VFIXUPIMMPSZrmbikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmbikz) + .value("VFIXUPIMMPSZrmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmi) + .value("VFIXUPIMMPSZrmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmik) + .value("VFIXUPIMMPSZrmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrmikz) + .value("VFIXUPIMMPSZrri", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrri) + .value("VFIXUPIMMPSZrrib", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrrib) + .value("VFIXUPIMMPSZrribk", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrribk) + .value("VFIXUPIMMPSZrribkz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrribkz) + .value("VFIXUPIMMPSZrrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrrik) + .value("VFIXUPIMMPSZrrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMPSZrrikz) + .value("VFIXUPIMMSDZrmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrmi) + .value("VFIXUPIMMSDZrmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrmik) + .value("VFIXUPIMMSDZrmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrmikz) + .value("VFIXUPIMMSDZrri", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrri) + .value("VFIXUPIMMSDZrrib", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrrib) + .value("VFIXUPIMMSDZrribk", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrribk) + .value("VFIXUPIMMSDZrribkz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrribkz) + .value("VFIXUPIMMSDZrrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrrik) + .value("VFIXUPIMMSDZrrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSDZrrikz) + .value("VFIXUPIMMSSZrmi", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrmi) + .value("VFIXUPIMMSSZrmik", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrmik) + .value("VFIXUPIMMSSZrmikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrmikz) + .value("VFIXUPIMMSSZrri", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrri) + .value("VFIXUPIMMSSZrrib", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrrib) + .value("VFIXUPIMMSSZrribk", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrribk) + .value("VFIXUPIMMSSZrribkz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrribkz) + .value("VFIXUPIMMSSZrrik", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrrik) + .value("VFIXUPIMMSSZrrikz", LIEF::assembly::x86::OPCODE::VFIXUPIMMSSZrrikz) + .value("VFMADD132BF16Z128m", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128m) + .value("VFMADD132BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128mb) + .value("VFMADD132BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128mbk) + .value("VFMADD132BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128mbkz) + .value("VFMADD132BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128mk) + .value("VFMADD132BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128mkz) + .value("VFMADD132BF16Z128r", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128r); + opcodes.value("VFMADD132BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128rk) + .value("VFMADD132BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z128rkz) + .value("VFMADD132BF16Z256m", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256m) + .value("VFMADD132BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256mb) + .value("VFMADD132BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256mbk) + .value("VFMADD132BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256mbkz) + .value("VFMADD132BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256mk) + .value("VFMADD132BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256mkz) + .value("VFMADD132BF16Z256r", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256r) + .value("VFMADD132BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256rk) + .value("VFMADD132BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Z256rkz) + .value("VFMADD132BF16Zm", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zm) + .value("VFMADD132BF16Zmb", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zmb) + .value("VFMADD132BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zmbk) + .value("VFMADD132BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zmbkz) + .value("VFMADD132BF16Zmk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zmk) + .value("VFMADD132BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zmkz) + .value("VFMADD132BF16Zr", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zr) + .value("VFMADD132BF16Zrk", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zrk) + .value("VFMADD132BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMADD132BF16Zrkz) + .value("VFMADD132PDYm", LIEF::assembly::x86::OPCODE::VFMADD132PDYm) + .value("VFMADD132PDYr", LIEF::assembly::x86::OPCODE::VFMADD132PDYr) + .value("VFMADD132PDZ128m", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128m) + .value("VFMADD132PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128mb) + .value("VFMADD132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128mbk) + .value("VFMADD132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128mbkz) + .value("VFMADD132PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128mk) + .value("VFMADD132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128mkz) + .value("VFMADD132PDZ128r", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128r) + .value("VFMADD132PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128rk) + .value("VFMADD132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ128rkz) + .value("VFMADD132PDZ256m", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256m) + .value("VFMADD132PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256mb) + .value("VFMADD132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256mbk) + .value("VFMADD132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256mbkz) + .value("VFMADD132PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256mk) + .value("VFMADD132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256mkz) + .value("VFMADD132PDZ256r", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256r) + .value("VFMADD132PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256rk) + .value("VFMADD132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZ256rkz) + .value("VFMADD132PDZm", LIEF::assembly::x86::OPCODE::VFMADD132PDZm) + .value("VFMADD132PDZmb", LIEF::assembly::x86::OPCODE::VFMADD132PDZmb) + .value("VFMADD132PDZmbk", LIEF::assembly::x86::OPCODE::VFMADD132PDZmbk) + .value("VFMADD132PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZmbkz) + .value("VFMADD132PDZmk", LIEF::assembly::x86::OPCODE::VFMADD132PDZmk) + .value("VFMADD132PDZmkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZmkz) + .value("VFMADD132PDZr", LIEF::assembly::x86::OPCODE::VFMADD132PDZr) + .value("VFMADD132PDZrb", LIEF::assembly::x86::OPCODE::VFMADD132PDZrb) + .value("VFMADD132PDZrbk", LIEF::assembly::x86::OPCODE::VFMADD132PDZrbk) + .value("VFMADD132PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZrbkz) + .value("VFMADD132PDZrk", LIEF::assembly::x86::OPCODE::VFMADD132PDZrk) + .value("VFMADD132PDZrkz", LIEF::assembly::x86::OPCODE::VFMADD132PDZrkz) + .value("VFMADD132PDm", LIEF::assembly::x86::OPCODE::VFMADD132PDm) + .value("VFMADD132PDr", LIEF::assembly::x86::OPCODE::VFMADD132PDr) + .value("VFMADD132PHZ128m", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128m) + .value("VFMADD132PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128mb) + .value("VFMADD132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128mbk) + .value("VFMADD132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128mbkz) + .value("VFMADD132PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128mk) + .value("VFMADD132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128mkz) + .value("VFMADD132PHZ128r", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128r) + .value("VFMADD132PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128rk) + .value("VFMADD132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ128rkz) + .value("VFMADD132PHZ256m", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256m) + .value("VFMADD132PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256mb) + .value("VFMADD132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256mbk) + .value("VFMADD132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256mbkz) + .value("VFMADD132PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256mk) + .value("VFMADD132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256mkz) + .value("VFMADD132PHZ256r", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256r) + .value("VFMADD132PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256rk) + .value("VFMADD132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZ256rkz) + .value("VFMADD132PHZm", LIEF::assembly::x86::OPCODE::VFMADD132PHZm) + .value("VFMADD132PHZmb", LIEF::assembly::x86::OPCODE::VFMADD132PHZmb) + .value("VFMADD132PHZmbk", LIEF::assembly::x86::OPCODE::VFMADD132PHZmbk) + .value("VFMADD132PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZmbkz) + .value("VFMADD132PHZmk", LIEF::assembly::x86::OPCODE::VFMADD132PHZmk) + .value("VFMADD132PHZmkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZmkz) + .value("VFMADD132PHZr", LIEF::assembly::x86::OPCODE::VFMADD132PHZr) + .value("VFMADD132PHZrb", LIEF::assembly::x86::OPCODE::VFMADD132PHZrb) + .value("VFMADD132PHZrbk", LIEF::assembly::x86::OPCODE::VFMADD132PHZrbk) + .value("VFMADD132PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZrbkz) + .value("VFMADD132PHZrk", LIEF::assembly::x86::OPCODE::VFMADD132PHZrk) + .value("VFMADD132PHZrkz", LIEF::assembly::x86::OPCODE::VFMADD132PHZrkz) + .value("VFMADD132PSYm", LIEF::assembly::x86::OPCODE::VFMADD132PSYm) + .value("VFMADD132PSYr", LIEF::assembly::x86::OPCODE::VFMADD132PSYr) + .value("VFMADD132PSZ128m", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128m) + .value("VFMADD132PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128mb) + .value("VFMADD132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128mbk) + .value("VFMADD132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128mbkz) + .value("VFMADD132PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128mk) + .value("VFMADD132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128mkz) + .value("VFMADD132PSZ128r", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128r) + .value("VFMADD132PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128rk) + .value("VFMADD132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ128rkz) + .value("VFMADD132PSZ256m", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256m) + .value("VFMADD132PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256mb) + .value("VFMADD132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256mbk) + .value("VFMADD132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256mbkz) + .value("VFMADD132PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256mk) + .value("VFMADD132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256mkz) + .value("VFMADD132PSZ256r", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256r) + .value("VFMADD132PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256rk) + .value("VFMADD132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZ256rkz) + .value("VFMADD132PSZm", LIEF::assembly::x86::OPCODE::VFMADD132PSZm) + .value("VFMADD132PSZmb", LIEF::assembly::x86::OPCODE::VFMADD132PSZmb) + .value("VFMADD132PSZmbk", LIEF::assembly::x86::OPCODE::VFMADD132PSZmbk) + .value("VFMADD132PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZmbkz) + .value("VFMADD132PSZmk", LIEF::assembly::x86::OPCODE::VFMADD132PSZmk) + .value("VFMADD132PSZmkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZmkz) + .value("VFMADD132PSZr", LIEF::assembly::x86::OPCODE::VFMADD132PSZr) + .value("VFMADD132PSZrb", LIEF::assembly::x86::OPCODE::VFMADD132PSZrb) + .value("VFMADD132PSZrbk", LIEF::assembly::x86::OPCODE::VFMADD132PSZrbk) + .value("VFMADD132PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZrbkz) + .value("VFMADD132PSZrk", LIEF::assembly::x86::OPCODE::VFMADD132PSZrk) + .value("VFMADD132PSZrkz", LIEF::assembly::x86::OPCODE::VFMADD132PSZrkz) + .value("VFMADD132PSm", LIEF::assembly::x86::OPCODE::VFMADD132PSm) + .value("VFMADD132PSr", LIEF::assembly::x86::OPCODE::VFMADD132PSr) + .value("VFMADD132SDZm", LIEF::assembly::x86::OPCODE::VFMADD132SDZm) + .value("VFMADD132SDZm_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZm_Int) + .value("VFMADD132SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZmk_Int) + .value("VFMADD132SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZmkz_Int) + .value("VFMADD132SDZr", LIEF::assembly::x86::OPCODE::VFMADD132SDZr) + .value("VFMADD132SDZr_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZr_Int) + .value("VFMADD132SDZrb", LIEF::assembly::x86::OPCODE::VFMADD132SDZrb) + .value("VFMADD132SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZrb_Int) + .value("VFMADD132SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZrbk_Int) + .value("VFMADD132SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZrbkz_Int) + .value("VFMADD132SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZrk_Int) + .value("VFMADD132SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDZrkz_Int) + .value("VFMADD132SDm", LIEF::assembly::x86::OPCODE::VFMADD132SDm) + .value("VFMADD132SDm_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDm_Int) + .value("VFMADD132SDr", LIEF::assembly::x86::OPCODE::VFMADD132SDr) + .value("VFMADD132SDr_Int", LIEF::assembly::x86::OPCODE::VFMADD132SDr_Int) + .value("VFMADD132SHZm", LIEF::assembly::x86::OPCODE::VFMADD132SHZm) + .value("VFMADD132SHZm_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZm_Int) + .value("VFMADD132SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZmk_Int) + .value("VFMADD132SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZmkz_Int) + .value("VFMADD132SHZr", LIEF::assembly::x86::OPCODE::VFMADD132SHZr) + .value("VFMADD132SHZr_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZr_Int) + .value("VFMADD132SHZrb", LIEF::assembly::x86::OPCODE::VFMADD132SHZrb) + .value("VFMADD132SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZrb_Int) + .value("VFMADD132SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZrbk_Int) + .value("VFMADD132SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZrbkz_Int) + .value("VFMADD132SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZrk_Int) + .value("VFMADD132SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SHZrkz_Int) + .value("VFMADD132SSZm", LIEF::assembly::x86::OPCODE::VFMADD132SSZm) + .value("VFMADD132SSZm_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZm_Int) + .value("VFMADD132SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZmk_Int) + .value("VFMADD132SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZmkz_Int) + .value("VFMADD132SSZr", LIEF::assembly::x86::OPCODE::VFMADD132SSZr) + .value("VFMADD132SSZr_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZr_Int) + .value("VFMADD132SSZrb", LIEF::assembly::x86::OPCODE::VFMADD132SSZrb) + .value("VFMADD132SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZrb_Int) + .value("VFMADD132SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZrbk_Int) + .value("VFMADD132SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZrbkz_Int) + .value("VFMADD132SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZrk_Int) + .value("VFMADD132SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSZrkz_Int) + .value("VFMADD132SSm", LIEF::assembly::x86::OPCODE::VFMADD132SSm) + .value("VFMADD132SSm_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSm_Int) + .value("VFMADD132SSr", LIEF::assembly::x86::OPCODE::VFMADD132SSr) + .value("VFMADD132SSr_Int", LIEF::assembly::x86::OPCODE::VFMADD132SSr_Int) + .value("VFMADD213BF16Z128m", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128m) + .value("VFMADD213BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128mb) + .value("VFMADD213BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128mbk) + .value("VFMADD213BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128mbkz) + .value("VFMADD213BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128mk) + .value("VFMADD213BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128mkz) + .value("VFMADD213BF16Z128r", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128r) + .value("VFMADD213BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128rk) + .value("VFMADD213BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z128rkz) + .value("VFMADD213BF16Z256m", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256m) + .value("VFMADD213BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256mb) + .value("VFMADD213BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256mbk) + .value("VFMADD213BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256mbkz) + .value("VFMADD213BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256mk) + .value("VFMADD213BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256mkz) + .value("VFMADD213BF16Z256r", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256r) + .value("VFMADD213BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256rk) + .value("VFMADD213BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Z256rkz) + .value("VFMADD213BF16Zm", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zm) + .value("VFMADD213BF16Zmb", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zmb) + .value("VFMADD213BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zmbk) + .value("VFMADD213BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zmbkz) + .value("VFMADD213BF16Zmk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zmk) + .value("VFMADD213BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zmkz) + .value("VFMADD213BF16Zr", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zr) + .value("VFMADD213BF16Zrk", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zrk) + .value("VFMADD213BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMADD213BF16Zrkz) + .value("VFMADD213PDYm", LIEF::assembly::x86::OPCODE::VFMADD213PDYm) + .value("VFMADD213PDYr", LIEF::assembly::x86::OPCODE::VFMADD213PDYr) + .value("VFMADD213PDZ128m", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128m) + .value("VFMADD213PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128mb) + .value("VFMADD213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128mbk) + .value("VFMADD213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128mbkz) + .value("VFMADD213PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128mk) + .value("VFMADD213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128mkz) + .value("VFMADD213PDZ128r", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128r) + .value("VFMADD213PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128rk) + .value("VFMADD213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ128rkz) + .value("VFMADD213PDZ256m", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256m) + .value("VFMADD213PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256mb) + .value("VFMADD213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256mbk) + .value("VFMADD213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256mbkz) + .value("VFMADD213PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256mk) + .value("VFMADD213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256mkz) + .value("VFMADD213PDZ256r", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256r) + .value("VFMADD213PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256rk) + .value("VFMADD213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZ256rkz) + .value("VFMADD213PDZm", LIEF::assembly::x86::OPCODE::VFMADD213PDZm) + .value("VFMADD213PDZmb", LIEF::assembly::x86::OPCODE::VFMADD213PDZmb) + .value("VFMADD213PDZmbk", LIEF::assembly::x86::OPCODE::VFMADD213PDZmbk) + .value("VFMADD213PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZmbkz) + .value("VFMADD213PDZmk", LIEF::assembly::x86::OPCODE::VFMADD213PDZmk) + .value("VFMADD213PDZmkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZmkz) + .value("VFMADD213PDZr", LIEF::assembly::x86::OPCODE::VFMADD213PDZr) + .value("VFMADD213PDZrb", LIEF::assembly::x86::OPCODE::VFMADD213PDZrb) + .value("VFMADD213PDZrbk", LIEF::assembly::x86::OPCODE::VFMADD213PDZrbk) + .value("VFMADD213PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZrbkz) + .value("VFMADD213PDZrk", LIEF::assembly::x86::OPCODE::VFMADD213PDZrk) + .value("VFMADD213PDZrkz", LIEF::assembly::x86::OPCODE::VFMADD213PDZrkz) + .value("VFMADD213PDm", LIEF::assembly::x86::OPCODE::VFMADD213PDm) + .value("VFMADD213PDr", LIEF::assembly::x86::OPCODE::VFMADD213PDr) + .value("VFMADD213PHZ128m", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128m) + .value("VFMADD213PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128mb) + .value("VFMADD213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128mbk) + .value("VFMADD213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128mbkz) + .value("VFMADD213PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128mk) + .value("VFMADD213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128mkz) + .value("VFMADD213PHZ128r", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128r) + .value("VFMADD213PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128rk) + .value("VFMADD213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ128rkz) + .value("VFMADD213PHZ256m", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256m) + .value("VFMADD213PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256mb) + .value("VFMADD213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256mbk) + .value("VFMADD213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256mbkz) + .value("VFMADD213PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256mk) + .value("VFMADD213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256mkz) + .value("VFMADD213PHZ256r", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256r) + .value("VFMADD213PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256rk) + .value("VFMADD213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZ256rkz) + .value("VFMADD213PHZm", LIEF::assembly::x86::OPCODE::VFMADD213PHZm) + .value("VFMADD213PHZmb", LIEF::assembly::x86::OPCODE::VFMADD213PHZmb) + .value("VFMADD213PHZmbk", LIEF::assembly::x86::OPCODE::VFMADD213PHZmbk) + .value("VFMADD213PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZmbkz) + .value("VFMADD213PHZmk", LIEF::assembly::x86::OPCODE::VFMADD213PHZmk) + .value("VFMADD213PHZmkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZmkz) + .value("VFMADD213PHZr", LIEF::assembly::x86::OPCODE::VFMADD213PHZr) + .value("VFMADD213PHZrb", LIEF::assembly::x86::OPCODE::VFMADD213PHZrb) + .value("VFMADD213PHZrbk", LIEF::assembly::x86::OPCODE::VFMADD213PHZrbk) + .value("VFMADD213PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZrbkz) + .value("VFMADD213PHZrk", LIEF::assembly::x86::OPCODE::VFMADD213PHZrk) + .value("VFMADD213PHZrkz", LIEF::assembly::x86::OPCODE::VFMADD213PHZrkz) + .value("VFMADD213PSYm", LIEF::assembly::x86::OPCODE::VFMADD213PSYm) + .value("VFMADD213PSYr", LIEF::assembly::x86::OPCODE::VFMADD213PSYr) + .value("VFMADD213PSZ128m", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128m) + .value("VFMADD213PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128mb) + .value("VFMADD213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128mbk) + .value("VFMADD213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128mbkz) + .value("VFMADD213PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128mk) + .value("VFMADD213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128mkz) + .value("VFMADD213PSZ128r", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128r) + .value("VFMADD213PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128rk) + .value("VFMADD213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ128rkz) + .value("VFMADD213PSZ256m", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256m) + .value("VFMADD213PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256mb) + .value("VFMADD213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256mbk) + .value("VFMADD213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256mbkz) + .value("VFMADD213PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256mk) + .value("VFMADD213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256mkz) + .value("VFMADD213PSZ256r", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256r) + .value("VFMADD213PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256rk) + .value("VFMADD213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZ256rkz) + .value("VFMADD213PSZm", LIEF::assembly::x86::OPCODE::VFMADD213PSZm) + .value("VFMADD213PSZmb", LIEF::assembly::x86::OPCODE::VFMADD213PSZmb) + .value("VFMADD213PSZmbk", LIEF::assembly::x86::OPCODE::VFMADD213PSZmbk) + .value("VFMADD213PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZmbkz) + .value("VFMADD213PSZmk", LIEF::assembly::x86::OPCODE::VFMADD213PSZmk) + .value("VFMADD213PSZmkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZmkz) + .value("VFMADD213PSZr", LIEF::assembly::x86::OPCODE::VFMADD213PSZr) + .value("VFMADD213PSZrb", LIEF::assembly::x86::OPCODE::VFMADD213PSZrb) + .value("VFMADD213PSZrbk", LIEF::assembly::x86::OPCODE::VFMADD213PSZrbk) + .value("VFMADD213PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZrbkz) + .value("VFMADD213PSZrk", LIEF::assembly::x86::OPCODE::VFMADD213PSZrk) + .value("VFMADD213PSZrkz", LIEF::assembly::x86::OPCODE::VFMADD213PSZrkz) + .value("VFMADD213PSm", LIEF::assembly::x86::OPCODE::VFMADD213PSm) + .value("VFMADD213PSr", LIEF::assembly::x86::OPCODE::VFMADD213PSr) + .value("VFMADD213SDZm", LIEF::assembly::x86::OPCODE::VFMADD213SDZm) + .value("VFMADD213SDZm_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZm_Int) + .value("VFMADD213SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZmk_Int) + .value("VFMADD213SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZmkz_Int) + .value("VFMADD213SDZr", LIEF::assembly::x86::OPCODE::VFMADD213SDZr) + .value("VFMADD213SDZr_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZr_Int) + .value("VFMADD213SDZrb", LIEF::assembly::x86::OPCODE::VFMADD213SDZrb) + .value("VFMADD213SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZrb_Int) + .value("VFMADD213SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZrbk_Int) + .value("VFMADD213SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZrbkz_Int) + .value("VFMADD213SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZrk_Int) + .value("VFMADD213SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDZrkz_Int) + .value("VFMADD213SDm", LIEF::assembly::x86::OPCODE::VFMADD213SDm); + opcodes.value("VFMADD213SDm_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDm_Int) + .value("VFMADD213SDr", LIEF::assembly::x86::OPCODE::VFMADD213SDr) + .value("VFMADD213SDr_Int", LIEF::assembly::x86::OPCODE::VFMADD213SDr_Int) + .value("VFMADD213SHZm", LIEF::assembly::x86::OPCODE::VFMADD213SHZm) + .value("VFMADD213SHZm_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZm_Int) + .value("VFMADD213SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZmk_Int) + .value("VFMADD213SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZmkz_Int) + .value("VFMADD213SHZr", LIEF::assembly::x86::OPCODE::VFMADD213SHZr) + .value("VFMADD213SHZr_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZr_Int) + .value("VFMADD213SHZrb", LIEF::assembly::x86::OPCODE::VFMADD213SHZrb) + .value("VFMADD213SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZrb_Int) + .value("VFMADD213SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZrbk_Int) + .value("VFMADD213SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZrbkz_Int) + .value("VFMADD213SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZrk_Int) + .value("VFMADD213SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SHZrkz_Int) + .value("VFMADD213SSZm", LIEF::assembly::x86::OPCODE::VFMADD213SSZm) + .value("VFMADD213SSZm_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZm_Int) + .value("VFMADD213SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZmk_Int) + .value("VFMADD213SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZmkz_Int) + .value("VFMADD213SSZr", LIEF::assembly::x86::OPCODE::VFMADD213SSZr) + .value("VFMADD213SSZr_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZr_Int) + .value("VFMADD213SSZrb", LIEF::assembly::x86::OPCODE::VFMADD213SSZrb) + .value("VFMADD213SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZrb_Int) + .value("VFMADD213SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZrbk_Int) + .value("VFMADD213SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZrbkz_Int) + .value("VFMADD213SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZrk_Int) + .value("VFMADD213SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSZrkz_Int) + .value("VFMADD213SSm", LIEF::assembly::x86::OPCODE::VFMADD213SSm) + .value("VFMADD213SSm_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSm_Int) + .value("VFMADD213SSr", LIEF::assembly::x86::OPCODE::VFMADD213SSr) + .value("VFMADD213SSr_Int", LIEF::assembly::x86::OPCODE::VFMADD213SSr_Int) + .value("VFMADD231BF16Z128m", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128m) + .value("VFMADD231BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128mb) + .value("VFMADD231BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128mbk) + .value("VFMADD231BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128mbkz) + .value("VFMADD231BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128mk) + .value("VFMADD231BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128mkz) + .value("VFMADD231BF16Z128r", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128r) + .value("VFMADD231BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128rk) + .value("VFMADD231BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z128rkz) + .value("VFMADD231BF16Z256m", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256m) + .value("VFMADD231BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256mb) + .value("VFMADD231BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256mbk) + .value("VFMADD231BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256mbkz) + .value("VFMADD231BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256mk) + .value("VFMADD231BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256mkz) + .value("VFMADD231BF16Z256r", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256r) + .value("VFMADD231BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256rk) + .value("VFMADD231BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Z256rkz) + .value("VFMADD231BF16Zm", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zm) + .value("VFMADD231BF16Zmb", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zmb) + .value("VFMADD231BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zmbk) + .value("VFMADD231BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zmbkz) + .value("VFMADD231BF16Zmk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zmk) + .value("VFMADD231BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zmkz) + .value("VFMADD231BF16Zr", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zr) + .value("VFMADD231BF16Zrk", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zrk) + .value("VFMADD231BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMADD231BF16Zrkz) + .value("VFMADD231PDYm", LIEF::assembly::x86::OPCODE::VFMADD231PDYm) + .value("VFMADD231PDYr", LIEF::assembly::x86::OPCODE::VFMADD231PDYr) + .value("VFMADD231PDZ128m", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128m) + .value("VFMADD231PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128mb) + .value("VFMADD231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128mbk) + .value("VFMADD231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128mbkz) + .value("VFMADD231PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128mk) + .value("VFMADD231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128mkz) + .value("VFMADD231PDZ128r", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128r) + .value("VFMADD231PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128rk) + .value("VFMADD231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ128rkz) + .value("VFMADD231PDZ256m", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256m) + .value("VFMADD231PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256mb) + .value("VFMADD231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256mbk) + .value("VFMADD231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256mbkz) + .value("VFMADD231PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256mk) + .value("VFMADD231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256mkz) + .value("VFMADD231PDZ256r", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256r) + .value("VFMADD231PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256rk) + .value("VFMADD231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZ256rkz) + .value("VFMADD231PDZm", LIEF::assembly::x86::OPCODE::VFMADD231PDZm) + .value("VFMADD231PDZmb", LIEF::assembly::x86::OPCODE::VFMADD231PDZmb) + .value("VFMADD231PDZmbk", LIEF::assembly::x86::OPCODE::VFMADD231PDZmbk) + .value("VFMADD231PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZmbkz) + .value("VFMADD231PDZmk", LIEF::assembly::x86::OPCODE::VFMADD231PDZmk) + .value("VFMADD231PDZmkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZmkz) + .value("VFMADD231PDZr", LIEF::assembly::x86::OPCODE::VFMADD231PDZr) + .value("VFMADD231PDZrb", LIEF::assembly::x86::OPCODE::VFMADD231PDZrb) + .value("VFMADD231PDZrbk", LIEF::assembly::x86::OPCODE::VFMADD231PDZrbk) + .value("VFMADD231PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZrbkz) + .value("VFMADD231PDZrk", LIEF::assembly::x86::OPCODE::VFMADD231PDZrk) + .value("VFMADD231PDZrkz", LIEF::assembly::x86::OPCODE::VFMADD231PDZrkz) + .value("VFMADD231PDm", LIEF::assembly::x86::OPCODE::VFMADD231PDm) + .value("VFMADD231PDr", LIEF::assembly::x86::OPCODE::VFMADD231PDr) + .value("VFMADD231PHZ128m", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128m) + .value("VFMADD231PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128mb) + .value("VFMADD231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128mbk) + .value("VFMADD231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128mbkz) + .value("VFMADD231PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128mk) + .value("VFMADD231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128mkz) + .value("VFMADD231PHZ128r", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128r) + .value("VFMADD231PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128rk) + .value("VFMADD231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ128rkz) + .value("VFMADD231PHZ256m", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256m) + .value("VFMADD231PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256mb) + .value("VFMADD231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256mbk) + .value("VFMADD231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256mbkz) + .value("VFMADD231PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256mk) + .value("VFMADD231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256mkz) + .value("VFMADD231PHZ256r", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256r) + .value("VFMADD231PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256rk) + .value("VFMADD231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZ256rkz) + .value("VFMADD231PHZm", LIEF::assembly::x86::OPCODE::VFMADD231PHZm) + .value("VFMADD231PHZmb", LIEF::assembly::x86::OPCODE::VFMADD231PHZmb) + .value("VFMADD231PHZmbk", LIEF::assembly::x86::OPCODE::VFMADD231PHZmbk) + .value("VFMADD231PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZmbkz) + .value("VFMADD231PHZmk", LIEF::assembly::x86::OPCODE::VFMADD231PHZmk) + .value("VFMADD231PHZmkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZmkz) + .value("VFMADD231PHZr", LIEF::assembly::x86::OPCODE::VFMADD231PHZr) + .value("VFMADD231PHZrb", LIEF::assembly::x86::OPCODE::VFMADD231PHZrb) + .value("VFMADD231PHZrbk", LIEF::assembly::x86::OPCODE::VFMADD231PHZrbk) + .value("VFMADD231PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZrbkz) + .value("VFMADD231PHZrk", LIEF::assembly::x86::OPCODE::VFMADD231PHZrk) + .value("VFMADD231PHZrkz", LIEF::assembly::x86::OPCODE::VFMADD231PHZrkz) + .value("VFMADD231PSYm", LIEF::assembly::x86::OPCODE::VFMADD231PSYm) + .value("VFMADD231PSYr", LIEF::assembly::x86::OPCODE::VFMADD231PSYr) + .value("VFMADD231PSZ128m", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128m) + .value("VFMADD231PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128mb) + .value("VFMADD231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128mbk) + .value("VFMADD231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128mbkz) + .value("VFMADD231PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128mk) + .value("VFMADD231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128mkz) + .value("VFMADD231PSZ128r", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128r) + .value("VFMADD231PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128rk) + .value("VFMADD231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ128rkz) + .value("VFMADD231PSZ256m", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256m) + .value("VFMADD231PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256mb) + .value("VFMADD231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256mbk) + .value("VFMADD231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256mbkz) + .value("VFMADD231PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256mk) + .value("VFMADD231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256mkz) + .value("VFMADD231PSZ256r", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256r) + .value("VFMADD231PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256rk) + .value("VFMADD231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZ256rkz) + .value("VFMADD231PSZm", LIEF::assembly::x86::OPCODE::VFMADD231PSZm) + .value("VFMADD231PSZmb", LIEF::assembly::x86::OPCODE::VFMADD231PSZmb) + .value("VFMADD231PSZmbk", LIEF::assembly::x86::OPCODE::VFMADD231PSZmbk) + .value("VFMADD231PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZmbkz) + .value("VFMADD231PSZmk", LIEF::assembly::x86::OPCODE::VFMADD231PSZmk) + .value("VFMADD231PSZmkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZmkz) + .value("VFMADD231PSZr", LIEF::assembly::x86::OPCODE::VFMADD231PSZr) + .value("VFMADD231PSZrb", LIEF::assembly::x86::OPCODE::VFMADD231PSZrb) + .value("VFMADD231PSZrbk", LIEF::assembly::x86::OPCODE::VFMADD231PSZrbk) + .value("VFMADD231PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZrbkz) + .value("VFMADD231PSZrk", LIEF::assembly::x86::OPCODE::VFMADD231PSZrk) + .value("VFMADD231PSZrkz", LIEF::assembly::x86::OPCODE::VFMADD231PSZrkz) + .value("VFMADD231PSm", LIEF::assembly::x86::OPCODE::VFMADD231PSm) + .value("VFMADD231PSr", LIEF::assembly::x86::OPCODE::VFMADD231PSr) + .value("VFMADD231SDZm", LIEF::assembly::x86::OPCODE::VFMADD231SDZm) + .value("VFMADD231SDZm_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZm_Int) + .value("VFMADD231SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZmk_Int) + .value("VFMADD231SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZmkz_Int) + .value("VFMADD231SDZr", LIEF::assembly::x86::OPCODE::VFMADD231SDZr) + .value("VFMADD231SDZr_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZr_Int) + .value("VFMADD231SDZrb", LIEF::assembly::x86::OPCODE::VFMADD231SDZrb) + .value("VFMADD231SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZrb_Int) + .value("VFMADD231SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZrbk_Int) + .value("VFMADD231SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZrbkz_Int) + .value("VFMADD231SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZrk_Int) + .value("VFMADD231SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDZrkz_Int) + .value("VFMADD231SDm", LIEF::assembly::x86::OPCODE::VFMADD231SDm) + .value("VFMADD231SDm_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDm_Int) + .value("VFMADD231SDr", LIEF::assembly::x86::OPCODE::VFMADD231SDr) + .value("VFMADD231SDr_Int", LIEF::assembly::x86::OPCODE::VFMADD231SDr_Int) + .value("VFMADD231SHZm", LIEF::assembly::x86::OPCODE::VFMADD231SHZm) + .value("VFMADD231SHZm_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZm_Int) + .value("VFMADD231SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZmk_Int) + .value("VFMADD231SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZmkz_Int) + .value("VFMADD231SHZr", LIEF::assembly::x86::OPCODE::VFMADD231SHZr) + .value("VFMADD231SHZr_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZr_Int) + .value("VFMADD231SHZrb", LIEF::assembly::x86::OPCODE::VFMADD231SHZrb) + .value("VFMADD231SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZrb_Int) + .value("VFMADD231SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZrbk_Int) + .value("VFMADD231SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZrbkz_Int) + .value("VFMADD231SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZrk_Int) + .value("VFMADD231SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SHZrkz_Int) + .value("VFMADD231SSZm", LIEF::assembly::x86::OPCODE::VFMADD231SSZm) + .value("VFMADD231SSZm_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZm_Int) + .value("VFMADD231SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZmk_Int) + .value("VFMADD231SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZmkz_Int) + .value("VFMADD231SSZr", LIEF::assembly::x86::OPCODE::VFMADD231SSZr) + .value("VFMADD231SSZr_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZr_Int) + .value("VFMADD231SSZrb", LIEF::assembly::x86::OPCODE::VFMADD231SSZrb) + .value("VFMADD231SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZrb_Int) + .value("VFMADD231SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZrbk_Int) + .value("VFMADD231SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZrbkz_Int) + .value("VFMADD231SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZrk_Int) + .value("VFMADD231SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSZrkz_Int) + .value("VFMADD231SSm", LIEF::assembly::x86::OPCODE::VFMADD231SSm) + .value("VFMADD231SSm_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSm_Int) + .value("VFMADD231SSr", LIEF::assembly::x86::OPCODE::VFMADD231SSr) + .value("VFMADD231SSr_Int", LIEF::assembly::x86::OPCODE::VFMADD231SSr_Int) + .value("VFMADDCPHZ128m", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128m) + .value("VFMADDCPHZ128mb", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128mb) + .value("VFMADDCPHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128mbk) + .value("VFMADDCPHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128mbkz) + .value("VFMADDCPHZ128mk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128mk) + .value("VFMADDCPHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128mkz) + .value("VFMADDCPHZ128r", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128r) + .value("VFMADDCPHZ128rk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128rk) + .value("VFMADDCPHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ128rkz) + .value("VFMADDCPHZ256m", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256m) + .value("VFMADDCPHZ256mb", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256mb) + .value("VFMADDCPHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256mbk) + .value("VFMADDCPHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256mbkz) + .value("VFMADDCPHZ256mk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256mk) + .value("VFMADDCPHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256mkz) + .value("VFMADDCPHZ256r", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256r) + .value("VFMADDCPHZ256rk", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256rk) + .value("VFMADDCPHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZ256rkz) + .value("VFMADDCPHZm", LIEF::assembly::x86::OPCODE::VFMADDCPHZm) + .value("VFMADDCPHZmb", LIEF::assembly::x86::OPCODE::VFMADDCPHZmb) + .value("VFMADDCPHZmbk", LIEF::assembly::x86::OPCODE::VFMADDCPHZmbk) + .value("VFMADDCPHZmbkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZmbkz) + .value("VFMADDCPHZmk", LIEF::assembly::x86::OPCODE::VFMADDCPHZmk) + .value("VFMADDCPHZmkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZmkz) + .value("VFMADDCPHZr", LIEF::assembly::x86::OPCODE::VFMADDCPHZr) + .value("VFMADDCPHZrb", LIEF::assembly::x86::OPCODE::VFMADDCPHZrb) + .value("VFMADDCPHZrbk", LIEF::assembly::x86::OPCODE::VFMADDCPHZrbk) + .value("VFMADDCPHZrbkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZrbkz) + .value("VFMADDCPHZrk", LIEF::assembly::x86::OPCODE::VFMADDCPHZrk) + .value("VFMADDCPHZrkz", LIEF::assembly::x86::OPCODE::VFMADDCPHZrkz) + .value("VFMADDCSHZm", LIEF::assembly::x86::OPCODE::VFMADDCSHZm) + .value("VFMADDCSHZmk", LIEF::assembly::x86::OPCODE::VFMADDCSHZmk) + .value("VFMADDCSHZmkz", LIEF::assembly::x86::OPCODE::VFMADDCSHZmkz) + .value("VFMADDCSHZr", LIEF::assembly::x86::OPCODE::VFMADDCSHZr) + .value("VFMADDCSHZrb", LIEF::assembly::x86::OPCODE::VFMADDCSHZrb) + .value("VFMADDCSHZrbk", LIEF::assembly::x86::OPCODE::VFMADDCSHZrbk) + .value("VFMADDCSHZrbkz", LIEF::assembly::x86::OPCODE::VFMADDCSHZrbkz) + .value("VFMADDCSHZrk", LIEF::assembly::x86::OPCODE::VFMADDCSHZrk) + .value("VFMADDCSHZrkz", LIEF::assembly::x86::OPCODE::VFMADDCSHZrkz) + .value("VFMADDPD4Ymr", LIEF::assembly::x86::OPCODE::VFMADDPD4Ymr) + .value("VFMADDPD4Yrm", LIEF::assembly::x86::OPCODE::VFMADDPD4Yrm) + .value("VFMADDPD4Yrr", LIEF::assembly::x86::OPCODE::VFMADDPD4Yrr) + .value("VFMADDPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMADDPD4Yrr_REV) + .value("VFMADDPD4mr", LIEF::assembly::x86::OPCODE::VFMADDPD4mr) + .value("VFMADDPD4rm", LIEF::assembly::x86::OPCODE::VFMADDPD4rm) + .value("VFMADDPD4rr", LIEF::assembly::x86::OPCODE::VFMADDPD4rr) + .value("VFMADDPD4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDPD4rr_REV) + .value("VFMADDPS4Ymr", LIEF::assembly::x86::OPCODE::VFMADDPS4Ymr) + .value("VFMADDPS4Yrm", LIEF::assembly::x86::OPCODE::VFMADDPS4Yrm) + .value("VFMADDPS4Yrr", LIEF::assembly::x86::OPCODE::VFMADDPS4Yrr) + .value("VFMADDPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMADDPS4Yrr_REV) + .value("VFMADDPS4mr", LIEF::assembly::x86::OPCODE::VFMADDPS4mr) + .value("VFMADDPS4rm", LIEF::assembly::x86::OPCODE::VFMADDPS4rm) + .value("VFMADDPS4rr", LIEF::assembly::x86::OPCODE::VFMADDPS4rr) + .value("VFMADDPS4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDPS4rr_REV) + .value("VFMADDSD4mr", LIEF::assembly::x86::OPCODE::VFMADDSD4mr) + .value("VFMADDSD4mr_Int", LIEF::assembly::x86::OPCODE::VFMADDSD4mr_Int) + .value("VFMADDSD4rm", LIEF::assembly::x86::OPCODE::VFMADDSD4rm) + .value("VFMADDSD4rm_Int", LIEF::assembly::x86::OPCODE::VFMADDSD4rm_Int) + .value("VFMADDSD4rr", LIEF::assembly::x86::OPCODE::VFMADDSD4rr) + .value("VFMADDSD4rr_Int", LIEF::assembly::x86::OPCODE::VFMADDSD4rr_Int) + .value("VFMADDSD4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFMADDSD4rr_Int_REV) + .value("VFMADDSD4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDSD4rr_REV) + .value("VFMADDSS4mr", LIEF::assembly::x86::OPCODE::VFMADDSS4mr) + .value("VFMADDSS4mr_Int", LIEF::assembly::x86::OPCODE::VFMADDSS4mr_Int) + .value("VFMADDSS4rm", LIEF::assembly::x86::OPCODE::VFMADDSS4rm) + .value("VFMADDSS4rm_Int", LIEF::assembly::x86::OPCODE::VFMADDSS4rm_Int) + .value("VFMADDSS4rr", LIEF::assembly::x86::OPCODE::VFMADDSS4rr) + .value("VFMADDSS4rr_Int", LIEF::assembly::x86::OPCODE::VFMADDSS4rr_Int) + .value("VFMADDSS4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFMADDSS4rr_Int_REV) + .value("VFMADDSS4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDSS4rr_REV) + .value("VFMADDSUB132PDYm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDYm) + .value("VFMADDSUB132PDYr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDYr) + .value("VFMADDSUB132PDZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128m) + .value("VFMADDSUB132PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128mb) + .value("VFMADDSUB132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128mbk) + .value("VFMADDSUB132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128mbkz) + .value("VFMADDSUB132PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128mk) + .value("VFMADDSUB132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128mkz) + .value("VFMADDSUB132PDZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128r) + .value("VFMADDSUB132PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128rk) + .value("VFMADDSUB132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ128rkz) + .value("VFMADDSUB132PDZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256m) + .value("VFMADDSUB132PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256mb) + .value("VFMADDSUB132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256mbk) + .value("VFMADDSUB132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256mbkz) + .value("VFMADDSUB132PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256mk) + .value("VFMADDSUB132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256mkz) + .value("VFMADDSUB132PDZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256r) + .value("VFMADDSUB132PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256rk) + .value("VFMADDSUB132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZ256rkz) + .value("VFMADDSUB132PDZm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZm) + .value("VFMADDSUB132PDZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZmb) + .value("VFMADDSUB132PDZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZmbk) + .value("VFMADDSUB132PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZmbkz) + .value("VFMADDSUB132PDZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZmk) + .value("VFMADDSUB132PDZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZmkz) + .value("VFMADDSUB132PDZr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZr) + .value("VFMADDSUB132PDZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZrb) + .value("VFMADDSUB132PDZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZrbk); + opcodes.value("VFMADDSUB132PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZrbkz) + .value("VFMADDSUB132PDZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZrk) + .value("VFMADDSUB132PDZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDZrkz) + .value("VFMADDSUB132PDm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDm) + .value("VFMADDSUB132PDr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PDr) + .value("VFMADDSUB132PHZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128m) + .value("VFMADDSUB132PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128mb) + .value("VFMADDSUB132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128mbk) + .value("VFMADDSUB132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128mbkz) + .value("VFMADDSUB132PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128mk) + .value("VFMADDSUB132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128mkz) + .value("VFMADDSUB132PHZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128r) + .value("VFMADDSUB132PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128rk) + .value("VFMADDSUB132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ128rkz) + .value("VFMADDSUB132PHZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256m) + .value("VFMADDSUB132PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256mb) + .value("VFMADDSUB132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256mbk) + .value("VFMADDSUB132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256mbkz) + .value("VFMADDSUB132PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256mk) + .value("VFMADDSUB132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256mkz) + .value("VFMADDSUB132PHZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256r) + .value("VFMADDSUB132PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256rk) + .value("VFMADDSUB132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZ256rkz) + .value("VFMADDSUB132PHZm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZm) + .value("VFMADDSUB132PHZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZmb) + .value("VFMADDSUB132PHZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZmbk) + .value("VFMADDSUB132PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZmbkz) + .value("VFMADDSUB132PHZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZmk) + .value("VFMADDSUB132PHZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZmkz) + .value("VFMADDSUB132PHZr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZr) + .value("VFMADDSUB132PHZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZrb) + .value("VFMADDSUB132PHZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZrbk) + .value("VFMADDSUB132PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZrbkz) + .value("VFMADDSUB132PHZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZrk) + .value("VFMADDSUB132PHZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PHZrkz) + .value("VFMADDSUB132PSYm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSYm) + .value("VFMADDSUB132PSYr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSYr) + .value("VFMADDSUB132PSZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128m) + .value("VFMADDSUB132PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128mb) + .value("VFMADDSUB132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128mbk) + .value("VFMADDSUB132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128mbkz) + .value("VFMADDSUB132PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128mk) + .value("VFMADDSUB132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128mkz) + .value("VFMADDSUB132PSZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128r) + .value("VFMADDSUB132PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128rk) + .value("VFMADDSUB132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ128rkz) + .value("VFMADDSUB132PSZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256m) + .value("VFMADDSUB132PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256mb) + .value("VFMADDSUB132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256mbk) + .value("VFMADDSUB132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256mbkz) + .value("VFMADDSUB132PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256mk) + .value("VFMADDSUB132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256mkz) + .value("VFMADDSUB132PSZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256r) + .value("VFMADDSUB132PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256rk) + .value("VFMADDSUB132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZ256rkz) + .value("VFMADDSUB132PSZm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZm) + .value("VFMADDSUB132PSZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZmb) + .value("VFMADDSUB132PSZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZmbk) + .value("VFMADDSUB132PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZmbkz) + .value("VFMADDSUB132PSZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZmk) + .value("VFMADDSUB132PSZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZmkz) + .value("VFMADDSUB132PSZr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZr) + .value("VFMADDSUB132PSZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZrb) + .value("VFMADDSUB132PSZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZrbk) + .value("VFMADDSUB132PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZrbkz) + .value("VFMADDSUB132PSZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZrk) + .value("VFMADDSUB132PSZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSZrkz) + .value("VFMADDSUB132PSm", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSm) + .value("VFMADDSUB132PSr", LIEF::assembly::x86::OPCODE::VFMADDSUB132PSr) + .value("VFMADDSUB213PDYm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDYm) + .value("VFMADDSUB213PDYr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDYr) + .value("VFMADDSUB213PDZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128m) + .value("VFMADDSUB213PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128mb) + .value("VFMADDSUB213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128mbk) + .value("VFMADDSUB213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128mbkz) + .value("VFMADDSUB213PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128mk) + .value("VFMADDSUB213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128mkz) + .value("VFMADDSUB213PDZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128r) + .value("VFMADDSUB213PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128rk) + .value("VFMADDSUB213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ128rkz) + .value("VFMADDSUB213PDZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256m) + .value("VFMADDSUB213PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256mb) + .value("VFMADDSUB213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256mbk) + .value("VFMADDSUB213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256mbkz) + .value("VFMADDSUB213PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256mk) + .value("VFMADDSUB213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256mkz) + .value("VFMADDSUB213PDZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256r) + .value("VFMADDSUB213PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256rk) + .value("VFMADDSUB213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZ256rkz) + .value("VFMADDSUB213PDZm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZm) + .value("VFMADDSUB213PDZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZmb) + .value("VFMADDSUB213PDZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZmbk) + .value("VFMADDSUB213PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZmbkz) + .value("VFMADDSUB213PDZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZmk) + .value("VFMADDSUB213PDZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZmkz) + .value("VFMADDSUB213PDZr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZr) + .value("VFMADDSUB213PDZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZrb) + .value("VFMADDSUB213PDZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZrbk) + .value("VFMADDSUB213PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZrbkz) + .value("VFMADDSUB213PDZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZrk) + .value("VFMADDSUB213PDZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDZrkz) + .value("VFMADDSUB213PDm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDm) + .value("VFMADDSUB213PDr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PDr) + .value("VFMADDSUB213PHZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128m) + .value("VFMADDSUB213PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128mb) + .value("VFMADDSUB213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128mbk) + .value("VFMADDSUB213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128mbkz) + .value("VFMADDSUB213PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128mk) + .value("VFMADDSUB213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128mkz) + .value("VFMADDSUB213PHZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128r) + .value("VFMADDSUB213PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128rk) + .value("VFMADDSUB213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ128rkz) + .value("VFMADDSUB213PHZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256m) + .value("VFMADDSUB213PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256mb) + .value("VFMADDSUB213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256mbk) + .value("VFMADDSUB213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256mbkz) + .value("VFMADDSUB213PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256mk) + .value("VFMADDSUB213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256mkz) + .value("VFMADDSUB213PHZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256r) + .value("VFMADDSUB213PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256rk) + .value("VFMADDSUB213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZ256rkz) + .value("VFMADDSUB213PHZm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZm) + .value("VFMADDSUB213PHZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZmb) + .value("VFMADDSUB213PHZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZmbk) + .value("VFMADDSUB213PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZmbkz) + .value("VFMADDSUB213PHZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZmk) + .value("VFMADDSUB213PHZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZmkz) + .value("VFMADDSUB213PHZr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZr) + .value("VFMADDSUB213PHZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZrb) + .value("VFMADDSUB213PHZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZrbk) + .value("VFMADDSUB213PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZrbkz) + .value("VFMADDSUB213PHZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZrk) + .value("VFMADDSUB213PHZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PHZrkz) + .value("VFMADDSUB213PSYm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSYm) + .value("VFMADDSUB213PSYr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSYr) + .value("VFMADDSUB213PSZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128m) + .value("VFMADDSUB213PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128mb) + .value("VFMADDSUB213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128mbk) + .value("VFMADDSUB213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128mbkz) + .value("VFMADDSUB213PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128mk) + .value("VFMADDSUB213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128mkz) + .value("VFMADDSUB213PSZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128r) + .value("VFMADDSUB213PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128rk) + .value("VFMADDSUB213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ128rkz) + .value("VFMADDSUB213PSZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256m) + .value("VFMADDSUB213PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256mb) + .value("VFMADDSUB213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256mbk) + .value("VFMADDSUB213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256mbkz) + .value("VFMADDSUB213PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256mk) + .value("VFMADDSUB213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256mkz) + .value("VFMADDSUB213PSZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256r) + .value("VFMADDSUB213PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256rk) + .value("VFMADDSUB213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZ256rkz) + .value("VFMADDSUB213PSZm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZm) + .value("VFMADDSUB213PSZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZmb) + .value("VFMADDSUB213PSZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZmbk) + .value("VFMADDSUB213PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZmbkz) + .value("VFMADDSUB213PSZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZmk) + .value("VFMADDSUB213PSZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZmkz) + .value("VFMADDSUB213PSZr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZr) + .value("VFMADDSUB213PSZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZrb) + .value("VFMADDSUB213PSZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZrbk) + .value("VFMADDSUB213PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZrbkz) + .value("VFMADDSUB213PSZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZrk) + .value("VFMADDSUB213PSZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSZrkz) + .value("VFMADDSUB213PSm", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSm) + .value("VFMADDSUB213PSr", LIEF::assembly::x86::OPCODE::VFMADDSUB213PSr) + .value("VFMADDSUB231PDYm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDYm) + .value("VFMADDSUB231PDYr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDYr) + .value("VFMADDSUB231PDZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128m) + .value("VFMADDSUB231PDZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128mb) + .value("VFMADDSUB231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128mbk) + .value("VFMADDSUB231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128mbkz) + .value("VFMADDSUB231PDZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128mk) + .value("VFMADDSUB231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128mkz) + .value("VFMADDSUB231PDZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128r) + .value("VFMADDSUB231PDZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128rk) + .value("VFMADDSUB231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ128rkz) + .value("VFMADDSUB231PDZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256m) + .value("VFMADDSUB231PDZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256mb) + .value("VFMADDSUB231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256mbk) + .value("VFMADDSUB231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256mbkz) + .value("VFMADDSUB231PDZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256mk) + .value("VFMADDSUB231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256mkz) + .value("VFMADDSUB231PDZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256r) + .value("VFMADDSUB231PDZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256rk) + .value("VFMADDSUB231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZ256rkz) + .value("VFMADDSUB231PDZm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZm) + .value("VFMADDSUB231PDZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZmb) + .value("VFMADDSUB231PDZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZmbk) + .value("VFMADDSUB231PDZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZmbkz) + .value("VFMADDSUB231PDZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZmk) + .value("VFMADDSUB231PDZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZmkz) + .value("VFMADDSUB231PDZr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZr) + .value("VFMADDSUB231PDZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZrb) + .value("VFMADDSUB231PDZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZrbk) + .value("VFMADDSUB231PDZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZrbkz) + .value("VFMADDSUB231PDZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZrk) + .value("VFMADDSUB231PDZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDZrkz) + .value("VFMADDSUB231PDm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDm) + .value("VFMADDSUB231PDr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PDr) + .value("VFMADDSUB231PHZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128m) + .value("VFMADDSUB231PHZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128mb) + .value("VFMADDSUB231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128mbk) + .value("VFMADDSUB231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128mbkz) + .value("VFMADDSUB231PHZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128mk) + .value("VFMADDSUB231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128mkz) + .value("VFMADDSUB231PHZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128r) + .value("VFMADDSUB231PHZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128rk) + .value("VFMADDSUB231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ128rkz) + .value("VFMADDSUB231PHZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256m) + .value("VFMADDSUB231PHZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256mb) + .value("VFMADDSUB231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256mbk) + .value("VFMADDSUB231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256mbkz) + .value("VFMADDSUB231PHZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256mk) + .value("VFMADDSUB231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256mkz) + .value("VFMADDSUB231PHZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256r) + .value("VFMADDSUB231PHZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256rk) + .value("VFMADDSUB231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZ256rkz) + .value("VFMADDSUB231PHZm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZm) + .value("VFMADDSUB231PHZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZmb) + .value("VFMADDSUB231PHZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZmbk) + .value("VFMADDSUB231PHZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZmbkz) + .value("VFMADDSUB231PHZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZmk) + .value("VFMADDSUB231PHZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZmkz) + .value("VFMADDSUB231PHZr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZr) + .value("VFMADDSUB231PHZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZrb) + .value("VFMADDSUB231PHZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZrbk) + .value("VFMADDSUB231PHZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZrbkz) + .value("VFMADDSUB231PHZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZrk) + .value("VFMADDSUB231PHZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PHZrkz) + .value("VFMADDSUB231PSYm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSYm) + .value("VFMADDSUB231PSYr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSYr) + .value("VFMADDSUB231PSZ128m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128m) + .value("VFMADDSUB231PSZ128mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128mb) + .value("VFMADDSUB231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128mbk) + .value("VFMADDSUB231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128mbkz) + .value("VFMADDSUB231PSZ128mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128mk) + .value("VFMADDSUB231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128mkz) + .value("VFMADDSUB231PSZ128r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128r) + .value("VFMADDSUB231PSZ128rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128rk) + .value("VFMADDSUB231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ128rkz) + .value("VFMADDSUB231PSZ256m", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256m) + .value("VFMADDSUB231PSZ256mb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256mb) + .value("VFMADDSUB231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256mbk) + .value("VFMADDSUB231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256mbkz) + .value("VFMADDSUB231PSZ256mk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256mk) + .value("VFMADDSUB231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256mkz) + .value("VFMADDSUB231PSZ256r", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256r) + .value("VFMADDSUB231PSZ256rk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256rk) + .value("VFMADDSUB231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZ256rkz) + .value("VFMADDSUB231PSZm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZm) + .value("VFMADDSUB231PSZmb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZmb) + .value("VFMADDSUB231PSZmbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZmbk) + .value("VFMADDSUB231PSZmbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZmbkz) + .value("VFMADDSUB231PSZmk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZmk) + .value("VFMADDSUB231PSZmkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZmkz) + .value("VFMADDSUB231PSZr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZr) + .value("VFMADDSUB231PSZrb", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZrb) + .value("VFMADDSUB231PSZrbk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZrbk) + .value("VFMADDSUB231PSZrbkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZrbkz) + .value("VFMADDSUB231PSZrk", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZrk) + .value("VFMADDSUB231PSZrkz", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSZrkz) + .value("VFMADDSUB231PSm", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSm) + .value("VFMADDSUB231PSr", LIEF::assembly::x86::OPCODE::VFMADDSUB231PSr) + .value("VFMADDSUBPD4Ymr", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4Ymr) + .value("VFMADDSUBPD4Yrm", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4Yrm) + .value("VFMADDSUBPD4Yrr", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4Yrr) + .value("VFMADDSUBPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4Yrr_REV) + .value("VFMADDSUBPD4mr", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4mr) + .value("VFMADDSUBPD4rm", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4rm) + .value("VFMADDSUBPD4rr", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4rr) + .value("VFMADDSUBPD4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDSUBPD4rr_REV) + .value("VFMADDSUBPS4Ymr", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4Ymr) + .value("VFMADDSUBPS4Yrm", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4Yrm) + .value("VFMADDSUBPS4Yrr", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4Yrr) + .value("VFMADDSUBPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4Yrr_REV) + .value("VFMADDSUBPS4mr", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4mr) + .value("VFMADDSUBPS4rm", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4rm) + .value("VFMADDSUBPS4rr", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4rr) + .value("VFMADDSUBPS4rr_REV", LIEF::assembly::x86::OPCODE::VFMADDSUBPS4rr_REV) + .value("VFMSUB132BF16Z128m", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128m) + .value("VFMSUB132BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128mb) + .value("VFMSUB132BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128mbk) + .value("VFMSUB132BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128mbkz) + .value("VFMSUB132BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128mk) + .value("VFMSUB132BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128mkz) + .value("VFMSUB132BF16Z128r", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128r) + .value("VFMSUB132BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128rk) + .value("VFMSUB132BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z128rkz) + .value("VFMSUB132BF16Z256m", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256m) + .value("VFMSUB132BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256mb) + .value("VFMSUB132BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256mbk) + .value("VFMSUB132BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256mbkz) + .value("VFMSUB132BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256mk) + .value("VFMSUB132BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256mkz) + .value("VFMSUB132BF16Z256r", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256r) + .value("VFMSUB132BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256rk) + .value("VFMSUB132BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Z256rkz) + .value("VFMSUB132BF16Zm", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zm); + opcodes.value("VFMSUB132BF16Zmb", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zmb) + .value("VFMSUB132BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zmbk) + .value("VFMSUB132BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zmbkz) + .value("VFMSUB132BF16Zmk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zmk) + .value("VFMSUB132BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zmkz) + .value("VFMSUB132BF16Zr", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zr) + .value("VFMSUB132BF16Zrk", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zrk) + .value("VFMSUB132BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMSUB132BF16Zrkz) + .value("VFMSUB132PDYm", LIEF::assembly::x86::OPCODE::VFMSUB132PDYm) + .value("VFMSUB132PDYr", LIEF::assembly::x86::OPCODE::VFMSUB132PDYr) + .value("VFMSUB132PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128m) + .value("VFMSUB132PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128mb) + .value("VFMSUB132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128mbk) + .value("VFMSUB132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128mbkz) + .value("VFMSUB132PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128mk) + .value("VFMSUB132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128mkz) + .value("VFMSUB132PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128r) + .value("VFMSUB132PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128rk) + .value("VFMSUB132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ128rkz) + .value("VFMSUB132PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256m) + .value("VFMSUB132PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256mb) + .value("VFMSUB132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256mbk) + .value("VFMSUB132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256mbkz) + .value("VFMSUB132PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256mk) + .value("VFMSUB132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256mkz) + .value("VFMSUB132PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256r) + .value("VFMSUB132PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256rk) + .value("VFMSUB132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZ256rkz) + .value("VFMSUB132PDZm", LIEF::assembly::x86::OPCODE::VFMSUB132PDZm) + .value("VFMSUB132PDZmb", LIEF::assembly::x86::OPCODE::VFMSUB132PDZmb) + .value("VFMSUB132PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZmbk) + .value("VFMSUB132PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZmbkz) + .value("VFMSUB132PDZmk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZmk) + .value("VFMSUB132PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZmkz) + .value("VFMSUB132PDZr", LIEF::assembly::x86::OPCODE::VFMSUB132PDZr) + .value("VFMSUB132PDZrb", LIEF::assembly::x86::OPCODE::VFMSUB132PDZrb) + .value("VFMSUB132PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZrbk) + .value("VFMSUB132PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZrbkz) + .value("VFMSUB132PDZrk", LIEF::assembly::x86::OPCODE::VFMSUB132PDZrk) + .value("VFMSUB132PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUB132PDZrkz) + .value("VFMSUB132PDm", LIEF::assembly::x86::OPCODE::VFMSUB132PDm) + .value("VFMSUB132PDr", LIEF::assembly::x86::OPCODE::VFMSUB132PDr) + .value("VFMSUB132PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128m) + .value("VFMSUB132PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128mb) + .value("VFMSUB132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128mbk) + .value("VFMSUB132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128mbkz) + .value("VFMSUB132PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128mk) + .value("VFMSUB132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128mkz) + .value("VFMSUB132PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128r) + .value("VFMSUB132PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128rk) + .value("VFMSUB132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ128rkz) + .value("VFMSUB132PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256m) + .value("VFMSUB132PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256mb) + .value("VFMSUB132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256mbk) + .value("VFMSUB132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256mbkz) + .value("VFMSUB132PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256mk) + .value("VFMSUB132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256mkz) + .value("VFMSUB132PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256r) + .value("VFMSUB132PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256rk) + .value("VFMSUB132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZ256rkz) + .value("VFMSUB132PHZm", LIEF::assembly::x86::OPCODE::VFMSUB132PHZm) + .value("VFMSUB132PHZmb", LIEF::assembly::x86::OPCODE::VFMSUB132PHZmb) + .value("VFMSUB132PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZmbk) + .value("VFMSUB132PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZmbkz) + .value("VFMSUB132PHZmk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZmk) + .value("VFMSUB132PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZmkz) + .value("VFMSUB132PHZr", LIEF::assembly::x86::OPCODE::VFMSUB132PHZr) + .value("VFMSUB132PHZrb", LIEF::assembly::x86::OPCODE::VFMSUB132PHZrb) + .value("VFMSUB132PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZrbk) + .value("VFMSUB132PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZrbkz) + .value("VFMSUB132PHZrk", LIEF::assembly::x86::OPCODE::VFMSUB132PHZrk) + .value("VFMSUB132PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUB132PHZrkz) + .value("VFMSUB132PSYm", LIEF::assembly::x86::OPCODE::VFMSUB132PSYm) + .value("VFMSUB132PSYr", LIEF::assembly::x86::OPCODE::VFMSUB132PSYr) + .value("VFMSUB132PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128m) + .value("VFMSUB132PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128mb) + .value("VFMSUB132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128mbk) + .value("VFMSUB132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128mbkz) + .value("VFMSUB132PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128mk) + .value("VFMSUB132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128mkz) + .value("VFMSUB132PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128r) + .value("VFMSUB132PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128rk) + .value("VFMSUB132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ128rkz) + .value("VFMSUB132PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256m) + .value("VFMSUB132PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256mb) + .value("VFMSUB132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256mbk) + .value("VFMSUB132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256mbkz) + .value("VFMSUB132PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256mk) + .value("VFMSUB132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256mkz) + .value("VFMSUB132PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256r) + .value("VFMSUB132PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256rk) + .value("VFMSUB132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZ256rkz) + .value("VFMSUB132PSZm", LIEF::assembly::x86::OPCODE::VFMSUB132PSZm) + .value("VFMSUB132PSZmb", LIEF::assembly::x86::OPCODE::VFMSUB132PSZmb) + .value("VFMSUB132PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZmbk) + .value("VFMSUB132PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZmbkz) + .value("VFMSUB132PSZmk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZmk) + .value("VFMSUB132PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZmkz) + .value("VFMSUB132PSZr", LIEF::assembly::x86::OPCODE::VFMSUB132PSZr) + .value("VFMSUB132PSZrb", LIEF::assembly::x86::OPCODE::VFMSUB132PSZrb) + .value("VFMSUB132PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZrbk) + .value("VFMSUB132PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZrbkz) + .value("VFMSUB132PSZrk", LIEF::assembly::x86::OPCODE::VFMSUB132PSZrk) + .value("VFMSUB132PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUB132PSZrkz) + .value("VFMSUB132PSm", LIEF::assembly::x86::OPCODE::VFMSUB132PSm) + .value("VFMSUB132PSr", LIEF::assembly::x86::OPCODE::VFMSUB132PSr) + .value("VFMSUB132SDZm", LIEF::assembly::x86::OPCODE::VFMSUB132SDZm) + .value("VFMSUB132SDZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZm_Int) + .value("VFMSUB132SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZmk_Int) + .value("VFMSUB132SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZmkz_Int) + .value("VFMSUB132SDZr", LIEF::assembly::x86::OPCODE::VFMSUB132SDZr) + .value("VFMSUB132SDZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZr_Int) + .value("VFMSUB132SDZrb", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrb) + .value("VFMSUB132SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrb_Int) + .value("VFMSUB132SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrbk_Int) + .value("VFMSUB132SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrbkz_Int) + .value("VFMSUB132SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrk_Int) + .value("VFMSUB132SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDZrkz_Int) + .value("VFMSUB132SDm", LIEF::assembly::x86::OPCODE::VFMSUB132SDm) + .value("VFMSUB132SDm_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDm_Int) + .value("VFMSUB132SDr", LIEF::assembly::x86::OPCODE::VFMSUB132SDr) + .value("VFMSUB132SDr_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SDr_Int) + .value("VFMSUB132SHZm", LIEF::assembly::x86::OPCODE::VFMSUB132SHZm) + .value("VFMSUB132SHZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZm_Int) + .value("VFMSUB132SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZmk_Int) + .value("VFMSUB132SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZmkz_Int) + .value("VFMSUB132SHZr", LIEF::assembly::x86::OPCODE::VFMSUB132SHZr) + .value("VFMSUB132SHZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZr_Int) + .value("VFMSUB132SHZrb", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrb) + .value("VFMSUB132SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrb_Int) + .value("VFMSUB132SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrbk_Int) + .value("VFMSUB132SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrbkz_Int) + .value("VFMSUB132SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrk_Int) + .value("VFMSUB132SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SHZrkz_Int) + .value("VFMSUB132SSZm", LIEF::assembly::x86::OPCODE::VFMSUB132SSZm) + .value("VFMSUB132SSZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZm_Int) + .value("VFMSUB132SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZmk_Int) + .value("VFMSUB132SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZmkz_Int) + .value("VFMSUB132SSZr", LIEF::assembly::x86::OPCODE::VFMSUB132SSZr) + .value("VFMSUB132SSZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZr_Int) + .value("VFMSUB132SSZrb", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrb) + .value("VFMSUB132SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrb_Int) + .value("VFMSUB132SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrbk_Int) + .value("VFMSUB132SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrbkz_Int) + .value("VFMSUB132SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrk_Int) + .value("VFMSUB132SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSZrkz_Int) + .value("VFMSUB132SSm", LIEF::assembly::x86::OPCODE::VFMSUB132SSm) + .value("VFMSUB132SSm_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSm_Int) + .value("VFMSUB132SSr", LIEF::assembly::x86::OPCODE::VFMSUB132SSr) + .value("VFMSUB132SSr_Int", LIEF::assembly::x86::OPCODE::VFMSUB132SSr_Int) + .value("VFMSUB213BF16Z128m", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128m) + .value("VFMSUB213BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128mb) + .value("VFMSUB213BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128mbk) + .value("VFMSUB213BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128mbkz) + .value("VFMSUB213BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128mk) + .value("VFMSUB213BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128mkz) + .value("VFMSUB213BF16Z128r", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128r) + .value("VFMSUB213BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128rk) + .value("VFMSUB213BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z128rkz) + .value("VFMSUB213BF16Z256m", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256m) + .value("VFMSUB213BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256mb) + .value("VFMSUB213BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256mbk) + .value("VFMSUB213BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256mbkz) + .value("VFMSUB213BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256mk) + .value("VFMSUB213BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256mkz) + .value("VFMSUB213BF16Z256r", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256r) + .value("VFMSUB213BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256rk) + .value("VFMSUB213BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Z256rkz) + .value("VFMSUB213BF16Zm", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zm) + .value("VFMSUB213BF16Zmb", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zmb) + .value("VFMSUB213BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zmbk) + .value("VFMSUB213BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zmbkz) + .value("VFMSUB213BF16Zmk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zmk) + .value("VFMSUB213BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zmkz) + .value("VFMSUB213BF16Zr", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zr) + .value("VFMSUB213BF16Zrk", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zrk) + .value("VFMSUB213BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMSUB213BF16Zrkz) + .value("VFMSUB213PDYm", LIEF::assembly::x86::OPCODE::VFMSUB213PDYm) + .value("VFMSUB213PDYr", LIEF::assembly::x86::OPCODE::VFMSUB213PDYr) + .value("VFMSUB213PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128m) + .value("VFMSUB213PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128mb) + .value("VFMSUB213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128mbk) + .value("VFMSUB213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128mbkz) + .value("VFMSUB213PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128mk) + .value("VFMSUB213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128mkz) + .value("VFMSUB213PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128r) + .value("VFMSUB213PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128rk) + .value("VFMSUB213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ128rkz) + .value("VFMSUB213PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256m) + .value("VFMSUB213PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256mb) + .value("VFMSUB213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256mbk) + .value("VFMSUB213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256mbkz) + .value("VFMSUB213PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256mk) + .value("VFMSUB213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256mkz) + .value("VFMSUB213PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256r) + .value("VFMSUB213PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256rk) + .value("VFMSUB213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZ256rkz) + .value("VFMSUB213PDZm", LIEF::assembly::x86::OPCODE::VFMSUB213PDZm) + .value("VFMSUB213PDZmb", LIEF::assembly::x86::OPCODE::VFMSUB213PDZmb) + .value("VFMSUB213PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZmbk) + .value("VFMSUB213PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZmbkz) + .value("VFMSUB213PDZmk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZmk) + .value("VFMSUB213PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZmkz) + .value("VFMSUB213PDZr", LIEF::assembly::x86::OPCODE::VFMSUB213PDZr) + .value("VFMSUB213PDZrb", LIEF::assembly::x86::OPCODE::VFMSUB213PDZrb) + .value("VFMSUB213PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZrbk) + .value("VFMSUB213PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZrbkz) + .value("VFMSUB213PDZrk", LIEF::assembly::x86::OPCODE::VFMSUB213PDZrk) + .value("VFMSUB213PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUB213PDZrkz) + .value("VFMSUB213PDm", LIEF::assembly::x86::OPCODE::VFMSUB213PDm) + .value("VFMSUB213PDr", LIEF::assembly::x86::OPCODE::VFMSUB213PDr) + .value("VFMSUB213PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128m) + .value("VFMSUB213PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128mb) + .value("VFMSUB213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128mbk) + .value("VFMSUB213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128mbkz) + .value("VFMSUB213PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128mk) + .value("VFMSUB213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128mkz) + .value("VFMSUB213PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128r) + .value("VFMSUB213PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128rk) + .value("VFMSUB213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ128rkz) + .value("VFMSUB213PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256m) + .value("VFMSUB213PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256mb) + .value("VFMSUB213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256mbk) + .value("VFMSUB213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256mbkz) + .value("VFMSUB213PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256mk) + .value("VFMSUB213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256mkz) + .value("VFMSUB213PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256r) + .value("VFMSUB213PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256rk) + .value("VFMSUB213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZ256rkz) + .value("VFMSUB213PHZm", LIEF::assembly::x86::OPCODE::VFMSUB213PHZm) + .value("VFMSUB213PHZmb", LIEF::assembly::x86::OPCODE::VFMSUB213PHZmb) + .value("VFMSUB213PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZmbk) + .value("VFMSUB213PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZmbkz) + .value("VFMSUB213PHZmk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZmk) + .value("VFMSUB213PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZmkz) + .value("VFMSUB213PHZr", LIEF::assembly::x86::OPCODE::VFMSUB213PHZr) + .value("VFMSUB213PHZrb", LIEF::assembly::x86::OPCODE::VFMSUB213PHZrb) + .value("VFMSUB213PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZrbk) + .value("VFMSUB213PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZrbkz) + .value("VFMSUB213PHZrk", LIEF::assembly::x86::OPCODE::VFMSUB213PHZrk) + .value("VFMSUB213PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUB213PHZrkz) + .value("VFMSUB213PSYm", LIEF::assembly::x86::OPCODE::VFMSUB213PSYm) + .value("VFMSUB213PSYr", LIEF::assembly::x86::OPCODE::VFMSUB213PSYr) + .value("VFMSUB213PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128m) + .value("VFMSUB213PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128mb) + .value("VFMSUB213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128mbk) + .value("VFMSUB213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128mbkz) + .value("VFMSUB213PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128mk) + .value("VFMSUB213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128mkz) + .value("VFMSUB213PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128r) + .value("VFMSUB213PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128rk) + .value("VFMSUB213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ128rkz) + .value("VFMSUB213PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256m) + .value("VFMSUB213PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256mb) + .value("VFMSUB213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256mbk) + .value("VFMSUB213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256mbkz) + .value("VFMSUB213PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256mk) + .value("VFMSUB213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256mkz) + .value("VFMSUB213PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256r) + .value("VFMSUB213PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256rk) + .value("VFMSUB213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZ256rkz) + .value("VFMSUB213PSZm", LIEF::assembly::x86::OPCODE::VFMSUB213PSZm) + .value("VFMSUB213PSZmb", LIEF::assembly::x86::OPCODE::VFMSUB213PSZmb) + .value("VFMSUB213PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZmbk) + .value("VFMSUB213PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZmbkz) + .value("VFMSUB213PSZmk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZmk) + .value("VFMSUB213PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZmkz) + .value("VFMSUB213PSZr", LIEF::assembly::x86::OPCODE::VFMSUB213PSZr) + .value("VFMSUB213PSZrb", LIEF::assembly::x86::OPCODE::VFMSUB213PSZrb) + .value("VFMSUB213PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZrbk) + .value("VFMSUB213PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZrbkz) + .value("VFMSUB213PSZrk", LIEF::assembly::x86::OPCODE::VFMSUB213PSZrk) + .value("VFMSUB213PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUB213PSZrkz) + .value("VFMSUB213PSm", LIEF::assembly::x86::OPCODE::VFMSUB213PSm) + .value("VFMSUB213PSr", LIEF::assembly::x86::OPCODE::VFMSUB213PSr) + .value("VFMSUB213SDZm", LIEF::assembly::x86::OPCODE::VFMSUB213SDZm) + .value("VFMSUB213SDZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZm_Int) + .value("VFMSUB213SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZmk_Int) + .value("VFMSUB213SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZmkz_Int) + .value("VFMSUB213SDZr", LIEF::assembly::x86::OPCODE::VFMSUB213SDZr) + .value("VFMSUB213SDZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZr_Int) + .value("VFMSUB213SDZrb", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrb) + .value("VFMSUB213SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrb_Int) + .value("VFMSUB213SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrbk_Int) + .value("VFMSUB213SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrbkz_Int) + .value("VFMSUB213SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrk_Int) + .value("VFMSUB213SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDZrkz_Int) + .value("VFMSUB213SDm", LIEF::assembly::x86::OPCODE::VFMSUB213SDm) + .value("VFMSUB213SDm_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDm_Int) + .value("VFMSUB213SDr", LIEF::assembly::x86::OPCODE::VFMSUB213SDr) + .value("VFMSUB213SDr_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SDr_Int) + .value("VFMSUB213SHZm", LIEF::assembly::x86::OPCODE::VFMSUB213SHZm) + .value("VFMSUB213SHZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZm_Int) + .value("VFMSUB213SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZmk_Int) + .value("VFMSUB213SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZmkz_Int) + .value("VFMSUB213SHZr", LIEF::assembly::x86::OPCODE::VFMSUB213SHZr) + .value("VFMSUB213SHZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZr_Int) + .value("VFMSUB213SHZrb", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrb) + .value("VFMSUB213SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrb_Int) + .value("VFMSUB213SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrbk_Int); + opcodes.value("VFMSUB213SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrbkz_Int) + .value("VFMSUB213SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrk_Int) + .value("VFMSUB213SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SHZrkz_Int) + .value("VFMSUB213SSZm", LIEF::assembly::x86::OPCODE::VFMSUB213SSZm) + .value("VFMSUB213SSZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZm_Int) + .value("VFMSUB213SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZmk_Int) + .value("VFMSUB213SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZmkz_Int) + .value("VFMSUB213SSZr", LIEF::assembly::x86::OPCODE::VFMSUB213SSZr) + .value("VFMSUB213SSZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZr_Int) + .value("VFMSUB213SSZrb", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrb) + .value("VFMSUB213SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrb_Int) + .value("VFMSUB213SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrbk_Int) + .value("VFMSUB213SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrbkz_Int) + .value("VFMSUB213SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrk_Int) + .value("VFMSUB213SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSZrkz_Int) + .value("VFMSUB213SSm", LIEF::assembly::x86::OPCODE::VFMSUB213SSm) + .value("VFMSUB213SSm_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSm_Int) + .value("VFMSUB213SSr", LIEF::assembly::x86::OPCODE::VFMSUB213SSr) + .value("VFMSUB213SSr_Int", LIEF::assembly::x86::OPCODE::VFMSUB213SSr_Int) + .value("VFMSUB231BF16Z128m", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128m) + .value("VFMSUB231BF16Z128mb", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128mb) + .value("VFMSUB231BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128mbk) + .value("VFMSUB231BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128mbkz) + .value("VFMSUB231BF16Z128mk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128mk) + .value("VFMSUB231BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128mkz) + .value("VFMSUB231BF16Z128r", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128r) + .value("VFMSUB231BF16Z128rk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128rk) + .value("VFMSUB231BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z128rkz) + .value("VFMSUB231BF16Z256m", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256m) + .value("VFMSUB231BF16Z256mb", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256mb) + .value("VFMSUB231BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256mbk) + .value("VFMSUB231BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256mbkz) + .value("VFMSUB231BF16Z256mk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256mk) + .value("VFMSUB231BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256mkz) + .value("VFMSUB231BF16Z256r", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256r) + .value("VFMSUB231BF16Z256rk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256rk) + .value("VFMSUB231BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Z256rkz) + .value("VFMSUB231BF16Zm", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zm) + .value("VFMSUB231BF16Zmb", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zmb) + .value("VFMSUB231BF16Zmbk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zmbk) + .value("VFMSUB231BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zmbkz) + .value("VFMSUB231BF16Zmk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zmk) + .value("VFMSUB231BF16Zmkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zmkz) + .value("VFMSUB231BF16Zr", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zr) + .value("VFMSUB231BF16Zrk", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zrk) + .value("VFMSUB231BF16Zrkz", LIEF::assembly::x86::OPCODE::VFMSUB231BF16Zrkz) + .value("VFMSUB231PDYm", LIEF::assembly::x86::OPCODE::VFMSUB231PDYm) + .value("VFMSUB231PDYr", LIEF::assembly::x86::OPCODE::VFMSUB231PDYr) + .value("VFMSUB231PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128m) + .value("VFMSUB231PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128mb) + .value("VFMSUB231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128mbk) + .value("VFMSUB231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128mbkz) + .value("VFMSUB231PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128mk) + .value("VFMSUB231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128mkz) + .value("VFMSUB231PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128r) + .value("VFMSUB231PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128rk) + .value("VFMSUB231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ128rkz) + .value("VFMSUB231PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256m) + .value("VFMSUB231PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256mb) + .value("VFMSUB231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256mbk) + .value("VFMSUB231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256mbkz) + .value("VFMSUB231PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256mk) + .value("VFMSUB231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256mkz) + .value("VFMSUB231PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256r) + .value("VFMSUB231PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256rk) + .value("VFMSUB231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZ256rkz) + .value("VFMSUB231PDZm", LIEF::assembly::x86::OPCODE::VFMSUB231PDZm) + .value("VFMSUB231PDZmb", LIEF::assembly::x86::OPCODE::VFMSUB231PDZmb) + .value("VFMSUB231PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZmbk) + .value("VFMSUB231PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZmbkz) + .value("VFMSUB231PDZmk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZmk) + .value("VFMSUB231PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZmkz) + .value("VFMSUB231PDZr", LIEF::assembly::x86::OPCODE::VFMSUB231PDZr) + .value("VFMSUB231PDZrb", LIEF::assembly::x86::OPCODE::VFMSUB231PDZrb) + .value("VFMSUB231PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZrbk) + .value("VFMSUB231PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZrbkz) + .value("VFMSUB231PDZrk", LIEF::assembly::x86::OPCODE::VFMSUB231PDZrk) + .value("VFMSUB231PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUB231PDZrkz) + .value("VFMSUB231PDm", LIEF::assembly::x86::OPCODE::VFMSUB231PDm) + .value("VFMSUB231PDr", LIEF::assembly::x86::OPCODE::VFMSUB231PDr) + .value("VFMSUB231PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128m) + .value("VFMSUB231PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128mb) + .value("VFMSUB231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128mbk) + .value("VFMSUB231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128mbkz) + .value("VFMSUB231PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128mk) + .value("VFMSUB231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128mkz) + .value("VFMSUB231PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128r) + .value("VFMSUB231PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128rk) + .value("VFMSUB231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ128rkz) + .value("VFMSUB231PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256m) + .value("VFMSUB231PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256mb) + .value("VFMSUB231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256mbk) + .value("VFMSUB231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256mbkz) + .value("VFMSUB231PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256mk) + .value("VFMSUB231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256mkz) + .value("VFMSUB231PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256r) + .value("VFMSUB231PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256rk) + .value("VFMSUB231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZ256rkz) + .value("VFMSUB231PHZm", LIEF::assembly::x86::OPCODE::VFMSUB231PHZm) + .value("VFMSUB231PHZmb", LIEF::assembly::x86::OPCODE::VFMSUB231PHZmb) + .value("VFMSUB231PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZmbk) + .value("VFMSUB231PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZmbkz) + .value("VFMSUB231PHZmk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZmk) + .value("VFMSUB231PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZmkz) + .value("VFMSUB231PHZr", LIEF::assembly::x86::OPCODE::VFMSUB231PHZr) + .value("VFMSUB231PHZrb", LIEF::assembly::x86::OPCODE::VFMSUB231PHZrb) + .value("VFMSUB231PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZrbk) + .value("VFMSUB231PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZrbkz) + .value("VFMSUB231PHZrk", LIEF::assembly::x86::OPCODE::VFMSUB231PHZrk) + .value("VFMSUB231PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUB231PHZrkz) + .value("VFMSUB231PSYm", LIEF::assembly::x86::OPCODE::VFMSUB231PSYm) + .value("VFMSUB231PSYr", LIEF::assembly::x86::OPCODE::VFMSUB231PSYr) + .value("VFMSUB231PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128m) + .value("VFMSUB231PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128mb) + .value("VFMSUB231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128mbk) + .value("VFMSUB231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128mbkz) + .value("VFMSUB231PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128mk) + .value("VFMSUB231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128mkz) + .value("VFMSUB231PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128r) + .value("VFMSUB231PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128rk) + .value("VFMSUB231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ128rkz) + .value("VFMSUB231PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256m) + .value("VFMSUB231PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256mb) + .value("VFMSUB231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256mbk) + .value("VFMSUB231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256mbkz) + .value("VFMSUB231PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256mk) + .value("VFMSUB231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256mkz) + .value("VFMSUB231PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256r) + .value("VFMSUB231PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256rk) + .value("VFMSUB231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZ256rkz) + .value("VFMSUB231PSZm", LIEF::assembly::x86::OPCODE::VFMSUB231PSZm) + .value("VFMSUB231PSZmb", LIEF::assembly::x86::OPCODE::VFMSUB231PSZmb) + .value("VFMSUB231PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZmbk) + .value("VFMSUB231PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZmbkz) + .value("VFMSUB231PSZmk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZmk) + .value("VFMSUB231PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZmkz) + .value("VFMSUB231PSZr", LIEF::assembly::x86::OPCODE::VFMSUB231PSZr) + .value("VFMSUB231PSZrb", LIEF::assembly::x86::OPCODE::VFMSUB231PSZrb) + .value("VFMSUB231PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZrbk) + .value("VFMSUB231PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZrbkz) + .value("VFMSUB231PSZrk", LIEF::assembly::x86::OPCODE::VFMSUB231PSZrk) + .value("VFMSUB231PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUB231PSZrkz) + .value("VFMSUB231PSm", LIEF::assembly::x86::OPCODE::VFMSUB231PSm) + .value("VFMSUB231PSr", LIEF::assembly::x86::OPCODE::VFMSUB231PSr) + .value("VFMSUB231SDZm", LIEF::assembly::x86::OPCODE::VFMSUB231SDZm) + .value("VFMSUB231SDZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZm_Int) + .value("VFMSUB231SDZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZmk_Int) + .value("VFMSUB231SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZmkz_Int) + .value("VFMSUB231SDZr", LIEF::assembly::x86::OPCODE::VFMSUB231SDZr) + .value("VFMSUB231SDZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZr_Int) + .value("VFMSUB231SDZrb", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrb) + .value("VFMSUB231SDZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrb_Int) + .value("VFMSUB231SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrbk_Int) + .value("VFMSUB231SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrbkz_Int) + .value("VFMSUB231SDZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrk_Int) + .value("VFMSUB231SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDZrkz_Int) + .value("VFMSUB231SDm", LIEF::assembly::x86::OPCODE::VFMSUB231SDm) + .value("VFMSUB231SDm_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDm_Int) + .value("VFMSUB231SDr", LIEF::assembly::x86::OPCODE::VFMSUB231SDr) + .value("VFMSUB231SDr_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SDr_Int) + .value("VFMSUB231SHZm", LIEF::assembly::x86::OPCODE::VFMSUB231SHZm) + .value("VFMSUB231SHZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZm_Int) + .value("VFMSUB231SHZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZmk_Int) + .value("VFMSUB231SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZmkz_Int) + .value("VFMSUB231SHZr", LIEF::assembly::x86::OPCODE::VFMSUB231SHZr) + .value("VFMSUB231SHZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZr_Int) + .value("VFMSUB231SHZrb", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrb) + .value("VFMSUB231SHZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrb_Int) + .value("VFMSUB231SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrbk_Int) + .value("VFMSUB231SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrbkz_Int) + .value("VFMSUB231SHZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrk_Int) + .value("VFMSUB231SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SHZrkz_Int) + .value("VFMSUB231SSZm", LIEF::assembly::x86::OPCODE::VFMSUB231SSZm) + .value("VFMSUB231SSZm_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZm_Int) + .value("VFMSUB231SSZmk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZmk_Int) + .value("VFMSUB231SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZmkz_Int) + .value("VFMSUB231SSZr", LIEF::assembly::x86::OPCODE::VFMSUB231SSZr) + .value("VFMSUB231SSZr_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZr_Int) + .value("VFMSUB231SSZrb", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrb) + .value("VFMSUB231SSZrb_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrb_Int) + .value("VFMSUB231SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrbk_Int) + .value("VFMSUB231SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrbkz_Int) + .value("VFMSUB231SSZrk_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrk_Int) + .value("VFMSUB231SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSZrkz_Int) + .value("VFMSUB231SSm", LIEF::assembly::x86::OPCODE::VFMSUB231SSm) + .value("VFMSUB231SSm_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSm_Int) + .value("VFMSUB231SSr", LIEF::assembly::x86::OPCODE::VFMSUB231SSr) + .value("VFMSUB231SSr_Int", LIEF::assembly::x86::OPCODE::VFMSUB231SSr_Int) + .value("VFMSUBADD132PDYm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDYm) + .value("VFMSUBADD132PDYr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDYr) + .value("VFMSUBADD132PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128m) + .value("VFMSUBADD132PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128mb) + .value("VFMSUBADD132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128mbk) + .value("VFMSUBADD132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128mbkz) + .value("VFMSUBADD132PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128mk) + .value("VFMSUBADD132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128mkz) + .value("VFMSUBADD132PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128r) + .value("VFMSUBADD132PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128rk) + .value("VFMSUBADD132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ128rkz) + .value("VFMSUBADD132PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256m) + .value("VFMSUBADD132PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256mb) + .value("VFMSUBADD132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256mbk) + .value("VFMSUBADD132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256mbkz) + .value("VFMSUBADD132PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256mk) + .value("VFMSUBADD132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256mkz) + .value("VFMSUBADD132PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256r) + .value("VFMSUBADD132PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256rk) + .value("VFMSUBADD132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZ256rkz) + .value("VFMSUBADD132PDZm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZm) + .value("VFMSUBADD132PDZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZmb) + .value("VFMSUBADD132PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZmbk) + .value("VFMSUBADD132PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZmbkz) + .value("VFMSUBADD132PDZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZmk) + .value("VFMSUBADD132PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZmkz) + .value("VFMSUBADD132PDZr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZr) + .value("VFMSUBADD132PDZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZrb) + .value("VFMSUBADD132PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZrbk) + .value("VFMSUBADD132PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZrbkz) + .value("VFMSUBADD132PDZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZrk) + .value("VFMSUBADD132PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDZrkz) + .value("VFMSUBADD132PDm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDm) + .value("VFMSUBADD132PDr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PDr) + .value("VFMSUBADD132PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128m) + .value("VFMSUBADD132PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128mb) + .value("VFMSUBADD132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128mbk) + .value("VFMSUBADD132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128mbkz) + .value("VFMSUBADD132PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128mk) + .value("VFMSUBADD132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128mkz) + .value("VFMSUBADD132PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128r) + .value("VFMSUBADD132PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128rk) + .value("VFMSUBADD132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ128rkz) + .value("VFMSUBADD132PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256m) + .value("VFMSUBADD132PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256mb) + .value("VFMSUBADD132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256mbk) + .value("VFMSUBADD132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256mbkz) + .value("VFMSUBADD132PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256mk) + .value("VFMSUBADD132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256mkz) + .value("VFMSUBADD132PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256r) + .value("VFMSUBADD132PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256rk) + .value("VFMSUBADD132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZ256rkz) + .value("VFMSUBADD132PHZm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZm) + .value("VFMSUBADD132PHZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZmb) + .value("VFMSUBADD132PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZmbk) + .value("VFMSUBADD132PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZmbkz) + .value("VFMSUBADD132PHZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZmk) + .value("VFMSUBADD132PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZmkz) + .value("VFMSUBADD132PHZr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZr) + .value("VFMSUBADD132PHZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZrb) + .value("VFMSUBADD132PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZrbk) + .value("VFMSUBADD132PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZrbkz) + .value("VFMSUBADD132PHZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZrk) + .value("VFMSUBADD132PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PHZrkz) + .value("VFMSUBADD132PSYm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSYm) + .value("VFMSUBADD132PSYr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSYr) + .value("VFMSUBADD132PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128m) + .value("VFMSUBADD132PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128mb) + .value("VFMSUBADD132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128mbk) + .value("VFMSUBADD132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128mbkz) + .value("VFMSUBADD132PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128mk) + .value("VFMSUBADD132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128mkz) + .value("VFMSUBADD132PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128r) + .value("VFMSUBADD132PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128rk) + .value("VFMSUBADD132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ128rkz) + .value("VFMSUBADD132PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256m) + .value("VFMSUBADD132PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256mb) + .value("VFMSUBADD132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256mbk) + .value("VFMSUBADD132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256mbkz) + .value("VFMSUBADD132PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256mk) + .value("VFMSUBADD132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256mkz) + .value("VFMSUBADD132PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256r) + .value("VFMSUBADD132PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256rk) + .value("VFMSUBADD132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZ256rkz) + .value("VFMSUBADD132PSZm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZm) + .value("VFMSUBADD132PSZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZmb) + .value("VFMSUBADD132PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZmbk) + .value("VFMSUBADD132PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZmbkz) + .value("VFMSUBADD132PSZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZmk) + .value("VFMSUBADD132PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZmkz) + .value("VFMSUBADD132PSZr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZr) + .value("VFMSUBADD132PSZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZrb) + .value("VFMSUBADD132PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZrbk) + .value("VFMSUBADD132PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZrbkz) + .value("VFMSUBADD132PSZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZrk) + .value("VFMSUBADD132PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSZrkz) + .value("VFMSUBADD132PSm", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSm) + .value("VFMSUBADD132PSr", LIEF::assembly::x86::OPCODE::VFMSUBADD132PSr) + .value("VFMSUBADD213PDYm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDYm) + .value("VFMSUBADD213PDYr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDYr) + .value("VFMSUBADD213PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128m) + .value("VFMSUBADD213PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128mb) + .value("VFMSUBADD213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128mbk) + .value("VFMSUBADD213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128mbkz) + .value("VFMSUBADD213PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128mk) + .value("VFMSUBADD213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128mkz) + .value("VFMSUBADD213PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128r) + .value("VFMSUBADD213PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128rk) + .value("VFMSUBADD213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ128rkz) + .value("VFMSUBADD213PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256m) + .value("VFMSUBADD213PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256mb) + .value("VFMSUBADD213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256mbk); + opcodes.value("VFMSUBADD213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256mbkz) + .value("VFMSUBADD213PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256mk) + .value("VFMSUBADD213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256mkz) + .value("VFMSUBADD213PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256r) + .value("VFMSUBADD213PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256rk) + .value("VFMSUBADD213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZ256rkz) + .value("VFMSUBADD213PDZm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZm) + .value("VFMSUBADD213PDZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZmb) + .value("VFMSUBADD213PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZmbk) + .value("VFMSUBADD213PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZmbkz) + .value("VFMSUBADD213PDZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZmk) + .value("VFMSUBADD213PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZmkz) + .value("VFMSUBADD213PDZr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZr) + .value("VFMSUBADD213PDZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZrb) + .value("VFMSUBADD213PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZrbk) + .value("VFMSUBADD213PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZrbkz) + .value("VFMSUBADD213PDZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZrk) + .value("VFMSUBADD213PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDZrkz) + .value("VFMSUBADD213PDm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDm) + .value("VFMSUBADD213PDr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PDr) + .value("VFMSUBADD213PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128m) + .value("VFMSUBADD213PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128mb) + .value("VFMSUBADD213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128mbk) + .value("VFMSUBADD213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128mbkz) + .value("VFMSUBADD213PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128mk) + .value("VFMSUBADD213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128mkz) + .value("VFMSUBADD213PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128r) + .value("VFMSUBADD213PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128rk) + .value("VFMSUBADD213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ128rkz) + .value("VFMSUBADD213PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256m) + .value("VFMSUBADD213PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256mb) + .value("VFMSUBADD213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256mbk) + .value("VFMSUBADD213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256mbkz) + .value("VFMSUBADD213PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256mk) + .value("VFMSUBADD213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256mkz) + .value("VFMSUBADD213PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256r) + .value("VFMSUBADD213PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256rk) + .value("VFMSUBADD213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZ256rkz) + .value("VFMSUBADD213PHZm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZm) + .value("VFMSUBADD213PHZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZmb) + .value("VFMSUBADD213PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZmbk) + .value("VFMSUBADD213PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZmbkz) + .value("VFMSUBADD213PHZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZmk) + .value("VFMSUBADD213PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZmkz) + .value("VFMSUBADD213PHZr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZr) + .value("VFMSUBADD213PHZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZrb) + .value("VFMSUBADD213PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZrbk) + .value("VFMSUBADD213PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZrbkz) + .value("VFMSUBADD213PHZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZrk) + .value("VFMSUBADD213PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PHZrkz) + .value("VFMSUBADD213PSYm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSYm) + .value("VFMSUBADD213PSYr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSYr) + .value("VFMSUBADD213PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128m) + .value("VFMSUBADD213PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128mb) + .value("VFMSUBADD213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128mbk) + .value("VFMSUBADD213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128mbkz) + .value("VFMSUBADD213PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128mk) + .value("VFMSUBADD213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128mkz) + .value("VFMSUBADD213PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128r) + .value("VFMSUBADD213PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128rk) + .value("VFMSUBADD213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ128rkz) + .value("VFMSUBADD213PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256m) + .value("VFMSUBADD213PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256mb) + .value("VFMSUBADD213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256mbk) + .value("VFMSUBADD213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256mbkz) + .value("VFMSUBADD213PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256mk) + .value("VFMSUBADD213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256mkz) + .value("VFMSUBADD213PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256r) + .value("VFMSUBADD213PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256rk) + .value("VFMSUBADD213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZ256rkz) + .value("VFMSUBADD213PSZm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZm) + .value("VFMSUBADD213PSZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZmb) + .value("VFMSUBADD213PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZmbk) + .value("VFMSUBADD213PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZmbkz) + .value("VFMSUBADD213PSZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZmk) + .value("VFMSUBADD213PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZmkz) + .value("VFMSUBADD213PSZr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZr) + .value("VFMSUBADD213PSZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZrb) + .value("VFMSUBADD213PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZrbk) + .value("VFMSUBADD213PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZrbkz) + .value("VFMSUBADD213PSZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZrk) + .value("VFMSUBADD213PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSZrkz) + .value("VFMSUBADD213PSm", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSm) + .value("VFMSUBADD213PSr", LIEF::assembly::x86::OPCODE::VFMSUBADD213PSr) + .value("VFMSUBADD231PDYm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDYm) + .value("VFMSUBADD231PDYr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDYr) + .value("VFMSUBADD231PDZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128m) + .value("VFMSUBADD231PDZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128mb) + .value("VFMSUBADD231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128mbk) + .value("VFMSUBADD231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128mbkz) + .value("VFMSUBADD231PDZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128mk) + .value("VFMSUBADD231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128mkz) + .value("VFMSUBADD231PDZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128r) + .value("VFMSUBADD231PDZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128rk) + .value("VFMSUBADD231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ128rkz) + .value("VFMSUBADD231PDZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256m) + .value("VFMSUBADD231PDZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256mb) + .value("VFMSUBADD231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256mbk) + .value("VFMSUBADD231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256mbkz) + .value("VFMSUBADD231PDZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256mk) + .value("VFMSUBADD231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256mkz) + .value("VFMSUBADD231PDZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256r) + .value("VFMSUBADD231PDZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256rk) + .value("VFMSUBADD231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZ256rkz) + .value("VFMSUBADD231PDZm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZm) + .value("VFMSUBADD231PDZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZmb) + .value("VFMSUBADD231PDZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZmbk) + .value("VFMSUBADD231PDZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZmbkz) + .value("VFMSUBADD231PDZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZmk) + .value("VFMSUBADD231PDZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZmkz) + .value("VFMSUBADD231PDZr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZr) + .value("VFMSUBADD231PDZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZrb) + .value("VFMSUBADD231PDZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZrbk) + .value("VFMSUBADD231PDZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZrbkz) + .value("VFMSUBADD231PDZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZrk) + .value("VFMSUBADD231PDZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDZrkz) + .value("VFMSUBADD231PDm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDm) + .value("VFMSUBADD231PDr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PDr) + .value("VFMSUBADD231PHZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128m) + .value("VFMSUBADD231PHZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128mb) + .value("VFMSUBADD231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128mbk) + .value("VFMSUBADD231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128mbkz) + .value("VFMSUBADD231PHZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128mk) + .value("VFMSUBADD231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128mkz) + .value("VFMSUBADD231PHZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128r) + .value("VFMSUBADD231PHZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128rk) + .value("VFMSUBADD231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ128rkz) + .value("VFMSUBADD231PHZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256m) + .value("VFMSUBADD231PHZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256mb) + .value("VFMSUBADD231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256mbk) + .value("VFMSUBADD231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256mbkz) + .value("VFMSUBADD231PHZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256mk) + .value("VFMSUBADD231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256mkz) + .value("VFMSUBADD231PHZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256r) + .value("VFMSUBADD231PHZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256rk) + .value("VFMSUBADD231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZ256rkz) + .value("VFMSUBADD231PHZm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZm) + .value("VFMSUBADD231PHZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZmb) + .value("VFMSUBADD231PHZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZmbk) + .value("VFMSUBADD231PHZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZmbkz) + .value("VFMSUBADD231PHZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZmk) + .value("VFMSUBADD231PHZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZmkz) + .value("VFMSUBADD231PHZr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZr) + .value("VFMSUBADD231PHZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZrb) + .value("VFMSUBADD231PHZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZrbk) + .value("VFMSUBADD231PHZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZrbkz) + .value("VFMSUBADD231PHZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZrk) + .value("VFMSUBADD231PHZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PHZrkz) + .value("VFMSUBADD231PSYm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSYm) + .value("VFMSUBADD231PSYr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSYr) + .value("VFMSUBADD231PSZ128m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128m) + .value("VFMSUBADD231PSZ128mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128mb) + .value("VFMSUBADD231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128mbk) + .value("VFMSUBADD231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128mbkz) + .value("VFMSUBADD231PSZ128mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128mk) + .value("VFMSUBADD231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128mkz) + .value("VFMSUBADD231PSZ128r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128r) + .value("VFMSUBADD231PSZ128rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128rk) + .value("VFMSUBADD231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ128rkz) + .value("VFMSUBADD231PSZ256m", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256m) + .value("VFMSUBADD231PSZ256mb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256mb) + .value("VFMSUBADD231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256mbk) + .value("VFMSUBADD231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256mbkz) + .value("VFMSUBADD231PSZ256mk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256mk) + .value("VFMSUBADD231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256mkz) + .value("VFMSUBADD231PSZ256r", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256r) + .value("VFMSUBADD231PSZ256rk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256rk) + .value("VFMSUBADD231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZ256rkz) + .value("VFMSUBADD231PSZm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZm) + .value("VFMSUBADD231PSZmb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZmb) + .value("VFMSUBADD231PSZmbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZmbk) + .value("VFMSUBADD231PSZmbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZmbkz) + .value("VFMSUBADD231PSZmk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZmk) + .value("VFMSUBADD231PSZmkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZmkz) + .value("VFMSUBADD231PSZr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZr) + .value("VFMSUBADD231PSZrb", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZrb) + .value("VFMSUBADD231PSZrbk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZrbk) + .value("VFMSUBADD231PSZrbkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZrbkz) + .value("VFMSUBADD231PSZrk", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZrk) + .value("VFMSUBADD231PSZrkz", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSZrkz) + .value("VFMSUBADD231PSm", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSm) + .value("VFMSUBADD231PSr", LIEF::assembly::x86::OPCODE::VFMSUBADD231PSr) + .value("VFMSUBADDPD4Ymr", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4Ymr) + .value("VFMSUBADDPD4Yrm", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4Yrm) + .value("VFMSUBADDPD4Yrr", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4Yrr) + .value("VFMSUBADDPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4Yrr_REV) + .value("VFMSUBADDPD4mr", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4mr) + .value("VFMSUBADDPD4rm", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4rm) + .value("VFMSUBADDPD4rr", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4rr) + .value("VFMSUBADDPD4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBADDPD4rr_REV) + .value("VFMSUBADDPS4Ymr", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4Ymr) + .value("VFMSUBADDPS4Yrm", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4Yrm) + .value("VFMSUBADDPS4Yrr", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4Yrr) + .value("VFMSUBADDPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4Yrr_REV) + .value("VFMSUBADDPS4mr", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4mr) + .value("VFMSUBADDPS4rm", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4rm) + .value("VFMSUBADDPS4rr", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4rr) + .value("VFMSUBADDPS4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBADDPS4rr_REV) + .value("VFMSUBPD4Ymr", LIEF::assembly::x86::OPCODE::VFMSUBPD4Ymr) + .value("VFMSUBPD4Yrm", LIEF::assembly::x86::OPCODE::VFMSUBPD4Yrm) + .value("VFMSUBPD4Yrr", LIEF::assembly::x86::OPCODE::VFMSUBPD4Yrr) + .value("VFMSUBPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMSUBPD4Yrr_REV) + .value("VFMSUBPD4mr", LIEF::assembly::x86::OPCODE::VFMSUBPD4mr) + .value("VFMSUBPD4rm", LIEF::assembly::x86::OPCODE::VFMSUBPD4rm) + .value("VFMSUBPD4rr", LIEF::assembly::x86::OPCODE::VFMSUBPD4rr) + .value("VFMSUBPD4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBPD4rr_REV) + .value("VFMSUBPS4Ymr", LIEF::assembly::x86::OPCODE::VFMSUBPS4Ymr) + .value("VFMSUBPS4Yrm", LIEF::assembly::x86::OPCODE::VFMSUBPS4Yrm) + .value("VFMSUBPS4Yrr", LIEF::assembly::x86::OPCODE::VFMSUBPS4Yrr) + .value("VFMSUBPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFMSUBPS4Yrr_REV) + .value("VFMSUBPS4mr", LIEF::assembly::x86::OPCODE::VFMSUBPS4mr) + .value("VFMSUBPS4rm", LIEF::assembly::x86::OPCODE::VFMSUBPS4rm) + .value("VFMSUBPS4rr", LIEF::assembly::x86::OPCODE::VFMSUBPS4rr) + .value("VFMSUBPS4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBPS4rr_REV) + .value("VFMSUBSD4mr", LIEF::assembly::x86::OPCODE::VFMSUBSD4mr) + .value("VFMSUBSD4mr_Int", LIEF::assembly::x86::OPCODE::VFMSUBSD4mr_Int) + .value("VFMSUBSD4rm", LIEF::assembly::x86::OPCODE::VFMSUBSD4rm) + .value("VFMSUBSD4rm_Int", LIEF::assembly::x86::OPCODE::VFMSUBSD4rm_Int) + .value("VFMSUBSD4rr", LIEF::assembly::x86::OPCODE::VFMSUBSD4rr) + .value("VFMSUBSD4rr_Int", LIEF::assembly::x86::OPCODE::VFMSUBSD4rr_Int) + .value("VFMSUBSD4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFMSUBSD4rr_Int_REV) + .value("VFMSUBSD4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBSD4rr_REV) + .value("VFMSUBSS4mr", LIEF::assembly::x86::OPCODE::VFMSUBSS4mr) + .value("VFMSUBSS4mr_Int", LIEF::assembly::x86::OPCODE::VFMSUBSS4mr_Int) + .value("VFMSUBSS4rm", LIEF::assembly::x86::OPCODE::VFMSUBSS4rm) + .value("VFMSUBSS4rm_Int", LIEF::assembly::x86::OPCODE::VFMSUBSS4rm_Int) + .value("VFMSUBSS4rr", LIEF::assembly::x86::OPCODE::VFMSUBSS4rr) + .value("VFMSUBSS4rr_Int", LIEF::assembly::x86::OPCODE::VFMSUBSS4rr_Int) + .value("VFMSUBSS4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFMSUBSS4rr_Int_REV) + .value("VFMSUBSS4rr_REV", LIEF::assembly::x86::OPCODE::VFMSUBSS4rr_REV) + .value("VFMULCPHZ128rm", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rm) + .value("VFMULCPHZ128rmb", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rmb) + .value("VFMULCPHZ128rmbk", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rmbk) + .value("VFMULCPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rmbkz) + .value("VFMULCPHZ128rmk", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rmk) + .value("VFMULCPHZ128rmkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rmkz) + .value("VFMULCPHZ128rr", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rr) + .value("VFMULCPHZ128rrk", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rrk) + .value("VFMULCPHZ128rrkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ128rrkz) + .value("VFMULCPHZ256rm", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rm) + .value("VFMULCPHZ256rmb", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rmb) + .value("VFMULCPHZ256rmbk", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rmbk) + .value("VFMULCPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rmbkz) + .value("VFMULCPHZ256rmk", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rmk) + .value("VFMULCPHZ256rmkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rmkz) + .value("VFMULCPHZ256rr", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rr) + .value("VFMULCPHZ256rrk", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rrk) + .value("VFMULCPHZ256rrkz", LIEF::assembly::x86::OPCODE::VFMULCPHZ256rrkz) + .value("VFMULCPHZrm", LIEF::assembly::x86::OPCODE::VFMULCPHZrm) + .value("VFMULCPHZrmb", LIEF::assembly::x86::OPCODE::VFMULCPHZrmb) + .value("VFMULCPHZrmbk", LIEF::assembly::x86::OPCODE::VFMULCPHZrmbk) + .value("VFMULCPHZrmbkz", LIEF::assembly::x86::OPCODE::VFMULCPHZrmbkz) + .value("VFMULCPHZrmk", LIEF::assembly::x86::OPCODE::VFMULCPHZrmk) + .value("VFMULCPHZrmkz", LIEF::assembly::x86::OPCODE::VFMULCPHZrmkz) + .value("VFMULCPHZrr", LIEF::assembly::x86::OPCODE::VFMULCPHZrr) + .value("VFMULCPHZrrb", LIEF::assembly::x86::OPCODE::VFMULCPHZrrb) + .value("VFMULCPHZrrbk", LIEF::assembly::x86::OPCODE::VFMULCPHZrrbk) + .value("VFMULCPHZrrbkz", LIEF::assembly::x86::OPCODE::VFMULCPHZrrbkz) + .value("VFMULCPHZrrk", LIEF::assembly::x86::OPCODE::VFMULCPHZrrk) + .value("VFMULCPHZrrkz", LIEF::assembly::x86::OPCODE::VFMULCPHZrrkz) + .value("VFMULCSHZrm", LIEF::assembly::x86::OPCODE::VFMULCSHZrm) + .value("VFMULCSHZrmk", LIEF::assembly::x86::OPCODE::VFMULCSHZrmk) + .value("VFMULCSHZrmkz", LIEF::assembly::x86::OPCODE::VFMULCSHZrmkz) + .value("VFMULCSHZrr", LIEF::assembly::x86::OPCODE::VFMULCSHZrr) + .value("VFMULCSHZrrb", LIEF::assembly::x86::OPCODE::VFMULCSHZrrb) + .value("VFMULCSHZrrbk", LIEF::assembly::x86::OPCODE::VFMULCSHZrrbk) + .value("VFMULCSHZrrbkz", LIEF::assembly::x86::OPCODE::VFMULCSHZrrbkz) + .value("VFMULCSHZrrk", LIEF::assembly::x86::OPCODE::VFMULCSHZrrk) + .value("VFMULCSHZrrkz", LIEF::assembly::x86::OPCODE::VFMULCSHZrrkz) + .value("VFNMADD132BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128m) + .value("VFNMADD132BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128mb) + .value("VFNMADD132BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128mbk) + .value("VFNMADD132BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128mbkz) + .value("VFNMADD132BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128mk) + .value("VFNMADD132BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128mkz) + .value("VFNMADD132BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128r) + .value("VFNMADD132BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128rk) + .value("VFNMADD132BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z128rkz) + .value("VFNMADD132BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256m) + .value("VFNMADD132BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256mb) + .value("VFNMADD132BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256mbk) + .value("VFNMADD132BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256mbkz) + .value("VFNMADD132BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256mk) + .value("VFNMADD132BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256mkz) + .value("VFNMADD132BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256r) + .value("VFNMADD132BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256rk) + .value("VFNMADD132BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Z256rkz) + .value("VFNMADD132BF16Zm", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zm) + .value("VFNMADD132BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zmb) + .value("VFNMADD132BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zmbk) + .value("VFNMADD132BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zmbkz) + .value("VFNMADD132BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zmk) + .value("VFNMADD132BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zmkz) + .value("VFNMADD132BF16Zr", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zr) + .value("VFNMADD132BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zrk) + .value("VFNMADD132BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMADD132BF16Zrkz) + .value("VFNMADD132PDYm", LIEF::assembly::x86::OPCODE::VFNMADD132PDYm) + .value("VFNMADD132PDYr", LIEF::assembly::x86::OPCODE::VFNMADD132PDYr) + .value("VFNMADD132PDZ128m", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128m) + .value("VFNMADD132PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128mb); + opcodes.value("VFNMADD132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128mbk) + .value("VFNMADD132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128mbkz) + .value("VFNMADD132PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128mk) + .value("VFNMADD132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128mkz) + .value("VFNMADD132PDZ128r", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128r) + .value("VFNMADD132PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128rk) + .value("VFNMADD132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ128rkz) + .value("VFNMADD132PDZ256m", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256m) + .value("VFNMADD132PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256mb) + .value("VFNMADD132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256mbk) + .value("VFNMADD132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256mbkz) + .value("VFNMADD132PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256mk) + .value("VFNMADD132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256mkz) + .value("VFNMADD132PDZ256r", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256r) + .value("VFNMADD132PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256rk) + .value("VFNMADD132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZ256rkz) + .value("VFNMADD132PDZm", LIEF::assembly::x86::OPCODE::VFNMADD132PDZm) + .value("VFNMADD132PDZmb", LIEF::assembly::x86::OPCODE::VFNMADD132PDZmb) + .value("VFNMADD132PDZmbk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZmbk) + .value("VFNMADD132PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZmbkz) + .value("VFNMADD132PDZmk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZmk) + .value("VFNMADD132PDZmkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZmkz) + .value("VFNMADD132PDZr", LIEF::assembly::x86::OPCODE::VFNMADD132PDZr) + .value("VFNMADD132PDZrb", LIEF::assembly::x86::OPCODE::VFNMADD132PDZrb) + .value("VFNMADD132PDZrbk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZrbk) + .value("VFNMADD132PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZrbkz) + .value("VFNMADD132PDZrk", LIEF::assembly::x86::OPCODE::VFNMADD132PDZrk) + .value("VFNMADD132PDZrkz", LIEF::assembly::x86::OPCODE::VFNMADD132PDZrkz) + .value("VFNMADD132PDm", LIEF::assembly::x86::OPCODE::VFNMADD132PDm) + .value("VFNMADD132PDr", LIEF::assembly::x86::OPCODE::VFNMADD132PDr) + .value("VFNMADD132PHZ128m", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128m) + .value("VFNMADD132PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128mb) + .value("VFNMADD132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128mbk) + .value("VFNMADD132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128mbkz) + .value("VFNMADD132PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128mk) + .value("VFNMADD132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128mkz) + .value("VFNMADD132PHZ128r", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128r) + .value("VFNMADD132PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128rk) + .value("VFNMADD132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ128rkz) + .value("VFNMADD132PHZ256m", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256m) + .value("VFNMADD132PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256mb) + .value("VFNMADD132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256mbk) + .value("VFNMADD132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256mbkz) + .value("VFNMADD132PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256mk) + .value("VFNMADD132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256mkz) + .value("VFNMADD132PHZ256r", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256r) + .value("VFNMADD132PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256rk) + .value("VFNMADD132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZ256rkz) + .value("VFNMADD132PHZm", LIEF::assembly::x86::OPCODE::VFNMADD132PHZm) + .value("VFNMADD132PHZmb", LIEF::assembly::x86::OPCODE::VFNMADD132PHZmb) + .value("VFNMADD132PHZmbk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZmbk) + .value("VFNMADD132PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZmbkz) + .value("VFNMADD132PHZmk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZmk) + .value("VFNMADD132PHZmkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZmkz) + .value("VFNMADD132PHZr", LIEF::assembly::x86::OPCODE::VFNMADD132PHZr) + .value("VFNMADD132PHZrb", LIEF::assembly::x86::OPCODE::VFNMADD132PHZrb) + .value("VFNMADD132PHZrbk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZrbk) + .value("VFNMADD132PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZrbkz) + .value("VFNMADD132PHZrk", LIEF::assembly::x86::OPCODE::VFNMADD132PHZrk) + .value("VFNMADD132PHZrkz", LIEF::assembly::x86::OPCODE::VFNMADD132PHZrkz) + .value("VFNMADD132PSYm", LIEF::assembly::x86::OPCODE::VFNMADD132PSYm) + .value("VFNMADD132PSYr", LIEF::assembly::x86::OPCODE::VFNMADD132PSYr) + .value("VFNMADD132PSZ128m", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128m) + .value("VFNMADD132PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128mb) + .value("VFNMADD132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128mbk) + .value("VFNMADD132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128mbkz) + .value("VFNMADD132PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128mk) + .value("VFNMADD132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128mkz) + .value("VFNMADD132PSZ128r", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128r) + .value("VFNMADD132PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128rk) + .value("VFNMADD132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ128rkz) + .value("VFNMADD132PSZ256m", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256m) + .value("VFNMADD132PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256mb) + .value("VFNMADD132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256mbk) + .value("VFNMADD132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256mbkz) + .value("VFNMADD132PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256mk) + .value("VFNMADD132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256mkz) + .value("VFNMADD132PSZ256r", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256r) + .value("VFNMADD132PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256rk) + .value("VFNMADD132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZ256rkz) + .value("VFNMADD132PSZm", LIEF::assembly::x86::OPCODE::VFNMADD132PSZm) + .value("VFNMADD132PSZmb", LIEF::assembly::x86::OPCODE::VFNMADD132PSZmb) + .value("VFNMADD132PSZmbk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZmbk) + .value("VFNMADD132PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZmbkz) + .value("VFNMADD132PSZmk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZmk) + .value("VFNMADD132PSZmkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZmkz) + .value("VFNMADD132PSZr", LIEF::assembly::x86::OPCODE::VFNMADD132PSZr) + .value("VFNMADD132PSZrb", LIEF::assembly::x86::OPCODE::VFNMADD132PSZrb) + .value("VFNMADD132PSZrbk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZrbk) + .value("VFNMADD132PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZrbkz) + .value("VFNMADD132PSZrk", LIEF::assembly::x86::OPCODE::VFNMADD132PSZrk) + .value("VFNMADD132PSZrkz", LIEF::assembly::x86::OPCODE::VFNMADD132PSZrkz) + .value("VFNMADD132PSm", LIEF::assembly::x86::OPCODE::VFNMADD132PSm) + .value("VFNMADD132PSr", LIEF::assembly::x86::OPCODE::VFNMADD132PSr) + .value("VFNMADD132SDZm", LIEF::assembly::x86::OPCODE::VFNMADD132SDZm) + .value("VFNMADD132SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZm_Int) + .value("VFNMADD132SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZmk_Int) + .value("VFNMADD132SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZmkz_Int) + .value("VFNMADD132SDZr", LIEF::assembly::x86::OPCODE::VFNMADD132SDZr) + .value("VFNMADD132SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZr_Int) + .value("VFNMADD132SDZrb", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrb) + .value("VFNMADD132SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrb_Int) + .value("VFNMADD132SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrbk_Int) + .value("VFNMADD132SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrbkz_Int) + .value("VFNMADD132SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrk_Int) + .value("VFNMADD132SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDZrkz_Int) + .value("VFNMADD132SDm", LIEF::assembly::x86::OPCODE::VFNMADD132SDm) + .value("VFNMADD132SDm_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDm_Int) + .value("VFNMADD132SDr", LIEF::assembly::x86::OPCODE::VFNMADD132SDr) + .value("VFNMADD132SDr_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SDr_Int) + .value("VFNMADD132SHZm", LIEF::assembly::x86::OPCODE::VFNMADD132SHZm) + .value("VFNMADD132SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZm_Int) + .value("VFNMADD132SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZmk_Int) + .value("VFNMADD132SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZmkz_Int) + .value("VFNMADD132SHZr", LIEF::assembly::x86::OPCODE::VFNMADD132SHZr) + .value("VFNMADD132SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZr_Int) + .value("VFNMADD132SHZrb", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrb) + .value("VFNMADD132SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrb_Int) + .value("VFNMADD132SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrbk_Int) + .value("VFNMADD132SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrbkz_Int) + .value("VFNMADD132SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrk_Int) + .value("VFNMADD132SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SHZrkz_Int) + .value("VFNMADD132SSZm", LIEF::assembly::x86::OPCODE::VFNMADD132SSZm) + .value("VFNMADD132SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZm_Int) + .value("VFNMADD132SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZmk_Int) + .value("VFNMADD132SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZmkz_Int) + .value("VFNMADD132SSZr", LIEF::assembly::x86::OPCODE::VFNMADD132SSZr) + .value("VFNMADD132SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZr_Int) + .value("VFNMADD132SSZrb", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrb) + .value("VFNMADD132SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrb_Int) + .value("VFNMADD132SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrbk_Int) + .value("VFNMADD132SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrbkz_Int) + .value("VFNMADD132SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrk_Int) + .value("VFNMADD132SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSZrkz_Int) + .value("VFNMADD132SSm", LIEF::assembly::x86::OPCODE::VFNMADD132SSm) + .value("VFNMADD132SSm_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSm_Int) + .value("VFNMADD132SSr", LIEF::assembly::x86::OPCODE::VFNMADD132SSr) + .value("VFNMADD132SSr_Int", LIEF::assembly::x86::OPCODE::VFNMADD132SSr_Int) + .value("VFNMADD213BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128m) + .value("VFNMADD213BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128mb) + .value("VFNMADD213BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128mbk) + .value("VFNMADD213BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128mbkz) + .value("VFNMADD213BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128mk) + .value("VFNMADD213BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128mkz) + .value("VFNMADD213BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128r) + .value("VFNMADD213BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128rk) + .value("VFNMADD213BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z128rkz) + .value("VFNMADD213BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256m) + .value("VFNMADD213BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256mb) + .value("VFNMADD213BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256mbk) + .value("VFNMADD213BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256mbkz) + .value("VFNMADD213BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256mk) + .value("VFNMADD213BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256mkz) + .value("VFNMADD213BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256r) + .value("VFNMADD213BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256rk) + .value("VFNMADD213BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Z256rkz) + .value("VFNMADD213BF16Zm", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zm) + .value("VFNMADD213BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zmb) + .value("VFNMADD213BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zmbk) + .value("VFNMADD213BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zmbkz) + .value("VFNMADD213BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zmk) + .value("VFNMADD213BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zmkz) + .value("VFNMADD213BF16Zr", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zr) + .value("VFNMADD213BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zrk) + .value("VFNMADD213BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMADD213BF16Zrkz) + .value("VFNMADD213PDYm", LIEF::assembly::x86::OPCODE::VFNMADD213PDYm) + .value("VFNMADD213PDYr", LIEF::assembly::x86::OPCODE::VFNMADD213PDYr) + .value("VFNMADD213PDZ128m", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128m) + .value("VFNMADD213PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128mb) + .value("VFNMADD213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128mbk) + .value("VFNMADD213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128mbkz) + .value("VFNMADD213PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128mk) + .value("VFNMADD213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128mkz) + .value("VFNMADD213PDZ128r", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128r) + .value("VFNMADD213PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128rk) + .value("VFNMADD213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ128rkz) + .value("VFNMADD213PDZ256m", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256m) + .value("VFNMADD213PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256mb) + .value("VFNMADD213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256mbk) + .value("VFNMADD213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256mbkz) + .value("VFNMADD213PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256mk) + .value("VFNMADD213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256mkz) + .value("VFNMADD213PDZ256r", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256r) + .value("VFNMADD213PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256rk) + .value("VFNMADD213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZ256rkz) + .value("VFNMADD213PDZm", LIEF::assembly::x86::OPCODE::VFNMADD213PDZm) + .value("VFNMADD213PDZmb", LIEF::assembly::x86::OPCODE::VFNMADD213PDZmb) + .value("VFNMADD213PDZmbk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZmbk) + .value("VFNMADD213PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZmbkz) + .value("VFNMADD213PDZmk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZmk) + .value("VFNMADD213PDZmkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZmkz) + .value("VFNMADD213PDZr", LIEF::assembly::x86::OPCODE::VFNMADD213PDZr) + .value("VFNMADD213PDZrb", LIEF::assembly::x86::OPCODE::VFNMADD213PDZrb) + .value("VFNMADD213PDZrbk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZrbk) + .value("VFNMADD213PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZrbkz) + .value("VFNMADD213PDZrk", LIEF::assembly::x86::OPCODE::VFNMADD213PDZrk) + .value("VFNMADD213PDZrkz", LIEF::assembly::x86::OPCODE::VFNMADD213PDZrkz) + .value("VFNMADD213PDm", LIEF::assembly::x86::OPCODE::VFNMADD213PDm) + .value("VFNMADD213PDr", LIEF::assembly::x86::OPCODE::VFNMADD213PDr) + .value("VFNMADD213PHZ128m", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128m) + .value("VFNMADD213PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128mb) + .value("VFNMADD213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128mbk) + .value("VFNMADD213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128mbkz) + .value("VFNMADD213PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128mk) + .value("VFNMADD213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128mkz) + .value("VFNMADD213PHZ128r", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128r) + .value("VFNMADD213PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128rk) + .value("VFNMADD213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ128rkz) + .value("VFNMADD213PHZ256m", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256m) + .value("VFNMADD213PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256mb) + .value("VFNMADD213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256mbk) + .value("VFNMADD213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256mbkz) + .value("VFNMADD213PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256mk) + .value("VFNMADD213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256mkz) + .value("VFNMADD213PHZ256r", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256r) + .value("VFNMADD213PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256rk) + .value("VFNMADD213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZ256rkz) + .value("VFNMADD213PHZm", LIEF::assembly::x86::OPCODE::VFNMADD213PHZm) + .value("VFNMADD213PHZmb", LIEF::assembly::x86::OPCODE::VFNMADD213PHZmb) + .value("VFNMADD213PHZmbk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZmbk) + .value("VFNMADD213PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZmbkz) + .value("VFNMADD213PHZmk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZmk) + .value("VFNMADD213PHZmkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZmkz) + .value("VFNMADD213PHZr", LIEF::assembly::x86::OPCODE::VFNMADD213PHZr) + .value("VFNMADD213PHZrb", LIEF::assembly::x86::OPCODE::VFNMADD213PHZrb) + .value("VFNMADD213PHZrbk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZrbk) + .value("VFNMADD213PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZrbkz) + .value("VFNMADD213PHZrk", LIEF::assembly::x86::OPCODE::VFNMADD213PHZrk) + .value("VFNMADD213PHZrkz", LIEF::assembly::x86::OPCODE::VFNMADD213PHZrkz) + .value("VFNMADD213PSYm", LIEF::assembly::x86::OPCODE::VFNMADD213PSYm) + .value("VFNMADD213PSYr", LIEF::assembly::x86::OPCODE::VFNMADD213PSYr) + .value("VFNMADD213PSZ128m", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128m) + .value("VFNMADD213PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128mb) + .value("VFNMADD213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128mbk) + .value("VFNMADD213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128mbkz) + .value("VFNMADD213PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128mk) + .value("VFNMADD213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128mkz) + .value("VFNMADD213PSZ128r", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128r) + .value("VFNMADD213PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128rk) + .value("VFNMADD213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ128rkz) + .value("VFNMADD213PSZ256m", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256m) + .value("VFNMADD213PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256mb) + .value("VFNMADD213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256mbk) + .value("VFNMADD213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256mbkz) + .value("VFNMADD213PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256mk) + .value("VFNMADD213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256mkz) + .value("VFNMADD213PSZ256r", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256r) + .value("VFNMADD213PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256rk) + .value("VFNMADD213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZ256rkz) + .value("VFNMADD213PSZm", LIEF::assembly::x86::OPCODE::VFNMADD213PSZm) + .value("VFNMADD213PSZmb", LIEF::assembly::x86::OPCODE::VFNMADD213PSZmb) + .value("VFNMADD213PSZmbk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZmbk) + .value("VFNMADD213PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZmbkz) + .value("VFNMADD213PSZmk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZmk) + .value("VFNMADD213PSZmkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZmkz) + .value("VFNMADD213PSZr", LIEF::assembly::x86::OPCODE::VFNMADD213PSZr) + .value("VFNMADD213PSZrb", LIEF::assembly::x86::OPCODE::VFNMADD213PSZrb) + .value("VFNMADD213PSZrbk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZrbk) + .value("VFNMADD213PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZrbkz) + .value("VFNMADD213PSZrk", LIEF::assembly::x86::OPCODE::VFNMADD213PSZrk) + .value("VFNMADD213PSZrkz", LIEF::assembly::x86::OPCODE::VFNMADD213PSZrkz) + .value("VFNMADD213PSm", LIEF::assembly::x86::OPCODE::VFNMADD213PSm) + .value("VFNMADD213PSr", LIEF::assembly::x86::OPCODE::VFNMADD213PSr) + .value("VFNMADD213SDZm", LIEF::assembly::x86::OPCODE::VFNMADD213SDZm) + .value("VFNMADD213SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZm_Int) + .value("VFNMADD213SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZmk_Int) + .value("VFNMADD213SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZmkz_Int) + .value("VFNMADD213SDZr", LIEF::assembly::x86::OPCODE::VFNMADD213SDZr) + .value("VFNMADD213SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZr_Int) + .value("VFNMADD213SDZrb", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrb) + .value("VFNMADD213SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrb_Int) + .value("VFNMADD213SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrbk_Int) + .value("VFNMADD213SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrbkz_Int) + .value("VFNMADD213SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrk_Int) + .value("VFNMADD213SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDZrkz_Int) + .value("VFNMADD213SDm", LIEF::assembly::x86::OPCODE::VFNMADD213SDm) + .value("VFNMADD213SDm_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDm_Int) + .value("VFNMADD213SDr", LIEF::assembly::x86::OPCODE::VFNMADD213SDr) + .value("VFNMADD213SDr_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SDr_Int) + .value("VFNMADD213SHZm", LIEF::assembly::x86::OPCODE::VFNMADD213SHZm) + .value("VFNMADD213SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZm_Int) + .value("VFNMADD213SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZmk_Int) + .value("VFNMADD213SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZmkz_Int) + .value("VFNMADD213SHZr", LIEF::assembly::x86::OPCODE::VFNMADD213SHZr) + .value("VFNMADD213SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZr_Int) + .value("VFNMADD213SHZrb", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrb) + .value("VFNMADD213SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrb_Int) + .value("VFNMADD213SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrbk_Int) + .value("VFNMADD213SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrbkz_Int) + .value("VFNMADD213SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrk_Int) + .value("VFNMADD213SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SHZrkz_Int) + .value("VFNMADD213SSZm", LIEF::assembly::x86::OPCODE::VFNMADD213SSZm) + .value("VFNMADD213SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZm_Int) + .value("VFNMADD213SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZmk_Int) + .value("VFNMADD213SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZmkz_Int) + .value("VFNMADD213SSZr", LIEF::assembly::x86::OPCODE::VFNMADD213SSZr) + .value("VFNMADD213SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZr_Int) + .value("VFNMADD213SSZrb", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrb) + .value("VFNMADD213SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrb_Int) + .value("VFNMADD213SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrbk_Int); + opcodes.value("VFNMADD213SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrbkz_Int) + .value("VFNMADD213SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrk_Int) + .value("VFNMADD213SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSZrkz_Int) + .value("VFNMADD213SSm", LIEF::assembly::x86::OPCODE::VFNMADD213SSm) + .value("VFNMADD213SSm_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSm_Int) + .value("VFNMADD213SSr", LIEF::assembly::x86::OPCODE::VFNMADD213SSr) + .value("VFNMADD213SSr_Int", LIEF::assembly::x86::OPCODE::VFNMADD213SSr_Int) + .value("VFNMADD231BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128m) + .value("VFNMADD231BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128mb) + .value("VFNMADD231BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128mbk) + .value("VFNMADD231BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128mbkz) + .value("VFNMADD231BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128mk) + .value("VFNMADD231BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128mkz) + .value("VFNMADD231BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128r) + .value("VFNMADD231BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128rk) + .value("VFNMADD231BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z128rkz) + .value("VFNMADD231BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256m) + .value("VFNMADD231BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256mb) + .value("VFNMADD231BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256mbk) + .value("VFNMADD231BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256mbkz) + .value("VFNMADD231BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256mk) + .value("VFNMADD231BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256mkz) + .value("VFNMADD231BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256r) + .value("VFNMADD231BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256rk) + .value("VFNMADD231BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Z256rkz) + .value("VFNMADD231BF16Zm", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zm) + .value("VFNMADD231BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zmb) + .value("VFNMADD231BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zmbk) + .value("VFNMADD231BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zmbkz) + .value("VFNMADD231BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zmk) + .value("VFNMADD231BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zmkz) + .value("VFNMADD231BF16Zr", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zr) + .value("VFNMADD231BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zrk) + .value("VFNMADD231BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMADD231BF16Zrkz) + .value("VFNMADD231PDYm", LIEF::assembly::x86::OPCODE::VFNMADD231PDYm) + .value("VFNMADD231PDYr", LIEF::assembly::x86::OPCODE::VFNMADD231PDYr) + .value("VFNMADD231PDZ128m", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128m) + .value("VFNMADD231PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128mb) + .value("VFNMADD231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128mbk) + .value("VFNMADD231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128mbkz) + .value("VFNMADD231PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128mk) + .value("VFNMADD231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128mkz) + .value("VFNMADD231PDZ128r", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128r) + .value("VFNMADD231PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128rk) + .value("VFNMADD231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ128rkz) + .value("VFNMADD231PDZ256m", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256m) + .value("VFNMADD231PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256mb) + .value("VFNMADD231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256mbk) + .value("VFNMADD231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256mbkz) + .value("VFNMADD231PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256mk) + .value("VFNMADD231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256mkz) + .value("VFNMADD231PDZ256r", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256r) + .value("VFNMADD231PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256rk) + .value("VFNMADD231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZ256rkz) + .value("VFNMADD231PDZm", LIEF::assembly::x86::OPCODE::VFNMADD231PDZm) + .value("VFNMADD231PDZmb", LIEF::assembly::x86::OPCODE::VFNMADD231PDZmb) + .value("VFNMADD231PDZmbk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZmbk) + .value("VFNMADD231PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZmbkz) + .value("VFNMADD231PDZmk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZmk) + .value("VFNMADD231PDZmkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZmkz) + .value("VFNMADD231PDZr", LIEF::assembly::x86::OPCODE::VFNMADD231PDZr) + .value("VFNMADD231PDZrb", LIEF::assembly::x86::OPCODE::VFNMADD231PDZrb) + .value("VFNMADD231PDZrbk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZrbk) + .value("VFNMADD231PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZrbkz) + .value("VFNMADD231PDZrk", LIEF::assembly::x86::OPCODE::VFNMADD231PDZrk) + .value("VFNMADD231PDZrkz", LIEF::assembly::x86::OPCODE::VFNMADD231PDZrkz) + .value("VFNMADD231PDm", LIEF::assembly::x86::OPCODE::VFNMADD231PDm) + .value("VFNMADD231PDr", LIEF::assembly::x86::OPCODE::VFNMADD231PDr) + .value("VFNMADD231PHZ128m", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128m) + .value("VFNMADD231PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128mb) + .value("VFNMADD231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128mbk) + .value("VFNMADD231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128mbkz) + .value("VFNMADD231PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128mk) + .value("VFNMADD231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128mkz) + .value("VFNMADD231PHZ128r", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128r) + .value("VFNMADD231PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128rk) + .value("VFNMADD231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ128rkz) + .value("VFNMADD231PHZ256m", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256m) + .value("VFNMADD231PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256mb) + .value("VFNMADD231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256mbk) + .value("VFNMADD231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256mbkz) + .value("VFNMADD231PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256mk) + .value("VFNMADD231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256mkz) + .value("VFNMADD231PHZ256r", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256r) + .value("VFNMADD231PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256rk) + .value("VFNMADD231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZ256rkz) + .value("VFNMADD231PHZm", LIEF::assembly::x86::OPCODE::VFNMADD231PHZm) + .value("VFNMADD231PHZmb", LIEF::assembly::x86::OPCODE::VFNMADD231PHZmb) + .value("VFNMADD231PHZmbk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZmbk) + .value("VFNMADD231PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZmbkz) + .value("VFNMADD231PHZmk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZmk) + .value("VFNMADD231PHZmkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZmkz) + .value("VFNMADD231PHZr", LIEF::assembly::x86::OPCODE::VFNMADD231PHZr) + .value("VFNMADD231PHZrb", LIEF::assembly::x86::OPCODE::VFNMADD231PHZrb) + .value("VFNMADD231PHZrbk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZrbk) + .value("VFNMADD231PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZrbkz) + .value("VFNMADD231PHZrk", LIEF::assembly::x86::OPCODE::VFNMADD231PHZrk) + .value("VFNMADD231PHZrkz", LIEF::assembly::x86::OPCODE::VFNMADD231PHZrkz) + .value("VFNMADD231PSYm", LIEF::assembly::x86::OPCODE::VFNMADD231PSYm) + .value("VFNMADD231PSYr", LIEF::assembly::x86::OPCODE::VFNMADD231PSYr) + .value("VFNMADD231PSZ128m", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128m) + .value("VFNMADD231PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128mb) + .value("VFNMADD231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128mbk) + .value("VFNMADD231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128mbkz) + .value("VFNMADD231PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128mk) + .value("VFNMADD231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128mkz) + .value("VFNMADD231PSZ128r", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128r) + .value("VFNMADD231PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128rk) + .value("VFNMADD231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ128rkz) + .value("VFNMADD231PSZ256m", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256m) + .value("VFNMADD231PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256mb) + .value("VFNMADD231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256mbk) + .value("VFNMADD231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256mbkz) + .value("VFNMADD231PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256mk) + .value("VFNMADD231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256mkz) + .value("VFNMADD231PSZ256r", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256r) + .value("VFNMADD231PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256rk) + .value("VFNMADD231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZ256rkz) + .value("VFNMADD231PSZm", LIEF::assembly::x86::OPCODE::VFNMADD231PSZm) + .value("VFNMADD231PSZmb", LIEF::assembly::x86::OPCODE::VFNMADD231PSZmb) + .value("VFNMADD231PSZmbk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZmbk) + .value("VFNMADD231PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZmbkz) + .value("VFNMADD231PSZmk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZmk) + .value("VFNMADD231PSZmkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZmkz) + .value("VFNMADD231PSZr", LIEF::assembly::x86::OPCODE::VFNMADD231PSZr) + .value("VFNMADD231PSZrb", LIEF::assembly::x86::OPCODE::VFNMADD231PSZrb) + .value("VFNMADD231PSZrbk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZrbk) + .value("VFNMADD231PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZrbkz) + .value("VFNMADD231PSZrk", LIEF::assembly::x86::OPCODE::VFNMADD231PSZrk) + .value("VFNMADD231PSZrkz", LIEF::assembly::x86::OPCODE::VFNMADD231PSZrkz) + .value("VFNMADD231PSm", LIEF::assembly::x86::OPCODE::VFNMADD231PSm) + .value("VFNMADD231PSr", LIEF::assembly::x86::OPCODE::VFNMADD231PSr) + .value("VFNMADD231SDZm", LIEF::assembly::x86::OPCODE::VFNMADD231SDZm) + .value("VFNMADD231SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZm_Int) + .value("VFNMADD231SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZmk_Int) + .value("VFNMADD231SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZmkz_Int) + .value("VFNMADD231SDZr", LIEF::assembly::x86::OPCODE::VFNMADD231SDZr) + .value("VFNMADD231SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZr_Int) + .value("VFNMADD231SDZrb", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrb) + .value("VFNMADD231SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrb_Int) + .value("VFNMADD231SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrbk_Int) + .value("VFNMADD231SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrbkz_Int) + .value("VFNMADD231SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrk_Int) + .value("VFNMADD231SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDZrkz_Int) + .value("VFNMADD231SDm", LIEF::assembly::x86::OPCODE::VFNMADD231SDm) + .value("VFNMADD231SDm_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDm_Int) + .value("VFNMADD231SDr", LIEF::assembly::x86::OPCODE::VFNMADD231SDr) + .value("VFNMADD231SDr_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SDr_Int) + .value("VFNMADD231SHZm", LIEF::assembly::x86::OPCODE::VFNMADD231SHZm) + .value("VFNMADD231SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZm_Int) + .value("VFNMADD231SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZmk_Int) + .value("VFNMADD231SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZmkz_Int) + .value("VFNMADD231SHZr", LIEF::assembly::x86::OPCODE::VFNMADD231SHZr) + .value("VFNMADD231SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZr_Int) + .value("VFNMADD231SHZrb", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrb) + .value("VFNMADD231SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrb_Int) + .value("VFNMADD231SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrbk_Int) + .value("VFNMADD231SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrbkz_Int) + .value("VFNMADD231SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrk_Int) + .value("VFNMADD231SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SHZrkz_Int) + .value("VFNMADD231SSZm", LIEF::assembly::x86::OPCODE::VFNMADD231SSZm) + .value("VFNMADD231SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZm_Int) + .value("VFNMADD231SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZmk_Int) + .value("VFNMADD231SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZmkz_Int) + .value("VFNMADD231SSZr", LIEF::assembly::x86::OPCODE::VFNMADD231SSZr) + .value("VFNMADD231SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZr_Int) + .value("VFNMADD231SSZrb", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrb) + .value("VFNMADD231SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrb_Int) + .value("VFNMADD231SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrbk_Int) + .value("VFNMADD231SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrbkz_Int) + .value("VFNMADD231SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrk_Int) + .value("VFNMADD231SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSZrkz_Int) + .value("VFNMADD231SSm", LIEF::assembly::x86::OPCODE::VFNMADD231SSm) + .value("VFNMADD231SSm_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSm_Int) + .value("VFNMADD231SSr", LIEF::assembly::x86::OPCODE::VFNMADD231SSr) + .value("VFNMADD231SSr_Int", LIEF::assembly::x86::OPCODE::VFNMADD231SSr_Int) + .value("VFNMADDPD4Ymr", LIEF::assembly::x86::OPCODE::VFNMADDPD4Ymr) + .value("VFNMADDPD4Yrm", LIEF::assembly::x86::OPCODE::VFNMADDPD4Yrm) + .value("VFNMADDPD4Yrr", LIEF::assembly::x86::OPCODE::VFNMADDPD4Yrr) + .value("VFNMADDPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFNMADDPD4Yrr_REV) + .value("VFNMADDPD4mr", LIEF::assembly::x86::OPCODE::VFNMADDPD4mr) + .value("VFNMADDPD4rm", LIEF::assembly::x86::OPCODE::VFNMADDPD4rm) + .value("VFNMADDPD4rr", LIEF::assembly::x86::OPCODE::VFNMADDPD4rr) + .value("VFNMADDPD4rr_REV", LIEF::assembly::x86::OPCODE::VFNMADDPD4rr_REV) + .value("VFNMADDPS4Ymr", LIEF::assembly::x86::OPCODE::VFNMADDPS4Ymr) + .value("VFNMADDPS4Yrm", LIEF::assembly::x86::OPCODE::VFNMADDPS4Yrm) + .value("VFNMADDPS4Yrr", LIEF::assembly::x86::OPCODE::VFNMADDPS4Yrr) + .value("VFNMADDPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFNMADDPS4Yrr_REV) + .value("VFNMADDPS4mr", LIEF::assembly::x86::OPCODE::VFNMADDPS4mr) + .value("VFNMADDPS4rm", LIEF::assembly::x86::OPCODE::VFNMADDPS4rm) + .value("VFNMADDPS4rr", LIEF::assembly::x86::OPCODE::VFNMADDPS4rr) + .value("VFNMADDPS4rr_REV", LIEF::assembly::x86::OPCODE::VFNMADDPS4rr_REV) + .value("VFNMADDSD4mr", LIEF::assembly::x86::OPCODE::VFNMADDSD4mr) + .value("VFNMADDSD4mr_Int", LIEF::assembly::x86::OPCODE::VFNMADDSD4mr_Int) + .value("VFNMADDSD4rm", LIEF::assembly::x86::OPCODE::VFNMADDSD4rm) + .value("VFNMADDSD4rm_Int", LIEF::assembly::x86::OPCODE::VFNMADDSD4rm_Int) + .value("VFNMADDSD4rr", LIEF::assembly::x86::OPCODE::VFNMADDSD4rr) + .value("VFNMADDSD4rr_Int", LIEF::assembly::x86::OPCODE::VFNMADDSD4rr_Int) + .value("VFNMADDSD4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFNMADDSD4rr_Int_REV) + .value("VFNMADDSD4rr_REV", LIEF::assembly::x86::OPCODE::VFNMADDSD4rr_REV) + .value("VFNMADDSS4mr", LIEF::assembly::x86::OPCODE::VFNMADDSS4mr) + .value("VFNMADDSS4mr_Int", LIEF::assembly::x86::OPCODE::VFNMADDSS4mr_Int) + .value("VFNMADDSS4rm", LIEF::assembly::x86::OPCODE::VFNMADDSS4rm) + .value("VFNMADDSS4rm_Int", LIEF::assembly::x86::OPCODE::VFNMADDSS4rm_Int) + .value("VFNMADDSS4rr", LIEF::assembly::x86::OPCODE::VFNMADDSS4rr) + .value("VFNMADDSS4rr_Int", LIEF::assembly::x86::OPCODE::VFNMADDSS4rr_Int) + .value("VFNMADDSS4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFNMADDSS4rr_Int_REV) + .value("VFNMADDSS4rr_REV", LIEF::assembly::x86::OPCODE::VFNMADDSS4rr_REV) + .value("VFNMSUB132BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128m) + .value("VFNMSUB132BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128mb) + .value("VFNMSUB132BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128mbk) + .value("VFNMSUB132BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128mbkz) + .value("VFNMSUB132BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128mk) + .value("VFNMSUB132BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128mkz) + .value("VFNMSUB132BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128r) + .value("VFNMSUB132BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128rk) + .value("VFNMSUB132BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z128rkz) + .value("VFNMSUB132BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256m) + .value("VFNMSUB132BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256mb) + .value("VFNMSUB132BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256mbk) + .value("VFNMSUB132BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256mbkz) + .value("VFNMSUB132BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256mk) + .value("VFNMSUB132BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256mkz) + .value("VFNMSUB132BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256r) + .value("VFNMSUB132BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256rk) + .value("VFNMSUB132BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Z256rkz) + .value("VFNMSUB132BF16Zm", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zm) + .value("VFNMSUB132BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zmb) + .value("VFNMSUB132BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zmbk) + .value("VFNMSUB132BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zmbkz) + .value("VFNMSUB132BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zmk) + .value("VFNMSUB132BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zmkz) + .value("VFNMSUB132BF16Zr", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zr) + .value("VFNMSUB132BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zrk) + .value("VFNMSUB132BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMSUB132BF16Zrkz) + .value("VFNMSUB132PDYm", LIEF::assembly::x86::OPCODE::VFNMSUB132PDYm) + .value("VFNMSUB132PDYr", LIEF::assembly::x86::OPCODE::VFNMSUB132PDYr) + .value("VFNMSUB132PDZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128m) + .value("VFNMSUB132PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128mb) + .value("VFNMSUB132PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128mbk) + .value("VFNMSUB132PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128mbkz) + .value("VFNMSUB132PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128mk) + .value("VFNMSUB132PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128mkz) + .value("VFNMSUB132PDZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128r) + .value("VFNMSUB132PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128rk) + .value("VFNMSUB132PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ128rkz) + .value("VFNMSUB132PDZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256m) + .value("VFNMSUB132PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256mb) + .value("VFNMSUB132PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256mbk) + .value("VFNMSUB132PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256mbkz) + .value("VFNMSUB132PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256mk) + .value("VFNMSUB132PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256mkz) + .value("VFNMSUB132PDZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256r) + .value("VFNMSUB132PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256rk) + .value("VFNMSUB132PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZ256rkz) + .value("VFNMSUB132PDZm", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZm) + .value("VFNMSUB132PDZmb", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZmb) + .value("VFNMSUB132PDZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZmbk) + .value("VFNMSUB132PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZmbkz) + .value("VFNMSUB132PDZmk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZmk) + .value("VFNMSUB132PDZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZmkz) + .value("VFNMSUB132PDZr", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZr) + .value("VFNMSUB132PDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZrb) + .value("VFNMSUB132PDZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZrbk) + .value("VFNMSUB132PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZrbkz) + .value("VFNMSUB132PDZrk", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZrk) + .value("VFNMSUB132PDZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PDZrkz) + .value("VFNMSUB132PDm", LIEF::assembly::x86::OPCODE::VFNMSUB132PDm) + .value("VFNMSUB132PDr", LIEF::assembly::x86::OPCODE::VFNMSUB132PDr) + .value("VFNMSUB132PHZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128m) + .value("VFNMSUB132PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128mb) + .value("VFNMSUB132PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128mbk) + .value("VFNMSUB132PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128mbkz) + .value("VFNMSUB132PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128mk) + .value("VFNMSUB132PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128mkz) + .value("VFNMSUB132PHZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128r) + .value("VFNMSUB132PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128rk) + .value("VFNMSUB132PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ128rkz) + .value("VFNMSUB132PHZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256m) + .value("VFNMSUB132PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256mb) + .value("VFNMSUB132PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256mbk) + .value("VFNMSUB132PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256mbkz) + .value("VFNMSUB132PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256mk) + .value("VFNMSUB132PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256mkz) + .value("VFNMSUB132PHZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256r) + .value("VFNMSUB132PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256rk) + .value("VFNMSUB132PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZ256rkz) + .value("VFNMSUB132PHZm", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZm) + .value("VFNMSUB132PHZmb", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZmb) + .value("VFNMSUB132PHZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZmbk) + .value("VFNMSUB132PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZmbkz) + .value("VFNMSUB132PHZmk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZmk) + .value("VFNMSUB132PHZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZmkz) + .value("VFNMSUB132PHZr", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZr) + .value("VFNMSUB132PHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZrb) + .value("VFNMSUB132PHZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZrbk) + .value("VFNMSUB132PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZrbkz) + .value("VFNMSUB132PHZrk", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZrk) + .value("VFNMSUB132PHZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PHZrkz) + .value("VFNMSUB132PSYm", LIEF::assembly::x86::OPCODE::VFNMSUB132PSYm); + opcodes.value("VFNMSUB132PSYr", LIEF::assembly::x86::OPCODE::VFNMSUB132PSYr) + .value("VFNMSUB132PSZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128m) + .value("VFNMSUB132PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128mb) + .value("VFNMSUB132PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128mbk) + .value("VFNMSUB132PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128mbkz) + .value("VFNMSUB132PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128mk) + .value("VFNMSUB132PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128mkz) + .value("VFNMSUB132PSZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128r) + .value("VFNMSUB132PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128rk) + .value("VFNMSUB132PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ128rkz) + .value("VFNMSUB132PSZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256m) + .value("VFNMSUB132PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256mb) + .value("VFNMSUB132PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256mbk) + .value("VFNMSUB132PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256mbkz) + .value("VFNMSUB132PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256mk) + .value("VFNMSUB132PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256mkz) + .value("VFNMSUB132PSZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256r) + .value("VFNMSUB132PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256rk) + .value("VFNMSUB132PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZ256rkz) + .value("VFNMSUB132PSZm", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZm) + .value("VFNMSUB132PSZmb", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZmb) + .value("VFNMSUB132PSZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZmbk) + .value("VFNMSUB132PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZmbkz) + .value("VFNMSUB132PSZmk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZmk) + .value("VFNMSUB132PSZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZmkz) + .value("VFNMSUB132PSZr", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZr) + .value("VFNMSUB132PSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZrb) + .value("VFNMSUB132PSZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZrbk) + .value("VFNMSUB132PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZrbkz) + .value("VFNMSUB132PSZrk", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZrk) + .value("VFNMSUB132PSZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB132PSZrkz) + .value("VFNMSUB132PSm", LIEF::assembly::x86::OPCODE::VFNMSUB132PSm) + .value("VFNMSUB132PSr", LIEF::assembly::x86::OPCODE::VFNMSUB132PSr) + .value("VFNMSUB132SDZm", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZm) + .value("VFNMSUB132SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZm_Int) + .value("VFNMSUB132SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZmk_Int) + .value("VFNMSUB132SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZmkz_Int) + .value("VFNMSUB132SDZr", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZr) + .value("VFNMSUB132SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZr_Int) + .value("VFNMSUB132SDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrb) + .value("VFNMSUB132SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrb_Int) + .value("VFNMSUB132SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrbk_Int) + .value("VFNMSUB132SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrbkz_Int) + .value("VFNMSUB132SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrk_Int) + .value("VFNMSUB132SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDZrkz_Int) + .value("VFNMSUB132SDm", LIEF::assembly::x86::OPCODE::VFNMSUB132SDm) + .value("VFNMSUB132SDm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDm_Int) + .value("VFNMSUB132SDr", LIEF::assembly::x86::OPCODE::VFNMSUB132SDr) + .value("VFNMSUB132SDr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SDr_Int) + .value("VFNMSUB132SHZm", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZm) + .value("VFNMSUB132SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZm_Int) + .value("VFNMSUB132SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZmk_Int) + .value("VFNMSUB132SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZmkz_Int) + .value("VFNMSUB132SHZr", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZr) + .value("VFNMSUB132SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZr_Int) + .value("VFNMSUB132SHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrb) + .value("VFNMSUB132SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrb_Int) + .value("VFNMSUB132SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrbk_Int) + .value("VFNMSUB132SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrbkz_Int) + .value("VFNMSUB132SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrk_Int) + .value("VFNMSUB132SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SHZrkz_Int) + .value("VFNMSUB132SSZm", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZm) + .value("VFNMSUB132SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZm_Int) + .value("VFNMSUB132SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZmk_Int) + .value("VFNMSUB132SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZmkz_Int) + .value("VFNMSUB132SSZr", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZr) + .value("VFNMSUB132SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZr_Int) + .value("VFNMSUB132SSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrb) + .value("VFNMSUB132SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrb_Int) + .value("VFNMSUB132SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrbk_Int) + .value("VFNMSUB132SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrbkz_Int) + .value("VFNMSUB132SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrk_Int) + .value("VFNMSUB132SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSZrkz_Int) + .value("VFNMSUB132SSm", LIEF::assembly::x86::OPCODE::VFNMSUB132SSm) + .value("VFNMSUB132SSm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSm_Int) + .value("VFNMSUB132SSr", LIEF::assembly::x86::OPCODE::VFNMSUB132SSr) + .value("VFNMSUB132SSr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB132SSr_Int) + .value("VFNMSUB213BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128m) + .value("VFNMSUB213BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128mb) + .value("VFNMSUB213BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128mbk) + .value("VFNMSUB213BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128mbkz) + .value("VFNMSUB213BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128mk) + .value("VFNMSUB213BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128mkz) + .value("VFNMSUB213BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128r) + .value("VFNMSUB213BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128rk) + .value("VFNMSUB213BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z128rkz) + .value("VFNMSUB213BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256m) + .value("VFNMSUB213BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256mb) + .value("VFNMSUB213BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256mbk) + .value("VFNMSUB213BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256mbkz) + .value("VFNMSUB213BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256mk) + .value("VFNMSUB213BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256mkz) + .value("VFNMSUB213BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256r) + .value("VFNMSUB213BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256rk) + .value("VFNMSUB213BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Z256rkz) + .value("VFNMSUB213BF16Zm", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zm) + .value("VFNMSUB213BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zmb) + .value("VFNMSUB213BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zmbk) + .value("VFNMSUB213BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zmbkz) + .value("VFNMSUB213BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zmk) + .value("VFNMSUB213BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zmkz) + .value("VFNMSUB213BF16Zr", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zr) + .value("VFNMSUB213BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zrk) + .value("VFNMSUB213BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMSUB213BF16Zrkz) + .value("VFNMSUB213PDYm", LIEF::assembly::x86::OPCODE::VFNMSUB213PDYm) + .value("VFNMSUB213PDYr", LIEF::assembly::x86::OPCODE::VFNMSUB213PDYr) + .value("VFNMSUB213PDZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128m) + .value("VFNMSUB213PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128mb) + .value("VFNMSUB213PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128mbk) + .value("VFNMSUB213PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128mbkz) + .value("VFNMSUB213PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128mk) + .value("VFNMSUB213PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128mkz) + .value("VFNMSUB213PDZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128r) + .value("VFNMSUB213PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128rk) + .value("VFNMSUB213PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ128rkz) + .value("VFNMSUB213PDZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256m) + .value("VFNMSUB213PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256mb) + .value("VFNMSUB213PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256mbk) + .value("VFNMSUB213PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256mbkz) + .value("VFNMSUB213PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256mk) + .value("VFNMSUB213PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256mkz) + .value("VFNMSUB213PDZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256r) + .value("VFNMSUB213PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256rk) + .value("VFNMSUB213PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZ256rkz) + .value("VFNMSUB213PDZm", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZm) + .value("VFNMSUB213PDZmb", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZmb) + .value("VFNMSUB213PDZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZmbk) + .value("VFNMSUB213PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZmbkz) + .value("VFNMSUB213PDZmk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZmk) + .value("VFNMSUB213PDZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZmkz) + .value("VFNMSUB213PDZr", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZr) + .value("VFNMSUB213PDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZrb) + .value("VFNMSUB213PDZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZrbk) + .value("VFNMSUB213PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZrbkz) + .value("VFNMSUB213PDZrk", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZrk) + .value("VFNMSUB213PDZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PDZrkz) + .value("VFNMSUB213PDm", LIEF::assembly::x86::OPCODE::VFNMSUB213PDm) + .value("VFNMSUB213PDr", LIEF::assembly::x86::OPCODE::VFNMSUB213PDr) + .value("VFNMSUB213PHZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128m) + .value("VFNMSUB213PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128mb) + .value("VFNMSUB213PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128mbk) + .value("VFNMSUB213PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128mbkz) + .value("VFNMSUB213PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128mk) + .value("VFNMSUB213PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128mkz) + .value("VFNMSUB213PHZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128r) + .value("VFNMSUB213PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128rk) + .value("VFNMSUB213PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ128rkz) + .value("VFNMSUB213PHZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256m) + .value("VFNMSUB213PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256mb) + .value("VFNMSUB213PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256mbk) + .value("VFNMSUB213PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256mbkz) + .value("VFNMSUB213PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256mk) + .value("VFNMSUB213PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256mkz) + .value("VFNMSUB213PHZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256r) + .value("VFNMSUB213PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256rk) + .value("VFNMSUB213PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZ256rkz) + .value("VFNMSUB213PHZm", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZm) + .value("VFNMSUB213PHZmb", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZmb) + .value("VFNMSUB213PHZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZmbk) + .value("VFNMSUB213PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZmbkz) + .value("VFNMSUB213PHZmk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZmk) + .value("VFNMSUB213PHZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZmkz) + .value("VFNMSUB213PHZr", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZr) + .value("VFNMSUB213PHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZrb) + .value("VFNMSUB213PHZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZrbk) + .value("VFNMSUB213PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZrbkz) + .value("VFNMSUB213PHZrk", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZrk) + .value("VFNMSUB213PHZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PHZrkz) + .value("VFNMSUB213PSYm", LIEF::assembly::x86::OPCODE::VFNMSUB213PSYm) + .value("VFNMSUB213PSYr", LIEF::assembly::x86::OPCODE::VFNMSUB213PSYr) + .value("VFNMSUB213PSZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128m) + .value("VFNMSUB213PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128mb) + .value("VFNMSUB213PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128mbk) + .value("VFNMSUB213PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128mbkz) + .value("VFNMSUB213PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128mk) + .value("VFNMSUB213PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128mkz) + .value("VFNMSUB213PSZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128r) + .value("VFNMSUB213PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128rk) + .value("VFNMSUB213PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ128rkz) + .value("VFNMSUB213PSZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256m) + .value("VFNMSUB213PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256mb) + .value("VFNMSUB213PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256mbk) + .value("VFNMSUB213PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256mbkz) + .value("VFNMSUB213PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256mk) + .value("VFNMSUB213PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256mkz) + .value("VFNMSUB213PSZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256r) + .value("VFNMSUB213PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256rk) + .value("VFNMSUB213PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZ256rkz) + .value("VFNMSUB213PSZm", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZm) + .value("VFNMSUB213PSZmb", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZmb) + .value("VFNMSUB213PSZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZmbk) + .value("VFNMSUB213PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZmbkz) + .value("VFNMSUB213PSZmk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZmk) + .value("VFNMSUB213PSZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZmkz) + .value("VFNMSUB213PSZr", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZr) + .value("VFNMSUB213PSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZrb) + .value("VFNMSUB213PSZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZrbk) + .value("VFNMSUB213PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZrbkz) + .value("VFNMSUB213PSZrk", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZrk) + .value("VFNMSUB213PSZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB213PSZrkz) + .value("VFNMSUB213PSm", LIEF::assembly::x86::OPCODE::VFNMSUB213PSm) + .value("VFNMSUB213PSr", LIEF::assembly::x86::OPCODE::VFNMSUB213PSr) + .value("VFNMSUB213SDZm", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZm) + .value("VFNMSUB213SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZm_Int) + .value("VFNMSUB213SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZmk_Int) + .value("VFNMSUB213SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZmkz_Int) + .value("VFNMSUB213SDZr", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZr) + .value("VFNMSUB213SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZr_Int) + .value("VFNMSUB213SDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrb) + .value("VFNMSUB213SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrb_Int) + .value("VFNMSUB213SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrbk_Int) + .value("VFNMSUB213SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrbkz_Int) + .value("VFNMSUB213SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrk_Int) + .value("VFNMSUB213SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDZrkz_Int) + .value("VFNMSUB213SDm", LIEF::assembly::x86::OPCODE::VFNMSUB213SDm) + .value("VFNMSUB213SDm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDm_Int) + .value("VFNMSUB213SDr", LIEF::assembly::x86::OPCODE::VFNMSUB213SDr) + .value("VFNMSUB213SDr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SDr_Int) + .value("VFNMSUB213SHZm", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZm) + .value("VFNMSUB213SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZm_Int) + .value("VFNMSUB213SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZmk_Int) + .value("VFNMSUB213SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZmkz_Int) + .value("VFNMSUB213SHZr", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZr) + .value("VFNMSUB213SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZr_Int) + .value("VFNMSUB213SHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrb) + .value("VFNMSUB213SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrb_Int) + .value("VFNMSUB213SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrbk_Int) + .value("VFNMSUB213SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrbkz_Int) + .value("VFNMSUB213SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrk_Int) + .value("VFNMSUB213SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SHZrkz_Int) + .value("VFNMSUB213SSZm", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZm) + .value("VFNMSUB213SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZm_Int) + .value("VFNMSUB213SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZmk_Int) + .value("VFNMSUB213SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZmkz_Int) + .value("VFNMSUB213SSZr", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZr) + .value("VFNMSUB213SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZr_Int) + .value("VFNMSUB213SSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrb) + .value("VFNMSUB213SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrb_Int) + .value("VFNMSUB213SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrbk_Int) + .value("VFNMSUB213SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrbkz_Int) + .value("VFNMSUB213SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrk_Int) + .value("VFNMSUB213SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSZrkz_Int) + .value("VFNMSUB213SSm", LIEF::assembly::x86::OPCODE::VFNMSUB213SSm) + .value("VFNMSUB213SSm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSm_Int) + .value("VFNMSUB213SSr", LIEF::assembly::x86::OPCODE::VFNMSUB213SSr) + .value("VFNMSUB213SSr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB213SSr_Int) + .value("VFNMSUB231BF16Z128m", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128m) + .value("VFNMSUB231BF16Z128mb", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128mb) + .value("VFNMSUB231BF16Z128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128mbk) + .value("VFNMSUB231BF16Z128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128mbkz) + .value("VFNMSUB231BF16Z128mk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128mk) + .value("VFNMSUB231BF16Z128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128mkz) + .value("VFNMSUB231BF16Z128r", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128r) + .value("VFNMSUB231BF16Z128rk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128rk) + .value("VFNMSUB231BF16Z128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z128rkz) + .value("VFNMSUB231BF16Z256m", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256m) + .value("VFNMSUB231BF16Z256mb", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256mb) + .value("VFNMSUB231BF16Z256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256mbk) + .value("VFNMSUB231BF16Z256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256mbkz) + .value("VFNMSUB231BF16Z256mk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256mk) + .value("VFNMSUB231BF16Z256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256mkz) + .value("VFNMSUB231BF16Z256r", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256r) + .value("VFNMSUB231BF16Z256rk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256rk) + .value("VFNMSUB231BF16Z256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Z256rkz) + .value("VFNMSUB231BF16Zm", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zm) + .value("VFNMSUB231BF16Zmb", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zmb) + .value("VFNMSUB231BF16Zmbk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zmbk) + .value("VFNMSUB231BF16Zmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zmbkz) + .value("VFNMSUB231BF16Zmk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zmk) + .value("VFNMSUB231BF16Zmkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zmkz) + .value("VFNMSUB231BF16Zr", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zr) + .value("VFNMSUB231BF16Zrk", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zrk) + .value("VFNMSUB231BF16Zrkz", LIEF::assembly::x86::OPCODE::VFNMSUB231BF16Zrkz) + .value("VFNMSUB231PDYm", LIEF::assembly::x86::OPCODE::VFNMSUB231PDYm) + .value("VFNMSUB231PDYr", LIEF::assembly::x86::OPCODE::VFNMSUB231PDYr) + .value("VFNMSUB231PDZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128m) + .value("VFNMSUB231PDZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128mb) + .value("VFNMSUB231PDZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128mbk) + .value("VFNMSUB231PDZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128mbkz) + .value("VFNMSUB231PDZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128mk) + .value("VFNMSUB231PDZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128mkz) + .value("VFNMSUB231PDZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128r) + .value("VFNMSUB231PDZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128rk) + .value("VFNMSUB231PDZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ128rkz) + .value("VFNMSUB231PDZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256m) + .value("VFNMSUB231PDZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256mb) + .value("VFNMSUB231PDZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256mbk) + .value("VFNMSUB231PDZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256mbkz) + .value("VFNMSUB231PDZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256mk) + .value("VFNMSUB231PDZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256mkz) + .value("VFNMSUB231PDZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256r) + .value("VFNMSUB231PDZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256rk) + .value("VFNMSUB231PDZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZ256rkz) + .value("VFNMSUB231PDZm", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZm) + .value("VFNMSUB231PDZmb", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZmb) + .value("VFNMSUB231PDZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZmbk) + .value("VFNMSUB231PDZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZmbkz) + .value("VFNMSUB231PDZmk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZmk) + .value("VFNMSUB231PDZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZmkz) + .value("VFNMSUB231PDZr", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZr); + opcodes.value("VFNMSUB231PDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZrb) + .value("VFNMSUB231PDZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZrbk) + .value("VFNMSUB231PDZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZrbkz) + .value("VFNMSUB231PDZrk", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZrk) + .value("VFNMSUB231PDZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PDZrkz) + .value("VFNMSUB231PDm", LIEF::assembly::x86::OPCODE::VFNMSUB231PDm) + .value("VFNMSUB231PDr", LIEF::assembly::x86::OPCODE::VFNMSUB231PDr) + .value("VFNMSUB231PHZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128m) + .value("VFNMSUB231PHZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128mb) + .value("VFNMSUB231PHZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128mbk) + .value("VFNMSUB231PHZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128mbkz) + .value("VFNMSUB231PHZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128mk) + .value("VFNMSUB231PHZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128mkz) + .value("VFNMSUB231PHZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128r) + .value("VFNMSUB231PHZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128rk) + .value("VFNMSUB231PHZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ128rkz) + .value("VFNMSUB231PHZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256m) + .value("VFNMSUB231PHZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256mb) + .value("VFNMSUB231PHZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256mbk) + .value("VFNMSUB231PHZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256mbkz) + .value("VFNMSUB231PHZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256mk) + .value("VFNMSUB231PHZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256mkz) + .value("VFNMSUB231PHZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256r) + .value("VFNMSUB231PHZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256rk) + .value("VFNMSUB231PHZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZ256rkz) + .value("VFNMSUB231PHZm", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZm) + .value("VFNMSUB231PHZmb", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZmb) + .value("VFNMSUB231PHZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZmbk) + .value("VFNMSUB231PHZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZmbkz) + .value("VFNMSUB231PHZmk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZmk) + .value("VFNMSUB231PHZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZmkz) + .value("VFNMSUB231PHZr", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZr) + .value("VFNMSUB231PHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZrb) + .value("VFNMSUB231PHZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZrbk) + .value("VFNMSUB231PHZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZrbkz) + .value("VFNMSUB231PHZrk", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZrk) + .value("VFNMSUB231PHZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PHZrkz) + .value("VFNMSUB231PSYm", LIEF::assembly::x86::OPCODE::VFNMSUB231PSYm) + .value("VFNMSUB231PSYr", LIEF::assembly::x86::OPCODE::VFNMSUB231PSYr) + .value("VFNMSUB231PSZ128m", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128m) + .value("VFNMSUB231PSZ128mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128mb) + .value("VFNMSUB231PSZ128mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128mbk) + .value("VFNMSUB231PSZ128mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128mbkz) + .value("VFNMSUB231PSZ128mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128mk) + .value("VFNMSUB231PSZ128mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128mkz) + .value("VFNMSUB231PSZ128r", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128r) + .value("VFNMSUB231PSZ128rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128rk) + .value("VFNMSUB231PSZ128rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ128rkz) + .value("VFNMSUB231PSZ256m", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256m) + .value("VFNMSUB231PSZ256mb", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256mb) + .value("VFNMSUB231PSZ256mbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256mbk) + .value("VFNMSUB231PSZ256mbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256mbkz) + .value("VFNMSUB231PSZ256mk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256mk) + .value("VFNMSUB231PSZ256mkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256mkz) + .value("VFNMSUB231PSZ256r", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256r) + .value("VFNMSUB231PSZ256rk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256rk) + .value("VFNMSUB231PSZ256rkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZ256rkz) + .value("VFNMSUB231PSZm", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZm) + .value("VFNMSUB231PSZmb", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZmb) + .value("VFNMSUB231PSZmbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZmbk) + .value("VFNMSUB231PSZmbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZmbkz) + .value("VFNMSUB231PSZmk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZmk) + .value("VFNMSUB231PSZmkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZmkz) + .value("VFNMSUB231PSZr", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZr) + .value("VFNMSUB231PSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZrb) + .value("VFNMSUB231PSZrbk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZrbk) + .value("VFNMSUB231PSZrbkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZrbkz) + .value("VFNMSUB231PSZrk", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZrk) + .value("VFNMSUB231PSZrkz", LIEF::assembly::x86::OPCODE::VFNMSUB231PSZrkz) + .value("VFNMSUB231PSm", LIEF::assembly::x86::OPCODE::VFNMSUB231PSm) + .value("VFNMSUB231PSr", LIEF::assembly::x86::OPCODE::VFNMSUB231PSr) + .value("VFNMSUB231SDZm", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZm) + .value("VFNMSUB231SDZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZm_Int) + .value("VFNMSUB231SDZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZmk_Int) + .value("VFNMSUB231SDZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZmkz_Int) + .value("VFNMSUB231SDZr", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZr) + .value("VFNMSUB231SDZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZr_Int) + .value("VFNMSUB231SDZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrb) + .value("VFNMSUB231SDZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrb_Int) + .value("VFNMSUB231SDZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrbk_Int) + .value("VFNMSUB231SDZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrbkz_Int) + .value("VFNMSUB231SDZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrk_Int) + .value("VFNMSUB231SDZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDZrkz_Int) + .value("VFNMSUB231SDm", LIEF::assembly::x86::OPCODE::VFNMSUB231SDm) + .value("VFNMSUB231SDm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDm_Int) + .value("VFNMSUB231SDr", LIEF::assembly::x86::OPCODE::VFNMSUB231SDr) + .value("VFNMSUB231SDr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SDr_Int) + .value("VFNMSUB231SHZm", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZm) + .value("VFNMSUB231SHZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZm_Int) + .value("VFNMSUB231SHZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZmk_Int) + .value("VFNMSUB231SHZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZmkz_Int) + .value("VFNMSUB231SHZr", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZr) + .value("VFNMSUB231SHZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZr_Int) + .value("VFNMSUB231SHZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrb) + .value("VFNMSUB231SHZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrb_Int) + .value("VFNMSUB231SHZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrbk_Int) + .value("VFNMSUB231SHZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrbkz_Int) + .value("VFNMSUB231SHZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrk_Int) + .value("VFNMSUB231SHZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SHZrkz_Int) + .value("VFNMSUB231SSZm", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZm) + .value("VFNMSUB231SSZm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZm_Int) + .value("VFNMSUB231SSZmk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZmk_Int) + .value("VFNMSUB231SSZmkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZmkz_Int) + .value("VFNMSUB231SSZr", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZr) + .value("VFNMSUB231SSZr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZr_Int) + .value("VFNMSUB231SSZrb", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrb) + .value("VFNMSUB231SSZrb_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrb_Int) + .value("VFNMSUB231SSZrbk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrbk_Int) + .value("VFNMSUB231SSZrbkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrbkz_Int) + .value("VFNMSUB231SSZrk_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrk_Int) + .value("VFNMSUB231SSZrkz_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSZrkz_Int) + .value("VFNMSUB231SSm", LIEF::assembly::x86::OPCODE::VFNMSUB231SSm) + .value("VFNMSUB231SSm_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSm_Int) + .value("VFNMSUB231SSr", LIEF::assembly::x86::OPCODE::VFNMSUB231SSr) + .value("VFNMSUB231SSr_Int", LIEF::assembly::x86::OPCODE::VFNMSUB231SSr_Int) + .value("VFNMSUBPD4Ymr", LIEF::assembly::x86::OPCODE::VFNMSUBPD4Ymr) + .value("VFNMSUBPD4Yrm", LIEF::assembly::x86::OPCODE::VFNMSUBPD4Yrm) + .value("VFNMSUBPD4Yrr", LIEF::assembly::x86::OPCODE::VFNMSUBPD4Yrr) + .value("VFNMSUBPD4Yrr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBPD4Yrr_REV) + .value("VFNMSUBPD4mr", LIEF::assembly::x86::OPCODE::VFNMSUBPD4mr) + .value("VFNMSUBPD4rm", LIEF::assembly::x86::OPCODE::VFNMSUBPD4rm) + .value("VFNMSUBPD4rr", LIEF::assembly::x86::OPCODE::VFNMSUBPD4rr) + .value("VFNMSUBPD4rr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBPD4rr_REV) + .value("VFNMSUBPS4Ymr", LIEF::assembly::x86::OPCODE::VFNMSUBPS4Ymr) + .value("VFNMSUBPS4Yrm", LIEF::assembly::x86::OPCODE::VFNMSUBPS4Yrm) + .value("VFNMSUBPS4Yrr", LIEF::assembly::x86::OPCODE::VFNMSUBPS4Yrr) + .value("VFNMSUBPS4Yrr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBPS4Yrr_REV) + .value("VFNMSUBPS4mr", LIEF::assembly::x86::OPCODE::VFNMSUBPS4mr) + .value("VFNMSUBPS4rm", LIEF::assembly::x86::OPCODE::VFNMSUBPS4rm) + .value("VFNMSUBPS4rr", LIEF::assembly::x86::OPCODE::VFNMSUBPS4rr) + .value("VFNMSUBPS4rr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBPS4rr_REV) + .value("VFNMSUBSD4mr", LIEF::assembly::x86::OPCODE::VFNMSUBSD4mr) + .value("VFNMSUBSD4mr_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSD4mr_Int) + .value("VFNMSUBSD4rm", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rm) + .value("VFNMSUBSD4rm_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rm_Int) + .value("VFNMSUBSD4rr", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rr) + .value("VFNMSUBSD4rr_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rr_Int) + .value("VFNMSUBSD4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rr_Int_REV) + .value("VFNMSUBSD4rr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBSD4rr_REV) + .value("VFNMSUBSS4mr", LIEF::assembly::x86::OPCODE::VFNMSUBSS4mr) + .value("VFNMSUBSS4mr_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSS4mr_Int) + .value("VFNMSUBSS4rm", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rm) + .value("VFNMSUBSS4rm_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rm_Int) + .value("VFNMSUBSS4rr", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rr) + .value("VFNMSUBSS4rr_Int", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rr_Int) + .value("VFNMSUBSS4rr_Int_REV", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rr_Int_REV) + .value("VFNMSUBSS4rr_REV", LIEF::assembly::x86::OPCODE::VFNMSUBSS4rr_REV) + .value("VFPCLASSBF16Z128mbi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128mbi) + .value("VFPCLASSBF16Z128mbik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128mbik) + .value("VFPCLASSBF16Z128mi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128mi) + .value("VFPCLASSBF16Z128mik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128mik) + .value("VFPCLASSBF16Z128ri", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128ri) + .value("VFPCLASSBF16Z128rik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z128rik) + .value("VFPCLASSBF16Z256mbi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256mbi) + .value("VFPCLASSBF16Z256mbik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256mbik) + .value("VFPCLASSBF16Z256mi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256mi) + .value("VFPCLASSBF16Z256mik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256mik) + .value("VFPCLASSBF16Z256ri", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256ri) + .value("VFPCLASSBF16Z256rik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Z256rik) + .value("VFPCLASSBF16Zmbi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zmbi) + .value("VFPCLASSBF16Zmbik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zmbik) + .value("VFPCLASSBF16Zmi", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zmi) + .value("VFPCLASSBF16Zmik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zmik) + .value("VFPCLASSBF16Zri", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zri) + .value("VFPCLASSBF16Zrik", LIEF::assembly::x86::OPCODE::VFPCLASSBF16Zrik) + .value("VFPCLASSPDZ128mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128mbi) + .value("VFPCLASSPDZ128mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128mbik) + .value("VFPCLASSPDZ128mi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128mi) + .value("VFPCLASSPDZ128mik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128mik) + .value("VFPCLASSPDZ128ri", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128ri) + .value("VFPCLASSPDZ128rik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ128rik) + .value("VFPCLASSPDZ256mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256mbi) + .value("VFPCLASSPDZ256mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256mbik) + .value("VFPCLASSPDZ256mi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256mi) + .value("VFPCLASSPDZ256mik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256mik) + .value("VFPCLASSPDZ256ri", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256ri) + .value("VFPCLASSPDZ256rik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZ256rik) + .value("VFPCLASSPDZmbi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZmbi) + .value("VFPCLASSPDZmbik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZmbik) + .value("VFPCLASSPDZmi", LIEF::assembly::x86::OPCODE::VFPCLASSPDZmi) + .value("VFPCLASSPDZmik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZmik) + .value("VFPCLASSPDZri", LIEF::assembly::x86::OPCODE::VFPCLASSPDZri) + .value("VFPCLASSPDZrik", LIEF::assembly::x86::OPCODE::VFPCLASSPDZrik) + .value("VFPCLASSPHZ128mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128mbi) + .value("VFPCLASSPHZ128mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128mbik) + .value("VFPCLASSPHZ128mi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128mi) + .value("VFPCLASSPHZ128mik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128mik) + .value("VFPCLASSPHZ128ri", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128ri) + .value("VFPCLASSPHZ128rik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ128rik) + .value("VFPCLASSPHZ256mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256mbi) + .value("VFPCLASSPHZ256mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256mbik) + .value("VFPCLASSPHZ256mi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256mi) + .value("VFPCLASSPHZ256mik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256mik) + .value("VFPCLASSPHZ256ri", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256ri) + .value("VFPCLASSPHZ256rik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZ256rik) + .value("VFPCLASSPHZmbi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZmbi) + .value("VFPCLASSPHZmbik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZmbik) + .value("VFPCLASSPHZmi", LIEF::assembly::x86::OPCODE::VFPCLASSPHZmi) + .value("VFPCLASSPHZmik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZmik) + .value("VFPCLASSPHZri", LIEF::assembly::x86::OPCODE::VFPCLASSPHZri) + .value("VFPCLASSPHZrik", LIEF::assembly::x86::OPCODE::VFPCLASSPHZrik) + .value("VFPCLASSPSZ128mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128mbi) + .value("VFPCLASSPSZ128mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128mbik) + .value("VFPCLASSPSZ128mi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128mi) + .value("VFPCLASSPSZ128mik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128mik) + .value("VFPCLASSPSZ128ri", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128ri) + .value("VFPCLASSPSZ128rik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ128rik) + .value("VFPCLASSPSZ256mbi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256mbi) + .value("VFPCLASSPSZ256mbik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256mbik) + .value("VFPCLASSPSZ256mi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256mi) + .value("VFPCLASSPSZ256mik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256mik) + .value("VFPCLASSPSZ256ri", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256ri) + .value("VFPCLASSPSZ256rik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZ256rik) + .value("VFPCLASSPSZmbi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZmbi) + .value("VFPCLASSPSZmbik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZmbik) + .value("VFPCLASSPSZmi", LIEF::assembly::x86::OPCODE::VFPCLASSPSZmi) + .value("VFPCLASSPSZmik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZmik) + .value("VFPCLASSPSZri", LIEF::assembly::x86::OPCODE::VFPCLASSPSZri) + .value("VFPCLASSPSZrik", LIEF::assembly::x86::OPCODE::VFPCLASSPSZrik) + .value("VFPCLASSSDZmi", LIEF::assembly::x86::OPCODE::VFPCLASSSDZmi) + .value("VFPCLASSSDZmik", LIEF::assembly::x86::OPCODE::VFPCLASSSDZmik) + .value("VFPCLASSSDZri", LIEF::assembly::x86::OPCODE::VFPCLASSSDZri) + .value("VFPCLASSSDZrik", LIEF::assembly::x86::OPCODE::VFPCLASSSDZrik) + .value("VFPCLASSSHZmi", LIEF::assembly::x86::OPCODE::VFPCLASSSHZmi) + .value("VFPCLASSSHZmik", LIEF::assembly::x86::OPCODE::VFPCLASSSHZmik) + .value("VFPCLASSSHZri", LIEF::assembly::x86::OPCODE::VFPCLASSSHZri) + .value("VFPCLASSSHZrik", LIEF::assembly::x86::OPCODE::VFPCLASSSHZrik) + .value("VFPCLASSSSZmi", LIEF::assembly::x86::OPCODE::VFPCLASSSSZmi) + .value("VFPCLASSSSZmik", LIEF::assembly::x86::OPCODE::VFPCLASSSSZmik) + .value("VFPCLASSSSZri", LIEF::assembly::x86::OPCODE::VFPCLASSSSZri) + .value("VFPCLASSSSZrik", LIEF::assembly::x86::OPCODE::VFPCLASSSSZrik) + .value("VFRCZPDYrm", LIEF::assembly::x86::OPCODE::VFRCZPDYrm) + .value("VFRCZPDYrr", LIEF::assembly::x86::OPCODE::VFRCZPDYrr) + .value("VFRCZPDrm", LIEF::assembly::x86::OPCODE::VFRCZPDrm) + .value("VFRCZPDrr", LIEF::assembly::x86::OPCODE::VFRCZPDrr) + .value("VFRCZPSYrm", LIEF::assembly::x86::OPCODE::VFRCZPSYrm) + .value("VFRCZPSYrr", LIEF::assembly::x86::OPCODE::VFRCZPSYrr) + .value("VFRCZPSrm", LIEF::assembly::x86::OPCODE::VFRCZPSrm) + .value("VFRCZPSrr", LIEF::assembly::x86::OPCODE::VFRCZPSrr) + .value("VFRCZSDrm", LIEF::assembly::x86::OPCODE::VFRCZSDrm) + .value("VFRCZSDrr", LIEF::assembly::x86::OPCODE::VFRCZSDrr) + .value("VFRCZSSrm", LIEF::assembly::x86::OPCODE::VFRCZSSrm) + .value("VFRCZSSrr", LIEF::assembly::x86::OPCODE::VFRCZSSrr) + .value("VGATHERDPDYrm", LIEF::assembly::x86::OPCODE::VGATHERDPDYrm) + .value("VGATHERDPDZ128rm", LIEF::assembly::x86::OPCODE::VGATHERDPDZ128rm) + .value("VGATHERDPDZ256rm", LIEF::assembly::x86::OPCODE::VGATHERDPDZ256rm) + .value("VGATHERDPDZrm", LIEF::assembly::x86::OPCODE::VGATHERDPDZrm) + .value("VGATHERDPDrm", LIEF::assembly::x86::OPCODE::VGATHERDPDrm) + .value("VGATHERDPSYrm", LIEF::assembly::x86::OPCODE::VGATHERDPSYrm) + .value("VGATHERDPSZ128rm", LIEF::assembly::x86::OPCODE::VGATHERDPSZ128rm) + .value("VGATHERDPSZ256rm", LIEF::assembly::x86::OPCODE::VGATHERDPSZ256rm) + .value("VGATHERDPSZrm", LIEF::assembly::x86::OPCODE::VGATHERDPSZrm) + .value("VGATHERDPSrm", LIEF::assembly::x86::OPCODE::VGATHERDPSrm) + .value("VGATHERPF0DPDm", LIEF::assembly::x86::OPCODE::VGATHERPF0DPDm) + .value("VGATHERPF0DPSm", LIEF::assembly::x86::OPCODE::VGATHERPF0DPSm) + .value("VGATHERPF0QPDm", LIEF::assembly::x86::OPCODE::VGATHERPF0QPDm) + .value("VGATHERPF0QPSm", LIEF::assembly::x86::OPCODE::VGATHERPF0QPSm) + .value("VGATHERPF1DPDm", LIEF::assembly::x86::OPCODE::VGATHERPF1DPDm) + .value("VGATHERPF1DPSm", LIEF::assembly::x86::OPCODE::VGATHERPF1DPSm) + .value("VGATHERPF1QPDm", LIEF::assembly::x86::OPCODE::VGATHERPF1QPDm) + .value("VGATHERPF1QPSm", LIEF::assembly::x86::OPCODE::VGATHERPF1QPSm) + .value("VGATHERQPDYrm", LIEF::assembly::x86::OPCODE::VGATHERQPDYrm) + .value("VGATHERQPDZ128rm", LIEF::assembly::x86::OPCODE::VGATHERQPDZ128rm) + .value("VGATHERQPDZ256rm", LIEF::assembly::x86::OPCODE::VGATHERQPDZ256rm) + .value("VGATHERQPDZrm", LIEF::assembly::x86::OPCODE::VGATHERQPDZrm) + .value("VGATHERQPDrm", LIEF::assembly::x86::OPCODE::VGATHERQPDrm) + .value("VGATHERQPSYrm", LIEF::assembly::x86::OPCODE::VGATHERQPSYrm) + .value("VGATHERQPSZ128rm", LIEF::assembly::x86::OPCODE::VGATHERQPSZ128rm) + .value("VGATHERQPSZ256rm", LIEF::assembly::x86::OPCODE::VGATHERQPSZ256rm) + .value("VGATHERQPSZrm", LIEF::assembly::x86::OPCODE::VGATHERQPSZrm) + .value("VGATHERQPSrm", LIEF::assembly::x86::OPCODE::VGATHERQPSrm) + .value("VGETEXPBF16Z128m", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128m) + .value("VGETEXPBF16Z128mb", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128mb) + .value("VGETEXPBF16Z128mbk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128mbk) + .value("VGETEXPBF16Z128mbkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128mbkz) + .value("VGETEXPBF16Z128mk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128mk) + .value("VGETEXPBF16Z128mkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128mkz) + .value("VGETEXPBF16Z128r", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128r) + .value("VGETEXPBF16Z128rk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128rk) + .value("VGETEXPBF16Z128rkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z128rkz) + .value("VGETEXPBF16Z256m", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256m) + .value("VGETEXPBF16Z256mb", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256mb) + .value("VGETEXPBF16Z256mbk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256mbk) + .value("VGETEXPBF16Z256mbkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256mbkz) + .value("VGETEXPBF16Z256mk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256mk) + .value("VGETEXPBF16Z256mkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256mkz) + .value("VGETEXPBF16Z256r", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256r) + .value("VGETEXPBF16Z256rk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256rk) + .value("VGETEXPBF16Z256rkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Z256rkz) + .value("VGETEXPBF16Zm", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zm) + .value("VGETEXPBF16Zmb", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zmb) + .value("VGETEXPBF16Zmbk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zmbk) + .value("VGETEXPBF16Zmbkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zmbkz) + .value("VGETEXPBF16Zmk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zmk) + .value("VGETEXPBF16Zmkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zmkz) + .value("VGETEXPBF16Zr", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zr) + .value("VGETEXPBF16Zrk", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zrk) + .value("VGETEXPBF16Zrkz", LIEF::assembly::x86::OPCODE::VGETEXPBF16Zrkz) + .value("VGETEXPPDZ128m", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128m) + .value("VGETEXPPDZ128mb", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128mb); + opcodes.value("VGETEXPPDZ128mbk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128mbk) + .value("VGETEXPPDZ128mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128mbkz) + .value("VGETEXPPDZ128mk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128mk) + .value("VGETEXPPDZ128mkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128mkz) + .value("VGETEXPPDZ128r", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128r) + .value("VGETEXPPDZ128rk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128rk) + .value("VGETEXPPDZ128rkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ128rkz) + .value("VGETEXPPDZ256m", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256m) + .value("VGETEXPPDZ256mb", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256mb) + .value("VGETEXPPDZ256mbk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256mbk) + .value("VGETEXPPDZ256mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256mbkz) + .value("VGETEXPPDZ256mk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256mk) + .value("VGETEXPPDZ256mkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256mkz) + .value("VGETEXPPDZ256r", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256r) + .value("VGETEXPPDZ256rk", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256rk) + .value("VGETEXPPDZ256rkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZ256rkz) + .value("VGETEXPPDZm", LIEF::assembly::x86::OPCODE::VGETEXPPDZm) + .value("VGETEXPPDZmb", LIEF::assembly::x86::OPCODE::VGETEXPPDZmb) + .value("VGETEXPPDZmbk", LIEF::assembly::x86::OPCODE::VGETEXPPDZmbk) + .value("VGETEXPPDZmbkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZmbkz) + .value("VGETEXPPDZmk", LIEF::assembly::x86::OPCODE::VGETEXPPDZmk) + .value("VGETEXPPDZmkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZmkz) + .value("VGETEXPPDZr", LIEF::assembly::x86::OPCODE::VGETEXPPDZr) + .value("VGETEXPPDZrb", LIEF::assembly::x86::OPCODE::VGETEXPPDZrb) + .value("VGETEXPPDZrbk", LIEF::assembly::x86::OPCODE::VGETEXPPDZrbk) + .value("VGETEXPPDZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZrbkz) + .value("VGETEXPPDZrk", LIEF::assembly::x86::OPCODE::VGETEXPPDZrk) + .value("VGETEXPPDZrkz", LIEF::assembly::x86::OPCODE::VGETEXPPDZrkz) + .value("VGETEXPPHZ128m", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128m) + .value("VGETEXPPHZ128mb", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128mb) + .value("VGETEXPPHZ128mbk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128mbk) + .value("VGETEXPPHZ128mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128mbkz) + .value("VGETEXPPHZ128mk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128mk) + .value("VGETEXPPHZ128mkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128mkz) + .value("VGETEXPPHZ128r", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128r) + .value("VGETEXPPHZ128rk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128rk) + .value("VGETEXPPHZ128rkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ128rkz) + .value("VGETEXPPHZ256m", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256m) + .value("VGETEXPPHZ256mb", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256mb) + .value("VGETEXPPHZ256mbk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256mbk) + .value("VGETEXPPHZ256mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256mbkz) + .value("VGETEXPPHZ256mk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256mk) + .value("VGETEXPPHZ256mkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256mkz) + .value("VGETEXPPHZ256r", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256r) + .value("VGETEXPPHZ256rk", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256rk) + .value("VGETEXPPHZ256rkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZ256rkz) + .value("VGETEXPPHZm", LIEF::assembly::x86::OPCODE::VGETEXPPHZm) + .value("VGETEXPPHZmb", LIEF::assembly::x86::OPCODE::VGETEXPPHZmb) + .value("VGETEXPPHZmbk", LIEF::assembly::x86::OPCODE::VGETEXPPHZmbk) + .value("VGETEXPPHZmbkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZmbkz) + .value("VGETEXPPHZmk", LIEF::assembly::x86::OPCODE::VGETEXPPHZmk) + .value("VGETEXPPHZmkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZmkz) + .value("VGETEXPPHZr", LIEF::assembly::x86::OPCODE::VGETEXPPHZr) + .value("VGETEXPPHZrb", LIEF::assembly::x86::OPCODE::VGETEXPPHZrb) + .value("VGETEXPPHZrbk", LIEF::assembly::x86::OPCODE::VGETEXPPHZrbk) + .value("VGETEXPPHZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZrbkz) + .value("VGETEXPPHZrk", LIEF::assembly::x86::OPCODE::VGETEXPPHZrk) + .value("VGETEXPPHZrkz", LIEF::assembly::x86::OPCODE::VGETEXPPHZrkz) + .value("VGETEXPPSZ128m", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128m) + .value("VGETEXPPSZ128mb", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128mb) + .value("VGETEXPPSZ128mbk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128mbk) + .value("VGETEXPPSZ128mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128mbkz) + .value("VGETEXPPSZ128mk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128mk) + .value("VGETEXPPSZ128mkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128mkz) + .value("VGETEXPPSZ128r", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128r) + .value("VGETEXPPSZ128rk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128rk) + .value("VGETEXPPSZ128rkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ128rkz) + .value("VGETEXPPSZ256m", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256m) + .value("VGETEXPPSZ256mb", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256mb) + .value("VGETEXPPSZ256mbk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256mbk) + .value("VGETEXPPSZ256mbkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256mbkz) + .value("VGETEXPPSZ256mk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256mk) + .value("VGETEXPPSZ256mkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256mkz) + .value("VGETEXPPSZ256r", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256r) + .value("VGETEXPPSZ256rk", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256rk) + .value("VGETEXPPSZ256rkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZ256rkz) + .value("VGETEXPPSZm", LIEF::assembly::x86::OPCODE::VGETEXPPSZm) + .value("VGETEXPPSZmb", LIEF::assembly::x86::OPCODE::VGETEXPPSZmb) + .value("VGETEXPPSZmbk", LIEF::assembly::x86::OPCODE::VGETEXPPSZmbk) + .value("VGETEXPPSZmbkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZmbkz) + .value("VGETEXPPSZmk", LIEF::assembly::x86::OPCODE::VGETEXPPSZmk) + .value("VGETEXPPSZmkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZmkz) + .value("VGETEXPPSZr", LIEF::assembly::x86::OPCODE::VGETEXPPSZr) + .value("VGETEXPPSZrb", LIEF::assembly::x86::OPCODE::VGETEXPPSZrb) + .value("VGETEXPPSZrbk", LIEF::assembly::x86::OPCODE::VGETEXPPSZrbk) + .value("VGETEXPPSZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZrbkz) + .value("VGETEXPPSZrk", LIEF::assembly::x86::OPCODE::VGETEXPPSZrk) + .value("VGETEXPPSZrkz", LIEF::assembly::x86::OPCODE::VGETEXPPSZrkz) + .value("VGETEXPSDZm", LIEF::assembly::x86::OPCODE::VGETEXPSDZm) + .value("VGETEXPSDZmk", LIEF::assembly::x86::OPCODE::VGETEXPSDZmk) + .value("VGETEXPSDZmkz", LIEF::assembly::x86::OPCODE::VGETEXPSDZmkz) + .value("VGETEXPSDZr", LIEF::assembly::x86::OPCODE::VGETEXPSDZr) + .value("VGETEXPSDZrb", LIEF::assembly::x86::OPCODE::VGETEXPSDZrb) + .value("VGETEXPSDZrbk", LIEF::assembly::x86::OPCODE::VGETEXPSDZrbk) + .value("VGETEXPSDZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPSDZrbkz) + .value("VGETEXPSDZrk", LIEF::assembly::x86::OPCODE::VGETEXPSDZrk) + .value("VGETEXPSDZrkz", LIEF::assembly::x86::OPCODE::VGETEXPSDZrkz) + .value("VGETEXPSHZm", LIEF::assembly::x86::OPCODE::VGETEXPSHZm) + .value("VGETEXPSHZmk", LIEF::assembly::x86::OPCODE::VGETEXPSHZmk) + .value("VGETEXPSHZmkz", LIEF::assembly::x86::OPCODE::VGETEXPSHZmkz) + .value("VGETEXPSHZr", LIEF::assembly::x86::OPCODE::VGETEXPSHZr) + .value("VGETEXPSHZrb", LIEF::assembly::x86::OPCODE::VGETEXPSHZrb) + .value("VGETEXPSHZrbk", LIEF::assembly::x86::OPCODE::VGETEXPSHZrbk) + .value("VGETEXPSHZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPSHZrbkz) + .value("VGETEXPSHZrk", LIEF::assembly::x86::OPCODE::VGETEXPSHZrk) + .value("VGETEXPSHZrkz", LIEF::assembly::x86::OPCODE::VGETEXPSHZrkz) + .value("VGETEXPSSZm", LIEF::assembly::x86::OPCODE::VGETEXPSSZm) + .value("VGETEXPSSZmk", LIEF::assembly::x86::OPCODE::VGETEXPSSZmk) + .value("VGETEXPSSZmkz", LIEF::assembly::x86::OPCODE::VGETEXPSSZmkz) + .value("VGETEXPSSZr", LIEF::assembly::x86::OPCODE::VGETEXPSSZr) + .value("VGETEXPSSZrb", LIEF::assembly::x86::OPCODE::VGETEXPSSZrb) + .value("VGETEXPSSZrbk", LIEF::assembly::x86::OPCODE::VGETEXPSSZrbk) + .value("VGETEXPSSZrbkz", LIEF::assembly::x86::OPCODE::VGETEXPSSZrbkz) + .value("VGETEXPSSZrk", LIEF::assembly::x86::OPCODE::VGETEXPSSZrk) + .value("VGETEXPSSZrkz", LIEF::assembly::x86::OPCODE::VGETEXPSSZrkz) + .value("VGETMANTBF16Z128rmbi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmbi) + .value("VGETMANTBF16Z128rmbik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmbik) + .value("VGETMANTBF16Z128rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmbikz) + .value("VGETMANTBF16Z128rmi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmi) + .value("VGETMANTBF16Z128rmik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmik) + .value("VGETMANTBF16Z128rmikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rmikz) + .value("VGETMANTBF16Z128rri", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rri) + .value("VGETMANTBF16Z128rrik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rrik) + .value("VGETMANTBF16Z128rrikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z128rrikz) + .value("VGETMANTBF16Z256rmbi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmbi) + .value("VGETMANTBF16Z256rmbik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmbik) + .value("VGETMANTBF16Z256rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmbikz) + .value("VGETMANTBF16Z256rmi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmi) + .value("VGETMANTBF16Z256rmik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmik) + .value("VGETMANTBF16Z256rmikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rmikz) + .value("VGETMANTBF16Z256rri", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rri) + .value("VGETMANTBF16Z256rrik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rrik) + .value("VGETMANTBF16Z256rrikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Z256rrikz) + .value("VGETMANTBF16Zrmbi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmbi) + .value("VGETMANTBF16Zrmbik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmbik) + .value("VGETMANTBF16Zrmbikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmbikz) + .value("VGETMANTBF16Zrmi", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmi) + .value("VGETMANTBF16Zrmik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmik) + .value("VGETMANTBF16Zrmikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrmikz) + .value("VGETMANTBF16Zrri", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrri) + .value("VGETMANTBF16Zrrik", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrrik) + .value("VGETMANTBF16Zrrikz", LIEF::assembly::x86::OPCODE::VGETMANTBF16Zrrikz) + .value("VGETMANTPDZ128rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmbi) + .value("VGETMANTPDZ128rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmbik) + .value("VGETMANTPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmbikz) + .value("VGETMANTPDZ128rmi", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmi) + .value("VGETMANTPDZ128rmik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmik) + .value("VGETMANTPDZ128rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rmikz) + .value("VGETMANTPDZ128rri", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rri) + .value("VGETMANTPDZ128rrik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rrik) + .value("VGETMANTPDZ128rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ128rrikz) + .value("VGETMANTPDZ256rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmbi) + .value("VGETMANTPDZ256rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmbik) + .value("VGETMANTPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmbikz) + .value("VGETMANTPDZ256rmi", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmi) + .value("VGETMANTPDZ256rmik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmik) + .value("VGETMANTPDZ256rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rmikz) + .value("VGETMANTPDZ256rri", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rri) + .value("VGETMANTPDZ256rrik", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rrik) + .value("VGETMANTPDZ256rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZ256rrikz) + .value("VGETMANTPDZrmbi", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmbi) + .value("VGETMANTPDZrmbik", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmbik) + .value("VGETMANTPDZrmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmbikz) + .value("VGETMANTPDZrmi", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmi) + .value("VGETMANTPDZrmik", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmik) + .value("VGETMANTPDZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZrmikz) + .value("VGETMANTPDZrri", LIEF::assembly::x86::OPCODE::VGETMANTPDZrri) + .value("VGETMANTPDZrrib", LIEF::assembly::x86::OPCODE::VGETMANTPDZrrib) + .value("VGETMANTPDZrribk", LIEF::assembly::x86::OPCODE::VGETMANTPDZrribk) + .value("VGETMANTPDZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTPDZrribkz) + .value("VGETMANTPDZrrik", LIEF::assembly::x86::OPCODE::VGETMANTPDZrrik) + .value("VGETMANTPDZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTPDZrrikz) + .value("VGETMANTPHZ128rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmbi) + .value("VGETMANTPHZ128rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmbik) + .value("VGETMANTPHZ128rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmbikz) + .value("VGETMANTPHZ128rmi", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmi) + .value("VGETMANTPHZ128rmik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmik) + .value("VGETMANTPHZ128rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rmikz) + .value("VGETMANTPHZ128rri", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rri) + .value("VGETMANTPHZ128rrik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rrik) + .value("VGETMANTPHZ128rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ128rrikz) + .value("VGETMANTPHZ256rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmbi) + .value("VGETMANTPHZ256rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmbik) + .value("VGETMANTPHZ256rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmbikz) + .value("VGETMANTPHZ256rmi", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmi) + .value("VGETMANTPHZ256rmik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmik) + .value("VGETMANTPHZ256rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rmikz) + .value("VGETMANTPHZ256rri", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rri) + .value("VGETMANTPHZ256rrik", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rrik) + .value("VGETMANTPHZ256rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZ256rrikz) + .value("VGETMANTPHZrmbi", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmbi) + .value("VGETMANTPHZrmbik", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmbik) + .value("VGETMANTPHZrmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmbikz) + .value("VGETMANTPHZrmi", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmi) + .value("VGETMANTPHZrmik", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmik) + .value("VGETMANTPHZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZrmikz) + .value("VGETMANTPHZrri", LIEF::assembly::x86::OPCODE::VGETMANTPHZrri) + .value("VGETMANTPHZrrib", LIEF::assembly::x86::OPCODE::VGETMANTPHZrrib) + .value("VGETMANTPHZrribk", LIEF::assembly::x86::OPCODE::VGETMANTPHZrribk) + .value("VGETMANTPHZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTPHZrribkz) + .value("VGETMANTPHZrrik", LIEF::assembly::x86::OPCODE::VGETMANTPHZrrik) + .value("VGETMANTPHZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTPHZrrikz) + .value("VGETMANTPSZ128rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmbi) + .value("VGETMANTPSZ128rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmbik) + .value("VGETMANTPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmbikz) + .value("VGETMANTPSZ128rmi", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmi) + .value("VGETMANTPSZ128rmik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmik) + .value("VGETMANTPSZ128rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rmikz) + .value("VGETMANTPSZ128rri", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rri) + .value("VGETMANTPSZ128rrik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rrik) + .value("VGETMANTPSZ128rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ128rrikz) + .value("VGETMANTPSZ256rmbi", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmbi) + .value("VGETMANTPSZ256rmbik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmbik) + .value("VGETMANTPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmbikz) + .value("VGETMANTPSZ256rmi", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmi) + .value("VGETMANTPSZ256rmik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmik) + .value("VGETMANTPSZ256rmikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rmikz) + .value("VGETMANTPSZ256rri", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rri) + .value("VGETMANTPSZ256rrik", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rrik) + .value("VGETMANTPSZ256rrikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZ256rrikz) + .value("VGETMANTPSZrmbi", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmbi) + .value("VGETMANTPSZrmbik", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmbik) + .value("VGETMANTPSZrmbikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmbikz) + .value("VGETMANTPSZrmi", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmi) + .value("VGETMANTPSZrmik", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmik) + .value("VGETMANTPSZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZrmikz) + .value("VGETMANTPSZrri", LIEF::assembly::x86::OPCODE::VGETMANTPSZrri) + .value("VGETMANTPSZrrib", LIEF::assembly::x86::OPCODE::VGETMANTPSZrrib) + .value("VGETMANTPSZrribk", LIEF::assembly::x86::OPCODE::VGETMANTPSZrribk) + .value("VGETMANTPSZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTPSZrribkz) + .value("VGETMANTPSZrrik", LIEF::assembly::x86::OPCODE::VGETMANTPSZrrik) + .value("VGETMANTPSZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTPSZrrikz) + .value("VGETMANTSDZrmi", LIEF::assembly::x86::OPCODE::VGETMANTSDZrmi) + .value("VGETMANTSDZrmik", LIEF::assembly::x86::OPCODE::VGETMANTSDZrmik) + .value("VGETMANTSDZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTSDZrmikz) + .value("VGETMANTSDZrri", LIEF::assembly::x86::OPCODE::VGETMANTSDZrri) + .value("VGETMANTSDZrrib", LIEF::assembly::x86::OPCODE::VGETMANTSDZrrib) + .value("VGETMANTSDZrribk", LIEF::assembly::x86::OPCODE::VGETMANTSDZrribk) + .value("VGETMANTSDZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTSDZrribkz) + .value("VGETMANTSDZrrik", LIEF::assembly::x86::OPCODE::VGETMANTSDZrrik) + .value("VGETMANTSDZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTSDZrrikz) + .value("VGETMANTSHZrmi", LIEF::assembly::x86::OPCODE::VGETMANTSHZrmi) + .value("VGETMANTSHZrmik", LIEF::assembly::x86::OPCODE::VGETMANTSHZrmik) + .value("VGETMANTSHZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTSHZrmikz) + .value("VGETMANTSHZrri", LIEF::assembly::x86::OPCODE::VGETMANTSHZrri) + .value("VGETMANTSHZrrib", LIEF::assembly::x86::OPCODE::VGETMANTSHZrrib) + .value("VGETMANTSHZrribk", LIEF::assembly::x86::OPCODE::VGETMANTSHZrribk) + .value("VGETMANTSHZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTSHZrribkz) + .value("VGETMANTSHZrrik", LIEF::assembly::x86::OPCODE::VGETMANTSHZrrik) + .value("VGETMANTSHZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTSHZrrikz) + .value("VGETMANTSSZrmi", LIEF::assembly::x86::OPCODE::VGETMANTSSZrmi) + .value("VGETMANTSSZrmik", LIEF::assembly::x86::OPCODE::VGETMANTSSZrmik) + .value("VGETMANTSSZrmikz", LIEF::assembly::x86::OPCODE::VGETMANTSSZrmikz) + .value("VGETMANTSSZrri", LIEF::assembly::x86::OPCODE::VGETMANTSSZrri) + .value("VGETMANTSSZrrib", LIEF::assembly::x86::OPCODE::VGETMANTSSZrrib) + .value("VGETMANTSSZrribk", LIEF::assembly::x86::OPCODE::VGETMANTSSZrribk) + .value("VGETMANTSSZrribkz", LIEF::assembly::x86::OPCODE::VGETMANTSSZrribkz) + .value("VGETMANTSSZrrik", LIEF::assembly::x86::OPCODE::VGETMANTSSZrrik) + .value("VGETMANTSSZrrikz", LIEF::assembly::x86::OPCODE::VGETMANTSSZrrikz) + .value("VGF2P8AFFINEINVQBYrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBYrmi) + .value("VGF2P8AFFINEINVQBYrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBYrri) + .value("VGF2P8AFFINEINVQBZ128rmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmbi) + .value("VGF2P8AFFINEINVQBZ128rmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmbik) + .value("VGF2P8AFFINEINVQBZ128rmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmbikz) + .value("VGF2P8AFFINEINVQBZ128rmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmi) + .value("VGF2P8AFFINEINVQBZ128rmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmik) + .value("VGF2P8AFFINEINVQBZ128rmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rmikz) + .value("VGF2P8AFFINEINVQBZ128rri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rri) + .value("VGF2P8AFFINEINVQBZ128rrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rrik) + .value("VGF2P8AFFINEINVQBZ128rrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ128rrikz) + .value("VGF2P8AFFINEINVQBZ256rmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmbi) + .value("VGF2P8AFFINEINVQBZ256rmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmbik) + .value("VGF2P8AFFINEINVQBZ256rmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmbikz) + .value("VGF2P8AFFINEINVQBZ256rmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmi) + .value("VGF2P8AFFINEINVQBZ256rmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmik) + .value("VGF2P8AFFINEINVQBZ256rmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rmikz) + .value("VGF2P8AFFINEINVQBZ256rri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rri) + .value("VGF2P8AFFINEINVQBZ256rrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rrik) + .value("VGF2P8AFFINEINVQBZ256rrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZ256rrikz) + .value("VGF2P8AFFINEINVQBZrmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmbi) + .value("VGF2P8AFFINEINVQBZrmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmbik) + .value("VGF2P8AFFINEINVQBZrmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmbikz) + .value("VGF2P8AFFINEINVQBZrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmi) + .value("VGF2P8AFFINEINVQBZrmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmik) + .value("VGF2P8AFFINEINVQBZrmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrmikz) + .value("VGF2P8AFFINEINVQBZrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrri) + .value("VGF2P8AFFINEINVQBZrrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrrik) + .value("VGF2P8AFFINEINVQBZrrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBZrrikz) + .value("VGF2P8AFFINEINVQBrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBrmi) + .value("VGF2P8AFFINEINVQBrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEINVQBrri) + .value("VGF2P8AFFINEQBYrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBYrmi) + .value("VGF2P8AFFINEQBYrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBYrri) + .value("VGF2P8AFFINEQBZ128rmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmbi) + .value("VGF2P8AFFINEQBZ128rmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmbik) + .value("VGF2P8AFFINEQBZ128rmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmbikz) + .value("VGF2P8AFFINEQBZ128rmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmi) + .value("VGF2P8AFFINEQBZ128rmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmik) + .value("VGF2P8AFFINEQBZ128rmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rmikz) + .value("VGF2P8AFFINEQBZ128rri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rri) + .value("VGF2P8AFFINEQBZ128rrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rrik); + opcodes.value("VGF2P8AFFINEQBZ128rrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ128rrikz) + .value("VGF2P8AFFINEQBZ256rmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmbi) + .value("VGF2P8AFFINEQBZ256rmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmbik) + .value("VGF2P8AFFINEQBZ256rmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmbikz) + .value("VGF2P8AFFINEQBZ256rmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmi) + .value("VGF2P8AFFINEQBZ256rmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmik) + .value("VGF2P8AFFINEQBZ256rmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rmikz) + .value("VGF2P8AFFINEQBZ256rri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rri) + .value("VGF2P8AFFINEQBZ256rrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rrik) + .value("VGF2P8AFFINEQBZ256rrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZ256rrikz) + .value("VGF2P8AFFINEQBZrmbi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmbi) + .value("VGF2P8AFFINEQBZrmbik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmbik) + .value("VGF2P8AFFINEQBZrmbikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmbikz) + .value("VGF2P8AFFINEQBZrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmi) + .value("VGF2P8AFFINEQBZrmik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmik) + .value("VGF2P8AFFINEQBZrmikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrmikz) + .value("VGF2P8AFFINEQBZrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrri) + .value("VGF2P8AFFINEQBZrrik", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrrik) + .value("VGF2P8AFFINEQBZrrikz", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBZrrikz) + .value("VGF2P8AFFINEQBrmi", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBrmi) + .value("VGF2P8AFFINEQBrri", LIEF::assembly::x86::OPCODE::VGF2P8AFFINEQBrri) + .value("VGF2P8MULBYrm", LIEF::assembly::x86::OPCODE::VGF2P8MULBYrm) + .value("VGF2P8MULBYrr", LIEF::assembly::x86::OPCODE::VGF2P8MULBYrr) + .value("VGF2P8MULBZ128rm", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rm) + .value("VGF2P8MULBZ128rmk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rmk) + .value("VGF2P8MULBZ128rmkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rmkz) + .value("VGF2P8MULBZ128rr", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rr) + .value("VGF2P8MULBZ128rrk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rrk) + .value("VGF2P8MULBZ128rrkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ128rrkz) + .value("VGF2P8MULBZ256rm", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rm) + .value("VGF2P8MULBZ256rmk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rmk) + .value("VGF2P8MULBZ256rmkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rmkz) + .value("VGF2P8MULBZ256rr", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rr) + .value("VGF2P8MULBZ256rrk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rrk) + .value("VGF2P8MULBZ256rrkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZ256rrkz) + .value("VGF2P8MULBZrm", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrm) + .value("VGF2P8MULBZrmk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrmk) + .value("VGF2P8MULBZrmkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrmkz) + .value("VGF2P8MULBZrr", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrr) + .value("VGF2P8MULBZrrk", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrrk) + .value("VGF2P8MULBZrrkz", LIEF::assembly::x86::OPCODE::VGF2P8MULBZrrkz) + .value("VGF2P8MULBrm", LIEF::assembly::x86::OPCODE::VGF2P8MULBrm) + .value("VGF2P8MULBrr", LIEF::assembly::x86::OPCODE::VGF2P8MULBrr) + .value("VHADDPDYrm", LIEF::assembly::x86::OPCODE::VHADDPDYrm) + .value("VHADDPDYrr", LIEF::assembly::x86::OPCODE::VHADDPDYrr) + .value("VHADDPDrm", LIEF::assembly::x86::OPCODE::VHADDPDrm) + .value("VHADDPDrr", LIEF::assembly::x86::OPCODE::VHADDPDrr) + .value("VHADDPSYrm", LIEF::assembly::x86::OPCODE::VHADDPSYrm) + .value("VHADDPSYrr", LIEF::assembly::x86::OPCODE::VHADDPSYrr) + .value("VHADDPSrm", LIEF::assembly::x86::OPCODE::VHADDPSrm) + .value("VHADDPSrr", LIEF::assembly::x86::OPCODE::VHADDPSrr) + .value("VHSUBPDYrm", LIEF::assembly::x86::OPCODE::VHSUBPDYrm) + .value("VHSUBPDYrr", LIEF::assembly::x86::OPCODE::VHSUBPDYrr) + .value("VHSUBPDrm", LIEF::assembly::x86::OPCODE::VHSUBPDrm) + .value("VHSUBPDrr", LIEF::assembly::x86::OPCODE::VHSUBPDrr) + .value("VHSUBPSYrm", LIEF::assembly::x86::OPCODE::VHSUBPSYrm) + .value("VHSUBPSYrr", LIEF::assembly::x86::OPCODE::VHSUBPSYrr) + .value("VHSUBPSrm", LIEF::assembly::x86::OPCODE::VHSUBPSrm) + .value("VHSUBPSrr", LIEF::assembly::x86::OPCODE::VHSUBPSrr) + .value("VINSERTF128rmi", LIEF::assembly::x86::OPCODE::VINSERTF128rmi) + .value("VINSERTF128rri", LIEF::assembly::x86::OPCODE::VINSERTF128rri) + .value("VINSERTF32X4Z256rmi", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rmi) + .value("VINSERTF32X4Z256rmik", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rmik) + .value("VINSERTF32X4Z256rmikz", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rmikz) + .value("VINSERTF32X4Z256rri", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rri) + .value("VINSERTF32X4Z256rrik", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rrik) + .value("VINSERTF32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VINSERTF32X4Z256rrikz) + .value("VINSERTF32X4Zrmi", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrmi) + .value("VINSERTF32X4Zrmik", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrmik) + .value("VINSERTF32X4Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrmikz) + .value("VINSERTF32X4Zrri", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrri) + .value("VINSERTF32X4Zrrik", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrrik) + .value("VINSERTF32X4Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTF32X4Zrrikz) + .value("VINSERTF32X8Zrmi", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrmi) + .value("VINSERTF32X8Zrmik", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrmik) + .value("VINSERTF32X8Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrmikz) + .value("VINSERTF32X8Zrri", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrri) + .value("VINSERTF32X8Zrrik", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrrik) + .value("VINSERTF32X8Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTF32X8Zrrikz) + .value("VINSERTF64X2Z256rmi", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rmi) + .value("VINSERTF64X2Z256rmik", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rmik) + .value("VINSERTF64X2Z256rmikz", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rmikz) + .value("VINSERTF64X2Z256rri", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rri) + .value("VINSERTF64X2Z256rrik", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rrik) + .value("VINSERTF64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VINSERTF64X2Z256rrikz) + .value("VINSERTF64X2Zrmi", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrmi) + .value("VINSERTF64X2Zrmik", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrmik) + .value("VINSERTF64X2Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrmikz) + .value("VINSERTF64X2Zrri", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrri) + .value("VINSERTF64X2Zrrik", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrrik) + .value("VINSERTF64X2Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTF64X2Zrrikz) + .value("VINSERTF64X4Zrmi", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrmi) + .value("VINSERTF64X4Zrmik", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrmik) + .value("VINSERTF64X4Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrmikz) + .value("VINSERTF64X4Zrri", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrri) + .value("VINSERTF64X4Zrrik", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrrik) + .value("VINSERTF64X4Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTF64X4Zrrikz) + .value("VINSERTI128rmi", LIEF::assembly::x86::OPCODE::VINSERTI128rmi) + .value("VINSERTI128rri", LIEF::assembly::x86::OPCODE::VINSERTI128rri) + .value("VINSERTI32X4Z256rmi", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rmi) + .value("VINSERTI32X4Z256rmik", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rmik) + .value("VINSERTI32X4Z256rmikz", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rmikz) + .value("VINSERTI32X4Z256rri", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rri) + .value("VINSERTI32X4Z256rrik", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rrik) + .value("VINSERTI32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VINSERTI32X4Z256rrikz) + .value("VINSERTI32X4Zrmi", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrmi) + .value("VINSERTI32X4Zrmik", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrmik) + .value("VINSERTI32X4Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrmikz) + .value("VINSERTI32X4Zrri", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrri) + .value("VINSERTI32X4Zrrik", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrrik) + .value("VINSERTI32X4Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTI32X4Zrrikz) + .value("VINSERTI32X8Zrmi", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrmi) + .value("VINSERTI32X8Zrmik", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrmik) + .value("VINSERTI32X8Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrmikz) + .value("VINSERTI32X8Zrri", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrri) + .value("VINSERTI32X8Zrrik", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrrik) + .value("VINSERTI32X8Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTI32X8Zrrikz) + .value("VINSERTI64X2Z256rmi", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rmi) + .value("VINSERTI64X2Z256rmik", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rmik) + .value("VINSERTI64X2Z256rmikz", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rmikz) + .value("VINSERTI64X2Z256rri", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rri) + .value("VINSERTI64X2Z256rrik", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rrik) + .value("VINSERTI64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VINSERTI64X2Z256rrikz) + .value("VINSERTI64X2Zrmi", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrmi) + .value("VINSERTI64X2Zrmik", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrmik) + .value("VINSERTI64X2Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrmikz) + .value("VINSERTI64X2Zrri", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrri) + .value("VINSERTI64X2Zrrik", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrrik) + .value("VINSERTI64X2Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTI64X2Zrrikz) + .value("VINSERTI64X4Zrmi", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrmi) + .value("VINSERTI64X4Zrmik", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrmik) + .value("VINSERTI64X4Zrmikz", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrmikz) + .value("VINSERTI64X4Zrri", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrri) + .value("VINSERTI64X4Zrrik", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrrik) + .value("VINSERTI64X4Zrrikz", LIEF::assembly::x86::OPCODE::VINSERTI64X4Zrrikz) + .value("VINSERTPSZrmi", LIEF::assembly::x86::OPCODE::VINSERTPSZrmi) + .value("VINSERTPSZrri", LIEF::assembly::x86::OPCODE::VINSERTPSZrri) + .value("VINSERTPSrmi", LIEF::assembly::x86::OPCODE::VINSERTPSrmi) + .value("VINSERTPSrri", LIEF::assembly::x86::OPCODE::VINSERTPSrri) + .value("VLDDQUYrm", LIEF::assembly::x86::OPCODE::VLDDQUYrm) + .value("VLDDQUrm", LIEF::assembly::x86::OPCODE::VLDDQUrm) + .value("VLDMXCSR", LIEF::assembly::x86::OPCODE::VLDMXCSR) + .value("VMASKMOVDQU", LIEF::assembly::x86::OPCODE::VMASKMOVDQU) + .value("VMASKMOVDQU64", LIEF::assembly::x86::OPCODE::VMASKMOVDQU64) + .value("VMASKMOVPDYmr", LIEF::assembly::x86::OPCODE::VMASKMOVPDYmr) + .value("VMASKMOVPDYrm", LIEF::assembly::x86::OPCODE::VMASKMOVPDYrm) + .value("VMASKMOVPDmr", LIEF::assembly::x86::OPCODE::VMASKMOVPDmr) + .value("VMASKMOVPDrm", LIEF::assembly::x86::OPCODE::VMASKMOVPDrm) + .value("VMASKMOVPSYmr", LIEF::assembly::x86::OPCODE::VMASKMOVPSYmr) + .value("VMASKMOVPSYrm", LIEF::assembly::x86::OPCODE::VMASKMOVPSYrm) + .value("VMASKMOVPSmr", LIEF::assembly::x86::OPCODE::VMASKMOVPSmr) + .value("VMASKMOVPSrm", LIEF::assembly::x86::OPCODE::VMASKMOVPSrm) + .value("VMAXBF16Z128rm", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rm) + .value("VMAXBF16Z128rmb", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rmb) + .value("VMAXBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rmbk) + .value("VMAXBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rmbkz) + .value("VMAXBF16Z128rmk", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rmk) + .value("VMAXBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rmkz) + .value("VMAXBF16Z128rr", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rr) + .value("VMAXBF16Z128rrk", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rrk) + .value("VMAXBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z128rrkz) + .value("VMAXBF16Z256rm", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rm) + .value("VMAXBF16Z256rmb", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rmb) + .value("VMAXBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rmbk) + .value("VMAXBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rmbkz) + .value("VMAXBF16Z256rmk", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rmk) + .value("VMAXBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rmkz) + .value("VMAXBF16Z256rr", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rr) + .value("VMAXBF16Z256rrk", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rrk) + .value("VMAXBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VMAXBF16Z256rrkz) + .value("VMAXBF16Zrm", LIEF::assembly::x86::OPCODE::VMAXBF16Zrm) + .value("VMAXBF16Zrmb", LIEF::assembly::x86::OPCODE::VMAXBF16Zrmb) + .value("VMAXBF16Zrmbk", LIEF::assembly::x86::OPCODE::VMAXBF16Zrmbk) + .value("VMAXBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VMAXBF16Zrmbkz) + .value("VMAXBF16Zrmk", LIEF::assembly::x86::OPCODE::VMAXBF16Zrmk) + .value("VMAXBF16Zrmkz", LIEF::assembly::x86::OPCODE::VMAXBF16Zrmkz) + .value("VMAXBF16Zrr", LIEF::assembly::x86::OPCODE::VMAXBF16Zrr) + .value("VMAXBF16Zrrk", LIEF::assembly::x86::OPCODE::VMAXBF16Zrrk) + .value("VMAXBF16Zrrkz", LIEF::assembly::x86::OPCODE::VMAXBF16Zrrkz) + .value("VMAXCPDYrm", LIEF::assembly::x86::OPCODE::VMAXCPDYrm) + .value("VMAXCPDYrr", LIEF::assembly::x86::OPCODE::VMAXCPDYrr) + .value("VMAXCPDZ128rm", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rm) + .value("VMAXCPDZ128rmb", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rmb) + .value("VMAXCPDZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rmbk) + .value("VMAXCPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rmbkz) + .value("VMAXCPDZ128rmk", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rmk) + .value("VMAXCPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rmkz) + .value("VMAXCPDZ128rr", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rr) + .value("VMAXCPDZ128rrk", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rrk) + .value("VMAXCPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ128rrkz) + .value("VMAXCPDZ256rm", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rm) + .value("VMAXCPDZ256rmb", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rmb) + .value("VMAXCPDZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rmbk) + .value("VMAXCPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rmbkz) + .value("VMAXCPDZ256rmk", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rmk) + .value("VMAXCPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rmkz) + .value("VMAXCPDZ256rr", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rr) + .value("VMAXCPDZ256rrk", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rrk) + .value("VMAXCPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXCPDZ256rrkz) + .value("VMAXCPDZrm", LIEF::assembly::x86::OPCODE::VMAXCPDZrm) + .value("VMAXCPDZrmb", LIEF::assembly::x86::OPCODE::VMAXCPDZrmb) + .value("VMAXCPDZrmbk", LIEF::assembly::x86::OPCODE::VMAXCPDZrmbk) + .value("VMAXCPDZrmbkz", LIEF::assembly::x86::OPCODE::VMAXCPDZrmbkz) + .value("VMAXCPDZrmk", LIEF::assembly::x86::OPCODE::VMAXCPDZrmk) + .value("VMAXCPDZrmkz", LIEF::assembly::x86::OPCODE::VMAXCPDZrmkz) + .value("VMAXCPDZrr", LIEF::assembly::x86::OPCODE::VMAXCPDZrr) + .value("VMAXCPDZrrk", LIEF::assembly::x86::OPCODE::VMAXCPDZrrk) + .value("VMAXCPDZrrkz", LIEF::assembly::x86::OPCODE::VMAXCPDZrrkz) + .value("VMAXCPDrm", LIEF::assembly::x86::OPCODE::VMAXCPDrm) + .value("VMAXCPDrr", LIEF::assembly::x86::OPCODE::VMAXCPDrr) + .value("VMAXCPHZ128rm", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rm) + .value("VMAXCPHZ128rmb", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rmb) + .value("VMAXCPHZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rmbk) + .value("VMAXCPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rmbkz) + .value("VMAXCPHZ128rmk", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rmk) + .value("VMAXCPHZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rmkz) + .value("VMAXCPHZ128rr", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rr) + .value("VMAXCPHZ128rrk", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rrk) + .value("VMAXCPHZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ128rrkz) + .value("VMAXCPHZ256rm", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rm) + .value("VMAXCPHZ256rmb", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rmb) + .value("VMAXCPHZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rmbk) + .value("VMAXCPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rmbkz) + .value("VMAXCPHZ256rmk", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rmk) + .value("VMAXCPHZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rmkz) + .value("VMAXCPHZ256rr", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rr) + .value("VMAXCPHZ256rrk", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rrk) + .value("VMAXCPHZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXCPHZ256rrkz) + .value("VMAXCPHZrm", LIEF::assembly::x86::OPCODE::VMAXCPHZrm) + .value("VMAXCPHZrmb", LIEF::assembly::x86::OPCODE::VMAXCPHZrmb) + .value("VMAXCPHZrmbk", LIEF::assembly::x86::OPCODE::VMAXCPHZrmbk) + .value("VMAXCPHZrmbkz", LIEF::assembly::x86::OPCODE::VMAXCPHZrmbkz) + .value("VMAXCPHZrmk", LIEF::assembly::x86::OPCODE::VMAXCPHZrmk) + .value("VMAXCPHZrmkz", LIEF::assembly::x86::OPCODE::VMAXCPHZrmkz) + .value("VMAXCPHZrr", LIEF::assembly::x86::OPCODE::VMAXCPHZrr) + .value("VMAXCPHZrrk", LIEF::assembly::x86::OPCODE::VMAXCPHZrrk) + .value("VMAXCPHZrrkz", LIEF::assembly::x86::OPCODE::VMAXCPHZrrkz) + .value("VMAXCPSYrm", LIEF::assembly::x86::OPCODE::VMAXCPSYrm) + .value("VMAXCPSYrr", LIEF::assembly::x86::OPCODE::VMAXCPSYrr) + .value("VMAXCPSZ128rm", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rm) + .value("VMAXCPSZ128rmb", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rmb) + .value("VMAXCPSZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rmbk) + .value("VMAXCPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rmbkz) + .value("VMAXCPSZ128rmk", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rmk) + .value("VMAXCPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rmkz) + .value("VMAXCPSZ128rr", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rr) + .value("VMAXCPSZ128rrk", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rrk) + .value("VMAXCPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ128rrkz) + .value("VMAXCPSZ256rm", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rm) + .value("VMAXCPSZ256rmb", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rmb) + .value("VMAXCPSZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rmbk) + .value("VMAXCPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rmbkz) + .value("VMAXCPSZ256rmk", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rmk) + .value("VMAXCPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rmkz) + .value("VMAXCPSZ256rr", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rr) + .value("VMAXCPSZ256rrk", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rrk) + .value("VMAXCPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXCPSZ256rrkz) + .value("VMAXCPSZrm", LIEF::assembly::x86::OPCODE::VMAXCPSZrm) + .value("VMAXCPSZrmb", LIEF::assembly::x86::OPCODE::VMAXCPSZrmb) + .value("VMAXCPSZrmbk", LIEF::assembly::x86::OPCODE::VMAXCPSZrmbk) + .value("VMAXCPSZrmbkz", LIEF::assembly::x86::OPCODE::VMAXCPSZrmbkz) + .value("VMAXCPSZrmk", LIEF::assembly::x86::OPCODE::VMAXCPSZrmk) + .value("VMAXCPSZrmkz", LIEF::assembly::x86::OPCODE::VMAXCPSZrmkz) + .value("VMAXCPSZrr", LIEF::assembly::x86::OPCODE::VMAXCPSZrr) + .value("VMAXCPSZrrk", LIEF::assembly::x86::OPCODE::VMAXCPSZrrk) + .value("VMAXCPSZrrkz", LIEF::assembly::x86::OPCODE::VMAXCPSZrrkz) + .value("VMAXCPSrm", LIEF::assembly::x86::OPCODE::VMAXCPSrm) + .value("VMAXCPSrr", LIEF::assembly::x86::OPCODE::VMAXCPSrr) + .value("VMAXCSDZrm", LIEF::assembly::x86::OPCODE::VMAXCSDZrm) + .value("VMAXCSDZrr", LIEF::assembly::x86::OPCODE::VMAXCSDZrr) + .value("VMAXCSDrm", LIEF::assembly::x86::OPCODE::VMAXCSDrm) + .value("VMAXCSDrr", LIEF::assembly::x86::OPCODE::VMAXCSDrr) + .value("VMAXCSHZrm", LIEF::assembly::x86::OPCODE::VMAXCSHZrm) + .value("VMAXCSHZrr", LIEF::assembly::x86::OPCODE::VMAXCSHZrr) + .value("VMAXCSSZrm", LIEF::assembly::x86::OPCODE::VMAXCSSZrm) + .value("VMAXCSSZrr", LIEF::assembly::x86::OPCODE::VMAXCSSZrr) + .value("VMAXCSSrm", LIEF::assembly::x86::OPCODE::VMAXCSSrm) + .value("VMAXCSSrr", LIEF::assembly::x86::OPCODE::VMAXCSSrr) + .value("VMAXPDYrm", LIEF::assembly::x86::OPCODE::VMAXPDYrm) + .value("VMAXPDYrr", LIEF::assembly::x86::OPCODE::VMAXPDYrr) + .value("VMAXPDZ128rm", LIEF::assembly::x86::OPCODE::VMAXPDZ128rm) + .value("VMAXPDZ128rmb", LIEF::assembly::x86::OPCODE::VMAXPDZ128rmb) + .value("VMAXPDZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXPDZ128rmbk) + .value("VMAXPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXPDZ128rmbkz) + .value("VMAXPDZ128rmk", LIEF::assembly::x86::OPCODE::VMAXPDZ128rmk) + .value("VMAXPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXPDZ128rmkz) + .value("VMAXPDZ128rr", LIEF::assembly::x86::OPCODE::VMAXPDZ128rr) + .value("VMAXPDZ128rrk", LIEF::assembly::x86::OPCODE::VMAXPDZ128rrk) + .value("VMAXPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXPDZ128rrkz) + .value("VMAXPDZ256rm", LIEF::assembly::x86::OPCODE::VMAXPDZ256rm) + .value("VMAXPDZ256rmb", LIEF::assembly::x86::OPCODE::VMAXPDZ256rmb) + .value("VMAXPDZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXPDZ256rmbk) + .value("VMAXPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXPDZ256rmbkz) + .value("VMAXPDZ256rmk", LIEF::assembly::x86::OPCODE::VMAXPDZ256rmk) + .value("VMAXPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXPDZ256rmkz) + .value("VMAXPDZ256rr", LIEF::assembly::x86::OPCODE::VMAXPDZ256rr) + .value("VMAXPDZ256rrk", LIEF::assembly::x86::OPCODE::VMAXPDZ256rrk) + .value("VMAXPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXPDZ256rrkz) + .value("VMAXPDZrm", LIEF::assembly::x86::OPCODE::VMAXPDZrm) + .value("VMAXPDZrmb", LIEF::assembly::x86::OPCODE::VMAXPDZrmb); + opcodes.value("VMAXPDZrmbk", LIEF::assembly::x86::OPCODE::VMAXPDZrmbk) + .value("VMAXPDZrmbkz", LIEF::assembly::x86::OPCODE::VMAXPDZrmbkz) + .value("VMAXPDZrmk", LIEF::assembly::x86::OPCODE::VMAXPDZrmk) + .value("VMAXPDZrmkz", LIEF::assembly::x86::OPCODE::VMAXPDZrmkz) + .value("VMAXPDZrr", LIEF::assembly::x86::OPCODE::VMAXPDZrr) + .value("VMAXPDZrrb", LIEF::assembly::x86::OPCODE::VMAXPDZrrb) + .value("VMAXPDZrrbk", LIEF::assembly::x86::OPCODE::VMAXPDZrrbk) + .value("VMAXPDZrrbkz", LIEF::assembly::x86::OPCODE::VMAXPDZrrbkz) + .value("VMAXPDZrrk", LIEF::assembly::x86::OPCODE::VMAXPDZrrk) + .value("VMAXPDZrrkz", LIEF::assembly::x86::OPCODE::VMAXPDZrrkz) + .value("VMAXPDrm", LIEF::assembly::x86::OPCODE::VMAXPDrm) + .value("VMAXPDrr", LIEF::assembly::x86::OPCODE::VMAXPDrr) + .value("VMAXPHZ128rm", LIEF::assembly::x86::OPCODE::VMAXPHZ128rm) + .value("VMAXPHZ128rmb", LIEF::assembly::x86::OPCODE::VMAXPHZ128rmb) + .value("VMAXPHZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXPHZ128rmbk) + .value("VMAXPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXPHZ128rmbkz) + .value("VMAXPHZ128rmk", LIEF::assembly::x86::OPCODE::VMAXPHZ128rmk) + .value("VMAXPHZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXPHZ128rmkz) + .value("VMAXPHZ128rr", LIEF::assembly::x86::OPCODE::VMAXPHZ128rr) + .value("VMAXPHZ128rrk", LIEF::assembly::x86::OPCODE::VMAXPHZ128rrk) + .value("VMAXPHZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXPHZ128rrkz) + .value("VMAXPHZ256rm", LIEF::assembly::x86::OPCODE::VMAXPHZ256rm) + .value("VMAXPHZ256rmb", LIEF::assembly::x86::OPCODE::VMAXPHZ256rmb) + .value("VMAXPHZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXPHZ256rmbk) + .value("VMAXPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXPHZ256rmbkz) + .value("VMAXPHZ256rmk", LIEF::assembly::x86::OPCODE::VMAXPHZ256rmk) + .value("VMAXPHZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXPHZ256rmkz) + .value("VMAXPHZ256rr", LIEF::assembly::x86::OPCODE::VMAXPHZ256rr) + .value("VMAXPHZ256rrk", LIEF::assembly::x86::OPCODE::VMAXPHZ256rrk) + .value("VMAXPHZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXPHZ256rrkz) + .value("VMAXPHZrm", LIEF::assembly::x86::OPCODE::VMAXPHZrm) + .value("VMAXPHZrmb", LIEF::assembly::x86::OPCODE::VMAXPHZrmb) + .value("VMAXPHZrmbk", LIEF::assembly::x86::OPCODE::VMAXPHZrmbk) + .value("VMAXPHZrmbkz", LIEF::assembly::x86::OPCODE::VMAXPHZrmbkz) + .value("VMAXPHZrmk", LIEF::assembly::x86::OPCODE::VMAXPHZrmk) + .value("VMAXPHZrmkz", LIEF::assembly::x86::OPCODE::VMAXPHZrmkz) + .value("VMAXPHZrr", LIEF::assembly::x86::OPCODE::VMAXPHZrr) + .value("VMAXPHZrrb", LIEF::assembly::x86::OPCODE::VMAXPHZrrb) + .value("VMAXPHZrrbk", LIEF::assembly::x86::OPCODE::VMAXPHZrrbk) + .value("VMAXPHZrrbkz", LIEF::assembly::x86::OPCODE::VMAXPHZrrbkz) + .value("VMAXPHZrrk", LIEF::assembly::x86::OPCODE::VMAXPHZrrk) + .value("VMAXPHZrrkz", LIEF::assembly::x86::OPCODE::VMAXPHZrrkz) + .value("VMAXPSYrm", LIEF::assembly::x86::OPCODE::VMAXPSYrm) + .value("VMAXPSYrr", LIEF::assembly::x86::OPCODE::VMAXPSYrr) + .value("VMAXPSZ128rm", LIEF::assembly::x86::OPCODE::VMAXPSZ128rm) + .value("VMAXPSZ128rmb", LIEF::assembly::x86::OPCODE::VMAXPSZ128rmb) + .value("VMAXPSZ128rmbk", LIEF::assembly::x86::OPCODE::VMAXPSZ128rmbk) + .value("VMAXPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VMAXPSZ128rmbkz) + .value("VMAXPSZ128rmk", LIEF::assembly::x86::OPCODE::VMAXPSZ128rmk) + .value("VMAXPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMAXPSZ128rmkz) + .value("VMAXPSZ128rr", LIEF::assembly::x86::OPCODE::VMAXPSZ128rr) + .value("VMAXPSZ128rrk", LIEF::assembly::x86::OPCODE::VMAXPSZ128rrk) + .value("VMAXPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMAXPSZ128rrkz) + .value("VMAXPSZ256rm", LIEF::assembly::x86::OPCODE::VMAXPSZ256rm) + .value("VMAXPSZ256rmb", LIEF::assembly::x86::OPCODE::VMAXPSZ256rmb) + .value("VMAXPSZ256rmbk", LIEF::assembly::x86::OPCODE::VMAXPSZ256rmbk) + .value("VMAXPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VMAXPSZ256rmbkz) + .value("VMAXPSZ256rmk", LIEF::assembly::x86::OPCODE::VMAXPSZ256rmk) + .value("VMAXPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMAXPSZ256rmkz) + .value("VMAXPSZ256rr", LIEF::assembly::x86::OPCODE::VMAXPSZ256rr) + .value("VMAXPSZ256rrk", LIEF::assembly::x86::OPCODE::VMAXPSZ256rrk) + .value("VMAXPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMAXPSZ256rrkz) + .value("VMAXPSZrm", LIEF::assembly::x86::OPCODE::VMAXPSZrm) + .value("VMAXPSZrmb", LIEF::assembly::x86::OPCODE::VMAXPSZrmb) + .value("VMAXPSZrmbk", LIEF::assembly::x86::OPCODE::VMAXPSZrmbk) + .value("VMAXPSZrmbkz", LIEF::assembly::x86::OPCODE::VMAXPSZrmbkz) + .value("VMAXPSZrmk", LIEF::assembly::x86::OPCODE::VMAXPSZrmk) + .value("VMAXPSZrmkz", LIEF::assembly::x86::OPCODE::VMAXPSZrmkz) + .value("VMAXPSZrr", LIEF::assembly::x86::OPCODE::VMAXPSZrr) + .value("VMAXPSZrrb", LIEF::assembly::x86::OPCODE::VMAXPSZrrb) + .value("VMAXPSZrrbk", LIEF::assembly::x86::OPCODE::VMAXPSZrrbk) + .value("VMAXPSZrrbkz", LIEF::assembly::x86::OPCODE::VMAXPSZrrbkz) + .value("VMAXPSZrrk", LIEF::assembly::x86::OPCODE::VMAXPSZrrk) + .value("VMAXPSZrrkz", LIEF::assembly::x86::OPCODE::VMAXPSZrrkz) + .value("VMAXPSrm", LIEF::assembly::x86::OPCODE::VMAXPSrm) + .value("VMAXPSrr", LIEF::assembly::x86::OPCODE::VMAXPSrr) + .value("VMAXSDZrm", LIEF::assembly::x86::OPCODE::VMAXSDZrm) + .value("VMAXSDZrm_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrm_Int) + .value("VMAXSDZrmk_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrmk_Int) + .value("VMAXSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrmkz_Int) + .value("VMAXSDZrr", LIEF::assembly::x86::OPCODE::VMAXSDZrr) + .value("VMAXSDZrr_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrr_Int) + .value("VMAXSDZrrb_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrrb_Int) + .value("VMAXSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrrbk_Int) + .value("VMAXSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrrbkz_Int) + .value("VMAXSDZrrk_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrrk_Int) + .value("VMAXSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VMAXSDZrrkz_Int) + .value("VMAXSDrm", LIEF::assembly::x86::OPCODE::VMAXSDrm) + .value("VMAXSDrm_Int", LIEF::assembly::x86::OPCODE::VMAXSDrm_Int) + .value("VMAXSDrr", LIEF::assembly::x86::OPCODE::VMAXSDrr) + .value("VMAXSDrr_Int", LIEF::assembly::x86::OPCODE::VMAXSDrr_Int) + .value("VMAXSHZrm", LIEF::assembly::x86::OPCODE::VMAXSHZrm) + .value("VMAXSHZrm_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrm_Int) + .value("VMAXSHZrmk_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrmk_Int) + .value("VMAXSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrmkz_Int) + .value("VMAXSHZrr", LIEF::assembly::x86::OPCODE::VMAXSHZrr) + .value("VMAXSHZrr_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrr_Int) + .value("VMAXSHZrrb_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrrb_Int) + .value("VMAXSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrrbk_Int) + .value("VMAXSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrrbkz_Int) + .value("VMAXSHZrrk_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrrk_Int) + .value("VMAXSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VMAXSHZrrkz_Int) + .value("VMAXSSZrm", LIEF::assembly::x86::OPCODE::VMAXSSZrm) + .value("VMAXSSZrm_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrm_Int) + .value("VMAXSSZrmk_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrmk_Int) + .value("VMAXSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrmkz_Int) + .value("VMAXSSZrr", LIEF::assembly::x86::OPCODE::VMAXSSZrr) + .value("VMAXSSZrr_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrr_Int) + .value("VMAXSSZrrb_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrrb_Int) + .value("VMAXSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrrbk_Int) + .value("VMAXSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrrbkz_Int) + .value("VMAXSSZrrk_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrrk_Int) + .value("VMAXSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VMAXSSZrrkz_Int) + .value("VMAXSSrm", LIEF::assembly::x86::OPCODE::VMAXSSrm) + .value("VMAXSSrm_Int", LIEF::assembly::x86::OPCODE::VMAXSSrm_Int) + .value("VMAXSSrr", LIEF::assembly::x86::OPCODE::VMAXSSrr) + .value("VMAXSSrr_Int", LIEF::assembly::x86::OPCODE::VMAXSSrr_Int) + .value("VMCALL", LIEF::assembly::x86::OPCODE::VMCALL) + .value("VMCLEARm", LIEF::assembly::x86::OPCODE::VMCLEARm) + .value("VMFUNC", LIEF::assembly::x86::OPCODE::VMFUNC) + .value("VMINBF16Z128rm", LIEF::assembly::x86::OPCODE::VMINBF16Z128rm) + .value("VMINBF16Z128rmb", LIEF::assembly::x86::OPCODE::VMINBF16Z128rmb) + .value("VMINBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VMINBF16Z128rmbk) + .value("VMINBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VMINBF16Z128rmbkz) + .value("VMINBF16Z128rmk", LIEF::assembly::x86::OPCODE::VMINBF16Z128rmk) + .value("VMINBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VMINBF16Z128rmkz) + .value("VMINBF16Z128rr", LIEF::assembly::x86::OPCODE::VMINBF16Z128rr) + .value("VMINBF16Z128rrk", LIEF::assembly::x86::OPCODE::VMINBF16Z128rrk) + .value("VMINBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VMINBF16Z128rrkz) + .value("VMINBF16Z256rm", LIEF::assembly::x86::OPCODE::VMINBF16Z256rm) + .value("VMINBF16Z256rmb", LIEF::assembly::x86::OPCODE::VMINBF16Z256rmb) + .value("VMINBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VMINBF16Z256rmbk) + .value("VMINBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VMINBF16Z256rmbkz) + .value("VMINBF16Z256rmk", LIEF::assembly::x86::OPCODE::VMINBF16Z256rmk) + .value("VMINBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VMINBF16Z256rmkz) + .value("VMINBF16Z256rr", LIEF::assembly::x86::OPCODE::VMINBF16Z256rr) + .value("VMINBF16Z256rrk", LIEF::assembly::x86::OPCODE::VMINBF16Z256rrk) + .value("VMINBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VMINBF16Z256rrkz) + .value("VMINBF16Zrm", LIEF::assembly::x86::OPCODE::VMINBF16Zrm) + .value("VMINBF16Zrmb", LIEF::assembly::x86::OPCODE::VMINBF16Zrmb) + .value("VMINBF16Zrmbk", LIEF::assembly::x86::OPCODE::VMINBF16Zrmbk) + .value("VMINBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VMINBF16Zrmbkz) + .value("VMINBF16Zrmk", LIEF::assembly::x86::OPCODE::VMINBF16Zrmk) + .value("VMINBF16Zrmkz", LIEF::assembly::x86::OPCODE::VMINBF16Zrmkz) + .value("VMINBF16Zrr", LIEF::assembly::x86::OPCODE::VMINBF16Zrr) + .value("VMINBF16Zrrk", LIEF::assembly::x86::OPCODE::VMINBF16Zrrk) + .value("VMINBF16Zrrkz", LIEF::assembly::x86::OPCODE::VMINBF16Zrrkz) + .value("VMINCPDYrm", LIEF::assembly::x86::OPCODE::VMINCPDYrm) + .value("VMINCPDYrr", LIEF::assembly::x86::OPCODE::VMINCPDYrr) + .value("VMINCPDZ128rm", LIEF::assembly::x86::OPCODE::VMINCPDZ128rm) + .value("VMINCPDZ128rmb", LIEF::assembly::x86::OPCODE::VMINCPDZ128rmb) + .value("VMINCPDZ128rmbk", LIEF::assembly::x86::OPCODE::VMINCPDZ128rmbk) + .value("VMINCPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINCPDZ128rmbkz) + .value("VMINCPDZ128rmk", LIEF::assembly::x86::OPCODE::VMINCPDZ128rmk) + .value("VMINCPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMINCPDZ128rmkz) + .value("VMINCPDZ128rr", LIEF::assembly::x86::OPCODE::VMINCPDZ128rr) + .value("VMINCPDZ128rrk", LIEF::assembly::x86::OPCODE::VMINCPDZ128rrk) + .value("VMINCPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMINCPDZ128rrkz) + .value("VMINCPDZ256rm", LIEF::assembly::x86::OPCODE::VMINCPDZ256rm) + .value("VMINCPDZ256rmb", LIEF::assembly::x86::OPCODE::VMINCPDZ256rmb) + .value("VMINCPDZ256rmbk", LIEF::assembly::x86::OPCODE::VMINCPDZ256rmbk) + .value("VMINCPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINCPDZ256rmbkz) + .value("VMINCPDZ256rmk", LIEF::assembly::x86::OPCODE::VMINCPDZ256rmk) + .value("VMINCPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMINCPDZ256rmkz) + .value("VMINCPDZ256rr", LIEF::assembly::x86::OPCODE::VMINCPDZ256rr) + .value("VMINCPDZ256rrk", LIEF::assembly::x86::OPCODE::VMINCPDZ256rrk) + .value("VMINCPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMINCPDZ256rrkz) + .value("VMINCPDZrm", LIEF::assembly::x86::OPCODE::VMINCPDZrm) + .value("VMINCPDZrmb", LIEF::assembly::x86::OPCODE::VMINCPDZrmb) + .value("VMINCPDZrmbk", LIEF::assembly::x86::OPCODE::VMINCPDZrmbk) + .value("VMINCPDZrmbkz", LIEF::assembly::x86::OPCODE::VMINCPDZrmbkz) + .value("VMINCPDZrmk", LIEF::assembly::x86::OPCODE::VMINCPDZrmk) + .value("VMINCPDZrmkz", LIEF::assembly::x86::OPCODE::VMINCPDZrmkz) + .value("VMINCPDZrr", LIEF::assembly::x86::OPCODE::VMINCPDZrr) + .value("VMINCPDZrrk", LIEF::assembly::x86::OPCODE::VMINCPDZrrk) + .value("VMINCPDZrrkz", LIEF::assembly::x86::OPCODE::VMINCPDZrrkz) + .value("VMINCPDrm", LIEF::assembly::x86::OPCODE::VMINCPDrm) + .value("VMINCPDrr", LIEF::assembly::x86::OPCODE::VMINCPDrr) + .value("VMINCPHZ128rm", LIEF::assembly::x86::OPCODE::VMINCPHZ128rm) + .value("VMINCPHZ128rmb", LIEF::assembly::x86::OPCODE::VMINCPHZ128rmb) + .value("VMINCPHZ128rmbk", LIEF::assembly::x86::OPCODE::VMINCPHZ128rmbk) + .value("VMINCPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINCPHZ128rmbkz) + .value("VMINCPHZ128rmk", LIEF::assembly::x86::OPCODE::VMINCPHZ128rmk) + .value("VMINCPHZ128rmkz", LIEF::assembly::x86::OPCODE::VMINCPHZ128rmkz) + .value("VMINCPHZ128rr", LIEF::assembly::x86::OPCODE::VMINCPHZ128rr) + .value("VMINCPHZ128rrk", LIEF::assembly::x86::OPCODE::VMINCPHZ128rrk) + .value("VMINCPHZ128rrkz", LIEF::assembly::x86::OPCODE::VMINCPHZ128rrkz) + .value("VMINCPHZ256rm", LIEF::assembly::x86::OPCODE::VMINCPHZ256rm) + .value("VMINCPHZ256rmb", LIEF::assembly::x86::OPCODE::VMINCPHZ256rmb) + .value("VMINCPHZ256rmbk", LIEF::assembly::x86::OPCODE::VMINCPHZ256rmbk) + .value("VMINCPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINCPHZ256rmbkz) + .value("VMINCPHZ256rmk", LIEF::assembly::x86::OPCODE::VMINCPHZ256rmk) + .value("VMINCPHZ256rmkz", LIEF::assembly::x86::OPCODE::VMINCPHZ256rmkz) + .value("VMINCPHZ256rr", LIEF::assembly::x86::OPCODE::VMINCPHZ256rr) + .value("VMINCPHZ256rrk", LIEF::assembly::x86::OPCODE::VMINCPHZ256rrk) + .value("VMINCPHZ256rrkz", LIEF::assembly::x86::OPCODE::VMINCPHZ256rrkz) + .value("VMINCPHZrm", LIEF::assembly::x86::OPCODE::VMINCPHZrm) + .value("VMINCPHZrmb", LIEF::assembly::x86::OPCODE::VMINCPHZrmb) + .value("VMINCPHZrmbk", LIEF::assembly::x86::OPCODE::VMINCPHZrmbk) + .value("VMINCPHZrmbkz", LIEF::assembly::x86::OPCODE::VMINCPHZrmbkz) + .value("VMINCPHZrmk", LIEF::assembly::x86::OPCODE::VMINCPHZrmk) + .value("VMINCPHZrmkz", LIEF::assembly::x86::OPCODE::VMINCPHZrmkz) + .value("VMINCPHZrr", LIEF::assembly::x86::OPCODE::VMINCPHZrr) + .value("VMINCPHZrrk", LIEF::assembly::x86::OPCODE::VMINCPHZrrk) + .value("VMINCPHZrrkz", LIEF::assembly::x86::OPCODE::VMINCPHZrrkz) + .value("VMINCPSYrm", LIEF::assembly::x86::OPCODE::VMINCPSYrm) + .value("VMINCPSYrr", LIEF::assembly::x86::OPCODE::VMINCPSYrr) + .value("VMINCPSZ128rm", LIEF::assembly::x86::OPCODE::VMINCPSZ128rm) + .value("VMINCPSZ128rmb", LIEF::assembly::x86::OPCODE::VMINCPSZ128rmb) + .value("VMINCPSZ128rmbk", LIEF::assembly::x86::OPCODE::VMINCPSZ128rmbk) + .value("VMINCPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINCPSZ128rmbkz) + .value("VMINCPSZ128rmk", LIEF::assembly::x86::OPCODE::VMINCPSZ128rmk) + .value("VMINCPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMINCPSZ128rmkz) + .value("VMINCPSZ128rr", LIEF::assembly::x86::OPCODE::VMINCPSZ128rr) + .value("VMINCPSZ128rrk", LIEF::assembly::x86::OPCODE::VMINCPSZ128rrk) + .value("VMINCPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMINCPSZ128rrkz) + .value("VMINCPSZ256rm", LIEF::assembly::x86::OPCODE::VMINCPSZ256rm) + .value("VMINCPSZ256rmb", LIEF::assembly::x86::OPCODE::VMINCPSZ256rmb) + .value("VMINCPSZ256rmbk", LIEF::assembly::x86::OPCODE::VMINCPSZ256rmbk) + .value("VMINCPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINCPSZ256rmbkz) + .value("VMINCPSZ256rmk", LIEF::assembly::x86::OPCODE::VMINCPSZ256rmk) + .value("VMINCPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMINCPSZ256rmkz) + .value("VMINCPSZ256rr", LIEF::assembly::x86::OPCODE::VMINCPSZ256rr) + .value("VMINCPSZ256rrk", LIEF::assembly::x86::OPCODE::VMINCPSZ256rrk) + .value("VMINCPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMINCPSZ256rrkz) + .value("VMINCPSZrm", LIEF::assembly::x86::OPCODE::VMINCPSZrm) + .value("VMINCPSZrmb", LIEF::assembly::x86::OPCODE::VMINCPSZrmb) + .value("VMINCPSZrmbk", LIEF::assembly::x86::OPCODE::VMINCPSZrmbk) + .value("VMINCPSZrmbkz", LIEF::assembly::x86::OPCODE::VMINCPSZrmbkz) + .value("VMINCPSZrmk", LIEF::assembly::x86::OPCODE::VMINCPSZrmk) + .value("VMINCPSZrmkz", LIEF::assembly::x86::OPCODE::VMINCPSZrmkz) + .value("VMINCPSZrr", LIEF::assembly::x86::OPCODE::VMINCPSZrr) + .value("VMINCPSZrrk", LIEF::assembly::x86::OPCODE::VMINCPSZrrk) + .value("VMINCPSZrrkz", LIEF::assembly::x86::OPCODE::VMINCPSZrrkz) + .value("VMINCPSrm", LIEF::assembly::x86::OPCODE::VMINCPSrm) + .value("VMINCPSrr", LIEF::assembly::x86::OPCODE::VMINCPSrr) + .value("VMINCSDZrm", LIEF::assembly::x86::OPCODE::VMINCSDZrm) + .value("VMINCSDZrr", LIEF::assembly::x86::OPCODE::VMINCSDZrr) + .value("VMINCSDrm", LIEF::assembly::x86::OPCODE::VMINCSDrm) + .value("VMINCSDrr", LIEF::assembly::x86::OPCODE::VMINCSDrr) + .value("VMINCSHZrm", LIEF::assembly::x86::OPCODE::VMINCSHZrm) + .value("VMINCSHZrr", LIEF::assembly::x86::OPCODE::VMINCSHZrr) + .value("VMINCSSZrm", LIEF::assembly::x86::OPCODE::VMINCSSZrm) + .value("VMINCSSZrr", LIEF::assembly::x86::OPCODE::VMINCSSZrr) + .value("VMINCSSrm", LIEF::assembly::x86::OPCODE::VMINCSSrm) + .value("VMINCSSrr", LIEF::assembly::x86::OPCODE::VMINCSSrr) + .value("VMINMAXBF16Z128rmbi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmbi) + .value("VMINMAXBF16Z128rmbik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmbik) + .value("VMINMAXBF16Z128rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmbikz) + .value("VMINMAXBF16Z128rmi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmi) + .value("VMINMAXBF16Z128rmik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmik) + .value("VMINMAXBF16Z128rmikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rmikz) + .value("VMINMAXBF16Z128rri", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rri) + .value("VMINMAXBF16Z128rrik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rrik) + .value("VMINMAXBF16Z128rrikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z128rrikz) + .value("VMINMAXBF16Z256rmbi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmbi) + .value("VMINMAXBF16Z256rmbik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmbik) + .value("VMINMAXBF16Z256rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmbikz) + .value("VMINMAXBF16Z256rmi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmi) + .value("VMINMAXBF16Z256rmik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmik) + .value("VMINMAXBF16Z256rmikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rmikz) + .value("VMINMAXBF16Z256rri", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rri) + .value("VMINMAXBF16Z256rrik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rrik) + .value("VMINMAXBF16Z256rrikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Z256rrikz) + .value("VMINMAXBF16Zrmbi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmbi) + .value("VMINMAXBF16Zrmbik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmbik) + .value("VMINMAXBF16Zrmbikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmbikz) + .value("VMINMAXBF16Zrmi", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmi) + .value("VMINMAXBF16Zrmik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmik) + .value("VMINMAXBF16Zrmikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrmikz) + .value("VMINMAXBF16Zrri", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrri) + .value("VMINMAXBF16Zrrik", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrrik) + .value("VMINMAXBF16Zrrikz", LIEF::assembly::x86::OPCODE::VMINMAXBF16Zrrikz) + .value("VMINMAXPDZ128rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmbi) + .value("VMINMAXPDZ128rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmbik) + .value("VMINMAXPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmbikz) + .value("VMINMAXPDZ128rmi", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmi) + .value("VMINMAXPDZ128rmik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmik) + .value("VMINMAXPDZ128rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rmikz) + .value("VMINMAXPDZ128rri", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rri) + .value("VMINMAXPDZ128rrik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rrik) + .value("VMINMAXPDZ128rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ128rrikz) + .value("VMINMAXPDZ256rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmbi) + .value("VMINMAXPDZ256rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmbik) + .value("VMINMAXPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmbikz) + .value("VMINMAXPDZ256rmi", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmi) + .value("VMINMAXPDZ256rmik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmik) + .value("VMINMAXPDZ256rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rmikz) + .value("VMINMAXPDZ256rri", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rri) + .value("VMINMAXPDZ256rrik", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rrik) + .value("VMINMAXPDZ256rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZ256rrikz) + .value("VMINMAXPDZrmbi", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmbi) + .value("VMINMAXPDZrmbik", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmbik) + .value("VMINMAXPDZrmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmbikz) + .value("VMINMAXPDZrmi", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmi) + .value("VMINMAXPDZrmik", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmik) + .value("VMINMAXPDZrmikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZrmikz) + .value("VMINMAXPDZrri", LIEF::assembly::x86::OPCODE::VMINMAXPDZrri) + .value("VMINMAXPDZrrib", LIEF::assembly::x86::OPCODE::VMINMAXPDZrrib) + .value("VMINMAXPDZrribk", LIEF::assembly::x86::OPCODE::VMINMAXPDZrribk); + opcodes.value("VMINMAXPDZrribkz", LIEF::assembly::x86::OPCODE::VMINMAXPDZrribkz) + .value("VMINMAXPDZrrik", LIEF::assembly::x86::OPCODE::VMINMAXPDZrrik) + .value("VMINMAXPDZrrikz", LIEF::assembly::x86::OPCODE::VMINMAXPDZrrikz) + .value("VMINMAXPHZ128rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmbi) + .value("VMINMAXPHZ128rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmbik) + .value("VMINMAXPHZ128rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmbikz) + .value("VMINMAXPHZ128rmi", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmi) + .value("VMINMAXPHZ128rmik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmik) + .value("VMINMAXPHZ128rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rmikz) + .value("VMINMAXPHZ128rri", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rri) + .value("VMINMAXPHZ128rrik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rrik) + .value("VMINMAXPHZ128rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ128rrikz) + .value("VMINMAXPHZ256rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmbi) + .value("VMINMAXPHZ256rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmbik) + .value("VMINMAXPHZ256rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmbikz) + .value("VMINMAXPHZ256rmi", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmi) + .value("VMINMAXPHZ256rmik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmik) + .value("VMINMAXPHZ256rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rmikz) + .value("VMINMAXPHZ256rri", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rri) + .value("VMINMAXPHZ256rrik", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rrik) + .value("VMINMAXPHZ256rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZ256rrikz) + .value("VMINMAXPHZrmbi", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmbi) + .value("VMINMAXPHZrmbik", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmbik) + .value("VMINMAXPHZrmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmbikz) + .value("VMINMAXPHZrmi", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmi) + .value("VMINMAXPHZrmik", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmik) + .value("VMINMAXPHZrmikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZrmikz) + .value("VMINMAXPHZrri", LIEF::assembly::x86::OPCODE::VMINMAXPHZrri) + .value("VMINMAXPHZrrib", LIEF::assembly::x86::OPCODE::VMINMAXPHZrrib) + .value("VMINMAXPHZrribk", LIEF::assembly::x86::OPCODE::VMINMAXPHZrribk) + .value("VMINMAXPHZrribkz", LIEF::assembly::x86::OPCODE::VMINMAXPHZrribkz) + .value("VMINMAXPHZrrik", LIEF::assembly::x86::OPCODE::VMINMAXPHZrrik) + .value("VMINMAXPHZrrikz", LIEF::assembly::x86::OPCODE::VMINMAXPHZrrikz) + .value("VMINMAXPSZ128rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmbi) + .value("VMINMAXPSZ128rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmbik) + .value("VMINMAXPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmbikz) + .value("VMINMAXPSZ128rmi", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmi) + .value("VMINMAXPSZ128rmik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmik) + .value("VMINMAXPSZ128rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rmikz) + .value("VMINMAXPSZ128rri", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rri) + .value("VMINMAXPSZ128rrik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rrik) + .value("VMINMAXPSZ128rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ128rrikz) + .value("VMINMAXPSZ256rmbi", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmbi) + .value("VMINMAXPSZ256rmbik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmbik) + .value("VMINMAXPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmbikz) + .value("VMINMAXPSZ256rmi", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmi) + .value("VMINMAXPSZ256rmik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmik) + .value("VMINMAXPSZ256rmikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rmikz) + .value("VMINMAXPSZ256rri", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rri) + .value("VMINMAXPSZ256rrik", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rrik) + .value("VMINMAXPSZ256rrikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZ256rrikz) + .value("VMINMAXPSZrmbi", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmbi) + .value("VMINMAXPSZrmbik", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmbik) + .value("VMINMAXPSZrmbikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmbikz) + .value("VMINMAXPSZrmi", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmi) + .value("VMINMAXPSZrmik", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmik) + .value("VMINMAXPSZrmikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZrmikz) + .value("VMINMAXPSZrri", LIEF::assembly::x86::OPCODE::VMINMAXPSZrri) + .value("VMINMAXPSZrrib", LIEF::assembly::x86::OPCODE::VMINMAXPSZrrib) + .value("VMINMAXPSZrribk", LIEF::assembly::x86::OPCODE::VMINMAXPSZrribk) + .value("VMINMAXPSZrribkz", LIEF::assembly::x86::OPCODE::VMINMAXPSZrribkz) + .value("VMINMAXPSZrrik", LIEF::assembly::x86::OPCODE::VMINMAXPSZrrik) + .value("VMINMAXPSZrrikz", LIEF::assembly::x86::OPCODE::VMINMAXPSZrrikz) + .value("VMINMAXSDrmi", LIEF::assembly::x86::OPCODE::VMINMAXSDrmi) + .value("VMINMAXSDrmi_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrmi_Int) + .value("VMINMAXSDrmik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrmik_Int) + .value("VMINMAXSDrmikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrmikz_Int) + .value("VMINMAXSDrri", LIEF::assembly::x86::OPCODE::VMINMAXSDrri) + .value("VMINMAXSDrri_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrri_Int) + .value("VMINMAXSDrrib_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrrib_Int) + .value("VMINMAXSDrribk_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrribk_Int) + .value("VMINMAXSDrribkz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrribkz_Int) + .value("VMINMAXSDrrik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrrik_Int) + .value("VMINMAXSDrrikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSDrrikz_Int) + .value("VMINMAXSHrmi", LIEF::assembly::x86::OPCODE::VMINMAXSHrmi) + .value("VMINMAXSHrmi_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrmi_Int) + .value("VMINMAXSHrmik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrmik_Int) + .value("VMINMAXSHrmikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrmikz_Int) + .value("VMINMAXSHrri", LIEF::assembly::x86::OPCODE::VMINMAXSHrri) + .value("VMINMAXSHrri_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrri_Int) + .value("VMINMAXSHrrib_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrrib_Int) + .value("VMINMAXSHrribk_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrribk_Int) + .value("VMINMAXSHrribkz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrribkz_Int) + .value("VMINMAXSHrrik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrrik_Int) + .value("VMINMAXSHrrikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSHrrikz_Int) + .value("VMINMAXSSrmi", LIEF::assembly::x86::OPCODE::VMINMAXSSrmi) + .value("VMINMAXSSrmi_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrmi_Int) + .value("VMINMAXSSrmik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrmik_Int) + .value("VMINMAXSSrmikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrmikz_Int) + .value("VMINMAXSSrri", LIEF::assembly::x86::OPCODE::VMINMAXSSrri) + .value("VMINMAXSSrri_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrri_Int) + .value("VMINMAXSSrrib_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrrib_Int) + .value("VMINMAXSSrribk_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrribk_Int) + .value("VMINMAXSSrribkz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrribkz_Int) + .value("VMINMAXSSrrik_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrrik_Int) + .value("VMINMAXSSrrikz_Int", LIEF::assembly::x86::OPCODE::VMINMAXSSrrikz_Int) + .value("VMINPDYrm", LIEF::assembly::x86::OPCODE::VMINPDYrm) + .value("VMINPDYrr", LIEF::assembly::x86::OPCODE::VMINPDYrr) + .value("VMINPDZ128rm", LIEF::assembly::x86::OPCODE::VMINPDZ128rm) + .value("VMINPDZ128rmb", LIEF::assembly::x86::OPCODE::VMINPDZ128rmb) + .value("VMINPDZ128rmbk", LIEF::assembly::x86::OPCODE::VMINPDZ128rmbk) + .value("VMINPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINPDZ128rmbkz) + .value("VMINPDZ128rmk", LIEF::assembly::x86::OPCODE::VMINPDZ128rmk) + .value("VMINPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMINPDZ128rmkz) + .value("VMINPDZ128rr", LIEF::assembly::x86::OPCODE::VMINPDZ128rr) + .value("VMINPDZ128rrk", LIEF::assembly::x86::OPCODE::VMINPDZ128rrk) + .value("VMINPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMINPDZ128rrkz) + .value("VMINPDZ256rm", LIEF::assembly::x86::OPCODE::VMINPDZ256rm) + .value("VMINPDZ256rmb", LIEF::assembly::x86::OPCODE::VMINPDZ256rmb) + .value("VMINPDZ256rmbk", LIEF::assembly::x86::OPCODE::VMINPDZ256rmbk) + .value("VMINPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINPDZ256rmbkz) + .value("VMINPDZ256rmk", LIEF::assembly::x86::OPCODE::VMINPDZ256rmk) + .value("VMINPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMINPDZ256rmkz) + .value("VMINPDZ256rr", LIEF::assembly::x86::OPCODE::VMINPDZ256rr) + .value("VMINPDZ256rrk", LIEF::assembly::x86::OPCODE::VMINPDZ256rrk) + .value("VMINPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMINPDZ256rrkz) + .value("VMINPDZrm", LIEF::assembly::x86::OPCODE::VMINPDZrm) + .value("VMINPDZrmb", LIEF::assembly::x86::OPCODE::VMINPDZrmb) + .value("VMINPDZrmbk", LIEF::assembly::x86::OPCODE::VMINPDZrmbk) + .value("VMINPDZrmbkz", LIEF::assembly::x86::OPCODE::VMINPDZrmbkz) + .value("VMINPDZrmk", LIEF::assembly::x86::OPCODE::VMINPDZrmk) + .value("VMINPDZrmkz", LIEF::assembly::x86::OPCODE::VMINPDZrmkz) + .value("VMINPDZrr", LIEF::assembly::x86::OPCODE::VMINPDZrr) + .value("VMINPDZrrb", LIEF::assembly::x86::OPCODE::VMINPDZrrb) + .value("VMINPDZrrbk", LIEF::assembly::x86::OPCODE::VMINPDZrrbk) + .value("VMINPDZrrbkz", LIEF::assembly::x86::OPCODE::VMINPDZrrbkz) + .value("VMINPDZrrk", LIEF::assembly::x86::OPCODE::VMINPDZrrk) + .value("VMINPDZrrkz", LIEF::assembly::x86::OPCODE::VMINPDZrrkz) + .value("VMINPDrm", LIEF::assembly::x86::OPCODE::VMINPDrm) + .value("VMINPDrr", LIEF::assembly::x86::OPCODE::VMINPDrr) + .value("VMINPHZ128rm", LIEF::assembly::x86::OPCODE::VMINPHZ128rm) + .value("VMINPHZ128rmb", LIEF::assembly::x86::OPCODE::VMINPHZ128rmb) + .value("VMINPHZ128rmbk", LIEF::assembly::x86::OPCODE::VMINPHZ128rmbk) + .value("VMINPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINPHZ128rmbkz) + .value("VMINPHZ128rmk", LIEF::assembly::x86::OPCODE::VMINPHZ128rmk) + .value("VMINPHZ128rmkz", LIEF::assembly::x86::OPCODE::VMINPHZ128rmkz) + .value("VMINPHZ128rr", LIEF::assembly::x86::OPCODE::VMINPHZ128rr) + .value("VMINPHZ128rrk", LIEF::assembly::x86::OPCODE::VMINPHZ128rrk) + .value("VMINPHZ128rrkz", LIEF::assembly::x86::OPCODE::VMINPHZ128rrkz) + .value("VMINPHZ256rm", LIEF::assembly::x86::OPCODE::VMINPHZ256rm) + .value("VMINPHZ256rmb", LIEF::assembly::x86::OPCODE::VMINPHZ256rmb) + .value("VMINPHZ256rmbk", LIEF::assembly::x86::OPCODE::VMINPHZ256rmbk) + .value("VMINPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINPHZ256rmbkz) + .value("VMINPHZ256rmk", LIEF::assembly::x86::OPCODE::VMINPHZ256rmk) + .value("VMINPHZ256rmkz", LIEF::assembly::x86::OPCODE::VMINPHZ256rmkz) + .value("VMINPHZ256rr", LIEF::assembly::x86::OPCODE::VMINPHZ256rr) + .value("VMINPHZ256rrk", LIEF::assembly::x86::OPCODE::VMINPHZ256rrk) + .value("VMINPHZ256rrkz", LIEF::assembly::x86::OPCODE::VMINPHZ256rrkz) + .value("VMINPHZrm", LIEF::assembly::x86::OPCODE::VMINPHZrm) + .value("VMINPHZrmb", LIEF::assembly::x86::OPCODE::VMINPHZrmb) + .value("VMINPHZrmbk", LIEF::assembly::x86::OPCODE::VMINPHZrmbk) + .value("VMINPHZrmbkz", LIEF::assembly::x86::OPCODE::VMINPHZrmbkz) + .value("VMINPHZrmk", LIEF::assembly::x86::OPCODE::VMINPHZrmk) + .value("VMINPHZrmkz", LIEF::assembly::x86::OPCODE::VMINPHZrmkz) + .value("VMINPHZrr", LIEF::assembly::x86::OPCODE::VMINPHZrr) + .value("VMINPHZrrb", LIEF::assembly::x86::OPCODE::VMINPHZrrb) + .value("VMINPHZrrbk", LIEF::assembly::x86::OPCODE::VMINPHZrrbk) + .value("VMINPHZrrbkz", LIEF::assembly::x86::OPCODE::VMINPHZrrbkz) + .value("VMINPHZrrk", LIEF::assembly::x86::OPCODE::VMINPHZrrk) + .value("VMINPHZrrkz", LIEF::assembly::x86::OPCODE::VMINPHZrrkz) + .value("VMINPSYrm", LIEF::assembly::x86::OPCODE::VMINPSYrm) + .value("VMINPSYrr", LIEF::assembly::x86::OPCODE::VMINPSYrr) + .value("VMINPSZ128rm", LIEF::assembly::x86::OPCODE::VMINPSZ128rm) + .value("VMINPSZ128rmb", LIEF::assembly::x86::OPCODE::VMINPSZ128rmb) + .value("VMINPSZ128rmbk", LIEF::assembly::x86::OPCODE::VMINPSZ128rmbk) + .value("VMINPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VMINPSZ128rmbkz) + .value("VMINPSZ128rmk", LIEF::assembly::x86::OPCODE::VMINPSZ128rmk) + .value("VMINPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMINPSZ128rmkz) + .value("VMINPSZ128rr", LIEF::assembly::x86::OPCODE::VMINPSZ128rr) + .value("VMINPSZ128rrk", LIEF::assembly::x86::OPCODE::VMINPSZ128rrk) + .value("VMINPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMINPSZ128rrkz) + .value("VMINPSZ256rm", LIEF::assembly::x86::OPCODE::VMINPSZ256rm) + .value("VMINPSZ256rmb", LIEF::assembly::x86::OPCODE::VMINPSZ256rmb) + .value("VMINPSZ256rmbk", LIEF::assembly::x86::OPCODE::VMINPSZ256rmbk) + .value("VMINPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VMINPSZ256rmbkz) + .value("VMINPSZ256rmk", LIEF::assembly::x86::OPCODE::VMINPSZ256rmk) + .value("VMINPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMINPSZ256rmkz) + .value("VMINPSZ256rr", LIEF::assembly::x86::OPCODE::VMINPSZ256rr) + .value("VMINPSZ256rrk", LIEF::assembly::x86::OPCODE::VMINPSZ256rrk) + .value("VMINPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMINPSZ256rrkz) + .value("VMINPSZrm", LIEF::assembly::x86::OPCODE::VMINPSZrm) + .value("VMINPSZrmb", LIEF::assembly::x86::OPCODE::VMINPSZrmb) + .value("VMINPSZrmbk", LIEF::assembly::x86::OPCODE::VMINPSZrmbk) + .value("VMINPSZrmbkz", LIEF::assembly::x86::OPCODE::VMINPSZrmbkz) + .value("VMINPSZrmk", LIEF::assembly::x86::OPCODE::VMINPSZrmk) + .value("VMINPSZrmkz", LIEF::assembly::x86::OPCODE::VMINPSZrmkz) + .value("VMINPSZrr", LIEF::assembly::x86::OPCODE::VMINPSZrr) + .value("VMINPSZrrb", LIEF::assembly::x86::OPCODE::VMINPSZrrb) + .value("VMINPSZrrbk", LIEF::assembly::x86::OPCODE::VMINPSZrrbk) + .value("VMINPSZrrbkz", LIEF::assembly::x86::OPCODE::VMINPSZrrbkz) + .value("VMINPSZrrk", LIEF::assembly::x86::OPCODE::VMINPSZrrk) + .value("VMINPSZrrkz", LIEF::assembly::x86::OPCODE::VMINPSZrrkz) + .value("VMINPSrm", LIEF::assembly::x86::OPCODE::VMINPSrm) + .value("VMINPSrr", LIEF::assembly::x86::OPCODE::VMINPSrr) + .value("VMINSDZrm", LIEF::assembly::x86::OPCODE::VMINSDZrm) + .value("VMINSDZrm_Int", LIEF::assembly::x86::OPCODE::VMINSDZrm_Int) + .value("VMINSDZrmk_Int", LIEF::assembly::x86::OPCODE::VMINSDZrmk_Int) + .value("VMINSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VMINSDZrmkz_Int) + .value("VMINSDZrr", LIEF::assembly::x86::OPCODE::VMINSDZrr) + .value("VMINSDZrr_Int", LIEF::assembly::x86::OPCODE::VMINSDZrr_Int) + .value("VMINSDZrrb_Int", LIEF::assembly::x86::OPCODE::VMINSDZrrb_Int) + .value("VMINSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VMINSDZrrbk_Int) + .value("VMINSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMINSDZrrbkz_Int) + .value("VMINSDZrrk_Int", LIEF::assembly::x86::OPCODE::VMINSDZrrk_Int) + .value("VMINSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VMINSDZrrkz_Int) + .value("VMINSDrm", LIEF::assembly::x86::OPCODE::VMINSDrm) + .value("VMINSDrm_Int", LIEF::assembly::x86::OPCODE::VMINSDrm_Int) + .value("VMINSDrr", LIEF::assembly::x86::OPCODE::VMINSDrr) + .value("VMINSDrr_Int", LIEF::assembly::x86::OPCODE::VMINSDrr_Int) + .value("VMINSHZrm", LIEF::assembly::x86::OPCODE::VMINSHZrm) + .value("VMINSHZrm_Int", LIEF::assembly::x86::OPCODE::VMINSHZrm_Int) + .value("VMINSHZrmk_Int", LIEF::assembly::x86::OPCODE::VMINSHZrmk_Int) + .value("VMINSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VMINSHZrmkz_Int) + .value("VMINSHZrr", LIEF::assembly::x86::OPCODE::VMINSHZrr) + .value("VMINSHZrr_Int", LIEF::assembly::x86::OPCODE::VMINSHZrr_Int) + .value("VMINSHZrrb_Int", LIEF::assembly::x86::OPCODE::VMINSHZrrb_Int) + .value("VMINSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VMINSHZrrbk_Int) + .value("VMINSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMINSHZrrbkz_Int) + .value("VMINSHZrrk_Int", LIEF::assembly::x86::OPCODE::VMINSHZrrk_Int) + .value("VMINSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VMINSHZrrkz_Int) + .value("VMINSSZrm", LIEF::assembly::x86::OPCODE::VMINSSZrm) + .value("VMINSSZrm_Int", LIEF::assembly::x86::OPCODE::VMINSSZrm_Int) + .value("VMINSSZrmk_Int", LIEF::assembly::x86::OPCODE::VMINSSZrmk_Int) + .value("VMINSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VMINSSZrmkz_Int) + .value("VMINSSZrr", LIEF::assembly::x86::OPCODE::VMINSSZrr) + .value("VMINSSZrr_Int", LIEF::assembly::x86::OPCODE::VMINSSZrr_Int) + .value("VMINSSZrrb_Int", LIEF::assembly::x86::OPCODE::VMINSSZrrb_Int) + .value("VMINSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VMINSSZrrbk_Int) + .value("VMINSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMINSSZrrbkz_Int) + .value("VMINSSZrrk_Int", LIEF::assembly::x86::OPCODE::VMINSSZrrk_Int) + .value("VMINSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VMINSSZrrkz_Int) + .value("VMINSSrm", LIEF::assembly::x86::OPCODE::VMINSSrm) + .value("VMINSSrm_Int", LIEF::assembly::x86::OPCODE::VMINSSrm_Int) + .value("VMINSSrr", LIEF::assembly::x86::OPCODE::VMINSSrr) + .value("VMINSSrr_Int", LIEF::assembly::x86::OPCODE::VMINSSrr_Int) + .value("VMLAUNCH", LIEF::assembly::x86::OPCODE::VMLAUNCH) + .value("VMLOAD32", LIEF::assembly::x86::OPCODE::VMLOAD32) + .value("VMLOAD64", LIEF::assembly::x86::OPCODE::VMLOAD64) + .value("VMMCALL", LIEF::assembly::x86::OPCODE::VMMCALL) + .value("VMOV64toPQIZrm", LIEF::assembly::x86::OPCODE::VMOV64toPQIZrm) + .value("VMOV64toPQIZrr", LIEF::assembly::x86::OPCODE::VMOV64toPQIZrr) + .value("VMOV64toPQIrm", LIEF::assembly::x86::OPCODE::VMOV64toPQIrm) + .value("VMOV64toPQIrr", LIEF::assembly::x86::OPCODE::VMOV64toPQIrr) + .value("VMOV64toSDZrr", LIEF::assembly::x86::OPCODE::VMOV64toSDZrr) + .value("VMOV64toSDrr", LIEF::assembly::x86::OPCODE::VMOV64toSDrr) + .value("VMOVAPDYmr", LIEF::assembly::x86::OPCODE::VMOVAPDYmr) + .value("VMOVAPDYrm", LIEF::assembly::x86::OPCODE::VMOVAPDYrm) + .value("VMOVAPDYrr", LIEF::assembly::x86::OPCODE::VMOVAPDYrr) + .value("VMOVAPDYrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPDYrr_REV) + .value("VMOVAPDZ128mr", LIEF::assembly::x86::OPCODE::VMOVAPDZ128mr) + .value("VMOVAPDZ128mrk", LIEF::assembly::x86::OPCODE::VMOVAPDZ128mrk) + .value("VMOVAPDZ128rm", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rm) + .value("VMOVAPDZ128rmk", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rmk) + .value("VMOVAPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rmkz) + .value("VMOVAPDZ128rr", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rr) + .value("VMOVAPDZ128rr_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rr_REV) + .value("VMOVAPDZ128rrk", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rrk) + .value("VMOVAPDZ128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rrk_REV) + .value("VMOVAPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rrkz) + .value("VMOVAPDZ128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ128rrkz_REV) + .value("VMOVAPDZ256mr", LIEF::assembly::x86::OPCODE::VMOVAPDZ256mr) + .value("VMOVAPDZ256mrk", LIEF::assembly::x86::OPCODE::VMOVAPDZ256mrk) + .value("VMOVAPDZ256rm", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rm) + .value("VMOVAPDZ256rmk", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rmk) + .value("VMOVAPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rmkz) + .value("VMOVAPDZ256rr", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rr) + .value("VMOVAPDZ256rr_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rr_REV) + .value("VMOVAPDZ256rrk", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rrk) + .value("VMOVAPDZ256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rrk_REV) + .value("VMOVAPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rrkz) + .value("VMOVAPDZ256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZ256rrkz_REV) + .value("VMOVAPDZmr", LIEF::assembly::x86::OPCODE::VMOVAPDZmr) + .value("VMOVAPDZmrk", LIEF::assembly::x86::OPCODE::VMOVAPDZmrk) + .value("VMOVAPDZrm", LIEF::assembly::x86::OPCODE::VMOVAPDZrm) + .value("VMOVAPDZrmk", LIEF::assembly::x86::OPCODE::VMOVAPDZrmk) + .value("VMOVAPDZrmkz", LIEF::assembly::x86::OPCODE::VMOVAPDZrmkz) + .value("VMOVAPDZrr", LIEF::assembly::x86::OPCODE::VMOVAPDZrr) + .value("VMOVAPDZrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZrr_REV) + .value("VMOVAPDZrrk", LIEF::assembly::x86::OPCODE::VMOVAPDZrrk) + .value("VMOVAPDZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZrrk_REV) + .value("VMOVAPDZrrkz", LIEF::assembly::x86::OPCODE::VMOVAPDZrrkz) + .value("VMOVAPDZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPDZrrkz_REV) + .value("VMOVAPDmr", LIEF::assembly::x86::OPCODE::VMOVAPDmr) + .value("VMOVAPDrm", LIEF::assembly::x86::OPCODE::VMOVAPDrm) + .value("VMOVAPDrr", LIEF::assembly::x86::OPCODE::VMOVAPDrr) + .value("VMOVAPDrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPDrr_REV) + .value("VMOVAPSYmr", LIEF::assembly::x86::OPCODE::VMOVAPSYmr) + .value("VMOVAPSYrm", LIEF::assembly::x86::OPCODE::VMOVAPSYrm) + .value("VMOVAPSYrr", LIEF::assembly::x86::OPCODE::VMOVAPSYrr) + .value("VMOVAPSYrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPSYrr_REV) + .value("VMOVAPSZ128mr", LIEF::assembly::x86::OPCODE::VMOVAPSZ128mr) + .value("VMOVAPSZ128mrk", LIEF::assembly::x86::OPCODE::VMOVAPSZ128mrk) + .value("VMOVAPSZ128rm", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rm) + .value("VMOVAPSZ128rmk", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rmk) + .value("VMOVAPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rmkz) + .value("VMOVAPSZ128rr", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rr) + .value("VMOVAPSZ128rr_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rr_REV) + .value("VMOVAPSZ128rrk", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rrk) + .value("VMOVAPSZ128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rrk_REV) + .value("VMOVAPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rrkz); + opcodes.value("VMOVAPSZ128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ128rrkz_REV) + .value("VMOVAPSZ256mr", LIEF::assembly::x86::OPCODE::VMOVAPSZ256mr) + .value("VMOVAPSZ256mrk", LIEF::assembly::x86::OPCODE::VMOVAPSZ256mrk) + .value("VMOVAPSZ256rm", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rm) + .value("VMOVAPSZ256rmk", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rmk) + .value("VMOVAPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rmkz) + .value("VMOVAPSZ256rr", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rr) + .value("VMOVAPSZ256rr_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rr_REV) + .value("VMOVAPSZ256rrk", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rrk) + .value("VMOVAPSZ256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rrk_REV) + .value("VMOVAPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rrkz) + .value("VMOVAPSZ256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZ256rrkz_REV) + .value("VMOVAPSZmr", LIEF::assembly::x86::OPCODE::VMOVAPSZmr) + .value("VMOVAPSZmrk", LIEF::assembly::x86::OPCODE::VMOVAPSZmrk) + .value("VMOVAPSZrm", LIEF::assembly::x86::OPCODE::VMOVAPSZrm) + .value("VMOVAPSZrmk", LIEF::assembly::x86::OPCODE::VMOVAPSZrmk) + .value("VMOVAPSZrmkz", LIEF::assembly::x86::OPCODE::VMOVAPSZrmkz) + .value("VMOVAPSZrr", LIEF::assembly::x86::OPCODE::VMOVAPSZrr) + .value("VMOVAPSZrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZrr_REV) + .value("VMOVAPSZrrk", LIEF::assembly::x86::OPCODE::VMOVAPSZrrk) + .value("VMOVAPSZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZrrk_REV) + .value("VMOVAPSZrrkz", LIEF::assembly::x86::OPCODE::VMOVAPSZrrkz) + .value("VMOVAPSZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVAPSZrrkz_REV) + .value("VMOVAPSmr", LIEF::assembly::x86::OPCODE::VMOVAPSmr) + .value("VMOVAPSrm", LIEF::assembly::x86::OPCODE::VMOVAPSrm) + .value("VMOVAPSrr", LIEF::assembly::x86::OPCODE::VMOVAPSrr) + .value("VMOVAPSrr_REV", LIEF::assembly::x86::OPCODE::VMOVAPSrr_REV) + .value("VMOVDDUPYrm", LIEF::assembly::x86::OPCODE::VMOVDDUPYrm) + .value("VMOVDDUPYrr", LIEF::assembly::x86::OPCODE::VMOVDDUPYrr) + .value("VMOVDDUPZ128rm", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rm) + .value("VMOVDDUPZ128rmk", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rmk) + .value("VMOVDDUPZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rmkz) + .value("VMOVDDUPZ128rr", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rr) + .value("VMOVDDUPZ128rrk", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rrk) + .value("VMOVDDUPZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZ128rrkz) + .value("VMOVDDUPZ256rm", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rm) + .value("VMOVDDUPZ256rmk", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rmk) + .value("VMOVDDUPZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rmkz) + .value("VMOVDDUPZ256rr", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rr) + .value("VMOVDDUPZ256rrk", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rrk) + .value("VMOVDDUPZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZ256rrkz) + .value("VMOVDDUPZrm", LIEF::assembly::x86::OPCODE::VMOVDDUPZrm) + .value("VMOVDDUPZrmk", LIEF::assembly::x86::OPCODE::VMOVDDUPZrmk) + .value("VMOVDDUPZrmkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZrmkz) + .value("VMOVDDUPZrr", LIEF::assembly::x86::OPCODE::VMOVDDUPZrr) + .value("VMOVDDUPZrrk", LIEF::assembly::x86::OPCODE::VMOVDDUPZrrk) + .value("VMOVDDUPZrrkz", LIEF::assembly::x86::OPCODE::VMOVDDUPZrrkz) + .value("VMOVDDUPrm", LIEF::assembly::x86::OPCODE::VMOVDDUPrm) + .value("VMOVDDUPrr", LIEF::assembly::x86::OPCODE::VMOVDDUPrr) + .value("VMOVDI2PDIZrm", LIEF::assembly::x86::OPCODE::VMOVDI2PDIZrm) + .value("VMOVDI2PDIZrr", LIEF::assembly::x86::OPCODE::VMOVDI2PDIZrr) + .value("VMOVDI2PDIrm", LIEF::assembly::x86::OPCODE::VMOVDI2PDIrm) + .value("VMOVDI2PDIrr", LIEF::assembly::x86::OPCODE::VMOVDI2PDIrr) + .value("VMOVDI2SSZrr", LIEF::assembly::x86::OPCODE::VMOVDI2SSZrr) + .value("VMOVDI2SSrr", LIEF::assembly::x86::OPCODE::VMOVDI2SSrr) + .value("VMOVDQA32Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128mr) + .value("VMOVDQA32Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128mrk) + .value("VMOVDQA32Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rm) + .value("VMOVDQA32Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rmk) + .value("VMOVDQA32Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rmkz) + .value("VMOVDQA32Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rr) + .value("VMOVDQA32Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rr_REV) + .value("VMOVDQA32Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rrk) + .value("VMOVDQA32Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rrk_REV) + .value("VMOVDQA32Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rrkz) + .value("VMOVDQA32Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z128rrkz_REV) + .value("VMOVDQA32Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256mr) + .value("VMOVDQA32Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256mrk) + .value("VMOVDQA32Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rm) + .value("VMOVDQA32Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rmk) + .value("VMOVDQA32Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rmkz) + .value("VMOVDQA32Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rr) + .value("VMOVDQA32Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rr_REV) + .value("VMOVDQA32Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rrk) + .value("VMOVDQA32Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rrk_REV) + .value("VMOVDQA32Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rrkz) + .value("VMOVDQA32Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Z256rrkz_REV) + .value("VMOVDQA32Zmr", LIEF::assembly::x86::OPCODE::VMOVDQA32Zmr) + .value("VMOVDQA32Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Zmrk) + .value("VMOVDQA32Zrm", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrm) + .value("VMOVDQA32Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrmk) + .value("VMOVDQA32Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrmkz) + .value("VMOVDQA32Zrr", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrr) + .value("VMOVDQA32Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrr_REV) + .value("VMOVDQA32Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrrk) + .value("VMOVDQA32Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrrk_REV) + .value("VMOVDQA32Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrrkz) + .value("VMOVDQA32Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA32Zrrkz_REV) + .value("VMOVDQA64Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128mr) + .value("VMOVDQA64Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128mrk) + .value("VMOVDQA64Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rm) + .value("VMOVDQA64Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rmk) + .value("VMOVDQA64Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rmkz) + .value("VMOVDQA64Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rr) + .value("VMOVDQA64Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rr_REV) + .value("VMOVDQA64Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rrk) + .value("VMOVDQA64Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rrk_REV) + .value("VMOVDQA64Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rrkz) + .value("VMOVDQA64Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z128rrkz_REV) + .value("VMOVDQA64Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256mr) + .value("VMOVDQA64Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256mrk) + .value("VMOVDQA64Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rm) + .value("VMOVDQA64Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rmk) + .value("VMOVDQA64Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rmkz) + .value("VMOVDQA64Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rr) + .value("VMOVDQA64Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rr_REV) + .value("VMOVDQA64Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rrk) + .value("VMOVDQA64Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rrk_REV) + .value("VMOVDQA64Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rrkz) + .value("VMOVDQA64Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Z256rrkz_REV) + .value("VMOVDQA64Zmr", LIEF::assembly::x86::OPCODE::VMOVDQA64Zmr) + .value("VMOVDQA64Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Zmrk) + .value("VMOVDQA64Zrm", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrm) + .value("VMOVDQA64Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrmk) + .value("VMOVDQA64Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrmkz) + .value("VMOVDQA64Zrr", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrr) + .value("VMOVDQA64Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrr_REV) + .value("VMOVDQA64Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrrk) + .value("VMOVDQA64Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrrk_REV) + .value("VMOVDQA64Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrrkz) + .value("VMOVDQA64Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQA64Zrrkz_REV) + .value("VMOVDQAYmr", LIEF::assembly::x86::OPCODE::VMOVDQAYmr) + .value("VMOVDQAYrm", LIEF::assembly::x86::OPCODE::VMOVDQAYrm) + .value("VMOVDQAYrr", LIEF::assembly::x86::OPCODE::VMOVDQAYrr) + .value("VMOVDQAYrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQAYrr_REV) + .value("VMOVDQAmr", LIEF::assembly::x86::OPCODE::VMOVDQAmr) + .value("VMOVDQArm", LIEF::assembly::x86::OPCODE::VMOVDQArm) + .value("VMOVDQArr", LIEF::assembly::x86::OPCODE::VMOVDQArr) + .value("VMOVDQArr_REV", LIEF::assembly::x86::OPCODE::VMOVDQArr_REV) + .value("VMOVDQU16Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128mr) + .value("VMOVDQU16Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128mrk) + .value("VMOVDQU16Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rm) + .value("VMOVDQU16Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rmk) + .value("VMOVDQU16Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rmkz) + .value("VMOVDQU16Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rr) + .value("VMOVDQU16Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rr_REV) + .value("VMOVDQU16Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rrk) + .value("VMOVDQU16Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rrk_REV) + .value("VMOVDQU16Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rrkz) + .value("VMOVDQU16Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z128rrkz_REV) + .value("VMOVDQU16Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256mr) + .value("VMOVDQU16Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256mrk) + .value("VMOVDQU16Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rm) + .value("VMOVDQU16Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rmk) + .value("VMOVDQU16Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rmkz) + .value("VMOVDQU16Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rr) + .value("VMOVDQU16Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rr_REV) + .value("VMOVDQU16Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rrk) + .value("VMOVDQU16Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rrk_REV) + .value("VMOVDQU16Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rrkz) + .value("VMOVDQU16Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Z256rrkz_REV) + .value("VMOVDQU16Zmr", LIEF::assembly::x86::OPCODE::VMOVDQU16Zmr) + .value("VMOVDQU16Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Zmrk) + .value("VMOVDQU16Zrm", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrm) + .value("VMOVDQU16Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrmk) + .value("VMOVDQU16Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrmkz) + .value("VMOVDQU16Zrr", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrr) + .value("VMOVDQU16Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrr_REV) + .value("VMOVDQU16Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrrk) + .value("VMOVDQU16Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrrk_REV) + .value("VMOVDQU16Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrrkz) + .value("VMOVDQU16Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU16Zrrkz_REV) + .value("VMOVDQU32Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128mr) + .value("VMOVDQU32Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128mrk) + .value("VMOVDQU32Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rm) + .value("VMOVDQU32Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rmk) + .value("VMOVDQU32Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rmkz) + .value("VMOVDQU32Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rr) + .value("VMOVDQU32Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rr_REV) + .value("VMOVDQU32Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rrk) + .value("VMOVDQU32Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rrk_REV) + .value("VMOVDQU32Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rrkz) + .value("VMOVDQU32Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z128rrkz_REV) + .value("VMOVDQU32Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256mr) + .value("VMOVDQU32Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256mrk) + .value("VMOVDQU32Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rm) + .value("VMOVDQU32Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rmk) + .value("VMOVDQU32Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rmkz) + .value("VMOVDQU32Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rr) + .value("VMOVDQU32Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rr_REV) + .value("VMOVDQU32Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rrk) + .value("VMOVDQU32Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rrk_REV) + .value("VMOVDQU32Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rrkz) + .value("VMOVDQU32Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Z256rrkz_REV) + .value("VMOVDQU32Zmr", LIEF::assembly::x86::OPCODE::VMOVDQU32Zmr) + .value("VMOVDQU32Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Zmrk) + .value("VMOVDQU32Zrm", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrm) + .value("VMOVDQU32Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrmk) + .value("VMOVDQU32Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrmkz) + .value("VMOVDQU32Zrr", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrr) + .value("VMOVDQU32Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrr_REV) + .value("VMOVDQU32Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrrk) + .value("VMOVDQU32Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrrk_REV) + .value("VMOVDQU32Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrrkz) + .value("VMOVDQU32Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU32Zrrkz_REV) + .value("VMOVDQU64Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128mr) + .value("VMOVDQU64Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128mrk) + .value("VMOVDQU64Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rm) + .value("VMOVDQU64Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rmk) + .value("VMOVDQU64Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rmkz) + .value("VMOVDQU64Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rr) + .value("VMOVDQU64Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rr_REV) + .value("VMOVDQU64Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rrk) + .value("VMOVDQU64Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rrk_REV) + .value("VMOVDQU64Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rrkz) + .value("VMOVDQU64Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z128rrkz_REV) + .value("VMOVDQU64Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256mr) + .value("VMOVDQU64Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256mrk) + .value("VMOVDQU64Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rm) + .value("VMOVDQU64Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rmk) + .value("VMOVDQU64Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rmkz) + .value("VMOVDQU64Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rr) + .value("VMOVDQU64Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rr_REV) + .value("VMOVDQU64Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rrk) + .value("VMOVDQU64Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rrk_REV) + .value("VMOVDQU64Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rrkz) + .value("VMOVDQU64Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Z256rrkz_REV) + .value("VMOVDQU64Zmr", LIEF::assembly::x86::OPCODE::VMOVDQU64Zmr) + .value("VMOVDQU64Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Zmrk) + .value("VMOVDQU64Zrm", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrm) + .value("VMOVDQU64Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrmk) + .value("VMOVDQU64Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrmkz) + .value("VMOVDQU64Zrr", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrr) + .value("VMOVDQU64Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrr_REV) + .value("VMOVDQU64Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrrk) + .value("VMOVDQU64Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrrk_REV) + .value("VMOVDQU64Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrrkz) + .value("VMOVDQU64Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU64Zrrkz_REV) + .value("VMOVDQU8Z128mr", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128mr) + .value("VMOVDQU8Z128mrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128mrk) + .value("VMOVDQU8Z128rm", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rm) + .value("VMOVDQU8Z128rmk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rmk) + .value("VMOVDQU8Z128rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rmkz) + .value("VMOVDQU8Z128rr", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rr) + .value("VMOVDQU8Z128rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rr_REV) + .value("VMOVDQU8Z128rrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rrk) + .value("VMOVDQU8Z128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rrk_REV) + .value("VMOVDQU8Z128rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rrkz) + .value("VMOVDQU8Z128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z128rrkz_REV) + .value("VMOVDQU8Z256mr", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256mr) + .value("VMOVDQU8Z256mrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256mrk) + .value("VMOVDQU8Z256rm", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rm) + .value("VMOVDQU8Z256rmk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rmk) + .value("VMOVDQU8Z256rmkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rmkz) + .value("VMOVDQU8Z256rr", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rr) + .value("VMOVDQU8Z256rr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rr_REV) + .value("VMOVDQU8Z256rrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rrk) + .value("VMOVDQU8Z256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rrk_REV) + .value("VMOVDQU8Z256rrkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rrkz) + .value("VMOVDQU8Z256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Z256rrkz_REV) + .value("VMOVDQU8Zmr", LIEF::assembly::x86::OPCODE::VMOVDQU8Zmr) + .value("VMOVDQU8Zmrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Zmrk) + .value("VMOVDQU8Zrm", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrm) + .value("VMOVDQU8Zrmk", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrmk) + .value("VMOVDQU8Zrmkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrmkz) + .value("VMOVDQU8Zrr", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrr) + .value("VMOVDQU8Zrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrr_REV) + .value("VMOVDQU8Zrrk", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrrk) + .value("VMOVDQU8Zrrk_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrrk_REV) + .value("VMOVDQU8Zrrkz", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrrkz) + .value("VMOVDQU8Zrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVDQU8Zrrkz_REV) + .value("VMOVDQUYmr", LIEF::assembly::x86::OPCODE::VMOVDQUYmr) + .value("VMOVDQUYrm", LIEF::assembly::x86::OPCODE::VMOVDQUYrm) + .value("VMOVDQUYrr", LIEF::assembly::x86::OPCODE::VMOVDQUYrr) + .value("VMOVDQUYrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQUYrr_REV) + .value("VMOVDQUmr", LIEF::assembly::x86::OPCODE::VMOVDQUmr) + .value("VMOVDQUrm", LIEF::assembly::x86::OPCODE::VMOVDQUrm) + .value("VMOVDQUrr", LIEF::assembly::x86::OPCODE::VMOVDQUrr) + .value("VMOVDQUrr_REV", LIEF::assembly::x86::OPCODE::VMOVDQUrr_REV) + .value("VMOVHLPSZrr", LIEF::assembly::x86::OPCODE::VMOVHLPSZrr) + .value("VMOVHLPSrr", LIEF::assembly::x86::OPCODE::VMOVHLPSrr) + .value("VMOVHPDZ128mr", LIEF::assembly::x86::OPCODE::VMOVHPDZ128mr) + .value("VMOVHPDZ128rm", LIEF::assembly::x86::OPCODE::VMOVHPDZ128rm) + .value("VMOVHPDmr", LIEF::assembly::x86::OPCODE::VMOVHPDmr) + .value("VMOVHPDrm", LIEF::assembly::x86::OPCODE::VMOVHPDrm) + .value("VMOVHPSZ128mr", LIEF::assembly::x86::OPCODE::VMOVHPSZ128mr) + .value("VMOVHPSZ128rm", LIEF::assembly::x86::OPCODE::VMOVHPSZ128rm) + .value("VMOVHPSmr", LIEF::assembly::x86::OPCODE::VMOVHPSmr) + .value("VMOVHPSrm", LIEF::assembly::x86::OPCODE::VMOVHPSrm) + .value("VMOVLHPSZrr", LIEF::assembly::x86::OPCODE::VMOVLHPSZrr) + .value("VMOVLHPSrr", LIEF::assembly::x86::OPCODE::VMOVLHPSrr) + .value("VMOVLPDZ128mr", LIEF::assembly::x86::OPCODE::VMOVLPDZ128mr) + .value("VMOVLPDZ128rm", LIEF::assembly::x86::OPCODE::VMOVLPDZ128rm) + .value("VMOVLPDmr", LIEF::assembly::x86::OPCODE::VMOVLPDmr) + .value("VMOVLPDrm", LIEF::assembly::x86::OPCODE::VMOVLPDrm) + .value("VMOVLPSZ128mr", LIEF::assembly::x86::OPCODE::VMOVLPSZ128mr) + .value("VMOVLPSZ128rm", LIEF::assembly::x86::OPCODE::VMOVLPSZ128rm) + .value("VMOVLPSmr", LIEF::assembly::x86::OPCODE::VMOVLPSmr) + .value("VMOVLPSrm", LIEF::assembly::x86::OPCODE::VMOVLPSrm) + .value("VMOVMSKPDYrr", LIEF::assembly::x86::OPCODE::VMOVMSKPDYrr) + .value("VMOVMSKPDrr", LIEF::assembly::x86::OPCODE::VMOVMSKPDrr) + .value("VMOVMSKPSYrr", LIEF::assembly::x86::OPCODE::VMOVMSKPSYrr) + .value("VMOVMSKPSrr", LIEF::assembly::x86::OPCODE::VMOVMSKPSrr) + .value("VMOVNTDQAYrm", LIEF::assembly::x86::OPCODE::VMOVNTDQAYrm) + .value("VMOVNTDQAZ128rm", LIEF::assembly::x86::OPCODE::VMOVNTDQAZ128rm) + .value("VMOVNTDQAZ256rm", LIEF::assembly::x86::OPCODE::VMOVNTDQAZ256rm) + .value("VMOVNTDQAZrm", LIEF::assembly::x86::OPCODE::VMOVNTDQAZrm) + .value("VMOVNTDQArm", LIEF::assembly::x86::OPCODE::VMOVNTDQArm) + .value("VMOVNTDQYmr", LIEF::assembly::x86::OPCODE::VMOVNTDQYmr) + .value("VMOVNTDQZ128mr", LIEF::assembly::x86::OPCODE::VMOVNTDQZ128mr); + opcodes.value("VMOVNTDQZ256mr", LIEF::assembly::x86::OPCODE::VMOVNTDQZ256mr) + .value("VMOVNTDQZmr", LIEF::assembly::x86::OPCODE::VMOVNTDQZmr) + .value("VMOVNTDQmr", LIEF::assembly::x86::OPCODE::VMOVNTDQmr) + .value("VMOVNTPDYmr", LIEF::assembly::x86::OPCODE::VMOVNTPDYmr) + .value("VMOVNTPDZ128mr", LIEF::assembly::x86::OPCODE::VMOVNTPDZ128mr) + .value("VMOVNTPDZ256mr", LIEF::assembly::x86::OPCODE::VMOVNTPDZ256mr) + .value("VMOVNTPDZmr", LIEF::assembly::x86::OPCODE::VMOVNTPDZmr) + .value("VMOVNTPDmr", LIEF::assembly::x86::OPCODE::VMOVNTPDmr) + .value("VMOVNTPSYmr", LIEF::assembly::x86::OPCODE::VMOVNTPSYmr) + .value("VMOVNTPSZ128mr", LIEF::assembly::x86::OPCODE::VMOVNTPSZ128mr) + .value("VMOVNTPSZ256mr", LIEF::assembly::x86::OPCODE::VMOVNTPSZ256mr) + .value("VMOVNTPSZmr", LIEF::assembly::x86::OPCODE::VMOVNTPSZmr) + .value("VMOVNTPSmr", LIEF::assembly::x86::OPCODE::VMOVNTPSmr) + .value("VMOVPDI2DIZmr", LIEF::assembly::x86::OPCODE::VMOVPDI2DIZmr) + .value("VMOVPDI2DIZrr", LIEF::assembly::x86::OPCODE::VMOVPDI2DIZrr) + .value("VMOVPDI2DImr", LIEF::assembly::x86::OPCODE::VMOVPDI2DImr) + .value("VMOVPDI2DIrr", LIEF::assembly::x86::OPCODE::VMOVPDI2DIrr) + .value("VMOVPQI2QIZmr", LIEF::assembly::x86::OPCODE::VMOVPQI2QIZmr) + .value("VMOVPQI2QIZrr", LIEF::assembly::x86::OPCODE::VMOVPQI2QIZrr) + .value("VMOVPQI2QImr", LIEF::assembly::x86::OPCODE::VMOVPQI2QImr) + .value("VMOVPQI2QIrr", LIEF::assembly::x86::OPCODE::VMOVPQI2QIrr) + .value("VMOVPQIto64Zmr", LIEF::assembly::x86::OPCODE::VMOVPQIto64Zmr) + .value("VMOVPQIto64Zrr", LIEF::assembly::x86::OPCODE::VMOVPQIto64Zrr) + .value("VMOVPQIto64mr", LIEF::assembly::x86::OPCODE::VMOVPQIto64mr) + .value("VMOVPQIto64rr", LIEF::assembly::x86::OPCODE::VMOVPQIto64rr) + .value("VMOVQI2PQIZrm", LIEF::assembly::x86::OPCODE::VMOVQI2PQIZrm) + .value("VMOVQI2PQIrm", LIEF::assembly::x86::OPCODE::VMOVQI2PQIrm) + .value("VMOVRSBZ128m", LIEF::assembly::x86::OPCODE::VMOVRSBZ128m) + .value("VMOVRSBZ128mk", LIEF::assembly::x86::OPCODE::VMOVRSBZ128mk) + .value("VMOVRSBZ128mkz", LIEF::assembly::x86::OPCODE::VMOVRSBZ128mkz) + .value("VMOVRSBZ256m", LIEF::assembly::x86::OPCODE::VMOVRSBZ256m) + .value("VMOVRSBZ256mk", LIEF::assembly::x86::OPCODE::VMOVRSBZ256mk) + .value("VMOVRSBZ256mkz", LIEF::assembly::x86::OPCODE::VMOVRSBZ256mkz) + .value("VMOVRSBZm", LIEF::assembly::x86::OPCODE::VMOVRSBZm) + .value("VMOVRSBZmk", LIEF::assembly::x86::OPCODE::VMOVRSBZmk) + .value("VMOVRSBZmkz", LIEF::assembly::x86::OPCODE::VMOVRSBZmkz) + .value("VMOVRSDZ128m", LIEF::assembly::x86::OPCODE::VMOVRSDZ128m) + .value("VMOVRSDZ128mk", LIEF::assembly::x86::OPCODE::VMOVRSDZ128mk) + .value("VMOVRSDZ128mkz", LIEF::assembly::x86::OPCODE::VMOVRSDZ128mkz) + .value("VMOVRSDZ256m", LIEF::assembly::x86::OPCODE::VMOVRSDZ256m) + .value("VMOVRSDZ256mk", LIEF::assembly::x86::OPCODE::VMOVRSDZ256mk) + .value("VMOVRSDZ256mkz", LIEF::assembly::x86::OPCODE::VMOVRSDZ256mkz) + .value("VMOVRSDZm", LIEF::assembly::x86::OPCODE::VMOVRSDZm) + .value("VMOVRSDZmk", LIEF::assembly::x86::OPCODE::VMOVRSDZmk) + .value("VMOVRSDZmkz", LIEF::assembly::x86::OPCODE::VMOVRSDZmkz) + .value("VMOVRSQZ128m", LIEF::assembly::x86::OPCODE::VMOVRSQZ128m) + .value("VMOVRSQZ128mk", LIEF::assembly::x86::OPCODE::VMOVRSQZ128mk) + .value("VMOVRSQZ128mkz", LIEF::assembly::x86::OPCODE::VMOVRSQZ128mkz) + .value("VMOVRSQZ256m", LIEF::assembly::x86::OPCODE::VMOVRSQZ256m) + .value("VMOVRSQZ256mk", LIEF::assembly::x86::OPCODE::VMOVRSQZ256mk) + .value("VMOVRSQZ256mkz", LIEF::assembly::x86::OPCODE::VMOVRSQZ256mkz) + .value("VMOVRSQZm", LIEF::assembly::x86::OPCODE::VMOVRSQZm) + .value("VMOVRSQZmk", LIEF::assembly::x86::OPCODE::VMOVRSQZmk) + .value("VMOVRSQZmkz", LIEF::assembly::x86::OPCODE::VMOVRSQZmkz) + .value("VMOVRSWZ128m", LIEF::assembly::x86::OPCODE::VMOVRSWZ128m) + .value("VMOVRSWZ128mk", LIEF::assembly::x86::OPCODE::VMOVRSWZ128mk) + .value("VMOVRSWZ128mkz", LIEF::assembly::x86::OPCODE::VMOVRSWZ128mkz) + .value("VMOVRSWZ256m", LIEF::assembly::x86::OPCODE::VMOVRSWZ256m) + .value("VMOVRSWZ256mk", LIEF::assembly::x86::OPCODE::VMOVRSWZ256mk) + .value("VMOVRSWZ256mkz", LIEF::assembly::x86::OPCODE::VMOVRSWZ256mkz) + .value("VMOVRSWZm", LIEF::assembly::x86::OPCODE::VMOVRSWZm) + .value("VMOVRSWZmk", LIEF::assembly::x86::OPCODE::VMOVRSWZmk) + .value("VMOVRSWZmkz", LIEF::assembly::x86::OPCODE::VMOVRSWZmkz) + .value("VMOVSDZmr", LIEF::assembly::x86::OPCODE::VMOVSDZmr) + .value("VMOVSDZmrk", LIEF::assembly::x86::OPCODE::VMOVSDZmrk) + .value("VMOVSDZrm", LIEF::assembly::x86::OPCODE::VMOVSDZrm) + .value("VMOVSDZrm_alt", LIEF::assembly::x86::OPCODE::VMOVSDZrm_alt) + .value("VMOVSDZrmk", LIEF::assembly::x86::OPCODE::VMOVSDZrmk) + .value("VMOVSDZrmkz", LIEF::assembly::x86::OPCODE::VMOVSDZrmkz) + .value("VMOVSDZrr", LIEF::assembly::x86::OPCODE::VMOVSDZrr) + .value("VMOVSDZrr_REV", LIEF::assembly::x86::OPCODE::VMOVSDZrr_REV) + .value("VMOVSDZrrk", LIEF::assembly::x86::OPCODE::VMOVSDZrrk) + .value("VMOVSDZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVSDZrrk_REV) + .value("VMOVSDZrrkz", LIEF::assembly::x86::OPCODE::VMOVSDZrrkz) + .value("VMOVSDZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVSDZrrkz_REV) + .value("VMOVSDmr", LIEF::assembly::x86::OPCODE::VMOVSDmr) + .value("VMOVSDrm", LIEF::assembly::x86::OPCODE::VMOVSDrm) + .value("VMOVSDrm_alt", LIEF::assembly::x86::OPCODE::VMOVSDrm_alt) + .value("VMOVSDrr", LIEF::assembly::x86::OPCODE::VMOVSDrr) + .value("VMOVSDrr_REV", LIEF::assembly::x86::OPCODE::VMOVSDrr_REV) + .value("VMOVSDto64Zrr", LIEF::assembly::x86::OPCODE::VMOVSDto64Zrr) + .value("VMOVSDto64rr", LIEF::assembly::x86::OPCODE::VMOVSDto64rr) + .value("VMOVSH2Wrr", LIEF::assembly::x86::OPCODE::VMOVSH2Wrr) + .value("VMOVSHDUPYrm", LIEF::assembly::x86::OPCODE::VMOVSHDUPYrm) + .value("VMOVSHDUPYrr", LIEF::assembly::x86::OPCODE::VMOVSHDUPYrr) + .value("VMOVSHDUPZ128rm", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rm) + .value("VMOVSHDUPZ128rmk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rmk) + .value("VMOVSHDUPZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rmkz) + .value("VMOVSHDUPZ128rr", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rr) + .value("VMOVSHDUPZ128rrk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rrk) + .value("VMOVSHDUPZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ128rrkz) + .value("VMOVSHDUPZ256rm", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rm) + .value("VMOVSHDUPZ256rmk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rmk) + .value("VMOVSHDUPZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rmkz) + .value("VMOVSHDUPZ256rr", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rr) + .value("VMOVSHDUPZ256rrk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rrk) + .value("VMOVSHDUPZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZ256rrkz) + .value("VMOVSHDUPZrm", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrm) + .value("VMOVSHDUPZrmk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrmk) + .value("VMOVSHDUPZrmkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrmkz) + .value("VMOVSHDUPZrr", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrr) + .value("VMOVSHDUPZrrk", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrrk) + .value("VMOVSHDUPZrrkz", LIEF::assembly::x86::OPCODE::VMOVSHDUPZrrkz) + .value("VMOVSHDUPrm", LIEF::assembly::x86::OPCODE::VMOVSHDUPrm) + .value("VMOVSHDUPrr", LIEF::assembly::x86::OPCODE::VMOVSHDUPrr) + .value("VMOVSHZmr", LIEF::assembly::x86::OPCODE::VMOVSHZmr) + .value("VMOVSHZmrk", LIEF::assembly::x86::OPCODE::VMOVSHZmrk) + .value("VMOVSHZrm", LIEF::assembly::x86::OPCODE::VMOVSHZrm) + .value("VMOVSHZrm_alt", LIEF::assembly::x86::OPCODE::VMOVSHZrm_alt) + .value("VMOVSHZrmk", LIEF::assembly::x86::OPCODE::VMOVSHZrmk) + .value("VMOVSHZrmkz", LIEF::assembly::x86::OPCODE::VMOVSHZrmkz) + .value("VMOVSHZrr", LIEF::assembly::x86::OPCODE::VMOVSHZrr) + .value("VMOVSHZrr_REV", LIEF::assembly::x86::OPCODE::VMOVSHZrr_REV) + .value("VMOVSHZrrk", LIEF::assembly::x86::OPCODE::VMOVSHZrrk) + .value("VMOVSHZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVSHZrrk_REV) + .value("VMOVSHZrrkz", LIEF::assembly::x86::OPCODE::VMOVSHZrrkz) + .value("VMOVSHZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVSHZrrkz_REV) + .value("VMOVSHtoW64rr", LIEF::assembly::x86::OPCODE::VMOVSHtoW64rr) + .value("VMOVSLDUPYrm", LIEF::assembly::x86::OPCODE::VMOVSLDUPYrm) + .value("VMOVSLDUPYrr", LIEF::assembly::x86::OPCODE::VMOVSLDUPYrr) + .value("VMOVSLDUPZ128rm", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rm) + .value("VMOVSLDUPZ128rmk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rmk) + .value("VMOVSLDUPZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rmkz) + .value("VMOVSLDUPZ128rr", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rr) + .value("VMOVSLDUPZ128rrk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rrk) + .value("VMOVSLDUPZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ128rrkz) + .value("VMOVSLDUPZ256rm", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rm) + .value("VMOVSLDUPZ256rmk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rmk) + .value("VMOVSLDUPZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rmkz) + .value("VMOVSLDUPZ256rr", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rr) + .value("VMOVSLDUPZ256rrk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rrk) + .value("VMOVSLDUPZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZ256rrkz) + .value("VMOVSLDUPZrm", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrm) + .value("VMOVSLDUPZrmk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrmk) + .value("VMOVSLDUPZrmkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrmkz) + .value("VMOVSLDUPZrr", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrr) + .value("VMOVSLDUPZrrk", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrrk) + .value("VMOVSLDUPZrrkz", LIEF::assembly::x86::OPCODE::VMOVSLDUPZrrkz) + .value("VMOVSLDUPrm", LIEF::assembly::x86::OPCODE::VMOVSLDUPrm) + .value("VMOVSLDUPrr", LIEF::assembly::x86::OPCODE::VMOVSLDUPrr) + .value("VMOVSS2DIZrr", LIEF::assembly::x86::OPCODE::VMOVSS2DIZrr) + .value("VMOVSS2DIrr", LIEF::assembly::x86::OPCODE::VMOVSS2DIrr) + .value("VMOVSSZmr", LIEF::assembly::x86::OPCODE::VMOVSSZmr) + .value("VMOVSSZmrk", LIEF::assembly::x86::OPCODE::VMOVSSZmrk) + .value("VMOVSSZrm", LIEF::assembly::x86::OPCODE::VMOVSSZrm) + .value("VMOVSSZrm_alt", LIEF::assembly::x86::OPCODE::VMOVSSZrm_alt) + .value("VMOVSSZrmk", LIEF::assembly::x86::OPCODE::VMOVSSZrmk) + .value("VMOVSSZrmkz", LIEF::assembly::x86::OPCODE::VMOVSSZrmkz) + .value("VMOVSSZrr", LIEF::assembly::x86::OPCODE::VMOVSSZrr) + .value("VMOVSSZrr_REV", LIEF::assembly::x86::OPCODE::VMOVSSZrr_REV) + .value("VMOVSSZrrk", LIEF::assembly::x86::OPCODE::VMOVSSZrrk) + .value("VMOVSSZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVSSZrrk_REV) + .value("VMOVSSZrrkz", LIEF::assembly::x86::OPCODE::VMOVSSZrrkz) + .value("VMOVSSZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVSSZrrkz_REV) + .value("VMOVSSmr", LIEF::assembly::x86::OPCODE::VMOVSSmr) + .value("VMOVSSrm", LIEF::assembly::x86::OPCODE::VMOVSSrm) + .value("VMOVSSrm_alt", LIEF::assembly::x86::OPCODE::VMOVSSrm_alt) + .value("VMOVSSrr", LIEF::assembly::x86::OPCODE::VMOVSSrr) + .value("VMOVSSrr_REV", LIEF::assembly::x86::OPCODE::VMOVSSrr_REV) + .value("VMOVUPDYmr", LIEF::assembly::x86::OPCODE::VMOVUPDYmr) + .value("VMOVUPDYrm", LIEF::assembly::x86::OPCODE::VMOVUPDYrm) + .value("VMOVUPDYrr", LIEF::assembly::x86::OPCODE::VMOVUPDYrr) + .value("VMOVUPDYrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPDYrr_REV) + .value("VMOVUPDZ128mr", LIEF::assembly::x86::OPCODE::VMOVUPDZ128mr) + .value("VMOVUPDZ128mrk", LIEF::assembly::x86::OPCODE::VMOVUPDZ128mrk) + .value("VMOVUPDZ128rm", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rm) + .value("VMOVUPDZ128rmk", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rmk) + .value("VMOVUPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rmkz) + .value("VMOVUPDZ128rr", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rr) + .value("VMOVUPDZ128rr_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rr_REV) + .value("VMOVUPDZ128rrk", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rrk) + .value("VMOVUPDZ128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rrk_REV) + .value("VMOVUPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rrkz) + .value("VMOVUPDZ128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ128rrkz_REV) + .value("VMOVUPDZ256mr", LIEF::assembly::x86::OPCODE::VMOVUPDZ256mr) + .value("VMOVUPDZ256mrk", LIEF::assembly::x86::OPCODE::VMOVUPDZ256mrk) + .value("VMOVUPDZ256rm", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rm) + .value("VMOVUPDZ256rmk", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rmk) + .value("VMOVUPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rmkz) + .value("VMOVUPDZ256rr", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rr) + .value("VMOVUPDZ256rr_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rr_REV) + .value("VMOVUPDZ256rrk", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rrk) + .value("VMOVUPDZ256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rrk_REV) + .value("VMOVUPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rrkz) + .value("VMOVUPDZ256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZ256rrkz_REV) + .value("VMOVUPDZmr", LIEF::assembly::x86::OPCODE::VMOVUPDZmr) + .value("VMOVUPDZmrk", LIEF::assembly::x86::OPCODE::VMOVUPDZmrk) + .value("VMOVUPDZrm", LIEF::assembly::x86::OPCODE::VMOVUPDZrm) + .value("VMOVUPDZrmk", LIEF::assembly::x86::OPCODE::VMOVUPDZrmk) + .value("VMOVUPDZrmkz", LIEF::assembly::x86::OPCODE::VMOVUPDZrmkz) + .value("VMOVUPDZrr", LIEF::assembly::x86::OPCODE::VMOVUPDZrr) + .value("VMOVUPDZrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZrr_REV) + .value("VMOVUPDZrrk", LIEF::assembly::x86::OPCODE::VMOVUPDZrrk) + .value("VMOVUPDZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZrrk_REV) + .value("VMOVUPDZrrkz", LIEF::assembly::x86::OPCODE::VMOVUPDZrrkz) + .value("VMOVUPDZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPDZrrkz_REV) + .value("VMOVUPDmr", LIEF::assembly::x86::OPCODE::VMOVUPDmr) + .value("VMOVUPDrm", LIEF::assembly::x86::OPCODE::VMOVUPDrm) + .value("VMOVUPDrr", LIEF::assembly::x86::OPCODE::VMOVUPDrr) + .value("VMOVUPDrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPDrr_REV) + .value("VMOVUPSYmr", LIEF::assembly::x86::OPCODE::VMOVUPSYmr) + .value("VMOVUPSYrm", LIEF::assembly::x86::OPCODE::VMOVUPSYrm) + .value("VMOVUPSYrr", LIEF::assembly::x86::OPCODE::VMOVUPSYrr) + .value("VMOVUPSYrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPSYrr_REV) + .value("VMOVUPSZ128mr", LIEF::assembly::x86::OPCODE::VMOVUPSZ128mr) + .value("VMOVUPSZ128mrk", LIEF::assembly::x86::OPCODE::VMOVUPSZ128mrk) + .value("VMOVUPSZ128rm", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rm) + .value("VMOVUPSZ128rmk", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rmk) + .value("VMOVUPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rmkz) + .value("VMOVUPSZ128rr", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rr) + .value("VMOVUPSZ128rr_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rr_REV) + .value("VMOVUPSZ128rrk", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rrk) + .value("VMOVUPSZ128rrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rrk_REV) + .value("VMOVUPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rrkz) + .value("VMOVUPSZ128rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ128rrkz_REV) + .value("VMOVUPSZ256mr", LIEF::assembly::x86::OPCODE::VMOVUPSZ256mr) + .value("VMOVUPSZ256mrk", LIEF::assembly::x86::OPCODE::VMOVUPSZ256mrk) + .value("VMOVUPSZ256rm", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rm) + .value("VMOVUPSZ256rmk", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rmk) + .value("VMOVUPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rmkz) + .value("VMOVUPSZ256rr", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rr) + .value("VMOVUPSZ256rr_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rr_REV) + .value("VMOVUPSZ256rrk", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rrk) + .value("VMOVUPSZ256rrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rrk_REV) + .value("VMOVUPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rrkz) + .value("VMOVUPSZ256rrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZ256rrkz_REV) + .value("VMOVUPSZmr", LIEF::assembly::x86::OPCODE::VMOVUPSZmr) + .value("VMOVUPSZmrk", LIEF::assembly::x86::OPCODE::VMOVUPSZmrk) + .value("VMOVUPSZrm", LIEF::assembly::x86::OPCODE::VMOVUPSZrm) + .value("VMOVUPSZrmk", LIEF::assembly::x86::OPCODE::VMOVUPSZrmk) + .value("VMOVUPSZrmkz", LIEF::assembly::x86::OPCODE::VMOVUPSZrmkz) + .value("VMOVUPSZrr", LIEF::assembly::x86::OPCODE::VMOVUPSZrr) + .value("VMOVUPSZrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZrr_REV) + .value("VMOVUPSZrrk", LIEF::assembly::x86::OPCODE::VMOVUPSZrrk) + .value("VMOVUPSZrrk_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZrrk_REV) + .value("VMOVUPSZrrkz", LIEF::assembly::x86::OPCODE::VMOVUPSZrrkz) + .value("VMOVUPSZrrkz_REV", LIEF::assembly::x86::OPCODE::VMOVUPSZrrkz_REV) + .value("VMOVUPSmr", LIEF::assembly::x86::OPCODE::VMOVUPSmr) + .value("VMOVUPSrm", LIEF::assembly::x86::OPCODE::VMOVUPSrm) + .value("VMOVUPSrr", LIEF::assembly::x86::OPCODE::VMOVUPSrr) + .value("VMOVUPSrr_REV", LIEF::assembly::x86::OPCODE::VMOVUPSrr_REV) + .value("VMOVW2SHrr", LIEF::assembly::x86::OPCODE::VMOVW2SHrr) + .value("VMOVW64toSHrr", LIEF::assembly::x86::OPCODE::VMOVW64toSHrr) + .value("VMOVWmr", LIEF::assembly::x86::OPCODE::VMOVWmr) + .value("VMOVWrm", LIEF::assembly::x86::OPCODE::VMOVWrm) + .value("VMOVZPDILo2PDIZmr", LIEF::assembly::x86::OPCODE::VMOVZPDILo2PDIZmr) + .value("VMOVZPDILo2PDIZrm", LIEF::assembly::x86::OPCODE::VMOVZPDILo2PDIZrm) + .value("VMOVZPDILo2PDIZrr", LIEF::assembly::x86::OPCODE::VMOVZPDILo2PDIZrr) + .value("VMOVZPDILo2PDIZrr2", LIEF::assembly::x86::OPCODE::VMOVZPDILo2PDIZrr2) + .value("VMOVZPQILo2PQIZrr", LIEF::assembly::x86::OPCODE::VMOVZPQILo2PQIZrr) + .value("VMOVZPQILo2PQIrr", LIEF::assembly::x86::OPCODE::VMOVZPQILo2PQIrr) + .value("VMOVZPWILo2PWIZmr", LIEF::assembly::x86::OPCODE::VMOVZPWILo2PWIZmr) + .value("VMOVZPWILo2PWIZrm", LIEF::assembly::x86::OPCODE::VMOVZPWILo2PWIZrm) + .value("VMOVZPWILo2PWIZrr", LIEF::assembly::x86::OPCODE::VMOVZPWILo2PWIZrr) + .value("VMOVZPWILo2PWIZrr2", LIEF::assembly::x86::OPCODE::VMOVZPWILo2PWIZrr2) + .value("VMPSADBWYrmi", LIEF::assembly::x86::OPCODE::VMPSADBWYrmi) + .value("VMPSADBWYrri", LIEF::assembly::x86::OPCODE::VMPSADBWYrri) + .value("VMPSADBWZ128rmi", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rmi) + .value("VMPSADBWZ128rmik", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rmik) + .value("VMPSADBWZ128rmikz", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rmikz) + .value("VMPSADBWZ128rri", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rri) + .value("VMPSADBWZ128rrik", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rrik) + .value("VMPSADBWZ128rrikz", LIEF::assembly::x86::OPCODE::VMPSADBWZ128rrikz) + .value("VMPSADBWZ256rmi", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rmi) + .value("VMPSADBWZ256rmik", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rmik) + .value("VMPSADBWZ256rmikz", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rmikz) + .value("VMPSADBWZ256rri", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rri) + .value("VMPSADBWZ256rrik", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rrik) + .value("VMPSADBWZ256rrikz", LIEF::assembly::x86::OPCODE::VMPSADBWZ256rrikz) + .value("VMPSADBWZrmi", LIEF::assembly::x86::OPCODE::VMPSADBWZrmi) + .value("VMPSADBWZrmik", LIEF::assembly::x86::OPCODE::VMPSADBWZrmik) + .value("VMPSADBWZrmikz", LIEF::assembly::x86::OPCODE::VMPSADBWZrmikz) + .value("VMPSADBWZrri", LIEF::assembly::x86::OPCODE::VMPSADBWZrri) + .value("VMPSADBWZrrik", LIEF::assembly::x86::OPCODE::VMPSADBWZrrik) + .value("VMPSADBWZrrikz", LIEF::assembly::x86::OPCODE::VMPSADBWZrrikz) + .value("VMPSADBWrmi", LIEF::assembly::x86::OPCODE::VMPSADBWrmi) + .value("VMPSADBWrri", LIEF::assembly::x86::OPCODE::VMPSADBWrri) + .value("VMPTRLDm", LIEF::assembly::x86::OPCODE::VMPTRLDm) + .value("VMPTRSTm", LIEF::assembly::x86::OPCODE::VMPTRSTm) + .value("VMREAD32mr", LIEF::assembly::x86::OPCODE::VMREAD32mr) + .value("VMREAD32rr", LIEF::assembly::x86::OPCODE::VMREAD32rr) + .value("VMREAD64mr", LIEF::assembly::x86::OPCODE::VMREAD64mr) + .value("VMREAD64rr", LIEF::assembly::x86::OPCODE::VMREAD64rr) + .value("VMRESUME", LIEF::assembly::x86::OPCODE::VMRESUME) + .value("VMRUN32", LIEF::assembly::x86::OPCODE::VMRUN32) + .value("VMRUN64", LIEF::assembly::x86::OPCODE::VMRUN64) + .value("VMSAVE32", LIEF::assembly::x86::OPCODE::VMSAVE32) + .value("VMSAVE64", LIEF::assembly::x86::OPCODE::VMSAVE64) + .value("VMULBF16Z128rm", LIEF::assembly::x86::OPCODE::VMULBF16Z128rm) + .value("VMULBF16Z128rmb", LIEF::assembly::x86::OPCODE::VMULBF16Z128rmb) + .value("VMULBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VMULBF16Z128rmbk) + .value("VMULBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VMULBF16Z128rmbkz) + .value("VMULBF16Z128rmk", LIEF::assembly::x86::OPCODE::VMULBF16Z128rmk) + .value("VMULBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VMULBF16Z128rmkz) + .value("VMULBF16Z128rr", LIEF::assembly::x86::OPCODE::VMULBF16Z128rr) + .value("VMULBF16Z128rrk", LIEF::assembly::x86::OPCODE::VMULBF16Z128rrk) + .value("VMULBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VMULBF16Z128rrkz) + .value("VMULBF16Z256rm", LIEF::assembly::x86::OPCODE::VMULBF16Z256rm) + .value("VMULBF16Z256rmb", LIEF::assembly::x86::OPCODE::VMULBF16Z256rmb) + .value("VMULBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VMULBF16Z256rmbk); + opcodes.value("VMULBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VMULBF16Z256rmbkz) + .value("VMULBF16Z256rmk", LIEF::assembly::x86::OPCODE::VMULBF16Z256rmk) + .value("VMULBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VMULBF16Z256rmkz) + .value("VMULBF16Z256rr", LIEF::assembly::x86::OPCODE::VMULBF16Z256rr) + .value("VMULBF16Z256rrk", LIEF::assembly::x86::OPCODE::VMULBF16Z256rrk) + .value("VMULBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VMULBF16Z256rrkz) + .value("VMULBF16Zrm", LIEF::assembly::x86::OPCODE::VMULBF16Zrm) + .value("VMULBF16Zrmb", LIEF::assembly::x86::OPCODE::VMULBF16Zrmb) + .value("VMULBF16Zrmbk", LIEF::assembly::x86::OPCODE::VMULBF16Zrmbk) + .value("VMULBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VMULBF16Zrmbkz) + .value("VMULBF16Zrmk", LIEF::assembly::x86::OPCODE::VMULBF16Zrmk) + .value("VMULBF16Zrmkz", LIEF::assembly::x86::OPCODE::VMULBF16Zrmkz) + .value("VMULBF16Zrr", LIEF::assembly::x86::OPCODE::VMULBF16Zrr) + .value("VMULBF16Zrrk", LIEF::assembly::x86::OPCODE::VMULBF16Zrrk) + .value("VMULBF16Zrrkz", LIEF::assembly::x86::OPCODE::VMULBF16Zrrkz) + .value("VMULPDYrm", LIEF::assembly::x86::OPCODE::VMULPDYrm) + .value("VMULPDYrr", LIEF::assembly::x86::OPCODE::VMULPDYrr) + .value("VMULPDZ128rm", LIEF::assembly::x86::OPCODE::VMULPDZ128rm) + .value("VMULPDZ128rmb", LIEF::assembly::x86::OPCODE::VMULPDZ128rmb) + .value("VMULPDZ128rmbk", LIEF::assembly::x86::OPCODE::VMULPDZ128rmbk) + .value("VMULPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VMULPDZ128rmbkz) + .value("VMULPDZ128rmk", LIEF::assembly::x86::OPCODE::VMULPDZ128rmk) + .value("VMULPDZ128rmkz", LIEF::assembly::x86::OPCODE::VMULPDZ128rmkz) + .value("VMULPDZ128rr", LIEF::assembly::x86::OPCODE::VMULPDZ128rr) + .value("VMULPDZ128rrk", LIEF::assembly::x86::OPCODE::VMULPDZ128rrk) + .value("VMULPDZ128rrkz", LIEF::assembly::x86::OPCODE::VMULPDZ128rrkz) + .value("VMULPDZ256rm", LIEF::assembly::x86::OPCODE::VMULPDZ256rm) + .value("VMULPDZ256rmb", LIEF::assembly::x86::OPCODE::VMULPDZ256rmb) + .value("VMULPDZ256rmbk", LIEF::assembly::x86::OPCODE::VMULPDZ256rmbk) + .value("VMULPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VMULPDZ256rmbkz) + .value("VMULPDZ256rmk", LIEF::assembly::x86::OPCODE::VMULPDZ256rmk) + .value("VMULPDZ256rmkz", LIEF::assembly::x86::OPCODE::VMULPDZ256rmkz) + .value("VMULPDZ256rr", LIEF::assembly::x86::OPCODE::VMULPDZ256rr) + .value("VMULPDZ256rrk", LIEF::assembly::x86::OPCODE::VMULPDZ256rrk) + .value("VMULPDZ256rrkz", LIEF::assembly::x86::OPCODE::VMULPDZ256rrkz) + .value("VMULPDZrm", LIEF::assembly::x86::OPCODE::VMULPDZrm) + .value("VMULPDZrmb", LIEF::assembly::x86::OPCODE::VMULPDZrmb) + .value("VMULPDZrmbk", LIEF::assembly::x86::OPCODE::VMULPDZrmbk) + .value("VMULPDZrmbkz", LIEF::assembly::x86::OPCODE::VMULPDZrmbkz) + .value("VMULPDZrmk", LIEF::assembly::x86::OPCODE::VMULPDZrmk) + .value("VMULPDZrmkz", LIEF::assembly::x86::OPCODE::VMULPDZrmkz) + .value("VMULPDZrr", LIEF::assembly::x86::OPCODE::VMULPDZrr) + .value("VMULPDZrrb", LIEF::assembly::x86::OPCODE::VMULPDZrrb) + .value("VMULPDZrrbk", LIEF::assembly::x86::OPCODE::VMULPDZrrbk) + .value("VMULPDZrrbkz", LIEF::assembly::x86::OPCODE::VMULPDZrrbkz) + .value("VMULPDZrrk", LIEF::assembly::x86::OPCODE::VMULPDZrrk) + .value("VMULPDZrrkz", LIEF::assembly::x86::OPCODE::VMULPDZrrkz) + .value("VMULPDrm", LIEF::assembly::x86::OPCODE::VMULPDrm) + .value("VMULPDrr", LIEF::assembly::x86::OPCODE::VMULPDrr) + .value("VMULPHZ128rm", LIEF::assembly::x86::OPCODE::VMULPHZ128rm) + .value("VMULPHZ128rmb", LIEF::assembly::x86::OPCODE::VMULPHZ128rmb) + .value("VMULPHZ128rmbk", LIEF::assembly::x86::OPCODE::VMULPHZ128rmbk) + .value("VMULPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VMULPHZ128rmbkz) + .value("VMULPHZ128rmk", LIEF::assembly::x86::OPCODE::VMULPHZ128rmk) + .value("VMULPHZ128rmkz", LIEF::assembly::x86::OPCODE::VMULPHZ128rmkz) + .value("VMULPHZ128rr", LIEF::assembly::x86::OPCODE::VMULPHZ128rr) + .value("VMULPHZ128rrk", LIEF::assembly::x86::OPCODE::VMULPHZ128rrk) + .value("VMULPHZ128rrkz", LIEF::assembly::x86::OPCODE::VMULPHZ128rrkz) + .value("VMULPHZ256rm", LIEF::assembly::x86::OPCODE::VMULPHZ256rm) + .value("VMULPHZ256rmb", LIEF::assembly::x86::OPCODE::VMULPHZ256rmb) + .value("VMULPHZ256rmbk", LIEF::assembly::x86::OPCODE::VMULPHZ256rmbk) + .value("VMULPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VMULPHZ256rmbkz) + .value("VMULPHZ256rmk", LIEF::assembly::x86::OPCODE::VMULPHZ256rmk) + .value("VMULPHZ256rmkz", LIEF::assembly::x86::OPCODE::VMULPHZ256rmkz) + .value("VMULPHZ256rr", LIEF::assembly::x86::OPCODE::VMULPHZ256rr) + .value("VMULPHZ256rrk", LIEF::assembly::x86::OPCODE::VMULPHZ256rrk) + .value("VMULPHZ256rrkz", LIEF::assembly::x86::OPCODE::VMULPHZ256rrkz) + .value("VMULPHZrm", LIEF::assembly::x86::OPCODE::VMULPHZrm) + .value("VMULPHZrmb", LIEF::assembly::x86::OPCODE::VMULPHZrmb) + .value("VMULPHZrmbk", LIEF::assembly::x86::OPCODE::VMULPHZrmbk) + .value("VMULPHZrmbkz", LIEF::assembly::x86::OPCODE::VMULPHZrmbkz) + .value("VMULPHZrmk", LIEF::assembly::x86::OPCODE::VMULPHZrmk) + .value("VMULPHZrmkz", LIEF::assembly::x86::OPCODE::VMULPHZrmkz) + .value("VMULPHZrr", LIEF::assembly::x86::OPCODE::VMULPHZrr) + .value("VMULPHZrrb", LIEF::assembly::x86::OPCODE::VMULPHZrrb) + .value("VMULPHZrrbk", LIEF::assembly::x86::OPCODE::VMULPHZrrbk) + .value("VMULPHZrrbkz", LIEF::assembly::x86::OPCODE::VMULPHZrrbkz) + .value("VMULPHZrrk", LIEF::assembly::x86::OPCODE::VMULPHZrrk) + .value("VMULPHZrrkz", LIEF::assembly::x86::OPCODE::VMULPHZrrkz) + .value("VMULPSYrm", LIEF::assembly::x86::OPCODE::VMULPSYrm) + .value("VMULPSYrr", LIEF::assembly::x86::OPCODE::VMULPSYrr) + .value("VMULPSZ128rm", LIEF::assembly::x86::OPCODE::VMULPSZ128rm) + .value("VMULPSZ128rmb", LIEF::assembly::x86::OPCODE::VMULPSZ128rmb) + .value("VMULPSZ128rmbk", LIEF::assembly::x86::OPCODE::VMULPSZ128rmbk) + .value("VMULPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VMULPSZ128rmbkz) + .value("VMULPSZ128rmk", LIEF::assembly::x86::OPCODE::VMULPSZ128rmk) + .value("VMULPSZ128rmkz", LIEF::assembly::x86::OPCODE::VMULPSZ128rmkz) + .value("VMULPSZ128rr", LIEF::assembly::x86::OPCODE::VMULPSZ128rr) + .value("VMULPSZ128rrk", LIEF::assembly::x86::OPCODE::VMULPSZ128rrk) + .value("VMULPSZ128rrkz", LIEF::assembly::x86::OPCODE::VMULPSZ128rrkz) + .value("VMULPSZ256rm", LIEF::assembly::x86::OPCODE::VMULPSZ256rm) + .value("VMULPSZ256rmb", LIEF::assembly::x86::OPCODE::VMULPSZ256rmb) + .value("VMULPSZ256rmbk", LIEF::assembly::x86::OPCODE::VMULPSZ256rmbk) + .value("VMULPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VMULPSZ256rmbkz) + .value("VMULPSZ256rmk", LIEF::assembly::x86::OPCODE::VMULPSZ256rmk) + .value("VMULPSZ256rmkz", LIEF::assembly::x86::OPCODE::VMULPSZ256rmkz) + .value("VMULPSZ256rr", LIEF::assembly::x86::OPCODE::VMULPSZ256rr) + .value("VMULPSZ256rrk", LIEF::assembly::x86::OPCODE::VMULPSZ256rrk) + .value("VMULPSZ256rrkz", LIEF::assembly::x86::OPCODE::VMULPSZ256rrkz) + .value("VMULPSZrm", LIEF::assembly::x86::OPCODE::VMULPSZrm) + .value("VMULPSZrmb", LIEF::assembly::x86::OPCODE::VMULPSZrmb) + .value("VMULPSZrmbk", LIEF::assembly::x86::OPCODE::VMULPSZrmbk) + .value("VMULPSZrmbkz", LIEF::assembly::x86::OPCODE::VMULPSZrmbkz) + .value("VMULPSZrmk", LIEF::assembly::x86::OPCODE::VMULPSZrmk) + .value("VMULPSZrmkz", LIEF::assembly::x86::OPCODE::VMULPSZrmkz) + .value("VMULPSZrr", LIEF::assembly::x86::OPCODE::VMULPSZrr) + .value("VMULPSZrrb", LIEF::assembly::x86::OPCODE::VMULPSZrrb) + .value("VMULPSZrrbk", LIEF::assembly::x86::OPCODE::VMULPSZrrbk) + .value("VMULPSZrrbkz", LIEF::assembly::x86::OPCODE::VMULPSZrrbkz) + .value("VMULPSZrrk", LIEF::assembly::x86::OPCODE::VMULPSZrrk) + .value("VMULPSZrrkz", LIEF::assembly::x86::OPCODE::VMULPSZrrkz) + .value("VMULPSrm", LIEF::assembly::x86::OPCODE::VMULPSrm) + .value("VMULPSrr", LIEF::assembly::x86::OPCODE::VMULPSrr) + .value("VMULSDZrm", LIEF::assembly::x86::OPCODE::VMULSDZrm) + .value("VMULSDZrm_Int", LIEF::assembly::x86::OPCODE::VMULSDZrm_Int) + .value("VMULSDZrmk_Int", LIEF::assembly::x86::OPCODE::VMULSDZrmk_Int) + .value("VMULSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VMULSDZrmkz_Int) + .value("VMULSDZrr", LIEF::assembly::x86::OPCODE::VMULSDZrr) + .value("VMULSDZrr_Int", LIEF::assembly::x86::OPCODE::VMULSDZrr_Int) + .value("VMULSDZrrb_Int", LIEF::assembly::x86::OPCODE::VMULSDZrrb_Int) + .value("VMULSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VMULSDZrrbk_Int) + .value("VMULSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMULSDZrrbkz_Int) + .value("VMULSDZrrk_Int", LIEF::assembly::x86::OPCODE::VMULSDZrrk_Int) + .value("VMULSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VMULSDZrrkz_Int) + .value("VMULSDrm", LIEF::assembly::x86::OPCODE::VMULSDrm) + .value("VMULSDrm_Int", LIEF::assembly::x86::OPCODE::VMULSDrm_Int) + .value("VMULSDrr", LIEF::assembly::x86::OPCODE::VMULSDrr) + .value("VMULSDrr_Int", LIEF::assembly::x86::OPCODE::VMULSDrr_Int) + .value("VMULSHZrm", LIEF::assembly::x86::OPCODE::VMULSHZrm) + .value("VMULSHZrm_Int", LIEF::assembly::x86::OPCODE::VMULSHZrm_Int) + .value("VMULSHZrmk_Int", LIEF::assembly::x86::OPCODE::VMULSHZrmk_Int) + .value("VMULSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VMULSHZrmkz_Int) + .value("VMULSHZrr", LIEF::assembly::x86::OPCODE::VMULSHZrr) + .value("VMULSHZrr_Int", LIEF::assembly::x86::OPCODE::VMULSHZrr_Int) + .value("VMULSHZrrb_Int", LIEF::assembly::x86::OPCODE::VMULSHZrrb_Int) + .value("VMULSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VMULSHZrrbk_Int) + .value("VMULSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMULSHZrrbkz_Int) + .value("VMULSHZrrk_Int", LIEF::assembly::x86::OPCODE::VMULSHZrrk_Int) + .value("VMULSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VMULSHZrrkz_Int) + .value("VMULSSZrm", LIEF::assembly::x86::OPCODE::VMULSSZrm) + .value("VMULSSZrm_Int", LIEF::assembly::x86::OPCODE::VMULSSZrm_Int) + .value("VMULSSZrmk_Int", LIEF::assembly::x86::OPCODE::VMULSSZrmk_Int) + .value("VMULSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VMULSSZrmkz_Int) + .value("VMULSSZrr", LIEF::assembly::x86::OPCODE::VMULSSZrr) + .value("VMULSSZrr_Int", LIEF::assembly::x86::OPCODE::VMULSSZrr_Int) + .value("VMULSSZrrb_Int", LIEF::assembly::x86::OPCODE::VMULSSZrrb_Int) + .value("VMULSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VMULSSZrrbk_Int) + .value("VMULSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VMULSSZrrbkz_Int) + .value("VMULSSZrrk_Int", LIEF::assembly::x86::OPCODE::VMULSSZrrk_Int) + .value("VMULSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VMULSSZrrkz_Int) + .value("VMULSSrm", LIEF::assembly::x86::OPCODE::VMULSSrm) + .value("VMULSSrm_Int", LIEF::assembly::x86::OPCODE::VMULSSrm_Int) + .value("VMULSSrr", LIEF::assembly::x86::OPCODE::VMULSSrr) + .value("VMULSSrr_Int", LIEF::assembly::x86::OPCODE::VMULSSrr_Int) + .value("VMWRITE32rm", LIEF::assembly::x86::OPCODE::VMWRITE32rm) + .value("VMWRITE32rr", LIEF::assembly::x86::OPCODE::VMWRITE32rr) + .value("VMWRITE64rm", LIEF::assembly::x86::OPCODE::VMWRITE64rm) + .value("VMWRITE64rr", LIEF::assembly::x86::OPCODE::VMWRITE64rr) + .value("VMXOFF", LIEF::assembly::x86::OPCODE::VMXOFF) + .value("VMXON", LIEF::assembly::x86::OPCODE::VMXON) + .value("VORPDYrm", LIEF::assembly::x86::OPCODE::VORPDYrm) + .value("VORPDYrr", LIEF::assembly::x86::OPCODE::VORPDYrr) + .value("VORPDZ128rm", LIEF::assembly::x86::OPCODE::VORPDZ128rm) + .value("VORPDZ128rmb", LIEF::assembly::x86::OPCODE::VORPDZ128rmb) + .value("VORPDZ128rmbk", LIEF::assembly::x86::OPCODE::VORPDZ128rmbk) + .value("VORPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VORPDZ128rmbkz) + .value("VORPDZ128rmk", LIEF::assembly::x86::OPCODE::VORPDZ128rmk) + .value("VORPDZ128rmkz", LIEF::assembly::x86::OPCODE::VORPDZ128rmkz) + .value("VORPDZ128rr", LIEF::assembly::x86::OPCODE::VORPDZ128rr) + .value("VORPDZ128rrk", LIEF::assembly::x86::OPCODE::VORPDZ128rrk) + .value("VORPDZ128rrkz", LIEF::assembly::x86::OPCODE::VORPDZ128rrkz) + .value("VORPDZ256rm", LIEF::assembly::x86::OPCODE::VORPDZ256rm) + .value("VORPDZ256rmb", LIEF::assembly::x86::OPCODE::VORPDZ256rmb) + .value("VORPDZ256rmbk", LIEF::assembly::x86::OPCODE::VORPDZ256rmbk) + .value("VORPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VORPDZ256rmbkz) + .value("VORPDZ256rmk", LIEF::assembly::x86::OPCODE::VORPDZ256rmk) + .value("VORPDZ256rmkz", LIEF::assembly::x86::OPCODE::VORPDZ256rmkz) + .value("VORPDZ256rr", LIEF::assembly::x86::OPCODE::VORPDZ256rr) + .value("VORPDZ256rrk", LIEF::assembly::x86::OPCODE::VORPDZ256rrk) + .value("VORPDZ256rrkz", LIEF::assembly::x86::OPCODE::VORPDZ256rrkz) + .value("VORPDZrm", LIEF::assembly::x86::OPCODE::VORPDZrm) + .value("VORPDZrmb", LIEF::assembly::x86::OPCODE::VORPDZrmb) + .value("VORPDZrmbk", LIEF::assembly::x86::OPCODE::VORPDZrmbk) + .value("VORPDZrmbkz", LIEF::assembly::x86::OPCODE::VORPDZrmbkz) + .value("VORPDZrmk", LIEF::assembly::x86::OPCODE::VORPDZrmk) + .value("VORPDZrmkz", LIEF::assembly::x86::OPCODE::VORPDZrmkz) + .value("VORPDZrr", LIEF::assembly::x86::OPCODE::VORPDZrr) + .value("VORPDZrrk", LIEF::assembly::x86::OPCODE::VORPDZrrk) + .value("VORPDZrrkz", LIEF::assembly::x86::OPCODE::VORPDZrrkz) + .value("VORPDrm", LIEF::assembly::x86::OPCODE::VORPDrm) + .value("VORPDrr", LIEF::assembly::x86::OPCODE::VORPDrr) + .value("VORPSYrm", LIEF::assembly::x86::OPCODE::VORPSYrm) + .value("VORPSYrr", LIEF::assembly::x86::OPCODE::VORPSYrr) + .value("VORPSZ128rm", LIEF::assembly::x86::OPCODE::VORPSZ128rm) + .value("VORPSZ128rmb", LIEF::assembly::x86::OPCODE::VORPSZ128rmb) + .value("VORPSZ128rmbk", LIEF::assembly::x86::OPCODE::VORPSZ128rmbk) + .value("VORPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VORPSZ128rmbkz) + .value("VORPSZ128rmk", LIEF::assembly::x86::OPCODE::VORPSZ128rmk) + .value("VORPSZ128rmkz", LIEF::assembly::x86::OPCODE::VORPSZ128rmkz) + .value("VORPSZ128rr", LIEF::assembly::x86::OPCODE::VORPSZ128rr) + .value("VORPSZ128rrk", LIEF::assembly::x86::OPCODE::VORPSZ128rrk) + .value("VORPSZ128rrkz", LIEF::assembly::x86::OPCODE::VORPSZ128rrkz) + .value("VORPSZ256rm", LIEF::assembly::x86::OPCODE::VORPSZ256rm) + .value("VORPSZ256rmb", LIEF::assembly::x86::OPCODE::VORPSZ256rmb) + .value("VORPSZ256rmbk", LIEF::assembly::x86::OPCODE::VORPSZ256rmbk) + .value("VORPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VORPSZ256rmbkz) + .value("VORPSZ256rmk", LIEF::assembly::x86::OPCODE::VORPSZ256rmk) + .value("VORPSZ256rmkz", LIEF::assembly::x86::OPCODE::VORPSZ256rmkz) + .value("VORPSZ256rr", LIEF::assembly::x86::OPCODE::VORPSZ256rr) + .value("VORPSZ256rrk", LIEF::assembly::x86::OPCODE::VORPSZ256rrk) + .value("VORPSZ256rrkz", LIEF::assembly::x86::OPCODE::VORPSZ256rrkz) + .value("VORPSZrm", LIEF::assembly::x86::OPCODE::VORPSZrm) + .value("VORPSZrmb", LIEF::assembly::x86::OPCODE::VORPSZrmb) + .value("VORPSZrmbk", LIEF::assembly::x86::OPCODE::VORPSZrmbk) + .value("VORPSZrmbkz", LIEF::assembly::x86::OPCODE::VORPSZrmbkz) + .value("VORPSZrmk", LIEF::assembly::x86::OPCODE::VORPSZrmk) + .value("VORPSZrmkz", LIEF::assembly::x86::OPCODE::VORPSZrmkz) + .value("VORPSZrr", LIEF::assembly::x86::OPCODE::VORPSZrr) + .value("VORPSZrrk", LIEF::assembly::x86::OPCODE::VORPSZrrk) + .value("VORPSZrrkz", LIEF::assembly::x86::OPCODE::VORPSZrrkz) + .value("VORPSrm", LIEF::assembly::x86::OPCODE::VORPSrm) + .value("VORPSrr", LIEF::assembly::x86::OPCODE::VORPSrr) + .value("VP2INTERSECTDZ128rm", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ128rm) + .value("VP2INTERSECTDZ128rmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ128rmb) + .value("VP2INTERSECTDZ128rr", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ128rr) + .value("VP2INTERSECTDZ256rm", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ256rm) + .value("VP2INTERSECTDZ256rmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ256rmb) + .value("VP2INTERSECTDZ256rr", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZ256rr) + .value("VP2INTERSECTDZrm", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZrm) + .value("VP2INTERSECTDZrmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZrmb) + .value("VP2INTERSECTDZrr", LIEF::assembly::x86::OPCODE::VP2INTERSECTDZrr) + .value("VP2INTERSECTQZ128rm", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ128rm) + .value("VP2INTERSECTQZ128rmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ128rmb) + .value("VP2INTERSECTQZ128rr", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ128rr) + .value("VP2INTERSECTQZ256rm", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ256rm) + .value("VP2INTERSECTQZ256rmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ256rmb) + .value("VP2INTERSECTQZ256rr", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZ256rr) + .value("VP2INTERSECTQZrm", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZrm) + .value("VP2INTERSECTQZrmb", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZrmb) + .value("VP2INTERSECTQZrr", LIEF::assembly::x86::OPCODE::VP2INTERSECTQZrr) + .value("VP4DPWSSDSrm", LIEF::assembly::x86::OPCODE::VP4DPWSSDSrm) + .value("VP4DPWSSDSrmk", LIEF::assembly::x86::OPCODE::VP4DPWSSDSrmk) + .value("VP4DPWSSDSrmkz", LIEF::assembly::x86::OPCODE::VP4DPWSSDSrmkz) + .value("VP4DPWSSDrm", LIEF::assembly::x86::OPCODE::VP4DPWSSDrm) + .value("VP4DPWSSDrmk", LIEF::assembly::x86::OPCODE::VP4DPWSSDrmk) + .value("VP4DPWSSDrmkz", LIEF::assembly::x86::OPCODE::VP4DPWSSDrmkz) + .value("VPABSBYrm", LIEF::assembly::x86::OPCODE::VPABSBYrm) + .value("VPABSBYrr", LIEF::assembly::x86::OPCODE::VPABSBYrr) + .value("VPABSBZ128rm", LIEF::assembly::x86::OPCODE::VPABSBZ128rm) + .value("VPABSBZ128rmk", LIEF::assembly::x86::OPCODE::VPABSBZ128rmk) + .value("VPABSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPABSBZ128rmkz) + .value("VPABSBZ128rr", LIEF::assembly::x86::OPCODE::VPABSBZ128rr) + .value("VPABSBZ128rrk", LIEF::assembly::x86::OPCODE::VPABSBZ128rrk) + .value("VPABSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPABSBZ128rrkz) + .value("VPABSBZ256rm", LIEF::assembly::x86::OPCODE::VPABSBZ256rm) + .value("VPABSBZ256rmk", LIEF::assembly::x86::OPCODE::VPABSBZ256rmk) + .value("VPABSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPABSBZ256rmkz) + .value("VPABSBZ256rr", LIEF::assembly::x86::OPCODE::VPABSBZ256rr) + .value("VPABSBZ256rrk", LIEF::assembly::x86::OPCODE::VPABSBZ256rrk) + .value("VPABSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPABSBZ256rrkz) + .value("VPABSBZrm", LIEF::assembly::x86::OPCODE::VPABSBZrm) + .value("VPABSBZrmk", LIEF::assembly::x86::OPCODE::VPABSBZrmk) + .value("VPABSBZrmkz", LIEF::assembly::x86::OPCODE::VPABSBZrmkz) + .value("VPABSBZrr", LIEF::assembly::x86::OPCODE::VPABSBZrr) + .value("VPABSBZrrk", LIEF::assembly::x86::OPCODE::VPABSBZrrk) + .value("VPABSBZrrkz", LIEF::assembly::x86::OPCODE::VPABSBZrrkz) + .value("VPABSBrm", LIEF::assembly::x86::OPCODE::VPABSBrm) + .value("VPABSBrr", LIEF::assembly::x86::OPCODE::VPABSBrr) + .value("VPABSDYrm", LIEF::assembly::x86::OPCODE::VPABSDYrm) + .value("VPABSDYrr", LIEF::assembly::x86::OPCODE::VPABSDYrr) + .value("VPABSDZ128rm", LIEF::assembly::x86::OPCODE::VPABSDZ128rm) + .value("VPABSDZ128rmb", LIEF::assembly::x86::OPCODE::VPABSDZ128rmb) + .value("VPABSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPABSDZ128rmbk) + .value("VPABSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPABSDZ128rmbkz) + .value("VPABSDZ128rmk", LIEF::assembly::x86::OPCODE::VPABSDZ128rmk) + .value("VPABSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPABSDZ128rmkz) + .value("VPABSDZ128rr", LIEF::assembly::x86::OPCODE::VPABSDZ128rr) + .value("VPABSDZ128rrk", LIEF::assembly::x86::OPCODE::VPABSDZ128rrk) + .value("VPABSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPABSDZ128rrkz) + .value("VPABSDZ256rm", LIEF::assembly::x86::OPCODE::VPABSDZ256rm) + .value("VPABSDZ256rmb", LIEF::assembly::x86::OPCODE::VPABSDZ256rmb) + .value("VPABSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPABSDZ256rmbk) + .value("VPABSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPABSDZ256rmbkz) + .value("VPABSDZ256rmk", LIEF::assembly::x86::OPCODE::VPABSDZ256rmk) + .value("VPABSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPABSDZ256rmkz) + .value("VPABSDZ256rr", LIEF::assembly::x86::OPCODE::VPABSDZ256rr) + .value("VPABSDZ256rrk", LIEF::assembly::x86::OPCODE::VPABSDZ256rrk) + .value("VPABSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPABSDZ256rrkz) + .value("VPABSDZrm", LIEF::assembly::x86::OPCODE::VPABSDZrm) + .value("VPABSDZrmb", LIEF::assembly::x86::OPCODE::VPABSDZrmb) + .value("VPABSDZrmbk", LIEF::assembly::x86::OPCODE::VPABSDZrmbk) + .value("VPABSDZrmbkz", LIEF::assembly::x86::OPCODE::VPABSDZrmbkz) + .value("VPABSDZrmk", LIEF::assembly::x86::OPCODE::VPABSDZrmk) + .value("VPABSDZrmkz", LIEF::assembly::x86::OPCODE::VPABSDZrmkz) + .value("VPABSDZrr", LIEF::assembly::x86::OPCODE::VPABSDZrr) + .value("VPABSDZrrk", LIEF::assembly::x86::OPCODE::VPABSDZrrk) + .value("VPABSDZrrkz", LIEF::assembly::x86::OPCODE::VPABSDZrrkz) + .value("VPABSDrm", LIEF::assembly::x86::OPCODE::VPABSDrm) + .value("VPABSDrr", LIEF::assembly::x86::OPCODE::VPABSDrr) + .value("VPABSQZ128rm", LIEF::assembly::x86::OPCODE::VPABSQZ128rm); + opcodes.value("VPABSQZ128rmb", LIEF::assembly::x86::OPCODE::VPABSQZ128rmb) + .value("VPABSQZ128rmbk", LIEF::assembly::x86::OPCODE::VPABSQZ128rmbk) + .value("VPABSQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPABSQZ128rmbkz) + .value("VPABSQZ128rmk", LIEF::assembly::x86::OPCODE::VPABSQZ128rmk) + .value("VPABSQZ128rmkz", LIEF::assembly::x86::OPCODE::VPABSQZ128rmkz) + .value("VPABSQZ128rr", LIEF::assembly::x86::OPCODE::VPABSQZ128rr) + .value("VPABSQZ128rrk", LIEF::assembly::x86::OPCODE::VPABSQZ128rrk) + .value("VPABSQZ128rrkz", LIEF::assembly::x86::OPCODE::VPABSQZ128rrkz) + .value("VPABSQZ256rm", LIEF::assembly::x86::OPCODE::VPABSQZ256rm) + .value("VPABSQZ256rmb", LIEF::assembly::x86::OPCODE::VPABSQZ256rmb) + .value("VPABSQZ256rmbk", LIEF::assembly::x86::OPCODE::VPABSQZ256rmbk) + .value("VPABSQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPABSQZ256rmbkz) + .value("VPABSQZ256rmk", LIEF::assembly::x86::OPCODE::VPABSQZ256rmk) + .value("VPABSQZ256rmkz", LIEF::assembly::x86::OPCODE::VPABSQZ256rmkz) + .value("VPABSQZ256rr", LIEF::assembly::x86::OPCODE::VPABSQZ256rr) + .value("VPABSQZ256rrk", LIEF::assembly::x86::OPCODE::VPABSQZ256rrk) + .value("VPABSQZ256rrkz", LIEF::assembly::x86::OPCODE::VPABSQZ256rrkz) + .value("VPABSQZrm", LIEF::assembly::x86::OPCODE::VPABSQZrm) + .value("VPABSQZrmb", LIEF::assembly::x86::OPCODE::VPABSQZrmb) + .value("VPABSQZrmbk", LIEF::assembly::x86::OPCODE::VPABSQZrmbk) + .value("VPABSQZrmbkz", LIEF::assembly::x86::OPCODE::VPABSQZrmbkz) + .value("VPABSQZrmk", LIEF::assembly::x86::OPCODE::VPABSQZrmk) + .value("VPABSQZrmkz", LIEF::assembly::x86::OPCODE::VPABSQZrmkz) + .value("VPABSQZrr", LIEF::assembly::x86::OPCODE::VPABSQZrr) + .value("VPABSQZrrk", LIEF::assembly::x86::OPCODE::VPABSQZrrk) + .value("VPABSQZrrkz", LIEF::assembly::x86::OPCODE::VPABSQZrrkz) + .value("VPABSWYrm", LIEF::assembly::x86::OPCODE::VPABSWYrm) + .value("VPABSWYrr", LIEF::assembly::x86::OPCODE::VPABSWYrr) + .value("VPABSWZ128rm", LIEF::assembly::x86::OPCODE::VPABSWZ128rm) + .value("VPABSWZ128rmk", LIEF::assembly::x86::OPCODE::VPABSWZ128rmk) + .value("VPABSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPABSWZ128rmkz) + .value("VPABSWZ128rr", LIEF::assembly::x86::OPCODE::VPABSWZ128rr) + .value("VPABSWZ128rrk", LIEF::assembly::x86::OPCODE::VPABSWZ128rrk) + .value("VPABSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPABSWZ128rrkz) + .value("VPABSWZ256rm", LIEF::assembly::x86::OPCODE::VPABSWZ256rm) + .value("VPABSWZ256rmk", LIEF::assembly::x86::OPCODE::VPABSWZ256rmk) + .value("VPABSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPABSWZ256rmkz) + .value("VPABSWZ256rr", LIEF::assembly::x86::OPCODE::VPABSWZ256rr) + .value("VPABSWZ256rrk", LIEF::assembly::x86::OPCODE::VPABSWZ256rrk) + .value("VPABSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPABSWZ256rrkz) + .value("VPABSWZrm", LIEF::assembly::x86::OPCODE::VPABSWZrm) + .value("VPABSWZrmk", LIEF::assembly::x86::OPCODE::VPABSWZrmk) + .value("VPABSWZrmkz", LIEF::assembly::x86::OPCODE::VPABSWZrmkz) + .value("VPABSWZrr", LIEF::assembly::x86::OPCODE::VPABSWZrr) + .value("VPABSWZrrk", LIEF::assembly::x86::OPCODE::VPABSWZrrk) + .value("VPABSWZrrkz", LIEF::assembly::x86::OPCODE::VPABSWZrrkz) + .value("VPABSWrm", LIEF::assembly::x86::OPCODE::VPABSWrm) + .value("VPABSWrr", LIEF::assembly::x86::OPCODE::VPABSWrr) + .value("VPACKSSDWYrm", LIEF::assembly::x86::OPCODE::VPACKSSDWYrm) + .value("VPACKSSDWYrr", LIEF::assembly::x86::OPCODE::VPACKSSDWYrr) + .value("VPACKSSDWZ128rm", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rm) + .value("VPACKSSDWZ128rmb", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rmb) + .value("VPACKSSDWZ128rmbk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rmbk) + .value("VPACKSSDWZ128rmbkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rmbkz) + .value("VPACKSSDWZ128rmk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rmk) + .value("VPACKSSDWZ128rmkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rmkz) + .value("VPACKSSDWZ128rr", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rr) + .value("VPACKSSDWZ128rrk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rrk) + .value("VPACKSSDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ128rrkz) + .value("VPACKSSDWZ256rm", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rm) + .value("VPACKSSDWZ256rmb", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rmb) + .value("VPACKSSDWZ256rmbk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rmbk) + .value("VPACKSSDWZ256rmbkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rmbkz) + .value("VPACKSSDWZ256rmk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rmk) + .value("VPACKSSDWZ256rmkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rmkz) + .value("VPACKSSDWZ256rr", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rr) + .value("VPACKSSDWZ256rrk", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rrk) + .value("VPACKSSDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZ256rrkz) + .value("VPACKSSDWZrm", LIEF::assembly::x86::OPCODE::VPACKSSDWZrm) + .value("VPACKSSDWZrmb", LIEF::assembly::x86::OPCODE::VPACKSSDWZrmb) + .value("VPACKSSDWZrmbk", LIEF::assembly::x86::OPCODE::VPACKSSDWZrmbk) + .value("VPACKSSDWZrmbkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZrmbkz) + .value("VPACKSSDWZrmk", LIEF::assembly::x86::OPCODE::VPACKSSDWZrmk) + .value("VPACKSSDWZrmkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZrmkz) + .value("VPACKSSDWZrr", LIEF::assembly::x86::OPCODE::VPACKSSDWZrr) + .value("VPACKSSDWZrrk", LIEF::assembly::x86::OPCODE::VPACKSSDWZrrk) + .value("VPACKSSDWZrrkz", LIEF::assembly::x86::OPCODE::VPACKSSDWZrrkz) + .value("VPACKSSDWrm", LIEF::assembly::x86::OPCODE::VPACKSSDWrm) + .value("VPACKSSDWrr", LIEF::assembly::x86::OPCODE::VPACKSSDWrr) + .value("VPACKSSWBYrm", LIEF::assembly::x86::OPCODE::VPACKSSWBYrm) + .value("VPACKSSWBYrr", LIEF::assembly::x86::OPCODE::VPACKSSWBYrr) + .value("VPACKSSWBZ128rm", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rm) + .value("VPACKSSWBZ128rmk", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rmk) + .value("VPACKSSWBZ128rmkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rmkz) + .value("VPACKSSWBZ128rr", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rr) + .value("VPACKSSWBZ128rrk", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rrk) + .value("VPACKSSWBZ128rrkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZ128rrkz) + .value("VPACKSSWBZ256rm", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rm) + .value("VPACKSSWBZ256rmk", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rmk) + .value("VPACKSSWBZ256rmkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rmkz) + .value("VPACKSSWBZ256rr", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rr) + .value("VPACKSSWBZ256rrk", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rrk) + .value("VPACKSSWBZ256rrkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZ256rrkz) + .value("VPACKSSWBZrm", LIEF::assembly::x86::OPCODE::VPACKSSWBZrm) + .value("VPACKSSWBZrmk", LIEF::assembly::x86::OPCODE::VPACKSSWBZrmk) + .value("VPACKSSWBZrmkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZrmkz) + .value("VPACKSSWBZrr", LIEF::assembly::x86::OPCODE::VPACKSSWBZrr) + .value("VPACKSSWBZrrk", LIEF::assembly::x86::OPCODE::VPACKSSWBZrrk) + .value("VPACKSSWBZrrkz", LIEF::assembly::x86::OPCODE::VPACKSSWBZrrkz) + .value("VPACKSSWBrm", LIEF::assembly::x86::OPCODE::VPACKSSWBrm) + .value("VPACKSSWBrr", LIEF::assembly::x86::OPCODE::VPACKSSWBrr) + .value("VPACKUSDWYrm", LIEF::assembly::x86::OPCODE::VPACKUSDWYrm) + .value("VPACKUSDWYrr", LIEF::assembly::x86::OPCODE::VPACKUSDWYrr) + .value("VPACKUSDWZ128rm", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rm) + .value("VPACKUSDWZ128rmb", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rmb) + .value("VPACKUSDWZ128rmbk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rmbk) + .value("VPACKUSDWZ128rmbkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rmbkz) + .value("VPACKUSDWZ128rmk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rmk) + .value("VPACKUSDWZ128rmkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rmkz) + .value("VPACKUSDWZ128rr", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rr) + .value("VPACKUSDWZ128rrk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rrk) + .value("VPACKUSDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ128rrkz) + .value("VPACKUSDWZ256rm", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rm) + .value("VPACKUSDWZ256rmb", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rmb) + .value("VPACKUSDWZ256rmbk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rmbk) + .value("VPACKUSDWZ256rmbkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rmbkz) + .value("VPACKUSDWZ256rmk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rmk) + .value("VPACKUSDWZ256rmkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rmkz) + .value("VPACKUSDWZ256rr", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rr) + .value("VPACKUSDWZ256rrk", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rrk) + .value("VPACKUSDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZ256rrkz) + .value("VPACKUSDWZrm", LIEF::assembly::x86::OPCODE::VPACKUSDWZrm) + .value("VPACKUSDWZrmb", LIEF::assembly::x86::OPCODE::VPACKUSDWZrmb) + .value("VPACKUSDWZrmbk", LIEF::assembly::x86::OPCODE::VPACKUSDWZrmbk) + .value("VPACKUSDWZrmbkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZrmbkz) + .value("VPACKUSDWZrmk", LIEF::assembly::x86::OPCODE::VPACKUSDWZrmk) + .value("VPACKUSDWZrmkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZrmkz) + .value("VPACKUSDWZrr", LIEF::assembly::x86::OPCODE::VPACKUSDWZrr) + .value("VPACKUSDWZrrk", LIEF::assembly::x86::OPCODE::VPACKUSDWZrrk) + .value("VPACKUSDWZrrkz", LIEF::assembly::x86::OPCODE::VPACKUSDWZrrkz) + .value("VPACKUSDWrm", LIEF::assembly::x86::OPCODE::VPACKUSDWrm) + .value("VPACKUSDWrr", LIEF::assembly::x86::OPCODE::VPACKUSDWrr) + .value("VPACKUSWBYrm", LIEF::assembly::x86::OPCODE::VPACKUSWBYrm) + .value("VPACKUSWBYrr", LIEF::assembly::x86::OPCODE::VPACKUSWBYrr) + .value("VPACKUSWBZ128rm", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rm) + .value("VPACKUSWBZ128rmk", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rmk) + .value("VPACKUSWBZ128rmkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rmkz) + .value("VPACKUSWBZ128rr", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rr) + .value("VPACKUSWBZ128rrk", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rrk) + .value("VPACKUSWBZ128rrkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZ128rrkz) + .value("VPACKUSWBZ256rm", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rm) + .value("VPACKUSWBZ256rmk", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rmk) + .value("VPACKUSWBZ256rmkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rmkz) + .value("VPACKUSWBZ256rr", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rr) + .value("VPACKUSWBZ256rrk", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rrk) + .value("VPACKUSWBZ256rrkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZ256rrkz) + .value("VPACKUSWBZrm", LIEF::assembly::x86::OPCODE::VPACKUSWBZrm) + .value("VPACKUSWBZrmk", LIEF::assembly::x86::OPCODE::VPACKUSWBZrmk) + .value("VPACKUSWBZrmkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZrmkz) + .value("VPACKUSWBZrr", LIEF::assembly::x86::OPCODE::VPACKUSWBZrr) + .value("VPACKUSWBZrrk", LIEF::assembly::x86::OPCODE::VPACKUSWBZrrk) + .value("VPACKUSWBZrrkz", LIEF::assembly::x86::OPCODE::VPACKUSWBZrrkz) + .value("VPACKUSWBrm", LIEF::assembly::x86::OPCODE::VPACKUSWBrm) + .value("VPACKUSWBrr", LIEF::assembly::x86::OPCODE::VPACKUSWBrr) + .value("VPADDBYrm", LIEF::assembly::x86::OPCODE::VPADDBYrm) + .value("VPADDBYrr", LIEF::assembly::x86::OPCODE::VPADDBYrr) + .value("VPADDBZ128rm", LIEF::assembly::x86::OPCODE::VPADDBZ128rm) + .value("VPADDBZ128rmk", LIEF::assembly::x86::OPCODE::VPADDBZ128rmk) + .value("VPADDBZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDBZ128rmkz) + .value("VPADDBZ128rr", LIEF::assembly::x86::OPCODE::VPADDBZ128rr) + .value("VPADDBZ128rrk", LIEF::assembly::x86::OPCODE::VPADDBZ128rrk) + .value("VPADDBZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDBZ128rrkz) + .value("VPADDBZ256rm", LIEF::assembly::x86::OPCODE::VPADDBZ256rm) + .value("VPADDBZ256rmk", LIEF::assembly::x86::OPCODE::VPADDBZ256rmk) + .value("VPADDBZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDBZ256rmkz) + .value("VPADDBZ256rr", LIEF::assembly::x86::OPCODE::VPADDBZ256rr) + .value("VPADDBZ256rrk", LIEF::assembly::x86::OPCODE::VPADDBZ256rrk) + .value("VPADDBZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDBZ256rrkz) + .value("VPADDBZrm", LIEF::assembly::x86::OPCODE::VPADDBZrm) + .value("VPADDBZrmk", LIEF::assembly::x86::OPCODE::VPADDBZrmk) + .value("VPADDBZrmkz", LIEF::assembly::x86::OPCODE::VPADDBZrmkz) + .value("VPADDBZrr", LIEF::assembly::x86::OPCODE::VPADDBZrr) + .value("VPADDBZrrk", LIEF::assembly::x86::OPCODE::VPADDBZrrk) + .value("VPADDBZrrkz", LIEF::assembly::x86::OPCODE::VPADDBZrrkz) + .value("VPADDBrm", LIEF::assembly::x86::OPCODE::VPADDBrm) + .value("VPADDBrr", LIEF::assembly::x86::OPCODE::VPADDBrr) + .value("VPADDDYrm", LIEF::assembly::x86::OPCODE::VPADDDYrm) + .value("VPADDDYrr", LIEF::assembly::x86::OPCODE::VPADDDYrr) + .value("VPADDDZ128rm", LIEF::assembly::x86::OPCODE::VPADDDZ128rm) + .value("VPADDDZ128rmb", LIEF::assembly::x86::OPCODE::VPADDDZ128rmb) + .value("VPADDDZ128rmbk", LIEF::assembly::x86::OPCODE::VPADDDZ128rmbk) + .value("VPADDDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPADDDZ128rmbkz) + .value("VPADDDZ128rmk", LIEF::assembly::x86::OPCODE::VPADDDZ128rmk) + .value("VPADDDZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDDZ128rmkz) + .value("VPADDDZ128rr", LIEF::assembly::x86::OPCODE::VPADDDZ128rr) + .value("VPADDDZ128rrk", LIEF::assembly::x86::OPCODE::VPADDDZ128rrk) + .value("VPADDDZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDDZ128rrkz) + .value("VPADDDZ256rm", LIEF::assembly::x86::OPCODE::VPADDDZ256rm) + .value("VPADDDZ256rmb", LIEF::assembly::x86::OPCODE::VPADDDZ256rmb) + .value("VPADDDZ256rmbk", LIEF::assembly::x86::OPCODE::VPADDDZ256rmbk) + .value("VPADDDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPADDDZ256rmbkz) + .value("VPADDDZ256rmk", LIEF::assembly::x86::OPCODE::VPADDDZ256rmk) + .value("VPADDDZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDDZ256rmkz) + .value("VPADDDZ256rr", LIEF::assembly::x86::OPCODE::VPADDDZ256rr) + .value("VPADDDZ256rrk", LIEF::assembly::x86::OPCODE::VPADDDZ256rrk) + .value("VPADDDZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDDZ256rrkz) + .value("VPADDDZrm", LIEF::assembly::x86::OPCODE::VPADDDZrm) + .value("VPADDDZrmb", LIEF::assembly::x86::OPCODE::VPADDDZrmb) + .value("VPADDDZrmbk", LIEF::assembly::x86::OPCODE::VPADDDZrmbk) + .value("VPADDDZrmbkz", LIEF::assembly::x86::OPCODE::VPADDDZrmbkz) + .value("VPADDDZrmk", LIEF::assembly::x86::OPCODE::VPADDDZrmk) + .value("VPADDDZrmkz", LIEF::assembly::x86::OPCODE::VPADDDZrmkz) + .value("VPADDDZrr", LIEF::assembly::x86::OPCODE::VPADDDZrr) + .value("VPADDDZrrk", LIEF::assembly::x86::OPCODE::VPADDDZrrk) + .value("VPADDDZrrkz", LIEF::assembly::x86::OPCODE::VPADDDZrrkz) + .value("VPADDDrm", LIEF::assembly::x86::OPCODE::VPADDDrm) + .value("VPADDDrr", LIEF::assembly::x86::OPCODE::VPADDDrr) + .value("VPADDQYrm", LIEF::assembly::x86::OPCODE::VPADDQYrm) + .value("VPADDQYrr", LIEF::assembly::x86::OPCODE::VPADDQYrr) + .value("VPADDQZ128rm", LIEF::assembly::x86::OPCODE::VPADDQZ128rm) + .value("VPADDQZ128rmb", LIEF::assembly::x86::OPCODE::VPADDQZ128rmb) + .value("VPADDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPADDQZ128rmbk) + .value("VPADDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPADDQZ128rmbkz) + .value("VPADDQZ128rmk", LIEF::assembly::x86::OPCODE::VPADDQZ128rmk) + .value("VPADDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDQZ128rmkz) + .value("VPADDQZ128rr", LIEF::assembly::x86::OPCODE::VPADDQZ128rr) + .value("VPADDQZ128rrk", LIEF::assembly::x86::OPCODE::VPADDQZ128rrk) + .value("VPADDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDQZ128rrkz) + .value("VPADDQZ256rm", LIEF::assembly::x86::OPCODE::VPADDQZ256rm) + .value("VPADDQZ256rmb", LIEF::assembly::x86::OPCODE::VPADDQZ256rmb) + .value("VPADDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPADDQZ256rmbk) + .value("VPADDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPADDQZ256rmbkz) + .value("VPADDQZ256rmk", LIEF::assembly::x86::OPCODE::VPADDQZ256rmk) + .value("VPADDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDQZ256rmkz) + .value("VPADDQZ256rr", LIEF::assembly::x86::OPCODE::VPADDQZ256rr) + .value("VPADDQZ256rrk", LIEF::assembly::x86::OPCODE::VPADDQZ256rrk) + .value("VPADDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDQZ256rrkz) + .value("VPADDQZrm", LIEF::assembly::x86::OPCODE::VPADDQZrm) + .value("VPADDQZrmb", LIEF::assembly::x86::OPCODE::VPADDQZrmb) + .value("VPADDQZrmbk", LIEF::assembly::x86::OPCODE::VPADDQZrmbk) + .value("VPADDQZrmbkz", LIEF::assembly::x86::OPCODE::VPADDQZrmbkz) + .value("VPADDQZrmk", LIEF::assembly::x86::OPCODE::VPADDQZrmk) + .value("VPADDQZrmkz", LIEF::assembly::x86::OPCODE::VPADDQZrmkz) + .value("VPADDQZrr", LIEF::assembly::x86::OPCODE::VPADDQZrr) + .value("VPADDQZrrk", LIEF::assembly::x86::OPCODE::VPADDQZrrk) + .value("VPADDQZrrkz", LIEF::assembly::x86::OPCODE::VPADDQZrrkz) + .value("VPADDQrm", LIEF::assembly::x86::OPCODE::VPADDQrm) + .value("VPADDQrr", LIEF::assembly::x86::OPCODE::VPADDQrr) + .value("VPADDSBYrm", LIEF::assembly::x86::OPCODE::VPADDSBYrm) + .value("VPADDSBYrr", LIEF::assembly::x86::OPCODE::VPADDSBYrr) + .value("VPADDSBZ128rm", LIEF::assembly::x86::OPCODE::VPADDSBZ128rm) + .value("VPADDSBZ128rmk", LIEF::assembly::x86::OPCODE::VPADDSBZ128rmk) + .value("VPADDSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDSBZ128rmkz) + .value("VPADDSBZ128rr", LIEF::assembly::x86::OPCODE::VPADDSBZ128rr) + .value("VPADDSBZ128rrk", LIEF::assembly::x86::OPCODE::VPADDSBZ128rrk) + .value("VPADDSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDSBZ128rrkz) + .value("VPADDSBZ256rm", LIEF::assembly::x86::OPCODE::VPADDSBZ256rm) + .value("VPADDSBZ256rmk", LIEF::assembly::x86::OPCODE::VPADDSBZ256rmk) + .value("VPADDSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDSBZ256rmkz) + .value("VPADDSBZ256rr", LIEF::assembly::x86::OPCODE::VPADDSBZ256rr) + .value("VPADDSBZ256rrk", LIEF::assembly::x86::OPCODE::VPADDSBZ256rrk) + .value("VPADDSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDSBZ256rrkz) + .value("VPADDSBZrm", LIEF::assembly::x86::OPCODE::VPADDSBZrm) + .value("VPADDSBZrmk", LIEF::assembly::x86::OPCODE::VPADDSBZrmk) + .value("VPADDSBZrmkz", LIEF::assembly::x86::OPCODE::VPADDSBZrmkz) + .value("VPADDSBZrr", LIEF::assembly::x86::OPCODE::VPADDSBZrr) + .value("VPADDSBZrrk", LIEF::assembly::x86::OPCODE::VPADDSBZrrk) + .value("VPADDSBZrrkz", LIEF::assembly::x86::OPCODE::VPADDSBZrrkz) + .value("VPADDSBrm", LIEF::assembly::x86::OPCODE::VPADDSBrm) + .value("VPADDSBrr", LIEF::assembly::x86::OPCODE::VPADDSBrr) + .value("VPADDSWYrm", LIEF::assembly::x86::OPCODE::VPADDSWYrm) + .value("VPADDSWYrr", LIEF::assembly::x86::OPCODE::VPADDSWYrr) + .value("VPADDSWZ128rm", LIEF::assembly::x86::OPCODE::VPADDSWZ128rm) + .value("VPADDSWZ128rmk", LIEF::assembly::x86::OPCODE::VPADDSWZ128rmk) + .value("VPADDSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDSWZ128rmkz) + .value("VPADDSWZ128rr", LIEF::assembly::x86::OPCODE::VPADDSWZ128rr) + .value("VPADDSWZ128rrk", LIEF::assembly::x86::OPCODE::VPADDSWZ128rrk) + .value("VPADDSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDSWZ128rrkz) + .value("VPADDSWZ256rm", LIEF::assembly::x86::OPCODE::VPADDSWZ256rm) + .value("VPADDSWZ256rmk", LIEF::assembly::x86::OPCODE::VPADDSWZ256rmk) + .value("VPADDSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDSWZ256rmkz) + .value("VPADDSWZ256rr", LIEF::assembly::x86::OPCODE::VPADDSWZ256rr) + .value("VPADDSWZ256rrk", LIEF::assembly::x86::OPCODE::VPADDSWZ256rrk) + .value("VPADDSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDSWZ256rrkz) + .value("VPADDSWZrm", LIEF::assembly::x86::OPCODE::VPADDSWZrm) + .value("VPADDSWZrmk", LIEF::assembly::x86::OPCODE::VPADDSWZrmk) + .value("VPADDSWZrmkz", LIEF::assembly::x86::OPCODE::VPADDSWZrmkz) + .value("VPADDSWZrr", LIEF::assembly::x86::OPCODE::VPADDSWZrr) + .value("VPADDSWZrrk", LIEF::assembly::x86::OPCODE::VPADDSWZrrk) + .value("VPADDSWZrrkz", LIEF::assembly::x86::OPCODE::VPADDSWZrrkz) + .value("VPADDSWrm", LIEF::assembly::x86::OPCODE::VPADDSWrm) + .value("VPADDSWrr", LIEF::assembly::x86::OPCODE::VPADDSWrr) + .value("VPADDUSBYrm", LIEF::assembly::x86::OPCODE::VPADDUSBYrm) + .value("VPADDUSBYrr", LIEF::assembly::x86::OPCODE::VPADDUSBYrr) + .value("VPADDUSBZ128rm", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rm) + .value("VPADDUSBZ128rmk", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rmk) + .value("VPADDUSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rmkz) + .value("VPADDUSBZ128rr", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rr) + .value("VPADDUSBZ128rrk", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rrk) + .value("VPADDUSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDUSBZ128rrkz) + .value("VPADDUSBZ256rm", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rm) + .value("VPADDUSBZ256rmk", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rmk) + .value("VPADDUSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rmkz) + .value("VPADDUSBZ256rr", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rr) + .value("VPADDUSBZ256rrk", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rrk) + .value("VPADDUSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDUSBZ256rrkz) + .value("VPADDUSBZrm", LIEF::assembly::x86::OPCODE::VPADDUSBZrm) + .value("VPADDUSBZrmk", LIEF::assembly::x86::OPCODE::VPADDUSBZrmk) + .value("VPADDUSBZrmkz", LIEF::assembly::x86::OPCODE::VPADDUSBZrmkz) + .value("VPADDUSBZrr", LIEF::assembly::x86::OPCODE::VPADDUSBZrr); + opcodes.value("VPADDUSBZrrk", LIEF::assembly::x86::OPCODE::VPADDUSBZrrk) + .value("VPADDUSBZrrkz", LIEF::assembly::x86::OPCODE::VPADDUSBZrrkz) + .value("VPADDUSBrm", LIEF::assembly::x86::OPCODE::VPADDUSBrm) + .value("VPADDUSBrr", LIEF::assembly::x86::OPCODE::VPADDUSBrr) + .value("VPADDUSWYrm", LIEF::assembly::x86::OPCODE::VPADDUSWYrm) + .value("VPADDUSWYrr", LIEF::assembly::x86::OPCODE::VPADDUSWYrr) + .value("VPADDUSWZ128rm", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rm) + .value("VPADDUSWZ128rmk", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rmk) + .value("VPADDUSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rmkz) + .value("VPADDUSWZ128rr", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rr) + .value("VPADDUSWZ128rrk", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rrk) + .value("VPADDUSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDUSWZ128rrkz) + .value("VPADDUSWZ256rm", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rm) + .value("VPADDUSWZ256rmk", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rmk) + .value("VPADDUSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rmkz) + .value("VPADDUSWZ256rr", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rr) + .value("VPADDUSWZ256rrk", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rrk) + .value("VPADDUSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDUSWZ256rrkz) + .value("VPADDUSWZrm", LIEF::assembly::x86::OPCODE::VPADDUSWZrm) + .value("VPADDUSWZrmk", LIEF::assembly::x86::OPCODE::VPADDUSWZrmk) + .value("VPADDUSWZrmkz", LIEF::assembly::x86::OPCODE::VPADDUSWZrmkz) + .value("VPADDUSWZrr", LIEF::assembly::x86::OPCODE::VPADDUSWZrr) + .value("VPADDUSWZrrk", LIEF::assembly::x86::OPCODE::VPADDUSWZrrk) + .value("VPADDUSWZrrkz", LIEF::assembly::x86::OPCODE::VPADDUSWZrrkz) + .value("VPADDUSWrm", LIEF::assembly::x86::OPCODE::VPADDUSWrm) + .value("VPADDUSWrr", LIEF::assembly::x86::OPCODE::VPADDUSWrr) + .value("VPADDWYrm", LIEF::assembly::x86::OPCODE::VPADDWYrm) + .value("VPADDWYrr", LIEF::assembly::x86::OPCODE::VPADDWYrr) + .value("VPADDWZ128rm", LIEF::assembly::x86::OPCODE::VPADDWZ128rm) + .value("VPADDWZ128rmk", LIEF::assembly::x86::OPCODE::VPADDWZ128rmk) + .value("VPADDWZ128rmkz", LIEF::assembly::x86::OPCODE::VPADDWZ128rmkz) + .value("VPADDWZ128rr", LIEF::assembly::x86::OPCODE::VPADDWZ128rr) + .value("VPADDWZ128rrk", LIEF::assembly::x86::OPCODE::VPADDWZ128rrk) + .value("VPADDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPADDWZ128rrkz) + .value("VPADDWZ256rm", LIEF::assembly::x86::OPCODE::VPADDWZ256rm) + .value("VPADDWZ256rmk", LIEF::assembly::x86::OPCODE::VPADDWZ256rmk) + .value("VPADDWZ256rmkz", LIEF::assembly::x86::OPCODE::VPADDWZ256rmkz) + .value("VPADDWZ256rr", LIEF::assembly::x86::OPCODE::VPADDWZ256rr) + .value("VPADDWZ256rrk", LIEF::assembly::x86::OPCODE::VPADDWZ256rrk) + .value("VPADDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPADDWZ256rrkz) + .value("VPADDWZrm", LIEF::assembly::x86::OPCODE::VPADDWZrm) + .value("VPADDWZrmk", LIEF::assembly::x86::OPCODE::VPADDWZrmk) + .value("VPADDWZrmkz", LIEF::assembly::x86::OPCODE::VPADDWZrmkz) + .value("VPADDWZrr", LIEF::assembly::x86::OPCODE::VPADDWZrr) + .value("VPADDWZrrk", LIEF::assembly::x86::OPCODE::VPADDWZrrk) + .value("VPADDWZrrkz", LIEF::assembly::x86::OPCODE::VPADDWZrrkz) + .value("VPADDWrm", LIEF::assembly::x86::OPCODE::VPADDWrm) + .value("VPADDWrr", LIEF::assembly::x86::OPCODE::VPADDWrr) + .value("VPALIGNRYrmi", LIEF::assembly::x86::OPCODE::VPALIGNRYrmi) + .value("VPALIGNRYrri", LIEF::assembly::x86::OPCODE::VPALIGNRYrri) + .value("VPALIGNRZ128rmi", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rmi) + .value("VPALIGNRZ128rmik", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rmik) + .value("VPALIGNRZ128rmikz", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rmikz) + .value("VPALIGNRZ128rri", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rri) + .value("VPALIGNRZ128rrik", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rrik) + .value("VPALIGNRZ128rrikz", LIEF::assembly::x86::OPCODE::VPALIGNRZ128rrikz) + .value("VPALIGNRZ256rmi", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rmi) + .value("VPALIGNRZ256rmik", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rmik) + .value("VPALIGNRZ256rmikz", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rmikz) + .value("VPALIGNRZ256rri", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rri) + .value("VPALIGNRZ256rrik", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rrik) + .value("VPALIGNRZ256rrikz", LIEF::assembly::x86::OPCODE::VPALIGNRZ256rrikz) + .value("VPALIGNRZrmi", LIEF::assembly::x86::OPCODE::VPALIGNRZrmi) + .value("VPALIGNRZrmik", LIEF::assembly::x86::OPCODE::VPALIGNRZrmik) + .value("VPALIGNRZrmikz", LIEF::assembly::x86::OPCODE::VPALIGNRZrmikz) + .value("VPALIGNRZrri", LIEF::assembly::x86::OPCODE::VPALIGNRZrri) + .value("VPALIGNRZrrik", LIEF::assembly::x86::OPCODE::VPALIGNRZrrik) + .value("VPALIGNRZrrikz", LIEF::assembly::x86::OPCODE::VPALIGNRZrrikz) + .value("VPALIGNRrmi", LIEF::assembly::x86::OPCODE::VPALIGNRrmi) + .value("VPALIGNRrri", LIEF::assembly::x86::OPCODE::VPALIGNRrri) + .value("VPANDDZ128rm", LIEF::assembly::x86::OPCODE::VPANDDZ128rm) + .value("VPANDDZ128rmb", LIEF::assembly::x86::OPCODE::VPANDDZ128rmb) + .value("VPANDDZ128rmbk", LIEF::assembly::x86::OPCODE::VPANDDZ128rmbk) + .value("VPANDDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPANDDZ128rmbkz) + .value("VPANDDZ128rmk", LIEF::assembly::x86::OPCODE::VPANDDZ128rmk) + .value("VPANDDZ128rmkz", LIEF::assembly::x86::OPCODE::VPANDDZ128rmkz) + .value("VPANDDZ128rr", LIEF::assembly::x86::OPCODE::VPANDDZ128rr) + .value("VPANDDZ128rrk", LIEF::assembly::x86::OPCODE::VPANDDZ128rrk) + .value("VPANDDZ128rrkz", LIEF::assembly::x86::OPCODE::VPANDDZ128rrkz) + .value("VPANDDZ256rm", LIEF::assembly::x86::OPCODE::VPANDDZ256rm) + .value("VPANDDZ256rmb", LIEF::assembly::x86::OPCODE::VPANDDZ256rmb) + .value("VPANDDZ256rmbk", LIEF::assembly::x86::OPCODE::VPANDDZ256rmbk) + .value("VPANDDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPANDDZ256rmbkz) + .value("VPANDDZ256rmk", LIEF::assembly::x86::OPCODE::VPANDDZ256rmk) + .value("VPANDDZ256rmkz", LIEF::assembly::x86::OPCODE::VPANDDZ256rmkz) + .value("VPANDDZ256rr", LIEF::assembly::x86::OPCODE::VPANDDZ256rr) + .value("VPANDDZ256rrk", LIEF::assembly::x86::OPCODE::VPANDDZ256rrk) + .value("VPANDDZ256rrkz", LIEF::assembly::x86::OPCODE::VPANDDZ256rrkz) + .value("VPANDDZrm", LIEF::assembly::x86::OPCODE::VPANDDZrm) + .value("VPANDDZrmb", LIEF::assembly::x86::OPCODE::VPANDDZrmb) + .value("VPANDDZrmbk", LIEF::assembly::x86::OPCODE::VPANDDZrmbk) + .value("VPANDDZrmbkz", LIEF::assembly::x86::OPCODE::VPANDDZrmbkz) + .value("VPANDDZrmk", LIEF::assembly::x86::OPCODE::VPANDDZrmk) + .value("VPANDDZrmkz", LIEF::assembly::x86::OPCODE::VPANDDZrmkz) + .value("VPANDDZrr", LIEF::assembly::x86::OPCODE::VPANDDZrr) + .value("VPANDDZrrk", LIEF::assembly::x86::OPCODE::VPANDDZrrk) + .value("VPANDDZrrkz", LIEF::assembly::x86::OPCODE::VPANDDZrrkz) + .value("VPANDNDZ128rm", LIEF::assembly::x86::OPCODE::VPANDNDZ128rm) + .value("VPANDNDZ128rmb", LIEF::assembly::x86::OPCODE::VPANDNDZ128rmb) + .value("VPANDNDZ128rmbk", LIEF::assembly::x86::OPCODE::VPANDNDZ128rmbk) + .value("VPANDNDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPANDNDZ128rmbkz) + .value("VPANDNDZ128rmk", LIEF::assembly::x86::OPCODE::VPANDNDZ128rmk) + .value("VPANDNDZ128rmkz", LIEF::assembly::x86::OPCODE::VPANDNDZ128rmkz) + .value("VPANDNDZ128rr", LIEF::assembly::x86::OPCODE::VPANDNDZ128rr) + .value("VPANDNDZ128rrk", LIEF::assembly::x86::OPCODE::VPANDNDZ128rrk) + .value("VPANDNDZ128rrkz", LIEF::assembly::x86::OPCODE::VPANDNDZ128rrkz) + .value("VPANDNDZ256rm", LIEF::assembly::x86::OPCODE::VPANDNDZ256rm) + .value("VPANDNDZ256rmb", LIEF::assembly::x86::OPCODE::VPANDNDZ256rmb) + .value("VPANDNDZ256rmbk", LIEF::assembly::x86::OPCODE::VPANDNDZ256rmbk) + .value("VPANDNDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPANDNDZ256rmbkz) + .value("VPANDNDZ256rmk", LIEF::assembly::x86::OPCODE::VPANDNDZ256rmk) + .value("VPANDNDZ256rmkz", LIEF::assembly::x86::OPCODE::VPANDNDZ256rmkz) + .value("VPANDNDZ256rr", LIEF::assembly::x86::OPCODE::VPANDNDZ256rr) + .value("VPANDNDZ256rrk", LIEF::assembly::x86::OPCODE::VPANDNDZ256rrk) + .value("VPANDNDZ256rrkz", LIEF::assembly::x86::OPCODE::VPANDNDZ256rrkz) + .value("VPANDNDZrm", LIEF::assembly::x86::OPCODE::VPANDNDZrm) + .value("VPANDNDZrmb", LIEF::assembly::x86::OPCODE::VPANDNDZrmb) + .value("VPANDNDZrmbk", LIEF::assembly::x86::OPCODE::VPANDNDZrmbk) + .value("VPANDNDZrmbkz", LIEF::assembly::x86::OPCODE::VPANDNDZrmbkz) + .value("VPANDNDZrmk", LIEF::assembly::x86::OPCODE::VPANDNDZrmk) + .value("VPANDNDZrmkz", LIEF::assembly::x86::OPCODE::VPANDNDZrmkz) + .value("VPANDNDZrr", LIEF::assembly::x86::OPCODE::VPANDNDZrr) + .value("VPANDNDZrrk", LIEF::assembly::x86::OPCODE::VPANDNDZrrk) + .value("VPANDNDZrrkz", LIEF::assembly::x86::OPCODE::VPANDNDZrrkz) + .value("VPANDNQZ128rm", LIEF::assembly::x86::OPCODE::VPANDNQZ128rm) + .value("VPANDNQZ128rmb", LIEF::assembly::x86::OPCODE::VPANDNQZ128rmb) + .value("VPANDNQZ128rmbk", LIEF::assembly::x86::OPCODE::VPANDNQZ128rmbk) + .value("VPANDNQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPANDNQZ128rmbkz) + .value("VPANDNQZ128rmk", LIEF::assembly::x86::OPCODE::VPANDNQZ128rmk) + .value("VPANDNQZ128rmkz", LIEF::assembly::x86::OPCODE::VPANDNQZ128rmkz) + .value("VPANDNQZ128rr", LIEF::assembly::x86::OPCODE::VPANDNQZ128rr) + .value("VPANDNQZ128rrk", LIEF::assembly::x86::OPCODE::VPANDNQZ128rrk) + .value("VPANDNQZ128rrkz", LIEF::assembly::x86::OPCODE::VPANDNQZ128rrkz) + .value("VPANDNQZ256rm", LIEF::assembly::x86::OPCODE::VPANDNQZ256rm) + .value("VPANDNQZ256rmb", LIEF::assembly::x86::OPCODE::VPANDNQZ256rmb) + .value("VPANDNQZ256rmbk", LIEF::assembly::x86::OPCODE::VPANDNQZ256rmbk) + .value("VPANDNQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPANDNQZ256rmbkz) + .value("VPANDNQZ256rmk", LIEF::assembly::x86::OPCODE::VPANDNQZ256rmk) + .value("VPANDNQZ256rmkz", LIEF::assembly::x86::OPCODE::VPANDNQZ256rmkz) + .value("VPANDNQZ256rr", LIEF::assembly::x86::OPCODE::VPANDNQZ256rr) + .value("VPANDNQZ256rrk", LIEF::assembly::x86::OPCODE::VPANDNQZ256rrk) + .value("VPANDNQZ256rrkz", LIEF::assembly::x86::OPCODE::VPANDNQZ256rrkz) + .value("VPANDNQZrm", LIEF::assembly::x86::OPCODE::VPANDNQZrm) + .value("VPANDNQZrmb", LIEF::assembly::x86::OPCODE::VPANDNQZrmb) + .value("VPANDNQZrmbk", LIEF::assembly::x86::OPCODE::VPANDNQZrmbk) + .value("VPANDNQZrmbkz", LIEF::assembly::x86::OPCODE::VPANDNQZrmbkz) + .value("VPANDNQZrmk", LIEF::assembly::x86::OPCODE::VPANDNQZrmk) + .value("VPANDNQZrmkz", LIEF::assembly::x86::OPCODE::VPANDNQZrmkz) + .value("VPANDNQZrr", LIEF::assembly::x86::OPCODE::VPANDNQZrr) + .value("VPANDNQZrrk", LIEF::assembly::x86::OPCODE::VPANDNQZrrk) + .value("VPANDNQZrrkz", LIEF::assembly::x86::OPCODE::VPANDNQZrrkz) + .value("VPANDNYrm", LIEF::assembly::x86::OPCODE::VPANDNYrm) + .value("VPANDNYrr", LIEF::assembly::x86::OPCODE::VPANDNYrr) + .value("VPANDNrm", LIEF::assembly::x86::OPCODE::VPANDNrm) + .value("VPANDNrr", LIEF::assembly::x86::OPCODE::VPANDNrr) + .value("VPANDQZ128rm", LIEF::assembly::x86::OPCODE::VPANDQZ128rm) + .value("VPANDQZ128rmb", LIEF::assembly::x86::OPCODE::VPANDQZ128rmb) + .value("VPANDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPANDQZ128rmbk) + .value("VPANDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPANDQZ128rmbkz) + .value("VPANDQZ128rmk", LIEF::assembly::x86::OPCODE::VPANDQZ128rmk) + .value("VPANDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPANDQZ128rmkz) + .value("VPANDQZ128rr", LIEF::assembly::x86::OPCODE::VPANDQZ128rr) + .value("VPANDQZ128rrk", LIEF::assembly::x86::OPCODE::VPANDQZ128rrk) + .value("VPANDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPANDQZ128rrkz) + .value("VPANDQZ256rm", LIEF::assembly::x86::OPCODE::VPANDQZ256rm) + .value("VPANDQZ256rmb", LIEF::assembly::x86::OPCODE::VPANDQZ256rmb) + .value("VPANDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPANDQZ256rmbk) + .value("VPANDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPANDQZ256rmbkz) + .value("VPANDQZ256rmk", LIEF::assembly::x86::OPCODE::VPANDQZ256rmk) + .value("VPANDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPANDQZ256rmkz) + .value("VPANDQZ256rr", LIEF::assembly::x86::OPCODE::VPANDQZ256rr) + .value("VPANDQZ256rrk", LIEF::assembly::x86::OPCODE::VPANDQZ256rrk) + .value("VPANDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPANDQZ256rrkz) + .value("VPANDQZrm", LIEF::assembly::x86::OPCODE::VPANDQZrm) + .value("VPANDQZrmb", LIEF::assembly::x86::OPCODE::VPANDQZrmb) + .value("VPANDQZrmbk", LIEF::assembly::x86::OPCODE::VPANDQZrmbk) + .value("VPANDQZrmbkz", LIEF::assembly::x86::OPCODE::VPANDQZrmbkz) + .value("VPANDQZrmk", LIEF::assembly::x86::OPCODE::VPANDQZrmk) + .value("VPANDQZrmkz", LIEF::assembly::x86::OPCODE::VPANDQZrmkz) + .value("VPANDQZrr", LIEF::assembly::x86::OPCODE::VPANDQZrr) + .value("VPANDQZrrk", LIEF::assembly::x86::OPCODE::VPANDQZrrk) + .value("VPANDQZrrkz", LIEF::assembly::x86::OPCODE::VPANDQZrrkz) + .value("VPANDYrm", LIEF::assembly::x86::OPCODE::VPANDYrm) + .value("VPANDYrr", LIEF::assembly::x86::OPCODE::VPANDYrr) + .value("VPANDrm", LIEF::assembly::x86::OPCODE::VPANDrm) + .value("VPANDrr", LIEF::assembly::x86::OPCODE::VPANDrr) + .value("VPAVGBYrm", LIEF::assembly::x86::OPCODE::VPAVGBYrm) + .value("VPAVGBYrr", LIEF::assembly::x86::OPCODE::VPAVGBYrr) + .value("VPAVGBZ128rm", LIEF::assembly::x86::OPCODE::VPAVGBZ128rm) + .value("VPAVGBZ128rmk", LIEF::assembly::x86::OPCODE::VPAVGBZ128rmk) + .value("VPAVGBZ128rmkz", LIEF::assembly::x86::OPCODE::VPAVGBZ128rmkz) + .value("VPAVGBZ128rr", LIEF::assembly::x86::OPCODE::VPAVGBZ128rr) + .value("VPAVGBZ128rrk", LIEF::assembly::x86::OPCODE::VPAVGBZ128rrk) + .value("VPAVGBZ128rrkz", LIEF::assembly::x86::OPCODE::VPAVGBZ128rrkz) + .value("VPAVGBZ256rm", LIEF::assembly::x86::OPCODE::VPAVGBZ256rm) + .value("VPAVGBZ256rmk", LIEF::assembly::x86::OPCODE::VPAVGBZ256rmk) + .value("VPAVGBZ256rmkz", LIEF::assembly::x86::OPCODE::VPAVGBZ256rmkz) + .value("VPAVGBZ256rr", LIEF::assembly::x86::OPCODE::VPAVGBZ256rr) + .value("VPAVGBZ256rrk", LIEF::assembly::x86::OPCODE::VPAVGBZ256rrk) + .value("VPAVGBZ256rrkz", LIEF::assembly::x86::OPCODE::VPAVGBZ256rrkz) + .value("VPAVGBZrm", LIEF::assembly::x86::OPCODE::VPAVGBZrm) + .value("VPAVGBZrmk", LIEF::assembly::x86::OPCODE::VPAVGBZrmk) + .value("VPAVGBZrmkz", LIEF::assembly::x86::OPCODE::VPAVGBZrmkz) + .value("VPAVGBZrr", LIEF::assembly::x86::OPCODE::VPAVGBZrr) + .value("VPAVGBZrrk", LIEF::assembly::x86::OPCODE::VPAVGBZrrk) + .value("VPAVGBZrrkz", LIEF::assembly::x86::OPCODE::VPAVGBZrrkz) + .value("VPAVGBrm", LIEF::assembly::x86::OPCODE::VPAVGBrm) + .value("VPAVGBrr", LIEF::assembly::x86::OPCODE::VPAVGBrr) + .value("VPAVGWYrm", LIEF::assembly::x86::OPCODE::VPAVGWYrm) + .value("VPAVGWYrr", LIEF::assembly::x86::OPCODE::VPAVGWYrr) + .value("VPAVGWZ128rm", LIEF::assembly::x86::OPCODE::VPAVGWZ128rm) + .value("VPAVGWZ128rmk", LIEF::assembly::x86::OPCODE::VPAVGWZ128rmk) + .value("VPAVGWZ128rmkz", LIEF::assembly::x86::OPCODE::VPAVGWZ128rmkz) + .value("VPAVGWZ128rr", LIEF::assembly::x86::OPCODE::VPAVGWZ128rr) + .value("VPAVGWZ128rrk", LIEF::assembly::x86::OPCODE::VPAVGWZ128rrk) + .value("VPAVGWZ128rrkz", LIEF::assembly::x86::OPCODE::VPAVGWZ128rrkz) + .value("VPAVGWZ256rm", LIEF::assembly::x86::OPCODE::VPAVGWZ256rm) + .value("VPAVGWZ256rmk", LIEF::assembly::x86::OPCODE::VPAVGWZ256rmk) + .value("VPAVGWZ256rmkz", LIEF::assembly::x86::OPCODE::VPAVGWZ256rmkz) + .value("VPAVGWZ256rr", LIEF::assembly::x86::OPCODE::VPAVGWZ256rr) + .value("VPAVGWZ256rrk", LIEF::assembly::x86::OPCODE::VPAVGWZ256rrk) + .value("VPAVGWZ256rrkz", LIEF::assembly::x86::OPCODE::VPAVGWZ256rrkz) + .value("VPAVGWZrm", LIEF::assembly::x86::OPCODE::VPAVGWZrm) + .value("VPAVGWZrmk", LIEF::assembly::x86::OPCODE::VPAVGWZrmk) + .value("VPAVGWZrmkz", LIEF::assembly::x86::OPCODE::VPAVGWZrmkz) + .value("VPAVGWZrr", LIEF::assembly::x86::OPCODE::VPAVGWZrr) + .value("VPAVGWZrrk", LIEF::assembly::x86::OPCODE::VPAVGWZrrk) + .value("VPAVGWZrrkz", LIEF::assembly::x86::OPCODE::VPAVGWZrrkz) + .value("VPAVGWrm", LIEF::assembly::x86::OPCODE::VPAVGWrm) + .value("VPAVGWrr", LIEF::assembly::x86::OPCODE::VPAVGWrr) + .value("VPBLENDDYrmi", LIEF::assembly::x86::OPCODE::VPBLENDDYrmi) + .value("VPBLENDDYrri", LIEF::assembly::x86::OPCODE::VPBLENDDYrri) + .value("VPBLENDDrmi", LIEF::assembly::x86::OPCODE::VPBLENDDrmi) + .value("VPBLENDDrri", LIEF::assembly::x86::OPCODE::VPBLENDDrri) + .value("VPBLENDMBZ128rm", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rm) + .value("VPBLENDMBZ128rmk", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rmk) + .value("VPBLENDMBZ128rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rmkz) + .value("VPBLENDMBZ128rr", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rr) + .value("VPBLENDMBZ128rrk", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rrk) + .value("VPBLENDMBZ128rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZ128rrkz) + .value("VPBLENDMBZ256rm", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rm) + .value("VPBLENDMBZ256rmk", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rmk) + .value("VPBLENDMBZ256rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rmkz) + .value("VPBLENDMBZ256rr", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rr) + .value("VPBLENDMBZ256rrk", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rrk) + .value("VPBLENDMBZ256rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZ256rrkz) + .value("VPBLENDMBZrm", LIEF::assembly::x86::OPCODE::VPBLENDMBZrm) + .value("VPBLENDMBZrmk", LIEF::assembly::x86::OPCODE::VPBLENDMBZrmk) + .value("VPBLENDMBZrmkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZrmkz) + .value("VPBLENDMBZrr", LIEF::assembly::x86::OPCODE::VPBLENDMBZrr) + .value("VPBLENDMBZrrk", LIEF::assembly::x86::OPCODE::VPBLENDMBZrrk) + .value("VPBLENDMBZrrkz", LIEF::assembly::x86::OPCODE::VPBLENDMBZrrkz) + .value("VPBLENDMDZ128rm", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rm) + .value("VPBLENDMDZ128rmb", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rmb) + .value("VPBLENDMDZ128rmbk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rmbk) + .value("VPBLENDMDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rmbkz) + .value("VPBLENDMDZ128rmk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rmk) + .value("VPBLENDMDZ128rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rmkz) + .value("VPBLENDMDZ128rr", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rr) + .value("VPBLENDMDZ128rrk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rrk) + .value("VPBLENDMDZ128rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ128rrkz) + .value("VPBLENDMDZ256rm", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rm) + .value("VPBLENDMDZ256rmb", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rmb) + .value("VPBLENDMDZ256rmbk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rmbk) + .value("VPBLENDMDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rmbkz) + .value("VPBLENDMDZ256rmk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rmk) + .value("VPBLENDMDZ256rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rmkz) + .value("VPBLENDMDZ256rr", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rr) + .value("VPBLENDMDZ256rrk", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rrk) + .value("VPBLENDMDZ256rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZ256rrkz) + .value("VPBLENDMDZrm", LIEF::assembly::x86::OPCODE::VPBLENDMDZrm) + .value("VPBLENDMDZrmb", LIEF::assembly::x86::OPCODE::VPBLENDMDZrmb) + .value("VPBLENDMDZrmbk", LIEF::assembly::x86::OPCODE::VPBLENDMDZrmbk) + .value("VPBLENDMDZrmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZrmbkz) + .value("VPBLENDMDZrmk", LIEF::assembly::x86::OPCODE::VPBLENDMDZrmk) + .value("VPBLENDMDZrmkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZrmkz) + .value("VPBLENDMDZrr", LIEF::assembly::x86::OPCODE::VPBLENDMDZrr) + .value("VPBLENDMDZrrk", LIEF::assembly::x86::OPCODE::VPBLENDMDZrrk) + .value("VPBLENDMDZrrkz", LIEF::assembly::x86::OPCODE::VPBLENDMDZrrkz) + .value("VPBLENDMQZ128rm", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rm) + .value("VPBLENDMQZ128rmb", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rmb) + .value("VPBLENDMQZ128rmbk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rmbk) + .value("VPBLENDMQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rmbkz) + .value("VPBLENDMQZ128rmk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rmk) + .value("VPBLENDMQZ128rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rmkz) + .value("VPBLENDMQZ128rr", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rr) + .value("VPBLENDMQZ128rrk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rrk) + .value("VPBLENDMQZ128rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ128rrkz) + .value("VPBLENDMQZ256rm", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rm) + .value("VPBLENDMQZ256rmb", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rmb) + .value("VPBLENDMQZ256rmbk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rmbk) + .value("VPBLENDMQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rmbkz) + .value("VPBLENDMQZ256rmk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rmk) + .value("VPBLENDMQZ256rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rmkz) + .value("VPBLENDMQZ256rr", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rr) + .value("VPBLENDMQZ256rrk", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rrk) + .value("VPBLENDMQZ256rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZ256rrkz) + .value("VPBLENDMQZrm", LIEF::assembly::x86::OPCODE::VPBLENDMQZrm) + .value("VPBLENDMQZrmb", LIEF::assembly::x86::OPCODE::VPBLENDMQZrmb) + .value("VPBLENDMQZrmbk", LIEF::assembly::x86::OPCODE::VPBLENDMQZrmbk); + opcodes.value("VPBLENDMQZrmbkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZrmbkz) + .value("VPBLENDMQZrmk", LIEF::assembly::x86::OPCODE::VPBLENDMQZrmk) + .value("VPBLENDMQZrmkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZrmkz) + .value("VPBLENDMQZrr", LIEF::assembly::x86::OPCODE::VPBLENDMQZrr) + .value("VPBLENDMQZrrk", LIEF::assembly::x86::OPCODE::VPBLENDMQZrrk) + .value("VPBLENDMQZrrkz", LIEF::assembly::x86::OPCODE::VPBLENDMQZrrkz) + .value("VPBLENDMWZ128rm", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rm) + .value("VPBLENDMWZ128rmk", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rmk) + .value("VPBLENDMWZ128rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rmkz) + .value("VPBLENDMWZ128rr", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rr) + .value("VPBLENDMWZ128rrk", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rrk) + .value("VPBLENDMWZ128rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZ128rrkz) + .value("VPBLENDMWZ256rm", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rm) + .value("VPBLENDMWZ256rmk", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rmk) + .value("VPBLENDMWZ256rmkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rmkz) + .value("VPBLENDMWZ256rr", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rr) + .value("VPBLENDMWZ256rrk", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rrk) + .value("VPBLENDMWZ256rrkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZ256rrkz) + .value("VPBLENDMWZrm", LIEF::assembly::x86::OPCODE::VPBLENDMWZrm) + .value("VPBLENDMWZrmk", LIEF::assembly::x86::OPCODE::VPBLENDMWZrmk) + .value("VPBLENDMWZrmkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZrmkz) + .value("VPBLENDMWZrr", LIEF::assembly::x86::OPCODE::VPBLENDMWZrr) + .value("VPBLENDMWZrrk", LIEF::assembly::x86::OPCODE::VPBLENDMWZrrk) + .value("VPBLENDMWZrrkz", LIEF::assembly::x86::OPCODE::VPBLENDMWZrrkz) + .value("VPBLENDVBYrmr", LIEF::assembly::x86::OPCODE::VPBLENDVBYrmr) + .value("VPBLENDVBYrrr", LIEF::assembly::x86::OPCODE::VPBLENDVBYrrr) + .value("VPBLENDVBrmr", LIEF::assembly::x86::OPCODE::VPBLENDVBrmr) + .value("VPBLENDVBrrr", LIEF::assembly::x86::OPCODE::VPBLENDVBrrr) + .value("VPBLENDWYrmi", LIEF::assembly::x86::OPCODE::VPBLENDWYrmi) + .value("VPBLENDWYrri", LIEF::assembly::x86::OPCODE::VPBLENDWYrri) + .value("VPBLENDWrmi", LIEF::assembly::x86::OPCODE::VPBLENDWrmi) + .value("VPBLENDWrri", LIEF::assembly::x86::OPCODE::VPBLENDWrri) + .value("VPBROADCASTBYrm", LIEF::assembly::x86::OPCODE::VPBROADCASTBYrm) + .value("VPBROADCASTBYrr", LIEF::assembly::x86::OPCODE::VPBROADCASTBYrr) + .value("VPBROADCASTBZ128rm", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rm) + .value("VPBROADCASTBZ128rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rmk) + .value("VPBROADCASTBZ128rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rmkz) + .value("VPBROADCASTBZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rr) + .value("VPBROADCASTBZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rrk) + .value("VPBROADCASTBZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ128rrkz) + .value("VPBROADCASTBZ256rm", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rm) + .value("VPBROADCASTBZ256rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rmk) + .value("VPBROADCASTBZ256rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rmkz) + .value("VPBROADCASTBZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rr) + .value("VPBROADCASTBZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rrk) + .value("VPBROADCASTBZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZ256rrkz) + .value("VPBROADCASTBZrm", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrm) + .value("VPBROADCASTBZrmk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrmk) + .value("VPBROADCASTBZrmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrmkz) + .value("VPBROADCASTBZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrr) + .value("VPBROADCASTBZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrrk) + .value("VPBROADCASTBZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBZrrkz) + .value("VPBROADCASTBrZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ128rr) + .value("VPBROADCASTBrZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ128rrk) + .value("VPBROADCASTBrZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ128rrkz) + .value("VPBROADCASTBrZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ256rr) + .value("VPBROADCASTBrZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ256rrk) + .value("VPBROADCASTBrZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZ256rrkz) + .value("VPBROADCASTBrZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZrr) + .value("VPBROADCASTBrZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZrrk) + .value("VPBROADCASTBrZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTBrZrrkz) + .value("VPBROADCASTBrm", LIEF::assembly::x86::OPCODE::VPBROADCASTBrm) + .value("VPBROADCASTBrr", LIEF::assembly::x86::OPCODE::VPBROADCASTBrr) + .value("VPBROADCASTDYrm", LIEF::assembly::x86::OPCODE::VPBROADCASTDYrm) + .value("VPBROADCASTDYrr", LIEF::assembly::x86::OPCODE::VPBROADCASTDYrr) + .value("VPBROADCASTDZ128rm", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rm) + .value("VPBROADCASTDZ128rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rmk) + .value("VPBROADCASTDZ128rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rmkz) + .value("VPBROADCASTDZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rr) + .value("VPBROADCASTDZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rrk) + .value("VPBROADCASTDZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ128rrkz) + .value("VPBROADCASTDZ256rm", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rm) + .value("VPBROADCASTDZ256rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rmk) + .value("VPBROADCASTDZ256rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rmkz) + .value("VPBROADCASTDZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rr) + .value("VPBROADCASTDZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rrk) + .value("VPBROADCASTDZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZ256rrkz) + .value("VPBROADCASTDZrm", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrm) + .value("VPBROADCASTDZrmk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrmk) + .value("VPBROADCASTDZrmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrmkz) + .value("VPBROADCASTDZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrr) + .value("VPBROADCASTDZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrrk) + .value("VPBROADCASTDZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDZrrkz) + .value("VPBROADCASTDrZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ128rr) + .value("VPBROADCASTDrZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ128rrk) + .value("VPBROADCASTDrZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ128rrkz) + .value("VPBROADCASTDrZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ256rr) + .value("VPBROADCASTDrZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ256rrk) + .value("VPBROADCASTDrZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZ256rrkz) + .value("VPBROADCASTDrZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZrr) + .value("VPBROADCASTDrZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZrrk) + .value("VPBROADCASTDrZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTDrZrrkz) + .value("VPBROADCASTDrm", LIEF::assembly::x86::OPCODE::VPBROADCASTDrm) + .value("VPBROADCASTDrr", LIEF::assembly::x86::OPCODE::VPBROADCASTDrr) + .value("VPBROADCASTMB2QZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTMB2QZ128rr) + .value("VPBROADCASTMB2QZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTMB2QZ256rr) + .value("VPBROADCASTMB2QZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTMB2QZrr) + .value("VPBROADCASTMW2DZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTMW2DZ128rr) + .value("VPBROADCASTMW2DZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTMW2DZ256rr) + .value("VPBROADCASTMW2DZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTMW2DZrr) + .value("VPBROADCASTQYrm", LIEF::assembly::x86::OPCODE::VPBROADCASTQYrm) + .value("VPBROADCASTQYrr", LIEF::assembly::x86::OPCODE::VPBROADCASTQYrr) + .value("VPBROADCASTQZ128rm", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rm) + .value("VPBROADCASTQZ128rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rmk) + .value("VPBROADCASTQZ128rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rmkz) + .value("VPBROADCASTQZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rr) + .value("VPBROADCASTQZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rrk) + .value("VPBROADCASTQZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ128rrkz) + .value("VPBROADCASTQZ256rm", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rm) + .value("VPBROADCASTQZ256rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rmk) + .value("VPBROADCASTQZ256rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rmkz) + .value("VPBROADCASTQZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rr) + .value("VPBROADCASTQZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rrk) + .value("VPBROADCASTQZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZ256rrkz) + .value("VPBROADCASTQZrm", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrm) + .value("VPBROADCASTQZrmk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrmk) + .value("VPBROADCASTQZrmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrmkz) + .value("VPBROADCASTQZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrr) + .value("VPBROADCASTQZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrrk) + .value("VPBROADCASTQZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQZrrkz) + .value("VPBROADCASTQrZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ128rr) + .value("VPBROADCASTQrZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ128rrk) + .value("VPBROADCASTQrZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ128rrkz) + .value("VPBROADCASTQrZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ256rr) + .value("VPBROADCASTQrZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ256rrk) + .value("VPBROADCASTQrZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZ256rrkz) + .value("VPBROADCASTQrZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZrr) + .value("VPBROADCASTQrZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZrrk) + .value("VPBROADCASTQrZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTQrZrrkz) + .value("VPBROADCASTQrm", LIEF::assembly::x86::OPCODE::VPBROADCASTQrm) + .value("VPBROADCASTQrr", LIEF::assembly::x86::OPCODE::VPBROADCASTQrr) + .value("VPBROADCASTWYrm", LIEF::assembly::x86::OPCODE::VPBROADCASTWYrm) + .value("VPBROADCASTWYrr", LIEF::assembly::x86::OPCODE::VPBROADCASTWYrr) + .value("VPBROADCASTWZ128rm", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rm) + .value("VPBROADCASTWZ128rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rmk) + .value("VPBROADCASTWZ128rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rmkz) + .value("VPBROADCASTWZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rr) + .value("VPBROADCASTWZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rrk) + .value("VPBROADCASTWZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ128rrkz) + .value("VPBROADCASTWZ256rm", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rm) + .value("VPBROADCASTWZ256rmk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rmk) + .value("VPBROADCASTWZ256rmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rmkz) + .value("VPBROADCASTWZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rr) + .value("VPBROADCASTWZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rrk) + .value("VPBROADCASTWZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZ256rrkz) + .value("VPBROADCASTWZrm", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrm) + .value("VPBROADCASTWZrmk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrmk) + .value("VPBROADCASTWZrmkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrmkz) + .value("VPBROADCASTWZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrr) + .value("VPBROADCASTWZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrrk) + .value("VPBROADCASTWZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWZrrkz) + .value("VPBROADCASTWrZ128rr", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ128rr) + .value("VPBROADCASTWrZ128rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ128rrk) + .value("VPBROADCASTWrZ128rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ128rrkz) + .value("VPBROADCASTWrZ256rr", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ256rr) + .value("VPBROADCASTWrZ256rrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ256rrk) + .value("VPBROADCASTWrZ256rrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZ256rrkz) + .value("VPBROADCASTWrZrr", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZrr) + .value("VPBROADCASTWrZrrk", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZrrk) + .value("VPBROADCASTWrZrrkz", LIEF::assembly::x86::OPCODE::VPBROADCASTWrZrrkz) + .value("VPBROADCASTWrm", LIEF::assembly::x86::OPCODE::VPBROADCASTWrm) + .value("VPBROADCASTWrr", LIEF::assembly::x86::OPCODE::VPBROADCASTWrr) + .value("VPCLMULQDQYrmi", LIEF::assembly::x86::OPCODE::VPCLMULQDQYrmi) + .value("VPCLMULQDQYrri", LIEF::assembly::x86::OPCODE::VPCLMULQDQYrri) + .value("VPCLMULQDQZ128rmi", LIEF::assembly::x86::OPCODE::VPCLMULQDQZ128rmi) + .value("VPCLMULQDQZ128rri", LIEF::assembly::x86::OPCODE::VPCLMULQDQZ128rri) + .value("VPCLMULQDQZ256rmi", LIEF::assembly::x86::OPCODE::VPCLMULQDQZ256rmi) + .value("VPCLMULQDQZ256rri", LIEF::assembly::x86::OPCODE::VPCLMULQDQZ256rri) + .value("VPCLMULQDQZrmi", LIEF::assembly::x86::OPCODE::VPCLMULQDQZrmi) + .value("VPCLMULQDQZrri", LIEF::assembly::x86::OPCODE::VPCLMULQDQZrri) + .value("VPCLMULQDQrmi", LIEF::assembly::x86::OPCODE::VPCLMULQDQrmi) + .value("VPCLMULQDQrri", LIEF::assembly::x86::OPCODE::VPCLMULQDQrri) + .value("VPCMOVYrmr", LIEF::assembly::x86::OPCODE::VPCMOVYrmr) + .value("VPCMOVYrrm", LIEF::assembly::x86::OPCODE::VPCMOVYrrm) + .value("VPCMOVYrrr", LIEF::assembly::x86::OPCODE::VPCMOVYrrr) + .value("VPCMOVYrrr_REV", LIEF::assembly::x86::OPCODE::VPCMOVYrrr_REV) + .value("VPCMOVrmr", LIEF::assembly::x86::OPCODE::VPCMOVrmr) + .value("VPCMOVrrm", LIEF::assembly::x86::OPCODE::VPCMOVrrm) + .value("VPCMOVrrr", LIEF::assembly::x86::OPCODE::VPCMOVrrr) + .value("VPCMOVrrr_REV", LIEF::assembly::x86::OPCODE::VPCMOVrrr_REV) + .value("VPCMPBZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPBZ128rmi) + .value("VPCMPBZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPBZ128rmik) + .value("VPCMPBZ128rri", LIEF::assembly::x86::OPCODE::VPCMPBZ128rri) + .value("VPCMPBZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPBZ128rrik) + .value("VPCMPBZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPBZ256rmi) + .value("VPCMPBZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPBZ256rmik) + .value("VPCMPBZ256rri", LIEF::assembly::x86::OPCODE::VPCMPBZ256rri) + .value("VPCMPBZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPBZ256rrik) + .value("VPCMPBZrmi", LIEF::assembly::x86::OPCODE::VPCMPBZrmi) + .value("VPCMPBZrmik", LIEF::assembly::x86::OPCODE::VPCMPBZrmik) + .value("VPCMPBZrri", LIEF::assembly::x86::OPCODE::VPCMPBZrri) + .value("VPCMPBZrrik", LIEF::assembly::x86::OPCODE::VPCMPBZrrik) + .value("VPCMPDZ128rmbi", LIEF::assembly::x86::OPCODE::VPCMPDZ128rmbi) + .value("VPCMPDZ128rmbik", LIEF::assembly::x86::OPCODE::VPCMPDZ128rmbik) + .value("VPCMPDZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPDZ128rmi) + .value("VPCMPDZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPDZ128rmik) + .value("VPCMPDZ128rri", LIEF::assembly::x86::OPCODE::VPCMPDZ128rri) + .value("VPCMPDZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPDZ128rrik) + .value("VPCMPDZ256rmbi", LIEF::assembly::x86::OPCODE::VPCMPDZ256rmbi) + .value("VPCMPDZ256rmbik", LIEF::assembly::x86::OPCODE::VPCMPDZ256rmbik) + .value("VPCMPDZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPDZ256rmi) + .value("VPCMPDZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPDZ256rmik) + .value("VPCMPDZ256rri", LIEF::assembly::x86::OPCODE::VPCMPDZ256rri) + .value("VPCMPDZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPDZ256rrik) + .value("VPCMPDZrmbi", LIEF::assembly::x86::OPCODE::VPCMPDZrmbi) + .value("VPCMPDZrmbik", LIEF::assembly::x86::OPCODE::VPCMPDZrmbik) + .value("VPCMPDZrmi", LIEF::assembly::x86::OPCODE::VPCMPDZrmi) + .value("VPCMPDZrmik", LIEF::assembly::x86::OPCODE::VPCMPDZrmik) + .value("VPCMPDZrri", LIEF::assembly::x86::OPCODE::VPCMPDZrri) + .value("VPCMPDZrrik", LIEF::assembly::x86::OPCODE::VPCMPDZrrik) + .value("VPCMPEQBYrm", LIEF::assembly::x86::OPCODE::VPCMPEQBYrm) + .value("VPCMPEQBYrr", LIEF::assembly::x86::OPCODE::VPCMPEQBYrr) + .value("VPCMPEQBZ128rm", LIEF::assembly::x86::OPCODE::VPCMPEQBZ128rm) + .value("VPCMPEQBZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPEQBZ128rmk) + .value("VPCMPEQBZ128rr", LIEF::assembly::x86::OPCODE::VPCMPEQBZ128rr) + .value("VPCMPEQBZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPEQBZ128rrk) + .value("VPCMPEQBZ256rm", LIEF::assembly::x86::OPCODE::VPCMPEQBZ256rm) + .value("VPCMPEQBZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPEQBZ256rmk) + .value("VPCMPEQBZ256rr", LIEF::assembly::x86::OPCODE::VPCMPEQBZ256rr) + .value("VPCMPEQBZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPEQBZ256rrk) + .value("VPCMPEQBZrm", LIEF::assembly::x86::OPCODE::VPCMPEQBZrm) + .value("VPCMPEQBZrmk", LIEF::assembly::x86::OPCODE::VPCMPEQBZrmk) + .value("VPCMPEQBZrr", LIEF::assembly::x86::OPCODE::VPCMPEQBZrr) + .value("VPCMPEQBZrrk", LIEF::assembly::x86::OPCODE::VPCMPEQBZrrk) + .value("VPCMPEQBrm", LIEF::assembly::x86::OPCODE::VPCMPEQBrm) + .value("VPCMPEQBrr", LIEF::assembly::x86::OPCODE::VPCMPEQBrr) + .value("VPCMPEQDYrm", LIEF::assembly::x86::OPCODE::VPCMPEQDYrm) + .value("VPCMPEQDYrr", LIEF::assembly::x86::OPCODE::VPCMPEQDYrr) + .value("VPCMPEQDZ128rm", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rm) + .value("VPCMPEQDZ128rmb", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rmb) + .value("VPCMPEQDZ128rmbk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rmbk) + .value("VPCMPEQDZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rmk) + .value("VPCMPEQDZ128rr", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rr) + .value("VPCMPEQDZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ128rrk) + .value("VPCMPEQDZ256rm", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rm) + .value("VPCMPEQDZ256rmb", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rmb) + .value("VPCMPEQDZ256rmbk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rmbk) + .value("VPCMPEQDZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rmk) + .value("VPCMPEQDZ256rr", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rr) + .value("VPCMPEQDZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPEQDZ256rrk) + .value("VPCMPEQDZrm", LIEF::assembly::x86::OPCODE::VPCMPEQDZrm) + .value("VPCMPEQDZrmb", LIEF::assembly::x86::OPCODE::VPCMPEQDZrmb) + .value("VPCMPEQDZrmbk", LIEF::assembly::x86::OPCODE::VPCMPEQDZrmbk) + .value("VPCMPEQDZrmk", LIEF::assembly::x86::OPCODE::VPCMPEQDZrmk) + .value("VPCMPEQDZrr", LIEF::assembly::x86::OPCODE::VPCMPEQDZrr) + .value("VPCMPEQDZrrk", LIEF::assembly::x86::OPCODE::VPCMPEQDZrrk) + .value("VPCMPEQDrm", LIEF::assembly::x86::OPCODE::VPCMPEQDrm) + .value("VPCMPEQDrr", LIEF::assembly::x86::OPCODE::VPCMPEQDrr) + .value("VPCMPEQQYrm", LIEF::assembly::x86::OPCODE::VPCMPEQQYrm) + .value("VPCMPEQQYrr", LIEF::assembly::x86::OPCODE::VPCMPEQQYrr) + .value("VPCMPEQQZ128rm", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rm) + .value("VPCMPEQQZ128rmb", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rmb) + .value("VPCMPEQQZ128rmbk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rmbk) + .value("VPCMPEQQZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rmk) + .value("VPCMPEQQZ128rr", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rr) + .value("VPCMPEQQZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ128rrk) + .value("VPCMPEQQZ256rm", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rm) + .value("VPCMPEQQZ256rmb", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rmb) + .value("VPCMPEQQZ256rmbk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rmbk) + .value("VPCMPEQQZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rmk) + .value("VPCMPEQQZ256rr", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rr) + .value("VPCMPEQQZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPEQQZ256rrk) + .value("VPCMPEQQZrm", LIEF::assembly::x86::OPCODE::VPCMPEQQZrm) + .value("VPCMPEQQZrmb", LIEF::assembly::x86::OPCODE::VPCMPEQQZrmb) + .value("VPCMPEQQZrmbk", LIEF::assembly::x86::OPCODE::VPCMPEQQZrmbk) + .value("VPCMPEQQZrmk", LIEF::assembly::x86::OPCODE::VPCMPEQQZrmk) + .value("VPCMPEQQZrr", LIEF::assembly::x86::OPCODE::VPCMPEQQZrr) + .value("VPCMPEQQZrrk", LIEF::assembly::x86::OPCODE::VPCMPEQQZrrk) + .value("VPCMPEQQrm", LIEF::assembly::x86::OPCODE::VPCMPEQQrm) + .value("VPCMPEQQrr", LIEF::assembly::x86::OPCODE::VPCMPEQQrr) + .value("VPCMPEQWYrm", LIEF::assembly::x86::OPCODE::VPCMPEQWYrm) + .value("VPCMPEQWYrr", LIEF::assembly::x86::OPCODE::VPCMPEQWYrr) + .value("VPCMPEQWZ128rm", LIEF::assembly::x86::OPCODE::VPCMPEQWZ128rm) + .value("VPCMPEQWZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPEQWZ128rmk) + .value("VPCMPEQWZ128rr", LIEF::assembly::x86::OPCODE::VPCMPEQWZ128rr) + .value("VPCMPEQWZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPEQWZ128rrk) + .value("VPCMPEQWZ256rm", LIEF::assembly::x86::OPCODE::VPCMPEQWZ256rm) + .value("VPCMPEQWZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPEQWZ256rmk) + .value("VPCMPEQWZ256rr", LIEF::assembly::x86::OPCODE::VPCMPEQWZ256rr) + .value("VPCMPEQWZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPEQWZ256rrk) + .value("VPCMPEQWZrm", LIEF::assembly::x86::OPCODE::VPCMPEQWZrm) + .value("VPCMPEQWZrmk", LIEF::assembly::x86::OPCODE::VPCMPEQWZrmk) + .value("VPCMPEQWZrr", LIEF::assembly::x86::OPCODE::VPCMPEQWZrr) + .value("VPCMPEQWZrrk", LIEF::assembly::x86::OPCODE::VPCMPEQWZrrk) + .value("VPCMPEQWrm", LIEF::assembly::x86::OPCODE::VPCMPEQWrm) + .value("VPCMPEQWrr", LIEF::assembly::x86::OPCODE::VPCMPEQWrr) + .value("VPCMPESTRIrmi", LIEF::assembly::x86::OPCODE::VPCMPESTRIrmi) + .value("VPCMPESTRIrri", LIEF::assembly::x86::OPCODE::VPCMPESTRIrri) + .value("VPCMPESTRMrmi", LIEF::assembly::x86::OPCODE::VPCMPESTRMrmi) + .value("VPCMPESTRMrri", LIEF::assembly::x86::OPCODE::VPCMPESTRMrri) + .value("VPCMPGTBYrm", LIEF::assembly::x86::OPCODE::VPCMPGTBYrm) + .value("VPCMPGTBYrr", LIEF::assembly::x86::OPCODE::VPCMPGTBYrr) + .value("VPCMPGTBZ128rm", LIEF::assembly::x86::OPCODE::VPCMPGTBZ128rm) + .value("VPCMPGTBZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPGTBZ128rmk) + .value("VPCMPGTBZ128rr", LIEF::assembly::x86::OPCODE::VPCMPGTBZ128rr) + .value("VPCMPGTBZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPGTBZ128rrk) + .value("VPCMPGTBZ256rm", LIEF::assembly::x86::OPCODE::VPCMPGTBZ256rm) + .value("VPCMPGTBZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPGTBZ256rmk) + .value("VPCMPGTBZ256rr", LIEF::assembly::x86::OPCODE::VPCMPGTBZ256rr) + .value("VPCMPGTBZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPGTBZ256rrk); + opcodes.value("VPCMPGTBZrm", LIEF::assembly::x86::OPCODE::VPCMPGTBZrm) + .value("VPCMPGTBZrmk", LIEF::assembly::x86::OPCODE::VPCMPGTBZrmk) + .value("VPCMPGTBZrr", LIEF::assembly::x86::OPCODE::VPCMPGTBZrr) + .value("VPCMPGTBZrrk", LIEF::assembly::x86::OPCODE::VPCMPGTBZrrk) + .value("VPCMPGTBrm", LIEF::assembly::x86::OPCODE::VPCMPGTBrm) + .value("VPCMPGTBrr", LIEF::assembly::x86::OPCODE::VPCMPGTBrr) + .value("VPCMPGTDYrm", LIEF::assembly::x86::OPCODE::VPCMPGTDYrm) + .value("VPCMPGTDYrr", LIEF::assembly::x86::OPCODE::VPCMPGTDYrr) + .value("VPCMPGTDZ128rm", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rm) + .value("VPCMPGTDZ128rmb", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rmb) + .value("VPCMPGTDZ128rmbk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rmbk) + .value("VPCMPGTDZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rmk) + .value("VPCMPGTDZ128rr", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rr) + .value("VPCMPGTDZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ128rrk) + .value("VPCMPGTDZ256rm", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rm) + .value("VPCMPGTDZ256rmb", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rmb) + .value("VPCMPGTDZ256rmbk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rmbk) + .value("VPCMPGTDZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rmk) + .value("VPCMPGTDZ256rr", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rr) + .value("VPCMPGTDZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPGTDZ256rrk) + .value("VPCMPGTDZrm", LIEF::assembly::x86::OPCODE::VPCMPGTDZrm) + .value("VPCMPGTDZrmb", LIEF::assembly::x86::OPCODE::VPCMPGTDZrmb) + .value("VPCMPGTDZrmbk", LIEF::assembly::x86::OPCODE::VPCMPGTDZrmbk) + .value("VPCMPGTDZrmk", LIEF::assembly::x86::OPCODE::VPCMPGTDZrmk) + .value("VPCMPGTDZrr", LIEF::assembly::x86::OPCODE::VPCMPGTDZrr) + .value("VPCMPGTDZrrk", LIEF::assembly::x86::OPCODE::VPCMPGTDZrrk) + .value("VPCMPGTDrm", LIEF::assembly::x86::OPCODE::VPCMPGTDrm) + .value("VPCMPGTDrr", LIEF::assembly::x86::OPCODE::VPCMPGTDrr) + .value("VPCMPGTQYrm", LIEF::assembly::x86::OPCODE::VPCMPGTQYrm) + .value("VPCMPGTQYrr", LIEF::assembly::x86::OPCODE::VPCMPGTQYrr) + .value("VPCMPGTQZ128rm", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rm) + .value("VPCMPGTQZ128rmb", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rmb) + .value("VPCMPGTQZ128rmbk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rmbk) + .value("VPCMPGTQZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rmk) + .value("VPCMPGTQZ128rr", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rr) + .value("VPCMPGTQZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ128rrk) + .value("VPCMPGTQZ256rm", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rm) + .value("VPCMPGTQZ256rmb", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rmb) + .value("VPCMPGTQZ256rmbk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rmbk) + .value("VPCMPGTQZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rmk) + .value("VPCMPGTQZ256rr", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rr) + .value("VPCMPGTQZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPGTQZ256rrk) + .value("VPCMPGTQZrm", LIEF::assembly::x86::OPCODE::VPCMPGTQZrm) + .value("VPCMPGTQZrmb", LIEF::assembly::x86::OPCODE::VPCMPGTQZrmb) + .value("VPCMPGTQZrmbk", LIEF::assembly::x86::OPCODE::VPCMPGTQZrmbk) + .value("VPCMPGTQZrmk", LIEF::assembly::x86::OPCODE::VPCMPGTQZrmk) + .value("VPCMPGTQZrr", LIEF::assembly::x86::OPCODE::VPCMPGTQZrr) + .value("VPCMPGTQZrrk", LIEF::assembly::x86::OPCODE::VPCMPGTQZrrk) + .value("VPCMPGTQrm", LIEF::assembly::x86::OPCODE::VPCMPGTQrm) + .value("VPCMPGTQrr", LIEF::assembly::x86::OPCODE::VPCMPGTQrr) + .value("VPCMPGTWYrm", LIEF::assembly::x86::OPCODE::VPCMPGTWYrm) + .value("VPCMPGTWYrr", LIEF::assembly::x86::OPCODE::VPCMPGTWYrr) + .value("VPCMPGTWZ128rm", LIEF::assembly::x86::OPCODE::VPCMPGTWZ128rm) + .value("VPCMPGTWZ128rmk", LIEF::assembly::x86::OPCODE::VPCMPGTWZ128rmk) + .value("VPCMPGTWZ128rr", LIEF::assembly::x86::OPCODE::VPCMPGTWZ128rr) + .value("VPCMPGTWZ128rrk", LIEF::assembly::x86::OPCODE::VPCMPGTWZ128rrk) + .value("VPCMPGTWZ256rm", LIEF::assembly::x86::OPCODE::VPCMPGTWZ256rm) + .value("VPCMPGTWZ256rmk", LIEF::assembly::x86::OPCODE::VPCMPGTWZ256rmk) + .value("VPCMPGTWZ256rr", LIEF::assembly::x86::OPCODE::VPCMPGTWZ256rr) + .value("VPCMPGTWZ256rrk", LIEF::assembly::x86::OPCODE::VPCMPGTWZ256rrk) + .value("VPCMPGTWZrm", LIEF::assembly::x86::OPCODE::VPCMPGTWZrm) + .value("VPCMPGTWZrmk", LIEF::assembly::x86::OPCODE::VPCMPGTWZrmk) + .value("VPCMPGTWZrr", LIEF::assembly::x86::OPCODE::VPCMPGTWZrr) + .value("VPCMPGTWZrrk", LIEF::assembly::x86::OPCODE::VPCMPGTWZrrk) + .value("VPCMPGTWrm", LIEF::assembly::x86::OPCODE::VPCMPGTWrm) + .value("VPCMPGTWrr", LIEF::assembly::x86::OPCODE::VPCMPGTWrr) + .value("VPCMPISTRIrmi", LIEF::assembly::x86::OPCODE::VPCMPISTRIrmi) + .value("VPCMPISTRIrri", LIEF::assembly::x86::OPCODE::VPCMPISTRIrri) + .value("VPCMPISTRMrmi", LIEF::assembly::x86::OPCODE::VPCMPISTRMrmi) + .value("VPCMPISTRMrri", LIEF::assembly::x86::OPCODE::VPCMPISTRMrri) + .value("VPCMPQZ128rmbi", LIEF::assembly::x86::OPCODE::VPCMPQZ128rmbi) + .value("VPCMPQZ128rmbik", LIEF::assembly::x86::OPCODE::VPCMPQZ128rmbik) + .value("VPCMPQZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPQZ128rmi) + .value("VPCMPQZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPQZ128rmik) + .value("VPCMPQZ128rri", LIEF::assembly::x86::OPCODE::VPCMPQZ128rri) + .value("VPCMPQZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPQZ128rrik) + .value("VPCMPQZ256rmbi", LIEF::assembly::x86::OPCODE::VPCMPQZ256rmbi) + .value("VPCMPQZ256rmbik", LIEF::assembly::x86::OPCODE::VPCMPQZ256rmbik) + .value("VPCMPQZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPQZ256rmi) + .value("VPCMPQZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPQZ256rmik) + .value("VPCMPQZ256rri", LIEF::assembly::x86::OPCODE::VPCMPQZ256rri) + .value("VPCMPQZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPQZ256rrik) + .value("VPCMPQZrmbi", LIEF::assembly::x86::OPCODE::VPCMPQZrmbi) + .value("VPCMPQZrmbik", LIEF::assembly::x86::OPCODE::VPCMPQZrmbik) + .value("VPCMPQZrmi", LIEF::assembly::x86::OPCODE::VPCMPQZrmi) + .value("VPCMPQZrmik", LIEF::assembly::x86::OPCODE::VPCMPQZrmik) + .value("VPCMPQZrri", LIEF::assembly::x86::OPCODE::VPCMPQZrri) + .value("VPCMPQZrrik", LIEF::assembly::x86::OPCODE::VPCMPQZrrik) + .value("VPCMPUBZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPUBZ128rmi) + .value("VPCMPUBZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPUBZ128rmik) + .value("VPCMPUBZ128rri", LIEF::assembly::x86::OPCODE::VPCMPUBZ128rri) + .value("VPCMPUBZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPUBZ128rrik) + .value("VPCMPUBZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPUBZ256rmi) + .value("VPCMPUBZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPUBZ256rmik) + .value("VPCMPUBZ256rri", LIEF::assembly::x86::OPCODE::VPCMPUBZ256rri) + .value("VPCMPUBZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPUBZ256rrik) + .value("VPCMPUBZrmi", LIEF::assembly::x86::OPCODE::VPCMPUBZrmi) + .value("VPCMPUBZrmik", LIEF::assembly::x86::OPCODE::VPCMPUBZrmik) + .value("VPCMPUBZrri", LIEF::assembly::x86::OPCODE::VPCMPUBZrri) + .value("VPCMPUBZrrik", LIEF::assembly::x86::OPCODE::VPCMPUBZrrik) + .value("VPCMPUDZ128rmbi", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rmbi) + .value("VPCMPUDZ128rmbik", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rmbik) + .value("VPCMPUDZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rmi) + .value("VPCMPUDZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rmik) + .value("VPCMPUDZ128rri", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rri) + .value("VPCMPUDZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPUDZ128rrik) + .value("VPCMPUDZ256rmbi", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rmbi) + .value("VPCMPUDZ256rmbik", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rmbik) + .value("VPCMPUDZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rmi) + .value("VPCMPUDZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rmik) + .value("VPCMPUDZ256rri", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rri) + .value("VPCMPUDZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPUDZ256rrik) + .value("VPCMPUDZrmbi", LIEF::assembly::x86::OPCODE::VPCMPUDZrmbi) + .value("VPCMPUDZrmbik", LIEF::assembly::x86::OPCODE::VPCMPUDZrmbik) + .value("VPCMPUDZrmi", LIEF::assembly::x86::OPCODE::VPCMPUDZrmi) + .value("VPCMPUDZrmik", LIEF::assembly::x86::OPCODE::VPCMPUDZrmik) + .value("VPCMPUDZrri", LIEF::assembly::x86::OPCODE::VPCMPUDZrri) + .value("VPCMPUDZrrik", LIEF::assembly::x86::OPCODE::VPCMPUDZrrik) + .value("VPCMPUQZ128rmbi", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rmbi) + .value("VPCMPUQZ128rmbik", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rmbik) + .value("VPCMPUQZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rmi) + .value("VPCMPUQZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rmik) + .value("VPCMPUQZ128rri", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rri) + .value("VPCMPUQZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPUQZ128rrik) + .value("VPCMPUQZ256rmbi", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rmbi) + .value("VPCMPUQZ256rmbik", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rmbik) + .value("VPCMPUQZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rmi) + .value("VPCMPUQZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rmik) + .value("VPCMPUQZ256rri", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rri) + .value("VPCMPUQZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPUQZ256rrik) + .value("VPCMPUQZrmbi", LIEF::assembly::x86::OPCODE::VPCMPUQZrmbi) + .value("VPCMPUQZrmbik", LIEF::assembly::x86::OPCODE::VPCMPUQZrmbik) + .value("VPCMPUQZrmi", LIEF::assembly::x86::OPCODE::VPCMPUQZrmi) + .value("VPCMPUQZrmik", LIEF::assembly::x86::OPCODE::VPCMPUQZrmik) + .value("VPCMPUQZrri", LIEF::assembly::x86::OPCODE::VPCMPUQZrri) + .value("VPCMPUQZrrik", LIEF::assembly::x86::OPCODE::VPCMPUQZrrik) + .value("VPCMPUWZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPUWZ128rmi) + .value("VPCMPUWZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPUWZ128rmik) + .value("VPCMPUWZ128rri", LIEF::assembly::x86::OPCODE::VPCMPUWZ128rri) + .value("VPCMPUWZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPUWZ128rrik) + .value("VPCMPUWZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPUWZ256rmi) + .value("VPCMPUWZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPUWZ256rmik) + .value("VPCMPUWZ256rri", LIEF::assembly::x86::OPCODE::VPCMPUWZ256rri) + .value("VPCMPUWZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPUWZ256rrik) + .value("VPCMPUWZrmi", LIEF::assembly::x86::OPCODE::VPCMPUWZrmi) + .value("VPCMPUWZrmik", LIEF::assembly::x86::OPCODE::VPCMPUWZrmik) + .value("VPCMPUWZrri", LIEF::assembly::x86::OPCODE::VPCMPUWZrri) + .value("VPCMPUWZrrik", LIEF::assembly::x86::OPCODE::VPCMPUWZrrik) + .value("VPCMPWZ128rmi", LIEF::assembly::x86::OPCODE::VPCMPWZ128rmi) + .value("VPCMPWZ128rmik", LIEF::assembly::x86::OPCODE::VPCMPWZ128rmik) + .value("VPCMPWZ128rri", LIEF::assembly::x86::OPCODE::VPCMPWZ128rri) + .value("VPCMPWZ128rrik", LIEF::assembly::x86::OPCODE::VPCMPWZ128rrik) + .value("VPCMPWZ256rmi", LIEF::assembly::x86::OPCODE::VPCMPWZ256rmi) + .value("VPCMPWZ256rmik", LIEF::assembly::x86::OPCODE::VPCMPWZ256rmik) + .value("VPCMPWZ256rri", LIEF::assembly::x86::OPCODE::VPCMPWZ256rri) + .value("VPCMPWZ256rrik", LIEF::assembly::x86::OPCODE::VPCMPWZ256rrik) + .value("VPCMPWZrmi", LIEF::assembly::x86::OPCODE::VPCMPWZrmi) + .value("VPCMPWZrmik", LIEF::assembly::x86::OPCODE::VPCMPWZrmik) + .value("VPCMPWZrri", LIEF::assembly::x86::OPCODE::VPCMPWZrri) + .value("VPCMPWZrrik", LIEF::assembly::x86::OPCODE::VPCMPWZrrik) + .value("VPCOMBmi", LIEF::assembly::x86::OPCODE::VPCOMBmi) + .value("VPCOMBri", LIEF::assembly::x86::OPCODE::VPCOMBri) + .value("VPCOMDmi", LIEF::assembly::x86::OPCODE::VPCOMDmi) + .value("VPCOMDri", LIEF::assembly::x86::OPCODE::VPCOMDri) + .value("VPCOMPRESSBZ128mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ128mr) + .value("VPCOMPRESSBZ128mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ128mrk) + .value("VPCOMPRESSBZ128rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ128rr) + .value("VPCOMPRESSBZ128rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ128rrk) + .value("VPCOMPRESSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ128rrkz) + .value("VPCOMPRESSBZ256mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ256mr) + .value("VPCOMPRESSBZ256mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ256mrk) + .value("VPCOMPRESSBZ256rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ256rr) + .value("VPCOMPRESSBZ256rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ256rrk) + .value("VPCOMPRESSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZ256rrkz) + .value("VPCOMPRESSBZmr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZmr) + .value("VPCOMPRESSBZmrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZmrk) + .value("VPCOMPRESSBZrr", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZrr) + .value("VPCOMPRESSBZrrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZrrk) + .value("VPCOMPRESSBZrrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSBZrrkz) + .value("VPCOMPRESSDZ128mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ128mr) + .value("VPCOMPRESSDZ128mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ128mrk) + .value("VPCOMPRESSDZ128rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ128rr) + .value("VPCOMPRESSDZ128rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ128rrk) + .value("VPCOMPRESSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ128rrkz) + .value("VPCOMPRESSDZ256mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ256mr) + .value("VPCOMPRESSDZ256mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ256mrk) + .value("VPCOMPRESSDZ256rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ256rr) + .value("VPCOMPRESSDZ256rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ256rrk) + .value("VPCOMPRESSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZ256rrkz) + .value("VPCOMPRESSDZmr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZmr) + .value("VPCOMPRESSDZmrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZmrk) + .value("VPCOMPRESSDZrr", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZrr) + .value("VPCOMPRESSDZrrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZrrk) + .value("VPCOMPRESSDZrrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSDZrrkz) + .value("VPCOMPRESSQZ128mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ128mr) + .value("VPCOMPRESSQZ128mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ128mrk) + .value("VPCOMPRESSQZ128rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ128rr) + .value("VPCOMPRESSQZ128rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ128rrk) + .value("VPCOMPRESSQZ128rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ128rrkz) + .value("VPCOMPRESSQZ256mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ256mr) + .value("VPCOMPRESSQZ256mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ256mrk) + .value("VPCOMPRESSQZ256rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ256rr) + .value("VPCOMPRESSQZ256rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ256rrk) + .value("VPCOMPRESSQZ256rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZ256rrkz) + .value("VPCOMPRESSQZmr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZmr) + .value("VPCOMPRESSQZmrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZmrk) + .value("VPCOMPRESSQZrr", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZrr) + .value("VPCOMPRESSQZrrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZrrk) + .value("VPCOMPRESSQZrrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSQZrrkz) + .value("VPCOMPRESSWZ128mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ128mr) + .value("VPCOMPRESSWZ128mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ128mrk) + .value("VPCOMPRESSWZ128rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ128rr) + .value("VPCOMPRESSWZ128rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ128rrk) + .value("VPCOMPRESSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ128rrkz) + .value("VPCOMPRESSWZ256mr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ256mr) + .value("VPCOMPRESSWZ256mrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ256mrk) + .value("VPCOMPRESSWZ256rr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ256rr) + .value("VPCOMPRESSWZ256rrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ256rrk) + .value("VPCOMPRESSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZ256rrkz) + .value("VPCOMPRESSWZmr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZmr) + .value("VPCOMPRESSWZmrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZmrk) + .value("VPCOMPRESSWZrr", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZrr) + .value("VPCOMPRESSWZrrk", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZrrk) + .value("VPCOMPRESSWZrrkz", LIEF::assembly::x86::OPCODE::VPCOMPRESSWZrrkz) + .value("VPCOMQmi", LIEF::assembly::x86::OPCODE::VPCOMQmi) + .value("VPCOMQri", LIEF::assembly::x86::OPCODE::VPCOMQri) + .value("VPCOMUBmi", LIEF::assembly::x86::OPCODE::VPCOMUBmi) + .value("VPCOMUBri", LIEF::assembly::x86::OPCODE::VPCOMUBri) + .value("VPCOMUDmi", LIEF::assembly::x86::OPCODE::VPCOMUDmi) + .value("VPCOMUDri", LIEF::assembly::x86::OPCODE::VPCOMUDri) + .value("VPCOMUQmi", LIEF::assembly::x86::OPCODE::VPCOMUQmi) + .value("VPCOMUQri", LIEF::assembly::x86::OPCODE::VPCOMUQri) + .value("VPCOMUWmi", LIEF::assembly::x86::OPCODE::VPCOMUWmi) + .value("VPCOMUWri", LIEF::assembly::x86::OPCODE::VPCOMUWri) + .value("VPCOMWmi", LIEF::assembly::x86::OPCODE::VPCOMWmi) + .value("VPCOMWri", LIEF::assembly::x86::OPCODE::VPCOMWri) + .value("VPCONFLICTDZ128rm", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rm) + .value("VPCONFLICTDZ128rmb", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rmb) + .value("VPCONFLICTDZ128rmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rmbk) + .value("VPCONFLICTDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rmbkz) + .value("VPCONFLICTDZ128rmk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rmk) + .value("VPCONFLICTDZ128rmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rmkz) + .value("VPCONFLICTDZ128rr", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rr) + .value("VPCONFLICTDZ128rrk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rrk) + .value("VPCONFLICTDZ128rrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ128rrkz) + .value("VPCONFLICTDZ256rm", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rm) + .value("VPCONFLICTDZ256rmb", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rmb) + .value("VPCONFLICTDZ256rmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rmbk) + .value("VPCONFLICTDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rmbkz) + .value("VPCONFLICTDZ256rmk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rmk) + .value("VPCONFLICTDZ256rmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rmkz) + .value("VPCONFLICTDZ256rr", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rr) + .value("VPCONFLICTDZ256rrk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rrk) + .value("VPCONFLICTDZ256rrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZ256rrkz) + .value("VPCONFLICTDZrm", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrm) + .value("VPCONFLICTDZrmb", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrmb) + .value("VPCONFLICTDZrmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrmbk) + .value("VPCONFLICTDZrmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrmbkz) + .value("VPCONFLICTDZrmk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrmk) + .value("VPCONFLICTDZrmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrmkz) + .value("VPCONFLICTDZrr", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrr) + .value("VPCONFLICTDZrrk", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrrk) + .value("VPCONFLICTDZrrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTDZrrkz) + .value("VPCONFLICTQZ128rm", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rm) + .value("VPCONFLICTQZ128rmb", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rmb) + .value("VPCONFLICTQZ128rmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rmbk) + .value("VPCONFLICTQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rmbkz) + .value("VPCONFLICTQZ128rmk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rmk) + .value("VPCONFLICTQZ128rmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rmkz) + .value("VPCONFLICTQZ128rr", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rr) + .value("VPCONFLICTQZ128rrk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rrk) + .value("VPCONFLICTQZ128rrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ128rrkz) + .value("VPCONFLICTQZ256rm", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rm) + .value("VPCONFLICTQZ256rmb", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rmb) + .value("VPCONFLICTQZ256rmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rmbk) + .value("VPCONFLICTQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rmbkz) + .value("VPCONFLICTQZ256rmk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rmk) + .value("VPCONFLICTQZ256rmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rmkz) + .value("VPCONFLICTQZ256rr", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rr) + .value("VPCONFLICTQZ256rrk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rrk) + .value("VPCONFLICTQZ256rrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZ256rrkz) + .value("VPCONFLICTQZrm", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrm) + .value("VPCONFLICTQZrmb", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrmb) + .value("VPCONFLICTQZrmbk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrmbk) + .value("VPCONFLICTQZrmbkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrmbkz) + .value("VPCONFLICTQZrmk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrmk) + .value("VPCONFLICTQZrmkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrmkz) + .value("VPCONFLICTQZrr", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrr) + .value("VPCONFLICTQZrrk", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrrk) + .value("VPCONFLICTQZrrkz", LIEF::assembly::x86::OPCODE::VPCONFLICTQZrrkz) + .value("VPDPBSSDSYrm", LIEF::assembly::x86::OPCODE::VPDPBSSDSYrm) + .value("VPDPBSSDSYrr", LIEF::assembly::x86::OPCODE::VPDPBSSDSYrr) + .value("VPDPBSSDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rm) + .value("VPDPBSSDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rmb) + .value("VPDPBSSDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rmbk) + .value("VPDPBSSDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rmbkz) + .value("VPDPBSSDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rmk) + .value("VPDPBSSDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rmkz) + .value("VPDPBSSDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rr) + .value("VPDPBSSDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rrk); + opcodes.value("VPDPBSSDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ128rrkz) + .value("VPDPBSSDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rm) + .value("VPDPBSSDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rmb) + .value("VPDPBSSDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rmbk) + .value("VPDPBSSDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rmbkz) + .value("VPDPBSSDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rmk) + .value("VPDPBSSDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rmkz) + .value("VPDPBSSDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rr) + .value("VPDPBSSDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rrk) + .value("VPDPBSSDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZ256rrkz) + .value("VPDPBSSDSZrm", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrm) + .value("VPDPBSSDSZrmb", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrmb) + .value("VPDPBSSDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrmbk) + .value("VPDPBSSDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrmbkz) + .value("VPDPBSSDSZrmk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrmk) + .value("VPDPBSSDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrmkz) + .value("VPDPBSSDSZrr", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrr) + .value("VPDPBSSDSZrrk", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrrk) + .value("VPDPBSSDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDSZrrkz) + .value("VPDPBSSDSrm", LIEF::assembly::x86::OPCODE::VPDPBSSDSrm) + .value("VPDPBSSDSrr", LIEF::assembly::x86::OPCODE::VPDPBSSDSrr) + .value("VPDPBSSDYrm", LIEF::assembly::x86::OPCODE::VPDPBSSDYrm) + .value("VPDPBSSDYrr", LIEF::assembly::x86::OPCODE::VPDPBSSDYrr) + .value("VPDPBSSDZ128rm", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rm) + .value("VPDPBSSDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rmb) + .value("VPDPBSSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rmbk) + .value("VPDPBSSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rmbkz) + .value("VPDPBSSDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rmk) + .value("VPDPBSSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rmkz) + .value("VPDPBSSDZ128rr", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rr) + .value("VPDPBSSDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rrk) + .value("VPDPBSSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ128rrkz) + .value("VPDPBSSDZ256rm", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rm) + .value("VPDPBSSDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rmb) + .value("VPDPBSSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rmbk) + .value("VPDPBSSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rmbkz) + .value("VPDPBSSDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rmk) + .value("VPDPBSSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rmkz) + .value("VPDPBSSDZ256rr", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rr) + .value("VPDPBSSDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rrk) + .value("VPDPBSSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZ256rrkz) + .value("VPDPBSSDZrm", LIEF::assembly::x86::OPCODE::VPDPBSSDZrm) + .value("VPDPBSSDZrmb", LIEF::assembly::x86::OPCODE::VPDPBSSDZrmb) + .value("VPDPBSSDZrmbk", LIEF::assembly::x86::OPCODE::VPDPBSSDZrmbk) + .value("VPDPBSSDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZrmbkz) + .value("VPDPBSSDZrmk", LIEF::assembly::x86::OPCODE::VPDPBSSDZrmk) + .value("VPDPBSSDZrmkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZrmkz) + .value("VPDPBSSDZrr", LIEF::assembly::x86::OPCODE::VPDPBSSDZrr) + .value("VPDPBSSDZrrk", LIEF::assembly::x86::OPCODE::VPDPBSSDZrrk) + .value("VPDPBSSDZrrkz", LIEF::assembly::x86::OPCODE::VPDPBSSDZrrkz) + .value("VPDPBSSDrm", LIEF::assembly::x86::OPCODE::VPDPBSSDrm) + .value("VPDPBSSDrr", LIEF::assembly::x86::OPCODE::VPDPBSSDrr) + .value("VPDPBSUDSYrm", LIEF::assembly::x86::OPCODE::VPDPBSUDSYrm) + .value("VPDPBSUDSYrr", LIEF::assembly::x86::OPCODE::VPDPBSUDSYrr) + .value("VPDPBSUDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rm) + .value("VPDPBSUDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rmb) + .value("VPDPBSUDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rmbk) + .value("VPDPBSUDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rmbkz) + .value("VPDPBSUDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rmk) + .value("VPDPBSUDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rmkz) + .value("VPDPBSUDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rr) + .value("VPDPBSUDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rrk) + .value("VPDPBSUDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ128rrkz) + .value("VPDPBSUDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rm) + .value("VPDPBSUDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rmb) + .value("VPDPBSUDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rmbk) + .value("VPDPBSUDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rmbkz) + .value("VPDPBSUDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rmk) + .value("VPDPBSUDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rmkz) + .value("VPDPBSUDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rr) + .value("VPDPBSUDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rrk) + .value("VPDPBSUDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZ256rrkz) + .value("VPDPBSUDSZrm", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrm) + .value("VPDPBSUDSZrmb", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrmb) + .value("VPDPBSUDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrmbk) + .value("VPDPBSUDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrmbkz) + .value("VPDPBSUDSZrmk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrmk) + .value("VPDPBSUDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrmkz) + .value("VPDPBSUDSZrr", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrr) + .value("VPDPBSUDSZrrk", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrrk) + .value("VPDPBSUDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDSZrrkz) + .value("VPDPBSUDSrm", LIEF::assembly::x86::OPCODE::VPDPBSUDSrm) + .value("VPDPBSUDSrr", LIEF::assembly::x86::OPCODE::VPDPBSUDSrr) + .value("VPDPBSUDYrm", LIEF::assembly::x86::OPCODE::VPDPBSUDYrm) + .value("VPDPBSUDYrr", LIEF::assembly::x86::OPCODE::VPDPBSUDYrr) + .value("VPDPBSUDZ128rm", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rm) + .value("VPDPBSUDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rmb) + .value("VPDPBSUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rmbk) + .value("VPDPBSUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rmbkz) + .value("VPDPBSUDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rmk) + .value("VPDPBSUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rmkz) + .value("VPDPBSUDZ128rr", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rr) + .value("VPDPBSUDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rrk) + .value("VPDPBSUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ128rrkz) + .value("VPDPBSUDZ256rm", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rm) + .value("VPDPBSUDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rmb) + .value("VPDPBSUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rmbk) + .value("VPDPBSUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rmbkz) + .value("VPDPBSUDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rmk) + .value("VPDPBSUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rmkz) + .value("VPDPBSUDZ256rr", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rr) + .value("VPDPBSUDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rrk) + .value("VPDPBSUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZ256rrkz) + .value("VPDPBSUDZrm", LIEF::assembly::x86::OPCODE::VPDPBSUDZrm) + .value("VPDPBSUDZrmb", LIEF::assembly::x86::OPCODE::VPDPBSUDZrmb) + .value("VPDPBSUDZrmbk", LIEF::assembly::x86::OPCODE::VPDPBSUDZrmbk) + .value("VPDPBSUDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZrmbkz) + .value("VPDPBSUDZrmk", LIEF::assembly::x86::OPCODE::VPDPBSUDZrmk) + .value("VPDPBSUDZrmkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZrmkz) + .value("VPDPBSUDZrr", LIEF::assembly::x86::OPCODE::VPDPBSUDZrr) + .value("VPDPBSUDZrrk", LIEF::assembly::x86::OPCODE::VPDPBSUDZrrk) + .value("VPDPBSUDZrrkz", LIEF::assembly::x86::OPCODE::VPDPBSUDZrrkz) + .value("VPDPBSUDrm", LIEF::assembly::x86::OPCODE::VPDPBSUDrm) + .value("VPDPBSUDrr", LIEF::assembly::x86::OPCODE::VPDPBSUDrr) + .value("VPDPBUSDSYrm", LIEF::assembly::x86::OPCODE::VPDPBUSDSYrm) + .value("VPDPBUSDSYrr", LIEF::assembly::x86::OPCODE::VPDPBUSDSYrr) + .value("VPDPBUSDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rm) + .value("VPDPBUSDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rmb) + .value("VPDPBUSDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rmbk) + .value("VPDPBUSDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rmbkz) + .value("VPDPBUSDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rmk) + .value("VPDPBUSDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rmkz) + .value("VPDPBUSDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rr) + .value("VPDPBUSDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rrk) + .value("VPDPBUSDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ128rrkz) + .value("VPDPBUSDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rm) + .value("VPDPBUSDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rmb) + .value("VPDPBUSDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rmbk) + .value("VPDPBUSDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rmbkz) + .value("VPDPBUSDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rmk) + .value("VPDPBUSDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rmkz) + .value("VPDPBUSDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rr) + .value("VPDPBUSDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rrk) + .value("VPDPBUSDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZ256rrkz) + .value("VPDPBUSDSZrm", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrm) + .value("VPDPBUSDSZrmb", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrmb) + .value("VPDPBUSDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrmbk) + .value("VPDPBUSDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrmbkz) + .value("VPDPBUSDSZrmk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrmk) + .value("VPDPBUSDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrmkz) + .value("VPDPBUSDSZrr", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrr) + .value("VPDPBUSDSZrrk", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrrk) + .value("VPDPBUSDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDSZrrkz) + .value("VPDPBUSDSrm", LIEF::assembly::x86::OPCODE::VPDPBUSDSrm) + .value("VPDPBUSDSrr", LIEF::assembly::x86::OPCODE::VPDPBUSDSrr) + .value("VPDPBUSDYrm", LIEF::assembly::x86::OPCODE::VPDPBUSDYrm) + .value("VPDPBUSDYrr", LIEF::assembly::x86::OPCODE::VPDPBUSDYrr) + .value("VPDPBUSDZ128rm", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rm) + .value("VPDPBUSDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rmb) + .value("VPDPBUSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rmbk) + .value("VPDPBUSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rmbkz) + .value("VPDPBUSDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rmk) + .value("VPDPBUSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rmkz) + .value("VPDPBUSDZ128rr", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rr) + .value("VPDPBUSDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rrk) + .value("VPDPBUSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ128rrkz) + .value("VPDPBUSDZ256rm", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rm) + .value("VPDPBUSDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rmb) + .value("VPDPBUSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rmbk) + .value("VPDPBUSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rmbkz) + .value("VPDPBUSDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rmk) + .value("VPDPBUSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rmkz) + .value("VPDPBUSDZ256rr", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rr) + .value("VPDPBUSDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rrk) + .value("VPDPBUSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZ256rrkz) + .value("VPDPBUSDZrm", LIEF::assembly::x86::OPCODE::VPDPBUSDZrm) + .value("VPDPBUSDZrmb", LIEF::assembly::x86::OPCODE::VPDPBUSDZrmb) + .value("VPDPBUSDZrmbk", LIEF::assembly::x86::OPCODE::VPDPBUSDZrmbk) + .value("VPDPBUSDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZrmbkz) + .value("VPDPBUSDZrmk", LIEF::assembly::x86::OPCODE::VPDPBUSDZrmk) + .value("VPDPBUSDZrmkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZrmkz) + .value("VPDPBUSDZrr", LIEF::assembly::x86::OPCODE::VPDPBUSDZrr) + .value("VPDPBUSDZrrk", LIEF::assembly::x86::OPCODE::VPDPBUSDZrrk) + .value("VPDPBUSDZrrkz", LIEF::assembly::x86::OPCODE::VPDPBUSDZrrkz) + .value("VPDPBUSDrm", LIEF::assembly::x86::OPCODE::VPDPBUSDrm) + .value("VPDPBUSDrr", LIEF::assembly::x86::OPCODE::VPDPBUSDrr) + .value("VPDPBUUDSYrm", LIEF::assembly::x86::OPCODE::VPDPBUUDSYrm) + .value("VPDPBUUDSYrr", LIEF::assembly::x86::OPCODE::VPDPBUUDSYrr) + .value("VPDPBUUDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rm) + .value("VPDPBUUDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rmb) + .value("VPDPBUUDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rmbk) + .value("VPDPBUUDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rmbkz) + .value("VPDPBUUDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rmk) + .value("VPDPBUUDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rmkz) + .value("VPDPBUUDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rr) + .value("VPDPBUUDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rrk) + .value("VPDPBUUDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ128rrkz) + .value("VPDPBUUDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rm) + .value("VPDPBUUDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rmb) + .value("VPDPBUUDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rmbk) + .value("VPDPBUUDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rmbkz) + .value("VPDPBUUDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rmk) + .value("VPDPBUUDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rmkz) + .value("VPDPBUUDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rr) + .value("VPDPBUUDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rrk) + .value("VPDPBUUDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZ256rrkz) + .value("VPDPBUUDSZrm", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrm) + .value("VPDPBUUDSZrmb", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrmb) + .value("VPDPBUUDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrmbk) + .value("VPDPBUUDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrmbkz) + .value("VPDPBUUDSZrmk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrmk) + .value("VPDPBUUDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrmkz) + .value("VPDPBUUDSZrr", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrr) + .value("VPDPBUUDSZrrk", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrrk) + .value("VPDPBUUDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDSZrrkz) + .value("VPDPBUUDSrm", LIEF::assembly::x86::OPCODE::VPDPBUUDSrm) + .value("VPDPBUUDSrr", LIEF::assembly::x86::OPCODE::VPDPBUUDSrr) + .value("VPDPBUUDYrm", LIEF::assembly::x86::OPCODE::VPDPBUUDYrm) + .value("VPDPBUUDYrr", LIEF::assembly::x86::OPCODE::VPDPBUUDYrr) + .value("VPDPBUUDZ128rm", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rm) + .value("VPDPBUUDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rmb) + .value("VPDPBUUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rmbk) + .value("VPDPBUUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rmbkz) + .value("VPDPBUUDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rmk) + .value("VPDPBUUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rmkz) + .value("VPDPBUUDZ128rr", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rr) + .value("VPDPBUUDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rrk) + .value("VPDPBUUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ128rrkz) + .value("VPDPBUUDZ256rm", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rm) + .value("VPDPBUUDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rmb) + .value("VPDPBUUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rmbk) + .value("VPDPBUUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rmbkz) + .value("VPDPBUUDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rmk) + .value("VPDPBUUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rmkz) + .value("VPDPBUUDZ256rr", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rr) + .value("VPDPBUUDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rrk) + .value("VPDPBUUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZ256rrkz) + .value("VPDPBUUDZrm", LIEF::assembly::x86::OPCODE::VPDPBUUDZrm) + .value("VPDPBUUDZrmb", LIEF::assembly::x86::OPCODE::VPDPBUUDZrmb) + .value("VPDPBUUDZrmbk", LIEF::assembly::x86::OPCODE::VPDPBUUDZrmbk) + .value("VPDPBUUDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZrmbkz) + .value("VPDPBUUDZrmk", LIEF::assembly::x86::OPCODE::VPDPBUUDZrmk) + .value("VPDPBUUDZrmkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZrmkz) + .value("VPDPBUUDZrr", LIEF::assembly::x86::OPCODE::VPDPBUUDZrr) + .value("VPDPBUUDZrrk", LIEF::assembly::x86::OPCODE::VPDPBUUDZrrk) + .value("VPDPBUUDZrrkz", LIEF::assembly::x86::OPCODE::VPDPBUUDZrrkz) + .value("VPDPBUUDrm", LIEF::assembly::x86::OPCODE::VPDPBUUDrm) + .value("VPDPBUUDrr", LIEF::assembly::x86::OPCODE::VPDPBUUDrr) + .value("VPDPWSSDSYrm", LIEF::assembly::x86::OPCODE::VPDPWSSDSYrm) + .value("VPDPWSSDSYrr", LIEF::assembly::x86::OPCODE::VPDPWSSDSYrr) + .value("VPDPWSSDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rm) + .value("VPDPWSSDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rmb) + .value("VPDPWSSDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rmbk) + .value("VPDPWSSDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rmbkz) + .value("VPDPWSSDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rmk) + .value("VPDPWSSDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rmkz) + .value("VPDPWSSDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rr) + .value("VPDPWSSDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rrk) + .value("VPDPWSSDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ128rrkz) + .value("VPDPWSSDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rm) + .value("VPDPWSSDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rmb) + .value("VPDPWSSDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rmbk) + .value("VPDPWSSDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rmbkz) + .value("VPDPWSSDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rmk) + .value("VPDPWSSDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rmkz) + .value("VPDPWSSDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rr) + .value("VPDPWSSDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rrk) + .value("VPDPWSSDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZ256rrkz) + .value("VPDPWSSDSZrm", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrm) + .value("VPDPWSSDSZrmb", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrmb) + .value("VPDPWSSDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrmbk) + .value("VPDPWSSDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrmbkz) + .value("VPDPWSSDSZrmk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrmk) + .value("VPDPWSSDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrmkz) + .value("VPDPWSSDSZrr", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrr) + .value("VPDPWSSDSZrrk", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrrk) + .value("VPDPWSSDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDSZrrkz) + .value("VPDPWSSDSrm", LIEF::assembly::x86::OPCODE::VPDPWSSDSrm) + .value("VPDPWSSDSrr", LIEF::assembly::x86::OPCODE::VPDPWSSDSrr) + .value("VPDPWSSDYrm", LIEF::assembly::x86::OPCODE::VPDPWSSDYrm) + .value("VPDPWSSDYrr", LIEF::assembly::x86::OPCODE::VPDPWSSDYrr) + .value("VPDPWSSDZ128rm", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rm) + .value("VPDPWSSDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rmb) + .value("VPDPWSSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rmbk) + .value("VPDPWSSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rmbkz) + .value("VPDPWSSDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rmk) + .value("VPDPWSSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rmkz) + .value("VPDPWSSDZ128rr", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rr) + .value("VPDPWSSDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rrk) + .value("VPDPWSSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ128rrkz) + .value("VPDPWSSDZ256rm", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rm) + .value("VPDPWSSDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rmb) + .value("VPDPWSSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rmbk) + .value("VPDPWSSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rmbkz) + .value("VPDPWSSDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rmk) + .value("VPDPWSSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rmkz) + .value("VPDPWSSDZ256rr", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rr) + .value("VPDPWSSDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rrk) + .value("VPDPWSSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZ256rrkz) + .value("VPDPWSSDZrm", LIEF::assembly::x86::OPCODE::VPDPWSSDZrm) + .value("VPDPWSSDZrmb", LIEF::assembly::x86::OPCODE::VPDPWSSDZrmb) + .value("VPDPWSSDZrmbk", LIEF::assembly::x86::OPCODE::VPDPWSSDZrmbk) + .value("VPDPWSSDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZrmbkz) + .value("VPDPWSSDZrmk", LIEF::assembly::x86::OPCODE::VPDPWSSDZrmk) + .value("VPDPWSSDZrmkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZrmkz) + .value("VPDPWSSDZrr", LIEF::assembly::x86::OPCODE::VPDPWSSDZrr) + .value("VPDPWSSDZrrk", LIEF::assembly::x86::OPCODE::VPDPWSSDZrrk) + .value("VPDPWSSDZrrkz", LIEF::assembly::x86::OPCODE::VPDPWSSDZrrkz) + .value("VPDPWSSDrm", LIEF::assembly::x86::OPCODE::VPDPWSSDrm) + .value("VPDPWSSDrr", LIEF::assembly::x86::OPCODE::VPDPWSSDrr); + opcodes.value("VPDPWSUDSYrm", LIEF::assembly::x86::OPCODE::VPDPWSUDSYrm) + .value("VPDPWSUDSYrr", LIEF::assembly::x86::OPCODE::VPDPWSUDSYrr) + .value("VPDPWSUDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rm) + .value("VPDPWSUDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rmb) + .value("VPDPWSUDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rmbk) + .value("VPDPWSUDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rmbkz) + .value("VPDPWSUDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rmk) + .value("VPDPWSUDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rmkz) + .value("VPDPWSUDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rr) + .value("VPDPWSUDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rrk) + .value("VPDPWSUDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ128rrkz) + .value("VPDPWSUDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rm) + .value("VPDPWSUDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rmb) + .value("VPDPWSUDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rmbk) + .value("VPDPWSUDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rmbkz) + .value("VPDPWSUDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rmk) + .value("VPDPWSUDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rmkz) + .value("VPDPWSUDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rr) + .value("VPDPWSUDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rrk) + .value("VPDPWSUDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZ256rrkz) + .value("VPDPWSUDSZrm", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrm) + .value("VPDPWSUDSZrmb", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrmb) + .value("VPDPWSUDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrmbk) + .value("VPDPWSUDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrmbkz) + .value("VPDPWSUDSZrmk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrmk) + .value("VPDPWSUDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrmkz) + .value("VPDPWSUDSZrr", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrr) + .value("VPDPWSUDSZrrk", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrrk) + .value("VPDPWSUDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDSZrrkz) + .value("VPDPWSUDSrm", LIEF::assembly::x86::OPCODE::VPDPWSUDSrm) + .value("VPDPWSUDSrr", LIEF::assembly::x86::OPCODE::VPDPWSUDSrr) + .value("VPDPWSUDYrm", LIEF::assembly::x86::OPCODE::VPDPWSUDYrm) + .value("VPDPWSUDYrr", LIEF::assembly::x86::OPCODE::VPDPWSUDYrr) + .value("VPDPWSUDZ128rm", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rm) + .value("VPDPWSUDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rmb) + .value("VPDPWSUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rmbk) + .value("VPDPWSUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rmbkz) + .value("VPDPWSUDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rmk) + .value("VPDPWSUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rmkz) + .value("VPDPWSUDZ128rr", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rr) + .value("VPDPWSUDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rrk) + .value("VPDPWSUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ128rrkz) + .value("VPDPWSUDZ256rm", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rm) + .value("VPDPWSUDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rmb) + .value("VPDPWSUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rmbk) + .value("VPDPWSUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rmbkz) + .value("VPDPWSUDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rmk) + .value("VPDPWSUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rmkz) + .value("VPDPWSUDZ256rr", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rr) + .value("VPDPWSUDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rrk) + .value("VPDPWSUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZ256rrkz) + .value("VPDPWSUDZrm", LIEF::assembly::x86::OPCODE::VPDPWSUDZrm) + .value("VPDPWSUDZrmb", LIEF::assembly::x86::OPCODE::VPDPWSUDZrmb) + .value("VPDPWSUDZrmbk", LIEF::assembly::x86::OPCODE::VPDPWSUDZrmbk) + .value("VPDPWSUDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZrmbkz) + .value("VPDPWSUDZrmk", LIEF::assembly::x86::OPCODE::VPDPWSUDZrmk) + .value("VPDPWSUDZrmkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZrmkz) + .value("VPDPWSUDZrr", LIEF::assembly::x86::OPCODE::VPDPWSUDZrr) + .value("VPDPWSUDZrrk", LIEF::assembly::x86::OPCODE::VPDPWSUDZrrk) + .value("VPDPWSUDZrrkz", LIEF::assembly::x86::OPCODE::VPDPWSUDZrrkz) + .value("VPDPWSUDrm", LIEF::assembly::x86::OPCODE::VPDPWSUDrm) + .value("VPDPWSUDrr", LIEF::assembly::x86::OPCODE::VPDPWSUDrr) + .value("VPDPWUSDSYrm", LIEF::assembly::x86::OPCODE::VPDPWUSDSYrm) + .value("VPDPWUSDSYrr", LIEF::assembly::x86::OPCODE::VPDPWUSDSYrr) + .value("VPDPWUSDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rm) + .value("VPDPWUSDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rmb) + .value("VPDPWUSDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rmbk) + .value("VPDPWUSDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rmbkz) + .value("VPDPWUSDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rmk) + .value("VPDPWUSDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rmkz) + .value("VPDPWUSDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rr) + .value("VPDPWUSDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rrk) + .value("VPDPWUSDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ128rrkz) + .value("VPDPWUSDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rm) + .value("VPDPWUSDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rmb) + .value("VPDPWUSDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rmbk) + .value("VPDPWUSDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rmbkz) + .value("VPDPWUSDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rmk) + .value("VPDPWUSDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rmkz) + .value("VPDPWUSDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rr) + .value("VPDPWUSDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rrk) + .value("VPDPWUSDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZ256rrkz) + .value("VPDPWUSDSZrm", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrm) + .value("VPDPWUSDSZrmb", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrmb) + .value("VPDPWUSDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrmbk) + .value("VPDPWUSDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrmbkz) + .value("VPDPWUSDSZrmk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrmk) + .value("VPDPWUSDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrmkz) + .value("VPDPWUSDSZrr", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrr) + .value("VPDPWUSDSZrrk", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrrk) + .value("VPDPWUSDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDSZrrkz) + .value("VPDPWUSDSrm", LIEF::assembly::x86::OPCODE::VPDPWUSDSrm) + .value("VPDPWUSDSrr", LIEF::assembly::x86::OPCODE::VPDPWUSDSrr) + .value("VPDPWUSDYrm", LIEF::assembly::x86::OPCODE::VPDPWUSDYrm) + .value("VPDPWUSDYrr", LIEF::assembly::x86::OPCODE::VPDPWUSDYrr) + .value("VPDPWUSDZ128rm", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rm) + .value("VPDPWUSDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rmb) + .value("VPDPWUSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rmbk) + .value("VPDPWUSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rmbkz) + .value("VPDPWUSDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rmk) + .value("VPDPWUSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rmkz) + .value("VPDPWUSDZ128rr", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rr) + .value("VPDPWUSDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rrk) + .value("VPDPWUSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ128rrkz) + .value("VPDPWUSDZ256rm", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rm) + .value("VPDPWUSDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rmb) + .value("VPDPWUSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rmbk) + .value("VPDPWUSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rmbkz) + .value("VPDPWUSDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rmk) + .value("VPDPWUSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rmkz) + .value("VPDPWUSDZ256rr", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rr) + .value("VPDPWUSDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rrk) + .value("VPDPWUSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZ256rrkz) + .value("VPDPWUSDZrm", LIEF::assembly::x86::OPCODE::VPDPWUSDZrm) + .value("VPDPWUSDZrmb", LIEF::assembly::x86::OPCODE::VPDPWUSDZrmb) + .value("VPDPWUSDZrmbk", LIEF::assembly::x86::OPCODE::VPDPWUSDZrmbk) + .value("VPDPWUSDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZrmbkz) + .value("VPDPWUSDZrmk", LIEF::assembly::x86::OPCODE::VPDPWUSDZrmk) + .value("VPDPWUSDZrmkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZrmkz) + .value("VPDPWUSDZrr", LIEF::assembly::x86::OPCODE::VPDPWUSDZrr) + .value("VPDPWUSDZrrk", LIEF::assembly::x86::OPCODE::VPDPWUSDZrrk) + .value("VPDPWUSDZrrkz", LIEF::assembly::x86::OPCODE::VPDPWUSDZrrkz) + .value("VPDPWUSDrm", LIEF::assembly::x86::OPCODE::VPDPWUSDrm) + .value("VPDPWUSDrr", LIEF::assembly::x86::OPCODE::VPDPWUSDrr) + .value("VPDPWUUDSYrm", LIEF::assembly::x86::OPCODE::VPDPWUUDSYrm) + .value("VPDPWUUDSYrr", LIEF::assembly::x86::OPCODE::VPDPWUUDSYrr) + .value("VPDPWUUDSZ128rm", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rm) + .value("VPDPWUUDSZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rmb) + .value("VPDPWUUDSZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rmbk) + .value("VPDPWUUDSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rmbkz) + .value("VPDPWUUDSZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rmk) + .value("VPDPWUUDSZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rmkz) + .value("VPDPWUUDSZ128rr", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rr) + .value("VPDPWUUDSZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rrk) + .value("VPDPWUUDSZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ128rrkz) + .value("VPDPWUUDSZ256rm", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rm) + .value("VPDPWUUDSZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rmb) + .value("VPDPWUUDSZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rmbk) + .value("VPDPWUUDSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rmbkz) + .value("VPDPWUUDSZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rmk) + .value("VPDPWUUDSZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rmkz) + .value("VPDPWUUDSZ256rr", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rr) + .value("VPDPWUUDSZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rrk) + .value("VPDPWUUDSZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZ256rrkz) + .value("VPDPWUUDSZrm", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrm) + .value("VPDPWUUDSZrmb", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrmb) + .value("VPDPWUUDSZrmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrmbk) + .value("VPDPWUUDSZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrmbkz) + .value("VPDPWUUDSZrmk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrmk) + .value("VPDPWUUDSZrmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrmkz) + .value("VPDPWUUDSZrr", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrr) + .value("VPDPWUUDSZrrk", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrrk) + .value("VPDPWUUDSZrrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDSZrrkz) + .value("VPDPWUUDSrm", LIEF::assembly::x86::OPCODE::VPDPWUUDSrm) + .value("VPDPWUUDSrr", LIEF::assembly::x86::OPCODE::VPDPWUUDSrr) + .value("VPDPWUUDYrm", LIEF::assembly::x86::OPCODE::VPDPWUUDYrm) + .value("VPDPWUUDYrr", LIEF::assembly::x86::OPCODE::VPDPWUUDYrr) + .value("VPDPWUUDZ128rm", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rm) + .value("VPDPWUUDZ128rmb", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rmb) + .value("VPDPWUUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rmbk) + .value("VPDPWUUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rmbkz) + .value("VPDPWUUDZ128rmk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rmk) + .value("VPDPWUUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rmkz) + .value("VPDPWUUDZ128rr", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rr) + .value("VPDPWUUDZ128rrk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rrk) + .value("VPDPWUUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ128rrkz) + .value("VPDPWUUDZ256rm", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rm) + .value("VPDPWUUDZ256rmb", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rmb) + .value("VPDPWUUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rmbk) + .value("VPDPWUUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rmbkz) + .value("VPDPWUUDZ256rmk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rmk) + .value("VPDPWUUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rmkz) + .value("VPDPWUUDZ256rr", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rr) + .value("VPDPWUUDZ256rrk", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rrk) + .value("VPDPWUUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZ256rrkz) + .value("VPDPWUUDZrm", LIEF::assembly::x86::OPCODE::VPDPWUUDZrm) + .value("VPDPWUUDZrmb", LIEF::assembly::x86::OPCODE::VPDPWUUDZrmb) + .value("VPDPWUUDZrmbk", LIEF::assembly::x86::OPCODE::VPDPWUUDZrmbk) + .value("VPDPWUUDZrmbkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZrmbkz) + .value("VPDPWUUDZrmk", LIEF::assembly::x86::OPCODE::VPDPWUUDZrmk) + .value("VPDPWUUDZrmkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZrmkz) + .value("VPDPWUUDZrr", LIEF::assembly::x86::OPCODE::VPDPWUUDZrr) + .value("VPDPWUUDZrrk", LIEF::assembly::x86::OPCODE::VPDPWUUDZrrk) + .value("VPDPWUUDZrrkz", LIEF::assembly::x86::OPCODE::VPDPWUUDZrrkz) + .value("VPDPWUUDrm", LIEF::assembly::x86::OPCODE::VPDPWUUDrm) + .value("VPDPWUUDrr", LIEF::assembly::x86::OPCODE::VPDPWUUDrr) + .value("VPERM2F128rmi", LIEF::assembly::x86::OPCODE::VPERM2F128rmi) + .value("VPERM2F128rri", LIEF::assembly::x86::OPCODE::VPERM2F128rri) + .value("VPERM2I128rmi", LIEF::assembly::x86::OPCODE::VPERM2I128rmi) + .value("VPERM2I128rri", LIEF::assembly::x86::OPCODE::VPERM2I128rri) + .value("VPERMBZ128rm", LIEF::assembly::x86::OPCODE::VPERMBZ128rm) + .value("VPERMBZ128rmk", LIEF::assembly::x86::OPCODE::VPERMBZ128rmk) + .value("VPERMBZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMBZ128rmkz) + .value("VPERMBZ128rr", LIEF::assembly::x86::OPCODE::VPERMBZ128rr) + .value("VPERMBZ128rrk", LIEF::assembly::x86::OPCODE::VPERMBZ128rrk) + .value("VPERMBZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMBZ128rrkz) + .value("VPERMBZ256rm", LIEF::assembly::x86::OPCODE::VPERMBZ256rm) + .value("VPERMBZ256rmk", LIEF::assembly::x86::OPCODE::VPERMBZ256rmk) + .value("VPERMBZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMBZ256rmkz) + .value("VPERMBZ256rr", LIEF::assembly::x86::OPCODE::VPERMBZ256rr) + .value("VPERMBZ256rrk", LIEF::assembly::x86::OPCODE::VPERMBZ256rrk) + .value("VPERMBZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMBZ256rrkz) + .value("VPERMBZrm", LIEF::assembly::x86::OPCODE::VPERMBZrm) + .value("VPERMBZrmk", LIEF::assembly::x86::OPCODE::VPERMBZrmk) + .value("VPERMBZrmkz", LIEF::assembly::x86::OPCODE::VPERMBZrmkz) + .value("VPERMBZrr", LIEF::assembly::x86::OPCODE::VPERMBZrr) + .value("VPERMBZrrk", LIEF::assembly::x86::OPCODE::VPERMBZrrk) + .value("VPERMBZrrkz", LIEF::assembly::x86::OPCODE::VPERMBZrrkz) + .value("VPERMDYrm", LIEF::assembly::x86::OPCODE::VPERMDYrm) + .value("VPERMDYrr", LIEF::assembly::x86::OPCODE::VPERMDYrr) + .value("VPERMDZ256rm", LIEF::assembly::x86::OPCODE::VPERMDZ256rm) + .value("VPERMDZ256rmb", LIEF::assembly::x86::OPCODE::VPERMDZ256rmb) + .value("VPERMDZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMDZ256rmbk) + .value("VPERMDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMDZ256rmbkz) + .value("VPERMDZ256rmk", LIEF::assembly::x86::OPCODE::VPERMDZ256rmk) + .value("VPERMDZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMDZ256rmkz) + .value("VPERMDZ256rr", LIEF::assembly::x86::OPCODE::VPERMDZ256rr) + .value("VPERMDZ256rrk", LIEF::assembly::x86::OPCODE::VPERMDZ256rrk) + .value("VPERMDZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMDZ256rrkz) + .value("VPERMDZrm", LIEF::assembly::x86::OPCODE::VPERMDZrm) + .value("VPERMDZrmb", LIEF::assembly::x86::OPCODE::VPERMDZrmb) + .value("VPERMDZrmbk", LIEF::assembly::x86::OPCODE::VPERMDZrmbk) + .value("VPERMDZrmbkz", LIEF::assembly::x86::OPCODE::VPERMDZrmbkz) + .value("VPERMDZrmk", LIEF::assembly::x86::OPCODE::VPERMDZrmk) + .value("VPERMDZrmkz", LIEF::assembly::x86::OPCODE::VPERMDZrmkz) + .value("VPERMDZrr", LIEF::assembly::x86::OPCODE::VPERMDZrr) + .value("VPERMDZrrk", LIEF::assembly::x86::OPCODE::VPERMDZrrk) + .value("VPERMDZrrkz", LIEF::assembly::x86::OPCODE::VPERMDZrrkz) + .value("VPERMI2BZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rm) + .value("VPERMI2BZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rmk) + .value("VPERMI2BZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rmkz) + .value("VPERMI2BZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rr) + .value("VPERMI2BZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rrk) + .value("VPERMI2BZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2BZ128rrkz) + .value("VPERMI2BZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rm) + .value("VPERMI2BZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rmk) + .value("VPERMI2BZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rmkz) + .value("VPERMI2BZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rr) + .value("VPERMI2BZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rrk) + .value("VPERMI2BZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2BZ256rrkz) + .value("VPERMI2BZrm", LIEF::assembly::x86::OPCODE::VPERMI2BZrm) + .value("VPERMI2BZrmk", LIEF::assembly::x86::OPCODE::VPERMI2BZrmk) + .value("VPERMI2BZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2BZrmkz) + .value("VPERMI2BZrr", LIEF::assembly::x86::OPCODE::VPERMI2BZrr) + .value("VPERMI2BZrrk", LIEF::assembly::x86::OPCODE::VPERMI2BZrrk) + .value("VPERMI2BZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2BZrrkz) + .value("VPERMI2DZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rm) + .value("VPERMI2DZ128rmb", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rmb) + .value("VPERMI2DZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rmbk) + .value("VPERMI2DZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rmbkz) + .value("VPERMI2DZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rmk) + .value("VPERMI2DZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rmkz) + .value("VPERMI2DZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rr) + .value("VPERMI2DZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rrk) + .value("VPERMI2DZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ128rrkz) + .value("VPERMI2DZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rm) + .value("VPERMI2DZ256rmb", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rmb) + .value("VPERMI2DZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rmbk) + .value("VPERMI2DZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rmbkz) + .value("VPERMI2DZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rmk) + .value("VPERMI2DZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rmkz) + .value("VPERMI2DZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rr) + .value("VPERMI2DZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rrk) + .value("VPERMI2DZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2DZ256rrkz) + .value("VPERMI2DZrm", LIEF::assembly::x86::OPCODE::VPERMI2DZrm) + .value("VPERMI2DZrmb", LIEF::assembly::x86::OPCODE::VPERMI2DZrmb) + .value("VPERMI2DZrmbk", LIEF::assembly::x86::OPCODE::VPERMI2DZrmbk) + .value("VPERMI2DZrmbkz", LIEF::assembly::x86::OPCODE::VPERMI2DZrmbkz) + .value("VPERMI2DZrmk", LIEF::assembly::x86::OPCODE::VPERMI2DZrmk) + .value("VPERMI2DZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2DZrmkz) + .value("VPERMI2DZrr", LIEF::assembly::x86::OPCODE::VPERMI2DZrr) + .value("VPERMI2DZrrk", LIEF::assembly::x86::OPCODE::VPERMI2DZrrk) + .value("VPERMI2DZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2DZrrkz) + .value("VPERMI2PDZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rm) + .value("VPERMI2PDZ128rmb", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rmb) + .value("VPERMI2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rmbk) + .value("VPERMI2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rmbkz) + .value("VPERMI2PDZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rmk) + .value("VPERMI2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rmkz) + .value("VPERMI2PDZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rr) + .value("VPERMI2PDZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rrk) + .value("VPERMI2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ128rrkz) + .value("VPERMI2PDZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rm) + .value("VPERMI2PDZ256rmb", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rmb) + .value("VPERMI2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rmbk) + .value("VPERMI2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rmbkz) + .value("VPERMI2PDZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rmk) + .value("VPERMI2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rmkz) + .value("VPERMI2PDZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rr) + .value("VPERMI2PDZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rrk) + .value("VPERMI2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZ256rrkz) + .value("VPERMI2PDZrm", LIEF::assembly::x86::OPCODE::VPERMI2PDZrm) + .value("VPERMI2PDZrmb", LIEF::assembly::x86::OPCODE::VPERMI2PDZrmb) + .value("VPERMI2PDZrmbk", LIEF::assembly::x86::OPCODE::VPERMI2PDZrmbk) + .value("VPERMI2PDZrmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZrmbkz) + .value("VPERMI2PDZrmk", LIEF::assembly::x86::OPCODE::VPERMI2PDZrmk) + .value("VPERMI2PDZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZrmkz) + .value("VPERMI2PDZrr", LIEF::assembly::x86::OPCODE::VPERMI2PDZrr) + .value("VPERMI2PDZrrk", LIEF::assembly::x86::OPCODE::VPERMI2PDZrrk) + .value("VPERMI2PDZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2PDZrrkz); + opcodes.value("VPERMI2PSZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rm) + .value("VPERMI2PSZ128rmb", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rmb) + .value("VPERMI2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rmbk) + .value("VPERMI2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rmbkz) + .value("VPERMI2PSZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rmk) + .value("VPERMI2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rmkz) + .value("VPERMI2PSZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rr) + .value("VPERMI2PSZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rrk) + .value("VPERMI2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ128rrkz) + .value("VPERMI2PSZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rm) + .value("VPERMI2PSZ256rmb", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rmb) + .value("VPERMI2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rmbk) + .value("VPERMI2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rmbkz) + .value("VPERMI2PSZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rmk) + .value("VPERMI2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rmkz) + .value("VPERMI2PSZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rr) + .value("VPERMI2PSZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rrk) + .value("VPERMI2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZ256rrkz) + .value("VPERMI2PSZrm", LIEF::assembly::x86::OPCODE::VPERMI2PSZrm) + .value("VPERMI2PSZrmb", LIEF::assembly::x86::OPCODE::VPERMI2PSZrmb) + .value("VPERMI2PSZrmbk", LIEF::assembly::x86::OPCODE::VPERMI2PSZrmbk) + .value("VPERMI2PSZrmbkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZrmbkz) + .value("VPERMI2PSZrmk", LIEF::assembly::x86::OPCODE::VPERMI2PSZrmk) + .value("VPERMI2PSZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZrmkz) + .value("VPERMI2PSZrr", LIEF::assembly::x86::OPCODE::VPERMI2PSZrr) + .value("VPERMI2PSZrrk", LIEF::assembly::x86::OPCODE::VPERMI2PSZrrk) + .value("VPERMI2PSZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2PSZrrkz) + .value("VPERMI2QZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rm) + .value("VPERMI2QZ128rmb", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rmb) + .value("VPERMI2QZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rmbk) + .value("VPERMI2QZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rmbkz) + .value("VPERMI2QZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rmk) + .value("VPERMI2QZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rmkz) + .value("VPERMI2QZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rr) + .value("VPERMI2QZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rrk) + .value("VPERMI2QZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ128rrkz) + .value("VPERMI2QZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rm) + .value("VPERMI2QZ256rmb", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rmb) + .value("VPERMI2QZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rmbk) + .value("VPERMI2QZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rmbkz) + .value("VPERMI2QZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rmk) + .value("VPERMI2QZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rmkz) + .value("VPERMI2QZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rr) + .value("VPERMI2QZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rrk) + .value("VPERMI2QZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2QZ256rrkz) + .value("VPERMI2QZrm", LIEF::assembly::x86::OPCODE::VPERMI2QZrm) + .value("VPERMI2QZrmb", LIEF::assembly::x86::OPCODE::VPERMI2QZrmb) + .value("VPERMI2QZrmbk", LIEF::assembly::x86::OPCODE::VPERMI2QZrmbk) + .value("VPERMI2QZrmbkz", LIEF::assembly::x86::OPCODE::VPERMI2QZrmbkz) + .value("VPERMI2QZrmk", LIEF::assembly::x86::OPCODE::VPERMI2QZrmk) + .value("VPERMI2QZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2QZrmkz) + .value("VPERMI2QZrr", LIEF::assembly::x86::OPCODE::VPERMI2QZrr) + .value("VPERMI2QZrrk", LIEF::assembly::x86::OPCODE::VPERMI2QZrrk) + .value("VPERMI2QZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2QZrrkz) + .value("VPERMI2WZ128rm", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rm) + .value("VPERMI2WZ128rmk", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rmk) + .value("VPERMI2WZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rmkz) + .value("VPERMI2WZ128rr", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rr) + .value("VPERMI2WZ128rrk", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rrk) + .value("VPERMI2WZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMI2WZ128rrkz) + .value("VPERMI2WZ256rm", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rm) + .value("VPERMI2WZ256rmk", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rmk) + .value("VPERMI2WZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rmkz) + .value("VPERMI2WZ256rr", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rr) + .value("VPERMI2WZ256rrk", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rrk) + .value("VPERMI2WZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMI2WZ256rrkz) + .value("VPERMI2WZrm", LIEF::assembly::x86::OPCODE::VPERMI2WZrm) + .value("VPERMI2WZrmk", LIEF::assembly::x86::OPCODE::VPERMI2WZrmk) + .value("VPERMI2WZrmkz", LIEF::assembly::x86::OPCODE::VPERMI2WZrmkz) + .value("VPERMI2WZrr", LIEF::assembly::x86::OPCODE::VPERMI2WZrr) + .value("VPERMI2WZrrk", LIEF::assembly::x86::OPCODE::VPERMI2WZrrk) + .value("VPERMI2WZrrkz", LIEF::assembly::x86::OPCODE::VPERMI2WZrrkz) + .value("VPERMIL2PDYmr", LIEF::assembly::x86::OPCODE::VPERMIL2PDYmr) + .value("VPERMIL2PDYrm", LIEF::assembly::x86::OPCODE::VPERMIL2PDYrm) + .value("VPERMIL2PDYrr", LIEF::assembly::x86::OPCODE::VPERMIL2PDYrr) + .value("VPERMIL2PDYrr_REV", LIEF::assembly::x86::OPCODE::VPERMIL2PDYrr_REV) + .value("VPERMIL2PDmr", LIEF::assembly::x86::OPCODE::VPERMIL2PDmr) + .value("VPERMIL2PDrm", LIEF::assembly::x86::OPCODE::VPERMIL2PDrm) + .value("VPERMIL2PDrr", LIEF::assembly::x86::OPCODE::VPERMIL2PDrr) + .value("VPERMIL2PDrr_REV", LIEF::assembly::x86::OPCODE::VPERMIL2PDrr_REV) + .value("VPERMIL2PSYmr", LIEF::assembly::x86::OPCODE::VPERMIL2PSYmr) + .value("VPERMIL2PSYrm", LIEF::assembly::x86::OPCODE::VPERMIL2PSYrm) + .value("VPERMIL2PSYrr", LIEF::assembly::x86::OPCODE::VPERMIL2PSYrr) + .value("VPERMIL2PSYrr_REV", LIEF::assembly::x86::OPCODE::VPERMIL2PSYrr_REV) + .value("VPERMIL2PSmr", LIEF::assembly::x86::OPCODE::VPERMIL2PSmr) + .value("VPERMIL2PSrm", LIEF::assembly::x86::OPCODE::VPERMIL2PSrm) + .value("VPERMIL2PSrr", LIEF::assembly::x86::OPCODE::VPERMIL2PSrr) + .value("VPERMIL2PSrr_REV", LIEF::assembly::x86::OPCODE::VPERMIL2PSrr_REV) + .value("VPERMILPDYmi", LIEF::assembly::x86::OPCODE::VPERMILPDYmi) + .value("VPERMILPDYri", LIEF::assembly::x86::OPCODE::VPERMILPDYri) + .value("VPERMILPDYrm", LIEF::assembly::x86::OPCODE::VPERMILPDYrm) + .value("VPERMILPDYrr", LIEF::assembly::x86::OPCODE::VPERMILPDYrr) + .value("VPERMILPDZ128mbi", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mbi) + .value("VPERMILPDZ128mbik", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mbik) + .value("VPERMILPDZ128mbikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mbikz) + .value("VPERMILPDZ128mi", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mi) + .value("VPERMILPDZ128mik", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mik) + .value("VPERMILPDZ128mikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128mikz) + .value("VPERMILPDZ128ri", LIEF::assembly::x86::OPCODE::VPERMILPDZ128ri) + .value("VPERMILPDZ128rik", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rik) + .value("VPERMILPDZ128rikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rikz) + .value("VPERMILPDZ128rm", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rm) + .value("VPERMILPDZ128rmb", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rmb) + .value("VPERMILPDZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rmbk) + .value("VPERMILPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rmbkz) + .value("VPERMILPDZ128rmk", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rmk) + .value("VPERMILPDZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rmkz) + .value("VPERMILPDZ128rr", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rr) + .value("VPERMILPDZ128rrk", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rrk) + .value("VPERMILPDZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ128rrkz) + .value("VPERMILPDZ256mbi", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mbi) + .value("VPERMILPDZ256mbik", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mbik) + .value("VPERMILPDZ256mbikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mbikz) + .value("VPERMILPDZ256mi", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mi) + .value("VPERMILPDZ256mik", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mik) + .value("VPERMILPDZ256mikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256mikz) + .value("VPERMILPDZ256ri", LIEF::assembly::x86::OPCODE::VPERMILPDZ256ri) + .value("VPERMILPDZ256rik", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rik) + .value("VPERMILPDZ256rikz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rikz) + .value("VPERMILPDZ256rm", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rm) + .value("VPERMILPDZ256rmb", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rmb) + .value("VPERMILPDZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rmbk) + .value("VPERMILPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rmbkz) + .value("VPERMILPDZ256rmk", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rmk) + .value("VPERMILPDZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rmkz) + .value("VPERMILPDZ256rr", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rr) + .value("VPERMILPDZ256rrk", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rrk) + .value("VPERMILPDZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMILPDZ256rrkz) + .value("VPERMILPDZmbi", LIEF::assembly::x86::OPCODE::VPERMILPDZmbi) + .value("VPERMILPDZmbik", LIEF::assembly::x86::OPCODE::VPERMILPDZmbik) + .value("VPERMILPDZmbikz", LIEF::assembly::x86::OPCODE::VPERMILPDZmbikz) + .value("VPERMILPDZmi", LIEF::assembly::x86::OPCODE::VPERMILPDZmi) + .value("VPERMILPDZmik", LIEF::assembly::x86::OPCODE::VPERMILPDZmik) + .value("VPERMILPDZmikz", LIEF::assembly::x86::OPCODE::VPERMILPDZmikz) + .value("VPERMILPDZri", LIEF::assembly::x86::OPCODE::VPERMILPDZri) + .value("VPERMILPDZrik", LIEF::assembly::x86::OPCODE::VPERMILPDZrik) + .value("VPERMILPDZrikz", LIEF::assembly::x86::OPCODE::VPERMILPDZrikz) + .value("VPERMILPDZrm", LIEF::assembly::x86::OPCODE::VPERMILPDZrm) + .value("VPERMILPDZrmb", LIEF::assembly::x86::OPCODE::VPERMILPDZrmb) + .value("VPERMILPDZrmbk", LIEF::assembly::x86::OPCODE::VPERMILPDZrmbk) + .value("VPERMILPDZrmbkz", LIEF::assembly::x86::OPCODE::VPERMILPDZrmbkz) + .value("VPERMILPDZrmk", LIEF::assembly::x86::OPCODE::VPERMILPDZrmk) + .value("VPERMILPDZrmkz", LIEF::assembly::x86::OPCODE::VPERMILPDZrmkz) + .value("VPERMILPDZrr", LIEF::assembly::x86::OPCODE::VPERMILPDZrr) + .value("VPERMILPDZrrk", LIEF::assembly::x86::OPCODE::VPERMILPDZrrk) + .value("VPERMILPDZrrkz", LIEF::assembly::x86::OPCODE::VPERMILPDZrrkz) + .value("VPERMILPDmi", LIEF::assembly::x86::OPCODE::VPERMILPDmi) + .value("VPERMILPDri", LIEF::assembly::x86::OPCODE::VPERMILPDri) + .value("VPERMILPDrm", LIEF::assembly::x86::OPCODE::VPERMILPDrm) + .value("VPERMILPDrr", LIEF::assembly::x86::OPCODE::VPERMILPDrr) + .value("VPERMILPSYmi", LIEF::assembly::x86::OPCODE::VPERMILPSYmi) + .value("VPERMILPSYri", LIEF::assembly::x86::OPCODE::VPERMILPSYri) + .value("VPERMILPSYrm", LIEF::assembly::x86::OPCODE::VPERMILPSYrm) + .value("VPERMILPSYrr", LIEF::assembly::x86::OPCODE::VPERMILPSYrr) + .value("VPERMILPSZ128mbi", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mbi) + .value("VPERMILPSZ128mbik", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mbik) + .value("VPERMILPSZ128mbikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mbikz) + .value("VPERMILPSZ128mi", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mi) + .value("VPERMILPSZ128mik", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mik) + .value("VPERMILPSZ128mikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128mikz) + .value("VPERMILPSZ128ri", LIEF::assembly::x86::OPCODE::VPERMILPSZ128ri) + .value("VPERMILPSZ128rik", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rik) + .value("VPERMILPSZ128rikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rikz) + .value("VPERMILPSZ128rm", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rm) + .value("VPERMILPSZ128rmb", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rmb) + .value("VPERMILPSZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rmbk) + .value("VPERMILPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rmbkz) + .value("VPERMILPSZ128rmk", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rmk) + .value("VPERMILPSZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rmkz) + .value("VPERMILPSZ128rr", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rr) + .value("VPERMILPSZ128rrk", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rrk) + .value("VPERMILPSZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ128rrkz) + .value("VPERMILPSZ256mbi", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mbi) + .value("VPERMILPSZ256mbik", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mbik) + .value("VPERMILPSZ256mbikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mbikz) + .value("VPERMILPSZ256mi", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mi) + .value("VPERMILPSZ256mik", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mik) + .value("VPERMILPSZ256mikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256mikz) + .value("VPERMILPSZ256ri", LIEF::assembly::x86::OPCODE::VPERMILPSZ256ri) + .value("VPERMILPSZ256rik", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rik) + .value("VPERMILPSZ256rikz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rikz) + .value("VPERMILPSZ256rm", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rm) + .value("VPERMILPSZ256rmb", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rmb) + .value("VPERMILPSZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rmbk) + .value("VPERMILPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rmbkz) + .value("VPERMILPSZ256rmk", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rmk) + .value("VPERMILPSZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rmkz) + .value("VPERMILPSZ256rr", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rr) + .value("VPERMILPSZ256rrk", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rrk) + .value("VPERMILPSZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMILPSZ256rrkz) + .value("VPERMILPSZmbi", LIEF::assembly::x86::OPCODE::VPERMILPSZmbi) + .value("VPERMILPSZmbik", LIEF::assembly::x86::OPCODE::VPERMILPSZmbik) + .value("VPERMILPSZmbikz", LIEF::assembly::x86::OPCODE::VPERMILPSZmbikz) + .value("VPERMILPSZmi", LIEF::assembly::x86::OPCODE::VPERMILPSZmi) + .value("VPERMILPSZmik", LIEF::assembly::x86::OPCODE::VPERMILPSZmik) + .value("VPERMILPSZmikz", LIEF::assembly::x86::OPCODE::VPERMILPSZmikz) + .value("VPERMILPSZri", LIEF::assembly::x86::OPCODE::VPERMILPSZri) + .value("VPERMILPSZrik", LIEF::assembly::x86::OPCODE::VPERMILPSZrik) + .value("VPERMILPSZrikz", LIEF::assembly::x86::OPCODE::VPERMILPSZrikz) + .value("VPERMILPSZrm", LIEF::assembly::x86::OPCODE::VPERMILPSZrm) + .value("VPERMILPSZrmb", LIEF::assembly::x86::OPCODE::VPERMILPSZrmb) + .value("VPERMILPSZrmbk", LIEF::assembly::x86::OPCODE::VPERMILPSZrmbk) + .value("VPERMILPSZrmbkz", LIEF::assembly::x86::OPCODE::VPERMILPSZrmbkz) + .value("VPERMILPSZrmk", LIEF::assembly::x86::OPCODE::VPERMILPSZrmk) + .value("VPERMILPSZrmkz", LIEF::assembly::x86::OPCODE::VPERMILPSZrmkz) + .value("VPERMILPSZrr", LIEF::assembly::x86::OPCODE::VPERMILPSZrr) + .value("VPERMILPSZrrk", LIEF::assembly::x86::OPCODE::VPERMILPSZrrk) + .value("VPERMILPSZrrkz", LIEF::assembly::x86::OPCODE::VPERMILPSZrrkz) + .value("VPERMILPSmi", LIEF::assembly::x86::OPCODE::VPERMILPSmi) + .value("VPERMILPSri", LIEF::assembly::x86::OPCODE::VPERMILPSri) + .value("VPERMILPSrm", LIEF::assembly::x86::OPCODE::VPERMILPSrm) + .value("VPERMILPSrr", LIEF::assembly::x86::OPCODE::VPERMILPSrr) + .value("VPERMPDYmi", LIEF::assembly::x86::OPCODE::VPERMPDYmi) + .value("VPERMPDYri", LIEF::assembly::x86::OPCODE::VPERMPDYri) + .value("VPERMPDZ256mbi", LIEF::assembly::x86::OPCODE::VPERMPDZ256mbi) + .value("VPERMPDZ256mbik", LIEF::assembly::x86::OPCODE::VPERMPDZ256mbik) + .value("VPERMPDZ256mbikz", LIEF::assembly::x86::OPCODE::VPERMPDZ256mbikz) + .value("VPERMPDZ256mi", LIEF::assembly::x86::OPCODE::VPERMPDZ256mi) + .value("VPERMPDZ256mik", LIEF::assembly::x86::OPCODE::VPERMPDZ256mik) + .value("VPERMPDZ256mikz", LIEF::assembly::x86::OPCODE::VPERMPDZ256mikz) + .value("VPERMPDZ256ri", LIEF::assembly::x86::OPCODE::VPERMPDZ256ri) + .value("VPERMPDZ256rik", LIEF::assembly::x86::OPCODE::VPERMPDZ256rik) + .value("VPERMPDZ256rikz", LIEF::assembly::x86::OPCODE::VPERMPDZ256rikz) + .value("VPERMPDZ256rm", LIEF::assembly::x86::OPCODE::VPERMPDZ256rm) + .value("VPERMPDZ256rmb", LIEF::assembly::x86::OPCODE::VPERMPDZ256rmb) + .value("VPERMPDZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMPDZ256rmbk) + .value("VPERMPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMPDZ256rmbkz) + .value("VPERMPDZ256rmk", LIEF::assembly::x86::OPCODE::VPERMPDZ256rmk) + .value("VPERMPDZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMPDZ256rmkz) + .value("VPERMPDZ256rr", LIEF::assembly::x86::OPCODE::VPERMPDZ256rr) + .value("VPERMPDZ256rrk", LIEF::assembly::x86::OPCODE::VPERMPDZ256rrk) + .value("VPERMPDZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMPDZ256rrkz) + .value("VPERMPDZmbi", LIEF::assembly::x86::OPCODE::VPERMPDZmbi) + .value("VPERMPDZmbik", LIEF::assembly::x86::OPCODE::VPERMPDZmbik) + .value("VPERMPDZmbikz", LIEF::assembly::x86::OPCODE::VPERMPDZmbikz) + .value("VPERMPDZmi", LIEF::assembly::x86::OPCODE::VPERMPDZmi) + .value("VPERMPDZmik", LIEF::assembly::x86::OPCODE::VPERMPDZmik) + .value("VPERMPDZmikz", LIEF::assembly::x86::OPCODE::VPERMPDZmikz) + .value("VPERMPDZri", LIEF::assembly::x86::OPCODE::VPERMPDZri) + .value("VPERMPDZrik", LIEF::assembly::x86::OPCODE::VPERMPDZrik) + .value("VPERMPDZrikz", LIEF::assembly::x86::OPCODE::VPERMPDZrikz) + .value("VPERMPDZrm", LIEF::assembly::x86::OPCODE::VPERMPDZrm) + .value("VPERMPDZrmb", LIEF::assembly::x86::OPCODE::VPERMPDZrmb) + .value("VPERMPDZrmbk", LIEF::assembly::x86::OPCODE::VPERMPDZrmbk) + .value("VPERMPDZrmbkz", LIEF::assembly::x86::OPCODE::VPERMPDZrmbkz) + .value("VPERMPDZrmk", LIEF::assembly::x86::OPCODE::VPERMPDZrmk) + .value("VPERMPDZrmkz", LIEF::assembly::x86::OPCODE::VPERMPDZrmkz) + .value("VPERMPDZrr", LIEF::assembly::x86::OPCODE::VPERMPDZrr) + .value("VPERMPDZrrk", LIEF::assembly::x86::OPCODE::VPERMPDZrrk) + .value("VPERMPDZrrkz", LIEF::assembly::x86::OPCODE::VPERMPDZrrkz) + .value("VPERMPSYrm", LIEF::assembly::x86::OPCODE::VPERMPSYrm) + .value("VPERMPSYrr", LIEF::assembly::x86::OPCODE::VPERMPSYrr) + .value("VPERMPSZ256rm", LIEF::assembly::x86::OPCODE::VPERMPSZ256rm) + .value("VPERMPSZ256rmb", LIEF::assembly::x86::OPCODE::VPERMPSZ256rmb) + .value("VPERMPSZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMPSZ256rmbk) + .value("VPERMPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMPSZ256rmbkz) + .value("VPERMPSZ256rmk", LIEF::assembly::x86::OPCODE::VPERMPSZ256rmk) + .value("VPERMPSZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMPSZ256rmkz) + .value("VPERMPSZ256rr", LIEF::assembly::x86::OPCODE::VPERMPSZ256rr) + .value("VPERMPSZ256rrk", LIEF::assembly::x86::OPCODE::VPERMPSZ256rrk) + .value("VPERMPSZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMPSZ256rrkz) + .value("VPERMPSZrm", LIEF::assembly::x86::OPCODE::VPERMPSZrm) + .value("VPERMPSZrmb", LIEF::assembly::x86::OPCODE::VPERMPSZrmb) + .value("VPERMPSZrmbk", LIEF::assembly::x86::OPCODE::VPERMPSZrmbk) + .value("VPERMPSZrmbkz", LIEF::assembly::x86::OPCODE::VPERMPSZrmbkz) + .value("VPERMPSZrmk", LIEF::assembly::x86::OPCODE::VPERMPSZrmk) + .value("VPERMPSZrmkz", LIEF::assembly::x86::OPCODE::VPERMPSZrmkz) + .value("VPERMPSZrr", LIEF::assembly::x86::OPCODE::VPERMPSZrr) + .value("VPERMPSZrrk", LIEF::assembly::x86::OPCODE::VPERMPSZrrk) + .value("VPERMPSZrrkz", LIEF::assembly::x86::OPCODE::VPERMPSZrrkz) + .value("VPERMQYmi", LIEF::assembly::x86::OPCODE::VPERMQYmi) + .value("VPERMQYri", LIEF::assembly::x86::OPCODE::VPERMQYri) + .value("VPERMQZ256mbi", LIEF::assembly::x86::OPCODE::VPERMQZ256mbi) + .value("VPERMQZ256mbik", LIEF::assembly::x86::OPCODE::VPERMQZ256mbik) + .value("VPERMQZ256mbikz", LIEF::assembly::x86::OPCODE::VPERMQZ256mbikz) + .value("VPERMQZ256mi", LIEF::assembly::x86::OPCODE::VPERMQZ256mi) + .value("VPERMQZ256mik", LIEF::assembly::x86::OPCODE::VPERMQZ256mik) + .value("VPERMQZ256mikz", LIEF::assembly::x86::OPCODE::VPERMQZ256mikz) + .value("VPERMQZ256ri", LIEF::assembly::x86::OPCODE::VPERMQZ256ri) + .value("VPERMQZ256rik", LIEF::assembly::x86::OPCODE::VPERMQZ256rik) + .value("VPERMQZ256rikz", LIEF::assembly::x86::OPCODE::VPERMQZ256rikz) + .value("VPERMQZ256rm", LIEF::assembly::x86::OPCODE::VPERMQZ256rm) + .value("VPERMQZ256rmb", LIEF::assembly::x86::OPCODE::VPERMQZ256rmb) + .value("VPERMQZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMQZ256rmbk) + .value("VPERMQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMQZ256rmbkz) + .value("VPERMQZ256rmk", LIEF::assembly::x86::OPCODE::VPERMQZ256rmk) + .value("VPERMQZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMQZ256rmkz) + .value("VPERMQZ256rr", LIEF::assembly::x86::OPCODE::VPERMQZ256rr) + .value("VPERMQZ256rrk", LIEF::assembly::x86::OPCODE::VPERMQZ256rrk) + .value("VPERMQZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMQZ256rrkz) + .value("VPERMQZmbi", LIEF::assembly::x86::OPCODE::VPERMQZmbi) + .value("VPERMQZmbik", LIEF::assembly::x86::OPCODE::VPERMQZmbik) + .value("VPERMQZmbikz", LIEF::assembly::x86::OPCODE::VPERMQZmbikz) + .value("VPERMQZmi", LIEF::assembly::x86::OPCODE::VPERMQZmi) + .value("VPERMQZmik", LIEF::assembly::x86::OPCODE::VPERMQZmik) + .value("VPERMQZmikz", LIEF::assembly::x86::OPCODE::VPERMQZmikz) + .value("VPERMQZri", LIEF::assembly::x86::OPCODE::VPERMQZri) + .value("VPERMQZrik", LIEF::assembly::x86::OPCODE::VPERMQZrik) + .value("VPERMQZrikz", LIEF::assembly::x86::OPCODE::VPERMQZrikz) + .value("VPERMQZrm", LIEF::assembly::x86::OPCODE::VPERMQZrm); + opcodes.value("VPERMQZrmb", LIEF::assembly::x86::OPCODE::VPERMQZrmb) + .value("VPERMQZrmbk", LIEF::assembly::x86::OPCODE::VPERMQZrmbk) + .value("VPERMQZrmbkz", LIEF::assembly::x86::OPCODE::VPERMQZrmbkz) + .value("VPERMQZrmk", LIEF::assembly::x86::OPCODE::VPERMQZrmk) + .value("VPERMQZrmkz", LIEF::assembly::x86::OPCODE::VPERMQZrmkz) + .value("VPERMQZrr", LIEF::assembly::x86::OPCODE::VPERMQZrr) + .value("VPERMQZrrk", LIEF::assembly::x86::OPCODE::VPERMQZrrk) + .value("VPERMQZrrkz", LIEF::assembly::x86::OPCODE::VPERMQZrrkz) + .value("VPERMT2BZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rm) + .value("VPERMT2BZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rmk) + .value("VPERMT2BZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rmkz) + .value("VPERMT2BZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rr) + .value("VPERMT2BZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rrk) + .value("VPERMT2BZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2BZ128rrkz) + .value("VPERMT2BZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rm) + .value("VPERMT2BZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rmk) + .value("VPERMT2BZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rmkz) + .value("VPERMT2BZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rr) + .value("VPERMT2BZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rrk) + .value("VPERMT2BZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2BZ256rrkz) + .value("VPERMT2BZrm", LIEF::assembly::x86::OPCODE::VPERMT2BZrm) + .value("VPERMT2BZrmk", LIEF::assembly::x86::OPCODE::VPERMT2BZrmk) + .value("VPERMT2BZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2BZrmkz) + .value("VPERMT2BZrr", LIEF::assembly::x86::OPCODE::VPERMT2BZrr) + .value("VPERMT2BZrrk", LIEF::assembly::x86::OPCODE::VPERMT2BZrrk) + .value("VPERMT2BZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2BZrrkz) + .value("VPERMT2DZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rm) + .value("VPERMT2DZ128rmb", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rmb) + .value("VPERMT2DZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rmbk) + .value("VPERMT2DZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rmbkz) + .value("VPERMT2DZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rmk) + .value("VPERMT2DZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rmkz) + .value("VPERMT2DZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rr) + .value("VPERMT2DZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rrk) + .value("VPERMT2DZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ128rrkz) + .value("VPERMT2DZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rm) + .value("VPERMT2DZ256rmb", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rmb) + .value("VPERMT2DZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rmbk) + .value("VPERMT2DZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rmbkz) + .value("VPERMT2DZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rmk) + .value("VPERMT2DZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rmkz) + .value("VPERMT2DZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rr) + .value("VPERMT2DZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rrk) + .value("VPERMT2DZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2DZ256rrkz) + .value("VPERMT2DZrm", LIEF::assembly::x86::OPCODE::VPERMT2DZrm) + .value("VPERMT2DZrmb", LIEF::assembly::x86::OPCODE::VPERMT2DZrmb) + .value("VPERMT2DZrmbk", LIEF::assembly::x86::OPCODE::VPERMT2DZrmbk) + .value("VPERMT2DZrmbkz", LIEF::assembly::x86::OPCODE::VPERMT2DZrmbkz) + .value("VPERMT2DZrmk", LIEF::assembly::x86::OPCODE::VPERMT2DZrmk) + .value("VPERMT2DZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2DZrmkz) + .value("VPERMT2DZrr", LIEF::assembly::x86::OPCODE::VPERMT2DZrr) + .value("VPERMT2DZrrk", LIEF::assembly::x86::OPCODE::VPERMT2DZrrk) + .value("VPERMT2DZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2DZrrkz) + .value("VPERMT2PDZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rm) + .value("VPERMT2PDZ128rmb", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rmb) + .value("VPERMT2PDZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rmbk) + .value("VPERMT2PDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rmbkz) + .value("VPERMT2PDZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rmk) + .value("VPERMT2PDZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rmkz) + .value("VPERMT2PDZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rr) + .value("VPERMT2PDZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rrk) + .value("VPERMT2PDZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ128rrkz) + .value("VPERMT2PDZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rm) + .value("VPERMT2PDZ256rmb", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rmb) + .value("VPERMT2PDZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rmbk) + .value("VPERMT2PDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rmbkz) + .value("VPERMT2PDZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rmk) + .value("VPERMT2PDZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rmkz) + .value("VPERMT2PDZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rr) + .value("VPERMT2PDZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rrk) + .value("VPERMT2PDZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZ256rrkz) + .value("VPERMT2PDZrm", LIEF::assembly::x86::OPCODE::VPERMT2PDZrm) + .value("VPERMT2PDZrmb", LIEF::assembly::x86::OPCODE::VPERMT2PDZrmb) + .value("VPERMT2PDZrmbk", LIEF::assembly::x86::OPCODE::VPERMT2PDZrmbk) + .value("VPERMT2PDZrmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZrmbkz) + .value("VPERMT2PDZrmk", LIEF::assembly::x86::OPCODE::VPERMT2PDZrmk) + .value("VPERMT2PDZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZrmkz) + .value("VPERMT2PDZrr", LIEF::assembly::x86::OPCODE::VPERMT2PDZrr) + .value("VPERMT2PDZrrk", LIEF::assembly::x86::OPCODE::VPERMT2PDZrrk) + .value("VPERMT2PDZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2PDZrrkz) + .value("VPERMT2PSZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rm) + .value("VPERMT2PSZ128rmb", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rmb) + .value("VPERMT2PSZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rmbk) + .value("VPERMT2PSZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rmbkz) + .value("VPERMT2PSZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rmk) + .value("VPERMT2PSZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rmkz) + .value("VPERMT2PSZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rr) + .value("VPERMT2PSZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rrk) + .value("VPERMT2PSZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ128rrkz) + .value("VPERMT2PSZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rm) + .value("VPERMT2PSZ256rmb", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rmb) + .value("VPERMT2PSZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rmbk) + .value("VPERMT2PSZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rmbkz) + .value("VPERMT2PSZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rmk) + .value("VPERMT2PSZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rmkz) + .value("VPERMT2PSZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rr) + .value("VPERMT2PSZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rrk) + .value("VPERMT2PSZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZ256rrkz) + .value("VPERMT2PSZrm", LIEF::assembly::x86::OPCODE::VPERMT2PSZrm) + .value("VPERMT2PSZrmb", LIEF::assembly::x86::OPCODE::VPERMT2PSZrmb) + .value("VPERMT2PSZrmbk", LIEF::assembly::x86::OPCODE::VPERMT2PSZrmbk) + .value("VPERMT2PSZrmbkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZrmbkz) + .value("VPERMT2PSZrmk", LIEF::assembly::x86::OPCODE::VPERMT2PSZrmk) + .value("VPERMT2PSZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZrmkz) + .value("VPERMT2PSZrr", LIEF::assembly::x86::OPCODE::VPERMT2PSZrr) + .value("VPERMT2PSZrrk", LIEF::assembly::x86::OPCODE::VPERMT2PSZrrk) + .value("VPERMT2PSZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2PSZrrkz) + .value("VPERMT2QZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rm) + .value("VPERMT2QZ128rmb", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rmb) + .value("VPERMT2QZ128rmbk", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rmbk) + .value("VPERMT2QZ128rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rmbkz) + .value("VPERMT2QZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rmk) + .value("VPERMT2QZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rmkz) + .value("VPERMT2QZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rr) + .value("VPERMT2QZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rrk) + .value("VPERMT2QZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ128rrkz) + .value("VPERMT2QZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rm) + .value("VPERMT2QZ256rmb", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rmb) + .value("VPERMT2QZ256rmbk", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rmbk) + .value("VPERMT2QZ256rmbkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rmbkz) + .value("VPERMT2QZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rmk) + .value("VPERMT2QZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rmkz) + .value("VPERMT2QZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rr) + .value("VPERMT2QZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rrk) + .value("VPERMT2QZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2QZ256rrkz) + .value("VPERMT2QZrm", LIEF::assembly::x86::OPCODE::VPERMT2QZrm) + .value("VPERMT2QZrmb", LIEF::assembly::x86::OPCODE::VPERMT2QZrmb) + .value("VPERMT2QZrmbk", LIEF::assembly::x86::OPCODE::VPERMT2QZrmbk) + .value("VPERMT2QZrmbkz", LIEF::assembly::x86::OPCODE::VPERMT2QZrmbkz) + .value("VPERMT2QZrmk", LIEF::assembly::x86::OPCODE::VPERMT2QZrmk) + .value("VPERMT2QZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2QZrmkz) + .value("VPERMT2QZrr", LIEF::assembly::x86::OPCODE::VPERMT2QZrr) + .value("VPERMT2QZrrk", LIEF::assembly::x86::OPCODE::VPERMT2QZrrk) + .value("VPERMT2QZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2QZrrkz) + .value("VPERMT2WZ128rm", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rm) + .value("VPERMT2WZ128rmk", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rmk) + .value("VPERMT2WZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rmkz) + .value("VPERMT2WZ128rr", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rr) + .value("VPERMT2WZ128rrk", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rrk) + .value("VPERMT2WZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMT2WZ128rrkz) + .value("VPERMT2WZ256rm", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rm) + .value("VPERMT2WZ256rmk", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rmk) + .value("VPERMT2WZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rmkz) + .value("VPERMT2WZ256rr", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rr) + .value("VPERMT2WZ256rrk", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rrk) + .value("VPERMT2WZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMT2WZ256rrkz) + .value("VPERMT2WZrm", LIEF::assembly::x86::OPCODE::VPERMT2WZrm) + .value("VPERMT2WZrmk", LIEF::assembly::x86::OPCODE::VPERMT2WZrmk) + .value("VPERMT2WZrmkz", LIEF::assembly::x86::OPCODE::VPERMT2WZrmkz) + .value("VPERMT2WZrr", LIEF::assembly::x86::OPCODE::VPERMT2WZrr) + .value("VPERMT2WZrrk", LIEF::assembly::x86::OPCODE::VPERMT2WZrrk) + .value("VPERMT2WZrrkz", LIEF::assembly::x86::OPCODE::VPERMT2WZrrkz) + .value("VPERMWZ128rm", LIEF::assembly::x86::OPCODE::VPERMWZ128rm) + .value("VPERMWZ128rmk", LIEF::assembly::x86::OPCODE::VPERMWZ128rmk) + .value("VPERMWZ128rmkz", LIEF::assembly::x86::OPCODE::VPERMWZ128rmkz) + .value("VPERMWZ128rr", LIEF::assembly::x86::OPCODE::VPERMWZ128rr) + .value("VPERMWZ128rrk", LIEF::assembly::x86::OPCODE::VPERMWZ128rrk) + .value("VPERMWZ128rrkz", LIEF::assembly::x86::OPCODE::VPERMWZ128rrkz) + .value("VPERMWZ256rm", LIEF::assembly::x86::OPCODE::VPERMWZ256rm) + .value("VPERMWZ256rmk", LIEF::assembly::x86::OPCODE::VPERMWZ256rmk) + .value("VPERMWZ256rmkz", LIEF::assembly::x86::OPCODE::VPERMWZ256rmkz) + .value("VPERMWZ256rr", LIEF::assembly::x86::OPCODE::VPERMWZ256rr) + .value("VPERMWZ256rrk", LIEF::assembly::x86::OPCODE::VPERMWZ256rrk) + .value("VPERMWZ256rrkz", LIEF::assembly::x86::OPCODE::VPERMWZ256rrkz) + .value("VPERMWZrm", LIEF::assembly::x86::OPCODE::VPERMWZrm) + .value("VPERMWZrmk", LIEF::assembly::x86::OPCODE::VPERMWZrmk) + .value("VPERMWZrmkz", LIEF::assembly::x86::OPCODE::VPERMWZrmkz) + .value("VPERMWZrr", LIEF::assembly::x86::OPCODE::VPERMWZrr) + .value("VPERMWZrrk", LIEF::assembly::x86::OPCODE::VPERMWZrrk) + .value("VPERMWZrrkz", LIEF::assembly::x86::OPCODE::VPERMWZrrkz) + .value("VPEXPANDBZ128rm", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rm) + .value("VPEXPANDBZ128rmk", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rmk) + .value("VPEXPANDBZ128rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rmkz) + .value("VPEXPANDBZ128rr", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rr) + .value("VPEXPANDBZ128rrk", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rrk) + .value("VPEXPANDBZ128rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZ128rrkz) + .value("VPEXPANDBZ256rm", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rm) + .value("VPEXPANDBZ256rmk", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rmk) + .value("VPEXPANDBZ256rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rmkz) + .value("VPEXPANDBZ256rr", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rr) + .value("VPEXPANDBZ256rrk", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rrk) + .value("VPEXPANDBZ256rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZ256rrkz) + .value("VPEXPANDBZrm", LIEF::assembly::x86::OPCODE::VPEXPANDBZrm) + .value("VPEXPANDBZrmk", LIEF::assembly::x86::OPCODE::VPEXPANDBZrmk) + .value("VPEXPANDBZrmkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZrmkz) + .value("VPEXPANDBZrr", LIEF::assembly::x86::OPCODE::VPEXPANDBZrr) + .value("VPEXPANDBZrrk", LIEF::assembly::x86::OPCODE::VPEXPANDBZrrk) + .value("VPEXPANDBZrrkz", LIEF::assembly::x86::OPCODE::VPEXPANDBZrrkz) + .value("VPEXPANDDZ128rm", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rm) + .value("VPEXPANDDZ128rmk", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rmk) + .value("VPEXPANDDZ128rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rmkz) + .value("VPEXPANDDZ128rr", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rr) + .value("VPEXPANDDZ128rrk", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rrk) + .value("VPEXPANDDZ128rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZ128rrkz) + .value("VPEXPANDDZ256rm", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rm) + .value("VPEXPANDDZ256rmk", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rmk) + .value("VPEXPANDDZ256rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rmkz) + .value("VPEXPANDDZ256rr", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rr) + .value("VPEXPANDDZ256rrk", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rrk) + .value("VPEXPANDDZ256rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZ256rrkz) + .value("VPEXPANDDZrm", LIEF::assembly::x86::OPCODE::VPEXPANDDZrm) + .value("VPEXPANDDZrmk", LIEF::assembly::x86::OPCODE::VPEXPANDDZrmk) + .value("VPEXPANDDZrmkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZrmkz) + .value("VPEXPANDDZrr", LIEF::assembly::x86::OPCODE::VPEXPANDDZrr) + .value("VPEXPANDDZrrk", LIEF::assembly::x86::OPCODE::VPEXPANDDZrrk) + .value("VPEXPANDDZrrkz", LIEF::assembly::x86::OPCODE::VPEXPANDDZrrkz) + .value("VPEXPANDQZ128rm", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rm) + .value("VPEXPANDQZ128rmk", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rmk) + .value("VPEXPANDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rmkz) + .value("VPEXPANDQZ128rr", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rr) + .value("VPEXPANDQZ128rrk", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rrk) + .value("VPEXPANDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZ128rrkz) + .value("VPEXPANDQZ256rm", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rm) + .value("VPEXPANDQZ256rmk", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rmk) + .value("VPEXPANDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rmkz) + .value("VPEXPANDQZ256rr", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rr) + .value("VPEXPANDQZ256rrk", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rrk) + .value("VPEXPANDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZ256rrkz) + .value("VPEXPANDQZrm", LIEF::assembly::x86::OPCODE::VPEXPANDQZrm) + .value("VPEXPANDQZrmk", LIEF::assembly::x86::OPCODE::VPEXPANDQZrmk) + .value("VPEXPANDQZrmkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZrmkz) + .value("VPEXPANDQZrr", LIEF::assembly::x86::OPCODE::VPEXPANDQZrr) + .value("VPEXPANDQZrrk", LIEF::assembly::x86::OPCODE::VPEXPANDQZrrk) + .value("VPEXPANDQZrrkz", LIEF::assembly::x86::OPCODE::VPEXPANDQZrrkz) + .value("VPEXPANDWZ128rm", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rm) + .value("VPEXPANDWZ128rmk", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rmk) + .value("VPEXPANDWZ128rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rmkz) + .value("VPEXPANDWZ128rr", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rr) + .value("VPEXPANDWZ128rrk", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rrk) + .value("VPEXPANDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZ128rrkz) + .value("VPEXPANDWZ256rm", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rm) + .value("VPEXPANDWZ256rmk", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rmk) + .value("VPEXPANDWZ256rmkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rmkz) + .value("VPEXPANDWZ256rr", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rr) + .value("VPEXPANDWZ256rrk", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rrk) + .value("VPEXPANDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZ256rrkz) + .value("VPEXPANDWZrm", LIEF::assembly::x86::OPCODE::VPEXPANDWZrm) + .value("VPEXPANDWZrmk", LIEF::assembly::x86::OPCODE::VPEXPANDWZrmk) + .value("VPEXPANDWZrmkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZrmkz) + .value("VPEXPANDWZrr", LIEF::assembly::x86::OPCODE::VPEXPANDWZrr) + .value("VPEXPANDWZrrk", LIEF::assembly::x86::OPCODE::VPEXPANDWZrrk) + .value("VPEXPANDWZrrkz", LIEF::assembly::x86::OPCODE::VPEXPANDWZrrkz) + .value("VPEXTRBZmri", LIEF::assembly::x86::OPCODE::VPEXTRBZmri) + .value("VPEXTRBZrri", LIEF::assembly::x86::OPCODE::VPEXTRBZrri) + .value("VPEXTRBmri", LIEF::assembly::x86::OPCODE::VPEXTRBmri) + .value("VPEXTRBrri", LIEF::assembly::x86::OPCODE::VPEXTRBrri) + .value("VPEXTRDZmri", LIEF::assembly::x86::OPCODE::VPEXTRDZmri) + .value("VPEXTRDZrri", LIEF::assembly::x86::OPCODE::VPEXTRDZrri) + .value("VPEXTRDmri", LIEF::assembly::x86::OPCODE::VPEXTRDmri) + .value("VPEXTRDrri", LIEF::assembly::x86::OPCODE::VPEXTRDrri) + .value("VPEXTRQZmri", LIEF::assembly::x86::OPCODE::VPEXTRQZmri) + .value("VPEXTRQZrri", LIEF::assembly::x86::OPCODE::VPEXTRQZrri) + .value("VPEXTRQmri", LIEF::assembly::x86::OPCODE::VPEXTRQmri) + .value("VPEXTRQrri", LIEF::assembly::x86::OPCODE::VPEXTRQrri) + .value("VPEXTRWZmri", LIEF::assembly::x86::OPCODE::VPEXTRWZmri) + .value("VPEXTRWZrri", LIEF::assembly::x86::OPCODE::VPEXTRWZrri) + .value("VPEXTRWZrri_REV", LIEF::assembly::x86::OPCODE::VPEXTRWZrri_REV) + .value("VPEXTRWmri", LIEF::assembly::x86::OPCODE::VPEXTRWmri) + .value("VPEXTRWrri", LIEF::assembly::x86::OPCODE::VPEXTRWrri) + .value("VPEXTRWrri_REV", LIEF::assembly::x86::OPCODE::VPEXTRWrri_REV) + .value("VPGATHERDDYrm", LIEF::assembly::x86::OPCODE::VPGATHERDDYrm) + .value("VPGATHERDDZ128rm", LIEF::assembly::x86::OPCODE::VPGATHERDDZ128rm) + .value("VPGATHERDDZ256rm", LIEF::assembly::x86::OPCODE::VPGATHERDDZ256rm) + .value("VPGATHERDDZrm", LIEF::assembly::x86::OPCODE::VPGATHERDDZrm) + .value("VPGATHERDDrm", LIEF::assembly::x86::OPCODE::VPGATHERDDrm) + .value("VPGATHERDQYrm", LIEF::assembly::x86::OPCODE::VPGATHERDQYrm) + .value("VPGATHERDQZ128rm", LIEF::assembly::x86::OPCODE::VPGATHERDQZ128rm) + .value("VPGATHERDQZ256rm", LIEF::assembly::x86::OPCODE::VPGATHERDQZ256rm) + .value("VPGATHERDQZrm", LIEF::assembly::x86::OPCODE::VPGATHERDQZrm) + .value("VPGATHERDQrm", LIEF::assembly::x86::OPCODE::VPGATHERDQrm) + .value("VPGATHERQDYrm", LIEF::assembly::x86::OPCODE::VPGATHERQDYrm) + .value("VPGATHERQDZ128rm", LIEF::assembly::x86::OPCODE::VPGATHERQDZ128rm) + .value("VPGATHERQDZ256rm", LIEF::assembly::x86::OPCODE::VPGATHERQDZ256rm) + .value("VPGATHERQDZrm", LIEF::assembly::x86::OPCODE::VPGATHERQDZrm) + .value("VPGATHERQDrm", LIEF::assembly::x86::OPCODE::VPGATHERQDrm) + .value("VPGATHERQQYrm", LIEF::assembly::x86::OPCODE::VPGATHERQQYrm) + .value("VPGATHERQQZ128rm", LIEF::assembly::x86::OPCODE::VPGATHERQQZ128rm) + .value("VPGATHERQQZ256rm", LIEF::assembly::x86::OPCODE::VPGATHERQQZ256rm) + .value("VPGATHERQQZrm", LIEF::assembly::x86::OPCODE::VPGATHERQQZrm) + .value("VPGATHERQQrm", LIEF::assembly::x86::OPCODE::VPGATHERQQrm) + .value("VPHADDBDrm", LIEF::assembly::x86::OPCODE::VPHADDBDrm) + .value("VPHADDBDrr", LIEF::assembly::x86::OPCODE::VPHADDBDrr) + .value("VPHADDBQrm", LIEF::assembly::x86::OPCODE::VPHADDBQrm) + .value("VPHADDBQrr", LIEF::assembly::x86::OPCODE::VPHADDBQrr) + .value("VPHADDBWrm", LIEF::assembly::x86::OPCODE::VPHADDBWrm) + .value("VPHADDBWrr", LIEF::assembly::x86::OPCODE::VPHADDBWrr) + .value("VPHADDDQrm", LIEF::assembly::x86::OPCODE::VPHADDDQrm) + .value("VPHADDDQrr", LIEF::assembly::x86::OPCODE::VPHADDDQrr) + .value("VPHADDDYrm", LIEF::assembly::x86::OPCODE::VPHADDDYrm) + .value("VPHADDDYrr", LIEF::assembly::x86::OPCODE::VPHADDDYrr) + .value("VPHADDDrm", LIEF::assembly::x86::OPCODE::VPHADDDrm) + .value("VPHADDDrr", LIEF::assembly::x86::OPCODE::VPHADDDrr) + .value("VPHADDSWYrm", LIEF::assembly::x86::OPCODE::VPHADDSWYrm) + .value("VPHADDSWYrr", LIEF::assembly::x86::OPCODE::VPHADDSWYrr) + .value("VPHADDSWrm", LIEF::assembly::x86::OPCODE::VPHADDSWrm) + .value("VPHADDSWrr", LIEF::assembly::x86::OPCODE::VPHADDSWrr) + .value("VPHADDUBDrm", LIEF::assembly::x86::OPCODE::VPHADDUBDrm) + .value("VPHADDUBDrr", LIEF::assembly::x86::OPCODE::VPHADDUBDrr) + .value("VPHADDUBQrm", LIEF::assembly::x86::OPCODE::VPHADDUBQrm) + .value("VPHADDUBQrr", LIEF::assembly::x86::OPCODE::VPHADDUBQrr); + opcodes.value("VPHADDUBWrm", LIEF::assembly::x86::OPCODE::VPHADDUBWrm) + .value("VPHADDUBWrr", LIEF::assembly::x86::OPCODE::VPHADDUBWrr) + .value("VPHADDUDQrm", LIEF::assembly::x86::OPCODE::VPHADDUDQrm) + .value("VPHADDUDQrr", LIEF::assembly::x86::OPCODE::VPHADDUDQrr) + .value("VPHADDUWDrm", LIEF::assembly::x86::OPCODE::VPHADDUWDrm) + .value("VPHADDUWDrr", LIEF::assembly::x86::OPCODE::VPHADDUWDrr) + .value("VPHADDUWQrm", LIEF::assembly::x86::OPCODE::VPHADDUWQrm) + .value("VPHADDUWQrr", LIEF::assembly::x86::OPCODE::VPHADDUWQrr) + .value("VPHADDWDrm", LIEF::assembly::x86::OPCODE::VPHADDWDrm) + .value("VPHADDWDrr", LIEF::assembly::x86::OPCODE::VPHADDWDrr) + .value("VPHADDWQrm", LIEF::assembly::x86::OPCODE::VPHADDWQrm) + .value("VPHADDWQrr", LIEF::assembly::x86::OPCODE::VPHADDWQrr) + .value("VPHADDWYrm", LIEF::assembly::x86::OPCODE::VPHADDWYrm) + .value("VPHADDWYrr", LIEF::assembly::x86::OPCODE::VPHADDWYrr) + .value("VPHADDWrm", LIEF::assembly::x86::OPCODE::VPHADDWrm) + .value("VPHADDWrr", LIEF::assembly::x86::OPCODE::VPHADDWrr) + .value("VPHMINPOSUWrm", LIEF::assembly::x86::OPCODE::VPHMINPOSUWrm) + .value("VPHMINPOSUWrr", LIEF::assembly::x86::OPCODE::VPHMINPOSUWrr) + .value("VPHSUBBWrm", LIEF::assembly::x86::OPCODE::VPHSUBBWrm) + .value("VPHSUBBWrr", LIEF::assembly::x86::OPCODE::VPHSUBBWrr) + .value("VPHSUBDQrm", LIEF::assembly::x86::OPCODE::VPHSUBDQrm) + .value("VPHSUBDQrr", LIEF::assembly::x86::OPCODE::VPHSUBDQrr) + .value("VPHSUBDYrm", LIEF::assembly::x86::OPCODE::VPHSUBDYrm) + .value("VPHSUBDYrr", LIEF::assembly::x86::OPCODE::VPHSUBDYrr) + .value("VPHSUBDrm", LIEF::assembly::x86::OPCODE::VPHSUBDrm) + .value("VPHSUBDrr", LIEF::assembly::x86::OPCODE::VPHSUBDrr) + .value("VPHSUBSWYrm", LIEF::assembly::x86::OPCODE::VPHSUBSWYrm) + .value("VPHSUBSWYrr", LIEF::assembly::x86::OPCODE::VPHSUBSWYrr) + .value("VPHSUBSWrm", LIEF::assembly::x86::OPCODE::VPHSUBSWrm) + .value("VPHSUBSWrr", LIEF::assembly::x86::OPCODE::VPHSUBSWrr) + .value("VPHSUBWDrm", LIEF::assembly::x86::OPCODE::VPHSUBWDrm) + .value("VPHSUBWDrr", LIEF::assembly::x86::OPCODE::VPHSUBWDrr) + .value("VPHSUBWYrm", LIEF::assembly::x86::OPCODE::VPHSUBWYrm) + .value("VPHSUBWYrr", LIEF::assembly::x86::OPCODE::VPHSUBWYrr) + .value("VPHSUBWrm", LIEF::assembly::x86::OPCODE::VPHSUBWrm) + .value("VPHSUBWrr", LIEF::assembly::x86::OPCODE::VPHSUBWrr) + .value("VPINSRBZrmi", LIEF::assembly::x86::OPCODE::VPINSRBZrmi) + .value("VPINSRBZrri", LIEF::assembly::x86::OPCODE::VPINSRBZrri) + .value("VPINSRBrmi", LIEF::assembly::x86::OPCODE::VPINSRBrmi) + .value("VPINSRBrri", LIEF::assembly::x86::OPCODE::VPINSRBrri) + .value("VPINSRDZrmi", LIEF::assembly::x86::OPCODE::VPINSRDZrmi) + .value("VPINSRDZrri", LIEF::assembly::x86::OPCODE::VPINSRDZrri) + .value("VPINSRDrmi", LIEF::assembly::x86::OPCODE::VPINSRDrmi) + .value("VPINSRDrri", LIEF::assembly::x86::OPCODE::VPINSRDrri) + .value("VPINSRQZrmi", LIEF::assembly::x86::OPCODE::VPINSRQZrmi) + .value("VPINSRQZrri", LIEF::assembly::x86::OPCODE::VPINSRQZrri) + .value("VPINSRQrmi", LIEF::assembly::x86::OPCODE::VPINSRQrmi) + .value("VPINSRQrri", LIEF::assembly::x86::OPCODE::VPINSRQrri) + .value("VPINSRWZrmi", LIEF::assembly::x86::OPCODE::VPINSRWZrmi) + .value("VPINSRWZrri", LIEF::assembly::x86::OPCODE::VPINSRWZrri) + .value("VPINSRWrmi", LIEF::assembly::x86::OPCODE::VPINSRWrmi) + .value("VPINSRWrri", LIEF::assembly::x86::OPCODE::VPINSRWrri) + .value("VPLZCNTDZ128rm", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rm) + .value("VPLZCNTDZ128rmb", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rmb) + .value("VPLZCNTDZ128rmbk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rmbk) + .value("VPLZCNTDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rmbkz) + .value("VPLZCNTDZ128rmk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rmk) + .value("VPLZCNTDZ128rmkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rmkz) + .value("VPLZCNTDZ128rr", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rr) + .value("VPLZCNTDZ128rrk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rrk) + .value("VPLZCNTDZ128rrkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ128rrkz) + .value("VPLZCNTDZ256rm", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rm) + .value("VPLZCNTDZ256rmb", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rmb) + .value("VPLZCNTDZ256rmbk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rmbk) + .value("VPLZCNTDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rmbkz) + .value("VPLZCNTDZ256rmk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rmk) + .value("VPLZCNTDZ256rmkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rmkz) + .value("VPLZCNTDZ256rr", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rr) + .value("VPLZCNTDZ256rrk", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rrk) + .value("VPLZCNTDZ256rrkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZ256rrkz) + .value("VPLZCNTDZrm", LIEF::assembly::x86::OPCODE::VPLZCNTDZrm) + .value("VPLZCNTDZrmb", LIEF::assembly::x86::OPCODE::VPLZCNTDZrmb) + .value("VPLZCNTDZrmbk", LIEF::assembly::x86::OPCODE::VPLZCNTDZrmbk) + .value("VPLZCNTDZrmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZrmbkz) + .value("VPLZCNTDZrmk", LIEF::assembly::x86::OPCODE::VPLZCNTDZrmk) + .value("VPLZCNTDZrmkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZrmkz) + .value("VPLZCNTDZrr", LIEF::assembly::x86::OPCODE::VPLZCNTDZrr) + .value("VPLZCNTDZrrk", LIEF::assembly::x86::OPCODE::VPLZCNTDZrrk) + .value("VPLZCNTDZrrkz", LIEF::assembly::x86::OPCODE::VPLZCNTDZrrkz) + .value("VPLZCNTQZ128rm", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rm) + .value("VPLZCNTQZ128rmb", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rmb) + .value("VPLZCNTQZ128rmbk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rmbk) + .value("VPLZCNTQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rmbkz) + .value("VPLZCNTQZ128rmk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rmk) + .value("VPLZCNTQZ128rmkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rmkz) + .value("VPLZCNTQZ128rr", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rr) + .value("VPLZCNTQZ128rrk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rrk) + .value("VPLZCNTQZ128rrkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ128rrkz) + .value("VPLZCNTQZ256rm", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rm) + .value("VPLZCNTQZ256rmb", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rmb) + .value("VPLZCNTQZ256rmbk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rmbk) + .value("VPLZCNTQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rmbkz) + .value("VPLZCNTQZ256rmk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rmk) + .value("VPLZCNTQZ256rmkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rmkz) + .value("VPLZCNTQZ256rr", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rr) + .value("VPLZCNTQZ256rrk", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rrk) + .value("VPLZCNTQZ256rrkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZ256rrkz) + .value("VPLZCNTQZrm", LIEF::assembly::x86::OPCODE::VPLZCNTQZrm) + .value("VPLZCNTQZrmb", LIEF::assembly::x86::OPCODE::VPLZCNTQZrmb) + .value("VPLZCNTQZrmbk", LIEF::assembly::x86::OPCODE::VPLZCNTQZrmbk) + .value("VPLZCNTQZrmbkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZrmbkz) + .value("VPLZCNTQZrmk", LIEF::assembly::x86::OPCODE::VPLZCNTQZrmk) + .value("VPLZCNTQZrmkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZrmkz) + .value("VPLZCNTQZrr", LIEF::assembly::x86::OPCODE::VPLZCNTQZrr) + .value("VPLZCNTQZrrk", LIEF::assembly::x86::OPCODE::VPLZCNTQZrrk) + .value("VPLZCNTQZrrkz", LIEF::assembly::x86::OPCODE::VPLZCNTQZrrkz) + .value("VPMACSDDrm", LIEF::assembly::x86::OPCODE::VPMACSDDrm) + .value("VPMACSDDrr", LIEF::assembly::x86::OPCODE::VPMACSDDrr) + .value("VPMACSDQHrm", LIEF::assembly::x86::OPCODE::VPMACSDQHrm) + .value("VPMACSDQHrr", LIEF::assembly::x86::OPCODE::VPMACSDQHrr) + .value("VPMACSDQLrm", LIEF::assembly::x86::OPCODE::VPMACSDQLrm) + .value("VPMACSDQLrr", LIEF::assembly::x86::OPCODE::VPMACSDQLrr) + .value("VPMACSSDDrm", LIEF::assembly::x86::OPCODE::VPMACSSDDrm) + .value("VPMACSSDDrr", LIEF::assembly::x86::OPCODE::VPMACSSDDrr) + .value("VPMACSSDQHrm", LIEF::assembly::x86::OPCODE::VPMACSSDQHrm) + .value("VPMACSSDQHrr", LIEF::assembly::x86::OPCODE::VPMACSSDQHrr) + .value("VPMACSSDQLrm", LIEF::assembly::x86::OPCODE::VPMACSSDQLrm) + .value("VPMACSSDQLrr", LIEF::assembly::x86::OPCODE::VPMACSSDQLrr) + .value("VPMACSSWDrm", LIEF::assembly::x86::OPCODE::VPMACSSWDrm) + .value("VPMACSSWDrr", LIEF::assembly::x86::OPCODE::VPMACSSWDrr) + .value("VPMACSSWWrm", LIEF::assembly::x86::OPCODE::VPMACSSWWrm) + .value("VPMACSSWWrr", LIEF::assembly::x86::OPCODE::VPMACSSWWrr) + .value("VPMACSWDrm", LIEF::assembly::x86::OPCODE::VPMACSWDrm) + .value("VPMACSWDrr", LIEF::assembly::x86::OPCODE::VPMACSWDrr) + .value("VPMACSWWrm", LIEF::assembly::x86::OPCODE::VPMACSWWrm) + .value("VPMACSWWrr", LIEF::assembly::x86::OPCODE::VPMACSWWrr) + .value("VPMADCSSWDrm", LIEF::assembly::x86::OPCODE::VPMADCSSWDrm) + .value("VPMADCSSWDrr", LIEF::assembly::x86::OPCODE::VPMADCSSWDrr) + .value("VPMADCSWDrm", LIEF::assembly::x86::OPCODE::VPMADCSWDrm) + .value("VPMADCSWDrr", LIEF::assembly::x86::OPCODE::VPMADCSWDrr) + .value("VPMADD52HUQYrm", LIEF::assembly::x86::OPCODE::VPMADD52HUQYrm) + .value("VPMADD52HUQYrr", LIEF::assembly::x86::OPCODE::VPMADD52HUQYrr) + .value("VPMADD52HUQZ128m", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128m) + .value("VPMADD52HUQZ128mb", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128mb) + .value("VPMADD52HUQZ128mbk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128mbk) + .value("VPMADD52HUQZ128mbkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128mbkz) + .value("VPMADD52HUQZ128mk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128mk) + .value("VPMADD52HUQZ128mkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128mkz) + .value("VPMADD52HUQZ128r", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128r) + .value("VPMADD52HUQZ128rk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128rk) + .value("VPMADD52HUQZ128rkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ128rkz) + .value("VPMADD52HUQZ256m", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256m) + .value("VPMADD52HUQZ256mb", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256mb) + .value("VPMADD52HUQZ256mbk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256mbk) + .value("VPMADD52HUQZ256mbkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256mbkz) + .value("VPMADD52HUQZ256mk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256mk) + .value("VPMADD52HUQZ256mkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256mkz) + .value("VPMADD52HUQZ256r", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256r) + .value("VPMADD52HUQZ256rk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256rk) + .value("VPMADD52HUQZ256rkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZ256rkz) + .value("VPMADD52HUQZm", LIEF::assembly::x86::OPCODE::VPMADD52HUQZm) + .value("VPMADD52HUQZmb", LIEF::assembly::x86::OPCODE::VPMADD52HUQZmb) + .value("VPMADD52HUQZmbk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZmbk) + .value("VPMADD52HUQZmbkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZmbkz) + .value("VPMADD52HUQZmk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZmk) + .value("VPMADD52HUQZmkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZmkz) + .value("VPMADD52HUQZr", LIEF::assembly::x86::OPCODE::VPMADD52HUQZr) + .value("VPMADD52HUQZrk", LIEF::assembly::x86::OPCODE::VPMADD52HUQZrk) + .value("VPMADD52HUQZrkz", LIEF::assembly::x86::OPCODE::VPMADD52HUQZrkz) + .value("VPMADD52HUQrm", LIEF::assembly::x86::OPCODE::VPMADD52HUQrm) + .value("VPMADD52HUQrr", LIEF::assembly::x86::OPCODE::VPMADD52HUQrr) + .value("VPMADD52LUQYrm", LIEF::assembly::x86::OPCODE::VPMADD52LUQYrm) + .value("VPMADD52LUQYrr", LIEF::assembly::x86::OPCODE::VPMADD52LUQYrr) + .value("VPMADD52LUQZ128m", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128m) + .value("VPMADD52LUQZ128mb", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128mb) + .value("VPMADD52LUQZ128mbk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128mbk) + .value("VPMADD52LUQZ128mbkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128mbkz) + .value("VPMADD52LUQZ128mk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128mk) + .value("VPMADD52LUQZ128mkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128mkz) + .value("VPMADD52LUQZ128r", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128r) + .value("VPMADD52LUQZ128rk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128rk) + .value("VPMADD52LUQZ128rkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ128rkz) + .value("VPMADD52LUQZ256m", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256m) + .value("VPMADD52LUQZ256mb", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256mb) + .value("VPMADD52LUQZ256mbk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256mbk) + .value("VPMADD52LUQZ256mbkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256mbkz) + .value("VPMADD52LUQZ256mk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256mk) + .value("VPMADD52LUQZ256mkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256mkz) + .value("VPMADD52LUQZ256r", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256r) + .value("VPMADD52LUQZ256rk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256rk) + .value("VPMADD52LUQZ256rkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZ256rkz) + .value("VPMADD52LUQZm", LIEF::assembly::x86::OPCODE::VPMADD52LUQZm) + .value("VPMADD52LUQZmb", LIEF::assembly::x86::OPCODE::VPMADD52LUQZmb) + .value("VPMADD52LUQZmbk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZmbk) + .value("VPMADD52LUQZmbkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZmbkz) + .value("VPMADD52LUQZmk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZmk) + .value("VPMADD52LUQZmkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZmkz) + .value("VPMADD52LUQZr", LIEF::assembly::x86::OPCODE::VPMADD52LUQZr) + .value("VPMADD52LUQZrk", LIEF::assembly::x86::OPCODE::VPMADD52LUQZrk) + .value("VPMADD52LUQZrkz", LIEF::assembly::x86::OPCODE::VPMADD52LUQZrkz) + .value("VPMADD52LUQrm", LIEF::assembly::x86::OPCODE::VPMADD52LUQrm) + .value("VPMADD52LUQrr", LIEF::assembly::x86::OPCODE::VPMADD52LUQrr) + .value("VPMADDUBSWYrm", LIEF::assembly::x86::OPCODE::VPMADDUBSWYrm) + .value("VPMADDUBSWYrr", LIEF::assembly::x86::OPCODE::VPMADDUBSWYrr) + .value("VPMADDUBSWZ128rm", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rm) + .value("VPMADDUBSWZ128rmk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rmk) + .value("VPMADDUBSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rmkz) + .value("VPMADDUBSWZ128rr", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rr) + .value("VPMADDUBSWZ128rrk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rrk) + .value("VPMADDUBSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ128rrkz) + .value("VPMADDUBSWZ256rm", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rm) + .value("VPMADDUBSWZ256rmk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rmk) + .value("VPMADDUBSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rmkz) + .value("VPMADDUBSWZ256rr", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rr) + .value("VPMADDUBSWZ256rrk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rrk) + .value("VPMADDUBSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZ256rrkz) + .value("VPMADDUBSWZrm", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrm) + .value("VPMADDUBSWZrmk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrmk) + .value("VPMADDUBSWZrmkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrmkz) + .value("VPMADDUBSWZrr", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrr) + .value("VPMADDUBSWZrrk", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrrk) + .value("VPMADDUBSWZrrkz", LIEF::assembly::x86::OPCODE::VPMADDUBSWZrrkz) + .value("VPMADDUBSWrm", LIEF::assembly::x86::OPCODE::VPMADDUBSWrm) + .value("VPMADDUBSWrr", LIEF::assembly::x86::OPCODE::VPMADDUBSWrr) + .value("VPMADDWDYrm", LIEF::assembly::x86::OPCODE::VPMADDWDYrm) + .value("VPMADDWDYrr", LIEF::assembly::x86::OPCODE::VPMADDWDYrr) + .value("VPMADDWDZ128rm", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rm) + .value("VPMADDWDZ128rmk", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rmk) + .value("VPMADDWDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rmkz) + .value("VPMADDWDZ128rr", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rr) + .value("VPMADDWDZ128rrk", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rrk) + .value("VPMADDWDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMADDWDZ128rrkz) + .value("VPMADDWDZ256rm", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rm) + .value("VPMADDWDZ256rmk", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rmk) + .value("VPMADDWDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rmkz) + .value("VPMADDWDZ256rr", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rr) + .value("VPMADDWDZ256rrk", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rrk) + .value("VPMADDWDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMADDWDZ256rrkz) + .value("VPMADDWDZrm", LIEF::assembly::x86::OPCODE::VPMADDWDZrm) + .value("VPMADDWDZrmk", LIEF::assembly::x86::OPCODE::VPMADDWDZrmk) + .value("VPMADDWDZrmkz", LIEF::assembly::x86::OPCODE::VPMADDWDZrmkz) + .value("VPMADDWDZrr", LIEF::assembly::x86::OPCODE::VPMADDWDZrr) + .value("VPMADDWDZrrk", LIEF::assembly::x86::OPCODE::VPMADDWDZrrk) + .value("VPMADDWDZrrkz", LIEF::assembly::x86::OPCODE::VPMADDWDZrrkz) + .value("VPMADDWDrm", LIEF::assembly::x86::OPCODE::VPMADDWDrm) + .value("VPMADDWDrr", LIEF::assembly::x86::OPCODE::VPMADDWDrr) + .value("VPMASKMOVDYmr", LIEF::assembly::x86::OPCODE::VPMASKMOVDYmr) + .value("VPMASKMOVDYrm", LIEF::assembly::x86::OPCODE::VPMASKMOVDYrm) + .value("VPMASKMOVDmr", LIEF::assembly::x86::OPCODE::VPMASKMOVDmr) + .value("VPMASKMOVDrm", LIEF::assembly::x86::OPCODE::VPMASKMOVDrm) + .value("VPMASKMOVQYmr", LIEF::assembly::x86::OPCODE::VPMASKMOVQYmr) + .value("VPMASKMOVQYrm", LIEF::assembly::x86::OPCODE::VPMASKMOVQYrm) + .value("VPMASKMOVQmr", LIEF::assembly::x86::OPCODE::VPMASKMOVQmr) + .value("VPMASKMOVQrm", LIEF::assembly::x86::OPCODE::VPMASKMOVQrm) + .value("VPMAXSBYrm", LIEF::assembly::x86::OPCODE::VPMAXSBYrm) + .value("VPMAXSBYrr", LIEF::assembly::x86::OPCODE::VPMAXSBYrr) + .value("VPMAXSBZ128rm", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rm) + .value("VPMAXSBZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rmk) + .value("VPMAXSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rmkz) + .value("VPMAXSBZ128rr", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rr) + .value("VPMAXSBZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rrk) + .value("VPMAXSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXSBZ128rrkz) + .value("VPMAXSBZ256rm", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rm) + .value("VPMAXSBZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rmk) + .value("VPMAXSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rmkz) + .value("VPMAXSBZ256rr", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rr) + .value("VPMAXSBZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rrk) + .value("VPMAXSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXSBZ256rrkz) + .value("VPMAXSBZrm", LIEF::assembly::x86::OPCODE::VPMAXSBZrm) + .value("VPMAXSBZrmk", LIEF::assembly::x86::OPCODE::VPMAXSBZrmk) + .value("VPMAXSBZrmkz", LIEF::assembly::x86::OPCODE::VPMAXSBZrmkz) + .value("VPMAXSBZrr", LIEF::assembly::x86::OPCODE::VPMAXSBZrr) + .value("VPMAXSBZrrk", LIEF::assembly::x86::OPCODE::VPMAXSBZrrk) + .value("VPMAXSBZrrkz", LIEF::assembly::x86::OPCODE::VPMAXSBZrrkz) + .value("VPMAXSBrm", LIEF::assembly::x86::OPCODE::VPMAXSBrm) + .value("VPMAXSBrr", LIEF::assembly::x86::OPCODE::VPMAXSBrr) + .value("VPMAXSDYrm", LIEF::assembly::x86::OPCODE::VPMAXSDYrm) + .value("VPMAXSDYrr", LIEF::assembly::x86::OPCODE::VPMAXSDYrr) + .value("VPMAXSDZ128rm", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rm) + .value("VPMAXSDZ128rmb", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rmb) + .value("VPMAXSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rmbk) + .value("VPMAXSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rmbkz) + .value("VPMAXSDZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rmk) + .value("VPMAXSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rmkz) + .value("VPMAXSDZ128rr", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rr) + .value("VPMAXSDZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rrk) + .value("VPMAXSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ128rrkz) + .value("VPMAXSDZ256rm", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rm) + .value("VPMAXSDZ256rmb", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rmb) + .value("VPMAXSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rmbk) + .value("VPMAXSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rmbkz) + .value("VPMAXSDZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rmk) + .value("VPMAXSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rmkz) + .value("VPMAXSDZ256rr", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rr) + .value("VPMAXSDZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rrk) + .value("VPMAXSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXSDZ256rrkz) + .value("VPMAXSDZrm", LIEF::assembly::x86::OPCODE::VPMAXSDZrm) + .value("VPMAXSDZrmb", LIEF::assembly::x86::OPCODE::VPMAXSDZrmb) + .value("VPMAXSDZrmbk", LIEF::assembly::x86::OPCODE::VPMAXSDZrmbk) + .value("VPMAXSDZrmbkz", LIEF::assembly::x86::OPCODE::VPMAXSDZrmbkz) + .value("VPMAXSDZrmk", LIEF::assembly::x86::OPCODE::VPMAXSDZrmk) + .value("VPMAXSDZrmkz", LIEF::assembly::x86::OPCODE::VPMAXSDZrmkz) + .value("VPMAXSDZrr", LIEF::assembly::x86::OPCODE::VPMAXSDZrr) + .value("VPMAXSDZrrk", LIEF::assembly::x86::OPCODE::VPMAXSDZrrk) + .value("VPMAXSDZrrkz", LIEF::assembly::x86::OPCODE::VPMAXSDZrrkz) + .value("VPMAXSDrm", LIEF::assembly::x86::OPCODE::VPMAXSDrm) + .value("VPMAXSDrr", LIEF::assembly::x86::OPCODE::VPMAXSDrr) + .value("VPMAXSQZ128rm", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rm) + .value("VPMAXSQZ128rmb", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rmb) + .value("VPMAXSQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rmbk); + opcodes.value("VPMAXSQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rmbkz) + .value("VPMAXSQZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rmk) + .value("VPMAXSQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rmkz) + .value("VPMAXSQZ128rr", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rr) + .value("VPMAXSQZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rrk) + .value("VPMAXSQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ128rrkz) + .value("VPMAXSQZ256rm", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rm) + .value("VPMAXSQZ256rmb", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rmb) + .value("VPMAXSQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rmbk) + .value("VPMAXSQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rmbkz) + .value("VPMAXSQZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rmk) + .value("VPMAXSQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rmkz) + .value("VPMAXSQZ256rr", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rr) + .value("VPMAXSQZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rrk) + .value("VPMAXSQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXSQZ256rrkz) + .value("VPMAXSQZrm", LIEF::assembly::x86::OPCODE::VPMAXSQZrm) + .value("VPMAXSQZrmb", LIEF::assembly::x86::OPCODE::VPMAXSQZrmb) + .value("VPMAXSQZrmbk", LIEF::assembly::x86::OPCODE::VPMAXSQZrmbk) + .value("VPMAXSQZrmbkz", LIEF::assembly::x86::OPCODE::VPMAXSQZrmbkz) + .value("VPMAXSQZrmk", LIEF::assembly::x86::OPCODE::VPMAXSQZrmk) + .value("VPMAXSQZrmkz", LIEF::assembly::x86::OPCODE::VPMAXSQZrmkz) + .value("VPMAXSQZrr", LIEF::assembly::x86::OPCODE::VPMAXSQZrr) + .value("VPMAXSQZrrk", LIEF::assembly::x86::OPCODE::VPMAXSQZrrk) + .value("VPMAXSQZrrkz", LIEF::assembly::x86::OPCODE::VPMAXSQZrrkz) + .value("VPMAXSWYrm", LIEF::assembly::x86::OPCODE::VPMAXSWYrm) + .value("VPMAXSWYrr", LIEF::assembly::x86::OPCODE::VPMAXSWYrr) + .value("VPMAXSWZ128rm", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rm) + .value("VPMAXSWZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rmk) + .value("VPMAXSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rmkz) + .value("VPMAXSWZ128rr", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rr) + .value("VPMAXSWZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rrk) + .value("VPMAXSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXSWZ128rrkz) + .value("VPMAXSWZ256rm", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rm) + .value("VPMAXSWZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rmk) + .value("VPMAXSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rmkz) + .value("VPMAXSWZ256rr", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rr) + .value("VPMAXSWZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rrk) + .value("VPMAXSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXSWZ256rrkz) + .value("VPMAXSWZrm", LIEF::assembly::x86::OPCODE::VPMAXSWZrm) + .value("VPMAXSWZrmk", LIEF::assembly::x86::OPCODE::VPMAXSWZrmk) + .value("VPMAXSWZrmkz", LIEF::assembly::x86::OPCODE::VPMAXSWZrmkz) + .value("VPMAXSWZrr", LIEF::assembly::x86::OPCODE::VPMAXSWZrr) + .value("VPMAXSWZrrk", LIEF::assembly::x86::OPCODE::VPMAXSWZrrk) + .value("VPMAXSWZrrkz", LIEF::assembly::x86::OPCODE::VPMAXSWZrrkz) + .value("VPMAXSWrm", LIEF::assembly::x86::OPCODE::VPMAXSWrm) + .value("VPMAXSWrr", LIEF::assembly::x86::OPCODE::VPMAXSWrr) + .value("VPMAXUBYrm", LIEF::assembly::x86::OPCODE::VPMAXUBYrm) + .value("VPMAXUBYrr", LIEF::assembly::x86::OPCODE::VPMAXUBYrr) + .value("VPMAXUBZ128rm", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rm) + .value("VPMAXUBZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rmk) + .value("VPMAXUBZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rmkz) + .value("VPMAXUBZ128rr", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rr) + .value("VPMAXUBZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rrk) + .value("VPMAXUBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXUBZ128rrkz) + .value("VPMAXUBZ256rm", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rm) + .value("VPMAXUBZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rmk) + .value("VPMAXUBZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rmkz) + .value("VPMAXUBZ256rr", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rr) + .value("VPMAXUBZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rrk) + .value("VPMAXUBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXUBZ256rrkz) + .value("VPMAXUBZrm", LIEF::assembly::x86::OPCODE::VPMAXUBZrm) + .value("VPMAXUBZrmk", LIEF::assembly::x86::OPCODE::VPMAXUBZrmk) + .value("VPMAXUBZrmkz", LIEF::assembly::x86::OPCODE::VPMAXUBZrmkz) + .value("VPMAXUBZrr", LIEF::assembly::x86::OPCODE::VPMAXUBZrr) + .value("VPMAXUBZrrk", LIEF::assembly::x86::OPCODE::VPMAXUBZrrk) + .value("VPMAXUBZrrkz", LIEF::assembly::x86::OPCODE::VPMAXUBZrrkz) + .value("VPMAXUBrm", LIEF::assembly::x86::OPCODE::VPMAXUBrm) + .value("VPMAXUBrr", LIEF::assembly::x86::OPCODE::VPMAXUBrr) + .value("VPMAXUDYrm", LIEF::assembly::x86::OPCODE::VPMAXUDYrm) + .value("VPMAXUDYrr", LIEF::assembly::x86::OPCODE::VPMAXUDYrr) + .value("VPMAXUDZ128rm", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rm) + .value("VPMAXUDZ128rmb", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rmb) + .value("VPMAXUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rmbk) + .value("VPMAXUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rmbkz) + .value("VPMAXUDZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rmk) + .value("VPMAXUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rmkz) + .value("VPMAXUDZ128rr", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rr) + .value("VPMAXUDZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rrk) + .value("VPMAXUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ128rrkz) + .value("VPMAXUDZ256rm", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rm) + .value("VPMAXUDZ256rmb", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rmb) + .value("VPMAXUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rmbk) + .value("VPMAXUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rmbkz) + .value("VPMAXUDZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rmk) + .value("VPMAXUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rmkz) + .value("VPMAXUDZ256rr", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rr) + .value("VPMAXUDZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rrk) + .value("VPMAXUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXUDZ256rrkz) + .value("VPMAXUDZrm", LIEF::assembly::x86::OPCODE::VPMAXUDZrm) + .value("VPMAXUDZrmb", LIEF::assembly::x86::OPCODE::VPMAXUDZrmb) + .value("VPMAXUDZrmbk", LIEF::assembly::x86::OPCODE::VPMAXUDZrmbk) + .value("VPMAXUDZrmbkz", LIEF::assembly::x86::OPCODE::VPMAXUDZrmbkz) + .value("VPMAXUDZrmk", LIEF::assembly::x86::OPCODE::VPMAXUDZrmk) + .value("VPMAXUDZrmkz", LIEF::assembly::x86::OPCODE::VPMAXUDZrmkz) + .value("VPMAXUDZrr", LIEF::assembly::x86::OPCODE::VPMAXUDZrr) + .value("VPMAXUDZrrk", LIEF::assembly::x86::OPCODE::VPMAXUDZrrk) + .value("VPMAXUDZrrkz", LIEF::assembly::x86::OPCODE::VPMAXUDZrrkz) + .value("VPMAXUDrm", LIEF::assembly::x86::OPCODE::VPMAXUDrm) + .value("VPMAXUDrr", LIEF::assembly::x86::OPCODE::VPMAXUDrr) + .value("VPMAXUQZ128rm", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rm) + .value("VPMAXUQZ128rmb", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rmb) + .value("VPMAXUQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rmbk) + .value("VPMAXUQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rmbkz) + .value("VPMAXUQZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rmk) + .value("VPMAXUQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rmkz) + .value("VPMAXUQZ128rr", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rr) + .value("VPMAXUQZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rrk) + .value("VPMAXUQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ128rrkz) + .value("VPMAXUQZ256rm", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rm) + .value("VPMAXUQZ256rmb", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rmb) + .value("VPMAXUQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rmbk) + .value("VPMAXUQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rmbkz) + .value("VPMAXUQZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rmk) + .value("VPMAXUQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rmkz) + .value("VPMAXUQZ256rr", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rr) + .value("VPMAXUQZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rrk) + .value("VPMAXUQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXUQZ256rrkz) + .value("VPMAXUQZrm", LIEF::assembly::x86::OPCODE::VPMAXUQZrm) + .value("VPMAXUQZrmb", LIEF::assembly::x86::OPCODE::VPMAXUQZrmb) + .value("VPMAXUQZrmbk", LIEF::assembly::x86::OPCODE::VPMAXUQZrmbk) + .value("VPMAXUQZrmbkz", LIEF::assembly::x86::OPCODE::VPMAXUQZrmbkz) + .value("VPMAXUQZrmk", LIEF::assembly::x86::OPCODE::VPMAXUQZrmk) + .value("VPMAXUQZrmkz", LIEF::assembly::x86::OPCODE::VPMAXUQZrmkz) + .value("VPMAXUQZrr", LIEF::assembly::x86::OPCODE::VPMAXUQZrr) + .value("VPMAXUQZrrk", LIEF::assembly::x86::OPCODE::VPMAXUQZrrk) + .value("VPMAXUQZrrkz", LIEF::assembly::x86::OPCODE::VPMAXUQZrrkz) + .value("VPMAXUWYrm", LIEF::assembly::x86::OPCODE::VPMAXUWYrm) + .value("VPMAXUWYrr", LIEF::assembly::x86::OPCODE::VPMAXUWYrr) + .value("VPMAXUWZ128rm", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rm) + .value("VPMAXUWZ128rmk", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rmk) + .value("VPMAXUWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rmkz) + .value("VPMAXUWZ128rr", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rr) + .value("VPMAXUWZ128rrk", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rrk) + .value("VPMAXUWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMAXUWZ128rrkz) + .value("VPMAXUWZ256rm", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rm) + .value("VPMAXUWZ256rmk", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rmk) + .value("VPMAXUWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rmkz) + .value("VPMAXUWZ256rr", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rr) + .value("VPMAXUWZ256rrk", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rrk) + .value("VPMAXUWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMAXUWZ256rrkz) + .value("VPMAXUWZrm", LIEF::assembly::x86::OPCODE::VPMAXUWZrm) + .value("VPMAXUWZrmk", LIEF::assembly::x86::OPCODE::VPMAXUWZrmk) + .value("VPMAXUWZrmkz", LIEF::assembly::x86::OPCODE::VPMAXUWZrmkz) + .value("VPMAXUWZrr", LIEF::assembly::x86::OPCODE::VPMAXUWZrr) + .value("VPMAXUWZrrk", LIEF::assembly::x86::OPCODE::VPMAXUWZrrk) + .value("VPMAXUWZrrkz", LIEF::assembly::x86::OPCODE::VPMAXUWZrrkz) + .value("VPMAXUWrm", LIEF::assembly::x86::OPCODE::VPMAXUWrm) + .value("VPMAXUWrr", LIEF::assembly::x86::OPCODE::VPMAXUWrr) + .value("VPMINSBYrm", LIEF::assembly::x86::OPCODE::VPMINSBYrm) + .value("VPMINSBYrr", LIEF::assembly::x86::OPCODE::VPMINSBYrr) + .value("VPMINSBZ128rm", LIEF::assembly::x86::OPCODE::VPMINSBZ128rm) + .value("VPMINSBZ128rmk", LIEF::assembly::x86::OPCODE::VPMINSBZ128rmk) + .value("VPMINSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINSBZ128rmkz) + .value("VPMINSBZ128rr", LIEF::assembly::x86::OPCODE::VPMINSBZ128rr) + .value("VPMINSBZ128rrk", LIEF::assembly::x86::OPCODE::VPMINSBZ128rrk) + .value("VPMINSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINSBZ128rrkz) + .value("VPMINSBZ256rm", LIEF::assembly::x86::OPCODE::VPMINSBZ256rm) + .value("VPMINSBZ256rmk", LIEF::assembly::x86::OPCODE::VPMINSBZ256rmk) + .value("VPMINSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINSBZ256rmkz) + .value("VPMINSBZ256rr", LIEF::assembly::x86::OPCODE::VPMINSBZ256rr) + .value("VPMINSBZ256rrk", LIEF::assembly::x86::OPCODE::VPMINSBZ256rrk) + .value("VPMINSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINSBZ256rrkz) + .value("VPMINSBZrm", LIEF::assembly::x86::OPCODE::VPMINSBZrm) + .value("VPMINSBZrmk", LIEF::assembly::x86::OPCODE::VPMINSBZrmk) + .value("VPMINSBZrmkz", LIEF::assembly::x86::OPCODE::VPMINSBZrmkz) + .value("VPMINSBZrr", LIEF::assembly::x86::OPCODE::VPMINSBZrr) + .value("VPMINSBZrrk", LIEF::assembly::x86::OPCODE::VPMINSBZrrk) + .value("VPMINSBZrrkz", LIEF::assembly::x86::OPCODE::VPMINSBZrrkz) + .value("VPMINSBrm", LIEF::assembly::x86::OPCODE::VPMINSBrm) + .value("VPMINSBrr", LIEF::assembly::x86::OPCODE::VPMINSBrr) + .value("VPMINSDYrm", LIEF::assembly::x86::OPCODE::VPMINSDYrm) + .value("VPMINSDYrr", LIEF::assembly::x86::OPCODE::VPMINSDYrr) + .value("VPMINSDZ128rm", LIEF::assembly::x86::OPCODE::VPMINSDZ128rm) + .value("VPMINSDZ128rmb", LIEF::assembly::x86::OPCODE::VPMINSDZ128rmb) + .value("VPMINSDZ128rmbk", LIEF::assembly::x86::OPCODE::VPMINSDZ128rmbk) + .value("VPMINSDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMINSDZ128rmbkz) + .value("VPMINSDZ128rmk", LIEF::assembly::x86::OPCODE::VPMINSDZ128rmk) + .value("VPMINSDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINSDZ128rmkz) + .value("VPMINSDZ128rr", LIEF::assembly::x86::OPCODE::VPMINSDZ128rr) + .value("VPMINSDZ128rrk", LIEF::assembly::x86::OPCODE::VPMINSDZ128rrk) + .value("VPMINSDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINSDZ128rrkz) + .value("VPMINSDZ256rm", LIEF::assembly::x86::OPCODE::VPMINSDZ256rm) + .value("VPMINSDZ256rmb", LIEF::assembly::x86::OPCODE::VPMINSDZ256rmb) + .value("VPMINSDZ256rmbk", LIEF::assembly::x86::OPCODE::VPMINSDZ256rmbk) + .value("VPMINSDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMINSDZ256rmbkz) + .value("VPMINSDZ256rmk", LIEF::assembly::x86::OPCODE::VPMINSDZ256rmk) + .value("VPMINSDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINSDZ256rmkz) + .value("VPMINSDZ256rr", LIEF::assembly::x86::OPCODE::VPMINSDZ256rr) + .value("VPMINSDZ256rrk", LIEF::assembly::x86::OPCODE::VPMINSDZ256rrk) + .value("VPMINSDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINSDZ256rrkz) + .value("VPMINSDZrm", LIEF::assembly::x86::OPCODE::VPMINSDZrm) + .value("VPMINSDZrmb", LIEF::assembly::x86::OPCODE::VPMINSDZrmb) + .value("VPMINSDZrmbk", LIEF::assembly::x86::OPCODE::VPMINSDZrmbk) + .value("VPMINSDZrmbkz", LIEF::assembly::x86::OPCODE::VPMINSDZrmbkz) + .value("VPMINSDZrmk", LIEF::assembly::x86::OPCODE::VPMINSDZrmk) + .value("VPMINSDZrmkz", LIEF::assembly::x86::OPCODE::VPMINSDZrmkz) + .value("VPMINSDZrr", LIEF::assembly::x86::OPCODE::VPMINSDZrr) + .value("VPMINSDZrrk", LIEF::assembly::x86::OPCODE::VPMINSDZrrk) + .value("VPMINSDZrrkz", LIEF::assembly::x86::OPCODE::VPMINSDZrrkz) + .value("VPMINSDrm", LIEF::assembly::x86::OPCODE::VPMINSDrm) + .value("VPMINSDrr", LIEF::assembly::x86::OPCODE::VPMINSDrr) + .value("VPMINSQZ128rm", LIEF::assembly::x86::OPCODE::VPMINSQZ128rm) + .value("VPMINSQZ128rmb", LIEF::assembly::x86::OPCODE::VPMINSQZ128rmb) + .value("VPMINSQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMINSQZ128rmbk) + .value("VPMINSQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMINSQZ128rmbkz) + .value("VPMINSQZ128rmk", LIEF::assembly::x86::OPCODE::VPMINSQZ128rmk) + .value("VPMINSQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINSQZ128rmkz) + .value("VPMINSQZ128rr", LIEF::assembly::x86::OPCODE::VPMINSQZ128rr) + .value("VPMINSQZ128rrk", LIEF::assembly::x86::OPCODE::VPMINSQZ128rrk) + .value("VPMINSQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINSQZ128rrkz) + .value("VPMINSQZ256rm", LIEF::assembly::x86::OPCODE::VPMINSQZ256rm) + .value("VPMINSQZ256rmb", LIEF::assembly::x86::OPCODE::VPMINSQZ256rmb) + .value("VPMINSQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMINSQZ256rmbk) + .value("VPMINSQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMINSQZ256rmbkz) + .value("VPMINSQZ256rmk", LIEF::assembly::x86::OPCODE::VPMINSQZ256rmk) + .value("VPMINSQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINSQZ256rmkz) + .value("VPMINSQZ256rr", LIEF::assembly::x86::OPCODE::VPMINSQZ256rr) + .value("VPMINSQZ256rrk", LIEF::assembly::x86::OPCODE::VPMINSQZ256rrk) + .value("VPMINSQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINSQZ256rrkz) + .value("VPMINSQZrm", LIEF::assembly::x86::OPCODE::VPMINSQZrm) + .value("VPMINSQZrmb", LIEF::assembly::x86::OPCODE::VPMINSQZrmb) + .value("VPMINSQZrmbk", LIEF::assembly::x86::OPCODE::VPMINSQZrmbk) + .value("VPMINSQZrmbkz", LIEF::assembly::x86::OPCODE::VPMINSQZrmbkz) + .value("VPMINSQZrmk", LIEF::assembly::x86::OPCODE::VPMINSQZrmk) + .value("VPMINSQZrmkz", LIEF::assembly::x86::OPCODE::VPMINSQZrmkz) + .value("VPMINSQZrr", LIEF::assembly::x86::OPCODE::VPMINSQZrr) + .value("VPMINSQZrrk", LIEF::assembly::x86::OPCODE::VPMINSQZrrk) + .value("VPMINSQZrrkz", LIEF::assembly::x86::OPCODE::VPMINSQZrrkz) + .value("VPMINSWYrm", LIEF::assembly::x86::OPCODE::VPMINSWYrm) + .value("VPMINSWYrr", LIEF::assembly::x86::OPCODE::VPMINSWYrr) + .value("VPMINSWZ128rm", LIEF::assembly::x86::OPCODE::VPMINSWZ128rm) + .value("VPMINSWZ128rmk", LIEF::assembly::x86::OPCODE::VPMINSWZ128rmk) + .value("VPMINSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINSWZ128rmkz) + .value("VPMINSWZ128rr", LIEF::assembly::x86::OPCODE::VPMINSWZ128rr) + .value("VPMINSWZ128rrk", LIEF::assembly::x86::OPCODE::VPMINSWZ128rrk) + .value("VPMINSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINSWZ128rrkz) + .value("VPMINSWZ256rm", LIEF::assembly::x86::OPCODE::VPMINSWZ256rm) + .value("VPMINSWZ256rmk", LIEF::assembly::x86::OPCODE::VPMINSWZ256rmk) + .value("VPMINSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINSWZ256rmkz) + .value("VPMINSWZ256rr", LIEF::assembly::x86::OPCODE::VPMINSWZ256rr) + .value("VPMINSWZ256rrk", LIEF::assembly::x86::OPCODE::VPMINSWZ256rrk) + .value("VPMINSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINSWZ256rrkz) + .value("VPMINSWZrm", LIEF::assembly::x86::OPCODE::VPMINSWZrm) + .value("VPMINSWZrmk", LIEF::assembly::x86::OPCODE::VPMINSWZrmk) + .value("VPMINSWZrmkz", LIEF::assembly::x86::OPCODE::VPMINSWZrmkz) + .value("VPMINSWZrr", LIEF::assembly::x86::OPCODE::VPMINSWZrr) + .value("VPMINSWZrrk", LIEF::assembly::x86::OPCODE::VPMINSWZrrk) + .value("VPMINSWZrrkz", LIEF::assembly::x86::OPCODE::VPMINSWZrrkz) + .value("VPMINSWrm", LIEF::assembly::x86::OPCODE::VPMINSWrm) + .value("VPMINSWrr", LIEF::assembly::x86::OPCODE::VPMINSWrr) + .value("VPMINUBYrm", LIEF::assembly::x86::OPCODE::VPMINUBYrm) + .value("VPMINUBYrr", LIEF::assembly::x86::OPCODE::VPMINUBYrr) + .value("VPMINUBZ128rm", LIEF::assembly::x86::OPCODE::VPMINUBZ128rm) + .value("VPMINUBZ128rmk", LIEF::assembly::x86::OPCODE::VPMINUBZ128rmk) + .value("VPMINUBZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINUBZ128rmkz) + .value("VPMINUBZ128rr", LIEF::assembly::x86::OPCODE::VPMINUBZ128rr) + .value("VPMINUBZ128rrk", LIEF::assembly::x86::OPCODE::VPMINUBZ128rrk) + .value("VPMINUBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINUBZ128rrkz) + .value("VPMINUBZ256rm", LIEF::assembly::x86::OPCODE::VPMINUBZ256rm) + .value("VPMINUBZ256rmk", LIEF::assembly::x86::OPCODE::VPMINUBZ256rmk) + .value("VPMINUBZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINUBZ256rmkz) + .value("VPMINUBZ256rr", LIEF::assembly::x86::OPCODE::VPMINUBZ256rr) + .value("VPMINUBZ256rrk", LIEF::assembly::x86::OPCODE::VPMINUBZ256rrk) + .value("VPMINUBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINUBZ256rrkz) + .value("VPMINUBZrm", LIEF::assembly::x86::OPCODE::VPMINUBZrm) + .value("VPMINUBZrmk", LIEF::assembly::x86::OPCODE::VPMINUBZrmk) + .value("VPMINUBZrmkz", LIEF::assembly::x86::OPCODE::VPMINUBZrmkz) + .value("VPMINUBZrr", LIEF::assembly::x86::OPCODE::VPMINUBZrr) + .value("VPMINUBZrrk", LIEF::assembly::x86::OPCODE::VPMINUBZrrk) + .value("VPMINUBZrrkz", LIEF::assembly::x86::OPCODE::VPMINUBZrrkz) + .value("VPMINUBrm", LIEF::assembly::x86::OPCODE::VPMINUBrm) + .value("VPMINUBrr", LIEF::assembly::x86::OPCODE::VPMINUBrr) + .value("VPMINUDYrm", LIEF::assembly::x86::OPCODE::VPMINUDYrm) + .value("VPMINUDYrr", LIEF::assembly::x86::OPCODE::VPMINUDYrr) + .value("VPMINUDZ128rm", LIEF::assembly::x86::OPCODE::VPMINUDZ128rm) + .value("VPMINUDZ128rmb", LIEF::assembly::x86::OPCODE::VPMINUDZ128rmb) + .value("VPMINUDZ128rmbk", LIEF::assembly::x86::OPCODE::VPMINUDZ128rmbk) + .value("VPMINUDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMINUDZ128rmbkz) + .value("VPMINUDZ128rmk", LIEF::assembly::x86::OPCODE::VPMINUDZ128rmk) + .value("VPMINUDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINUDZ128rmkz) + .value("VPMINUDZ128rr", LIEF::assembly::x86::OPCODE::VPMINUDZ128rr) + .value("VPMINUDZ128rrk", LIEF::assembly::x86::OPCODE::VPMINUDZ128rrk) + .value("VPMINUDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINUDZ128rrkz) + .value("VPMINUDZ256rm", LIEF::assembly::x86::OPCODE::VPMINUDZ256rm) + .value("VPMINUDZ256rmb", LIEF::assembly::x86::OPCODE::VPMINUDZ256rmb) + .value("VPMINUDZ256rmbk", LIEF::assembly::x86::OPCODE::VPMINUDZ256rmbk) + .value("VPMINUDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMINUDZ256rmbkz) + .value("VPMINUDZ256rmk", LIEF::assembly::x86::OPCODE::VPMINUDZ256rmk) + .value("VPMINUDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINUDZ256rmkz) + .value("VPMINUDZ256rr", LIEF::assembly::x86::OPCODE::VPMINUDZ256rr) + .value("VPMINUDZ256rrk", LIEF::assembly::x86::OPCODE::VPMINUDZ256rrk) + .value("VPMINUDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINUDZ256rrkz) + .value("VPMINUDZrm", LIEF::assembly::x86::OPCODE::VPMINUDZrm) + .value("VPMINUDZrmb", LIEF::assembly::x86::OPCODE::VPMINUDZrmb) + .value("VPMINUDZrmbk", LIEF::assembly::x86::OPCODE::VPMINUDZrmbk) + .value("VPMINUDZrmbkz", LIEF::assembly::x86::OPCODE::VPMINUDZrmbkz) + .value("VPMINUDZrmk", LIEF::assembly::x86::OPCODE::VPMINUDZrmk) + .value("VPMINUDZrmkz", LIEF::assembly::x86::OPCODE::VPMINUDZrmkz) + .value("VPMINUDZrr", LIEF::assembly::x86::OPCODE::VPMINUDZrr) + .value("VPMINUDZrrk", LIEF::assembly::x86::OPCODE::VPMINUDZrrk); + opcodes.value("VPMINUDZrrkz", LIEF::assembly::x86::OPCODE::VPMINUDZrrkz) + .value("VPMINUDrm", LIEF::assembly::x86::OPCODE::VPMINUDrm) + .value("VPMINUDrr", LIEF::assembly::x86::OPCODE::VPMINUDrr) + .value("VPMINUQZ128rm", LIEF::assembly::x86::OPCODE::VPMINUQZ128rm) + .value("VPMINUQZ128rmb", LIEF::assembly::x86::OPCODE::VPMINUQZ128rmb) + .value("VPMINUQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMINUQZ128rmbk) + .value("VPMINUQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMINUQZ128rmbkz) + .value("VPMINUQZ128rmk", LIEF::assembly::x86::OPCODE::VPMINUQZ128rmk) + .value("VPMINUQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINUQZ128rmkz) + .value("VPMINUQZ128rr", LIEF::assembly::x86::OPCODE::VPMINUQZ128rr) + .value("VPMINUQZ128rrk", LIEF::assembly::x86::OPCODE::VPMINUQZ128rrk) + .value("VPMINUQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINUQZ128rrkz) + .value("VPMINUQZ256rm", LIEF::assembly::x86::OPCODE::VPMINUQZ256rm) + .value("VPMINUQZ256rmb", LIEF::assembly::x86::OPCODE::VPMINUQZ256rmb) + .value("VPMINUQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMINUQZ256rmbk) + .value("VPMINUQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMINUQZ256rmbkz) + .value("VPMINUQZ256rmk", LIEF::assembly::x86::OPCODE::VPMINUQZ256rmk) + .value("VPMINUQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINUQZ256rmkz) + .value("VPMINUQZ256rr", LIEF::assembly::x86::OPCODE::VPMINUQZ256rr) + .value("VPMINUQZ256rrk", LIEF::assembly::x86::OPCODE::VPMINUQZ256rrk) + .value("VPMINUQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINUQZ256rrkz) + .value("VPMINUQZrm", LIEF::assembly::x86::OPCODE::VPMINUQZrm) + .value("VPMINUQZrmb", LIEF::assembly::x86::OPCODE::VPMINUQZrmb) + .value("VPMINUQZrmbk", LIEF::assembly::x86::OPCODE::VPMINUQZrmbk) + .value("VPMINUQZrmbkz", LIEF::assembly::x86::OPCODE::VPMINUQZrmbkz) + .value("VPMINUQZrmk", LIEF::assembly::x86::OPCODE::VPMINUQZrmk) + .value("VPMINUQZrmkz", LIEF::assembly::x86::OPCODE::VPMINUQZrmkz) + .value("VPMINUQZrr", LIEF::assembly::x86::OPCODE::VPMINUQZrr) + .value("VPMINUQZrrk", LIEF::assembly::x86::OPCODE::VPMINUQZrrk) + .value("VPMINUQZrrkz", LIEF::assembly::x86::OPCODE::VPMINUQZrrkz) + .value("VPMINUWYrm", LIEF::assembly::x86::OPCODE::VPMINUWYrm) + .value("VPMINUWYrr", LIEF::assembly::x86::OPCODE::VPMINUWYrr) + .value("VPMINUWZ128rm", LIEF::assembly::x86::OPCODE::VPMINUWZ128rm) + .value("VPMINUWZ128rmk", LIEF::assembly::x86::OPCODE::VPMINUWZ128rmk) + .value("VPMINUWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMINUWZ128rmkz) + .value("VPMINUWZ128rr", LIEF::assembly::x86::OPCODE::VPMINUWZ128rr) + .value("VPMINUWZ128rrk", LIEF::assembly::x86::OPCODE::VPMINUWZ128rrk) + .value("VPMINUWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMINUWZ128rrkz) + .value("VPMINUWZ256rm", LIEF::assembly::x86::OPCODE::VPMINUWZ256rm) + .value("VPMINUWZ256rmk", LIEF::assembly::x86::OPCODE::VPMINUWZ256rmk) + .value("VPMINUWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMINUWZ256rmkz) + .value("VPMINUWZ256rr", LIEF::assembly::x86::OPCODE::VPMINUWZ256rr) + .value("VPMINUWZ256rrk", LIEF::assembly::x86::OPCODE::VPMINUWZ256rrk) + .value("VPMINUWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMINUWZ256rrkz) + .value("VPMINUWZrm", LIEF::assembly::x86::OPCODE::VPMINUWZrm) + .value("VPMINUWZrmk", LIEF::assembly::x86::OPCODE::VPMINUWZrmk) + .value("VPMINUWZrmkz", LIEF::assembly::x86::OPCODE::VPMINUWZrmkz) + .value("VPMINUWZrr", LIEF::assembly::x86::OPCODE::VPMINUWZrr) + .value("VPMINUWZrrk", LIEF::assembly::x86::OPCODE::VPMINUWZrrk) + .value("VPMINUWZrrkz", LIEF::assembly::x86::OPCODE::VPMINUWZrrkz) + .value("VPMINUWrm", LIEF::assembly::x86::OPCODE::VPMINUWrm) + .value("VPMINUWrr", LIEF::assembly::x86::OPCODE::VPMINUWrr) + .value("VPMOVB2MZ128kr", LIEF::assembly::x86::OPCODE::VPMOVB2MZ128kr) + .value("VPMOVB2MZ256kr", LIEF::assembly::x86::OPCODE::VPMOVB2MZ256kr) + .value("VPMOVB2MZkr", LIEF::assembly::x86::OPCODE::VPMOVB2MZkr) + .value("VPMOVD2MZ128kr", LIEF::assembly::x86::OPCODE::VPMOVD2MZ128kr) + .value("VPMOVD2MZ256kr", LIEF::assembly::x86::OPCODE::VPMOVD2MZ256kr) + .value("VPMOVD2MZkr", LIEF::assembly::x86::OPCODE::VPMOVD2MZkr) + .value("VPMOVDBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVDBZ128mr) + .value("VPMOVDBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVDBZ128mrk) + .value("VPMOVDBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVDBZ128rr) + .value("VPMOVDBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVDBZ128rrk) + .value("VPMOVDBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVDBZ128rrkz) + .value("VPMOVDBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVDBZ256mr) + .value("VPMOVDBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVDBZ256mrk) + .value("VPMOVDBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVDBZ256rr) + .value("VPMOVDBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVDBZ256rrk) + .value("VPMOVDBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVDBZ256rrkz) + .value("VPMOVDBZmr", LIEF::assembly::x86::OPCODE::VPMOVDBZmr) + .value("VPMOVDBZmrk", LIEF::assembly::x86::OPCODE::VPMOVDBZmrk) + .value("VPMOVDBZrr", LIEF::assembly::x86::OPCODE::VPMOVDBZrr) + .value("VPMOVDBZrrk", LIEF::assembly::x86::OPCODE::VPMOVDBZrrk) + .value("VPMOVDBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVDBZrrkz) + .value("VPMOVDWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVDWZ128mr) + .value("VPMOVDWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVDWZ128mrk) + .value("VPMOVDWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVDWZ128rr) + .value("VPMOVDWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVDWZ128rrk) + .value("VPMOVDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVDWZ128rrkz) + .value("VPMOVDWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVDWZ256mr) + .value("VPMOVDWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVDWZ256mrk) + .value("VPMOVDWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVDWZ256rr) + .value("VPMOVDWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVDWZ256rrk) + .value("VPMOVDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVDWZ256rrkz) + .value("VPMOVDWZmr", LIEF::assembly::x86::OPCODE::VPMOVDWZmr) + .value("VPMOVDWZmrk", LIEF::assembly::x86::OPCODE::VPMOVDWZmrk) + .value("VPMOVDWZrr", LIEF::assembly::x86::OPCODE::VPMOVDWZrr) + .value("VPMOVDWZrrk", LIEF::assembly::x86::OPCODE::VPMOVDWZrrk) + .value("VPMOVDWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVDWZrrkz) + .value("VPMOVM2BZ128rk", LIEF::assembly::x86::OPCODE::VPMOVM2BZ128rk) + .value("VPMOVM2BZ256rk", LIEF::assembly::x86::OPCODE::VPMOVM2BZ256rk) + .value("VPMOVM2BZrk", LIEF::assembly::x86::OPCODE::VPMOVM2BZrk) + .value("VPMOVM2DZ128rk", LIEF::assembly::x86::OPCODE::VPMOVM2DZ128rk) + .value("VPMOVM2DZ256rk", LIEF::assembly::x86::OPCODE::VPMOVM2DZ256rk) + .value("VPMOVM2DZrk", LIEF::assembly::x86::OPCODE::VPMOVM2DZrk) + .value("VPMOVM2QZ128rk", LIEF::assembly::x86::OPCODE::VPMOVM2QZ128rk) + .value("VPMOVM2QZ256rk", LIEF::assembly::x86::OPCODE::VPMOVM2QZ256rk) + .value("VPMOVM2QZrk", LIEF::assembly::x86::OPCODE::VPMOVM2QZrk) + .value("VPMOVM2WZ128rk", LIEF::assembly::x86::OPCODE::VPMOVM2WZ128rk) + .value("VPMOVM2WZ256rk", LIEF::assembly::x86::OPCODE::VPMOVM2WZ256rk) + .value("VPMOVM2WZrk", LIEF::assembly::x86::OPCODE::VPMOVM2WZrk) + .value("VPMOVMSKBYrr", LIEF::assembly::x86::OPCODE::VPMOVMSKBYrr) + .value("VPMOVMSKBrr", LIEF::assembly::x86::OPCODE::VPMOVMSKBrr) + .value("VPMOVQ2MZ128kr", LIEF::assembly::x86::OPCODE::VPMOVQ2MZ128kr) + .value("VPMOVQ2MZ256kr", LIEF::assembly::x86::OPCODE::VPMOVQ2MZ256kr) + .value("VPMOVQ2MZkr", LIEF::assembly::x86::OPCODE::VPMOVQ2MZkr) + .value("VPMOVQBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVQBZ128mr) + .value("VPMOVQBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVQBZ128mrk) + .value("VPMOVQBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVQBZ128rr) + .value("VPMOVQBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVQBZ128rrk) + .value("VPMOVQBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVQBZ128rrkz) + .value("VPMOVQBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVQBZ256mr) + .value("VPMOVQBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVQBZ256mrk) + .value("VPMOVQBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVQBZ256rr) + .value("VPMOVQBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVQBZ256rrk) + .value("VPMOVQBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVQBZ256rrkz) + .value("VPMOVQBZmr", LIEF::assembly::x86::OPCODE::VPMOVQBZmr) + .value("VPMOVQBZmrk", LIEF::assembly::x86::OPCODE::VPMOVQBZmrk) + .value("VPMOVQBZrr", LIEF::assembly::x86::OPCODE::VPMOVQBZrr) + .value("VPMOVQBZrrk", LIEF::assembly::x86::OPCODE::VPMOVQBZrrk) + .value("VPMOVQBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVQBZrrkz) + .value("VPMOVQDZ128mr", LIEF::assembly::x86::OPCODE::VPMOVQDZ128mr) + .value("VPMOVQDZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVQDZ128mrk) + .value("VPMOVQDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVQDZ128rr) + .value("VPMOVQDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVQDZ128rrk) + .value("VPMOVQDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVQDZ128rrkz) + .value("VPMOVQDZ256mr", LIEF::assembly::x86::OPCODE::VPMOVQDZ256mr) + .value("VPMOVQDZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVQDZ256mrk) + .value("VPMOVQDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVQDZ256rr) + .value("VPMOVQDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVQDZ256rrk) + .value("VPMOVQDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVQDZ256rrkz) + .value("VPMOVQDZmr", LIEF::assembly::x86::OPCODE::VPMOVQDZmr) + .value("VPMOVQDZmrk", LIEF::assembly::x86::OPCODE::VPMOVQDZmrk) + .value("VPMOVQDZrr", LIEF::assembly::x86::OPCODE::VPMOVQDZrr) + .value("VPMOVQDZrrk", LIEF::assembly::x86::OPCODE::VPMOVQDZrrk) + .value("VPMOVQDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVQDZrrkz) + .value("VPMOVQWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVQWZ128mr) + .value("VPMOVQWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVQWZ128mrk) + .value("VPMOVQWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVQWZ128rr) + .value("VPMOVQWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVQWZ128rrk) + .value("VPMOVQWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVQWZ128rrkz) + .value("VPMOVQWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVQWZ256mr) + .value("VPMOVQWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVQWZ256mrk) + .value("VPMOVQWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVQWZ256rr) + .value("VPMOVQWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVQWZ256rrk) + .value("VPMOVQWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVQWZ256rrkz) + .value("VPMOVQWZmr", LIEF::assembly::x86::OPCODE::VPMOVQWZmr) + .value("VPMOVQWZmrk", LIEF::assembly::x86::OPCODE::VPMOVQWZmrk) + .value("VPMOVQWZrr", LIEF::assembly::x86::OPCODE::VPMOVQWZrr) + .value("VPMOVQWZrrk", LIEF::assembly::x86::OPCODE::VPMOVQWZrrk) + .value("VPMOVQWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVQWZrrkz) + .value("VPMOVSDBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSDBZ128mr) + .value("VPMOVSDBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZ128mrk) + .value("VPMOVSDBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSDBZ128rr) + .value("VPMOVSDBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZ128rrk) + .value("VPMOVSDBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSDBZ128rrkz) + .value("VPMOVSDBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSDBZ256mr) + .value("VPMOVSDBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZ256mrk) + .value("VPMOVSDBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSDBZ256rr) + .value("VPMOVSDBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZ256rrk) + .value("VPMOVSDBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSDBZ256rrkz) + .value("VPMOVSDBZmr", LIEF::assembly::x86::OPCODE::VPMOVSDBZmr) + .value("VPMOVSDBZmrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZmrk) + .value("VPMOVSDBZrr", LIEF::assembly::x86::OPCODE::VPMOVSDBZrr) + .value("VPMOVSDBZrrk", LIEF::assembly::x86::OPCODE::VPMOVSDBZrrk) + .value("VPMOVSDBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSDBZrrkz) + .value("VPMOVSDWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSDWZ128mr) + .value("VPMOVSDWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZ128mrk) + .value("VPMOVSDWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSDWZ128rr) + .value("VPMOVSDWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZ128rrk) + .value("VPMOVSDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSDWZ128rrkz) + .value("VPMOVSDWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSDWZ256mr) + .value("VPMOVSDWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZ256mrk) + .value("VPMOVSDWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSDWZ256rr) + .value("VPMOVSDWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZ256rrk) + .value("VPMOVSDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSDWZ256rrkz) + .value("VPMOVSDWZmr", LIEF::assembly::x86::OPCODE::VPMOVSDWZmr) + .value("VPMOVSDWZmrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZmrk) + .value("VPMOVSDWZrr", LIEF::assembly::x86::OPCODE::VPMOVSDWZrr) + .value("VPMOVSDWZrrk", LIEF::assembly::x86::OPCODE::VPMOVSDWZrrk) + .value("VPMOVSDWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSDWZrrkz) + .value("VPMOVSQBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSQBZ128mr) + .value("VPMOVSQBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZ128mrk) + .value("VPMOVSQBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSQBZ128rr) + .value("VPMOVSQBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZ128rrk) + .value("VPMOVSQBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQBZ128rrkz) + .value("VPMOVSQBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSQBZ256mr) + .value("VPMOVSQBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZ256mrk) + .value("VPMOVSQBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSQBZ256rr) + .value("VPMOVSQBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZ256rrk) + .value("VPMOVSQBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQBZ256rrkz) + .value("VPMOVSQBZmr", LIEF::assembly::x86::OPCODE::VPMOVSQBZmr) + .value("VPMOVSQBZmrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZmrk) + .value("VPMOVSQBZrr", LIEF::assembly::x86::OPCODE::VPMOVSQBZrr) + .value("VPMOVSQBZrrk", LIEF::assembly::x86::OPCODE::VPMOVSQBZrrk) + .value("VPMOVSQBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSQBZrrkz) + .value("VPMOVSQDZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSQDZ128mr) + .value("VPMOVSQDZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZ128mrk) + .value("VPMOVSQDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSQDZ128rr) + .value("VPMOVSQDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZ128rrk) + .value("VPMOVSQDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQDZ128rrkz) + .value("VPMOVSQDZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSQDZ256mr) + .value("VPMOVSQDZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZ256mrk) + .value("VPMOVSQDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSQDZ256rr) + .value("VPMOVSQDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZ256rrk) + .value("VPMOVSQDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQDZ256rrkz) + .value("VPMOVSQDZmr", LIEF::assembly::x86::OPCODE::VPMOVSQDZmr) + .value("VPMOVSQDZmrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZmrk) + .value("VPMOVSQDZrr", LIEF::assembly::x86::OPCODE::VPMOVSQDZrr) + .value("VPMOVSQDZrrk", LIEF::assembly::x86::OPCODE::VPMOVSQDZrrk) + .value("VPMOVSQDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSQDZrrkz) + .value("VPMOVSQWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSQWZ128mr) + .value("VPMOVSQWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZ128mrk) + .value("VPMOVSQWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSQWZ128rr) + .value("VPMOVSQWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZ128rrk) + .value("VPMOVSQWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQWZ128rrkz) + .value("VPMOVSQWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSQWZ256mr) + .value("VPMOVSQWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZ256mrk) + .value("VPMOVSQWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSQWZ256rr) + .value("VPMOVSQWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZ256rrk) + .value("VPMOVSQWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSQWZ256rrkz) + .value("VPMOVSQWZmr", LIEF::assembly::x86::OPCODE::VPMOVSQWZmr) + .value("VPMOVSQWZmrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZmrk) + .value("VPMOVSQWZrr", LIEF::assembly::x86::OPCODE::VPMOVSQWZrr) + .value("VPMOVSQWZrrk", LIEF::assembly::x86::OPCODE::VPMOVSQWZrrk) + .value("VPMOVSQWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSQWZrrkz) + .value("VPMOVSWBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVSWBZ128mr) + .value("VPMOVSWBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZ128mrk) + .value("VPMOVSWBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSWBZ128rr) + .value("VPMOVSWBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZ128rrk) + .value("VPMOVSWBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSWBZ128rrkz) + .value("VPMOVSWBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVSWBZ256mr) + .value("VPMOVSWBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZ256mrk) + .value("VPMOVSWBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSWBZ256rr) + .value("VPMOVSWBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZ256rrk) + .value("VPMOVSWBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSWBZ256rrkz) + .value("VPMOVSWBZmr", LIEF::assembly::x86::OPCODE::VPMOVSWBZmr) + .value("VPMOVSWBZmrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZmrk) + .value("VPMOVSWBZrr", LIEF::assembly::x86::OPCODE::VPMOVSWBZrr) + .value("VPMOVSWBZrrk", LIEF::assembly::x86::OPCODE::VPMOVSWBZrrk) + .value("VPMOVSWBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSWBZrrkz) + .value("VPMOVSXBDYrm", LIEF::assembly::x86::OPCODE::VPMOVSXBDYrm) + .value("VPMOVSXBDYrr", LIEF::assembly::x86::OPCODE::VPMOVSXBDYrr) + .value("VPMOVSXBDZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rm) + .value("VPMOVSXBDZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rmk) + .value("VPMOVSXBDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rmkz) + .value("VPMOVSXBDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rr) + .value("VPMOVSXBDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rrk) + .value("VPMOVSXBDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ128rrkz) + .value("VPMOVSXBDZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rm) + .value("VPMOVSXBDZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rmk) + .value("VPMOVSXBDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rmkz) + .value("VPMOVSXBDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rr) + .value("VPMOVSXBDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rrk) + .value("VPMOVSXBDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZ256rrkz) + .value("VPMOVSXBDZrm", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrm) + .value("VPMOVSXBDZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrmk) + .value("VPMOVSXBDZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrmkz) + .value("VPMOVSXBDZrr", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrr) + .value("VPMOVSXBDZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrrk) + .value("VPMOVSXBDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBDZrrkz) + .value("VPMOVSXBDrm", LIEF::assembly::x86::OPCODE::VPMOVSXBDrm) + .value("VPMOVSXBDrr", LIEF::assembly::x86::OPCODE::VPMOVSXBDrr) + .value("VPMOVSXBQYrm", LIEF::assembly::x86::OPCODE::VPMOVSXBQYrm) + .value("VPMOVSXBQYrr", LIEF::assembly::x86::OPCODE::VPMOVSXBQYrr) + .value("VPMOVSXBQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rm) + .value("VPMOVSXBQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rmk) + .value("VPMOVSXBQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rmkz) + .value("VPMOVSXBQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rr) + .value("VPMOVSXBQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rrk) + .value("VPMOVSXBQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ128rrkz) + .value("VPMOVSXBQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rm) + .value("VPMOVSXBQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rmk) + .value("VPMOVSXBQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rmkz) + .value("VPMOVSXBQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rr) + .value("VPMOVSXBQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rrk) + .value("VPMOVSXBQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZ256rrkz) + .value("VPMOVSXBQZrm", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrm) + .value("VPMOVSXBQZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrmk) + .value("VPMOVSXBQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrmkz) + .value("VPMOVSXBQZrr", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrr) + .value("VPMOVSXBQZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrrk) + .value("VPMOVSXBQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBQZrrkz) + .value("VPMOVSXBQrm", LIEF::assembly::x86::OPCODE::VPMOVSXBQrm) + .value("VPMOVSXBQrr", LIEF::assembly::x86::OPCODE::VPMOVSXBQrr) + .value("VPMOVSXBWYrm", LIEF::assembly::x86::OPCODE::VPMOVSXBWYrm) + .value("VPMOVSXBWYrr", LIEF::assembly::x86::OPCODE::VPMOVSXBWYrr) + .value("VPMOVSXBWZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rm) + .value("VPMOVSXBWZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rmk) + .value("VPMOVSXBWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rmkz) + .value("VPMOVSXBWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rr) + .value("VPMOVSXBWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rrk) + .value("VPMOVSXBWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ128rrkz) + .value("VPMOVSXBWZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rm) + .value("VPMOVSXBWZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rmk) + .value("VPMOVSXBWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rmkz) + .value("VPMOVSXBWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rr) + .value("VPMOVSXBWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rrk) + .value("VPMOVSXBWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZ256rrkz) + .value("VPMOVSXBWZrm", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrm) + .value("VPMOVSXBWZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrmk); + opcodes.value("VPMOVSXBWZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrmkz) + .value("VPMOVSXBWZrr", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrr) + .value("VPMOVSXBWZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrrk) + .value("VPMOVSXBWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXBWZrrkz) + .value("VPMOVSXBWrm", LIEF::assembly::x86::OPCODE::VPMOVSXBWrm) + .value("VPMOVSXBWrr", LIEF::assembly::x86::OPCODE::VPMOVSXBWrr) + .value("VPMOVSXDQYrm", LIEF::assembly::x86::OPCODE::VPMOVSXDQYrm) + .value("VPMOVSXDQYrr", LIEF::assembly::x86::OPCODE::VPMOVSXDQYrr) + .value("VPMOVSXDQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rm) + .value("VPMOVSXDQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rmk) + .value("VPMOVSXDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rmkz) + .value("VPMOVSXDQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rr) + .value("VPMOVSXDQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rrk) + .value("VPMOVSXDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ128rrkz) + .value("VPMOVSXDQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rm) + .value("VPMOVSXDQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rmk) + .value("VPMOVSXDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rmkz) + .value("VPMOVSXDQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rr) + .value("VPMOVSXDQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rrk) + .value("VPMOVSXDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZ256rrkz) + .value("VPMOVSXDQZrm", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrm) + .value("VPMOVSXDQZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrmk) + .value("VPMOVSXDQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrmkz) + .value("VPMOVSXDQZrr", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrr) + .value("VPMOVSXDQZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrrk) + .value("VPMOVSXDQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXDQZrrkz) + .value("VPMOVSXDQrm", LIEF::assembly::x86::OPCODE::VPMOVSXDQrm) + .value("VPMOVSXDQrr", LIEF::assembly::x86::OPCODE::VPMOVSXDQrr) + .value("VPMOVSXWDYrm", LIEF::assembly::x86::OPCODE::VPMOVSXWDYrm) + .value("VPMOVSXWDYrr", LIEF::assembly::x86::OPCODE::VPMOVSXWDYrr) + .value("VPMOVSXWDZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rm) + .value("VPMOVSXWDZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rmk) + .value("VPMOVSXWDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rmkz) + .value("VPMOVSXWDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rr) + .value("VPMOVSXWDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rrk) + .value("VPMOVSXWDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ128rrkz) + .value("VPMOVSXWDZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rm) + .value("VPMOVSXWDZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rmk) + .value("VPMOVSXWDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rmkz) + .value("VPMOVSXWDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rr) + .value("VPMOVSXWDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rrk) + .value("VPMOVSXWDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZ256rrkz) + .value("VPMOVSXWDZrm", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrm) + .value("VPMOVSXWDZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrmk) + .value("VPMOVSXWDZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrmkz) + .value("VPMOVSXWDZrr", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrr) + .value("VPMOVSXWDZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrrk) + .value("VPMOVSXWDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWDZrrkz) + .value("VPMOVSXWDrm", LIEF::assembly::x86::OPCODE::VPMOVSXWDrm) + .value("VPMOVSXWDrr", LIEF::assembly::x86::OPCODE::VPMOVSXWDrr) + .value("VPMOVSXWQYrm", LIEF::assembly::x86::OPCODE::VPMOVSXWQYrm) + .value("VPMOVSXWQYrr", LIEF::assembly::x86::OPCODE::VPMOVSXWQYrr) + .value("VPMOVSXWQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rm) + .value("VPMOVSXWQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rmk) + .value("VPMOVSXWQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rmkz) + .value("VPMOVSXWQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rr) + .value("VPMOVSXWQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rrk) + .value("VPMOVSXWQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ128rrkz) + .value("VPMOVSXWQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rm) + .value("VPMOVSXWQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rmk) + .value("VPMOVSXWQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rmkz) + .value("VPMOVSXWQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rr) + .value("VPMOVSXWQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rrk) + .value("VPMOVSXWQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZ256rrkz) + .value("VPMOVSXWQZrm", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrm) + .value("VPMOVSXWQZrmk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrmk) + .value("VPMOVSXWQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrmkz) + .value("VPMOVSXWQZrr", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrr) + .value("VPMOVSXWQZrrk", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrrk) + .value("VPMOVSXWQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVSXWQZrrkz) + .value("VPMOVSXWQrm", LIEF::assembly::x86::OPCODE::VPMOVSXWQrm) + .value("VPMOVSXWQrr", LIEF::assembly::x86::OPCODE::VPMOVSXWQrr) + .value("VPMOVUSDBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ128mr) + .value("VPMOVUSDBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ128mrk) + .value("VPMOVUSDBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ128rr) + .value("VPMOVUSDBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ128rrk) + .value("VPMOVUSDBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ128rrkz) + .value("VPMOVUSDBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ256mr) + .value("VPMOVUSDBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ256mrk) + .value("VPMOVUSDBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ256rr) + .value("VPMOVUSDBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ256rrk) + .value("VPMOVUSDBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDBZ256rrkz) + .value("VPMOVUSDBZmr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZmr) + .value("VPMOVUSDBZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZmrk) + .value("VPMOVUSDBZrr", LIEF::assembly::x86::OPCODE::VPMOVUSDBZrr) + .value("VPMOVUSDBZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSDBZrrk) + .value("VPMOVUSDBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDBZrrkz) + .value("VPMOVUSDWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ128mr) + .value("VPMOVUSDWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ128mrk) + .value("VPMOVUSDWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ128rr) + .value("VPMOVUSDWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ128rrk) + .value("VPMOVUSDWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ128rrkz) + .value("VPMOVUSDWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ256mr) + .value("VPMOVUSDWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ256mrk) + .value("VPMOVUSDWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ256rr) + .value("VPMOVUSDWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ256rrk) + .value("VPMOVUSDWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDWZ256rrkz) + .value("VPMOVUSDWZmr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZmr) + .value("VPMOVUSDWZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZmrk) + .value("VPMOVUSDWZrr", LIEF::assembly::x86::OPCODE::VPMOVUSDWZrr) + .value("VPMOVUSDWZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSDWZrrk) + .value("VPMOVUSDWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSDWZrrkz) + .value("VPMOVUSQBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ128mr) + .value("VPMOVUSQBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ128mrk) + .value("VPMOVUSQBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ128rr) + .value("VPMOVUSQBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ128rrk) + .value("VPMOVUSQBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ128rrkz) + .value("VPMOVUSQBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ256mr) + .value("VPMOVUSQBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ256mrk) + .value("VPMOVUSQBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ256rr) + .value("VPMOVUSQBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ256rrk) + .value("VPMOVUSQBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQBZ256rrkz) + .value("VPMOVUSQBZmr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZmr) + .value("VPMOVUSQBZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZmrk) + .value("VPMOVUSQBZrr", LIEF::assembly::x86::OPCODE::VPMOVUSQBZrr) + .value("VPMOVUSQBZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSQBZrrk) + .value("VPMOVUSQBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQBZrrkz) + .value("VPMOVUSQDZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ128mr) + .value("VPMOVUSQDZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ128mrk) + .value("VPMOVUSQDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ128rr) + .value("VPMOVUSQDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ128rrk) + .value("VPMOVUSQDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ128rrkz) + .value("VPMOVUSQDZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ256mr) + .value("VPMOVUSQDZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ256mrk) + .value("VPMOVUSQDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ256rr) + .value("VPMOVUSQDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ256rrk) + .value("VPMOVUSQDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQDZ256rrkz) + .value("VPMOVUSQDZmr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZmr) + .value("VPMOVUSQDZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZmrk) + .value("VPMOVUSQDZrr", LIEF::assembly::x86::OPCODE::VPMOVUSQDZrr) + .value("VPMOVUSQDZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSQDZrrk) + .value("VPMOVUSQDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQDZrrkz) + .value("VPMOVUSQWZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ128mr) + .value("VPMOVUSQWZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ128mrk) + .value("VPMOVUSQWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ128rr) + .value("VPMOVUSQWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ128rrk) + .value("VPMOVUSQWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ128rrkz) + .value("VPMOVUSQWZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ256mr) + .value("VPMOVUSQWZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ256mrk) + .value("VPMOVUSQWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ256rr) + .value("VPMOVUSQWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ256rrk) + .value("VPMOVUSQWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQWZ256rrkz) + .value("VPMOVUSQWZmr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZmr) + .value("VPMOVUSQWZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZmrk) + .value("VPMOVUSQWZrr", LIEF::assembly::x86::OPCODE::VPMOVUSQWZrr) + .value("VPMOVUSQWZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSQWZrrk) + .value("VPMOVUSQWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSQWZrrkz) + .value("VPMOVUSWBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ128mr) + .value("VPMOVUSWBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ128mrk) + .value("VPMOVUSWBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ128rr) + .value("VPMOVUSWBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ128rrk) + .value("VPMOVUSWBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ128rrkz) + .value("VPMOVUSWBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ256mr) + .value("VPMOVUSWBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ256mrk) + .value("VPMOVUSWBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ256rr) + .value("VPMOVUSWBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ256rrk) + .value("VPMOVUSWBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVUSWBZ256rrkz) + .value("VPMOVUSWBZmr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZmr) + .value("VPMOVUSWBZmrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZmrk) + .value("VPMOVUSWBZrr", LIEF::assembly::x86::OPCODE::VPMOVUSWBZrr) + .value("VPMOVUSWBZrrk", LIEF::assembly::x86::OPCODE::VPMOVUSWBZrrk) + .value("VPMOVUSWBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVUSWBZrrkz) + .value("VPMOVW2MZ128kr", LIEF::assembly::x86::OPCODE::VPMOVW2MZ128kr) + .value("VPMOVW2MZ256kr", LIEF::assembly::x86::OPCODE::VPMOVW2MZ256kr) + .value("VPMOVW2MZkr", LIEF::assembly::x86::OPCODE::VPMOVW2MZkr) + .value("VPMOVWBZ128mr", LIEF::assembly::x86::OPCODE::VPMOVWBZ128mr) + .value("VPMOVWBZ128mrk", LIEF::assembly::x86::OPCODE::VPMOVWBZ128mrk) + .value("VPMOVWBZ128rr", LIEF::assembly::x86::OPCODE::VPMOVWBZ128rr) + .value("VPMOVWBZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVWBZ128rrk) + .value("VPMOVWBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVWBZ128rrkz) + .value("VPMOVWBZ256mr", LIEF::assembly::x86::OPCODE::VPMOVWBZ256mr) + .value("VPMOVWBZ256mrk", LIEF::assembly::x86::OPCODE::VPMOVWBZ256mrk) + .value("VPMOVWBZ256rr", LIEF::assembly::x86::OPCODE::VPMOVWBZ256rr) + .value("VPMOVWBZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVWBZ256rrk) + .value("VPMOVWBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVWBZ256rrkz) + .value("VPMOVWBZmr", LIEF::assembly::x86::OPCODE::VPMOVWBZmr) + .value("VPMOVWBZmrk", LIEF::assembly::x86::OPCODE::VPMOVWBZmrk) + .value("VPMOVWBZrr", LIEF::assembly::x86::OPCODE::VPMOVWBZrr) + .value("VPMOVWBZrrk", LIEF::assembly::x86::OPCODE::VPMOVWBZrrk) + .value("VPMOVWBZrrkz", LIEF::assembly::x86::OPCODE::VPMOVWBZrrkz) + .value("VPMOVZXBDYrm", LIEF::assembly::x86::OPCODE::VPMOVZXBDYrm) + .value("VPMOVZXBDYrr", LIEF::assembly::x86::OPCODE::VPMOVZXBDYrr) + .value("VPMOVZXBDZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rm) + .value("VPMOVZXBDZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rmk) + .value("VPMOVZXBDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rmkz) + .value("VPMOVZXBDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rr) + .value("VPMOVZXBDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rrk) + .value("VPMOVZXBDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ128rrkz) + .value("VPMOVZXBDZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rm) + .value("VPMOVZXBDZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rmk) + .value("VPMOVZXBDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rmkz) + .value("VPMOVZXBDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rr) + .value("VPMOVZXBDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rrk) + .value("VPMOVZXBDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZ256rrkz) + .value("VPMOVZXBDZrm", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrm) + .value("VPMOVZXBDZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrmk) + .value("VPMOVZXBDZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrmkz) + .value("VPMOVZXBDZrr", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrr) + .value("VPMOVZXBDZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrrk) + .value("VPMOVZXBDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBDZrrkz) + .value("VPMOVZXBDrm", LIEF::assembly::x86::OPCODE::VPMOVZXBDrm) + .value("VPMOVZXBDrr", LIEF::assembly::x86::OPCODE::VPMOVZXBDrr) + .value("VPMOVZXBQYrm", LIEF::assembly::x86::OPCODE::VPMOVZXBQYrm) + .value("VPMOVZXBQYrr", LIEF::assembly::x86::OPCODE::VPMOVZXBQYrr) + .value("VPMOVZXBQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rm) + .value("VPMOVZXBQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rmk) + .value("VPMOVZXBQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rmkz) + .value("VPMOVZXBQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rr) + .value("VPMOVZXBQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rrk) + .value("VPMOVZXBQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ128rrkz) + .value("VPMOVZXBQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rm) + .value("VPMOVZXBQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rmk) + .value("VPMOVZXBQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rmkz) + .value("VPMOVZXBQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rr) + .value("VPMOVZXBQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rrk) + .value("VPMOVZXBQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZ256rrkz) + .value("VPMOVZXBQZrm", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrm) + .value("VPMOVZXBQZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrmk) + .value("VPMOVZXBQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrmkz) + .value("VPMOVZXBQZrr", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrr) + .value("VPMOVZXBQZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrrk) + .value("VPMOVZXBQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBQZrrkz) + .value("VPMOVZXBQrm", LIEF::assembly::x86::OPCODE::VPMOVZXBQrm) + .value("VPMOVZXBQrr", LIEF::assembly::x86::OPCODE::VPMOVZXBQrr) + .value("VPMOVZXBWYrm", LIEF::assembly::x86::OPCODE::VPMOVZXBWYrm) + .value("VPMOVZXBWYrr", LIEF::assembly::x86::OPCODE::VPMOVZXBWYrr) + .value("VPMOVZXBWZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rm) + .value("VPMOVZXBWZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rmk) + .value("VPMOVZXBWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rmkz) + .value("VPMOVZXBWZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rr) + .value("VPMOVZXBWZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rrk) + .value("VPMOVZXBWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ128rrkz) + .value("VPMOVZXBWZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rm) + .value("VPMOVZXBWZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rmk) + .value("VPMOVZXBWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rmkz) + .value("VPMOVZXBWZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rr) + .value("VPMOVZXBWZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rrk) + .value("VPMOVZXBWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZ256rrkz) + .value("VPMOVZXBWZrm", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrm) + .value("VPMOVZXBWZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrmk) + .value("VPMOVZXBWZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrmkz) + .value("VPMOVZXBWZrr", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrr) + .value("VPMOVZXBWZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrrk) + .value("VPMOVZXBWZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXBWZrrkz) + .value("VPMOVZXBWrm", LIEF::assembly::x86::OPCODE::VPMOVZXBWrm) + .value("VPMOVZXBWrr", LIEF::assembly::x86::OPCODE::VPMOVZXBWrr) + .value("VPMOVZXDQYrm", LIEF::assembly::x86::OPCODE::VPMOVZXDQYrm) + .value("VPMOVZXDQYrr", LIEF::assembly::x86::OPCODE::VPMOVZXDQYrr) + .value("VPMOVZXDQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rm) + .value("VPMOVZXDQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rmk) + .value("VPMOVZXDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rmkz) + .value("VPMOVZXDQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rr) + .value("VPMOVZXDQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rrk) + .value("VPMOVZXDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ128rrkz) + .value("VPMOVZXDQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rm) + .value("VPMOVZXDQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rmk) + .value("VPMOVZXDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rmkz) + .value("VPMOVZXDQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rr) + .value("VPMOVZXDQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rrk) + .value("VPMOVZXDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZ256rrkz) + .value("VPMOVZXDQZrm", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrm) + .value("VPMOVZXDQZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrmk) + .value("VPMOVZXDQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrmkz) + .value("VPMOVZXDQZrr", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrr) + .value("VPMOVZXDQZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrrk) + .value("VPMOVZXDQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXDQZrrkz) + .value("VPMOVZXDQrm", LIEF::assembly::x86::OPCODE::VPMOVZXDQrm) + .value("VPMOVZXDQrr", LIEF::assembly::x86::OPCODE::VPMOVZXDQrr) + .value("VPMOVZXWDYrm", LIEF::assembly::x86::OPCODE::VPMOVZXWDYrm) + .value("VPMOVZXWDYrr", LIEF::assembly::x86::OPCODE::VPMOVZXWDYrr) + .value("VPMOVZXWDZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rm) + .value("VPMOVZXWDZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rmk) + .value("VPMOVZXWDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rmkz) + .value("VPMOVZXWDZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rr) + .value("VPMOVZXWDZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rrk) + .value("VPMOVZXWDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ128rrkz) + .value("VPMOVZXWDZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rm) + .value("VPMOVZXWDZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rmk) + .value("VPMOVZXWDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rmkz) + .value("VPMOVZXWDZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rr) + .value("VPMOVZXWDZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rrk) + .value("VPMOVZXWDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZ256rrkz) + .value("VPMOVZXWDZrm", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrm) + .value("VPMOVZXWDZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrmk) + .value("VPMOVZXWDZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrmkz) + .value("VPMOVZXWDZrr", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrr) + .value("VPMOVZXWDZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrrk) + .value("VPMOVZXWDZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWDZrrkz) + .value("VPMOVZXWDrm", LIEF::assembly::x86::OPCODE::VPMOVZXWDrm) + .value("VPMOVZXWDrr", LIEF::assembly::x86::OPCODE::VPMOVZXWDrr) + .value("VPMOVZXWQYrm", LIEF::assembly::x86::OPCODE::VPMOVZXWQYrm) + .value("VPMOVZXWQYrr", LIEF::assembly::x86::OPCODE::VPMOVZXWQYrr) + .value("VPMOVZXWQZ128rm", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rm) + .value("VPMOVZXWQZ128rmk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rmk) + .value("VPMOVZXWQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rmkz) + .value("VPMOVZXWQZ128rr", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rr) + .value("VPMOVZXWQZ128rrk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rrk) + .value("VPMOVZXWQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ128rrkz) + .value("VPMOVZXWQZ256rm", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rm) + .value("VPMOVZXWQZ256rmk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rmk); + opcodes.value("VPMOVZXWQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rmkz) + .value("VPMOVZXWQZ256rr", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rr) + .value("VPMOVZXWQZ256rrk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rrk) + .value("VPMOVZXWQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZ256rrkz) + .value("VPMOVZXWQZrm", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrm) + .value("VPMOVZXWQZrmk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrmk) + .value("VPMOVZXWQZrmkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrmkz) + .value("VPMOVZXWQZrr", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrr) + .value("VPMOVZXWQZrrk", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrrk) + .value("VPMOVZXWQZrrkz", LIEF::assembly::x86::OPCODE::VPMOVZXWQZrrkz) + .value("VPMOVZXWQrm", LIEF::assembly::x86::OPCODE::VPMOVZXWQrm) + .value("VPMOVZXWQrr", LIEF::assembly::x86::OPCODE::VPMOVZXWQrr) + .value("VPMULDQYrm", LIEF::assembly::x86::OPCODE::VPMULDQYrm) + .value("VPMULDQYrr", LIEF::assembly::x86::OPCODE::VPMULDQYrr) + .value("VPMULDQZ128rm", LIEF::assembly::x86::OPCODE::VPMULDQZ128rm) + .value("VPMULDQZ128rmb", LIEF::assembly::x86::OPCODE::VPMULDQZ128rmb) + .value("VPMULDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMULDQZ128rmbk) + .value("VPMULDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMULDQZ128rmbkz) + .value("VPMULDQZ128rmk", LIEF::assembly::x86::OPCODE::VPMULDQZ128rmk) + .value("VPMULDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULDQZ128rmkz) + .value("VPMULDQZ128rr", LIEF::assembly::x86::OPCODE::VPMULDQZ128rr) + .value("VPMULDQZ128rrk", LIEF::assembly::x86::OPCODE::VPMULDQZ128rrk) + .value("VPMULDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULDQZ128rrkz) + .value("VPMULDQZ256rm", LIEF::assembly::x86::OPCODE::VPMULDQZ256rm) + .value("VPMULDQZ256rmb", LIEF::assembly::x86::OPCODE::VPMULDQZ256rmb) + .value("VPMULDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMULDQZ256rmbk) + .value("VPMULDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMULDQZ256rmbkz) + .value("VPMULDQZ256rmk", LIEF::assembly::x86::OPCODE::VPMULDQZ256rmk) + .value("VPMULDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULDQZ256rmkz) + .value("VPMULDQZ256rr", LIEF::assembly::x86::OPCODE::VPMULDQZ256rr) + .value("VPMULDQZ256rrk", LIEF::assembly::x86::OPCODE::VPMULDQZ256rrk) + .value("VPMULDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULDQZ256rrkz) + .value("VPMULDQZrm", LIEF::assembly::x86::OPCODE::VPMULDQZrm) + .value("VPMULDQZrmb", LIEF::assembly::x86::OPCODE::VPMULDQZrmb) + .value("VPMULDQZrmbk", LIEF::assembly::x86::OPCODE::VPMULDQZrmbk) + .value("VPMULDQZrmbkz", LIEF::assembly::x86::OPCODE::VPMULDQZrmbkz) + .value("VPMULDQZrmk", LIEF::assembly::x86::OPCODE::VPMULDQZrmk) + .value("VPMULDQZrmkz", LIEF::assembly::x86::OPCODE::VPMULDQZrmkz) + .value("VPMULDQZrr", LIEF::assembly::x86::OPCODE::VPMULDQZrr) + .value("VPMULDQZrrk", LIEF::assembly::x86::OPCODE::VPMULDQZrrk) + .value("VPMULDQZrrkz", LIEF::assembly::x86::OPCODE::VPMULDQZrrkz) + .value("VPMULDQrm", LIEF::assembly::x86::OPCODE::VPMULDQrm) + .value("VPMULDQrr", LIEF::assembly::x86::OPCODE::VPMULDQrr) + .value("VPMULHRSWYrm", LIEF::assembly::x86::OPCODE::VPMULHRSWYrm) + .value("VPMULHRSWYrr", LIEF::assembly::x86::OPCODE::VPMULHRSWYrr) + .value("VPMULHRSWZ128rm", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rm) + .value("VPMULHRSWZ128rmk", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rmk) + .value("VPMULHRSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rmkz) + .value("VPMULHRSWZ128rr", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rr) + .value("VPMULHRSWZ128rrk", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rrk) + .value("VPMULHRSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZ128rrkz) + .value("VPMULHRSWZ256rm", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rm) + .value("VPMULHRSWZ256rmk", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rmk) + .value("VPMULHRSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rmkz) + .value("VPMULHRSWZ256rr", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rr) + .value("VPMULHRSWZ256rrk", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rrk) + .value("VPMULHRSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZ256rrkz) + .value("VPMULHRSWZrm", LIEF::assembly::x86::OPCODE::VPMULHRSWZrm) + .value("VPMULHRSWZrmk", LIEF::assembly::x86::OPCODE::VPMULHRSWZrmk) + .value("VPMULHRSWZrmkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZrmkz) + .value("VPMULHRSWZrr", LIEF::assembly::x86::OPCODE::VPMULHRSWZrr) + .value("VPMULHRSWZrrk", LIEF::assembly::x86::OPCODE::VPMULHRSWZrrk) + .value("VPMULHRSWZrrkz", LIEF::assembly::x86::OPCODE::VPMULHRSWZrrkz) + .value("VPMULHRSWrm", LIEF::assembly::x86::OPCODE::VPMULHRSWrm) + .value("VPMULHRSWrr", LIEF::assembly::x86::OPCODE::VPMULHRSWrr) + .value("VPMULHUWYrm", LIEF::assembly::x86::OPCODE::VPMULHUWYrm) + .value("VPMULHUWYrr", LIEF::assembly::x86::OPCODE::VPMULHUWYrr) + .value("VPMULHUWZ128rm", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rm) + .value("VPMULHUWZ128rmk", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rmk) + .value("VPMULHUWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rmkz) + .value("VPMULHUWZ128rr", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rr) + .value("VPMULHUWZ128rrk", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rrk) + .value("VPMULHUWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULHUWZ128rrkz) + .value("VPMULHUWZ256rm", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rm) + .value("VPMULHUWZ256rmk", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rmk) + .value("VPMULHUWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rmkz) + .value("VPMULHUWZ256rr", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rr) + .value("VPMULHUWZ256rrk", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rrk) + .value("VPMULHUWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULHUWZ256rrkz) + .value("VPMULHUWZrm", LIEF::assembly::x86::OPCODE::VPMULHUWZrm) + .value("VPMULHUWZrmk", LIEF::assembly::x86::OPCODE::VPMULHUWZrmk) + .value("VPMULHUWZrmkz", LIEF::assembly::x86::OPCODE::VPMULHUWZrmkz) + .value("VPMULHUWZrr", LIEF::assembly::x86::OPCODE::VPMULHUWZrr) + .value("VPMULHUWZrrk", LIEF::assembly::x86::OPCODE::VPMULHUWZrrk) + .value("VPMULHUWZrrkz", LIEF::assembly::x86::OPCODE::VPMULHUWZrrkz) + .value("VPMULHUWrm", LIEF::assembly::x86::OPCODE::VPMULHUWrm) + .value("VPMULHUWrr", LIEF::assembly::x86::OPCODE::VPMULHUWrr) + .value("VPMULHWYrm", LIEF::assembly::x86::OPCODE::VPMULHWYrm) + .value("VPMULHWYrr", LIEF::assembly::x86::OPCODE::VPMULHWYrr) + .value("VPMULHWZ128rm", LIEF::assembly::x86::OPCODE::VPMULHWZ128rm) + .value("VPMULHWZ128rmk", LIEF::assembly::x86::OPCODE::VPMULHWZ128rmk) + .value("VPMULHWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULHWZ128rmkz) + .value("VPMULHWZ128rr", LIEF::assembly::x86::OPCODE::VPMULHWZ128rr) + .value("VPMULHWZ128rrk", LIEF::assembly::x86::OPCODE::VPMULHWZ128rrk) + .value("VPMULHWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULHWZ128rrkz) + .value("VPMULHWZ256rm", LIEF::assembly::x86::OPCODE::VPMULHWZ256rm) + .value("VPMULHWZ256rmk", LIEF::assembly::x86::OPCODE::VPMULHWZ256rmk) + .value("VPMULHWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULHWZ256rmkz) + .value("VPMULHWZ256rr", LIEF::assembly::x86::OPCODE::VPMULHWZ256rr) + .value("VPMULHWZ256rrk", LIEF::assembly::x86::OPCODE::VPMULHWZ256rrk) + .value("VPMULHWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULHWZ256rrkz) + .value("VPMULHWZrm", LIEF::assembly::x86::OPCODE::VPMULHWZrm) + .value("VPMULHWZrmk", LIEF::assembly::x86::OPCODE::VPMULHWZrmk) + .value("VPMULHWZrmkz", LIEF::assembly::x86::OPCODE::VPMULHWZrmkz) + .value("VPMULHWZrr", LIEF::assembly::x86::OPCODE::VPMULHWZrr) + .value("VPMULHWZrrk", LIEF::assembly::x86::OPCODE::VPMULHWZrrk) + .value("VPMULHWZrrkz", LIEF::assembly::x86::OPCODE::VPMULHWZrrkz) + .value("VPMULHWrm", LIEF::assembly::x86::OPCODE::VPMULHWrm) + .value("VPMULHWrr", LIEF::assembly::x86::OPCODE::VPMULHWrr) + .value("VPMULLDYrm", LIEF::assembly::x86::OPCODE::VPMULLDYrm) + .value("VPMULLDYrr", LIEF::assembly::x86::OPCODE::VPMULLDYrr) + .value("VPMULLDZ128rm", LIEF::assembly::x86::OPCODE::VPMULLDZ128rm) + .value("VPMULLDZ128rmb", LIEF::assembly::x86::OPCODE::VPMULLDZ128rmb) + .value("VPMULLDZ128rmbk", LIEF::assembly::x86::OPCODE::VPMULLDZ128rmbk) + .value("VPMULLDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMULLDZ128rmbkz) + .value("VPMULLDZ128rmk", LIEF::assembly::x86::OPCODE::VPMULLDZ128rmk) + .value("VPMULLDZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULLDZ128rmkz) + .value("VPMULLDZ128rr", LIEF::assembly::x86::OPCODE::VPMULLDZ128rr) + .value("VPMULLDZ128rrk", LIEF::assembly::x86::OPCODE::VPMULLDZ128rrk) + .value("VPMULLDZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULLDZ128rrkz) + .value("VPMULLDZ256rm", LIEF::assembly::x86::OPCODE::VPMULLDZ256rm) + .value("VPMULLDZ256rmb", LIEF::assembly::x86::OPCODE::VPMULLDZ256rmb) + .value("VPMULLDZ256rmbk", LIEF::assembly::x86::OPCODE::VPMULLDZ256rmbk) + .value("VPMULLDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMULLDZ256rmbkz) + .value("VPMULLDZ256rmk", LIEF::assembly::x86::OPCODE::VPMULLDZ256rmk) + .value("VPMULLDZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULLDZ256rmkz) + .value("VPMULLDZ256rr", LIEF::assembly::x86::OPCODE::VPMULLDZ256rr) + .value("VPMULLDZ256rrk", LIEF::assembly::x86::OPCODE::VPMULLDZ256rrk) + .value("VPMULLDZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULLDZ256rrkz) + .value("VPMULLDZrm", LIEF::assembly::x86::OPCODE::VPMULLDZrm) + .value("VPMULLDZrmb", LIEF::assembly::x86::OPCODE::VPMULLDZrmb) + .value("VPMULLDZrmbk", LIEF::assembly::x86::OPCODE::VPMULLDZrmbk) + .value("VPMULLDZrmbkz", LIEF::assembly::x86::OPCODE::VPMULLDZrmbkz) + .value("VPMULLDZrmk", LIEF::assembly::x86::OPCODE::VPMULLDZrmk) + .value("VPMULLDZrmkz", LIEF::assembly::x86::OPCODE::VPMULLDZrmkz) + .value("VPMULLDZrr", LIEF::assembly::x86::OPCODE::VPMULLDZrr) + .value("VPMULLDZrrk", LIEF::assembly::x86::OPCODE::VPMULLDZrrk) + .value("VPMULLDZrrkz", LIEF::assembly::x86::OPCODE::VPMULLDZrrkz) + .value("VPMULLDrm", LIEF::assembly::x86::OPCODE::VPMULLDrm) + .value("VPMULLDrr", LIEF::assembly::x86::OPCODE::VPMULLDrr) + .value("VPMULLQZ128rm", LIEF::assembly::x86::OPCODE::VPMULLQZ128rm) + .value("VPMULLQZ128rmb", LIEF::assembly::x86::OPCODE::VPMULLQZ128rmb) + .value("VPMULLQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMULLQZ128rmbk) + .value("VPMULLQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMULLQZ128rmbkz) + .value("VPMULLQZ128rmk", LIEF::assembly::x86::OPCODE::VPMULLQZ128rmk) + .value("VPMULLQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULLQZ128rmkz) + .value("VPMULLQZ128rr", LIEF::assembly::x86::OPCODE::VPMULLQZ128rr) + .value("VPMULLQZ128rrk", LIEF::assembly::x86::OPCODE::VPMULLQZ128rrk) + .value("VPMULLQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULLQZ128rrkz) + .value("VPMULLQZ256rm", LIEF::assembly::x86::OPCODE::VPMULLQZ256rm) + .value("VPMULLQZ256rmb", LIEF::assembly::x86::OPCODE::VPMULLQZ256rmb) + .value("VPMULLQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMULLQZ256rmbk) + .value("VPMULLQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMULLQZ256rmbkz) + .value("VPMULLQZ256rmk", LIEF::assembly::x86::OPCODE::VPMULLQZ256rmk) + .value("VPMULLQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULLQZ256rmkz) + .value("VPMULLQZ256rr", LIEF::assembly::x86::OPCODE::VPMULLQZ256rr) + .value("VPMULLQZ256rrk", LIEF::assembly::x86::OPCODE::VPMULLQZ256rrk) + .value("VPMULLQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULLQZ256rrkz) + .value("VPMULLQZrm", LIEF::assembly::x86::OPCODE::VPMULLQZrm) + .value("VPMULLQZrmb", LIEF::assembly::x86::OPCODE::VPMULLQZrmb) + .value("VPMULLQZrmbk", LIEF::assembly::x86::OPCODE::VPMULLQZrmbk) + .value("VPMULLQZrmbkz", LIEF::assembly::x86::OPCODE::VPMULLQZrmbkz) + .value("VPMULLQZrmk", LIEF::assembly::x86::OPCODE::VPMULLQZrmk) + .value("VPMULLQZrmkz", LIEF::assembly::x86::OPCODE::VPMULLQZrmkz) + .value("VPMULLQZrr", LIEF::assembly::x86::OPCODE::VPMULLQZrr) + .value("VPMULLQZrrk", LIEF::assembly::x86::OPCODE::VPMULLQZrrk) + .value("VPMULLQZrrkz", LIEF::assembly::x86::OPCODE::VPMULLQZrrkz) + .value("VPMULLWYrm", LIEF::assembly::x86::OPCODE::VPMULLWYrm) + .value("VPMULLWYrr", LIEF::assembly::x86::OPCODE::VPMULLWYrr) + .value("VPMULLWZ128rm", LIEF::assembly::x86::OPCODE::VPMULLWZ128rm) + .value("VPMULLWZ128rmk", LIEF::assembly::x86::OPCODE::VPMULLWZ128rmk) + .value("VPMULLWZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULLWZ128rmkz) + .value("VPMULLWZ128rr", LIEF::assembly::x86::OPCODE::VPMULLWZ128rr) + .value("VPMULLWZ128rrk", LIEF::assembly::x86::OPCODE::VPMULLWZ128rrk) + .value("VPMULLWZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULLWZ128rrkz) + .value("VPMULLWZ256rm", LIEF::assembly::x86::OPCODE::VPMULLWZ256rm) + .value("VPMULLWZ256rmk", LIEF::assembly::x86::OPCODE::VPMULLWZ256rmk) + .value("VPMULLWZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULLWZ256rmkz) + .value("VPMULLWZ256rr", LIEF::assembly::x86::OPCODE::VPMULLWZ256rr) + .value("VPMULLWZ256rrk", LIEF::assembly::x86::OPCODE::VPMULLWZ256rrk) + .value("VPMULLWZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULLWZ256rrkz) + .value("VPMULLWZrm", LIEF::assembly::x86::OPCODE::VPMULLWZrm) + .value("VPMULLWZrmk", LIEF::assembly::x86::OPCODE::VPMULLWZrmk) + .value("VPMULLWZrmkz", LIEF::assembly::x86::OPCODE::VPMULLWZrmkz) + .value("VPMULLWZrr", LIEF::assembly::x86::OPCODE::VPMULLWZrr) + .value("VPMULLWZrrk", LIEF::assembly::x86::OPCODE::VPMULLWZrrk) + .value("VPMULLWZrrkz", LIEF::assembly::x86::OPCODE::VPMULLWZrrkz) + .value("VPMULLWrm", LIEF::assembly::x86::OPCODE::VPMULLWrm) + .value("VPMULLWrr", LIEF::assembly::x86::OPCODE::VPMULLWrr) + .value("VPMULTISHIFTQBZ128rm", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rm) + .value("VPMULTISHIFTQBZ128rmb", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rmb) + .value("VPMULTISHIFTQBZ128rmbk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rmbk) + .value("VPMULTISHIFTQBZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rmbkz) + .value("VPMULTISHIFTQBZ128rmk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rmk) + .value("VPMULTISHIFTQBZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rmkz) + .value("VPMULTISHIFTQBZ128rr", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rr) + .value("VPMULTISHIFTQBZ128rrk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rrk) + .value("VPMULTISHIFTQBZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ128rrkz) + .value("VPMULTISHIFTQBZ256rm", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rm) + .value("VPMULTISHIFTQBZ256rmb", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rmb) + .value("VPMULTISHIFTQBZ256rmbk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rmbk) + .value("VPMULTISHIFTQBZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rmbkz) + .value("VPMULTISHIFTQBZ256rmk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rmk) + .value("VPMULTISHIFTQBZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rmkz) + .value("VPMULTISHIFTQBZ256rr", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rr) + .value("VPMULTISHIFTQBZ256rrk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rrk) + .value("VPMULTISHIFTQBZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZ256rrkz) + .value("VPMULTISHIFTQBZrm", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrm) + .value("VPMULTISHIFTQBZrmb", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrmb) + .value("VPMULTISHIFTQBZrmbk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrmbk) + .value("VPMULTISHIFTQBZrmbkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrmbkz) + .value("VPMULTISHIFTQBZrmk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrmk) + .value("VPMULTISHIFTQBZrmkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrmkz) + .value("VPMULTISHIFTQBZrr", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrr) + .value("VPMULTISHIFTQBZrrk", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrrk) + .value("VPMULTISHIFTQBZrrkz", LIEF::assembly::x86::OPCODE::VPMULTISHIFTQBZrrkz) + .value("VPMULUDQYrm", LIEF::assembly::x86::OPCODE::VPMULUDQYrm) + .value("VPMULUDQYrr", LIEF::assembly::x86::OPCODE::VPMULUDQYrr) + .value("VPMULUDQZ128rm", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rm) + .value("VPMULUDQZ128rmb", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rmb) + .value("VPMULUDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rmbk) + .value("VPMULUDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rmbkz) + .value("VPMULUDQZ128rmk", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rmk) + .value("VPMULUDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rmkz) + .value("VPMULUDQZ128rr", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rr) + .value("VPMULUDQZ128rrk", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rrk) + .value("VPMULUDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ128rrkz) + .value("VPMULUDQZ256rm", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rm) + .value("VPMULUDQZ256rmb", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rmb) + .value("VPMULUDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rmbk) + .value("VPMULUDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rmbkz) + .value("VPMULUDQZ256rmk", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rmk) + .value("VPMULUDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rmkz) + .value("VPMULUDQZ256rr", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rr) + .value("VPMULUDQZ256rrk", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rrk) + .value("VPMULUDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPMULUDQZ256rrkz) + .value("VPMULUDQZrm", LIEF::assembly::x86::OPCODE::VPMULUDQZrm) + .value("VPMULUDQZrmb", LIEF::assembly::x86::OPCODE::VPMULUDQZrmb) + .value("VPMULUDQZrmbk", LIEF::assembly::x86::OPCODE::VPMULUDQZrmbk) + .value("VPMULUDQZrmbkz", LIEF::assembly::x86::OPCODE::VPMULUDQZrmbkz) + .value("VPMULUDQZrmk", LIEF::assembly::x86::OPCODE::VPMULUDQZrmk) + .value("VPMULUDQZrmkz", LIEF::assembly::x86::OPCODE::VPMULUDQZrmkz) + .value("VPMULUDQZrr", LIEF::assembly::x86::OPCODE::VPMULUDQZrr) + .value("VPMULUDQZrrk", LIEF::assembly::x86::OPCODE::VPMULUDQZrrk) + .value("VPMULUDQZrrkz", LIEF::assembly::x86::OPCODE::VPMULUDQZrrkz) + .value("VPMULUDQrm", LIEF::assembly::x86::OPCODE::VPMULUDQrm) + .value("VPMULUDQrr", LIEF::assembly::x86::OPCODE::VPMULUDQrr) + .value("VPOPCNTBZ128rm", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rm) + .value("VPOPCNTBZ128rmk", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rmk) + .value("VPOPCNTBZ128rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rmkz) + .value("VPOPCNTBZ128rr", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rr) + .value("VPOPCNTBZ128rrk", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rrk) + .value("VPOPCNTBZ128rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZ128rrkz) + .value("VPOPCNTBZ256rm", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rm) + .value("VPOPCNTBZ256rmk", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rmk) + .value("VPOPCNTBZ256rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rmkz) + .value("VPOPCNTBZ256rr", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rr) + .value("VPOPCNTBZ256rrk", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rrk) + .value("VPOPCNTBZ256rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZ256rrkz) + .value("VPOPCNTBZrm", LIEF::assembly::x86::OPCODE::VPOPCNTBZrm) + .value("VPOPCNTBZrmk", LIEF::assembly::x86::OPCODE::VPOPCNTBZrmk) + .value("VPOPCNTBZrmkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZrmkz) + .value("VPOPCNTBZrr", LIEF::assembly::x86::OPCODE::VPOPCNTBZrr) + .value("VPOPCNTBZrrk", LIEF::assembly::x86::OPCODE::VPOPCNTBZrrk) + .value("VPOPCNTBZrrkz", LIEF::assembly::x86::OPCODE::VPOPCNTBZrrkz) + .value("VPOPCNTDZ128rm", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rm) + .value("VPOPCNTDZ128rmb", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rmb) + .value("VPOPCNTDZ128rmbk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rmbk) + .value("VPOPCNTDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rmbkz) + .value("VPOPCNTDZ128rmk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rmk) + .value("VPOPCNTDZ128rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rmkz) + .value("VPOPCNTDZ128rr", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rr) + .value("VPOPCNTDZ128rrk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rrk) + .value("VPOPCNTDZ128rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ128rrkz) + .value("VPOPCNTDZ256rm", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rm) + .value("VPOPCNTDZ256rmb", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rmb) + .value("VPOPCNTDZ256rmbk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rmbk) + .value("VPOPCNTDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rmbkz) + .value("VPOPCNTDZ256rmk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rmk) + .value("VPOPCNTDZ256rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rmkz) + .value("VPOPCNTDZ256rr", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rr) + .value("VPOPCNTDZ256rrk", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rrk) + .value("VPOPCNTDZ256rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZ256rrkz) + .value("VPOPCNTDZrm", LIEF::assembly::x86::OPCODE::VPOPCNTDZrm) + .value("VPOPCNTDZrmb", LIEF::assembly::x86::OPCODE::VPOPCNTDZrmb) + .value("VPOPCNTDZrmbk", LIEF::assembly::x86::OPCODE::VPOPCNTDZrmbk) + .value("VPOPCNTDZrmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZrmbkz) + .value("VPOPCNTDZrmk", LIEF::assembly::x86::OPCODE::VPOPCNTDZrmk) + .value("VPOPCNTDZrmkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZrmkz) + .value("VPOPCNTDZrr", LIEF::assembly::x86::OPCODE::VPOPCNTDZrr) + .value("VPOPCNTDZrrk", LIEF::assembly::x86::OPCODE::VPOPCNTDZrrk) + .value("VPOPCNTDZrrkz", LIEF::assembly::x86::OPCODE::VPOPCNTDZrrkz) + .value("VPOPCNTQZ128rm", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rm) + .value("VPOPCNTQZ128rmb", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rmb) + .value("VPOPCNTQZ128rmbk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rmbk) + .value("VPOPCNTQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rmbkz) + .value("VPOPCNTQZ128rmk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rmk) + .value("VPOPCNTQZ128rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rmkz) + .value("VPOPCNTQZ128rr", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rr) + .value("VPOPCNTQZ128rrk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rrk); + opcodes.value("VPOPCNTQZ128rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ128rrkz) + .value("VPOPCNTQZ256rm", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rm) + .value("VPOPCNTQZ256rmb", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rmb) + .value("VPOPCNTQZ256rmbk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rmbk) + .value("VPOPCNTQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rmbkz) + .value("VPOPCNTQZ256rmk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rmk) + .value("VPOPCNTQZ256rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rmkz) + .value("VPOPCNTQZ256rr", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rr) + .value("VPOPCNTQZ256rrk", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rrk) + .value("VPOPCNTQZ256rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZ256rrkz) + .value("VPOPCNTQZrm", LIEF::assembly::x86::OPCODE::VPOPCNTQZrm) + .value("VPOPCNTQZrmb", LIEF::assembly::x86::OPCODE::VPOPCNTQZrmb) + .value("VPOPCNTQZrmbk", LIEF::assembly::x86::OPCODE::VPOPCNTQZrmbk) + .value("VPOPCNTQZrmbkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZrmbkz) + .value("VPOPCNTQZrmk", LIEF::assembly::x86::OPCODE::VPOPCNTQZrmk) + .value("VPOPCNTQZrmkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZrmkz) + .value("VPOPCNTQZrr", LIEF::assembly::x86::OPCODE::VPOPCNTQZrr) + .value("VPOPCNTQZrrk", LIEF::assembly::x86::OPCODE::VPOPCNTQZrrk) + .value("VPOPCNTQZrrkz", LIEF::assembly::x86::OPCODE::VPOPCNTQZrrkz) + .value("VPOPCNTWZ128rm", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rm) + .value("VPOPCNTWZ128rmk", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rmk) + .value("VPOPCNTWZ128rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rmkz) + .value("VPOPCNTWZ128rr", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rr) + .value("VPOPCNTWZ128rrk", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rrk) + .value("VPOPCNTWZ128rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZ128rrkz) + .value("VPOPCNTWZ256rm", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rm) + .value("VPOPCNTWZ256rmk", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rmk) + .value("VPOPCNTWZ256rmkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rmkz) + .value("VPOPCNTWZ256rr", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rr) + .value("VPOPCNTWZ256rrk", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rrk) + .value("VPOPCNTWZ256rrkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZ256rrkz) + .value("VPOPCNTWZrm", LIEF::assembly::x86::OPCODE::VPOPCNTWZrm) + .value("VPOPCNTWZrmk", LIEF::assembly::x86::OPCODE::VPOPCNTWZrmk) + .value("VPOPCNTWZrmkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZrmkz) + .value("VPOPCNTWZrr", LIEF::assembly::x86::OPCODE::VPOPCNTWZrr) + .value("VPOPCNTWZrrk", LIEF::assembly::x86::OPCODE::VPOPCNTWZrrk) + .value("VPOPCNTWZrrkz", LIEF::assembly::x86::OPCODE::VPOPCNTWZrrkz) + .value("VPORDZ128rm", LIEF::assembly::x86::OPCODE::VPORDZ128rm) + .value("VPORDZ128rmb", LIEF::assembly::x86::OPCODE::VPORDZ128rmb) + .value("VPORDZ128rmbk", LIEF::assembly::x86::OPCODE::VPORDZ128rmbk) + .value("VPORDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPORDZ128rmbkz) + .value("VPORDZ128rmk", LIEF::assembly::x86::OPCODE::VPORDZ128rmk) + .value("VPORDZ128rmkz", LIEF::assembly::x86::OPCODE::VPORDZ128rmkz) + .value("VPORDZ128rr", LIEF::assembly::x86::OPCODE::VPORDZ128rr) + .value("VPORDZ128rrk", LIEF::assembly::x86::OPCODE::VPORDZ128rrk) + .value("VPORDZ128rrkz", LIEF::assembly::x86::OPCODE::VPORDZ128rrkz) + .value("VPORDZ256rm", LIEF::assembly::x86::OPCODE::VPORDZ256rm) + .value("VPORDZ256rmb", LIEF::assembly::x86::OPCODE::VPORDZ256rmb) + .value("VPORDZ256rmbk", LIEF::assembly::x86::OPCODE::VPORDZ256rmbk) + .value("VPORDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPORDZ256rmbkz) + .value("VPORDZ256rmk", LIEF::assembly::x86::OPCODE::VPORDZ256rmk) + .value("VPORDZ256rmkz", LIEF::assembly::x86::OPCODE::VPORDZ256rmkz) + .value("VPORDZ256rr", LIEF::assembly::x86::OPCODE::VPORDZ256rr) + .value("VPORDZ256rrk", LIEF::assembly::x86::OPCODE::VPORDZ256rrk) + .value("VPORDZ256rrkz", LIEF::assembly::x86::OPCODE::VPORDZ256rrkz) + .value("VPORDZrm", LIEF::assembly::x86::OPCODE::VPORDZrm) + .value("VPORDZrmb", LIEF::assembly::x86::OPCODE::VPORDZrmb) + .value("VPORDZrmbk", LIEF::assembly::x86::OPCODE::VPORDZrmbk) + .value("VPORDZrmbkz", LIEF::assembly::x86::OPCODE::VPORDZrmbkz) + .value("VPORDZrmk", LIEF::assembly::x86::OPCODE::VPORDZrmk) + .value("VPORDZrmkz", LIEF::assembly::x86::OPCODE::VPORDZrmkz) + .value("VPORDZrr", LIEF::assembly::x86::OPCODE::VPORDZrr) + .value("VPORDZrrk", LIEF::assembly::x86::OPCODE::VPORDZrrk) + .value("VPORDZrrkz", LIEF::assembly::x86::OPCODE::VPORDZrrkz) + .value("VPORQZ128rm", LIEF::assembly::x86::OPCODE::VPORQZ128rm) + .value("VPORQZ128rmb", LIEF::assembly::x86::OPCODE::VPORQZ128rmb) + .value("VPORQZ128rmbk", LIEF::assembly::x86::OPCODE::VPORQZ128rmbk) + .value("VPORQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPORQZ128rmbkz) + .value("VPORQZ128rmk", LIEF::assembly::x86::OPCODE::VPORQZ128rmk) + .value("VPORQZ128rmkz", LIEF::assembly::x86::OPCODE::VPORQZ128rmkz) + .value("VPORQZ128rr", LIEF::assembly::x86::OPCODE::VPORQZ128rr) + .value("VPORQZ128rrk", LIEF::assembly::x86::OPCODE::VPORQZ128rrk) + .value("VPORQZ128rrkz", LIEF::assembly::x86::OPCODE::VPORQZ128rrkz) + .value("VPORQZ256rm", LIEF::assembly::x86::OPCODE::VPORQZ256rm) + .value("VPORQZ256rmb", LIEF::assembly::x86::OPCODE::VPORQZ256rmb) + .value("VPORQZ256rmbk", LIEF::assembly::x86::OPCODE::VPORQZ256rmbk) + .value("VPORQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPORQZ256rmbkz) + .value("VPORQZ256rmk", LIEF::assembly::x86::OPCODE::VPORQZ256rmk) + .value("VPORQZ256rmkz", LIEF::assembly::x86::OPCODE::VPORQZ256rmkz) + .value("VPORQZ256rr", LIEF::assembly::x86::OPCODE::VPORQZ256rr) + .value("VPORQZ256rrk", LIEF::assembly::x86::OPCODE::VPORQZ256rrk) + .value("VPORQZ256rrkz", LIEF::assembly::x86::OPCODE::VPORQZ256rrkz) + .value("VPORQZrm", LIEF::assembly::x86::OPCODE::VPORQZrm) + .value("VPORQZrmb", LIEF::assembly::x86::OPCODE::VPORQZrmb) + .value("VPORQZrmbk", LIEF::assembly::x86::OPCODE::VPORQZrmbk) + .value("VPORQZrmbkz", LIEF::assembly::x86::OPCODE::VPORQZrmbkz) + .value("VPORQZrmk", LIEF::assembly::x86::OPCODE::VPORQZrmk) + .value("VPORQZrmkz", LIEF::assembly::x86::OPCODE::VPORQZrmkz) + .value("VPORQZrr", LIEF::assembly::x86::OPCODE::VPORQZrr) + .value("VPORQZrrk", LIEF::assembly::x86::OPCODE::VPORQZrrk) + .value("VPORQZrrkz", LIEF::assembly::x86::OPCODE::VPORQZrrkz) + .value("VPORYrm", LIEF::assembly::x86::OPCODE::VPORYrm) + .value("VPORYrr", LIEF::assembly::x86::OPCODE::VPORYrr) + .value("VPORrm", LIEF::assembly::x86::OPCODE::VPORrm) + .value("VPORrr", LIEF::assembly::x86::OPCODE::VPORrr) + .value("VPPERMrmr", LIEF::assembly::x86::OPCODE::VPPERMrmr) + .value("VPPERMrrm", LIEF::assembly::x86::OPCODE::VPPERMrrm) + .value("VPPERMrrr", LIEF::assembly::x86::OPCODE::VPPERMrrr) + .value("VPPERMrrr_REV", LIEF::assembly::x86::OPCODE::VPPERMrrr_REV) + .value("VPROLDZ128mbi", LIEF::assembly::x86::OPCODE::VPROLDZ128mbi) + .value("VPROLDZ128mbik", LIEF::assembly::x86::OPCODE::VPROLDZ128mbik) + .value("VPROLDZ128mbikz", LIEF::assembly::x86::OPCODE::VPROLDZ128mbikz) + .value("VPROLDZ128mi", LIEF::assembly::x86::OPCODE::VPROLDZ128mi) + .value("VPROLDZ128mik", LIEF::assembly::x86::OPCODE::VPROLDZ128mik) + .value("VPROLDZ128mikz", LIEF::assembly::x86::OPCODE::VPROLDZ128mikz) + .value("VPROLDZ128ri", LIEF::assembly::x86::OPCODE::VPROLDZ128ri) + .value("VPROLDZ128rik", LIEF::assembly::x86::OPCODE::VPROLDZ128rik) + .value("VPROLDZ128rikz", LIEF::assembly::x86::OPCODE::VPROLDZ128rikz) + .value("VPROLDZ256mbi", LIEF::assembly::x86::OPCODE::VPROLDZ256mbi) + .value("VPROLDZ256mbik", LIEF::assembly::x86::OPCODE::VPROLDZ256mbik) + .value("VPROLDZ256mbikz", LIEF::assembly::x86::OPCODE::VPROLDZ256mbikz) + .value("VPROLDZ256mi", LIEF::assembly::x86::OPCODE::VPROLDZ256mi) + .value("VPROLDZ256mik", LIEF::assembly::x86::OPCODE::VPROLDZ256mik) + .value("VPROLDZ256mikz", LIEF::assembly::x86::OPCODE::VPROLDZ256mikz) + .value("VPROLDZ256ri", LIEF::assembly::x86::OPCODE::VPROLDZ256ri) + .value("VPROLDZ256rik", LIEF::assembly::x86::OPCODE::VPROLDZ256rik) + .value("VPROLDZ256rikz", LIEF::assembly::x86::OPCODE::VPROLDZ256rikz) + .value("VPROLDZmbi", LIEF::assembly::x86::OPCODE::VPROLDZmbi) + .value("VPROLDZmbik", LIEF::assembly::x86::OPCODE::VPROLDZmbik) + .value("VPROLDZmbikz", LIEF::assembly::x86::OPCODE::VPROLDZmbikz) + .value("VPROLDZmi", LIEF::assembly::x86::OPCODE::VPROLDZmi) + .value("VPROLDZmik", LIEF::assembly::x86::OPCODE::VPROLDZmik) + .value("VPROLDZmikz", LIEF::assembly::x86::OPCODE::VPROLDZmikz) + .value("VPROLDZri", LIEF::assembly::x86::OPCODE::VPROLDZri) + .value("VPROLDZrik", LIEF::assembly::x86::OPCODE::VPROLDZrik) + .value("VPROLDZrikz", LIEF::assembly::x86::OPCODE::VPROLDZrikz) + .value("VPROLQZ128mbi", LIEF::assembly::x86::OPCODE::VPROLQZ128mbi) + .value("VPROLQZ128mbik", LIEF::assembly::x86::OPCODE::VPROLQZ128mbik) + .value("VPROLQZ128mbikz", LIEF::assembly::x86::OPCODE::VPROLQZ128mbikz) + .value("VPROLQZ128mi", LIEF::assembly::x86::OPCODE::VPROLQZ128mi) + .value("VPROLQZ128mik", LIEF::assembly::x86::OPCODE::VPROLQZ128mik) + .value("VPROLQZ128mikz", LIEF::assembly::x86::OPCODE::VPROLQZ128mikz) + .value("VPROLQZ128ri", LIEF::assembly::x86::OPCODE::VPROLQZ128ri) + .value("VPROLQZ128rik", LIEF::assembly::x86::OPCODE::VPROLQZ128rik) + .value("VPROLQZ128rikz", LIEF::assembly::x86::OPCODE::VPROLQZ128rikz) + .value("VPROLQZ256mbi", LIEF::assembly::x86::OPCODE::VPROLQZ256mbi) + .value("VPROLQZ256mbik", LIEF::assembly::x86::OPCODE::VPROLQZ256mbik) + .value("VPROLQZ256mbikz", LIEF::assembly::x86::OPCODE::VPROLQZ256mbikz) + .value("VPROLQZ256mi", LIEF::assembly::x86::OPCODE::VPROLQZ256mi) + .value("VPROLQZ256mik", LIEF::assembly::x86::OPCODE::VPROLQZ256mik) + .value("VPROLQZ256mikz", LIEF::assembly::x86::OPCODE::VPROLQZ256mikz) + .value("VPROLQZ256ri", LIEF::assembly::x86::OPCODE::VPROLQZ256ri) + .value("VPROLQZ256rik", LIEF::assembly::x86::OPCODE::VPROLQZ256rik) + .value("VPROLQZ256rikz", LIEF::assembly::x86::OPCODE::VPROLQZ256rikz) + .value("VPROLQZmbi", LIEF::assembly::x86::OPCODE::VPROLQZmbi) + .value("VPROLQZmbik", LIEF::assembly::x86::OPCODE::VPROLQZmbik) + .value("VPROLQZmbikz", LIEF::assembly::x86::OPCODE::VPROLQZmbikz) + .value("VPROLQZmi", LIEF::assembly::x86::OPCODE::VPROLQZmi) + .value("VPROLQZmik", LIEF::assembly::x86::OPCODE::VPROLQZmik) + .value("VPROLQZmikz", LIEF::assembly::x86::OPCODE::VPROLQZmikz) + .value("VPROLQZri", LIEF::assembly::x86::OPCODE::VPROLQZri) + .value("VPROLQZrik", LIEF::assembly::x86::OPCODE::VPROLQZrik) + .value("VPROLQZrikz", LIEF::assembly::x86::OPCODE::VPROLQZrikz) + .value("VPROLVDZ128rm", LIEF::assembly::x86::OPCODE::VPROLVDZ128rm) + .value("VPROLVDZ128rmb", LIEF::assembly::x86::OPCODE::VPROLVDZ128rmb) + .value("VPROLVDZ128rmbk", LIEF::assembly::x86::OPCODE::VPROLVDZ128rmbk) + .value("VPROLVDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPROLVDZ128rmbkz) + .value("VPROLVDZ128rmk", LIEF::assembly::x86::OPCODE::VPROLVDZ128rmk) + .value("VPROLVDZ128rmkz", LIEF::assembly::x86::OPCODE::VPROLVDZ128rmkz) + .value("VPROLVDZ128rr", LIEF::assembly::x86::OPCODE::VPROLVDZ128rr) + .value("VPROLVDZ128rrk", LIEF::assembly::x86::OPCODE::VPROLVDZ128rrk) + .value("VPROLVDZ128rrkz", LIEF::assembly::x86::OPCODE::VPROLVDZ128rrkz) + .value("VPROLVDZ256rm", LIEF::assembly::x86::OPCODE::VPROLVDZ256rm) + .value("VPROLVDZ256rmb", LIEF::assembly::x86::OPCODE::VPROLVDZ256rmb) + .value("VPROLVDZ256rmbk", LIEF::assembly::x86::OPCODE::VPROLVDZ256rmbk) + .value("VPROLVDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPROLVDZ256rmbkz) + .value("VPROLVDZ256rmk", LIEF::assembly::x86::OPCODE::VPROLVDZ256rmk) + .value("VPROLVDZ256rmkz", LIEF::assembly::x86::OPCODE::VPROLVDZ256rmkz) + .value("VPROLVDZ256rr", LIEF::assembly::x86::OPCODE::VPROLVDZ256rr) + .value("VPROLVDZ256rrk", LIEF::assembly::x86::OPCODE::VPROLVDZ256rrk) + .value("VPROLVDZ256rrkz", LIEF::assembly::x86::OPCODE::VPROLVDZ256rrkz) + .value("VPROLVDZrm", LIEF::assembly::x86::OPCODE::VPROLVDZrm) + .value("VPROLVDZrmb", LIEF::assembly::x86::OPCODE::VPROLVDZrmb) + .value("VPROLVDZrmbk", LIEF::assembly::x86::OPCODE::VPROLVDZrmbk) + .value("VPROLVDZrmbkz", LIEF::assembly::x86::OPCODE::VPROLVDZrmbkz) + .value("VPROLVDZrmk", LIEF::assembly::x86::OPCODE::VPROLVDZrmk) + .value("VPROLVDZrmkz", LIEF::assembly::x86::OPCODE::VPROLVDZrmkz) + .value("VPROLVDZrr", LIEF::assembly::x86::OPCODE::VPROLVDZrr) + .value("VPROLVDZrrk", LIEF::assembly::x86::OPCODE::VPROLVDZrrk) + .value("VPROLVDZrrkz", LIEF::assembly::x86::OPCODE::VPROLVDZrrkz) + .value("VPROLVQZ128rm", LIEF::assembly::x86::OPCODE::VPROLVQZ128rm) + .value("VPROLVQZ128rmb", LIEF::assembly::x86::OPCODE::VPROLVQZ128rmb) + .value("VPROLVQZ128rmbk", LIEF::assembly::x86::OPCODE::VPROLVQZ128rmbk) + .value("VPROLVQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPROLVQZ128rmbkz) + .value("VPROLVQZ128rmk", LIEF::assembly::x86::OPCODE::VPROLVQZ128rmk) + .value("VPROLVQZ128rmkz", LIEF::assembly::x86::OPCODE::VPROLVQZ128rmkz) + .value("VPROLVQZ128rr", LIEF::assembly::x86::OPCODE::VPROLVQZ128rr) + .value("VPROLVQZ128rrk", LIEF::assembly::x86::OPCODE::VPROLVQZ128rrk) + .value("VPROLVQZ128rrkz", LIEF::assembly::x86::OPCODE::VPROLVQZ128rrkz) + .value("VPROLVQZ256rm", LIEF::assembly::x86::OPCODE::VPROLVQZ256rm) + .value("VPROLVQZ256rmb", LIEF::assembly::x86::OPCODE::VPROLVQZ256rmb) + .value("VPROLVQZ256rmbk", LIEF::assembly::x86::OPCODE::VPROLVQZ256rmbk) + .value("VPROLVQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPROLVQZ256rmbkz) + .value("VPROLVQZ256rmk", LIEF::assembly::x86::OPCODE::VPROLVQZ256rmk) + .value("VPROLVQZ256rmkz", LIEF::assembly::x86::OPCODE::VPROLVQZ256rmkz) + .value("VPROLVQZ256rr", LIEF::assembly::x86::OPCODE::VPROLVQZ256rr) + .value("VPROLVQZ256rrk", LIEF::assembly::x86::OPCODE::VPROLVQZ256rrk) + .value("VPROLVQZ256rrkz", LIEF::assembly::x86::OPCODE::VPROLVQZ256rrkz) + .value("VPROLVQZrm", LIEF::assembly::x86::OPCODE::VPROLVQZrm) + .value("VPROLVQZrmb", LIEF::assembly::x86::OPCODE::VPROLVQZrmb) + .value("VPROLVQZrmbk", LIEF::assembly::x86::OPCODE::VPROLVQZrmbk) + .value("VPROLVQZrmbkz", LIEF::assembly::x86::OPCODE::VPROLVQZrmbkz) + .value("VPROLVQZrmk", LIEF::assembly::x86::OPCODE::VPROLVQZrmk) + .value("VPROLVQZrmkz", LIEF::assembly::x86::OPCODE::VPROLVQZrmkz) + .value("VPROLVQZrr", LIEF::assembly::x86::OPCODE::VPROLVQZrr) + .value("VPROLVQZrrk", LIEF::assembly::x86::OPCODE::VPROLVQZrrk) + .value("VPROLVQZrrkz", LIEF::assembly::x86::OPCODE::VPROLVQZrrkz) + .value("VPRORDZ128mbi", LIEF::assembly::x86::OPCODE::VPRORDZ128mbi) + .value("VPRORDZ128mbik", LIEF::assembly::x86::OPCODE::VPRORDZ128mbik) + .value("VPRORDZ128mbikz", LIEF::assembly::x86::OPCODE::VPRORDZ128mbikz) + .value("VPRORDZ128mi", LIEF::assembly::x86::OPCODE::VPRORDZ128mi) + .value("VPRORDZ128mik", LIEF::assembly::x86::OPCODE::VPRORDZ128mik) + .value("VPRORDZ128mikz", LIEF::assembly::x86::OPCODE::VPRORDZ128mikz) + .value("VPRORDZ128ri", LIEF::assembly::x86::OPCODE::VPRORDZ128ri) + .value("VPRORDZ128rik", LIEF::assembly::x86::OPCODE::VPRORDZ128rik) + .value("VPRORDZ128rikz", LIEF::assembly::x86::OPCODE::VPRORDZ128rikz) + .value("VPRORDZ256mbi", LIEF::assembly::x86::OPCODE::VPRORDZ256mbi) + .value("VPRORDZ256mbik", LIEF::assembly::x86::OPCODE::VPRORDZ256mbik) + .value("VPRORDZ256mbikz", LIEF::assembly::x86::OPCODE::VPRORDZ256mbikz) + .value("VPRORDZ256mi", LIEF::assembly::x86::OPCODE::VPRORDZ256mi) + .value("VPRORDZ256mik", LIEF::assembly::x86::OPCODE::VPRORDZ256mik) + .value("VPRORDZ256mikz", LIEF::assembly::x86::OPCODE::VPRORDZ256mikz) + .value("VPRORDZ256ri", LIEF::assembly::x86::OPCODE::VPRORDZ256ri) + .value("VPRORDZ256rik", LIEF::assembly::x86::OPCODE::VPRORDZ256rik) + .value("VPRORDZ256rikz", LIEF::assembly::x86::OPCODE::VPRORDZ256rikz) + .value("VPRORDZmbi", LIEF::assembly::x86::OPCODE::VPRORDZmbi) + .value("VPRORDZmbik", LIEF::assembly::x86::OPCODE::VPRORDZmbik) + .value("VPRORDZmbikz", LIEF::assembly::x86::OPCODE::VPRORDZmbikz) + .value("VPRORDZmi", LIEF::assembly::x86::OPCODE::VPRORDZmi) + .value("VPRORDZmik", LIEF::assembly::x86::OPCODE::VPRORDZmik) + .value("VPRORDZmikz", LIEF::assembly::x86::OPCODE::VPRORDZmikz) + .value("VPRORDZri", LIEF::assembly::x86::OPCODE::VPRORDZri) + .value("VPRORDZrik", LIEF::assembly::x86::OPCODE::VPRORDZrik) + .value("VPRORDZrikz", LIEF::assembly::x86::OPCODE::VPRORDZrikz) + .value("VPRORQZ128mbi", LIEF::assembly::x86::OPCODE::VPRORQZ128mbi) + .value("VPRORQZ128mbik", LIEF::assembly::x86::OPCODE::VPRORQZ128mbik) + .value("VPRORQZ128mbikz", LIEF::assembly::x86::OPCODE::VPRORQZ128mbikz) + .value("VPRORQZ128mi", LIEF::assembly::x86::OPCODE::VPRORQZ128mi) + .value("VPRORQZ128mik", LIEF::assembly::x86::OPCODE::VPRORQZ128mik) + .value("VPRORQZ128mikz", LIEF::assembly::x86::OPCODE::VPRORQZ128mikz) + .value("VPRORQZ128ri", LIEF::assembly::x86::OPCODE::VPRORQZ128ri) + .value("VPRORQZ128rik", LIEF::assembly::x86::OPCODE::VPRORQZ128rik) + .value("VPRORQZ128rikz", LIEF::assembly::x86::OPCODE::VPRORQZ128rikz) + .value("VPRORQZ256mbi", LIEF::assembly::x86::OPCODE::VPRORQZ256mbi) + .value("VPRORQZ256mbik", LIEF::assembly::x86::OPCODE::VPRORQZ256mbik) + .value("VPRORQZ256mbikz", LIEF::assembly::x86::OPCODE::VPRORQZ256mbikz) + .value("VPRORQZ256mi", LIEF::assembly::x86::OPCODE::VPRORQZ256mi) + .value("VPRORQZ256mik", LIEF::assembly::x86::OPCODE::VPRORQZ256mik) + .value("VPRORQZ256mikz", LIEF::assembly::x86::OPCODE::VPRORQZ256mikz) + .value("VPRORQZ256ri", LIEF::assembly::x86::OPCODE::VPRORQZ256ri) + .value("VPRORQZ256rik", LIEF::assembly::x86::OPCODE::VPRORQZ256rik) + .value("VPRORQZ256rikz", LIEF::assembly::x86::OPCODE::VPRORQZ256rikz) + .value("VPRORQZmbi", LIEF::assembly::x86::OPCODE::VPRORQZmbi) + .value("VPRORQZmbik", LIEF::assembly::x86::OPCODE::VPRORQZmbik) + .value("VPRORQZmbikz", LIEF::assembly::x86::OPCODE::VPRORQZmbikz) + .value("VPRORQZmi", LIEF::assembly::x86::OPCODE::VPRORQZmi) + .value("VPRORQZmik", LIEF::assembly::x86::OPCODE::VPRORQZmik) + .value("VPRORQZmikz", LIEF::assembly::x86::OPCODE::VPRORQZmikz) + .value("VPRORQZri", LIEF::assembly::x86::OPCODE::VPRORQZri) + .value("VPRORQZrik", LIEF::assembly::x86::OPCODE::VPRORQZrik) + .value("VPRORQZrikz", LIEF::assembly::x86::OPCODE::VPRORQZrikz) + .value("VPRORVDZ128rm", LIEF::assembly::x86::OPCODE::VPRORVDZ128rm) + .value("VPRORVDZ128rmb", LIEF::assembly::x86::OPCODE::VPRORVDZ128rmb) + .value("VPRORVDZ128rmbk", LIEF::assembly::x86::OPCODE::VPRORVDZ128rmbk) + .value("VPRORVDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPRORVDZ128rmbkz) + .value("VPRORVDZ128rmk", LIEF::assembly::x86::OPCODE::VPRORVDZ128rmk) + .value("VPRORVDZ128rmkz", LIEF::assembly::x86::OPCODE::VPRORVDZ128rmkz) + .value("VPRORVDZ128rr", LIEF::assembly::x86::OPCODE::VPRORVDZ128rr) + .value("VPRORVDZ128rrk", LIEF::assembly::x86::OPCODE::VPRORVDZ128rrk) + .value("VPRORVDZ128rrkz", LIEF::assembly::x86::OPCODE::VPRORVDZ128rrkz) + .value("VPRORVDZ256rm", LIEF::assembly::x86::OPCODE::VPRORVDZ256rm) + .value("VPRORVDZ256rmb", LIEF::assembly::x86::OPCODE::VPRORVDZ256rmb) + .value("VPRORVDZ256rmbk", LIEF::assembly::x86::OPCODE::VPRORVDZ256rmbk) + .value("VPRORVDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPRORVDZ256rmbkz) + .value("VPRORVDZ256rmk", LIEF::assembly::x86::OPCODE::VPRORVDZ256rmk) + .value("VPRORVDZ256rmkz", LIEF::assembly::x86::OPCODE::VPRORVDZ256rmkz) + .value("VPRORVDZ256rr", LIEF::assembly::x86::OPCODE::VPRORVDZ256rr) + .value("VPRORVDZ256rrk", LIEF::assembly::x86::OPCODE::VPRORVDZ256rrk) + .value("VPRORVDZ256rrkz", LIEF::assembly::x86::OPCODE::VPRORVDZ256rrkz) + .value("VPRORVDZrm", LIEF::assembly::x86::OPCODE::VPRORVDZrm) + .value("VPRORVDZrmb", LIEF::assembly::x86::OPCODE::VPRORVDZrmb) + .value("VPRORVDZrmbk", LIEF::assembly::x86::OPCODE::VPRORVDZrmbk) + .value("VPRORVDZrmbkz", LIEF::assembly::x86::OPCODE::VPRORVDZrmbkz) + .value("VPRORVDZrmk", LIEF::assembly::x86::OPCODE::VPRORVDZrmk) + .value("VPRORVDZrmkz", LIEF::assembly::x86::OPCODE::VPRORVDZrmkz) + .value("VPRORVDZrr", LIEF::assembly::x86::OPCODE::VPRORVDZrr) + .value("VPRORVDZrrk", LIEF::assembly::x86::OPCODE::VPRORVDZrrk) + .value("VPRORVDZrrkz", LIEF::assembly::x86::OPCODE::VPRORVDZrrkz) + .value("VPRORVQZ128rm", LIEF::assembly::x86::OPCODE::VPRORVQZ128rm) + .value("VPRORVQZ128rmb", LIEF::assembly::x86::OPCODE::VPRORVQZ128rmb) + .value("VPRORVQZ128rmbk", LIEF::assembly::x86::OPCODE::VPRORVQZ128rmbk) + .value("VPRORVQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPRORVQZ128rmbkz) + .value("VPRORVQZ128rmk", LIEF::assembly::x86::OPCODE::VPRORVQZ128rmk) + .value("VPRORVQZ128rmkz", LIEF::assembly::x86::OPCODE::VPRORVQZ128rmkz) + .value("VPRORVQZ128rr", LIEF::assembly::x86::OPCODE::VPRORVQZ128rr) + .value("VPRORVQZ128rrk", LIEF::assembly::x86::OPCODE::VPRORVQZ128rrk) + .value("VPRORVQZ128rrkz", LIEF::assembly::x86::OPCODE::VPRORVQZ128rrkz) + .value("VPRORVQZ256rm", LIEF::assembly::x86::OPCODE::VPRORVQZ256rm) + .value("VPRORVQZ256rmb", LIEF::assembly::x86::OPCODE::VPRORVQZ256rmb) + .value("VPRORVQZ256rmbk", LIEF::assembly::x86::OPCODE::VPRORVQZ256rmbk); + opcodes.value("VPRORVQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPRORVQZ256rmbkz) + .value("VPRORVQZ256rmk", LIEF::assembly::x86::OPCODE::VPRORVQZ256rmk) + .value("VPRORVQZ256rmkz", LIEF::assembly::x86::OPCODE::VPRORVQZ256rmkz) + .value("VPRORVQZ256rr", LIEF::assembly::x86::OPCODE::VPRORVQZ256rr) + .value("VPRORVQZ256rrk", LIEF::assembly::x86::OPCODE::VPRORVQZ256rrk) + .value("VPRORVQZ256rrkz", LIEF::assembly::x86::OPCODE::VPRORVQZ256rrkz) + .value("VPRORVQZrm", LIEF::assembly::x86::OPCODE::VPRORVQZrm) + .value("VPRORVQZrmb", LIEF::assembly::x86::OPCODE::VPRORVQZrmb) + .value("VPRORVQZrmbk", LIEF::assembly::x86::OPCODE::VPRORVQZrmbk) + .value("VPRORVQZrmbkz", LIEF::assembly::x86::OPCODE::VPRORVQZrmbkz) + .value("VPRORVQZrmk", LIEF::assembly::x86::OPCODE::VPRORVQZrmk) + .value("VPRORVQZrmkz", LIEF::assembly::x86::OPCODE::VPRORVQZrmkz) + .value("VPRORVQZrr", LIEF::assembly::x86::OPCODE::VPRORVQZrr) + .value("VPRORVQZrrk", LIEF::assembly::x86::OPCODE::VPRORVQZrrk) + .value("VPRORVQZrrkz", LIEF::assembly::x86::OPCODE::VPRORVQZrrkz) + .value("VPROTBmi", LIEF::assembly::x86::OPCODE::VPROTBmi) + .value("VPROTBmr", LIEF::assembly::x86::OPCODE::VPROTBmr) + .value("VPROTBri", LIEF::assembly::x86::OPCODE::VPROTBri) + .value("VPROTBrm", LIEF::assembly::x86::OPCODE::VPROTBrm) + .value("VPROTBrr", LIEF::assembly::x86::OPCODE::VPROTBrr) + .value("VPROTBrr_REV", LIEF::assembly::x86::OPCODE::VPROTBrr_REV) + .value("VPROTDmi", LIEF::assembly::x86::OPCODE::VPROTDmi) + .value("VPROTDmr", LIEF::assembly::x86::OPCODE::VPROTDmr) + .value("VPROTDri", LIEF::assembly::x86::OPCODE::VPROTDri) + .value("VPROTDrm", LIEF::assembly::x86::OPCODE::VPROTDrm) + .value("VPROTDrr", LIEF::assembly::x86::OPCODE::VPROTDrr) + .value("VPROTDrr_REV", LIEF::assembly::x86::OPCODE::VPROTDrr_REV) + .value("VPROTQmi", LIEF::assembly::x86::OPCODE::VPROTQmi) + .value("VPROTQmr", LIEF::assembly::x86::OPCODE::VPROTQmr) + .value("VPROTQri", LIEF::assembly::x86::OPCODE::VPROTQri) + .value("VPROTQrm", LIEF::assembly::x86::OPCODE::VPROTQrm) + .value("VPROTQrr", LIEF::assembly::x86::OPCODE::VPROTQrr) + .value("VPROTQrr_REV", LIEF::assembly::x86::OPCODE::VPROTQrr_REV) + .value("VPROTWmi", LIEF::assembly::x86::OPCODE::VPROTWmi) + .value("VPROTWmr", LIEF::assembly::x86::OPCODE::VPROTWmr) + .value("VPROTWri", LIEF::assembly::x86::OPCODE::VPROTWri) + .value("VPROTWrm", LIEF::assembly::x86::OPCODE::VPROTWrm) + .value("VPROTWrr", LIEF::assembly::x86::OPCODE::VPROTWrr) + .value("VPROTWrr_REV", LIEF::assembly::x86::OPCODE::VPROTWrr_REV) + .value("VPSADBWYrm", LIEF::assembly::x86::OPCODE::VPSADBWYrm) + .value("VPSADBWYrr", LIEF::assembly::x86::OPCODE::VPSADBWYrr) + .value("VPSADBWZ128rm", LIEF::assembly::x86::OPCODE::VPSADBWZ128rm) + .value("VPSADBWZ128rr", LIEF::assembly::x86::OPCODE::VPSADBWZ128rr) + .value("VPSADBWZ256rm", LIEF::assembly::x86::OPCODE::VPSADBWZ256rm) + .value("VPSADBWZ256rr", LIEF::assembly::x86::OPCODE::VPSADBWZ256rr) + .value("VPSADBWZrm", LIEF::assembly::x86::OPCODE::VPSADBWZrm) + .value("VPSADBWZrr", LIEF::assembly::x86::OPCODE::VPSADBWZrr) + .value("VPSADBWrm", LIEF::assembly::x86::OPCODE::VPSADBWrm) + .value("VPSADBWrr", LIEF::assembly::x86::OPCODE::VPSADBWrr) + .value("VPSCATTERDDZ128mr", LIEF::assembly::x86::OPCODE::VPSCATTERDDZ128mr) + .value("VPSCATTERDDZ256mr", LIEF::assembly::x86::OPCODE::VPSCATTERDDZ256mr) + .value("VPSCATTERDDZmr", LIEF::assembly::x86::OPCODE::VPSCATTERDDZmr) + .value("VPSCATTERDQZ128mr", LIEF::assembly::x86::OPCODE::VPSCATTERDQZ128mr) + .value("VPSCATTERDQZ256mr", LIEF::assembly::x86::OPCODE::VPSCATTERDQZ256mr) + .value("VPSCATTERDQZmr", LIEF::assembly::x86::OPCODE::VPSCATTERDQZmr) + .value("VPSCATTERQDZ128mr", LIEF::assembly::x86::OPCODE::VPSCATTERQDZ128mr) + .value("VPSCATTERQDZ256mr", LIEF::assembly::x86::OPCODE::VPSCATTERQDZ256mr) + .value("VPSCATTERQDZmr", LIEF::assembly::x86::OPCODE::VPSCATTERQDZmr) + .value("VPSCATTERQQZ128mr", LIEF::assembly::x86::OPCODE::VPSCATTERQQZ128mr) + .value("VPSCATTERQQZ256mr", LIEF::assembly::x86::OPCODE::VPSCATTERQQZ256mr) + .value("VPSCATTERQQZmr", LIEF::assembly::x86::OPCODE::VPSCATTERQQZmr) + .value("VPSHABmr", LIEF::assembly::x86::OPCODE::VPSHABmr) + .value("VPSHABrm", LIEF::assembly::x86::OPCODE::VPSHABrm) + .value("VPSHABrr", LIEF::assembly::x86::OPCODE::VPSHABrr) + .value("VPSHABrr_REV", LIEF::assembly::x86::OPCODE::VPSHABrr_REV) + .value("VPSHADmr", LIEF::assembly::x86::OPCODE::VPSHADmr) + .value("VPSHADrm", LIEF::assembly::x86::OPCODE::VPSHADrm) + .value("VPSHADrr", LIEF::assembly::x86::OPCODE::VPSHADrr) + .value("VPSHADrr_REV", LIEF::assembly::x86::OPCODE::VPSHADrr_REV) + .value("VPSHAQmr", LIEF::assembly::x86::OPCODE::VPSHAQmr) + .value("VPSHAQrm", LIEF::assembly::x86::OPCODE::VPSHAQrm) + .value("VPSHAQrr", LIEF::assembly::x86::OPCODE::VPSHAQrr) + .value("VPSHAQrr_REV", LIEF::assembly::x86::OPCODE::VPSHAQrr_REV) + .value("VPSHAWmr", LIEF::assembly::x86::OPCODE::VPSHAWmr) + .value("VPSHAWrm", LIEF::assembly::x86::OPCODE::VPSHAWrm) + .value("VPSHAWrr", LIEF::assembly::x86::OPCODE::VPSHAWrr) + .value("VPSHAWrr_REV", LIEF::assembly::x86::OPCODE::VPSHAWrr_REV) + .value("VPSHLBmr", LIEF::assembly::x86::OPCODE::VPSHLBmr) + .value("VPSHLBrm", LIEF::assembly::x86::OPCODE::VPSHLBrm) + .value("VPSHLBrr", LIEF::assembly::x86::OPCODE::VPSHLBrr) + .value("VPSHLBrr_REV", LIEF::assembly::x86::OPCODE::VPSHLBrr_REV) + .value("VPSHLDDZ128rmbi", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmbi) + .value("VPSHLDDZ128rmbik", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmbik) + .value("VPSHLDDZ128rmbikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmbikz) + .value("VPSHLDDZ128rmi", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmi) + .value("VPSHLDDZ128rmik", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmik) + .value("VPSHLDDZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rmikz) + .value("VPSHLDDZ128rri", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rri) + .value("VPSHLDDZ128rrik", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rrik) + .value("VPSHLDDZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ128rrikz) + .value("VPSHLDDZ256rmbi", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmbi) + .value("VPSHLDDZ256rmbik", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmbik) + .value("VPSHLDDZ256rmbikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmbikz) + .value("VPSHLDDZ256rmi", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmi) + .value("VPSHLDDZ256rmik", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmik) + .value("VPSHLDDZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rmikz) + .value("VPSHLDDZ256rri", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rri) + .value("VPSHLDDZ256rrik", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rrik) + .value("VPSHLDDZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHLDDZ256rrikz) + .value("VPSHLDDZrmbi", LIEF::assembly::x86::OPCODE::VPSHLDDZrmbi) + .value("VPSHLDDZrmbik", LIEF::assembly::x86::OPCODE::VPSHLDDZrmbik) + .value("VPSHLDDZrmbikz", LIEF::assembly::x86::OPCODE::VPSHLDDZrmbikz) + .value("VPSHLDDZrmi", LIEF::assembly::x86::OPCODE::VPSHLDDZrmi) + .value("VPSHLDDZrmik", LIEF::assembly::x86::OPCODE::VPSHLDDZrmik) + .value("VPSHLDDZrmikz", LIEF::assembly::x86::OPCODE::VPSHLDDZrmikz) + .value("VPSHLDDZrri", LIEF::assembly::x86::OPCODE::VPSHLDDZrri) + .value("VPSHLDDZrrik", LIEF::assembly::x86::OPCODE::VPSHLDDZrrik) + .value("VPSHLDDZrrikz", LIEF::assembly::x86::OPCODE::VPSHLDDZrrikz) + .value("VPSHLDQZ128rmbi", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmbi) + .value("VPSHLDQZ128rmbik", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmbik) + .value("VPSHLDQZ128rmbikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmbikz) + .value("VPSHLDQZ128rmi", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmi) + .value("VPSHLDQZ128rmik", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmik) + .value("VPSHLDQZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rmikz) + .value("VPSHLDQZ128rri", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rri) + .value("VPSHLDQZ128rrik", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rrik) + .value("VPSHLDQZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ128rrikz) + .value("VPSHLDQZ256rmbi", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmbi) + .value("VPSHLDQZ256rmbik", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmbik) + .value("VPSHLDQZ256rmbikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmbikz) + .value("VPSHLDQZ256rmi", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmi) + .value("VPSHLDQZ256rmik", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmik) + .value("VPSHLDQZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rmikz) + .value("VPSHLDQZ256rri", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rri) + .value("VPSHLDQZ256rrik", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rrik) + .value("VPSHLDQZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHLDQZ256rrikz) + .value("VPSHLDQZrmbi", LIEF::assembly::x86::OPCODE::VPSHLDQZrmbi) + .value("VPSHLDQZrmbik", LIEF::assembly::x86::OPCODE::VPSHLDQZrmbik) + .value("VPSHLDQZrmbikz", LIEF::assembly::x86::OPCODE::VPSHLDQZrmbikz) + .value("VPSHLDQZrmi", LIEF::assembly::x86::OPCODE::VPSHLDQZrmi) + .value("VPSHLDQZrmik", LIEF::assembly::x86::OPCODE::VPSHLDQZrmik) + .value("VPSHLDQZrmikz", LIEF::assembly::x86::OPCODE::VPSHLDQZrmikz) + .value("VPSHLDQZrri", LIEF::assembly::x86::OPCODE::VPSHLDQZrri) + .value("VPSHLDQZrrik", LIEF::assembly::x86::OPCODE::VPSHLDQZrrik) + .value("VPSHLDQZrrikz", LIEF::assembly::x86::OPCODE::VPSHLDQZrrikz) + .value("VPSHLDVDZ128m", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128m) + .value("VPSHLDVDZ128mb", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128mb) + .value("VPSHLDVDZ128mbk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128mbk) + .value("VPSHLDVDZ128mbkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128mbkz) + .value("VPSHLDVDZ128mk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128mk) + .value("VPSHLDVDZ128mkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128mkz) + .value("VPSHLDVDZ128r", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128r) + .value("VPSHLDVDZ128rk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128rk) + .value("VPSHLDVDZ128rkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ128rkz) + .value("VPSHLDVDZ256m", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256m) + .value("VPSHLDVDZ256mb", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256mb) + .value("VPSHLDVDZ256mbk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256mbk) + .value("VPSHLDVDZ256mbkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256mbkz) + .value("VPSHLDVDZ256mk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256mk) + .value("VPSHLDVDZ256mkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256mkz) + .value("VPSHLDVDZ256r", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256r) + .value("VPSHLDVDZ256rk", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256rk) + .value("VPSHLDVDZ256rkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZ256rkz) + .value("VPSHLDVDZm", LIEF::assembly::x86::OPCODE::VPSHLDVDZm) + .value("VPSHLDVDZmb", LIEF::assembly::x86::OPCODE::VPSHLDVDZmb) + .value("VPSHLDVDZmbk", LIEF::assembly::x86::OPCODE::VPSHLDVDZmbk) + .value("VPSHLDVDZmbkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZmbkz) + .value("VPSHLDVDZmk", LIEF::assembly::x86::OPCODE::VPSHLDVDZmk) + .value("VPSHLDVDZmkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZmkz) + .value("VPSHLDVDZr", LIEF::assembly::x86::OPCODE::VPSHLDVDZr) + .value("VPSHLDVDZrk", LIEF::assembly::x86::OPCODE::VPSHLDVDZrk) + .value("VPSHLDVDZrkz", LIEF::assembly::x86::OPCODE::VPSHLDVDZrkz) + .value("VPSHLDVQZ128m", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128m) + .value("VPSHLDVQZ128mb", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128mb) + .value("VPSHLDVQZ128mbk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128mbk) + .value("VPSHLDVQZ128mbkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128mbkz) + .value("VPSHLDVQZ128mk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128mk) + .value("VPSHLDVQZ128mkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128mkz) + .value("VPSHLDVQZ128r", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128r) + .value("VPSHLDVQZ128rk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128rk) + .value("VPSHLDVQZ128rkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ128rkz) + .value("VPSHLDVQZ256m", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256m) + .value("VPSHLDVQZ256mb", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256mb) + .value("VPSHLDVQZ256mbk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256mbk) + .value("VPSHLDVQZ256mbkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256mbkz) + .value("VPSHLDVQZ256mk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256mk) + .value("VPSHLDVQZ256mkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256mkz) + .value("VPSHLDVQZ256r", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256r) + .value("VPSHLDVQZ256rk", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256rk) + .value("VPSHLDVQZ256rkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZ256rkz) + .value("VPSHLDVQZm", LIEF::assembly::x86::OPCODE::VPSHLDVQZm) + .value("VPSHLDVQZmb", LIEF::assembly::x86::OPCODE::VPSHLDVQZmb) + .value("VPSHLDVQZmbk", LIEF::assembly::x86::OPCODE::VPSHLDVQZmbk) + .value("VPSHLDVQZmbkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZmbkz) + .value("VPSHLDVQZmk", LIEF::assembly::x86::OPCODE::VPSHLDVQZmk) + .value("VPSHLDVQZmkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZmkz) + .value("VPSHLDVQZr", LIEF::assembly::x86::OPCODE::VPSHLDVQZr) + .value("VPSHLDVQZrk", LIEF::assembly::x86::OPCODE::VPSHLDVQZrk) + .value("VPSHLDVQZrkz", LIEF::assembly::x86::OPCODE::VPSHLDVQZrkz) + .value("VPSHLDVWZ128m", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128m) + .value("VPSHLDVWZ128mk", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128mk) + .value("VPSHLDVWZ128mkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128mkz) + .value("VPSHLDVWZ128r", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128r) + .value("VPSHLDVWZ128rk", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128rk) + .value("VPSHLDVWZ128rkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZ128rkz) + .value("VPSHLDVWZ256m", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256m) + .value("VPSHLDVWZ256mk", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256mk) + .value("VPSHLDVWZ256mkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256mkz) + .value("VPSHLDVWZ256r", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256r) + .value("VPSHLDVWZ256rk", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256rk) + .value("VPSHLDVWZ256rkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZ256rkz) + .value("VPSHLDVWZm", LIEF::assembly::x86::OPCODE::VPSHLDVWZm) + .value("VPSHLDVWZmk", LIEF::assembly::x86::OPCODE::VPSHLDVWZmk) + .value("VPSHLDVWZmkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZmkz) + .value("VPSHLDVWZr", LIEF::assembly::x86::OPCODE::VPSHLDVWZr) + .value("VPSHLDVWZrk", LIEF::assembly::x86::OPCODE::VPSHLDVWZrk) + .value("VPSHLDVWZrkz", LIEF::assembly::x86::OPCODE::VPSHLDVWZrkz) + .value("VPSHLDWZ128rmi", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rmi) + .value("VPSHLDWZ128rmik", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rmik) + .value("VPSHLDWZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rmikz) + .value("VPSHLDWZ128rri", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rri) + .value("VPSHLDWZ128rrik", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rrik) + .value("VPSHLDWZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHLDWZ128rrikz) + .value("VPSHLDWZ256rmi", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rmi) + .value("VPSHLDWZ256rmik", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rmik) + .value("VPSHLDWZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rmikz) + .value("VPSHLDWZ256rri", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rri) + .value("VPSHLDWZ256rrik", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rrik) + .value("VPSHLDWZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHLDWZ256rrikz) + .value("VPSHLDWZrmi", LIEF::assembly::x86::OPCODE::VPSHLDWZrmi) + .value("VPSHLDWZrmik", LIEF::assembly::x86::OPCODE::VPSHLDWZrmik) + .value("VPSHLDWZrmikz", LIEF::assembly::x86::OPCODE::VPSHLDWZrmikz) + .value("VPSHLDWZrri", LIEF::assembly::x86::OPCODE::VPSHLDWZrri) + .value("VPSHLDWZrrik", LIEF::assembly::x86::OPCODE::VPSHLDWZrrik) + .value("VPSHLDWZrrikz", LIEF::assembly::x86::OPCODE::VPSHLDWZrrikz) + .value("VPSHLDmr", LIEF::assembly::x86::OPCODE::VPSHLDmr) + .value("VPSHLDrm", LIEF::assembly::x86::OPCODE::VPSHLDrm) + .value("VPSHLDrr", LIEF::assembly::x86::OPCODE::VPSHLDrr) + .value("VPSHLDrr_REV", LIEF::assembly::x86::OPCODE::VPSHLDrr_REV) + .value("VPSHLQmr", LIEF::assembly::x86::OPCODE::VPSHLQmr) + .value("VPSHLQrm", LIEF::assembly::x86::OPCODE::VPSHLQrm) + .value("VPSHLQrr", LIEF::assembly::x86::OPCODE::VPSHLQrr) + .value("VPSHLQrr_REV", LIEF::assembly::x86::OPCODE::VPSHLQrr_REV) + .value("VPSHLWmr", LIEF::assembly::x86::OPCODE::VPSHLWmr) + .value("VPSHLWrm", LIEF::assembly::x86::OPCODE::VPSHLWrm) + .value("VPSHLWrr", LIEF::assembly::x86::OPCODE::VPSHLWrr) + .value("VPSHLWrr_REV", LIEF::assembly::x86::OPCODE::VPSHLWrr_REV) + .value("VPSHRDDZ128rmbi", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmbi) + .value("VPSHRDDZ128rmbik", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmbik) + .value("VPSHRDDZ128rmbikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmbikz) + .value("VPSHRDDZ128rmi", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmi) + .value("VPSHRDDZ128rmik", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmik) + .value("VPSHRDDZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rmikz) + .value("VPSHRDDZ128rri", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rri) + .value("VPSHRDDZ128rrik", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rrik) + .value("VPSHRDDZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ128rrikz) + .value("VPSHRDDZ256rmbi", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmbi) + .value("VPSHRDDZ256rmbik", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmbik) + .value("VPSHRDDZ256rmbikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmbikz) + .value("VPSHRDDZ256rmi", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmi) + .value("VPSHRDDZ256rmik", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmik) + .value("VPSHRDDZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rmikz) + .value("VPSHRDDZ256rri", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rri) + .value("VPSHRDDZ256rrik", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rrik) + .value("VPSHRDDZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHRDDZ256rrikz) + .value("VPSHRDDZrmbi", LIEF::assembly::x86::OPCODE::VPSHRDDZrmbi) + .value("VPSHRDDZrmbik", LIEF::assembly::x86::OPCODE::VPSHRDDZrmbik) + .value("VPSHRDDZrmbikz", LIEF::assembly::x86::OPCODE::VPSHRDDZrmbikz) + .value("VPSHRDDZrmi", LIEF::assembly::x86::OPCODE::VPSHRDDZrmi) + .value("VPSHRDDZrmik", LIEF::assembly::x86::OPCODE::VPSHRDDZrmik) + .value("VPSHRDDZrmikz", LIEF::assembly::x86::OPCODE::VPSHRDDZrmikz) + .value("VPSHRDDZrri", LIEF::assembly::x86::OPCODE::VPSHRDDZrri) + .value("VPSHRDDZrrik", LIEF::assembly::x86::OPCODE::VPSHRDDZrrik) + .value("VPSHRDDZrrikz", LIEF::assembly::x86::OPCODE::VPSHRDDZrrikz) + .value("VPSHRDQZ128rmbi", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmbi) + .value("VPSHRDQZ128rmbik", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmbik) + .value("VPSHRDQZ128rmbikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmbikz) + .value("VPSHRDQZ128rmi", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmi) + .value("VPSHRDQZ128rmik", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmik) + .value("VPSHRDQZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rmikz) + .value("VPSHRDQZ128rri", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rri) + .value("VPSHRDQZ128rrik", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rrik) + .value("VPSHRDQZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ128rrikz) + .value("VPSHRDQZ256rmbi", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmbi) + .value("VPSHRDQZ256rmbik", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmbik) + .value("VPSHRDQZ256rmbikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmbikz) + .value("VPSHRDQZ256rmi", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmi) + .value("VPSHRDQZ256rmik", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmik) + .value("VPSHRDQZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rmikz) + .value("VPSHRDQZ256rri", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rri) + .value("VPSHRDQZ256rrik", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rrik) + .value("VPSHRDQZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHRDQZ256rrikz) + .value("VPSHRDQZrmbi", LIEF::assembly::x86::OPCODE::VPSHRDQZrmbi) + .value("VPSHRDQZrmbik", LIEF::assembly::x86::OPCODE::VPSHRDQZrmbik) + .value("VPSHRDQZrmbikz", LIEF::assembly::x86::OPCODE::VPSHRDQZrmbikz) + .value("VPSHRDQZrmi", LIEF::assembly::x86::OPCODE::VPSHRDQZrmi) + .value("VPSHRDQZrmik", LIEF::assembly::x86::OPCODE::VPSHRDQZrmik) + .value("VPSHRDQZrmikz", LIEF::assembly::x86::OPCODE::VPSHRDQZrmikz) + .value("VPSHRDQZrri", LIEF::assembly::x86::OPCODE::VPSHRDQZrri) + .value("VPSHRDQZrrik", LIEF::assembly::x86::OPCODE::VPSHRDQZrrik) + .value("VPSHRDQZrrikz", LIEF::assembly::x86::OPCODE::VPSHRDQZrrikz) + .value("VPSHRDVDZ128m", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128m) + .value("VPSHRDVDZ128mb", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128mb) + .value("VPSHRDVDZ128mbk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128mbk) + .value("VPSHRDVDZ128mbkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128mbkz) + .value("VPSHRDVDZ128mk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128mk) + .value("VPSHRDVDZ128mkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128mkz) + .value("VPSHRDVDZ128r", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128r) + .value("VPSHRDVDZ128rk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128rk) + .value("VPSHRDVDZ128rkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ128rkz); + opcodes.value("VPSHRDVDZ256m", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256m) + .value("VPSHRDVDZ256mb", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256mb) + .value("VPSHRDVDZ256mbk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256mbk) + .value("VPSHRDVDZ256mbkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256mbkz) + .value("VPSHRDVDZ256mk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256mk) + .value("VPSHRDVDZ256mkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256mkz) + .value("VPSHRDVDZ256r", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256r) + .value("VPSHRDVDZ256rk", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256rk) + .value("VPSHRDVDZ256rkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZ256rkz) + .value("VPSHRDVDZm", LIEF::assembly::x86::OPCODE::VPSHRDVDZm) + .value("VPSHRDVDZmb", LIEF::assembly::x86::OPCODE::VPSHRDVDZmb) + .value("VPSHRDVDZmbk", LIEF::assembly::x86::OPCODE::VPSHRDVDZmbk) + .value("VPSHRDVDZmbkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZmbkz) + .value("VPSHRDVDZmk", LIEF::assembly::x86::OPCODE::VPSHRDVDZmk) + .value("VPSHRDVDZmkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZmkz) + .value("VPSHRDVDZr", LIEF::assembly::x86::OPCODE::VPSHRDVDZr) + .value("VPSHRDVDZrk", LIEF::assembly::x86::OPCODE::VPSHRDVDZrk) + .value("VPSHRDVDZrkz", LIEF::assembly::x86::OPCODE::VPSHRDVDZrkz) + .value("VPSHRDVQZ128m", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128m) + .value("VPSHRDVQZ128mb", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128mb) + .value("VPSHRDVQZ128mbk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128mbk) + .value("VPSHRDVQZ128mbkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128mbkz) + .value("VPSHRDVQZ128mk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128mk) + .value("VPSHRDVQZ128mkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128mkz) + .value("VPSHRDVQZ128r", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128r) + .value("VPSHRDVQZ128rk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128rk) + .value("VPSHRDVQZ128rkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ128rkz) + .value("VPSHRDVQZ256m", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256m) + .value("VPSHRDVQZ256mb", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256mb) + .value("VPSHRDVQZ256mbk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256mbk) + .value("VPSHRDVQZ256mbkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256mbkz) + .value("VPSHRDVQZ256mk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256mk) + .value("VPSHRDVQZ256mkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256mkz) + .value("VPSHRDVQZ256r", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256r) + .value("VPSHRDVQZ256rk", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256rk) + .value("VPSHRDVQZ256rkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZ256rkz) + .value("VPSHRDVQZm", LIEF::assembly::x86::OPCODE::VPSHRDVQZm) + .value("VPSHRDVQZmb", LIEF::assembly::x86::OPCODE::VPSHRDVQZmb) + .value("VPSHRDVQZmbk", LIEF::assembly::x86::OPCODE::VPSHRDVQZmbk) + .value("VPSHRDVQZmbkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZmbkz) + .value("VPSHRDVQZmk", LIEF::assembly::x86::OPCODE::VPSHRDVQZmk) + .value("VPSHRDVQZmkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZmkz) + .value("VPSHRDVQZr", LIEF::assembly::x86::OPCODE::VPSHRDVQZr) + .value("VPSHRDVQZrk", LIEF::assembly::x86::OPCODE::VPSHRDVQZrk) + .value("VPSHRDVQZrkz", LIEF::assembly::x86::OPCODE::VPSHRDVQZrkz) + .value("VPSHRDVWZ128m", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128m) + .value("VPSHRDVWZ128mk", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128mk) + .value("VPSHRDVWZ128mkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128mkz) + .value("VPSHRDVWZ128r", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128r) + .value("VPSHRDVWZ128rk", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128rk) + .value("VPSHRDVWZ128rkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZ128rkz) + .value("VPSHRDVWZ256m", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256m) + .value("VPSHRDVWZ256mk", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256mk) + .value("VPSHRDVWZ256mkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256mkz) + .value("VPSHRDVWZ256r", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256r) + .value("VPSHRDVWZ256rk", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256rk) + .value("VPSHRDVWZ256rkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZ256rkz) + .value("VPSHRDVWZm", LIEF::assembly::x86::OPCODE::VPSHRDVWZm) + .value("VPSHRDVWZmk", LIEF::assembly::x86::OPCODE::VPSHRDVWZmk) + .value("VPSHRDVWZmkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZmkz) + .value("VPSHRDVWZr", LIEF::assembly::x86::OPCODE::VPSHRDVWZr) + .value("VPSHRDVWZrk", LIEF::assembly::x86::OPCODE::VPSHRDVWZrk) + .value("VPSHRDVWZrkz", LIEF::assembly::x86::OPCODE::VPSHRDVWZrkz) + .value("VPSHRDWZ128rmi", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rmi) + .value("VPSHRDWZ128rmik", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rmik) + .value("VPSHRDWZ128rmikz", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rmikz) + .value("VPSHRDWZ128rri", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rri) + .value("VPSHRDWZ128rrik", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rrik) + .value("VPSHRDWZ128rrikz", LIEF::assembly::x86::OPCODE::VPSHRDWZ128rrikz) + .value("VPSHRDWZ256rmi", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rmi) + .value("VPSHRDWZ256rmik", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rmik) + .value("VPSHRDWZ256rmikz", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rmikz) + .value("VPSHRDWZ256rri", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rri) + .value("VPSHRDWZ256rrik", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rrik) + .value("VPSHRDWZ256rrikz", LIEF::assembly::x86::OPCODE::VPSHRDWZ256rrikz) + .value("VPSHRDWZrmi", LIEF::assembly::x86::OPCODE::VPSHRDWZrmi) + .value("VPSHRDWZrmik", LIEF::assembly::x86::OPCODE::VPSHRDWZrmik) + .value("VPSHRDWZrmikz", LIEF::assembly::x86::OPCODE::VPSHRDWZrmikz) + .value("VPSHRDWZrri", LIEF::assembly::x86::OPCODE::VPSHRDWZrri) + .value("VPSHRDWZrrik", LIEF::assembly::x86::OPCODE::VPSHRDWZrrik) + .value("VPSHRDWZrrikz", LIEF::assembly::x86::OPCODE::VPSHRDWZrrikz) + .value("VPSHUFBITQMBZ128rm", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ128rm) + .value("VPSHUFBITQMBZ128rmk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ128rmk) + .value("VPSHUFBITQMBZ128rr", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ128rr) + .value("VPSHUFBITQMBZ128rrk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ128rrk) + .value("VPSHUFBITQMBZ256rm", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ256rm) + .value("VPSHUFBITQMBZ256rmk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ256rmk) + .value("VPSHUFBITQMBZ256rr", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ256rr) + .value("VPSHUFBITQMBZ256rrk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZ256rrk) + .value("VPSHUFBITQMBZrm", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZrm) + .value("VPSHUFBITQMBZrmk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZrmk) + .value("VPSHUFBITQMBZrr", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZrr) + .value("VPSHUFBITQMBZrrk", LIEF::assembly::x86::OPCODE::VPSHUFBITQMBZrrk) + .value("VPSHUFBYrm", LIEF::assembly::x86::OPCODE::VPSHUFBYrm) + .value("VPSHUFBYrr", LIEF::assembly::x86::OPCODE::VPSHUFBYrr) + .value("VPSHUFBZ128rm", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rm) + .value("VPSHUFBZ128rmk", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rmk) + .value("VPSHUFBZ128rmkz", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rmkz) + .value("VPSHUFBZ128rr", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rr) + .value("VPSHUFBZ128rrk", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rrk) + .value("VPSHUFBZ128rrkz", LIEF::assembly::x86::OPCODE::VPSHUFBZ128rrkz) + .value("VPSHUFBZ256rm", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rm) + .value("VPSHUFBZ256rmk", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rmk) + .value("VPSHUFBZ256rmkz", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rmkz) + .value("VPSHUFBZ256rr", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rr) + .value("VPSHUFBZ256rrk", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rrk) + .value("VPSHUFBZ256rrkz", LIEF::assembly::x86::OPCODE::VPSHUFBZ256rrkz) + .value("VPSHUFBZrm", LIEF::assembly::x86::OPCODE::VPSHUFBZrm) + .value("VPSHUFBZrmk", LIEF::assembly::x86::OPCODE::VPSHUFBZrmk) + .value("VPSHUFBZrmkz", LIEF::assembly::x86::OPCODE::VPSHUFBZrmkz) + .value("VPSHUFBZrr", LIEF::assembly::x86::OPCODE::VPSHUFBZrr) + .value("VPSHUFBZrrk", LIEF::assembly::x86::OPCODE::VPSHUFBZrrk) + .value("VPSHUFBZrrkz", LIEF::assembly::x86::OPCODE::VPSHUFBZrrkz) + .value("VPSHUFBrm", LIEF::assembly::x86::OPCODE::VPSHUFBrm) + .value("VPSHUFBrr", LIEF::assembly::x86::OPCODE::VPSHUFBrr) + .value("VPSHUFDYmi", LIEF::assembly::x86::OPCODE::VPSHUFDYmi) + .value("VPSHUFDYri", LIEF::assembly::x86::OPCODE::VPSHUFDYri) + .value("VPSHUFDZ128mbi", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mbi) + .value("VPSHUFDZ128mbik", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mbik) + .value("VPSHUFDZ128mbikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mbikz) + .value("VPSHUFDZ128mi", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mi) + .value("VPSHUFDZ128mik", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mik) + .value("VPSHUFDZ128mikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ128mikz) + .value("VPSHUFDZ128ri", LIEF::assembly::x86::OPCODE::VPSHUFDZ128ri) + .value("VPSHUFDZ128rik", LIEF::assembly::x86::OPCODE::VPSHUFDZ128rik) + .value("VPSHUFDZ128rikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ128rikz) + .value("VPSHUFDZ256mbi", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mbi) + .value("VPSHUFDZ256mbik", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mbik) + .value("VPSHUFDZ256mbikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mbikz) + .value("VPSHUFDZ256mi", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mi) + .value("VPSHUFDZ256mik", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mik) + .value("VPSHUFDZ256mikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ256mikz) + .value("VPSHUFDZ256ri", LIEF::assembly::x86::OPCODE::VPSHUFDZ256ri) + .value("VPSHUFDZ256rik", LIEF::assembly::x86::OPCODE::VPSHUFDZ256rik) + .value("VPSHUFDZ256rikz", LIEF::assembly::x86::OPCODE::VPSHUFDZ256rikz) + .value("VPSHUFDZmbi", LIEF::assembly::x86::OPCODE::VPSHUFDZmbi) + .value("VPSHUFDZmbik", LIEF::assembly::x86::OPCODE::VPSHUFDZmbik) + .value("VPSHUFDZmbikz", LIEF::assembly::x86::OPCODE::VPSHUFDZmbikz) + .value("VPSHUFDZmi", LIEF::assembly::x86::OPCODE::VPSHUFDZmi) + .value("VPSHUFDZmik", LIEF::assembly::x86::OPCODE::VPSHUFDZmik) + .value("VPSHUFDZmikz", LIEF::assembly::x86::OPCODE::VPSHUFDZmikz) + .value("VPSHUFDZri", LIEF::assembly::x86::OPCODE::VPSHUFDZri) + .value("VPSHUFDZrik", LIEF::assembly::x86::OPCODE::VPSHUFDZrik) + .value("VPSHUFDZrikz", LIEF::assembly::x86::OPCODE::VPSHUFDZrikz) + .value("VPSHUFDmi", LIEF::assembly::x86::OPCODE::VPSHUFDmi) + .value("VPSHUFDri", LIEF::assembly::x86::OPCODE::VPSHUFDri) + .value("VPSHUFHWYmi", LIEF::assembly::x86::OPCODE::VPSHUFHWYmi) + .value("VPSHUFHWYri", LIEF::assembly::x86::OPCODE::VPSHUFHWYri) + .value("VPSHUFHWZ128mi", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128mi) + .value("VPSHUFHWZ128mik", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128mik) + .value("VPSHUFHWZ128mikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128mikz) + .value("VPSHUFHWZ128ri", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128ri) + .value("VPSHUFHWZ128rik", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128rik) + .value("VPSHUFHWZ128rikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZ128rikz) + .value("VPSHUFHWZ256mi", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256mi) + .value("VPSHUFHWZ256mik", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256mik) + .value("VPSHUFHWZ256mikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256mikz) + .value("VPSHUFHWZ256ri", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256ri) + .value("VPSHUFHWZ256rik", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256rik) + .value("VPSHUFHWZ256rikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZ256rikz) + .value("VPSHUFHWZmi", LIEF::assembly::x86::OPCODE::VPSHUFHWZmi) + .value("VPSHUFHWZmik", LIEF::assembly::x86::OPCODE::VPSHUFHWZmik) + .value("VPSHUFHWZmikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZmikz) + .value("VPSHUFHWZri", LIEF::assembly::x86::OPCODE::VPSHUFHWZri) + .value("VPSHUFHWZrik", LIEF::assembly::x86::OPCODE::VPSHUFHWZrik) + .value("VPSHUFHWZrikz", LIEF::assembly::x86::OPCODE::VPSHUFHWZrikz) + .value("VPSHUFHWmi", LIEF::assembly::x86::OPCODE::VPSHUFHWmi) + .value("VPSHUFHWri", LIEF::assembly::x86::OPCODE::VPSHUFHWri) + .value("VPSHUFLWYmi", LIEF::assembly::x86::OPCODE::VPSHUFLWYmi) + .value("VPSHUFLWYri", LIEF::assembly::x86::OPCODE::VPSHUFLWYri) + .value("VPSHUFLWZ128mi", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128mi) + .value("VPSHUFLWZ128mik", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128mik) + .value("VPSHUFLWZ128mikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128mikz) + .value("VPSHUFLWZ128ri", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128ri) + .value("VPSHUFLWZ128rik", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128rik) + .value("VPSHUFLWZ128rikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZ128rikz) + .value("VPSHUFLWZ256mi", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256mi) + .value("VPSHUFLWZ256mik", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256mik) + .value("VPSHUFLWZ256mikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256mikz) + .value("VPSHUFLWZ256ri", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256ri) + .value("VPSHUFLWZ256rik", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256rik) + .value("VPSHUFLWZ256rikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZ256rikz) + .value("VPSHUFLWZmi", LIEF::assembly::x86::OPCODE::VPSHUFLWZmi) + .value("VPSHUFLWZmik", LIEF::assembly::x86::OPCODE::VPSHUFLWZmik) + .value("VPSHUFLWZmikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZmikz) + .value("VPSHUFLWZri", LIEF::assembly::x86::OPCODE::VPSHUFLWZri) + .value("VPSHUFLWZrik", LIEF::assembly::x86::OPCODE::VPSHUFLWZrik) + .value("VPSHUFLWZrikz", LIEF::assembly::x86::OPCODE::VPSHUFLWZrikz) + .value("VPSHUFLWmi", LIEF::assembly::x86::OPCODE::VPSHUFLWmi) + .value("VPSHUFLWri", LIEF::assembly::x86::OPCODE::VPSHUFLWri) + .value("VPSIGNBYrm", LIEF::assembly::x86::OPCODE::VPSIGNBYrm) + .value("VPSIGNBYrr", LIEF::assembly::x86::OPCODE::VPSIGNBYrr) + .value("VPSIGNBrm", LIEF::assembly::x86::OPCODE::VPSIGNBrm) + .value("VPSIGNBrr", LIEF::assembly::x86::OPCODE::VPSIGNBrr) + .value("VPSIGNDYrm", LIEF::assembly::x86::OPCODE::VPSIGNDYrm) + .value("VPSIGNDYrr", LIEF::assembly::x86::OPCODE::VPSIGNDYrr) + .value("VPSIGNDrm", LIEF::assembly::x86::OPCODE::VPSIGNDrm) + .value("VPSIGNDrr", LIEF::assembly::x86::OPCODE::VPSIGNDrr) + .value("VPSIGNWYrm", LIEF::assembly::x86::OPCODE::VPSIGNWYrm) + .value("VPSIGNWYrr", LIEF::assembly::x86::OPCODE::VPSIGNWYrr) + .value("VPSIGNWrm", LIEF::assembly::x86::OPCODE::VPSIGNWrm) + .value("VPSIGNWrr", LIEF::assembly::x86::OPCODE::VPSIGNWrr) + .value("VPSLLDQYri", LIEF::assembly::x86::OPCODE::VPSLLDQYri) + .value("VPSLLDQZ128mi", LIEF::assembly::x86::OPCODE::VPSLLDQZ128mi) + .value("VPSLLDQZ128ri", LIEF::assembly::x86::OPCODE::VPSLLDQZ128ri) + .value("VPSLLDQZ256mi", LIEF::assembly::x86::OPCODE::VPSLLDQZ256mi) + .value("VPSLLDQZ256ri", LIEF::assembly::x86::OPCODE::VPSLLDQZ256ri) + .value("VPSLLDQZmi", LIEF::assembly::x86::OPCODE::VPSLLDQZmi) + .value("VPSLLDQZri", LIEF::assembly::x86::OPCODE::VPSLLDQZri) + .value("VPSLLDQri", LIEF::assembly::x86::OPCODE::VPSLLDQri) + .value("VPSLLDYri", LIEF::assembly::x86::OPCODE::VPSLLDYri) + .value("VPSLLDYrm", LIEF::assembly::x86::OPCODE::VPSLLDYrm) + .value("VPSLLDYrr", LIEF::assembly::x86::OPCODE::VPSLLDYrr) + .value("VPSLLDZ128mbi", LIEF::assembly::x86::OPCODE::VPSLLDZ128mbi) + .value("VPSLLDZ128mbik", LIEF::assembly::x86::OPCODE::VPSLLDZ128mbik) + .value("VPSLLDZ128mbikz", LIEF::assembly::x86::OPCODE::VPSLLDZ128mbikz) + .value("VPSLLDZ128mi", LIEF::assembly::x86::OPCODE::VPSLLDZ128mi) + .value("VPSLLDZ128mik", LIEF::assembly::x86::OPCODE::VPSLLDZ128mik) + .value("VPSLLDZ128mikz", LIEF::assembly::x86::OPCODE::VPSLLDZ128mikz) + .value("VPSLLDZ128ri", LIEF::assembly::x86::OPCODE::VPSLLDZ128ri) + .value("VPSLLDZ128rik", LIEF::assembly::x86::OPCODE::VPSLLDZ128rik) + .value("VPSLLDZ128rikz", LIEF::assembly::x86::OPCODE::VPSLLDZ128rikz) + .value("VPSLLDZ128rm", LIEF::assembly::x86::OPCODE::VPSLLDZ128rm) + .value("VPSLLDZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLDZ128rmk) + .value("VPSLLDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLDZ128rmkz) + .value("VPSLLDZ128rr", LIEF::assembly::x86::OPCODE::VPSLLDZ128rr) + .value("VPSLLDZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLDZ128rrk) + .value("VPSLLDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLDZ128rrkz) + .value("VPSLLDZ256mbi", LIEF::assembly::x86::OPCODE::VPSLLDZ256mbi) + .value("VPSLLDZ256mbik", LIEF::assembly::x86::OPCODE::VPSLLDZ256mbik) + .value("VPSLLDZ256mbikz", LIEF::assembly::x86::OPCODE::VPSLLDZ256mbikz) + .value("VPSLLDZ256mi", LIEF::assembly::x86::OPCODE::VPSLLDZ256mi) + .value("VPSLLDZ256mik", LIEF::assembly::x86::OPCODE::VPSLLDZ256mik) + .value("VPSLLDZ256mikz", LIEF::assembly::x86::OPCODE::VPSLLDZ256mikz) + .value("VPSLLDZ256ri", LIEF::assembly::x86::OPCODE::VPSLLDZ256ri) + .value("VPSLLDZ256rik", LIEF::assembly::x86::OPCODE::VPSLLDZ256rik) + .value("VPSLLDZ256rikz", LIEF::assembly::x86::OPCODE::VPSLLDZ256rikz) + .value("VPSLLDZ256rm", LIEF::assembly::x86::OPCODE::VPSLLDZ256rm) + .value("VPSLLDZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLDZ256rmk) + .value("VPSLLDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLDZ256rmkz) + .value("VPSLLDZ256rr", LIEF::assembly::x86::OPCODE::VPSLLDZ256rr) + .value("VPSLLDZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLDZ256rrk) + .value("VPSLLDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLDZ256rrkz) + .value("VPSLLDZmbi", LIEF::assembly::x86::OPCODE::VPSLLDZmbi) + .value("VPSLLDZmbik", LIEF::assembly::x86::OPCODE::VPSLLDZmbik) + .value("VPSLLDZmbikz", LIEF::assembly::x86::OPCODE::VPSLLDZmbikz) + .value("VPSLLDZmi", LIEF::assembly::x86::OPCODE::VPSLLDZmi) + .value("VPSLLDZmik", LIEF::assembly::x86::OPCODE::VPSLLDZmik) + .value("VPSLLDZmikz", LIEF::assembly::x86::OPCODE::VPSLLDZmikz) + .value("VPSLLDZri", LIEF::assembly::x86::OPCODE::VPSLLDZri) + .value("VPSLLDZrik", LIEF::assembly::x86::OPCODE::VPSLLDZrik) + .value("VPSLLDZrikz", LIEF::assembly::x86::OPCODE::VPSLLDZrikz) + .value("VPSLLDZrm", LIEF::assembly::x86::OPCODE::VPSLLDZrm) + .value("VPSLLDZrmk", LIEF::assembly::x86::OPCODE::VPSLLDZrmk) + .value("VPSLLDZrmkz", LIEF::assembly::x86::OPCODE::VPSLLDZrmkz) + .value("VPSLLDZrr", LIEF::assembly::x86::OPCODE::VPSLLDZrr) + .value("VPSLLDZrrk", LIEF::assembly::x86::OPCODE::VPSLLDZrrk) + .value("VPSLLDZrrkz", LIEF::assembly::x86::OPCODE::VPSLLDZrrkz) + .value("VPSLLDri", LIEF::assembly::x86::OPCODE::VPSLLDri) + .value("VPSLLDrm", LIEF::assembly::x86::OPCODE::VPSLLDrm) + .value("VPSLLDrr", LIEF::assembly::x86::OPCODE::VPSLLDrr) + .value("VPSLLQYri", LIEF::assembly::x86::OPCODE::VPSLLQYri) + .value("VPSLLQYrm", LIEF::assembly::x86::OPCODE::VPSLLQYrm) + .value("VPSLLQYrr", LIEF::assembly::x86::OPCODE::VPSLLQYrr) + .value("VPSLLQZ128mbi", LIEF::assembly::x86::OPCODE::VPSLLQZ128mbi) + .value("VPSLLQZ128mbik", LIEF::assembly::x86::OPCODE::VPSLLQZ128mbik) + .value("VPSLLQZ128mbikz", LIEF::assembly::x86::OPCODE::VPSLLQZ128mbikz) + .value("VPSLLQZ128mi", LIEF::assembly::x86::OPCODE::VPSLLQZ128mi) + .value("VPSLLQZ128mik", LIEF::assembly::x86::OPCODE::VPSLLQZ128mik) + .value("VPSLLQZ128mikz", LIEF::assembly::x86::OPCODE::VPSLLQZ128mikz) + .value("VPSLLQZ128ri", LIEF::assembly::x86::OPCODE::VPSLLQZ128ri) + .value("VPSLLQZ128rik", LIEF::assembly::x86::OPCODE::VPSLLQZ128rik) + .value("VPSLLQZ128rikz", LIEF::assembly::x86::OPCODE::VPSLLQZ128rikz) + .value("VPSLLQZ128rm", LIEF::assembly::x86::OPCODE::VPSLLQZ128rm) + .value("VPSLLQZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLQZ128rmk) + .value("VPSLLQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLQZ128rmkz) + .value("VPSLLQZ128rr", LIEF::assembly::x86::OPCODE::VPSLLQZ128rr) + .value("VPSLLQZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLQZ128rrk) + .value("VPSLLQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLQZ128rrkz) + .value("VPSLLQZ256mbi", LIEF::assembly::x86::OPCODE::VPSLLQZ256mbi) + .value("VPSLLQZ256mbik", LIEF::assembly::x86::OPCODE::VPSLLQZ256mbik) + .value("VPSLLQZ256mbikz", LIEF::assembly::x86::OPCODE::VPSLLQZ256mbikz) + .value("VPSLLQZ256mi", LIEF::assembly::x86::OPCODE::VPSLLQZ256mi) + .value("VPSLLQZ256mik", LIEF::assembly::x86::OPCODE::VPSLLQZ256mik) + .value("VPSLLQZ256mikz", LIEF::assembly::x86::OPCODE::VPSLLQZ256mikz) + .value("VPSLLQZ256ri", LIEF::assembly::x86::OPCODE::VPSLLQZ256ri) + .value("VPSLLQZ256rik", LIEF::assembly::x86::OPCODE::VPSLLQZ256rik) + .value("VPSLLQZ256rikz", LIEF::assembly::x86::OPCODE::VPSLLQZ256rikz) + .value("VPSLLQZ256rm", LIEF::assembly::x86::OPCODE::VPSLLQZ256rm) + .value("VPSLLQZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLQZ256rmk) + .value("VPSLLQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLQZ256rmkz) + .value("VPSLLQZ256rr", LIEF::assembly::x86::OPCODE::VPSLLQZ256rr) + .value("VPSLLQZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLQZ256rrk) + .value("VPSLLQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLQZ256rrkz) + .value("VPSLLQZmbi", LIEF::assembly::x86::OPCODE::VPSLLQZmbi) + .value("VPSLLQZmbik", LIEF::assembly::x86::OPCODE::VPSLLQZmbik) + .value("VPSLLQZmbikz", LIEF::assembly::x86::OPCODE::VPSLLQZmbikz) + .value("VPSLLQZmi", LIEF::assembly::x86::OPCODE::VPSLLQZmi) + .value("VPSLLQZmik", LIEF::assembly::x86::OPCODE::VPSLLQZmik) + .value("VPSLLQZmikz", LIEF::assembly::x86::OPCODE::VPSLLQZmikz); + opcodes.value("VPSLLQZri", LIEF::assembly::x86::OPCODE::VPSLLQZri) + .value("VPSLLQZrik", LIEF::assembly::x86::OPCODE::VPSLLQZrik) + .value("VPSLLQZrikz", LIEF::assembly::x86::OPCODE::VPSLLQZrikz) + .value("VPSLLQZrm", LIEF::assembly::x86::OPCODE::VPSLLQZrm) + .value("VPSLLQZrmk", LIEF::assembly::x86::OPCODE::VPSLLQZrmk) + .value("VPSLLQZrmkz", LIEF::assembly::x86::OPCODE::VPSLLQZrmkz) + .value("VPSLLQZrr", LIEF::assembly::x86::OPCODE::VPSLLQZrr) + .value("VPSLLQZrrk", LIEF::assembly::x86::OPCODE::VPSLLQZrrk) + .value("VPSLLQZrrkz", LIEF::assembly::x86::OPCODE::VPSLLQZrrkz) + .value("VPSLLQri", LIEF::assembly::x86::OPCODE::VPSLLQri) + .value("VPSLLQrm", LIEF::assembly::x86::OPCODE::VPSLLQrm) + .value("VPSLLQrr", LIEF::assembly::x86::OPCODE::VPSLLQrr) + .value("VPSLLVDYrm", LIEF::assembly::x86::OPCODE::VPSLLVDYrm) + .value("VPSLLVDYrr", LIEF::assembly::x86::OPCODE::VPSLLVDYrr) + .value("VPSLLVDZ128rm", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rm) + .value("VPSLLVDZ128rmb", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rmb) + .value("VPSLLVDZ128rmbk", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rmbk) + .value("VPSLLVDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rmbkz) + .value("VPSLLVDZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rmk) + .value("VPSLLVDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rmkz) + .value("VPSLLVDZ128rr", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rr) + .value("VPSLLVDZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rrk) + .value("VPSLLVDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ128rrkz) + .value("VPSLLVDZ256rm", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rm) + .value("VPSLLVDZ256rmb", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rmb) + .value("VPSLLVDZ256rmbk", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rmbk) + .value("VPSLLVDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rmbkz) + .value("VPSLLVDZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rmk) + .value("VPSLLVDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rmkz) + .value("VPSLLVDZ256rr", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rr) + .value("VPSLLVDZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rrk) + .value("VPSLLVDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLVDZ256rrkz) + .value("VPSLLVDZrm", LIEF::assembly::x86::OPCODE::VPSLLVDZrm) + .value("VPSLLVDZrmb", LIEF::assembly::x86::OPCODE::VPSLLVDZrmb) + .value("VPSLLVDZrmbk", LIEF::assembly::x86::OPCODE::VPSLLVDZrmbk) + .value("VPSLLVDZrmbkz", LIEF::assembly::x86::OPCODE::VPSLLVDZrmbkz) + .value("VPSLLVDZrmk", LIEF::assembly::x86::OPCODE::VPSLLVDZrmk) + .value("VPSLLVDZrmkz", LIEF::assembly::x86::OPCODE::VPSLLVDZrmkz) + .value("VPSLLVDZrr", LIEF::assembly::x86::OPCODE::VPSLLVDZrr) + .value("VPSLLVDZrrk", LIEF::assembly::x86::OPCODE::VPSLLVDZrrk) + .value("VPSLLVDZrrkz", LIEF::assembly::x86::OPCODE::VPSLLVDZrrkz) + .value("VPSLLVDrm", LIEF::assembly::x86::OPCODE::VPSLLVDrm) + .value("VPSLLVDrr", LIEF::assembly::x86::OPCODE::VPSLLVDrr) + .value("VPSLLVQYrm", LIEF::assembly::x86::OPCODE::VPSLLVQYrm) + .value("VPSLLVQYrr", LIEF::assembly::x86::OPCODE::VPSLLVQYrr) + .value("VPSLLVQZ128rm", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rm) + .value("VPSLLVQZ128rmb", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rmb) + .value("VPSLLVQZ128rmbk", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rmbk) + .value("VPSLLVQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rmbkz) + .value("VPSLLVQZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rmk) + .value("VPSLLVQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rmkz) + .value("VPSLLVQZ128rr", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rr) + .value("VPSLLVQZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rrk) + .value("VPSLLVQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ128rrkz) + .value("VPSLLVQZ256rm", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rm) + .value("VPSLLVQZ256rmb", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rmb) + .value("VPSLLVQZ256rmbk", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rmbk) + .value("VPSLLVQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rmbkz) + .value("VPSLLVQZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rmk) + .value("VPSLLVQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rmkz) + .value("VPSLLVQZ256rr", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rr) + .value("VPSLLVQZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rrk) + .value("VPSLLVQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLVQZ256rrkz) + .value("VPSLLVQZrm", LIEF::assembly::x86::OPCODE::VPSLLVQZrm) + .value("VPSLLVQZrmb", LIEF::assembly::x86::OPCODE::VPSLLVQZrmb) + .value("VPSLLVQZrmbk", LIEF::assembly::x86::OPCODE::VPSLLVQZrmbk) + .value("VPSLLVQZrmbkz", LIEF::assembly::x86::OPCODE::VPSLLVQZrmbkz) + .value("VPSLLVQZrmk", LIEF::assembly::x86::OPCODE::VPSLLVQZrmk) + .value("VPSLLVQZrmkz", LIEF::assembly::x86::OPCODE::VPSLLVQZrmkz) + .value("VPSLLVQZrr", LIEF::assembly::x86::OPCODE::VPSLLVQZrr) + .value("VPSLLVQZrrk", LIEF::assembly::x86::OPCODE::VPSLLVQZrrk) + .value("VPSLLVQZrrkz", LIEF::assembly::x86::OPCODE::VPSLLVQZrrkz) + .value("VPSLLVQrm", LIEF::assembly::x86::OPCODE::VPSLLVQrm) + .value("VPSLLVQrr", LIEF::assembly::x86::OPCODE::VPSLLVQrr) + .value("VPSLLVWZ128rm", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rm) + .value("VPSLLVWZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rmk) + .value("VPSLLVWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rmkz) + .value("VPSLLVWZ128rr", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rr) + .value("VPSLLVWZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rrk) + .value("VPSLLVWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLVWZ128rrkz) + .value("VPSLLVWZ256rm", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rm) + .value("VPSLLVWZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rmk) + .value("VPSLLVWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rmkz) + .value("VPSLLVWZ256rr", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rr) + .value("VPSLLVWZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rrk) + .value("VPSLLVWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLVWZ256rrkz) + .value("VPSLLVWZrm", LIEF::assembly::x86::OPCODE::VPSLLVWZrm) + .value("VPSLLVWZrmk", LIEF::assembly::x86::OPCODE::VPSLLVWZrmk) + .value("VPSLLVWZrmkz", LIEF::assembly::x86::OPCODE::VPSLLVWZrmkz) + .value("VPSLLVWZrr", LIEF::assembly::x86::OPCODE::VPSLLVWZrr) + .value("VPSLLVWZrrk", LIEF::assembly::x86::OPCODE::VPSLLVWZrrk) + .value("VPSLLVWZrrkz", LIEF::assembly::x86::OPCODE::VPSLLVWZrrkz) + .value("VPSLLWYri", LIEF::assembly::x86::OPCODE::VPSLLWYri) + .value("VPSLLWYrm", LIEF::assembly::x86::OPCODE::VPSLLWYrm) + .value("VPSLLWYrr", LIEF::assembly::x86::OPCODE::VPSLLWYrr) + .value("VPSLLWZ128mi", LIEF::assembly::x86::OPCODE::VPSLLWZ128mi) + .value("VPSLLWZ128mik", LIEF::assembly::x86::OPCODE::VPSLLWZ128mik) + .value("VPSLLWZ128mikz", LIEF::assembly::x86::OPCODE::VPSLLWZ128mikz) + .value("VPSLLWZ128ri", LIEF::assembly::x86::OPCODE::VPSLLWZ128ri) + .value("VPSLLWZ128rik", LIEF::assembly::x86::OPCODE::VPSLLWZ128rik) + .value("VPSLLWZ128rikz", LIEF::assembly::x86::OPCODE::VPSLLWZ128rikz) + .value("VPSLLWZ128rm", LIEF::assembly::x86::OPCODE::VPSLLWZ128rm) + .value("VPSLLWZ128rmk", LIEF::assembly::x86::OPCODE::VPSLLWZ128rmk) + .value("VPSLLWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSLLWZ128rmkz) + .value("VPSLLWZ128rr", LIEF::assembly::x86::OPCODE::VPSLLWZ128rr) + .value("VPSLLWZ128rrk", LIEF::assembly::x86::OPCODE::VPSLLWZ128rrk) + .value("VPSLLWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSLLWZ128rrkz) + .value("VPSLLWZ256mi", LIEF::assembly::x86::OPCODE::VPSLLWZ256mi) + .value("VPSLLWZ256mik", LIEF::assembly::x86::OPCODE::VPSLLWZ256mik) + .value("VPSLLWZ256mikz", LIEF::assembly::x86::OPCODE::VPSLLWZ256mikz) + .value("VPSLLWZ256ri", LIEF::assembly::x86::OPCODE::VPSLLWZ256ri) + .value("VPSLLWZ256rik", LIEF::assembly::x86::OPCODE::VPSLLWZ256rik) + .value("VPSLLWZ256rikz", LIEF::assembly::x86::OPCODE::VPSLLWZ256rikz) + .value("VPSLLWZ256rm", LIEF::assembly::x86::OPCODE::VPSLLWZ256rm) + .value("VPSLLWZ256rmk", LIEF::assembly::x86::OPCODE::VPSLLWZ256rmk) + .value("VPSLLWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSLLWZ256rmkz) + .value("VPSLLWZ256rr", LIEF::assembly::x86::OPCODE::VPSLLWZ256rr) + .value("VPSLLWZ256rrk", LIEF::assembly::x86::OPCODE::VPSLLWZ256rrk) + .value("VPSLLWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSLLWZ256rrkz) + .value("VPSLLWZmi", LIEF::assembly::x86::OPCODE::VPSLLWZmi) + .value("VPSLLWZmik", LIEF::assembly::x86::OPCODE::VPSLLWZmik) + .value("VPSLLWZmikz", LIEF::assembly::x86::OPCODE::VPSLLWZmikz) + .value("VPSLLWZri", LIEF::assembly::x86::OPCODE::VPSLLWZri) + .value("VPSLLWZrik", LIEF::assembly::x86::OPCODE::VPSLLWZrik) + .value("VPSLLWZrikz", LIEF::assembly::x86::OPCODE::VPSLLWZrikz) + .value("VPSLLWZrm", LIEF::assembly::x86::OPCODE::VPSLLWZrm) + .value("VPSLLWZrmk", LIEF::assembly::x86::OPCODE::VPSLLWZrmk) + .value("VPSLLWZrmkz", LIEF::assembly::x86::OPCODE::VPSLLWZrmkz) + .value("VPSLLWZrr", LIEF::assembly::x86::OPCODE::VPSLLWZrr) + .value("VPSLLWZrrk", LIEF::assembly::x86::OPCODE::VPSLLWZrrk) + .value("VPSLLWZrrkz", LIEF::assembly::x86::OPCODE::VPSLLWZrrkz) + .value("VPSLLWri", LIEF::assembly::x86::OPCODE::VPSLLWri) + .value("VPSLLWrm", LIEF::assembly::x86::OPCODE::VPSLLWrm) + .value("VPSLLWrr", LIEF::assembly::x86::OPCODE::VPSLLWrr) + .value("VPSRADYri", LIEF::assembly::x86::OPCODE::VPSRADYri) + .value("VPSRADYrm", LIEF::assembly::x86::OPCODE::VPSRADYrm) + .value("VPSRADYrr", LIEF::assembly::x86::OPCODE::VPSRADYrr) + .value("VPSRADZ128mbi", LIEF::assembly::x86::OPCODE::VPSRADZ128mbi) + .value("VPSRADZ128mbik", LIEF::assembly::x86::OPCODE::VPSRADZ128mbik) + .value("VPSRADZ128mbikz", LIEF::assembly::x86::OPCODE::VPSRADZ128mbikz) + .value("VPSRADZ128mi", LIEF::assembly::x86::OPCODE::VPSRADZ128mi) + .value("VPSRADZ128mik", LIEF::assembly::x86::OPCODE::VPSRADZ128mik) + .value("VPSRADZ128mikz", LIEF::assembly::x86::OPCODE::VPSRADZ128mikz) + .value("VPSRADZ128ri", LIEF::assembly::x86::OPCODE::VPSRADZ128ri) + .value("VPSRADZ128rik", LIEF::assembly::x86::OPCODE::VPSRADZ128rik) + .value("VPSRADZ128rikz", LIEF::assembly::x86::OPCODE::VPSRADZ128rikz) + .value("VPSRADZ128rm", LIEF::assembly::x86::OPCODE::VPSRADZ128rm) + .value("VPSRADZ128rmk", LIEF::assembly::x86::OPCODE::VPSRADZ128rmk) + .value("VPSRADZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRADZ128rmkz) + .value("VPSRADZ128rr", LIEF::assembly::x86::OPCODE::VPSRADZ128rr) + .value("VPSRADZ128rrk", LIEF::assembly::x86::OPCODE::VPSRADZ128rrk) + .value("VPSRADZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRADZ128rrkz) + .value("VPSRADZ256mbi", LIEF::assembly::x86::OPCODE::VPSRADZ256mbi) + .value("VPSRADZ256mbik", LIEF::assembly::x86::OPCODE::VPSRADZ256mbik) + .value("VPSRADZ256mbikz", LIEF::assembly::x86::OPCODE::VPSRADZ256mbikz) + .value("VPSRADZ256mi", LIEF::assembly::x86::OPCODE::VPSRADZ256mi) + .value("VPSRADZ256mik", LIEF::assembly::x86::OPCODE::VPSRADZ256mik) + .value("VPSRADZ256mikz", LIEF::assembly::x86::OPCODE::VPSRADZ256mikz) + .value("VPSRADZ256ri", LIEF::assembly::x86::OPCODE::VPSRADZ256ri) + .value("VPSRADZ256rik", LIEF::assembly::x86::OPCODE::VPSRADZ256rik) + .value("VPSRADZ256rikz", LIEF::assembly::x86::OPCODE::VPSRADZ256rikz) + .value("VPSRADZ256rm", LIEF::assembly::x86::OPCODE::VPSRADZ256rm) + .value("VPSRADZ256rmk", LIEF::assembly::x86::OPCODE::VPSRADZ256rmk) + .value("VPSRADZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRADZ256rmkz) + .value("VPSRADZ256rr", LIEF::assembly::x86::OPCODE::VPSRADZ256rr) + .value("VPSRADZ256rrk", LIEF::assembly::x86::OPCODE::VPSRADZ256rrk) + .value("VPSRADZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRADZ256rrkz) + .value("VPSRADZmbi", LIEF::assembly::x86::OPCODE::VPSRADZmbi) + .value("VPSRADZmbik", LIEF::assembly::x86::OPCODE::VPSRADZmbik) + .value("VPSRADZmbikz", LIEF::assembly::x86::OPCODE::VPSRADZmbikz) + .value("VPSRADZmi", LIEF::assembly::x86::OPCODE::VPSRADZmi) + .value("VPSRADZmik", LIEF::assembly::x86::OPCODE::VPSRADZmik) + .value("VPSRADZmikz", LIEF::assembly::x86::OPCODE::VPSRADZmikz) + .value("VPSRADZri", LIEF::assembly::x86::OPCODE::VPSRADZri) + .value("VPSRADZrik", LIEF::assembly::x86::OPCODE::VPSRADZrik) + .value("VPSRADZrikz", LIEF::assembly::x86::OPCODE::VPSRADZrikz) + .value("VPSRADZrm", LIEF::assembly::x86::OPCODE::VPSRADZrm) + .value("VPSRADZrmk", LIEF::assembly::x86::OPCODE::VPSRADZrmk) + .value("VPSRADZrmkz", LIEF::assembly::x86::OPCODE::VPSRADZrmkz) + .value("VPSRADZrr", LIEF::assembly::x86::OPCODE::VPSRADZrr) + .value("VPSRADZrrk", LIEF::assembly::x86::OPCODE::VPSRADZrrk) + .value("VPSRADZrrkz", LIEF::assembly::x86::OPCODE::VPSRADZrrkz) + .value("VPSRADri", LIEF::assembly::x86::OPCODE::VPSRADri) + .value("VPSRADrm", LIEF::assembly::x86::OPCODE::VPSRADrm) + .value("VPSRADrr", LIEF::assembly::x86::OPCODE::VPSRADrr) + .value("VPSRAQZ128mbi", LIEF::assembly::x86::OPCODE::VPSRAQZ128mbi) + .value("VPSRAQZ128mbik", LIEF::assembly::x86::OPCODE::VPSRAQZ128mbik) + .value("VPSRAQZ128mbikz", LIEF::assembly::x86::OPCODE::VPSRAQZ128mbikz) + .value("VPSRAQZ128mi", LIEF::assembly::x86::OPCODE::VPSRAQZ128mi) + .value("VPSRAQZ128mik", LIEF::assembly::x86::OPCODE::VPSRAQZ128mik) + .value("VPSRAQZ128mikz", LIEF::assembly::x86::OPCODE::VPSRAQZ128mikz) + .value("VPSRAQZ128ri", LIEF::assembly::x86::OPCODE::VPSRAQZ128ri) + .value("VPSRAQZ128rik", LIEF::assembly::x86::OPCODE::VPSRAQZ128rik) + .value("VPSRAQZ128rikz", LIEF::assembly::x86::OPCODE::VPSRAQZ128rikz) + .value("VPSRAQZ128rm", LIEF::assembly::x86::OPCODE::VPSRAQZ128rm) + .value("VPSRAQZ128rmk", LIEF::assembly::x86::OPCODE::VPSRAQZ128rmk) + .value("VPSRAQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRAQZ128rmkz) + .value("VPSRAQZ128rr", LIEF::assembly::x86::OPCODE::VPSRAQZ128rr) + .value("VPSRAQZ128rrk", LIEF::assembly::x86::OPCODE::VPSRAQZ128rrk) + .value("VPSRAQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRAQZ128rrkz) + .value("VPSRAQZ256mbi", LIEF::assembly::x86::OPCODE::VPSRAQZ256mbi) + .value("VPSRAQZ256mbik", LIEF::assembly::x86::OPCODE::VPSRAQZ256mbik) + .value("VPSRAQZ256mbikz", LIEF::assembly::x86::OPCODE::VPSRAQZ256mbikz) + .value("VPSRAQZ256mi", LIEF::assembly::x86::OPCODE::VPSRAQZ256mi) + .value("VPSRAQZ256mik", LIEF::assembly::x86::OPCODE::VPSRAQZ256mik) + .value("VPSRAQZ256mikz", LIEF::assembly::x86::OPCODE::VPSRAQZ256mikz) + .value("VPSRAQZ256ri", LIEF::assembly::x86::OPCODE::VPSRAQZ256ri) + .value("VPSRAQZ256rik", LIEF::assembly::x86::OPCODE::VPSRAQZ256rik) + .value("VPSRAQZ256rikz", LIEF::assembly::x86::OPCODE::VPSRAQZ256rikz) + .value("VPSRAQZ256rm", LIEF::assembly::x86::OPCODE::VPSRAQZ256rm) + .value("VPSRAQZ256rmk", LIEF::assembly::x86::OPCODE::VPSRAQZ256rmk) + .value("VPSRAQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRAQZ256rmkz) + .value("VPSRAQZ256rr", LIEF::assembly::x86::OPCODE::VPSRAQZ256rr) + .value("VPSRAQZ256rrk", LIEF::assembly::x86::OPCODE::VPSRAQZ256rrk) + .value("VPSRAQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRAQZ256rrkz) + .value("VPSRAQZmbi", LIEF::assembly::x86::OPCODE::VPSRAQZmbi) + .value("VPSRAQZmbik", LIEF::assembly::x86::OPCODE::VPSRAQZmbik) + .value("VPSRAQZmbikz", LIEF::assembly::x86::OPCODE::VPSRAQZmbikz) + .value("VPSRAQZmi", LIEF::assembly::x86::OPCODE::VPSRAQZmi) + .value("VPSRAQZmik", LIEF::assembly::x86::OPCODE::VPSRAQZmik) + .value("VPSRAQZmikz", LIEF::assembly::x86::OPCODE::VPSRAQZmikz) + .value("VPSRAQZri", LIEF::assembly::x86::OPCODE::VPSRAQZri) + .value("VPSRAQZrik", LIEF::assembly::x86::OPCODE::VPSRAQZrik) + .value("VPSRAQZrikz", LIEF::assembly::x86::OPCODE::VPSRAQZrikz) + .value("VPSRAQZrm", LIEF::assembly::x86::OPCODE::VPSRAQZrm) + .value("VPSRAQZrmk", LIEF::assembly::x86::OPCODE::VPSRAQZrmk) + .value("VPSRAQZrmkz", LIEF::assembly::x86::OPCODE::VPSRAQZrmkz) + .value("VPSRAQZrr", LIEF::assembly::x86::OPCODE::VPSRAQZrr) + .value("VPSRAQZrrk", LIEF::assembly::x86::OPCODE::VPSRAQZrrk) + .value("VPSRAQZrrkz", LIEF::assembly::x86::OPCODE::VPSRAQZrrkz) + .value("VPSRAVDYrm", LIEF::assembly::x86::OPCODE::VPSRAVDYrm) + .value("VPSRAVDYrr", LIEF::assembly::x86::OPCODE::VPSRAVDYrr) + .value("VPSRAVDZ128rm", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rm) + .value("VPSRAVDZ128rmb", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rmb) + .value("VPSRAVDZ128rmbk", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rmbk) + .value("VPSRAVDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rmbkz) + .value("VPSRAVDZ128rmk", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rmk) + .value("VPSRAVDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rmkz) + .value("VPSRAVDZ128rr", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rr) + .value("VPSRAVDZ128rrk", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rrk) + .value("VPSRAVDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ128rrkz) + .value("VPSRAVDZ256rm", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rm) + .value("VPSRAVDZ256rmb", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rmb) + .value("VPSRAVDZ256rmbk", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rmbk) + .value("VPSRAVDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rmbkz) + .value("VPSRAVDZ256rmk", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rmk) + .value("VPSRAVDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rmkz) + .value("VPSRAVDZ256rr", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rr) + .value("VPSRAVDZ256rrk", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rrk) + .value("VPSRAVDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRAVDZ256rrkz) + .value("VPSRAVDZrm", LIEF::assembly::x86::OPCODE::VPSRAVDZrm) + .value("VPSRAVDZrmb", LIEF::assembly::x86::OPCODE::VPSRAVDZrmb) + .value("VPSRAVDZrmbk", LIEF::assembly::x86::OPCODE::VPSRAVDZrmbk) + .value("VPSRAVDZrmbkz", LIEF::assembly::x86::OPCODE::VPSRAVDZrmbkz) + .value("VPSRAVDZrmk", LIEF::assembly::x86::OPCODE::VPSRAVDZrmk) + .value("VPSRAVDZrmkz", LIEF::assembly::x86::OPCODE::VPSRAVDZrmkz) + .value("VPSRAVDZrr", LIEF::assembly::x86::OPCODE::VPSRAVDZrr) + .value("VPSRAVDZrrk", LIEF::assembly::x86::OPCODE::VPSRAVDZrrk) + .value("VPSRAVDZrrkz", LIEF::assembly::x86::OPCODE::VPSRAVDZrrkz) + .value("VPSRAVDrm", LIEF::assembly::x86::OPCODE::VPSRAVDrm) + .value("VPSRAVDrr", LIEF::assembly::x86::OPCODE::VPSRAVDrr) + .value("VPSRAVQZ128rm", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rm) + .value("VPSRAVQZ128rmb", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rmb) + .value("VPSRAVQZ128rmbk", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rmbk) + .value("VPSRAVQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rmbkz) + .value("VPSRAVQZ128rmk", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rmk) + .value("VPSRAVQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rmkz) + .value("VPSRAVQZ128rr", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rr) + .value("VPSRAVQZ128rrk", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rrk) + .value("VPSRAVQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ128rrkz) + .value("VPSRAVQZ256rm", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rm) + .value("VPSRAVQZ256rmb", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rmb) + .value("VPSRAVQZ256rmbk", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rmbk) + .value("VPSRAVQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rmbkz) + .value("VPSRAVQZ256rmk", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rmk) + .value("VPSRAVQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rmkz) + .value("VPSRAVQZ256rr", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rr) + .value("VPSRAVQZ256rrk", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rrk) + .value("VPSRAVQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRAVQZ256rrkz) + .value("VPSRAVQZrm", LIEF::assembly::x86::OPCODE::VPSRAVQZrm) + .value("VPSRAVQZrmb", LIEF::assembly::x86::OPCODE::VPSRAVQZrmb) + .value("VPSRAVQZrmbk", LIEF::assembly::x86::OPCODE::VPSRAVQZrmbk) + .value("VPSRAVQZrmbkz", LIEF::assembly::x86::OPCODE::VPSRAVQZrmbkz) + .value("VPSRAVQZrmk", LIEF::assembly::x86::OPCODE::VPSRAVQZrmk) + .value("VPSRAVQZrmkz", LIEF::assembly::x86::OPCODE::VPSRAVQZrmkz) + .value("VPSRAVQZrr", LIEF::assembly::x86::OPCODE::VPSRAVQZrr) + .value("VPSRAVQZrrk", LIEF::assembly::x86::OPCODE::VPSRAVQZrrk) + .value("VPSRAVQZrrkz", LIEF::assembly::x86::OPCODE::VPSRAVQZrrkz) + .value("VPSRAVWZ128rm", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rm) + .value("VPSRAVWZ128rmk", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rmk) + .value("VPSRAVWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rmkz) + .value("VPSRAVWZ128rr", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rr) + .value("VPSRAVWZ128rrk", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rrk) + .value("VPSRAVWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRAVWZ128rrkz) + .value("VPSRAVWZ256rm", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rm) + .value("VPSRAVWZ256rmk", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rmk) + .value("VPSRAVWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rmkz) + .value("VPSRAVWZ256rr", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rr) + .value("VPSRAVWZ256rrk", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rrk) + .value("VPSRAVWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRAVWZ256rrkz); + opcodes.value("VPSRAVWZrm", LIEF::assembly::x86::OPCODE::VPSRAVWZrm) + .value("VPSRAVWZrmk", LIEF::assembly::x86::OPCODE::VPSRAVWZrmk) + .value("VPSRAVWZrmkz", LIEF::assembly::x86::OPCODE::VPSRAVWZrmkz) + .value("VPSRAVWZrr", LIEF::assembly::x86::OPCODE::VPSRAVWZrr) + .value("VPSRAVWZrrk", LIEF::assembly::x86::OPCODE::VPSRAVWZrrk) + .value("VPSRAVWZrrkz", LIEF::assembly::x86::OPCODE::VPSRAVWZrrkz) + .value("VPSRAWYri", LIEF::assembly::x86::OPCODE::VPSRAWYri) + .value("VPSRAWYrm", LIEF::assembly::x86::OPCODE::VPSRAWYrm) + .value("VPSRAWYrr", LIEF::assembly::x86::OPCODE::VPSRAWYrr) + .value("VPSRAWZ128mi", LIEF::assembly::x86::OPCODE::VPSRAWZ128mi) + .value("VPSRAWZ128mik", LIEF::assembly::x86::OPCODE::VPSRAWZ128mik) + .value("VPSRAWZ128mikz", LIEF::assembly::x86::OPCODE::VPSRAWZ128mikz) + .value("VPSRAWZ128ri", LIEF::assembly::x86::OPCODE::VPSRAWZ128ri) + .value("VPSRAWZ128rik", LIEF::assembly::x86::OPCODE::VPSRAWZ128rik) + .value("VPSRAWZ128rikz", LIEF::assembly::x86::OPCODE::VPSRAWZ128rikz) + .value("VPSRAWZ128rm", LIEF::assembly::x86::OPCODE::VPSRAWZ128rm) + .value("VPSRAWZ128rmk", LIEF::assembly::x86::OPCODE::VPSRAWZ128rmk) + .value("VPSRAWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRAWZ128rmkz) + .value("VPSRAWZ128rr", LIEF::assembly::x86::OPCODE::VPSRAWZ128rr) + .value("VPSRAWZ128rrk", LIEF::assembly::x86::OPCODE::VPSRAWZ128rrk) + .value("VPSRAWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRAWZ128rrkz) + .value("VPSRAWZ256mi", LIEF::assembly::x86::OPCODE::VPSRAWZ256mi) + .value("VPSRAWZ256mik", LIEF::assembly::x86::OPCODE::VPSRAWZ256mik) + .value("VPSRAWZ256mikz", LIEF::assembly::x86::OPCODE::VPSRAWZ256mikz) + .value("VPSRAWZ256ri", LIEF::assembly::x86::OPCODE::VPSRAWZ256ri) + .value("VPSRAWZ256rik", LIEF::assembly::x86::OPCODE::VPSRAWZ256rik) + .value("VPSRAWZ256rikz", LIEF::assembly::x86::OPCODE::VPSRAWZ256rikz) + .value("VPSRAWZ256rm", LIEF::assembly::x86::OPCODE::VPSRAWZ256rm) + .value("VPSRAWZ256rmk", LIEF::assembly::x86::OPCODE::VPSRAWZ256rmk) + .value("VPSRAWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRAWZ256rmkz) + .value("VPSRAWZ256rr", LIEF::assembly::x86::OPCODE::VPSRAWZ256rr) + .value("VPSRAWZ256rrk", LIEF::assembly::x86::OPCODE::VPSRAWZ256rrk) + .value("VPSRAWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRAWZ256rrkz) + .value("VPSRAWZmi", LIEF::assembly::x86::OPCODE::VPSRAWZmi) + .value("VPSRAWZmik", LIEF::assembly::x86::OPCODE::VPSRAWZmik) + .value("VPSRAWZmikz", LIEF::assembly::x86::OPCODE::VPSRAWZmikz) + .value("VPSRAWZri", LIEF::assembly::x86::OPCODE::VPSRAWZri) + .value("VPSRAWZrik", LIEF::assembly::x86::OPCODE::VPSRAWZrik) + .value("VPSRAWZrikz", LIEF::assembly::x86::OPCODE::VPSRAWZrikz) + .value("VPSRAWZrm", LIEF::assembly::x86::OPCODE::VPSRAWZrm) + .value("VPSRAWZrmk", LIEF::assembly::x86::OPCODE::VPSRAWZrmk) + .value("VPSRAWZrmkz", LIEF::assembly::x86::OPCODE::VPSRAWZrmkz) + .value("VPSRAWZrr", LIEF::assembly::x86::OPCODE::VPSRAWZrr) + .value("VPSRAWZrrk", LIEF::assembly::x86::OPCODE::VPSRAWZrrk) + .value("VPSRAWZrrkz", LIEF::assembly::x86::OPCODE::VPSRAWZrrkz) + .value("VPSRAWri", LIEF::assembly::x86::OPCODE::VPSRAWri) + .value("VPSRAWrm", LIEF::assembly::x86::OPCODE::VPSRAWrm) + .value("VPSRAWrr", LIEF::assembly::x86::OPCODE::VPSRAWrr) + .value("VPSRLDQYri", LIEF::assembly::x86::OPCODE::VPSRLDQYri) + .value("VPSRLDQZ128mi", LIEF::assembly::x86::OPCODE::VPSRLDQZ128mi) + .value("VPSRLDQZ128ri", LIEF::assembly::x86::OPCODE::VPSRLDQZ128ri) + .value("VPSRLDQZ256mi", LIEF::assembly::x86::OPCODE::VPSRLDQZ256mi) + .value("VPSRLDQZ256ri", LIEF::assembly::x86::OPCODE::VPSRLDQZ256ri) + .value("VPSRLDQZmi", LIEF::assembly::x86::OPCODE::VPSRLDQZmi) + .value("VPSRLDQZri", LIEF::assembly::x86::OPCODE::VPSRLDQZri) + .value("VPSRLDQri", LIEF::assembly::x86::OPCODE::VPSRLDQri) + .value("VPSRLDYri", LIEF::assembly::x86::OPCODE::VPSRLDYri) + .value("VPSRLDYrm", LIEF::assembly::x86::OPCODE::VPSRLDYrm) + .value("VPSRLDYrr", LIEF::assembly::x86::OPCODE::VPSRLDYrr) + .value("VPSRLDZ128mbi", LIEF::assembly::x86::OPCODE::VPSRLDZ128mbi) + .value("VPSRLDZ128mbik", LIEF::assembly::x86::OPCODE::VPSRLDZ128mbik) + .value("VPSRLDZ128mbikz", LIEF::assembly::x86::OPCODE::VPSRLDZ128mbikz) + .value("VPSRLDZ128mi", LIEF::assembly::x86::OPCODE::VPSRLDZ128mi) + .value("VPSRLDZ128mik", LIEF::assembly::x86::OPCODE::VPSRLDZ128mik) + .value("VPSRLDZ128mikz", LIEF::assembly::x86::OPCODE::VPSRLDZ128mikz) + .value("VPSRLDZ128ri", LIEF::assembly::x86::OPCODE::VPSRLDZ128ri) + .value("VPSRLDZ128rik", LIEF::assembly::x86::OPCODE::VPSRLDZ128rik) + .value("VPSRLDZ128rikz", LIEF::assembly::x86::OPCODE::VPSRLDZ128rikz) + .value("VPSRLDZ128rm", LIEF::assembly::x86::OPCODE::VPSRLDZ128rm) + .value("VPSRLDZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLDZ128rmk) + .value("VPSRLDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLDZ128rmkz) + .value("VPSRLDZ128rr", LIEF::assembly::x86::OPCODE::VPSRLDZ128rr) + .value("VPSRLDZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLDZ128rrk) + .value("VPSRLDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLDZ128rrkz) + .value("VPSRLDZ256mbi", LIEF::assembly::x86::OPCODE::VPSRLDZ256mbi) + .value("VPSRLDZ256mbik", LIEF::assembly::x86::OPCODE::VPSRLDZ256mbik) + .value("VPSRLDZ256mbikz", LIEF::assembly::x86::OPCODE::VPSRLDZ256mbikz) + .value("VPSRLDZ256mi", LIEF::assembly::x86::OPCODE::VPSRLDZ256mi) + .value("VPSRLDZ256mik", LIEF::assembly::x86::OPCODE::VPSRLDZ256mik) + .value("VPSRLDZ256mikz", LIEF::assembly::x86::OPCODE::VPSRLDZ256mikz) + .value("VPSRLDZ256ri", LIEF::assembly::x86::OPCODE::VPSRLDZ256ri) + .value("VPSRLDZ256rik", LIEF::assembly::x86::OPCODE::VPSRLDZ256rik) + .value("VPSRLDZ256rikz", LIEF::assembly::x86::OPCODE::VPSRLDZ256rikz) + .value("VPSRLDZ256rm", LIEF::assembly::x86::OPCODE::VPSRLDZ256rm) + .value("VPSRLDZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLDZ256rmk) + .value("VPSRLDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLDZ256rmkz) + .value("VPSRLDZ256rr", LIEF::assembly::x86::OPCODE::VPSRLDZ256rr) + .value("VPSRLDZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLDZ256rrk) + .value("VPSRLDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLDZ256rrkz) + .value("VPSRLDZmbi", LIEF::assembly::x86::OPCODE::VPSRLDZmbi) + .value("VPSRLDZmbik", LIEF::assembly::x86::OPCODE::VPSRLDZmbik) + .value("VPSRLDZmbikz", LIEF::assembly::x86::OPCODE::VPSRLDZmbikz) + .value("VPSRLDZmi", LIEF::assembly::x86::OPCODE::VPSRLDZmi) + .value("VPSRLDZmik", LIEF::assembly::x86::OPCODE::VPSRLDZmik) + .value("VPSRLDZmikz", LIEF::assembly::x86::OPCODE::VPSRLDZmikz) + .value("VPSRLDZri", LIEF::assembly::x86::OPCODE::VPSRLDZri) + .value("VPSRLDZrik", LIEF::assembly::x86::OPCODE::VPSRLDZrik) + .value("VPSRLDZrikz", LIEF::assembly::x86::OPCODE::VPSRLDZrikz) + .value("VPSRLDZrm", LIEF::assembly::x86::OPCODE::VPSRLDZrm) + .value("VPSRLDZrmk", LIEF::assembly::x86::OPCODE::VPSRLDZrmk) + .value("VPSRLDZrmkz", LIEF::assembly::x86::OPCODE::VPSRLDZrmkz) + .value("VPSRLDZrr", LIEF::assembly::x86::OPCODE::VPSRLDZrr) + .value("VPSRLDZrrk", LIEF::assembly::x86::OPCODE::VPSRLDZrrk) + .value("VPSRLDZrrkz", LIEF::assembly::x86::OPCODE::VPSRLDZrrkz) + .value("VPSRLDri", LIEF::assembly::x86::OPCODE::VPSRLDri) + .value("VPSRLDrm", LIEF::assembly::x86::OPCODE::VPSRLDrm) + .value("VPSRLDrr", LIEF::assembly::x86::OPCODE::VPSRLDrr) + .value("VPSRLQYri", LIEF::assembly::x86::OPCODE::VPSRLQYri) + .value("VPSRLQYrm", LIEF::assembly::x86::OPCODE::VPSRLQYrm) + .value("VPSRLQYrr", LIEF::assembly::x86::OPCODE::VPSRLQYrr) + .value("VPSRLQZ128mbi", LIEF::assembly::x86::OPCODE::VPSRLQZ128mbi) + .value("VPSRLQZ128mbik", LIEF::assembly::x86::OPCODE::VPSRLQZ128mbik) + .value("VPSRLQZ128mbikz", LIEF::assembly::x86::OPCODE::VPSRLQZ128mbikz) + .value("VPSRLQZ128mi", LIEF::assembly::x86::OPCODE::VPSRLQZ128mi) + .value("VPSRLQZ128mik", LIEF::assembly::x86::OPCODE::VPSRLQZ128mik) + .value("VPSRLQZ128mikz", LIEF::assembly::x86::OPCODE::VPSRLQZ128mikz) + .value("VPSRLQZ128ri", LIEF::assembly::x86::OPCODE::VPSRLQZ128ri) + .value("VPSRLQZ128rik", LIEF::assembly::x86::OPCODE::VPSRLQZ128rik) + .value("VPSRLQZ128rikz", LIEF::assembly::x86::OPCODE::VPSRLQZ128rikz) + .value("VPSRLQZ128rm", LIEF::assembly::x86::OPCODE::VPSRLQZ128rm) + .value("VPSRLQZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLQZ128rmk) + .value("VPSRLQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLQZ128rmkz) + .value("VPSRLQZ128rr", LIEF::assembly::x86::OPCODE::VPSRLQZ128rr) + .value("VPSRLQZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLQZ128rrk) + .value("VPSRLQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLQZ128rrkz) + .value("VPSRLQZ256mbi", LIEF::assembly::x86::OPCODE::VPSRLQZ256mbi) + .value("VPSRLQZ256mbik", LIEF::assembly::x86::OPCODE::VPSRLQZ256mbik) + .value("VPSRLQZ256mbikz", LIEF::assembly::x86::OPCODE::VPSRLQZ256mbikz) + .value("VPSRLQZ256mi", LIEF::assembly::x86::OPCODE::VPSRLQZ256mi) + .value("VPSRLQZ256mik", LIEF::assembly::x86::OPCODE::VPSRLQZ256mik) + .value("VPSRLQZ256mikz", LIEF::assembly::x86::OPCODE::VPSRLQZ256mikz) + .value("VPSRLQZ256ri", LIEF::assembly::x86::OPCODE::VPSRLQZ256ri) + .value("VPSRLQZ256rik", LIEF::assembly::x86::OPCODE::VPSRLQZ256rik) + .value("VPSRLQZ256rikz", LIEF::assembly::x86::OPCODE::VPSRLQZ256rikz) + .value("VPSRLQZ256rm", LIEF::assembly::x86::OPCODE::VPSRLQZ256rm) + .value("VPSRLQZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLQZ256rmk) + .value("VPSRLQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLQZ256rmkz) + .value("VPSRLQZ256rr", LIEF::assembly::x86::OPCODE::VPSRLQZ256rr) + .value("VPSRLQZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLQZ256rrk) + .value("VPSRLQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLQZ256rrkz) + .value("VPSRLQZmbi", LIEF::assembly::x86::OPCODE::VPSRLQZmbi) + .value("VPSRLQZmbik", LIEF::assembly::x86::OPCODE::VPSRLQZmbik) + .value("VPSRLQZmbikz", LIEF::assembly::x86::OPCODE::VPSRLQZmbikz) + .value("VPSRLQZmi", LIEF::assembly::x86::OPCODE::VPSRLQZmi) + .value("VPSRLQZmik", LIEF::assembly::x86::OPCODE::VPSRLQZmik) + .value("VPSRLQZmikz", LIEF::assembly::x86::OPCODE::VPSRLQZmikz) + .value("VPSRLQZri", LIEF::assembly::x86::OPCODE::VPSRLQZri) + .value("VPSRLQZrik", LIEF::assembly::x86::OPCODE::VPSRLQZrik) + .value("VPSRLQZrikz", LIEF::assembly::x86::OPCODE::VPSRLQZrikz) + .value("VPSRLQZrm", LIEF::assembly::x86::OPCODE::VPSRLQZrm) + .value("VPSRLQZrmk", LIEF::assembly::x86::OPCODE::VPSRLQZrmk) + .value("VPSRLQZrmkz", LIEF::assembly::x86::OPCODE::VPSRLQZrmkz) + .value("VPSRLQZrr", LIEF::assembly::x86::OPCODE::VPSRLQZrr) + .value("VPSRLQZrrk", LIEF::assembly::x86::OPCODE::VPSRLQZrrk) + .value("VPSRLQZrrkz", LIEF::assembly::x86::OPCODE::VPSRLQZrrkz) + .value("VPSRLQri", LIEF::assembly::x86::OPCODE::VPSRLQri) + .value("VPSRLQrm", LIEF::assembly::x86::OPCODE::VPSRLQrm) + .value("VPSRLQrr", LIEF::assembly::x86::OPCODE::VPSRLQrr) + .value("VPSRLVDYrm", LIEF::assembly::x86::OPCODE::VPSRLVDYrm) + .value("VPSRLVDYrr", LIEF::assembly::x86::OPCODE::VPSRLVDYrr) + .value("VPSRLVDZ128rm", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rm) + .value("VPSRLVDZ128rmb", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rmb) + .value("VPSRLVDZ128rmbk", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rmbk) + .value("VPSRLVDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rmbkz) + .value("VPSRLVDZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rmk) + .value("VPSRLVDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rmkz) + .value("VPSRLVDZ128rr", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rr) + .value("VPSRLVDZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rrk) + .value("VPSRLVDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ128rrkz) + .value("VPSRLVDZ256rm", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rm) + .value("VPSRLVDZ256rmb", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rmb) + .value("VPSRLVDZ256rmbk", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rmbk) + .value("VPSRLVDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rmbkz) + .value("VPSRLVDZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rmk) + .value("VPSRLVDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rmkz) + .value("VPSRLVDZ256rr", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rr) + .value("VPSRLVDZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rrk) + .value("VPSRLVDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLVDZ256rrkz) + .value("VPSRLVDZrm", LIEF::assembly::x86::OPCODE::VPSRLVDZrm) + .value("VPSRLVDZrmb", LIEF::assembly::x86::OPCODE::VPSRLVDZrmb) + .value("VPSRLVDZrmbk", LIEF::assembly::x86::OPCODE::VPSRLVDZrmbk) + .value("VPSRLVDZrmbkz", LIEF::assembly::x86::OPCODE::VPSRLVDZrmbkz) + .value("VPSRLVDZrmk", LIEF::assembly::x86::OPCODE::VPSRLVDZrmk) + .value("VPSRLVDZrmkz", LIEF::assembly::x86::OPCODE::VPSRLVDZrmkz) + .value("VPSRLVDZrr", LIEF::assembly::x86::OPCODE::VPSRLVDZrr) + .value("VPSRLVDZrrk", LIEF::assembly::x86::OPCODE::VPSRLVDZrrk) + .value("VPSRLVDZrrkz", LIEF::assembly::x86::OPCODE::VPSRLVDZrrkz) + .value("VPSRLVDrm", LIEF::assembly::x86::OPCODE::VPSRLVDrm) + .value("VPSRLVDrr", LIEF::assembly::x86::OPCODE::VPSRLVDrr) + .value("VPSRLVQYrm", LIEF::assembly::x86::OPCODE::VPSRLVQYrm) + .value("VPSRLVQYrr", LIEF::assembly::x86::OPCODE::VPSRLVQYrr) + .value("VPSRLVQZ128rm", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rm) + .value("VPSRLVQZ128rmb", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rmb) + .value("VPSRLVQZ128rmbk", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rmbk) + .value("VPSRLVQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rmbkz) + .value("VPSRLVQZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rmk) + .value("VPSRLVQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rmkz) + .value("VPSRLVQZ128rr", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rr) + .value("VPSRLVQZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rrk) + .value("VPSRLVQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ128rrkz) + .value("VPSRLVQZ256rm", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rm) + .value("VPSRLVQZ256rmb", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rmb) + .value("VPSRLVQZ256rmbk", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rmbk) + .value("VPSRLVQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rmbkz) + .value("VPSRLVQZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rmk) + .value("VPSRLVQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rmkz) + .value("VPSRLVQZ256rr", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rr) + .value("VPSRLVQZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rrk) + .value("VPSRLVQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLVQZ256rrkz) + .value("VPSRLVQZrm", LIEF::assembly::x86::OPCODE::VPSRLVQZrm) + .value("VPSRLVQZrmb", LIEF::assembly::x86::OPCODE::VPSRLVQZrmb) + .value("VPSRLVQZrmbk", LIEF::assembly::x86::OPCODE::VPSRLVQZrmbk) + .value("VPSRLVQZrmbkz", LIEF::assembly::x86::OPCODE::VPSRLVQZrmbkz) + .value("VPSRLVQZrmk", LIEF::assembly::x86::OPCODE::VPSRLVQZrmk) + .value("VPSRLVQZrmkz", LIEF::assembly::x86::OPCODE::VPSRLVQZrmkz) + .value("VPSRLVQZrr", LIEF::assembly::x86::OPCODE::VPSRLVQZrr) + .value("VPSRLVQZrrk", LIEF::assembly::x86::OPCODE::VPSRLVQZrrk) + .value("VPSRLVQZrrkz", LIEF::assembly::x86::OPCODE::VPSRLVQZrrkz) + .value("VPSRLVQrm", LIEF::assembly::x86::OPCODE::VPSRLVQrm) + .value("VPSRLVQrr", LIEF::assembly::x86::OPCODE::VPSRLVQrr) + .value("VPSRLVWZ128rm", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rm) + .value("VPSRLVWZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rmk) + .value("VPSRLVWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rmkz) + .value("VPSRLVWZ128rr", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rr) + .value("VPSRLVWZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rrk) + .value("VPSRLVWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLVWZ128rrkz) + .value("VPSRLVWZ256rm", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rm) + .value("VPSRLVWZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rmk) + .value("VPSRLVWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rmkz) + .value("VPSRLVWZ256rr", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rr) + .value("VPSRLVWZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rrk) + .value("VPSRLVWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLVWZ256rrkz) + .value("VPSRLVWZrm", LIEF::assembly::x86::OPCODE::VPSRLVWZrm) + .value("VPSRLVWZrmk", LIEF::assembly::x86::OPCODE::VPSRLVWZrmk) + .value("VPSRLVWZrmkz", LIEF::assembly::x86::OPCODE::VPSRLVWZrmkz) + .value("VPSRLVWZrr", LIEF::assembly::x86::OPCODE::VPSRLVWZrr) + .value("VPSRLVWZrrk", LIEF::assembly::x86::OPCODE::VPSRLVWZrrk) + .value("VPSRLVWZrrkz", LIEF::assembly::x86::OPCODE::VPSRLVWZrrkz) + .value("VPSRLWYri", LIEF::assembly::x86::OPCODE::VPSRLWYri) + .value("VPSRLWYrm", LIEF::assembly::x86::OPCODE::VPSRLWYrm) + .value("VPSRLWYrr", LIEF::assembly::x86::OPCODE::VPSRLWYrr) + .value("VPSRLWZ128mi", LIEF::assembly::x86::OPCODE::VPSRLWZ128mi) + .value("VPSRLWZ128mik", LIEF::assembly::x86::OPCODE::VPSRLWZ128mik) + .value("VPSRLWZ128mikz", LIEF::assembly::x86::OPCODE::VPSRLWZ128mikz) + .value("VPSRLWZ128ri", LIEF::assembly::x86::OPCODE::VPSRLWZ128ri) + .value("VPSRLWZ128rik", LIEF::assembly::x86::OPCODE::VPSRLWZ128rik) + .value("VPSRLWZ128rikz", LIEF::assembly::x86::OPCODE::VPSRLWZ128rikz) + .value("VPSRLWZ128rm", LIEF::assembly::x86::OPCODE::VPSRLWZ128rm) + .value("VPSRLWZ128rmk", LIEF::assembly::x86::OPCODE::VPSRLWZ128rmk) + .value("VPSRLWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSRLWZ128rmkz) + .value("VPSRLWZ128rr", LIEF::assembly::x86::OPCODE::VPSRLWZ128rr) + .value("VPSRLWZ128rrk", LIEF::assembly::x86::OPCODE::VPSRLWZ128rrk) + .value("VPSRLWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSRLWZ128rrkz) + .value("VPSRLWZ256mi", LIEF::assembly::x86::OPCODE::VPSRLWZ256mi) + .value("VPSRLWZ256mik", LIEF::assembly::x86::OPCODE::VPSRLWZ256mik) + .value("VPSRLWZ256mikz", LIEF::assembly::x86::OPCODE::VPSRLWZ256mikz) + .value("VPSRLWZ256ri", LIEF::assembly::x86::OPCODE::VPSRLWZ256ri) + .value("VPSRLWZ256rik", LIEF::assembly::x86::OPCODE::VPSRLWZ256rik) + .value("VPSRLWZ256rikz", LIEF::assembly::x86::OPCODE::VPSRLWZ256rikz) + .value("VPSRLWZ256rm", LIEF::assembly::x86::OPCODE::VPSRLWZ256rm) + .value("VPSRLWZ256rmk", LIEF::assembly::x86::OPCODE::VPSRLWZ256rmk) + .value("VPSRLWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSRLWZ256rmkz) + .value("VPSRLWZ256rr", LIEF::assembly::x86::OPCODE::VPSRLWZ256rr) + .value("VPSRLWZ256rrk", LIEF::assembly::x86::OPCODE::VPSRLWZ256rrk) + .value("VPSRLWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSRLWZ256rrkz) + .value("VPSRLWZmi", LIEF::assembly::x86::OPCODE::VPSRLWZmi) + .value("VPSRLWZmik", LIEF::assembly::x86::OPCODE::VPSRLWZmik) + .value("VPSRLWZmikz", LIEF::assembly::x86::OPCODE::VPSRLWZmikz) + .value("VPSRLWZri", LIEF::assembly::x86::OPCODE::VPSRLWZri) + .value("VPSRLWZrik", LIEF::assembly::x86::OPCODE::VPSRLWZrik) + .value("VPSRLWZrikz", LIEF::assembly::x86::OPCODE::VPSRLWZrikz) + .value("VPSRLWZrm", LIEF::assembly::x86::OPCODE::VPSRLWZrm) + .value("VPSRLWZrmk", LIEF::assembly::x86::OPCODE::VPSRLWZrmk) + .value("VPSRLWZrmkz", LIEF::assembly::x86::OPCODE::VPSRLWZrmkz) + .value("VPSRLWZrr", LIEF::assembly::x86::OPCODE::VPSRLWZrr) + .value("VPSRLWZrrk", LIEF::assembly::x86::OPCODE::VPSRLWZrrk) + .value("VPSRLWZrrkz", LIEF::assembly::x86::OPCODE::VPSRLWZrrkz) + .value("VPSRLWri", LIEF::assembly::x86::OPCODE::VPSRLWri) + .value("VPSRLWrm", LIEF::assembly::x86::OPCODE::VPSRLWrm) + .value("VPSRLWrr", LIEF::assembly::x86::OPCODE::VPSRLWrr) + .value("VPSUBBYrm", LIEF::assembly::x86::OPCODE::VPSUBBYrm) + .value("VPSUBBYrr", LIEF::assembly::x86::OPCODE::VPSUBBYrr) + .value("VPSUBBZ128rm", LIEF::assembly::x86::OPCODE::VPSUBBZ128rm) + .value("VPSUBBZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBBZ128rmk) + .value("VPSUBBZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBBZ128rmkz) + .value("VPSUBBZ128rr", LIEF::assembly::x86::OPCODE::VPSUBBZ128rr) + .value("VPSUBBZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBBZ128rrk) + .value("VPSUBBZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBBZ128rrkz) + .value("VPSUBBZ256rm", LIEF::assembly::x86::OPCODE::VPSUBBZ256rm) + .value("VPSUBBZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBBZ256rmk) + .value("VPSUBBZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBBZ256rmkz) + .value("VPSUBBZ256rr", LIEF::assembly::x86::OPCODE::VPSUBBZ256rr) + .value("VPSUBBZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBBZ256rrk) + .value("VPSUBBZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBBZ256rrkz) + .value("VPSUBBZrm", LIEF::assembly::x86::OPCODE::VPSUBBZrm) + .value("VPSUBBZrmk", LIEF::assembly::x86::OPCODE::VPSUBBZrmk) + .value("VPSUBBZrmkz", LIEF::assembly::x86::OPCODE::VPSUBBZrmkz) + .value("VPSUBBZrr", LIEF::assembly::x86::OPCODE::VPSUBBZrr) + .value("VPSUBBZrrk", LIEF::assembly::x86::OPCODE::VPSUBBZrrk) + .value("VPSUBBZrrkz", LIEF::assembly::x86::OPCODE::VPSUBBZrrkz); + opcodes.value("VPSUBBrm", LIEF::assembly::x86::OPCODE::VPSUBBrm) + .value("VPSUBBrr", LIEF::assembly::x86::OPCODE::VPSUBBrr) + .value("VPSUBDYrm", LIEF::assembly::x86::OPCODE::VPSUBDYrm) + .value("VPSUBDYrr", LIEF::assembly::x86::OPCODE::VPSUBDYrr) + .value("VPSUBDZ128rm", LIEF::assembly::x86::OPCODE::VPSUBDZ128rm) + .value("VPSUBDZ128rmb", LIEF::assembly::x86::OPCODE::VPSUBDZ128rmb) + .value("VPSUBDZ128rmbk", LIEF::assembly::x86::OPCODE::VPSUBDZ128rmbk) + .value("VPSUBDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSUBDZ128rmbkz) + .value("VPSUBDZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBDZ128rmk) + .value("VPSUBDZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBDZ128rmkz) + .value("VPSUBDZ128rr", LIEF::assembly::x86::OPCODE::VPSUBDZ128rr) + .value("VPSUBDZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBDZ128rrk) + .value("VPSUBDZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBDZ128rrkz) + .value("VPSUBDZ256rm", LIEF::assembly::x86::OPCODE::VPSUBDZ256rm) + .value("VPSUBDZ256rmb", LIEF::assembly::x86::OPCODE::VPSUBDZ256rmb) + .value("VPSUBDZ256rmbk", LIEF::assembly::x86::OPCODE::VPSUBDZ256rmbk) + .value("VPSUBDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSUBDZ256rmbkz) + .value("VPSUBDZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBDZ256rmk) + .value("VPSUBDZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBDZ256rmkz) + .value("VPSUBDZ256rr", LIEF::assembly::x86::OPCODE::VPSUBDZ256rr) + .value("VPSUBDZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBDZ256rrk) + .value("VPSUBDZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBDZ256rrkz) + .value("VPSUBDZrm", LIEF::assembly::x86::OPCODE::VPSUBDZrm) + .value("VPSUBDZrmb", LIEF::assembly::x86::OPCODE::VPSUBDZrmb) + .value("VPSUBDZrmbk", LIEF::assembly::x86::OPCODE::VPSUBDZrmbk) + .value("VPSUBDZrmbkz", LIEF::assembly::x86::OPCODE::VPSUBDZrmbkz) + .value("VPSUBDZrmk", LIEF::assembly::x86::OPCODE::VPSUBDZrmk) + .value("VPSUBDZrmkz", LIEF::assembly::x86::OPCODE::VPSUBDZrmkz) + .value("VPSUBDZrr", LIEF::assembly::x86::OPCODE::VPSUBDZrr) + .value("VPSUBDZrrk", LIEF::assembly::x86::OPCODE::VPSUBDZrrk) + .value("VPSUBDZrrkz", LIEF::assembly::x86::OPCODE::VPSUBDZrrkz) + .value("VPSUBDrm", LIEF::assembly::x86::OPCODE::VPSUBDrm) + .value("VPSUBDrr", LIEF::assembly::x86::OPCODE::VPSUBDrr) + .value("VPSUBQYrm", LIEF::assembly::x86::OPCODE::VPSUBQYrm) + .value("VPSUBQYrr", LIEF::assembly::x86::OPCODE::VPSUBQYrr) + .value("VPSUBQZ128rm", LIEF::assembly::x86::OPCODE::VPSUBQZ128rm) + .value("VPSUBQZ128rmb", LIEF::assembly::x86::OPCODE::VPSUBQZ128rmb) + .value("VPSUBQZ128rmbk", LIEF::assembly::x86::OPCODE::VPSUBQZ128rmbk) + .value("VPSUBQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPSUBQZ128rmbkz) + .value("VPSUBQZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBQZ128rmk) + .value("VPSUBQZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBQZ128rmkz) + .value("VPSUBQZ128rr", LIEF::assembly::x86::OPCODE::VPSUBQZ128rr) + .value("VPSUBQZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBQZ128rrk) + .value("VPSUBQZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBQZ128rrkz) + .value("VPSUBQZ256rm", LIEF::assembly::x86::OPCODE::VPSUBQZ256rm) + .value("VPSUBQZ256rmb", LIEF::assembly::x86::OPCODE::VPSUBQZ256rmb) + .value("VPSUBQZ256rmbk", LIEF::assembly::x86::OPCODE::VPSUBQZ256rmbk) + .value("VPSUBQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPSUBQZ256rmbkz) + .value("VPSUBQZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBQZ256rmk) + .value("VPSUBQZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBQZ256rmkz) + .value("VPSUBQZ256rr", LIEF::assembly::x86::OPCODE::VPSUBQZ256rr) + .value("VPSUBQZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBQZ256rrk) + .value("VPSUBQZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBQZ256rrkz) + .value("VPSUBQZrm", LIEF::assembly::x86::OPCODE::VPSUBQZrm) + .value("VPSUBQZrmb", LIEF::assembly::x86::OPCODE::VPSUBQZrmb) + .value("VPSUBQZrmbk", LIEF::assembly::x86::OPCODE::VPSUBQZrmbk) + .value("VPSUBQZrmbkz", LIEF::assembly::x86::OPCODE::VPSUBQZrmbkz) + .value("VPSUBQZrmk", LIEF::assembly::x86::OPCODE::VPSUBQZrmk) + .value("VPSUBQZrmkz", LIEF::assembly::x86::OPCODE::VPSUBQZrmkz) + .value("VPSUBQZrr", LIEF::assembly::x86::OPCODE::VPSUBQZrr) + .value("VPSUBQZrrk", LIEF::assembly::x86::OPCODE::VPSUBQZrrk) + .value("VPSUBQZrrkz", LIEF::assembly::x86::OPCODE::VPSUBQZrrkz) + .value("VPSUBQrm", LIEF::assembly::x86::OPCODE::VPSUBQrm) + .value("VPSUBQrr", LIEF::assembly::x86::OPCODE::VPSUBQrr) + .value("VPSUBSBYrm", LIEF::assembly::x86::OPCODE::VPSUBSBYrm) + .value("VPSUBSBYrr", LIEF::assembly::x86::OPCODE::VPSUBSBYrr) + .value("VPSUBSBZ128rm", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rm) + .value("VPSUBSBZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rmk) + .value("VPSUBSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rmkz) + .value("VPSUBSBZ128rr", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rr) + .value("VPSUBSBZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rrk) + .value("VPSUBSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBSBZ128rrkz) + .value("VPSUBSBZ256rm", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rm) + .value("VPSUBSBZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rmk) + .value("VPSUBSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rmkz) + .value("VPSUBSBZ256rr", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rr) + .value("VPSUBSBZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rrk) + .value("VPSUBSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBSBZ256rrkz) + .value("VPSUBSBZrm", LIEF::assembly::x86::OPCODE::VPSUBSBZrm) + .value("VPSUBSBZrmk", LIEF::assembly::x86::OPCODE::VPSUBSBZrmk) + .value("VPSUBSBZrmkz", LIEF::assembly::x86::OPCODE::VPSUBSBZrmkz) + .value("VPSUBSBZrr", LIEF::assembly::x86::OPCODE::VPSUBSBZrr) + .value("VPSUBSBZrrk", LIEF::assembly::x86::OPCODE::VPSUBSBZrrk) + .value("VPSUBSBZrrkz", LIEF::assembly::x86::OPCODE::VPSUBSBZrrkz) + .value("VPSUBSBrm", LIEF::assembly::x86::OPCODE::VPSUBSBrm) + .value("VPSUBSBrr", LIEF::assembly::x86::OPCODE::VPSUBSBrr) + .value("VPSUBSWYrm", LIEF::assembly::x86::OPCODE::VPSUBSWYrm) + .value("VPSUBSWYrr", LIEF::assembly::x86::OPCODE::VPSUBSWYrr) + .value("VPSUBSWZ128rm", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rm) + .value("VPSUBSWZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rmk) + .value("VPSUBSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rmkz) + .value("VPSUBSWZ128rr", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rr) + .value("VPSUBSWZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rrk) + .value("VPSUBSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBSWZ128rrkz) + .value("VPSUBSWZ256rm", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rm) + .value("VPSUBSWZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rmk) + .value("VPSUBSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rmkz) + .value("VPSUBSWZ256rr", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rr) + .value("VPSUBSWZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rrk) + .value("VPSUBSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBSWZ256rrkz) + .value("VPSUBSWZrm", LIEF::assembly::x86::OPCODE::VPSUBSWZrm) + .value("VPSUBSWZrmk", LIEF::assembly::x86::OPCODE::VPSUBSWZrmk) + .value("VPSUBSWZrmkz", LIEF::assembly::x86::OPCODE::VPSUBSWZrmkz) + .value("VPSUBSWZrr", LIEF::assembly::x86::OPCODE::VPSUBSWZrr) + .value("VPSUBSWZrrk", LIEF::assembly::x86::OPCODE::VPSUBSWZrrk) + .value("VPSUBSWZrrkz", LIEF::assembly::x86::OPCODE::VPSUBSWZrrkz) + .value("VPSUBSWrm", LIEF::assembly::x86::OPCODE::VPSUBSWrm) + .value("VPSUBSWrr", LIEF::assembly::x86::OPCODE::VPSUBSWrr) + .value("VPSUBUSBYrm", LIEF::assembly::x86::OPCODE::VPSUBUSBYrm) + .value("VPSUBUSBYrr", LIEF::assembly::x86::OPCODE::VPSUBUSBYrr) + .value("VPSUBUSBZ128rm", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rm) + .value("VPSUBUSBZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rmk) + .value("VPSUBUSBZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rmkz) + .value("VPSUBUSBZ128rr", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rr) + .value("VPSUBUSBZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rrk) + .value("VPSUBUSBZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZ128rrkz) + .value("VPSUBUSBZ256rm", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rm) + .value("VPSUBUSBZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rmk) + .value("VPSUBUSBZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rmkz) + .value("VPSUBUSBZ256rr", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rr) + .value("VPSUBUSBZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rrk) + .value("VPSUBUSBZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZ256rrkz) + .value("VPSUBUSBZrm", LIEF::assembly::x86::OPCODE::VPSUBUSBZrm) + .value("VPSUBUSBZrmk", LIEF::assembly::x86::OPCODE::VPSUBUSBZrmk) + .value("VPSUBUSBZrmkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZrmkz) + .value("VPSUBUSBZrr", LIEF::assembly::x86::OPCODE::VPSUBUSBZrr) + .value("VPSUBUSBZrrk", LIEF::assembly::x86::OPCODE::VPSUBUSBZrrk) + .value("VPSUBUSBZrrkz", LIEF::assembly::x86::OPCODE::VPSUBUSBZrrkz) + .value("VPSUBUSBrm", LIEF::assembly::x86::OPCODE::VPSUBUSBrm) + .value("VPSUBUSBrr", LIEF::assembly::x86::OPCODE::VPSUBUSBrr) + .value("VPSUBUSWYrm", LIEF::assembly::x86::OPCODE::VPSUBUSWYrm) + .value("VPSUBUSWYrr", LIEF::assembly::x86::OPCODE::VPSUBUSWYrr) + .value("VPSUBUSWZ128rm", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rm) + .value("VPSUBUSWZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rmk) + .value("VPSUBUSWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rmkz) + .value("VPSUBUSWZ128rr", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rr) + .value("VPSUBUSWZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rrk) + .value("VPSUBUSWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZ128rrkz) + .value("VPSUBUSWZ256rm", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rm) + .value("VPSUBUSWZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rmk) + .value("VPSUBUSWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rmkz) + .value("VPSUBUSWZ256rr", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rr) + .value("VPSUBUSWZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rrk) + .value("VPSUBUSWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZ256rrkz) + .value("VPSUBUSWZrm", LIEF::assembly::x86::OPCODE::VPSUBUSWZrm) + .value("VPSUBUSWZrmk", LIEF::assembly::x86::OPCODE::VPSUBUSWZrmk) + .value("VPSUBUSWZrmkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZrmkz) + .value("VPSUBUSWZrr", LIEF::assembly::x86::OPCODE::VPSUBUSWZrr) + .value("VPSUBUSWZrrk", LIEF::assembly::x86::OPCODE::VPSUBUSWZrrk) + .value("VPSUBUSWZrrkz", LIEF::assembly::x86::OPCODE::VPSUBUSWZrrkz) + .value("VPSUBUSWrm", LIEF::assembly::x86::OPCODE::VPSUBUSWrm) + .value("VPSUBUSWrr", LIEF::assembly::x86::OPCODE::VPSUBUSWrr) + .value("VPSUBWYrm", LIEF::assembly::x86::OPCODE::VPSUBWYrm) + .value("VPSUBWYrr", LIEF::assembly::x86::OPCODE::VPSUBWYrr) + .value("VPSUBWZ128rm", LIEF::assembly::x86::OPCODE::VPSUBWZ128rm) + .value("VPSUBWZ128rmk", LIEF::assembly::x86::OPCODE::VPSUBWZ128rmk) + .value("VPSUBWZ128rmkz", LIEF::assembly::x86::OPCODE::VPSUBWZ128rmkz) + .value("VPSUBWZ128rr", LIEF::assembly::x86::OPCODE::VPSUBWZ128rr) + .value("VPSUBWZ128rrk", LIEF::assembly::x86::OPCODE::VPSUBWZ128rrk) + .value("VPSUBWZ128rrkz", LIEF::assembly::x86::OPCODE::VPSUBWZ128rrkz) + .value("VPSUBWZ256rm", LIEF::assembly::x86::OPCODE::VPSUBWZ256rm) + .value("VPSUBWZ256rmk", LIEF::assembly::x86::OPCODE::VPSUBWZ256rmk) + .value("VPSUBWZ256rmkz", LIEF::assembly::x86::OPCODE::VPSUBWZ256rmkz) + .value("VPSUBWZ256rr", LIEF::assembly::x86::OPCODE::VPSUBWZ256rr) + .value("VPSUBWZ256rrk", LIEF::assembly::x86::OPCODE::VPSUBWZ256rrk) + .value("VPSUBWZ256rrkz", LIEF::assembly::x86::OPCODE::VPSUBWZ256rrkz) + .value("VPSUBWZrm", LIEF::assembly::x86::OPCODE::VPSUBWZrm) + .value("VPSUBWZrmk", LIEF::assembly::x86::OPCODE::VPSUBWZrmk) + .value("VPSUBWZrmkz", LIEF::assembly::x86::OPCODE::VPSUBWZrmkz) + .value("VPSUBWZrr", LIEF::assembly::x86::OPCODE::VPSUBWZrr) + .value("VPSUBWZrrk", LIEF::assembly::x86::OPCODE::VPSUBWZrrk) + .value("VPSUBWZrrkz", LIEF::assembly::x86::OPCODE::VPSUBWZrrkz) + .value("VPSUBWrm", LIEF::assembly::x86::OPCODE::VPSUBWrm) + .value("VPSUBWrr", LIEF::assembly::x86::OPCODE::VPSUBWrr) + .value("VPTERNLOGDZ128rmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmbi) + .value("VPTERNLOGDZ128rmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmbik) + .value("VPTERNLOGDZ128rmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmbikz) + .value("VPTERNLOGDZ128rmi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmi) + .value("VPTERNLOGDZ128rmik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmik) + .value("VPTERNLOGDZ128rmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rmikz) + .value("VPTERNLOGDZ128rri", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rri) + .value("VPTERNLOGDZ128rrik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rrik) + .value("VPTERNLOGDZ128rrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ128rrikz) + .value("VPTERNLOGDZ256rmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmbi) + .value("VPTERNLOGDZ256rmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmbik) + .value("VPTERNLOGDZ256rmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmbikz) + .value("VPTERNLOGDZ256rmi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmi) + .value("VPTERNLOGDZ256rmik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmik) + .value("VPTERNLOGDZ256rmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rmikz) + .value("VPTERNLOGDZ256rri", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rri) + .value("VPTERNLOGDZ256rrik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rrik) + .value("VPTERNLOGDZ256rrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZ256rrikz) + .value("VPTERNLOGDZrmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmbi) + .value("VPTERNLOGDZrmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmbik) + .value("VPTERNLOGDZrmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmbikz) + .value("VPTERNLOGDZrmi", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmi) + .value("VPTERNLOGDZrmik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmik) + .value("VPTERNLOGDZrmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrmikz) + .value("VPTERNLOGDZrri", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrri) + .value("VPTERNLOGDZrrik", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrrik) + .value("VPTERNLOGDZrrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGDZrrikz) + .value("VPTERNLOGQZ128rmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmbi) + .value("VPTERNLOGQZ128rmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmbik) + .value("VPTERNLOGQZ128rmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmbikz) + .value("VPTERNLOGQZ128rmi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmi) + .value("VPTERNLOGQZ128rmik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmik) + .value("VPTERNLOGQZ128rmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rmikz) + .value("VPTERNLOGQZ128rri", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rri) + .value("VPTERNLOGQZ128rrik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rrik) + .value("VPTERNLOGQZ128rrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ128rrikz) + .value("VPTERNLOGQZ256rmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmbi) + .value("VPTERNLOGQZ256rmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmbik) + .value("VPTERNLOGQZ256rmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmbikz) + .value("VPTERNLOGQZ256rmi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmi) + .value("VPTERNLOGQZ256rmik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmik) + .value("VPTERNLOGQZ256rmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rmikz) + .value("VPTERNLOGQZ256rri", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rri) + .value("VPTERNLOGQZ256rrik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rrik) + .value("VPTERNLOGQZ256rrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZ256rrikz) + .value("VPTERNLOGQZrmbi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmbi) + .value("VPTERNLOGQZrmbik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmbik) + .value("VPTERNLOGQZrmbikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmbikz) + .value("VPTERNLOGQZrmi", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmi) + .value("VPTERNLOGQZrmik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmik) + .value("VPTERNLOGQZrmikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrmikz) + .value("VPTERNLOGQZrri", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrri) + .value("VPTERNLOGQZrrik", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrrik) + .value("VPTERNLOGQZrrikz", LIEF::assembly::x86::OPCODE::VPTERNLOGQZrrikz) + .value("VPTESTMBZ128rm", LIEF::assembly::x86::OPCODE::VPTESTMBZ128rm) + .value("VPTESTMBZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTMBZ128rmk) + .value("VPTESTMBZ128rr", LIEF::assembly::x86::OPCODE::VPTESTMBZ128rr) + .value("VPTESTMBZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTMBZ128rrk) + .value("VPTESTMBZ256rm", LIEF::assembly::x86::OPCODE::VPTESTMBZ256rm) + .value("VPTESTMBZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTMBZ256rmk) + .value("VPTESTMBZ256rr", LIEF::assembly::x86::OPCODE::VPTESTMBZ256rr) + .value("VPTESTMBZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTMBZ256rrk) + .value("VPTESTMBZrm", LIEF::assembly::x86::OPCODE::VPTESTMBZrm) + .value("VPTESTMBZrmk", LIEF::assembly::x86::OPCODE::VPTESTMBZrmk) + .value("VPTESTMBZrr", LIEF::assembly::x86::OPCODE::VPTESTMBZrr) + .value("VPTESTMBZrrk", LIEF::assembly::x86::OPCODE::VPTESTMBZrrk) + .value("VPTESTMDZ128rm", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rm) + .value("VPTESTMDZ128rmb", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rmb) + .value("VPTESTMDZ128rmbk", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rmbk) + .value("VPTESTMDZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rmk) + .value("VPTESTMDZ128rr", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rr) + .value("VPTESTMDZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTMDZ128rrk) + .value("VPTESTMDZ256rm", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rm) + .value("VPTESTMDZ256rmb", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rmb) + .value("VPTESTMDZ256rmbk", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rmbk) + .value("VPTESTMDZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rmk) + .value("VPTESTMDZ256rr", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rr) + .value("VPTESTMDZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTMDZ256rrk) + .value("VPTESTMDZrm", LIEF::assembly::x86::OPCODE::VPTESTMDZrm) + .value("VPTESTMDZrmb", LIEF::assembly::x86::OPCODE::VPTESTMDZrmb) + .value("VPTESTMDZrmbk", LIEF::assembly::x86::OPCODE::VPTESTMDZrmbk) + .value("VPTESTMDZrmk", LIEF::assembly::x86::OPCODE::VPTESTMDZrmk) + .value("VPTESTMDZrr", LIEF::assembly::x86::OPCODE::VPTESTMDZrr) + .value("VPTESTMDZrrk", LIEF::assembly::x86::OPCODE::VPTESTMDZrrk) + .value("VPTESTMQZ128rm", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rm) + .value("VPTESTMQZ128rmb", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rmb) + .value("VPTESTMQZ128rmbk", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rmbk) + .value("VPTESTMQZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rmk) + .value("VPTESTMQZ128rr", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rr) + .value("VPTESTMQZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTMQZ128rrk) + .value("VPTESTMQZ256rm", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rm) + .value("VPTESTMQZ256rmb", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rmb) + .value("VPTESTMQZ256rmbk", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rmbk) + .value("VPTESTMQZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rmk) + .value("VPTESTMQZ256rr", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rr) + .value("VPTESTMQZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTMQZ256rrk) + .value("VPTESTMQZrm", LIEF::assembly::x86::OPCODE::VPTESTMQZrm) + .value("VPTESTMQZrmb", LIEF::assembly::x86::OPCODE::VPTESTMQZrmb) + .value("VPTESTMQZrmbk", LIEF::assembly::x86::OPCODE::VPTESTMQZrmbk) + .value("VPTESTMQZrmk", LIEF::assembly::x86::OPCODE::VPTESTMQZrmk) + .value("VPTESTMQZrr", LIEF::assembly::x86::OPCODE::VPTESTMQZrr) + .value("VPTESTMQZrrk", LIEF::assembly::x86::OPCODE::VPTESTMQZrrk) + .value("VPTESTMWZ128rm", LIEF::assembly::x86::OPCODE::VPTESTMWZ128rm) + .value("VPTESTMWZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTMWZ128rmk) + .value("VPTESTMWZ128rr", LIEF::assembly::x86::OPCODE::VPTESTMWZ128rr) + .value("VPTESTMWZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTMWZ128rrk) + .value("VPTESTMWZ256rm", LIEF::assembly::x86::OPCODE::VPTESTMWZ256rm) + .value("VPTESTMWZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTMWZ256rmk) + .value("VPTESTMWZ256rr", LIEF::assembly::x86::OPCODE::VPTESTMWZ256rr) + .value("VPTESTMWZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTMWZ256rrk) + .value("VPTESTMWZrm", LIEF::assembly::x86::OPCODE::VPTESTMWZrm) + .value("VPTESTMWZrmk", LIEF::assembly::x86::OPCODE::VPTESTMWZrmk) + .value("VPTESTMWZrr", LIEF::assembly::x86::OPCODE::VPTESTMWZrr) + .value("VPTESTMWZrrk", LIEF::assembly::x86::OPCODE::VPTESTMWZrrk) + .value("VPTESTNMBZ128rm", LIEF::assembly::x86::OPCODE::VPTESTNMBZ128rm) + .value("VPTESTNMBZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTNMBZ128rmk) + .value("VPTESTNMBZ128rr", LIEF::assembly::x86::OPCODE::VPTESTNMBZ128rr) + .value("VPTESTNMBZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTNMBZ128rrk) + .value("VPTESTNMBZ256rm", LIEF::assembly::x86::OPCODE::VPTESTNMBZ256rm) + .value("VPTESTNMBZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTNMBZ256rmk) + .value("VPTESTNMBZ256rr", LIEF::assembly::x86::OPCODE::VPTESTNMBZ256rr) + .value("VPTESTNMBZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTNMBZ256rrk) + .value("VPTESTNMBZrm", LIEF::assembly::x86::OPCODE::VPTESTNMBZrm) + .value("VPTESTNMBZrmk", LIEF::assembly::x86::OPCODE::VPTESTNMBZrmk) + .value("VPTESTNMBZrr", LIEF::assembly::x86::OPCODE::VPTESTNMBZrr) + .value("VPTESTNMBZrrk", LIEF::assembly::x86::OPCODE::VPTESTNMBZrrk); + opcodes.value("VPTESTNMDZ128rm", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rm) + .value("VPTESTNMDZ128rmb", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rmb) + .value("VPTESTNMDZ128rmbk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rmbk) + .value("VPTESTNMDZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rmk) + .value("VPTESTNMDZ128rr", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rr) + .value("VPTESTNMDZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ128rrk) + .value("VPTESTNMDZ256rm", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rm) + .value("VPTESTNMDZ256rmb", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rmb) + .value("VPTESTNMDZ256rmbk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rmbk) + .value("VPTESTNMDZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rmk) + .value("VPTESTNMDZ256rr", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rr) + .value("VPTESTNMDZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTNMDZ256rrk) + .value("VPTESTNMDZrm", LIEF::assembly::x86::OPCODE::VPTESTNMDZrm) + .value("VPTESTNMDZrmb", LIEF::assembly::x86::OPCODE::VPTESTNMDZrmb) + .value("VPTESTNMDZrmbk", LIEF::assembly::x86::OPCODE::VPTESTNMDZrmbk) + .value("VPTESTNMDZrmk", LIEF::assembly::x86::OPCODE::VPTESTNMDZrmk) + .value("VPTESTNMDZrr", LIEF::assembly::x86::OPCODE::VPTESTNMDZrr) + .value("VPTESTNMDZrrk", LIEF::assembly::x86::OPCODE::VPTESTNMDZrrk) + .value("VPTESTNMQZ128rm", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rm) + .value("VPTESTNMQZ128rmb", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rmb) + .value("VPTESTNMQZ128rmbk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rmbk) + .value("VPTESTNMQZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rmk) + .value("VPTESTNMQZ128rr", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rr) + .value("VPTESTNMQZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ128rrk) + .value("VPTESTNMQZ256rm", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rm) + .value("VPTESTNMQZ256rmb", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rmb) + .value("VPTESTNMQZ256rmbk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rmbk) + .value("VPTESTNMQZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rmk) + .value("VPTESTNMQZ256rr", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rr) + .value("VPTESTNMQZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTNMQZ256rrk) + .value("VPTESTNMQZrm", LIEF::assembly::x86::OPCODE::VPTESTNMQZrm) + .value("VPTESTNMQZrmb", LIEF::assembly::x86::OPCODE::VPTESTNMQZrmb) + .value("VPTESTNMQZrmbk", LIEF::assembly::x86::OPCODE::VPTESTNMQZrmbk) + .value("VPTESTNMQZrmk", LIEF::assembly::x86::OPCODE::VPTESTNMQZrmk) + .value("VPTESTNMQZrr", LIEF::assembly::x86::OPCODE::VPTESTNMQZrr) + .value("VPTESTNMQZrrk", LIEF::assembly::x86::OPCODE::VPTESTNMQZrrk) + .value("VPTESTNMWZ128rm", LIEF::assembly::x86::OPCODE::VPTESTNMWZ128rm) + .value("VPTESTNMWZ128rmk", LIEF::assembly::x86::OPCODE::VPTESTNMWZ128rmk) + .value("VPTESTNMWZ128rr", LIEF::assembly::x86::OPCODE::VPTESTNMWZ128rr) + .value("VPTESTNMWZ128rrk", LIEF::assembly::x86::OPCODE::VPTESTNMWZ128rrk) + .value("VPTESTNMWZ256rm", LIEF::assembly::x86::OPCODE::VPTESTNMWZ256rm) + .value("VPTESTNMWZ256rmk", LIEF::assembly::x86::OPCODE::VPTESTNMWZ256rmk) + .value("VPTESTNMWZ256rr", LIEF::assembly::x86::OPCODE::VPTESTNMWZ256rr) + .value("VPTESTNMWZ256rrk", LIEF::assembly::x86::OPCODE::VPTESTNMWZ256rrk) + .value("VPTESTNMWZrm", LIEF::assembly::x86::OPCODE::VPTESTNMWZrm) + .value("VPTESTNMWZrmk", LIEF::assembly::x86::OPCODE::VPTESTNMWZrmk) + .value("VPTESTNMWZrr", LIEF::assembly::x86::OPCODE::VPTESTNMWZrr) + .value("VPTESTNMWZrrk", LIEF::assembly::x86::OPCODE::VPTESTNMWZrrk) + .value("VPTESTYrm", LIEF::assembly::x86::OPCODE::VPTESTYrm) + .value("VPTESTYrr", LIEF::assembly::x86::OPCODE::VPTESTYrr) + .value("VPTESTrm", LIEF::assembly::x86::OPCODE::VPTESTrm) + .value("VPTESTrr", LIEF::assembly::x86::OPCODE::VPTESTrr) + .value("VPUNPCKHBWYrm", LIEF::assembly::x86::OPCODE::VPUNPCKHBWYrm) + .value("VPUNPCKHBWYrr", LIEF::assembly::x86::OPCODE::VPUNPCKHBWYrr) + .value("VPUNPCKHBWZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rm) + .value("VPUNPCKHBWZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rmk) + .value("VPUNPCKHBWZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rmkz) + .value("VPUNPCKHBWZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rr) + .value("VPUNPCKHBWZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rrk) + .value("VPUNPCKHBWZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ128rrkz) + .value("VPUNPCKHBWZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rm) + .value("VPUNPCKHBWZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rmk) + .value("VPUNPCKHBWZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rmkz) + .value("VPUNPCKHBWZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rr) + .value("VPUNPCKHBWZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rrk) + .value("VPUNPCKHBWZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZ256rrkz) + .value("VPUNPCKHBWZrm", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrm) + .value("VPUNPCKHBWZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrmk) + .value("VPUNPCKHBWZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrmkz) + .value("VPUNPCKHBWZrr", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrr) + .value("VPUNPCKHBWZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrrk) + .value("VPUNPCKHBWZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHBWZrrkz) + .value("VPUNPCKHBWrm", LIEF::assembly::x86::OPCODE::VPUNPCKHBWrm) + .value("VPUNPCKHBWrr", LIEF::assembly::x86::OPCODE::VPUNPCKHBWrr) + .value("VPUNPCKHDQYrm", LIEF::assembly::x86::OPCODE::VPUNPCKHDQYrm) + .value("VPUNPCKHDQYrr", LIEF::assembly::x86::OPCODE::VPUNPCKHDQYrr) + .value("VPUNPCKHDQZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rm) + .value("VPUNPCKHDQZ128rmb", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rmb) + .value("VPUNPCKHDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rmbk) + .value("VPUNPCKHDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rmbkz) + .value("VPUNPCKHDQZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rmk) + .value("VPUNPCKHDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rmkz) + .value("VPUNPCKHDQZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rr) + .value("VPUNPCKHDQZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rrk) + .value("VPUNPCKHDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ128rrkz) + .value("VPUNPCKHDQZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rm) + .value("VPUNPCKHDQZ256rmb", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rmb) + .value("VPUNPCKHDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rmbk) + .value("VPUNPCKHDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rmbkz) + .value("VPUNPCKHDQZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rmk) + .value("VPUNPCKHDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rmkz) + .value("VPUNPCKHDQZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rr) + .value("VPUNPCKHDQZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rrk) + .value("VPUNPCKHDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZ256rrkz) + .value("VPUNPCKHDQZrm", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrm) + .value("VPUNPCKHDQZrmb", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrmb) + .value("VPUNPCKHDQZrmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrmbk) + .value("VPUNPCKHDQZrmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrmbkz) + .value("VPUNPCKHDQZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrmk) + .value("VPUNPCKHDQZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrmkz) + .value("VPUNPCKHDQZrr", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrr) + .value("VPUNPCKHDQZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrrk) + .value("VPUNPCKHDQZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHDQZrrkz) + .value("VPUNPCKHDQrm", LIEF::assembly::x86::OPCODE::VPUNPCKHDQrm) + .value("VPUNPCKHDQrr", LIEF::assembly::x86::OPCODE::VPUNPCKHDQrr) + .value("VPUNPCKHQDQYrm", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQYrm) + .value("VPUNPCKHQDQYrr", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQYrr) + .value("VPUNPCKHQDQZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rm) + .value("VPUNPCKHQDQZ128rmb", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rmb) + .value("VPUNPCKHQDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rmbk) + .value("VPUNPCKHQDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rmbkz) + .value("VPUNPCKHQDQZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rmk) + .value("VPUNPCKHQDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rmkz) + .value("VPUNPCKHQDQZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rr) + .value("VPUNPCKHQDQZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rrk) + .value("VPUNPCKHQDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ128rrkz) + .value("VPUNPCKHQDQZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rm) + .value("VPUNPCKHQDQZ256rmb", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rmb) + .value("VPUNPCKHQDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rmbk) + .value("VPUNPCKHQDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rmbkz) + .value("VPUNPCKHQDQZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rmk) + .value("VPUNPCKHQDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rmkz) + .value("VPUNPCKHQDQZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rr) + .value("VPUNPCKHQDQZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rrk) + .value("VPUNPCKHQDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZ256rrkz) + .value("VPUNPCKHQDQZrm", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrm) + .value("VPUNPCKHQDQZrmb", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrmb) + .value("VPUNPCKHQDQZrmbk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrmbk) + .value("VPUNPCKHQDQZrmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrmbkz) + .value("VPUNPCKHQDQZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrmk) + .value("VPUNPCKHQDQZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrmkz) + .value("VPUNPCKHQDQZrr", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrr) + .value("VPUNPCKHQDQZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrrk) + .value("VPUNPCKHQDQZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQZrrkz) + .value("VPUNPCKHQDQrm", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQrm) + .value("VPUNPCKHQDQrr", LIEF::assembly::x86::OPCODE::VPUNPCKHQDQrr) + .value("VPUNPCKHWDYrm", LIEF::assembly::x86::OPCODE::VPUNPCKHWDYrm) + .value("VPUNPCKHWDYrr", LIEF::assembly::x86::OPCODE::VPUNPCKHWDYrr) + .value("VPUNPCKHWDZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rm) + .value("VPUNPCKHWDZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rmk) + .value("VPUNPCKHWDZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rmkz) + .value("VPUNPCKHWDZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rr) + .value("VPUNPCKHWDZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rrk) + .value("VPUNPCKHWDZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ128rrkz) + .value("VPUNPCKHWDZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rm) + .value("VPUNPCKHWDZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rmk) + .value("VPUNPCKHWDZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rmkz) + .value("VPUNPCKHWDZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rr) + .value("VPUNPCKHWDZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rrk) + .value("VPUNPCKHWDZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZ256rrkz) + .value("VPUNPCKHWDZrm", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrm) + .value("VPUNPCKHWDZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrmk) + .value("VPUNPCKHWDZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrmkz) + .value("VPUNPCKHWDZrr", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrr) + .value("VPUNPCKHWDZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrrk) + .value("VPUNPCKHWDZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKHWDZrrkz) + .value("VPUNPCKHWDrm", LIEF::assembly::x86::OPCODE::VPUNPCKHWDrm) + .value("VPUNPCKHWDrr", LIEF::assembly::x86::OPCODE::VPUNPCKHWDrr) + .value("VPUNPCKLBWYrm", LIEF::assembly::x86::OPCODE::VPUNPCKLBWYrm) + .value("VPUNPCKLBWYrr", LIEF::assembly::x86::OPCODE::VPUNPCKLBWYrr) + .value("VPUNPCKLBWZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rm) + .value("VPUNPCKLBWZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rmk) + .value("VPUNPCKLBWZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rmkz) + .value("VPUNPCKLBWZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rr) + .value("VPUNPCKLBWZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rrk) + .value("VPUNPCKLBWZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ128rrkz) + .value("VPUNPCKLBWZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rm) + .value("VPUNPCKLBWZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rmk) + .value("VPUNPCKLBWZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rmkz) + .value("VPUNPCKLBWZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rr) + .value("VPUNPCKLBWZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rrk) + .value("VPUNPCKLBWZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZ256rrkz) + .value("VPUNPCKLBWZrm", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrm) + .value("VPUNPCKLBWZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrmk) + .value("VPUNPCKLBWZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrmkz) + .value("VPUNPCKLBWZrr", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrr) + .value("VPUNPCKLBWZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrrk) + .value("VPUNPCKLBWZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLBWZrrkz) + .value("VPUNPCKLBWrm", LIEF::assembly::x86::OPCODE::VPUNPCKLBWrm) + .value("VPUNPCKLBWrr", LIEF::assembly::x86::OPCODE::VPUNPCKLBWrr) + .value("VPUNPCKLDQYrm", LIEF::assembly::x86::OPCODE::VPUNPCKLDQYrm) + .value("VPUNPCKLDQYrr", LIEF::assembly::x86::OPCODE::VPUNPCKLDQYrr) + .value("VPUNPCKLDQZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rm) + .value("VPUNPCKLDQZ128rmb", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rmb) + .value("VPUNPCKLDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rmbk) + .value("VPUNPCKLDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rmbkz) + .value("VPUNPCKLDQZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rmk) + .value("VPUNPCKLDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rmkz) + .value("VPUNPCKLDQZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rr) + .value("VPUNPCKLDQZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rrk) + .value("VPUNPCKLDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ128rrkz) + .value("VPUNPCKLDQZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rm) + .value("VPUNPCKLDQZ256rmb", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rmb) + .value("VPUNPCKLDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rmbk) + .value("VPUNPCKLDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rmbkz) + .value("VPUNPCKLDQZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rmk) + .value("VPUNPCKLDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rmkz) + .value("VPUNPCKLDQZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rr) + .value("VPUNPCKLDQZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rrk) + .value("VPUNPCKLDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZ256rrkz) + .value("VPUNPCKLDQZrm", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrm) + .value("VPUNPCKLDQZrmb", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrmb) + .value("VPUNPCKLDQZrmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrmbk) + .value("VPUNPCKLDQZrmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrmbkz) + .value("VPUNPCKLDQZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrmk) + .value("VPUNPCKLDQZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrmkz) + .value("VPUNPCKLDQZrr", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrr) + .value("VPUNPCKLDQZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrrk) + .value("VPUNPCKLDQZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLDQZrrkz) + .value("VPUNPCKLDQrm", LIEF::assembly::x86::OPCODE::VPUNPCKLDQrm) + .value("VPUNPCKLDQrr", LIEF::assembly::x86::OPCODE::VPUNPCKLDQrr) + .value("VPUNPCKLQDQYrm", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQYrm) + .value("VPUNPCKLQDQYrr", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQYrr) + .value("VPUNPCKLQDQZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rm) + .value("VPUNPCKLQDQZ128rmb", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rmb) + .value("VPUNPCKLQDQZ128rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rmbk) + .value("VPUNPCKLQDQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rmbkz) + .value("VPUNPCKLQDQZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rmk) + .value("VPUNPCKLQDQZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rmkz) + .value("VPUNPCKLQDQZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rr) + .value("VPUNPCKLQDQZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rrk) + .value("VPUNPCKLQDQZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ128rrkz) + .value("VPUNPCKLQDQZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rm) + .value("VPUNPCKLQDQZ256rmb", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rmb) + .value("VPUNPCKLQDQZ256rmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rmbk) + .value("VPUNPCKLQDQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rmbkz) + .value("VPUNPCKLQDQZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rmk) + .value("VPUNPCKLQDQZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rmkz) + .value("VPUNPCKLQDQZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rr) + .value("VPUNPCKLQDQZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rrk) + .value("VPUNPCKLQDQZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZ256rrkz) + .value("VPUNPCKLQDQZrm", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrm) + .value("VPUNPCKLQDQZrmb", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrmb) + .value("VPUNPCKLQDQZrmbk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrmbk) + .value("VPUNPCKLQDQZrmbkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrmbkz) + .value("VPUNPCKLQDQZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrmk) + .value("VPUNPCKLQDQZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrmkz) + .value("VPUNPCKLQDQZrr", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrr) + .value("VPUNPCKLQDQZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrrk) + .value("VPUNPCKLQDQZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQZrrkz) + .value("VPUNPCKLQDQrm", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQrm) + .value("VPUNPCKLQDQrr", LIEF::assembly::x86::OPCODE::VPUNPCKLQDQrr) + .value("VPUNPCKLWDYrm", LIEF::assembly::x86::OPCODE::VPUNPCKLWDYrm) + .value("VPUNPCKLWDYrr", LIEF::assembly::x86::OPCODE::VPUNPCKLWDYrr) + .value("VPUNPCKLWDZ128rm", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rm) + .value("VPUNPCKLWDZ128rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rmk) + .value("VPUNPCKLWDZ128rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rmkz) + .value("VPUNPCKLWDZ128rr", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rr) + .value("VPUNPCKLWDZ128rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rrk) + .value("VPUNPCKLWDZ128rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ128rrkz) + .value("VPUNPCKLWDZ256rm", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rm) + .value("VPUNPCKLWDZ256rmk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rmk) + .value("VPUNPCKLWDZ256rmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rmkz) + .value("VPUNPCKLWDZ256rr", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rr) + .value("VPUNPCKLWDZ256rrk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rrk) + .value("VPUNPCKLWDZ256rrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZ256rrkz) + .value("VPUNPCKLWDZrm", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrm) + .value("VPUNPCKLWDZrmk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrmk) + .value("VPUNPCKLWDZrmkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrmkz) + .value("VPUNPCKLWDZrr", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrr) + .value("VPUNPCKLWDZrrk", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrrk) + .value("VPUNPCKLWDZrrkz", LIEF::assembly::x86::OPCODE::VPUNPCKLWDZrrkz) + .value("VPUNPCKLWDrm", LIEF::assembly::x86::OPCODE::VPUNPCKLWDrm) + .value("VPUNPCKLWDrr", LIEF::assembly::x86::OPCODE::VPUNPCKLWDrr) + .value("VPXORDZ128rm", LIEF::assembly::x86::OPCODE::VPXORDZ128rm) + .value("VPXORDZ128rmb", LIEF::assembly::x86::OPCODE::VPXORDZ128rmb) + .value("VPXORDZ128rmbk", LIEF::assembly::x86::OPCODE::VPXORDZ128rmbk) + .value("VPXORDZ128rmbkz", LIEF::assembly::x86::OPCODE::VPXORDZ128rmbkz) + .value("VPXORDZ128rmk", LIEF::assembly::x86::OPCODE::VPXORDZ128rmk) + .value("VPXORDZ128rmkz", LIEF::assembly::x86::OPCODE::VPXORDZ128rmkz) + .value("VPXORDZ128rr", LIEF::assembly::x86::OPCODE::VPXORDZ128rr) + .value("VPXORDZ128rrk", LIEF::assembly::x86::OPCODE::VPXORDZ128rrk) + .value("VPXORDZ128rrkz", LIEF::assembly::x86::OPCODE::VPXORDZ128rrkz) + .value("VPXORDZ256rm", LIEF::assembly::x86::OPCODE::VPXORDZ256rm) + .value("VPXORDZ256rmb", LIEF::assembly::x86::OPCODE::VPXORDZ256rmb) + .value("VPXORDZ256rmbk", LIEF::assembly::x86::OPCODE::VPXORDZ256rmbk) + .value("VPXORDZ256rmbkz", LIEF::assembly::x86::OPCODE::VPXORDZ256rmbkz) + .value("VPXORDZ256rmk", LIEF::assembly::x86::OPCODE::VPXORDZ256rmk) + .value("VPXORDZ256rmkz", LIEF::assembly::x86::OPCODE::VPXORDZ256rmkz) + .value("VPXORDZ256rr", LIEF::assembly::x86::OPCODE::VPXORDZ256rr) + .value("VPXORDZ256rrk", LIEF::assembly::x86::OPCODE::VPXORDZ256rrk) + .value("VPXORDZ256rrkz", LIEF::assembly::x86::OPCODE::VPXORDZ256rrkz) + .value("VPXORDZrm", LIEF::assembly::x86::OPCODE::VPXORDZrm) + .value("VPXORDZrmb", LIEF::assembly::x86::OPCODE::VPXORDZrmb) + .value("VPXORDZrmbk", LIEF::assembly::x86::OPCODE::VPXORDZrmbk) + .value("VPXORDZrmbkz", LIEF::assembly::x86::OPCODE::VPXORDZrmbkz) + .value("VPXORDZrmk", LIEF::assembly::x86::OPCODE::VPXORDZrmk) + .value("VPXORDZrmkz", LIEF::assembly::x86::OPCODE::VPXORDZrmkz) + .value("VPXORDZrr", LIEF::assembly::x86::OPCODE::VPXORDZrr) + .value("VPXORDZrrk", LIEF::assembly::x86::OPCODE::VPXORDZrrk) + .value("VPXORDZrrkz", LIEF::assembly::x86::OPCODE::VPXORDZrrkz) + .value("VPXORQZ128rm", LIEF::assembly::x86::OPCODE::VPXORQZ128rm) + .value("VPXORQZ128rmb", LIEF::assembly::x86::OPCODE::VPXORQZ128rmb) + .value("VPXORQZ128rmbk", LIEF::assembly::x86::OPCODE::VPXORQZ128rmbk) + .value("VPXORQZ128rmbkz", LIEF::assembly::x86::OPCODE::VPXORQZ128rmbkz) + .value("VPXORQZ128rmk", LIEF::assembly::x86::OPCODE::VPXORQZ128rmk) + .value("VPXORQZ128rmkz", LIEF::assembly::x86::OPCODE::VPXORQZ128rmkz) + .value("VPXORQZ128rr", LIEF::assembly::x86::OPCODE::VPXORQZ128rr) + .value("VPXORQZ128rrk", LIEF::assembly::x86::OPCODE::VPXORQZ128rrk) + .value("VPXORQZ128rrkz", LIEF::assembly::x86::OPCODE::VPXORQZ128rrkz); + opcodes.value("VPXORQZ256rm", LIEF::assembly::x86::OPCODE::VPXORQZ256rm) + .value("VPXORQZ256rmb", LIEF::assembly::x86::OPCODE::VPXORQZ256rmb) + .value("VPXORQZ256rmbk", LIEF::assembly::x86::OPCODE::VPXORQZ256rmbk) + .value("VPXORQZ256rmbkz", LIEF::assembly::x86::OPCODE::VPXORQZ256rmbkz) + .value("VPXORQZ256rmk", LIEF::assembly::x86::OPCODE::VPXORQZ256rmk) + .value("VPXORQZ256rmkz", LIEF::assembly::x86::OPCODE::VPXORQZ256rmkz) + .value("VPXORQZ256rr", LIEF::assembly::x86::OPCODE::VPXORQZ256rr) + .value("VPXORQZ256rrk", LIEF::assembly::x86::OPCODE::VPXORQZ256rrk) + .value("VPXORQZ256rrkz", LIEF::assembly::x86::OPCODE::VPXORQZ256rrkz) + .value("VPXORQZrm", LIEF::assembly::x86::OPCODE::VPXORQZrm) + .value("VPXORQZrmb", LIEF::assembly::x86::OPCODE::VPXORQZrmb) + .value("VPXORQZrmbk", LIEF::assembly::x86::OPCODE::VPXORQZrmbk) + .value("VPXORQZrmbkz", LIEF::assembly::x86::OPCODE::VPXORQZrmbkz) + .value("VPXORQZrmk", LIEF::assembly::x86::OPCODE::VPXORQZrmk) + .value("VPXORQZrmkz", LIEF::assembly::x86::OPCODE::VPXORQZrmkz) + .value("VPXORQZrr", LIEF::assembly::x86::OPCODE::VPXORQZrr) + .value("VPXORQZrrk", LIEF::assembly::x86::OPCODE::VPXORQZrrk) + .value("VPXORQZrrkz", LIEF::assembly::x86::OPCODE::VPXORQZrrkz) + .value("VPXORYrm", LIEF::assembly::x86::OPCODE::VPXORYrm) + .value("VPXORYrr", LIEF::assembly::x86::OPCODE::VPXORYrr) + .value("VPXORrm", LIEF::assembly::x86::OPCODE::VPXORrm) + .value("VPXORrr", LIEF::assembly::x86::OPCODE::VPXORrr) + .value("VRANGEPDZ128rmbi", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmbi) + .value("VRANGEPDZ128rmbik", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmbik) + .value("VRANGEPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmbikz) + .value("VRANGEPDZ128rmi", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmi) + .value("VRANGEPDZ128rmik", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmik) + .value("VRANGEPDZ128rmikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rmikz) + .value("VRANGEPDZ128rri", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rri) + .value("VRANGEPDZ128rrik", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rrik) + .value("VRANGEPDZ128rrikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ128rrikz) + .value("VRANGEPDZ256rmbi", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmbi) + .value("VRANGEPDZ256rmbik", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmbik) + .value("VRANGEPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmbikz) + .value("VRANGEPDZ256rmi", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmi) + .value("VRANGEPDZ256rmik", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmik) + .value("VRANGEPDZ256rmikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rmikz) + .value("VRANGEPDZ256rri", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rri) + .value("VRANGEPDZ256rrik", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rrik) + .value("VRANGEPDZ256rrikz", LIEF::assembly::x86::OPCODE::VRANGEPDZ256rrikz) + .value("VRANGEPDZrmbi", LIEF::assembly::x86::OPCODE::VRANGEPDZrmbi) + .value("VRANGEPDZrmbik", LIEF::assembly::x86::OPCODE::VRANGEPDZrmbik) + .value("VRANGEPDZrmbikz", LIEF::assembly::x86::OPCODE::VRANGEPDZrmbikz) + .value("VRANGEPDZrmi", LIEF::assembly::x86::OPCODE::VRANGEPDZrmi) + .value("VRANGEPDZrmik", LIEF::assembly::x86::OPCODE::VRANGEPDZrmik) + .value("VRANGEPDZrmikz", LIEF::assembly::x86::OPCODE::VRANGEPDZrmikz) + .value("VRANGEPDZrri", LIEF::assembly::x86::OPCODE::VRANGEPDZrri) + .value("VRANGEPDZrrib", LIEF::assembly::x86::OPCODE::VRANGEPDZrrib) + .value("VRANGEPDZrribk", LIEF::assembly::x86::OPCODE::VRANGEPDZrribk) + .value("VRANGEPDZrribkz", LIEF::assembly::x86::OPCODE::VRANGEPDZrribkz) + .value("VRANGEPDZrrik", LIEF::assembly::x86::OPCODE::VRANGEPDZrrik) + .value("VRANGEPDZrrikz", LIEF::assembly::x86::OPCODE::VRANGEPDZrrikz) + .value("VRANGEPSZ128rmbi", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmbi) + .value("VRANGEPSZ128rmbik", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmbik) + .value("VRANGEPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmbikz) + .value("VRANGEPSZ128rmi", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmi) + .value("VRANGEPSZ128rmik", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmik) + .value("VRANGEPSZ128rmikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rmikz) + .value("VRANGEPSZ128rri", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rri) + .value("VRANGEPSZ128rrik", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rrik) + .value("VRANGEPSZ128rrikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ128rrikz) + .value("VRANGEPSZ256rmbi", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmbi) + .value("VRANGEPSZ256rmbik", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmbik) + .value("VRANGEPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmbikz) + .value("VRANGEPSZ256rmi", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmi) + .value("VRANGEPSZ256rmik", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmik) + .value("VRANGEPSZ256rmikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rmikz) + .value("VRANGEPSZ256rri", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rri) + .value("VRANGEPSZ256rrik", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rrik) + .value("VRANGEPSZ256rrikz", LIEF::assembly::x86::OPCODE::VRANGEPSZ256rrikz) + .value("VRANGEPSZrmbi", LIEF::assembly::x86::OPCODE::VRANGEPSZrmbi) + .value("VRANGEPSZrmbik", LIEF::assembly::x86::OPCODE::VRANGEPSZrmbik) + .value("VRANGEPSZrmbikz", LIEF::assembly::x86::OPCODE::VRANGEPSZrmbikz) + .value("VRANGEPSZrmi", LIEF::assembly::x86::OPCODE::VRANGEPSZrmi) + .value("VRANGEPSZrmik", LIEF::assembly::x86::OPCODE::VRANGEPSZrmik) + .value("VRANGEPSZrmikz", LIEF::assembly::x86::OPCODE::VRANGEPSZrmikz) + .value("VRANGEPSZrri", LIEF::assembly::x86::OPCODE::VRANGEPSZrri) + .value("VRANGEPSZrrib", LIEF::assembly::x86::OPCODE::VRANGEPSZrrib) + .value("VRANGEPSZrribk", LIEF::assembly::x86::OPCODE::VRANGEPSZrribk) + .value("VRANGEPSZrribkz", LIEF::assembly::x86::OPCODE::VRANGEPSZrribkz) + .value("VRANGEPSZrrik", LIEF::assembly::x86::OPCODE::VRANGEPSZrrik) + .value("VRANGEPSZrrikz", LIEF::assembly::x86::OPCODE::VRANGEPSZrrikz) + .value("VRANGESDZrmi", LIEF::assembly::x86::OPCODE::VRANGESDZrmi) + .value("VRANGESDZrmik", LIEF::assembly::x86::OPCODE::VRANGESDZrmik) + .value("VRANGESDZrmikz", LIEF::assembly::x86::OPCODE::VRANGESDZrmikz) + .value("VRANGESDZrri", LIEF::assembly::x86::OPCODE::VRANGESDZrri) + .value("VRANGESDZrrib", LIEF::assembly::x86::OPCODE::VRANGESDZrrib) + .value("VRANGESDZrribk", LIEF::assembly::x86::OPCODE::VRANGESDZrribk) + .value("VRANGESDZrribkz", LIEF::assembly::x86::OPCODE::VRANGESDZrribkz) + .value("VRANGESDZrrik", LIEF::assembly::x86::OPCODE::VRANGESDZrrik) + .value("VRANGESDZrrikz", LIEF::assembly::x86::OPCODE::VRANGESDZrrikz) + .value("VRANGESSZrmi", LIEF::assembly::x86::OPCODE::VRANGESSZrmi) + .value("VRANGESSZrmik", LIEF::assembly::x86::OPCODE::VRANGESSZrmik) + .value("VRANGESSZrmikz", LIEF::assembly::x86::OPCODE::VRANGESSZrmikz) + .value("VRANGESSZrri", LIEF::assembly::x86::OPCODE::VRANGESSZrri) + .value("VRANGESSZrrib", LIEF::assembly::x86::OPCODE::VRANGESSZrrib) + .value("VRANGESSZrribk", LIEF::assembly::x86::OPCODE::VRANGESSZrribk) + .value("VRANGESSZrribkz", LIEF::assembly::x86::OPCODE::VRANGESSZrribkz) + .value("VRANGESSZrrik", LIEF::assembly::x86::OPCODE::VRANGESSZrrik) + .value("VRANGESSZrrikz", LIEF::assembly::x86::OPCODE::VRANGESSZrrikz) + .value("VRCP14PDZ128m", LIEF::assembly::x86::OPCODE::VRCP14PDZ128m) + .value("VRCP14PDZ128mb", LIEF::assembly::x86::OPCODE::VRCP14PDZ128mb) + .value("VRCP14PDZ128mbk", LIEF::assembly::x86::OPCODE::VRCP14PDZ128mbk) + .value("VRCP14PDZ128mbkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ128mbkz) + .value("VRCP14PDZ128mk", LIEF::assembly::x86::OPCODE::VRCP14PDZ128mk) + .value("VRCP14PDZ128mkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ128mkz) + .value("VRCP14PDZ128r", LIEF::assembly::x86::OPCODE::VRCP14PDZ128r) + .value("VRCP14PDZ128rk", LIEF::assembly::x86::OPCODE::VRCP14PDZ128rk) + .value("VRCP14PDZ128rkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ128rkz) + .value("VRCP14PDZ256m", LIEF::assembly::x86::OPCODE::VRCP14PDZ256m) + .value("VRCP14PDZ256mb", LIEF::assembly::x86::OPCODE::VRCP14PDZ256mb) + .value("VRCP14PDZ256mbk", LIEF::assembly::x86::OPCODE::VRCP14PDZ256mbk) + .value("VRCP14PDZ256mbkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ256mbkz) + .value("VRCP14PDZ256mk", LIEF::assembly::x86::OPCODE::VRCP14PDZ256mk) + .value("VRCP14PDZ256mkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ256mkz) + .value("VRCP14PDZ256r", LIEF::assembly::x86::OPCODE::VRCP14PDZ256r) + .value("VRCP14PDZ256rk", LIEF::assembly::x86::OPCODE::VRCP14PDZ256rk) + .value("VRCP14PDZ256rkz", LIEF::assembly::x86::OPCODE::VRCP14PDZ256rkz) + .value("VRCP14PDZm", LIEF::assembly::x86::OPCODE::VRCP14PDZm) + .value("VRCP14PDZmb", LIEF::assembly::x86::OPCODE::VRCP14PDZmb) + .value("VRCP14PDZmbk", LIEF::assembly::x86::OPCODE::VRCP14PDZmbk) + .value("VRCP14PDZmbkz", LIEF::assembly::x86::OPCODE::VRCP14PDZmbkz) + .value("VRCP14PDZmk", LIEF::assembly::x86::OPCODE::VRCP14PDZmk) + .value("VRCP14PDZmkz", LIEF::assembly::x86::OPCODE::VRCP14PDZmkz) + .value("VRCP14PDZr", LIEF::assembly::x86::OPCODE::VRCP14PDZr) + .value("VRCP14PDZrk", LIEF::assembly::x86::OPCODE::VRCP14PDZrk) + .value("VRCP14PDZrkz", LIEF::assembly::x86::OPCODE::VRCP14PDZrkz) + .value("VRCP14PSZ128m", LIEF::assembly::x86::OPCODE::VRCP14PSZ128m) + .value("VRCP14PSZ128mb", LIEF::assembly::x86::OPCODE::VRCP14PSZ128mb) + .value("VRCP14PSZ128mbk", LIEF::assembly::x86::OPCODE::VRCP14PSZ128mbk) + .value("VRCP14PSZ128mbkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ128mbkz) + .value("VRCP14PSZ128mk", LIEF::assembly::x86::OPCODE::VRCP14PSZ128mk) + .value("VRCP14PSZ128mkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ128mkz) + .value("VRCP14PSZ128r", LIEF::assembly::x86::OPCODE::VRCP14PSZ128r) + .value("VRCP14PSZ128rk", LIEF::assembly::x86::OPCODE::VRCP14PSZ128rk) + .value("VRCP14PSZ128rkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ128rkz) + .value("VRCP14PSZ256m", LIEF::assembly::x86::OPCODE::VRCP14PSZ256m) + .value("VRCP14PSZ256mb", LIEF::assembly::x86::OPCODE::VRCP14PSZ256mb) + .value("VRCP14PSZ256mbk", LIEF::assembly::x86::OPCODE::VRCP14PSZ256mbk) + .value("VRCP14PSZ256mbkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ256mbkz) + .value("VRCP14PSZ256mk", LIEF::assembly::x86::OPCODE::VRCP14PSZ256mk) + .value("VRCP14PSZ256mkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ256mkz) + .value("VRCP14PSZ256r", LIEF::assembly::x86::OPCODE::VRCP14PSZ256r) + .value("VRCP14PSZ256rk", LIEF::assembly::x86::OPCODE::VRCP14PSZ256rk) + .value("VRCP14PSZ256rkz", LIEF::assembly::x86::OPCODE::VRCP14PSZ256rkz) + .value("VRCP14PSZm", LIEF::assembly::x86::OPCODE::VRCP14PSZm) + .value("VRCP14PSZmb", LIEF::assembly::x86::OPCODE::VRCP14PSZmb) + .value("VRCP14PSZmbk", LIEF::assembly::x86::OPCODE::VRCP14PSZmbk) + .value("VRCP14PSZmbkz", LIEF::assembly::x86::OPCODE::VRCP14PSZmbkz) + .value("VRCP14PSZmk", LIEF::assembly::x86::OPCODE::VRCP14PSZmk) + .value("VRCP14PSZmkz", LIEF::assembly::x86::OPCODE::VRCP14PSZmkz) + .value("VRCP14PSZr", LIEF::assembly::x86::OPCODE::VRCP14PSZr) + .value("VRCP14PSZrk", LIEF::assembly::x86::OPCODE::VRCP14PSZrk) + .value("VRCP14PSZrkz", LIEF::assembly::x86::OPCODE::VRCP14PSZrkz) + .value("VRCP14SDZrm", LIEF::assembly::x86::OPCODE::VRCP14SDZrm) + .value("VRCP14SDZrmk", LIEF::assembly::x86::OPCODE::VRCP14SDZrmk) + .value("VRCP14SDZrmkz", LIEF::assembly::x86::OPCODE::VRCP14SDZrmkz) + .value("VRCP14SDZrr", LIEF::assembly::x86::OPCODE::VRCP14SDZrr) + .value("VRCP14SDZrrk", LIEF::assembly::x86::OPCODE::VRCP14SDZrrk) + .value("VRCP14SDZrrkz", LIEF::assembly::x86::OPCODE::VRCP14SDZrrkz) + .value("VRCP14SSZrm", LIEF::assembly::x86::OPCODE::VRCP14SSZrm) + .value("VRCP14SSZrmk", LIEF::assembly::x86::OPCODE::VRCP14SSZrmk) + .value("VRCP14SSZrmkz", LIEF::assembly::x86::OPCODE::VRCP14SSZrmkz) + .value("VRCP14SSZrr", LIEF::assembly::x86::OPCODE::VRCP14SSZrr) + .value("VRCP14SSZrrk", LIEF::assembly::x86::OPCODE::VRCP14SSZrrk) + .value("VRCP14SSZrrkz", LIEF::assembly::x86::OPCODE::VRCP14SSZrrkz) + .value("VRCP28PDZm", LIEF::assembly::x86::OPCODE::VRCP28PDZm) + .value("VRCP28PDZmb", LIEF::assembly::x86::OPCODE::VRCP28PDZmb) + .value("VRCP28PDZmbk", LIEF::assembly::x86::OPCODE::VRCP28PDZmbk) + .value("VRCP28PDZmbkz", LIEF::assembly::x86::OPCODE::VRCP28PDZmbkz) + .value("VRCP28PDZmk", LIEF::assembly::x86::OPCODE::VRCP28PDZmk) + .value("VRCP28PDZmkz", LIEF::assembly::x86::OPCODE::VRCP28PDZmkz) + .value("VRCP28PDZr", LIEF::assembly::x86::OPCODE::VRCP28PDZr) + .value("VRCP28PDZrb", LIEF::assembly::x86::OPCODE::VRCP28PDZrb) + .value("VRCP28PDZrbk", LIEF::assembly::x86::OPCODE::VRCP28PDZrbk) + .value("VRCP28PDZrbkz", LIEF::assembly::x86::OPCODE::VRCP28PDZrbkz) + .value("VRCP28PDZrk", LIEF::assembly::x86::OPCODE::VRCP28PDZrk) + .value("VRCP28PDZrkz", LIEF::assembly::x86::OPCODE::VRCP28PDZrkz) + .value("VRCP28PSZm", LIEF::assembly::x86::OPCODE::VRCP28PSZm) + .value("VRCP28PSZmb", LIEF::assembly::x86::OPCODE::VRCP28PSZmb) + .value("VRCP28PSZmbk", LIEF::assembly::x86::OPCODE::VRCP28PSZmbk) + .value("VRCP28PSZmbkz", LIEF::assembly::x86::OPCODE::VRCP28PSZmbkz) + .value("VRCP28PSZmk", LIEF::assembly::x86::OPCODE::VRCP28PSZmk) + .value("VRCP28PSZmkz", LIEF::assembly::x86::OPCODE::VRCP28PSZmkz) + .value("VRCP28PSZr", LIEF::assembly::x86::OPCODE::VRCP28PSZr) + .value("VRCP28PSZrb", LIEF::assembly::x86::OPCODE::VRCP28PSZrb) + .value("VRCP28PSZrbk", LIEF::assembly::x86::OPCODE::VRCP28PSZrbk) + .value("VRCP28PSZrbkz", LIEF::assembly::x86::OPCODE::VRCP28PSZrbkz) + .value("VRCP28PSZrk", LIEF::assembly::x86::OPCODE::VRCP28PSZrk) + .value("VRCP28PSZrkz", LIEF::assembly::x86::OPCODE::VRCP28PSZrkz) + .value("VRCP28SDZm", LIEF::assembly::x86::OPCODE::VRCP28SDZm) + .value("VRCP28SDZmk", LIEF::assembly::x86::OPCODE::VRCP28SDZmk) + .value("VRCP28SDZmkz", LIEF::assembly::x86::OPCODE::VRCP28SDZmkz) + .value("VRCP28SDZr", LIEF::assembly::x86::OPCODE::VRCP28SDZr) + .value("VRCP28SDZrb", LIEF::assembly::x86::OPCODE::VRCP28SDZrb) + .value("VRCP28SDZrbk", LIEF::assembly::x86::OPCODE::VRCP28SDZrbk) + .value("VRCP28SDZrbkz", LIEF::assembly::x86::OPCODE::VRCP28SDZrbkz) + .value("VRCP28SDZrk", LIEF::assembly::x86::OPCODE::VRCP28SDZrk) + .value("VRCP28SDZrkz", LIEF::assembly::x86::OPCODE::VRCP28SDZrkz) + .value("VRCP28SSZm", LIEF::assembly::x86::OPCODE::VRCP28SSZm) + .value("VRCP28SSZmk", LIEF::assembly::x86::OPCODE::VRCP28SSZmk) + .value("VRCP28SSZmkz", LIEF::assembly::x86::OPCODE::VRCP28SSZmkz) + .value("VRCP28SSZr", LIEF::assembly::x86::OPCODE::VRCP28SSZr) + .value("VRCP28SSZrb", LIEF::assembly::x86::OPCODE::VRCP28SSZrb) + .value("VRCP28SSZrbk", LIEF::assembly::x86::OPCODE::VRCP28SSZrbk) + .value("VRCP28SSZrbkz", LIEF::assembly::x86::OPCODE::VRCP28SSZrbkz) + .value("VRCP28SSZrk", LIEF::assembly::x86::OPCODE::VRCP28SSZrk) + .value("VRCP28SSZrkz", LIEF::assembly::x86::OPCODE::VRCP28SSZrkz) + .value("VRCPBF16Z128m", LIEF::assembly::x86::OPCODE::VRCPBF16Z128m) + .value("VRCPBF16Z128mb", LIEF::assembly::x86::OPCODE::VRCPBF16Z128mb) + .value("VRCPBF16Z128mbk", LIEF::assembly::x86::OPCODE::VRCPBF16Z128mbk) + .value("VRCPBF16Z128mbkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z128mbkz) + .value("VRCPBF16Z128mk", LIEF::assembly::x86::OPCODE::VRCPBF16Z128mk) + .value("VRCPBF16Z128mkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z128mkz) + .value("VRCPBF16Z128r", LIEF::assembly::x86::OPCODE::VRCPBF16Z128r) + .value("VRCPBF16Z128rk", LIEF::assembly::x86::OPCODE::VRCPBF16Z128rk) + .value("VRCPBF16Z128rkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z128rkz) + .value("VRCPBF16Z256m", LIEF::assembly::x86::OPCODE::VRCPBF16Z256m) + .value("VRCPBF16Z256mb", LIEF::assembly::x86::OPCODE::VRCPBF16Z256mb) + .value("VRCPBF16Z256mbk", LIEF::assembly::x86::OPCODE::VRCPBF16Z256mbk) + .value("VRCPBF16Z256mbkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z256mbkz) + .value("VRCPBF16Z256mk", LIEF::assembly::x86::OPCODE::VRCPBF16Z256mk) + .value("VRCPBF16Z256mkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z256mkz) + .value("VRCPBF16Z256r", LIEF::assembly::x86::OPCODE::VRCPBF16Z256r) + .value("VRCPBF16Z256rk", LIEF::assembly::x86::OPCODE::VRCPBF16Z256rk) + .value("VRCPBF16Z256rkz", LIEF::assembly::x86::OPCODE::VRCPBF16Z256rkz) + .value("VRCPBF16Zm", LIEF::assembly::x86::OPCODE::VRCPBF16Zm) + .value("VRCPBF16Zmb", LIEF::assembly::x86::OPCODE::VRCPBF16Zmb) + .value("VRCPBF16Zmbk", LIEF::assembly::x86::OPCODE::VRCPBF16Zmbk) + .value("VRCPBF16Zmbkz", LIEF::assembly::x86::OPCODE::VRCPBF16Zmbkz) + .value("VRCPBF16Zmk", LIEF::assembly::x86::OPCODE::VRCPBF16Zmk) + .value("VRCPBF16Zmkz", LIEF::assembly::x86::OPCODE::VRCPBF16Zmkz) + .value("VRCPBF16Zr", LIEF::assembly::x86::OPCODE::VRCPBF16Zr) + .value("VRCPBF16Zrk", LIEF::assembly::x86::OPCODE::VRCPBF16Zrk) + .value("VRCPBF16Zrkz", LIEF::assembly::x86::OPCODE::VRCPBF16Zrkz) + .value("VRCPPHZ128m", LIEF::assembly::x86::OPCODE::VRCPPHZ128m) + .value("VRCPPHZ128mb", LIEF::assembly::x86::OPCODE::VRCPPHZ128mb) + .value("VRCPPHZ128mbk", LIEF::assembly::x86::OPCODE::VRCPPHZ128mbk) + .value("VRCPPHZ128mbkz", LIEF::assembly::x86::OPCODE::VRCPPHZ128mbkz) + .value("VRCPPHZ128mk", LIEF::assembly::x86::OPCODE::VRCPPHZ128mk) + .value("VRCPPHZ128mkz", LIEF::assembly::x86::OPCODE::VRCPPHZ128mkz) + .value("VRCPPHZ128r", LIEF::assembly::x86::OPCODE::VRCPPHZ128r) + .value("VRCPPHZ128rk", LIEF::assembly::x86::OPCODE::VRCPPHZ128rk) + .value("VRCPPHZ128rkz", LIEF::assembly::x86::OPCODE::VRCPPHZ128rkz) + .value("VRCPPHZ256m", LIEF::assembly::x86::OPCODE::VRCPPHZ256m) + .value("VRCPPHZ256mb", LIEF::assembly::x86::OPCODE::VRCPPHZ256mb) + .value("VRCPPHZ256mbk", LIEF::assembly::x86::OPCODE::VRCPPHZ256mbk) + .value("VRCPPHZ256mbkz", LIEF::assembly::x86::OPCODE::VRCPPHZ256mbkz) + .value("VRCPPHZ256mk", LIEF::assembly::x86::OPCODE::VRCPPHZ256mk) + .value("VRCPPHZ256mkz", LIEF::assembly::x86::OPCODE::VRCPPHZ256mkz) + .value("VRCPPHZ256r", LIEF::assembly::x86::OPCODE::VRCPPHZ256r) + .value("VRCPPHZ256rk", LIEF::assembly::x86::OPCODE::VRCPPHZ256rk) + .value("VRCPPHZ256rkz", LIEF::assembly::x86::OPCODE::VRCPPHZ256rkz) + .value("VRCPPHZm", LIEF::assembly::x86::OPCODE::VRCPPHZm) + .value("VRCPPHZmb", LIEF::assembly::x86::OPCODE::VRCPPHZmb) + .value("VRCPPHZmbk", LIEF::assembly::x86::OPCODE::VRCPPHZmbk) + .value("VRCPPHZmbkz", LIEF::assembly::x86::OPCODE::VRCPPHZmbkz) + .value("VRCPPHZmk", LIEF::assembly::x86::OPCODE::VRCPPHZmk) + .value("VRCPPHZmkz", LIEF::assembly::x86::OPCODE::VRCPPHZmkz) + .value("VRCPPHZr", LIEF::assembly::x86::OPCODE::VRCPPHZr) + .value("VRCPPHZrk", LIEF::assembly::x86::OPCODE::VRCPPHZrk) + .value("VRCPPHZrkz", LIEF::assembly::x86::OPCODE::VRCPPHZrkz) + .value("VRCPPSYm", LIEF::assembly::x86::OPCODE::VRCPPSYm) + .value("VRCPPSYr", LIEF::assembly::x86::OPCODE::VRCPPSYr) + .value("VRCPPSm", LIEF::assembly::x86::OPCODE::VRCPPSm) + .value("VRCPPSr", LIEF::assembly::x86::OPCODE::VRCPPSr) + .value("VRCPSHZrm", LIEF::assembly::x86::OPCODE::VRCPSHZrm) + .value("VRCPSHZrmk", LIEF::assembly::x86::OPCODE::VRCPSHZrmk) + .value("VRCPSHZrmkz", LIEF::assembly::x86::OPCODE::VRCPSHZrmkz) + .value("VRCPSHZrr", LIEF::assembly::x86::OPCODE::VRCPSHZrr) + .value("VRCPSHZrrk", LIEF::assembly::x86::OPCODE::VRCPSHZrrk) + .value("VRCPSHZrrkz", LIEF::assembly::x86::OPCODE::VRCPSHZrrkz) + .value("VRCPSSm", LIEF::assembly::x86::OPCODE::VRCPSSm) + .value("VRCPSSm_Int", LIEF::assembly::x86::OPCODE::VRCPSSm_Int) + .value("VRCPSSr", LIEF::assembly::x86::OPCODE::VRCPSSr) + .value("VRCPSSr_Int", LIEF::assembly::x86::OPCODE::VRCPSSr_Int) + .value("VREDUCEBF16Z128rmbi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmbi) + .value("VREDUCEBF16Z128rmbik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmbik) + .value("VREDUCEBF16Z128rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmbikz) + .value("VREDUCEBF16Z128rmi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmi) + .value("VREDUCEBF16Z128rmik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmik) + .value("VREDUCEBF16Z128rmikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rmikz) + .value("VREDUCEBF16Z128rri", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rri) + .value("VREDUCEBF16Z128rrik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rrik) + .value("VREDUCEBF16Z128rrikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z128rrikz) + .value("VREDUCEBF16Z256rmbi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmbi) + .value("VREDUCEBF16Z256rmbik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmbik) + .value("VREDUCEBF16Z256rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmbikz) + .value("VREDUCEBF16Z256rmi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmi) + .value("VREDUCEBF16Z256rmik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmik) + .value("VREDUCEBF16Z256rmikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rmikz) + .value("VREDUCEBF16Z256rri", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rri) + .value("VREDUCEBF16Z256rrik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rrik) + .value("VREDUCEBF16Z256rrikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Z256rrikz) + .value("VREDUCEBF16Zrmbi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmbi) + .value("VREDUCEBF16Zrmbik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmbik) + .value("VREDUCEBF16Zrmbikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmbikz) + .value("VREDUCEBF16Zrmi", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmi) + .value("VREDUCEBF16Zrmik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmik) + .value("VREDUCEBF16Zrmikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrmikz); + opcodes.value("VREDUCEBF16Zrri", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrri) + .value("VREDUCEBF16Zrrik", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrrik) + .value("VREDUCEBF16Zrrikz", LIEF::assembly::x86::OPCODE::VREDUCEBF16Zrrikz) + .value("VREDUCEPDZ128rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmbi) + .value("VREDUCEPDZ128rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmbik) + .value("VREDUCEPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmbikz) + .value("VREDUCEPDZ128rmi", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmi) + .value("VREDUCEPDZ128rmik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmik) + .value("VREDUCEPDZ128rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rmikz) + .value("VREDUCEPDZ128rri", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rri) + .value("VREDUCEPDZ128rrik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rrik) + .value("VREDUCEPDZ128rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ128rrikz) + .value("VREDUCEPDZ256rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmbi) + .value("VREDUCEPDZ256rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmbik) + .value("VREDUCEPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmbikz) + .value("VREDUCEPDZ256rmi", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmi) + .value("VREDUCEPDZ256rmik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmik) + .value("VREDUCEPDZ256rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rmikz) + .value("VREDUCEPDZ256rri", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rri) + .value("VREDUCEPDZ256rrik", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rrik) + .value("VREDUCEPDZ256rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZ256rrikz) + .value("VREDUCEPDZrmbi", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmbi) + .value("VREDUCEPDZrmbik", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmbik) + .value("VREDUCEPDZrmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmbikz) + .value("VREDUCEPDZrmi", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmi) + .value("VREDUCEPDZrmik", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmik) + .value("VREDUCEPDZrmikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZrmikz) + .value("VREDUCEPDZrri", LIEF::assembly::x86::OPCODE::VREDUCEPDZrri) + .value("VREDUCEPDZrrib", LIEF::assembly::x86::OPCODE::VREDUCEPDZrrib) + .value("VREDUCEPDZrribk", LIEF::assembly::x86::OPCODE::VREDUCEPDZrribk) + .value("VREDUCEPDZrribkz", LIEF::assembly::x86::OPCODE::VREDUCEPDZrribkz) + .value("VREDUCEPDZrrik", LIEF::assembly::x86::OPCODE::VREDUCEPDZrrik) + .value("VREDUCEPDZrrikz", LIEF::assembly::x86::OPCODE::VREDUCEPDZrrikz) + .value("VREDUCEPHZ128rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmbi) + .value("VREDUCEPHZ128rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmbik) + .value("VREDUCEPHZ128rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmbikz) + .value("VREDUCEPHZ128rmi", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmi) + .value("VREDUCEPHZ128rmik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmik) + .value("VREDUCEPHZ128rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rmikz) + .value("VREDUCEPHZ128rri", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rri) + .value("VREDUCEPHZ128rrik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rrik) + .value("VREDUCEPHZ128rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ128rrikz) + .value("VREDUCEPHZ256rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmbi) + .value("VREDUCEPHZ256rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmbik) + .value("VREDUCEPHZ256rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmbikz) + .value("VREDUCEPHZ256rmi", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmi) + .value("VREDUCEPHZ256rmik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmik) + .value("VREDUCEPHZ256rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rmikz) + .value("VREDUCEPHZ256rri", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rri) + .value("VREDUCEPHZ256rrik", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rrik) + .value("VREDUCEPHZ256rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZ256rrikz) + .value("VREDUCEPHZrmbi", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmbi) + .value("VREDUCEPHZrmbik", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmbik) + .value("VREDUCEPHZrmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmbikz) + .value("VREDUCEPHZrmi", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmi) + .value("VREDUCEPHZrmik", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmik) + .value("VREDUCEPHZrmikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZrmikz) + .value("VREDUCEPHZrri", LIEF::assembly::x86::OPCODE::VREDUCEPHZrri) + .value("VREDUCEPHZrrib", LIEF::assembly::x86::OPCODE::VREDUCEPHZrrib) + .value("VREDUCEPHZrribk", LIEF::assembly::x86::OPCODE::VREDUCEPHZrribk) + .value("VREDUCEPHZrribkz", LIEF::assembly::x86::OPCODE::VREDUCEPHZrribkz) + .value("VREDUCEPHZrrik", LIEF::assembly::x86::OPCODE::VREDUCEPHZrrik) + .value("VREDUCEPHZrrikz", LIEF::assembly::x86::OPCODE::VREDUCEPHZrrikz) + .value("VREDUCEPSZ128rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmbi) + .value("VREDUCEPSZ128rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmbik) + .value("VREDUCEPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmbikz) + .value("VREDUCEPSZ128rmi", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmi) + .value("VREDUCEPSZ128rmik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmik) + .value("VREDUCEPSZ128rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rmikz) + .value("VREDUCEPSZ128rri", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rri) + .value("VREDUCEPSZ128rrik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rrik) + .value("VREDUCEPSZ128rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ128rrikz) + .value("VREDUCEPSZ256rmbi", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmbi) + .value("VREDUCEPSZ256rmbik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmbik) + .value("VREDUCEPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmbikz) + .value("VREDUCEPSZ256rmi", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmi) + .value("VREDUCEPSZ256rmik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmik) + .value("VREDUCEPSZ256rmikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rmikz) + .value("VREDUCEPSZ256rri", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rri) + .value("VREDUCEPSZ256rrik", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rrik) + .value("VREDUCEPSZ256rrikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZ256rrikz) + .value("VREDUCEPSZrmbi", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmbi) + .value("VREDUCEPSZrmbik", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmbik) + .value("VREDUCEPSZrmbikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmbikz) + .value("VREDUCEPSZrmi", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmi) + .value("VREDUCEPSZrmik", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmik) + .value("VREDUCEPSZrmikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZrmikz) + .value("VREDUCEPSZrri", LIEF::assembly::x86::OPCODE::VREDUCEPSZrri) + .value("VREDUCEPSZrrib", LIEF::assembly::x86::OPCODE::VREDUCEPSZrrib) + .value("VREDUCEPSZrribk", LIEF::assembly::x86::OPCODE::VREDUCEPSZrribk) + .value("VREDUCEPSZrribkz", LIEF::assembly::x86::OPCODE::VREDUCEPSZrribkz) + .value("VREDUCEPSZrrik", LIEF::assembly::x86::OPCODE::VREDUCEPSZrrik) + .value("VREDUCEPSZrrikz", LIEF::assembly::x86::OPCODE::VREDUCEPSZrrikz) + .value("VREDUCESDZrmi", LIEF::assembly::x86::OPCODE::VREDUCESDZrmi) + .value("VREDUCESDZrmik", LIEF::assembly::x86::OPCODE::VREDUCESDZrmik) + .value("VREDUCESDZrmikz", LIEF::assembly::x86::OPCODE::VREDUCESDZrmikz) + .value("VREDUCESDZrri", LIEF::assembly::x86::OPCODE::VREDUCESDZrri) + .value("VREDUCESDZrrib", LIEF::assembly::x86::OPCODE::VREDUCESDZrrib) + .value("VREDUCESDZrribk", LIEF::assembly::x86::OPCODE::VREDUCESDZrribk) + .value("VREDUCESDZrribkz", LIEF::assembly::x86::OPCODE::VREDUCESDZrribkz) + .value("VREDUCESDZrrik", LIEF::assembly::x86::OPCODE::VREDUCESDZrrik) + .value("VREDUCESDZrrikz", LIEF::assembly::x86::OPCODE::VREDUCESDZrrikz) + .value("VREDUCESHZrmi", LIEF::assembly::x86::OPCODE::VREDUCESHZrmi) + .value("VREDUCESHZrmik", LIEF::assembly::x86::OPCODE::VREDUCESHZrmik) + .value("VREDUCESHZrmikz", LIEF::assembly::x86::OPCODE::VREDUCESHZrmikz) + .value("VREDUCESHZrri", LIEF::assembly::x86::OPCODE::VREDUCESHZrri) + .value("VREDUCESHZrrib", LIEF::assembly::x86::OPCODE::VREDUCESHZrrib) + .value("VREDUCESHZrribk", LIEF::assembly::x86::OPCODE::VREDUCESHZrribk) + .value("VREDUCESHZrribkz", LIEF::assembly::x86::OPCODE::VREDUCESHZrribkz) + .value("VREDUCESHZrrik", LIEF::assembly::x86::OPCODE::VREDUCESHZrrik) + .value("VREDUCESHZrrikz", LIEF::assembly::x86::OPCODE::VREDUCESHZrrikz) + .value("VREDUCESSZrmi", LIEF::assembly::x86::OPCODE::VREDUCESSZrmi) + .value("VREDUCESSZrmik", LIEF::assembly::x86::OPCODE::VREDUCESSZrmik) + .value("VREDUCESSZrmikz", LIEF::assembly::x86::OPCODE::VREDUCESSZrmikz) + .value("VREDUCESSZrri", LIEF::assembly::x86::OPCODE::VREDUCESSZrri) + .value("VREDUCESSZrrib", LIEF::assembly::x86::OPCODE::VREDUCESSZrrib) + .value("VREDUCESSZrribk", LIEF::assembly::x86::OPCODE::VREDUCESSZrribk) + .value("VREDUCESSZrribkz", LIEF::assembly::x86::OPCODE::VREDUCESSZrribkz) + .value("VREDUCESSZrrik", LIEF::assembly::x86::OPCODE::VREDUCESSZrrik) + .value("VREDUCESSZrrikz", LIEF::assembly::x86::OPCODE::VREDUCESSZrrikz) + .value("VRNDSCALEBF16Z128rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmbi) + .value("VRNDSCALEBF16Z128rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmbik) + .value("VRNDSCALEBF16Z128rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmbikz) + .value("VRNDSCALEBF16Z128rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmi) + .value("VRNDSCALEBF16Z128rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmik) + .value("VRNDSCALEBF16Z128rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rmikz) + .value("VRNDSCALEBF16Z128rri", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rri) + .value("VRNDSCALEBF16Z128rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rrik) + .value("VRNDSCALEBF16Z128rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z128rrikz) + .value("VRNDSCALEBF16Z256rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmbi) + .value("VRNDSCALEBF16Z256rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmbik) + .value("VRNDSCALEBF16Z256rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmbikz) + .value("VRNDSCALEBF16Z256rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmi) + .value("VRNDSCALEBF16Z256rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmik) + .value("VRNDSCALEBF16Z256rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rmikz) + .value("VRNDSCALEBF16Z256rri", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rri) + .value("VRNDSCALEBF16Z256rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rrik) + .value("VRNDSCALEBF16Z256rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Z256rrikz) + .value("VRNDSCALEBF16Zrmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmbi) + .value("VRNDSCALEBF16Zrmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmbik) + .value("VRNDSCALEBF16Zrmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmbikz) + .value("VRNDSCALEBF16Zrmi", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmi) + .value("VRNDSCALEBF16Zrmik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmik) + .value("VRNDSCALEBF16Zrmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrmikz) + .value("VRNDSCALEBF16Zrri", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrri) + .value("VRNDSCALEBF16Zrrik", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrrik) + .value("VRNDSCALEBF16Zrrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEBF16Zrrikz) + .value("VRNDSCALEPDZ128rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmbi) + .value("VRNDSCALEPDZ128rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmbik) + .value("VRNDSCALEPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmbikz) + .value("VRNDSCALEPDZ128rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmi) + .value("VRNDSCALEPDZ128rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmik) + .value("VRNDSCALEPDZ128rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rmikz) + .value("VRNDSCALEPDZ128rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rri) + .value("VRNDSCALEPDZ128rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rrik) + .value("VRNDSCALEPDZ128rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ128rrikz) + .value("VRNDSCALEPDZ256rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmbi) + .value("VRNDSCALEPDZ256rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmbik) + .value("VRNDSCALEPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmbikz) + .value("VRNDSCALEPDZ256rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmi) + .value("VRNDSCALEPDZ256rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmik) + .value("VRNDSCALEPDZ256rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rmikz) + .value("VRNDSCALEPDZ256rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rri) + .value("VRNDSCALEPDZ256rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rrik) + .value("VRNDSCALEPDZ256rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZ256rrikz) + .value("VRNDSCALEPDZrmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmbi) + .value("VRNDSCALEPDZrmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmbik) + .value("VRNDSCALEPDZrmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmbikz) + .value("VRNDSCALEPDZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmi) + .value("VRNDSCALEPDZrmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmik) + .value("VRNDSCALEPDZrmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrmikz) + .value("VRNDSCALEPDZrri", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrri) + .value("VRNDSCALEPDZrrib", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrrib) + .value("VRNDSCALEPDZrribk", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrribk) + .value("VRNDSCALEPDZrribkz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrribkz) + .value("VRNDSCALEPDZrrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrrik) + .value("VRNDSCALEPDZrrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPDZrrikz) + .value("VRNDSCALEPHZ128rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmbi) + .value("VRNDSCALEPHZ128rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmbik) + .value("VRNDSCALEPHZ128rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmbikz) + .value("VRNDSCALEPHZ128rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmi) + .value("VRNDSCALEPHZ128rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmik) + .value("VRNDSCALEPHZ128rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rmikz) + .value("VRNDSCALEPHZ128rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rri) + .value("VRNDSCALEPHZ128rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rrik) + .value("VRNDSCALEPHZ128rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ128rrikz) + .value("VRNDSCALEPHZ256rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmbi) + .value("VRNDSCALEPHZ256rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmbik) + .value("VRNDSCALEPHZ256rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmbikz) + .value("VRNDSCALEPHZ256rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmi) + .value("VRNDSCALEPHZ256rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmik) + .value("VRNDSCALEPHZ256rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rmikz) + .value("VRNDSCALEPHZ256rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rri) + .value("VRNDSCALEPHZ256rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rrik) + .value("VRNDSCALEPHZ256rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZ256rrikz) + .value("VRNDSCALEPHZrmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmbi) + .value("VRNDSCALEPHZrmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmbik) + .value("VRNDSCALEPHZrmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmbikz) + .value("VRNDSCALEPHZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmi) + .value("VRNDSCALEPHZrmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmik) + .value("VRNDSCALEPHZrmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrmikz) + .value("VRNDSCALEPHZrri", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrri) + .value("VRNDSCALEPHZrrib", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrrib) + .value("VRNDSCALEPHZrribk", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrribk) + .value("VRNDSCALEPHZrribkz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrribkz) + .value("VRNDSCALEPHZrrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrrik) + .value("VRNDSCALEPHZrrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPHZrrikz) + .value("VRNDSCALEPSZ128rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmbi) + .value("VRNDSCALEPSZ128rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmbik) + .value("VRNDSCALEPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmbikz) + .value("VRNDSCALEPSZ128rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmi) + .value("VRNDSCALEPSZ128rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmik) + .value("VRNDSCALEPSZ128rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rmikz) + .value("VRNDSCALEPSZ128rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rri) + .value("VRNDSCALEPSZ128rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rrik) + .value("VRNDSCALEPSZ128rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ128rrikz) + .value("VRNDSCALEPSZ256rmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmbi) + .value("VRNDSCALEPSZ256rmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmbik) + .value("VRNDSCALEPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmbikz) + .value("VRNDSCALEPSZ256rmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmi) + .value("VRNDSCALEPSZ256rmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmik) + .value("VRNDSCALEPSZ256rmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rmikz) + .value("VRNDSCALEPSZ256rri", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rri) + .value("VRNDSCALEPSZ256rrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rrik) + .value("VRNDSCALEPSZ256rrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZ256rrikz) + .value("VRNDSCALEPSZrmbi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmbi) + .value("VRNDSCALEPSZrmbik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmbik) + .value("VRNDSCALEPSZrmbikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmbikz) + .value("VRNDSCALEPSZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmi) + .value("VRNDSCALEPSZrmik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmik) + .value("VRNDSCALEPSZrmikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrmikz) + .value("VRNDSCALEPSZrri", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrri) + .value("VRNDSCALEPSZrrib", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrrib) + .value("VRNDSCALEPSZrribk", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrribk) + .value("VRNDSCALEPSZrribkz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrribkz) + .value("VRNDSCALEPSZrrik", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrrik) + .value("VRNDSCALEPSZrrikz", LIEF::assembly::x86::OPCODE::VRNDSCALEPSZrrikz) + .value("VRNDSCALESDZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrmi) + .value("VRNDSCALESDZrmi_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrmi_Int) + .value("VRNDSCALESDZrmik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrmik_Int) + .value("VRNDSCALESDZrmikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrmikz_Int) + .value("VRNDSCALESDZrri", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrri) + .value("VRNDSCALESDZrri_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrri_Int) + .value("VRNDSCALESDZrrib_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrrib_Int) + .value("VRNDSCALESDZrribk_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrribk_Int) + .value("VRNDSCALESDZrribkz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrribkz_Int) + .value("VRNDSCALESDZrrik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrrik_Int) + .value("VRNDSCALESDZrrikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESDZrrikz_Int) + .value("VRNDSCALESHZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrmi) + .value("VRNDSCALESHZrmi_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrmi_Int) + .value("VRNDSCALESHZrmik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrmik_Int) + .value("VRNDSCALESHZrmikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrmikz_Int) + .value("VRNDSCALESHZrri", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrri) + .value("VRNDSCALESHZrri_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrri_Int) + .value("VRNDSCALESHZrrib_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrrib_Int) + .value("VRNDSCALESHZrribk_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrribk_Int) + .value("VRNDSCALESHZrribkz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrribkz_Int) + .value("VRNDSCALESHZrrik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrrik_Int) + .value("VRNDSCALESHZrrikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESHZrrikz_Int) + .value("VRNDSCALESSZrmi", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrmi) + .value("VRNDSCALESSZrmi_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrmi_Int) + .value("VRNDSCALESSZrmik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrmik_Int) + .value("VRNDSCALESSZrmikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrmikz_Int) + .value("VRNDSCALESSZrri", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrri) + .value("VRNDSCALESSZrri_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrri_Int) + .value("VRNDSCALESSZrrib_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrrib_Int) + .value("VRNDSCALESSZrribk_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrribk_Int) + .value("VRNDSCALESSZrribkz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrribkz_Int) + .value("VRNDSCALESSZrrik_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrrik_Int) + .value("VRNDSCALESSZrrikz_Int", LIEF::assembly::x86::OPCODE::VRNDSCALESSZrrikz_Int) + .value("VROUNDPDYmi", LIEF::assembly::x86::OPCODE::VROUNDPDYmi) + .value("VROUNDPDYri", LIEF::assembly::x86::OPCODE::VROUNDPDYri) + .value("VROUNDPDmi", LIEF::assembly::x86::OPCODE::VROUNDPDmi) + .value("VROUNDPDri", LIEF::assembly::x86::OPCODE::VROUNDPDri) + .value("VROUNDPSYmi", LIEF::assembly::x86::OPCODE::VROUNDPSYmi) + .value("VROUNDPSYri", LIEF::assembly::x86::OPCODE::VROUNDPSYri) + .value("VROUNDPSmi", LIEF::assembly::x86::OPCODE::VROUNDPSmi) + .value("VROUNDPSri", LIEF::assembly::x86::OPCODE::VROUNDPSri) + .value("VROUNDSDmi", LIEF::assembly::x86::OPCODE::VROUNDSDmi) + .value("VROUNDSDmi_Int", LIEF::assembly::x86::OPCODE::VROUNDSDmi_Int) + .value("VROUNDSDri", LIEF::assembly::x86::OPCODE::VROUNDSDri) + .value("VROUNDSDri_Int", LIEF::assembly::x86::OPCODE::VROUNDSDri_Int) + .value("VROUNDSSmi", LIEF::assembly::x86::OPCODE::VROUNDSSmi) + .value("VROUNDSSmi_Int", LIEF::assembly::x86::OPCODE::VROUNDSSmi_Int) + .value("VROUNDSSri", LIEF::assembly::x86::OPCODE::VROUNDSSri) + .value("VROUNDSSri_Int", LIEF::assembly::x86::OPCODE::VROUNDSSri_Int) + .value("VRSQRT14PDZ128m", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128m) + .value("VRSQRT14PDZ128mb", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128mb) + .value("VRSQRT14PDZ128mbk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128mbk) + .value("VRSQRT14PDZ128mbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128mbkz) + .value("VRSQRT14PDZ128mk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128mk) + .value("VRSQRT14PDZ128mkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128mkz) + .value("VRSQRT14PDZ128r", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128r) + .value("VRSQRT14PDZ128rk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128rk) + .value("VRSQRT14PDZ128rkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ128rkz) + .value("VRSQRT14PDZ256m", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256m) + .value("VRSQRT14PDZ256mb", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256mb) + .value("VRSQRT14PDZ256mbk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256mbk) + .value("VRSQRT14PDZ256mbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256mbkz) + .value("VRSQRT14PDZ256mk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256mk); + opcodes.value("VRSQRT14PDZ256mkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256mkz) + .value("VRSQRT14PDZ256r", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256r) + .value("VRSQRT14PDZ256rk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256rk) + .value("VRSQRT14PDZ256rkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZ256rkz) + .value("VRSQRT14PDZm", LIEF::assembly::x86::OPCODE::VRSQRT14PDZm) + .value("VRSQRT14PDZmb", LIEF::assembly::x86::OPCODE::VRSQRT14PDZmb) + .value("VRSQRT14PDZmbk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZmbk) + .value("VRSQRT14PDZmbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZmbkz) + .value("VRSQRT14PDZmk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZmk) + .value("VRSQRT14PDZmkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZmkz) + .value("VRSQRT14PDZr", LIEF::assembly::x86::OPCODE::VRSQRT14PDZr) + .value("VRSQRT14PDZrk", LIEF::assembly::x86::OPCODE::VRSQRT14PDZrk) + .value("VRSQRT14PDZrkz", LIEF::assembly::x86::OPCODE::VRSQRT14PDZrkz) + .value("VRSQRT14PSZ128m", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128m) + .value("VRSQRT14PSZ128mb", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128mb) + .value("VRSQRT14PSZ128mbk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128mbk) + .value("VRSQRT14PSZ128mbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128mbkz) + .value("VRSQRT14PSZ128mk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128mk) + .value("VRSQRT14PSZ128mkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128mkz) + .value("VRSQRT14PSZ128r", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128r) + .value("VRSQRT14PSZ128rk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128rk) + .value("VRSQRT14PSZ128rkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ128rkz) + .value("VRSQRT14PSZ256m", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256m) + .value("VRSQRT14PSZ256mb", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256mb) + .value("VRSQRT14PSZ256mbk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256mbk) + .value("VRSQRT14PSZ256mbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256mbkz) + .value("VRSQRT14PSZ256mk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256mk) + .value("VRSQRT14PSZ256mkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256mkz) + .value("VRSQRT14PSZ256r", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256r) + .value("VRSQRT14PSZ256rk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256rk) + .value("VRSQRT14PSZ256rkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZ256rkz) + .value("VRSQRT14PSZm", LIEF::assembly::x86::OPCODE::VRSQRT14PSZm) + .value("VRSQRT14PSZmb", LIEF::assembly::x86::OPCODE::VRSQRT14PSZmb) + .value("VRSQRT14PSZmbk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZmbk) + .value("VRSQRT14PSZmbkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZmbkz) + .value("VRSQRT14PSZmk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZmk) + .value("VRSQRT14PSZmkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZmkz) + .value("VRSQRT14PSZr", LIEF::assembly::x86::OPCODE::VRSQRT14PSZr) + .value("VRSQRT14PSZrk", LIEF::assembly::x86::OPCODE::VRSQRT14PSZrk) + .value("VRSQRT14PSZrkz", LIEF::assembly::x86::OPCODE::VRSQRT14PSZrkz) + .value("VRSQRT14SDZrm", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrm) + .value("VRSQRT14SDZrmk", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrmk) + .value("VRSQRT14SDZrmkz", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrmkz) + .value("VRSQRT14SDZrr", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrr) + .value("VRSQRT14SDZrrk", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrrk) + .value("VRSQRT14SDZrrkz", LIEF::assembly::x86::OPCODE::VRSQRT14SDZrrkz) + .value("VRSQRT14SSZrm", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrm) + .value("VRSQRT14SSZrmk", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrmk) + .value("VRSQRT14SSZrmkz", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrmkz) + .value("VRSQRT14SSZrr", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrr) + .value("VRSQRT14SSZrrk", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrrk) + .value("VRSQRT14SSZrrkz", LIEF::assembly::x86::OPCODE::VRSQRT14SSZrrkz) + .value("VRSQRT28PDZm", LIEF::assembly::x86::OPCODE::VRSQRT28PDZm) + .value("VRSQRT28PDZmb", LIEF::assembly::x86::OPCODE::VRSQRT28PDZmb) + .value("VRSQRT28PDZmbk", LIEF::assembly::x86::OPCODE::VRSQRT28PDZmbk) + .value("VRSQRT28PDZmbkz", LIEF::assembly::x86::OPCODE::VRSQRT28PDZmbkz) + .value("VRSQRT28PDZmk", LIEF::assembly::x86::OPCODE::VRSQRT28PDZmk) + .value("VRSQRT28PDZmkz", LIEF::assembly::x86::OPCODE::VRSQRT28PDZmkz) + .value("VRSQRT28PDZr", LIEF::assembly::x86::OPCODE::VRSQRT28PDZr) + .value("VRSQRT28PDZrb", LIEF::assembly::x86::OPCODE::VRSQRT28PDZrb) + .value("VRSQRT28PDZrbk", LIEF::assembly::x86::OPCODE::VRSQRT28PDZrbk) + .value("VRSQRT28PDZrbkz", LIEF::assembly::x86::OPCODE::VRSQRT28PDZrbkz) + .value("VRSQRT28PDZrk", LIEF::assembly::x86::OPCODE::VRSQRT28PDZrk) + .value("VRSQRT28PDZrkz", LIEF::assembly::x86::OPCODE::VRSQRT28PDZrkz) + .value("VRSQRT28PSZm", LIEF::assembly::x86::OPCODE::VRSQRT28PSZm) + .value("VRSQRT28PSZmb", LIEF::assembly::x86::OPCODE::VRSQRT28PSZmb) + .value("VRSQRT28PSZmbk", LIEF::assembly::x86::OPCODE::VRSQRT28PSZmbk) + .value("VRSQRT28PSZmbkz", LIEF::assembly::x86::OPCODE::VRSQRT28PSZmbkz) + .value("VRSQRT28PSZmk", LIEF::assembly::x86::OPCODE::VRSQRT28PSZmk) + .value("VRSQRT28PSZmkz", LIEF::assembly::x86::OPCODE::VRSQRT28PSZmkz) + .value("VRSQRT28PSZr", LIEF::assembly::x86::OPCODE::VRSQRT28PSZr) + .value("VRSQRT28PSZrb", LIEF::assembly::x86::OPCODE::VRSQRT28PSZrb) + .value("VRSQRT28PSZrbk", LIEF::assembly::x86::OPCODE::VRSQRT28PSZrbk) + .value("VRSQRT28PSZrbkz", LIEF::assembly::x86::OPCODE::VRSQRT28PSZrbkz) + .value("VRSQRT28PSZrk", LIEF::assembly::x86::OPCODE::VRSQRT28PSZrk) + .value("VRSQRT28PSZrkz", LIEF::assembly::x86::OPCODE::VRSQRT28PSZrkz) + .value("VRSQRT28SDZm", LIEF::assembly::x86::OPCODE::VRSQRT28SDZm) + .value("VRSQRT28SDZmk", LIEF::assembly::x86::OPCODE::VRSQRT28SDZmk) + .value("VRSQRT28SDZmkz", LIEF::assembly::x86::OPCODE::VRSQRT28SDZmkz) + .value("VRSQRT28SDZr", LIEF::assembly::x86::OPCODE::VRSQRT28SDZr) + .value("VRSQRT28SDZrb", LIEF::assembly::x86::OPCODE::VRSQRT28SDZrb) + .value("VRSQRT28SDZrbk", LIEF::assembly::x86::OPCODE::VRSQRT28SDZrbk) + .value("VRSQRT28SDZrbkz", LIEF::assembly::x86::OPCODE::VRSQRT28SDZrbkz) + .value("VRSQRT28SDZrk", LIEF::assembly::x86::OPCODE::VRSQRT28SDZrk) + .value("VRSQRT28SDZrkz", LIEF::assembly::x86::OPCODE::VRSQRT28SDZrkz) + .value("VRSQRT28SSZm", LIEF::assembly::x86::OPCODE::VRSQRT28SSZm) + .value("VRSQRT28SSZmk", LIEF::assembly::x86::OPCODE::VRSQRT28SSZmk) + .value("VRSQRT28SSZmkz", LIEF::assembly::x86::OPCODE::VRSQRT28SSZmkz) + .value("VRSQRT28SSZr", LIEF::assembly::x86::OPCODE::VRSQRT28SSZr) + .value("VRSQRT28SSZrb", LIEF::assembly::x86::OPCODE::VRSQRT28SSZrb) + .value("VRSQRT28SSZrbk", LIEF::assembly::x86::OPCODE::VRSQRT28SSZrbk) + .value("VRSQRT28SSZrbkz", LIEF::assembly::x86::OPCODE::VRSQRT28SSZrbkz) + .value("VRSQRT28SSZrk", LIEF::assembly::x86::OPCODE::VRSQRT28SSZrk) + .value("VRSQRT28SSZrkz", LIEF::assembly::x86::OPCODE::VRSQRT28SSZrkz) + .value("VRSQRTBF16Z128m", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128m) + .value("VRSQRTBF16Z128mb", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128mb) + .value("VRSQRTBF16Z128mbk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128mbk) + .value("VRSQRTBF16Z128mbkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128mbkz) + .value("VRSQRTBF16Z128mk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128mk) + .value("VRSQRTBF16Z128mkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128mkz) + .value("VRSQRTBF16Z128r", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128r) + .value("VRSQRTBF16Z128rk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128rk) + .value("VRSQRTBF16Z128rkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z128rkz) + .value("VRSQRTBF16Z256m", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256m) + .value("VRSQRTBF16Z256mb", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256mb) + .value("VRSQRTBF16Z256mbk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256mbk) + .value("VRSQRTBF16Z256mbkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256mbkz) + .value("VRSQRTBF16Z256mk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256mk) + .value("VRSQRTBF16Z256mkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256mkz) + .value("VRSQRTBF16Z256r", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256r) + .value("VRSQRTBF16Z256rk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256rk) + .value("VRSQRTBF16Z256rkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Z256rkz) + .value("VRSQRTBF16Zm", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zm) + .value("VRSQRTBF16Zmb", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zmb) + .value("VRSQRTBF16Zmbk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zmbk) + .value("VRSQRTBF16Zmbkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zmbkz) + .value("VRSQRTBF16Zmk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zmk) + .value("VRSQRTBF16Zmkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zmkz) + .value("VRSQRTBF16Zr", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zr) + .value("VRSQRTBF16Zrk", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zrk) + .value("VRSQRTBF16Zrkz", LIEF::assembly::x86::OPCODE::VRSQRTBF16Zrkz) + .value("VRSQRTPHZ128m", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128m) + .value("VRSQRTPHZ128mb", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128mb) + .value("VRSQRTPHZ128mbk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128mbk) + .value("VRSQRTPHZ128mbkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128mbkz) + .value("VRSQRTPHZ128mk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128mk) + .value("VRSQRTPHZ128mkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128mkz) + .value("VRSQRTPHZ128r", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128r) + .value("VRSQRTPHZ128rk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128rk) + .value("VRSQRTPHZ128rkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ128rkz) + .value("VRSQRTPHZ256m", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256m) + .value("VRSQRTPHZ256mb", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256mb) + .value("VRSQRTPHZ256mbk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256mbk) + .value("VRSQRTPHZ256mbkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256mbkz) + .value("VRSQRTPHZ256mk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256mk) + .value("VRSQRTPHZ256mkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256mkz) + .value("VRSQRTPHZ256r", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256r) + .value("VRSQRTPHZ256rk", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256rk) + .value("VRSQRTPHZ256rkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZ256rkz) + .value("VRSQRTPHZm", LIEF::assembly::x86::OPCODE::VRSQRTPHZm) + .value("VRSQRTPHZmb", LIEF::assembly::x86::OPCODE::VRSQRTPHZmb) + .value("VRSQRTPHZmbk", LIEF::assembly::x86::OPCODE::VRSQRTPHZmbk) + .value("VRSQRTPHZmbkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZmbkz) + .value("VRSQRTPHZmk", LIEF::assembly::x86::OPCODE::VRSQRTPHZmk) + .value("VRSQRTPHZmkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZmkz) + .value("VRSQRTPHZr", LIEF::assembly::x86::OPCODE::VRSQRTPHZr) + .value("VRSQRTPHZrk", LIEF::assembly::x86::OPCODE::VRSQRTPHZrk) + .value("VRSQRTPHZrkz", LIEF::assembly::x86::OPCODE::VRSQRTPHZrkz) + .value("VRSQRTPSYm", LIEF::assembly::x86::OPCODE::VRSQRTPSYm) + .value("VRSQRTPSYr", LIEF::assembly::x86::OPCODE::VRSQRTPSYr) + .value("VRSQRTPSm", LIEF::assembly::x86::OPCODE::VRSQRTPSm) + .value("VRSQRTPSr", LIEF::assembly::x86::OPCODE::VRSQRTPSr) + .value("VRSQRTSHZrm", LIEF::assembly::x86::OPCODE::VRSQRTSHZrm) + .value("VRSQRTSHZrmk", LIEF::assembly::x86::OPCODE::VRSQRTSHZrmk) + .value("VRSQRTSHZrmkz", LIEF::assembly::x86::OPCODE::VRSQRTSHZrmkz) + .value("VRSQRTSHZrr", LIEF::assembly::x86::OPCODE::VRSQRTSHZrr) + .value("VRSQRTSHZrrk", LIEF::assembly::x86::OPCODE::VRSQRTSHZrrk) + .value("VRSQRTSHZrrkz", LIEF::assembly::x86::OPCODE::VRSQRTSHZrrkz) + .value("VRSQRTSSm", LIEF::assembly::x86::OPCODE::VRSQRTSSm) + .value("VRSQRTSSm_Int", LIEF::assembly::x86::OPCODE::VRSQRTSSm_Int) + .value("VRSQRTSSr", LIEF::assembly::x86::OPCODE::VRSQRTSSr) + .value("VRSQRTSSr_Int", LIEF::assembly::x86::OPCODE::VRSQRTSSr_Int) + .value("VSCALEFBF16Z128rm", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rm) + .value("VSCALEFBF16Z128rmb", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rmb) + .value("VSCALEFBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rmbk) + .value("VSCALEFBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rmbkz) + .value("VSCALEFBF16Z128rmk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rmk) + .value("VSCALEFBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rmkz) + .value("VSCALEFBF16Z128rr", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rr) + .value("VSCALEFBF16Z128rrk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rrk) + .value("VSCALEFBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z128rrkz) + .value("VSCALEFBF16Z256rm", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rm) + .value("VSCALEFBF16Z256rmb", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rmb) + .value("VSCALEFBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rmbk) + .value("VSCALEFBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rmbkz) + .value("VSCALEFBF16Z256rmk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rmk) + .value("VSCALEFBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rmkz) + .value("VSCALEFBF16Z256rr", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rr) + .value("VSCALEFBF16Z256rrk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rrk) + .value("VSCALEFBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Z256rrkz) + .value("VSCALEFBF16Zrm", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrm) + .value("VSCALEFBF16Zrmb", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrmb) + .value("VSCALEFBF16Zrmbk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrmbk) + .value("VSCALEFBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrmbkz) + .value("VSCALEFBF16Zrmk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrmk) + .value("VSCALEFBF16Zrmkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrmkz) + .value("VSCALEFBF16Zrr", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrr) + .value("VSCALEFBF16Zrrk", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrrk) + .value("VSCALEFBF16Zrrkz", LIEF::assembly::x86::OPCODE::VSCALEFBF16Zrrkz) + .value("VSCALEFPDZ128rm", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rm) + .value("VSCALEFPDZ128rmb", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rmb) + .value("VSCALEFPDZ128rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rmbk) + .value("VSCALEFPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rmbkz) + .value("VSCALEFPDZ128rmk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rmk) + .value("VSCALEFPDZ128rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rmkz) + .value("VSCALEFPDZ128rr", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rr) + .value("VSCALEFPDZ128rrk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rrk) + .value("VSCALEFPDZ128rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ128rrkz) + .value("VSCALEFPDZ256rm", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rm) + .value("VSCALEFPDZ256rmb", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rmb) + .value("VSCALEFPDZ256rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rmbk) + .value("VSCALEFPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rmbkz) + .value("VSCALEFPDZ256rmk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rmk) + .value("VSCALEFPDZ256rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rmkz) + .value("VSCALEFPDZ256rr", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rr) + .value("VSCALEFPDZ256rrk", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rrk) + .value("VSCALEFPDZ256rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZ256rrkz) + .value("VSCALEFPDZrm", LIEF::assembly::x86::OPCODE::VSCALEFPDZrm) + .value("VSCALEFPDZrmb", LIEF::assembly::x86::OPCODE::VSCALEFPDZrmb) + .value("VSCALEFPDZrmbk", LIEF::assembly::x86::OPCODE::VSCALEFPDZrmbk) + .value("VSCALEFPDZrmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZrmbkz) + .value("VSCALEFPDZrmk", LIEF::assembly::x86::OPCODE::VSCALEFPDZrmk) + .value("VSCALEFPDZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZrmkz) + .value("VSCALEFPDZrr", LIEF::assembly::x86::OPCODE::VSCALEFPDZrr) + .value("VSCALEFPDZrrb", LIEF::assembly::x86::OPCODE::VSCALEFPDZrrb) + .value("VSCALEFPDZrrbk", LIEF::assembly::x86::OPCODE::VSCALEFPDZrrbk) + .value("VSCALEFPDZrrbkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZrrbkz) + .value("VSCALEFPDZrrk", LIEF::assembly::x86::OPCODE::VSCALEFPDZrrk) + .value("VSCALEFPDZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFPDZrrkz) + .value("VSCALEFPHZ128rm", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rm) + .value("VSCALEFPHZ128rmb", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rmb) + .value("VSCALEFPHZ128rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rmbk) + .value("VSCALEFPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rmbkz) + .value("VSCALEFPHZ128rmk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rmk) + .value("VSCALEFPHZ128rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rmkz) + .value("VSCALEFPHZ128rr", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rr) + .value("VSCALEFPHZ128rrk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rrk) + .value("VSCALEFPHZ128rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ128rrkz) + .value("VSCALEFPHZ256rm", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rm) + .value("VSCALEFPHZ256rmb", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rmb) + .value("VSCALEFPHZ256rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rmbk) + .value("VSCALEFPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rmbkz) + .value("VSCALEFPHZ256rmk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rmk) + .value("VSCALEFPHZ256rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rmkz) + .value("VSCALEFPHZ256rr", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rr) + .value("VSCALEFPHZ256rrk", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rrk) + .value("VSCALEFPHZ256rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZ256rrkz) + .value("VSCALEFPHZrm", LIEF::assembly::x86::OPCODE::VSCALEFPHZrm) + .value("VSCALEFPHZrmb", LIEF::assembly::x86::OPCODE::VSCALEFPHZrmb) + .value("VSCALEFPHZrmbk", LIEF::assembly::x86::OPCODE::VSCALEFPHZrmbk) + .value("VSCALEFPHZrmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZrmbkz) + .value("VSCALEFPHZrmk", LIEF::assembly::x86::OPCODE::VSCALEFPHZrmk) + .value("VSCALEFPHZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZrmkz) + .value("VSCALEFPHZrr", LIEF::assembly::x86::OPCODE::VSCALEFPHZrr) + .value("VSCALEFPHZrrb", LIEF::assembly::x86::OPCODE::VSCALEFPHZrrb) + .value("VSCALEFPHZrrbk", LIEF::assembly::x86::OPCODE::VSCALEFPHZrrbk) + .value("VSCALEFPHZrrbkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZrrbkz) + .value("VSCALEFPHZrrk", LIEF::assembly::x86::OPCODE::VSCALEFPHZrrk) + .value("VSCALEFPHZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFPHZrrkz) + .value("VSCALEFPSZ128rm", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rm) + .value("VSCALEFPSZ128rmb", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rmb) + .value("VSCALEFPSZ128rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rmbk) + .value("VSCALEFPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rmbkz) + .value("VSCALEFPSZ128rmk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rmk) + .value("VSCALEFPSZ128rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rmkz) + .value("VSCALEFPSZ128rr", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rr) + .value("VSCALEFPSZ128rrk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rrk) + .value("VSCALEFPSZ128rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ128rrkz) + .value("VSCALEFPSZ256rm", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rm) + .value("VSCALEFPSZ256rmb", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rmb) + .value("VSCALEFPSZ256rmbk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rmbk) + .value("VSCALEFPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rmbkz) + .value("VSCALEFPSZ256rmk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rmk) + .value("VSCALEFPSZ256rmkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rmkz) + .value("VSCALEFPSZ256rr", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rr) + .value("VSCALEFPSZ256rrk", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rrk) + .value("VSCALEFPSZ256rrkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZ256rrkz) + .value("VSCALEFPSZrm", LIEF::assembly::x86::OPCODE::VSCALEFPSZrm) + .value("VSCALEFPSZrmb", LIEF::assembly::x86::OPCODE::VSCALEFPSZrmb) + .value("VSCALEFPSZrmbk", LIEF::assembly::x86::OPCODE::VSCALEFPSZrmbk) + .value("VSCALEFPSZrmbkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZrmbkz) + .value("VSCALEFPSZrmk", LIEF::assembly::x86::OPCODE::VSCALEFPSZrmk) + .value("VSCALEFPSZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZrmkz) + .value("VSCALEFPSZrr", LIEF::assembly::x86::OPCODE::VSCALEFPSZrr) + .value("VSCALEFPSZrrb", LIEF::assembly::x86::OPCODE::VSCALEFPSZrrb) + .value("VSCALEFPSZrrbk", LIEF::assembly::x86::OPCODE::VSCALEFPSZrrbk) + .value("VSCALEFPSZrrbkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZrrbkz) + .value("VSCALEFPSZrrk", LIEF::assembly::x86::OPCODE::VSCALEFPSZrrk) + .value("VSCALEFPSZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFPSZrrkz) + .value("VSCALEFSDZrm", LIEF::assembly::x86::OPCODE::VSCALEFSDZrm) + .value("VSCALEFSDZrmk", LIEF::assembly::x86::OPCODE::VSCALEFSDZrmk) + .value("VSCALEFSDZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFSDZrmkz) + .value("VSCALEFSDZrr", LIEF::assembly::x86::OPCODE::VSCALEFSDZrr) + .value("VSCALEFSDZrrb_Int", LIEF::assembly::x86::OPCODE::VSCALEFSDZrrb_Int) + .value("VSCALEFSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VSCALEFSDZrrbk_Int) + .value("VSCALEFSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSCALEFSDZrrbkz_Int) + .value("VSCALEFSDZrrk", LIEF::assembly::x86::OPCODE::VSCALEFSDZrrk) + .value("VSCALEFSDZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFSDZrrkz) + .value("VSCALEFSHZrm", LIEF::assembly::x86::OPCODE::VSCALEFSHZrm) + .value("VSCALEFSHZrmk", LIEF::assembly::x86::OPCODE::VSCALEFSHZrmk) + .value("VSCALEFSHZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFSHZrmkz) + .value("VSCALEFSHZrr", LIEF::assembly::x86::OPCODE::VSCALEFSHZrr) + .value("VSCALEFSHZrrb_Int", LIEF::assembly::x86::OPCODE::VSCALEFSHZrrb_Int) + .value("VSCALEFSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VSCALEFSHZrrbk_Int) + .value("VSCALEFSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSCALEFSHZrrbkz_Int) + .value("VSCALEFSHZrrk", LIEF::assembly::x86::OPCODE::VSCALEFSHZrrk) + .value("VSCALEFSHZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFSHZrrkz) + .value("VSCALEFSSZrm", LIEF::assembly::x86::OPCODE::VSCALEFSSZrm) + .value("VSCALEFSSZrmk", LIEF::assembly::x86::OPCODE::VSCALEFSSZrmk) + .value("VSCALEFSSZrmkz", LIEF::assembly::x86::OPCODE::VSCALEFSSZrmkz); + opcodes.value("VSCALEFSSZrr", LIEF::assembly::x86::OPCODE::VSCALEFSSZrr) + .value("VSCALEFSSZrrb_Int", LIEF::assembly::x86::OPCODE::VSCALEFSSZrrb_Int) + .value("VSCALEFSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VSCALEFSSZrrbk_Int) + .value("VSCALEFSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSCALEFSSZrrbkz_Int) + .value("VSCALEFSSZrrk", LIEF::assembly::x86::OPCODE::VSCALEFSSZrrk) + .value("VSCALEFSSZrrkz", LIEF::assembly::x86::OPCODE::VSCALEFSSZrrkz) + .value("VSCATTERDPDZ128mr", LIEF::assembly::x86::OPCODE::VSCATTERDPDZ128mr) + .value("VSCATTERDPDZ256mr", LIEF::assembly::x86::OPCODE::VSCATTERDPDZ256mr) + .value("VSCATTERDPDZmr", LIEF::assembly::x86::OPCODE::VSCATTERDPDZmr) + .value("VSCATTERDPSZ128mr", LIEF::assembly::x86::OPCODE::VSCATTERDPSZ128mr) + .value("VSCATTERDPSZ256mr", LIEF::assembly::x86::OPCODE::VSCATTERDPSZ256mr) + .value("VSCATTERDPSZmr", LIEF::assembly::x86::OPCODE::VSCATTERDPSZmr) + .value("VSCATTERPF0DPDm", LIEF::assembly::x86::OPCODE::VSCATTERPF0DPDm) + .value("VSCATTERPF0DPSm", LIEF::assembly::x86::OPCODE::VSCATTERPF0DPSm) + .value("VSCATTERPF0QPDm", LIEF::assembly::x86::OPCODE::VSCATTERPF0QPDm) + .value("VSCATTERPF0QPSm", LIEF::assembly::x86::OPCODE::VSCATTERPF0QPSm) + .value("VSCATTERPF1DPDm", LIEF::assembly::x86::OPCODE::VSCATTERPF1DPDm) + .value("VSCATTERPF1DPSm", LIEF::assembly::x86::OPCODE::VSCATTERPF1DPSm) + .value("VSCATTERPF1QPDm", LIEF::assembly::x86::OPCODE::VSCATTERPF1QPDm) + .value("VSCATTERPF1QPSm", LIEF::assembly::x86::OPCODE::VSCATTERPF1QPSm) + .value("VSCATTERQPDZ128mr", LIEF::assembly::x86::OPCODE::VSCATTERQPDZ128mr) + .value("VSCATTERQPDZ256mr", LIEF::assembly::x86::OPCODE::VSCATTERQPDZ256mr) + .value("VSCATTERQPDZmr", LIEF::assembly::x86::OPCODE::VSCATTERQPDZmr) + .value("VSCATTERQPSZ128mr", LIEF::assembly::x86::OPCODE::VSCATTERQPSZ128mr) + .value("VSCATTERQPSZ256mr", LIEF::assembly::x86::OPCODE::VSCATTERQPSZ256mr) + .value("VSCATTERQPSZmr", LIEF::assembly::x86::OPCODE::VSCATTERQPSZmr) + .value("VSHA512MSG1rr", LIEF::assembly::x86::OPCODE::VSHA512MSG1rr) + .value("VSHA512MSG2rr", LIEF::assembly::x86::OPCODE::VSHA512MSG2rr) + .value("VSHA512RNDS2rr", LIEF::assembly::x86::OPCODE::VSHA512RNDS2rr) + .value("VSHUFF32X4Z256rmbi", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmbi) + .value("VSHUFF32X4Z256rmbik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmbik) + .value("VSHUFF32X4Z256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmbikz) + .value("VSHUFF32X4Z256rmi", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmi) + .value("VSHUFF32X4Z256rmik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmik) + .value("VSHUFF32X4Z256rmikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rmikz) + .value("VSHUFF32X4Z256rri", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rri) + .value("VSHUFF32X4Z256rrik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rrik) + .value("VSHUFF32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Z256rrikz) + .value("VSHUFF32X4Zrmbi", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmbi) + .value("VSHUFF32X4Zrmbik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmbik) + .value("VSHUFF32X4Zrmbikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmbikz) + .value("VSHUFF32X4Zrmi", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmi) + .value("VSHUFF32X4Zrmik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmik) + .value("VSHUFF32X4Zrmikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrmikz) + .value("VSHUFF32X4Zrri", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrri) + .value("VSHUFF32X4Zrrik", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrrik) + .value("VSHUFF32X4Zrrikz", LIEF::assembly::x86::OPCODE::VSHUFF32X4Zrrikz) + .value("VSHUFF64X2Z256rmbi", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmbi) + .value("VSHUFF64X2Z256rmbik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmbik) + .value("VSHUFF64X2Z256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmbikz) + .value("VSHUFF64X2Z256rmi", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmi) + .value("VSHUFF64X2Z256rmik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmik) + .value("VSHUFF64X2Z256rmikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rmikz) + .value("VSHUFF64X2Z256rri", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rri) + .value("VSHUFF64X2Z256rrik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rrik) + .value("VSHUFF64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Z256rrikz) + .value("VSHUFF64X2Zrmbi", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmbi) + .value("VSHUFF64X2Zrmbik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmbik) + .value("VSHUFF64X2Zrmbikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmbikz) + .value("VSHUFF64X2Zrmi", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmi) + .value("VSHUFF64X2Zrmik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmik) + .value("VSHUFF64X2Zrmikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrmikz) + .value("VSHUFF64X2Zrri", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrri) + .value("VSHUFF64X2Zrrik", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrrik) + .value("VSHUFF64X2Zrrikz", LIEF::assembly::x86::OPCODE::VSHUFF64X2Zrrikz) + .value("VSHUFI32X4Z256rmbi", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmbi) + .value("VSHUFI32X4Z256rmbik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmbik) + .value("VSHUFI32X4Z256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmbikz) + .value("VSHUFI32X4Z256rmi", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmi) + .value("VSHUFI32X4Z256rmik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmik) + .value("VSHUFI32X4Z256rmikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rmikz) + .value("VSHUFI32X4Z256rri", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rri) + .value("VSHUFI32X4Z256rrik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rrik) + .value("VSHUFI32X4Z256rrikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Z256rrikz) + .value("VSHUFI32X4Zrmbi", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmbi) + .value("VSHUFI32X4Zrmbik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmbik) + .value("VSHUFI32X4Zrmbikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmbikz) + .value("VSHUFI32X4Zrmi", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmi) + .value("VSHUFI32X4Zrmik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmik) + .value("VSHUFI32X4Zrmikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrmikz) + .value("VSHUFI32X4Zrri", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrri) + .value("VSHUFI32X4Zrrik", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrrik) + .value("VSHUFI32X4Zrrikz", LIEF::assembly::x86::OPCODE::VSHUFI32X4Zrrikz) + .value("VSHUFI64X2Z256rmbi", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmbi) + .value("VSHUFI64X2Z256rmbik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmbik) + .value("VSHUFI64X2Z256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmbikz) + .value("VSHUFI64X2Z256rmi", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmi) + .value("VSHUFI64X2Z256rmik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmik) + .value("VSHUFI64X2Z256rmikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rmikz) + .value("VSHUFI64X2Z256rri", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rri) + .value("VSHUFI64X2Z256rrik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rrik) + .value("VSHUFI64X2Z256rrikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Z256rrikz) + .value("VSHUFI64X2Zrmbi", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmbi) + .value("VSHUFI64X2Zrmbik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmbik) + .value("VSHUFI64X2Zrmbikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmbikz) + .value("VSHUFI64X2Zrmi", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmi) + .value("VSHUFI64X2Zrmik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmik) + .value("VSHUFI64X2Zrmikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrmikz) + .value("VSHUFI64X2Zrri", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrri) + .value("VSHUFI64X2Zrrik", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrrik) + .value("VSHUFI64X2Zrrikz", LIEF::assembly::x86::OPCODE::VSHUFI64X2Zrrikz) + .value("VSHUFPDYrmi", LIEF::assembly::x86::OPCODE::VSHUFPDYrmi) + .value("VSHUFPDYrri", LIEF::assembly::x86::OPCODE::VSHUFPDYrri) + .value("VSHUFPDZ128rmbi", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmbi) + .value("VSHUFPDZ128rmbik", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmbik) + .value("VSHUFPDZ128rmbikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmbikz) + .value("VSHUFPDZ128rmi", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmi) + .value("VSHUFPDZ128rmik", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmik) + .value("VSHUFPDZ128rmikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rmikz) + .value("VSHUFPDZ128rri", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rri) + .value("VSHUFPDZ128rrik", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rrik) + .value("VSHUFPDZ128rrikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ128rrikz) + .value("VSHUFPDZ256rmbi", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmbi) + .value("VSHUFPDZ256rmbik", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmbik) + .value("VSHUFPDZ256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmbikz) + .value("VSHUFPDZ256rmi", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmi) + .value("VSHUFPDZ256rmik", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmik) + .value("VSHUFPDZ256rmikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rmikz) + .value("VSHUFPDZ256rri", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rri) + .value("VSHUFPDZ256rrik", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rrik) + .value("VSHUFPDZ256rrikz", LIEF::assembly::x86::OPCODE::VSHUFPDZ256rrikz) + .value("VSHUFPDZrmbi", LIEF::assembly::x86::OPCODE::VSHUFPDZrmbi) + .value("VSHUFPDZrmbik", LIEF::assembly::x86::OPCODE::VSHUFPDZrmbik) + .value("VSHUFPDZrmbikz", LIEF::assembly::x86::OPCODE::VSHUFPDZrmbikz) + .value("VSHUFPDZrmi", LIEF::assembly::x86::OPCODE::VSHUFPDZrmi) + .value("VSHUFPDZrmik", LIEF::assembly::x86::OPCODE::VSHUFPDZrmik) + .value("VSHUFPDZrmikz", LIEF::assembly::x86::OPCODE::VSHUFPDZrmikz) + .value("VSHUFPDZrri", LIEF::assembly::x86::OPCODE::VSHUFPDZrri) + .value("VSHUFPDZrrik", LIEF::assembly::x86::OPCODE::VSHUFPDZrrik) + .value("VSHUFPDZrrikz", LIEF::assembly::x86::OPCODE::VSHUFPDZrrikz) + .value("VSHUFPDrmi", LIEF::assembly::x86::OPCODE::VSHUFPDrmi) + .value("VSHUFPDrri", LIEF::assembly::x86::OPCODE::VSHUFPDrri) + .value("VSHUFPSYrmi", LIEF::assembly::x86::OPCODE::VSHUFPSYrmi) + .value("VSHUFPSYrri", LIEF::assembly::x86::OPCODE::VSHUFPSYrri) + .value("VSHUFPSZ128rmbi", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmbi) + .value("VSHUFPSZ128rmbik", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmbik) + .value("VSHUFPSZ128rmbikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmbikz) + .value("VSHUFPSZ128rmi", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmi) + .value("VSHUFPSZ128rmik", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmik) + .value("VSHUFPSZ128rmikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rmikz) + .value("VSHUFPSZ128rri", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rri) + .value("VSHUFPSZ128rrik", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rrik) + .value("VSHUFPSZ128rrikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ128rrikz) + .value("VSHUFPSZ256rmbi", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmbi) + .value("VSHUFPSZ256rmbik", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmbik) + .value("VSHUFPSZ256rmbikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmbikz) + .value("VSHUFPSZ256rmi", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmi) + .value("VSHUFPSZ256rmik", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmik) + .value("VSHUFPSZ256rmikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rmikz) + .value("VSHUFPSZ256rri", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rri) + .value("VSHUFPSZ256rrik", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rrik) + .value("VSHUFPSZ256rrikz", LIEF::assembly::x86::OPCODE::VSHUFPSZ256rrikz) + .value("VSHUFPSZrmbi", LIEF::assembly::x86::OPCODE::VSHUFPSZrmbi) + .value("VSHUFPSZrmbik", LIEF::assembly::x86::OPCODE::VSHUFPSZrmbik) + .value("VSHUFPSZrmbikz", LIEF::assembly::x86::OPCODE::VSHUFPSZrmbikz) + .value("VSHUFPSZrmi", LIEF::assembly::x86::OPCODE::VSHUFPSZrmi) + .value("VSHUFPSZrmik", LIEF::assembly::x86::OPCODE::VSHUFPSZrmik) + .value("VSHUFPSZrmikz", LIEF::assembly::x86::OPCODE::VSHUFPSZrmikz) + .value("VSHUFPSZrri", LIEF::assembly::x86::OPCODE::VSHUFPSZrri) + .value("VSHUFPSZrrik", LIEF::assembly::x86::OPCODE::VSHUFPSZrrik) + .value("VSHUFPSZrrikz", LIEF::assembly::x86::OPCODE::VSHUFPSZrrikz) + .value("VSHUFPSrmi", LIEF::assembly::x86::OPCODE::VSHUFPSrmi) + .value("VSHUFPSrri", LIEF::assembly::x86::OPCODE::VSHUFPSrri) + .value("VSM3MSG1rm", LIEF::assembly::x86::OPCODE::VSM3MSG1rm) + .value("VSM3MSG1rr", LIEF::assembly::x86::OPCODE::VSM3MSG1rr) + .value("VSM3MSG2rm", LIEF::assembly::x86::OPCODE::VSM3MSG2rm) + .value("VSM3MSG2rr", LIEF::assembly::x86::OPCODE::VSM3MSG2rr) + .value("VSM3RNDS2rmi", LIEF::assembly::x86::OPCODE::VSM3RNDS2rmi) + .value("VSM3RNDS2rri", LIEF::assembly::x86::OPCODE::VSM3RNDS2rri) + .value("VSM4KEY4Yrm", LIEF::assembly::x86::OPCODE::VSM4KEY4Yrm) + .value("VSM4KEY4Yrr", LIEF::assembly::x86::OPCODE::VSM4KEY4Yrr) + .value("VSM4KEY4Z128rm", LIEF::assembly::x86::OPCODE::VSM4KEY4Z128rm) + .value("VSM4KEY4Z128rr", LIEF::assembly::x86::OPCODE::VSM4KEY4Z128rr) + .value("VSM4KEY4Z256rm", LIEF::assembly::x86::OPCODE::VSM4KEY4Z256rm) + .value("VSM4KEY4Z256rr", LIEF::assembly::x86::OPCODE::VSM4KEY4Z256rr) + .value("VSM4KEY4Zrm", LIEF::assembly::x86::OPCODE::VSM4KEY4Zrm) + .value("VSM4KEY4Zrr", LIEF::assembly::x86::OPCODE::VSM4KEY4Zrr) + .value("VSM4KEY4rm", LIEF::assembly::x86::OPCODE::VSM4KEY4rm) + .value("VSM4KEY4rr", LIEF::assembly::x86::OPCODE::VSM4KEY4rr) + .value("VSM4RNDS4Yrm", LIEF::assembly::x86::OPCODE::VSM4RNDS4Yrm) + .value("VSM4RNDS4Yrr", LIEF::assembly::x86::OPCODE::VSM4RNDS4Yrr) + .value("VSM4RNDS4Z128rm", LIEF::assembly::x86::OPCODE::VSM4RNDS4Z128rm) + .value("VSM4RNDS4Z128rr", LIEF::assembly::x86::OPCODE::VSM4RNDS4Z128rr) + .value("VSM4RNDS4Z256rm", LIEF::assembly::x86::OPCODE::VSM4RNDS4Z256rm) + .value("VSM4RNDS4Z256rr", LIEF::assembly::x86::OPCODE::VSM4RNDS4Z256rr) + .value("VSM4RNDS4Zrm", LIEF::assembly::x86::OPCODE::VSM4RNDS4Zrm) + .value("VSM4RNDS4Zrr", LIEF::assembly::x86::OPCODE::VSM4RNDS4Zrr) + .value("VSM4RNDS4rm", LIEF::assembly::x86::OPCODE::VSM4RNDS4rm) + .value("VSM4RNDS4rr", LIEF::assembly::x86::OPCODE::VSM4RNDS4rr) + .value("VSQRTBF16Z128m", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128m) + .value("VSQRTBF16Z128mb", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128mb) + .value("VSQRTBF16Z128mbk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128mbk) + .value("VSQRTBF16Z128mbkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128mbkz) + .value("VSQRTBF16Z128mk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128mk) + .value("VSQRTBF16Z128mkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128mkz) + .value("VSQRTBF16Z128r", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128r) + .value("VSQRTBF16Z128rk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128rk) + .value("VSQRTBF16Z128rkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z128rkz) + .value("VSQRTBF16Z256m", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256m) + .value("VSQRTBF16Z256mb", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256mb) + .value("VSQRTBF16Z256mbk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256mbk) + .value("VSQRTBF16Z256mbkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256mbkz) + .value("VSQRTBF16Z256mk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256mk) + .value("VSQRTBF16Z256mkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256mkz) + .value("VSQRTBF16Z256r", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256r) + .value("VSQRTBF16Z256rk", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256rk) + .value("VSQRTBF16Z256rkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Z256rkz) + .value("VSQRTBF16Zm", LIEF::assembly::x86::OPCODE::VSQRTBF16Zm) + .value("VSQRTBF16Zmb", LIEF::assembly::x86::OPCODE::VSQRTBF16Zmb) + .value("VSQRTBF16Zmbk", LIEF::assembly::x86::OPCODE::VSQRTBF16Zmbk) + .value("VSQRTBF16Zmbkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Zmbkz) + .value("VSQRTBF16Zmk", LIEF::assembly::x86::OPCODE::VSQRTBF16Zmk) + .value("VSQRTBF16Zmkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Zmkz) + .value("VSQRTBF16Zr", LIEF::assembly::x86::OPCODE::VSQRTBF16Zr) + .value("VSQRTBF16Zrk", LIEF::assembly::x86::OPCODE::VSQRTBF16Zrk) + .value("VSQRTBF16Zrkz", LIEF::assembly::x86::OPCODE::VSQRTBF16Zrkz) + .value("VSQRTPDYm", LIEF::assembly::x86::OPCODE::VSQRTPDYm) + .value("VSQRTPDYr", LIEF::assembly::x86::OPCODE::VSQRTPDYr) + .value("VSQRTPDZ128m", LIEF::assembly::x86::OPCODE::VSQRTPDZ128m) + .value("VSQRTPDZ128mb", LIEF::assembly::x86::OPCODE::VSQRTPDZ128mb) + .value("VSQRTPDZ128mbk", LIEF::assembly::x86::OPCODE::VSQRTPDZ128mbk) + .value("VSQRTPDZ128mbkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ128mbkz) + .value("VSQRTPDZ128mk", LIEF::assembly::x86::OPCODE::VSQRTPDZ128mk) + .value("VSQRTPDZ128mkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ128mkz) + .value("VSQRTPDZ128r", LIEF::assembly::x86::OPCODE::VSQRTPDZ128r) + .value("VSQRTPDZ128rk", LIEF::assembly::x86::OPCODE::VSQRTPDZ128rk) + .value("VSQRTPDZ128rkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ128rkz) + .value("VSQRTPDZ256m", LIEF::assembly::x86::OPCODE::VSQRTPDZ256m) + .value("VSQRTPDZ256mb", LIEF::assembly::x86::OPCODE::VSQRTPDZ256mb) + .value("VSQRTPDZ256mbk", LIEF::assembly::x86::OPCODE::VSQRTPDZ256mbk) + .value("VSQRTPDZ256mbkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ256mbkz) + .value("VSQRTPDZ256mk", LIEF::assembly::x86::OPCODE::VSQRTPDZ256mk) + .value("VSQRTPDZ256mkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ256mkz) + .value("VSQRTPDZ256r", LIEF::assembly::x86::OPCODE::VSQRTPDZ256r) + .value("VSQRTPDZ256rk", LIEF::assembly::x86::OPCODE::VSQRTPDZ256rk) + .value("VSQRTPDZ256rkz", LIEF::assembly::x86::OPCODE::VSQRTPDZ256rkz) + .value("VSQRTPDZm", LIEF::assembly::x86::OPCODE::VSQRTPDZm) + .value("VSQRTPDZmb", LIEF::assembly::x86::OPCODE::VSQRTPDZmb) + .value("VSQRTPDZmbk", LIEF::assembly::x86::OPCODE::VSQRTPDZmbk) + .value("VSQRTPDZmbkz", LIEF::assembly::x86::OPCODE::VSQRTPDZmbkz) + .value("VSQRTPDZmk", LIEF::assembly::x86::OPCODE::VSQRTPDZmk) + .value("VSQRTPDZmkz", LIEF::assembly::x86::OPCODE::VSQRTPDZmkz) + .value("VSQRTPDZr", LIEF::assembly::x86::OPCODE::VSQRTPDZr) + .value("VSQRTPDZrb", LIEF::assembly::x86::OPCODE::VSQRTPDZrb) + .value("VSQRTPDZrbk", LIEF::assembly::x86::OPCODE::VSQRTPDZrbk) + .value("VSQRTPDZrbkz", LIEF::assembly::x86::OPCODE::VSQRTPDZrbkz) + .value("VSQRTPDZrk", LIEF::assembly::x86::OPCODE::VSQRTPDZrk) + .value("VSQRTPDZrkz", LIEF::assembly::x86::OPCODE::VSQRTPDZrkz) + .value("VSQRTPDm", LIEF::assembly::x86::OPCODE::VSQRTPDm) + .value("VSQRTPDr", LIEF::assembly::x86::OPCODE::VSQRTPDr) + .value("VSQRTPHZ128m", LIEF::assembly::x86::OPCODE::VSQRTPHZ128m) + .value("VSQRTPHZ128mb", LIEF::assembly::x86::OPCODE::VSQRTPHZ128mb) + .value("VSQRTPHZ128mbk", LIEF::assembly::x86::OPCODE::VSQRTPHZ128mbk) + .value("VSQRTPHZ128mbkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ128mbkz) + .value("VSQRTPHZ128mk", LIEF::assembly::x86::OPCODE::VSQRTPHZ128mk) + .value("VSQRTPHZ128mkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ128mkz) + .value("VSQRTPHZ128r", LIEF::assembly::x86::OPCODE::VSQRTPHZ128r) + .value("VSQRTPHZ128rk", LIEF::assembly::x86::OPCODE::VSQRTPHZ128rk) + .value("VSQRTPHZ128rkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ128rkz) + .value("VSQRTPHZ256m", LIEF::assembly::x86::OPCODE::VSQRTPHZ256m) + .value("VSQRTPHZ256mb", LIEF::assembly::x86::OPCODE::VSQRTPHZ256mb) + .value("VSQRTPHZ256mbk", LIEF::assembly::x86::OPCODE::VSQRTPHZ256mbk) + .value("VSQRTPHZ256mbkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ256mbkz) + .value("VSQRTPHZ256mk", LIEF::assembly::x86::OPCODE::VSQRTPHZ256mk) + .value("VSQRTPHZ256mkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ256mkz) + .value("VSQRTPHZ256r", LIEF::assembly::x86::OPCODE::VSQRTPHZ256r) + .value("VSQRTPHZ256rk", LIEF::assembly::x86::OPCODE::VSQRTPHZ256rk) + .value("VSQRTPHZ256rkz", LIEF::assembly::x86::OPCODE::VSQRTPHZ256rkz) + .value("VSQRTPHZm", LIEF::assembly::x86::OPCODE::VSQRTPHZm) + .value("VSQRTPHZmb", LIEF::assembly::x86::OPCODE::VSQRTPHZmb) + .value("VSQRTPHZmbk", LIEF::assembly::x86::OPCODE::VSQRTPHZmbk) + .value("VSQRTPHZmbkz", LIEF::assembly::x86::OPCODE::VSQRTPHZmbkz) + .value("VSQRTPHZmk", LIEF::assembly::x86::OPCODE::VSQRTPHZmk) + .value("VSQRTPHZmkz", LIEF::assembly::x86::OPCODE::VSQRTPHZmkz) + .value("VSQRTPHZr", LIEF::assembly::x86::OPCODE::VSQRTPHZr) + .value("VSQRTPHZrb", LIEF::assembly::x86::OPCODE::VSQRTPHZrb) + .value("VSQRTPHZrbk", LIEF::assembly::x86::OPCODE::VSQRTPHZrbk) + .value("VSQRTPHZrbkz", LIEF::assembly::x86::OPCODE::VSQRTPHZrbkz) + .value("VSQRTPHZrk", LIEF::assembly::x86::OPCODE::VSQRTPHZrk) + .value("VSQRTPHZrkz", LIEF::assembly::x86::OPCODE::VSQRTPHZrkz) + .value("VSQRTPSYm", LIEF::assembly::x86::OPCODE::VSQRTPSYm) + .value("VSQRTPSYr", LIEF::assembly::x86::OPCODE::VSQRTPSYr) + .value("VSQRTPSZ128m", LIEF::assembly::x86::OPCODE::VSQRTPSZ128m) + .value("VSQRTPSZ128mb", LIEF::assembly::x86::OPCODE::VSQRTPSZ128mb) + .value("VSQRTPSZ128mbk", LIEF::assembly::x86::OPCODE::VSQRTPSZ128mbk) + .value("VSQRTPSZ128mbkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ128mbkz) + .value("VSQRTPSZ128mk", LIEF::assembly::x86::OPCODE::VSQRTPSZ128mk) + .value("VSQRTPSZ128mkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ128mkz) + .value("VSQRTPSZ128r", LIEF::assembly::x86::OPCODE::VSQRTPSZ128r) + .value("VSQRTPSZ128rk", LIEF::assembly::x86::OPCODE::VSQRTPSZ128rk) + .value("VSQRTPSZ128rkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ128rkz) + .value("VSQRTPSZ256m", LIEF::assembly::x86::OPCODE::VSQRTPSZ256m) + .value("VSQRTPSZ256mb", LIEF::assembly::x86::OPCODE::VSQRTPSZ256mb) + .value("VSQRTPSZ256mbk", LIEF::assembly::x86::OPCODE::VSQRTPSZ256mbk) + .value("VSQRTPSZ256mbkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ256mbkz) + .value("VSQRTPSZ256mk", LIEF::assembly::x86::OPCODE::VSQRTPSZ256mk) + .value("VSQRTPSZ256mkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ256mkz) + .value("VSQRTPSZ256r", LIEF::assembly::x86::OPCODE::VSQRTPSZ256r) + .value("VSQRTPSZ256rk", LIEF::assembly::x86::OPCODE::VSQRTPSZ256rk) + .value("VSQRTPSZ256rkz", LIEF::assembly::x86::OPCODE::VSQRTPSZ256rkz); + opcodes.value("VSQRTPSZm", LIEF::assembly::x86::OPCODE::VSQRTPSZm) + .value("VSQRTPSZmb", LIEF::assembly::x86::OPCODE::VSQRTPSZmb) + .value("VSQRTPSZmbk", LIEF::assembly::x86::OPCODE::VSQRTPSZmbk) + .value("VSQRTPSZmbkz", LIEF::assembly::x86::OPCODE::VSQRTPSZmbkz) + .value("VSQRTPSZmk", LIEF::assembly::x86::OPCODE::VSQRTPSZmk) + .value("VSQRTPSZmkz", LIEF::assembly::x86::OPCODE::VSQRTPSZmkz) + .value("VSQRTPSZr", LIEF::assembly::x86::OPCODE::VSQRTPSZr) + .value("VSQRTPSZrb", LIEF::assembly::x86::OPCODE::VSQRTPSZrb) + .value("VSQRTPSZrbk", LIEF::assembly::x86::OPCODE::VSQRTPSZrbk) + .value("VSQRTPSZrbkz", LIEF::assembly::x86::OPCODE::VSQRTPSZrbkz) + .value("VSQRTPSZrk", LIEF::assembly::x86::OPCODE::VSQRTPSZrk) + .value("VSQRTPSZrkz", LIEF::assembly::x86::OPCODE::VSQRTPSZrkz) + .value("VSQRTPSm", LIEF::assembly::x86::OPCODE::VSQRTPSm) + .value("VSQRTPSr", LIEF::assembly::x86::OPCODE::VSQRTPSr) + .value("VSQRTSDZm", LIEF::assembly::x86::OPCODE::VSQRTSDZm) + .value("VSQRTSDZm_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZm_Int) + .value("VSQRTSDZmk_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZmk_Int) + .value("VSQRTSDZmkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZmkz_Int) + .value("VSQRTSDZr", LIEF::assembly::x86::OPCODE::VSQRTSDZr) + .value("VSQRTSDZr_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZr_Int) + .value("VSQRTSDZrb_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZrb_Int) + .value("VSQRTSDZrbk_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZrbk_Int) + .value("VSQRTSDZrbkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZrbkz_Int) + .value("VSQRTSDZrk_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZrk_Int) + .value("VSQRTSDZrkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSDZrkz_Int) + .value("VSQRTSDm", LIEF::assembly::x86::OPCODE::VSQRTSDm) + .value("VSQRTSDm_Int", LIEF::assembly::x86::OPCODE::VSQRTSDm_Int) + .value("VSQRTSDr", LIEF::assembly::x86::OPCODE::VSQRTSDr) + .value("VSQRTSDr_Int", LIEF::assembly::x86::OPCODE::VSQRTSDr_Int) + .value("VSQRTSHZm", LIEF::assembly::x86::OPCODE::VSQRTSHZm) + .value("VSQRTSHZm_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZm_Int) + .value("VSQRTSHZmk_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZmk_Int) + .value("VSQRTSHZmkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZmkz_Int) + .value("VSQRTSHZr", LIEF::assembly::x86::OPCODE::VSQRTSHZr) + .value("VSQRTSHZr_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZr_Int) + .value("VSQRTSHZrb_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZrb_Int) + .value("VSQRTSHZrbk_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZrbk_Int) + .value("VSQRTSHZrbkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZrbkz_Int) + .value("VSQRTSHZrk_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZrk_Int) + .value("VSQRTSHZrkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSHZrkz_Int) + .value("VSQRTSSZm", LIEF::assembly::x86::OPCODE::VSQRTSSZm) + .value("VSQRTSSZm_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZm_Int) + .value("VSQRTSSZmk_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZmk_Int) + .value("VSQRTSSZmkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZmkz_Int) + .value("VSQRTSSZr", LIEF::assembly::x86::OPCODE::VSQRTSSZr) + .value("VSQRTSSZr_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZr_Int) + .value("VSQRTSSZrb_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZrb_Int) + .value("VSQRTSSZrbk_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZrbk_Int) + .value("VSQRTSSZrbkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZrbkz_Int) + .value("VSQRTSSZrk_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZrk_Int) + .value("VSQRTSSZrkz_Int", LIEF::assembly::x86::OPCODE::VSQRTSSZrkz_Int) + .value("VSQRTSSm", LIEF::assembly::x86::OPCODE::VSQRTSSm) + .value("VSQRTSSm_Int", LIEF::assembly::x86::OPCODE::VSQRTSSm_Int) + .value("VSQRTSSr", LIEF::assembly::x86::OPCODE::VSQRTSSr) + .value("VSQRTSSr_Int", LIEF::assembly::x86::OPCODE::VSQRTSSr_Int) + .value("VSTMXCSR", LIEF::assembly::x86::OPCODE::VSTMXCSR) + .value("VSUBBF16Z128rm", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rm) + .value("VSUBBF16Z128rmb", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rmb) + .value("VSUBBF16Z128rmbk", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rmbk) + .value("VSUBBF16Z128rmbkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rmbkz) + .value("VSUBBF16Z128rmk", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rmk) + .value("VSUBBF16Z128rmkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rmkz) + .value("VSUBBF16Z128rr", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rr) + .value("VSUBBF16Z128rrk", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rrk) + .value("VSUBBF16Z128rrkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z128rrkz) + .value("VSUBBF16Z256rm", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rm) + .value("VSUBBF16Z256rmb", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rmb) + .value("VSUBBF16Z256rmbk", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rmbk) + .value("VSUBBF16Z256rmbkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rmbkz) + .value("VSUBBF16Z256rmk", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rmk) + .value("VSUBBF16Z256rmkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rmkz) + .value("VSUBBF16Z256rr", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rr) + .value("VSUBBF16Z256rrk", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rrk) + .value("VSUBBF16Z256rrkz", LIEF::assembly::x86::OPCODE::VSUBBF16Z256rrkz) + .value("VSUBBF16Zrm", LIEF::assembly::x86::OPCODE::VSUBBF16Zrm) + .value("VSUBBF16Zrmb", LIEF::assembly::x86::OPCODE::VSUBBF16Zrmb) + .value("VSUBBF16Zrmbk", LIEF::assembly::x86::OPCODE::VSUBBF16Zrmbk) + .value("VSUBBF16Zrmbkz", LIEF::assembly::x86::OPCODE::VSUBBF16Zrmbkz) + .value("VSUBBF16Zrmk", LIEF::assembly::x86::OPCODE::VSUBBF16Zrmk) + .value("VSUBBF16Zrmkz", LIEF::assembly::x86::OPCODE::VSUBBF16Zrmkz) + .value("VSUBBF16Zrr", LIEF::assembly::x86::OPCODE::VSUBBF16Zrr) + .value("VSUBBF16Zrrk", LIEF::assembly::x86::OPCODE::VSUBBF16Zrrk) + .value("VSUBBF16Zrrkz", LIEF::assembly::x86::OPCODE::VSUBBF16Zrrkz) + .value("VSUBPDYrm", LIEF::assembly::x86::OPCODE::VSUBPDYrm) + .value("VSUBPDYrr", LIEF::assembly::x86::OPCODE::VSUBPDYrr) + .value("VSUBPDZ128rm", LIEF::assembly::x86::OPCODE::VSUBPDZ128rm) + .value("VSUBPDZ128rmb", LIEF::assembly::x86::OPCODE::VSUBPDZ128rmb) + .value("VSUBPDZ128rmbk", LIEF::assembly::x86::OPCODE::VSUBPDZ128rmbk) + .value("VSUBPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VSUBPDZ128rmbkz) + .value("VSUBPDZ128rmk", LIEF::assembly::x86::OPCODE::VSUBPDZ128rmk) + .value("VSUBPDZ128rmkz", LIEF::assembly::x86::OPCODE::VSUBPDZ128rmkz) + .value("VSUBPDZ128rr", LIEF::assembly::x86::OPCODE::VSUBPDZ128rr) + .value("VSUBPDZ128rrk", LIEF::assembly::x86::OPCODE::VSUBPDZ128rrk) + .value("VSUBPDZ128rrkz", LIEF::assembly::x86::OPCODE::VSUBPDZ128rrkz) + .value("VSUBPDZ256rm", LIEF::assembly::x86::OPCODE::VSUBPDZ256rm) + .value("VSUBPDZ256rmb", LIEF::assembly::x86::OPCODE::VSUBPDZ256rmb) + .value("VSUBPDZ256rmbk", LIEF::assembly::x86::OPCODE::VSUBPDZ256rmbk) + .value("VSUBPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VSUBPDZ256rmbkz) + .value("VSUBPDZ256rmk", LIEF::assembly::x86::OPCODE::VSUBPDZ256rmk) + .value("VSUBPDZ256rmkz", LIEF::assembly::x86::OPCODE::VSUBPDZ256rmkz) + .value("VSUBPDZ256rr", LIEF::assembly::x86::OPCODE::VSUBPDZ256rr) + .value("VSUBPDZ256rrk", LIEF::assembly::x86::OPCODE::VSUBPDZ256rrk) + .value("VSUBPDZ256rrkz", LIEF::assembly::x86::OPCODE::VSUBPDZ256rrkz) + .value("VSUBPDZrm", LIEF::assembly::x86::OPCODE::VSUBPDZrm) + .value("VSUBPDZrmb", LIEF::assembly::x86::OPCODE::VSUBPDZrmb) + .value("VSUBPDZrmbk", LIEF::assembly::x86::OPCODE::VSUBPDZrmbk) + .value("VSUBPDZrmbkz", LIEF::assembly::x86::OPCODE::VSUBPDZrmbkz) + .value("VSUBPDZrmk", LIEF::assembly::x86::OPCODE::VSUBPDZrmk) + .value("VSUBPDZrmkz", LIEF::assembly::x86::OPCODE::VSUBPDZrmkz) + .value("VSUBPDZrr", LIEF::assembly::x86::OPCODE::VSUBPDZrr) + .value("VSUBPDZrrb", LIEF::assembly::x86::OPCODE::VSUBPDZrrb) + .value("VSUBPDZrrbk", LIEF::assembly::x86::OPCODE::VSUBPDZrrbk) + .value("VSUBPDZrrbkz", LIEF::assembly::x86::OPCODE::VSUBPDZrrbkz) + .value("VSUBPDZrrk", LIEF::assembly::x86::OPCODE::VSUBPDZrrk) + .value("VSUBPDZrrkz", LIEF::assembly::x86::OPCODE::VSUBPDZrrkz) + .value("VSUBPDrm", LIEF::assembly::x86::OPCODE::VSUBPDrm) + .value("VSUBPDrr", LIEF::assembly::x86::OPCODE::VSUBPDrr) + .value("VSUBPHZ128rm", LIEF::assembly::x86::OPCODE::VSUBPHZ128rm) + .value("VSUBPHZ128rmb", LIEF::assembly::x86::OPCODE::VSUBPHZ128rmb) + .value("VSUBPHZ128rmbk", LIEF::assembly::x86::OPCODE::VSUBPHZ128rmbk) + .value("VSUBPHZ128rmbkz", LIEF::assembly::x86::OPCODE::VSUBPHZ128rmbkz) + .value("VSUBPHZ128rmk", LIEF::assembly::x86::OPCODE::VSUBPHZ128rmk) + .value("VSUBPHZ128rmkz", LIEF::assembly::x86::OPCODE::VSUBPHZ128rmkz) + .value("VSUBPHZ128rr", LIEF::assembly::x86::OPCODE::VSUBPHZ128rr) + .value("VSUBPHZ128rrk", LIEF::assembly::x86::OPCODE::VSUBPHZ128rrk) + .value("VSUBPHZ128rrkz", LIEF::assembly::x86::OPCODE::VSUBPHZ128rrkz) + .value("VSUBPHZ256rm", LIEF::assembly::x86::OPCODE::VSUBPHZ256rm) + .value("VSUBPHZ256rmb", LIEF::assembly::x86::OPCODE::VSUBPHZ256rmb) + .value("VSUBPHZ256rmbk", LIEF::assembly::x86::OPCODE::VSUBPHZ256rmbk) + .value("VSUBPHZ256rmbkz", LIEF::assembly::x86::OPCODE::VSUBPHZ256rmbkz) + .value("VSUBPHZ256rmk", LIEF::assembly::x86::OPCODE::VSUBPHZ256rmk) + .value("VSUBPHZ256rmkz", LIEF::assembly::x86::OPCODE::VSUBPHZ256rmkz) + .value("VSUBPHZ256rr", LIEF::assembly::x86::OPCODE::VSUBPHZ256rr) + .value("VSUBPHZ256rrk", LIEF::assembly::x86::OPCODE::VSUBPHZ256rrk) + .value("VSUBPHZ256rrkz", LIEF::assembly::x86::OPCODE::VSUBPHZ256rrkz) + .value("VSUBPHZrm", LIEF::assembly::x86::OPCODE::VSUBPHZrm) + .value("VSUBPHZrmb", LIEF::assembly::x86::OPCODE::VSUBPHZrmb) + .value("VSUBPHZrmbk", LIEF::assembly::x86::OPCODE::VSUBPHZrmbk) + .value("VSUBPHZrmbkz", LIEF::assembly::x86::OPCODE::VSUBPHZrmbkz) + .value("VSUBPHZrmk", LIEF::assembly::x86::OPCODE::VSUBPHZrmk) + .value("VSUBPHZrmkz", LIEF::assembly::x86::OPCODE::VSUBPHZrmkz) + .value("VSUBPHZrr", LIEF::assembly::x86::OPCODE::VSUBPHZrr) + .value("VSUBPHZrrb", LIEF::assembly::x86::OPCODE::VSUBPHZrrb) + .value("VSUBPHZrrbk", LIEF::assembly::x86::OPCODE::VSUBPHZrrbk) + .value("VSUBPHZrrbkz", LIEF::assembly::x86::OPCODE::VSUBPHZrrbkz) + .value("VSUBPHZrrk", LIEF::assembly::x86::OPCODE::VSUBPHZrrk) + .value("VSUBPHZrrkz", LIEF::assembly::x86::OPCODE::VSUBPHZrrkz) + .value("VSUBPSYrm", LIEF::assembly::x86::OPCODE::VSUBPSYrm) + .value("VSUBPSYrr", LIEF::assembly::x86::OPCODE::VSUBPSYrr) + .value("VSUBPSZ128rm", LIEF::assembly::x86::OPCODE::VSUBPSZ128rm) + .value("VSUBPSZ128rmb", LIEF::assembly::x86::OPCODE::VSUBPSZ128rmb) + .value("VSUBPSZ128rmbk", LIEF::assembly::x86::OPCODE::VSUBPSZ128rmbk) + .value("VSUBPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VSUBPSZ128rmbkz) + .value("VSUBPSZ128rmk", LIEF::assembly::x86::OPCODE::VSUBPSZ128rmk) + .value("VSUBPSZ128rmkz", LIEF::assembly::x86::OPCODE::VSUBPSZ128rmkz) + .value("VSUBPSZ128rr", LIEF::assembly::x86::OPCODE::VSUBPSZ128rr) + .value("VSUBPSZ128rrk", LIEF::assembly::x86::OPCODE::VSUBPSZ128rrk) + .value("VSUBPSZ128rrkz", LIEF::assembly::x86::OPCODE::VSUBPSZ128rrkz) + .value("VSUBPSZ256rm", LIEF::assembly::x86::OPCODE::VSUBPSZ256rm) + .value("VSUBPSZ256rmb", LIEF::assembly::x86::OPCODE::VSUBPSZ256rmb) + .value("VSUBPSZ256rmbk", LIEF::assembly::x86::OPCODE::VSUBPSZ256rmbk) + .value("VSUBPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VSUBPSZ256rmbkz) + .value("VSUBPSZ256rmk", LIEF::assembly::x86::OPCODE::VSUBPSZ256rmk) + .value("VSUBPSZ256rmkz", LIEF::assembly::x86::OPCODE::VSUBPSZ256rmkz) + .value("VSUBPSZ256rr", LIEF::assembly::x86::OPCODE::VSUBPSZ256rr) + .value("VSUBPSZ256rrk", LIEF::assembly::x86::OPCODE::VSUBPSZ256rrk) + .value("VSUBPSZ256rrkz", LIEF::assembly::x86::OPCODE::VSUBPSZ256rrkz) + .value("VSUBPSZrm", LIEF::assembly::x86::OPCODE::VSUBPSZrm) + .value("VSUBPSZrmb", LIEF::assembly::x86::OPCODE::VSUBPSZrmb) + .value("VSUBPSZrmbk", LIEF::assembly::x86::OPCODE::VSUBPSZrmbk) + .value("VSUBPSZrmbkz", LIEF::assembly::x86::OPCODE::VSUBPSZrmbkz) + .value("VSUBPSZrmk", LIEF::assembly::x86::OPCODE::VSUBPSZrmk) + .value("VSUBPSZrmkz", LIEF::assembly::x86::OPCODE::VSUBPSZrmkz) + .value("VSUBPSZrr", LIEF::assembly::x86::OPCODE::VSUBPSZrr) + .value("VSUBPSZrrb", LIEF::assembly::x86::OPCODE::VSUBPSZrrb) + .value("VSUBPSZrrbk", LIEF::assembly::x86::OPCODE::VSUBPSZrrbk) + .value("VSUBPSZrrbkz", LIEF::assembly::x86::OPCODE::VSUBPSZrrbkz) + .value("VSUBPSZrrk", LIEF::assembly::x86::OPCODE::VSUBPSZrrk) + .value("VSUBPSZrrkz", LIEF::assembly::x86::OPCODE::VSUBPSZrrkz) + .value("VSUBPSrm", LIEF::assembly::x86::OPCODE::VSUBPSrm) + .value("VSUBPSrr", LIEF::assembly::x86::OPCODE::VSUBPSrr) + .value("VSUBSDZrm", LIEF::assembly::x86::OPCODE::VSUBSDZrm) + .value("VSUBSDZrm_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrm_Int) + .value("VSUBSDZrmk_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrmk_Int) + .value("VSUBSDZrmkz_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrmkz_Int) + .value("VSUBSDZrr", LIEF::assembly::x86::OPCODE::VSUBSDZrr) + .value("VSUBSDZrr_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrr_Int) + .value("VSUBSDZrrb_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrrb_Int) + .value("VSUBSDZrrbk_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrrbk_Int) + .value("VSUBSDZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrrbkz_Int) + .value("VSUBSDZrrk_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrrk_Int) + .value("VSUBSDZrrkz_Int", LIEF::assembly::x86::OPCODE::VSUBSDZrrkz_Int) + .value("VSUBSDrm", LIEF::assembly::x86::OPCODE::VSUBSDrm) + .value("VSUBSDrm_Int", LIEF::assembly::x86::OPCODE::VSUBSDrm_Int) + .value("VSUBSDrr", LIEF::assembly::x86::OPCODE::VSUBSDrr) + .value("VSUBSDrr_Int", LIEF::assembly::x86::OPCODE::VSUBSDrr_Int) + .value("VSUBSHZrm", LIEF::assembly::x86::OPCODE::VSUBSHZrm) + .value("VSUBSHZrm_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrm_Int) + .value("VSUBSHZrmk_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrmk_Int) + .value("VSUBSHZrmkz_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrmkz_Int) + .value("VSUBSHZrr", LIEF::assembly::x86::OPCODE::VSUBSHZrr) + .value("VSUBSHZrr_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrr_Int) + .value("VSUBSHZrrb_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrrb_Int) + .value("VSUBSHZrrbk_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrrbk_Int) + .value("VSUBSHZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrrbkz_Int) + .value("VSUBSHZrrk_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrrk_Int) + .value("VSUBSHZrrkz_Int", LIEF::assembly::x86::OPCODE::VSUBSHZrrkz_Int) + .value("VSUBSSZrm", LIEF::assembly::x86::OPCODE::VSUBSSZrm) + .value("VSUBSSZrm_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrm_Int) + .value("VSUBSSZrmk_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrmk_Int) + .value("VSUBSSZrmkz_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrmkz_Int) + .value("VSUBSSZrr", LIEF::assembly::x86::OPCODE::VSUBSSZrr) + .value("VSUBSSZrr_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrr_Int) + .value("VSUBSSZrrb_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrrb_Int) + .value("VSUBSSZrrbk_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrrbk_Int) + .value("VSUBSSZrrbkz_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrrbkz_Int) + .value("VSUBSSZrrk_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrrk_Int) + .value("VSUBSSZrrkz_Int", LIEF::assembly::x86::OPCODE::VSUBSSZrrkz_Int) + .value("VSUBSSrm", LIEF::assembly::x86::OPCODE::VSUBSSrm) + .value("VSUBSSrm_Int", LIEF::assembly::x86::OPCODE::VSUBSSrm_Int) + .value("VSUBSSrr", LIEF::assembly::x86::OPCODE::VSUBSSrr) + .value("VSUBSSrr_Int", LIEF::assembly::x86::OPCODE::VSUBSSrr_Int) + .value("VTESTPDYrm", LIEF::assembly::x86::OPCODE::VTESTPDYrm) + .value("VTESTPDYrr", LIEF::assembly::x86::OPCODE::VTESTPDYrr) + .value("VTESTPDrm", LIEF::assembly::x86::OPCODE::VTESTPDrm) + .value("VTESTPDrr", LIEF::assembly::x86::OPCODE::VTESTPDrr) + .value("VTESTPSYrm", LIEF::assembly::x86::OPCODE::VTESTPSYrm) + .value("VTESTPSYrr", LIEF::assembly::x86::OPCODE::VTESTPSYrr) + .value("VTESTPSrm", LIEF::assembly::x86::OPCODE::VTESTPSrm) + .value("VTESTPSrr", LIEF::assembly::x86::OPCODE::VTESTPSrr) + .value("VUCOMISDZrm", LIEF::assembly::x86::OPCODE::VUCOMISDZrm) + .value("VUCOMISDZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMISDZrm_Int) + .value("VUCOMISDZrr", LIEF::assembly::x86::OPCODE::VUCOMISDZrr) + .value("VUCOMISDZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMISDZrr_Int) + .value("VUCOMISDZrrb", LIEF::assembly::x86::OPCODE::VUCOMISDZrrb) + .value("VUCOMISDrm", LIEF::assembly::x86::OPCODE::VUCOMISDrm) + .value("VUCOMISDrm_Int", LIEF::assembly::x86::OPCODE::VUCOMISDrm_Int) + .value("VUCOMISDrr", LIEF::assembly::x86::OPCODE::VUCOMISDrr) + .value("VUCOMISDrr_Int", LIEF::assembly::x86::OPCODE::VUCOMISDrr_Int) + .value("VUCOMISHZrm", LIEF::assembly::x86::OPCODE::VUCOMISHZrm) + .value("VUCOMISHZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMISHZrm_Int) + .value("VUCOMISHZrr", LIEF::assembly::x86::OPCODE::VUCOMISHZrr) + .value("VUCOMISHZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMISHZrr_Int) + .value("VUCOMISHZrrb", LIEF::assembly::x86::OPCODE::VUCOMISHZrrb) + .value("VUCOMISSZrm", LIEF::assembly::x86::OPCODE::VUCOMISSZrm) + .value("VUCOMISSZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMISSZrm_Int) + .value("VUCOMISSZrr", LIEF::assembly::x86::OPCODE::VUCOMISSZrr) + .value("VUCOMISSZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMISSZrr_Int) + .value("VUCOMISSZrrb", LIEF::assembly::x86::OPCODE::VUCOMISSZrrb) + .value("VUCOMISSrm", LIEF::assembly::x86::OPCODE::VUCOMISSrm) + .value("VUCOMISSrm_Int", LIEF::assembly::x86::OPCODE::VUCOMISSrm_Int) + .value("VUCOMISSrr", LIEF::assembly::x86::OPCODE::VUCOMISSrr) + .value("VUCOMISSrr_Int", LIEF::assembly::x86::OPCODE::VUCOMISSrr_Int) + .value("VUCOMXSDZrm", LIEF::assembly::x86::OPCODE::VUCOMXSDZrm) + .value("VUCOMXSDZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMXSDZrm_Int) + .value("VUCOMXSDZrr", LIEF::assembly::x86::OPCODE::VUCOMXSDZrr) + .value("VUCOMXSDZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMXSDZrr_Int) + .value("VUCOMXSDZrrb_Int", LIEF::assembly::x86::OPCODE::VUCOMXSDZrrb_Int) + .value("VUCOMXSHZrm", LIEF::assembly::x86::OPCODE::VUCOMXSHZrm) + .value("VUCOMXSHZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMXSHZrm_Int) + .value("VUCOMXSHZrr", LIEF::assembly::x86::OPCODE::VUCOMXSHZrr) + .value("VUCOMXSHZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMXSHZrr_Int) + .value("VUCOMXSHZrrb_Int", LIEF::assembly::x86::OPCODE::VUCOMXSHZrrb_Int) + .value("VUCOMXSSZrm", LIEF::assembly::x86::OPCODE::VUCOMXSSZrm) + .value("VUCOMXSSZrm_Int", LIEF::assembly::x86::OPCODE::VUCOMXSSZrm_Int) + .value("VUCOMXSSZrr", LIEF::assembly::x86::OPCODE::VUCOMXSSZrr) + .value("VUCOMXSSZrr_Int", LIEF::assembly::x86::OPCODE::VUCOMXSSZrr_Int) + .value("VUCOMXSSZrrb_Int", LIEF::assembly::x86::OPCODE::VUCOMXSSZrrb_Int) + .value("VUNPCKHPDYrm", LIEF::assembly::x86::OPCODE::VUNPCKHPDYrm) + .value("VUNPCKHPDYrr", LIEF::assembly::x86::OPCODE::VUNPCKHPDYrr) + .value("VUNPCKHPDZ128rm", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rm) + .value("VUNPCKHPDZ128rmb", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rmb) + .value("VUNPCKHPDZ128rmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rmbk) + .value("VUNPCKHPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rmbkz) + .value("VUNPCKHPDZ128rmk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rmk) + .value("VUNPCKHPDZ128rmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rmkz) + .value("VUNPCKHPDZ128rr", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rr) + .value("VUNPCKHPDZ128rrk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rrk) + .value("VUNPCKHPDZ128rrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ128rrkz) + .value("VUNPCKHPDZ256rm", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rm) + .value("VUNPCKHPDZ256rmb", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rmb) + .value("VUNPCKHPDZ256rmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rmbk) + .value("VUNPCKHPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rmbkz) + .value("VUNPCKHPDZ256rmk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rmk) + .value("VUNPCKHPDZ256rmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rmkz) + .value("VUNPCKHPDZ256rr", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rr) + .value("VUNPCKHPDZ256rrk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rrk) + .value("VUNPCKHPDZ256rrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZ256rrkz) + .value("VUNPCKHPDZrm", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrm) + .value("VUNPCKHPDZrmb", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrmb) + .value("VUNPCKHPDZrmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrmbk) + .value("VUNPCKHPDZrmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrmbkz) + .value("VUNPCKHPDZrmk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrmk) + .value("VUNPCKHPDZrmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrmkz) + .value("VUNPCKHPDZrr", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrr) + .value("VUNPCKHPDZrrk", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrrk) + .value("VUNPCKHPDZrrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPDZrrkz) + .value("VUNPCKHPDrm", LIEF::assembly::x86::OPCODE::VUNPCKHPDrm) + .value("VUNPCKHPDrr", LIEF::assembly::x86::OPCODE::VUNPCKHPDrr) + .value("VUNPCKHPSYrm", LIEF::assembly::x86::OPCODE::VUNPCKHPSYrm); + opcodes.value("VUNPCKHPSYrr", LIEF::assembly::x86::OPCODE::VUNPCKHPSYrr) + .value("VUNPCKHPSZ128rm", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rm) + .value("VUNPCKHPSZ128rmb", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rmb) + .value("VUNPCKHPSZ128rmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rmbk) + .value("VUNPCKHPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rmbkz) + .value("VUNPCKHPSZ128rmk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rmk) + .value("VUNPCKHPSZ128rmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rmkz) + .value("VUNPCKHPSZ128rr", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rr) + .value("VUNPCKHPSZ128rrk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rrk) + .value("VUNPCKHPSZ128rrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ128rrkz) + .value("VUNPCKHPSZ256rm", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rm) + .value("VUNPCKHPSZ256rmb", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rmb) + .value("VUNPCKHPSZ256rmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rmbk) + .value("VUNPCKHPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rmbkz) + .value("VUNPCKHPSZ256rmk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rmk) + .value("VUNPCKHPSZ256rmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rmkz) + .value("VUNPCKHPSZ256rr", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rr) + .value("VUNPCKHPSZ256rrk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rrk) + .value("VUNPCKHPSZ256rrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZ256rrkz) + .value("VUNPCKHPSZrm", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrm) + .value("VUNPCKHPSZrmb", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrmb) + .value("VUNPCKHPSZrmbk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrmbk) + .value("VUNPCKHPSZrmbkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrmbkz) + .value("VUNPCKHPSZrmk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrmk) + .value("VUNPCKHPSZrmkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrmkz) + .value("VUNPCKHPSZrr", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrr) + .value("VUNPCKHPSZrrk", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrrk) + .value("VUNPCKHPSZrrkz", LIEF::assembly::x86::OPCODE::VUNPCKHPSZrrkz) + .value("VUNPCKHPSrm", LIEF::assembly::x86::OPCODE::VUNPCKHPSrm) + .value("VUNPCKHPSrr", LIEF::assembly::x86::OPCODE::VUNPCKHPSrr) + .value("VUNPCKLPDYrm", LIEF::assembly::x86::OPCODE::VUNPCKLPDYrm) + .value("VUNPCKLPDYrr", LIEF::assembly::x86::OPCODE::VUNPCKLPDYrr) + .value("VUNPCKLPDZ128rm", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rm) + .value("VUNPCKLPDZ128rmb", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rmb) + .value("VUNPCKLPDZ128rmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rmbk) + .value("VUNPCKLPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rmbkz) + .value("VUNPCKLPDZ128rmk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rmk) + .value("VUNPCKLPDZ128rmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rmkz) + .value("VUNPCKLPDZ128rr", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rr) + .value("VUNPCKLPDZ128rrk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rrk) + .value("VUNPCKLPDZ128rrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ128rrkz) + .value("VUNPCKLPDZ256rm", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rm) + .value("VUNPCKLPDZ256rmb", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rmb) + .value("VUNPCKLPDZ256rmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rmbk) + .value("VUNPCKLPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rmbkz) + .value("VUNPCKLPDZ256rmk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rmk) + .value("VUNPCKLPDZ256rmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rmkz) + .value("VUNPCKLPDZ256rr", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rr) + .value("VUNPCKLPDZ256rrk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rrk) + .value("VUNPCKLPDZ256rrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZ256rrkz) + .value("VUNPCKLPDZrm", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrm) + .value("VUNPCKLPDZrmb", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrmb) + .value("VUNPCKLPDZrmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrmbk) + .value("VUNPCKLPDZrmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrmbkz) + .value("VUNPCKLPDZrmk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrmk) + .value("VUNPCKLPDZrmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrmkz) + .value("VUNPCKLPDZrr", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrr) + .value("VUNPCKLPDZrrk", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrrk) + .value("VUNPCKLPDZrrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPDZrrkz) + .value("VUNPCKLPDrm", LIEF::assembly::x86::OPCODE::VUNPCKLPDrm) + .value("VUNPCKLPDrr", LIEF::assembly::x86::OPCODE::VUNPCKLPDrr) + .value("VUNPCKLPSYrm", LIEF::assembly::x86::OPCODE::VUNPCKLPSYrm) + .value("VUNPCKLPSYrr", LIEF::assembly::x86::OPCODE::VUNPCKLPSYrr) + .value("VUNPCKLPSZ128rm", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rm) + .value("VUNPCKLPSZ128rmb", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rmb) + .value("VUNPCKLPSZ128rmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rmbk) + .value("VUNPCKLPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rmbkz) + .value("VUNPCKLPSZ128rmk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rmk) + .value("VUNPCKLPSZ128rmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rmkz) + .value("VUNPCKLPSZ128rr", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rr) + .value("VUNPCKLPSZ128rrk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rrk) + .value("VUNPCKLPSZ128rrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ128rrkz) + .value("VUNPCKLPSZ256rm", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rm) + .value("VUNPCKLPSZ256rmb", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rmb) + .value("VUNPCKLPSZ256rmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rmbk) + .value("VUNPCKLPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rmbkz) + .value("VUNPCKLPSZ256rmk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rmk) + .value("VUNPCKLPSZ256rmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rmkz) + .value("VUNPCKLPSZ256rr", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rr) + .value("VUNPCKLPSZ256rrk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rrk) + .value("VUNPCKLPSZ256rrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZ256rrkz) + .value("VUNPCKLPSZrm", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrm) + .value("VUNPCKLPSZrmb", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrmb) + .value("VUNPCKLPSZrmbk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrmbk) + .value("VUNPCKLPSZrmbkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrmbkz) + .value("VUNPCKLPSZrmk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrmk) + .value("VUNPCKLPSZrmkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrmkz) + .value("VUNPCKLPSZrr", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrr) + .value("VUNPCKLPSZrrk", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrrk) + .value("VUNPCKLPSZrrkz", LIEF::assembly::x86::OPCODE::VUNPCKLPSZrrkz) + .value("VUNPCKLPSrm", LIEF::assembly::x86::OPCODE::VUNPCKLPSrm) + .value("VUNPCKLPSrr", LIEF::assembly::x86::OPCODE::VUNPCKLPSrr) + .value("VXORPDYrm", LIEF::assembly::x86::OPCODE::VXORPDYrm) + .value("VXORPDYrr", LIEF::assembly::x86::OPCODE::VXORPDYrr) + .value("VXORPDZ128rm", LIEF::assembly::x86::OPCODE::VXORPDZ128rm) + .value("VXORPDZ128rmb", LIEF::assembly::x86::OPCODE::VXORPDZ128rmb) + .value("VXORPDZ128rmbk", LIEF::assembly::x86::OPCODE::VXORPDZ128rmbk) + .value("VXORPDZ128rmbkz", LIEF::assembly::x86::OPCODE::VXORPDZ128rmbkz) + .value("VXORPDZ128rmk", LIEF::assembly::x86::OPCODE::VXORPDZ128rmk) + .value("VXORPDZ128rmkz", LIEF::assembly::x86::OPCODE::VXORPDZ128rmkz) + .value("VXORPDZ128rr", LIEF::assembly::x86::OPCODE::VXORPDZ128rr) + .value("VXORPDZ128rrk", LIEF::assembly::x86::OPCODE::VXORPDZ128rrk) + .value("VXORPDZ128rrkz", LIEF::assembly::x86::OPCODE::VXORPDZ128rrkz) + .value("VXORPDZ256rm", LIEF::assembly::x86::OPCODE::VXORPDZ256rm) + .value("VXORPDZ256rmb", LIEF::assembly::x86::OPCODE::VXORPDZ256rmb) + .value("VXORPDZ256rmbk", LIEF::assembly::x86::OPCODE::VXORPDZ256rmbk) + .value("VXORPDZ256rmbkz", LIEF::assembly::x86::OPCODE::VXORPDZ256rmbkz) + .value("VXORPDZ256rmk", LIEF::assembly::x86::OPCODE::VXORPDZ256rmk) + .value("VXORPDZ256rmkz", LIEF::assembly::x86::OPCODE::VXORPDZ256rmkz) + .value("VXORPDZ256rr", LIEF::assembly::x86::OPCODE::VXORPDZ256rr) + .value("VXORPDZ256rrk", LIEF::assembly::x86::OPCODE::VXORPDZ256rrk) + .value("VXORPDZ256rrkz", LIEF::assembly::x86::OPCODE::VXORPDZ256rrkz) + .value("VXORPDZrm", LIEF::assembly::x86::OPCODE::VXORPDZrm) + .value("VXORPDZrmb", LIEF::assembly::x86::OPCODE::VXORPDZrmb) + .value("VXORPDZrmbk", LIEF::assembly::x86::OPCODE::VXORPDZrmbk) + .value("VXORPDZrmbkz", LIEF::assembly::x86::OPCODE::VXORPDZrmbkz) + .value("VXORPDZrmk", LIEF::assembly::x86::OPCODE::VXORPDZrmk) + .value("VXORPDZrmkz", LIEF::assembly::x86::OPCODE::VXORPDZrmkz) + .value("VXORPDZrr", LIEF::assembly::x86::OPCODE::VXORPDZrr) + .value("VXORPDZrrk", LIEF::assembly::x86::OPCODE::VXORPDZrrk) + .value("VXORPDZrrkz", LIEF::assembly::x86::OPCODE::VXORPDZrrkz) + .value("VXORPDrm", LIEF::assembly::x86::OPCODE::VXORPDrm) + .value("VXORPDrr", LIEF::assembly::x86::OPCODE::VXORPDrr) + .value("VXORPSYrm", LIEF::assembly::x86::OPCODE::VXORPSYrm) + .value("VXORPSYrr", LIEF::assembly::x86::OPCODE::VXORPSYrr) + .value("VXORPSZ128rm", LIEF::assembly::x86::OPCODE::VXORPSZ128rm) + .value("VXORPSZ128rmb", LIEF::assembly::x86::OPCODE::VXORPSZ128rmb) + .value("VXORPSZ128rmbk", LIEF::assembly::x86::OPCODE::VXORPSZ128rmbk) + .value("VXORPSZ128rmbkz", LIEF::assembly::x86::OPCODE::VXORPSZ128rmbkz) + .value("VXORPSZ128rmk", LIEF::assembly::x86::OPCODE::VXORPSZ128rmk) + .value("VXORPSZ128rmkz", LIEF::assembly::x86::OPCODE::VXORPSZ128rmkz) + .value("VXORPSZ128rr", LIEF::assembly::x86::OPCODE::VXORPSZ128rr) + .value("VXORPSZ128rrk", LIEF::assembly::x86::OPCODE::VXORPSZ128rrk) + .value("VXORPSZ128rrkz", LIEF::assembly::x86::OPCODE::VXORPSZ128rrkz) + .value("VXORPSZ256rm", LIEF::assembly::x86::OPCODE::VXORPSZ256rm) + .value("VXORPSZ256rmb", LIEF::assembly::x86::OPCODE::VXORPSZ256rmb) + .value("VXORPSZ256rmbk", LIEF::assembly::x86::OPCODE::VXORPSZ256rmbk) + .value("VXORPSZ256rmbkz", LIEF::assembly::x86::OPCODE::VXORPSZ256rmbkz) + .value("VXORPSZ256rmk", LIEF::assembly::x86::OPCODE::VXORPSZ256rmk) + .value("VXORPSZ256rmkz", LIEF::assembly::x86::OPCODE::VXORPSZ256rmkz) + .value("VXORPSZ256rr", LIEF::assembly::x86::OPCODE::VXORPSZ256rr) + .value("VXORPSZ256rrk", LIEF::assembly::x86::OPCODE::VXORPSZ256rrk) + .value("VXORPSZ256rrkz", LIEF::assembly::x86::OPCODE::VXORPSZ256rrkz) + .value("VXORPSZrm", LIEF::assembly::x86::OPCODE::VXORPSZrm) + .value("VXORPSZrmb", LIEF::assembly::x86::OPCODE::VXORPSZrmb) + .value("VXORPSZrmbk", LIEF::assembly::x86::OPCODE::VXORPSZrmbk) + .value("VXORPSZrmbkz", LIEF::assembly::x86::OPCODE::VXORPSZrmbkz) + .value("VXORPSZrmk", LIEF::assembly::x86::OPCODE::VXORPSZrmk) + .value("VXORPSZrmkz", LIEF::assembly::x86::OPCODE::VXORPSZrmkz) + .value("VXORPSZrr", LIEF::assembly::x86::OPCODE::VXORPSZrr) + .value("VXORPSZrrk", LIEF::assembly::x86::OPCODE::VXORPSZrrk) + .value("VXORPSZrrkz", LIEF::assembly::x86::OPCODE::VXORPSZrrkz) + .value("VXORPSrm", LIEF::assembly::x86::OPCODE::VXORPSrm) + .value("VXORPSrr", LIEF::assembly::x86::OPCODE::VXORPSrr) + .value("VZEROALL", LIEF::assembly::x86::OPCODE::VZEROALL) + .value("VZEROUPPER", LIEF::assembly::x86::OPCODE::VZEROUPPER) + .value("WAIT", LIEF::assembly::x86::OPCODE::WAIT) + .value("WBINVD", LIEF::assembly::x86::OPCODE::WBINVD) + .value("WBNOINVD", LIEF::assembly::x86::OPCODE::WBNOINVD) + .value("WRFSBASE", LIEF::assembly::x86::OPCODE::WRFSBASE) + .value("WRFSBASE64", LIEF::assembly::x86::OPCODE::WRFSBASE64) + .value("WRGSBASE", LIEF::assembly::x86::OPCODE::WRGSBASE) + .value("WRGSBASE64", LIEF::assembly::x86::OPCODE::WRGSBASE64) + .value("WRMSR", LIEF::assembly::x86::OPCODE::WRMSR) + .value("WRMSRLIST", LIEF::assembly::x86::OPCODE::WRMSRLIST) + .value("WRMSRNS", LIEF::assembly::x86::OPCODE::WRMSRNS) + .value("WRMSRNSir", LIEF::assembly::x86::OPCODE::WRMSRNSir) + .value("WRMSRNSir_EVEX", LIEF::assembly::x86::OPCODE::WRMSRNSir_EVEX) + .value("WRPKRUr", LIEF::assembly::x86::OPCODE::WRPKRUr) + .value("WRSSD", LIEF::assembly::x86::OPCODE::WRSSD) + .value("WRSSD_EVEX", LIEF::assembly::x86::OPCODE::WRSSD_EVEX) + .value("WRSSQ", LIEF::assembly::x86::OPCODE::WRSSQ) + .value("WRSSQ_EVEX", LIEF::assembly::x86::OPCODE::WRSSQ_EVEX) + .value("WRUSSD", LIEF::assembly::x86::OPCODE::WRUSSD) + .value("WRUSSD_EVEX", LIEF::assembly::x86::OPCODE::WRUSSD_EVEX) + .value("WRUSSQ", LIEF::assembly::x86::OPCODE::WRUSSQ) + .value("WRUSSQ_EVEX", LIEF::assembly::x86::OPCODE::WRUSSQ_EVEX) + .value("XABORT", LIEF::assembly::x86::OPCODE::XABORT) + .value("XACQUIRE_PREFIX", LIEF::assembly::x86::OPCODE::XACQUIRE_PREFIX) + .value("XADD16rm", LIEF::assembly::x86::OPCODE::XADD16rm) + .value("XADD16rr", LIEF::assembly::x86::OPCODE::XADD16rr) + .value("XADD32rm", LIEF::assembly::x86::OPCODE::XADD32rm) + .value("XADD32rr", LIEF::assembly::x86::OPCODE::XADD32rr) + .value("XADD64rm", LIEF::assembly::x86::OPCODE::XADD64rm) + .value("XADD64rr", LIEF::assembly::x86::OPCODE::XADD64rr) + .value("XADD8rm", LIEF::assembly::x86::OPCODE::XADD8rm) + .value("XADD8rr", LIEF::assembly::x86::OPCODE::XADD8rr) + .value("XAM_F", LIEF::assembly::x86::OPCODE::XAM_F) + .value("XAM_Fp32", LIEF::assembly::x86::OPCODE::XAM_Fp32) + .value("XAM_Fp64", LIEF::assembly::x86::OPCODE::XAM_Fp64) + .value("XAM_Fp80", LIEF::assembly::x86::OPCODE::XAM_Fp80) + .value("XBEGIN", LIEF::assembly::x86::OPCODE::XBEGIN) + .value("XBEGIN_2", LIEF::assembly::x86::OPCODE::XBEGIN_2) + .value("XBEGIN_4", LIEF::assembly::x86::OPCODE::XBEGIN_4) + .value("XCHG16ar", LIEF::assembly::x86::OPCODE::XCHG16ar) + .value("XCHG16rm", LIEF::assembly::x86::OPCODE::XCHG16rm) + .value("XCHG16rr", LIEF::assembly::x86::OPCODE::XCHG16rr) + .value("XCHG32ar", LIEF::assembly::x86::OPCODE::XCHG32ar) + .value("XCHG32rm", LIEF::assembly::x86::OPCODE::XCHG32rm) + .value("XCHG32rr", LIEF::assembly::x86::OPCODE::XCHG32rr) + .value("XCHG64ar", LIEF::assembly::x86::OPCODE::XCHG64ar) + .value("XCHG64rm", LIEF::assembly::x86::OPCODE::XCHG64rm) + .value("XCHG64rr", LIEF::assembly::x86::OPCODE::XCHG64rr) + .value("XCHG8rm", LIEF::assembly::x86::OPCODE::XCHG8rm) + .value("XCHG8rr", LIEF::assembly::x86::OPCODE::XCHG8rr) + .value("XCH_F", LIEF::assembly::x86::OPCODE::XCH_F) + .value("XCRYPTCBC", LIEF::assembly::x86::OPCODE::XCRYPTCBC) + .value("XCRYPTCFB", LIEF::assembly::x86::OPCODE::XCRYPTCFB) + .value("XCRYPTCTR", LIEF::assembly::x86::OPCODE::XCRYPTCTR) + .value("XCRYPTECB", LIEF::assembly::x86::OPCODE::XCRYPTECB) + .value("XCRYPTOFB", LIEF::assembly::x86::OPCODE::XCRYPTOFB) + .value("XEND", LIEF::assembly::x86::OPCODE::XEND) + .value("XGETBV", LIEF::assembly::x86::OPCODE::XGETBV) + .value("XLAT", LIEF::assembly::x86::OPCODE::XLAT) + .value("XOR16i16", LIEF::assembly::x86::OPCODE::XOR16i16) + .value("XOR16mi", LIEF::assembly::x86::OPCODE::XOR16mi) + .value("XOR16mi8", LIEF::assembly::x86::OPCODE::XOR16mi8) + .value("XOR16mi8_EVEX", LIEF::assembly::x86::OPCODE::XOR16mi8_EVEX) + .value("XOR16mi8_ND", LIEF::assembly::x86::OPCODE::XOR16mi8_ND) + .value("XOR16mi8_NF", LIEF::assembly::x86::OPCODE::XOR16mi8_NF) + .value("XOR16mi8_NF_ND", LIEF::assembly::x86::OPCODE::XOR16mi8_NF_ND) + .value("XOR16mi_EVEX", LIEF::assembly::x86::OPCODE::XOR16mi_EVEX) + .value("XOR16mi_ND", LIEF::assembly::x86::OPCODE::XOR16mi_ND) + .value("XOR16mi_NF", LIEF::assembly::x86::OPCODE::XOR16mi_NF) + .value("XOR16mi_NF_ND", LIEF::assembly::x86::OPCODE::XOR16mi_NF_ND) + .value("XOR16mr", LIEF::assembly::x86::OPCODE::XOR16mr) + .value("XOR16mr_EVEX", LIEF::assembly::x86::OPCODE::XOR16mr_EVEX) + .value("XOR16mr_ND", LIEF::assembly::x86::OPCODE::XOR16mr_ND) + .value("XOR16mr_NF", LIEF::assembly::x86::OPCODE::XOR16mr_NF) + .value("XOR16mr_NF_ND", LIEF::assembly::x86::OPCODE::XOR16mr_NF_ND) + .value("XOR16ri", LIEF::assembly::x86::OPCODE::XOR16ri) + .value("XOR16ri8", LIEF::assembly::x86::OPCODE::XOR16ri8) + .value("XOR16ri8_EVEX", LIEF::assembly::x86::OPCODE::XOR16ri8_EVEX) + .value("XOR16ri8_ND", LIEF::assembly::x86::OPCODE::XOR16ri8_ND) + .value("XOR16ri8_NF", LIEF::assembly::x86::OPCODE::XOR16ri8_NF) + .value("XOR16ri8_NF_ND", LIEF::assembly::x86::OPCODE::XOR16ri8_NF_ND) + .value("XOR16ri_EVEX", LIEF::assembly::x86::OPCODE::XOR16ri_EVEX) + .value("XOR16ri_ND", LIEF::assembly::x86::OPCODE::XOR16ri_ND) + .value("XOR16ri_NF", LIEF::assembly::x86::OPCODE::XOR16ri_NF) + .value("XOR16ri_NF_ND", LIEF::assembly::x86::OPCODE::XOR16ri_NF_ND) + .value("XOR16rm", LIEF::assembly::x86::OPCODE::XOR16rm) + .value("XOR16rm_EVEX", LIEF::assembly::x86::OPCODE::XOR16rm_EVEX) + .value("XOR16rm_ND", LIEF::assembly::x86::OPCODE::XOR16rm_ND) + .value("XOR16rm_NF", LIEF::assembly::x86::OPCODE::XOR16rm_NF) + .value("XOR16rm_NF_ND", LIEF::assembly::x86::OPCODE::XOR16rm_NF_ND) + .value("XOR16rr", LIEF::assembly::x86::OPCODE::XOR16rr) + .value("XOR16rr_EVEX", LIEF::assembly::x86::OPCODE::XOR16rr_EVEX) + .value("XOR16rr_EVEX_REV", LIEF::assembly::x86::OPCODE::XOR16rr_EVEX_REV) + .value("XOR16rr_ND", LIEF::assembly::x86::OPCODE::XOR16rr_ND) + .value("XOR16rr_ND_REV", LIEF::assembly::x86::OPCODE::XOR16rr_ND_REV) + .value("XOR16rr_NF", LIEF::assembly::x86::OPCODE::XOR16rr_NF) + .value("XOR16rr_NF_ND", LIEF::assembly::x86::OPCODE::XOR16rr_NF_ND) + .value("XOR16rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::XOR16rr_NF_ND_REV) + .value("XOR16rr_NF_REV", LIEF::assembly::x86::OPCODE::XOR16rr_NF_REV) + .value("XOR16rr_REV", LIEF::assembly::x86::OPCODE::XOR16rr_REV) + .value("XOR32i32", LIEF::assembly::x86::OPCODE::XOR32i32) + .value("XOR32mi", LIEF::assembly::x86::OPCODE::XOR32mi) + .value("XOR32mi8", LIEF::assembly::x86::OPCODE::XOR32mi8) + .value("XOR32mi8_EVEX", LIEF::assembly::x86::OPCODE::XOR32mi8_EVEX) + .value("XOR32mi8_ND", LIEF::assembly::x86::OPCODE::XOR32mi8_ND) + .value("XOR32mi8_NF", LIEF::assembly::x86::OPCODE::XOR32mi8_NF) + .value("XOR32mi8_NF_ND", LIEF::assembly::x86::OPCODE::XOR32mi8_NF_ND) + .value("XOR32mi_EVEX", LIEF::assembly::x86::OPCODE::XOR32mi_EVEX) + .value("XOR32mi_ND", LIEF::assembly::x86::OPCODE::XOR32mi_ND) + .value("XOR32mi_NF", LIEF::assembly::x86::OPCODE::XOR32mi_NF) + .value("XOR32mi_NF_ND", LIEF::assembly::x86::OPCODE::XOR32mi_NF_ND) + .value("XOR32mr", LIEF::assembly::x86::OPCODE::XOR32mr) + .value("XOR32mr_EVEX", LIEF::assembly::x86::OPCODE::XOR32mr_EVEX) + .value("XOR32mr_ND", LIEF::assembly::x86::OPCODE::XOR32mr_ND) + .value("XOR32mr_NF", LIEF::assembly::x86::OPCODE::XOR32mr_NF) + .value("XOR32mr_NF_ND", LIEF::assembly::x86::OPCODE::XOR32mr_NF_ND) + .value("XOR32ri", LIEF::assembly::x86::OPCODE::XOR32ri) + .value("XOR32ri8", LIEF::assembly::x86::OPCODE::XOR32ri8) + .value("XOR32ri8_EVEX", LIEF::assembly::x86::OPCODE::XOR32ri8_EVEX) + .value("XOR32ri8_ND", LIEF::assembly::x86::OPCODE::XOR32ri8_ND) + .value("XOR32ri8_NF", LIEF::assembly::x86::OPCODE::XOR32ri8_NF) + .value("XOR32ri8_NF_ND", LIEF::assembly::x86::OPCODE::XOR32ri8_NF_ND) + .value("XOR32ri_EVEX", LIEF::assembly::x86::OPCODE::XOR32ri_EVEX) + .value("XOR32ri_ND", LIEF::assembly::x86::OPCODE::XOR32ri_ND) + .value("XOR32ri_NF", LIEF::assembly::x86::OPCODE::XOR32ri_NF) + .value("XOR32ri_NF_ND", LIEF::assembly::x86::OPCODE::XOR32ri_NF_ND) + .value("XOR32rm", LIEF::assembly::x86::OPCODE::XOR32rm) + .value("XOR32rm_EVEX", LIEF::assembly::x86::OPCODE::XOR32rm_EVEX) + .value("XOR32rm_ND", LIEF::assembly::x86::OPCODE::XOR32rm_ND) + .value("XOR32rm_NF", LIEF::assembly::x86::OPCODE::XOR32rm_NF) + .value("XOR32rm_NF_ND", LIEF::assembly::x86::OPCODE::XOR32rm_NF_ND) + .value("XOR32rr", LIEF::assembly::x86::OPCODE::XOR32rr) + .value("XOR32rr_EVEX", LIEF::assembly::x86::OPCODE::XOR32rr_EVEX) + .value("XOR32rr_EVEX_REV", LIEF::assembly::x86::OPCODE::XOR32rr_EVEX_REV) + .value("XOR32rr_ND", LIEF::assembly::x86::OPCODE::XOR32rr_ND) + .value("XOR32rr_ND_REV", LIEF::assembly::x86::OPCODE::XOR32rr_ND_REV) + .value("XOR32rr_NF", LIEF::assembly::x86::OPCODE::XOR32rr_NF) + .value("XOR32rr_NF_ND", LIEF::assembly::x86::OPCODE::XOR32rr_NF_ND) + .value("XOR32rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::XOR32rr_NF_ND_REV) + .value("XOR32rr_NF_REV", LIEF::assembly::x86::OPCODE::XOR32rr_NF_REV) + .value("XOR32rr_REV", LIEF::assembly::x86::OPCODE::XOR32rr_REV) + .value("XOR64i32", LIEF::assembly::x86::OPCODE::XOR64i32) + .value("XOR64mi32", LIEF::assembly::x86::OPCODE::XOR64mi32) + .value("XOR64mi32_EVEX", LIEF::assembly::x86::OPCODE::XOR64mi32_EVEX) + .value("XOR64mi32_ND", LIEF::assembly::x86::OPCODE::XOR64mi32_ND); + opcodes.value("XOR64mi32_NF", LIEF::assembly::x86::OPCODE::XOR64mi32_NF) + .value("XOR64mi32_NF_ND", LIEF::assembly::x86::OPCODE::XOR64mi32_NF_ND) + .value("XOR64mi8", LIEF::assembly::x86::OPCODE::XOR64mi8) + .value("XOR64mi8_EVEX", LIEF::assembly::x86::OPCODE::XOR64mi8_EVEX) + .value("XOR64mi8_ND", LIEF::assembly::x86::OPCODE::XOR64mi8_ND) + .value("XOR64mi8_NF", LIEF::assembly::x86::OPCODE::XOR64mi8_NF) + .value("XOR64mi8_NF_ND", LIEF::assembly::x86::OPCODE::XOR64mi8_NF_ND) + .value("XOR64mr", LIEF::assembly::x86::OPCODE::XOR64mr) + .value("XOR64mr_EVEX", LIEF::assembly::x86::OPCODE::XOR64mr_EVEX) + .value("XOR64mr_ND", LIEF::assembly::x86::OPCODE::XOR64mr_ND) + .value("XOR64mr_NF", LIEF::assembly::x86::OPCODE::XOR64mr_NF) + .value("XOR64mr_NF_ND", LIEF::assembly::x86::OPCODE::XOR64mr_NF_ND) + .value("XOR64ri32", LIEF::assembly::x86::OPCODE::XOR64ri32) + .value("XOR64ri32_EVEX", LIEF::assembly::x86::OPCODE::XOR64ri32_EVEX) + .value("XOR64ri32_ND", LIEF::assembly::x86::OPCODE::XOR64ri32_ND) + .value("XOR64ri32_NF", LIEF::assembly::x86::OPCODE::XOR64ri32_NF) + .value("XOR64ri32_NF_ND", LIEF::assembly::x86::OPCODE::XOR64ri32_NF_ND) + .value("XOR64ri8", LIEF::assembly::x86::OPCODE::XOR64ri8) + .value("XOR64ri8_EVEX", LIEF::assembly::x86::OPCODE::XOR64ri8_EVEX) + .value("XOR64ri8_ND", LIEF::assembly::x86::OPCODE::XOR64ri8_ND) + .value("XOR64ri8_NF", LIEF::assembly::x86::OPCODE::XOR64ri8_NF) + .value("XOR64ri8_NF_ND", LIEF::assembly::x86::OPCODE::XOR64ri8_NF_ND) + .value("XOR64rm", LIEF::assembly::x86::OPCODE::XOR64rm) + .value("XOR64rm_EVEX", LIEF::assembly::x86::OPCODE::XOR64rm_EVEX) + .value("XOR64rm_ND", LIEF::assembly::x86::OPCODE::XOR64rm_ND) + .value("XOR64rm_NF", LIEF::assembly::x86::OPCODE::XOR64rm_NF) + .value("XOR64rm_NF_ND", LIEF::assembly::x86::OPCODE::XOR64rm_NF_ND) + .value("XOR64rr", LIEF::assembly::x86::OPCODE::XOR64rr) + .value("XOR64rr_EVEX", LIEF::assembly::x86::OPCODE::XOR64rr_EVEX) + .value("XOR64rr_EVEX_REV", LIEF::assembly::x86::OPCODE::XOR64rr_EVEX_REV) + .value("XOR64rr_ND", LIEF::assembly::x86::OPCODE::XOR64rr_ND) + .value("XOR64rr_ND_REV", LIEF::assembly::x86::OPCODE::XOR64rr_ND_REV) + .value("XOR64rr_NF", LIEF::assembly::x86::OPCODE::XOR64rr_NF) + .value("XOR64rr_NF_ND", LIEF::assembly::x86::OPCODE::XOR64rr_NF_ND) + .value("XOR64rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::XOR64rr_NF_ND_REV) + .value("XOR64rr_NF_REV", LIEF::assembly::x86::OPCODE::XOR64rr_NF_REV) + .value("XOR64rr_REV", LIEF::assembly::x86::OPCODE::XOR64rr_REV) + .value("XOR8i8", LIEF::assembly::x86::OPCODE::XOR8i8) + .value("XOR8mi", LIEF::assembly::x86::OPCODE::XOR8mi) + .value("XOR8mi8", LIEF::assembly::x86::OPCODE::XOR8mi8) + .value("XOR8mi_EVEX", LIEF::assembly::x86::OPCODE::XOR8mi_EVEX) + .value("XOR8mi_ND", LIEF::assembly::x86::OPCODE::XOR8mi_ND) + .value("XOR8mi_NF", LIEF::assembly::x86::OPCODE::XOR8mi_NF) + .value("XOR8mi_NF_ND", LIEF::assembly::x86::OPCODE::XOR8mi_NF_ND) + .value("XOR8mr", LIEF::assembly::x86::OPCODE::XOR8mr) + .value("XOR8mr_EVEX", LIEF::assembly::x86::OPCODE::XOR8mr_EVEX) + .value("XOR8mr_ND", LIEF::assembly::x86::OPCODE::XOR8mr_ND) + .value("XOR8mr_NF", LIEF::assembly::x86::OPCODE::XOR8mr_NF) + .value("XOR8mr_NF_ND", LIEF::assembly::x86::OPCODE::XOR8mr_NF_ND) + .value("XOR8ri", LIEF::assembly::x86::OPCODE::XOR8ri) + .value("XOR8ri8", LIEF::assembly::x86::OPCODE::XOR8ri8) + .value("XOR8ri_EVEX", LIEF::assembly::x86::OPCODE::XOR8ri_EVEX) + .value("XOR8ri_ND", LIEF::assembly::x86::OPCODE::XOR8ri_ND) + .value("XOR8ri_NF", LIEF::assembly::x86::OPCODE::XOR8ri_NF) + .value("XOR8ri_NF_ND", LIEF::assembly::x86::OPCODE::XOR8ri_NF_ND) + .value("XOR8rm", LIEF::assembly::x86::OPCODE::XOR8rm) + .value("XOR8rm_EVEX", LIEF::assembly::x86::OPCODE::XOR8rm_EVEX) + .value("XOR8rm_ND", LIEF::assembly::x86::OPCODE::XOR8rm_ND) + .value("XOR8rm_NF", LIEF::assembly::x86::OPCODE::XOR8rm_NF) + .value("XOR8rm_NF_ND", LIEF::assembly::x86::OPCODE::XOR8rm_NF_ND) + .value("XOR8rr", LIEF::assembly::x86::OPCODE::XOR8rr) + .value("XOR8rr_EVEX", LIEF::assembly::x86::OPCODE::XOR8rr_EVEX) + .value("XOR8rr_EVEX_REV", LIEF::assembly::x86::OPCODE::XOR8rr_EVEX_REV) + .value("XOR8rr_ND", LIEF::assembly::x86::OPCODE::XOR8rr_ND) + .value("XOR8rr_ND_REV", LIEF::assembly::x86::OPCODE::XOR8rr_ND_REV) + .value("XOR8rr_NF", LIEF::assembly::x86::OPCODE::XOR8rr_NF) + .value("XOR8rr_NF_ND", LIEF::assembly::x86::OPCODE::XOR8rr_NF_ND) + .value("XOR8rr_NF_ND_REV", LIEF::assembly::x86::OPCODE::XOR8rr_NF_ND_REV) + .value("XOR8rr_NF_REV", LIEF::assembly::x86::OPCODE::XOR8rr_NF_REV) + .value("XOR8rr_NOREX", LIEF::assembly::x86::OPCODE::XOR8rr_NOREX) + .value("XOR8rr_REV", LIEF::assembly::x86::OPCODE::XOR8rr_REV) + .value("XORPDrm", LIEF::assembly::x86::OPCODE::XORPDrm) + .value("XORPDrr", LIEF::assembly::x86::OPCODE::XORPDrr) + .value("XORPSrm", LIEF::assembly::x86::OPCODE::XORPSrm) + .value("XORPSrr", LIEF::assembly::x86::OPCODE::XORPSrr) + .value("XRELEASE_PREFIX", LIEF::assembly::x86::OPCODE::XRELEASE_PREFIX) + .value("XRESLDTRK", LIEF::assembly::x86::OPCODE::XRESLDTRK) + .value("XRSTOR", LIEF::assembly::x86::OPCODE::XRSTOR) + .value("XRSTOR64", LIEF::assembly::x86::OPCODE::XRSTOR64) + .value("XRSTORS", LIEF::assembly::x86::OPCODE::XRSTORS) + .value("XRSTORS64", LIEF::assembly::x86::OPCODE::XRSTORS64) + .value("XSAVE", LIEF::assembly::x86::OPCODE::XSAVE) + .value("XSAVE64", LIEF::assembly::x86::OPCODE::XSAVE64) + .value("XSAVEC", LIEF::assembly::x86::OPCODE::XSAVEC) + .value("XSAVEC64", LIEF::assembly::x86::OPCODE::XSAVEC64) + .value("XSAVEOPT", LIEF::assembly::x86::OPCODE::XSAVEOPT) + .value("XSAVEOPT64", LIEF::assembly::x86::OPCODE::XSAVEOPT64) + .value("XSAVES", LIEF::assembly::x86::OPCODE::XSAVES) + .value("XSAVES64", LIEF::assembly::x86::OPCODE::XSAVES64) + .value("XSETBV", LIEF::assembly::x86::OPCODE::XSETBV) + .value("XSHA1", LIEF::assembly::x86::OPCODE::XSHA1) + .value("XSHA256", LIEF::assembly::x86::OPCODE::XSHA256) + .value("XSTORE", LIEF::assembly::x86::OPCODE::XSTORE) + .value("XSUSLDTRK", LIEF::assembly::x86::OPCODE::XSUSLDTRK) + .value("XTEST", LIEF::assembly::x86::OPCODE::XTEST) + .value("INSTRUCTION_LIST_END", LIEF::assembly::x86::OPCODE::INSTRUCTION_LIST_END) + ; +} +} diff --git a/vendor/lief/api/python/src/asm/x86/pyOperand.cpp b/vendor/lief/api/python/src/asm/x86/pyOperand.cpp new file mode 100644 index 0000000..888f78c --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/pyOperand.cpp @@ -0,0 +1,39 @@ +#include +#include + +#include "LIEF/asm/x86/Operand.hpp" + +#include "asm/x86/init.hpp" + +#include + +#include "pyLIEF.hpp" + +namespace LIEF::assembly::x86::operands { +class Immediate; +class Register; +class Memory; +class PCRelative; +} + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Operand", + R"doc(This class represents an operand for an x86/x86-64 instruction)doc"_doc + ); + + obj + .def_prop_ro("to_string", &Operand::to_string, + R"doc(Pretty representation of the operand)doc"_doc + ) + LIEF_DEFAULT_STR(x86::Operand) + ; + + nb::module_ operands = m.def_submodule("operands"); + create(operands); + create(operands); + create(operands); + create(operands); +} +} diff --git a/vendor/lief/api/python/src/asm/x86/pyRegister.cpp b/vendor/lief/api/python/src/asm/x86/pyRegister.cpp new file mode 100644 index 0000000..254b698 --- /dev/null +++ b/vendor/lief/api/python/src/asm/x86/pyRegister.cpp @@ -0,0 +1,400 @@ +#include "asm/x86/init.hpp" + +#include "LIEF/asm/x86/registers.hpp" + +namespace LIEF::assembly::x86::py { +template<> +void create(nb::module_& m) { + nb::enum_ reg(m, "REG"); + reg.value("NoRegister", LIEF::assembly::x86::REG::NoRegister) + .value("AH", LIEF::assembly::x86::REG::AH) + .value("AL", LIEF::assembly::x86::REG::AL) + .value("AX", LIEF::assembly::x86::REG::AX) + .value("BH", LIEF::assembly::x86::REG::BH) + .value("BL", LIEF::assembly::x86::REG::BL) + .value("BP", LIEF::assembly::x86::REG::BP) + .value("BPH", LIEF::assembly::x86::REG::BPH) + .value("BPL", LIEF::assembly::x86::REG::BPL) + .value("BX", LIEF::assembly::x86::REG::BX) + .value("CH", LIEF::assembly::x86::REG::CH) + .value("CL", LIEF::assembly::x86::REG::CL) + .value("CS", LIEF::assembly::x86::REG::CS) + .value("CX", LIEF::assembly::x86::REG::CX) + .value("DF", LIEF::assembly::x86::REG::DF) + .value("DH", LIEF::assembly::x86::REG::DH) + .value("DI", LIEF::assembly::x86::REG::DI) + .value("DIH", LIEF::assembly::x86::REG::DIH) + .value("DIL", LIEF::assembly::x86::REG::DIL) + .value("DL", LIEF::assembly::x86::REG::DL) + .value("DS", LIEF::assembly::x86::REG::DS) + .value("DX", LIEF::assembly::x86::REG::DX) + .value("EAX", LIEF::assembly::x86::REG::EAX) + .value("EBP", LIEF::assembly::x86::REG::EBP) + .value("EBX", LIEF::assembly::x86::REG::EBX) + .value("ECX", LIEF::assembly::x86::REG::ECX) + .value("EDI", LIEF::assembly::x86::REG::EDI) + .value("EDX", LIEF::assembly::x86::REG::EDX) + .value("EFLAGS", LIEF::assembly::x86::REG::EFLAGS) + .value("EIP", LIEF::assembly::x86::REG::EIP) + .value("EIZ", LIEF::assembly::x86::REG::EIZ) + .value("ES", LIEF::assembly::x86::REG::ES) + .value("ESI", LIEF::assembly::x86::REG::ESI) + .value("ESP", LIEF::assembly::x86::REG::ESP) + .value("FPCW", LIEF::assembly::x86::REG::FPCW) + .value("FPSW", LIEF::assembly::x86::REG::FPSW) + .value("FS", LIEF::assembly::x86::REG::FS) + .value("FS_BASE", LIEF::assembly::x86::REG::FS_BASE) + .value("GS", LIEF::assembly::x86::REG::GS) + .value("GS_BASE", LIEF::assembly::x86::REG::GS_BASE) + .value("HAX", LIEF::assembly::x86::REG::HAX) + .value("HBP", LIEF::assembly::x86::REG::HBP) + .value("HBX", LIEF::assembly::x86::REG::HBX) + .value("HCX", LIEF::assembly::x86::REG::HCX) + .value("HDI", LIEF::assembly::x86::REG::HDI) + .value("HDX", LIEF::assembly::x86::REG::HDX) + .value("HIP", LIEF::assembly::x86::REG::HIP) + .value("HSI", LIEF::assembly::x86::REG::HSI) + .value("HSP", LIEF::assembly::x86::REG::HSP) + .value("IP", LIEF::assembly::x86::REG::IP) + .value("MXCSR", LIEF::assembly::x86::REG::MXCSR) + .value("RAX", LIEF::assembly::x86::REG::RAX) + .value("RBP", LIEF::assembly::x86::REG::RBP) + .value("RBX", LIEF::assembly::x86::REG::RBX) + .value("RCX", LIEF::assembly::x86::REG::RCX) + .value("RDI", LIEF::assembly::x86::REG::RDI) + .value("RDX", LIEF::assembly::x86::REG::RDX) + .value("RFLAGS", LIEF::assembly::x86::REG::RFLAGS) + .value("RIP", LIEF::assembly::x86::REG::RIP) + .value("RIZ", LIEF::assembly::x86::REG::RIZ) + .value("RSI", LIEF::assembly::x86::REG::RSI) + .value("RSP", LIEF::assembly::x86::REG::RSP) + .value("SI", LIEF::assembly::x86::REG::SI) + .value("SIH", LIEF::assembly::x86::REG::SIH) + .value("SIL", LIEF::assembly::x86::REG::SIL) + .value("SP", LIEF::assembly::x86::REG::SP) + .value("SPH", LIEF::assembly::x86::REG::SPH) + .value("SPL", LIEF::assembly::x86::REG::SPL) + .value("SS", LIEF::assembly::x86::REG::SS) + .value("SSP", LIEF::assembly::x86::REG::SSP) + .value("_EFLAGS", LIEF::assembly::x86::REG::_EFLAGS) + .value("CR0", LIEF::assembly::x86::REG::CR0) + .value("CR1", LIEF::assembly::x86::REG::CR1) + .value("CR2", LIEF::assembly::x86::REG::CR2) + .value("CR3", LIEF::assembly::x86::REG::CR3) + .value("CR4", LIEF::assembly::x86::REG::CR4) + .value("CR5", LIEF::assembly::x86::REG::CR5) + .value("CR6", LIEF::assembly::x86::REG::CR6) + .value("CR7", LIEF::assembly::x86::REG::CR7) + .value("CR8", LIEF::assembly::x86::REG::CR8) + .value("CR9", LIEF::assembly::x86::REG::CR9) + .value("CR10", LIEF::assembly::x86::REG::CR10) + .value("CR11", LIEF::assembly::x86::REG::CR11) + .value("CR12", LIEF::assembly::x86::REG::CR12) + .value("CR13", LIEF::assembly::x86::REG::CR13) + .value("CR14", LIEF::assembly::x86::REG::CR14) + .value("CR15", LIEF::assembly::x86::REG::CR15) + .value("DR0", LIEF::assembly::x86::REG::DR0) + .value("DR1", LIEF::assembly::x86::REG::DR1) + .value("DR2", LIEF::assembly::x86::REG::DR2) + .value("DR3", LIEF::assembly::x86::REG::DR3) + .value("DR4", LIEF::assembly::x86::REG::DR4) + .value("DR5", LIEF::assembly::x86::REG::DR5) + .value("DR6", LIEF::assembly::x86::REG::DR6) + .value("DR7", LIEF::assembly::x86::REG::DR7) + .value("DR8", LIEF::assembly::x86::REG::DR8) + .value("DR9", LIEF::assembly::x86::REG::DR9) + .value("DR10", LIEF::assembly::x86::REG::DR10) + .value("DR11", LIEF::assembly::x86::REG::DR11) + .value("DR12", LIEF::assembly::x86::REG::DR12) + .value("DR13", LIEF::assembly::x86::REG::DR13) + .value("DR14", LIEF::assembly::x86::REG::DR14) + .value("DR15", LIEF::assembly::x86::REG::DR15) + .value("FP0", LIEF::assembly::x86::REG::FP0) + .value("FP1", LIEF::assembly::x86::REG::FP1) + .value("FP2", LIEF::assembly::x86::REG::FP2) + .value("FP3", LIEF::assembly::x86::REG::FP3) + .value("FP4", LIEF::assembly::x86::REG::FP4) + .value("FP5", LIEF::assembly::x86::REG::FP5) + .value("FP6", LIEF::assembly::x86::REG::FP6) + .value("FP7", LIEF::assembly::x86::REG::FP7) + .value("MM0", LIEF::assembly::x86::REG::MM0) + .value("MM1", LIEF::assembly::x86::REG::MM1) + .value("MM2", LIEF::assembly::x86::REG::MM2) + .value("MM3", LIEF::assembly::x86::REG::MM3) + .value("MM4", LIEF::assembly::x86::REG::MM4) + .value("MM5", LIEF::assembly::x86::REG::MM5) + .value("MM6", LIEF::assembly::x86::REG::MM6) + .value("MM7", LIEF::assembly::x86::REG::MM7) + .value("R8", LIEF::assembly::x86::REG::R8) + .value("R9", LIEF::assembly::x86::REG::R9) + .value("R10", LIEF::assembly::x86::REG::R10) + .value("R11", LIEF::assembly::x86::REG::R11) + .value("R12", LIEF::assembly::x86::REG::R12) + .value("R13", LIEF::assembly::x86::REG::R13) + .value("R14", LIEF::assembly::x86::REG::R14) + .value("R15", LIEF::assembly::x86::REG::R15) + .value("ST0", LIEF::assembly::x86::REG::ST0) + .value("ST1", LIEF::assembly::x86::REG::ST1) + .value("ST2", LIEF::assembly::x86::REG::ST2) + .value("ST3", LIEF::assembly::x86::REG::ST3) + .value("ST4", LIEF::assembly::x86::REG::ST4) + .value("ST5", LIEF::assembly::x86::REG::ST5) + .value("ST6", LIEF::assembly::x86::REG::ST6) + .value("ST7", LIEF::assembly::x86::REG::ST7) + .value("XMM0", LIEF::assembly::x86::REG::XMM0) + .value("XMM1", LIEF::assembly::x86::REG::XMM1) + .value("XMM2", LIEF::assembly::x86::REG::XMM2) + .value("XMM3", LIEF::assembly::x86::REG::XMM3) + .value("XMM4", LIEF::assembly::x86::REG::XMM4) + .value("XMM5", LIEF::assembly::x86::REG::XMM5) + .value("XMM6", LIEF::assembly::x86::REG::XMM6) + .value("XMM7", LIEF::assembly::x86::REG::XMM7) + .value("XMM8", LIEF::assembly::x86::REG::XMM8) + .value("XMM9", LIEF::assembly::x86::REG::XMM9) + .value("XMM10", LIEF::assembly::x86::REG::XMM10) + .value("XMM11", LIEF::assembly::x86::REG::XMM11) + .value("XMM12", LIEF::assembly::x86::REG::XMM12) + .value("XMM13", LIEF::assembly::x86::REG::XMM13) + .value("XMM14", LIEF::assembly::x86::REG::XMM14) + .value("XMM15", LIEF::assembly::x86::REG::XMM15) + .value("R8B", LIEF::assembly::x86::REG::R8B) + .value("R9B", LIEF::assembly::x86::REG::R9B) + .value("R10B", LIEF::assembly::x86::REG::R10B) + .value("R11B", LIEF::assembly::x86::REG::R11B) + .value("R12B", LIEF::assembly::x86::REG::R12B) + .value("R13B", LIEF::assembly::x86::REG::R13B) + .value("R14B", LIEF::assembly::x86::REG::R14B) + .value("R15B", LIEF::assembly::x86::REG::R15B) + .value("R8BH", LIEF::assembly::x86::REG::R8BH) + .value("R9BH", LIEF::assembly::x86::REG::R9BH) + .value("R10BH", LIEF::assembly::x86::REG::R10BH) + .value("R11BH", LIEF::assembly::x86::REG::R11BH) + .value("R12BH", LIEF::assembly::x86::REG::R12BH) + .value("R13BH", LIEF::assembly::x86::REG::R13BH) + .value("R14BH", LIEF::assembly::x86::REG::R14BH) + .value("R15BH", LIEF::assembly::x86::REG::R15BH) + .value("R8D", LIEF::assembly::x86::REG::R8D) + .value("R9D", LIEF::assembly::x86::REG::R9D) + .value("R10D", LIEF::assembly::x86::REG::R10D) + .value("R11D", LIEF::assembly::x86::REG::R11D) + .value("R12D", LIEF::assembly::x86::REG::R12D) + .value("R13D", LIEF::assembly::x86::REG::R13D) + .value("R14D", LIEF::assembly::x86::REG::R14D) + .value("R15D", LIEF::assembly::x86::REG::R15D) + .value("R8W", LIEF::assembly::x86::REG::R8W) + .value("R9W", LIEF::assembly::x86::REG::R9W) + .value("R10W", LIEF::assembly::x86::REG::R10W) + .value("R11W", LIEF::assembly::x86::REG::R11W) + .value("R12W", LIEF::assembly::x86::REG::R12W) + .value("R13W", LIEF::assembly::x86::REG::R13W) + .value("R14W", LIEF::assembly::x86::REG::R14W) + .value("R15W", LIEF::assembly::x86::REG::R15W) + .value("R8WH", LIEF::assembly::x86::REG::R8WH) + .value("R9WH", LIEF::assembly::x86::REG::R9WH) + .value("R10WH", LIEF::assembly::x86::REG::R10WH) + .value("R11WH", LIEF::assembly::x86::REG::R11WH) + .value("R12WH", LIEF::assembly::x86::REG::R12WH) + .value("R13WH", LIEF::assembly::x86::REG::R13WH) + .value("R14WH", LIEF::assembly::x86::REG::R14WH) + .value("R15WH", LIEF::assembly::x86::REG::R15WH) + .value("YMM0", LIEF::assembly::x86::REG::YMM0) + .value("YMM1", LIEF::assembly::x86::REG::YMM1) + .value("YMM2", LIEF::assembly::x86::REG::YMM2) + .value("YMM3", LIEF::assembly::x86::REG::YMM3) + .value("YMM4", LIEF::assembly::x86::REG::YMM4) + .value("YMM5", LIEF::assembly::x86::REG::YMM5) + .value("YMM6", LIEF::assembly::x86::REG::YMM6) + .value("YMM7", LIEF::assembly::x86::REG::YMM7) + .value("YMM8", LIEF::assembly::x86::REG::YMM8) + .value("YMM9", LIEF::assembly::x86::REG::YMM9) + .value("YMM10", LIEF::assembly::x86::REG::YMM10) + .value("YMM11", LIEF::assembly::x86::REG::YMM11) + .value("YMM12", LIEF::assembly::x86::REG::YMM12) + .value("YMM13", LIEF::assembly::x86::REG::YMM13) + .value("YMM14", LIEF::assembly::x86::REG::YMM14) + .value("YMM15", LIEF::assembly::x86::REG::YMM15) + .value("K0", LIEF::assembly::x86::REG::K0) + .value("K1", LIEF::assembly::x86::REG::K1) + .value("K2", LIEF::assembly::x86::REG::K2) + .value("K3", LIEF::assembly::x86::REG::K3) + .value("K4", LIEF::assembly::x86::REG::K4) + .value("K5", LIEF::assembly::x86::REG::K5) + .value("K6", LIEF::assembly::x86::REG::K6) + .value("K7", LIEF::assembly::x86::REG::K7) + .value("XMM16", LIEF::assembly::x86::REG::XMM16) + .value("XMM17", LIEF::assembly::x86::REG::XMM17) + .value("XMM18", LIEF::assembly::x86::REG::XMM18) + .value("XMM19", LIEF::assembly::x86::REG::XMM19) + .value("XMM20", LIEF::assembly::x86::REG::XMM20) + .value("XMM21", LIEF::assembly::x86::REG::XMM21) + .value("XMM22", LIEF::assembly::x86::REG::XMM22) + .value("XMM23", LIEF::assembly::x86::REG::XMM23) + .value("XMM24", LIEF::assembly::x86::REG::XMM24) + .value("XMM25", LIEF::assembly::x86::REG::XMM25) + .value("XMM26", LIEF::assembly::x86::REG::XMM26) + .value("XMM27", LIEF::assembly::x86::REG::XMM27) + .value("XMM28", LIEF::assembly::x86::REG::XMM28) + .value("XMM29", LIEF::assembly::x86::REG::XMM29) + .value("XMM30", LIEF::assembly::x86::REG::XMM30) + .value("XMM31", LIEF::assembly::x86::REG::XMM31) + .value("YMM16", LIEF::assembly::x86::REG::YMM16) + .value("YMM17", LIEF::assembly::x86::REG::YMM17) + .value("YMM18", LIEF::assembly::x86::REG::YMM18) + .value("YMM19", LIEF::assembly::x86::REG::YMM19) + .value("YMM20", LIEF::assembly::x86::REG::YMM20) + .value("YMM21", LIEF::assembly::x86::REG::YMM21) + .value("YMM22", LIEF::assembly::x86::REG::YMM22) + .value("YMM23", LIEF::assembly::x86::REG::YMM23) + .value("YMM24", LIEF::assembly::x86::REG::YMM24) + .value("YMM25", LIEF::assembly::x86::REG::YMM25) + .value("YMM26", LIEF::assembly::x86::REG::YMM26) + .value("YMM27", LIEF::assembly::x86::REG::YMM27) + .value("YMM28", LIEF::assembly::x86::REG::YMM28) + .value("YMM29", LIEF::assembly::x86::REG::YMM29) + .value("YMM30", LIEF::assembly::x86::REG::YMM30) + .value("YMM31", LIEF::assembly::x86::REG::YMM31) + .value("ZMM0", LIEF::assembly::x86::REG::ZMM0) + .value("ZMM1", LIEF::assembly::x86::REG::ZMM1) + .value("ZMM2", LIEF::assembly::x86::REG::ZMM2) + .value("ZMM3", LIEF::assembly::x86::REG::ZMM3) + .value("ZMM4", LIEF::assembly::x86::REG::ZMM4) + .value("ZMM5", LIEF::assembly::x86::REG::ZMM5) + .value("ZMM6", LIEF::assembly::x86::REG::ZMM6) + .value("ZMM7", LIEF::assembly::x86::REG::ZMM7) + .value("ZMM8", LIEF::assembly::x86::REG::ZMM8) + .value("ZMM9", LIEF::assembly::x86::REG::ZMM9) + .value("ZMM10", LIEF::assembly::x86::REG::ZMM10) + .value("ZMM11", LIEF::assembly::x86::REG::ZMM11) + .value("ZMM12", LIEF::assembly::x86::REG::ZMM12) + .value("ZMM13", LIEF::assembly::x86::REG::ZMM13) + .value("ZMM14", LIEF::assembly::x86::REG::ZMM14) + .value("ZMM15", LIEF::assembly::x86::REG::ZMM15) + .value("ZMM16", LIEF::assembly::x86::REG::ZMM16) + .value("ZMM17", LIEF::assembly::x86::REG::ZMM17) + .value("ZMM18", LIEF::assembly::x86::REG::ZMM18) + .value("ZMM19", LIEF::assembly::x86::REG::ZMM19) + .value("ZMM20", LIEF::assembly::x86::REG::ZMM20) + .value("ZMM21", LIEF::assembly::x86::REG::ZMM21) + .value("ZMM22", LIEF::assembly::x86::REG::ZMM22) + .value("ZMM23", LIEF::assembly::x86::REG::ZMM23) + .value("ZMM24", LIEF::assembly::x86::REG::ZMM24) + .value("ZMM25", LIEF::assembly::x86::REG::ZMM25) + .value("ZMM26", LIEF::assembly::x86::REG::ZMM26) + .value("ZMM27", LIEF::assembly::x86::REG::ZMM27) + .value("ZMM28", LIEF::assembly::x86::REG::ZMM28) + .value("ZMM29", LIEF::assembly::x86::REG::ZMM29) + .value("ZMM30", LIEF::assembly::x86::REG::ZMM30) + .value("ZMM31", LIEF::assembly::x86::REG::ZMM31) + .value("K0_K1", LIEF::assembly::x86::REG::K0_K1) + .value("K2_K3", LIEF::assembly::x86::REG::K2_K3) + .value("K4_K5", LIEF::assembly::x86::REG::K4_K5) + .value("K6_K7", LIEF::assembly::x86::REG::K6_K7) + .value("TMMCFG", LIEF::assembly::x86::REG::TMMCFG) + .value("TMM0", LIEF::assembly::x86::REG::TMM0) + .value("TMM1", LIEF::assembly::x86::REG::TMM1) + .value("TMM2", LIEF::assembly::x86::REG::TMM2) + .value("TMM3", LIEF::assembly::x86::REG::TMM3) + .value("TMM4", LIEF::assembly::x86::REG::TMM4) + .value("TMM5", LIEF::assembly::x86::REG::TMM5) + .value("TMM6", LIEF::assembly::x86::REG::TMM6) + .value("TMM7", LIEF::assembly::x86::REG::TMM7) + .value("R16", LIEF::assembly::x86::REG::R16) + .value("R17", LIEF::assembly::x86::REG::R17) + .value("R18", LIEF::assembly::x86::REG::R18) + .value("R19", LIEF::assembly::x86::REG::R19) + .value("R20", LIEF::assembly::x86::REG::R20) + .value("R21", LIEF::assembly::x86::REG::R21) + .value("R22", LIEF::assembly::x86::REG::R22) + .value("R23", LIEF::assembly::x86::REG::R23); + reg.value("R24", LIEF::assembly::x86::REG::R24) + .value("R25", LIEF::assembly::x86::REG::R25) + .value("R26", LIEF::assembly::x86::REG::R26) + .value("R27", LIEF::assembly::x86::REG::R27) + .value("R28", LIEF::assembly::x86::REG::R28) + .value("R29", LIEF::assembly::x86::REG::R29) + .value("R30", LIEF::assembly::x86::REG::R30) + .value("R31", LIEF::assembly::x86::REG::R31) + .value("R16B", LIEF::assembly::x86::REG::R16B) + .value("R17B", LIEF::assembly::x86::REG::R17B) + .value("R18B", LIEF::assembly::x86::REG::R18B) + .value("R19B", LIEF::assembly::x86::REG::R19B) + .value("R20B", LIEF::assembly::x86::REG::R20B) + .value("R21B", LIEF::assembly::x86::REG::R21B) + .value("R22B", LIEF::assembly::x86::REG::R22B) + .value("R23B", LIEF::assembly::x86::REG::R23B) + .value("R24B", LIEF::assembly::x86::REG::R24B) + .value("R25B", LIEF::assembly::x86::REG::R25B) + .value("R26B", LIEF::assembly::x86::REG::R26B) + .value("R27B", LIEF::assembly::x86::REG::R27B) + .value("R28B", LIEF::assembly::x86::REG::R28B) + .value("R29B", LIEF::assembly::x86::REG::R29B) + .value("R30B", LIEF::assembly::x86::REG::R30B) + .value("R31B", LIEF::assembly::x86::REG::R31B) + .value("R16BH", LIEF::assembly::x86::REG::R16BH) + .value("R17BH", LIEF::assembly::x86::REG::R17BH) + .value("R18BH", LIEF::assembly::x86::REG::R18BH) + .value("R19BH", LIEF::assembly::x86::REG::R19BH) + .value("R20BH", LIEF::assembly::x86::REG::R20BH) + .value("R21BH", LIEF::assembly::x86::REG::R21BH) + .value("R22BH", LIEF::assembly::x86::REG::R22BH) + .value("R23BH", LIEF::assembly::x86::REG::R23BH) + .value("R24BH", LIEF::assembly::x86::REG::R24BH) + .value("R25BH", LIEF::assembly::x86::REG::R25BH) + .value("R26BH", LIEF::assembly::x86::REG::R26BH) + .value("R27BH", LIEF::assembly::x86::REG::R27BH) + .value("R28BH", LIEF::assembly::x86::REG::R28BH) + .value("R29BH", LIEF::assembly::x86::REG::R29BH) + .value("R30BH", LIEF::assembly::x86::REG::R30BH) + .value("R31BH", LIEF::assembly::x86::REG::R31BH) + .value("R16D", LIEF::assembly::x86::REG::R16D) + .value("R17D", LIEF::assembly::x86::REG::R17D) + .value("R18D", LIEF::assembly::x86::REG::R18D) + .value("R19D", LIEF::assembly::x86::REG::R19D) + .value("R20D", LIEF::assembly::x86::REG::R20D) + .value("R21D", LIEF::assembly::x86::REG::R21D) + .value("R22D", LIEF::assembly::x86::REG::R22D) + .value("R23D", LIEF::assembly::x86::REG::R23D) + .value("R24D", LIEF::assembly::x86::REG::R24D) + .value("R25D", LIEF::assembly::x86::REG::R25D) + .value("R26D", LIEF::assembly::x86::REG::R26D) + .value("R27D", LIEF::assembly::x86::REG::R27D) + .value("R28D", LIEF::assembly::x86::REG::R28D) + .value("R29D", LIEF::assembly::x86::REG::R29D) + .value("R30D", LIEF::assembly::x86::REG::R30D) + .value("R31D", LIEF::assembly::x86::REG::R31D) + .value("R16W", LIEF::assembly::x86::REG::R16W) + .value("R17W", LIEF::assembly::x86::REG::R17W) + .value("R18W", LIEF::assembly::x86::REG::R18W) + .value("R19W", LIEF::assembly::x86::REG::R19W) + .value("R20W", LIEF::assembly::x86::REG::R20W) + .value("R21W", LIEF::assembly::x86::REG::R21W) + .value("R22W", LIEF::assembly::x86::REG::R22W) + .value("R23W", LIEF::assembly::x86::REG::R23W) + .value("R24W", LIEF::assembly::x86::REG::R24W) + .value("R25W", LIEF::assembly::x86::REG::R25W) + .value("R26W", LIEF::assembly::x86::REG::R26W) + .value("R27W", LIEF::assembly::x86::REG::R27W) + .value("R28W", LIEF::assembly::x86::REG::R28W) + .value("R29W", LIEF::assembly::x86::REG::R29W) + .value("R30W", LIEF::assembly::x86::REG::R30W) + .value("R31W", LIEF::assembly::x86::REG::R31W) + .value("R16WH", LIEF::assembly::x86::REG::R16WH) + .value("R17WH", LIEF::assembly::x86::REG::R17WH) + .value("R18WH", LIEF::assembly::x86::REG::R18WH) + .value("R19WH", LIEF::assembly::x86::REG::R19WH) + .value("R20WH", LIEF::assembly::x86::REG::R20WH) + .value("R21WH", LIEF::assembly::x86::REG::R21WH) + .value("R22WH", LIEF::assembly::x86::REG::R22WH) + .value("R23WH", LIEF::assembly::x86::REG::R23WH) + .value("R24WH", LIEF::assembly::x86::REG::R24WH) + .value("R25WH", LIEF::assembly::x86::REG::R25WH) + .value("R26WH", LIEF::assembly::x86::REG::R26WH) + .value("R27WH", LIEF::assembly::x86::REG::R27WH) + .value("R28WH", LIEF::assembly::x86::REG::R28WH) + .value("R29WH", LIEF::assembly::x86::REG::R29WH) + .value("R30WH", LIEF::assembly::x86::REG::R30WH) + .value("R31WH", LIEF::assembly::x86::REG::R31WH) + .value("NUM_TARGET_REGS", LIEF::assembly::x86::REG::NUM_TARGET_REGS) + ; +} +} diff --git a/vendor/lief/api/python/src/enums_wrapper.hpp b/vendor/lief/api/python/src/enums_wrapper.hpp new file mode 100644 index 0000000..c22f697 --- /dev/null +++ b/vendor/lief/api/python/src/enums_wrapper.hpp @@ -0,0 +1,60 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ENUMS_WRAPPER_H +#define PY_LIEF_ENUMS_WRAPPER_H +#include +#include + +#include "LIEF/visibility.h" + +namespace nb = nanobind; + +namespace LIEF { + +template +class LIEF_LOCAL enum_ : public nanobind::enum_ { + public: + using Base = typename nanobind::enum_::Base; + using Underlying = typename nanobind::enum_::Underlying; + using nanobind::enum_::def_prop_ro; + using nanobind::enum_::def_static; + using nanobind::enum_::def; + + template + NB_INLINE enum_(nanobind::handle scope, const char *name, const Extra &... extra) : + nanobind::enum_{scope, name, extra...} + { + def_static("from_value", [] (Underlying i) -> Type { + nb::object out = nb::cast(static_cast(i)); + if (nb::isinstance(out)) { + throw nb::value_error("Conversion error"); + } + return static_cast(i); + }); + + def("__eq__", [](const Type &value, Underlying value2) { return (Underlying) value == value2; }); + def("__eq__", [](const Type &value, Type value2) { return (Underlying) value == (Underlying) value2; }); + + def("__ne__", [](const Type &value, Underlying value2) { return (Underlying) value != value2; }); + def("__ne__", [](const Type &value, Type value2) { return (Underlying) value != (Underlying) value2; }); + + def("__int__", [](const Type &value) { return (Underlying) value; }); + } +}; + +} + +#endif diff --git a/vendor/lief/api/python/src/nanobind/extra/memoryview.hpp b/vendor/lief/api/python/src/nanobind/extra/memoryview.hpp new file mode 100644 index 0000000..3b6dc09 --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/memoryview.hpp @@ -0,0 +1,85 @@ +#ifndef PY_LIEF_MEMORY_VIEW_H +#define PY_LIEF_MEMORY_VIEW_H + +#include + +NAMESPACE_BEGIN(NB_NAMESPACE) + +namespace extra { +/* the memoryview wrapper class has been introduced in nanobind with the commit + * 7206bc2 but it misses important helpers like data(). + * + * Tracked by the discussion: https://github.com/wjakob/nanobind/discussions/233 + * PR: https://github.com/wjakob/nanobind/pull/1291 + */ +class memoryview : public object { + using ssize_t = Py_ssize_t; +public: + NB_OBJECT(memoryview, object, "memoryview", PyMemoryView_Check) + + memoryview(const object &o) + : object(check_(o) ? o.inc_ref().ptr() : + PyMemoryView_FromObject(o.ptr()), detail::steal_t{}) { + if (!m_ptr) + detail::raise_python_error(); + } + + memoryview(object &&o) + : object(check_(o) ? o.release().ptr() : + PyMemoryView_FromObject(o.ptr()), detail::steal_t{}) { + + if (!m_ptr) + detail::raise_python_error(); + } + + static memoryview from_memory(void *mem, ssize_t size, bool readonly = false) { + PyObject *ptr = PyMemoryView_FromMemory( + reinterpret_cast(mem), size, (readonly) ? PyBUF_READ : PyBUF_WRITE); + if (!ptr) { + detail::raise_python_error(); + } + return memoryview(object(ptr, detail::steal_t{})); + } + + static memoryview from_memory(const void *mem, ssize_t size) { + return memoryview::from_memory(const_cast(mem), size, true); + } + + const uint8_t* data() const { +#if defined(Py_LIMITED_API) + Py_buffer view; + if (PyObject_GetBuffer(ptr(), &view, PyBUF_SIMPLE) != 0) { + detail::raise_python_error(); + } + + auto* buf_ptr = static_cast(view.buf); + + PyBuffer_Release(&view); + return buf_ptr; +#else + return (const uint8_t*)PyMemoryView_GET_BUFFER(this->ptr())->buf; +#endif + } + + size_t size() const { +#if defined(Py_LIMITED_API) + Py_buffer view; + if (PyObject_GetBuffer(ptr(), &view, PyBUF_SIMPLE) != 0) { + detail::raise_python_error(); + } + + size_t len = static_cast(view.len); + + PyBuffer_Release(&view); + return len; +#else + return PyMemoryView_GET_BUFFER(ptr())->len; +#endif + } +}; + +} + +NAMESPACE_END(NB_NAMESPACE) + +#endif diff --git a/vendor/lief/api/python/src/nanobind/extra/random_access_iterator.hpp b/vendor/lief/api/python/src/nanobind/extra/random_access_iterator.hpp new file mode 100644 index 0000000..13e33bb --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/random_access_iterator.hpp @@ -0,0 +1,106 @@ +#ifndef PY_LIEF_RANDOM_ACCESS_IT_H +#define PY_LIEF_RANDOM_ACCESS_IT_H + +#include +#include + +NAMESPACE_BEGIN(NB_NAMESPACE) +namespace detail { +template +class TypedRandomIterator : public nanobind::iterator { + public: + static constexpr auto Name = const_name("collections.abc.Sequence[") + make_caster::Name + const_name("]"); + TypedRandomIterator(nanobind::iterator&& it) : + nanobind::iterator::iterator(std::move(it)) + {} +}; + +template +struct random_iterator_state { + Iterator it; + Iterator begin; + Sentinel end; + bool first_or_done; +}; + +template +iterator make_rnd_iterator_impl(handle scope, const char *name, + Iterator &&first, Sentinel &&last, + Extra &&...extra) { + using State = random_iterator_state; + + static ft_mutex mu; + ft_lock_guard lock(mu); + + if (!type().is_valid()) { + class_(scope, name) + .def("__iter__", [](handle h) { return h; }) + .def("__len__", [](State &s) { return std::distance(s.begin, s.end); }) + .def("__getitem__", + [] (State& s, Py_ssize_t i) -> ValueType { + const size_t size = std::distance(s.begin, s.end); + if (i < 0) { + i += static_cast(size); + } + if (i < 0 || static_cast(i) >= size) { + throw nanobind::index_error(); + } + Iterator it = s.begin + i; + return Access()(it); + }, std::forward(extra)..., rv_policy::policy_tag()) + + .def("__next__", + [](State &s) -> iter_result { + if (!s.first_or_done) + ++s.it; + else + s.first_or_done = false; + + if (s.it == s.end) { + s.first_or_done = true; + return { }; + } + + return Access()(s.it); + }, + std::forward(extra)..., + rv_policy::policy_tag()); + } + auto begin = first; + return borrow(cast(State{ std::forward(first), + std::move(begin), + std::forward(last), true })); +} +} + + +template ::result_type, + typename... Extra> +detail::TypedRandomIterator make_random_access_iterator(handle scope, const char *name, Iterator &&first, Sentinel &&last, Extra &&...extra) { + return detail::make_rnd_iterator_impl, Policy, + Iterator, Sentinel, ValueType, Extra...>( + scope, name, std::forward(first), + std::forward(last), std::forward(extra)...); +} + +template ::result_type, + typename... Extra> +detail::TypedRandomIterator make_random_access_iterator( + handle scope, const char *name, Type &value, Extra &&...extra) +{ + return make_random_access_iterator( + scope, name, std::begin(value), std::end(value), + std::forward(extra)... + ); +} + +NAMESPACE_END(NB_NAMESPACE) + +#endif diff --git a/vendor/lief/api/python/src/nanobind/extra/stl/lief_result.h b/vendor/lief/api/python/src/nanobind/extra/stl/lief_result.h new file mode 100644 index 0000000..328589d --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/stl/lief_result.h @@ -0,0 +1,50 @@ +#pragma once + +#include +#include + +#include "LIEF/errors.hpp" + +NAMESPACE_BEGIN(NB_NAMESPACE) +NAMESPACE_BEGIN(detail) + +template +struct type_caster> { + using Caster = make_caster; + using ErrCaster = make_caster; + NB_TYPE_CASTER(LIEF::result, + const_name("Union[") + Caster::Name + const_name(",") + const_name("lief.lief_errors") + const_name("]")); + + + bool from_python(handle src, uint32_t flags, cleanup_list * cleanup) noexcept { + Caster caster; + if (!caster.from_python(src, flags_for_local_caster(flags), cleanup) || + !caster.template can_cast()) + { + ErrCaster err_caster; + if (!err_caster.from_python(src, flags_for_local_caster(flags), cleanup) || + !err_caster.template can_cast()) + { + value.emplace(err_caster.operator cast_t()); + return true; + } + return false; + } + + value.emplace(caster.operator cast_t()); + return true; + } + + template + static handle from_cpp(T_ &&value, rv_policy policy, cleanup_list *cleanup) noexcept + { + if (value) { + return Caster::from_cpp(forward_like_(*value), policy, cleanup); + } + + return ErrCaster::from_cpp(forward_like_(get_error(value)), policy, cleanup); + } +}; + +NAMESPACE_END(detail) +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/nanobind/extra/stl/lief_span.h b/vendor/lief/api/python/src/nanobind/extra/stl/lief_span.h new file mode 100644 index 0000000..6a36d45 --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/stl/lief_span.h @@ -0,0 +1,38 @@ +#pragma once + +#include + +#include "LIEF/span.hpp" + +NAMESPACE_BEGIN(NB_NAMESPACE) +NAMESPACE_BEGIN(detail) + +template +struct type_caster> { + static_assert(std::is_same_v> || + std::is_same_v>, + "Need uint8_t type"); + + static constexpr auto IsRO = std::is_const_v; + + NB_TYPE_CASTER(LIEF::span, const_name("memoryview")); + + bool from_python(handle /*src*/, uint32_t, cleanup_list *) noexcept { + return false; + } + + static handle from_cpp(LIEF::span val, rv_policy, + cleanup_list *) noexcept { + static const uint8_t empty = 0; + void* mem = (void*)val.data(); + if (val.empty()) { + mem = (void*)∅ + } + + return PyMemoryView_FromMemory( + reinterpret_cast(mem), val.size(), IsRO ? PyBUF_READ : PyBUF_WRITE); + } +}; + +NAMESPACE_END(detail) +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/nanobind/extra/stl/pathlike.h b/vendor/lief/api/python/src/nanobind/extra/stl/pathlike.h new file mode 100644 index 0000000..3aae1f1 --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/stl/pathlike.h @@ -0,0 +1,35 @@ +#pragma once + +#include +#include + +#include + +#include "typing.hpp" +#include "pyutils.hpp" + +NAMESPACE_BEGIN(NB_NAMESPACE) + +struct PathLike : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(PathLike, nanobind::object); + + NB_OBJECT_DEFAULT(PathLike, object, "Union[str | os.PathLike]", check) + + std::string to_string() const { + if (nb::isinstance(*this)) { + return nb::cast(*this); + } + auto path_str = LIEF::py::path_to_str(*this); + assert(path_str); + return *path_str; + } + + operator std::string() const { return to_string(); } + + static bool check(handle h) { + return nb::isinstance(h) || + LIEF::py::path_to_str(nb::object(h, nb::detail::borrow_t{})); + } +}; + +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/nanobind/extra/stl/u16string.h b/vendor/lief/api/python/src/nanobind/extra/stl/u16string.h new file mode 100644 index 0000000..bb7e6a4 --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/stl/u16string.h @@ -0,0 +1,41 @@ +#pragma once + +#include +#include + +NAMESPACE_BEGIN(NB_NAMESPACE) +NAMESPACE_BEGIN(detail) + +template <> struct type_caster { + using ssize_t = Py_ssize_t; + using CharT = typename std::u16string::value_type; + NB_TYPE_CASTER(std::u16string, const_name("str")); + + bool from_python(handle src, uint32_t, cleanup_list *) noexcept { + const object Nbytes = steal(PyUnicode_AsUTF16String(src.ptr())); + if (!Nbytes) { + PyErr_Clear(); + return false; + } + const auto *buffer + = reinterpret_cast(PyBytes_AsString(Nbytes.ptr())); + + size_t length = (size_t) PyBytes_Size(Nbytes.ptr()) / sizeof(CharT); + + // Skip BOM + buffer++; + length--; + value = std::u16string(buffer, length); + return true; + } + + static handle from_cpp(const std::u16string &value, rv_policy, + cleanup_list *) noexcept { + const auto *buffer = reinterpret_cast(value.data()); + auto nbytes = ssize_t(value.size() * sizeof(CharT)); + return PyUnicode_DecodeUTF16(buffer, nbytes, nullptr, nullptr); + } +}; + +NAMESPACE_END(detail) +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/nanobind/extra/stl/wstring.h b/vendor/lief/api/python/src/nanobind/extra/stl/wstring.h new file mode 100644 index 0000000..bf1208d --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/extra/stl/wstring.h @@ -0,0 +1,30 @@ +#pragma once + +#include +#include + +NAMESPACE_BEGIN(NB_NAMESPACE) +NAMESPACE_BEGIN(detail) + +template <> struct type_caster { + NB_TYPE_CASTER(std::wstring, const_name("Union[str, bytes]")); + + bool from_python(handle src, uint32_t, cleanup_list *) noexcept { + Py_ssize_t size; + const wchar_t *str = PyUnicode_AsWideCharString(src.ptr(), &size); + if (str == nullptr) { + PyErr_Clear(); + return false; + } + value = std::wstring(str, (size_t) size); + return true; + } + + static handle from_cpp(const std::wstring &value, rv_policy, + cleanup_list *) noexcept { + return PyUnicode_FromWideChar(value.c_str(), value.size()); + } +}; + +NAMESPACE_END(detail) +NAMESPACE_END(NB_NAMESPACE) diff --git a/vendor/lief/api/python/src/nanobind/utils.hpp b/vendor/lief/api/python/src/nanobind/utils.hpp new file mode 100644 index 0000000..ab0cc04 --- /dev/null +++ b/vendor/lief/api/python/src/nanobind/utils.hpp @@ -0,0 +1,50 @@ +#ifndef PY_LIEF_NB_UTILS_H +#define PY_LIEF_NB_UTILS_H + +#include +#include +#include +#include +#include + +#include "nanobind/extra/memoryview.hpp" + +NAMESPACE_BEGIN(NB_NAMESPACE) + +inline nanobind::bytes to_bytes(const std::vector& vec) { + return nanobind::bytes(reinterpret_cast(vec.data()), vec.size()); +} + +inline nanobind::bytes to_bytes(LIEF::span sp) { + return nanobind::bytes(reinterpret_cast(sp.data()), sp.size()); +} + +inline nanobind::bytes to_bytes(const std::string& str) { + return nanobind::bytes(str.data(), str.size()); +} + +inline nanobind::bytes to_bytes(const std::string_view& str) { + return nanobind::bytes(str.data(), str.size()); +} + +inline nanobind::extra::memoryview to_memoryview(LIEF::span sp) { + return nanobind::extra::memoryview::from_memory(sp.data(), sp.size()); +} + +inline nanobind::extra::memoryview to_memoryview(const std::vector& vec) { + return nanobind::extra::memoryview::from_memory(vec.data(), vec.size()); +} + +inline std::vector to_vector(nanobind::bytes bytes) { + const auto* ptr = reinterpret_cast(bytes.c_str()); + return {ptr, ptr + bytes.size()}; +} + +inline std::unique_ptr to_stream(nanobind::bytes bytes) { + const auto* ptr = reinterpret_cast(bytes.c_str()); + return std::make_unique(ptr, bytes.size()); +} + +NAMESPACE_END(NB_NAMESPACE) + +#endif diff --git a/vendor/lief/api/python/src/platforms/CMakeLists.txt b/vendor/lief/api/python/src/platforms/CMakeLists.txt new file mode 100644 index 0000000..cb5b131 --- /dev/null +++ b/vendor/lief/api/python/src/platforms/CMakeLists.txt @@ -0,0 +1,4 @@ +target_sources(pyLIEF PRIVATE + pyPlatform.cpp +) +add_subdirectory(android) diff --git a/vendor/lief/api/python/src/platforms/android/CMakeLists.txt b/vendor/lief/api/python/src/platforms/android/CMakeLists.txt new file mode 100644 index 0000000..ca62090 --- /dev/null +++ b/vendor/lief/api/python/src/platforms/android/CMakeLists.txt @@ -0,0 +1,4 @@ +target_sources(pyLIEF PRIVATE + pyAndroid.cpp +) + diff --git a/vendor/lief/api/python/src/platforms/android/pyAndroid.cpp b/vendor/lief/api/python/src/platforms/android/pyAndroid.cpp new file mode 100644 index 0000000..604c5c4 --- /dev/null +++ b/vendor/lief/api/python/src/platforms/android/pyAndroid.cpp @@ -0,0 +1,60 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/platforms/android/version.hpp" + +#include "enums_wrapper.hpp" +#include "platforms/android/pyAndroid.hpp" +#include "pyLIEF.hpp" + +#define PY_ENUM(x) to_string(x), x + +namespace LIEF::Android::py { + +void init_versions(nb::module_& m) { + enum_(m, "ANDROID_VERSIONS") + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_UNKNOWN)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_601)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_700)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_710)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_712)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_800)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_810)) + .value(PY_ENUM(ANDROID_VERSIONS::VERSION_900)); + + m.def("code_name", + &code_name, + R"delim( + Return the Android code associated with a :class:`~.ANDROID_VERSIONS`. + + For example: ``Nougat`` + )delim"_doc, "version"_a); + + m.def("version_string", + &version_string, + R"delim( + Return the :class:`~.ANDROID_VERSIONS` as a string. + + For example: ``7.0.1`` + )delim"_doc, "version"_a); +} + + +void init_module(nb::module_& m) { + nb::module_ android = m.def_submodule("Android", "Python API for Android platform"); + + init_versions(android); +} +} diff --git a/vendor/lief/api/python/src/platforms/android/pyAndroid.hpp b/vendor/lief/api/python/src/platforms/android/pyAndroid.hpp new file mode 100644 index 0000000..ef5cf8d --- /dev/null +++ b/vendor/lief/api/python/src/platforms/android/pyAndroid.hpp @@ -0,0 +1,27 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ANDROID_H +#define PY_LIEF_ANDROID_H + +namespace nanobind { +class module_; +} + +namespace LIEF::Android::py { +void init_module(nanobind::module_&); +} + +#endif diff --git a/vendor/lief/api/python/src/platforms/pyPlatform.cpp b/vendor/lief/api/python/src/platforms/pyPlatform.cpp new file mode 100644 index 0000000..7c45106 --- /dev/null +++ b/vendor/lief/api/python/src/platforms/pyPlatform.cpp @@ -0,0 +1,39 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "platforms/pyPlatform.hpp" +#include "LIEF/platforms.hpp" +#include "enums_wrapper.hpp" +#include "pyLIEF.hpp" +#include "platforms/android/pyAndroid.hpp" + +namespace LIEF::py { + +void init_platforms(nb::module_& m) { + LIEF::enum_(m, "PLATFORMS") + .value("UNKNOWN", PLATFORMS::PLAT_WINDOWS) + .value("LINUX", PLATFORMS::PLAT_LINUX) + .value("ANDROID", PLATFORMS::PLAT_ANDROID) + .value("WINDOWS", PLATFORMS::PLAT_WINDOWS) + .value("IOS", PLATFORMS::PLAT_IOS) + .value("OSX", PLATFORMS::PLAT_OSX); + + m.def("current_platform", ¤t_platform, + "Return the current platform (Linux, Windows, ...) as a :attr:`lief.PLATFORMS` enum"_doc); + + LIEF::Android::py::init_module(m); +} + +} diff --git a/vendor/lief/api/python/src/platforms/pyPlatform.hpp b/vendor/lief/api/python/src/platforms/pyPlatform.hpp new file mode 100644 index 0000000..3c47908 --- /dev/null +++ b/vendor/lief/api/python/src/platforms/pyPlatform.hpp @@ -0,0 +1,27 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_PLATFORM_H +#define PY_LIEF_PLATFORM_H + +namespace nanobind { +class module_; +} + +namespace LIEF::py { +void init_platforms(nanobind::module_&); +} + +#endif diff --git a/vendor/lief/api/python/src/pyDebugDeclOpt.cpp b/vendor/lief/api/python/src/pyDebugDeclOpt.cpp new file mode 100644 index 0000000..13acaa8 --- /dev/null +++ b/vendor/lief/api/python/src/pyDebugDeclOpt.cpp @@ -0,0 +1,135 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/DebugDeclOpt.hpp" +#include "pyLIEF.hpp" + +#include + +#include +#include + +namespace LIEF::py { +template<> +void create(nb::module_& m) { + nb::class_(m, "DeclOpt", + R"doc( + Configuration options for generated code from debug info. + + This structure configures how the debug information (DWARF/PDB) translated + into an AST is generated. You can use it to configure the indentation, and + the information to generate when translating DWARF/PDB into C++-like + definitions + )doc"_doc) + + .def(nb::init<>()) + + .def_prop_rw("indentation", + nb::overload_cast<>(&DeclOpt::indentation, nb::const_), + nb::overload_cast(&DeclOpt::indentation), + "The number of spaces for indentation."_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("is_cpp", + nb::overload_cast<>(&DeclOpt::is_cpp, nb::const_), + nb::overload_cast(&DeclOpt::is_cpp), + R"doc( + Prefer C++ syntax over C syntax. + + If true, the output will use C++ features (e.g., ``bool`` keyword) + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("show_extended_annotations", + nb::overload_cast<>(&DeclOpt::show_extended_annotations, nb::const_), + nb::overload_cast(&DeclOpt::show_extended_annotations), + R"doc( + Enable extended comments and annotations. + + If true, the generated code will include comments containing low-level + details such as memory addresses, offsets, type sizes, and original + source locations. + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("include_types", + nb::overload_cast<>(&DeclOpt::include_types, nb::const_), + nb::overload_cast(&DeclOpt::include_types), + R"doc( + Include full type definitions. + + If true, the output will contain the full definition of types (structs, + enums, unions). + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("include_locals", + nb::overload_cast<>(&DeclOpt::include_locals, nb::const_), + nb::overload_cast(&DeclOpt::include_locals), + R"doc( + Emit a function body listing its local / stack variables. + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("desugar", + nb::overload_cast<>(&DeclOpt::desugar, nb::const_), + nb::overload_cast(&DeclOpt::desugar), + R"doc( + Resolve type aliases (sugar). + + If true, typedef and type aliases are replaced by their underlying + canonical types (e.g., ``uint32_t`` might become ``unsigned int``). + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("show_field_offsets", + nb::overload_cast<>(&DeclOpt::show_field_offsets, nb::const_), + nb::overload_cast(&DeclOpt::show_field_offsets), + R"doc( + Show the relative offset of each field/attribute in structures. + + If true, every member of a structure is prefixed with its byte offset + (e.g. ``/* 0x04 */``). + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def_prop_rw("type_aliases", + nb::overload_cast<>(&DeclOpt::type_aliases, nb::const_), + nb::overload_cast(&DeclOpt::type_aliases), + R"doc( + Mapping of type names to user-friendly aliases used while + rendering types (e.g. + ``std::basic_string`` -> ``std::string``). + )doc"_doc, + nb::rv_policy::reference_internal + ) + + .def("add_type_alias", + [] (DeclOpt& self, std::string name, std::string alias) -> DeclOpt& { + return self.add_type_alias(std::move(name), std::move(alias)); + }, + "name"_a, "alias"_a, + "Register a single type alias (see :attr:`~.type_aliases`)."_doc, + nb::rv_policy::reference_internal + ) + ; +} +} diff --git a/vendor/lief/api/python/src/pyErr.cpp b/vendor/lief/api/python/src/pyErr.cpp new file mode 100644 index 0000000..e258d1a --- /dev/null +++ b/vendor/lief/api/python/src/pyErr.cpp @@ -0,0 +1,45 @@ +#include "pyErr.hpp" +#include "pyLIEF.hpp" + +namespace LIEF::py { +void init_errors(nb::module_& m) { + nb::class_(m, "ok_t", + R"delim( + Opaque value returned when a **void** function + is executed successfully. + )delim") + .def("__bool__", [] (const ok_t&) { return true; }); + + nb::class_(m, "ok_error_t", + R"delim( + Return either: :class:`~.ok_t` (success) or :class:`~.lief_errors` (error) + )delim") + .def_prop_ro("is_error", [] (const ok_error_t& val) { return !val.has_value(); }) + .def_prop_ro("is_value", [] (const ok_error_t& val) { return val.has_value(); }) + .def_prop_ro("error", [] (const ok_error_t& val) { return val.error(); }) + .def_prop_ro("value", [] (const ok_error_t& val) { return val.value(); }) + .def("__bool__", [] (const ok_error_t& val) { return val.has_value(); }); + + + nb::enum_(m, "lief_errors", R"delim( + Enum class which represents an error generated by LIEF's functions + )delim") + .value("read_error", lief_errors::read_error) + .value("not_found", lief_errors::not_found) + .value("not_implemented", lief_errors::not_implemented) + .value("not_supported", lief_errors::not_supported) + .value("corrupted", lief_errors::corrupted) + .value("conversion_error", lief_errors::conversion_error) + .value("read_out_of_bound", lief_errors::read_out_of_bound) + .value("asn1_bad_tag", lief_errors::asn1_bad_tag) + .value("file_error", lief_errors::file_error) + .value("file_format_error", lief_errors::file_format_error) + .value("parsing_error", lief_errors::parsing_error) + .value("build_error", lief_errors::build_error) + .value("data_too_large", lief_errors::data_too_large) + .value("require_extended_version", lief_errors::require_extended_version) + .value("inconsistent", lief_errors::inconsistent) + .value("runtime_error", lief_errors::runtime_error) + ; +} +} diff --git a/vendor/lief/api/python/src/pyErr.hpp b/vendor/lief/api/python/src/pyErr.hpp new file mode 100644 index 0000000..c9a0ae0 --- /dev/null +++ b/vendor/lief/api/python/src/pyErr.hpp @@ -0,0 +1,107 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ERROR_H +#define PY_LIEF_ERROR_H + +#include +#include "LIEF/errors.hpp" + +#include "typing.hpp" + +namespace LIEF::py { +template +struct typing_error : public nanobind::object { + using value_type = typename RetTy::value_type; + using err_type = typename RetTy::error_type; + + static constexpr auto Name = nanobind::detail::const_name("Union[") + + nanobind::detail::make_caster::Name + + nanobind::detail::const_name(", ") + + nanobind::detail::make_caster::Name + + nanobind::detail::const_name("]"); + + LIEF_PY_DEFAULT_CTOR(typing_error, nanobind::object); + NB_OBJECT_DEFAULT_NONAME(typing_error, object, check) + + static bool check(handle /*h*/) { + return true; + } +}; + +template +struct value_or_none_t : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(value_or_none_t, nanobind::object); + using value_type = typename RetTy::value_type; + + static constexpr auto Name = nanobind::detail::const_name("Optional[") + + nanobind::detail::make_caster::Name + + nanobind::detail::const_name("]"); + + NB_OBJECT_DEFAULT_NONAME(value_or_none_t, object, check) + static bool check(handle /*h*/) { + return true; + } +}; + + +template , + std::enable_if_t>{}, int> = 0> +typing_error error_or(Func f, Ts&&... args) { + namespace nb = nanobind; + auto&& ret = f(std::forward(args)...); + if (!ret) { + return nb::cast(as_lief_err(ret)); + } + return nb::cast(ret.value()); +} + +template , + std::enable_if_t>{}, int> = 0> +typing_error error_or(Func f, Ts&&... args) { + namespace nb = nanobind; + auto&& ret = std::mem_fn(f)(std::forward(args)...); + if (!ret) { + return nb::cast(LIEF::as_lief_err(ret)); + } + return nb::cast(ret.value()); +} + + +template > +value_or_none_t value_or_none(Func f, Ts&&... args) { + namespace nb = nanobind; + if constexpr (std::is_member_pointer_v>) { + auto&& ret = std::mem_fn(f)(std::forward(args)...); + if (!ret) { + return nb::none(); + } + return nb::cast(*ret); + } else { + auto&& ret = f(std::forward(args)...); + if (!ret) { + return nb::none(); + } + return nb::cast(*ret); + } +} + +void init_errors(nanobind::module_&); +} + +#endif diff --git a/vendor/lief/api/python/src/pyIOStream.cpp b/vendor/lief/api/python/src/pyIOStream.cpp new file mode 100644 index 0000000..05b8af4 --- /dev/null +++ b/vendor/lief/api/python/src/pyIOStream.cpp @@ -0,0 +1,77 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pyIOStream.hpp" +#include "nanobind/extra/memoryview.hpp" +#include "pyutils.hpp" +#include "LIEF/logging.hpp" + +static constexpr int PY_SEEK_SET = 0; +static constexpr int PY_SEEK_END = 2; + +namespace LIEF::py { +PyIOStream::PyIOStream(PyIOStream&& other) = default; +PyIOStream& PyIOStream::operator=(PyIOStream&& other) = default; + +result PyIOStream::from_python(nb::object object) { + const nb::module_ mod_io = nb::module_::import_("io"); + const nb::object IOBase = mod_io.attr("IOBase"); + + if (!nb::isinstance(object, IOBase)) { + logging::log(logging::Level::Err, + "The provided io object does not sub-class io.IOBase"); + return make_error_code(lief_errors::read_error); + } + + if (!nb::hasattr(object, "read") && !nb::hasattr(object, "readinto")) { + logging::log(logging::Level::Err, + "The provided io object does not implement read() or readinto()"); + return make_error_code(lief_errors::read_error); + } + + auto seek = object.attr("seek"); + seek(0, PY_SEEK_SET); + seek(0, PY_SEEK_END); + const auto size = nb::cast(object.attr("tell")()); + + if (size == 0) { + return PyIOStream(std::move(object), {}); + } + + std::vector data; + data.resize(size); + + seek(0, PY_SEEK_SET); + if (nb::hasattr(object, "readinto")) { + auto view = nb::extra::memoryview::from_memory(data.data(), size); + object.attr("readinto")(view); + } + else if (nb::hasattr(object, "read")) { + auto content = nb::cast(object.attr("read")(size)); + std::string tmp(content.c_str(), content.size()); + std::move(std::begin(tmp), std::end(tmp), data.data()); + } + + return PyIOStream(std::move(object), std::move(data)); +} + +PyIOStream::PyIOStream(nb::object io, std::vector data) : + VectorStream(std::move(data)), + io_{std::move(io)} +{} + + +PyIOStream::~PyIOStream() = default; +} diff --git a/vendor/lief/api/python/src/pyIOStream.hpp b/vendor/lief/api/python/src/pyIOStream.hpp new file mode 100644 index 0000000..0ea5135 --- /dev/null +++ b/vendor/lief/api/python/src/pyIOStream.hpp @@ -0,0 +1,46 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_PY_IO_STREAM_H +#define LIEF_PY_IO_STREAM_H + +#include +#include + +#include "LIEF/errors.hpp" +#include "LIEF/BinaryStream/VectorStream.hpp" +#include "pyLIEF.hpp" + +namespace LIEF::py { +class PyIOStream : public VectorStream { + public: + static result from_python(nb::object object); + PyIOStream() = delete; + + PyIOStream(const PyIOStream&) = delete; + PyIOStream& operator=(const PyIOStream&) = delete; + + PyIOStream(PyIOStream&& other); + PyIOStream& operator=(PyIOStream&& other); + + ~PyIOStream() override; + + protected: + PyIOStream(nb::object io, std::vector data); + nb::object io_; +}; +} + +#endif diff --git a/vendor/lief/api/python/src/pyIterator.hpp b/vendor/lief/api/python/src/pyIterator.hpp new file mode 100644 index 0000000..629be25 --- /dev/null +++ b/vendor/lief/api/python/src/pyIterator.hpp @@ -0,0 +1,86 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_ITERATORS_H +#define PY_LIEF_ITERATORS_H + +#include "nanobind/nanobind.h" +#include "nanobind/make_iterator.h" + +#include + +namespace nb = nanobind; + +namespace LIEF::py { + +template +void init_ref_iterator(nanobind::handle& m, const char* it_name) { + using ElementTy = typename T::value_type; + + static nb::ft_mutex mu; + nb::ft_lock_guard lock(mu); + + if (auto type = nb::type(); type.is_valid()) { + m.attr(it_name) = type; + return; + } + + nb::class_(m, it_name) + .def_prop_ro_static("__doc__", + [] (const nb::object&) -> std::string { + using namespace std::literals; + if (auto type = nb::type(); type.is_valid()) { + nb::str name = nb::type_name(type); + return "Iterator over :class:`"s + name.c_str() + "`"; + } + return ""; + }) + + .def("__getitem__", + [] (T& v, Py_ssize_t i) -> typename T::reference { + const size_t size = v.size(); + if (i < 0) { + i += static_cast(size); + } + if (i < 0 || static_cast(i) >= size) { + throw nb::index_error(); + } + return v[i]; + }, + nb::rv_policy::reference_internal) + + .def("__len__", + [] (T& v) { + return v.size(); + }) + + .def("__iter__", + [] (const T& v) { + return v; + }, nb::rv_policy::reference_internal) + + .def("__next__", + [] (T& v) -> typename T::reference { + if (v == std::end(v)) { + throw nb::stop_iteration(); + } + auto& value = *v; + ++v; + return value; + }, nb::rv_policy::reference_internal); +} +} + +#endif diff --git a/vendor/lief/api/python/src/pyLIEF.cpp b/vendor/lief/api/python/src/pyLIEF.cpp new file mode 100644 index 0000000..f5ad800 --- /dev/null +++ b/vendor/lief/api/python/src/pyLIEF.cpp @@ -0,0 +1,448 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyLIEF.hpp" +#include "pyErr.hpp" +#include +#include "spdlog/sinks/python_sink.h" + +#include +#include +#include +#include +#include "nanobind/extra/stl/pathlike.h" + +#include "LIEF/utils.hpp" +#include "LIEF/hash.hpp" +#include "LIEF/Object.hpp" +#include "LIEF/range.hpp" +#include "LIEF/debug_loc.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/logging.hpp" +#include "LIEF/version.h" +#include "LIEF/json.hpp" + +#include "platforms/pyPlatform.hpp" + +#include "Abstract/init.hpp" +#include "DWARF/init.hpp" +#include "PDB/init.hpp" +#include "ObjC/init.hpp" +#include "DyldSharedCache/init.hpp" +#include "asm/init.hpp" +#include "BinaryStream/init.hpp" +#include "runtime/init.hpp" + +#include "pyWriteStream.hpp" + +#if defined(LIEF_ELF_SUPPORT) + #include "ELF/init.hpp" +#endif + +#if defined(LIEF_PE_SUPPORT) + #include "PE/init.hpp" +#endif + +#if defined(LIEF_MACHO_SUPPORT) + #include "MachO/init.hpp" +#endif + +#if defined(LIEF_OAT_SUPPORT) + #include "OAT/init.hpp" +#endif + +#if defined(LIEF_DEX_SUPPORT) + #include "DEX/init.hpp" +#endif + +#if defined(LIEF_VDEX_SUPPORT) + #include "VDEX/init.hpp" +#endif + +#if defined(LIEF_ART_SUPPORT) + #include "ART/init.hpp" +#endif + +#if defined(LIEF_COFF_SUPPORT) + #include "COFF/init.hpp" +#endif + + +// NOLINTNEXTLINE +nb::module_* lief_mod = nullptr; + +namespace LIEF { +class DeclOpt; +} + +namespace LIEF::py { + +void init_extension(nb::module_& m) { + m.attr("__extended__") = false; +} + +void init_object(nb::module_& m) { + nb::class_(m, "Object") + .def("__hash__", [] (const Object& self) { + return hash(self); + }) + .def("__eq__", + [] (const Object& lhs, const Object& rhs) { + return hash(lhs) == hash(rhs); + }); +} + +void init_python_sink() { + spdlog::details::registry::instance().drop("LIEF"); + LIEF::logging::set_logger(spdlog::stderr_python_mt("LIEF")); +} + +template +void log_impl(nb::args args) { + std::string msg; + for (size_t i = 0; i < args.size(); ++i) { + nb::handle arg = args[i]; + if (i > 0) { + msg.push_back(' '); + } + if (nb::isinstance(arg)) { + msg.append(nb::cast(arg)); + } else { + msg.append(nb::cast(arg.attr("__str__")())); + } + } + LIEF::logging::log(lvl, msg); +} + +void init_logger(nb::module_& m) { + nb::module_ logging = m.def_submodule("logging"); + + #define PY_ENUM(x) LIEF::logging::to_string(x), x + nb::enum_(logging, "Level") + .value(PY_ENUM(logging::Level::Off)) + .value(PY_ENUM(logging::Level::Trace)) + .value(PY_ENUM(logging::Level::Debug)) + .value(PY_ENUM(logging::Level::Critical)) + .value(PY_ENUM(logging::Level::Err)) + .value(PY_ENUM(logging::Level::Warn)) + .value(PY_ENUM(logging::Level::Info)); + #undef PY_ENUM + + nb::class_(logging, "Scoped") + .def("__enter__", [] (logging::Scoped& self) { + return &self; + }, nb::rv_policy::reference) + + .def("__exit__", [] (logging::Scoped& self, const nb::args& /*args*/) { + self.reset(); + }); + + logging.def("disable", nb::overload_cast<>(&logging::disable), + "Disable the logger globally"_doc); + + logging.def("enable", nb::overload_cast<>(&logging::enable), + "Enable the logger globally"_doc); + + logging.def("set_level", nb::overload_cast(&logging::set_level), + "Change logging level", "level"_a); + + logging.def("level_scope", + [] (logging::Level lvl) { + return std::make_unique(lvl); + }, + "level"_a, nb::rv_policy::take_ownership, + nb::sig("def level_scope(level: Level) -> Scoped") + ); + + logging.def("level_scope", + [] (const std::string& name, logging::Level lvl) { + return std::make_unique(lvl, name); + }, "name"_a, "lvl"_a, nb::rv_policy::take_ownership, + nb::sig("def level_scope(name: str, lvl: Level) -> Scoped") + ); + + logging.def("get_level", nb::overload_cast<>(&logging::get_level), + "Get current logging level"); + + logging.def("set_path", [] (nb::PathLike path) { logging::set_path(path); }, + "Change the logger as a file-base logging and set its path"_doc, + "path"_a); + + logging.def("log", + static_cast(&logging::log), + "Log a message with the LIEF's logger"_doc, + "level"_a, "msg"_a); + + logging.def("debug", &log_impl, + "Log a :attr:`~.Level.Debug` message"_doc, "msg"_a); + + logging.def("info", &log_impl, + "Log an :attr:`~.Level.Info` message"_doc, "args"_a); + + logging.def("warn", &log_impl, + "Log a :attr:`~.Level.Warn` message"_doc, "msg"_a); + + logging.def("err", &log_impl, + "Log an :attr:`~.Level.Err` message"_doc, "msg"_a); + + logging.def("critical", &log_impl, + "Log an :attr:`~.Level.Critical` message"_doc, "msg"_a); + + logging.def("enable_debug", nb::overload_cast<>(&logging::enable_debug), + "Enable :attr:`~.Level.Debug` log level"_doc); + + logging.def("reset", [] { + logging::reset(); + init_python_sink(); + }); +} + +void init_hash(nb::module_& m) { + m.def("hash", nb::overload_cast(&hash)); + m.def("hash", nb::overload_cast&>(&hash)); + m.def("hash", + [] (nb::bytes bytes) { + const auto* begin = reinterpret_cast(bytes.c_str()); + const auto* end = begin + bytes.size(); + return LIEF::hash(std::vector(begin, end)); + }); + + m.def("hash", + [] (const std::string& bytes) { + const std::vector data = {std::begin(bytes), std::end(bytes)}; + return hash(data); + }); +} + + +void init_json(nb::module_& m) { + m.def("to_json", &LIEF::to_json); +} + +void init_range(nb::module_& m) { + nb::class_(m, "range_t") + .def_rw("low", &LIEF::range_t::low) + .def_rw("high", &LIEF::range_t::high) + .def_prop_ro("size", &LIEF::range_t::size) + .def("__repr__", + [] (const LIEF::range_t& R) { + return fmt::format("", R.low, R.high); + } + ) + + LIEF_DEFAULT_STR(LIEF::range_t); + ; +} + +void init_debug_location(nb::module_& m) { + nb::class_(m, "debug_location_t") + .def_rw("line", &LIEF::debug_location_t::line) + .def_rw("file", &LIEF::debug_location_t::file) + .def("__repr__", + [] (const LIEF::debug_location_t& loc) { + return fmt::format("", loc.file, loc.line); + } + ) + ; +} + + +void init(nb::module_& m) { + lief_mod = &m; + m.attr("__version__") = nb::str(LIEF_VERSION); + m.attr("__tag__") = nb::str(LIEF_TAG); + m.attr("__commit__") = nb::str(LIEF_COMMIT); + m.attr("__is_tagged__") = bool(LIEF_TAGGED); + m.doc() = "LIEF Python API"; + +// This attribute reflects whether LIEF was compiled with free-threading support +#if defined (NB_FREE_THREADED) + m.attr("__free_threaded__") = true; +#else + m.attr("__free_threaded__") = false; +#endif + + nb::class_(m, "lief_version_t") + .def_rw("major", &LIEF::lief_version_t::major) + .def_rw("minor", &LIEF::lief_version_t::minor) + .def_rw("patch", &LIEF::lief_version_t::patch) + .def_rw("id", &LIEF::lief_version_t::id) + .def("__repr__", + [] (const LIEF::lief_version_t& version) { + return fmt::format("", version.to_string()); + } + ) + .def("__str__", + [] (const LIEF::lief_version_t& version) { + return version.to_string(); + } + ) + ; + + + m.def("disable_leak_warning", [] { + nb::set_leak_warnings(false); + }, R"doc( + Disable nanobind warnings about leaked objects. + For instance: + + .. code-block:: text + + nanobind: leaked 45 instances! + nanobind: leaked 25 types! + - leaked type "lief._lief.FORMATS" + - ... skipped remainder + nanobind: leaked 201 functions! + - leaked function "" + - leaked function "export_symbol" + - ... skipped remainder + nanobind: this is likely caused by a reference counting issue in the binding code. + )doc"_doc); + + m.def("demangle", + [] (const std::string& mangled) { + return LIEF::py::value_or_none(&LIEF::demangle, mangled); + }, + R"doc( + Demangle the given input. + + .. warning:: + + This function only works with the extended version of LIEF + )doc"_doc, + "mangled"_a + ); + + m.def("dump", [] (nb::extra::memoryview view, const std::string& title, + const std::string& prefix, size_t limit) + { + return LIEF::dump(view.data(), view.size(), title, prefix, limit); + }, "buffer"_a, "title"_a = "", "prefix"_a = "", "limit"_a = 0, + R"doc( + Hexdump the provided buffer: + + .. code-block:: text + + +---------------------------------------------------------------------+ + | 88 56 05 00 00 00 00 00 00 00 00 00 22 58 05 00 | .V.........."X.. | + | 10 71 02 00 78 55 05 00 00 00 00 00 00 00 00 00 | .q..xU.......... | + | 68 5c 05 00 00 70 02 00 00 00 00 00 00 00 00 00 | h\...p.......... | + | 00 00 00 00 00 00 00 00 00 00 00 00 | ............ | + +---------------------------------------------------------------------+ + )doc"_doc + ); + + m.def("dump", [] (const nb::bytes& bytes, const std::string& title, + const std::string& prefix, size_t limit) + { + return LIEF::dump(reinterpret_cast(bytes.data()), bytes.size(), title, prefix, limit); + }, "buffer"_a, "title"_a = "", "prefix"_a = "", "limit"_a = 0, + R"doc( + Hexdump the provided buffer: + + .. code-block:: text + + +---------------------------------------------------------------------+ + | 88 56 05 00 00 00 00 00 00 00 00 00 22 58 05 00 | .V.........."X.. | + | 10 71 02 00 78 55 05 00 00 00 00 00 00 00 00 00 | .q..xU.......... | + | 68 5c 05 00 00 70 02 00 00 00 00 00 00 00 00 00 | h\...p.......... | + | 00 00 00 00 00 00 00 00 00 00 00 00 | ............ | + +---------------------------------------------------------------------+ + )doc"_doc + ); + + m.def("extended_version_info", &LIEF::extended_version_info, + "Details about the extended version"_doc); + + m.def("extended_version", &LIEF::extended_version, + "Return the extended version"_doc); + + m.def("to_int", [] (const void* ptr) { + return reinterpret_cast(ptr); + }, "ptr"_a, "Convert an opaque pointer into an address (int)"_doc); + + m.def("to_ptr", [] (uintptr_t ptr) { + return reinterpret_cast(ptr); + }, "ptr"_a, "Convert an integer into an opaque pointer (``void*``)"_doc); + + LIEF::py::init_extension(m); + + LIEF::py::init_python_sink(); + + LIEF::py::init_range(m); + LIEF::py::init_debug_location(m); + LIEF::py::init_platforms(m); + LIEF::py::init_object(m); + LIEF::py::init_errors(m); + LIEF::py::init_logger(m); + LIEF::py::init_hash(m); + LIEF::py::init_json(m); + + LIEF::py::init_binarystream(m); + LIEF::py::init_writerstream(m); + + LIEF::assembly::py::init(m); + + LIEF::py::init_abstract(m); + + LIEF::py::create(m); + + LIEF::dwarf::py::init(m); + LIEF::pdb::py::init(m); + LIEF::objc::py::init(m); + LIEF::dsc::py::init(m); + + LIEF::runtime::py::init(m); + +#if defined(LIEF_ELF_SUPPORT) + LIEF::ELF::py::init(m); +#endif + +#if defined(LIEF_PE_SUPPORT) + LIEF::PE::py::init(m); +#endif + +#if defined(LIEF_MACHO_SUPPORT) + LIEF::MachO::py::init(m); +#endif + +#if defined(LIEF_OAT_SUPPORT) + LIEF::OAT::py::init(m); +#endif + +#if defined(LIEF_DEX_SUPPORT) + LIEF::DEX::py::init(m); +#endif + +#if defined(LIEF_VDEX_SUPPORT) + LIEF::VDEX::py::init(m); +#endif + +#if defined(LIEF_ART_SUPPORT) + LIEF::ART::py::init(m); +#endif + +#if defined(LIEF_COFF_SUPPORT) + LIEF::COFF::py::init(m); +#endif + +} + +} + +NB_MODULE(_lief, m) { + LIEF::py::init(m); +} diff --git a/vendor/lief/api/python/src/pyLIEF.hpp b/vendor/lief/api/python/src/pyLIEF.hpp new file mode 100644 index 0000000..c07f7e2 --- /dev/null +++ b/vendor/lief/api/python/src/pyLIEF.hpp @@ -0,0 +1,65 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_H +#define PY_LIEF_H + +#include + +#define RST_CLASS_REF(X) ":class:`~"#X"`" +#define RST_CLASS_REF_FULL(X) ":class:`"#X"`" + +#define RST_ATTR_REF(X) ":attr:`~"#X"`" +#define RST_ATTR_REF_FULL(X) ":attr:`"#X"`" + +#define RST_METH_REF(X) ":class:`~"#X"`" +#define RST_METH_REF_FULL(X) ":class:`"#X"`" + +#define LIEF_MOD_NAME "lief" + +#define LIEF_DEFAULT_STR(OBJ) \ + .def("__str__", \ + [] (const OBJ& O) { \ + std::ostringstream stream; \ + stream << O; \ + return stream.str(); \ + }) + +#define LIEF_COPYABLE(OBJ) \ + .def("copy", [] (OBJ& self) { return OBJ(self); }, \ + "Duplicate the current instance of this object"_doc, \ + nb::rv_policy::move) + +#define LIEF_CLONABLE(OBJ) \ + .def("copy", [] (OBJ& self) {return self.clone(); }, \ + "Duplicate the current instance of this object"_doc, \ + nb::rv_policy::take_ownership) + +constexpr const char* operator ""_doc(const char* value, size_t) { + return value; +} + +namespace nb = nanobind; + +extern nb::module_* lief_mod; + +using namespace nb::literals; + +namespace LIEF::py { +template +void create(nb::module_&); +} + +#endif diff --git a/vendor/lief/api/python/src/pyOwningIterator.hpp b/vendor/lief/api/python/src/pyOwningIterator.hpp new file mode 100644 index 0000000..7c8de8a --- /dev/null +++ b/vendor/lief/api/python/src/pyOwningIterator.hpp @@ -0,0 +1,183 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_OWNING_ITERATOR_H +#define PY_LIEF_OWNING_ITERATOR_H + +#include +#include +#include + +#include "LIEF/iterators.hpp" + +namespace LIEF::py { + +template +class OwningIterator { + public: + using underlying_type = + typename std::iterator_traits::value_type; + + using iterator_category = std::input_iterator_tag; + using value_type = std::unique_ptr; + using difference_type = std::ptrdiff_t; + using pointer = void; + using reference = std::unique_ptr; + + OwningIterator() = default; + explicit OwningIterator(It it) : + it_(std::move(it)) {} + + OwningIterator& operator=(const OwningIterator&) = default; + OwningIterator(const OwningIterator&) = default; + + OwningIterator& operator=(OwningIterator&&) noexcept = default; + OwningIterator(OwningIterator&&) noexcept = default; + + ~OwningIterator() = default; + + std::unique_ptr operator*() { + return it_.yield(); + } + + OwningIterator& operator++() { + ++it_; + return *this; + } + + OwningIterator operator++(int) { + OwningIterator tmp = *this; + ++(*this); + return tmp; + } + + friend bool operator==(const OwningIterator& lhs, const OwningIterator& rhs) { + return lhs.it_ == rhs.it_; + } + + friend bool operator!=(const OwningIterator& lhs, const OwningIterator& rhs) { + return !(lhs == rhs); + } + + private: + It it_; +}; + +template +iterator_range> + owning_range(const iterator_range& range) { + return { + OwningIterator(std::move(range.begin())), + OwningIterator(std::move(range.end())) + }; +} + +template +class OwningRandomAccessIterator { + public: + using underlying_type = + typename std::iterator_traits::value_type; + + using iterator_category = std::random_access_iterator_tag; + using value_type = std::unique_ptr; + using difference_type = std::ptrdiff_t; + using pointer = void; + using reference = std::unique_ptr; + + OwningRandomAccessIterator() = default; + explicit OwningRandomAccessIterator(It it) : + it_(std::move(it)) {} + + std::unique_ptr operator*() const { + It scratch = it_; + return scratch.yield(); + } + + OwningRandomAccessIterator& operator++() { + ++it_; + return *this; + } + + OwningRandomAccessIterator operator++(int) { + OwningRandomAccessIterator tmp = *this; + ++(*this); + return tmp; + } + + OwningRandomAccessIterator& operator--() { + --it_; + return *this; + } + + OwningRandomAccessIterator operator--(int) { + OwningRandomAccessIterator tmp = *this; + --(*this); + return tmp; + } + + OwningRandomAccessIterator& operator+=(difference_type n) { + it_ += n; + return *this; + } + + OwningRandomAccessIterator& operator-=(difference_type n) { + it_ -= n; + return *this; + } + + OwningRandomAccessIterator operator+(difference_type n) const { + OwningRandomAccessIterator tmp = *this; + tmp += n; + return tmp; + } + + OwningRandomAccessIterator operator-(difference_type n) const { + OwningRandomAccessIterator tmp = *this; + tmp -= n; + return tmp; + } + + difference_type operator-(const OwningRandomAccessIterator& other) const { + return it_ - other.it_; + } + + friend bool operator==(const OwningRandomAccessIterator& lhs, + const OwningRandomAccessIterator& rhs) { + return lhs.it_ == rhs.it_; + } + + friend bool operator!=(const OwningRandomAccessIterator& lhs, + const OwningRandomAccessIterator& rhs) { + return !(lhs == rhs); + } + + friend bool operator<(const OwningRandomAccessIterator& lhs, + const OwningRandomAccessIterator& rhs) { + return lhs.it_ < rhs.it_; + } + + private: + It it_; +}; + +template +iterator_range> + owning_random_access_range(const iterator_range& range) { + return {OwningRandomAccessIterator(range.begin()), + OwningRandomAccessIterator(range.end())}; +} +} + +#endif diff --git a/vendor/lief/api/python/src/pyParser.cpp b/vendor/lief/api/python/src/pyParser.cpp new file mode 100644 index 0000000..7a25c36 --- /dev/null +++ b/vendor/lief/api/python/src/pyParser.cpp @@ -0,0 +1,163 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Abstract/init.hpp" +#include "pyLIEF.hpp" +#include "typing/InputParser.hpp" + +#include +#include + +#include "LIEF/Abstract/Parser.hpp" +#include "LIEF/BinaryStream/BinaryStream.hpp" + +#include "LIEF/config.h" + +#if LIEF_PE_SUPPORT +#include "LIEF/PE/utils.hpp" +#include "LIEF/PE/Parser.hpp" +#include "LIEF/PE/Binary.hpp" +#endif + +#if LIEF_ELF_SUPPORT +#include "LIEF/ELF/utils.hpp" +#include "LIEF/ELF/Parser.hpp" +#include "LIEF/ELF/Binary.hpp" +#endif + +#if LIEF_OAT_SUPPORT +#include "LIEF/OAT/utils.hpp" +#include "LIEF/OAT/Parser.hpp" +#include "LIEF/OAT/Binary.hpp" +#endif + +#if LIEF_MACHO_SUPPORT +#include "LIEF/MachO/utils.hpp" +#include "LIEF/MachO/Parser.hpp" +#include "LIEF/MachO/Binary.hpp" +#include "LIEF/MachO/FatBinary.hpp" +#endif + +#if LIEF_COFF_SUPPORT +#include "LIEF/COFF/utils.hpp" +#include "LIEF/COFF/Parser.hpp" +#include "LIEF/COFF/Binary.hpp" +#endif + +namespace LIEF::py { + +typing::OutputParser from_stream(std::unique_ptr stream) { + if (stream == nullptr) { + return nb::none(); + } + + #if LIEF_PE_SUPPORT + if (LIEF::PE::is_pe(*stream)) { + return nb::cast(LIEF::PE::Parser::parse(std::move(stream))); + } + #endif + + #if LIEF_ELF_SUPPORT + if (LIEF::ELF::is_elf(*stream)) { + return nb::cast(LIEF::ELF::Parser::parse(std::move(stream))); + } + #endif + + #if LIEF_MACHO_SUPPORT + if (LIEF::MachO::is_macho(*stream)) { + std::unique_ptr fat = + LIEF::MachO::Parser::parse(std::move(stream)); + + // NOTE(romain): We could nb::cast the fat binary object but + // to avoid a breaking change in the logic of parse() we return a + // `LIEF::MachO::Binary` as we did since the beginning. + // + // We could introduce this breaking change later though. + if (fat == nullptr || fat->empty()) { + return nb::none(); + } + return nb::cast(fat->take(0)); + } + #endif + + #if LIEF_COFF_SUPPORT + if (LIEF::COFF::is_coff(*stream)) { + return nb::cast(LIEF::COFF::Parser::parse(std::move(stream))); + } + #endif + + return nb::none(); +} + +typing::OutputParser parse_dump_from_stream(std::unique_ptr stream, + uint64_t addr) { + if (stream == nullptr) { + return nb::none(); + } + + #if LIEF_PE_SUPPORT + if (LIEF::PE::is_pe(*stream)) { + return nb::cast(LIEF::PE::Parser::parse_from_dump(std::move(stream), addr)); + } + #endif + + #if LIEF_ELF_SUPPORT + if (LIEF::ELF::is_elf(*stream)) { + return nb::cast(LIEF::ELF::Parser::parse_from_dump(std::move(stream), addr)); + } + #endif + + #if LIEF_MACHO_SUPPORT + if (LIEF::MachO::is_macho(*stream)) { + std::unique_ptr fat = + LIEF::MachO::Parser::parse_from_dump(std::move(stream), addr); + + if (fat == nullptr || fat->empty()) { + return nb::none(); + } + return nb::cast(fat->take(0)); + } + #endif + + return nb::none(); +} + +template<> +void create(nb::module_& m) { + m.def("parse", + [] (typing::InputParser generic) -> typing::OutputParser { + return from_stream(generic.into_stream()); + }, + R"delim( + Parse a binary supported by LIEF (ELF, PE, Mach-O, ...) from the given + Python object and return the corresponding :class:`~lief.Binary` object. + )delim"_doc, + "obj"_a, nb::rv_policy::take_ownership); + + m.def("parse_from_dump", + [] (typing::InputParser generic, uint64_t addr) -> typing::OutputParser { + return parse_dump_from_stream(generic.into_stream(), addr); + }, + R"delim( + Parse a binary (ELF, PE, Mach-O, ...) from a memory dump. + + A dump is a raw capture of the process' memory that was mapped starting at + the virtual address ``addr`` (given as the second parameter). The format is + auto-detected from the content of the dump. + )delim"_doc, + "obj"_a, "addr"_a, nb::rv_policy::take_ownership); + +} +} diff --git a/vendor/lief/api/python/src/pySafeString.cpp b/vendor/lief/api/python/src/pySafeString.cpp new file mode 100644 index 0000000..cfdcbce --- /dev/null +++ b/vendor/lief/api/python/src/pySafeString.cpp @@ -0,0 +1,28 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pySafeString.hpp" +#include "pyLIEF.hpp" + +namespace LIEF::py { +safe_string_t safe_string(std::string_view str) { + nb::bytes str_bytes(str.data(), str.size()); + try { + return nb::str(str_bytes.attr("decode")("utf8")); + } catch (const std::exception& e) { + return str_bytes; + } +} +} diff --git a/vendor/lief/api/python/src/pySafeString.hpp b/vendor/lief/api/python/src/pySafeString.hpp new file mode 100644 index 0000000..37f09d7 --- /dev/null +++ b/vendor/lief/api/python/src/pySafeString.hpp @@ -0,0 +1,35 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_SAFE_STRING_H +#define PY_LIEF_SAFE_STRING_H +#include +#include "typing.hpp" + +struct safe_string_t : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(safe_string_t, nanobind::str); + LIEF_PY_DEFAULT_CTOR(safe_string_t, nanobind::bytes); + + NB_OBJECT_DEFAULT(safe_string_t, object, "Union[str, bytes]", check) + + static bool check(handle /*h*/) { + return true; + } +}; + +namespace LIEF::py { +safe_string_t safe_string(std::string_view str); +} +#endif diff --git a/vendor/lief/api/python/src/pyWriteStream.cpp b/vendor/lief/api/python/src/pyWriteStream.cpp new file mode 100644 index 0000000..0b5d390 --- /dev/null +++ b/vendor/lief/api/python/src/pyWriteStream.cpp @@ -0,0 +1,119 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "pyWriteStream.hpp" + +#include +#include + +#include "nanobind/utils.hpp" + +#include "LIEF/iostream.hpp" + +namespace LIEF::py { + +void init_writerstream(nb::module_& m) { + nb::class_(m, "WriteStream") + .def(nb::init<>()) + .def(nb::init(), "endian_swap"_a) + + .def("reserve", &vector_iostream::reserve, "size"_a, + nb::rv_policy::reference_internal) + + .def("increase_capacity", &vector_iostream::increase_capacity, "size"_a, + nb::rv_policy::reference_internal) + + .def("align", &vector_iostream::align, "alignment"_a, "fill"_a = 0, + nb::rv_policy::reference_internal) + + .def_prop_ro("size", &vector_iostream::size) + .def("__len__", &vector_iostream::size) + + .def_prop_ro("tellp", [] (vector_iostream& self) { + return (uint64_t)self.tellp(); + }) + + .def("seekp", [] (vector_iostream& self, uint64_t pos) { + using off_type = vector_iostream::off_type; + using pos_type = vector_iostream::pos_type; + if (pos > (uint64_t)std::numeric_limits::max()) { + throw std::overflow_error("WriteStream position is out of range"); + } + return self.seekp((pos_type)pos); + }, "pos"_a, nb::rv_policy::reference_internal) + + .def("seek_end", &vector_iostream::seek_end, + nb::rv_policy::reference_internal) + + .def("pad", &vector_iostream::pad, "size"_a, "value"_a = 0, + nb::rv_policy::reference_internal) + + .def("set_endian_swap", &vector_iostream::set_endian_swap, "swap"_a) + .def_prop_ro("endian_swap", &vector_iostream::endian_swap) + + .def_prop_ro("raw", [] (const vector_iostream& self) { + return nb::to_memoryview(self.raw()); + }, nb::keep_alive<0, 1>()) + + .def("__bytes__", [] (const vector_iostream& self) { + return nb::to_bytes(self.raw()); + }) + + .def("write_u8", [] (vector_iostream& self, uint8_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + .def("write_i8", [] (vector_iostream& self, int8_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + + .def("write_u16", [] (vector_iostream& self, uint16_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + .def("write_i16", [] (vector_iostream& self, int16_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + + .def("write_u32", [] (vector_iostream& self, uint32_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + .def("write_i32", [] (vector_iostream& self, int32_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + + .def("write_u64", [] (vector_iostream& self, uint64_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + .def("write_i64", [] (vector_iostream& self, int64_t c) { return self.write(c); }, nb::rv_policy::reference_internal) + + .def("write_uleb128", &vector_iostream::write_uleb128, "value"_a, + nb::rv_policy::reference_internal + ) + .def("write_sleb128", &vector_iostream::write_sleb128, "value"_a, + nb::rv_policy::reference_internal + ) + + .def("write", [] (vector_iostream& self, const std::string& str) { + return self.write(str); + }, "s"_a, nb::rv_policy::reference_internal + ) + + .def("write", [] (vector_iostream& self, nb::bytes& bytes) { + return self.write((const uint8_t*)bytes.data(), bytes.size()); + }, "buffer"_a, nb::rv_policy::reference_internal + ) + + .def("write", [] (vector_iostream& self, const std::vector& buffer) { + return self.write(buffer); + }, "buffer"_a, nb::rv_policy::reference_internal + ) + + .def("write", [] (vector_iostream& self, const vector_iostream& other) { + return self.write(other); + }, "other"_a, nb::rv_policy::reference_internal + ) + + .def("put", [] (vector_iostream& self, uint8_t c) { + return self.put(c); + }, "c"_a, nb::rv_policy::reference_internal + ) + ; +} +} diff --git a/vendor/lief/api/python/src/pyWriteStream.hpp b/vendor/lief/api/python/src/pyWriteStream.hpp new file mode 100644 index 0000000..1a2dd2f --- /dev/null +++ b/vendor/lief/api/python/src/pyWriteStream.hpp @@ -0,0 +1,22 @@ +/* Copyright 2017 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_WRITERSTREAM_INIT_H +#define PY_LIEF_WRITERSTREAM_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::py { +void init_writerstream(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/pylief-pch.hpp b/vendor/lief/api/python/src/pylief-pch.hpp new file mode 100644 index 0000000..5e27e42 --- /dev/null +++ b/vendor/lief/api/python/src/pylief-pch.hpp @@ -0,0 +1,17 @@ +#if defined __cplusplus + #include + #include + #include + #include + + #include + #include + #include + #include + #include + #include + #include +#else + #include + #include +#endif diff --git a/vendor/lief/api/python/src/pyutils.cpp b/vendor/lief/api/python/src/pyutils.cpp new file mode 100644 index 0000000..ac1f781 --- /dev/null +++ b/vendor/lief/api/python/src/pyutils.cpp @@ -0,0 +1,26 @@ +#include "pyutils.hpp" + +namespace LIEF::py { +result path_to_str(nb::object pathlike) { + PyObject* buf = PyOS_FSPath(pathlike.ptr()); + if (!buf) { + PyErr_Clear(); + return make_error_code(lief_errors::conversion_error); + } + + PyObject* native = nullptr; + std::string path_str; + if (PyUnicode_FSConverter(buf, &native) != 0) { + if (char* c_str = PyBytes_AsString(native)) { + path_str = c_str; + } + } + Py_XDECREF(native); + Py_DECREF(buf); + if (PyErr_Occurred()) { + PyErr_Clear(); + return make_error_code(lief_errors::conversion_error); + } + return path_str; +} +} diff --git a/vendor/lief/api/python/src/pyutils.hpp b/vendor/lief/api/python/src/pyutils.hpp new file mode 100644 index 0000000..ba04d80 --- /dev/null +++ b/vendor/lief/api/python/src/pyutils.hpp @@ -0,0 +1,28 @@ +#ifndef PY_LIEF_UTILS_H +#define PY_LIEF_UTILS_H +#include + +#include + +#include + +namespace nb = nanobind; + +namespace LIEF::py { + +inline std::string type2str(nb::object obj) { + auto pytype = nb::steal(nb::detail::nb_inst_name(obj.ptr())); + std::string type = pytype.c_str(); + size_t pos_1 = type.find('.'); + size_t pos_2 = type.find('.', pos_1 + 1); + if (pos_1 == std::string::npos || pos_2 == std::string::npos) { + return type; + } + return "lief." + type.substr(pos_2 + 1); +} + +result path_to_str(nb::object pathlike); + +} + +#endif diff --git a/vendor/lief/api/python/src/runtime/CMakeLists.txt b/vendor/lief/api/python/src/runtime/CMakeLists.txt new file mode 100644 index 0000000..b6bda75 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + init.cpp +) + +add_subdirectory(objects) diff --git a/vendor/lief/api/python/src/runtime/init.cpp b/vendor/lief/api/python/src/runtime/init.cpp new file mode 100644 index 0000000..4fe15d8 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/init.cpp @@ -0,0 +1,74 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "runtime/init.hpp" +#include "runtime/pyRuntime.hpp" +#include "runtime/objects/linux/init.hpp" +#include "runtime/objects/windows/init.hpp" +#include "runtime/objects/android/init.hpp" +#include "runtime/objects/osx/init.hpp" + +#include "LIEF/runtime/utils.hpp" +#include "LIEF/config.h" + +namespace LIEF::runtime { +class Process; +class Module; +class Memory; +class MemoryLayout; +class Host; +} + +namespace LIEF::runtime::py { +void init_disassembler(nb::module_& m); +void init_assembler(nb::module_& m); + +void init(nb::module_& m) { + nb::module_ runtime_mod = m.def_submodule("runtime"); + + nb::enum_(runtime_mod, "ARCH") + .value("NONE", ARCH::NONE) + .value("X86_64", ARCH::X86_64) + .value("ARM64", ARCH::ARM64) + .value("RISCV64", ARCH::RISCV64) + ; + + nb::enum_(runtime_mod, "PLATFORMS") + .value("NONE", PLATFORMS::NONE) + .value("LINUX", PLATFORMS::LINUX) + .value("WINDOWS", PLATFORMS::WINDOWS) + .value("ANDROID", PLATFORMS::ANDROID_) + .value("OSX", PLATFORMS::OSX) + .value("IOS", PLATFORMS::IOS) + ; + + runtime_mod.attr("enabled") = (bool)lief_runtime_support; + runtime_mod.attr("platform") = platform(); + runtime_mod.attr("arch") = arch(); + + create(runtime_mod); + create(runtime_mod); + create(runtime_mod); + create(runtime_mod); + create(runtime_mod); + init_disassembler(runtime_mod); + init_assembler(runtime_mod); + + Linux::py::init(runtime_mod); + android::py::init(runtime_mod); + windows::py::init(runtime_mod); + osx::py::init(runtime_mod); +} +} diff --git a/vendor/lief/api/python/src/runtime/init.hpp b/vendor/lief/api/python/src/runtime/init.hpp new file mode 100644 index 0000000..8c9a6f5 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_INIT_H +#define PY_LIEF_RUNTIME_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/CMakeLists.txt b/vendor/lief/api/python/src/runtime/objects/CMakeLists.txt new file mode 100644 index 0000000..9c74af5 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/CMakeLists.txt @@ -0,0 +1,14 @@ +target_sources(pyLIEF PRIVATE + pyProcess.cpp + pyModule.cpp + pyHost.cpp + pyMemory.cpp + pyMemoryLayout.cpp + pyDisassembler.cpp + pyAssembler.cpp +) + +add_subdirectory(linux) +add_subdirectory(windows) +add_subdirectory(android) +add_subdirectory(osx) diff --git a/vendor/lief/api/python/src/runtime/objects/android/CMakeLists.txt b/vendor/lief/api/python/src/runtime/objects/android/CMakeLists.txt new file mode 100644 index 0000000..a58b400 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/CMakeLists.txt @@ -0,0 +1,7 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyModule.cpp + pyHost.cpp + pyProcess.cpp + pyProperty.cpp +) diff --git a/vendor/lief/api/python/src/runtime/objects/android/init.cpp b/vendor/lief/api/python/src/runtime/objects/android/init.cpp new file mode 100644 index 0000000..eac2588 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/init.cpp @@ -0,0 +1,37 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "runtime/objects/android/init.hpp" +#include "runtime/pyRuntime.hpp" + +#include "LIEF/config.h" + +namespace LIEF::runtime::android { +class Module; +class Host; +class Process; +class Property; +} + +namespace LIEF::runtime::android::py { +void init(nb::module_& m) { + nb::module_ android_mod = m.def_submodule("android"); + + create(android_mod); + create(android_mod); + create(android_mod); + create(android_mod); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/android/init.hpp b/vendor/lief/api/python/src/runtime/objects/android/init.hpp new file mode 100644 index 0000000..eb00e07 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_ANDROID_INIT_H +#define PY_LIEF_RUNTIME_ANDROID_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::android::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/android/pyHost.cpp b/vendor/lief/api/python/src/runtime/objects/android/pyHost.cpp new file mode 100644 index 0000000..4895d67 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/pyHost.cpp @@ -0,0 +1,24 @@ +#include "LIEF/runtime/android/Host.hpp" +#include "runtime/pyRuntime.hpp" + +#include + +namespace LIEF::runtime::android::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Host", + R"doc( + This class exposes Android-specific host information. + )doc"_doc + ) + .def_prop_ro_static("sdk_version", [] (nb::handle) { + return Host::sdk_version(); + }, + R"doc( + Return the Android SDK/API level of the device (e.g. ``34`` for Android 14). + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/android/pyModule.cpp b/vendor/lief/api/python/src/runtime/objects/android/pyModule.cpp new file mode 100644 index 0000000..7b55177 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/pyModule.cpp @@ -0,0 +1,61 @@ +#include "LIEF/ELF/ParserConfig.hpp" +#include "LIEF/ELF/Binary.hpp" +#include "LIEF/runtime/android/Module.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include "typing/StrOrPath.hpp" + +namespace LIEF::runtime::android::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Module", + R"doc( + This class exposes an Android-specific API for a module + )doc"_doc + ); + + obj + .def_prop_ro("handle", &Module::handle, + R"doc( + Return the dlopen handle for this library. + + Return a nullptr if the function fails or if the handler can't be found + )doc"_doc + ) + .def("dlsym", &Module::dlsym, "name"_a, + "Resolve the symbol with the given name for the current module"_doc + ) + .def_static("from_handle", &Module::from_handle, + R"doc( + Create a :class:`~lief.runtime.android.Module` from the given ``dlopen`` + handle (passed as an opaque pointer). + )doc"_doc, + "handle"_a) + + .def("parse_from_path", nb::overload_cast<>(&Module::parse_from_path, nb::const_), + "Parse the ELF module from its path on the filesystem"_doc) + + .def("parse_from_path", nb::overload_cast(&Module::parse_from_path, nb::const_), + "Parse the ELF module from its path on the filesystem and given the parser configuration"_doc, + "config"_a) + + .def("parse_from_memory", nb::overload_cast<>(&Module::parse_from_memory, nb::const_), + "Parse the ELF module from memory"_doc) + + .def("parse_from_memory", nb::overload_cast(&Module::parse_from_memory, nb::const_), + "Parse the ELF module from memory with the given configuration"_doc, + "config"_a) + ; + + m.def("dlopen", [] (LIEF::py::typing::StrOrPath name) { + return dlopen(*name.to_string()); + }, "name"_a, + "Load the library with the given path/name"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/android/pyProcess.cpp b/vendor/lief/api/python/src/runtime/objects/android/pyProcess.cpp new file mode 100644 index 0000000..5a7e239 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/pyProcess.cpp @@ -0,0 +1,42 @@ +#include "LIEF/runtime/android/Process.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" +#include "nanobind/stl/vector.h" +#include + +namespace LIEF::runtime::android::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Process", + R"doc( + This class exposes Android-specific API for the current process. + )doc"_doc + ); + + obj + .def_prop_ro_static("cmdline", [] (nb::handle) { + return Process::cmdline(); + }, + R"doc( + Return the content of ``/proc/cmdline`` + )doc"_doc) + + .def_static("get_system_property", &Process::get_system_property, "name"_a, + R"doc( + Return the value of the Android system property with the given ``name`` + (e.g. ``ro.build.version.sdk``). + )doc"_doc) + + .def_prop_ro_static("properties", [] (nb::handle) { + return Process::properties(); + }, + R"doc( + Return all the Android system properties as a list of + :class:`~lief.runtime.android.Property`. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/android/pyProperty.cpp b/vendor/lief/api/python/src/runtime/objects/android/pyProperty.cpp new file mode 100644 index 0000000..617ff41 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/android/pyProperty.cpp @@ -0,0 +1,35 @@ +#include "LIEF/runtime/android/Property.hpp" +#include "runtime/pyRuntime.hpp" + +#include + +#include +#include + +namespace LIEF::runtime::android::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Property", + R"doc( + This class represents an Android system property such as ``ro.boot.hardware``. + )doc"_doc + ); + + obj + .def_prop_ro("name", &Property::name, + "Name of the property (e.g. ``ro.boot.hardware``)"_doc) + + .def_prop_ro("value", &Property::value, + "Value associated with the property"_doc) + + .def_prop_ro("serial", &Property::serial, + R"doc( + Serial number of the property. + )doc"_doc) + + LIEF_DEFAULT_STR(Property) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/linux/CMakeLists.txt b/vendor/lief/api/python/src/runtime/objects/linux/CMakeLists.txt new file mode 100644 index 0000000..ce8917c --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyModule.cpp + pyHost.cpp + pyProcess.cpp +) diff --git a/vendor/lief/api/python/src/runtime/objects/linux/init.cpp b/vendor/lief/api/python/src/runtime/objects/linux/init.cpp new file mode 100644 index 0000000..b747d00 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/init.cpp @@ -0,0 +1,35 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "runtime/objects/linux/init.hpp" +#include "runtime/pyRuntime.hpp" + +#include "LIEF/config.h" + +namespace LIEF::runtime::Linux { +class Module; +class Host; +class Process; +} + +namespace LIEF::runtime::Linux::py { +void init(nb::module_& m) { + nb::module_ linux_mod = m.def_submodule("linux"); + + create(linux_mod); + create(linux_mod); + create(linux_mod); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/linux/init.hpp b/vendor/lief/api/python/src/runtime/objects/linux/init.hpp new file mode 100644 index 0000000..fac0ee6 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_LINUX_INIT_H +#define PY_LIEF_RUNTIME_LINUX_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::Linux::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/linux/pyHost.cpp b/vendor/lief/api/python/src/runtime/objects/linux/pyHost.cpp new file mode 100644 index 0000000..8fdc415 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/pyHost.cpp @@ -0,0 +1,33 @@ +#include "LIEF/runtime/linux/Host.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +namespace LIEF::runtime::Linux::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "Host", + R"doc( + This class exposes Linux-specific host information. + )doc"_doc + ) + .def_prop_ro_static("sys_name", [] (nb::handle) { + return Host::sys_name(); + }, "Operating system name (e.g. ``Linux``)"_doc) + + .def_prop_ro_static("sys_release", [] (nb::handle) { + return Host::sys_release(); + }, "Operating system release (e.g. ``2.6.28``)"_doc) + + .def_prop_ro_static("sys_version", [] (nb::handle) { + return Host::sys_version(); + }, "Operating system version"_doc) + + .def_prop_ro_static("hardware", [] (nb::handle) { + return Host::hardware(); + }, "Hardware type identifier (e.g. ``x86_64``)"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/linux/pyModule.cpp b/vendor/lief/api/python/src/runtime/objects/linux/pyModule.cpp new file mode 100644 index 0000000..3c452b6 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/pyModule.cpp @@ -0,0 +1,65 @@ +#include "LIEF/ELF/ParserConfig.hpp" +#include "LIEF/ELF/Binary.hpp" +#include "LIEF/runtime/linux/Module.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include "typing/StrOrPath.hpp" + +namespace LIEF::runtime::Linux::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Module", + R"doc( + This class exposes a Linux-specific API for a module + )doc"_doc + ); + + obj + .def_prop_ro("handle", &Module::handle, + R"doc( + Return the ``dlopen`` handle for this library as an opaque pointer. + + Return ``None`` if the function fails or if the handler can't be found + )doc"_doc + ) + .def("dlsym", &Module::dlsym, + "Resolve the symbol with the given name for the current module"_doc, + "name"_a) + + .def_static("from_handle", &Module::from_handle, + R"doc( + Create a :class:`~lief.runtime.linux.Module` from the given ``dlopen`` handle. + + The handle is expected to be an opaque pointer as returned by + :attr:`handle` or :func:`dlopen`. + )doc"_doc, + "handle"_a) + + .def("parse_from_path", nb::overload_cast<>(&Module::parse_from_path, nb::const_), + "Parse the ELF module from its path on the filesystem"_doc) + + .def("parse_from_path", nb::overload_cast(&Module::parse_from_path, nb::const_), + "Parse the ELF module from its path on the filesystem and given the parser configuration"_doc, + "config"_a) + + .def("parse_from_memory", nb::overload_cast<>(&Module::parse_from_memory, nb::const_), + "Parse the ELF module from memory"_doc) + + .def("parse_from_memory", nb::overload_cast(&Module::parse_from_memory, nb::const_), + "Parse the ELF module from memory with the given configuration"_doc, + "config"_a) + ; + + m.def("dlopen", [] (LIEF::py::typing::StrOrPath name) { + return Linux::dlopen(*name.to_string()); + }, + "Load the library with the given path or name."_doc, + "name"_a + ); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/linux/pyProcess.cpp b/vendor/lief/api/python/src/runtime/objects/linux/pyProcess.cpp new file mode 100644 index 0000000..a336584 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/linux/pyProcess.cpp @@ -0,0 +1,36 @@ +#include "LIEF/runtime/linux/Process.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +namespace LIEF::runtime::Linux::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Process", + R"doc( + This class exposes Linux-specific API for the current process. + )doc"_doc + ); + + obj + .def_prop_ro_static("cmdline", [] (nb::handle) { + return Process::cmdline(); + }, + R"doc( + Return the content of ``/proc/cmdline`` + )doc"_doc) + + .def_prop_ro_static("glibc_version", [] (nb::handle) { + return Process::glibc_version(); + }, + R"doc( + Return the version of the GNU C Library (glibc) loaded in the current + process (e.g. ``2.39``). + + Return an empty string if the version cannot be determined. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/osx/CMakeLists.txt b/vendor/lief/api/python/src/runtime/objects/osx/CMakeLists.txt new file mode 100644 index 0000000..ce8917c --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyModule.cpp + pyHost.cpp + pyProcess.cpp +) diff --git a/vendor/lief/api/python/src/runtime/objects/osx/init.cpp b/vendor/lief/api/python/src/runtime/objects/osx/init.cpp new file mode 100644 index 0000000..9fddd36 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/init.cpp @@ -0,0 +1,35 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "runtime/objects/osx/init.hpp" +#include "runtime/pyRuntime.hpp" + +#include "LIEF/config.h" + +namespace LIEF::runtime::osx { +class Module; +class Host; +class Process; +} + +namespace LIEF::runtime::osx::py { +void init(nb::module_& m) { + nb::module_ osx_mod = m.def_submodule("osx"); + + create(osx_mod); + create(osx_mod); + create(osx_mod); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/osx/init.hpp b/vendor/lief/api/python/src/runtime/objects/osx/init.hpp new file mode 100644 index 0000000..47d38dc --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_OSX_INIT_H +#define PY_LIEF_RUNTIME_OSX_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::osx::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/osx/pyHost.cpp b/vendor/lief/api/python/src/runtime/objects/osx/pyHost.cpp new file mode 100644 index 0000000..411efbb --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/pyHost.cpp @@ -0,0 +1,74 @@ +#include "LIEF/runtime/osx/Host.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +#include + +namespace LIEF::runtime::osx::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Host", + R"doc( + This class exposes OSX-specific host information. + )doc"_doc + ); + + using version_t = Host::version_t; + nb::class_(obj, "version_t", + R"doc( + This class represents a macOS version number (major.minor.patch). + )doc"_doc + ) + .def(nb::init(), + "major"_a, "minor"_a, "patch"_a) + .def_rw("major", &version_t::major, "Major version number"_doc) + .def_rw("minor", &version_t::minor, "Minor version number"_doc) + .def_rw("patch", &version_t::patch, "Patch version number"_doc) + + .def("__eq__", &version_t::operator==) + .def("__ne__", &version_t::operator!=) + .def("__le__", &version_t::operator<=) + .def("__gt__", &version_t::operator>) + .def("__ge__", &version_t::operator>=) + .def("__lt__", [] (version_t& self, const version_t& rhs) { + return self < rhs; + }) + + .def_static("big_sur", &version_t::BigSur, + nb::rv_policy::reference, "macOS Big Sur (11.0)"_doc) + .def_static("monterey", &version_t::Monterey, + nb::rv_policy::reference, "macOS Monterey (12.0)"_doc) + .def_static("ventura", &version_t::Ventura, + nb::rv_policy::reference, "macOS Ventura (13.0)"_doc) + .def_static("sonoma", &version_t::Sonoma, + nb::rv_policy::reference, "macOS Sonoma (14.0)"_doc) + .def_static("sequoia", &version_t::Sequoia, + nb::rv_policy::reference, "macOS Sequoia (15.0)"_doc) + .def_static("tahoe", &version_t::Tahoe, + nb::rv_policy::reference, "macOS Tahoe (26.0)"_doc) + + LIEF_DEFAULT_STR(version_t) + ; + + obj + .def_prop_ro_static("os_version_name", [] (nb::handle) { + return Host::os_version_name(); + }, "The operating system version string"_doc) + + .def_prop_ro_static("os_version", [] (nb::handle) { + return Host::os_version(); + }, "The operating system version as a :class:`~.version_t`"_doc) + + .def_prop_ro_static("is_sip_enabled", [] (nb::handle) { + return Host::is_sip_enabled(); + }, R"doc( + Whether System Integrity Protection (SIP) is enabled on this host. + + This conservatively returns ``True`` when the status can't be determined. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/osx/pyModule.cpp b/vendor/lief/api/python/src/runtime/objects/osx/pyModule.cpp new file mode 100644 index 0000000..ecc9a8a --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/pyModule.cpp @@ -0,0 +1,62 @@ +#include "LIEF/MachO/Binary.hpp" +#include "LIEF/MachO/ParserConfig.hpp" +#include "LIEF/runtime/osx/Module.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include "typing/StrOrPath.hpp" + +namespace LIEF::runtime::osx::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Module", + R"doc( + This class exposes an OSX-specific API for a module + )doc"_doc + ); + + obj + .def_prop_ro("handle", &Module::handle, + R"doc( + Return the ``dlopen`` handle for this library as an opaque pointer. + + Return ``None`` if the function fails or if the handler can't be found + )doc"_doc + ) + .def("dlsym", &Module::dlsym, + "Resolve the symbol with the given name for the current module"_doc, + "name"_a) + + .def_static("from_handle", &Module::from_handle, + R"doc( + Create a :class:`~lief.runtime.osx.Module` from the given ``dlopen`` + handle (passed as an opaque pointer). + )doc"_doc, + "handle"_a) + + .def("parse_from_path", nb::overload_cast<>(&Module::parse_from_path, nb::const_), + "Parse the Mach-O module from its path on the filesystem"_doc) + + .def("parse_from_path", nb::overload_cast(&Module::parse_from_path, nb::const_), + "Parse the Mach-O module from its path on the filesystem and given the parser configuration"_doc, + "config"_a) + + .def("parse_from_memory", nb::overload_cast<>(&Module::parse_from_memory, nb::const_), + "Parse the Mach-O module from memory"_doc) + + .def("parse_from_memory", nb::overload_cast(&Module::parse_from_memory, nb::const_), + "Parse the Mach-O module from memory with the given configuration"_doc, + "config"_a) + ; + + m.def("dlopen", [] (LIEF::py::typing::StrOrPath name) { + return dlopen(*name.to_string()); + }, "name"_a, + "Load the library with the given path or name"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/osx/pyProcess.cpp b/vendor/lief/api/python/src/runtime/objects/osx/pyProcess.cpp new file mode 100644 index 0000000..2aa760d --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/osx/pyProcess.cpp @@ -0,0 +1,23 @@ +#include "LIEF/runtime/osx/Process.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +namespace LIEF::runtime::osx::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Process", + R"doc( + This class exposes OSX-specific API for the current process. + )doc"_doc + ); + + obj + .def_prop_ro_static("dyld_version", [] (nb::handle) { + return Process::dyld_version(); + }, "Return the version of dyld for the current process"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyAssembler.cpp b/vendor/lief/api/python/src/runtime/objects/pyAssembler.cpp new file mode 100644 index 0000000..081b66a --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyAssembler.cpp @@ -0,0 +1,50 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "LIEF/runtime/assembler.hpp" +#include "LIEF/asm/AssemblerConfig.hpp" +#include "pyLIEF.hpp" +#include "nanobind/utils.hpp" + +namespace LIEF::runtime::py { +void init_assembler(nb::module_& m) { + m.def("assemble", + [] (uint64_t address, const std::string& Asm, + assembly::AssemblerConfig& config) + { + return nb::to_bytes(runtime::assemble(address, Asm, config)); + }, "address"_a, "assembly"_a, + "config"_a = assembly::AssemblerConfig::default_config(), + R"doc( + Assemble the provided assembly code at the specified (absolute) virtual + address. + + The function returns the generated assembly bytes. + + .. code-block:: python + + from lief import runtime + code = runtime.assemble(0x7f0011223344, """ + xor rax, rbx; + mov rcx, rax; + """) + + If you need to configure the assembly engine or to define addresses for + symbols, you can provide your own :class:`~.assembly.AssemblerConfig` instance. + )doc"_doc); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyDisassembler.cpp b/vendor/lief/api/python/src/runtime/objects/pyDisassembler.cpp new file mode 100644 index 0000000..ebd0aef --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyDisassembler.cpp @@ -0,0 +1,44 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/runtime/disassembler.hpp" +#include "LIEF/asm/Instruction.hpp" +#include "pyLIEF.hpp" + +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::runtime::py { +void init_disassembler(nb::module_& m) { + m.def("disassemble", [] (uintptr_t addr) { + auto insts = LIEF::py::owning_range(runtime::disassemble(addr)); + return nb::make_iterator( + nb::type(), "instructions_it", insts); + }, "addr"_a, + R"doc( + Start disassembling instructions at the given **absolute** virtual address. + + .. code-block:: python + + from lief import runtime + for inst in runtime.disassemble(0x7f0011223344): + print(inst) + + .. seealso:: :class:`lief.assembly.Instruction` + )doc"_doc); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyHost.cpp b/vendor/lief/api/python/src/runtime/objects/pyHost.cpp new file mode 100644 index 0000000..2ce8fd4 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyHost.cpp @@ -0,0 +1,47 @@ +#include "LIEF/runtime/Host.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +namespace LIEF::runtime::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Host", + "This class represents the current host."_doc + ); + + obj + .def_prop_ro_static("name", [] (nb::handle) { + return Host::name(); + }, "The machine hostname"_doc) + + .def_prop_ro_static("home_dir", [] (nb::handle) { + return Host::home_dir(); + }, R"doc( + The user home dir (e.g. ``/home/romain`` or ``C:\Users\romain``) + )doc"_doc) + + .def_prop_ro_static("tmp_dir", [] (nb::handle) { + return Host::tmp_dir(); + }, R"doc( + Temporary directory. + + This function looks at the environment variables to determine the suitable + temp directory (e.g. ``TEMP``, ``TMPDIR``) + )doc"_doc) + + .def_prop_ro_static("config_dir", [] (nb::handle) { + return Host::config_dir(); + }, "The directory to store user-specific configuration"_doc) + + .def_prop_ro_static("cache_dir", [] (nb::handle) { + return Host::cache_dir(); + }, R"doc( + The directory where software should store their cache files + (e.g. ``$HOME/.cache``) + )doc"_doc) + + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyMemory.cpp b/vendor/lief/api/python/src/runtime/objects/pyMemory.cpp new file mode 100644 index 0000000..b361e8d --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyMemory.cpp @@ -0,0 +1,185 @@ +#include +#include "LIEF/runtime/Memory.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include +#include + +namespace LIEF::runtime::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Memory", + R"doc( + This class exposes API to access and manage memory + )doc"_doc + ); + + nb::enum_(obj, "MMAP_FLAGS", nb::is_arithmetic(), nb::is_flag(), + "Flags used when creating a memory map (mmap)."_doc + ) + .value("NONE", Memory::MMAP_FLAGS::MP_NONE) + .value("PRIVATE", Memory::MMAP_FLAGS::MP_PRIVATE, + "Changes are private to this process (copy-on-write)."_doc) + .value("ANONYMOUS", Memory::MMAP_FLAGS::MP_ANONYMOUS, + "The mapping is not backed by any file."_doc) + .value("SHARED", Memory::MMAP_FLAGS::MP_SHARED, + "Changes are shared."_doc) + .value("FIXED", Memory::MMAP_FLAGS::MP_FIXED, + "Interpret the address as a fixed requirement."_doc) + .value("JIT", Memory::MMAP_FLAGS::MP_JIT, + "Map for Just-In-Time code generation."_doc).export_values(); + + nb::enum_(obj, "PERM", nb::is_arithmetic(), nb::is_flag()) + .value("NONE", Memory::PERM::P_NONE) + .value("READ", Memory::PERM::P_READ) + .value("WRITE", Memory::PERM::P_WRITE) + .value("EXEC", Memory::PERM::P_EXEC).export_values(); + + + using Chunk = Memory::Chunk; + nb::class_(obj, "Chunk", + R"doc( + Represents a contiguous chunk of memory allocated or inspected by the runtime. + )doc"_doc + ) + .def(nb::init(), + "addr"_a, "size"_a, "permissions"_a) + .def(nb::init(), "addr"_a, "size"_a) + .def(nb::init(), "addr"_a) + .def_prop_ro("addr_ptr", nb::overload_cast<>(&Chunk::addr_ptr), + "Returns the start address of the memory chunk as an opaque pointer"_doc + ) + .def_prop_ro("addr", nb::overload_cast<>(&Chunk::addr, nb::const_), + "Returns the start address of the memory chunk"_doc + ) + .def_prop_ro("size", &Chunk::size, + "Returns the size of the memory chunk in bytes."_doc + ) + .def_prop_ro("permissions", &Chunk::permissions, + "Returns the current permissions of the memory chunk."_doc + ) + .def_prop_ro("page_start", &Chunk::page_start, + "Returns the address of the start of the page containing this chunk."_doc + ) + .def_prop_ro("page_end", &Chunk::page_end, + "Returns the address of the end of the page containing this chunk."_doc + ) + .def("change_permissions", &Chunk::change_permissions, + "Changes the permissions of the memory chunk."_doc, + "permission"_a, nb::rv_policy::reference_internal + ) + .def("make_x", &Chunk::make_x, + "Sets the permissions to Execute only."_doc, + nb::rv_policy::reference_internal + ) + .def("make_rw", &Chunk::make_rw, + "Sets the permissions to Read and Write."_doc, + nb::rv_policy::reference_internal + ) + .def("make_rx", &Chunk::make_rx, + "Sets the permissions to Read and Execute."_doc, + nb::rv_policy::reference_internal + ) + .def("make_rwx", &Chunk::make_rwx, + "Sets the permissions to read/write/exec"_doc, + nb::rv_policy::reference_internal + ) + .def("make_ro", &Chunk::make_ro, + "Sets the permissions to Read Only."_doc, + nb::rv_policy::reference_internal + ) + .def("cache_flush", &Chunk::cache_flush, + R"doc( + Flushes the instruction cache for this memory chunk. + This should be used when modifying code in memory (e.g., hooking, JIT). + )doc"_doc, + nb::rv_policy::reference_internal + ) + .def("is_valid", &Chunk::is_valid) + .def("__bool__", &Chunk::is_valid) + + .def("deallocate", &Chunk::deallocate) + + LIEF_DEFAULT_STR(Chunk); + + obj + .def_static("mmap", &Memory::mmap, + "Allocates a memory chunk through mmap-like function"_doc, + "size"_a, "flags"_a, "permissions"_a = Memory::P_NONE) + + .def_static("mmap_hint", &Memory::mmap_hint, + R"doc( + Allocates a memory chunk through mmap-like function, asking the system + to place the allocation at the address given in the first parameter. + + This address is a **hint**: it is rounded up to the next page boundary + (next allocation granularity on Windows) and the system remains free to + return a chunk located somewhere else. + )doc"_doc, + "hint"_a, "size"_a, "flags"_a, "permissions"_a = Memory::P_NONE) + + .def_static("munmap", &Memory::munmap, + "Deallocates a mmaped memory chunk"_doc, + "chunk"_a) + + .def_static("mprotect", &Memory::mprotect, + "Sets the permission of the given memory chunk"_doc, + "chunk"_a, "flags"_a) + + .def_static("perm_str", &Memory::perm_str, + "Convert the given permission into a human-readable string"_doc, + "flags"_a + ) + + .def_static("write", [] (const void* ptr, size_t size, uintptr_t addr) { + return Memory::write(reinterpret_cast(ptr), size, addr); + }, "ptr"_a, "size"_a, "addr"_a) + + .def_static("write", [] (nb::extra::memoryview buffer, uintptr_t addr) { + return Memory::write(buffer.data(), buffer.size(), addr); + }, "buffer"_a, "addr"_a) + + .def_static("write", [] (nb::bytes buffer, uintptr_t addr) { + return Memory::write(reinterpret_cast(buffer.data()), + buffer.size(), addr); + }, "buffer"_a, "addr"_a) + + .def_static("write_u8", &Memory::write, "value"_a, "addr"_a) + .def_static("write_i8", &Memory::write, "value"_a, "addr"_a) + + .def_static("write_u16", &Memory::write, "value"_a, "addr"_a) + .def_static("write_i16", &Memory::write, "value"_a, "addr"_a) + + .def_static("write_u32", &Memory::write, "value"_a, "addr"_a) + .def_static("write_i32", &Memory::write, "value"_a, "addr"_a) + + .def_static("write_u64", &Memory::write, "value"_a, "addr"_a) + .def_static("write_i64", &Memory::write, "value"_a, "addr"_a) + + .def_static("read", [] (uintptr_t addr, size_t size) { + std::vector buffer; + Memory::read(addr, buffer, size); + return nb::bytes(buffer.data(), buffer.size()); + }, "addr"_a, "size"_a) + + .def_static("read", [] (uintptr_t addr, void* out, size_t size) { + Memory::read(addr, reinterpret_cast(out), size); + }, "addr"_a, "out"_a, "size"_a) + + .def_static("read_u8", &Memory::read, "addr"_a) + .def_static("read_i8", &Memory::read, "addr"_a) + + .def_static("read_u16", &Memory::read, "addr"_a) + .def_static("read_i16", &Memory::read, "addr"_a) + + .def_static("read_u32", &Memory::read, "addr"_a) + .def_static("read_i32", &Memory::read, "addr"_a) + + .def_static("read_u64", &Memory::read, "addr"_a) + .def_static("read_i64", &Memory::read, "addr"_a); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyMemoryLayout.cpp b/vendor/lief/api/python/src/runtime/objects/pyMemoryLayout.cpp new file mode 100644 index 0000000..176cadb --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyMemoryLayout.cpp @@ -0,0 +1,61 @@ +#include +#include "LIEF/runtime/MemoryLayout.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::runtime::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "MemoryLayout", + R"doc( + This class exposes the memory layout of the current process. + )doc"_doc + ); + + using Region = MemoryLayout::Region; + nb::class_(obj, "Region", + R"doc( + A contiguous range of memory mapped in the current process. + )doc"_doc + ) + .def_prop_ro("name", &Region::name, + R"doc( + Name associated with the region: the name or the path of the module + mapped at this address (e.g. ``libc.so.6``) or the identifier of a + region that is not backed by a file (e.g. ``[stack]``, ``[heap]``). + + It can be empty for anonymous regions. + )doc"_doc + ) + .def_prop_ro("addr", &Region::addr, + "Address at which the region starts"_doc + ) + .def_prop_ro("size", &Region::size, + "Size of the region"_doc + ) + .def_prop_ro("end_addr", &Region::end_addr, + "Address at which the region ends"_doc + ) + .def("contains", &Region::contains, "addr"_a, + "Whether the given address is within this region"_doc + ) + LIEF_DEFAULT_STR(Region) + ; + + m.def("memory_layout", [] () { + auto layout = LIEF::py::owning_range(runtime::memory_layout()); + return nb::make_iterator( + nb::type(), "memory_layout_iterator", layout); + }, R"doc( + Return an iterator over the memory layout of the current process + )doc"_doc); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyModule.cpp b/vendor/lief/api/python/src/runtime/objects/pyModule.cpp new file mode 100644 index 0000000..9e88bed --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyModule.cpp @@ -0,0 +1,79 @@ +#include +#include "LIEF/runtime/Module.hpp" +#include "runtime/pyRuntime.hpp" +#include "runtime/objects/pyModule.hpp" + +#include +#include +#include +#include "nanobind/utils.hpp" + +#include "pyOwningIterator.hpp" + +namespace LIEF::runtime::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Module", + R"doc( + This class represents an in-memory module which can be an executable or a + library + )doc"_doc + ); + + obj + .def_prop_ro("name", &Module::name, + "Name of the module (e.g. ``libc.so.6, kernel32.dll, libsystem_c.dylib``)"_doc + ) + .def_prop_ro("path", &Module::path, + "Path of the module"_doc + ) + .def_prop_ro("imagebase", &Module::imagebase, + "Imagebase of the module"_doc + ) + .def_prop_ro("end", &Module::end, + "End address of the module"_doc + ) + .def_prop_ro("size", &Module::size, + "Virtual size of the current module"_doc + ) + .def("contains", &Module::contains, "addr"_a, + "Check if the current module contains the given address"_doc + ) + .def("dump", + [] (const Module& self) { + return nb::to_bytes(self.dump()); + }, + "Return the content of the module as it is currently mapped in memory"_doc + ) + .def("dump", + [] (const Module& self, const std::string& filepath) { + return nb::to_bytes(self.dump(filepath)); + }, + "Same as :meth:`dump` but also write the content into the file given in " + "parameter"_doc, "filepath"_a + ) + + LIEF_DEFAULT_STR(Module); + + m.def("modules", [] () { + auto mods = LIEF::py::owning_range(runtime::modules()); + return nb::make_iterator( + nb::type(), "modules_iterator", mods); + }, R"doc( + Return an iterator over the different modules loaded in the current process + )doc"_doc); + + m.def("module_from_name", &runtime::module_from_name, "name"_a, + "Find the module with the given name"_doc + ); + + m.def("module_from_path", &runtime::module_from_path, "path"_a, + "Find the module with the given path"_doc + ); + + m.def("module_from_addr", &runtime::module_from_addr, "addr"_a, + "Find the module that encompasses the given virtual address (absolute)"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/pyModule.hpp b/vendor/lief/api/python/src/runtime/objects/pyModule.hpp new file mode 100644 index 0000000..8aedae4 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyModule.hpp @@ -0,0 +1,53 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_MODULE_H +#define PY_LIEF_RUNTIME_MODULE_H + +#include + +#include "LIEF/runtime/linux/Module.hpp" +#include "LIEF/runtime/windows/Module.hpp" +#include "LIEF/runtime/android/Module.hpp" +#include "LIEF/runtime/osx/Module.hpp" + +namespace nanobind::detail { +template<> struct type_hook { + static const std::type_info* get(const LIEF::runtime::Module* M) { + using namespace LIEF::runtime; + if (M) { + if (Linux::Module::classof(M)) { + return &typeid(Linux::Module); + } + + if (windows::Module::classof(M)) { + return &typeid(windows::Module); + } + + if (android::Module::classof(M)) { + return &typeid(android::Module); + } + + if (osx::Module::classof(M)) { + return &typeid(osx::Module); + } + } + + return &typeid(Module); + } +}; +} + +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/pyProcess.cpp b/vendor/lief/api/python/src/runtime/objects/pyProcess.cpp new file mode 100644 index 0000000..246af64 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/pyProcess.cpp @@ -0,0 +1,62 @@ +#include "LIEF/runtime/Process.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" +#include "nanobind/stl/unordered_map.h" +#include + +namespace LIEF::runtime::py { +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Process", + R"doc( + This class represents the current process and provides functions to query + process-level information. + )doc"_doc + ); + + nb::class_(obj, "EnvVars", + R"doc(This structure wraps environment variables)doc"_doc + ) + .def_rw("vars", &Process::EnvVars::vars) + ; + + obj + .def_prop_ro_static("pid", [] (nb::handle) { + return Process::pid(); + }, "Get the Process ID of the current process."_doc) + + .def_prop_ro_static("tid", [] (nb::handle) { + return Process::tid(); + }, "Get the Thread ID of the current thread."_doc) + + .def_prop_ro_static("arch", [] (nb::handle) { + return Process::arch(); + }, "Return the target architecture of the current process."_doc) + + .def_prop_ro_static("page_size", [] (nb::handle) { + return Process::page_size(); + }, R"doc( + Return the number of bytes in a memory page. + + For instance: + * ``0x1000`` (4096 bytes) for x86_64 + * ``0x4000`` (16384 bytes) for ARM64 + )doc"_doc) + + .def_prop_ro_static("platform", [] (nb::handle) { + return Process::platform(); + }, "Return the target platform of the current process."_doc) + + .def_static("get_env", &Process::get_env, + "Return the environment variable associated with the given key"_doc, + "key"_a + ) + + .def_prop_ro_static("envs", [] (nb::handle) { + return Process::get_envs(); + }, "Return the environment variables present in the current process"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/CMakeLists.txt b/vendor/lief/api/python/src/runtime/objects/windows/CMakeLists.txt new file mode 100644 index 0000000..f70d60b --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/CMakeLists.txt @@ -0,0 +1,9 @@ +target_sources(pyLIEF PRIVATE + init.cpp + pyModule.cpp + pyHost.cpp + pyInjector.cpp + pyProcess.cpp + pyPEB.cpp + pyLdrDataTableEntry.cpp +) diff --git a/vendor/lief/api/python/src/runtime/objects/windows/init.cpp b/vendor/lief/api/python/src/runtime/objects/windows/init.cpp new file mode 100644 index 0000000..666cfc7 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/init.cpp @@ -0,0 +1,41 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "runtime/objects/windows/init.hpp" +#include "runtime/pyRuntime.hpp" + +namespace LIEF::runtime::windows { +class Module; +class Host; +class Process; +class PEB; +class LdrDataTableEntry; +} + +namespace LIEF::runtime::windows::py { +void init_injector(nb::module_& m); + +void init(nb::module_& m) { + nb::module_ win_mod = m.def_submodule("windows"); + + create(win_mod); + create(win_mod); + create(win_mod); + create(win_mod); + create(win_mod); + + init_injector(win_mod); +} +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/init.hpp b/vendor/lief/api/python/src/runtime/objects/windows/init.hpp new file mode 100644 index 0000000..4886f72 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/init.hpp @@ -0,0 +1,23 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_WIN_INIT_H +#define PY_LIEF_RUNTIME_WIN_INIT_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::windows::py { +void init(nb::module_& m); +} +#endif diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyHost.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyHost.cpp new file mode 100644 index 0000000..9081d2f --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyHost.cpp @@ -0,0 +1,48 @@ +#include "LIEF/runtime/windows/Host.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" + +#include + +namespace LIEF::runtime::windows::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Host", + R"doc( + This class exposes Windows-specific host information. + )doc"_doc + ); + + using version_t = Host::version_t; + nb::class_(obj, "version_t", + R"doc( + This class represents a Windows version number. + )doc"_doc + ) + .def(nb::init<>()) + .def(nb::init(), + "major"_a, "minor"_a, "build_number"_a) + .def_rw("major", &version_t::major, "Major version number"_doc) + .def_rw("minor", &version_t::minor, "Minor version number"_doc) + .def_rw("build_number", &version_t::build_number, "Build number"_doc) + + .def("__eq__", &version_t::operator==) + .def("__ne__", &version_t::operator!=) + .def("__le__", &version_t::operator<=) + .def("__gt__", &version_t::operator>) + .def("__ge__", &version_t::operator>=) + .def("__lt__", &version_t::operator<) + + LIEF_DEFAULT_STR(version_t) + ; + + obj + .def_prop_ro_static("version", [] (nb::handle) { + return Host::version(); + }, "The Windows version (e.g. ``10.0.26200``)"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyInjector.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyInjector.cpp new file mode 100644 index 0000000..d93dcb3 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyInjector.cpp @@ -0,0 +1,41 @@ +#include "LIEF/runtime/windows/injector.hpp" +#include "runtime/pyRuntime.hpp" +#include "pyErr.hpp" + +#include +#include +namespace LIEF::runtime::windows::py { + +void init_injector(nb::module_& m) { + nb::class_(m, "injection_context_t", + R"doc( + Describes how to spawn a new process and inject a library into it. + )doc"_doc + ) + .def(nb::init<>()) + .def_rw("target_path", &injection_context_t::target_path, + "Absolute path to the target executable to spawn."_doc) + .def_rw("args", &injection_context_t::args, + "Command-line arguments passed to the spawned process."_doc) + .def_rw("library", &injection_context_t::library, + "Absolute path to the library (DLL) that should be injected."_doc) + .def_rw("env", &injection_context_t::env, + R"doc( + Environment variables to set in the spawned process. If left empty, + the current process environment is inherited. + )doc"_doc) + ; + + m.def("inject_spawn", + [] (const injection_context_t& ctx) { + return LIEF::py::error_or(&inject_spawn, ctx); + }, + "ctx"_a, + R"doc( + Spawn the target described by the given injection context and inject the + associated library before the main thread starts executing. + )doc"_doc + ); +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyLdrDataTableEntry.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyLdrDataTableEntry.cpp new file mode 100644 index 0000000..022dc75 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyLdrDataTableEntry.cpp @@ -0,0 +1,211 @@ +#include + +#include "LIEF/runtime/windows/LdrDataTableEntry.hpp" +#include "runtime/pyRuntime.hpp" + +#include "nanobind/stl/string.h" +#include + +namespace LIEF::runtime::windows::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "LdrDataTableEntry", + R"doc( + This class exposes a user-friendly interface over a ``LDR_DATA_TABLE_ENTRY``, + the structure used by the Windows loader to describe a module loaded in the + current process. + + These entries can be enumerated through :meth:`lief.runtime.windows.PEB.entries`. + )doc"_doc + ) + .def_prop_ro("dll_base", &LdrDataTableEntry::dll_base, + "Base address at which the module is mapped in memory (``DllBase``)."_doc) + + .def_prop_ro("entry_point", &LdrDataTableEntry::entry_point, + "Address of the entry point of the module (``EntryPoint``)."_doc) + + .def_prop_ro("size_of_image", &LdrDataTableEntry::size_of_image, + "Size (in bytes) of the module's image in memory (``SizeOfImage``)."_doc) + + .def_prop_ro("full_dll_name", &LdrDataTableEntry::full_dll_name, + R"doc( + Full path of the module (``FullDllName``), + e.g. ``C:\Windows\System32\ntdll.dll``. + )doc"_doc) + + .def_prop_ro("base_dll_name", &LdrDataTableEntry::base_dll_name, + "Base name of the module (``BaseDllName``), e.g. ``ntdll.dll``."_doc) + + .def_prop_ro("flags", &LdrDataTableEntry::flags, + "Loader flags describing the state of the module (``Flags``)."_doc) + + .def_prop_ro("obsolete_load_count", &LdrDataTableEntry::obsolete_load_count, + R"doc( + Legacy load count of the module (``ObsoleteLoadCount``). Superseded by + :attr:`~.reference_count` on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("tls_index", &LdrDataTableEntry::tls_index, + "TLS slot index assigned to the module, or ``0`` when it has no TLS " + "(``TlsIndex``)."_doc) + + .def_prop_ro("time_date_stamp", &LdrDataTableEntry::time_date_stamp, + "``TimeDateStamp`` of the module as cached by the loader."_doc) + + .def_prop_ro("entry_point_activation_context", + &LdrDataTableEntry::entry_point_activation_context, + R"doc( + Address of the activation context associated with the module's entry + point. + )doc"_doc) + + .def_prop_ro("lock", &LdrDataTableEntry::lock, + "Address of the per-entry loader lock."_doc) + + .def_prop_ro("ddag_node", &LdrDataTableEntry::ddag_node, + R"doc( + Address of the dependency-graph node of the module (``DdagNode``). + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("load_context", &LdrDataTableEntry::load_context, + R"doc( + Address of the loader context used while the module is being snapped + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("parent_dll_base", &LdrDataTableEntry::parent_dll_base, + R"doc( + Base address of the module that triggered the load of this one. + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("switch_back_context", &LdrDataTableEntry::switch_back_context, + R"doc( + Address of the CHPE switch-back context. + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("original_base", &LdrDataTableEntry::original_base, + R"doc( + Preferred base address recorded in the PE headers + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("load_time", &LdrDataTableEntry::load_time, + R"doc( + Time at which the module was loaded. + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("base_name_hash_value", + &LdrDataTableEntry::base_name_hash_value, + R"doc( + Hash of the module's base name used to index the loader tables + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("load_reason", &LdrDataTableEntry::load_reason, + R"doc( + Reason why the module was loaded, as a ``LDR_DLL_LOAD_REASON`` value + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("implicit_path_options", + &LdrDataTableEntry::implicit_path_options, + R"doc( + Path-search options implied when the module was resolved + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("reference_count", &LdrDataTableEntry::reference_count, + R"doc( + Number of references currently held on the module. + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("dependent_load_flags", + &LdrDataTableEntry::dependent_load_flags, + R"doc( + Flags controlling how the statically-linked dependencies of the module + are loaded. + + .. note:: + + Available on Windows 8 and later. + )doc"_doc) + + .def_prop_ro("signing_level", &LdrDataTableEntry::signing_level, + R"doc( + Signing level of the module's image, as a ``SE_SIGNING_LEVEL`` value + + .. note:: + + Available on Windows 10 and later. + )doc"_doc) + + .def_prop_ro("check_sum", &LdrDataTableEntry::check_sum, + R"doc( + Image checksum cached by the loader + + .. note:: + + Available on Windows 10 and later. + )doc"_doc) + + .def_prop_ro("active_patch_image_base", + &LdrDataTableEntry::active_patch_image_base, + R"doc( + Base address of the active hot-patch image, if any. + + .. note:: + + Available on Windows 11 and later. + )doc"_doc) + + .def_prop_ro("hot_patch_state", &LdrDataTableEntry::hot_patch_state, + R"doc( + State of the hot-patch engine for this module, as a + ``LDR_HOT_PATCH_STATE`` value. + + .. note:: + + Available on Windows 11 and later. + )doc"_doc) + + LIEF_DEFAULT_STR(LdrDataTableEntry) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyModule.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyModule.cpp new file mode 100644 index 0000000..2651a07 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyModule.cpp @@ -0,0 +1,85 @@ +#include "LIEF/PE/ParserConfig.hpp" +#include "LIEF/PE/Binary.hpp" +#include "LIEF/runtime/windows/Module.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include "typing/StrOrPath.hpp" + +namespace LIEF::runtime::windows::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Module", + R"doc( + This class exposes a Windows-specific API for a module + )doc"_doc + ); + + obj + .def_prop_ro("handle", &Module::handle, + R"doc( + Return the ``HMODULE`` handle as an opaque pointer. + + Return ``None`` if the function fails or if the handler can't be found + )doc"_doc + ) + .def("dlsym", &Module::dlsym, + "Resolve the symbol with the given name for the current module"_doc, + "name"_a) + + .def_static("from_handle", &Module::from_handle, + R"doc( + Create a :class:`~lief.runtime.windows.Module` from the given + ``HMODULE`` handle (passed as an opaque pointer). + )doc"_doc, + "handle"_a) + + .def("parse_from_path", nb::overload_cast<>(&Module::parse_from_path, nb::const_), + "Parse the PE module from its path on the filesystem"_doc) + + .def("parse_from_path", nb::overload_cast(&Module::parse_from_path, nb::const_), + "Parse the PE module from its path on the filesystem and given the parser configuration"_doc, + "config"_a) + + .def("parse_from_memory", nb::overload_cast<>(&Module::parse_from_memory, nb::const_), + "Parse the PE module from memory"_doc) + + .def("parse_from_memory", nb::overload_cast(&Module::parse_from_memory, nb::const_), + "Parse the PE module from memory with the given configuration"_doc, + "config"_a) + ; + + + m.def("dlopen", [] (LIEF::py::typing::StrOrPath name) { + return windows::dlopen(*name.to_string()); + }, + "Load the windows library with the given path or name."_doc, + "name"_a + ); + + m.def("find_module", &windows::find_module, + R"doc( + Try to get the :class:`~lief.runtime.windows.Module` with the given name. + + Return ``None`` if the module is not found. + + .. code-block:: python + + if ntdll := lief.runtime.windows.find_module("ntdll.dll"): + print(ntdll.path) + + .. note:: + + This function relies on the Windows API ``GetModuleHandle`` which is + more efficient than the generic implementation + :func:`lief.runtime.module_from_name`. + )doc"_doc, + "name"_a + ); + +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyPEB.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyPEB.cpp new file mode 100644 index 0000000..d4b1185 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyPEB.cpp @@ -0,0 +1,65 @@ +#include "LIEF/runtime/windows/PEB.hpp" +#include "LIEF/runtime/windows/LdrDataTableEntry.hpp" +#include "runtime/pyRuntime.hpp" + +#include +#include + +#include "pyOwningIterator.hpp" + +namespace LIEF::runtime::windows::py { + +template<> +void create(nb::module_& m) { + nb::class_(m, "PEB", + R"doc( + This class exposes a user-friendly interface over the Process Environment + Block (PEB) of the current process. + + It can be accessed through :attr:`lief.runtime.windows.Process.peb`. + )doc"_doc + ) + .def_prop_ro("being_debugged", &PEB::being_debugged, + R"doc( + Whether the current process is being debugged. + )doc"_doc) + + .def_prop_ro("ldr", &PEB::ldr, + R"doc( + Address of the loader data structure (``PEB_LDR_DATA``) which holds the + list of the modules loaded in the current process. + )doc"_doc) + + .def_prop_ro("process_parameters", &PEB::process_parameters, + R"doc( + Address of the process parameters (``RTL_USER_PROCESS_PARAMETERS``) which + holds information such as the command line or the current directory. + )doc"_doc) + + .def_prop_ro("atl_thunk_slist_ptr", &PEB::atl_thunk_slist_ptr, + "Address of the per-process ATL thunk SList (single-linked list)."_doc) + + .def_prop_ro("atl_thunk_slist_ptr32", &PEB::atl_thunk_slist_ptr32, + "32-bit value of the ATL thunk SList pointer."_doc) + + .def_prop_ro("post_process_init_routine", &PEB::post_process_init_routine, + R"doc( + Address of the routine called once the process completed its + initialization (``PostProcessInitRoutine``). + )doc"_doc) + + .def_prop_ro("session_id", &PEB::session_id, + "Session ID associated with the current process."_doc) + + .def_prop_ro("entries", [] (const PEB& self) { + auto entries = LIEF::py::owning_range(self.entries()); + return nb::make_iterator( + nb::type(), "ldr_entries_iterator", entries); + }, R"doc( + Iterate over the modules referenced by the loader data of the PEB, in load + order, yielding :class:`~lief.runtime.windows.LdrDataTableEntry` objects. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/objects/windows/pyProcess.cpp b/vendor/lief/api/python/src/runtime/objects/windows/pyProcess.cpp new file mode 100644 index 0000000..6ed5365 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/objects/windows/pyProcess.cpp @@ -0,0 +1,30 @@ +#include "LIEF/runtime/windows/Process.hpp" +#include "LIEF/runtime/windows/PEB.hpp" +#include "runtime/pyRuntime.hpp" + +#include + +namespace LIEF::runtime::windows::py { + +template<> +void create(nb::module_& m) { + nb::class_ obj(m, "Process", + R"doc( + This class exposes Windows-specific API for the current process. + )doc"_doc + ); + + obj + .def_prop_ro_static("peb", [] (nb::handle) { + return Process::peb(); + }, + R"doc( + Return an interface over the internal Process Environment Block (PEB) of + the current process. + + Return ``None`` if the PEB cannot be located. + )doc"_doc) + ; +} + +} diff --git a/vendor/lief/api/python/src/runtime/pyRuntime.hpp b/vendor/lief/api/python/src/runtime/pyRuntime.hpp new file mode 100644 index 0000000..70ec696 --- /dev/null +++ b/vendor/lief/api/python/src/runtime/pyRuntime.hpp @@ -0,0 +1,44 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_RUNTIME_H +#define PY_LIEF_RUNTIME_H +#include "pyLIEF.hpp" + +namespace LIEF::runtime::py { +template +void create(nb::module_&); +} + +namespace LIEF::runtime::Linux::py { +template +void create(nb::module_&); +} + +namespace LIEF::runtime::android::py { +template +void create(nb::module_&); +} + +namespace LIEF::runtime::windows::py { +template +void create(nb::module_&); +} + +namespace LIEF::runtime::osx::py { +template +void create(nb::module_&); +} +#endif diff --git a/vendor/lief/api/python/src/spdlog/sinks/python_sink.h b/vendor/lief/api/python/src/spdlog/sinks/python_sink.h new file mode 100644 index 0000000..6a48b98 --- /dev/null +++ b/vendor/lief/api/python/src/spdlog/sinks/python_sink.h @@ -0,0 +1,74 @@ +#pragma once + +#include + +#include +#include +#include + +#include + +namespace spdlog { +namespace sinks { + +struct py_stderr_tag {}; +struct py_stdout_tag {}; + +template +class python_base_sink final : public base_sink { + public: + explicit python_base_sink() = default; + + protected: + void set_pattern_(const std::string &pattern) override { + nanobind::ft_lock_guard lock(pymu_); + base_sink::set_pattern_(pattern); + } + + void set_formatter_(std::unique_ptr sink_formatter) override { + nanobind::ft_lock_guard lock(pymu_); + base_sink::set_formatter_(std::move(sink_formatter)); + } + + void flush_() override {} + void sink_it_(const details::log_msg &msg) override { + // See: https://github.com/python/cpython/blob/453da532fee26dc4f83d4cab77eb9bdb17b941e6/Python/sysmodule.c#L4001 + static constexpr auto BUFFER_SIZE = 1000; + memory_buf_t formatted; + base_sink::formatter_->format(msg, formatted); + std::string msg_str(formatted.data(), formatted.size()); + + const size_t nb_chunks = (msg_str.size() / BUFFER_SIZE) + 1; + + for (size_t i = 0; i < nb_chunks; ++i) { + const size_t rem = msg_str.size() - i * BUFFER_SIZE; + std::string msg = msg_str.substr(i * BUFFER_SIZE, + std::min(rem, BUFFER_SIZE)); + + if constexpr (std::is_same_v) { + PySys_WriteStderr("%s", msg.c_str()); + } else { + PySys_WriteStdout("%s", msg.c_str()); + } + } + } + private: + Mutex pymu_; +}; + +using python_stderr_sink_mt = python_base_sink; +using python_stderr_sink_st = python_base_sink; +} + +template +inline std::shared_ptr stderr_python_mt(const std::string& logger_name) +{ + return Factory::template create(logger_name); +} + +template +inline std::shared_ptr stderr_python_st(const std::string& logger_name) +{ + return Factory::template create(logger_name); +} +} diff --git a/vendor/lief/api/python/src/typing.hpp b/vendor/lief/api/python/src/typing.hpp new file mode 100644 index 0000000..cd128f9 --- /dev/null +++ b/vendor/lief/api/python/src/typing.hpp @@ -0,0 +1,46 @@ +/* Copyright 2018 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_TYPING_H +#define PY_LIEF_TYPING_H +#include + +#define LIEF_PY_DEFAULT_CTOR(Class_, Ty) \ + Class_(Ty obj_) : nanobind::object(obj_, nanobind::detail::borrow_t{}) {} + +#define NB_OBJECT_DEFAULT_NONAME(Type, Parent, Check) \ +public: \ + NB_INLINE Type(handle h, ::nanobind::detail::borrow_t) \ + : Parent(h, ::nanobind::detail::borrow_t{}) { } \ + NB_INLINE Type(handle h, ::nanobind::detail::steal_t) \ + : Parent(h, ::nanobind::detail::steal_t{}) { } \ + NB_INLINE static bool check_(handle h) { \ + return Check(h.ptr()); \ + } \ + NB_INLINE Type() : Parent() {} + +struct IntOrNone : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(IntOrNone, nanobind::object); + + static constexpr auto Name = nanobind::detail::const_name("Optional[int]"); + + NB_OBJECT_DEFAULT_NONAME(IntOrNone, object, check) + static bool check(handle /*h*/) { + return true; + } +}; + + +#endif diff --git a/vendor/lief/api/python/src/typing/CMakeLists.txt b/vendor/lief/api/python/src/typing/CMakeLists.txt new file mode 100644 index 0000000..55537aa --- /dev/null +++ b/vendor/lief/api/python/src/typing/CMakeLists.txt @@ -0,0 +1,5 @@ +target_sources(pyLIEF PRIVATE + InputParser.cpp + StrOrPath.cpp +) + diff --git a/vendor/lief/api/python/src/typing/InputParser.cpp b/vendor/lief/api/python/src/typing/InputParser.cpp new file mode 100644 index 0000000..ff54c70 --- /dev/null +++ b/vendor/lief/api/python/src/typing/InputParser.cpp @@ -0,0 +1,56 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LIEF/logging.hpp" + +#include + +#include "typing/InputParser.hpp" +#include "LIEF/BinaryStream/SpanStream.hpp" +#include "LIEF/BinaryStream/VectorStream.hpp" +#include "pyIOStream.hpp" +#include "pyutils.hpp" + +namespace LIEF::py::typing { +std::unique_ptr InputParser::into_stream() { + if (auto path_str = path_to_str(*this)) { + if (auto strm = VectorStream::from_file(*path_str)) { + return std::make_unique(std::move(*strm)); + } + return nullptr; + } + + if (nb::isinstance(*this)) { + auto bytes = nb::cast(*this); + return std::make_unique( + static_cast(bytes.data()), bytes.size() + ); + } + + if (nb::isinstance(*this)) { + auto bytes = nb::cast>(*this); + return std::make_unique(std::move(bytes)); + } + + if (auto stream = PyIOStream::from_python(*this)) { + return std::make_unique(std::move(*stream)); + } + + logging::log(logging::Level::Err, + "LIEF parser interface does not support this Python object: " + + type2str(*this)); + return nullptr; +} +} diff --git a/vendor/lief/api/python/src/typing/InputParser.hpp b/vendor/lief/api/python/src/typing/InputParser.hpp new file mode 100644 index 0000000..c639a5c --- /dev/null +++ b/vendor/lief/api/python/src/typing/InputParser.hpp @@ -0,0 +1,80 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_TYPING_INPUT_PARSER_H +#define PY_LIEF_TYPING_INPUT_PARSER_H +#include "pyLIEF.hpp" +#include "typing.hpp" +#include "LIEF/config.h" + +#include +#include + +namespace LIEF { +class BinaryStream; +} + +namespace LIEF::py::typing { + +constexpr auto out_descr() { + return nb::detail::union_name( +#if LIEF_PE_SUPPORT + nb::detail::const_name("_lief.PE.Binary"), +#endif + +#if LIEF_OAT_SUPPORT + nb::detail::const_name("_lief.OAT.Binary"), +#endif + +#if LIEF_ELF_SUPPORT + nb::detail::const_name("_lief.ELF.Binary"), +#endif + +#if LIEF_MACHO_SUPPORT + nb::detail::const_name("_lief.MachO.Binary"), +#endif + +#if LIEF_COFF_SUPPORT + nb::detail::const_name("_lief.COFF.Binary"), +#endif + + nb::detail::const_name("None") + ); +} + +struct InputParser : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(InputParser, nanobind::object); + + NB_OBJECT_DEFAULT(InputParser, object, "Union[str | io.IOBase | os.PathLike | bytes | list[int]]", check) + + std::unique_ptr into_stream(); + + static bool check(handle /*h*/) { + return true; + } +}; + +struct OutputParser : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(OutputParser, nanobind::object); + + static constexpr auto Name = out_descr(); + NB_OBJECT_DEFAULT_NONAME(OutputParser, object, check); + + static bool check(handle /*h*/) { + return true; + } +}; +} +#endif diff --git a/vendor/lief/api/python/src/typing/StrOrPath.cpp b/vendor/lief/api/python/src/typing/StrOrPath.cpp new file mode 100644 index 0000000..a6931d6 --- /dev/null +++ b/vendor/lief/api/python/src/typing/StrOrPath.cpp @@ -0,0 +1,43 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "typing/StrOrPath.hpp" + +namespace LIEF::py::typing { + +std::optional StrOrPath::to_string() { + PyObject* buf = PyOS_FSPath(this->ptr()); + if (!buf) { + PyErr_Clear(); + return std::nullopt; + } + + PyObject* native = nullptr; + std::string path_str; + if (PyUnicode_FSConverter(buf, &native) != 0) { + if (char* c_str = PyBytes_AsString(native)) { + path_str = c_str; + } + } + Py_XDECREF(native); + Py_DECREF(buf); + if (PyErr_Occurred()) { + PyErr_Clear(); + return std::nullopt; + } + + return path_str; +} +} diff --git a/vendor/lief/api/python/src/typing/StrOrPath.hpp b/vendor/lief/api/python/src/typing/StrOrPath.hpp new file mode 100644 index 0000000..f9cae80 --- /dev/null +++ b/vendor/lief/api/python/src/typing/StrOrPath.hpp @@ -0,0 +1,47 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PY_LIEF_TYPING_PATH_OR_STR_H +#define PY_LIEF_TYPING_PATH_OR_STR_H +#include "pyLIEF.hpp" +#include "typing.hpp" + +#include +#include + +#include + + +namespace LIEF::py::typing { + +struct StrOrPath : public nanobind::object { + LIEF_PY_DEFAULT_CTOR(StrOrPath, nanobind::object); + + NB_OBJECT_DEFAULT(StrOrPath, object, "Union[str, os.PathLike]", check) + + std::optional to_string(); + + static bool check(handle h) { + PyObject* buf = PyOS_FSPath(h.ptr()); + if (buf == nullptr) { + PyErr_Clear(); + return false; + } + return true; + } +}; + +} +#endif diff --git a/vendor/lief/api/python/ty.toml b/vendor/lief/api/python/ty.toml new file mode 100644 index 0000000..982319a --- /dev/null +++ b/vendor/lief/api/python/ty.toml @@ -0,0 +1,8 @@ +[environment] +python-version = "3.10" + +[rules] +unused-type-ignore-comment = "ignore" +unused-ignore-comment = "ignore" +invalid-argument-type = "ignore" +redundant-final-classvar = "ignore" diff --git a/vendor/lief/api/rust/CMakeLists.txt b/vendor/lief/api/rust/CMakeLists.txt new file mode 100644 index 0000000..fb4dff2 --- /dev/null +++ b/vendor/lief/api/rust/CMakeLists.txt @@ -0,0 +1,14 @@ +target_include_directories(LIB_LIEF PUBLIC + "$") + +add_subdirectory(src) + +if(LIEF_INSTALL) + install( + DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/include/ + DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} + COMPONENT headers) +endif() + + + diff --git a/vendor/lief/api/rust/cmake-ffi/CMakeLists.txt b/vendor/lief/api/rust/cmake-ffi/CMakeLists.txt new file mode 100644 index 0000000..54e96d7 --- /dev/null +++ b/vendor/lief/api/rust/cmake-ffi/CMakeLists.txt @@ -0,0 +1,56 @@ +cmake_minimum_required(VERSION 3.24) + +project(lief-rust-ffi) + +option(INSTALL_LIEF_CORE "Whether the libLIEF library should be installed along with lief-sys" ON) + +if (NOT DEFINED LIEF_RUST_FFI_SRC) + message(FATAL_ERROR "'LIEF_RUST_FFI_SRC' is not set") +endif() + +find_package(LIEF REQUIRED) + +message(STATUS "Rust FFI source: ${LIEF_RUST_FFI_SRC}") + +file(GLOB_RECURSE LIEF_SYS_GENERATED_SRC + CONFIGURE_DEPENDS + ${LIEF_RUST_FFI_SRC}/*.cpp +) + +add_library(lief-sys STATIC + ${LIEF_SYS_GENERATED_SRC} + + rust_cpp_bridge.cpp +) + +set_target_properties(lief-sys PROPERTIES + POSITION_INDEPENDENT_CODE ON + CXX_STANDARD 17 + CXX_STANDARD_REQUIRED ON + CXX_VISIBILITY_PRESET hidden + C_VISIBILITY_PRESET hidden + OUTPUT_NAME "lief-sys" +) + +target_compile_options(lief-sys PRIVATE + -O3 + -fno-rtti -fno-exceptions + -ffunction-sections -fdata-sections + -fvisibility=hidden -fvisibility-inlines-hidden +) + +get_property(LIEF_LIB_LOCATION TARGET LIEF::LIEF PROPERTY LOCATION) +install(TARGETS lief-sys + LIBRARY DESTINATION lib/ + ARCHIVE DESTINATION lib/ + RUNTIME DESTINATION lib/ +) + +if (INSTALL_LIEF_CORE) + install(FILES ${LIEF_LIB_LOCATION} DESTINATION lib/) +endif() + +target_include_directories(lief-sys PUBLIC + ${LIEF_RUST_FFI_SRC} + ${LIEF_INCLUDE_DIRS} +) diff --git a/vendor/lief/api/rust/cmake-ffi/rust_cpp_bridge.cpp b/vendor/lief/api/rust/cmake-ffi/rust_cpp_bridge.cpp new file mode 100644 index 0000000..1e6f44c --- /dev/null +++ b/vendor/lief/api/rust/cmake-ffi/rust_cpp_bridge.cpp @@ -0,0 +1,30 @@ +#include "asm/config.hpp" + +#include "LIEF/rust/asm/AssemblerConfig.hpp" + +#include + +class RustAssemblerConfig : public LIEF::assembly::AssemblerConfig { + public: + RustAssemblerConfig(const AssemblerConfig_r& impl) : + LIEF::assembly::AssemblerConfig(), + impl_(const_cast(&impl)) {} + + std::optional resolve_symbol(const std::string& name) override { + int64_t addr = impl_->resolve_symbol(name); + if (addr < 0) { + return std::nullopt; + } + return addr; + } + + ~RustAssemblerConfig() override = default; + + protected: + AssemblerConfig_r* impl_ = nullptr; +}; + +std::unique_ptr + from_rust(const AssemblerConfig_r& config) { + return std::make_unique(config); +} diff --git a/vendor/lief/api/rust/crates/Cargo.lock b/vendor/lief/api/rust/crates/Cargo.lock new file mode 100644 index 0000000..21aa6e1 --- /dev/null +++ b/vendor/lief/api/rust/crates/Cargo.lock @@ -0,0 +1,2305 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "addr2line" +version = "0.25.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b5d307320b3181d6d7954e663bd7c774a838b8220fe0593c86d9fb09f498b4b" +dependencies = [ + "gimli", +] + +[[package]] +name = "adler2" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa" + +[[package]] +name = "anstream" +version = "1.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d" +dependencies = [ + "anstyle", + "anstyle-parse", + "anstyle-query", + "anstyle-wincon", + "colorchoice", + "is_terminal_polyfill", + "utf8parse", +] + +[[package]] +name = "anstyle" +version = "1.0.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" + +[[package]] +name = "anstyle-parse" +version = "1.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e" +dependencies = [ + "utf8parse", +] + +[[package]] +name = "anstyle-query" +version = "1.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "anstyle-wincon" +version = "3.0.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d" +dependencies = [ + "anstyle", + "once_cell_polyfill", + "windows-sys 0.61.2", +] + +[[package]] +name = "atomic-waker" +version = "1.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1505bd5d3d116872e7271a6d4e16d81d0c8570876c8de68093a09ac269d8aac0" + +[[package]] +name = "autocfg" +version = "1.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53" + +[[package]] +name = "aws-lc-rs" +version = "1.18.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ce2b2dcc879c3bae0d371e77c99f2238400ef24ec001394befa67b6e543add9e" +dependencies = [ + "aws-lc-sys", + "zeroize", +] + +[[package]] +name = "aws-lc-sys" +version = "0.44.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f09fae7be8bb3174e05c6afdb34199e6dc0c7c04ba9fa237b1967adfbde27483" +dependencies = [ + "cc", + "cmake", + "dunce", + "fs_extra", + "pkg-config", +] + +[[package]] +name = "backtrace" +version = "0.3.76" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb531853791a215d7c62a30daf0dde835f381ab5de4589cfe7c649d2cbe92bd6" +dependencies = [ + "addr2line", + "cfg-if", + "libc", + "miniz_oxide", + "object", + "rustc-demangle", + "windows-link", +] + +[[package]] +name = "backtrace-ext" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "537beee3be4a18fb023b570f80e3ae28003db9167a751266b259926e25539d50" +dependencies = [ + "backtrace", +] + +[[package]] +name = "base64" +version = "0.22.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6" + +[[package]] +name = "bitflags" +version = "2.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b588b76d00fde79687d7646a9b5bdf3cc0f655e0bbd080335a95d7e96f3587da" + +[[package]] +name = "bumpalo" +version = "3.20.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72f5acc6cb2ba439de613abc23857ec3d78374d8ed5ac84e9d11336e87da8649" + +[[package]] +name = "bytes" +version = "1.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fc652a48c352aef3ea3aed32080501cf3ef6ed5da78602a020c991775b0aff04" + +[[package]] +name = "cc" +version = "1.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "509591b7bcd67f4ef775afad7662703b4935daaa6ec0e5605cfb1090b32a2b6d" +dependencies = [ + "find-msvc-tools", + "jobserver", + "libc", + "shlex", +] + +[[package]] +name = "cfg-if" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" + +[[package]] +name = "cfg_aliases" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f079e83a288787bcd14a6aea84cee5c87a67c5a3e660c30f557a3d24761b3527" + +[[package]] +name = "chacha20" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d524456ba66e72eb8b115ff89e01e497f8e6d11d78b70b1aa13c0fbd97540a81" +dependencies = [ + "cfg-if", + "cpufeatures", + "rand_core", +] + +[[package]] +name = "clap" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "473c7e07f409a8d772161724aa8db6a765a2532a70f9667eeb7b49d3d02fbdca" +dependencies = [ + "clap_builder", + "clap_derive", +] + +[[package]] +name = "clap_builder" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7b48fea5a88e9ae728a2dcbedbfc0e730f7d60da42e1cb049a83c9fb8b789889" +dependencies = [ + "anstream", + "anstyle", + "clap_lex", + "strsim", +] + +[[package]] +name = "clap_derive" +version = "4.6.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d012d2b9d65aca7f18f4d9878a045bc17899bba951561ba5ec3c2ba1eed9a061" +dependencies = [ + "heck", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "clap_lex" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" + +[[package]] +name = "cmake" +version = "0.1.58" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c0f78a02292a74a88ac736019ab962ece0bc380e3f977bf72e376c5d78ff0678" +dependencies = [ + "cc", +] + +[[package]] +name = "codespan-reporting" +version = "0.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "af491d569909a7e4dee0ad7db7f5341fef5c614d5b8ec8cf765732aba3cff681" +dependencies = [ + "serde", + "termcolor", + "unicode-width 0.2.2", +] + +[[package]] +name = "colorchoice" +version = "1.0.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570" + +[[package]] +name = "combine" +version = "4.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ba5a308b75df32fe02788e748662718f03fde005016435c444eea572398219fd" +dependencies = [ + "bytes", + "memchr", +] + +[[package]] +name = "core-foundation" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2a6cd9ae233e7f62ba4e9353e81a88df7fc8a5987b8d445b4d90c879bd156f6" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "core-foundation-sys" +version = "0.8.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "773648b94d0e5d620f64f280777445740e61fe701025087ec8b57f45c791888b" + +[[package]] +name = "cpufeatures" +version = "0.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b2a41393f66f16b0823bb79094d54ac5fbd34ab292ddafb9a0456ac9f87d201" +dependencies = [ + "libc", +] + +[[package]] +name = "crc32fast" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511" +dependencies = [ + "cfg-if", +] + +[[package]] +name = "cxx" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6fe442a792c7c736eea18b32a7f8a3b63cf8aafabda6760042dc2fdeda456291" +dependencies = [ + "cc", + "cxx-build", + "cxxbridge-cmd", + "cxxbridge-flags", + "cxxbridge-macro", + "foldhash", + "link-cplusplus", +] + +[[package]] +name = "cxx-build" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3184a94384c663718698311a78a51ac00c484c10b4eeac06fb0a068c5f64fa2" +dependencies = [ + "cc", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "scratch", + "syn 3.0.3", +] + +[[package]] +name = "cxx-gen" +version = "0.7.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fb0f24fd8cafa20f043e24372ca5d8273ab1fdce055ee977b989f82c1bcd89b5" +dependencies = [ + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-cmd" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0148d8fd1199329ddf1d157a5e134e51ceff37c6a7ddd38615c399d81cb05d8d" +dependencies = [ + "clap", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-flags" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "52850339faed2eaadd24e286dc1d8268cc6f8a7bd9524d713adc9099566b4c89" + +[[package]] +name = "cxxbridge-macro" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2c77c856545d886c9bd5215409ebb63b925e262135248b50c79e5a5f194ee47c" +dependencies = [ + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "deranged" +version = "0.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7cd812cc2bc1d69d4764bd80df88b4317eaef9e773c75226407d9bc0876b211c" +dependencies = [ + "powerfmt", +] + +[[package]] +name = "displaydoc" +version = "0.2.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6232dd377dcc64799954cbd3a9bb882e9cdc1308ccd87b1c098f1fb2eaf82a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "dunce" +version = "1.0.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92773504d58c093f6de2459af4af33faa518c13451eb8f2b5698ed3d36e7c813" + +[[package]] +name = "equivalent" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" + +[[package]] +name = "errno" +version = "0.3.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "fastrand" +version = "2.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "da7c62ceae207dd37ea5b845da6a0696c799f85e97da1ab5b7910be3c1c80223" + +[[package]] +name = "find-msvc-tools" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d45db016d36b838f563236e9193d0ee6ce38f3f68b6c94e914b4929c96bbb890" + +[[package]] +name = "flate2" +version = "1.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c" +dependencies = [ + "miniz_oxide", + "zlib-rs", +] + +[[package]] +name = "foldhash" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77ce24cb58228fbb8aa041425bb1050850ac19177686ea6e0f41a70416f56fdb" + +[[package]] +name = "foreign-types" +version = "0.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f6f339eb8adc052cd2ca78910fda869aefa38d22d5cb648e6485e4d3fc06f3b1" +dependencies = [ + "foreign-types-shared", +] + +[[package]] +name = "foreign-types-shared" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "00b0228411908ca8685dba7fc2cdd70ec9990a6e753e89b6ac91a84c40fbaf4b" + +[[package]] +name = "form_urlencoded" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cb4cb245038516f5f85277875cdaa4f7d2c9a0fa0468de06ed190163b1581fcf" +dependencies = [ + "percent-encoding", +] + +[[package]] +name = "fs_extra" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "42703706b716c37f96a77aea830392ad231f44c9e9a67872fa5548707e11b11c" + +[[package]] +name = "futures-channel" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1f9e3d69d39e4862ffed03ed071a76f9a13ba1d9109d355b0f0aa6b15e393c4" +dependencies = [ + "futures-core", + "futures-sink", +] + +[[package]] +name = "futures-core" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92d699e522242e69e3003b94ecc1f960f3a5e015aa7c5d7486e65ad01dd94f5e" + +[[package]] +name = "futures-io" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53c0fa8157de1303bfffdaa1cc2a673bfffb60102f76b0ef4441659124373fed" + +[[package]] +name = "futures-sink" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1944426bf7d03f1d14f708785e4b33efd750b36d48a157b836b3efc15ede8e1d" + +[[package]] +name = "futures-task" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cd417de3d1d015fc3bfd2b1ea46dfc7bab72ef86f1cc7cc9c78e728b34a6d1fd" + +[[package]] +name = "futures-util" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0d50a92467f8ba5dd6e3ee5d4bd04d73ab2e4e1c44474a0674821dfce14b79bc" +dependencies = [ + "futures-core", + "futures-io", + "futures-sink", + "futures-task", + "memchr", + "pin-project-lite", + "slab", +] + +[[package]] +name = "getrandom" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "wasi", + "wasm-bindgen", +] + +[[package]] +name = "getrandom" +version = "0.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "300e883d756b2e4ec94e02791f39b04b522276138852cfc41d9fb7e904106099" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "r-efi", + "rand_core", + "wasm-bindgen", +] + +[[package]] +name = "gimli" +version = "0.32.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e629b9b98ef3dd8afe6ca2bd0f89306cec16d43d907889945bc5d6687f2f13c7" + +[[package]] +name = "git-version" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1ad568aa3db0fcbc81f2f116137f263d7304f512a1209b35b85150d3ef88ad19" +dependencies = [ + "git-version-macro", +] + +[[package]] +name = "git-version-macro" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53010ccb100b96a67bc32c0175f0ed1426b31b655d562898e57325f81c023ac0" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "hashbrown" +version = "0.17.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" + +[[package]] +name = "heck" +version = "0.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea" + +[[package]] +name = "http" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "918d3568bebf352712bc2ef3d46a8bcf1a75b373be6539de198e9105cbbf9ce0" +dependencies = [ + "bytes", + "itoa", +] + +[[package]] +name = "http-body" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ca2a8f2913ee65f60facd6a5905613afaa448497a0230cc41ce022d93290bc2c" +dependencies = [ + "bytes", + "http", +] + +[[package]] +name = "http-body-util" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "23169fe34a5fbcdd3f3862e78fb9b6fccd5f02a6dc6f732547005d45631ce71c" +dependencies = [ + "bytes", + "futures-core", + "http", + "http-body", + "pin-project-lite", +] + +[[package]] +name = "httparse" +version = "1.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6dbf3de79e51f3d586ab4cb9d5c3e2c14aa28ed23d180cf89b4df0454a69cc87" + +[[package]] +name = "hyper" +version = "1.11.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d22053281f852e11534f5198498373cbb59295120a20771d90f7ed1897490a72" +dependencies = [ + "atomic-waker", + "bytes", + "futures-channel", + "futures-core", + "http", + "http-body", + "httparse", + "itoa", + "pin-project-lite", + "smallvec", + "tokio", + "want", +] + +[[package]] +name = "hyper-rustls" +version = "0.27.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "33ca68d021ef39cf6463ab54c1d0f5daf03377b70561305bb89a8f83aab66e0f" +dependencies = [ + "http", + "hyper", + "hyper-util", + "rustls", + "tokio", + "tokio-rustls", + "tower-service", +] + +[[package]] +name = "hyper-tls" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "70206fc6890eaca9fde8a0bf71caa2ddfc9fe045ac9e5c70df101a7dbde866e0" +dependencies = [ + "bytes", + "http-body-util", + "hyper", + "hyper-util", + "native-tls", + "tokio", + "tokio-native-tls", + "tower-service", +] + +[[package]] +name = "hyper-util" +version = "0.1.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "96547c2556ec9d12fb1578c4eaf448b04993e7fb79cbaad930a656880a6bdfa0" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-util", + "http", + "http-body", + "hyper", + "ipnet", + "libc", + "percent-encoding", + "pin-project-lite", + "socket2", + "tokio", + "tower-service", + "tracing", +] + +[[package]] +name = "icu_collections" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4c6b649701667bbe825c3b7e6388cb521c23d88644678e83c0c4d0a621a34b43" +dependencies = [ + "displaydoc", + "potential_utf", + "yoke", + "zerofrom", + "zerovec", +] + +[[package]] +name = "icu_locale_core" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "edba7861004dd3714265b4db54a3c390e880ab658fec5f7db895fae2046b5bb6" +dependencies = [ + "displaydoc", + "litemap", + "tinystr", + "writeable", + "zerovec", +] + +[[package]] +name = "icu_normalizer" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f6c8828b67bf8908d82127b2054ea1b4427ff0230ee9141c54251934ab1b599" +dependencies = [ + "icu_collections", + "icu_normalizer_data", + "icu_properties", + "icu_provider", + "smallvec", + "zerovec", +] + +[[package]] +name = "icu_normalizer_data" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7aedcccd01fc5fe81e6b489c15b247b8b0690feb23304303a9e560f37efc560a" + +[[package]] +name = "icu_properties" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "020bfc02fe870ec3a66d93e677ccca0562506e5872c650f893269e08615d74ec" +dependencies = [ + "icu_collections", + "icu_locale_core", + "icu_properties_data", + "icu_provider", + "zerotrie", + "zerovec", +] + +[[package]] +name = "icu_properties_data" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "616c294cf8d725c6afcd8f55abc17c56464ef6211f9ed59cccffe534129c77af" + +[[package]] +name = "icu_provider" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "85962cf0ce02e1e0a629cc34e7ca3e373ce20dda4c4d7294bbd0bf1fdb59e614" +dependencies = [ + "displaydoc", + "icu_locale_core", + "writeable", + "yoke", + "zerofrom", + "zerotrie", + "zerovec", +] + +[[package]] +name = "idna" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b0875f23caa03898994f6ddc501886a45c7d3d62d04d2d90788d47be1b1e4de" +dependencies = [ + "idna_adapter", + "smallvec", + "utf8_iter", +] + +[[package]] +name = "idna_adapter" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3acae9609540aa318d1bc588455225fb2085b9ed0c4f6bd0d9d5bcd86f1a0344" +dependencies = [ + "icu_normalizer", + "icu_properties", +] + +[[package]] +name = "indexmap" +version = "2.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" +dependencies = [ + "equivalent", + "hashbrown", +] + +[[package]] +name = "ipnet" +version = "2.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6a756c3fac73139e83f14c2d742155dd2b78d3ee56597b419a0579b7bdd6dd78" + +[[package]] +name = "is_ci" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7655c9839580ee829dfacba1d1278c2b7883e50a277ff7541299489d6bdfdc45" + +[[package]] +name = "is_terminal_polyfill" +version = "1.70.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695" + +[[package]] +name = "itoa" +version = "1.0.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" + +[[package]] +name = "jni" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5efd9a482cf3a427f00d6b35f14332adc7902ce91efb778580e180ff90fa3498" +dependencies = [ + "cfg-if", + "combine", + "jni-macros", + "jni-sys", + "log", + "simd_cesu8", + "thiserror", + "walkdir", + "windows-link", +] + +[[package]] +name = "jni-macros" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a00109accc170f0bdb141fed3e393c565b6f5e072365c3bd58f5b062591560a3" +dependencies = [ + "proc-macro2", + "quote", + "rustc_version", + "simd_cesu8", + "syn 2.0.119", +] + +[[package]] +name = "jni-sys" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6377a88cb3910bee9b0fa88d4f42e1d2da8e79915598f65fb0c7ee14c878af2" +dependencies = [ + "jni-sys-macros", +] + +[[package]] +name = "jni-sys-macros" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "38c0b942f458fe50cdac086d2f946512305e5631e720728f2a61aabcd47a6264" +dependencies = [ + "quote", + "syn 2.0.119", +] + +[[package]] +name = "jobserver" +version = "0.1.35" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1c00acbd29eabad4a2392fa0e921c874934dbbf4194312ad20f04a0ed67a3cb3" +dependencies = [ + "getrandom 0.4.3", + "libc", +] + +[[package]] +name = "js-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0e0c1080212aad755ea003d18543e8768dd432c48819efd73a7bf1e39b7a5a3a" +dependencies = [ + "cfg-if", + "futures-util", + "wasm-bindgen", +] + +[[package]] +name = "libc" +version = "0.2.189" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2" + +[[package]] +name = "lief" +version = "2.0.0" +dependencies = [ + "bitflags", + "cxx", + "lief-ffi", + "num-bigint", + "num-derive", + "num-traits", + "tempfile", +] + +[[package]] +name = "lief-build" +version = "2.0.0" +dependencies = [ + "git-version", + "miette", + "reqwest", + "semver", + "zip", +] + +[[package]] +name = "lief-ffi" +version = "2.0.0" +dependencies = [ + "cxx", + "lief-build", + "miette", +] + +[[package]] +name = "lief-ffigen" +version = "2.0.0" +dependencies = [ + "clap", + "cxx-gen", + "miette", + "proc-macro2", + "serde", + "thiserror", +] + +[[package]] +name = "link-cplusplus" +version = "1.0.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7f78c730aaa7d0b9336a299029ea49f9ee53b0ed06e9202e8cb7db9bae7b8c82" +dependencies = [ + "cc", +] + +[[package]] +name = "linux-raw-sys" +version = "0.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53" + +[[package]] +name = "litemap" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "47d9d19d1d6efa0109d2f65ff4c85cddd50bd572e5a00127ab10987290bcefae" + +[[package]] +name = "log" +version = "0.4.33" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ceec5bc11778974d1bcb055b18002eba7f4b3518b6a0081b3af5f21666da9ad" + +[[package]] +name = "lru-slab" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "112b39cec0b298b6c1999fee3e31427f74f676e4cb9879ed1a121b43661a4154" + +[[package]] +name = "memchr" +version = "2.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf8baf1c55e62ffcace7a9f06f4bd9cd3f0c4beb022d3b367256b91b87513d98" + +[[package]] +name = "miette" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f98efec8807c63c752b5bd61f862c165c115b0a35685bdcfd9238c7aeb592b7" +dependencies = [ + "backtrace", + "backtrace-ext", + "cfg-if", + "miette-derive", + "owo-colors", + "supports-color", + "supports-hyperlinks", + "supports-unicode", + "terminal_size", + "textwrap", + "unicode-width 0.1.14", +] + +[[package]] +name = "miette-derive" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db5b29714e950dbb20d5e6f74f9dcec4edbcc1067bb7f8ed198c097b8c1a818b" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "miniz_oxide" +version = "0.8.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316" +dependencies = [ + "adler2", + "simd-adler32", +] + +[[package]] +name = "mio" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "30d65c71f1ce40ab09135ce117d742b9f8a19ff91a41a8b57ed50bc2de59c427" +dependencies = [ + "libc", + "wasi", + "windows-sys 0.61.2", +] + +[[package]] +name = "native-tls" +version = "0.2.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "465500e14ea162429d264d44189adc38b199b62b1c21eea9f69e4b73cb03bbf2" +dependencies = [ + "libc", + "log", + "openssl", + "openssl-probe", + "openssl-sys", + "schannel", + "security-framework", + "security-framework-sys", + "tempfile", +] + +[[package]] +name = "num-bigint" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93e7820bc0a80a0238e650327316f929ba18d5be054b647490a3a6a339f3e7c0" +dependencies = [ + "num-integer", + "num-traits", +] + +[[package]] +name = "num-conv" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9" + +[[package]] +name = "num-derive" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e4e98dc3b890f6c23a0f9d3d491a2823d0dea0fa656302a13dd225fa924112a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "num-integer" +version = "0.1.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ce2d95d4b3734dc35aa2f45e1aa22cd416814592a4f9d9205e11affd5b8e10b" +dependencies = [ + "num-traits", +] + +[[package]] +name = "num-traits" +version = "0.2.19" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" +dependencies = [ + "autocfg", +] + +[[package]] +name = "object" +version = "0.37.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe" +dependencies = [ + "memchr", +] + +[[package]] +name = "once_cell" +version = "1.21.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" + +[[package]] +name = "once_cell_polyfill" +version = "1.70.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe" + +[[package]] +name = "openssl" +version = "0.10.81" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77823a27f0babb03091cb9ed9ef80af3b39dbc82f97e8fa530374b7dafd87a45" +dependencies = [ + "bitflags", + "cfg-if", + "foreign-types", + "libc", + "openssl-macros", + "openssl-sys", +] + +[[package]] +name = "openssl-macros" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a948666b637a0f465e8564c73e89d4dde00d72d4d473cc972f390fc3dcee7d9c" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "openssl-probe" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7c87def4c32ab89d880effc9e097653c8da5d6ef28e6b539d313baaacfbafcbe" + +[[package]] +name = "openssl-sys" +version = "0.9.117" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b47e7e6bb2c38cd930d25a23b40fa52e068c10e85f3e03a7f5ba5aaca5713695" +dependencies = [ + "cc", + "libc", + "pkg-config", + "vcpkg", +] + +[[package]] +name = "owo-colors" +version = "4.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d211803b9b6b570f68772237e415a029d5a50c65d382910b879fb19d3271f94d" + +[[package]] +name = "percent-encoding" +version = "2.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220" + +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" + +[[package]] +name = "pkg-config" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f6b464fbc74e149a392436b17d523f769e057cb6877f6a5c4618bc6f11800548" + +[[package]] +name = "potential_utf" +version = "0.1.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d83eb9bc6d8e5cf568e7a1101d60ee05e81ed50ea106026f3d18deeb046d7661" +dependencies = [ + "zerovec", +] + +[[package]] +name = "powerfmt" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "439ee305def115ba05938db6eb1644ff94165c5ab5e9420d1c1bcedbba909391" + +[[package]] +name = "proc-macro2" +version = "1.0.107" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "985e7ec9bb745e6ce6535b544d84d6cd6f7ad8bd711c398938ae983b91a766d9" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "quinn" +version = "0.11.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c1a41e437b6bbd489372cd4971de128e85c855f56c57f283d20ff016cf7c0a8" +dependencies = [ + "bytes", + "cfg_aliases", + "pin-project-lite", + "quinn-proto", + "quinn-udp", + "rustc-hash", + "rustls", + "socket2", + "thiserror", + "tokio", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-proto" +version = "0.11.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "04759210543be93709136e28212294a659ef5001836ff4eab4d663e4529bba83" +dependencies = [ + "aws-lc-rs", + "bytes", + "getrandom 0.4.3", + "lru-slab", + "rand", + "rand_pcg", + "ring", + "rustc-hash", + "rustls", + "rustls-pki-types", + "slab", + "thiserror", + "tinyvec", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-udp" +version = "0.5.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "35a133f956daabe89a61a685c2649f13d82d5aa4bd5d12d1277e1072a21c0694" +dependencies = [ + "cfg_aliases", + "libc", + "once_cell", + "socket2", + "tracing", + "windows-sys 0.61.2", +] + +[[package]] +name = "quote" +version = "1.0.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fbf4db142a473a8d80c26bbf18454ed458bf8d26c8219c331daecfdbd079001" +dependencies = [ + "proc-macro2", +] + +[[package]] +name = "r-efi" +version = "6.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf" + +[[package]] +name = "rand" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c7f5fa3a058cd35567ef9bfa5e75732bee0f9e4c55fa90477bef2dfcdbc4be80" +dependencies = [ + "chacha20", + "getrandom 0.4.3", + "rand_core", +] + +[[package]] +name = "rand_core" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63b8176103e19a2643978565ca18b50549f6101881c443590420e4dc998a3c69" + +[[package]] +name = "rand_pcg" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "caa0f4137e1c0a72f4c651489402276c8e8e1cf081f3b0ba156d2cbeef09e86a" +dependencies = [ + "rand_core", +] + +[[package]] +name = "reqwest" +version = "0.13.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "219c5811de6525e5416c7d5d53bb656d3afdbc6c5af816e0802bcfa42dbdc1c3" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-core", + "futures-util", + "http", + "http-body", + "http-body-util", + "hyper", + "hyper-rustls", + "hyper-tls", + "hyper-util", + "js-sys", + "log", + "native-tls", + "percent-encoding", + "pin-project-lite", + "quinn", + "rustls", + "rustls-pki-types", + "rustls-platform-verifier", + "sync_wrapper", + "tokio", + "tokio-native-tls", + "tokio-rustls", + "tower", + "tower-http", + "tower-service", + "url", + "wasm-bindgen", + "wasm-bindgen-futures", + "web-sys", +] + +[[package]] +name = "ring" +version = "0.17.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7" +dependencies = [ + "cc", + "cfg-if", + "getrandom 0.2.17", + "libc", + "untrusted", + "windows-sys 0.52.0", +] + +[[package]] +name = "rustc-demangle" +version = "0.1.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b74b56ffa8bb2830709a538c2cbcae9aa062db0d2a42563bfb09bdaae44020eb" + +[[package]] +name = "rustc-hash" +version = "2.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b1e7f9a428571be2dc5bc0505c13fb6bf936822b894ec87abf8a08a4e51742d" + +[[package]] +name = "rustc_version" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cfcb3a22ef46e85b45de6ee7e79d063319ebb6594faafcf1c225ea92ab6e9b92" +dependencies = [ + "semver", +] + +[[package]] +name = "rustix" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190" +dependencies = [ + "bitflags", + "errno", + "libc", + "linux-raw-sys", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls" +version = "0.23.43" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0283386ce02abc0151e1761d08802dfe86c173b0b494af5cbc086574e453da06" +dependencies = [ + "aws-lc-rs", + "once_cell", + "rustls-pki-types", + "rustls-webpki", + "subtle", + "zeroize", +] + +[[package]] +name = "rustls-native-certs" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dab5152771c58876a2146916e53e35057e1a4dfa2b9df0f0305b07f611fdea4d" +dependencies = [ + "openssl-probe", + "rustls-pki-types", + "schannel", + "security-framework", +] + +[[package]] +name = "rustls-pki-types" +version = "1.15.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2f4925028c7eb5d1fcdaf196971378ed9d2c1c4efc7dc5d011256f76c99c0a96" +dependencies = [ + "web-time", + "zeroize", +] + +[[package]] +name = "rustls-platform-verifier" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "26d1e2536ce4f35f4846aa13bff16bd0ff40157cdb14cc056c7b14ba41233ba0" +dependencies = [ + "core-foundation", + "core-foundation-sys", + "jni", + "log", + "once_cell", + "rustls", + "rustls-native-certs", + "rustls-platform-verifier-android", + "rustls-webpki", + "security-framework", + "security-framework-sys", + "webpki-root-certs", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls-platform-verifier-android" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f87165f0995f63a9fbeea62b64d10b4d9d8e78ec6d7d51fb2125fda7bb36788f" + +[[package]] +name = "rustls-webpki" +version = "0.103.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0527518605e68109d875e248ea259b6758801cf165e4b2c2733ae3b51f12535a" +dependencies = [ + "aws-lc-rs", + "ring", + "rustls-pki-types", + "untrusted", +] + +[[package]] +name = "rustversion" +version = "1.0.23" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf54715a573b99ac80df0bc206da022bcd442c974952c7b9720069370852e21f" + +[[package]] +name = "same-file" +version = "1.0.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "schannel" +version = "0.1.29" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "91c1b7e4904c873ef0710c1f407dde2e6287de2bebc1bbbf7d430bb7cbffd939" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "scratch" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d68f2ec51b097e4c1a75b681a8bec621909b5e91f15bb7b840c4f2f7b01148b2" + +[[package]] +name = "security-framework" +version = "3.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7f4bc775c73d9a02cde8bf7b2ec4c9d12743edf609006c7facc23998404cd1d" +dependencies = [ + "bitflags", + "core-foundation", + "core-foundation-sys", + "libc", + "security-framework-sys", +] + +[[package]] +name = "security-framework-sys" +version = "2.17.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2691df843ecc5d231c0b14ece2acc3efb62c0a398c7e1d875f3983ce020e3" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "semver" +version = "1.0.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd" + +[[package]] +name = "serde" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4148590afebada386688f18773da617792bf2ef03ffc1e4cbd2b1d45b023e0ba" +dependencies = [ + "serde_core", + "serde_derive", +] + +[[package]] +name = "serde_core" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67dca2c9c51e58a4791a4b1ed58308b39c64224d349a935ab5039aa360942a48" +dependencies = [ + "serde_derive", +] + +[[package]] +name = "serde_derive" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e7a5d71263a5a7d47b41f6b3f06ba276f10cc18b0931f1799f710578e2309348" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "shlex" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8fadd59c855ef2080decdef8ff161eb6661b86933c9d82e5ba29dc602a55aba" + +[[package]] +name = "simd-adler32" +version = "0.3.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3a219298ac11a56ea9a6d2120044824d6f01aeb034955e7af7bc16858527deea" + +[[package]] +name = "simd_cesu8" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11031e251abf8611c80f460e19dbdeb54a66db918e49c65a7065b46ac7aec520" +dependencies = [ + "rustc_version", + "simdutf8", +] + +[[package]] +name = "simdutf8" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3a9fe34e3e7a50316060351f37187a3f546bce95496156754b601a5fa71b76e" + +[[package]] +name = "slab" +version = "0.4.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5" + +[[package]] +name = "smallvec" +version = "1.15.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ed6a63f02c8539c91a8685a86f4099661ba3da017932f6ebbea6de3f0fa7c90" + +[[package]] +name = "socket2" +version = "0.6.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c3d1e2c7f27f8d4cb10542a02c49005dbd6e93095799d6f3be745fae9f8fedd4" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "stable_deref_trait" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596" + +[[package]] +name = "strsim" +version = "0.11.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" + +[[package]] +name = "subtle" +version = "2.6.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292" + +[[package]] +name = "supports-color" +version = "3.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c64fc7232dd8d2e4ac5ce4ef302b1d81e0b80d055b9d77c7c4f51f6aa4c867d6" +dependencies = [ + "is_ci", +] + +[[package]] +name = "supports-hyperlinks" +version = "3.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e396b6523b11ccb83120b115a0b7366de372751aa6edf19844dfb13a6af97e91" + +[[package]] +name = "supports-unicode" +version = "3.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7401a30af6cb5818bb64852270bb722533397edcfc7344954a38f420819ece2" + +[[package]] +name = "syn" +version = "2.0.119" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "872831b642d1a07999a962a351ed35b955ea2cfc8f3862091e2a240a84f17297" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "syn" +version = "3.0.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53e9bae58849f64dfa4f5d5ae372c8341f7305f82a3868709269343628b659a3" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "sync_wrapper" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0bf256ce5efdfa370213c1dabab5935a12e49f2c58d15e9eac2870d3b4f27263" +dependencies = [ + "futures-core", +] + +[[package]] +name = "synstructure" +version = "0.13.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "728a70f3dbaf5bab7f0c4b1ac8d7ae5ea60a4b5549c8a5914361c99147a709d2" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "tempfile" +version = "3.27.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32497e9a4c7b38532efcdebeef879707aa9f794296a4f0244f6f69e9bc8574bd" +dependencies = [ + "fastrand", + "getrandom 0.4.3", + "once_cell", + "rustix", + "windows-sys 0.61.2", +] + +[[package]] +name = "termcolor" +version = "1.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "06794f8f6c5c898b3275aebefa6b8a1cb24cd2c6c79397ab15774837a0bc5755" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "terminal_size" +version = "0.4.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "230a1b821ccbd75b185820a1f1ff7b14d21da1e442e22c0863ea5f08771a8874" +dependencies = [ + "rustix", + "windows-sys 0.61.2", +] + +[[package]] +name = "textwrap" +version = "0.16.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c13547615a44dc9c452a8a534638acdf07120d4b6847c8178705da06306a3057" +dependencies = [ + "unicode-linebreak", + "unicode-width 0.2.2", +] + +[[package]] +name = "thiserror" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ec86235f5fcc2a73650310756d2ac5b138a5780bbbdfae3eeccec992c435ba4f" +dependencies = [ + "thiserror-impl", +] + +[[package]] +name = "thiserror-impl" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bc04cd3e1236dd4a98afca4569f2deb3f120e5422a4023be2cb683f8486292af" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "time" +version = "0.3.45" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f9e442fc33d7fdb45aa9bfeb312c095964abdf596f7567261062b2a7107aaabd" +dependencies = [ + "deranged", + "js-sys", + "num-conv", + "powerfmt", + "serde_core", + "time-core", +] + +[[package]] +name = "time-core" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b36ee98fd31ec7426d599183e8fe26932a8dc1fb76ddb6214d05493377d34ca" + +[[package]] +name = "tinystr" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1e27c91459209c2986af3dcf603a5a74a4368754ce37414f59acc971167f643" +dependencies = [ + "displaydoc", + "zerovec", +] + +[[package]] +name = "tinyvec" +version = "1.12.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb4ebadaa0af04fab11ae01eb5f9fdb5f9c5b875506e210e71c07873528baa7f" +dependencies = [ + "tinyvec_macros", +] + +[[package]] +name = "tinyvec_macros" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1f3ccbac311fea05f86f61904b462b55fb3df8837a366dfc601a0161d0532f20" + +[[package]] +name = "tokio" +version = "1.53.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "202caea871b69668250d242070849eb495be178ed697a3e98aebce5bc81a0bed" +dependencies = [ + "bytes", + "libc", + "mio", + "pin-project-lite", + "socket2", + "windows-sys 0.61.2", +] + +[[package]] +name = "tokio-native-tls" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bbae76ab933c85776efabc971569dd6119c580d8f5d448769dec1764bf796ef2" +dependencies = [ + "native-tls", + "tokio", +] + +[[package]] +name = "tokio-rustls" +version = "0.26.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1729aa945f29d91ba541258c8df89027d5792d85a8841fb65e8bf0f4ede4ef61" +dependencies = [ + "rustls", + "tokio", +] + +[[package]] +name = "tower" +version = "0.5.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ebe5ef63511595f1344e2d5cfa636d973292adc0eec1f0ad45fae9f0851ab1d4" +dependencies = [ + "futures-core", + "futures-util", + "pin-project-lite", + "sync_wrapper", + "tokio", + "tower-layer", + "tower-service", +] + +[[package]] +name = "tower-http" +version = "0.6.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4cfcf7e2740e6fc6d4d688b4ef00650406bb94adf4731e43c096c3a19fe40840" +dependencies = [ + "bitflags", + "bytes", + "futures-util", + "http", + "http-body", + "pin-project-lite", + "tower", + "tower-layer", + "tower-service", + "url", +] + +[[package]] +name = "tower-layer" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "121c2a6cda46980bb0fcd1647ffaf6cd3fc79a013de288782836f6df9c48780e" + +[[package]] +name = "tower-service" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8df9b6e13f2d32c91b9bd719c00d1958837bc7dec474d94952798cc8e69eeec3" + +[[package]] +name = "tracing" +version = "0.1.44" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63e71662fa4b2a2c3a26f570f037eb95bb1f85397f3cd8076caed2f026a6d100" +dependencies = [ + "pin-project-lite", + "tracing-core", +] + +[[package]] +name = "tracing-core" +version = "0.1.36" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db97caf9d906fbde555dd62fa95ddba9eecfd14cb388e4f491a66d74cd5fb79a" +dependencies = [ + "once_cell", +] + +[[package]] +name = "try-lock" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e421abadd41a4225275504ea4d6566923418b7f05506fbc9c0fe86ba7396114b" + +[[package]] +name = "typed-path" +version = "0.12.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e28f89b80c87b8fb0cf04ab448d5dd0dd0ade2f8891bae878de66a75a28600e" + +[[package]] +name = "unicode-ident" +version = "1.0.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" + +[[package]] +name = "unicode-linebreak" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b09c83c3c29d37506a3e260c08c03743a6bb66a9cd432c6934ab501a190571f" + +[[package]] +name = "unicode-width" +version = "0.1.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af" + +[[package]] +name = "unicode-width" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b4ac048d71ede7ee76d585517add45da530660ef4390e49b098733c6e897f254" + +[[package]] +name = "untrusted" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1" + +[[package]] +name = "url" +version = "2.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff67a8a4397373c3ef660812acab3268222035010ab8680ec4215f38ba3d0eed" +dependencies = [ + "form_urlencoded", + "idna", + "percent-encoding", + "serde", +] + +[[package]] +name = "utf8_iter" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be" + +[[package]] +name = "utf8parse" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821" + +[[package]] +name = "vcpkg" +version = "0.2.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "accd4ea62f7bb7a82fe23066fb0957d48ef677f6eeb8215f372f52e48bb32426" + +[[package]] +name = "walkdir" +version = "2.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "29790946404f91d9c5d06f9874efddea1dc06c5efe94541a7d6863108e3a5e4b" +dependencies = [ + "same-file", + "winapi-util", +] + +[[package]] +name = "want" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bfa7760aed19e106de2c7c0b581b509f2f25d3dacaf737cb82ac61bc6d760b0e" +dependencies = [ + "try-lock", +] + +[[package]] +name = "wasi" +version = "0.11.1+wasi-snapshot-preview1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" + +[[package]] +name = "wasm-bindgen" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b70935747edd64d89de3efa29d73789b806c15798f8e7dca4d8ac356b50ce70" +dependencies = [ + "cfg-if", + "once_cell", + "rustversion", + "wasm-bindgen-macro", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-futures" +version = "0.4.77" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b7777d5cc23d0e91404e53ce2d5e8ec7acae3026b16233dba62cd3246457950" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "wasm-bindgen-macro" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77775f8f3f7217702089053b94958f8f54061a3f663417df76e19cbdcca29bc1" +dependencies = [ + "quote", + "wasm-bindgen-macro-support", +] + +[[package]] +name = "wasm-bindgen-macro-support" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e11d33f857dc2fb11b8bc75aee111aa9cbeb12cd9f25efd3d4c2a3dd4e235284" +dependencies = [ + "bumpalo", + "proc-macro2", + "quote", + "syn 2.0.119", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-shared" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ef64dbcc55df09c7e5a46182d181c2cfa3e925f3da937ea764728b4bbb9dcbf" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "web-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c435338968042f4f59a557f690a253676d47ce13ceb55d70100e7facf6620a30" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "web-time" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5a6580f308b1fad9207618087a65c04e7a10bc77e02c8e84e9b00dd4b12fa0bb" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "webpki-root-certs" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b96554aa2acc8ccdb7e1c9a58a7a68dd5d13bccc69cd124cb09406db612a1c9b" +dependencies = [ + "rustls-pki-types", +] + +[[package]] +name = "winapi-util" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "windows-link" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" + +[[package]] +name = "windows-sys" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" +dependencies = [ + "windows-targets", +] + +[[package]] +name = "windows-sys" +version = "0.61.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc" +dependencies = [ + "windows-link", +] + +[[package]] +name = "windows-targets" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" +dependencies = [ + "windows_aarch64_gnullvm", + "windows_aarch64_msvc", + "windows_i686_gnu", + "windows_i686_gnullvm", + "windows_i686_msvc", + "windows_x86_64_gnu", + "windows_x86_64_gnullvm", + "windows_x86_64_msvc", +] + +[[package]] +name = "windows_aarch64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" + +[[package]] +name = "windows_aarch64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" + +[[package]] +name = "windows_i686_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" + +[[package]] +name = "windows_i686_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" + +[[package]] +name = "windows_i686_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66" + +[[package]] +name = "windows_x86_64_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78" + +[[package]] +name = "windows_x86_64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" + +[[package]] +name = "writeable" +version = "0.6.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ad82d2a33cdc9674dc7465672f271e096168fcdbe0f799d9e6db8c5892679dc" + +[[package]] +name = "yoke" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "709fe23a0424b6a435d82152b1bd3fdfb0833487d5fa90d05d42762a9891fef5" +dependencies = [ + "stable_deref_trait", + "yoke-derive", + "zerofrom", +] + +[[package]] +name = "yoke-derive" +version = "0.8.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "de844c262c8848816172cef550288e7dc6c7b7814b4ee56b3e1553f275f1858e" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zerofrom" +version = "0.1.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ec05a11813ea801ff6d75110ad09cd0824ddba17dfe17128ea0d5f68e6c5272" +dependencies = [ + "zerofrom-derive", +] + +[[package]] +name = "zerofrom-derive" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11532158c46691caf0f2593ea8358fed6bbf68a0315e80aae9bd41fbade684a1" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zeroize" +version = "1.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e13c156562582aa81c60cb29407084cdb54c4164760106ab78e6c5b0858cf64e" + +[[package]] +name = "zerotrie" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4ea269c3bd32f0a32c321907a2ae912ba6f4649bb0fc764a15627e99a7095a3f" +dependencies = [ + "displaydoc", + "yoke", + "zerofrom", +] + +[[package]] +name = "zerovec" +version = "0.11.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb0464e17806c1d976d5cba29399c7f08e516e279e2ba493f63123b5fca67dd8" +dependencies = [ + "yoke", + "zerofrom", + "zerovec-derive", +] + +[[package]] +name = "zerovec-derive" +version = "0.11.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f212a141d820099d57ffafb9569be9617a6f27d3dc881fbee8fb56642f917a9" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "zip" +version = "7.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c42e33efc22a0650c311c2ef19115ce232583abbe80850bc8b66509ebef02de0" +dependencies = [ + "crc32fast", + "flate2", + "indexmap", + "memchr", + "time", + "typed-path", + "zopfli", +] + +[[package]] +name = "zlib-rs" +version = "0.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "34b31d188d9d685a4f9c7b46d6e36631b07058d2cfe190267adce54dc230bf12" + +[[package]] +name = "zopfli" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f05cd8797d63865425ff89b5c4a48804f35ba0ce8d125800027ad6017d2b5249" +dependencies = [ + "bumpalo", + "crc32fast", + "log", + "simd-adler32", +] diff --git a/vendor/lief/api/rust/crates/Cargo.toml b/vendor/lief/api/rust/crates/Cargo.toml new file mode 100644 index 0000000..6b8258c --- /dev/null +++ b/vendor/lief/api/rust/crates/Cargo.toml @@ -0,0 +1,53 @@ +[workspace.package] +authors = ["Romain Thomas "] +license = "Apache-2.0" +description = "Official Rust bindings for LIEF." +readme = "README.md" +version = "2.0.0" +edition = "2024" +homepage = "https://lief.re" +keywords = ["ELF", "PE", "Mach-O", "reverse-engineering"] +repository = "https://github.com/lief-project/LIEF" +categories = [ + "api-bindings", + "development-tools::debugging", + "development-tools::profiling", + "development-tools::build-utils", + "parsing" +] + +rust-version = "1.85.0" + +[workspace] +members = [ + "lief-ffi", + "lief", + "lief-build", + "lief-ffigen", +] +default-members = [ + "lief", +] +resolver = "3" + +[workspace.dependencies] +bitflags = "2.13.0" +clap = { version = "4.6.1", features = ["derive"] } +cxx = { version = "=1.0.198", features = ["c++17"] } +cxx-gen = "=0.7.198" +git-version = "0.3.9" +miette = { version = "7.6.0", features = ["fancy"] } +num-bigint = "0.5.1" +num-derive = "0.5.1" +num-traits = "0.2.19" +proc-macro2 = "1.0.106" +reqwest = { version = "0.13.3", default-features = false, features = ["blocking"] } +semver = "1.0.28" +serde = "1.0.228" +tempfile = "3.27.0" +thiserror = "2.0.18" +zip = { version = "7.2.0", default-features = false, features = ["deflate", "time"] } + +lief = { version = "2.0.0", path = "lief" } +lief-ffi = { version = "2.0.0", path = "lief-ffi" } +lief-build = { version = "2.0.0", path = "lief-build" } diff --git a/vendor/lief/api/rust/crates/README.md b/vendor/lief/api/rust/crates/README.md new file mode 100644 index 0000000..1e67c03 --- /dev/null +++ b/vendor/lief/api/rust/crates/README.md @@ -0,0 +1,40 @@ +# LIEF Rust Bindings + +These are the official Rust bindings for LIEF. + +![LIEF Architecture](https://raw.githubusercontent.com/lief-project/LIEF/main/.github/images/architecture.png) + +## Getting Started + +```toml +[dependencies] +lief = "1.0.0" +``` + +The bindings require Rust edition 2024 and `rustc >= 1.85.0` + +```rust +use lief; + +if let Some(lief::Binary::ELF(elf)) = lief::Binary::from(&mut file) { + println!("Dependencies:"); + for entry in elf.dynamic_entries() { + if let dynamic::Entries::Library(lib) = entry { + println!(" - {}", lib.name()); + } + } + println!("Versions:"); + for version in elf.symbols_version_requirement() { + println!(" From {}", version.name()); + for aux in version.auxiliary_symbols() { + println!(" - {}", aux.name()); + } + } +} +``` + + +## Documentation + +- Rust API: https://lief.re/doc/stable/rust/lief/ +- Bootstrapping and tweaks: https://lief.re/doc/latest/api/rust/index.html diff --git a/vendor/lief/api/rust/crates/lief-build/Cargo.toml b/vendor/lief/api/rust/crates/lief-build/Cargo.toml new file mode 100644 index 0000000..93c996a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-build/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "lief-build" +description = "Build helper for the Rust bindings of LIEF" +edition.workspace = true +version.workspace = true +authors.workspace = true +license.workspace = true +rust-version.workspace = true + +[dependencies] +miette = { workspace = true } +reqwest = { workspace = true } +zip = { workspace = true } +git-version = { workspace = true } +semver = { workspace = true } + +[features] +default = ["rustls-tls"] +rustls-tls = ["reqwest/rustls"] +native-tls = ["reqwest/native-tls"] diff --git a/vendor/lief/api/rust/crates/lief-build/src/lib.rs b/vendor/lief/api/rust/crates/lief-build/src/lib.rs new file mode 100644 index 0000000..0cb2ec2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-build/src/lib.rs @@ -0,0 +1,220 @@ +use git_version::git_version; +use miette::IntoDiagnostic; +use semver::Version; +use std::env; +use std::path::{Path, PathBuf}; + +const GIT_VERSION: &str = git_version!( + args = ["--tags", "--long", "--dirty"], + prefix = "git:", + cargo_prefix = "cargo:", + fallback = "latest" +); + +const GH_URL: &str = "https://github.com/lief-project/LIEF/releases/download"; +const DEFAULT_S3_URL: &str = "https://lief-rs.s3.fr-par.scw.cloud"; + +const SUPPORTED_TARGETS: &[&str; 16] = &[ + "aarch64-apple-darwin", + "aarch64-apple-ios", + "aarch64-linux-android", + "aarch64-pc-windows-msvc", + "aarch64-unknown-linux-gnu", + "aarch64-unknown-linux-musl", + "armv7-linux-androideabi", + "i686-unknown-linux-gnu", + "i686-unknown-linux-musl", + "riscv64a23-unknown-linux-gnu", + "riscv64gc-unknown-linux-musl", + "x86_64-apple-darwin", + "x86_64-linux-android", + "x86_64-pc-windows-msvc", + "x86_64-unknown-linux-gnu", + "x86_64-unknown-linux-musl", +]; + +fn get_s3_url() -> String { + env::var("LIEF_RUST_S3_PREFIX").unwrap_or(DEFAULT_S3_URL.to_string()) +} + +fn get_target() -> String { + let current_target = env::var("TARGET").unwrap(); + let supported = SUPPORTED_TARGETS + .iter() + .find(|&supported| *supported == current_target); + if supported.is_none() { + panic!("Target: {} is not currently supported.", current_target); + } + current_target.to_string() +} + +fn get_filename(target: &String) -> String { + if let Some(crt) = get_crt_prefix() { + return format!("LIEF-rs-{}-{}.zip", crt, target); + } + format!("LIEF-rs-{}.zip", target) +} + +fn get_urls_from_cargo(target: &String, version: &str) -> Vec { + let mut urls = Vec::new(); + let s3_prefix = get_s3_url(); + let github_url = format!("{GH_URL}/{version}/{}", get_filename(target)); + let s3_url = format!("{s3_prefix}/precompiled/{version}/{}", get_filename(target)); + let s3_latest_url = format!("{s3_prefix}/precompiled/latest/{}", get_filename(target)); + urls.push(github_url); + urls.push(s3_url); + urls.push(s3_latest_url); // Fallback if it's not yet a release + urls +} + +fn get_urls_from_git(target: &String, version: &str) -> Vec { + let mut urls = Vec::new(); + let parts: Vec<&str> = version.split('-').collect(); + let cargo_version = env::var("CARGO_PKG_VERSION").unwrap(); + + if parts.is_empty() { + // Fallback on cargo version + eprintln!("Invalid Git-based version. Falling back to Cargo-based version"); + return get_urls_from_cargo(target, cargo_version.as_str()); + } + + let git_ver = parts[0]; + let sem_version = Version::parse(git_ver); + if sem_version.is_err() { + eprintln!("Invalid Git-based version. Falling back to Cargo-based version"); + return get_urls_from_cargo(target, cargo_version.as_str()); + } + + if parts.len() == 1 { + // Tagged version + println!("Using tagged version: {git_ver}"); + let s3_prefix = get_s3_url(); + let github_url = format!("{GH_URL}/{git_ver}/{}", get_filename(target)); + let s3_url = format!("{s3_prefix}/precompiled/{git_ver}/{}", get_filename(target)); + urls.push(github_url); + urls.push(s3_url); + return urls; + } + + get_nightly_url(target) +} + +fn get_nightly_url(target: &String) -> Vec { + println!("Using nightly url"); + let mut urls = Vec::new(); + let s3_prefix = get_s3_url(); + let s3_url = format!("{s3_prefix}/precompiled/latest/{}", get_filename(target)); + urls.push(s3_url); + urls +} + +fn get_cache_urls() -> Vec { + let version = String::from(GIT_VERSION); + let target = get_target(); + if version.starts_with("cargo:") { + let tag = version + .strip_prefix("cargo:") + .expect("Can't strip 'cargo:' prefix"); + return get_urls_from_cargo(&target, tag); + } + if version.starts_with("git:") { + let git_ver = version + .strip_prefix("git:") + .expect("Can't strip 'git:' prefix") + .to_string(); + return get_urls_from_git(&target, &git_ver); + } + get_nightly_url(&target) +} + +fn emit_cargo_directives(root: &Path) -> miette::Result<()> { + println!("cargo:rustc-link-search=native={}/lib", root.display()); + + println!("cargo:rustc-link-lib=lief-sys"); + println!("cargo:rustc-link-lib=LIEF"); + + let os = env::var("CARGO_CFG_TARGET_OS").expect("Can't access 'CARGO_CFG_TARGET_OS"); + if os.to_lowercase() == "windows" { + println!("cargo:rustc-link-lib=bcrypt"); + println!("cargo:rustc-link-lib=shell32"); + } + + Ok(()) +} + +fn download(dst_archive: &PathBuf) -> bool { + let urls = get_cache_urls(); + if urls.is_empty() { + panic!( + "Can't determine precompiled URL for this build.\n + Please consider opening a GitHub issue." + ); + } + for url in urls.iter() { + println!("Trying to download from {}", url); + let mut resp = reqwest::blocking::get(url).expect("failed to download LIEF cache"); + if resp.status().is_client_error() || resp.status().is_server_error() { + eprintln!("Can't download precompiled LIEF ffi bindings from: {}", url); + continue; + } + let mut out = std::fs::File::create(dst_archive).expect("failed to create zip cache file"); + std::io::copy(&mut resp, &mut out).expect("failed to copy cache content"); + return true; + } + false +} + +fn get_crt_prefix() -> Option { + let os = env::var("CARGO_CFG_TARGET_OS").expect("Can't access 'CARGO_CFG_TARGET_OS"); + if os.to_lowercase() != "windows" { + return None; + } + + let use_static_crt = { + let target_features = env::var("CARGO_CFG_TARGET_FEATURE").unwrap_or_default(); + target_features.split(',').any(|f| f == "crt-static") + }; + + if use_static_crt { + return Some("MT".to_string()); + } + + Some("MD".to_string()) +} + +fn build_from_precompiled() -> miette::Result<()> { + let target_arch = env::var("CARGO_CFG_TARGET_ARCH").unwrap(); + let target_os = env::var("CARGO_CFG_TARGET_OS").unwrap(); + let target = env::var("TARGET").unwrap(); + + println!("Target: {}", target); + println!("Arch: {}", target_arch); + println!("OS: {}", target_os); + println!("Version: {}", GIT_VERSION); + + if let Ok(var) = env::var("LIEF_RUST_PRECOMPILED") { + let root = PathBuf::from(var); + return emit_cargo_directives(&root); + } + let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap()); + let dst_dir = out_dir.join("lief-rs"); + let dst_archive = dst_dir.join("cache.zip"); + if !dst_dir.exists() { + std::fs::create_dir_all(&dst_dir).into_diagnostic()?; + } + println!("Cache dst: {}", dst_dir.display()); + + if !dst_archive.exists() && !download(&dst_archive) { + panic!("Can't download precompiled ffi package"); + } + + let cache_file = std::fs::File::open(dst_archive).into_diagnostic()?; + let mut zip = zip::ZipArchive::new(&cache_file).into_diagnostic()?; + zip.extract(&dst_dir).into_diagnostic()?; + emit_cargo_directives(&dst_dir) +} + +pub fn build() -> miette::Result<()> { + build_from_precompiled()?; + Ok(()) +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/Cargo.toml b/vendor/lief/api/rust/crates/lief-ffi/Cargo.toml new file mode 100644 index 0000000..ee82dd3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "lief-ffi" +description = "LIEF ffi" +edition.workspace = true +version.workspace = true +authors.workspace = true +license.workspace = true +rust-version.workspace = true + +[dependencies] +cxx = { workspace = true } + +[build-dependencies] +lief-build = { workspace = true } +miette = { workspace = true } + +[features] +default = ["rustls-tls"] +rustls-tls = ["lief-build/rustls-tls"] +native-tls = ["lief-build/native-tls"] diff --git a/vendor/lief/api/rust/crates/lief-ffi/build.rs b/vendor/lief/api/rust/crates/lief-ffi/build.rs new file mode 100644 index 0000000..5fefa21 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/build.rs @@ -0,0 +1,3 @@ +fn main() -> miette::Result<()> { + lief_build::build() +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm.rs new file mode 100644 index 0000000..aefb625 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm.rs @@ -0,0 +1,9 @@ +pub mod aarch64; +pub mod arm; +pub mod config; +pub mod ebpf; +pub mod instruction; +pub mod mips; +pub mod powerpc; +pub mod riscv; +pub mod x86; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/instruction.rs new file mode 100644 index 0000000..5fb9450 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/instruction.rs @@ -0,0 +1,27 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_aarch64_Operand = crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; + + type asm_aarch64_Instruction; + + #[Self = "asm_aarch64_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_aarch64_Instruction) -> u64; + fn operands( + self: &asm_aarch64_Instruction, + ) -> UniquePtr; + + type asm_aarch64_Instruction_it_operands; + + fn next( + self: Pin<&mut asm_aarch64_Instruction_it_operands>, + ) -> UniquePtr; + fn size(self: &asm_aarch64_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operand.rs new file mode 100644 index 0000000..2672ae7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/Operand.hpp"); + + type asm_aarch64_Operand; + + fn to_string(self: &asm_aarch64_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/immediate.rs new file mode 100644 index 0000000..ded3e7c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/operands/Immediate.hpp"); + + type asm_aarch64_Operand = crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; + + type asm_aarch64_operands_Immediate; + + #[Self = "asm_aarch64_operands_Immediate"] + fn classof(inst: &asm_aarch64_Operand) -> bool; + fn value(self: &asm_aarch64_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/memory.rs new file mode 100644 index 0000000..fb1c3c4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/memory.rs @@ -0,0 +1,45 @@ +#[repr(C)] +pub struct offset_t { + pub value: u64, + pub enum_type: u32, +} + +unsafe impl cxx::ExternType for offset_t { + type Id = cxx::type_id!("asm_aarch64_operands_Memory_offset_t"); + type Kind = cxx::kind::Trivial; +} + +#[repr(C)] +pub struct shift_info_t { + pub enum_type: i32, + pub value: i8, +} + +unsafe impl cxx::ExternType for shift_info_t { + type Id = cxx::type_id!("asm_aarch64_operands_Memory_shift_info_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/operands/Memory.hpp"); + + type asm_aarch64_Operand = crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; + + type asm_aarch64_operands_Memory_offset_t = crate::asm::aarch64::operands::memory::offset_t; + + type asm_aarch64_operands_Memory; + + type asm_aarch64_operands_Memory_shift_info_t = + crate::asm::aarch64::operands::memory::shift_info_t; + + #[Self = "asm_aarch64_operands_Memory"] + fn classof(inst: &asm_aarch64_Operand) -> bool; + fn base(self: &asm_aarch64_operands_Memory) -> u64; + fn offset(self: &asm_aarch64_operands_Memory) -> asm_aarch64_operands_Memory_offset_t; + fn shift(self: &asm_aarch64_operands_Memory) -> asm_aarch64_operands_Memory_shift_info_t; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/pc_relative.rs new file mode 100644 index 0000000..c5312d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/operands/PCRelative.hpp"); + + type asm_aarch64_Operand = crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; + + type asm_aarch64_operands_PCRelative; + + #[Self = "asm_aarch64_operands_PCRelative"] + fn classof(inst: &asm_aarch64_Operand) -> bool; + fn value(self: &asm_aarch64_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/register.rs new file mode 100644 index 0000000..4965c95 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/aarch64/operands/register.rs @@ -0,0 +1,28 @@ +#[repr(C)] +pub struct reg_t { + pub reg: u64, + pub enum_type: u32, +} + +unsafe impl cxx::ExternType for reg_t { + type Id = cxx::type_id!("asm_aarch64_operands_Register_reg_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/aarch64/operands/Register.hpp"); + + type asm_aarch64_Operand = crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; + + type asm_aarch64_operands_Register; + + type asm_aarch64_operands_Register_reg_t = crate::asm::aarch64::operands::register::reg_t; + + #[Self = "asm_aarch64_operands_Register"] + fn classof(inst: &asm_aarch64_Operand) -> bool; + fn value(self: &asm_aarch64_operands_Register) -> asm_aarch64_operands_Register_reg_t; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm.rs new file mode 100644 index 0000000..ca4b15f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm.rs @@ -0,0 +1 @@ +pub mod instruction; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm/instruction.rs new file mode 100644 index 0000000..67e9685 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/arm/instruction.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/arm/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + + type asm_arm_Instruction; + + #[Self = "asm_arm_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_arm_Instruction) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/config.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/config.rs new file mode 100644 index 0000000..8ea2ca2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/config.rs @@ -0,0 +1,31 @@ +#[cxx::bridge] +pub mod ffi { + extern "Rust" { + #[derive(ExternType)] + pub type AssemblerConfig_r; + fn resolve_symbol(&self, name: &str) -> i64; + } +} + +#[allow(non_camel_case_types)] +pub struct AssemblerConfig_r { + resolver: Box Option + Send + Sync + 'static>, +} + +impl AssemblerConfig_r { + pub fn new(resolver: F) -> Box + where + F: Fn(&str) -> Option + Send + Sync + 'static, + { + Box::new(Self { + resolver: Box::new(resolver), + }) + } + + fn resolve_symbol(&self, name: &str) -> i64 { + match (self.resolver)(name) { + Some(value) => value as i64, + None => -1, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/instruction.rs new file mode 100644 index 0000000..926f8d6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/instruction.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_ebpf_Operand = crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; + + type asm_ebpf_Instruction; + + #[Self = "asm_ebpf_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_ebpf_Instruction) -> u64; + fn operands(self: &asm_ebpf_Instruction) -> UniquePtr; + + type asm_ebpf_Instruction_it_operands; + + fn next(self: Pin<&mut asm_ebpf_Instruction_it_operands>) -> UniquePtr; + fn size(self: &asm_ebpf_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operand.rs new file mode 100644 index 0000000..3a5c097 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/Operand.hpp"); + + type asm_ebpf_Operand; + + fn to_string(self: &asm_ebpf_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/immediate.rs new file mode 100644 index 0000000..5b43b7e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/operands/Immediate.hpp"); + + type asm_ebpf_Operand = crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; + + type asm_ebpf_operands_Immediate; + + #[Self = "asm_ebpf_operands_Immediate"] + fn classof(inst: &asm_ebpf_Operand) -> bool; + fn value(self: &asm_ebpf_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/memory.rs new file mode 100644 index 0000000..3dfc424 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/memory.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/operands/Memory.hpp"); + + type asm_ebpf_Operand = crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; + + type asm_ebpf_operands_Memory; + + #[Self = "asm_ebpf_operands_Memory"] + fn classof(inst: &asm_ebpf_Operand) -> bool; + fn base(self: &asm_ebpf_operands_Memory) -> u64; + fn displacement(self: &asm_ebpf_operands_Memory) -> i64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/pc_relative.rs new file mode 100644 index 0000000..488e0e2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/operands/PCRelative.hpp"); + + type asm_ebpf_Operand = crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; + + type asm_ebpf_operands_PCRelative; + + #[Self = "asm_ebpf_operands_PCRelative"] + fn classof(inst: &asm_ebpf_Operand) -> bool; + fn value(self: &asm_ebpf_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/register.rs new file mode 100644 index 0000000..aa32abb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/ebpf/operands/register.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/ebpf/operands/Register.hpp"); + + type asm_ebpf_Operand = crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; + + type asm_ebpf_operands_Register; + + #[Self = "asm_ebpf_operands_Register"] + fn classof(inst: &asm_ebpf_Operand) -> bool; + fn value(self: &asm_ebpf_operands_Register) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/instruction.rs new file mode 100644 index 0000000..3c79c73 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/instruction.rs @@ -0,0 +1,37 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/Instruction.hpp"); + + type Span = crate::utils::ffi::Span; + type asm_Instruction; + + fn raw(self: &asm_Instruction) -> Span; + + fn address(self: &asm_Instruction) -> u64; + fn size(self: &asm_Instruction) -> u64; + fn mnemonic(self: &asm_Instruction) -> UniquePtr; + fn to_string(self: &asm_Instruction) -> UniquePtr; + fn to_string_no_address(self: &asm_Instruction) -> UniquePtr; + fn is_call(self: &asm_Instruction) -> bool; + fn is_terminator(self: &asm_Instruction) -> bool; + fn is_branch(self: &asm_Instruction) -> bool; + fn is_syscall(self: &asm_Instruction) -> bool; + fn is_memory_access(self: &asm_Instruction) -> bool; + fn is_move_reg(self: &asm_Instruction) -> bool; + fn is_add(self: &asm_Instruction) -> bool; + fn is_trap(self: &asm_Instruction) -> bool; + fn is_barrier(self: &asm_Instruction) -> bool; + fn is_return(self: &asm_Instruction) -> bool; + fn is_indirect_branch(self: &asm_Instruction) -> bool; + fn is_conditional_branch(self: &asm_Instruction) -> bool; + fn is_unconditional_branch(self: &asm_Instruction) -> bool; + fn is_compare(self: &asm_Instruction) -> bool; + fn is_move_immediate(self: &asm_Instruction) -> bool; + fn is_bitcast(self: &asm_Instruction) -> bool; + fn memory_access(self: &asm_Instruction) -> u64; + fn branch_target(self: &asm_Instruction, err: Pin<&mut u32>) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/instruction.rs new file mode 100644 index 0000000..bee05c7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/instruction.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_mips_Operand = crate::asm::mips::operand::ffi::asm_mips_Operand; + + type asm_mips_Instruction; + + #[Self = "asm_mips_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_mips_Instruction) -> u64; + fn operands(self: &asm_mips_Instruction) -> UniquePtr; + + type asm_mips_Instruction_it_operands; + + fn next(self: Pin<&mut asm_mips_Instruction_it_operands>) -> UniquePtr; + fn size(self: &asm_mips_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operand.rs new file mode 100644 index 0000000..a2c6f0d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/Operand.hpp"); + + type asm_mips_Operand; + + fn to_string(self: &asm_mips_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/immediate.rs new file mode 100644 index 0000000..a422d2d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/operands/Immediate.hpp"); + + type asm_mips_Operand = crate::asm::mips::operand::ffi::asm_mips_Operand; + + type asm_mips_operands_Immediate; + + #[Self = "asm_mips_operands_Immediate"] + fn classof(inst: &asm_mips_Operand) -> bool; + fn value(self: &asm_mips_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/memory.rs new file mode 100644 index 0000000..0d18be6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/memory.rs @@ -0,0 +1,30 @@ +#[repr(C)] +pub struct offset_t { + pub value: u64, + pub enum_type: u32, +} + +unsafe impl cxx::ExternType for offset_t { + type Id = cxx::type_id!("asm_mips_operands_Memory_offset_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/operands/Memory.hpp"); + + type asm_mips_Operand = crate::asm::mips::operand::ffi::asm_mips_Operand; + + type asm_mips_operands_Memory_offset_t = crate::asm::mips::operands::memory::offset_t; + + type asm_mips_operands_Memory; + + #[Self = "asm_mips_operands_Memory"] + fn classof(inst: &asm_mips_Operand) -> bool; + fn base(self: &asm_mips_operands_Memory) -> u64; + fn offset(self: &asm_mips_operands_Memory) -> asm_mips_operands_Memory_offset_t; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/pc_relative.rs new file mode 100644 index 0000000..18d967f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/operands/PCRelative.hpp"); + + type asm_mips_Operand = crate::asm::mips::operand::ffi::asm_mips_Operand; + + type asm_mips_operands_PCRelative; + + #[Self = "asm_mips_operands_PCRelative"] + fn classof(inst: &asm_mips_Operand) -> bool; + fn value(self: &asm_mips_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/register.rs new file mode 100644 index 0000000..9e9d39a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/mips/operands/register.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/mips/operands/Register.hpp"); + + type asm_mips_Operand = crate::asm::mips::operand::ffi::asm_mips_Operand; + + type asm_mips_operands_Register; + + #[Self = "asm_mips_operands_Register"] + fn classof(inst: &asm_mips_Operand) -> bool; + fn value(self: &asm_mips_operands_Register) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/instruction.rs new file mode 100644 index 0000000..cae4d0f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/instruction.rs @@ -0,0 +1,27 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_powerpc_Operand = crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; + + type asm_powerpc_Instruction; + + #[Self = "asm_powerpc_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_powerpc_Instruction) -> u64; + fn operands( + self: &asm_powerpc_Instruction, + ) -> UniquePtr; + + type asm_powerpc_Instruction_it_operands; + + fn next( + self: Pin<&mut asm_powerpc_Instruction_it_operands>, + ) -> UniquePtr; + fn size(self: &asm_powerpc_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operand.rs new file mode 100644 index 0000000..e1ea504 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/Operand.hpp"); + + type asm_powerpc_Operand; + + fn to_string(self: &asm_powerpc_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/immediate.rs new file mode 100644 index 0000000..a670ecb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/operands/Immediate.hpp"); + + type asm_powerpc_Operand = crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; + + type asm_powerpc_operands_Immediate; + + #[Self = "asm_powerpc_operands_Immediate"] + fn classof(inst: &asm_powerpc_Operand) -> bool; + fn value(self: &asm_powerpc_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/memory.rs new file mode 100644 index 0000000..deae9c1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/memory.rs @@ -0,0 +1,30 @@ +#[repr(C)] +pub struct offset_t { + pub value: u64, + pub enum_type: u32, +} + +unsafe impl cxx::ExternType for offset_t { + type Id = cxx::type_id!("asm_powerpc_operands_Memory_offset_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/operands/Memory.hpp"); + + type asm_powerpc_Operand = crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; + + type asm_powerpc_operands_Memory_offset_t = crate::asm::powerpc::operands::memory::offset_t; + + type asm_powerpc_operands_Memory; + + #[Self = "asm_powerpc_operands_Memory"] + fn classof(inst: &asm_powerpc_Operand) -> bool; + fn base(self: &asm_powerpc_operands_Memory) -> u64; + fn offset(self: &asm_powerpc_operands_Memory) -> asm_powerpc_operands_Memory_offset_t; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/pc_relative.rs new file mode 100644 index 0000000..0fa73e2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/operands/PCRelative.hpp"); + + type asm_powerpc_Operand = crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; + + type asm_powerpc_operands_PCRelative; + + #[Self = "asm_powerpc_operands_PCRelative"] + fn classof(inst: &asm_powerpc_Operand) -> bool; + fn value(self: &asm_powerpc_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/register.rs new file mode 100644 index 0000000..0921e06 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/powerpc/operands/register.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/powerpc/operands/Register.hpp"); + + type asm_powerpc_Operand = crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; + + type asm_powerpc_operands_Register; + + #[Self = "asm_powerpc_operands_Register"] + fn classof(inst: &asm_powerpc_Operand) -> bool; + fn value(self: &asm_powerpc_operands_Register) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/instruction.rs new file mode 100644 index 0000000..c61a5b6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/instruction.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_riscv_Operand = crate::asm::riscv::operand::ffi::asm_riscv_Operand; + + type asm_riscv_Instruction; + + #[Self = "asm_riscv_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_riscv_Instruction) -> u64; + fn operands(self: &asm_riscv_Instruction) -> UniquePtr; + + type asm_riscv_Instruction_it_operands; + + fn next(self: Pin<&mut asm_riscv_Instruction_it_operands>) -> UniquePtr; + fn size(self: &asm_riscv_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operand.rs new file mode 100644 index 0000000..b16634b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/Operand.hpp"); + + type asm_riscv_Operand; + + fn to_string(self: &asm_riscv_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/immediate.rs new file mode 100644 index 0000000..18fccd5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/operands/Immediate.hpp"); + + type asm_riscv_Operand = crate::asm::riscv::operand::ffi::asm_riscv_Operand; + + type asm_riscv_operands_Immediate; + + #[Self = "asm_riscv_operands_Immediate"] + fn classof(inst: &asm_riscv_Operand) -> bool; + fn value(self: &asm_riscv_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/memory.rs new file mode 100644 index 0000000..25571ef --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/memory.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/operands/Memory.hpp"); + + type asm_riscv_Operand = crate::asm::riscv::operand::ffi::asm_riscv_Operand; + + type asm_riscv_operands_Memory; + + #[Self = "asm_riscv_operands_Memory"] + fn classof(inst: &asm_riscv_Operand) -> bool; + fn base(self: &asm_riscv_operands_Memory) -> u64; + fn displacement(self: &asm_riscv_operands_Memory) -> i64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/pc_relative.rs new file mode 100644 index 0000000..bc13102 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/operands/PCRelative.hpp"); + + type asm_riscv_Operand = crate::asm::riscv::operand::ffi::asm_riscv_Operand; + + type asm_riscv_operands_PCRelative; + + #[Self = "asm_riscv_operands_PCRelative"] + fn classof(inst: &asm_riscv_Operand) -> bool; + fn value(self: &asm_riscv_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/register.rs new file mode 100644 index 0000000..4e63175 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/riscv/operands/register.rs @@ -0,0 +1,28 @@ +#[repr(C)] +pub struct reg_t { + pub reg: u64, + pub enum_type: u32, +} + +unsafe impl cxx::ExternType for reg_t { + type Id = cxx::type_id!("asm_riscv_operands_Register_reg_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/riscv/operands/Register.hpp"); + + type asm_riscv_Operand = crate::asm::riscv::operand::ffi::asm_riscv_Operand; + + type asm_riscv_operands_Register; + + type asm_riscv_operands_Register_reg_t = crate::asm::riscv::operands::register::reg_t; + + #[Self = "asm_riscv_operands_Register"] + fn classof(inst: &asm_riscv_Operand) -> bool; + fn value(self: &asm_riscv_operands_Register) -> asm_riscv_operands_Register_reg_t; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86.rs new file mode 100644 index 0000000..60a68d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86.rs @@ -0,0 +1,3 @@ +pub mod instruction; +pub mod operand; +pub mod operands; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/instruction.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/instruction.rs new file mode 100644 index 0000000..7cd76fb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/instruction.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/Instruction.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type asm_x86_Operand = crate::asm::x86::operand::ffi::asm_x86_Operand; + + type asm_x86_Instruction; + + #[Self = "asm_x86_Instruction"] + fn classof(inst: &asm_Instruction) -> bool; + fn opcode(self: &asm_x86_Instruction) -> u64; + fn operands(self: &asm_x86_Instruction) -> UniquePtr; + fn has_lock_prefix(self: &asm_x86_Instruction) -> bool; + fn is_lockable(self: &asm_x86_Instruction) -> bool; + fn is_atomic(self: &asm_x86_Instruction) -> bool; + fn lock(self: &asm_x86_Instruction) -> UniquePtr; + fn unlock(self: &asm_x86_Instruction) -> UniquePtr; + + type asm_x86_Instruction_it_operands; + + fn next(self: Pin<&mut asm_x86_Instruction_it_operands>) -> UniquePtr; + fn size(self: &asm_x86_Instruction_it_operands) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operand.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operand.rs new file mode 100644 index 0000000..87c404a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operand.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/Operand.hpp"); + + type asm_x86_Operand; + + fn to_string(self: &asm_x86_Operand) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands.rs new file mode 100644 index 0000000..bca3a48 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands.rs @@ -0,0 +1,4 @@ +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/immediate.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/immediate.rs new file mode 100644 index 0000000..c461dc1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/immediate.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/operands/Immediate.hpp"); + + type asm_x86_Operand = crate::asm::x86::operand::ffi::asm_x86_Operand; + + type asm_x86_operands_Immediate; + + #[Self = "asm_x86_operands_Immediate"] + fn classof(inst: &asm_x86_Operand) -> bool; + fn value(self: &asm_x86_operands_Immediate) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/memory.rs new file mode 100644 index 0000000..10d5e62 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/memory.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/operands/Memory.hpp"); + + type asm_x86_Operand = crate::asm::x86::operand::ffi::asm_x86_Operand; + + type asm_x86_operands_Memory; + + #[Self = "asm_x86_operands_Memory"] + fn classof(inst: &asm_x86_Operand) -> bool; + fn base(self: &asm_x86_operands_Memory) -> u64; + fn scaled_register(self: &asm_x86_operands_Memory) -> u64; + fn segment_register(self: &asm_x86_operands_Memory) -> u64; + fn scale(self: &asm_x86_operands_Memory) -> u64; + fn displacement(self: &asm_x86_operands_Memory) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/pc_relative.rs new file mode 100644 index 0000000..f3945fb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/pc_relative.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/operands/PCRelative.hpp"); + + type asm_x86_Operand = crate::asm::x86::operand::ffi::asm_x86_Operand; + + type asm_x86_operands_PCRelative; + + #[Self = "asm_x86_operands_PCRelative"] + fn classof(inst: &asm_x86_Operand) -> bool; + fn value(self: &asm_x86_operands_PCRelative) -> i64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/register.rs b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/register.rs new file mode 100644 index 0000000..6e99a56 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/asm/x86/operands/register.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/asm/x86/operands/Register.hpp"); + + type asm_x86_Operand = crate::asm::x86::operand::ffi::asm_x86_Operand; + + type asm_x86_operands_Register; + + #[Self = "asm_x86_operands_Register"] + fn classof(inst: &asm_x86_Operand) -> bool; + fn value(self: &asm_x86_operands_Register) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff.rs new file mode 100644 index 0000000..7fb95c0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff.rs @@ -0,0 +1,9 @@ +pub mod auxiliary_symbol; +pub mod auxiliary_symbols; +pub mod binary; +pub mod header; +pub mod relocation; +pub mod section; +pub mod string; +pub mod symbol; +pub mod utils; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbol.rs new file mode 100644 index 0000000..692ff61 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbol.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbol.hpp"); + + type Span = crate::utils::ffi::Span; + type COFF_AuxiliarySymbol; + + fn payload(self: &COFF_AuxiliarySymbol) -> Span; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols.rs new file mode 100644 index 0000000..3bf22e2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols.rs @@ -0,0 +1,6 @@ +pub mod auxiliary_clr_token; +pub mod auxiliary_file; +pub mod auxiliary_function_definition; +pub mod auxiliary_section_definition; +pub mod auxiliary_weak_external; +pub mod auxiliarybf_andef_symbol; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_clr_token.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_clr_token.rs new file mode 100644 index 0000000..578d27c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_clr_token.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type Span = crate::utils::ffi::Span; + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + type COFF_Symbol = crate::coff::symbol::ffi::COFF_Symbol; + + type COFF_AuxiliaryCLRToken; + + fn rgb_reserved(self: &COFF_AuxiliaryCLRToken) -> Span; + #[Self = "COFF_AuxiliaryCLRToken"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + fn aux_type(self: &COFF_AuxiliaryCLRToken) -> u8; + fn reserved(self: &COFF_AuxiliaryCLRToken) -> u8; + fn symbol_idx(self: &COFF_AuxiliaryCLRToken) -> u32; + fn symbol(self: &COFF_AuxiliaryCLRToken) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_file.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_file.rs new file mode 100644 index 0000000..c61ba59 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_file.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFile.hpp"); + + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + + type COFF_AuxiliaryFile; + + #[Self = "COFF_AuxiliaryFile"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + fn filename(self: &COFF_AuxiliaryFile) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_function_definition.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_function_definition.rs new file mode 100644 index 0000000..cd0e905 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_function_definition.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp"); + + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + + type COFF_AuxiliaryFunctionDefinition; + + #[Self = "COFF_AuxiliaryFunctionDefinition"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + fn tag_index(self: &COFF_AuxiliaryFunctionDefinition) -> u32; + fn total_size(self: &COFF_AuxiliaryFunctionDefinition) -> u32; + fn ptr_to_line_number(self: &COFF_AuxiliaryFunctionDefinition) -> u32; + fn ptr_to_next_func(self: &COFF_AuxiliaryFunctionDefinition) -> u32; + fn padding(self: &COFF_AuxiliaryFunctionDefinition) -> u16; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_section_definition.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_section_definition.rs new file mode 100644 index 0000000..cb61f22 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_section_definition.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp"); + + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + + type COFF_AuxiliarySectionDefinition; + + #[Self = "COFF_AuxiliarySectionDefinition"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + fn length(self: &COFF_AuxiliarySectionDefinition) -> u32; + fn nb_relocs(self: &COFF_AuxiliarySectionDefinition) -> u16; + fn nb_line_numbers(self: &COFF_AuxiliarySectionDefinition) -> u16; + fn checksum(self: &COFF_AuxiliarySectionDefinition) -> u32; + fn section_idx(self: &COFF_AuxiliarySectionDefinition) -> u32; + fn selection(self: &COFF_AuxiliarySectionDefinition) -> u8; + fn reserved(self: &COFF_AuxiliarySectionDefinition) -> u8; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_weak_external.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_weak_external.rs new file mode 100644 index 0000000..6418e23 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliary_weak_external.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp"); + + type Span = crate::utils::ffi::Span; + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + + type COFF_AuxiliaryWeakExternal; + + fn padding(self: &COFF_AuxiliaryWeakExternal) -> Span; + #[Self = "COFF_AuxiliaryWeakExternal"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + fn sym_idx(self: &COFF_AuxiliaryWeakExternal) -> u32; + fn characteristics(self: &COFF_AuxiliaryWeakExternal) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliarybf_andef_symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliarybf_andef_symbol.rs new file mode 100644 index 0000000..6176bfd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/auxiliary_symbols/auxiliarybf_andef_symbol.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp"); + + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + + type COFF_AuxiliarybfAndefSymbol; + + #[Self = "COFF_AuxiliarybfAndefSymbol"] + fn classof(entry: &COFF_AuxiliarySymbol) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/binary.rs new file mode 100644 index 0000000..51ed6f6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/binary.rs @@ -0,0 +1,81 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/Binary.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + include!("LIEF/rust/COFF/Relocation.hpp"); + + type COFF_Header = crate::coff::header::ffi::COFF_Header; + type COFF_Relocation = crate::coff::relocation::ffi::COFF_Relocation; + type COFF_Section = crate::coff::section::ffi::COFF_Section; + type COFF_String = crate::coff::string::ffi::COFF_String; + type COFF_Symbol = crate::coff::symbol::ffi::COFF_Symbol; + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + + type COFF_Binary; + + #[Self = "COFF_Binary"] + fn parse(path: &CxxString) -> UniquePtr; + fn header(self: &COFF_Binary) -> UniquePtr; + fn sections(self: &COFF_Binary) -> UniquePtr; + fn symbols(self: &COFF_Binary) -> UniquePtr; + fn relocations(self: &COFF_Binary) -> UniquePtr; + fn string_table(self: &COFF_Binary) -> UniquePtr; + fn section_by_name(self: &COFF_Binary, name: &CxxString) -> UniquePtr; + fn find_string(self: &COFF_Binary, offset: u32) -> UniquePtr; + fn find_function(self: &COFF_Binary, name: &CxxString) -> UniquePtr; + fn find_demangled_function(self: &COFF_Binary, name: &CxxString) -> UniquePtr; + fn functions(self: &COFF_Binary) -> UniquePtr; + fn disassemble_function( + self: &COFF_Binary, + function: &CxxString, + ) -> UniquePtr; + fn to_string(self: &COFF_Binary) -> UniquePtr; + fn disassemble_symbol( + self: &COFF_Binary, + sym: &COFF_Symbol, + ) -> UniquePtr; + unsafe fn disassemble_buffer( + self: &COFF_Binary, + ptr: *const u8, + size: u64, + addr: u64, + ) -> UniquePtr; + + type COFF_Binary_it_functions; + + fn next(self: Pin<&mut COFF_Binary_it_functions>) -> UniquePtr; + fn size(self: &COFF_Binary_it_functions) -> u64; + + type COFF_Binary_it_instructions; + + fn next(self: Pin<&mut COFF_Binary_it_instructions>) -> UniquePtr; + + type COFF_Binary_it_relocations; + + fn next(self: Pin<&mut COFF_Binary_it_relocations>) -> UniquePtr; + fn size(self: &COFF_Binary_it_relocations) -> u64; + + type COFF_Binary_it_sections; + + fn next(self: Pin<&mut COFF_Binary_it_sections>) -> UniquePtr; + fn size(self: &COFF_Binary_it_sections) -> u64; + + type COFF_Binary_it_strings; + + fn next(self: Pin<&mut COFF_Binary_it_strings>) -> UniquePtr; + fn size(self: &COFF_Binary_it_strings) -> u64; + + type COFF_Binary_it_symbols; + + fn next(self: Pin<&mut COFF_Binary_it_symbols>) -> UniquePtr; + fn size(self: &COFF_Binary_it_symbols) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/header.rs new file mode 100644 index 0000000..9cf69c3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/header.rs @@ -0,0 +1,38 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/Header.hpp"); + + type Span = crate::utils::ffi::Span; + type COFF_BigObjHeader; + + fn uuid(self: &COFF_BigObjHeader) -> Span; + #[Self = "COFF_BigObjHeader"] + fn classof(hdr: &COFF_Header) -> bool; + fn version(self: &COFF_BigObjHeader) -> u16; + fn sizeof_data(self: &COFF_BigObjHeader) -> u32; + fn flags(self: &COFF_BigObjHeader) -> u32; + fn metadata_size(self: &COFF_BigObjHeader) -> u32; + fn metadata_offset(self: &COFF_BigObjHeader) -> u32; + + type COFF_Header; + + fn machine(self: &COFF_Header) -> u32; + fn nb_sections(self: &COFF_Header) -> u32; + fn pointerto_symbol_table(self: &COFF_Header) -> u32; + fn nb_symbols(self: &COFF_Header) -> u32; + fn timedatestamp(self: &COFF_Header) -> u32; + fn to_string(self: &COFF_Header) -> UniquePtr; + + type COFF_RegularHeader; + + #[Self = "COFF_RegularHeader"] + fn classof(hdr: &COFF_Header) -> bool; + fn sizeof_optionalheader(self: &COFF_RegularHeader) -> u16; + fn characteristics(self: &COFF_RegularHeader) -> u16; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/relocation.rs new file mode 100644 index 0000000..206ca06 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/relocation.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/Relocation.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + include!("LIEF/rust/COFF/Symbol.hpp"); + + type COFF_Section = crate::coff::section::ffi::COFF_Section; + type COFF_Symbol = crate::coff::symbol::ffi::COFF_Symbol; + + type COFF_Relocation; + + fn symbol_idx(self: &COFF_Relocation) -> u32; + fn symbol(self: &COFF_Relocation) -> UniquePtr; + fn get_type(self: &COFF_Relocation) -> u32; + fn section(self: &COFF_Relocation) -> UniquePtr; + fn to_string(self: &COFF_Relocation) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/section.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/section.rs new file mode 100644 index 0000000..c9276c7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/section.rs @@ -0,0 +1,50 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/Section.hpp"); + include!("LIEF/rust/COFF/Symbol.hpp"); + include!("LIEF/rust/COFF/Relocation.hpp"); + + type COFF_Relocation = crate::coff::relocation::ffi::COFF_Relocation; + type COFF_String = crate::coff::string::ffi::COFF_String; + type COFF_Symbol = crate::coff::symbol::ffi::COFF_Symbol; + + type COFF_Section; + + fn sizeof_raw_data(self: &COFF_Section) -> u32; + fn virtual_size(self: &COFF_Section) -> u32; + fn pointerto_raw_data(self: &COFF_Section) -> u32; + fn pointerto_relocation(self: &COFF_Section) -> u32; + fn pointerto_line_numbers(self: &COFF_Section) -> u32; + fn numberof_relocations(self: &COFF_Section) -> u16; + fn numberof_line_numbers(self: &COFF_Section) -> u16; + fn characteristics(self: &COFF_Section) -> u32; + fn is_discardable(self: &COFF_Section) -> bool; + fn has_extended_relocations(self: &COFF_Section) -> bool; + fn relocations(self: &COFF_Section) -> UniquePtr; + fn symbols(self: &COFF_Section) -> UniquePtr; + fn comdat_info(self: &COFF_Section) -> UniquePtr; + fn coff_string(self: &COFF_Section) -> UniquePtr; + fn to_string(self: &COFF_Section) -> UniquePtr; + + type COFF_Section_ComdataInfo; + + fn symbol(self: &COFF_Section_ComdataInfo) -> UniquePtr; + fn kind(self: &COFF_Section_ComdataInfo) -> u8; + + type COFF_Section_it_relocations; + + fn next(self: Pin<&mut COFF_Section_it_relocations>) -> UniquePtr; + fn size(self: &COFF_Section_it_relocations) -> u64; + + type COFF_Section_it_symbols; + + fn next(self: Pin<&mut COFF_Section_it_symbols>) -> UniquePtr; + fn size(self: &COFF_Section_it_symbols) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/string.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/string.rs new file mode 100644 index 0000000..5b4f3e7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/string.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/String.hpp"); + + type COFF_String; + + fn str(self: &COFF_String) -> UniquePtr; + fn offset(self: &COFF_String) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/symbol.rs new file mode 100644 index 0000000..73610f1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/symbol.rs @@ -0,0 +1,38 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/Symbol.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type COFF_AuxiliarySymbol = crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; + type COFF_Section = crate::coff::section::ffi::COFF_Section; + + type COFF_Symbol; + + fn storage_class(self: &COFF_Symbol) -> u32; + fn base_type(self: &COFF_Symbol) -> u32; + fn complex_type(self: &COFF_Symbol) -> u32; + fn section_idx(self: &COFF_Symbol) -> i16; + fn section(self: &COFF_Symbol) -> UniquePtr; + fn is_external(self: &COFF_Symbol) -> bool; + fn is_function(self: &COFF_Symbol) -> bool; + fn is_absolute(self: &COFF_Symbol) -> bool; + fn is_weak_external(self: &COFF_Symbol) -> bool; + fn is_undefined(self: &COFF_Symbol) -> bool; + fn is_function_line_info(self: &COFF_Symbol) -> bool; + fn is_file_record(self: &COFF_Symbol) -> bool; + fn auxiliary_symbols(self: &COFF_Symbol) -> UniquePtr; + fn demangled_name(self: &COFF_Symbol) -> UniquePtr; + fn to_string(self: &COFF_Symbol) -> UniquePtr; + + type COFF_Symbol_it_auxiliary_symbols; + + fn next( + self: Pin<&mut COFF_Symbol_it_auxiliary_symbols>, + ) -> UniquePtr; + fn size(self: &COFF_Symbol_it_auxiliary_symbols) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/coff/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/coff/utils.rs new file mode 100644 index 0000000..49ce609 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/coff/utils.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/COFF/utils.hpp"); + + type COFF_Utils; + + #[Self = "COFF_Utils"] + fn is_coff(file: &CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/debug_decl_opt.rs b/vendor/lief/api/rust/crates/lief-ffi/src/debug_decl_opt.rs new file mode 100644 index 0000000..fa158d5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/debug_decl_opt.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DebugDeclOpt.hpp"); + + type LIEF_DeclOpt; + + #[Self = "LIEF_DeclOpt"] + fn create() -> UniquePtr; + fn set_indentation(self: Pin<&mut LIEF_DeclOpt>, value: u32); + fn set_is_cpp(self: Pin<&mut LIEF_DeclOpt>, value: bool); + fn set_show_extended_annotations(self: Pin<&mut LIEF_DeclOpt>, value: bool); + fn set_include_types(self: Pin<&mut LIEF_DeclOpt>, value: bool); + fn set_include_locals(self: Pin<&mut LIEF_DeclOpt>, value: bool); + fn set_desugar(self: Pin<&mut LIEF_DeclOpt>, value: bool); + fn set_show_field_offsets(self: Pin<&mut LIEF_DeclOpt>, value: bool); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/debug_location.rs b/vendor/lief/api/rust/crates/lief-ffi/src/debug_location.rs new file mode 100644 index 0000000..bbed7c4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/debug_location.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/debug_location.hpp"); + + type DebugLocation; + + fn file(self: &DebugLocation) -> UniquePtr; + fn line(self: &DebugLocation) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc.rs new file mode 100644 index 0000000..2b18013 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc.rs @@ -0,0 +1,6 @@ +pub mod caching; +pub mod dyld_shared_cache; +pub mod dylib; +pub mod mapping_info; +pub mod sub_cache; +pub mod utils; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/caching.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/caching.rs new file mode 100644 index 0000000..286641f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/caching.rs @@ -0,0 +1,9 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/caching.hpp"); + + fn dsc_enable_cache() -> bool; + fn dsc_enable_cache_from_dir(dir: &CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dyld_shared_cache.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dyld_shared_cache.rs new file mode 100644 index 0000000..2d03369 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dyld_shared_cache.rs @@ -0,0 +1,81 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/DyldSharedCache.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type dsc_Dylib = crate::dsc::dylib::ffi::dsc_Dylib; + type dsc_MappingInfo = crate::dsc::mapping_info::ffi::dsc_MappingInfo; + type dsc_SubCache = crate::dsc::sub_cache::ffi::dsc_SubCache; + + type dsc_DyldSharedCache; + + #[Self = "dsc_DyldSharedCache"] + fn from_path(file: &CxxString, arch: &CxxString) -> UniquePtr; + #[Self = "dsc_DyldSharedCache"] + unsafe fn from_files(ptr: *const c_char, size: usize) -> UniquePtr; + fn libraries(self: &dsc_DyldSharedCache) -> UniquePtr; + fn mapping_info( + self: &dsc_DyldSharedCache, + ) -> UniquePtr; + fn subcaches(self: &dsc_DyldSharedCache) -> UniquePtr; + fn filename(self: &dsc_DyldSharedCache) -> UniquePtr; + fn version(self: &dsc_DyldSharedCache) -> u32; + fn filepath(self: &dsc_DyldSharedCache) -> UniquePtr; + fn load_address(self: &dsc_DyldSharedCache) -> u64; + fn arch_name(self: &dsc_DyldSharedCache) -> UniquePtr; + fn platform(self: &dsc_DyldSharedCache) -> u32; + fn arch(self: &dsc_DyldSharedCache) -> u32; + fn has_subcaches(self: &dsc_DyldSharedCache) -> bool; + fn find_lib_from_va(self: &dsc_DyldSharedCache, va: u64) -> UniquePtr; + fn find_lib_from_path(self: &dsc_DyldSharedCache, path: &CxxString) + -> UniquePtr; + fn find_lib_from_name(self: &dsc_DyldSharedCache, name: &CxxString) + -> UniquePtr; + fn enable_caching(self: &dsc_DyldSharedCache, dir: &CxxString); + fn flush_cache(self: &dsc_DyldSharedCache); + fn disassemble( + self: &dsc_DyldSharedCache, + addr: u64, + ) -> UniquePtr; + fn cache_for_address( + self: &dsc_DyldSharedCache, + addr: u64, + ) -> UniquePtr; + fn main_cache(self: &dsc_DyldSharedCache) -> UniquePtr; + fn find_subcache( + self: &dsc_DyldSharedCache, + filename: &CxxString, + ) -> UniquePtr; + fn va_to_offset(self: &dsc_DyldSharedCache, va: u64, err: Pin<&mut u32>) -> u64; + fn get_content_from_va( + self: &dsc_DyldSharedCache, + va: u64, + size: u64, + ) -> UniquePtr>; + + type dsc_DyldSharedCache_it_instructions; + + fn next(self: Pin<&mut dsc_DyldSharedCache_it_instructions>) -> UniquePtr; + + type dsc_DyldSharedCache_it_libraries; + + fn next(self: Pin<&mut dsc_DyldSharedCache_it_libraries>) -> UniquePtr; + fn size(self: &dsc_DyldSharedCache_it_libraries) -> u64; + + type dsc_DyldSharedCache_it_mapping_info; + + fn next(self: Pin<&mut dsc_DyldSharedCache_it_mapping_info>) -> UniquePtr; + fn size(self: &dsc_DyldSharedCache_it_mapping_info) -> u64; + + type dsc_DyldSharedCache_it_subcaches; + + fn next(self: Pin<&mut dsc_DyldSharedCache_it_subcaches>) -> UniquePtr; + fn size(self: &dsc_DyldSharedCache_it_subcaches) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dylib.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dylib.rs new file mode 100644 index 0000000..c6d8059 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/dylib.rs @@ -0,0 +1,38 @@ +#[repr(C)] +pub struct extract_opt { + pub pack: bool, + pub fix_branches: bool, + pub fix_memory: bool, + pub fix_relocations: bool, + pub fix_objc: bool, + pub create_dyld_chained_fixup_cmd: bool, + pub create_dyld_chained_fixup_cmd_set: bool, +} + +unsafe impl cxx::ExternType for extract_opt { + type Id = cxx::type_id!("dsc_Dylib_extract_opt"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/Dylib.hpp"); + + type MachO_Binary = crate::macho::binary::ffi::MachO_Binary; + + type dsc_Dylib_extract_opt = crate::dsc::dylib::extract_opt; + + type dsc_Dylib; + + fn path(self: &dsc_Dylib) -> UniquePtr; + fn address(self: &dsc_Dylib) -> u64; + fn modtime(self: &dsc_Dylib) -> u64; + fn inode(self: &dsc_Dylib) -> u64; + fn padding(self: &dsc_Dylib) -> u64; + fn get_macho(self: &dsc_Dylib, opt: &dsc_Dylib_extract_opt) -> UniquePtr; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/mapping_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/mapping_info.rs new file mode 100644 index 0000000..15490b0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/mapping_info.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/MappingInfo.hpp"); + + type dsc_MappingInfo; + + fn address(self: &dsc_MappingInfo) -> u64; + fn size(self: &dsc_MappingInfo) -> u64; + fn end_address(self: &dsc_MappingInfo) -> u64; + fn file_offset(self: &dsc_MappingInfo) -> u64; + fn max_prot(self: &dsc_MappingInfo) -> u32; + fn init_prot(self: &dsc_MappingInfo) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/sub_cache.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/sub_cache.rs new file mode 100644 index 0000000..ec507ef --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/sub_cache.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/SubCache.hpp"); + include!("LIEF/rust/DyldSharedCache/DyldSharedCache.hpp"); + + type dsc_DyldSharedCache = crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache; + + type dsc_SubCache; + + fn vm_offset(self: &dsc_SubCache) -> u64; + fn suffix(self: &dsc_SubCache) -> UniquePtr; + fn uuid(self: &dsc_SubCache) -> UniquePtr>; + fn cache(self: &dsc_SubCache) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dsc/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/utils.rs new file mode 100644 index 0000000..870cff5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dsc/utils.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DyldSharedCache/utils.hpp"); + + type dsc_Utils; + + #[Self = "dsc_Utils"] + fn is_shared_cache(file: &CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf.rs new file mode 100644 index 0000000..be9bd38 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf.rs @@ -0,0 +1,10 @@ +pub mod compilation_unit; +pub mod debug_info; +pub mod editor; +pub mod function; +pub mod lexical_block; +pub mod parameter; +pub mod scope; +pub mod type_; +pub mod types; +pub mod variable; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/compilation_unit.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/compilation_unit.rs new file mode 100644 index 0000000..65fffe4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/compilation_unit.rs @@ -0,0 +1,86 @@ +#[repr(C)] +pub struct Language { + pub lang: u32, + pub version: u32, +} + +unsafe impl cxx::ExternType for Language { + type Id = cxx::type_id!("DWARF_CompilationUnit_Language"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/CompilationUnit.hpp"); + + type Range = crate::utils::ffi::Range; + type DWARF_Function = crate::dwarf::function::ffi::DWARF_Function; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + type DWARF_Variable = crate::dwarf::variable::ffi::DWARF_Variable; + type DWARF_CompilationUnit_Language = crate::dwarf::compilation_unit::Language; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type DWARF_CompilationUnit; + + fn ranges(self: &DWARF_CompilationUnit) -> UniquePtr>; + fn language(self: &DWARF_CompilationUnit) -> DWARF_CompilationUnit_Language; + + fn name(self: &DWARF_CompilationUnit) -> UniquePtr; + fn producer(self: &DWARF_CompilationUnit) -> UniquePtr; + fn compilation_dir(self: &DWARF_CompilationUnit) -> UniquePtr; + fn low_address(self: &DWARF_CompilationUnit) -> u64; + fn high_address(self: &DWARF_CompilationUnit) -> u64; + fn size(self: &DWARF_CompilationUnit) -> u64; + fn function_by_name( + self: &DWARF_CompilationUnit, + name: &CxxString, + ) -> UniquePtr; + fn variable_by_name( + self: &DWARF_CompilationUnit, + name: &CxxString, + ) -> UniquePtr; + fn functions(self: &DWARF_CompilationUnit) + -> UniquePtr; + fn imported_functions( + self: &DWARF_CompilationUnit, + ) -> UniquePtr; + fn types(self: &DWARF_CompilationUnit) -> UniquePtr; + fn variables(self: &DWARF_CompilationUnit) + -> UniquePtr; + fn function_by_address( + self: &DWARF_CompilationUnit, + addr: u64, + ) -> UniquePtr; + fn variable_by_address( + self: &DWARF_CompilationUnit, + addr: u64, + ) -> UniquePtr; + fn to_decl(self: &DWARF_CompilationUnit) -> UniquePtr; + fn to_decl_with_opt( + self: &DWARF_CompilationUnit, + opt: &LIEF_DeclOpt, + ) -> UniquePtr; + + type DWARF_CompilationUnit_it_functions; + + fn next(self: Pin<&mut DWARF_CompilationUnit_it_functions>) -> UniquePtr; + fn size(self: &DWARF_CompilationUnit_it_functions) -> u64; + + type DWARF_CompilationUnit_it_types; + + fn next(self: Pin<&mut DWARF_CompilationUnit_it_types>) -> UniquePtr; + fn size(self: &DWARF_CompilationUnit_it_types) -> u64; + + type DWARF_CompilationUnit_it_variables; + + fn next(self: Pin<&mut DWARF_CompilationUnit_it_variables>) -> UniquePtr; + fn size(self: &DWARF_CompilationUnit_it_variables) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl CxxVector {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/debug_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/debug_info.rs new file mode 100644 index 0000000..16c23fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/debug_info.rs @@ -0,0 +1,36 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/DebugInfo.hpp"); + + type AbstracDebugInfo = crate::generic::debug_info::ffi::AbstracDebugInfo; + type DWARF_CompilationUnit = crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit; + type DWARF_Function = crate::dwarf::function::ffi::DWARF_Function; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + type DWARF_Variable = crate::dwarf::variable::ffi::DWARF_Variable; + + type DWARF_DebugInfo; + + #[Self = "DWARF_DebugInfo"] + fn from_file(file: &CxxString) -> UniquePtr; + #[Self = "DWARF_DebugInfo"] + fn classof(reloc: &AbstracDebugInfo) -> bool; + fn compilation_units( + self: &DWARF_DebugInfo, + ) -> UniquePtr; + fn function_by_name(self: &DWARF_DebugInfo, name: &CxxString) -> UniquePtr; + fn variable_by_name(self: &DWARF_DebugInfo, name: &CxxString) -> UniquePtr; + fn type_by_name(self: &DWARF_DebugInfo, name: &CxxString) -> UniquePtr; + fn function_by_addr(self: &DWARF_DebugInfo, addr: u64) -> UniquePtr; + fn variable_by_addr(self: &DWARF_DebugInfo, addr: u64) -> UniquePtr; + + type DWARF_DebugInfo_it_compilation_units; + + fn next( + self: Pin<&mut DWARF_DebugInfo_it_compilation_units>, + ) -> UniquePtr; + fn size(self: &DWARF_DebugInfo_it_compilation_units) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor.rs new file mode 100644 index 0000000..d4317ab --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor.rs @@ -0,0 +1,37 @@ +pub mod array_type; +pub mod base_type; +pub mod compilation_unit; +pub mod enum_type; +pub mod function; +pub mod function_type; +pub mod pointer_type; +pub mod struct_type; +pub mod type_; +pub mod type_def; +pub mod variable; + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Editor.hpp"); + + type AbstractBinary = crate::generic::binary::ffi::AbstractBinary; + type DWARF_editor_CompilationUnit = + crate::dwarf::editor::compilation_unit::ffi::DWARF_editor_CompilationUnit; + + type DWARF_Editor; + + fn create_compilation_unit( + self: Pin<&mut DWARF_Editor>, + ) -> UniquePtr; + + fn write(self: Pin<&mut DWARF_Editor>, output: &CxxString); + + #[Self = "DWARF_Editor"] + fn from_binary(bin: Pin<&mut AbstractBinary>) -> UniquePtr; + + #[Self = "DWARF_Editor"] + fn create(fmt: u32, arch: u32) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/array_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/array_type.rs new file mode 100644 index 0000000..3768500 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/array_type.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/ArrayType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_ArrayType; + + #[Self = "DWARF_editor_ArrayType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/base_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/base_type.rs new file mode 100644 index 0000000..9c8bffd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/base_type.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/BaseType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_BaseType; + + #[Self = "DWARF_editor_BaseType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/compilation_unit.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/compilation_unit.rs new file mode 100644 index 0000000..bb0ffd7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/compilation_unit.rs @@ -0,0 +1,75 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/CompilationUnit.hpp"); + + type DWARF_editor_ArrayType = crate::dwarf::editor::array_type::ffi::DWARF_editor_ArrayType; + type DWARF_editor_BaseType = crate::dwarf::editor::base_type::ffi::DWARF_editor_BaseType; + type DWARF_editor_EnumType = crate::dwarf::editor::enum_type::ffi::DWARF_editor_EnumType; + type DWARF_editor_Function = crate::dwarf::editor::function::ffi::DWARF_editor_Function; + type DWARF_editor_FunctionType = + crate::dwarf::editor::function_type::ffi::DWARF_editor_FunctionType; + type DWARF_editor_PointerType = + crate::dwarf::editor::pointer_type::ffi::DWARF_editor_PointerType; + type DWARF_editor_StructType = + crate::dwarf::editor::struct_type::ffi::DWARF_editor_StructType; + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + type DWARF_editor_TypeDef = crate::dwarf::editor::type_def::ffi::DWARF_editor_TypeDef; + type DWARF_editor_Variable = crate::dwarf::editor::variable::ffi::DWARF_editor_Variable; + + type DWARF_editor_CompilationUnit; + + fn set_producer(self: Pin<&mut DWARF_editor_CompilationUnit>, value: &CxxString); + fn create_function( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ) -> UniquePtr; + fn create_variable( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ) -> UniquePtr; + fn create_generic_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ) -> UniquePtr; + fn create_enum( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ) -> UniquePtr; + fn create_typedef( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ty: &DWARF_editor_Type, + ) -> UniquePtr; + fn create_structure( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + kind: u32, + ) -> UniquePtr; + fn create_base_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + size: u64, + encoding: u32, + ) -> UniquePtr; + fn create_function_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ) -> UniquePtr; + fn create_pointer_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + ty: &DWARF_editor_Type, + ) -> UniquePtr; + fn create_void_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + ) -> UniquePtr; + fn create_array_type( + self: Pin<&mut DWARF_editor_CompilationUnit>, + name: &CxxString, + ty: &DWARF_editor_Type, + count: u64, + ) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/enum_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/enum_type.rs new file mode 100644 index 0000000..d256af5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/enum_type.rs @@ -0,0 +1,25 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/EnumType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_EnumType; + + #[Self = "DWARF_editor_EnumType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + fn set_size(self: Pin<&mut DWARF_editor_EnumType>, size: u64); + fn set_underlying_type(self: Pin<&mut DWARF_editor_EnumType>, ty: &DWARF_editor_Type); + fn add_value( + self: Pin<&mut DWARF_editor_EnumType>, + name: &CxxString, + value: i64, + ) -> UniquePtr; + + type DWARF_editor_EnumType_Value; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function.rs new file mode 100644 index 0000000..38fba84 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function.rs @@ -0,0 +1,81 @@ +pub struct Range { + pub start: u64, + pub end: u64, +} + +unsafe impl cxx::ExternType for Range { + type Id = cxx::type_id!("DWARF_editor_Function_Range"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/Function.hpp"); + + type DWARF_editor_Function_Range = crate::dwarf::editor::function::Range; + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + type DWARF_editor_Variable = crate::dwarf::editor::variable::ffi::DWARF_editor_Variable; + + type DWARF_editor_Function; + + fn set_address(self: Pin<&mut DWARF_editor_Function>, addr: u64); + fn set_low_high(self: Pin<&mut DWARF_editor_Function>, low: u64, high: u64); + fn set_ranges( + self: Pin<&mut DWARF_editor_Function>, + ranges: &CxxVector, + ); + fn set_external(self: Pin<&mut DWARF_editor_Function>); + fn set_return_type(self: Pin<&mut DWARF_editor_Function>, ty: &DWARF_editor_Type); + fn add_parameter( + self: Pin<&mut DWARF_editor_Function>, + name: &CxxString, + ty: &DWARF_editor_Type, + ) -> UniquePtr; + fn create_stack_variable( + self: Pin<&mut DWARF_editor_Function>, + name: &CxxString, + ) -> UniquePtr; + fn add_lexical_block( + self: Pin<&mut DWARF_editor_Function>, + start: u64, + end: u64, + ) -> UniquePtr; + fn add_label( + self: Pin<&mut DWARF_editor_Function>, + addr: u64, + label: &CxxString, + ) -> UniquePtr; + fn add_description(self: Pin<&mut DWARF_editor_Function>, desc: &CxxString); + + type DWARF_editor_Function_Label; + + type DWARF_editor_Function_LexicalBlock; + + fn add_block( + self: Pin<&mut DWARF_editor_Function_LexicalBlock>, + start: u64, + end: u64, + ) -> UniquePtr; + fn add_block_from_range( + self: Pin<&mut DWARF_editor_Function_LexicalBlock>, + ranges: &CxxVector, + ) -> UniquePtr; + fn add_name(self: Pin<&mut DWARF_editor_Function_LexicalBlock>, name: &CxxString); + fn add_description(self: Pin<&mut DWARF_editor_Function_LexicalBlock>, name: &CxxString); + + type DWARF_editor_Function_Parameter; + + fn assign_register_by_name( + self: Pin<&mut DWARF_editor_Function_Parameter>, + name: &CxxString, + ); + fn assign_register_by_id(self: Pin<&mut DWARF_editor_Function_Parameter>, id: u64); + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl CxxVector {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function_type.rs new file mode 100644 index 0000000..4e5b5cc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/function_type.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/FunctionType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_FunctionType; + + #[Self = "DWARF_editor_FunctionType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + fn set_return_type(self: Pin<&mut DWARF_editor_FunctionType>, ty: &DWARF_editor_Type); + fn add_parameter( + self: Pin<&mut DWARF_editor_FunctionType>, + ty: &DWARF_editor_Type, + ) -> UniquePtr; + + type DWARF_editor_FunctionType_Parameter; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/pointer_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/pointer_type.rs new file mode 100644 index 0000000..136b44b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/pointer_type.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/PointerType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_PointerType; + + #[Self = "DWARF_editor_PointerType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + fn pointer_to(self: &DWARF_editor_PointerType) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/struct_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/struct_type.rs new file mode 100644 index 0000000..c4ee7f8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/struct_type.rs @@ -0,0 +1,43 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/StructType.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_StructType; + + #[Self = "DWARF_editor_StructType"] + fn classof(type_: &DWARF_editor_Type) -> bool; + fn set_size(self: Pin<&mut DWARF_editor_StructType>, size: u64); + fn add_member( + self: Pin<&mut DWARF_editor_StructType>, + name: &CxxString, + ty: &DWARF_editor_Type, + ) -> UniquePtr; + fn add_member_with_offset( + self: Pin<&mut DWARF_editor_StructType>, + name: &CxxString, + ty: &DWARF_editor_Type, + offset: u64, + ) -> UniquePtr; + fn add_bitfield( + self: Pin<&mut DWARF_editor_StructType>, + name: &CxxString, + ty: &DWARF_editor_Type, + bitsize: u64, + ) -> UniquePtr; + fn add_bitfield_with_offset( + self: Pin<&mut DWARF_editor_StructType>, + name: &CxxString, + ty: &DWARF_editor_Type, + bitsize: u64, + offset: u64, + ) -> UniquePtr; + + type DWARF_editor_StructType_Member; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_.rs new file mode 100644 index 0000000..be7f667 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/Type.hpp"); + include!("LIEF/rust/DWARF/editor/PointerType.hpp"); + + type DWARF_editor_PointerType = + crate::dwarf::editor::pointer_type::ffi::DWARF_editor_PointerType; + + type DWARF_editor_Type; + + fn pointer_to(self: &DWARF_editor_Type) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_def.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_def.rs new file mode 100644 index 0000000..b70724f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/type_def.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/TypeDef.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_TypeDef; + + #[Self = "DWARF_editor_TypeDef"] + fn classof(type_: &DWARF_editor_Type) -> bool; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/variable.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/variable.rs new file mode 100644 index 0000000..ccbc667 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/editor/variable.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/editor/Variable.hpp"); + + type DWARF_editor_Type = crate::dwarf::editor::type_::ffi::DWARF_editor_Type; + + type DWARF_editor_Variable; + + fn set_external(self: Pin<&mut DWARF_editor_Variable>); + fn set_addr(self: Pin<&mut DWARF_editor_Variable>, addr: u64); + fn set_stack_offset(self: Pin<&mut DWARF_editor_Variable>, addr: u64); + fn set_type(self: Pin<&mut DWARF_editor_Variable>, ty: &DWARF_editor_Type); + fn add_description(self: Pin<&mut DWARF_editor_Variable>, desc: &CxxString); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/function.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/function.rs new file mode 100644 index 0000000..84a75de --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/function.rs @@ -0,0 +1,68 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Function.hpp"); + + type Range = crate::utils::ffi::Range; + type DWARF_LexicalBlock = crate::dwarf::lexical_block::ffi::DWARF_LexicalBlock; + type DWARF_Parameter = crate::dwarf::parameter::ffi::DWARF_Parameter; + type DWARF_Scope = crate::dwarf::scope::ffi::DWARF_Scope; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + type DWARF_Variable = crate::dwarf::variable::ffi::DWARF_Variable; + type DebugLocation = crate::debug_location::ffi::DebugLocation; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + + type DWARF_Function; + + fn ranges(self: &DWARF_Function) -> UniquePtr>; + fn name(self: &DWARF_Function) -> UniquePtr; + fn linkage_name(self: &DWARF_Function) -> UniquePtr; + fn variables(self: &DWARF_Function) -> UniquePtr; + fn address(self: &DWARF_Function, err: Pin<&mut u32>) -> u64; + fn is_artificial(self: &DWARF_Function) -> bool; + fn is_external(self: &DWARF_Function) -> bool; + fn size(self: &DWARF_Function) -> u64; + fn debug_location(self: &DWARF_Function) -> UniquePtr; + fn get_type(self: &DWARF_Function) -> UniquePtr; + fn parameters(self: &DWARF_Function) -> UniquePtr; + fn thrown_types(self: &DWARF_Function) -> UniquePtr; + fn scope(self: &DWARF_Function) -> UniquePtr; + fn instructions(self: &DWARF_Function) -> UniquePtr; + fn description(self: &DWARF_Function) -> UniquePtr; + fn lexical_blocks(self: &DWARF_Function) -> UniquePtr; + fn to_decl(self: &DWARF_Function) -> UniquePtr; + fn to_decl_with_opt(self: &DWARF_Function, opt: &LIEF_DeclOpt) -> UniquePtr; + + type DWARF_Function_it_instructions; + + fn next(self: Pin<&mut DWARF_Function_it_instructions>) -> UniquePtr; + + type DWARF_Function_it_lexical_blocks; + + fn next(self: Pin<&mut DWARF_Function_it_lexical_blocks>) -> UniquePtr; + fn size(self: &DWARF_Function_it_lexical_blocks) -> u64; + + type DWARF_Function_it_parameters; + + fn next(self: Pin<&mut DWARF_Function_it_parameters>) -> UniquePtr; + fn size(self: &DWARF_Function_it_parameters) -> u64; + + type DWARF_Function_it_thrown_types; + + fn next(self: Pin<&mut DWARF_Function_it_thrown_types>) -> UniquePtr; + fn size(self: &DWARF_Function_it_thrown_types) -> u64; + + type DWARF_Function_it_variables; + + fn next(self: Pin<&mut DWARF_Function_it_variables>) -> UniquePtr; + fn size(self: &DWARF_Function_it_variables) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/lexical_block.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/lexical_block.rs new file mode 100644 index 0000000..51f9dc0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/lexical_block.rs @@ -0,0 +1,25 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/LexicalBlock.hpp"); + + type Range = crate::utils::ffi::Range; + type DWARF_LexicalBlock; + + fn ranges(self: &DWARF_LexicalBlock) -> UniquePtr>; + fn name(self: &DWARF_LexicalBlock) -> UniquePtr; + fn description(self: &DWARF_LexicalBlock) -> UniquePtr; + fn addr(self: &DWARF_LexicalBlock, is_set: Pin<&mut u32>) -> u64; + fn low_pc(self: &DWARF_LexicalBlock, is_set: Pin<&mut u32>) -> u64; + fn high_pc(self: &DWARF_LexicalBlock, is_set: Pin<&mut u32>) -> u64; + fn size(self: &DWARF_LexicalBlock) -> u64; + fn sub_blocks(self: &DWARF_LexicalBlock) -> UniquePtr; + + type DWARF_LexicalBlock_it_sub_blocks; + + fn next(self: Pin<&mut DWARF_LexicalBlock_it_sub_blocks>) -> UniquePtr; + fn size(self: &DWARF_LexicalBlock_it_sub_blocks) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/parameter.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/parameter.rs new file mode 100644 index 0000000..94619a6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/parameter.rs @@ -0,0 +1,46 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Parameter.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_Parameter; + + fn name(self: &DWARF_Parameter) -> UniquePtr; + fn get_type(self: &DWARF_Parameter) -> UniquePtr; + fn location(self: &DWARF_Parameter) -> UniquePtr; + + type DWARF_Parameter_Location; + + fn get_type(self: &DWARF_Parameter_Location) -> u8; + + type DWARF_Parameter_RegisterLocation; + + #[Self = "DWARF_Parameter_RegisterLocation"] + fn classof(loc: &DWARF_Parameter_Location) -> bool; + fn id(self: &DWARF_Parameter_RegisterLocation) -> u64; + + type DWARF_parameters_Formal; + + #[Self = "DWARF_parameters_Formal"] + fn classof(type_: &DWARF_Parameter) -> bool; + + type DWARF_parameters_TemplateType; + + #[Self = "DWARF_parameters_TemplateType"] + fn classof(type_: &DWARF_Parameter) -> bool; + + type DWARF_parameters_TemplateValue; + + #[Self = "DWARF_parameters_TemplateValue"] + fn classof(type_: &DWARF_Parameter) -> bool; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/scope.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/scope.rs new file mode 100644 index 0000000..947aaf3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/scope.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Scope.hpp"); + + type DWARF_Scope; + + fn name(self: &DWARF_Scope) -> UniquePtr; + fn parent(self: &DWARF_Scope) -> UniquePtr; + fn get_type(self: &DWARF_Scope) -> u32; + fn chained(self: &DWARF_Scope, sep: &CxxString) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/type_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/type_.rs new file mode 100644 index 0000000..b4adce8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/type_.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Type.hpp"); + + type DWARF_Scope = crate::dwarf::scope::ffi::DWARF_Scope; + type DebugLocation = crate::debug_location::ffi::DebugLocation; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type DWARF_Type; + + fn name(self: &DWARF_Type, err: Pin<&mut u32>) -> UniquePtr; + fn size(self: &DWARF_Type, err: Pin<&mut u32>) -> u64; + fn location(self: &DWARF_Type) -> UniquePtr; + fn is_unspecified(self: &DWARF_Type) -> bool; + fn scope(self: &DWARF_Type) -> UniquePtr; + fn to_decl(self: &DWARF_Type) -> UniquePtr; + fn to_decl_with_opt(self: &DWARF_Type, opt: &LIEF_DeclOpt) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types.rs new file mode 100644 index 0000000..55cb64b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types.rs @@ -0,0 +1,24 @@ +pub mod array; +pub mod atomic; +pub mod base; +pub mod class_like; +pub mod coarray; +pub mod const_; +pub mod dynamic; +pub mod enum_; +pub mod file; +pub mod immutable; +pub mod interface; +pub mod pointer; +pub mod pointer_to_member; +pub mod r_value_ref; +pub mod reference; +pub mod restrict; +pub mod set_ty; +pub mod shared; +pub mod string_ty; +pub mod subroutine; +pub mod template_alias; +pub mod thrown; +pub mod typedef; +pub mod volatile; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/array.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/array.rs new file mode 100644 index 0000000..346e99d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/array.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Array.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Array; + + #[Self = "DWARF_types_Array"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Array) -> UniquePtr; + fn size_info(self: &DWARF_types_Array) -> UniquePtr; + + type DWARF_types_array_size_info; + + fn name(self: &DWARF_types_array_size_info) -> UniquePtr; + fn size(self: &DWARF_types_array_size_info) -> u64; + fn get_type(self: &DWARF_types_array_size_info) -> UniquePtr; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/atomic.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/atomic.rs new file mode 100644 index 0000000..79fa8ca --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/atomic.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Atomic.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Atomic; + + #[Self = "DWARF_types_Atomic"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Atomic) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/base.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/base.rs new file mode 100644 index 0000000..3647d81 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/base.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Base.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Base; + + #[Self = "DWARF_types_Base"] + fn classof(type_: &DWARF_Type) -> bool; + fn encoding(self: &DWARF_types_Base) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/class_like.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/class_like.rs new file mode 100644 index 0000000..870d60d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/class_like.rs @@ -0,0 +1,71 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/ClassLike.hpp"); + + type DWARF_Function = crate::dwarf::function::ffi::DWARF_Function; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Class; + + #[Self = "DWARF_types_Class"] + fn classof(type_: &DWARF_Type) -> bool; + + type DWARF_types_ClassLike; + + #[Self = "DWARF_types_ClassLike"] + fn classof(type_: &DWARF_Type) -> bool; + fn find_member( + self: &DWARF_types_ClassLike, + offset: u64, + ) -> UniquePtr; + fn members(self: &DWARF_types_ClassLike) -> UniquePtr; + fn functions(self: &DWARF_types_ClassLike) + -> UniquePtr; + + type DWARF_types_ClassLike_Member; + + fn name(self: &DWARF_types_ClassLike_Member) -> UniquePtr; + fn bit_offset(self: &DWARF_types_ClassLike_Member, err: Pin<&mut u32>) -> u64; + fn bit_size(self: &DWARF_types_ClassLike_Member, err: Pin<&mut u32>) -> u64; + fn offset(self: &DWARF_types_ClassLike_Member, err: Pin<&mut u32>) -> u64; + fn is_declaration(self: &DWARF_types_ClassLike_Member) -> bool; + fn is_external(self: &DWARF_types_ClassLike_Member) -> bool; + fn get_type(self: &DWARF_types_ClassLike_Member) -> UniquePtr; + + type DWARF_types_ClassLike_it_functions; + + fn next(self: Pin<&mut DWARF_types_ClassLike_it_functions>) -> UniquePtr; + fn size(self: &DWARF_types_ClassLike_it_functions) -> u64; + + type DWARF_types_ClassLike_it_members; + + fn next( + self: Pin<&mut DWARF_types_ClassLike_it_members>, + ) -> UniquePtr; + fn size(self: &DWARF_types_ClassLike_it_members) -> u64; + + type DWARF_types_Packed; + + #[Self = "DWARF_types_Packed"] + fn classof(type_: &DWARF_Type) -> bool; + + type DWARF_types_Structure; + + #[Self = "DWARF_types_Structure"] + fn classof(type_: &DWARF_Type) -> bool; + + type DWARF_types_Union; + + #[Self = "DWARF_types_Union"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/coarray.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/coarray.rs new file mode 100644 index 0000000..6159951 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/coarray.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Coarray.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Coarray; + + #[Self = "DWARF_types_Coarray"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/const_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/const_.rs new file mode 100644 index 0000000..96aecc2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/const_.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Const.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Const; + + #[Self = "DWARF_types_Const"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Const) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/dynamic.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/dynamic.rs new file mode 100644 index 0000000..91d075e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/dynamic.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Dynamic.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Dynamic; + + #[Self = "DWARF_types_Dynamic"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/enum_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/enum_.rs new file mode 100644 index 0000000..e75f81e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/enum_.rs @@ -0,0 +1,29 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Enum.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Enum; + + #[Self = "DWARF_types_Enum"] + fn classof(type_: &DWARF_Type) -> bool; + fn entries(self: &DWARF_types_Enum) -> UniquePtr; + fn underlying_type(self: &DWARF_types_Enum) -> UniquePtr; + fn find_entry(self: &DWARF_types_Enum, value: i64) -> UniquePtr; + + type DWARF_types_Enum_Entry; + + fn name(self: &DWARF_types_Enum_Entry) -> UniquePtr; + fn value(self: &DWARF_types_Enum_Entry, is_set: Pin<&mut u32>) -> i64; + + type DWARF_types_Enum_it_entries; + + fn next(self: Pin<&mut DWARF_types_Enum_it_entries>) -> UniquePtr; + fn size(self: &DWARF_types_Enum_it_entries) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/file.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/file.rs new file mode 100644 index 0000000..0f1463f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/file.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/File.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_File; + + #[Self = "DWARF_types_File"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/immutable.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/immutable.rs new file mode 100644 index 0000000..3e39f82 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/immutable.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Immutable.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Immutable; + + #[Self = "DWARF_types_Immutable"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Immutable) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/interface.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/interface.rs new file mode 100644 index 0000000..eccc2c4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/interface.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Interface.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Interface; + + #[Self = "DWARF_types_Interface"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer.rs new file mode 100644 index 0000000..d313b4e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Pointer.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Pointer; + + #[Self = "DWARF_types_Pointer"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Pointer) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer_to_member.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer_to_member.rs new file mode 100644 index 0000000..d3ba897 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/pointer_to_member.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/PointerToMember.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_PointerToMember; + + #[Self = "DWARF_types_PointerToMember"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_PointerToMember) -> UniquePtr; + fn containing_type(self: &DWARF_types_PointerToMember) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/r_value_ref.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/r_value_ref.rs new file mode 100644 index 0000000..4c67e06 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/r_value_ref.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/RValueRef.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_RValueReference; + + #[Self = "DWARF_types_RValueReference"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_RValueReference) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/reference.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/reference.rs new file mode 100644 index 0000000..c39f01b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/reference.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Reference.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Reference; + + #[Self = "DWARF_types_Reference"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Reference) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/restrict.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/restrict.rs new file mode 100644 index 0000000..caa15db --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/restrict.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Restrict.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Restrict; + + #[Self = "DWARF_types_Restrict"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Restrict) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/set_ty.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/set_ty.rs new file mode 100644 index 0000000..41d6bbb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/set_ty.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/SetTy.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_SetTy; + + #[Self = "DWARF_types_SetTy"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_SetTy) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/shared.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/shared.rs new file mode 100644 index 0000000..2f24ecd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/shared.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Shared.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Shared; + + #[Self = "DWARF_types_Shared"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Shared) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/string_ty.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/string_ty.rs new file mode 100644 index 0000000..0d15a67 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/string_ty.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/StringTy.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_StringTy; + + #[Self = "DWARF_types_StringTy"] + fn classof(type_: &DWARF_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/subroutine.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/subroutine.rs new file mode 100644 index 0000000..3f85a11 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/subroutine.rs @@ -0,0 +1,26 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Subroutine.hpp"); + + type DWARF_Parameter = crate::dwarf::parameter::ffi::DWARF_Parameter; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Subroutine; + + #[Self = "DWARF_types_Subroutine"] + fn classof(type_: &DWARF_Type) -> bool; + fn return_type(self: &DWARF_types_Subroutine) -> UniquePtr; + fn parameters( + self: &DWARF_types_Subroutine, + ) -> UniquePtr; + + type DWARF_types_Subroutine_it_parameters; + + fn next(self: Pin<&mut DWARF_types_Subroutine_it_parameters>) + -> UniquePtr; + fn size(self: &DWARF_types_Subroutine_it_parameters) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/template_alias.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/template_alias.rs new file mode 100644 index 0000000..d59b4d0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/template_alias.rs @@ -0,0 +1,27 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/TemplateAlias.hpp"); + + type DWARF_Parameter = crate::dwarf::parameter::ffi::DWARF_Parameter; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_TemplateAlias; + + #[Self = "DWARF_types_TemplateAlias"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_TemplateAlias) -> UniquePtr; + fn parameters( + self: &DWARF_types_TemplateAlias, + ) -> UniquePtr; + + type DWARF_types_TemplateAlias_it_parameters; + + fn next( + self: Pin<&mut DWARF_types_TemplateAlias_it_parameters>, + ) -> UniquePtr; + fn size(self: &DWARF_types_TemplateAlias_it_parameters) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/thrown.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/thrown.rs new file mode 100644 index 0000000..fb5e6fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/thrown.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Thrown.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Thrown; + + #[Self = "DWARF_types_Thrown"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Thrown) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/typedef.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/typedef.rs new file mode 100644 index 0000000..5f7b3f7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/typedef.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Typedef.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Typedef; + + #[Self = "DWARF_types_Typedef"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Typedef) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/volatile.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/volatile.rs new file mode 100644 index 0000000..6e9f3ca --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/types/volatile.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/types/Volatile.hpp"); + + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + + type DWARF_types_Volatile; + + #[Self = "DWARF_types_Volatile"] + fn classof(type_: &DWARF_Type) -> bool; + fn underlying_type(self: &DWARF_types_Volatile) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/variable.rs b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/variable.rs new file mode 100644 index 0000000..701fb09 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/dwarf/variable.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/DWARF/Variable.hpp"); + + type DWARF_Scope = crate::dwarf::scope::ffi::DWARF_Scope; + type DWARF_Type = crate::dwarf::type_::ffi::DWARF_Type; + type DebugLocation = crate::debug_location::ffi::DebugLocation; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type DWARF_Variable; + + fn name(self: &DWARF_Variable) -> UniquePtr; + fn linkage_name(self: &DWARF_Variable) -> UniquePtr; + fn address(self: &DWARF_Variable, err: Pin<&mut u32>) -> i64; + fn size(self: &DWARF_Variable, err: Pin<&mut u32>) -> u64; + fn debug_location(self: &DWARF_Variable) -> UniquePtr; + fn is_constexpr(self: &DWARF_Variable) -> bool; + fn is_stack_based(self: &DWARF_Variable) -> bool; + fn get_type(self: &DWARF_Variable) -> UniquePtr; + fn scope(self: &DWARF_Variable) -> UniquePtr; + fn description(self: &DWARF_Variable) -> UniquePtr; + fn to_decl(self: &DWARF_Variable) -> UniquePtr; + fn to_decl_with_opt(self: &DWARF_Variable, opt: &LIEF_DeclOpt) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf.rs new file mode 100644 index 0000000..fbf475a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf.rs @@ -0,0 +1,33 @@ +pub mod binary; +pub mod core_auxv; +pub mod core_file; +pub mod core_pr_ps_info; +pub mod core_pr_status; +pub mod core_sig_info; +pub mod dynamic_entry; +pub mod dynamic_entry_array; +pub mod dynamic_entry_auxiliary; +pub mod dynamic_entry_filter; +pub mod dynamic_entry_flags; +pub mod dynamic_entry_library; +pub mod dynamic_entry_rpath; +pub mod dynamic_entry_run_path; +pub mod dynamic_shared_object; +pub mod gnu_hash; +pub mod header; +pub mod note; +pub mod note_abi; +pub mod note_android_ident; +pub mod note_gnu_property; +pub mod note_qnx_stack; +pub mod relocation; +pub mod section; +pub mod segment; +pub mod symbol; +pub mod symbol_version; +pub mod symbol_version_aux; +pub mod symbol_version_aux_requirement; +pub mod symbol_version_definition; +pub mod symbol_version_requirement; +pub mod sysvhash; +pub mod utils; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/binary.rs new file mode 100644 index 0000000..1dc1e14 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/binary.rs @@ -0,0 +1,365 @@ +#[repr(C)] +pub struct write_config_t { + pub dt_hash: bool, + pub dyn_str: bool, + pub dynamic_section: bool, + pub fini_array: bool, + pub gnu_hash: bool, + pub init_array: bool, + pub interpreter: bool, + pub jmprel: bool, + pub notes: bool, + pub preinit_array: bool, + pub relr: bool, + pub android_rela: bool, + pub rela: bool, + pub static_symtab: bool, + pub sym_verdef: bool, + pub sym_verneed: bool, + pub sym_versym: bool, + pub symtab: bool, + pub coredump_notes: bool, + pub force_relocate: bool, + pub keep_empty_version_requirement: bool, + pub skip_dynamic: bool, +} + +unsafe impl cxx::ExternType for write_config_t { + type Id = cxx::type_id!("ELF_Binary_write_config_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Binary.hpp"); + + type Span = crate::utils::ffi::Span; + type AbstractBinary_it_functions = crate::generic::binary::ffi::AbstractBinary_it_functions; + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + type ELF_DynamicEntryLibrary = + crate::elf::dynamic_entry_library::ffi::ELF_DynamicEntryLibrary; + type ELF_GnuHash = crate::elf::gnu_hash::ffi::ELF_GnuHash; + type ELF_Header = crate::elf::header::ffi::ELF_Header; + type ELF_Note = crate::elf::note::ffi::ELF_Note; + type ELF_Relocation = crate::elf::relocation::ffi::ELF_Relocation; + type ELF_Section = crate::elf::section::ffi::ELF_Section; + type ELF_Segment = crate::elf::segment::ffi::ELF_Segment; + type ELF_Symbol = crate::elf::symbol::ffi::ELF_Symbol; + type ELF_SymbolVersion = crate::elf::symbol_version::ffi::ELF_SymbolVersion; + type ELF_SymbolVersionDefinition = + crate::elf::symbol_version_definition::ffi::ELF_SymbolVersionDefinition; + type ELF_SymbolVersionRequirement = + crate::elf::symbol_version_requirement::ffi::ELF_SymbolVersionRequirement; + type ELF_SysvHash = crate::elf::sysvhash::ffi::ELF_SysvHash; + + type ELF_Binary_write_config_t = crate::elf::binary::write_config_t; + + type LIEF_ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::LIEF_ELF_DynamicEntry; + + type ELF_Binary; + + fn get_content_from_virtual_address( + self: &ELF_Binary, + virtual_address: u64, + size: u64, + ) -> Span; + fn get_overlay(self: &ELF_Binary) -> Span; + #[Self = "ELF_Binary"] + fn parse(path: &CxxString) -> UniquePtr; + #[Self = "ELF_Binary"] + fn parse_with_config(path: &CxxString, config: &ELF_ParserConfig) -> UniquePtr; + #[Self = "ELF_Binary"] + fn parse_from_dump(path: &CxxString, addr: u64) -> UniquePtr; + #[Self = "ELF_Binary"] + fn parse_from_dump_with_config( + path: &CxxString, + addr: u64, + config: &ELF_ParserConfig, + ) -> UniquePtr; + fn header(self: &ELF_Binary) -> UniquePtr; + fn gnu_hash(self: &ELF_Binary) -> UniquePtr; + fn sysv_hash(self: &ELF_Binary) -> UniquePtr; + fn sections(self: &ELF_Binary) -> UniquePtr; + fn segments(self: &ELF_Binary) -> UniquePtr; + fn dynamic_entries(self: &ELF_Binary) -> UniquePtr; + fn dynamic_symbols(self: &ELF_Binary) -> UniquePtr; + fn exported_symbols(self: &ELF_Binary) -> UniquePtr; + fn imported_symbols(self: &ELF_Binary) -> UniquePtr; + fn symtab_symbols(self: &ELF_Binary) -> UniquePtr; + fn notes(self: &ELF_Binary) -> UniquePtr; + fn relocations(self: &ELF_Binary) -> UniquePtr; + fn pltgot_relocations(self: &ELF_Binary) -> UniquePtr; + fn dynamic_relocations(self: &ELF_Binary) -> UniquePtr; + fn object_relocations(self: &ELF_Binary) -> UniquePtr; + fn symbols_version(self: &ELF_Binary) -> UniquePtr; + fn symbols_version_requirement( + self: &ELF_Binary, + ) -> UniquePtr; + fn symbols_version_definition( + self: &ELF_Binary, + ) -> UniquePtr; + fn section_by_name(self: &ELF_Binary, name: &CxxString) -> UniquePtr; + fn relocation_for_symbol(self: &ELF_Binary, name: &CxxString) -> UniquePtr; + fn get_dynamic_symbol(self: &ELF_Binary, name: &CxxString) -> UniquePtr; + fn get_symtab_symbol(self: &ELF_Binary, name: &CxxString) -> UniquePtr; + fn get_library(self: &ELF_Binary, name: &CxxString) -> UniquePtr; + fn section_from_offset( + self: &ELF_Binary, + offset: u64, + skip_nobits: bool, + ) -> UniquePtr; + fn section_from_virtual_address( + self: &ELF_Binary, + address: u64, + skip_nobits: bool, + ) -> UniquePtr; + fn segment_from_virtual_address(self: &ELF_Binary, address: u64) -> UniquePtr; + fn segment_from_offset(self: &ELF_Binary, offset: u64) -> UniquePtr; + fn virtual_address_to_offset( + self: &ELF_Binary, + virtual_address: u64, + error: Pin<&mut u32>, + ) -> u64; + fn virtual_size(self: &ELF_Binary) -> u64; + fn interpreter(self: &ELF_Binary) -> UniquePtr; + fn set_interpreter(self: Pin<&mut ELF_Binary>, name: &CxxString); + fn get_relocated_dynamic_array(self: &ELF_Binary, tag: u64) -> UniquePtr>; + fn is_targeting_android(self: &ELF_Binary) -> bool; + fn add_library( + self: Pin<&mut ELF_Binary>, + library: &CxxString, + ) -> UniquePtr; + fn functions(self: &ELF_Binary) -> UniquePtr; + fn remove_library(self: Pin<&mut ELF_Binary>, name: &CxxString); + fn find_version_requirement( + self: &ELF_Binary, + libname: &CxxString, + ) -> UniquePtr; + fn remove_version_requirement(self: Pin<&mut ELF_Binary>, libname: &CxxString) -> bool; + fn symbols(self: &ELF_Binary) -> UniquePtr; + fn strings(self: &ELF_Binary, min_size: u64) -> UniquePtr>; + fn last_offset_section(self: &ELF_Binary) -> u64; + fn last_offset_segment(self: &ELF_Binary) -> u64; + fn next_virtual_address(self: &ELF_Binary) -> u64; + fn eof_offset(self: &ELF_Binary) -> u64; + fn dtor_functions(self: &ELF_Binary) -> UniquePtr; + fn has_section(self: &ELF_Binary, name: &CxxString) -> bool; + fn has_section_with_offset(self: &ELF_Binary, offset: u64) -> bool; + fn has_section_with_va(self: &ELF_Binary, va: u64) -> bool; + fn has_library(self: &ELF_Binary, name: &CxxString) -> bool; + fn has_dynamic_symbol(self: &ELF_Binary, name: &CxxString) -> bool; + fn has_symtab_symbol(self: &ELF_Binary, name: &CxxString) -> bool; + fn dynsym_idx(self: &ELF_Binary, name: &CxxString) -> i64; + fn symtab_idx(self: &ELF_Binary, name: &CxxString) -> i64; + fn patch_pltgot_by_name(self: Pin<&mut ELF_Binary>, symbol_name: &CxxString, address: u64); + fn add_section( + self: Pin<&mut ELF_Binary>, + section: &ELF_Section, + loaded: bool, + pos: u32, + ) -> UniquePtr; + fn add_dynamic_relocation( + self: Pin<&mut ELF_Binary>, + reloc: &ELF_Relocation, + ) -> UniquePtr; + fn add_pltgot_relocation( + self: Pin<&mut ELF_Binary>, + reloc: &ELF_Relocation, + ) -> UniquePtr; + fn add_symtab_symbol( + self: Pin<&mut ELF_Binary>, + symbol: &ELF_Symbol, + ) -> UniquePtr; + fn add_dynamic_symbol( + self: Pin<&mut ELF_Binary>, + symbol: &ELF_Symbol, + ) -> UniquePtr; + fn add_exported_function( + self: Pin<&mut ELF_Binary>, + address: u64, + name: &CxxString, + ) -> UniquePtr; + fn export_symbol_by_name( + self: Pin<&mut ELF_Binary>, + symbol_name: &CxxString, + value: u64, + ) -> UniquePtr; + fn remove_symtab_symbol_by_name(self: Pin<&mut ELF_Binary>, name: &CxxString); + fn remove_dynamic_symbol_by_name(self: Pin<&mut ELF_Binary>, name: &CxxString); + fn remove_section(self: Pin<&mut ELF_Binary>, section: &ELF_Section, clear: bool); + fn extend_segment( + self: Pin<&mut ELF_Binary>, + segment: &ELF_Segment, + size: u64, + ) -> UniquePtr; + fn extend_section( + self: Pin<&mut ELF_Binary>, + section: &ELF_Section, + size: u64, + ) -> UniquePtr; + fn strip(self: Pin<&mut ELF_Binary>); + fn get_section_idx_by_name(self: &ELF_Binary, name: &CxxString) -> i64; + fn relocate_phdr_table(self: Pin<&mut ELF_Binary>, type_: u32) -> u64; + fn write(self: Pin<&mut ELF_Binary>, output: &CxxString); + fn remove_dynamic_entries_by_tag(self: Pin<&mut ELF_Binary>, tag: u64); + fn remove_dynamic_entry(self: Pin<&mut ELF_Binary>, entry: &ELF_DynamicEntry); + unsafe fn remove_dynamic_entry_from_ptr( + self: Pin<&mut ELF_Binary>, + ptr: *const LIEF_ELF_DynamicEntry, + ); + unsafe fn set_overlay(self: Pin<&mut ELF_Binary>, data: *const u8, size: u64); + fn add_dynamic_entry( + self: Pin<&mut ELF_Binary>, + entry: &ELF_DynamicEntry, + ) -> UniquePtr; + fn relocation_by_addr(self: &ELF_Binary, addr: u64) -> UniquePtr; + fn dynamic_entry_by_tag(self: &ELF_Binary, tag: u64) -> UniquePtr; + fn segment_by_type(self: &ELF_Binary, ty: u64) -> UniquePtr; + fn add_segment(self: Pin<&mut ELF_Binary>, segment: &ELF_Segment) + -> UniquePtr; + fn remove_segment(self: Pin<&mut ELF_Binary>, segment: &ELF_Segment, clear: bool); + fn remove_segments_by_type(self: Pin<&mut ELF_Binary>, ty: u64, clear: bool); + fn has_dynamic_entry_tag(self: &ELF_Binary, tag: u64) -> bool; + fn has_segment_type(self: &ELF_Binary, ty: u64) -> bool; + fn has_note_type(self: &ELF_Binary, ty: u32) -> bool; + fn has_section_type(self: &ELF_Binary, ty: u64) -> bool; + fn get_note_by_type(self: &ELF_Binary, ty: u32) -> UniquePtr; + fn get_section_by_type(self: &ELF_Binary, ty: u64) -> UniquePtr; + fn add_note(self: Pin<&mut ELF_Binary>, note: &ELF_Note) -> UniquePtr; + fn export_symbol_obj( + self: Pin<&mut ELF_Binary>, + symbol: &ELF_Symbol, + ) -> UniquePtr; + fn remove_note(self: Pin<&mut ELF_Binary>, note: &ELF_Note); + fn get_section_idx_by_section(self: &ELF_Binary, section: &ELF_Section) -> i64; + + type ELF_Binary_it_dynamic_entries; + + fn next(self: Pin<&mut ELF_Binary_it_dynamic_entries>) -> UniquePtr; + fn size(self: &ELF_Binary_it_dynamic_entries) -> u64; + + type ELF_Binary_it_dynamic_relocations; + + fn next(self: Pin<&mut ELF_Binary_it_dynamic_relocations>) -> UniquePtr; + fn size(self: &ELF_Binary_it_dynamic_relocations) -> u64; + + type ELF_Binary_it_dynamic_symbols; + + fn next(self: Pin<&mut ELF_Binary_it_dynamic_symbols>) -> UniquePtr; + fn size(self: &ELF_Binary_it_dynamic_symbols) -> u64; + + type ELF_Binary_it_exported_symbols; + + fn next(self: Pin<&mut ELF_Binary_it_exported_symbols>) -> UniquePtr; + fn size(self: &ELF_Binary_it_exported_symbols) -> u64; + + type ELF_Binary_it_imported_symbols; + + fn next(self: Pin<&mut ELF_Binary_it_imported_symbols>) -> UniquePtr; + fn size(self: &ELF_Binary_it_imported_symbols) -> u64; + + type ELF_Binary_it_notes; + + fn next(self: Pin<&mut ELF_Binary_it_notes>) -> UniquePtr; + fn size(self: &ELF_Binary_it_notes) -> u64; + + type ELF_Binary_it_object_relocations; + + fn next(self: Pin<&mut ELF_Binary_it_object_relocations>) -> UniquePtr; + fn size(self: &ELF_Binary_it_object_relocations) -> u64; + + type ELF_Binary_it_pltgot_relocations; + + fn next(self: Pin<&mut ELF_Binary_it_pltgot_relocations>) -> UniquePtr; + fn size(self: &ELF_Binary_it_pltgot_relocations) -> u64; + + type ELF_Binary_it_relocations; + + fn next(self: Pin<&mut ELF_Binary_it_relocations>) -> UniquePtr; + fn size(self: &ELF_Binary_it_relocations) -> u64; + + type ELF_Binary_it_sections; + + fn next(self: Pin<&mut ELF_Binary_it_sections>) -> UniquePtr; + fn size(self: &ELF_Binary_it_sections) -> u64; + + type ELF_Binary_it_segments; + + fn next(self: Pin<&mut ELF_Binary_it_segments>) -> UniquePtr; + fn size(self: &ELF_Binary_it_segments) -> u64; + + type ELF_Binary_it_symbols; + + fn next(self: Pin<&mut ELF_Binary_it_symbols>) -> UniquePtr; + fn size(self: &ELF_Binary_it_symbols) -> u64; + + type ELF_Binary_it_symbols_version; + + fn next(self: Pin<&mut ELF_Binary_it_symbols_version>) -> UniquePtr; + fn size(self: &ELF_Binary_it_symbols_version) -> u64; + + type ELF_Binary_it_symbols_version_definition; + + fn next( + self: Pin<&mut ELF_Binary_it_symbols_version_definition>, + ) -> UniquePtr; + fn size(self: &ELF_Binary_it_symbols_version_definition) -> u64; + + type ELF_Binary_it_symbols_version_requirement; + + fn next( + self: Pin<&mut ELF_Binary_it_symbols_version_requirement>, + ) -> UniquePtr; + fn size(self: &ELF_Binary_it_symbols_version_requirement) -> u64; + + type ELF_Binary_it_symtab_symbols; + + fn next(self: Pin<&mut ELF_Binary_it_symtab_symbols>) -> UniquePtr; + fn size(self: &ELF_Binary_it_symtab_symbols) -> u64; + + fn write_with_config( + self: Pin<&mut ELF_Binary>, + output: &CxxString, + config: &ELF_Binary_write_config_t, + ); + + fn write_to_bytes(self: Pin<&mut ELF_Binary>) -> UniquePtr>; + + fn write_to_bytes_with_config( + self: Pin<&mut ELF_Binary>, + config: &ELF_Binary_write_config_t, + ) -> UniquePtr>; + + type ELF_ParserConfig; + + #[Self = "ELF_ParserConfig"] + fn create() -> UniquePtr; + fn set_parse_relocations(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_parse_dyn_symbols(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_parse_symtab_symbols(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_parse_symbol_versions(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_parse_notes(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_parse_overlay(self: Pin<&mut ELF_ParserConfig>, value: bool); + fn set_count_mtd(self: Pin<&mut ELF_ParserConfig>, value: u32); + fn set_page_size(self: Pin<&mut ELF_ParserConfig>, value: u64); + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_auxv.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_auxv.rs new file mode 100644 index 0000000..9c7bcf5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_auxv.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/CoreAuxv.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_CoreAuxv; + + #[Self = "ELF_CoreAuxv"] + fn classof(note: &ELF_Note) -> bool; + fn values(self: &ELF_CoreAuxv) -> UniquePtr>; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_file.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_file.rs new file mode 100644 index 0000000..6e60ebe --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_file.rs @@ -0,0 +1,30 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/CoreFile.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_CoreFile; + + #[Self = "ELF_CoreFile"] + fn classof(note: &ELF_Note) -> bool; + fn count(self: &ELF_CoreFile) -> u64; + fn files(self: &ELF_CoreFile) -> UniquePtr; + + type ELF_CoreFile_entry; + + fn start(self: &ELF_CoreFile_entry) -> u64; + fn end(self: &ELF_CoreFile_entry) -> u64; + fn path(self: &ELF_CoreFile_entry) -> UniquePtr; + fn file_ofs(self: &ELF_CoreFile_entry) -> u64; + + type ELF_CoreFile_it_files; + + fn next(self: Pin<&mut ELF_CoreFile_it_files>) -> UniquePtr; + fn size(self: &ELF_CoreFile_it_files) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_ps_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_ps_info.rs new file mode 100644 index 0000000..3e084cc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_ps_info.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/CorePrPsInfo.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_CorePrPsInfo; + + #[Self = "ELF_CorePrPsInfo"] + fn classof(note: &ELF_Note) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_status.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_status.rs new file mode 100644 index 0000000..1541e43 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_pr_status.rs @@ -0,0 +1,58 @@ +#[repr(C)] +pub struct Status { + pub signo: i32, + pub code: i32, + pub err: i32, + + pub cursig: u16, + pub reserved: u16, + + pub sigpend: u64, + pub sighold: u64, + + pub pid: i32, + pub ppid: i32, + pub pgrp: i32, + pub sid: i32, + + pub utime_sec: u64, + pub utime_usec: u64, + + pub stime_sec: u64, + pub stime_usec: u64, + + pub cutime_sec: u64, + pub cutime_usec: u64, + + pub cstime_sec: u64, + pub cstime_usec: u64, +} + +unsafe impl cxx::ExternType for Status { + type Id = cxx::type_id!("ELF_CorePrStatus_Status"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/CorePrStatus.hpp"); + + type Span = crate::utils::ffi::Span; + type ELF_Note = crate::elf::note::ffi::ELF_Note; + type ELF_CorePrStatus_Status = crate::elf::core_pr_status::Status; + + type ELF_CorePrStatus; + + #[Self = "ELF_CorePrStatus"] + fn classof(note: &ELF_Note) -> bool; + fn architecture(self: &ELF_CorePrStatus) -> u32; + fn pc(self: &ELF_CorePrStatus, err: Pin<&mut u32>) -> u64; + fn sp(self: &ELF_CorePrStatus, err: Pin<&mut u32>) -> u64; + fn return_value(self: &ELF_CorePrStatus, err: Pin<&mut u32>) -> u64; + fn register_values(self: &ELF_CorePrStatus) -> UniquePtr>; + fn status(self: &ELF_CorePrStatus) -> ELF_CorePrStatus_Status; + + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_sig_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_sig_info.rs new file mode 100644 index 0000000..c94f25c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/core_sig_info.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/CoreSigInfo.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_CoreSigInfo; + + #[Self = "ELF_CoreSigInfo"] + fn classof(note: &ELF_Note) -> bool; + fn signo(self: &ELF_CoreSigInfo, err: Pin<&mut u32>) -> i32; + fn sigcode(self: &ELF_CoreSigInfo, err: Pin<&mut u32>) -> i32; + fn sigerrno(self: &ELF_CoreSigInfo, err: Pin<&mut u32>) -> i32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry.rs new file mode 100644 index 0000000..23f99fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntry.hpp"); + + type ELF_DynamicEntry; + + type LIEF_ELF_DynamicEntry; + + #[Self = "ELF_DynamicEntry"] + fn create(tag: u64) -> UniquePtr; + fn tag(self: &ELF_DynamicEntry) -> u64; + fn value(self: &ELF_DynamicEntry) -> u64; + fn set_value(self: Pin<&mut ELF_DynamicEntry>, value: u64); + fn to_string(self: &ELF_DynamicEntry) -> UniquePtr; + fn raw_ptr(self: &ELF_DynamicEntry) -> *const LIEF_ELF_DynamicEntry; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_array.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_array.rs new file mode 100644 index 0000000..8267489 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_array.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryArray.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryArray; + + #[Self = "ELF_DynamicEntryArray"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn array(self: &ELF_DynamicEntryArray) -> UniquePtr>; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_auxiliary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_auxiliary.rs new file mode 100644 index 0000000..1dcb707 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_auxiliary.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryAuxiliary.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryAuxiliary; + + #[Self = "ELF_DynamicEntryAuxiliary"] + fn create(name: &CxxString) -> UniquePtr; + #[Self = "ELF_DynamicEntryAuxiliary"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn name(self: &ELF_DynamicEntryAuxiliary) -> UniquePtr; + fn set_name(self: Pin<&mut ELF_DynamicEntryAuxiliary>, name: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_filter.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_filter.rs new file mode 100644 index 0000000..bed717e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_filter.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryFilter.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryFilter; + + #[Self = "ELF_DynamicEntryFilter"] + fn create(name: &CxxString) -> UniquePtr; + #[Self = "ELF_DynamicEntryFilter"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn name(self: &ELF_DynamicEntryFilter) -> UniquePtr; + fn set_name(self: Pin<&mut ELF_DynamicEntryFilter>, name: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_flags.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_flags.rs new file mode 100644 index 0000000..3b4d7ad --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_flags.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryFlags.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryFlags; + + #[Self = "ELF_DynamicEntryFlags"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + #[Self = "ELF_DynamicEntryFlags"] + fn create_dt_flag(value: u64) -> UniquePtr; + #[Self = "ELF_DynamicEntryFlags"] + fn create_dt_flag_1(value: u64) -> UniquePtr; + fn flags(self: &ELF_DynamicEntryFlags) -> u64; + fn add_flag(self: Pin<&mut ELF_DynamicEntryFlags>, f: u64); + fn remove_flag(self: Pin<&mut ELF_DynamicEntryFlags>, f: u64); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_library.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_library.rs new file mode 100644 index 0000000..3c44d60 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_library.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryLibrary.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryLibrary; + + #[Self = "ELF_DynamicEntryLibrary"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn name(self: &ELF_DynamicEntryLibrary) -> UniquePtr; + fn set_name(self: Pin<&mut ELF_DynamicEntryLibrary>, name: &CxxString); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_rpath.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_rpath.rs new file mode 100644 index 0000000..ba85e17 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_rpath.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryRpath.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryRpath; + + #[Self = "ELF_DynamicEntryRpath"] + fn create(name: &CxxString) -> UniquePtr; + #[Self = "ELF_DynamicEntryRpath"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn rpath(self: &ELF_DynamicEntryRpath) -> UniquePtr; + fn paths(self: &ELF_DynamicEntryRpath) -> UniquePtr>; + fn insert(self: Pin<&mut ELF_DynamicEntryRpath>, pos: u32, name: &CxxString); + fn append(self: Pin<&mut ELF_DynamicEntryRpath>, name: &CxxString); + fn remove(self: Pin<&mut ELF_DynamicEntryRpath>, path: &CxxString); + fn set_rpath(self: Pin<&mut ELF_DynamicEntryRpath>, path: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_run_path.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_run_path.rs new file mode 100644 index 0000000..72897c9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_entry_run_path.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicEntryRunPath.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicEntryRunPath; + + #[Self = "ELF_DynamicEntryRunPath"] + fn create(name: &CxxString) -> UniquePtr; + #[Self = "ELF_DynamicEntryRunPath"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn runpath(self: &ELF_DynamicEntryRunPath) -> UniquePtr; + fn paths(self: &ELF_DynamicEntryRunPath) -> UniquePtr>; + fn insert(self: Pin<&mut ELF_DynamicEntryRunPath>, pos: u32, name: &CxxString); + fn append(self: Pin<&mut ELF_DynamicEntryRunPath>, name: &CxxString); + fn remove(self: Pin<&mut ELF_DynamicEntryRunPath>, path: &CxxString); + fn set_runpath(self: Pin<&mut ELF_DynamicEntryRunPath>, path: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_shared_object.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_shared_object.rs new file mode 100644 index 0000000..b314762 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/dynamic_shared_object.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/DynamicSharedObject.hpp"); + + type ELF_DynamicEntry = crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; + + type ELF_DynamicSharedObject; + + #[Self = "ELF_DynamicSharedObject"] + fn create(name: &CxxString) -> UniquePtr; + #[Self = "ELF_DynamicSharedObject"] + fn classof(entry: &ELF_DynamicEntry) -> bool; + fn name(self: &ELF_DynamicSharedObject) -> UniquePtr; + fn set_name(self: Pin<&mut ELF_DynamicSharedObject>, name: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/gnu_hash.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/gnu_hash.rs new file mode 100644 index 0000000..cdddeea --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/gnu_hash.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/GnuHash.hpp"); + + type ELF_GnuHash; + + fn nb_buckets(self: &ELF_GnuHash) -> u32; + fn symbol_index(self: &ELF_GnuHash) -> u32; + fn shift2(self: &ELF_GnuHash) -> u32; + fn maskwords(self: &ELF_GnuHash) -> u32; + fn bloom_filters(self: &ELF_GnuHash) -> UniquePtr>; + fn buckets(self: &ELF_GnuHash) -> UniquePtr>; + fn hash_values(self: &ELF_GnuHash) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/header.rs new file mode 100644 index 0000000..6c791fd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/header.rs @@ -0,0 +1,31 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Header.hpp"); + + type ELF_Header; + + fn entrypoint(self: &ELF_Header) -> u64; + fn file_type(self: &ELF_Header) -> u32; + fn machine_type(self: &ELF_Header) -> u32; + fn object_file_version(self: &ELF_Header) -> u32; + fn identity_class(self: &ELF_Header) -> u32; + fn identity_os_abi(self: &ELF_Header) -> u32; + fn identity_version(self: &ELF_Header) -> u32; + fn identity_data(self: &ELF_Header) -> u32; + fn is_mips_n64(self: &ELF_Header) -> bool; + fn identity_abi_version(self: &ELF_Header) -> u32; + fn program_headers_offset(self: &ELF_Header) -> u64; + fn section_headers_offset(self: &ELF_Header) -> u64; + fn processor_flag(self: &ELF_Header) -> u32; + fn header_size(self: &ELF_Header) -> u32; + fn program_header_size(self: &ELF_Header) -> u32; + fn numberof_segments(self: &ELF_Header) -> u32; + fn section_header_size(self: &ELF_Header) -> u32; + fn numberof_sections(self: &ELF_Header) -> u32; + fn section_name_table_idx(self: &ELF_Header) -> u32; + fn set_osabi(self: Pin<&mut ELF_Header>, value: u32); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/note.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note.rs new file mode 100644 index 0000000..d379171 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Note.hpp"); + + type Span = crate::utils::ffi::Span; + type ELF_Note; + + fn name(self: &ELF_Note) -> UniquePtr; + fn get_type(self: &ELF_Note) -> u32; + fn original_type(self: &ELF_Note) -> u32; + fn size(self: &ELF_Note) -> u64; + fn description(self: &ELF_Note) -> Span; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_abi.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_abi.rs new file mode 100644 index 0000000..5b8dc69 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_abi.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/NoteAbi.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_NoteAbi; + + #[Self = "ELF_NoteAbi"] + fn classof(note: &ELF_Note) -> bool; + fn abi(self: &ELF_NoteAbi) -> u32; + fn version(self: &ELF_NoteAbi) -> UniquePtr>; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_android_ident.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_android_ident.rs new file mode 100644 index 0000000..f5e020c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_android_ident.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/NoteAndroidIdent.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_AndroidIdent; + + #[Self = "ELF_AndroidIdent"] + fn classof(note: &ELF_Note) -> bool; + fn sdk_version(self: &ELF_AndroidIdent) -> u32; + fn ndk_version(self: &ELF_AndroidIdent) -> UniquePtr; + fn ndk_build_number(self: &ELF_AndroidIdent) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_gnu_property.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_gnu_property.rs new file mode 100644 index 0000000..5fe51ae --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_gnu_property.rs @@ -0,0 +1,85 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/NoteGnuProperty.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_NoteGnuProperty; + + #[Self = "ELF_NoteGnuProperty"] + fn classof(note: &ELF_Note) -> bool; + fn properties(self: &ELF_NoteGnuProperty) -> UniquePtr; + fn find(self: &ELF_NoteGnuProperty, type_: u32) -> UniquePtr; + + type ELF_NoteGnuProperty_AArch64Feature; + + #[Self = "ELF_NoteGnuProperty_AArch64Feature"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn features(self: &ELF_NoteGnuProperty_AArch64Feature) -> UniquePtr>; + + type ELF_NoteGnuProperty_AArch64PAuth; + + #[Self = "ELF_NoteGnuProperty_AArch64PAuth"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn platform(self: &ELF_NoteGnuProperty_AArch64PAuth) -> u64; + fn version(self: &ELF_NoteGnuProperty_AArch64PAuth) -> u64; + + type ELF_NoteGnuProperty_Generic; + + #[Self = "ELF_NoteGnuProperty_Generic"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn raw_type(self: &ELF_NoteGnuProperty_Generic) -> u32; + + type ELF_NoteGnuProperty_Needed; + + #[Self = "ELF_NoteGnuProperty_Needed"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn needs(self: &ELF_NoteGnuProperty_Needed) -> UniquePtr>; + + type ELF_NoteGnuProperty_NoteNoCopyOnProtected; + + #[Self = "ELF_NoteGnuProperty_NoteNoCopyOnProtected"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + + type ELF_NoteGnuProperty_Property; + + fn get_type(self: &ELF_NoteGnuProperty_Property) -> u32; + + type ELF_NoteGnuProperty_StackSize; + + #[Self = "ELF_NoteGnuProperty_StackSize"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn stack_size(self: &ELF_NoteGnuProperty_StackSize) -> u64; + + type ELF_NoteGnuProperty_X86Features; + + #[Self = "ELF_NoteGnuProperty_X86Features"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn features(self: &ELF_NoteGnuProperty_X86Features) -> UniquePtr>; + + type ELF_NoteGnuProperty_X86ISA; + + #[Self = "ELF_NoteGnuProperty_X86ISA"] + fn classof(prop: &ELF_NoteGnuProperty_Property) -> bool; + fn values(self: &ELF_NoteGnuProperty_X86ISA) -> UniquePtr>; + + type ELF_NoteGnuProperty_it_properties; + + fn next( + self: Pin<&mut ELF_NoteGnuProperty_it_properties>, + ) -> UniquePtr; + fn size(self: &ELF_NoteGnuProperty_it_properties) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_qnx_stack.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_qnx_stack.rs new file mode 100644 index 0000000..6dfecdc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/note_qnx_stack.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/NoteQNXStack.hpp"); + + type ELF_Note = crate::elf::note::ffi::ELF_Note; + + type ELF_QNXStack; + + #[Self = "ELF_QNXStack"] + fn classof(note: &ELF_Note) -> bool; + fn stack_size(self: &ELF_QNXStack) -> u32; + fn stack_allocated(self: &ELF_QNXStack) -> u32; + fn is_executable(self: &ELF_QNXStack) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/relocation.rs new file mode 100644 index 0000000..2803e1c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/relocation.rs @@ -0,0 +1,26 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Relocation.hpp"); + + type ELF_Section = crate::elf::section::ffi::ELF_Section; + type ELF_Symbol = crate::elf::symbol::ffi::ELF_Symbol; + + type ELF_Relocation; + + fn addend(self: &ELF_Relocation) -> i64; + fn get_type(self: &ELF_Relocation) -> u32; + fn is_rela(self: &ELF_Relocation) -> bool; + fn is_rel(self: &ELF_Relocation) -> bool; + fn info(self: &ELF_Relocation) -> u32; + fn architecture(self: &ELF_Relocation) -> u32; + fn purpose(self: &ELF_Relocation) -> u32; + fn encoding(self: &ELF_Relocation) -> u32; + fn symbol(self: &ELF_Relocation) -> UniquePtr; + fn section(self: &ELF_Relocation) -> UniquePtr; + fn symbol_table(self: &ELF_Relocation) -> UniquePtr; + fn resolve(self: &ELF_Relocation, base_address: u64, err: Pin<&mut u32>) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/section.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/section.rs new file mode 100644 index 0000000..563986b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/section.rs @@ -0,0 +1,32 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Section.hpp"); + + type Span = crate::utils::ffi::Span; + type ELF_Section; + + #[Self = "ELF_Section"] + fn create() -> UniquePtr; + #[Self = "ELF_Section"] + fn create_with_name(name: &CxxString) -> UniquePtr; + #[Self = "ELF_Section"] + unsafe fn create_with_content( + name: &CxxString, + buffer: *const u8, + size: usize, + ) -> UniquePtr; + fn get_type(self: &ELF_Section) -> u64; + fn flags(self: &ELF_Section) -> u64; + fn alignment(self: &ELF_Section) -> u64; + fn information(self: &ELF_Section) -> u64; + fn entry_size(self: &ELF_Section) -> u64; + fn link(self: &ELF_Section) -> u64; + fn file_offset(self: &ELF_Section) -> u64; + fn original_size(self: &ELF_Section) -> u64; + fn content(self: &ELF_Section) -> Span; + fn to_string(self: &ELF_Section) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/segment.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/segment.rs new file mode 100644 index 0000000..ec300fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/segment.rs @@ -0,0 +1,33 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Segment.hpp"); + + type Span = crate::utils::ffi::Span; + type ELF_Segment; + + fn content(self: &ELF_Segment) -> Span; + #[Self = "ELF_Segment"] + fn create() -> UniquePtr; + fn flags(self: &ELF_Segment) -> u32; + fn file_offset(self: &ELF_Segment) -> u64; + fn virtual_address(self: &ELF_Segment) -> u64; + fn physical_address(self: &ELF_Segment) -> u64; + fn physical_size(self: &ELF_Segment) -> u64; + fn virtual_size(self: &ELF_Segment) -> u64; + fn alignment(self: &ELF_Segment) -> u64; + fn set_type(self: Pin<&mut ELF_Segment>, ty: u64); + fn fill(self: Pin<&mut ELF_Segment>, c: i8); + fn clear(self: Pin<&mut ELF_Segment>); + fn to_string(self: &ELF_Segment) -> UniquePtr; + fn stype(self: &ELF_Segment) -> u64; + fn set_flags(self: Pin<&mut ELF_Segment>, value: u32); + fn set_file_offset(self: Pin<&mut ELF_Segment>, value: u64); + fn set_virtual_address(self: Pin<&mut ELF_Segment>, value: u64); + fn set_physical_address(self: Pin<&mut ELF_Segment>, value: u64); + fn set_virtual_size(self: Pin<&mut ELF_Segment>, value: u64); + fn set_alignment(self: Pin<&mut ELF_Segment>, value: u64); + unsafe fn set_content(self: Pin<&mut ELF_Segment>, ptr: *const u8, size: u64); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol.rs new file mode 100644 index 0000000..fb7e7d1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Symbol.hpp"); + + type ELF_Section = crate::elf::section::ffi::ELF_Section; + type ELF_SymbolVersion = crate::elf::symbol_version::ffi::ELF_SymbolVersion; + + type ELF_Symbol; + + fn get_type(self: &ELF_Symbol) -> u32; + fn binding(self: &ELF_Symbol) -> u32; + fn information(self: &ELF_Symbol) -> u8; + fn other(self: &ELF_Symbol) -> u8; + fn section_idx(self: &ELF_Symbol) -> u16; + fn visibility(self: &ELF_Symbol) -> u32; + fn section(self: &ELF_Symbol) -> UniquePtr; + fn symbol_version(self: &ELF_Symbol) -> UniquePtr; + fn demangled_name(self: &ELF_Symbol) -> UniquePtr; + fn to_string(self: &ELF_Symbol) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version.rs new file mode 100644 index 0000000..bc73f28 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/SymbolVersion.hpp"); + + type ELF_SymbolVersionAux = crate::elf::symbol_version_aux::ffi::ELF_SymbolVersionAux; + + type ELF_SymbolVersion; + + fn value(self: &ELF_SymbolVersion) -> u16; + fn symbol_version_auxiliary(self: &ELF_SymbolVersion) -> UniquePtr; + fn drop_version(self: Pin<&mut ELF_SymbolVersion>, value: u16); + fn as_local(self: Pin<&mut ELF_SymbolVersion>); + fn as_global(self: Pin<&mut ELF_SymbolVersion>); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux.rs new file mode 100644 index 0000000..b9559fb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux.rs @@ -0,0 +1,12 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/SymbolVersionAux.hpp"); + + type ELF_SymbolVersionAux; + + fn name(self: &ELF_SymbolVersionAux) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux_requirement.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux_requirement.rs new file mode 100644 index 0000000..fe1bfcb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_aux_requirement.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/SymbolVersionAuxRequirement.hpp"); + + type ELF_SymbolVersionAuxRequirement; + + fn hash(self: &ELF_SymbolVersionAuxRequirement) -> u32; + fn flags(self: &ELF_SymbolVersionAuxRequirement) -> u16; + fn other(self: &ELF_SymbolVersionAuxRequirement) -> u16; + fn name(self: &ELF_SymbolVersionAuxRequirement) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_definition.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_definition.rs new file mode 100644 index 0000000..a038893 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_definition.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/SymbolVersionDefinition.hpp"); + + type ELF_SymbolVersionAux = crate::elf::symbol_version_aux::ffi::ELF_SymbolVersionAux; + + type ELF_SymbolVersionDefinition; + + fn version(self: &ELF_SymbolVersionDefinition) -> u16; + fn flags(self: &ELF_SymbolVersionDefinition) -> u16; + fn ndx(self: &ELF_SymbolVersionDefinition) -> u16; + fn hash(self: &ELF_SymbolVersionDefinition) -> u32; + fn sym_aux( + self: &ELF_SymbolVersionDefinition, + ) -> UniquePtr; + + type ELF_SymbolVersionDefinition_it_auxiliary_symbols; + + fn next( + self: Pin<&mut ELF_SymbolVersionDefinition_it_auxiliary_symbols>, + ) -> UniquePtr; + fn size(self: &ELF_SymbolVersionDefinition_it_auxiliary_symbols) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_requirement.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_requirement.rs new file mode 100644 index 0000000..3d5509f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/symbol_version_requirement.rs @@ -0,0 +1,38 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/SymbolVersionRequirement.hpp"); + + type ELF_SymbolVersionAuxRequirement = + crate::elf::symbol_version_aux_requirement::ffi::ELF_SymbolVersionAuxRequirement; + + type ELF_SymbolVersionRequirement; + + fn version(self: &ELF_SymbolVersionRequirement) -> u16; + fn cnt(self: &ELF_SymbolVersionRequirement) -> u32; + fn name(self: &ELF_SymbolVersionRequirement) -> UniquePtr; + fn auxiliary_symbols( + self: &ELF_SymbolVersionRequirement, + ) -> UniquePtr; + fn set_name(self: Pin<&mut ELF_SymbolVersionRequirement>, name: &CxxString); + fn find_aux( + self: &ELF_SymbolVersionRequirement, + name: &CxxString, + ) -> UniquePtr; + fn remove_aux_requirement_by_name( + self: Pin<&mut ELF_SymbolVersionRequirement>, + name: &CxxString, + ) -> bool; + fn set_version(self: Pin<&mut ELF_SymbolVersionRequirement>, version: u16); + + type ELF_SymbolVersionRequirement_it_auxiliary_symbols; + + fn next( + self: Pin<&mut ELF_SymbolVersionRequirement_it_auxiliary_symbols>, + ) -> UniquePtr; + fn size(self: &ELF_SymbolVersionRequirement_it_auxiliary_symbols) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/sysvhash.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/sysvhash.rs new file mode 100644 index 0000000..80b64e3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/sysvhash.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/Sysvhash.hpp"); + + type ELF_SysvHash; + + fn nbucket(self: &ELF_SysvHash) -> u32; + fn nchain(self: &ELF_SysvHash) -> u32; + fn buckets(self: &ELF_SysvHash) -> UniquePtr>; + fn chains(self: &ELF_SysvHash) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/elf/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/elf/utils.rs new file mode 100644 index 0000000..330be15 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/elf/utils.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ELF/utils.hpp"); + + type ELF_Binary = crate::elf::binary::ffi::ELF_Binary; + type ELF_Utils; + + #[Self = "ELF_Utils"] + fn is_elf(file: &CxxString) -> bool; + #[Self = "ELF_Utils"] + unsafe fn check_layout(bin: &ELF_Binary, error: *mut CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic.rs new file mode 100644 index 0000000..6d60b3d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic.rs @@ -0,0 +1,6 @@ +pub mod binary; +pub mod debug_info; +pub mod function; +pub mod relocation; +pub mod section; +pub mod symbol; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/binary.rs new file mode 100644 index 0000000..3ac0fef --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/binary.rs @@ -0,0 +1,91 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/Binary.hpp"); + + type AbstracDebugInfo = crate::generic::debug_info::ffi::AbstracDebugInfo; + type AbstractFunction = crate::generic::function::ffi::AbstractFunction; + type AssemblerConfig_r = crate::asm::config::AssemblerConfig_r; + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + + type AbstractBinary; + + fn entrypoint(self: &AbstractBinary) -> u64; + fn imagebase(self: &AbstractBinary) -> u64; + fn virtual_size(self: &AbstractBinary) -> u64; + fn original_size(self: &AbstractBinary) -> u64; + fn is_pie(self: &AbstractBinary) -> bool; + fn has_nx(self: &AbstractBinary) -> bool; + fn offset_to_virtual_address( + self: &AbstractBinary, + offset: u64, + slide: u64, + err: Pin<&mut u32>, + ) -> u64; + fn debug_info(self: &AbstractBinary) -> UniquePtr; + fn disassemble( + self: &AbstractBinary, + addr: u64, + size: u64, + ) -> UniquePtr; + fn disassemble_function( + self: &AbstractBinary, + function: &CxxString, + ) -> UniquePtr; + fn assemble( + self: Pin<&mut AbstractBinary>, + address: u64, + Asm: &CxxString, + ) -> UniquePtr>; + fn assemble_with_config( + self: Pin<&mut AbstractBinary>, + address: u64, + Asm: &CxxString, + ffi_config: &AssemblerConfig_r, + ) -> UniquePtr>; + fn load_debug_info( + self: Pin<&mut AbstractBinary>, + file: &CxxString, + ) -> UniquePtr; + fn page_size(self: &AbstractBinary) -> u64; + unsafe fn patch_address_bytes( + self: Pin<&mut AbstractBinary>, + address: u64, + patch_value: *const u8, + size: u64, + ); + fn patch_address_value( + self: Pin<&mut AbstractBinary>, + address: u64, + patch_value: u64, + size: u64, + ); + fn get_u8(self: &AbstractBinary, addr: u64, err: Pin<&mut u32>) -> u8; + fn get_u16(self: &AbstractBinary, addr: u64, err: Pin<&mut u32>) -> u16; + fn get_u32(self: &AbstractBinary, addr: u64, err: Pin<&mut u32>) -> u32; + fn get_u64(self: &AbstractBinary, addr: u64, err: Pin<&mut u32>) -> u64; + fn disassemble_address( + self: &AbstractBinary, + addr: u64, + ) -> UniquePtr; + unsafe fn disassemble_buffer( + self: &AbstractBinary, + ptr: *const u8, + size: u64, + addr: u64, + ) -> UniquePtr; + + type AbstractBinary_it_functions; + + fn next(self: Pin<&mut AbstractBinary_it_functions>) -> UniquePtr; + fn size(self: &AbstractBinary_it_functions) -> u64; + + type AbstractBinary_it_instructions; + + fn next(self: Pin<&mut AbstractBinary_it_instructions>) -> UniquePtr; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/debug_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/debug_info.rs new file mode 100644 index 0000000..0cddc80 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/debug_info.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/DebugInfo.hpp"); + + type AbstracDebugInfo; + + fn find_function_address( + self: &AbstracDebugInfo, + name: &CxxString, + is_set: Pin<&mut u32>, + ) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/function.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/function.rs new file mode 100644 index 0000000..965e96e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/function.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/Function.hpp"); + + type AbstractFunction; + + fn address(self: &AbstractFunction) -> u64; + fn flags(self: &AbstractFunction) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/relocation.rs new file mode 100644 index 0000000..4cb1e5e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/relocation.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/Relocation.hpp"); + + type AbstractRelocation; + + fn size(self: &AbstractRelocation) -> u64; + fn address(self: &AbstractRelocation) -> u64; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/section.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/section.rs new file mode 100644 index 0000000..bbe0f53 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/section.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/Section.hpp"); + + type Span = crate::utils::ffi::Span; + type AbstractSection; + + fn name(self: &AbstractSection) -> UniquePtr; + fn content(self: &AbstractSection) -> Span; + fn size(self: &AbstractSection) -> u64; + fn offset(self: &AbstractSection) -> u64; + fn virtual_address(self: &AbstractSection) -> u64; + fn set_name(self: Pin<&mut AbstractSection>, name: &CxxString); + fn set_size(self: Pin<&mut AbstractSection>, size: u64); + unsafe fn set_content(self: Pin<&mut AbstractSection>, buffer: *const u8, size: usize); + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/generic/symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/generic/symbol.rs new file mode 100644 index 0000000..19f204f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/generic/symbol.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Abstract/Symbol.hpp"); + + type AbstractSymbol; + + fn name(self: &AbstractSymbol) -> UniquePtr; + fn size(self: &AbstractSymbol) -> u64; + fn value(self: &AbstractSymbol) -> u64; + fn set_name(self: Pin<&mut AbstractSymbol>, name: &CxxString); + fn set_size(self: Pin<&mut AbstractSymbol>, sz: u64); + fn set_value(self: Pin<&mut AbstractSymbol>, value: u64); + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/lib.rs b/vendor/lief/api/rust/crates/lief-ffi/src/lib.rs new file mode 100644 index 0000000..d5d9ee4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/lib.rs @@ -0,0 +1,1730 @@ +//! lief-ffi: low-level FFI bindings to LIEF (cxx-based). +//! +//! Generated bridge surface. Manual additions belong below the +//! re-export block. + +pub mod asm; +pub mod coff; +pub mod debug_decl_opt; +pub mod debug_location; +pub mod dsc; +pub mod dwarf; +pub mod elf; +pub mod generic; +pub mod logging; +pub mod macho; +pub mod objc; +pub mod pdb; +pub mod pe; +pub mod runtime; +pub mod stream; +pub mod utils; + +// Re-exports of FFI types so the high-level `lief` crate can access +// them via the flat `lief_ffi::` path. +pub use crate::asm::aarch64::instruction::ffi::asm_aarch64_Instruction; +pub use crate::asm::aarch64::instruction::ffi::asm_aarch64_Instruction_it_operands; +pub use crate::asm::aarch64::operand::ffi::asm_aarch64_Operand; +pub use crate::asm::aarch64::operands::immediate::ffi::asm_aarch64_operands_Immediate; +pub use crate::asm::aarch64::operands::memory::ffi::asm_aarch64_operands_Memory; +pub use crate::asm::aarch64::operands::pc_relative::ffi::asm_aarch64_operands_PCRelative; +pub use crate::asm::aarch64::operands::register::ffi::asm_aarch64_operands_Register; +pub use crate::asm::arm::instruction::ffi::asm_arm_Instruction; +pub use crate::asm::config::AssemblerConfig_r; +pub use crate::asm::ebpf::instruction::ffi::asm_ebpf_Instruction; +pub use crate::asm::ebpf::instruction::ffi::asm_ebpf_Instruction_it_operands; +pub use crate::asm::ebpf::operand::ffi::asm_ebpf_Operand; +pub use crate::asm::ebpf::operands::immediate::ffi::asm_ebpf_operands_Immediate; +pub use crate::asm::ebpf::operands::memory::ffi::asm_ebpf_operands_Memory; +pub use crate::asm::ebpf::operands::pc_relative::ffi::asm_ebpf_operands_PCRelative; +pub use crate::asm::ebpf::operands::register::ffi::asm_ebpf_operands_Register; +pub use crate::asm::instruction::ffi::asm_Instruction; +pub use crate::asm::mips::instruction::ffi::asm_mips_Instruction; +pub use crate::asm::mips::instruction::ffi::asm_mips_Instruction_it_operands; +pub use crate::asm::mips::operand::ffi::asm_mips_Operand; +pub use crate::asm::mips::operands::immediate::ffi::asm_mips_operands_Immediate; +pub use crate::asm::mips::operands::memory::ffi::asm_mips_operands_Memory; +pub use crate::asm::mips::operands::pc_relative::ffi::asm_mips_operands_PCRelative; +pub use crate::asm::mips::operands::register::ffi::asm_mips_operands_Register; +pub use crate::asm::powerpc::instruction::ffi::asm_powerpc_Instruction; +pub use crate::asm::powerpc::instruction::ffi::asm_powerpc_Instruction_it_operands; +pub use crate::asm::powerpc::operand::ffi::asm_powerpc_Operand; +pub use crate::asm::powerpc::operands::immediate::ffi::asm_powerpc_operands_Immediate; +pub use crate::asm::powerpc::operands::memory::ffi::asm_powerpc_operands_Memory; +pub use crate::asm::powerpc::operands::pc_relative::ffi::asm_powerpc_operands_PCRelative; +pub use crate::asm::powerpc::operands::register::ffi::asm_powerpc_operands_Register; +pub use crate::asm::riscv::instruction::ffi::asm_riscv_Instruction; +pub use crate::asm::riscv::instruction::ffi::asm_riscv_Instruction_it_operands; +pub use crate::asm::riscv::operand::ffi::asm_riscv_Operand; +pub use crate::asm::riscv::operands::immediate::ffi::asm_riscv_operands_Immediate; +pub use crate::asm::riscv::operands::memory::ffi::asm_riscv_operands_Memory; +pub use crate::asm::riscv::operands::pc_relative::ffi::asm_riscv_operands_PCRelative; +pub use crate::asm::riscv::operands::register::ffi::asm_riscv_operands_Register; +pub use crate::asm::x86::instruction::ffi::asm_x86_Instruction; +pub use crate::asm::x86::instruction::ffi::asm_x86_Instruction_it_operands; +pub use crate::asm::x86::operand::ffi::asm_x86_Operand; +pub use crate::asm::x86::operands::immediate::ffi::asm_x86_operands_Immediate; +pub use crate::asm::x86::operands::memory::ffi::asm_x86_operands_Memory; +pub use crate::asm::x86::operands::pc_relative::ffi::asm_x86_operands_PCRelative; +pub use crate::asm::x86::operands::register::ffi::asm_x86_operands_Register; +pub use crate::coff::auxiliary_symbol::ffi::COFF_AuxiliarySymbol; +pub use crate::coff::auxiliary_symbols::auxiliary_clr_token::ffi::COFF_AuxiliaryCLRToken; +pub use crate::coff::auxiliary_symbols::auxiliary_file::ffi::COFF_AuxiliaryFile; +pub use crate::coff::auxiliary_symbols::auxiliary_function_definition::ffi::COFF_AuxiliaryFunctionDefinition; +pub use crate::coff::auxiliary_symbols::auxiliary_section_definition::ffi::COFF_AuxiliarySectionDefinition; +pub use crate::coff::auxiliary_symbols::auxiliary_weak_external::ffi::COFF_AuxiliaryWeakExternal; +pub use crate::coff::auxiliary_symbols::auxiliarybf_andef_symbol::ffi::COFF_AuxiliarybfAndefSymbol; +pub use crate::coff::binary::ffi::COFF_Binary; +pub use crate::coff::binary::ffi::COFF_Binary_it_functions; +pub use crate::coff::binary::ffi::COFF_Binary_it_instructions; +pub use crate::coff::binary::ffi::COFF_Binary_it_relocations; +pub use crate::coff::binary::ffi::COFF_Binary_it_sections; +pub use crate::coff::binary::ffi::COFF_Binary_it_strings; +pub use crate::coff::binary::ffi::COFF_Binary_it_symbols; +pub use crate::coff::header::ffi::COFF_BigObjHeader; +pub use crate::coff::header::ffi::COFF_Header; +pub use crate::coff::header::ffi::COFF_RegularHeader; +pub use crate::coff::relocation::ffi::COFF_Relocation; +pub use crate::coff::section::ffi::COFF_Section; +pub use crate::coff::section::ffi::COFF_Section_ComdataInfo; +pub use crate::coff::section::ffi::COFF_Section_it_relocations; +pub use crate::coff::section::ffi::COFF_Section_it_symbols; +pub use crate::coff::string::ffi::COFF_String; +pub use crate::coff::symbol::ffi::COFF_Symbol; +pub use crate::coff::symbol::ffi::COFF_Symbol_it_auxiliary_symbols; +pub use crate::coff::utils::ffi::COFF_Utils; +pub use crate::debug_decl_opt::ffi::LIEF_DeclOpt; +pub use crate::debug_location::ffi::DebugLocation; +pub use crate::dsc::caching::ffi::dsc_enable_cache; +pub use crate::dsc::caching::ffi::dsc_enable_cache_from_dir; +pub use crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache; +pub use crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache_it_instructions; +pub use crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache_it_libraries; +pub use crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache_it_mapping_info; +pub use crate::dsc::dyld_shared_cache::ffi::dsc_DyldSharedCache_it_subcaches; +pub use crate::dsc::dylib::ffi::dsc_Dylib; +pub use crate::dsc::dylib::ffi::dsc_Dylib_extract_opt; +pub use crate::dsc::mapping_info::ffi::dsc_MappingInfo; +pub use crate::dsc::sub_cache::ffi::dsc_SubCache; +pub use crate::dsc::utils::ffi::dsc_Utils; +pub use crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit; +pub use crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit_Language; +pub use crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit_it_functions; +pub use crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit_it_types; +pub use crate::dwarf::compilation_unit::ffi::DWARF_CompilationUnit_it_variables; +pub use crate::dwarf::debug_info::ffi::DWARF_DebugInfo; +pub use crate::dwarf::debug_info::ffi::DWARF_DebugInfo_it_compilation_units; +pub use crate::dwarf::editor::array_type::ffi::DWARF_editor_ArrayType; +pub use crate::dwarf::editor::base_type::ffi::DWARF_editor_BaseType; +pub use crate::dwarf::editor::compilation_unit::ffi::DWARF_editor_CompilationUnit; +pub use crate::dwarf::editor::enum_type::ffi::DWARF_editor_EnumType; +pub use crate::dwarf::editor::enum_type::ffi::DWARF_editor_EnumType_Value; +pub use crate::dwarf::editor::ffi::DWARF_Editor; +pub use crate::dwarf::editor::function::ffi::DWARF_editor_Function; +pub use crate::dwarf::editor::function::ffi::DWARF_editor_Function_Label; +pub use crate::dwarf::editor::function::ffi::DWARF_editor_Function_LexicalBlock; +pub use crate::dwarf::editor::function::ffi::DWARF_editor_Function_Parameter; +pub use crate::dwarf::editor::function::ffi::DWARF_editor_Function_Range; +pub use crate::dwarf::editor::function_type::ffi::DWARF_editor_FunctionType; +pub use crate::dwarf::editor::function_type::ffi::DWARF_editor_FunctionType_Parameter; +pub use crate::dwarf::editor::pointer_type::ffi::DWARF_editor_PointerType; +pub use crate::dwarf::editor::struct_type::ffi::DWARF_editor_StructType; +pub use crate::dwarf::editor::struct_type::ffi::DWARF_editor_StructType_Member; +pub use crate::dwarf::editor::type_::ffi::DWARF_editor_Type; +pub use crate::dwarf::editor::type_def::ffi::DWARF_editor_TypeDef; +pub use crate::dwarf::editor::variable::ffi::DWARF_editor_Variable; +pub use crate::dwarf::function::ffi::DWARF_Function; +pub use crate::dwarf::function::ffi::DWARF_Function_it_instructions; +pub use crate::dwarf::function::ffi::DWARF_Function_it_lexical_blocks; +pub use crate::dwarf::function::ffi::DWARF_Function_it_parameters; +pub use crate::dwarf::function::ffi::DWARF_Function_it_thrown_types; +pub use crate::dwarf::function::ffi::DWARF_Function_it_variables; +pub use crate::dwarf::lexical_block::ffi::DWARF_LexicalBlock; +pub use crate::dwarf::lexical_block::ffi::DWARF_LexicalBlock_it_sub_blocks; +pub use crate::dwarf::parameter::ffi::DWARF_Parameter; +pub use crate::dwarf::parameter::ffi::DWARF_Parameter_Location; +pub use crate::dwarf::parameter::ffi::DWARF_Parameter_RegisterLocation; +pub use crate::dwarf::parameter::ffi::DWARF_parameters_Formal; +pub use crate::dwarf::parameter::ffi::DWARF_parameters_TemplateType; +pub use crate::dwarf::parameter::ffi::DWARF_parameters_TemplateValue; +pub use crate::dwarf::scope::ffi::DWARF_Scope; +pub use crate::dwarf::type_::ffi::DWARF_Type; +pub use crate::dwarf::types::array::ffi::DWARF_types_Array; +pub use crate::dwarf::types::array::ffi::DWARF_types_array_size_info; +pub use crate::dwarf::types::atomic::ffi::DWARF_types_Atomic; +pub use crate::dwarf::types::base::ffi::DWARF_types_Base; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_Class; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_ClassLike; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_ClassLike_Member; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_ClassLike_it_functions; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_ClassLike_it_members; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_Packed; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_Structure; +pub use crate::dwarf::types::class_like::ffi::DWARF_types_Union; +pub use crate::dwarf::types::coarray::ffi::DWARF_types_Coarray; +pub use crate::dwarf::types::const_::ffi::DWARF_types_Const; +pub use crate::dwarf::types::dynamic::ffi::DWARF_types_Dynamic; +pub use crate::dwarf::types::enum_::ffi::DWARF_types_Enum; +pub use crate::dwarf::types::enum_::ffi::DWARF_types_Enum_Entry; +pub use crate::dwarf::types::enum_::ffi::DWARF_types_Enum_it_entries; +pub use crate::dwarf::types::file::ffi::DWARF_types_File; +pub use crate::dwarf::types::immutable::ffi::DWARF_types_Immutable; +pub use crate::dwarf::types::interface::ffi::DWARF_types_Interface; +pub use crate::dwarf::types::pointer::ffi::DWARF_types_Pointer; +pub use crate::dwarf::types::pointer_to_member::ffi::DWARF_types_PointerToMember; +pub use crate::dwarf::types::r_value_ref::ffi::DWARF_types_RValueReference; +pub use crate::dwarf::types::reference::ffi::DWARF_types_Reference; +pub use crate::dwarf::types::restrict::ffi::DWARF_types_Restrict; +pub use crate::dwarf::types::set_ty::ffi::DWARF_types_SetTy; +pub use crate::dwarf::types::shared::ffi::DWARF_types_Shared; +pub use crate::dwarf::types::string_ty::ffi::DWARF_types_StringTy; +pub use crate::dwarf::types::subroutine::ffi::DWARF_types_Subroutine; +pub use crate::dwarf::types::subroutine::ffi::DWARF_types_Subroutine_it_parameters; +pub use crate::dwarf::types::template_alias::ffi::DWARF_types_TemplateAlias; +pub use crate::dwarf::types::template_alias::ffi::DWARF_types_TemplateAlias_it_parameters; +pub use crate::dwarf::types::thrown::ffi::DWARF_types_Thrown; +pub use crate::dwarf::types::typedef::ffi::DWARF_types_Typedef; +pub use crate::dwarf::types::volatile::ffi::DWARF_types_Volatile; +pub use crate::dwarf::variable::ffi::DWARF_Variable; +pub use crate::elf::binary::ffi::ELF_Binary; +pub use crate::elf::binary::ffi::ELF_Binary_it_dynamic_entries; +pub use crate::elf::binary::ffi::ELF_Binary_it_dynamic_relocations; +pub use crate::elf::binary::ffi::ELF_Binary_it_dynamic_symbols; +pub use crate::elf::binary::ffi::ELF_Binary_it_exported_symbols; +pub use crate::elf::binary::ffi::ELF_Binary_it_imported_symbols; +pub use crate::elf::binary::ffi::ELF_Binary_it_notes; +pub use crate::elf::binary::ffi::ELF_Binary_it_object_relocations; +pub use crate::elf::binary::ffi::ELF_Binary_it_pltgot_relocations; +pub use crate::elf::binary::ffi::ELF_Binary_it_relocations; +pub use crate::elf::binary::ffi::ELF_Binary_it_sections; +pub use crate::elf::binary::ffi::ELF_Binary_it_segments; +pub use crate::elf::binary::ffi::ELF_Binary_it_symbols; +pub use crate::elf::binary::ffi::ELF_Binary_it_symbols_version; +pub use crate::elf::binary::ffi::ELF_Binary_it_symbols_version_definition; +pub use crate::elf::binary::ffi::ELF_Binary_it_symbols_version_requirement; +pub use crate::elf::binary::ffi::ELF_Binary_it_symtab_symbols; +pub use crate::elf::binary::ffi::ELF_Binary_write_config_t; +pub use crate::elf::binary::ffi::ELF_ParserConfig; +pub use crate::elf::core_auxv::ffi::ELF_CoreAuxv; +pub use crate::elf::core_file::ffi::ELF_CoreFile; +pub use crate::elf::core_file::ffi::ELF_CoreFile_entry; +pub use crate::elf::core_file::ffi::ELF_CoreFile_it_files; +pub use crate::elf::core_pr_ps_info::ffi::ELF_CorePrPsInfo; +pub use crate::elf::core_pr_status::ffi::ELF_CorePrStatus; +pub use crate::elf::core_sig_info::ffi::ELF_CoreSigInfo; +pub use crate::elf::dynamic_entry::ffi::ELF_DynamicEntry; +pub use crate::elf::dynamic_entry_array::ffi::ELF_DynamicEntryArray; +pub use crate::elf::dynamic_entry_auxiliary::ffi::ELF_DynamicEntryAuxiliary; +pub use crate::elf::dynamic_entry_filter::ffi::ELF_DynamicEntryFilter; +pub use crate::elf::dynamic_entry_flags::ffi::ELF_DynamicEntryFlags; +pub use crate::elf::dynamic_entry_library::ffi::ELF_DynamicEntryLibrary; +pub use crate::elf::dynamic_entry_rpath::ffi::ELF_DynamicEntryRpath; +pub use crate::elf::dynamic_entry_run_path::ffi::ELF_DynamicEntryRunPath; +pub use crate::elf::dynamic_shared_object::ffi::ELF_DynamicSharedObject; +pub use crate::elf::gnu_hash::ffi::ELF_GnuHash; +pub use crate::elf::header::ffi::ELF_Header; +pub use crate::elf::note::ffi::ELF_Note; +pub use crate::elf::note_abi::ffi::ELF_NoteAbi; +pub use crate::elf::note_android_ident::ffi::ELF_AndroidIdent; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_AArch64Feature; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_AArch64PAuth; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_Generic; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_Needed; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_NoteNoCopyOnProtected; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_Property; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_StackSize; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_X86Features; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_X86ISA; +pub use crate::elf::note_gnu_property::ffi::ELF_NoteGnuProperty_it_properties; +pub use crate::elf::note_qnx_stack::ffi::ELF_QNXStack; +pub use crate::elf::relocation::ffi::ELF_Relocation; +pub use crate::elf::section::ffi::ELF_Section; +pub use crate::elf::segment::ffi::ELF_Segment; +pub use crate::elf::symbol::ffi::ELF_Symbol; +pub use crate::elf::symbol_version::ffi::ELF_SymbolVersion; +pub use crate::elf::symbol_version_aux::ffi::ELF_SymbolVersionAux; +pub use crate::elf::symbol_version_aux_requirement::ffi::ELF_SymbolVersionAuxRequirement; +pub use crate::elf::symbol_version_definition::ffi::ELF_SymbolVersionDefinition; +pub use crate::elf::symbol_version_definition::ffi::ELF_SymbolVersionDefinition_it_auxiliary_symbols; +pub use crate::elf::symbol_version_requirement::ffi::ELF_SymbolVersionRequirement; +pub use crate::elf::symbol_version_requirement::ffi::ELF_SymbolVersionRequirement_it_auxiliary_symbols; +pub use crate::elf::sysvhash::ffi::ELF_SysvHash; +pub use crate::elf::utils::ffi::ELF_Utils; +pub use crate::generic::binary::ffi::AbstractBinary; +pub use crate::generic::binary::ffi::AbstractBinary_it_functions; +pub use crate::generic::binary::ffi::AbstractBinary_it_instructions; +pub use crate::generic::debug_info::ffi::AbstracDebugInfo; +pub use crate::generic::function::ffi::AbstractFunction; +pub use crate::generic::relocation::ffi::AbstractRelocation; +pub use crate::generic::section::ffi::AbstractSection; +pub use crate::generic::symbol::ffi::AbstractSymbol; +pub use crate::logging::ffi::LIEF_Logging; +pub use crate::logging::ffi::LIEF_Logging_Scoped; +pub use crate::macho::atom_info::ffi::MachO_AtomInfo; +pub use crate::macho::binary::ffi::MachO_Binary; +pub use crate::macho::binary::ffi::MachO_Binary_it_bindings_info; +pub use crate::macho::binary::ffi::MachO_Binary_it_commands; +pub use crate::macho::binary::ffi::MachO_Binary_it_exported_symbols; +pub use crate::macho::binary::ffi::MachO_Binary_it_fileset_binaries; +pub use crate::macho::binary::ffi::MachO_Binary_it_lazy_load_dylib_info; +pub use crate::macho::binary::ffi::MachO_Binary_it_libraries; +pub use crate::macho::binary::ffi::MachO_Binary_it_notes; +pub use crate::macho::binary::ffi::MachO_Binary_it_relocations; +pub use crate::macho::binary::ffi::MachO_Binary_it_rpaths; +pub use crate::macho::binary::ffi::MachO_Binary_it_sections; +pub use crate::macho::binary::ffi::MachO_Binary_it_segments; +pub use crate::macho::binary::ffi::MachO_Binary_it_stubs; +pub use crate::macho::binary::ffi::MachO_Binary_it_sub_clients; +pub use crate::macho::binary::ffi::MachO_Binary_it_symbols; +pub use crate::macho::binary::ffi::MachO_Binary_write_config_t; +pub use crate::macho::binding_info::ffi::MachO_BindingInfo; +pub use crate::macho::build_tool_version::ffi::MachO_BuildToolVersion; +pub use crate::macho::build_version::ffi::MachO_BuildVersion; +pub use crate::macho::build_version::ffi::MachO_BuildVersion_it_tools; +pub use crate::macho::chained_binding_info::ffi::MachO_ChainedBindingInfo; +pub use crate::macho::code_signature::ffi::MachO_CodeSignature; +pub use crate::macho::code_signature_dir::ffi::MachO_CodeSignatureDir; +pub use crate::macho::data_code_entry::ffi::MachO_DataCodeEntry; +pub use crate::macho::data_in_code::ffi::MachO_DataInCode; +pub use crate::macho::data_in_code::ffi::MachO_DataInCode_it_entries; +pub use crate::macho::dyld_binding_info::ffi::MachO_DyldBindingInfo; +pub use crate::macho::dyld_chained_fixups::ffi::MachO_DyldChainedFixups; +pub use crate::macho::dyld_chained_fixups::ffi::MachO_DyldChainedFixups_it_bindings; +pub use crate::macho::dyld_environment::ffi::MachO_DyldEnvironment; +pub use crate::macho::dyld_exports_trie::ffi::MachO_DyldExportsTrie; +pub use crate::macho::dyld_exports_trie::ffi::MachO_DyldExportsTrie_it_exports; +pub use crate::macho::dyld_info::ffi::MachO_DyldInfo; +pub use crate::macho::dyld_info::ffi::MachO_DyldInfo_it_bindings; +pub use crate::macho::dyld_info::ffi::MachO_DyldInfo_it_exports; +pub use crate::macho::dylib::ffi::MachO_Dylib; +pub use crate::macho::dylinker::ffi::MachO_Dylinker; +pub use crate::macho::dynamic_symbol_command::ffi::MachO_DynamicSymbolCommand; +pub use crate::macho::dynamic_symbol_command::ffi::MachO_DynamicSymbolCommand_it_indirect_symbols; +pub use crate::macho::encryption_info::ffi::MachO_EncryptionInfo; +pub use crate::macho::export_info::ffi::MachO_ExportInfo; +pub use crate::macho::fat_binary::ffi::MachO_FatBinary; +pub use crate::macho::fat_binary::ffi::MachO_ParserConfig; +pub use crate::macho::fileset::ffi::MachO_Fileset; +pub use crate::macho::function_starts::ffi::MachO_FunctionStarts; +pub use crate::macho::function_variant_fixups::ffi::MachO_FunctionVariantFixups; +pub use crate::macho::function_variant_fixups::ffi::MachO_FunctionVariantFixups_Fixup; +pub use crate::macho::function_variant_fixups::ffi::MachO_FunctionVariantFixups_it_fixups; +pub use crate::macho::function_variants::ffi::MachO_FunctionVariants; +pub use crate::macho::function_variants::ffi::MachO_FunctionVariants_RuntimeTable; +pub use crate::macho::function_variants::ffi::MachO_FunctionVariants_RuntimeTable_it_entries; +pub use crate::macho::function_variants::ffi::MachO_FunctionVariants_RuntimeTableEntry; +pub use crate::macho::function_variants::ffi::MachO_FunctionVariants_it_runtime_table; +pub use crate::macho::header::ffi::MachO_Header; +pub use crate::macho::indirect_binding_info::ffi::MachO_IndirectBindingInfo; +pub use crate::macho::lazy_load_dylib_info::ffi::MachO_LazyLoadDylibInfo; +pub use crate::macho::lazy_load_dylib_info::ffi::MachO_LazyLoadDylibInfo_Fixup; +pub use crate::macho::lazy_load_dylib_info::ffi::MachO_LazyLoadDylibInfo_it_fixups; +pub use crate::macho::linker_opt_hint::ffi::MachO_LinkerOptHint; +pub use crate::macho::load_command::ffi::MachO_Command; +pub use crate::macho::main::ffi::MachO_Main; +pub use crate::macho::note_command::ffi::MachO_NoteCommand; +pub use crate::macho::r_path_command::ffi::MachO_RPathCommand; +pub use crate::macho::relocation::ffi::MachO_Relocation; +pub use crate::macho::relocation_dyld::ffi::MachO_RelocationDyld; +pub use crate::macho::relocation_fixup::ffi::MachO_RelocationFixup; +pub use crate::macho::relocation_object::ffi::MachO_RelocationObject; +pub use crate::macho::routine::ffi::MachO_Routine; +pub use crate::macho::section::ffi::MachO_Section; +pub use crate::macho::section::ffi::MachO_Section_it_relocations; +pub use crate::macho::segment_command::ffi::MachO_SegmentCommand; +pub use crate::macho::segment_command::ffi::MachO_SegmentCommand_it_relocations; +pub use crate::macho::segment_command::ffi::MachO_SegmentCommand_it_sections; +pub use crate::macho::segment_split_info::ffi::MachO_SegmentSplitInfo; +pub use crate::macho::source_version::ffi::MachO_SourceVersion; +pub use crate::macho::stub::ffi::MachO_Stub; +pub use crate::macho::sub_client::ffi::MachO_SubClient; +pub use crate::macho::sub_framework::ffi::MachO_SubFramework; +pub use crate::macho::symbol::ffi::MachO_Symbol; +pub use crate::macho::symbol_command::ffi::MachO_SymbolCommand; +pub use crate::macho::thread_command::ffi::MachO_ThreadCommand; +pub use crate::macho::thread_local_variables::ffi::MachO_ThreadLocalVariables; +pub use crate::macho::thread_local_variables::ffi::MachO_ThreadLocalVariables_Thunk; +pub use crate::macho::thread_local_variables::ffi::MachO_ThreadLocalVariables_it_thunks; +pub use crate::macho::two_level_hints::ffi::MachO_TwoLevelHints; +pub use crate::macho::unknown_command::ffi::MachO_UnknownCommand; +pub use crate::macho::utils::ffi::MachO_Utils; +pub use crate::macho::uuid_command::ffi::MachO_UUIDCommand; +pub use crate::macho::version_min::ffi::MachO_VersionMin; +pub use crate::objc::category::ffi::ObjC_Category; +pub use crate::objc::category::ffi::ObjC_Category_it_methods; +pub use crate::objc::category::ffi::ObjC_Category_it_properties; +pub use crate::objc::category::ffi::ObjC_Category_it_protocols; +pub use crate::objc::class::ffi::ObjC_Class; +pub use crate::objc::class::ffi::ObjC_Class_it_ivars; +pub use crate::objc::class::ffi::ObjC_Class_it_methods; +pub use crate::objc::class::ffi::ObjC_Class_it_properties; +pub use crate::objc::class::ffi::ObjC_Class_it_protocols; +pub use crate::objc::decl_opt::ffi::ObjC_DeclOpt; +pub use crate::objc::i_var::ffi::ObjC_IVar; +pub use crate::objc::metadata::ffi::ObjC_Metadata; +pub use crate::objc::metadata::ffi::ObjC_Metadata_it_categories; +pub use crate::objc::metadata::ffi::ObjC_Metadata_it_classes; +pub use crate::objc::metadata::ffi::ObjC_Metadata_it_protocols; +pub use crate::objc::method::ffi::ObjC_Method; +pub use crate::objc::property::ffi::ObjC_Property; +pub use crate::objc::protocol::ffi::ObjC_Protocol; +pub use crate::objc::protocol::ffi::ObjC_Protocol_it_opt_methods; +pub use crate::objc::protocol::ffi::ObjC_Protocol_it_properties; +pub use crate::objc::protocol::ffi::ObjC_Protocol_it_protocols; +pub use crate::objc::protocol::ffi::ObjC_Protocol_it_req_methods; +pub use crate::pdb::build_metadata::ffi::PDB_BuildMetadata; +pub use crate::pdb::compilation_unit::ffi::PDB_CompilationUnit; +pub use crate::pdb::compilation_unit::ffi::PDB_CompilationUnit_it_functions; +pub use crate::pdb::compilation_unit::ffi::PDB_CompilationUnit_it_sources; +pub use crate::pdb::debug_info::ffi::PDB_DebugInfo; +pub use crate::pdb::debug_info::ffi::PDB_DebugInfo_it_compilation_units; +pub use crate::pdb::debug_info::ffi::PDB_DebugInfo_it_public_symbols; +pub use crate::pdb::debug_info::ffi::PDB_DebugInfo_it_types; +pub use crate::pdb::function::ffi::PDB_Function; +pub use crate::pdb::public_symbol::ffi::PDB_PublicSymbol; +pub use crate::pdb::type_::ffi::PDB_Type; +pub use crate::pdb::types::array::ffi::PDB_types_Array; +pub use crate::pdb::types::attribute::ffi::PDB_types_Attribute; +pub use crate::pdb::types::bit_field::ffi::PDB_types_BitField; +pub use crate::pdb::types::class_like::ffi::PDB_types_Class; +pub use crate::pdb::types::class_like::ffi::PDB_types_ClassLike; +pub use crate::pdb::types::class_like::ffi::PDB_types_ClassLike_it_attributes; +pub use crate::pdb::types::class_like::ffi::PDB_types_ClassLike_it_methods; +pub use crate::pdb::types::class_like::ffi::PDB_types_Interface; +pub use crate::pdb::types::class_like::ffi::PDB_types_Structure; +pub use crate::pdb::types::enum_::ffi::PDB_types_Enum; +pub use crate::pdb::types::enum_::ffi::PDB_types_Enum_Entry; +pub use crate::pdb::types::enum_::ffi::PDB_types_Enum_it_entries; +pub use crate::pdb::types::function::ffi::PDB_types_Function; +pub use crate::pdb::types::function::ffi::PDB_types_Function_it_parameters; +pub use crate::pdb::types::method::ffi::PDB_types_Method; +pub use crate::pdb::types::modifier::ffi::PDB_types_Modifier; +pub use crate::pdb::types::pointer::ffi::PDB_types_Pointer; +pub use crate::pdb::types::simple::ffi::PDB_types_Simple; +pub use crate::pdb::types::union_::ffi::PDB_types_Union; +pub use crate::pdb::utils::ffi::PDB_Utils; +pub use crate::pe::binary::ffi::PE_Binary; +pub use crate::pe::binary::ffi::PE_Binary_it_data_directories; +pub use crate::pe::binary::ffi::PE_Binary_it_debug; +pub use crate::pe::binary::ffi::PE_Binary_it_delay_imports; +pub use crate::pe::binary::ffi::PE_Binary_it_exceptions; +pub use crate::pe::binary::ffi::PE_Binary_it_imports; +pub use crate::pe::binary::ffi::PE_Binary_it_relocations; +pub use crate::pe::binary::ffi::PE_Binary_it_sections; +pub use crate::pe::binary::ffi::PE_Binary_it_signatures; +pub use crate::pe::binary::ffi::PE_Binary_it_strings_table; +pub use crate::pe::binary::ffi::PE_Binary_it_symbols; +pub use crate::pe::binary::ffi::PE_Binary_write_config_t; +pub use crate::pe::binary::ffi::PE_ParserConfig; +pub use crate::pe::code_integrity::ffi::PE_CodeIntegrity; +pub use crate::pe::data_directories::ffi::PE_DataDirectory; +pub use crate::pe::debug::code_view::ffi::PE_CodeView; +pub use crate::pe::debug::code_view_pdb::ffi::PE_CodeViewPDB; +pub use crate::pe::debug::debug::ffi::PE_Debug; +pub use crate::pe::debug::ex_dll_characteristics::ffi::PE_ExDllCharacteristics; +pub use crate::pe::debug::fpo::ffi::PE_FPO; +pub use crate::pe::debug::fpo::ffi::PE_FPO_entry_t; +pub use crate::pe::debug::fpo::ffi::PE_FPO_it_entries; +pub use crate::pe::debug::pdb_checksum::ffi::PE_PDBChecksum; +pub use crate::pe::debug::pogo::ffi::PE_Pogo; +pub use crate::pe::debug::pogo::ffi::PE_Pogo_it_entries; +pub use crate::pe::debug::pogo_entry::ffi::PE_PogoEntry; +pub use crate::pe::debug::repro::ffi::PE_Repro; +pub use crate::pe::debug::vc_feature::ffi::PE_VCFeature; +pub use crate::pe::delay_import::ffi::PE_DelayImport; +pub use crate::pe::delay_import::ffi::PE_DelayImport_it_entries; +pub use crate::pe::delay_import_entry::ffi::PE_DelayImportEntry; +pub use crate::pe::dos_header::ffi::PE_DosHeader; +pub use crate::pe::exception_info::ffi::PE_ExceptionInfo; +pub use crate::pe::export::ffi::PE_Export; +pub use crate::pe::export::ffi::PE_Export_it_entries; +pub use crate::pe::export_entry::ffi::PE_ExportEntry; +pub use crate::pe::factory::ffi::PE_Factory; +pub use crate::pe::header::ffi::PE_Header; +pub use crate::pe::import::ffi::PE_Import; +pub use crate::pe::import::ffi::PE_Import_it_entries; +pub use crate::pe::import_entry::ffi::PE_ImportEntry; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadata; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_code_range_entry_point_t; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_it_const_code_range_entry_point; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_it_const_range_entries; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_it_const_redirection_entries; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_range_entry_t; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataARM64_redirection_entry_t; +pub use crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadataX86; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixup; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64Kernel; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64Kernel_entry; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64Kernel_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64X; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64X_entry; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupARM64X_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupControlTransfer; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupControlTransfer_entry; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupControlTransfer_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupGeneric; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupGeneric_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixupUnknown; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride_image_bdd_dynamic_relocation_t; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride_image_bdd_info_t; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride_image_bdd_info_t_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride_it_bdd_info; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverride_it_func_overriding_info; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverrideInfo; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_FunctionOverrideInfo_it_relocations; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_relocation::ffi::PE_DynamicRelocation; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_relocation::ffi::PE_DynamicRelocationV1; +pub use crate::pe::load_configuration::dynamic_relocation::dynamic_relocation::ffi::PE_DynamicRelocationV2; +pub use crate::pe::load_configuration::enclave_configuration::ffi::PE_EnclaveConfiguration; +pub use crate::pe::load_configuration::enclave_configuration::ffi::PE_EnclaveConfiguration_it_imports; +pub use crate::pe::load_configuration::enclave_configuration::ffi::PE_EnclaveImport; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_guard_function_t; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_it_dynamic_relocations; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_it_guard_address_taken_iat_entries; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_it_guard_cf_functions; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_it_guard_eh_continuation; +pub use crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration_it_guard_long_jump_targets; +pub use crate::pe::load_configuration::volatile_metadata::ffi::PE_VolatileMetadata; +pub use crate::pe::load_configuration::volatile_metadata::ffi::PE_VolatileMetadata_it_ranges; +pub use crate::pe::load_configuration::volatile_metadata::ffi::PE_VolatileMetadata_range_t; +pub use crate::pe::optional_header::ffi::PE_OptionalHeader; +pub use crate::pe::relocation::ffi::PE_Relocation; +pub use crate::pe::relocation::ffi::PE_Relocation_it_entries; +pub use crate::pe::relocation_entry::ffi::PE_RelocationEntry; +pub use crate::pe::resource_accelerator::ffi::PE_ResourceAccelerator; +pub use crate::pe::resource_data::ffi::PE_ResourceData; +pub use crate::pe::resource_directory::ffi::PE_ResourceDirectory; +pub use crate::pe::resource_icon::ffi::PE_ResourceIcon; +pub use crate::pe::resource_node::ffi::PE_ResourceNode; +pub use crate::pe::resource_node::ffi::PE_ResourceNode_it_childs; +pub use crate::pe::resource_version::ffi::PE_ResourceStringFileInfo; +pub use crate::pe::resource_version::ffi::PE_ResourceStringFileInfo_it_children; +pub use crate::pe::resource_version::ffi::PE_ResourceStringTable; +pub use crate::pe::resource_version::ffi::PE_ResourceStringTable_entry_t; +pub use crate::pe::resource_version::ffi::PE_ResourceStringTable_it_entries; +pub use crate::pe::resource_version::ffi::PE_ResourceVar; +pub use crate::pe::resource_version::ffi::PE_ResourceVarFileInfo; +pub use crate::pe::resource_version::ffi::PE_ResourceVarFileInfo_it_vars; +pub use crate::pe::resource_version::ffi::PE_ResourceVersion; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager_it_accelerator; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager_it_icons; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager_it_string_table_entry; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager_it_version; +pub use crate::pe::resources_manager::ffi::PE_ResourcesManager_string_entry_t; +pub use crate::pe::rich_entry::ffi::PE_RichEntry; +pub use crate::pe::rich_header::ffi::PE_RichHeader; +pub use crate::pe::rich_header::ffi::PE_RichHeader_it_entries; +pub use crate::pe::runtime_function_a_arch64::ffi::PE_RuntimeFunctionAArch64; +pub use crate::pe::runtime_function_a_arch64::ffi::PE_unwind_aarch64_PackedFunction; +pub use crate::pe::runtime_function_a_arch64::ffi::PE_unwind_aarch64_UnpackedFunction; +pub use crate::pe::runtime_function_a_arch64::ffi::PE_unwind_aarch64_UnpackedFunction_epilog_scope_t; +pub use crate::pe::runtime_function_a_arch64::ffi::PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes; +pub use crate::pe::runtime_function_x64::ffi::PE_RuntimeFunctionX64; +pub use crate::pe::runtime_function_x64::ffi::PE_RuntimeFunctionX64_unwind_info_t; +pub use crate::pe::runtime_function_x64::ffi::PE_RuntimeFunctionX64_unwind_info_t_it_opcodes; +pub use crate::pe::section::ffi::PE_Section; +pub use crate::pe::signature::attributes::attribute::ffi::PE_Attribute; +pub use crate::pe::signature::attributes::content_type::ffi::PE_ContentType; +pub use crate::pe::signature::attributes::generic_type::ffi::PE_GenericType; +pub use crate::pe::signature::attributes::ms_counter_sign::ffi::PE_MsCounterSign; +pub use crate::pe::signature::attributes::ms_counter_sign::ffi::PE_MsCounterSign_it_certificates; +pub use crate::pe::signature::attributes::ms_counter_sign::ffi::PE_MsCounterSign_it_signers; +pub use crate::pe::signature::attributes::ms_manifest_binary_id::ffi::PE_MsManifestBinaryID; +pub use crate::pe::signature::attributes::ms_spc_nested_signature::ffi::PE_MsSpcNestedSignature; +pub use crate::pe::signature::attributes::ms_spc_statement_type::ffi::PE_MsSpcStatementType; +pub use crate::pe::signature::attributes::pkcs9_at_sequence_number::ffi::PE_PKCS9AtSequenceNumber; +pub use crate::pe::signature::attributes::pkcs9_counter_signature::ffi::PE_PKCS9CounterSignature; +pub use crate::pe::signature::attributes::pkcs9_message_digest::ffi::PE_PKCS9MessageDigest; +pub use crate::pe::signature::attributes::pkcs9_signing_time::ffi::PE_PKCS9SigningTime; +pub use crate::pe::signature::attributes::signing_certificate_v2::ffi::PE_SigningCertificateV2; +pub use crate::pe::signature::attributes::spc_relaxed_pe_marker_check::ffi::PE_SpcRelaxedPeMarkerCheck; +pub use crate::pe::signature::attributes::spc_sp_opus_info::ffi::PE_SpcSpOpusInfo; +pub use crate::pe::signature::content_info::ffi::PE_ContentInfo; +pub use crate::pe::signature::content_info::ffi::PE_ContentInfo_Content; +pub use crate::pe::signature::generic_content::ffi::PE_GenericContent; +pub use crate::pe::signature::pkcs9_tst_info::ffi::PE_PKCS9TSTInfo; +pub use crate::pe::signature::rsa_info::ffi::PE_RsaInfo; +pub use crate::pe::signature::signature::ffi::PE_Signature; +pub use crate::pe::signature::signature::ffi::PE_Signature_it_certificates; +pub use crate::pe::signature::signature::ffi::PE_Signature_it_signers; +pub use crate::pe::signature::signer_info::ffi::PE_SignerInfo; +pub use crate::pe::signature::signer_info::ffi::PE_SignerInfo_it_authenticated_attributes; +pub use crate::pe::signature::signer_info::ffi::PE_SignerInfo_it_unauthenticated_attributes; +pub use crate::pe::signature::spc_indirect_data::ffi::PE_SpcIndirectData; +pub use crate::pe::signature::x509::ffi::PE_x509; +pub use crate::pe::tls::ffi::PE_TLS; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_Alloc; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_Code; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_Epilog; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_PushMachFrame; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_PushNonVol; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_SaveNonVolatile; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_SaveXMM128; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_SetFPReg; +pub use crate::pe::unwind_code_x64::ffi::PE_unwind_x64_Spare; +pub use crate::pe::utils::ffi::PE_Utils; +pub use crate::runtime::android::host::ffi::runtime_android_Host; +pub use crate::runtime::android::module::ffi::runtime_android_Module; +pub use crate::runtime::android::module::ffi::runtime_android_dlopen; +pub use crate::runtime::android::process::ffi::runtime_android_Process; +pub use crate::runtime::android::property::ffi::runtime_android_Property; +pub use crate::runtime::android::property::ffi::runtime_android_it_properties; +pub use crate::runtime::assembler::ffi::runtime_assemble; +pub use crate::runtime::assembler::ffi::runtime_assemble_with_config; +pub use crate::runtime::disassembler::ffi::runtime_disassemble; +pub use crate::runtime::disassembler::ffi::runtime_it_instructions; +pub use crate::runtime::ffi::runtime_arch; +pub use crate::runtime::ffi::runtime_enabled; +pub use crate::runtime::ffi::runtime_platform; +pub use crate::runtime::host::ffi::runtime_Host; +pub use crate::runtime::linux::host::ffi::runtime_linux_Host; +pub use crate::runtime::linux::module::ffi::runtime_linux_Module; +pub use crate::runtime::linux::module::ffi::runtime_linux_dlopen; +pub use crate::runtime::linux::process::ffi::runtime_linux_Process; +pub use crate::runtime::memory::ffi::runtime_Memory; +pub use crate::runtime::memory::ffi::runtime_Memory_Chunk; +pub use crate::runtime::memory_layout::ffi::runtime_MemoryLayout_Region; +pub use crate::runtime::memory_layout::ffi::runtime_it_memory_layout; +pub use crate::runtime::memory_layout::ffi::runtime_memory_layout; +pub use crate::runtime::module::ffi::runtime_Module; +pub use crate::runtime::module::ffi::runtime_it_modules; +pub use crate::runtime::module::ffi::runtime_module_from_addr; +pub use crate::runtime::module::ffi::runtime_module_from_name; +pub use crate::runtime::module::ffi::runtime_module_from_path; +pub use crate::runtime::module::ffi::runtime_modules; +pub use crate::runtime::osx::host::ffi::runtime_osx_Host; +pub use crate::runtime::osx::host::ffi::runtime_osx_Host_version_t; +pub use crate::runtime::osx::module::ffi::runtime_osx_Module; +pub use crate::runtime::osx::module::ffi::runtime_osx_dlopen; +pub use crate::runtime::osx::process::ffi::runtime_osx_Process; +pub use crate::runtime::process::ffi::runtime_Process; +pub use crate::runtime::windows::host::ffi::runtime_windows_Host; +pub use crate::runtime::windows::host::ffi::runtime_windows_Host_version_t; +pub use crate::runtime::windows::ldr_data_table_entry::ffi::runtime_windows_LdrDataTableEntry; +pub use crate::runtime::windows::ldr_data_table_entry::ffi::runtime_windows_it_ldr_data_table_entry; +pub use crate::runtime::windows::module::ffi::runtime_windows_Module; +pub use crate::runtime::windows::module::ffi::runtime_windows_dlopen; +pub use crate::runtime::windows::module::ffi::runtime_windows_find_module; +pub use crate::runtime::windows::peb::ffi::runtime_windows_PEB; +pub use crate::runtime::windows::process::ffi::runtime_windows_Process; +pub use crate::stream::ffi::RustStream; +pub use crate::utils::ffi::LIEFVersion; +pub use crate::utils::ffi::Range; +pub use crate::utils::ffi::demangle; +pub use crate::utils::ffi::dump; +pub use crate::utils::ffi::dump_with_limit; +pub use crate::utils::ffi::extended_version; +pub use crate::utils::ffi::extended_version_info; +pub use crate::utils::ffi::is_extended; +pub use crate::utils::ffi::version; + +// AsRef impls for inheritance chains. The unsafe pointer cast is safe +// because every type uses the Mirror pattern with single inheritance +// so the parent class is at offset 0 within the child. +impl AsRef for AbstractFunction { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const AbstractFunction as *const AbstractSymbol) } + } +} +impl AsRef for COFF_AuxiliaryCLRToken { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { &*(self as *const COFF_AuxiliaryCLRToken as *const COFF_AuxiliarySymbol) } + } +} +impl AsRef for COFF_AuxiliaryFile { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { &*(self as *const COFF_AuxiliaryFile as *const COFF_AuxiliarySymbol) } + } +} +impl AsRef for COFF_AuxiliaryFunctionDefinition { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { + &*(self as *const COFF_AuxiliaryFunctionDefinition as *const COFF_AuxiliarySymbol) + } + } +} +impl AsRef for COFF_AuxiliarySectionDefinition { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { &*(self as *const COFF_AuxiliarySectionDefinition as *const COFF_AuxiliarySymbol) } + } +} +impl AsRef for COFF_AuxiliaryWeakExternal { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { &*(self as *const COFF_AuxiliaryWeakExternal as *const COFF_AuxiliarySymbol) } + } +} +impl AsRef for COFF_AuxiliarybfAndefSymbol { + fn as_ref(&self) -> &COFF_AuxiliarySymbol { + unsafe { &*(self as *const COFF_AuxiliarybfAndefSymbol as *const COFF_AuxiliarySymbol) } + } +} +impl AsRef for COFF_BigObjHeader { + fn as_ref(&self) -> &COFF_Header { + unsafe { &*(self as *const COFF_BigObjHeader as *const COFF_Header) } + } +} +impl AsRef for COFF_RegularHeader { + fn as_ref(&self) -> &COFF_Header { + unsafe { &*(self as *const COFF_RegularHeader as *const COFF_Header) } + } +} +impl AsRef for COFF_Relocation { + fn as_ref(&self) -> &AbstractRelocation { + unsafe { &*(self as *const COFF_Relocation as *const AbstractRelocation) } + } +} +impl AsRef for COFF_Section { + fn as_ref(&self) -> &AbstractSection { + unsafe { &*(self as *const COFF_Section as *const AbstractSection) } + } +} +impl AsRef for COFF_Symbol { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const COFF_Symbol as *const AbstractSymbol) } + } +} +impl AsRef for DWARF_DebugInfo { + fn as_ref(&self) -> &AbstracDebugInfo { + unsafe { &*(self as *const DWARF_DebugInfo as *const AbstracDebugInfo) } + } +} +impl AsRef for DWARF_editor_ArrayType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_ArrayType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_BaseType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_BaseType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_EnumType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_EnumType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_FunctionType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_FunctionType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_PointerType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_PointerType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_StructType { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_StructType as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_editor_TypeDef { + fn as_ref(&self) -> &DWARF_editor_Type { + unsafe { &*(self as *const DWARF_editor_TypeDef as *const DWARF_editor_Type) } + } +} +impl AsRef for DWARF_parameters_Formal { + fn as_ref(&self) -> &DWARF_Parameter { + unsafe { &*(self as *const DWARF_parameters_Formal as *const DWARF_Parameter) } + } +} +impl AsRef for DWARF_parameters_TemplateType { + fn as_ref(&self) -> &DWARF_Parameter { + unsafe { &*(self as *const DWARF_parameters_TemplateType as *const DWARF_Parameter) } + } +} +impl AsRef for DWARF_parameters_TemplateValue { + fn as_ref(&self) -> &DWARF_Parameter { + unsafe { &*(self as *const DWARF_parameters_TemplateValue as *const DWARF_Parameter) } + } +} +impl AsRef for DWARF_types_Array { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Array as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Atomic { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Atomic as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Base { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Base as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Class { + fn as_ref(&self) -> &DWARF_types_ClassLike { + unsafe { &*(self as *const DWARF_types_Class as *const DWARF_types_ClassLike) } + } +} +impl AsRef for DWARF_types_ClassLike { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_ClassLike as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Coarray { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Coarray as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Const { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Const as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Dynamic { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Dynamic as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Enum { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Enum as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_File { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_File as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Immutable { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Immutable as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Interface { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Interface as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Packed { + fn as_ref(&self) -> &DWARF_types_ClassLike { + unsafe { &*(self as *const DWARF_types_Packed as *const DWARF_types_ClassLike) } + } +} +impl AsRef for DWARF_types_Pointer { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Pointer as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_PointerToMember { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_PointerToMember as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_RValueReference { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_RValueReference as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Reference { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Reference as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Restrict { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Restrict as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_SetTy { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_SetTy as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Shared { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Shared as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_StringTy { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_StringTy as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Structure { + fn as_ref(&self) -> &DWARF_types_ClassLike { + unsafe { &*(self as *const DWARF_types_Structure as *const DWARF_types_ClassLike) } + } +} +impl AsRef for DWARF_types_Subroutine { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Subroutine as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_TemplateAlias { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_TemplateAlias as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Thrown { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Thrown as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Typedef { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Typedef as *const DWARF_Type) } + } +} +impl AsRef for DWARF_types_Union { + fn as_ref(&self) -> &DWARF_types_ClassLike { + unsafe { &*(self as *const DWARF_types_Union as *const DWARF_types_ClassLike) } + } +} +impl AsRef for DWARF_types_Volatile { + fn as_ref(&self) -> &DWARF_Type { + unsafe { &*(self as *const DWARF_types_Volatile as *const DWARF_Type) } + } +} +impl AsRef for ELF_AndroidIdent { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_AndroidIdent as *const ELF_Note) } + } +} +impl AsRef for ELF_Binary { + fn as_ref(&self) -> &AbstractBinary { + unsafe { &*(self as *const ELF_Binary as *const AbstractBinary) } + } +} +impl AsRef for ELF_CoreAuxv { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_CoreAuxv as *const ELF_Note) } + } +} +impl AsRef for ELF_CoreFile { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_CoreFile as *const ELF_Note) } + } +} +impl AsRef for ELF_CorePrPsInfo { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_CorePrPsInfo as *const ELF_Note) } + } +} +impl AsRef for ELF_CorePrStatus { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_CorePrStatus as *const ELF_Note) } + } +} +impl AsRef for ELF_CoreSigInfo { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_CoreSigInfo as *const ELF_Note) } + } +} +impl AsRef for ELF_DynamicEntryArray { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryArray as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryAuxiliary { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryAuxiliary as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryFilter { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryFilter as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryFlags { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryFlags as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryLibrary { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryLibrary as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryRpath { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryRpath as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicEntryRunPath { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicEntryRunPath as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_DynamicSharedObject { + fn as_ref(&self) -> &ELF_DynamicEntry { + unsafe { &*(self as *const ELF_DynamicSharedObject as *const ELF_DynamicEntry) } + } +} +impl AsRef for ELF_NoteAbi { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_NoteAbi as *const ELF_Note) } + } +} +impl AsRef for ELF_NoteGnuProperty { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_NoteGnuProperty as *const ELF_Note) } + } +} +impl AsRef for ELF_NoteGnuProperty_AArch64Feature { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_AArch64Feature + as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_AArch64PAuth { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_AArch64PAuth + as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_Generic { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_Generic as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_Needed { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_Needed as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_NoteNoCopyOnProtected { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_NoteNoCopyOnProtected + as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_StackSize { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_StackSize as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_X86Features { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_X86Features + as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_NoteGnuProperty_X86ISA { + fn as_ref(&self) -> &ELF_NoteGnuProperty_Property { + unsafe { + &*(self as *const ELF_NoteGnuProperty_X86ISA as *const ELF_NoteGnuProperty_Property) + } + } +} +impl AsRef for ELF_QNXStack { + fn as_ref(&self) -> &ELF_Note { + unsafe { &*(self as *const ELF_QNXStack as *const ELF_Note) } + } +} +impl AsRef for ELF_Relocation { + fn as_ref(&self) -> &AbstractRelocation { + unsafe { &*(self as *const ELF_Relocation as *const AbstractRelocation) } + } +} +impl AsRef for ELF_Section { + fn as_ref(&self) -> &AbstractSection { + unsafe { &*(self as *const ELF_Section as *const AbstractSection) } + } +} +impl AsRef for ELF_Symbol { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const ELF_Symbol as *const AbstractSymbol) } + } +} +impl AsRef for ELF_SymbolVersionAuxRequirement { + fn as_ref(&self) -> &ELF_SymbolVersionAux { + unsafe { &*(self as *const ELF_SymbolVersionAuxRequirement as *const ELF_SymbolVersionAux) } + } +} +impl AsRef for MachO_AtomInfo { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_AtomInfo as *const MachO_Command) } + } +} +impl AsRef for MachO_Binary { + fn as_ref(&self) -> &AbstractBinary { + unsafe { &*(self as *const MachO_Binary as *const AbstractBinary) } + } +} +impl AsRef for MachO_BuildVersion { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_BuildVersion as *const MachO_Command) } + } +} +impl AsRef for MachO_ChainedBindingInfo { + fn as_ref(&self) -> &MachO_BindingInfo { + unsafe { &*(self as *const MachO_ChainedBindingInfo as *const MachO_BindingInfo) } + } +} +impl AsRef for MachO_CodeSignature { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_CodeSignature as *const MachO_Command) } + } +} +impl AsRef for MachO_CodeSignatureDir { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_CodeSignatureDir as *const MachO_Command) } + } +} +impl AsRef for MachO_DataInCode { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DataInCode as *const MachO_Command) } + } +} +impl AsRef for MachO_DyldBindingInfo { + fn as_ref(&self) -> &MachO_BindingInfo { + unsafe { &*(self as *const MachO_DyldBindingInfo as *const MachO_BindingInfo) } + } +} +impl AsRef for MachO_DyldChainedFixups { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DyldChainedFixups as *const MachO_Command) } + } +} +impl AsRef for MachO_DyldEnvironment { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DyldEnvironment as *const MachO_Command) } + } +} +impl AsRef for MachO_DyldExportsTrie { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DyldExportsTrie as *const MachO_Command) } + } +} +impl AsRef for MachO_DyldInfo { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DyldInfo as *const MachO_Command) } + } +} +impl AsRef for MachO_Dylib { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_Dylib as *const MachO_Command) } + } +} +impl AsRef for MachO_Dylinker { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_Dylinker as *const MachO_Command) } + } +} +impl AsRef for MachO_DynamicSymbolCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_DynamicSymbolCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_EncryptionInfo { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_EncryptionInfo as *const MachO_Command) } + } +} +impl AsRef for MachO_Fileset { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_Fileset as *const MachO_Command) } + } +} +impl AsRef for MachO_FunctionStarts { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_FunctionStarts as *const MachO_Command) } + } +} +impl AsRef for MachO_FunctionVariantFixups { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_FunctionVariantFixups as *const MachO_Command) } + } +} +impl AsRef for MachO_FunctionVariants { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_FunctionVariants as *const MachO_Command) } + } +} +impl AsRef for MachO_LazyLoadDylibInfo { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_LazyLoadDylibInfo as *const MachO_Command) } + } +} +impl AsRef for MachO_IndirectBindingInfo { + fn as_ref(&self) -> &MachO_BindingInfo { + unsafe { &*(self as *const MachO_IndirectBindingInfo as *const MachO_BindingInfo) } + } +} +impl AsRef for MachO_LinkerOptHint { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_LinkerOptHint as *const MachO_Command) } + } +} +impl AsRef for MachO_Main { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_Main as *const MachO_Command) } + } +} +impl AsRef for MachO_NoteCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_NoteCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_RPathCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_RPathCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_Relocation { + fn as_ref(&self) -> &AbstractRelocation { + unsafe { &*(self as *const MachO_Relocation as *const AbstractRelocation) } + } +} +impl AsRef for MachO_RelocationDyld { + fn as_ref(&self) -> &MachO_Relocation { + unsafe { &*(self as *const MachO_RelocationDyld as *const MachO_Relocation) } + } +} +impl AsRef for MachO_RelocationFixup { + fn as_ref(&self) -> &MachO_Relocation { + unsafe { &*(self as *const MachO_RelocationFixup as *const MachO_Relocation) } + } +} +impl AsRef for MachO_RelocationObject { + fn as_ref(&self) -> &MachO_Relocation { + unsafe { &*(self as *const MachO_RelocationObject as *const MachO_Relocation) } + } +} +impl AsRef for MachO_Routine { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_Routine as *const MachO_Command) } + } +} +impl AsRef for MachO_Section { + fn as_ref(&self) -> &AbstractSection { + unsafe { &*(self as *const MachO_Section as *const AbstractSection) } + } +} +impl AsRef for MachO_SegmentCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SegmentCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_SegmentSplitInfo { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SegmentSplitInfo as *const MachO_Command) } + } +} +impl AsRef for MachO_SourceVersion { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SourceVersion as *const MachO_Command) } + } +} +impl AsRef for MachO_SubClient { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SubClient as *const MachO_Command) } + } +} +impl AsRef for MachO_SubFramework { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SubFramework as *const MachO_Command) } + } +} +impl AsRef for MachO_Symbol { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const MachO_Symbol as *const AbstractSymbol) } + } +} +impl AsRef for MachO_SymbolCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_SymbolCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_ThreadCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_ThreadCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_ThreadLocalVariables { + fn as_ref(&self) -> &MachO_Section { + unsafe { &*(self as *const MachO_ThreadLocalVariables as *const MachO_Section) } + } +} +impl AsRef for MachO_TwoLevelHints { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_TwoLevelHints as *const MachO_Command) } + } +} +impl AsRef for MachO_UUIDCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_UUIDCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_UnknownCommand { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_UnknownCommand as *const MachO_Command) } + } +} +impl AsRef for MachO_VersionMin { + fn as_ref(&self) -> &MachO_Command { + unsafe { &*(self as *const MachO_VersionMin as *const MachO_Command) } + } +} +impl AsRef for PDB_DebugInfo { + fn as_ref(&self) -> &AbstracDebugInfo { + unsafe { &*(self as *const PDB_DebugInfo as *const AbstracDebugInfo) } + } +} +impl AsRef for PDB_types_Array { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Array as *const PDB_Type) } + } +} +impl AsRef for PDB_types_BitField { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_BitField as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Class { + fn as_ref(&self) -> &PDB_types_ClassLike { + unsafe { &*(self as *const PDB_types_Class as *const PDB_types_ClassLike) } + } +} +impl AsRef for PDB_types_ClassLike { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_ClassLike as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Enum { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Enum as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Function { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Function as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Interface { + fn as_ref(&self) -> &PDB_types_ClassLike { + unsafe { &*(self as *const PDB_types_Interface as *const PDB_types_ClassLike) } + } +} +impl AsRef for PDB_types_Modifier { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Modifier as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Pointer { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Pointer as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Simple { + fn as_ref(&self) -> &PDB_Type { + unsafe { &*(self as *const PDB_types_Simple as *const PDB_Type) } + } +} +impl AsRef for PDB_types_Structure { + fn as_ref(&self) -> &PDB_types_ClassLike { + unsafe { &*(self as *const PDB_types_Structure as *const PDB_types_ClassLike) } + } +} +impl AsRef for PDB_types_Union { + fn as_ref(&self) -> &PDB_types_ClassLike { + unsafe { &*(self as *const PDB_types_Union as *const PDB_types_ClassLike) } + } +} +impl AsRef for PE_Binary { + fn as_ref(&self) -> &AbstractBinary { + unsafe { &*(self as *const PE_Binary as *const AbstractBinary) } + } +} +impl AsRef for PE_CHPEMetadataARM64 { + fn as_ref(&self) -> &PE_CHPEMetadata { + unsafe { &*(self as *const PE_CHPEMetadataARM64 as *const PE_CHPEMetadata) } + } +} +impl AsRef for PE_CHPEMetadataX86 { + fn as_ref(&self) -> &PE_CHPEMetadata { + unsafe { &*(self as *const PE_CHPEMetadataX86 as *const PE_CHPEMetadata) } + } +} +impl AsRef for PE_CodeView { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_CodeView as *const PE_Debug) } + } +} +impl AsRef for PE_CodeViewPDB { + fn as_ref(&self) -> &PE_CodeView { + unsafe { &*(self as *const PE_CodeViewPDB as *const PE_CodeView) } + } +} +impl AsRef for PE_DelayImportEntry { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const PE_DelayImportEntry as *const AbstractSymbol) } + } +} +impl AsRef for PE_DynamicFixupARM64Kernel { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_DynamicFixupARM64Kernel as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_DynamicFixupARM64X { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_DynamicFixupARM64X as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_DynamicFixupControlTransfer { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_DynamicFixupControlTransfer as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_DynamicFixupGeneric { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_DynamicFixupGeneric as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_DynamicFixupUnknown { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_DynamicFixupUnknown as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_DynamicRelocationV1 { + fn as_ref(&self) -> &PE_DynamicRelocation { + unsafe { &*(self as *const PE_DynamicRelocationV1 as *const PE_DynamicRelocation) } + } +} +impl AsRef for PE_DynamicRelocationV2 { + fn as_ref(&self) -> &PE_DynamicRelocation { + unsafe { &*(self as *const PE_DynamicRelocationV2 as *const PE_DynamicRelocation) } + } +} +impl AsRef for PE_ExDllCharacteristics { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_ExDllCharacteristics as *const PE_Debug) } + } +} +impl AsRef for PE_ExportEntry { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const PE_ExportEntry as *const AbstractSymbol) } + } +} +impl AsRef for PE_FPO { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_FPO as *const PE_Debug) } + } +} +impl AsRef for PE_FunctionOverride { + fn as_ref(&self) -> &PE_DynamicFixup { + unsafe { &*(self as *const PE_FunctionOverride as *const PE_DynamicFixup) } + } +} +impl AsRef for PE_GenericContent { + fn as_ref(&self) -> &PE_ContentInfo_Content { + unsafe { &*(self as *const PE_GenericContent as *const PE_ContentInfo_Content) } + } +} +impl AsRef for PE_ImportEntry { + fn as_ref(&self) -> &AbstractSymbol { + unsafe { &*(self as *const PE_ImportEntry as *const AbstractSymbol) } + } +} +impl AsRef for PE_PDBChecksum { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_PDBChecksum as *const PE_Debug) } + } +} +impl AsRef for PE_PKCS9TSTInfo { + fn as_ref(&self) -> &PE_ContentInfo_Content { + unsafe { &*(self as *const PE_PKCS9TSTInfo as *const PE_ContentInfo_Content) } + } +} +impl AsRef for PE_Pogo { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_Pogo as *const PE_Debug) } + } +} +impl AsRef for PE_RelocationEntry { + fn as_ref(&self) -> &AbstractRelocation { + unsafe { &*(self as *const PE_RelocationEntry as *const AbstractRelocation) } + } +} +impl AsRef for PE_Repro { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_Repro as *const PE_Debug) } + } +} +impl AsRef for PE_ResourceData { + fn as_ref(&self) -> &PE_ResourceNode { + unsafe { &*(self as *const PE_ResourceData as *const PE_ResourceNode) } + } +} +impl AsRef for PE_ResourceDirectory { + fn as_ref(&self) -> &PE_ResourceNode { + unsafe { &*(self as *const PE_ResourceDirectory as *const PE_ResourceNode) } + } +} +impl AsRef for PE_RuntimeFunctionAArch64 { + fn as_ref(&self) -> &PE_ExceptionInfo { + unsafe { &*(self as *const PE_RuntimeFunctionAArch64 as *const PE_ExceptionInfo) } + } +} +impl AsRef for PE_RuntimeFunctionX64 { + fn as_ref(&self) -> &PE_ExceptionInfo { + unsafe { &*(self as *const PE_RuntimeFunctionX64 as *const PE_ExceptionInfo) } + } +} +impl AsRef for PE_Section { + fn as_ref(&self) -> &AbstractSection { + unsafe { &*(self as *const PE_Section as *const AbstractSection) } + } +} +impl AsRef for PE_SpcIndirectData { + fn as_ref(&self) -> &PE_ContentInfo_Content { + unsafe { &*(self as *const PE_SpcIndirectData as *const PE_ContentInfo_Content) } + } +} +impl AsRef for PE_VCFeature { + fn as_ref(&self) -> &PE_Debug { + unsafe { &*(self as *const PE_VCFeature as *const PE_Debug) } + } +} +impl AsRef for PE_unwind_aarch64_PackedFunction { + fn as_ref(&self) -> &PE_RuntimeFunctionAArch64 { + unsafe { + &*(self as *const PE_unwind_aarch64_PackedFunction as *const PE_RuntimeFunctionAArch64) + } + } +} +impl AsRef for PE_unwind_aarch64_UnpackedFunction { + fn as_ref(&self) -> &PE_RuntimeFunctionAArch64 { + unsafe { + &*(self as *const PE_unwind_aarch64_UnpackedFunction + as *const PE_RuntimeFunctionAArch64) + } + } +} +impl AsRef for PE_unwind_x64_Alloc { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_Alloc as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_Epilog { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_Epilog as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_PushMachFrame { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_PushMachFrame as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_PushNonVol { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_PushNonVol as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_SaveNonVolatile { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_SaveNonVolatile as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_SaveXMM128 { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_SaveXMM128 as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_SetFPReg { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_SetFPReg as *const PE_unwind_x64_Code) } + } +} +impl AsRef for PE_unwind_x64_Spare { + fn as_ref(&self) -> &PE_unwind_x64_Code { + unsafe { &*(self as *const PE_unwind_x64_Spare as *const PE_unwind_x64_Code) } + } +} +impl AsRef for asm_aarch64_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_aarch64_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_aarch64_operands_Immediate { + fn as_ref(&self) -> &asm_aarch64_Operand { + unsafe { &*(self as *const asm_aarch64_operands_Immediate as *const asm_aarch64_Operand) } + } +} +impl AsRef for asm_aarch64_operands_Memory { + fn as_ref(&self) -> &asm_aarch64_Operand { + unsafe { &*(self as *const asm_aarch64_operands_Memory as *const asm_aarch64_Operand) } + } +} +impl AsRef for asm_aarch64_operands_PCRelative { + fn as_ref(&self) -> &asm_aarch64_Operand { + unsafe { &*(self as *const asm_aarch64_operands_PCRelative as *const asm_aarch64_Operand) } + } +} +impl AsRef for asm_aarch64_operands_Register { + fn as_ref(&self) -> &asm_aarch64_Operand { + unsafe { &*(self as *const asm_aarch64_operands_Register as *const asm_aarch64_Operand) } + } +} +impl AsRef for asm_arm_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_arm_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_ebpf_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_ebpf_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_mips_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_mips_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_powerpc_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_powerpc_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_riscv_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_riscv_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_x86_Instruction { + fn as_ref(&self) -> &asm_Instruction { + unsafe { &*(self as *const asm_x86_Instruction as *const asm_Instruction) } + } +} +impl AsRef for asm_mips_operands_Immediate { + fn as_ref(&self) -> &asm_mips_Operand { + unsafe { &*(self as *const asm_mips_operands_Immediate as *const asm_mips_Operand) } + } +} +impl AsRef for asm_mips_operands_Memory { + fn as_ref(&self) -> &asm_mips_Operand { + unsafe { &*(self as *const asm_mips_operands_Memory as *const asm_mips_Operand) } + } +} +impl AsRef for asm_mips_operands_PCRelative { + fn as_ref(&self) -> &asm_mips_Operand { + unsafe { &*(self as *const asm_mips_operands_PCRelative as *const asm_mips_Operand) } + } +} +impl AsRef for asm_mips_operands_Register { + fn as_ref(&self) -> &asm_mips_Operand { + unsafe { &*(self as *const asm_mips_operands_Register as *const asm_mips_Operand) } + } +} +impl AsRef for asm_powerpc_operands_Immediate { + fn as_ref(&self) -> &asm_powerpc_Operand { + unsafe { &*(self as *const asm_powerpc_operands_Immediate as *const asm_powerpc_Operand) } + } +} +impl AsRef for asm_powerpc_operands_Memory { + fn as_ref(&self) -> &asm_powerpc_Operand { + unsafe { &*(self as *const asm_powerpc_operands_Memory as *const asm_powerpc_Operand) } + } +} +impl AsRef for asm_powerpc_operands_PCRelative { + fn as_ref(&self) -> &asm_powerpc_Operand { + unsafe { &*(self as *const asm_powerpc_operands_PCRelative as *const asm_powerpc_Operand) } + } +} +impl AsRef for asm_powerpc_operands_Register { + fn as_ref(&self) -> &asm_powerpc_Operand { + unsafe { &*(self as *const asm_powerpc_operands_Register as *const asm_powerpc_Operand) } + } +} +impl AsRef for asm_ebpf_operands_Immediate { + fn as_ref(&self) -> &asm_ebpf_Operand { + unsafe { &*(self as *const asm_ebpf_operands_Immediate as *const asm_ebpf_Operand) } + } +} +impl AsRef for asm_ebpf_operands_Memory { + fn as_ref(&self) -> &asm_ebpf_Operand { + unsafe { &*(self as *const asm_ebpf_operands_Memory as *const asm_ebpf_Operand) } + } +} +impl AsRef for asm_ebpf_operands_PCRelative { + fn as_ref(&self) -> &asm_ebpf_Operand { + unsafe { &*(self as *const asm_ebpf_operands_PCRelative as *const asm_ebpf_Operand) } + } +} +impl AsRef for asm_ebpf_operands_Register { + fn as_ref(&self) -> &asm_ebpf_Operand { + unsafe { &*(self as *const asm_ebpf_operands_Register as *const asm_ebpf_Operand) } + } +} +impl AsRef for asm_riscv_operands_Immediate { + fn as_ref(&self) -> &asm_riscv_Operand { + unsafe { &*(self as *const asm_riscv_operands_Immediate as *const asm_riscv_Operand) } + } +} +impl AsRef for asm_riscv_operands_Memory { + fn as_ref(&self) -> &asm_riscv_Operand { + unsafe { &*(self as *const asm_riscv_operands_Memory as *const asm_riscv_Operand) } + } +} +impl AsRef for asm_riscv_operands_PCRelative { + fn as_ref(&self) -> &asm_riscv_Operand { + unsafe { &*(self as *const asm_riscv_operands_PCRelative as *const asm_riscv_Operand) } + } +} +impl AsRef for asm_riscv_operands_Register { + fn as_ref(&self) -> &asm_riscv_Operand { + unsafe { &*(self as *const asm_riscv_operands_Register as *const asm_riscv_Operand) } + } +} +impl AsRef for asm_x86_operands_Immediate { + fn as_ref(&self) -> &asm_x86_Operand { + unsafe { &*(self as *const asm_x86_operands_Immediate as *const asm_x86_Operand) } + } +} +impl AsRef for asm_x86_operands_Memory { + fn as_ref(&self) -> &asm_x86_Operand { + unsafe { &*(self as *const asm_x86_operands_Memory as *const asm_x86_Operand) } + } +} +impl AsRef for asm_x86_operands_PCRelative { + fn as_ref(&self) -> &asm_x86_Operand { + unsafe { &*(self as *const asm_x86_operands_PCRelative as *const asm_x86_Operand) } + } +} +impl AsRef for asm_x86_operands_Register { + fn as_ref(&self) -> &asm_x86_Operand { + unsafe { &*(self as *const asm_x86_operands_Register as *const asm_x86_Operand) } + } +} +impl AsRef for runtime_linux_Module { + fn as_ref(&self) -> &runtime_Module { + unsafe { &*(self as *const runtime_linux_Module as *const runtime_Module) } + } +} +impl AsRef for runtime_osx_Module { + fn as_ref(&self) -> &runtime_Module { + unsafe { &*(self as *const runtime_osx_Module as *const runtime_Module) } + } +} +impl AsRef for runtime_windows_Module { + fn as_ref(&self) -> &runtime_Module { + unsafe { &*(self as *const runtime_windows_Module as *const runtime_Module) } + } +} +impl AsRef for runtime_android_Module { + fn as_ref(&self) -> &runtime_Module { + unsafe { &*(self as *const runtime_android_Module as *const runtime_Module) } + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/logging.rs b/vendor/lief/api/rust/crates/lief-ffi/src/logging.rs new file mode 100644 index 0000000..db58d2b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/logging.rs @@ -0,0 +1,31 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/logging.hpp"); + + type LIEF_Logging; + + #[Self = "LIEF_Logging"] + fn disable(); + #[Self = "LIEF_Logging"] + fn reset(); + #[Self = "LIEF_Logging"] + fn enable(); + #[Self = "LIEF_Logging"] + fn set_level(lvl: u32); + #[Self = "LIEF_Logging"] + fn set_path(path: &CxxString); + #[Self = "LIEF_Logging"] + fn log(lvl: u32, msg: &CxxString); + #[Self = "LIEF_Logging"] + fn get_level() -> u32; + + type LIEF_Logging_Scoped; + + #[Self = "LIEF_Logging_Scoped"] + fn create(lvl: u32) -> UniquePtr; + fn set_level(self: &LIEF_Logging_Scoped, lvl: u32); + fn reset(self: Pin<&mut LIEF_Logging_Scoped>); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho.rs new file mode 100644 index 0000000..ef9c4b7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho.rs @@ -0,0 +1,54 @@ +pub mod atom_info; +pub mod binary; +pub mod binding_info; +pub mod build_tool_version; +pub mod build_version; +pub mod chained_binding_info; +pub mod code_signature; +pub mod code_signature_dir; +pub mod data_code_entry; +pub mod data_in_code; +pub mod dyld_binding_info; +pub mod dyld_chained_fixups; +pub mod dyld_environment; +pub mod dyld_exports_trie; +pub mod dyld_info; +pub mod dylib; +pub mod dylinker; +pub mod dynamic_symbol_command; +pub mod encryption_info; +pub mod export_info; +pub mod fat_binary; +pub mod fileset; +pub mod function_starts; +pub mod function_variant_fixups; +pub mod function_variants; +pub mod header; +pub mod indirect_binding_info; +pub mod lazy_load_dylib_info; +pub mod linker_opt_hint; +pub mod load_command; +pub mod main; +pub mod note_command; +pub mod r_path_command; +pub mod relocation; +pub mod relocation_dyld; +pub mod relocation_fixup; +pub mod relocation_object; +pub mod routine; +pub mod section; +pub mod segment_command; +pub mod segment_split_info; +pub mod source_version; +pub mod stub; +pub mod sub_client; +pub mod sub_framework; +pub mod symbol; +pub mod symbol_command; +pub mod thread_command; +pub mod thread_local_variables; +pub mod two_level_hints; +pub mod unknown_command; +pub mod utils; +pub mod uuid_command; +pub mod version_min; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/atom_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/atom_info.rs new file mode 100644 index 0000000..e781c9c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/atom_info.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/AtomInfo.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_AtomInfo; + + fn content(self: &MachO_AtomInfo) -> Span; + #[Self = "MachO_AtomInfo"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_AtomInfo) -> u32; + fn data_size(self: &MachO_AtomInfo) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/binary.rs new file mode 100644 index 0000000..548144d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/binary.rs @@ -0,0 +1,297 @@ +#[repr(C)] +pub struct write_config_t { + pub linkedit: bool, +} + +unsafe impl cxx::ExternType for write_config_t { + type Id = cxx::type_id!("MachO_Binary_write_config_t"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Binary.hpp"); + + type Range = crate::utils::ffi::Range; + type Span = crate::utils::ffi::Span; + type AbstractBinary_it_functions = crate::generic::binary::ffi::AbstractBinary_it_functions; + type MachO_AtomInfo = crate::macho::atom_info::ffi::MachO_AtomInfo; + type MachO_BindingInfo = crate::macho::binding_info::ffi::MachO_BindingInfo; + type MachO_BuildVersion = crate::macho::build_version::ffi::MachO_BuildVersion; + type MachO_CodeSignature = crate::macho::code_signature::ffi::MachO_CodeSignature; + type MachO_CodeSignatureDir = crate::macho::code_signature_dir::ffi::MachO_CodeSignatureDir; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_DataInCode = crate::macho::data_in_code::ffi::MachO_DataInCode; + type MachO_DyldChainedFixups = + crate::macho::dyld_chained_fixups::ffi::MachO_DyldChainedFixups; + type MachO_DyldEnvironment = crate::macho::dyld_environment::ffi::MachO_DyldEnvironment; + type MachO_DyldExportsTrie = crate::macho::dyld_exports_trie::ffi::MachO_DyldExportsTrie; + type MachO_DyldInfo = crate::macho::dyld_info::ffi::MachO_DyldInfo; + type MachO_Dylib = crate::macho::dylib::ffi::MachO_Dylib; + type MachO_Dylinker = crate::macho::dylinker::ffi::MachO_Dylinker; + type MachO_DynamicSymbolCommand = + crate::macho::dynamic_symbol_command::ffi::MachO_DynamicSymbolCommand; + type MachO_EncryptionInfo = crate::macho::encryption_info::ffi::MachO_EncryptionInfo; + type MachO_ExportInfo = crate::macho::export_info::ffi::MachO_ExportInfo; + type MachO_FunctionStarts = crate::macho::function_starts::ffi::MachO_FunctionStarts; + type MachO_FunctionVariantFixups = + crate::macho::function_variant_fixups::ffi::MachO_FunctionVariantFixups; + type MachO_FunctionVariants = crate::macho::function_variants::ffi::MachO_FunctionVariants; + type MachO_LazyLoadDylibInfo = + crate::macho::lazy_load_dylib_info::ffi::MachO_LazyLoadDylibInfo; + type MachO_Header = crate::macho::header::ffi::MachO_Header; + type MachO_LinkerOptHint = crate::macho::linker_opt_hint::ffi::MachO_LinkerOptHint; + type MachO_Main = crate::macho::main::ffi::MachO_Main; + type MachO_NoteCommand = crate::macho::note_command::ffi::MachO_NoteCommand; + type MachO_RPathCommand = crate::macho::r_path_command::ffi::MachO_RPathCommand; + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + type MachO_Routine = crate::macho::routine::ffi::MachO_Routine; + type MachO_Section = crate::macho::section::ffi::MachO_Section; + type MachO_SegmentCommand = crate::macho::segment_command::ffi::MachO_SegmentCommand; + type MachO_SegmentSplitInfo = crate::macho::segment_split_info::ffi::MachO_SegmentSplitInfo; + type MachO_SourceVersion = crate::macho::source_version::ffi::MachO_SourceVersion; + type MachO_Stub = crate::macho::stub::ffi::MachO_Stub; + type MachO_SubClient = crate::macho::sub_client::ffi::MachO_SubClient; + type MachO_SubFramework = crate::macho::sub_framework::ffi::MachO_SubFramework; + type MachO_Symbol = crate::macho::symbol::ffi::MachO_Symbol; + type MachO_SymbolCommand = crate::macho::symbol_command::ffi::MachO_SymbolCommand; + type MachO_ThreadCommand = crate::macho::thread_command::ffi::MachO_ThreadCommand; + type MachO_TwoLevelHints = crate::macho::two_level_hints::ffi::MachO_TwoLevelHints; + type MachO_UUIDCommand = crate::macho::uuid_command::ffi::MachO_UUIDCommand; + type MachO_VersionMin = crate::macho::version_min::ffi::MachO_VersionMin; + type ObjC_Metadata = crate::objc::metadata::ffi::ObjC_Metadata; + + type MachO_Binary_write_config_t = crate::macho::binary::write_config_t; + + type MachO_Binary; + + fn overlay(self: &MachO_Binary) -> Span; + #[Self = "MachO_Binary"] + fn is_exported(symbol: &MachO_Symbol) -> bool; + fn header(self: &MachO_Binary) -> UniquePtr; + fn commands(self: &MachO_Binary) -> UniquePtr; + fn symbols(self: &MachO_Binary) -> UniquePtr; + fn exported_symbols(self: &MachO_Binary) -> UniquePtr; + fn sections(self: &MachO_Binary) -> UniquePtr; + fn segments(self: &MachO_Binary) -> UniquePtr; + fn libraries(self: &MachO_Binary) -> UniquePtr; + fn lazy_load_dylib_infos( + self: &MachO_Binary, + ) -> UniquePtr; + fn relocations(self: &MachO_Binary) -> UniquePtr; + fn rpaths(self: &MachO_Binary) -> UniquePtr; + fn bindings(self: &MachO_Binary) -> UniquePtr; + fn symbol_stubs(self: &MachO_Binary) -> UniquePtr; + fn notes(self: &MachO_Binary) -> UniquePtr; + fn dyld_info(self: &MachO_Binary) -> UniquePtr; + fn uuid(self: &MachO_Binary) -> UniquePtr; + fn main_command(self: &MachO_Binary) -> UniquePtr; + fn dylinker(self: &MachO_Binary) -> UniquePtr; + fn function_starts(self: &MachO_Binary) -> UniquePtr; + fn source_version(self: &MachO_Binary) -> UniquePtr; + fn thread_command(self: &MachO_Binary) -> UniquePtr; + fn routine_command(self: &MachO_Binary) -> UniquePtr; + fn rpath(self: &MachO_Binary) -> UniquePtr; + fn symbol_command(self: &MachO_Binary) -> UniquePtr; + fn dynamic_symbol_command(self: &MachO_Binary) -> UniquePtr; + fn code_signature(self: &MachO_Binary) -> UniquePtr; + fn code_signature_dir(self: &MachO_Binary) -> UniquePtr; + fn data_in_code(self: &MachO_Binary) -> UniquePtr; + fn segment_split_info(self: &MachO_Binary) -> UniquePtr; + fn encryption_info(self: &MachO_Binary) -> UniquePtr; + fn sub_framework(self: &MachO_Binary) -> UniquePtr; + fn subclients(self: &MachO_Binary) -> UniquePtr; + fn dyld_environment(self: &MachO_Binary) -> UniquePtr; + fn build_version(self: &MachO_Binary) -> UniquePtr; + fn dyld_chained_fixups(self: &MachO_Binary) -> UniquePtr; + fn dyld_exports_trie(self: &MachO_Binary) -> UniquePtr; + fn two_level_hints(self: &MachO_Binary) -> UniquePtr; + fn linker_opt_hint(self: &MachO_Binary) -> UniquePtr; + fn atom_info(self: &MachO_Binary) -> UniquePtr; + fn function_variants(self: &MachO_Binary) -> UniquePtr; + fn function_variant_fixups(self: &MachO_Binary) -> UniquePtr; + fn version_min(self: &MachO_Binary) -> UniquePtr; + fn support_arm64_ptr_auth(self: &MachO_Binary) -> bool; + fn objc_metadata(self: &MachO_Binary) -> UniquePtr; + fn platform(self: &MachO_Binary) -> u32; + fn functions(self: &MachO_Binary) -> UniquePtr; + fn is_ios(self: &MachO_Binary) -> bool; + fn is_macos(self: &MachO_Binary) -> bool; + fn find_library(self: &MachO_Binary, name: &CxxString) -> UniquePtr; + fn write(self: Pin<&mut MachO_Binary>, output: &CxxString); + fn tlv_initial_content_range(self: &MachO_Binary) -> Range; + fn write_with_config( + self: Pin<&mut MachO_Binary>, + output: &CxxString, + config: &MachO_Binary_write_config_t, + ); + fn write_to_bytes(self: Pin<&mut MachO_Binary>) -> UniquePtr>; + fn write_to_bytes_with_config( + self: Pin<&mut MachO_Binary>, + config: &MachO_Binary_write_config_t, + ) -> UniquePtr>; + + fn add_library(self: Pin<&mut MachO_Binary>, name: &CxxString) -> UniquePtr; + fn filesets(self: &MachO_Binary) -> UniquePtr; + fn has_filesets(self: &MachO_Binary) -> bool; + fn fileset_name(self: &MachO_Binary) -> UniquePtr; + fn fileset_addr(self: &MachO_Binary) -> u64; + fn virtual_address_to_offset( + self: &MachO_Binary, + virtual_address: u64, + error: Pin<&mut u32>, + ) -> u64; + fn segment_from_offset(self: &MachO_Binary, offset: u64) + -> UniquePtr; + fn segment_from_virtual_address( + self: &MachO_Binary, + va: u64, + ) -> UniquePtr; + fn section_from_virtual_address(self: &MachO_Binary, va: u64) -> UniquePtr; + fn get_segment(self: &MachO_Binary, name: &CxxString) -> UniquePtr; + fn get_section( + self: &MachO_Binary, + segname: &CxxString, + secname: &CxxString, + ) -> UniquePtr; + fn fat_offset(self: &MachO_Binary) -> u64; + fn is_valid_addr(self: &MachO_Binary, address: u64) -> bool; + fn has_symbol(self: &MachO_Binary, name: &CxxString) -> bool; + fn get_symbol(self: &MachO_Binary, name: &CxxString) -> UniquePtr; + fn has_section(self: &MachO_Binary, name: &CxxString) -> bool; + fn section_from_offset(self: &MachO_Binary, offset: u64) -> UniquePtr; + fn has_segment(self: &MachO_Binary, name: &CxxString) -> bool; + fn remove_command(self: Pin<&mut MachO_Binary>, index: u32) -> bool; + fn remove_section(self: Pin<&mut MachO_Binary>, name: &CxxString, clear: bool); + fn remove_section_seg( + self: Pin<&mut MachO_Binary>, + segname: &CxxString, + secname: &CxxString, + clear: bool, + ); + fn remove_signature(self: Pin<&mut MachO_Binary>) -> bool; + fn remove_symbol(self: Pin<&mut MachO_Binary>, name: &CxxString) -> bool; + fn can_remove(self: &MachO_Binary, sym: &MachO_Symbol) -> bool; + fn can_remove_symbol(self: &MachO_Binary, name: &CxxString) -> bool; + fn unexport_name(self: Pin<&mut MachO_Binary>, name: &CxxString) -> bool; + fn extend(self: Pin<&mut MachO_Binary>, command: &MachO_Command, size: u64) -> bool; + fn extend_segment( + self: Pin<&mut MachO_Binary>, + segment: &MachO_SegmentCommand, + size: u64, + ) -> bool; + fn add_exported_function( + self: Pin<&mut MachO_Binary>, + address: u64, + name: &CxxString, + ) -> UniquePtr; + fn add_local_symbol( + self: Pin<&mut MachO_Binary>, + address: u64, + name: &CxxString, + ) -> UniquePtr; + fn shift(self: Pin<&mut MachO_Binary>, value: u64, err: Pin<&mut u32>) -> bool; + fn shift_linkedit(self: Pin<&mut MachO_Binary>, width: u64, err: Pin<&mut u32>) -> bool; + fn add_command( + self: Pin<&mut MachO_Binary>, + command: &MachO_Command, + ) -> UniquePtr; + fn remove_commands_by_type(self: Pin<&mut MachO_Binary>, type_: u64) -> bool; + fn has_command_type(self: &MachO_Binary, type_: u64) -> bool; + fn get_command_type(self: &MachO_Binary, type_: u64) -> UniquePtr; + fn unexport_symbol(self: Pin<&mut MachO_Binary>, sym: &MachO_Symbol) -> bool; + fn add_section_default( + self: Pin<&mut MachO_Binary>, + section: &MachO_Section, + ) -> UniquePtr; + + type MachO_Binary_it_bindings_info; + + fn next(self: Pin<&mut MachO_Binary_it_bindings_info>) -> UniquePtr; + fn size(self: &MachO_Binary_it_bindings_info) -> u64; + + type MachO_Binary_it_commands; + + fn next(self: Pin<&mut MachO_Binary_it_commands>) -> UniquePtr; + fn size(self: &MachO_Binary_it_commands) -> u64; + + type MachO_Binary_it_fileset_binaries; + + fn next(self: Pin<&mut MachO_Binary_it_fileset_binaries>) -> UniquePtr; + fn size(self: &MachO_Binary_it_fileset_binaries) -> u64; + + type MachO_Binary_it_libraries; + + fn next(self: Pin<&mut MachO_Binary_it_libraries>) -> UniquePtr; + fn size(self: &MachO_Binary_it_libraries) -> u64; + + type MachO_Binary_it_lazy_load_dylib_info; + + fn next( + self: Pin<&mut MachO_Binary_it_lazy_load_dylib_info>, + ) -> UniquePtr; + fn size(self: &MachO_Binary_it_lazy_load_dylib_info) -> u64; + + type MachO_Binary_it_notes; + + fn next(self: Pin<&mut MachO_Binary_it_notes>) -> UniquePtr; + fn size(self: &MachO_Binary_it_notes) -> u64; + + type MachO_Binary_it_relocations; + + fn next(self: Pin<&mut MachO_Binary_it_relocations>) -> UniquePtr; + fn size(self: &MachO_Binary_it_relocations) -> u64; + + type MachO_Binary_it_rpaths; + + fn next(self: Pin<&mut MachO_Binary_it_rpaths>) -> UniquePtr; + fn size(self: &MachO_Binary_it_rpaths) -> u64; + + type MachO_Binary_it_sections; + + fn next(self: Pin<&mut MachO_Binary_it_sections>) -> UniquePtr; + fn size(self: &MachO_Binary_it_sections) -> u64; + + type MachO_Binary_it_segments; + + fn next(self: Pin<&mut MachO_Binary_it_segments>) -> UniquePtr; + fn size(self: &MachO_Binary_it_segments) -> u64; + + type MachO_Binary_it_stubs; + + fn next(self: Pin<&mut MachO_Binary_it_stubs>) -> UniquePtr; + fn size(self: &MachO_Binary_it_stubs) -> u64; + + type MachO_Binary_it_sub_clients; + + fn next(self: Pin<&mut MachO_Binary_it_sub_clients>) -> UniquePtr; + fn size(self: &MachO_Binary_it_sub_clients) -> u64; + + type MachO_Binary_it_symbols; + + fn next(self: Pin<&mut MachO_Binary_it_symbols>) -> UniquePtr; + fn size(self: &MachO_Binary_it_symbols) -> u64; + + type MachO_Binary_it_exported_symbols; + + fn next(self: Pin<&mut MachO_Binary_it_exported_symbols>) -> UniquePtr; + fn size(self: &MachO_Binary_it_exported_symbols) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/binding_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/binding_info.rs new file mode 100644 index 0000000..77e6d3f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/binding_info.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/BindingInfo.hpp"); + + type MachO_Dylib = crate::macho::dylib::ffi::MachO_Dylib; + type MachO_SegmentCommand = crate::macho::segment_command::ffi::MachO_SegmentCommand; + type MachO_Symbol = crate::macho::symbol::ffi::MachO_Symbol; + + type MachO_BindingInfo; + + fn address(self: &MachO_BindingInfo) -> u64; + fn addend(self: &MachO_BindingInfo) -> i64; + fn library_ordinal(self: &MachO_BindingInfo) -> i32; + fn library(self: &MachO_BindingInfo) -> UniquePtr; + fn symbol(self: &MachO_BindingInfo) -> UniquePtr; + fn segment(self: &MachO_BindingInfo) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_tool_version.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_tool_version.rs new file mode 100644 index 0000000..ddb10fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_tool_version.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/BuildToolVersion.hpp"); + + type MachO_BuildToolVersion; + + fn tool(self: &MachO_BuildToolVersion) -> u32; + fn version(self: &MachO_BuildToolVersion) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_version.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_version.rs new file mode 100644 index 0000000..1db5b6b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/build_version.rs @@ -0,0 +1,26 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/BuildVersion.hpp"); + + type MachO_BuildToolVersion = crate::macho::build_tool_version::ffi::MachO_BuildToolVersion; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_BuildVersion; + + #[Self = "MachO_BuildVersion"] + fn classof(cmd: &MachO_Command) -> bool; + fn sdk(self: &MachO_BuildVersion) -> UniquePtr>; + fn minos(self: &MachO_BuildVersion) -> UniquePtr>; + fn platform(self: &MachO_BuildVersion) -> u32; + fn tools(self: &MachO_BuildVersion) -> UniquePtr; + + type MachO_BuildVersion_it_tools; + + fn next(self: Pin<&mut MachO_BuildVersion_it_tools>) -> UniquePtr; + fn size(self: &MachO_BuildVersion_it_tools) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/chained_binding_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/chained_binding_info.rs new file mode 100644 index 0000000..7220a16 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/chained_binding_info.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/ChainedBindingInfo.hpp"); + + type MachO_BindingInfo = crate::macho::binding_info::ffi::MachO_BindingInfo; + + type MachO_ChainedBindingInfo; + + #[Self = "MachO_ChainedBindingInfo"] + fn classof(binding: &MachO_BindingInfo) -> bool; + fn format(self: &MachO_ChainedBindingInfo) -> u32; + fn ptr_format(self: &MachO_ChainedBindingInfo) -> u32; + fn offset(self: &MachO_ChainedBindingInfo) -> u32; + fn sign_extended_addend(self: &MachO_ChainedBindingInfo) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature.rs new file mode 100644 index 0000000..52b70c8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/CodeSignature.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_CodeSignature; + + fn content(self: &MachO_CodeSignature) -> Span; + #[Self = "MachO_CodeSignature"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_CodeSignature) -> u32; + fn data_size(self: &MachO_CodeSignature) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature_dir.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature_dir.rs new file mode 100644 index 0000000..05bcf94 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/code_signature_dir.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/CodeSignatureDir.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_CodeSignatureDir; + + fn content(self: &MachO_CodeSignatureDir) -> Span; + #[Self = "MachO_CodeSignatureDir"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_CodeSignatureDir) -> u32; + fn data_size(self: &MachO_CodeSignatureDir) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_code_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_code_entry.rs new file mode 100644 index 0000000..c72009b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_code_entry.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DataCodeEntry.hpp"); + + type MachO_DataCodeEntry; + + fn offset(self: &MachO_DataCodeEntry) -> u32; + fn length(self: &MachO_DataCodeEntry) -> u32; + fn get_type(self: &MachO_DataCodeEntry) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_in_code.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_in_code.rs new file mode 100644 index 0000000..590baed --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/data_in_code.rs @@ -0,0 +1,27 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DataInCode.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_DataCodeEntry = crate::macho::data_code_entry::ffi::MachO_DataCodeEntry; + + type MachO_DataInCode; + + fn content(self: &MachO_DataInCode) -> Span; + #[Self = "MachO_DataInCode"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_DataInCode) -> u32; + fn data_size(self: &MachO_DataInCode) -> u32; + fn entries(self: &MachO_DataInCode) -> UniquePtr; + + type MachO_DataInCode_it_entries; + + fn next(self: Pin<&mut MachO_DataInCode_it_entries>) -> UniquePtr; + fn size(self: &MachO_DataInCode_it_entries) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_binding_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_binding_info.rs new file mode 100644 index 0000000..88ffb32 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_binding_info.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DyldBindingInfo.hpp"); + + type MachO_BindingInfo = crate::macho::binding_info::ffi::MachO_BindingInfo; + + type MachO_DyldBindingInfo; + + #[Self = "MachO_DyldBindingInfo"] + fn classof(binding: &MachO_BindingInfo) -> bool; + fn binding_class(self: &MachO_DyldBindingInfo) -> u64; + fn binding_type(self: &MachO_DyldBindingInfo) -> u64; + fn is_non_weak_definition(self: &MachO_DyldBindingInfo) -> bool; + fn original_offset(self: &MachO_DyldBindingInfo) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_chained_fixups.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_chained_fixups.rs new file mode 100644 index 0000000..d46806e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_chained_fixups.rs @@ -0,0 +1,39 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DyldChainedFixups.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_ChainedBindingInfo = + crate::macho::chained_binding_info::ffi::MachO_ChainedBindingInfo; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_DyldChainedFixups; + + fn payload(self: &MachO_DyldChainedFixups) -> Span; + #[Self = "MachO_DyldChainedFixups"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_DyldChainedFixups) -> u32; + fn data_size(self: &MachO_DyldChainedFixups) -> u32; + fn fixups_version(self: &MachO_DyldChainedFixups) -> u32; + fn starts_offset(self: &MachO_DyldChainedFixups) -> u32; + fn imports_offset(self: &MachO_DyldChainedFixups) -> u32; + fn symbols_offset(self: &MachO_DyldChainedFixups) -> u32; + fn imports_count(self: &MachO_DyldChainedFixups) -> u32; + fn symbols_format(self: &MachO_DyldChainedFixups) -> u32; + fn imports_format(self: &MachO_DyldChainedFixups) -> u32; + fn bindings( + self: &MachO_DyldChainedFixups, + ) -> UniquePtr; + + type MachO_DyldChainedFixups_it_bindings; + + fn next( + self: Pin<&mut MachO_DyldChainedFixups_it_bindings>, + ) -> UniquePtr; + fn size(self: &MachO_DyldChainedFixups_it_bindings) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_environment.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_environment.rs new file mode 100644 index 0000000..4b1a44b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_environment.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DyldEnvironment.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_DyldEnvironment; + + #[Self = "MachO_DyldEnvironment"] + fn classof(cmd: &MachO_Command) -> bool; + fn value(self: &MachO_DyldEnvironment) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_exports_trie.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_exports_trie.rs new file mode 100644 index 0000000..c505c4b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_exports_trie.rs @@ -0,0 +1,27 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DyldExportsTrie.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_ExportInfo = crate::macho::export_info::ffi::MachO_ExportInfo; + + type MachO_DyldExportsTrie; + + fn content(self: &MachO_DyldExportsTrie) -> Span; + #[Self = "MachO_DyldExportsTrie"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_DyldExportsTrie) -> u32; + fn data_size(self: &MachO_DyldExportsTrie) -> u32; + fn exports(self: &MachO_DyldExportsTrie) -> UniquePtr; + + type MachO_DyldExportsTrie_it_exports; + + fn next(self: Pin<&mut MachO_DyldExportsTrie_it_exports>) -> UniquePtr; + fn size(self: &MachO_DyldExportsTrie_it_exports) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_info.rs new file mode 100644 index 0000000..60a4f7a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dyld_info.rs @@ -0,0 +1,37 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DyldInfo.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_DyldBindingInfo = crate::macho::dyld_binding_info::ffi::MachO_DyldBindingInfo; + type MachO_ExportInfo = crate::macho::export_info::ffi::MachO_ExportInfo; + + type MachO_DyldInfo; + + fn rebase_opcodes(self: &MachO_DyldInfo) -> Span; + fn lazy_bind_opcodes(self: &MachO_DyldInfo) -> Span; + fn bind_opcodes(self: &MachO_DyldInfo) -> Span; + fn export_trie(self: &MachO_DyldInfo) -> Span; + fn weak_bind_opcodes(self: &MachO_DyldInfo) -> Span; + #[Self = "MachO_DyldInfo"] + fn classof(cmd: &MachO_Command) -> bool; + fn bindings(self: &MachO_DyldInfo) -> UniquePtr; + fn exports(self: &MachO_DyldInfo) -> UniquePtr; + + type MachO_DyldInfo_it_bindings; + + fn next(self: Pin<&mut MachO_DyldInfo_it_bindings>) -> UniquePtr; + fn size(self: &MachO_DyldInfo_it_bindings) -> u64; + + type MachO_DyldInfo_it_exports; + + fn next(self: Pin<&mut MachO_DyldInfo_it_exports>) -> UniquePtr; + fn size(self: &MachO_DyldInfo_it_exports) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylib.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylib.rs new file mode 100644 index 0000000..f34872d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylib.rs @@ -0,0 +1,55 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Dylib.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_Dylib; + + #[Self = "MachO_Dylib"] + fn id_dylib( + name: &CxxString, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> UniquePtr; + #[Self = "MachO_Dylib"] + fn load_dylib( + name: &CxxString, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> UniquePtr; + #[Self = "MachO_Dylib"] + fn reexport_dylib( + name: &CxxString, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> UniquePtr; + #[Self = "MachO_Dylib"] + fn weak_dylib( + name: &CxxString, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> UniquePtr; + #[Self = "MachO_Dylib"] + fn lazy_load_dylib( + name: &CxxString, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> UniquePtr; + #[Self = "MachO_Dylib"] + fn classof(cmd: &MachO_Command) -> bool; + fn name(self: &MachO_Dylib) -> UniquePtr; + fn timestamp(self: &MachO_Dylib) -> u32; + fn name_offset(self: &MachO_Dylib) -> u32; + fn current_version(self: &MachO_Dylib) -> UniquePtr>; + fn compatibility_version(self: &MachO_Dylib) -> UniquePtr>; + fn set_name(self: Pin<&mut MachO_Dylib>, name: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylinker.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylinker.rs new file mode 100644 index 0000000..03d8ed9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dylinker.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Dylinker.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_Dylinker; + + #[Self = "MachO_Dylinker"] + fn classof(cmd: &MachO_Command) -> bool; + fn name(self: &MachO_Dylinker) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/dynamic_symbol_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dynamic_symbol_command.rs new file mode 100644 index 0000000..4a63298 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/dynamic_symbol_command.rs @@ -0,0 +1,45 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/DynamicSymbolCommand.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_Symbol = crate::macho::symbol::ffi::MachO_Symbol; + + type MachO_DynamicSymbolCommand; + + #[Self = "MachO_DynamicSymbolCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn idx_local_symbol(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_local_symbols(self: &MachO_DynamicSymbolCommand) -> u32; + fn idx_external_define_symbol(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_external_define_symbols(self: &MachO_DynamicSymbolCommand) -> u32; + fn idx_undefined_symbol(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_undefined_symbols(self: &MachO_DynamicSymbolCommand) -> u32; + fn toc_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_toc(self: &MachO_DynamicSymbolCommand) -> u32; + fn module_table_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_module_table(self: &MachO_DynamicSymbolCommand) -> u32; + fn external_reference_symbol_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_external_reference_symbols(self: &MachO_DynamicSymbolCommand) -> u32; + fn indirect_symbol_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_indirect_symbols(self: &MachO_DynamicSymbolCommand) -> u32; + fn external_relocation_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_external_relocations(self: &MachO_DynamicSymbolCommand) -> u32; + fn local_relocation_offset(self: &MachO_DynamicSymbolCommand) -> u32; + fn nb_local_relocations(self: &MachO_DynamicSymbolCommand) -> u32; + fn indirect_symbols( + self: &MachO_DynamicSymbolCommand, + ) -> UniquePtr; + + type MachO_DynamicSymbolCommand_it_indirect_symbols; + + fn next( + self: Pin<&mut MachO_DynamicSymbolCommand_it_indirect_symbols>, + ) -> UniquePtr; + fn size(self: &MachO_DynamicSymbolCommand_it_indirect_symbols) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/encryption_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/encryption_info.rs new file mode 100644 index 0000000..ab778d2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/encryption_info.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/EncryptionInfo.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_EncryptionInfo; + + #[Self = "MachO_EncryptionInfo"] + fn classof(cmd: &MachO_Command) -> bool; + fn crypt_offset(self: &MachO_EncryptionInfo) -> u32; + fn crypt_size(self: &MachO_EncryptionInfo) -> u32; + fn crypt_id(self: &MachO_EncryptionInfo) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/export_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/export_info.rs new file mode 100644 index 0000000..1f2c8cd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/export_info.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/ExportInfo.hpp"); + + type MachO_Dylib = crate::macho::dylib::ffi::MachO_Dylib; + type MachO_Symbol = crate::macho::symbol::ffi::MachO_Symbol; + + type MachO_ExportInfo; + + fn node_offset(self: &MachO_ExportInfo) -> u64; + fn flags(self: &MachO_ExportInfo) -> u64; + fn address(self: &MachO_ExportInfo) -> u64; + fn other(self: &MachO_ExportInfo) -> u64; + fn kind(self: &MachO_ExportInfo) -> u64; + fn symbol(self: &MachO_ExportInfo) -> UniquePtr; + fn alias(self: &MachO_ExportInfo) -> UniquePtr; + fn alias_library(self: &MachO_ExportInfo) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/fat_binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/fat_binary.rs new file mode 100644 index 0000000..1192dbe --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/fat_binary.rs @@ -0,0 +1,43 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/FatBinary.hpp"); + + type MachO_Binary = crate::macho::binary::ffi::MachO_Binary; + + type MachO_FatBinary; + + #[Self = "MachO_FatBinary"] + fn parse(path: &CxxString) -> UniquePtr; + #[Self = "MachO_FatBinary"] + fn parse_with_config( + path: &CxxString, + config: &MachO_ParserConfig, + ) -> UniquePtr; + #[Self = "MachO_FatBinary"] + fn parse_from_dump(path: &CxxString, addr: u64) -> UniquePtr; + #[Self = "MachO_FatBinary"] + fn parse_from_dump_with_config( + path: &CxxString, + addr: u64, + config: &MachO_ParserConfig, + ) -> UniquePtr; + fn size(self: &MachO_FatBinary) -> u32; + fn write(self: Pin<&mut MachO_FatBinary>, output: &CxxString); + fn binary_at(self: &MachO_FatBinary, index: u32) -> UniquePtr; + fn binary_from_arch(self: &MachO_FatBinary, cpu: i32) -> UniquePtr; + + type MachO_ParserConfig; + + #[Self = "MachO_ParserConfig"] + fn create() -> UniquePtr; + fn set_parse_overlay(self: Pin<&mut MachO_ParserConfig>, value: bool); + fn set_parse_dyld_exports(self: Pin<&mut MachO_ParserConfig>, value: bool); + fn set_parse_dyld_bindings(self: Pin<&mut MachO_ParserConfig>, value: bool); + fn set_parse_dyld_rebases(self: Pin<&mut MachO_ParserConfig>, value: bool); + fn set_fix_from_memory(self: Pin<&mut MachO_ParserConfig>, value: bool); + fn set_from_dyld_shared_cache(self: Pin<&mut MachO_ParserConfig>, value: bool); + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/fileset.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/fileset.rs new file mode 100644 index 0000000..6e75d9a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/fileset.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Fileset.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_Fileset; + + #[Self = "MachO_Fileset"] + fn classof(cmd: &MachO_Command) -> bool; + fn name(self: &MachO_Fileset) -> UniquePtr; + fn virtual_address(self: &MachO_Fileset) -> u64; + fn file_offset(self: &MachO_Fileset) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_starts.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_starts.rs new file mode 100644 index 0000000..5de04b2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_starts.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/FunctionStarts.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_FunctionStarts; + + fn content(self: &MachO_FunctionStarts) -> Span; + #[Self = "MachO_FunctionStarts"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_FunctionStarts) -> u32; + fn data_size(self: &MachO_FunctionStarts) -> u32; + fn functions(self: &MachO_FunctionStarts) -> UniquePtr>; + fn add_function(self: Pin<&mut MachO_FunctionStarts>, address: u64); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variant_fixups.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variant_fixups.rs new file mode 100644 index 0000000..36b7352 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variant_fixups.rs @@ -0,0 +1,44 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/FunctionVariantFixups.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_SegmentCommand = crate::macho::segment_command::ffi::MachO_SegmentCommand; + + type MachO_FunctionVariantFixups; + + fn content(self: &MachO_FunctionVariantFixups) -> Span; + #[Self = "MachO_FunctionVariantFixups"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_FunctionVariantFixups) -> u32; + fn data_size(self: &MachO_FunctionVariantFixups) -> u32; + fn fixups( + self: &MachO_FunctionVariantFixups, + ) -> UniquePtr; + + type MachO_FunctionVariantFixups_Fixup; + + fn seg_offset(self: &MachO_FunctionVariantFixups_Fixup) -> u32; + fn seg_index(self: &MachO_FunctionVariantFixups_Fixup) -> u32; + fn variant_index(self: &MachO_FunctionVariantFixups_Fixup) -> u32; + fn pac_auth(self: &MachO_FunctionVariantFixups_Fixup) -> bool; + fn pac_address(self: &MachO_FunctionVariantFixups_Fixup) -> bool; + fn pac_key(self: &MachO_FunctionVariantFixups_Fixup) -> u8; + fn pac_diversity(self: &MachO_FunctionVariantFixups_Fixup) -> u16; + fn segment(self: &MachO_FunctionVariantFixups_Fixup) -> UniquePtr; + fn to_string(self: &MachO_FunctionVariantFixups_Fixup) -> UniquePtr; + + type MachO_FunctionVariantFixups_it_fixups; + + fn next( + self: Pin<&mut MachO_FunctionVariantFixups_it_fixups>, + ) -> UniquePtr; + fn size(self: &MachO_FunctionVariantFixups_it_fixups) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variants.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variants.rs new file mode 100644 index 0000000..b8504a2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/function_variants.rs @@ -0,0 +1,57 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/FunctionVariants.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_FunctionVariants; + + fn content(self: &MachO_FunctionVariants) -> Span; + #[Self = "MachO_FunctionVariants"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_FunctionVariants) -> u32; + fn data_size(self: &MachO_FunctionVariants) -> u32; + fn runtime_table( + self: &MachO_FunctionVariants, + ) -> UniquePtr; + + type MachO_FunctionVariants_RuntimeTable; + + fn kind(self: &MachO_FunctionVariants_RuntimeTable) -> u32; + fn offset(self: &MachO_FunctionVariants_RuntimeTable) -> u32; + fn entries( + self: &MachO_FunctionVariants_RuntimeTable, + ) -> UniquePtr; + fn to_string(self: &MachO_FunctionVariants_RuntimeTable) -> UniquePtr; + + type MachO_FunctionVariants_RuntimeTableEntry; + + fn flag_bit_nums(self: &MachO_FunctionVariants_RuntimeTableEntry) -> Span; + fn another_table(self: &MachO_FunctionVariants_RuntimeTableEntry) -> bool; + fn flags(self: &MachO_FunctionVariants_RuntimeTableEntry) -> UniquePtr>; + fn to_string(self: &MachO_FunctionVariants_RuntimeTableEntry) -> UniquePtr; + fn implementation(self: &MachO_FunctionVariants_RuntimeTableEntry) -> u32; + + type MachO_FunctionVariants_RuntimeTable_it_entries; + + fn next( + self: Pin<&mut MachO_FunctionVariants_RuntimeTable_it_entries>, + ) -> UniquePtr; + fn size(self: &MachO_FunctionVariants_RuntimeTable_it_entries) -> u64; + + type MachO_FunctionVariants_it_runtime_table; + + fn next( + self: Pin<&mut MachO_FunctionVariants_it_runtime_table>, + ) -> UniquePtr; + fn size(self: &MachO_FunctionVariants_it_runtime_table) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/header.rs new file mode 100644 index 0000000..dfd81d8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/header.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Header.hpp"); + + type MachO_Header; + + fn magic(self: &MachO_Header) -> u32; + fn cpu_type(self: &MachO_Header) -> i32; + fn cpu_subtype(self: &MachO_Header) -> u32; + fn file_type(self: &MachO_Header) -> u32; + fn nb_cmds(self: &MachO_Header) -> u32; + fn sizeof_cmds(self: &MachO_Header) -> u32; + fn flags(self: &MachO_Header) -> u32; + fn reserved(self: &MachO_Header) -> u32; + fn is_32bit(self: &MachO_Header) -> bool; + fn is_64bit(self: &MachO_Header) -> bool; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/indirect_binding_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/indirect_binding_info.rs new file mode 100644 index 0000000..8c1f197 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/indirect_binding_info.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/IndirectBindingInfo.hpp"); + + type MachO_BindingInfo = crate::macho::binding_info::ffi::MachO_BindingInfo; + + type MachO_IndirectBindingInfo; + + #[Self = "MachO_IndirectBindingInfo"] + fn classof(binding: &MachO_BindingInfo) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/lazy_load_dylib_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/lazy_load_dylib_info.rs new file mode 100644 index 0000000..e657f58 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/lazy_load_dylib_info.rs @@ -0,0 +1,53 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/LazyLoadDylibInfo.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_LazyLoadDylibInfo; + + #[Self = "MachO_LazyLoadDylibInfo"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_LazyLoadDylibInfo) -> u32; + fn data_size(self: &MachO_LazyLoadDylibInfo) -> u32; + fn content(self: &MachO_LazyLoadDylibInfo) -> Span; + fn load_path(self: &MachO_LazyLoadDylibInfo) -> UniquePtr; + fn flag_image_offset(self: &MachO_LazyLoadDylibInfo) -> u32; + fn flags(self: &MachO_LazyLoadDylibInfo) -> u16; + fn may_be_missing(self: &MachO_LazyLoadDylibInfo) -> bool; + fn pointer_format(self: &MachO_LazyLoadDylibInfo) -> u16; + fn chain_start_image_offset(self: &MachO_LazyLoadDylibInfo) -> u32; + fn symbols(self: &MachO_LazyLoadDylibInfo) -> UniquePtr>; + fn fixups(self: &MachO_LazyLoadDylibInfo) -> UniquePtr; + + fn set_load_path(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: &CxxString); + fn set_flag_image_offset(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: u32); + fn set_flags(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: u16); + fn set_may_be_missing(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: bool); + fn set_pointer_format(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: u16); + fn set_chain_start_image_offset(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: u32); + fn add_symbol(self: Pin<&mut MachO_LazyLoadDylibInfo>, value: &CxxString); + fn clear_symbols(self: Pin<&mut MachO_LazyLoadDylibInfo>); + + type MachO_LazyLoadDylibInfo_Fixup; + + fn address(self: &MachO_LazyLoadDylibInfo_Fixup) -> u64; + fn ordinal(self: &MachO_LazyLoadDylibInfo_Fixup) -> u32; + fn symbol(self: &MachO_LazyLoadDylibInfo_Fixup) -> UniquePtr; + fn is_auth(self: &MachO_LazyLoadDylibInfo_Fixup) -> bool; + fn to_string(self: &MachO_LazyLoadDylibInfo_Fixup) -> UniquePtr; + + type MachO_LazyLoadDylibInfo_it_fixups; + + fn next( + self: Pin<&mut MachO_LazyLoadDylibInfo_it_fixups>, + ) -> UniquePtr; + fn size(self: &MachO_LazyLoadDylibInfo_it_fixups) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/linker_opt_hint.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/linker_opt_hint.rs new file mode 100644 index 0000000..cf4103f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/linker_opt_hint.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/LinkerOptHint.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_LinkerOptHint; + + fn content(self: &MachO_LinkerOptHint) -> Span; + #[Self = "MachO_LinkerOptHint"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_LinkerOptHint) -> u32; + fn data_size(self: &MachO_LinkerOptHint) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/load_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/load_command.rs new file mode 100644 index 0000000..a9fd719 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/load_command.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/LoadCommand.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command; + + fn size(self: &MachO_Command) -> u32; + fn command_offset(self: &MachO_Command) -> u64; + fn cmd_type(self: &MachO_Command) -> u64; + fn data(self: &MachO_Command) -> Span; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/main.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/main.rs new file mode 100644 index 0000000..e2ab6f1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/main.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Main.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_Main; + + #[Self = "MachO_Main"] + fn classof(cmd: &MachO_Command) -> bool; + fn entrypoint(self: &MachO_Main) -> u64; + fn stack_size(self: &MachO_Main) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/note_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/note_command.rs new file mode 100644 index 0000000..7917983 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/note_command.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/NoteCommand.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_NoteCommand; + + #[Self = "MachO_NoteCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn note_offset(self: &MachO_NoteCommand) -> u64; + fn note_size(self: &MachO_NoteCommand) -> u64; + fn owner(self: &MachO_NoteCommand) -> Span; + fn set_note_offset(self: Pin<&mut MachO_NoteCommand>, value: u64); + fn set_note_size(self: Pin<&mut MachO_NoteCommand>, value: u64); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/r_path_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/r_path_command.rs new file mode 100644 index 0000000..57e8a6d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/r_path_command.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/RPathCommand.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_RPathCommand; + + #[Self = "MachO_RPathCommand"] + fn create(path: &CxxString) -> UniquePtr; + #[Self = "MachO_RPathCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn path(self: &MachO_RPathCommand) -> UniquePtr; + fn path_offset(self: &MachO_RPathCommand) -> u32; + fn set_path(self: Pin<&mut MachO_RPathCommand>, path: &CxxString); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation.rs new file mode 100644 index 0000000..860d37b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Relocation.hpp"); + + type MachO_Section = crate::macho::section::ffi::MachO_Section; + type MachO_SegmentCommand = crate::macho::segment_command::ffi::MachO_SegmentCommand; + type MachO_Symbol = crate::macho::symbol::ffi::MachO_Symbol; + + type MachO_Relocation; + + fn is_pc_relative(self: &MachO_Relocation) -> bool; + fn architecture(self: &MachO_Relocation) -> u32; + fn origin(self: &MachO_Relocation) -> u32; + fn symbol(self: &MachO_Relocation) -> UniquePtr; + fn section(self: &MachO_Relocation) -> UniquePtr; + fn segment(self: &MachO_Relocation) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_dyld.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_dyld.rs new file mode 100644 index 0000000..6a0bdfb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_dyld.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/RelocationDyld.hpp"); + + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + + type MachO_RelocationDyld; + + #[Self = "MachO_RelocationDyld"] + fn classof(reloc: &MachO_Relocation) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_fixup.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_fixup.rs new file mode 100644 index 0000000..81c2596 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_fixup.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/RelocationFixup.hpp"); + + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + + type MachO_RelocationFixup; + + #[Self = "MachO_RelocationFixup"] + fn classof(reloc: &MachO_Relocation) -> bool; + fn target(self: &MachO_RelocationFixup) -> u64; + fn ptr_format(self: &MachO_RelocationFixup) -> u32; + fn offset(self: &MachO_RelocationFixup) -> u32; + fn next(self: &MachO_RelocationFixup) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_object.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_object.rs new file mode 100644 index 0000000..bc9b5aa --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/relocation_object.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/RelocationObject.hpp"); + + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + + type MachO_RelocationObject; + + #[Self = "MachO_RelocationObject"] + fn classof(reloc: &MachO_Relocation) -> bool; + fn is_scattered(self: &MachO_RelocationObject) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/routine.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/routine.rs new file mode 100644 index 0000000..0c447f4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/routine.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Routine.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_Routine; + + #[Self = "MachO_Routine"] + fn classof(cmd: &MachO_Command) -> bool; + fn init_address(self: &MachO_Routine) -> u64; + fn init_module(self: &MachO_Routine) -> u64; + fn reserved1(self: &MachO_Routine) -> u64; + fn reserved2(self: &MachO_Routine) -> u64; + fn reserved3(self: &MachO_Routine) -> u64; + fn reserved4(self: &MachO_Routine) -> u64; + fn reserved5(self: &MachO_Routine) -> u64; + fn reserved6(self: &MachO_Routine) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/section.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/section.rs new file mode 100644 index 0000000..80628ba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/section.rs @@ -0,0 +1,35 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Section.hpp"); + include!("LIEF/rust/MachO/Relocation.hpp"); + + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + type MachO_SegmentCommand = crate::macho::segment_command::ffi::MachO_SegmentCommand; + + type MachO_Section; + + fn segment_name(self: &MachO_Section) -> UniquePtr; + fn address(self: &MachO_Section) -> u64; + fn alignment(self: &MachO_Section) -> u32; + fn relocation_offset(self: &MachO_Section) -> u32; + fn numberof_relocations(self: &MachO_Section) -> u32; + fn flags(self: &MachO_Section) -> u64; + fn reserved1(self: &MachO_Section) -> u32; + fn reserved2(self: &MachO_Section) -> u32; + fn reserved3(self: &MachO_Section) -> u32; + fn raw_flags(self: &MachO_Section) -> u32; + fn segment(self: &MachO_Section) -> UniquePtr; + fn relocations(self: &MachO_Section) -> UniquePtr; + fn has_segment(self: &MachO_Section) -> bool; + fn section_type(self: &MachO_Section) -> u64; + + type MachO_Section_it_relocations; + + fn next(self: Pin<&mut MachO_Section_it_relocations>) -> UniquePtr; + fn size(self: &MachO_Section_it_relocations) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_command.rs new file mode 100644 index 0000000..5255c9c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_command.rs @@ -0,0 +1,47 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SegmentCommand.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + type MachO_Relocation = crate::macho::relocation::ffi::MachO_Relocation; + type MachO_Section = crate::macho::section::ffi::MachO_Section; + + type MachO_SegmentCommand; + + fn content(self: &MachO_SegmentCommand) -> Span; + #[Self = "MachO_SegmentCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn name(self: &MachO_SegmentCommand) -> UniquePtr; + fn virtual_address(self: &MachO_SegmentCommand) -> u64; + fn virtual_size(self: &MachO_SegmentCommand) -> u64; + fn file_size(self: &MachO_SegmentCommand) -> u64; + fn file_offset(self: &MachO_SegmentCommand) -> u64; + fn max_protection(self: &MachO_SegmentCommand) -> u32; + fn init_protection(self: &MachO_SegmentCommand) -> u32; + fn numberof_sections(self: &MachO_SegmentCommand) -> u32; + fn flags(self: &MachO_SegmentCommand) -> u32; + fn sections(self: &MachO_SegmentCommand) -> UniquePtr; + fn relocations( + self: &MachO_SegmentCommand, + ) -> UniquePtr; + fn index(self: &MachO_SegmentCommand) -> i8; + fn get_section(self: &MachO_SegmentCommand, name: &CxxString) -> UniquePtr; + + type MachO_SegmentCommand_it_relocations; + + fn next(self: Pin<&mut MachO_SegmentCommand_it_relocations>) + -> UniquePtr; + fn size(self: &MachO_SegmentCommand_it_relocations) -> u64; + + type MachO_SegmentCommand_it_sections; + + fn next(self: Pin<&mut MachO_SegmentCommand_it_sections>) -> UniquePtr; + fn size(self: &MachO_SegmentCommand_it_sections) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_split_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_split_info.rs new file mode 100644 index 0000000..179c518 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/segment_split_info.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SegmentSplitInfo.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_SegmentSplitInfo; + + fn content(self: &MachO_SegmentSplitInfo) -> Span; + #[Self = "MachO_SegmentSplitInfo"] + fn classof(cmd: &MachO_Command) -> bool; + fn data_offset(self: &MachO_SegmentSplitInfo) -> u32; + fn data_size(self: &MachO_SegmentSplitInfo) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/source_version.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/source_version.rs new file mode 100644 index 0000000..a90c206 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/source_version.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SourceVersion.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_SourceVersion; + + #[Self = "MachO_SourceVersion"] + fn classof(cmd: &MachO_Command) -> bool; + fn version(self: &MachO_SourceVersion) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/stub.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/stub.rs new file mode 100644 index 0000000..a4b4637 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/stub.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Stub.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Stub; + + fn raw(self: &MachO_Stub) -> Span; + fn address(self: &MachO_Stub) -> u64; + fn target(self: &MachO_Stub, err: Pin<&mut u32>) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_client.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_client.rs new file mode 100644 index 0000000..ac30b40 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_client.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SubClient.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_SubClient; + + #[Self = "MachO_SubClient"] + fn classof(cmd: &MachO_Command) -> bool; + fn client(self: &MachO_SubClient) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_framework.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_framework.rs new file mode 100644 index 0000000..a853881 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/sub_framework.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SubFramework.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_SubFramework; + + #[Self = "MachO_SubFramework"] + fn classof(cmd: &MachO_Command) -> bool; + fn umbrella(self: &MachO_SubFramework) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol.rs new file mode 100644 index 0000000..c6baa0c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/Symbol.hpp"); + include!("LIEF/rust/MachO/ExportInfo.hpp"); + include!("LIEF/rust/MachO/BindingInfo.hpp"); + + type MachO_BindingInfo = crate::macho::binding_info::ffi::MachO_BindingInfo; + type MachO_Dylib = crate::macho::dylib::ffi::MachO_Dylib; + type MachO_ExportInfo = crate::macho::export_info::ffi::MachO_ExportInfo; + + type MachO_Symbol; + + fn get_type(self: &MachO_Symbol) -> u8; + fn numberof_sections(self: &MachO_Symbol) -> u8; + fn description(self: &MachO_Symbol) -> u16; + fn origin(self: &MachO_Symbol) -> u32; + fn category(self: &MachO_Symbol) -> u32; + fn is_external(self: &MachO_Symbol) -> bool; + fn demangled_name(self: &MachO_Symbol) -> UniquePtr; + fn export_info(self: &MachO_Symbol) -> UniquePtr; + fn binding_info(self: &MachO_Symbol) -> UniquePtr; + fn library(self: &MachO_Symbol) -> UniquePtr; + fn library_ordinal(self: &MachO_Symbol) -> i32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol_command.rs new file mode 100644 index 0000000..c8f361d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/symbol_command.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/SymbolCommand.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_SymbolCommand; + + fn string_table(self: &MachO_SymbolCommand) -> Span; + fn symbol_table(self: &MachO_SymbolCommand) -> Span; + #[Self = "MachO_SymbolCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn symbol_offset(self: &MachO_SymbolCommand) -> u32; + fn numberof_symbols(self: &MachO_SymbolCommand) -> u32; + fn strings_offset(self: &MachO_SymbolCommand) -> u32; + fn strings_size(self: &MachO_SymbolCommand) -> u32; + fn original_str_size(self: &MachO_SymbolCommand) -> u32; + fn original_nb_symbols(self: &MachO_SymbolCommand) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_command.rs new file mode 100644 index 0000000..2b73b21 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_command.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/ThreadCommand.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_ThreadCommand; + + fn state(self: &MachO_ThreadCommand) -> Span; + #[Self = "MachO_ThreadCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn flavor(self: &MachO_ThreadCommand) -> u32; + fn count(self: &MachO_ThreadCommand) -> u32; + fn architecture(self: &MachO_ThreadCommand) -> i32; + fn pc(self: &MachO_ThreadCommand) -> u64; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_local_variables.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_local_variables.rs new file mode 100644 index 0000000..6da5620 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/thread_local_variables.rs @@ -0,0 +1,45 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/ThreadLocalVariables.hpp"); + include!("LIEF/rust/MachO/Relocation.hpp"); + + type MachO_Section = crate::macho::section::ffi::MachO_Section; + + type MachO_ThreadLocalVariables; + + #[Self = "MachO_ThreadLocalVariables"] + fn classof(sec: &MachO_Section) -> bool; + fn nb_thunks(self: &MachO_ThreadLocalVariables) -> usize; + fn thunks( + self: &MachO_ThreadLocalVariables, + ) -> UniquePtr; + fn get_thunk( + self: &MachO_ThreadLocalVariables, + idx: u64, + ) -> UniquePtr; + fn set_thunk( + self: Pin<&mut MachO_ThreadLocalVariables>, + idx: u64, + func: u64, + key: u64, + offset: u64, + ); + + type MachO_ThreadLocalVariables_Thunk; + + fn key(self: &MachO_ThreadLocalVariables_Thunk) -> u64; + fn offset(self: &MachO_ThreadLocalVariables_Thunk) -> u64; + fn func(self: &MachO_ThreadLocalVariables_Thunk) -> u64; + + type MachO_ThreadLocalVariables_it_thunks; + + fn next( + self: Pin<&mut MachO_ThreadLocalVariables_it_thunks>, + ) -> UniquePtr; + fn size(self: &MachO_ThreadLocalVariables_it_thunks) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/two_level_hints.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/two_level_hints.rs new file mode 100644 index 0000000..1af46a8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/two_level_hints.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/TwoLevelHints.hpp"); + + type Span = crate::utils::ffi::Span; + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_TwoLevelHints; + + fn content(self: &MachO_TwoLevelHints) -> Span; + #[Self = "MachO_TwoLevelHints"] + fn classof(cmd: &MachO_Command) -> bool; + fn offset(self: &MachO_TwoLevelHints) -> u32; + fn original_nb_hints(self: &MachO_TwoLevelHints) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/unknown_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/unknown_command.rs new file mode 100644 index 0000000..37f099d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/unknown_command.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/UnknownCommand.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_UnknownCommand; + + #[Self = "MachO_UnknownCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn original_command(self: &MachO_UnknownCommand) -> u64; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/utils.rs new file mode 100644 index 0000000..ac222b2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/utils.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/utils.hpp"); + + type MachO_Binary = crate::macho::binary::ffi::MachO_Binary; + type MachO_FatBinary = crate::macho::fat_binary::ffi::MachO_FatBinary; + type MachO_Utils; + + #[Self = "MachO_Utils"] + fn is_macho(file: &CxxString) -> bool; + #[Self = "MachO_Utils"] + fn is_fat(file: &CxxString) -> bool; + #[Self = "MachO_Utils"] + fn is_64(file: &CxxString) -> bool; + #[Self = "MachO_Utils"] + unsafe fn check_layout(bin: &MachO_Binary, error: *mut CxxString) -> bool; + #[Self = "MachO_Utils"] + unsafe fn check_layout_fat(bin: &MachO_FatBinary, error: *mut CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/uuid_command.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/uuid_command.rs new file mode 100644 index 0000000..e58fbb4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/uuid_command.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/UUIDCommand.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_UUIDCommand; + + #[Self = "MachO_UUIDCommand"] + fn classof(cmd: &MachO_Command) -> bool; + fn uuid(self: &MachO_UUIDCommand) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/macho/version_min.rs b/vendor/lief/api/rust/crates/lief-ffi/src/macho/version_min.rs new file mode 100644 index 0000000..5d40b75 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/macho/version_min.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/MachO/VersionMin.hpp"); + + type MachO_Command = crate::macho::load_command::ffi::MachO_Command; + + type MachO_VersionMin; + + #[Self = "MachO_VersionMin"] + fn classof(cmd: &MachO_Command) -> bool; + fn version(self: &MachO_VersionMin) -> UniquePtr>; + fn sdk(self: &MachO_VersionMin) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc.rs new file mode 100644 index 0000000..f7af0c7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc.rs @@ -0,0 +1,8 @@ +pub mod category; +pub mod class; +pub mod decl_opt; +pub mod i_var; +pub mod metadata; +pub mod method; +pub mod property; +pub mod protocol; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/category.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/category.rs new file mode 100644 index 0000000..3931bf3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/category.rs @@ -0,0 +1,41 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Category.hpp"); + + type ObjC_DeclOpt = crate::objc::decl_opt::ffi::ObjC_DeclOpt; + type ObjC_Method = crate::objc::method::ffi::ObjC_Method; + type ObjC_Property = crate::objc::property::ffi::ObjC_Property; + type ObjC_Protocol = crate::objc::protocol::ffi::ObjC_Protocol; + + type ObjC_Category; + + fn name(self: &ObjC_Category) -> UniquePtr; + fn class_name(self: &ObjC_Category) -> UniquePtr; + fn methods(self: &ObjC_Category) -> UniquePtr; + fn protocols(self: &ObjC_Category) -> UniquePtr; + fn properties(self: &ObjC_Category) -> UniquePtr; + fn to_decl(self: &ObjC_Category) -> UniquePtr; + fn to_decl_with_opt(self: &ObjC_Category, opt: &ObjC_DeclOpt) -> UniquePtr; + + type ObjC_Category_it_methods; + + fn next(self: Pin<&mut ObjC_Category_it_methods>) -> UniquePtr; + fn size(self: &ObjC_Category_it_methods) -> u64; + + type ObjC_Category_it_protocols; + + fn next(self: Pin<&mut ObjC_Category_it_protocols>) -> UniquePtr; + fn size(self: &ObjC_Category_it_protocols) -> u64; + + type ObjC_Category_it_properties; + + fn next(self: Pin<&mut ObjC_Category_it_properties>) -> UniquePtr; + fn size(self: &ObjC_Category_it_properties) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/class.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/class.rs new file mode 100644 index 0000000..fbd237c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/class.rs @@ -0,0 +1,53 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Class.hpp"); + + type ObjC_DeclOpt = crate::objc::decl_opt::ffi::ObjC_DeclOpt; + type ObjC_IVar = crate::objc::i_var::ffi::ObjC_IVar; + type ObjC_Method = crate::objc::method::ffi::ObjC_Method; + type ObjC_Property = crate::objc::property::ffi::ObjC_Property; + type ObjC_Protocol = crate::objc::protocol::ffi::ObjC_Protocol; + + type ObjC_Class; + + fn to_decl_with_opt(self: &ObjC_Class, opt: &ObjC_DeclOpt) -> UniquePtr; + + fn name(self: &ObjC_Class) -> UniquePtr; + fn demangled_name(self: &ObjC_Class) -> UniquePtr; + fn is_meta(self: &ObjC_Class) -> bool; + fn super_class(self: &ObjC_Class) -> UniquePtr; + fn super_name(self: &ObjC_Class) -> UniquePtr; + fn demangled_super_name(self: &ObjC_Class) -> UniquePtr; + fn methods(self: &ObjC_Class) -> UniquePtr; + fn protocols(self: &ObjC_Class) -> UniquePtr; + fn properties(self: &ObjC_Class) -> UniquePtr; + fn ivars(self: &ObjC_Class) -> UniquePtr; + fn to_decl(self: &ObjC_Class) -> UniquePtr; + + type ObjC_Class_it_ivars; + + fn next(self: Pin<&mut ObjC_Class_it_ivars>) -> UniquePtr; + fn size(self: &ObjC_Class_it_ivars) -> u64; + + type ObjC_Class_it_methods; + + fn next(self: Pin<&mut ObjC_Class_it_methods>) -> UniquePtr; + fn size(self: &ObjC_Class_it_methods) -> u64; + + type ObjC_Class_it_properties; + + fn next(self: Pin<&mut ObjC_Class_it_properties>) -> UniquePtr; + fn size(self: &ObjC_Class_it_properties) -> u64; + + type ObjC_Class_it_protocols; + + fn next(self: Pin<&mut ObjC_Class_it_protocols>) -> UniquePtr; + fn size(self: &ObjC_Class_it_protocols) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/decl_opt.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/decl_opt.rs new file mode 100644 index 0000000..4de5332 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/decl_opt.rs @@ -0,0 +1,18 @@ +#[repr(C)] +pub struct DeclOpt { + pub show_annotations: bool, +} + +unsafe impl cxx::ExternType for DeclOpt { + type Id = cxx::type_id!("ObjC_DeclOpt"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/DeclOpt.hpp"); + + type ObjC_DeclOpt = crate::objc::decl_opt::DeclOpt; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/i_var.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/i_var.rs new file mode 100644 index 0000000..0a3811a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/i_var.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/IVar.hpp"); + + type ObjC_IVar; + + fn name(self: &ObjC_IVar) -> UniquePtr; + fn mangled_type(self: &ObjC_IVar) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/metadata.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/metadata.rs new file mode 100644 index 0000000..294ece3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/metadata.rs @@ -0,0 +1,41 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Metadata.hpp"); + + type ObjC_Class = crate::objc::class::ffi::ObjC_Class; + type ObjC_DeclOpt = crate::objc::decl_opt::ffi::ObjC_DeclOpt; + type ObjC_Protocol = crate::objc::protocol::ffi::ObjC_Protocol; + type ObjC_Category = crate::objc::category::ffi::ObjC_Category; + + type ObjC_Metadata; + + fn get_class(self: &ObjC_Metadata, name: &CxxString) -> UniquePtr; + fn get_protocol(self: &ObjC_Metadata, name: &CxxString) -> UniquePtr; + fn classes(self: &ObjC_Metadata) -> UniquePtr; + fn protocols(self: &ObjC_Metadata) -> UniquePtr; + fn categories(self: &ObjC_Metadata) -> UniquePtr; + fn to_decl(self: &ObjC_Metadata) -> UniquePtr; + fn to_decl_with_opt(self: &ObjC_Metadata, opt: &ObjC_DeclOpt) -> UniquePtr; + + type ObjC_Metadata_it_classes; + + fn next(self: Pin<&mut ObjC_Metadata_it_classes>) -> UniquePtr; + fn size(self: &ObjC_Metadata_it_classes) -> u64; + + type ObjC_Metadata_it_protocols; + + fn next(self: Pin<&mut ObjC_Metadata_it_protocols>) -> UniquePtr; + fn size(self: &ObjC_Metadata_it_protocols) -> u64; + + type ObjC_Metadata_it_categories; + + fn next(self: Pin<&mut ObjC_Metadata_it_categories>) -> UniquePtr; + fn size(self: &ObjC_Metadata_it_categories) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/method.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/method.rs new file mode 100644 index 0000000..7e3140e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/method.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Method.hpp"); + + type ObjC_Method; + + fn name(self: &ObjC_Method) -> UniquePtr; + fn mangled_type(self: &ObjC_Method) -> UniquePtr; + fn address(self: &ObjC_Method) -> u64; + fn is_instance(self: &ObjC_Method) -> bool; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/property.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/property.rs new file mode 100644 index 0000000..ade6f31 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/property.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Property.hpp"); + + type ObjC_Property; + + fn name(self: &ObjC_Property) -> UniquePtr; + fn attribute(self: &ObjC_Property) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/objc/protocol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/objc/protocol.rs new file mode 100644 index 0000000..7deb545 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/objc/protocol.rs @@ -0,0 +1,46 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/ObjC/Protocol.hpp"); + + type ObjC_DeclOpt = crate::objc::decl_opt::ffi::ObjC_DeclOpt; + type ObjC_Method = crate::objc::method::ffi::ObjC_Method; + type ObjC_Property = crate::objc::property::ffi::ObjC_Property; + + type ObjC_Protocol; + + fn mangled_name(self: &ObjC_Protocol) -> UniquePtr; + fn protocols(self: &ObjC_Protocol) -> UniquePtr; + fn optional_methods(self: &ObjC_Protocol) -> UniquePtr; + fn required_methods(self: &ObjC_Protocol) -> UniquePtr; + fn properties(self: &ObjC_Protocol) -> UniquePtr; + fn to_decl(self: &ObjC_Protocol) -> UniquePtr; + fn to_decl_with_opt(self: &ObjC_Protocol, opt: &ObjC_DeclOpt) -> UniquePtr; + + type ObjC_Protocol_it_protocols; + + fn next(self: Pin<&mut ObjC_Protocol_it_protocols>) -> UniquePtr; + fn size(self: &ObjC_Protocol_it_protocols) -> u64; + + type ObjC_Protocol_it_opt_methods; + + fn next(self: Pin<&mut ObjC_Protocol_it_opt_methods>) -> UniquePtr; + fn size(self: &ObjC_Protocol_it_opt_methods) -> u64; + + type ObjC_Protocol_it_properties; + + fn next(self: Pin<&mut ObjC_Protocol_it_properties>) -> UniquePtr; + fn size(self: &ObjC_Protocol_it_properties) -> u64; + + type ObjC_Protocol_it_req_methods; + + fn next(self: Pin<&mut ObjC_Protocol_it_req_methods>) -> UniquePtr; + fn size(self: &ObjC_Protocol_it_req_methods) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb.rs new file mode 100644 index 0000000..3b9fd4d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb.rs @@ -0,0 +1,8 @@ +pub mod build_metadata; +pub mod compilation_unit; +pub mod debug_info; +pub mod function; +pub mod public_symbol; +pub mod type_; +pub mod types; +pub mod utils; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/build_metadata.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/build_metadata.rs new file mode 100644 index 0000000..653f3eb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/build_metadata.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/BuildMetadata.hpp"); + + type PDB_BuildMetadata; + + fn frontend_version(self: &PDB_BuildMetadata) -> UniquePtr>; + fn backend_version(self: &PDB_BuildMetadata) -> UniquePtr>; + fn version(self: &PDB_BuildMetadata) -> UniquePtr; + fn language(self: &PDB_BuildMetadata) -> u8; + fn target_cpu(self: &PDB_BuildMetadata) -> u16; + fn env(self: &PDB_BuildMetadata) -> UniquePtr>; + fn build_info(self: &PDB_BuildMetadata) -> UniquePtr>; + fn to_string(self: &PDB_BuildMetadata) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/compilation_unit.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/compilation_unit.rs new file mode 100644 index 0000000..69dc56d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/compilation_unit.rs @@ -0,0 +1,36 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/CompilationUnit.hpp"); + + type PDB_BuildMetadata = crate::pdb::build_metadata::ffi::PDB_BuildMetadata; + type PDB_Function = crate::pdb::function::ffi::PDB_Function; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type PDB_CompilationUnit; + + fn module_name(self: &PDB_CompilationUnit) -> UniquePtr; + fn object_filename(self: &PDB_CompilationUnit) -> UniquePtr; + fn sources(self: &PDB_CompilationUnit) -> UniquePtr; + fn functions(self: &PDB_CompilationUnit) -> UniquePtr; + fn build_metadata(self: &PDB_CompilationUnit) -> UniquePtr; + fn to_string(self: &PDB_CompilationUnit) -> UniquePtr; + fn to_decl(self: &PDB_CompilationUnit) -> UniquePtr; + fn to_decl_with_opt(self: &PDB_CompilationUnit, opt: &LIEF_DeclOpt) + -> UniquePtr; + + type PDB_CompilationUnit_it_functions; + + fn next(self: Pin<&mut PDB_CompilationUnit_it_functions>) -> UniquePtr; + fn size(self: &PDB_CompilationUnit_it_functions) -> u64; + + type PDB_CompilationUnit_it_sources; + + fn next(self: Pin<&mut PDB_CompilationUnit_it_sources>) -> UniquePtr; + fn size(self: &PDB_CompilationUnit_it_sources) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/debug_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/debug_info.rs new file mode 100644 index 0000000..a3ae49c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/debug_info.rs @@ -0,0 +1,52 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/DebugInfo.hpp"); + + type AbstracDebugInfo = crate::generic::debug_info::ffi::AbstracDebugInfo; + type PDB_CompilationUnit = crate::pdb::compilation_unit::ffi::PDB_CompilationUnit; + type PDB_PublicSymbol = crate::pdb::public_symbol::ffi::PDB_PublicSymbol; + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_DebugInfo; + + #[Self = "PDB_DebugInfo"] + fn from_file(file: &CxxString) -> UniquePtr; + #[Self = "PDB_DebugInfo"] + fn classof(reloc: &AbstracDebugInfo) -> bool; + fn age(self: &PDB_DebugInfo) -> u32; + fn guid(self: &PDB_DebugInfo) -> UniquePtr; + fn compilation_units(self: &PDB_DebugInfo) + -> UniquePtr; + fn public_symbols(self: &PDB_DebugInfo) -> UniquePtr; + fn types(self: &PDB_DebugInfo) -> UniquePtr; + fn public_symbol_by_name( + self: &PDB_DebugInfo, + name: &CxxString, + ) -> UniquePtr; + fn find_type(self: &PDB_DebugInfo, name: &CxxString) -> UniquePtr; + fn to_string(self: &PDB_DebugInfo) -> UniquePtr; + fn find_type_by_index(self: &PDB_DebugInfo, index: u32) -> UniquePtr; + + type PDB_DebugInfo_it_compilation_units; + + fn next( + self: Pin<&mut PDB_DebugInfo_it_compilation_units>, + ) -> UniquePtr; + fn size(self: &PDB_DebugInfo_it_compilation_units) -> u64; + + type PDB_DebugInfo_it_public_symbols; + + fn next(self: Pin<&mut PDB_DebugInfo_it_public_symbols>) -> UniquePtr; + fn size(self: &PDB_DebugInfo_it_public_symbols) -> u64; + + type PDB_DebugInfo_it_types; + + fn next(self: Pin<&mut PDB_DebugInfo_it_types>) -> UniquePtr; + fn size(self: &PDB_DebugInfo_it_types) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/function.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/function.rs new file mode 100644 index 0000000..cf0b34b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/function.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/Function.hpp"); + + type DebugLocation = crate::debug_location::ffi::DebugLocation; + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type PDB_Function; + + fn name(self: &PDB_Function) -> UniquePtr; + fn RVA(self: &PDB_Function) -> u32; + fn code_size(self: &PDB_Function) -> u32; + fn section_name(self: &PDB_Function) -> UniquePtr; + fn debug_location(self: &PDB_Function) -> UniquePtr; + fn to_string(self: &PDB_Function) -> UniquePtr; + fn to_decl(self: &PDB_Function) -> UniquePtr; + fn to_decl_with_opt(self: &PDB_Function, opt: &LIEF_DeclOpt) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/public_symbol.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/public_symbol.rs new file mode 100644 index 0000000..11e6781 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/public_symbol.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/PublicSymbol.hpp"); + + type PDB_PublicSymbol; + + fn name(self: &PDB_PublicSymbol) -> UniquePtr; + fn demangled_name(self: &PDB_PublicSymbol) -> UniquePtr; + fn section_name(self: &PDB_PublicSymbol) -> UniquePtr; + fn RVA(self: &PDB_PublicSymbol) -> u32; + fn to_string(self: &PDB_PublicSymbol) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/type_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/type_.rs new file mode 100644 index 0000000..a043c43 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/type_.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/Type.hpp"); + + type LIEF_DeclOpt = crate::debug_decl_opt::ffi::LIEF_DeclOpt; + + type PDB_Type; + + fn kind(self: &PDB_Type) -> u32; + fn name(self: &PDB_Type, is_set: Pin<&mut u32>) -> UniquePtr; + fn size(self: &PDB_Type, is_set: Pin<&mut u32>) -> u64; + fn to_decl(self: &PDB_Type) -> UniquePtr; + fn to_decl_with_opt(self: &PDB_Type, opt: &LIEF_DeclOpt) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types.rs new file mode 100644 index 0000000..fcb74a1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types.rs @@ -0,0 +1,11 @@ +pub mod array; +pub mod attribute; +pub mod bit_field; +pub mod class_like; +pub mod enum_; +pub mod function; +pub mod method; +pub mod modifier; +pub mod pointer; +pub mod simple; +pub mod union_; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/array.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/array.rs new file mode 100644 index 0000000..4a5c941 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/array.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Array.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Array; + + #[Self = "PDB_types_Array"] + fn classof(type_: &PDB_Type) -> bool; + fn numberof_elements(self: &PDB_types_Array) -> u64; + fn element_type(self: &PDB_types_Array) -> UniquePtr; + fn index_type(self: &PDB_types_Array) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/attribute.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/attribute.rs new file mode 100644 index 0000000..1271b20 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/attribute.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Attribute.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Attribute; + + fn name(self: &PDB_types_Attribute) -> UniquePtr; + fn field_offset(self: &PDB_types_Attribute) -> u64; + fn get_type(self: &PDB_types_Attribute) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/bit_field.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/bit_field.rs new file mode 100644 index 0000000..b609568 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/bit_field.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/BitField.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_BitField; + + #[Self = "PDB_types_BitField"] + fn classof(type_: &PDB_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/class_like.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/class_like.rs new file mode 100644 index 0000000..bb22077 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/class_like.rs @@ -0,0 +1,49 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/ClassLike.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + type PDB_types_Attribute = crate::pdb::types::attribute::ffi::PDB_types_Attribute; + type PDB_types_Method = crate::pdb::types::method::ffi::PDB_types_Method; + + type PDB_types_Class; + + #[Self = "PDB_types_Class"] + fn classof(type_: &PDB_Type) -> bool; + + type PDB_types_ClassLike; + + fn unique_name(self: &PDB_types_ClassLike) -> UniquePtr; + fn attributes(self: &PDB_types_ClassLike) -> UniquePtr; + fn methods(self: &PDB_types_ClassLike) -> UniquePtr; + + type PDB_types_ClassLike_it_attributes; + + fn next( + self: Pin<&mut PDB_types_ClassLike_it_attributes>, + ) -> UniquePtr; + fn size(self: &PDB_types_ClassLike_it_attributes) -> u64; + + type PDB_types_ClassLike_it_methods; + + fn next(self: Pin<&mut PDB_types_ClassLike_it_methods>) -> UniquePtr; + fn size(self: &PDB_types_ClassLike_it_methods) -> u64; + + type PDB_types_Interface; + + #[Self = "PDB_types_Interface"] + fn classof(type_: &PDB_Type) -> bool; + + type PDB_types_Structure; + + #[Self = "PDB_types_Structure"] + fn classof(type_: &PDB_Type) -> bool; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/enum_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/enum_.rs new file mode 100644 index 0000000..ee5c865 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/enum_.rs @@ -0,0 +1,30 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Enum.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Enum; + + #[Self = "PDB_types_Enum"] + fn classof(type_: &PDB_Type) -> bool; + fn entries(self: &PDB_types_Enum) -> UniquePtr; + fn underlying_type(self: &PDB_types_Enum) -> UniquePtr; + fn find_entry(self: &PDB_types_Enum, value: i64) -> UniquePtr; + fn unique_name(self: &PDB_types_Enum) -> UniquePtr; + + type PDB_types_Enum_Entry; + + fn name(self: &PDB_types_Enum_Entry) -> UniquePtr; + fn value(self: &PDB_types_Enum_Entry) -> i64; + + type PDB_types_Enum_it_entries; + + fn next(self: Pin<&mut PDB_types_Enum_it_entries>) -> UniquePtr; + fn size(self: &PDB_types_Enum_it_entries) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/function.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/function.rs new file mode 100644 index 0000000..2ee8cc1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/function.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Function.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Function; + + #[Self = "PDB_types_Function"] + fn classof(type_: &PDB_Type) -> bool; + fn return_type(self: &PDB_types_Function) -> UniquePtr; + fn parameters(self: &PDB_types_Function) -> UniquePtr; + + type PDB_types_Function_it_parameters; + + fn next(self: Pin<&mut PDB_types_Function_it_parameters>) -> UniquePtr; + fn size(self: &PDB_types_Function_it_parameters) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/method.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/method.rs new file mode 100644 index 0000000..ec4c10f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/method.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Method.hpp"); + + type PDB_types_Method; + + fn name(self: &PDB_types_Method) -> UniquePtr; + fn get_type(self: &PDB_types_Method) -> u32; + fn access(self: &PDB_types_Method) -> u8; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/modifier.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/modifier.rs new file mode 100644 index 0000000..23a6959 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/modifier.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Modifier.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Modifier; + + #[Self = "PDB_types_Modifier"] + fn classof(type_: &PDB_Type) -> bool; + fn underlying_type(self: &PDB_types_Modifier) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/pointer.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/pointer.rs new file mode 100644 index 0000000..ebacb14 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/pointer.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Pointer.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Pointer; + + #[Self = "PDB_types_Pointer"] + fn classof(type_: &PDB_Type) -> bool; + fn underlying_type(self: &PDB_types_Pointer) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/simple.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/simple.rs new file mode 100644 index 0000000..1d4c137 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/simple.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Simple.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Simple; + + #[Self = "PDB_types_Simple"] + fn classof(type_: &PDB_Type) -> bool; + fn get_type(self: &PDB_types_Simple) -> u32; + fn modes(self: &PDB_types_Simple) -> u32; + fn is_pointer(self: &PDB_types_Simple) -> bool; + fn is_signed(self: &PDB_types_Simple) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/union_.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/union_.rs new file mode 100644 index 0000000..6135e37 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/types/union_.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/types/Union.hpp"); + + type PDB_Type = crate::pdb::type_::ffi::PDB_Type; + + type PDB_types_Union; + + #[Self = "PDB_types_Union"] + fn classof(type_: &PDB_Type) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pdb/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/utils.rs new file mode 100644 index 0000000..4d8796d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pdb/utils.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PDB/utils.hpp"); + + type PDB_Utils; + + #[Self = "PDB_Utils"] + fn is_pdb(file: &CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe.rs new file mode 100644 index 0000000..17df377 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe.rs @@ -0,0 +1,34 @@ +pub mod binary; +pub mod code_integrity; +pub mod data_directories; +pub mod debug; +pub mod delay_import; +pub mod delay_import_entry; +pub mod dos_header; +pub mod exception_info; +pub mod export; +pub mod export_entry; +pub mod factory; +pub mod header; +pub mod import; +pub mod import_entry; +pub mod load_configuration; +pub mod optional_header; +pub mod relocation; +pub mod relocation_entry; +pub mod resource_accelerator; +pub mod resource_data; +pub mod resource_directory; +pub mod resource_icon; +pub mod resource_node; +pub mod resource_version; +pub mod resources_manager; +pub mod rich_entry; +pub mod rich_header; +pub mod runtime_function_a_arch64; +pub mod runtime_function_x64; +pub mod section; +pub mod signature; +pub mod tls; +pub mod unwind_code_x64; +pub mod utils; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/binary.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/binary.rs new file mode 100644 index 0000000..96a7e26 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/binary.rs @@ -0,0 +1,244 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Binary.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type Span = crate::utils::ffi::Span; + type AbstractBinary_it_functions = crate::generic::binary::ffi::AbstractBinary_it_functions; + type COFF_String = crate::coff::string::ffi::COFF_String; + type COFF_Symbol = crate::coff::symbol::ffi::COFF_Symbol; + type PE_CodeViewPDB = crate::pe::debug::code_view_pdb::ffi::PE_CodeViewPDB; + type PE_DataDirectory = crate::pe::data_directories::ffi::PE_DataDirectory; + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + type PE_DelayImport = crate::pe::delay_import::ffi::PE_DelayImport; + type PE_DosHeader = crate::pe::dos_header::ffi::PE_DosHeader; + type PE_ExceptionInfo = crate::pe::exception_info::ffi::PE_ExceptionInfo; + type PE_Export = crate::pe::export::ffi::PE_Export; + type PE_Header = crate::pe::header::ffi::PE_Header; + type PE_Import = crate::pe::import::ffi::PE_Import; + type PE_LoadConfiguration = + crate::pe::load_configuration::load_configuration::ffi::PE_LoadConfiguration; + type PE_OptionalHeader = crate::pe::optional_header::ffi::PE_OptionalHeader; + type PE_Relocation = crate::pe::relocation::ffi::PE_Relocation; + type PE_ResourceNode = crate::pe::resource_node::ffi::PE_ResourceNode; + type PE_ResourcesManager = crate::pe::resources_manager::ffi::PE_ResourcesManager; + type PE_RichHeader = crate::pe::rich_header::ffi::PE_RichHeader; + type PE_Section = crate::pe::section::ffi::PE_Section; + type PE_Signature = crate::pe::signature::signature::ffi::PE_Signature; + type PE_TLS = crate::pe::tls::ffi::PE_TLS; + + type PE_Binary; + + fn get_content_from_virtual_address( + self: &PE_Binary, + virtual_address: u64, + size: u64, + ) -> Span; + fn dos_stub(self: &PE_Binary) -> Span; + fn overlay(self: &PE_Binary) -> Span; + #[Self = "PE_Binary"] + fn parse(path: &CxxString) -> UniquePtr; + #[Self = "PE_Binary"] + fn parse_with_config(path: &CxxString, config: &PE_ParserConfig) -> UniquePtr; + #[Self = "PE_Binary"] + fn parse_from_memory(addr: u64) -> UniquePtr; + #[Self = "PE_Binary"] + fn parse_from_memory_with_config( + addr: u64, + config: &PE_ParserConfig, + ) -> UniquePtr; + #[Self = "PE_Binary"] + fn parse_from_dump(path: &CxxString, addr: u64) -> UniquePtr; + #[Self = "PE_Binary"] + fn parse_from_dump_with_config( + path: &CxxString, + addr: u64, + config: &PE_ParserConfig, + ) -> UniquePtr; + fn debug(self: &PE_Binary) -> UniquePtr; + fn signatures(self: &PE_Binary) -> UniquePtr; + fn sections(self: &PE_Binary) -> UniquePtr; + fn relocations(self: &PE_Binary) -> UniquePtr; + fn imports(self: &PE_Binary) -> UniquePtr; + fn delay_imports(self: &PE_Binary) -> UniquePtr; + fn data_directories(self: &PE_Binary) -> UniquePtr; + fn tls(self: &PE_Binary) -> UniquePtr; + fn rich_header(self: &PE_Binary) -> UniquePtr; + fn get_export(self: &PE_Binary) -> UniquePtr; + fn resources(self: &PE_Binary) -> UniquePtr; + fn load_configuration(self: &PE_Binary) -> UniquePtr; + fn dos_header(self: &PE_Binary) -> UniquePtr; + fn header(self: &PE_Binary) -> UniquePtr; + fn optional_header(self: &PE_Binary) -> UniquePtr; + fn compute_checksum(self: &PE_Binary) -> u32; + fn resources_manager(self: &PE_Binary) -> UniquePtr; + fn verify_signature(self: &PE_Binary, flags: u32) -> u32; + fn authentihash(self: &PE_Binary, algo: u32) -> UniquePtr>; + fn overlay_offset(self: &PE_Binary) -> u64; + fn rva_to_offset(self: &PE_Binary, rva: u64) -> u64; + fn va_to_offset(self: &PE_Binary, rva: u64) -> u64; + fn offset_to_rva(self: &PE_Binary, offset: u64) -> u64; + fn virtual_size(self: &PE_Binary) -> u64; + fn sizeof_headers(self: &PE_Binary) -> u64; + fn section_from_offset(self: &PE_Binary, offset: u64) -> UniquePtr; + fn section_from_rva(self: &PE_Binary, address: u64) -> UniquePtr; + fn section_by_name(self: &PE_Binary, name: &CxxString) -> UniquePtr; + fn add_section(self: Pin<&mut PE_Binary>, section: &PE_Section) -> UniquePtr; + fn import_by_name(self: &PE_Binary, name: &CxxString) -> UniquePtr; + fn delay_import_by_name(self: &PE_Binary, name: &CxxString) -> UniquePtr; + fn export_dir(self: &PE_Binary) -> UniquePtr; + fn import_dir(self: &PE_Binary) -> UniquePtr; + fn rsrc_dir(self: &PE_Binary) -> UniquePtr; + fn exceptions_dir(self: &PE_Binary) -> UniquePtr; + fn cert_dir(self: &PE_Binary) -> UniquePtr; + fn relocation_dir(self: &PE_Binary) -> UniquePtr; + fn debug_dir(self: &PE_Binary) -> UniquePtr; + fn tls_dir(self: &PE_Binary) -> UniquePtr; + fn load_config_dir(self: &PE_Binary) -> UniquePtr; + fn iat_dir(self: &PE_Binary) -> UniquePtr; + fn delay_dir(self: &PE_Binary) -> UniquePtr; + fn functions(self: &PE_Binary) -> UniquePtr; + fn add_import(self: Pin<&mut PE_Binary>, name: &CxxString) -> UniquePtr; + fn add_import_pos( + self: Pin<&mut PE_Binary>, + name: &CxxString, + pos: u32, + ) -> UniquePtr; + fn remove_import(self: Pin<&mut PE_Binary>, name: &CxxString); + fn remove_all_imports(self: Pin<&mut PE_Binary>); + fn remove_tls(self: Pin<&mut PE_Binary>); + fn set_tls(self: Pin<&mut PE_Binary>, tls: &PE_TLS); + fn set_resources(self: Pin<&mut PE_Binary>, node: &PE_ResourceNode); + fn add_debug_info(self: Pin<&mut PE_Binary>, entry: &PE_Debug) -> UniquePtr; + fn remove_debug(self: Pin<&mut PE_Binary>, entry: &PE_Debug) -> bool; + fn clear_debug(self: Pin<&mut PE_Binary>) -> bool; + fn codeview_pdb(self: &PE_Binary) -> UniquePtr; + fn coff_string_table(self: &PE_Binary) -> UniquePtr; + fn symbols(self: &PE_Binary) -> UniquePtr; + fn exceptions(self: &PE_Binary) -> UniquePtr; + fn find_exception_at(self: &PE_Binary, rva: u32) -> UniquePtr; + fn is_arm64x(self: &PE_Binary) -> bool; + fn is_arm64ec(self: &PE_Binary) -> bool; + fn nested_pe_binary(self: &PE_Binary) -> UniquePtr; + fn write(self: Pin<&mut PE_Binary>, output: &CxxString); + fn write_with_config( + self: Pin<&mut PE_Binary>, + output: &CxxString, + config: &PE_Binary_write_config_t, + ); + fn write_to_bytes(self: Pin<&mut PE_Binary>) -> UniquePtr>; + fn write_to_bytes_with_config( + self: Pin<&mut PE_Binary>, + config: &PE_Binary_write_config_t, + ) -> UniquePtr>; + fn set_export(self: Pin<&mut PE_Binary>, exp: &PE_Export); + fn is_reproducible_build(self: &PE_Binary) -> bool; + fn has_import(self: &PE_Binary, name: &CxxString) -> bool; + fn has_delay_import(self: &PE_Binary, name: &CxxString) -> bool; + fn exception_functions(self: &PE_Binary) -> UniquePtr; + fn remove_section(self: Pin<&mut PE_Binary>, name: &CxxString, clear: bool); + fn fill_address(self: Pin<&mut PE_Binary>, address: u64, size: u64, value: u8); + fn remove_all_relocations(self: Pin<&mut PE_Binary>); + fn verify_with_signature(self: &PE_Binary, sig: &PE_Signature, flags: u32) -> u32; + fn data_directory_by_type(self: &PE_Binary, type_: u32) -> UniquePtr; + fn find_coff_string_at(self: &PE_Binary, offset: u32) -> UniquePtr; + + type PE_Binary_it_data_directories; + + fn next(self: Pin<&mut PE_Binary_it_data_directories>) -> UniquePtr; + fn size(self: &PE_Binary_it_data_directories) -> u64; + + type PE_Binary_it_debug; + + fn next(self: Pin<&mut PE_Binary_it_debug>) -> UniquePtr; + fn size(self: &PE_Binary_it_debug) -> u64; + + type PE_Binary_it_delay_imports; + + fn next(self: Pin<&mut PE_Binary_it_delay_imports>) -> UniquePtr; + fn size(self: &PE_Binary_it_delay_imports) -> u64; + + type PE_Binary_it_exceptions; + + fn next(self: Pin<&mut PE_Binary_it_exceptions>) -> UniquePtr; + fn size(self: &PE_Binary_it_exceptions) -> u64; + + type PE_Binary_it_imports; + + fn next(self: Pin<&mut PE_Binary_it_imports>) -> UniquePtr; + fn size(self: &PE_Binary_it_imports) -> u64; + + type PE_Binary_it_relocations; + + fn next(self: Pin<&mut PE_Binary_it_relocations>) -> UniquePtr; + fn size(self: &PE_Binary_it_relocations) -> u64; + + type PE_Binary_it_sections; + + fn next(self: Pin<&mut PE_Binary_it_sections>) -> UniquePtr; + fn size(self: &PE_Binary_it_sections) -> u64; + + type PE_Binary_it_signatures; + + fn next(self: Pin<&mut PE_Binary_it_signatures>) -> UniquePtr; + fn size(self: &PE_Binary_it_signatures) -> u64; + + type PE_Binary_it_strings_table; + + fn next(self: Pin<&mut PE_Binary_it_strings_table>) -> UniquePtr; + fn size(self: &PE_Binary_it_strings_table) -> u64; + + type PE_Binary_it_symbols; + + fn next(self: Pin<&mut PE_Binary_it_symbols>) -> UniquePtr; + fn size(self: &PE_Binary_it_symbols) -> u64; + + type PE_Binary_write_config_t; + + #[Self = "PE_Binary_write_config_t"] + fn create() -> UniquePtr; + fn set_resources(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_overlay(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_rsrc_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_idata_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_tls_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_reloc_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_export_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_debug_section(self: Pin<&mut PE_Binary_write_config_t>, sec: &CxxString); + fn set_import(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_exports(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_relocations(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_load_config(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_tls(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_debug(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + fn set_dos_stub(self: Pin<&mut PE_Binary_write_config_t>, value: bool); + + type PE_ParserConfig; + + #[Self = "PE_ParserConfig"] + fn create() -> UniquePtr; + fn set_parse_signature(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_exports(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_imports(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_rsrc(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_reloc(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_exceptions(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_parse_arm64x_binary(self: Pin<&mut PE_ParserConfig>, value: bool); + fn set_rebase(self: Pin<&mut PE_ParserConfig>, value: u64); + fn clear_rebase(self: Pin<&mut PE_ParserConfig>); + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/code_integrity.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/code_integrity.rs new file mode 100644 index 0000000..175ee07 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/code_integrity.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/CodeIntegrity.hpp"); + + type PE_CodeIntegrity; + + fn flags(self: &PE_CodeIntegrity) -> u16; + fn catalog(self: &PE_CodeIntegrity) -> u16; + fn catalog_offset(self: &PE_CodeIntegrity) -> u32; + fn reserved(self: &PE_CodeIntegrity) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/data_directories.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/data_directories.rs new file mode 100644 index 0000000..6bddccc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/data_directories.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/DataDirectories.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Section = crate::pe::section::ffi::PE_Section; + + type PE_DataDirectory; + + fn content(self: &PE_DataDirectory) -> Span; + fn RVA(self: &PE_DataDirectory) -> u32; + fn size(self: &PE_DataDirectory) -> u32; + fn get_type(self: &PE_DataDirectory) -> u32; + fn section(self: &PE_DataDirectory) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug.rs new file mode 100644 index 0000000..5ae4868 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug.rs @@ -0,0 +1,10 @@ +pub mod code_view; +pub mod code_view_pdb; +pub mod debug; +pub mod ex_dll_characteristics; +pub mod fpo; +pub mod pdb_checksum; +pub mod pogo; +pub mod pogo_entry; +pub mod repro; +pub mod vc_feature; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view.rs new file mode 100644 index 0000000..5a6ef76 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/CodeView.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_CodeView; + + #[Self = "PE_CodeView"] + fn classof(entry: &PE_Debug) -> bool; + fn signature(self: &PE_CodeView) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view_pdb.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view_pdb.rs new file mode 100644 index 0000000..3c7d357 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/code_view_pdb.rs @@ -0,0 +1,25 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/CodeViewPDB.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_CodeViewPDB; + + #[Self = "PE_CodeViewPDB"] + fn create() -> UniquePtr; + #[Self = "PE_CodeViewPDB"] + fn create_with_filename(filename: &CxxString) -> UniquePtr; + #[Self = "PE_CodeViewPDB"] + fn classof(entry: &PE_Debug) -> bool; + fn age(self: &PE_CodeViewPDB) -> u32; + fn guid(self: &PE_CodeViewPDB) -> UniquePtr; + fn filename(self: &PE_CodeViewPDB) -> UniquePtr; + fn signature(self: &PE_CodeViewPDB) -> UniquePtr>; + fn set_filename(self: Pin<&mut PE_CodeViewPDB>, filename: &CxxString); + fn set_age(self: Pin<&mut PE_CodeViewPDB>, age: u32); + unsafe fn set_signature(self: Pin<&mut PE_CodeViewPDB>, array: *const u8, size: usize); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/debug.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/debug.rs new file mode 100644 index 0000000..90f1d5d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/debug.rs @@ -0,0 +1,29 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/Debug.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Section = crate::pe::section::ffi::PE_Section; + + type PE_Debug; + + fn payload(self: &PE_Debug) -> Span; + + fn characteristics(self: &PE_Debug) -> u32; + fn timestamp(self: &PE_Debug) -> u32; + fn major_version(self: &PE_Debug) -> u16; + fn minor_version(self: &PE_Debug) -> u16; + fn get_type(self: &PE_Debug) -> u32; + fn sizeof_data(self: &PE_Debug) -> u32; + fn addressof_rawdata(self: &PE_Debug) -> u32; + fn pointerto_rawdata(self: &PE_Debug) -> u32; + fn section(self: &PE_Debug) -> UniquePtr; + fn set_characteristics(self: Pin<&mut PE_Debug>, value: u32); + fn set_timestamp(self: Pin<&mut PE_Debug>, value: u32); + fn set_major_version(self: Pin<&mut PE_Debug>, value: u16); + fn set_minor_version(self: Pin<&mut PE_Debug>, value: u16); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/ex_dll_characteristics.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/ex_dll_characteristics.rs new file mode 100644 index 0000000..b8e36eb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/ex_dll_characteristics.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/ExDllCharacteristics.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_ExDllCharacteristics; + + #[Self = "PE_ExDllCharacteristics"] + fn classof(entry: &PE_Debug) -> bool; + fn characteristics(self: &PE_ExDllCharacteristics) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/fpo.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/fpo.rs new file mode 100644 index 0000000..730a6b6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/fpo.rs @@ -0,0 +1,36 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/FPO.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_FPO; + + #[Self = "PE_FPO"] + fn classof(entry: &PE_Debug) -> bool; + fn entries(self: &PE_FPO) -> UniquePtr; + + type PE_FPO_entry_t; + + fn rva(self: &PE_FPO_entry_t) -> u32; + fn reserved(self: &PE_FPO_entry_t) -> u16; + fn get_type(self: &PE_FPO_entry_t) -> u32; + fn to_string(self: &PE_FPO_entry_t) -> UniquePtr; + fn proc_size(self: &PE_FPO_entry_t) -> u32; + fn nb_locals(self: &PE_FPO_entry_t) -> u32; + fn parameters_size(self: &PE_FPO_entry_t) -> u32; + fn prolog_size(self: &PE_FPO_entry_t) -> u16; + fn nb_saved_regs(self: &PE_FPO_entry_t) -> u16; + fn use_seh(self: &PE_FPO_entry_t) -> bool; + fn use_bp(self: &PE_FPO_entry_t) -> bool; + + type PE_FPO_it_entries; + + fn next(self: Pin<&mut PE_FPO_it_entries>) -> UniquePtr; + fn size(self: &PE_FPO_it_entries) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pdb_checksum.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pdb_checksum.rs new file mode 100644 index 0000000..f5ffc52 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pdb_checksum.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/PDBChecksum.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_PDBChecksum; + + fn hash(self: &PE_PDBChecksum) -> Span; + #[Self = "PE_PDBChecksum"] + fn classof(entry: &PE_Debug) -> bool; + fn algo(self: &PE_PDBChecksum) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo.rs new file mode 100644 index 0000000..269d11b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/Pogo.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + type PE_PogoEntry = crate::pe::debug::pogo_entry::ffi::PE_PogoEntry; + + type PE_Pogo; + + #[Self = "PE_Pogo"] + fn classof(entry: &PE_Debug) -> bool; + fn entries(self: &PE_Pogo) -> UniquePtr; + fn pogo_signature(self: &PE_Pogo) -> u32; + + type PE_Pogo_it_entries; + + fn next(self: Pin<&mut PE_Pogo_it_entries>) -> UniquePtr; + fn size(self: &PE_Pogo_it_entries) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo_entry.rs new file mode 100644 index 0000000..6a81de8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/pogo_entry.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/PogoEntry.hpp"); + + type PE_PogoEntry; + + fn start_rva(self: &PE_PogoEntry) -> u32; + fn size(self: &PE_PogoEntry) -> u32; + fn name(self: &PE_PogoEntry) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/repro.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/repro.rs new file mode 100644 index 0000000..aad927a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/repro.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/Repro.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_Repro; + + fn hash(self: &PE_Repro) -> Span; + #[Self = "PE_Repro"] + fn classof(entry: &PE_Debug) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/vc_feature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/vc_feature.rs new file mode 100644 index 0000000..1c61af6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/debug/vc_feature.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/debug/VCFeature.hpp"); + + type PE_Debug = crate::pe::debug::debug::ffi::PE_Debug; + + type PE_VCFeature; + + #[Self = "PE_VCFeature"] + fn classof(entry: &PE_Debug) -> bool; + fn pre_vcpp(self: &PE_VCFeature) -> u32; + fn c_cpp(self: &PE_VCFeature) -> u32; + fn gs(self: &PE_VCFeature) -> u32; + fn sdl(self: &PE_VCFeature) -> u32; + fn guards(self: &PE_VCFeature) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import.rs new file mode 100644 index 0000000..b319c3e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/DelayImport.hpp"); + + type PE_DelayImportEntry = crate::pe::delay_import_entry::ffi::PE_DelayImportEntry; + + type PE_DelayImport; + + fn attribute(self: &PE_DelayImport) -> u32; + fn name(self: &PE_DelayImport) -> UniquePtr; + fn handle(self: &PE_DelayImport) -> u32; + fn iat(self: &PE_DelayImport) -> u32; + fn names_table(self: &PE_DelayImport) -> u32; + fn biat(self: &PE_DelayImport) -> u32; + fn uiat(self: &PE_DelayImport) -> u32; + fn timestamp(self: &PE_DelayImport) -> u32; + fn entries(self: &PE_DelayImport) -> UniquePtr; + + type PE_DelayImport_it_entries; + + fn next(self: Pin<&mut PE_DelayImport_it_entries>) -> UniquePtr; + fn size(self: &PE_DelayImport_it_entries) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import_entry.rs new file mode 100644 index 0000000..0d8f578 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/delay_import_entry.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/DelayImportEntry.hpp"); + + type PE_DelayImportEntry; + + fn is_ordinal(self: &PE_DelayImportEntry) -> bool; + fn ordinal(self: &PE_DelayImportEntry) -> u16; + fn hint_name_rva(self: &PE_DelayImportEntry) -> u64; + fn hint(self: &PE_DelayImportEntry) -> u16; + fn iat_value(self: &PE_DelayImportEntry) -> u64; + fn data(self: &PE_DelayImportEntry) -> u64; + fn demangled_name(self: &PE_DelayImportEntry) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/dos_header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/dos_header.rs new file mode 100644 index 0000000..f3a11c1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/dos_header.rs @@ -0,0 +1,30 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/DosHeader.hpp"); + + type PE_DosHeader; + + fn magic(self: &PE_DosHeader) -> u16; + fn used_bytes_in_last_page(self: &PE_DosHeader) -> u16; + fn file_size_in_pages(self: &PE_DosHeader) -> u16; + fn numberof_relocation(self: &PE_DosHeader) -> u16; + fn header_size_in_paragraphs(self: &PE_DosHeader) -> u16; + fn minimum_extra_paragraphs(self: &PE_DosHeader) -> u16; + fn maximum_extra_paragraphs(self: &PE_DosHeader) -> u16; + fn initial_relative_ss(self: &PE_DosHeader) -> u16; + fn initial_sp(self: &PE_DosHeader) -> u16; + fn checksum(self: &PE_DosHeader) -> u16; + fn initial_ip(self: &PE_DosHeader) -> u16; + fn initial_relative_cs(self: &PE_DosHeader) -> u16; + fn addressof_relocation_table(self: &PE_DosHeader) -> u16; + fn overlay_number(self: &PE_DosHeader) -> u16; + fn reserved(self: &PE_DosHeader) -> UniquePtr>; + fn oem_id(self: &PE_DosHeader) -> u16; + fn oem_info(self: &PE_DosHeader) -> u16; + fn reserved2(self: &PE_DosHeader) -> UniquePtr>; + fn addressof_new_exeheader(self: &PE_DosHeader) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/exception_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/exception_info.rs new file mode 100644 index 0000000..41337da --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/exception_info.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ExceptionInfo.hpp"); + + type PE_ExceptionInfo; + + fn rva_start(self: &PE_ExceptionInfo) -> u32; + fn offset(self: &PE_ExceptionInfo) -> u64; + fn to_string(self: &PE_ExceptionInfo) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/export.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/export.rs new file mode 100644 index 0000000..d52c362 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/export.rs @@ -0,0 +1,53 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Export.hpp"); + + type PE_ExportEntry = crate::pe::export_entry::ffi::PE_ExportEntry; + + type PE_Export; + + #[Self = "PE_Export"] + fn create() -> UniquePtr; + fn export_flags(self: &PE_Export) -> u32; + fn timestamp(self: &PE_Export) -> u32; + fn major_version(self: &PE_Export) -> u16; + fn minor_version(self: &PE_Export) -> u16; + fn ordinal_base(self: &PE_Export) -> u32; + fn name_rva(self: &PE_Export) -> u32; + fn export_addr_table_rva(self: &PE_Export) -> u32; + fn export_addr_table_cnt(self: &PE_Export) -> u32; + fn names_addr_table_rva(self: &PE_Export) -> u32; + fn names_addr_table_cnt(self: &PE_Export) -> u32; + fn ord_addr_table_rva(self: &PE_Export) -> u32; + fn name(self: &PE_Export) -> UniquePtr; + fn entries(self: &PE_Export) -> UniquePtr; + fn set_name(self: Pin<&mut PE_Export>, name: &CxxString); + fn entry_by_name(self: &PE_Export, name: &CxxString) -> UniquePtr; + fn add_entry( + self: Pin<&mut PE_Export>, + entry: &PE_ExportEntry, + ) -> UniquePtr; + fn add_entry_by_name( + self: Pin<&mut PE_Export>, + name: &CxxString, + rva: u32, + ) -> UniquePtr; + fn remove_entry(self: Pin<&mut PE_Export>, entry: UniquePtr) -> bool; + fn remove_entry_by_name(self: Pin<&mut PE_Export>, name: &CxxString) -> bool; + fn set_export_flags(self: Pin<&mut PE_Export>, flags: u32); + fn set_timestamp(self: Pin<&mut PE_Export>, ts: u32); + fn set_major_version(self: Pin<&mut PE_Export>, version: u32); + fn set_minor_version(self: Pin<&mut PE_Export>, version: u32); + fn entry_by_ordinal(self: &PE_Export, ord: u32) -> UniquePtr; + fn entry_at_rva(self: &PE_Export, rva: u32) -> UniquePtr; + fn remove_entry_at(self: Pin<&mut PE_Export>, rva: u32) -> bool; + + type PE_Export_it_entries; + + fn next(self: Pin<&mut PE_Export_it_entries>) -> UniquePtr; + fn size(self: &PE_Export_it_entries) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/export_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/export_entry.rs new file mode 100644 index 0000000..9fd92ab --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/export_entry.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ExportEntry.hpp"); + + type PE_ExportEntry; + + #[Self = "PE_ExportEntry"] + fn create() -> UniquePtr; + #[Self = "PE_ExportEntry"] + fn create_with_name(name: &CxxString, addr: u32) -> UniquePtr; + fn ordinal(self: &PE_ExportEntry) -> u16; + fn address(self: &PE_ExportEntry) -> u32; + fn is_extern(self: &PE_ExportEntry) -> bool; + fn is_forwarded(self: &PE_ExportEntry) -> bool; + fn function_rva(self: &PE_ExportEntry) -> u32; + fn fwd_library(self: &PE_ExportEntry) -> UniquePtr; + fn fwd_function(self: &PE_ExportEntry) -> UniquePtr; + fn set_address(self: Pin<&mut PE_ExportEntry>, addr: u32); + fn demangled_name(self: &PE_ExportEntry) -> UniquePtr; + fn set_ordinal(self: Pin<&mut PE_ExportEntry>, ordinal: u16); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/factory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/factory.rs new file mode 100644 index 0000000..7ed08b3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/factory.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Factory.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type PE_Binary = crate::pe::binary::ffi::PE_Binary; + type PE_Section = crate::pe::section::ffi::PE_Section; + + type PE_Factory; + + #[Self = "PE_Factory"] + fn create(pe_type: u32) -> UniquePtr; + fn set_arch(self: Pin<&mut PE_Factory>, arch: u32); + fn set_entrypoint(self: Pin<&mut PE_Factory>, ep: u64); + fn add_section(self: Pin<&mut PE_Factory>, section: &PE_Section); + fn get(self: Pin<&mut PE_Factory>) -> UniquePtr; + fn is_32bit(self: &PE_Factory) -> bool; + fn is_64bit(self: &PE_Factory) -> bool; + fn section_align(self: &PE_Factory) -> u32; + fn file_align(self: &PE_Factory) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/header.rs new file mode 100644 index 0000000..9cb7e1d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/header.rs @@ -0,0 +1,28 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Header.hpp"); + + type PE_Header; + + fn signature(self: &PE_Header) -> UniquePtr>; + fn machine(self: &PE_Header) -> u32; + fn numberof_sections(self: &PE_Header) -> u16; + fn time_date_stamp(self: &PE_Header) -> u32; + fn pointerto_symbol_table(self: &PE_Header) -> u32; + fn numberof_symbols(self: &PE_Header) -> u32; + fn sizeof_optional_header(self: &PE_Header) -> u16; + fn characteristics(self: &PE_Header) -> u32; + fn add_characteristic(self: Pin<&mut PE_Header>, value: u32); + fn remove_characteristic(self: Pin<&mut PE_Header>, value: u32); + fn set_machine(self: Pin<&mut PE_Header>, value: u32); + fn set_numberof_sections(self: Pin<&mut PE_Header>, value: u16); + fn set_time_date_stamp(self: Pin<&mut PE_Header>, value: u32); + fn set_pointerto_symbol_table(self: Pin<&mut PE_Header>, value: u32); + fn set_numberof_symbols(self: Pin<&mut PE_Header>, value: u32); + fn set_sizeof_optional_header(self: Pin<&mut PE_Header>, value: u16); + fn set_characteristics(self: Pin<&mut PE_Header>, value: u32); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/import.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/import.rs new file mode 100644 index 0000000..e651c45 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/import.rs @@ -0,0 +1,37 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Import.hpp"); + + type PE_DataDirectory = crate::pe::data_directories::ffi::PE_DataDirectory; + type PE_ImportEntry = crate::pe::import_entry::ffi::PE_ImportEntry; + + type PE_Import; + + fn forwarder_chain(self: &PE_Import) -> u32; + fn timedatestamp(self: &PE_Import) -> u32; + fn import_address_table_rva(self: &PE_Import) -> u32; + fn import_lookup_table_rva(self: &PE_Import) -> u32; + fn name(self: &PE_Import) -> UniquePtr; + fn name_rva(self: &PE_Import) -> u32; + fn directory(self: &PE_Import) -> UniquePtr; + fn iat_directory(self: &PE_Import) -> UniquePtr; + fn entries(self: &PE_Import) -> UniquePtr; + fn entry_by_name(self: &PE_Import, name: &CxxString) -> UniquePtr; + fn remove_entry_by_name(self: Pin<&mut PE_Import>, name: &CxxString) -> bool; + fn add_entry_by_name( + self: Pin<&mut PE_Import>, + name: &CxxString, + ) -> UniquePtr; + fn set_name(self: Pin<&mut PE_Import>, name: &CxxString); + fn remove_entry_by_ordinal(self: Pin<&mut PE_Import>, ord: u32) -> bool; + + type PE_Import_it_entries; + + fn next(self: Pin<&mut PE_Import_it_entries>) -> UniquePtr; + fn size(self: &PE_Import_it_entries) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/import_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/import_entry.rs new file mode 100644 index 0000000..94b35cb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/import_entry.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ImportEntry.hpp"); + + type PE_ImportEntry; + + fn is_ordinal(self: &PE_ImportEntry) -> bool; + fn ordinal(self: &PE_ImportEntry) -> u16; + fn hint_name_rva(self: &PE_ImportEntry) -> u64; + fn hint(self: &PE_ImportEntry) -> u16; + fn iat_value(self: &PE_ImportEntry) -> u64; + fn ilt_value(self: &PE_ImportEntry) -> u64; + fn data(self: &PE_ImportEntry) -> u64; + fn iat_address(self: &PE_ImportEntry) -> u64; + fn demangled_name(self: &PE_ImportEntry) -> UniquePtr; + fn set_iat_value(self: Pin<&mut PE_ImportEntry>, value: u64); + fn set_ilt_value(self: Pin<&mut PE_ImportEntry>, value: u64); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration.rs new file mode 100644 index 0000000..4a7e4ce --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration.rs @@ -0,0 +1,5 @@ +pub mod chpe_metadata; +pub mod dynamic_relocation; +pub mod enclave_configuration; +pub mod load_configuration; +pub mod volatile_metadata; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/chpe_metadata.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/chpe_metadata.rs new file mode 100644 index 0000000..f3585f7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/chpe_metadata.rs @@ -0,0 +1,113 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp"); + + type PE_CHPEMetadata; + + fn version(self: &PE_CHPEMetadata) -> u32; + fn to_string(self: &PE_CHPEMetadata) -> UniquePtr; + + type PE_CHPEMetadataARM64; + + #[Self = "PE_CHPEMetadataARM64"] + fn classof(meta: &PE_CHPEMetadata) -> bool; + fn code_map(self: &PE_CHPEMetadataARM64) -> u32; + fn code_map_count(self: &PE_CHPEMetadataARM64) -> u32; + fn code_ranges_to_entrypoints(self: &PE_CHPEMetadataARM64) -> u32; + fn redirection_metadata(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_call_no_redirect(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_ret(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_call(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_icall(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_icall_cfg(self: &PE_CHPEMetadataARM64) -> u32; + fn alternate_entry_point(self: &PE_CHPEMetadataARM64) -> u32; + fn auxiliary_iat(self: &PE_CHPEMetadataARM64) -> u32; + fn code_ranges_to_entry_points_count(self: &PE_CHPEMetadataARM64) -> u32; + fn redirection_metadata_count(self: &PE_CHPEMetadataARM64) -> u32; + fn get_x64_information_function_pointer(self: &PE_CHPEMetadataARM64) -> u32; + fn set_x64_information_function_pointer(self: &PE_CHPEMetadataARM64) -> u32; + fn extra_rfe_table(self: &PE_CHPEMetadataARM64) -> u32; + fn extra_rfe_table_size(self: &PE_CHPEMetadataARM64) -> u32; + fn os_arm64x_dispatch_fptr(self: &PE_CHPEMetadataARM64) -> u32; + fn auxiliary_iat_copy(self: &PE_CHPEMetadataARM64) -> u32; + fn auxiliary_delay_import(self: &PE_CHPEMetadataARM64) -> u32; + fn auxiliary_delay_import_copy(self: &PE_CHPEMetadataARM64) -> u32; + fn bitfield_info(self: &PE_CHPEMetadataARM64) -> u32; + fn code_ranges( + self: &PE_CHPEMetadataARM64, + ) -> UniquePtr; + fn redirections( + self: &PE_CHPEMetadataARM64, + ) -> UniquePtr; + fn code_range_entry_point( + self: &PE_CHPEMetadataARM64, + ) -> UniquePtr; + + type PE_CHPEMetadataARM64_code_range_entry_point_t; + + fn start_rva(self: &PE_CHPEMetadataARM64_code_range_entry_point_t) -> u32; + fn entrypoint(self: &PE_CHPEMetadataARM64_code_range_entry_point_t) -> u32; + fn end_rva(self: &PE_CHPEMetadataARM64_code_range_entry_point_t) -> u32; + + type PE_CHPEMetadataARM64_it_const_code_range_entry_point; + + fn next( + self: Pin<&mut PE_CHPEMetadataARM64_it_const_code_range_entry_point>, + ) -> UniquePtr; + fn size(self: &PE_CHPEMetadataARM64_it_const_code_range_entry_point) -> u64; + + type PE_CHPEMetadataARM64_it_const_range_entries; + + fn next( + self: Pin<&mut PE_CHPEMetadataARM64_it_const_range_entries>, + ) -> UniquePtr; + fn size(self: &PE_CHPEMetadataARM64_it_const_range_entries) -> u64; + + type PE_CHPEMetadataARM64_it_const_redirection_entries; + + fn next( + self: Pin<&mut PE_CHPEMetadataARM64_it_const_redirection_entries>, + ) -> UniquePtr; + fn size(self: &PE_CHPEMetadataARM64_it_const_redirection_entries) -> u64; + + type PE_CHPEMetadataARM64_redirection_entry_t; + + fn src(self: &PE_CHPEMetadataARM64_redirection_entry_t) -> u32; + fn dst(self: &PE_CHPEMetadataARM64_redirection_entry_t) -> u32; + + type PE_CHPEMetadataARM64_range_entry_t; + + fn length(self: &PE_CHPEMetadataARM64_range_entry_t) -> u32; + fn start(self: &PE_CHPEMetadataARM64_range_entry_t) -> u32; + fn get_type(self: &PE_CHPEMetadataARM64_range_entry_t) -> u32; + fn end(self: &PE_CHPEMetadataARM64_range_entry_t) -> u32; + fn start_offset(self: &PE_CHPEMetadataARM64_range_entry_t) -> u32; + + type PE_CHPEMetadataX86; + + #[Self = "PE_CHPEMetadataX86"] + fn classof(meta: &PE_CHPEMetadata) -> bool; + fn chpe_code_address_range_offset(self: &PE_CHPEMetadataX86) -> u32; + fn chpe_code_address_range_count(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_exception_handler_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_call_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_indirect_call_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_indirect_call_cfg_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_ret_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_ret_leaf_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn wowa64_dispatch_jump_function_pointer(self: &PE_CHPEMetadataX86) -> u32; + fn compiler_iat_pointer(self: &PE_CHPEMetadataX86, is_set: Pin<&mut u32>) -> u32; + fn wowa64_rdtsc_function_pointer(self: &PE_CHPEMetadataX86, is_set: Pin<&mut u32>) -> u32; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation.rs new file mode 100644 index 0000000..f85c67e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation.rs @@ -0,0 +1,2 @@ +pub mod dynamic_fixup; +pub mod dynamic_relocation; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_fixup.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_fixup.rs new file mode 100644 index 0000000..464bc2d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_fixup.rs @@ -0,0 +1,195 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Relocation = crate::pe::relocation::ffi::PE_Relocation; + + type PE_DynamicFixup; + + fn to_string(self: &PE_DynamicFixup) -> UniquePtr; + + type PE_DynamicFixupARM64Kernel; + + #[Self = "PE_DynamicFixupARM64Kernel"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn relocations( + self: &PE_DynamicFixupARM64Kernel, + ) -> UniquePtr; + + type PE_DynamicFixupARM64Kernel_entry; + + fn to_string(self: &PE_DynamicFixupARM64Kernel_entry) -> UniquePtr; + fn rva(self: &PE_DynamicFixupARM64Kernel_entry) -> u32; + fn indirect_call(self: &PE_DynamicFixupARM64Kernel_entry) -> bool; + fn register_index(self: &PE_DynamicFixupARM64Kernel_entry) -> u8; + fn import_type(self: &PE_DynamicFixupARM64Kernel_entry) -> u8; + fn iat_index(self: &PE_DynamicFixupARM64Kernel_entry) -> u16; + + type PE_DynamicFixupARM64Kernel_it_relocations; + + fn next( + self: Pin<&mut PE_DynamicFixupARM64Kernel_it_relocations>, + ) -> UniquePtr; + fn size(self: &PE_DynamicFixupARM64Kernel_it_relocations) -> u64; + + type PE_DynamicFixupARM64X; + + #[Self = "PE_DynamicFixupARM64X"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn relocations( + self: &PE_DynamicFixupARM64X, + ) -> UniquePtr; + + type PE_DynamicFixupARM64X_entry; + + fn get_bytes(self: &PE_DynamicFixupARM64X_entry) -> Span; + fn rva(self: &PE_DynamicFixupARM64X_entry) -> u32; + fn value(self: &PE_DynamicFixupARM64X_entry) -> i64; + fn size(self: &PE_DynamicFixupARM64X_entry) -> u32; + fn get_type(self: &PE_DynamicFixupARM64X_entry) -> u32; + fn to_string(self: &PE_DynamicFixupARM64X_entry) -> UniquePtr; + + type PE_DynamicFixupARM64X_it_relocations; + + fn next( + self: Pin<&mut PE_DynamicFixupARM64X_it_relocations>, + ) -> UniquePtr; + fn size(self: &PE_DynamicFixupARM64X_it_relocations) -> u64; + + type PE_DynamicFixupControlTransfer; + + #[Self = "PE_DynamicFixupControlTransfer"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn relocations( + self: &PE_DynamicFixupControlTransfer, + ) -> UniquePtr; + + type PE_DynamicFixupControlTransfer_entry; + + fn rva(self: &PE_DynamicFixupControlTransfer_entry) -> u32; + fn is_call(self: &PE_DynamicFixupControlTransfer_entry) -> bool; + fn iat_index(self: &PE_DynamicFixupControlTransfer_entry) -> u16; + fn to_string(self: &PE_DynamicFixupControlTransfer_entry) -> UniquePtr; + + type PE_DynamicFixupControlTransfer_it_relocations; + + fn next( + self: Pin<&mut PE_DynamicFixupControlTransfer_it_relocations>, + ) -> UniquePtr; + fn size(self: &PE_DynamicFixupControlTransfer_it_relocations) -> u64; + + type PE_DynamicFixupGeneric; + + #[Self = "PE_DynamicFixupGeneric"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn relocations( + self: &PE_DynamicFixupGeneric, + ) -> UniquePtr; + + type PE_DynamicFixupGeneric_it_relocations; + + fn next(self: Pin<&mut PE_DynamicFixupGeneric_it_relocations>) -> UniquePtr; + fn size(self: &PE_DynamicFixupGeneric_it_relocations) -> u64; + + type PE_DynamicFixupUnknown; + + #[Self = "PE_DynamicFixupUnknown"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn payload(self: &PE_DynamicFixupUnknown) -> Span; + type PE_FunctionOverride; + + #[Self = "PE_FunctionOverride"] + fn classof(meta: &PE_DynamicFixup) -> bool; + fn func_overriding_info( + self: &PE_FunctionOverride, + ) -> UniquePtr; + fn bdd_info(self: &PE_FunctionOverride) -> UniquePtr; + fn bdd_info_at( + self: &PE_FunctionOverride, + offset: u32, + ) -> UniquePtr; + fn bdd_info_for( + self: &PE_FunctionOverride, + info: &PE_FunctionOverrideInfo, + ) -> UniquePtr; + + type PE_FunctionOverrideInfo; + + fn original_rva(self: &PE_FunctionOverrideInfo) -> u32; + fn bdd_offset(self: &PE_FunctionOverrideInfo) -> u32; + fn rva_size(self: &PE_FunctionOverrideInfo) -> u32; + fn base_reloc_size(self: &PE_FunctionOverrideInfo) -> u32; + fn functions_rva(self: &PE_FunctionOverrideInfo) -> UniquePtr>; + fn relocations( + self: &PE_FunctionOverrideInfo, + ) -> UniquePtr; + fn to_string(self: &PE_FunctionOverrideInfo) -> UniquePtr; + + type PE_FunctionOverrideInfo_it_relocations; + + fn next(self: Pin<&mut PE_FunctionOverrideInfo_it_relocations>) + -> UniquePtr; + fn size(self: &PE_FunctionOverrideInfo_it_relocations) -> u64; + + type PE_FunctionOverride_image_bdd_dynamic_relocation_t; + + fn value(self: &PE_FunctionOverride_image_bdd_dynamic_relocation_t) -> u32; + fn left(self: &PE_FunctionOverride_image_bdd_dynamic_relocation_t) -> u16; + fn right(self: &PE_FunctionOverride_image_bdd_dynamic_relocation_t) -> u16; + + type PE_FunctionOverride_image_bdd_info_t; + + fn payload(self: &PE_FunctionOverride_image_bdd_info_t) -> Span; + fn version(self: &PE_FunctionOverride_image_bdd_info_t) -> u32; + fn original_size(self: &PE_FunctionOverride_image_bdd_info_t) -> u32; + fn original_offset(self: &PE_FunctionOverride_image_bdd_info_t) -> u32; + fn relocations( + self: &PE_FunctionOverride_image_bdd_info_t, + ) -> UniquePtr; + + type PE_FunctionOverride_image_bdd_info_t_it_relocations; + + fn next( + self: Pin<&mut PE_FunctionOverride_image_bdd_info_t_it_relocations>, + ) -> UniquePtr; + fn size(self: &PE_FunctionOverride_image_bdd_info_t_it_relocations) -> u64; + + type PE_FunctionOverride_it_bdd_info; + + fn next( + self: Pin<&mut PE_FunctionOverride_it_bdd_info>, + ) -> UniquePtr; + fn size(self: &PE_FunctionOverride_it_bdd_info) -> u64; + + type PE_FunctionOverride_it_func_overriding_info; + + fn next( + self: Pin<&mut PE_FunctionOverride_it_func_overriding_info>, + ) -> UniquePtr; + fn size(self: &PE_FunctionOverride_it_func_overriding_info) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_relocation.rs new file mode 100644 index 0000000..4e7d168 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/dynamic_relocation/dynamic_relocation.rs @@ -0,0 +1,30 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp"); + + type PE_DynamicFixup = + crate::pe::load_configuration::dynamic_relocation::dynamic_fixup::ffi::PE_DynamicFixup; + + type PE_DynamicRelocation; + + fn version(self: &PE_DynamicRelocation) -> u32; + fn symbol(self: &PE_DynamicRelocation) -> u64; + fn fixups(self: &PE_DynamicRelocation) -> UniquePtr; + fn to_string(self: &PE_DynamicRelocation) -> UniquePtr; + + type PE_DynamicRelocationV1; + + #[Self = "PE_DynamicRelocationV1"] + fn classof(entry: &PE_DynamicRelocation) -> bool; + + type PE_DynamicRelocationV2; + + #[Self = "PE_DynamicRelocationV2"] + fn classof(entry: &PE_DynamicRelocation) -> bool; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/enclave_configuration.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/enclave_configuration.rs new file mode 100644 index 0000000..7a91346 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/enclave_configuration.rs @@ -0,0 +1,48 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_EnclaveConfiguration; + + fn family_id(self: &PE_EnclaveConfiguration) -> Span; + fn image_id(self: &PE_EnclaveConfiguration) -> Span; + fn size(self: &PE_EnclaveConfiguration) -> u32; + fn min_required_config_size(self: &PE_EnclaveConfiguration) -> u32; + fn policy_flags(self: &PE_EnclaveConfiguration) -> u32; + fn is_debuggable(self: &PE_EnclaveConfiguration) -> bool; + fn import_list_rva(self: &PE_EnclaveConfiguration) -> u32; + fn import_entry_size(self: &PE_EnclaveConfiguration) -> u32; + fn nb_imports(self: &PE_EnclaveConfiguration) -> u32; + fn imports(self: &PE_EnclaveConfiguration) + -> UniquePtr; + fn image_version(self: &PE_EnclaveConfiguration) -> u32; + fn security_version(self: &PE_EnclaveConfiguration) -> u32; + fn enclave_size(self: &PE_EnclaveConfiguration) -> u64; + fn nb_threads(self: &PE_EnclaveConfiguration) -> u32; + fn enclave_flags(self: &PE_EnclaveConfiguration) -> u32; + fn to_string(self: &PE_EnclaveConfiguration) -> UniquePtr; + + type PE_EnclaveConfiguration_it_imports; + + fn next(self: Pin<&mut PE_EnclaveConfiguration_it_imports>) -> UniquePtr; + fn size(self: &PE_EnclaveConfiguration_it_imports) -> u64; + + type PE_EnclaveImport; + + fn id(self: &PE_EnclaveImport) -> Span; + fn family_id(self: &PE_EnclaveImport) -> Span; + fn image_id(self: &PE_EnclaveImport) -> Span; + fn get_type(self: &PE_EnclaveImport) -> u32; + fn min_security_version(self: &PE_EnclaveImport) -> u32; + fn import_name_rva(self: &PE_EnclaveImport) -> u32; + fn import_name(self: &PE_EnclaveImport) -> UniquePtr; + fn reserved(self: &PE_EnclaveImport) -> u32; + fn to_string(self: &PE_EnclaveImport) -> UniquePtr; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/load_configuration.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/load_configuration.rs new file mode 100644 index 0000000..5a9b1df --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/load_configuration.rs @@ -0,0 +1,246 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp"); + + type PE_CHPEMetadata = crate::pe::load_configuration::chpe_metadata::ffi::PE_CHPEMetadata; + type PE_CodeIntegrity = crate::pe::code_integrity::ffi::PE_CodeIntegrity; + type PE_DynamicRelocation = crate::pe::load_configuration::dynamic_relocation::dynamic_relocation::ffi::PE_DynamicRelocation; + type PE_EnclaveConfiguration = + crate::pe::load_configuration::enclave_configuration::ffi::PE_EnclaveConfiguration; + type PE_VolatileMetadata = + crate::pe::load_configuration::volatile_metadata::ffi::PE_VolatileMetadata; + + type PE_LoadConfiguration; + + fn characteristics(self: &PE_LoadConfiguration) -> u32; + fn size(self: &PE_LoadConfiguration) -> u32; + fn timedatestamp(self: &PE_LoadConfiguration) -> u32; + fn major_version(self: &PE_LoadConfiguration) -> u16; + fn minor_version(self: &PE_LoadConfiguration) -> u16; + fn global_flags_clear(self: &PE_LoadConfiguration) -> u32; + fn global_flags_set(self: &PE_LoadConfiguration) -> u32; + fn critical_section_default_timeout(self: &PE_LoadConfiguration) -> u32; + fn decommit_free_block_threshold(self: &PE_LoadConfiguration) -> u64; + fn decommit_total_free_threshold(self: &PE_LoadConfiguration) -> u64; + fn lock_prefix_table(self: &PE_LoadConfiguration) -> u64; + fn maximum_allocation_size(self: &PE_LoadConfiguration) -> u64; + fn virtual_memory_threshold(self: &PE_LoadConfiguration) -> u64; + fn process_affinity_mask(self: &PE_LoadConfiguration) -> u64; + fn process_heap_flags(self: &PE_LoadConfiguration) -> u32; + fn csd_version(self: &PE_LoadConfiguration) -> u16; + fn reserved1(self: &PE_LoadConfiguration) -> u16; + fn dependent_load_flags(self: &PE_LoadConfiguration) -> u16; + fn editlist(self: &PE_LoadConfiguration) -> u64; + fn security_cookie(self: &PE_LoadConfiguration) -> u64; + fn se_handler_table(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn se_handler_count(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn seh_functions(self: &PE_LoadConfiguration) -> UniquePtr>; + fn guard_cf_check_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_cf_dispatch_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_cf_function_table(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_cf_function_count(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_cf_functions( + self: &PE_LoadConfiguration, + ) -> UniquePtr; + fn code_integrity(self: &PE_LoadConfiguration) -> UniquePtr; + fn guard_address_taken_iat_entry_table( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_address_taken_iat_entry_count( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_address_taken_iat_entries( + self: &PE_LoadConfiguration, + ) -> UniquePtr; + fn guard_long_jump_target_table(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_long_jump_target_count(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_long_jump_targets( + self: &PE_LoadConfiguration, + ) -> UniquePtr; + fn dynamic_value_reloc_table(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn hybrid_metadata_pointer(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn chpe_metadata_pointer(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn chpe_metadata(self: &PE_LoadConfiguration) -> UniquePtr; + fn guard_rf_failure_routine(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_rf_failure_routine_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn dynamic_relocations( + self: &PE_LoadConfiguration, + ) -> UniquePtr; + fn guard_rf_verify_stackpointer_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn enclave_configuration_ptr(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn enclave_config(self: &PE_LoadConfiguration) -> UniquePtr; + fn volatile_metadata_pointer(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn volatile_metadata(self: &PE_LoadConfiguration) -> UniquePtr; + fn guard_eh_continuation_table(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_eh_continuation_count(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_eh_continuation_functions( + self: &PE_LoadConfiguration, + ) -> UniquePtr; + fn guard_xfg_check_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_xfg_dispatch_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_xfg_table_dispatch_function_pointer( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn cast_guard_os_determined_failure_mode( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u64; + fn guard_memcpy_function_pointer(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) + -> u64; + fn uma_function_pointers(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u64; + fn guard_flags(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u32; + fn dynamic_value_reloctable_offset( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u32; + fn dynamic_value_reloctable_section( + self: &PE_LoadConfiguration, + is_set: Pin<&mut u32>, + ) -> u16; + fn reserved2(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u16; + fn hotpatch_table_offset(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u32; + fn reserved3(self: &PE_LoadConfiguration, is_set: Pin<&mut u32>) -> u32; + fn set_characteristics(self: Pin<&mut PE_LoadConfiguration>, characteristics: u32); + fn set_size(self: Pin<&mut PE_LoadConfiguration>, value: u32); + fn set_major_version(self: Pin<&mut PE_LoadConfiguration>, major_version: u16); + fn set_minor_version(self: Pin<&mut PE_LoadConfiguration>, minor_version: u16); + fn set_timedatestamp(self: Pin<&mut PE_LoadConfiguration>, timedatestamp: u32); + fn set_global_flags_clear(self: Pin<&mut PE_LoadConfiguration>, global_flags_clear: u32); + fn set_global_flags_set(self: Pin<&mut PE_LoadConfiguration>, global_flags_set: u32); + fn set_critical_section_default_timeout(self: Pin<&mut PE_LoadConfiguration>, val: u32); + fn set_decommit_free_block_threshold(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_decommit_total_free_threshold(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_lock_prefix_table(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_maximum_allocation_size(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_virtual_memory_threshold(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_process_affinity_mask(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_process_heap_flags(self: Pin<&mut PE_LoadConfiguration>, val: u32); + fn set_csd_version(self: Pin<&mut PE_LoadConfiguration>, val: u16); + fn set_reserved1(self: Pin<&mut PE_LoadConfiguration>, val: u16); + fn set_dependent_load_flags(self: Pin<&mut PE_LoadConfiguration>, val: u16); + fn set_editlist(self: Pin<&mut PE_LoadConfiguration>, val: u32); + fn set_security_cookie(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_se_handler_table(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_se_handler_count(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_guard_cf_check_function_pointer(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_guard_cf_dispatch_function_pointer(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_guard_cf_function_table(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_guard_cf_function_count(self: Pin<&mut PE_LoadConfiguration>, val: u64); + fn set_guard_flags(self: Pin<&mut PE_LoadConfiguration>, flags: u32); + fn set_guard_address_taken_iat_entry_table( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_guard_address_taken_iat_entry_count( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_guard_long_jump_target_table(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_long_jump_target_count(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_dynamic_value_reloc_table(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_hybrid_metadata_pointer(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_rf_failure_routine(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_rf_failure_routine_function_pointer( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_dynamic_value_reloctable_offset(self: Pin<&mut PE_LoadConfiguration>, value: u32); + fn set_dynamic_value_reloctable_section(self: Pin<&mut PE_LoadConfiguration>, value: u16); + fn set_reserved2(self: Pin<&mut PE_LoadConfiguration>, value: u16); + fn set_guard_rf_verify_stackpointer_function_pointer( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_hotpatch_table_offset(self: Pin<&mut PE_LoadConfiguration>, value: u32); + fn set_reserved3(self: Pin<&mut PE_LoadConfiguration>, value: u32); + fn set_enclave_configuration_ptr(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_volatile_metadata_pointer(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_eh_continuation_table(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_eh_continuation_count(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_xfg_check_function_pointer(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_guard_xfg_dispatch_function_pointer( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_guard_xfg_table_dispatch_function_pointer( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_cast_guard_os_determined_failure_mode( + self: Pin<&mut PE_LoadConfiguration>, + value: u64, + ); + fn set_guard_memcpy_function_pointer(self: Pin<&mut PE_LoadConfiguration>, value: u64); + fn set_uma_function_pointers(self: Pin<&mut PE_LoadConfiguration>, value: u64); + + type PE_LoadConfiguration_guard_function_t; + + fn rva(self: &PE_LoadConfiguration_guard_function_t) -> u32; + fn extra(self: &PE_LoadConfiguration_guard_function_t) -> u32; + + type PE_LoadConfiguration_it_dynamic_relocations; + + fn next( + self: Pin<&mut PE_LoadConfiguration_it_dynamic_relocations>, + ) -> UniquePtr; + fn size(self: &PE_LoadConfiguration_it_dynamic_relocations) -> u64; + + type PE_LoadConfiguration_it_guard_address_taken_iat_entries; + + fn next( + self: Pin<&mut PE_LoadConfiguration_it_guard_address_taken_iat_entries>, + ) -> UniquePtr; + fn size(self: &PE_LoadConfiguration_it_guard_address_taken_iat_entries) -> u64; + + type PE_LoadConfiguration_it_guard_cf_functions; + + fn next( + self: Pin<&mut PE_LoadConfiguration_it_guard_cf_functions>, + ) -> UniquePtr; + fn size(self: &PE_LoadConfiguration_it_guard_cf_functions) -> u64; + + type PE_LoadConfiguration_it_guard_eh_continuation; + + fn next( + self: Pin<&mut PE_LoadConfiguration_it_guard_eh_continuation>, + ) -> UniquePtr; + fn size(self: &PE_LoadConfiguration_it_guard_eh_continuation) -> u64; + + type PE_LoadConfiguration_it_guard_long_jump_targets; + + fn next( + self: Pin<&mut PE_LoadConfiguration_it_guard_long_jump_targets>, + ) -> UniquePtr; + fn size(self: &PE_LoadConfiguration_it_guard_long_jump_targets) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/volatile_metadata.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/volatile_metadata.rs new file mode 100644 index 0000000..14446eb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/load_configuration/volatile_metadata.rs @@ -0,0 +1,36 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp"); + + type PE_VolatileMetadata; + + fn size(self: &PE_VolatileMetadata) -> u32; + fn min_version(self: &PE_VolatileMetadata) -> u16; + fn max_version(self: &PE_VolatileMetadata) -> u16; + fn access_table_rva(self: &PE_VolatileMetadata) -> u32; + fn access_table_size(self: &PE_VolatileMetadata) -> u32; + fn info_range_rva(self: &PE_VolatileMetadata) -> u32; + fn info_ranges_size(self: &PE_VolatileMetadata) -> u32; + fn access_table(self: &PE_VolatileMetadata) -> &CxxVector; + fn info_ranges(self: &PE_VolatileMetadata) -> UniquePtr; + fn to_string(self: &PE_VolatileMetadata) -> UniquePtr; + + type PE_VolatileMetadata_it_ranges; + + fn next( + self: Pin<&mut PE_VolatileMetadata_it_ranges>, + ) -> UniquePtr; + fn size(self: &PE_VolatileMetadata_it_ranges) -> u64; + + type PE_VolatileMetadata_range_t; + + fn start(self: &PE_VolatileMetadata_range_t) -> u32; + fn size(self: &PE_VolatileMetadata_range_t) -> u32; + fn end(self: &PE_VolatileMetadata_range_t) -> u32; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/optional_header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/optional_header.rs new file mode 100644 index 0000000..60c89dd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/optional_header.rs @@ -0,0 +1,45 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/OptionalHeader.hpp"); + + type PE_OptionalHeader; + + fn magic(self: &PE_OptionalHeader) -> u16; + fn major_linker_version(self: &PE_OptionalHeader) -> u8; + fn minor_linker_version(self: &PE_OptionalHeader) -> u8; + fn sizeof_code(self: &PE_OptionalHeader) -> u32; + fn sizeof_initialized_data(self: &PE_OptionalHeader) -> u32; + fn sizeof_uninitialized_data(self: &PE_OptionalHeader) -> u32; + fn addressof_entrypoint(self: &PE_OptionalHeader) -> u32; + fn baseof_code(self: &PE_OptionalHeader) -> u32; + fn baseof_data(self: &PE_OptionalHeader) -> u32; + fn imagebase(self: &PE_OptionalHeader) -> u64; + fn section_alignment(self: &PE_OptionalHeader) -> u32; + fn file_alignment(self: &PE_OptionalHeader) -> u32; + fn major_operating_system_version(self: &PE_OptionalHeader) -> u16; + fn minor_operating_system_version(self: &PE_OptionalHeader) -> u16; + fn major_image_version(self: &PE_OptionalHeader) -> u16; + fn minor_image_version(self: &PE_OptionalHeader) -> u16; + fn major_subsystem_version(self: &PE_OptionalHeader) -> u16; + fn minor_subsystem_version(self: &PE_OptionalHeader) -> u16; + fn win32_version_value(self: &PE_OptionalHeader) -> u32; + fn sizeof_image(self: &PE_OptionalHeader) -> u32; + fn sizeof_headers(self: &PE_OptionalHeader) -> u32; + fn checksum(self: &PE_OptionalHeader) -> u32; + fn subsystem(self: &PE_OptionalHeader) -> u64; + fn dll_characteristics(self: &PE_OptionalHeader) -> u32; + fn sizeof_stack_reserve(self: &PE_OptionalHeader) -> u64; + fn sizeof_stack_commit(self: &PE_OptionalHeader) -> u64; + fn sizeof_heap_reserve(self: &PE_OptionalHeader) -> u64; + fn sizeof_heap_commit(self: &PE_OptionalHeader) -> u64; + fn loader_flags(self: &PE_OptionalHeader) -> u32; + fn numberof_rva_and_size(self: &PE_OptionalHeader) -> u32; + fn set_addressof_entrypoint(self: Pin<&mut PE_OptionalHeader>, value: u32); + fn set_imagebase(self: Pin<&mut PE_OptionalHeader>, value: u64); + fn add_dll_characteristic(self: Pin<&mut PE_OptionalHeader>, value: u32); + fn remove_dll_characteristic(self: Pin<&mut PE_OptionalHeader>, value: u32); + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation.rs new file mode 100644 index 0000000..6912644 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation.rs @@ -0,0 +1,22 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Relocation.hpp"); + + type PE_RelocationEntry = crate::pe::relocation_entry::ffi::PE_RelocationEntry; + + type PE_Relocation; + + fn virtual_address(self: &PE_Relocation) -> u32; + fn block_size(self: &PE_Relocation) -> u32; + fn entries(self: &PE_Relocation) -> UniquePtr; + + type PE_Relocation_it_entries; + + fn next(self: Pin<&mut PE_Relocation_it_entries>) -> UniquePtr; + fn size(self: &PE_Relocation_it_entries) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation_entry.rs new file mode 100644 index 0000000..7b5b85c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/relocation_entry.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/RelocationEntry.hpp"); + + type PE_RelocationEntry; + + fn position(self: &PE_RelocationEntry) -> u64; + fn get_type(self: &PE_RelocationEntry) -> u32; + fn data(self: &PE_RelocationEntry) -> u16; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_accelerator.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_accelerator.rs new file mode 100644 index 0000000..5182fe3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_accelerator.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceAccelerator.hpp"); + + type PE_ResourceAccelerator; + + fn flags(self: &PE_ResourceAccelerator) -> i16; + fn ansi(self: &PE_ResourceAccelerator) -> i16; + fn id(self: &PE_ResourceAccelerator) -> u16; + fn padding(self: &PE_ResourceAccelerator) -> i16; + fn ansi_str(self: &PE_ResourceAccelerator) -> UniquePtr; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_data.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_data.rs new file mode 100644 index 0000000..3d9e708 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_data.rs @@ -0,0 +1,26 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceData.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ResourceNode = crate::pe::resource_node::ffi::PE_ResourceNode; + + type PE_ResourceData; + + fn content(self: &PE_ResourceData) -> Span; + #[Self = "PE_ResourceData"] + fn create() -> UniquePtr; + #[Self = "PE_ResourceData"] + unsafe fn create_from_data(buffer: *const u8, size: usize) -> UniquePtr; + #[Self = "PE_ResourceData"] + fn classof(node: &PE_ResourceNode) -> bool; + fn code_page(self: &PE_ResourceData) -> u32; + fn reserved(self: &PE_ResourceData) -> u32; + fn offset(self: &PE_ResourceData) -> u32; + fn set_code_page(self: Pin<&mut PE_ResourceData>, value: u32); + fn set_reserved(self: Pin<&mut PE_ResourceData>, value: u32); + unsafe fn set_content(self: Pin<&mut PE_ResourceData>, ptr: *const u8, size: usize); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_directory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_directory.rs new file mode 100644 index 0000000..135600f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_directory.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceDirectory.hpp"); + + type PE_ResourceNode = crate::pe::resource_node::ffi::PE_ResourceNode; + + type PE_ResourceDirectory; + + #[Self = "PE_ResourceDirectory"] + fn create_from_id(id: u32) -> UniquePtr; + #[Self = "PE_ResourceDirectory"] + fn create() -> UniquePtr; + #[Self = "PE_ResourceDirectory"] + fn classof(node: &PE_ResourceNode) -> bool; + fn characteristics(self: &PE_ResourceDirectory) -> u32; + fn time_date_stamp(self: &PE_ResourceDirectory) -> u32; + fn major_version(self: &PE_ResourceDirectory) -> u32; + fn minor_version(self: &PE_ResourceDirectory) -> u32; + fn numberof_name_entries(self: &PE_ResourceDirectory) -> u32; + fn numberof_id_entries(self: &PE_ResourceDirectory) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_icon.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_icon.rs new file mode 100644 index 0000000..3dbc267 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_icon.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceIcon.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ResourceIcon; + + fn pixels(self: &PE_ResourceIcon) -> Span; + fn id(self: &PE_ResourceIcon) -> u32; + fn lang(self: &PE_ResourceIcon) -> u32; + fn sublang(self: &PE_ResourceIcon) -> u32; + fn width(self: &PE_ResourceIcon) -> u8; + fn height(self: &PE_ResourceIcon) -> u8; + fn color_count(self: &PE_ResourceIcon) -> u8; + fn reserved(self: &PE_ResourceIcon) -> u8; + fn planes(self: &PE_ResourceIcon) -> u16; + fn bit_count(self: &PE_ResourceIcon) -> u16; + fn size(self: &PE_ResourceIcon) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_node.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_node.rs new file mode 100644 index 0000000..699993b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_node.rs @@ -0,0 +1,35 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceNode.hpp"); + + type PE_ResourceNode; + + #[Self = "PE_ResourceNode"] + unsafe fn from_slice( + buffer: *const u8, + size: usize, + rva: u64, + ) -> UniquePtr; + fn has_name(self: &PE_ResourceNode) -> bool; + fn name(self: &PE_ResourceNode) -> UniquePtr; + fn id(self: &PE_ResourceNode) -> u32; + fn depth(self: &PE_ResourceNode) -> u32; + fn is_directory(self: &PE_ResourceNode) -> bool; + fn is_data(self: &PE_ResourceNode) -> bool; + fn childs(self: &PE_ResourceNode) -> UniquePtr; + fn add_child( + self: Pin<&mut PE_ResourceNode>, + node: &PE_ResourceNode, + ) -> UniquePtr; + fn delete_child(self: Pin<&mut PE_ResourceNode>, id: u32); + fn print(self: &PE_ResourceNode) -> UniquePtr; + + type PE_ResourceNode_it_childs; + + fn next(self: Pin<&mut PE_ResourceNode_it_childs>) -> UniquePtr; + fn size(self: &PE_ResourceNode_it_childs) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_version.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_version.rs new file mode 100644 index 0000000..9152a52 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resource_version.rs @@ -0,0 +1,86 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourceVersion.hpp"); + + type PE_ResourceStringFileInfo; + + fn get_type(self: &PE_ResourceStringFileInfo) -> u16; + fn key(self: &PE_ResourceStringFileInfo) -> UniquePtr; + fn children( + self: &PE_ResourceStringFileInfo, + ) -> UniquePtr; + + type PE_ResourceStringFileInfo_it_children; + + fn next( + self: Pin<&mut PE_ResourceStringFileInfo_it_children>, + ) -> UniquePtr; + fn size(self: &PE_ResourceStringFileInfo_it_children) -> u64; + + type PE_ResourceStringTable; + + fn get_type(self: &PE_ResourceStringTable) -> u16; + fn key(self: &PE_ResourceStringTable) -> UniquePtr; + fn entries(self: &PE_ResourceStringTable) -> UniquePtr; + + type PE_ResourceStringTable_entry_t; + + fn key(self: &PE_ResourceStringTable_entry_t) -> UniquePtr; + fn value(self: &PE_ResourceStringTable_entry_t) -> UniquePtr; + + type PE_ResourceStringTable_it_entries; + + fn next( + self: Pin<&mut PE_ResourceStringTable_it_entries>, + ) -> UniquePtr; + fn size(self: &PE_ResourceStringTable_it_entries) -> u64; + + type PE_ResourceVar; + + fn get_type(self: &PE_ResourceVar) -> u16; + fn key(self: &PE_ResourceVar) -> UniquePtr; + fn values(self: &PE_ResourceVar) -> UniquePtr>; + + type PE_ResourceVarFileInfo; + + fn get_type(self: &PE_ResourceVarFileInfo) -> u16; + fn key(self: &PE_ResourceVarFileInfo) -> UniquePtr; + fn vars(self: &PE_ResourceVarFileInfo) -> UniquePtr; + + type PE_ResourceVarFileInfo_it_vars; + + fn next(self: Pin<&mut PE_ResourceVarFileInfo_it_vars>) -> UniquePtr; + fn size(self: &PE_ResourceVarFileInfo_it_vars) -> u64; + + type PE_ResourceVersion; + + fn get_type(self: &PE_ResourceVersion) -> u16; + fn key(self: &PE_ResourceVersion) -> UniquePtr; + fn string_file_info(self: &PE_ResourceVersion) -> UniquePtr; + fn var_file_info(self: &PE_ResourceVersion) -> UniquePtr; + fn file_info_signature(self: &PE_ResourceVersion) -> u32; + fn file_info_struct_version(self: &PE_ResourceVersion) -> u32; + fn file_info_file_version_ms(self: &PE_ResourceVersion) -> u32; + fn file_info_file_version_ls(self: &PE_ResourceVersion) -> u32; + fn file_info_product_version_ms(self: &PE_ResourceVersion) -> u32; + fn file_info_product_version_ls(self: &PE_ResourceVersion) -> u32; + fn file_info_file_flags_mask(self: &PE_ResourceVersion) -> u32; + fn file_info_file_flags(self: &PE_ResourceVersion) -> u32; + fn file_info_file_os(self: &PE_ResourceVersion) -> u32; + fn file_info_file_type(self: &PE_ResourceVersion) -> u32; + fn file_info_file_subtype(self: &PE_ResourceVersion) -> u32; + fn file_info_file_date_ms(self: &PE_ResourceVersion) -> u32; + fn file_info_file_date_ls(self: &PE_ResourceVersion) -> u32; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/resources_manager.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resources_manager.rs new file mode 100644 index 0000000..65713ad --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/resources_manager.rs @@ -0,0 +1,65 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/ResourcesManager.hpp"); + + type PE_ResourceAccelerator = crate::pe::resource_accelerator::ffi::PE_ResourceAccelerator; + type PE_ResourceIcon = crate::pe::resource_icon::ffi::PE_ResourceIcon; + type PE_ResourceNode = crate::pe::resource_node::ffi::PE_ResourceNode; + type PE_ResourceVersion = crate::pe::resource_version::ffi::PE_ResourceVersion; + + type PE_ResourcesManager; + + fn get_types(self: &PE_ResourcesManager) -> UniquePtr>; + fn has_type(self: &PE_ResourcesManager, type_: u32) -> bool; + fn manifest(self: &PE_ResourcesManager) -> UniquePtr; + fn set_manifest(self: Pin<&mut PE_ResourcesManager>, str_: &CxxString); + fn print_tree(self: &PE_ResourcesManager) -> UniquePtr; + fn print_tree_with_depth(self: &PE_ResourcesManager, depth: u32) -> UniquePtr; + fn html(self: &PE_ResourcesManager) -> UniquePtr>; + fn icons(self: &PE_ResourcesManager) -> UniquePtr; + fn version(self: &PE_ResourcesManager) -> UniquePtr; + fn accelerator(self: &PE_ResourcesManager) + -> UniquePtr; + fn string_table( + self: &PE_ResourcesManager, + ) -> UniquePtr; + fn find_node_type(self: &PE_ResourcesManager, type_: u32) -> UniquePtr; + + type PE_ResourcesManager_it_accelerator; + + fn next( + self: Pin<&mut PE_ResourcesManager_it_accelerator>, + ) -> UniquePtr; + fn size(self: &PE_ResourcesManager_it_accelerator) -> u64; + + type PE_ResourcesManager_it_icons; + + fn next(self: Pin<&mut PE_ResourcesManager_it_icons>) -> UniquePtr; + fn size(self: &PE_ResourcesManager_it_icons) -> u64; + + type PE_ResourcesManager_it_string_table_entry; + + fn next( + self: Pin<&mut PE_ResourcesManager_it_string_table_entry>, + ) -> UniquePtr; + fn size(self: &PE_ResourcesManager_it_string_table_entry) -> u64; + + type PE_ResourcesManager_it_version; + + fn next(self: Pin<&mut PE_ResourcesManager_it_version>) -> UniquePtr; + fn size(self: &PE_ResourcesManager_it_version) -> u64; + + type PE_ResourcesManager_string_entry_t; + + fn string(self: &PE_ResourcesManager_string_entry_t) -> UniquePtr; + fn id(self: &PE_ResourcesManager_string_entry_t) -> u32; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_entry.rs new file mode 100644 index 0000000..fff1854 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_entry.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/RichEntry.hpp"); + + type PE_RichEntry; + + fn id(self: &PE_RichEntry) -> u16; + fn build_id(self: &PE_RichEntry) -> u16; + fn count(self: &PE_RichEntry) -> u32; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_header.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_header.rs new file mode 100644 index 0000000..80aa6ce --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/rich_header.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/RichHeader.hpp"); + + type PE_RichEntry = crate::pe::rich_entry::ffi::PE_RichEntry; + + type PE_RichHeader; + + fn key(self: &PE_RichHeader) -> u32; + fn raw(self: &PE_RichHeader) -> UniquePtr>; + fn raw_with_key(self: &PE_RichHeader, xor_key: u32) -> UniquePtr>; + fn entries(self: &PE_RichHeader) -> UniquePtr; + fn set_key(self: Pin<&mut PE_RichHeader>, key: u32); + + type PE_RichHeader_it_entries; + + fn next(self: Pin<&mut PE_RichHeader_it_entries>) -> UniquePtr; + fn size(self: &PE_RichHeader_it_entries) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_a_arch64.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_a_arch64.rs new file mode 100644 index 0000000..c291d02 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_a_arch64.rs @@ -0,0 +1,62 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/RuntimeFunctionAArch64.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ExceptionInfo = crate::pe::exception_info::ffi::PE_ExceptionInfo; + + type PE_RuntimeFunctionAArch64; + + #[Self = "PE_RuntimeFunctionAArch64"] + fn classof(entry: &PE_ExceptionInfo) -> bool; + fn length(self: &PE_RuntimeFunctionAArch64) -> u32; + fn flag(self: &PE_RuntimeFunctionAArch64) -> u32; + fn rva_end(self: &PE_RuntimeFunctionAArch64) -> u32; + + type PE_unwind_aarch64_PackedFunction; + + #[Self = "PE_unwind_aarch64_PackedFunction"] + fn classof(entry: &PE_RuntimeFunctionAArch64) -> bool; + fn frame_size(self: &PE_unwind_aarch64_PackedFunction) -> u8; + fn reg_I(self: &PE_unwind_aarch64_PackedFunction) -> u8; + fn reg_F(self: &PE_unwind_aarch64_PackedFunction) -> u8; + fn H(self: &PE_unwind_aarch64_PackedFunction) -> u8; + fn CR(self: &PE_unwind_aarch64_PackedFunction) -> u8; + + type PE_unwind_aarch64_UnpackedFunction; + + fn unwind_code(self: &PE_unwind_aarch64_UnpackedFunction) -> Span; + #[Self = "PE_unwind_aarch64_UnpackedFunction"] + fn classof(entry: &PE_RuntimeFunctionAArch64) -> bool; + fn xdata_rva(self: &PE_unwind_aarch64_UnpackedFunction) -> u32; + fn version(self: &PE_unwind_aarch64_UnpackedFunction) -> u32; + fn X(self: &PE_unwind_aarch64_UnpackedFunction) -> u8; + fn E(self: &PE_unwind_aarch64_UnpackedFunction) -> u8; + fn epilog_count(self: &PE_unwind_aarch64_UnpackedFunction) -> u16; + fn epilog_offset(self: &PE_unwind_aarch64_UnpackedFunction) -> u16; + fn code_words(self: &PE_unwind_aarch64_UnpackedFunction) -> u32; + fn exception_handler(self: &PE_unwind_aarch64_UnpackedFunction) -> u32; + fn epilog_scopes( + self: &PE_unwind_aarch64_UnpackedFunction, + ) -> UniquePtr; + + type PE_unwind_aarch64_UnpackedFunction_epilog_scope_t; + + fn start_offset(self: &PE_unwind_aarch64_UnpackedFunction_epilog_scope_t) -> u32; + fn reserved(self: &PE_unwind_aarch64_UnpackedFunction_epilog_scope_t) -> u8; + fn start_index(self: &PE_unwind_aarch64_UnpackedFunction_epilog_scope_t) -> u16; + + type PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes; + + fn next( + self: Pin<&mut PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes>, + ) -> UniquePtr; + fn size(self: &PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_x64.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_x64.rs new file mode 100644 index 0000000..b3d81ae --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/runtime_function_x64.rs @@ -0,0 +1,47 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/RuntimeFunctionX64.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ExceptionInfo = crate::pe::exception_info::ffi::PE_ExceptionInfo; + type PE_unwind_x64_Code = crate::pe::unwind_code_x64::ffi::PE_unwind_x64_Code; + + type PE_RuntimeFunctionX64; + + #[Self = "PE_RuntimeFunctionX64"] + fn classof(entry: &PE_ExceptionInfo) -> bool; + fn rva_end(self: &PE_RuntimeFunctionX64) -> u32; + fn unwind_rva(self: &PE_RuntimeFunctionX64) -> u32; + fn size(self: &PE_RuntimeFunctionX64) -> u32; + fn unwind_info( + self: &PE_RuntimeFunctionX64, + ) -> UniquePtr; + + type PE_RuntimeFunctionX64_unwind_info_t; + + fn raw_opcodes(self: &PE_RuntimeFunctionX64_unwind_info_t) -> Span; + fn version(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn flags(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn opcodes( + self: &PE_RuntimeFunctionX64_unwind_info_t, + ) -> UniquePtr; + fn chained(self: &PE_RuntimeFunctionX64_unwind_info_t) -> UniquePtr; + fn to_string(self: &PE_RuntimeFunctionX64_unwind_info_t) -> UniquePtr; + fn sizeof_prologue(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn count_opcodes(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn frame_reg(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn frame_reg_offset(self: &PE_RuntimeFunctionX64_unwind_info_t) -> u8; + fn handler(self: &PE_RuntimeFunctionX64_unwind_info_t, is_set: Pin<&mut u32>) -> u32; + + type PE_RuntimeFunctionX64_unwind_info_t_it_opcodes; + + fn next( + self: Pin<&mut PE_RuntimeFunctionX64_unwind_info_t_it_opcodes>, + ) -> UniquePtr; + fn size(self: &PE_RuntimeFunctionX64_unwind_info_t_it_opcodes) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/section.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/section.rs new file mode 100644 index 0000000..9485031 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/section.rs @@ -0,0 +1,35 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/Section.hpp"); + + type Span = crate::utils::ffi::Span; + type COFF_String = crate::coff::string::ffi::COFF_String; + + type PE_Section; + + fn padding(self: &PE_Section) -> Span; + #[Self = "PE_Section"] + fn create() -> UniquePtr; + #[Self = "PE_Section"] + fn create_with_name(name: &CxxString) -> UniquePtr; + #[Self = "PE_Section"] + unsafe fn create_with_content( + name: &CxxString, + buffer: *const u8, + size: usize, + ) -> UniquePtr; + fn sizeof_raw_data(self: &PE_Section) -> u32; + fn virtual_size(self: &PE_Section) -> u32; + fn pointerto_raw_data(self: &PE_Section) -> u32; + fn pointerto_relocation(self: &PE_Section) -> u32; + fn pointerto_line_numbers(self: &PE_Section) -> u32; + fn numberof_relocations(self: &PE_Section) -> u16; + fn numberof_line_numbers(self: &PE_Section) -> u16; + fn characteristics(self: &PE_Section) -> u32; + fn is_discardable(self: &PE_Section) -> bool; + fn coff_string(self: &PE_Section) -> UniquePtr; + fn set_virtual_size(self: Pin<&mut PE_Section>, virtual_size: u32); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature.rs new file mode 100644 index 0000000..45ffbeb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature.rs @@ -0,0 +1,9 @@ +pub mod attributes; +pub mod content_info; +pub mod generic_content; +pub mod pkcs9_tst_info; +pub mod rsa_info; +pub mod signature; +pub mod signer_info; +pub mod spc_indirect_data; +pub mod x509; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes.rs new file mode 100644 index 0000000..d55fd08 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes.rs @@ -0,0 +1,14 @@ +pub mod attribute; +pub mod content_type; +pub mod generic_type; +pub mod ms_counter_sign; +pub mod ms_manifest_binary_id; +pub mod ms_spc_nested_signature; +pub mod ms_spc_statement_type; +pub mod pkcs9_at_sequence_number; +pub mod pkcs9_counter_signature; +pub mod pkcs9_message_digest; +pub mod pkcs9_signing_time; +pub mod signing_certificate_v2; +pub mod spc_relaxed_pe_marker_check; +pub mod spc_sp_opus_info; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/attribute.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/attribute.rs new file mode 100644 index 0000000..616686b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/attribute.rs @@ -0,0 +1,10 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/Attribute.hpp"); + + type PE_Attribute; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/content_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/content_type.rs new file mode 100644 index 0000000..d96455e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/content_type.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/ContentType.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_ContentType; + + #[Self = "PE_ContentType"] + fn classof(attr: &PE_Attribute) -> bool; + fn oid(self: &PE_ContentType) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/generic_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/generic_type.rs new file mode 100644 index 0000000..9a61f3c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/generic_type.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/GenericType.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_GenericType; + fn raw_content(self: &PE_GenericType) -> Span; + #[Self = "PE_GenericType"] + fn classof(attr: &PE_Attribute) -> bool; + + fn oid(self: &PE_GenericType) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_counter_sign.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_counter_sign.rs new file mode 100644 index 0000000..7033c50 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_counter_sign.rs @@ -0,0 +1,35 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/MsCounterSign.hpp"); + + type PE_ContentInfo = crate::pe::signature::content_info::ffi::PE_ContentInfo; + type PE_SignerInfo = crate::pe::signature::signer_info::ffi::PE_SignerInfo; + type PE_x509 = crate::pe::signature::x509::ffi::PE_x509; + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_MsCounterSign; + #[Self = "PE_MsCounterSign"] + fn classof(attr: &PE_Attribute) -> bool; + + fn version(self: &PE_MsCounterSign) -> u32; + fn digest_algorithm(self: &PE_MsCounterSign) -> u32; + fn content_info(self: &PE_MsCounterSign) -> UniquePtr; + fn certificates(self: &PE_MsCounterSign) -> UniquePtr; + fn signers(self: &PE_MsCounterSign) -> UniquePtr; + + type PE_MsCounterSign_it_certificates; + + fn next(self: Pin<&mut PE_MsCounterSign_it_certificates>) -> UniquePtr; + fn size(self: &PE_MsCounterSign_it_certificates) -> u64; + + type PE_MsCounterSign_it_signers; + + fn next(self: Pin<&mut PE_MsCounterSign_it_signers>) -> UniquePtr; + fn size(self: &PE_MsCounterSign_it_signers) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_manifest_binary_id.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_manifest_binary_id.rs new file mode 100644 index 0000000..4304419 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_manifest_binary_id.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/MsManifestBinaryID.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_MsManifestBinaryID; + #[Self = "PE_MsManifestBinaryID"] + fn classof(attr: &PE_Attribute) -> bool; + + fn manifest_id(self: &PE_MsManifestBinaryID) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_nested_signature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_nested_signature.rs new file mode 100644 index 0000000..9a5c9d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_nested_signature.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/MsSpcNestedSignature.hpp"); + + type PE_Signature = crate::pe::signature::signature::ffi::PE_Signature; + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_MsSpcNestedSignature; + #[Self = "PE_MsSpcNestedSignature"] + fn classof(attr: &PE_Attribute) -> bool; + + fn sig(self: &PE_MsSpcNestedSignature) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_statement_type.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_statement_type.rs new file mode 100644 index 0000000..ee2ce54 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/ms_spc_statement_type.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/MsSpcStatementType.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_MsSpcStatementType; + #[Self = "PE_MsSpcStatementType"] + fn classof(attr: &PE_Attribute) -> bool; + + fn oid(self: &PE_MsSpcStatementType) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_at_sequence_number.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_at_sequence_number.rs new file mode 100644 index 0000000..effee84 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_at_sequence_number.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/PKCS9AtSequenceNumber.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_PKCS9AtSequenceNumber; + #[Self = "PE_PKCS9AtSequenceNumber"] + fn classof(attr: &PE_Attribute) -> bool; + + fn number(self: &PE_PKCS9AtSequenceNumber) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_counter_signature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_counter_signature.rs new file mode 100644 index 0000000..534f154 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_counter_signature.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/PKCS9CounterSignature.hpp"); + + type PE_SignerInfo = crate::pe::signature::signer_info::ffi::PE_SignerInfo; + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_PKCS9CounterSignature; + #[Self = "PE_PKCS9CounterSignature"] + fn classof(attr: &PE_Attribute) -> bool; + + fn signer(self: &PE_PKCS9CounterSignature) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_message_digest.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_message_digest.rs new file mode 100644 index 0000000..39c3393 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_message_digest.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/PKCS9MessageDigest.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_PKCS9MessageDigest; + fn digest(self: &PE_PKCS9MessageDigest) -> Span; + #[Self = "PE_PKCS9MessageDigest"] + fn classof(attr: &PE_Attribute) -> bool; + + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_signing_time.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_signing_time.rs new file mode 100644 index 0000000..3d8d6d3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/pkcs9_signing_time.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/PKCS9SigningTime.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_PKCS9SigningTime; + #[Self = "PE_PKCS9SigningTime"] + fn classof(attr: &PE_Attribute) -> bool; + + fn time(self: &PE_PKCS9SigningTime) -> UniquePtr>; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/signing_certificate_v2.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/signing_certificate_v2.rs new file mode 100644 index 0000000..49dc2df --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/signing_certificate_v2.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/SigningCertificateV2.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_SigningCertificateV2; + #[Self = "PE_SigningCertificateV2"] + fn classof(attr: &PE_Attribute) -> bool; + + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_relaxed_pe_marker_check.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_relaxed_pe_marker_check.rs new file mode 100644 index 0000000..b43ff63 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_relaxed_pe_marker_check.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_SpcRelaxedPeMarkerCheck; + #[Self = "PE_SpcRelaxedPeMarkerCheck"] + fn classof(attr: &PE_Attribute) -> bool; + + fn value(self: &PE_SpcRelaxedPeMarkerCheck) -> u32; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_sp_opus_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_sp_opus_info.rs new file mode 100644 index 0000000..ebf0148 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/attributes/spc_sp_opus_info.rs @@ -0,0 +1,16 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/attributes/SpcSpOpusInfo.hpp"); + + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_SpcSpOpusInfo; + #[Self = "PE_SpcSpOpusInfo"] + fn classof(attr: &PE_Attribute) -> bool; + + fn program_name(self: &PE_SpcSpOpusInfo) -> UniquePtr; + fn more_info(self: &PE_SpcSpOpusInfo) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/content_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/content_info.rs new file mode 100644 index 0000000..127ac17 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/content_info.rs @@ -0,0 +1,20 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/ContentInfo.hpp"); + + type PE_ContentInfo; + + fn content_type(self: &PE_ContentInfo) -> UniquePtr; + fn value(self: &PE_ContentInfo) -> UniquePtr; + fn digest_algorithm(self: &PE_ContentInfo) -> u32; + fn digest(self: &PE_ContentInfo) -> UniquePtr>; + + type PE_ContentInfo_Content; + + fn content_type(self: &PE_ContentInfo_Content) -> UniquePtr; + } + + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/generic_content.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/generic_content.rs new file mode 100644 index 0000000..f8cfe35 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/generic_content.rs @@ -0,0 +1,18 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/GenericContent.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ContentInfo_Content = + crate::pe::signature::content_info::ffi::PE_ContentInfo_Content; + + type PE_GenericContent; + + fn raw(self: &PE_GenericContent) -> Span; + #[Self = "PE_GenericContent"] + fn classof(info: &PE_ContentInfo_Content) -> bool; + fn oid(self: &PE_GenericContent) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/pkcs9_tst_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/pkcs9_tst_info.rs new file mode 100644 index 0000000..8e44373 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/pkcs9_tst_info.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/PKCS9TSTInfo.hpp"); + + type PE_ContentInfo_Content = + crate::pe::signature::content_info::ffi::PE_ContentInfo_Content; + + type PE_PKCS9TSTInfo; + + #[Self = "PE_PKCS9TSTInfo"] + fn classof(info: &PE_ContentInfo_Content) -> bool; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/rsa_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/rsa_info.rs new file mode 100644 index 0000000..0b27d17 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/rsa_info.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/RsaInfo.hpp"); + + type PE_RsaInfo; + + fn key_size(self: &PE_RsaInfo) -> u32; + fn has_public_key(self: &PE_RsaInfo) -> bool; + fn has_private_key(self: &PE_RsaInfo) -> bool; + fn N(self: &PE_RsaInfo) -> UniquePtr>; + fn E(self: &PE_RsaInfo) -> UniquePtr>; + fn D(self: &PE_RsaInfo) -> UniquePtr>; + fn P(self: &PE_RsaInfo) -> UniquePtr>; + fn Q(self: &PE_RsaInfo) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signature.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signature.rs new file mode 100644 index 0000000..26cbb83 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signature.rs @@ -0,0 +1,57 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/Signature.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ContentInfo = crate::pe::signature::content_info::ffi::PE_ContentInfo; + type PE_SignerInfo = crate::pe::signature::signer_info::ffi::PE_SignerInfo; + type PE_x509 = crate::pe::signature::x509::ffi::PE_x509; + + type PE_Signature; + + fn raw_der(self: &PE_Signature) -> Span; + #[Self = "PE_Signature"] + fn parse(path: &CxxString) -> UniquePtr; + #[Self = "PE_Signature"] + unsafe fn from_raw(buffer: *mut u8, size: usize) -> UniquePtr; + fn version(self: &PE_Signature) -> u32; + fn digest_algorithm(self: &PE_Signature) -> u32; + fn content_info(self: &PE_Signature) -> UniquePtr; + fn certificates(self: &PE_Signature) -> UniquePtr; + fn signers(self: &PE_Signature) -> UniquePtr; + fn find_crt_by_subject(self: &PE_Signature, subject: &CxxString) -> UniquePtr; + fn find_crt_by_issuer(self: &PE_Signature, issuer: &CxxString) -> UniquePtr; + unsafe fn find_crt_by_serial( + self: &PE_Signature, + serial: *const u8, + size: usize, + ) -> UniquePtr; + unsafe fn find_crt_by_subject_and_serial( + self: &PE_Signature, + subject: &CxxString, + serial: *const u8, + size: usize, + ) -> UniquePtr; + unsafe fn find_crt_by_issuer_and_serial( + self: &PE_Signature, + issuer: &CxxString, + serial: *const u8, + size: usize, + ) -> UniquePtr; + fn check(self: &PE_Signature, flags: u32) -> u32; + + type PE_Signature_it_certificates; + + fn next(self: Pin<&mut PE_Signature_it_certificates>) -> UniquePtr; + fn size(self: &PE_Signature_it_certificates) -> u64; + + type PE_Signature_it_signers; + + fn next(self: Pin<&mut PE_Signature_it_signers>) -> UniquePtr; + fn size(self: &PE_Signature_it_signers) -> u64; + } + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signer_info.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signer_info.rs new file mode 100644 index 0000000..d923a4b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/signer_info.rs @@ -0,0 +1,48 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/SignerInfo.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_x509 = crate::pe::signature::x509::ffi::PE_x509; + type PE_Attribute = crate::pe::signature::attributes::attribute::ffi::PE_Attribute; + + type PE_SignerInfo; + + fn serial_number(self: &PE_SignerInfo) -> Span; + fn raw_auth_data(self: &PE_SignerInfo) -> Span; + fn version(self: &PE_SignerInfo) -> u32; + fn issuer(self: &PE_SignerInfo) -> UniquePtr; + fn digest_algorithm(self: &PE_SignerInfo) -> u32; + fn encryption_algorithm(self: &PE_SignerInfo) -> u32; + fn encrypted_digest(self: &PE_SignerInfo) -> UniquePtr>; + fn cert(self: &PE_SignerInfo) -> UniquePtr; + fn get_attribute(self: &PE_SignerInfo, kind: u32) -> UniquePtr; + fn get_auth_attribute(self: &PE_SignerInfo, kind: u32) -> UniquePtr; + fn get_unauth_attribute(self: &PE_SignerInfo, kind: u32) -> UniquePtr; + fn authenticated_attributes( + self: &PE_SignerInfo, + ) -> UniquePtr; + fn unauthenticated_attributes( + self: &PE_SignerInfo, + ) -> UniquePtr; + + type PE_SignerInfo_it_authenticated_attributes; + + fn next( + self: Pin<&mut PE_SignerInfo_it_authenticated_attributes>, + ) -> UniquePtr; + fn size(self: &PE_SignerInfo_it_authenticated_attributes) -> u64; + + type PE_SignerInfo_it_unauthenticated_attributes; + + fn next( + self: Pin<&mut PE_SignerInfo_it_unauthenticated_attributes>, + ) -> UniquePtr; + fn size(self: &PE_SignerInfo_it_unauthenticated_attributes) -> u64; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/spc_indirect_data.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/spc_indirect_data.rs new file mode 100644 index 0000000..b0c76d1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/spc_indirect_data.rs @@ -0,0 +1,20 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/SpcIndirectData.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_ContentInfo_Content = + crate::pe::signature::content_info::ffi::PE_ContentInfo_Content; + + type PE_SpcIndirectData; + + fn digest(self: &PE_SpcIndirectData) -> Span; + #[Self = "PE_SpcIndirectData"] + fn classof(info: &PE_ContentInfo_Content) -> bool; + fn digest_algorithm(self: &PE_SpcIndirectData) -> u32; + fn file(self: &PE_SpcIndirectData) -> UniquePtr; + fn url(self: &PE_SpcIndirectData) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/x509.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/x509.rs new file mode 100644 index 0000000..e53949d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/signature/x509.rs @@ -0,0 +1,37 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/signature/x509.hpp"); + + type PE_RsaInfo = crate::pe::signature::rsa_info::ffi::PE_RsaInfo; + + type PE_x509; + + fn version(self: &PE_x509) -> u32; + fn serial_number(self: &PE_x509) -> UniquePtr>; + fn signature_algorithm(self: &PE_x509) -> UniquePtr; + fn valid_from(self: &PE_x509) -> UniquePtr>; + fn valid_to(self: &PE_x509) -> UniquePtr>; + fn issuer(self: &PE_x509) -> UniquePtr; + fn subject(self: &PE_x509) -> UniquePtr; + fn raw(self: &PE_x509) -> UniquePtr>; + fn key_type(self: &PE_x509) -> u32; + fn is_ca(self: &PE_x509) -> bool; + fn signature(self: &PE_x509) -> UniquePtr>; + fn rsa_info(self: &PE_x509) -> UniquePtr; + fn verify(self: &PE_x509, ca: &PE_x509) -> u32; + unsafe fn check_signature( + self: &PE_x509, + hash: *const u8, + hsize: usize, + signature: *const u8, + sigsiz: usize, + algo: u32, + ) -> u32; + fn key_usage(self: &PE_x509) -> UniquePtr>; + fn ext_key_usage(self: &PE_x509) -> UniquePtr>; + fn certificate_policies(self: &PE_x509) -> UniquePtr>; + } + + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/tls.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/tls.rs new file mode 100644 index 0000000..adc8798 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/tls.rs @@ -0,0 +1,32 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/TLS.hpp"); + + type Span = crate::utils::ffi::Span; + type PE_DataDirectory = crate::pe::data_directories::ffi::PE_DataDirectory; + type PE_Section = crate::pe::section::ffi::PE_Section; + + type PE_TLS; + + fn data_template(self: &PE_TLS) -> Span; + #[Self = "PE_TLS"] + fn create() -> UniquePtr; + fn callbacks(self: &PE_TLS) -> UniquePtr>; + fn addressof_index(self: &PE_TLS) -> u64; + fn addressof_callbacks(self: &PE_TLS) -> u64; + fn sizeof_zero_fill(self: &PE_TLS) -> u32; + fn characteristics(self: &PE_TLS) -> u32; + fn addressof_raw_data(self: &PE_TLS) -> UniquePtr>; + fn section(self: &PE_TLS) -> UniquePtr; + fn data_directory(self: &PE_TLS) -> UniquePtr; + fn add_callback(self: Pin<&mut PE_TLS>, addr: u64); + fn set_characteristics(self: Pin<&mut PE_TLS>, value: u32); + fn set_addressof_index(self: Pin<&mut PE_TLS>, value: u64); + fn set_addressof_callback(self: Pin<&mut PE_TLS>, value: u64); + fn set_sizeof_zero_fill(self: Pin<&mut PE_TLS>, value: u32); + unsafe fn set_callbacks(self: Pin<&mut PE_TLS>, ptr: *const u64, size: usize); + unsafe fn set_data_template(self: Pin<&mut PE_TLS>, ptr: *const u8, size: usize); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/unwind_code_x64.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/unwind_code_x64.rs new file mode 100644 index 0000000..98fa31d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/unwind_code_x64.rs @@ -0,0 +1,72 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/UnwindCodeX64.hpp"); + + type PE_unwind_x64_Alloc; + + #[Self = "PE_unwind_x64_Alloc"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn size(self: &PE_unwind_x64_Alloc) -> u32; + + type PE_unwind_x64_Code; + + fn position(self: &PE_unwind_x64_Code) -> u32; + fn opcode(self: &PE_unwind_x64_Code) -> u32; + fn to_string(self: &PE_unwind_x64_Code) -> UniquePtr; + + type PE_unwind_x64_Epilog; + + #[Self = "PE_unwind_x64_Epilog"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn flags(self: &PE_unwind_x64_Epilog) -> u8; + fn size(self: &PE_unwind_x64_Epilog) -> u32; + + type PE_unwind_x64_PushMachFrame; + + #[Self = "PE_unwind_x64_PushMachFrame"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn value(self: &PE_unwind_x64_PushMachFrame) -> u8; + + type PE_unwind_x64_PushNonVol; + + #[Self = "PE_unwind_x64_PushNonVol"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn reg(self: &PE_unwind_x64_PushNonVol) -> u32; + + type PE_unwind_x64_SaveNonVolatile; + + #[Self = "PE_unwind_x64_SaveNonVolatile"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn reg(self: &PE_unwind_x64_SaveNonVolatile) -> u32; + fn offset(self: &PE_unwind_x64_SaveNonVolatile) -> u32; + + type PE_unwind_x64_SaveXMM128; + + #[Self = "PE_unwind_x64_SaveXMM128"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn num(self: &PE_unwind_x64_SaveXMM128) -> u8; + fn offset(self: &PE_unwind_x64_SaveXMM128) -> u32; + + type PE_unwind_x64_SetFPReg; + + #[Self = "PE_unwind_x64_SetFPReg"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + fn reg(self: &PE_unwind_x64_SetFPReg) -> u32; + + type PE_unwind_x64_Spare; + + #[Self = "PE_unwind_x64_Spare"] + fn classof(entry: &PE_unwind_x64_Code) -> bool; + } + + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/pe/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/pe/utils.rs new file mode 100644 index 0000000..1795061 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/pe/utils.rs @@ -0,0 +1,25 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/PE/utils.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type PE_Binary = crate::pe::binary::ffi::PE_Binary; + type PE_Import = crate::pe::import::ffi::PE_Import; + + type PE_Utils; + + #[Self = "PE_Utils"] + fn is_pe(file: &CxxString) -> bool; + #[Self = "PE_Utils"] + fn get_type(file: &CxxString) -> u32; + #[Self = "PE_Utils"] + fn get_imphash(bin: &PE_Binary, mode: u32) -> UniquePtr; + #[Self = "PE_Utils"] + fn oid_to_string(oid: &CxxString) -> UniquePtr; + #[Self = "PE_Utils"] + fn resolve_ordinals(imp: &PE_Import, strict: bool, use_std: bool) -> UniquePtr; + #[Self = "PE_Utils"] + unsafe fn check_layout(bin: &PE_Binary, error: *mut CxxString) -> bool; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime.rs new file mode 100644 index 0000000..8ddfe75 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime.rs @@ -0,0 +1,23 @@ +pub mod android; +pub mod assembler; +pub mod disassembler; +pub mod host; +pub mod linux; +pub mod memory; +pub mod memory_layout; +pub mod module; +pub mod osx; +pub mod process; +pub mod windows; + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + fn runtime_enabled() -> bool; + fn runtime_platform() -> u32; + fn runtime_arch() -> u32; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android.rs new file mode 100644 index 0000000..5e84f5e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android.rs @@ -0,0 +1,4 @@ +pub mod host; +pub mod module; +pub mod process; +pub mod property; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/host.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/host.rs new file mode 100644 index 0000000..97a524f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/host.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/android/Host.hpp"); + + type runtime_android_Host; + + #[Self = "runtime_android_Host"] + fn sdk_version() -> i64; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/module.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/module.rs new file mode 100644 index 0000000..0154654 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/module.rs @@ -0,0 +1,33 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/android/Module.hpp"); + + type runtime_Module = crate::runtime::module::ffi::runtime_Module; + type ELF_Binary = crate::elf::binary::ffi::ELF_Binary; + type ELF_ParserConfig = crate::elf::binary::ffi::ELF_ParserConfig; + + type runtime_android_Module; + + fn handle(self: &runtime_android_Module) -> u64; + fn dlsym(self: &runtime_android_Module, name: &CxxString) -> u64; + fn parse_from_path(self: &runtime_android_Module) -> UniquePtr; + fn parse_from_path_with_config( + self: &runtime_android_Module, + config: &ELF_ParserConfig, + ) -> UniquePtr; + fn parse_from_memory(self: &runtime_android_Module) -> UniquePtr; + fn parse_from_memory_with_config( + self: &runtime_android_Module, + config: &ELF_ParserConfig, + ) -> UniquePtr; + + #[Self = "runtime_android_Module"] + fn from_handle(handle: u64) -> UniquePtr; + #[Self = "runtime_android_Module"] + fn classof(m: &runtime_Module) -> bool; + + fn runtime_android_dlopen(name: &CxxString) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/process.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/process.rs new file mode 100644 index 0000000..424b067 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/process.rs @@ -0,0 +1,21 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/android/Process.hpp"); + + type runtime_android_Process; + type runtime_android_Property = + crate::runtime::android::property::ffi::runtime_android_Property; + type runtime_android_it_properties = + crate::runtime::android::property::ffi::runtime_android_it_properties; + + #[Self = "runtime_android_Process"] + fn cmdline() -> UniquePtr; + + #[Self = "runtime_android_Process"] + fn get_system_property(name: &CxxString) -> UniquePtr; + + #[Self = "runtime_android_Process"] + fn properties() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/property.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/property.rs new file mode 100644 index 0000000..b667179 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/android/property.rs @@ -0,0 +1,20 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/android/Property.hpp"); + + type runtime_android_Property; + type runtime_android_it_properties; + + fn name(self: &runtime_android_Property) -> UniquePtr; + fn value(self: &runtime_android_Property) -> UniquePtr; + fn serial(self: &runtime_android_Property) -> u32; + fn to_string(self: &runtime_android_Property) -> UniquePtr; + + fn next( + self: Pin<&mut runtime_android_it_properties>, + ) -> UniquePtr; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/assembler.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/assembler.rs new file mode 100644 index 0000000..2983ef1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/assembler.rs @@ -0,0 +1,15 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Assembler.hpp"); + + type AssemblerConfig_r = crate::asm::config::AssemblerConfig_r; + + fn runtime_assemble(address: u64, Asm: &CxxString) -> UniquePtr>; + fn runtime_assemble_with_config( + address: u64, + Asm: &CxxString, + ffi_config: &AssemblerConfig_r, + ) -> UniquePtr>; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/disassembler.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/disassembler.rs new file mode 100644 index 0000000..57db4b3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/disassembler.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Disassembler.hpp"); + + type asm_Instruction = crate::asm::instruction::ffi::asm_Instruction; + type runtime_it_instructions; + + fn next(self: Pin<&mut runtime_it_instructions>) -> UniquePtr; + + fn runtime_disassemble(addr: u64) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/host.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/host.rs new file mode 100644 index 0000000..5294595 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/host.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Host.hpp"); + + type runtime_Host; + + #[Self = "runtime_Host"] + fn name() -> UniquePtr; + #[Self = "runtime_Host"] + fn home_dir() -> UniquePtr; + #[Self = "runtime_Host"] + fn tmp_dir() -> UniquePtr; + #[Self = "runtime_Host"] + fn config_dir() -> UniquePtr; + #[Self = "runtime_Host"] + fn cache_dir() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux.rs new file mode 100644 index 0000000..45c92a1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux.rs @@ -0,0 +1,3 @@ +pub mod host; +pub mod module; +pub mod process; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/host.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/host.rs new file mode 100644 index 0000000..b016df5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/host.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/linux/Host.hpp"); + + type runtime_linux_Host; + + #[Self = "runtime_linux_Host"] + fn sys_name() -> UniquePtr; + #[Self = "runtime_linux_Host"] + fn sys_release() -> UniquePtr; + #[Self = "runtime_linux_Host"] + fn sys_version() -> UniquePtr; + #[Self = "runtime_linux_Host"] + fn hardware() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/module.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/module.rs new file mode 100644 index 0000000..1f5113d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/module.rs @@ -0,0 +1,33 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/linux/Module.hpp"); + + type runtime_Module = crate::runtime::module::ffi::runtime_Module; + type ELF_Binary = crate::elf::binary::ffi::ELF_Binary; + type ELF_ParserConfig = crate::elf::binary::ffi::ELF_ParserConfig; + + type runtime_linux_Module; + + fn handle(self: &runtime_linux_Module) -> u64; + fn dlsym(self: &runtime_linux_Module, name: &CxxString) -> u64; + fn parse_from_path(self: &runtime_linux_Module) -> UniquePtr; + fn parse_from_path_with_config( + self: &runtime_linux_Module, + config: &ELF_ParserConfig, + ) -> UniquePtr; + fn parse_from_memory(self: &runtime_linux_Module) -> UniquePtr; + fn parse_from_memory_with_config( + self: &runtime_linux_Module, + config: &ELF_ParserConfig, + ) -> UniquePtr; + + #[Self = "runtime_linux_Module"] + fn from_handle(handle: u64) -> UniquePtr; + #[Self = "runtime_linux_Module"] + fn classof(m: &runtime_Module) -> bool; + + fn runtime_linux_dlopen(name: &CxxString) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/process.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/process.rs new file mode 100644 index 0000000..a4d4718 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/linux/process.rs @@ -0,0 +1,14 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/linux/Process.hpp"); + + type runtime_linux_Process; + + #[Self = "runtime_linux_Process"] + fn cmdline() -> UniquePtr; + + #[Self = "runtime_linux_Process"] + fn glibc_version() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory.rs new file mode 100644 index 0000000..c0f396c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory.rs @@ -0,0 +1,40 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Memory.hpp"); + + type runtime_Memory; + type runtime_Memory_Chunk; + + fn addr(self: &runtime_Memory_Chunk) -> u64; + fn size(self: &runtime_Memory_Chunk) -> u64; + fn permissions(self: &runtime_Memory_Chunk) -> u32; + fn page_start(self: &runtime_Memory_Chunk) -> u64; + fn page_end(self: &runtime_Memory_Chunk) -> u64; + fn change_permissions(self: Pin<&mut runtime_Memory_Chunk>, p: u32); + fn make_x(self: Pin<&mut runtime_Memory_Chunk>); + fn make_rw(self: Pin<&mut runtime_Memory_Chunk>); + fn make_rx(self: Pin<&mut runtime_Memory_Chunk>); + fn make_rwx(self: Pin<&mut runtime_Memory_Chunk>); + fn make_ro(self: Pin<&mut runtime_Memory_Chunk>); + fn cache_flush(self: Pin<&mut runtime_Memory_Chunk>); + fn is_valid(self: &runtime_Memory_Chunk) -> bool; + fn deallocate(self: Pin<&mut runtime_Memory_Chunk>, err: Pin<&mut u32>); + fn to_string(self: &runtime_Memory_Chunk) -> UniquePtr; + + #[Self = "runtime_Memory"] + fn mmap(size: u64, flags: u32, permission: u32) -> UniquePtr; + #[Self = "runtime_Memory"] + fn mmap_hint( + hint: u64, + size: u64, + flags: u32, + permission: u32, + ) -> UniquePtr; + #[Self = "runtime_Memory"] + fn munmap(chunk: Pin<&mut runtime_Memory_Chunk>, err: Pin<&mut u32>); + #[Self = "runtime_Memory"] + fn mprotect(chunk: Pin<&mut runtime_Memory_Chunk>, flags: u32, err: Pin<&mut u32>); + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory_layout.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory_layout.rs new file mode 100644 index 0000000..fc745db --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/memory_layout.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/MemoryLayout.hpp"); + + type runtime_MemoryLayout_Region; + type runtime_it_memory_layout; + + fn name(self: &runtime_MemoryLayout_Region) -> UniquePtr; + fn addr(self: &runtime_MemoryLayout_Region) -> u64; + fn size(self: &runtime_MemoryLayout_Region) -> u64; + fn end_addr(self: &runtime_MemoryLayout_Region) -> u64; + fn contains(self: &runtime_MemoryLayout_Region, addr: u64) -> bool; + fn to_string(self: &runtime_MemoryLayout_Region) -> UniquePtr; + + fn next(self: Pin<&mut runtime_it_memory_layout>) + -> UniquePtr; + + fn runtime_memory_layout() -> UniquePtr; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/module.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/module.rs new file mode 100644 index 0000000..31585ec --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/module.rs @@ -0,0 +1,25 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Module.hpp"); + + type runtime_Module; + type runtime_it_modules; + + fn name(self: &runtime_Module) -> UniquePtr; + fn path(self: &runtime_Module) -> UniquePtr; + fn imagebase(self: &runtime_Module) -> u64; + fn size(self: &runtime_Module) -> u64; + fn end(self: &runtime_Module) -> u64; + fn contains(self: &runtime_Module, addr: u64) -> bool; + + fn next(self: Pin<&mut runtime_it_modules>) -> UniquePtr; + + fn runtime_modules() -> UniquePtr; + fn runtime_module_from_name(name: &CxxString) -> UniquePtr; + fn runtime_module_from_path(path: &CxxString) -> UniquePtr; + fn runtime_module_from_addr(addr: u64) -> UniquePtr; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx.rs new file mode 100644 index 0000000..45c92a1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx.rs @@ -0,0 +1,3 @@ +pub mod host; +pub mod module; +pub mod process; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/host.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/host.rs new file mode 100644 index 0000000..75256ab --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/host.rs @@ -0,0 +1,36 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/osx/Host.hpp"); + + type runtime_osx_Host; + type runtime_osx_Host_version_t; + + #[Self = "runtime_osx_Host"] + fn os_version_name() -> UniquePtr; + + #[Self = "runtime_osx_Host"] + fn is_sip_enabled() -> bool; + + fn get_major(self: &runtime_osx_Host_version_t) -> u32; + fn get_minor(self: &runtime_osx_Host_version_t) -> u32; + fn get_patch(self: &runtime_osx_Host_version_t) -> u32; + fn to_string(self: &runtime_osx_Host_version_t) -> UniquePtr; + + #[Self = "runtime_osx_Host_version_t"] + fn os_version() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn big_sur() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn monterey() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn ventura() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn sonoma() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn sequoia() -> UniquePtr; + #[Self = "runtime_osx_Host_version_t"] + fn tahoe() -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/module.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/module.rs new file mode 100644 index 0000000..eb46177 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/module.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/osx/Module.hpp"); + + type runtime_Module = crate::runtime::module::ffi::runtime_Module; + type MachO_Binary = crate::macho::binary::ffi::MachO_Binary; + + type runtime_osx_Module; + + fn handle(self: &runtime_osx_Module) -> u64; + fn dlsym(self: &runtime_osx_Module, name: &CxxString) -> u64; + fn parse_from_path(self: &runtime_osx_Module) -> UniquePtr; + fn parse_from_memory(self: &runtime_osx_Module) -> UniquePtr; + + #[Self = "runtime_osx_Module"] + fn from_handle(handle: u64) -> UniquePtr; + #[Self = "runtime_osx_Module"] + fn classof(m: &runtime_Module) -> bool; + + fn runtime_osx_dlopen(name: &CxxString) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/process.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/process.rs new file mode 100644 index 0000000..954cc4b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/osx/process.rs @@ -0,0 +1,11 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/osx/Process.hpp"); + + type runtime_osx_Process; + + #[Self = "runtime_osx_Process"] + fn dyld_version() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/process.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/process.rs new file mode 100644 index 0000000..cd7d0ac --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/process.rs @@ -0,0 +1,19 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/Process.hpp"); + + type runtime_Process; + + #[Self = "runtime_Process"] + fn pid() -> i32; + #[Self = "runtime_Process"] + fn tid() -> i32; + #[Self = "runtime_Process"] + fn platform() -> u32; + #[Self = "runtime_Process"] + fn arch() -> u32; + #[Self = "runtime_Process"] + fn page_size() -> u32; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows.rs new file mode 100644 index 0000000..2441dc2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows.rs @@ -0,0 +1,5 @@ +pub mod host; +pub mod ldr_data_table_entry; +pub mod module; +pub mod peb; +pub mod process; diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/host.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/host.rs new file mode 100644 index 0000000..d2874d1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/host.rs @@ -0,0 +1,17 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/windows/Host.hpp"); + + type runtime_windows_Host; + type runtime_windows_Host_version_t; + + fn get_major(self: &runtime_windows_Host_version_t) -> u32; + fn get_minor(self: &runtime_windows_Host_version_t) -> u32; + fn get_build_number(self: &runtime_windows_Host_version_t) -> u32; + + #[Self = "runtime_windows_Host"] + fn version() -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/ldr_data_table_entry.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/ldr_data_table_entry.rs new file mode 100644 index 0000000..d61d93c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/ldr_data_table_entry.rs @@ -0,0 +1,61 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/windows/LdrDataTableEntry.hpp"); + + type runtime_windows_LdrDataTableEntry; + type runtime_windows_it_ldr_data_table_entry; + + fn dll_base(self: &runtime_windows_LdrDataTableEntry) -> u64; + fn entry_point(self: &runtime_windows_LdrDataTableEntry) -> u64; + fn size_of_image(self: &runtime_windows_LdrDataTableEntry) -> u32; + fn full_dll_name(self: &runtime_windows_LdrDataTableEntry) -> UniquePtr; + fn base_dll_name(self: &runtime_windows_LdrDataTableEntry) -> UniquePtr; + + fn flags(self: &runtime_windows_LdrDataTableEntry) -> u32; + fn obsolete_load_count(self: &runtime_windows_LdrDataTableEntry) -> u16; + fn tls_index(self: &runtime_windows_LdrDataTableEntry) -> u16; + fn time_date_stamp(self: &runtime_windows_LdrDataTableEntry) -> u32; + fn entry_point_activation_context(self: &runtime_windows_LdrDataTableEntry) -> u64; + fn lock(self: &runtime_windows_LdrDataTableEntry) -> u64; + + fn ddag_node(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u64; + fn load_context(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u64; + fn parent_dll_base(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u64; + fn switch_back_context( + self: &runtime_windows_LdrDataTableEntry, + is_set: Pin<&mut u32>, + ) -> u64; + fn original_base(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u64; + fn load_time(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> i64; + fn base_name_hash_value( + self: &runtime_windows_LdrDataTableEntry, + is_set: Pin<&mut u32>, + ) -> u32; + fn load_reason(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> i32; + fn implicit_path_options( + self: &runtime_windows_LdrDataTableEntry, + is_set: Pin<&mut u32>, + ) -> u32; + fn reference_count(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u32; + fn dependent_load_flags( + self: &runtime_windows_LdrDataTableEntry, + is_set: Pin<&mut u32>, + ) -> u32; + fn signing_level(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u8; + fn check_sum(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u32; + fn active_patch_image_base( + self: &runtime_windows_LdrDataTableEntry, + is_set: Pin<&mut u32>, + ) -> u64; + fn hot_patch_state(self: &runtime_windows_LdrDataTableEntry, is_set: Pin<&mut u32>) -> u32; + + fn to_string(self: &runtime_windows_LdrDataTableEntry) -> UniquePtr; + + fn next( + self: Pin<&mut runtime_windows_it_ldr_data_table_entry>, + ) -> UniquePtr; + } + impl UniquePtr {} + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/module.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/module.rs new file mode 100644 index 0000000..de39739 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/module.rs @@ -0,0 +1,33 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/windows/Module.hpp"); + include!("LIEF/rust/COFF/Section.hpp"); + + type runtime_Module = crate::runtime::module::ffi::runtime_Module; + type PE_Binary = crate::pe::binary::ffi::PE_Binary; + type PE_ParserConfig = crate::pe::binary::ffi::PE_ParserConfig; + + type runtime_windows_Module; + + fn handle(self: &runtime_windows_Module) -> u64; + fn dlsym(self: &runtime_windows_Module, name: &CxxString) -> u64; + fn parse_from_path(self: &runtime_windows_Module) -> UniquePtr; + fn parse_from_path_with_config( + self: &runtime_windows_Module, + config: &PE_ParserConfig, + ) -> UniquePtr; + fn parse_from_memory(self: &runtime_windows_Module) -> UniquePtr; + fn parse_from_memory_with_config( + self: &runtime_windows_Module, + config: &PE_ParserConfig, + ) -> UniquePtr; + + #[Self = "runtime_windows_Module"] + fn classof(m: &runtime_Module) -> bool; + + fn runtime_windows_find_module(name: &CxxString) -> UniquePtr; + fn runtime_windows_dlopen(name: &CxxString) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/peb.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/peb.rs new file mode 100644 index 0000000..b4e9881 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/peb.rs @@ -0,0 +1,23 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/windows/PEB.hpp"); + + type runtime_windows_PEB; + type runtime_windows_it_ldr_data_table_entry = + crate::runtime::windows::ldr_data_table_entry::ffi::runtime_windows_it_ldr_data_table_entry; + + fn being_debugged(self: &runtime_windows_PEB) -> bool; + fn ldr(self: &runtime_windows_PEB) -> u64; + fn process_parameters(self: &runtime_windows_PEB) -> u64; + fn atl_thunk_slist_ptr(self: &runtime_windows_PEB) -> u64; + fn atl_thunk_slist_ptr32(self: &runtime_windows_PEB) -> u32; + fn post_process_init_routine(self: &runtime_windows_PEB) -> u64; + fn session_id(self: &runtime_windows_PEB) -> u32; + + fn entries( + self: &runtime_windows_PEB, + ) -> UniquePtr; + } + impl UniquePtr {} +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/process.rs b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/process.rs new file mode 100644 index 0000000..d9b36a8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/runtime/windows/process.rs @@ -0,0 +1,13 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/runtime/windows/Process.hpp"); + + type runtime_windows_PEB = crate::runtime::windows::peb::ffi::runtime_windows_PEB; + + type runtime_windows_Process; + + #[Self = "runtime_windows_Process"] + fn peb() -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/stream.rs b/vendor/lief/api/rust/crates/lief-ffi/src/stream.rs new file mode 100644 index 0000000..acac3a4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/stream.rs @@ -0,0 +1,24 @@ +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/Stream.hpp"); + + type COFF_Binary = crate::coff::binary::ffi::COFF_Binary; + type ELF_Binary = crate::elf::binary::ffi::ELF_Binary; + type MachO_FatBinary = crate::macho::fat_binary::ffi::MachO_FatBinary; + type PE_Binary = crate::pe::binary::ffi::PE_Binary; + + type RustStream; + + #[Self = "RustStream"] + unsafe fn from_rust(buffer: *mut u8, size: usize) -> UniquePtr; + fn is_elf(self: &RustStream) -> bool; + fn is_pe(self: &RustStream) -> bool; + fn is_macho(self: &RustStream) -> bool; + fn is_coff(self: &RustStream) -> bool; + fn as_elf(self: Pin<&mut RustStream>) -> UniquePtr; + fn as_macho(self: Pin<&mut RustStream>) -> UniquePtr; + fn as_pe(self: Pin<&mut RustStream>) -> UniquePtr; + fn as_coff(self: Pin<&mut RustStream>) -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffi/src/utils.rs b/vendor/lief/api/rust/crates/lief-ffi/src/utils.rs new file mode 100644 index 0000000..6f819da --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffi/src/utils.rs @@ -0,0 +1,64 @@ +#[repr(C)] +pub struct LIEFVersion { + pub major: u64, + pub minor: u64, + pub patch: u64, + pub id: u64, +} + +unsafe impl cxx::ExternType for LIEFVersion { + type Id = cxx::type_id!("LIEFVersion"); + type Kind = cxx::kind::Trivial; +} + +#[repr(C)] +pub struct Span { + pub ptr: *mut u8, + pub size: u64, +} + +unsafe impl cxx::ExternType for Span { + type Id = cxx::type_id!("Span"); + type Kind = cxx::kind::Trivial; +} + +pub struct Range { + pub low: u64, + pub high: u64, +} + +unsafe impl cxx::ExternType for Range { + type Id = cxx::type_id!("Range"); + type Kind = cxx::kind::Trivial; +} + +#[cxx::bridge] +pub mod ffi { + unsafe extern "C++" { + include!("LIEF/rust/utils.hpp"); + + type LIEFVersion = crate::utils::LIEFVersion; + + type Span = crate::utils::Span; + + type Range = crate::utils::Range; + + fn is_extended() -> bool; + + fn extended_version_info() -> UniquePtr; + + fn extended_version() -> LIEFVersion; + + fn version() -> LIEFVersion; + + fn demangle(mangled: &CxxString, err: Pin<&mut u32>) -> UniquePtr; + + unsafe fn dump(buffer: *const u8, size: usize) -> UniquePtr; + + unsafe fn dump_with_limit( + buffer: *const u8, + size: usize, + limit: u64, + ) -> UniquePtr; + } +} diff --git a/vendor/lief/api/rust/crates/lief-ffigen/Cargo.toml b/vendor/lief/api/rust/crates/lief-ffigen/Cargo.toml new file mode 100644 index 0000000..f2d205c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffigen/Cargo.toml @@ -0,0 +1,16 @@ +[package] +name = "lief-ffigen" +description = "Generate FFI bindings for LIEF" +edition.workspace = true +version.workspace = true +authors.workspace = true +license.workspace = true +rust-version.workspace = true + +[dependencies] +cxx-gen = { workspace = true } +serde = { workspace = true } +thiserror = { workspace = true } +proc-macro2 = { workspace = true } +miette = { workspace = true } +clap = { workspace = true } diff --git a/vendor/lief/api/rust/crates/lief-ffigen/src/main.rs b/vendor/lief/api/rust/crates/lief-ffigen/src/main.rs new file mode 100644 index 0000000..2455ae7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief-ffigen/src/main.rs @@ -0,0 +1,101 @@ +use clap::Parser; +use proc_macro2::TokenStream; +use std::fs; +use std::path::{Path, PathBuf}; + +#[derive(Parser, Debug)] +#[command(version, about, long_about = None)] +struct Args { + #[arg(short, long)] + output_dir: String, + + #[arg(long)] + source_dir: Option, +} + +fn should_skip(file: &Path) -> bool { + let filename = file.file_name().unwrap().to_str().unwrap(); + if filename == "mod.rs" || filename == "lib.rs" { + return true; + } + // Skip module-declaration files that have no #[cxx::bridge]. + if let Ok(text) = fs::read_to_string(file) { + if !text.contains("#[cxx::bridge]") { + return true; + } + } + false +} + +fn iter_dir(dir: &Path, recursive: bool) -> Vec { + fs::read_dir(dir) + .map(|entries| { + entries + .flatten() + .flat_map(|entry| { + let path = entry.path(); + if should_skip(&path) { + return vec![]; + } + if path.is_file() { + return vec![path]; + } + if path.is_dir() && recursive { + return iter_dir(&path, recursive); + } + vec![] + }) + .collect() + }) + .unwrap_or_default() +} + +fn file_to_ts(file: &Path) -> TokenStream { + match fs::read_to_string(file).unwrap().parse::() { + Ok(tokens) => tokens, + Err(e) => panic!("Failed to parse string to TokenStream: {}", e), + } +} + +fn main() -> miette::Result<()> { + let args = Args::parse(); + + let ffi_dir = args.source_dir.map(PathBuf::from).unwrap_or_else(|| { + PathBuf::from(env!("CARGO_MANIFEST_DIR")) + .parent() + .unwrap() + .join("lief-ffi") + }); + + let dst_root_dir = PathBuf::from(args.output_dir); + let ffi_src_dir = ffi_dir.join("src"); + let files = iter_dir(&ffi_src_dir, true); + let opt = cxx_gen::Opt::default(); + for f in files { + let code = cxx_gen::generate_header_and_cc(file_to_ts(&f), &opt).unwrap(); + let dir = f.parent().unwrap().strip_prefix(&ffi_src_dir).unwrap(); + let dst_dir = dst_root_dir.join(dir); + fs::create_dir_all(&dst_dir).unwrap(); + + let cpp = dst_dir.join( + f.with_extension("cpp") + .file_name() + .unwrap() + .to_str() + .unwrap(), + ); + + let header = dst_dir.join( + f.with_extension("hpp") + .file_name() + .unwrap() + .to_str() + .unwrap(), + ); + + fs::write(&header, code.header).unwrap(); + fs::write(&cpp, code.implementation).unwrap(); + } + + Ok(()) +} diff --git a/vendor/lief/api/rust/crates/lief/Cargo.toml b/vendor/lief/api/rust/crates/lief/Cargo.toml new file mode 100644 index 0000000..a3fc8ba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/Cargo.toml @@ -0,0 +1,35 @@ +[package] +name = "lief" +description = "Official Rust bindings for LIEF" +documentation = "https://lief.re/doc/stable/rust/lief/" +edition.workspace = true +version.workspace = true +authors.workspace = true +license.workspace = true +readme.workspace = true +homepage.workspace = true +keywords.workspace = true +repository.workspace = true +categories.workspace = true +rust-version.workspace = true + +[lib] +doctest = false + +[dependencies] +cxx = { workspace = true } +bitflags = { workspace = true } +num-traits = { workspace = true } +num-derive = { workspace = true } +num-bigint = { workspace = true } +lief-ffi = { workspace = true } + +[dev-dependencies] +tempfile = { workspace = true } + +[features] +default = ["rustls-tls"] +rustls-tls = ["lief-ffi/rustls-tls"] + +[lints.clippy] +needless_doctest_main = "allow" diff --git a/vendor/lief/api/rust/crates/lief/src/assembly.rs b/vendor/lief/api/rust/crates/lief/src/assembly.rs new file mode 100644 index 0000000..2a0244b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly.rs @@ -0,0 +1,43 @@ +//! Assembly/Disassembly Module +//! +//! ### Getting Started +//! +//! One can start disassembling code by using the different functions exposes in the +//! [`crate::generic::Binary`] trait: +//! +//! ``` +//! fn disassemble(target: &dyn lief::generic::Binary) { +//! for inst in target.disassemble_symbol("_entrypoint") { +//! println!("{}", inst); +//! } +//! } +//! ``` +//! +//! An instruction is represented by the enum: [`Instructions`] which implements the **trait** +//! [`Instruction`]. +//! +//! For architecture-dependant API, you can check the following structures: +//! +//! - [`aarch64::Instruction`] +//! - [`x86::Instruction`] +//! - [`arm::Instruction`] +//! - [`powerpc::Instruction`] +//! - [`riscv::Instruction`] +//! - [`mips::Instruction`] +//! - [`ebpf::Instruction`] + +pub mod aarch64; +pub mod arm; +pub mod config; +pub mod ebpf; +pub mod instruction; +pub mod mips; +pub mod powerpc; +pub mod riscv; +pub mod x86; + +#[doc(inline)] +pub use instruction::{Instruction, Instructions}; + +#[doc(inline)] +pub use config::AssemblerConfig; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64.rs new file mode 100644 index 0000000..e28b8ee --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64.rs @@ -0,0 +1,21 @@ +//! AArch64 architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use registers::{Reg, SysReg}; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/instruction.rs new file mode 100644 index 0000000..f10f6ec --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/instruction.rs @@ -0,0 +1,52 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +use crate::assembly::aarch64; +use crate::declare_fwd_iterator; + +/// This structure represents an AArch64 instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`aarch64::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } +} + +declare_fwd_iterator!( + Operands, + aarch64::Operands, + ffi::asm_Instruction, + ffi::asm_aarch64_Operand, + ffi::asm_aarch64_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/opcodes.rs new file mode 100644 index 0000000..7e63e0b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/opcodes.rs @@ -0,0 +1,18285 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ABS_ZPmZ_B_UNDEF, + ABS_ZPmZ_D_UNDEF, + ABS_ZPmZ_H_UNDEF, + ABS_ZPmZ_S_UNDEF, + ADDHA_MPPZ_D_PSEUDO_D, + ADDHA_MPPZ_S_PSEUDO_S, + ADDSWrr, + ADDSXrr, + ADDVA_MPPZ_D_PSEUDO_D, + ADDVA_MPPZ_S_PSEUDO_S, + ADDWrr, + ADDXrr, + ADD_VG2_M2Z2Z_D_PSEUDO, + ADD_VG2_M2Z2Z_S_PSEUDO, + ADD_VG2_M2ZZ_D_PSEUDO, + ADD_VG2_M2ZZ_S_PSEUDO, + ADD_VG2_M2Z_D_PSEUDO, + ADD_VG2_M2Z_S_PSEUDO, + ADD_VG4_M4Z4Z_D_PSEUDO, + ADD_VG4_M4Z4Z_S_PSEUDO, + ADD_VG4_M4ZZ_D_PSEUDO, + ADD_VG4_M4ZZ_S_PSEUDO, + ADD_VG4_M4Z_D_PSEUDO, + ADD_VG4_M4Z_S_PSEUDO, + ADD_ZPZZ_B_ZERO, + ADD_ZPZZ_D_ZERO, + ADD_ZPZZ_H_ZERO, + ADD_ZPZZ_S_ZERO, + ADDlowTLS, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + AESIMCrrTied, + AESMCrrTied, + ANDSWrr, + ANDSXrr, + ANDWrr, + ANDXrr, + AND_ZPZZ_B_ZERO, + AND_ZPZZ_D_ZERO, + AND_ZPZZ_H_ZERO, + AND_ZPZZ_S_ZERO, + ASRD_ZPZI_B_ZERO, + ASRD_ZPZI_D_ZERO, + ASRD_ZPZI_H_ZERO, + ASRD_ZPZI_S_ZERO, + ASR_ZPZI_B_UNDEF, + ASR_ZPZI_B_ZERO, + ASR_ZPZI_D_UNDEF, + ASR_ZPZI_D_ZERO, + ASR_ZPZI_H_UNDEF, + ASR_ZPZI_H_ZERO, + ASR_ZPZI_S_UNDEF, + ASR_ZPZI_S_ZERO, + ASR_ZPZZ_B_UNDEF, + ASR_ZPZZ_B_ZERO, + ASR_ZPZZ_D_UNDEF, + ASR_ZPZZ_D_ZERO, + ASR_ZPZZ_H_UNDEF, + ASR_ZPZZ_H_ZERO, + ASR_ZPZZ_S_UNDEF, + ASR_ZPZZ_S_ZERO, + AUTH_TCRETURN, + AUTH_TCRETURN_BTI, + AUTPAC, + AUTx16x17, + AUTxMxN, + AllocateSMESaveBuffer, + AllocateZABuffer, + BFADD_VG2_M2Z_H_PSEUDO, + BFADD_VG4_M4Z_H_PSEUDO, + BFADD_ZPZZ_UNDEF, + BFADD_ZPZZ_ZERO, + BFDOT_VG2_M2Z2Z_HtoS_PSEUDO, + BFDOT_VG2_M2ZZI_HtoS_PSEUDO, + BFDOT_VG2_M2ZZ_HtoS_PSEUDO, + BFDOT_VG4_M4Z4Z_HtoS_PSEUDO, + BFDOT_VG4_M4ZZI_HtoS_PSEUDO, + BFDOT_VG4_M4ZZ_HtoS_PSEUDO, + BFMAXNM_ZPZZ_UNDEF, + BFMAXNM_ZPZZ_ZERO, + BFMAX_ZPZZ_UNDEF, + BFMAX_ZPZZ_ZERO, + BFMINNM_ZPZZ_UNDEF, + BFMINNM_ZPZZ_ZERO, + BFMIN_ZPZZ_UNDEF, + BFMIN_ZPZZ_ZERO, + BFMLAL_MZZI_HtoS_PSEUDO, + BFMLAL_MZZ_HtoS_PSEUDO, + BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + BFMLAL_VG2_M2ZZI_HtoS_PSEUDO, + BFMLAL_VG2_M2ZZ_HtoS_PSEUDO, + BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + BFMLAL_VG4_M4ZZI_HtoS_PSEUDO, + BFMLAL_VG4_M4ZZ_HtoS_PSEUDO, + BFMLA_VG2_M2Z2Z_PSEUDO, + BFMLA_VG2_M2ZZI_PSEUDO, + BFMLA_VG2_M2ZZ_PSEUDO, + BFMLA_VG4_M4Z4Z_PSEUDO, + BFMLA_VG4_M4ZZI_PSEUDO, + BFMLA_VG4_M4ZZ_PSEUDO, + BFMLA_ZPZZZ_UNDEF, + BFMLSL_MZZI_HtoS_PSEUDO, + BFMLSL_MZZ_HtoS_PSEUDO, + BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + BFMLSL_VG2_M2ZZI_HtoS_PSEUDO, + BFMLSL_VG2_M2ZZ_HtoS_PSEUDO, + BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + BFMLSL_VG4_M4ZZI_HtoS_PSEUDO, + BFMLSL_VG4_M4ZZ_HtoS_PSEUDO, + BFMLS_VG2_M2Z2Z_PSEUDO, + BFMLS_VG2_M2ZZI_PSEUDO, + BFMLS_VG2_M2ZZ_PSEUDO, + BFMLS_VG4_M4Z4Z_PSEUDO, + BFMLS_VG4_M4ZZI_PSEUDO, + BFMLS_VG4_M4ZZ_PSEUDO, + BFMLS_ZPZZZ_UNDEF, + BFMOP4A_M2Z2Z_H_PSEUDO, + BFMOP4A_M2Z2Z_S_PSEUDO, + BFMOP4A_M2ZZ_H_PSEUDO, + BFMOP4A_M2ZZ_S_PSEUDO, + BFMOP4A_MZ2Z_H_PSEUDO, + BFMOP4A_MZ2Z_S_PSEUDO, + BFMOP4A_MZZ_H_PSEUDO, + BFMOP4A_MZZ_S_PSEUDO, + BFMOP4S_M2Z2Z_H_PSEUDO, + BFMOP4S_M2Z2Z_S_PSEUDO, + BFMOP4S_M2ZZ_H_PSEUDO, + BFMOP4S_M2ZZ_S_PSEUDO, + BFMOP4S_MZ2Z_H_PSEUDO, + BFMOP4S_MZ2Z_S_PSEUDO, + BFMOP4S_MZZ_H_PSEUDO, + BFMOP4S_MZZ_S_PSEUDO, + BFMOPA_MPPZZ_H_PSEUDO, + BFMOPA_MPPZZ_PSEUDO, + BFMOPS_MPPZZ_H_PSEUDO, + BFMOPS_MPPZZ_PSEUDO, + BFMUL_ZPZZ_UNDEF, + BFMUL_ZPZZ_ZERO, + BFSUB_VG2_M2Z_H_PSEUDO, + BFSUB_VG4_M4Z_H_PSEUDO, + BFSUB_ZPZZ_UNDEF, + BFSUB_ZPZZ_ZERO, + BFTMOPA_M2ZZZI_HtoH_PSEUDO, + BFTMOPA_M2ZZZI_HtoS_PSEUDO, + BFVDOT_VG2_M2ZZI_HtoS_PSEUDO, + BICSWrr, + BICSXrr, + BICWrr, + BICXrr, + BIC_ZPZZ_B_ZERO, + BIC_ZPZZ_D_ZERO, + BIC_ZPZZ_H_ZERO, + BIC_ZPZZ_S_ZERO, + BLRA, + BLRA_RVMARKER, + BLRNoIP, + BLR_BTI, + BLR_RVMARKER, + BLR_X16, + BMOPA_MPPZZ_S_PSEUDO, + BMOPS_MPPZZ_S_PSEUDO, + BRA, + BR_JumpTable, + BSPv16i8, + BSPv8i8, + CATCHRET, + CBBAssertExt, + CBHAssertExt, + CBWPri, + CBWPrr, + CBXPri, + CBXPrr, + CHECK_MATCHING_VL_PSEUDO, + CLEANUPRET, + CLS_ZPmZ_B_UNDEF, + CLS_ZPmZ_D_UNDEF, + CLS_ZPmZ_H_UNDEF, + CLS_ZPmZ_S_UNDEF, + CLZ_ZPmZ_B_UNDEF, + CLZ_ZPmZ_D_UNDEF, + CLZ_ZPmZ_H_UNDEF, + CLZ_ZPmZ_S_UNDEF, + CMP_SWAP_128, + CMP_SWAP_128_ACQUIRE, + CMP_SWAP_128_MONOTONIC, + CMP_SWAP_128_RELEASE, + CMP_SWAP_16, + CMP_SWAP_32, + CMP_SWAP_64, + CMP_SWAP_8, + CNOT_ZPmZ_B_UNDEF, + CNOT_ZPmZ_D_UNDEF, + CNOT_ZPmZ_H_UNDEF, + CNOT_ZPmZ_S_UNDEF, + CNT_ZPmZ_B_UNDEF, + CNT_ZPmZ_D_UNDEF, + CNT_ZPmZ_H_UNDEF, + CNT_ZPmZ_S_UNDEF, + COALESCER_BARRIER_FPR128, + COALESCER_BARRIER_FPR16, + COALESCER_BARRIER_FPR32, + COALESCER_BARRIER_FPR64, + CommitZASavePseudo, + EMITBKEY, + EMITMTETAGGED, + EONWrr, + EONXrr, + EORWrr, + EORXrr, + EOR_ZPZZ_B_ZERO, + EOR_ZPZZ_D_ZERO, + EOR_ZPZZ_H_ZERO, + EOR_ZPZZ_S_ZERO, + EXT_ZZI_CONSTRUCTIVE, + EntryPStateSM, + F128CSEL, + FABD_ZPZZ_D_UNDEF, + FABD_ZPZZ_D_ZERO, + FABD_ZPZZ_H_UNDEF, + FABD_ZPZZ_H_ZERO, + FABD_ZPZZ_S_UNDEF, + FABD_ZPZZ_S_ZERO, + FABS_ZPmZ_D_UNDEF, + FABS_ZPmZ_H_UNDEF, + FABS_ZPmZ_S_UNDEF, + FADD_VG2_M2Z_D_PSEUDO, + FADD_VG2_M2Z_H_PSEUDO, + FADD_VG2_M2Z_S_PSEUDO, + FADD_VG4_M4Z_D_PSEUDO, + FADD_VG4_M4Z_H_PSEUDO, + FADD_VG4_M4Z_S_PSEUDO, + FADD_ZPZI_D_UNDEF, + FADD_ZPZI_D_ZERO, + FADD_ZPZI_H_UNDEF, + FADD_ZPZI_H_ZERO, + FADD_ZPZI_S_UNDEF, + FADD_ZPZI_S_ZERO, + FADD_ZPZZ_D_UNDEF, + FADD_ZPZZ_D_ZERO, + FADD_ZPZZ_H_UNDEF, + FADD_ZPZZ_H_ZERO, + FADD_ZPZZ_S_UNDEF, + FADD_ZPZZ_S_ZERO, + FAMAX_ZPZZ_D_UNDEF, + FAMAX_ZPZZ_H_UNDEF, + FAMAX_ZPZZ_S_UNDEF, + FAMIN_ZPZZ_D_UNDEF, + FAMIN_ZPZZ_H_UNDEF, + FAMIN_ZPZZ_S_UNDEF, + FCVTZS_ZPmZ_DtoD_UNDEF, + FCVTZS_ZPmZ_DtoS_UNDEF, + FCVTZS_ZPmZ_HtoD_UNDEF, + FCVTZS_ZPmZ_HtoH_UNDEF, + FCVTZS_ZPmZ_HtoS_UNDEF, + FCVTZS_ZPmZ_StoD_UNDEF, + FCVTZS_ZPmZ_StoS_UNDEF, + FCVTZU_ZPmZ_DtoD_UNDEF, + FCVTZU_ZPmZ_DtoS_UNDEF, + FCVTZU_ZPmZ_HtoD_UNDEF, + FCVTZU_ZPmZ_HtoH_UNDEF, + FCVTZU_ZPmZ_HtoS_UNDEF, + FCVTZU_ZPmZ_StoD_UNDEF, + FCVTZU_ZPmZ_StoS_UNDEF, + FCVT_ZPmZ_DtoH_UNDEF, + FCVT_ZPmZ_DtoS_UNDEF, + FCVT_ZPmZ_HtoD_UNDEF, + FCVT_ZPmZ_HtoS_UNDEF, + FCVT_ZPmZ_StoD_UNDEF, + FCVT_ZPmZ_StoH_UNDEF, + FDIVR_ZPZZ_D_ZERO, + FDIVR_ZPZZ_H_ZERO, + FDIVR_ZPZZ_S_ZERO, + FDIV_ZPZZ_D_UNDEF, + FDIV_ZPZZ_D_ZERO, + FDIV_ZPZZ_H_UNDEF, + FDIV_ZPZZ_H_ZERO, + FDIV_ZPZZ_S_UNDEF, + FDIV_ZPZZ_S_ZERO, + FDOT_VG2_M2Z2Z_BtoH_PSEUDO, + FDOT_VG2_M2Z2Z_BtoS_PSEUDO, + FDOT_VG2_M2Z2Z_HtoS_PSEUDO, + FDOT_VG2_M2ZZI_BtoH_PSEUDO, + FDOT_VG2_M2ZZI_BtoS_PSEUDO, + FDOT_VG2_M2ZZI_HtoS_PSEUDO, + FDOT_VG2_M2ZZ_BtoH_PSEUDO, + FDOT_VG2_M2ZZ_BtoS_PSEUDO, + FDOT_VG2_M2ZZ_HtoS_PSEUDO, + FDOT_VG4_M4Z4Z_BtoH_PSEUDO, + FDOT_VG4_M4Z4Z_BtoS_PSEUDO, + FDOT_VG4_M4Z4Z_HtoS_PSEUDO, + FDOT_VG4_M4ZZI_BtoH_PSEUDO, + FDOT_VG4_M4ZZI_BtoS_PSEUDO, + FDOT_VG4_M4ZZI_HtoS_PSEUDO, + FDOT_VG4_M4ZZ_BtoH_PSEUDO, + FDOT_VG4_M4ZZ_BtoS_PSEUDO, + FDOT_VG4_M4ZZ_HtoS_PSEUDO, + FLOGB_ZPZZ_D_ZERO, + FLOGB_ZPZZ_H_ZERO, + FLOGB_ZPZZ_S_ZERO, + FMAXNM_ZPZI_D_UNDEF, + FMAXNM_ZPZI_D_ZERO, + FMAXNM_ZPZI_H_UNDEF, + FMAXNM_ZPZI_H_ZERO, + FMAXNM_ZPZI_S_UNDEF, + FMAXNM_ZPZI_S_ZERO, + FMAXNM_ZPZZ_D_UNDEF, + FMAXNM_ZPZZ_D_ZERO, + FMAXNM_ZPZZ_H_UNDEF, + FMAXNM_ZPZZ_H_ZERO, + FMAXNM_ZPZZ_S_UNDEF, + FMAXNM_ZPZZ_S_ZERO, + FMAX_ZPZI_D_UNDEF, + FMAX_ZPZI_D_ZERO, + FMAX_ZPZI_H_UNDEF, + FMAX_ZPZI_H_ZERO, + FMAX_ZPZI_S_UNDEF, + FMAX_ZPZI_S_ZERO, + FMAX_ZPZZ_D_UNDEF, + FMAX_ZPZZ_D_ZERO, + FMAX_ZPZZ_H_UNDEF, + FMAX_ZPZZ_H_ZERO, + FMAX_ZPZZ_S_UNDEF, + FMAX_ZPZZ_S_ZERO, + FMINNM_ZPZI_D_UNDEF, + FMINNM_ZPZI_D_ZERO, + FMINNM_ZPZI_H_UNDEF, + FMINNM_ZPZI_H_ZERO, + FMINNM_ZPZI_S_UNDEF, + FMINNM_ZPZI_S_ZERO, + FMINNM_ZPZZ_D_UNDEF, + FMINNM_ZPZZ_D_ZERO, + FMINNM_ZPZZ_H_UNDEF, + FMINNM_ZPZZ_H_ZERO, + FMINNM_ZPZZ_S_UNDEF, + FMINNM_ZPZZ_S_ZERO, + FMIN_ZPZI_D_UNDEF, + FMIN_ZPZI_D_ZERO, + FMIN_ZPZI_H_UNDEF, + FMIN_ZPZI_H_ZERO, + FMIN_ZPZI_S_UNDEF, + FMIN_ZPZI_S_ZERO, + FMIN_ZPZZ_D_UNDEF, + FMIN_ZPZZ_D_ZERO, + FMIN_ZPZZ_H_UNDEF, + FMIN_ZPZZ_H_ZERO, + FMIN_ZPZZ_S_UNDEF, + FMIN_ZPZZ_S_ZERO, + FMLALL_MZZI_BtoS_PSEUDO, + FMLALL_MZZ_BtoS_PSEUDO, + FMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + FMLALL_VG2_M2ZZI_BtoS_PSEUDO, + FMLALL_VG2_M2ZZ_BtoS_PSEUDO, + FMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + FMLALL_VG4_M4ZZI_BtoS_PSEUDO, + FMLALL_VG4_M4ZZ_BtoS_PSEUDO, + FMLAL_MZZI_BtoH_PSEUDO, + FMLAL_MZZI_HtoS_PSEUDO, + FMLAL_MZZ_HtoS_PSEUDO, + FMLAL_VG2_M2Z2Z_BtoH_PSEUDO, + FMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + FMLAL_VG2_M2ZZI_BtoH_PSEUDO, + FMLAL_VG2_M2ZZI_HtoS_PSEUDO, + FMLAL_VG2_M2ZZ_BtoH_PSEUDO, + FMLAL_VG2_M2ZZ_HtoS_PSEUDO, + FMLAL_VG2_MZZ_BtoH_PSEUDO, + FMLAL_VG4_M4Z4Z_BtoH_PSEUDO, + FMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + FMLAL_VG4_M4ZZI_BtoH_PSEUDO, + FMLAL_VG4_M4ZZI_HtoS_PSEUDO, + FMLAL_VG4_M4ZZ_BtoH_PSEUDO, + FMLAL_VG4_M4ZZ_HtoS_PSEUDO, + FMLA_VG2_M2Z2Z_D_PSEUDO, + FMLA_VG2_M2Z2Z_H_PSEUDO, + FMLA_VG2_M2Z2Z_S_PSEUDO, + FMLA_VG2_M2ZZI_D_PSEUDO, + FMLA_VG2_M2ZZI_H_PSEUDO, + FMLA_VG2_M2ZZI_S_PSEUDO, + FMLA_VG2_M2ZZ_D_PSEUDO, + FMLA_VG2_M2ZZ_H_PSEUDO, + FMLA_VG2_M2ZZ_S_PSEUDO, + FMLA_VG4_M4Z4Z_D_PSEUDO, + FMLA_VG4_M4Z4Z_H_PSEUDO, + FMLA_VG4_M4Z4Z_S_PSEUDO, + FMLA_VG4_M4ZZI_D_PSEUDO, + FMLA_VG4_M4ZZI_H_PSEUDO, + FMLA_VG4_M4ZZI_S_PSEUDO, + FMLA_VG4_M4ZZ_D_PSEUDO, + FMLA_VG4_M4ZZ_H_PSEUDO, + FMLA_VG4_M4ZZ_S_PSEUDO, + FMLA_ZPZZZ_D_UNDEF, + FMLA_ZPZZZ_H_UNDEF, + FMLA_ZPZZZ_S_UNDEF, + FMLSL_MZZI_HtoS_PSEUDO, + FMLSL_MZZ_HtoS_PSEUDO, + FMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + FMLSL_VG2_M2ZZI_HtoS_PSEUDO, + FMLSL_VG2_M2ZZ_HtoS_PSEUDO, + FMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + FMLSL_VG4_M4ZZI_HtoS_PSEUDO, + FMLSL_VG4_M4ZZ_HtoS_PSEUDO, + FMLS_VG2_M2Z2Z_D_PSEUDO, + FMLS_VG2_M2Z2Z_H_PSEUDO, + FMLS_VG2_M2Z2Z_S_PSEUDO, + FMLS_VG2_M2ZZI_D_PSEUDO, + FMLS_VG2_M2ZZI_H_PSEUDO, + FMLS_VG2_M2ZZI_S_PSEUDO, + FMLS_VG2_M2ZZ_D_PSEUDO, + FMLS_VG2_M2ZZ_H_PSEUDO, + FMLS_VG2_M2ZZ_S_PSEUDO, + FMLS_VG4_M4Z4Z_D_PSEUDO, + FMLS_VG4_M4Z4Z_H_PSEUDO, + FMLS_VG4_M4Z4Z_S_PSEUDO, + FMLS_VG4_M4ZZI_D_PSEUDO, + FMLS_VG4_M4ZZI_H_PSEUDO, + FMLS_VG4_M4ZZI_S_PSEUDO, + FMLS_VG4_M4ZZ_D_PSEUDO, + FMLS_VG4_M4ZZ_H_PSEUDO, + FMLS_VG4_M4ZZ_S_PSEUDO, + FMLS_ZPZZZ_D_UNDEF, + FMLS_ZPZZZ_H_UNDEF, + FMLS_ZPZZZ_S_UNDEF, + FMOP4A_M2Z2Z_BtoH_PSEUDO, + FMOP4A_M2Z2Z_BtoS_PSEUDO, + FMOP4A_M2Z2Z_D_PSEUDO, + FMOP4A_M2Z2Z_H_PSEUDO, + FMOP4A_M2Z2Z_HtoS_PSEUDO, + FMOP4A_M2Z2Z_S_PSEUDO, + FMOP4A_M2ZZ_BtoH_PSEUDO, + FMOP4A_M2ZZ_BtoS_PSEUDO, + FMOP4A_M2ZZ_D_PSEUDO, + FMOP4A_M2ZZ_H_PSEUDO, + FMOP4A_M2ZZ_HtoS_PSEUDO, + FMOP4A_M2ZZ_S_PSEUDO, + FMOP4A_MZ2Z_BtoH_PSEUDO, + FMOP4A_MZ2Z_BtoS_PSEUDO, + FMOP4A_MZ2Z_D_PSEUDO, + FMOP4A_MZ2Z_H_PSEUDO, + FMOP4A_MZ2Z_HtoS_PSEUDO, + FMOP4A_MZ2Z_S_PSEUDO, + FMOP4A_MZZ_BtoH_PSEUDO, + FMOP4A_MZZ_BtoS_PSEUDO, + FMOP4A_MZZ_D_PSEUDO, + FMOP4A_MZZ_H_PSEUDO, + FMOP4A_MZZ_HtoS_PSEUDO, + FMOP4A_MZZ_S_PSEUDO, + FMOP4S_M2Z2Z_D_PSEUDO, + FMOP4S_M2Z2Z_H_PSEUDO, + FMOP4S_M2Z2Z_HtoS_PSEUDO, + FMOP4S_M2Z2Z_S_PSEUDO, + FMOP4S_M2ZZ_D_PSEUDO, + FMOP4S_M2ZZ_H_PSEUDO, + FMOP4S_M2ZZ_HtoS_PSEUDO, + FMOP4S_M2ZZ_S_PSEUDO, + FMOP4S_MZ2Z_D_PSEUDO, + FMOP4S_MZ2Z_H_PSEUDO, + FMOP4S_MZ2Z_HtoS_PSEUDO, + FMOP4S_MZ2Z_S_PSEUDO, + FMOP4S_MZZ_D_PSEUDO, + FMOP4S_MZZ_H_PSEUDO, + FMOP4S_MZZ_HtoS_PSEUDO, + FMOP4S_MZZ_S_PSEUDO, + FMOPAL_MPPZZ_PSEUDO, + FMOPA_MPPZZ_BtoH_PSEUDO, + FMOPA_MPPZZ_BtoS_PSEUDO, + FMOPA_MPPZZ_D_PSEUDO, + FMOPA_MPPZZ_H_PSEUDO, + FMOPA_MPPZZ_S_PSEUDO, + FMOPSL_MPPZZ_PSEUDO, + FMOPS_MPPZZ_D_PSEUDO, + FMOPS_MPPZZ_H_PSEUDO, + FMOPS_MPPZZ_S_PSEUDO, + FMOVD0, + FMOVH0, + FMOVS0, + FMULX_ZPZZ_D_UNDEF, + FMULX_ZPZZ_D_ZERO, + FMULX_ZPZZ_H_UNDEF, + FMULX_ZPZZ_H_ZERO, + FMULX_ZPZZ_S_UNDEF, + FMULX_ZPZZ_S_ZERO, + FMUL_ZPZI_D_UNDEF, + FMUL_ZPZI_D_ZERO, + FMUL_ZPZI_H_UNDEF, + FMUL_ZPZI_H_ZERO, + FMUL_ZPZI_S_UNDEF, + FMUL_ZPZI_S_ZERO, + FMUL_ZPZZ_D_UNDEF, + FMUL_ZPZZ_D_ZERO, + FMUL_ZPZZ_H_UNDEF, + FMUL_ZPZZ_H_ZERO, + FMUL_ZPZZ_S_UNDEF, + FMUL_ZPZZ_S_ZERO, + FNEG_ZPmZ_D_UNDEF, + FNEG_ZPmZ_H_UNDEF, + FNEG_ZPmZ_S_UNDEF, + FNMLA_ZPZZZ_D_UNDEF, + FNMLA_ZPZZZ_H_UNDEF, + FNMLA_ZPZZZ_S_UNDEF, + FNMLS_ZPZZZ_D_UNDEF, + FNMLS_ZPZZZ_H_UNDEF, + FNMLS_ZPZZZ_S_UNDEF, + FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO, + FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO, + FRECPX_ZPmZ_D_UNDEF, + FRECPX_ZPmZ_H_UNDEF, + FRECPX_ZPmZ_S_UNDEF, + FRINT32X_ZPmZ_D_UNDEF, + FRINT32X_ZPmZ_S_UNDEF, + FRINT32Z_ZPmZ_D_UNDEF, + FRINT32Z_ZPmZ_S_UNDEF, + FRINT64X_ZPmZ_D_UNDEF, + FRINT64X_ZPmZ_S_UNDEF, + FRINT64Z_ZPmZ_D_UNDEF, + FRINT64Z_ZPmZ_S_UNDEF, + FRINTA_ZPmZ_D_UNDEF, + FRINTA_ZPmZ_H_UNDEF, + FRINTA_ZPmZ_S_UNDEF, + FRINTI_ZPmZ_D_UNDEF, + FRINTI_ZPmZ_H_UNDEF, + FRINTI_ZPmZ_S_UNDEF, + FRINTM_ZPmZ_D_UNDEF, + FRINTM_ZPmZ_H_UNDEF, + FRINTM_ZPmZ_S_UNDEF, + FRINTN_ZPmZ_D_UNDEF, + FRINTN_ZPmZ_H_UNDEF, + FRINTN_ZPmZ_S_UNDEF, + FRINTP_ZPmZ_D_UNDEF, + FRINTP_ZPmZ_H_UNDEF, + FRINTP_ZPmZ_S_UNDEF, + FRINTX_ZPmZ_D_UNDEF, + FRINTX_ZPmZ_H_UNDEF, + FRINTX_ZPmZ_S_UNDEF, + FRINTZ_ZPmZ_D_UNDEF, + FRINTZ_ZPmZ_H_UNDEF, + FRINTZ_ZPmZ_S_UNDEF, + FSQRT_ZPmZ_D_UNDEF, + FSQRT_ZPmZ_H_UNDEF, + FSQRT_ZPmZ_S_UNDEF, + FSUBR_ZPZI_D_UNDEF, + FSUBR_ZPZI_D_ZERO, + FSUBR_ZPZI_H_UNDEF, + FSUBR_ZPZI_H_ZERO, + FSUBR_ZPZI_S_UNDEF, + FSUBR_ZPZI_S_ZERO, + FSUBR_ZPZZ_D_ZERO, + FSUBR_ZPZZ_H_ZERO, + FSUBR_ZPZZ_S_ZERO, + FSUB_VG2_M2Z_D_PSEUDO, + FSUB_VG2_M2Z_H_PSEUDO, + FSUB_VG2_M2Z_S_PSEUDO, + FSUB_VG4_M4Z_D_PSEUDO, + FSUB_VG4_M4Z_H_PSEUDO, + FSUB_VG4_M4Z_S_PSEUDO, + FSUB_ZPZI_D_UNDEF, + FSUB_ZPZI_D_ZERO, + FSUB_ZPZI_H_UNDEF, + FSUB_ZPZI_H_ZERO, + FSUB_ZPZI_S_UNDEF, + FSUB_ZPZI_S_ZERO, + FSUB_ZPZZ_D_UNDEF, + FSUB_ZPZZ_D_ZERO, + FSUB_ZPZZ_H_UNDEF, + FSUB_ZPZZ_H_ZERO, + FSUB_ZPZZ_S_UNDEF, + FSUB_ZPZZ_S_ZERO, + FTMOPA_M2ZZZI_BtoH_PSEUDO, + FTMOPA_M2ZZZI_BtoS_PSEUDO, + FTMOPA_M2ZZZI_HtoH_PSEUDO, + FTMOPA_M2ZZZI_HtoS_PSEUDO, + FTMOPA_M2ZZZI_StoS_PSEUDO, + FVDOTB_VG4_M2ZZI_BtoS_PSEUDO, + FVDOTT_VG4_M2ZZI_BtoS_PSEUDO, + FVDOT_VG2_M2ZZI_BtoH_PSEUDO, + FVDOT_VG2_M2ZZI_HtoS_PSEUDO, + G_AARCH64_PREFETCH, + G_AARCH64_RANGE_PREFETCH, + G_ADD_LOW, + G_BSP, + G_DUP, + G_DUPLANE16, + G_DUPLANE32, + G_DUPLANE64, + G_DUPLANE8, + G_EXT, + G_FCMEQ, + G_FCMGE, + G_FCMGT, + G_FPTRUNC_ODD, + G_PMULL, + G_REV16, + G_REV32, + G_REV64, + G_SADDLP, + G_SADDLV, + G_SDOT, + G_SITOF, + G_SLI, + G_SMULL, + G_SQSHLU_I, + G_SRI, + G_SRSHR_I, + G_TRN1, + G_TRN2, + G_UADDLP, + G_UADDLV, + G_UDOT, + G_UITOF, + G_UMULL, + G_URSHR_I, + G_USDOT, + G_UZP1, + G_UZP2, + G_VASHR, + G_VLSHR, + G_ZIP1, + G_ZIP2, + GetSMESaveSize, + HOM_Epilog, + HOM_Prolog, + HWASAN_CHECK_MEMACCESS, + HWASAN_CHECK_MEMACCESS_FIXEDSHADOW, + HWASAN_CHECK_MEMACCESS_SHORTGRANULES, + HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW, + INSERT_MXIPZ_H_PSEUDO_B, + INSERT_MXIPZ_H_PSEUDO_D, + INSERT_MXIPZ_H_PSEUDO_H, + INSERT_MXIPZ_H_PSEUDO_Q, + INSERT_MXIPZ_H_PSEUDO_S, + INSERT_MXIPZ_V_PSEUDO_B, + INSERT_MXIPZ_V_PSEUDO_D, + INSERT_MXIPZ_V_PSEUDO_H, + INSERT_MXIPZ_V_PSEUDO_Q, + INSERT_MXIPZ_V_PSEUDO_S, + IRGstack, + InOutZAUsePseudo, + InitTPIDR2Obj, + JumpTableDest16, + JumpTableDest32, + JumpTableDest8, + KCFI_CHECK, + LD1B_2Z_IMM_PSEUDO, + LD1B_2Z_PSEUDO, + LD1B_4Z_IMM_PSEUDO, + LD1B_4Z_PSEUDO, + LD1D_2Z_IMM_PSEUDO, + LD1D_2Z_PSEUDO, + LD1D_4Z_IMM_PSEUDO, + LD1D_4Z_PSEUDO, + LD1H_2Z_IMM_PSEUDO, + LD1H_2Z_PSEUDO, + LD1H_4Z_IMM_PSEUDO, + LD1H_4Z_PSEUDO, + LD1W_2Z_IMM_PSEUDO, + LD1W_2Z_PSEUDO, + LD1W_4Z_IMM_PSEUDO, + LD1W_4Z_PSEUDO, + LD1_MXIPXX_H_PSEUDO_B, + LD1_MXIPXX_H_PSEUDO_D, + LD1_MXIPXX_H_PSEUDO_H, + LD1_MXIPXX_H_PSEUDO_Q, + LD1_MXIPXX_H_PSEUDO_S, + LD1_MXIPXX_V_PSEUDO_B, + LD1_MXIPXX_V_PSEUDO_D, + LD1_MXIPXX_V_PSEUDO_H, + LD1_MXIPXX_V_PSEUDO_Q, + LD1_MXIPXX_V_PSEUDO_S, + LDNT1B_2Z_IMM_PSEUDO, + LDNT1B_2Z_PSEUDO, + LDNT1B_4Z_IMM_PSEUDO, + LDNT1B_4Z_PSEUDO, + LDNT1D_2Z_IMM_PSEUDO, + LDNT1D_2Z_PSEUDO, + LDNT1D_4Z_IMM_PSEUDO, + LDNT1D_4Z_PSEUDO, + LDNT1H_2Z_IMM_PSEUDO, + LDNT1H_2Z_PSEUDO, + LDNT1H_4Z_IMM_PSEUDO, + LDNT1H_4Z_PSEUDO, + LDNT1W_2Z_IMM_PSEUDO, + LDNT1W_2Z_PSEUDO, + LDNT1W_4Z_IMM_PSEUDO, + LDNT1W_4Z_PSEUDO, + LDR_PPXI, + LDR_TX_PSEUDO, + LDR_ZA_PSEUDO, + LDR_ZZXI, + LDR_ZZXI_STRIDED_CONTIGUOUS, + LDR_ZZZXI, + LDR_ZZZZXI, + LDR_ZZZZXI_STRIDED_CONTIGUOUS, + LOADauthptrstatic, + LOADgot, + LOADgotAUTH, + LOADgotPAC, + LSL_ZPZI_B_UNDEF, + LSL_ZPZI_B_ZERO, + LSL_ZPZI_D_UNDEF, + LSL_ZPZI_D_ZERO, + LSL_ZPZI_H_UNDEF, + LSL_ZPZI_H_ZERO, + LSL_ZPZI_S_UNDEF, + LSL_ZPZI_S_ZERO, + LSL_ZPZZ_B_UNDEF, + LSL_ZPZZ_B_ZERO, + LSL_ZPZZ_D_UNDEF, + LSL_ZPZZ_D_ZERO, + LSL_ZPZZ_H_UNDEF, + LSL_ZPZZ_H_ZERO, + LSL_ZPZZ_S_UNDEF, + LSL_ZPZZ_S_ZERO, + LSR_ZPZI_B_UNDEF, + LSR_ZPZI_B_ZERO, + LSR_ZPZI_D_UNDEF, + LSR_ZPZI_D_ZERO, + LSR_ZPZI_H_UNDEF, + LSR_ZPZI_H_ZERO, + LSR_ZPZI_S_UNDEF, + LSR_ZPZI_S_ZERO, + LSR_ZPZZ_B_UNDEF, + LSR_ZPZZ_B_ZERO, + LSR_ZPZZ_D_UNDEF, + LSR_ZPZZ_D_ZERO, + LSR_ZPZZ_H_UNDEF, + LSR_ZPZZ_H_ZERO, + LSR_ZPZZ_S_UNDEF, + LSR_ZPZZ_S_ZERO, + MLA_ZPZZZ_B_UNDEF, + MLA_ZPZZZ_D_UNDEF, + MLA_ZPZZZ_H_UNDEF, + MLA_ZPZZZ_S_UNDEF, + MLS_ZPZZZ_B_UNDEF, + MLS_ZPZZZ_D_UNDEF, + MLS_ZPZZZ_H_UNDEF, + MLS_ZPZZZ_S_UNDEF, + MOPSMemoryCopyPseudo, + MOPSMemoryMovePseudo, + MOPSMemorySetPseudo, + MOPSMemorySetTaggingPseudo, + MOVAZ_2ZMI_H_B_PSEUDO, + MOVAZ_2ZMI_H_D_PSEUDO, + MOVAZ_2ZMI_H_H_PSEUDO, + MOVAZ_2ZMI_H_S_PSEUDO, + MOVAZ_2ZMI_V_B_PSEUDO, + MOVAZ_2ZMI_V_D_PSEUDO, + MOVAZ_2ZMI_V_H_PSEUDO, + MOVAZ_2ZMI_V_S_PSEUDO, + MOVAZ_4ZMI_H_B_PSEUDO, + MOVAZ_4ZMI_H_D_PSEUDO, + MOVAZ_4ZMI_H_H_PSEUDO, + MOVAZ_4ZMI_H_S_PSEUDO, + MOVAZ_4ZMI_V_B_PSEUDO, + MOVAZ_4ZMI_V_D_PSEUDO, + MOVAZ_4ZMI_V_H_PSEUDO, + MOVAZ_4ZMI_V_S_PSEUDO, + MOVAZ_VG2_2ZMXI_PSEUDO, + MOVAZ_VG4_4ZMXI_PSEUDO, + MOVAZ_ZMI_H_B_PSEUDO, + MOVAZ_ZMI_H_D_PSEUDO, + MOVAZ_ZMI_H_H_PSEUDO, + MOVAZ_ZMI_H_Q_PSEUDO, + MOVAZ_ZMI_H_S_PSEUDO, + MOVAZ_ZMI_V_B_PSEUDO, + MOVAZ_ZMI_V_D_PSEUDO, + MOVAZ_ZMI_V_H_PSEUDO, + MOVAZ_ZMI_V_Q_PSEUDO, + MOVAZ_ZMI_V_S_PSEUDO, + MOVA_MXI2Z_H_B_PSEUDO, + MOVA_MXI2Z_H_D_PSEUDO, + MOVA_MXI2Z_H_H_PSEUDO, + MOVA_MXI2Z_H_S_PSEUDO, + MOVA_MXI2Z_V_B_PSEUDO, + MOVA_MXI2Z_V_D_PSEUDO, + MOVA_MXI2Z_V_H_PSEUDO, + MOVA_MXI2Z_V_S_PSEUDO, + MOVA_MXI4Z_H_B_PSEUDO, + MOVA_MXI4Z_H_D_PSEUDO, + MOVA_MXI4Z_H_H_PSEUDO, + MOVA_MXI4Z_H_S_PSEUDO, + MOVA_MXI4Z_V_B_PSEUDO, + MOVA_MXI4Z_V_D_PSEUDO, + MOVA_MXI4Z_V_H_PSEUDO, + MOVA_MXI4Z_V_S_PSEUDO, + MOVA_VG2_MXI2Z_PSEUDO, + MOVA_VG4_MXI4Z_PSEUDO, + MOVMCSym, + MOVT_TIZ_PSEUDO, + MOVaddr, + MOVaddrBA, + MOVaddrCP, + MOVaddrEXT, + MOVaddrJT, + MOVaddrPAC, + MOVaddrTLS, + MOVbaseTLS, + MOVi32imm, + MOVi64imm, + MRS_FPCR, + MRS_FPSR, + MSR_FPCR, + MSR_FPMR, + MSR_FPSR, + MSRpstatePseudo, + MUL_ZPZZ_B_UNDEF, + MUL_ZPZZ_D_UNDEF, + MUL_ZPZZ_H_UNDEF, + MUL_ZPZZ_S_UNDEF, + NEG_ZPmZ_B_UNDEF, + NEG_ZPmZ_D_UNDEF, + NEG_ZPmZ_H_UNDEF, + NEG_ZPmZ_S_UNDEF, + NOT_ZPmZ_B_UNDEF, + NOT_ZPmZ_D_UNDEF, + NOT_ZPmZ_H_UNDEF, + NOT_ZPmZ_S_UNDEF, + ORNWrr, + ORNXrr, + ORRWrr, + ORRXrr, + ORR_ZPZZ_B_ZERO, + ORR_ZPZZ_D_ZERO, + ORR_ZPZZ_H_ZERO, + ORR_ZPZZ_S_ZERO, + PAC, + PAUTH_EPILOGUE, + PAUTH_PROLOGUE, + PROBED_STACKALLOC, + PROBED_STACKALLOC_DYN, + PROBED_STACKALLOC_VAR, + PTEST_PP_ANY, + PTEST_PP_FIRST, + RET_ReallyLR, + RequiresZASavePseudo, + RequiresZT0SavePseudo, + RestoreZAPseudo, + SABD_ZPZZ_B_UNDEF, + SABD_ZPZZ_D_UNDEF, + SABD_ZPZZ_H_UNDEF, + SABD_ZPZZ_S_UNDEF, + SCVTF_ZPmZ_DtoD_UNDEF, + SCVTF_ZPmZ_DtoH_UNDEF, + SCVTF_ZPmZ_DtoS_UNDEF, + SCVTF_ZPmZ_HtoH_UNDEF, + SCVTF_ZPmZ_StoD_UNDEF, + SCVTF_ZPmZ_StoH_UNDEF, + SCVTF_ZPmZ_StoS_UNDEF, + SDIV_ZPZZ_D_UNDEF, + SDIV_ZPZZ_S_UNDEF, + SDOT_VG2_M2Z2Z_BtoS_PSEUDO, + SDOT_VG2_M2Z2Z_HtoD_PSEUDO, + SDOT_VG2_M2Z2Z_HtoS_PSEUDO, + SDOT_VG2_M2ZZI_BToS_PSEUDO, + SDOT_VG2_M2ZZI_HToS_PSEUDO, + SDOT_VG2_M2ZZI_HtoD_PSEUDO, + SDOT_VG2_M2ZZ_BtoS_PSEUDO, + SDOT_VG2_M2ZZ_HtoD_PSEUDO, + SDOT_VG2_M2ZZ_HtoS_PSEUDO, + SDOT_VG4_M4Z4Z_BtoS_PSEUDO, + SDOT_VG4_M4Z4Z_HtoD_PSEUDO, + SDOT_VG4_M4Z4Z_HtoS_PSEUDO, + SDOT_VG4_M4ZZI_BToS_PSEUDO, + SDOT_VG4_M4ZZI_HToS_PSEUDO, + SDOT_VG4_M4ZZI_HtoD_PSEUDO, + SDOT_VG4_M4ZZ_BtoS_PSEUDO, + SDOT_VG4_M4ZZ_HtoD_PSEUDO, + SDOT_VG4_M4ZZ_HtoS_PSEUDO, + SEH_AddFP, + SEH_AllocZ, + SEH_EpilogEnd, + SEH_EpilogStart, + SEH_Nop, + SEH_PACSignLR, + SEH_PrologEnd, + SEH_SaveAnyRegI, + SEH_SaveAnyRegIP, + SEH_SaveAnyRegQP, + SEH_SaveAnyRegQPX, + SEH_SaveFPLR, + SEH_SaveFPLR_X, + SEH_SaveFReg, + SEH_SaveFRegP, + SEH_SaveFRegP_X, + SEH_SaveFReg_X, + SEH_SavePReg, + SEH_SaveReg, + SEH_SaveRegP, + SEH_SaveRegP_X, + SEH_SaveReg_X, + SEH_SaveZReg, + SEH_SetFP, + SEH_StackAlloc, + SHSUB_ZPZZ_B_UNDEF, + SHSUB_ZPZZ_D_UNDEF, + SHSUB_ZPZZ_H_UNDEF, + SHSUB_ZPZZ_S_UNDEF, + SMAX_ZPZZ_B_UNDEF, + SMAX_ZPZZ_D_UNDEF, + SMAX_ZPZZ_H_UNDEF, + SMAX_ZPZZ_S_UNDEF, + SMEStateAllocPseudo, + SMIN_ZPZZ_B_UNDEF, + SMIN_ZPZZ_D_UNDEF, + SMIN_ZPZZ_H_UNDEF, + SMIN_ZPZZ_S_UNDEF, + SMLALL_MZZI_BtoS_PSEUDO, + SMLALL_MZZI_HtoD_PSEUDO, + SMLALL_MZZ_BtoS_PSEUDO, + SMLALL_MZZ_HtoD_PSEUDO, + SMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + SMLALL_VG2_M2Z2Z_HtoD_PSEUDO, + SMLALL_VG2_M2ZZI_BtoS_PSEUDO, + SMLALL_VG2_M2ZZI_HtoD_PSEUDO, + SMLALL_VG2_M2ZZ_BtoS_PSEUDO, + SMLALL_VG2_M2ZZ_HtoD_PSEUDO, + SMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + SMLALL_VG4_M4Z4Z_HtoD_PSEUDO, + SMLALL_VG4_M4ZZI_BtoS_PSEUDO, + SMLALL_VG4_M4ZZI_HtoD_PSEUDO, + SMLALL_VG4_M4ZZ_BtoS_PSEUDO, + SMLALL_VG4_M4ZZ_HtoD_PSEUDO, + SMLAL_MZZI_HtoS_PSEUDO, + SMLAL_MZZ_HtoS_PSEUDO, + SMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + SMLAL_VG2_M2ZZI_S_PSEUDO, + SMLAL_VG2_M2ZZ_HtoS_PSEUDO, + SMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + SMLAL_VG4_M4ZZI_HtoS_PSEUDO, + SMLAL_VG4_M4ZZ_HtoS_PSEUDO, + SMLSLL_MZZI_BtoS_PSEUDO, + SMLSLL_MZZI_HtoD_PSEUDO, + SMLSLL_MZZ_BtoS_PSEUDO, + SMLSLL_MZZ_HtoD_PSEUDO, + SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO, + SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO, + SMLSLL_VG2_M2ZZI_BtoS_PSEUDO, + SMLSLL_VG2_M2ZZI_HtoD_PSEUDO, + SMLSLL_VG2_M2ZZ_BtoS_PSEUDO, + SMLSLL_VG2_M2ZZ_HtoD_PSEUDO, + SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO, + SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO, + SMLSLL_VG4_M4ZZI_BtoS_PSEUDO, + SMLSLL_VG4_M4ZZI_HtoD_PSEUDO, + SMLSLL_VG4_M4ZZ_BtoS_PSEUDO, + SMLSLL_VG4_M4ZZ_HtoD_PSEUDO, + SMLSL_MZZI_HtoS_PSEUDO, + SMLSL_MZZ_HtoS_PSEUDO, + SMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + SMLSL_VG2_M2ZZI_S_PSEUDO, + SMLSL_VG2_M2ZZ_HtoS_PSEUDO, + SMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + SMLSL_VG4_M4ZZI_HtoS_PSEUDO, + SMLSL_VG4_M4ZZ_HtoS_PSEUDO, + SMOP4A_M2Z2Z_BToS_PSEUDO, + SMOP4A_M2Z2Z_HToS_PSEUDO, + SMOP4A_M2Z2Z_HtoD_PSEUDO, + SMOP4A_M2ZZ_BToS_PSEUDO, + SMOP4A_M2ZZ_HToS_PSEUDO, + SMOP4A_M2ZZ_HtoD_PSEUDO, + SMOP4A_MZ2Z_BToS_PSEUDO, + SMOP4A_MZ2Z_HToS_PSEUDO, + SMOP4A_MZ2Z_HtoD_PSEUDO, + SMOP4A_MZZ_BToS_PSEUDO, + SMOP4A_MZZ_HToS_PSEUDO, + SMOP4A_MZZ_HtoD_PSEUDO, + SMOP4S_M2Z2Z_BToS_PSEUDO, + SMOP4S_M2Z2Z_HToS_PSEUDO, + SMOP4S_M2Z2Z_HtoD_PSEUDO, + SMOP4S_M2ZZ_BToS_PSEUDO, + SMOP4S_M2ZZ_HToS_PSEUDO, + SMOP4S_M2ZZ_HtoD_PSEUDO, + SMOP4S_MZ2Z_BToS_PSEUDO, + SMOP4S_MZ2Z_HToS_PSEUDO, + SMOP4S_MZ2Z_HtoD_PSEUDO, + SMOP4S_MZZ_BToS_PSEUDO, + SMOP4S_MZZ_HToS_PSEUDO, + SMOP4S_MZZ_HtoD_PSEUDO, + SMOPA_MPPZZ_D_PSEUDO, + SMOPA_MPPZZ_HtoS_PSEUDO, + SMOPA_MPPZZ_S_PSEUDO, + SMOPS_MPPZZ_D_PSEUDO, + SMOPS_MPPZZ_HtoS_PSEUDO, + SMOPS_MPPZZ_S_PSEUDO, + SMULH_ZPZZ_B_UNDEF, + SMULH_ZPZZ_D_UNDEF, + SMULH_ZPZZ_H_UNDEF, + SMULH_ZPZZ_S_UNDEF, + SPACE, + SQABS_ZPmZ_B_UNDEF, + SQABS_ZPmZ_D_UNDEF, + SQABS_ZPmZ_H_UNDEF, + SQABS_ZPmZ_S_UNDEF, + SQNEG_ZPmZ_B_UNDEF, + SQNEG_ZPmZ_D_UNDEF, + SQNEG_ZPmZ_H_UNDEF, + SQNEG_ZPmZ_S_UNDEF, + SQRSHL_ZPZZ_B_UNDEF, + SQRSHL_ZPZZ_D_UNDEF, + SQRSHL_ZPZZ_H_UNDEF, + SQRSHL_ZPZZ_S_UNDEF, + SQSHLU_ZPZI_B_ZERO, + SQSHLU_ZPZI_D_ZERO, + SQSHLU_ZPZI_H_ZERO, + SQSHLU_ZPZI_S_ZERO, + SQSHL_ZPZI_B_UNDEF, + SQSHL_ZPZI_B_ZERO, + SQSHL_ZPZI_D_UNDEF, + SQSHL_ZPZI_D_ZERO, + SQSHL_ZPZI_H_UNDEF, + SQSHL_ZPZI_H_ZERO, + SQSHL_ZPZI_S_UNDEF, + SQSHL_ZPZI_S_ZERO, + SQSHL_ZPZZ_B_UNDEF, + SQSHL_ZPZZ_D_UNDEF, + SQSHL_ZPZZ_H_UNDEF, + SQSHL_ZPZZ_S_UNDEF, + SRSHL_ZPZZ_B_UNDEF, + SRSHL_ZPZZ_D_UNDEF, + SRSHL_ZPZZ_H_UNDEF, + SRSHL_ZPZZ_S_UNDEF, + SRSHR_ZPZI_B_ZERO, + SRSHR_ZPZI_D_ZERO, + SRSHR_ZPZI_H_ZERO, + SRSHR_ZPZI_S_ZERO, + STGloop, + STGloop_wback, + STMOPA_M2ZZZI_BtoS_PSEUDO, + STMOPA_M2ZZZI_HtoS_PSEUDO, + STR_PPXI, + STR_TX_PSEUDO, + STR_ZZXI, + STR_ZZXI_STRIDED_CONTIGUOUS, + STR_ZZZXI, + STR_ZZZZXI, + STR_ZZZZXI_STRIDED_CONTIGUOUS, + STZGloop, + STZGloop_wback, + SUBR_ZPZZ_B_ZERO, + SUBR_ZPZZ_D_ZERO, + SUBR_ZPZZ_H_ZERO, + SUBR_ZPZZ_S_ZERO, + SUBSWrr, + SUBSXrr, + SUBWrr, + SUBXrr, + SUB_VG2_M2Z2Z_D_PSEUDO, + SUB_VG2_M2Z2Z_S_PSEUDO, + SUB_VG2_M2ZZ_D_PSEUDO, + SUB_VG2_M2ZZ_S_PSEUDO, + SUB_VG2_M2Z_D_PSEUDO, + SUB_VG2_M2Z_S_PSEUDO, + SUB_VG4_M4Z4Z_D_PSEUDO, + SUB_VG4_M4Z4Z_S_PSEUDO, + SUB_VG4_M4ZZ_D_PSEUDO, + SUB_VG4_M4ZZ_S_PSEUDO, + SUB_VG4_M4Z_D_PSEUDO, + SUB_VG4_M4Z_S_PSEUDO, + SUB_ZPZZ_B_ZERO, + SUB_ZPZZ_D_ZERO, + SUB_ZPZZ_H_ZERO, + SUB_ZPZZ_S_ZERO, + SUDOT_VG2_M2ZZI_BToS_PSEUDO, + SUDOT_VG2_M2ZZ_BToS_PSEUDO, + SUDOT_VG4_M4ZZI_BToS_PSEUDO, + SUDOT_VG4_M4ZZ_BToS_PSEUDO, + SUMLALL_MZZI_BtoS_PSEUDO, + SUMLALL_VG2_M2ZZI_BtoS_PSEUDO, + SUMLALL_VG2_M2ZZ_BtoS_PSEUDO, + SUMLALL_VG4_M4ZZI_BtoS_PSEUDO, + SUMLALL_VG4_M4ZZ_BtoS_PSEUDO, + SUMOP4A_M2Z2Z_BToS_PSEUDO, + SUMOP4A_M2Z2Z_HtoD_PSEUDO, + SUMOP4A_M2ZZ_BToS_PSEUDO, + SUMOP4A_M2ZZ_HtoD_PSEUDO, + SUMOP4A_MZ2Z_BToS_PSEUDO, + SUMOP4A_MZ2Z_HtoD_PSEUDO, + SUMOP4A_MZZ_BToS_PSEUDO, + SUMOP4A_MZZ_HtoD_PSEUDO, + SUMOP4S_M2Z2Z_BToS_PSEUDO, + SUMOP4S_M2Z2Z_HtoD_PSEUDO, + SUMOP4S_M2ZZ_BToS_PSEUDO, + SUMOP4S_M2ZZ_HtoD_PSEUDO, + SUMOP4S_MZ2Z_BToS_PSEUDO, + SUMOP4S_MZ2Z_HtoD_PSEUDO, + SUMOP4S_MZZ_BToS_PSEUDO, + SUMOP4S_MZZ_HtoD_PSEUDO, + SUMOPA_MPPZZ_D_PSEUDO, + SUMOPA_MPPZZ_S_PSEUDO, + SUMOPS_MPPZZ_D_PSEUDO, + SUMOPS_MPPZZ_S_PSEUDO, + SUTMOPA_M2ZZZI_BtoS_PSEUDO, + SUVDOT_VG4_M4ZZI_BToS_PSEUDO, + SVDOT_VG2_M2ZZI_HtoS_PSEUDO, + SVDOT_VG4_M4ZZI_BtoS_PSEUDO, + SVDOT_VG4_M4ZZI_HtoD_PSEUDO, + SXTB_ZPmZ_D_UNDEF, + SXTB_ZPmZ_H_UNDEF, + SXTB_ZPmZ_S_UNDEF, + SXTH_ZPmZ_D_UNDEF, + SXTH_ZPmZ_S_UNDEF, + SXTW_ZPmZ_D_UNDEF, + SpeculationBarrierISBDSBEndBB, + SpeculationBarrierSBEndBB, + SpeculationSafeValueW, + SpeculationSafeValueX, + StoreSwiftAsyncContext, + TAGPstack, + TCRETURNdi, + TCRETURNri, + TCRETURNriALL, + TCRETURNrinotx16, + TCRETURNrix16x17, + TCRETURNrix17, + TLSDESCCALL, + TLSDESC_AUTH_CALLSEQ, + TLSDESC_CALLSEQ, + UABD_ZPZZ_B_UNDEF, + UABD_ZPZZ_D_UNDEF, + UABD_ZPZZ_H_UNDEF, + UABD_ZPZZ_S_UNDEF, + UCVTF_ZPmZ_DtoD_UNDEF, + UCVTF_ZPmZ_DtoH_UNDEF, + UCVTF_ZPmZ_DtoS_UNDEF, + UCVTF_ZPmZ_HtoH_UNDEF, + UCVTF_ZPmZ_StoD_UNDEF, + UCVTF_ZPmZ_StoH_UNDEF, + UCVTF_ZPmZ_StoS_UNDEF, + UDIV_ZPZZ_D_UNDEF, + UDIV_ZPZZ_S_UNDEF, + UDOT_VG2_M2Z2Z_BtoS_PSEUDO, + UDOT_VG2_M2Z2Z_HtoD_PSEUDO, + UDOT_VG2_M2Z2Z_HtoS_PSEUDO, + UDOT_VG2_M2ZZI_BToS_PSEUDO, + UDOT_VG2_M2ZZI_HToS_PSEUDO, + UDOT_VG2_M2ZZI_HtoD_PSEUDO, + UDOT_VG2_M2ZZ_BtoS_PSEUDO, + UDOT_VG2_M2ZZ_HtoD_PSEUDO, + UDOT_VG2_M2ZZ_HtoS_PSEUDO, + UDOT_VG4_M4Z4Z_BtoS_PSEUDO, + UDOT_VG4_M4Z4Z_HtoD_PSEUDO, + UDOT_VG4_M4Z4Z_HtoS_PSEUDO, + UDOT_VG4_M4ZZI_BtoS_PSEUDO, + UDOT_VG4_M4ZZI_HToS_PSEUDO, + UDOT_VG4_M4ZZI_HtoD_PSEUDO, + UDOT_VG4_M4ZZ_BtoS_PSEUDO, + UDOT_VG4_M4ZZ_HtoD_PSEUDO, + UDOT_VG4_M4ZZ_HtoS_PSEUDO, + UHSUB_ZPZZ_B_UNDEF, + UHSUB_ZPZZ_D_UNDEF, + UHSUB_ZPZZ_H_UNDEF, + UHSUB_ZPZZ_S_UNDEF, + UMAX_ZPZZ_B_UNDEF, + UMAX_ZPZZ_D_UNDEF, + UMAX_ZPZZ_H_UNDEF, + UMAX_ZPZZ_S_UNDEF, + UMIN_ZPZZ_B_UNDEF, + UMIN_ZPZZ_D_UNDEF, + UMIN_ZPZZ_H_UNDEF, + UMIN_ZPZZ_S_UNDEF, + UMLALL_MZZI_BtoS_PSEUDO, + UMLALL_MZZI_HtoD_PSEUDO, + UMLALL_MZZ_BtoS_PSEUDO, + UMLALL_MZZ_HtoD_PSEUDO, + UMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + UMLALL_VG2_M2Z2Z_HtoD_PSEUDO, + UMLALL_VG2_M2ZZI_BtoS_PSEUDO, + UMLALL_VG2_M2ZZI_HtoD_PSEUDO, + UMLALL_VG2_M2ZZ_BtoS_PSEUDO, + UMLALL_VG2_M2ZZ_HtoD_PSEUDO, + UMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + UMLALL_VG4_M4Z4Z_HtoD_PSEUDO, + UMLALL_VG4_M4ZZI_BtoS_PSEUDO, + UMLALL_VG4_M4ZZI_HtoD_PSEUDO, + UMLALL_VG4_M4ZZ_BtoS_PSEUDO, + UMLALL_VG4_M4ZZ_HtoD_PSEUDO, + UMLAL_MZZI_HtoS_PSEUDO, + UMLAL_MZZ_HtoS_PSEUDO, + UMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + UMLAL_VG2_M2ZZI_S_PSEUDO, + UMLAL_VG2_M2ZZ_HtoS_PSEUDO, + UMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + UMLAL_VG4_M4ZZI_HtoS_PSEUDO, + UMLAL_VG4_M4ZZ_HtoS_PSEUDO, + UMLSLL_MZZI_BtoS_PSEUDO, + UMLSLL_MZZI_HtoD_PSEUDO, + UMLSLL_MZZ_BtoS_PSEUDO, + UMLSLL_MZZ_HtoD_PSEUDO, + UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO, + UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO, + UMLSLL_VG2_M2ZZI_BtoS_PSEUDO, + UMLSLL_VG2_M2ZZI_HtoD_PSEUDO, + UMLSLL_VG2_M2ZZ_BtoS_PSEUDO, + UMLSLL_VG2_M2ZZ_HtoD_PSEUDO, + UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO, + UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO, + UMLSLL_VG4_M4ZZI_BtoS_PSEUDO, + UMLSLL_VG4_M4ZZI_HtoD_PSEUDO, + UMLSLL_VG4_M4ZZ_BtoS_PSEUDO, + UMLSLL_VG4_M4ZZ_HtoD_PSEUDO, + UMLSL_MZZI_HtoS_PSEUDO, + UMLSL_MZZ_HtoS_PSEUDO, + UMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + UMLSL_VG2_M2ZZI_S_PSEUDO, + UMLSL_VG2_M2ZZ_HtoS_PSEUDO, + UMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + UMLSL_VG4_M4ZZI_HtoS_PSEUDO, + UMLSL_VG4_M4ZZ_HtoS_PSEUDO, + UMOP4A_M2Z2Z_BToS_PSEUDO, + UMOP4A_M2Z2Z_HToS_PSEUDO, + UMOP4A_M2Z2Z_HtoD_PSEUDO, + UMOP4A_M2ZZ_BToS_PSEUDO, + UMOP4A_M2ZZ_HToS_PSEUDO, + UMOP4A_M2ZZ_HtoD_PSEUDO, + UMOP4A_MZ2Z_BToS_PSEUDO, + UMOP4A_MZ2Z_HToS_PSEUDO, + UMOP4A_MZ2Z_HtoD_PSEUDO, + UMOP4A_MZZ_BToS_PSEUDO, + UMOP4A_MZZ_HToS_PSEUDO, + UMOP4A_MZZ_HtoD_PSEUDO, + UMOP4S_M2Z2Z_BToS_PSEUDO, + UMOP4S_M2Z2Z_HToS_PSEUDO, + UMOP4S_M2Z2Z_HtoD_PSEUDO, + UMOP4S_M2ZZ_BToS_PSEUDO, + UMOP4S_M2ZZ_HToS_PSEUDO, + UMOP4S_M2ZZ_HtoD_PSEUDO, + UMOP4S_MZ2Z_BToS_PSEUDO, + UMOP4S_MZ2Z_HToS_PSEUDO, + UMOP4S_MZ2Z_HtoD_PSEUDO, + UMOP4S_MZZ_BToS_PSEUDO, + UMOP4S_MZZ_HToS_PSEUDO, + UMOP4S_MZZ_HtoD_PSEUDO, + UMOPA_MPPZZ_D_PSEUDO, + UMOPA_MPPZZ_HtoS_PSEUDO, + UMOPA_MPPZZ_S_PSEUDO, + UMOPS_MPPZZ_D_PSEUDO, + UMOPS_MPPZZ_HtoS_PSEUDO, + UMOPS_MPPZZ_S_PSEUDO, + UMULH_ZPZZ_B_UNDEF, + UMULH_ZPZZ_D_UNDEF, + UMULH_ZPZZ_H_UNDEF, + UMULH_ZPZZ_S_UNDEF, + UQRSHL_ZPZZ_B_UNDEF, + UQRSHL_ZPZZ_D_UNDEF, + UQRSHL_ZPZZ_H_UNDEF, + UQRSHL_ZPZZ_S_UNDEF, + UQSHL_ZPZI_B_UNDEF, + UQSHL_ZPZI_B_ZERO, + UQSHL_ZPZI_D_UNDEF, + UQSHL_ZPZI_D_ZERO, + UQSHL_ZPZI_H_UNDEF, + UQSHL_ZPZI_H_ZERO, + UQSHL_ZPZI_S_UNDEF, + UQSHL_ZPZI_S_ZERO, + UQSHL_ZPZZ_B_UNDEF, + UQSHL_ZPZZ_D_UNDEF, + UQSHL_ZPZZ_H_UNDEF, + UQSHL_ZPZZ_S_UNDEF, + URECPE_ZPmZ_S_UNDEF, + URSHL_ZPZZ_B_UNDEF, + URSHL_ZPZZ_D_UNDEF, + URSHL_ZPZZ_H_UNDEF, + URSHL_ZPZZ_S_UNDEF, + URSHR_ZPZI_B_ZERO, + URSHR_ZPZI_D_ZERO, + URSHR_ZPZI_H_ZERO, + URSHR_ZPZI_S_ZERO, + URSQRTE_ZPmZ_S_UNDEF, + USDOT_VG2_M2Z2Z_BToS_PSEUDO, + USDOT_VG2_M2ZZI_BToS_PSEUDO, + USDOT_VG2_M2ZZ_BToS_PSEUDO, + USDOT_VG4_M4Z4Z_BToS_PSEUDO, + USDOT_VG4_M4ZZI_BToS_PSEUDO, + USDOT_VG4_M4ZZ_BToS_PSEUDO, + USMLALL_MZZI_BtoS_PSEUDO, + USMLALL_MZZ_BtoS_PSEUDO, + USMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + USMLALL_VG2_M2ZZI_BtoS_PSEUDO, + USMLALL_VG2_M2ZZ_BtoS_PSEUDO, + USMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + USMLALL_VG4_M4ZZI_BtoS_PSEUDO, + USMLALL_VG4_M4ZZ_BtoS_PSEUDO, + USMOP4A_M2Z2Z_BToS_PSEUDO, + USMOP4A_M2Z2Z_HtoD_PSEUDO, + USMOP4A_M2ZZ_BToS_PSEUDO, + USMOP4A_M2ZZ_HtoD_PSEUDO, + USMOP4A_MZ2Z_BToS_PSEUDO, + USMOP4A_MZ2Z_HtoD_PSEUDO, + USMOP4A_MZZ_BToS_PSEUDO, + USMOP4A_MZZ_HtoD_PSEUDO, + USMOP4S_M2Z2Z_BToS_PSEUDO, + USMOP4S_M2Z2Z_HtoD_PSEUDO, + USMOP4S_M2ZZ_BToS_PSEUDO, + USMOP4S_M2ZZ_HtoD_PSEUDO, + USMOP4S_MZ2Z_BToS_PSEUDO, + USMOP4S_MZ2Z_HtoD_PSEUDO, + USMOP4S_MZZ_BToS_PSEUDO, + USMOP4S_MZZ_HtoD_PSEUDO, + USMOPA_MPPZZ_D_PSEUDO, + USMOPA_MPPZZ_S_PSEUDO, + USMOPS_MPPZZ_D_PSEUDO, + USMOPS_MPPZZ_S_PSEUDO, + USTMOPA_M2ZZZI_BtoS_PSEUDO, + USVDOT_VG4_M4ZZI_BToS_PSEUDO, + UTMOPA_M2ZZZI_BtoS_PSEUDO, + UTMOPA_M2ZZZI_HtoS_PSEUDO, + UVDOT_VG2_M2ZZI_HtoS_PSEUDO, + UVDOT_VG4_M4ZZI_BtoS_PSEUDO, + UVDOT_VG4_M4ZZI_HtoD_PSEUDO, + UXTB_ZPmZ_D_UNDEF, + UXTB_ZPmZ_H_UNDEF, + UXTB_ZPmZ_S_UNDEF, + UXTH_ZPmZ_D_UNDEF, + UXTH_ZPmZ_S_UNDEF, + UXTW_ZPmZ_D_UNDEF, + ZERO_MXI_2Z_PSEUDO, + ZERO_MXI_4Z_PSEUDO, + ZERO_MXI_VG2_2Z_PSEUDO, + ZERO_MXI_VG2_4Z_PSEUDO, + ZERO_MXI_VG2_Z_PSEUDO, + ZERO_MXI_VG4_2Z_PSEUDO, + ZERO_MXI_VG4_4Z_PSEUDO, + ZERO_MXI_VG4_Z_PSEUDO, + ZERO_M_PSEUDO, + ZERO_T_PSEUDO, + ABSWr, + ABSXr, + ABS_ZPmZ_B, + ABS_ZPmZ_D, + ABS_ZPmZ_H, + ABS_ZPmZ_S, + ABS_ZPzZ_B, + ABS_ZPzZ_D, + ABS_ZPzZ_H, + ABS_ZPzZ_S, + ABSv16i8, + ABSv1i64, + ABSv2i32, + ABSv2i64, + ABSv4i16, + ABSv4i32, + ABSv8i16, + ABSv8i8, + ADCLB_ZZZ_D, + ADCLB_ZZZ_S, + ADCLT_ZZZ_D, + ADCLT_ZZZ_S, + ADCSWr, + ADCSXr, + ADCWr, + ADCXr, + ADDG, + ADDHA_MPPZ_D, + ADDHA_MPPZ_S, + ADDHNB_ZZZ_B, + ADDHNB_ZZZ_H, + ADDHNB_ZZZ_S, + ADDHNT_ZZZ_B, + ADDHNT_ZZZ_H, + ADDHNT_ZZZ_S, + ADDHNv2i64_v2i32, + ADDHNv2i64_v4i32, + ADDHNv4i32_v4i16, + ADDHNv4i32_v8i16, + ADDHNv8i16_v16i8, + ADDHNv8i16_v8i8, + ADDPL_XXI, + ADDPT_shift, + ADDP_ZPmZ_B, + ADDP_ZPmZ_D, + ADDP_ZPmZ_H, + ADDP_ZPmZ_S, + ADDPv16i8, + ADDPv2i32, + ADDPv2i64, + ADDPv2i64p, + ADDPv4i16, + ADDPv4i32, + ADDPv8i16, + ADDPv8i8, + ADDQP_ZZZ_B, + ADDQP_ZZZ_D, + ADDQP_ZZZ_H, + ADDQP_ZZZ_S, + ADDQV_VPZ_B, + ADDQV_VPZ_D, + ADDQV_VPZ_H, + ADDQV_VPZ_S, + ADDSPL_XXI, + ADDSUBP_ZZZ_B, + ADDSUBP_ZZZ_D, + ADDSUBP_ZZZ_H, + ADDSUBP_ZZZ_S, + ADDSVL_XXI, + ADDSWri, + ADDSWrs, + ADDSWrx, + ADDSXri, + ADDSXrs, + ADDSXrx, + ADDSXrx64, + ADDVA_MPPZ_D, + ADDVA_MPPZ_S, + ADDVL_XXI, + ADDVv16i8v, + ADDVv4i16v, + ADDVv4i32v, + ADDVv8i16v, + ADDVv8i8v, + ADDWri, + ADDWrs, + ADDWrx, + ADDXri, + ADDXrs, + ADDXrx, + ADDXrx64, + ADD_VG2_2ZZ_B, + ADD_VG2_2ZZ_D, + ADD_VG2_2ZZ_H, + ADD_VG2_2ZZ_S, + ADD_VG2_M2Z2Z_D, + ADD_VG2_M2Z2Z_S, + ADD_VG2_M2ZZ_D, + ADD_VG2_M2ZZ_S, + ADD_VG2_M2Z_D, + ADD_VG2_M2Z_S, + ADD_VG4_4ZZ_B, + ADD_VG4_4ZZ_D, + ADD_VG4_4ZZ_H, + ADD_VG4_4ZZ_S, + ADD_VG4_M4Z4Z_D, + ADD_VG4_M4Z4Z_S, + ADD_VG4_M4ZZ_D, + ADD_VG4_M4ZZ_S, + ADD_VG4_M4Z_D, + ADD_VG4_M4Z_S, + ADD_ZI_B, + ADD_ZI_D, + ADD_ZI_H, + ADD_ZI_S, + ADD_ZPmZ_B, + ADD_ZPmZ_CPA, + ADD_ZPmZ_D, + ADD_ZPmZ_H, + ADD_ZPmZ_S, + ADD_ZZZ_B, + ADD_ZZZ_CPA, + ADD_ZZZ_D, + ADD_ZZZ_H, + ADD_ZZZ_S, + ADDv16i8, + ADDv1i64, + ADDv2i32, + ADDv2i64, + ADDv4i16, + ADDv4i32, + ADDv8i16, + ADDv8i8, + ADR, + ADRP, + ADR_LSL_ZZZ_D_0, + ADR_LSL_ZZZ_D_1, + ADR_LSL_ZZZ_D_2, + ADR_LSL_ZZZ_D_3, + ADR_LSL_ZZZ_S_0, + ADR_LSL_ZZZ_S_1, + ADR_LSL_ZZZ_S_2, + ADR_LSL_ZZZ_S_3, + ADR_SXTW_ZZZ_D_0, + ADR_SXTW_ZZZ_D_1, + ADR_SXTW_ZZZ_D_2, + ADR_SXTW_ZZZ_D_3, + ADR_UXTW_ZZZ_D_0, + ADR_UXTW_ZZZ_D_1, + ADR_UXTW_ZZZ_D_2, + ADR_UXTW_ZZZ_D_3, + AESDIMC_2ZZI_B, + AESDIMC_4ZZI_B, + AESD_2ZZI_B, + AESD_4ZZI_B, + AESD_ZZZ_B, + AESDrr, + AESEMC_2ZZI_B, + AESEMC_4ZZI_B, + AESE_2ZZI_B, + AESE_4ZZI_B, + AESE_ZZZ_B, + AESErr, + AESIMC_ZZ_B, + AESIMCrr, + AESMC_ZZ_B, + AESMCrr, + ANDQV_VPZ_B, + ANDQV_VPZ_D, + ANDQV_VPZ_H, + ANDQV_VPZ_S, + ANDSWri, + ANDSWrs, + ANDSXri, + ANDSXrs, + ANDS_PPzPP, + ANDV_VPZ_B, + ANDV_VPZ_D, + ANDV_VPZ_H, + ANDV_VPZ_S, + ANDWri, + ANDWrs, + ANDXri, + ANDXrs, + AND_PPzPP, + AND_ZI, + AND_ZPmZ_B, + AND_ZPmZ_D, + AND_ZPmZ_H, + AND_ZPmZ_S, + AND_ZZZ, + ANDv16i8, + ANDv8i8, + APAS, + ASRD_ZPmI_B, + ASRD_ZPmI_D, + ASRD_ZPmI_H, + ASRD_ZPmI_S, + ASRR_ZPmZ_B, + ASRR_ZPmZ_D, + ASRR_ZPmZ_H, + ASRR_ZPmZ_S, + ASRVWr, + ASRVXr, + ASR_WIDE_ZPmZ_B, + ASR_WIDE_ZPmZ_H, + ASR_WIDE_ZPmZ_S, + ASR_WIDE_ZZZ_B, + ASR_WIDE_ZZZ_H, + ASR_WIDE_ZZZ_S, + ASR_ZPmI_B, + ASR_ZPmI_D, + ASR_ZPmI_H, + ASR_ZPmI_S, + ASR_ZPmZ_B, + ASR_ZPmZ_D, + ASR_ZPmZ_H, + ASR_ZPmZ_S, + ASR_ZZI_B, + ASR_ZZI_D, + ASR_ZZI_H, + ASR_ZZI_S, + AUTDA, + AUTDB, + AUTDZA, + AUTDZB, + AUTIA, + AUTIA1716, + AUTIA171615, + AUTIASP, + AUTIASPPCi, + AUTIASPPCr, + AUTIAZ, + AUTIB, + AUTIB1716, + AUTIB171615, + AUTIBSP, + AUTIBSPPCi, + AUTIBSPPCr, + AUTIBZ, + AUTIZA, + AUTIZB, + AXFLAG, + B, + BCAX, + BCAX_ZZZZ, + BCcc, + BDEP_ZZZ_B, + BDEP_ZZZ_D, + BDEP_ZZZ_H, + BDEP_ZZZ_S, + BEXT_ZZZ_B, + BEXT_ZZZ_D, + BEXT_ZZZ_H, + BEXT_ZZZ_S, + BF16DOTlanev4bf16, + BF16DOTlanev8bf16, + BF1CVTL, + BF1CVTL2, + BF1CVTLT_ZZ_BtoH, + BF1CVTL_2ZZ_BtoH, + BF1CVT_2ZZ_BtoH, + BF1CVT_ZZ_BtoH, + BF2CVTL, + BF2CVTL2, + BF2CVTLT_ZZ_BtoH, + BF2CVTL_2ZZ_BtoH, + BF2CVT_2ZZ_BtoH, + BF2CVT_ZZ_BtoH, + BFADD_VG2_M2Z_H, + BFADD_VG4_M4Z_H, + BFADD_ZPmZZ, + BFADD_ZZZ, + BFCLAMP_VG2_2ZZZ_H, + BFCLAMP_VG4_4ZZZ_H, + BFCLAMP_ZZZ, + BFCVT, + BFCVTN, + BFCVTN2, + BFCVTNT_ZPmZ, + BFCVTNT_ZPzZ_StoH, + BFCVTN_Z2Z_HtoB, + BFCVTN_Z2Z_StoH, + BFCVT_Z2Z_HtoB, + BFCVT_Z2Z_StoH, + BFCVT_ZPmZ, + BFCVT_ZPzZ_StoH, + BFDOT_VG2_M2Z2Z_HtoS, + BFDOT_VG2_M2ZZI_HtoS, + BFDOT_VG2_M2ZZ_HtoS, + BFDOT_VG4_M4Z4Z_HtoS, + BFDOT_VG4_M4ZZI_HtoS, + BFDOT_VG4_M4ZZ_HtoS, + BFDOT_ZZI, + BFDOT_ZZZ, + BFDOTv4bf16, + BFDOTv8bf16, + BFMAXNM_VG2_2Z2Z_H, + BFMAXNM_VG2_2ZZ_H, + BFMAXNM_VG4_4Z2Z_H, + BFMAXNM_VG4_4ZZ_H, + BFMAXNM_ZPmZZ, + BFMAX_VG2_2Z2Z_H, + BFMAX_VG2_2ZZ_H, + BFMAX_VG4_4Z2Z_H, + BFMAX_VG4_4ZZ_H, + BFMAX_ZPmZZ, + BFMINNM_VG2_2Z2Z_H, + BFMINNM_VG2_2ZZ_H, + BFMINNM_VG4_4Z2Z_H, + BFMINNM_VG4_4ZZ_H, + BFMINNM_ZPmZZ, + BFMIN_VG2_2Z2Z_H, + BFMIN_VG2_2ZZ_H, + BFMIN_VG4_4Z2Z_H, + BFMIN_VG4_4ZZ_H, + BFMIN_ZPmZZ, + BFMLALB, + BFMLALBIdx, + BFMLALB_ZZZ, + BFMLALB_ZZZI, + BFMLALT, + BFMLALTIdx, + BFMLALT_ZZZ, + BFMLALT_ZZZI, + BFMLAL_MZZI_HtoS, + BFMLAL_MZZ_HtoS, + BFMLAL_VG2_M2Z2Z_HtoS, + BFMLAL_VG2_M2ZZI_HtoS, + BFMLAL_VG2_M2ZZ_HtoS, + BFMLAL_VG4_M4Z4Z_HtoS, + BFMLAL_VG4_M4ZZI_HtoS, + BFMLAL_VG4_M4ZZ_HtoS, + BFMLA_VG2_M2Z2Z, + BFMLA_VG2_M2ZZ, + BFMLA_VG2_M2ZZI, + BFMLA_VG4_M4Z4Z, + BFMLA_VG4_M4ZZ, + BFMLA_VG4_M4ZZI, + BFMLA_ZPmZZ, + BFMLA_ZZZI, + BFMLSLB_ZZZI_S, + BFMLSLB_ZZZ_S, + BFMLSLT_ZZZI_S, + BFMLSLT_ZZZ_S, + BFMLSL_MZZI_HtoS, + BFMLSL_MZZ_HtoS, + BFMLSL_VG2_M2Z2Z_HtoS, + BFMLSL_VG2_M2ZZI_HtoS, + BFMLSL_VG2_M2ZZ_HtoS, + BFMLSL_VG4_M4Z4Z_HtoS, + BFMLSL_VG4_M4ZZI_HtoS, + BFMLSL_VG4_M4ZZ_HtoS, + BFMLS_VG2_M2Z2Z, + BFMLS_VG2_M2ZZ, + BFMLS_VG2_M2ZZI, + BFMLS_VG4_M4Z4Z, + BFMLS_VG4_M4ZZ, + BFMLS_VG4_M4ZZI, + BFMLS_ZPmZZ, + BFMLS_ZZZI, + BFMMLA, + BFMMLA_ZZZ_H, + BFMMLA_ZZZ_HtoS, + BFMOP4A_M2Z2Z_H, + BFMOP4A_M2Z2Z_S, + BFMOP4A_M2ZZ_H, + BFMOP4A_M2ZZ_S, + BFMOP4A_MZ2Z_H, + BFMOP4A_MZ2Z_S, + BFMOP4A_MZZ_H, + BFMOP4A_MZZ_S, + BFMOP4S_M2Z2Z_H, + BFMOP4S_M2Z2Z_S, + BFMOP4S_M2ZZ_H, + BFMOP4S_M2ZZ_S, + BFMOP4S_MZ2Z_H, + BFMOP4S_MZ2Z_S, + BFMOP4S_MZZ_H, + BFMOP4S_MZZ_S, + BFMOPA_MPPZZ, + BFMOPA_MPPZZ_H, + BFMOPS_MPPZZ, + BFMOPS_MPPZZ_H, + BFMUL_2Z2Z, + BFMUL_2ZZ, + BFMUL_4Z4Z, + BFMUL_4ZZ, + BFMUL_ZPmZZ, + BFMUL_ZZZ, + BFMUL_ZZZI, + BFMWri, + BFMXri, + BFSCALE_2Z2Z, + BFSCALE_2ZZ, + BFSCALE_4Z4Z, + BFSCALE_4ZZ, + BFSCALE_ZPZZ_H, + BFSUB_VG2_M2Z_H, + BFSUB_VG4_M4Z_H, + BFSUB_ZPmZZ, + BFSUB_ZZZ, + BFTMOPA_M2ZZZI_HtoH, + BFTMOPA_M2ZZZI_HtoS, + BFVDOT_VG2_M2ZZI_HtoS, + BGRP_ZZZ_B, + BGRP_ZZZ_D, + BGRP_ZZZ_H, + BGRP_ZZZ_S, + BICSWrs, + BICSXrs, + BICS_PPzPP, + BICWrs, + BICXrs, + BIC_PPzPP, + BIC_ZPmZ_B, + BIC_ZPmZ_D, + BIC_ZPmZ_H, + BIC_ZPmZ_S, + BIC_ZZZ, + BICv16i8, + BICv2i32, + BICv4i16, + BICv4i32, + BICv8i16, + BICv8i8, + BIFv16i8, + BIFv8i8, + BITv16i8, + BITv8i8, + BL, + BLR, + BLRAA, + BLRAAZ, + BLRAB, + BLRABZ, + BMOPA_MPPZZ_S, + BMOPS_MPPZZ_S, + BR, + BRAA, + BRAAZ, + BRAB, + BRABZ, + BRB_IALL, + BRB_INJ, + BRK, + BRKAS_PPzP, + BRKA_PPmP, + BRKA_PPzP, + BRKBS_PPzP, + BRKB_PPmP, + BRKB_PPzP, + BRKNS_PPzP, + BRKN_PPzP, + BRKPAS_PPzPP, + BRKPA_PPzPP, + BRKPBS_PPzPP, + BRKPB_PPzPP, + BSL1N_ZZZZ, + BSL2N_ZZZZ, + BSL_ZZZZ, + BSLv16i8, + BSLv8i8, + Bcc, + CADD_ZZI_B, + CADD_ZZI_D, + CADD_ZZI_H, + CADD_ZZI_S, + CASAB, + CASAH, + CASALB, + CASALH, + CASALTX, + CASALW, + CASALX, + CASATX, + CASAW, + CASAX, + CASB, + CASH, + CASLB, + CASLH, + CASLTX, + CASLW, + CASLX, + CASPALTX, + CASPALW, + CASPALX, + CASPATX, + CASPAW, + CASPAX, + CASPLTX, + CASPLW, + CASPLX, + CASPTX, + CASPW, + CASPX, + CASTX, + CASW, + CASX, + CBBEQWrr, + CBBGEWrr, + CBBGTWrr, + CBBHIWrr, + CBBHSWrr, + CBBNEWrr, + CBEQWri, + CBEQWrr, + CBEQXri, + CBEQXrr, + CBGEWrr, + CBGEXrr, + CBGTWri, + CBGTWrr, + CBGTXri, + CBGTXrr, + CBHEQWrr, + CBHGEWrr, + CBHGTWrr, + CBHHIWrr, + CBHHSWrr, + CBHIWri, + CBHIWrr, + CBHIXri, + CBHIXrr, + CBHNEWrr, + CBHSWrr, + CBHSXrr, + CBLOWri, + CBLOXri, + CBLTWri, + CBLTXri, + CBNEWri, + CBNEWrr, + CBNEXri, + CBNEXrr, + CBNZW, + CBNZX, + CBZW, + CBZX, + CCMNWi, + CCMNWr, + CCMNXi, + CCMNXr, + CCMPWi, + CCMPWr, + CCMPXi, + CCMPXr, + CDOT_ZZZI_D, + CDOT_ZZZI_S, + CDOT_ZZZ_D, + CDOT_ZZZ_S, + CFINV, + CHKFEAT, + CLASTA_RPZ_B, + CLASTA_RPZ_D, + CLASTA_RPZ_H, + CLASTA_RPZ_S, + CLASTA_VPZ_B, + CLASTA_VPZ_D, + CLASTA_VPZ_H, + CLASTA_VPZ_S, + CLASTA_ZPZ_B, + CLASTA_ZPZ_D, + CLASTA_ZPZ_H, + CLASTA_ZPZ_S, + CLASTB_RPZ_B, + CLASTB_RPZ_D, + CLASTB_RPZ_H, + CLASTB_RPZ_S, + CLASTB_VPZ_B, + CLASTB_VPZ_D, + CLASTB_VPZ_H, + CLASTB_VPZ_S, + CLASTB_ZPZ_B, + CLASTB_ZPZ_D, + CLASTB_ZPZ_H, + CLASTB_ZPZ_S, + CLREX, + CLSWr, + CLSXr, + CLS_ZPmZ_B, + CLS_ZPmZ_D, + CLS_ZPmZ_H, + CLS_ZPmZ_S, + CLS_ZPzZ_B, + CLS_ZPzZ_D, + CLS_ZPzZ_H, + CLS_ZPzZ_S, + CLSv16i8, + CLSv2i32, + CLSv4i16, + CLSv4i32, + CLSv8i16, + CLSv8i8, + CLZWr, + CLZXr, + CLZ_ZPmZ_B, + CLZ_ZPmZ_D, + CLZ_ZPmZ_H, + CLZ_ZPmZ_S, + CLZ_ZPzZ_B, + CLZ_ZPzZ_D, + CLZ_ZPzZ_H, + CLZ_ZPzZ_S, + CLZv16i8, + CLZv2i32, + CLZv4i16, + CLZv4i32, + CLZv8i16, + CLZv8i8, + CMEQv16i8, + CMEQv16i8rz, + CMEQv1i64, + CMEQv1i64rz, + CMEQv2i32, + CMEQv2i32rz, + CMEQv2i64, + CMEQv2i64rz, + CMEQv4i16, + CMEQv4i16rz, + CMEQv4i32, + CMEQv4i32rz, + CMEQv8i16, + CMEQv8i16rz, + CMEQv8i8, + CMEQv8i8rz, + CMGEv16i8, + CMGEv16i8rz, + CMGEv1i64, + CMGEv1i64rz, + CMGEv2i32, + CMGEv2i32rz, + CMGEv2i64, + CMGEv2i64rz, + CMGEv4i16, + CMGEv4i16rz, + CMGEv4i32, + CMGEv4i32rz, + CMGEv8i16, + CMGEv8i16rz, + CMGEv8i8, + CMGEv8i8rz, + CMGTv16i8, + CMGTv16i8rz, + CMGTv1i64, + CMGTv1i64rz, + CMGTv2i32, + CMGTv2i32rz, + CMGTv2i64, + CMGTv2i64rz, + CMGTv4i16, + CMGTv4i16rz, + CMGTv4i32, + CMGTv4i32rz, + CMGTv8i16, + CMGTv8i16rz, + CMGTv8i8, + CMGTv8i8rz, + CMHIv16i8, + CMHIv1i64, + CMHIv2i32, + CMHIv2i64, + CMHIv4i16, + CMHIv4i32, + CMHIv8i16, + CMHIv8i8, + CMHSv16i8, + CMHSv1i64, + CMHSv2i32, + CMHSv2i64, + CMHSv4i16, + CMHSv4i32, + CMHSv8i16, + CMHSv8i8, + CMLA_ZZZI_H, + CMLA_ZZZI_S, + CMLA_ZZZ_B, + CMLA_ZZZ_D, + CMLA_ZZZ_H, + CMLA_ZZZ_S, + CMLEv16i8rz, + CMLEv1i64rz, + CMLEv2i32rz, + CMLEv2i64rz, + CMLEv4i16rz, + CMLEv4i32rz, + CMLEv8i16rz, + CMLEv8i8rz, + CMLTv16i8rz, + CMLTv1i64rz, + CMLTv2i32rz, + CMLTv2i64rz, + CMLTv4i16rz, + CMLTv4i32rz, + CMLTv8i16rz, + CMLTv8i8rz, + CMPEQ_PPzZI_B, + CMPEQ_PPzZI_D, + CMPEQ_PPzZI_H, + CMPEQ_PPzZI_S, + CMPEQ_PPzZZ_B, + CMPEQ_PPzZZ_D, + CMPEQ_PPzZZ_H, + CMPEQ_PPzZZ_S, + CMPEQ_WIDE_PPzZZ_B, + CMPEQ_WIDE_PPzZZ_H, + CMPEQ_WIDE_PPzZZ_S, + CMPGE_PPzZI_B, + CMPGE_PPzZI_D, + CMPGE_PPzZI_H, + CMPGE_PPzZI_S, + CMPGE_PPzZZ_B, + CMPGE_PPzZZ_D, + CMPGE_PPzZZ_H, + CMPGE_PPzZZ_S, + CMPGE_WIDE_PPzZZ_B, + CMPGE_WIDE_PPzZZ_H, + CMPGE_WIDE_PPzZZ_S, + CMPGT_PPzZI_B, + CMPGT_PPzZI_D, + CMPGT_PPzZI_H, + CMPGT_PPzZI_S, + CMPGT_PPzZZ_B, + CMPGT_PPzZZ_D, + CMPGT_PPzZZ_H, + CMPGT_PPzZZ_S, + CMPGT_WIDE_PPzZZ_B, + CMPGT_WIDE_PPzZZ_H, + CMPGT_WIDE_PPzZZ_S, + CMPHI_PPzZI_B, + CMPHI_PPzZI_D, + CMPHI_PPzZI_H, + CMPHI_PPzZI_S, + CMPHI_PPzZZ_B, + CMPHI_PPzZZ_D, + CMPHI_PPzZZ_H, + CMPHI_PPzZZ_S, + CMPHI_WIDE_PPzZZ_B, + CMPHI_WIDE_PPzZZ_H, + CMPHI_WIDE_PPzZZ_S, + CMPHS_PPzZI_B, + CMPHS_PPzZI_D, + CMPHS_PPzZI_H, + CMPHS_PPzZI_S, + CMPHS_PPzZZ_B, + CMPHS_PPzZZ_D, + CMPHS_PPzZZ_H, + CMPHS_PPzZZ_S, + CMPHS_WIDE_PPzZZ_B, + CMPHS_WIDE_PPzZZ_H, + CMPHS_WIDE_PPzZZ_S, + CMPLE_PPzZI_B, + CMPLE_PPzZI_D, + CMPLE_PPzZI_H, + CMPLE_PPzZI_S, + CMPLE_WIDE_PPzZZ_B, + CMPLE_WIDE_PPzZZ_H, + CMPLE_WIDE_PPzZZ_S, + CMPLO_PPzZI_B, + CMPLO_PPzZI_D, + CMPLO_PPzZI_H, + CMPLO_PPzZI_S, + CMPLO_WIDE_PPzZZ_B, + CMPLO_WIDE_PPzZZ_H, + CMPLO_WIDE_PPzZZ_S, + CMPLS_PPzZI_B, + CMPLS_PPzZI_D, + CMPLS_PPzZI_H, + CMPLS_PPzZI_S, + CMPLS_WIDE_PPzZZ_B, + CMPLS_WIDE_PPzZZ_H, + CMPLS_WIDE_PPzZZ_S, + CMPLT_PPzZI_B, + CMPLT_PPzZI_D, + CMPLT_PPzZI_H, + CMPLT_PPzZI_S, + CMPLT_WIDE_PPzZZ_B, + CMPLT_WIDE_PPzZZ_H, + CMPLT_WIDE_PPzZZ_S, + CMPNE_PPzZI_B, + CMPNE_PPzZI_D, + CMPNE_PPzZI_H, + CMPNE_PPzZI_S, + CMPNE_PPzZZ_B, + CMPNE_PPzZZ_D, + CMPNE_PPzZZ_H, + CMPNE_PPzZZ_S, + CMPNE_WIDE_PPzZZ_B, + CMPNE_WIDE_PPzZZ_H, + CMPNE_WIDE_PPzZZ_S, + CMTSTv16i8, + CMTSTv1i64, + CMTSTv2i32, + CMTSTv2i64, + CMTSTv4i16, + CMTSTv4i32, + CMTSTv8i16, + CMTSTv8i8, + CNOT_ZPmZ_B, + CNOT_ZPmZ_D, + CNOT_ZPmZ_H, + CNOT_ZPmZ_S, + CNOT_ZPzZ_B, + CNOT_ZPzZ_D, + CNOT_ZPzZ_H, + CNOT_ZPzZ_S, + CNTB_XPiI, + CNTD_XPiI, + CNTH_XPiI, + CNTP_XCI_B, + CNTP_XCI_D, + CNTP_XCI_H, + CNTP_XCI_S, + CNTP_XPP_B, + CNTP_XPP_D, + CNTP_XPP_H, + CNTP_XPP_S, + CNTW_XPiI, + CNTWr, + CNTXr, + CNT_ZPmZ_B, + CNT_ZPmZ_D, + CNT_ZPmZ_H, + CNT_ZPmZ_S, + CNT_ZPzZ_B, + CNT_ZPzZ_D, + CNT_ZPzZ_H, + CNT_ZPzZ_S, + CNTv16i8, + CNTv8i8, + COMPACT_ZPZ_B, + COMPACT_ZPZ_D, + COMPACT_ZPZ_H, + COMPACT_ZPZ_S, + CPYE, + CPYEN, + CPYERN, + CPYERT, + CPYERTN, + CPYERTRN, + CPYERTWN, + CPYET, + CPYETN, + CPYETRN, + CPYETWN, + CPYEWN, + CPYEWT, + CPYEWTN, + CPYEWTRN, + CPYEWTWN, + CPYFE, + CPYFEN, + CPYFERN, + CPYFERT, + CPYFERTN, + CPYFERTRN, + CPYFERTWN, + CPYFET, + CPYFETN, + CPYFETRN, + CPYFETWN, + CPYFEWN, + CPYFEWT, + CPYFEWTN, + CPYFEWTRN, + CPYFEWTWN, + CPYFM, + CPYFMN, + CPYFMRN, + CPYFMRT, + CPYFMRTN, + CPYFMRTRN, + CPYFMRTWN, + CPYFMT, + CPYFMTN, + CPYFMTRN, + CPYFMTWN, + CPYFMWN, + CPYFMWT, + CPYFMWTN, + CPYFMWTRN, + CPYFMWTWN, + CPYFP, + CPYFPN, + CPYFPRN, + CPYFPRT, + CPYFPRTN, + CPYFPRTRN, + CPYFPRTWN, + CPYFPT, + CPYFPTN, + CPYFPTRN, + CPYFPTWN, + CPYFPWN, + CPYFPWT, + CPYFPWTN, + CPYFPWTRN, + CPYFPWTWN, + CPYM, + CPYMN, + CPYMRN, + CPYMRT, + CPYMRTN, + CPYMRTRN, + CPYMRTWN, + CPYMT, + CPYMTN, + CPYMTRN, + CPYMTWN, + CPYMWN, + CPYMWT, + CPYMWTN, + CPYMWTRN, + CPYMWTWN, + CPYP, + CPYPN, + CPYPRN, + CPYPRT, + CPYPRTN, + CPYPRTRN, + CPYPRTWN, + CPYPT, + CPYPTN, + CPYPTRN, + CPYPTWN, + CPYPWN, + CPYPWT, + CPYPWTN, + CPYPWTRN, + CPYPWTWN, + CPY_ZPmI_B, + CPY_ZPmI_D, + CPY_ZPmI_H, + CPY_ZPmI_S, + CPY_ZPmR_B, + CPY_ZPmR_D, + CPY_ZPmR_H, + CPY_ZPmR_S, + CPY_ZPmV_B, + CPY_ZPmV_D, + CPY_ZPmV_H, + CPY_ZPmV_S, + CPY_ZPzI_B, + CPY_ZPzI_D, + CPY_ZPzI_H, + CPY_ZPzI_S, + CRC32Brr, + CRC32CBrr, + CRC32CHrr, + CRC32CWrr, + CRC32CXrr, + CRC32Hrr, + CRC32Wrr, + CRC32Xrr, + CSELWr, + CSELXr, + CSINCWr, + CSINCXr, + CSINVWr, + CSINVXr, + CSNEGWr, + CSNEGXr, + CTERMEQ_WW, + CTERMEQ_XX, + CTERMNE_WW, + CTERMNE_XX, + CTZWr, + CTZXr, + DCPS1, + DCPS2, + DCPS3, + DECB_XPiI, + DECD_XPiI, + DECD_ZPiI, + DECH_XPiI, + DECH_ZPiI, + DECP_XP_B, + DECP_XP_D, + DECP_XP_H, + DECP_XP_S, + DECP_ZP_D, + DECP_ZP_H, + DECP_ZP_S, + DECW_XPiI, + DECW_ZPiI, + DMB, + DRPS, + DSB, + DSBnXS, + DUPM_ZI, + DUPQ_ZZI_B, + DUPQ_ZZI_D, + DUPQ_ZZI_H, + DUPQ_ZZI_S, + DUP_ZI_B, + DUP_ZI_D, + DUP_ZI_H, + DUP_ZI_S, + DUP_ZR_B, + DUP_ZR_D, + DUP_ZR_H, + DUP_ZR_S, + DUP_ZZI_B, + DUP_ZZI_D, + DUP_ZZI_H, + DUP_ZZI_Q, + DUP_ZZI_S, + DUPi16, + DUPi32, + DUPi64, + DUPi8, + DUPv16i8gpr, + DUPv16i8lane, + DUPv2i32gpr, + DUPv2i32lane, + DUPv2i64gpr, + DUPv2i64lane, + DUPv4i16gpr, + DUPv4i16lane, + DUPv4i32gpr, + DUPv4i32lane, + DUPv8i16gpr, + DUPv8i16lane, + DUPv8i8gpr, + DUPv8i8lane, + EONWrs, + EONXrs, + EOR3, + EOR3_ZZZZ, + EORBT_ZZZ_B, + EORBT_ZZZ_D, + EORBT_ZZZ_H, + EORBT_ZZZ_S, + EORQV_VPZ_B, + EORQV_VPZ_D, + EORQV_VPZ_H, + EORQV_VPZ_S, + EORS_PPzPP, + EORTB_ZZZ_B, + EORTB_ZZZ_D, + EORTB_ZZZ_H, + EORTB_ZZZ_S, + EORV_VPZ_B, + EORV_VPZ_D, + EORV_VPZ_H, + EORV_VPZ_S, + EORWri, + EORWrs, + EORXri, + EORXrs, + EOR_PPzPP, + EOR_ZI, + EOR_ZPmZ_B, + EOR_ZPmZ_D, + EOR_ZPmZ_H, + EOR_ZPmZ_S, + EOR_ZZZ, + EORv16i8, + EORv8i8, + ERET, + ERETAA, + ERETAB, + EXPAND_ZPZ_B, + EXPAND_ZPZ_D, + EXPAND_ZPZ_H, + EXPAND_ZPZ_S, + EXTQ_ZZI, + EXTRACT_ZPMXI_H_B, + EXTRACT_ZPMXI_H_D, + EXTRACT_ZPMXI_H_H, + EXTRACT_ZPMXI_H_Q, + EXTRACT_ZPMXI_H_S, + EXTRACT_ZPMXI_V_B, + EXTRACT_ZPMXI_V_D, + EXTRACT_ZPMXI_V_H, + EXTRACT_ZPMXI_V_Q, + EXTRACT_ZPMXI_V_S, + EXTRWrri, + EXTRXrri, + EXT_ZZI, + EXT_ZZI_B, + EXTv16i8, + EXTv8i8, + F1CVTL, + F1CVTL2, + F1CVTLT_ZZ_BtoH, + F1CVTL_2ZZ_BtoH, + F1CVT_2ZZ_BtoH, + F1CVT_ZZ_BtoH, + F2CVTL, + F2CVTL2, + F2CVTLT_ZZ_BtoH, + F2CVTL_2ZZ_BtoH, + F2CVT_2ZZ_BtoH, + F2CVT_ZZ_BtoH, + FABD16, + FABD32, + FABD64, + FABD_ZPmZ_D, + FABD_ZPmZ_H, + FABD_ZPmZ_S, + FABDv2f32, + FABDv2f64, + FABDv4f16, + FABDv4f32, + FABDv8f16, + FABSDr, + FABSHr, + FABSSr, + FABS_ZPmZ_D, + FABS_ZPmZ_H, + FABS_ZPmZ_S, + FABS_ZPzZ_D, + FABS_ZPzZ_H, + FABS_ZPzZ_S, + FABSv2f32, + FABSv2f64, + FABSv4f16, + FABSv4f32, + FABSv8f16, + FACGE16, + FACGE32, + FACGE64, + FACGE_PPzZZ_D, + FACGE_PPzZZ_H, + FACGE_PPzZZ_S, + FACGEv2f32, + FACGEv2f64, + FACGEv4f16, + FACGEv4f32, + FACGEv8f16, + FACGT16, + FACGT32, + FACGT64, + FACGT_PPzZZ_D, + FACGT_PPzZZ_H, + FACGT_PPzZZ_S, + FACGTv2f32, + FACGTv2f64, + FACGTv4f16, + FACGTv4f32, + FACGTv8f16, + FADDA_VPZ_D, + FADDA_VPZ_H, + FADDA_VPZ_S, + FADDDrr, + FADDHrr, + FADDP_ZPmZZ_D, + FADDP_ZPmZZ_H, + FADDP_ZPmZZ_S, + FADDPv2f32, + FADDPv2f64, + FADDPv2i16p, + FADDPv2i32p, + FADDPv2i64p, + FADDPv4f16, + FADDPv4f32, + FADDPv8f16, + FADDQV_D, + FADDQV_H, + FADDQV_S, + FADDSrr, + FADDV_VPZ_D, + FADDV_VPZ_H, + FADDV_VPZ_S, + FADD_VG2_M2Z_D, + FADD_VG2_M2Z_H, + FADD_VG2_M2Z_S, + FADD_VG4_M4Z_D, + FADD_VG4_M4Z_H, + FADD_VG4_M4Z_S, + FADD_ZPmI_D, + FADD_ZPmI_H, + FADD_ZPmI_S, + FADD_ZPmZ_D, + FADD_ZPmZ_H, + FADD_ZPmZ_S, + FADD_ZZZ_D, + FADD_ZZZ_H, + FADD_ZZZ_S, + FADDv2f32, + FADDv2f64, + FADDv4f16, + FADDv4f32, + FADDv8f16, + FAMAX_2Z2Z_D, + FAMAX_2Z2Z_H, + FAMAX_2Z2Z_S, + FAMAX_4Z4Z_D, + FAMAX_4Z4Z_H, + FAMAX_4Z4Z_S, + FAMAX_ZPmZ_D, + FAMAX_ZPmZ_H, + FAMAX_ZPmZ_S, + FAMAXv2f32, + FAMAXv2f64, + FAMAXv4f16, + FAMAXv4f32, + FAMAXv8f16, + FAMIN_2Z2Z_D, + FAMIN_2Z2Z_H, + FAMIN_2Z2Z_S, + FAMIN_4Z4Z_D, + FAMIN_4Z4Z_H, + FAMIN_4Z4Z_S, + FAMIN_ZPmZ_D, + FAMIN_ZPmZ_H, + FAMIN_ZPmZ_S, + FAMINv2f32, + FAMINv2f64, + FAMINv4f16, + FAMINv4f32, + FAMINv8f16, + FCADD_ZPmZ_D, + FCADD_ZPmZ_H, + FCADD_ZPmZ_S, + FCADDv2f32, + FCADDv2f64, + FCADDv4f16, + FCADDv4f32, + FCADDv8f16, + FCCMPDrr, + FCCMPEDrr, + FCCMPEHrr, + FCCMPESrr, + FCCMPHrr, + FCCMPSrr, + FCLAMP_VG2_2Z2Z_D, + FCLAMP_VG2_2Z2Z_H, + FCLAMP_VG2_2Z2Z_S, + FCLAMP_VG4_4Z4Z_D, + FCLAMP_VG4_4Z4Z_H, + FCLAMP_VG4_4Z4Z_S, + FCLAMP_ZZZ_D, + FCLAMP_ZZZ_H, + FCLAMP_ZZZ_S, + FCMEQ16, + FCMEQ32, + FCMEQ64, + FCMEQ_PPzZ0_D, + FCMEQ_PPzZ0_H, + FCMEQ_PPzZ0_S, + FCMEQ_PPzZZ_D, + FCMEQ_PPzZZ_H, + FCMEQ_PPzZZ_S, + FCMEQv1i16rz, + FCMEQv1i32rz, + FCMEQv1i64rz, + FCMEQv2f32, + FCMEQv2f64, + FCMEQv2i32rz, + FCMEQv2i64rz, + FCMEQv4f16, + FCMEQv4f32, + FCMEQv4i16rz, + FCMEQv4i32rz, + FCMEQv8f16, + FCMEQv8i16rz, + FCMGE16, + FCMGE32, + FCMGE64, + FCMGE_PPzZ0_D, + FCMGE_PPzZ0_H, + FCMGE_PPzZ0_S, + FCMGE_PPzZZ_D, + FCMGE_PPzZZ_H, + FCMGE_PPzZZ_S, + FCMGEv1i16rz, + FCMGEv1i32rz, + FCMGEv1i64rz, + FCMGEv2f32, + FCMGEv2f64, + FCMGEv2i32rz, + FCMGEv2i64rz, + FCMGEv4f16, + FCMGEv4f32, + FCMGEv4i16rz, + FCMGEv4i32rz, + FCMGEv8f16, + FCMGEv8i16rz, + FCMGT16, + FCMGT32, + FCMGT64, + FCMGT_PPzZ0_D, + FCMGT_PPzZ0_H, + FCMGT_PPzZ0_S, + FCMGT_PPzZZ_D, + FCMGT_PPzZZ_H, + FCMGT_PPzZZ_S, + FCMGTv1i16rz, + FCMGTv1i32rz, + FCMGTv1i64rz, + FCMGTv2f32, + FCMGTv2f64, + FCMGTv2i32rz, + FCMGTv2i64rz, + FCMGTv4f16, + FCMGTv4f32, + FCMGTv4i16rz, + FCMGTv4i32rz, + FCMGTv8f16, + FCMGTv8i16rz, + FCMLA_ZPmZZ_D, + FCMLA_ZPmZZ_H, + FCMLA_ZPmZZ_S, + FCMLA_ZZZI_H, + FCMLA_ZZZI_S, + FCMLAv2f32, + FCMLAv2f64, + FCMLAv4f16, + FCMLAv4f16_indexed, + FCMLAv4f32, + FCMLAv4f32_indexed, + FCMLAv8f16, + FCMLAv8f16_indexed, + FCMLE_PPzZ0_D, + FCMLE_PPzZ0_H, + FCMLE_PPzZ0_S, + FCMLEv1i16rz, + FCMLEv1i32rz, + FCMLEv1i64rz, + FCMLEv2i32rz, + FCMLEv2i64rz, + FCMLEv4i16rz, + FCMLEv4i32rz, + FCMLEv8i16rz, + FCMLT_PPzZ0_D, + FCMLT_PPzZ0_H, + FCMLT_PPzZ0_S, + FCMLTv1i16rz, + FCMLTv1i32rz, + FCMLTv1i64rz, + FCMLTv2i32rz, + FCMLTv2i64rz, + FCMLTv4i16rz, + FCMLTv4i32rz, + FCMLTv8i16rz, + FCMNE_PPzZ0_D, + FCMNE_PPzZ0_H, + FCMNE_PPzZ0_S, + FCMNE_PPzZZ_D, + FCMNE_PPzZZ_H, + FCMNE_PPzZZ_S, + FCMPDri, + FCMPDrr, + FCMPEDri, + FCMPEDrr, + FCMPEHri, + FCMPEHrr, + FCMPESri, + FCMPESrr, + FCMPHri, + FCMPHrr, + FCMPSri, + FCMPSrr, + FCMUO_PPzZZ_D, + FCMUO_PPzZZ_H, + FCMUO_PPzZZ_S, + FCPY_ZPmI_D, + FCPY_ZPmI_H, + FCPY_ZPmI_S, + FCSELDrrr, + FCSELHrrr, + FCSELSrrr, + FCVTASDHr, + FCVTASDSr, + FCVTASSDr, + FCVTASSHr, + FCVTASUWDr, + FCVTASUWHr, + FCVTASUWSr, + FCVTASUXDr, + FCVTASUXHr, + FCVTASUXSr, + FCVTASv1f16, + FCVTASv1i32, + FCVTASv1i64, + FCVTASv2f32, + FCVTASv2f64, + FCVTASv4f16, + FCVTASv4f32, + FCVTASv8f16, + FCVTAUDHr, + FCVTAUDSr, + FCVTAUSDr, + FCVTAUSHr, + FCVTAUUWDr, + FCVTAUUWHr, + FCVTAUUWSr, + FCVTAUUXDr, + FCVTAUUXHr, + FCVTAUUXSr, + FCVTAUv1f16, + FCVTAUv1i32, + FCVTAUv1i64, + FCVTAUv2f32, + FCVTAUv2f64, + FCVTAUv4f16, + FCVTAUv4f32, + FCVTAUv8f16, + FCVTDHr, + FCVTDSr, + FCVTHDr, + FCVTHSr, + FCVTLT_ZPmZ_HtoS, + FCVTLT_ZPmZ_StoD, + FCVTLT_ZPzZ_HtoS, + FCVTLT_ZPzZ_StoD, + FCVTL_2ZZ_H_S, + FCVTLv2i32, + FCVTLv4i16, + FCVTLv4i32, + FCVTLv8i16, + FCVTMSDHr, + FCVTMSDSr, + FCVTMSSDr, + FCVTMSSHr, + FCVTMSUWDr, + FCVTMSUWHr, + FCVTMSUWSr, + FCVTMSUXDr, + FCVTMSUXHr, + FCVTMSUXSr, + FCVTMSv1f16, + FCVTMSv1i32, + FCVTMSv1i64, + FCVTMSv2f32, + FCVTMSv2f64, + FCVTMSv4f16, + FCVTMSv4f32, + FCVTMSv8f16, + FCVTMUDHr, + FCVTMUDSr, + FCVTMUSDr, + FCVTMUSHr, + FCVTMUUWDr, + FCVTMUUWHr, + FCVTMUUWSr, + FCVTMUUXDr, + FCVTMUUXHr, + FCVTMUUXSr, + FCVTMUv1f16, + FCVTMUv1i32, + FCVTMUv1i64, + FCVTMUv2f32, + FCVTMUv2f64, + FCVTMUv4f16, + FCVTMUv4f32, + FCVTMUv8f16, + FCVTNB_Z2Z_StoB, + FCVTNSDHr, + FCVTNSDSr, + FCVTNSSDr, + FCVTNSSHr, + FCVTNSUWDr, + FCVTNSUWHr, + FCVTNSUWSr, + FCVTNSUXDr, + FCVTNSUXHr, + FCVTNSUXSr, + FCVTNSv1f16, + FCVTNSv1i32, + FCVTNSv1i64, + FCVTNSv2f32, + FCVTNSv2f64, + FCVTNSv4f16, + FCVTNSv4f32, + FCVTNSv8f16, + FCVTNT_Z2Z_StoB, + FCVTNT_ZPmZ_DtoS, + FCVTNT_ZPmZ_StoH, + FCVTNT_ZPzZ_DtoS, + FCVTNT_ZPzZ_StoH, + FCVTNUDHr, + FCVTNUDSr, + FCVTNUSDr, + FCVTNUSHr, + FCVTNUUWDr, + FCVTNUUWHr, + FCVTNUUWSr, + FCVTNUUXDr, + FCVTNUUXHr, + FCVTNUUXSr, + FCVTNUv1f16, + FCVTNUv1i32, + FCVTNUv1i64, + FCVTNUv2f32, + FCVTNUv2f64, + FCVTNUv4f16, + FCVTNUv4f32, + FCVTNUv8f16, + FCVTN_F16v16f8, + FCVTN_F16v8f8, + FCVTN_F322v16f8, + FCVTN_F32v8f8, + FCVTN_Z2Z_HtoB, + FCVTN_Z2Z_StoH, + FCVTN_Z4Z_StoB, + FCVTNv2i32, + FCVTNv4i16, + FCVTNv4i32, + FCVTNv8i16, + FCVTPSDHr, + FCVTPSDSr, + FCVTPSSDr, + FCVTPSSHr, + FCVTPSUWDr, + FCVTPSUWHr, + FCVTPSUWSr, + FCVTPSUXDr, + FCVTPSUXHr, + FCVTPSUXSr, + FCVTPSv1f16, + FCVTPSv1i32, + FCVTPSv1i64, + FCVTPSv2f32, + FCVTPSv2f64, + FCVTPSv4f16, + FCVTPSv4f32, + FCVTPSv8f16, + FCVTPUDHr, + FCVTPUDSr, + FCVTPUSDr, + FCVTPUSHr, + FCVTPUUWDr, + FCVTPUUWHr, + FCVTPUUWSr, + FCVTPUUXDr, + FCVTPUUXHr, + FCVTPUUXSr, + FCVTPUv1f16, + FCVTPUv1i32, + FCVTPUv1i64, + FCVTPUv2f32, + FCVTPUv2f64, + FCVTPUv4f16, + FCVTPUv4f32, + FCVTPUv8f16, + FCVTSDr, + FCVTSHr, + FCVTXNT_ZPmZ_DtoS, + FCVTXNT_ZPzZ_StoD, + FCVTXNv1i64, + FCVTXNv2f32, + FCVTXNv4f32, + FCVTX_ZPmZ_DtoS, + FCVTX_ZPzZ_DtoS, + FCVTZSDHr, + FCVTZSDSr, + FCVTZSN_Z2Z_DtoS, + FCVTZSN_Z2Z_HtoB, + FCVTZSN_Z2Z_StoH, + FCVTZSSDr, + FCVTZSSHr, + FCVTZSSWDri, + FCVTZSSWHri, + FCVTZSSWSri, + FCVTZSSXDri, + FCVTZSSXHri, + FCVTZSSXSri, + FCVTZSUWDr, + FCVTZSUWHr, + FCVTZSUWSr, + FCVTZSUXDr, + FCVTZSUXHr, + FCVTZSUXSr, + FCVTZS_2Z2Z_StoS, + FCVTZS_4Z4Z_StoS, + FCVTZS_ZPmZ_DtoD, + FCVTZS_ZPmZ_DtoS, + FCVTZS_ZPmZ_HtoD, + FCVTZS_ZPmZ_HtoH, + FCVTZS_ZPmZ_HtoS, + FCVTZS_ZPmZ_StoD, + FCVTZS_ZPmZ_StoS, + FCVTZS_ZPzZ_DtoD, + FCVTZS_ZPzZ_DtoS, + FCVTZS_ZPzZ_HtoD, + FCVTZS_ZPzZ_HtoH, + FCVTZS_ZPzZ_HtoS, + FCVTZS_ZPzZ_StoD, + FCVTZS_ZPzZ_StoS, + FCVTZSd, + FCVTZSh, + FCVTZSs, + FCVTZSv1f16, + FCVTZSv1i32, + FCVTZSv1i64, + FCVTZSv2f32, + FCVTZSv2f64, + FCVTZSv2i32_shift, + FCVTZSv2i64_shift, + FCVTZSv4f16, + FCVTZSv4f32, + FCVTZSv4i16_shift, + FCVTZSv4i32_shift, + FCVTZSv8f16, + FCVTZSv8i16_shift, + FCVTZUDHr, + FCVTZUDSr, + FCVTZUN_Z2Z_DtoS, + FCVTZUN_Z2Z_HtoB, + FCVTZUN_Z2Z_StoH, + FCVTZUSDr, + FCVTZUSHr, + FCVTZUSWDri, + FCVTZUSWHri, + FCVTZUSWSri, + FCVTZUSXDri, + FCVTZUSXHri, + FCVTZUSXSri, + FCVTZUUWDr, + FCVTZUUWHr, + FCVTZUUWSr, + FCVTZUUXDr, + FCVTZUUXHr, + FCVTZUUXSr, + FCVTZU_2Z2Z_StoS, + FCVTZU_4Z4Z_StoS, + FCVTZU_ZPmZ_DtoD, + FCVTZU_ZPmZ_DtoS, + FCVTZU_ZPmZ_HtoD, + FCVTZU_ZPmZ_HtoH, + FCVTZU_ZPmZ_HtoS, + FCVTZU_ZPmZ_StoD, + FCVTZU_ZPmZ_StoS, + FCVTZU_ZPzZ_DtoD, + FCVTZU_ZPzZ_DtoS, + FCVTZU_ZPzZ_HtoD, + FCVTZU_ZPzZ_HtoH, + FCVTZU_ZPzZ_HtoS, + FCVTZU_ZPzZ_StoD, + FCVTZU_ZPzZ_StoS, + FCVTZUd, + FCVTZUh, + FCVTZUs, + FCVTZUv1f16, + FCVTZUv1i32, + FCVTZUv1i64, + FCVTZUv2f32, + FCVTZUv2f64, + FCVTZUv2i32_shift, + FCVTZUv2i64_shift, + FCVTZUv4f16, + FCVTZUv4f32, + FCVTZUv4i16_shift, + FCVTZUv4i32_shift, + FCVTZUv8f16, + FCVTZUv8i16_shift, + FCVT_2ZZ_H_S, + FCVT_Z2Z_HtoB, + FCVT_Z2Z_StoH, + FCVT_Z4Z_StoB, + FCVT_ZPmZ_DtoH, + FCVT_ZPmZ_DtoS, + FCVT_ZPmZ_HtoD, + FCVT_ZPmZ_HtoS, + FCVT_ZPmZ_StoD, + FCVT_ZPmZ_StoH, + FCVT_ZPzZ_DtoH, + FCVT_ZPzZ_DtoS, + FCVT_ZPzZ_HtoD, + FCVT_ZPzZ_HtoS, + FCVT_ZPzZ_StoD, + FCVT_ZPzZ_StoH, + FDIVDrr, + FDIVHrr, + FDIVR_ZPmZ_D, + FDIVR_ZPmZ_H, + FDIVR_ZPmZ_S, + FDIVSrr, + FDIV_ZPmZ_D, + FDIV_ZPmZ_H, + FDIV_ZPmZ_S, + FDIVv2f32, + FDIVv2f64, + FDIVv4f16, + FDIVv4f32, + FDIVv8f16, + FDOT_VG2_M2Z2Z_BtoH, + FDOT_VG2_M2Z2Z_BtoS, + FDOT_VG2_M2Z2Z_HtoS, + FDOT_VG2_M2ZZI_BtoH, + FDOT_VG2_M2ZZI_BtoS, + FDOT_VG2_M2ZZI_HtoS, + FDOT_VG2_M2ZZ_BtoH, + FDOT_VG2_M2ZZ_BtoS, + FDOT_VG2_M2ZZ_HtoS, + FDOT_VG4_M4Z4Z_BtoH, + FDOT_VG4_M4Z4Z_BtoS, + FDOT_VG4_M4Z4Z_HtoS, + FDOT_VG4_M4ZZI_BtoH, + FDOT_VG4_M4ZZI_BtoS, + FDOT_VG4_M4ZZI_HtoS, + FDOT_VG4_M4ZZ_BtoH, + FDOT_VG4_M4ZZ_BtoS, + FDOT_VG4_M4ZZ_HtoS, + FDOT_ZZZI_BtoH, + FDOT_ZZZI_BtoS, + FDOT_ZZZI_S, + FDOT_ZZZ_BtoH, + FDOT_ZZZ_BtoS, + FDOT_ZZZ_S, + FDOTlanev2f32, + FDOTlanev4f16, + FDOTlanev4f16_v2f32, + FDOTlanev4f32, + FDOTlanev8f16, + FDOTlanev8f16_v4f32, + FDOTv2f32, + FDOTv4f16, + FDOTv4f16_v2f32, + FDOTv4f32, + FDOTv8f16, + FDOTv8f16_v4f32, + FDUP_ZI_D, + FDUP_ZI_H, + FDUP_ZI_S, + FEXPA_ZZ_D, + FEXPA_ZZ_H, + FEXPA_ZZ_S, + FIRSTP_XPP_B, + FIRSTP_XPP_D, + FIRSTP_XPP_H, + FIRSTP_XPP_S, + FJCVTZS, + FLOGB_ZPmZ_D, + FLOGB_ZPmZ_H, + FLOGB_ZPmZ_S, + FLOGB_ZPzZ_D, + FLOGB_ZPzZ_H, + FLOGB_ZPzZ_S, + FMADDDrrr, + FMADDHrrr, + FMADDSrrr, + FMAD_ZPmZZ_D, + FMAD_ZPmZZ_H, + FMAD_ZPmZZ_S, + FMAXDrr, + FMAXHrr, + FMAXNMDrr, + FMAXNMHrr, + FMAXNMP_ZPmZZ_D, + FMAXNMP_ZPmZZ_H, + FMAXNMP_ZPmZZ_S, + FMAXNMPv2f32, + FMAXNMPv2f64, + FMAXNMPv2i16p, + FMAXNMPv2i32p, + FMAXNMPv2i64p, + FMAXNMPv4f16, + FMAXNMPv4f32, + FMAXNMPv8f16, + FMAXNMQV_D, + FMAXNMQV_H, + FMAXNMQV_S, + FMAXNMSrr, + FMAXNMV_VPZ_D, + FMAXNMV_VPZ_H, + FMAXNMV_VPZ_S, + FMAXNMVv4i16v, + FMAXNMVv4i32v, + FMAXNMVv8i16v, + FMAXNM_VG2_2Z2Z_D, + FMAXNM_VG2_2Z2Z_H, + FMAXNM_VG2_2Z2Z_S, + FMAXNM_VG2_2ZZ_D, + FMAXNM_VG2_2ZZ_H, + FMAXNM_VG2_2ZZ_S, + FMAXNM_VG4_4Z4Z_D, + FMAXNM_VG4_4Z4Z_H, + FMAXNM_VG4_4Z4Z_S, + FMAXNM_VG4_4ZZ_D, + FMAXNM_VG4_4ZZ_H, + FMAXNM_VG4_4ZZ_S, + FMAXNM_ZPmI_D, + FMAXNM_ZPmI_H, + FMAXNM_ZPmI_S, + FMAXNM_ZPmZ_D, + FMAXNM_ZPmZ_H, + FMAXNM_ZPmZ_S, + FMAXNMv2f32, + FMAXNMv2f64, + FMAXNMv4f16, + FMAXNMv4f32, + FMAXNMv8f16, + FMAXP_ZPmZZ_D, + FMAXP_ZPmZZ_H, + FMAXP_ZPmZZ_S, + FMAXPv2f32, + FMAXPv2f64, + FMAXPv2i16p, + FMAXPv2i32p, + FMAXPv2i64p, + FMAXPv4f16, + FMAXPv4f32, + FMAXPv8f16, + FMAXQV_D, + FMAXQV_H, + FMAXQV_S, + FMAXSrr, + FMAXV_VPZ_D, + FMAXV_VPZ_H, + FMAXV_VPZ_S, + FMAXVv4i16v, + FMAXVv4i32v, + FMAXVv8i16v, + FMAX_VG2_2Z2Z_D, + FMAX_VG2_2Z2Z_H, + FMAX_VG2_2Z2Z_S, + FMAX_VG2_2ZZ_D, + FMAX_VG2_2ZZ_H, + FMAX_VG2_2ZZ_S, + FMAX_VG4_4Z4Z_D, + FMAX_VG4_4Z4Z_H, + FMAX_VG4_4Z4Z_S, + FMAX_VG4_4ZZ_D, + FMAX_VG4_4ZZ_H, + FMAX_VG4_4ZZ_S, + FMAX_ZPmI_D, + FMAX_ZPmI_H, + FMAX_ZPmI_S, + FMAX_ZPmZ_D, + FMAX_ZPmZ_H, + FMAX_ZPmZ_S, + FMAXv2f32, + FMAXv2f64, + FMAXv4f16, + FMAXv4f32, + FMAXv8f16, + FMINDrr, + FMINHrr, + FMINNMDrr, + FMINNMHrr, + FMINNMP_ZPmZZ_D, + FMINNMP_ZPmZZ_H, + FMINNMP_ZPmZZ_S, + FMINNMPv2f32, + FMINNMPv2f64, + FMINNMPv2i16p, + FMINNMPv2i32p, + FMINNMPv2i64p, + FMINNMPv4f16, + FMINNMPv4f32, + FMINNMPv8f16, + FMINNMQV_D, + FMINNMQV_H, + FMINNMQV_S, + FMINNMSrr, + FMINNMV_VPZ_D, + FMINNMV_VPZ_H, + FMINNMV_VPZ_S, + FMINNMVv4i16v, + FMINNMVv4i32v, + FMINNMVv8i16v, + FMINNM_VG2_2Z2Z_D, + FMINNM_VG2_2Z2Z_H, + FMINNM_VG2_2Z2Z_S, + FMINNM_VG2_2ZZ_D, + FMINNM_VG2_2ZZ_H, + FMINNM_VG2_2ZZ_S, + FMINNM_VG4_4Z4Z_D, + FMINNM_VG4_4Z4Z_H, + FMINNM_VG4_4Z4Z_S, + FMINNM_VG4_4ZZ_D, + FMINNM_VG4_4ZZ_H, + FMINNM_VG4_4ZZ_S, + FMINNM_ZPmI_D, + FMINNM_ZPmI_H, + FMINNM_ZPmI_S, + FMINNM_ZPmZ_D, + FMINNM_ZPmZ_H, + FMINNM_ZPmZ_S, + FMINNMv2f32, + FMINNMv2f64, + FMINNMv4f16, + FMINNMv4f32, + FMINNMv8f16, + FMINP_ZPmZZ_D, + FMINP_ZPmZZ_H, + FMINP_ZPmZZ_S, + FMINPv2f32, + FMINPv2f64, + FMINPv2i16p, + FMINPv2i32p, + FMINPv2i64p, + FMINPv4f16, + FMINPv4f32, + FMINPv8f16, + FMINQV_D, + FMINQV_H, + FMINQV_S, + FMINSrr, + FMINV_VPZ_D, + FMINV_VPZ_H, + FMINV_VPZ_S, + FMINVv4i16v, + FMINVv4i32v, + FMINVv8i16v, + FMIN_VG2_2Z2Z_D, + FMIN_VG2_2Z2Z_H, + FMIN_VG2_2Z2Z_S, + FMIN_VG2_2ZZ_D, + FMIN_VG2_2ZZ_H, + FMIN_VG2_2ZZ_S, + FMIN_VG4_4Z4Z_D, + FMIN_VG4_4Z4Z_H, + FMIN_VG4_4Z4Z_S, + FMIN_VG4_4ZZ_D, + FMIN_VG4_4ZZ_H, + FMIN_VG4_4ZZ_S, + FMIN_ZPmI_D, + FMIN_ZPmI_H, + FMIN_ZPmI_S, + FMIN_ZPmZ_D, + FMIN_ZPmZ_H, + FMIN_ZPmZ_S, + FMINv2f32, + FMINv2f64, + FMINv4f16, + FMINv4f32, + FMINv8f16, + FMLAL2lanev4f16, + FMLAL2lanev8f16, + FMLAL2v4f16, + FMLAL2v8f16, + FMLALB_ZZZ, + FMLALB_ZZZI, + FMLALB_ZZZI_SHH, + FMLALB_ZZZ_SHH, + FMLALBlanev8f16, + FMLALBv16i8_v8f16, + FMLALLBB_ZZZ, + FMLALLBB_ZZZI, + FMLALLBBlanev4f32, + FMLALLBBv4f32, + FMLALLBT_ZZZ, + FMLALLBT_ZZZI, + FMLALLBTlanev4f32, + FMLALLBTv4f32, + FMLALLTB_ZZZ, + FMLALLTB_ZZZI, + FMLALLTBlanev4f32, + FMLALLTBv4f32, + FMLALLTT_ZZZ, + FMLALLTT_ZZZI, + FMLALLTTlanev4f32, + FMLALLTTv4f32, + FMLALL_MZZI_BtoS, + FMLALL_MZZ_BtoS, + FMLALL_VG2_M2Z2Z_BtoS, + FMLALL_VG2_M2ZZI_BtoS, + FMLALL_VG2_M2ZZ_BtoS, + FMLALL_VG4_M4Z4Z_BtoS, + FMLALL_VG4_M4ZZI_BtoS, + FMLALL_VG4_M4ZZ_BtoS, + FMLALT_ZZZ, + FMLALT_ZZZI, + FMLALT_ZZZI_SHH, + FMLALT_ZZZ_SHH, + FMLALTlanev8f16, + FMLALTv16i8_v8f16, + FMLAL_MZZI_BtoH, + FMLAL_MZZI_HtoS, + FMLAL_MZZ_HtoS, + FMLAL_VG2_M2Z2Z_BtoH, + FMLAL_VG2_M2Z2Z_HtoS, + FMLAL_VG2_M2ZZI_BtoH, + FMLAL_VG2_M2ZZI_HtoS, + FMLAL_VG2_M2ZZ_BtoH, + FMLAL_VG2_M2ZZ_HtoS, + FMLAL_VG2_MZZ_BtoH, + FMLAL_VG4_M4Z4Z_BtoH, + FMLAL_VG4_M4Z4Z_HtoS, + FMLAL_VG4_M4ZZI_BtoH, + FMLAL_VG4_M4ZZI_HtoS, + FMLAL_VG4_M4ZZ_BtoH, + FMLAL_VG4_M4ZZ_HtoS, + FMLALlanev4f16, + FMLALlanev8f16, + FMLALv4f16, + FMLALv8f16, + FMLA_VG2_M2Z2Z_D, + FMLA_VG2_M2Z2Z_H, + FMLA_VG2_M2Z2Z_S, + FMLA_VG2_M2ZZI_D, + FMLA_VG2_M2ZZI_H, + FMLA_VG2_M2ZZI_S, + FMLA_VG2_M2ZZ_D, + FMLA_VG2_M2ZZ_H, + FMLA_VG2_M2ZZ_S, + FMLA_VG4_M4Z4Z_D, + FMLA_VG4_M4Z4Z_H, + FMLA_VG4_M4Z4Z_S, + FMLA_VG4_M4ZZI_D, + FMLA_VG4_M4ZZI_H, + FMLA_VG4_M4ZZI_S, + FMLA_VG4_M4ZZ_D, + FMLA_VG4_M4ZZ_H, + FMLA_VG4_M4ZZ_S, + FMLA_ZPmZZ_D, + FMLA_ZPmZZ_H, + FMLA_ZPmZZ_S, + FMLA_ZZZI_D, + FMLA_ZZZI_H, + FMLA_ZZZI_S, + FMLAv1i16_indexed, + FMLAv1i32_indexed, + FMLAv1i64_indexed, + FMLAv2f32, + FMLAv2f64, + FMLAv2i32_indexed, + FMLAv2i64_indexed, + FMLAv4f16, + FMLAv4f32, + FMLAv4i16_indexed, + FMLAv4i32_indexed, + FMLAv8f16, + FMLAv8i16_indexed, + FMLLA_ZZZ_HtoS, + FMLSL2lanev4f16, + FMLSL2lanev8f16, + FMLSL2v4f16, + FMLSL2v8f16, + FMLSLB_ZZZI_SHH, + FMLSLB_ZZZ_SHH, + FMLSLT_ZZZI_SHH, + FMLSLT_ZZZ_SHH, + FMLSL_MZZI_HtoS, + FMLSL_MZZ_HtoS, + FMLSL_VG2_M2Z2Z_HtoS, + FMLSL_VG2_M2ZZI_HtoS, + FMLSL_VG2_M2ZZ_HtoS, + FMLSL_VG4_M4Z4Z_HtoS, + FMLSL_VG4_M4ZZI_HtoS, + FMLSL_VG4_M4ZZ_HtoS, + FMLSLlanev4f16, + FMLSLlanev8f16, + FMLSLv4f16, + FMLSLv8f16, + FMLS_VG2_M2Z2Z_D, + FMLS_VG2_M2Z2Z_H, + FMLS_VG2_M2Z2Z_S, + FMLS_VG2_M2ZZI_D, + FMLS_VG2_M2ZZI_H, + FMLS_VG2_M2ZZI_S, + FMLS_VG2_M2ZZ_D, + FMLS_VG2_M2ZZ_H, + FMLS_VG2_M2ZZ_S, + FMLS_VG4_M4Z4Z_D, + FMLS_VG4_M4Z4Z_H, + FMLS_VG4_M4Z4Z_S, + FMLS_VG4_M4ZZI_D, + FMLS_VG4_M4ZZI_H, + FMLS_VG4_M4ZZI_S, + FMLS_VG4_M4ZZ_D, + FMLS_VG4_M4ZZ_H, + FMLS_VG4_M4ZZ_S, + FMLS_ZPmZZ_D, + FMLS_ZPmZZ_H, + FMLS_ZPmZZ_S, + FMLS_ZZZI_D, + FMLS_ZZZI_H, + FMLS_ZZZI_S, + FMLSv1i16_indexed, + FMLSv1i32_indexed, + FMLSv1i64_indexed, + FMLSv2f32, + FMLSv2f64, + FMLSv2i32_indexed, + FMLSv2i64_indexed, + FMLSv4f16, + FMLSv4f32, + FMLSv4i16_indexed, + FMLSv4i32_indexed, + FMLSv8f16, + FMLSv8i16_indexed, + FMMLA_ZZZ_BtoH, + FMMLA_ZZZ_BtoS, + FMMLA_ZZZ_D, + FMMLA_ZZZ_H, + FMMLA_ZZZ_S, + FMMLAv4f32, + FMMLAv8f16, + FMMLAv8f16_v4f32, + FMMLAv8f16_v8f16, + FMOP4A_M2Z2Z_BtoH, + FMOP4A_M2Z2Z_BtoS, + FMOP4A_M2Z2Z_D, + FMOP4A_M2Z2Z_H, + FMOP4A_M2Z2Z_HtoS, + FMOP4A_M2Z2Z_S, + FMOP4A_M2ZZ_BtoH, + FMOP4A_M2ZZ_BtoS, + FMOP4A_M2ZZ_D, + FMOP4A_M2ZZ_H, + FMOP4A_M2ZZ_HtoS, + FMOP4A_M2ZZ_S, + FMOP4A_MZ2Z_BtoH, + FMOP4A_MZ2Z_BtoS, + FMOP4A_MZ2Z_D, + FMOP4A_MZ2Z_H, + FMOP4A_MZ2Z_HtoS, + FMOP4A_MZ2Z_S, + FMOP4A_MZZ_BtoH, + FMOP4A_MZZ_BtoS, + FMOP4A_MZZ_D, + FMOP4A_MZZ_H, + FMOP4A_MZZ_HtoS, + FMOP4A_MZZ_S, + FMOP4S_M2Z2Z_D, + FMOP4S_M2Z2Z_H, + FMOP4S_M2Z2Z_HtoS, + FMOP4S_M2Z2Z_S, + FMOP4S_M2ZZ_D, + FMOP4S_M2ZZ_H, + FMOP4S_M2ZZ_HtoS, + FMOP4S_M2ZZ_S, + FMOP4S_MZ2Z_D, + FMOP4S_MZ2Z_H, + FMOP4S_MZ2Z_HtoS, + FMOP4S_MZ2Z_S, + FMOP4S_MZZ_D, + FMOP4S_MZZ_H, + FMOP4S_MZZ_HtoS, + FMOP4S_MZZ_S, + FMOPAL_MPPZZ, + FMOPA_MPPZZ_BtoH, + FMOPA_MPPZZ_BtoS, + FMOPA_MPPZZ_D, + FMOPA_MPPZZ_H, + FMOPA_MPPZZ_S, + FMOPSL_MPPZZ, + FMOPS_MPPZZ_D, + FMOPS_MPPZZ_H, + FMOPS_MPPZZ_S, + FMOVDXHighr, + FMOVDXr, + FMOVDi, + FMOVDr, + FMOVHWr, + FMOVHXr, + FMOVHi, + FMOVHr, + FMOVSWr, + FMOVSi, + FMOVSr, + FMOVWHr, + FMOVWSr, + FMOVXDHighr, + FMOVXDr, + FMOVXHr, + FMOVv2f32_ns, + FMOVv2f64_ns, + FMOVv4f16_ns, + FMOVv4f32_ns, + FMOVv8f16_ns, + FMSB_ZPmZZ_D, + FMSB_ZPmZZ_H, + FMSB_ZPmZZ_S, + FMSUBDrrr, + FMSUBHrrr, + FMSUBSrrr, + FMULDrr, + FMULHrr, + FMULSrr, + FMULX16, + FMULX32, + FMULX64, + FMULX_ZPmZ_D, + FMULX_ZPmZ_H, + FMULX_ZPmZ_S, + FMULXv1i16_indexed, + FMULXv1i32_indexed, + FMULXv1i64_indexed, + FMULXv2f32, + FMULXv2f64, + FMULXv2i32_indexed, + FMULXv2i64_indexed, + FMULXv4f16, + FMULXv4f32, + FMULXv4i16_indexed, + FMULXv4i32_indexed, + FMULXv8f16, + FMULXv8i16_indexed, + FMUL_2Z2Z_D, + FMUL_2Z2Z_H, + FMUL_2Z2Z_S, + FMUL_2ZZ_D, + FMUL_2ZZ_H, + FMUL_2ZZ_S, + FMUL_4Z4Z_D, + FMUL_4Z4Z_H, + FMUL_4Z4Z_S, + FMUL_4ZZ_D, + FMUL_4ZZ_H, + FMUL_4ZZ_S, + FMUL_ZPmI_D, + FMUL_ZPmI_H, + FMUL_ZPmI_S, + FMUL_ZPmZ_D, + FMUL_ZPmZ_H, + FMUL_ZPmZ_S, + FMUL_ZZZI_D, + FMUL_ZZZI_H, + FMUL_ZZZI_S, + FMUL_ZZZ_D, + FMUL_ZZZ_H, + FMUL_ZZZ_S, + FMULv1i16_indexed, + FMULv1i32_indexed, + FMULv1i64_indexed, + FMULv2f32, + FMULv2f64, + FMULv2i32_indexed, + FMULv2i64_indexed, + FMULv4f16, + FMULv4f32, + FMULv4i16_indexed, + FMULv4i32_indexed, + FMULv8f16, + FMULv8i16_indexed, + FNEGDr, + FNEGHr, + FNEGSr, + FNEG_ZPmZ_D, + FNEG_ZPmZ_H, + FNEG_ZPmZ_S, + FNEG_ZPzZ_D, + FNEG_ZPzZ_H, + FNEG_ZPzZ_S, + FNEGv2f32, + FNEGv2f64, + FNEGv4f16, + FNEGv4f32, + FNEGv8f16, + FNMADDDrrr, + FNMADDHrrr, + FNMADDSrrr, + FNMAD_ZPmZZ_D, + FNMAD_ZPmZZ_H, + FNMAD_ZPmZZ_S, + FNMLA_ZPmZZ_D, + FNMLA_ZPmZZ_H, + FNMLA_ZPmZZ_S, + FNMLS_ZPmZZ_D, + FNMLS_ZPmZZ_H, + FNMLS_ZPmZZ_S, + FNMSB_ZPmZZ_D, + FNMSB_ZPmZZ_H, + FNMSB_ZPmZZ_S, + FNMSUBDrrr, + FNMSUBHrrr, + FNMSUBSrrr, + FNMULDrr, + FNMULHrr, + FNMULSrr, + FRECPE_ZZ_D, + FRECPE_ZZ_H, + FRECPE_ZZ_S, + FRECPEv1f16, + FRECPEv1i32, + FRECPEv1i64, + FRECPEv2f32, + FRECPEv2f64, + FRECPEv4f16, + FRECPEv4f32, + FRECPEv8f16, + FRECPS16, + FRECPS32, + FRECPS64, + FRECPS_ZZZ_D, + FRECPS_ZZZ_H, + FRECPS_ZZZ_S, + FRECPSv2f32, + FRECPSv2f64, + FRECPSv4f16, + FRECPSv4f32, + FRECPSv8f16, + FRECPX_ZPmZ_D, + FRECPX_ZPmZ_H, + FRECPX_ZPmZ_S, + FRECPX_ZPzZ_D, + FRECPX_ZPzZ_H, + FRECPX_ZPzZ_S, + FRECPXv1f16, + FRECPXv1i32, + FRECPXv1i64, + FRINT32XDr, + FRINT32XSr, + FRINT32X_ZPmZ_D, + FRINT32X_ZPmZ_S, + FRINT32X_ZPzZ_D, + FRINT32X_ZPzZ_S, + FRINT32Xv2f32, + FRINT32Xv2f64, + FRINT32Xv4f32, + FRINT32ZDr, + FRINT32ZSr, + FRINT32Z_ZPmZ_D, + FRINT32Z_ZPmZ_S, + FRINT32Z_ZPzZ_D, + FRINT32Z_ZPzZ_S, + FRINT32Zv2f32, + FRINT32Zv2f64, + FRINT32Zv4f32, + FRINT64XDr, + FRINT64XSr, + FRINT64X_ZPmZ_D, + FRINT64X_ZPmZ_S, + FRINT64X_ZPzZ_D, + FRINT64X_ZPzZ_S, + FRINT64Xv2f32, + FRINT64Xv2f64, + FRINT64Xv4f32, + FRINT64ZDr, + FRINT64ZSr, + FRINT64Z_ZPmZ_D, + FRINT64Z_ZPmZ_S, + FRINT64Z_ZPzZ_D, + FRINT64Z_ZPzZ_S, + FRINT64Zv2f32, + FRINT64Zv2f64, + FRINT64Zv4f32, + FRINTADr, + FRINTAHr, + FRINTASr, + FRINTA_2Z2Z_S, + FRINTA_4Z4Z_S, + FRINTA_ZPmZ_D, + FRINTA_ZPmZ_H, + FRINTA_ZPmZ_S, + FRINTA_ZPzZ_D, + FRINTA_ZPzZ_H, + FRINTA_ZPzZ_S, + FRINTAv2f32, + FRINTAv2f64, + FRINTAv4f16, + FRINTAv4f32, + FRINTAv8f16, + FRINTIDr, + FRINTIHr, + FRINTISr, + FRINTI_ZPmZ_D, + FRINTI_ZPmZ_H, + FRINTI_ZPmZ_S, + FRINTI_ZPzZ_D, + FRINTI_ZPzZ_H, + FRINTI_ZPzZ_S, + FRINTIv2f32, + FRINTIv2f64, + FRINTIv4f16, + FRINTIv4f32, + FRINTIv8f16, + FRINTMDr, + FRINTMHr, + FRINTMSr, + FRINTM_2Z2Z_S, + FRINTM_4Z4Z_S, + FRINTM_ZPmZ_D, + FRINTM_ZPmZ_H, + FRINTM_ZPmZ_S, + FRINTM_ZPzZ_D, + FRINTM_ZPzZ_H, + FRINTM_ZPzZ_S, + FRINTMv2f32, + FRINTMv2f64, + FRINTMv4f16, + FRINTMv4f32, + FRINTMv8f16, + FRINTNDr, + FRINTNHr, + FRINTNSr, + FRINTN_2Z2Z_S, + FRINTN_4Z4Z_S, + FRINTN_ZPmZ_D, + FRINTN_ZPmZ_H, + FRINTN_ZPmZ_S, + FRINTN_ZPzZ_D, + FRINTN_ZPzZ_H, + FRINTN_ZPzZ_S, + FRINTNv2f32, + FRINTNv2f64, + FRINTNv4f16, + FRINTNv4f32, + FRINTNv8f16, + FRINTPDr, + FRINTPHr, + FRINTPSr, + FRINTP_2Z2Z_S, + FRINTP_4Z4Z_S, + FRINTP_ZPmZ_D, + FRINTP_ZPmZ_H, + FRINTP_ZPmZ_S, + FRINTP_ZPzZ_D, + FRINTP_ZPzZ_H, + FRINTP_ZPzZ_S, + FRINTPv2f32, + FRINTPv2f64, + FRINTPv4f16, + FRINTPv4f32, + FRINTPv8f16, + FRINTXDr, + FRINTXHr, + FRINTXSr, + FRINTX_ZPmZ_D, + FRINTX_ZPmZ_H, + FRINTX_ZPmZ_S, + FRINTX_ZPzZ_D, + FRINTX_ZPzZ_H, + FRINTX_ZPzZ_S, + FRINTXv2f32, + FRINTXv2f64, + FRINTXv4f16, + FRINTXv4f32, + FRINTXv8f16, + FRINTZDr, + FRINTZHr, + FRINTZSr, + FRINTZ_ZPmZ_D, + FRINTZ_ZPmZ_H, + FRINTZ_ZPmZ_S, + FRINTZ_ZPzZ_D, + FRINTZ_ZPzZ_H, + FRINTZ_ZPzZ_S, + FRINTZv2f32, + FRINTZv2f64, + FRINTZv4f16, + FRINTZv4f32, + FRINTZv8f16, + FRSQRTE_ZZ_D, + FRSQRTE_ZZ_H, + FRSQRTE_ZZ_S, + FRSQRTEv1f16, + FRSQRTEv1i32, + FRSQRTEv1i64, + FRSQRTEv2f32, + FRSQRTEv2f64, + FRSQRTEv4f16, + FRSQRTEv4f32, + FRSQRTEv8f16, + FRSQRTS16, + FRSQRTS32, + FRSQRTS64, + FRSQRTS_ZZZ_D, + FRSQRTS_ZZZ_H, + FRSQRTS_ZZZ_S, + FRSQRTSv2f32, + FRSQRTSv2f64, + FRSQRTSv4f16, + FRSQRTSv4f32, + FRSQRTSv8f16, + FSCALE_2Z2Z_D, + FSCALE_2Z2Z_H, + FSCALE_2Z2Z_S, + FSCALE_2ZZ_D, + FSCALE_2ZZ_H, + FSCALE_2ZZ_S, + FSCALE_4Z4Z_D, + FSCALE_4Z4Z_H, + FSCALE_4Z4Z_S, + FSCALE_4ZZ_D, + FSCALE_4ZZ_H, + FSCALE_4ZZ_S, + FSCALE_ZPmZ_D, + FSCALE_ZPmZ_H, + FSCALE_ZPmZ_S, + FSCALEv2f32, + FSCALEv2f64, + FSCALEv4f16, + FSCALEv4f32, + FSCALEv8f16, + FSQRTDr, + FSQRTHr, + FSQRTSr, + FSQRT_ZPZz_D, + FSQRT_ZPZz_H, + FSQRT_ZPZz_S, + FSQRT_ZPmZ_D, + FSQRT_ZPmZ_H, + FSQRT_ZPmZ_S, + FSQRTv2f32, + FSQRTv2f64, + FSQRTv4f16, + FSQRTv4f32, + FSQRTv8f16, + FSUBDrr, + FSUBHrr, + FSUBR_ZPmI_D, + FSUBR_ZPmI_H, + FSUBR_ZPmI_S, + FSUBR_ZPmZ_D, + FSUBR_ZPmZ_H, + FSUBR_ZPmZ_S, + FSUBSrr, + FSUB_VG2_M2Z_D, + FSUB_VG2_M2Z_H, + FSUB_VG2_M2Z_S, + FSUB_VG4_M4Z_D, + FSUB_VG4_M4Z_H, + FSUB_VG4_M4Z_S, + FSUB_ZPmI_D, + FSUB_ZPmI_H, + FSUB_ZPmI_S, + FSUB_ZPmZ_D, + FSUB_ZPmZ_H, + FSUB_ZPmZ_S, + FSUB_ZZZ_D, + FSUB_ZZZ_H, + FSUB_ZZZ_S, + FSUBv2f32, + FSUBv2f64, + FSUBv4f16, + FSUBv4f32, + FSUBv8f16, + FTMAD_ZZI_D, + FTMAD_ZZI_H, + FTMAD_ZZI_S, + FTMOPA_M2ZZZI_BtoH, + FTMOPA_M2ZZZI_BtoS, + FTMOPA_M2ZZZI_HtoH, + FTMOPA_M2ZZZI_HtoS, + FTMOPA_M2ZZZI_StoS, + FTSMUL_ZZZ_D, + FTSMUL_ZZZ_H, + FTSMUL_ZZZ_S, + FTSSEL_ZZZ_D, + FTSSEL_ZZZ_H, + FTSSEL_ZZZ_S, + FVDOTB_VG4_M2ZZI_BtoS, + FVDOTT_VG4_M2ZZI_BtoS, + FVDOT_VG2_M2ZZI_BtoH, + FVDOT_VG2_M2ZZI_HtoS, + GCSPOPCX, + GCSPOPM, + GCSPOPX, + GCSPUSHM, + GCSPUSHX, + GCSSS1, + GCSSS2, + GCSSTR, + GCSSTTR, + GLD1B_D, + GLD1B_D_IMM, + GLD1B_D_SXTW, + GLD1B_D_UXTW, + GLD1B_S_IMM, + GLD1B_S_SXTW, + GLD1B_S_UXTW, + GLD1D, + GLD1D_IMM, + GLD1D_SCALED, + GLD1D_SXTW, + GLD1D_SXTW_SCALED, + GLD1D_UXTW, + GLD1D_UXTW_SCALED, + GLD1H_D, + GLD1H_D_IMM, + GLD1H_D_SCALED, + GLD1H_D_SXTW, + GLD1H_D_SXTW_SCALED, + GLD1H_D_UXTW, + GLD1H_D_UXTW_SCALED, + GLD1H_S_IMM, + GLD1H_S_SXTW, + GLD1H_S_SXTW_SCALED, + GLD1H_S_UXTW, + GLD1H_S_UXTW_SCALED, + GLD1Q, + GLD1SB_D, + GLD1SB_D_IMM, + GLD1SB_D_SXTW, + GLD1SB_D_UXTW, + GLD1SB_S_IMM, + GLD1SB_S_SXTW, + GLD1SB_S_UXTW, + GLD1SH_D, + GLD1SH_D_IMM, + GLD1SH_D_SCALED, + GLD1SH_D_SXTW, + GLD1SH_D_SXTW_SCALED, + GLD1SH_D_UXTW, + GLD1SH_D_UXTW_SCALED, + GLD1SH_S_IMM, + GLD1SH_S_SXTW, + GLD1SH_S_SXTW_SCALED, + GLD1SH_S_UXTW, + GLD1SH_S_UXTW_SCALED, + GLD1SW_D, + GLD1SW_D_IMM, + GLD1SW_D_SCALED, + GLD1SW_D_SXTW, + GLD1SW_D_SXTW_SCALED, + GLD1SW_D_UXTW, + GLD1SW_D_UXTW_SCALED, + GLD1W_D, + GLD1W_D_IMM, + GLD1W_D_SCALED, + GLD1W_D_SXTW, + GLD1W_D_SXTW_SCALED, + GLD1W_D_UXTW, + GLD1W_D_UXTW_SCALED, + GLD1W_IMM, + GLD1W_SXTW, + GLD1W_SXTW_SCALED, + GLD1W_UXTW, + GLD1W_UXTW_SCALED, + GLDFF1B_D, + GLDFF1B_D_IMM, + GLDFF1B_D_SXTW, + GLDFF1B_D_UXTW, + GLDFF1B_S_IMM, + GLDFF1B_S_SXTW, + GLDFF1B_S_UXTW, + GLDFF1D, + GLDFF1D_IMM, + GLDFF1D_SCALED, + GLDFF1D_SXTW, + GLDFF1D_SXTW_SCALED, + GLDFF1D_UXTW, + GLDFF1D_UXTW_SCALED, + GLDFF1H_D, + GLDFF1H_D_IMM, + GLDFF1H_D_SCALED, + GLDFF1H_D_SXTW, + GLDFF1H_D_SXTW_SCALED, + GLDFF1H_D_UXTW, + GLDFF1H_D_UXTW_SCALED, + GLDFF1H_S_IMM, + GLDFF1H_S_SXTW, + GLDFF1H_S_SXTW_SCALED, + GLDFF1H_S_UXTW, + GLDFF1H_S_UXTW_SCALED, + GLDFF1SB_D, + GLDFF1SB_D_IMM, + GLDFF1SB_D_SXTW, + GLDFF1SB_D_UXTW, + GLDFF1SB_S_IMM, + GLDFF1SB_S_SXTW, + GLDFF1SB_S_UXTW, + GLDFF1SH_D, + GLDFF1SH_D_IMM, + GLDFF1SH_D_SCALED, + GLDFF1SH_D_SXTW, + GLDFF1SH_D_SXTW_SCALED, + GLDFF1SH_D_UXTW, + GLDFF1SH_D_UXTW_SCALED, + GLDFF1SH_S_IMM, + GLDFF1SH_S_SXTW, + GLDFF1SH_S_SXTW_SCALED, + GLDFF1SH_S_UXTW, + GLDFF1SH_S_UXTW_SCALED, + GLDFF1SW_D, + GLDFF1SW_D_IMM, + GLDFF1SW_D_SCALED, + GLDFF1SW_D_SXTW, + GLDFF1SW_D_SXTW_SCALED, + GLDFF1SW_D_UXTW, + GLDFF1SW_D_UXTW_SCALED, + GLDFF1W_D, + GLDFF1W_D_IMM, + GLDFF1W_D_SCALED, + GLDFF1W_D_SXTW, + GLDFF1W_D_SXTW_SCALED, + GLDFF1W_D_UXTW, + GLDFF1W_D_UXTW_SCALED, + GLDFF1W_IMM, + GLDFF1W_SXTW, + GLDFF1W_SXTW_SCALED, + GLDFF1W_UXTW, + GLDFF1W_UXTW_SCALED, + GMI, + HINT, + HISTCNT_ZPzZZ_D, + HISTCNT_ZPzZZ_S, + HISTSEG_ZZZ, + HLT, + HVC, + INCB_XPiI, + INCD_XPiI, + INCD_ZPiI, + INCH_XPiI, + INCH_ZPiI, + INCP_XP_B, + INCP_XP_D, + INCP_XP_H, + INCP_XP_S, + INCP_ZP_D, + INCP_ZP_H, + INCP_ZP_S, + INCW_XPiI, + INCW_ZPiI, + INDEX_II_B, + INDEX_II_D, + INDEX_II_H, + INDEX_II_S, + INDEX_IR_B, + INDEX_IR_D, + INDEX_IR_H, + INDEX_IR_S, + INDEX_RI_B, + INDEX_RI_D, + INDEX_RI_H, + INDEX_RI_S, + INDEX_RR_B, + INDEX_RR_D, + INDEX_RR_H, + INDEX_RR_S, + INSERT_MXIPZ_H_B, + INSERT_MXIPZ_H_D, + INSERT_MXIPZ_H_H, + INSERT_MXIPZ_H_Q, + INSERT_MXIPZ_H_S, + INSERT_MXIPZ_V_B, + INSERT_MXIPZ_V_D, + INSERT_MXIPZ_V_H, + INSERT_MXIPZ_V_Q, + INSERT_MXIPZ_V_S, + INSR_ZR_B, + INSR_ZR_D, + INSR_ZR_H, + INSR_ZR_S, + INSR_ZV_B, + INSR_ZV_D, + INSR_ZV_H, + INSR_ZV_S, + INSvi16gpr, + INSvi16lane, + INSvi32gpr, + INSvi32lane, + INSvi64gpr, + INSvi64lane, + INSvi8gpr, + INSvi8lane, + IRG, + ISB, + LASTA_RPZ_B, + LASTA_RPZ_D, + LASTA_RPZ_H, + LASTA_RPZ_S, + LASTA_VPZ_B, + LASTA_VPZ_D, + LASTA_VPZ_H, + LASTA_VPZ_S, + LASTB_RPZ_B, + LASTB_RPZ_D, + LASTB_RPZ_H, + LASTB_RPZ_S, + LASTB_VPZ_B, + LASTB_VPZ_D, + LASTB_VPZ_H, + LASTB_VPZ_S, + LASTP_XPP_B, + LASTP_XPP_D, + LASTP_XPP_H, + LASTP_XPP_S, + LD1B, + LD1B_2Z, + LD1B_2Z_IMM, + LD1B_2Z_STRIDED, + LD1B_2Z_STRIDED_IMM, + LD1B_4Z, + LD1B_4Z_IMM, + LD1B_4Z_STRIDED, + LD1B_4Z_STRIDED_IMM, + LD1B_D, + LD1B_D_IMM, + LD1B_H, + LD1B_H_IMM, + LD1B_IMM, + LD1B_S, + LD1B_S_IMM, + LD1D, + LD1D_2Z, + LD1D_2Z_IMM, + LD1D_2Z_STRIDED, + LD1D_2Z_STRIDED_IMM, + LD1D_4Z, + LD1D_4Z_IMM, + LD1D_4Z_STRIDED, + LD1D_4Z_STRIDED_IMM, + LD1D_IMM, + LD1D_Q, + LD1D_Q_IMM, + LD1Fourv16b, + LD1Fourv16b_POST, + LD1Fourv1d, + LD1Fourv1d_POST, + LD1Fourv2d, + LD1Fourv2d_POST, + LD1Fourv2s, + LD1Fourv2s_POST, + LD1Fourv4h, + LD1Fourv4h_POST, + LD1Fourv4s, + LD1Fourv4s_POST, + LD1Fourv8b, + LD1Fourv8b_POST, + LD1Fourv8h, + LD1Fourv8h_POST, + LD1H, + LD1H_2Z, + LD1H_2Z_IMM, + LD1H_2Z_STRIDED, + LD1H_2Z_STRIDED_IMM, + LD1H_4Z, + LD1H_4Z_IMM, + LD1H_4Z_STRIDED, + LD1H_4Z_STRIDED_IMM, + LD1H_D, + LD1H_D_IMM, + LD1H_IMM, + LD1H_S, + LD1H_S_IMM, + LD1Onev16b, + LD1Onev16b_POST, + LD1Onev1d, + LD1Onev1d_POST, + LD1Onev2d, + LD1Onev2d_POST, + LD1Onev2s, + LD1Onev2s_POST, + LD1Onev4h, + LD1Onev4h_POST, + LD1Onev4s, + LD1Onev4s_POST, + LD1Onev8b, + LD1Onev8b_POST, + LD1Onev8h, + LD1Onev8h_POST, + LD1RB_D_IMM, + LD1RB_H_IMM, + LD1RB_IMM, + LD1RB_S_IMM, + LD1RD_IMM, + LD1RH_D_IMM, + LD1RH_IMM, + LD1RH_S_IMM, + LD1RO_B, + LD1RO_B_IMM, + LD1RO_D, + LD1RO_D_IMM, + LD1RO_H, + LD1RO_H_IMM, + LD1RO_W, + LD1RO_W_IMM, + LD1RQ_B, + LD1RQ_B_IMM, + LD1RQ_D, + LD1RQ_D_IMM, + LD1RQ_H, + LD1RQ_H_IMM, + LD1RQ_W, + LD1RQ_W_IMM, + LD1RSB_D_IMM, + LD1RSB_H_IMM, + LD1RSB_S_IMM, + LD1RSH_D_IMM, + LD1RSH_S_IMM, + LD1RSW_IMM, + LD1RW_D_IMM, + LD1RW_IMM, + LD1Rv16b, + LD1Rv16b_POST, + LD1Rv1d, + LD1Rv1d_POST, + LD1Rv2d, + LD1Rv2d_POST, + LD1Rv2s, + LD1Rv2s_POST, + LD1Rv4h, + LD1Rv4h_POST, + LD1Rv4s, + LD1Rv4s_POST, + LD1Rv8b, + LD1Rv8b_POST, + LD1Rv8h, + LD1Rv8h_POST, + LD1SB_D, + LD1SB_D_IMM, + LD1SB_H, + LD1SB_H_IMM, + LD1SB_S, + LD1SB_S_IMM, + LD1SH_D, + LD1SH_D_IMM, + LD1SH_S, + LD1SH_S_IMM, + LD1SW_D, + LD1SW_D_IMM, + LD1Threev16b, + LD1Threev16b_POST, + LD1Threev1d, + LD1Threev1d_POST, + LD1Threev2d, + LD1Threev2d_POST, + LD1Threev2s, + LD1Threev2s_POST, + LD1Threev4h, + LD1Threev4h_POST, + LD1Threev4s, + LD1Threev4s_POST, + LD1Threev8b, + LD1Threev8b_POST, + LD1Threev8h, + LD1Threev8h_POST, + LD1Twov16b, + LD1Twov16b_POST, + LD1Twov1d, + LD1Twov1d_POST, + LD1Twov2d, + LD1Twov2d_POST, + LD1Twov2s, + LD1Twov2s_POST, + LD1Twov4h, + LD1Twov4h_POST, + LD1Twov4s, + LD1Twov4s_POST, + LD1Twov8b, + LD1Twov8b_POST, + LD1Twov8h, + LD1Twov8h_POST, + LD1W, + LD1W_2Z, + LD1W_2Z_IMM, + LD1W_2Z_STRIDED, + LD1W_2Z_STRIDED_IMM, + LD1W_4Z, + LD1W_4Z_IMM, + LD1W_4Z_STRIDED, + LD1W_4Z_STRIDED_IMM, + LD1W_D, + LD1W_D_IMM, + LD1W_IMM, + LD1W_Q, + LD1W_Q_IMM, + LD1_MXIPXX_H_B, + LD1_MXIPXX_H_D, + LD1_MXIPXX_H_H, + LD1_MXIPXX_H_Q, + LD1_MXIPXX_H_S, + LD1_MXIPXX_V_B, + LD1_MXIPXX_V_D, + LD1_MXIPXX_V_H, + LD1_MXIPXX_V_Q, + LD1_MXIPXX_V_S, + LD1i16, + LD1i16_POST, + LD1i32, + LD1i32_POST, + LD1i64, + LD1i64_POST, + LD1i8, + LD1i8_POST, + LD2B, + LD2B_IMM, + LD2D, + LD2D_IMM, + LD2H, + LD2H_IMM, + LD2Q, + LD2Q_IMM, + LD2Rv16b, + LD2Rv16b_POST, + LD2Rv1d, + LD2Rv1d_POST, + LD2Rv2d, + LD2Rv2d_POST, + LD2Rv2s, + LD2Rv2s_POST, + LD2Rv4h, + LD2Rv4h_POST, + LD2Rv4s, + LD2Rv4s_POST, + LD2Rv8b, + LD2Rv8b_POST, + LD2Rv8h, + LD2Rv8h_POST, + LD2Twov16b, + LD2Twov16b_POST, + LD2Twov2d, + LD2Twov2d_POST, + LD2Twov2s, + LD2Twov2s_POST, + LD2Twov4h, + LD2Twov4h_POST, + LD2Twov4s, + LD2Twov4s_POST, + LD2Twov8b, + LD2Twov8b_POST, + LD2Twov8h, + LD2Twov8h_POST, + LD2W, + LD2W_IMM, + LD2i16, + LD2i16_POST, + LD2i32, + LD2i32_POST, + LD2i64, + LD2i64_POST, + LD2i8, + LD2i8_POST, + LD3B, + LD3B_IMM, + LD3D, + LD3D_IMM, + LD3H, + LD3H_IMM, + LD3Q, + LD3Q_IMM, + LD3Rv16b, + LD3Rv16b_POST, + LD3Rv1d, + LD3Rv1d_POST, + LD3Rv2d, + LD3Rv2d_POST, + LD3Rv2s, + LD3Rv2s_POST, + LD3Rv4h, + LD3Rv4h_POST, + LD3Rv4s, + LD3Rv4s_POST, + LD3Rv8b, + LD3Rv8b_POST, + LD3Rv8h, + LD3Rv8h_POST, + LD3Threev16b, + LD3Threev16b_POST, + LD3Threev2d, + LD3Threev2d_POST, + LD3Threev2s, + LD3Threev2s_POST, + LD3Threev4h, + LD3Threev4h_POST, + LD3Threev4s, + LD3Threev4s_POST, + LD3Threev8b, + LD3Threev8b_POST, + LD3Threev8h, + LD3Threev8h_POST, + LD3W, + LD3W_IMM, + LD3i16, + LD3i16_POST, + LD3i32, + LD3i32_POST, + LD3i64, + LD3i64_POST, + LD3i8, + LD3i8_POST, + LD4B, + LD4B_IMM, + LD4D, + LD4D_IMM, + LD4Fourv16b, + LD4Fourv16b_POST, + LD4Fourv2d, + LD4Fourv2d_POST, + LD4Fourv2s, + LD4Fourv2s_POST, + LD4Fourv4h, + LD4Fourv4h_POST, + LD4Fourv4s, + LD4Fourv4s_POST, + LD4Fourv8b, + LD4Fourv8b_POST, + LD4Fourv8h, + LD4Fourv8h_POST, + LD4H, + LD4H_IMM, + LD4Q, + LD4Q_IMM, + LD4Rv16b, + LD4Rv16b_POST, + LD4Rv1d, + LD4Rv1d_POST, + LD4Rv2d, + LD4Rv2d_POST, + LD4Rv2s, + LD4Rv2s_POST, + LD4Rv4h, + LD4Rv4h_POST, + LD4Rv4s, + LD4Rv4s_POST, + LD4Rv8b, + LD4Rv8b_POST, + LD4Rv8h, + LD4Rv8h_POST, + LD4W, + LD4W_IMM, + LD4i16, + LD4i16_POST, + LD4i32, + LD4i32_POST, + LD4i64, + LD4i64_POST, + LD4i8, + LD4i8_POST, + LD64B, + LDADDAB, + LDADDAH, + LDADDALB, + LDADDALH, + LDADDALW, + LDADDALX, + LDADDAW, + LDADDAX, + LDADDB, + LDADDH, + LDADDLB, + LDADDLH, + LDADDLW, + LDADDLX, + LDADDW, + LDADDX, + LDAP1, + LDAPPi, + LDAPRB, + LDAPRH, + LDAPRW, + LDAPRWpost, + LDAPRX, + LDAPRXpost, + LDAPURBi, + LDAPURHi, + LDAPURSBWi, + LDAPURSBXi, + LDAPURSHWi, + LDAPURSHXi, + LDAPURSWi, + LDAPURXi, + LDAPURbi, + LDAPURdi, + LDAPURhi, + LDAPURi, + LDAPURqi, + LDAPURsi, + LDAPi, + LDARB, + LDARH, + LDARW, + LDARX, + LDATXRW, + LDATXRX, + LDAXPW, + LDAXPX, + LDAXRB, + LDAXRH, + LDAXRW, + LDAXRX, + LDBFADD, + LDBFADDA, + LDBFADDAL, + LDBFADDL, + LDBFMAX, + LDBFMAXA, + LDBFMAXAL, + LDBFMAXL, + LDBFMAXNM, + LDBFMAXNMA, + LDBFMAXNMAL, + LDBFMAXNML, + LDBFMIN, + LDBFMINA, + LDBFMINAL, + LDBFMINL, + LDBFMINNM, + LDBFMINNMA, + LDBFMINNMAL, + LDBFMINNML, + LDCLRAB, + LDCLRAH, + LDCLRALB, + LDCLRALH, + LDCLRALW, + LDCLRALX, + LDCLRAW, + LDCLRAX, + LDCLRB, + LDCLRH, + LDCLRLB, + LDCLRLH, + LDCLRLW, + LDCLRLX, + LDCLRP, + LDCLRPA, + LDCLRPAL, + LDCLRPL, + LDCLRW, + LDCLRX, + LDEORAB, + LDEORAH, + LDEORALB, + LDEORALH, + LDEORALW, + LDEORALX, + LDEORAW, + LDEORAX, + LDEORB, + LDEORH, + LDEORLB, + LDEORLH, + LDEORLW, + LDEORLX, + LDEORW, + LDEORX, + LDFADDAD, + LDFADDAH, + LDFADDALD, + LDFADDALH, + LDFADDALS, + LDFADDAS, + LDFADDD, + LDFADDH, + LDFADDLD, + LDFADDLH, + LDFADDLS, + LDFADDS, + LDFF1B, + LDFF1B_D, + LDFF1B_H, + LDFF1B_S, + LDFF1D, + LDFF1H, + LDFF1H_D, + LDFF1H_S, + LDFF1SB_D, + LDFF1SB_H, + LDFF1SB_S, + LDFF1SH_D, + LDFF1SH_S, + LDFF1SW_D, + LDFF1W, + LDFF1W_D, + LDFMAXAD, + LDFMAXAH, + LDFMAXALD, + LDFMAXALH, + LDFMAXALS, + LDFMAXAS, + LDFMAXD, + LDFMAXH, + LDFMAXLD, + LDFMAXLH, + LDFMAXLS, + LDFMAXNMAD, + LDFMAXNMAH, + LDFMAXNMALD, + LDFMAXNMALH, + LDFMAXNMALS, + LDFMAXNMAS, + LDFMAXNMD, + LDFMAXNMH, + LDFMAXNMLD, + LDFMAXNMLH, + LDFMAXNMLS, + LDFMAXNMS, + LDFMAXS, + LDFMINAD, + LDFMINAH, + LDFMINALD, + LDFMINALH, + LDFMINALS, + LDFMINAS, + LDFMIND, + LDFMINH, + LDFMINLD, + LDFMINLH, + LDFMINLS, + LDFMINNMAD, + LDFMINNMAH, + LDFMINNMALD, + LDFMINNMALH, + LDFMINNMALS, + LDFMINNMAS, + LDFMINNMD, + LDFMINNMH, + LDFMINNMLD, + LDFMINNMLH, + LDFMINNMLS, + LDFMINNMS, + LDFMINS, + LDG, + LDGM, + LDIAPPW, + LDIAPPWpost, + LDIAPPX, + LDIAPPXpost, + LDLARB, + LDLARH, + LDLARW, + LDLARX, + LDNF1B_D_IMM, + LDNF1B_H_IMM, + LDNF1B_IMM, + LDNF1B_S_IMM, + LDNF1D_IMM, + LDNF1H_D_IMM, + LDNF1H_IMM, + LDNF1H_S_IMM, + LDNF1SB_D_IMM, + LDNF1SB_H_IMM, + LDNF1SB_S_IMM, + LDNF1SH_D_IMM, + LDNF1SH_S_IMM, + LDNF1SW_D_IMM, + LDNF1W_D_IMM, + LDNF1W_IMM, + LDNPDi, + LDNPQi, + LDNPSi, + LDNPWi, + LDNPXi, + LDNT1B_2Z, + LDNT1B_2Z_IMM, + LDNT1B_2Z_STRIDED, + LDNT1B_2Z_STRIDED_IMM, + LDNT1B_4Z, + LDNT1B_4Z_IMM, + LDNT1B_4Z_STRIDED, + LDNT1B_4Z_STRIDED_IMM, + LDNT1B_ZRI, + LDNT1B_ZRR, + LDNT1B_ZZR_D, + LDNT1B_ZZR_S, + LDNT1D_2Z, + LDNT1D_2Z_IMM, + LDNT1D_2Z_STRIDED, + LDNT1D_2Z_STRIDED_IMM, + LDNT1D_4Z, + LDNT1D_4Z_IMM, + LDNT1D_4Z_STRIDED, + LDNT1D_4Z_STRIDED_IMM, + LDNT1D_ZRI, + LDNT1D_ZRR, + LDNT1D_ZZR_D, + LDNT1H_2Z, + LDNT1H_2Z_IMM, + LDNT1H_2Z_STRIDED, + LDNT1H_2Z_STRIDED_IMM, + LDNT1H_4Z, + LDNT1H_4Z_IMM, + LDNT1H_4Z_STRIDED, + LDNT1H_4Z_STRIDED_IMM, + LDNT1H_ZRI, + LDNT1H_ZRR, + LDNT1H_ZZR_D, + LDNT1H_ZZR_S, + LDNT1SB_ZZR_D, + LDNT1SB_ZZR_S, + LDNT1SH_ZZR_D, + LDNT1SH_ZZR_S, + LDNT1SW_ZZR_D, + LDNT1W_2Z, + LDNT1W_2Z_IMM, + LDNT1W_2Z_STRIDED, + LDNT1W_2Z_STRIDED_IMM, + LDNT1W_4Z, + LDNT1W_4Z_IMM, + LDNT1W_4Z_STRIDED, + LDNT1W_4Z_STRIDED_IMM, + LDNT1W_ZRI, + LDNT1W_ZRR, + LDNT1W_ZZR_D, + LDNT1W_ZZR_S, + LDPDi, + LDPDpost, + LDPDpre, + LDPQi, + LDPQpost, + LDPQpre, + LDPSWi, + LDPSWpost, + LDPSWpre, + LDPSi, + LDPSpost, + LDPSpre, + LDPWi, + LDPWpost, + LDPWpre, + LDPXi, + LDPXpost, + LDPXpre, + LDRAAindexed, + LDRAAwriteback, + LDRABindexed, + LDRABwriteback, + LDRBBpost, + LDRBBpre, + LDRBBroW, + LDRBBroX, + LDRBBui, + LDRBpost, + LDRBpre, + LDRBroW, + LDRBroX, + LDRBui, + LDRDl, + LDRDpost, + LDRDpre, + LDRDroW, + LDRDroX, + LDRDui, + LDRHHpost, + LDRHHpre, + LDRHHroW, + LDRHHroX, + LDRHHui, + LDRHpost, + LDRHpre, + LDRHroW, + LDRHroX, + LDRHui, + LDRQl, + LDRQpost, + LDRQpre, + LDRQroW, + LDRQroX, + LDRQui, + LDRSBWpost, + LDRSBWpre, + LDRSBWroW, + LDRSBWroX, + LDRSBWui, + LDRSBXpost, + LDRSBXpre, + LDRSBXroW, + LDRSBXroX, + LDRSBXui, + LDRSHWpost, + LDRSHWpre, + LDRSHWroW, + LDRSHWroX, + LDRSHWui, + LDRSHXpost, + LDRSHXpre, + LDRSHXroW, + LDRSHXroX, + LDRSHXui, + LDRSWl, + LDRSWpost, + LDRSWpre, + LDRSWroW, + LDRSWroX, + LDRSWui, + LDRSl, + LDRSpost, + LDRSpre, + LDRSroW, + LDRSroX, + LDRSui, + LDRWl, + LDRWpost, + LDRWpre, + LDRWroW, + LDRWroX, + LDRWui, + LDRXl, + LDRXpost, + LDRXpre, + LDRXroW, + LDRXroX, + LDRXui, + LDR_PXI, + LDR_TX, + LDR_ZA, + LDR_ZXI, + LDSETAB, + LDSETAH, + LDSETALB, + LDSETALH, + LDSETALW, + LDSETALX, + LDSETAW, + LDSETAX, + LDSETB, + LDSETH, + LDSETLB, + LDSETLH, + LDSETLW, + LDSETLX, + LDSETP, + LDSETPA, + LDSETPAL, + LDSETPL, + LDSETW, + LDSETX, + LDSMAXAB, + LDSMAXAH, + LDSMAXALB, + LDSMAXALH, + LDSMAXALW, + LDSMAXALX, + LDSMAXAW, + LDSMAXAX, + LDSMAXB, + LDSMAXH, + LDSMAXLB, + LDSMAXLH, + LDSMAXLW, + LDSMAXLX, + LDSMAXW, + LDSMAXX, + LDSMINAB, + LDSMINAH, + LDSMINALB, + LDSMINALH, + LDSMINALW, + LDSMINALX, + LDSMINAW, + LDSMINAX, + LDSMINB, + LDSMINH, + LDSMINLB, + LDSMINLH, + LDSMINLW, + LDSMINLX, + LDSMINW, + LDSMINX, + LDTADDALW, + LDTADDALX, + LDTADDAW, + LDTADDAX, + LDTADDLW, + LDTADDLX, + LDTADDW, + LDTADDX, + LDTCLRALW, + LDTCLRALX, + LDTCLRAW, + LDTCLRAX, + LDTCLRLW, + LDTCLRLX, + LDTCLRW, + LDTCLRX, + LDTNPQi, + LDTNPXi, + LDTPQi, + LDTPQpost, + LDTPQpre, + LDTPi, + LDTPpost, + LDTPpre, + LDTRBi, + LDTRHi, + LDTRSBWi, + LDTRSBXi, + LDTRSHWi, + LDTRSHXi, + LDTRSWi, + LDTRWi, + LDTRXi, + LDTSETALW, + LDTSETALX, + LDTSETAW, + LDTSETAX, + LDTSETLW, + LDTSETLX, + LDTSETW, + LDTSETX, + LDTXRWr, + LDTXRXr, + LDUMAXAB, + LDUMAXAH, + LDUMAXALB, + LDUMAXALH, + LDUMAXALW, + LDUMAXALX, + LDUMAXAW, + LDUMAXAX, + LDUMAXB, + LDUMAXH, + LDUMAXLB, + LDUMAXLH, + LDUMAXLW, + LDUMAXLX, + LDUMAXW, + LDUMAXX, + LDUMINAB, + LDUMINAH, + LDUMINALB, + LDUMINALH, + LDUMINALW, + LDUMINALX, + LDUMINAW, + LDUMINAX, + LDUMINB, + LDUMINH, + LDUMINLB, + LDUMINLH, + LDUMINLW, + LDUMINLX, + LDUMINW, + LDUMINX, + LDURBBi, + LDURBi, + LDURDi, + LDURHHi, + LDURHi, + LDURQi, + LDURSBWi, + LDURSBXi, + LDURSHWi, + LDURSHXi, + LDURSWi, + LDURSi, + LDURWi, + LDURXi, + LDXPW, + LDXPX, + LDXRB, + LDXRH, + LDXRW, + LDXRX, + LSLR_ZPmZ_B, + LSLR_ZPmZ_D, + LSLR_ZPmZ_H, + LSLR_ZPmZ_S, + LSLVWr, + LSLVXr, + LSL_WIDE_ZPmZ_B, + LSL_WIDE_ZPmZ_H, + LSL_WIDE_ZPmZ_S, + LSL_WIDE_ZZZ_B, + LSL_WIDE_ZZZ_H, + LSL_WIDE_ZZZ_S, + LSL_ZPmI_B, + LSL_ZPmI_D, + LSL_ZPmI_H, + LSL_ZPmI_S, + LSL_ZPmZ_B, + LSL_ZPmZ_D, + LSL_ZPmZ_H, + LSL_ZPmZ_S, + LSL_ZZI_B, + LSL_ZZI_D, + LSL_ZZI_H, + LSL_ZZI_S, + LSRR_ZPmZ_B, + LSRR_ZPmZ_D, + LSRR_ZPmZ_H, + LSRR_ZPmZ_S, + LSRVWr, + LSRVXr, + LSR_WIDE_ZPmZ_B, + LSR_WIDE_ZPmZ_H, + LSR_WIDE_ZPmZ_S, + LSR_WIDE_ZZZ_B, + LSR_WIDE_ZZZ_H, + LSR_WIDE_ZZZ_S, + LSR_ZPmI_B, + LSR_ZPmI_D, + LSR_ZPmI_H, + LSR_ZPmI_S, + LSR_ZPmZ_B, + LSR_ZPmZ_D, + LSR_ZPmZ_H, + LSR_ZPmZ_S, + LSR_ZZI_B, + LSR_ZZI_D, + LSR_ZZI_H, + LSR_ZZI_S, + LUT2_B, + LUT2_H, + LUT4_B, + LUT4_H, + LUTI2_2ZTZI_B, + LUTI2_2ZTZI_H, + LUTI2_2ZTZI_S, + LUTI2_4ZTZI_B, + LUTI2_4ZTZI_H, + LUTI2_4ZTZI_S, + LUTI2_S_2ZTZI_B, + LUTI2_S_2ZTZI_H, + LUTI2_S_4ZTZI_B, + LUTI2_S_4ZTZI_H, + LUTI2_ZTZI_B, + LUTI2_ZTZI_H, + LUTI2_ZTZI_S, + LUTI2_ZZZI_B, + LUTI2_ZZZI_H, + LUTI4_2ZTZI_B, + LUTI4_2ZTZI_H, + LUTI4_2ZTZI_S, + LUTI4_4ZTZI_H, + LUTI4_4ZTZI_S, + LUTI4_4ZZT2Z, + LUTI4_S_2ZTZI_B, + LUTI4_S_2ZTZI_H, + LUTI4_S_4ZTZI_H, + LUTI4_S_4ZZT2Z, + LUTI4_Z2ZZI, + LUTI4_ZTZI_B, + LUTI4_ZTZI_H, + LUTI4_ZTZI_S, + LUTI4_ZZZI_B, + LUTI4_ZZZI_H, + LUTI6_4Z2Z2ZI, + LUTI6_4ZT3Z, + LUTI6_S_4Z2Z2ZI, + LUTI6_S_4ZT3Z, + LUTI6_Z2ZZ, + LUTI6_Z2ZZI_H, + LUTI6_ZTZ, + MADDPT, + MADDWrrr, + MADDXrrr, + MAD_CPA, + MAD_ZPmZZ_B, + MAD_ZPmZZ_D, + MAD_ZPmZZ_H, + MAD_ZPmZZ_S, + MATCH_PPzZZ_B, + MATCH_PPzZZ_H, + MLA_CPA, + MLA_ZPmZZ_B, + MLA_ZPmZZ_D, + MLA_ZPmZZ_H, + MLA_ZPmZZ_S, + MLA_ZZZI_D, + MLA_ZZZI_H, + MLA_ZZZI_S, + MLAv16i8, + MLAv2i32, + MLAv2i32_indexed, + MLAv4i16, + MLAv4i16_indexed, + MLAv4i32, + MLAv4i32_indexed, + MLAv8i16, + MLAv8i16_indexed, + MLAv8i8, + MLS_ZPmZZ_B, + MLS_ZPmZZ_D, + MLS_ZPmZZ_H, + MLS_ZPmZZ_S, + MLS_ZZZI_D, + MLS_ZZZI_H, + MLS_ZZZI_S, + MLSv16i8, + MLSv2i32, + MLSv2i32_indexed, + MLSv4i16, + MLSv4i16_indexed, + MLSv4i32, + MLSv4i32_indexed, + MLSv8i16, + MLSv8i16_indexed, + MLSv8i8, + MOPSSETGE, + MOPSSETGEN, + MOPSSETGET, + MOPSSETGETN, + MOVAZ_2ZMI_H_B, + MOVAZ_2ZMI_H_D, + MOVAZ_2ZMI_H_H, + MOVAZ_2ZMI_H_S, + MOVAZ_2ZMI_V_B, + MOVAZ_2ZMI_V_D, + MOVAZ_2ZMI_V_H, + MOVAZ_2ZMI_V_S, + MOVAZ_4ZMI_H_B, + MOVAZ_4ZMI_H_D, + MOVAZ_4ZMI_H_H, + MOVAZ_4ZMI_H_S, + MOVAZ_4ZMI_V_B, + MOVAZ_4ZMI_V_D, + MOVAZ_4ZMI_V_H, + MOVAZ_4ZMI_V_S, + MOVAZ_VG2_2ZMXI, + MOVAZ_VG4_4ZMXI, + MOVAZ_ZMI_H_B, + MOVAZ_ZMI_H_D, + MOVAZ_ZMI_H_H, + MOVAZ_ZMI_H_Q, + MOVAZ_ZMI_H_S, + MOVAZ_ZMI_V_B, + MOVAZ_ZMI_V_D, + MOVAZ_ZMI_V_H, + MOVAZ_ZMI_V_Q, + MOVAZ_ZMI_V_S, + MOVA_2ZMXI_H_B, + MOVA_2ZMXI_H_D, + MOVA_2ZMXI_H_H, + MOVA_2ZMXI_H_S, + MOVA_2ZMXI_V_B, + MOVA_2ZMXI_V_D, + MOVA_2ZMXI_V_H, + MOVA_2ZMXI_V_S, + MOVA_4ZMXI_H_B, + MOVA_4ZMXI_H_D, + MOVA_4ZMXI_H_H, + MOVA_4ZMXI_H_S, + MOVA_4ZMXI_V_B, + MOVA_4ZMXI_V_D, + MOVA_4ZMXI_V_H, + MOVA_4ZMXI_V_S, + MOVA_MXI2Z_H_B, + MOVA_MXI2Z_H_D, + MOVA_MXI2Z_H_H, + MOVA_MXI2Z_H_S, + MOVA_MXI2Z_V_B, + MOVA_MXI2Z_V_D, + MOVA_MXI2Z_V_H, + MOVA_MXI2Z_V_S, + MOVA_MXI4Z_H_B, + MOVA_MXI4Z_H_D, + MOVA_MXI4Z_H_H, + MOVA_MXI4Z_H_S, + MOVA_MXI4Z_V_B, + MOVA_MXI4Z_V_D, + MOVA_MXI4Z_V_H, + MOVA_MXI4Z_V_S, + MOVA_VG2_2ZMXI, + MOVA_VG2_MXI2Z, + MOVA_VG4_4ZMXI, + MOVA_VG4_MXI4Z, + MOVID, + MOVIv16b_ns, + MOVIv2d_ns, + MOVIv2i32, + MOVIv2s_msl, + MOVIv4i16, + MOVIv4i32, + MOVIv4s_msl, + MOVIv8b_ns, + MOVIv8i16, + MOVKWi, + MOVKXi, + MOVNWi, + MOVNXi, + MOVPRFX_ZPmZ_B, + MOVPRFX_ZPmZ_D, + MOVPRFX_ZPmZ_H, + MOVPRFX_ZPmZ_S, + MOVPRFX_ZPzZ_B, + MOVPRFX_ZPzZ_D, + MOVPRFX_ZPzZ_H, + MOVPRFX_ZPzZ_S, + MOVPRFX_ZZ, + MOVT_TIX, + MOVT_TIZ, + MOVT_XTI, + MOVZWi, + MOVZXi, + MRRS, + MRS, + MSB_ZPmZZ_B, + MSB_ZPmZZ_D, + MSB_ZPmZZ_H, + MSB_ZPmZZ_S, + MSR, + MSRR, + MSRpstateImm1, + MSRpstateImm4, + MSRpstatesvcrImm1, + MSUBPT, + MSUBWrrr, + MSUBXrrr, + MUL_ZI_B, + MUL_ZI_D, + MUL_ZI_H, + MUL_ZI_S, + MUL_ZPmZ_B, + MUL_ZPmZ_D, + MUL_ZPmZ_H, + MUL_ZPmZ_S, + MUL_ZZZI_D, + MUL_ZZZI_H, + MUL_ZZZI_S, + MUL_ZZZ_B, + MUL_ZZZ_D, + MUL_ZZZ_H, + MUL_ZZZ_S, + MULv16i8, + MULv2i32, + MULv2i32_indexed, + MULv4i16, + MULv4i16_indexed, + MULv4i32, + MULv4i32_indexed, + MULv8i16, + MULv8i16_indexed, + MULv8i8, + MVNIv2i32, + MVNIv2s_msl, + MVNIv4i16, + MVNIv4i32, + MVNIv4s_msl, + MVNIv8i16, + NANDS_PPzPP, + NAND_PPzPP, + NBSL_ZZZZ, + NEG_ZPmZ_B, + NEG_ZPmZ_D, + NEG_ZPmZ_H, + NEG_ZPmZ_S, + NEG_ZPzZ_B, + NEG_ZPzZ_D, + NEG_ZPzZ_H, + NEG_ZPzZ_S, + NEGv16i8, + NEGv1i64, + NEGv2i32, + NEGv2i64, + NEGv4i16, + NEGv4i32, + NEGv8i16, + NEGv8i8, + NMATCH_PPzZZ_B, + NMATCH_PPzZZ_H, + NOP, + NORS_PPzPP, + NOR_PPzPP, + NOT_ZPmZ_B, + NOT_ZPmZ_D, + NOT_ZPmZ_H, + NOT_ZPmZ_S, + NOT_ZPzZ_B, + NOT_ZPzZ_D, + NOT_ZPzZ_H, + NOT_ZPzZ_S, + NOTv16i8, + NOTv8i8, + ORNS_PPzPP, + ORNWrs, + ORNXrs, + ORN_PPzPP, + ORNv16i8, + ORNv8i8, + ORQV_VPZ_B, + ORQV_VPZ_D, + ORQV_VPZ_H, + ORQV_VPZ_S, + ORRS_PPzPP, + ORRWri, + ORRWrs, + ORRXri, + ORRXrs, + ORR_PPzPP, + ORR_ZI, + ORR_ZPmZ_B, + ORR_ZPmZ_D, + ORR_ZPmZ_H, + ORR_ZPmZ_S, + ORR_ZZZ, + ORRv16i8, + ORRv2i32, + ORRv4i16, + ORRv4i32, + ORRv8i16, + ORRv8i8, + ORV_VPZ_B, + ORV_VPZ_D, + ORV_VPZ_H, + ORV_VPZ_S, + PACDA, + PACDB, + PACDZA, + PACDZB, + PACGA, + PACIA, + PACIA1716, + PACIA171615, + PACIASP, + PACIASPPC, + PACIAZ, + PACIB, + PACIB1716, + PACIB171615, + PACIBSP, + PACIBSPPC, + PACIBZ, + PACIZA, + PACIZB, + PACM, + PACNBIASPPC, + PACNBIBSPPC, + PEXT_2PCI_B, + PEXT_2PCI_D, + PEXT_2PCI_H, + PEXT_2PCI_S, + PEXT_PCI_B, + PEXT_PCI_D, + PEXT_PCI_H, + PEXT_PCI_S, + PFALSE, + PFIRST_B, + PMLAL_2ZZZ_Q, + PMOV_PZI_B, + PMOV_PZI_D, + PMOV_PZI_H, + PMOV_PZI_S, + PMOV_ZIP_B, + PMOV_ZIP_D, + PMOV_ZIP_H, + PMOV_ZIP_S, + PMULLB_ZZZ_D, + PMULLB_ZZZ_H, + PMULLB_ZZZ_Q, + PMULLT_ZZZ_D, + PMULLT_ZZZ_H, + PMULLT_ZZZ_Q, + PMULL_2ZZZ_Q, + PMULLv16i8, + PMULLv1i64, + PMULLv2i64, + PMULLv8i8, + PMUL_ZZZ_B, + PMULv16i8, + PMULv8i8, + PNEXT_B, + PNEXT_D, + PNEXT_H, + PNEXT_S, + PRFB_D_PZI, + PRFB_D_SCALED, + PRFB_D_SXTW_SCALED, + PRFB_D_UXTW_SCALED, + PRFB_PRI, + PRFB_PRR, + PRFB_S_PZI, + PRFB_S_SXTW_SCALED, + PRFB_S_UXTW_SCALED, + PRFD_D_PZI, + PRFD_D_SCALED, + PRFD_D_SXTW_SCALED, + PRFD_D_UXTW_SCALED, + PRFD_PRI, + PRFD_PRR, + PRFD_S_PZI, + PRFD_S_SXTW_SCALED, + PRFD_S_UXTW_SCALED, + PRFH_D_PZI, + PRFH_D_SCALED, + PRFH_D_SXTW_SCALED, + PRFH_D_UXTW_SCALED, + PRFH_PRI, + PRFH_PRR, + PRFH_S_PZI, + PRFH_S_SXTW_SCALED, + PRFH_S_UXTW_SCALED, + PRFMl, + PRFMroW, + PRFMroX, + PRFMui, + PRFUMi, + PRFW_D_PZI, + PRFW_D_SCALED, + PRFW_D_SXTW_SCALED, + PRFW_D_UXTW_SCALED, + PRFW_PRI, + PRFW_PRR, + PRFW_S_PZI, + PRFW_S_SXTW_SCALED, + PRFW_S_UXTW_SCALED, + PSEL_PPPRI_B, + PSEL_PPPRI_D, + PSEL_PPPRI_H, + PSEL_PPPRI_S, + PTEST_PP, + PTRUES_B, + PTRUES_D, + PTRUES_H, + PTRUES_S, + PTRUE_B, + PTRUE_C_B, + PTRUE_C_D, + PTRUE_C_H, + PTRUE_C_S, + PTRUE_D, + PTRUE_H, + PTRUE_S, + PUNPKHI_PP, + PUNPKLO_PP, + RADDHNB_ZZZ_B, + RADDHNB_ZZZ_H, + RADDHNB_ZZZ_S, + RADDHNT_ZZZ_B, + RADDHNT_ZZZ_H, + RADDHNT_ZZZ_S, + RADDHNv2i64_v2i32, + RADDHNv2i64_v4i32, + RADDHNv4i32_v4i16, + RADDHNv4i32_v8i16, + RADDHNv8i16_v16i8, + RADDHNv8i16_v8i8, + RAX1, + RAX1_ZZZ_D, + RBITWr, + RBITXr, + RBIT_ZPmZ_B, + RBIT_ZPmZ_D, + RBIT_ZPmZ_H, + RBIT_ZPmZ_S, + RBIT_ZPzZ_B, + RBIT_ZPzZ_D, + RBIT_ZPzZ_H, + RBIT_ZPzZ_S, + RBITv16i8, + RBITv8i8, + RCWCAS, + RCWCASA, + RCWCASAL, + RCWCASL, + RCWCASP, + RCWCASPA, + RCWCASPAL, + RCWCASPL, + RCWCLR, + RCWCLRA, + RCWCLRAL, + RCWCLRL, + RCWCLRP, + RCWCLRPA, + RCWCLRPAL, + RCWCLRPL, + RCWCLRS, + RCWCLRSA, + RCWCLRSAL, + RCWCLRSL, + RCWCLRSP, + RCWCLRSPA, + RCWCLRSPAL, + RCWCLRSPL, + RCWSCAS, + RCWSCASA, + RCWSCASAL, + RCWSCASL, + RCWSCASP, + RCWSCASPA, + RCWSCASPAL, + RCWSCASPL, + RCWSET, + RCWSETA, + RCWSETAL, + RCWSETL, + RCWSETP, + RCWSETPA, + RCWSETPAL, + RCWSETPL, + RCWSETS, + RCWSETSA, + RCWSETSAL, + RCWSETSL, + RCWSETSP, + RCWSETSPA, + RCWSETSPAL, + RCWSETSPL, + RCWSWP, + RCWSWPA, + RCWSWPAL, + RCWSWPL, + RCWSWPP, + RCWSWPPA, + RCWSWPPAL, + RCWSWPPL, + RCWSWPS, + RCWSWPSA, + RCWSWPSAL, + RCWSWPSL, + RCWSWPSP, + RCWSWPSPA, + RCWSWPSPAL, + RCWSWPSPL, + RDFFRS_PPz, + RDFFR_P, + RDFFR_PPz, + RDSVLI_XI, + RDVLI_XI, + RET, + RETAA, + RETAASPPCi, + RETAASPPCr, + RETAB, + RETABSPPCi, + RETABSPPCr, + REV16Wr, + REV16Xr, + REV16v16i8, + REV16v8i8, + REV32Xr, + REV32v16i8, + REV32v4i16, + REV32v8i16, + REV32v8i8, + REV64v16i8, + REV64v2i32, + REV64v4i16, + REV64v4i32, + REV64v8i16, + REV64v8i8, + REVB_ZPmZ_D, + REVB_ZPmZ_H, + REVB_ZPmZ_S, + REVB_ZPzZ_D, + REVB_ZPzZ_H, + REVB_ZPzZ_S, + REVD_ZPmZ, + REVD_ZPzZ, + REVH_ZPmZ_D, + REVH_ZPmZ_S, + REVH_ZPzZ_D, + REVH_ZPzZ_S, + REVW_ZPmZ_D, + REVW_ZPzZ_D, + REVWr, + REVXr, + REV_PP_B, + REV_PP_D, + REV_PP_H, + REV_PP_S, + REV_ZZ_B, + REV_ZZ_D, + REV_ZZ_H, + REV_ZZ_S, + RMIF, + RORVWr, + RORVXr, + RPRFM, + RSHRNB_ZZI_B, + RSHRNB_ZZI_H, + RSHRNB_ZZI_S, + RSHRNT_ZZI_B, + RSHRNT_ZZI_H, + RSHRNT_ZZI_S, + RSHRNv16i8_shift, + RSHRNv2i32_shift, + RSHRNv4i16_shift, + RSHRNv4i32_shift, + RSHRNv8i16_shift, + RSHRNv8i8_shift, + RSUBHNB_ZZZ_B, + RSUBHNB_ZZZ_H, + RSUBHNB_ZZZ_S, + RSUBHNT_ZZZ_B, + RSUBHNT_ZZZ_H, + RSUBHNT_ZZZ_S, + RSUBHNv2i64_v2i32, + RSUBHNv2i64_v4i32, + RSUBHNv4i32_v4i16, + RSUBHNv4i32_v8i16, + RSUBHNv8i16_v16i8, + RSUBHNv8i16_v8i8, + SABALB_ZZZ_D, + SABALB_ZZZ_H, + SABALB_ZZZ_S, + SABALT_ZZZ_D, + SABALT_ZZZ_H, + SABALT_ZZZ_S, + SABAL_ZZZ_BtoH, + SABAL_ZZZ_HtoS, + SABAL_ZZZ_StoD, + SABALv16i8_v8i16, + SABALv2i32_v2i64, + SABALv4i16_v4i32, + SABALv4i32_v2i64, + SABALv8i16_v4i32, + SABALv8i8_v8i16, + SABA_ZZZ_B, + SABA_ZZZ_D, + SABA_ZZZ_H, + SABA_ZZZ_S, + SABAv16i8, + SABAv2i32, + SABAv4i16, + SABAv4i32, + SABAv8i16, + SABAv8i8, + SABDLB_ZZZ_D, + SABDLB_ZZZ_H, + SABDLB_ZZZ_S, + SABDLT_ZZZ_D, + SABDLT_ZZZ_H, + SABDLT_ZZZ_S, + SABDLv16i8_v8i16, + SABDLv2i32_v2i64, + SABDLv4i16_v4i32, + SABDLv4i32_v2i64, + SABDLv8i16_v4i32, + SABDLv8i8_v8i16, + SABD_ZPmZ_B, + SABD_ZPmZ_D, + SABD_ZPmZ_H, + SABD_ZPmZ_S, + SABDv16i8, + SABDv2i32, + SABDv4i16, + SABDv4i32, + SABDv8i16, + SABDv8i8, + SADALP_ZPmZ_D, + SADALP_ZPmZ_H, + SADALP_ZPmZ_S, + SADALPv16i8_v8i16, + SADALPv2i32_v1i64, + SADALPv4i16_v2i32, + SADALPv4i32_v2i64, + SADALPv8i16_v4i32, + SADALPv8i8_v4i16, + SADDLBT_ZZZ_D, + SADDLBT_ZZZ_H, + SADDLBT_ZZZ_S, + SADDLB_ZZZ_D, + SADDLB_ZZZ_H, + SADDLB_ZZZ_S, + SADDLPv16i8_v8i16, + SADDLPv2i32_v1i64, + SADDLPv4i16_v2i32, + SADDLPv4i32_v2i64, + SADDLPv8i16_v4i32, + SADDLPv8i8_v4i16, + SADDLT_ZZZ_D, + SADDLT_ZZZ_H, + SADDLT_ZZZ_S, + SADDLVv16i8v, + SADDLVv4i16v, + SADDLVv4i32v, + SADDLVv8i16v, + SADDLVv8i8v, + SADDLv16i8_v8i16, + SADDLv2i32_v2i64, + SADDLv4i16_v4i32, + SADDLv4i32_v2i64, + SADDLv8i16_v4i32, + SADDLv8i8_v8i16, + SADDV_VPZ_B, + SADDV_VPZ_H, + SADDV_VPZ_S, + SADDWB_ZZZ_D, + SADDWB_ZZZ_H, + SADDWB_ZZZ_S, + SADDWT_ZZZ_D, + SADDWT_ZZZ_H, + SADDWT_ZZZ_S, + SADDWv16i8_v8i16, + SADDWv2i32_v2i64, + SADDWv4i16_v4i32, + SADDWv4i32_v2i64, + SADDWv8i16_v4i32, + SADDWv8i8_v8i16, + SB, + SBCLB_ZZZ_D, + SBCLB_ZZZ_S, + SBCLT_ZZZ_D, + SBCLT_ZZZ_S, + SBCSWr, + SBCSXr, + SBCWr, + SBCXr, + SBFMWri, + SBFMXri, + SCLAMP_VG2_2Z2Z_B, + SCLAMP_VG2_2Z2Z_D, + SCLAMP_VG2_2Z2Z_H, + SCLAMP_VG2_2Z2Z_S, + SCLAMP_VG4_4Z4Z_B, + SCLAMP_VG4_4Z4Z_D, + SCLAMP_VG4_4Z4Z_H, + SCLAMP_VG4_4Z4Z_S, + SCLAMP_ZZZ_B, + SCLAMP_ZZZ_D, + SCLAMP_ZZZ_H, + SCLAMP_ZZZ_S, + SCVTFDSr, + SCVTFHDr, + SCVTFHSr, + SCVTFLT_ZZ_BtoH, + SCVTFLT_ZZ_HtoS, + SCVTFLT_ZZ_StoD, + SCVTFSDr, + SCVTFSWDri, + SCVTFSWHri, + SCVTFSWSri, + SCVTFSXDri, + SCVTFSXHri, + SCVTFSXSri, + SCVTFUWDri, + SCVTFUWHri, + SCVTFUWSri, + SCVTFUXDri, + SCVTFUXHri, + SCVTFUXSri, + SCVTF_2Z2Z_StoS, + SCVTF_4Z4Z_StoS, + SCVTF_ZPmZ_DtoD, + SCVTF_ZPmZ_DtoH, + SCVTF_ZPmZ_DtoS, + SCVTF_ZPmZ_HtoH, + SCVTF_ZPmZ_StoD, + SCVTF_ZPmZ_StoH, + SCVTF_ZPmZ_StoS, + SCVTF_ZPzZ_DtoD, + SCVTF_ZPzZ_DtoH, + SCVTF_ZPzZ_DtoS, + SCVTF_ZPzZ_HtoH, + SCVTF_ZPzZ_StoD, + SCVTF_ZPzZ_StoH, + SCVTF_ZPzZ_StoS, + SCVTF_ZZ_BtoH, + SCVTF_ZZ_HtoS, + SCVTF_ZZ_StoD, + SCVTFd, + SCVTFh, + SCVTFs, + SCVTFv1i16, + SCVTFv1i32, + SCVTFv1i64, + SCVTFv2f32, + SCVTFv2f64, + SCVTFv2i32_shift, + SCVTFv2i64_shift, + SCVTFv4f16, + SCVTFv4f32, + SCVTFv4i16_shift, + SCVTFv4i32_shift, + SCVTFv8f16, + SCVTFv8i16_shift, + SDIVR_ZPmZ_D, + SDIVR_ZPmZ_S, + SDIVWr, + SDIVXr, + SDIV_ZPmZ_D, + SDIV_ZPmZ_S, + SDOT_VG2_M2Z2Z_BtoS, + SDOT_VG2_M2Z2Z_HtoD, + SDOT_VG2_M2Z2Z_HtoS, + SDOT_VG2_M2ZZI_BToS, + SDOT_VG2_M2ZZI_HToS, + SDOT_VG2_M2ZZI_HtoD, + SDOT_VG2_M2ZZ_BtoS, + SDOT_VG2_M2ZZ_HtoD, + SDOT_VG2_M2ZZ_HtoS, + SDOT_VG4_M4Z4Z_BtoS, + SDOT_VG4_M4Z4Z_HtoD, + SDOT_VG4_M4Z4Z_HtoS, + SDOT_VG4_M4ZZI_BToS, + SDOT_VG4_M4ZZI_HToS, + SDOT_VG4_M4ZZI_HtoD, + SDOT_VG4_M4ZZ_BtoS, + SDOT_VG4_M4ZZ_HtoD, + SDOT_VG4_M4ZZ_HtoS, + SDOT_ZZZI_BtoH, + SDOT_ZZZI_BtoS, + SDOT_ZZZI_HtoD, + SDOT_ZZZI_HtoS, + SDOT_ZZZ_BtoH, + SDOT_ZZZ_BtoS, + SDOT_ZZZ_HtoD, + SDOT_ZZZ_HtoS, + SDOTlanev16i8, + SDOTlanev8i8, + SDOTv16i8, + SDOTv8i8, + SEL_PPPP, + SEL_VG2_2ZC2Z2Z_B, + SEL_VG2_2ZC2Z2Z_D, + SEL_VG2_2ZC2Z2Z_H, + SEL_VG2_2ZC2Z2Z_S, + SEL_VG4_4ZC4Z4Z_B, + SEL_VG4_4ZC4Z4Z_D, + SEL_VG4_4ZC4Z4Z_H, + SEL_VG4_4ZC4Z4Z_S, + SEL_ZPZZ_B, + SEL_ZPZZ_D, + SEL_ZPZZ_H, + SEL_ZPZZ_S, + SETE, + SETEN, + SETET, + SETETN, + SETF16, + SETF8, + SETFFR, + SETGM, + SETGMN, + SETGMT, + SETGMTN, + SETGOE, + SETGOEN, + SETGOET, + SETGOETN, + SETGOM, + SETGOMN, + SETGOMT, + SETGOMTN, + SETGOP, + SETGOPN, + SETGOPT, + SETGOPTN, + SETGP, + SETGPN, + SETGPT, + SETGPTN, + SETM, + SETMN, + SETMT, + SETMTN, + SETP, + SETPN, + SETPT, + SETPTN, + SHA1Crrr, + SHA1Hrr, + SHA1Mrrr, + SHA1Prrr, + SHA1SU0rrr, + SHA1SU1rr, + SHA256H2rrr, + SHA256Hrrr, + SHA256SU0rr, + SHA256SU1rrr, + SHA512H, + SHA512H2, + SHA512SU0, + SHA512SU1, + SHADD_ZPmZ_B, + SHADD_ZPmZ_D, + SHADD_ZPmZ_H, + SHADD_ZPmZ_S, + SHADDv16i8, + SHADDv2i32, + SHADDv4i16, + SHADDv4i32, + SHADDv8i16, + SHADDv8i8, + SHLLv16i8, + SHLLv2i32, + SHLLv4i16, + SHLLv4i32, + SHLLv8i16, + SHLLv8i8, + SHLd, + SHLv16i8_shift, + SHLv2i32_shift, + SHLv2i64_shift, + SHLv4i16_shift, + SHLv4i32_shift, + SHLv8i16_shift, + SHLv8i8_shift, + SHRNB_ZZI_B, + SHRNB_ZZI_H, + SHRNB_ZZI_S, + SHRNT_ZZI_B, + SHRNT_ZZI_H, + SHRNT_ZZI_S, + SHRNv16i8_shift, + SHRNv2i32_shift, + SHRNv4i16_shift, + SHRNv4i32_shift, + SHRNv8i16_shift, + SHRNv8i8_shift, + SHSUBR_ZPmZ_B, + SHSUBR_ZPmZ_D, + SHSUBR_ZPmZ_H, + SHSUBR_ZPmZ_S, + SHSUB_ZPmZ_B, + SHSUB_ZPmZ_D, + SHSUB_ZPmZ_H, + SHSUB_ZPmZ_S, + SHSUBv16i8, + SHSUBv2i32, + SHSUBv4i16, + SHSUBv4i32, + SHSUBv8i16, + SHSUBv8i8, + SHUH, + SLI_ZZI_B, + SLI_ZZI_D, + SLI_ZZI_H, + SLI_ZZI_S, + SLId, + SLIv16i8_shift, + SLIv2i32_shift, + SLIv2i64_shift, + SLIv4i16_shift, + SLIv4i32_shift, + SLIv8i16_shift, + SLIv8i8_shift, + SM3PARTW1, + SM3PARTW2, + SM3SS1, + SM3TT1A, + SM3TT1B, + SM3TT2A, + SM3TT2B, + SM4E, + SM4EKEY_ZZZ_S, + SM4ENCKEY, + SM4E_ZZZ_S, + SMADDLrrr, + SMAXP_ZPmZ_B, + SMAXP_ZPmZ_D, + SMAXP_ZPmZ_H, + SMAXP_ZPmZ_S, + SMAXPv16i8, + SMAXPv2i32, + SMAXPv4i16, + SMAXPv4i32, + SMAXPv8i16, + SMAXPv8i8, + SMAXQV_VPZ_B, + SMAXQV_VPZ_D, + SMAXQV_VPZ_H, + SMAXQV_VPZ_S, + SMAXV_VPZ_B, + SMAXV_VPZ_D, + SMAXV_VPZ_H, + SMAXV_VPZ_S, + SMAXVv16i8v, + SMAXVv4i16v, + SMAXVv4i32v, + SMAXVv8i16v, + SMAXVv8i8v, + SMAXWri, + SMAXWrr, + SMAXXri, + SMAXXrr, + SMAX_VG2_2Z2Z_B, + SMAX_VG2_2Z2Z_D, + SMAX_VG2_2Z2Z_H, + SMAX_VG2_2Z2Z_S, + SMAX_VG2_2ZZ_B, + SMAX_VG2_2ZZ_D, + SMAX_VG2_2ZZ_H, + SMAX_VG2_2ZZ_S, + SMAX_VG4_4Z4Z_B, + SMAX_VG4_4Z4Z_D, + SMAX_VG4_4Z4Z_H, + SMAX_VG4_4Z4Z_S, + SMAX_VG4_4ZZ_B, + SMAX_VG4_4ZZ_D, + SMAX_VG4_4ZZ_H, + SMAX_VG4_4ZZ_S, + SMAX_ZI_B, + SMAX_ZI_D, + SMAX_ZI_H, + SMAX_ZI_S, + SMAX_ZPmZ_B, + SMAX_ZPmZ_D, + SMAX_ZPmZ_H, + SMAX_ZPmZ_S, + SMAXv16i8, + SMAXv2i32, + SMAXv4i16, + SMAXv4i32, + SMAXv8i16, + SMAXv8i8, + SMC, + SMINP_ZPmZ_B, + SMINP_ZPmZ_D, + SMINP_ZPmZ_H, + SMINP_ZPmZ_S, + SMINPv16i8, + SMINPv2i32, + SMINPv4i16, + SMINPv4i32, + SMINPv8i16, + SMINPv8i8, + SMINQV_VPZ_B, + SMINQV_VPZ_D, + SMINQV_VPZ_H, + SMINQV_VPZ_S, + SMINV_VPZ_B, + SMINV_VPZ_D, + SMINV_VPZ_H, + SMINV_VPZ_S, + SMINVv16i8v, + SMINVv4i16v, + SMINVv4i32v, + SMINVv8i16v, + SMINVv8i8v, + SMINWri, + SMINWrr, + SMINXri, + SMINXrr, + SMIN_VG2_2Z2Z_B, + SMIN_VG2_2Z2Z_D, + SMIN_VG2_2Z2Z_H, + SMIN_VG2_2Z2Z_S, + SMIN_VG2_2ZZ_B, + SMIN_VG2_2ZZ_D, + SMIN_VG2_2ZZ_H, + SMIN_VG2_2ZZ_S, + SMIN_VG4_4Z4Z_B, + SMIN_VG4_4Z4Z_D, + SMIN_VG4_4Z4Z_H, + SMIN_VG4_4Z4Z_S, + SMIN_VG4_4ZZ_B, + SMIN_VG4_4ZZ_D, + SMIN_VG4_4ZZ_H, + SMIN_VG4_4ZZ_S, + SMIN_ZI_B, + SMIN_ZI_D, + SMIN_ZI_H, + SMIN_ZI_S, + SMIN_ZPmZ_B, + SMIN_ZPmZ_D, + SMIN_ZPmZ_H, + SMIN_ZPmZ_S, + SMINv16i8, + SMINv2i32, + SMINv4i16, + SMINv4i32, + SMINv8i16, + SMINv8i8, + SMLALB_ZZZI_D, + SMLALB_ZZZI_S, + SMLALB_ZZZ_D, + SMLALB_ZZZ_H, + SMLALB_ZZZ_S, + SMLALL_MZZI_BtoS, + SMLALL_MZZI_HtoD, + SMLALL_MZZ_BtoS, + SMLALL_MZZ_HtoD, + SMLALL_VG2_M2Z2Z_BtoS, + SMLALL_VG2_M2Z2Z_HtoD, + SMLALL_VG2_M2ZZI_BtoS, + SMLALL_VG2_M2ZZI_HtoD, + SMLALL_VG2_M2ZZ_BtoS, + SMLALL_VG2_M2ZZ_HtoD, + SMLALL_VG4_M4Z4Z_BtoS, + SMLALL_VG4_M4Z4Z_HtoD, + SMLALL_VG4_M4ZZI_BtoS, + SMLALL_VG4_M4ZZI_HtoD, + SMLALL_VG4_M4ZZ_BtoS, + SMLALL_VG4_M4ZZ_HtoD, + SMLALT_ZZZI_D, + SMLALT_ZZZI_S, + SMLALT_ZZZ_D, + SMLALT_ZZZ_H, + SMLALT_ZZZ_S, + SMLAL_MZZI_HtoS, + SMLAL_MZZ_HtoS, + SMLAL_VG2_M2Z2Z_HtoS, + SMLAL_VG2_M2ZZI_S, + SMLAL_VG2_M2ZZ_HtoS, + SMLAL_VG4_M4Z4Z_HtoS, + SMLAL_VG4_M4ZZI_HtoS, + SMLAL_VG4_M4ZZ_HtoS, + SMLALv16i8_v8i16, + SMLALv2i32_indexed, + SMLALv2i32_v2i64, + SMLALv4i16_indexed, + SMLALv4i16_v4i32, + SMLALv4i32_indexed, + SMLALv4i32_v2i64, + SMLALv8i16_indexed, + SMLALv8i16_v4i32, + SMLALv8i8_v8i16, + SMLSLB_ZZZI_D, + SMLSLB_ZZZI_S, + SMLSLB_ZZZ_D, + SMLSLB_ZZZ_H, + SMLSLB_ZZZ_S, + SMLSLL_MZZI_BtoS, + SMLSLL_MZZI_HtoD, + SMLSLL_MZZ_BtoS, + SMLSLL_MZZ_HtoD, + SMLSLL_VG2_M2Z2Z_BtoS, + SMLSLL_VG2_M2Z2Z_HtoD, + SMLSLL_VG2_M2ZZI_BtoS, + SMLSLL_VG2_M2ZZI_HtoD, + SMLSLL_VG2_M2ZZ_BtoS, + SMLSLL_VG2_M2ZZ_HtoD, + SMLSLL_VG4_M4Z4Z_BtoS, + SMLSLL_VG4_M4Z4Z_HtoD, + SMLSLL_VG4_M4ZZI_BtoS, + SMLSLL_VG4_M4ZZI_HtoD, + SMLSLL_VG4_M4ZZ_BtoS, + SMLSLL_VG4_M4ZZ_HtoD, + SMLSLT_ZZZI_D, + SMLSLT_ZZZI_S, + SMLSLT_ZZZ_D, + SMLSLT_ZZZ_H, + SMLSLT_ZZZ_S, + SMLSL_MZZI_HtoS, + SMLSL_MZZ_HtoS, + SMLSL_VG2_M2Z2Z_HtoS, + SMLSL_VG2_M2ZZI_S, + SMLSL_VG2_M2ZZ_HtoS, + SMLSL_VG4_M4Z4Z_HtoS, + SMLSL_VG4_M4ZZI_HtoS, + SMLSL_VG4_M4ZZ_HtoS, + SMLSLv16i8_v8i16, + SMLSLv2i32_indexed, + SMLSLv2i32_v2i64, + SMLSLv4i16_indexed, + SMLSLv4i16_v4i32, + SMLSLv4i32_indexed, + SMLSLv4i32_v2i64, + SMLSLv8i16_indexed, + SMLSLv8i16_v4i32, + SMLSLv8i8_v8i16, + SMMLA, + SMMLA_ZZZ, + SMOP4A_M2Z2Z_BToS, + SMOP4A_M2Z2Z_HToS, + SMOP4A_M2Z2Z_HtoD, + SMOP4A_M2ZZ_BToS, + SMOP4A_M2ZZ_HToS, + SMOP4A_M2ZZ_HtoD, + SMOP4A_MZ2Z_BToS, + SMOP4A_MZ2Z_HToS, + SMOP4A_MZ2Z_HtoD, + SMOP4A_MZZ_BToS, + SMOP4A_MZZ_HToS, + SMOP4A_MZZ_HtoD, + SMOP4S_M2Z2Z_BToS, + SMOP4S_M2Z2Z_HToS, + SMOP4S_M2Z2Z_HtoD, + SMOP4S_M2ZZ_BToS, + SMOP4S_M2ZZ_HToS, + SMOP4S_M2ZZ_HtoD, + SMOP4S_MZ2Z_BToS, + SMOP4S_MZ2Z_HToS, + SMOP4S_MZ2Z_HtoD, + SMOP4S_MZZ_BToS, + SMOP4S_MZZ_HToS, + SMOP4S_MZZ_HtoD, + SMOPA_MPPZZ_D, + SMOPA_MPPZZ_HtoS, + SMOPA_MPPZZ_S, + SMOPS_MPPZZ_D, + SMOPS_MPPZZ_HtoS, + SMOPS_MPPZZ_S, + SMOVvi16to32, + SMOVvi16to32_idx0, + SMOVvi16to64, + SMOVvi16to64_idx0, + SMOVvi32to64, + SMOVvi32to64_idx0, + SMOVvi8to32, + SMOVvi8to32_idx0, + SMOVvi8to64, + SMOVvi8to64_idx0, + SMSUBLrrr, + SMULH_ZPmZ_B, + SMULH_ZPmZ_D, + SMULH_ZPmZ_H, + SMULH_ZPmZ_S, + SMULH_ZZZ_B, + SMULH_ZZZ_D, + SMULH_ZZZ_H, + SMULH_ZZZ_S, + SMULHrr, + SMULLB_ZZZI_D, + SMULLB_ZZZI_S, + SMULLB_ZZZ_D, + SMULLB_ZZZ_H, + SMULLB_ZZZ_S, + SMULLT_ZZZI_D, + SMULLT_ZZZI_S, + SMULLT_ZZZ_D, + SMULLT_ZZZ_H, + SMULLT_ZZZ_S, + SMULLv16i8_v8i16, + SMULLv2i32_indexed, + SMULLv2i32_v2i64, + SMULLv4i16_indexed, + SMULLv4i16_v4i32, + SMULLv4i32_indexed, + SMULLv4i32_v2i64, + SMULLv8i16_indexed, + SMULLv8i16_v4i32, + SMULLv8i8_v8i16, + SPLICE_ZPZZ_B, + SPLICE_ZPZZ_D, + SPLICE_ZPZZ_H, + SPLICE_ZPZZ_S, + SPLICE_ZPZ_B, + SPLICE_ZPZ_D, + SPLICE_ZPZ_H, + SPLICE_ZPZ_S, + SQABS_ZPmZ_B, + SQABS_ZPmZ_D, + SQABS_ZPmZ_H, + SQABS_ZPmZ_S, + SQABS_ZPzZ_B, + SQABS_ZPzZ_D, + SQABS_ZPzZ_H, + SQABS_ZPzZ_S, + SQABSv16i8, + SQABSv1i16, + SQABSv1i32, + SQABSv1i64, + SQABSv1i8, + SQABSv2i32, + SQABSv2i64, + SQABSv4i16, + SQABSv4i32, + SQABSv8i16, + SQABSv8i8, + SQADD_ZI_B, + SQADD_ZI_D, + SQADD_ZI_H, + SQADD_ZI_S, + SQADD_ZPmZ_B, + SQADD_ZPmZ_D, + SQADD_ZPmZ_H, + SQADD_ZPmZ_S, + SQADD_ZZZ_B, + SQADD_ZZZ_D, + SQADD_ZZZ_H, + SQADD_ZZZ_S, + SQADDv16i8, + SQADDv1i16, + SQADDv1i32, + SQADDv1i64, + SQADDv1i8, + SQADDv2i32, + SQADDv2i64, + SQADDv4i16, + SQADDv4i32, + SQADDv8i16, + SQADDv8i8, + SQCADD_ZZI_B, + SQCADD_ZZI_D, + SQCADD_ZZI_H, + SQCADD_ZZI_S, + SQCVTN_Z2Z_StoH, + SQCVTN_Z4Z_DtoH, + SQCVTN_Z4Z_StoB, + SQCVTUN_Z2Z_StoH, + SQCVTUN_Z4Z_DtoH, + SQCVTUN_Z4Z_StoB, + SQCVTU_Z2Z_StoH, + SQCVTU_Z4Z_DtoH, + SQCVTU_Z4Z_StoB, + SQCVT_Z2Z_StoH, + SQCVT_Z4Z_DtoH, + SQCVT_Z4Z_StoB, + SQDECB_XPiI, + SQDECB_XPiWdI, + SQDECD_XPiI, + SQDECD_XPiWdI, + SQDECD_ZPiI, + SQDECH_XPiI, + SQDECH_XPiWdI, + SQDECH_ZPiI, + SQDECP_XPWd_B, + SQDECP_XPWd_D, + SQDECP_XPWd_H, + SQDECP_XPWd_S, + SQDECP_XP_B, + SQDECP_XP_D, + SQDECP_XP_H, + SQDECP_XP_S, + SQDECP_ZP_D, + SQDECP_ZP_H, + SQDECP_ZP_S, + SQDECW_XPiI, + SQDECW_XPiWdI, + SQDECW_ZPiI, + SQDMLALBT_ZZZ_D, + SQDMLALBT_ZZZ_H, + SQDMLALBT_ZZZ_S, + SQDMLALB_ZZZI_D, + SQDMLALB_ZZZI_S, + SQDMLALB_ZZZ_D, + SQDMLALB_ZZZ_H, + SQDMLALB_ZZZ_S, + SQDMLALT_ZZZI_D, + SQDMLALT_ZZZI_S, + SQDMLALT_ZZZ_D, + SQDMLALT_ZZZ_H, + SQDMLALT_ZZZ_S, + SQDMLALi16, + SQDMLALi32, + SQDMLALv1i32_indexed, + SQDMLALv1i64_indexed, + SQDMLALv2i32_indexed, + SQDMLALv2i32_v2i64, + SQDMLALv4i16_indexed, + SQDMLALv4i16_v4i32, + SQDMLALv4i32_indexed, + SQDMLALv4i32_v2i64, + SQDMLALv8i16_indexed, + SQDMLALv8i16_v4i32, + SQDMLSLBT_ZZZ_D, + SQDMLSLBT_ZZZ_H, + SQDMLSLBT_ZZZ_S, + SQDMLSLB_ZZZI_D, + SQDMLSLB_ZZZI_S, + SQDMLSLB_ZZZ_D, + SQDMLSLB_ZZZ_H, + SQDMLSLB_ZZZ_S, + SQDMLSLT_ZZZI_D, + SQDMLSLT_ZZZI_S, + SQDMLSLT_ZZZ_D, + SQDMLSLT_ZZZ_H, + SQDMLSLT_ZZZ_S, + SQDMLSLi16, + SQDMLSLi32, + SQDMLSLv1i32_indexed, + SQDMLSLv1i64_indexed, + SQDMLSLv2i32_indexed, + SQDMLSLv2i32_v2i64, + SQDMLSLv4i16_indexed, + SQDMLSLv4i16_v4i32, + SQDMLSLv4i32_indexed, + SQDMLSLv4i32_v2i64, + SQDMLSLv8i16_indexed, + SQDMLSLv8i16_v4i32, + SQDMULH_VG2_2Z2Z_B, + SQDMULH_VG2_2Z2Z_D, + SQDMULH_VG2_2Z2Z_H, + SQDMULH_VG2_2Z2Z_S, + SQDMULH_VG2_2ZZ_B, + SQDMULH_VG2_2ZZ_D, + SQDMULH_VG2_2ZZ_H, + SQDMULH_VG2_2ZZ_S, + SQDMULH_VG4_4Z4Z_B, + SQDMULH_VG4_4Z4Z_D, + SQDMULH_VG4_4Z4Z_H, + SQDMULH_VG4_4Z4Z_S, + SQDMULH_VG4_4ZZ_B, + SQDMULH_VG4_4ZZ_D, + SQDMULH_VG4_4ZZ_H, + SQDMULH_VG4_4ZZ_S, + SQDMULH_ZZZI_D, + SQDMULH_ZZZI_H, + SQDMULH_ZZZI_S, + SQDMULH_ZZZ_B, + SQDMULH_ZZZ_D, + SQDMULH_ZZZ_H, + SQDMULH_ZZZ_S, + SQDMULHv1i16, + SQDMULHv1i16_indexed, + SQDMULHv1i32, + SQDMULHv1i32_indexed, + SQDMULHv2i32, + SQDMULHv2i32_indexed, + SQDMULHv4i16, + SQDMULHv4i16_indexed, + SQDMULHv4i32, + SQDMULHv4i32_indexed, + SQDMULHv8i16, + SQDMULHv8i16_indexed, + SQDMULLB_ZZZI_D, + SQDMULLB_ZZZI_S, + SQDMULLB_ZZZ_D, + SQDMULLB_ZZZ_H, + SQDMULLB_ZZZ_S, + SQDMULLT_ZZZI_D, + SQDMULLT_ZZZI_S, + SQDMULLT_ZZZ_D, + SQDMULLT_ZZZ_H, + SQDMULLT_ZZZ_S, + SQDMULLi16, + SQDMULLi32, + SQDMULLv1i32_indexed, + SQDMULLv1i64_indexed, + SQDMULLv2i32_indexed, + SQDMULLv2i32_v2i64, + SQDMULLv4i16_indexed, + SQDMULLv4i16_v4i32, + SQDMULLv4i32_indexed, + SQDMULLv4i32_v2i64, + SQDMULLv8i16_indexed, + SQDMULLv8i16_v4i32, + SQINCB_XPiI, + SQINCB_XPiWdI, + SQINCD_XPiI, + SQINCD_XPiWdI, + SQINCD_ZPiI, + SQINCH_XPiI, + SQINCH_XPiWdI, + SQINCH_ZPiI, + SQINCP_XPWd_B, + SQINCP_XPWd_D, + SQINCP_XPWd_H, + SQINCP_XPWd_S, + SQINCP_XP_B, + SQINCP_XP_D, + SQINCP_XP_H, + SQINCP_XP_S, + SQINCP_ZP_D, + SQINCP_ZP_H, + SQINCP_ZP_S, + SQINCW_XPiI, + SQINCW_XPiWdI, + SQINCW_ZPiI, + SQNEG_ZPmZ_B, + SQNEG_ZPmZ_D, + SQNEG_ZPmZ_H, + SQNEG_ZPmZ_S, + SQNEG_ZPzZ_B, + SQNEG_ZPzZ_D, + SQNEG_ZPzZ_H, + SQNEG_ZPzZ_S, + SQNEGv16i8, + SQNEGv1i16, + SQNEGv1i32, + SQNEGv1i64, + SQNEGv1i8, + SQNEGv2i32, + SQNEGv2i64, + SQNEGv4i16, + SQNEGv4i32, + SQNEGv8i16, + SQNEGv8i8, + SQRDCMLAH_ZZZI_H, + SQRDCMLAH_ZZZI_S, + SQRDCMLAH_ZZZ_B, + SQRDCMLAH_ZZZ_D, + SQRDCMLAH_ZZZ_H, + SQRDCMLAH_ZZZ_S, + SQRDMLAH_ZZZI_D, + SQRDMLAH_ZZZI_H, + SQRDMLAH_ZZZI_S, + SQRDMLAH_ZZZ_B, + SQRDMLAH_ZZZ_D, + SQRDMLAH_ZZZ_H, + SQRDMLAH_ZZZ_S, + SQRDMLAHv1i16, + SQRDMLAHv1i16_indexed, + SQRDMLAHv1i32, + SQRDMLAHv1i32_indexed, + SQRDMLAHv2i32, + SQRDMLAHv2i32_indexed, + SQRDMLAHv4i16, + SQRDMLAHv4i16_indexed, + SQRDMLAHv4i32, + SQRDMLAHv4i32_indexed, + SQRDMLAHv8i16, + SQRDMLAHv8i16_indexed, + SQRDMLSH_ZZZI_D, + SQRDMLSH_ZZZI_H, + SQRDMLSH_ZZZI_S, + SQRDMLSH_ZZZ_B, + SQRDMLSH_ZZZ_D, + SQRDMLSH_ZZZ_H, + SQRDMLSH_ZZZ_S, + SQRDMLSHv1i16, + SQRDMLSHv1i16_indexed, + SQRDMLSHv1i32, + SQRDMLSHv1i32_indexed, + SQRDMLSHv2i32, + SQRDMLSHv2i32_indexed, + SQRDMLSHv4i16, + SQRDMLSHv4i16_indexed, + SQRDMLSHv4i32, + SQRDMLSHv4i32_indexed, + SQRDMLSHv8i16, + SQRDMLSHv8i16_indexed, + SQRDMULH_ZZZI_D, + SQRDMULH_ZZZI_H, + SQRDMULH_ZZZI_S, + SQRDMULH_ZZZ_B, + SQRDMULH_ZZZ_D, + SQRDMULH_ZZZ_H, + SQRDMULH_ZZZ_S, + SQRDMULHv1i16, + SQRDMULHv1i16_indexed, + SQRDMULHv1i32, + SQRDMULHv1i32_indexed, + SQRDMULHv2i32, + SQRDMULHv2i32_indexed, + SQRDMULHv4i16, + SQRDMULHv4i16_indexed, + SQRDMULHv4i32, + SQRDMULHv4i32_indexed, + SQRDMULHv8i16, + SQRDMULHv8i16_indexed, + SQRSHLR_ZPmZ_B, + SQRSHLR_ZPmZ_D, + SQRSHLR_ZPmZ_H, + SQRSHLR_ZPmZ_S, + SQRSHL_ZPmZ_B, + SQRSHL_ZPmZ_D, + SQRSHL_ZPmZ_H, + SQRSHL_ZPmZ_S, + SQRSHLv16i8, + SQRSHLv1i16, + SQRSHLv1i32, + SQRSHLv1i64, + SQRSHLv1i8, + SQRSHLv2i32, + SQRSHLv2i64, + SQRSHLv4i16, + SQRSHLv4i32, + SQRSHLv8i16, + SQRSHLv8i8, + SQRSHRNB_ZZI_B, + SQRSHRNB_ZZI_H, + SQRSHRNB_ZZI_S, + SQRSHRNT_ZZI_B, + SQRSHRNT_ZZI_H, + SQRSHRNT_ZZI_S, + SQRSHRN_VG4_Z4ZI_B, + SQRSHRN_VG4_Z4ZI_H, + SQRSHRN_Z2ZI_HtoB, + SQRSHRN_Z2ZI_StoH, + SQRSHRNb, + SQRSHRNh, + SQRSHRNs, + SQRSHRNv16i8_shift, + SQRSHRNv2i32_shift, + SQRSHRNv4i16_shift, + SQRSHRNv4i32_shift, + SQRSHRNv8i16_shift, + SQRSHRNv8i8_shift, + SQRSHRUNB_ZZI_B, + SQRSHRUNB_ZZI_H, + SQRSHRUNB_ZZI_S, + SQRSHRUNT_ZZI_B, + SQRSHRUNT_ZZI_H, + SQRSHRUNT_ZZI_S, + SQRSHRUN_VG4_Z4ZI_B, + SQRSHRUN_VG4_Z4ZI_H, + SQRSHRUN_Z2ZI_HtoB, + SQRSHRUN_Z2ZI_StoH, + SQRSHRUNb, + SQRSHRUNh, + SQRSHRUNs, + SQRSHRUNv16i8_shift, + SQRSHRUNv2i32_shift, + SQRSHRUNv4i16_shift, + SQRSHRUNv4i32_shift, + SQRSHRUNv8i16_shift, + SQRSHRUNv8i8_shift, + SQRSHRU_VG2_Z2ZI_H, + SQRSHRU_VG4_Z4ZI_B, + SQRSHRU_VG4_Z4ZI_H, + SQRSHR_VG2_Z2ZI_H, + SQRSHR_VG4_Z4ZI_B, + SQRSHR_VG4_Z4ZI_H, + SQSHLR_ZPmZ_B, + SQSHLR_ZPmZ_D, + SQSHLR_ZPmZ_H, + SQSHLR_ZPmZ_S, + SQSHLU_ZPmI_B, + SQSHLU_ZPmI_D, + SQSHLU_ZPmI_H, + SQSHLU_ZPmI_S, + SQSHLUb, + SQSHLUd, + SQSHLUh, + SQSHLUs, + SQSHLUv16i8_shift, + SQSHLUv2i32_shift, + SQSHLUv2i64_shift, + SQSHLUv4i16_shift, + SQSHLUv4i32_shift, + SQSHLUv8i16_shift, + SQSHLUv8i8_shift, + SQSHL_ZPmI_B, + SQSHL_ZPmI_D, + SQSHL_ZPmI_H, + SQSHL_ZPmI_S, + SQSHL_ZPmZ_B, + SQSHL_ZPmZ_D, + SQSHL_ZPmZ_H, + SQSHL_ZPmZ_S, + SQSHLb, + SQSHLd, + SQSHLh, + SQSHLs, + SQSHLv16i8, + SQSHLv16i8_shift, + SQSHLv1i16, + SQSHLv1i32, + SQSHLv1i64, + SQSHLv1i8, + SQSHLv2i32, + SQSHLv2i32_shift, + SQSHLv2i64, + SQSHLv2i64_shift, + SQSHLv4i16, + SQSHLv4i16_shift, + SQSHLv4i32, + SQSHLv4i32_shift, + SQSHLv8i16, + SQSHLv8i16_shift, + SQSHLv8i8, + SQSHLv8i8_shift, + SQSHRNB_ZZI_B, + SQSHRNB_ZZI_H, + SQSHRNB_ZZI_S, + SQSHRNT_ZZI_B, + SQSHRNT_ZZI_H, + SQSHRNT_ZZI_S, + SQSHRN_Z2ZI_HtoB, + SQSHRN_Z2ZI_StoH, + SQSHRNb, + SQSHRNh, + SQSHRNs, + SQSHRNv16i8_shift, + SQSHRNv2i32_shift, + SQSHRNv4i16_shift, + SQSHRNv4i32_shift, + SQSHRNv8i16_shift, + SQSHRNv8i8_shift, + SQSHRUNB_ZZI_B, + SQSHRUNB_ZZI_H, + SQSHRUNB_ZZI_S, + SQSHRUNT_ZZI_B, + SQSHRUNT_ZZI_H, + SQSHRUNT_ZZI_S, + SQSHRUN_Z2ZI_HtoB, + SQSHRUN_Z2ZI_StoH, + SQSHRUNb, + SQSHRUNh, + SQSHRUNs, + SQSHRUNv16i8_shift, + SQSHRUNv2i32_shift, + SQSHRUNv4i16_shift, + SQSHRUNv4i32_shift, + SQSHRUNv8i16_shift, + SQSHRUNv8i8_shift, + SQSUBR_ZPmZ_B, + SQSUBR_ZPmZ_D, + SQSUBR_ZPmZ_H, + SQSUBR_ZPmZ_S, + SQSUB_ZI_B, + SQSUB_ZI_D, + SQSUB_ZI_H, + SQSUB_ZI_S, + SQSUB_ZPmZ_B, + SQSUB_ZPmZ_D, + SQSUB_ZPmZ_H, + SQSUB_ZPmZ_S, + SQSUB_ZZZ_B, + SQSUB_ZZZ_D, + SQSUB_ZZZ_H, + SQSUB_ZZZ_S, + SQSUBv16i8, + SQSUBv1i16, + SQSUBv1i32, + SQSUBv1i64, + SQSUBv1i8, + SQSUBv2i32, + SQSUBv2i64, + SQSUBv4i16, + SQSUBv4i32, + SQSUBv8i16, + SQSUBv8i8, + SQXTNB_ZZ_B, + SQXTNB_ZZ_H, + SQXTNB_ZZ_S, + SQXTNT_ZZ_B, + SQXTNT_ZZ_H, + SQXTNT_ZZ_S, + SQXTNv16i8, + SQXTNv1i16, + SQXTNv1i32, + SQXTNv1i8, + SQXTNv2i32, + SQXTNv4i16, + SQXTNv4i32, + SQXTNv8i16, + SQXTNv8i8, + SQXTUNB_ZZ_B, + SQXTUNB_ZZ_H, + SQXTUNB_ZZ_S, + SQXTUNT_ZZ_B, + SQXTUNT_ZZ_H, + SQXTUNT_ZZ_S, + SQXTUNv16i8, + SQXTUNv1i16, + SQXTUNv1i32, + SQXTUNv1i8, + SQXTUNv2i32, + SQXTUNv4i16, + SQXTUNv4i32, + SQXTUNv8i16, + SQXTUNv8i8, + SRHADD_ZPmZ_B, + SRHADD_ZPmZ_D, + SRHADD_ZPmZ_H, + SRHADD_ZPmZ_S, + SRHADDv16i8, + SRHADDv2i32, + SRHADDv4i16, + SRHADDv4i32, + SRHADDv8i16, + SRHADDv8i8, + SRI_ZZI_B, + SRI_ZZI_D, + SRI_ZZI_H, + SRI_ZZI_S, + SRId, + SRIv16i8_shift, + SRIv2i32_shift, + SRIv2i64_shift, + SRIv4i16_shift, + SRIv4i32_shift, + SRIv8i16_shift, + SRIv8i8_shift, + SRSHLR_ZPmZ_B, + SRSHLR_ZPmZ_D, + SRSHLR_ZPmZ_H, + SRSHLR_ZPmZ_S, + SRSHL_VG2_2Z2Z_B, + SRSHL_VG2_2Z2Z_D, + SRSHL_VG2_2Z2Z_H, + SRSHL_VG2_2Z2Z_S, + SRSHL_VG2_2ZZ_B, + SRSHL_VG2_2ZZ_D, + SRSHL_VG2_2ZZ_H, + SRSHL_VG2_2ZZ_S, + SRSHL_VG4_4Z4Z_B, + SRSHL_VG4_4Z4Z_D, + SRSHL_VG4_4Z4Z_H, + SRSHL_VG4_4Z4Z_S, + SRSHL_VG4_4ZZ_B, + SRSHL_VG4_4ZZ_D, + SRSHL_VG4_4ZZ_H, + SRSHL_VG4_4ZZ_S, + SRSHL_ZPmZ_B, + SRSHL_ZPmZ_D, + SRSHL_ZPmZ_H, + SRSHL_ZPmZ_S, + SRSHLv16i8, + SRSHLv1i64, + SRSHLv2i32, + SRSHLv2i64, + SRSHLv4i16, + SRSHLv4i32, + SRSHLv8i16, + SRSHLv8i8, + SRSHR_ZPmI_B, + SRSHR_ZPmI_D, + SRSHR_ZPmI_H, + SRSHR_ZPmI_S, + SRSHRd, + SRSHRv16i8_shift, + SRSHRv2i32_shift, + SRSHRv2i64_shift, + SRSHRv4i16_shift, + SRSHRv4i32_shift, + SRSHRv8i16_shift, + SRSHRv8i8_shift, + SRSRA_ZZI_B, + SRSRA_ZZI_D, + SRSRA_ZZI_H, + SRSRA_ZZI_S, + SRSRAd, + SRSRAv16i8_shift, + SRSRAv2i32_shift, + SRSRAv2i64_shift, + SRSRAv4i16_shift, + SRSRAv4i32_shift, + SRSRAv8i16_shift, + SRSRAv8i8_shift, + SSHLLB_ZZI_D, + SSHLLB_ZZI_H, + SSHLLB_ZZI_S, + SSHLLT_ZZI_D, + SSHLLT_ZZI_H, + SSHLLT_ZZI_S, + SSHLLv16i8_shift, + SSHLLv2i32_shift, + SSHLLv4i16_shift, + SSHLLv4i32_shift, + SSHLLv8i16_shift, + SSHLLv8i8_shift, + SSHLv16i8, + SSHLv1i64, + SSHLv2i32, + SSHLv2i64, + SSHLv4i16, + SSHLv4i32, + SSHLv8i16, + SSHLv8i8, + SSHRd, + SSHRv16i8_shift, + SSHRv2i32_shift, + SSHRv2i64_shift, + SSHRv4i16_shift, + SSHRv4i32_shift, + SSHRv8i16_shift, + SSHRv8i8_shift, + SSRA_ZZI_B, + SSRA_ZZI_D, + SSRA_ZZI_H, + SSRA_ZZI_S, + SSRAd, + SSRAv16i8_shift, + SSRAv2i32_shift, + SSRAv2i64_shift, + SSRAv4i16_shift, + SSRAv4i32_shift, + SSRAv8i16_shift, + SSRAv8i8_shift, + SST1B_D, + SST1B_D_IMM, + SST1B_D_SXTW, + SST1B_D_UXTW, + SST1B_S_IMM, + SST1B_S_SXTW, + SST1B_S_UXTW, + SST1D, + SST1D_IMM, + SST1D_SCALED, + SST1D_SXTW, + SST1D_SXTW_SCALED, + SST1D_UXTW, + SST1D_UXTW_SCALED, + SST1H_D, + SST1H_D_IMM, + SST1H_D_SCALED, + SST1H_D_SXTW, + SST1H_D_SXTW_SCALED, + SST1H_D_UXTW, + SST1H_D_UXTW_SCALED, + SST1H_S_IMM, + SST1H_S_SXTW, + SST1H_S_SXTW_SCALED, + SST1H_S_UXTW, + SST1H_S_UXTW_SCALED, + SST1Q, + SST1W_D, + SST1W_D_IMM, + SST1W_D_SCALED, + SST1W_D_SXTW, + SST1W_D_SXTW_SCALED, + SST1W_D_UXTW, + SST1W_D_UXTW_SCALED, + SST1W_IMM, + SST1W_SXTW, + SST1W_SXTW_SCALED, + SST1W_UXTW, + SST1W_UXTW_SCALED, + SSUBLBT_ZZZ_D, + SSUBLBT_ZZZ_H, + SSUBLBT_ZZZ_S, + SSUBLB_ZZZ_D, + SSUBLB_ZZZ_H, + SSUBLB_ZZZ_S, + SSUBLTB_ZZZ_D, + SSUBLTB_ZZZ_H, + SSUBLTB_ZZZ_S, + SSUBLT_ZZZ_D, + SSUBLT_ZZZ_H, + SSUBLT_ZZZ_S, + SSUBLv16i8_v8i16, + SSUBLv2i32_v2i64, + SSUBLv4i16_v4i32, + SSUBLv4i32_v2i64, + SSUBLv8i16_v4i32, + SSUBLv8i8_v8i16, + SSUBWB_ZZZ_D, + SSUBWB_ZZZ_H, + SSUBWB_ZZZ_S, + SSUBWT_ZZZ_D, + SSUBWT_ZZZ_H, + SSUBWT_ZZZ_S, + SSUBWv16i8_v8i16, + SSUBWv2i32_v2i64, + SSUBWv4i16_v4i32, + SSUBWv4i32_v2i64, + SSUBWv8i16_v4i32, + SSUBWv8i8_v8i16, + ST1B, + ST1B_2Z, + ST1B_2Z_IMM, + ST1B_2Z_STRIDED, + ST1B_2Z_STRIDED_IMM, + ST1B_4Z, + ST1B_4Z_IMM, + ST1B_4Z_STRIDED, + ST1B_4Z_STRIDED_IMM, + ST1B_D, + ST1B_D_IMM, + ST1B_H, + ST1B_H_IMM, + ST1B_IMM, + ST1B_S, + ST1B_S_IMM, + ST1D, + ST1D_2Z, + ST1D_2Z_IMM, + ST1D_2Z_STRIDED, + ST1D_2Z_STRIDED_IMM, + ST1D_4Z, + ST1D_4Z_IMM, + ST1D_4Z_STRIDED, + ST1D_4Z_STRIDED_IMM, + ST1D_IMM, + ST1D_Q, + ST1D_Q_IMM, + ST1Fourv16b, + ST1Fourv16b_POST, + ST1Fourv1d, + ST1Fourv1d_POST, + ST1Fourv2d, + ST1Fourv2d_POST, + ST1Fourv2s, + ST1Fourv2s_POST, + ST1Fourv4h, + ST1Fourv4h_POST, + ST1Fourv4s, + ST1Fourv4s_POST, + ST1Fourv8b, + ST1Fourv8b_POST, + ST1Fourv8h, + ST1Fourv8h_POST, + ST1H, + ST1H_2Z, + ST1H_2Z_IMM, + ST1H_2Z_STRIDED, + ST1H_2Z_STRIDED_IMM, + ST1H_4Z, + ST1H_4Z_IMM, + ST1H_4Z_STRIDED, + ST1H_4Z_STRIDED_IMM, + ST1H_D, + ST1H_D_IMM, + ST1H_IMM, + ST1H_S, + ST1H_S_IMM, + ST1Onev16b, + ST1Onev16b_POST, + ST1Onev1d, + ST1Onev1d_POST, + ST1Onev2d, + ST1Onev2d_POST, + ST1Onev2s, + ST1Onev2s_POST, + ST1Onev4h, + ST1Onev4h_POST, + ST1Onev4s, + ST1Onev4s_POST, + ST1Onev8b, + ST1Onev8b_POST, + ST1Onev8h, + ST1Onev8h_POST, + ST1Threev16b, + ST1Threev16b_POST, + ST1Threev1d, + ST1Threev1d_POST, + ST1Threev2d, + ST1Threev2d_POST, + ST1Threev2s, + ST1Threev2s_POST, + ST1Threev4h, + ST1Threev4h_POST, + ST1Threev4s, + ST1Threev4s_POST, + ST1Threev8b, + ST1Threev8b_POST, + ST1Threev8h, + ST1Threev8h_POST, + ST1Twov16b, + ST1Twov16b_POST, + ST1Twov1d, + ST1Twov1d_POST, + ST1Twov2d, + ST1Twov2d_POST, + ST1Twov2s, + ST1Twov2s_POST, + ST1Twov4h, + ST1Twov4h_POST, + ST1Twov4s, + ST1Twov4s_POST, + ST1Twov8b, + ST1Twov8b_POST, + ST1Twov8h, + ST1Twov8h_POST, + ST1W, + ST1W_2Z, + ST1W_2Z_IMM, + ST1W_2Z_STRIDED, + ST1W_2Z_STRIDED_IMM, + ST1W_4Z, + ST1W_4Z_IMM, + ST1W_4Z_STRIDED, + ST1W_4Z_STRIDED_IMM, + ST1W_D, + ST1W_D_IMM, + ST1W_IMM, + ST1W_Q, + ST1W_Q_IMM, + ST1_MXIPXX_H_B, + ST1_MXIPXX_H_D, + ST1_MXIPXX_H_H, + ST1_MXIPXX_H_Q, + ST1_MXIPXX_H_S, + ST1_MXIPXX_V_B, + ST1_MXIPXX_V_D, + ST1_MXIPXX_V_H, + ST1_MXIPXX_V_Q, + ST1_MXIPXX_V_S, + ST1i16, + ST1i16_POST, + ST1i32, + ST1i32_POST, + ST1i64, + ST1i64_POST, + ST1i8, + ST1i8_POST, + ST2B, + ST2B_IMM, + ST2D, + ST2D_IMM, + ST2GPostIndex, + ST2GPreIndex, + ST2Gi, + ST2H, + ST2H_IMM, + ST2Q, + ST2Q_IMM, + ST2Twov16b, + ST2Twov16b_POST, + ST2Twov2d, + ST2Twov2d_POST, + ST2Twov2s, + ST2Twov2s_POST, + ST2Twov4h, + ST2Twov4h_POST, + ST2Twov4s, + ST2Twov4s_POST, + ST2Twov8b, + ST2Twov8b_POST, + ST2Twov8h, + ST2Twov8h_POST, + ST2W, + ST2W_IMM, + ST2i16, + ST2i16_POST, + ST2i32, + ST2i32_POST, + ST2i64, + ST2i64_POST, + ST2i8, + ST2i8_POST, + ST3B, + ST3B_IMM, + ST3D, + ST3D_IMM, + ST3H, + ST3H_IMM, + ST3Q, + ST3Q_IMM, + ST3Threev16b, + ST3Threev16b_POST, + ST3Threev2d, + ST3Threev2d_POST, + ST3Threev2s, + ST3Threev2s_POST, + ST3Threev4h, + ST3Threev4h_POST, + ST3Threev4s, + ST3Threev4s_POST, + ST3Threev8b, + ST3Threev8b_POST, + ST3Threev8h, + ST3Threev8h_POST, + ST3W, + ST3W_IMM, + ST3i16, + ST3i16_POST, + ST3i32, + ST3i32_POST, + ST3i64, + ST3i64_POST, + ST3i8, + ST3i8_POST, + ST4B, + ST4B_IMM, + ST4D, + ST4D_IMM, + ST4Fourv16b, + ST4Fourv16b_POST, + ST4Fourv2d, + ST4Fourv2d_POST, + ST4Fourv2s, + ST4Fourv2s_POST, + ST4Fourv4h, + ST4Fourv4h_POST, + ST4Fourv4s, + ST4Fourv4s_POST, + ST4Fourv8b, + ST4Fourv8b_POST, + ST4Fourv8h, + ST4Fourv8h_POST, + ST4H, + ST4H_IMM, + ST4Q, + ST4Q_IMM, + ST4W, + ST4W_IMM, + ST4i16, + ST4i16_POST, + ST4i32, + ST4i32_POST, + ST4i64, + ST4i64_POST, + ST4i8, + ST4i8_POST, + ST64B, + ST64BV, + ST64BV0, + STBFADD, + STBFADDL, + STBFMAX, + STBFMAXL, + STBFMAXNM, + STBFMAXNML, + STBFMIN, + STBFMINL, + STBFMINNM, + STBFMINNML, + STCPH, + STFADDD, + STFADDH, + STFADDLD, + STFADDLH, + STFADDLS, + STFADDS, + STFMAXD, + STFMAXH, + STFMAXLD, + STFMAXLH, + STFMAXLS, + STFMAXNMD, + STFMAXNMH, + STFMAXNMLD, + STFMAXNMLH, + STFMAXNMLS, + STFMAXNMS, + STFMAXS, + STFMIND, + STFMINH, + STFMINLD, + STFMINLH, + STFMINLS, + STFMINNMD, + STFMINNMH, + STFMINNMLD, + STFMINNMLH, + STFMINNMLS, + STFMINNMS, + STFMINS, + STGM, + STGPi, + STGPostIndex, + STGPpost, + STGPpre, + STGPreIndex, + STGi, + STILPW, + STILPWpre, + STILPX, + STILPXpre, + STL1, + STLLRB, + STLLRH, + STLLRW, + STLLRX, + STLPi, + STLRB, + STLRH, + STLRW, + STLRWpre, + STLRX, + STLRXpre, + STLTXRW, + STLTXRX, + STLURBi, + STLURHi, + STLURWi, + STLURXi, + STLURbi, + STLURdi, + STLURhi, + STLURqi, + STLURsi, + STLXPW, + STLXPX, + STLXRB, + STLXRH, + STLXRW, + STLXRX, + STMOPA_M2ZZZI_BtoS, + STMOPA_M2ZZZI_HtoS, + STNPDi, + STNPQi, + STNPSi, + STNPWi, + STNPXi, + STNT1B_2Z, + STNT1B_2Z_IMM, + STNT1B_2Z_STRIDED, + STNT1B_2Z_STRIDED_IMM, + STNT1B_4Z, + STNT1B_4Z_IMM, + STNT1B_4Z_STRIDED, + STNT1B_4Z_STRIDED_IMM, + STNT1B_ZRI, + STNT1B_ZRR, + STNT1B_ZZR_D, + STNT1B_ZZR_S, + STNT1D_2Z, + STNT1D_2Z_IMM, + STNT1D_2Z_STRIDED, + STNT1D_2Z_STRIDED_IMM, + STNT1D_4Z, + STNT1D_4Z_IMM, + STNT1D_4Z_STRIDED, + STNT1D_4Z_STRIDED_IMM, + STNT1D_ZRI, + STNT1D_ZRR, + STNT1D_ZZR_D, + STNT1H_2Z, + STNT1H_2Z_IMM, + STNT1H_2Z_STRIDED, + STNT1H_2Z_STRIDED_IMM, + STNT1H_4Z, + STNT1H_4Z_IMM, + STNT1H_4Z_STRIDED, + STNT1H_4Z_STRIDED_IMM, + STNT1H_ZRI, + STNT1H_ZRR, + STNT1H_ZZR_D, + STNT1H_ZZR_S, + STNT1W_2Z, + STNT1W_2Z_IMM, + STNT1W_2Z_STRIDED, + STNT1W_2Z_STRIDED_IMM, + STNT1W_4Z, + STNT1W_4Z_IMM, + STNT1W_4Z_STRIDED, + STNT1W_4Z_STRIDED_IMM, + STNT1W_ZRI, + STNT1W_ZRR, + STNT1W_ZZR_D, + STNT1W_ZZR_S, + STPDi, + STPDpost, + STPDpre, + STPQi, + STPQpost, + STPQpre, + STPSi, + STPSpost, + STPSpre, + STPWi, + STPWpost, + STPWpre, + STPXi, + STPXpost, + STPXpre, + STRBBpost, + STRBBpre, + STRBBroW, + STRBBroX, + STRBBui, + STRBpost, + STRBpre, + STRBroW, + STRBroX, + STRBui, + STRDpost, + STRDpre, + STRDroW, + STRDroX, + STRDui, + STRHHpost, + STRHHpre, + STRHHroW, + STRHHroX, + STRHHui, + STRHpost, + STRHpre, + STRHroW, + STRHroX, + STRHui, + STRQpost, + STRQpre, + STRQroW, + STRQroX, + STRQui, + STRSpost, + STRSpre, + STRSroW, + STRSroX, + STRSui, + STRWpost, + STRWpre, + STRWroW, + STRWroX, + STRWui, + STRXpost, + STRXpre, + STRXroW, + STRXroX, + STRXui, + STR_PXI, + STR_TX, + STR_ZA, + STR_ZXI, + STSHH, + STTNPQi, + STTNPXi, + STTPQi, + STTPQpost, + STTPQpre, + STTPi, + STTPpost, + STTPpre, + STTRBi, + STTRHi, + STTRWi, + STTRXi, + STTXRWr, + STTXRXr, + STURBBi, + STURBi, + STURDi, + STURHHi, + STURHi, + STURQi, + STURSi, + STURWi, + STURXi, + STXPW, + STXPX, + STXRB, + STXRH, + STXRW, + STXRX, + STZ2GPostIndex, + STZ2GPreIndex, + STZ2Gi, + STZGM, + STZGPostIndex, + STZGPreIndex, + STZGi, + SUBG, + SUBHNB_ZZZ_B, + SUBHNB_ZZZ_H, + SUBHNB_ZZZ_S, + SUBHNT_ZZZ_B, + SUBHNT_ZZZ_H, + SUBHNT_ZZZ_S, + SUBHNv2i64_v2i32, + SUBHNv2i64_v4i32, + SUBHNv4i32_v4i16, + SUBHNv4i32_v8i16, + SUBHNv8i16_v16i8, + SUBHNv8i16_v8i8, + SUBP, + SUBPS, + SUBPT_shift, + SUBP_ZPmZZ_B, + SUBP_ZPmZZ_D, + SUBP_ZPmZZ_H, + SUBP_ZPmZZ_S, + SUBR_ZI_B, + SUBR_ZI_D, + SUBR_ZI_H, + SUBR_ZI_S, + SUBR_ZPmZ_B, + SUBR_ZPmZ_D, + SUBR_ZPmZ_H, + SUBR_ZPmZ_S, + SUBSWri, + SUBSWrs, + SUBSWrx, + SUBSXri, + SUBSXrs, + SUBSXrx, + SUBSXrx64, + SUBWri, + SUBWrs, + SUBWrx, + SUBXri, + SUBXrs, + SUBXrx, + SUBXrx64, + SUB_VG2_M2Z2Z_D, + SUB_VG2_M2Z2Z_S, + SUB_VG2_M2ZZ_D, + SUB_VG2_M2ZZ_S, + SUB_VG2_M2Z_D, + SUB_VG2_M2Z_S, + SUB_VG4_M4Z4Z_D, + SUB_VG4_M4Z4Z_S, + SUB_VG4_M4ZZ_D, + SUB_VG4_M4ZZ_S, + SUB_VG4_M4Z_D, + SUB_VG4_M4Z_S, + SUB_ZI_B, + SUB_ZI_D, + SUB_ZI_H, + SUB_ZI_S, + SUB_ZPmZ_B, + SUB_ZPmZ_CPA, + SUB_ZPmZ_D, + SUB_ZPmZ_H, + SUB_ZPmZ_S, + SUB_ZZZ_B, + SUB_ZZZ_CPA, + SUB_ZZZ_D, + SUB_ZZZ_H, + SUB_ZZZ_S, + SUBv16i8, + SUBv1i64, + SUBv2i32, + SUBv2i64, + SUBv4i16, + SUBv4i32, + SUBv8i16, + SUBv8i8, + SUDOT_VG2_M2ZZI_BToS, + SUDOT_VG2_M2ZZ_BToS, + SUDOT_VG4_M4ZZI_BToS, + SUDOT_VG4_M4ZZ_BToS, + SUDOT_ZZZI, + SUDOTlanev16i8, + SUDOTlanev8i8, + SUMLALL_MZZI_BtoS, + SUMLALL_VG2_M2ZZI_BtoS, + SUMLALL_VG2_M2ZZ_BtoS, + SUMLALL_VG4_M4ZZI_BtoS, + SUMLALL_VG4_M4ZZ_BtoS, + SUMOP4A_M2Z2Z_BToS, + SUMOP4A_M2Z2Z_HtoD, + SUMOP4A_M2ZZ_BToS, + SUMOP4A_M2ZZ_HtoD, + SUMOP4A_MZ2Z_BToS, + SUMOP4A_MZ2Z_HtoD, + SUMOP4A_MZZ_BToS, + SUMOP4A_MZZ_HtoD, + SUMOP4S_M2Z2Z_BToS, + SUMOP4S_M2Z2Z_HtoD, + SUMOP4S_M2ZZ_BToS, + SUMOP4S_M2ZZ_HtoD, + SUMOP4S_MZ2Z_BToS, + SUMOP4S_MZ2Z_HtoD, + SUMOP4S_MZZ_BToS, + SUMOP4S_MZZ_HtoD, + SUMOPA_MPPZZ_D, + SUMOPA_MPPZZ_S, + SUMOPS_MPPZZ_D, + SUMOPS_MPPZZ_S, + SUNPKHI_ZZ_D, + SUNPKHI_ZZ_H, + SUNPKHI_ZZ_S, + SUNPKLO_ZZ_D, + SUNPKLO_ZZ_H, + SUNPKLO_ZZ_S, + SUNPK_VG2_2ZZ_D, + SUNPK_VG2_2ZZ_H, + SUNPK_VG2_2ZZ_S, + SUNPK_VG4_4Z2Z_D, + SUNPK_VG4_4Z2Z_H, + SUNPK_VG4_4Z2Z_S, + SUQADD_ZPmZ_B, + SUQADD_ZPmZ_D, + SUQADD_ZPmZ_H, + SUQADD_ZPmZ_S, + SUQADDv16i8, + SUQADDv1i16, + SUQADDv1i32, + SUQADDv1i64, + SUQADDv1i8, + SUQADDv2i32, + SUQADDv2i64, + SUQADDv4i16, + SUQADDv4i32, + SUQADDv8i16, + SUQADDv8i8, + SUTMOPA_M2ZZZI_BtoS, + SUVDOT_VG4_M4ZZI_BToS, + SVC, + SVDOT_VG2_M2ZZI_HtoS, + SVDOT_VG4_M4ZZI_BtoS, + SVDOT_VG4_M4ZZI_HtoD, + SWPAB, + SWPAH, + SWPALB, + SWPALH, + SWPALW, + SWPALX, + SWPAW, + SWPAX, + SWPB, + SWPH, + SWPLB, + SWPLH, + SWPLW, + SWPLX, + SWPP, + SWPPA, + SWPPAL, + SWPPL, + SWPTALW, + SWPTALX, + SWPTAW, + SWPTAX, + SWPTLW, + SWPTLX, + SWPTW, + SWPTX, + SWPW, + SWPX, + SXTB_ZPmZ_D, + SXTB_ZPmZ_H, + SXTB_ZPmZ_S, + SXTB_ZPzZ_D, + SXTB_ZPzZ_H, + SXTB_ZPzZ_S, + SXTH_ZPmZ_D, + SXTH_ZPmZ_S, + SXTH_ZPzZ_D, + SXTH_ZPzZ_S, + SXTW_ZPmZ_D, + SXTW_ZPzZ_D, + SYSLxt, + SYSPxt, + SYSPxt_XZR, + SYSxt, + TBLQ_ZZZ_B, + TBLQ_ZZZ_D, + TBLQ_ZZZ_H, + TBLQ_ZZZ_S, + TBL_ZZZZ_B, + TBL_ZZZZ_D, + TBL_ZZZZ_H, + TBL_ZZZZ_S, + TBL_ZZZ_B, + TBL_ZZZ_D, + TBL_ZZZ_H, + TBL_ZZZ_S, + TBLv16i8Four, + TBLv16i8One, + TBLv16i8Three, + TBLv16i8Two, + TBLv8i8Four, + TBLv8i8One, + TBLv8i8Three, + TBLv8i8Two, + TBNZW, + TBNZX, + TBXQ_ZZZ_B, + TBXQ_ZZZ_D, + TBXQ_ZZZ_H, + TBXQ_ZZZ_S, + TBX_ZZZ_B, + TBX_ZZZ_D, + TBX_ZZZ_H, + TBX_ZZZ_S, + TBXv16i8Four, + TBXv16i8One, + TBXv16i8Three, + TBXv16i8Two, + TBXv8i8Four, + TBXv8i8One, + TBXv8i8Three, + TBXv8i8Two, + TBZW, + TBZX, + TCHANGEBri, + TCHANGEBrr, + TCHANGEFri, + TCHANGEFrr, + TENTER, + TEXIT, + TRCIT, + TRN1_PPP_B, + TRN1_PPP_D, + TRN1_PPP_H, + TRN1_PPP_S, + TRN1_ZZZ_B, + TRN1_ZZZ_D, + TRN1_ZZZ_H, + TRN1_ZZZ_Q, + TRN1_ZZZ_S, + TRN1v16i8, + TRN1v2i32, + TRN1v2i64, + TRN1v4i16, + TRN1v4i32, + TRN1v8i16, + TRN1v8i8, + TRN2_PPP_B, + TRN2_PPP_D, + TRN2_PPP_H, + TRN2_PPP_S, + TRN2_ZZZ_B, + TRN2_ZZZ_D, + TRN2_ZZZ_H, + TRN2_ZZZ_Q, + TRN2_ZZZ_S, + TRN2v16i8, + TRN2v2i32, + TRN2v2i64, + TRN2v4i16, + TRN2v4i32, + TRN2v8i16, + TRN2v8i8, + TSB, + UABALB_ZZZ_D, + UABALB_ZZZ_H, + UABALB_ZZZ_S, + UABALT_ZZZ_D, + UABALT_ZZZ_H, + UABALT_ZZZ_S, + UABAL_ZZZ_BtoH, + UABAL_ZZZ_HtoS, + UABAL_ZZZ_StoD, + UABALv16i8_v8i16, + UABALv2i32_v2i64, + UABALv4i16_v4i32, + UABALv4i32_v2i64, + UABALv8i16_v4i32, + UABALv8i8_v8i16, + UABA_ZZZ_B, + UABA_ZZZ_D, + UABA_ZZZ_H, + UABA_ZZZ_S, + UABAv16i8, + UABAv2i32, + UABAv4i16, + UABAv4i32, + UABAv8i16, + UABAv8i8, + UABDLB_ZZZ_D, + UABDLB_ZZZ_H, + UABDLB_ZZZ_S, + UABDLT_ZZZ_D, + UABDLT_ZZZ_H, + UABDLT_ZZZ_S, + UABDLv16i8_v8i16, + UABDLv2i32_v2i64, + UABDLv4i16_v4i32, + UABDLv4i32_v2i64, + UABDLv8i16_v4i32, + UABDLv8i8_v8i16, + UABD_ZPmZ_B, + UABD_ZPmZ_D, + UABD_ZPmZ_H, + UABD_ZPmZ_S, + UABDv16i8, + UABDv2i32, + UABDv4i16, + UABDv4i32, + UABDv8i16, + UABDv8i8, + UADALP_ZPmZ_D, + UADALP_ZPmZ_H, + UADALP_ZPmZ_S, + UADALPv16i8_v8i16, + UADALPv2i32_v1i64, + UADALPv4i16_v2i32, + UADALPv4i32_v2i64, + UADALPv8i16_v4i32, + UADALPv8i8_v4i16, + UADDLB_ZZZ_D, + UADDLB_ZZZ_H, + UADDLB_ZZZ_S, + UADDLPv16i8_v8i16, + UADDLPv2i32_v1i64, + UADDLPv4i16_v2i32, + UADDLPv4i32_v2i64, + UADDLPv8i16_v4i32, + UADDLPv8i8_v4i16, + UADDLT_ZZZ_D, + UADDLT_ZZZ_H, + UADDLT_ZZZ_S, + UADDLVv16i8v, + UADDLVv4i16v, + UADDLVv4i32v, + UADDLVv8i16v, + UADDLVv8i8v, + UADDLv16i8_v8i16, + UADDLv2i32_v2i64, + UADDLv4i16_v4i32, + UADDLv4i32_v2i64, + UADDLv8i16_v4i32, + UADDLv8i8_v8i16, + UADDV_VPZ_B, + UADDV_VPZ_D, + UADDV_VPZ_H, + UADDV_VPZ_S, + UADDWB_ZZZ_D, + UADDWB_ZZZ_H, + UADDWB_ZZZ_S, + UADDWT_ZZZ_D, + UADDWT_ZZZ_H, + UADDWT_ZZZ_S, + UADDWv16i8_v8i16, + UADDWv2i32_v2i64, + UADDWv4i16_v4i32, + UADDWv4i32_v2i64, + UADDWv8i16_v4i32, + UADDWv8i8_v8i16, + UBFMWri, + UBFMXri, + UCLAMP_VG2_2Z2Z_B, + UCLAMP_VG2_2Z2Z_D, + UCLAMP_VG2_2Z2Z_H, + UCLAMP_VG2_2Z2Z_S, + UCLAMP_VG4_4Z4Z_B, + UCLAMP_VG4_4Z4Z_D, + UCLAMP_VG4_4Z4Z_H, + UCLAMP_VG4_4Z4Z_S, + UCLAMP_ZZZ_B, + UCLAMP_ZZZ_D, + UCLAMP_ZZZ_H, + UCLAMP_ZZZ_S, + UCVTFDSr, + UCVTFHDr, + UCVTFHSr, + UCVTFLT_ZZ_BtoH, + UCVTFLT_ZZ_HtoS, + UCVTFLT_ZZ_StoD, + UCVTFSDr, + UCVTFSWDri, + UCVTFSWHri, + UCVTFSWSri, + UCVTFSXDri, + UCVTFSXHri, + UCVTFSXSri, + UCVTFUWDri, + UCVTFUWHri, + UCVTFUWSri, + UCVTFUXDri, + UCVTFUXHri, + UCVTFUXSri, + UCVTF_2Z2Z_StoS, + UCVTF_4Z4Z_StoS, + UCVTF_ZPmZ_DtoD, + UCVTF_ZPmZ_DtoH, + UCVTF_ZPmZ_DtoS, + UCVTF_ZPmZ_HtoH, + UCVTF_ZPmZ_StoD, + UCVTF_ZPmZ_StoH, + UCVTF_ZPmZ_StoS, + UCVTF_ZPzZ_DtoD, + UCVTF_ZPzZ_DtoH, + UCVTF_ZPzZ_DtoS, + UCVTF_ZPzZ_HtoH, + UCVTF_ZPzZ_StoD, + UCVTF_ZPzZ_StoH, + UCVTF_ZPzZ_StoS, + UCVTF_ZZ_BtoH, + UCVTF_ZZ_HtoS, + UCVTF_ZZ_StoD, + UCVTFd, + UCVTFh, + UCVTFs, + UCVTFv1i16, + UCVTFv1i32, + UCVTFv1i64, + UCVTFv2f32, + UCVTFv2f64, + UCVTFv2i32_shift, + UCVTFv2i64_shift, + UCVTFv4f16, + UCVTFv4f32, + UCVTFv4i16_shift, + UCVTFv4i32_shift, + UCVTFv8f16, + UCVTFv8i16_shift, + UDF, + UDIVR_ZPmZ_D, + UDIVR_ZPmZ_S, + UDIVWr, + UDIVXr, + UDIV_ZPmZ_D, + UDIV_ZPmZ_S, + UDOT_VG2_M2Z2Z_BtoS, + UDOT_VG2_M2Z2Z_HtoD, + UDOT_VG2_M2Z2Z_HtoS, + UDOT_VG2_M2ZZI_BToS, + UDOT_VG2_M2ZZI_HToS, + UDOT_VG2_M2ZZI_HtoD, + UDOT_VG2_M2ZZ_BtoS, + UDOT_VG2_M2ZZ_HtoD, + UDOT_VG2_M2ZZ_HtoS, + UDOT_VG4_M4Z4Z_BtoS, + UDOT_VG4_M4Z4Z_HtoD, + UDOT_VG4_M4Z4Z_HtoS, + UDOT_VG4_M4ZZI_BtoS, + UDOT_VG4_M4ZZI_HToS, + UDOT_VG4_M4ZZI_HtoD, + UDOT_VG4_M4ZZ_BtoS, + UDOT_VG4_M4ZZ_HtoD, + UDOT_VG4_M4ZZ_HtoS, + UDOT_ZZZI_BtoH, + UDOT_ZZZI_BtoS, + UDOT_ZZZI_HtoD, + UDOT_ZZZI_HtoS, + UDOT_ZZZ_BtoH, + UDOT_ZZZ_BtoS, + UDOT_ZZZ_HtoD, + UDOT_ZZZ_HtoS, + UDOTlanev16i8, + UDOTlanev8i8, + UDOTv16i8, + UDOTv8i8, + UHADD_ZPmZ_B, + UHADD_ZPmZ_D, + UHADD_ZPmZ_H, + UHADD_ZPmZ_S, + UHADDv16i8, + UHADDv2i32, + UHADDv4i16, + UHADDv4i32, + UHADDv8i16, + UHADDv8i8, + UHSUBR_ZPmZ_B, + UHSUBR_ZPmZ_D, + UHSUBR_ZPmZ_H, + UHSUBR_ZPmZ_S, + UHSUB_ZPmZ_B, + UHSUB_ZPmZ_D, + UHSUB_ZPmZ_H, + UHSUB_ZPmZ_S, + UHSUBv16i8, + UHSUBv2i32, + UHSUBv4i16, + UHSUBv4i32, + UHSUBv8i16, + UHSUBv8i8, + UMADDLrrr, + UMAXP_ZPmZ_B, + UMAXP_ZPmZ_D, + UMAXP_ZPmZ_H, + UMAXP_ZPmZ_S, + UMAXPv16i8, + UMAXPv2i32, + UMAXPv4i16, + UMAXPv4i32, + UMAXPv8i16, + UMAXPv8i8, + UMAXQV_VPZ_B, + UMAXQV_VPZ_D, + UMAXQV_VPZ_H, + UMAXQV_VPZ_S, + UMAXV_VPZ_B, + UMAXV_VPZ_D, + UMAXV_VPZ_H, + UMAXV_VPZ_S, + UMAXVv16i8v, + UMAXVv4i16v, + UMAXVv4i32v, + UMAXVv8i16v, + UMAXVv8i8v, + UMAXWri, + UMAXWrr, + UMAXXri, + UMAXXrr, + UMAX_VG2_2Z2Z_B, + UMAX_VG2_2Z2Z_D, + UMAX_VG2_2Z2Z_H, + UMAX_VG2_2Z2Z_S, + UMAX_VG2_2ZZ_B, + UMAX_VG2_2ZZ_D, + UMAX_VG2_2ZZ_H, + UMAX_VG2_2ZZ_S, + UMAX_VG4_4Z4Z_B, + UMAX_VG4_4Z4Z_D, + UMAX_VG4_4Z4Z_H, + UMAX_VG4_4Z4Z_S, + UMAX_VG4_4ZZ_B, + UMAX_VG4_4ZZ_D, + UMAX_VG4_4ZZ_H, + UMAX_VG4_4ZZ_S, + UMAX_ZI_B, + UMAX_ZI_D, + UMAX_ZI_H, + UMAX_ZI_S, + UMAX_ZPmZ_B, + UMAX_ZPmZ_D, + UMAX_ZPmZ_H, + UMAX_ZPmZ_S, + UMAXv16i8, + UMAXv2i32, + UMAXv4i16, + UMAXv4i32, + UMAXv8i16, + UMAXv8i8, + UMINP_ZPmZ_B, + UMINP_ZPmZ_D, + UMINP_ZPmZ_H, + UMINP_ZPmZ_S, + UMINPv16i8, + UMINPv2i32, + UMINPv4i16, + UMINPv4i32, + UMINPv8i16, + UMINPv8i8, + UMINQV_VPZ_B, + UMINQV_VPZ_D, + UMINQV_VPZ_H, + UMINQV_VPZ_S, + UMINV_VPZ_B, + UMINV_VPZ_D, + UMINV_VPZ_H, + UMINV_VPZ_S, + UMINVv16i8v, + UMINVv4i16v, + UMINVv4i32v, + UMINVv8i16v, + UMINVv8i8v, + UMINWri, + UMINWrr, + UMINXri, + UMINXrr, + UMIN_VG2_2Z2Z_B, + UMIN_VG2_2Z2Z_D, + UMIN_VG2_2Z2Z_H, + UMIN_VG2_2Z2Z_S, + UMIN_VG2_2ZZ_B, + UMIN_VG2_2ZZ_D, + UMIN_VG2_2ZZ_H, + UMIN_VG2_2ZZ_S, + UMIN_VG4_4Z4Z_B, + UMIN_VG4_4Z4Z_D, + UMIN_VG4_4Z4Z_H, + UMIN_VG4_4Z4Z_S, + UMIN_VG4_4ZZ_B, + UMIN_VG4_4ZZ_D, + UMIN_VG4_4ZZ_H, + UMIN_VG4_4ZZ_S, + UMIN_ZI_B, + UMIN_ZI_D, + UMIN_ZI_H, + UMIN_ZI_S, + UMIN_ZPmZ_B, + UMIN_ZPmZ_D, + UMIN_ZPmZ_H, + UMIN_ZPmZ_S, + UMINv16i8, + UMINv2i32, + UMINv4i16, + UMINv4i32, + UMINv8i16, + UMINv8i8, + UMLALB_ZZZI_D, + UMLALB_ZZZI_S, + UMLALB_ZZZ_D, + UMLALB_ZZZ_H, + UMLALB_ZZZ_S, + UMLALL_MZZI_BtoS, + UMLALL_MZZI_HtoD, + UMLALL_MZZ_BtoS, + UMLALL_MZZ_HtoD, + UMLALL_VG2_M2Z2Z_BtoS, + UMLALL_VG2_M2Z2Z_HtoD, + UMLALL_VG2_M2ZZI_BtoS, + UMLALL_VG2_M2ZZI_HtoD, + UMLALL_VG2_M2ZZ_BtoS, + UMLALL_VG2_M2ZZ_HtoD, + UMLALL_VG4_M4Z4Z_BtoS, + UMLALL_VG4_M4Z4Z_HtoD, + UMLALL_VG4_M4ZZI_BtoS, + UMLALL_VG4_M4ZZI_HtoD, + UMLALL_VG4_M4ZZ_BtoS, + UMLALL_VG4_M4ZZ_HtoD, + UMLALT_ZZZI_D, + UMLALT_ZZZI_S, + UMLALT_ZZZ_D, + UMLALT_ZZZ_H, + UMLALT_ZZZ_S, + UMLAL_MZZI_HtoS, + UMLAL_MZZ_HtoS, + UMLAL_VG2_M2Z2Z_HtoS, + UMLAL_VG2_M2ZZI_S, + UMLAL_VG2_M2ZZ_HtoS, + UMLAL_VG4_M4Z4Z_HtoS, + UMLAL_VG4_M4ZZI_HtoS, + UMLAL_VG4_M4ZZ_HtoS, + UMLALv16i8_v8i16, + UMLALv2i32_indexed, + UMLALv2i32_v2i64, + UMLALv4i16_indexed, + UMLALv4i16_v4i32, + UMLALv4i32_indexed, + UMLALv4i32_v2i64, + UMLALv8i16_indexed, + UMLALv8i16_v4i32, + UMLALv8i8_v8i16, + UMLSLB_ZZZI_D, + UMLSLB_ZZZI_S, + UMLSLB_ZZZ_D, + UMLSLB_ZZZ_H, + UMLSLB_ZZZ_S, + UMLSLL_MZZI_BtoS, + UMLSLL_MZZI_HtoD, + UMLSLL_MZZ_BtoS, + UMLSLL_MZZ_HtoD, + UMLSLL_VG2_M2Z2Z_BtoS, + UMLSLL_VG2_M2Z2Z_HtoD, + UMLSLL_VG2_M2ZZI_BtoS, + UMLSLL_VG2_M2ZZI_HtoD, + UMLSLL_VG2_M2ZZ_BtoS, + UMLSLL_VG2_M2ZZ_HtoD, + UMLSLL_VG4_M4Z4Z_BtoS, + UMLSLL_VG4_M4Z4Z_HtoD, + UMLSLL_VG4_M4ZZI_BtoS, + UMLSLL_VG4_M4ZZI_HtoD, + UMLSLL_VG4_M4ZZ_BtoS, + UMLSLL_VG4_M4ZZ_HtoD, + UMLSLT_ZZZI_D, + UMLSLT_ZZZI_S, + UMLSLT_ZZZ_D, + UMLSLT_ZZZ_H, + UMLSLT_ZZZ_S, + UMLSL_MZZI_HtoS, + UMLSL_MZZ_HtoS, + UMLSL_VG2_M2Z2Z_HtoS, + UMLSL_VG2_M2ZZI_S, + UMLSL_VG2_M2ZZ_HtoS, + UMLSL_VG4_M4Z4Z_HtoS, + UMLSL_VG4_M4ZZI_HtoS, + UMLSL_VG4_M4ZZ_HtoS, + UMLSLv16i8_v8i16, + UMLSLv2i32_indexed, + UMLSLv2i32_v2i64, + UMLSLv4i16_indexed, + UMLSLv4i16_v4i32, + UMLSLv4i32_indexed, + UMLSLv4i32_v2i64, + UMLSLv8i16_indexed, + UMLSLv8i16_v4i32, + UMLSLv8i8_v8i16, + UMMLA, + UMMLA_ZZZ, + UMOP4A_M2Z2Z_BToS, + UMOP4A_M2Z2Z_HToS, + UMOP4A_M2Z2Z_HtoD, + UMOP4A_M2ZZ_BToS, + UMOP4A_M2ZZ_HToS, + UMOP4A_M2ZZ_HtoD, + UMOP4A_MZ2Z_BToS, + UMOP4A_MZ2Z_HToS, + UMOP4A_MZ2Z_HtoD, + UMOP4A_MZZ_BToS, + UMOP4A_MZZ_HToS, + UMOP4A_MZZ_HtoD, + UMOP4S_M2Z2Z_BToS, + UMOP4S_M2Z2Z_HToS, + UMOP4S_M2Z2Z_HtoD, + UMOP4S_M2ZZ_BToS, + UMOP4S_M2ZZ_HToS, + UMOP4S_M2ZZ_HtoD, + UMOP4S_MZ2Z_BToS, + UMOP4S_MZ2Z_HToS, + UMOP4S_MZ2Z_HtoD, + UMOP4S_MZZ_BToS, + UMOP4S_MZZ_HToS, + UMOP4S_MZZ_HtoD, + UMOPA_MPPZZ_D, + UMOPA_MPPZZ_HtoS, + UMOPA_MPPZZ_S, + UMOPS_MPPZZ_D, + UMOPS_MPPZZ_HtoS, + UMOPS_MPPZZ_S, + UMOVvi16, + UMOVvi16_idx0, + UMOVvi32, + UMOVvi32_idx0, + UMOVvi64, + UMOVvi64_idx0, + UMOVvi8, + UMOVvi8_idx0, + UMSUBLrrr, + UMULH_ZPmZ_B, + UMULH_ZPmZ_D, + UMULH_ZPmZ_H, + UMULH_ZPmZ_S, + UMULH_ZZZ_B, + UMULH_ZZZ_D, + UMULH_ZZZ_H, + UMULH_ZZZ_S, + UMULHrr, + UMULLB_ZZZI_D, + UMULLB_ZZZI_S, + UMULLB_ZZZ_D, + UMULLB_ZZZ_H, + UMULLB_ZZZ_S, + UMULLT_ZZZI_D, + UMULLT_ZZZI_S, + UMULLT_ZZZ_D, + UMULLT_ZZZ_H, + UMULLT_ZZZ_S, + UMULLv16i8_v8i16, + UMULLv2i32_indexed, + UMULLv2i32_v2i64, + UMULLv4i16_indexed, + UMULLv4i16_v4i32, + UMULLv4i32_indexed, + UMULLv4i32_v2i64, + UMULLv8i16_indexed, + UMULLv8i16_v4i32, + UMULLv8i8_v8i16, + UQADD_ZI_B, + UQADD_ZI_D, + UQADD_ZI_H, + UQADD_ZI_S, + UQADD_ZPmZ_B, + UQADD_ZPmZ_D, + UQADD_ZPmZ_H, + UQADD_ZPmZ_S, + UQADD_ZZZ_B, + UQADD_ZZZ_D, + UQADD_ZZZ_H, + UQADD_ZZZ_S, + UQADDv16i8, + UQADDv1i16, + UQADDv1i32, + UQADDv1i64, + UQADDv1i8, + UQADDv2i32, + UQADDv2i64, + UQADDv4i16, + UQADDv4i32, + UQADDv8i16, + UQADDv8i8, + UQCVTN_Z2Z_StoH, + UQCVTN_Z4Z_DtoH, + UQCVTN_Z4Z_StoB, + UQCVT_Z2Z_StoH, + UQCVT_Z4Z_DtoH, + UQCVT_Z4Z_StoB, + UQDECB_WPiI, + UQDECB_XPiI, + UQDECD_WPiI, + UQDECD_XPiI, + UQDECD_ZPiI, + UQDECH_WPiI, + UQDECH_XPiI, + UQDECH_ZPiI, + UQDECP_WP_B, + UQDECP_WP_D, + UQDECP_WP_H, + UQDECP_WP_S, + UQDECP_XP_B, + UQDECP_XP_D, + UQDECP_XP_H, + UQDECP_XP_S, + UQDECP_ZP_D, + UQDECP_ZP_H, + UQDECP_ZP_S, + UQDECW_WPiI, + UQDECW_XPiI, + UQDECW_ZPiI, + UQINCB_WPiI, + UQINCB_XPiI, + UQINCD_WPiI, + UQINCD_XPiI, + UQINCD_ZPiI, + UQINCH_WPiI, + UQINCH_XPiI, + UQINCH_ZPiI, + UQINCP_WP_B, + UQINCP_WP_D, + UQINCP_WP_H, + UQINCP_WP_S, + UQINCP_XP_B, + UQINCP_XP_D, + UQINCP_XP_H, + UQINCP_XP_S, + UQINCP_ZP_D, + UQINCP_ZP_H, + UQINCP_ZP_S, + UQINCW_WPiI, + UQINCW_XPiI, + UQINCW_ZPiI, + UQRSHLR_ZPmZ_B, + UQRSHLR_ZPmZ_D, + UQRSHLR_ZPmZ_H, + UQRSHLR_ZPmZ_S, + UQRSHL_ZPmZ_B, + UQRSHL_ZPmZ_D, + UQRSHL_ZPmZ_H, + UQRSHL_ZPmZ_S, + UQRSHLv16i8, + UQRSHLv1i16, + UQRSHLv1i32, + UQRSHLv1i64, + UQRSHLv1i8, + UQRSHLv2i32, + UQRSHLv2i64, + UQRSHLv4i16, + UQRSHLv4i32, + UQRSHLv8i16, + UQRSHLv8i8, + UQRSHRNB_ZZI_B, + UQRSHRNB_ZZI_H, + UQRSHRNB_ZZI_S, + UQRSHRNT_ZZI_B, + UQRSHRNT_ZZI_H, + UQRSHRNT_ZZI_S, + UQRSHRN_VG4_Z4ZI_B, + UQRSHRN_VG4_Z4ZI_H, + UQRSHRN_Z2ZI_HtoB, + UQRSHRN_Z2ZI_StoH, + UQRSHRNb, + UQRSHRNh, + UQRSHRNs, + UQRSHRNv16i8_shift, + UQRSHRNv2i32_shift, + UQRSHRNv4i16_shift, + UQRSHRNv4i32_shift, + UQRSHRNv8i16_shift, + UQRSHRNv8i8_shift, + UQRSHR_VG2_Z2ZI_H, + UQRSHR_VG4_Z4ZI_B, + UQRSHR_VG4_Z4ZI_H, + UQSHLR_ZPmZ_B, + UQSHLR_ZPmZ_D, + UQSHLR_ZPmZ_H, + UQSHLR_ZPmZ_S, + UQSHL_ZPmI_B, + UQSHL_ZPmI_D, + UQSHL_ZPmI_H, + UQSHL_ZPmI_S, + UQSHL_ZPmZ_B, + UQSHL_ZPmZ_D, + UQSHL_ZPmZ_H, + UQSHL_ZPmZ_S, + UQSHLb, + UQSHLd, + UQSHLh, + UQSHLs, + UQSHLv16i8, + UQSHLv16i8_shift, + UQSHLv1i16, + UQSHLv1i32, + UQSHLv1i64, + UQSHLv1i8, + UQSHLv2i32, + UQSHLv2i32_shift, + UQSHLv2i64, + UQSHLv2i64_shift, + UQSHLv4i16, + UQSHLv4i16_shift, + UQSHLv4i32, + UQSHLv4i32_shift, + UQSHLv8i16, + UQSHLv8i16_shift, + UQSHLv8i8, + UQSHLv8i8_shift, + UQSHRNB_ZZI_B, + UQSHRNB_ZZI_H, + UQSHRNB_ZZI_S, + UQSHRNT_ZZI_B, + UQSHRNT_ZZI_H, + UQSHRNT_ZZI_S, + UQSHRN_Z2ZI_HtoB, + UQSHRN_Z2ZI_StoH, + UQSHRNb, + UQSHRNh, + UQSHRNs, + UQSHRNv16i8_shift, + UQSHRNv2i32_shift, + UQSHRNv4i16_shift, + UQSHRNv4i32_shift, + UQSHRNv8i16_shift, + UQSHRNv8i8_shift, + UQSUBR_ZPmZ_B, + UQSUBR_ZPmZ_D, + UQSUBR_ZPmZ_H, + UQSUBR_ZPmZ_S, + UQSUB_ZI_B, + UQSUB_ZI_D, + UQSUB_ZI_H, + UQSUB_ZI_S, + UQSUB_ZPmZ_B, + UQSUB_ZPmZ_D, + UQSUB_ZPmZ_H, + UQSUB_ZPmZ_S, + UQSUB_ZZZ_B, + UQSUB_ZZZ_D, + UQSUB_ZZZ_H, + UQSUB_ZZZ_S, + UQSUBv16i8, + UQSUBv1i16, + UQSUBv1i32, + UQSUBv1i64, + UQSUBv1i8, + UQSUBv2i32, + UQSUBv2i64, + UQSUBv4i16, + UQSUBv4i32, + UQSUBv8i16, + UQSUBv8i8, + UQXTNB_ZZ_B, + UQXTNB_ZZ_H, + UQXTNB_ZZ_S, + UQXTNT_ZZ_B, + UQXTNT_ZZ_H, + UQXTNT_ZZ_S, + UQXTNv16i8, + UQXTNv1i16, + UQXTNv1i32, + UQXTNv1i8, + UQXTNv2i32, + UQXTNv4i16, + UQXTNv4i32, + UQXTNv8i16, + UQXTNv8i8, + URECPE_ZPmZ_S, + URECPE_ZPzZ_S, + URECPEv2i32, + URECPEv4i32, + URHADD_ZPmZ_B, + URHADD_ZPmZ_D, + URHADD_ZPmZ_H, + URHADD_ZPmZ_S, + URHADDv16i8, + URHADDv2i32, + URHADDv4i16, + URHADDv4i32, + URHADDv8i16, + URHADDv8i8, + URSHLR_ZPmZ_B, + URSHLR_ZPmZ_D, + URSHLR_ZPmZ_H, + URSHLR_ZPmZ_S, + URSHL_VG2_2Z2Z_B, + URSHL_VG2_2Z2Z_D, + URSHL_VG2_2Z2Z_H, + URSHL_VG2_2Z2Z_S, + URSHL_VG2_2ZZ_B, + URSHL_VG2_2ZZ_D, + URSHL_VG2_2ZZ_H, + URSHL_VG2_2ZZ_S, + URSHL_VG4_4Z4Z_B, + URSHL_VG4_4Z4Z_D, + URSHL_VG4_4Z4Z_H, + URSHL_VG4_4Z4Z_S, + URSHL_VG4_4ZZ_B, + URSHL_VG4_4ZZ_D, + URSHL_VG4_4ZZ_H, + URSHL_VG4_4ZZ_S, + URSHL_ZPmZ_B, + URSHL_ZPmZ_D, + URSHL_ZPmZ_H, + URSHL_ZPmZ_S, + URSHLv16i8, + URSHLv1i64, + URSHLv2i32, + URSHLv2i64, + URSHLv4i16, + URSHLv4i32, + URSHLv8i16, + URSHLv8i8, + URSHR_ZPmI_B, + URSHR_ZPmI_D, + URSHR_ZPmI_H, + URSHR_ZPmI_S, + URSHRd, + URSHRv16i8_shift, + URSHRv2i32_shift, + URSHRv2i64_shift, + URSHRv4i16_shift, + URSHRv4i32_shift, + URSHRv8i16_shift, + URSHRv8i8_shift, + URSQRTE_ZPmZ_S, + URSQRTE_ZPzZ_S, + URSQRTEv2i32, + URSQRTEv4i32, + URSRA_ZZI_B, + URSRA_ZZI_D, + URSRA_ZZI_H, + URSRA_ZZI_S, + URSRAd, + URSRAv16i8_shift, + URSRAv2i32_shift, + URSRAv2i64_shift, + URSRAv4i16_shift, + URSRAv4i32_shift, + URSRAv8i16_shift, + URSRAv8i8_shift, + USDOT_VG2_M2Z2Z_BToS, + USDOT_VG2_M2ZZI_BToS, + USDOT_VG2_M2ZZ_BToS, + USDOT_VG4_M4Z4Z_BToS, + USDOT_VG4_M4ZZI_BToS, + USDOT_VG4_M4ZZ_BToS, + USDOT_ZZZ, + USDOT_ZZZI, + USDOTlanev16i8, + USDOTlanev8i8, + USDOTv16i8, + USDOTv8i8, + USHLLB_ZZI_D, + USHLLB_ZZI_H, + USHLLB_ZZI_S, + USHLLT_ZZI_D, + USHLLT_ZZI_H, + USHLLT_ZZI_S, + USHLLv16i8_shift, + USHLLv2i32_shift, + USHLLv4i16_shift, + USHLLv4i32_shift, + USHLLv8i16_shift, + USHLLv8i8_shift, + USHLv16i8, + USHLv1i64, + USHLv2i32, + USHLv2i64, + USHLv4i16, + USHLv4i32, + USHLv8i16, + USHLv8i8, + USHRd, + USHRv16i8_shift, + USHRv2i32_shift, + USHRv2i64_shift, + USHRv4i16_shift, + USHRv4i32_shift, + USHRv8i16_shift, + USHRv8i8_shift, + USMLALL_MZZI_BtoS, + USMLALL_MZZ_BtoS, + USMLALL_VG2_M2Z2Z_BtoS, + USMLALL_VG2_M2ZZI_BtoS, + USMLALL_VG2_M2ZZ_BtoS, + USMLALL_VG4_M4Z4Z_BtoS, + USMLALL_VG4_M4ZZI_BtoS, + USMLALL_VG4_M4ZZ_BtoS, + USMMLA, + USMMLA_ZZZ, + USMOP4A_M2Z2Z_BToS, + USMOP4A_M2Z2Z_HtoD, + USMOP4A_M2ZZ_BToS, + USMOP4A_M2ZZ_HtoD, + USMOP4A_MZ2Z_BToS, + USMOP4A_MZ2Z_HtoD, + USMOP4A_MZZ_BToS, + USMOP4A_MZZ_HtoD, + USMOP4S_M2Z2Z_BToS, + USMOP4S_M2Z2Z_HtoD, + USMOP4S_M2ZZ_BToS, + USMOP4S_M2ZZ_HtoD, + USMOP4S_MZ2Z_BToS, + USMOP4S_MZ2Z_HtoD, + USMOP4S_MZZ_BToS, + USMOP4S_MZZ_HtoD, + USMOPA_MPPZZ_D, + USMOPA_MPPZZ_S, + USMOPS_MPPZZ_D, + USMOPS_MPPZZ_S, + USQADD_ZPmZ_B, + USQADD_ZPmZ_D, + USQADD_ZPmZ_H, + USQADD_ZPmZ_S, + USQADDv16i8, + USQADDv1i16, + USQADDv1i32, + USQADDv1i64, + USQADDv1i8, + USQADDv2i32, + USQADDv2i64, + USQADDv4i16, + USQADDv4i32, + USQADDv8i16, + USQADDv8i8, + USRA_ZZI_B, + USRA_ZZI_D, + USRA_ZZI_H, + USRA_ZZI_S, + USRAd, + USRAv16i8_shift, + USRAv2i32_shift, + USRAv2i64_shift, + USRAv4i16_shift, + USRAv4i32_shift, + USRAv8i16_shift, + USRAv8i8_shift, + USTMOPA_M2ZZZI_BtoS, + USUBLB_ZZZ_D, + USUBLB_ZZZ_H, + USUBLB_ZZZ_S, + USUBLT_ZZZ_D, + USUBLT_ZZZ_H, + USUBLT_ZZZ_S, + USUBLv16i8_v8i16, + USUBLv2i32_v2i64, + USUBLv4i16_v4i32, + USUBLv4i32_v2i64, + USUBLv8i16_v4i32, + USUBLv8i8_v8i16, + USUBWB_ZZZ_D, + USUBWB_ZZZ_H, + USUBWB_ZZZ_S, + USUBWT_ZZZ_D, + USUBWT_ZZZ_H, + USUBWT_ZZZ_S, + USUBWv16i8_v8i16, + USUBWv2i32_v2i64, + USUBWv4i16_v4i32, + USUBWv4i32_v2i64, + USUBWv8i16_v4i32, + USUBWv8i8_v8i16, + USVDOT_VG4_M4ZZI_BToS, + UTMOPA_M2ZZZI_BtoS, + UTMOPA_M2ZZZI_HtoS, + UUNPKHI_ZZ_D, + UUNPKHI_ZZ_H, + UUNPKHI_ZZ_S, + UUNPKLO_ZZ_D, + UUNPKLO_ZZ_H, + UUNPKLO_ZZ_S, + UUNPK_VG2_2ZZ_D, + UUNPK_VG2_2ZZ_H, + UUNPK_VG2_2ZZ_S, + UUNPK_VG4_4Z2Z_D, + UUNPK_VG4_4Z2Z_H, + UUNPK_VG4_4Z2Z_S, + UVDOT_VG2_M2ZZI_HtoS, + UVDOT_VG4_M4ZZI_BtoS, + UVDOT_VG4_M4ZZI_HtoD, + UXTB_ZPmZ_D, + UXTB_ZPmZ_H, + UXTB_ZPmZ_S, + UXTB_ZPzZ_D, + UXTB_ZPzZ_H, + UXTB_ZPzZ_S, + UXTH_ZPmZ_D, + UXTH_ZPmZ_S, + UXTH_ZPzZ_D, + UXTH_ZPzZ_S, + UXTW_ZPmZ_D, + UXTW_ZPzZ_D, + UZP1_PPP_B, + UZP1_PPP_D, + UZP1_PPP_H, + UZP1_PPP_S, + UZP1_ZZZ_B, + UZP1_ZZZ_D, + UZP1_ZZZ_H, + UZP1_ZZZ_Q, + UZP1_ZZZ_S, + UZP1v16i8, + UZP1v2i32, + UZP1v2i64, + UZP1v4i16, + UZP1v4i32, + UZP1v8i16, + UZP1v8i8, + UZP2_PPP_B, + UZP2_PPP_D, + UZP2_PPP_H, + UZP2_PPP_S, + UZP2_ZZZ_B, + UZP2_ZZZ_D, + UZP2_ZZZ_H, + UZP2_ZZZ_Q, + UZP2_ZZZ_S, + UZP2v16i8, + UZP2v2i32, + UZP2v2i64, + UZP2v4i16, + UZP2v4i32, + UZP2v8i16, + UZP2v8i8, + UZPQ1_ZZZ_B, + UZPQ1_ZZZ_D, + UZPQ1_ZZZ_H, + UZPQ1_ZZZ_S, + UZPQ2_ZZZ_B, + UZPQ2_ZZZ_D, + UZPQ2_ZZZ_H, + UZPQ2_ZZZ_S, + UZP_VG2_2ZZZ_B, + UZP_VG2_2ZZZ_D, + UZP_VG2_2ZZZ_H, + UZP_VG2_2ZZZ_Q, + UZP_VG2_2ZZZ_S, + UZP_VG4_4Z4Z_B, + UZP_VG4_4Z4Z_D, + UZP_VG4_4Z4Z_H, + UZP_VG4_4Z4Z_Q, + UZP_VG4_4Z4Z_S, + WFET, + WFIT, + WHILEGE_2PXX_B, + WHILEGE_2PXX_D, + WHILEGE_2PXX_H, + WHILEGE_2PXX_S, + WHILEGE_CXX_B, + WHILEGE_CXX_D, + WHILEGE_CXX_H, + WHILEGE_CXX_S, + WHILEGE_PWW_B, + WHILEGE_PWW_D, + WHILEGE_PWW_H, + WHILEGE_PWW_S, + WHILEGE_PXX_B, + WHILEGE_PXX_D, + WHILEGE_PXX_H, + WHILEGE_PXX_S, + WHILEGT_2PXX_B, + WHILEGT_2PXX_D, + WHILEGT_2PXX_H, + WHILEGT_2PXX_S, + WHILEGT_CXX_B, + WHILEGT_CXX_D, + WHILEGT_CXX_H, + WHILEGT_CXX_S, + WHILEGT_PWW_B, + WHILEGT_PWW_D, + WHILEGT_PWW_H, + WHILEGT_PWW_S, + WHILEGT_PXX_B, + WHILEGT_PXX_D, + WHILEGT_PXX_H, + WHILEGT_PXX_S, + WHILEHI_2PXX_B, + WHILEHI_2PXX_D, + WHILEHI_2PXX_H, + WHILEHI_2PXX_S, + WHILEHI_CXX_B, + WHILEHI_CXX_D, + WHILEHI_CXX_H, + WHILEHI_CXX_S, + WHILEHI_PWW_B, + WHILEHI_PWW_D, + WHILEHI_PWW_H, + WHILEHI_PWW_S, + WHILEHI_PXX_B, + WHILEHI_PXX_D, + WHILEHI_PXX_H, + WHILEHI_PXX_S, + WHILEHS_2PXX_B, + WHILEHS_2PXX_D, + WHILEHS_2PXX_H, + WHILEHS_2PXX_S, + WHILEHS_CXX_B, + WHILEHS_CXX_D, + WHILEHS_CXX_H, + WHILEHS_CXX_S, + WHILEHS_PWW_B, + WHILEHS_PWW_D, + WHILEHS_PWW_H, + WHILEHS_PWW_S, + WHILEHS_PXX_B, + WHILEHS_PXX_D, + WHILEHS_PXX_H, + WHILEHS_PXX_S, + WHILELE_2PXX_B, + WHILELE_2PXX_D, + WHILELE_2PXX_H, + WHILELE_2PXX_S, + WHILELE_CXX_B, + WHILELE_CXX_D, + WHILELE_CXX_H, + WHILELE_CXX_S, + WHILELE_PWW_B, + WHILELE_PWW_D, + WHILELE_PWW_H, + WHILELE_PWW_S, + WHILELE_PXX_B, + WHILELE_PXX_D, + WHILELE_PXX_H, + WHILELE_PXX_S, + WHILELO_2PXX_B, + WHILELO_2PXX_D, + WHILELO_2PXX_H, + WHILELO_2PXX_S, + WHILELO_CXX_B, + WHILELO_CXX_D, + WHILELO_CXX_H, + WHILELO_CXX_S, + WHILELO_PWW_B, + WHILELO_PWW_D, + WHILELO_PWW_H, + WHILELO_PWW_S, + WHILELO_PXX_B, + WHILELO_PXX_D, + WHILELO_PXX_H, + WHILELO_PXX_S, + WHILELS_2PXX_B, + WHILELS_2PXX_D, + WHILELS_2PXX_H, + WHILELS_2PXX_S, + WHILELS_CXX_B, + WHILELS_CXX_D, + WHILELS_CXX_H, + WHILELS_CXX_S, + WHILELS_PWW_B, + WHILELS_PWW_D, + WHILELS_PWW_H, + WHILELS_PWW_S, + WHILELS_PXX_B, + WHILELS_PXX_D, + WHILELS_PXX_H, + WHILELS_PXX_S, + WHILELT_2PXX_B, + WHILELT_2PXX_D, + WHILELT_2PXX_H, + WHILELT_2PXX_S, + WHILELT_CXX_B, + WHILELT_CXX_D, + WHILELT_CXX_H, + WHILELT_CXX_S, + WHILELT_PWW_B, + WHILELT_PWW_D, + WHILELT_PWW_H, + WHILELT_PWW_S, + WHILELT_PXX_B, + WHILELT_PXX_D, + WHILELT_PXX_H, + WHILELT_PXX_S, + WHILERW_PXX_B, + WHILERW_PXX_D, + WHILERW_PXX_H, + WHILERW_PXX_S, + WHILEWR_PXX_B, + WHILEWR_PXX_D, + WHILEWR_PXX_H, + WHILEWR_PXX_S, + WRFFR, + XAFLAG, + XAR, + XAR_ZZZI_B, + XAR_ZZZI_D, + XAR_ZZZI_H, + XAR_ZZZI_S, + XPACD, + XPACI, + XPACLRI, + XTNv16i8, + XTNv2i32, + XTNv4i16, + XTNv4i32, + XTNv8i16, + XTNv8i8, + ZERO_M, + ZERO_MXI_2Z, + ZERO_MXI_4Z, + ZERO_MXI_VG2_2Z, + ZERO_MXI_VG2_4Z, + ZERO_MXI_VG2_Z, + ZERO_MXI_VG4_2Z, + ZERO_MXI_VG4_4Z, + ZERO_MXI_VG4_Z, + ZERO_T, + ZIP1_PPP_B, + ZIP1_PPP_D, + ZIP1_PPP_H, + ZIP1_PPP_S, + ZIP1_ZZZ_B, + ZIP1_ZZZ_D, + ZIP1_ZZZ_H, + ZIP1_ZZZ_Q, + ZIP1_ZZZ_S, + ZIP1v16i8, + ZIP1v2i32, + ZIP1v2i64, + ZIP1v4i16, + ZIP1v4i32, + ZIP1v8i16, + ZIP1v8i8, + ZIP2_PPP_B, + ZIP2_PPP_D, + ZIP2_PPP_H, + ZIP2_PPP_S, + ZIP2_ZZZ_B, + ZIP2_ZZZ_D, + ZIP2_ZZZ_H, + ZIP2_ZZZ_Q, + ZIP2_ZZZ_S, + ZIP2v16i8, + ZIP2v2i32, + ZIP2v2i64, + ZIP2v4i16, + ZIP2v4i32, + ZIP2v8i16, + ZIP2v8i8, + ZIPQ1_ZZZ_B, + ZIPQ1_ZZZ_D, + ZIPQ1_ZZZ_H, + ZIPQ1_ZZZ_S, + ZIPQ2_ZZZ_B, + ZIPQ2_ZZZ_D, + ZIPQ2_ZZZ_H, + ZIPQ2_ZZZ_S, + ZIP_VG2_2ZZZ_B, + ZIP_VG2_2ZZZ_D, + ZIP_VG2_2ZZZ_H, + ZIP_VG2_2ZZZ_Q, + ZIP_VG2_2ZZZ_S, + ZIP_VG4_4Z4Z_B, + ZIP_VG4_4Z4Z_D, + ZIP_VG4_4Z4Z_H, + ZIP_VG4_4Z4Z_Q, + ZIP_VG4_4Z4Z_S, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ABS_ZPmZ_B_UNDEF, + 323 => Opcode::ABS_ZPmZ_D_UNDEF, + 324 => Opcode::ABS_ZPmZ_H_UNDEF, + 325 => Opcode::ABS_ZPmZ_S_UNDEF, + 326 => Opcode::ADDHA_MPPZ_D_PSEUDO_D, + 327 => Opcode::ADDHA_MPPZ_S_PSEUDO_S, + 328 => Opcode::ADDSWrr, + 329 => Opcode::ADDSXrr, + 330 => Opcode::ADDVA_MPPZ_D_PSEUDO_D, + 331 => Opcode::ADDVA_MPPZ_S_PSEUDO_S, + 332 => Opcode::ADDWrr, + 333 => Opcode::ADDXrr, + 334 => Opcode::ADD_VG2_M2Z2Z_D_PSEUDO, + 335 => Opcode::ADD_VG2_M2Z2Z_S_PSEUDO, + 336 => Opcode::ADD_VG2_M2ZZ_D_PSEUDO, + 337 => Opcode::ADD_VG2_M2ZZ_S_PSEUDO, + 338 => Opcode::ADD_VG2_M2Z_D_PSEUDO, + 339 => Opcode::ADD_VG2_M2Z_S_PSEUDO, + 340 => Opcode::ADD_VG4_M4Z4Z_D_PSEUDO, + 341 => Opcode::ADD_VG4_M4Z4Z_S_PSEUDO, + 342 => Opcode::ADD_VG4_M4ZZ_D_PSEUDO, + 343 => Opcode::ADD_VG4_M4ZZ_S_PSEUDO, + 344 => Opcode::ADD_VG4_M4Z_D_PSEUDO, + 345 => Opcode::ADD_VG4_M4Z_S_PSEUDO, + 346 => Opcode::ADD_ZPZZ_B_ZERO, + 347 => Opcode::ADD_ZPZZ_D_ZERO, + 348 => Opcode::ADD_ZPZZ_H_ZERO, + 349 => Opcode::ADD_ZPZZ_S_ZERO, + 350 => Opcode::ADDlowTLS, + 351 => Opcode::ADJCALLSTACKDOWN, + 352 => Opcode::ADJCALLSTACKUP, + 353 => Opcode::AESIMCrrTied, + 354 => Opcode::AESMCrrTied, + 355 => Opcode::ANDSWrr, + 356 => Opcode::ANDSXrr, + 357 => Opcode::ANDWrr, + 358 => Opcode::ANDXrr, + 359 => Opcode::AND_ZPZZ_B_ZERO, + 360 => Opcode::AND_ZPZZ_D_ZERO, + 361 => Opcode::AND_ZPZZ_H_ZERO, + 362 => Opcode::AND_ZPZZ_S_ZERO, + 363 => Opcode::ASRD_ZPZI_B_ZERO, + 364 => Opcode::ASRD_ZPZI_D_ZERO, + 365 => Opcode::ASRD_ZPZI_H_ZERO, + 366 => Opcode::ASRD_ZPZI_S_ZERO, + 367 => Opcode::ASR_ZPZI_B_UNDEF, + 368 => Opcode::ASR_ZPZI_B_ZERO, + 369 => Opcode::ASR_ZPZI_D_UNDEF, + 370 => Opcode::ASR_ZPZI_D_ZERO, + 371 => Opcode::ASR_ZPZI_H_UNDEF, + 372 => Opcode::ASR_ZPZI_H_ZERO, + 373 => Opcode::ASR_ZPZI_S_UNDEF, + 374 => Opcode::ASR_ZPZI_S_ZERO, + 375 => Opcode::ASR_ZPZZ_B_UNDEF, + 376 => Opcode::ASR_ZPZZ_B_ZERO, + 377 => Opcode::ASR_ZPZZ_D_UNDEF, + 378 => Opcode::ASR_ZPZZ_D_ZERO, + 379 => Opcode::ASR_ZPZZ_H_UNDEF, + 380 => Opcode::ASR_ZPZZ_H_ZERO, + 381 => Opcode::ASR_ZPZZ_S_UNDEF, + 382 => Opcode::ASR_ZPZZ_S_ZERO, + 383 => Opcode::AUTH_TCRETURN, + 384 => Opcode::AUTH_TCRETURN_BTI, + 385 => Opcode::AUTPAC, + 386 => Opcode::AUTx16x17, + 387 => Opcode::AUTxMxN, + 388 => Opcode::AllocateSMESaveBuffer, + 389 => Opcode::AllocateZABuffer, + 390 => Opcode::BFADD_VG2_M2Z_H_PSEUDO, + 391 => Opcode::BFADD_VG4_M4Z_H_PSEUDO, + 392 => Opcode::BFADD_ZPZZ_UNDEF, + 393 => Opcode::BFADD_ZPZZ_ZERO, + 394 => Opcode::BFDOT_VG2_M2Z2Z_HtoS_PSEUDO, + 395 => Opcode::BFDOT_VG2_M2ZZI_HtoS_PSEUDO, + 396 => Opcode::BFDOT_VG2_M2ZZ_HtoS_PSEUDO, + 397 => Opcode::BFDOT_VG4_M4Z4Z_HtoS_PSEUDO, + 398 => Opcode::BFDOT_VG4_M4ZZI_HtoS_PSEUDO, + 399 => Opcode::BFDOT_VG4_M4ZZ_HtoS_PSEUDO, + 400 => Opcode::BFMAXNM_ZPZZ_UNDEF, + 401 => Opcode::BFMAXNM_ZPZZ_ZERO, + 402 => Opcode::BFMAX_ZPZZ_UNDEF, + 403 => Opcode::BFMAX_ZPZZ_ZERO, + 404 => Opcode::BFMINNM_ZPZZ_UNDEF, + 405 => Opcode::BFMINNM_ZPZZ_ZERO, + 406 => Opcode::BFMIN_ZPZZ_UNDEF, + 407 => Opcode::BFMIN_ZPZZ_ZERO, + 408 => Opcode::BFMLAL_MZZI_HtoS_PSEUDO, + 409 => Opcode::BFMLAL_MZZ_HtoS_PSEUDO, + 410 => Opcode::BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + 411 => Opcode::BFMLAL_VG2_M2ZZI_HtoS_PSEUDO, + 412 => Opcode::BFMLAL_VG2_M2ZZ_HtoS_PSEUDO, + 413 => Opcode::BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + 414 => Opcode::BFMLAL_VG4_M4ZZI_HtoS_PSEUDO, + 415 => Opcode::BFMLAL_VG4_M4ZZ_HtoS_PSEUDO, + 416 => Opcode::BFMLA_VG2_M2Z2Z_PSEUDO, + 417 => Opcode::BFMLA_VG2_M2ZZI_PSEUDO, + 418 => Opcode::BFMLA_VG2_M2ZZ_PSEUDO, + 419 => Opcode::BFMLA_VG4_M4Z4Z_PSEUDO, + 420 => Opcode::BFMLA_VG4_M4ZZI_PSEUDO, + 421 => Opcode::BFMLA_VG4_M4ZZ_PSEUDO, + 422 => Opcode::BFMLA_ZPZZZ_UNDEF, + 423 => Opcode::BFMLSL_MZZI_HtoS_PSEUDO, + 424 => Opcode::BFMLSL_MZZ_HtoS_PSEUDO, + 425 => Opcode::BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + 426 => Opcode::BFMLSL_VG2_M2ZZI_HtoS_PSEUDO, + 427 => Opcode::BFMLSL_VG2_M2ZZ_HtoS_PSEUDO, + 428 => Opcode::BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + 429 => Opcode::BFMLSL_VG4_M4ZZI_HtoS_PSEUDO, + 430 => Opcode::BFMLSL_VG4_M4ZZ_HtoS_PSEUDO, + 431 => Opcode::BFMLS_VG2_M2Z2Z_PSEUDO, + 432 => Opcode::BFMLS_VG2_M2ZZI_PSEUDO, + 433 => Opcode::BFMLS_VG2_M2ZZ_PSEUDO, + 434 => Opcode::BFMLS_VG4_M4Z4Z_PSEUDO, + 435 => Opcode::BFMLS_VG4_M4ZZI_PSEUDO, + 436 => Opcode::BFMLS_VG4_M4ZZ_PSEUDO, + 437 => Opcode::BFMLS_ZPZZZ_UNDEF, + 438 => Opcode::BFMOP4A_M2Z2Z_H_PSEUDO, + 439 => Opcode::BFMOP4A_M2Z2Z_S_PSEUDO, + 440 => Opcode::BFMOP4A_M2ZZ_H_PSEUDO, + 441 => Opcode::BFMOP4A_M2ZZ_S_PSEUDO, + 442 => Opcode::BFMOP4A_MZ2Z_H_PSEUDO, + 443 => Opcode::BFMOP4A_MZ2Z_S_PSEUDO, + 444 => Opcode::BFMOP4A_MZZ_H_PSEUDO, + 445 => Opcode::BFMOP4A_MZZ_S_PSEUDO, + 446 => Opcode::BFMOP4S_M2Z2Z_H_PSEUDO, + 447 => Opcode::BFMOP4S_M2Z2Z_S_PSEUDO, + 448 => Opcode::BFMOP4S_M2ZZ_H_PSEUDO, + 449 => Opcode::BFMOP4S_M2ZZ_S_PSEUDO, + 450 => Opcode::BFMOP4S_MZ2Z_H_PSEUDO, + 451 => Opcode::BFMOP4S_MZ2Z_S_PSEUDO, + 452 => Opcode::BFMOP4S_MZZ_H_PSEUDO, + 453 => Opcode::BFMOP4S_MZZ_S_PSEUDO, + 454 => Opcode::BFMOPA_MPPZZ_H_PSEUDO, + 455 => Opcode::BFMOPA_MPPZZ_PSEUDO, + 456 => Opcode::BFMOPS_MPPZZ_H_PSEUDO, + 457 => Opcode::BFMOPS_MPPZZ_PSEUDO, + 458 => Opcode::BFMUL_ZPZZ_UNDEF, + 459 => Opcode::BFMUL_ZPZZ_ZERO, + 460 => Opcode::BFSUB_VG2_M2Z_H_PSEUDO, + 461 => Opcode::BFSUB_VG4_M4Z_H_PSEUDO, + 462 => Opcode::BFSUB_ZPZZ_UNDEF, + 463 => Opcode::BFSUB_ZPZZ_ZERO, + 464 => Opcode::BFTMOPA_M2ZZZI_HtoH_PSEUDO, + 465 => Opcode::BFTMOPA_M2ZZZI_HtoS_PSEUDO, + 466 => Opcode::BFVDOT_VG2_M2ZZI_HtoS_PSEUDO, + 467 => Opcode::BICSWrr, + 468 => Opcode::BICSXrr, + 469 => Opcode::BICWrr, + 470 => Opcode::BICXrr, + 471 => Opcode::BIC_ZPZZ_B_ZERO, + 472 => Opcode::BIC_ZPZZ_D_ZERO, + 473 => Opcode::BIC_ZPZZ_H_ZERO, + 474 => Opcode::BIC_ZPZZ_S_ZERO, + 475 => Opcode::BLRA, + 476 => Opcode::BLRA_RVMARKER, + 477 => Opcode::BLRNoIP, + 478 => Opcode::BLR_BTI, + 479 => Opcode::BLR_RVMARKER, + 480 => Opcode::BLR_X16, + 481 => Opcode::BMOPA_MPPZZ_S_PSEUDO, + 482 => Opcode::BMOPS_MPPZZ_S_PSEUDO, + 483 => Opcode::BRA, + 484 => Opcode::BR_JumpTable, + 485 => Opcode::BSPv16i8, + 486 => Opcode::BSPv8i8, + 487 => Opcode::CATCHRET, + 488 => Opcode::CBBAssertExt, + 489 => Opcode::CBHAssertExt, + 490 => Opcode::CBWPri, + 491 => Opcode::CBWPrr, + 492 => Opcode::CBXPri, + 493 => Opcode::CBXPrr, + 494 => Opcode::CHECK_MATCHING_VL_PSEUDO, + 495 => Opcode::CLEANUPRET, + 496 => Opcode::CLS_ZPmZ_B_UNDEF, + 497 => Opcode::CLS_ZPmZ_D_UNDEF, + 498 => Opcode::CLS_ZPmZ_H_UNDEF, + 499 => Opcode::CLS_ZPmZ_S_UNDEF, + 500 => Opcode::CLZ_ZPmZ_B_UNDEF, + 501 => Opcode::CLZ_ZPmZ_D_UNDEF, + 502 => Opcode::CLZ_ZPmZ_H_UNDEF, + 503 => Opcode::CLZ_ZPmZ_S_UNDEF, + 504 => Opcode::CMP_SWAP_128, + 505 => Opcode::CMP_SWAP_128_ACQUIRE, + 506 => Opcode::CMP_SWAP_128_MONOTONIC, + 507 => Opcode::CMP_SWAP_128_RELEASE, + 508 => Opcode::CMP_SWAP_16, + 509 => Opcode::CMP_SWAP_32, + 510 => Opcode::CMP_SWAP_64, + 511 => Opcode::CMP_SWAP_8, + 512 => Opcode::CNOT_ZPmZ_B_UNDEF, + 513 => Opcode::CNOT_ZPmZ_D_UNDEF, + 514 => Opcode::CNOT_ZPmZ_H_UNDEF, + 515 => Opcode::CNOT_ZPmZ_S_UNDEF, + 516 => Opcode::CNT_ZPmZ_B_UNDEF, + 517 => Opcode::CNT_ZPmZ_D_UNDEF, + 518 => Opcode::CNT_ZPmZ_H_UNDEF, + 519 => Opcode::CNT_ZPmZ_S_UNDEF, + 520 => Opcode::COALESCER_BARRIER_FPR128, + 521 => Opcode::COALESCER_BARRIER_FPR16, + 522 => Opcode::COALESCER_BARRIER_FPR32, + 523 => Opcode::COALESCER_BARRIER_FPR64, + 524 => Opcode::CommitZASavePseudo, + 525 => Opcode::EMITBKEY, + 526 => Opcode::EMITMTETAGGED, + 527 => Opcode::EONWrr, + 528 => Opcode::EONXrr, + 529 => Opcode::EORWrr, + 530 => Opcode::EORXrr, + 531 => Opcode::EOR_ZPZZ_B_ZERO, + 532 => Opcode::EOR_ZPZZ_D_ZERO, + 533 => Opcode::EOR_ZPZZ_H_ZERO, + 534 => Opcode::EOR_ZPZZ_S_ZERO, + 535 => Opcode::EXT_ZZI_CONSTRUCTIVE, + 536 => Opcode::EntryPStateSM, + 537 => Opcode::F128CSEL, + 538 => Opcode::FABD_ZPZZ_D_UNDEF, + 539 => Opcode::FABD_ZPZZ_D_ZERO, + 540 => Opcode::FABD_ZPZZ_H_UNDEF, + 541 => Opcode::FABD_ZPZZ_H_ZERO, + 542 => Opcode::FABD_ZPZZ_S_UNDEF, + 543 => Opcode::FABD_ZPZZ_S_ZERO, + 544 => Opcode::FABS_ZPmZ_D_UNDEF, + 545 => Opcode::FABS_ZPmZ_H_UNDEF, + 546 => Opcode::FABS_ZPmZ_S_UNDEF, + 547 => Opcode::FADD_VG2_M2Z_D_PSEUDO, + 548 => Opcode::FADD_VG2_M2Z_H_PSEUDO, + 549 => Opcode::FADD_VG2_M2Z_S_PSEUDO, + 550 => Opcode::FADD_VG4_M4Z_D_PSEUDO, + 551 => Opcode::FADD_VG4_M4Z_H_PSEUDO, + 552 => Opcode::FADD_VG4_M4Z_S_PSEUDO, + 553 => Opcode::FADD_ZPZI_D_UNDEF, + 554 => Opcode::FADD_ZPZI_D_ZERO, + 555 => Opcode::FADD_ZPZI_H_UNDEF, + 556 => Opcode::FADD_ZPZI_H_ZERO, + 557 => Opcode::FADD_ZPZI_S_UNDEF, + 558 => Opcode::FADD_ZPZI_S_ZERO, + 559 => Opcode::FADD_ZPZZ_D_UNDEF, + 560 => Opcode::FADD_ZPZZ_D_ZERO, + 561 => Opcode::FADD_ZPZZ_H_UNDEF, + 562 => Opcode::FADD_ZPZZ_H_ZERO, + 563 => Opcode::FADD_ZPZZ_S_UNDEF, + 564 => Opcode::FADD_ZPZZ_S_ZERO, + 565 => Opcode::FAMAX_ZPZZ_D_UNDEF, + 566 => Opcode::FAMAX_ZPZZ_H_UNDEF, + 567 => Opcode::FAMAX_ZPZZ_S_UNDEF, + 568 => Opcode::FAMIN_ZPZZ_D_UNDEF, + 569 => Opcode::FAMIN_ZPZZ_H_UNDEF, + 570 => Opcode::FAMIN_ZPZZ_S_UNDEF, + 571 => Opcode::FCVTZS_ZPmZ_DtoD_UNDEF, + 572 => Opcode::FCVTZS_ZPmZ_DtoS_UNDEF, + 573 => Opcode::FCVTZS_ZPmZ_HtoD_UNDEF, + 574 => Opcode::FCVTZS_ZPmZ_HtoH_UNDEF, + 575 => Opcode::FCVTZS_ZPmZ_HtoS_UNDEF, + 576 => Opcode::FCVTZS_ZPmZ_StoD_UNDEF, + 577 => Opcode::FCVTZS_ZPmZ_StoS_UNDEF, + 578 => Opcode::FCVTZU_ZPmZ_DtoD_UNDEF, + 579 => Opcode::FCVTZU_ZPmZ_DtoS_UNDEF, + 580 => Opcode::FCVTZU_ZPmZ_HtoD_UNDEF, + 581 => Opcode::FCVTZU_ZPmZ_HtoH_UNDEF, + 582 => Opcode::FCVTZU_ZPmZ_HtoS_UNDEF, + 583 => Opcode::FCVTZU_ZPmZ_StoD_UNDEF, + 584 => Opcode::FCVTZU_ZPmZ_StoS_UNDEF, + 585 => Opcode::FCVT_ZPmZ_DtoH_UNDEF, + 586 => Opcode::FCVT_ZPmZ_DtoS_UNDEF, + 587 => Opcode::FCVT_ZPmZ_HtoD_UNDEF, + 588 => Opcode::FCVT_ZPmZ_HtoS_UNDEF, + 589 => Opcode::FCVT_ZPmZ_StoD_UNDEF, + 590 => Opcode::FCVT_ZPmZ_StoH_UNDEF, + 591 => Opcode::FDIVR_ZPZZ_D_ZERO, + 592 => Opcode::FDIVR_ZPZZ_H_ZERO, + 593 => Opcode::FDIVR_ZPZZ_S_ZERO, + 594 => Opcode::FDIV_ZPZZ_D_UNDEF, + 595 => Opcode::FDIV_ZPZZ_D_ZERO, + 596 => Opcode::FDIV_ZPZZ_H_UNDEF, + 597 => Opcode::FDIV_ZPZZ_H_ZERO, + 598 => Opcode::FDIV_ZPZZ_S_UNDEF, + 599 => Opcode::FDIV_ZPZZ_S_ZERO, + 600 => Opcode::FDOT_VG2_M2Z2Z_BtoH_PSEUDO, + 601 => Opcode::FDOT_VG2_M2Z2Z_BtoS_PSEUDO, + 602 => Opcode::FDOT_VG2_M2Z2Z_HtoS_PSEUDO, + 603 => Opcode::FDOT_VG2_M2ZZI_BtoH_PSEUDO, + 604 => Opcode::FDOT_VG2_M2ZZI_BtoS_PSEUDO, + 605 => Opcode::FDOT_VG2_M2ZZI_HtoS_PSEUDO, + 606 => Opcode::FDOT_VG2_M2ZZ_BtoH_PSEUDO, + 607 => Opcode::FDOT_VG2_M2ZZ_BtoS_PSEUDO, + 608 => Opcode::FDOT_VG2_M2ZZ_HtoS_PSEUDO, + 609 => Opcode::FDOT_VG4_M4Z4Z_BtoH_PSEUDO, + 610 => Opcode::FDOT_VG4_M4Z4Z_BtoS_PSEUDO, + 611 => Opcode::FDOT_VG4_M4Z4Z_HtoS_PSEUDO, + 612 => Opcode::FDOT_VG4_M4ZZI_BtoH_PSEUDO, + 613 => Opcode::FDOT_VG4_M4ZZI_BtoS_PSEUDO, + 614 => Opcode::FDOT_VG4_M4ZZI_HtoS_PSEUDO, + 615 => Opcode::FDOT_VG4_M4ZZ_BtoH_PSEUDO, + 616 => Opcode::FDOT_VG4_M4ZZ_BtoS_PSEUDO, + 617 => Opcode::FDOT_VG4_M4ZZ_HtoS_PSEUDO, + 618 => Opcode::FLOGB_ZPZZ_D_ZERO, + 619 => Opcode::FLOGB_ZPZZ_H_ZERO, + 620 => Opcode::FLOGB_ZPZZ_S_ZERO, + 621 => Opcode::FMAXNM_ZPZI_D_UNDEF, + 622 => Opcode::FMAXNM_ZPZI_D_ZERO, + 623 => Opcode::FMAXNM_ZPZI_H_UNDEF, + 624 => Opcode::FMAXNM_ZPZI_H_ZERO, + 625 => Opcode::FMAXNM_ZPZI_S_UNDEF, + 626 => Opcode::FMAXNM_ZPZI_S_ZERO, + 627 => Opcode::FMAXNM_ZPZZ_D_UNDEF, + 628 => Opcode::FMAXNM_ZPZZ_D_ZERO, + 629 => Opcode::FMAXNM_ZPZZ_H_UNDEF, + 630 => Opcode::FMAXNM_ZPZZ_H_ZERO, + 631 => Opcode::FMAXNM_ZPZZ_S_UNDEF, + 632 => Opcode::FMAXNM_ZPZZ_S_ZERO, + 633 => Opcode::FMAX_ZPZI_D_UNDEF, + 634 => Opcode::FMAX_ZPZI_D_ZERO, + 635 => Opcode::FMAX_ZPZI_H_UNDEF, + 636 => Opcode::FMAX_ZPZI_H_ZERO, + 637 => Opcode::FMAX_ZPZI_S_UNDEF, + 638 => Opcode::FMAX_ZPZI_S_ZERO, + 639 => Opcode::FMAX_ZPZZ_D_UNDEF, + 640 => Opcode::FMAX_ZPZZ_D_ZERO, + 641 => Opcode::FMAX_ZPZZ_H_UNDEF, + 642 => Opcode::FMAX_ZPZZ_H_ZERO, + 643 => Opcode::FMAX_ZPZZ_S_UNDEF, + 644 => Opcode::FMAX_ZPZZ_S_ZERO, + 645 => Opcode::FMINNM_ZPZI_D_UNDEF, + 646 => Opcode::FMINNM_ZPZI_D_ZERO, + 647 => Opcode::FMINNM_ZPZI_H_UNDEF, + 648 => Opcode::FMINNM_ZPZI_H_ZERO, + 649 => Opcode::FMINNM_ZPZI_S_UNDEF, + 650 => Opcode::FMINNM_ZPZI_S_ZERO, + 651 => Opcode::FMINNM_ZPZZ_D_UNDEF, + 652 => Opcode::FMINNM_ZPZZ_D_ZERO, + 653 => Opcode::FMINNM_ZPZZ_H_UNDEF, + 654 => Opcode::FMINNM_ZPZZ_H_ZERO, + 655 => Opcode::FMINNM_ZPZZ_S_UNDEF, + 656 => Opcode::FMINNM_ZPZZ_S_ZERO, + 657 => Opcode::FMIN_ZPZI_D_UNDEF, + 658 => Opcode::FMIN_ZPZI_D_ZERO, + 659 => Opcode::FMIN_ZPZI_H_UNDEF, + 660 => Opcode::FMIN_ZPZI_H_ZERO, + 661 => Opcode::FMIN_ZPZI_S_UNDEF, + 662 => Opcode::FMIN_ZPZI_S_ZERO, + 663 => Opcode::FMIN_ZPZZ_D_UNDEF, + 664 => Opcode::FMIN_ZPZZ_D_ZERO, + 665 => Opcode::FMIN_ZPZZ_H_UNDEF, + 666 => Opcode::FMIN_ZPZZ_H_ZERO, + 667 => Opcode::FMIN_ZPZZ_S_UNDEF, + 668 => Opcode::FMIN_ZPZZ_S_ZERO, + 669 => Opcode::FMLALL_MZZI_BtoS_PSEUDO, + 670 => Opcode::FMLALL_MZZ_BtoS_PSEUDO, + 671 => Opcode::FMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + 672 => Opcode::FMLALL_VG2_M2ZZI_BtoS_PSEUDO, + 673 => Opcode::FMLALL_VG2_M2ZZ_BtoS_PSEUDO, + 674 => Opcode::FMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + 675 => Opcode::FMLALL_VG4_M4ZZI_BtoS_PSEUDO, + 676 => Opcode::FMLALL_VG4_M4ZZ_BtoS_PSEUDO, + 677 => Opcode::FMLAL_MZZI_BtoH_PSEUDO, + 678 => Opcode::FMLAL_MZZI_HtoS_PSEUDO, + 679 => Opcode::FMLAL_MZZ_HtoS_PSEUDO, + 680 => Opcode::FMLAL_VG2_M2Z2Z_BtoH_PSEUDO, + 681 => Opcode::FMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + 682 => Opcode::FMLAL_VG2_M2ZZI_BtoH_PSEUDO, + 683 => Opcode::FMLAL_VG2_M2ZZI_HtoS_PSEUDO, + 684 => Opcode::FMLAL_VG2_M2ZZ_BtoH_PSEUDO, + 685 => Opcode::FMLAL_VG2_M2ZZ_HtoS_PSEUDO, + 686 => Opcode::FMLAL_VG2_MZZ_BtoH_PSEUDO, + 687 => Opcode::FMLAL_VG4_M4Z4Z_BtoH_PSEUDO, + 688 => Opcode::FMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + 689 => Opcode::FMLAL_VG4_M4ZZI_BtoH_PSEUDO, + 690 => Opcode::FMLAL_VG4_M4ZZI_HtoS_PSEUDO, + 691 => Opcode::FMLAL_VG4_M4ZZ_BtoH_PSEUDO, + 692 => Opcode::FMLAL_VG4_M4ZZ_HtoS_PSEUDO, + 693 => Opcode::FMLA_VG2_M2Z2Z_D_PSEUDO, + 694 => Opcode::FMLA_VG2_M2Z2Z_H_PSEUDO, + 695 => Opcode::FMLA_VG2_M2Z2Z_S_PSEUDO, + 696 => Opcode::FMLA_VG2_M2ZZI_D_PSEUDO, + 697 => Opcode::FMLA_VG2_M2ZZI_H_PSEUDO, + 698 => Opcode::FMLA_VG2_M2ZZI_S_PSEUDO, + 699 => Opcode::FMLA_VG2_M2ZZ_D_PSEUDO, + 700 => Opcode::FMLA_VG2_M2ZZ_H_PSEUDO, + 701 => Opcode::FMLA_VG2_M2ZZ_S_PSEUDO, + 702 => Opcode::FMLA_VG4_M4Z4Z_D_PSEUDO, + 703 => Opcode::FMLA_VG4_M4Z4Z_H_PSEUDO, + 704 => Opcode::FMLA_VG4_M4Z4Z_S_PSEUDO, + 705 => Opcode::FMLA_VG4_M4ZZI_D_PSEUDO, + 706 => Opcode::FMLA_VG4_M4ZZI_H_PSEUDO, + 707 => Opcode::FMLA_VG4_M4ZZI_S_PSEUDO, + 708 => Opcode::FMLA_VG4_M4ZZ_D_PSEUDO, + 709 => Opcode::FMLA_VG4_M4ZZ_H_PSEUDO, + 710 => Opcode::FMLA_VG4_M4ZZ_S_PSEUDO, + 711 => Opcode::FMLA_ZPZZZ_D_UNDEF, + 712 => Opcode::FMLA_ZPZZZ_H_UNDEF, + 713 => Opcode::FMLA_ZPZZZ_S_UNDEF, + 714 => Opcode::FMLSL_MZZI_HtoS_PSEUDO, + 715 => Opcode::FMLSL_MZZ_HtoS_PSEUDO, + 716 => Opcode::FMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + 717 => Opcode::FMLSL_VG2_M2ZZI_HtoS_PSEUDO, + 718 => Opcode::FMLSL_VG2_M2ZZ_HtoS_PSEUDO, + 719 => Opcode::FMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + 720 => Opcode::FMLSL_VG4_M4ZZI_HtoS_PSEUDO, + 721 => Opcode::FMLSL_VG4_M4ZZ_HtoS_PSEUDO, + 722 => Opcode::FMLS_VG2_M2Z2Z_D_PSEUDO, + 723 => Opcode::FMLS_VG2_M2Z2Z_H_PSEUDO, + 724 => Opcode::FMLS_VG2_M2Z2Z_S_PSEUDO, + 725 => Opcode::FMLS_VG2_M2ZZI_D_PSEUDO, + 726 => Opcode::FMLS_VG2_M2ZZI_H_PSEUDO, + 727 => Opcode::FMLS_VG2_M2ZZI_S_PSEUDO, + 728 => Opcode::FMLS_VG2_M2ZZ_D_PSEUDO, + 729 => Opcode::FMLS_VG2_M2ZZ_H_PSEUDO, + 730 => Opcode::FMLS_VG2_M2ZZ_S_PSEUDO, + 731 => Opcode::FMLS_VG4_M4Z4Z_D_PSEUDO, + 732 => Opcode::FMLS_VG4_M4Z4Z_H_PSEUDO, + 733 => Opcode::FMLS_VG4_M4Z4Z_S_PSEUDO, + 734 => Opcode::FMLS_VG4_M4ZZI_D_PSEUDO, + 735 => Opcode::FMLS_VG4_M4ZZI_H_PSEUDO, + 736 => Opcode::FMLS_VG4_M4ZZI_S_PSEUDO, + 737 => Opcode::FMLS_VG4_M4ZZ_D_PSEUDO, + 738 => Opcode::FMLS_VG4_M4ZZ_H_PSEUDO, + 739 => Opcode::FMLS_VG4_M4ZZ_S_PSEUDO, + 740 => Opcode::FMLS_ZPZZZ_D_UNDEF, + 741 => Opcode::FMLS_ZPZZZ_H_UNDEF, + 742 => Opcode::FMLS_ZPZZZ_S_UNDEF, + 743 => Opcode::FMOP4A_M2Z2Z_BtoH_PSEUDO, + 744 => Opcode::FMOP4A_M2Z2Z_BtoS_PSEUDO, + 745 => Opcode::FMOP4A_M2Z2Z_D_PSEUDO, + 746 => Opcode::FMOP4A_M2Z2Z_H_PSEUDO, + 747 => Opcode::FMOP4A_M2Z2Z_HtoS_PSEUDO, + 748 => Opcode::FMOP4A_M2Z2Z_S_PSEUDO, + 749 => Opcode::FMOP4A_M2ZZ_BtoH_PSEUDO, + 750 => Opcode::FMOP4A_M2ZZ_BtoS_PSEUDO, + 751 => Opcode::FMOP4A_M2ZZ_D_PSEUDO, + 752 => Opcode::FMOP4A_M2ZZ_H_PSEUDO, + 753 => Opcode::FMOP4A_M2ZZ_HtoS_PSEUDO, + 754 => Opcode::FMOP4A_M2ZZ_S_PSEUDO, + 755 => Opcode::FMOP4A_MZ2Z_BtoH_PSEUDO, + 756 => Opcode::FMOP4A_MZ2Z_BtoS_PSEUDO, + 757 => Opcode::FMOP4A_MZ2Z_D_PSEUDO, + 758 => Opcode::FMOP4A_MZ2Z_H_PSEUDO, + 759 => Opcode::FMOP4A_MZ2Z_HtoS_PSEUDO, + 760 => Opcode::FMOP4A_MZ2Z_S_PSEUDO, + 761 => Opcode::FMOP4A_MZZ_BtoH_PSEUDO, + 762 => Opcode::FMOP4A_MZZ_BtoS_PSEUDO, + 763 => Opcode::FMOP4A_MZZ_D_PSEUDO, + 764 => Opcode::FMOP4A_MZZ_H_PSEUDO, + 765 => Opcode::FMOP4A_MZZ_HtoS_PSEUDO, + 766 => Opcode::FMOP4A_MZZ_S_PSEUDO, + 767 => Opcode::FMOP4S_M2Z2Z_D_PSEUDO, + 768 => Opcode::FMOP4S_M2Z2Z_H_PSEUDO, + 769 => Opcode::FMOP4S_M2Z2Z_HtoS_PSEUDO, + 770 => Opcode::FMOP4S_M2Z2Z_S_PSEUDO, + 771 => Opcode::FMOP4S_M2ZZ_D_PSEUDO, + 772 => Opcode::FMOP4S_M2ZZ_H_PSEUDO, + 773 => Opcode::FMOP4S_M2ZZ_HtoS_PSEUDO, + 774 => Opcode::FMOP4S_M2ZZ_S_PSEUDO, + 775 => Opcode::FMOP4S_MZ2Z_D_PSEUDO, + 776 => Opcode::FMOP4S_MZ2Z_H_PSEUDO, + 777 => Opcode::FMOP4S_MZ2Z_HtoS_PSEUDO, + 778 => Opcode::FMOP4S_MZ2Z_S_PSEUDO, + 779 => Opcode::FMOP4S_MZZ_D_PSEUDO, + 780 => Opcode::FMOP4S_MZZ_H_PSEUDO, + 781 => Opcode::FMOP4S_MZZ_HtoS_PSEUDO, + 782 => Opcode::FMOP4S_MZZ_S_PSEUDO, + 783 => Opcode::FMOPAL_MPPZZ_PSEUDO, + 784 => Opcode::FMOPA_MPPZZ_BtoH_PSEUDO, + 785 => Opcode::FMOPA_MPPZZ_BtoS_PSEUDO, + 786 => Opcode::FMOPA_MPPZZ_D_PSEUDO, + 787 => Opcode::FMOPA_MPPZZ_H_PSEUDO, + 788 => Opcode::FMOPA_MPPZZ_S_PSEUDO, + 789 => Opcode::FMOPSL_MPPZZ_PSEUDO, + 790 => Opcode::FMOPS_MPPZZ_D_PSEUDO, + 791 => Opcode::FMOPS_MPPZZ_H_PSEUDO, + 792 => Opcode::FMOPS_MPPZZ_S_PSEUDO, + 793 => Opcode::FMOVD0, + 794 => Opcode::FMOVH0, + 795 => Opcode::FMOVS0, + 796 => Opcode::FMULX_ZPZZ_D_UNDEF, + 797 => Opcode::FMULX_ZPZZ_D_ZERO, + 798 => Opcode::FMULX_ZPZZ_H_UNDEF, + 799 => Opcode::FMULX_ZPZZ_H_ZERO, + 800 => Opcode::FMULX_ZPZZ_S_UNDEF, + 801 => Opcode::FMULX_ZPZZ_S_ZERO, + 802 => Opcode::FMUL_ZPZI_D_UNDEF, + 803 => Opcode::FMUL_ZPZI_D_ZERO, + 804 => Opcode::FMUL_ZPZI_H_UNDEF, + 805 => Opcode::FMUL_ZPZI_H_ZERO, + 806 => Opcode::FMUL_ZPZI_S_UNDEF, + 807 => Opcode::FMUL_ZPZI_S_ZERO, + 808 => Opcode::FMUL_ZPZZ_D_UNDEF, + 809 => Opcode::FMUL_ZPZZ_D_ZERO, + 810 => Opcode::FMUL_ZPZZ_H_UNDEF, + 811 => Opcode::FMUL_ZPZZ_H_ZERO, + 812 => Opcode::FMUL_ZPZZ_S_UNDEF, + 813 => Opcode::FMUL_ZPZZ_S_ZERO, + 814 => Opcode::FNEG_ZPmZ_D_UNDEF, + 815 => Opcode::FNEG_ZPmZ_H_UNDEF, + 816 => Opcode::FNEG_ZPmZ_S_UNDEF, + 817 => Opcode::FNMLA_ZPZZZ_D_UNDEF, + 818 => Opcode::FNMLA_ZPZZZ_H_UNDEF, + 819 => Opcode::FNMLA_ZPZZZ_S_UNDEF, + 820 => Opcode::FNMLS_ZPZZZ_D_UNDEF, + 821 => Opcode::FNMLS_ZPZZZ_H_UNDEF, + 822 => Opcode::FNMLS_ZPZZZ_S_UNDEF, + 823 => Opcode::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO, + 824 => Opcode::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO, + 825 => Opcode::FRECPX_ZPmZ_D_UNDEF, + 826 => Opcode::FRECPX_ZPmZ_H_UNDEF, + 827 => Opcode::FRECPX_ZPmZ_S_UNDEF, + 828 => Opcode::FRINT32X_ZPmZ_D_UNDEF, + 829 => Opcode::FRINT32X_ZPmZ_S_UNDEF, + 830 => Opcode::FRINT32Z_ZPmZ_D_UNDEF, + 831 => Opcode::FRINT32Z_ZPmZ_S_UNDEF, + 832 => Opcode::FRINT64X_ZPmZ_D_UNDEF, + 833 => Opcode::FRINT64X_ZPmZ_S_UNDEF, + 834 => Opcode::FRINT64Z_ZPmZ_D_UNDEF, + 835 => Opcode::FRINT64Z_ZPmZ_S_UNDEF, + 836 => Opcode::FRINTA_ZPmZ_D_UNDEF, + 837 => Opcode::FRINTA_ZPmZ_H_UNDEF, + 838 => Opcode::FRINTA_ZPmZ_S_UNDEF, + 839 => Opcode::FRINTI_ZPmZ_D_UNDEF, + 840 => Opcode::FRINTI_ZPmZ_H_UNDEF, + 841 => Opcode::FRINTI_ZPmZ_S_UNDEF, + 842 => Opcode::FRINTM_ZPmZ_D_UNDEF, + 843 => Opcode::FRINTM_ZPmZ_H_UNDEF, + 844 => Opcode::FRINTM_ZPmZ_S_UNDEF, + 845 => Opcode::FRINTN_ZPmZ_D_UNDEF, + 846 => Opcode::FRINTN_ZPmZ_H_UNDEF, + 847 => Opcode::FRINTN_ZPmZ_S_UNDEF, + 848 => Opcode::FRINTP_ZPmZ_D_UNDEF, + 849 => Opcode::FRINTP_ZPmZ_H_UNDEF, + 850 => Opcode::FRINTP_ZPmZ_S_UNDEF, + 851 => Opcode::FRINTX_ZPmZ_D_UNDEF, + 852 => Opcode::FRINTX_ZPmZ_H_UNDEF, + 853 => Opcode::FRINTX_ZPmZ_S_UNDEF, + 854 => Opcode::FRINTZ_ZPmZ_D_UNDEF, + 855 => Opcode::FRINTZ_ZPmZ_H_UNDEF, + 856 => Opcode::FRINTZ_ZPmZ_S_UNDEF, + 857 => Opcode::FSQRT_ZPmZ_D_UNDEF, + 858 => Opcode::FSQRT_ZPmZ_H_UNDEF, + 859 => Opcode::FSQRT_ZPmZ_S_UNDEF, + 860 => Opcode::FSUBR_ZPZI_D_UNDEF, + 861 => Opcode::FSUBR_ZPZI_D_ZERO, + 862 => Opcode::FSUBR_ZPZI_H_UNDEF, + 863 => Opcode::FSUBR_ZPZI_H_ZERO, + 864 => Opcode::FSUBR_ZPZI_S_UNDEF, + 865 => Opcode::FSUBR_ZPZI_S_ZERO, + 866 => Opcode::FSUBR_ZPZZ_D_ZERO, + 867 => Opcode::FSUBR_ZPZZ_H_ZERO, + 868 => Opcode::FSUBR_ZPZZ_S_ZERO, + 869 => Opcode::FSUB_VG2_M2Z_D_PSEUDO, + 870 => Opcode::FSUB_VG2_M2Z_H_PSEUDO, + 871 => Opcode::FSUB_VG2_M2Z_S_PSEUDO, + 872 => Opcode::FSUB_VG4_M4Z_D_PSEUDO, + 873 => Opcode::FSUB_VG4_M4Z_H_PSEUDO, + 874 => Opcode::FSUB_VG4_M4Z_S_PSEUDO, + 875 => Opcode::FSUB_ZPZI_D_UNDEF, + 876 => Opcode::FSUB_ZPZI_D_ZERO, + 877 => Opcode::FSUB_ZPZI_H_UNDEF, + 878 => Opcode::FSUB_ZPZI_H_ZERO, + 879 => Opcode::FSUB_ZPZI_S_UNDEF, + 880 => Opcode::FSUB_ZPZI_S_ZERO, + 881 => Opcode::FSUB_ZPZZ_D_UNDEF, + 882 => Opcode::FSUB_ZPZZ_D_ZERO, + 883 => Opcode::FSUB_ZPZZ_H_UNDEF, + 884 => Opcode::FSUB_ZPZZ_H_ZERO, + 885 => Opcode::FSUB_ZPZZ_S_UNDEF, + 886 => Opcode::FSUB_ZPZZ_S_ZERO, + 887 => Opcode::FTMOPA_M2ZZZI_BtoH_PSEUDO, + 888 => Opcode::FTMOPA_M2ZZZI_BtoS_PSEUDO, + 889 => Opcode::FTMOPA_M2ZZZI_HtoH_PSEUDO, + 890 => Opcode::FTMOPA_M2ZZZI_HtoS_PSEUDO, + 891 => Opcode::FTMOPA_M2ZZZI_StoS_PSEUDO, + 892 => Opcode::FVDOTB_VG4_M2ZZI_BtoS_PSEUDO, + 893 => Opcode::FVDOTT_VG4_M2ZZI_BtoS_PSEUDO, + 894 => Opcode::FVDOT_VG2_M2ZZI_BtoH_PSEUDO, + 895 => Opcode::FVDOT_VG2_M2ZZI_HtoS_PSEUDO, + 896 => Opcode::G_AARCH64_PREFETCH, + 897 => Opcode::G_AARCH64_RANGE_PREFETCH, + 898 => Opcode::G_ADD_LOW, + 899 => Opcode::G_BSP, + 900 => Opcode::G_DUP, + 901 => Opcode::G_DUPLANE16, + 902 => Opcode::G_DUPLANE32, + 903 => Opcode::G_DUPLANE64, + 904 => Opcode::G_DUPLANE8, + 905 => Opcode::G_EXT, + 906 => Opcode::G_FCMEQ, + 907 => Opcode::G_FCMGE, + 908 => Opcode::G_FCMGT, + 909 => Opcode::G_FPTRUNC_ODD, + 910 => Opcode::G_PMULL, + 911 => Opcode::G_REV16, + 912 => Opcode::G_REV32, + 913 => Opcode::G_REV64, + 914 => Opcode::G_SADDLP, + 915 => Opcode::G_SADDLV, + 916 => Opcode::G_SDOT, + 917 => Opcode::G_SITOF, + 918 => Opcode::G_SLI, + 919 => Opcode::G_SMULL, + 920 => Opcode::G_SQSHLU_I, + 921 => Opcode::G_SRI, + 922 => Opcode::G_SRSHR_I, + 923 => Opcode::G_TRN1, + 924 => Opcode::G_TRN2, + 925 => Opcode::G_UADDLP, + 926 => Opcode::G_UADDLV, + 927 => Opcode::G_UDOT, + 928 => Opcode::G_UITOF, + 929 => Opcode::G_UMULL, + 930 => Opcode::G_URSHR_I, + 931 => Opcode::G_USDOT, + 932 => Opcode::G_UZP1, + 933 => Opcode::G_UZP2, + 934 => Opcode::G_VASHR, + 935 => Opcode::G_VLSHR, + 936 => Opcode::G_ZIP1, + 937 => Opcode::G_ZIP2, + 938 => Opcode::GetSMESaveSize, + 939 => Opcode::HOM_Epilog, + 940 => Opcode::HOM_Prolog, + 941 => Opcode::HWASAN_CHECK_MEMACCESS, + 942 => Opcode::HWASAN_CHECK_MEMACCESS_FIXEDSHADOW, + 943 => Opcode::HWASAN_CHECK_MEMACCESS_SHORTGRANULES, + 944 => Opcode::HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW, + 945 => Opcode::INSERT_MXIPZ_H_PSEUDO_B, + 946 => Opcode::INSERT_MXIPZ_H_PSEUDO_D, + 947 => Opcode::INSERT_MXIPZ_H_PSEUDO_H, + 948 => Opcode::INSERT_MXIPZ_H_PSEUDO_Q, + 949 => Opcode::INSERT_MXIPZ_H_PSEUDO_S, + 950 => Opcode::INSERT_MXIPZ_V_PSEUDO_B, + 951 => Opcode::INSERT_MXIPZ_V_PSEUDO_D, + 952 => Opcode::INSERT_MXIPZ_V_PSEUDO_H, + 953 => Opcode::INSERT_MXIPZ_V_PSEUDO_Q, + 954 => Opcode::INSERT_MXIPZ_V_PSEUDO_S, + 955 => Opcode::IRGstack, + 956 => Opcode::InOutZAUsePseudo, + 957 => Opcode::InitTPIDR2Obj, + 958 => Opcode::JumpTableDest16, + 959 => Opcode::JumpTableDest32, + 960 => Opcode::JumpTableDest8, + 961 => Opcode::KCFI_CHECK, + 962 => Opcode::LD1B_2Z_IMM_PSEUDO, + 963 => Opcode::LD1B_2Z_PSEUDO, + 964 => Opcode::LD1B_4Z_IMM_PSEUDO, + 965 => Opcode::LD1B_4Z_PSEUDO, + 966 => Opcode::LD1D_2Z_IMM_PSEUDO, + 967 => Opcode::LD1D_2Z_PSEUDO, + 968 => Opcode::LD1D_4Z_IMM_PSEUDO, + 969 => Opcode::LD1D_4Z_PSEUDO, + 970 => Opcode::LD1H_2Z_IMM_PSEUDO, + 971 => Opcode::LD1H_2Z_PSEUDO, + 972 => Opcode::LD1H_4Z_IMM_PSEUDO, + 973 => Opcode::LD1H_4Z_PSEUDO, + 974 => Opcode::LD1W_2Z_IMM_PSEUDO, + 975 => Opcode::LD1W_2Z_PSEUDO, + 976 => Opcode::LD1W_4Z_IMM_PSEUDO, + 977 => Opcode::LD1W_4Z_PSEUDO, + 978 => Opcode::LD1_MXIPXX_H_PSEUDO_B, + 979 => Opcode::LD1_MXIPXX_H_PSEUDO_D, + 980 => Opcode::LD1_MXIPXX_H_PSEUDO_H, + 981 => Opcode::LD1_MXIPXX_H_PSEUDO_Q, + 982 => Opcode::LD1_MXIPXX_H_PSEUDO_S, + 983 => Opcode::LD1_MXIPXX_V_PSEUDO_B, + 984 => Opcode::LD1_MXIPXX_V_PSEUDO_D, + 985 => Opcode::LD1_MXIPXX_V_PSEUDO_H, + 986 => Opcode::LD1_MXIPXX_V_PSEUDO_Q, + 987 => Opcode::LD1_MXIPXX_V_PSEUDO_S, + 988 => Opcode::LDNT1B_2Z_IMM_PSEUDO, + 989 => Opcode::LDNT1B_2Z_PSEUDO, + 990 => Opcode::LDNT1B_4Z_IMM_PSEUDO, + 991 => Opcode::LDNT1B_4Z_PSEUDO, + 992 => Opcode::LDNT1D_2Z_IMM_PSEUDO, + 993 => Opcode::LDNT1D_2Z_PSEUDO, + 994 => Opcode::LDNT1D_4Z_IMM_PSEUDO, + 995 => Opcode::LDNT1D_4Z_PSEUDO, + 996 => Opcode::LDNT1H_2Z_IMM_PSEUDO, + 997 => Opcode::LDNT1H_2Z_PSEUDO, + 998 => Opcode::LDNT1H_4Z_IMM_PSEUDO, + 999 => Opcode::LDNT1H_4Z_PSEUDO, + 1000 => Opcode::LDNT1W_2Z_IMM_PSEUDO, + 1001 => Opcode::LDNT1W_2Z_PSEUDO, + 1002 => Opcode::LDNT1W_4Z_IMM_PSEUDO, + 1003 => Opcode::LDNT1W_4Z_PSEUDO, + 1004 => Opcode::LDR_PPXI, + 1005 => Opcode::LDR_TX_PSEUDO, + 1006 => Opcode::LDR_ZA_PSEUDO, + 1007 => Opcode::LDR_ZZXI, + 1008 => Opcode::LDR_ZZXI_STRIDED_CONTIGUOUS, + 1009 => Opcode::LDR_ZZZXI, + 1010 => Opcode::LDR_ZZZZXI, + 1011 => Opcode::LDR_ZZZZXI_STRIDED_CONTIGUOUS, + 1012 => Opcode::LOADauthptrstatic, + 1013 => Opcode::LOADgot, + 1014 => Opcode::LOADgotAUTH, + 1015 => Opcode::LOADgotPAC, + 1016 => Opcode::LSL_ZPZI_B_UNDEF, + 1017 => Opcode::LSL_ZPZI_B_ZERO, + 1018 => Opcode::LSL_ZPZI_D_UNDEF, + 1019 => Opcode::LSL_ZPZI_D_ZERO, + 1020 => Opcode::LSL_ZPZI_H_UNDEF, + 1021 => Opcode::LSL_ZPZI_H_ZERO, + 1022 => Opcode::LSL_ZPZI_S_UNDEF, + 1023 => Opcode::LSL_ZPZI_S_ZERO, + 1024 => Opcode::LSL_ZPZZ_B_UNDEF, + 1025 => Opcode::LSL_ZPZZ_B_ZERO, + 1026 => Opcode::LSL_ZPZZ_D_UNDEF, + 1027 => Opcode::LSL_ZPZZ_D_ZERO, + 1028 => Opcode::LSL_ZPZZ_H_UNDEF, + 1029 => Opcode::LSL_ZPZZ_H_ZERO, + 1030 => Opcode::LSL_ZPZZ_S_UNDEF, + 1031 => Opcode::LSL_ZPZZ_S_ZERO, + 1032 => Opcode::LSR_ZPZI_B_UNDEF, + 1033 => Opcode::LSR_ZPZI_B_ZERO, + 1034 => Opcode::LSR_ZPZI_D_UNDEF, + 1035 => Opcode::LSR_ZPZI_D_ZERO, + 1036 => Opcode::LSR_ZPZI_H_UNDEF, + 1037 => Opcode::LSR_ZPZI_H_ZERO, + 1038 => Opcode::LSR_ZPZI_S_UNDEF, + 1039 => Opcode::LSR_ZPZI_S_ZERO, + 1040 => Opcode::LSR_ZPZZ_B_UNDEF, + 1041 => Opcode::LSR_ZPZZ_B_ZERO, + 1042 => Opcode::LSR_ZPZZ_D_UNDEF, + 1043 => Opcode::LSR_ZPZZ_D_ZERO, + 1044 => Opcode::LSR_ZPZZ_H_UNDEF, + 1045 => Opcode::LSR_ZPZZ_H_ZERO, + 1046 => Opcode::LSR_ZPZZ_S_UNDEF, + 1047 => Opcode::LSR_ZPZZ_S_ZERO, + 1048 => Opcode::MLA_ZPZZZ_B_UNDEF, + 1049 => Opcode::MLA_ZPZZZ_D_UNDEF, + 1050 => Opcode::MLA_ZPZZZ_H_UNDEF, + 1051 => Opcode::MLA_ZPZZZ_S_UNDEF, + 1052 => Opcode::MLS_ZPZZZ_B_UNDEF, + 1053 => Opcode::MLS_ZPZZZ_D_UNDEF, + 1054 => Opcode::MLS_ZPZZZ_H_UNDEF, + 1055 => Opcode::MLS_ZPZZZ_S_UNDEF, + 1056 => Opcode::MOPSMemoryCopyPseudo, + 1057 => Opcode::MOPSMemoryMovePseudo, + 1058 => Opcode::MOPSMemorySetPseudo, + 1059 => Opcode::MOPSMemorySetTaggingPseudo, + 1060 => Opcode::MOVAZ_2ZMI_H_B_PSEUDO, + 1061 => Opcode::MOVAZ_2ZMI_H_D_PSEUDO, + 1062 => Opcode::MOVAZ_2ZMI_H_H_PSEUDO, + 1063 => Opcode::MOVAZ_2ZMI_H_S_PSEUDO, + 1064 => Opcode::MOVAZ_2ZMI_V_B_PSEUDO, + 1065 => Opcode::MOVAZ_2ZMI_V_D_PSEUDO, + 1066 => Opcode::MOVAZ_2ZMI_V_H_PSEUDO, + 1067 => Opcode::MOVAZ_2ZMI_V_S_PSEUDO, + 1068 => Opcode::MOVAZ_4ZMI_H_B_PSEUDO, + 1069 => Opcode::MOVAZ_4ZMI_H_D_PSEUDO, + 1070 => Opcode::MOVAZ_4ZMI_H_H_PSEUDO, + 1071 => Opcode::MOVAZ_4ZMI_H_S_PSEUDO, + 1072 => Opcode::MOVAZ_4ZMI_V_B_PSEUDO, + 1073 => Opcode::MOVAZ_4ZMI_V_D_PSEUDO, + 1074 => Opcode::MOVAZ_4ZMI_V_H_PSEUDO, + 1075 => Opcode::MOVAZ_4ZMI_V_S_PSEUDO, + 1076 => Opcode::MOVAZ_VG2_2ZMXI_PSEUDO, + 1077 => Opcode::MOVAZ_VG4_4ZMXI_PSEUDO, + 1078 => Opcode::MOVAZ_ZMI_H_B_PSEUDO, + 1079 => Opcode::MOVAZ_ZMI_H_D_PSEUDO, + 1080 => Opcode::MOVAZ_ZMI_H_H_PSEUDO, + 1081 => Opcode::MOVAZ_ZMI_H_Q_PSEUDO, + 1082 => Opcode::MOVAZ_ZMI_H_S_PSEUDO, + 1083 => Opcode::MOVAZ_ZMI_V_B_PSEUDO, + 1084 => Opcode::MOVAZ_ZMI_V_D_PSEUDO, + 1085 => Opcode::MOVAZ_ZMI_V_H_PSEUDO, + 1086 => Opcode::MOVAZ_ZMI_V_Q_PSEUDO, + 1087 => Opcode::MOVAZ_ZMI_V_S_PSEUDO, + 1088 => Opcode::MOVA_MXI2Z_H_B_PSEUDO, + 1089 => Opcode::MOVA_MXI2Z_H_D_PSEUDO, + 1090 => Opcode::MOVA_MXI2Z_H_H_PSEUDO, + 1091 => Opcode::MOVA_MXI2Z_H_S_PSEUDO, + 1092 => Opcode::MOVA_MXI2Z_V_B_PSEUDO, + 1093 => Opcode::MOVA_MXI2Z_V_D_PSEUDO, + 1094 => Opcode::MOVA_MXI2Z_V_H_PSEUDO, + 1095 => Opcode::MOVA_MXI2Z_V_S_PSEUDO, + 1096 => Opcode::MOVA_MXI4Z_H_B_PSEUDO, + 1097 => Opcode::MOVA_MXI4Z_H_D_PSEUDO, + 1098 => Opcode::MOVA_MXI4Z_H_H_PSEUDO, + 1099 => Opcode::MOVA_MXI4Z_H_S_PSEUDO, + 1100 => Opcode::MOVA_MXI4Z_V_B_PSEUDO, + 1101 => Opcode::MOVA_MXI4Z_V_D_PSEUDO, + 1102 => Opcode::MOVA_MXI4Z_V_H_PSEUDO, + 1103 => Opcode::MOVA_MXI4Z_V_S_PSEUDO, + 1104 => Opcode::MOVA_VG2_MXI2Z_PSEUDO, + 1105 => Opcode::MOVA_VG4_MXI4Z_PSEUDO, + 1106 => Opcode::MOVMCSym, + 1107 => Opcode::MOVT_TIZ_PSEUDO, + 1108 => Opcode::MOVaddr, + 1109 => Opcode::MOVaddrBA, + 1110 => Opcode::MOVaddrCP, + 1111 => Opcode::MOVaddrEXT, + 1112 => Opcode::MOVaddrJT, + 1113 => Opcode::MOVaddrPAC, + 1114 => Opcode::MOVaddrTLS, + 1115 => Opcode::MOVbaseTLS, + 1116 => Opcode::MOVi32imm, + 1117 => Opcode::MOVi64imm, + 1118 => Opcode::MRS_FPCR, + 1119 => Opcode::MRS_FPSR, + 1120 => Opcode::MSR_FPCR, + 1121 => Opcode::MSR_FPMR, + 1122 => Opcode::MSR_FPSR, + 1123 => Opcode::MSRpstatePseudo, + 1124 => Opcode::MUL_ZPZZ_B_UNDEF, + 1125 => Opcode::MUL_ZPZZ_D_UNDEF, + 1126 => Opcode::MUL_ZPZZ_H_UNDEF, + 1127 => Opcode::MUL_ZPZZ_S_UNDEF, + 1128 => Opcode::NEG_ZPmZ_B_UNDEF, + 1129 => Opcode::NEG_ZPmZ_D_UNDEF, + 1130 => Opcode::NEG_ZPmZ_H_UNDEF, + 1131 => Opcode::NEG_ZPmZ_S_UNDEF, + 1132 => Opcode::NOT_ZPmZ_B_UNDEF, + 1133 => Opcode::NOT_ZPmZ_D_UNDEF, + 1134 => Opcode::NOT_ZPmZ_H_UNDEF, + 1135 => Opcode::NOT_ZPmZ_S_UNDEF, + 1136 => Opcode::ORNWrr, + 1137 => Opcode::ORNXrr, + 1138 => Opcode::ORRWrr, + 1139 => Opcode::ORRXrr, + 1140 => Opcode::ORR_ZPZZ_B_ZERO, + 1141 => Opcode::ORR_ZPZZ_D_ZERO, + 1142 => Opcode::ORR_ZPZZ_H_ZERO, + 1143 => Opcode::ORR_ZPZZ_S_ZERO, + 1144 => Opcode::PAC, + 1145 => Opcode::PAUTH_EPILOGUE, + 1146 => Opcode::PAUTH_PROLOGUE, + 1147 => Opcode::PROBED_STACKALLOC, + 1148 => Opcode::PROBED_STACKALLOC_DYN, + 1149 => Opcode::PROBED_STACKALLOC_VAR, + 1150 => Opcode::PTEST_PP_ANY, + 1151 => Opcode::PTEST_PP_FIRST, + 1152 => Opcode::RET_ReallyLR, + 1153 => Opcode::RequiresZASavePseudo, + 1154 => Opcode::RequiresZT0SavePseudo, + 1155 => Opcode::RestoreZAPseudo, + 1156 => Opcode::SABD_ZPZZ_B_UNDEF, + 1157 => Opcode::SABD_ZPZZ_D_UNDEF, + 1158 => Opcode::SABD_ZPZZ_H_UNDEF, + 1159 => Opcode::SABD_ZPZZ_S_UNDEF, + 1160 => Opcode::SCVTF_ZPmZ_DtoD_UNDEF, + 1161 => Opcode::SCVTF_ZPmZ_DtoH_UNDEF, + 1162 => Opcode::SCVTF_ZPmZ_DtoS_UNDEF, + 1163 => Opcode::SCVTF_ZPmZ_HtoH_UNDEF, + 1164 => Opcode::SCVTF_ZPmZ_StoD_UNDEF, + 1165 => Opcode::SCVTF_ZPmZ_StoH_UNDEF, + 1166 => Opcode::SCVTF_ZPmZ_StoS_UNDEF, + 1167 => Opcode::SDIV_ZPZZ_D_UNDEF, + 1168 => Opcode::SDIV_ZPZZ_S_UNDEF, + 1169 => Opcode::SDOT_VG2_M2Z2Z_BtoS_PSEUDO, + 1170 => Opcode::SDOT_VG2_M2Z2Z_HtoD_PSEUDO, + 1171 => Opcode::SDOT_VG2_M2Z2Z_HtoS_PSEUDO, + 1172 => Opcode::SDOT_VG2_M2ZZI_BToS_PSEUDO, + 1173 => Opcode::SDOT_VG2_M2ZZI_HToS_PSEUDO, + 1174 => Opcode::SDOT_VG2_M2ZZI_HtoD_PSEUDO, + 1175 => Opcode::SDOT_VG2_M2ZZ_BtoS_PSEUDO, + 1176 => Opcode::SDOT_VG2_M2ZZ_HtoD_PSEUDO, + 1177 => Opcode::SDOT_VG2_M2ZZ_HtoS_PSEUDO, + 1178 => Opcode::SDOT_VG4_M4Z4Z_BtoS_PSEUDO, + 1179 => Opcode::SDOT_VG4_M4Z4Z_HtoD_PSEUDO, + 1180 => Opcode::SDOT_VG4_M4Z4Z_HtoS_PSEUDO, + 1181 => Opcode::SDOT_VG4_M4ZZI_BToS_PSEUDO, + 1182 => Opcode::SDOT_VG4_M4ZZI_HToS_PSEUDO, + 1183 => Opcode::SDOT_VG4_M4ZZI_HtoD_PSEUDO, + 1184 => Opcode::SDOT_VG4_M4ZZ_BtoS_PSEUDO, + 1185 => Opcode::SDOT_VG4_M4ZZ_HtoD_PSEUDO, + 1186 => Opcode::SDOT_VG4_M4ZZ_HtoS_PSEUDO, + 1187 => Opcode::SEH_AddFP, + 1188 => Opcode::SEH_AllocZ, + 1189 => Opcode::SEH_EpilogEnd, + 1190 => Opcode::SEH_EpilogStart, + 1191 => Opcode::SEH_Nop, + 1192 => Opcode::SEH_PACSignLR, + 1193 => Opcode::SEH_PrologEnd, + 1194 => Opcode::SEH_SaveAnyRegI, + 1195 => Opcode::SEH_SaveAnyRegIP, + 1196 => Opcode::SEH_SaveAnyRegQP, + 1197 => Opcode::SEH_SaveAnyRegQPX, + 1198 => Opcode::SEH_SaveFPLR, + 1199 => Opcode::SEH_SaveFPLR_X, + 1200 => Opcode::SEH_SaveFReg, + 1201 => Opcode::SEH_SaveFRegP, + 1202 => Opcode::SEH_SaveFRegP_X, + 1203 => Opcode::SEH_SaveFReg_X, + 1204 => Opcode::SEH_SavePReg, + 1205 => Opcode::SEH_SaveReg, + 1206 => Opcode::SEH_SaveRegP, + 1207 => Opcode::SEH_SaveRegP_X, + 1208 => Opcode::SEH_SaveReg_X, + 1209 => Opcode::SEH_SaveZReg, + 1210 => Opcode::SEH_SetFP, + 1211 => Opcode::SEH_StackAlloc, + 1212 => Opcode::SHSUB_ZPZZ_B_UNDEF, + 1213 => Opcode::SHSUB_ZPZZ_D_UNDEF, + 1214 => Opcode::SHSUB_ZPZZ_H_UNDEF, + 1215 => Opcode::SHSUB_ZPZZ_S_UNDEF, + 1216 => Opcode::SMAX_ZPZZ_B_UNDEF, + 1217 => Opcode::SMAX_ZPZZ_D_UNDEF, + 1218 => Opcode::SMAX_ZPZZ_H_UNDEF, + 1219 => Opcode::SMAX_ZPZZ_S_UNDEF, + 1220 => Opcode::SMEStateAllocPseudo, + 1221 => Opcode::SMIN_ZPZZ_B_UNDEF, + 1222 => Opcode::SMIN_ZPZZ_D_UNDEF, + 1223 => Opcode::SMIN_ZPZZ_H_UNDEF, + 1224 => Opcode::SMIN_ZPZZ_S_UNDEF, + 1225 => Opcode::SMLALL_MZZI_BtoS_PSEUDO, + 1226 => Opcode::SMLALL_MZZI_HtoD_PSEUDO, + 1227 => Opcode::SMLALL_MZZ_BtoS_PSEUDO, + 1228 => Opcode::SMLALL_MZZ_HtoD_PSEUDO, + 1229 => Opcode::SMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + 1230 => Opcode::SMLALL_VG2_M2Z2Z_HtoD_PSEUDO, + 1231 => Opcode::SMLALL_VG2_M2ZZI_BtoS_PSEUDO, + 1232 => Opcode::SMLALL_VG2_M2ZZI_HtoD_PSEUDO, + 1233 => Opcode::SMLALL_VG2_M2ZZ_BtoS_PSEUDO, + 1234 => Opcode::SMLALL_VG2_M2ZZ_HtoD_PSEUDO, + 1235 => Opcode::SMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + 1236 => Opcode::SMLALL_VG4_M4Z4Z_HtoD_PSEUDO, + 1237 => Opcode::SMLALL_VG4_M4ZZI_BtoS_PSEUDO, + 1238 => Opcode::SMLALL_VG4_M4ZZI_HtoD_PSEUDO, + 1239 => Opcode::SMLALL_VG4_M4ZZ_BtoS_PSEUDO, + 1240 => Opcode::SMLALL_VG4_M4ZZ_HtoD_PSEUDO, + 1241 => Opcode::SMLAL_MZZI_HtoS_PSEUDO, + 1242 => Opcode::SMLAL_MZZ_HtoS_PSEUDO, + 1243 => Opcode::SMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + 1244 => Opcode::SMLAL_VG2_M2ZZI_S_PSEUDO, + 1245 => Opcode::SMLAL_VG2_M2ZZ_HtoS_PSEUDO, + 1246 => Opcode::SMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + 1247 => Opcode::SMLAL_VG4_M4ZZI_HtoS_PSEUDO, + 1248 => Opcode::SMLAL_VG4_M4ZZ_HtoS_PSEUDO, + 1249 => Opcode::SMLSLL_MZZI_BtoS_PSEUDO, + 1250 => Opcode::SMLSLL_MZZI_HtoD_PSEUDO, + 1251 => Opcode::SMLSLL_MZZ_BtoS_PSEUDO, + 1252 => Opcode::SMLSLL_MZZ_HtoD_PSEUDO, + 1253 => Opcode::SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO, + 1254 => Opcode::SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO, + 1255 => Opcode::SMLSLL_VG2_M2ZZI_BtoS_PSEUDO, + 1256 => Opcode::SMLSLL_VG2_M2ZZI_HtoD_PSEUDO, + 1257 => Opcode::SMLSLL_VG2_M2ZZ_BtoS_PSEUDO, + 1258 => Opcode::SMLSLL_VG2_M2ZZ_HtoD_PSEUDO, + 1259 => Opcode::SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO, + 1260 => Opcode::SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO, + 1261 => Opcode::SMLSLL_VG4_M4ZZI_BtoS_PSEUDO, + 1262 => Opcode::SMLSLL_VG4_M4ZZI_HtoD_PSEUDO, + 1263 => Opcode::SMLSLL_VG4_M4ZZ_BtoS_PSEUDO, + 1264 => Opcode::SMLSLL_VG4_M4ZZ_HtoD_PSEUDO, + 1265 => Opcode::SMLSL_MZZI_HtoS_PSEUDO, + 1266 => Opcode::SMLSL_MZZ_HtoS_PSEUDO, + 1267 => Opcode::SMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + 1268 => Opcode::SMLSL_VG2_M2ZZI_S_PSEUDO, + 1269 => Opcode::SMLSL_VG2_M2ZZ_HtoS_PSEUDO, + 1270 => Opcode::SMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + 1271 => Opcode::SMLSL_VG4_M4ZZI_HtoS_PSEUDO, + 1272 => Opcode::SMLSL_VG4_M4ZZ_HtoS_PSEUDO, + 1273 => Opcode::SMOP4A_M2Z2Z_BToS_PSEUDO, + 1274 => Opcode::SMOP4A_M2Z2Z_HToS_PSEUDO, + 1275 => Opcode::SMOP4A_M2Z2Z_HtoD_PSEUDO, + 1276 => Opcode::SMOP4A_M2ZZ_BToS_PSEUDO, + 1277 => Opcode::SMOP4A_M2ZZ_HToS_PSEUDO, + 1278 => Opcode::SMOP4A_M2ZZ_HtoD_PSEUDO, + 1279 => Opcode::SMOP4A_MZ2Z_BToS_PSEUDO, + 1280 => Opcode::SMOP4A_MZ2Z_HToS_PSEUDO, + 1281 => Opcode::SMOP4A_MZ2Z_HtoD_PSEUDO, + 1282 => Opcode::SMOP4A_MZZ_BToS_PSEUDO, + 1283 => Opcode::SMOP4A_MZZ_HToS_PSEUDO, + 1284 => Opcode::SMOP4A_MZZ_HtoD_PSEUDO, + 1285 => Opcode::SMOP4S_M2Z2Z_BToS_PSEUDO, + 1286 => Opcode::SMOP4S_M2Z2Z_HToS_PSEUDO, + 1287 => Opcode::SMOP4S_M2Z2Z_HtoD_PSEUDO, + 1288 => Opcode::SMOP4S_M2ZZ_BToS_PSEUDO, + 1289 => Opcode::SMOP4S_M2ZZ_HToS_PSEUDO, + 1290 => Opcode::SMOP4S_M2ZZ_HtoD_PSEUDO, + 1291 => Opcode::SMOP4S_MZ2Z_BToS_PSEUDO, + 1292 => Opcode::SMOP4S_MZ2Z_HToS_PSEUDO, + 1293 => Opcode::SMOP4S_MZ2Z_HtoD_PSEUDO, + 1294 => Opcode::SMOP4S_MZZ_BToS_PSEUDO, + 1295 => Opcode::SMOP4S_MZZ_HToS_PSEUDO, + 1296 => Opcode::SMOP4S_MZZ_HtoD_PSEUDO, + 1297 => Opcode::SMOPA_MPPZZ_D_PSEUDO, + 1298 => Opcode::SMOPA_MPPZZ_HtoS_PSEUDO, + 1299 => Opcode::SMOPA_MPPZZ_S_PSEUDO, + 1300 => Opcode::SMOPS_MPPZZ_D_PSEUDO, + 1301 => Opcode::SMOPS_MPPZZ_HtoS_PSEUDO, + 1302 => Opcode::SMOPS_MPPZZ_S_PSEUDO, + 1303 => Opcode::SMULH_ZPZZ_B_UNDEF, + 1304 => Opcode::SMULH_ZPZZ_D_UNDEF, + 1305 => Opcode::SMULH_ZPZZ_H_UNDEF, + 1306 => Opcode::SMULH_ZPZZ_S_UNDEF, + 1307 => Opcode::SPACE, + 1308 => Opcode::SQABS_ZPmZ_B_UNDEF, + 1309 => Opcode::SQABS_ZPmZ_D_UNDEF, + 1310 => Opcode::SQABS_ZPmZ_H_UNDEF, + 1311 => Opcode::SQABS_ZPmZ_S_UNDEF, + 1312 => Opcode::SQNEG_ZPmZ_B_UNDEF, + 1313 => Opcode::SQNEG_ZPmZ_D_UNDEF, + 1314 => Opcode::SQNEG_ZPmZ_H_UNDEF, + 1315 => Opcode::SQNEG_ZPmZ_S_UNDEF, + 1316 => Opcode::SQRSHL_ZPZZ_B_UNDEF, + 1317 => Opcode::SQRSHL_ZPZZ_D_UNDEF, + 1318 => Opcode::SQRSHL_ZPZZ_H_UNDEF, + 1319 => Opcode::SQRSHL_ZPZZ_S_UNDEF, + 1320 => Opcode::SQSHLU_ZPZI_B_ZERO, + 1321 => Opcode::SQSHLU_ZPZI_D_ZERO, + 1322 => Opcode::SQSHLU_ZPZI_H_ZERO, + 1323 => Opcode::SQSHLU_ZPZI_S_ZERO, + 1324 => Opcode::SQSHL_ZPZI_B_UNDEF, + 1325 => Opcode::SQSHL_ZPZI_B_ZERO, + 1326 => Opcode::SQSHL_ZPZI_D_UNDEF, + 1327 => Opcode::SQSHL_ZPZI_D_ZERO, + 1328 => Opcode::SQSHL_ZPZI_H_UNDEF, + 1329 => Opcode::SQSHL_ZPZI_H_ZERO, + 1330 => Opcode::SQSHL_ZPZI_S_UNDEF, + 1331 => Opcode::SQSHL_ZPZI_S_ZERO, + 1332 => Opcode::SQSHL_ZPZZ_B_UNDEF, + 1333 => Opcode::SQSHL_ZPZZ_D_UNDEF, + 1334 => Opcode::SQSHL_ZPZZ_H_UNDEF, + 1335 => Opcode::SQSHL_ZPZZ_S_UNDEF, + 1336 => Opcode::SRSHL_ZPZZ_B_UNDEF, + 1337 => Opcode::SRSHL_ZPZZ_D_UNDEF, + 1338 => Opcode::SRSHL_ZPZZ_H_UNDEF, + 1339 => Opcode::SRSHL_ZPZZ_S_UNDEF, + 1340 => Opcode::SRSHR_ZPZI_B_ZERO, + 1341 => Opcode::SRSHR_ZPZI_D_ZERO, + 1342 => Opcode::SRSHR_ZPZI_H_ZERO, + 1343 => Opcode::SRSHR_ZPZI_S_ZERO, + 1344 => Opcode::STGloop, + 1345 => Opcode::STGloop_wback, + 1346 => Opcode::STMOPA_M2ZZZI_BtoS_PSEUDO, + 1347 => Opcode::STMOPA_M2ZZZI_HtoS_PSEUDO, + 1348 => Opcode::STR_PPXI, + 1349 => Opcode::STR_TX_PSEUDO, + 1350 => Opcode::STR_ZZXI, + 1351 => Opcode::STR_ZZXI_STRIDED_CONTIGUOUS, + 1352 => Opcode::STR_ZZZXI, + 1353 => Opcode::STR_ZZZZXI, + 1354 => Opcode::STR_ZZZZXI_STRIDED_CONTIGUOUS, + 1355 => Opcode::STZGloop, + 1356 => Opcode::STZGloop_wback, + 1357 => Opcode::SUBR_ZPZZ_B_ZERO, + 1358 => Opcode::SUBR_ZPZZ_D_ZERO, + 1359 => Opcode::SUBR_ZPZZ_H_ZERO, + 1360 => Opcode::SUBR_ZPZZ_S_ZERO, + 1361 => Opcode::SUBSWrr, + 1362 => Opcode::SUBSXrr, + 1363 => Opcode::SUBWrr, + 1364 => Opcode::SUBXrr, + 1365 => Opcode::SUB_VG2_M2Z2Z_D_PSEUDO, + 1366 => Opcode::SUB_VG2_M2Z2Z_S_PSEUDO, + 1367 => Opcode::SUB_VG2_M2ZZ_D_PSEUDO, + 1368 => Opcode::SUB_VG2_M2ZZ_S_PSEUDO, + 1369 => Opcode::SUB_VG2_M2Z_D_PSEUDO, + 1370 => Opcode::SUB_VG2_M2Z_S_PSEUDO, + 1371 => Opcode::SUB_VG4_M4Z4Z_D_PSEUDO, + 1372 => Opcode::SUB_VG4_M4Z4Z_S_PSEUDO, + 1373 => Opcode::SUB_VG4_M4ZZ_D_PSEUDO, + 1374 => Opcode::SUB_VG4_M4ZZ_S_PSEUDO, + 1375 => Opcode::SUB_VG4_M4Z_D_PSEUDO, + 1376 => Opcode::SUB_VG4_M4Z_S_PSEUDO, + 1377 => Opcode::SUB_ZPZZ_B_ZERO, + 1378 => Opcode::SUB_ZPZZ_D_ZERO, + 1379 => Opcode::SUB_ZPZZ_H_ZERO, + 1380 => Opcode::SUB_ZPZZ_S_ZERO, + 1381 => Opcode::SUDOT_VG2_M2ZZI_BToS_PSEUDO, + 1382 => Opcode::SUDOT_VG2_M2ZZ_BToS_PSEUDO, + 1383 => Opcode::SUDOT_VG4_M4ZZI_BToS_PSEUDO, + 1384 => Opcode::SUDOT_VG4_M4ZZ_BToS_PSEUDO, + 1385 => Opcode::SUMLALL_MZZI_BtoS_PSEUDO, + 1386 => Opcode::SUMLALL_VG2_M2ZZI_BtoS_PSEUDO, + 1387 => Opcode::SUMLALL_VG2_M2ZZ_BtoS_PSEUDO, + 1388 => Opcode::SUMLALL_VG4_M4ZZI_BtoS_PSEUDO, + 1389 => Opcode::SUMLALL_VG4_M4ZZ_BtoS_PSEUDO, + 1390 => Opcode::SUMOP4A_M2Z2Z_BToS_PSEUDO, + 1391 => Opcode::SUMOP4A_M2Z2Z_HtoD_PSEUDO, + 1392 => Opcode::SUMOP4A_M2ZZ_BToS_PSEUDO, + 1393 => Opcode::SUMOP4A_M2ZZ_HtoD_PSEUDO, + 1394 => Opcode::SUMOP4A_MZ2Z_BToS_PSEUDO, + 1395 => Opcode::SUMOP4A_MZ2Z_HtoD_PSEUDO, + 1396 => Opcode::SUMOP4A_MZZ_BToS_PSEUDO, + 1397 => Opcode::SUMOP4A_MZZ_HtoD_PSEUDO, + 1398 => Opcode::SUMOP4S_M2Z2Z_BToS_PSEUDO, + 1399 => Opcode::SUMOP4S_M2Z2Z_HtoD_PSEUDO, + 1400 => Opcode::SUMOP4S_M2ZZ_BToS_PSEUDO, + 1401 => Opcode::SUMOP4S_M2ZZ_HtoD_PSEUDO, + 1402 => Opcode::SUMOP4S_MZ2Z_BToS_PSEUDO, + 1403 => Opcode::SUMOP4S_MZ2Z_HtoD_PSEUDO, + 1404 => Opcode::SUMOP4S_MZZ_BToS_PSEUDO, + 1405 => Opcode::SUMOP4S_MZZ_HtoD_PSEUDO, + 1406 => Opcode::SUMOPA_MPPZZ_D_PSEUDO, + 1407 => Opcode::SUMOPA_MPPZZ_S_PSEUDO, + 1408 => Opcode::SUMOPS_MPPZZ_D_PSEUDO, + 1409 => Opcode::SUMOPS_MPPZZ_S_PSEUDO, + 1410 => Opcode::SUTMOPA_M2ZZZI_BtoS_PSEUDO, + 1411 => Opcode::SUVDOT_VG4_M4ZZI_BToS_PSEUDO, + 1412 => Opcode::SVDOT_VG2_M2ZZI_HtoS_PSEUDO, + 1413 => Opcode::SVDOT_VG4_M4ZZI_BtoS_PSEUDO, + 1414 => Opcode::SVDOT_VG4_M4ZZI_HtoD_PSEUDO, + 1415 => Opcode::SXTB_ZPmZ_D_UNDEF, + 1416 => Opcode::SXTB_ZPmZ_H_UNDEF, + 1417 => Opcode::SXTB_ZPmZ_S_UNDEF, + 1418 => Opcode::SXTH_ZPmZ_D_UNDEF, + 1419 => Opcode::SXTH_ZPmZ_S_UNDEF, + 1420 => Opcode::SXTW_ZPmZ_D_UNDEF, + 1421 => Opcode::SpeculationBarrierISBDSBEndBB, + 1422 => Opcode::SpeculationBarrierSBEndBB, + 1423 => Opcode::SpeculationSafeValueW, + 1424 => Opcode::SpeculationSafeValueX, + 1425 => Opcode::StoreSwiftAsyncContext, + 1426 => Opcode::TAGPstack, + 1427 => Opcode::TCRETURNdi, + 1428 => Opcode::TCRETURNri, + 1429 => Opcode::TCRETURNriALL, + 1430 => Opcode::TCRETURNrinotx16, + 1431 => Opcode::TCRETURNrix16x17, + 1432 => Opcode::TCRETURNrix17, + 1433 => Opcode::TLSDESCCALL, + 1434 => Opcode::TLSDESC_AUTH_CALLSEQ, + 1435 => Opcode::TLSDESC_CALLSEQ, + 1436 => Opcode::UABD_ZPZZ_B_UNDEF, + 1437 => Opcode::UABD_ZPZZ_D_UNDEF, + 1438 => Opcode::UABD_ZPZZ_H_UNDEF, + 1439 => Opcode::UABD_ZPZZ_S_UNDEF, + 1440 => Opcode::UCVTF_ZPmZ_DtoD_UNDEF, + 1441 => Opcode::UCVTF_ZPmZ_DtoH_UNDEF, + 1442 => Opcode::UCVTF_ZPmZ_DtoS_UNDEF, + 1443 => Opcode::UCVTF_ZPmZ_HtoH_UNDEF, + 1444 => Opcode::UCVTF_ZPmZ_StoD_UNDEF, + 1445 => Opcode::UCVTF_ZPmZ_StoH_UNDEF, + 1446 => Opcode::UCVTF_ZPmZ_StoS_UNDEF, + 1447 => Opcode::UDIV_ZPZZ_D_UNDEF, + 1448 => Opcode::UDIV_ZPZZ_S_UNDEF, + 1449 => Opcode::UDOT_VG2_M2Z2Z_BtoS_PSEUDO, + 1450 => Opcode::UDOT_VG2_M2Z2Z_HtoD_PSEUDO, + 1451 => Opcode::UDOT_VG2_M2Z2Z_HtoS_PSEUDO, + 1452 => Opcode::UDOT_VG2_M2ZZI_BToS_PSEUDO, + 1453 => Opcode::UDOT_VG2_M2ZZI_HToS_PSEUDO, + 1454 => Opcode::UDOT_VG2_M2ZZI_HtoD_PSEUDO, + 1455 => Opcode::UDOT_VG2_M2ZZ_BtoS_PSEUDO, + 1456 => Opcode::UDOT_VG2_M2ZZ_HtoD_PSEUDO, + 1457 => Opcode::UDOT_VG2_M2ZZ_HtoS_PSEUDO, + 1458 => Opcode::UDOT_VG4_M4Z4Z_BtoS_PSEUDO, + 1459 => Opcode::UDOT_VG4_M4Z4Z_HtoD_PSEUDO, + 1460 => Opcode::UDOT_VG4_M4Z4Z_HtoS_PSEUDO, + 1461 => Opcode::UDOT_VG4_M4ZZI_BtoS_PSEUDO, + 1462 => Opcode::UDOT_VG4_M4ZZI_HToS_PSEUDO, + 1463 => Opcode::UDOT_VG4_M4ZZI_HtoD_PSEUDO, + 1464 => Opcode::UDOT_VG4_M4ZZ_BtoS_PSEUDO, + 1465 => Opcode::UDOT_VG4_M4ZZ_HtoD_PSEUDO, + 1466 => Opcode::UDOT_VG4_M4ZZ_HtoS_PSEUDO, + 1467 => Opcode::UHSUB_ZPZZ_B_UNDEF, + 1468 => Opcode::UHSUB_ZPZZ_D_UNDEF, + 1469 => Opcode::UHSUB_ZPZZ_H_UNDEF, + 1470 => Opcode::UHSUB_ZPZZ_S_UNDEF, + 1471 => Opcode::UMAX_ZPZZ_B_UNDEF, + 1472 => Opcode::UMAX_ZPZZ_D_UNDEF, + 1473 => Opcode::UMAX_ZPZZ_H_UNDEF, + 1474 => Opcode::UMAX_ZPZZ_S_UNDEF, + 1475 => Opcode::UMIN_ZPZZ_B_UNDEF, + 1476 => Opcode::UMIN_ZPZZ_D_UNDEF, + 1477 => Opcode::UMIN_ZPZZ_H_UNDEF, + 1478 => Opcode::UMIN_ZPZZ_S_UNDEF, + 1479 => Opcode::UMLALL_MZZI_BtoS_PSEUDO, + 1480 => Opcode::UMLALL_MZZI_HtoD_PSEUDO, + 1481 => Opcode::UMLALL_MZZ_BtoS_PSEUDO, + 1482 => Opcode::UMLALL_MZZ_HtoD_PSEUDO, + 1483 => Opcode::UMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + 1484 => Opcode::UMLALL_VG2_M2Z2Z_HtoD_PSEUDO, + 1485 => Opcode::UMLALL_VG2_M2ZZI_BtoS_PSEUDO, + 1486 => Opcode::UMLALL_VG2_M2ZZI_HtoD_PSEUDO, + 1487 => Opcode::UMLALL_VG2_M2ZZ_BtoS_PSEUDO, + 1488 => Opcode::UMLALL_VG2_M2ZZ_HtoD_PSEUDO, + 1489 => Opcode::UMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + 1490 => Opcode::UMLALL_VG4_M4Z4Z_HtoD_PSEUDO, + 1491 => Opcode::UMLALL_VG4_M4ZZI_BtoS_PSEUDO, + 1492 => Opcode::UMLALL_VG4_M4ZZI_HtoD_PSEUDO, + 1493 => Opcode::UMLALL_VG4_M4ZZ_BtoS_PSEUDO, + 1494 => Opcode::UMLALL_VG4_M4ZZ_HtoD_PSEUDO, + 1495 => Opcode::UMLAL_MZZI_HtoS_PSEUDO, + 1496 => Opcode::UMLAL_MZZ_HtoS_PSEUDO, + 1497 => Opcode::UMLAL_VG2_M2Z2Z_HtoS_PSEUDO, + 1498 => Opcode::UMLAL_VG2_M2ZZI_S_PSEUDO, + 1499 => Opcode::UMLAL_VG2_M2ZZ_HtoS_PSEUDO, + 1500 => Opcode::UMLAL_VG4_M4Z4Z_HtoS_PSEUDO, + 1501 => Opcode::UMLAL_VG4_M4ZZI_HtoS_PSEUDO, + 1502 => Opcode::UMLAL_VG4_M4ZZ_HtoS_PSEUDO, + 1503 => Opcode::UMLSLL_MZZI_BtoS_PSEUDO, + 1504 => Opcode::UMLSLL_MZZI_HtoD_PSEUDO, + 1505 => Opcode::UMLSLL_MZZ_BtoS_PSEUDO, + 1506 => Opcode::UMLSLL_MZZ_HtoD_PSEUDO, + 1507 => Opcode::UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO, + 1508 => Opcode::UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO, + 1509 => Opcode::UMLSLL_VG2_M2ZZI_BtoS_PSEUDO, + 1510 => Opcode::UMLSLL_VG2_M2ZZI_HtoD_PSEUDO, + 1511 => Opcode::UMLSLL_VG2_M2ZZ_BtoS_PSEUDO, + 1512 => Opcode::UMLSLL_VG2_M2ZZ_HtoD_PSEUDO, + 1513 => Opcode::UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO, + 1514 => Opcode::UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO, + 1515 => Opcode::UMLSLL_VG4_M4ZZI_BtoS_PSEUDO, + 1516 => Opcode::UMLSLL_VG4_M4ZZI_HtoD_PSEUDO, + 1517 => Opcode::UMLSLL_VG4_M4ZZ_BtoS_PSEUDO, + 1518 => Opcode::UMLSLL_VG4_M4ZZ_HtoD_PSEUDO, + 1519 => Opcode::UMLSL_MZZI_HtoS_PSEUDO, + 1520 => Opcode::UMLSL_MZZ_HtoS_PSEUDO, + 1521 => Opcode::UMLSL_VG2_M2Z2Z_HtoS_PSEUDO, + 1522 => Opcode::UMLSL_VG2_M2ZZI_S_PSEUDO, + 1523 => Opcode::UMLSL_VG2_M2ZZ_HtoS_PSEUDO, + 1524 => Opcode::UMLSL_VG4_M4Z4Z_HtoS_PSEUDO, + 1525 => Opcode::UMLSL_VG4_M4ZZI_HtoS_PSEUDO, + 1526 => Opcode::UMLSL_VG4_M4ZZ_HtoS_PSEUDO, + 1527 => Opcode::UMOP4A_M2Z2Z_BToS_PSEUDO, + 1528 => Opcode::UMOP4A_M2Z2Z_HToS_PSEUDO, + 1529 => Opcode::UMOP4A_M2Z2Z_HtoD_PSEUDO, + 1530 => Opcode::UMOP4A_M2ZZ_BToS_PSEUDO, + 1531 => Opcode::UMOP4A_M2ZZ_HToS_PSEUDO, + 1532 => Opcode::UMOP4A_M2ZZ_HtoD_PSEUDO, + 1533 => Opcode::UMOP4A_MZ2Z_BToS_PSEUDO, + 1534 => Opcode::UMOP4A_MZ2Z_HToS_PSEUDO, + 1535 => Opcode::UMOP4A_MZ2Z_HtoD_PSEUDO, + 1536 => Opcode::UMOP4A_MZZ_BToS_PSEUDO, + 1537 => Opcode::UMOP4A_MZZ_HToS_PSEUDO, + 1538 => Opcode::UMOP4A_MZZ_HtoD_PSEUDO, + 1539 => Opcode::UMOP4S_M2Z2Z_BToS_PSEUDO, + 1540 => Opcode::UMOP4S_M2Z2Z_HToS_PSEUDO, + 1541 => Opcode::UMOP4S_M2Z2Z_HtoD_PSEUDO, + 1542 => Opcode::UMOP4S_M2ZZ_BToS_PSEUDO, + 1543 => Opcode::UMOP4S_M2ZZ_HToS_PSEUDO, + 1544 => Opcode::UMOP4S_M2ZZ_HtoD_PSEUDO, + 1545 => Opcode::UMOP4S_MZ2Z_BToS_PSEUDO, + 1546 => Opcode::UMOP4S_MZ2Z_HToS_PSEUDO, + 1547 => Opcode::UMOP4S_MZ2Z_HtoD_PSEUDO, + 1548 => Opcode::UMOP4S_MZZ_BToS_PSEUDO, + 1549 => Opcode::UMOP4S_MZZ_HToS_PSEUDO, + 1550 => Opcode::UMOP4S_MZZ_HtoD_PSEUDO, + 1551 => Opcode::UMOPA_MPPZZ_D_PSEUDO, + 1552 => Opcode::UMOPA_MPPZZ_HtoS_PSEUDO, + 1553 => Opcode::UMOPA_MPPZZ_S_PSEUDO, + 1554 => Opcode::UMOPS_MPPZZ_D_PSEUDO, + 1555 => Opcode::UMOPS_MPPZZ_HtoS_PSEUDO, + 1556 => Opcode::UMOPS_MPPZZ_S_PSEUDO, + 1557 => Opcode::UMULH_ZPZZ_B_UNDEF, + 1558 => Opcode::UMULH_ZPZZ_D_UNDEF, + 1559 => Opcode::UMULH_ZPZZ_H_UNDEF, + 1560 => Opcode::UMULH_ZPZZ_S_UNDEF, + 1561 => Opcode::UQRSHL_ZPZZ_B_UNDEF, + 1562 => Opcode::UQRSHL_ZPZZ_D_UNDEF, + 1563 => Opcode::UQRSHL_ZPZZ_H_UNDEF, + 1564 => Opcode::UQRSHL_ZPZZ_S_UNDEF, + 1565 => Opcode::UQSHL_ZPZI_B_UNDEF, + 1566 => Opcode::UQSHL_ZPZI_B_ZERO, + 1567 => Opcode::UQSHL_ZPZI_D_UNDEF, + 1568 => Opcode::UQSHL_ZPZI_D_ZERO, + 1569 => Opcode::UQSHL_ZPZI_H_UNDEF, + 1570 => Opcode::UQSHL_ZPZI_H_ZERO, + 1571 => Opcode::UQSHL_ZPZI_S_UNDEF, + 1572 => Opcode::UQSHL_ZPZI_S_ZERO, + 1573 => Opcode::UQSHL_ZPZZ_B_UNDEF, + 1574 => Opcode::UQSHL_ZPZZ_D_UNDEF, + 1575 => Opcode::UQSHL_ZPZZ_H_UNDEF, + 1576 => Opcode::UQSHL_ZPZZ_S_UNDEF, + 1577 => Opcode::URECPE_ZPmZ_S_UNDEF, + 1578 => Opcode::URSHL_ZPZZ_B_UNDEF, + 1579 => Opcode::URSHL_ZPZZ_D_UNDEF, + 1580 => Opcode::URSHL_ZPZZ_H_UNDEF, + 1581 => Opcode::URSHL_ZPZZ_S_UNDEF, + 1582 => Opcode::URSHR_ZPZI_B_ZERO, + 1583 => Opcode::URSHR_ZPZI_D_ZERO, + 1584 => Opcode::URSHR_ZPZI_H_ZERO, + 1585 => Opcode::URSHR_ZPZI_S_ZERO, + 1586 => Opcode::URSQRTE_ZPmZ_S_UNDEF, + 1587 => Opcode::USDOT_VG2_M2Z2Z_BToS_PSEUDO, + 1588 => Opcode::USDOT_VG2_M2ZZI_BToS_PSEUDO, + 1589 => Opcode::USDOT_VG2_M2ZZ_BToS_PSEUDO, + 1590 => Opcode::USDOT_VG4_M4Z4Z_BToS_PSEUDO, + 1591 => Opcode::USDOT_VG4_M4ZZI_BToS_PSEUDO, + 1592 => Opcode::USDOT_VG4_M4ZZ_BToS_PSEUDO, + 1593 => Opcode::USMLALL_MZZI_BtoS_PSEUDO, + 1594 => Opcode::USMLALL_MZZ_BtoS_PSEUDO, + 1595 => Opcode::USMLALL_VG2_M2Z2Z_BtoS_PSEUDO, + 1596 => Opcode::USMLALL_VG2_M2ZZI_BtoS_PSEUDO, + 1597 => Opcode::USMLALL_VG2_M2ZZ_BtoS_PSEUDO, + 1598 => Opcode::USMLALL_VG4_M4Z4Z_BtoS_PSEUDO, + 1599 => Opcode::USMLALL_VG4_M4ZZI_BtoS_PSEUDO, + 1600 => Opcode::USMLALL_VG4_M4ZZ_BtoS_PSEUDO, + 1601 => Opcode::USMOP4A_M2Z2Z_BToS_PSEUDO, + 1602 => Opcode::USMOP4A_M2Z2Z_HtoD_PSEUDO, + 1603 => Opcode::USMOP4A_M2ZZ_BToS_PSEUDO, + 1604 => Opcode::USMOP4A_M2ZZ_HtoD_PSEUDO, + 1605 => Opcode::USMOP4A_MZ2Z_BToS_PSEUDO, + 1606 => Opcode::USMOP4A_MZ2Z_HtoD_PSEUDO, + 1607 => Opcode::USMOP4A_MZZ_BToS_PSEUDO, + 1608 => Opcode::USMOP4A_MZZ_HtoD_PSEUDO, + 1609 => Opcode::USMOP4S_M2Z2Z_BToS_PSEUDO, + 1610 => Opcode::USMOP4S_M2Z2Z_HtoD_PSEUDO, + 1611 => Opcode::USMOP4S_M2ZZ_BToS_PSEUDO, + 1612 => Opcode::USMOP4S_M2ZZ_HtoD_PSEUDO, + 1613 => Opcode::USMOP4S_MZ2Z_BToS_PSEUDO, + 1614 => Opcode::USMOP4S_MZ2Z_HtoD_PSEUDO, + 1615 => Opcode::USMOP4S_MZZ_BToS_PSEUDO, + 1616 => Opcode::USMOP4S_MZZ_HtoD_PSEUDO, + 1617 => Opcode::USMOPA_MPPZZ_D_PSEUDO, + 1618 => Opcode::USMOPA_MPPZZ_S_PSEUDO, + 1619 => Opcode::USMOPS_MPPZZ_D_PSEUDO, + 1620 => Opcode::USMOPS_MPPZZ_S_PSEUDO, + 1621 => Opcode::USTMOPA_M2ZZZI_BtoS_PSEUDO, + 1622 => Opcode::USVDOT_VG4_M4ZZI_BToS_PSEUDO, + 1623 => Opcode::UTMOPA_M2ZZZI_BtoS_PSEUDO, + 1624 => Opcode::UTMOPA_M2ZZZI_HtoS_PSEUDO, + 1625 => Opcode::UVDOT_VG2_M2ZZI_HtoS_PSEUDO, + 1626 => Opcode::UVDOT_VG4_M4ZZI_BtoS_PSEUDO, + 1627 => Opcode::UVDOT_VG4_M4ZZI_HtoD_PSEUDO, + 1628 => Opcode::UXTB_ZPmZ_D_UNDEF, + 1629 => Opcode::UXTB_ZPmZ_H_UNDEF, + 1630 => Opcode::UXTB_ZPmZ_S_UNDEF, + 1631 => Opcode::UXTH_ZPmZ_D_UNDEF, + 1632 => Opcode::UXTH_ZPmZ_S_UNDEF, + 1633 => Opcode::UXTW_ZPmZ_D_UNDEF, + 1634 => Opcode::ZERO_MXI_2Z_PSEUDO, + 1635 => Opcode::ZERO_MXI_4Z_PSEUDO, + 1636 => Opcode::ZERO_MXI_VG2_2Z_PSEUDO, + 1637 => Opcode::ZERO_MXI_VG2_4Z_PSEUDO, + 1638 => Opcode::ZERO_MXI_VG2_Z_PSEUDO, + 1639 => Opcode::ZERO_MXI_VG4_2Z_PSEUDO, + 1640 => Opcode::ZERO_MXI_VG4_4Z_PSEUDO, + 1641 => Opcode::ZERO_MXI_VG4_Z_PSEUDO, + 1642 => Opcode::ZERO_M_PSEUDO, + 1643 => Opcode::ZERO_T_PSEUDO, + 1644 => Opcode::ABSWr, + 1645 => Opcode::ABSXr, + 1646 => Opcode::ABS_ZPmZ_B, + 1647 => Opcode::ABS_ZPmZ_D, + 1648 => Opcode::ABS_ZPmZ_H, + 1649 => Opcode::ABS_ZPmZ_S, + 1650 => Opcode::ABS_ZPzZ_B, + 1651 => Opcode::ABS_ZPzZ_D, + 1652 => Opcode::ABS_ZPzZ_H, + 1653 => Opcode::ABS_ZPzZ_S, + 1654 => Opcode::ABSv16i8, + 1655 => Opcode::ABSv1i64, + 1656 => Opcode::ABSv2i32, + 1657 => Opcode::ABSv2i64, + 1658 => Opcode::ABSv4i16, + 1659 => Opcode::ABSv4i32, + 1660 => Opcode::ABSv8i16, + 1661 => Opcode::ABSv8i8, + 1662 => Opcode::ADCLB_ZZZ_D, + 1663 => Opcode::ADCLB_ZZZ_S, + 1664 => Opcode::ADCLT_ZZZ_D, + 1665 => Opcode::ADCLT_ZZZ_S, + 1666 => Opcode::ADCSWr, + 1667 => Opcode::ADCSXr, + 1668 => Opcode::ADCWr, + 1669 => Opcode::ADCXr, + 1670 => Opcode::ADDG, + 1671 => Opcode::ADDHA_MPPZ_D, + 1672 => Opcode::ADDHA_MPPZ_S, + 1673 => Opcode::ADDHNB_ZZZ_B, + 1674 => Opcode::ADDHNB_ZZZ_H, + 1675 => Opcode::ADDHNB_ZZZ_S, + 1676 => Opcode::ADDHNT_ZZZ_B, + 1677 => Opcode::ADDHNT_ZZZ_H, + 1678 => Opcode::ADDHNT_ZZZ_S, + 1679 => Opcode::ADDHNv2i64_v2i32, + 1680 => Opcode::ADDHNv2i64_v4i32, + 1681 => Opcode::ADDHNv4i32_v4i16, + 1682 => Opcode::ADDHNv4i32_v8i16, + 1683 => Opcode::ADDHNv8i16_v16i8, + 1684 => Opcode::ADDHNv8i16_v8i8, + 1685 => Opcode::ADDPL_XXI, + 1686 => Opcode::ADDPT_shift, + 1687 => Opcode::ADDP_ZPmZ_B, + 1688 => Opcode::ADDP_ZPmZ_D, + 1689 => Opcode::ADDP_ZPmZ_H, + 1690 => Opcode::ADDP_ZPmZ_S, + 1691 => Opcode::ADDPv16i8, + 1692 => Opcode::ADDPv2i32, + 1693 => Opcode::ADDPv2i64, + 1694 => Opcode::ADDPv2i64p, + 1695 => Opcode::ADDPv4i16, + 1696 => Opcode::ADDPv4i32, + 1697 => Opcode::ADDPv8i16, + 1698 => Opcode::ADDPv8i8, + 1699 => Opcode::ADDQP_ZZZ_B, + 1700 => Opcode::ADDQP_ZZZ_D, + 1701 => Opcode::ADDQP_ZZZ_H, + 1702 => Opcode::ADDQP_ZZZ_S, + 1703 => Opcode::ADDQV_VPZ_B, + 1704 => Opcode::ADDQV_VPZ_D, + 1705 => Opcode::ADDQV_VPZ_H, + 1706 => Opcode::ADDQV_VPZ_S, + 1707 => Opcode::ADDSPL_XXI, + 1708 => Opcode::ADDSUBP_ZZZ_B, + 1709 => Opcode::ADDSUBP_ZZZ_D, + 1710 => Opcode::ADDSUBP_ZZZ_H, + 1711 => Opcode::ADDSUBP_ZZZ_S, + 1712 => Opcode::ADDSVL_XXI, + 1713 => Opcode::ADDSWri, + 1714 => Opcode::ADDSWrs, + 1715 => Opcode::ADDSWrx, + 1716 => Opcode::ADDSXri, + 1717 => Opcode::ADDSXrs, + 1718 => Opcode::ADDSXrx, + 1719 => Opcode::ADDSXrx64, + 1720 => Opcode::ADDVA_MPPZ_D, + 1721 => Opcode::ADDVA_MPPZ_S, + 1722 => Opcode::ADDVL_XXI, + 1723 => Opcode::ADDVv16i8v, + 1724 => Opcode::ADDVv4i16v, + 1725 => Opcode::ADDVv4i32v, + 1726 => Opcode::ADDVv8i16v, + 1727 => Opcode::ADDVv8i8v, + 1728 => Opcode::ADDWri, + 1729 => Opcode::ADDWrs, + 1730 => Opcode::ADDWrx, + 1731 => Opcode::ADDXri, + 1732 => Opcode::ADDXrs, + 1733 => Opcode::ADDXrx, + 1734 => Opcode::ADDXrx64, + 1735 => Opcode::ADD_VG2_2ZZ_B, + 1736 => Opcode::ADD_VG2_2ZZ_D, + 1737 => Opcode::ADD_VG2_2ZZ_H, + 1738 => Opcode::ADD_VG2_2ZZ_S, + 1739 => Opcode::ADD_VG2_M2Z2Z_D, + 1740 => Opcode::ADD_VG2_M2Z2Z_S, + 1741 => Opcode::ADD_VG2_M2ZZ_D, + 1742 => Opcode::ADD_VG2_M2ZZ_S, + 1743 => Opcode::ADD_VG2_M2Z_D, + 1744 => Opcode::ADD_VG2_M2Z_S, + 1745 => Opcode::ADD_VG4_4ZZ_B, + 1746 => Opcode::ADD_VG4_4ZZ_D, + 1747 => Opcode::ADD_VG4_4ZZ_H, + 1748 => Opcode::ADD_VG4_4ZZ_S, + 1749 => Opcode::ADD_VG4_M4Z4Z_D, + 1750 => Opcode::ADD_VG4_M4Z4Z_S, + 1751 => Opcode::ADD_VG4_M4ZZ_D, + 1752 => Opcode::ADD_VG4_M4ZZ_S, + 1753 => Opcode::ADD_VG4_M4Z_D, + 1754 => Opcode::ADD_VG4_M4Z_S, + 1755 => Opcode::ADD_ZI_B, + 1756 => Opcode::ADD_ZI_D, + 1757 => Opcode::ADD_ZI_H, + 1758 => Opcode::ADD_ZI_S, + 1759 => Opcode::ADD_ZPmZ_B, + 1760 => Opcode::ADD_ZPmZ_CPA, + 1761 => Opcode::ADD_ZPmZ_D, + 1762 => Opcode::ADD_ZPmZ_H, + 1763 => Opcode::ADD_ZPmZ_S, + 1764 => Opcode::ADD_ZZZ_B, + 1765 => Opcode::ADD_ZZZ_CPA, + 1766 => Opcode::ADD_ZZZ_D, + 1767 => Opcode::ADD_ZZZ_H, + 1768 => Opcode::ADD_ZZZ_S, + 1769 => Opcode::ADDv16i8, + 1770 => Opcode::ADDv1i64, + 1771 => Opcode::ADDv2i32, + 1772 => Opcode::ADDv2i64, + 1773 => Opcode::ADDv4i16, + 1774 => Opcode::ADDv4i32, + 1775 => Opcode::ADDv8i16, + 1776 => Opcode::ADDv8i8, + 1777 => Opcode::ADR, + 1778 => Opcode::ADRP, + 1779 => Opcode::ADR_LSL_ZZZ_D_0, + 1780 => Opcode::ADR_LSL_ZZZ_D_1, + 1781 => Opcode::ADR_LSL_ZZZ_D_2, + 1782 => Opcode::ADR_LSL_ZZZ_D_3, + 1783 => Opcode::ADR_LSL_ZZZ_S_0, + 1784 => Opcode::ADR_LSL_ZZZ_S_1, + 1785 => Opcode::ADR_LSL_ZZZ_S_2, + 1786 => Opcode::ADR_LSL_ZZZ_S_3, + 1787 => Opcode::ADR_SXTW_ZZZ_D_0, + 1788 => Opcode::ADR_SXTW_ZZZ_D_1, + 1789 => Opcode::ADR_SXTW_ZZZ_D_2, + 1790 => Opcode::ADR_SXTW_ZZZ_D_3, + 1791 => Opcode::ADR_UXTW_ZZZ_D_0, + 1792 => Opcode::ADR_UXTW_ZZZ_D_1, + 1793 => Opcode::ADR_UXTW_ZZZ_D_2, + 1794 => Opcode::ADR_UXTW_ZZZ_D_3, + 1795 => Opcode::AESDIMC_2ZZI_B, + 1796 => Opcode::AESDIMC_4ZZI_B, + 1797 => Opcode::AESD_2ZZI_B, + 1798 => Opcode::AESD_4ZZI_B, + 1799 => Opcode::AESD_ZZZ_B, + 1800 => Opcode::AESDrr, + 1801 => Opcode::AESEMC_2ZZI_B, + 1802 => Opcode::AESEMC_4ZZI_B, + 1803 => Opcode::AESE_2ZZI_B, + 1804 => Opcode::AESE_4ZZI_B, + 1805 => Opcode::AESE_ZZZ_B, + 1806 => Opcode::AESErr, + 1807 => Opcode::AESIMC_ZZ_B, + 1808 => Opcode::AESIMCrr, + 1809 => Opcode::AESMC_ZZ_B, + 1810 => Opcode::AESMCrr, + 1811 => Opcode::ANDQV_VPZ_B, + 1812 => Opcode::ANDQV_VPZ_D, + 1813 => Opcode::ANDQV_VPZ_H, + 1814 => Opcode::ANDQV_VPZ_S, + 1815 => Opcode::ANDSWri, + 1816 => Opcode::ANDSWrs, + 1817 => Opcode::ANDSXri, + 1818 => Opcode::ANDSXrs, + 1819 => Opcode::ANDS_PPzPP, + 1820 => Opcode::ANDV_VPZ_B, + 1821 => Opcode::ANDV_VPZ_D, + 1822 => Opcode::ANDV_VPZ_H, + 1823 => Opcode::ANDV_VPZ_S, + 1824 => Opcode::ANDWri, + 1825 => Opcode::ANDWrs, + 1826 => Opcode::ANDXri, + 1827 => Opcode::ANDXrs, + 1828 => Opcode::AND_PPzPP, + 1829 => Opcode::AND_ZI, + 1830 => Opcode::AND_ZPmZ_B, + 1831 => Opcode::AND_ZPmZ_D, + 1832 => Opcode::AND_ZPmZ_H, + 1833 => Opcode::AND_ZPmZ_S, + 1834 => Opcode::AND_ZZZ, + 1835 => Opcode::ANDv16i8, + 1836 => Opcode::ANDv8i8, + 1837 => Opcode::APAS, + 1838 => Opcode::ASRD_ZPmI_B, + 1839 => Opcode::ASRD_ZPmI_D, + 1840 => Opcode::ASRD_ZPmI_H, + 1841 => Opcode::ASRD_ZPmI_S, + 1842 => Opcode::ASRR_ZPmZ_B, + 1843 => Opcode::ASRR_ZPmZ_D, + 1844 => Opcode::ASRR_ZPmZ_H, + 1845 => Opcode::ASRR_ZPmZ_S, + 1846 => Opcode::ASRVWr, + 1847 => Opcode::ASRVXr, + 1848 => Opcode::ASR_WIDE_ZPmZ_B, + 1849 => Opcode::ASR_WIDE_ZPmZ_H, + 1850 => Opcode::ASR_WIDE_ZPmZ_S, + 1851 => Opcode::ASR_WIDE_ZZZ_B, + 1852 => Opcode::ASR_WIDE_ZZZ_H, + 1853 => Opcode::ASR_WIDE_ZZZ_S, + 1854 => Opcode::ASR_ZPmI_B, + 1855 => Opcode::ASR_ZPmI_D, + 1856 => Opcode::ASR_ZPmI_H, + 1857 => Opcode::ASR_ZPmI_S, + 1858 => Opcode::ASR_ZPmZ_B, + 1859 => Opcode::ASR_ZPmZ_D, + 1860 => Opcode::ASR_ZPmZ_H, + 1861 => Opcode::ASR_ZPmZ_S, + 1862 => Opcode::ASR_ZZI_B, + 1863 => Opcode::ASR_ZZI_D, + 1864 => Opcode::ASR_ZZI_H, + 1865 => Opcode::ASR_ZZI_S, + 1866 => Opcode::AUTDA, + 1867 => Opcode::AUTDB, + 1868 => Opcode::AUTDZA, + 1869 => Opcode::AUTDZB, + 1870 => Opcode::AUTIA, + 1871 => Opcode::AUTIA1716, + 1872 => Opcode::AUTIA171615, + 1873 => Opcode::AUTIASP, + 1874 => Opcode::AUTIASPPCi, + 1875 => Opcode::AUTIASPPCr, + 1876 => Opcode::AUTIAZ, + 1877 => Opcode::AUTIB, + 1878 => Opcode::AUTIB1716, + 1879 => Opcode::AUTIB171615, + 1880 => Opcode::AUTIBSP, + 1881 => Opcode::AUTIBSPPCi, + 1882 => Opcode::AUTIBSPPCr, + 1883 => Opcode::AUTIBZ, + 1884 => Opcode::AUTIZA, + 1885 => Opcode::AUTIZB, + 1886 => Opcode::AXFLAG, + 1887 => Opcode::B, + 1888 => Opcode::BCAX, + 1889 => Opcode::BCAX_ZZZZ, + 1890 => Opcode::BCcc, + 1891 => Opcode::BDEP_ZZZ_B, + 1892 => Opcode::BDEP_ZZZ_D, + 1893 => Opcode::BDEP_ZZZ_H, + 1894 => Opcode::BDEP_ZZZ_S, + 1895 => Opcode::BEXT_ZZZ_B, + 1896 => Opcode::BEXT_ZZZ_D, + 1897 => Opcode::BEXT_ZZZ_H, + 1898 => Opcode::BEXT_ZZZ_S, + 1899 => Opcode::BF16DOTlanev4bf16, + 1900 => Opcode::BF16DOTlanev8bf16, + 1901 => Opcode::BF1CVTL, + 1902 => Opcode::BF1CVTL2, + 1903 => Opcode::BF1CVTLT_ZZ_BtoH, + 1904 => Opcode::BF1CVTL_2ZZ_BtoH, + 1905 => Opcode::BF1CVT_2ZZ_BtoH, + 1906 => Opcode::BF1CVT_ZZ_BtoH, + 1907 => Opcode::BF2CVTL, + 1908 => Opcode::BF2CVTL2, + 1909 => Opcode::BF2CVTLT_ZZ_BtoH, + 1910 => Opcode::BF2CVTL_2ZZ_BtoH, + 1911 => Opcode::BF2CVT_2ZZ_BtoH, + 1912 => Opcode::BF2CVT_ZZ_BtoH, + 1913 => Opcode::BFADD_VG2_M2Z_H, + 1914 => Opcode::BFADD_VG4_M4Z_H, + 1915 => Opcode::BFADD_ZPmZZ, + 1916 => Opcode::BFADD_ZZZ, + 1917 => Opcode::BFCLAMP_VG2_2ZZZ_H, + 1918 => Opcode::BFCLAMP_VG4_4ZZZ_H, + 1919 => Opcode::BFCLAMP_ZZZ, + 1920 => Opcode::BFCVT, + 1921 => Opcode::BFCVTN, + 1922 => Opcode::BFCVTN2, + 1923 => Opcode::BFCVTNT_ZPmZ, + 1924 => Opcode::BFCVTNT_ZPzZ_StoH, + 1925 => Opcode::BFCVTN_Z2Z_HtoB, + 1926 => Opcode::BFCVTN_Z2Z_StoH, + 1927 => Opcode::BFCVT_Z2Z_HtoB, + 1928 => Opcode::BFCVT_Z2Z_StoH, + 1929 => Opcode::BFCVT_ZPmZ, + 1930 => Opcode::BFCVT_ZPzZ_StoH, + 1931 => Opcode::BFDOT_VG2_M2Z2Z_HtoS, + 1932 => Opcode::BFDOT_VG2_M2ZZI_HtoS, + 1933 => Opcode::BFDOT_VG2_M2ZZ_HtoS, + 1934 => Opcode::BFDOT_VG4_M4Z4Z_HtoS, + 1935 => Opcode::BFDOT_VG4_M4ZZI_HtoS, + 1936 => Opcode::BFDOT_VG4_M4ZZ_HtoS, + 1937 => Opcode::BFDOT_ZZI, + 1938 => Opcode::BFDOT_ZZZ, + 1939 => Opcode::BFDOTv4bf16, + 1940 => Opcode::BFDOTv8bf16, + 1941 => Opcode::BFMAXNM_VG2_2Z2Z_H, + 1942 => Opcode::BFMAXNM_VG2_2ZZ_H, + 1943 => Opcode::BFMAXNM_VG4_4Z2Z_H, + 1944 => Opcode::BFMAXNM_VG4_4ZZ_H, + 1945 => Opcode::BFMAXNM_ZPmZZ, + 1946 => Opcode::BFMAX_VG2_2Z2Z_H, + 1947 => Opcode::BFMAX_VG2_2ZZ_H, + 1948 => Opcode::BFMAX_VG4_4Z2Z_H, + 1949 => Opcode::BFMAX_VG4_4ZZ_H, + 1950 => Opcode::BFMAX_ZPmZZ, + 1951 => Opcode::BFMINNM_VG2_2Z2Z_H, + 1952 => Opcode::BFMINNM_VG2_2ZZ_H, + 1953 => Opcode::BFMINNM_VG4_4Z2Z_H, + 1954 => Opcode::BFMINNM_VG4_4ZZ_H, + 1955 => Opcode::BFMINNM_ZPmZZ, + 1956 => Opcode::BFMIN_VG2_2Z2Z_H, + 1957 => Opcode::BFMIN_VG2_2ZZ_H, + 1958 => Opcode::BFMIN_VG4_4Z2Z_H, + 1959 => Opcode::BFMIN_VG4_4ZZ_H, + 1960 => Opcode::BFMIN_ZPmZZ, + 1961 => Opcode::BFMLALB, + 1962 => Opcode::BFMLALBIdx, + 1963 => Opcode::BFMLALB_ZZZ, + 1964 => Opcode::BFMLALB_ZZZI, + 1965 => Opcode::BFMLALT, + 1966 => Opcode::BFMLALTIdx, + 1967 => Opcode::BFMLALT_ZZZ, + 1968 => Opcode::BFMLALT_ZZZI, + 1969 => Opcode::BFMLAL_MZZI_HtoS, + 1970 => Opcode::BFMLAL_MZZ_HtoS, + 1971 => Opcode::BFMLAL_VG2_M2Z2Z_HtoS, + 1972 => Opcode::BFMLAL_VG2_M2ZZI_HtoS, + 1973 => Opcode::BFMLAL_VG2_M2ZZ_HtoS, + 1974 => Opcode::BFMLAL_VG4_M4Z4Z_HtoS, + 1975 => Opcode::BFMLAL_VG4_M4ZZI_HtoS, + 1976 => Opcode::BFMLAL_VG4_M4ZZ_HtoS, + 1977 => Opcode::BFMLA_VG2_M2Z2Z, + 1978 => Opcode::BFMLA_VG2_M2ZZ, + 1979 => Opcode::BFMLA_VG2_M2ZZI, + 1980 => Opcode::BFMLA_VG4_M4Z4Z, + 1981 => Opcode::BFMLA_VG4_M4ZZ, + 1982 => Opcode::BFMLA_VG4_M4ZZI, + 1983 => Opcode::BFMLA_ZPmZZ, + 1984 => Opcode::BFMLA_ZZZI, + 1985 => Opcode::BFMLSLB_ZZZI_S, + 1986 => Opcode::BFMLSLB_ZZZ_S, + 1987 => Opcode::BFMLSLT_ZZZI_S, + 1988 => Opcode::BFMLSLT_ZZZ_S, + 1989 => Opcode::BFMLSL_MZZI_HtoS, + 1990 => Opcode::BFMLSL_MZZ_HtoS, + 1991 => Opcode::BFMLSL_VG2_M2Z2Z_HtoS, + 1992 => Opcode::BFMLSL_VG2_M2ZZI_HtoS, + 1993 => Opcode::BFMLSL_VG2_M2ZZ_HtoS, + 1994 => Opcode::BFMLSL_VG4_M4Z4Z_HtoS, + 1995 => Opcode::BFMLSL_VG4_M4ZZI_HtoS, + 1996 => Opcode::BFMLSL_VG4_M4ZZ_HtoS, + 1997 => Opcode::BFMLS_VG2_M2Z2Z, + 1998 => Opcode::BFMLS_VG2_M2ZZ, + 1999 => Opcode::BFMLS_VG2_M2ZZI, + 2000 => Opcode::BFMLS_VG4_M4Z4Z, + 2001 => Opcode::BFMLS_VG4_M4ZZ, + 2002 => Opcode::BFMLS_VG4_M4ZZI, + 2003 => Opcode::BFMLS_ZPmZZ, + 2004 => Opcode::BFMLS_ZZZI, + 2005 => Opcode::BFMMLA, + 2006 => Opcode::BFMMLA_ZZZ_H, + 2007 => Opcode::BFMMLA_ZZZ_HtoS, + 2008 => Opcode::BFMOP4A_M2Z2Z_H, + 2009 => Opcode::BFMOP4A_M2Z2Z_S, + 2010 => Opcode::BFMOP4A_M2ZZ_H, + 2011 => Opcode::BFMOP4A_M2ZZ_S, + 2012 => Opcode::BFMOP4A_MZ2Z_H, + 2013 => Opcode::BFMOP4A_MZ2Z_S, + 2014 => Opcode::BFMOP4A_MZZ_H, + 2015 => Opcode::BFMOP4A_MZZ_S, + 2016 => Opcode::BFMOP4S_M2Z2Z_H, + 2017 => Opcode::BFMOP4S_M2Z2Z_S, + 2018 => Opcode::BFMOP4S_M2ZZ_H, + 2019 => Opcode::BFMOP4S_M2ZZ_S, + 2020 => Opcode::BFMOP4S_MZ2Z_H, + 2021 => Opcode::BFMOP4S_MZ2Z_S, + 2022 => Opcode::BFMOP4S_MZZ_H, + 2023 => Opcode::BFMOP4S_MZZ_S, + 2024 => Opcode::BFMOPA_MPPZZ, + 2025 => Opcode::BFMOPA_MPPZZ_H, + 2026 => Opcode::BFMOPS_MPPZZ, + 2027 => Opcode::BFMOPS_MPPZZ_H, + 2028 => Opcode::BFMUL_2Z2Z, + 2029 => Opcode::BFMUL_2ZZ, + 2030 => Opcode::BFMUL_4Z4Z, + 2031 => Opcode::BFMUL_4ZZ, + 2032 => Opcode::BFMUL_ZPmZZ, + 2033 => Opcode::BFMUL_ZZZ, + 2034 => Opcode::BFMUL_ZZZI, + 2035 => Opcode::BFMWri, + 2036 => Opcode::BFMXri, + 2037 => Opcode::BFSCALE_2Z2Z, + 2038 => Opcode::BFSCALE_2ZZ, + 2039 => Opcode::BFSCALE_4Z4Z, + 2040 => Opcode::BFSCALE_4ZZ, + 2041 => Opcode::BFSCALE_ZPZZ_H, + 2042 => Opcode::BFSUB_VG2_M2Z_H, + 2043 => Opcode::BFSUB_VG4_M4Z_H, + 2044 => Opcode::BFSUB_ZPmZZ, + 2045 => Opcode::BFSUB_ZZZ, + 2046 => Opcode::BFTMOPA_M2ZZZI_HtoH, + 2047 => Opcode::BFTMOPA_M2ZZZI_HtoS, + 2048 => Opcode::BFVDOT_VG2_M2ZZI_HtoS, + 2049 => Opcode::BGRP_ZZZ_B, + 2050 => Opcode::BGRP_ZZZ_D, + 2051 => Opcode::BGRP_ZZZ_H, + 2052 => Opcode::BGRP_ZZZ_S, + 2053 => Opcode::BICSWrs, + 2054 => Opcode::BICSXrs, + 2055 => Opcode::BICS_PPzPP, + 2056 => Opcode::BICWrs, + 2057 => Opcode::BICXrs, + 2058 => Opcode::BIC_PPzPP, + 2059 => Opcode::BIC_ZPmZ_B, + 2060 => Opcode::BIC_ZPmZ_D, + 2061 => Opcode::BIC_ZPmZ_H, + 2062 => Opcode::BIC_ZPmZ_S, + 2063 => Opcode::BIC_ZZZ, + 2064 => Opcode::BICv16i8, + 2065 => Opcode::BICv2i32, + 2066 => Opcode::BICv4i16, + 2067 => Opcode::BICv4i32, + 2068 => Opcode::BICv8i16, + 2069 => Opcode::BICv8i8, + 2070 => Opcode::BIFv16i8, + 2071 => Opcode::BIFv8i8, + 2072 => Opcode::BITv16i8, + 2073 => Opcode::BITv8i8, + 2074 => Opcode::BL, + 2075 => Opcode::BLR, + 2076 => Opcode::BLRAA, + 2077 => Opcode::BLRAAZ, + 2078 => Opcode::BLRAB, + 2079 => Opcode::BLRABZ, + 2080 => Opcode::BMOPA_MPPZZ_S, + 2081 => Opcode::BMOPS_MPPZZ_S, + 2082 => Opcode::BR, + 2083 => Opcode::BRAA, + 2084 => Opcode::BRAAZ, + 2085 => Opcode::BRAB, + 2086 => Opcode::BRABZ, + 2087 => Opcode::BRB_IALL, + 2088 => Opcode::BRB_INJ, + 2089 => Opcode::BRK, + 2090 => Opcode::BRKAS_PPzP, + 2091 => Opcode::BRKA_PPmP, + 2092 => Opcode::BRKA_PPzP, + 2093 => Opcode::BRKBS_PPzP, + 2094 => Opcode::BRKB_PPmP, + 2095 => Opcode::BRKB_PPzP, + 2096 => Opcode::BRKNS_PPzP, + 2097 => Opcode::BRKN_PPzP, + 2098 => Opcode::BRKPAS_PPzPP, + 2099 => Opcode::BRKPA_PPzPP, + 2100 => Opcode::BRKPBS_PPzPP, + 2101 => Opcode::BRKPB_PPzPP, + 2102 => Opcode::BSL1N_ZZZZ, + 2103 => Opcode::BSL2N_ZZZZ, + 2104 => Opcode::BSL_ZZZZ, + 2105 => Opcode::BSLv16i8, + 2106 => Opcode::BSLv8i8, + 2107 => Opcode::Bcc, + 2108 => Opcode::CADD_ZZI_B, + 2109 => Opcode::CADD_ZZI_D, + 2110 => Opcode::CADD_ZZI_H, + 2111 => Opcode::CADD_ZZI_S, + 2112 => Opcode::CASAB, + 2113 => Opcode::CASAH, + 2114 => Opcode::CASALB, + 2115 => Opcode::CASALH, + 2116 => Opcode::CASALTX, + 2117 => Opcode::CASALW, + 2118 => Opcode::CASALX, + 2119 => Opcode::CASATX, + 2120 => Opcode::CASAW, + 2121 => Opcode::CASAX, + 2122 => Opcode::CASB, + 2123 => Opcode::CASH, + 2124 => Opcode::CASLB, + 2125 => Opcode::CASLH, + 2126 => Opcode::CASLTX, + 2127 => Opcode::CASLW, + 2128 => Opcode::CASLX, + 2129 => Opcode::CASPALTX, + 2130 => Opcode::CASPALW, + 2131 => Opcode::CASPALX, + 2132 => Opcode::CASPATX, + 2133 => Opcode::CASPAW, + 2134 => Opcode::CASPAX, + 2135 => Opcode::CASPLTX, + 2136 => Opcode::CASPLW, + 2137 => Opcode::CASPLX, + 2138 => Opcode::CASPTX, + 2139 => Opcode::CASPW, + 2140 => Opcode::CASPX, + 2141 => Opcode::CASTX, + 2142 => Opcode::CASW, + 2143 => Opcode::CASX, + 2144 => Opcode::CBBEQWrr, + 2145 => Opcode::CBBGEWrr, + 2146 => Opcode::CBBGTWrr, + 2147 => Opcode::CBBHIWrr, + 2148 => Opcode::CBBHSWrr, + 2149 => Opcode::CBBNEWrr, + 2150 => Opcode::CBEQWri, + 2151 => Opcode::CBEQWrr, + 2152 => Opcode::CBEQXri, + 2153 => Opcode::CBEQXrr, + 2154 => Opcode::CBGEWrr, + 2155 => Opcode::CBGEXrr, + 2156 => Opcode::CBGTWri, + 2157 => Opcode::CBGTWrr, + 2158 => Opcode::CBGTXri, + 2159 => Opcode::CBGTXrr, + 2160 => Opcode::CBHEQWrr, + 2161 => Opcode::CBHGEWrr, + 2162 => Opcode::CBHGTWrr, + 2163 => Opcode::CBHHIWrr, + 2164 => Opcode::CBHHSWrr, + 2165 => Opcode::CBHIWri, + 2166 => Opcode::CBHIWrr, + 2167 => Opcode::CBHIXri, + 2168 => Opcode::CBHIXrr, + 2169 => Opcode::CBHNEWrr, + 2170 => Opcode::CBHSWrr, + 2171 => Opcode::CBHSXrr, + 2172 => Opcode::CBLOWri, + 2173 => Opcode::CBLOXri, + 2174 => Opcode::CBLTWri, + 2175 => Opcode::CBLTXri, + 2176 => Opcode::CBNEWri, + 2177 => Opcode::CBNEWrr, + 2178 => Opcode::CBNEXri, + 2179 => Opcode::CBNEXrr, + 2180 => Opcode::CBNZW, + 2181 => Opcode::CBNZX, + 2182 => Opcode::CBZW, + 2183 => Opcode::CBZX, + 2184 => Opcode::CCMNWi, + 2185 => Opcode::CCMNWr, + 2186 => Opcode::CCMNXi, + 2187 => Opcode::CCMNXr, + 2188 => Opcode::CCMPWi, + 2189 => Opcode::CCMPWr, + 2190 => Opcode::CCMPXi, + 2191 => Opcode::CCMPXr, + 2192 => Opcode::CDOT_ZZZI_D, + 2193 => Opcode::CDOT_ZZZI_S, + 2194 => Opcode::CDOT_ZZZ_D, + 2195 => Opcode::CDOT_ZZZ_S, + 2196 => Opcode::CFINV, + 2197 => Opcode::CHKFEAT, + 2198 => Opcode::CLASTA_RPZ_B, + 2199 => Opcode::CLASTA_RPZ_D, + 2200 => Opcode::CLASTA_RPZ_H, + 2201 => Opcode::CLASTA_RPZ_S, + 2202 => Opcode::CLASTA_VPZ_B, + 2203 => Opcode::CLASTA_VPZ_D, + 2204 => Opcode::CLASTA_VPZ_H, + 2205 => Opcode::CLASTA_VPZ_S, + 2206 => Opcode::CLASTA_ZPZ_B, + 2207 => Opcode::CLASTA_ZPZ_D, + 2208 => Opcode::CLASTA_ZPZ_H, + 2209 => Opcode::CLASTA_ZPZ_S, + 2210 => Opcode::CLASTB_RPZ_B, + 2211 => Opcode::CLASTB_RPZ_D, + 2212 => Opcode::CLASTB_RPZ_H, + 2213 => Opcode::CLASTB_RPZ_S, + 2214 => Opcode::CLASTB_VPZ_B, + 2215 => Opcode::CLASTB_VPZ_D, + 2216 => Opcode::CLASTB_VPZ_H, + 2217 => Opcode::CLASTB_VPZ_S, + 2218 => Opcode::CLASTB_ZPZ_B, + 2219 => Opcode::CLASTB_ZPZ_D, + 2220 => Opcode::CLASTB_ZPZ_H, + 2221 => Opcode::CLASTB_ZPZ_S, + 2222 => Opcode::CLREX, + 2223 => Opcode::CLSWr, + 2224 => Opcode::CLSXr, + 2225 => Opcode::CLS_ZPmZ_B, + 2226 => Opcode::CLS_ZPmZ_D, + 2227 => Opcode::CLS_ZPmZ_H, + 2228 => Opcode::CLS_ZPmZ_S, + 2229 => Opcode::CLS_ZPzZ_B, + 2230 => Opcode::CLS_ZPzZ_D, + 2231 => Opcode::CLS_ZPzZ_H, + 2232 => Opcode::CLS_ZPzZ_S, + 2233 => Opcode::CLSv16i8, + 2234 => Opcode::CLSv2i32, + 2235 => Opcode::CLSv4i16, + 2236 => Opcode::CLSv4i32, + 2237 => Opcode::CLSv8i16, + 2238 => Opcode::CLSv8i8, + 2239 => Opcode::CLZWr, + 2240 => Opcode::CLZXr, + 2241 => Opcode::CLZ_ZPmZ_B, + 2242 => Opcode::CLZ_ZPmZ_D, + 2243 => Opcode::CLZ_ZPmZ_H, + 2244 => Opcode::CLZ_ZPmZ_S, + 2245 => Opcode::CLZ_ZPzZ_B, + 2246 => Opcode::CLZ_ZPzZ_D, + 2247 => Opcode::CLZ_ZPzZ_H, + 2248 => Opcode::CLZ_ZPzZ_S, + 2249 => Opcode::CLZv16i8, + 2250 => Opcode::CLZv2i32, + 2251 => Opcode::CLZv4i16, + 2252 => Opcode::CLZv4i32, + 2253 => Opcode::CLZv8i16, + 2254 => Opcode::CLZv8i8, + 2255 => Opcode::CMEQv16i8, + 2256 => Opcode::CMEQv16i8rz, + 2257 => Opcode::CMEQv1i64, + 2258 => Opcode::CMEQv1i64rz, + 2259 => Opcode::CMEQv2i32, + 2260 => Opcode::CMEQv2i32rz, + 2261 => Opcode::CMEQv2i64, + 2262 => Opcode::CMEQv2i64rz, + 2263 => Opcode::CMEQv4i16, + 2264 => Opcode::CMEQv4i16rz, + 2265 => Opcode::CMEQv4i32, + 2266 => Opcode::CMEQv4i32rz, + 2267 => Opcode::CMEQv8i16, + 2268 => Opcode::CMEQv8i16rz, + 2269 => Opcode::CMEQv8i8, + 2270 => Opcode::CMEQv8i8rz, + 2271 => Opcode::CMGEv16i8, + 2272 => Opcode::CMGEv16i8rz, + 2273 => Opcode::CMGEv1i64, + 2274 => Opcode::CMGEv1i64rz, + 2275 => Opcode::CMGEv2i32, + 2276 => Opcode::CMGEv2i32rz, + 2277 => Opcode::CMGEv2i64, + 2278 => Opcode::CMGEv2i64rz, + 2279 => Opcode::CMGEv4i16, + 2280 => Opcode::CMGEv4i16rz, + 2281 => Opcode::CMGEv4i32, + 2282 => Opcode::CMGEv4i32rz, + 2283 => Opcode::CMGEv8i16, + 2284 => Opcode::CMGEv8i16rz, + 2285 => Opcode::CMGEv8i8, + 2286 => Opcode::CMGEv8i8rz, + 2287 => Opcode::CMGTv16i8, + 2288 => Opcode::CMGTv16i8rz, + 2289 => Opcode::CMGTv1i64, + 2290 => Opcode::CMGTv1i64rz, + 2291 => Opcode::CMGTv2i32, + 2292 => Opcode::CMGTv2i32rz, + 2293 => Opcode::CMGTv2i64, + 2294 => Opcode::CMGTv2i64rz, + 2295 => Opcode::CMGTv4i16, + 2296 => Opcode::CMGTv4i16rz, + 2297 => Opcode::CMGTv4i32, + 2298 => Opcode::CMGTv4i32rz, + 2299 => Opcode::CMGTv8i16, + 2300 => Opcode::CMGTv8i16rz, + 2301 => Opcode::CMGTv8i8, + 2302 => Opcode::CMGTv8i8rz, + 2303 => Opcode::CMHIv16i8, + 2304 => Opcode::CMHIv1i64, + 2305 => Opcode::CMHIv2i32, + 2306 => Opcode::CMHIv2i64, + 2307 => Opcode::CMHIv4i16, + 2308 => Opcode::CMHIv4i32, + 2309 => Opcode::CMHIv8i16, + 2310 => Opcode::CMHIv8i8, + 2311 => Opcode::CMHSv16i8, + 2312 => Opcode::CMHSv1i64, + 2313 => Opcode::CMHSv2i32, + 2314 => Opcode::CMHSv2i64, + 2315 => Opcode::CMHSv4i16, + 2316 => Opcode::CMHSv4i32, + 2317 => Opcode::CMHSv8i16, + 2318 => Opcode::CMHSv8i8, + 2319 => Opcode::CMLA_ZZZI_H, + 2320 => Opcode::CMLA_ZZZI_S, + 2321 => Opcode::CMLA_ZZZ_B, + 2322 => Opcode::CMLA_ZZZ_D, + 2323 => Opcode::CMLA_ZZZ_H, + 2324 => Opcode::CMLA_ZZZ_S, + 2325 => Opcode::CMLEv16i8rz, + 2326 => Opcode::CMLEv1i64rz, + 2327 => Opcode::CMLEv2i32rz, + 2328 => Opcode::CMLEv2i64rz, + 2329 => Opcode::CMLEv4i16rz, + 2330 => Opcode::CMLEv4i32rz, + 2331 => Opcode::CMLEv8i16rz, + 2332 => Opcode::CMLEv8i8rz, + 2333 => Opcode::CMLTv16i8rz, + 2334 => Opcode::CMLTv1i64rz, + 2335 => Opcode::CMLTv2i32rz, + 2336 => Opcode::CMLTv2i64rz, + 2337 => Opcode::CMLTv4i16rz, + 2338 => Opcode::CMLTv4i32rz, + 2339 => Opcode::CMLTv8i16rz, + 2340 => Opcode::CMLTv8i8rz, + 2341 => Opcode::CMPEQ_PPzZI_B, + 2342 => Opcode::CMPEQ_PPzZI_D, + 2343 => Opcode::CMPEQ_PPzZI_H, + 2344 => Opcode::CMPEQ_PPzZI_S, + 2345 => Opcode::CMPEQ_PPzZZ_B, + 2346 => Opcode::CMPEQ_PPzZZ_D, + 2347 => Opcode::CMPEQ_PPzZZ_H, + 2348 => Opcode::CMPEQ_PPzZZ_S, + 2349 => Opcode::CMPEQ_WIDE_PPzZZ_B, + 2350 => Opcode::CMPEQ_WIDE_PPzZZ_H, + 2351 => Opcode::CMPEQ_WIDE_PPzZZ_S, + 2352 => Opcode::CMPGE_PPzZI_B, + 2353 => Opcode::CMPGE_PPzZI_D, + 2354 => Opcode::CMPGE_PPzZI_H, + 2355 => Opcode::CMPGE_PPzZI_S, + 2356 => Opcode::CMPGE_PPzZZ_B, + 2357 => Opcode::CMPGE_PPzZZ_D, + 2358 => Opcode::CMPGE_PPzZZ_H, + 2359 => Opcode::CMPGE_PPzZZ_S, + 2360 => Opcode::CMPGE_WIDE_PPzZZ_B, + 2361 => Opcode::CMPGE_WIDE_PPzZZ_H, + 2362 => Opcode::CMPGE_WIDE_PPzZZ_S, + 2363 => Opcode::CMPGT_PPzZI_B, + 2364 => Opcode::CMPGT_PPzZI_D, + 2365 => Opcode::CMPGT_PPzZI_H, + 2366 => Opcode::CMPGT_PPzZI_S, + 2367 => Opcode::CMPGT_PPzZZ_B, + 2368 => Opcode::CMPGT_PPzZZ_D, + 2369 => Opcode::CMPGT_PPzZZ_H, + 2370 => Opcode::CMPGT_PPzZZ_S, + 2371 => Opcode::CMPGT_WIDE_PPzZZ_B, + 2372 => Opcode::CMPGT_WIDE_PPzZZ_H, + 2373 => Opcode::CMPGT_WIDE_PPzZZ_S, + 2374 => Opcode::CMPHI_PPzZI_B, + 2375 => Opcode::CMPHI_PPzZI_D, + 2376 => Opcode::CMPHI_PPzZI_H, + 2377 => Opcode::CMPHI_PPzZI_S, + 2378 => Opcode::CMPHI_PPzZZ_B, + 2379 => Opcode::CMPHI_PPzZZ_D, + 2380 => Opcode::CMPHI_PPzZZ_H, + 2381 => Opcode::CMPHI_PPzZZ_S, + 2382 => Opcode::CMPHI_WIDE_PPzZZ_B, + 2383 => Opcode::CMPHI_WIDE_PPzZZ_H, + 2384 => Opcode::CMPHI_WIDE_PPzZZ_S, + 2385 => Opcode::CMPHS_PPzZI_B, + 2386 => Opcode::CMPHS_PPzZI_D, + 2387 => Opcode::CMPHS_PPzZI_H, + 2388 => Opcode::CMPHS_PPzZI_S, + 2389 => Opcode::CMPHS_PPzZZ_B, + 2390 => Opcode::CMPHS_PPzZZ_D, + 2391 => Opcode::CMPHS_PPzZZ_H, + 2392 => Opcode::CMPHS_PPzZZ_S, + 2393 => Opcode::CMPHS_WIDE_PPzZZ_B, + 2394 => Opcode::CMPHS_WIDE_PPzZZ_H, + 2395 => Opcode::CMPHS_WIDE_PPzZZ_S, + 2396 => Opcode::CMPLE_PPzZI_B, + 2397 => Opcode::CMPLE_PPzZI_D, + 2398 => Opcode::CMPLE_PPzZI_H, + 2399 => Opcode::CMPLE_PPzZI_S, + 2400 => Opcode::CMPLE_WIDE_PPzZZ_B, + 2401 => Opcode::CMPLE_WIDE_PPzZZ_H, + 2402 => Opcode::CMPLE_WIDE_PPzZZ_S, + 2403 => Opcode::CMPLO_PPzZI_B, + 2404 => Opcode::CMPLO_PPzZI_D, + 2405 => Opcode::CMPLO_PPzZI_H, + 2406 => Opcode::CMPLO_PPzZI_S, + 2407 => Opcode::CMPLO_WIDE_PPzZZ_B, + 2408 => Opcode::CMPLO_WIDE_PPzZZ_H, + 2409 => Opcode::CMPLO_WIDE_PPzZZ_S, + 2410 => Opcode::CMPLS_PPzZI_B, + 2411 => Opcode::CMPLS_PPzZI_D, + 2412 => Opcode::CMPLS_PPzZI_H, + 2413 => Opcode::CMPLS_PPzZI_S, + 2414 => Opcode::CMPLS_WIDE_PPzZZ_B, + 2415 => Opcode::CMPLS_WIDE_PPzZZ_H, + 2416 => Opcode::CMPLS_WIDE_PPzZZ_S, + 2417 => Opcode::CMPLT_PPzZI_B, + 2418 => Opcode::CMPLT_PPzZI_D, + 2419 => Opcode::CMPLT_PPzZI_H, + 2420 => Opcode::CMPLT_PPzZI_S, + 2421 => Opcode::CMPLT_WIDE_PPzZZ_B, + 2422 => Opcode::CMPLT_WIDE_PPzZZ_H, + 2423 => Opcode::CMPLT_WIDE_PPzZZ_S, + 2424 => Opcode::CMPNE_PPzZI_B, + 2425 => Opcode::CMPNE_PPzZI_D, + 2426 => Opcode::CMPNE_PPzZI_H, + 2427 => Opcode::CMPNE_PPzZI_S, + 2428 => Opcode::CMPNE_PPzZZ_B, + 2429 => Opcode::CMPNE_PPzZZ_D, + 2430 => Opcode::CMPNE_PPzZZ_H, + 2431 => Opcode::CMPNE_PPzZZ_S, + 2432 => Opcode::CMPNE_WIDE_PPzZZ_B, + 2433 => Opcode::CMPNE_WIDE_PPzZZ_H, + 2434 => Opcode::CMPNE_WIDE_PPzZZ_S, + 2435 => Opcode::CMTSTv16i8, + 2436 => Opcode::CMTSTv1i64, + 2437 => Opcode::CMTSTv2i32, + 2438 => Opcode::CMTSTv2i64, + 2439 => Opcode::CMTSTv4i16, + 2440 => Opcode::CMTSTv4i32, + 2441 => Opcode::CMTSTv8i16, + 2442 => Opcode::CMTSTv8i8, + 2443 => Opcode::CNOT_ZPmZ_B, + 2444 => Opcode::CNOT_ZPmZ_D, + 2445 => Opcode::CNOT_ZPmZ_H, + 2446 => Opcode::CNOT_ZPmZ_S, + 2447 => Opcode::CNOT_ZPzZ_B, + 2448 => Opcode::CNOT_ZPzZ_D, + 2449 => Opcode::CNOT_ZPzZ_H, + 2450 => Opcode::CNOT_ZPzZ_S, + 2451 => Opcode::CNTB_XPiI, + 2452 => Opcode::CNTD_XPiI, + 2453 => Opcode::CNTH_XPiI, + 2454 => Opcode::CNTP_XCI_B, + 2455 => Opcode::CNTP_XCI_D, + 2456 => Opcode::CNTP_XCI_H, + 2457 => Opcode::CNTP_XCI_S, + 2458 => Opcode::CNTP_XPP_B, + 2459 => Opcode::CNTP_XPP_D, + 2460 => Opcode::CNTP_XPP_H, + 2461 => Opcode::CNTP_XPP_S, + 2462 => Opcode::CNTW_XPiI, + 2463 => Opcode::CNTWr, + 2464 => Opcode::CNTXr, + 2465 => Opcode::CNT_ZPmZ_B, + 2466 => Opcode::CNT_ZPmZ_D, + 2467 => Opcode::CNT_ZPmZ_H, + 2468 => Opcode::CNT_ZPmZ_S, + 2469 => Opcode::CNT_ZPzZ_B, + 2470 => Opcode::CNT_ZPzZ_D, + 2471 => Opcode::CNT_ZPzZ_H, + 2472 => Opcode::CNT_ZPzZ_S, + 2473 => Opcode::CNTv16i8, + 2474 => Opcode::CNTv8i8, + 2475 => Opcode::COMPACT_ZPZ_B, + 2476 => Opcode::COMPACT_ZPZ_D, + 2477 => Opcode::COMPACT_ZPZ_H, + 2478 => Opcode::COMPACT_ZPZ_S, + 2479 => Opcode::CPYE, + 2480 => Opcode::CPYEN, + 2481 => Opcode::CPYERN, + 2482 => Opcode::CPYERT, + 2483 => Opcode::CPYERTN, + 2484 => Opcode::CPYERTRN, + 2485 => Opcode::CPYERTWN, + 2486 => Opcode::CPYET, + 2487 => Opcode::CPYETN, + 2488 => Opcode::CPYETRN, + 2489 => Opcode::CPYETWN, + 2490 => Opcode::CPYEWN, + 2491 => Opcode::CPYEWT, + 2492 => Opcode::CPYEWTN, + 2493 => Opcode::CPYEWTRN, + 2494 => Opcode::CPYEWTWN, + 2495 => Opcode::CPYFE, + 2496 => Opcode::CPYFEN, + 2497 => Opcode::CPYFERN, + 2498 => Opcode::CPYFERT, + 2499 => Opcode::CPYFERTN, + 2500 => Opcode::CPYFERTRN, + 2501 => Opcode::CPYFERTWN, + 2502 => Opcode::CPYFET, + 2503 => Opcode::CPYFETN, + 2504 => Opcode::CPYFETRN, + 2505 => Opcode::CPYFETWN, + 2506 => Opcode::CPYFEWN, + 2507 => Opcode::CPYFEWT, + 2508 => Opcode::CPYFEWTN, + 2509 => Opcode::CPYFEWTRN, + 2510 => Opcode::CPYFEWTWN, + 2511 => Opcode::CPYFM, + 2512 => Opcode::CPYFMN, + 2513 => Opcode::CPYFMRN, + 2514 => Opcode::CPYFMRT, + 2515 => Opcode::CPYFMRTN, + 2516 => Opcode::CPYFMRTRN, + 2517 => Opcode::CPYFMRTWN, + 2518 => Opcode::CPYFMT, + 2519 => Opcode::CPYFMTN, + 2520 => Opcode::CPYFMTRN, + 2521 => Opcode::CPYFMTWN, + 2522 => Opcode::CPYFMWN, + 2523 => Opcode::CPYFMWT, + 2524 => Opcode::CPYFMWTN, + 2525 => Opcode::CPYFMWTRN, + 2526 => Opcode::CPYFMWTWN, + 2527 => Opcode::CPYFP, + 2528 => Opcode::CPYFPN, + 2529 => Opcode::CPYFPRN, + 2530 => Opcode::CPYFPRT, + 2531 => Opcode::CPYFPRTN, + 2532 => Opcode::CPYFPRTRN, + 2533 => Opcode::CPYFPRTWN, + 2534 => Opcode::CPYFPT, + 2535 => Opcode::CPYFPTN, + 2536 => Opcode::CPYFPTRN, + 2537 => Opcode::CPYFPTWN, + 2538 => Opcode::CPYFPWN, + 2539 => Opcode::CPYFPWT, + 2540 => Opcode::CPYFPWTN, + 2541 => Opcode::CPYFPWTRN, + 2542 => Opcode::CPYFPWTWN, + 2543 => Opcode::CPYM, + 2544 => Opcode::CPYMN, + 2545 => Opcode::CPYMRN, + 2546 => Opcode::CPYMRT, + 2547 => Opcode::CPYMRTN, + 2548 => Opcode::CPYMRTRN, + 2549 => Opcode::CPYMRTWN, + 2550 => Opcode::CPYMT, + 2551 => Opcode::CPYMTN, + 2552 => Opcode::CPYMTRN, + 2553 => Opcode::CPYMTWN, + 2554 => Opcode::CPYMWN, + 2555 => Opcode::CPYMWT, + 2556 => Opcode::CPYMWTN, + 2557 => Opcode::CPYMWTRN, + 2558 => Opcode::CPYMWTWN, + 2559 => Opcode::CPYP, + 2560 => Opcode::CPYPN, + 2561 => Opcode::CPYPRN, + 2562 => Opcode::CPYPRT, + 2563 => Opcode::CPYPRTN, + 2564 => Opcode::CPYPRTRN, + 2565 => Opcode::CPYPRTWN, + 2566 => Opcode::CPYPT, + 2567 => Opcode::CPYPTN, + 2568 => Opcode::CPYPTRN, + 2569 => Opcode::CPYPTWN, + 2570 => Opcode::CPYPWN, + 2571 => Opcode::CPYPWT, + 2572 => Opcode::CPYPWTN, + 2573 => Opcode::CPYPWTRN, + 2574 => Opcode::CPYPWTWN, + 2575 => Opcode::CPY_ZPmI_B, + 2576 => Opcode::CPY_ZPmI_D, + 2577 => Opcode::CPY_ZPmI_H, + 2578 => Opcode::CPY_ZPmI_S, + 2579 => Opcode::CPY_ZPmR_B, + 2580 => Opcode::CPY_ZPmR_D, + 2581 => Opcode::CPY_ZPmR_H, + 2582 => Opcode::CPY_ZPmR_S, + 2583 => Opcode::CPY_ZPmV_B, + 2584 => Opcode::CPY_ZPmV_D, + 2585 => Opcode::CPY_ZPmV_H, + 2586 => Opcode::CPY_ZPmV_S, + 2587 => Opcode::CPY_ZPzI_B, + 2588 => Opcode::CPY_ZPzI_D, + 2589 => Opcode::CPY_ZPzI_H, + 2590 => Opcode::CPY_ZPzI_S, + 2591 => Opcode::CRC32Brr, + 2592 => Opcode::CRC32CBrr, + 2593 => Opcode::CRC32CHrr, + 2594 => Opcode::CRC32CWrr, + 2595 => Opcode::CRC32CXrr, + 2596 => Opcode::CRC32Hrr, + 2597 => Opcode::CRC32Wrr, + 2598 => Opcode::CRC32Xrr, + 2599 => Opcode::CSELWr, + 2600 => Opcode::CSELXr, + 2601 => Opcode::CSINCWr, + 2602 => Opcode::CSINCXr, + 2603 => Opcode::CSINVWr, + 2604 => Opcode::CSINVXr, + 2605 => Opcode::CSNEGWr, + 2606 => Opcode::CSNEGXr, + 2607 => Opcode::CTERMEQ_WW, + 2608 => Opcode::CTERMEQ_XX, + 2609 => Opcode::CTERMNE_WW, + 2610 => Opcode::CTERMNE_XX, + 2611 => Opcode::CTZWr, + 2612 => Opcode::CTZXr, + 2613 => Opcode::DCPS1, + 2614 => Opcode::DCPS2, + 2615 => Opcode::DCPS3, + 2616 => Opcode::DECB_XPiI, + 2617 => Opcode::DECD_XPiI, + 2618 => Opcode::DECD_ZPiI, + 2619 => Opcode::DECH_XPiI, + 2620 => Opcode::DECH_ZPiI, + 2621 => Opcode::DECP_XP_B, + 2622 => Opcode::DECP_XP_D, + 2623 => Opcode::DECP_XP_H, + 2624 => Opcode::DECP_XP_S, + 2625 => Opcode::DECP_ZP_D, + 2626 => Opcode::DECP_ZP_H, + 2627 => Opcode::DECP_ZP_S, + 2628 => Opcode::DECW_XPiI, + 2629 => Opcode::DECW_ZPiI, + 2630 => Opcode::DMB, + 2631 => Opcode::DRPS, + 2632 => Opcode::DSB, + 2633 => Opcode::DSBnXS, + 2634 => Opcode::DUPM_ZI, + 2635 => Opcode::DUPQ_ZZI_B, + 2636 => Opcode::DUPQ_ZZI_D, + 2637 => Opcode::DUPQ_ZZI_H, + 2638 => Opcode::DUPQ_ZZI_S, + 2639 => Opcode::DUP_ZI_B, + 2640 => Opcode::DUP_ZI_D, + 2641 => Opcode::DUP_ZI_H, + 2642 => Opcode::DUP_ZI_S, + 2643 => Opcode::DUP_ZR_B, + 2644 => Opcode::DUP_ZR_D, + 2645 => Opcode::DUP_ZR_H, + 2646 => Opcode::DUP_ZR_S, + 2647 => Opcode::DUP_ZZI_B, + 2648 => Opcode::DUP_ZZI_D, + 2649 => Opcode::DUP_ZZI_H, + 2650 => Opcode::DUP_ZZI_Q, + 2651 => Opcode::DUP_ZZI_S, + 2652 => Opcode::DUPi16, + 2653 => Opcode::DUPi32, + 2654 => Opcode::DUPi64, + 2655 => Opcode::DUPi8, + 2656 => Opcode::DUPv16i8gpr, + 2657 => Opcode::DUPv16i8lane, + 2658 => Opcode::DUPv2i32gpr, + 2659 => Opcode::DUPv2i32lane, + 2660 => Opcode::DUPv2i64gpr, + 2661 => Opcode::DUPv2i64lane, + 2662 => Opcode::DUPv4i16gpr, + 2663 => Opcode::DUPv4i16lane, + 2664 => Opcode::DUPv4i32gpr, + 2665 => Opcode::DUPv4i32lane, + 2666 => Opcode::DUPv8i16gpr, + 2667 => Opcode::DUPv8i16lane, + 2668 => Opcode::DUPv8i8gpr, + 2669 => Opcode::DUPv8i8lane, + 2670 => Opcode::EONWrs, + 2671 => Opcode::EONXrs, + 2672 => Opcode::EOR3, + 2673 => Opcode::EOR3_ZZZZ, + 2674 => Opcode::EORBT_ZZZ_B, + 2675 => Opcode::EORBT_ZZZ_D, + 2676 => Opcode::EORBT_ZZZ_H, + 2677 => Opcode::EORBT_ZZZ_S, + 2678 => Opcode::EORQV_VPZ_B, + 2679 => Opcode::EORQV_VPZ_D, + 2680 => Opcode::EORQV_VPZ_H, + 2681 => Opcode::EORQV_VPZ_S, + 2682 => Opcode::EORS_PPzPP, + 2683 => Opcode::EORTB_ZZZ_B, + 2684 => Opcode::EORTB_ZZZ_D, + 2685 => Opcode::EORTB_ZZZ_H, + 2686 => Opcode::EORTB_ZZZ_S, + 2687 => Opcode::EORV_VPZ_B, + 2688 => Opcode::EORV_VPZ_D, + 2689 => Opcode::EORV_VPZ_H, + 2690 => Opcode::EORV_VPZ_S, + 2691 => Opcode::EORWri, + 2692 => Opcode::EORWrs, + 2693 => Opcode::EORXri, + 2694 => Opcode::EORXrs, + 2695 => Opcode::EOR_PPzPP, + 2696 => Opcode::EOR_ZI, + 2697 => Opcode::EOR_ZPmZ_B, + 2698 => Opcode::EOR_ZPmZ_D, + 2699 => Opcode::EOR_ZPmZ_H, + 2700 => Opcode::EOR_ZPmZ_S, + 2701 => Opcode::EOR_ZZZ, + 2702 => Opcode::EORv16i8, + 2703 => Opcode::EORv8i8, + 2704 => Opcode::ERET, + 2705 => Opcode::ERETAA, + 2706 => Opcode::ERETAB, + 2707 => Opcode::EXPAND_ZPZ_B, + 2708 => Opcode::EXPAND_ZPZ_D, + 2709 => Opcode::EXPAND_ZPZ_H, + 2710 => Opcode::EXPAND_ZPZ_S, + 2711 => Opcode::EXTQ_ZZI, + 2712 => Opcode::EXTRACT_ZPMXI_H_B, + 2713 => Opcode::EXTRACT_ZPMXI_H_D, + 2714 => Opcode::EXTRACT_ZPMXI_H_H, + 2715 => Opcode::EXTRACT_ZPMXI_H_Q, + 2716 => Opcode::EXTRACT_ZPMXI_H_S, + 2717 => Opcode::EXTRACT_ZPMXI_V_B, + 2718 => Opcode::EXTRACT_ZPMXI_V_D, + 2719 => Opcode::EXTRACT_ZPMXI_V_H, + 2720 => Opcode::EXTRACT_ZPMXI_V_Q, + 2721 => Opcode::EXTRACT_ZPMXI_V_S, + 2722 => Opcode::EXTRWrri, + 2723 => Opcode::EXTRXrri, + 2724 => Opcode::EXT_ZZI, + 2725 => Opcode::EXT_ZZI_B, + 2726 => Opcode::EXTv16i8, + 2727 => Opcode::EXTv8i8, + 2728 => Opcode::F1CVTL, + 2729 => Opcode::F1CVTL2, + 2730 => Opcode::F1CVTLT_ZZ_BtoH, + 2731 => Opcode::F1CVTL_2ZZ_BtoH, + 2732 => Opcode::F1CVT_2ZZ_BtoH, + 2733 => Opcode::F1CVT_ZZ_BtoH, + 2734 => Opcode::F2CVTL, + 2735 => Opcode::F2CVTL2, + 2736 => Opcode::F2CVTLT_ZZ_BtoH, + 2737 => Opcode::F2CVTL_2ZZ_BtoH, + 2738 => Opcode::F2CVT_2ZZ_BtoH, + 2739 => Opcode::F2CVT_ZZ_BtoH, + 2740 => Opcode::FABD16, + 2741 => Opcode::FABD32, + 2742 => Opcode::FABD64, + 2743 => Opcode::FABD_ZPmZ_D, + 2744 => Opcode::FABD_ZPmZ_H, + 2745 => Opcode::FABD_ZPmZ_S, + 2746 => Opcode::FABDv2f32, + 2747 => Opcode::FABDv2f64, + 2748 => Opcode::FABDv4f16, + 2749 => Opcode::FABDv4f32, + 2750 => Opcode::FABDv8f16, + 2751 => Opcode::FABSDr, + 2752 => Opcode::FABSHr, + 2753 => Opcode::FABSSr, + 2754 => Opcode::FABS_ZPmZ_D, + 2755 => Opcode::FABS_ZPmZ_H, + 2756 => Opcode::FABS_ZPmZ_S, + 2757 => Opcode::FABS_ZPzZ_D, + 2758 => Opcode::FABS_ZPzZ_H, + 2759 => Opcode::FABS_ZPzZ_S, + 2760 => Opcode::FABSv2f32, + 2761 => Opcode::FABSv2f64, + 2762 => Opcode::FABSv4f16, + 2763 => Opcode::FABSv4f32, + 2764 => Opcode::FABSv8f16, + 2765 => Opcode::FACGE16, + 2766 => Opcode::FACGE32, + 2767 => Opcode::FACGE64, + 2768 => Opcode::FACGE_PPzZZ_D, + 2769 => Opcode::FACGE_PPzZZ_H, + 2770 => Opcode::FACGE_PPzZZ_S, + 2771 => Opcode::FACGEv2f32, + 2772 => Opcode::FACGEv2f64, + 2773 => Opcode::FACGEv4f16, + 2774 => Opcode::FACGEv4f32, + 2775 => Opcode::FACGEv8f16, + 2776 => Opcode::FACGT16, + 2777 => Opcode::FACGT32, + 2778 => Opcode::FACGT64, + 2779 => Opcode::FACGT_PPzZZ_D, + 2780 => Opcode::FACGT_PPzZZ_H, + 2781 => Opcode::FACGT_PPzZZ_S, + 2782 => Opcode::FACGTv2f32, + 2783 => Opcode::FACGTv2f64, + 2784 => Opcode::FACGTv4f16, + 2785 => Opcode::FACGTv4f32, + 2786 => Opcode::FACGTv8f16, + 2787 => Opcode::FADDA_VPZ_D, + 2788 => Opcode::FADDA_VPZ_H, + 2789 => Opcode::FADDA_VPZ_S, + 2790 => Opcode::FADDDrr, + 2791 => Opcode::FADDHrr, + 2792 => Opcode::FADDP_ZPmZZ_D, + 2793 => Opcode::FADDP_ZPmZZ_H, + 2794 => Opcode::FADDP_ZPmZZ_S, + 2795 => Opcode::FADDPv2f32, + 2796 => Opcode::FADDPv2f64, + 2797 => Opcode::FADDPv2i16p, + 2798 => Opcode::FADDPv2i32p, + 2799 => Opcode::FADDPv2i64p, + 2800 => Opcode::FADDPv4f16, + 2801 => Opcode::FADDPv4f32, + 2802 => Opcode::FADDPv8f16, + 2803 => Opcode::FADDQV_D, + 2804 => Opcode::FADDQV_H, + 2805 => Opcode::FADDQV_S, + 2806 => Opcode::FADDSrr, + 2807 => Opcode::FADDV_VPZ_D, + 2808 => Opcode::FADDV_VPZ_H, + 2809 => Opcode::FADDV_VPZ_S, + 2810 => Opcode::FADD_VG2_M2Z_D, + 2811 => Opcode::FADD_VG2_M2Z_H, + 2812 => Opcode::FADD_VG2_M2Z_S, + 2813 => Opcode::FADD_VG4_M4Z_D, + 2814 => Opcode::FADD_VG4_M4Z_H, + 2815 => Opcode::FADD_VG4_M4Z_S, + 2816 => Opcode::FADD_ZPmI_D, + 2817 => Opcode::FADD_ZPmI_H, + 2818 => Opcode::FADD_ZPmI_S, + 2819 => Opcode::FADD_ZPmZ_D, + 2820 => Opcode::FADD_ZPmZ_H, + 2821 => Opcode::FADD_ZPmZ_S, + 2822 => Opcode::FADD_ZZZ_D, + 2823 => Opcode::FADD_ZZZ_H, + 2824 => Opcode::FADD_ZZZ_S, + 2825 => Opcode::FADDv2f32, + 2826 => Opcode::FADDv2f64, + 2827 => Opcode::FADDv4f16, + 2828 => Opcode::FADDv4f32, + 2829 => Opcode::FADDv8f16, + 2830 => Opcode::FAMAX_2Z2Z_D, + 2831 => Opcode::FAMAX_2Z2Z_H, + 2832 => Opcode::FAMAX_2Z2Z_S, + 2833 => Opcode::FAMAX_4Z4Z_D, + 2834 => Opcode::FAMAX_4Z4Z_H, + 2835 => Opcode::FAMAX_4Z4Z_S, + 2836 => Opcode::FAMAX_ZPmZ_D, + 2837 => Opcode::FAMAX_ZPmZ_H, + 2838 => Opcode::FAMAX_ZPmZ_S, + 2839 => Opcode::FAMAXv2f32, + 2840 => Opcode::FAMAXv2f64, + 2841 => Opcode::FAMAXv4f16, + 2842 => Opcode::FAMAXv4f32, + 2843 => Opcode::FAMAXv8f16, + 2844 => Opcode::FAMIN_2Z2Z_D, + 2845 => Opcode::FAMIN_2Z2Z_H, + 2846 => Opcode::FAMIN_2Z2Z_S, + 2847 => Opcode::FAMIN_4Z4Z_D, + 2848 => Opcode::FAMIN_4Z4Z_H, + 2849 => Opcode::FAMIN_4Z4Z_S, + 2850 => Opcode::FAMIN_ZPmZ_D, + 2851 => Opcode::FAMIN_ZPmZ_H, + 2852 => Opcode::FAMIN_ZPmZ_S, + 2853 => Opcode::FAMINv2f32, + 2854 => Opcode::FAMINv2f64, + 2855 => Opcode::FAMINv4f16, + 2856 => Opcode::FAMINv4f32, + 2857 => Opcode::FAMINv8f16, + 2858 => Opcode::FCADD_ZPmZ_D, + 2859 => Opcode::FCADD_ZPmZ_H, + 2860 => Opcode::FCADD_ZPmZ_S, + 2861 => Opcode::FCADDv2f32, + 2862 => Opcode::FCADDv2f64, + 2863 => Opcode::FCADDv4f16, + 2864 => Opcode::FCADDv4f32, + 2865 => Opcode::FCADDv8f16, + 2866 => Opcode::FCCMPDrr, + 2867 => Opcode::FCCMPEDrr, + 2868 => Opcode::FCCMPEHrr, + 2869 => Opcode::FCCMPESrr, + 2870 => Opcode::FCCMPHrr, + 2871 => Opcode::FCCMPSrr, + 2872 => Opcode::FCLAMP_VG2_2Z2Z_D, + 2873 => Opcode::FCLAMP_VG2_2Z2Z_H, + 2874 => Opcode::FCLAMP_VG2_2Z2Z_S, + 2875 => Opcode::FCLAMP_VG4_4Z4Z_D, + 2876 => Opcode::FCLAMP_VG4_4Z4Z_H, + 2877 => Opcode::FCLAMP_VG4_4Z4Z_S, + 2878 => Opcode::FCLAMP_ZZZ_D, + 2879 => Opcode::FCLAMP_ZZZ_H, + 2880 => Opcode::FCLAMP_ZZZ_S, + 2881 => Opcode::FCMEQ16, + 2882 => Opcode::FCMEQ32, + 2883 => Opcode::FCMEQ64, + 2884 => Opcode::FCMEQ_PPzZ0_D, + 2885 => Opcode::FCMEQ_PPzZ0_H, + 2886 => Opcode::FCMEQ_PPzZ0_S, + 2887 => Opcode::FCMEQ_PPzZZ_D, + 2888 => Opcode::FCMEQ_PPzZZ_H, + 2889 => Opcode::FCMEQ_PPzZZ_S, + 2890 => Opcode::FCMEQv1i16rz, + 2891 => Opcode::FCMEQv1i32rz, + 2892 => Opcode::FCMEQv1i64rz, + 2893 => Opcode::FCMEQv2f32, + 2894 => Opcode::FCMEQv2f64, + 2895 => Opcode::FCMEQv2i32rz, + 2896 => Opcode::FCMEQv2i64rz, + 2897 => Opcode::FCMEQv4f16, + 2898 => Opcode::FCMEQv4f32, + 2899 => Opcode::FCMEQv4i16rz, + 2900 => Opcode::FCMEQv4i32rz, + 2901 => Opcode::FCMEQv8f16, + 2902 => Opcode::FCMEQv8i16rz, + 2903 => Opcode::FCMGE16, + 2904 => Opcode::FCMGE32, + 2905 => Opcode::FCMGE64, + 2906 => Opcode::FCMGE_PPzZ0_D, + 2907 => Opcode::FCMGE_PPzZ0_H, + 2908 => Opcode::FCMGE_PPzZ0_S, + 2909 => Opcode::FCMGE_PPzZZ_D, + 2910 => Opcode::FCMGE_PPzZZ_H, + 2911 => Opcode::FCMGE_PPzZZ_S, + 2912 => Opcode::FCMGEv1i16rz, + 2913 => Opcode::FCMGEv1i32rz, + 2914 => Opcode::FCMGEv1i64rz, + 2915 => Opcode::FCMGEv2f32, + 2916 => Opcode::FCMGEv2f64, + 2917 => Opcode::FCMGEv2i32rz, + 2918 => Opcode::FCMGEv2i64rz, + 2919 => Opcode::FCMGEv4f16, + 2920 => Opcode::FCMGEv4f32, + 2921 => Opcode::FCMGEv4i16rz, + 2922 => Opcode::FCMGEv4i32rz, + 2923 => Opcode::FCMGEv8f16, + 2924 => Opcode::FCMGEv8i16rz, + 2925 => Opcode::FCMGT16, + 2926 => Opcode::FCMGT32, + 2927 => Opcode::FCMGT64, + 2928 => Opcode::FCMGT_PPzZ0_D, + 2929 => Opcode::FCMGT_PPzZ0_H, + 2930 => Opcode::FCMGT_PPzZ0_S, + 2931 => Opcode::FCMGT_PPzZZ_D, + 2932 => Opcode::FCMGT_PPzZZ_H, + 2933 => Opcode::FCMGT_PPzZZ_S, + 2934 => Opcode::FCMGTv1i16rz, + 2935 => Opcode::FCMGTv1i32rz, + 2936 => Opcode::FCMGTv1i64rz, + 2937 => Opcode::FCMGTv2f32, + 2938 => Opcode::FCMGTv2f64, + 2939 => Opcode::FCMGTv2i32rz, + 2940 => Opcode::FCMGTv2i64rz, + 2941 => Opcode::FCMGTv4f16, + 2942 => Opcode::FCMGTv4f32, + 2943 => Opcode::FCMGTv4i16rz, + 2944 => Opcode::FCMGTv4i32rz, + 2945 => Opcode::FCMGTv8f16, + 2946 => Opcode::FCMGTv8i16rz, + 2947 => Opcode::FCMLA_ZPmZZ_D, + 2948 => Opcode::FCMLA_ZPmZZ_H, + 2949 => Opcode::FCMLA_ZPmZZ_S, + 2950 => Opcode::FCMLA_ZZZI_H, + 2951 => Opcode::FCMLA_ZZZI_S, + 2952 => Opcode::FCMLAv2f32, + 2953 => Opcode::FCMLAv2f64, + 2954 => Opcode::FCMLAv4f16, + 2955 => Opcode::FCMLAv4f16_indexed, + 2956 => Opcode::FCMLAv4f32, + 2957 => Opcode::FCMLAv4f32_indexed, + 2958 => Opcode::FCMLAv8f16, + 2959 => Opcode::FCMLAv8f16_indexed, + 2960 => Opcode::FCMLE_PPzZ0_D, + 2961 => Opcode::FCMLE_PPzZ0_H, + 2962 => Opcode::FCMLE_PPzZ0_S, + 2963 => Opcode::FCMLEv1i16rz, + 2964 => Opcode::FCMLEv1i32rz, + 2965 => Opcode::FCMLEv1i64rz, + 2966 => Opcode::FCMLEv2i32rz, + 2967 => Opcode::FCMLEv2i64rz, + 2968 => Opcode::FCMLEv4i16rz, + 2969 => Opcode::FCMLEv4i32rz, + 2970 => Opcode::FCMLEv8i16rz, + 2971 => Opcode::FCMLT_PPzZ0_D, + 2972 => Opcode::FCMLT_PPzZ0_H, + 2973 => Opcode::FCMLT_PPzZ0_S, + 2974 => Opcode::FCMLTv1i16rz, + 2975 => Opcode::FCMLTv1i32rz, + 2976 => Opcode::FCMLTv1i64rz, + 2977 => Opcode::FCMLTv2i32rz, + 2978 => Opcode::FCMLTv2i64rz, + 2979 => Opcode::FCMLTv4i16rz, + 2980 => Opcode::FCMLTv4i32rz, + 2981 => Opcode::FCMLTv8i16rz, + 2982 => Opcode::FCMNE_PPzZ0_D, + 2983 => Opcode::FCMNE_PPzZ0_H, + 2984 => Opcode::FCMNE_PPzZ0_S, + 2985 => Opcode::FCMNE_PPzZZ_D, + 2986 => Opcode::FCMNE_PPzZZ_H, + 2987 => Opcode::FCMNE_PPzZZ_S, + 2988 => Opcode::FCMPDri, + 2989 => Opcode::FCMPDrr, + 2990 => Opcode::FCMPEDri, + 2991 => Opcode::FCMPEDrr, + 2992 => Opcode::FCMPEHri, + 2993 => Opcode::FCMPEHrr, + 2994 => Opcode::FCMPESri, + 2995 => Opcode::FCMPESrr, + 2996 => Opcode::FCMPHri, + 2997 => Opcode::FCMPHrr, + 2998 => Opcode::FCMPSri, + 2999 => Opcode::FCMPSrr, + 3000 => Opcode::FCMUO_PPzZZ_D, + 3001 => Opcode::FCMUO_PPzZZ_H, + 3002 => Opcode::FCMUO_PPzZZ_S, + 3003 => Opcode::FCPY_ZPmI_D, + 3004 => Opcode::FCPY_ZPmI_H, + 3005 => Opcode::FCPY_ZPmI_S, + 3006 => Opcode::FCSELDrrr, + 3007 => Opcode::FCSELHrrr, + 3008 => Opcode::FCSELSrrr, + 3009 => Opcode::FCVTASDHr, + 3010 => Opcode::FCVTASDSr, + 3011 => Opcode::FCVTASSDr, + 3012 => Opcode::FCVTASSHr, + 3013 => Opcode::FCVTASUWDr, + 3014 => Opcode::FCVTASUWHr, + 3015 => Opcode::FCVTASUWSr, + 3016 => Opcode::FCVTASUXDr, + 3017 => Opcode::FCVTASUXHr, + 3018 => Opcode::FCVTASUXSr, + 3019 => Opcode::FCVTASv1f16, + 3020 => Opcode::FCVTASv1i32, + 3021 => Opcode::FCVTASv1i64, + 3022 => Opcode::FCVTASv2f32, + 3023 => Opcode::FCVTASv2f64, + 3024 => Opcode::FCVTASv4f16, + 3025 => Opcode::FCVTASv4f32, + 3026 => Opcode::FCVTASv8f16, + 3027 => Opcode::FCVTAUDHr, + 3028 => Opcode::FCVTAUDSr, + 3029 => Opcode::FCVTAUSDr, + 3030 => Opcode::FCVTAUSHr, + 3031 => Opcode::FCVTAUUWDr, + 3032 => Opcode::FCVTAUUWHr, + 3033 => Opcode::FCVTAUUWSr, + 3034 => Opcode::FCVTAUUXDr, + 3035 => Opcode::FCVTAUUXHr, + 3036 => Opcode::FCVTAUUXSr, + 3037 => Opcode::FCVTAUv1f16, + 3038 => Opcode::FCVTAUv1i32, + 3039 => Opcode::FCVTAUv1i64, + 3040 => Opcode::FCVTAUv2f32, + 3041 => Opcode::FCVTAUv2f64, + 3042 => Opcode::FCVTAUv4f16, + 3043 => Opcode::FCVTAUv4f32, + 3044 => Opcode::FCVTAUv8f16, + 3045 => Opcode::FCVTDHr, + 3046 => Opcode::FCVTDSr, + 3047 => Opcode::FCVTHDr, + 3048 => Opcode::FCVTHSr, + 3049 => Opcode::FCVTLT_ZPmZ_HtoS, + 3050 => Opcode::FCVTLT_ZPmZ_StoD, + 3051 => Opcode::FCVTLT_ZPzZ_HtoS, + 3052 => Opcode::FCVTLT_ZPzZ_StoD, + 3053 => Opcode::FCVTL_2ZZ_H_S, + 3054 => Opcode::FCVTLv2i32, + 3055 => Opcode::FCVTLv4i16, + 3056 => Opcode::FCVTLv4i32, + 3057 => Opcode::FCVTLv8i16, + 3058 => Opcode::FCVTMSDHr, + 3059 => Opcode::FCVTMSDSr, + 3060 => Opcode::FCVTMSSDr, + 3061 => Opcode::FCVTMSSHr, + 3062 => Opcode::FCVTMSUWDr, + 3063 => Opcode::FCVTMSUWHr, + 3064 => Opcode::FCVTMSUWSr, + 3065 => Opcode::FCVTMSUXDr, + 3066 => Opcode::FCVTMSUXHr, + 3067 => Opcode::FCVTMSUXSr, + 3068 => Opcode::FCVTMSv1f16, + 3069 => Opcode::FCVTMSv1i32, + 3070 => Opcode::FCVTMSv1i64, + 3071 => Opcode::FCVTMSv2f32, + 3072 => Opcode::FCVTMSv2f64, + 3073 => Opcode::FCVTMSv4f16, + 3074 => Opcode::FCVTMSv4f32, + 3075 => Opcode::FCVTMSv8f16, + 3076 => Opcode::FCVTMUDHr, + 3077 => Opcode::FCVTMUDSr, + 3078 => Opcode::FCVTMUSDr, + 3079 => Opcode::FCVTMUSHr, + 3080 => Opcode::FCVTMUUWDr, + 3081 => Opcode::FCVTMUUWHr, + 3082 => Opcode::FCVTMUUWSr, + 3083 => Opcode::FCVTMUUXDr, + 3084 => Opcode::FCVTMUUXHr, + 3085 => Opcode::FCVTMUUXSr, + 3086 => Opcode::FCVTMUv1f16, + 3087 => Opcode::FCVTMUv1i32, + 3088 => Opcode::FCVTMUv1i64, + 3089 => Opcode::FCVTMUv2f32, + 3090 => Opcode::FCVTMUv2f64, + 3091 => Opcode::FCVTMUv4f16, + 3092 => Opcode::FCVTMUv4f32, + 3093 => Opcode::FCVTMUv8f16, + 3094 => Opcode::FCVTNB_Z2Z_StoB, + 3095 => Opcode::FCVTNSDHr, + 3096 => Opcode::FCVTNSDSr, + 3097 => Opcode::FCVTNSSDr, + 3098 => Opcode::FCVTNSSHr, + 3099 => Opcode::FCVTNSUWDr, + 3100 => Opcode::FCVTNSUWHr, + 3101 => Opcode::FCVTNSUWSr, + 3102 => Opcode::FCVTNSUXDr, + 3103 => Opcode::FCVTNSUXHr, + 3104 => Opcode::FCVTNSUXSr, + 3105 => Opcode::FCVTNSv1f16, + 3106 => Opcode::FCVTNSv1i32, + 3107 => Opcode::FCVTNSv1i64, + 3108 => Opcode::FCVTNSv2f32, + 3109 => Opcode::FCVTNSv2f64, + 3110 => Opcode::FCVTNSv4f16, + 3111 => Opcode::FCVTNSv4f32, + 3112 => Opcode::FCVTNSv8f16, + 3113 => Opcode::FCVTNT_Z2Z_StoB, + 3114 => Opcode::FCVTNT_ZPmZ_DtoS, + 3115 => Opcode::FCVTNT_ZPmZ_StoH, + 3116 => Opcode::FCVTNT_ZPzZ_DtoS, + 3117 => Opcode::FCVTNT_ZPzZ_StoH, + 3118 => Opcode::FCVTNUDHr, + 3119 => Opcode::FCVTNUDSr, + 3120 => Opcode::FCVTNUSDr, + 3121 => Opcode::FCVTNUSHr, + 3122 => Opcode::FCVTNUUWDr, + 3123 => Opcode::FCVTNUUWHr, + 3124 => Opcode::FCVTNUUWSr, + 3125 => Opcode::FCVTNUUXDr, + 3126 => Opcode::FCVTNUUXHr, + 3127 => Opcode::FCVTNUUXSr, + 3128 => Opcode::FCVTNUv1f16, + 3129 => Opcode::FCVTNUv1i32, + 3130 => Opcode::FCVTNUv1i64, + 3131 => Opcode::FCVTNUv2f32, + 3132 => Opcode::FCVTNUv2f64, + 3133 => Opcode::FCVTNUv4f16, + 3134 => Opcode::FCVTNUv4f32, + 3135 => Opcode::FCVTNUv8f16, + 3136 => Opcode::FCVTN_F16v16f8, + 3137 => Opcode::FCVTN_F16v8f8, + 3138 => Opcode::FCVTN_F322v16f8, + 3139 => Opcode::FCVTN_F32v8f8, + 3140 => Opcode::FCVTN_Z2Z_HtoB, + 3141 => Opcode::FCVTN_Z2Z_StoH, + 3142 => Opcode::FCVTN_Z4Z_StoB, + 3143 => Opcode::FCVTNv2i32, + 3144 => Opcode::FCVTNv4i16, + 3145 => Opcode::FCVTNv4i32, + 3146 => Opcode::FCVTNv8i16, + 3147 => Opcode::FCVTPSDHr, + 3148 => Opcode::FCVTPSDSr, + 3149 => Opcode::FCVTPSSDr, + 3150 => Opcode::FCVTPSSHr, + 3151 => Opcode::FCVTPSUWDr, + 3152 => Opcode::FCVTPSUWHr, + 3153 => Opcode::FCVTPSUWSr, + 3154 => Opcode::FCVTPSUXDr, + 3155 => Opcode::FCVTPSUXHr, + 3156 => Opcode::FCVTPSUXSr, + 3157 => Opcode::FCVTPSv1f16, + 3158 => Opcode::FCVTPSv1i32, + 3159 => Opcode::FCVTPSv1i64, + 3160 => Opcode::FCVTPSv2f32, + 3161 => Opcode::FCVTPSv2f64, + 3162 => Opcode::FCVTPSv4f16, + 3163 => Opcode::FCVTPSv4f32, + 3164 => Opcode::FCVTPSv8f16, + 3165 => Opcode::FCVTPUDHr, + 3166 => Opcode::FCVTPUDSr, + 3167 => Opcode::FCVTPUSDr, + 3168 => Opcode::FCVTPUSHr, + 3169 => Opcode::FCVTPUUWDr, + 3170 => Opcode::FCVTPUUWHr, + 3171 => Opcode::FCVTPUUWSr, + 3172 => Opcode::FCVTPUUXDr, + 3173 => Opcode::FCVTPUUXHr, + 3174 => Opcode::FCVTPUUXSr, + 3175 => Opcode::FCVTPUv1f16, + 3176 => Opcode::FCVTPUv1i32, + 3177 => Opcode::FCVTPUv1i64, + 3178 => Opcode::FCVTPUv2f32, + 3179 => Opcode::FCVTPUv2f64, + 3180 => Opcode::FCVTPUv4f16, + 3181 => Opcode::FCVTPUv4f32, + 3182 => Opcode::FCVTPUv8f16, + 3183 => Opcode::FCVTSDr, + 3184 => Opcode::FCVTSHr, + 3185 => Opcode::FCVTXNT_ZPmZ_DtoS, + 3186 => Opcode::FCVTXNT_ZPzZ_StoD, + 3187 => Opcode::FCVTXNv1i64, + 3188 => Opcode::FCVTXNv2f32, + 3189 => Opcode::FCVTXNv4f32, + 3190 => Opcode::FCVTX_ZPmZ_DtoS, + 3191 => Opcode::FCVTX_ZPzZ_DtoS, + 3192 => Opcode::FCVTZSDHr, + 3193 => Opcode::FCVTZSDSr, + 3194 => Opcode::FCVTZSN_Z2Z_DtoS, + 3195 => Opcode::FCVTZSN_Z2Z_HtoB, + 3196 => Opcode::FCVTZSN_Z2Z_StoH, + 3197 => Opcode::FCVTZSSDr, + 3198 => Opcode::FCVTZSSHr, + 3199 => Opcode::FCVTZSSWDri, + 3200 => Opcode::FCVTZSSWHri, + 3201 => Opcode::FCVTZSSWSri, + 3202 => Opcode::FCVTZSSXDri, + 3203 => Opcode::FCVTZSSXHri, + 3204 => Opcode::FCVTZSSXSri, + 3205 => Opcode::FCVTZSUWDr, + 3206 => Opcode::FCVTZSUWHr, + 3207 => Opcode::FCVTZSUWSr, + 3208 => Opcode::FCVTZSUXDr, + 3209 => Opcode::FCVTZSUXHr, + 3210 => Opcode::FCVTZSUXSr, + 3211 => Opcode::FCVTZS_2Z2Z_StoS, + 3212 => Opcode::FCVTZS_4Z4Z_StoS, + 3213 => Opcode::FCVTZS_ZPmZ_DtoD, + 3214 => Opcode::FCVTZS_ZPmZ_DtoS, + 3215 => Opcode::FCVTZS_ZPmZ_HtoD, + 3216 => Opcode::FCVTZS_ZPmZ_HtoH, + 3217 => Opcode::FCVTZS_ZPmZ_HtoS, + 3218 => Opcode::FCVTZS_ZPmZ_StoD, + 3219 => Opcode::FCVTZS_ZPmZ_StoS, + 3220 => Opcode::FCVTZS_ZPzZ_DtoD, + 3221 => Opcode::FCVTZS_ZPzZ_DtoS, + 3222 => Opcode::FCVTZS_ZPzZ_HtoD, + 3223 => Opcode::FCVTZS_ZPzZ_HtoH, + 3224 => Opcode::FCVTZS_ZPzZ_HtoS, + 3225 => Opcode::FCVTZS_ZPzZ_StoD, + 3226 => Opcode::FCVTZS_ZPzZ_StoS, + 3227 => Opcode::FCVTZSd, + 3228 => Opcode::FCVTZSh, + 3229 => Opcode::FCVTZSs, + 3230 => Opcode::FCVTZSv1f16, + 3231 => Opcode::FCVTZSv1i32, + 3232 => Opcode::FCVTZSv1i64, + 3233 => Opcode::FCVTZSv2f32, + 3234 => Opcode::FCVTZSv2f64, + 3235 => Opcode::FCVTZSv2i32_shift, + 3236 => Opcode::FCVTZSv2i64_shift, + 3237 => Opcode::FCVTZSv4f16, + 3238 => Opcode::FCVTZSv4f32, + 3239 => Opcode::FCVTZSv4i16_shift, + 3240 => Opcode::FCVTZSv4i32_shift, + 3241 => Opcode::FCVTZSv8f16, + 3242 => Opcode::FCVTZSv8i16_shift, + 3243 => Opcode::FCVTZUDHr, + 3244 => Opcode::FCVTZUDSr, + 3245 => Opcode::FCVTZUN_Z2Z_DtoS, + 3246 => Opcode::FCVTZUN_Z2Z_HtoB, + 3247 => Opcode::FCVTZUN_Z2Z_StoH, + 3248 => Opcode::FCVTZUSDr, + 3249 => Opcode::FCVTZUSHr, + 3250 => Opcode::FCVTZUSWDri, + 3251 => Opcode::FCVTZUSWHri, + 3252 => Opcode::FCVTZUSWSri, + 3253 => Opcode::FCVTZUSXDri, + 3254 => Opcode::FCVTZUSXHri, + 3255 => Opcode::FCVTZUSXSri, + 3256 => Opcode::FCVTZUUWDr, + 3257 => Opcode::FCVTZUUWHr, + 3258 => Opcode::FCVTZUUWSr, + 3259 => Opcode::FCVTZUUXDr, + 3260 => Opcode::FCVTZUUXHr, + 3261 => Opcode::FCVTZUUXSr, + 3262 => Opcode::FCVTZU_2Z2Z_StoS, + 3263 => Opcode::FCVTZU_4Z4Z_StoS, + 3264 => Opcode::FCVTZU_ZPmZ_DtoD, + 3265 => Opcode::FCVTZU_ZPmZ_DtoS, + 3266 => Opcode::FCVTZU_ZPmZ_HtoD, + 3267 => Opcode::FCVTZU_ZPmZ_HtoH, + 3268 => Opcode::FCVTZU_ZPmZ_HtoS, + 3269 => Opcode::FCVTZU_ZPmZ_StoD, + 3270 => Opcode::FCVTZU_ZPmZ_StoS, + 3271 => Opcode::FCVTZU_ZPzZ_DtoD, + 3272 => Opcode::FCVTZU_ZPzZ_DtoS, + 3273 => Opcode::FCVTZU_ZPzZ_HtoD, + 3274 => Opcode::FCVTZU_ZPzZ_HtoH, + 3275 => Opcode::FCVTZU_ZPzZ_HtoS, + 3276 => Opcode::FCVTZU_ZPzZ_StoD, + 3277 => Opcode::FCVTZU_ZPzZ_StoS, + 3278 => Opcode::FCVTZUd, + 3279 => Opcode::FCVTZUh, + 3280 => Opcode::FCVTZUs, + 3281 => Opcode::FCVTZUv1f16, + 3282 => Opcode::FCVTZUv1i32, + 3283 => Opcode::FCVTZUv1i64, + 3284 => Opcode::FCVTZUv2f32, + 3285 => Opcode::FCVTZUv2f64, + 3286 => Opcode::FCVTZUv2i32_shift, + 3287 => Opcode::FCVTZUv2i64_shift, + 3288 => Opcode::FCVTZUv4f16, + 3289 => Opcode::FCVTZUv4f32, + 3290 => Opcode::FCVTZUv4i16_shift, + 3291 => Opcode::FCVTZUv4i32_shift, + 3292 => Opcode::FCVTZUv8f16, + 3293 => Opcode::FCVTZUv8i16_shift, + 3294 => Opcode::FCVT_2ZZ_H_S, + 3295 => Opcode::FCVT_Z2Z_HtoB, + 3296 => Opcode::FCVT_Z2Z_StoH, + 3297 => Opcode::FCVT_Z4Z_StoB, + 3298 => Opcode::FCVT_ZPmZ_DtoH, + 3299 => Opcode::FCVT_ZPmZ_DtoS, + 3300 => Opcode::FCVT_ZPmZ_HtoD, + 3301 => Opcode::FCVT_ZPmZ_HtoS, + 3302 => Opcode::FCVT_ZPmZ_StoD, + 3303 => Opcode::FCVT_ZPmZ_StoH, + 3304 => Opcode::FCVT_ZPzZ_DtoH, + 3305 => Opcode::FCVT_ZPzZ_DtoS, + 3306 => Opcode::FCVT_ZPzZ_HtoD, + 3307 => Opcode::FCVT_ZPzZ_HtoS, + 3308 => Opcode::FCVT_ZPzZ_StoD, + 3309 => Opcode::FCVT_ZPzZ_StoH, + 3310 => Opcode::FDIVDrr, + 3311 => Opcode::FDIVHrr, + 3312 => Opcode::FDIVR_ZPmZ_D, + 3313 => Opcode::FDIVR_ZPmZ_H, + 3314 => Opcode::FDIVR_ZPmZ_S, + 3315 => Opcode::FDIVSrr, + 3316 => Opcode::FDIV_ZPmZ_D, + 3317 => Opcode::FDIV_ZPmZ_H, + 3318 => Opcode::FDIV_ZPmZ_S, + 3319 => Opcode::FDIVv2f32, + 3320 => Opcode::FDIVv2f64, + 3321 => Opcode::FDIVv4f16, + 3322 => Opcode::FDIVv4f32, + 3323 => Opcode::FDIVv8f16, + 3324 => Opcode::FDOT_VG2_M2Z2Z_BtoH, + 3325 => Opcode::FDOT_VG2_M2Z2Z_BtoS, + 3326 => Opcode::FDOT_VG2_M2Z2Z_HtoS, + 3327 => Opcode::FDOT_VG2_M2ZZI_BtoH, + 3328 => Opcode::FDOT_VG2_M2ZZI_BtoS, + 3329 => Opcode::FDOT_VG2_M2ZZI_HtoS, + 3330 => Opcode::FDOT_VG2_M2ZZ_BtoH, + 3331 => Opcode::FDOT_VG2_M2ZZ_BtoS, + 3332 => Opcode::FDOT_VG2_M2ZZ_HtoS, + 3333 => Opcode::FDOT_VG4_M4Z4Z_BtoH, + 3334 => Opcode::FDOT_VG4_M4Z4Z_BtoS, + 3335 => Opcode::FDOT_VG4_M4Z4Z_HtoS, + 3336 => Opcode::FDOT_VG4_M4ZZI_BtoH, + 3337 => Opcode::FDOT_VG4_M4ZZI_BtoS, + 3338 => Opcode::FDOT_VG4_M4ZZI_HtoS, + 3339 => Opcode::FDOT_VG4_M4ZZ_BtoH, + 3340 => Opcode::FDOT_VG4_M4ZZ_BtoS, + 3341 => Opcode::FDOT_VG4_M4ZZ_HtoS, + 3342 => Opcode::FDOT_ZZZI_BtoH, + 3343 => Opcode::FDOT_ZZZI_BtoS, + 3344 => Opcode::FDOT_ZZZI_S, + 3345 => Opcode::FDOT_ZZZ_BtoH, + 3346 => Opcode::FDOT_ZZZ_BtoS, + 3347 => Opcode::FDOT_ZZZ_S, + 3348 => Opcode::FDOTlanev2f32, + 3349 => Opcode::FDOTlanev4f16, + 3350 => Opcode::FDOTlanev4f16_v2f32, + 3351 => Opcode::FDOTlanev4f32, + 3352 => Opcode::FDOTlanev8f16, + 3353 => Opcode::FDOTlanev8f16_v4f32, + 3354 => Opcode::FDOTv2f32, + 3355 => Opcode::FDOTv4f16, + 3356 => Opcode::FDOTv4f16_v2f32, + 3357 => Opcode::FDOTv4f32, + 3358 => Opcode::FDOTv8f16, + 3359 => Opcode::FDOTv8f16_v4f32, + 3360 => Opcode::FDUP_ZI_D, + 3361 => Opcode::FDUP_ZI_H, + 3362 => Opcode::FDUP_ZI_S, + 3363 => Opcode::FEXPA_ZZ_D, + 3364 => Opcode::FEXPA_ZZ_H, + 3365 => Opcode::FEXPA_ZZ_S, + 3366 => Opcode::FIRSTP_XPP_B, + 3367 => Opcode::FIRSTP_XPP_D, + 3368 => Opcode::FIRSTP_XPP_H, + 3369 => Opcode::FIRSTP_XPP_S, + 3370 => Opcode::FJCVTZS, + 3371 => Opcode::FLOGB_ZPmZ_D, + 3372 => Opcode::FLOGB_ZPmZ_H, + 3373 => Opcode::FLOGB_ZPmZ_S, + 3374 => Opcode::FLOGB_ZPzZ_D, + 3375 => Opcode::FLOGB_ZPzZ_H, + 3376 => Opcode::FLOGB_ZPzZ_S, + 3377 => Opcode::FMADDDrrr, + 3378 => Opcode::FMADDHrrr, + 3379 => Opcode::FMADDSrrr, + 3380 => Opcode::FMAD_ZPmZZ_D, + 3381 => Opcode::FMAD_ZPmZZ_H, + 3382 => Opcode::FMAD_ZPmZZ_S, + 3383 => Opcode::FMAXDrr, + 3384 => Opcode::FMAXHrr, + 3385 => Opcode::FMAXNMDrr, + 3386 => Opcode::FMAXNMHrr, + 3387 => Opcode::FMAXNMP_ZPmZZ_D, + 3388 => Opcode::FMAXNMP_ZPmZZ_H, + 3389 => Opcode::FMAXNMP_ZPmZZ_S, + 3390 => Opcode::FMAXNMPv2f32, + 3391 => Opcode::FMAXNMPv2f64, + 3392 => Opcode::FMAXNMPv2i16p, + 3393 => Opcode::FMAXNMPv2i32p, + 3394 => Opcode::FMAXNMPv2i64p, + 3395 => Opcode::FMAXNMPv4f16, + 3396 => Opcode::FMAXNMPv4f32, + 3397 => Opcode::FMAXNMPv8f16, + 3398 => Opcode::FMAXNMQV_D, + 3399 => Opcode::FMAXNMQV_H, + 3400 => Opcode::FMAXNMQV_S, + 3401 => Opcode::FMAXNMSrr, + 3402 => Opcode::FMAXNMV_VPZ_D, + 3403 => Opcode::FMAXNMV_VPZ_H, + 3404 => Opcode::FMAXNMV_VPZ_S, + 3405 => Opcode::FMAXNMVv4i16v, + 3406 => Opcode::FMAXNMVv4i32v, + 3407 => Opcode::FMAXNMVv8i16v, + 3408 => Opcode::FMAXNM_VG2_2Z2Z_D, + 3409 => Opcode::FMAXNM_VG2_2Z2Z_H, + 3410 => Opcode::FMAXNM_VG2_2Z2Z_S, + 3411 => Opcode::FMAXNM_VG2_2ZZ_D, + 3412 => Opcode::FMAXNM_VG2_2ZZ_H, + 3413 => Opcode::FMAXNM_VG2_2ZZ_S, + 3414 => Opcode::FMAXNM_VG4_4Z4Z_D, + 3415 => Opcode::FMAXNM_VG4_4Z4Z_H, + 3416 => Opcode::FMAXNM_VG4_4Z4Z_S, + 3417 => Opcode::FMAXNM_VG4_4ZZ_D, + 3418 => Opcode::FMAXNM_VG4_4ZZ_H, + 3419 => Opcode::FMAXNM_VG4_4ZZ_S, + 3420 => Opcode::FMAXNM_ZPmI_D, + 3421 => Opcode::FMAXNM_ZPmI_H, + 3422 => Opcode::FMAXNM_ZPmI_S, + 3423 => Opcode::FMAXNM_ZPmZ_D, + 3424 => Opcode::FMAXNM_ZPmZ_H, + 3425 => Opcode::FMAXNM_ZPmZ_S, + 3426 => Opcode::FMAXNMv2f32, + 3427 => Opcode::FMAXNMv2f64, + 3428 => Opcode::FMAXNMv4f16, + 3429 => Opcode::FMAXNMv4f32, + 3430 => Opcode::FMAXNMv8f16, + 3431 => Opcode::FMAXP_ZPmZZ_D, + 3432 => Opcode::FMAXP_ZPmZZ_H, + 3433 => Opcode::FMAXP_ZPmZZ_S, + 3434 => Opcode::FMAXPv2f32, + 3435 => Opcode::FMAXPv2f64, + 3436 => Opcode::FMAXPv2i16p, + 3437 => Opcode::FMAXPv2i32p, + 3438 => Opcode::FMAXPv2i64p, + 3439 => Opcode::FMAXPv4f16, + 3440 => Opcode::FMAXPv4f32, + 3441 => Opcode::FMAXPv8f16, + 3442 => Opcode::FMAXQV_D, + 3443 => Opcode::FMAXQV_H, + 3444 => Opcode::FMAXQV_S, + 3445 => Opcode::FMAXSrr, + 3446 => Opcode::FMAXV_VPZ_D, + 3447 => Opcode::FMAXV_VPZ_H, + 3448 => Opcode::FMAXV_VPZ_S, + 3449 => Opcode::FMAXVv4i16v, + 3450 => Opcode::FMAXVv4i32v, + 3451 => Opcode::FMAXVv8i16v, + 3452 => Opcode::FMAX_VG2_2Z2Z_D, + 3453 => Opcode::FMAX_VG2_2Z2Z_H, + 3454 => Opcode::FMAX_VG2_2Z2Z_S, + 3455 => Opcode::FMAX_VG2_2ZZ_D, + 3456 => Opcode::FMAX_VG2_2ZZ_H, + 3457 => Opcode::FMAX_VG2_2ZZ_S, + 3458 => Opcode::FMAX_VG4_4Z4Z_D, + 3459 => Opcode::FMAX_VG4_4Z4Z_H, + 3460 => Opcode::FMAX_VG4_4Z4Z_S, + 3461 => Opcode::FMAX_VG4_4ZZ_D, + 3462 => Opcode::FMAX_VG4_4ZZ_H, + 3463 => Opcode::FMAX_VG4_4ZZ_S, + 3464 => Opcode::FMAX_ZPmI_D, + 3465 => Opcode::FMAX_ZPmI_H, + 3466 => Opcode::FMAX_ZPmI_S, + 3467 => Opcode::FMAX_ZPmZ_D, + 3468 => Opcode::FMAX_ZPmZ_H, + 3469 => Opcode::FMAX_ZPmZ_S, + 3470 => Opcode::FMAXv2f32, + 3471 => Opcode::FMAXv2f64, + 3472 => Opcode::FMAXv4f16, + 3473 => Opcode::FMAXv4f32, + 3474 => Opcode::FMAXv8f16, + 3475 => Opcode::FMINDrr, + 3476 => Opcode::FMINHrr, + 3477 => Opcode::FMINNMDrr, + 3478 => Opcode::FMINNMHrr, + 3479 => Opcode::FMINNMP_ZPmZZ_D, + 3480 => Opcode::FMINNMP_ZPmZZ_H, + 3481 => Opcode::FMINNMP_ZPmZZ_S, + 3482 => Opcode::FMINNMPv2f32, + 3483 => Opcode::FMINNMPv2f64, + 3484 => Opcode::FMINNMPv2i16p, + 3485 => Opcode::FMINNMPv2i32p, + 3486 => Opcode::FMINNMPv2i64p, + 3487 => Opcode::FMINNMPv4f16, + 3488 => Opcode::FMINNMPv4f32, + 3489 => Opcode::FMINNMPv8f16, + 3490 => Opcode::FMINNMQV_D, + 3491 => Opcode::FMINNMQV_H, + 3492 => Opcode::FMINNMQV_S, + 3493 => Opcode::FMINNMSrr, + 3494 => Opcode::FMINNMV_VPZ_D, + 3495 => Opcode::FMINNMV_VPZ_H, + 3496 => Opcode::FMINNMV_VPZ_S, + 3497 => Opcode::FMINNMVv4i16v, + 3498 => Opcode::FMINNMVv4i32v, + 3499 => Opcode::FMINNMVv8i16v, + 3500 => Opcode::FMINNM_VG2_2Z2Z_D, + 3501 => Opcode::FMINNM_VG2_2Z2Z_H, + 3502 => Opcode::FMINNM_VG2_2Z2Z_S, + 3503 => Opcode::FMINNM_VG2_2ZZ_D, + 3504 => Opcode::FMINNM_VG2_2ZZ_H, + 3505 => Opcode::FMINNM_VG2_2ZZ_S, + 3506 => Opcode::FMINNM_VG4_4Z4Z_D, + 3507 => Opcode::FMINNM_VG4_4Z4Z_H, + 3508 => Opcode::FMINNM_VG4_4Z4Z_S, + 3509 => Opcode::FMINNM_VG4_4ZZ_D, + 3510 => Opcode::FMINNM_VG4_4ZZ_H, + 3511 => Opcode::FMINNM_VG4_4ZZ_S, + 3512 => Opcode::FMINNM_ZPmI_D, + 3513 => Opcode::FMINNM_ZPmI_H, + 3514 => Opcode::FMINNM_ZPmI_S, + 3515 => Opcode::FMINNM_ZPmZ_D, + 3516 => Opcode::FMINNM_ZPmZ_H, + 3517 => Opcode::FMINNM_ZPmZ_S, + 3518 => Opcode::FMINNMv2f32, + 3519 => Opcode::FMINNMv2f64, + 3520 => Opcode::FMINNMv4f16, + 3521 => Opcode::FMINNMv4f32, + 3522 => Opcode::FMINNMv8f16, + 3523 => Opcode::FMINP_ZPmZZ_D, + 3524 => Opcode::FMINP_ZPmZZ_H, + 3525 => Opcode::FMINP_ZPmZZ_S, + 3526 => Opcode::FMINPv2f32, + 3527 => Opcode::FMINPv2f64, + 3528 => Opcode::FMINPv2i16p, + 3529 => Opcode::FMINPv2i32p, + 3530 => Opcode::FMINPv2i64p, + 3531 => Opcode::FMINPv4f16, + 3532 => Opcode::FMINPv4f32, + 3533 => Opcode::FMINPv8f16, + 3534 => Opcode::FMINQV_D, + 3535 => Opcode::FMINQV_H, + 3536 => Opcode::FMINQV_S, + 3537 => Opcode::FMINSrr, + 3538 => Opcode::FMINV_VPZ_D, + 3539 => Opcode::FMINV_VPZ_H, + 3540 => Opcode::FMINV_VPZ_S, + 3541 => Opcode::FMINVv4i16v, + 3542 => Opcode::FMINVv4i32v, + 3543 => Opcode::FMINVv8i16v, + 3544 => Opcode::FMIN_VG2_2Z2Z_D, + 3545 => Opcode::FMIN_VG2_2Z2Z_H, + 3546 => Opcode::FMIN_VG2_2Z2Z_S, + 3547 => Opcode::FMIN_VG2_2ZZ_D, + 3548 => Opcode::FMIN_VG2_2ZZ_H, + 3549 => Opcode::FMIN_VG2_2ZZ_S, + 3550 => Opcode::FMIN_VG4_4Z4Z_D, + 3551 => Opcode::FMIN_VG4_4Z4Z_H, + 3552 => Opcode::FMIN_VG4_4Z4Z_S, + 3553 => Opcode::FMIN_VG4_4ZZ_D, + 3554 => Opcode::FMIN_VG4_4ZZ_H, + 3555 => Opcode::FMIN_VG4_4ZZ_S, + 3556 => Opcode::FMIN_ZPmI_D, + 3557 => Opcode::FMIN_ZPmI_H, + 3558 => Opcode::FMIN_ZPmI_S, + 3559 => Opcode::FMIN_ZPmZ_D, + 3560 => Opcode::FMIN_ZPmZ_H, + 3561 => Opcode::FMIN_ZPmZ_S, + 3562 => Opcode::FMINv2f32, + 3563 => Opcode::FMINv2f64, + 3564 => Opcode::FMINv4f16, + 3565 => Opcode::FMINv4f32, + 3566 => Opcode::FMINv8f16, + 3567 => Opcode::FMLAL2lanev4f16, + 3568 => Opcode::FMLAL2lanev8f16, + 3569 => Opcode::FMLAL2v4f16, + 3570 => Opcode::FMLAL2v8f16, + 3571 => Opcode::FMLALB_ZZZ, + 3572 => Opcode::FMLALB_ZZZI, + 3573 => Opcode::FMLALB_ZZZI_SHH, + 3574 => Opcode::FMLALB_ZZZ_SHH, + 3575 => Opcode::FMLALBlanev8f16, + 3576 => Opcode::FMLALBv16i8_v8f16, + 3577 => Opcode::FMLALLBB_ZZZ, + 3578 => Opcode::FMLALLBB_ZZZI, + 3579 => Opcode::FMLALLBBlanev4f32, + 3580 => Opcode::FMLALLBBv4f32, + 3581 => Opcode::FMLALLBT_ZZZ, + 3582 => Opcode::FMLALLBT_ZZZI, + 3583 => Opcode::FMLALLBTlanev4f32, + 3584 => Opcode::FMLALLBTv4f32, + 3585 => Opcode::FMLALLTB_ZZZ, + 3586 => Opcode::FMLALLTB_ZZZI, + 3587 => Opcode::FMLALLTBlanev4f32, + 3588 => Opcode::FMLALLTBv4f32, + 3589 => Opcode::FMLALLTT_ZZZ, + 3590 => Opcode::FMLALLTT_ZZZI, + 3591 => Opcode::FMLALLTTlanev4f32, + 3592 => Opcode::FMLALLTTv4f32, + 3593 => Opcode::FMLALL_MZZI_BtoS, + 3594 => Opcode::FMLALL_MZZ_BtoS, + 3595 => Opcode::FMLALL_VG2_M2Z2Z_BtoS, + 3596 => Opcode::FMLALL_VG2_M2ZZI_BtoS, + 3597 => Opcode::FMLALL_VG2_M2ZZ_BtoS, + 3598 => Opcode::FMLALL_VG4_M4Z4Z_BtoS, + 3599 => Opcode::FMLALL_VG4_M4ZZI_BtoS, + 3600 => Opcode::FMLALL_VG4_M4ZZ_BtoS, + 3601 => Opcode::FMLALT_ZZZ, + 3602 => Opcode::FMLALT_ZZZI, + 3603 => Opcode::FMLALT_ZZZI_SHH, + 3604 => Opcode::FMLALT_ZZZ_SHH, + 3605 => Opcode::FMLALTlanev8f16, + 3606 => Opcode::FMLALTv16i8_v8f16, + 3607 => Opcode::FMLAL_MZZI_BtoH, + 3608 => Opcode::FMLAL_MZZI_HtoS, + 3609 => Opcode::FMLAL_MZZ_HtoS, + 3610 => Opcode::FMLAL_VG2_M2Z2Z_BtoH, + 3611 => Opcode::FMLAL_VG2_M2Z2Z_HtoS, + 3612 => Opcode::FMLAL_VG2_M2ZZI_BtoH, + 3613 => Opcode::FMLAL_VG2_M2ZZI_HtoS, + 3614 => Opcode::FMLAL_VG2_M2ZZ_BtoH, + 3615 => Opcode::FMLAL_VG2_M2ZZ_HtoS, + 3616 => Opcode::FMLAL_VG2_MZZ_BtoH, + 3617 => Opcode::FMLAL_VG4_M4Z4Z_BtoH, + 3618 => Opcode::FMLAL_VG4_M4Z4Z_HtoS, + 3619 => Opcode::FMLAL_VG4_M4ZZI_BtoH, + 3620 => Opcode::FMLAL_VG4_M4ZZI_HtoS, + 3621 => Opcode::FMLAL_VG4_M4ZZ_BtoH, + 3622 => Opcode::FMLAL_VG4_M4ZZ_HtoS, + 3623 => Opcode::FMLALlanev4f16, + 3624 => Opcode::FMLALlanev8f16, + 3625 => Opcode::FMLALv4f16, + 3626 => Opcode::FMLALv8f16, + 3627 => Opcode::FMLA_VG2_M2Z2Z_D, + 3628 => Opcode::FMLA_VG2_M2Z2Z_H, + 3629 => Opcode::FMLA_VG2_M2Z2Z_S, + 3630 => Opcode::FMLA_VG2_M2ZZI_D, + 3631 => Opcode::FMLA_VG2_M2ZZI_H, + 3632 => Opcode::FMLA_VG2_M2ZZI_S, + 3633 => Opcode::FMLA_VG2_M2ZZ_D, + 3634 => Opcode::FMLA_VG2_M2ZZ_H, + 3635 => Opcode::FMLA_VG2_M2ZZ_S, + 3636 => Opcode::FMLA_VG4_M4Z4Z_D, + 3637 => Opcode::FMLA_VG4_M4Z4Z_H, + 3638 => Opcode::FMLA_VG4_M4Z4Z_S, + 3639 => Opcode::FMLA_VG4_M4ZZI_D, + 3640 => Opcode::FMLA_VG4_M4ZZI_H, + 3641 => Opcode::FMLA_VG4_M4ZZI_S, + 3642 => Opcode::FMLA_VG4_M4ZZ_D, + 3643 => Opcode::FMLA_VG4_M4ZZ_H, + 3644 => Opcode::FMLA_VG4_M4ZZ_S, + 3645 => Opcode::FMLA_ZPmZZ_D, + 3646 => Opcode::FMLA_ZPmZZ_H, + 3647 => Opcode::FMLA_ZPmZZ_S, + 3648 => Opcode::FMLA_ZZZI_D, + 3649 => Opcode::FMLA_ZZZI_H, + 3650 => Opcode::FMLA_ZZZI_S, + 3651 => Opcode::FMLAv1i16_indexed, + 3652 => Opcode::FMLAv1i32_indexed, + 3653 => Opcode::FMLAv1i64_indexed, + 3654 => Opcode::FMLAv2f32, + 3655 => Opcode::FMLAv2f64, + 3656 => Opcode::FMLAv2i32_indexed, + 3657 => Opcode::FMLAv2i64_indexed, + 3658 => Opcode::FMLAv4f16, + 3659 => Opcode::FMLAv4f32, + 3660 => Opcode::FMLAv4i16_indexed, + 3661 => Opcode::FMLAv4i32_indexed, + 3662 => Opcode::FMLAv8f16, + 3663 => Opcode::FMLAv8i16_indexed, + 3664 => Opcode::FMLLA_ZZZ_HtoS, + 3665 => Opcode::FMLSL2lanev4f16, + 3666 => Opcode::FMLSL2lanev8f16, + 3667 => Opcode::FMLSL2v4f16, + 3668 => Opcode::FMLSL2v8f16, + 3669 => Opcode::FMLSLB_ZZZI_SHH, + 3670 => Opcode::FMLSLB_ZZZ_SHH, + 3671 => Opcode::FMLSLT_ZZZI_SHH, + 3672 => Opcode::FMLSLT_ZZZ_SHH, + 3673 => Opcode::FMLSL_MZZI_HtoS, + 3674 => Opcode::FMLSL_MZZ_HtoS, + 3675 => Opcode::FMLSL_VG2_M2Z2Z_HtoS, + 3676 => Opcode::FMLSL_VG2_M2ZZI_HtoS, + 3677 => Opcode::FMLSL_VG2_M2ZZ_HtoS, + 3678 => Opcode::FMLSL_VG4_M4Z4Z_HtoS, + 3679 => Opcode::FMLSL_VG4_M4ZZI_HtoS, + 3680 => Opcode::FMLSL_VG4_M4ZZ_HtoS, + 3681 => Opcode::FMLSLlanev4f16, + 3682 => Opcode::FMLSLlanev8f16, + 3683 => Opcode::FMLSLv4f16, + 3684 => Opcode::FMLSLv8f16, + 3685 => Opcode::FMLS_VG2_M2Z2Z_D, + 3686 => Opcode::FMLS_VG2_M2Z2Z_H, + 3687 => Opcode::FMLS_VG2_M2Z2Z_S, + 3688 => Opcode::FMLS_VG2_M2ZZI_D, + 3689 => Opcode::FMLS_VG2_M2ZZI_H, + 3690 => Opcode::FMLS_VG2_M2ZZI_S, + 3691 => Opcode::FMLS_VG2_M2ZZ_D, + 3692 => Opcode::FMLS_VG2_M2ZZ_H, + 3693 => Opcode::FMLS_VG2_M2ZZ_S, + 3694 => Opcode::FMLS_VG4_M4Z4Z_D, + 3695 => Opcode::FMLS_VG4_M4Z4Z_H, + 3696 => Opcode::FMLS_VG4_M4Z4Z_S, + 3697 => Opcode::FMLS_VG4_M4ZZI_D, + 3698 => Opcode::FMLS_VG4_M4ZZI_H, + 3699 => Opcode::FMLS_VG4_M4ZZI_S, + 3700 => Opcode::FMLS_VG4_M4ZZ_D, + 3701 => Opcode::FMLS_VG4_M4ZZ_H, + 3702 => Opcode::FMLS_VG4_M4ZZ_S, + 3703 => Opcode::FMLS_ZPmZZ_D, + 3704 => Opcode::FMLS_ZPmZZ_H, + 3705 => Opcode::FMLS_ZPmZZ_S, + 3706 => Opcode::FMLS_ZZZI_D, + 3707 => Opcode::FMLS_ZZZI_H, + 3708 => Opcode::FMLS_ZZZI_S, + 3709 => Opcode::FMLSv1i16_indexed, + 3710 => Opcode::FMLSv1i32_indexed, + 3711 => Opcode::FMLSv1i64_indexed, + 3712 => Opcode::FMLSv2f32, + 3713 => Opcode::FMLSv2f64, + 3714 => Opcode::FMLSv2i32_indexed, + 3715 => Opcode::FMLSv2i64_indexed, + 3716 => Opcode::FMLSv4f16, + 3717 => Opcode::FMLSv4f32, + 3718 => Opcode::FMLSv4i16_indexed, + 3719 => Opcode::FMLSv4i32_indexed, + 3720 => Opcode::FMLSv8f16, + 3721 => Opcode::FMLSv8i16_indexed, + 3722 => Opcode::FMMLA_ZZZ_BtoH, + 3723 => Opcode::FMMLA_ZZZ_BtoS, + 3724 => Opcode::FMMLA_ZZZ_D, + 3725 => Opcode::FMMLA_ZZZ_H, + 3726 => Opcode::FMMLA_ZZZ_S, + 3727 => Opcode::FMMLAv4f32, + 3728 => Opcode::FMMLAv8f16, + 3729 => Opcode::FMMLAv8f16_v4f32, + 3730 => Opcode::FMMLAv8f16_v8f16, + 3731 => Opcode::FMOP4A_M2Z2Z_BtoH, + 3732 => Opcode::FMOP4A_M2Z2Z_BtoS, + 3733 => Opcode::FMOP4A_M2Z2Z_D, + 3734 => Opcode::FMOP4A_M2Z2Z_H, + 3735 => Opcode::FMOP4A_M2Z2Z_HtoS, + 3736 => Opcode::FMOP4A_M2Z2Z_S, + 3737 => Opcode::FMOP4A_M2ZZ_BtoH, + 3738 => Opcode::FMOP4A_M2ZZ_BtoS, + 3739 => Opcode::FMOP4A_M2ZZ_D, + 3740 => Opcode::FMOP4A_M2ZZ_H, + 3741 => Opcode::FMOP4A_M2ZZ_HtoS, + 3742 => Opcode::FMOP4A_M2ZZ_S, + 3743 => Opcode::FMOP4A_MZ2Z_BtoH, + 3744 => Opcode::FMOP4A_MZ2Z_BtoS, + 3745 => Opcode::FMOP4A_MZ2Z_D, + 3746 => Opcode::FMOP4A_MZ2Z_H, + 3747 => Opcode::FMOP4A_MZ2Z_HtoS, + 3748 => Opcode::FMOP4A_MZ2Z_S, + 3749 => Opcode::FMOP4A_MZZ_BtoH, + 3750 => Opcode::FMOP4A_MZZ_BtoS, + 3751 => Opcode::FMOP4A_MZZ_D, + 3752 => Opcode::FMOP4A_MZZ_H, + 3753 => Opcode::FMOP4A_MZZ_HtoS, + 3754 => Opcode::FMOP4A_MZZ_S, + 3755 => Opcode::FMOP4S_M2Z2Z_D, + 3756 => Opcode::FMOP4S_M2Z2Z_H, + 3757 => Opcode::FMOP4S_M2Z2Z_HtoS, + 3758 => Opcode::FMOP4S_M2Z2Z_S, + 3759 => Opcode::FMOP4S_M2ZZ_D, + 3760 => Opcode::FMOP4S_M2ZZ_H, + 3761 => Opcode::FMOP4S_M2ZZ_HtoS, + 3762 => Opcode::FMOP4S_M2ZZ_S, + 3763 => Opcode::FMOP4S_MZ2Z_D, + 3764 => Opcode::FMOP4S_MZ2Z_H, + 3765 => Opcode::FMOP4S_MZ2Z_HtoS, + 3766 => Opcode::FMOP4S_MZ2Z_S, + 3767 => Opcode::FMOP4S_MZZ_D, + 3768 => Opcode::FMOP4S_MZZ_H, + 3769 => Opcode::FMOP4S_MZZ_HtoS, + 3770 => Opcode::FMOP4S_MZZ_S, + 3771 => Opcode::FMOPAL_MPPZZ, + 3772 => Opcode::FMOPA_MPPZZ_BtoH, + 3773 => Opcode::FMOPA_MPPZZ_BtoS, + 3774 => Opcode::FMOPA_MPPZZ_D, + 3775 => Opcode::FMOPA_MPPZZ_H, + 3776 => Opcode::FMOPA_MPPZZ_S, + 3777 => Opcode::FMOPSL_MPPZZ, + 3778 => Opcode::FMOPS_MPPZZ_D, + 3779 => Opcode::FMOPS_MPPZZ_H, + 3780 => Opcode::FMOPS_MPPZZ_S, + 3781 => Opcode::FMOVDXHighr, + 3782 => Opcode::FMOVDXr, + 3783 => Opcode::FMOVDi, + 3784 => Opcode::FMOVDr, + 3785 => Opcode::FMOVHWr, + 3786 => Opcode::FMOVHXr, + 3787 => Opcode::FMOVHi, + 3788 => Opcode::FMOVHr, + 3789 => Opcode::FMOVSWr, + 3790 => Opcode::FMOVSi, + 3791 => Opcode::FMOVSr, + 3792 => Opcode::FMOVWHr, + 3793 => Opcode::FMOVWSr, + 3794 => Opcode::FMOVXDHighr, + 3795 => Opcode::FMOVXDr, + 3796 => Opcode::FMOVXHr, + 3797 => Opcode::FMOVv2f32_ns, + 3798 => Opcode::FMOVv2f64_ns, + 3799 => Opcode::FMOVv4f16_ns, + 3800 => Opcode::FMOVv4f32_ns, + 3801 => Opcode::FMOVv8f16_ns, + 3802 => Opcode::FMSB_ZPmZZ_D, + 3803 => Opcode::FMSB_ZPmZZ_H, + 3804 => Opcode::FMSB_ZPmZZ_S, + 3805 => Opcode::FMSUBDrrr, + 3806 => Opcode::FMSUBHrrr, + 3807 => Opcode::FMSUBSrrr, + 3808 => Opcode::FMULDrr, + 3809 => Opcode::FMULHrr, + 3810 => Opcode::FMULSrr, + 3811 => Opcode::FMULX16, + 3812 => Opcode::FMULX32, + 3813 => Opcode::FMULX64, + 3814 => Opcode::FMULX_ZPmZ_D, + 3815 => Opcode::FMULX_ZPmZ_H, + 3816 => Opcode::FMULX_ZPmZ_S, + 3817 => Opcode::FMULXv1i16_indexed, + 3818 => Opcode::FMULXv1i32_indexed, + 3819 => Opcode::FMULXv1i64_indexed, + 3820 => Opcode::FMULXv2f32, + 3821 => Opcode::FMULXv2f64, + 3822 => Opcode::FMULXv2i32_indexed, + 3823 => Opcode::FMULXv2i64_indexed, + 3824 => Opcode::FMULXv4f16, + 3825 => Opcode::FMULXv4f32, + 3826 => Opcode::FMULXv4i16_indexed, + 3827 => Opcode::FMULXv4i32_indexed, + 3828 => Opcode::FMULXv8f16, + 3829 => Opcode::FMULXv8i16_indexed, + 3830 => Opcode::FMUL_2Z2Z_D, + 3831 => Opcode::FMUL_2Z2Z_H, + 3832 => Opcode::FMUL_2Z2Z_S, + 3833 => Opcode::FMUL_2ZZ_D, + 3834 => Opcode::FMUL_2ZZ_H, + 3835 => Opcode::FMUL_2ZZ_S, + 3836 => Opcode::FMUL_4Z4Z_D, + 3837 => Opcode::FMUL_4Z4Z_H, + 3838 => Opcode::FMUL_4Z4Z_S, + 3839 => Opcode::FMUL_4ZZ_D, + 3840 => Opcode::FMUL_4ZZ_H, + 3841 => Opcode::FMUL_4ZZ_S, + 3842 => Opcode::FMUL_ZPmI_D, + 3843 => Opcode::FMUL_ZPmI_H, + 3844 => Opcode::FMUL_ZPmI_S, + 3845 => Opcode::FMUL_ZPmZ_D, + 3846 => Opcode::FMUL_ZPmZ_H, + 3847 => Opcode::FMUL_ZPmZ_S, + 3848 => Opcode::FMUL_ZZZI_D, + 3849 => Opcode::FMUL_ZZZI_H, + 3850 => Opcode::FMUL_ZZZI_S, + 3851 => Opcode::FMUL_ZZZ_D, + 3852 => Opcode::FMUL_ZZZ_H, + 3853 => Opcode::FMUL_ZZZ_S, + 3854 => Opcode::FMULv1i16_indexed, + 3855 => Opcode::FMULv1i32_indexed, + 3856 => Opcode::FMULv1i64_indexed, + 3857 => Opcode::FMULv2f32, + 3858 => Opcode::FMULv2f64, + 3859 => Opcode::FMULv2i32_indexed, + 3860 => Opcode::FMULv2i64_indexed, + 3861 => Opcode::FMULv4f16, + 3862 => Opcode::FMULv4f32, + 3863 => Opcode::FMULv4i16_indexed, + 3864 => Opcode::FMULv4i32_indexed, + 3865 => Opcode::FMULv8f16, + 3866 => Opcode::FMULv8i16_indexed, + 3867 => Opcode::FNEGDr, + 3868 => Opcode::FNEGHr, + 3869 => Opcode::FNEGSr, + 3870 => Opcode::FNEG_ZPmZ_D, + 3871 => Opcode::FNEG_ZPmZ_H, + 3872 => Opcode::FNEG_ZPmZ_S, + 3873 => Opcode::FNEG_ZPzZ_D, + 3874 => Opcode::FNEG_ZPzZ_H, + 3875 => Opcode::FNEG_ZPzZ_S, + 3876 => Opcode::FNEGv2f32, + 3877 => Opcode::FNEGv2f64, + 3878 => Opcode::FNEGv4f16, + 3879 => Opcode::FNEGv4f32, + 3880 => Opcode::FNEGv8f16, + 3881 => Opcode::FNMADDDrrr, + 3882 => Opcode::FNMADDHrrr, + 3883 => Opcode::FNMADDSrrr, + 3884 => Opcode::FNMAD_ZPmZZ_D, + 3885 => Opcode::FNMAD_ZPmZZ_H, + 3886 => Opcode::FNMAD_ZPmZZ_S, + 3887 => Opcode::FNMLA_ZPmZZ_D, + 3888 => Opcode::FNMLA_ZPmZZ_H, + 3889 => Opcode::FNMLA_ZPmZZ_S, + 3890 => Opcode::FNMLS_ZPmZZ_D, + 3891 => Opcode::FNMLS_ZPmZZ_H, + 3892 => Opcode::FNMLS_ZPmZZ_S, + 3893 => Opcode::FNMSB_ZPmZZ_D, + 3894 => Opcode::FNMSB_ZPmZZ_H, + 3895 => Opcode::FNMSB_ZPmZZ_S, + 3896 => Opcode::FNMSUBDrrr, + 3897 => Opcode::FNMSUBHrrr, + 3898 => Opcode::FNMSUBSrrr, + 3899 => Opcode::FNMULDrr, + 3900 => Opcode::FNMULHrr, + 3901 => Opcode::FNMULSrr, + 3902 => Opcode::FRECPE_ZZ_D, + 3903 => Opcode::FRECPE_ZZ_H, + 3904 => Opcode::FRECPE_ZZ_S, + 3905 => Opcode::FRECPEv1f16, + 3906 => Opcode::FRECPEv1i32, + 3907 => Opcode::FRECPEv1i64, + 3908 => Opcode::FRECPEv2f32, + 3909 => Opcode::FRECPEv2f64, + 3910 => Opcode::FRECPEv4f16, + 3911 => Opcode::FRECPEv4f32, + 3912 => Opcode::FRECPEv8f16, + 3913 => Opcode::FRECPS16, + 3914 => Opcode::FRECPS32, + 3915 => Opcode::FRECPS64, + 3916 => Opcode::FRECPS_ZZZ_D, + 3917 => Opcode::FRECPS_ZZZ_H, + 3918 => Opcode::FRECPS_ZZZ_S, + 3919 => Opcode::FRECPSv2f32, + 3920 => Opcode::FRECPSv2f64, + 3921 => Opcode::FRECPSv4f16, + 3922 => Opcode::FRECPSv4f32, + 3923 => Opcode::FRECPSv8f16, + 3924 => Opcode::FRECPX_ZPmZ_D, + 3925 => Opcode::FRECPX_ZPmZ_H, + 3926 => Opcode::FRECPX_ZPmZ_S, + 3927 => Opcode::FRECPX_ZPzZ_D, + 3928 => Opcode::FRECPX_ZPzZ_H, + 3929 => Opcode::FRECPX_ZPzZ_S, + 3930 => Opcode::FRECPXv1f16, + 3931 => Opcode::FRECPXv1i32, + 3932 => Opcode::FRECPXv1i64, + 3933 => Opcode::FRINT32XDr, + 3934 => Opcode::FRINT32XSr, + 3935 => Opcode::FRINT32X_ZPmZ_D, + 3936 => Opcode::FRINT32X_ZPmZ_S, + 3937 => Opcode::FRINT32X_ZPzZ_D, + 3938 => Opcode::FRINT32X_ZPzZ_S, + 3939 => Opcode::FRINT32Xv2f32, + 3940 => Opcode::FRINT32Xv2f64, + 3941 => Opcode::FRINT32Xv4f32, + 3942 => Opcode::FRINT32ZDr, + 3943 => Opcode::FRINT32ZSr, + 3944 => Opcode::FRINT32Z_ZPmZ_D, + 3945 => Opcode::FRINT32Z_ZPmZ_S, + 3946 => Opcode::FRINT32Z_ZPzZ_D, + 3947 => Opcode::FRINT32Z_ZPzZ_S, + 3948 => Opcode::FRINT32Zv2f32, + 3949 => Opcode::FRINT32Zv2f64, + 3950 => Opcode::FRINT32Zv4f32, + 3951 => Opcode::FRINT64XDr, + 3952 => Opcode::FRINT64XSr, + 3953 => Opcode::FRINT64X_ZPmZ_D, + 3954 => Opcode::FRINT64X_ZPmZ_S, + 3955 => Opcode::FRINT64X_ZPzZ_D, + 3956 => Opcode::FRINT64X_ZPzZ_S, + 3957 => Opcode::FRINT64Xv2f32, + 3958 => Opcode::FRINT64Xv2f64, + 3959 => Opcode::FRINT64Xv4f32, + 3960 => Opcode::FRINT64ZDr, + 3961 => Opcode::FRINT64ZSr, + 3962 => Opcode::FRINT64Z_ZPmZ_D, + 3963 => Opcode::FRINT64Z_ZPmZ_S, + 3964 => Opcode::FRINT64Z_ZPzZ_D, + 3965 => Opcode::FRINT64Z_ZPzZ_S, + 3966 => Opcode::FRINT64Zv2f32, + 3967 => Opcode::FRINT64Zv2f64, + 3968 => Opcode::FRINT64Zv4f32, + 3969 => Opcode::FRINTADr, + 3970 => Opcode::FRINTAHr, + 3971 => Opcode::FRINTASr, + 3972 => Opcode::FRINTA_2Z2Z_S, + 3973 => Opcode::FRINTA_4Z4Z_S, + 3974 => Opcode::FRINTA_ZPmZ_D, + 3975 => Opcode::FRINTA_ZPmZ_H, + 3976 => Opcode::FRINTA_ZPmZ_S, + 3977 => Opcode::FRINTA_ZPzZ_D, + 3978 => Opcode::FRINTA_ZPzZ_H, + 3979 => Opcode::FRINTA_ZPzZ_S, + 3980 => Opcode::FRINTAv2f32, + 3981 => Opcode::FRINTAv2f64, + 3982 => Opcode::FRINTAv4f16, + 3983 => Opcode::FRINTAv4f32, + 3984 => Opcode::FRINTAv8f16, + 3985 => Opcode::FRINTIDr, + 3986 => Opcode::FRINTIHr, + 3987 => Opcode::FRINTISr, + 3988 => Opcode::FRINTI_ZPmZ_D, + 3989 => Opcode::FRINTI_ZPmZ_H, + 3990 => Opcode::FRINTI_ZPmZ_S, + 3991 => Opcode::FRINTI_ZPzZ_D, + 3992 => Opcode::FRINTI_ZPzZ_H, + 3993 => Opcode::FRINTI_ZPzZ_S, + 3994 => Opcode::FRINTIv2f32, + 3995 => Opcode::FRINTIv2f64, + 3996 => Opcode::FRINTIv4f16, + 3997 => Opcode::FRINTIv4f32, + 3998 => Opcode::FRINTIv8f16, + 3999 => Opcode::FRINTMDr, + 4000 => Opcode::FRINTMHr, + 4001 => Opcode::FRINTMSr, + 4002 => Opcode::FRINTM_2Z2Z_S, + 4003 => Opcode::FRINTM_4Z4Z_S, + 4004 => Opcode::FRINTM_ZPmZ_D, + 4005 => Opcode::FRINTM_ZPmZ_H, + 4006 => Opcode::FRINTM_ZPmZ_S, + 4007 => Opcode::FRINTM_ZPzZ_D, + 4008 => Opcode::FRINTM_ZPzZ_H, + 4009 => Opcode::FRINTM_ZPzZ_S, + 4010 => Opcode::FRINTMv2f32, + 4011 => Opcode::FRINTMv2f64, + 4012 => Opcode::FRINTMv4f16, + 4013 => Opcode::FRINTMv4f32, + 4014 => Opcode::FRINTMv8f16, + 4015 => Opcode::FRINTNDr, + 4016 => Opcode::FRINTNHr, + 4017 => Opcode::FRINTNSr, + 4018 => Opcode::FRINTN_2Z2Z_S, + 4019 => Opcode::FRINTN_4Z4Z_S, + 4020 => Opcode::FRINTN_ZPmZ_D, + 4021 => Opcode::FRINTN_ZPmZ_H, + 4022 => Opcode::FRINTN_ZPmZ_S, + 4023 => Opcode::FRINTN_ZPzZ_D, + 4024 => Opcode::FRINTN_ZPzZ_H, + 4025 => Opcode::FRINTN_ZPzZ_S, + 4026 => Opcode::FRINTNv2f32, + 4027 => Opcode::FRINTNv2f64, + 4028 => Opcode::FRINTNv4f16, + 4029 => Opcode::FRINTNv4f32, + 4030 => Opcode::FRINTNv8f16, + 4031 => Opcode::FRINTPDr, + 4032 => Opcode::FRINTPHr, + 4033 => Opcode::FRINTPSr, + 4034 => Opcode::FRINTP_2Z2Z_S, + 4035 => Opcode::FRINTP_4Z4Z_S, + 4036 => Opcode::FRINTP_ZPmZ_D, + 4037 => Opcode::FRINTP_ZPmZ_H, + 4038 => Opcode::FRINTP_ZPmZ_S, + 4039 => Opcode::FRINTP_ZPzZ_D, + 4040 => Opcode::FRINTP_ZPzZ_H, + 4041 => Opcode::FRINTP_ZPzZ_S, + 4042 => Opcode::FRINTPv2f32, + 4043 => Opcode::FRINTPv2f64, + 4044 => Opcode::FRINTPv4f16, + 4045 => Opcode::FRINTPv4f32, + 4046 => Opcode::FRINTPv8f16, + 4047 => Opcode::FRINTXDr, + 4048 => Opcode::FRINTXHr, + 4049 => Opcode::FRINTXSr, + 4050 => Opcode::FRINTX_ZPmZ_D, + 4051 => Opcode::FRINTX_ZPmZ_H, + 4052 => Opcode::FRINTX_ZPmZ_S, + 4053 => Opcode::FRINTX_ZPzZ_D, + 4054 => Opcode::FRINTX_ZPzZ_H, + 4055 => Opcode::FRINTX_ZPzZ_S, + 4056 => Opcode::FRINTXv2f32, + 4057 => Opcode::FRINTXv2f64, + 4058 => Opcode::FRINTXv4f16, + 4059 => Opcode::FRINTXv4f32, + 4060 => Opcode::FRINTXv8f16, + 4061 => Opcode::FRINTZDr, + 4062 => Opcode::FRINTZHr, + 4063 => Opcode::FRINTZSr, + 4064 => Opcode::FRINTZ_ZPmZ_D, + 4065 => Opcode::FRINTZ_ZPmZ_H, + 4066 => Opcode::FRINTZ_ZPmZ_S, + 4067 => Opcode::FRINTZ_ZPzZ_D, + 4068 => Opcode::FRINTZ_ZPzZ_H, + 4069 => Opcode::FRINTZ_ZPzZ_S, + 4070 => Opcode::FRINTZv2f32, + 4071 => Opcode::FRINTZv2f64, + 4072 => Opcode::FRINTZv4f16, + 4073 => Opcode::FRINTZv4f32, + 4074 => Opcode::FRINTZv8f16, + 4075 => Opcode::FRSQRTE_ZZ_D, + 4076 => Opcode::FRSQRTE_ZZ_H, + 4077 => Opcode::FRSQRTE_ZZ_S, + 4078 => Opcode::FRSQRTEv1f16, + 4079 => Opcode::FRSQRTEv1i32, + 4080 => Opcode::FRSQRTEv1i64, + 4081 => Opcode::FRSQRTEv2f32, + 4082 => Opcode::FRSQRTEv2f64, + 4083 => Opcode::FRSQRTEv4f16, + 4084 => Opcode::FRSQRTEv4f32, + 4085 => Opcode::FRSQRTEv8f16, + 4086 => Opcode::FRSQRTS16, + 4087 => Opcode::FRSQRTS32, + 4088 => Opcode::FRSQRTS64, + 4089 => Opcode::FRSQRTS_ZZZ_D, + 4090 => Opcode::FRSQRTS_ZZZ_H, + 4091 => Opcode::FRSQRTS_ZZZ_S, + 4092 => Opcode::FRSQRTSv2f32, + 4093 => Opcode::FRSQRTSv2f64, + 4094 => Opcode::FRSQRTSv4f16, + 4095 => Opcode::FRSQRTSv4f32, + 4096 => Opcode::FRSQRTSv8f16, + 4097 => Opcode::FSCALE_2Z2Z_D, + 4098 => Opcode::FSCALE_2Z2Z_H, + 4099 => Opcode::FSCALE_2Z2Z_S, + 4100 => Opcode::FSCALE_2ZZ_D, + 4101 => Opcode::FSCALE_2ZZ_H, + 4102 => Opcode::FSCALE_2ZZ_S, + 4103 => Opcode::FSCALE_4Z4Z_D, + 4104 => Opcode::FSCALE_4Z4Z_H, + 4105 => Opcode::FSCALE_4Z4Z_S, + 4106 => Opcode::FSCALE_4ZZ_D, + 4107 => Opcode::FSCALE_4ZZ_H, + 4108 => Opcode::FSCALE_4ZZ_S, + 4109 => Opcode::FSCALE_ZPmZ_D, + 4110 => Opcode::FSCALE_ZPmZ_H, + 4111 => Opcode::FSCALE_ZPmZ_S, + 4112 => Opcode::FSCALEv2f32, + 4113 => Opcode::FSCALEv2f64, + 4114 => Opcode::FSCALEv4f16, + 4115 => Opcode::FSCALEv4f32, + 4116 => Opcode::FSCALEv8f16, + 4117 => Opcode::FSQRTDr, + 4118 => Opcode::FSQRTHr, + 4119 => Opcode::FSQRTSr, + 4120 => Opcode::FSQRT_ZPZz_D, + 4121 => Opcode::FSQRT_ZPZz_H, + 4122 => Opcode::FSQRT_ZPZz_S, + 4123 => Opcode::FSQRT_ZPmZ_D, + 4124 => Opcode::FSQRT_ZPmZ_H, + 4125 => Opcode::FSQRT_ZPmZ_S, + 4126 => Opcode::FSQRTv2f32, + 4127 => Opcode::FSQRTv2f64, + 4128 => Opcode::FSQRTv4f16, + 4129 => Opcode::FSQRTv4f32, + 4130 => Opcode::FSQRTv8f16, + 4131 => Opcode::FSUBDrr, + 4132 => Opcode::FSUBHrr, + 4133 => Opcode::FSUBR_ZPmI_D, + 4134 => Opcode::FSUBR_ZPmI_H, + 4135 => Opcode::FSUBR_ZPmI_S, + 4136 => Opcode::FSUBR_ZPmZ_D, + 4137 => Opcode::FSUBR_ZPmZ_H, + 4138 => Opcode::FSUBR_ZPmZ_S, + 4139 => Opcode::FSUBSrr, + 4140 => Opcode::FSUB_VG2_M2Z_D, + 4141 => Opcode::FSUB_VG2_M2Z_H, + 4142 => Opcode::FSUB_VG2_M2Z_S, + 4143 => Opcode::FSUB_VG4_M4Z_D, + 4144 => Opcode::FSUB_VG4_M4Z_H, + 4145 => Opcode::FSUB_VG4_M4Z_S, + 4146 => Opcode::FSUB_ZPmI_D, + 4147 => Opcode::FSUB_ZPmI_H, + 4148 => Opcode::FSUB_ZPmI_S, + 4149 => Opcode::FSUB_ZPmZ_D, + 4150 => Opcode::FSUB_ZPmZ_H, + 4151 => Opcode::FSUB_ZPmZ_S, + 4152 => Opcode::FSUB_ZZZ_D, + 4153 => Opcode::FSUB_ZZZ_H, + 4154 => Opcode::FSUB_ZZZ_S, + 4155 => Opcode::FSUBv2f32, + 4156 => Opcode::FSUBv2f64, + 4157 => Opcode::FSUBv4f16, + 4158 => Opcode::FSUBv4f32, + 4159 => Opcode::FSUBv8f16, + 4160 => Opcode::FTMAD_ZZI_D, + 4161 => Opcode::FTMAD_ZZI_H, + 4162 => Opcode::FTMAD_ZZI_S, + 4163 => Opcode::FTMOPA_M2ZZZI_BtoH, + 4164 => Opcode::FTMOPA_M2ZZZI_BtoS, + 4165 => Opcode::FTMOPA_M2ZZZI_HtoH, + 4166 => Opcode::FTMOPA_M2ZZZI_HtoS, + 4167 => Opcode::FTMOPA_M2ZZZI_StoS, + 4168 => Opcode::FTSMUL_ZZZ_D, + 4169 => Opcode::FTSMUL_ZZZ_H, + 4170 => Opcode::FTSMUL_ZZZ_S, + 4171 => Opcode::FTSSEL_ZZZ_D, + 4172 => Opcode::FTSSEL_ZZZ_H, + 4173 => Opcode::FTSSEL_ZZZ_S, + 4174 => Opcode::FVDOTB_VG4_M2ZZI_BtoS, + 4175 => Opcode::FVDOTT_VG4_M2ZZI_BtoS, + 4176 => Opcode::FVDOT_VG2_M2ZZI_BtoH, + 4177 => Opcode::FVDOT_VG2_M2ZZI_HtoS, + 4178 => Opcode::GCSPOPCX, + 4179 => Opcode::GCSPOPM, + 4180 => Opcode::GCSPOPX, + 4181 => Opcode::GCSPUSHM, + 4182 => Opcode::GCSPUSHX, + 4183 => Opcode::GCSSS1, + 4184 => Opcode::GCSSS2, + 4185 => Opcode::GCSSTR, + 4186 => Opcode::GCSSTTR, + 4187 => Opcode::GLD1B_D, + 4188 => Opcode::GLD1B_D_IMM, + 4189 => Opcode::GLD1B_D_SXTW, + 4190 => Opcode::GLD1B_D_UXTW, + 4191 => Opcode::GLD1B_S_IMM, + 4192 => Opcode::GLD1B_S_SXTW, + 4193 => Opcode::GLD1B_S_UXTW, + 4194 => Opcode::GLD1D, + 4195 => Opcode::GLD1D_IMM, + 4196 => Opcode::GLD1D_SCALED, + 4197 => Opcode::GLD1D_SXTW, + 4198 => Opcode::GLD1D_SXTW_SCALED, + 4199 => Opcode::GLD1D_UXTW, + 4200 => Opcode::GLD1D_UXTW_SCALED, + 4201 => Opcode::GLD1H_D, + 4202 => Opcode::GLD1H_D_IMM, + 4203 => Opcode::GLD1H_D_SCALED, + 4204 => Opcode::GLD1H_D_SXTW, + 4205 => Opcode::GLD1H_D_SXTW_SCALED, + 4206 => Opcode::GLD1H_D_UXTW, + 4207 => Opcode::GLD1H_D_UXTW_SCALED, + 4208 => Opcode::GLD1H_S_IMM, + 4209 => Opcode::GLD1H_S_SXTW, + 4210 => Opcode::GLD1H_S_SXTW_SCALED, + 4211 => Opcode::GLD1H_S_UXTW, + 4212 => Opcode::GLD1H_S_UXTW_SCALED, + 4213 => Opcode::GLD1Q, + 4214 => Opcode::GLD1SB_D, + 4215 => Opcode::GLD1SB_D_IMM, + 4216 => Opcode::GLD1SB_D_SXTW, + 4217 => Opcode::GLD1SB_D_UXTW, + 4218 => Opcode::GLD1SB_S_IMM, + 4219 => Opcode::GLD1SB_S_SXTW, + 4220 => Opcode::GLD1SB_S_UXTW, + 4221 => Opcode::GLD1SH_D, + 4222 => Opcode::GLD1SH_D_IMM, + 4223 => Opcode::GLD1SH_D_SCALED, + 4224 => Opcode::GLD1SH_D_SXTW, + 4225 => Opcode::GLD1SH_D_SXTW_SCALED, + 4226 => Opcode::GLD1SH_D_UXTW, + 4227 => Opcode::GLD1SH_D_UXTW_SCALED, + 4228 => Opcode::GLD1SH_S_IMM, + 4229 => Opcode::GLD1SH_S_SXTW, + 4230 => Opcode::GLD1SH_S_SXTW_SCALED, + 4231 => Opcode::GLD1SH_S_UXTW, + 4232 => Opcode::GLD1SH_S_UXTW_SCALED, + 4233 => Opcode::GLD1SW_D, + 4234 => Opcode::GLD1SW_D_IMM, + 4235 => Opcode::GLD1SW_D_SCALED, + 4236 => Opcode::GLD1SW_D_SXTW, + 4237 => Opcode::GLD1SW_D_SXTW_SCALED, + 4238 => Opcode::GLD1SW_D_UXTW, + 4239 => Opcode::GLD1SW_D_UXTW_SCALED, + 4240 => Opcode::GLD1W_D, + 4241 => Opcode::GLD1W_D_IMM, + 4242 => Opcode::GLD1W_D_SCALED, + 4243 => Opcode::GLD1W_D_SXTW, + 4244 => Opcode::GLD1W_D_SXTW_SCALED, + 4245 => Opcode::GLD1W_D_UXTW, + 4246 => Opcode::GLD1W_D_UXTW_SCALED, + 4247 => Opcode::GLD1W_IMM, + 4248 => Opcode::GLD1W_SXTW, + 4249 => Opcode::GLD1W_SXTW_SCALED, + 4250 => Opcode::GLD1W_UXTW, + 4251 => Opcode::GLD1W_UXTW_SCALED, + 4252 => Opcode::GLDFF1B_D, + 4253 => Opcode::GLDFF1B_D_IMM, + 4254 => Opcode::GLDFF1B_D_SXTW, + 4255 => Opcode::GLDFF1B_D_UXTW, + 4256 => Opcode::GLDFF1B_S_IMM, + 4257 => Opcode::GLDFF1B_S_SXTW, + 4258 => Opcode::GLDFF1B_S_UXTW, + 4259 => Opcode::GLDFF1D, + 4260 => Opcode::GLDFF1D_IMM, + 4261 => Opcode::GLDFF1D_SCALED, + 4262 => Opcode::GLDFF1D_SXTW, + 4263 => Opcode::GLDFF1D_SXTW_SCALED, + 4264 => Opcode::GLDFF1D_UXTW, + 4265 => Opcode::GLDFF1D_UXTW_SCALED, + 4266 => Opcode::GLDFF1H_D, + 4267 => Opcode::GLDFF1H_D_IMM, + 4268 => Opcode::GLDFF1H_D_SCALED, + 4269 => Opcode::GLDFF1H_D_SXTW, + 4270 => Opcode::GLDFF1H_D_SXTW_SCALED, + 4271 => Opcode::GLDFF1H_D_UXTW, + 4272 => Opcode::GLDFF1H_D_UXTW_SCALED, + 4273 => Opcode::GLDFF1H_S_IMM, + 4274 => Opcode::GLDFF1H_S_SXTW, + 4275 => Opcode::GLDFF1H_S_SXTW_SCALED, + 4276 => Opcode::GLDFF1H_S_UXTW, + 4277 => Opcode::GLDFF1H_S_UXTW_SCALED, + 4278 => Opcode::GLDFF1SB_D, + 4279 => Opcode::GLDFF1SB_D_IMM, + 4280 => Opcode::GLDFF1SB_D_SXTW, + 4281 => Opcode::GLDFF1SB_D_UXTW, + 4282 => Opcode::GLDFF1SB_S_IMM, + 4283 => Opcode::GLDFF1SB_S_SXTW, + 4284 => Opcode::GLDFF1SB_S_UXTW, + 4285 => Opcode::GLDFF1SH_D, + 4286 => Opcode::GLDFF1SH_D_IMM, + 4287 => Opcode::GLDFF1SH_D_SCALED, + 4288 => Opcode::GLDFF1SH_D_SXTW, + 4289 => Opcode::GLDFF1SH_D_SXTW_SCALED, + 4290 => Opcode::GLDFF1SH_D_UXTW, + 4291 => Opcode::GLDFF1SH_D_UXTW_SCALED, + 4292 => Opcode::GLDFF1SH_S_IMM, + 4293 => Opcode::GLDFF1SH_S_SXTW, + 4294 => Opcode::GLDFF1SH_S_SXTW_SCALED, + 4295 => Opcode::GLDFF1SH_S_UXTW, + 4296 => Opcode::GLDFF1SH_S_UXTW_SCALED, + 4297 => Opcode::GLDFF1SW_D, + 4298 => Opcode::GLDFF1SW_D_IMM, + 4299 => Opcode::GLDFF1SW_D_SCALED, + 4300 => Opcode::GLDFF1SW_D_SXTW, + 4301 => Opcode::GLDFF1SW_D_SXTW_SCALED, + 4302 => Opcode::GLDFF1SW_D_UXTW, + 4303 => Opcode::GLDFF1SW_D_UXTW_SCALED, + 4304 => Opcode::GLDFF1W_D, + 4305 => Opcode::GLDFF1W_D_IMM, + 4306 => Opcode::GLDFF1W_D_SCALED, + 4307 => Opcode::GLDFF1W_D_SXTW, + 4308 => Opcode::GLDFF1W_D_SXTW_SCALED, + 4309 => Opcode::GLDFF1W_D_UXTW, + 4310 => Opcode::GLDFF1W_D_UXTW_SCALED, + 4311 => Opcode::GLDFF1W_IMM, + 4312 => Opcode::GLDFF1W_SXTW, + 4313 => Opcode::GLDFF1W_SXTW_SCALED, + 4314 => Opcode::GLDFF1W_UXTW, + 4315 => Opcode::GLDFF1W_UXTW_SCALED, + 4316 => Opcode::GMI, + 4317 => Opcode::HINT, + 4318 => Opcode::HISTCNT_ZPzZZ_D, + 4319 => Opcode::HISTCNT_ZPzZZ_S, + 4320 => Opcode::HISTSEG_ZZZ, + 4321 => Opcode::HLT, + 4322 => Opcode::HVC, + 4323 => Opcode::INCB_XPiI, + 4324 => Opcode::INCD_XPiI, + 4325 => Opcode::INCD_ZPiI, + 4326 => Opcode::INCH_XPiI, + 4327 => Opcode::INCH_ZPiI, + 4328 => Opcode::INCP_XP_B, + 4329 => Opcode::INCP_XP_D, + 4330 => Opcode::INCP_XP_H, + 4331 => Opcode::INCP_XP_S, + 4332 => Opcode::INCP_ZP_D, + 4333 => Opcode::INCP_ZP_H, + 4334 => Opcode::INCP_ZP_S, + 4335 => Opcode::INCW_XPiI, + 4336 => Opcode::INCW_ZPiI, + 4337 => Opcode::INDEX_II_B, + 4338 => Opcode::INDEX_II_D, + 4339 => Opcode::INDEX_II_H, + 4340 => Opcode::INDEX_II_S, + 4341 => Opcode::INDEX_IR_B, + 4342 => Opcode::INDEX_IR_D, + 4343 => Opcode::INDEX_IR_H, + 4344 => Opcode::INDEX_IR_S, + 4345 => Opcode::INDEX_RI_B, + 4346 => Opcode::INDEX_RI_D, + 4347 => Opcode::INDEX_RI_H, + 4348 => Opcode::INDEX_RI_S, + 4349 => Opcode::INDEX_RR_B, + 4350 => Opcode::INDEX_RR_D, + 4351 => Opcode::INDEX_RR_H, + 4352 => Opcode::INDEX_RR_S, + 4353 => Opcode::INSERT_MXIPZ_H_B, + 4354 => Opcode::INSERT_MXIPZ_H_D, + 4355 => Opcode::INSERT_MXIPZ_H_H, + 4356 => Opcode::INSERT_MXIPZ_H_Q, + 4357 => Opcode::INSERT_MXIPZ_H_S, + 4358 => Opcode::INSERT_MXIPZ_V_B, + 4359 => Opcode::INSERT_MXIPZ_V_D, + 4360 => Opcode::INSERT_MXIPZ_V_H, + 4361 => Opcode::INSERT_MXIPZ_V_Q, + 4362 => Opcode::INSERT_MXIPZ_V_S, + 4363 => Opcode::INSR_ZR_B, + 4364 => Opcode::INSR_ZR_D, + 4365 => Opcode::INSR_ZR_H, + 4366 => Opcode::INSR_ZR_S, + 4367 => Opcode::INSR_ZV_B, + 4368 => Opcode::INSR_ZV_D, + 4369 => Opcode::INSR_ZV_H, + 4370 => Opcode::INSR_ZV_S, + 4371 => Opcode::INSvi16gpr, + 4372 => Opcode::INSvi16lane, + 4373 => Opcode::INSvi32gpr, + 4374 => Opcode::INSvi32lane, + 4375 => Opcode::INSvi64gpr, + 4376 => Opcode::INSvi64lane, + 4377 => Opcode::INSvi8gpr, + 4378 => Opcode::INSvi8lane, + 4379 => Opcode::IRG, + 4380 => Opcode::ISB, + 4381 => Opcode::LASTA_RPZ_B, + 4382 => Opcode::LASTA_RPZ_D, + 4383 => Opcode::LASTA_RPZ_H, + 4384 => Opcode::LASTA_RPZ_S, + 4385 => Opcode::LASTA_VPZ_B, + 4386 => Opcode::LASTA_VPZ_D, + 4387 => Opcode::LASTA_VPZ_H, + 4388 => Opcode::LASTA_VPZ_S, + 4389 => Opcode::LASTB_RPZ_B, + 4390 => Opcode::LASTB_RPZ_D, + 4391 => Opcode::LASTB_RPZ_H, + 4392 => Opcode::LASTB_RPZ_S, + 4393 => Opcode::LASTB_VPZ_B, + 4394 => Opcode::LASTB_VPZ_D, + 4395 => Opcode::LASTB_VPZ_H, + 4396 => Opcode::LASTB_VPZ_S, + 4397 => Opcode::LASTP_XPP_B, + 4398 => Opcode::LASTP_XPP_D, + 4399 => Opcode::LASTP_XPP_H, + 4400 => Opcode::LASTP_XPP_S, + 4401 => Opcode::LD1B, + 4402 => Opcode::LD1B_2Z, + 4403 => Opcode::LD1B_2Z_IMM, + 4404 => Opcode::LD1B_2Z_STRIDED, + 4405 => Opcode::LD1B_2Z_STRIDED_IMM, + 4406 => Opcode::LD1B_4Z, + 4407 => Opcode::LD1B_4Z_IMM, + 4408 => Opcode::LD1B_4Z_STRIDED, + 4409 => Opcode::LD1B_4Z_STRIDED_IMM, + 4410 => Opcode::LD1B_D, + 4411 => Opcode::LD1B_D_IMM, + 4412 => Opcode::LD1B_H, + 4413 => Opcode::LD1B_H_IMM, + 4414 => Opcode::LD1B_IMM, + 4415 => Opcode::LD1B_S, + 4416 => Opcode::LD1B_S_IMM, + 4417 => Opcode::LD1D, + 4418 => Opcode::LD1D_2Z, + 4419 => Opcode::LD1D_2Z_IMM, + 4420 => Opcode::LD1D_2Z_STRIDED, + 4421 => Opcode::LD1D_2Z_STRIDED_IMM, + 4422 => Opcode::LD1D_4Z, + 4423 => Opcode::LD1D_4Z_IMM, + 4424 => Opcode::LD1D_4Z_STRIDED, + 4425 => Opcode::LD1D_4Z_STRIDED_IMM, + 4426 => Opcode::LD1D_IMM, + 4427 => Opcode::LD1D_Q, + 4428 => Opcode::LD1D_Q_IMM, + 4429 => Opcode::LD1Fourv16b, + 4430 => Opcode::LD1Fourv16b_POST, + 4431 => Opcode::LD1Fourv1d, + 4432 => Opcode::LD1Fourv1d_POST, + 4433 => Opcode::LD1Fourv2d, + 4434 => Opcode::LD1Fourv2d_POST, + 4435 => Opcode::LD1Fourv2s, + 4436 => Opcode::LD1Fourv2s_POST, + 4437 => Opcode::LD1Fourv4h, + 4438 => Opcode::LD1Fourv4h_POST, + 4439 => Opcode::LD1Fourv4s, + 4440 => Opcode::LD1Fourv4s_POST, + 4441 => Opcode::LD1Fourv8b, + 4442 => Opcode::LD1Fourv8b_POST, + 4443 => Opcode::LD1Fourv8h, + 4444 => Opcode::LD1Fourv8h_POST, + 4445 => Opcode::LD1H, + 4446 => Opcode::LD1H_2Z, + 4447 => Opcode::LD1H_2Z_IMM, + 4448 => Opcode::LD1H_2Z_STRIDED, + 4449 => Opcode::LD1H_2Z_STRIDED_IMM, + 4450 => Opcode::LD1H_4Z, + 4451 => Opcode::LD1H_4Z_IMM, + 4452 => Opcode::LD1H_4Z_STRIDED, + 4453 => Opcode::LD1H_4Z_STRIDED_IMM, + 4454 => Opcode::LD1H_D, + 4455 => Opcode::LD1H_D_IMM, + 4456 => Opcode::LD1H_IMM, + 4457 => Opcode::LD1H_S, + 4458 => Opcode::LD1H_S_IMM, + 4459 => Opcode::LD1Onev16b, + 4460 => Opcode::LD1Onev16b_POST, + 4461 => Opcode::LD1Onev1d, + 4462 => Opcode::LD1Onev1d_POST, + 4463 => Opcode::LD1Onev2d, + 4464 => Opcode::LD1Onev2d_POST, + 4465 => Opcode::LD1Onev2s, + 4466 => Opcode::LD1Onev2s_POST, + 4467 => Opcode::LD1Onev4h, + 4468 => Opcode::LD1Onev4h_POST, + 4469 => Opcode::LD1Onev4s, + 4470 => Opcode::LD1Onev4s_POST, + 4471 => Opcode::LD1Onev8b, + 4472 => Opcode::LD1Onev8b_POST, + 4473 => Opcode::LD1Onev8h, + 4474 => Opcode::LD1Onev8h_POST, + 4475 => Opcode::LD1RB_D_IMM, + 4476 => Opcode::LD1RB_H_IMM, + 4477 => Opcode::LD1RB_IMM, + 4478 => Opcode::LD1RB_S_IMM, + 4479 => Opcode::LD1RD_IMM, + 4480 => Opcode::LD1RH_D_IMM, + 4481 => Opcode::LD1RH_IMM, + 4482 => Opcode::LD1RH_S_IMM, + 4483 => Opcode::LD1RO_B, + 4484 => Opcode::LD1RO_B_IMM, + 4485 => Opcode::LD1RO_D, + 4486 => Opcode::LD1RO_D_IMM, + 4487 => Opcode::LD1RO_H, + 4488 => Opcode::LD1RO_H_IMM, + 4489 => Opcode::LD1RO_W, + 4490 => Opcode::LD1RO_W_IMM, + 4491 => Opcode::LD1RQ_B, + 4492 => Opcode::LD1RQ_B_IMM, + 4493 => Opcode::LD1RQ_D, + 4494 => Opcode::LD1RQ_D_IMM, + 4495 => Opcode::LD1RQ_H, + 4496 => Opcode::LD1RQ_H_IMM, + 4497 => Opcode::LD1RQ_W, + 4498 => Opcode::LD1RQ_W_IMM, + 4499 => Opcode::LD1RSB_D_IMM, + 4500 => Opcode::LD1RSB_H_IMM, + 4501 => Opcode::LD1RSB_S_IMM, + 4502 => Opcode::LD1RSH_D_IMM, + 4503 => Opcode::LD1RSH_S_IMM, + 4504 => Opcode::LD1RSW_IMM, + 4505 => Opcode::LD1RW_D_IMM, + 4506 => Opcode::LD1RW_IMM, + 4507 => Opcode::LD1Rv16b, + 4508 => Opcode::LD1Rv16b_POST, + 4509 => Opcode::LD1Rv1d, + 4510 => Opcode::LD1Rv1d_POST, + 4511 => Opcode::LD1Rv2d, + 4512 => Opcode::LD1Rv2d_POST, + 4513 => Opcode::LD1Rv2s, + 4514 => Opcode::LD1Rv2s_POST, + 4515 => Opcode::LD1Rv4h, + 4516 => Opcode::LD1Rv4h_POST, + 4517 => Opcode::LD1Rv4s, + 4518 => Opcode::LD1Rv4s_POST, + 4519 => Opcode::LD1Rv8b, + 4520 => Opcode::LD1Rv8b_POST, + 4521 => Opcode::LD1Rv8h, + 4522 => Opcode::LD1Rv8h_POST, + 4523 => Opcode::LD1SB_D, + 4524 => Opcode::LD1SB_D_IMM, + 4525 => Opcode::LD1SB_H, + 4526 => Opcode::LD1SB_H_IMM, + 4527 => Opcode::LD1SB_S, + 4528 => Opcode::LD1SB_S_IMM, + 4529 => Opcode::LD1SH_D, + 4530 => Opcode::LD1SH_D_IMM, + 4531 => Opcode::LD1SH_S, + 4532 => Opcode::LD1SH_S_IMM, + 4533 => Opcode::LD1SW_D, + 4534 => Opcode::LD1SW_D_IMM, + 4535 => Opcode::LD1Threev16b, + 4536 => Opcode::LD1Threev16b_POST, + 4537 => Opcode::LD1Threev1d, + 4538 => Opcode::LD1Threev1d_POST, + 4539 => Opcode::LD1Threev2d, + 4540 => Opcode::LD1Threev2d_POST, + 4541 => Opcode::LD1Threev2s, + 4542 => Opcode::LD1Threev2s_POST, + 4543 => Opcode::LD1Threev4h, + 4544 => Opcode::LD1Threev4h_POST, + 4545 => Opcode::LD1Threev4s, + 4546 => Opcode::LD1Threev4s_POST, + 4547 => Opcode::LD1Threev8b, + 4548 => Opcode::LD1Threev8b_POST, + 4549 => Opcode::LD1Threev8h, + 4550 => Opcode::LD1Threev8h_POST, + 4551 => Opcode::LD1Twov16b, + 4552 => Opcode::LD1Twov16b_POST, + 4553 => Opcode::LD1Twov1d, + 4554 => Opcode::LD1Twov1d_POST, + 4555 => Opcode::LD1Twov2d, + 4556 => Opcode::LD1Twov2d_POST, + 4557 => Opcode::LD1Twov2s, + 4558 => Opcode::LD1Twov2s_POST, + 4559 => Opcode::LD1Twov4h, + 4560 => Opcode::LD1Twov4h_POST, + 4561 => Opcode::LD1Twov4s, + 4562 => Opcode::LD1Twov4s_POST, + 4563 => Opcode::LD1Twov8b, + 4564 => Opcode::LD1Twov8b_POST, + 4565 => Opcode::LD1Twov8h, + 4566 => Opcode::LD1Twov8h_POST, + 4567 => Opcode::LD1W, + 4568 => Opcode::LD1W_2Z, + 4569 => Opcode::LD1W_2Z_IMM, + 4570 => Opcode::LD1W_2Z_STRIDED, + 4571 => Opcode::LD1W_2Z_STRIDED_IMM, + 4572 => Opcode::LD1W_4Z, + 4573 => Opcode::LD1W_4Z_IMM, + 4574 => Opcode::LD1W_4Z_STRIDED, + 4575 => Opcode::LD1W_4Z_STRIDED_IMM, + 4576 => Opcode::LD1W_D, + 4577 => Opcode::LD1W_D_IMM, + 4578 => Opcode::LD1W_IMM, + 4579 => Opcode::LD1W_Q, + 4580 => Opcode::LD1W_Q_IMM, + 4581 => Opcode::LD1_MXIPXX_H_B, + 4582 => Opcode::LD1_MXIPXX_H_D, + 4583 => Opcode::LD1_MXIPXX_H_H, + 4584 => Opcode::LD1_MXIPXX_H_Q, + 4585 => Opcode::LD1_MXIPXX_H_S, + 4586 => Opcode::LD1_MXIPXX_V_B, + 4587 => Opcode::LD1_MXIPXX_V_D, + 4588 => Opcode::LD1_MXIPXX_V_H, + 4589 => Opcode::LD1_MXIPXX_V_Q, + 4590 => Opcode::LD1_MXIPXX_V_S, + 4591 => Opcode::LD1i16, + 4592 => Opcode::LD1i16_POST, + 4593 => Opcode::LD1i32, + 4594 => Opcode::LD1i32_POST, + 4595 => Opcode::LD1i64, + 4596 => Opcode::LD1i64_POST, + 4597 => Opcode::LD1i8, + 4598 => Opcode::LD1i8_POST, + 4599 => Opcode::LD2B, + 4600 => Opcode::LD2B_IMM, + 4601 => Opcode::LD2D, + 4602 => Opcode::LD2D_IMM, + 4603 => Opcode::LD2H, + 4604 => Opcode::LD2H_IMM, + 4605 => Opcode::LD2Q, + 4606 => Opcode::LD2Q_IMM, + 4607 => Opcode::LD2Rv16b, + 4608 => Opcode::LD2Rv16b_POST, + 4609 => Opcode::LD2Rv1d, + 4610 => Opcode::LD2Rv1d_POST, + 4611 => Opcode::LD2Rv2d, + 4612 => Opcode::LD2Rv2d_POST, + 4613 => Opcode::LD2Rv2s, + 4614 => Opcode::LD2Rv2s_POST, + 4615 => Opcode::LD2Rv4h, + 4616 => Opcode::LD2Rv4h_POST, + 4617 => Opcode::LD2Rv4s, + 4618 => Opcode::LD2Rv4s_POST, + 4619 => Opcode::LD2Rv8b, + 4620 => Opcode::LD2Rv8b_POST, + 4621 => Opcode::LD2Rv8h, + 4622 => Opcode::LD2Rv8h_POST, + 4623 => Opcode::LD2Twov16b, + 4624 => Opcode::LD2Twov16b_POST, + 4625 => Opcode::LD2Twov2d, + 4626 => Opcode::LD2Twov2d_POST, + 4627 => Opcode::LD2Twov2s, + 4628 => Opcode::LD2Twov2s_POST, + 4629 => Opcode::LD2Twov4h, + 4630 => Opcode::LD2Twov4h_POST, + 4631 => Opcode::LD2Twov4s, + 4632 => Opcode::LD2Twov4s_POST, + 4633 => Opcode::LD2Twov8b, + 4634 => Opcode::LD2Twov8b_POST, + 4635 => Opcode::LD2Twov8h, + 4636 => Opcode::LD2Twov8h_POST, + 4637 => Opcode::LD2W, + 4638 => Opcode::LD2W_IMM, + 4639 => Opcode::LD2i16, + 4640 => Opcode::LD2i16_POST, + 4641 => Opcode::LD2i32, + 4642 => Opcode::LD2i32_POST, + 4643 => Opcode::LD2i64, + 4644 => Opcode::LD2i64_POST, + 4645 => Opcode::LD2i8, + 4646 => Opcode::LD2i8_POST, + 4647 => Opcode::LD3B, + 4648 => Opcode::LD3B_IMM, + 4649 => Opcode::LD3D, + 4650 => Opcode::LD3D_IMM, + 4651 => Opcode::LD3H, + 4652 => Opcode::LD3H_IMM, + 4653 => Opcode::LD3Q, + 4654 => Opcode::LD3Q_IMM, + 4655 => Opcode::LD3Rv16b, + 4656 => Opcode::LD3Rv16b_POST, + 4657 => Opcode::LD3Rv1d, + 4658 => Opcode::LD3Rv1d_POST, + 4659 => Opcode::LD3Rv2d, + 4660 => Opcode::LD3Rv2d_POST, + 4661 => Opcode::LD3Rv2s, + 4662 => Opcode::LD3Rv2s_POST, + 4663 => Opcode::LD3Rv4h, + 4664 => Opcode::LD3Rv4h_POST, + 4665 => Opcode::LD3Rv4s, + 4666 => Opcode::LD3Rv4s_POST, + 4667 => Opcode::LD3Rv8b, + 4668 => Opcode::LD3Rv8b_POST, + 4669 => Opcode::LD3Rv8h, + 4670 => Opcode::LD3Rv8h_POST, + 4671 => Opcode::LD3Threev16b, + 4672 => Opcode::LD3Threev16b_POST, + 4673 => Opcode::LD3Threev2d, + 4674 => Opcode::LD3Threev2d_POST, + 4675 => Opcode::LD3Threev2s, + 4676 => Opcode::LD3Threev2s_POST, + 4677 => Opcode::LD3Threev4h, + 4678 => Opcode::LD3Threev4h_POST, + 4679 => Opcode::LD3Threev4s, + 4680 => Opcode::LD3Threev4s_POST, + 4681 => Opcode::LD3Threev8b, + 4682 => Opcode::LD3Threev8b_POST, + 4683 => Opcode::LD3Threev8h, + 4684 => Opcode::LD3Threev8h_POST, + 4685 => Opcode::LD3W, + 4686 => Opcode::LD3W_IMM, + 4687 => Opcode::LD3i16, + 4688 => Opcode::LD3i16_POST, + 4689 => Opcode::LD3i32, + 4690 => Opcode::LD3i32_POST, + 4691 => Opcode::LD3i64, + 4692 => Opcode::LD3i64_POST, + 4693 => Opcode::LD3i8, + 4694 => Opcode::LD3i8_POST, + 4695 => Opcode::LD4B, + 4696 => Opcode::LD4B_IMM, + 4697 => Opcode::LD4D, + 4698 => Opcode::LD4D_IMM, + 4699 => Opcode::LD4Fourv16b, + 4700 => Opcode::LD4Fourv16b_POST, + 4701 => Opcode::LD4Fourv2d, + 4702 => Opcode::LD4Fourv2d_POST, + 4703 => Opcode::LD4Fourv2s, + 4704 => Opcode::LD4Fourv2s_POST, + 4705 => Opcode::LD4Fourv4h, + 4706 => Opcode::LD4Fourv4h_POST, + 4707 => Opcode::LD4Fourv4s, + 4708 => Opcode::LD4Fourv4s_POST, + 4709 => Opcode::LD4Fourv8b, + 4710 => Opcode::LD4Fourv8b_POST, + 4711 => Opcode::LD4Fourv8h, + 4712 => Opcode::LD4Fourv8h_POST, + 4713 => Opcode::LD4H, + 4714 => Opcode::LD4H_IMM, + 4715 => Opcode::LD4Q, + 4716 => Opcode::LD4Q_IMM, + 4717 => Opcode::LD4Rv16b, + 4718 => Opcode::LD4Rv16b_POST, + 4719 => Opcode::LD4Rv1d, + 4720 => Opcode::LD4Rv1d_POST, + 4721 => Opcode::LD4Rv2d, + 4722 => Opcode::LD4Rv2d_POST, + 4723 => Opcode::LD4Rv2s, + 4724 => Opcode::LD4Rv2s_POST, + 4725 => Opcode::LD4Rv4h, + 4726 => Opcode::LD4Rv4h_POST, + 4727 => Opcode::LD4Rv4s, + 4728 => Opcode::LD4Rv4s_POST, + 4729 => Opcode::LD4Rv8b, + 4730 => Opcode::LD4Rv8b_POST, + 4731 => Opcode::LD4Rv8h, + 4732 => Opcode::LD4Rv8h_POST, + 4733 => Opcode::LD4W, + 4734 => Opcode::LD4W_IMM, + 4735 => Opcode::LD4i16, + 4736 => Opcode::LD4i16_POST, + 4737 => Opcode::LD4i32, + 4738 => Opcode::LD4i32_POST, + 4739 => Opcode::LD4i64, + 4740 => Opcode::LD4i64_POST, + 4741 => Opcode::LD4i8, + 4742 => Opcode::LD4i8_POST, + 4743 => Opcode::LD64B, + 4744 => Opcode::LDADDAB, + 4745 => Opcode::LDADDAH, + 4746 => Opcode::LDADDALB, + 4747 => Opcode::LDADDALH, + 4748 => Opcode::LDADDALW, + 4749 => Opcode::LDADDALX, + 4750 => Opcode::LDADDAW, + 4751 => Opcode::LDADDAX, + 4752 => Opcode::LDADDB, + 4753 => Opcode::LDADDH, + 4754 => Opcode::LDADDLB, + 4755 => Opcode::LDADDLH, + 4756 => Opcode::LDADDLW, + 4757 => Opcode::LDADDLX, + 4758 => Opcode::LDADDW, + 4759 => Opcode::LDADDX, + 4760 => Opcode::LDAP1, + 4761 => Opcode::LDAPPi, + 4762 => Opcode::LDAPRB, + 4763 => Opcode::LDAPRH, + 4764 => Opcode::LDAPRW, + 4765 => Opcode::LDAPRWpost, + 4766 => Opcode::LDAPRX, + 4767 => Opcode::LDAPRXpost, + 4768 => Opcode::LDAPURBi, + 4769 => Opcode::LDAPURHi, + 4770 => Opcode::LDAPURSBWi, + 4771 => Opcode::LDAPURSBXi, + 4772 => Opcode::LDAPURSHWi, + 4773 => Opcode::LDAPURSHXi, + 4774 => Opcode::LDAPURSWi, + 4775 => Opcode::LDAPURXi, + 4776 => Opcode::LDAPURbi, + 4777 => Opcode::LDAPURdi, + 4778 => Opcode::LDAPURhi, + 4779 => Opcode::LDAPURi, + 4780 => Opcode::LDAPURqi, + 4781 => Opcode::LDAPURsi, + 4782 => Opcode::LDAPi, + 4783 => Opcode::LDARB, + 4784 => Opcode::LDARH, + 4785 => Opcode::LDARW, + 4786 => Opcode::LDARX, + 4787 => Opcode::LDATXRW, + 4788 => Opcode::LDATXRX, + 4789 => Opcode::LDAXPW, + 4790 => Opcode::LDAXPX, + 4791 => Opcode::LDAXRB, + 4792 => Opcode::LDAXRH, + 4793 => Opcode::LDAXRW, + 4794 => Opcode::LDAXRX, + 4795 => Opcode::LDBFADD, + 4796 => Opcode::LDBFADDA, + 4797 => Opcode::LDBFADDAL, + 4798 => Opcode::LDBFADDL, + 4799 => Opcode::LDBFMAX, + 4800 => Opcode::LDBFMAXA, + 4801 => Opcode::LDBFMAXAL, + 4802 => Opcode::LDBFMAXL, + 4803 => Opcode::LDBFMAXNM, + 4804 => Opcode::LDBFMAXNMA, + 4805 => Opcode::LDBFMAXNMAL, + 4806 => Opcode::LDBFMAXNML, + 4807 => Opcode::LDBFMIN, + 4808 => Opcode::LDBFMINA, + 4809 => Opcode::LDBFMINAL, + 4810 => Opcode::LDBFMINL, + 4811 => Opcode::LDBFMINNM, + 4812 => Opcode::LDBFMINNMA, + 4813 => Opcode::LDBFMINNMAL, + 4814 => Opcode::LDBFMINNML, + 4815 => Opcode::LDCLRAB, + 4816 => Opcode::LDCLRAH, + 4817 => Opcode::LDCLRALB, + 4818 => Opcode::LDCLRALH, + 4819 => Opcode::LDCLRALW, + 4820 => Opcode::LDCLRALX, + 4821 => Opcode::LDCLRAW, + 4822 => Opcode::LDCLRAX, + 4823 => Opcode::LDCLRB, + 4824 => Opcode::LDCLRH, + 4825 => Opcode::LDCLRLB, + 4826 => Opcode::LDCLRLH, + 4827 => Opcode::LDCLRLW, + 4828 => Opcode::LDCLRLX, + 4829 => Opcode::LDCLRP, + 4830 => Opcode::LDCLRPA, + 4831 => Opcode::LDCLRPAL, + 4832 => Opcode::LDCLRPL, + 4833 => Opcode::LDCLRW, + 4834 => Opcode::LDCLRX, + 4835 => Opcode::LDEORAB, + 4836 => Opcode::LDEORAH, + 4837 => Opcode::LDEORALB, + 4838 => Opcode::LDEORALH, + 4839 => Opcode::LDEORALW, + 4840 => Opcode::LDEORALX, + 4841 => Opcode::LDEORAW, + 4842 => Opcode::LDEORAX, + 4843 => Opcode::LDEORB, + 4844 => Opcode::LDEORH, + 4845 => Opcode::LDEORLB, + 4846 => Opcode::LDEORLH, + 4847 => Opcode::LDEORLW, + 4848 => Opcode::LDEORLX, + 4849 => Opcode::LDEORW, + 4850 => Opcode::LDEORX, + 4851 => Opcode::LDFADDAD, + 4852 => Opcode::LDFADDAH, + 4853 => Opcode::LDFADDALD, + 4854 => Opcode::LDFADDALH, + 4855 => Opcode::LDFADDALS, + 4856 => Opcode::LDFADDAS, + 4857 => Opcode::LDFADDD, + 4858 => Opcode::LDFADDH, + 4859 => Opcode::LDFADDLD, + 4860 => Opcode::LDFADDLH, + 4861 => Opcode::LDFADDLS, + 4862 => Opcode::LDFADDS, + 4863 => Opcode::LDFF1B, + 4864 => Opcode::LDFF1B_D, + 4865 => Opcode::LDFF1B_H, + 4866 => Opcode::LDFF1B_S, + 4867 => Opcode::LDFF1D, + 4868 => Opcode::LDFF1H, + 4869 => Opcode::LDFF1H_D, + 4870 => Opcode::LDFF1H_S, + 4871 => Opcode::LDFF1SB_D, + 4872 => Opcode::LDFF1SB_H, + 4873 => Opcode::LDFF1SB_S, + 4874 => Opcode::LDFF1SH_D, + 4875 => Opcode::LDFF1SH_S, + 4876 => Opcode::LDFF1SW_D, + 4877 => Opcode::LDFF1W, + 4878 => Opcode::LDFF1W_D, + 4879 => Opcode::LDFMAXAD, + 4880 => Opcode::LDFMAXAH, + 4881 => Opcode::LDFMAXALD, + 4882 => Opcode::LDFMAXALH, + 4883 => Opcode::LDFMAXALS, + 4884 => Opcode::LDFMAXAS, + 4885 => Opcode::LDFMAXD, + 4886 => Opcode::LDFMAXH, + 4887 => Opcode::LDFMAXLD, + 4888 => Opcode::LDFMAXLH, + 4889 => Opcode::LDFMAXLS, + 4890 => Opcode::LDFMAXNMAD, + 4891 => Opcode::LDFMAXNMAH, + 4892 => Opcode::LDFMAXNMALD, + 4893 => Opcode::LDFMAXNMALH, + 4894 => Opcode::LDFMAXNMALS, + 4895 => Opcode::LDFMAXNMAS, + 4896 => Opcode::LDFMAXNMD, + 4897 => Opcode::LDFMAXNMH, + 4898 => Opcode::LDFMAXNMLD, + 4899 => Opcode::LDFMAXNMLH, + 4900 => Opcode::LDFMAXNMLS, + 4901 => Opcode::LDFMAXNMS, + 4902 => Opcode::LDFMAXS, + 4903 => Opcode::LDFMINAD, + 4904 => Opcode::LDFMINAH, + 4905 => Opcode::LDFMINALD, + 4906 => Opcode::LDFMINALH, + 4907 => Opcode::LDFMINALS, + 4908 => Opcode::LDFMINAS, + 4909 => Opcode::LDFMIND, + 4910 => Opcode::LDFMINH, + 4911 => Opcode::LDFMINLD, + 4912 => Opcode::LDFMINLH, + 4913 => Opcode::LDFMINLS, + 4914 => Opcode::LDFMINNMAD, + 4915 => Opcode::LDFMINNMAH, + 4916 => Opcode::LDFMINNMALD, + 4917 => Opcode::LDFMINNMALH, + 4918 => Opcode::LDFMINNMALS, + 4919 => Opcode::LDFMINNMAS, + 4920 => Opcode::LDFMINNMD, + 4921 => Opcode::LDFMINNMH, + 4922 => Opcode::LDFMINNMLD, + 4923 => Opcode::LDFMINNMLH, + 4924 => Opcode::LDFMINNMLS, + 4925 => Opcode::LDFMINNMS, + 4926 => Opcode::LDFMINS, + 4927 => Opcode::LDG, + 4928 => Opcode::LDGM, + 4929 => Opcode::LDIAPPW, + 4930 => Opcode::LDIAPPWpost, + 4931 => Opcode::LDIAPPX, + 4932 => Opcode::LDIAPPXpost, + 4933 => Opcode::LDLARB, + 4934 => Opcode::LDLARH, + 4935 => Opcode::LDLARW, + 4936 => Opcode::LDLARX, + 4937 => Opcode::LDNF1B_D_IMM, + 4938 => Opcode::LDNF1B_H_IMM, + 4939 => Opcode::LDNF1B_IMM, + 4940 => Opcode::LDNF1B_S_IMM, + 4941 => Opcode::LDNF1D_IMM, + 4942 => Opcode::LDNF1H_D_IMM, + 4943 => Opcode::LDNF1H_IMM, + 4944 => Opcode::LDNF1H_S_IMM, + 4945 => Opcode::LDNF1SB_D_IMM, + 4946 => Opcode::LDNF1SB_H_IMM, + 4947 => Opcode::LDNF1SB_S_IMM, + 4948 => Opcode::LDNF1SH_D_IMM, + 4949 => Opcode::LDNF1SH_S_IMM, + 4950 => Opcode::LDNF1SW_D_IMM, + 4951 => Opcode::LDNF1W_D_IMM, + 4952 => Opcode::LDNF1W_IMM, + 4953 => Opcode::LDNPDi, + 4954 => Opcode::LDNPQi, + 4955 => Opcode::LDNPSi, + 4956 => Opcode::LDNPWi, + 4957 => Opcode::LDNPXi, + 4958 => Opcode::LDNT1B_2Z, + 4959 => Opcode::LDNT1B_2Z_IMM, + 4960 => Opcode::LDNT1B_2Z_STRIDED, + 4961 => Opcode::LDNT1B_2Z_STRIDED_IMM, + 4962 => Opcode::LDNT1B_4Z, + 4963 => Opcode::LDNT1B_4Z_IMM, + 4964 => Opcode::LDNT1B_4Z_STRIDED, + 4965 => Opcode::LDNT1B_4Z_STRIDED_IMM, + 4966 => Opcode::LDNT1B_ZRI, + 4967 => Opcode::LDNT1B_ZRR, + 4968 => Opcode::LDNT1B_ZZR_D, + 4969 => Opcode::LDNT1B_ZZR_S, + 4970 => Opcode::LDNT1D_2Z, + 4971 => Opcode::LDNT1D_2Z_IMM, + 4972 => Opcode::LDNT1D_2Z_STRIDED, + 4973 => Opcode::LDNT1D_2Z_STRIDED_IMM, + 4974 => Opcode::LDNT1D_4Z, + 4975 => Opcode::LDNT1D_4Z_IMM, + 4976 => Opcode::LDNT1D_4Z_STRIDED, + 4977 => Opcode::LDNT1D_4Z_STRIDED_IMM, + 4978 => Opcode::LDNT1D_ZRI, + 4979 => Opcode::LDNT1D_ZRR, + 4980 => Opcode::LDNT1D_ZZR_D, + 4981 => Opcode::LDNT1H_2Z, + 4982 => Opcode::LDNT1H_2Z_IMM, + 4983 => Opcode::LDNT1H_2Z_STRIDED, + 4984 => Opcode::LDNT1H_2Z_STRIDED_IMM, + 4985 => Opcode::LDNT1H_4Z, + 4986 => Opcode::LDNT1H_4Z_IMM, + 4987 => Opcode::LDNT1H_4Z_STRIDED, + 4988 => Opcode::LDNT1H_4Z_STRIDED_IMM, + 4989 => Opcode::LDNT1H_ZRI, + 4990 => Opcode::LDNT1H_ZRR, + 4991 => Opcode::LDNT1H_ZZR_D, + 4992 => Opcode::LDNT1H_ZZR_S, + 4993 => Opcode::LDNT1SB_ZZR_D, + 4994 => Opcode::LDNT1SB_ZZR_S, + 4995 => Opcode::LDNT1SH_ZZR_D, + 4996 => Opcode::LDNT1SH_ZZR_S, + 4997 => Opcode::LDNT1SW_ZZR_D, + 4998 => Opcode::LDNT1W_2Z, + 4999 => Opcode::LDNT1W_2Z_IMM, + 5000 => Opcode::LDNT1W_2Z_STRIDED, + 5001 => Opcode::LDNT1W_2Z_STRIDED_IMM, + 5002 => Opcode::LDNT1W_4Z, + 5003 => Opcode::LDNT1W_4Z_IMM, + 5004 => Opcode::LDNT1W_4Z_STRIDED, + 5005 => Opcode::LDNT1W_4Z_STRIDED_IMM, + 5006 => Opcode::LDNT1W_ZRI, + 5007 => Opcode::LDNT1W_ZRR, + 5008 => Opcode::LDNT1W_ZZR_D, + 5009 => Opcode::LDNT1W_ZZR_S, + 5010 => Opcode::LDPDi, + 5011 => Opcode::LDPDpost, + 5012 => Opcode::LDPDpre, + 5013 => Opcode::LDPQi, + 5014 => Opcode::LDPQpost, + 5015 => Opcode::LDPQpre, + 5016 => Opcode::LDPSWi, + 5017 => Opcode::LDPSWpost, + 5018 => Opcode::LDPSWpre, + 5019 => Opcode::LDPSi, + 5020 => Opcode::LDPSpost, + 5021 => Opcode::LDPSpre, + 5022 => Opcode::LDPWi, + 5023 => Opcode::LDPWpost, + 5024 => Opcode::LDPWpre, + 5025 => Opcode::LDPXi, + 5026 => Opcode::LDPXpost, + 5027 => Opcode::LDPXpre, + 5028 => Opcode::LDRAAindexed, + 5029 => Opcode::LDRAAwriteback, + 5030 => Opcode::LDRABindexed, + 5031 => Opcode::LDRABwriteback, + 5032 => Opcode::LDRBBpost, + 5033 => Opcode::LDRBBpre, + 5034 => Opcode::LDRBBroW, + 5035 => Opcode::LDRBBroX, + 5036 => Opcode::LDRBBui, + 5037 => Opcode::LDRBpost, + 5038 => Opcode::LDRBpre, + 5039 => Opcode::LDRBroW, + 5040 => Opcode::LDRBroX, + 5041 => Opcode::LDRBui, + 5042 => Opcode::LDRDl, + 5043 => Opcode::LDRDpost, + 5044 => Opcode::LDRDpre, + 5045 => Opcode::LDRDroW, + 5046 => Opcode::LDRDroX, + 5047 => Opcode::LDRDui, + 5048 => Opcode::LDRHHpost, + 5049 => Opcode::LDRHHpre, + 5050 => Opcode::LDRHHroW, + 5051 => Opcode::LDRHHroX, + 5052 => Opcode::LDRHHui, + 5053 => Opcode::LDRHpost, + 5054 => Opcode::LDRHpre, + 5055 => Opcode::LDRHroW, + 5056 => Opcode::LDRHroX, + 5057 => Opcode::LDRHui, + 5058 => Opcode::LDRQl, + 5059 => Opcode::LDRQpost, + 5060 => Opcode::LDRQpre, + 5061 => Opcode::LDRQroW, + 5062 => Opcode::LDRQroX, + 5063 => Opcode::LDRQui, + 5064 => Opcode::LDRSBWpost, + 5065 => Opcode::LDRSBWpre, + 5066 => Opcode::LDRSBWroW, + 5067 => Opcode::LDRSBWroX, + 5068 => Opcode::LDRSBWui, + 5069 => Opcode::LDRSBXpost, + 5070 => Opcode::LDRSBXpre, + 5071 => Opcode::LDRSBXroW, + 5072 => Opcode::LDRSBXroX, + 5073 => Opcode::LDRSBXui, + 5074 => Opcode::LDRSHWpost, + 5075 => Opcode::LDRSHWpre, + 5076 => Opcode::LDRSHWroW, + 5077 => Opcode::LDRSHWroX, + 5078 => Opcode::LDRSHWui, + 5079 => Opcode::LDRSHXpost, + 5080 => Opcode::LDRSHXpre, + 5081 => Opcode::LDRSHXroW, + 5082 => Opcode::LDRSHXroX, + 5083 => Opcode::LDRSHXui, + 5084 => Opcode::LDRSWl, + 5085 => Opcode::LDRSWpost, + 5086 => Opcode::LDRSWpre, + 5087 => Opcode::LDRSWroW, + 5088 => Opcode::LDRSWroX, + 5089 => Opcode::LDRSWui, + 5090 => Opcode::LDRSl, + 5091 => Opcode::LDRSpost, + 5092 => Opcode::LDRSpre, + 5093 => Opcode::LDRSroW, + 5094 => Opcode::LDRSroX, + 5095 => Opcode::LDRSui, + 5096 => Opcode::LDRWl, + 5097 => Opcode::LDRWpost, + 5098 => Opcode::LDRWpre, + 5099 => Opcode::LDRWroW, + 5100 => Opcode::LDRWroX, + 5101 => Opcode::LDRWui, + 5102 => Opcode::LDRXl, + 5103 => Opcode::LDRXpost, + 5104 => Opcode::LDRXpre, + 5105 => Opcode::LDRXroW, + 5106 => Opcode::LDRXroX, + 5107 => Opcode::LDRXui, + 5108 => Opcode::LDR_PXI, + 5109 => Opcode::LDR_TX, + 5110 => Opcode::LDR_ZA, + 5111 => Opcode::LDR_ZXI, + 5112 => Opcode::LDSETAB, + 5113 => Opcode::LDSETAH, + 5114 => Opcode::LDSETALB, + 5115 => Opcode::LDSETALH, + 5116 => Opcode::LDSETALW, + 5117 => Opcode::LDSETALX, + 5118 => Opcode::LDSETAW, + 5119 => Opcode::LDSETAX, + 5120 => Opcode::LDSETB, + 5121 => Opcode::LDSETH, + 5122 => Opcode::LDSETLB, + 5123 => Opcode::LDSETLH, + 5124 => Opcode::LDSETLW, + 5125 => Opcode::LDSETLX, + 5126 => Opcode::LDSETP, + 5127 => Opcode::LDSETPA, + 5128 => Opcode::LDSETPAL, + 5129 => Opcode::LDSETPL, + 5130 => Opcode::LDSETW, + 5131 => Opcode::LDSETX, + 5132 => Opcode::LDSMAXAB, + 5133 => Opcode::LDSMAXAH, + 5134 => Opcode::LDSMAXALB, + 5135 => Opcode::LDSMAXALH, + 5136 => Opcode::LDSMAXALW, + 5137 => Opcode::LDSMAXALX, + 5138 => Opcode::LDSMAXAW, + 5139 => Opcode::LDSMAXAX, + 5140 => Opcode::LDSMAXB, + 5141 => Opcode::LDSMAXH, + 5142 => Opcode::LDSMAXLB, + 5143 => Opcode::LDSMAXLH, + 5144 => Opcode::LDSMAXLW, + 5145 => Opcode::LDSMAXLX, + 5146 => Opcode::LDSMAXW, + 5147 => Opcode::LDSMAXX, + 5148 => Opcode::LDSMINAB, + 5149 => Opcode::LDSMINAH, + 5150 => Opcode::LDSMINALB, + 5151 => Opcode::LDSMINALH, + 5152 => Opcode::LDSMINALW, + 5153 => Opcode::LDSMINALX, + 5154 => Opcode::LDSMINAW, + 5155 => Opcode::LDSMINAX, + 5156 => Opcode::LDSMINB, + 5157 => Opcode::LDSMINH, + 5158 => Opcode::LDSMINLB, + 5159 => Opcode::LDSMINLH, + 5160 => Opcode::LDSMINLW, + 5161 => Opcode::LDSMINLX, + 5162 => Opcode::LDSMINW, + 5163 => Opcode::LDSMINX, + 5164 => Opcode::LDTADDALW, + 5165 => Opcode::LDTADDALX, + 5166 => Opcode::LDTADDAW, + 5167 => Opcode::LDTADDAX, + 5168 => Opcode::LDTADDLW, + 5169 => Opcode::LDTADDLX, + 5170 => Opcode::LDTADDW, + 5171 => Opcode::LDTADDX, + 5172 => Opcode::LDTCLRALW, + 5173 => Opcode::LDTCLRALX, + 5174 => Opcode::LDTCLRAW, + 5175 => Opcode::LDTCLRAX, + 5176 => Opcode::LDTCLRLW, + 5177 => Opcode::LDTCLRLX, + 5178 => Opcode::LDTCLRW, + 5179 => Opcode::LDTCLRX, + 5180 => Opcode::LDTNPQi, + 5181 => Opcode::LDTNPXi, + 5182 => Opcode::LDTPQi, + 5183 => Opcode::LDTPQpost, + 5184 => Opcode::LDTPQpre, + 5185 => Opcode::LDTPi, + 5186 => Opcode::LDTPpost, + 5187 => Opcode::LDTPpre, + 5188 => Opcode::LDTRBi, + 5189 => Opcode::LDTRHi, + 5190 => Opcode::LDTRSBWi, + 5191 => Opcode::LDTRSBXi, + 5192 => Opcode::LDTRSHWi, + 5193 => Opcode::LDTRSHXi, + 5194 => Opcode::LDTRSWi, + 5195 => Opcode::LDTRWi, + 5196 => Opcode::LDTRXi, + 5197 => Opcode::LDTSETALW, + 5198 => Opcode::LDTSETALX, + 5199 => Opcode::LDTSETAW, + 5200 => Opcode::LDTSETAX, + 5201 => Opcode::LDTSETLW, + 5202 => Opcode::LDTSETLX, + 5203 => Opcode::LDTSETW, + 5204 => Opcode::LDTSETX, + 5205 => Opcode::LDTXRWr, + 5206 => Opcode::LDTXRXr, + 5207 => Opcode::LDUMAXAB, + 5208 => Opcode::LDUMAXAH, + 5209 => Opcode::LDUMAXALB, + 5210 => Opcode::LDUMAXALH, + 5211 => Opcode::LDUMAXALW, + 5212 => Opcode::LDUMAXALX, + 5213 => Opcode::LDUMAXAW, + 5214 => Opcode::LDUMAXAX, + 5215 => Opcode::LDUMAXB, + 5216 => Opcode::LDUMAXH, + 5217 => Opcode::LDUMAXLB, + 5218 => Opcode::LDUMAXLH, + 5219 => Opcode::LDUMAXLW, + 5220 => Opcode::LDUMAXLX, + 5221 => Opcode::LDUMAXW, + 5222 => Opcode::LDUMAXX, + 5223 => Opcode::LDUMINAB, + 5224 => Opcode::LDUMINAH, + 5225 => Opcode::LDUMINALB, + 5226 => Opcode::LDUMINALH, + 5227 => Opcode::LDUMINALW, + 5228 => Opcode::LDUMINALX, + 5229 => Opcode::LDUMINAW, + 5230 => Opcode::LDUMINAX, + 5231 => Opcode::LDUMINB, + 5232 => Opcode::LDUMINH, + 5233 => Opcode::LDUMINLB, + 5234 => Opcode::LDUMINLH, + 5235 => Opcode::LDUMINLW, + 5236 => Opcode::LDUMINLX, + 5237 => Opcode::LDUMINW, + 5238 => Opcode::LDUMINX, + 5239 => Opcode::LDURBBi, + 5240 => Opcode::LDURBi, + 5241 => Opcode::LDURDi, + 5242 => Opcode::LDURHHi, + 5243 => Opcode::LDURHi, + 5244 => Opcode::LDURQi, + 5245 => Opcode::LDURSBWi, + 5246 => Opcode::LDURSBXi, + 5247 => Opcode::LDURSHWi, + 5248 => Opcode::LDURSHXi, + 5249 => Opcode::LDURSWi, + 5250 => Opcode::LDURSi, + 5251 => Opcode::LDURWi, + 5252 => Opcode::LDURXi, + 5253 => Opcode::LDXPW, + 5254 => Opcode::LDXPX, + 5255 => Opcode::LDXRB, + 5256 => Opcode::LDXRH, + 5257 => Opcode::LDXRW, + 5258 => Opcode::LDXRX, + 5259 => Opcode::LSLR_ZPmZ_B, + 5260 => Opcode::LSLR_ZPmZ_D, + 5261 => Opcode::LSLR_ZPmZ_H, + 5262 => Opcode::LSLR_ZPmZ_S, + 5263 => Opcode::LSLVWr, + 5264 => Opcode::LSLVXr, + 5265 => Opcode::LSL_WIDE_ZPmZ_B, + 5266 => Opcode::LSL_WIDE_ZPmZ_H, + 5267 => Opcode::LSL_WIDE_ZPmZ_S, + 5268 => Opcode::LSL_WIDE_ZZZ_B, + 5269 => Opcode::LSL_WIDE_ZZZ_H, + 5270 => Opcode::LSL_WIDE_ZZZ_S, + 5271 => Opcode::LSL_ZPmI_B, + 5272 => Opcode::LSL_ZPmI_D, + 5273 => Opcode::LSL_ZPmI_H, + 5274 => Opcode::LSL_ZPmI_S, + 5275 => Opcode::LSL_ZPmZ_B, + 5276 => Opcode::LSL_ZPmZ_D, + 5277 => Opcode::LSL_ZPmZ_H, + 5278 => Opcode::LSL_ZPmZ_S, + 5279 => Opcode::LSL_ZZI_B, + 5280 => Opcode::LSL_ZZI_D, + 5281 => Opcode::LSL_ZZI_H, + 5282 => Opcode::LSL_ZZI_S, + 5283 => Opcode::LSRR_ZPmZ_B, + 5284 => Opcode::LSRR_ZPmZ_D, + 5285 => Opcode::LSRR_ZPmZ_H, + 5286 => Opcode::LSRR_ZPmZ_S, + 5287 => Opcode::LSRVWr, + 5288 => Opcode::LSRVXr, + 5289 => Opcode::LSR_WIDE_ZPmZ_B, + 5290 => Opcode::LSR_WIDE_ZPmZ_H, + 5291 => Opcode::LSR_WIDE_ZPmZ_S, + 5292 => Opcode::LSR_WIDE_ZZZ_B, + 5293 => Opcode::LSR_WIDE_ZZZ_H, + 5294 => Opcode::LSR_WIDE_ZZZ_S, + 5295 => Opcode::LSR_ZPmI_B, + 5296 => Opcode::LSR_ZPmI_D, + 5297 => Opcode::LSR_ZPmI_H, + 5298 => Opcode::LSR_ZPmI_S, + 5299 => Opcode::LSR_ZPmZ_B, + 5300 => Opcode::LSR_ZPmZ_D, + 5301 => Opcode::LSR_ZPmZ_H, + 5302 => Opcode::LSR_ZPmZ_S, + 5303 => Opcode::LSR_ZZI_B, + 5304 => Opcode::LSR_ZZI_D, + 5305 => Opcode::LSR_ZZI_H, + 5306 => Opcode::LSR_ZZI_S, + 5307 => Opcode::LUT2_B, + 5308 => Opcode::LUT2_H, + 5309 => Opcode::LUT4_B, + 5310 => Opcode::LUT4_H, + 5311 => Opcode::LUTI2_2ZTZI_B, + 5312 => Opcode::LUTI2_2ZTZI_H, + 5313 => Opcode::LUTI2_2ZTZI_S, + 5314 => Opcode::LUTI2_4ZTZI_B, + 5315 => Opcode::LUTI2_4ZTZI_H, + 5316 => Opcode::LUTI2_4ZTZI_S, + 5317 => Opcode::LUTI2_S_2ZTZI_B, + 5318 => Opcode::LUTI2_S_2ZTZI_H, + 5319 => Opcode::LUTI2_S_4ZTZI_B, + 5320 => Opcode::LUTI2_S_4ZTZI_H, + 5321 => Opcode::LUTI2_ZTZI_B, + 5322 => Opcode::LUTI2_ZTZI_H, + 5323 => Opcode::LUTI2_ZTZI_S, + 5324 => Opcode::LUTI2_ZZZI_B, + 5325 => Opcode::LUTI2_ZZZI_H, + 5326 => Opcode::LUTI4_2ZTZI_B, + 5327 => Opcode::LUTI4_2ZTZI_H, + 5328 => Opcode::LUTI4_2ZTZI_S, + 5329 => Opcode::LUTI4_4ZTZI_H, + 5330 => Opcode::LUTI4_4ZTZI_S, + 5331 => Opcode::LUTI4_4ZZT2Z, + 5332 => Opcode::LUTI4_S_2ZTZI_B, + 5333 => Opcode::LUTI4_S_2ZTZI_H, + 5334 => Opcode::LUTI4_S_4ZTZI_H, + 5335 => Opcode::LUTI4_S_4ZZT2Z, + 5336 => Opcode::LUTI4_Z2ZZI, + 5337 => Opcode::LUTI4_ZTZI_B, + 5338 => Opcode::LUTI4_ZTZI_H, + 5339 => Opcode::LUTI4_ZTZI_S, + 5340 => Opcode::LUTI4_ZZZI_B, + 5341 => Opcode::LUTI4_ZZZI_H, + 5342 => Opcode::LUTI6_4Z2Z2ZI, + 5343 => Opcode::LUTI6_4ZT3Z, + 5344 => Opcode::LUTI6_S_4Z2Z2ZI, + 5345 => Opcode::LUTI6_S_4ZT3Z, + 5346 => Opcode::LUTI6_Z2ZZ, + 5347 => Opcode::LUTI6_Z2ZZI_H, + 5348 => Opcode::LUTI6_ZTZ, + 5349 => Opcode::MADDPT, + 5350 => Opcode::MADDWrrr, + 5351 => Opcode::MADDXrrr, + 5352 => Opcode::MAD_CPA, + 5353 => Opcode::MAD_ZPmZZ_B, + 5354 => Opcode::MAD_ZPmZZ_D, + 5355 => Opcode::MAD_ZPmZZ_H, + 5356 => Opcode::MAD_ZPmZZ_S, + 5357 => Opcode::MATCH_PPzZZ_B, + 5358 => Opcode::MATCH_PPzZZ_H, + 5359 => Opcode::MLA_CPA, + 5360 => Opcode::MLA_ZPmZZ_B, + 5361 => Opcode::MLA_ZPmZZ_D, + 5362 => Opcode::MLA_ZPmZZ_H, + 5363 => Opcode::MLA_ZPmZZ_S, + 5364 => Opcode::MLA_ZZZI_D, + 5365 => Opcode::MLA_ZZZI_H, + 5366 => Opcode::MLA_ZZZI_S, + 5367 => Opcode::MLAv16i8, + 5368 => Opcode::MLAv2i32, + 5369 => Opcode::MLAv2i32_indexed, + 5370 => Opcode::MLAv4i16, + 5371 => Opcode::MLAv4i16_indexed, + 5372 => Opcode::MLAv4i32, + 5373 => Opcode::MLAv4i32_indexed, + 5374 => Opcode::MLAv8i16, + 5375 => Opcode::MLAv8i16_indexed, + 5376 => Opcode::MLAv8i8, + 5377 => Opcode::MLS_ZPmZZ_B, + 5378 => Opcode::MLS_ZPmZZ_D, + 5379 => Opcode::MLS_ZPmZZ_H, + 5380 => Opcode::MLS_ZPmZZ_S, + 5381 => Opcode::MLS_ZZZI_D, + 5382 => Opcode::MLS_ZZZI_H, + 5383 => Opcode::MLS_ZZZI_S, + 5384 => Opcode::MLSv16i8, + 5385 => Opcode::MLSv2i32, + 5386 => Opcode::MLSv2i32_indexed, + 5387 => Opcode::MLSv4i16, + 5388 => Opcode::MLSv4i16_indexed, + 5389 => Opcode::MLSv4i32, + 5390 => Opcode::MLSv4i32_indexed, + 5391 => Opcode::MLSv8i16, + 5392 => Opcode::MLSv8i16_indexed, + 5393 => Opcode::MLSv8i8, + 5394 => Opcode::MOPSSETGE, + 5395 => Opcode::MOPSSETGEN, + 5396 => Opcode::MOPSSETGET, + 5397 => Opcode::MOPSSETGETN, + 5398 => Opcode::MOVAZ_2ZMI_H_B, + 5399 => Opcode::MOVAZ_2ZMI_H_D, + 5400 => Opcode::MOVAZ_2ZMI_H_H, + 5401 => Opcode::MOVAZ_2ZMI_H_S, + 5402 => Opcode::MOVAZ_2ZMI_V_B, + 5403 => Opcode::MOVAZ_2ZMI_V_D, + 5404 => Opcode::MOVAZ_2ZMI_V_H, + 5405 => Opcode::MOVAZ_2ZMI_V_S, + 5406 => Opcode::MOVAZ_4ZMI_H_B, + 5407 => Opcode::MOVAZ_4ZMI_H_D, + 5408 => Opcode::MOVAZ_4ZMI_H_H, + 5409 => Opcode::MOVAZ_4ZMI_H_S, + 5410 => Opcode::MOVAZ_4ZMI_V_B, + 5411 => Opcode::MOVAZ_4ZMI_V_D, + 5412 => Opcode::MOVAZ_4ZMI_V_H, + 5413 => Opcode::MOVAZ_4ZMI_V_S, + 5414 => Opcode::MOVAZ_VG2_2ZMXI, + 5415 => Opcode::MOVAZ_VG4_4ZMXI, + 5416 => Opcode::MOVAZ_ZMI_H_B, + 5417 => Opcode::MOVAZ_ZMI_H_D, + 5418 => Opcode::MOVAZ_ZMI_H_H, + 5419 => Opcode::MOVAZ_ZMI_H_Q, + 5420 => Opcode::MOVAZ_ZMI_H_S, + 5421 => Opcode::MOVAZ_ZMI_V_B, + 5422 => Opcode::MOVAZ_ZMI_V_D, + 5423 => Opcode::MOVAZ_ZMI_V_H, + 5424 => Opcode::MOVAZ_ZMI_V_Q, + 5425 => Opcode::MOVAZ_ZMI_V_S, + 5426 => Opcode::MOVA_2ZMXI_H_B, + 5427 => Opcode::MOVA_2ZMXI_H_D, + 5428 => Opcode::MOVA_2ZMXI_H_H, + 5429 => Opcode::MOVA_2ZMXI_H_S, + 5430 => Opcode::MOVA_2ZMXI_V_B, + 5431 => Opcode::MOVA_2ZMXI_V_D, + 5432 => Opcode::MOVA_2ZMXI_V_H, + 5433 => Opcode::MOVA_2ZMXI_V_S, + 5434 => Opcode::MOVA_4ZMXI_H_B, + 5435 => Opcode::MOVA_4ZMXI_H_D, + 5436 => Opcode::MOVA_4ZMXI_H_H, + 5437 => Opcode::MOVA_4ZMXI_H_S, + 5438 => Opcode::MOVA_4ZMXI_V_B, + 5439 => Opcode::MOVA_4ZMXI_V_D, + 5440 => Opcode::MOVA_4ZMXI_V_H, + 5441 => Opcode::MOVA_4ZMXI_V_S, + 5442 => Opcode::MOVA_MXI2Z_H_B, + 5443 => Opcode::MOVA_MXI2Z_H_D, + 5444 => Opcode::MOVA_MXI2Z_H_H, + 5445 => Opcode::MOVA_MXI2Z_H_S, + 5446 => Opcode::MOVA_MXI2Z_V_B, + 5447 => Opcode::MOVA_MXI2Z_V_D, + 5448 => Opcode::MOVA_MXI2Z_V_H, + 5449 => Opcode::MOVA_MXI2Z_V_S, + 5450 => Opcode::MOVA_MXI4Z_H_B, + 5451 => Opcode::MOVA_MXI4Z_H_D, + 5452 => Opcode::MOVA_MXI4Z_H_H, + 5453 => Opcode::MOVA_MXI4Z_H_S, + 5454 => Opcode::MOVA_MXI4Z_V_B, + 5455 => Opcode::MOVA_MXI4Z_V_D, + 5456 => Opcode::MOVA_MXI4Z_V_H, + 5457 => Opcode::MOVA_MXI4Z_V_S, + 5458 => Opcode::MOVA_VG2_2ZMXI, + 5459 => Opcode::MOVA_VG2_MXI2Z, + 5460 => Opcode::MOVA_VG4_4ZMXI, + 5461 => Opcode::MOVA_VG4_MXI4Z, + 5462 => Opcode::MOVID, + 5463 => Opcode::MOVIv16b_ns, + 5464 => Opcode::MOVIv2d_ns, + 5465 => Opcode::MOVIv2i32, + 5466 => Opcode::MOVIv2s_msl, + 5467 => Opcode::MOVIv4i16, + 5468 => Opcode::MOVIv4i32, + 5469 => Opcode::MOVIv4s_msl, + 5470 => Opcode::MOVIv8b_ns, + 5471 => Opcode::MOVIv8i16, + 5472 => Opcode::MOVKWi, + 5473 => Opcode::MOVKXi, + 5474 => Opcode::MOVNWi, + 5475 => Opcode::MOVNXi, + 5476 => Opcode::MOVPRFX_ZPmZ_B, + 5477 => Opcode::MOVPRFX_ZPmZ_D, + 5478 => Opcode::MOVPRFX_ZPmZ_H, + 5479 => Opcode::MOVPRFX_ZPmZ_S, + 5480 => Opcode::MOVPRFX_ZPzZ_B, + 5481 => Opcode::MOVPRFX_ZPzZ_D, + 5482 => Opcode::MOVPRFX_ZPzZ_H, + 5483 => Opcode::MOVPRFX_ZPzZ_S, + 5484 => Opcode::MOVPRFX_ZZ, + 5485 => Opcode::MOVT_TIX, + 5486 => Opcode::MOVT_TIZ, + 5487 => Opcode::MOVT_XTI, + 5488 => Opcode::MOVZWi, + 5489 => Opcode::MOVZXi, + 5490 => Opcode::MRRS, + 5491 => Opcode::MRS, + 5492 => Opcode::MSB_ZPmZZ_B, + 5493 => Opcode::MSB_ZPmZZ_D, + 5494 => Opcode::MSB_ZPmZZ_H, + 5495 => Opcode::MSB_ZPmZZ_S, + 5496 => Opcode::MSR, + 5497 => Opcode::MSRR, + 5498 => Opcode::MSRpstateImm1, + 5499 => Opcode::MSRpstateImm4, + 5500 => Opcode::MSRpstatesvcrImm1, + 5501 => Opcode::MSUBPT, + 5502 => Opcode::MSUBWrrr, + 5503 => Opcode::MSUBXrrr, + 5504 => Opcode::MUL_ZI_B, + 5505 => Opcode::MUL_ZI_D, + 5506 => Opcode::MUL_ZI_H, + 5507 => Opcode::MUL_ZI_S, + 5508 => Opcode::MUL_ZPmZ_B, + 5509 => Opcode::MUL_ZPmZ_D, + 5510 => Opcode::MUL_ZPmZ_H, + 5511 => Opcode::MUL_ZPmZ_S, + 5512 => Opcode::MUL_ZZZI_D, + 5513 => Opcode::MUL_ZZZI_H, + 5514 => Opcode::MUL_ZZZI_S, + 5515 => Opcode::MUL_ZZZ_B, + 5516 => Opcode::MUL_ZZZ_D, + 5517 => Opcode::MUL_ZZZ_H, + 5518 => Opcode::MUL_ZZZ_S, + 5519 => Opcode::MULv16i8, + 5520 => Opcode::MULv2i32, + 5521 => Opcode::MULv2i32_indexed, + 5522 => Opcode::MULv4i16, + 5523 => Opcode::MULv4i16_indexed, + 5524 => Opcode::MULv4i32, + 5525 => Opcode::MULv4i32_indexed, + 5526 => Opcode::MULv8i16, + 5527 => Opcode::MULv8i16_indexed, + 5528 => Opcode::MULv8i8, + 5529 => Opcode::MVNIv2i32, + 5530 => Opcode::MVNIv2s_msl, + 5531 => Opcode::MVNIv4i16, + 5532 => Opcode::MVNIv4i32, + 5533 => Opcode::MVNIv4s_msl, + 5534 => Opcode::MVNIv8i16, + 5535 => Opcode::NANDS_PPzPP, + 5536 => Opcode::NAND_PPzPP, + 5537 => Opcode::NBSL_ZZZZ, + 5538 => Opcode::NEG_ZPmZ_B, + 5539 => Opcode::NEG_ZPmZ_D, + 5540 => Opcode::NEG_ZPmZ_H, + 5541 => Opcode::NEG_ZPmZ_S, + 5542 => Opcode::NEG_ZPzZ_B, + 5543 => Opcode::NEG_ZPzZ_D, + 5544 => Opcode::NEG_ZPzZ_H, + 5545 => Opcode::NEG_ZPzZ_S, + 5546 => Opcode::NEGv16i8, + 5547 => Opcode::NEGv1i64, + 5548 => Opcode::NEGv2i32, + 5549 => Opcode::NEGv2i64, + 5550 => Opcode::NEGv4i16, + 5551 => Opcode::NEGv4i32, + 5552 => Opcode::NEGv8i16, + 5553 => Opcode::NEGv8i8, + 5554 => Opcode::NMATCH_PPzZZ_B, + 5555 => Opcode::NMATCH_PPzZZ_H, + 5556 => Opcode::NOP, + 5557 => Opcode::NORS_PPzPP, + 5558 => Opcode::NOR_PPzPP, + 5559 => Opcode::NOT_ZPmZ_B, + 5560 => Opcode::NOT_ZPmZ_D, + 5561 => Opcode::NOT_ZPmZ_H, + 5562 => Opcode::NOT_ZPmZ_S, + 5563 => Opcode::NOT_ZPzZ_B, + 5564 => Opcode::NOT_ZPzZ_D, + 5565 => Opcode::NOT_ZPzZ_H, + 5566 => Opcode::NOT_ZPzZ_S, + 5567 => Opcode::NOTv16i8, + 5568 => Opcode::NOTv8i8, + 5569 => Opcode::ORNS_PPzPP, + 5570 => Opcode::ORNWrs, + 5571 => Opcode::ORNXrs, + 5572 => Opcode::ORN_PPzPP, + 5573 => Opcode::ORNv16i8, + 5574 => Opcode::ORNv8i8, + 5575 => Opcode::ORQV_VPZ_B, + 5576 => Opcode::ORQV_VPZ_D, + 5577 => Opcode::ORQV_VPZ_H, + 5578 => Opcode::ORQV_VPZ_S, + 5579 => Opcode::ORRS_PPzPP, + 5580 => Opcode::ORRWri, + 5581 => Opcode::ORRWrs, + 5582 => Opcode::ORRXri, + 5583 => Opcode::ORRXrs, + 5584 => Opcode::ORR_PPzPP, + 5585 => Opcode::ORR_ZI, + 5586 => Opcode::ORR_ZPmZ_B, + 5587 => Opcode::ORR_ZPmZ_D, + 5588 => Opcode::ORR_ZPmZ_H, + 5589 => Opcode::ORR_ZPmZ_S, + 5590 => Opcode::ORR_ZZZ, + 5591 => Opcode::ORRv16i8, + 5592 => Opcode::ORRv2i32, + 5593 => Opcode::ORRv4i16, + 5594 => Opcode::ORRv4i32, + 5595 => Opcode::ORRv8i16, + 5596 => Opcode::ORRv8i8, + 5597 => Opcode::ORV_VPZ_B, + 5598 => Opcode::ORV_VPZ_D, + 5599 => Opcode::ORV_VPZ_H, + 5600 => Opcode::ORV_VPZ_S, + 5601 => Opcode::PACDA, + 5602 => Opcode::PACDB, + 5603 => Opcode::PACDZA, + 5604 => Opcode::PACDZB, + 5605 => Opcode::PACGA, + 5606 => Opcode::PACIA, + 5607 => Opcode::PACIA1716, + 5608 => Opcode::PACIA171615, + 5609 => Opcode::PACIASP, + 5610 => Opcode::PACIASPPC, + 5611 => Opcode::PACIAZ, + 5612 => Opcode::PACIB, + 5613 => Opcode::PACIB1716, + 5614 => Opcode::PACIB171615, + 5615 => Opcode::PACIBSP, + 5616 => Opcode::PACIBSPPC, + 5617 => Opcode::PACIBZ, + 5618 => Opcode::PACIZA, + 5619 => Opcode::PACIZB, + 5620 => Opcode::PACM, + 5621 => Opcode::PACNBIASPPC, + 5622 => Opcode::PACNBIBSPPC, + 5623 => Opcode::PEXT_2PCI_B, + 5624 => Opcode::PEXT_2PCI_D, + 5625 => Opcode::PEXT_2PCI_H, + 5626 => Opcode::PEXT_2PCI_S, + 5627 => Opcode::PEXT_PCI_B, + 5628 => Opcode::PEXT_PCI_D, + 5629 => Opcode::PEXT_PCI_H, + 5630 => Opcode::PEXT_PCI_S, + 5631 => Opcode::PFALSE, + 5632 => Opcode::PFIRST_B, + 5633 => Opcode::PMLAL_2ZZZ_Q, + 5634 => Opcode::PMOV_PZI_B, + 5635 => Opcode::PMOV_PZI_D, + 5636 => Opcode::PMOV_PZI_H, + 5637 => Opcode::PMOV_PZI_S, + 5638 => Opcode::PMOV_ZIP_B, + 5639 => Opcode::PMOV_ZIP_D, + 5640 => Opcode::PMOV_ZIP_H, + 5641 => Opcode::PMOV_ZIP_S, + 5642 => Opcode::PMULLB_ZZZ_D, + 5643 => Opcode::PMULLB_ZZZ_H, + 5644 => Opcode::PMULLB_ZZZ_Q, + 5645 => Opcode::PMULLT_ZZZ_D, + 5646 => Opcode::PMULLT_ZZZ_H, + 5647 => Opcode::PMULLT_ZZZ_Q, + 5648 => Opcode::PMULL_2ZZZ_Q, + 5649 => Opcode::PMULLv16i8, + 5650 => Opcode::PMULLv1i64, + 5651 => Opcode::PMULLv2i64, + 5652 => Opcode::PMULLv8i8, + 5653 => Opcode::PMUL_ZZZ_B, + 5654 => Opcode::PMULv16i8, + 5655 => Opcode::PMULv8i8, + 5656 => Opcode::PNEXT_B, + 5657 => Opcode::PNEXT_D, + 5658 => Opcode::PNEXT_H, + 5659 => Opcode::PNEXT_S, + 5660 => Opcode::PRFB_D_PZI, + 5661 => Opcode::PRFB_D_SCALED, + 5662 => Opcode::PRFB_D_SXTW_SCALED, + 5663 => Opcode::PRFB_D_UXTW_SCALED, + 5664 => Opcode::PRFB_PRI, + 5665 => Opcode::PRFB_PRR, + 5666 => Opcode::PRFB_S_PZI, + 5667 => Opcode::PRFB_S_SXTW_SCALED, + 5668 => Opcode::PRFB_S_UXTW_SCALED, + 5669 => Opcode::PRFD_D_PZI, + 5670 => Opcode::PRFD_D_SCALED, + 5671 => Opcode::PRFD_D_SXTW_SCALED, + 5672 => Opcode::PRFD_D_UXTW_SCALED, + 5673 => Opcode::PRFD_PRI, + 5674 => Opcode::PRFD_PRR, + 5675 => Opcode::PRFD_S_PZI, + 5676 => Opcode::PRFD_S_SXTW_SCALED, + 5677 => Opcode::PRFD_S_UXTW_SCALED, + 5678 => Opcode::PRFH_D_PZI, + 5679 => Opcode::PRFH_D_SCALED, + 5680 => Opcode::PRFH_D_SXTW_SCALED, + 5681 => Opcode::PRFH_D_UXTW_SCALED, + 5682 => Opcode::PRFH_PRI, + 5683 => Opcode::PRFH_PRR, + 5684 => Opcode::PRFH_S_PZI, + 5685 => Opcode::PRFH_S_SXTW_SCALED, + 5686 => Opcode::PRFH_S_UXTW_SCALED, + 5687 => Opcode::PRFMl, + 5688 => Opcode::PRFMroW, + 5689 => Opcode::PRFMroX, + 5690 => Opcode::PRFMui, + 5691 => Opcode::PRFUMi, + 5692 => Opcode::PRFW_D_PZI, + 5693 => Opcode::PRFW_D_SCALED, + 5694 => Opcode::PRFW_D_SXTW_SCALED, + 5695 => Opcode::PRFW_D_UXTW_SCALED, + 5696 => Opcode::PRFW_PRI, + 5697 => Opcode::PRFW_PRR, + 5698 => Opcode::PRFW_S_PZI, + 5699 => Opcode::PRFW_S_SXTW_SCALED, + 5700 => Opcode::PRFW_S_UXTW_SCALED, + 5701 => Opcode::PSEL_PPPRI_B, + 5702 => Opcode::PSEL_PPPRI_D, + 5703 => Opcode::PSEL_PPPRI_H, + 5704 => Opcode::PSEL_PPPRI_S, + 5705 => Opcode::PTEST_PP, + 5706 => Opcode::PTRUES_B, + 5707 => Opcode::PTRUES_D, + 5708 => Opcode::PTRUES_H, + 5709 => Opcode::PTRUES_S, + 5710 => Opcode::PTRUE_B, + 5711 => Opcode::PTRUE_C_B, + 5712 => Opcode::PTRUE_C_D, + 5713 => Opcode::PTRUE_C_H, + 5714 => Opcode::PTRUE_C_S, + 5715 => Opcode::PTRUE_D, + 5716 => Opcode::PTRUE_H, + 5717 => Opcode::PTRUE_S, + 5718 => Opcode::PUNPKHI_PP, + 5719 => Opcode::PUNPKLO_PP, + 5720 => Opcode::RADDHNB_ZZZ_B, + 5721 => Opcode::RADDHNB_ZZZ_H, + 5722 => Opcode::RADDHNB_ZZZ_S, + 5723 => Opcode::RADDHNT_ZZZ_B, + 5724 => Opcode::RADDHNT_ZZZ_H, + 5725 => Opcode::RADDHNT_ZZZ_S, + 5726 => Opcode::RADDHNv2i64_v2i32, + 5727 => Opcode::RADDHNv2i64_v4i32, + 5728 => Opcode::RADDHNv4i32_v4i16, + 5729 => Opcode::RADDHNv4i32_v8i16, + 5730 => Opcode::RADDHNv8i16_v16i8, + 5731 => Opcode::RADDHNv8i16_v8i8, + 5732 => Opcode::RAX1, + 5733 => Opcode::RAX1_ZZZ_D, + 5734 => Opcode::RBITWr, + 5735 => Opcode::RBITXr, + 5736 => Opcode::RBIT_ZPmZ_B, + 5737 => Opcode::RBIT_ZPmZ_D, + 5738 => Opcode::RBIT_ZPmZ_H, + 5739 => Opcode::RBIT_ZPmZ_S, + 5740 => Opcode::RBIT_ZPzZ_B, + 5741 => Opcode::RBIT_ZPzZ_D, + 5742 => Opcode::RBIT_ZPzZ_H, + 5743 => Opcode::RBIT_ZPzZ_S, + 5744 => Opcode::RBITv16i8, + 5745 => Opcode::RBITv8i8, + 5746 => Opcode::RCWCAS, + 5747 => Opcode::RCWCASA, + 5748 => Opcode::RCWCASAL, + 5749 => Opcode::RCWCASL, + 5750 => Opcode::RCWCASP, + 5751 => Opcode::RCWCASPA, + 5752 => Opcode::RCWCASPAL, + 5753 => Opcode::RCWCASPL, + 5754 => Opcode::RCWCLR, + 5755 => Opcode::RCWCLRA, + 5756 => Opcode::RCWCLRAL, + 5757 => Opcode::RCWCLRL, + 5758 => Opcode::RCWCLRP, + 5759 => Opcode::RCWCLRPA, + 5760 => Opcode::RCWCLRPAL, + 5761 => Opcode::RCWCLRPL, + 5762 => Opcode::RCWCLRS, + 5763 => Opcode::RCWCLRSA, + 5764 => Opcode::RCWCLRSAL, + 5765 => Opcode::RCWCLRSL, + 5766 => Opcode::RCWCLRSP, + 5767 => Opcode::RCWCLRSPA, + 5768 => Opcode::RCWCLRSPAL, + 5769 => Opcode::RCWCLRSPL, + 5770 => Opcode::RCWSCAS, + 5771 => Opcode::RCWSCASA, + 5772 => Opcode::RCWSCASAL, + 5773 => Opcode::RCWSCASL, + 5774 => Opcode::RCWSCASP, + 5775 => Opcode::RCWSCASPA, + 5776 => Opcode::RCWSCASPAL, + 5777 => Opcode::RCWSCASPL, + 5778 => Opcode::RCWSET, + 5779 => Opcode::RCWSETA, + 5780 => Opcode::RCWSETAL, + 5781 => Opcode::RCWSETL, + 5782 => Opcode::RCWSETP, + 5783 => Opcode::RCWSETPA, + 5784 => Opcode::RCWSETPAL, + 5785 => Opcode::RCWSETPL, + 5786 => Opcode::RCWSETS, + 5787 => Opcode::RCWSETSA, + 5788 => Opcode::RCWSETSAL, + 5789 => Opcode::RCWSETSL, + 5790 => Opcode::RCWSETSP, + 5791 => Opcode::RCWSETSPA, + 5792 => Opcode::RCWSETSPAL, + 5793 => Opcode::RCWSETSPL, + 5794 => Opcode::RCWSWP, + 5795 => Opcode::RCWSWPA, + 5796 => Opcode::RCWSWPAL, + 5797 => Opcode::RCWSWPL, + 5798 => Opcode::RCWSWPP, + 5799 => Opcode::RCWSWPPA, + 5800 => Opcode::RCWSWPPAL, + 5801 => Opcode::RCWSWPPL, + 5802 => Opcode::RCWSWPS, + 5803 => Opcode::RCWSWPSA, + 5804 => Opcode::RCWSWPSAL, + 5805 => Opcode::RCWSWPSL, + 5806 => Opcode::RCWSWPSP, + 5807 => Opcode::RCWSWPSPA, + 5808 => Opcode::RCWSWPSPAL, + 5809 => Opcode::RCWSWPSPL, + 5810 => Opcode::RDFFRS_PPz, + 5811 => Opcode::RDFFR_P, + 5812 => Opcode::RDFFR_PPz, + 5813 => Opcode::RDSVLI_XI, + 5814 => Opcode::RDVLI_XI, + 5815 => Opcode::RET, + 5816 => Opcode::RETAA, + 5817 => Opcode::RETAASPPCi, + 5818 => Opcode::RETAASPPCr, + 5819 => Opcode::RETAB, + 5820 => Opcode::RETABSPPCi, + 5821 => Opcode::RETABSPPCr, + 5822 => Opcode::REV16Wr, + 5823 => Opcode::REV16Xr, + 5824 => Opcode::REV16v16i8, + 5825 => Opcode::REV16v8i8, + 5826 => Opcode::REV32Xr, + 5827 => Opcode::REV32v16i8, + 5828 => Opcode::REV32v4i16, + 5829 => Opcode::REV32v8i16, + 5830 => Opcode::REV32v8i8, + 5831 => Opcode::REV64v16i8, + 5832 => Opcode::REV64v2i32, + 5833 => Opcode::REV64v4i16, + 5834 => Opcode::REV64v4i32, + 5835 => Opcode::REV64v8i16, + 5836 => Opcode::REV64v8i8, + 5837 => Opcode::REVB_ZPmZ_D, + 5838 => Opcode::REVB_ZPmZ_H, + 5839 => Opcode::REVB_ZPmZ_S, + 5840 => Opcode::REVB_ZPzZ_D, + 5841 => Opcode::REVB_ZPzZ_H, + 5842 => Opcode::REVB_ZPzZ_S, + 5843 => Opcode::REVD_ZPmZ, + 5844 => Opcode::REVD_ZPzZ, + 5845 => Opcode::REVH_ZPmZ_D, + 5846 => Opcode::REVH_ZPmZ_S, + 5847 => Opcode::REVH_ZPzZ_D, + 5848 => Opcode::REVH_ZPzZ_S, + 5849 => Opcode::REVW_ZPmZ_D, + 5850 => Opcode::REVW_ZPzZ_D, + 5851 => Opcode::REVWr, + 5852 => Opcode::REVXr, + 5853 => Opcode::REV_PP_B, + 5854 => Opcode::REV_PP_D, + 5855 => Opcode::REV_PP_H, + 5856 => Opcode::REV_PP_S, + 5857 => Opcode::REV_ZZ_B, + 5858 => Opcode::REV_ZZ_D, + 5859 => Opcode::REV_ZZ_H, + 5860 => Opcode::REV_ZZ_S, + 5861 => Opcode::RMIF, + 5862 => Opcode::RORVWr, + 5863 => Opcode::RORVXr, + 5864 => Opcode::RPRFM, + 5865 => Opcode::RSHRNB_ZZI_B, + 5866 => Opcode::RSHRNB_ZZI_H, + 5867 => Opcode::RSHRNB_ZZI_S, + 5868 => Opcode::RSHRNT_ZZI_B, + 5869 => Opcode::RSHRNT_ZZI_H, + 5870 => Opcode::RSHRNT_ZZI_S, + 5871 => Opcode::RSHRNv16i8_shift, + 5872 => Opcode::RSHRNv2i32_shift, + 5873 => Opcode::RSHRNv4i16_shift, + 5874 => Opcode::RSHRNv4i32_shift, + 5875 => Opcode::RSHRNv8i16_shift, + 5876 => Opcode::RSHRNv8i8_shift, + 5877 => Opcode::RSUBHNB_ZZZ_B, + 5878 => Opcode::RSUBHNB_ZZZ_H, + 5879 => Opcode::RSUBHNB_ZZZ_S, + 5880 => Opcode::RSUBHNT_ZZZ_B, + 5881 => Opcode::RSUBHNT_ZZZ_H, + 5882 => Opcode::RSUBHNT_ZZZ_S, + 5883 => Opcode::RSUBHNv2i64_v2i32, + 5884 => Opcode::RSUBHNv2i64_v4i32, + 5885 => Opcode::RSUBHNv4i32_v4i16, + 5886 => Opcode::RSUBHNv4i32_v8i16, + 5887 => Opcode::RSUBHNv8i16_v16i8, + 5888 => Opcode::RSUBHNv8i16_v8i8, + 5889 => Opcode::SABALB_ZZZ_D, + 5890 => Opcode::SABALB_ZZZ_H, + 5891 => Opcode::SABALB_ZZZ_S, + 5892 => Opcode::SABALT_ZZZ_D, + 5893 => Opcode::SABALT_ZZZ_H, + 5894 => Opcode::SABALT_ZZZ_S, + 5895 => Opcode::SABAL_ZZZ_BtoH, + 5896 => Opcode::SABAL_ZZZ_HtoS, + 5897 => Opcode::SABAL_ZZZ_StoD, + 5898 => Opcode::SABALv16i8_v8i16, + 5899 => Opcode::SABALv2i32_v2i64, + 5900 => Opcode::SABALv4i16_v4i32, + 5901 => Opcode::SABALv4i32_v2i64, + 5902 => Opcode::SABALv8i16_v4i32, + 5903 => Opcode::SABALv8i8_v8i16, + 5904 => Opcode::SABA_ZZZ_B, + 5905 => Opcode::SABA_ZZZ_D, + 5906 => Opcode::SABA_ZZZ_H, + 5907 => Opcode::SABA_ZZZ_S, + 5908 => Opcode::SABAv16i8, + 5909 => Opcode::SABAv2i32, + 5910 => Opcode::SABAv4i16, + 5911 => Opcode::SABAv4i32, + 5912 => Opcode::SABAv8i16, + 5913 => Opcode::SABAv8i8, + 5914 => Opcode::SABDLB_ZZZ_D, + 5915 => Opcode::SABDLB_ZZZ_H, + 5916 => Opcode::SABDLB_ZZZ_S, + 5917 => Opcode::SABDLT_ZZZ_D, + 5918 => Opcode::SABDLT_ZZZ_H, + 5919 => Opcode::SABDLT_ZZZ_S, + 5920 => Opcode::SABDLv16i8_v8i16, + 5921 => Opcode::SABDLv2i32_v2i64, + 5922 => Opcode::SABDLv4i16_v4i32, + 5923 => Opcode::SABDLv4i32_v2i64, + 5924 => Opcode::SABDLv8i16_v4i32, + 5925 => Opcode::SABDLv8i8_v8i16, + 5926 => Opcode::SABD_ZPmZ_B, + 5927 => Opcode::SABD_ZPmZ_D, + 5928 => Opcode::SABD_ZPmZ_H, + 5929 => Opcode::SABD_ZPmZ_S, + 5930 => Opcode::SABDv16i8, + 5931 => Opcode::SABDv2i32, + 5932 => Opcode::SABDv4i16, + 5933 => Opcode::SABDv4i32, + 5934 => Opcode::SABDv8i16, + 5935 => Opcode::SABDv8i8, + 5936 => Opcode::SADALP_ZPmZ_D, + 5937 => Opcode::SADALP_ZPmZ_H, + 5938 => Opcode::SADALP_ZPmZ_S, + 5939 => Opcode::SADALPv16i8_v8i16, + 5940 => Opcode::SADALPv2i32_v1i64, + 5941 => Opcode::SADALPv4i16_v2i32, + 5942 => Opcode::SADALPv4i32_v2i64, + 5943 => Opcode::SADALPv8i16_v4i32, + 5944 => Opcode::SADALPv8i8_v4i16, + 5945 => Opcode::SADDLBT_ZZZ_D, + 5946 => Opcode::SADDLBT_ZZZ_H, + 5947 => Opcode::SADDLBT_ZZZ_S, + 5948 => Opcode::SADDLB_ZZZ_D, + 5949 => Opcode::SADDLB_ZZZ_H, + 5950 => Opcode::SADDLB_ZZZ_S, + 5951 => Opcode::SADDLPv16i8_v8i16, + 5952 => Opcode::SADDLPv2i32_v1i64, + 5953 => Opcode::SADDLPv4i16_v2i32, + 5954 => Opcode::SADDLPv4i32_v2i64, + 5955 => Opcode::SADDLPv8i16_v4i32, + 5956 => Opcode::SADDLPv8i8_v4i16, + 5957 => Opcode::SADDLT_ZZZ_D, + 5958 => Opcode::SADDLT_ZZZ_H, + 5959 => Opcode::SADDLT_ZZZ_S, + 5960 => Opcode::SADDLVv16i8v, + 5961 => Opcode::SADDLVv4i16v, + 5962 => Opcode::SADDLVv4i32v, + 5963 => Opcode::SADDLVv8i16v, + 5964 => Opcode::SADDLVv8i8v, + 5965 => Opcode::SADDLv16i8_v8i16, + 5966 => Opcode::SADDLv2i32_v2i64, + 5967 => Opcode::SADDLv4i16_v4i32, + 5968 => Opcode::SADDLv4i32_v2i64, + 5969 => Opcode::SADDLv8i16_v4i32, + 5970 => Opcode::SADDLv8i8_v8i16, + 5971 => Opcode::SADDV_VPZ_B, + 5972 => Opcode::SADDV_VPZ_H, + 5973 => Opcode::SADDV_VPZ_S, + 5974 => Opcode::SADDWB_ZZZ_D, + 5975 => Opcode::SADDWB_ZZZ_H, + 5976 => Opcode::SADDWB_ZZZ_S, + 5977 => Opcode::SADDWT_ZZZ_D, + 5978 => Opcode::SADDWT_ZZZ_H, + 5979 => Opcode::SADDWT_ZZZ_S, + 5980 => Opcode::SADDWv16i8_v8i16, + 5981 => Opcode::SADDWv2i32_v2i64, + 5982 => Opcode::SADDWv4i16_v4i32, + 5983 => Opcode::SADDWv4i32_v2i64, + 5984 => Opcode::SADDWv8i16_v4i32, + 5985 => Opcode::SADDWv8i8_v8i16, + 5986 => Opcode::SB, + 5987 => Opcode::SBCLB_ZZZ_D, + 5988 => Opcode::SBCLB_ZZZ_S, + 5989 => Opcode::SBCLT_ZZZ_D, + 5990 => Opcode::SBCLT_ZZZ_S, + 5991 => Opcode::SBCSWr, + 5992 => Opcode::SBCSXr, + 5993 => Opcode::SBCWr, + 5994 => Opcode::SBCXr, + 5995 => Opcode::SBFMWri, + 5996 => Opcode::SBFMXri, + 5997 => Opcode::SCLAMP_VG2_2Z2Z_B, + 5998 => Opcode::SCLAMP_VG2_2Z2Z_D, + 5999 => Opcode::SCLAMP_VG2_2Z2Z_H, + 6000 => Opcode::SCLAMP_VG2_2Z2Z_S, + 6001 => Opcode::SCLAMP_VG4_4Z4Z_B, + 6002 => Opcode::SCLAMP_VG4_4Z4Z_D, + 6003 => Opcode::SCLAMP_VG4_4Z4Z_H, + 6004 => Opcode::SCLAMP_VG4_4Z4Z_S, + 6005 => Opcode::SCLAMP_ZZZ_B, + 6006 => Opcode::SCLAMP_ZZZ_D, + 6007 => Opcode::SCLAMP_ZZZ_H, + 6008 => Opcode::SCLAMP_ZZZ_S, + 6009 => Opcode::SCVTFDSr, + 6010 => Opcode::SCVTFHDr, + 6011 => Opcode::SCVTFHSr, + 6012 => Opcode::SCVTFLT_ZZ_BtoH, + 6013 => Opcode::SCVTFLT_ZZ_HtoS, + 6014 => Opcode::SCVTFLT_ZZ_StoD, + 6015 => Opcode::SCVTFSDr, + 6016 => Opcode::SCVTFSWDri, + 6017 => Opcode::SCVTFSWHri, + 6018 => Opcode::SCVTFSWSri, + 6019 => Opcode::SCVTFSXDri, + 6020 => Opcode::SCVTFSXHri, + 6021 => Opcode::SCVTFSXSri, + 6022 => Opcode::SCVTFUWDri, + 6023 => Opcode::SCVTFUWHri, + 6024 => Opcode::SCVTFUWSri, + 6025 => Opcode::SCVTFUXDri, + 6026 => Opcode::SCVTFUXHri, + 6027 => Opcode::SCVTFUXSri, + 6028 => Opcode::SCVTF_2Z2Z_StoS, + 6029 => Opcode::SCVTF_4Z4Z_StoS, + 6030 => Opcode::SCVTF_ZPmZ_DtoD, + 6031 => Opcode::SCVTF_ZPmZ_DtoH, + 6032 => Opcode::SCVTF_ZPmZ_DtoS, + 6033 => Opcode::SCVTF_ZPmZ_HtoH, + 6034 => Opcode::SCVTF_ZPmZ_StoD, + 6035 => Opcode::SCVTF_ZPmZ_StoH, + 6036 => Opcode::SCVTF_ZPmZ_StoS, + 6037 => Opcode::SCVTF_ZPzZ_DtoD, + 6038 => Opcode::SCVTF_ZPzZ_DtoH, + 6039 => Opcode::SCVTF_ZPzZ_DtoS, + 6040 => Opcode::SCVTF_ZPzZ_HtoH, + 6041 => Opcode::SCVTF_ZPzZ_StoD, + 6042 => Opcode::SCVTF_ZPzZ_StoH, + 6043 => Opcode::SCVTF_ZPzZ_StoS, + 6044 => Opcode::SCVTF_ZZ_BtoH, + 6045 => Opcode::SCVTF_ZZ_HtoS, + 6046 => Opcode::SCVTF_ZZ_StoD, + 6047 => Opcode::SCVTFd, + 6048 => Opcode::SCVTFh, + 6049 => Opcode::SCVTFs, + 6050 => Opcode::SCVTFv1i16, + 6051 => Opcode::SCVTFv1i32, + 6052 => Opcode::SCVTFv1i64, + 6053 => Opcode::SCVTFv2f32, + 6054 => Opcode::SCVTFv2f64, + 6055 => Opcode::SCVTFv2i32_shift, + 6056 => Opcode::SCVTFv2i64_shift, + 6057 => Opcode::SCVTFv4f16, + 6058 => Opcode::SCVTFv4f32, + 6059 => Opcode::SCVTFv4i16_shift, + 6060 => Opcode::SCVTFv4i32_shift, + 6061 => Opcode::SCVTFv8f16, + 6062 => Opcode::SCVTFv8i16_shift, + 6063 => Opcode::SDIVR_ZPmZ_D, + 6064 => Opcode::SDIVR_ZPmZ_S, + 6065 => Opcode::SDIVWr, + 6066 => Opcode::SDIVXr, + 6067 => Opcode::SDIV_ZPmZ_D, + 6068 => Opcode::SDIV_ZPmZ_S, + 6069 => Opcode::SDOT_VG2_M2Z2Z_BtoS, + 6070 => Opcode::SDOT_VG2_M2Z2Z_HtoD, + 6071 => Opcode::SDOT_VG2_M2Z2Z_HtoS, + 6072 => Opcode::SDOT_VG2_M2ZZI_BToS, + 6073 => Opcode::SDOT_VG2_M2ZZI_HToS, + 6074 => Opcode::SDOT_VG2_M2ZZI_HtoD, + 6075 => Opcode::SDOT_VG2_M2ZZ_BtoS, + 6076 => Opcode::SDOT_VG2_M2ZZ_HtoD, + 6077 => Opcode::SDOT_VG2_M2ZZ_HtoS, + 6078 => Opcode::SDOT_VG4_M4Z4Z_BtoS, + 6079 => Opcode::SDOT_VG4_M4Z4Z_HtoD, + 6080 => Opcode::SDOT_VG4_M4Z4Z_HtoS, + 6081 => Opcode::SDOT_VG4_M4ZZI_BToS, + 6082 => Opcode::SDOT_VG4_M4ZZI_HToS, + 6083 => Opcode::SDOT_VG4_M4ZZI_HtoD, + 6084 => Opcode::SDOT_VG4_M4ZZ_BtoS, + 6085 => Opcode::SDOT_VG4_M4ZZ_HtoD, + 6086 => Opcode::SDOT_VG4_M4ZZ_HtoS, + 6087 => Opcode::SDOT_ZZZI_BtoH, + 6088 => Opcode::SDOT_ZZZI_BtoS, + 6089 => Opcode::SDOT_ZZZI_HtoD, + 6090 => Opcode::SDOT_ZZZI_HtoS, + 6091 => Opcode::SDOT_ZZZ_BtoH, + 6092 => Opcode::SDOT_ZZZ_BtoS, + 6093 => Opcode::SDOT_ZZZ_HtoD, + 6094 => Opcode::SDOT_ZZZ_HtoS, + 6095 => Opcode::SDOTlanev16i8, + 6096 => Opcode::SDOTlanev8i8, + 6097 => Opcode::SDOTv16i8, + 6098 => Opcode::SDOTv8i8, + 6099 => Opcode::SEL_PPPP, + 6100 => Opcode::SEL_VG2_2ZC2Z2Z_B, + 6101 => Opcode::SEL_VG2_2ZC2Z2Z_D, + 6102 => Opcode::SEL_VG2_2ZC2Z2Z_H, + 6103 => Opcode::SEL_VG2_2ZC2Z2Z_S, + 6104 => Opcode::SEL_VG4_4ZC4Z4Z_B, + 6105 => Opcode::SEL_VG4_4ZC4Z4Z_D, + 6106 => Opcode::SEL_VG4_4ZC4Z4Z_H, + 6107 => Opcode::SEL_VG4_4ZC4Z4Z_S, + 6108 => Opcode::SEL_ZPZZ_B, + 6109 => Opcode::SEL_ZPZZ_D, + 6110 => Opcode::SEL_ZPZZ_H, + 6111 => Opcode::SEL_ZPZZ_S, + 6112 => Opcode::SETE, + 6113 => Opcode::SETEN, + 6114 => Opcode::SETET, + 6115 => Opcode::SETETN, + 6116 => Opcode::SETF16, + 6117 => Opcode::SETF8, + 6118 => Opcode::SETFFR, + 6119 => Opcode::SETGM, + 6120 => Opcode::SETGMN, + 6121 => Opcode::SETGMT, + 6122 => Opcode::SETGMTN, + 6123 => Opcode::SETGOE, + 6124 => Opcode::SETGOEN, + 6125 => Opcode::SETGOET, + 6126 => Opcode::SETGOETN, + 6127 => Opcode::SETGOM, + 6128 => Opcode::SETGOMN, + 6129 => Opcode::SETGOMT, + 6130 => Opcode::SETGOMTN, + 6131 => Opcode::SETGOP, + 6132 => Opcode::SETGOPN, + 6133 => Opcode::SETGOPT, + 6134 => Opcode::SETGOPTN, + 6135 => Opcode::SETGP, + 6136 => Opcode::SETGPN, + 6137 => Opcode::SETGPT, + 6138 => Opcode::SETGPTN, + 6139 => Opcode::SETM, + 6140 => Opcode::SETMN, + 6141 => Opcode::SETMT, + 6142 => Opcode::SETMTN, + 6143 => Opcode::SETP, + 6144 => Opcode::SETPN, + 6145 => Opcode::SETPT, + 6146 => Opcode::SETPTN, + 6147 => Opcode::SHA1Crrr, + 6148 => Opcode::SHA1Hrr, + 6149 => Opcode::SHA1Mrrr, + 6150 => Opcode::SHA1Prrr, + 6151 => Opcode::SHA1SU0rrr, + 6152 => Opcode::SHA1SU1rr, + 6153 => Opcode::SHA256H2rrr, + 6154 => Opcode::SHA256Hrrr, + 6155 => Opcode::SHA256SU0rr, + 6156 => Opcode::SHA256SU1rrr, + 6157 => Opcode::SHA512H, + 6158 => Opcode::SHA512H2, + 6159 => Opcode::SHA512SU0, + 6160 => Opcode::SHA512SU1, + 6161 => Opcode::SHADD_ZPmZ_B, + 6162 => Opcode::SHADD_ZPmZ_D, + 6163 => Opcode::SHADD_ZPmZ_H, + 6164 => Opcode::SHADD_ZPmZ_S, + 6165 => Opcode::SHADDv16i8, + 6166 => Opcode::SHADDv2i32, + 6167 => Opcode::SHADDv4i16, + 6168 => Opcode::SHADDv4i32, + 6169 => Opcode::SHADDv8i16, + 6170 => Opcode::SHADDv8i8, + 6171 => Opcode::SHLLv16i8, + 6172 => Opcode::SHLLv2i32, + 6173 => Opcode::SHLLv4i16, + 6174 => Opcode::SHLLv4i32, + 6175 => Opcode::SHLLv8i16, + 6176 => Opcode::SHLLv8i8, + 6177 => Opcode::SHLd, + 6178 => Opcode::SHLv16i8_shift, + 6179 => Opcode::SHLv2i32_shift, + 6180 => Opcode::SHLv2i64_shift, + 6181 => Opcode::SHLv4i16_shift, + 6182 => Opcode::SHLv4i32_shift, + 6183 => Opcode::SHLv8i16_shift, + 6184 => Opcode::SHLv8i8_shift, + 6185 => Opcode::SHRNB_ZZI_B, + 6186 => Opcode::SHRNB_ZZI_H, + 6187 => Opcode::SHRNB_ZZI_S, + 6188 => Opcode::SHRNT_ZZI_B, + 6189 => Opcode::SHRNT_ZZI_H, + 6190 => Opcode::SHRNT_ZZI_S, + 6191 => Opcode::SHRNv16i8_shift, + 6192 => Opcode::SHRNv2i32_shift, + 6193 => Opcode::SHRNv4i16_shift, + 6194 => Opcode::SHRNv4i32_shift, + 6195 => Opcode::SHRNv8i16_shift, + 6196 => Opcode::SHRNv8i8_shift, + 6197 => Opcode::SHSUBR_ZPmZ_B, + 6198 => Opcode::SHSUBR_ZPmZ_D, + 6199 => Opcode::SHSUBR_ZPmZ_H, + 6200 => Opcode::SHSUBR_ZPmZ_S, + 6201 => Opcode::SHSUB_ZPmZ_B, + 6202 => Opcode::SHSUB_ZPmZ_D, + 6203 => Opcode::SHSUB_ZPmZ_H, + 6204 => Opcode::SHSUB_ZPmZ_S, + 6205 => Opcode::SHSUBv16i8, + 6206 => Opcode::SHSUBv2i32, + 6207 => Opcode::SHSUBv4i16, + 6208 => Opcode::SHSUBv4i32, + 6209 => Opcode::SHSUBv8i16, + 6210 => Opcode::SHSUBv8i8, + 6211 => Opcode::SHUH, + 6212 => Opcode::SLI_ZZI_B, + 6213 => Opcode::SLI_ZZI_D, + 6214 => Opcode::SLI_ZZI_H, + 6215 => Opcode::SLI_ZZI_S, + 6216 => Opcode::SLId, + 6217 => Opcode::SLIv16i8_shift, + 6218 => Opcode::SLIv2i32_shift, + 6219 => Opcode::SLIv2i64_shift, + 6220 => Opcode::SLIv4i16_shift, + 6221 => Opcode::SLIv4i32_shift, + 6222 => Opcode::SLIv8i16_shift, + 6223 => Opcode::SLIv8i8_shift, + 6224 => Opcode::SM3PARTW1, + 6225 => Opcode::SM3PARTW2, + 6226 => Opcode::SM3SS1, + 6227 => Opcode::SM3TT1A, + 6228 => Opcode::SM3TT1B, + 6229 => Opcode::SM3TT2A, + 6230 => Opcode::SM3TT2B, + 6231 => Opcode::SM4E, + 6232 => Opcode::SM4EKEY_ZZZ_S, + 6233 => Opcode::SM4ENCKEY, + 6234 => Opcode::SM4E_ZZZ_S, + 6235 => Opcode::SMADDLrrr, + 6236 => Opcode::SMAXP_ZPmZ_B, + 6237 => Opcode::SMAXP_ZPmZ_D, + 6238 => Opcode::SMAXP_ZPmZ_H, + 6239 => Opcode::SMAXP_ZPmZ_S, + 6240 => Opcode::SMAXPv16i8, + 6241 => Opcode::SMAXPv2i32, + 6242 => Opcode::SMAXPv4i16, + 6243 => Opcode::SMAXPv4i32, + 6244 => Opcode::SMAXPv8i16, + 6245 => Opcode::SMAXPv8i8, + 6246 => Opcode::SMAXQV_VPZ_B, + 6247 => Opcode::SMAXQV_VPZ_D, + 6248 => Opcode::SMAXQV_VPZ_H, + 6249 => Opcode::SMAXQV_VPZ_S, + 6250 => Opcode::SMAXV_VPZ_B, + 6251 => Opcode::SMAXV_VPZ_D, + 6252 => Opcode::SMAXV_VPZ_H, + 6253 => Opcode::SMAXV_VPZ_S, + 6254 => Opcode::SMAXVv16i8v, + 6255 => Opcode::SMAXVv4i16v, + 6256 => Opcode::SMAXVv4i32v, + 6257 => Opcode::SMAXVv8i16v, + 6258 => Opcode::SMAXVv8i8v, + 6259 => Opcode::SMAXWri, + 6260 => Opcode::SMAXWrr, + 6261 => Opcode::SMAXXri, + 6262 => Opcode::SMAXXrr, + 6263 => Opcode::SMAX_VG2_2Z2Z_B, + 6264 => Opcode::SMAX_VG2_2Z2Z_D, + 6265 => Opcode::SMAX_VG2_2Z2Z_H, + 6266 => Opcode::SMAX_VG2_2Z2Z_S, + 6267 => Opcode::SMAX_VG2_2ZZ_B, + 6268 => Opcode::SMAX_VG2_2ZZ_D, + 6269 => Opcode::SMAX_VG2_2ZZ_H, + 6270 => Opcode::SMAX_VG2_2ZZ_S, + 6271 => Opcode::SMAX_VG4_4Z4Z_B, + 6272 => Opcode::SMAX_VG4_4Z4Z_D, + 6273 => Opcode::SMAX_VG4_4Z4Z_H, + 6274 => Opcode::SMAX_VG4_4Z4Z_S, + 6275 => Opcode::SMAX_VG4_4ZZ_B, + 6276 => Opcode::SMAX_VG4_4ZZ_D, + 6277 => Opcode::SMAX_VG4_4ZZ_H, + 6278 => Opcode::SMAX_VG4_4ZZ_S, + 6279 => Opcode::SMAX_ZI_B, + 6280 => Opcode::SMAX_ZI_D, + 6281 => Opcode::SMAX_ZI_H, + 6282 => Opcode::SMAX_ZI_S, + 6283 => Opcode::SMAX_ZPmZ_B, + 6284 => Opcode::SMAX_ZPmZ_D, + 6285 => Opcode::SMAX_ZPmZ_H, + 6286 => Opcode::SMAX_ZPmZ_S, + 6287 => Opcode::SMAXv16i8, + 6288 => Opcode::SMAXv2i32, + 6289 => Opcode::SMAXv4i16, + 6290 => Opcode::SMAXv4i32, + 6291 => Opcode::SMAXv8i16, + 6292 => Opcode::SMAXv8i8, + 6293 => Opcode::SMC, + 6294 => Opcode::SMINP_ZPmZ_B, + 6295 => Opcode::SMINP_ZPmZ_D, + 6296 => Opcode::SMINP_ZPmZ_H, + 6297 => Opcode::SMINP_ZPmZ_S, + 6298 => Opcode::SMINPv16i8, + 6299 => Opcode::SMINPv2i32, + 6300 => Opcode::SMINPv4i16, + 6301 => Opcode::SMINPv4i32, + 6302 => Opcode::SMINPv8i16, + 6303 => Opcode::SMINPv8i8, + 6304 => Opcode::SMINQV_VPZ_B, + 6305 => Opcode::SMINQV_VPZ_D, + 6306 => Opcode::SMINQV_VPZ_H, + 6307 => Opcode::SMINQV_VPZ_S, + 6308 => Opcode::SMINV_VPZ_B, + 6309 => Opcode::SMINV_VPZ_D, + 6310 => Opcode::SMINV_VPZ_H, + 6311 => Opcode::SMINV_VPZ_S, + 6312 => Opcode::SMINVv16i8v, + 6313 => Opcode::SMINVv4i16v, + 6314 => Opcode::SMINVv4i32v, + 6315 => Opcode::SMINVv8i16v, + 6316 => Opcode::SMINVv8i8v, + 6317 => Opcode::SMINWri, + 6318 => Opcode::SMINWrr, + 6319 => Opcode::SMINXri, + 6320 => Opcode::SMINXrr, + 6321 => Opcode::SMIN_VG2_2Z2Z_B, + 6322 => Opcode::SMIN_VG2_2Z2Z_D, + 6323 => Opcode::SMIN_VG2_2Z2Z_H, + 6324 => Opcode::SMIN_VG2_2Z2Z_S, + 6325 => Opcode::SMIN_VG2_2ZZ_B, + 6326 => Opcode::SMIN_VG2_2ZZ_D, + 6327 => Opcode::SMIN_VG2_2ZZ_H, + 6328 => Opcode::SMIN_VG2_2ZZ_S, + 6329 => Opcode::SMIN_VG4_4Z4Z_B, + 6330 => Opcode::SMIN_VG4_4Z4Z_D, + 6331 => Opcode::SMIN_VG4_4Z4Z_H, + 6332 => Opcode::SMIN_VG4_4Z4Z_S, + 6333 => Opcode::SMIN_VG4_4ZZ_B, + 6334 => Opcode::SMIN_VG4_4ZZ_D, + 6335 => Opcode::SMIN_VG4_4ZZ_H, + 6336 => Opcode::SMIN_VG4_4ZZ_S, + 6337 => Opcode::SMIN_ZI_B, + 6338 => Opcode::SMIN_ZI_D, + 6339 => Opcode::SMIN_ZI_H, + 6340 => Opcode::SMIN_ZI_S, + 6341 => Opcode::SMIN_ZPmZ_B, + 6342 => Opcode::SMIN_ZPmZ_D, + 6343 => Opcode::SMIN_ZPmZ_H, + 6344 => Opcode::SMIN_ZPmZ_S, + 6345 => Opcode::SMINv16i8, + 6346 => Opcode::SMINv2i32, + 6347 => Opcode::SMINv4i16, + 6348 => Opcode::SMINv4i32, + 6349 => Opcode::SMINv8i16, + 6350 => Opcode::SMINv8i8, + 6351 => Opcode::SMLALB_ZZZI_D, + 6352 => Opcode::SMLALB_ZZZI_S, + 6353 => Opcode::SMLALB_ZZZ_D, + 6354 => Opcode::SMLALB_ZZZ_H, + 6355 => Opcode::SMLALB_ZZZ_S, + 6356 => Opcode::SMLALL_MZZI_BtoS, + 6357 => Opcode::SMLALL_MZZI_HtoD, + 6358 => Opcode::SMLALL_MZZ_BtoS, + 6359 => Opcode::SMLALL_MZZ_HtoD, + 6360 => Opcode::SMLALL_VG2_M2Z2Z_BtoS, + 6361 => Opcode::SMLALL_VG2_M2Z2Z_HtoD, + 6362 => Opcode::SMLALL_VG2_M2ZZI_BtoS, + 6363 => Opcode::SMLALL_VG2_M2ZZI_HtoD, + 6364 => Opcode::SMLALL_VG2_M2ZZ_BtoS, + 6365 => Opcode::SMLALL_VG2_M2ZZ_HtoD, + 6366 => Opcode::SMLALL_VG4_M4Z4Z_BtoS, + 6367 => Opcode::SMLALL_VG4_M4Z4Z_HtoD, + 6368 => Opcode::SMLALL_VG4_M4ZZI_BtoS, + 6369 => Opcode::SMLALL_VG4_M4ZZI_HtoD, + 6370 => Opcode::SMLALL_VG4_M4ZZ_BtoS, + 6371 => Opcode::SMLALL_VG4_M4ZZ_HtoD, + 6372 => Opcode::SMLALT_ZZZI_D, + 6373 => Opcode::SMLALT_ZZZI_S, + 6374 => Opcode::SMLALT_ZZZ_D, + 6375 => Opcode::SMLALT_ZZZ_H, + 6376 => Opcode::SMLALT_ZZZ_S, + 6377 => Opcode::SMLAL_MZZI_HtoS, + 6378 => Opcode::SMLAL_MZZ_HtoS, + 6379 => Opcode::SMLAL_VG2_M2Z2Z_HtoS, + 6380 => Opcode::SMLAL_VG2_M2ZZI_S, + 6381 => Opcode::SMLAL_VG2_M2ZZ_HtoS, + 6382 => Opcode::SMLAL_VG4_M4Z4Z_HtoS, + 6383 => Opcode::SMLAL_VG4_M4ZZI_HtoS, + 6384 => Opcode::SMLAL_VG4_M4ZZ_HtoS, + 6385 => Opcode::SMLALv16i8_v8i16, + 6386 => Opcode::SMLALv2i32_indexed, + 6387 => Opcode::SMLALv2i32_v2i64, + 6388 => Opcode::SMLALv4i16_indexed, + 6389 => Opcode::SMLALv4i16_v4i32, + 6390 => Opcode::SMLALv4i32_indexed, + 6391 => Opcode::SMLALv4i32_v2i64, + 6392 => Opcode::SMLALv8i16_indexed, + 6393 => Opcode::SMLALv8i16_v4i32, + 6394 => Opcode::SMLALv8i8_v8i16, + 6395 => Opcode::SMLSLB_ZZZI_D, + 6396 => Opcode::SMLSLB_ZZZI_S, + 6397 => Opcode::SMLSLB_ZZZ_D, + 6398 => Opcode::SMLSLB_ZZZ_H, + 6399 => Opcode::SMLSLB_ZZZ_S, + 6400 => Opcode::SMLSLL_MZZI_BtoS, + 6401 => Opcode::SMLSLL_MZZI_HtoD, + 6402 => Opcode::SMLSLL_MZZ_BtoS, + 6403 => Opcode::SMLSLL_MZZ_HtoD, + 6404 => Opcode::SMLSLL_VG2_M2Z2Z_BtoS, + 6405 => Opcode::SMLSLL_VG2_M2Z2Z_HtoD, + 6406 => Opcode::SMLSLL_VG2_M2ZZI_BtoS, + 6407 => Opcode::SMLSLL_VG2_M2ZZI_HtoD, + 6408 => Opcode::SMLSLL_VG2_M2ZZ_BtoS, + 6409 => Opcode::SMLSLL_VG2_M2ZZ_HtoD, + 6410 => Opcode::SMLSLL_VG4_M4Z4Z_BtoS, + 6411 => Opcode::SMLSLL_VG4_M4Z4Z_HtoD, + 6412 => Opcode::SMLSLL_VG4_M4ZZI_BtoS, + 6413 => Opcode::SMLSLL_VG4_M4ZZI_HtoD, + 6414 => Opcode::SMLSLL_VG4_M4ZZ_BtoS, + 6415 => Opcode::SMLSLL_VG4_M4ZZ_HtoD, + 6416 => Opcode::SMLSLT_ZZZI_D, + 6417 => Opcode::SMLSLT_ZZZI_S, + 6418 => Opcode::SMLSLT_ZZZ_D, + 6419 => Opcode::SMLSLT_ZZZ_H, + 6420 => Opcode::SMLSLT_ZZZ_S, + 6421 => Opcode::SMLSL_MZZI_HtoS, + 6422 => Opcode::SMLSL_MZZ_HtoS, + 6423 => Opcode::SMLSL_VG2_M2Z2Z_HtoS, + 6424 => Opcode::SMLSL_VG2_M2ZZI_S, + 6425 => Opcode::SMLSL_VG2_M2ZZ_HtoS, + 6426 => Opcode::SMLSL_VG4_M4Z4Z_HtoS, + 6427 => Opcode::SMLSL_VG4_M4ZZI_HtoS, + 6428 => Opcode::SMLSL_VG4_M4ZZ_HtoS, + 6429 => Opcode::SMLSLv16i8_v8i16, + 6430 => Opcode::SMLSLv2i32_indexed, + 6431 => Opcode::SMLSLv2i32_v2i64, + 6432 => Opcode::SMLSLv4i16_indexed, + 6433 => Opcode::SMLSLv4i16_v4i32, + 6434 => Opcode::SMLSLv4i32_indexed, + 6435 => Opcode::SMLSLv4i32_v2i64, + 6436 => Opcode::SMLSLv8i16_indexed, + 6437 => Opcode::SMLSLv8i16_v4i32, + 6438 => Opcode::SMLSLv8i8_v8i16, + 6439 => Opcode::SMMLA, + 6440 => Opcode::SMMLA_ZZZ, + 6441 => Opcode::SMOP4A_M2Z2Z_BToS, + 6442 => Opcode::SMOP4A_M2Z2Z_HToS, + 6443 => Opcode::SMOP4A_M2Z2Z_HtoD, + 6444 => Opcode::SMOP4A_M2ZZ_BToS, + 6445 => Opcode::SMOP4A_M2ZZ_HToS, + 6446 => Opcode::SMOP4A_M2ZZ_HtoD, + 6447 => Opcode::SMOP4A_MZ2Z_BToS, + 6448 => Opcode::SMOP4A_MZ2Z_HToS, + 6449 => Opcode::SMOP4A_MZ2Z_HtoD, + 6450 => Opcode::SMOP4A_MZZ_BToS, + 6451 => Opcode::SMOP4A_MZZ_HToS, + 6452 => Opcode::SMOP4A_MZZ_HtoD, + 6453 => Opcode::SMOP4S_M2Z2Z_BToS, + 6454 => Opcode::SMOP4S_M2Z2Z_HToS, + 6455 => Opcode::SMOP4S_M2Z2Z_HtoD, + 6456 => Opcode::SMOP4S_M2ZZ_BToS, + 6457 => Opcode::SMOP4S_M2ZZ_HToS, + 6458 => Opcode::SMOP4S_M2ZZ_HtoD, + 6459 => Opcode::SMOP4S_MZ2Z_BToS, + 6460 => Opcode::SMOP4S_MZ2Z_HToS, + 6461 => Opcode::SMOP4S_MZ2Z_HtoD, + 6462 => Opcode::SMOP4S_MZZ_BToS, + 6463 => Opcode::SMOP4S_MZZ_HToS, + 6464 => Opcode::SMOP4S_MZZ_HtoD, + 6465 => Opcode::SMOPA_MPPZZ_D, + 6466 => Opcode::SMOPA_MPPZZ_HtoS, + 6467 => Opcode::SMOPA_MPPZZ_S, + 6468 => Opcode::SMOPS_MPPZZ_D, + 6469 => Opcode::SMOPS_MPPZZ_HtoS, + 6470 => Opcode::SMOPS_MPPZZ_S, + 6471 => Opcode::SMOVvi16to32, + 6472 => Opcode::SMOVvi16to32_idx0, + 6473 => Opcode::SMOVvi16to64, + 6474 => Opcode::SMOVvi16to64_idx0, + 6475 => Opcode::SMOVvi32to64, + 6476 => Opcode::SMOVvi32to64_idx0, + 6477 => Opcode::SMOVvi8to32, + 6478 => Opcode::SMOVvi8to32_idx0, + 6479 => Opcode::SMOVvi8to64, + 6480 => Opcode::SMOVvi8to64_idx0, + 6481 => Opcode::SMSUBLrrr, + 6482 => Opcode::SMULH_ZPmZ_B, + 6483 => Opcode::SMULH_ZPmZ_D, + 6484 => Opcode::SMULH_ZPmZ_H, + 6485 => Opcode::SMULH_ZPmZ_S, + 6486 => Opcode::SMULH_ZZZ_B, + 6487 => Opcode::SMULH_ZZZ_D, + 6488 => Opcode::SMULH_ZZZ_H, + 6489 => Opcode::SMULH_ZZZ_S, + 6490 => Opcode::SMULHrr, + 6491 => Opcode::SMULLB_ZZZI_D, + 6492 => Opcode::SMULLB_ZZZI_S, + 6493 => Opcode::SMULLB_ZZZ_D, + 6494 => Opcode::SMULLB_ZZZ_H, + 6495 => Opcode::SMULLB_ZZZ_S, + 6496 => Opcode::SMULLT_ZZZI_D, + 6497 => Opcode::SMULLT_ZZZI_S, + 6498 => Opcode::SMULLT_ZZZ_D, + 6499 => Opcode::SMULLT_ZZZ_H, + 6500 => Opcode::SMULLT_ZZZ_S, + 6501 => Opcode::SMULLv16i8_v8i16, + 6502 => Opcode::SMULLv2i32_indexed, + 6503 => Opcode::SMULLv2i32_v2i64, + 6504 => Opcode::SMULLv4i16_indexed, + 6505 => Opcode::SMULLv4i16_v4i32, + 6506 => Opcode::SMULLv4i32_indexed, + 6507 => Opcode::SMULLv4i32_v2i64, + 6508 => Opcode::SMULLv8i16_indexed, + 6509 => Opcode::SMULLv8i16_v4i32, + 6510 => Opcode::SMULLv8i8_v8i16, + 6511 => Opcode::SPLICE_ZPZZ_B, + 6512 => Opcode::SPLICE_ZPZZ_D, + 6513 => Opcode::SPLICE_ZPZZ_H, + 6514 => Opcode::SPLICE_ZPZZ_S, + 6515 => Opcode::SPLICE_ZPZ_B, + 6516 => Opcode::SPLICE_ZPZ_D, + 6517 => Opcode::SPLICE_ZPZ_H, + 6518 => Opcode::SPLICE_ZPZ_S, + 6519 => Opcode::SQABS_ZPmZ_B, + 6520 => Opcode::SQABS_ZPmZ_D, + 6521 => Opcode::SQABS_ZPmZ_H, + 6522 => Opcode::SQABS_ZPmZ_S, + 6523 => Opcode::SQABS_ZPzZ_B, + 6524 => Opcode::SQABS_ZPzZ_D, + 6525 => Opcode::SQABS_ZPzZ_H, + 6526 => Opcode::SQABS_ZPzZ_S, + 6527 => Opcode::SQABSv16i8, + 6528 => Opcode::SQABSv1i16, + 6529 => Opcode::SQABSv1i32, + 6530 => Opcode::SQABSv1i64, + 6531 => Opcode::SQABSv1i8, + 6532 => Opcode::SQABSv2i32, + 6533 => Opcode::SQABSv2i64, + 6534 => Opcode::SQABSv4i16, + 6535 => Opcode::SQABSv4i32, + 6536 => Opcode::SQABSv8i16, + 6537 => Opcode::SQABSv8i8, + 6538 => Opcode::SQADD_ZI_B, + 6539 => Opcode::SQADD_ZI_D, + 6540 => Opcode::SQADD_ZI_H, + 6541 => Opcode::SQADD_ZI_S, + 6542 => Opcode::SQADD_ZPmZ_B, + 6543 => Opcode::SQADD_ZPmZ_D, + 6544 => Opcode::SQADD_ZPmZ_H, + 6545 => Opcode::SQADD_ZPmZ_S, + 6546 => Opcode::SQADD_ZZZ_B, + 6547 => Opcode::SQADD_ZZZ_D, + 6548 => Opcode::SQADD_ZZZ_H, + 6549 => Opcode::SQADD_ZZZ_S, + 6550 => Opcode::SQADDv16i8, + 6551 => Opcode::SQADDv1i16, + 6552 => Opcode::SQADDv1i32, + 6553 => Opcode::SQADDv1i64, + 6554 => Opcode::SQADDv1i8, + 6555 => Opcode::SQADDv2i32, + 6556 => Opcode::SQADDv2i64, + 6557 => Opcode::SQADDv4i16, + 6558 => Opcode::SQADDv4i32, + 6559 => Opcode::SQADDv8i16, + 6560 => Opcode::SQADDv8i8, + 6561 => Opcode::SQCADD_ZZI_B, + 6562 => Opcode::SQCADD_ZZI_D, + 6563 => Opcode::SQCADD_ZZI_H, + 6564 => Opcode::SQCADD_ZZI_S, + 6565 => Opcode::SQCVTN_Z2Z_StoH, + 6566 => Opcode::SQCVTN_Z4Z_DtoH, + 6567 => Opcode::SQCVTN_Z4Z_StoB, + 6568 => Opcode::SQCVTUN_Z2Z_StoH, + 6569 => Opcode::SQCVTUN_Z4Z_DtoH, + 6570 => Opcode::SQCVTUN_Z4Z_StoB, + 6571 => Opcode::SQCVTU_Z2Z_StoH, + 6572 => Opcode::SQCVTU_Z4Z_DtoH, + 6573 => Opcode::SQCVTU_Z4Z_StoB, + 6574 => Opcode::SQCVT_Z2Z_StoH, + 6575 => Opcode::SQCVT_Z4Z_DtoH, + 6576 => Opcode::SQCVT_Z4Z_StoB, + 6577 => Opcode::SQDECB_XPiI, + 6578 => Opcode::SQDECB_XPiWdI, + 6579 => Opcode::SQDECD_XPiI, + 6580 => Opcode::SQDECD_XPiWdI, + 6581 => Opcode::SQDECD_ZPiI, + 6582 => Opcode::SQDECH_XPiI, + 6583 => Opcode::SQDECH_XPiWdI, + 6584 => Opcode::SQDECH_ZPiI, + 6585 => Opcode::SQDECP_XPWd_B, + 6586 => Opcode::SQDECP_XPWd_D, + 6587 => Opcode::SQDECP_XPWd_H, + 6588 => Opcode::SQDECP_XPWd_S, + 6589 => Opcode::SQDECP_XP_B, + 6590 => Opcode::SQDECP_XP_D, + 6591 => Opcode::SQDECP_XP_H, + 6592 => Opcode::SQDECP_XP_S, + 6593 => Opcode::SQDECP_ZP_D, + 6594 => Opcode::SQDECP_ZP_H, + 6595 => Opcode::SQDECP_ZP_S, + 6596 => Opcode::SQDECW_XPiI, + 6597 => Opcode::SQDECW_XPiWdI, + 6598 => Opcode::SQDECW_ZPiI, + 6599 => Opcode::SQDMLALBT_ZZZ_D, + 6600 => Opcode::SQDMLALBT_ZZZ_H, + 6601 => Opcode::SQDMLALBT_ZZZ_S, + 6602 => Opcode::SQDMLALB_ZZZI_D, + 6603 => Opcode::SQDMLALB_ZZZI_S, + 6604 => Opcode::SQDMLALB_ZZZ_D, + 6605 => Opcode::SQDMLALB_ZZZ_H, + 6606 => Opcode::SQDMLALB_ZZZ_S, + 6607 => Opcode::SQDMLALT_ZZZI_D, + 6608 => Opcode::SQDMLALT_ZZZI_S, + 6609 => Opcode::SQDMLALT_ZZZ_D, + 6610 => Opcode::SQDMLALT_ZZZ_H, + 6611 => Opcode::SQDMLALT_ZZZ_S, + 6612 => Opcode::SQDMLALi16, + 6613 => Opcode::SQDMLALi32, + 6614 => Opcode::SQDMLALv1i32_indexed, + 6615 => Opcode::SQDMLALv1i64_indexed, + 6616 => Opcode::SQDMLALv2i32_indexed, + 6617 => Opcode::SQDMLALv2i32_v2i64, + 6618 => Opcode::SQDMLALv4i16_indexed, + 6619 => Opcode::SQDMLALv4i16_v4i32, + 6620 => Opcode::SQDMLALv4i32_indexed, + 6621 => Opcode::SQDMLALv4i32_v2i64, + 6622 => Opcode::SQDMLALv8i16_indexed, + 6623 => Opcode::SQDMLALv8i16_v4i32, + 6624 => Opcode::SQDMLSLBT_ZZZ_D, + 6625 => Opcode::SQDMLSLBT_ZZZ_H, + 6626 => Opcode::SQDMLSLBT_ZZZ_S, + 6627 => Opcode::SQDMLSLB_ZZZI_D, + 6628 => Opcode::SQDMLSLB_ZZZI_S, + 6629 => Opcode::SQDMLSLB_ZZZ_D, + 6630 => Opcode::SQDMLSLB_ZZZ_H, + 6631 => Opcode::SQDMLSLB_ZZZ_S, + 6632 => Opcode::SQDMLSLT_ZZZI_D, + 6633 => Opcode::SQDMLSLT_ZZZI_S, + 6634 => Opcode::SQDMLSLT_ZZZ_D, + 6635 => Opcode::SQDMLSLT_ZZZ_H, + 6636 => Opcode::SQDMLSLT_ZZZ_S, + 6637 => Opcode::SQDMLSLi16, + 6638 => Opcode::SQDMLSLi32, + 6639 => Opcode::SQDMLSLv1i32_indexed, + 6640 => Opcode::SQDMLSLv1i64_indexed, + 6641 => Opcode::SQDMLSLv2i32_indexed, + 6642 => Opcode::SQDMLSLv2i32_v2i64, + 6643 => Opcode::SQDMLSLv4i16_indexed, + 6644 => Opcode::SQDMLSLv4i16_v4i32, + 6645 => Opcode::SQDMLSLv4i32_indexed, + 6646 => Opcode::SQDMLSLv4i32_v2i64, + 6647 => Opcode::SQDMLSLv8i16_indexed, + 6648 => Opcode::SQDMLSLv8i16_v4i32, + 6649 => Opcode::SQDMULH_VG2_2Z2Z_B, + 6650 => Opcode::SQDMULH_VG2_2Z2Z_D, + 6651 => Opcode::SQDMULH_VG2_2Z2Z_H, + 6652 => Opcode::SQDMULH_VG2_2Z2Z_S, + 6653 => Opcode::SQDMULH_VG2_2ZZ_B, + 6654 => Opcode::SQDMULH_VG2_2ZZ_D, + 6655 => Opcode::SQDMULH_VG2_2ZZ_H, + 6656 => Opcode::SQDMULH_VG2_2ZZ_S, + 6657 => Opcode::SQDMULH_VG4_4Z4Z_B, + 6658 => Opcode::SQDMULH_VG4_4Z4Z_D, + 6659 => Opcode::SQDMULH_VG4_4Z4Z_H, + 6660 => Opcode::SQDMULH_VG4_4Z4Z_S, + 6661 => Opcode::SQDMULH_VG4_4ZZ_B, + 6662 => Opcode::SQDMULH_VG4_4ZZ_D, + 6663 => Opcode::SQDMULH_VG4_4ZZ_H, + 6664 => Opcode::SQDMULH_VG4_4ZZ_S, + 6665 => Opcode::SQDMULH_ZZZI_D, + 6666 => Opcode::SQDMULH_ZZZI_H, + 6667 => Opcode::SQDMULH_ZZZI_S, + 6668 => Opcode::SQDMULH_ZZZ_B, + 6669 => Opcode::SQDMULH_ZZZ_D, + 6670 => Opcode::SQDMULH_ZZZ_H, + 6671 => Opcode::SQDMULH_ZZZ_S, + 6672 => Opcode::SQDMULHv1i16, + 6673 => Opcode::SQDMULHv1i16_indexed, + 6674 => Opcode::SQDMULHv1i32, + 6675 => Opcode::SQDMULHv1i32_indexed, + 6676 => Opcode::SQDMULHv2i32, + 6677 => Opcode::SQDMULHv2i32_indexed, + 6678 => Opcode::SQDMULHv4i16, + 6679 => Opcode::SQDMULHv4i16_indexed, + 6680 => Opcode::SQDMULHv4i32, + 6681 => Opcode::SQDMULHv4i32_indexed, + 6682 => Opcode::SQDMULHv8i16, + 6683 => Opcode::SQDMULHv8i16_indexed, + 6684 => Opcode::SQDMULLB_ZZZI_D, + 6685 => Opcode::SQDMULLB_ZZZI_S, + 6686 => Opcode::SQDMULLB_ZZZ_D, + 6687 => Opcode::SQDMULLB_ZZZ_H, + 6688 => Opcode::SQDMULLB_ZZZ_S, + 6689 => Opcode::SQDMULLT_ZZZI_D, + 6690 => Opcode::SQDMULLT_ZZZI_S, + 6691 => Opcode::SQDMULLT_ZZZ_D, + 6692 => Opcode::SQDMULLT_ZZZ_H, + 6693 => Opcode::SQDMULLT_ZZZ_S, + 6694 => Opcode::SQDMULLi16, + 6695 => Opcode::SQDMULLi32, + 6696 => Opcode::SQDMULLv1i32_indexed, + 6697 => Opcode::SQDMULLv1i64_indexed, + 6698 => Opcode::SQDMULLv2i32_indexed, + 6699 => Opcode::SQDMULLv2i32_v2i64, + 6700 => Opcode::SQDMULLv4i16_indexed, + 6701 => Opcode::SQDMULLv4i16_v4i32, + 6702 => Opcode::SQDMULLv4i32_indexed, + 6703 => Opcode::SQDMULLv4i32_v2i64, + 6704 => Opcode::SQDMULLv8i16_indexed, + 6705 => Opcode::SQDMULLv8i16_v4i32, + 6706 => Opcode::SQINCB_XPiI, + 6707 => Opcode::SQINCB_XPiWdI, + 6708 => Opcode::SQINCD_XPiI, + 6709 => Opcode::SQINCD_XPiWdI, + 6710 => Opcode::SQINCD_ZPiI, + 6711 => Opcode::SQINCH_XPiI, + 6712 => Opcode::SQINCH_XPiWdI, + 6713 => Opcode::SQINCH_ZPiI, + 6714 => Opcode::SQINCP_XPWd_B, + 6715 => Opcode::SQINCP_XPWd_D, + 6716 => Opcode::SQINCP_XPWd_H, + 6717 => Opcode::SQINCP_XPWd_S, + 6718 => Opcode::SQINCP_XP_B, + 6719 => Opcode::SQINCP_XP_D, + 6720 => Opcode::SQINCP_XP_H, + 6721 => Opcode::SQINCP_XP_S, + 6722 => Opcode::SQINCP_ZP_D, + 6723 => Opcode::SQINCP_ZP_H, + 6724 => Opcode::SQINCP_ZP_S, + 6725 => Opcode::SQINCW_XPiI, + 6726 => Opcode::SQINCW_XPiWdI, + 6727 => Opcode::SQINCW_ZPiI, + 6728 => Opcode::SQNEG_ZPmZ_B, + 6729 => Opcode::SQNEG_ZPmZ_D, + 6730 => Opcode::SQNEG_ZPmZ_H, + 6731 => Opcode::SQNEG_ZPmZ_S, + 6732 => Opcode::SQNEG_ZPzZ_B, + 6733 => Opcode::SQNEG_ZPzZ_D, + 6734 => Opcode::SQNEG_ZPzZ_H, + 6735 => Opcode::SQNEG_ZPzZ_S, + 6736 => Opcode::SQNEGv16i8, + 6737 => Opcode::SQNEGv1i16, + 6738 => Opcode::SQNEGv1i32, + 6739 => Opcode::SQNEGv1i64, + 6740 => Opcode::SQNEGv1i8, + 6741 => Opcode::SQNEGv2i32, + 6742 => Opcode::SQNEGv2i64, + 6743 => Opcode::SQNEGv4i16, + 6744 => Opcode::SQNEGv4i32, + 6745 => Opcode::SQNEGv8i16, + 6746 => Opcode::SQNEGv8i8, + 6747 => Opcode::SQRDCMLAH_ZZZI_H, + 6748 => Opcode::SQRDCMLAH_ZZZI_S, + 6749 => Opcode::SQRDCMLAH_ZZZ_B, + 6750 => Opcode::SQRDCMLAH_ZZZ_D, + 6751 => Opcode::SQRDCMLAH_ZZZ_H, + 6752 => Opcode::SQRDCMLAH_ZZZ_S, + 6753 => Opcode::SQRDMLAH_ZZZI_D, + 6754 => Opcode::SQRDMLAH_ZZZI_H, + 6755 => Opcode::SQRDMLAH_ZZZI_S, + 6756 => Opcode::SQRDMLAH_ZZZ_B, + 6757 => Opcode::SQRDMLAH_ZZZ_D, + 6758 => Opcode::SQRDMLAH_ZZZ_H, + 6759 => Opcode::SQRDMLAH_ZZZ_S, + 6760 => Opcode::SQRDMLAHv1i16, + 6761 => Opcode::SQRDMLAHv1i16_indexed, + 6762 => Opcode::SQRDMLAHv1i32, + 6763 => Opcode::SQRDMLAHv1i32_indexed, + 6764 => Opcode::SQRDMLAHv2i32, + 6765 => Opcode::SQRDMLAHv2i32_indexed, + 6766 => Opcode::SQRDMLAHv4i16, + 6767 => Opcode::SQRDMLAHv4i16_indexed, + 6768 => Opcode::SQRDMLAHv4i32, + 6769 => Opcode::SQRDMLAHv4i32_indexed, + 6770 => Opcode::SQRDMLAHv8i16, + 6771 => Opcode::SQRDMLAHv8i16_indexed, + 6772 => Opcode::SQRDMLSH_ZZZI_D, + 6773 => Opcode::SQRDMLSH_ZZZI_H, + 6774 => Opcode::SQRDMLSH_ZZZI_S, + 6775 => Opcode::SQRDMLSH_ZZZ_B, + 6776 => Opcode::SQRDMLSH_ZZZ_D, + 6777 => Opcode::SQRDMLSH_ZZZ_H, + 6778 => Opcode::SQRDMLSH_ZZZ_S, + 6779 => Opcode::SQRDMLSHv1i16, + 6780 => Opcode::SQRDMLSHv1i16_indexed, + 6781 => Opcode::SQRDMLSHv1i32, + 6782 => Opcode::SQRDMLSHv1i32_indexed, + 6783 => Opcode::SQRDMLSHv2i32, + 6784 => Opcode::SQRDMLSHv2i32_indexed, + 6785 => Opcode::SQRDMLSHv4i16, + 6786 => Opcode::SQRDMLSHv4i16_indexed, + 6787 => Opcode::SQRDMLSHv4i32, + 6788 => Opcode::SQRDMLSHv4i32_indexed, + 6789 => Opcode::SQRDMLSHv8i16, + 6790 => Opcode::SQRDMLSHv8i16_indexed, + 6791 => Opcode::SQRDMULH_ZZZI_D, + 6792 => Opcode::SQRDMULH_ZZZI_H, + 6793 => Opcode::SQRDMULH_ZZZI_S, + 6794 => Opcode::SQRDMULH_ZZZ_B, + 6795 => Opcode::SQRDMULH_ZZZ_D, + 6796 => Opcode::SQRDMULH_ZZZ_H, + 6797 => Opcode::SQRDMULH_ZZZ_S, + 6798 => Opcode::SQRDMULHv1i16, + 6799 => Opcode::SQRDMULHv1i16_indexed, + 6800 => Opcode::SQRDMULHv1i32, + 6801 => Opcode::SQRDMULHv1i32_indexed, + 6802 => Opcode::SQRDMULHv2i32, + 6803 => Opcode::SQRDMULHv2i32_indexed, + 6804 => Opcode::SQRDMULHv4i16, + 6805 => Opcode::SQRDMULHv4i16_indexed, + 6806 => Opcode::SQRDMULHv4i32, + 6807 => Opcode::SQRDMULHv4i32_indexed, + 6808 => Opcode::SQRDMULHv8i16, + 6809 => Opcode::SQRDMULHv8i16_indexed, + 6810 => Opcode::SQRSHLR_ZPmZ_B, + 6811 => Opcode::SQRSHLR_ZPmZ_D, + 6812 => Opcode::SQRSHLR_ZPmZ_H, + 6813 => Opcode::SQRSHLR_ZPmZ_S, + 6814 => Opcode::SQRSHL_ZPmZ_B, + 6815 => Opcode::SQRSHL_ZPmZ_D, + 6816 => Opcode::SQRSHL_ZPmZ_H, + 6817 => Opcode::SQRSHL_ZPmZ_S, + 6818 => Opcode::SQRSHLv16i8, + 6819 => Opcode::SQRSHLv1i16, + 6820 => Opcode::SQRSHLv1i32, + 6821 => Opcode::SQRSHLv1i64, + 6822 => Opcode::SQRSHLv1i8, + 6823 => Opcode::SQRSHLv2i32, + 6824 => Opcode::SQRSHLv2i64, + 6825 => Opcode::SQRSHLv4i16, + 6826 => Opcode::SQRSHLv4i32, + 6827 => Opcode::SQRSHLv8i16, + 6828 => Opcode::SQRSHLv8i8, + 6829 => Opcode::SQRSHRNB_ZZI_B, + 6830 => Opcode::SQRSHRNB_ZZI_H, + 6831 => Opcode::SQRSHRNB_ZZI_S, + 6832 => Opcode::SQRSHRNT_ZZI_B, + 6833 => Opcode::SQRSHRNT_ZZI_H, + 6834 => Opcode::SQRSHRNT_ZZI_S, + 6835 => Opcode::SQRSHRN_VG4_Z4ZI_B, + 6836 => Opcode::SQRSHRN_VG4_Z4ZI_H, + 6837 => Opcode::SQRSHRN_Z2ZI_HtoB, + 6838 => Opcode::SQRSHRN_Z2ZI_StoH, + 6839 => Opcode::SQRSHRNb, + 6840 => Opcode::SQRSHRNh, + 6841 => Opcode::SQRSHRNs, + 6842 => Opcode::SQRSHRNv16i8_shift, + 6843 => Opcode::SQRSHRNv2i32_shift, + 6844 => Opcode::SQRSHRNv4i16_shift, + 6845 => Opcode::SQRSHRNv4i32_shift, + 6846 => Opcode::SQRSHRNv8i16_shift, + 6847 => Opcode::SQRSHRNv8i8_shift, + 6848 => Opcode::SQRSHRUNB_ZZI_B, + 6849 => Opcode::SQRSHRUNB_ZZI_H, + 6850 => Opcode::SQRSHRUNB_ZZI_S, + 6851 => Opcode::SQRSHRUNT_ZZI_B, + 6852 => Opcode::SQRSHRUNT_ZZI_H, + 6853 => Opcode::SQRSHRUNT_ZZI_S, + 6854 => Opcode::SQRSHRUN_VG4_Z4ZI_B, + 6855 => Opcode::SQRSHRUN_VG4_Z4ZI_H, + 6856 => Opcode::SQRSHRUN_Z2ZI_HtoB, + 6857 => Opcode::SQRSHRUN_Z2ZI_StoH, + 6858 => Opcode::SQRSHRUNb, + 6859 => Opcode::SQRSHRUNh, + 6860 => Opcode::SQRSHRUNs, + 6861 => Opcode::SQRSHRUNv16i8_shift, + 6862 => Opcode::SQRSHRUNv2i32_shift, + 6863 => Opcode::SQRSHRUNv4i16_shift, + 6864 => Opcode::SQRSHRUNv4i32_shift, + 6865 => Opcode::SQRSHRUNv8i16_shift, + 6866 => Opcode::SQRSHRUNv8i8_shift, + 6867 => Opcode::SQRSHRU_VG2_Z2ZI_H, + 6868 => Opcode::SQRSHRU_VG4_Z4ZI_B, + 6869 => Opcode::SQRSHRU_VG4_Z4ZI_H, + 6870 => Opcode::SQRSHR_VG2_Z2ZI_H, + 6871 => Opcode::SQRSHR_VG4_Z4ZI_B, + 6872 => Opcode::SQRSHR_VG4_Z4ZI_H, + 6873 => Opcode::SQSHLR_ZPmZ_B, + 6874 => Opcode::SQSHLR_ZPmZ_D, + 6875 => Opcode::SQSHLR_ZPmZ_H, + 6876 => Opcode::SQSHLR_ZPmZ_S, + 6877 => Opcode::SQSHLU_ZPmI_B, + 6878 => Opcode::SQSHLU_ZPmI_D, + 6879 => Opcode::SQSHLU_ZPmI_H, + 6880 => Opcode::SQSHLU_ZPmI_S, + 6881 => Opcode::SQSHLUb, + 6882 => Opcode::SQSHLUd, + 6883 => Opcode::SQSHLUh, + 6884 => Opcode::SQSHLUs, + 6885 => Opcode::SQSHLUv16i8_shift, + 6886 => Opcode::SQSHLUv2i32_shift, + 6887 => Opcode::SQSHLUv2i64_shift, + 6888 => Opcode::SQSHLUv4i16_shift, + 6889 => Opcode::SQSHLUv4i32_shift, + 6890 => Opcode::SQSHLUv8i16_shift, + 6891 => Opcode::SQSHLUv8i8_shift, + 6892 => Opcode::SQSHL_ZPmI_B, + 6893 => Opcode::SQSHL_ZPmI_D, + 6894 => Opcode::SQSHL_ZPmI_H, + 6895 => Opcode::SQSHL_ZPmI_S, + 6896 => Opcode::SQSHL_ZPmZ_B, + 6897 => Opcode::SQSHL_ZPmZ_D, + 6898 => Opcode::SQSHL_ZPmZ_H, + 6899 => Opcode::SQSHL_ZPmZ_S, + 6900 => Opcode::SQSHLb, + 6901 => Opcode::SQSHLd, + 6902 => Opcode::SQSHLh, + 6903 => Opcode::SQSHLs, + 6904 => Opcode::SQSHLv16i8, + 6905 => Opcode::SQSHLv16i8_shift, + 6906 => Opcode::SQSHLv1i16, + 6907 => Opcode::SQSHLv1i32, + 6908 => Opcode::SQSHLv1i64, + 6909 => Opcode::SQSHLv1i8, + 6910 => Opcode::SQSHLv2i32, + 6911 => Opcode::SQSHLv2i32_shift, + 6912 => Opcode::SQSHLv2i64, + 6913 => Opcode::SQSHLv2i64_shift, + 6914 => Opcode::SQSHLv4i16, + 6915 => Opcode::SQSHLv4i16_shift, + 6916 => Opcode::SQSHLv4i32, + 6917 => Opcode::SQSHLv4i32_shift, + 6918 => Opcode::SQSHLv8i16, + 6919 => Opcode::SQSHLv8i16_shift, + 6920 => Opcode::SQSHLv8i8, + 6921 => Opcode::SQSHLv8i8_shift, + 6922 => Opcode::SQSHRNB_ZZI_B, + 6923 => Opcode::SQSHRNB_ZZI_H, + 6924 => Opcode::SQSHRNB_ZZI_S, + 6925 => Opcode::SQSHRNT_ZZI_B, + 6926 => Opcode::SQSHRNT_ZZI_H, + 6927 => Opcode::SQSHRNT_ZZI_S, + 6928 => Opcode::SQSHRN_Z2ZI_HtoB, + 6929 => Opcode::SQSHRN_Z2ZI_StoH, + 6930 => Opcode::SQSHRNb, + 6931 => Opcode::SQSHRNh, + 6932 => Opcode::SQSHRNs, + 6933 => Opcode::SQSHRNv16i8_shift, + 6934 => Opcode::SQSHRNv2i32_shift, + 6935 => Opcode::SQSHRNv4i16_shift, + 6936 => Opcode::SQSHRNv4i32_shift, + 6937 => Opcode::SQSHRNv8i16_shift, + 6938 => Opcode::SQSHRNv8i8_shift, + 6939 => Opcode::SQSHRUNB_ZZI_B, + 6940 => Opcode::SQSHRUNB_ZZI_H, + 6941 => Opcode::SQSHRUNB_ZZI_S, + 6942 => Opcode::SQSHRUNT_ZZI_B, + 6943 => Opcode::SQSHRUNT_ZZI_H, + 6944 => Opcode::SQSHRUNT_ZZI_S, + 6945 => Opcode::SQSHRUN_Z2ZI_HtoB, + 6946 => Opcode::SQSHRUN_Z2ZI_StoH, + 6947 => Opcode::SQSHRUNb, + 6948 => Opcode::SQSHRUNh, + 6949 => Opcode::SQSHRUNs, + 6950 => Opcode::SQSHRUNv16i8_shift, + 6951 => Opcode::SQSHRUNv2i32_shift, + 6952 => Opcode::SQSHRUNv4i16_shift, + 6953 => Opcode::SQSHRUNv4i32_shift, + 6954 => Opcode::SQSHRUNv8i16_shift, + 6955 => Opcode::SQSHRUNv8i8_shift, + 6956 => Opcode::SQSUBR_ZPmZ_B, + 6957 => Opcode::SQSUBR_ZPmZ_D, + 6958 => Opcode::SQSUBR_ZPmZ_H, + 6959 => Opcode::SQSUBR_ZPmZ_S, + 6960 => Opcode::SQSUB_ZI_B, + 6961 => Opcode::SQSUB_ZI_D, + 6962 => Opcode::SQSUB_ZI_H, + 6963 => Opcode::SQSUB_ZI_S, + 6964 => Opcode::SQSUB_ZPmZ_B, + 6965 => Opcode::SQSUB_ZPmZ_D, + 6966 => Opcode::SQSUB_ZPmZ_H, + 6967 => Opcode::SQSUB_ZPmZ_S, + 6968 => Opcode::SQSUB_ZZZ_B, + 6969 => Opcode::SQSUB_ZZZ_D, + 6970 => Opcode::SQSUB_ZZZ_H, + 6971 => Opcode::SQSUB_ZZZ_S, + 6972 => Opcode::SQSUBv16i8, + 6973 => Opcode::SQSUBv1i16, + 6974 => Opcode::SQSUBv1i32, + 6975 => Opcode::SQSUBv1i64, + 6976 => Opcode::SQSUBv1i8, + 6977 => Opcode::SQSUBv2i32, + 6978 => Opcode::SQSUBv2i64, + 6979 => Opcode::SQSUBv4i16, + 6980 => Opcode::SQSUBv4i32, + 6981 => Opcode::SQSUBv8i16, + 6982 => Opcode::SQSUBv8i8, + 6983 => Opcode::SQXTNB_ZZ_B, + 6984 => Opcode::SQXTNB_ZZ_H, + 6985 => Opcode::SQXTNB_ZZ_S, + 6986 => Opcode::SQXTNT_ZZ_B, + 6987 => Opcode::SQXTNT_ZZ_H, + 6988 => Opcode::SQXTNT_ZZ_S, + 6989 => Opcode::SQXTNv16i8, + 6990 => Opcode::SQXTNv1i16, + 6991 => Opcode::SQXTNv1i32, + 6992 => Opcode::SQXTNv1i8, + 6993 => Opcode::SQXTNv2i32, + 6994 => Opcode::SQXTNv4i16, + 6995 => Opcode::SQXTNv4i32, + 6996 => Opcode::SQXTNv8i16, + 6997 => Opcode::SQXTNv8i8, + 6998 => Opcode::SQXTUNB_ZZ_B, + 6999 => Opcode::SQXTUNB_ZZ_H, + 7000 => Opcode::SQXTUNB_ZZ_S, + 7001 => Opcode::SQXTUNT_ZZ_B, + 7002 => Opcode::SQXTUNT_ZZ_H, + 7003 => Opcode::SQXTUNT_ZZ_S, + 7004 => Opcode::SQXTUNv16i8, + 7005 => Opcode::SQXTUNv1i16, + 7006 => Opcode::SQXTUNv1i32, + 7007 => Opcode::SQXTUNv1i8, + 7008 => Opcode::SQXTUNv2i32, + 7009 => Opcode::SQXTUNv4i16, + 7010 => Opcode::SQXTUNv4i32, + 7011 => Opcode::SQXTUNv8i16, + 7012 => Opcode::SQXTUNv8i8, + 7013 => Opcode::SRHADD_ZPmZ_B, + 7014 => Opcode::SRHADD_ZPmZ_D, + 7015 => Opcode::SRHADD_ZPmZ_H, + 7016 => Opcode::SRHADD_ZPmZ_S, + 7017 => Opcode::SRHADDv16i8, + 7018 => Opcode::SRHADDv2i32, + 7019 => Opcode::SRHADDv4i16, + 7020 => Opcode::SRHADDv4i32, + 7021 => Opcode::SRHADDv8i16, + 7022 => Opcode::SRHADDv8i8, + 7023 => Opcode::SRI_ZZI_B, + 7024 => Opcode::SRI_ZZI_D, + 7025 => Opcode::SRI_ZZI_H, + 7026 => Opcode::SRI_ZZI_S, + 7027 => Opcode::SRId, + 7028 => Opcode::SRIv16i8_shift, + 7029 => Opcode::SRIv2i32_shift, + 7030 => Opcode::SRIv2i64_shift, + 7031 => Opcode::SRIv4i16_shift, + 7032 => Opcode::SRIv4i32_shift, + 7033 => Opcode::SRIv8i16_shift, + 7034 => Opcode::SRIv8i8_shift, + 7035 => Opcode::SRSHLR_ZPmZ_B, + 7036 => Opcode::SRSHLR_ZPmZ_D, + 7037 => Opcode::SRSHLR_ZPmZ_H, + 7038 => Opcode::SRSHLR_ZPmZ_S, + 7039 => Opcode::SRSHL_VG2_2Z2Z_B, + 7040 => Opcode::SRSHL_VG2_2Z2Z_D, + 7041 => Opcode::SRSHL_VG2_2Z2Z_H, + 7042 => Opcode::SRSHL_VG2_2Z2Z_S, + 7043 => Opcode::SRSHL_VG2_2ZZ_B, + 7044 => Opcode::SRSHL_VG2_2ZZ_D, + 7045 => Opcode::SRSHL_VG2_2ZZ_H, + 7046 => Opcode::SRSHL_VG2_2ZZ_S, + 7047 => Opcode::SRSHL_VG4_4Z4Z_B, + 7048 => Opcode::SRSHL_VG4_4Z4Z_D, + 7049 => Opcode::SRSHL_VG4_4Z4Z_H, + 7050 => Opcode::SRSHL_VG4_4Z4Z_S, + 7051 => Opcode::SRSHL_VG4_4ZZ_B, + 7052 => Opcode::SRSHL_VG4_4ZZ_D, + 7053 => Opcode::SRSHL_VG4_4ZZ_H, + 7054 => Opcode::SRSHL_VG4_4ZZ_S, + 7055 => Opcode::SRSHL_ZPmZ_B, + 7056 => Opcode::SRSHL_ZPmZ_D, + 7057 => Opcode::SRSHL_ZPmZ_H, + 7058 => Opcode::SRSHL_ZPmZ_S, + 7059 => Opcode::SRSHLv16i8, + 7060 => Opcode::SRSHLv1i64, + 7061 => Opcode::SRSHLv2i32, + 7062 => Opcode::SRSHLv2i64, + 7063 => Opcode::SRSHLv4i16, + 7064 => Opcode::SRSHLv4i32, + 7065 => Opcode::SRSHLv8i16, + 7066 => Opcode::SRSHLv8i8, + 7067 => Opcode::SRSHR_ZPmI_B, + 7068 => Opcode::SRSHR_ZPmI_D, + 7069 => Opcode::SRSHR_ZPmI_H, + 7070 => Opcode::SRSHR_ZPmI_S, + 7071 => Opcode::SRSHRd, + 7072 => Opcode::SRSHRv16i8_shift, + 7073 => Opcode::SRSHRv2i32_shift, + 7074 => Opcode::SRSHRv2i64_shift, + 7075 => Opcode::SRSHRv4i16_shift, + 7076 => Opcode::SRSHRv4i32_shift, + 7077 => Opcode::SRSHRv8i16_shift, + 7078 => Opcode::SRSHRv8i8_shift, + 7079 => Opcode::SRSRA_ZZI_B, + 7080 => Opcode::SRSRA_ZZI_D, + 7081 => Opcode::SRSRA_ZZI_H, + 7082 => Opcode::SRSRA_ZZI_S, + 7083 => Opcode::SRSRAd, + 7084 => Opcode::SRSRAv16i8_shift, + 7085 => Opcode::SRSRAv2i32_shift, + 7086 => Opcode::SRSRAv2i64_shift, + 7087 => Opcode::SRSRAv4i16_shift, + 7088 => Opcode::SRSRAv4i32_shift, + 7089 => Opcode::SRSRAv8i16_shift, + 7090 => Opcode::SRSRAv8i8_shift, + 7091 => Opcode::SSHLLB_ZZI_D, + 7092 => Opcode::SSHLLB_ZZI_H, + 7093 => Opcode::SSHLLB_ZZI_S, + 7094 => Opcode::SSHLLT_ZZI_D, + 7095 => Opcode::SSHLLT_ZZI_H, + 7096 => Opcode::SSHLLT_ZZI_S, + 7097 => Opcode::SSHLLv16i8_shift, + 7098 => Opcode::SSHLLv2i32_shift, + 7099 => Opcode::SSHLLv4i16_shift, + 7100 => Opcode::SSHLLv4i32_shift, + 7101 => Opcode::SSHLLv8i16_shift, + 7102 => Opcode::SSHLLv8i8_shift, + 7103 => Opcode::SSHLv16i8, + 7104 => Opcode::SSHLv1i64, + 7105 => Opcode::SSHLv2i32, + 7106 => Opcode::SSHLv2i64, + 7107 => Opcode::SSHLv4i16, + 7108 => Opcode::SSHLv4i32, + 7109 => Opcode::SSHLv8i16, + 7110 => Opcode::SSHLv8i8, + 7111 => Opcode::SSHRd, + 7112 => Opcode::SSHRv16i8_shift, + 7113 => Opcode::SSHRv2i32_shift, + 7114 => Opcode::SSHRv2i64_shift, + 7115 => Opcode::SSHRv4i16_shift, + 7116 => Opcode::SSHRv4i32_shift, + 7117 => Opcode::SSHRv8i16_shift, + 7118 => Opcode::SSHRv8i8_shift, + 7119 => Opcode::SSRA_ZZI_B, + 7120 => Opcode::SSRA_ZZI_D, + 7121 => Opcode::SSRA_ZZI_H, + 7122 => Opcode::SSRA_ZZI_S, + 7123 => Opcode::SSRAd, + 7124 => Opcode::SSRAv16i8_shift, + 7125 => Opcode::SSRAv2i32_shift, + 7126 => Opcode::SSRAv2i64_shift, + 7127 => Opcode::SSRAv4i16_shift, + 7128 => Opcode::SSRAv4i32_shift, + 7129 => Opcode::SSRAv8i16_shift, + 7130 => Opcode::SSRAv8i8_shift, + 7131 => Opcode::SST1B_D, + 7132 => Opcode::SST1B_D_IMM, + 7133 => Opcode::SST1B_D_SXTW, + 7134 => Opcode::SST1B_D_UXTW, + 7135 => Opcode::SST1B_S_IMM, + 7136 => Opcode::SST1B_S_SXTW, + 7137 => Opcode::SST1B_S_UXTW, + 7138 => Opcode::SST1D, + 7139 => Opcode::SST1D_IMM, + 7140 => Opcode::SST1D_SCALED, + 7141 => Opcode::SST1D_SXTW, + 7142 => Opcode::SST1D_SXTW_SCALED, + 7143 => Opcode::SST1D_UXTW, + 7144 => Opcode::SST1D_UXTW_SCALED, + 7145 => Opcode::SST1H_D, + 7146 => Opcode::SST1H_D_IMM, + 7147 => Opcode::SST1H_D_SCALED, + 7148 => Opcode::SST1H_D_SXTW, + 7149 => Opcode::SST1H_D_SXTW_SCALED, + 7150 => Opcode::SST1H_D_UXTW, + 7151 => Opcode::SST1H_D_UXTW_SCALED, + 7152 => Opcode::SST1H_S_IMM, + 7153 => Opcode::SST1H_S_SXTW, + 7154 => Opcode::SST1H_S_SXTW_SCALED, + 7155 => Opcode::SST1H_S_UXTW, + 7156 => Opcode::SST1H_S_UXTW_SCALED, + 7157 => Opcode::SST1Q, + 7158 => Opcode::SST1W_D, + 7159 => Opcode::SST1W_D_IMM, + 7160 => Opcode::SST1W_D_SCALED, + 7161 => Opcode::SST1W_D_SXTW, + 7162 => Opcode::SST1W_D_SXTW_SCALED, + 7163 => Opcode::SST1W_D_UXTW, + 7164 => Opcode::SST1W_D_UXTW_SCALED, + 7165 => Opcode::SST1W_IMM, + 7166 => Opcode::SST1W_SXTW, + 7167 => Opcode::SST1W_SXTW_SCALED, + 7168 => Opcode::SST1W_UXTW, + 7169 => Opcode::SST1W_UXTW_SCALED, + 7170 => Opcode::SSUBLBT_ZZZ_D, + 7171 => Opcode::SSUBLBT_ZZZ_H, + 7172 => Opcode::SSUBLBT_ZZZ_S, + 7173 => Opcode::SSUBLB_ZZZ_D, + 7174 => Opcode::SSUBLB_ZZZ_H, + 7175 => Opcode::SSUBLB_ZZZ_S, + 7176 => Opcode::SSUBLTB_ZZZ_D, + 7177 => Opcode::SSUBLTB_ZZZ_H, + 7178 => Opcode::SSUBLTB_ZZZ_S, + 7179 => Opcode::SSUBLT_ZZZ_D, + 7180 => Opcode::SSUBLT_ZZZ_H, + 7181 => Opcode::SSUBLT_ZZZ_S, + 7182 => Opcode::SSUBLv16i8_v8i16, + 7183 => Opcode::SSUBLv2i32_v2i64, + 7184 => Opcode::SSUBLv4i16_v4i32, + 7185 => Opcode::SSUBLv4i32_v2i64, + 7186 => Opcode::SSUBLv8i16_v4i32, + 7187 => Opcode::SSUBLv8i8_v8i16, + 7188 => Opcode::SSUBWB_ZZZ_D, + 7189 => Opcode::SSUBWB_ZZZ_H, + 7190 => Opcode::SSUBWB_ZZZ_S, + 7191 => Opcode::SSUBWT_ZZZ_D, + 7192 => Opcode::SSUBWT_ZZZ_H, + 7193 => Opcode::SSUBWT_ZZZ_S, + 7194 => Opcode::SSUBWv16i8_v8i16, + 7195 => Opcode::SSUBWv2i32_v2i64, + 7196 => Opcode::SSUBWv4i16_v4i32, + 7197 => Opcode::SSUBWv4i32_v2i64, + 7198 => Opcode::SSUBWv8i16_v4i32, + 7199 => Opcode::SSUBWv8i8_v8i16, + 7200 => Opcode::ST1B, + 7201 => Opcode::ST1B_2Z, + 7202 => Opcode::ST1B_2Z_IMM, + 7203 => Opcode::ST1B_2Z_STRIDED, + 7204 => Opcode::ST1B_2Z_STRIDED_IMM, + 7205 => Opcode::ST1B_4Z, + 7206 => Opcode::ST1B_4Z_IMM, + 7207 => Opcode::ST1B_4Z_STRIDED, + 7208 => Opcode::ST1B_4Z_STRIDED_IMM, + 7209 => Opcode::ST1B_D, + 7210 => Opcode::ST1B_D_IMM, + 7211 => Opcode::ST1B_H, + 7212 => Opcode::ST1B_H_IMM, + 7213 => Opcode::ST1B_IMM, + 7214 => Opcode::ST1B_S, + 7215 => Opcode::ST1B_S_IMM, + 7216 => Opcode::ST1D, + 7217 => Opcode::ST1D_2Z, + 7218 => Opcode::ST1D_2Z_IMM, + 7219 => Opcode::ST1D_2Z_STRIDED, + 7220 => Opcode::ST1D_2Z_STRIDED_IMM, + 7221 => Opcode::ST1D_4Z, + 7222 => Opcode::ST1D_4Z_IMM, + 7223 => Opcode::ST1D_4Z_STRIDED, + 7224 => Opcode::ST1D_4Z_STRIDED_IMM, + 7225 => Opcode::ST1D_IMM, + 7226 => Opcode::ST1D_Q, + 7227 => Opcode::ST1D_Q_IMM, + 7228 => Opcode::ST1Fourv16b, + 7229 => Opcode::ST1Fourv16b_POST, + 7230 => Opcode::ST1Fourv1d, + 7231 => Opcode::ST1Fourv1d_POST, + 7232 => Opcode::ST1Fourv2d, + 7233 => Opcode::ST1Fourv2d_POST, + 7234 => Opcode::ST1Fourv2s, + 7235 => Opcode::ST1Fourv2s_POST, + 7236 => Opcode::ST1Fourv4h, + 7237 => Opcode::ST1Fourv4h_POST, + 7238 => Opcode::ST1Fourv4s, + 7239 => Opcode::ST1Fourv4s_POST, + 7240 => Opcode::ST1Fourv8b, + 7241 => Opcode::ST1Fourv8b_POST, + 7242 => Opcode::ST1Fourv8h, + 7243 => Opcode::ST1Fourv8h_POST, + 7244 => Opcode::ST1H, + 7245 => Opcode::ST1H_2Z, + 7246 => Opcode::ST1H_2Z_IMM, + 7247 => Opcode::ST1H_2Z_STRIDED, + 7248 => Opcode::ST1H_2Z_STRIDED_IMM, + 7249 => Opcode::ST1H_4Z, + 7250 => Opcode::ST1H_4Z_IMM, + 7251 => Opcode::ST1H_4Z_STRIDED, + 7252 => Opcode::ST1H_4Z_STRIDED_IMM, + 7253 => Opcode::ST1H_D, + 7254 => Opcode::ST1H_D_IMM, + 7255 => Opcode::ST1H_IMM, + 7256 => Opcode::ST1H_S, + 7257 => Opcode::ST1H_S_IMM, + 7258 => Opcode::ST1Onev16b, + 7259 => Opcode::ST1Onev16b_POST, + 7260 => Opcode::ST1Onev1d, + 7261 => Opcode::ST1Onev1d_POST, + 7262 => Opcode::ST1Onev2d, + 7263 => Opcode::ST1Onev2d_POST, + 7264 => Opcode::ST1Onev2s, + 7265 => Opcode::ST1Onev2s_POST, + 7266 => Opcode::ST1Onev4h, + 7267 => Opcode::ST1Onev4h_POST, + 7268 => Opcode::ST1Onev4s, + 7269 => Opcode::ST1Onev4s_POST, + 7270 => Opcode::ST1Onev8b, + 7271 => Opcode::ST1Onev8b_POST, + 7272 => Opcode::ST1Onev8h, + 7273 => Opcode::ST1Onev8h_POST, + 7274 => Opcode::ST1Threev16b, + 7275 => Opcode::ST1Threev16b_POST, + 7276 => Opcode::ST1Threev1d, + 7277 => Opcode::ST1Threev1d_POST, + 7278 => Opcode::ST1Threev2d, + 7279 => Opcode::ST1Threev2d_POST, + 7280 => Opcode::ST1Threev2s, + 7281 => Opcode::ST1Threev2s_POST, + 7282 => Opcode::ST1Threev4h, + 7283 => Opcode::ST1Threev4h_POST, + 7284 => Opcode::ST1Threev4s, + 7285 => Opcode::ST1Threev4s_POST, + 7286 => Opcode::ST1Threev8b, + 7287 => Opcode::ST1Threev8b_POST, + 7288 => Opcode::ST1Threev8h, + 7289 => Opcode::ST1Threev8h_POST, + 7290 => Opcode::ST1Twov16b, + 7291 => Opcode::ST1Twov16b_POST, + 7292 => Opcode::ST1Twov1d, + 7293 => Opcode::ST1Twov1d_POST, + 7294 => Opcode::ST1Twov2d, + 7295 => Opcode::ST1Twov2d_POST, + 7296 => Opcode::ST1Twov2s, + 7297 => Opcode::ST1Twov2s_POST, + 7298 => Opcode::ST1Twov4h, + 7299 => Opcode::ST1Twov4h_POST, + 7300 => Opcode::ST1Twov4s, + 7301 => Opcode::ST1Twov4s_POST, + 7302 => Opcode::ST1Twov8b, + 7303 => Opcode::ST1Twov8b_POST, + 7304 => Opcode::ST1Twov8h, + 7305 => Opcode::ST1Twov8h_POST, + 7306 => Opcode::ST1W, + 7307 => Opcode::ST1W_2Z, + 7308 => Opcode::ST1W_2Z_IMM, + 7309 => Opcode::ST1W_2Z_STRIDED, + 7310 => Opcode::ST1W_2Z_STRIDED_IMM, + 7311 => Opcode::ST1W_4Z, + 7312 => Opcode::ST1W_4Z_IMM, + 7313 => Opcode::ST1W_4Z_STRIDED, + 7314 => Opcode::ST1W_4Z_STRIDED_IMM, + 7315 => Opcode::ST1W_D, + 7316 => Opcode::ST1W_D_IMM, + 7317 => Opcode::ST1W_IMM, + 7318 => Opcode::ST1W_Q, + 7319 => Opcode::ST1W_Q_IMM, + 7320 => Opcode::ST1_MXIPXX_H_B, + 7321 => Opcode::ST1_MXIPXX_H_D, + 7322 => Opcode::ST1_MXIPXX_H_H, + 7323 => Opcode::ST1_MXIPXX_H_Q, + 7324 => Opcode::ST1_MXIPXX_H_S, + 7325 => Opcode::ST1_MXIPXX_V_B, + 7326 => Opcode::ST1_MXIPXX_V_D, + 7327 => Opcode::ST1_MXIPXX_V_H, + 7328 => Opcode::ST1_MXIPXX_V_Q, + 7329 => Opcode::ST1_MXIPXX_V_S, + 7330 => Opcode::ST1i16, + 7331 => Opcode::ST1i16_POST, + 7332 => Opcode::ST1i32, + 7333 => Opcode::ST1i32_POST, + 7334 => Opcode::ST1i64, + 7335 => Opcode::ST1i64_POST, + 7336 => Opcode::ST1i8, + 7337 => Opcode::ST1i8_POST, + 7338 => Opcode::ST2B, + 7339 => Opcode::ST2B_IMM, + 7340 => Opcode::ST2D, + 7341 => Opcode::ST2D_IMM, + 7342 => Opcode::ST2GPostIndex, + 7343 => Opcode::ST2GPreIndex, + 7344 => Opcode::ST2Gi, + 7345 => Opcode::ST2H, + 7346 => Opcode::ST2H_IMM, + 7347 => Opcode::ST2Q, + 7348 => Opcode::ST2Q_IMM, + 7349 => Opcode::ST2Twov16b, + 7350 => Opcode::ST2Twov16b_POST, + 7351 => Opcode::ST2Twov2d, + 7352 => Opcode::ST2Twov2d_POST, + 7353 => Opcode::ST2Twov2s, + 7354 => Opcode::ST2Twov2s_POST, + 7355 => Opcode::ST2Twov4h, + 7356 => Opcode::ST2Twov4h_POST, + 7357 => Opcode::ST2Twov4s, + 7358 => Opcode::ST2Twov4s_POST, + 7359 => Opcode::ST2Twov8b, + 7360 => Opcode::ST2Twov8b_POST, + 7361 => Opcode::ST2Twov8h, + 7362 => Opcode::ST2Twov8h_POST, + 7363 => Opcode::ST2W, + 7364 => Opcode::ST2W_IMM, + 7365 => Opcode::ST2i16, + 7366 => Opcode::ST2i16_POST, + 7367 => Opcode::ST2i32, + 7368 => Opcode::ST2i32_POST, + 7369 => Opcode::ST2i64, + 7370 => Opcode::ST2i64_POST, + 7371 => Opcode::ST2i8, + 7372 => Opcode::ST2i8_POST, + 7373 => Opcode::ST3B, + 7374 => Opcode::ST3B_IMM, + 7375 => Opcode::ST3D, + 7376 => Opcode::ST3D_IMM, + 7377 => Opcode::ST3H, + 7378 => Opcode::ST3H_IMM, + 7379 => Opcode::ST3Q, + 7380 => Opcode::ST3Q_IMM, + 7381 => Opcode::ST3Threev16b, + 7382 => Opcode::ST3Threev16b_POST, + 7383 => Opcode::ST3Threev2d, + 7384 => Opcode::ST3Threev2d_POST, + 7385 => Opcode::ST3Threev2s, + 7386 => Opcode::ST3Threev2s_POST, + 7387 => Opcode::ST3Threev4h, + 7388 => Opcode::ST3Threev4h_POST, + 7389 => Opcode::ST3Threev4s, + 7390 => Opcode::ST3Threev4s_POST, + 7391 => Opcode::ST3Threev8b, + 7392 => Opcode::ST3Threev8b_POST, + 7393 => Opcode::ST3Threev8h, + 7394 => Opcode::ST3Threev8h_POST, + 7395 => Opcode::ST3W, + 7396 => Opcode::ST3W_IMM, + 7397 => Opcode::ST3i16, + 7398 => Opcode::ST3i16_POST, + 7399 => Opcode::ST3i32, + 7400 => Opcode::ST3i32_POST, + 7401 => Opcode::ST3i64, + 7402 => Opcode::ST3i64_POST, + 7403 => Opcode::ST3i8, + 7404 => Opcode::ST3i8_POST, + 7405 => Opcode::ST4B, + 7406 => Opcode::ST4B_IMM, + 7407 => Opcode::ST4D, + 7408 => Opcode::ST4D_IMM, + 7409 => Opcode::ST4Fourv16b, + 7410 => Opcode::ST4Fourv16b_POST, + 7411 => Opcode::ST4Fourv2d, + 7412 => Opcode::ST4Fourv2d_POST, + 7413 => Opcode::ST4Fourv2s, + 7414 => Opcode::ST4Fourv2s_POST, + 7415 => Opcode::ST4Fourv4h, + 7416 => Opcode::ST4Fourv4h_POST, + 7417 => Opcode::ST4Fourv4s, + 7418 => Opcode::ST4Fourv4s_POST, + 7419 => Opcode::ST4Fourv8b, + 7420 => Opcode::ST4Fourv8b_POST, + 7421 => Opcode::ST4Fourv8h, + 7422 => Opcode::ST4Fourv8h_POST, + 7423 => Opcode::ST4H, + 7424 => Opcode::ST4H_IMM, + 7425 => Opcode::ST4Q, + 7426 => Opcode::ST4Q_IMM, + 7427 => Opcode::ST4W, + 7428 => Opcode::ST4W_IMM, + 7429 => Opcode::ST4i16, + 7430 => Opcode::ST4i16_POST, + 7431 => Opcode::ST4i32, + 7432 => Opcode::ST4i32_POST, + 7433 => Opcode::ST4i64, + 7434 => Opcode::ST4i64_POST, + 7435 => Opcode::ST4i8, + 7436 => Opcode::ST4i8_POST, + 7437 => Opcode::ST64B, + 7438 => Opcode::ST64BV, + 7439 => Opcode::ST64BV0, + 7440 => Opcode::STBFADD, + 7441 => Opcode::STBFADDL, + 7442 => Opcode::STBFMAX, + 7443 => Opcode::STBFMAXL, + 7444 => Opcode::STBFMAXNM, + 7445 => Opcode::STBFMAXNML, + 7446 => Opcode::STBFMIN, + 7447 => Opcode::STBFMINL, + 7448 => Opcode::STBFMINNM, + 7449 => Opcode::STBFMINNML, + 7450 => Opcode::STCPH, + 7451 => Opcode::STFADDD, + 7452 => Opcode::STFADDH, + 7453 => Opcode::STFADDLD, + 7454 => Opcode::STFADDLH, + 7455 => Opcode::STFADDLS, + 7456 => Opcode::STFADDS, + 7457 => Opcode::STFMAXD, + 7458 => Opcode::STFMAXH, + 7459 => Opcode::STFMAXLD, + 7460 => Opcode::STFMAXLH, + 7461 => Opcode::STFMAXLS, + 7462 => Opcode::STFMAXNMD, + 7463 => Opcode::STFMAXNMH, + 7464 => Opcode::STFMAXNMLD, + 7465 => Opcode::STFMAXNMLH, + 7466 => Opcode::STFMAXNMLS, + 7467 => Opcode::STFMAXNMS, + 7468 => Opcode::STFMAXS, + 7469 => Opcode::STFMIND, + 7470 => Opcode::STFMINH, + 7471 => Opcode::STFMINLD, + 7472 => Opcode::STFMINLH, + 7473 => Opcode::STFMINLS, + 7474 => Opcode::STFMINNMD, + 7475 => Opcode::STFMINNMH, + 7476 => Opcode::STFMINNMLD, + 7477 => Opcode::STFMINNMLH, + 7478 => Opcode::STFMINNMLS, + 7479 => Opcode::STFMINNMS, + 7480 => Opcode::STFMINS, + 7481 => Opcode::STGM, + 7482 => Opcode::STGPi, + 7483 => Opcode::STGPostIndex, + 7484 => Opcode::STGPpost, + 7485 => Opcode::STGPpre, + 7486 => Opcode::STGPreIndex, + 7487 => Opcode::STGi, + 7488 => Opcode::STILPW, + 7489 => Opcode::STILPWpre, + 7490 => Opcode::STILPX, + 7491 => Opcode::STILPXpre, + 7492 => Opcode::STL1, + 7493 => Opcode::STLLRB, + 7494 => Opcode::STLLRH, + 7495 => Opcode::STLLRW, + 7496 => Opcode::STLLRX, + 7497 => Opcode::STLPi, + 7498 => Opcode::STLRB, + 7499 => Opcode::STLRH, + 7500 => Opcode::STLRW, + 7501 => Opcode::STLRWpre, + 7502 => Opcode::STLRX, + 7503 => Opcode::STLRXpre, + 7504 => Opcode::STLTXRW, + 7505 => Opcode::STLTXRX, + 7506 => Opcode::STLURBi, + 7507 => Opcode::STLURHi, + 7508 => Opcode::STLURWi, + 7509 => Opcode::STLURXi, + 7510 => Opcode::STLURbi, + 7511 => Opcode::STLURdi, + 7512 => Opcode::STLURhi, + 7513 => Opcode::STLURqi, + 7514 => Opcode::STLURsi, + 7515 => Opcode::STLXPW, + 7516 => Opcode::STLXPX, + 7517 => Opcode::STLXRB, + 7518 => Opcode::STLXRH, + 7519 => Opcode::STLXRW, + 7520 => Opcode::STLXRX, + 7521 => Opcode::STMOPA_M2ZZZI_BtoS, + 7522 => Opcode::STMOPA_M2ZZZI_HtoS, + 7523 => Opcode::STNPDi, + 7524 => Opcode::STNPQi, + 7525 => Opcode::STNPSi, + 7526 => Opcode::STNPWi, + 7527 => Opcode::STNPXi, + 7528 => Opcode::STNT1B_2Z, + 7529 => Opcode::STNT1B_2Z_IMM, + 7530 => Opcode::STNT1B_2Z_STRIDED, + 7531 => Opcode::STNT1B_2Z_STRIDED_IMM, + 7532 => Opcode::STNT1B_4Z, + 7533 => Opcode::STNT1B_4Z_IMM, + 7534 => Opcode::STNT1B_4Z_STRIDED, + 7535 => Opcode::STNT1B_4Z_STRIDED_IMM, + 7536 => Opcode::STNT1B_ZRI, + 7537 => Opcode::STNT1B_ZRR, + 7538 => Opcode::STNT1B_ZZR_D, + 7539 => Opcode::STNT1B_ZZR_S, + 7540 => Opcode::STNT1D_2Z, + 7541 => Opcode::STNT1D_2Z_IMM, + 7542 => Opcode::STNT1D_2Z_STRIDED, + 7543 => Opcode::STNT1D_2Z_STRIDED_IMM, + 7544 => Opcode::STNT1D_4Z, + 7545 => Opcode::STNT1D_4Z_IMM, + 7546 => Opcode::STNT1D_4Z_STRIDED, + 7547 => Opcode::STNT1D_4Z_STRIDED_IMM, + 7548 => Opcode::STNT1D_ZRI, + 7549 => Opcode::STNT1D_ZRR, + 7550 => Opcode::STNT1D_ZZR_D, + 7551 => Opcode::STNT1H_2Z, + 7552 => Opcode::STNT1H_2Z_IMM, + 7553 => Opcode::STNT1H_2Z_STRIDED, + 7554 => Opcode::STNT1H_2Z_STRIDED_IMM, + 7555 => Opcode::STNT1H_4Z, + 7556 => Opcode::STNT1H_4Z_IMM, + 7557 => Opcode::STNT1H_4Z_STRIDED, + 7558 => Opcode::STNT1H_4Z_STRIDED_IMM, + 7559 => Opcode::STNT1H_ZRI, + 7560 => Opcode::STNT1H_ZRR, + 7561 => Opcode::STNT1H_ZZR_D, + 7562 => Opcode::STNT1H_ZZR_S, + 7563 => Opcode::STNT1W_2Z, + 7564 => Opcode::STNT1W_2Z_IMM, + 7565 => Opcode::STNT1W_2Z_STRIDED, + 7566 => Opcode::STNT1W_2Z_STRIDED_IMM, + 7567 => Opcode::STNT1W_4Z, + 7568 => Opcode::STNT1W_4Z_IMM, + 7569 => Opcode::STNT1W_4Z_STRIDED, + 7570 => Opcode::STNT1W_4Z_STRIDED_IMM, + 7571 => Opcode::STNT1W_ZRI, + 7572 => Opcode::STNT1W_ZRR, + 7573 => Opcode::STNT1W_ZZR_D, + 7574 => Opcode::STNT1W_ZZR_S, + 7575 => Opcode::STPDi, + 7576 => Opcode::STPDpost, + 7577 => Opcode::STPDpre, + 7578 => Opcode::STPQi, + 7579 => Opcode::STPQpost, + 7580 => Opcode::STPQpre, + 7581 => Opcode::STPSi, + 7582 => Opcode::STPSpost, + 7583 => Opcode::STPSpre, + 7584 => Opcode::STPWi, + 7585 => Opcode::STPWpost, + 7586 => Opcode::STPWpre, + 7587 => Opcode::STPXi, + 7588 => Opcode::STPXpost, + 7589 => Opcode::STPXpre, + 7590 => Opcode::STRBBpost, + 7591 => Opcode::STRBBpre, + 7592 => Opcode::STRBBroW, + 7593 => Opcode::STRBBroX, + 7594 => Opcode::STRBBui, + 7595 => Opcode::STRBpost, + 7596 => Opcode::STRBpre, + 7597 => Opcode::STRBroW, + 7598 => Opcode::STRBroX, + 7599 => Opcode::STRBui, + 7600 => Opcode::STRDpost, + 7601 => Opcode::STRDpre, + 7602 => Opcode::STRDroW, + 7603 => Opcode::STRDroX, + 7604 => Opcode::STRDui, + 7605 => Opcode::STRHHpost, + 7606 => Opcode::STRHHpre, + 7607 => Opcode::STRHHroW, + 7608 => Opcode::STRHHroX, + 7609 => Opcode::STRHHui, + 7610 => Opcode::STRHpost, + 7611 => Opcode::STRHpre, + 7612 => Opcode::STRHroW, + 7613 => Opcode::STRHroX, + 7614 => Opcode::STRHui, + 7615 => Opcode::STRQpost, + 7616 => Opcode::STRQpre, + 7617 => Opcode::STRQroW, + 7618 => Opcode::STRQroX, + 7619 => Opcode::STRQui, + 7620 => Opcode::STRSpost, + 7621 => Opcode::STRSpre, + 7622 => Opcode::STRSroW, + 7623 => Opcode::STRSroX, + 7624 => Opcode::STRSui, + 7625 => Opcode::STRWpost, + 7626 => Opcode::STRWpre, + 7627 => Opcode::STRWroW, + 7628 => Opcode::STRWroX, + 7629 => Opcode::STRWui, + 7630 => Opcode::STRXpost, + 7631 => Opcode::STRXpre, + 7632 => Opcode::STRXroW, + 7633 => Opcode::STRXroX, + 7634 => Opcode::STRXui, + 7635 => Opcode::STR_PXI, + 7636 => Opcode::STR_TX, + 7637 => Opcode::STR_ZA, + 7638 => Opcode::STR_ZXI, + 7639 => Opcode::STSHH, + 7640 => Opcode::STTNPQi, + 7641 => Opcode::STTNPXi, + 7642 => Opcode::STTPQi, + 7643 => Opcode::STTPQpost, + 7644 => Opcode::STTPQpre, + 7645 => Opcode::STTPi, + 7646 => Opcode::STTPpost, + 7647 => Opcode::STTPpre, + 7648 => Opcode::STTRBi, + 7649 => Opcode::STTRHi, + 7650 => Opcode::STTRWi, + 7651 => Opcode::STTRXi, + 7652 => Opcode::STTXRWr, + 7653 => Opcode::STTXRXr, + 7654 => Opcode::STURBBi, + 7655 => Opcode::STURBi, + 7656 => Opcode::STURDi, + 7657 => Opcode::STURHHi, + 7658 => Opcode::STURHi, + 7659 => Opcode::STURQi, + 7660 => Opcode::STURSi, + 7661 => Opcode::STURWi, + 7662 => Opcode::STURXi, + 7663 => Opcode::STXPW, + 7664 => Opcode::STXPX, + 7665 => Opcode::STXRB, + 7666 => Opcode::STXRH, + 7667 => Opcode::STXRW, + 7668 => Opcode::STXRX, + 7669 => Opcode::STZ2GPostIndex, + 7670 => Opcode::STZ2GPreIndex, + 7671 => Opcode::STZ2Gi, + 7672 => Opcode::STZGM, + 7673 => Opcode::STZGPostIndex, + 7674 => Opcode::STZGPreIndex, + 7675 => Opcode::STZGi, + 7676 => Opcode::SUBG, + 7677 => Opcode::SUBHNB_ZZZ_B, + 7678 => Opcode::SUBHNB_ZZZ_H, + 7679 => Opcode::SUBHNB_ZZZ_S, + 7680 => Opcode::SUBHNT_ZZZ_B, + 7681 => Opcode::SUBHNT_ZZZ_H, + 7682 => Opcode::SUBHNT_ZZZ_S, + 7683 => Opcode::SUBHNv2i64_v2i32, + 7684 => Opcode::SUBHNv2i64_v4i32, + 7685 => Opcode::SUBHNv4i32_v4i16, + 7686 => Opcode::SUBHNv4i32_v8i16, + 7687 => Opcode::SUBHNv8i16_v16i8, + 7688 => Opcode::SUBHNv8i16_v8i8, + 7689 => Opcode::SUBP, + 7690 => Opcode::SUBPS, + 7691 => Opcode::SUBPT_shift, + 7692 => Opcode::SUBP_ZPmZZ_B, + 7693 => Opcode::SUBP_ZPmZZ_D, + 7694 => Opcode::SUBP_ZPmZZ_H, + 7695 => Opcode::SUBP_ZPmZZ_S, + 7696 => Opcode::SUBR_ZI_B, + 7697 => Opcode::SUBR_ZI_D, + 7698 => Opcode::SUBR_ZI_H, + 7699 => Opcode::SUBR_ZI_S, + 7700 => Opcode::SUBR_ZPmZ_B, + 7701 => Opcode::SUBR_ZPmZ_D, + 7702 => Opcode::SUBR_ZPmZ_H, + 7703 => Opcode::SUBR_ZPmZ_S, + 7704 => Opcode::SUBSWri, + 7705 => Opcode::SUBSWrs, + 7706 => Opcode::SUBSWrx, + 7707 => Opcode::SUBSXri, + 7708 => Opcode::SUBSXrs, + 7709 => Opcode::SUBSXrx, + 7710 => Opcode::SUBSXrx64, + 7711 => Opcode::SUBWri, + 7712 => Opcode::SUBWrs, + 7713 => Opcode::SUBWrx, + 7714 => Opcode::SUBXri, + 7715 => Opcode::SUBXrs, + 7716 => Opcode::SUBXrx, + 7717 => Opcode::SUBXrx64, + 7718 => Opcode::SUB_VG2_M2Z2Z_D, + 7719 => Opcode::SUB_VG2_M2Z2Z_S, + 7720 => Opcode::SUB_VG2_M2ZZ_D, + 7721 => Opcode::SUB_VG2_M2ZZ_S, + 7722 => Opcode::SUB_VG2_M2Z_D, + 7723 => Opcode::SUB_VG2_M2Z_S, + 7724 => Opcode::SUB_VG4_M4Z4Z_D, + 7725 => Opcode::SUB_VG4_M4Z4Z_S, + 7726 => Opcode::SUB_VG4_M4ZZ_D, + 7727 => Opcode::SUB_VG4_M4ZZ_S, + 7728 => Opcode::SUB_VG4_M4Z_D, + 7729 => Opcode::SUB_VG4_M4Z_S, + 7730 => Opcode::SUB_ZI_B, + 7731 => Opcode::SUB_ZI_D, + 7732 => Opcode::SUB_ZI_H, + 7733 => Opcode::SUB_ZI_S, + 7734 => Opcode::SUB_ZPmZ_B, + 7735 => Opcode::SUB_ZPmZ_CPA, + 7736 => Opcode::SUB_ZPmZ_D, + 7737 => Opcode::SUB_ZPmZ_H, + 7738 => Opcode::SUB_ZPmZ_S, + 7739 => Opcode::SUB_ZZZ_B, + 7740 => Opcode::SUB_ZZZ_CPA, + 7741 => Opcode::SUB_ZZZ_D, + 7742 => Opcode::SUB_ZZZ_H, + 7743 => Opcode::SUB_ZZZ_S, + 7744 => Opcode::SUBv16i8, + 7745 => Opcode::SUBv1i64, + 7746 => Opcode::SUBv2i32, + 7747 => Opcode::SUBv2i64, + 7748 => Opcode::SUBv4i16, + 7749 => Opcode::SUBv4i32, + 7750 => Opcode::SUBv8i16, + 7751 => Opcode::SUBv8i8, + 7752 => Opcode::SUDOT_VG2_M2ZZI_BToS, + 7753 => Opcode::SUDOT_VG2_M2ZZ_BToS, + 7754 => Opcode::SUDOT_VG4_M4ZZI_BToS, + 7755 => Opcode::SUDOT_VG4_M4ZZ_BToS, + 7756 => Opcode::SUDOT_ZZZI, + 7757 => Opcode::SUDOTlanev16i8, + 7758 => Opcode::SUDOTlanev8i8, + 7759 => Opcode::SUMLALL_MZZI_BtoS, + 7760 => Opcode::SUMLALL_VG2_M2ZZI_BtoS, + 7761 => Opcode::SUMLALL_VG2_M2ZZ_BtoS, + 7762 => Opcode::SUMLALL_VG4_M4ZZI_BtoS, + 7763 => Opcode::SUMLALL_VG4_M4ZZ_BtoS, + 7764 => Opcode::SUMOP4A_M2Z2Z_BToS, + 7765 => Opcode::SUMOP4A_M2Z2Z_HtoD, + 7766 => Opcode::SUMOP4A_M2ZZ_BToS, + 7767 => Opcode::SUMOP4A_M2ZZ_HtoD, + 7768 => Opcode::SUMOP4A_MZ2Z_BToS, + 7769 => Opcode::SUMOP4A_MZ2Z_HtoD, + 7770 => Opcode::SUMOP4A_MZZ_BToS, + 7771 => Opcode::SUMOP4A_MZZ_HtoD, + 7772 => Opcode::SUMOP4S_M2Z2Z_BToS, + 7773 => Opcode::SUMOP4S_M2Z2Z_HtoD, + 7774 => Opcode::SUMOP4S_M2ZZ_BToS, + 7775 => Opcode::SUMOP4S_M2ZZ_HtoD, + 7776 => Opcode::SUMOP4S_MZ2Z_BToS, + 7777 => Opcode::SUMOP4S_MZ2Z_HtoD, + 7778 => Opcode::SUMOP4S_MZZ_BToS, + 7779 => Opcode::SUMOP4S_MZZ_HtoD, + 7780 => Opcode::SUMOPA_MPPZZ_D, + 7781 => Opcode::SUMOPA_MPPZZ_S, + 7782 => Opcode::SUMOPS_MPPZZ_D, + 7783 => Opcode::SUMOPS_MPPZZ_S, + 7784 => Opcode::SUNPKHI_ZZ_D, + 7785 => Opcode::SUNPKHI_ZZ_H, + 7786 => Opcode::SUNPKHI_ZZ_S, + 7787 => Opcode::SUNPKLO_ZZ_D, + 7788 => Opcode::SUNPKLO_ZZ_H, + 7789 => Opcode::SUNPKLO_ZZ_S, + 7790 => Opcode::SUNPK_VG2_2ZZ_D, + 7791 => Opcode::SUNPK_VG2_2ZZ_H, + 7792 => Opcode::SUNPK_VG2_2ZZ_S, + 7793 => Opcode::SUNPK_VG4_4Z2Z_D, + 7794 => Opcode::SUNPK_VG4_4Z2Z_H, + 7795 => Opcode::SUNPK_VG4_4Z2Z_S, + 7796 => Opcode::SUQADD_ZPmZ_B, + 7797 => Opcode::SUQADD_ZPmZ_D, + 7798 => Opcode::SUQADD_ZPmZ_H, + 7799 => Opcode::SUQADD_ZPmZ_S, + 7800 => Opcode::SUQADDv16i8, + 7801 => Opcode::SUQADDv1i16, + 7802 => Opcode::SUQADDv1i32, + 7803 => Opcode::SUQADDv1i64, + 7804 => Opcode::SUQADDv1i8, + 7805 => Opcode::SUQADDv2i32, + 7806 => Opcode::SUQADDv2i64, + 7807 => Opcode::SUQADDv4i16, + 7808 => Opcode::SUQADDv4i32, + 7809 => Opcode::SUQADDv8i16, + 7810 => Opcode::SUQADDv8i8, + 7811 => Opcode::SUTMOPA_M2ZZZI_BtoS, + 7812 => Opcode::SUVDOT_VG4_M4ZZI_BToS, + 7813 => Opcode::SVC, + 7814 => Opcode::SVDOT_VG2_M2ZZI_HtoS, + 7815 => Opcode::SVDOT_VG4_M4ZZI_BtoS, + 7816 => Opcode::SVDOT_VG4_M4ZZI_HtoD, + 7817 => Opcode::SWPAB, + 7818 => Opcode::SWPAH, + 7819 => Opcode::SWPALB, + 7820 => Opcode::SWPALH, + 7821 => Opcode::SWPALW, + 7822 => Opcode::SWPALX, + 7823 => Opcode::SWPAW, + 7824 => Opcode::SWPAX, + 7825 => Opcode::SWPB, + 7826 => Opcode::SWPH, + 7827 => Opcode::SWPLB, + 7828 => Opcode::SWPLH, + 7829 => Opcode::SWPLW, + 7830 => Opcode::SWPLX, + 7831 => Opcode::SWPP, + 7832 => Opcode::SWPPA, + 7833 => Opcode::SWPPAL, + 7834 => Opcode::SWPPL, + 7835 => Opcode::SWPTALW, + 7836 => Opcode::SWPTALX, + 7837 => Opcode::SWPTAW, + 7838 => Opcode::SWPTAX, + 7839 => Opcode::SWPTLW, + 7840 => Opcode::SWPTLX, + 7841 => Opcode::SWPTW, + 7842 => Opcode::SWPTX, + 7843 => Opcode::SWPW, + 7844 => Opcode::SWPX, + 7845 => Opcode::SXTB_ZPmZ_D, + 7846 => Opcode::SXTB_ZPmZ_H, + 7847 => Opcode::SXTB_ZPmZ_S, + 7848 => Opcode::SXTB_ZPzZ_D, + 7849 => Opcode::SXTB_ZPzZ_H, + 7850 => Opcode::SXTB_ZPzZ_S, + 7851 => Opcode::SXTH_ZPmZ_D, + 7852 => Opcode::SXTH_ZPmZ_S, + 7853 => Opcode::SXTH_ZPzZ_D, + 7854 => Opcode::SXTH_ZPzZ_S, + 7855 => Opcode::SXTW_ZPmZ_D, + 7856 => Opcode::SXTW_ZPzZ_D, + 7857 => Opcode::SYSLxt, + 7858 => Opcode::SYSPxt, + 7859 => Opcode::SYSPxt_XZR, + 7860 => Opcode::SYSxt, + 7861 => Opcode::TBLQ_ZZZ_B, + 7862 => Opcode::TBLQ_ZZZ_D, + 7863 => Opcode::TBLQ_ZZZ_H, + 7864 => Opcode::TBLQ_ZZZ_S, + 7865 => Opcode::TBL_ZZZZ_B, + 7866 => Opcode::TBL_ZZZZ_D, + 7867 => Opcode::TBL_ZZZZ_H, + 7868 => Opcode::TBL_ZZZZ_S, + 7869 => Opcode::TBL_ZZZ_B, + 7870 => Opcode::TBL_ZZZ_D, + 7871 => Opcode::TBL_ZZZ_H, + 7872 => Opcode::TBL_ZZZ_S, + 7873 => Opcode::TBLv16i8Four, + 7874 => Opcode::TBLv16i8One, + 7875 => Opcode::TBLv16i8Three, + 7876 => Opcode::TBLv16i8Two, + 7877 => Opcode::TBLv8i8Four, + 7878 => Opcode::TBLv8i8One, + 7879 => Opcode::TBLv8i8Three, + 7880 => Opcode::TBLv8i8Two, + 7881 => Opcode::TBNZW, + 7882 => Opcode::TBNZX, + 7883 => Opcode::TBXQ_ZZZ_B, + 7884 => Opcode::TBXQ_ZZZ_D, + 7885 => Opcode::TBXQ_ZZZ_H, + 7886 => Opcode::TBXQ_ZZZ_S, + 7887 => Opcode::TBX_ZZZ_B, + 7888 => Opcode::TBX_ZZZ_D, + 7889 => Opcode::TBX_ZZZ_H, + 7890 => Opcode::TBX_ZZZ_S, + 7891 => Opcode::TBXv16i8Four, + 7892 => Opcode::TBXv16i8One, + 7893 => Opcode::TBXv16i8Three, + 7894 => Opcode::TBXv16i8Two, + 7895 => Opcode::TBXv8i8Four, + 7896 => Opcode::TBXv8i8One, + 7897 => Opcode::TBXv8i8Three, + 7898 => Opcode::TBXv8i8Two, + 7899 => Opcode::TBZW, + 7900 => Opcode::TBZX, + 7901 => Opcode::TCHANGEBri, + 7902 => Opcode::TCHANGEBrr, + 7903 => Opcode::TCHANGEFri, + 7904 => Opcode::TCHANGEFrr, + 7905 => Opcode::TENTER, + 7906 => Opcode::TEXIT, + 7907 => Opcode::TRCIT, + 7908 => Opcode::TRN1_PPP_B, + 7909 => Opcode::TRN1_PPP_D, + 7910 => Opcode::TRN1_PPP_H, + 7911 => Opcode::TRN1_PPP_S, + 7912 => Opcode::TRN1_ZZZ_B, + 7913 => Opcode::TRN1_ZZZ_D, + 7914 => Opcode::TRN1_ZZZ_H, + 7915 => Opcode::TRN1_ZZZ_Q, + 7916 => Opcode::TRN1_ZZZ_S, + 7917 => Opcode::TRN1v16i8, + 7918 => Opcode::TRN1v2i32, + 7919 => Opcode::TRN1v2i64, + 7920 => Opcode::TRN1v4i16, + 7921 => Opcode::TRN1v4i32, + 7922 => Opcode::TRN1v8i16, + 7923 => Opcode::TRN1v8i8, + 7924 => Opcode::TRN2_PPP_B, + 7925 => Opcode::TRN2_PPP_D, + 7926 => Opcode::TRN2_PPP_H, + 7927 => Opcode::TRN2_PPP_S, + 7928 => Opcode::TRN2_ZZZ_B, + 7929 => Opcode::TRN2_ZZZ_D, + 7930 => Opcode::TRN2_ZZZ_H, + 7931 => Opcode::TRN2_ZZZ_Q, + 7932 => Opcode::TRN2_ZZZ_S, + 7933 => Opcode::TRN2v16i8, + 7934 => Opcode::TRN2v2i32, + 7935 => Opcode::TRN2v2i64, + 7936 => Opcode::TRN2v4i16, + 7937 => Opcode::TRN2v4i32, + 7938 => Opcode::TRN2v8i16, + 7939 => Opcode::TRN2v8i8, + 7940 => Opcode::TSB, + 7941 => Opcode::UABALB_ZZZ_D, + 7942 => Opcode::UABALB_ZZZ_H, + 7943 => Opcode::UABALB_ZZZ_S, + 7944 => Opcode::UABALT_ZZZ_D, + 7945 => Opcode::UABALT_ZZZ_H, + 7946 => Opcode::UABALT_ZZZ_S, + 7947 => Opcode::UABAL_ZZZ_BtoH, + 7948 => Opcode::UABAL_ZZZ_HtoS, + 7949 => Opcode::UABAL_ZZZ_StoD, + 7950 => Opcode::UABALv16i8_v8i16, + 7951 => Opcode::UABALv2i32_v2i64, + 7952 => Opcode::UABALv4i16_v4i32, + 7953 => Opcode::UABALv4i32_v2i64, + 7954 => Opcode::UABALv8i16_v4i32, + 7955 => Opcode::UABALv8i8_v8i16, + 7956 => Opcode::UABA_ZZZ_B, + 7957 => Opcode::UABA_ZZZ_D, + 7958 => Opcode::UABA_ZZZ_H, + 7959 => Opcode::UABA_ZZZ_S, + 7960 => Opcode::UABAv16i8, + 7961 => Opcode::UABAv2i32, + 7962 => Opcode::UABAv4i16, + 7963 => Opcode::UABAv4i32, + 7964 => Opcode::UABAv8i16, + 7965 => Opcode::UABAv8i8, + 7966 => Opcode::UABDLB_ZZZ_D, + 7967 => Opcode::UABDLB_ZZZ_H, + 7968 => Opcode::UABDLB_ZZZ_S, + 7969 => Opcode::UABDLT_ZZZ_D, + 7970 => Opcode::UABDLT_ZZZ_H, + 7971 => Opcode::UABDLT_ZZZ_S, + 7972 => Opcode::UABDLv16i8_v8i16, + 7973 => Opcode::UABDLv2i32_v2i64, + 7974 => Opcode::UABDLv4i16_v4i32, + 7975 => Opcode::UABDLv4i32_v2i64, + 7976 => Opcode::UABDLv8i16_v4i32, + 7977 => Opcode::UABDLv8i8_v8i16, + 7978 => Opcode::UABD_ZPmZ_B, + 7979 => Opcode::UABD_ZPmZ_D, + 7980 => Opcode::UABD_ZPmZ_H, + 7981 => Opcode::UABD_ZPmZ_S, + 7982 => Opcode::UABDv16i8, + 7983 => Opcode::UABDv2i32, + 7984 => Opcode::UABDv4i16, + 7985 => Opcode::UABDv4i32, + 7986 => Opcode::UABDv8i16, + 7987 => Opcode::UABDv8i8, + 7988 => Opcode::UADALP_ZPmZ_D, + 7989 => Opcode::UADALP_ZPmZ_H, + 7990 => Opcode::UADALP_ZPmZ_S, + 7991 => Opcode::UADALPv16i8_v8i16, + 7992 => Opcode::UADALPv2i32_v1i64, + 7993 => Opcode::UADALPv4i16_v2i32, + 7994 => Opcode::UADALPv4i32_v2i64, + 7995 => Opcode::UADALPv8i16_v4i32, + 7996 => Opcode::UADALPv8i8_v4i16, + 7997 => Opcode::UADDLB_ZZZ_D, + 7998 => Opcode::UADDLB_ZZZ_H, + 7999 => Opcode::UADDLB_ZZZ_S, + 8000 => Opcode::UADDLPv16i8_v8i16, + 8001 => Opcode::UADDLPv2i32_v1i64, + 8002 => Opcode::UADDLPv4i16_v2i32, + 8003 => Opcode::UADDLPv4i32_v2i64, + 8004 => Opcode::UADDLPv8i16_v4i32, + 8005 => Opcode::UADDLPv8i8_v4i16, + 8006 => Opcode::UADDLT_ZZZ_D, + 8007 => Opcode::UADDLT_ZZZ_H, + 8008 => Opcode::UADDLT_ZZZ_S, + 8009 => Opcode::UADDLVv16i8v, + 8010 => Opcode::UADDLVv4i16v, + 8011 => Opcode::UADDLVv4i32v, + 8012 => Opcode::UADDLVv8i16v, + 8013 => Opcode::UADDLVv8i8v, + 8014 => Opcode::UADDLv16i8_v8i16, + 8015 => Opcode::UADDLv2i32_v2i64, + 8016 => Opcode::UADDLv4i16_v4i32, + 8017 => Opcode::UADDLv4i32_v2i64, + 8018 => Opcode::UADDLv8i16_v4i32, + 8019 => Opcode::UADDLv8i8_v8i16, + 8020 => Opcode::UADDV_VPZ_B, + 8021 => Opcode::UADDV_VPZ_D, + 8022 => Opcode::UADDV_VPZ_H, + 8023 => Opcode::UADDV_VPZ_S, + 8024 => Opcode::UADDWB_ZZZ_D, + 8025 => Opcode::UADDWB_ZZZ_H, + 8026 => Opcode::UADDWB_ZZZ_S, + 8027 => Opcode::UADDWT_ZZZ_D, + 8028 => Opcode::UADDWT_ZZZ_H, + 8029 => Opcode::UADDWT_ZZZ_S, + 8030 => Opcode::UADDWv16i8_v8i16, + 8031 => Opcode::UADDWv2i32_v2i64, + 8032 => Opcode::UADDWv4i16_v4i32, + 8033 => Opcode::UADDWv4i32_v2i64, + 8034 => Opcode::UADDWv8i16_v4i32, + 8035 => Opcode::UADDWv8i8_v8i16, + 8036 => Opcode::UBFMWri, + 8037 => Opcode::UBFMXri, + 8038 => Opcode::UCLAMP_VG2_2Z2Z_B, + 8039 => Opcode::UCLAMP_VG2_2Z2Z_D, + 8040 => Opcode::UCLAMP_VG2_2Z2Z_H, + 8041 => Opcode::UCLAMP_VG2_2Z2Z_S, + 8042 => Opcode::UCLAMP_VG4_4Z4Z_B, + 8043 => Opcode::UCLAMP_VG4_4Z4Z_D, + 8044 => Opcode::UCLAMP_VG4_4Z4Z_H, + 8045 => Opcode::UCLAMP_VG4_4Z4Z_S, + 8046 => Opcode::UCLAMP_ZZZ_B, + 8047 => Opcode::UCLAMP_ZZZ_D, + 8048 => Opcode::UCLAMP_ZZZ_H, + 8049 => Opcode::UCLAMP_ZZZ_S, + 8050 => Opcode::UCVTFDSr, + 8051 => Opcode::UCVTFHDr, + 8052 => Opcode::UCVTFHSr, + 8053 => Opcode::UCVTFLT_ZZ_BtoH, + 8054 => Opcode::UCVTFLT_ZZ_HtoS, + 8055 => Opcode::UCVTFLT_ZZ_StoD, + 8056 => Opcode::UCVTFSDr, + 8057 => Opcode::UCVTFSWDri, + 8058 => Opcode::UCVTFSWHri, + 8059 => Opcode::UCVTFSWSri, + 8060 => Opcode::UCVTFSXDri, + 8061 => Opcode::UCVTFSXHri, + 8062 => Opcode::UCVTFSXSri, + 8063 => Opcode::UCVTFUWDri, + 8064 => Opcode::UCVTFUWHri, + 8065 => Opcode::UCVTFUWSri, + 8066 => Opcode::UCVTFUXDri, + 8067 => Opcode::UCVTFUXHri, + 8068 => Opcode::UCVTFUXSri, + 8069 => Opcode::UCVTF_2Z2Z_StoS, + 8070 => Opcode::UCVTF_4Z4Z_StoS, + 8071 => Opcode::UCVTF_ZPmZ_DtoD, + 8072 => Opcode::UCVTF_ZPmZ_DtoH, + 8073 => Opcode::UCVTF_ZPmZ_DtoS, + 8074 => Opcode::UCVTF_ZPmZ_HtoH, + 8075 => Opcode::UCVTF_ZPmZ_StoD, + 8076 => Opcode::UCVTF_ZPmZ_StoH, + 8077 => Opcode::UCVTF_ZPmZ_StoS, + 8078 => Opcode::UCVTF_ZPzZ_DtoD, + 8079 => Opcode::UCVTF_ZPzZ_DtoH, + 8080 => Opcode::UCVTF_ZPzZ_DtoS, + 8081 => Opcode::UCVTF_ZPzZ_HtoH, + 8082 => Opcode::UCVTF_ZPzZ_StoD, + 8083 => Opcode::UCVTF_ZPzZ_StoH, + 8084 => Opcode::UCVTF_ZPzZ_StoS, + 8085 => Opcode::UCVTF_ZZ_BtoH, + 8086 => Opcode::UCVTF_ZZ_HtoS, + 8087 => Opcode::UCVTF_ZZ_StoD, + 8088 => Opcode::UCVTFd, + 8089 => Opcode::UCVTFh, + 8090 => Opcode::UCVTFs, + 8091 => Opcode::UCVTFv1i16, + 8092 => Opcode::UCVTFv1i32, + 8093 => Opcode::UCVTFv1i64, + 8094 => Opcode::UCVTFv2f32, + 8095 => Opcode::UCVTFv2f64, + 8096 => Opcode::UCVTFv2i32_shift, + 8097 => Opcode::UCVTFv2i64_shift, + 8098 => Opcode::UCVTFv4f16, + 8099 => Opcode::UCVTFv4f32, + 8100 => Opcode::UCVTFv4i16_shift, + 8101 => Opcode::UCVTFv4i32_shift, + 8102 => Opcode::UCVTFv8f16, + 8103 => Opcode::UCVTFv8i16_shift, + 8104 => Opcode::UDF, + 8105 => Opcode::UDIVR_ZPmZ_D, + 8106 => Opcode::UDIVR_ZPmZ_S, + 8107 => Opcode::UDIVWr, + 8108 => Opcode::UDIVXr, + 8109 => Opcode::UDIV_ZPmZ_D, + 8110 => Opcode::UDIV_ZPmZ_S, + 8111 => Opcode::UDOT_VG2_M2Z2Z_BtoS, + 8112 => Opcode::UDOT_VG2_M2Z2Z_HtoD, + 8113 => Opcode::UDOT_VG2_M2Z2Z_HtoS, + 8114 => Opcode::UDOT_VG2_M2ZZI_BToS, + 8115 => Opcode::UDOT_VG2_M2ZZI_HToS, + 8116 => Opcode::UDOT_VG2_M2ZZI_HtoD, + 8117 => Opcode::UDOT_VG2_M2ZZ_BtoS, + 8118 => Opcode::UDOT_VG2_M2ZZ_HtoD, + 8119 => Opcode::UDOT_VG2_M2ZZ_HtoS, + 8120 => Opcode::UDOT_VG4_M4Z4Z_BtoS, + 8121 => Opcode::UDOT_VG4_M4Z4Z_HtoD, + 8122 => Opcode::UDOT_VG4_M4Z4Z_HtoS, + 8123 => Opcode::UDOT_VG4_M4ZZI_BtoS, + 8124 => Opcode::UDOT_VG4_M4ZZI_HToS, + 8125 => Opcode::UDOT_VG4_M4ZZI_HtoD, + 8126 => Opcode::UDOT_VG4_M4ZZ_BtoS, + 8127 => Opcode::UDOT_VG4_M4ZZ_HtoD, + 8128 => Opcode::UDOT_VG4_M4ZZ_HtoS, + 8129 => Opcode::UDOT_ZZZI_BtoH, + 8130 => Opcode::UDOT_ZZZI_BtoS, + 8131 => Opcode::UDOT_ZZZI_HtoD, + 8132 => Opcode::UDOT_ZZZI_HtoS, + 8133 => Opcode::UDOT_ZZZ_BtoH, + 8134 => Opcode::UDOT_ZZZ_BtoS, + 8135 => Opcode::UDOT_ZZZ_HtoD, + 8136 => Opcode::UDOT_ZZZ_HtoS, + 8137 => Opcode::UDOTlanev16i8, + 8138 => Opcode::UDOTlanev8i8, + 8139 => Opcode::UDOTv16i8, + 8140 => Opcode::UDOTv8i8, + 8141 => Opcode::UHADD_ZPmZ_B, + 8142 => Opcode::UHADD_ZPmZ_D, + 8143 => Opcode::UHADD_ZPmZ_H, + 8144 => Opcode::UHADD_ZPmZ_S, + 8145 => Opcode::UHADDv16i8, + 8146 => Opcode::UHADDv2i32, + 8147 => Opcode::UHADDv4i16, + 8148 => Opcode::UHADDv4i32, + 8149 => Opcode::UHADDv8i16, + 8150 => Opcode::UHADDv8i8, + 8151 => Opcode::UHSUBR_ZPmZ_B, + 8152 => Opcode::UHSUBR_ZPmZ_D, + 8153 => Opcode::UHSUBR_ZPmZ_H, + 8154 => Opcode::UHSUBR_ZPmZ_S, + 8155 => Opcode::UHSUB_ZPmZ_B, + 8156 => Opcode::UHSUB_ZPmZ_D, + 8157 => Opcode::UHSUB_ZPmZ_H, + 8158 => Opcode::UHSUB_ZPmZ_S, + 8159 => Opcode::UHSUBv16i8, + 8160 => Opcode::UHSUBv2i32, + 8161 => Opcode::UHSUBv4i16, + 8162 => Opcode::UHSUBv4i32, + 8163 => Opcode::UHSUBv8i16, + 8164 => Opcode::UHSUBv8i8, + 8165 => Opcode::UMADDLrrr, + 8166 => Opcode::UMAXP_ZPmZ_B, + 8167 => Opcode::UMAXP_ZPmZ_D, + 8168 => Opcode::UMAXP_ZPmZ_H, + 8169 => Opcode::UMAXP_ZPmZ_S, + 8170 => Opcode::UMAXPv16i8, + 8171 => Opcode::UMAXPv2i32, + 8172 => Opcode::UMAXPv4i16, + 8173 => Opcode::UMAXPv4i32, + 8174 => Opcode::UMAXPv8i16, + 8175 => Opcode::UMAXPv8i8, + 8176 => Opcode::UMAXQV_VPZ_B, + 8177 => Opcode::UMAXQV_VPZ_D, + 8178 => Opcode::UMAXQV_VPZ_H, + 8179 => Opcode::UMAXQV_VPZ_S, + 8180 => Opcode::UMAXV_VPZ_B, + 8181 => Opcode::UMAXV_VPZ_D, + 8182 => Opcode::UMAXV_VPZ_H, + 8183 => Opcode::UMAXV_VPZ_S, + 8184 => Opcode::UMAXVv16i8v, + 8185 => Opcode::UMAXVv4i16v, + 8186 => Opcode::UMAXVv4i32v, + 8187 => Opcode::UMAXVv8i16v, + 8188 => Opcode::UMAXVv8i8v, + 8189 => Opcode::UMAXWri, + 8190 => Opcode::UMAXWrr, + 8191 => Opcode::UMAXXri, + 8192 => Opcode::UMAXXrr, + 8193 => Opcode::UMAX_VG2_2Z2Z_B, + 8194 => Opcode::UMAX_VG2_2Z2Z_D, + 8195 => Opcode::UMAX_VG2_2Z2Z_H, + 8196 => Opcode::UMAX_VG2_2Z2Z_S, + 8197 => Opcode::UMAX_VG2_2ZZ_B, + 8198 => Opcode::UMAX_VG2_2ZZ_D, + 8199 => Opcode::UMAX_VG2_2ZZ_H, + 8200 => Opcode::UMAX_VG2_2ZZ_S, + 8201 => Opcode::UMAX_VG4_4Z4Z_B, + 8202 => Opcode::UMAX_VG4_4Z4Z_D, + 8203 => Opcode::UMAX_VG4_4Z4Z_H, + 8204 => Opcode::UMAX_VG4_4Z4Z_S, + 8205 => Opcode::UMAX_VG4_4ZZ_B, + 8206 => Opcode::UMAX_VG4_4ZZ_D, + 8207 => Opcode::UMAX_VG4_4ZZ_H, + 8208 => Opcode::UMAX_VG4_4ZZ_S, + 8209 => Opcode::UMAX_ZI_B, + 8210 => Opcode::UMAX_ZI_D, + 8211 => Opcode::UMAX_ZI_H, + 8212 => Opcode::UMAX_ZI_S, + 8213 => Opcode::UMAX_ZPmZ_B, + 8214 => Opcode::UMAX_ZPmZ_D, + 8215 => Opcode::UMAX_ZPmZ_H, + 8216 => Opcode::UMAX_ZPmZ_S, + 8217 => Opcode::UMAXv16i8, + 8218 => Opcode::UMAXv2i32, + 8219 => Opcode::UMAXv4i16, + 8220 => Opcode::UMAXv4i32, + 8221 => Opcode::UMAXv8i16, + 8222 => Opcode::UMAXv8i8, + 8223 => Opcode::UMINP_ZPmZ_B, + 8224 => Opcode::UMINP_ZPmZ_D, + 8225 => Opcode::UMINP_ZPmZ_H, + 8226 => Opcode::UMINP_ZPmZ_S, + 8227 => Opcode::UMINPv16i8, + 8228 => Opcode::UMINPv2i32, + 8229 => Opcode::UMINPv4i16, + 8230 => Opcode::UMINPv4i32, + 8231 => Opcode::UMINPv8i16, + 8232 => Opcode::UMINPv8i8, + 8233 => Opcode::UMINQV_VPZ_B, + 8234 => Opcode::UMINQV_VPZ_D, + 8235 => Opcode::UMINQV_VPZ_H, + 8236 => Opcode::UMINQV_VPZ_S, + 8237 => Opcode::UMINV_VPZ_B, + 8238 => Opcode::UMINV_VPZ_D, + 8239 => Opcode::UMINV_VPZ_H, + 8240 => Opcode::UMINV_VPZ_S, + 8241 => Opcode::UMINVv16i8v, + 8242 => Opcode::UMINVv4i16v, + 8243 => Opcode::UMINVv4i32v, + 8244 => Opcode::UMINVv8i16v, + 8245 => Opcode::UMINVv8i8v, + 8246 => Opcode::UMINWri, + 8247 => Opcode::UMINWrr, + 8248 => Opcode::UMINXri, + 8249 => Opcode::UMINXrr, + 8250 => Opcode::UMIN_VG2_2Z2Z_B, + 8251 => Opcode::UMIN_VG2_2Z2Z_D, + 8252 => Opcode::UMIN_VG2_2Z2Z_H, + 8253 => Opcode::UMIN_VG2_2Z2Z_S, + 8254 => Opcode::UMIN_VG2_2ZZ_B, + 8255 => Opcode::UMIN_VG2_2ZZ_D, + 8256 => Opcode::UMIN_VG2_2ZZ_H, + 8257 => Opcode::UMIN_VG2_2ZZ_S, + 8258 => Opcode::UMIN_VG4_4Z4Z_B, + 8259 => Opcode::UMIN_VG4_4Z4Z_D, + 8260 => Opcode::UMIN_VG4_4Z4Z_H, + 8261 => Opcode::UMIN_VG4_4Z4Z_S, + 8262 => Opcode::UMIN_VG4_4ZZ_B, + 8263 => Opcode::UMIN_VG4_4ZZ_D, + 8264 => Opcode::UMIN_VG4_4ZZ_H, + 8265 => Opcode::UMIN_VG4_4ZZ_S, + 8266 => Opcode::UMIN_ZI_B, + 8267 => Opcode::UMIN_ZI_D, + 8268 => Opcode::UMIN_ZI_H, + 8269 => Opcode::UMIN_ZI_S, + 8270 => Opcode::UMIN_ZPmZ_B, + 8271 => Opcode::UMIN_ZPmZ_D, + 8272 => Opcode::UMIN_ZPmZ_H, + 8273 => Opcode::UMIN_ZPmZ_S, + 8274 => Opcode::UMINv16i8, + 8275 => Opcode::UMINv2i32, + 8276 => Opcode::UMINv4i16, + 8277 => Opcode::UMINv4i32, + 8278 => Opcode::UMINv8i16, + 8279 => Opcode::UMINv8i8, + 8280 => Opcode::UMLALB_ZZZI_D, + 8281 => Opcode::UMLALB_ZZZI_S, + 8282 => Opcode::UMLALB_ZZZ_D, + 8283 => Opcode::UMLALB_ZZZ_H, + 8284 => Opcode::UMLALB_ZZZ_S, + 8285 => Opcode::UMLALL_MZZI_BtoS, + 8286 => Opcode::UMLALL_MZZI_HtoD, + 8287 => Opcode::UMLALL_MZZ_BtoS, + 8288 => Opcode::UMLALL_MZZ_HtoD, + 8289 => Opcode::UMLALL_VG2_M2Z2Z_BtoS, + 8290 => Opcode::UMLALL_VG2_M2Z2Z_HtoD, + 8291 => Opcode::UMLALL_VG2_M2ZZI_BtoS, + 8292 => Opcode::UMLALL_VG2_M2ZZI_HtoD, + 8293 => Opcode::UMLALL_VG2_M2ZZ_BtoS, + 8294 => Opcode::UMLALL_VG2_M2ZZ_HtoD, + 8295 => Opcode::UMLALL_VG4_M4Z4Z_BtoS, + 8296 => Opcode::UMLALL_VG4_M4Z4Z_HtoD, + 8297 => Opcode::UMLALL_VG4_M4ZZI_BtoS, + 8298 => Opcode::UMLALL_VG4_M4ZZI_HtoD, + 8299 => Opcode::UMLALL_VG4_M4ZZ_BtoS, + 8300 => Opcode::UMLALL_VG4_M4ZZ_HtoD, + 8301 => Opcode::UMLALT_ZZZI_D, + 8302 => Opcode::UMLALT_ZZZI_S, + 8303 => Opcode::UMLALT_ZZZ_D, + 8304 => Opcode::UMLALT_ZZZ_H, + 8305 => Opcode::UMLALT_ZZZ_S, + 8306 => Opcode::UMLAL_MZZI_HtoS, + 8307 => Opcode::UMLAL_MZZ_HtoS, + 8308 => Opcode::UMLAL_VG2_M2Z2Z_HtoS, + 8309 => Opcode::UMLAL_VG2_M2ZZI_S, + 8310 => Opcode::UMLAL_VG2_M2ZZ_HtoS, + 8311 => Opcode::UMLAL_VG4_M4Z4Z_HtoS, + 8312 => Opcode::UMLAL_VG4_M4ZZI_HtoS, + 8313 => Opcode::UMLAL_VG4_M4ZZ_HtoS, + 8314 => Opcode::UMLALv16i8_v8i16, + 8315 => Opcode::UMLALv2i32_indexed, + 8316 => Opcode::UMLALv2i32_v2i64, + 8317 => Opcode::UMLALv4i16_indexed, + 8318 => Opcode::UMLALv4i16_v4i32, + 8319 => Opcode::UMLALv4i32_indexed, + 8320 => Opcode::UMLALv4i32_v2i64, + 8321 => Opcode::UMLALv8i16_indexed, + 8322 => Opcode::UMLALv8i16_v4i32, + 8323 => Opcode::UMLALv8i8_v8i16, + 8324 => Opcode::UMLSLB_ZZZI_D, + 8325 => Opcode::UMLSLB_ZZZI_S, + 8326 => Opcode::UMLSLB_ZZZ_D, + 8327 => Opcode::UMLSLB_ZZZ_H, + 8328 => Opcode::UMLSLB_ZZZ_S, + 8329 => Opcode::UMLSLL_MZZI_BtoS, + 8330 => Opcode::UMLSLL_MZZI_HtoD, + 8331 => Opcode::UMLSLL_MZZ_BtoS, + 8332 => Opcode::UMLSLL_MZZ_HtoD, + 8333 => Opcode::UMLSLL_VG2_M2Z2Z_BtoS, + 8334 => Opcode::UMLSLL_VG2_M2Z2Z_HtoD, + 8335 => Opcode::UMLSLL_VG2_M2ZZI_BtoS, + 8336 => Opcode::UMLSLL_VG2_M2ZZI_HtoD, + 8337 => Opcode::UMLSLL_VG2_M2ZZ_BtoS, + 8338 => Opcode::UMLSLL_VG2_M2ZZ_HtoD, + 8339 => Opcode::UMLSLL_VG4_M4Z4Z_BtoS, + 8340 => Opcode::UMLSLL_VG4_M4Z4Z_HtoD, + 8341 => Opcode::UMLSLL_VG4_M4ZZI_BtoS, + 8342 => Opcode::UMLSLL_VG4_M4ZZI_HtoD, + 8343 => Opcode::UMLSLL_VG4_M4ZZ_BtoS, + 8344 => Opcode::UMLSLL_VG4_M4ZZ_HtoD, + 8345 => Opcode::UMLSLT_ZZZI_D, + 8346 => Opcode::UMLSLT_ZZZI_S, + 8347 => Opcode::UMLSLT_ZZZ_D, + 8348 => Opcode::UMLSLT_ZZZ_H, + 8349 => Opcode::UMLSLT_ZZZ_S, + 8350 => Opcode::UMLSL_MZZI_HtoS, + 8351 => Opcode::UMLSL_MZZ_HtoS, + 8352 => Opcode::UMLSL_VG2_M2Z2Z_HtoS, + 8353 => Opcode::UMLSL_VG2_M2ZZI_S, + 8354 => Opcode::UMLSL_VG2_M2ZZ_HtoS, + 8355 => Opcode::UMLSL_VG4_M4Z4Z_HtoS, + 8356 => Opcode::UMLSL_VG4_M4ZZI_HtoS, + 8357 => Opcode::UMLSL_VG4_M4ZZ_HtoS, + 8358 => Opcode::UMLSLv16i8_v8i16, + 8359 => Opcode::UMLSLv2i32_indexed, + 8360 => Opcode::UMLSLv2i32_v2i64, + 8361 => Opcode::UMLSLv4i16_indexed, + 8362 => Opcode::UMLSLv4i16_v4i32, + 8363 => Opcode::UMLSLv4i32_indexed, + 8364 => Opcode::UMLSLv4i32_v2i64, + 8365 => Opcode::UMLSLv8i16_indexed, + 8366 => Opcode::UMLSLv8i16_v4i32, + 8367 => Opcode::UMLSLv8i8_v8i16, + 8368 => Opcode::UMMLA, + 8369 => Opcode::UMMLA_ZZZ, + 8370 => Opcode::UMOP4A_M2Z2Z_BToS, + 8371 => Opcode::UMOP4A_M2Z2Z_HToS, + 8372 => Opcode::UMOP4A_M2Z2Z_HtoD, + 8373 => Opcode::UMOP4A_M2ZZ_BToS, + 8374 => Opcode::UMOP4A_M2ZZ_HToS, + 8375 => Opcode::UMOP4A_M2ZZ_HtoD, + 8376 => Opcode::UMOP4A_MZ2Z_BToS, + 8377 => Opcode::UMOP4A_MZ2Z_HToS, + 8378 => Opcode::UMOP4A_MZ2Z_HtoD, + 8379 => Opcode::UMOP4A_MZZ_BToS, + 8380 => Opcode::UMOP4A_MZZ_HToS, + 8381 => Opcode::UMOP4A_MZZ_HtoD, + 8382 => Opcode::UMOP4S_M2Z2Z_BToS, + 8383 => Opcode::UMOP4S_M2Z2Z_HToS, + 8384 => Opcode::UMOP4S_M2Z2Z_HtoD, + 8385 => Opcode::UMOP4S_M2ZZ_BToS, + 8386 => Opcode::UMOP4S_M2ZZ_HToS, + 8387 => Opcode::UMOP4S_M2ZZ_HtoD, + 8388 => Opcode::UMOP4S_MZ2Z_BToS, + 8389 => Opcode::UMOP4S_MZ2Z_HToS, + 8390 => Opcode::UMOP4S_MZ2Z_HtoD, + 8391 => Opcode::UMOP4S_MZZ_BToS, + 8392 => Opcode::UMOP4S_MZZ_HToS, + 8393 => Opcode::UMOP4S_MZZ_HtoD, + 8394 => Opcode::UMOPA_MPPZZ_D, + 8395 => Opcode::UMOPA_MPPZZ_HtoS, + 8396 => Opcode::UMOPA_MPPZZ_S, + 8397 => Opcode::UMOPS_MPPZZ_D, + 8398 => Opcode::UMOPS_MPPZZ_HtoS, + 8399 => Opcode::UMOPS_MPPZZ_S, + 8400 => Opcode::UMOVvi16, + 8401 => Opcode::UMOVvi16_idx0, + 8402 => Opcode::UMOVvi32, + 8403 => Opcode::UMOVvi32_idx0, + 8404 => Opcode::UMOVvi64, + 8405 => Opcode::UMOVvi64_idx0, + 8406 => Opcode::UMOVvi8, + 8407 => Opcode::UMOVvi8_idx0, + 8408 => Opcode::UMSUBLrrr, + 8409 => Opcode::UMULH_ZPmZ_B, + 8410 => Opcode::UMULH_ZPmZ_D, + 8411 => Opcode::UMULH_ZPmZ_H, + 8412 => Opcode::UMULH_ZPmZ_S, + 8413 => Opcode::UMULH_ZZZ_B, + 8414 => Opcode::UMULH_ZZZ_D, + 8415 => Opcode::UMULH_ZZZ_H, + 8416 => Opcode::UMULH_ZZZ_S, + 8417 => Opcode::UMULHrr, + 8418 => Opcode::UMULLB_ZZZI_D, + 8419 => Opcode::UMULLB_ZZZI_S, + 8420 => Opcode::UMULLB_ZZZ_D, + 8421 => Opcode::UMULLB_ZZZ_H, + 8422 => Opcode::UMULLB_ZZZ_S, + 8423 => Opcode::UMULLT_ZZZI_D, + 8424 => Opcode::UMULLT_ZZZI_S, + 8425 => Opcode::UMULLT_ZZZ_D, + 8426 => Opcode::UMULLT_ZZZ_H, + 8427 => Opcode::UMULLT_ZZZ_S, + 8428 => Opcode::UMULLv16i8_v8i16, + 8429 => Opcode::UMULLv2i32_indexed, + 8430 => Opcode::UMULLv2i32_v2i64, + 8431 => Opcode::UMULLv4i16_indexed, + 8432 => Opcode::UMULLv4i16_v4i32, + 8433 => Opcode::UMULLv4i32_indexed, + 8434 => Opcode::UMULLv4i32_v2i64, + 8435 => Opcode::UMULLv8i16_indexed, + 8436 => Opcode::UMULLv8i16_v4i32, + 8437 => Opcode::UMULLv8i8_v8i16, + 8438 => Opcode::UQADD_ZI_B, + 8439 => Opcode::UQADD_ZI_D, + 8440 => Opcode::UQADD_ZI_H, + 8441 => Opcode::UQADD_ZI_S, + 8442 => Opcode::UQADD_ZPmZ_B, + 8443 => Opcode::UQADD_ZPmZ_D, + 8444 => Opcode::UQADD_ZPmZ_H, + 8445 => Opcode::UQADD_ZPmZ_S, + 8446 => Opcode::UQADD_ZZZ_B, + 8447 => Opcode::UQADD_ZZZ_D, + 8448 => Opcode::UQADD_ZZZ_H, + 8449 => Opcode::UQADD_ZZZ_S, + 8450 => Opcode::UQADDv16i8, + 8451 => Opcode::UQADDv1i16, + 8452 => Opcode::UQADDv1i32, + 8453 => Opcode::UQADDv1i64, + 8454 => Opcode::UQADDv1i8, + 8455 => Opcode::UQADDv2i32, + 8456 => Opcode::UQADDv2i64, + 8457 => Opcode::UQADDv4i16, + 8458 => Opcode::UQADDv4i32, + 8459 => Opcode::UQADDv8i16, + 8460 => Opcode::UQADDv8i8, + 8461 => Opcode::UQCVTN_Z2Z_StoH, + 8462 => Opcode::UQCVTN_Z4Z_DtoH, + 8463 => Opcode::UQCVTN_Z4Z_StoB, + 8464 => Opcode::UQCVT_Z2Z_StoH, + 8465 => Opcode::UQCVT_Z4Z_DtoH, + 8466 => Opcode::UQCVT_Z4Z_StoB, + 8467 => Opcode::UQDECB_WPiI, + 8468 => Opcode::UQDECB_XPiI, + 8469 => Opcode::UQDECD_WPiI, + 8470 => Opcode::UQDECD_XPiI, + 8471 => Opcode::UQDECD_ZPiI, + 8472 => Opcode::UQDECH_WPiI, + 8473 => Opcode::UQDECH_XPiI, + 8474 => Opcode::UQDECH_ZPiI, + 8475 => Opcode::UQDECP_WP_B, + 8476 => Opcode::UQDECP_WP_D, + 8477 => Opcode::UQDECP_WP_H, + 8478 => Opcode::UQDECP_WP_S, + 8479 => Opcode::UQDECP_XP_B, + 8480 => Opcode::UQDECP_XP_D, + 8481 => Opcode::UQDECP_XP_H, + 8482 => Opcode::UQDECP_XP_S, + 8483 => Opcode::UQDECP_ZP_D, + 8484 => Opcode::UQDECP_ZP_H, + 8485 => Opcode::UQDECP_ZP_S, + 8486 => Opcode::UQDECW_WPiI, + 8487 => Opcode::UQDECW_XPiI, + 8488 => Opcode::UQDECW_ZPiI, + 8489 => Opcode::UQINCB_WPiI, + 8490 => Opcode::UQINCB_XPiI, + 8491 => Opcode::UQINCD_WPiI, + 8492 => Opcode::UQINCD_XPiI, + 8493 => Opcode::UQINCD_ZPiI, + 8494 => Opcode::UQINCH_WPiI, + 8495 => Opcode::UQINCH_XPiI, + 8496 => Opcode::UQINCH_ZPiI, + 8497 => Opcode::UQINCP_WP_B, + 8498 => Opcode::UQINCP_WP_D, + 8499 => Opcode::UQINCP_WP_H, + 8500 => Opcode::UQINCP_WP_S, + 8501 => Opcode::UQINCP_XP_B, + 8502 => Opcode::UQINCP_XP_D, + 8503 => Opcode::UQINCP_XP_H, + 8504 => Opcode::UQINCP_XP_S, + 8505 => Opcode::UQINCP_ZP_D, + 8506 => Opcode::UQINCP_ZP_H, + 8507 => Opcode::UQINCP_ZP_S, + 8508 => Opcode::UQINCW_WPiI, + 8509 => Opcode::UQINCW_XPiI, + 8510 => Opcode::UQINCW_ZPiI, + 8511 => Opcode::UQRSHLR_ZPmZ_B, + 8512 => Opcode::UQRSHLR_ZPmZ_D, + 8513 => Opcode::UQRSHLR_ZPmZ_H, + 8514 => Opcode::UQRSHLR_ZPmZ_S, + 8515 => Opcode::UQRSHL_ZPmZ_B, + 8516 => Opcode::UQRSHL_ZPmZ_D, + 8517 => Opcode::UQRSHL_ZPmZ_H, + 8518 => Opcode::UQRSHL_ZPmZ_S, + 8519 => Opcode::UQRSHLv16i8, + 8520 => Opcode::UQRSHLv1i16, + 8521 => Opcode::UQRSHLv1i32, + 8522 => Opcode::UQRSHLv1i64, + 8523 => Opcode::UQRSHLv1i8, + 8524 => Opcode::UQRSHLv2i32, + 8525 => Opcode::UQRSHLv2i64, + 8526 => Opcode::UQRSHLv4i16, + 8527 => Opcode::UQRSHLv4i32, + 8528 => Opcode::UQRSHLv8i16, + 8529 => Opcode::UQRSHLv8i8, + 8530 => Opcode::UQRSHRNB_ZZI_B, + 8531 => Opcode::UQRSHRNB_ZZI_H, + 8532 => Opcode::UQRSHRNB_ZZI_S, + 8533 => Opcode::UQRSHRNT_ZZI_B, + 8534 => Opcode::UQRSHRNT_ZZI_H, + 8535 => Opcode::UQRSHRNT_ZZI_S, + 8536 => Opcode::UQRSHRN_VG4_Z4ZI_B, + 8537 => Opcode::UQRSHRN_VG4_Z4ZI_H, + 8538 => Opcode::UQRSHRN_Z2ZI_HtoB, + 8539 => Opcode::UQRSHRN_Z2ZI_StoH, + 8540 => Opcode::UQRSHRNb, + 8541 => Opcode::UQRSHRNh, + 8542 => Opcode::UQRSHRNs, + 8543 => Opcode::UQRSHRNv16i8_shift, + 8544 => Opcode::UQRSHRNv2i32_shift, + 8545 => Opcode::UQRSHRNv4i16_shift, + 8546 => Opcode::UQRSHRNv4i32_shift, + 8547 => Opcode::UQRSHRNv8i16_shift, + 8548 => Opcode::UQRSHRNv8i8_shift, + 8549 => Opcode::UQRSHR_VG2_Z2ZI_H, + 8550 => Opcode::UQRSHR_VG4_Z4ZI_B, + 8551 => Opcode::UQRSHR_VG4_Z4ZI_H, + 8552 => Opcode::UQSHLR_ZPmZ_B, + 8553 => Opcode::UQSHLR_ZPmZ_D, + 8554 => Opcode::UQSHLR_ZPmZ_H, + 8555 => Opcode::UQSHLR_ZPmZ_S, + 8556 => Opcode::UQSHL_ZPmI_B, + 8557 => Opcode::UQSHL_ZPmI_D, + 8558 => Opcode::UQSHL_ZPmI_H, + 8559 => Opcode::UQSHL_ZPmI_S, + 8560 => Opcode::UQSHL_ZPmZ_B, + 8561 => Opcode::UQSHL_ZPmZ_D, + 8562 => Opcode::UQSHL_ZPmZ_H, + 8563 => Opcode::UQSHL_ZPmZ_S, + 8564 => Opcode::UQSHLb, + 8565 => Opcode::UQSHLd, + 8566 => Opcode::UQSHLh, + 8567 => Opcode::UQSHLs, + 8568 => Opcode::UQSHLv16i8, + 8569 => Opcode::UQSHLv16i8_shift, + 8570 => Opcode::UQSHLv1i16, + 8571 => Opcode::UQSHLv1i32, + 8572 => Opcode::UQSHLv1i64, + 8573 => Opcode::UQSHLv1i8, + 8574 => Opcode::UQSHLv2i32, + 8575 => Opcode::UQSHLv2i32_shift, + 8576 => Opcode::UQSHLv2i64, + 8577 => Opcode::UQSHLv2i64_shift, + 8578 => Opcode::UQSHLv4i16, + 8579 => Opcode::UQSHLv4i16_shift, + 8580 => Opcode::UQSHLv4i32, + 8581 => Opcode::UQSHLv4i32_shift, + 8582 => Opcode::UQSHLv8i16, + 8583 => Opcode::UQSHLv8i16_shift, + 8584 => Opcode::UQSHLv8i8, + 8585 => Opcode::UQSHLv8i8_shift, + 8586 => Opcode::UQSHRNB_ZZI_B, + 8587 => Opcode::UQSHRNB_ZZI_H, + 8588 => Opcode::UQSHRNB_ZZI_S, + 8589 => Opcode::UQSHRNT_ZZI_B, + 8590 => Opcode::UQSHRNT_ZZI_H, + 8591 => Opcode::UQSHRNT_ZZI_S, + 8592 => Opcode::UQSHRN_Z2ZI_HtoB, + 8593 => Opcode::UQSHRN_Z2ZI_StoH, + 8594 => Opcode::UQSHRNb, + 8595 => Opcode::UQSHRNh, + 8596 => Opcode::UQSHRNs, + 8597 => Opcode::UQSHRNv16i8_shift, + 8598 => Opcode::UQSHRNv2i32_shift, + 8599 => Opcode::UQSHRNv4i16_shift, + 8600 => Opcode::UQSHRNv4i32_shift, + 8601 => Opcode::UQSHRNv8i16_shift, + 8602 => Opcode::UQSHRNv8i8_shift, + 8603 => Opcode::UQSUBR_ZPmZ_B, + 8604 => Opcode::UQSUBR_ZPmZ_D, + 8605 => Opcode::UQSUBR_ZPmZ_H, + 8606 => Opcode::UQSUBR_ZPmZ_S, + 8607 => Opcode::UQSUB_ZI_B, + 8608 => Opcode::UQSUB_ZI_D, + 8609 => Opcode::UQSUB_ZI_H, + 8610 => Opcode::UQSUB_ZI_S, + 8611 => Opcode::UQSUB_ZPmZ_B, + 8612 => Opcode::UQSUB_ZPmZ_D, + 8613 => Opcode::UQSUB_ZPmZ_H, + 8614 => Opcode::UQSUB_ZPmZ_S, + 8615 => Opcode::UQSUB_ZZZ_B, + 8616 => Opcode::UQSUB_ZZZ_D, + 8617 => Opcode::UQSUB_ZZZ_H, + 8618 => Opcode::UQSUB_ZZZ_S, + 8619 => Opcode::UQSUBv16i8, + 8620 => Opcode::UQSUBv1i16, + 8621 => Opcode::UQSUBv1i32, + 8622 => Opcode::UQSUBv1i64, + 8623 => Opcode::UQSUBv1i8, + 8624 => Opcode::UQSUBv2i32, + 8625 => Opcode::UQSUBv2i64, + 8626 => Opcode::UQSUBv4i16, + 8627 => Opcode::UQSUBv4i32, + 8628 => Opcode::UQSUBv8i16, + 8629 => Opcode::UQSUBv8i8, + 8630 => Opcode::UQXTNB_ZZ_B, + 8631 => Opcode::UQXTNB_ZZ_H, + 8632 => Opcode::UQXTNB_ZZ_S, + 8633 => Opcode::UQXTNT_ZZ_B, + 8634 => Opcode::UQXTNT_ZZ_H, + 8635 => Opcode::UQXTNT_ZZ_S, + 8636 => Opcode::UQXTNv16i8, + 8637 => Opcode::UQXTNv1i16, + 8638 => Opcode::UQXTNv1i32, + 8639 => Opcode::UQXTNv1i8, + 8640 => Opcode::UQXTNv2i32, + 8641 => Opcode::UQXTNv4i16, + 8642 => Opcode::UQXTNv4i32, + 8643 => Opcode::UQXTNv8i16, + 8644 => Opcode::UQXTNv8i8, + 8645 => Opcode::URECPE_ZPmZ_S, + 8646 => Opcode::URECPE_ZPzZ_S, + 8647 => Opcode::URECPEv2i32, + 8648 => Opcode::URECPEv4i32, + 8649 => Opcode::URHADD_ZPmZ_B, + 8650 => Opcode::URHADD_ZPmZ_D, + 8651 => Opcode::URHADD_ZPmZ_H, + 8652 => Opcode::URHADD_ZPmZ_S, + 8653 => Opcode::URHADDv16i8, + 8654 => Opcode::URHADDv2i32, + 8655 => Opcode::URHADDv4i16, + 8656 => Opcode::URHADDv4i32, + 8657 => Opcode::URHADDv8i16, + 8658 => Opcode::URHADDv8i8, + 8659 => Opcode::URSHLR_ZPmZ_B, + 8660 => Opcode::URSHLR_ZPmZ_D, + 8661 => Opcode::URSHLR_ZPmZ_H, + 8662 => Opcode::URSHLR_ZPmZ_S, + 8663 => Opcode::URSHL_VG2_2Z2Z_B, + 8664 => Opcode::URSHL_VG2_2Z2Z_D, + 8665 => Opcode::URSHL_VG2_2Z2Z_H, + 8666 => Opcode::URSHL_VG2_2Z2Z_S, + 8667 => Opcode::URSHL_VG2_2ZZ_B, + 8668 => Opcode::URSHL_VG2_2ZZ_D, + 8669 => Opcode::URSHL_VG2_2ZZ_H, + 8670 => Opcode::URSHL_VG2_2ZZ_S, + 8671 => Opcode::URSHL_VG4_4Z4Z_B, + 8672 => Opcode::URSHL_VG4_4Z4Z_D, + 8673 => Opcode::URSHL_VG4_4Z4Z_H, + 8674 => Opcode::URSHL_VG4_4Z4Z_S, + 8675 => Opcode::URSHL_VG4_4ZZ_B, + 8676 => Opcode::URSHL_VG4_4ZZ_D, + 8677 => Opcode::URSHL_VG4_4ZZ_H, + 8678 => Opcode::URSHL_VG4_4ZZ_S, + 8679 => Opcode::URSHL_ZPmZ_B, + 8680 => Opcode::URSHL_ZPmZ_D, + 8681 => Opcode::URSHL_ZPmZ_H, + 8682 => Opcode::URSHL_ZPmZ_S, + 8683 => Opcode::URSHLv16i8, + 8684 => Opcode::URSHLv1i64, + 8685 => Opcode::URSHLv2i32, + 8686 => Opcode::URSHLv2i64, + 8687 => Opcode::URSHLv4i16, + 8688 => Opcode::URSHLv4i32, + 8689 => Opcode::URSHLv8i16, + 8690 => Opcode::URSHLv8i8, + 8691 => Opcode::URSHR_ZPmI_B, + 8692 => Opcode::URSHR_ZPmI_D, + 8693 => Opcode::URSHR_ZPmI_H, + 8694 => Opcode::URSHR_ZPmI_S, + 8695 => Opcode::URSHRd, + 8696 => Opcode::URSHRv16i8_shift, + 8697 => Opcode::URSHRv2i32_shift, + 8698 => Opcode::URSHRv2i64_shift, + 8699 => Opcode::URSHRv4i16_shift, + 8700 => Opcode::URSHRv4i32_shift, + 8701 => Opcode::URSHRv8i16_shift, + 8702 => Opcode::URSHRv8i8_shift, + 8703 => Opcode::URSQRTE_ZPmZ_S, + 8704 => Opcode::URSQRTE_ZPzZ_S, + 8705 => Opcode::URSQRTEv2i32, + 8706 => Opcode::URSQRTEv4i32, + 8707 => Opcode::URSRA_ZZI_B, + 8708 => Opcode::URSRA_ZZI_D, + 8709 => Opcode::URSRA_ZZI_H, + 8710 => Opcode::URSRA_ZZI_S, + 8711 => Opcode::URSRAd, + 8712 => Opcode::URSRAv16i8_shift, + 8713 => Opcode::URSRAv2i32_shift, + 8714 => Opcode::URSRAv2i64_shift, + 8715 => Opcode::URSRAv4i16_shift, + 8716 => Opcode::URSRAv4i32_shift, + 8717 => Opcode::URSRAv8i16_shift, + 8718 => Opcode::URSRAv8i8_shift, + 8719 => Opcode::USDOT_VG2_M2Z2Z_BToS, + 8720 => Opcode::USDOT_VG2_M2ZZI_BToS, + 8721 => Opcode::USDOT_VG2_M2ZZ_BToS, + 8722 => Opcode::USDOT_VG4_M4Z4Z_BToS, + 8723 => Opcode::USDOT_VG4_M4ZZI_BToS, + 8724 => Opcode::USDOT_VG4_M4ZZ_BToS, + 8725 => Opcode::USDOT_ZZZ, + 8726 => Opcode::USDOT_ZZZI, + 8727 => Opcode::USDOTlanev16i8, + 8728 => Opcode::USDOTlanev8i8, + 8729 => Opcode::USDOTv16i8, + 8730 => Opcode::USDOTv8i8, + 8731 => Opcode::USHLLB_ZZI_D, + 8732 => Opcode::USHLLB_ZZI_H, + 8733 => Opcode::USHLLB_ZZI_S, + 8734 => Opcode::USHLLT_ZZI_D, + 8735 => Opcode::USHLLT_ZZI_H, + 8736 => Opcode::USHLLT_ZZI_S, + 8737 => Opcode::USHLLv16i8_shift, + 8738 => Opcode::USHLLv2i32_shift, + 8739 => Opcode::USHLLv4i16_shift, + 8740 => Opcode::USHLLv4i32_shift, + 8741 => Opcode::USHLLv8i16_shift, + 8742 => Opcode::USHLLv8i8_shift, + 8743 => Opcode::USHLv16i8, + 8744 => Opcode::USHLv1i64, + 8745 => Opcode::USHLv2i32, + 8746 => Opcode::USHLv2i64, + 8747 => Opcode::USHLv4i16, + 8748 => Opcode::USHLv4i32, + 8749 => Opcode::USHLv8i16, + 8750 => Opcode::USHLv8i8, + 8751 => Opcode::USHRd, + 8752 => Opcode::USHRv16i8_shift, + 8753 => Opcode::USHRv2i32_shift, + 8754 => Opcode::USHRv2i64_shift, + 8755 => Opcode::USHRv4i16_shift, + 8756 => Opcode::USHRv4i32_shift, + 8757 => Opcode::USHRv8i16_shift, + 8758 => Opcode::USHRv8i8_shift, + 8759 => Opcode::USMLALL_MZZI_BtoS, + 8760 => Opcode::USMLALL_MZZ_BtoS, + 8761 => Opcode::USMLALL_VG2_M2Z2Z_BtoS, + 8762 => Opcode::USMLALL_VG2_M2ZZI_BtoS, + 8763 => Opcode::USMLALL_VG2_M2ZZ_BtoS, + 8764 => Opcode::USMLALL_VG4_M4Z4Z_BtoS, + 8765 => Opcode::USMLALL_VG4_M4ZZI_BtoS, + 8766 => Opcode::USMLALL_VG4_M4ZZ_BtoS, + 8767 => Opcode::USMMLA, + 8768 => Opcode::USMMLA_ZZZ, + 8769 => Opcode::USMOP4A_M2Z2Z_BToS, + 8770 => Opcode::USMOP4A_M2Z2Z_HtoD, + 8771 => Opcode::USMOP4A_M2ZZ_BToS, + 8772 => Opcode::USMOP4A_M2ZZ_HtoD, + 8773 => Opcode::USMOP4A_MZ2Z_BToS, + 8774 => Opcode::USMOP4A_MZ2Z_HtoD, + 8775 => Opcode::USMOP4A_MZZ_BToS, + 8776 => Opcode::USMOP4A_MZZ_HtoD, + 8777 => Opcode::USMOP4S_M2Z2Z_BToS, + 8778 => Opcode::USMOP4S_M2Z2Z_HtoD, + 8779 => Opcode::USMOP4S_M2ZZ_BToS, + 8780 => Opcode::USMOP4S_M2ZZ_HtoD, + 8781 => Opcode::USMOP4S_MZ2Z_BToS, + 8782 => Opcode::USMOP4S_MZ2Z_HtoD, + 8783 => Opcode::USMOP4S_MZZ_BToS, + 8784 => Opcode::USMOP4S_MZZ_HtoD, + 8785 => Opcode::USMOPA_MPPZZ_D, + 8786 => Opcode::USMOPA_MPPZZ_S, + 8787 => Opcode::USMOPS_MPPZZ_D, + 8788 => Opcode::USMOPS_MPPZZ_S, + 8789 => Opcode::USQADD_ZPmZ_B, + 8790 => Opcode::USQADD_ZPmZ_D, + 8791 => Opcode::USQADD_ZPmZ_H, + 8792 => Opcode::USQADD_ZPmZ_S, + 8793 => Opcode::USQADDv16i8, + 8794 => Opcode::USQADDv1i16, + 8795 => Opcode::USQADDv1i32, + 8796 => Opcode::USQADDv1i64, + 8797 => Opcode::USQADDv1i8, + 8798 => Opcode::USQADDv2i32, + 8799 => Opcode::USQADDv2i64, + 8800 => Opcode::USQADDv4i16, + 8801 => Opcode::USQADDv4i32, + 8802 => Opcode::USQADDv8i16, + 8803 => Opcode::USQADDv8i8, + 8804 => Opcode::USRA_ZZI_B, + 8805 => Opcode::USRA_ZZI_D, + 8806 => Opcode::USRA_ZZI_H, + 8807 => Opcode::USRA_ZZI_S, + 8808 => Opcode::USRAd, + 8809 => Opcode::USRAv16i8_shift, + 8810 => Opcode::USRAv2i32_shift, + 8811 => Opcode::USRAv2i64_shift, + 8812 => Opcode::USRAv4i16_shift, + 8813 => Opcode::USRAv4i32_shift, + 8814 => Opcode::USRAv8i16_shift, + 8815 => Opcode::USRAv8i8_shift, + 8816 => Opcode::USTMOPA_M2ZZZI_BtoS, + 8817 => Opcode::USUBLB_ZZZ_D, + 8818 => Opcode::USUBLB_ZZZ_H, + 8819 => Opcode::USUBLB_ZZZ_S, + 8820 => Opcode::USUBLT_ZZZ_D, + 8821 => Opcode::USUBLT_ZZZ_H, + 8822 => Opcode::USUBLT_ZZZ_S, + 8823 => Opcode::USUBLv16i8_v8i16, + 8824 => Opcode::USUBLv2i32_v2i64, + 8825 => Opcode::USUBLv4i16_v4i32, + 8826 => Opcode::USUBLv4i32_v2i64, + 8827 => Opcode::USUBLv8i16_v4i32, + 8828 => Opcode::USUBLv8i8_v8i16, + 8829 => Opcode::USUBWB_ZZZ_D, + 8830 => Opcode::USUBWB_ZZZ_H, + 8831 => Opcode::USUBWB_ZZZ_S, + 8832 => Opcode::USUBWT_ZZZ_D, + 8833 => Opcode::USUBWT_ZZZ_H, + 8834 => Opcode::USUBWT_ZZZ_S, + 8835 => Opcode::USUBWv16i8_v8i16, + 8836 => Opcode::USUBWv2i32_v2i64, + 8837 => Opcode::USUBWv4i16_v4i32, + 8838 => Opcode::USUBWv4i32_v2i64, + 8839 => Opcode::USUBWv8i16_v4i32, + 8840 => Opcode::USUBWv8i8_v8i16, + 8841 => Opcode::USVDOT_VG4_M4ZZI_BToS, + 8842 => Opcode::UTMOPA_M2ZZZI_BtoS, + 8843 => Opcode::UTMOPA_M2ZZZI_HtoS, + 8844 => Opcode::UUNPKHI_ZZ_D, + 8845 => Opcode::UUNPKHI_ZZ_H, + 8846 => Opcode::UUNPKHI_ZZ_S, + 8847 => Opcode::UUNPKLO_ZZ_D, + 8848 => Opcode::UUNPKLO_ZZ_H, + 8849 => Opcode::UUNPKLO_ZZ_S, + 8850 => Opcode::UUNPK_VG2_2ZZ_D, + 8851 => Opcode::UUNPK_VG2_2ZZ_H, + 8852 => Opcode::UUNPK_VG2_2ZZ_S, + 8853 => Opcode::UUNPK_VG4_4Z2Z_D, + 8854 => Opcode::UUNPK_VG4_4Z2Z_H, + 8855 => Opcode::UUNPK_VG4_4Z2Z_S, + 8856 => Opcode::UVDOT_VG2_M2ZZI_HtoS, + 8857 => Opcode::UVDOT_VG4_M4ZZI_BtoS, + 8858 => Opcode::UVDOT_VG4_M4ZZI_HtoD, + 8859 => Opcode::UXTB_ZPmZ_D, + 8860 => Opcode::UXTB_ZPmZ_H, + 8861 => Opcode::UXTB_ZPmZ_S, + 8862 => Opcode::UXTB_ZPzZ_D, + 8863 => Opcode::UXTB_ZPzZ_H, + 8864 => Opcode::UXTB_ZPzZ_S, + 8865 => Opcode::UXTH_ZPmZ_D, + 8866 => Opcode::UXTH_ZPmZ_S, + 8867 => Opcode::UXTH_ZPzZ_D, + 8868 => Opcode::UXTH_ZPzZ_S, + 8869 => Opcode::UXTW_ZPmZ_D, + 8870 => Opcode::UXTW_ZPzZ_D, + 8871 => Opcode::UZP1_PPP_B, + 8872 => Opcode::UZP1_PPP_D, + 8873 => Opcode::UZP1_PPP_H, + 8874 => Opcode::UZP1_PPP_S, + 8875 => Opcode::UZP1_ZZZ_B, + 8876 => Opcode::UZP1_ZZZ_D, + 8877 => Opcode::UZP1_ZZZ_H, + 8878 => Opcode::UZP1_ZZZ_Q, + 8879 => Opcode::UZP1_ZZZ_S, + 8880 => Opcode::UZP1v16i8, + 8881 => Opcode::UZP1v2i32, + 8882 => Opcode::UZP1v2i64, + 8883 => Opcode::UZP1v4i16, + 8884 => Opcode::UZP1v4i32, + 8885 => Opcode::UZP1v8i16, + 8886 => Opcode::UZP1v8i8, + 8887 => Opcode::UZP2_PPP_B, + 8888 => Opcode::UZP2_PPP_D, + 8889 => Opcode::UZP2_PPP_H, + 8890 => Opcode::UZP2_PPP_S, + 8891 => Opcode::UZP2_ZZZ_B, + 8892 => Opcode::UZP2_ZZZ_D, + 8893 => Opcode::UZP2_ZZZ_H, + 8894 => Opcode::UZP2_ZZZ_Q, + 8895 => Opcode::UZP2_ZZZ_S, + 8896 => Opcode::UZP2v16i8, + 8897 => Opcode::UZP2v2i32, + 8898 => Opcode::UZP2v2i64, + 8899 => Opcode::UZP2v4i16, + 8900 => Opcode::UZP2v4i32, + 8901 => Opcode::UZP2v8i16, + 8902 => Opcode::UZP2v8i8, + 8903 => Opcode::UZPQ1_ZZZ_B, + 8904 => Opcode::UZPQ1_ZZZ_D, + 8905 => Opcode::UZPQ1_ZZZ_H, + 8906 => Opcode::UZPQ1_ZZZ_S, + 8907 => Opcode::UZPQ2_ZZZ_B, + 8908 => Opcode::UZPQ2_ZZZ_D, + 8909 => Opcode::UZPQ2_ZZZ_H, + 8910 => Opcode::UZPQ2_ZZZ_S, + 8911 => Opcode::UZP_VG2_2ZZZ_B, + 8912 => Opcode::UZP_VG2_2ZZZ_D, + 8913 => Opcode::UZP_VG2_2ZZZ_H, + 8914 => Opcode::UZP_VG2_2ZZZ_Q, + 8915 => Opcode::UZP_VG2_2ZZZ_S, + 8916 => Opcode::UZP_VG4_4Z4Z_B, + 8917 => Opcode::UZP_VG4_4Z4Z_D, + 8918 => Opcode::UZP_VG4_4Z4Z_H, + 8919 => Opcode::UZP_VG4_4Z4Z_Q, + 8920 => Opcode::UZP_VG4_4Z4Z_S, + 8921 => Opcode::WFET, + 8922 => Opcode::WFIT, + 8923 => Opcode::WHILEGE_2PXX_B, + 8924 => Opcode::WHILEGE_2PXX_D, + 8925 => Opcode::WHILEGE_2PXX_H, + 8926 => Opcode::WHILEGE_2PXX_S, + 8927 => Opcode::WHILEGE_CXX_B, + 8928 => Opcode::WHILEGE_CXX_D, + 8929 => Opcode::WHILEGE_CXX_H, + 8930 => Opcode::WHILEGE_CXX_S, + 8931 => Opcode::WHILEGE_PWW_B, + 8932 => Opcode::WHILEGE_PWW_D, + 8933 => Opcode::WHILEGE_PWW_H, + 8934 => Opcode::WHILEGE_PWW_S, + 8935 => Opcode::WHILEGE_PXX_B, + 8936 => Opcode::WHILEGE_PXX_D, + 8937 => Opcode::WHILEGE_PXX_H, + 8938 => Opcode::WHILEGE_PXX_S, + 8939 => Opcode::WHILEGT_2PXX_B, + 8940 => Opcode::WHILEGT_2PXX_D, + 8941 => Opcode::WHILEGT_2PXX_H, + 8942 => Opcode::WHILEGT_2PXX_S, + 8943 => Opcode::WHILEGT_CXX_B, + 8944 => Opcode::WHILEGT_CXX_D, + 8945 => Opcode::WHILEGT_CXX_H, + 8946 => Opcode::WHILEGT_CXX_S, + 8947 => Opcode::WHILEGT_PWW_B, + 8948 => Opcode::WHILEGT_PWW_D, + 8949 => Opcode::WHILEGT_PWW_H, + 8950 => Opcode::WHILEGT_PWW_S, + 8951 => Opcode::WHILEGT_PXX_B, + 8952 => Opcode::WHILEGT_PXX_D, + 8953 => Opcode::WHILEGT_PXX_H, + 8954 => Opcode::WHILEGT_PXX_S, + 8955 => Opcode::WHILEHI_2PXX_B, + 8956 => Opcode::WHILEHI_2PXX_D, + 8957 => Opcode::WHILEHI_2PXX_H, + 8958 => Opcode::WHILEHI_2PXX_S, + 8959 => Opcode::WHILEHI_CXX_B, + 8960 => Opcode::WHILEHI_CXX_D, + 8961 => Opcode::WHILEHI_CXX_H, + 8962 => Opcode::WHILEHI_CXX_S, + 8963 => Opcode::WHILEHI_PWW_B, + 8964 => Opcode::WHILEHI_PWW_D, + 8965 => Opcode::WHILEHI_PWW_H, + 8966 => Opcode::WHILEHI_PWW_S, + 8967 => Opcode::WHILEHI_PXX_B, + 8968 => Opcode::WHILEHI_PXX_D, + 8969 => Opcode::WHILEHI_PXX_H, + 8970 => Opcode::WHILEHI_PXX_S, + 8971 => Opcode::WHILEHS_2PXX_B, + 8972 => Opcode::WHILEHS_2PXX_D, + 8973 => Opcode::WHILEHS_2PXX_H, + 8974 => Opcode::WHILEHS_2PXX_S, + 8975 => Opcode::WHILEHS_CXX_B, + 8976 => Opcode::WHILEHS_CXX_D, + 8977 => Opcode::WHILEHS_CXX_H, + 8978 => Opcode::WHILEHS_CXX_S, + 8979 => Opcode::WHILEHS_PWW_B, + 8980 => Opcode::WHILEHS_PWW_D, + 8981 => Opcode::WHILEHS_PWW_H, + 8982 => Opcode::WHILEHS_PWW_S, + 8983 => Opcode::WHILEHS_PXX_B, + 8984 => Opcode::WHILEHS_PXX_D, + 8985 => Opcode::WHILEHS_PXX_H, + 8986 => Opcode::WHILEHS_PXX_S, + 8987 => Opcode::WHILELE_2PXX_B, + 8988 => Opcode::WHILELE_2PXX_D, + 8989 => Opcode::WHILELE_2PXX_H, + 8990 => Opcode::WHILELE_2PXX_S, + 8991 => Opcode::WHILELE_CXX_B, + 8992 => Opcode::WHILELE_CXX_D, + 8993 => Opcode::WHILELE_CXX_H, + 8994 => Opcode::WHILELE_CXX_S, + 8995 => Opcode::WHILELE_PWW_B, + 8996 => Opcode::WHILELE_PWW_D, + 8997 => Opcode::WHILELE_PWW_H, + 8998 => Opcode::WHILELE_PWW_S, + 8999 => Opcode::WHILELE_PXX_B, + 9000 => Opcode::WHILELE_PXX_D, + 9001 => Opcode::WHILELE_PXX_H, + 9002 => Opcode::WHILELE_PXX_S, + 9003 => Opcode::WHILELO_2PXX_B, + 9004 => Opcode::WHILELO_2PXX_D, + 9005 => Opcode::WHILELO_2PXX_H, + 9006 => Opcode::WHILELO_2PXX_S, + 9007 => Opcode::WHILELO_CXX_B, + 9008 => Opcode::WHILELO_CXX_D, + 9009 => Opcode::WHILELO_CXX_H, + 9010 => Opcode::WHILELO_CXX_S, + 9011 => Opcode::WHILELO_PWW_B, + 9012 => Opcode::WHILELO_PWW_D, + 9013 => Opcode::WHILELO_PWW_H, + 9014 => Opcode::WHILELO_PWW_S, + 9015 => Opcode::WHILELO_PXX_B, + 9016 => Opcode::WHILELO_PXX_D, + 9017 => Opcode::WHILELO_PXX_H, + 9018 => Opcode::WHILELO_PXX_S, + 9019 => Opcode::WHILELS_2PXX_B, + 9020 => Opcode::WHILELS_2PXX_D, + 9021 => Opcode::WHILELS_2PXX_H, + 9022 => Opcode::WHILELS_2PXX_S, + 9023 => Opcode::WHILELS_CXX_B, + 9024 => Opcode::WHILELS_CXX_D, + 9025 => Opcode::WHILELS_CXX_H, + 9026 => Opcode::WHILELS_CXX_S, + 9027 => Opcode::WHILELS_PWW_B, + 9028 => Opcode::WHILELS_PWW_D, + 9029 => Opcode::WHILELS_PWW_H, + 9030 => Opcode::WHILELS_PWW_S, + 9031 => Opcode::WHILELS_PXX_B, + 9032 => Opcode::WHILELS_PXX_D, + 9033 => Opcode::WHILELS_PXX_H, + 9034 => Opcode::WHILELS_PXX_S, + 9035 => Opcode::WHILELT_2PXX_B, + 9036 => Opcode::WHILELT_2PXX_D, + 9037 => Opcode::WHILELT_2PXX_H, + 9038 => Opcode::WHILELT_2PXX_S, + 9039 => Opcode::WHILELT_CXX_B, + 9040 => Opcode::WHILELT_CXX_D, + 9041 => Opcode::WHILELT_CXX_H, + 9042 => Opcode::WHILELT_CXX_S, + 9043 => Opcode::WHILELT_PWW_B, + 9044 => Opcode::WHILELT_PWW_D, + 9045 => Opcode::WHILELT_PWW_H, + 9046 => Opcode::WHILELT_PWW_S, + 9047 => Opcode::WHILELT_PXX_B, + 9048 => Opcode::WHILELT_PXX_D, + 9049 => Opcode::WHILELT_PXX_H, + 9050 => Opcode::WHILELT_PXX_S, + 9051 => Opcode::WHILERW_PXX_B, + 9052 => Opcode::WHILERW_PXX_D, + 9053 => Opcode::WHILERW_PXX_H, + 9054 => Opcode::WHILERW_PXX_S, + 9055 => Opcode::WHILEWR_PXX_B, + 9056 => Opcode::WHILEWR_PXX_D, + 9057 => Opcode::WHILEWR_PXX_H, + 9058 => Opcode::WHILEWR_PXX_S, + 9059 => Opcode::WRFFR, + 9060 => Opcode::XAFLAG, + 9061 => Opcode::XAR, + 9062 => Opcode::XAR_ZZZI_B, + 9063 => Opcode::XAR_ZZZI_D, + 9064 => Opcode::XAR_ZZZI_H, + 9065 => Opcode::XAR_ZZZI_S, + 9066 => Opcode::XPACD, + 9067 => Opcode::XPACI, + 9068 => Opcode::XPACLRI, + 9069 => Opcode::XTNv16i8, + 9070 => Opcode::XTNv2i32, + 9071 => Opcode::XTNv4i16, + 9072 => Opcode::XTNv4i32, + 9073 => Opcode::XTNv8i16, + 9074 => Opcode::XTNv8i8, + 9075 => Opcode::ZERO_M, + 9076 => Opcode::ZERO_MXI_2Z, + 9077 => Opcode::ZERO_MXI_4Z, + 9078 => Opcode::ZERO_MXI_VG2_2Z, + 9079 => Opcode::ZERO_MXI_VG2_4Z, + 9080 => Opcode::ZERO_MXI_VG2_Z, + 9081 => Opcode::ZERO_MXI_VG4_2Z, + 9082 => Opcode::ZERO_MXI_VG4_4Z, + 9083 => Opcode::ZERO_MXI_VG4_Z, + 9084 => Opcode::ZERO_T, + 9085 => Opcode::ZIP1_PPP_B, + 9086 => Opcode::ZIP1_PPP_D, + 9087 => Opcode::ZIP1_PPP_H, + 9088 => Opcode::ZIP1_PPP_S, + 9089 => Opcode::ZIP1_ZZZ_B, + 9090 => Opcode::ZIP1_ZZZ_D, + 9091 => Opcode::ZIP1_ZZZ_H, + 9092 => Opcode::ZIP1_ZZZ_Q, + 9093 => Opcode::ZIP1_ZZZ_S, + 9094 => Opcode::ZIP1v16i8, + 9095 => Opcode::ZIP1v2i32, + 9096 => Opcode::ZIP1v2i64, + 9097 => Opcode::ZIP1v4i16, + 9098 => Opcode::ZIP1v4i32, + 9099 => Opcode::ZIP1v8i16, + 9100 => Opcode::ZIP1v8i8, + 9101 => Opcode::ZIP2_PPP_B, + 9102 => Opcode::ZIP2_PPP_D, + 9103 => Opcode::ZIP2_PPP_H, + 9104 => Opcode::ZIP2_PPP_S, + 9105 => Opcode::ZIP2_ZZZ_B, + 9106 => Opcode::ZIP2_ZZZ_D, + 9107 => Opcode::ZIP2_ZZZ_H, + 9108 => Opcode::ZIP2_ZZZ_Q, + 9109 => Opcode::ZIP2_ZZZ_S, + 9110 => Opcode::ZIP2v16i8, + 9111 => Opcode::ZIP2v2i32, + 9112 => Opcode::ZIP2v2i64, + 9113 => Opcode::ZIP2v4i16, + 9114 => Opcode::ZIP2v4i32, + 9115 => Opcode::ZIP2v8i16, + 9116 => Opcode::ZIP2v8i8, + 9117 => Opcode::ZIPQ1_ZZZ_B, + 9118 => Opcode::ZIPQ1_ZZZ_D, + 9119 => Opcode::ZIPQ1_ZZZ_H, + 9120 => Opcode::ZIPQ1_ZZZ_S, + 9121 => Opcode::ZIPQ2_ZZZ_B, + 9122 => Opcode::ZIPQ2_ZZZ_D, + 9123 => Opcode::ZIPQ2_ZZZ_H, + 9124 => Opcode::ZIPQ2_ZZZ_S, + 9125 => Opcode::ZIP_VG2_2ZZZ_B, + 9126 => Opcode::ZIP_VG2_2ZZZ_D, + 9127 => Opcode::ZIP_VG2_2ZZZ_H, + 9128 => Opcode::ZIP_VG2_2ZZZ_Q, + 9129 => Opcode::ZIP_VG2_2ZZZ_S, + 9130 => Opcode::ZIP_VG4_4Z4Z_B, + 9131 => Opcode::ZIP_VG4_4Z4Z_D, + 9132 => Opcode::ZIP_VG4_4Z4Z_H, + 9133 => Opcode::ZIP_VG4_4Z4Z_Q, + 9134 => Opcode::ZIP_VG4_4Z4Z_S, + 9135 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands.rs new file mode 100644 index 0000000..afec799 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand (e.g. `X0`) + Reg(Register), + + /// A PC-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_aarch64_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_aarch64_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_aarch64_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_aarch64_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/immediate.rs new file mode 100644 index 0000000..f21c0b7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// mov x0, #8; +/// | +/// +---> Immediate(8) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/memory.rs new file mode 100644 index 0000000..559a8cf --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/memory.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::{assembly::aarch64::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// ```text +/// ldr x0, [x1, x2, lsl #3] +/// | | | +/// +------------+ | +--------+ +/// | | | +/// v v v +/// Base Reg Offset Shift +/// +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Wraps a memory offset as an integer offset or as a register offset +#[derive(Debug)] +pub enum Offset { + /// Register offset + Reg(Reg), + /// Integer offset + Displacement(i64), +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Shift { + Unknown, + Lsl, + Uxtx, + Uxtw, + Sxtx, + Sxtw, +} + +impl From for Shift { + fn from(value: i32) -> Self { + match value { + 0 => Shift::Unknown, + 1 => Shift::Lsl, + 2 => Shift::Uxtx, + 3 => Shift::Uxtw, + 4 => Shift::Sxtx, + 5 => Shift::Sxtw, + _ => Shift::Unknown, + } + } +} + +/// This structure holds shift info (type + value) +#[derive(Debug)] +pub struct ShiftInfo { + pub shift_type: Shift, + pub value: i8, +} + +impl ShiftInfo { + pub fn new(shift: Shift, value: i8) -> Self { + Self { + shift_type: shift, + value, + } + } +} + +impl Memory { + /// The base register. + /// + /// For `str x3, [x8, #8]` it would return `x8` + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The addressing offset. + /// + /// It can be either: + /// - A register (e.g. `ldr x0, [x1, x3]`) + /// - An offset (e.g. `ldr x0, [x1, #8]`) + pub fn offset(&self) -> Option { + let ffi_offset = self.ptr.offset(); + match ffi_offset.enum_type { + 1 => Some(Offset::Reg(Reg::from(ffi_offset.value))), + 2 => Some(Offset::Displacement(ffi_offset.value as i64)), + _ => None, + } + } + + /// Shift information. + /// + /// For instance, for `ldr x1, [x2, x3, lsl #3]` it would + /// return a [`Shift::Lsl`] with a [`ShiftInfo::value`] set to `3` + pub fn shift(&self) -> Option { + let ffi_shift = self.ptr.shift(); + if ffi_shift.value == 0 { + return None; + } + Some(ShiftInfo::new( + Shift::from(ffi_shift.enum_type), + ffi_shift.value, + )) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/pc_relative.rs new file mode 100644 index 0000000..c48e31e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/pc_relative.rs @@ -0,0 +1,31 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a PC-relative operand. +/// +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `rip/eip` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/register.rs new file mode 100644 index 0000000..26a6d7d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/operands/register.rs @@ -0,0 +1,51 @@ +use lief_ffi as ffi; + +use crate::assembly::aarch64::registers::{Reg, SysReg}; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// ```text +/// mrs x0, TPIDR_EL0 +/// | | +/// +------+ +-------+ +/// | | +/// v v +/// REG SYSREG +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_aarch64_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +#[derive(Debug)] +pub enum Value { + Reg(Reg), + SysReg(SysReg), +} + +impl Register { + /// The effective register as either: a [`Reg`] or a [`SysReg`] + pub fn value(&self) -> Option { + let ffi_value = self.ptr.value(); + match ffi_value.enum_type { + 1 => Some(Value::SysReg(SysReg::from(ffi_value.reg))), + 2 => Some(Value::Reg(Reg::from(ffi_value.reg))), + _ => None, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/registers.rs new file mode 100644 index 0000000..4b6b998 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/aarch64/registers.rs @@ -0,0 +1,5079 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + FFR, + FP, + FPCR, + FPMR, + FPSR, + LR, + NZCV, + SP, + VG, + WSP, + WSP_HI, + WZR, + WZR_HI, + XZR, + ZA, + B0, + B1, + B2, + B3, + B4, + B5, + B6, + B7, + B8, + B9, + B10, + B11, + B12, + B13, + B14, + B15, + B16, + B17, + B18, + B19, + B20, + B21, + B22, + B23, + B24, + B25, + B26, + B27, + B28, + B29, + B30, + B31, + D0, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + D9, + D10, + D11, + D12, + D13, + D14, + D15, + D16, + D17, + D18, + D19, + D20, + D21, + D22, + D23, + D24, + D25, + D26, + D27, + D28, + D29, + D30, + D31, + H0, + H1, + H2, + H3, + H4, + H5, + H6, + H7, + H8, + H9, + H10, + H11, + H12, + H13, + H14, + H15, + H16, + H17, + H18, + H19, + H20, + H21, + H22, + H23, + H24, + H25, + H26, + H27, + H28, + H29, + H30, + H31, + P0, + P1, + P2, + P3, + P4, + P5, + P6, + P7, + P8, + P9, + P10, + P11, + P12, + P13, + P14, + P15, + PN0, + PN1, + PN2, + PN3, + PN4, + PN5, + PN6, + PN7, + PN8, + PN9, + PN10, + PN11, + PN12, + PN13, + PN14, + PN15, + Q0, + Q1, + Q2, + Q3, + Q4, + Q5, + Q6, + Q7, + Q8, + Q9, + Q10, + Q11, + Q12, + Q13, + Q14, + Q15, + Q16, + Q17, + Q18, + Q19, + Q20, + Q21, + Q22, + Q23, + Q24, + Q25, + Q26, + Q27, + Q28, + Q29, + Q30, + Q31, + S0, + S1, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + S12, + S13, + S14, + S15, + S16, + S17, + S18, + S19, + S20, + S21, + S22, + S23, + S24, + S25, + S26, + S27, + S28, + S29, + S30, + S31, + W0, + W1, + W2, + W3, + W4, + W5, + W6, + W7, + W8, + W9, + W10, + W11, + W12, + W13, + W14, + W15, + W16, + W17, + W18, + W19, + W20, + W21, + W22, + W23, + W24, + W25, + W26, + W27, + W28, + W29, + W30, + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + Z0, + Z1, + Z2, + Z3, + Z4, + Z5, + Z6, + Z7, + Z8, + Z9, + Z10, + Z11, + Z12, + Z13, + Z14, + Z15, + Z16, + Z17, + Z18, + Z19, + Z20, + Z21, + Z22, + Z23, + Z24, + Z25, + Z26, + Z27, + Z28, + Z29, + Z30, + Z31, + ZAB0, + ZAD0, + ZAD1, + ZAD2, + ZAD3, + ZAD4, + ZAD5, + ZAD6, + ZAD7, + ZAH0, + ZAH1, + ZAQ0, + ZAQ1, + ZAQ2, + ZAQ3, + ZAQ4, + ZAQ5, + ZAQ6, + ZAQ7, + ZAQ8, + ZAQ9, + ZAQ10, + ZAQ11, + ZAQ12, + ZAQ13, + ZAQ14, + ZAQ15, + ZAS0, + ZAS1, + ZAS2, + ZAS3, + ZT0, + B0_HI, + B1_HI, + B2_HI, + B3_HI, + B4_HI, + B5_HI, + B6_HI, + B7_HI, + B8_HI, + B9_HI, + B10_HI, + B11_HI, + B12_HI, + B13_HI, + B14_HI, + B15_HI, + B16_HI, + B17_HI, + B18_HI, + B19_HI, + B20_HI, + B21_HI, + B22_HI, + B23_HI, + B24_HI, + B25_HI, + B26_HI, + B27_HI, + B28_HI, + B29_HI, + B30_HI, + B31_HI, + D0_HI, + D1_HI, + D2_HI, + D3_HI, + D4_HI, + D5_HI, + D6_HI, + D7_HI, + D8_HI, + D9_HI, + D10_HI, + D11_HI, + D12_HI, + D13_HI, + D14_HI, + D15_HI, + D16_HI, + D17_HI, + D18_HI, + D19_HI, + D20_HI, + D21_HI, + D22_HI, + D23_HI, + D24_HI, + D25_HI, + D26_HI, + D27_HI, + D28_HI, + D29_HI, + D30_HI, + D31_HI, + H0_HI, + H1_HI, + H2_HI, + H3_HI, + H4_HI, + H5_HI, + H6_HI, + H7_HI, + H8_HI, + H9_HI, + H10_HI, + H11_HI, + H12_HI, + H13_HI, + H14_HI, + H15_HI, + H16_HI, + H17_HI, + H18_HI, + H19_HI, + H20_HI, + H21_HI, + H22_HI, + H23_HI, + H24_HI, + H25_HI, + H26_HI, + H27_HI, + H28_HI, + H29_HI, + H30_HI, + H31_HI, + Q0_HI, + Q1_HI, + Q2_HI, + Q3_HI, + Q4_HI, + Q5_HI, + Q6_HI, + Q7_HI, + Q8_HI, + Q9_HI, + Q10_HI, + Q11_HI, + Q12_HI, + Q13_HI, + Q14_HI, + Q15_HI, + Q16_HI, + Q17_HI, + Q18_HI, + Q19_HI, + Q20_HI, + Q21_HI, + Q22_HI, + Q23_HI, + Q24_HI, + Q25_HI, + Q26_HI, + Q27_HI, + Q28_HI, + Q29_HI, + Q30_HI, + Q31_HI, + S0_HI, + S1_HI, + S2_HI, + S3_HI, + S4_HI, + S5_HI, + S6_HI, + S7_HI, + S8_HI, + S9_HI, + S10_HI, + S11_HI, + S12_HI, + S13_HI, + S14_HI, + S15_HI, + S16_HI, + S17_HI, + S18_HI, + S19_HI, + S20_HI, + S21_HI, + S22_HI, + S23_HI, + S24_HI, + S25_HI, + S26_HI, + S27_HI, + S28_HI, + S29_HI, + S30_HI, + S31_HI, + W0_HI, + W1_HI, + W2_HI, + W3_HI, + W4_HI, + W5_HI, + W6_HI, + W7_HI, + W8_HI, + W9_HI, + W10_HI, + W11_HI, + W12_HI, + W13_HI, + W14_HI, + W15_HI, + W16_HI, + W17_HI, + W18_HI, + W19_HI, + W20_HI, + W21_HI, + W22_HI, + W23_HI, + W24_HI, + W25_HI, + W26_HI, + W27_HI, + W28_HI, + W29_HI, + W30_HI, + D0_D1, + D1_D2, + D2_D3, + D3_D4, + D4_D5, + D5_D6, + D6_D7, + D7_D8, + D8_D9, + D9_D10, + D10_D11, + D11_D12, + D12_D13, + D13_D14, + D14_D15, + D15_D16, + D16_D17, + D17_D18, + D18_D19, + D19_D20, + D20_D21, + D21_D22, + D22_D23, + D23_D24, + D24_D25, + D25_D26, + D26_D27, + D27_D28, + D28_D29, + D29_D30, + D30_D31, + D31_D0, + D0_D1_D2_D3, + D1_D2_D3_D4, + D2_D3_D4_D5, + D3_D4_D5_D6, + D4_D5_D6_D7, + D5_D6_D7_D8, + D6_D7_D8_D9, + D7_D8_D9_D10, + D8_D9_D10_D11, + D9_D10_D11_D12, + D10_D11_D12_D13, + D11_D12_D13_D14, + D12_D13_D14_D15, + D13_D14_D15_D16, + D14_D15_D16_D17, + D15_D16_D17_D18, + D16_D17_D18_D19, + D17_D18_D19_D20, + D18_D19_D20_D21, + D19_D20_D21_D22, + D20_D21_D22_D23, + D21_D22_D23_D24, + D22_D23_D24_D25, + D23_D24_D25_D26, + D24_D25_D26_D27, + D25_D26_D27_D28, + D26_D27_D28_D29, + D27_D28_D29_D30, + D28_D29_D30_D31, + D29_D30_D31_D0, + D30_D31_D0_D1, + D31_D0_D1_D2, + D0_D1_D2, + D1_D2_D3, + D2_D3_D4, + D3_D4_D5, + D4_D5_D6, + D5_D6_D7, + D6_D7_D8, + D7_D8_D9, + D8_D9_D10, + D9_D10_D11, + D10_D11_D12, + D11_D12_D13, + D12_D13_D14, + D13_D14_D15, + D14_D15_D16, + D15_D16_D17, + D16_D17_D18, + D17_D18_D19, + D18_D19_D20, + D19_D20_D21, + D20_D21_D22, + D21_D22_D23, + D22_D23_D24, + D23_D24_D25, + D24_D25_D26, + D25_D26_D27, + D26_D27_D28, + D27_D28_D29, + D28_D29_D30, + D29_D30_D31, + D30_D31_D0, + D31_D0_D1, + P0_P1, + P1_P2, + P2_P3, + P3_P4, + P4_P5, + P5_P6, + P6_P7, + P7_P8, + P8_P9, + P9_P10, + P10_P11, + P11_P12, + P12_P13, + P13_P14, + P14_P15, + P15_P0, + Q0_Q1, + Q1_Q2, + Q2_Q3, + Q3_Q4, + Q4_Q5, + Q5_Q6, + Q6_Q7, + Q7_Q8, + Q8_Q9, + Q9_Q10, + Q10_Q11, + Q11_Q12, + Q12_Q13, + Q13_Q14, + Q14_Q15, + Q15_Q16, + Q16_Q17, + Q17_Q18, + Q18_Q19, + Q19_Q20, + Q20_Q21, + Q21_Q22, + Q22_Q23, + Q23_Q24, + Q24_Q25, + Q25_Q26, + Q26_Q27, + Q27_Q28, + Q28_Q29, + Q29_Q30, + Q30_Q31, + Q31_Q0, + Q0_Q1_Q2_Q3, + Q1_Q2_Q3_Q4, + Q2_Q3_Q4_Q5, + Q3_Q4_Q5_Q6, + Q4_Q5_Q6_Q7, + Q5_Q6_Q7_Q8, + Q6_Q7_Q8_Q9, + Q7_Q8_Q9_Q10, + Q8_Q9_Q10_Q11, + Q9_Q10_Q11_Q12, + Q10_Q11_Q12_Q13, + Q11_Q12_Q13_Q14, + Q12_Q13_Q14_Q15, + Q13_Q14_Q15_Q16, + Q14_Q15_Q16_Q17, + Q15_Q16_Q17_Q18, + Q16_Q17_Q18_Q19, + Q17_Q18_Q19_Q20, + Q18_Q19_Q20_Q21, + Q19_Q20_Q21_Q22, + Q20_Q21_Q22_Q23, + Q21_Q22_Q23_Q24, + Q22_Q23_Q24_Q25, + Q23_Q24_Q25_Q26, + Q24_Q25_Q26_Q27, + Q25_Q26_Q27_Q28, + Q26_Q27_Q28_Q29, + Q27_Q28_Q29_Q30, + Q28_Q29_Q30_Q31, + Q29_Q30_Q31_Q0, + Q30_Q31_Q0_Q1, + Q31_Q0_Q1_Q2, + Q0_Q1_Q2, + Q1_Q2_Q3, + Q2_Q3_Q4, + Q3_Q4_Q5, + Q4_Q5_Q6, + Q5_Q6_Q7, + Q6_Q7_Q8, + Q7_Q8_Q9, + Q8_Q9_Q10, + Q9_Q10_Q11, + Q10_Q11_Q12, + Q11_Q12_Q13, + Q12_Q13_Q14, + Q13_Q14_Q15, + Q14_Q15_Q16, + Q15_Q16_Q17, + Q16_Q17_Q18, + Q17_Q18_Q19, + Q18_Q19_Q20, + Q19_Q20_Q21, + Q20_Q21_Q22, + Q21_Q22_Q23, + Q22_Q23_Q24, + Q23_Q24_Q25, + Q24_Q25_Q26, + Q25_Q26_Q27, + Q26_Q27_Q28, + Q27_Q28_Q29, + Q28_Q29_Q30, + Q29_Q30_Q31, + Q30_Q31_Q0, + Q31_Q0_Q1, + X22_X23_X24_X25_X26_X27_X28_FP, + X0_X1_X2_X3_X4_X5_X6_X7, + X2_X3_X4_X5_X6_X7_X8_X9, + X4_X5_X6_X7_X8_X9_X10_X11, + X6_X7_X8_X9_X10_X11_X12_X13, + X8_X9_X10_X11_X12_X13_X14_X15, + X10_X11_X12_X13_X14_X15_X16_X17, + X12_X13_X14_X15_X16_X17_X18_X19, + X14_X15_X16_X17_X18_X19_X20_X21, + X16_X17_X18_X19_X20_X21_X22_X23, + X18_X19_X20_X21_X22_X23_X24_X25, + X20_X21_X22_X23_X24_X25_X26_X27, + W30_WZR, + W0_W1, + W2_W3, + W4_W5, + W6_W7, + W8_W9, + W10_W11, + W12_W13, + W14_W15, + W16_W17, + W18_W19, + W20_W21, + W22_W23, + W24_W25, + W26_W27, + W28_W29, + LR_XZR, + X28_FP, + X0_X1, + X2_X3, + X4_X5, + X6_X7, + X8_X9, + X10_X11, + X12_X13, + X14_X15, + X16_X17, + X18_X19, + X20_X21, + X22_X23, + X24_X25, + X26_X27, + Z0_Z1, + Z1_Z2, + Z2_Z3, + Z3_Z4, + Z4_Z5, + Z5_Z6, + Z6_Z7, + Z7_Z8, + Z8_Z9, + Z9_Z10, + Z10_Z11, + Z11_Z12, + Z12_Z13, + Z13_Z14, + Z14_Z15, + Z15_Z16, + Z16_Z17, + Z17_Z18, + Z18_Z19, + Z19_Z20, + Z20_Z21, + Z21_Z22, + Z22_Z23, + Z23_Z24, + Z24_Z25, + Z25_Z26, + Z26_Z27, + Z27_Z28, + Z28_Z29, + Z29_Z30, + Z30_Z31, + Z31_Z0, + Z0_Z1_Z2_Z3, + Z1_Z2_Z3_Z4, + Z2_Z3_Z4_Z5, + Z3_Z4_Z5_Z6, + Z4_Z5_Z6_Z7, + Z5_Z6_Z7_Z8, + Z6_Z7_Z8_Z9, + Z7_Z8_Z9_Z10, + Z8_Z9_Z10_Z11, + Z9_Z10_Z11_Z12, + Z10_Z11_Z12_Z13, + Z11_Z12_Z13_Z14, + Z12_Z13_Z14_Z15, + Z13_Z14_Z15_Z16, + Z14_Z15_Z16_Z17, + Z15_Z16_Z17_Z18, + Z16_Z17_Z18_Z19, + Z17_Z18_Z19_Z20, + Z18_Z19_Z20_Z21, + Z19_Z20_Z21_Z22, + Z20_Z21_Z22_Z23, + Z21_Z22_Z23_Z24, + Z22_Z23_Z24_Z25, + Z23_Z24_Z25_Z26, + Z24_Z25_Z26_Z27, + Z25_Z26_Z27_Z28, + Z26_Z27_Z28_Z29, + Z27_Z28_Z29_Z30, + Z28_Z29_Z30_Z31, + Z29_Z30_Z31_Z0, + Z30_Z31_Z0_Z1, + Z31_Z0_Z1_Z2, + Z0_Z1_Z2, + Z1_Z2_Z3, + Z2_Z3_Z4, + Z3_Z4_Z5, + Z4_Z5_Z6, + Z5_Z6_Z7, + Z6_Z7_Z8, + Z7_Z8_Z9, + Z8_Z9_Z10, + Z9_Z10_Z11, + Z10_Z11_Z12, + Z11_Z12_Z13, + Z12_Z13_Z14, + Z13_Z14_Z15, + Z14_Z15_Z16, + Z15_Z16_Z17, + Z16_Z17_Z18, + Z17_Z18_Z19, + Z18_Z19_Z20, + Z19_Z20_Z21, + Z20_Z21_Z22, + Z21_Z22_Z23, + Z22_Z23_Z24, + Z23_Z24_Z25, + Z24_Z25_Z26, + Z25_Z26_Z27, + Z26_Z27_Z28, + Z27_Z28_Z29, + Z28_Z29_Z30, + Z29_Z30_Z31, + Z30_Z31_Z0, + Z31_Z0_Z1, + Z16_Z24, + Z17_Z25, + Z18_Z26, + Z19_Z27, + Z20_Z28, + Z21_Z29, + Z22_Z30, + Z23_Z31, + Z0_Z8, + Z1_Z9, + Z2_Z10, + Z3_Z11, + Z4_Z12, + Z5_Z13, + Z6_Z14, + Z7_Z15, + Z16_Z20_Z24_Z28, + Z17_Z21_Z25_Z29, + Z18_Z22_Z26_Z30, + Z19_Z23_Z27_Z31, + Z0_Z4_Z8_Z12, + Z1_Z5_Z9_Z13, + Z2_Z6_Z10_Z14, + Z3_Z7_Z11_Z15, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::FFR, + 2 => Reg::FP, + 3 => Reg::FPCR, + 4 => Reg::FPMR, + 5 => Reg::FPSR, + 6 => Reg::LR, + 7 => Reg::NZCV, + 8 => Reg::SP, + 9 => Reg::VG, + 10 => Reg::WSP, + 11 => Reg::WSP_HI, + 12 => Reg::WZR, + 13 => Reg::WZR_HI, + 14 => Reg::XZR, + 15 => Reg::ZA, + 16 => Reg::B0, + 17 => Reg::B1, + 18 => Reg::B2, + 19 => Reg::B3, + 20 => Reg::B4, + 21 => Reg::B5, + 22 => Reg::B6, + 23 => Reg::B7, + 24 => Reg::B8, + 25 => Reg::B9, + 26 => Reg::B10, + 27 => Reg::B11, + 28 => Reg::B12, + 29 => Reg::B13, + 30 => Reg::B14, + 31 => Reg::B15, + 32 => Reg::B16, + 33 => Reg::B17, + 34 => Reg::B18, + 35 => Reg::B19, + 36 => Reg::B20, + 37 => Reg::B21, + 38 => Reg::B22, + 39 => Reg::B23, + 40 => Reg::B24, + 41 => Reg::B25, + 42 => Reg::B26, + 43 => Reg::B27, + 44 => Reg::B28, + 45 => Reg::B29, + 46 => Reg::B30, + 47 => Reg::B31, + 48 => Reg::D0, + 49 => Reg::D1, + 50 => Reg::D2, + 51 => Reg::D3, + 52 => Reg::D4, + 53 => Reg::D5, + 54 => Reg::D6, + 55 => Reg::D7, + 56 => Reg::D8, + 57 => Reg::D9, + 58 => Reg::D10, + 59 => Reg::D11, + 60 => Reg::D12, + 61 => Reg::D13, + 62 => Reg::D14, + 63 => Reg::D15, + 64 => Reg::D16, + 65 => Reg::D17, + 66 => Reg::D18, + 67 => Reg::D19, + 68 => Reg::D20, + 69 => Reg::D21, + 70 => Reg::D22, + 71 => Reg::D23, + 72 => Reg::D24, + 73 => Reg::D25, + 74 => Reg::D26, + 75 => Reg::D27, + 76 => Reg::D28, + 77 => Reg::D29, + 78 => Reg::D30, + 79 => Reg::D31, + 80 => Reg::H0, + 81 => Reg::H1, + 82 => Reg::H2, + 83 => Reg::H3, + 84 => Reg::H4, + 85 => Reg::H5, + 86 => Reg::H6, + 87 => Reg::H7, + 88 => Reg::H8, + 89 => Reg::H9, + 90 => Reg::H10, + 91 => Reg::H11, + 92 => Reg::H12, + 93 => Reg::H13, + 94 => Reg::H14, + 95 => Reg::H15, + 96 => Reg::H16, + 97 => Reg::H17, + 98 => Reg::H18, + 99 => Reg::H19, + 100 => Reg::H20, + 101 => Reg::H21, + 102 => Reg::H22, + 103 => Reg::H23, + 104 => Reg::H24, + 105 => Reg::H25, + 106 => Reg::H26, + 107 => Reg::H27, + 108 => Reg::H28, + 109 => Reg::H29, + 110 => Reg::H30, + 111 => Reg::H31, + 112 => Reg::P0, + 113 => Reg::P1, + 114 => Reg::P2, + 115 => Reg::P3, + 116 => Reg::P4, + 117 => Reg::P5, + 118 => Reg::P6, + 119 => Reg::P7, + 120 => Reg::P8, + 121 => Reg::P9, + 122 => Reg::P10, + 123 => Reg::P11, + 124 => Reg::P12, + 125 => Reg::P13, + 126 => Reg::P14, + 127 => Reg::P15, + 128 => Reg::PN0, + 129 => Reg::PN1, + 130 => Reg::PN2, + 131 => Reg::PN3, + 132 => Reg::PN4, + 133 => Reg::PN5, + 134 => Reg::PN6, + 135 => Reg::PN7, + 136 => Reg::PN8, + 137 => Reg::PN9, + 138 => Reg::PN10, + 139 => Reg::PN11, + 140 => Reg::PN12, + 141 => Reg::PN13, + 142 => Reg::PN14, + 143 => Reg::PN15, + 144 => Reg::Q0, + 145 => Reg::Q1, + 146 => Reg::Q2, + 147 => Reg::Q3, + 148 => Reg::Q4, + 149 => Reg::Q5, + 150 => Reg::Q6, + 151 => Reg::Q7, + 152 => Reg::Q8, + 153 => Reg::Q9, + 154 => Reg::Q10, + 155 => Reg::Q11, + 156 => Reg::Q12, + 157 => Reg::Q13, + 158 => Reg::Q14, + 159 => Reg::Q15, + 160 => Reg::Q16, + 161 => Reg::Q17, + 162 => Reg::Q18, + 163 => Reg::Q19, + 164 => Reg::Q20, + 165 => Reg::Q21, + 166 => Reg::Q22, + 167 => Reg::Q23, + 168 => Reg::Q24, + 169 => Reg::Q25, + 170 => Reg::Q26, + 171 => Reg::Q27, + 172 => Reg::Q28, + 173 => Reg::Q29, + 174 => Reg::Q30, + 175 => Reg::Q31, + 176 => Reg::S0, + 177 => Reg::S1, + 178 => Reg::S2, + 179 => Reg::S3, + 180 => Reg::S4, + 181 => Reg::S5, + 182 => Reg::S6, + 183 => Reg::S7, + 184 => Reg::S8, + 185 => Reg::S9, + 186 => Reg::S10, + 187 => Reg::S11, + 188 => Reg::S12, + 189 => Reg::S13, + 190 => Reg::S14, + 191 => Reg::S15, + 192 => Reg::S16, + 193 => Reg::S17, + 194 => Reg::S18, + 195 => Reg::S19, + 196 => Reg::S20, + 197 => Reg::S21, + 198 => Reg::S22, + 199 => Reg::S23, + 200 => Reg::S24, + 201 => Reg::S25, + 202 => Reg::S26, + 203 => Reg::S27, + 204 => Reg::S28, + 205 => Reg::S29, + 206 => Reg::S30, + 207 => Reg::S31, + 208 => Reg::W0, + 209 => Reg::W1, + 210 => Reg::W2, + 211 => Reg::W3, + 212 => Reg::W4, + 213 => Reg::W5, + 214 => Reg::W6, + 215 => Reg::W7, + 216 => Reg::W8, + 217 => Reg::W9, + 218 => Reg::W10, + 219 => Reg::W11, + 220 => Reg::W12, + 221 => Reg::W13, + 222 => Reg::W14, + 223 => Reg::W15, + 224 => Reg::W16, + 225 => Reg::W17, + 226 => Reg::W18, + 227 => Reg::W19, + 228 => Reg::W20, + 229 => Reg::W21, + 230 => Reg::W22, + 231 => Reg::W23, + 232 => Reg::W24, + 233 => Reg::W25, + 234 => Reg::W26, + 235 => Reg::W27, + 236 => Reg::W28, + 237 => Reg::W29, + 238 => Reg::W30, + 239 => Reg::X0, + 240 => Reg::X1, + 241 => Reg::X2, + 242 => Reg::X3, + 243 => Reg::X4, + 244 => Reg::X5, + 245 => Reg::X6, + 246 => Reg::X7, + 247 => Reg::X8, + 248 => Reg::X9, + 249 => Reg::X10, + 250 => Reg::X11, + 251 => Reg::X12, + 252 => Reg::X13, + 253 => Reg::X14, + 254 => Reg::X15, + 255 => Reg::X16, + 256 => Reg::X17, + 257 => Reg::X18, + 258 => Reg::X19, + 259 => Reg::X20, + 260 => Reg::X21, + 261 => Reg::X22, + 262 => Reg::X23, + 263 => Reg::X24, + 264 => Reg::X25, + 265 => Reg::X26, + 266 => Reg::X27, + 267 => Reg::X28, + 268 => Reg::Z0, + 269 => Reg::Z1, + 270 => Reg::Z2, + 271 => Reg::Z3, + 272 => Reg::Z4, + 273 => Reg::Z5, + 274 => Reg::Z6, + 275 => Reg::Z7, + 276 => Reg::Z8, + 277 => Reg::Z9, + 278 => Reg::Z10, + 279 => Reg::Z11, + 280 => Reg::Z12, + 281 => Reg::Z13, + 282 => Reg::Z14, + 283 => Reg::Z15, + 284 => Reg::Z16, + 285 => Reg::Z17, + 286 => Reg::Z18, + 287 => Reg::Z19, + 288 => Reg::Z20, + 289 => Reg::Z21, + 290 => Reg::Z22, + 291 => Reg::Z23, + 292 => Reg::Z24, + 293 => Reg::Z25, + 294 => Reg::Z26, + 295 => Reg::Z27, + 296 => Reg::Z28, + 297 => Reg::Z29, + 298 => Reg::Z30, + 299 => Reg::Z31, + 300 => Reg::ZAB0, + 301 => Reg::ZAD0, + 302 => Reg::ZAD1, + 303 => Reg::ZAD2, + 304 => Reg::ZAD3, + 305 => Reg::ZAD4, + 306 => Reg::ZAD5, + 307 => Reg::ZAD6, + 308 => Reg::ZAD7, + 309 => Reg::ZAH0, + 310 => Reg::ZAH1, + 311 => Reg::ZAQ0, + 312 => Reg::ZAQ1, + 313 => Reg::ZAQ2, + 314 => Reg::ZAQ3, + 315 => Reg::ZAQ4, + 316 => Reg::ZAQ5, + 317 => Reg::ZAQ6, + 318 => Reg::ZAQ7, + 319 => Reg::ZAQ8, + 320 => Reg::ZAQ9, + 321 => Reg::ZAQ10, + 322 => Reg::ZAQ11, + 323 => Reg::ZAQ12, + 324 => Reg::ZAQ13, + 325 => Reg::ZAQ14, + 326 => Reg::ZAQ15, + 327 => Reg::ZAS0, + 328 => Reg::ZAS1, + 329 => Reg::ZAS2, + 330 => Reg::ZAS3, + 331 => Reg::ZT0, + 332 => Reg::B0_HI, + 333 => Reg::B1_HI, + 334 => Reg::B2_HI, + 335 => Reg::B3_HI, + 336 => Reg::B4_HI, + 337 => Reg::B5_HI, + 338 => Reg::B6_HI, + 339 => Reg::B7_HI, + 340 => Reg::B8_HI, + 341 => Reg::B9_HI, + 342 => Reg::B10_HI, + 343 => Reg::B11_HI, + 344 => Reg::B12_HI, + 345 => Reg::B13_HI, + 346 => Reg::B14_HI, + 347 => Reg::B15_HI, + 348 => Reg::B16_HI, + 349 => Reg::B17_HI, + 350 => Reg::B18_HI, + 351 => Reg::B19_HI, + 352 => Reg::B20_HI, + 353 => Reg::B21_HI, + 354 => Reg::B22_HI, + 355 => Reg::B23_HI, + 356 => Reg::B24_HI, + 357 => Reg::B25_HI, + 358 => Reg::B26_HI, + 359 => Reg::B27_HI, + 360 => Reg::B28_HI, + 361 => Reg::B29_HI, + 362 => Reg::B30_HI, + 363 => Reg::B31_HI, + 364 => Reg::D0_HI, + 365 => Reg::D1_HI, + 366 => Reg::D2_HI, + 367 => Reg::D3_HI, + 368 => Reg::D4_HI, + 369 => Reg::D5_HI, + 370 => Reg::D6_HI, + 371 => Reg::D7_HI, + 372 => Reg::D8_HI, + 373 => Reg::D9_HI, + 374 => Reg::D10_HI, + 375 => Reg::D11_HI, + 376 => Reg::D12_HI, + 377 => Reg::D13_HI, + 378 => Reg::D14_HI, + 379 => Reg::D15_HI, + 380 => Reg::D16_HI, + 381 => Reg::D17_HI, + 382 => Reg::D18_HI, + 383 => Reg::D19_HI, + 384 => Reg::D20_HI, + 385 => Reg::D21_HI, + 386 => Reg::D22_HI, + 387 => Reg::D23_HI, + 388 => Reg::D24_HI, + 389 => Reg::D25_HI, + 390 => Reg::D26_HI, + 391 => Reg::D27_HI, + 392 => Reg::D28_HI, + 393 => Reg::D29_HI, + 394 => Reg::D30_HI, + 395 => Reg::D31_HI, + 396 => Reg::H0_HI, + 397 => Reg::H1_HI, + 398 => Reg::H2_HI, + 399 => Reg::H3_HI, + 400 => Reg::H4_HI, + 401 => Reg::H5_HI, + 402 => Reg::H6_HI, + 403 => Reg::H7_HI, + 404 => Reg::H8_HI, + 405 => Reg::H9_HI, + 406 => Reg::H10_HI, + 407 => Reg::H11_HI, + 408 => Reg::H12_HI, + 409 => Reg::H13_HI, + 410 => Reg::H14_HI, + 411 => Reg::H15_HI, + 412 => Reg::H16_HI, + 413 => Reg::H17_HI, + 414 => Reg::H18_HI, + 415 => Reg::H19_HI, + 416 => Reg::H20_HI, + 417 => Reg::H21_HI, + 418 => Reg::H22_HI, + 419 => Reg::H23_HI, + 420 => Reg::H24_HI, + 421 => Reg::H25_HI, + 422 => Reg::H26_HI, + 423 => Reg::H27_HI, + 424 => Reg::H28_HI, + 425 => Reg::H29_HI, + 426 => Reg::H30_HI, + 427 => Reg::H31_HI, + 428 => Reg::Q0_HI, + 429 => Reg::Q1_HI, + 430 => Reg::Q2_HI, + 431 => Reg::Q3_HI, + 432 => Reg::Q4_HI, + 433 => Reg::Q5_HI, + 434 => Reg::Q6_HI, + 435 => Reg::Q7_HI, + 436 => Reg::Q8_HI, + 437 => Reg::Q9_HI, + 438 => Reg::Q10_HI, + 439 => Reg::Q11_HI, + 440 => Reg::Q12_HI, + 441 => Reg::Q13_HI, + 442 => Reg::Q14_HI, + 443 => Reg::Q15_HI, + 444 => Reg::Q16_HI, + 445 => Reg::Q17_HI, + 446 => Reg::Q18_HI, + 447 => Reg::Q19_HI, + 448 => Reg::Q20_HI, + 449 => Reg::Q21_HI, + 450 => Reg::Q22_HI, + 451 => Reg::Q23_HI, + 452 => Reg::Q24_HI, + 453 => Reg::Q25_HI, + 454 => Reg::Q26_HI, + 455 => Reg::Q27_HI, + 456 => Reg::Q28_HI, + 457 => Reg::Q29_HI, + 458 => Reg::Q30_HI, + 459 => Reg::Q31_HI, + 460 => Reg::S0_HI, + 461 => Reg::S1_HI, + 462 => Reg::S2_HI, + 463 => Reg::S3_HI, + 464 => Reg::S4_HI, + 465 => Reg::S5_HI, + 466 => Reg::S6_HI, + 467 => Reg::S7_HI, + 468 => Reg::S8_HI, + 469 => Reg::S9_HI, + 470 => Reg::S10_HI, + 471 => Reg::S11_HI, + 472 => Reg::S12_HI, + 473 => Reg::S13_HI, + 474 => Reg::S14_HI, + 475 => Reg::S15_HI, + 476 => Reg::S16_HI, + 477 => Reg::S17_HI, + 478 => Reg::S18_HI, + 479 => Reg::S19_HI, + 480 => Reg::S20_HI, + 481 => Reg::S21_HI, + 482 => Reg::S22_HI, + 483 => Reg::S23_HI, + 484 => Reg::S24_HI, + 485 => Reg::S25_HI, + 486 => Reg::S26_HI, + 487 => Reg::S27_HI, + 488 => Reg::S28_HI, + 489 => Reg::S29_HI, + 490 => Reg::S30_HI, + 491 => Reg::S31_HI, + 492 => Reg::W0_HI, + 493 => Reg::W1_HI, + 494 => Reg::W2_HI, + 495 => Reg::W3_HI, + 496 => Reg::W4_HI, + 497 => Reg::W5_HI, + 498 => Reg::W6_HI, + 499 => Reg::W7_HI, + 500 => Reg::W8_HI, + 501 => Reg::W9_HI, + 502 => Reg::W10_HI, + 503 => Reg::W11_HI, + 504 => Reg::W12_HI, + 505 => Reg::W13_HI, + 506 => Reg::W14_HI, + 507 => Reg::W15_HI, + 508 => Reg::W16_HI, + 509 => Reg::W17_HI, + 510 => Reg::W18_HI, + 511 => Reg::W19_HI, + 512 => Reg::W20_HI, + 513 => Reg::W21_HI, + 514 => Reg::W22_HI, + 515 => Reg::W23_HI, + 516 => Reg::W24_HI, + 517 => Reg::W25_HI, + 518 => Reg::W26_HI, + 519 => Reg::W27_HI, + 520 => Reg::W28_HI, + 521 => Reg::W29_HI, + 522 => Reg::W30_HI, + 523 => Reg::D0_D1, + 524 => Reg::D1_D2, + 525 => Reg::D2_D3, + 526 => Reg::D3_D4, + 527 => Reg::D4_D5, + 528 => Reg::D5_D6, + 529 => Reg::D6_D7, + 530 => Reg::D7_D8, + 531 => Reg::D8_D9, + 532 => Reg::D9_D10, + 533 => Reg::D10_D11, + 534 => Reg::D11_D12, + 535 => Reg::D12_D13, + 536 => Reg::D13_D14, + 537 => Reg::D14_D15, + 538 => Reg::D15_D16, + 539 => Reg::D16_D17, + 540 => Reg::D17_D18, + 541 => Reg::D18_D19, + 542 => Reg::D19_D20, + 543 => Reg::D20_D21, + 544 => Reg::D21_D22, + 545 => Reg::D22_D23, + 546 => Reg::D23_D24, + 547 => Reg::D24_D25, + 548 => Reg::D25_D26, + 549 => Reg::D26_D27, + 550 => Reg::D27_D28, + 551 => Reg::D28_D29, + 552 => Reg::D29_D30, + 553 => Reg::D30_D31, + 554 => Reg::D31_D0, + 555 => Reg::D0_D1_D2_D3, + 556 => Reg::D1_D2_D3_D4, + 557 => Reg::D2_D3_D4_D5, + 558 => Reg::D3_D4_D5_D6, + 559 => Reg::D4_D5_D6_D7, + 560 => Reg::D5_D6_D7_D8, + 561 => Reg::D6_D7_D8_D9, + 562 => Reg::D7_D8_D9_D10, + 563 => Reg::D8_D9_D10_D11, + 564 => Reg::D9_D10_D11_D12, + 565 => Reg::D10_D11_D12_D13, + 566 => Reg::D11_D12_D13_D14, + 567 => Reg::D12_D13_D14_D15, + 568 => Reg::D13_D14_D15_D16, + 569 => Reg::D14_D15_D16_D17, + 570 => Reg::D15_D16_D17_D18, + 571 => Reg::D16_D17_D18_D19, + 572 => Reg::D17_D18_D19_D20, + 573 => Reg::D18_D19_D20_D21, + 574 => Reg::D19_D20_D21_D22, + 575 => Reg::D20_D21_D22_D23, + 576 => Reg::D21_D22_D23_D24, + 577 => Reg::D22_D23_D24_D25, + 578 => Reg::D23_D24_D25_D26, + 579 => Reg::D24_D25_D26_D27, + 580 => Reg::D25_D26_D27_D28, + 581 => Reg::D26_D27_D28_D29, + 582 => Reg::D27_D28_D29_D30, + 583 => Reg::D28_D29_D30_D31, + 584 => Reg::D29_D30_D31_D0, + 585 => Reg::D30_D31_D0_D1, + 586 => Reg::D31_D0_D1_D2, + 587 => Reg::D0_D1_D2, + 588 => Reg::D1_D2_D3, + 589 => Reg::D2_D3_D4, + 590 => Reg::D3_D4_D5, + 591 => Reg::D4_D5_D6, + 592 => Reg::D5_D6_D7, + 593 => Reg::D6_D7_D8, + 594 => Reg::D7_D8_D9, + 595 => Reg::D8_D9_D10, + 596 => Reg::D9_D10_D11, + 597 => Reg::D10_D11_D12, + 598 => Reg::D11_D12_D13, + 599 => Reg::D12_D13_D14, + 600 => Reg::D13_D14_D15, + 601 => Reg::D14_D15_D16, + 602 => Reg::D15_D16_D17, + 603 => Reg::D16_D17_D18, + 604 => Reg::D17_D18_D19, + 605 => Reg::D18_D19_D20, + 606 => Reg::D19_D20_D21, + 607 => Reg::D20_D21_D22, + 608 => Reg::D21_D22_D23, + 609 => Reg::D22_D23_D24, + 610 => Reg::D23_D24_D25, + 611 => Reg::D24_D25_D26, + 612 => Reg::D25_D26_D27, + 613 => Reg::D26_D27_D28, + 614 => Reg::D27_D28_D29, + 615 => Reg::D28_D29_D30, + 616 => Reg::D29_D30_D31, + 617 => Reg::D30_D31_D0, + 618 => Reg::D31_D0_D1, + 619 => Reg::P0_P1, + 620 => Reg::P1_P2, + 621 => Reg::P2_P3, + 622 => Reg::P3_P4, + 623 => Reg::P4_P5, + 624 => Reg::P5_P6, + 625 => Reg::P6_P7, + 626 => Reg::P7_P8, + 627 => Reg::P8_P9, + 628 => Reg::P9_P10, + 629 => Reg::P10_P11, + 630 => Reg::P11_P12, + 631 => Reg::P12_P13, + 632 => Reg::P13_P14, + 633 => Reg::P14_P15, + 634 => Reg::P15_P0, + 635 => Reg::Q0_Q1, + 636 => Reg::Q1_Q2, + 637 => Reg::Q2_Q3, + 638 => Reg::Q3_Q4, + 639 => Reg::Q4_Q5, + 640 => Reg::Q5_Q6, + 641 => Reg::Q6_Q7, + 642 => Reg::Q7_Q8, + 643 => Reg::Q8_Q9, + 644 => Reg::Q9_Q10, + 645 => Reg::Q10_Q11, + 646 => Reg::Q11_Q12, + 647 => Reg::Q12_Q13, + 648 => Reg::Q13_Q14, + 649 => Reg::Q14_Q15, + 650 => Reg::Q15_Q16, + 651 => Reg::Q16_Q17, + 652 => Reg::Q17_Q18, + 653 => Reg::Q18_Q19, + 654 => Reg::Q19_Q20, + 655 => Reg::Q20_Q21, + 656 => Reg::Q21_Q22, + 657 => Reg::Q22_Q23, + 658 => Reg::Q23_Q24, + 659 => Reg::Q24_Q25, + 660 => Reg::Q25_Q26, + 661 => Reg::Q26_Q27, + 662 => Reg::Q27_Q28, + 663 => Reg::Q28_Q29, + 664 => Reg::Q29_Q30, + 665 => Reg::Q30_Q31, + 666 => Reg::Q31_Q0, + 667 => Reg::Q0_Q1_Q2_Q3, + 668 => Reg::Q1_Q2_Q3_Q4, + 669 => Reg::Q2_Q3_Q4_Q5, + 670 => Reg::Q3_Q4_Q5_Q6, + 671 => Reg::Q4_Q5_Q6_Q7, + 672 => Reg::Q5_Q6_Q7_Q8, + 673 => Reg::Q6_Q7_Q8_Q9, + 674 => Reg::Q7_Q8_Q9_Q10, + 675 => Reg::Q8_Q9_Q10_Q11, + 676 => Reg::Q9_Q10_Q11_Q12, + 677 => Reg::Q10_Q11_Q12_Q13, + 678 => Reg::Q11_Q12_Q13_Q14, + 679 => Reg::Q12_Q13_Q14_Q15, + 680 => Reg::Q13_Q14_Q15_Q16, + 681 => Reg::Q14_Q15_Q16_Q17, + 682 => Reg::Q15_Q16_Q17_Q18, + 683 => Reg::Q16_Q17_Q18_Q19, + 684 => Reg::Q17_Q18_Q19_Q20, + 685 => Reg::Q18_Q19_Q20_Q21, + 686 => Reg::Q19_Q20_Q21_Q22, + 687 => Reg::Q20_Q21_Q22_Q23, + 688 => Reg::Q21_Q22_Q23_Q24, + 689 => Reg::Q22_Q23_Q24_Q25, + 690 => Reg::Q23_Q24_Q25_Q26, + 691 => Reg::Q24_Q25_Q26_Q27, + 692 => Reg::Q25_Q26_Q27_Q28, + 693 => Reg::Q26_Q27_Q28_Q29, + 694 => Reg::Q27_Q28_Q29_Q30, + 695 => Reg::Q28_Q29_Q30_Q31, + 696 => Reg::Q29_Q30_Q31_Q0, + 697 => Reg::Q30_Q31_Q0_Q1, + 698 => Reg::Q31_Q0_Q1_Q2, + 699 => Reg::Q0_Q1_Q2, + 700 => Reg::Q1_Q2_Q3, + 701 => Reg::Q2_Q3_Q4, + 702 => Reg::Q3_Q4_Q5, + 703 => Reg::Q4_Q5_Q6, + 704 => Reg::Q5_Q6_Q7, + 705 => Reg::Q6_Q7_Q8, + 706 => Reg::Q7_Q8_Q9, + 707 => Reg::Q8_Q9_Q10, + 708 => Reg::Q9_Q10_Q11, + 709 => Reg::Q10_Q11_Q12, + 710 => Reg::Q11_Q12_Q13, + 711 => Reg::Q12_Q13_Q14, + 712 => Reg::Q13_Q14_Q15, + 713 => Reg::Q14_Q15_Q16, + 714 => Reg::Q15_Q16_Q17, + 715 => Reg::Q16_Q17_Q18, + 716 => Reg::Q17_Q18_Q19, + 717 => Reg::Q18_Q19_Q20, + 718 => Reg::Q19_Q20_Q21, + 719 => Reg::Q20_Q21_Q22, + 720 => Reg::Q21_Q22_Q23, + 721 => Reg::Q22_Q23_Q24, + 722 => Reg::Q23_Q24_Q25, + 723 => Reg::Q24_Q25_Q26, + 724 => Reg::Q25_Q26_Q27, + 725 => Reg::Q26_Q27_Q28, + 726 => Reg::Q27_Q28_Q29, + 727 => Reg::Q28_Q29_Q30, + 728 => Reg::Q29_Q30_Q31, + 729 => Reg::Q30_Q31_Q0, + 730 => Reg::Q31_Q0_Q1, + 731 => Reg::X22_X23_X24_X25_X26_X27_X28_FP, + 732 => Reg::X0_X1_X2_X3_X4_X5_X6_X7, + 733 => Reg::X2_X3_X4_X5_X6_X7_X8_X9, + 734 => Reg::X4_X5_X6_X7_X8_X9_X10_X11, + 735 => Reg::X6_X7_X8_X9_X10_X11_X12_X13, + 736 => Reg::X8_X9_X10_X11_X12_X13_X14_X15, + 737 => Reg::X10_X11_X12_X13_X14_X15_X16_X17, + 738 => Reg::X12_X13_X14_X15_X16_X17_X18_X19, + 739 => Reg::X14_X15_X16_X17_X18_X19_X20_X21, + 740 => Reg::X16_X17_X18_X19_X20_X21_X22_X23, + 741 => Reg::X18_X19_X20_X21_X22_X23_X24_X25, + 742 => Reg::X20_X21_X22_X23_X24_X25_X26_X27, + 743 => Reg::W30_WZR, + 744 => Reg::W0_W1, + 745 => Reg::W2_W3, + 746 => Reg::W4_W5, + 747 => Reg::W6_W7, + 748 => Reg::W8_W9, + 749 => Reg::W10_W11, + 750 => Reg::W12_W13, + 751 => Reg::W14_W15, + 752 => Reg::W16_W17, + 753 => Reg::W18_W19, + 754 => Reg::W20_W21, + 755 => Reg::W22_W23, + 756 => Reg::W24_W25, + 757 => Reg::W26_W27, + 758 => Reg::W28_W29, + 759 => Reg::LR_XZR, + 760 => Reg::X28_FP, + 761 => Reg::X0_X1, + 762 => Reg::X2_X3, + 763 => Reg::X4_X5, + 764 => Reg::X6_X7, + 765 => Reg::X8_X9, + 766 => Reg::X10_X11, + 767 => Reg::X12_X13, + 768 => Reg::X14_X15, + 769 => Reg::X16_X17, + 770 => Reg::X18_X19, + 771 => Reg::X20_X21, + 772 => Reg::X22_X23, + 773 => Reg::X24_X25, + 774 => Reg::X26_X27, + 775 => Reg::Z0_Z1, + 776 => Reg::Z1_Z2, + 777 => Reg::Z2_Z3, + 778 => Reg::Z3_Z4, + 779 => Reg::Z4_Z5, + 780 => Reg::Z5_Z6, + 781 => Reg::Z6_Z7, + 782 => Reg::Z7_Z8, + 783 => Reg::Z8_Z9, + 784 => Reg::Z9_Z10, + 785 => Reg::Z10_Z11, + 786 => Reg::Z11_Z12, + 787 => Reg::Z12_Z13, + 788 => Reg::Z13_Z14, + 789 => Reg::Z14_Z15, + 790 => Reg::Z15_Z16, + 791 => Reg::Z16_Z17, + 792 => Reg::Z17_Z18, + 793 => Reg::Z18_Z19, + 794 => Reg::Z19_Z20, + 795 => Reg::Z20_Z21, + 796 => Reg::Z21_Z22, + 797 => Reg::Z22_Z23, + 798 => Reg::Z23_Z24, + 799 => Reg::Z24_Z25, + 800 => Reg::Z25_Z26, + 801 => Reg::Z26_Z27, + 802 => Reg::Z27_Z28, + 803 => Reg::Z28_Z29, + 804 => Reg::Z29_Z30, + 805 => Reg::Z30_Z31, + 806 => Reg::Z31_Z0, + 807 => Reg::Z0_Z1_Z2_Z3, + 808 => Reg::Z1_Z2_Z3_Z4, + 809 => Reg::Z2_Z3_Z4_Z5, + 810 => Reg::Z3_Z4_Z5_Z6, + 811 => Reg::Z4_Z5_Z6_Z7, + 812 => Reg::Z5_Z6_Z7_Z8, + 813 => Reg::Z6_Z7_Z8_Z9, + 814 => Reg::Z7_Z8_Z9_Z10, + 815 => Reg::Z8_Z9_Z10_Z11, + 816 => Reg::Z9_Z10_Z11_Z12, + 817 => Reg::Z10_Z11_Z12_Z13, + 818 => Reg::Z11_Z12_Z13_Z14, + 819 => Reg::Z12_Z13_Z14_Z15, + 820 => Reg::Z13_Z14_Z15_Z16, + 821 => Reg::Z14_Z15_Z16_Z17, + 822 => Reg::Z15_Z16_Z17_Z18, + 823 => Reg::Z16_Z17_Z18_Z19, + 824 => Reg::Z17_Z18_Z19_Z20, + 825 => Reg::Z18_Z19_Z20_Z21, + 826 => Reg::Z19_Z20_Z21_Z22, + 827 => Reg::Z20_Z21_Z22_Z23, + 828 => Reg::Z21_Z22_Z23_Z24, + 829 => Reg::Z22_Z23_Z24_Z25, + 830 => Reg::Z23_Z24_Z25_Z26, + 831 => Reg::Z24_Z25_Z26_Z27, + 832 => Reg::Z25_Z26_Z27_Z28, + 833 => Reg::Z26_Z27_Z28_Z29, + 834 => Reg::Z27_Z28_Z29_Z30, + 835 => Reg::Z28_Z29_Z30_Z31, + 836 => Reg::Z29_Z30_Z31_Z0, + 837 => Reg::Z30_Z31_Z0_Z1, + 838 => Reg::Z31_Z0_Z1_Z2, + 839 => Reg::Z0_Z1_Z2, + 840 => Reg::Z1_Z2_Z3, + 841 => Reg::Z2_Z3_Z4, + 842 => Reg::Z3_Z4_Z5, + 843 => Reg::Z4_Z5_Z6, + 844 => Reg::Z5_Z6_Z7, + 845 => Reg::Z6_Z7_Z8, + 846 => Reg::Z7_Z8_Z9, + 847 => Reg::Z8_Z9_Z10, + 848 => Reg::Z9_Z10_Z11, + 849 => Reg::Z10_Z11_Z12, + 850 => Reg::Z11_Z12_Z13, + 851 => Reg::Z12_Z13_Z14, + 852 => Reg::Z13_Z14_Z15, + 853 => Reg::Z14_Z15_Z16, + 854 => Reg::Z15_Z16_Z17, + 855 => Reg::Z16_Z17_Z18, + 856 => Reg::Z17_Z18_Z19, + 857 => Reg::Z18_Z19_Z20, + 858 => Reg::Z19_Z20_Z21, + 859 => Reg::Z20_Z21_Z22, + 860 => Reg::Z21_Z22_Z23, + 861 => Reg::Z22_Z23_Z24, + 862 => Reg::Z23_Z24_Z25, + 863 => Reg::Z24_Z25_Z26, + 864 => Reg::Z25_Z26_Z27, + 865 => Reg::Z26_Z27_Z28, + 866 => Reg::Z27_Z28_Z29, + 867 => Reg::Z28_Z29_Z30, + 868 => Reg::Z29_Z30_Z31, + 869 => Reg::Z30_Z31_Z0, + 870 => Reg::Z31_Z0_Z1, + 871 => Reg::Z16_Z24, + 872 => Reg::Z17_Z25, + 873 => Reg::Z18_Z26, + 874 => Reg::Z19_Z27, + 875 => Reg::Z20_Z28, + 876 => Reg::Z21_Z29, + 877 => Reg::Z22_Z30, + 878 => Reg::Z23_Z31, + 879 => Reg::Z0_Z8, + 880 => Reg::Z1_Z9, + 881 => Reg::Z2_Z10, + 882 => Reg::Z3_Z11, + 883 => Reg::Z4_Z12, + 884 => Reg::Z5_Z13, + 885 => Reg::Z6_Z14, + 886 => Reg::Z7_Z15, + 887 => Reg::Z16_Z20_Z24_Z28, + 888 => Reg::Z17_Z21_Z25_Z29, + 889 => Reg::Z18_Z22_Z26_Z30, + 890 => Reg::Z19_Z23_Z27_Z31, + 891 => Reg::Z0_Z4_Z8_Z12, + 892 => Reg::Z1_Z5_Z9_Z13, + 893 => Reg::Z2_Z6_Z10_Z14, + 894 => Reg::Z3_Z7_Z11_Z15, + 895 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum SysReg { + OSDTRRX_EL1, + DBGBVR0_EL1, + DBGBCR0_EL1, + DBGWVR0_EL1, + DBGWCR0_EL1, + DBGBVR1_EL1, + DBGBCR1_EL1, + DBGWVR1_EL1, + DBGWCR1_EL1, + MDCCINT_EL1, + MDSCR_EL1, + DBGBVR2_EL1, + DBGBCR2_EL1, + DBGWVR2_EL1, + DBGWCR2_EL1, + OSDTRTX_EL1, + DBGBVR3_EL1, + DBGBCR3_EL1, + DBGWVR3_EL1, + DBGWCR3_EL1, + MDSELR_EL1, + DBGBVR4_EL1, + DBGBCR4_EL1, + DBGWVR4_EL1, + DBGWCR4_EL1, + MDSTEPOP_EL1, + DBGBVR5_EL1, + DBGBCR5_EL1, + DBGWVR5_EL1, + DBGWCR5_EL1, + OSECCR_EL1, + DBGBVR6_EL1, + DBGBCR6_EL1, + DBGWVR6_EL1, + DBGWCR6_EL1, + DBGBVR7_EL1, + DBGBCR7_EL1, + DBGWVR7_EL1, + DBGWCR7_EL1, + DBGBVR8_EL1, + DBGBCR8_EL1, + DBGWVR8_EL1, + DBGWCR8_EL1, + DBGBVR9_EL1, + DBGBCR9_EL1, + DBGWVR9_EL1, + DBGWCR9_EL1, + DBGBVR10_EL1, + DBGBCR10_EL1, + DBGWVR10_EL1, + DBGWCR10_EL1, + DBGBVR11_EL1, + DBGBCR11_EL1, + DBGWVR11_EL1, + DBGWCR11_EL1, + DBGBVR12_EL1, + DBGBCR12_EL1, + DBGWVR12_EL1, + DBGWCR12_EL1, + DBGBVR13_EL1, + DBGBCR13_EL1, + DBGWVR13_EL1, + DBGWCR13_EL1, + DBGBVR14_EL1, + DBGBCR14_EL1, + DBGWVR14_EL1, + DBGWCR14_EL1, + DBGBVR15_EL1, + DBGBCR15_EL1, + DBGWVR15_EL1, + DBGWCR15_EL1, + MDRAR_EL1, + OSLAR_EL1, + OSLSR_EL1, + OSDLR_EL1, + DBGPRCR_EL1, + DBGCLAIMSET_EL1, + DBGCLAIMCLR_EL1, + DBGAUTHSTATUS_EL1, + SPMCGCR0_EL1, + SPMCGCR1_EL1, + SPMACCESSR_EL1, + SPMIIDR_EL1, + SPMDEVARCH_EL1, + SPMDEVAFF_EL1, + SPMCFGR_EL1, + SPMINTENSET_EL1, + SPMINTENCLR_EL1, + PMEVCNTSVR0_EL1, + PMEVCNTSVR1_EL1, + PMEVCNTSVR2_EL1, + PMEVCNTSVR3_EL1, + PMEVCNTSVR4_EL1, + PMEVCNTSVR5_EL1, + PMEVCNTSVR6_EL1, + PMEVCNTSVR7_EL1, + PMEVCNTSVR8_EL1, + PMEVCNTSVR9_EL1, + PMEVCNTSVR10_EL1, + PMEVCNTSVR11_EL1, + PMEVCNTSVR12_EL1, + PMEVCNTSVR13_EL1, + PMEVCNTSVR14_EL1, + PMEVCNTSVR15_EL1, + PMEVCNTSVR16_EL1, + PMEVCNTSVR17_EL1, + PMEVCNTSVR18_EL1, + PMEVCNTSVR19_EL1, + PMEVCNTSVR20_EL1, + PMEVCNTSVR21_EL1, + PMEVCNTSVR22_EL1, + PMEVCNTSVR23_EL1, + PMEVCNTSVR24_EL1, + PMEVCNTSVR25_EL1, + PMEVCNTSVR26_EL1, + PMEVCNTSVR27_EL1, + PMEVCNTSVR28_EL1, + PMEVCNTSVR29_EL1, + PMEVCNTSVR30_EL1, + PMCCNTSVR_EL1, + PMICNTSVR_EL1, + TRCTRACEIDR, + TRCVICTLR, + TRCSEQEVR0, + TRCCNTRLDVR0, + TRCIDR8, + TRCIMSPEC0, + TRCPRGCTLR, + TRCQCTLR, + TRCVIIECTLR, + TRCSEQEVR1, + TRCCNTRLDVR1, + TRCIDR9, + TRCIMSPEC1, + TRCPROCSELR, + TRCITEEDCR, + TRCVISSCTLR, + TRCSEQEVR2, + TRCCNTRLDVR2, + TRCIDR10, + TRCIMSPEC2, + TRCSTATR, + TRCVIPCSSCTLR, + TRCCNTRLDVR3, + TRCIDR11, + TRCIMSPEC3, + TRCCONFIGR, + TRCCNTCTLR0, + TRCIDR12, + TRCIMSPEC4, + TRCCNTCTLR1, + TRCIDR13, + TRCIMSPEC5, + TRCAUXCTLR, + TRCSEQRSTEVR, + TRCCNTCTLR2, + TRCIMSPEC6, + TRCSEQSTR, + TRCCNTCTLR3, + TRCIMSPEC7, + TRCEVENTCTL0R, + TRCVDCTLR, + TRCEXTINSELR, + TRCCNTVR0, + TRCIDR0, + TRCEVENTCTL1R, + TRCVDSACCTLR, + TRCEXTINSELR1, + TRCCNTVR1, + TRCIDR1, + TRCRSR, + TRCVDARCCTLR, + TRCEXTINSELR2, + TRCCNTVR2, + TRCIDR2, + TRCSTALLCTLR, + TRCEXTINSELR3, + TRCCNTVR3, + TRCIDR3, + TRCTSCTLR, + TRCIDR4, + TRCSYNCPR, + TRCIDR5, + TRCCCCTLR, + TRCIDR6, + TRCBBCTLR, + TRCIDR7, + TRCRSCTLR16, + TRCSSCCR0, + TRCSSPCICR0, + TRCOSLAR, + TRCRSCTLR17, + TRCSSCCR1, + TRCSSPCICR1, + TRCOSLSR, + TRCRSCTLR2, + TRCRSCTLR18, + TRCSSCCR2, + TRCSSPCICR2, + TRCRSCTLR3, + TRCRSCTLR19, + TRCSSCCR3, + TRCSSPCICR3, + TRCRSCTLR4, + TRCRSCTLR20, + TRCSSCCR4, + TRCSSPCICR4, + TRCPDCR, + TRCRSCTLR5, + TRCRSCTLR21, + TRCSSCCR5, + TRCSSPCICR5, + TRCPDSR, + TRCRSCTLR6, + TRCRSCTLR22, + TRCSSCCR6, + TRCSSPCICR6, + TRCRSCTLR7, + TRCRSCTLR23, + TRCSSCCR7, + TRCSSPCICR7, + TRCRSCTLR8, + TRCRSCTLR24, + TRCSSCSR0, + TRCRSCTLR9, + TRCRSCTLR25, + TRCSSCSR1, + TRCRSCTLR10, + TRCRSCTLR26, + TRCSSCSR2, + TRCRSCTLR11, + TRCRSCTLR27, + TRCSSCSR3, + TRCRSCTLR12, + TRCRSCTLR28, + TRCSSCSR4, + TRCRSCTLR13, + TRCRSCTLR29, + TRCSSCSR5, + TRCRSCTLR14, + TRCRSCTLR30, + TRCSSCSR6, + TRCRSCTLR15, + TRCRSCTLR31, + TRCSSCSR7, + TRCACVR0, + TRCACVR8, + TRCACATR0, + TRCACATR8, + TRCDVCVR0, + TRCDVCVR4, + TRCDVCMR0, + TRCDVCMR4, + TRCACVR1, + TRCACVR9, + TRCACATR1, + TRCACATR9, + TRCACVR2, + TRCACVR10, + TRCACATR2, + TRCACATR10, + TRCDVCVR1, + TRCDVCVR5, + TRCDVCMR1, + TRCDVCMR5, + TRCACVR3, + TRCACVR11, + TRCACATR3, + TRCACATR11, + TRCACVR4, + TRCACVR12, + TRCACATR4, + TRCACATR12, + TRCDVCVR2, + TRCDVCVR6, + TRCDVCMR2, + TRCDVCMR6, + TRCACVR5, + TRCACVR13, + TRCACATR5, + TRCACATR13, + TRCACVR6, + TRCACVR14, + TRCACATR6, + TRCACATR14, + TRCDVCVR3, + TRCDVCVR7, + TRCDVCMR3, + TRCDVCMR7, + TRCACVR7, + TRCACVR15, + TRCACATR7, + TRCACATR15, + TRCCIDCVR0, + TRCVMIDCVR0, + TRCCIDCCTLR0, + TRCCIDCCTLR1, + TRCCIDCVR1, + TRCVMIDCVR1, + TRCVMIDCCTLR0, + TRCVMIDCCTLR1, + TRCCIDCVR2, + TRCVMIDCVR2, + TRCCIDCVR3, + TRCVMIDCVR3, + TRCCIDCVR4, + TRCVMIDCVR4, + TRCCIDCVR5, + TRCVMIDCVR5, + TRCCIDCVR6, + TRCVMIDCVR6, + TRCCIDCVR7, + TRCVMIDCVR7, + TRCITCTRL, + TRCDEVID, + TRCDEVTYPE, + TRCPIDR4, + TRCPIDR5, + TRCPIDR6, + TRCPIDR7, + TRCCLAIMSET, + TRCPIDR0, + TRCCLAIMCLR, + TRCPIDR1, + TRCDEVAFF0, + TRCPIDR2, + TRCDEVAFF1, + TRCPIDR3, + TRCLAR, + TRCCIDR0, + TRCLSR, + TRCCIDR1, + TRCAUTHSTATUS, + TRCCIDR2, + TRCDEVARCH, + TRCCIDR3, + BRBINF0_EL1, + BRBSRC0_EL1, + BRBTGT0_EL1, + BRBINF16_EL1, + BRBSRC16_EL1, + BRBTGT16_EL1, + BRBINF1_EL1, + BRBSRC1_EL1, + BRBTGT1_EL1, + BRBINF17_EL1, + BRBSRC17_EL1, + BRBTGT17_EL1, + BRBINF2_EL1, + BRBSRC2_EL1, + BRBTGT2_EL1, + BRBINF18_EL1, + BRBSRC18_EL1, + BRBTGT18_EL1, + BRBINF3_EL1, + BRBSRC3_EL1, + BRBTGT3_EL1, + BRBINF19_EL1, + BRBSRC19_EL1, + BRBTGT19_EL1, + BRBINF4_EL1, + BRBSRC4_EL1, + BRBTGT4_EL1, + BRBINF20_EL1, + BRBSRC20_EL1, + BRBTGT20_EL1, + BRBINF5_EL1, + BRBSRC5_EL1, + BRBTGT5_EL1, + BRBINF21_EL1, + BRBSRC21_EL1, + BRBTGT21_EL1, + BRBINF6_EL1, + BRBSRC6_EL1, + BRBTGT6_EL1, + BRBINF22_EL1, + BRBSRC22_EL1, + BRBTGT22_EL1, + BRBINF7_EL1, + BRBSRC7_EL1, + BRBTGT7_EL1, + BRBINF23_EL1, + BRBSRC23_EL1, + BRBTGT23_EL1, + BRBINF8_EL1, + BRBSRC8_EL1, + BRBTGT8_EL1, + BRBINF24_EL1, + BRBSRC24_EL1, + BRBTGT24_EL1, + BRBINF9_EL1, + BRBSRC9_EL1, + BRBTGT9_EL1, + BRBINF25_EL1, + BRBSRC25_EL1, + BRBTGT25_EL1, + BRBINF10_EL1, + BRBSRC10_EL1, + BRBTGT10_EL1, + BRBINF26_EL1, + BRBSRC26_EL1, + BRBTGT26_EL1, + BRBINF11_EL1, + BRBSRC11_EL1, + BRBTGT11_EL1, + BRBINF27_EL1, + BRBSRC27_EL1, + BRBTGT27_EL1, + BRBINF12_EL1, + BRBSRC12_EL1, + BRBTGT12_EL1, + BRBINF28_EL1, + BRBSRC28_EL1, + BRBTGT28_EL1, + BRBINF13_EL1, + BRBSRC13_EL1, + BRBTGT13_EL1, + BRBINF29_EL1, + BRBSRC29_EL1, + BRBTGT29_EL1, + BRBINF14_EL1, + BRBSRC14_EL1, + BRBTGT14_EL1, + BRBINF30_EL1, + BRBSRC30_EL1, + BRBTGT30_EL1, + BRBINF15_EL1, + BRBSRC15_EL1, + BRBTGT15_EL1, + BRBINF31_EL1, + BRBSRC31_EL1, + BRBTGT31_EL1, + BRBCR_EL1, + BRBFCR_EL1, + BRBTS_EL1, + BRBINFINJ_EL1, + BRBSRCINJ_EL1, + BRBTGTINJ_EL1, + BRBIDR0_EL1, + TEECR32_EL1, + TEEHBR32_EL1, + MDCCSR_EL0, + DBGDTR_EL0, + DBGDTRRX_EL0, + SPMCR_EL0, + SPMCNTENSET_EL0, + SPMCNTENCLR_EL0, + SPMOVSCLR_EL0, + SPMZR_EL0, + SPMSELR_EL0, + SPMOVSSET_EL0, + SPMEVCNTR0_EL0, + SPMEVCNTR1_EL0, + SPMEVCNTR2_EL0, + SPMEVCNTR3_EL0, + SPMEVCNTR4_EL0, + SPMEVCNTR5_EL0, + SPMEVCNTR6_EL0, + SPMEVCNTR7_EL0, + SPMEVCNTR8_EL0, + SPMEVCNTR9_EL0, + SPMEVCNTR10_EL0, + SPMEVCNTR11_EL0, + SPMEVCNTR12_EL0, + SPMEVCNTR13_EL0, + SPMEVCNTR14_EL0, + SPMEVCNTR15_EL0, + SPMEVTYPER0_EL0, + SPMEVTYPER1_EL0, + SPMEVTYPER2_EL0, + SPMEVTYPER3_EL0, + SPMEVTYPER4_EL0, + SPMEVTYPER5_EL0, + SPMEVTYPER6_EL0, + SPMEVTYPER7_EL0, + SPMEVTYPER8_EL0, + SPMEVTYPER9_EL0, + SPMEVTYPER10_EL0, + SPMEVTYPER11_EL0, + SPMEVTYPER12_EL0, + SPMEVTYPER13_EL0, + SPMEVTYPER14_EL0, + SPMEVTYPER15_EL0, + SPMEVFILTR0_EL0, + SPMEVFILTR1_EL0, + SPMEVFILTR2_EL0, + SPMEVFILTR3_EL0, + SPMEVFILTR4_EL0, + SPMEVFILTR5_EL0, + SPMEVFILTR6_EL0, + SPMEVFILTR7_EL0, + SPMEVFILTR8_EL0, + SPMEVFILTR9_EL0, + SPMEVFILTR10_EL0, + SPMEVFILTR11_EL0, + SPMEVFILTR12_EL0, + SPMEVFILTR13_EL0, + SPMEVFILTR14_EL0, + SPMEVFILTR15_EL0, + SPMEVFILT2R0_EL0, + SPMEVFILT2R1_EL0, + SPMEVFILT2R2_EL0, + SPMEVFILT2R3_EL0, + SPMEVFILT2R4_EL0, + SPMEVFILT2R5_EL0, + SPMEVFILT2R6_EL0, + SPMEVFILT2R7_EL0, + SPMEVFILT2R8_EL0, + SPMEVFILT2R9_EL0, + SPMEVFILT2R10_EL0, + SPMEVFILT2R11_EL0, + SPMEVFILT2R12_EL0, + SPMEVFILT2R13_EL0, + SPMEVFILT2R14_EL0, + SPMEVFILT2R15_EL0, + DBGVCR32_EL2, + BRBCR_EL2, + SPMACCESSR_EL2, + BRBCR_EL12, + SPMACCESSR_EL12, + SPMACCESSR_EL3, + SPMROOTCR_EL3, + SPMSCR_EL1, + MIDR_EL1, + MPUIR_EL1, + MPIDR_EL1, + REVIDR_EL1, + ID_PFR0_EL1, + ID_PFR1_EL1, + ID_DFR0_EL1, + ID_AFR0_EL1, + ID_MMFR0_EL1, + ID_MMFR1_EL1, + ID_MMFR2_EL1, + ID_MMFR3_EL1, + ID_ISAR0_EL1, + ID_ISAR1_EL1, + ID_ISAR2_EL1, + ID_ISAR3_EL1, + ID_ISAR4_EL1, + ID_ISAR5_EL1, + ID_MMFR4_EL1, + ID_ISAR6_EL1, + MVFR0_EL1, + MVFR1_EL1, + MVFR2_EL1, + ID_PFR2_EL1, + ID_DFR1_EL1, + ID_MMFR5_EL1, + ID_AA64PFR0_EL1, + ID_AA64PFR1_EL1, + ID_AA64PFR2_EL1, + ID_AA64ZFR0_EL1, + ID_AA64SMFR0_EL1, + ID_AA64FPFR0_EL1, + ID_AA64DFR0_EL1, + ID_AA64DFR1_EL1, + ID_AA64DFR2_EL1, + ID_AA64AFR0_EL1, + ID_AA64AFR1_EL1, + ID_AA64ISAR0_EL1, + ID_AA64ISAR1_EL1, + ID_AA64ISAR2_EL1, + ID_AA64ISAR3_EL1, + ID_AA64MMFR0_EL1, + ID_AA64MMFR1_EL1, + ID_AA64MMFR2_EL1, + ID_AA64MMFR3_EL1, + ID_AA64MMFR4_EL1, + SCTLR_EL1, + ACTLR_EL1, + CPACR_EL1, + SCTLR2_EL1, + RGSR_EL1, + GCR_EL1, + ZCR_EL1, + TRFCR_EL1, + TRCITECR_EL1, + SMPRI_EL1, + SMCR_EL1, + SCTLRMASK_EL1, + ACTLRMASK_EL1, + CPACRMASK_EL1, + SCTLR2MASK_EL1, + CPACRALIAS_EL1, + ACTLRALIAS_EL1, + SCTLRALIAS_EL1, + SCTLR2ALIAS_EL1, + TTBR0_EL1, + TTBR1_EL1, + TCR_EL1, + TCR2_EL1, + IRTBRU_EL1, + IRTBRP_EL1, + DPOTBR0_EL1, + DPOTBR1_EL1, + APIAKeyLo_EL1, + APIAKeyHi_EL1, + APIBKeyLo_EL1, + APIBKeyHi_EL1, + LDSTT_EL1, + APDAKeyLo_EL1, + APDAKeyHi_EL1, + APDBKeyLo_EL1, + APDBKeyHi_EL1, + TPMIN0_EL1, + TPMAX0_EL1, + TPMIN1_EL1, + TPMAX1_EL1, + APGAKeyLo_EL1, + APGAKeyHi_EL1, + GCSCR_EL1, + GCSPR_EL1, + GCSCRE0_EL1, + TCRMASK_EL1, + TCR2MASK_EL1, + TCRALIAS_EL1, + TCR2ALIAS_EL1, + FGDTP0_EL1, + FGDTP1_EL1, + FGDTP2_EL1, + FGDTP3_EL1, + FGDTP4_EL1, + FGDTP5_EL1, + FGDTP6_EL1, + FGDTP7_EL1, + FGDTP8_EL1, + FGDTP9_EL1, + FGDTP10_EL1, + FGDTP11_EL1, + FGDTP12_EL1, + FGDTP13_EL1, + FGDTP14_EL1, + FGDTP15_EL1, + FGDTU0_EL1, + FGDTU1_EL1, + FGDTU2_EL1, + FGDTU3_EL1, + FGDTU4_EL1, + FGDTU5_EL1, + FGDTU6_EL1, + FGDTU7_EL1, + FGDTU8_EL1, + FGDTU9_EL1, + FGDTU10_EL1, + FGDTU11_EL1, + FGDTU12_EL1, + FGDTU13_EL1, + FGDTU14_EL1, + FGDTU15_EL1, + AFGDTP0_EL1, + AFGDTP1_EL1, + AFGDTP2_EL1, + AFGDTP3_EL1, + AFGDTP4_EL1, + AFGDTP5_EL1, + AFGDTP6_EL1, + AFGDTP7_EL1, + AFGDTP8_EL1, + AFGDTP9_EL1, + AFGDTP10_EL1, + AFGDTP11_EL1, + AFGDTP12_EL1, + AFGDTP13_EL1, + AFGDTP14_EL1, + AFGDTP15_EL1, + AFGDTU0_EL1, + AFGDTU1_EL1, + AFGDTU2_EL1, + AFGDTU3_EL1, + AFGDTU4_EL1, + AFGDTU5_EL1, + AFGDTU6_EL1, + AFGDTU7_EL1, + AFGDTU8_EL1, + AFGDTU9_EL1, + AFGDTU10_EL1, + AFGDTU11_EL1, + AFGDTU12_EL1, + AFGDTU13_EL1, + AFGDTU14_EL1, + AFGDTU15_EL1, + SPSR_EL1, + ELR_EL1, + STINDEX_EL1, + TINDEX_EL1, + SP_EL0, + SPSel, + CurrentEL, + PAN, + UAO, + ALLINT, + PM, + ICC_PMR_EL1, + AFSR0_EL1, + AFSR1_EL1, + ESR_EL1, + ERRIDR_EL1, + ERRSELR_EL1, + ERXGSR_EL1, + ERXFR_EL1, + ERXCTLR_EL1, + ERXSTATUS_EL1, + ERXADDR_EL1, + ERXPFGF_EL1, + ERXPFGCTL_EL1, + ERXPFGCDN_EL1, + ERXMISC0_EL1, + ERXMISC1_EL1, + ERXMISC2_EL1, + ERXMISC3_EL1, + TFSR_EL1, + TFSRE0_EL1, + FAR_EL1, + PFAR_EL1, + PRENR_EL1, + PRSELR_EL1, + PRBAR_EL1, + PRLAR_EL1, + PRBAR1_EL1, + PRLAR1_EL1, + PRBAR2_EL1, + PRLAR2_EL1, + PRBAR3_EL1, + PRLAR3_EL1, + PRBAR4_EL1, + PRLAR4_EL1, + PRBAR5_EL1, + PRLAR5_EL1, + PRBAR6_EL1, + PRLAR6_EL1, + PRBAR7_EL1, + PRLAR7_EL1, + PRBAR8_EL1, + PRLAR8_EL1, + PRBAR9_EL1, + PRLAR9_EL1, + PRBAR10_EL1, + PRLAR10_EL1, + PRBAR11_EL1, + PRLAR11_EL1, + PRBAR12_EL1, + PRLAR12_EL1, + PRBAR13_EL1, + PRLAR13_EL1, + PRBAR14_EL1, + PRLAR14_EL1, + PRBAR15_EL1, + PRLAR15_EL1, + PAR_EL1, + PMSCR_EL1, + PMSNEVFR_EL1, + PMSICR_EL1, + PMSIRR_EL1, + PMSFCR_EL1, + PMSEVFR_EL1, + PMSLATFR_EL1, + PMSIDR_EL1, + PMBLIMITR_EL1, + PMBPTR_EL1, + PMBSR_EL1, + PMSDSFR_EL1, + PMBMAR_EL1, + PMBIDR_EL1, + TRBLIMITR_EL1, + TRBPTR_EL1, + TRBBASER_EL1, + TRBSR_EL1, + TRBMAR_EL1, + TRBMPAM_EL1, + TRBTRG_EL1, + TRBIDR_EL1, + PMSSCR_EL1, + PMINTENSET_EL1, + PMINTENCLR_EL1, + PMUACR_EL1, + PMECR_EL1, + PMMIR_EL1, + PMIAR_EL1, + MAIR_EL1, + MAIR2_EL1, + PIRE0_EL1, + PIR_EL1, + POR_EL1, + S2POR_EL1, + TTTBRU_EL1, + TTTBRP_EL1, + AMAIR_EL1, + AMAIR2_EL1, + LORSA_EL1, + LOREA_EL1, + LORN_EL1, + LORC_EL1, + MPAMIDR_EL1, + MPAMBWIDR_EL1, + TLBIDIDR_EL1, + LORID_EL1, + MPAM1_EL1, + MPAM0_EL1, + MPAMCTL_EL1, + MPAMSM_EL1, + MPAMBW1_EL1, + MPAMBW0_EL1, + MPAMBWSM_EL1, + VBAR_EL1, + RVBAR_EL1, + RMR_EL1, + ISR_EL1, + DISR_EL1, + ICC_IAR0_EL1, + ICC_EOIR0_EL1, + ICC_HPPIR0_EL1, + ICC_BPR0_EL1, + ICC_AP0R0_EL1, + ICC_AP0R1_EL1, + ICC_AP0R2_EL1, + ICC_AP0R3_EL1, + ICC_AP1R0_EL1, + ICC_AP1R1_EL1, + ICC_AP1R2_EL1, + ICC_AP1R3_EL1, + ICC_NMIAR1_EL1, + ICC_PPI_HMR0_EL1, + ICC_PPI_HMR1_EL1, + ICC_IDR0_EL1, + ICC_HPPIR_EL1, + ICC_ICSR_EL1, + ICC_IAFFIDR_EL1, + ICC_PPI_ENABLER0_EL1, + ICC_PPI_ENABLER1_EL1, + ICC_DIR_EL1, + ICC_RPR_EL1, + ICC_SGI1R_EL1, + ICC_ASGI1R_EL1, + ICC_SGI0R_EL1, + ICC_IAR1_EL1, + ICC_EOIR1_EL1, + ICC_HPPIR1_EL1, + ICC_BPR1_EL1, + ICC_CTLR_EL1, + ICC_SRE_EL1, + ICC_IGRPEN0_EL1, + ICC_IGRPEN1_EL1, + ICC_PPI_CACTIVER0_EL1, + ICC_PPI_CACTIVER1_EL1, + ICC_PPI_SACTIVER0_EL1, + ICC_PPI_SACTIVER1_EL1, + ICC_PPI_CPENDR0_EL1, + ICC_PPI_CPENDR1_EL1, + ICC_PPI_SPENDR0_EL1, + ICC_PPI_SPENDR1_EL1, + ICC_PPI_PRIORITYR0_EL1, + ICC_PPI_PRIORITYR1_EL1, + ICC_PPI_PRIORITYR2_EL1, + ICC_PPI_PRIORITYR3_EL1, + ICC_PPI_PRIORITYR4_EL1, + ICC_PPI_PRIORITYR5_EL1, + ICC_PPI_PRIORITYR6_EL1, + ICC_PPI_PRIORITYR7_EL1, + ICC_PPI_PRIORITYR8_EL1, + ICC_PPI_PRIORITYR9_EL1, + ICC_PPI_PRIORITYR10_EL1, + ICC_PPI_PRIORITYR11_EL1, + ICC_PPI_PRIORITYR12_EL1, + ICC_PPI_PRIORITYR13_EL1, + ICC_PPI_PRIORITYR14_EL1, + ICC_PPI_PRIORITYR15_EL1, + TPIDR3_EL1, + CONTEXTIDR_EL1, + RCWSMASK_EL1, + TPIDR_EL1, + ACCDATA_EL1, + RCWMASK_EL1, + SCXTNUM_EL1, + CNTKCTL_EL1, + CCSIDR_EL1, + CLIDR_EL1, + CCSIDR2_EL1, + GMID_EL1, + SMIDR_EL1, + AIDR_EL1, + ICC_APR_EL1, + ICC_CR0_EL1, + ICC_PCR_EL1, + ICC_HAPR_EL1, + CSSELR_EL1, + CTR_EL0, + DCZID_EL0, + TPMIN0_EL0, + TPMAX0_EL0, + TPMIN1_EL0, + TPMAX1_EL0, + RNDR, + RNDRRS, + GCSPR_EL0, + TINDEX_EL0, + NZCV, + DAIF, + SVCR, + DIT, + SSBS, + TCO, + FPCR, + FPSR, + FPMR, + DSPSR_EL0, + DLR_EL0, + DPOCR_EL0, + PMICNTR_EL0, + PMICFILTR_EL0, + PMCR_EL0, + PMCNTENSET_EL0, + PMCNTENCLR_EL0, + PMOVSCLR_EL0, + PMSWINC_EL0, + PMSELR_EL0, + PMCEID0_EL0, + PMCEID1_EL0, + PMCCNTR_EL0, + PMXEVTYPER_EL0, + PMXEVCNTR_EL0, + PMZR_EL0, + PMUSERENR_EL0, + PMOVSSET_EL0, + POR_EL0, + TPIDR3_EL0, + TPIDR_EL0, + TPIDRRO_EL0, + TPIDR2_EL0, + SCXTNUM_EL0, + AMCR_EL0, + AMCFGR_EL0, + AMCGCR_EL0, + AMUSERENR_EL0, + AMCNTENCLR0_EL0, + AMCNTENSET0_EL0, + AMCG1IDR_EL0, + AMCNTENCLR1_EL0, + AMCNTENSET1_EL0, + AMEVCNTR00_EL0, + AMEVCNTR01_EL0, + AMEVCNTR02_EL0, + AMEVCNTR03_EL0, + AMEVTYPER00_EL0, + AMEVTYPER01_EL0, + AMEVTYPER02_EL0, + AMEVTYPER03_EL0, + AMEVCNTR10_EL0, + AMEVCNTR11_EL0, + AMEVCNTR12_EL0, + AMEVCNTR13_EL0, + AMEVCNTR14_EL0, + AMEVCNTR15_EL0, + AMEVCNTR16_EL0, + AMEVCNTR17_EL0, + AMEVCNTR18_EL0, + AMEVCNTR19_EL0, + AMEVCNTR110_EL0, + AMEVCNTR111_EL0, + AMEVCNTR112_EL0, + AMEVCNTR113_EL0, + AMEVCNTR114_EL0, + AMEVCNTR115_EL0, + AMEVTYPER10_EL0, + AMEVTYPER11_EL0, + AMEVTYPER12_EL0, + AMEVTYPER13_EL0, + AMEVTYPER14_EL0, + AMEVTYPER15_EL0, + AMEVTYPER16_EL0, + AMEVTYPER17_EL0, + AMEVTYPER18_EL0, + AMEVTYPER19_EL0, + AMEVTYPER110_EL0, + AMEVTYPER111_EL0, + AMEVTYPER112_EL0, + AMEVTYPER113_EL0, + AMEVTYPER114_EL0, + AMEVTYPER115_EL0, + CNTFRQ_EL0, + CNTPCT_EL0, + CNTVCT_EL0, + CNTPCTSS_EL0, + CNTVCTSS_EL0, + CNTP_TVAL_EL0, + CNTP_CTL_EL0, + CNTP_CVAL_EL0, + CNTV_TVAL_EL0, + CNTV_CTL_EL0, + CNTV_CVAL_EL0, + PMEVCNTR0_EL0, + PMEVCNTR1_EL0, + PMEVCNTR2_EL0, + PMEVCNTR3_EL0, + PMEVCNTR4_EL0, + PMEVCNTR5_EL0, + PMEVCNTR6_EL0, + PMEVCNTR7_EL0, + PMEVCNTR8_EL0, + PMEVCNTR9_EL0, + PMEVCNTR10_EL0, + PMEVCNTR11_EL0, + PMEVCNTR12_EL0, + PMEVCNTR13_EL0, + PMEVCNTR14_EL0, + PMEVCNTR15_EL0, + PMEVCNTR16_EL0, + PMEVCNTR17_EL0, + PMEVCNTR18_EL0, + PMEVCNTR19_EL0, + PMEVCNTR20_EL0, + PMEVCNTR21_EL0, + PMEVCNTR22_EL0, + PMEVCNTR23_EL0, + PMEVCNTR24_EL0, + PMEVCNTR25_EL0, + PMEVCNTR26_EL0, + PMEVCNTR27_EL0, + PMEVCNTR28_EL0, + PMEVCNTR29_EL0, + PMEVCNTR30_EL0, + PMEVTYPER0_EL0, + PMEVTYPER1_EL0, + PMEVTYPER2_EL0, + PMEVTYPER3_EL0, + PMEVTYPER4_EL0, + PMEVTYPER5_EL0, + PMEVTYPER6_EL0, + PMEVTYPER7_EL0, + PMEVTYPER8_EL0, + PMEVTYPER9_EL0, + PMEVTYPER10_EL0, + PMEVTYPER11_EL0, + PMEVTYPER12_EL0, + PMEVTYPER13_EL0, + PMEVTYPER14_EL0, + PMEVTYPER15_EL0, + PMEVTYPER16_EL0, + PMEVTYPER17_EL0, + PMEVTYPER18_EL0, + PMEVTYPER19_EL0, + PMEVTYPER20_EL0, + PMEVTYPER21_EL0, + PMEVTYPER22_EL0, + PMEVTYPER23_EL0, + PMEVTYPER24_EL0, + PMEVTYPER25_EL0, + PMEVTYPER26_EL0, + PMEVTYPER27_EL0, + PMEVTYPER28_EL0, + PMEVTYPER29_EL0, + PMEVTYPER30_EL0, + PMCCFILTR_EL0, + VPIDR_EL2, + MPUIR_EL2, + VMPIDR_EL2, + SCTLR_EL2, + ACTLR_EL2, + SCTLR2_EL2, + HCR_EL2, + MDCR_EL2, + CPTR_EL2, + HSTR_EL2, + HFGRTR_EL2, + HFGWTR_EL2, + HFGITR_EL2, + HACR_EL2, + ZCR_EL2, + TRFCR_EL2, + HCRX_EL2, + TRCITECR_EL2, + SMPRIMAP_EL2, + SMCR_EL2, + SDER32_EL2, + SCTLRMASK_EL2, + ACTLRMASK_EL2, + CPTRMASK_EL2, + SCTLR2MASK_EL2, + NVHCR_EL2, + NVHCRX_EL2, + NVHCRMASK_EL2, + NVHCRXMASK_EL2, + HCRMASK_EL2, + HCRXMASK_EL2, + TTBR0_EL2, + TTBR1_EL2, + TCR_EL2, + TCR2_EL2, + IRTBRU_EL2, + IRTBRP_EL2, + DPOTBR0_EL2, + DPOTBR1_EL2, + VTTBR_EL2, + VTCR_EL2, + LDSTT_EL2, + VNCR_EL2, + VNCCR_EL2, + TPMIN0_EL2, + TPMAX0_EL2, + TPMIN1_EL2, + TPMAX1_EL2, + HDBSSBR_EL2, + HDBSSPROD_EL2, + HACDBSBR_EL2, + HACDBSCONS_EL2, + GCSCR_EL2, + GCSPR_EL2, + VSTTBR_EL2, + VSTCR_EL2, + TCRMASK_EL2, + TCR2MASK_EL2, + VTLBID0_EL2, + VTLBID1_EL2, + VTLBID2_EL2, + VTLBID3_EL2, + VTLBIDOS0_EL2, + VTLBIDOS1_EL2, + VTLBIDOS2_EL2, + VTLBIDOS3_EL2, + DACR32_EL2, + HDFGRTR2_EL2, + HDFGWTR2_EL2, + HFGRTR2_EL2, + HFGWTR2_EL2, + HDFGRTR_EL2, + HDFGWTR_EL2, + HAFGRTR_EL2, + HFGITR2_EL2, + FGDTP0_EL2, + FGDTP1_EL2, + FGDTP2_EL2, + FGDTP3_EL2, + FGDTP4_EL2, + FGDTP5_EL2, + FGDTP6_EL2, + FGDTP7_EL2, + FGDTP8_EL2, + FGDTP9_EL2, + FGDTP10_EL2, + FGDTP11_EL2, + FGDTP12_EL2, + FGDTP13_EL2, + FGDTP14_EL2, + FGDTP15_EL2, + FGDTU0_EL2, + FGDTU1_EL2, + FGDTU2_EL2, + FGDTU3_EL2, + FGDTU4_EL2, + FGDTU5_EL2, + FGDTU6_EL2, + FGDTU7_EL2, + FGDTU8_EL2, + FGDTU9_EL2, + FGDTU10_EL2, + FGDTU11_EL2, + FGDTU12_EL2, + FGDTU13_EL2, + FGDTU14_EL2, + FGDTU15_EL2, + AFGDTP0_EL2, + AFGDTP1_EL2, + AFGDTP2_EL2, + AFGDTP3_EL2, + AFGDTP4_EL2, + AFGDTP5_EL2, + AFGDTP6_EL2, + AFGDTP7_EL2, + AFGDTP8_EL2, + AFGDTP9_EL2, + AFGDTP10_EL2, + AFGDTP11_EL2, + AFGDTP12_EL2, + AFGDTP13_EL2, + AFGDTP14_EL2, + AFGDTP15_EL2, + AFGDTU0_EL2, + AFGDTU1_EL2, + AFGDTU2_EL2, + AFGDTU3_EL2, + AFGDTU4_EL2, + AFGDTU5_EL2, + AFGDTU6_EL2, + AFGDTU7_EL2, + AFGDTU8_EL2, + AFGDTU9_EL2, + AFGDTU10_EL2, + AFGDTU11_EL2, + AFGDTU12_EL2, + AFGDTU13_EL2, + AFGDTU14_EL2, + AFGDTU15_EL2, + SPSR_EL2, + ELR_EL2, + STINDEX_EL2, + TINDEX_EL2, + SP_EL1, + SPSR_irq, + SPSR_abt, + SPSR_und, + SPSR_fiq, + IFSR32_EL2, + AFSR0_EL2, + AFSR1_EL2, + ESR_EL2, + VSESR_EL2, + FPEXC32_EL2, + TFSR_EL2, + FAR_EL2, + HPFAR_EL2, + PFAR_EL2, + PRENR_EL2, + PRSELR_EL2, + PRBAR_EL2, + PRLAR_EL2, + PRBAR1_EL2, + PRLAR1_EL2, + PRBAR2_EL2, + PRLAR2_EL2, + PRBAR3_EL2, + PRLAR3_EL2, + PRBAR4_EL2, + PRLAR4_EL2, + PRBAR5_EL2, + PRLAR5_EL2, + PRBAR6_EL2, + PRLAR6_EL2, + PRBAR7_EL2, + PRLAR7_EL2, + PRBAR8_EL2, + PRLAR8_EL2, + PRBAR9_EL2, + PRLAR9_EL2, + PRBAR10_EL2, + PRLAR10_EL2, + PRBAR11_EL2, + PRLAR11_EL2, + PRBAR12_EL2, + PRLAR12_EL2, + PRBAR13_EL2, + PRLAR13_EL2, + PRBAR14_EL2, + PRLAR14_EL2, + PRBAR15_EL2, + PRLAR15_EL2, + PMSCR_EL2, + PMBSR_EL2, + TRBSR_EL2, + MAIR2_EL2, + MAIR_EL2, + PIRE0_EL2, + PIR_EL2, + POR_EL2, + S2PIR_EL2, + TTTBRU_EL2, + TTTBRP_EL2, + AMAIR_EL2, + AMAIR2_EL2, + MPAMHCR_EL2, + MPAMVPMV_EL2, + MPAM2_EL2, + MPAMCTL_EL2, + MPAMBW2_EL2, + MPAMBWCAP_EL2, + MPAMVPM0_EL2, + MPAMVPM1_EL2, + MPAMVPM2_EL2, + MPAMVPM3_EL2, + MPAMVPM4_EL2, + MPAMVPM5_EL2, + MPAMVPM6_EL2, + MPAMVPM7_EL2, + MPAMVIDCR_EL2, + MPAMVIDSR_EL2, + MECID_P0_EL2, + MECID_A0_EL2, + MECID_P1_EL2, + MECID_A1_EL2, + MECIDR_EL2, + VMECID_P_EL2, + VMECID_A_EL2, + VBAR_EL2, + RVBAR_EL2, + RMR_EL2, + VDISR_EL2, + ICH_AP0R0_EL2, + ICH_AP0R1_EL2, + ICH_AP0R2_EL2, + ICH_AP0R3_EL2, + ICH_APR_EL2, + ICH_HPPIR_EL2, + ICH_AP1R0_EL2, + ICH_AP1R1_EL2, + ICH_AP1R2_EL2, + ICH_AP1R3_EL2, + ICH_HFGRTR_EL2, + ICC_SRE_EL2, + ICH_HFGWTR_EL2, + ICH_HFGITR_EL2, + ICH_PPI_DVIR0_EL2, + ICH_PPI_DVIR1_EL2, + ICH_PPI_ENABLER0_EL2, + ICH_PPI_ENABLER1_EL2, + ICH_PPI_PENDR0_EL2, + ICH_PPI_PENDR1_EL2, + ICH_PPI_ACTIVER0_EL2, + ICH_PPI_ACTIVER1_EL2, + ICH_HCR_EL2, + ICH_VTR_EL2, + ICH_MISR_EL2, + ICH_EISR_EL2, + ICH_VCTLR_EL2, + ICH_ELRSR_EL2, + ICH_CONTEXTR_EL2, + ICH_VMCR_EL2, + ICH_LR0_EL2, + ICH_LR1_EL2, + ICH_LR2_EL2, + ICH_LR3_EL2, + ICH_LR4_EL2, + ICH_LR5_EL2, + ICH_LR6_EL2, + ICH_LR7_EL2, + ICH_LR8_EL2, + ICH_LR9_EL2, + ICH_LR10_EL2, + ICH_LR11_EL2, + ICH_LR12_EL2, + ICH_LR13_EL2, + ICH_LR14_EL2, + ICH_LR15_EL2, + ICH_PPI_PRIORITYR0_EL2, + ICH_PPI_PRIORITYR1_EL2, + ICH_PPI_PRIORITYR2_EL2, + ICH_PPI_PRIORITYR3_EL2, + ICH_PPI_PRIORITYR4_EL2, + ICH_PPI_PRIORITYR5_EL2, + ICH_PPI_PRIORITYR6_EL2, + ICH_PPI_PRIORITYR7_EL2, + ICH_PPI_PRIORITYR8_EL2, + ICH_PPI_PRIORITYR9_EL2, + ICH_PPI_PRIORITYR10_EL2, + ICH_PPI_PRIORITYR11_EL2, + ICH_PPI_PRIORITYR12_EL2, + ICH_PPI_PRIORITYR13_EL2, + ICH_PPI_PRIORITYR14_EL2, + ICH_PPI_PRIORITYR15_EL2, + TPIDR3_EL2, + CONTEXTIDR_EL2, + TPIDR_EL2, + SCXTNUM_EL2, + AMEVCNTVOFF00_EL2, + AMEVCNTVOFF01_EL2, + AMEVCNTVOFF02_EL2, + AMEVCNTVOFF03_EL2, + AMEVCNTVOFF04_EL2, + AMEVCNTVOFF05_EL2, + AMEVCNTVOFF06_EL2, + AMEVCNTVOFF07_EL2, + AMEVCNTVOFF08_EL2, + AMEVCNTVOFF09_EL2, + AMEVCNTVOFF010_EL2, + AMEVCNTVOFF011_EL2, + AMEVCNTVOFF012_EL2, + AMEVCNTVOFF013_EL2, + AMEVCNTVOFF014_EL2, + AMEVCNTVOFF015_EL2, + AMEVCNTVOFF10_EL2, + AMEVCNTVOFF11_EL2, + AMEVCNTVOFF12_EL2, + AMEVCNTVOFF13_EL2, + AMEVCNTVOFF14_EL2, + AMEVCNTVOFF15_EL2, + AMEVCNTVOFF16_EL2, + AMEVCNTVOFF17_EL2, + AMEVCNTVOFF18_EL2, + AMEVCNTVOFF19_EL2, + AMEVCNTVOFF110_EL2, + AMEVCNTVOFF111_EL2, + AMEVCNTVOFF112_EL2, + AMEVCNTVOFF113_EL2, + AMEVCNTVOFF114_EL2, + AMEVCNTVOFF115_EL2, + CNTVOFF_EL2, + CNTSCALE_EL2, + CNTISCALE_EL2, + CNTPOFF_EL2, + CNTVFRQ_EL2, + CNTHCTL_EL2, + CNTHP_TVAL_EL2, + CNTHP_CTL_EL2, + CNTHP_CVAL_EL2, + CNTHV_TVAL_EL2, + CNTHV_CTL_EL2, + CNTHV_CVAL_EL2, + CNTHVS_TVAL_EL2, + CNTHVS_CTL_EL2, + CNTHVS_CVAL_EL2, + CNTHPS_TVAL_EL2, + CNTHPS_CTL_EL2, + CNTHPS_CVAL_EL2, + SCTLR_EL12, + ACTLR_EL12, + CPACR_EL12, + SCTLR2_EL12, + ZCR_EL12, + TRFCR_EL12, + TRCITECR_EL12, + SMCR_EL12, + SCTLRMASK_EL12, + ACTLRMASK_EL12, + CPACRMASK_EL12, + SCTLR2MASK_EL12, + TTBR0_EL12, + TTBR1_EL12, + TCR_EL12, + TCR2_EL12, + IRTBRU_EL12, + IRTBRP_EL12, + DPOTBR0_EL12, + DPOTBR1_EL12, + LDSTT_EL12, + TPMIN0_EL12, + TPMAX0_EL12, + TPMIN1_EL12, + TPMAX1_EL12, + GCSCR_EL12, + GCSPR_EL12, + TCRMASK_EL12, + TCR2MASK_EL12, + FGDTP0_EL12, + FGDTP1_EL12, + FGDTP2_EL12, + FGDTP3_EL12, + FGDTP4_EL12, + FGDTP5_EL12, + FGDTP6_EL12, + FGDTP7_EL12, + FGDTP8_EL12, + FGDTP9_EL12, + FGDTP10_EL12, + FGDTP11_EL12, + FGDTP12_EL12, + FGDTP13_EL12, + FGDTP14_EL12, + FGDTP15_EL12, + FGDTU0_EL12, + FGDTU1_EL12, + FGDTU2_EL12, + FGDTU3_EL12, + FGDTU4_EL12, + FGDTU5_EL12, + FGDTU6_EL12, + FGDTU7_EL12, + FGDTU8_EL12, + FGDTU9_EL12, + FGDTU10_EL12, + FGDTU11_EL12, + FGDTU12_EL12, + FGDTU13_EL12, + FGDTU14_EL12, + FGDTU15_EL12, + AFGDTP0_EL12, + AFGDTP1_EL12, + AFGDTP2_EL12, + AFGDTP3_EL12, + AFGDTP4_EL12, + AFGDTP5_EL12, + AFGDTP6_EL12, + AFGDTP7_EL12, + AFGDTP8_EL12, + AFGDTP9_EL12, + AFGDTP10_EL12, + AFGDTP11_EL12, + AFGDTP12_EL12, + AFGDTP13_EL12, + AFGDTP14_EL12, + AFGDTP15_EL12, + AFGDTU0_EL12, + AFGDTU1_EL12, + AFGDTU2_EL12, + AFGDTU3_EL12, + AFGDTU4_EL12, + AFGDTU5_EL12, + AFGDTU6_EL12, + AFGDTU7_EL12, + AFGDTU8_EL12, + AFGDTU9_EL12, + AFGDTU10_EL12, + AFGDTU11_EL12, + AFGDTU12_EL12, + AFGDTU13_EL12, + AFGDTU14_EL12, + AFGDTU15_EL12, + SPSR_EL12, + ELR_EL12, + STINDEX_EL12, + TINDEX_EL12, + AFSR0_EL12, + AFSR1_EL12, + ESR_EL12, + TFSR_EL12, + FAR_EL12, + PFAR_EL12, + PMSCR_EL12, + PMBSR_EL12, + TRBSR_EL12, + MAIR_EL12, + MAIR2_EL12, + PIRE0_EL12, + PIR_EL12, + POR_EL12, + TTTBRU_EL12, + TTTBRP_EL12, + AMAIR_EL12, + AMAIR2_EL12, + MPAM1_EL12, + MPAMCTL_EL12, + MPAMBW1_EL12, + VBAR_EL12, + TPIDR3_EL12, + CONTEXTIDR_EL12, + SCXTNUM_EL12, + CNTKCTL_EL12, + CNTP_TVAL_EL02, + CNTP_CTL_EL02, + CNTP_CVAL_EL02, + CNTV_TVAL_EL02, + CNTV_CTL_EL02, + CNTV_CVAL_EL02, + SCTLR_EL3, + ACTLR_EL3, + SCTLR2_EL3, + SCR_EL3, + SDER32_EL3, + CPTR_EL3, + FGWTE3_EL3, + ZCR_EL3, + SMCR_EL3, + MDCR_EL3, + TTBR0_EL3, + TCR_EL3, + IRTBRP_EL3, + DPOTBR0_EL3, + GPTBR_EL3, + GPCBW_EL3, + GPCCR_EL3, + GCSCR_EL3, + GCSPR_EL3, + FGDTP0_EL3, + FGDTP1_EL3, + FGDTP2_EL3, + FGDTP3_EL3, + FGDTP4_EL3, + FGDTP5_EL3, + FGDTP6_EL3, + FGDTP7_EL3, + FGDTP8_EL3, + FGDTP9_EL3, + FGDTP10_EL3, + FGDTP11_EL3, + FGDTP12_EL3, + FGDTP13_EL3, + FGDTP14_EL3, + FGDTP15_EL3, + AFGDTP0_EL3, + AFGDTP1_EL3, + AFGDTP2_EL3, + AFGDTP3_EL3, + AFGDTP4_EL3, + AFGDTP5_EL3, + AFGDTP6_EL3, + AFGDTP7_EL3, + AFGDTP8_EL3, + AFGDTP9_EL3, + AFGDTP10_EL3, + AFGDTP11_EL3, + AFGDTP12_EL3, + AFGDTP13_EL3, + AFGDTP14_EL3, + AFGDTP15_EL3, + SPSR_EL3, + ELR_EL3, + STINDEX_EL3, + TINDEX_EL3, + SP_EL2, + AFSR0_EL3, + AFSR1_EL3, + ESR_EL3, + VSESR_EL3, + TFSR_EL3, + FAR_EL3, + MFAR_EL3, + PMBSR_EL3, + TRBSR_EL3, + MAIR2_EL3, + MAIR_EL3, + PIR_EL3, + POR_EL3, + TTTBRP_EL3, + AMAIR_EL3, + AMAIR2_EL3, + MPAM3_EL3, + MPAMCTL_EL3, + MPAMBW3_EL3, + MPAMVIDSR_EL3, + MECID_RL_A_EL3, + VBAR_EL3, + RVBAR_EL3, + RMR_EL3, + VDISR_EL3, + ICC_APR_EL3, + ICC_PCR_EL3, + ICC_DOMHPPIR_EL3, + ICC_PPI_DOMAINR0_EL3, + ICC_PPI_DOMAINR1_EL3, + ICC_PPI_DOMAINR2_EL3, + ICC_PPI_DOMAINR3_EL3, + ICC_CR0_EL3, + ICC_HPPIR_EL3, + ICC_CTLR_EL3, + ICC_SRE_EL3, + ICC_IGRPEN1_EL3, + TPIDR3_EL3, + TPIDR_EL3, + SCXTNUM_EL3, + CNTPS_TVAL_EL1, + CNTPS_CTL_EL1, + CNTPS_CVAL_EL1, + NUM_TARGET_SYSREGS, + UNKNOWN(u64), +} + +impl From for SysReg { + fn from(value: u64) -> Self { + match value { + 32770 => SysReg::OSDTRRX_EL1, + 32772 => SysReg::DBGBVR0_EL1, + 32773 => SysReg::DBGBCR0_EL1, + 32774 => SysReg::DBGWVR0_EL1, + 32775 => SysReg::DBGWCR0_EL1, + 32780 => SysReg::DBGBVR1_EL1, + 32781 => SysReg::DBGBCR1_EL1, + 32782 => SysReg::DBGWVR1_EL1, + 32783 => SysReg::DBGWCR1_EL1, + 32784 => SysReg::MDCCINT_EL1, + 32786 => SysReg::MDSCR_EL1, + 32788 => SysReg::DBGBVR2_EL1, + 32789 => SysReg::DBGBCR2_EL1, + 32790 => SysReg::DBGWVR2_EL1, + 32791 => SysReg::DBGWCR2_EL1, + 32794 => SysReg::OSDTRTX_EL1, + 32796 => SysReg::DBGBVR3_EL1, + 32797 => SysReg::DBGBCR3_EL1, + 32798 => SysReg::DBGWVR3_EL1, + 32799 => SysReg::DBGWCR3_EL1, + 32802 => SysReg::MDSELR_EL1, + 32804 => SysReg::DBGBVR4_EL1, + 32805 => SysReg::DBGBCR4_EL1, + 32806 => SysReg::DBGWVR4_EL1, + 32807 => SysReg::DBGWCR4_EL1, + 32810 => SysReg::MDSTEPOP_EL1, + 32812 => SysReg::DBGBVR5_EL1, + 32813 => SysReg::DBGBCR5_EL1, + 32814 => SysReg::DBGWVR5_EL1, + 32815 => SysReg::DBGWCR5_EL1, + 32818 => SysReg::OSECCR_EL1, + 32820 => SysReg::DBGBVR6_EL1, + 32821 => SysReg::DBGBCR6_EL1, + 32822 => SysReg::DBGWVR6_EL1, + 32823 => SysReg::DBGWCR6_EL1, + 32828 => SysReg::DBGBVR7_EL1, + 32829 => SysReg::DBGBCR7_EL1, + 32830 => SysReg::DBGWVR7_EL1, + 32831 => SysReg::DBGWCR7_EL1, + 32836 => SysReg::DBGBVR8_EL1, + 32837 => SysReg::DBGBCR8_EL1, + 32838 => SysReg::DBGWVR8_EL1, + 32839 => SysReg::DBGWCR8_EL1, + 32844 => SysReg::DBGBVR9_EL1, + 32845 => SysReg::DBGBCR9_EL1, + 32846 => SysReg::DBGWVR9_EL1, + 32847 => SysReg::DBGWCR9_EL1, + 32852 => SysReg::DBGBVR10_EL1, + 32853 => SysReg::DBGBCR10_EL1, + 32854 => SysReg::DBGWVR10_EL1, + 32855 => SysReg::DBGWCR10_EL1, + 32860 => SysReg::DBGBVR11_EL1, + 32861 => SysReg::DBGBCR11_EL1, + 32862 => SysReg::DBGWVR11_EL1, + 32863 => SysReg::DBGWCR11_EL1, + 32868 => SysReg::DBGBVR12_EL1, + 32869 => SysReg::DBGBCR12_EL1, + 32870 => SysReg::DBGWVR12_EL1, + 32871 => SysReg::DBGWCR12_EL1, + 32876 => SysReg::DBGBVR13_EL1, + 32877 => SysReg::DBGBCR13_EL1, + 32878 => SysReg::DBGWVR13_EL1, + 32879 => SysReg::DBGWCR13_EL1, + 32884 => SysReg::DBGBVR14_EL1, + 32885 => SysReg::DBGBCR14_EL1, + 32886 => SysReg::DBGWVR14_EL1, + 32887 => SysReg::DBGWCR14_EL1, + 32892 => SysReg::DBGBVR15_EL1, + 32893 => SysReg::DBGBCR15_EL1, + 32894 => SysReg::DBGWVR15_EL1, + 32895 => SysReg::DBGWCR15_EL1, + 32896 => SysReg::MDRAR_EL1, + 32900 => SysReg::OSLAR_EL1, + 32908 => SysReg::OSLSR_EL1, + 32924 => SysReg::OSDLR_EL1, + 32932 => SysReg::DBGPRCR_EL1, + 33734 => SysReg::DBGCLAIMSET_EL1, + 33742 => SysReg::DBGCLAIMCLR_EL1, + 33782 => SysReg::DBGAUTHSTATUS_EL1, + 34024 => SysReg::SPMCGCR0_EL1, + 34025 => SysReg::SPMCGCR1_EL1, + 34027 => SysReg::SPMACCESSR_EL1, + 34028 => SysReg::SPMIIDR_EL1, + 34029 => SysReg::SPMDEVARCH_EL1, + 34030 => SysReg::SPMDEVAFF_EL1, + 34031 => SysReg::SPMCFGR_EL1, + 34033 => SysReg::SPMINTENSET_EL1, + 34034 => SysReg::SPMINTENCLR_EL1, + 34624 => SysReg::PMEVCNTSVR0_EL1, + 34625 => SysReg::PMEVCNTSVR1_EL1, + 34626 => SysReg::PMEVCNTSVR2_EL1, + 34627 => SysReg::PMEVCNTSVR3_EL1, + 34628 => SysReg::PMEVCNTSVR4_EL1, + 34629 => SysReg::PMEVCNTSVR5_EL1, + 34630 => SysReg::PMEVCNTSVR6_EL1, + 34631 => SysReg::PMEVCNTSVR7_EL1, + 34632 => SysReg::PMEVCNTSVR8_EL1, + 34633 => SysReg::PMEVCNTSVR9_EL1, + 34634 => SysReg::PMEVCNTSVR10_EL1, + 34635 => SysReg::PMEVCNTSVR11_EL1, + 34636 => SysReg::PMEVCNTSVR12_EL1, + 34637 => SysReg::PMEVCNTSVR13_EL1, + 34638 => SysReg::PMEVCNTSVR14_EL1, + 34639 => SysReg::PMEVCNTSVR15_EL1, + 34640 => SysReg::PMEVCNTSVR16_EL1, + 34641 => SysReg::PMEVCNTSVR17_EL1, + 34642 => SysReg::PMEVCNTSVR18_EL1, + 34643 => SysReg::PMEVCNTSVR19_EL1, + 34644 => SysReg::PMEVCNTSVR20_EL1, + 34645 => SysReg::PMEVCNTSVR21_EL1, + 34646 => SysReg::PMEVCNTSVR22_EL1, + 34647 => SysReg::PMEVCNTSVR23_EL1, + 34648 => SysReg::PMEVCNTSVR24_EL1, + 34649 => SysReg::PMEVCNTSVR25_EL1, + 34650 => SysReg::PMEVCNTSVR26_EL1, + 34651 => SysReg::PMEVCNTSVR27_EL1, + 34652 => SysReg::PMEVCNTSVR28_EL1, + 34653 => SysReg::PMEVCNTSVR29_EL1, + 34654 => SysReg::PMEVCNTSVR30_EL1, + 34655 => SysReg::PMCCNTSVR_EL1, + 34656 => SysReg::PMICNTSVR_EL1, + 34817 => SysReg::TRCTRACEIDR, + 34818 => SysReg::TRCVICTLR, + 34820 => SysReg::TRCSEQEVR0, + 34821 => SysReg::TRCCNTRLDVR0, + 34822 => SysReg::TRCIDR8, + 34823 => SysReg::TRCIMSPEC0, + 34824 => SysReg::TRCPRGCTLR, + 34825 => SysReg::TRCQCTLR, + 34826 => SysReg::TRCVIIECTLR, + 34828 => SysReg::TRCSEQEVR1, + 34829 => SysReg::TRCCNTRLDVR1, + 34830 => SysReg::TRCIDR9, + 34831 => SysReg::TRCIMSPEC1, + 34832 => SysReg::TRCPROCSELR, + 34833 => SysReg::TRCITEEDCR, + 34834 => SysReg::TRCVISSCTLR, + 34836 => SysReg::TRCSEQEVR2, + 34837 => SysReg::TRCCNTRLDVR2, + 34838 => SysReg::TRCIDR10, + 34839 => SysReg::TRCIMSPEC2, + 34840 => SysReg::TRCSTATR, + 34842 => SysReg::TRCVIPCSSCTLR, + 34845 => SysReg::TRCCNTRLDVR3, + 34846 => SysReg::TRCIDR11, + 34847 => SysReg::TRCIMSPEC3, + 34848 => SysReg::TRCCONFIGR, + 34853 => SysReg::TRCCNTCTLR0, + 34854 => SysReg::TRCIDR12, + 34855 => SysReg::TRCIMSPEC4, + 34861 => SysReg::TRCCNTCTLR1, + 34862 => SysReg::TRCIDR13, + 34863 => SysReg::TRCIMSPEC5, + 34864 => SysReg::TRCAUXCTLR, + 34868 => SysReg::TRCSEQRSTEVR, + 34869 => SysReg::TRCCNTCTLR2, + 34871 => SysReg::TRCIMSPEC6, + 34876 => SysReg::TRCSEQSTR, + 34877 => SysReg::TRCCNTCTLR3, + 34879 => SysReg::TRCIMSPEC7, + 34880 => SysReg::TRCEVENTCTL0R, + 34882 => SysReg::TRCVDCTLR, + 34884 => SysReg::TRCEXTINSELR, + 34885 => SysReg::TRCCNTVR0, + 34887 => SysReg::TRCIDR0, + 34888 => SysReg::TRCEVENTCTL1R, + 34890 => SysReg::TRCVDSACCTLR, + 34892 => SysReg::TRCEXTINSELR1, + 34893 => SysReg::TRCCNTVR1, + 34895 => SysReg::TRCIDR1, + 34896 => SysReg::TRCRSR, + 34898 => SysReg::TRCVDARCCTLR, + 34900 => SysReg::TRCEXTINSELR2, + 34901 => SysReg::TRCCNTVR2, + 34903 => SysReg::TRCIDR2, + 34904 => SysReg::TRCSTALLCTLR, + 34908 => SysReg::TRCEXTINSELR3, + 34909 => SysReg::TRCCNTVR3, + 34911 => SysReg::TRCIDR3, + 34912 => SysReg::TRCTSCTLR, + 34919 => SysReg::TRCIDR4, + 34920 => SysReg::TRCSYNCPR, + 34927 => SysReg::TRCIDR5, + 34928 => SysReg::TRCCCCTLR, + 34935 => SysReg::TRCIDR6, + 34936 => SysReg::TRCBBCTLR, + 34943 => SysReg::TRCIDR7, + 34945 => SysReg::TRCRSCTLR16, + 34946 => SysReg::TRCSSCCR0, + 34947 => SysReg::TRCSSPCICR0, + 34948 => SysReg::TRCOSLAR, + 34953 => SysReg::TRCRSCTLR17, + 34954 => SysReg::TRCSSCCR1, + 34955 => SysReg::TRCSSPCICR1, + 34956 => SysReg::TRCOSLSR, + 34960 => SysReg::TRCRSCTLR2, + 34961 => SysReg::TRCRSCTLR18, + 34962 => SysReg::TRCSSCCR2, + 34963 => SysReg::TRCSSPCICR2, + 34968 => SysReg::TRCRSCTLR3, + 34969 => SysReg::TRCRSCTLR19, + 34970 => SysReg::TRCSSCCR3, + 34971 => SysReg::TRCSSPCICR3, + 34976 => SysReg::TRCRSCTLR4, + 34977 => SysReg::TRCRSCTLR20, + 34978 => SysReg::TRCSSCCR4, + 34979 => SysReg::TRCSSPCICR4, + 34980 => SysReg::TRCPDCR, + 34984 => SysReg::TRCRSCTLR5, + 34985 => SysReg::TRCRSCTLR21, + 34986 => SysReg::TRCSSCCR5, + 34987 => SysReg::TRCSSPCICR5, + 34988 => SysReg::TRCPDSR, + 34992 => SysReg::TRCRSCTLR6, + 34993 => SysReg::TRCRSCTLR22, + 34994 => SysReg::TRCSSCCR6, + 34995 => SysReg::TRCSSPCICR6, + 35000 => SysReg::TRCRSCTLR7, + 35001 => SysReg::TRCRSCTLR23, + 35002 => SysReg::TRCSSCCR7, + 35003 => SysReg::TRCSSPCICR7, + 35008 => SysReg::TRCRSCTLR8, + 35009 => SysReg::TRCRSCTLR24, + 35010 => SysReg::TRCSSCSR0, + 35016 => SysReg::TRCRSCTLR9, + 35017 => SysReg::TRCRSCTLR25, + 35018 => SysReg::TRCSSCSR1, + 35024 => SysReg::TRCRSCTLR10, + 35025 => SysReg::TRCRSCTLR26, + 35026 => SysReg::TRCSSCSR2, + 35032 => SysReg::TRCRSCTLR11, + 35033 => SysReg::TRCRSCTLR27, + 35034 => SysReg::TRCSSCSR3, + 35040 => SysReg::TRCRSCTLR12, + 35041 => SysReg::TRCRSCTLR28, + 35042 => SysReg::TRCSSCSR4, + 35048 => SysReg::TRCRSCTLR13, + 35049 => SysReg::TRCRSCTLR29, + 35050 => SysReg::TRCSSCSR5, + 35056 => SysReg::TRCRSCTLR14, + 35057 => SysReg::TRCRSCTLR30, + 35058 => SysReg::TRCSSCSR6, + 35064 => SysReg::TRCRSCTLR15, + 35065 => SysReg::TRCRSCTLR31, + 35066 => SysReg::TRCSSCSR7, + 35072 => SysReg::TRCACVR0, + 35073 => SysReg::TRCACVR8, + 35074 => SysReg::TRCACATR0, + 35075 => SysReg::TRCACATR8, + 35076 => SysReg::TRCDVCVR0, + 35077 => SysReg::TRCDVCVR4, + 35078 => SysReg::TRCDVCMR0, + 35079 => SysReg::TRCDVCMR4, + 35088 => SysReg::TRCACVR1, + 35089 => SysReg::TRCACVR9, + 35090 => SysReg::TRCACATR1, + 35091 => SysReg::TRCACATR9, + 35104 => SysReg::TRCACVR2, + 35105 => SysReg::TRCACVR10, + 35106 => SysReg::TRCACATR2, + 35107 => SysReg::TRCACATR10, + 35108 => SysReg::TRCDVCVR1, + 35109 => SysReg::TRCDVCVR5, + 35110 => SysReg::TRCDVCMR1, + 35111 => SysReg::TRCDVCMR5, + 35120 => SysReg::TRCACVR3, + 35121 => SysReg::TRCACVR11, + 35122 => SysReg::TRCACATR3, + 35123 => SysReg::TRCACATR11, + 35136 => SysReg::TRCACVR4, + 35137 => SysReg::TRCACVR12, + 35138 => SysReg::TRCACATR4, + 35139 => SysReg::TRCACATR12, + 35140 => SysReg::TRCDVCVR2, + 35141 => SysReg::TRCDVCVR6, + 35142 => SysReg::TRCDVCMR2, + 35143 => SysReg::TRCDVCMR6, + 35152 => SysReg::TRCACVR5, + 35153 => SysReg::TRCACVR13, + 35154 => SysReg::TRCACATR5, + 35155 => SysReg::TRCACATR13, + 35168 => SysReg::TRCACVR6, + 35169 => SysReg::TRCACVR14, + 35170 => SysReg::TRCACATR6, + 35171 => SysReg::TRCACATR14, + 35172 => SysReg::TRCDVCVR3, + 35173 => SysReg::TRCDVCVR7, + 35174 => SysReg::TRCDVCMR3, + 35175 => SysReg::TRCDVCMR7, + 35184 => SysReg::TRCACVR7, + 35185 => SysReg::TRCACVR15, + 35186 => SysReg::TRCACATR7, + 35187 => SysReg::TRCACATR15, + 35200 => SysReg::TRCCIDCVR0, + 35201 => SysReg::TRCVMIDCVR0, + 35202 => SysReg::TRCCIDCCTLR0, + 35210 => SysReg::TRCCIDCCTLR1, + 35216 => SysReg::TRCCIDCVR1, + 35217 => SysReg::TRCVMIDCVR1, + 35218 => SysReg::TRCVMIDCCTLR0, + 35226 => SysReg::TRCVMIDCCTLR1, + 35232 => SysReg::TRCCIDCVR2, + 35233 => SysReg::TRCVMIDCVR2, + 35248 => SysReg::TRCCIDCVR3, + 35249 => SysReg::TRCVMIDCVR3, + 35264 => SysReg::TRCCIDCVR4, + 35265 => SysReg::TRCVMIDCVR4, + 35280 => SysReg::TRCCIDCVR5, + 35281 => SysReg::TRCVMIDCVR5, + 35296 => SysReg::TRCCIDCVR6, + 35297 => SysReg::TRCVMIDCVR6, + 35312 => SysReg::TRCCIDCVR7, + 35313 => SysReg::TRCVMIDCVR7, + 35716 => SysReg::TRCITCTRL, + 35735 => SysReg::TRCDEVID, + 35743 => SysReg::TRCDEVTYPE, + 35751 => SysReg::TRCPIDR4, + 35759 => SysReg::TRCPIDR5, + 35767 => SysReg::TRCPIDR6, + 35775 => SysReg::TRCPIDR7, + 35782 => SysReg::TRCCLAIMSET, + 35783 => SysReg::TRCPIDR0, + 35790 => SysReg::TRCCLAIMCLR, + 35791 => SysReg::TRCPIDR1, + 35798 => SysReg::TRCDEVAFF0, + 35799 => SysReg::TRCPIDR2, + 35806 => SysReg::TRCDEVAFF1, + 35807 => SysReg::TRCPIDR3, + 35814 => SysReg::TRCLAR, + 35815 => SysReg::TRCCIDR0, + 35822 => SysReg::TRCLSR, + 35823 => SysReg::TRCCIDR1, + 35830 => SysReg::TRCAUTHSTATUS, + 35831 => SysReg::TRCCIDR2, + 35838 => SysReg::TRCDEVARCH, + 35839 => SysReg::TRCCIDR3, + 35840 => SysReg::BRBINF0_EL1, + 35841 => SysReg::BRBSRC0_EL1, + 35842 => SysReg::BRBTGT0_EL1, + 35844 => SysReg::BRBINF16_EL1, + 35845 => SysReg::BRBSRC16_EL1, + 35846 => SysReg::BRBTGT16_EL1, + 35848 => SysReg::BRBINF1_EL1, + 35849 => SysReg::BRBSRC1_EL1, + 35850 => SysReg::BRBTGT1_EL1, + 35852 => SysReg::BRBINF17_EL1, + 35853 => SysReg::BRBSRC17_EL1, + 35854 => SysReg::BRBTGT17_EL1, + 35856 => SysReg::BRBINF2_EL1, + 35857 => SysReg::BRBSRC2_EL1, + 35858 => SysReg::BRBTGT2_EL1, + 35860 => SysReg::BRBINF18_EL1, + 35861 => SysReg::BRBSRC18_EL1, + 35862 => SysReg::BRBTGT18_EL1, + 35864 => SysReg::BRBINF3_EL1, + 35865 => SysReg::BRBSRC3_EL1, + 35866 => SysReg::BRBTGT3_EL1, + 35868 => SysReg::BRBINF19_EL1, + 35869 => SysReg::BRBSRC19_EL1, + 35870 => SysReg::BRBTGT19_EL1, + 35872 => SysReg::BRBINF4_EL1, + 35873 => SysReg::BRBSRC4_EL1, + 35874 => SysReg::BRBTGT4_EL1, + 35876 => SysReg::BRBINF20_EL1, + 35877 => SysReg::BRBSRC20_EL1, + 35878 => SysReg::BRBTGT20_EL1, + 35880 => SysReg::BRBINF5_EL1, + 35881 => SysReg::BRBSRC5_EL1, + 35882 => SysReg::BRBTGT5_EL1, + 35884 => SysReg::BRBINF21_EL1, + 35885 => SysReg::BRBSRC21_EL1, + 35886 => SysReg::BRBTGT21_EL1, + 35888 => SysReg::BRBINF6_EL1, + 35889 => SysReg::BRBSRC6_EL1, + 35890 => SysReg::BRBTGT6_EL1, + 35892 => SysReg::BRBINF22_EL1, + 35893 => SysReg::BRBSRC22_EL1, + 35894 => SysReg::BRBTGT22_EL1, + 35896 => SysReg::BRBINF7_EL1, + 35897 => SysReg::BRBSRC7_EL1, + 35898 => SysReg::BRBTGT7_EL1, + 35900 => SysReg::BRBINF23_EL1, + 35901 => SysReg::BRBSRC23_EL1, + 35902 => SysReg::BRBTGT23_EL1, + 35904 => SysReg::BRBINF8_EL1, + 35905 => SysReg::BRBSRC8_EL1, + 35906 => SysReg::BRBTGT8_EL1, + 35908 => SysReg::BRBINF24_EL1, + 35909 => SysReg::BRBSRC24_EL1, + 35910 => SysReg::BRBTGT24_EL1, + 35912 => SysReg::BRBINF9_EL1, + 35913 => SysReg::BRBSRC9_EL1, + 35914 => SysReg::BRBTGT9_EL1, + 35916 => SysReg::BRBINF25_EL1, + 35917 => SysReg::BRBSRC25_EL1, + 35918 => SysReg::BRBTGT25_EL1, + 35920 => SysReg::BRBINF10_EL1, + 35921 => SysReg::BRBSRC10_EL1, + 35922 => SysReg::BRBTGT10_EL1, + 35924 => SysReg::BRBINF26_EL1, + 35925 => SysReg::BRBSRC26_EL1, + 35926 => SysReg::BRBTGT26_EL1, + 35928 => SysReg::BRBINF11_EL1, + 35929 => SysReg::BRBSRC11_EL1, + 35930 => SysReg::BRBTGT11_EL1, + 35932 => SysReg::BRBINF27_EL1, + 35933 => SysReg::BRBSRC27_EL1, + 35934 => SysReg::BRBTGT27_EL1, + 35936 => SysReg::BRBINF12_EL1, + 35937 => SysReg::BRBSRC12_EL1, + 35938 => SysReg::BRBTGT12_EL1, + 35940 => SysReg::BRBINF28_EL1, + 35941 => SysReg::BRBSRC28_EL1, + 35942 => SysReg::BRBTGT28_EL1, + 35944 => SysReg::BRBINF13_EL1, + 35945 => SysReg::BRBSRC13_EL1, + 35946 => SysReg::BRBTGT13_EL1, + 35948 => SysReg::BRBINF29_EL1, + 35949 => SysReg::BRBSRC29_EL1, + 35950 => SysReg::BRBTGT29_EL1, + 35952 => SysReg::BRBINF14_EL1, + 35953 => SysReg::BRBSRC14_EL1, + 35954 => SysReg::BRBTGT14_EL1, + 35956 => SysReg::BRBINF30_EL1, + 35957 => SysReg::BRBSRC30_EL1, + 35958 => SysReg::BRBTGT30_EL1, + 35960 => SysReg::BRBINF15_EL1, + 35961 => SysReg::BRBSRC15_EL1, + 35962 => SysReg::BRBTGT15_EL1, + 35964 => SysReg::BRBINF31_EL1, + 35965 => SysReg::BRBSRC31_EL1, + 35966 => SysReg::BRBTGT31_EL1, + 35968 => SysReg::BRBCR_EL1, + 35969 => SysReg::BRBFCR_EL1, + 35970 => SysReg::BRBTS_EL1, + 35976 => SysReg::BRBINFINJ_EL1, + 35977 => SysReg::BRBSRCINJ_EL1, + 35978 => SysReg::BRBTGTINJ_EL1, + 35984 => SysReg::BRBIDR0_EL1, + 36864 => SysReg::TEECR32_EL1, + 36992 => SysReg::TEEHBR32_EL1, + 38920 => SysReg::MDCCSR_EL0, + 38944 => SysReg::DBGDTR_EL0, + 38952 => SysReg::DBGDTRRX_EL0, + 40160 => SysReg::SPMCR_EL0, + 40161 => SysReg::SPMCNTENSET_EL0, + 40162 => SysReg::SPMCNTENCLR_EL0, + 40163 => SysReg::SPMOVSCLR_EL0, + 40164 => SysReg::SPMZR_EL0, + 40165 => SysReg::SPMSELR_EL0, + 40179 => SysReg::SPMOVSSET_EL0, + 40704 => SysReg::SPMEVCNTR0_EL0, + 40705 => SysReg::SPMEVCNTR1_EL0, + 40706 => SysReg::SPMEVCNTR2_EL0, + 40707 => SysReg::SPMEVCNTR3_EL0, + 40708 => SysReg::SPMEVCNTR4_EL0, + 40709 => SysReg::SPMEVCNTR5_EL0, + 40710 => SysReg::SPMEVCNTR6_EL0, + 40711 => SysReg::SPMEVCNTR7_EL0, + 40712 => SysReg::SPMEVCNTR8_EL0, + 40713 => SysReg::SPMEVCNTR9_EL0, + 40714 => SysReg::SPMEVCNTR10_EL0, + 40715 => SysReg::SPMEVCNTR11_EL0, + 40716 => SysReg::SPMEVCNTR12_EL0, + 40717 => SysReg::SPMEVCNTR13_EL0, + 40718 => SysReg::SPMEVCNTR14_EL0, + 40719 => SysReg::SPMEVCNTR15_EL0, + 40720 => SysReg::SPMEVTYPER0_EL0, + 40721 => SysReg::SPMEVTYPER1_EL0, + 40722 => SysReg::SPMEVTYPER2_EL0, + 40723 => SysReg::SPMEVTYPER3_EL0, + 40724 => SysReg::SPMEVTYPER4_EL0, + 40725 => SysReg::SPMEVTYPER5_EL0, + 40726 => SysReg::SPMEVTYPER6_EL0, + 40727 => SysReg::SPMEVTYPER7_EL0, + 40728 => SysReg::SPMEVTYPER8_EL0, + 40729 => SysReg::SPMEVTYPER9_EL0, + 40730 => SysReg::SPMEVTYPER10_EL0, + 40731 => SysReg::SPMEVTYPER11_EL0, + 40732 => SysReg::SPMEVTYPER12_EL0, + 40733 => SysReg::SPMEVTYPER13_EL0, + 40734 => SysReg::SPMEVTYPER14_EL0, + 40735 => SysReg::SPMEVTYPER15_EL0, + 40736 => SysReg::SPMEVFILTR0_EL0, + 40737 => SysReg::SPMEVFILTR1_EL0, + 40738 => SysReg::SPMEVFILTR2_EL0, + 40739 => SysReg::SPMEVFILTR3_EL0, + 40740 => SysReg::SPMEVFILTR4_EL0, + 40741 => SysReg::SPMEVFILTR5_EL0, + 40742 => SysReg::SPMEVFILTR6_EL0, + 40743 => SysReg::SPMEVFILTR7_EL0, + 40744 => SysReg::SPMEVFILTR8_EL0, + 40745 => SysReg::SPMEVFILTR9_EL0, + 40746 => SysReg::SPMEVFILTR10_EL0, + 40747 => SysReg::SPMEVFILTR11_EL0, + 40748 => SysReg::SPMEVFILTR12_EL0, + 40749 => SysReg::SPMEVFILTR13_EL0, + 40750 => SysReg::SPMEVFILTR14_EL0, + 40751 => SysReg::SPMEVFILTR15_EL0, + 40752 => SysReg::SPMEVFILT2R0_EL0, + 40753 => SysReg::SPMEVFILT2R1_EL0, + 40754 => SysReg::SPMEVFILT2R2_EL0, + 40755 => SysReg::SPMEVFILT2R3_EL0, + 40756 => SysReg::SPMEVFILT2R4_EL0, + 40757 => SysReg::SPMEVFILT2R5_EL0, + 40758 => SysReg::SPMEVFILT2R6_EL0, + 40759 => SysReg::SPMEVFILT2R7_EL0, + 40760 => SysReg::SPMEVFILT2R8_EL0, + 40761 => SysReg::SPMEVFILT2R9_EL0, + 40762 => SysReg::SPMEVFILT2R10_EL0, + 40763 => SysReg::SPMEVFILT2R11_EL0, + 40764 => SysReg::SPMEVFILT2R12_EL0, + 40765 => SysReg::SPMEVFILT2R13_EL0, + 40766 => SysReg::SPMEVFILT2R14_EL0, + 40767 => SysReg::SPMEVFILT2R15_EL0, + 41016 => SysReg::DBGVCR32_EL2, + 42112 => SysReg::BRBCR_EL2, + 42219 => SysReg::SPMACCESSR_EL2, + 44160 => SysReg::BRBCR_EL12, + 44267 => SysReg::SPMACCESSR_EL12, + 46315 => SysReg::SPMACCESSR_EL3, + 46327 => SysReg::SPMROOTCR_EL3, + 48375 => SysReg::SPMSCR_EL1, + 49152 => SysReg::MIDR_EL1, + 49156 => SysReg::MPUIR_EL1, + 49157 => SysReg::MPIDR_EL1, + 49158 => SysReg::REVIDR_EL1, + 49160 => SysReg::ID_PFR0_EL1, + 49161 => SysReg::ID_PFR1_EL1, + 49162 => SysReg::ID_DFR0_EL1, + 49163 => SysReg::ID_AFR0_EL1, + 49164 => SysReg::ID_MMFR0_EL1, + 49165 => SysReg::ID_MMFR1_EL1, + 49166 => SysReg::ID_MMFR2_EL1, + 49167 => SysReg::ID_MMFR3_EL1, + 49168 => SysReg::ID_ISAR0_EL1, + 49169 => SysReg::ID_ISAR1_EL1, + 49170 => SysReg::ID_ISAR2_EL1, + 49171 => SysReg::ID_ISAR3_EL1, + 49172 => SysReg::ID_ISAR4_EL1, + 49173 => SysReg::ID_ISAR5_EL1, + 49174 => SysReg::ID_MMFR4_EL1, + 49175 => SysReg::ID_ISAR6_EL1, + 49176 => SysReg::MVFR0_EL1, + 49177 => SysReg::MVFR1_EL1, + 49178 => SysReg::MVFR2_EL1, + 49180 => SysReg::ID_PFR2_EL1, + 49181 => SysReg::ID_DFR1_EL1, + 49182 => SysReg::ID_MMFR5_EL1, + 49184 => SysReg::ID_AA64PFR0_EL1, + 49185 => SysReg::ID_AA64PFR1_EL1, + 49186 => SysReg::ID_AA64PFR2_EL1, + 49188 => SysReg::ID_AA64ZFR0_EL1, + 49189 => SysReg::ID_AA64SMFR0_EL1, + 49191 => SysReg::ID_AA64FPFR0_EL1, + 49192 => SysReg::ID_AA64DFR0_EL1, + 49193 => SysReg::ID_AA64DFR1_EL1, + 49194 => SysReg::ID_AA64DFR2_EL1, + 49196 => SysReg::ID_AA64AFR0_EL1, + 49197 => SysReg::ID_AA64AFR1_EL1, + 49200 => SysReg::ID_AA64ISAR0_EL1, + 49201 => SysReg::ID_AA64ISAR1_EL1, + 49202 => SysReg::ID_AA64ISAR2_EL1, + 49203 => SysReg::ID_AA64ISAR3_EL1, + 49208 => SysReg::ID_AA64MMFR0_EL1, + 49209 => SysReg::ID_AA64MMFR1_EL1, + 49210 => SysReg::ID_AA64MMFR2_EL1, + 49211 => SysReg::ID_AA64MMFR3_EL1, + 49212 => SysReg::ID_AA64MMFR4_EL1, + 49280 => SysReg::SCTLR_EL1, + 49281 => SysReg::ACTLR_EL1, + 49282 => SysReg::CPACR_EL1, + 49283 => SysReg::SCTLR2_EL1, + 49285 => SysReg::RGSR_EL1, + 49286 => SysReg::GCR_EL1, + 49296 => SysReg::ZCR_EL1, + 49297 => SysReg::TRFCR_EL1, + 49299 => SysReg::TRCITECR_EL1, + 49300 => SysReg::SMPRI_EL1, + 49302 => SysReg::SMCR_EL1, + 49312 => SysReg::SCTLRMASK_EL1, + 49313 => SysReg::ACTLRMASK_EL1, + 49314 => SysReg::CPACRMASK_EL1, + 49315 => SysReg::SCTLR2MASK_EL1, + 49316 => SysReg::CPACRALIAS_EL1, + 49317 => SysReg::ACTLRALIAS_EL1, + 49318 => SysReg::SCTLRALIAS_EL1, + 49319 => SysReg::SCTLR2ALIAS_EL1, + 49408 => SysReg::TTBR0_EL1, + 49409 => SysReg::TTBR1_EL1, + 49410 => SysReg::TCR_EL1, + 49411 => SysReg::TCR2_EL1, + 49412 => SysReg::IRTBRU_EL1, + 49413 => SysReg::IRTBRP_EL1, + 49414 => SysReg::DPOTBR0_EL1, + 49415 => SysReg::DPOTBR1_EL1, + 49416 => SysReg::APIAKeyLo_EL1, + 49417 => SysReg::APIAKeyHi_EL1, + 49418 => SysReg::APIBKeyLo_EL1, + 49419 => SysReg::APIBKeyHi_EL1, + 49423 => SysReg::LDSTT_EL1, + 49424 => SysReg::APDAKeyLo_EL1, + 49425 => SysReg::APDAKeyHi_EL1, + 49426 => SysReg::APDBKeyLo_EL1, + 49427 => SysReg::APDBKeyHi_EL1, + 49428 => SysReg::TPMIN0_EL1, + 49429 => SysReg::TPMAX0_EL1, + 49430 => SysReg::TPMIN1_EL1, + 49431 => SysReg::TPMAX1_EL1, + 49432 => SysReg::APGAKeyLo_EL1, + 49433 => SysReg::APGAKeyHi_EL1, + 49448 => SysReg::GCSCR_EL1, + 49449 => SysReg::GCSPR_EL1, + 49450 => SysReg::GCSCRE0_EL1, + 49466 => SysReg::TCRMASK_EL1, + 49467 => SysReg::TCR2MASK_EL1, + 49470 => SysReg::TCRALIAS_EL1, + 49471 => SysReg::TCR2ALIAS_EL1, + 49552 => SysReg::FGDTP0_EL1, + 49553 => SysReg::FGDTP1_EL1, + 49554 => SysReg::FGDTP2_EL1, + 49555 => SysReg::FGDTP3_EL1, + 49556 => SysReg::FGDTP4_EL1, + 49557 => SysReg::FGDTP5_EL1, + 49558 => SysReg::FGDTP6_EL1, + 49559 => SysReg::FGDTP7_EL1, + 49560 => SysReg::FGDTP8_EL1, + 49561 => SysReg::FGDTP9_EL1, + 49562 => SysReg::FGDTP10_EL1, + 49563 => SysReg::FGDTP11_EL1, + 49564 => SysReg::FGDTP12_EL1, + 49565 => SysReg::FGDTP13_EL1, + 49566 => SysReg::FGDTP14_EL1, + 49567 => SysReg::FGDTP15_EL1, + 49568 => SysReg::FGDTU0_EL1, + 49569 => SysReg::FGDTU1_EL1, + 49570 => SysReg::FGDTU2_EL1, + 49571 => SysReg::FGDTU3_EL1, + 49572 => SysReg::FGDTU4_EL1, + 49573 => SysReg::FGDTU5_EL1, + 49574 => SysReg::FGDTU6_EL1, + 49575 => SysReg::FGDTU7_EL1, + 49576 => SysReg::FGDTU8_EL1, + 49577 => SysReg::FGDTU9_EL1, + 49578 => SysReg::FGDTU10_EL1, + 49579 => SysReg::FGDTU11_EL1, + 49580 => SysReg::FGDTU12_EL1, + 49581 => SysReg::FGDTU13_EL1, + 49582 => SysReg::FGDTU14_EL1, + 49583 => SysReg::FGDTU15_EL1, + 49584 => SysReg::AFGDTP0_EL1, + 49585 => SysReg::AFGDTP1_EL1, + 49586 => SysReg::AFGDTP2_EL1, + 49587 => SysReg::AFGDTP3_EL1, + 49588 => SysReg::AFGDTP4_EL1, + 49589 => SysReg::AFGDTP5_EL1, + 49590 => SysReg::AFGDTP6_EL1, + 49591 => SysReg::AFGDTP7_EL1, + 49592 => SysReg::AFGDTP8_EL1, + 49593 => SysReg::AFGDTP9_EL1, + 49594 => SysReg::AFGDTP10_EL1, + 49595 => SysReg::AFGDTP11_EL1, + 49596 => SysReg::AFGDTP12_EL1, + 49597 => SysReg::AFGDTP13_EL1, + 49598 => SysReg::AFGDTP14_EL1, + 49599 => SysReg::AFGDTP15_EL1, + 49600 => SysReg::AFGDTU0_EL1, + 49601 => SysReg::AFGDTU1_EL1, + 49602 => SysReg::AFGDTU2_EL1, + 49603 => SysReg::AFGDTU3_EL1, + 49604 => SysReg::AFGDTU4_EL1, + 49605 => SysReg::AFGDTU5_EL1, + 49606 => SysReg::AFGDTU6_EL1, + 49607 => SysReg::AFGDTU7_EL1, + 49608 => SysReg::AFGDTU8_EL1, + 49609 => SysReg::AFGDTU9_EL1, + 49610 => SysReg::AFGDTU10_EL1, + 49611 => SysReg::AFGDTU11_EL1, + 49612 => SysReg::AFGDTU12_EL1, + 49613 => SysReg::AFGDTU13_EL1, + 49614 => SysReg::AFGDTU14_EL1, + 49615 => SysReg::AFGDTU15_EL1, + 49664 => SysReg::SPSR_EL1, + 49665 => SysReg::ELR_EL1, + 49666 => SysReg::STINDEX_EL1, + 49667 => SysReg::TINDEX_EL1, + 49672 => SysReg::SP_EL0, + 49680 => SysReg::SPSel, + 49682 => SysReg::CurrentEL, + 49683 => SysReg::PAN, + 49684 => SysReg::UAO, + 49688 => SysReg::ALLINT, + 49689 => SysReg::PM, + 49712 => SysReg::ICC_PMR_EL1, + 49800 => SysReg::AFSR0_EL1, + 49801 => SysReg::AFSR1_EL1, + 49808 => SysReg::ESR_EL1, + 49816 => SysReg::ERRIDR_EL1, + 49817 => SysReg::ERRSELR_EL1, + 49818 => SysReg::ERXGSR_EL1, + 49824 => SysReg::ERXFR_EL1, + 49825 => SysReg::ERXCTLR_EL1, + 49826 => SysReg::ERXSTATUS_EL1, + 49827 => SysReg::ERXADDR_EL1, + 49828 => SysReg::ERXPFGF_EL1, + 49829 => SysReg::ERXPFGCTL_EL1, + 49830 => SysReg::ERXPFGCDN_EL1, + 49832 => SysReg::ERXMISC0_EL1, + 49833 => SysReg::ERXMISC1_EL1, + 49834 => SysReg::ERXMISC2_EL1, + 49835 => SysReg::ERXMISC3_EL1, + 49840 => SysReg::TFSR_EL1, + 49841 => SysReg::TFSRE0_EL1, + 49920 => SysReg::FAR_EL1, + 49925 => SysReg::PFAR_EL1, + 49929 => SysReg::PRENR_EL1, + 49937 => SysReg::PRSELR_EL1, + 49984 => SysReg::PRBAR_EL1, + 49985 => SysReg::PRLAR_EL1, + 49988 => SysReg::PRBAR1_EL1, + 49989 => SysReg::PRLAR1_EL1, + 49992 => SysReg::PRBAR2_EL1, + 49993 => SysReg::PRLAR2_EL1, + 49996 => SysReg::PRBAR3_EL1, + 49997 => SysReg::PRLAR3_EL1, + 50000 => SysReg::PRBAR4_EL1, + 50001 => SysReg::PRLAR4_EL1, + 50004 => SysReg::PRBAR5_EL1, + 50005 => SysReg::PRLAR5_EL1, + 50008 => SysReg::PRBAR6_EL1, + 50009 => SysReg::PRLAR6_EL1, + 50012 => SysReg::PRBAR7_EL1, + 50013 => SysReg::PRLAR7_EL1, + 50016 => SysReg::PRBAR8_EL1, + 50017 => SysReg::PRLAR8_EL1, + 50020 => SysReg::PRBAR9_EL1, + 50021 => SysReg::PRLAR9_EL1, + 50024 => SysReg::PRBAR10_EL1, + 50025 => SysReg::PRLAR10_EL1, + 50028 => SysReg::PRBAR11_EL1, + 50029 => SysReg::PRLAR11_EL1, + 50032 => SysReg::PRBAR12_EL1, + 50033 => SysReg::PRLAR12_EL1, + 50036 => SysReg::PRBAR13_EL1, + 50037 => SysReg::PRLAR13_EL1, + 50040 => SysReg::PRBAR14_EL1, + 50041 => SysReg::PRLAR14_EL1, + 50044 => SysReg::PRBAR15_EL1, + 50045 => SysReg::PRLAR15_EL1, + 50080 => SysReg::PAR_EL1, + 50376 => SysReg::PMSCR_EL1, + 50377 => SysReg::PMSNEVFR_EL1, + 50378 => SysReg::PMSICR_EL1, + 50379 => SysReg::PMSIRR_EL1, + 50380 => SysReg::PMSFCR_EL1, + 50381 => SysReg::PMSEVFR_EL1, + 50382 => SysReg::PMSLATFR_EL1, + 50383 => SysReg::PMSIDR_EL1, + 50384 => SysReg::PMBLIMITR_EL1, + 50385 => SysReg::PMBPTR_EL1, + 50387 => SysReg::PMBSR_EL1, + 50388 => SysReg::PMSDSFR_EL1, + 50389 => SysReg::PMBMAR_EL1, + 50391 => SysReg::PMBIDR_EL1, + 50392 => SysReg::TRBLIMITR_EL1, + 50393 => SysReg::TRBPTR_EL1, + 50394 => SysReg::TRBBASER_EL1, + 50395 => SysReg::TRBSR_EL1, + 50396 => SysReg::TRBMAR_EL1, + 50397 => SysReg::TRBMPAM_EL1, + 50398 => SysReg::TRBTRG_EL1, + 50399 => SysReg::TRBIDR_EL1, + 50411 => SysReg::PMSSCR_EL1, + 50417 => SysReg::PMINTENSET_EL1, + 50418 => SysReg::PMINTENCLR_EL1, + 50420 => SysReg::PMUACR_EL1, + 50421 => SysReg::PMECR_EL1, + 50422 => SysReg::PMMIR_EL1, + 50423 => SysReg::PMIAR_EL1, + 50448 => SysReg::MAIR_EL1, + 50449 => SysReg::MAIR2_EL1, + 50450 => SysReg::PIRE0_EL1, + 50451 => SysReg::PIR_EL1, + 50452 => SysReg::POR_EL1, + 50453 => SysReg::S2POR_EL1, + 50454 => SysReg::TTTBRU_EL1, + 50455 => SysReg::TTTBRP_EL1, + 50456 => SysReg::AMAIR_EL1, + 50457 => SysReg::AMAIR2_EL1, + 50464 => SysReg::LORSA_EL1, + 50465 => SysReg::LOREA_EL1, + 50466 => SysReg::LORN_EL1, + 50467 => SysReg::LORC_EL1, + 50468 => SysReg::MPAMIDR_EL1, + 50469 => SysReg::MPAMBWIDR_EL1, + 50470 => SysReg::TLBIDIDR_EL1, + 50471 => SysReg::LORID_EL1, + 50472 => SysReg::MPAM1_EL1, + 50473 => SysReg::MPAM0_EL1, + 50474 => SysReg::MPAMCTL_EL1, + 50475 => SysReg::MPAMSM_EL1, + 50476 => SysReg::MPAMBW1_EL1, + 50477 => SysReg::MPAMBW0_EL1, + 50479 => SysReg::MPAMBWSM_EL1, + 50688 => SysReg::VBAR_EL1, + 50689 => SysReg::RVBAR_EL1, + 50690 => SysReg::RMR_EL1, + 50696 => SysReg::ISR_EL1, + 50697 => SysReg::DISR_EL1, + 50752 => SysReg::ICC_IAR0_EL1, + 50753 => SysReg::ICC_EOIR0_EL1, + 50754 => SysReg::ICC_HPPIR0_EL1, + 50755 => SysReg::ICC_BPR0_EL1, + 50756 => SysReg::ICC_AP0R0_EL1, + 50757 => SysReg::ICC_AP0R1_EL1, + 50758 => SysReg::ICC_AP0R2_EL1, + 50759 => SysReg::ICC_AP0R3_EL1, + 50760 => SysReg::ICC_AP1R0_EL1, + 50761 => SysReg::ICC_AP1R1_EL1, + 50762 => SysReg::ICC_AP1R2_EL1, + 50763 => SysReg::ICC_AP1R3_EL1, + 50765 => SysReg::ICC_NMIAR1_EL1, + 50768 => SysReg::ICC_PPI_HMR0_EL1, + 50769 => SysReg::ICC_PPI_HMR1_EL1, + 50770 => SysReg::ICC_IDR0_EL1, + 50771 => SysReg::ICC_HPPIR_EL1, + 50772 => SysReg::ICC_ICSR_EL1, + 50773 => SysReg::ICC_IAFFIDR_EL1, + 50774 => SysReg::ICC_PPI_ENABLER0_EL1, + 50775 => SysReg::ICC_PPI_ENABLER1_EL1, + 50777 => SysReg::ICC_DIR_EL1, + 50779 => SysReg::ICC_RPR_EL1, + 50781 => SysReg::ICC_SGI1R_EL1, + 50782 => SysReg::ICC_ASGI1R_EL1, + 50783 => SysReg::ICC_SGI0R_EL1, + 50784 => SysReg::ICC_IAR1_EL1, + 50785 => SysReg::ICC_EOIR1_EL1, + 50786 => SysReg::ICC_HPPIR1_EL1, + 50787 => SysReg::ICC_BPR1_EL1, + 50788 => SysReg::ICC_CTLR_EL1, + 50789 => SysReg::ICC_SRE_EL1, + 50790 => SysReg::ICC_IGRPEN0_EL1, + 50791 => SysReg::ICC_IGRPEN1_EL1, + 50792 => SysReg::ICC_PPI_CACTIVER0_EL1, + 50793 => SysReg::ICC_PPI_CACTIVER1_EL1, + 50794 => SysReg::ICC_PPI_SACTIVER0_EL1, + 50795 => SysReg::ICC_PPI_SACTIVER1_EL1, + 50796 => SysReg::ICC_PPI_CPENDR0_EL1, + 50797 => SysReg::ICC_PPI_CPENDR1_EL1, + 50798 => SysReg::ICC_PPI_SPENDR0_EL1, + 50799 => SysReg::ICC_PPI_SPENDR1_EL1, + 50800 => SysReg::ICC_PPI_PRIORITYR0_EL1, + 50801 => SysReg::ICC_PPI_PRIORITYR1_EL1, + 50802 => SysReg::ICC_PPI_PRIORITYR2_EL1, + 50803 => SysReg::ICC_PPI_PRIORITYR3_EL1, + 50804 => SysReg::ICC_PPI_PRIORITYR4_EL1, + 50805 => SysReg::ICC_PPI_PRIORITYR5_EL1, + 50806 => SysReg::ICC_PPI_PRIORITYR6_EL1, + 50807 => SysReg::ICC_PPI_PRIORITYR7_EL1, + 50808 => SysReg::ICC_PPI_PRIORITYR8_EL1, + 50809 => SysReg::ICC_PPI_PRIORITYR9_EL1, + 50810 => SysReg::ICC_PPI_PRIORITYR10_EL1, + 50811 => SysReg::ICC_PPI_PRIORITYR11_EL1, + 50812 => SysReg::ICC_PPI_PRIORITYR12_EL1, + 50813 => SysReg::ICC_PPI_PRIORITYR13_EL1, + 50814 => SysReg::ICC_PPI_PRIORITYR14_EL1, + 50815 => SysReg::ICC_PPI_PRIORITYR15_EL1, + 50816 => SysReg::TPIDR3_EL1, + 50817 => SysReg::CONTEXTIDR_EL1, + 50819 => SysReg::RCWSMASK_EL1, + 50820 => SysReg::TPIDR_EL1, + 50821 => SysReg::ACCDATA_EL1, + 50822 => SysReg::RCWMASK_EL1, + 50823 => SysReg::SCXTNUM_EL1, + 50952 => SysReg::CNTKCTL_EL1, + 51200 => SysReg::CCSIDR_EL1, + 51201 => SysReg::CLIDR_EL1, + 51202 => SysReg::CCSIDR2_EL1, + 51204 => SysReg::GMID_EL1, + 51206 => SysReg::SMIDR_EL1, + 51207 => SysReg::AIDR_EL1, + 52736 => SysReg::ICC_APR_EL1, + 52737 => SysReg::ICC_CR0_EL1, + 52738 => SysReg::ICC_PCR_EL1, + 52739 => SysReg::ICC_HAPR_EL1, + 53248 => SysReg::CSSELR_EL1, + 55297 => SysReg::CTR_EL0, + 55303 => SysReg::DCZID_EL0, + 55572 => SysReg::TPMIN0_EL0, + 55573 => SysReg::TPMAX0_EL0, + 55574 => SysReg::TPMIN1_EL0, + 55575 => SysReg::TPMAX1_EL0, + 55584 => SysReg::RNDR, + 55585 => SysReg::RNDRRS, + 55593 => SysReg::GCSPR_EL0, + 55811 => SysReg::TINDEX_EL0, + 55824 => SysReg::NZCV, + 55825 => SysReg::DAIF, + 55826 => SysReg::SVCR, + 55829 => SysReg::DIT, + 55830 => SysReg::SSBS, + 55831 => SysReg::TCO, + 55840 => SysReg::FPCR, + 55841 => SysReg::FPSR, + 55842 => SysReg::FPMR, + 55848 => SysReg::DSPSR_EL0, + 55849 => SysReg::DLR_EL0, + 55850 => SysReg::DPOCR_EL0, + 56480 => SysReg::PMICNTR_EL0, + 56496 => SysReg::PMICFILTR_EL0, + 56544 => SysReg::PMCR_EL0, + 56545 => SysReg::PMCNTENSET_EL0, + 56546 => SysReg::PMCNTENCLR_EL0, + 56547 => SysReg::PMOVSCLR_EL0, + 56548 => SysReg::PMSWINC_EL0, + 56549 => SysReg::PMSELR_EL0, + 56550 => SysReg::PMCEID0_EL0, + 56551 => SysReg::PMCEID1_EL0, + 56552 => SysReg::PMCCNTR_EL0, + 56553 => SysReg::PMXEVTYPER_EL0, + 56554 => SysReg::PMXEVCNTR_EL0, + 56556 => SysReg::PMZR_EL0, + 56560 => SysReg::PMUSERENR_EL0, + 56563 => SysReg::PMOVSSET_EL0, + 56596 => SysReg::POR_EL0, + 56960 => SysReg::TPIDR3_EL0, + 56962 => SysReg::TPIDR_EL0, + 56963 => SysReg::TPIDRRO_EL0, + 56965 => SysReg::TPIDR2_EL0, + 56967 => SysReg::SCXTNUM_EL0, + 56976 => SysReg::AMCR_EL0, + 56977 => SysReg::AMCFGR_EL0, + 56978 => SysReg::AMCGCR_EL0, + 56979 => SysReg::AMUSERENR_EL0, + 56980 => SysReg::AMCNTENCLR0_EL0, + 56981 => SysReg::AMCNTENSET0_EL0, + 56982 => SysReg::AMCG1IDR_EL0, + 56984 => SysReg::AMCNTENCLR1_EL0, + 56985 => SysReg::AMCNTENSET1_EL0, + 56992 => SysReg::AMEVCNTR00_EL0, + 56993 => SysReg::AMEVCNTR01_EL0, + 56994 => SysReg::AMEVCNTR02_EL0, + 56995 => SysReg::AMEVCNTR03_EL0, + 57008 => SysReg::AMEVTYPER00_EL0, + 57009 => SysReg::AMEVTYPER01_EL0, + 57010 => SysReg::AMEVTYPER02_EL0, + 57011 => SysReg::AMEVTYPER03_EL0, + 57056 => SysReg::AMEVCNTR10_EL0, + 57057 => SysReg::AMEVCNTR11_EL0, + 57058 => SysReg::AMEVCNTR12_EL0, + 57059 => SysReg::AMEVCNTR13_EL0, + 57060 => SysReg::AMEVCNTR14_EL0, + 57061 => SysReg::AMEVCNTR15_EL0, + 57062 => SysReg::AMEVCNTR16_EL0, + 57063 => SysReg::AMEVCNTR17_EL0, + 57064 => SysReg::AMEVCNTR18_EL0, + 57065 => SysReg::AMEVCNTR19_EL0, + 57066 => SysReg::AMEVCNTR110_EL0, + 57067 => SysReg::AMEVCNTR111_EL0, + 57068 => SysReg::AMEVCNTR112_EL0, + 57069 => SysReg::AMEVCNTR113_EL0, + 57070 => SysReg::AMEVCNTR114_EL0, + 57071 => SysReg::AMEVCNTR115_EL0, + 57072 => SysReg::AMEVTYPER10_EL0, + 57073 => SysReg::AMEVTYPER11_EL0, + 57074 => SysReg::AMEVTYPER12_EL0, + 57075 => SysReg::AMEVTYPER13_EL0, + 57076 => SysReg::AMEVTYPER14_EL0, + 57077 => SysReg::AMEVTYPER15_EL0, + 57078 => SysReg::AMEVTYPER16_EL0, + 57079 => SysReg::AMEVTYPER17_EL0, + 57080 => SysReg::AMEVTYPER18_EL0, + 57081 => SysReg::AMEVTYPER19_EL0, + 57082 => SysReg::AMEVTYPER110_EL0, + 57083 => SysReg::AMEVTYPER111_EL0, + 57084 => SysReg::AMEVTYPER112_EL0, + 57085 => SysReg::AMEVTYPER113_EL0, + 57086 => SysReg::AMEVTYPER114_EL0, + 57087 => SysReg::AMEVTYPER115_EL0, + 57088 => SysReg::CNTFRQ_EL0, + 57089 => SysReg::CNTPCT_EL0, + 57090 => SysReg::CNTVCT_EL0, + 57093 => SysReg::CNTPCTSS_EL0, + 57094 => SysReg::CNTVCTSS_EL0, + 57104 => SysReg::CNTP_TVAL_EL0, + 57105 => SysReg::CNTP_CTL_EL0, + 57106 => SysReg::CNTP_CVAL_EL0, + 57112 => SysReg::CNTV_TVAL_EL0, + 57113 => SysReg::CNTV_CTL_EL0, + 57114 => SysReg::CNTV_CVAL_EL0, + 57152 => SysReg::PMEVCNTR0_EL0, + 57153 => SysReg::PMEVCNTR1_EL0, + 57154 => SysReg::PMEVCNTR2_EL0, + 57155 => SysReg::PMEVCNTR3_EL0, + 57156 => SysReg::PMEVCNTR4_EL0, + 57157 => SysReg::PMEVCNTR5_EL0, + 57158 => SysReg::PMEVCNTR6_EL0, + 57159 => SysReg::PMEVCNTR7_EL0, + 57160 => SysReg::PMEVCNTR8_EL0, + 57161 => SysReg::PMEVCNTR9_EL0, + 57162 => SysReg::PMEVCNTR10_EL0, + 57163 => SysReg::PMEVCNTR11_EL0, + 57164 => SysReg::PMEVCNTR12_EL0, + 57165 => SysReg::PMEVCNTR13_EL0, + 57166 => SysReg::PMEVCNTR14_EL0, + 57167 => SysReg::PMEVCNTR15_EL0, + 57168 => SysReg::PMEVCNTR16_EL0, + 57169 => SysReg::PMEVCNTR17_EL0, + 57170 => SysReg::PMEVCNTR18_EL0, + 57171 => SysReg::PMEVCNTR19_EL0, + 57172 => SysReg::PMEVCNTR20_EL0, + 57173 => SysReg::PMEVCNTR21_EL0, + 57174 => SysReg::PMEVCNTR22_EL0, + 57175 => SysReg::PMEVCNTR23_EL0, + 57176 => SysReg::PMEVCNTR24_EL0, + 57177 => SysReg::PMEVCNTR25_EL0, + 57178 => SysReg::PMEVCNTR26_EL0, + 57179 => SysReg::PMEVCNTR27_EL0, + 57180 => SysReg::PMEVCNTR28_EL0, + 57181 => SysReg::PMEVCNTR29_EL0, + 57182 => SysReg::PMEVCNTR30_EL0, + 57184 => SysReg::PMEVTYPER0_EL0, + 57185 => SysReg::PMEVTYPER1_EL0, + 57186 => SysReg::PMEVTYPER2_EL0, + 57187 => SysReg::PMEVTYPER3_EL0, + 57188 => SysReg::PMEVTYPER4_EL0, + 57189 => SysReg::PMEVTYPER5_EL0, + 57190 => SysReg::PMEVTYPER6_EL0, + 57191 => SysReg::PMEVTYPER7_EL0, + 57192 => SysReg::PMEVTYPER8_EL0, + 57193 => SysReg::PMEVTYPER9_EL0, + 57194 => SysReg::PMEVTYPER10_EL0, + 57195 => SysReg::PMEVTYPER11_EL0, + 57196 => SysReg::PMEVTYPER12_EL0, + 57197 => SysReg::PMEVTYPER13_EL0, + 57198 => SysReg::PMEVTYPER14_EL0, + 57199 => SysReg::PMEVTYPER15_EL0, + 57200 => SysReg::PMEVTYPER16_EL0, + 57201 => SysReg::PMEVTYPER17_EL0, + 57202 => SysReg::PMEVTYPER18_EL0, + 57203 => SysReg::PMEVTYPER19_EL0, + 57204 => SysReg::PMEVTYPER20_EL0, + 57205 => SysReg::PMEVTYPER21_EL0, + 57206 => SysReg::PMEVTYPER22_EL0, + 57207 => SysReg::PMEVTYPER23_EL0, + 57208 => SysReg::PMEVTYPER24_EL0, + 57209 => SysReg::PMEVTYPER25_EL0, + 57210 => SysReg::PMEVTYPER26_EL0, + 57211 => SysReg::PMEVTYPER27_EL0, + 57212 => SysReg::PMEVTYPER28_EL0, + 57213 => SysReg::PMEVTYPER29_EL0, + 57214 => SysReg::PMEVTYPER30_EL0, + 57215 => SysReg::PMCCFILTR_EL0, + 57344 => SysReg::VPIDR_EL2, + 57348 => SysReg::MPUIR_EL2, + 57349 => SysReg::VMPIDR_EL2, + 57472 => SysReg::SCTLR_EL2, + 57473 => SysReg::ACTLR_EL2, + 57475 => SysReg::SCTLR2_EL2, + 57480 => SysReg::HCR_EL2, + 57481 => SysReg::MDCR_EL2, + 57482 => SysReg::CPTR_EL2, + 57483 => SysReg::HSTR_EL2, + 57484 => SysReg::HFGRTR_EL2, + 57485 => SysReg::HFGWTR_EL2, + 57486 => SysReg::HFGITR_EL2, + 57487 => SysReg::HACR_EL2, + 57488 => SysReg::ZCR_EL2, + 57489 => SysReg::TRFCR_EL2, + 57490 => SysReg::HCRX_EL2, + 57491 => SysReg::TRCITECR_EL2, + 57493 => SysReg::SMPRIMAP_EL2, + 57494 => SysReg::SMCR_EL2, + 57497 => SysReg::SDER32_EL2, + 57504 => SysReg::SCTLRMASK_EL2, + 57505 => SysReg::ACTLRMASK_EL2, + 57506 => SysReg::CPTRMASK_EL2, + 57507 => SysReg::SCTLR2MASK_EL2, + 57512 => SysReg::NVHCR_EL2, + 57513 => SysReg::NVHCRX_EL2, + 57516 => SysReg::NVHCRMASK_EL2, + 57517 => SysReg::NVHCRXMASK_EL2, + 57518 => SysReg::HCRMASK_EL2, + 57519 => SysReg::HCRXMASK_EL2, + 57600 => SysReg::TTBR0_EL2, + 57601 => SysReg::TTBR1_EL2, + 57602 => SysReg::TCR_EL2, + 57603 => SysReg::TCR2_EL2, + 57604 => SysReg::IRTBRU_EL2, + 57605 => SysReg::IRTBRP_EL2, + 57606 => SysReg::DPOTBR0_EL2, + 57607 => SysReg::DPOTBR1_EL2, + 57608 => SysReg::VTTBR_EL2, + 57610 => SysReg::VTCR_EL2, + 57615 => SysReg::LDSTT_EL2, + 57616 => SysReg::VNCR_EL2, + 57617 => SysReg::VNCCR_EL2, + 57620 => SysReg::TPMIN0_EL2, + 57621 => SysReg::TPMAX0_EL2, + 57622 => SysReg::TPMIN1_EL2, + 57623 => SysReg::TPMAX1_EL2, + 57626 => SysReg::HDBSSBR_EL2, + 57627 => SysReg::HDBSSPROD_EL2, + 57628 => SysReg::HACDBSBR_EL2, + 57629 => SysReg::HACDBSCONS_EL2, + 57640 => SysReg::GCSCR_EL2, + 57641 => SysReg::GCSPR_EL2, + 57648 => SysReg::VSTTBR_EL2, + 57650 => SysReg::VSTCR_EL2, + 57658 => SysReg::TCRMASK_EL2, + 57659 => SysReg::TCR2MASK_EL2, + 57664 => SysReg::VTLBID0_EL2, + 57665 => SysReg::VTLBID1_EL2, + 57666 => SysReg::VTLBID2_EL2, + 57667 => SysReg::VTLBID3_EL2, + 57672 => SysReg::VTLBIDOS0_EL2, + 57673 => SysReg::VTLBIDOS1_EL2, + 57674 => SysReg::VTLBIDOS2_EL2, + 57675 => SysReg::VTLBIDOS3_EL2, + 57728 => SysReg::DACR32_EL2, + 57736 => SysReg::HDFGRTR2_EL2, + 57737 => SysReg::HDFGWTR2_EL2, + 57738 => SysReg::HFGRTR2_EL2, + 57739 => SysReg::HFGWTR2_EL2, + 57740 => SysReg::HDFGRTR_EL2, + 57741 => SysReg::HDFGWTR_EL2, + 57742 => SysReg::HAFGRTR_EL2, + 57743 => SysReg::HFGITR2_EL2, + 57744 => SysReg::FGDTP0_EL2, + 57745 => SysReg::FGDTP1_EL2, + 57746 => SysReg::FGDTP2_EL2, + 57747 => SysReg::FGDTP3_EL2, + 57748 => SysReg::FGDTP4_EL2, + 57749 => SysReg::FGDTP5_EL2, + 57750 => SysReg::FGDTP6_EL2, + 57751 => SysReg::FGDTP7_EL2, + 57752 => SysReg::FGDTP8_EL2, + 57753 => SysReg::FGDTP9_EL2, + 57754 => SysReg::FGDTP10_EL2, + 57755 => SysReg::FGDTP11_EL2, + 57756 => SysReg::FGDTP12_EL2, + 57757 => SysReg::FGDTP13_EL2, + 57758 => SysReg::FGDTP14_EL2, + 57759 => SysReg::FGDTP15_EL2, + 57760 => SysReg::FGDTU0_EL2, + 57761 => SysReg::FGDTU1_EL2, + 57762 => SysReg::FGDTU2_EL2, + 57763 => SysReg::FGDTU3_EL2, + 57764 => SysReg::FGDTU4_EL2, + 57765 => SysReg::FGDTU5_EL2, + 57766 => SysReg::FGDTU6_EL2, + 57767 => SysReg::FGDTU7_EL2, + 57768 => SysReg::FGDTU8_EL2, + 57769 => SysReg::FGDTU9_EL2, + 57770 => SysReg::FGDTU10_EL2, + 57771 => SysReg::FGDTU11_EL2, + 57772 => SysReg::FGDTU12_EL2, + 57773 => SysReg::FGDTU13_EL2, + 57774 => SysReg::FGDTU14_EL2, + 57775 => SysReg::FGDTU15_EL2, + 57776 => SysReg::AFGDTP0_EL2, + 57777 => SysReg::AFGDTP1_EL2, + 57778 => SysReg::AFGDTP2_EL2, + 57779 => SysReg::AFGDTP3_EL2, + 57780 => SysReg::AFGDTP4_EL2, + 57781 => SysReg::AFGDTP5_EL2, + 57782 => SysReg::AFGDTP6_EL2, + 57783 => SysReg::AFGDTP7_EL2, + 57784 => SysReg::AFGDTP8_EL2, + 57785 => SysReg::AFGDTP9_EL2, + 57786 => SysReg::AFGDTP10_EL2, + 57787 => SysReg::AFGDTP11_EL2, + 57788 => SysReg::AFGDTP12_EL2, + 57789 => SysReg::AFGDTP13_EL2, + 57790 => SysReg::AFGDTP14_EL2, + 57791 => SysReg::AFGDTP15_EL2, + 57792 => SysReg::AFGDTU0_EL2, + 57793 => SysReg::AFGDTU1_EL2, + 57794 => SysReg::AFGDTU2_EL2, + 57795 => SysReg::AFGDTU3_EL2, + 57796 => SysReg::AFGDTU4_EL2, + 57797 => SysReg::AFGDTU5_EL2, + 57798 => SysReg::AFGDTU6_EL2, + 57799 => SysReg::AFGDTU7_EL2, + 57800 => SysReg::AFGDTU8_EL2, + 57801 => SysReg::AFGDTU9_EL2, + 57802 => SysReg::AFGDTU10_EL2, + 57803 => SysReg::AFGDTU11_EL2, + 57804 => SysReg::AFGDTU12_EL2, + 57805 => SysReg::AFGDTU13_EL2, + 57806 => SysReg::AFGDTU14_EL2, + 57807 => SysReg::AFGDTU15_EL2, + 57856 => SysReg::SPSR_EL2, + 57857 => SysReg::ELR_EL2, + 57858 => SysReg::STINDEX_EL2, + 57859 => SysReg::TINDEX_EL2, + 57864 => SysReg::SP_EL1, + 57880 => SysReg::SPSR_irq, + 57881 => SysReg::SPSR_abt, + 57882 => SysReg::SPSR_und, + 57883 => SysReg::SPSR_fiq, + 57985 => SysReg::IFSR32_EL2, + 57992 => SysReg::AFSR0_EL2, + 57993 => SysReg::AFSR1_EL2, + 58000 => SysReg::ESR_EL2, + 58003 => SysReg::VSESR_EL2, + 58008 => SysReg::FPEXC32_EL2, + 58032 => SysReg::TFSR_EL2, + 58112 => SysReg::FAR_EL2, + 58116 => SysReg::HPFAR_EL2, + 58117 => SysReg::PFAR_EL2, + 58121 => SysReg::PRENR_EL2, + 58129 => SysReg::PRSELR_EL2, + 58176 => SysReg::PRBAR_EL2, + 58177 => SysReg::PRLAR_EL2, + 58180 => SysReg::PRBAR1_EL2, + 58181 => SysReg::PRLAR1_EL2, + 58184 => SysReg::PRBAR2_EL2, + 58185 => SysReg::PRLAR2_EL2, + 58188 => SysReg::PRBAR3_EL2, + 58189 => SysReg::PRLAR3_EL2, + 58192 => SysReg::PRBAR4_EL2, + 58193 => SysReg::PRLAR4_EL2, + 58196 => SysReg::PRBAR5_EL2, + 58197 => SysReg::PRLAR5_EL2, + 58200 => SysReg::PRBAR6_EL2, + 58201 => SysReg::PRLAR6_EL2, + 58204 => SysReg::PRBAR7_EL2, + 58205 => SysReg::PRLAR7_EL2, + 58208 => SysReg::PRBAR8_EL2, + 58209 => SysReg::PRLAR8_EL2, + 58212 => SysReg::PRBAR9_EL2, + 58213 => SysReg::PRLAR9_EL2, + 58216 => SysReg::PRBAR10_EL2, + 58217 => SysReg::PRLAR10_EL2, + 58220 => SysReg::PRBAR11_EL2, + 58221 => SysReg::PRLAR11_EL2, + 58224 => SysReg::PRBAR12_EL2, + 58225 => SysReg::PRLAR12_EL2, + 58228 => SysReg::PRBAR13_EL2, + 58229 => SysReg::PRLAR13_EL2, + 58232 => SysReg::PRBAR14_EL2, + 58233 => SysReg::PRLAR14_EL2, + 58236 => SysReg::PRBAR15_EL2, + 58237 => SysReg::PRLAR15_EL2, + 58568 => SysReg::PMSCR_EL2, + 58579 => SysReg::PMBSR_EL2, + 58587 => SysReg::TRBSR_EL2, + 58633 => SysReg::MAIR2_EL2, + 58640 => SysReg::MAIR_EL2, + 58642 => SysReg::PIRE0_EL2, + 58643 => SysReg::PIR_EL2, + 58644 => SysReg::POR_EL2, + 58645 => SysReg::S2PIR_EL2, + 58646 => SysReg::TTTBRU_EL2, + 58647 => SysReg::TTTBRP_EL2, + 58648 => SysReg::AMAIR_EL2, + 58649 => SysReg::AMAIR2_EL2, + 58656 => SysReg::MPAMHCR_EL2, + 58657 => SysReg::MPAMVPMV_EL2, + 58664 => SysReg::MPAM2_EL2, + 58666 => SysReg::MPAMCTL_EL2, + 58668 => SysReg::MPAMBW2_EL2, + 58670 => SysReg::MPAMBWCAP_EL2, + 58672 => SysReg::MPAMVPM0_EL2, + 58673 => SysReg::MPAMVPM1_EL2, + 58674 => SysReg::MPAMVPM2_EL2, + 58675 => SysReg::MPAMVPM3_EL2, + 58676 => SysReg::MPAMVPM4_EL2, + 58677 => SysReg::MPAMVPM5_EL2, + 58678 => SysReg::MPAMVPM6_EL2, + 58679 => SysReg::MPAMVPM7_EL2, + 58680 => SysReg::MPAMVIDCR_EL2, + 58681 => SysReg::MPAMVIDSR_EL2, + 58688 => SysReg::MECID_P0_EL2, + 58689 => SysReg::MECID_A0_EL2, + 58690 => SysReg::MECID_P1_EL2, + 58691 => SysReg::MECID_A1_EL2, + 58695 => SysReg::MECIDR_EL2, + 58696 => SysReg::VMECID_P_EL2, + 58697 => SysReg::VMECID_A_EL2, + 58880 => SysReg::VBAR_EL2, + 58881 => SysReg::RVBAR_EL2, + 58882 => SysReg::RMR_EL2, + 58889 => SysReg::VDISR_EL2, + 58944 => SysReg::ICH_AP0R0_EL2, + 58945 => SysReg::ICH_AP0R1_EL2, + 58946 => SysReg::ICH_AP0R2_EL2, + 58947 => SysReg::ICH_AP0R3_EL2, + 58948 => SysReg::ICH_APR_EL2, + 58949 => SysReg::ICH_HPPIR_EL2, + 58952 => SysReg::ICH_AP1R0_EL2, + 58953 => SysReg::ICH_AP1R1_EL2, + 58954 => SysReg::ICH_AP1R2_EL2, + 58955 => SysReg::ICH_AP1R3_EL2, + 58956 => SysReg::ICH_HFGRTR_EL2, + 58957 => SysReg::ICC_SRE_EL2, + 58958 => SysReg::ICH_HFGWTR_EL2, + 58959 => SysReg::ICH_HFGITR_EL2, + 58960 => SysReg::ICH_PPI_DVIR0_EL2, + 58961 => SysReg::ICH_PPI_DVIR1_EL2, + 58962 => SysReg::ICH_PPI_ENABLER0_EL2, + 58963 => SysReg::ICH_PPI_ENABLER1_EL2, + 58964 => SysReg::ICH_PPI_PENDR0_EL2, + 58965 => SysReg::ICH_PPI_PENDR1_EL2, + 58966 => SysReg::ICH_PPI_ACTIVER0_EL2, + 58967 => SysReg::ICH_PPI_ACTIVER1_EL2, + 58968 => SysReg::ICH_HCR_EL2, + 58969 => SysReg::ICH_VTR_EL2, + 58970 => SysReg::ICH_MISR_EL2, + 58971 => SysReg::ICH_EISR_EL2, + 58972 => SysReg::ICH_VCTLR_EL2, + 58973 => SysReg::ICH_ELRSR_EL2, + 58974 => SysReg::ICH_CONTEXTR_EL2, + 58975 => SysReg::ICH_VMCR_EL2, + 58976 => SysReg::ICH_LR0_EL2, + 58977 => SysReg::ICH_LR1_EL2, + 58978 => SysReg::ICH_LR2_EL2, + 58979 => SysReg::ICH_LR3_EL2, + 58980 => SysReg::ICH_LR4_EL2, + 58981 => SysReg::ICH_LR5_EL2, + 58982 => SysReg::ICH_LR6_EL2, + 58983 => SysReg::ICH_LR7_EL2, + 58984 => SysReg::ICH_LR8_EL2, + 58985 => SysReg::ICH_LR9_EL2, + 58986 => SysReg::ICH_LR10_EL2, + 58987 => SysReg::ICH_LR11_EL2, + 58988 => SysReg::ICH_LR12_EL2, + 58989 => SysReg::ICH_LR13_EL2, + 58990 => SysReg::ICH_LR14_EL2, + 58991 => SysReg::ICH_LR15_EL2, + 58992 => SysReg::ICH_PPI_PRIORITYR0_EL2, + 58993 => SysReg::ICH_PPI_PRIORITYR1_EL2, + 58994 => SysReg::ICH_PPI_PRIORITYR2_EL2, + 58995 => SysReg::ICH_PPI_PRIORITYR3_EL2, + 58996 => SysReg::ICH_PPI_PRIORITYR4_EL2, + 58997 => SysReg::ICH_PPI_PRIORITYR5_EL2, + 58998 => SysReg::ICH_PPI_PRIORITYR6_EL2, + 58999 => SysReg::ICH_PPI_PRIORITYR7_EL2, + 59000 => SysReg::ICH_PPI_PRIORITYR8_EL2, + 59001 => SysReg::ICH_PPI_PRIORITYR9_EL2, + 59002 => SysReg::ICH_PPI_PRIORITYR10_EL2, + 59003 => SysReg::ICH_PPI_PRIORITYR11_EL2, + 59004 => SysReg::ICH_PPI_PRIORITYR12_EL2, + 59005 => SysReg::ICH_PPI_PRIORITYR13_EL2, + 59006 => SysReg::ICH_PPI_PRIORITYR14_EL2, + 59007 => SysReg::ICH_PPI_PRIORITYR15_EL2, + 59008 => SysReg::TPIDR3_EL2, + 59009 => SysReg::CONTEXTIDR_EL2, + 59010 => SysReg::TPIDR_EL2, + 59015 => SysReg::SCXTNUM_EL2, + 59072 => SysReg::AMEVCNTVOFF00_EL2, + 59073 => SysReg::AMEVCNTVOFF01_EL2, + 59074 => SysReg::AMEVCNTVOFF02_EL2, + 59075 => SysReg::AMEVCNTVOFF03_EL2, + 59076 => SysReg::AMEVCNTVOFF04_EL2, + 59077 => SysReg::AMEVCNTVOFF05_EL2, + 59078 => SysReg::AMEVCNTVOFF06_EL2, + 59079 => SysReg::AMEVCNTVOFF07_EL2, + 59080 => SysReg::AMEVCNTVOFF08_EL2, + 59081 => SysReg::AMEVCNTVOFF09_EL2, + 59082 => SysReg::AMEVCNTVOFF010_EL2, + 59083 => SysReg::AMEVCNTVOFF011_EL2, + 59084 => SysReg::AMEVCNTVOFF012_EL2, + 59085 => SysReg::AMEVCNTVOFF013_EL2, + 59086 => SysReg::AMEVCNTVOFF014_EL2, + 59087 => SysReg::AMEVCNTVOFF015_EL2, + 59088 => SysReg::AMEVCNTVOFF10_EL2, + 59089 => SysReg::AMEVCNTVOFF11_EL2, + 59090 => SysReg::AMEVCNTVOFF12_EL2, + 59091 => SysReg::AMEVCNTVOFF13_EL2, + 59092 => SysReg::AMEVCNTVOFF14_EL2, + 59093 => SysReg::AMEVCNTVOFF15_EL2, + 59094 => SysReg::AMEVCNTVOFF16_EL2, + 59095 => SysReg::AMEVCNTVOFF17_EL2, + 59096 => SysReg::AMEVCNTVOFF18_EL2, + 59097 => SysReg::AMEVCNTVOFF19_EL2, + 59098 => SysReg::AMEVCNTVOFF110_EL2, + 59099 => SysReg::AMEVCNTVOFF111_EL2, + 59100 => SysReg::AMEVCNTVOFF112_EL2, + 59101 => SysReg::AMEVCNTVOFF113_EL2, + 59102 => SysReg::AMEVCNTVOFF114_EL2, + 59103 => SysReg::AMEVCNTVOFF115_EL2, + 59139 => SysReg::CNTVOFF_EL2, + 59140 => SysReg::CNTSCALE_EL2, + 59141 => SysReg::CNTISCALE_EL2, + 59142 => SysReg::CNTPOFF_EL2, + 59143 => SysReg::CNTVFRQ_EL2, + 59144 => SysReg::CNTHCTL_EL2, + 59152 => SysReg::CNTHP_TVAL_EL2, + 59153 => SysReg::CNTHP_CTL_EL2, + 59154 => SysReg::CNTHP_CVAL_EL2, + 59160 => SysReg::CNTHV_TVAL_EL2, + 59161 => SysReg::CNTHV_CTL_EL2, + 59162 => SysReg::CNTHV_CVAL_EL2, + 59168 => SysReg::CNTHVS_TVAL_EL2, + 59169 => SysReg::CNTHVS_CTL_EL2, + 59170 => SysReg::CNTHVS_CVAL_EL2, + 59176 => SysReg::CNTHPS_TVAL_EL2, + 59177 => SysReg::CNTHPS_CTL_EL2, + 59178 => SysReg::CNTHPS_CVAL_EL2, + 59520 => SysReg::SCTLR_EL12, + 59521 => SysReg::ACTLR_EL12, + 59522 => SysReg::CPACR_EL12, + 59523 => SysReg::SCTLR2_EL12, + 59536 => SysReg::ZCR_EL12, + 59537 => SysReg::TRFCR_EL12, + 59539 => SysReg::TRCITECR_EL12, + 59542 => SysReg::SMCR_EL12, + 59552 => SysReg::SCTLRMASK_EL12, + 59553 => SysReg::ACTLRMASK_EL12, + 59554 => SysReg::CPACRMASK_EL12, + 59555 => SysReg::SCTLR2MASK_EL12, + 59648 => SysReg::TTBR0_EL12, + 59649 => SysReg::TTBR1_EL12, + 59650 => SysReg::TCR_EL12, + 59651 => SysReg::TCR2_EL12, + 59652 => SysReg::IRTBRU_EL12, + 59653 => SysReg::IRTBRP_EL12, + 59654 => SysReg::DPOTBR0_EL12, + 59655 => SysReg::DPOTBR1_EL12, + 59663 => SysReg::LDSTT_EL12, + 59668 => SysReg::TPMIN0_EL12, + 59669 => SysReg::TPMAX0_EL12, + 59670 => SysReg::TPMIN1_EL12, + 59671 => SysReg::TPMAX1_EL12, + 59688 => SysReg::GCSCR_EL12, + 59689 => SysReg::GCSPR_EL12, + 59706 => SysReg::TCRMASK_EL12, + 59707 => SysReg::TCR2MASK_EL12, + 59792 => SysReg::FGDTP0_EL12, + 59793 => SysReg::FGDTP1_EL12, + 59794 => SysReg::FGDTP2_EL12, + 59795 => SysReg::FGDTP3_EL12, + 59796 => SysReg::FGDTP4_EL12, + 59797 => SysReg::FGDTP5_EL12, + 59798 => SysReg::FGDTP6_EL12, + 59799 => SysReg::FGDTP7_EL12, + 59800 => SysReg::FGDTP8_EL12, + 59801 => SysReg::FGDTP9_EL12, + 59802 => SysReg::FGDTP10_EL12, + 59803 => SysReg::FGDTP11_EL12, + 59804 => SysReg::FGDTP12_EL12, + 59805 => SysReg::FGDTP13_EL12, + 59806 => SysReg::FGDTP14_EL12, + 59807 => SysReg::FGDTP15_EL12, + 59808 => SysReg::FGDTU0_EL12, + 59809 => SysReg::FGDTU1_EL12, + 59810 => SysReg::FGDTU2_EL12, + 59811 => SysReg::FGDTU3_EL12, + 59812 => SysReg::FGDTU4_EL12, + 59813 => SysReg::FGDTU5_EL12, + 59814 => SysReg::FGDTU6_EL12, + 59815 => SysReg::FGDTU7_EL12, + 59816 => SysReg::FGDTU8_EL12, + 59817 => SysReg::FGDTU9_EL12, + 59818 => SysReg::FGDTU10_EL12, + 59819 => SysReg::FGDTU11_EL12, + 59820 => SysReg::FGDTU12_EL12, + 59821 => SysReg::FGDTU13_EL12, + 59822 => SysReg::FGDTU14_EL12, + 59823 => SysReg::FGDTU15_EL12, + 59824 => SysReg::AFGDTP0_EL12, + 59825 => SysReg::AFGDTP1_EL12, + 59826 => SysReg::AFGDTP2_EL12, + 59827 => SysReg::AFGDTP3_EL12, + 59828 => SysReg::AFGDTP4_EL12, + 59829 => SysReg::AFGDTP5_EL12, + 59830 => SysReg::AFGDTP6_EL12, + 59831 => SysReg::AFGDTP7_EL12, + 59832 => SysReg::AFGDTP8_EL12, + 59833 => SysReg::AFGDTP9_EL12, + 59834 => SysReg::AFGDTP10_EL12, + 59835 => SysReg::AFGDTP11_EL12, + 59836 => SysReg::AFGDTP12_EL12, + 59837 => SysReg::AFGDTP13_EL12, + 59838 => SysReg::AFGDTP14_EL12, + 59839 => SysReg::AFGDTP15_EL12, + 59840 => SysReg::AFGDTU0_EL12, + 59841 => SysReg::AFGDTU1_EL12, + 59842 => SysReg::AFGDTU2_EL12, + 59843 => SysReg::AFGDTU3_EL12, + 59844 => SysReg::AFGDTU4_EL12, + 59845 => SysReg::AFGDTU5_EL12, + 59846 => SysReg::AFGDTU6_EL12, + 59847 => SysReg::AFGDTU7_EL12, + 59848 => SysReg::AFGDTU8_EL12, + 59849 => SysReg::AFGDTU9_EL12, + 59850 => SysReg::AFGDTU10_EL12, + 59851 => SysReg::AFGDTU11_EL12, + 59852 => SysReg::AFGDTU12_EL12, + 59853 => SysReg::AFGDTU13_EL12, + 59854 => SysReg::AFGDTU14_EL12, + 59855 => SysReg::AFGDTU15_EL12, + 59904 => SysReg::SPSR_EL12, + 59905 => SysReg::ELR_EL12, + 59906 => SysReg::STINDEX_EL12, + 59907 => SysReg::TINDEX_EL12, + 60040 => SysReg::AFSR0_EL12, + 60041 => SysReg::AFSR1_EL12, + 60048 => SysReg::ESR_EL12, + 60080 => SysReg::TFSR_EL12, + 60160 => SysReg::FAR_EL12, + 60165 => SysReg::PFAR_EL12, + 60616 => SysReg::PMSCR_EL12, + 60627 => SysReg::PMBSR_EL12, + 60635 => SysReg::TRBSR_EL12, + 60688 => SysReg::MAIR_EL12, + 60689 => SysReg::MAIR2_EL12, + 60690 => SysReg::PIRE0_EL12, + 60691 => SysReg::PIR_EL12, + 60692 => SysReg::POR_EL12, + 60694 => SysReg::TTTBRU_EL12, + 60695 => SysReg::TTTBRP_EL12, + 60696 => SysReg::AMAIR_EL12, + 60697 => SysReg::AMAIR2_EL12, + 60712 => SysReg::MPAM1_EL12, + 60714 => SysReg::MPAMCTL_EL12, + 60716 => SysReg::MPAMBW1_EL12, + 60928 => SysReg::VBAR_EL12, + 61056 => SysReg::TPIDR3_EL12, + 61057 => SysReg::CONTEXTIDR_EL12, + 61063 => SysReg::SCXTNUM_EL12, + 61192 => SysReg::CNTKCTL_EL12, + 61200 => SysReg::CNTP_TVAL_EL02, + 61201 => SysReg::CNTP_CTL_EL02, + 61202 => SysReg::CNTP_CVAL_EL02, + 61208 => SysReg::CNTV_TVAL_EL02, + 61209 => SysReg::CNTV_CTL_EL02, + 61210 => SysReg::CNTV_CVAL_EL02, + 61568 => SysReg::SCTLR_EL3, + 61569 => SysReg::ACTLR_EL3, + 61571 => SysReg::SCTLR2_EL3, + 61576 => SysReg::SCR_EL3, + 61577 => SysReg::SDER32_EL3, + 61578 => SysReg::CPTR_EL3, + 61581 => SysReg::FGWTE3_EL3, + 61584 => SysReg::ZCR_EL3, + 61590 => SysReg::SMCR_EL3, + 61593 => SysReg::MDCR_EL3, + 61696 => SysReg::TTBR0_EL3, + 61698 => SysReg::TCR_EL3, + 61701 => SysReg::IRTBRP_EL3, + 61702 => SysReg::DPOTBR0_EL3, + 61708 => SysReg::GPTBR_EL3, + 61709 => SysReg::GPCBW_EL3, + 61710 => SysReg::GPCCR_EL3, + 61736 => SysReg::GCSCR_EL3, + 61737 => SysReg::GCSPR_EL3, + 61840 => SysReg::FGDTP0_EL3, + 61841 => SysReg::FGDTP1_EL3, + 61842 => SysReg::FGDTP2_EL3, + 61843 => SysReg::FGDTP3_EL3, + 61844 => SysReg::FGDTP4_EL3, + 61845 => SysReg::FGDTP5_EL3, + 61846 => SysReg::FGDTP6_EL3, + 61847 => SysReg::FGDTP7_EL3, + 61848 => SysReg::FGDTP8_EL3, + 61849 => SysReg::FGDTP9_EL3, + 61850 => SysReg::FGDTP10_EL3, + 61851 => SysReg::FGDTP11_EL3, + 61852 => SysReg::FGDTP12_EL3, + 61853 => SysReg::FGDTP13_EL3, + 61854 => SysReg::FGDTP14_EL3, + 61855 => SysReg::FGDTP15_EL3, + 61872 => SysReg::AFGDTP0_EL3, + 61873 => SysReg::AFGDTP1_EL3, + 61874 => SysReg::AFGDTP2_EL3, + 61875 => SysReg::AFGDTP3_EL3, + 61876 => SysReg::AFGDTP4_EL3, + 61877 => SysReg::AFGDTP5_EL3, + 61878 => SysReg::AFGDTP6_EL3, + 61879 => SysReg::AFGDTP7_EL3, + 61880 => SysReg::AFGDTP8_EL3, + 61881 => SysReg::AFGDTP9_EL3, + 61882 => SysReg::AFGDTP10_EL3, + 61883 => SysReg::AFGDTP11_EL3, + 61884 => SysReg::AFGDTP12_EL3, + 61885 => SysReg::AFGDTP13_EL3, + 61886 => SysReg::AFGDTP14_EL3, + 61887 => SysReg::AFGDTP15_EL3, + 61952 => SysReg::SPSR_EL3, + 61953 => SysReg::ELR_EL3, + 61954 => SysReg::STINDEX_EL3, + 61955 => SysReg::TINDEX_EL3, + 61960 => SysReg::SP_EL2, + 62088 => SysReg::AFSR0_EL3, + 62089 => SysReg::AFSR1_EL3, + 62096 => SysReg::ESR_EL3, + 62099 => SysReg::VSESR_EL3, + 62128 => SysReg::TFSR_EL3, + 62208 => SysReg::FAR_EL3, + 62213 => SysReg::MFAR_EL3, + 62675 => SysReg::PMBSR_EL3, + 62683 => SysReg::TRBSR_EL3, + 62729 => SysReg::MAIR2_EL3, + 62736 => SysReg::MAIR_EL3, + 62739 => SysReg::PIR_EL3, + 62740 => SysReg::POR_EL3, + 62743 => SysReg::TTTBRP_EL3, + 62744 => SysReg::AMAIR_EL3, + 62745 => SysReg::AMAIR2_EL3, + 62760 => SysReg::MPAM3_EL3, + 62762 => SysReg::MPAMCTL_EL3, + 62764 => SysReg::MPAMBW3_EL3, + 62777 => SysReg::MPAMVIDSR_EL3, + 62801 => SysReg::MECID_RL_A_EL3, + 62976 => SysReg::VBAR_EL3, + 62977 => SysReg::RVBAR_EL3, + 62978 => SysReg::RMR_EL3, + 62985 => SysReg::VDISR_EL3, + 63040 => SysReg::ICC_APR_EL3, + 63041 => SysReg::ICC_PCR_EL3, + 63042 => SysReg::ICC_DOMHPPIR_EL3, + 63044 => SysReg::ICC_PPI_DOMAINR0_EL3, + 63045 => SysReg::ICC_PPI_DOMAINR1_EL3, + 63046 => SysReg::ICC_PPI_DOMAINR2_EL3, + 63047 => SysReg::ICC_PPI_DOMAINR3_EL3, + 63048 => SysReg::ICC_CR0_EL3, + 63049 => SysReg::ICC_HPPIR_EL3, + 63076 => SysReg::ICC_CTLR_EL3, + 63077 => SysReg::ICC_SRE_EL3, + 63079 => SysReg::ICC_IGRPEN1_EL3, + 63104 => SysReg::TPIDR3_EL3, + 63106 => SysReg::TPIDR_EL3, + 63111 => SysReg::SCXTNUM_EL3, + 65296 => SysReg::CNTPS_TVAL_EL1, + 65297 => SysReg::CNTPS_CTL_EL1, + 65298 => SysReg::CNTPS_CVAL_EL1, + 1665 => SysReg::NUM_TARGET_SYSREGS, + _ => SysReg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/arm.rs b/vendor/lief/api/rust/crates/lief/src/assembly/arm.rs new file mode 100644 index 0000000..1c81ac0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/arm.rs @@ -0,0 +1,11 @@ +//! ARM architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/arm/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/arm/instruction.rs new file mode 100644 index 0000000..f4f479f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/arm/instruction.rs @@ -0,0 +1,36 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +/// This structure represents an ARM/Thumb instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/arm/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/arm/opcodes.rs new file mode 100644 index 0000000..da7302a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/arm/opcodes.rs @@ -0,0 +1,9053 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ADDSri, + ADDSrr, + ADDSrsi, + ADDSrsr, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + ASRi, + ASRr, + ASRs1, + B, + BCCZi64, + BCCi64, + BLX_noip, + BLX_pred_noip, + BL_PUSHLR, + BMOVPCB_CALL, + BMOVPCRX_CALL, + BR_JTadd, + BR_JTm_i12, + BR_JTm_rs, + BR_JTr, + BX_CALL, + CMP_SWAP_16, + CMP_SWAP_32, + CMP_SWAP_64, + CMP_SWAP_8, + CONSTPOOL_ENTRY, + COPY_STRUCT_BYVAL_I32, + ITasm, + Int_eh_sjlj_dispatchsetup, + Int_eh_sjlj_longjmp, + Int_eh_sjlj_setjmp, + Int_eh_sjlj_setjmp_nofp, + Int_eh_sjlj_setup_dispatch, + JUMPTABLE_ADDRS, + JUMPTABLE_INSTS, + JUMPTABLE_TBB, + JUMPTABLE_TBH, + KCFI_CHECK_ARM, + KCFI_CHECK_Thumb1, + KCFI_CHECK_Thumb2, + LDMIA_RET, + LDRBT_POST, + LDRConstPool, + LDRHTii, + LDRLIT_ga_abs, + LDRLIT_ga_pcrel, + LDRLIT_ga_pcrel_ldr, + LDRSBTii, + LDRSHTii, + LDRT_POST, + LEApcrel, + LEApcrelJT, + LOADDUAL, + LSLi, + LSLr, + LSRi, + LSRr, + LSRs1, + MEMCPY, + MLAv5, + MOVCCi, + MOVCCi16, + MOVCCi32imm, + MOVCCr, + MOVCCsi, + MOVCCsr, + MOVPCRX, + MOVTi16_ga_pcrel, + MOV_ga_pcrel, + MOV_ga_pcrel_ldr, + MOVi16_ga_pcrel, + MOVi32imm, + MQPRCopy, + MQQPRLoad, + MQQPRStore, + MQQQQPRLoad, + MQQQQPRStore, + MULv5, + MVE_MEMCPYLOOPINST, + MVE_MEMSETLOOPINST, + MVNCCi, + PICADD, + PICLDR, + PICLDRB, + PICLDRH, + PICLDRSB, + PICLDRSH, + PICSTR, + PICSTRB, + PICSTRH, + RORi, + RORr, + RRX, + RRXi, + RSBSri, + RSBSrsi, + RSBSrsr, + SEH_EpilogEnd, + SEH_EpilogStart, + SEH_Nop, + SEH_Nop_Ret, + SEH_PrologEnd, + SEH_SaveFRegs, + SEH_SaveLR, + SEH_SaveRegs, + SEH_SaveRegs_Ret, + SEH_SaveSP, + SEH_StackAlloc, + SMLALv5, + SMULLv5, + SPACE, + STOREDUAL, + STRBT_POST, + STRBi_preidx, + STRBr_preidx, + STRH_preidx, + STRT_POST, + STRi_preidx, + STRr_preidx, + SUBS_PC_LR, + SUBSri, + SUBSrr, + SUBSrsi, + SUBSrsr, + SpeculationBarrierISBDSBEndBB, + SpeculationBarrierSBEndBB, + TAILJMPd, + TAILJMPr, + TAILJMPr4, + TCRETURNdi, + TCRETURNri, + TCRETURNrinotr12, + TPsoft, + UMLALv5, + UMULLv5, + VLD1LNdAsm_16, + VLD1LNdAsm_32, + VLD1LNdAsm_8, + VLD1LNdWB_fixed_Asm_16, + VLD1LNdWB_fixed_Asm_32, + VLD1LNdWB_fixed_Asm_8, + VLD1LNdWB_register_Asm_16, + VLD1LNdWB_register_Asm_32, + VLD1LNdWB_register_Asm_8, + VLD2LNdAsm_16, + VLD2LNdAsm_32, + VLD2LNdAsm_8, + VLD2LNdWB_fixed_Asm_16, + VLD2LNdWB_fixed_Asm_32, + VLD2LNdWB_fixed_Asm_8, + VLD2LNdWB_register_Asm_16, + VLD2LNdWB_register_Asm_32, + VLD2LNdWB_register_Asm_8, + VLD2LNqAsm_16, + VLD2LNqAsm_32, + VLD2LNqWB_fixed_Asm_16, + VLD2LNqWB_fixed_Asm_32, + VLD2LNqWB_register_Asm_16, + VLD2LNqWB_register_Asm_32, + VLD3DUPdAsm_16, + VLD3DUPdAsm_32, + VLD3DUPdAsm_8, + VLD3DUPdWB_fixed_Asm_16, + VLD3DUPdWB_fixed_Asm_32, + VLD3DUPdWB_fixed_Asm_8, + VLD3DUPdWB_register_Asm_16, + VLD3DUPdWB_register_Asm_32, + VLD3DUPdWB_register_Asm_8, + VLD3DUPqAsm_16, + VLD3DUPqAsm_32, + VLD3DUPqAsm_8, + VLD3DUPqWB_fixed_Asm_16, + VLD3DUPqWB_fixed_Asm_32, + VLD3DUPqWB_fixed_Asm_8, + VLD3DUPqWB_register_Asm_16, + VLD3DUPqWB_register_Asm_32, + VLD3DUPqWB_register_Asm_8, + VLD3LNdAsm_16, + VLD3LNdAsm_32, + VLD3LNdAsm_8, + VLD3LNdWB_fixed_Asm_16, + VLD3LNdWB_fixed_Asm_32, + VLD3LNdWB_fixed_Asm_8, + VLD3LNdWB_register_Asm_16, + VLD3LNdWB_register_Asm_32, + VLD3LNdWB_register_Asm_8, + VLD3LNqAsm_16, + VLD3LNqAsm_32, + VLD3LNqWB_fixed_Asm_16, + VLD3LNqWB_fixed_Asm_32, + VLD3LNqWB_register_Asm_16, + VLD3LNqWB_register_Asm_32, + VLD3dAsm_16, + VLD3dAsm_32, + VLD3dAsm_8, + VLD3dWB_fixed_Asm_16, + VLD3dWB_fixed_Asm_32, + VLD3dWB_fixed_Asm_8, + VLD3dWB_register_Asm_16, + VLD3dWB_register_Asm_32, + VLD3dWB_register_Asm_8, + VLD3qAsm_16, + VLD3qAsm_32, + VLD3qAsm_8, + VLD3qWB_fixed_Asm_16, + VLD3qWB_fixed_Asm_32, + VLD3qWB_fixed_Asm_8, + VLD3qWB_register_Asm_16, + VLD3qWB_register_Asm_32, + VLD3qWB_register_Asm_8, + VLD4DUPdAsm_16, + VLD4DUPdAsm_32, + VLD4DUPdAsm_8, + VLD4DUPdWB_fixed_Asm_16, + VLD4DUPdWB_fixed_Asm_32, + VLD4DUPdWB_fixed_Asm_8, + VLD4DUPdWB_register_Asm_16, + VLD4DUPdWB_register_Asm_32, + VLD4DUPdWB_register_Asm_8, + VLD4DUPqAsm_16, + VLD4DUPqAsm_32, + VLD4DUPqAsm_8, + VLD4DUPqWB_fixed_Asm_16, + VLD4DUPqWB_fixed_Asm_32, + VLD4DUPqWB_fixed_Asm_8, + VLD4DUPqWB_register_Asm_16, + VLD4DUPqWB_register_Asm_32, + VLD4DUPqWB_register_Asm_8, + VLD4LNdAsm_16, + VLD4LNdAsm_32, + VLD4LNdAsm_8, + VLD4LNdWB_fixed_Asm_16, + VLD4LNdWB_fixed_Asm_32, + VLD4LNdWB_fixed_Asm_8, + VLD4LNdWB_register_Asm_16, + VLD4LNdWB_register_Asm_32, + VLD4LNdWB_register_Asm_8, + VLD4LNqAsm_16, + VLD4LNqAsm_32, + VLD4LNqWB_fixed_Asm_16, + VLD4LNqWB_fixed_Asm_32, + VLD4LNqWB_register_Asm_16, + VLD4LNqWB_register_Asm_32, + VLD4dAsm_16, + VLD4dAsm_32, + VLD4dAsm_8, + VLD4dWB_fixed_Asm_16, + VLD4dWB_fixed_Asm_32, + VLD4dWB_fixed_Asm_8, + VLD4dWB_register_Asm_16, + VLD4dWB_register_Asm_32, + VLD4dWB_register_Asm_8, + VLD4qAsm_16, + VLD4qAsm_32, + VLD4qAsm_8, + VLD4qWB_fixed_Asm_16, + VLD4qWB_fixed_Asm_32, + VLD4qWB_fixed_Asm_8, + VLD4qWB_register_Asm_16, + VLD4qWB_register_Asm_32, + VLD4qWB_register_Asm_8, + VMOVD0, + VMOVDcc, + VMOVHcc, + VMOVQ0, + VMOVScc, + VST1LNdAsm_16, + VST1LNdAsm_32, + VST1LNdAsm_8, + VST1LNdWB_fixed_Asm_16, + VST1LNdWB_fixed_Asm_32, + VST1LNdWB_fixed_Asm_8, + VST1LNdWB_register_Asm_16, + VST1LNdWB_register_Asm_32, + VST1LNdWB_register_Asm_8, + VST2LNdAsm_16, + VST2LNdAsm_32, + VST2LNdAsm_8, + VST2LNdWB_fixed_Asm_16, + VST2LNdWB_fixed_Asm_32, + VST2LNdWB_fixed_Asm_8, + VST2LNdWB_register_Asm_16, + VST2LNdWB_register_Asm_32, + VST2LNdWB_register_Asm_8, + VST2LNqAsm_16, + VST2LNqAsm_32, + VST2LNqWB_fixed_Asm_16, + VST2LNqWB_fixed_Asm_32, + VST2LNqWB_register_Asm_16, + VST2LNqWB_register_Asm_32, + VST3LNdAsm_16, + VST3LNdAsm_32, + VST3LNdAsm_8, + VST3LNdWB_fixed_Asm_16, + VST3LNdWB_fixed_Asm_32, + VST3LNdWB_fixed_Asm_8, + VST3LNdWB_register_Asm_16, + VST3LNdWB_register_Asm_32, + VST3LNdWB_register_Asm_8, + VST3LNqAsm_16, + VST3LNqAsm_32, + VST3LNqWB_fixed_Asm_16, + VST3LNqWB_fixed_Asm_32, + VST3LNqWB_register_Asm_16, + VST3LNqWB_register_Asm_32, + VST3dAsm_16, + VST3dAsm_32, + VST3dAsm_8, + VST3dWB_fixed_Asm_16, + VST3dWB_fixed_Asm_32, + VST3dWB_fixed_Asm_8, + VST3dWB_register_Asm_16, + VST3dWB_register_Asm_32, + VST3dWB_register_Asm_8, + VST3qAsm_16, + VST3qAsm_32, + VST3qAsm_8, + VST3qWB_fixed_Asm_16, + VST3qWB_fixed_Asm_32, + VST3qWB_fixed_Asm_8, + VST3qWB_register_Asm_16, + VST3qWB_register_Asm_32, + VST3qWB_register_Asm_8, + VST4LNdAsm_16, + VST4LNdAsm_32, + VST4LNdAsm_8, + VST4LNdWB_fixed_Asm_16, + VST4LNdWB_fixed_Asm_32, + VST4LNdWB_fixed_Asm_8, + VST4LNdWB_register_Asm_16, + VST4LNdWB_register_Asm_32, + VST4LNdWB_register_Asm_8, + VST4LNqAsm_16, + VST4LNqAsm_32, + VST4LNqWB_fixed_Asm_16, + VST4LNqWB_fixed_Asm_32, + VST4LNqWB_register_Asm_16, + VST4LNqWB_register_Asm_32, + VST4dAsm_16, + VST4dAsm_32, + VST4dAsm_8, + VST4dWB_fixed_Asm_16, + VST4dWB_fixed_Asm_32, + VST4dWB_fixed_Asm_8, + VST4dWB_register_Asm_16, + VST4dWB_register_Asm_32, + VST4dWB_register_Asm_8, + VST4qAsm_16, + VST4qAsm_32, + VST4qAsm_8, + VST4qWB_fixed_Asm_16, + VST4qWB_fixed_Asm_32, + VST4qWB_fixed_Asm_8, + VST4qWB_register_Asm_16, + VST4qWB_register_Asm_32, + VST4qWB_register_Asm_8, + WIN__CHKSTK, + WIN__DBZCHK, + t2ADDSri, + t2ADDSrr, + t2ADDSrs, + t2BF_LabelPseudo, + t2BR_JT, + t2CALL_BTI, + t2DoLoopStart, + t2DoLoopStartTP, + t2LDMIA_RET, + t2LDRB_OFFSET_imm, + t2LDRB_POST_imm, + t2LDRB_PRE_imm, + t2LDRBpcrel, + t2LDRConstPool, + t2LDRH_OFFSET_imm, + t2LDRH_POST_imm, + t2LDRH_PRE_imm, + t2LDRHpcrel, + t2LDRLIT_ga_pcrel, + t2LDRSB_OFFSET_imm, + t2LDRSB_POST_imm, + t2LDRSB_PRE_imm, + t2LDRSBpcrel, + t2LDRSH_OFFSET_imm, + t2LDRSH_POST_imm, + t2LDRSH_PRE_imm, + t2LDRSHpcrel, + t2LDR_POST_imm, + t2LDR_PRE_imm, + t2LDRpci_pic, + t2LDRpcrel, + t2LEApcrel, + t2LEApcrelJT, + t2LoopDec, + t2LoopEnd, + t2LoopEndDec, + t2MOVCCasr, + t2MOVCCi, + t2MOVCCi16, + t2MOVCCi32imm, + t2MOVCClsl, + t2MOVCClsr, + t2MOVCCr, + t2MOVCCror, + t2MOVSsi, + t2MOVSsr, + t2MOVTi16_ga_pcrel, + t2MOV_ga_pcrel, + t2MOVi16_ga_pcrel, + t2MOVi32imm, + t2MOVsi, + t2MOVsr, + t2MVNCCi, + t2RSBSri, + t2RSBSrs, + t2STRB_OFFSET_imm, + t2STRB_POST_imm, + t2STRB_PRE_imm, + t2STRB_preidx, + t2STRH_OFFSET_imm, + t2STRH_POST_imm, + t2STRH_PRE_imm, + t2STRH_preidx, + t2STR_POST_imm, + t2STR_PRE_imm, + t2STR_preidx, + t2SUBSri, + t2SUBSrr, + t2SUBSrs, + t2SpeculationBarrierISBDSBEndBB, + t2SpeculationBarrierSBEndBB, + t2TBB_JT, + t2TBH_JT, + t2WhileLoopSetup, + t2WhileLoopStart, + t2WhileLoopStartLR, + t2WhileLoopStartTP, + tADCS, + tADDSi3, + tADDSi8, + tADDSrr, + tADDframe, + tADJCALLSTACKDOWN, + tADJCALLSTACKUP, + tBLXNS_CALL, + tBLXr_noip, + tBL_PUSHLR, + tBRIND, + tBR_JTr, + tBXNS_RET, + tBX_CALL, + tBX_RET, + tBX_RET_vararg, + tBfar, + tCMP_SWAP_16, + tCMP_SWAP_32, + tCMP_SWAP_8, + tLDMIA_UPD, + tLDRConstPool, + tLDRLIT_ga_abs, + tLDRLIT_ga_pcrel, + tLDR_postidx, + tLDRpci_pic, + tLEApcrel, + tLEApcrelJT, + tLSLSri, + tMOVCCr_pseudo, + tMOVi32imm, + tPOP_RET, + tRSBS, + tSBCS, + tSUBSi3, + tSUBSi8, + tSUBSrr, + tTAILJMPd, + tTAILJMPdND, + tTAILJMPr, + tTBB_JT, + tTBH_JT, + tTPsoft, + ADCri, + ADCrr, + ADCrsi, + ADCrsr, + ADDri, + ADDrr, + ADDrsi, + ADDrsr, + ADR, + AESD, + AESE, + AESIMC, + AESMC, + ANDri, + ANDrr, + ANDrsi, + ANDrsr, + BF16VDOTI_VDOTD, + BF16VDOTI_VDOTQ, + BF16VDOTS_VDOTD, + BF16VDOTS_VDOTQ, + BF16_VCVT, + BF16_VCVTB, + BF16_VCVTT, + BFC, + BFI, + BICri, + BICrr, + BICrsi, + BICrsr, + BKPT, + BL, + BLX, + BLX_pred, + BLXi, + BL_pred, + BX, + BXJ, + BX_RET, + BX_pred, + Bcc, + CDE_CX1, + CDE_CX1A, + CDE_CX1D, + CDE_CX1DA, + CDE_CX2, + CDE_CX2A, + CDE_CX2D, + CDE_CX2DA, + CDE_CX3, + CDE_CX3A, + CDE_CX3D, + CDE_CX3DA, + CDE_VCX1A_fpdp, + CDE_VCX1A_fpsp, + CDE_VCX1A_vec, + CDE_VCX1_fpdp, + CDE_VCX1_fpsp, + CDE_VCX1_vec, + CDE_VCX2A_fpdp, + CDE_VCX2A_fpsp, + CDE_VCX2A_vec, + CDE_VCX2_fpdp, + CDE_VCX2_fpsp, + CDE_VCX2_vec, + CDE_VCX3A_fpdp, + CDE_VCX3A_fpsp, + CDE_VCX3A_vec, + CDE_VCX3_fpdp, + CDE_VCX3_fpsp, + CDE_VCX3_vec, + CDP, + CDP2, + CLREX, + CLZ, + CMNri, + CMNzrr, + CMNzrsi, + CMNzrsr, + CMPri, + CMPrr, + CMPrsi, + CMPrsr, + CPS1p, + CPS2p, + CPS3p, + CRC32B, + CRC32CB, + CRC32CH, + CRC32CW, + CRC32H, + CRC32W, + DBG, + DMB, + DSB, + EORri, + EORrr, + EORrsi, + EORrsr, + ERET, + FCONSTD, + FCONSTH, + FCONSTS, + FLDMXDB_UPD, + FLDMXIA, + FLDMXIA_UPD, + FMSTAT, + FSTMXDB_UPD, + FSTMXIA, + FSTMXIA_UPD, + HINT, + HLT, + HVC, + ISB, + LDA, + LDAB, + LDAEX, + LDAEXB, + LDAEXD, + LDAEXH, + LDAH, + LDC2L_OFFSET, + LDC2L_OPTION, + LDC2L_POST, + LDC2L_PRE, + LDC2_OFFSET, + LDC2_OPTION, + LDC2_POST, + LDC2_PRE, + LDCL_OFFSET, + LDCL_OPTION, + LDCL_POST, + LDCL_PRE, + LDC_OFFSET, + LDC_OPTION, + LDC_POST, + LDC_PRE, + LDMDA, + LDMDA_UPD, + LDMDB, + LDMDB_UPD, + LDMIA, + LDMIA_UPD, + LDMIB, + LDMIB_UPD, + LDRBT_POST_IMM, + LDRBT_POST_REG, + LDRB_POST_IMM, + LDRB_POST_REG, + LDRB_PRE_IMM, + LDRB_PRE_REG, + LDRBi12, + LDRBrs, + LDRD, + LDRD_POST, + LDRD_PRE, + LDREX, + LDREXB, + LDREXD, + LDREXH, + LDRH, + LDRHTi, + LDRHTr, + LDRH_POST, + LDRH_PRE, + LDRSB, + LDRSBTi, + LDRSBTr, + LDRSB_POST, + LDRSB_PRE, + LDRSH, + LDRSHTi, + LDRSHTr, + LDRSH_POST, + LDRSH_PRE, + LDRT_POST_IMM, + LDRT_POST_REG, + LDR_POST_IMM, + LDR_POST_REG, + LDR_PRE_IMM, + LDR_PRE_REG, + LDRcp, + LDRi12, + LDRrs, + MCR, + MCR2, + MCRR, + MCRR2, + MLA, + MLS, + MOVPCLR, + MOVTi16, + MOVi, + MOVi16, + MOVr, + MOVr_TC, + MOVsi, + MOVsr, + MRC, + MRC2, + MRRC, + MRRC2, + MRS, + MRSbanked, + MRSsys, + MSR, + MSRbanked, + MSRi, + MUL, + MVE_ASRLi, + MVE_ASRLr, + MVE_DLSTP_16, + MVE_DLSTP_32, + MVE_DLSTP_64, + MVE_DLSTP_8, + MVE_LCTP, + MVE_LETP, + MVE_LSLLi, + MVE_LSLLr, + MVE_LSRL, + MVE_SQRSHR, + MVE_SQRSHRL, + MVE_SQSHL, + MVE_SQSHLL, + MVE_SRSHR, + MVE_SRSHRL, + MVE_UQRSHL, + MVE_UQRSHLL, + MVE_UQSHL, + MVE_UQSHLL, + MVE_URSHR, + MVE_URSHRL, + MVE_VABAVs16, + MVE_VABAVs32, + MVE_VABAVs8, + MVE_VABAVu16, + MVE_VABAVu32, + MVE_VABAVu8, + MVE_VABDf16, + MVE_VABDf32, + MVE_VABDs16, + MVE_VABDs32, + MVE_VABDs8, + MVE_VABDu16, + MVE_VABDu32, + MVE_VABDu8, + MVE_VABSf16, + MVE_VABSf32, + MVE_VABSs16, + MVE_VABSs32, + MVE_VABSs8, + MVE_VADC, + MVE_VADCI, + MVE_VADDLVs32acc, + MVE_VADDLVs32no_acc, + MVE_VADDLVu32acc, + MVE_VADDLVu32no_acc, + MVE_VADDVs16acc, + MVE_VADDVs16no_acc, + MVE_VADDVs32acc, + MVE_VADDVs32no_acc, + MVE_VADDVs8acc, + MVE_VADDVs8no_acc, + MVE_VADDVu16acc, + MVE_VADDVu16no_acc, + MVE_VADDVu32acc, + MVE_VADDVu32no_acc, + MVE_VADDVu8acc, + MVE_VADDVu8no_acc, + MVE_VADD_qr_f16, + MVE_VADD_qr_f32, + MVE_VADD_qr_i16, + MVE_VADD_qr_i32, + MVE_VADD_qr_i8, + MVE_VADDf16, + MVE_VADDf32, + MVE_VADDi16, + MVE_VADDi32, + MVE_VADDi8, + MVE_VAND, + MVE_VBIC, + MVE_VBICimmi16, + MVE_VBICimmi32, + MVE_VBRSR16, + MVE_VBRSR32, + MVE_VBRSR8, + MVE_VCADDf16, + MVE_VCADDf32, + MVE_VCADDi16, + MVE_VCADDi32, + MVE_VCADDi8, + MVE_VCLSs16, + MVE_VCLSs32, + MVE_VCLSs8, + MVE_VCLZs16, + MVE_VCLZs32, + MVE_VCLZs8, + MVE_VCMLAf16, + MVE_VCMLAf32, + MVE_VCMPf16, + MVE_VCMPf16r, + MVE_VCMPf32, + MVE_VCMPf32r, + MVE_VCMPi16, + MVE_VCMPi16r, + MVE_VCMPi32, + MVE_VCMPi32r, + MVE_VCMPi8, + MVE_VCMPi8r, + MVE_VCMPs16, + MVE_VCMPs16r, + MVE_VCMPs32, + MVE_VCMPs32r, + MVE_VCMPs8, + MVE_VCMPs8r, + MVE_VCMPu16, + MVE_VCMPu16r, + MVE_VCMPu32, + MVE_VCMPu32r, + MVE_VCMPu8, + MVE_VCMPu8r, + MVE_VCMULf16, + MVE_VCMULf32, + MVE_VCTP16, + MVE_VCTP32, + MVE_VCTP64, + MVE_VCTP8, + MVE_VCVTf16f32bh, + MVE_VCVTf16f32th, + MVE_VCVTf16s16_fix, + MVE_VCVTf16s16n, + MVE_VCVTf16u16_fix, + MVE_VCVTf16u16n, + MVE_VCVTf32f16bh, + MVE_VCVTf32f16th, + MVE_VCVTf32s32_fix, + MVE_VCVTf32s32n, + MVE_VCVTf32u32_fix, + MVE_VCVTf32u32n, + MVE_VCVTs16f16_fix, + MVE_VCVTs16f16a, + MVE_VCVTs16f16m, + MVE_VCVTs16f16n, + MVE_VCVTs16f16p, + MVE_VCVTs16f16z, + MVE_VCVTs32f32_fix, + MVE_VCVTs32f32a, + MVE_VCVTs32f32m, + MVE_VCVTs32f32n, + MVE_VCVTs32f32p, + MVE_VCVTs32f32z, + MVE_VCVTu16f16_fix, + MVE_VCVTu16f16a, + MVE_VCVTu16f16m, + MVE_VCVTu16f16n, + MVE_VCVTu16f16p, + MVE_VCVTu16f16z, + MVE_VCVTu32f32_fix, + MVE_VCVTu32f32a, + MVE_VCVTu32f32m, + MVE_VCVTu32f32n, + MVE_VCVTu32f32p, + MVE_VCVTu32f32z, + MVE_VDDUPu16, + MVE_VDDUPu32, + MVE_VDDUPu8, + MVE_VDUP16, + MVE_VDUP32, + MVE_VDUP8, + MVE_VDWDUPu16, + MVE_VDWDUPu32, + MVE_VDWDUPu8, + MVE_VEOR, + MVE_VFMA_qr_Sf16, + MVE_VFMA_qr_Sf32, + MVE_VFMA_qr_f16, + MVE_VFMA_qr_f32, + MVE_VFMAf16, + MVE_VFMAf32, + MVE_VFMSf16, + MVE_VFMSf32, + MVE_VHADD_qr_s16, + MVE_VHADD_qr_s32, + MVE_VHADD_qr_s8, + MVE_VHADD_qr_u16, + MVE_VHADD_qr_u32, + MVE_VHADD_qr_u8, + MVE_VHADDs16, + MVE_VHADDs32, + MVE_VHADDs8, + MVE_VHADDu16, + MVE_VHADDu32, + MVE_VHADDu8, + MVE_VHCADDs16, + MVE_VHCADDs32, + MVE_VHCADDs8, + MVE_VHSUB_qr_s16, + MVE_VHSUB_qr_s32, + MVE_VHSUB_qr_s8, + MVE_VHSUB_qr_u16, + MVE_VHSUB_qr_u32, + MVE_VHSUB_qr_u8, + MVE_VHSUBs16, + MVE_VHSUBs32, + MVE_VHSUBs8, + MVE_VHSUBu16, + MVE_VHSUBu32, + MVE_VHSUBu8, + MVE_VIDUPu16, + MVE_VIDUPu32, + MVE_VIDUPu8, + MVE_VIWDUPu16, + MVE_VIWDUPu32, + MVE_VIWDUPu8, + MVE_VLD20_16, + MVE_VLD20_16_wb, + MVE_VLD20_32, + MVE_VLD20_32_wb, + MVE_VLD20_8, + MVE_VLD20_8_wb, + MVE_VLD21_16, + MVE_VLD21_16_wb, + MVE_VLD21_32, + MVE_VLD21_32_wb, + MVE_VLD21_8, + MVE_VLD21_8_wb, + MVE_VLD40_16, + MVE_VLD40_16_wb, + MVE_VLD40_32, + MVE_VLD40_32_wb, + MVE_VLD40_8, + MVE_VLD40_8_wb, + MVE_VLD41_16, + MVE_VLD41_16_wb, + MVE_VLD41_32, + MVE_VLD41_32_wb, + MVE_VLD41_8, + MVE_VLD41_8_wb, + MVE_VLD42_16, + MVE_VLD42_16_wb, + MVE_VLD42_32, + MVE_VLD42_32_wb, + MVE_VLD42_8, + MVE_VLD42_8_wb, + MVE_VLD43_16, + MVE_VLD43_16_wb, + MVE_VLD43_32, + MVE_VLD43_32_wb, + MVE_VLD43_8, + MVE_VLD43_8_wb, + MVE_VLDRBS16, + MVE_VLDRBS16_post, + MVE_VLDRBS16_pre, + MVE_VLDRBS16_rq, + MVE_VLDRBS32, + MVE_VLDRBS32_post, + MVE_VLDRBS32_pre, + MVE_VLDRBS32_rq, + MVE_VLDRBU16, + MVE_VLDRBU16_post, + MVE_VLDRBU16_pre, + MVE_VLDRBU16_rq, + MVE_VLDRBU32, + MVE_VLDRBU32_post, + MVE_VLDRBU32_pre, + MVE_VLDRBU32_rq, + MVE_VLDRBU8, + MVE_VLDRBU8_post, + MVE_VLDRBU8_pre, + MVE_VLDRBU8_rq, + MVE_VLDRDU64_qi, + MVE_VLDRDU64_qi_pre, + MVE_VLDRDU64_rq, + MVE_VLDRDU64_rq_u, + MVE_VLDRHS32, + MVE_VLDRHS32_post, + MVE_VLDRHS32_pre, + MVE_VLDRHS32_rq, + MVE_VLDRHS32_rq_u, + MVE_VLDRHU16, + MVE_VLDRHU16_post, + MVE_VLDRHU16_pre, + MVE_VLDRHU16_rq, + MVE_VLDRHU16_rq_u, + MVE_VLDRHU32, + MVE_VLDRHU32_post, + MVE_VLDRHU32_pre, + MVE_VLDRHU32_rq, + MVE_VLDRHU32_rq_u, + MVE_VLDRWU32, + MVE_VLDRWU32_post, + MVE_VLDRWU32_pre, + MVE_VLDRWU32_qi, + MVE_VLDRWU32_qi_pre, + MVE_VLDRWU32_rq, + MVE_VLDRWU32_rq_u, + MVE_VMAXAVs16, + MVE_VMAXAVs32, + MVE_VMAXAVs8, + MVE_VMAXAs16, + MVE_VMAXAs32, + MVE_VMAXAs8, + MVE_VMAXNMAVf16, + MVE_VMAXNMAVf32, + MVE_VMAXNMAf16, + MVE_VMAXNMAf32, + MVE_VMAXNMVf16, + MVE_VMAXNMVf32, + MVE_VMAXNMf16, + MVE_VMAXNMf32, + MVE_VMAXVs16, + MVE_VMAXVs32, + MVE_VMAXVs8, + MVE_VMAXVu16, + MVE_VMAXVu32, + MVE_VMAXVu8, + MVE_VMAXs16, + MVE_VMAXs32, + MVE_VMAXs8, + MVE_VMAXu16, + MVE_VMAXu32, + MVE_VMAXu8, + MVE_VMINAVs16, + MVE_VMINAVs32, + MVE_VMINAVs8, + MVE_VMINAs16, + MVE_VMINAs32, + MVE_VMINAs8, + MVE_VMINNMAVf16, + MVE_VMINNMAVf32, + MVE_VMINNMAf16, + MVE_VMINNMAf32, + MVE_VMINNMVf16, + MVE_VMINNMVf32, + MVE_VMINNMf16, + MVE_VMINNMf32, + MVE_VMINVs16, + MVE_VMINVs32, + MVE_VMINVs8, + MVE_VMINVu16, + MVE_VMINVu32, + MVE_VMINVu8, + MVE_VMINs16, + MVE_VMINs32, + MVE_VMINs8, + MVE_VMINu16, + MVE_VMINu32, + MVE_VMINu8, + MVE_VMLADAVas16, + MVE_VMLADAVas32, + MVE_VMLADAVas8, + MVE_VMLADAVau16, + MVE_VMLADAVau32, + MVE_VMLADAVau8, + MVE_VMLADAVaxs16, + MVE_VMLADAVaxs32, + MVE_VMLADAVaxs8, + MVE_VMLADAVs16, + MVE_VMLADAVs32, + MVE_VMLADAVs8, + MVE_VMLADAVu16, + MVE_VMLADAVu32, + MVE_VMLADAVu8, + MVE_VMLADAVxs16, + MVE_VMLADAVxs32, + MVE_VMLADAVxs8, + MVE_VMLALDAVas16, + MVE_VMLALDAVas32, + MVE_VMLALDAVau16, + MVE_VMLALDAVau32, + MVE_VMLALDAVaxs16, + MVE_VMLALDAVaxs32, + MVE_VMLALDAVs16, + MVE_VMLALDAVs32, + MVE_VMLALDAVu16, + MVE_VMLALDAVu32, + MVE_VMLALDAVxs16, + MVE_VMLALDAVxs32, + MVE_VMLAS_qr_i16, + MVE_VMLAS_qr_i32, + MVE_VMLAS_qr_i8, + MVE_VMLA_qr_i16, + MVE_VMLA_qr_i32, + MVE_VMLA_qr_i8, + MVE_VMLSDAVas16, + MVE_VMLSDAVas32, + MVE_VMLSDAVas8, + MVE_VMLSDAVaxs16, + MVE_VMLSDAVaxs32, + MVE_VMLSDAVaxs8, + MVE_VMLSDAVs16, + MVE_VMLSDAVs32, + MVE_VMLSDAVs8, + MVE_VMLSDAVxs16, + MVE_VMLSDAVxs32, + MVE_VMLSDAVxs8, + MVE_VMLSLDAVas16, + MVE_VMLSLDAVas32, + MVE_VMLSLDAVaxs16, + MVE_VMLSLDAVaxs32, + MVE_VMLSLDAVs16, + MVE_VMLSLDAVs32, + MVE_VMLSLDAVxs16, + MVE_VMLSLDAVxs32, + MVE_VMOVLs16bh, + MVE_VMOVLs16th, + MVE_VMOVLs8bh, + MVE_VMOVLs8th, + MVE_VMOVLu16bh, + MVE_VMOVLu16th, + MVE_VMOVLu8bh, + MVE_VMOVLu8th, + MVE_VMOVNi16bh, + MVE_VMOVNi16th, + MVE_VMOVNi32bh, + MVE_VMOVNi32th, + MVE_VMOV_from_lane_32, + MVE_VMOV_from_lane_s16, + MVE_VMOV_from_lane_s8, + MVE_VMOV_from_lane_u16, + MVE_VMOV_from_lane_u8, + MVE_VMOV_q_rr, + MVE_VMOV_rr_q, + MVE_VMOV_to_lane_16, + MVE_VMOV_to_lane_32, + MVE_VMOV_to_lane_8, + MVE_VMOVimmf32, + MVE_VMOVimmi16, + MVE_VMOVimmi32, + MVE_VMOVimmi64, + MVE_VMOVimmi8, + MVE_VMULHs16, + MVE_VMULHs32, + MVE_VMULHs8, + MVE_VMULHu16, + MVE_VMULHu32, + MVE_VMULHu8, + MVE_VMULLBp16, + MVE_VMULLBp8, + MVE_VMULLBs16, + MVE_VMULLBs32, + MVE_VMULLBs8, + MVE_VMULLBu16, + MVE_VMULLBu32, + MVE_VMULLBu8, + MVE_VMULLTp16, + MVE_VMULLTp8, + MVE_VMULLTs16, + MVE_VMULLTs32, + MVE_VMULLTs8, + MVE_VMULLTu16, + MVE_VMULLTu32, + MVE_VMULLTu8, + MVE_VMUL_qr_f16, + MVE_VMUL_qr_f32, + MVE_VMUL_qr_i16, + MVE_VMUL_qr_i32, + MVE_VMUL_qr_i8, + MVE_VMULf16, + MVE_VMULf32, + MVE_VMULi16, + MVE_VMULi32, + MVE_VMULi8, + MVE_VMVN, + MVE_VMVNimmi16, + MVE_VMVNimmi32, + MVE_VNEGf16, + MVE_VNEGf32, + MVE_VNEGs16, + MVE_VNEGs32, + MVE_VNEGs8, + MVE_VORN, + MVE_VORR, + MVE_VORRimmi16, + MVE_VORRimmi32, + MVE_VPNOT, + MVE_VPSEL, + MVE_VPST, + MVE_VPTv16i8, + MVE_VPTv16i8r, + MVE_VPTv16s8, + MVE_VPTv16s8r, + MVE_VPTv16u8, + MVE_VPTv16u8r, + MVE_VPTv4f32, + MVE_VPTv4f32r, + MVE_VPTv4i32, + MVE_VPTv4i32r, + MVE_VPTv4s32, + MVE_VPTv4s32r, + MVE_VPTv4u32, + MVE_VPTv4u32r, + MVE_VPTv8f16, + MVE_VPTv8f16r, + MVE_VPTv8i16, + MVE_VPTv8i16r, + MVE_VPTv8s16, + MVE_VPTv8s16r, + MVE_VPTv8u16, + MVE_VPTv8u16r, + MVE_VQABSs16, + MVE_VQABSs32, + MVE_VQABSs8, + MVE_VQADD_qr_s16, + MVE_VQADD_qr_s32, + MVE_VQADD_qr_s8, + MVE_VQADD_qr_u16, + MVE_VQADD_qr_u32, + MVE_VQADD_qr_u8, + MVE_VQADDs16, + MVE_VQADDs32, + MVE_VQADDs8, + MVE_VQADDu16, + MVE_VQADDu32, + MVE_VQADDu8, + MVE_VQDMLADHXs16, + MVE_VQDMLADHXs32, + MVE_VQDMLADHXs8, + MVE_VQDMLADHs16, + MVE_VQDMLADHs32, + MVE_VQDMLADHs8, + MVE_VQDMLAH_qrs16, + MVE_VQDMLAH_qrs32, + MVE_VQDMLAH_qrs8, + MVE_VQDMLASH_qrs16, + MVE_VQDMLASH_qrs32, + MVE_VQDMLASH_qrs8, + MVE_VQDMLSDHXs16, + MVE_VQDMLSDHXs32, + MVE_VQDMLSDHXs8, + MVE_VQDMLSDHs16, + MVE_VQDMLSDHs32, + MVE_VQDMLSDHs8, + MVE_VQDMULH_qr_s16, + MVE_VQDMULH_qr_s32, + MVE_VQDMULH_qr_s8, + MVE_VQDMULHi16, + MVE_VQDMULHi32, + MVE_VQDMULHi8, + MVE_VQDMULL_qr_s16bh, + MVE_VQDMULL_qr_s16th, + MVE_VQDMULL_qr_s32bh, + MVE_VQDMULL_qr_s32th, + MVE_VQDMULLs16bh, + MVE_VQDMULLs16th, + MVE_VQDMULLs32bh, + MVE_VQDMULLs32th, + MVE_VQMOVNs16bh, + MVE_VQMOVNs16th, + MVE_VQMOVNs32bh, + MVE_VQMOVNs32th, + MVE_VQMOVNu16bh, + MVE_VQMOVNu16th, + MVE_VQMOVNu32bh, + MVE_VQMOVNu32th, + MVE_VQMOVUNs16bh, + MVE_VQMOVUNs16th, + MVE_VQMOVUNs32bh, + MVE_VQMOVUNs32th, + MVE_VQNEGs16, + MVE_VQNEGs32, + MVE_VQNEGs8, + MVE_VQRDMLADHXs16, + MVE_VQRDMLADHXs32, + MVE_VQRDMLADHXs8, + MVE_VQRDMLADHs16, + MVE_VQRDMLADHs32, + MVE_VQRDMLADHs8, + MVE_VQRDMLAH_qrs16, + MVE_VQRDMLAH_qrs32, + MVE_VQRDMLAH_qrs8, + MVE_VQRDMLASH_qrs16, + MVE_VQRDMLASH_qrs32, + MVE_VQRDMLASH_qrs8, + MVE_VQRDMLSDHXs16, + MVE_VQRDMLSDHXs32, + MVE_VQRDMLSDHXs8, + MVE_VQRDMLSDHs16, + MVE_VQRDMLSDHs32, + MVE_VQRDMLSDHs8, + MVE_VQRDMULH_qr_s16, + MVE_VQRDMULH_qr_s32, + MVE_VQRDMULH_qr_s8, + MVE_VQRDMULHi16, + MVE_VQRDMULHi32, + MVE_VQRDMULHi8, + MVE_VQRSHL_by_vecs16, + MVE_VQRSHL_by_vecs32, + MVE_VQRSHL_by_vecs8, + MVE_VQRSHL_by_vecu16, + MVE_VQRSHL_by_vecu32, + MVE_VQRSHL_by_vecu8, + MVE_VQRSHL_qrs16, + MVE_VQRSHL_qrs32, + MVE_VQRSHL_qrs8, + MVE_VQRSHL_qru16, + MVE_VQRSHL_qru32, + MVE_VQRSHL_qru8, + MVE_VQRSHRNbhs16, + MVE_VQRSHRNbhs32, + MVE_VQRSHRNbhu16, + MVE_VQRSHRNbhu32, + MVE_VQRSHRNths16, + MVE_VQRSHRNths32, + MVE_VQRSHRNthu16, + MVE_VQRSHRNthu32, + MVE_VQRSHRUNs16bh, + MVE_VQRSHRUNs16th, + MVE_VQRSHRUNs32bh, + MVE_VQRSHRUNs32th, + MVE_VQSHLU_imms16, + MVE_VQSHLU_imms32, + MVE_VQSHLU_imms8, + MVE_VQSHL_by_vecs16, + MVE_VQSHL_by_vecs32, + MVE_VQSHL_by_vecs8, + MVE_VQSHL_by_vecu16, + MVE_VQSHL_by_vecu32, + MVE_VQSHL_by_vecu8, + MVE_VQSHL_qrs16, + MVE_VQSHL_qrs32, + MVE_VQSHL_qrs8, + MVE_VQSHL_qru16, + MVE_VQSHL_qru32, + MVE_VQSHL_qru8, + MVE_VQSHLimms16, + MVE_VQSHLimms32, + MVE_VQSHLimms8, + MVE_VQSHLimmu16, + MVE_VQSHLimmu32, + MVE_VQSHLimmu8, + MVE_VQSHRNbhs16, + MVE_VQSHRNbhs32, + MVE_VQSHRNbhu16, + MVE_VQSHRNbhu32, + MVE_VQSHRNths16, + MVE_VQSHRNths32, + MVE_VQSHRNthu16, + MVE_VQSHRNthu32, + MVE_VQSHRUNs16bh, + MVE_VQSHRUNs16th, + MVE_VQSHRUNs32bh, + MVE_VQSHRUNs32th, + MVE_VQSUB_qr_s16, + MVE_VQSUB_qr_s32, + MVE_VQSUB_qr_s8, + MVE_VQSUB_qr_u16, + MVE_VQSUB_qr_u32, + MVE_VQSUB_qr_u8, + MVE_VQSUBs16, + MVE_VQSUBs32, + MVE_VQSUBs8, + MVE_VQSUBu16, + MVE_VQSUBu32, + MVE_VQSUBu8, + MVE_VREV16_8, + MVE_VREV32_16, + MVE_VREV32_8, + MVE_VREV64_16, + MVE_VREV64_32, + MVE_VREV64_8, + MVE_VRHADDs16, + MVE_VRHADDs32, + MVE_VRHADDs8, + MVE_VRHADDu16, + MVE_VRHADDu32, + MVE_VRHADDu8, + MVE_VRINTf16A, + MVE_VRINTf16M, + MVE_VRINTf16N, + MVE_VRINTf16P, + MVE_VRINTf16X, + MVE_VRINTf16Z, + MVE_VRINTf32A, + MVE_VRINTf32M, + MVE_VRINTf32N, + MVE_VRINTf32P, + MVE_VRINTf32X, + MVE_VRINTf32Z, + MVE_VRMLALDAVHas32, + MVE_VRMLALDAVHau32, + MVE_VRMLALDAVHaxs32, + MVE_VRMLALDAVHs32, + MVE_VRMLALDAVHu32, + MVE_VRMLALDAVHxs32, + MVE_VRMLSLDAVHas32, + MVE_VRMLSLDAVHaxs32, + MVE_VRMLSLDAVHs32, + MVE_VRMLSLDAVHxs32, + MVE_VRMULHs16, + MVE_VRMULHs32, + MVE_VRMULHs8, + MVE_VRMULHu16, + MVE_VRMULHu32, + MVE_VRMULHu8, + MVE_VRSHL_by_vecs16, + MVE_VRSHL_by_vecs32, + MVE_VRSHL_by_vecs8, + MVE_VRSHL_by_vecu16, + MVE_VRSHL_by_vecu32, + MVE_VRSHL_by_vecu8, + MVE_VRSHL_qrs16, + MVE_VRSHL_qrs32, + MVE_VRSHL_qrs8, + MVE_VRSHL_qru16, + MVE_VRSHL_qru32, + MVE_VRSHL_qru8, + MVE_VRSHRNi16bh, + MVE_VRSHRNi16th, + MVE_VRSHRNi32bh, + MVE_VRSHRNi32th, + MVE_VRSHR_imms16, + MVE_VRSHR_imms32, + MVE_VRSHR_imms8, + MVE_VRSHR_immu16, + MVE_VRSHR_immu32, + MVE_VRSHR_immu8, + MVE_VSBC, + MVE_VSBCI, + MVE_VSHLC, + MVE_VSHLL_imms16bh, + MVE_VSHLL_imms16th, + MVE_VSHLL_imms8bh, + MVE_VSHLL_imms8th, + MVE_VSHLL_immu16bh, + MVE_VSHLL_immu16th, + MVE_VSHLL_immu8bh, + MVE_VSHLL_immu8th, + MVE_VSHLL_lws16bh, + MVE_VSHLL_lws16th, + MVE_VSHLL_lws8bh, + MVE_VSHLL_lws8th, + MVE_VSHLL_lwu16bh, + MVE_VSHLL_lwu16th, + MVE_VSHLL_lwu8bh, + MVE_VSHLL_lwu8th, + MVE_VSHL_by_vecs16, + MVE_VSHL_by_vecs32, + MVE_VSHL_by_vecs8, + MVE_VSHL_by_vecu16, + MVE_VSHL_by_vecu32, + MVE_VSHL_by_vecu8, + MVE_VSHL_immi16, + MVE_VSHL_immi32, + MVE_VSHL_immi8, + MVE_VSHL_qrs16, + MVE_VSHL_qrs32, + MVE_VSHL_qrs8, + MVE_VSHL_qru16, + MVE_VSHL_qru32, + MVE_VSHL_qru8, + MVE_VSHRNi16bh, + MVE_VSHRNi16th, + MVE_VSHRNi32bh, + MVE_VSHRNi32th, + MVE_VSHR_imms16, + MVE_VSHR_imms32, + MVE_VSHR_imms8, + MVE_VSHR_immu16, + MVE_VSHR_immu32, + MVE_VSHR_immu8, + MVE_VSLIimm16, + MVE_VSLIimm32, + MVE_VSLIimm8, + MVE_VSRIimm16, + MVE_VSRIimm32, + MVE_VSRIimm8, + MVE_VST20_16, + MVE_VST20_16_wb, + MVE_VST20_32, + MVE_VST20_32_wb, + MVE_VST20_8, + MVE_VST20_8_wb, + MVE_VST21_16, + MVE_VST21_16_wb, + MVE_VST21_32, + MVE_VST21_32_wb, + MVE_VST21_8, + MVE_VST21_8_wb, + MVE_VST40_16, + MVE_VST40_16_wb, + MVE_VST40_32, + MVE_VST40_32_wb, + MVE_VST40_8, + MVE_VST40_8_wb, + MVE_VST41_16, + MVE_VST41_16_wb, + MVE_VST41_32, + MVE_VST41_32_wb, + MVE_VST41_8, + MVE_VST41_8_wb, + MVE_VST42_16, + MVE_VST42_16_wb, + MVE_VST42_32, + MVE_VST42_32_wb, + MVE_VST42_8, + MVE_VST42_8_wb, + MVE_VST43_16, + MVE_VST43_16_wb, + MVE_VST43_32, + MVE_VST43_32_wb, + MVE_VST43_8, + MVE_VST43_8_wb, + MVE_VSTRB16, + MVE_VSTRB16_post, + MVE_VSTRB16_pre, + MVE_VSTRB16_rq, + MVE_VSTRB32, + MVE_VSTRB32_post, + MVE_VSTRB32_pre, + MVE_VSTRB32_rq, + MVE_VSTRB8_rq, + MVE_VSTRBU8, + MVE_VSTRBU8_post, + MVE_VSTRBU8_pre, + MVE_VSTRD64_qi, + MVE_VSTRD64_qi_pre, + MVE_VSTRD64_rq, + MVE_VSTRD64_rq_u, + MVE_VSTRH16_rq, + MVE_VSTRH16_rq_u, + MVE_VSTRH32, + MVE_VSTRH32_post, + MVE_VSTRH32_pre, + MVE_VSTRH32_rq, + MVE_VSTRH32_rq_u, + MVE_VSTRHU16, + MVE_VSTRHU16_post, + MVE_VSTRHU16_pre, + MVE_VSTRW32_qi, + MVE_VSTRW32_qi_pre, + MVE_VSTRW32_rq, + MVE_VSTRW32_rq_u, + MVE_VSTRWU32, + MVE_VSTRWU32_post, + MVE_VSTRWU32_pre, + MVE_VSUB_qr_f16, + MVE_VSUB_qr_f32, + MVE_VSUB_qr_i16, + MVE_VSUB_qr_i32, + MVE_VSUB_qr_i8, + MVE_VSUBf16, + MVE_VSUBf32, + MVE_VSUBi16, + MVE_VSUBi32, + MVE_VSUBi8, + MVE_WLSTP_16, + MVE_WLSTP_32, + MVE_WLSTP_64, + MVE_WLSTP_8, + MVNi, + MVNr, + MVNsi, + MVNsr, + NEON_VMAXNMNDf, + NEON_VMAXNMNDh, + NEON_VMAXNMNQf, + NEON_VMAXNMNQh, + NEON_VMINNMNDf, + NEON_VMINNMNDh, + NEON_VMINNMNQf, + NEON_VMINNMNQh, + ORRri, + ORRrr, + ORRrsi, + ORRrsr, + PKHBT, + PKHTB, + PLDWi12, + PLDWrs, + PLDi12, + PLDrs, + PLIi12, + PLIrs, + QADD, + QADD16, + QADD8, + QASX, + QDADD, + QDSUB, + QSAX, + QSUB, + QSUB16, + QSUB8, + RBIT, + REV, + REV16, + REVSH, + RFEDA, + RFEDA_UPD, + RFEDB, + RFEDB_UPD, + RFEIA, + RFEIA_UPD, + RFEIB, + RFEIB_UPD, + RSBri, + RSBrr, + RSBrsi, + RSBrsr, + RSCri, + RSCrr, + RSCrsi, + RSCrsr, + SADD16, + SADD8, + SASX, + SB, + SBCri, + SBCrr, + SBCrsi, + SBCrsr, + SBFX, + SDIV, + SEL, + SETEND, + SETPAN, + SHA1C, + SHA1H, + SHA1M, + SHA1P, + SHA1SU0, + SHA1SU1, + SHA256H, + SHA256H2, + SHA256SU0, + SHA256SU1, + SHADD16, + SHADD8, + SHASX, + SHSAX, + SHSUB16, + SHSUB8, + SMC, + SMLABB, + SMLABT, + SMLAD, + SMLADX, + SMLAL, + SMLALBB, + SMLALBT, + SMLALD, + SMLALDX, + SMLALTB, + SMLALTT, + SMLATB, + SMLATT, + SMLAWB, + SMLAWT, + SMLSD, + SMLSDX, + SMLSLD, + SMLSLDX, + SMMLA, + SMMLAR, + SMMLS, + SMMLSR, + SMMUL, + SMMULR, + SMUAD, + SMUADX, + SMULBB, + SMULBT, + SMULL, + SMULTB, + SMULTT, + SMULWB, + SMULWT, + SMUSD, + SMUSDX, + SRSDA, + SRSDA_UPD, + SRSDB, + SRSDB_UPD, + SRSIA, + SRSIA_UPD, + SRSIB, + SRSIB_UPD, + SSAT, + SSAT16, + SSAX, + SSUB16, + SSUB8, + STC2L_OFFSET, + STC2L_OPTION, + STC2L_POST, + STC2L_PRE, + STC2_OFFSET, + STC2_OPTION, + STC2_POST, + STC2_PRE, + STCL_OFFSET, + STCL_OPTION, + STCL_POST, + STCL_PRE, + STC_OFFSET, + STC_OPTION, + STC_POST, + STC_PRE, + STL, + STLB, + STLEX, + STLEXB, + STLEXD, + STLEXH, + STLH, + STMDA, + STMDA_UPD, + STMDB, + STMDB_UPD, + STMIA, + STMIA_UPD, + STMIB, + STMIB_UPD, + STRBT_POST_IMM, + STRBT_POST_REG, + STRB_POST_IMM, + STRB_POST_REG, + STRB_PRE_IMM, + STRB_PRE_REG, + STRBi12, + STRBrs, + STRD, + STRD_POST, + STRD_PRE, + STREX, + STREXB, + STREXD, + STREXH, + STRH, + STRHTi, + STRHTr, + STRH_POST, + STRH_PRE, + STRT_POST_IMM, + STRT_POST_REG, + STR_POST_IMM, + STR_POST_REG, + STR_PRE_IMM, + STR_PRE_REG, + STRi12, + STRrs, + SUBri, + SUBrr, + SUBrsi, + SUBrsr, + SVC, + SWP, + SWPB, + SXTAB, + SXTAB16, + SXTAH, + SXTB, + SXTB16, + SXTH, + TEQri, + TEQrr, + TEQrsi, + TEQrsr, + TRAP, + TSB, + TSTri, + TSTrr, + TSTrsi, + TSTrsr, + UADD16, + UADD8, + UASX, + UBFX, + UDF, + UDIV, + UHADD16, + UHADD8, + UHASX, + UHSAX, + UHSUB16, + UHSUB8, + UMAAL, + UMLAL, + UMULL, + UQADD16, + UQADD8, + UQASX, + UQSAX, + UQSUB16, + UQSUB8, + USAD8, + USADA8, + USAT, + USAT16, + USAX, + USUB16, + USUB8, + UXTAB, + UXTAB16, + UXTAH, + UXTB, + UXTB16, + UXTH, + VABALsv2i64, + VABALsv4i32, + VABALsv8i16, + VABALuv2i64, + VABALuv4i32, + VABALuv8i16, + VABAsv16i8, + VABAsv2i32, + VABAsv4i16, + VABAsv4i32, + VABAsv8i16, + VABAsv8i8, + VABAuv16i8, + VABAuv2i32, + VABAuv4i16, + VABAuv4i32, + VABAuv8i16, + VABAuv8i8, + VABDLsv2i64, + VABDLsv4i32, + VABDLsv8i16, + VABDLuv2i64, + VABDLuv4i32, + VABDLuv8i16, + VABDfd, + VABDfq, + VABDhd, + VABDhq, + VABDsv16i8, + VABDsv2i32, + VABDsv4i16, + VABDsv4i32, + VABDsv8i16, + VABDsv8i8, + VABDuv16i8, + VABDuv2i32, + VABDuv4i16, + VABDuv4i32, + VABDuv8i16, + VABDuv8i8, + VABSD, + VABSH, + VABSS, + VABSfd, + VABSfq, + VABShd, + VABShq, + VABSv16i8, + VABSv2i32, + VABSv4i16, + VABSv4i32, + VABSv8i16, + VABSv8i8, + VACGEfd, + VACGEfq, + VACGEhd, + VACGEhq, + VACGTfd, + VACGTfq, + VACGThd, + VACGThq, + VADDD, + VADDH, + VADDHNv2i32, + VADDHNv4i16, + VADDHNv8i8, + VADDLsv2i64, + VADDLsv4i32, + VADDLsv8i16, + VADDLuv2i64, + VADDLuv4i32, + VADDLuv8i16, + VADDS, + VADDWsv2i64, + VADDWsv4i32, + VADDWsv8i16, + VADDWuv2i64, + VADDWuv4i32, + VADDWuv8i16, + VADDfd, + VADDfq, + VADDhd, + VADDhq, + VADDv16i8, + VADDv1i64, + VADDv2i32, + VADDv2i64, + VADDv4i16, + VADDv4i32, + VADDv8i16, + VADDv8i8, + VANDd, + VANDq, + VBF16MALBQ, + VBF16MALBQI, + VBF16MALTQ, + VBF16MALTQI, + VBICd, + VBICiv2i32, + VBICiv4i16, + VBICiv4i32, + VBICiv8i16, + VBICq, + VBIFd, + VBIFq, + VBITd, + VBITq, + VBSLd, + VBSLq, + VBSPd, + VBSPq, + VCADDv2f32, + VCADDv4f16, + VCADDv4f32, + VCADDv8f16, + VCEQfd, + VCEQfq, + VCEQhd, + VCEQhq, + VCEQv16i8, + VCEQv2i32, + VCEQv4i16, + VCEQv4i32, + VCEQv8i16, + VCEQv8i8, + VCEQzv16i8, + VCEQzv2f32, + VCEQzv2i32, + VCEQzv4f16, + VCEQzv4f32, + VCEQzv4i16, + VCEQzv4i32, + VCEQzv8f16, + VCEQzv8i16, + VCEQzv8i8, + VCGEfd, + VCGEfq, + VCGEhd, + VCGEhq, + VCGEsv16i8, + VCGEsv2i32, + VCGEsv4i16, + VCGEsv4i32, + VCGEsv8i16, + VCGEsv8i8, + VCGEuv16i8, + VCGEuv2i32, + VCGEuv4i16, + VCGEuv4i32, + VCGEuv8i16, + VCGEuv8i8, + VCGEzv16i8, + VCGEzv2f32, + VCGEzv2i32, + VCGEzv4f16, + VCGEzv4f32, + VCGEzv4i16, + VCGEzv4i32, + VCGEzv8f16, + VCGEzv8i16, + VCGEzv8i8, + VCGTfd, + VCGTfq, + VCGThd, + VCGThq, + VCGTsv16i8, + VCGTsv2i32, + VCGTsv4i16, + VCGTsv4i32, + VCGTsv8i16, + VCGTsv8i8, + VCGTuv16i8, + VCGTuv2i32, + VCGTuv4i16, + VCGTuv4i32, + VCGTuv8i16, + VCGTuv8i8, + VCGTzv16i8, + VCGTzv2f32, + VCGTzv2i32, + VCGTzv4f16, + VCGTzv4f32, + VCGTzv4i16, + VCGTzv4i32, + VCGTzv8f16, + VCGTzv8i16, + VCGTzv8i8, + VCLEzv16i8, + VCLEzv2f32, + VCLEzv2i32, + VCLEzv4f16, + VCLEzv4f32, + VCLEzv4i16, + VCLEzv4i32, + VCLEzv8f16, + VCLEzv8i16, + VCLEzv8i8, + VCLSv16i8, + VCLSv2i32, + VCLSv4i16, + VCLSv4i32, + VCLSv8i16, + VCLSv8i8, + VCLTzv16i8, + VCLTzv2f32, + VCLTzv2i32, + VCLTzv4f16, + VCLTzv4f32, + VCLTzv4i16, + VCLTzv4i32, + VCLTzv8f16, + VCLTzv8i16, + VCLTzv8i8, + VCLZv16i8, + VCLZv2i32, + VCLZv4i16, + VCLZv4i32, + VCLZv8i16, + VCLZv8i8, + VCMLAv2f32, + VCMLAv2f32_indexed, + VCMLAv4f16, + VCMLAv4f16_indexed, + VCMLAv4f32, + VCMLAv4f32_indexed, + VCMLAv8f16, + VCMLAv8f16_indexed, + VCMPD, + VCMPED, + VCMPEH, + VCMPES, + VCMPEZD, + VCMPEZH, + VCMPEZS, + VCMPH, + VCMPS, + VCMPZD, + VCMPZH, + VCMPZS, + VCNTd, + VCNTq, + VCVTANSDf, + VCVTANSDh, + VCVTANSQf, + VCVTANSQh, + VCVTANUDf, + VCVTANUDh, + VCVTANUQf, + VCVTANUQh, + VCVTASD, + VCVTASH, + VCVTASS, + VCVTAUD, + VCVTAUH, + VCVTAUS, + VCVTBDH, + VCVTBHD, + VCVTBHS, + VCVTBSH, + VCVTDS, + VCVTMNSDf, + VCVTMNSDh, + VCVTMNSQf, + VCVTMNSQh, + VCVTMNUDf, + VCVTMNUDh, + VCVTMNUQf, + VCVTMNUQh, + VCVTMSD, + VCVTMSH, + VCVTMSS, + VCVTMUD, + VCVTMUH, + VCVTMUS, + VCVTNNSDf, + VCVTNNSDh, + VCVTNNSQf, + VCVTNNSQh, + VCVTNNUDf, + VCVTNNUDh, + VCVTNNUQf, + VCVTNNUQh, + VCVTNSD, + VCVTNSH, + VCVTNSS, + VCVTNUD, + VCVTNUH, + VCVTNUS, + VCVTPNSDf, + VCVTPNSDh, + VCVTPNSQf, + VCVTPNSQh, + VCVTPNUDf, + VCVTPNUDh, + VCVTPNUQf, + VCVTPNUQh, + VCVTPSD, + VCVTPSH, + VCVTPSS, + VCVTPUD, + VCVTPUH, + VCVTPUS, + VCVTSD, + VCVTTDH, + VCVTTHD, + VCVTTHS, + VCVTTSH, + VCVTf2h, + VCVTf2sd, + VCVTf2sq, + VCVTf2ud, + VCVTf2uq, + VCVTf2xsd, + VCVTf2xsq, + VCVTf2xud, + VCVTf2xuq, + VCVTh2f, + VCVTh2sd, + VCVTh2sq, + VCVTh2ud, + VCVTh2uq, + VCVTh2xsd, + VCVTh2xsq, + VCVTh2xud, + VCVTh2xuq, + VCVTs2fd, + VCVTs2fq, + VCVTs2hd, + VCVTs2hq, + VCVTu2fd, + VCVTu2fq, + VCVTu2hd, + VCVTu2hq, + VCVTxs2fd, + VCVTxs2fq, + VCVTxs2hd, + VCVTxs2hq, + VCVTxu2fd, + VCVTxu2fq, + VCVTxu2hd, + VCVTxu2hq, + VDIVD, + VDIVH, + VDIVS, + VDUP16d, + VDUP16q, + VDUP32d, + VDUP32q, + VDUP8d, + VDUP8q, + VDUPLN16d, + VDUPLN16q, + VDUPLN32d, + VDUPLN32q, + VDUPLN8d, + VDUPLN8q, + VEORd, + VEORq, + VEXTd16, + VEXTd32, + VEXTd8, + VEXTq16, + VEXTq32, + VEXTq64, + VEXTq8, + VFMAD, + VFMAH, + VFMALD, + VFMALDI, + VFMALQ, + VFMALQI, + VFMAS, + VFMAfd, + VFMAfq, + VFMAhd, + VFMAhq, + VFMSD, + VFMSH, + VFMSLD, + VFMSLDI, + VFMSLQ, + VFMSLQI, + VFMSS, + VFMSfd, + VFMSfq, + VFMShd, + VFMShq, + VFNMAD, + VFNMAH, + VFNMAS, + VFNMSD, + VFNMSH, + VFNMSS, + VFP_VMAXNMD, + VFP_VMAXNMH, + VFP_VMAXNMS, + VFP_VMINNMD, + VFP_VMINNMH, + VFP_VMINNMS, + VGETLNi32, + VGETLNs16, + VGETLNs8, + VGETLNu16, + VGETLNu8, + VHADDsv16i8, + VHADDsv2i32, + VHADDsv4i16, + VHADDsv4i32, + VHADDsv8i16, + VHADDsv8i8, + VHADDuv16i8, + VHADDuv2i32, + VHADDuv4i16, + VHADDuv4i32, + VHADDuv8i16, + VHADDuv8i8, + VHSUBsv16i8, + VHSUBsv2i32, + VHSUBsv4i16, + VHSUBsv4i32, + VHSUBsv8i16, + VHSUBsv8i8, + VHSUBuv16i8, + VHSUBuv2i32, + VHSUBuv4i16, + VHSUBuv4i32, + VHSUBuv8i16, + VHSUBuv8i8, + VINSH, + VJCVT, + VLD1DUPd16, + VLD1DUPd16wb_fixed, + VLD1DUPd16wb_register, + VLD1DUPd32, + VLD1DUPd32wb_fixed, + VLD1DUPd32wb_register, + VLD1DUPd8, + VLD1DUPd8wb_fixed, + VLD1DUPd8wb_register, + VLD1DUPq16, + VLD1DUPq16wb_fixed, + VLD1DUPq16wb_register, + VLD1DUPq32, + VLD1DUPq32wb_fixed, + VLD1DUPq32wb_register, + VLD1DUPq8, + VLD1DUPq8wb_fixed, + VLD1DUPq8wb_register, + VLD1LNd16, + VLD1LNd16_UPD, + VLD1LNd32, + VLD1LNd32_UPD, + VLD1LNd8, + VLD1LNd8_UPD, + VLD1LNq16Pseudo, + VLD1LNq16Pseudo_UPD, + VLD1LNq32Pseudo, + VLD1LNq32Pseudo_UPD, + VLD1LNq8Pseudo, + VLD1LNq8Pseudo_UPD, + VLD1d16, + VLD1d16Q, + VLD1d16QPseudo, + VLD1d16QPseudoWB_fixed, + VLD1d16QPseudoWB_register, + VLD1d16Qwb_fixed, + VLD1d16Qwb_register, + VLD1d16T, + VLD1d16TPseudo, + VLD1d16TPseudoWB_fixed, + VLD1d16TPseudoWB_register, + VLD1d16Twb_fixed, + VLD1d16Twb_register, + VLD1d16wb_fixed, + VLD1d16wb_register, + VLD1d32, + VLD1d32Q, + VLD1d32QPseudo, + VLD1d32QPseudoWB_fixed, + VLD1d32QPseudoWB_register, + VLD1d32Qwb_fixed, + VLD1d32Qwb_register, + VLD1d32T, + VLD1d32TPseudo, + VLD1d32TPseudoWB_fixed, + VLD1d32TPseudoWB_register, + VLD1d32Twb_fixed, + VLD1d32Twb_register, + VLD1d32wb_fixed, + VLD1d32wb_register, + VLD1d64, + VLD1d64Q, + VLD1d64QPseudo, + VLD1d64QPseudoWB_fixed, + VLD1d64QPseudoWB_register, + VLD1d64Qwb_fixed, + VLD1d64Qwb_register, + VLD1d64T, + VLD1d64TPseudo, + VLD1d64TPseudoWB_fixed, + VLD1d64TPseudoWB_register, + VLD1d64Twb_fixed, + VLD1d64Twb_register, + VLD1d64wb_fixed, + VLD1d64wb_register, + VLD1d8, + VLD1d8Q, + VLD1d8QPseudo, + VLD1d8QPseudoWB_fixed, + VLD1d8QPseudoWB_register, + VLD1d8Qwb_fixed, + VLD1d8Qwb_register, + VLD1d8T, + VLD1d8TPseudo, + VLD1d8TPseudoWB_fixed, + VLD1d8TPseudoWB_register, + VLD1d8Twb_fixed, + VLD1d8Twb_register, + VLD1d8wb_fixed, + VLD1d8wb_register, + VLD1q16, + VLD1q16HighQPseudo, + VLD1q16HighQPseudo_UPD, + VLD1q16HighTPseudo, + VLD1q16HighTPseudo_UPD, + VLD1q16LowQPseudo_UPD, + VLD1q16LowTPseudo_UPD, + VLD1q16wb_fixed, + VLD1q16wb_register, + VLD1q32, + VLD1q32HighQPseudo, + VLD1q32HighQPseudo_UPD, + VLD1q32HighTPseudo, + VLD1q32HighTPseudo_UPD, + VLD1q32LowQPseudo_UPD, + VLD1q32LowTPseudo_UPD, + VLD1q32wb_fixed, + VLD1q32wb_register, + VLD1q64, + VLD1q64HighQPseudo, + VLD1q64HighQPseudo_UPD, + VLD1q64HighTPseudo, + VLD1q64HighTPseudo_UPD, + VLD1q64LowQPseudo_UPD, + VLD1q64LowTPseudo_UPD, + VLD1q64wb_fixed, + VLD1q64wb_register, + VLD1q8, + VLD1q8HighQPseudo, + VLD1q8HighQPseudo_UPD, + VLD1q8HighTPseudo, + VLD1q8HighTPseudo_UPD, + VLD1q8LowQPseudo_UPD, + VLD1q8LowTPseudo_UPD, + VLD1q8wb_fixed, + VLD1q8wb_register, + VLD2DUPd16, + VLD2DUPd16wb_fixed, + VLD2DUPd16wb_register, + VLD2DUPd16x2, + VLD2DUPd16x2wb_fixed, + VLD2DUPd16x2wb_register, + VLD2DUPd32, + VLD2DUPd32wb_fixed, + VLD2DUPd32wb_register, + VLD2DUPd32x2, + VLD2DUPd32x2wb_fixed, + VLD2DUPd32x2wb_register, + VLD2DUPd8, + VLD2DUPd8wb_fixed, + VLD2DUPd8wb_register, + VLD2DUPd8x2, + VLD2DUPd8x2wb_fixed, + VLD2DUPd8x2wb_register, + VLD2DUPq16EvenPseudo, + VLD2DUPq16OddPseudo, + VLD2DUPq16OddPseudoWB_fixed, + VLD2DUPq16OddPseudoWB_register, + VLD2DUPq32EvenPseudo, + VLD2DUPq32OddPseudo, + VLD2DUPq32OddPseudoWB_fixed, + VLD2DUPq32OddPseudoWB_register, + VLD2DUPq8EvenPseudo, + VLD2DUPq8OddPseudo, + VLD2DUPq8OddPseudoWB_fixed, + VLD2DUPq8OddPseudoWB_register, + VLD2LNd16, + VLD2LNd16Pseudo, + VLD2LNd16Pseudo_UPD, + VLD2LNd16_UPD, + VLD2LNd32, + VLD2LNd32Pseudo, + VLD2LNd32Pseudo_UPD, + VLD2LNd32_UPD, + VLD2LNd8, + VLD2LNd8Pseudo, + VLD2LNd8Pseudo_UPD, + VLD2LNd8_UPD, + VLD2LNq16, + VLD2LNq16Pseudo, + VLD2LNq16Pseudo_UPD, + VLD2LNq16_UPD, + VLD2LNq32, + VLD2LNq32Pseudo, + VLD2LNq32Pseudo_UPD, + VLD2LNq32_UPD, + VLD2b16, + VLD2b16wb_fixed, + VLD2b16wb_register, + VLD2b32, + VLD2b32wb_fixed, + VLD2b32wb_register, + VLD2b8, + VLD2b8wb_fixed, + VLD2b8wb_register, + VLD2d16, + VLD2d16wb_fixed, + VLD2d16wb_register, + VLD2d32, + VLD2d32wb_fixed, + VLD2d32wb_register, + VLD2d8, + VLD2d8wb_fixed, + VLD2d8wb_register, + VLD2q16, + VLD2q16Pseudo, + VLD2q16PseudoWB_fixed, + VLD2q16PseudoWB_register, + VLD2q16wb_fixed, + VLD2q16wb_register, + VLD2q32, + VLD2q32Pseudo, + VLD2q32PseudoWB_fixed, + VLD2q32PseudoWB_register, + VLD2q32wb_fixed, + VLD2q32wb_register, + VLD2q8, + VLD2q8Pseudo, + VLD2q8PseudoWB_fixed, + VLD2q8PseudoWB_register, + VLD2q8wb_fixed, + VLD2q8wb_register, + VLD3DUPd16, + VLD3DUPd16Pseudo, + VLD3DUPd16Pseudo_UPD, + VLD3DUPd16_UPD, + VLD3DUPd32, + VLD3DUPd32Pseudo, + VLD3DUPd32Pseudo_UPD, + VLD3DUPd32_UPD, + VLD3DUPd8, + VLD3DUPd8Pseudo, + VLD3DUPd8Pseudo_UPD, + VLD3DUPd8_UPD, + VLD3DUPq16, + VLD3DUPq16EvenPseudo, + VLD3DUPq16OddPseudo, + VLD3DUPq16OddPseudo_UPD, + VLD3DUPq16_UPD, + VLD3DUPq32, + VLD3DUPq32EvenPseudo, + VLD3DUPq32OddPseudo, + VLD3DUPq32OddPseudo_UPD, + VLD3DUPq32_UPD, + VLD3DUPq8, + VLD3DUPq8EvenPseudo, + VLD3DUPq8OddPseudo, + VLD3DUPq8OddPseudo_UPD, + VLD3DUPq8_UPD, + VLD3LNd16, + VLD3LNd16Pseudo, + VLD3LNd16Pseudo_UPD, + VLD3LNd16_UPD, + VLD3LNd32, + VLD3LNd32Pseudo, + VLD3LNd32Pseudo_UPD, + VLD3LNd32_UPD, + VLD3LNd8, + VLD3LNd8Pseudo, + VLD3LNd8Pseudo_UPD, + VLD3LNd8_UPD, + VLD3LNq16, + VLD3LNq16Pseudo, + VLD3LNq16Pseudo_UPD, + VLD3LNq16_UPD, + VLD3LNq32, + VLD3LNq32Pseudo, + VLD3LNq32Pseudo_UPD, + VLD3LNq32_UPD, + VLD3d16, + VLD3d16Pseudo, + VLD3d16Pseudo_UPD, + VLD3d16_UPD, + VLD3d32, + VLD3d32Pseudo, + VLD3d32Pseudo_UPD, + VLD3d32_UPD, + VLD3d8, + VLD3d8Pseudo, + VLD3d8Pseudo_UPD, + VLD3d8_UPD, + VLD3q16, + VLD3q16Pseudo_UPD, + VLD3q16_UPD, + VLD3q16oddPseudo, + VLD3q16oddPseudo_UPD, + VLD3q32, + VLD3q32Pseudo_UPD, + VLD3q32_UPD, + VLD3q32oddPseudo, + VLD3q32oddPseudo_UPD, + VLD3q8, + VLD3q8Pseudo_UPD, + VLD3q8_UPD, + VLD3q8oddPseudo, + VLD3q8oddPseudo_UPD, + VLD4DUPd16, + VLD4DUPd16Pseudo, + VLD4DUPd16Pseudo_UPD, + VLD4DUPd16_UPD, + VLD4DUPd32, + VLD4DUPd32Pseudo, + VLD4DUPd32Pseudo_UPD, + VLD4DUPd32_UPD, + VLD4DUPd8, + VLD4DUPd8Pseudo, + VLD4DUPd8Pseudo_UPD, + VLD4DUPd8_UPD, + VLD4DUPq16, + VLD4DUPq16EvenPseudo, + VLD4DUPq16OddPseudo, + VLD4DUPq16OddPseudo_UPD, + VLD4DUPq16_UPD, + VLD4DUPq32, + VLD4DUPq32EvenPseudo, + VLD4DUPq32OddPseudo, + VLD4DUPq32OddPseudo_UPD, + VLD4DUPq32_UPD, + VLD4DUPq8, + VLD4DUPq8EvenPseudo, + VLD4DUPq8OddPseudo, + VLD4DUPq8OddPseudo_UPD, + VLD4DUPq8_UPD, + VLD4LNd16, + VLD4LNd16Pseudo, + VLD4LNd16Pseudo_UPD, + VLD4LNd16_UPD, + VLD4LNd32, + VLD4LNd32Pseudo, + VLD4LNd32Pseudo_UPD, + VLD4LNd32_UPD, + VLD4LNd8, + VLD4LNd8Pseudo, + VLD4LNd8Pseudo_UPD, + VLD4LNd8_UPD, + VLD4LNq16, + VLD4LNq16Pseudo, + VLD4LNq16Pseudo_UPD, + VLD4LNq16_UPD, + VLD4LNq32, + VLD4LNq32Pseudo, + VLD4LNq32Pseudo_UPD, + VLD4LNq32_UPD, + VLD4d16, + VLD4d16Pseudo, + VLD4d16Pseudo_UPD, + VLD4d16_UPD, + VLD4d32, + VLD4d32Pseudo, + VLD4d32Pseudo_UPD, + VLD4d32_UPD, + VLD4d8, + VLD4d8Pseudo, + VLD4d8Pseudo_UPD, + VLD4d8_UPD, + VLD4q16, + VLD4q16Pseudo_UPD, + VLD4q16_UPD, + VLD4q16oddPseudo, + VLD4q16oddPseudo_UPD, + VLD4q32, + VLD4q32Pseudo_UPD, + VLD4q32_UPD, + VLD4q32oddPseudo, + VLD4q32oddPseudo_UPD, + VLD4q8, + VLD4q8Pseudo_UPD, + VLD4q8_UPD, + VLD4q8oddPseudo, + VLD4q8oddPseudo_UPD, + VLDMDDB_UPD, + VLDMDIA, + VLDMDIA_UPD, + VLDMQIA, + VLDMSDB_UPD, + VLDMSIA, + VLDMSIA_UPD, + VLDRD, + VLDRH, + VLDRS, + VLDR_FPCXTNS_off, + VLDR_FPCXTNS_post, + VLDR_FPCXTNS_pre, + VLDR_FPCXTS_off, + VLDR_FPCXTS_post, + VLDR_FPCXTS_pre, + VLDR_FPSCR_NZCVQC_off, + VLDR_FPSCR_NZCVQC_post, + VLDR_FPSCR_NZCVQC_pre, + VLDR_FPSCR_off, + VLDR_FPSCR_post, + VLDR_FPSCR_pre, + VLDR_P0_off, + VLDR_P0_post, + VLDR_P0_pre, + VLDR_VPR_off, + VLDR_VPR_post, + VLDR_VPR_pre, + VLLDM, + VLLDM_T2, + VLSTM, + VLSTM_T2, + VMAXfd, + VMAXfq, + VMAXhd, + VMAXhq, + VMAXsv16i8, + VMAXsv2i32, + VMAXsv4i16, + VMAXsv4i32, + VMAXsv8i16, + VMAXsv8i8, + VMAXuv16i8, + VMAXuv2i32, + VMAXuv4i16, + VMAXuv4i32, + VMAXuv8i16, + VMAXuv8i8, + VMINfd, + VMINfq, + VMINhd, + VMINhq, + VMINsv16i8, + VMINsv2i32, + VMINsv4i16, + VMINsv4i32, + VMINsv8i16, + VMINsv8i8, + VMINuv16i8, + VMINuv2i32, + VMINuv4i16, + VMINuv4i32, + VMINuv8i16, + VMINuv8i8, + VMLAD, + VMLAH, + VMLALslsv2i32, + VMLALslsv4i16, + VMLALsluv2i32, + VMLALsluv4i16, + VMLALsv2i64, + VMLALsv4i32, + VMLALsv8i16, + VMLALuv2i64, + VMLALuv4i32, + VMLALuv8i16, + VMLAS, + VMLAfd, + VMLAfq, + VMLAhd, + VMLAhq, + VMLAslfd, + VMLAslfq, + VMLAslhd, + VMLAslhq, + VMLAslv2i32, + VMLAslv4i16, + VMLAslv4i32, + VMLAslv8i16, + VMLAv16i8, + VMLAv2i32, + VMLAv4i16, + VMLAv4i32, + VMLAv8i16, + VMLAv8i8, + VMLSD, + VMLSH, + VMLSLslsv2i32, + VMLSLslsv4i16, + VMLSLsluv2i32, + VMLSLsluv4i16, + VMLSLsv2i64, + VMLSLsv4i32, + VMLSLsv8i16, + VMLSLuv2i64, + VMLSLuv4i32, + VMLSLuv8i16, + VMLSS, + VMLSfd, + VMLSfq, + VMLShd, + VMLShq, + VMLSslfd, + VMLSslfq, + VMLSslhd, + VMLSslhq, + VMLSslv2i32, + VMLSslv4i16, + VMLSslv4i32, + VMLSslv8i16, + VMLSv16i8, + VMLSv2i32, + VMLSv4i16, + VMLSv4i32, + VMLSv8i16, + VMLSv8i8, + VMMLA, + VMOVD, + VMOVDRR, + VMOVH, + VMOVHR, + VMOVLsv2i64, + VMOVLsv4i32, + VMOVLsv8i16, + VMOVLuv2i64, + VMOVLuv4i32, + VMOVLuv8i16, + VMOVNv2i32, + VMOVNv4i16, + VMOVNv8i8, + VMOVRH, + VMOVRRD, + VMOVRRS, + VMOVRS, + VMOVS, + VMOVSR, + VMOVSRR, + VMOVv16i8, + VMOVv1i64, + VMOVv2f32, + VMOVv2i32, + VMOVv2i64, + VMOVv4f32, + VMOVv4i16, + VMOVv4i32, + VMOVv8i16, + VMOVv8i8, + VMRS, + VMRS_FPCXTNS, + VMRS_FPCXTS, + VMRS_FPEXC, + VMRS_FPINST, + VMRS_FPINST2, + VMRS_FPSCR_NZCVQC, + VMRS_FPSID, + VMRS_MVFR0, + VMRS_MVFR1, + VMRS_MVFR2, + VMRS_P0, + VMRS_VPR, + VMSR, + VMSR_FPCXTNS, + VMSR_FPCXTS, + VMSR_FPEXC, + VMSR_FPINST, + VMSR_FPINST2, + VMSR_FPSCR_NZCVQC, + VMSR_FPSID, + VMSR_P0, + VMSR_VPR, + VMULD, + VMULH, + VMULLp64, + VMULLp8, + VMULLslsv2i32, + VMULLslsv4i16, + VMULLsluv2i32, + VMULLsluv4i16, + VMULLsv2i64, + VMULLsv4i32, + VMULLsv8i16, + VMULLuv2i64, + VMULLuv4i32, + VMULLuv8i16, + VMULS, + VMULfd, + VMULfq, + VMULhd, + VMULhq, + VMULpd, + VMULpq, + VMULslfd, + VMULslfq, + VMULslhd, + VMULslhq, + VMULslv2i32, + VMULslv4i16, + VMULslv4i32, + VMULslv8i16, + VMULv16i8, + VMULv2i32, + VMULv4i16, + VMULv4i32, + VMULv8i16, + VMULv8i8, + VMVNd, + VMVNq, + VMVNv2i32, + VMVNv4i16, + VMVNv4i32, + VMVNv8i16, + VNEGD, + VNEGH, + VNEGS, + VNEGf32q, + VNEGfd, + VNEGhd, + VNEGhq, + VNEGs16d, + VNEGs16q, + VNEGs32d, + VNEGs32q, + VNEGs8d, + VNEGs8q, + VNMLAD, + VNMLAH, + VNMLAS, + VNMLSD, + VNMLSH, + VNMLSS, + VNMULD, + VNMULH, + VNMULS, + VORNd, + VORNq, + VORRd, + VORRiv2i32, + VORRiv4i16, + VORRiv4i32, + VORRiv8i16, + VORRq, + VPADALsv16i8, + VPADALsv2i32, + VPADALsv4i16, + VPADALsv4i32, + VPADALsv8i16, + VPADALsv8i8, + VPADALuv16i8, + VPADALuv2i32, + VPADALuv4i16, + VPADALuv4i32, + VPADALuv8i16, + VPADALuv8i8, + VPADDLsv16i8, + VPADDLsv2i32, + VPADDLsv4i16, + VPADDLsv4i32, + VPADDLsv8i16, + VPADDLsv8i8, + VPADDLuv16i8, + VPADDLuv2i32, + VPADDLuv4i16, + VPADDLuv4i32, + VPADDLuv8i16, + VPADDLuv8i8, + VPADDf, + VPADDh, + VPADDi16, + VPADDi32, + VPADDi8, + VPMAXf, + VPMAXh, + VPMAXs16, + VPMAXs32, + VPMAXs8, + VPMAXu16, + VPMAXu32, + VPMAXu8, + VPMINf, + VPMINh, + VPMINs16, + VPMINs32, + VPMINs8, + VPMINu16, + VPMINu32, + VPMINu8, + VQABSv16i8, + VQABSv2i32, + VQABSv4i16, + VQABSv4i32, + VQABSv8i16, + VQABSv8i8, + VQADDsv16i8, + VQADDsv1i64, + VQADDsv2i32, + VQADDsv2i64, + VQADDsv4i16, + VQADDsv4i32, + VQADDsv8i16, + VQADDsv8i8, + VQADDuv16i8, + VQADDuv1i64, + VQADDuv2i32, + VQADDuv2i64, + VQADDuv4i16, + VQADDuv4i32, + VQADDuv8i16, + VQADDuv8i8, + VQDMLALslv2i32, + VQDMLALslv4i16, + VQDMLALv2i64, + VQDMLALv4i32, + VQDMLSLslv2i32, + VQDMLSLslv4i16, + VQDMLSLv2i64, + VQDMLSLv4i32, + VQDMULHslv2i32, + VQDMULHslv4i16, + VQDMULHslv4i32, + VQDMULHslv8i16, + VQDMULHv2i32, + VQDMULHv4i16, + VQDMULHv4i32, + VQDMULHv8i16, + VQDMULLslv2i32, + VQDMULLslv4i16, + VQDMULLv2i64, + VQDMULLv4i32, + VQMOVNsuv2i32, + VQMOVNsuv4i16, + VQMOVNsuv8i8, + VQMOVNsv2i32, + VQMOVNsv4i16, + VQMOVNsv8i8, + VQMOVNuv2i32, + VQMOVNuv4i16, + VQMOVNuv8i8, + VQNEGv16i8, + VQNEGv2i32, + VQNEGv4i16, + VQNEGv4i32, + VQNEGv8i16, + VQNEGv8i8, + VQRDMLAHslv2i32, + VQRDMLAHslv4i16, + VQRDMLAHslv4i32, + VQRDMLAHslv8i16, + VQRDMLAHv2i32, + VQRDMLAHv4i16, + VQRDMLAHv4i32, + VQRDMLAHv8i16, + VQRDMLSHslv2i32, + VQRDMLSHslv4i16, + VQRDMLSHslv4i32, + VQRDMLSHslv8i16, + VQRDMLSHv2i32, + VQRDMLSHv4i16, + VQRDMLSHv4i32, + VQRDMLSHv8i16, + VQRDMULHslv2i32, + VQRDMULHslv4i16, + VQRDMULHslv4i32, + VQRDMULHslv8i16, + VQRDMULHv2i32, + VQRDMULHv4i16, + VQRDMULHv4i32, + VQRDMULHv8i16, + VQRSHLsv16i8, + VQRSHLsv1i64, + VQRSHLsv2i32, + VQRSHLsv2i64, + VQRSHLsv4i16, + VQRSHLsv4i32, + VQRSHLsv8i16, + VQRSHLsv8i8, + VQRSHLuv16i8, + VQRSHLuv1i64, + VQRSHLuv2i32, + VQRSHLuv2i64, + VQRSHLuv4i16, + VQRSHLuv4i32, + VQRSHLuv8i16, + VQRSHLuv8i8, + VQRSHRNsv2i32, + VQRSHRNsv4i16, + VQRSHRNsv8i8, + VQRSHRNuv2i32, + VQRSHRNuv4i16, + VQRSHRNuv8i8, + VQRSHRUNv2i32, + VQRSHRUNv4i16, + VQRSHRUNv8i8, + VQSHLsiv16i8, + VQSHLsiv1i64, + VQSHLsiv2i32, + VQSHLsiv2i64, + VQSHLsiv4i16, + VQSHLsiv4i32, + VQSHLsiv8i16, + VQSHLsiv8i8, + VQSHLsuv16i8, + VQSHLsuv1i64, + VQSHLsuv2i32, + VQSHLsuv2i64, + VQSHLsuv4i16, + VQSHLsuv4i32, + VQSHLsuv8i16, + VQSHLsuv8i8, + VQSHLsv16i8, + VQSHLsv1i64, + VQSHLsv2i32, + VQSHLsv2i64, + VQSHLsv4i16, + VQSHLsv4i32, + VQSHLsv8i16, + VQSHLsv8i8, + VQSHLuiv16i8, + VQSHLuiv1i64, + VQSHLuiv2i32, + VQSHLuiv2i64, + VQSHLuiv4i16, + VQSHLuiv4i32, + VQSHLuiv8i16, + VQSHLuiv8i8, + VQSHLuv16i8, + VQSHLuv1i64, + VQSHLuv2i32, + VQSHLuv2i64, + VQSHLuv4i16, + VQSHLuv4i32, + VQSHLuv8i16, + VQSHLuv8i8, + VQSHRNsv2i32, + VQSHRNsv4i16, + VQSHRNsv8i8, + VQSHRNuv2i32, + VQSHRNuv4i16, + VQSHRNuv8i8, + VQSHRUNv2i32, + VQSHRUNv4i16, + VQSHRUNv8i8, + VQSUBsv16i8, + VQSUBsv1i64, + VQSUBsv2i32, + VQSUBsv2i64, + VQSUBsv4i16, + VQSUBsv4i32, + VQSUBsv8i16, + VQSUBsv8i8, + VQSUBuv16i8, + VQSUBuv1i64, + VQSUBuv2i32, + VQSUBuv2i64, + VQSUBuv4i16, + VQSUBuv4i32, + VQSUBuv8i16, + VQSUBuv8i8, + VRADDHNv2i32, + VRADDHNv4i16, + VRADDHNv8i8, + VRECPEd, + VRECPEfd, + VRECPEfq, + VRECPEhd, + VRECPEhq, + VRECPEq, + VRECPSfd, + VRECPSfq, + VRECPShd, + VRECPShq, + VREV16d8, + VREV16q8, + VREV32d16, + VREV32d8, + VREV32q16, + VREV32q8, + VREV64d16, + VREV64d32, + VREV64d8, + VREV64q16, + VREV64q32, + VREV64q8, + VRHADDsv16i8, + VRHADDsv2i32, + VRHADDsv4i16, + VRHADDsv4i32, + VRHADDsv8i16, + VRHADDsv8i8, + VRHADDuv16i8, + VRHADDuv2i32, + VRHADDuv4i16, + VRHADDuv4i32, + VRHADDuv8i16, + VRHADDuv8i8, + VRINTAD, + VRINTAH, + VRINTANDf, + VRINTANDh, + VRINTANQf, + VRINTANQh, + VRINTAS, + VRINTMD, + VRINTMH, + VRINTMNDf, + VRINTMNDh, + VRINTMNQf, + VRINTMNQh, + VRINTMS, + VRINTND, + VRINTNH, + VRINTNNDf, + VRINTNNDh, + VRINTNNQf, + VRINTNNQh, + VRINTNS, + VRINTPD, + VRINTPH, + VRINTPNDf, + VRINTPNDh, + VRINTPNQf, + VRINTPNQh, + VRINTPS, + VRINTRD, + VRINTRH, + VRINTRS, + VRINTXD, + VRINTXH, + VRINTXNDf, + VRINTXNDh, + VRINTXNQf, + VRINTXNQh, + VRINTXS, + VRINTZD, + VRINTZH, + VRINTZNDf, + VRINTZNDh, + VRINTZNQf, + VRINTZNQh, + VRINTZS, + VRSHLsv16i8, + VRSHLsv1i64, + VRSHLsv2i32, + VRSHLsv2i64, + VRSHLsv4i16, + VRSHLsv4i32, + VRSHLsv8i16, + VRSHLsv8i8, + VRSHLuv16i8, + VRSHLuv1i64, + VRSHLuv2i32, + VRSHLuv2i64, + VRSHLuv4i16, + VRSHLuv4i32, + VRSHLuv8i16, + VRSHLuv8i8, + VRSHRNv2i32, + VRSHRNv4i16, + VRSHRNv8i8, + VRSHRsv16i8, + VRSHRsv1i64, + VRSHRsv2i32, + VRSHRsv2i64, + VRSHRsv4i16, + VRSHRsv4i32, + VRSHRsv8i16, + VRSHRsv8i8, + VRSHRuv16i8, + VRSHRuv1i64, + VRSHRuv2i32, + VRSHRuv2i64, + VRSHRuv4i16, + VRSHRuv4i32, + VRSHRuv8i16, + VRSHRuv8i8, + VRSQRTEd, + VRSQRTEfd, + VRSQRTEfq, + VRSQRTEhd, + VRSQRTEhq, + VRSQRTEq, + VRSQRTSfd, + VRSQRTSfq, + VRSQRTShd, + VRSQRTShq, + VRSRAsv16i8, + VRSRAsv1i64, + VRSRAsv2i32, + VRSRAsv2i64, + VRSRAsv4i16, + VRSRAsv4i32, + VRSRAsv8i16, + VRSRAsv8i8, + VRSRAuv16i8, + VRSRAuv1i64, + VRSRAuv2i32, + VRSRAuv2i64, + VRSRAuv4i16, + VRSRAuv4i32, + VRSRAuv8i16, + VRSRAuv8i8, + VRSUBHNv2i32, + VRSUBHNv4i16, + VRSUBHNv8i8, + VSCCLRMD, + VSCCLRMS, + VSDOTD, + VSDOTDI, + VSDOTQ, + VSDOTQI, + VSELEQD, + VSELEQH, + VSELEQS, + VSELGED, + VSELGEH, + VSELGES, + VSELGTD, + VSELGTH, + VSELGTS, + VSELVSD, + VSELVSH, + VSELVSS, + VSETLNi16, + VSETLNi32, + VSETLNi8, + VSHLLi16, + VSHLLi32, + VSHLLi8, + VSHLLsv2i64, + VSHLLsv4i32, + VSHLLsv8i16, + VSHLLuv2i64, + VSHLLuv4i32, + VSHLLuv8i16, + VSHLiv16i8, + VSHLiv1i64, + VSHLiv2i32, + VSHLiv2i64, + VSHLiv4i16, + VSHLiv4i32, + VSHLiv8i16, + VSHLiv8i8, + VSHLsv16i8, + VSHLsv1i64, + VSHLsv2i32, + VSHLsv2i64, + VSHLsv4i16, + VSHLsv4i32, + VSHLsv8i16, + VSHLsv8i8, + VSHLuv16i8, + VSHLuv1i64, + VSHLuv2i32, + VSHLuv2i64, + VSHLuv4i16, + VSHLuv4i32, + VSHLuv8i16, + VSHLuv8i8, + VSHRNv2i32, + VSHRNv4i16, + VSHRNv8i8, + VSHRsv16i8, + VSHRsv1i64, + VSHRsv2i32, + VSHRsv2i64, + VSHRsv4i16, + VSHRsv4i32, + VSHRsv8i16, + VSHRsv8i8, + VSHRuv16i8, + VSHRuv1i64, + VSHRuv2i32, + VSHRuv2i64, + VSHRuv4i16, + VSHRuv4i32, + VSHRuv8i16, + VSHRuv8i8, + VSHTOD, + VSHTOH, + VSHTOS, + VSITOD, + VSITOH, + VSITOS, + VSLIv16i8, + VSLIv1i64, + VSLIv2i32, + VSLIv2i64, + VSLIv4i16, + VSLIv4i32, + VSLIv8i16, + VSLIv8i8, + VSLTOD, + VSLTOH, + VSLTOS, + VSMMLA, + VSQRTD, + VSQRTH, + VSQRTS, + VSRAsv16i8, + VSRAsv1i64, + VSRAsv2i32, + VSRAsv2i64, + VSRAsv4i16, + VSRAsv4i32, + VSRAsv8i16, + VSRAsv8i8, + VSRAuv16i8, + VSRAuv1i64, + VSRAuv2i32, + VSRAuv2i64, + VSRAuv4i16, + VSRAuv4i32, + VSRAuv8i16, + VSRAuv8i8, + VSRIv16i8, + VSRIv1i64, + VSRIv2i32, + VSRIv2i64, + VSRIv4i16, + VSRIv4i32, + VSRIv8i16, + VSRIv8i8, + VST1LNd16, + VST1LNd16_UPD, + VST1LNd32, + VST1LNd32_UPD, + VST1LNd8, + VST1LNd8_UPD, + VST1LNq16Pseudo, + VST1LNq16Pseudo_UPD, + VST1LNq32Pseudo, + VST1LNq32Pseudo_UPD, + VST1LNq8Pseudo, + VST1LNq8Pseudo_UPD, + VST1d16, + VST1d16Q, + VST1d16QPseudo, + VST1d16QPseudoWB_fixed, + VST1d16QPseudoWB_register, + VST1d16Qwb_fixed, + VST1d16Qwb_register, + VST1d16T, + VST1d16TPseudo, + VST1d16TPseudoWB_fixed, + VST1d16TPseudoWB_register, + VST1d16Twb_fixed, + VST1d16Twb_register, + VST1d16wb_fixed, + VST1d16wb_register, + VST1d32, + VST1d32Q, + VST1d32QPseudo, + VST1d32QPseudoWB_fixed, + VST1d32QPseudoWB_register, + VST1d32Qwb_fixed, + VST1d32Qwb_register, + VST1d32T, + VST1d32TPseudo, + VST1d32TPseudoWB_fixed, + VST1d32TPseudoWB_register, + VST1d32Twb_fixed, + VST1d32Twb_register, + VST1d32wb_fixed, + VST1d32wb_register, + VST1d64, + VST1d64Q, + VST1d64QPseudo, + VST1d64QPseudoWB_fixed, + VST1d64QPseudoWB_register, + VST1d64Qwb_fixed, + VST1d64Qwb_register, + VST1d64T, + VST1d64TPseudo, + VST1d64TPseudoWB_fixed, + VST1d64TPseudoWB_register, + VST1d64Twb_fixed, + VST1d64Twb_register, + VST1d64wb_fixed, + VST1d64wb_register, + VST1d8, + VST1d8Q, + VST1d8QPseudo, + VST1d8QPseudoWB_fixed, + VST1d8QPseudoWB_register, + VST1d8Qwb_fixed, + VST1d8Qwb_register, + VST1d8T, + VST1d8TPseudo, + VST1d8TPseudoWB_fixed, + VST1d8TPseudoWB_register, + VST1d8Twb_fixed, + VST1d8Twb_register, + VST1d8wb_fixed, + VST1d8wb_register, + VST1q16, + VST1q16HighQPseudo, + VST1q16HighQPseudo_UPD, + VST1q16HighTPseudo, + VST1q16HighTPseudo_UPD, + VST1q16LowQPseudo_UPD, + VST1q16LowTPseudo_UPD, + VST1q16wb_fixed, + VST1q16wb_register, + VST1q32, + VST1q32HighQPseudo, + VST1q32HighQPseudo_UPD, + VST1q32HighTPseudo, + VST1q32HighTPseudo_UPD, + VST1q32LowQPseudo_UPD, + VST1q32LowTPseudo_UPD, + VST1q32wb_fixed, + VST1q32wb_register, + VST1q64, + VST1q64HighQPseudo, + VST1q64HighQPseudo_UPD, + VST1q64HighTPseudo, + VST1q64HighTPseudo_UPD, + VST1q64LowQPseudo_UPD, + VST1q64LowTPseudo_UPD, + VST1q64wb_fixed, + VST1q64wb_register, + VST1q8, + VST1q8HighQPseudo, + VST1q8HighQPseudo_UPD, + VST1q8HighTPseudo, + VST1q8HighTPseudo_UPD, + VST1q8LowQPseudo_UPD, + VST1q8LowTPseudo_UPD, + VST1q8wb_fixed, + VST1q8wb_register, + VST2LNd16, + VST2LNd16Pseudo, + VST2LNd16Pseudo_UPD, + VST2LNd16_UPD, + VST2LNd32, + VST2LNd32Pseudo, + VST2LNd32Pseudo_UPD, + VST2LNd32_UPD, + VST2LNd8, + VST2LNd8Pseudo, + VST2LNd8Pseudo_UPD, + VST2LNd8_UPD, + VST2LNq16, + VST2LNq16Pseudo, + VST2LNq16Pseudo_UPD, + VST2LNq16_UPD, + VST2LNq32, + VST2LNq32Pseudo, + VST2LNq32Pseudo_UPD, + VST2LNq32_UPD, + VST2b16, + VST2b16wb_fixed, + VST2b16wb_register, + VST2b32, + VST2b32wb_fixed, + VST2b32wb_register, + VST2b8, + VST2b8wb_fixed, + VST2b8wb_register, + VST2d16, + VST2d16wb_fixed, + VST2d16wb_register, + VST2d32, + VST2d32wb_fixed, + VST2d32wb_register, + VST2d8, + VST2d8wb_fixed, + VST2d8wb_register, + VST2q16, + VST2q16Pseudo, + VST2q16PseudoWB_fixed, + VST2q16PseudoWB_register, + VST2q16wb_fixed, + VST2q16wb_register, + VST2q32, + VST2q32Pseudo, + VST2q32PseudoWB_fixed, + VST2q32PseudoWB_register, + VST2q32wb_fixed, + VST2q32wb_register, + VST2q8, + VST2q8Pseudo, + VST2q8PseudoWB_fixed, + VST2q8PseudoWB_register, + VST2q8wb_fixed, + VST2q8wb_register, + VST3LNd16, + VST3LNd16Pseudo, + VST3LNd16Pseudo_UPD, + VST3LNd16_UPD, + VST3LNd32, + VST3LNd32Pseudo, + VST3LNd32Pseudo_UPD, + VST3LNd32_UPD, + VST3LNd8, + VST3LNd8Pseudo, + VST3LNd8Pseudo_UPD, + VST3LNd8_UPD, + VST3LNq16, + VST3LNq16Pseudo, + VST3LNq16Pseudo_UPD, + VST3LNq16_UPD, + VST3LNq32, + VST3LNq32Pseudo, + VST3LNq32Pseudo_UPD, + VST3LNq32_UPD, + VST3d16, + VST3d16Pseudo, + VST3d16Pseudo_UPD, + VST3d16_UPD, + VST3d32, + VST3d32Pseudo, + VST3d32Pseudo_UPD, + VST3d32_UPD, + VST3d8, + VST3d8Pseudo, + VST3d8Pseudo_UPD, + VST3d8_UPD, + VST3q16, + VST3q16Pseudo_UPD, + VST3q16_UPD, + VST3q16oddPseudo, + VST3q16oddPseudo_UPD, + VST3q32, + VST3q32Pseudo_UPD, + VST3q32_UPD, + VST3q32oddPseudo, + VST3q32oddPseudo_UPD, + VST3q8, + VST3q8Pseudo_UPD, + VST3q8_UPD, + VST3q8oddPseudo, + VST3q8oddPseudo_UPD, + VST4LNd16, + VST4LNd16Pseudo, + VST4LNd16Pseudo_UPD, + VST4LNd16_UPD, + VST4LNd32, + VST4LNd32Pseudo, + VST4LNd32Pseudo_UPD, + VST4LNd32_UPD, + VST4LNd8, + VST4LNd8Pseudo, + VST4LNd8Pseudo_UPD, + VST4LNd8_UPD, + VST4LNq16, + VST4LNq16Pseudo, + VST4LNq16Pseudo_UPD, + VST4LNq16_UPD, + VST4LNq32, + VST4LNq32Pseudo, + VST4LNq32Pseudo_UPD, + VST4LNq32_UPD, + VST4d16, + VST4d16Pseudo, + VST4d16Pseudo_UPD, + VST4d16_UPD, + VST4d32, + VST4d32Pseudo, + VST4d32Pseudo_UPD, + VST4d32_UPD, + VST4d8, + VST4d8Pseudo, + VST4d8Pseudo_UPD, + VST4d8_UPD, + VST4q16, + VST4q16Pseudo_UPD, + VST4q16_UPD, + VST4q16oddPseudo, + VST4q16oddPseudo_UPD, + VST4q32, + VST4q32Pseudo_UPD, + VST4q32_UPD, + VST4q32oddPseudo, + VST4q32oddPseudo_UPD, + VST4q8, + VST4q8Pseudo_UPD, + VST4q8_UPD, + VST4q8oddPseudo, + VST4q8oddPseudo_UPD, + VSTMDDB_UPD, + VSTMDIA, + VSTMDIA_UPD, + VSTMQIA, + VSTMSDB_UPD, + VSTMSIA, + VSTMSIA_UPD, + VSTRD, + VSTRH, + VSTRS, + VSTR_FPCXTNS_off, + VSTR_FPCXTNS_post, + VSTR_FPCXTNS_pre, + VSTR_FPCXTS_off, + VSTR_FPCXTS_post, + VSTR_FPCXTS_pre, + VSTR_FPSCR_NZCVQC_off, + VSTR_FPSCR_NZCVQC_post, + VSTR_FPSCR_NZCVQC_pre, + VSTR_FPSCR_off, + VSTR_FPSCR_post, + VSTR_FPSCR_pre, + VSTR_P0_off, + VSTR_P0_post, + VSTR_P0_pre, + VSTR_VPR_off, + VSTR_VPR_post, + VSTR_VPR_pre, + VSUBD, + VSUBH, + VSUBHNv2i32, + VSUBHNv4i16, + VSUBHNv8i8, + VSUBLsv2i64, + VSUBLsv4i32, + VSUBLsv8i16, + VSUBLuv2i64, + VSUBLuv4i32, + VSUBLuv8i16, + VSUBS, + VSUBWsv2i64, + VSUBWsv4i32, + VSUBWsv8i16, + VSUBWuv2i64, + VSUBWuv4i32, + VSUBWuv8i16, + VSUBfd, + VSUBfq, + VSUBhd, + VSUBhq, + VSUBv16i8, + VSUBv1i64, + VSUBv2i32, + VSUBv2i64, + VSUBv4i16, + VSUBv4i32, + VSUBv8i16, + VSUBv8i8, + VSUDOTDI, + VSUDOTQI, + VSWPd, + VSWPq, + VTBL1, + VTBL2, + VTBL3, + VTBL3Pseudo, + VTBL4, + VTBL4Pseudo, + VTBX1, + VTBX2, + VTBX3, + VTBX3Pseudo, + VTBX4, + VTBX4Pseudo, + VTOSHD, + VTOSHH, + VTOSHS, + VTOSIRD, + VTOSIRH, + VTOSIRS, + VTOSIZD, + VTOSIZH, + VTOSIZS, + VTOSLD, + VTOSLH, + VTOSLS, + VTOUHD, + VTOUHH, + VTOUHS, + VTOUIRD, + VTOUIRH, + VTOUIRS, + VTOUIZD, + VTOUIZH, + VTOUIZS, + VTOULD, + VTOULH, + VTOULS, + VTRNd16, + VTRNd32, + VTRNd8, + VTRNq16, + VTRNq32, + VTRNq8, + VTSTv16i8, + VTSTv2i32, + VTSTv4i16, + VTSTv4i32, + VTSTv8i16, + VTSTv8i8, + VUDOTD, + VUDOTDI, + VUDOTQ, + VUDOTQI, + VUHTOD, + VUHTOH, + VUHTOS, + VUITOD, + VUITOH, + VUITOS, + VULTOD, + VULTOH, + VULTOS, + VUMMLA, + VUSDOTD, + VUSDOTDI, + VUSDOTQ, + VUSDOTQI, + VUSMMLA, + VUZPd16, + VUZPd8, + VUZPq16, + VUZPq32, + VUZPq8, + VZIPd16, + VZIPd8, + VZIPq16, + VZIPq32, + VZIPq8, + sysLDMDA, + sysLDMDA_UPD, + sysLDMDB, + sysLDMDB_UPD, + sysLDMIA, + sysLDMIA_UPD, + sysLDMIB, + sysLDMIB_UPD, + sysSTMDA, + sysSTMDA_UPD, + sysSTMDB, + sysSTMDB_UPD, + sysSTMIA, + sysSTMIA_UPD, + sysSTMIB, + sysSTMIB_UPD, + t2ADCri, + t2ADCrr, + t2ADCrs, + t2ADDri, + t2ADDri12, + t2ADDrr, + t2ADDrs, + t2ADDspImm, + t2ADDspImm12, + t2ADR, + t2ANDri, + t2ANDrr, + t2ANDrs, + t2ASRri, + t2ASRrr, + t2ASRs1, + t2AUT, + t2AUTG, + t2B, + t2BFC, + t2BFI, + t2BFLi, + t2BFLr, + t2BFi, + t2BFic, + t2BFr, + t2BICri, + t2BICrr, + t2BICrs, + t2BTI, + t2BXAUT, + t2BXJ, + t2Bcc, + t2CDP, + t2CDP2, + t2CLREX, + t2CLRM, + t2CLZ, + t2CMNri, + t2CMNzrr, + t2CMNzrs, + t2CMPri, + t2CMPrr, + t2CMPrs, + t2CPS1p, + t2CPS2p, + t2CPS3p, + t2CRC32B, + t2CRC32CB, + t2CRC32CH, + t2CRC32CW, + t2CRC32H, + t2CRC32W, + t2CSEL, + t2CSINC, + t2CSINV, + t2CSNEG, + t2DBG, + t2DCPS1, + t2DCPS2, + t2DCPS3, + t2DLS, + t2DMB, + t2DSB, + t2EORri, + t2EORrr, + t2EORrs, + t2HINT, + t2HVC, + t2ISB, + t2IT, + t2Int_eh_sjlj_setjmp, + t2Int_eh_sjlj_setjmp_nofp, + t2LDA, + t2LDAB, + t2LDAEX, + t2LDAEXB, + t2LDAEXD, + t2LDAEXH, + t2LDAH, + t2LDC2L_OFFSET, + t2LDC2L_OPTION, + t2LDC2L_POST, + t2LDC2L_PRE, + t2LDC2_OFFSET, + t2LDC2_OPTION, + t2LDC2_POST, + t2LDC2_PRE, + t2LDCL_OFFSET, + t2LDCL_OPTION, + t2LDCL_POST, + t2LDCL_PRE, + t2LDC_OFFSET, + t2LDC_OPTION, + t2LDC_POST, + t2LDC_PRE, + t2LDMDB, + t2LDMDB_UPD, + t2LDMIA, + t2LDMIA_UPD, + t2LDRBT, + t2LDRB_POST, + t2LDRB_PRE, + t2LDRBi12, + t2LDRBi8, + t2LDRBpci, + t2LDRBs, + t2LDRD_POST, + t2LDRD_PRE, + t2LDRDi8, + t2LDREX, + t2LDREXB, + t2LDREXD, + t2LDREXH, + t2LDRHT, + t2LDRH_POST, + t2LDRH_PRE, + t2LDRHi12, + t2LDRHi8, + t2LDRHpci, + t2LDRHs, + t2LDRSBT, + t2LDRSB_POST, + t2LDRSB_PRE, + t2LDRSBi12, + t2LDRSBi8, + t2LDRSBpci, + t2LDRSBs, + t2LDRSHT, + t2LDRSH_POST, + t2LDRSH_PRE, + t2LDRSHi12, + t2LDRSHi8, + t2LDRSHpci, + t2LDRSHs, + t2LDRT, + t2LDR_POST, + t2LDR_PRE, + t2LDRi12, + t2LDRi8, + t2LDRpci, + t2LDRs, + t2LE, + t2LEUpdate, + t2LSLri, + t2LSLrr, + t2LSRri, + t2LSRrr, + t2LSRs1, + t2MCR, + t2MCR2, + t2MCRR, + t2MCRR2, + t2MLA, + t2MLS, + t2MOVTi16, + t2MOVi, + t2MOVi16, + t2MOVr, + t2MRC, + t2MRC2, + t2MRRC, + t2MRRC2, + t2MRS_AR, + t2MRS_M, + t2MRSbanked, + t2MRSsys_AR, + t2MSR_AR, + t2MSR_M, + t2MSRbanked, + t2MUL, + t2MVNi, + t2MVNr, + t2MVNs, + t2ORNri, + t2ORNrr, + t2ORNrs, + t2ORRri, + t2ORRrr, + t2ORRrs, + t2PAC, + t2PACBTI, + t2PACG, + t2PKHBT, + t2PKHTB, + t2PLDWi12, + t2PLDWi8, + t2PLDWs, + t2PLDi12, + t2PLDi8, + t2PLDpci, + t2PLDs, + t2PLIi12, + t2PLIi8, + t2PLIpci, + t2PLIs, + t2QADD, + t2QADD16, + t2QADD8, + t2QASX, + t2QDADD, + t2QDSUB, + t2QSAX, + t2QSUB, + t2QSUB16, + t2QSUB8, + t2RBIT, + t2REV, + t2REV16, + t2REVSH, + t2RFEDB, + t2RFEDBW, + t2RFEIA, + t2RFEIAW, + t2RORri, + t2RORrr, + t2RRX, + t2RSBri, + t2RSBrr, + t2RSBrs, + t2SADD16, + t2SADD8, + t2SASX, + t2SB, + t2SBCri, + t2SBCrr, + t2SBCrs, + t2SBFX, + t2SDIV, + t2SEL, + t2SETPAN, + t2SG, + t2SHADD16, + t2SHADD8, + t2SHASX, + t2SHSAX, + t2SHSUB16, + t2SHSUB8, + t2SMC, + t2SMLABB, + t2SMLABT, + t2SMLAD, + t2SMLADX, + t2SMLAL, + t2SMLALBB, + t2SMLALBT, + t2SMLALD, + t2SMLALDX, + t2SMLALTB, + t2SMLALTT, + t2SMLATB, + t2SMLATT, + t2SMLAWB, + t2SMLAWT, + t2SMLSD, + t2SMLSDX, + t2SMLSLD, + t2SMLSLDX, + t2SMMLA, + t2SMMLAR, + t2SMMLS, + t2SMMLSR, + t2SMMUL, + t2SMMULR, + t2SMUAD, + t2SMUADX, + t2SMULBB, + t2SMULBT, + t2SMULL, + t2SMULTB, + t2SMULTT, + t2SMULWB, + t2SMULWT, + t2SMUSD, + t2SMUSDX, + t2SRSDB, + t2SRSDB_UPD, + t2SRSIA, + t2SRSIA_UPD, + t2SSAT, + t2SSAT16, + t2SSAX, + t2SSUB16, + t2SSUB8, + t2STC2L_OFFSET, + t2STC2L_OPTION, + t2STC2L_POST, + t2STC2L_PRE, + t2STC2_OFFSET, + t2STC2_OPTION, + t2STC2_POST, + t2STC2_PRE, + t2STCL_OFFSET, + t2STCL_OPTION, + t2STCL_POST, + t2STCL_PRE, + t2STC_OFFSET, + t2STC_OPTION, + t2STC_POST, + t2STC_PRE, + t2STL, + t2STLB, + t2STLEX, + t2STLEXB, + t2STLEXD, + t2STLEXH, + t2STLH, + t2STMDB, + t2STMDB_UPD, + t2STMIA, + t2STMIA_UPD, + t2STRBT, + t2STRB_POST, + t2STRB_PRE, + t2STRBi12, + t2STRBi8, + t2STRBs, + t2STRD_POST, + t2STRD_PRE, + t2STRDi8, + t2STREX, + t2STREXB, + t2STREXD, + t2STREXH, + t2STRHT, + t2STRH_POST, + t2STRH_PRE, + t2STRHi12, + t2STRHi8, + t2STRHs, + t2STRT, + t2STR_POST, + t2STR_PRE, + t2STRi12, + t2STRi8, + t2STRs, + t2SUBS_PC_LR, + t2SUBri, + t2SUBri12, + t2SUBrr, + t2SUBrs, + t2SUBspImm, + t2SUBspImm12, + t2SXTAB, + t2SXTAB16, + t2SXTAH, + t2SXTB, + t2SXTB16, + t2SXTH, + t2TBB, + t2TBH, + t2TEQri, + t2TEQrr, + t2TEQrs, + t2TSB, + t2TSTri, + t2TSTrr, + t2TSTrs, + t2TT, + t2TTA, + t2TTAT, + t2TTT, + t2UADD16, + t2UADD8, + t2UASX, + t2UBFX, + t2UDF, + t2UDIV, + t2UHADD16, + t2UHADD8, + t2UHASX, + t2UHSAX, + t2UHSUB16, + t2UHSUB8, + t2UMAAL, + t2UMLAL, + t2UMULL, + t2UQADD16, + t2UQADD8, + t2UQASX, + t2UQSAX, + t2UQSUB16, + t2UQSUB8, + t2USAD8, + t2USADA8, + t2USAT, + t2USAT16, + t2USAX, + t2USUB16, + t2USUB8, + t2UXTAB, + t2UXTAB16, + t2UXTAH, + t2UXTB, + t2UXTB16, + t2UXTH, + t2WLS, + tADC, + tADDhirr, + tADDi3, + tADDi8, + tADDrSP, + tADDrSPi, + tADDrr, + tADDspi, + tADDspr, + tADR, + tAND, + tASRri, + tASRrr, + tB, + tBIC, + tBKPT, + tBL, + tBLXNSr, + tBLXi, + tBLXr, + tBX, + tBXNS, + tBcc, + tCBNZ, + tCBZ, + tCMNz, + tCMPhir, + tCMPi8, + tCMPr, + tCPS, + tEOR, + tHINT, + tHLT, + tInt_WIN_eh_sjlj_longjmp, + tInt_eh_sjlj_longjmp, + tInt_eh_sjlj_setjmp, + tLDMIA, + tLDRBi, + tLDRBr, + tLDRHi, + tLDRHr, + tLDRSB, + tLDRSH, + tLDRi, + tLDRpci, + tLDRr, + tLDRspi, + tLSLri, + tLSLrr, + tLSRri, + tLSRrr, + tMOVSr, + tMOVi8, + tMOVr, + tMUL, + tMVN, + tORR, + tPICADD, + tPOP, + tPUSH, + tREV, + tREV16, + tREVSH, + tROR, + tRSB, + tSBC, + tSETEND, + tSTMIA_UPD, + tSTRBi, + tSTRBr, + tSTRHi, + tSTRHr, + tSTRi, + tSTRr, + tSTRspi, + tSUBi3, + tSUBi8, + tSUBrr, + tSUBspi, + tSVC, + tSXTB, + tSXTH, + tTRAP, + tTST, + tUDF, + tUXTB, + tUXTH, + t__brkdiv0, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ADDSri, + 323 => Opcode::ADDSrr, + 324 => Opcode::ADDSrsi, + 325 => Opcode::ADDSrsr, + 326 => Opcode::ADJCALLSTACKDOWN, + 327 => Opcode::ADJCALLSTACKUP, + 328 => Opcode::ASRi, + 329 => Opcode::ASRr, + 330 => Opcode::ASRs1, + 331 => Opcode::B, + 332 => Opcode::BCCZi64, + 333 => Opcode::BCCi64, + 334 => Opcode::BLX_noip, + 335 => Opcode::BLX_pred_noip, + 336 => Opcode::BL_PUSHLR, + 337 => Opcode::BMOVPCB_CALL, + 338 => Opcode::BMOVPCRX_CALL, + 339 => Opcode::BR_JTadd, + 340 => Opcode::BR_JTm_i12, + 341 => Opcode::BR_JTm_rs, + 342 => Opcode::BR_JTr, + 343 => Opcode::BX_CALL, + 344 => Opcode::CMP_SWAP_16, + 345 => Opcode::CMP_SWAP_32, + 346 => Opcode::CMP_SWAP_64, + 347 => Opcode::CMP_SWAP_8, + 348 => Opcode::CONSTPOOL_ENTRY, + 349 => Opcode::COPY_STRUCT_BYVAL_I32, + 350 => Opcode::ITasm, + 351 => Opcode::Int_eh_sjlj_dispatchsetup, + 352 => Opcode::Int_eh_sjlj_longjmp, + 353 => Opcode::Int_eh_sjlj_setjmp, + 354 => Opcode::Int_eh_sjlj_setjmp_nofp, + 355 => Opcode::Int_eh_sjlj_setup_dispatch, + 356 => Opcode::JUMPTABLE_ADDRS, + 357 => Opcode::JUMPTABLE_INSTS, + 358 => Opcode::JUMPTABLE_TBB, + 359 => Opcode::JUMPTABLE_TBH, + 360 => Opcode::KCFI_CHECK_ARM, + 361 => Opcode::KCFI_CHECK_Thumb1, + 362 => Opcode::KCFI_CHECK_Thumb2, + 363 => Opcode::LDMIA_RET, + 364 => Opcode::LDRBT_POST, + 365 => Opcode::LDRConstPool, + 366 => Opcode::LDRHTii, + 367 => Opcode::LDRLIT_ga_abs, + 368 => Opcode::LDRLIT_ga_pcrel, + 369 => Opcode::LDRLIT_ga_pcrel_ldr, + 370 => Opcode::LDRSBTii, + 371 => Opcode::LDRSHTii, + 372 => Opcode::LDRT_POST, + 373 => Opcode::LEApcrel, + 374 => Opcode::LEApcrelJT, + 375 => Opcode::LOADDUAL, + 376 => Opcode::LSLi, + 377 => Opcode::LSLr, + 378 => Opcode::LSRi, + 379 => Opcode::LSRr, + 380 => Opcode::LSRs1, + 381 => Opcode::MEMCPY, + 382 => Opcode::MLAv5, + 383 => Opcode::MOVCCi, + 384 => Opcode::MOVCCi16, + 385 => Opcode::MOVCCi32imm, + 386 => Opcode::MOVCCr, + 387 => Opcode::MOVCCsi, + 388 => Opcode::MOVCCsr, + 389 => Opcode::MOVPCRX, + 390 => Opcode::MOVTi16_ga_pcrel, + 391 => Opcode::MOV_ga_pcrel, + 392 => Opcode::MOV_ga_pcrel_ldr, + 393 => Opcode::MOVi16_ga_pcrel, + 394 => Opcode::MOVi32imm, + 395 => Opcode::MQPRCopy, + 396 => Opcode::MQQPRLoad, + 397 => Opcode::MQQPRStore, + 398 => Opcode::MQQQQPRLoad, + 399 => Opcode::MQQQQPRStore, + 400 => Opcode::MULv5, + 401 => Opcode::MVE_MEMCPYLOOPINST, + 402 => Opcode::MVE_MEMSETLOOPINST, + 403 => Opcode::MVNCCi, + 404 => Opcode::PICADD, + 405 => Opcode::PICLDR, + 406 => Opcode::PICLDRB, + 407 => Opcode::PICLDRH, + 408 => Opcode::PICLDRSB, + 409 => Opcode::PICLDRSH, + 410 => Opcode::PICSTR, + 411 => Opcode::PICSTRB, + 412 => Opcode::PICSTRH, + 413 => Opcode::RORi, + 414 => Opcode::RORr, + 415 => Opcode::RRX, + 416 => Opcode::RRXi, + 417 => Opcode::RSBSri, + 418 => Opcode::RSBSrsi, + 419 => Opcode::RSBSrsr, + 420 => Opcode::SEH_EpilogEnd, + 421 => Opcode::SEH_EpilogStart, + 422 => Opcode::SEH_Nop, + 423 => Opcode::SEH_Nop_Ret, + 424 => Opcode::SEH_PrologEnd, + 425 => Opcode::SEH_SaveFRegs, + 426 => Opcode::SEH_SaveLR, + 427 => Opcode::SEH_SaveRegs, + 428 => Opcode::SEH_SaveRegs_Ret, + 429 => Opcode::SEH_SaveSP, + 430 => Opcode::SEH_StackAlloc, + 431 => Opcode::SMLALv5, + 432 => Opcode::SMULLv5, + 433 => Opcode::SPACE, + 434 => Opcode::STOREDUAL, + 435 => Opcode::STRBT_POST, + 436 => Opcode::STRBi_preidx, + 437 => Opcode::STRBr_preidx, + 438 => Opcode::STRH_preidx, + 439 => Opcode::STRT_POST, + 440 => Opcode::STRi_preidx, + 441 => Opcode::STRr_preidx, + 442 => Opcode::SUBS_PC_LR, + 443 => Opcode::SUBSri, + 444 => Opcode::SUBSrr, + 445 => Opcode::SUBSrsi, + 446 => Opcode::SUBSrsr, + 447 => Opcode::SpeculationBarrierISBDSBEndBB, + 448 => Opcode::SpeculationBarrierSBEndBB, + 449 => Opcode::TAILJMPd, + 450 => Opcode::TAILJMPr, + 451 => Opcode::TAILJMPr4, + 452 => Opcode::TCRETURNdi, + 453 => Opcode::TCRETURNri, + 454 => Opcode::TCRETURNrinotr12, + 455 => Opcode::TPsoft, + 456 => Opcode::UMLALv5, + 457 => Opcode::UMULLv5, + 458 => Opcode::VLD1LNdAsm_16, + 459 => Opcode::VLD1LNdAsm_32, + 460 => Opcode::VLD1LNdAsm_8, + 461 => Opcode::VLD1LNdWB_fixed_Asm_16, + 462 => Opcode::VLD1LNdWB_fixed_Asm_32, + 463 => Opcode::VLD1LNdWB_fixed_Asm_8, + 464 => Opcode::VLD1LNdWB_register_Asm_16, + 465 => Opcode::VLD1LNdWB_register_Asm_32, + 466 => Opcode::VLD1LNdWB_register_Asm_8, + 467 => Opcode::VLD2LNdAsm_16, + 468 => Opcode::VLD2LNdAsm_32, + 469 => Opcode::VLD2LNdAsm_8, + 470 => Opcode::VLD2LNdWB_fixed_Asm_16, + 471 => Opcode::VLD2LNdWB_fixed_Asm_32, + 472 => Opcode::VLD2LNdWB_fixed_Asm_8, + 473 => Opcode::VLD2LNdWB_register_Asm_16, + 474 => Opcode::VLD2LNdWB_register_Asm_32, + 475 => Opcode::VLD2LNdWB_register_Asm_8, + 476 => Opcode::VLD2LNqAsm_16, + 477 => Opcode::VLD2LNqAsm_32, + 478 => Opcode::VLD2LNqWB_fixed_Asm_16, + 479 => Opcode::VLD2LNqWB_fixed_Asm_32, + 480 => Opcode::VLD2LNqWB_register_Asm_16, + 481 => Opcode::VLD2LNqWB_register_Asm_32, + 482 => Opcode::VLD3DUPdAsm_16, + 483 => Opcode::VLD3DUPdAsm_32, + 484 => Opcode::VLD3DUPdAsm_8, + 485 => Opcode::VLD3DUPdWB_fixed_Asm_16, + 486 => Opcode::VLD3DUPdWB_fixed_Asm_32, + 487 => Opcode::VLD3DUPdWB_fixed_Asm_8, + 488 => Opcode::VLD3DUPdWB_register_Asm_16, + 489 => Opcode::VLD3DUPdWB_register_Asm_32, + 490 => Opcode::VLD3DUPdWB_register_Asm_8, + 491 => Opcode::VLD3DUPqAsm_16, + 492 => Opcode::VLD3DUPqAsm_32, + 493 => Opcode::VLD3DUPqAsm_8, + 494 => Opcode::VLD3DUPqWB_fixed_Asm_16, + 495 => Opcode::VLD3DUPqWB_fixed_Asm_32, + 496 => Opcode::VLD3DUPqWB_fixed_Asm_8, + 497 => Opcode::VLD3DUPqWB_register_Asm_16, + 498 => Opcode::VLD3DUPqWB_register_Asm_32, + 499 => Opcode::VLD3DUPqWB_register_Asm_8, + 500 => Opcode::VLD3LNdAsm_16, + 501 => Opcode::VLD3LNdAsm_32, + 502 => Opcode::VLD3LNdAsm_8, + 503 => Opcode::VLD3LNdWB_fixed_Asm_16, + 504 => Opcode::VLD3LNdWB_fixed_Asm_32, + 505 => Opcode::VLD3LNdWB_fixed_Asm_8, + 506 => Opcode::VLD3LNdWB_register_Asm_16, + 507 => Opcode::VLD3LNdWB_register_Asm_32, + 508 => Opcode::VLD3LNdWB_register_Asm_8, + 509 => Opcode::VLD3LNqAsm_16, + 510 => Opcode::VLD3LNqAsm_32, + 511 => Opcode::VLD3LNqWB_fixed_Asm_16, + 512 => Opcode::VLD3LNqWB_fixed_Asm_32, + 513 => Opcode::VLD3LNqWB_register_Asm_16, + 514 => Opcode::VLD3LNqWB_register_Asm_32, + 515 => Opcode::VLD3dAsm_16, + 516 => Opcode::VLD3dAsm_32, + 517 => Opcode::VLD3dAsm_8, + 518 => Opcode::VLD3dWB_fixed_Asm_16, + 519 => Opcode::VLD3dWB_fixed_Asm_32, + 520 => Opcode::VLD3dWB_fixed_Asm_8, + 521 => Opcode::VLD3dWB_register_Asm_16, + 522 => Opcode::VLD3dWB_register_Asm_32, + 523 => Opcode::VLD3dWB_register_Asm_8, + 524 => Opcode::VLD3qAsm_16, + 525 => Opcode::VLD3qAsm_32, + 526 => Opcode::VLD3qAsm_8, + 527 => Opcode::VLD3qWB_fixed_Asm_16, + 528 => Opcode::VLD3qWB_fixed_Asm_32, + 529 => Opcode::VLD3qWB_fixed_Asm_8, + 530 => Opcode::VLD3qWB_register_Asm_16, + 531 => Opcode::VLD3qWB_register_Asm_32, + 532 => Opcode::VLD3qWB_register_Asm_8, + 533 => Opcode::VLD4DUPdAsm_16, + 534 => Opcode::VLD4DUPdAsm_32, + 535 => Opcode::VLD4DUPdAsm_8, + 536 => Opcode::VLD4DUPdWB_fixed_Asm_16, + 537 => Opcode::VLD4DUPdWB_fixed_Asm_32, + 538 => Opcode::VLD4DUPdWB_fixed_Asm_8, + 539 => Opcode::VLD4DUPdWB_register_Asm_16, + 540 => Opcode::VLD4DUPdWB_register_Asm_32, + 541 => Opcode::VLD4DUPdWB_register_Asm_8, + 542 => Opcode::VLD4DUPqAsm_16, + 543 => Opcode::VLD4DUPqAsm_32, + 544 => Opcode::VLD4DUPqAsm_8, + 545 => Opcode::VLD4DUPqWB_fixed_Asm_16, + 546 => Opcode::VLD4DUPqWB_fixed_Asm_32, + 547 => Opcode::VLD4DUPqWB_fixed_Asm_8, + 548 => Opcode::VLD4DUPqWB_register_Asm_16, + 549 => Opcode::VLD4DUPqWB_register_Asm_32, + 550 => Opcode::VLD4DUPqWB_register_Asm_8, + 551 => Opcode::VLD4LNdAsm_16, + 552 => Opcode::VLD4LNdAsm_32, + 553 => Opcode::VLD4LNdAsm_8, + 554 => Opcode::VLD4LNdWB_fixed_Asm_16, + 555 => Opcode::VLD4LNdWB_fixed_Asm_32, + 556 => Opcode::VLD4LNdWB_fixed_Asm_8, + 557 => Opcode::VLD4LNdWB_register_Asm_16, + 558 => Opcode::VLD4LNdWB_register_Asm_32, + 559 => Opcode::VLD4LNdWB_register_Asm_8, + 560 => Opcode::VLD4LNqAsm_16, + 561 => Opcode::VLD4LNqAsm_32, + 562 => Opcode::VLD4LNqWB_fixed_Asm_16, + 563 => Opcode::VLD4LNqWB_fixed_Asm_32, + 564 => Opcode::VLD4LNqWB_register_Asm_16, + 565 => Opcode::VLD4LNqWB_register_Asm_32, + 566 => Opcode::VLD4dAsm_16, + 567 => Opcode::VLD4dAsm_32, + 568 => Opcode::VLD4dAsm_8, + 569 => Opcode::VLD4dWB_fixed_Asm_16, + 570 => Opcode::VLD4dWB_fixed_Asm_32, + 571 => Opcode::VLD4dWB_fixed_Asm_8, + 572 => Opcode::VLD4dWB_register_Asm_16, + 573 => Opcode::VLD4dWB_register_Asm_32, + 574 => Opcode::VLD4dWB_register_Asm_8, + 575 => Opcode::VLD4qAsm_16, + 576 => Opcode::VLD4qAsm_32, + 577 => Opcode::VLD4qAsm_8, + 578 => Opcode::VLD4qWB_fixed_Asm_16, + 579 => Opcode::VLD4qWB_fixed_Asm_32, + 580 => Opcode::VLD4qWB_fixed_Asm_8, + 581 => Opcode::VLD4qWB_register_Asm_16, + 582 => Opcode::VLD4qWB_register_Asm_32, + 583 => Opcode::VLD4qWB_register_Asm_8, + 584 => Opcode::VMOVD0, + 585 => Opcode::VMOVDcc, + 586 => Opcode::VMOVHcc, + 587 => Opcode::VMOVQ0, + 588 => Opcode::VMOVScc, + 589 => Opcode::VST1LNdAsm_16, + 590 => Opcode::VST1LNdAsm_32, + 591 => Opcode::VST1LNdAsm_8, + 592 => Opcode::VST1LNdWB_fixed_Asm_16, + 593 => Opcode::VST1LNdWB_fixed_Asm_32, + 594 => Opcode::VST1LNdWB_fixed_Asm_8, + 595 => Opcode::VST1LNdWB_register_Asm_16, + 596 => Opcode::VST1LNdWB_register_Asm_32, + 597 => Opcode::VST1LNdWB_register_Asm_8, + 598 => Opcode::VST2LNdAsm_16, + 599 => Opcode::VST2LNdAsm_32, + 600 => Opcode::VST2LNdAsm_8, + 601 => Opcode::VST2LNdWB_fixed_Asm_16, + 602 => Opcode::VST2LNdWB_fixed_Asm_32, + 603 => Opcode::VST2LNdWB_fixed_Asm_8, + 604 => Opcode::VST2LNdWB_register_Asm_16, + 605 => Opcode::VST2LNdWB_register_Asm_32, + 606 => Opcode::VST2LNdWB_register_Asm_8, + 607 => Opcode::VST2LNqAsm_16, + 608 => Opcode::VST2LNqAsm_32, + 609 => Opcode::VST2LNqWB_fixed_Asm_16, + 610 => Opcode::VST2LNqWB_fixed_Asm_32, + 611 => Opcode::VST2LNqWB_register_Asm_16, + 612 => Opcode::VST2LNqWB_register_Asm_32, + 613 => Opcode::VST3LNdAsm_16, + 614 => Opcode::VST3LNdAsm_32, + 615 => Opcode::VST3LNdAsm_8, + 616 => Opcode::VST3LNdWB_fixed_Asm_16, + 617 => Opcode::VST3LNdWB_fixed_Asm_32, + 618 => Opcode::VST3LNdWB_fixed_Asm_8, + 619 => Opcode::VST3LNdWB_register_Asm_16, + 620 => Opcode::VST3LNdWB_register_Asm_32, + 621 => Opcode::VST3LNdWB_register_Asm_8, + 622 => Opcode::VST3LNqAsm_16, + 623 => Opcode::VST3LNqAsm_32, + 624 => Opcode::VST3LNqWB_fixed_Asm_16, + 625 => Opcode::VST3LNqWB_fixed_Asm_32, + 626 => Opcode::VST3LNqWB_register_Asm_16, + 627 => Opcode::VST3LNqWB_register_Asm_32, + 628 => Opcode::VST3dAsm_16, + 629 => Opcode::VST3dAsm_32, + 630 => Opcode::VST3dAsm_8, + 631 => Opcode::VST3dWB_fixed_Asm_16, + 632 => Opcode::VST3dWB_fixed_Asm_32, + 633 => Opcode::VST3dWB_fixed_Asm_8, + 634 => Opcode::VST3dWB_register_Asm_16, + 635 => Opcode::VST3dWB_register_Asm_32, + 636 => Opcode::VST3dWB_register_Asm_8, + 637 => Opcode::VST3qAsm_16, + 638 => Opcode::VST3qAsm_32, + 639 => Opcode::VST3qAsm_8, + 640 => Opcode::VST3qWB_fixed_Asm_16, + 641 => Opcode::VST3qWB_fixed_Asm_32, + 642 => Opcode::VST3qWB_fixed_Asm_8, + 643 => Opcode::VST3qWB_register_Asm_16, + 644 => Opcode::VST3qWB_register_Asm_32, + 645 => Opcode::VST3qWB_register_Asm_8, + 646 => Opcode::VST4LNdAsm_16, + 647 => Opcode::VST4LNdAsm_32, + 648 => Opcode::VST4LNdAsm_8, + 649 => Opcode::VST4LNdWB_fixed_Asm_16, + 650 => Opcode::VST4LNdWB_fixed_Asm_32, + 651 => Opcode::VST4LNdWB_fixed_Asm_8, + 652 => Opcode::VST4LNdWB_register_Asm_16, + 653 => Opcode::VST4LNdWB_register_Asm_32, + 654 => Opcode::VST4LNdWB_register_Asm_8, + 655 => Opcode::VST4LNqAsm_16, + 656 => Opcode::VST4LNqAsm_32, + 657 => Opcode::VST4LNqWB_fixed_Asm_16, + 658 => Opcode::VST4LNqWB_fixed_Asm_32, + 659 => Opcode::VST4LNqWB_register_Asm_16, + 660 => Opcode::VST4LNqWB_register_Asm_32, + 661 => Opcode::VST4dAsm_16, + 662 => Opcode::VST4dAsm_32, + 663 => Opcode::VST4dAsm_8, + 664 => Opcode::VST4dWB_fixed_Asm_16, + 665 => Opcode::VST4dWB_fixed_Asm_32, + 666 => Opcode::VST4dWB_fixed_Asm_8, + 667 => Opcode::VST4dWB_register_Asm_16, + 668 => Opcode::VST4dWB_register_Asm_32, + 669 => Opcode::VST4dWB_register_Asm_8, + 670 => Opcode::VST4qAsm_16, + 671 => Opcode::VST4qAsm_32, + 672 => Opcode::VST4qAsm_8, + 673 => Opcode::VST4qWB_fixed_Asm_16, + 674 => Opcode::VST4qWB_fixed_Asm_32, + 675 => Opcode::VST4qWB_fixed_Asm_8, + 676 => Opcode::VST4qWB_register_Asm_16, + 677 => Opcode::VST4qWB_register_Asm_32, + 678 => Opcode::VST4qWB_register_Asm_8, + 679 => Opcode::WIN__CHKSTK, + 680 => Opcode::WIN__DBZCHK, + 681 => Opcode::t2ADDSri, + 682 => Opcode::t2ADDSrr, + 683 => Opcode::t2ADDSrs, + 684 => Opcode::t2BF_LabelPseudo, + 685 => Opcode::t2BR_JT, + 686 => Opcode::t2CALL_BTI, + 687 => Opcode::t2DoLoopStart, + 688 => Opcode::t2DoLoopStartTP, + 689 => Opcode::t2LDMIA_RET, + 690 => Opcode::t2LDRB_OFFSET_imm, + 691 => Opcode::t2LDRB_POST_imm, + 692 => Opcode::t2LDRB_PRE_imm, + 693 => Opcode::t2LDRBpcrel, + 694 => Opcode::t2LDRConstPool, + 695 => Opcode::t2LDRH_OFFSET_imm, + 696 => Opcode::t2LDRH_POST_imm, + 697 => Opcode::t2LDRH_PRE_imm, + 698 => Opcode::t2LDRHpcrel, + 699 => Opcode::t2LDRLIT_ga_pcrel, + 700 => Opcode::t2LDRSB_OFFSET_imm, + 701 => Opcode::t2LDRSB_POST_imm, + 702 => Opcode::t2LDRSB_PRE_imm, + 703 => Opcode::t2LDRSBpcrel, + 704 => Opcode::t2LDRSH_OFFSET_imm, + 705 => Opcode::t2LDRSH_POST_imm, + 706 => Opcode::t2LDRSH_PRE_imm, + 707 => Opcode::t2LDRSHpcrel, + 708 => Opcode::t2LDR_POST_imm, + 709 => Opcode::t2LDR_PRE_imm, + 710 => Opcode::t2LDRpci_pic, + 711 => Opcode::t2LDRpcrel, + 712 => Opcode::t2LEApcrel, + 713 => Opcode::t2LEApcrelJT, + 714 => Opcode::t2LoopDec, + 715 => Opcode::t2LoopEnd, + 716 => Opcode::t2LoopEndDec, + 717 => Opcode::t2MOVCCasr, + 718 => Opcode::t2MOVCCi, + 719 => Opcode::t2MOVCCi16, + 720 => Opcode::t2MOVCCi32imm, + 721 => Opcode::t2MOVCClsl, + 722 => Opcode::t2MOVCClsr, + 723 => Opcode::t2MOVCCr, + 724 => Opcode::t2MOVCCror, + 725 => Opcode::t2MOVSsi, + 726 => Opcode::t2MOVSsr, + 727 => Opcode::t2MOVTi16_ga_pcrel, + 728 => Opcode::t2MOV_ga_pcrel, + 729 => Opcode::t2MOVi16_ga_pcrel, + 730 => Opcode::t2MOVi32imm, + 731 => Opcode::t2MOVsi, + 732 => Opcode::t2MOVsr, + 733 => Opcode::t2MVNCCi, + 734 => Opcode::t2RSBSri, + 735 => Opcode::t2RSBSrs, + 736 => Opcode::t2STRB_OFFSET_imm, + 737 => Opcode::t2STRB_POST_imm, + 738 => Opcode::t2STRB_PRE_imm, + 739 => Opcode::t2STRB_preidx, + 740 => Opcode::t2STRH_OFFSET_imm, + 741 => Opcode::t2STRH_POST_imm, + 742 => Opcode::t2STRH_PRE_imm, + 743 => Opcode::t2STRH_preidx, + 744 => Opcode::t2STR_POST_imm, + 745 => Opcode::t2STR_PRE_imm, + 746 => Opcode::t2STR_preidx, + 747 => Opcode::t2SUBSri, + 748 => Opcode::t2SUBSrr, + 749 => Opcode::t2SUBSrs, + 750 => Opcode::t2SpeculationBarrierISBDSBEndBB, + 751 => Opcode::t2SpeculationBarrierSBEndBB, + 752 => Opcode::t2TBB_JT, + 753 => Opcode::t2TBH_JT, + 754 => Opcode::t2WhileLoopSetup, + 755 => Opcode::t2WhileLoopStart, + 756 => Opcode::t2WhileLoopStartLR, + 757 => Opcode::t2WhileLoopStartTP, + 758 => Opcode::tADCS, + 759 => Opcode::tADDSi3, + 760 => Opcode::tADDSi8, + 761 => Opcode::tADDSrr, + 762 => Opcode::tADDframe, + 763 => Opcode::tADJCALLSTACKDOWN, + 764 => Opcode::tADJCALLSTACKUP, + 765 => Opcode::tBLXNS_CALL, + 766 => Opcode::tBLXr_noip, + 767 => Opcode::tBL_PUSHLR, + 768 => Opcode::tBRIND, + 769 => Opcode::tBR_JTr, + 770 => Opcode::tBXNS_RET, + 771 => Opcode::tBX_CALL, + 772 => Opcode::tBX_RET, + 773 => Opcode::tBX_RET_vararg, + 774 => Opcode::tBfar, + 775 => Opcode::tCMP_SWAP_16, + 776 => Opcode::tCMP_SWAP_32, + 777 => Opcode::tCMP_SWAP_8, + 778 => Opcode::tLDMIA_UPD, + 779 => Opcode::tLDRConstPool, + 780 => Opcode::tLDRLIT_ga_abs, + 781 => Opcode::tLDRLIT_ga_pcrel, + 782 => Opcode::tLDR_postidx, + 783 => Opcode::tLDRpci_pic, + 784 => Opcode::tLEApcrel, + 785 => Opcode::tLEApcrelJT, + 786 => Opcode::tLSLSri, + 787 => Opcode::tMOVCCr_pseudo, + 788 => Opcode::tMOVi32imm, + 789 => Opcode::tPOP_RET, + 790 => Opcode::tRSBS, + 791 => Opcode::tSBCS, + 792 => Opcode::tSUBSi3, + 793 => Opcode::tSUBSi8, + 794 => Opcode::tSUBSrr, + 795 => Opcode::tTAILJMPd, + 796 => Opcode::tTAILJMPdND, + 797 => Opcode::tTAILJMPr, + 798 => Opcode::tTBB_JT, + 799 => Opcode::tTBH_JT, + 800 => Opcode::tTPsoft, + 801 => Opcode::ADCri, + 802 => Opcode::ADCrr, + 803 => Opcode::ADCrsi, + 804 => Opcode::ADCrsr, + 805 => Opcode::ADDri, + 806 => Opcode::ADDrr, + 807 => Opcode::ADDrsi, + 808 => Opcode::ADDrsr, + 809 => Opcode::ADR, + 810 => Opcode::AESD, + 811 => Opcode::AESE, + 812 => Opcode::AESIMC, + 813 => Opcode::AESMC, + 814 => Opcode::ANDri, + 815 => Opcode::ANDrr, + 816 => Opcode::ANDrsi, + 817 => Opcode::ANDrsr, + 818 => Opcode::BF16VDOTI_VDOTD, + 819 => Opcode::BF16VDOTI_VDOTQ, + 820 => Opcode::BF16VDOTS_VDOTD, + 821 => Opcode::BF16VDOTS_VDOTQ, + 822 => Opcode::BF16_VCVT, + 823 => Opcode::BF16_VCVTB, + 824 => Opcode::BF16_VCVTT, + 825 => Opcode::BFC, + 826 => Opcode::BFI, + 827 => Opcode::BICri, + 828 => Opcode::BICrr, + 829 => Opcode::BICrsi, + 830 => Opcode::BICrsr, + 831 => Opcode::BKPT, + 832 => Opcode::BL, + 833 => Opcode::BLX, + 834 => Opcode::BLX_pred, + 835 => Opcode::BLXi, + 836 => Opcode::BL_pred, + 837 => Opcode::BX, + 838 => Opcode::BXJ, + 839 => Opcode::BX_RET, + 840 => Opcode::BX_pred, + 841 => Opcode::Bcc, + 842 => Opcode::CDE_CX1, + 843 => Opcode::CDE_CX1A, + 844 => Opcode::CDE_CX1D, + 845 => Opcode::CDE_CX1DA, + 846 => Opcode::CDE_CX2, + 847 => Opcode::CDE_CX2A, + 848 => Opcode::CDE_CX2D, + 849 => Opcode::CDE_CX2DA, + 850 => Opcode::CDE_CX3, + 851 => Opcode::CDE_CX3A, + 852 => Opcode::CDE_CX3D, + 853 => Opcode::CDE_CX3DA, + 854 => Opcode::CDE_VCX1A_fpdp, + 855 => Opcode::CDE_VCX1A_fpsp, + 856 => Opcode::CDE_VCX1A_vec, + 857 => Opcode::CDE_VCX1_fpdp, + 858 => Opcode::CDE_VCX1_fpsp, + 859 => Opcode::CDE_VCX1_vec, + 860 => Opcode::CDE_VCX2A_fpdp, + 861 => Opcode::CDE_VCX2A_fpsp, + 862 => Opcode::CDE_VCX2A_vec, + 863 => Opcode::CDE_VCX2_fpdp, + 864 => Opcode::CDE_VCX2_fpsp, + 865 => Opcode::CDE_VCX2_vec, + 866 => Opcode::CDE_VCX3A_fpdp, + 867 => Opcode::CDE_VCX3A_fpsp, + 868 => Opcode::CDE_VCX3A_vec, + 869 => Opcode::CDE_VCX3_fpdp, + 870 => Opcode::CDE_VCX3_fpsp, + 871 => Opcode::CDE_VCX3_vec, + 872 => Opcode::CDP, + 873 => Opcode::CDP2, + 874 => Opcode::CLREX, + 875 => Opcode::CLZ, + 876 => Opcode::CMNri, + 877 => Opcode::CMNzrr, + 878 => Opcode::CMNzrsi, + 879 => Opcode::CMNzrsr, + 880 => Opcode::CMPri, + 881 => Opcode::CMPrr, + 882 => Opcode::CMPrsi, + 883 => Opcode::CMPrsr, + 884 => Opcode::CPS1p, + 885 => Opcode::CPS2p, + 886 => Opcode::CPS3p, + 887 => Opcode::CRC32B, + 888 => Opcode::CRC32CB, + 889 => Opcode::CRC32CH, + 890 => Opcode::CRC32CW, + 891 => Opcode::CRC32H, + 892 => Opcode::CRC32W, + 893 => Opcode::DBG, + 894 => Opcode::DMB, + 895 => Opcode::DSB, + 896 => Opcode::EORri, + 897 => Opcode::EORrr, + 898 => Opcode::EORrsi, + 899 => Opcode::EORrsr, + 900 => Opcode::ERET, + 901 => Opcode::FCONSTD, + 902 => Opcode::FCONSTH, + 903 => Opcode::FCONSTS, + 904 => Opcode::FLDMXDB_UPD, + 905 => Opcode::FLDMXIA, + 906 => Opcode::FLDMXIA_UPD, + 907 => Opcode::FMSTAT, + 908 => Opcode::FSTMXDB_UPD, + 909 => Opcode::FSTMXIA, + 910 => Opcode::FSTMXIA_UPD, + 911 => Opcode::HINT, + 912 => Opcode::HLT, + 913 => Opcode::HVC, + 914 => Opcode::ISB, + 915 => Opcode::LDA, + 916 => Opcode::LDAB, + 917 => Opcode::LDAEX, + 918 => Opcode::LDAEXB, + 919 => Opcode::LDAEXD, + 920 => Opcode::LDAEXH, + 921 => Opcode::LDAH, + 922 => Opcode::LDC2L_OFFSET, + 923 => Opcode::LDC2L_OPTION, + 924 => Opcode::LDC2L_POST, + 925 => Opcode::LDC2L_PRE, + 926 => Opcode::LDC2_OFFSET, + 927 => Opcode::LDC2_OPTION, + 928 => Opcode::LDC2_POST, + 929 => Opcode::LDC2_PRE, + 930 => Opcode::LDCL_OFFSET, + 931 => Opcode::LDCL_OPTION, + 932 => Opcode::LDCL_POST, + 933 => Opcode::LDCL_PRE, + 934 => Opcode::LDC_OFFSET, + 935 => Opcode::LDC_OPTION, + 936 => Opcode::LDC_POST, + 937 => Opcode::LDC_PRE, + 938 => Opcode::LDMDA, + 939 => Opcode::LDMDA_UPD, + 940 => Opcode::LDMDB, + 941 => Opcode::LDMDB_UPD, + 942 => Opcode::LDMIA, + 943 => Opcode::LDMIA_UPD, + 944 => Opcode::LDMIB, + 945 => Opcode::LDMIB_UPD, + 946 => Opcode::LDRBT_POST_IMM, + 947 => Opcode::LDRBT_POST_REG, + 948 => Opcode::LDRB_POST_IMM, + 949 => Opcode::LDRB_POST_REG, + 950 => Opcode::LDRB_PRE_IMM, + 951 => Opcode::LDRB_PRE_REG, + 952 => Opcode::LDRBi12, + 953 => Opcode::LDRBrs, + 954 => Opcode::LDRD, + 955 => Opcode::LDRD_POST, + 956 => Opcode::LDRD_PRE, + 957 => Opcode::LDREX, + 958 => Opcode::LDREXB, + 959 => Opcode::LDREXD, + 960 => Opcode::LDREXH, + 961 => Opcode::LDRH, + 962 => Opcode::LDRHTi, + 963 => Opcode::LDRHTr, + 964 => Opcode::LDRH_POST, + 965 => Opcode::LDRH_PRE, + 966 => Opcode::LDRSB, + 967 => Opcode::LDRSBTi, + 968 => Opcode::LDRSBTr, + 969 => Opcode::LDRSB_POST, + 970 => Opcode::LDRSB_PRE, + 971 => Opcode::LDRSH, + 972 => Opcode::LDRSHTi, + 973 => Opcode::LDRSHTr, + 974 => Opcode::LDRSH_POST, + 975 => Opcode::LDRSH_PRE, + 976 => Opcode::LDRT_POST_IMM, + 977 => Opcode::LDRT_POST_REG, + 978 => Opcode::LDR_POST_IMM, + 979 => Opcode::LDR_POST_REG, + 980 => Opcode::LDR_PRE_IMM, + 981 => Opcode::LDR_PRE_REG, + 982 => Opcode::LDRcp, + 983 => Opcode::LDRi12, + 984 => Opcode::LDRrs, + 985 => Opcode::MCR, + 986 => Opcode::MCR2, + 987 => Opcode::MCRR, + 988 => Opcode::MCRR2, + 989 => Opcode::MLA, + 990 => Opcode::MLS, + 991 => Opcode::MOVPCLR, + 992 => Opcode::MOVTi16, + 993 => Opcode::MOVi, + 994 => Opcode::MOVi16, + 995 => Opcode::MOVr, + 996 => Opcode::MOVr_TC, + 997 => Opcode::MOVsi, + 998 => Opcode::MOVsr, + 999 => Opcode::MRC, + 1000 => Opcode::MRC2, + 1001 => Opcode::MRRC, + 1002 => Opcode::MRRC2, + 1003 => Opcode::MRS, + 1004 => Opcode::MRSbanked, + 1005 => Opcode::MRSsys, + 1006 => Opcode::MSR, + 1007 => Opcode::MSRbanked, + 1008 => Opcode::MSRi, + 1009 => Opcode::MUL, + 1010 => Opcode::MVE_ASRLi, + 1011 => Opcode::MVE_ASRLr, + 1012 => Opcode::MVE_DLSTP_16, + 1013 => Opcode::MVE_DLSTP_32, + 1014 => Opcode::MVE_DLSTP_64, + 1015 => Opcode::MVE_DLSTP_8, + 1016 => Opcode::MVE_LCTP, + 1017 => Opcode::MVE_LETP, + 1018 => Opcode::MVE_LSLLi, + 1019 => Opcode::MVE_LSLLr, + 1020 => Opcode::MVE_LSRL, + 1021 => Opcode::MVE_SQRSHR, + 1022 => Opcode::MVE_SQRSHRL, + 1023 => Opcode::MVE_SQSHL, + 1024 => Opcode::MVE_SQSHLL, + 1025 => Opcode::MVE_SRSHR, + 1026 => Opcode::MVE_SRSHRL, + 1027 => Opcode::MVE_UQRSHL, + 1028 => Opcode::MVE_UQRSHLL, + 1029 => Opcode::MVE_UQSHL, + 1030 => Opcode::MVE_UQSHLL, + 1031 => Opcode::MVE_URSHR, + 1032 => Opcode::MVE_URSHRL, + 1033 => Opcode::MVE_VABAVs16, + 1034 => Opcode::MVE_VABAVs32, + 1035 => Opcode::MVE_VABAVs8, + 1036 => Opcode::MVE_VABAVu16, + 1037 => Opcode::MVE_VABAVu32, + 1038 => Opcode::MVE_VABAVu8, + 1039 => Opcode::MVE_VABDf16, + 1040 => Opcode::MVE_VABDf32, + 1041 => Opcode::MVE_VABDs16, + 1042 => Opcode::MVE_VABDs32, + 1043 => Opcode::MVE_VABDs8, + 1044 => Opcode::MVE_VABDu16, + 1045 => Opcode::MVE_VABDu32, + 1046 => Opcode::MVE_VABDu8, + 1047 => Opcode::MVE_VABSf16, + 1048 => Opcode::MVE_VABSf32, + 1049 => Opcode::MVE_VABSs16, + 1050 => Opcode::MVE_VABSs32, + 1051 => Opcode::MVE_VABSs8, + 1052 => Opcode::MVE_VADC, + 1053 => Opcode::MVE_VADCI, + 1054 => Opcode::MVE_VADDLVs32acc, + 1055 => Opcode::MVE_VADDLVs32no_acc, + 1056 => Opcode::MVE_VADDLVu32acc, + 1057 => Opcode::MVE_VADDLVu32no_acc, + 1058 => Opcode::MVE_VADDVs16acc, + 1059 => Opcode::MVE_VADDVs16no_acc, + 1060 => Opcode::MVE_VADDVs32acc, + 1061 => Opcode::MVE_VADDVs32no_acc, + 1062 => Opcode::MVE_VADDVs8acc, + 1063 => Opcode::MVE_VADDVs8no_acc, + 1064 => Opcode::MVE_VADDVu16acc, + 1065 => Opcode::MVE_VADDVu16no_acc, + 1066 => Opcode::MVE_VADDVu32acc, + 1067 => Opcode::MVE_VADDVu32no_acc, + 1068 => Opcode::MVE_VADDVu8acc, + 1069 => Opcode::MVE_VADDVu8no_acc, + 1070 => Opcode::MVE_VADD_qr_f16, + 1071 => Opcode::MVE_VADD_qr_f32, + 1072 => Opcode::MVE_VADD_qr_i16, + 1073 => Opcode::MVE_VADD_qr_i32, + 1074 => Opcode::MVE_VADD_qr_i8, + 1075 => Opcode::MVE_VADDf16, + 1076 => Opcode::MVE_VADDf32, + 1077 => Opcode::MVE_VADDi16, + 1078 => Opcode::MVE_VADDi32, + 1079 => Opcode::MVE_VADDi8, + 1080 => Opcode::MVE_VAND, + 1081 => Opcode::MVE_VBIC, + 1082 => Opcode::MVE_VBICimmi16, + 1083 => Opcode::MVE_VBICimmi32, + 1084 => Opcode::MVE_VBRSR16, + 1085 => Opcode::MVE_VBRSR32, + 1086 => Opcode::MVE_VBRSR8, + 1087 => Opcode::MVE_VCADDf16, + 1088 => Opcode::MVE_VCADDf32, + 1089 => Opcode::MVE_VCADDi16, + 1090 => Opcode::MVE_VCADDi32, + 1091 => Opcode::MVE_VCADDi8, + 1092 => Opcode::MVE_VCLSs16, + 1093 => Opcode::MVE_VCLSs32, + 1094 => Opcode::MVE_VCLSs8, + 1095 => Opcode::MVE_VCLZs16, + 1096 => Opcode::MVE_VCLZs32, + 1097 => Opcode::MVE_VCLZs8, + 1098 => Opcode::MVE_VCMLAf16, + 1099 => Opcode::MVE_VCMLAf32, + 1100 => Opcode::MVE_VCMPf16, + 1101 => Opcode::MVE_VCMPf16r, + 1102 => Opcode::MVE_VCMPf32, + 1103 => Opcode::MVE_VCMPf32r, + 1104 => Opcode::MVE_VCMPi16, + 1105 => Opcode::MVE_VCMPi16r, + 1106 => Opcode::MVE_VCMPi32, + 1107 => Opcode::MVE_VCMPi32r, + 1108 => Opcode::MVE_VCMPi8, + 1109 => Opcode::MVE_VCMPi8r, + 1110 => Opcode::MVE_VCMPs16, + 1111 => Opcode::MVE_VCMPs16r, + 1112 => Opcode::MVE_VCMPs32, + 1113 => Opcode::MVE_VCMPs32r, + 1114 => Opcode::MVE_VCMPs8, + 1115 => Opcode::MVE_VCMPs8r, + 1116 => Opcode::MVE_VCMPu16, + 1117 => Opcode::MVE_VCMPu16r, + 1118 => Opcode::MVE_VCMPu32, + 1119 => Opcode::MVE_VCMPu32r, + 1120 => Opcode::MVE_VCMPu8, + 1121 => Opcode::MVE_VCMPu8r, + 1122 => Opcode::MVE_VCMULf16, + 1123 => Opcode::MVE_VCMULf32, + 1124 => Opcode::MVE_VCTP16, + 1125 => Opcode::MVE_VCTP32, + 1126 => Opcode::MVE_VCTP64, + 1127 => Opcode::MVE_VCTP8, + 1128 => Opcode::MVE_VCVTf16f32bh, + 1129 => Opcode::MVE_VCVTf16f32th, + 1130 => Opcode::MVE_VCVTf16s16_fix, + 1131 => Opcode::MVE_VCVTf16s16n, + 1132 => Opcode::MVE_VCVTf16u16_fix, + 1133 => Opcode::MVE_VCVTf16u16n, + 1134 => Opcode::MVE_VCVTf32f16bh, + 1135 => Opcode::MVE_VCVTf32f16th, + 1136 => Opcode::MVE_VCVTf32s32_fix, + 1137 => Opcode::MVE_VCVTf32s32n, + 1138 => Opcode::MVE_VCVTf32u32_fix, + 1139 => Opcode::MVE_VCVTf32u32n, + 1140 => Opcode::MVE_VCVTs16f16_fix, + 1141 => Opcode::MVE_VCVTs16f16a, + 1142 => Opcode::MVE_VCVTs16f16m, + 1143 => Opcode::MVE_VCVTs16f16n, + 1144 => Opcode::MVE_VCVTs16f16p, + 1145 => Opcode::MVE_VCVTs16f16z, + 1146 => Opcode::MVE_VCVTs32f32_fix, + 1147 => Opcode::MVE_VCVTs32f32a, + 1148 => Opcode::MVE_VCVTs32f32m, + 1149 => Opcode::MVE_VCVTs32f32n, + 1150 => Opcode::MVE_VCVTs32f32p, + 1151 => Opcode::MVE_VCVTs32f32z, + 1152 => Opcode::MVE_VCVTu16f16_fix, + 1153 => Opcode::MVE_VCVTu16f16a, + 1154 => Opcode::MVE_VCVTu16f16m, + 1155 => Opcode::MVE_VCVTu16f16n, + 1156 => Opcode::MVE_VCVTu16f16p, + 1157 => Opcode::MVE_VCVTu16f16z, + 1158 => Opcode::MVE_VCVTu32f32_fix, + 1159 => Opcode::MVE_VCVTu32f32a, + 1160 => Opcode::MVE_VCVTu32f32m, + 1161 => Opcode::MVE_VCVTu32f32n, + 1162 => Opcode::MVE_VCVTu32f32p, + 1163 => Opcode::MVE_VCVTu32f32z, + 1164 => Opcode::MVE_VDDUPu16, + 1165 => Opcode::MVE_VDDUPu32, + 1166 => Opcode::MVE_VDDUPu8, + 1167 => Opcode::MVE_VDUP16, + 1168 => Opcode::MVE_VDUP32, + 1169 => Opcode::MVE_VDUP8, + 1170 => Opcode::MVE_VDWDUPu16, + 1171 => Opcode::MVE_VDWDUPu32, + 1172 => Opcode::MVE_VDWDUPu8, + 1173 => Opcode::MVE_VEOR, + 1174 => Opcode::MVE_VFMA_qr_Sf16, + 1175 => Opcode::MVE_VFMA_qr_Sf32, + 1176 => Opcode::MVE_VFMA_qr_f16, + 1177 => Opcode::MVE_VFMA_qr_f32, + 1178 => Opcode::MVE_VFMAf16, + 1179 => Opcode::MVE_VFMAf32, + 1180 => Opcode::MVE_VFMSf16, + 1181 => Opcode::MVE_VFMSf32, + 1182 => Opcode::MVE_VHADD_qr_s16, + 1183 => Opcode::MVE_VHADD_qr_s32, + 1184 => Opcode::MVE_VHADD_qr_s8, + 1185 => Opcode::MVE_VHADD_qr_u16, + 1186 => Opcode::MVE_VHADD_qr_u32, + 1187 => Opcode::MVE_VHADD_qr_u8, + 1188 => Opcode::MVE_VHADDs16, + 1189 => Opcode::MVE_VHADDs32, + 1190 => Opcode::MVE_VHADDs8, + 1191 => Opcode::MVE_VHADDu16, + 1192 => Opcode::MVE_VHADDu32, + 1193 => Opcode::MVE_VHADDu8, + 1194 => Opcode::MVE_VHCADDs16, + 1195 => Opcode::MVE_VHCADDs32, + 1196 => Opcode::MVE_VHCADDs8, + 1197 => Opcode::MVE_VHSUB_qr_s16, + 1198 => Opcode::MVE_VHSUB_qr_s32, + 1199 => Opcode::MVE_VHSUB_qr_s8, + 1200 => Opcode::MVE_VHSUB_qr_u16, + 1201 => Opcode::MVE_VHSUB_qr_u32, + 1202 => Opcode::MVE_VHSUB_qr_u8, + 1203 => Opcode::MVE_VHSUBs16, + 1204 => Opcode::MVE_VHSUBs32, + 1205 => Opcode::MVE_VHSUBs8, + 1206 => Opcode::MVE_VHSUBu16, + 1207 => Opcode::MVE_VHSUBu32, + 1208 => Opcode::MVE_VHSUBu8, + 1209 => Opcode::MVE_VIDUPu16, + 1210 => Opcode::MVE_VIDUPu32, + 1211 => Opcode::MVE_VIDUPu8, + 1212 => Opcode::MVE_VIWDUPu16, + 1213 => Opcode::MVE_VIWDUPu32, + 1214 => Opcode::MVE_VIWDUPu8, + 1215 => Opcode::MVE_VLD20_16, + 1216 => Opcode::MVE_VLD20_16_wb, + 1217 => Opcode::MVE_VLD20_32, + 1218 => Opcode::MVE_VLD20_32_wb, + 1219 => Opcode::MVE_VLD20_8, + 1220 => Opcode::MVE_VLD20_8_wb, + 1221 => Opcode::MVE_VLD21_16, + 1222 => Opcode::MVE_VLD21_16_wb, + 1223 => Opcode::MVE_VLD21_32, + 1224 => Opcode::MVE_VLD21_32_wb, + 1225 => Opcode::MVE_VLD21_8, + 1226 => Opcode::MVE_VLD21_8_wb, + 1227 => Opcode::MVE_VLD40_16, + 1228 => Opcode::MVE_VLD40_16_wb, + 1229 => Opcode::MVE_VLD40_32, + 1230 => Opcode::MVE_VLD40_32_wb, + 1231 => Opcode::MVE_VLD40_8, + 1232 => Opcode::MVE_VLD40_8_wb, + 1233 => Opcode::MVE_VLD41_16, + 1234 => Opcode::MVE_VLD41_16_wb, + 1235 => Opcode::MVE_VLD41_32, + 1236 => Opcode::MVE_VLD41_32_wb, + 1237 => Opcode::MVE_VLD41_8, + 1238 => Opcode::MVE_VLD41_8_wb, + 1239 => Opcode::MVE_VLD42_16, + 1240 => Opcode::MVE_VLD42_16_wb, + 1241 => Opcode::MVE_VLD42_32, + 1242 => Opcode::MVE_VLD42_32_wb, + 1243 => Opcode::MVE_VLD42_8, + 1244 => Opcode::MVE_VLD42_8_wb, + 1245 => Opcode::MVE_VLD43_16, + 1246 => Opcode::MVE_VLD43_16_wb, + 1247 => Opcode::MVE_VLD43_32, + 1248 => Opcode::MVE_VLD43_32_wb, + 1249 => Opcode::MVE_VLD43_8, + 1250 => Opcode::MVE_VLD43_8_wb, + 1251 => Opcode::MVE_VLDRBS16, + 1252 => Opcode::MVE_VLDRBS16_post, + 1253 => Opcode::MVE_VLDRBS16_pre, + 1254 => Opcode::MVE_VLDRBS16_rq, + 1255 => Opcode::MVE_VLDRBS32, + 1256 => Opcode::MVE_VLDRBS32_post, + 1257 => Opcode::MVE_VLDRBS32_pre, + 1258 => Opcode::MVE_VLDRBS32_rq, + 1259 => Opcode::MVE_VLDRBU16, + 1260 => Opcode::MVE_VLDRBU16_post, + 1261 => Opcode::MVE_VLDRBU16_pre, + 1262 => Opcode::MVE_VLDRBU16_rq, + 1263 => Opcode::MVE_VLDRBU32, + 1264 => Opcode::MVE_VLDRBU32_post, + 1265 => Opcode::MVE_VLDRBU32_pre, + 1266 => Opcode::MVE_VLDRBU32_rq, + 1267 => Opcode::MVE_VLDRBU8, + 1268 => Opcode::MVE_VLDRBU8_post, + 1269 => Opcode::MVE_VLDRBU8_pre, + 1270 => Opcode::MVE_VLDRBU8_rq, + 1271 => Opcode::MVE_VLDRDU64_qi, + 1272 => Opcode::MVE_VLDRDU64_qi_pre, + 1273 => Opcode::MVE_VLDRDU64_rq, + 1274 => Opcode::MVE_VLDRDU64_rq_u, + 1275 => Opcode::MVE_VLDRHS32, + 1276 => Opcode::MVE_VLDRHS32_post, + 1277 => Opcode::MVE_VLDRHS32_pre, + 1278 => Opcode::MVE_VLDRHS32_rq, + 1279 => Opcode::MVE_VLDRHS32_rq_u, + 1280 => Opcode::MVE_VLDRHU16, + 1281 => Opcode::MVE_VLDRHU16_post, + 1282 => Opcode::MVE_VLDRHU16_pre, + 1283 => Opcode::MVE_VLDRHU16_rq, + 1284 => Opcode::MVE_VLDRHU16_rq_u, + 1285 => Opcode::MVE_VLDRHU32, + 1286 => Opcode::MVE_VLDRHU32_post, + 1287 => Opcode::MVE_VLDRHU32_pre, + 1288 => Opcode::MVE_VLDRHU32_rq, + 1289 => Opcode::MVE_VLDRHU32_rq_u, + 1290 => Opcode::MVE_VLDRWU32, + 1291 => Opcode::MVE_VLDRWU32_post, + 1292 => Opcode::MVE_VLDRWU32_pre, + 1293 => Opcode::MVE_VLDRWU32_qi, + 1294 => Opcode::MVE_VLDRWU32_qi_pre, + 1295 => Opcode::MVE_VLDRWU32_rq, + 1296 => Opcode::MVE_VLDRWU32_rq_u, + 1297 => Opcode::MVE_VMAXAVs16, + 1298 => Opcode::MVE_VMAXAVs32, + 1299 => Opcode::MVE_VMAXAVs8, + 1300 => Opcode::MVE_VMAXAs16, + 1301 => Opcode::MVE_VMAXAs32, + 1302 => Opcode::MVE_VMAXAs8, + 1303 => Opcode::MVE_VMAXNMAVf16, + 1304 => Opcode::MVE_VMAXNMAVf32, + 1305 => Opcode::MVE_VMAXNMAf16, + 1306 => Opcode::MVE_VMAXNMAf32, + 1307 => Opcode::MVE_VMAXNMVf16, + 1308 => Opcode::MVE_VMAXNMVf32, + 1309 => Opcode::MVE_VMAXNMf16, + 1310 => Opcode::MVE_VMAXNMf32, + 1311 => Opcode::MVE_VMAXVs16, + 1312 => Opcode::MVE_VMAXVs32, + 1313 => Opcode::MVE_VMAXVs8, + 1314 => Opcode::MVE_VMAXVu16, + 1315 => Opcode::MVE_VMAXVu32, + 1316 => Opcode::MVE_VMAXVu8, + 1317 => Opcode::MVE_VMAXs16, + 1318 => Opcode::MVE_VMAXs32, + 1319 => Opcode::MVE_VMAXs8, + 1320 => Opcode::MVE_VMAXu16, + 1321 => Opcode::MVE_VMAXu32, + 1322 => Opcode::MVE_VMAXu8, + 1323 => Opcode::MVE_VMINAVs16, + 1324 => Opcode::MVE_VMINAVs32, + 1325 => Opcode::MVE_VMINAVs8, + 1326 => Opcode::MVE_VMINAs16, + 1327 => Opcode::MVE_VMINAs32, + 1328 => Opcode::MVE_VMINAs8, + 1329 => Opcode::MVE_VMINNMAVf16, + 1330 => Opcode::MVE_VMINNMAVf32, + 1331 => Opcode::MVE_VMINNMAf16, + 1332 => Opcode::MVE_VMINNMAf32, + 1333 => Opcode::MVE_VMINNMVf16, + 1334 => Opcode::MVE_VMINNMVf32, + 1335 => Opcode::MVE_VMINNMf16, + 1336 => Opcode::MVE_VMINNMf32, + 1337 => Opcode::MVE_VMINVs16, + 1338 => Opcode::MVE_VMINVs32, + 1339 => Opcode::MVE_VMINVs8, + 1340 => Opcode::MVE_VMINVu16, + 1341 => Opcode::MVE_VMINVu32, + 1342 => Opcode::MVE_VMINVu8, + 1343 => Opcode::MVE_VMINs16, + 1344 => Opcode::MVE_VMINs32, + 1345 => Opcode::MVE_VMINs8, + 1346 => Opcode::MVE_VMINu16, + 1347 => Opcode::MVE_VMINu32, + 1348 => Opcode::MVE_VMINu8, + 1349 => Opcode::MVE_VMLADAVas16, + 1350 => Opcode::MVE_VMLADAVas32, + 1351 => Opcode::MVE_VMLADAVas8, + 1352 => Opcode::MVE_VMLADAVau16, + 1353 => Opcode::MVE_VMLADAVau32, + 1354 => Opcode::MVE_VMLADAVau8, + 1355 => Opcode::MVE_VMLADAVaxs16, + 1356 => Opcode::MVE_VMLADAVaxs32, + 1357 => Opcode::MVE_VMLADAVaxs8, + 1358 => Opcode::MVE_VMLADAVs16, + 1359 => Opcode::MVE_VMLADAVs32, + 1360 => Opcode::MVE_VMLADAVs8, + 1361 => Opcode::MVE_VMLADAVu16, + 1362 => Opcode::MVE_VMLADAVu32, + 1363 => Opcode::MVE_VMLADAVu8, + 1364 => Opcode::MVE_VMLADAVxs16, + 1365 => Opcode::MVE_VMLADAVxs32, + 1366 => Opcode::MVE_VMLADAVxs8, + 1367 => Opcode::MVE_VMLALDAVas16, + 1368 => Opcode::MVE_VMLALDAVas32, + 1369 => Opcode::MVE_VMLALDAVau16, + 1370 => Opcode::MVE_VMLALDAVau32, + 1371 => Opcode::MVE_VMLALDAVaxs16, + 1372 => Opcode::MVE_VMLALDAVaxs32, + 1373 => Opcode::MVE_VMLALDAVs16, + 1374 => Opcode::MVE_VMLALDAVs32, + 1375 => Opcode::MVE_VMLALDAVu16, + 1376 => Opcode::MVE_VMLALDAVu32, + 1377 => Opcode::MVE_VMLALDAVxs16, + 1378 => Opcode::MVE_VMLALDAVxs32, + 1379 => Opcode::MVE_VMLAS_qr_i16, + 1380 => Opcode::MVE_VMLAS_qr_i32, + 1381 => Opcode::MVE_VMLAS_qr_i8, + 1382 => Opcode::MVE_VMLA_qr_i16, + 1383 => Opcode::MVE_VMLA_qr_i32, + 1384 => Opcode::MVE_VMLA_qr_i8, + 1385 => Opcode::MVE_VMLSDAVas16, + 1386 => Opcode::MVE_VMLSDAVas32, + 1387 => Opcode::MVE_VMLSDAVas8, + 1388 => Opcode::MVE_VMLSDAVaxs16, + 1389 => Opcode::MVE_VMLSDAVaxs32, + 1390 => Opcode::MVE_VMLSDAVaxs8, + 1391 => Opcode::MVE_VMLSDAVs16, + 1392 => Opcode::MVE_VMLSDAVs32, + 1393 => Opcode::MVE_VMLSDAVs8, + 1394 => Opcode::MVE_VMLSDAVxs16, + 1395 => Opcode::MVE_VMLSDAVxs32, + 1396 => Opcode::MVE_VMLSDAVxs8, + 1397 => Opcode::MVE_VMLSLDAVas16, + 1398 => Opcode::MVE_VMLSLDAVas32, + 1399 => Opcode::MVE_VMLSLDAVaxs16, + 1400 => Opcode::MVE_VMLSLDAVaxs32, + 1401 => Opcode::MVE_VMLSLDAVs16, + 1402 => Opcode::MVE_VMLSLDAVs32, + 1403 => Opcode::MVE_VMLSLDAVxs16, + 1404 => Opcode::MVE_VMLSLDAVxs32, + 1405 => Opcode::MVE_VMOVLs16bh, + 1406 => Opcode::MVE_VMOVLs16th, + 1407 => Opcode::MVE_VMOVLs8bh, + 1408 => Opcode::MVE_VMOVLs8th, + 1409 => Opcode::MVE_VMOVLu16bh, + 1410 => Opcode::MVE_VMOVLu16th, + 1411 => Opcode::MVE_VMOVLu8bh, + 1412 => Opcode::MVE_VMOVLu8th, + 1413 => Opcode::MVE_VMOVNi16bh, + 1414 => Opcode::MVE_VMOVNi16th, + 1415 => Opcode::MVE_VMOVNi32bh, + 1416 => Opcode::MVE_VMOVNi32th, + 1417 => Opcode::MVE_VMOV_from_lane_32, + 1418 => Opcode::MVE_VMOV_from_lane_s16, + 1419 => Opcode::MVE_VMOV_from_lane_s8, + 1420 => Opcode::MVE_VMOV_from_lane_u16, + 1421 => Opcode::MVE_VMOV_from_lane_u8, + 1422 => Opcode::MVE_VMOV_q_rr, + 1423 => Opcode::MVE_VMOV_rr_q, + 1424 => Opcode::MVE_VMOV_to_lane_16, + 1425 => Opcode::MVE_VMOV_to_lane_32, + 1426 => Opcode::MVE_VMOV_to_lane_8, + 1427 => Opcode::MVE_VMOVimmf32, + 1428 => Opcode::MVE_VMOVimmi16, + 1429 => Opcode::MVE_VMOVimmi32, + 1430 => Opcode::MVE_VMOVimmi64, + 1431 => Opcode::MVE_VMOVimmi8, + 1432 => Opcode::MVE_VMULHs16, + 1433 => Opcode::MVE_VMULHs32, + 1434 => Opcode::MVE_VMULHs8, + 1435 => Opcode::MVE_VMULHu16, + 1436 => Opcode::MVE_VMULHu32, + 1437 => Opcode::MVE_VMULHu8, + 1438 => Opcode::MVE_VMULLBp16, + 1439 => Opcode::MVE_VMULLBp8, + 1440 => Opcode::MVE_VMULLBs16, + 1441 => Opcode::MVE_VMULLBs32, + 1442 => Opcode::MVE_VMULLBs8, + 1443 => Opcode::MVE_VMULLBu16, + 1444 => Opcode::MVE_VMULLBu32, + 1445 => Opcode::MVE_VMULLBu8, + 1446 => Opcode::MVE_VMULLTp16, + 1447 => Opcode::MVE_VMULLTp8, + 1448 => Opcode::MVE_VMULLTs16, + 1449 => Opcode::MVE_VMULLTs32, + 1450 => Opcode::MVE_VMULLTs8, + 1451 => Opcode::MVE_VMULLTu16, + 1452 => Opcode::MVE_VMULLTu32, + 1453 => Opcode::MVE_VMULLTu8, + 1454 => Opcode::MVE_VMUL_qr_f16, + 1455 => Opcode::MVE_VMUL_qr_f32, + 1456 => Opcode::MVE_VMUL_qr_i16, + 1457 => Opcode::MVE_VMUL_qr_i32, + 1458 => Opcode::MVE_VMUL_qr_i8, + 1459 => Opcode::MVE_VMULf16, + 1460 => Opcode::MVE_VMULf32, + 1461 => Opcode::MVE_VMULi16, + 1462 => Opcode::MVE_VMULi32, + 1463 => Opcode::MVE_VMULi8, + 1464 => Opcode::MVE_VMVN, + 1465 => Opcode::MVE_VMVNimmi16, + 1466 => Opcode::MVE_VMVNimmi32, + 1467 => Opcode::MVE_VNEGf16, + 1468 => Opcode::MVE_VNEGf32, + 1469 => Opcode::MVE_VNEGs16, + 1470 => Opcode::MVE_VNEGs32, + 1471 => Opcode::MVE_VNEGs8, + 1472 => Opcode::MVE_VORN, + 1473 => Opcode::MVE_VORR, + 1474 => Opcode::MVE_VORRimmi16, + 1475 => Opcode::MVE_VORRimmi32, + 1476 => Opcode::MVE_VPNOT, + 1477 => Opcode::MVE_VPSEL, + 1478 => Opcode::MVE_VPST, + 1479 => Opcode::MVE_VPTv16i8, + 1480 => Opcode::MVE_VPTv16i8r, + 1481 => Opcode::MVE_VPTv16s8, + 1482 => Opcode::MVE_VPTv16s8r, + 1483 => Opcode::MVE_VPTv16u8, + 1484 => Opcode::MVE_VPTv16u8r, + 1485 => Opcode::MVE_VPTv4f32, + 1486 => Opcode::MVE_VPTv4f32r, + 1487 => Opcode::MVE_VPTv4i32, + 1488 => Opcode::MVE_VPTv4i32r, + 1489 => Opcode::MVE_VPTv4s32, + 1490 => Opcode::MVE_VPTv4s32r, + 1491 => Opcode::MVE_VPTv4u32, + 1492 => Opcode::MVE_VPTv4u32r, + 1493 => Opcode::MVE_VPTv8f16, + 1494 => Opcode::MVE_VPTv8f16r, + 1495 => Opcode::MVE_VPTv8i16, + 1496 => Opcode::MVE_VPTv8i16r, + 1497 => Opcode::MVE_VPTv8s16, + 1498 => Opcode::MVE_VPTv8s16r, + 1499 => Opcode::MVE_VPTv8u16, + 1500 => Opcode::MVE_VPTv8u16r, + 1501 => Opcode::MVE_VQABSs16, + 1502 => Opcode::MVE_VQABSs32, + 1503 => Opcode::MVE_VQABSs8, + 1504 => Opcode::MVE_VQADD_qr_s16, + 1505 => Opcode::MVE_VQADD_qr_s32, + 1506 => Opcode::MVE_VQADD_qr_s8, + 1507 => Opcode::MVE_VQADD_qr_u16, + 1508 => Opcode::MVE_VQADD_qr_u32, + 1509 => Opcode::MVE_VQADD_qr_u8, + 1510 => Opcode::MVE_VQADDs16, + 1511 => Opcode::MVE_VQADDs32, + 1512 => Opcode::MVE_VQADDs8, + 1513 => Opcode::MVE_VQADDu16, + 1514 => Opcode::MVE_VQADDu32, + 1515 => Opcode::MVE_VQADDu8, + 1516 => Opcode::MVE_VQDMLADHXs16, + 1517 => Opcode::MVE_VQDMLADHXs32, + 1518 => Opcode::MVE_VQDMLADHXs8, + 1519 => Opcode::MVE_VQDMLADHs16, + 1520 => Opcode::MVE_VQDMLADHs32, + 1521 => Opcode::MVE_VQDMLADHs8, + 1522 => Opcode::MVE_VQDMLAH_qrs16, + 1523 => Opcode::MVE_VQDMLAH_qrs32, + 1524 => Opcode::MVE_VQDMLAH_qrs8, + 1525 => Opcode::MVE_VQDMLASH_qrs16, + 1526 => Opcode::MVE_VQDMLASH_qrs32, + 1527 => Opcode::MVE_VQDMLASH_qrs8, + 1528 => Opcode::MVE_VQDMLSDHXs16, + 1529 => Opcode::MVE_VQDMLSDHXs32, + 1530 => Opcode::MVE_VQDMLSDHXs8, + 1531 => Opcode::MVE_VQDMLSDHs16, + 1532 => Opcode::MVE_VQDMLSDHs32, + 1533 => Opcode::MVE_VQDMLSDHs8, + 1534 => Opcode::MVE_VQDMULH_qr_s16, + 1535 => Opcode::MVE_VQDMULH_qr_s32, + 1536 => Opcode::MVE_VQDMULH_qr_s8, + 1537 => Opcode::MVE_VQDMULHi16, + 1538 => Opcode::MVE_VQDMULHi32, + 1539 => Opcode::MVE_VQDMULHi8, + 1540 => Opcode::MVE_VQDMULL_qr_s16bh, + 1541 => Opcode::MVE_VQDMULL_qr_s16th, + 1542 => Opcode::MVE_VQDMULL_qr_s32bh, + 1543 => Opcode::MVE_VQDMULL_qr_s32th, + 1544 => Opcode::MVE_VQDMULLs16bh, + 1545 => Opcode::MVE_VQDMULLs16th, + 1546 => Opcode::MVE_VQDMULLs32bh, + 1547 => Opcode::MVE_VQDMULLs32th, + 1548 => Opcode::MVE_VQMOVNs16bh, + 1549 => Opcode::MVE_VQMOVNs16th, + 1550 => Opcode::MVE_VQMOVNs32bh, + 1551 => Opcode::MVE_VQMOVNs32th, + 1552 => Opcode::MVE_VQMOVNu16bh, + 1553 => Opcode::MVE_VQMOVNu16th, + 1554 => Opcode::MVE_VQMOVNu32bh, + 1555 => Opcode::MVE_VQMOVNu32th, + 1556 => Opcode::MVE_VQMOVUNs16bh, + 1557 => Opcode::MVE_VQMOVUNs16th, + 1558 => Opcode::MVE_VQMOVUNs32bh, + 1559 => Opcode::MVE_VQMOVUNs32th, + 1560 => Opcode::MVE_VQNEGs16, + 1561 => Opcode::MVE_VQNEGs32, + 1562 => Opcode::MVE_VQNEGs8, + 1563 => Opcode::MVE_VQRDMLADHXs16, + 1564 => Opcode::MVE_VQRDMLADHXs32, + 1565 => Opcode::MVE_VQRDMLADHXs8, + 1566 => Opcode::MVE_VQRDMLADHs16, + 1567 => Opcode::MVE_VQRDMLADHs32, + 1568 => Opcode::MVE_VQRDMLADHs8, + 1569 => Opcode::MVE_VQRDMLAH_qrs16, + 1570 => Opcode::MVE_VQRDMLAH_qrs32, + 1571 => Opcode::MVE_VQRDMLAH_qrs8, + 1572 => Opcode::MVE_VQRDMLASH_qrs16, + 1573 => Opcode::MVE_VQRDMLASH_qrs32, + 1574 => Opcode::MVE_VQRDMLASH_qrs8, + 1575 => Opcode::MVE_VQRDMLSDHXs16, + 1576 => Opcode::MVE_VQRDMLSDHXs32, + 1577 => Opcode::MVE_VQRDMLSDHXs8, + 1578 => Opcode::MVE_VQRDMLSDHs16, + 1579 => Opcode::MVE_VQRDMLSDHs32, + 1580 => Opcode::MVE_VQRDMLSDHs8, + 1581 => Opcode::MVE_VQRDMULH_qr_s16, + 1582 => Opcode::MVE_VQRDMULH_qr_s32, + 1583 => Opcode::MVE_VQRDMULH_qr_s8, + 1584 => Opcode::MVE_VQRDMULHi16, + 1585 => Opcode::MVE_VQRDMULHi32, + 1586 => Opcode::MVE_VQRDMULHi8, + 1587 => Opcode::MVE_VQRSHL_by_vecs16, + 1588 => Opcode::MVE_VQRSHL_by_vecs32, + 1589 => Opcode::MVE_VQRSHL_by_vecs8, + 1590 => Opcode::MVE_VQRSHL_by_vecu16, + 1591 => Opcode::MVE_VQRSHL_by_vecu32, + 1592 => Opcode::MVE_VQRSHL_by_vecu8, + 1593 => Opcode::MVE_VQRSHL_qrs16, + 1594 => Opcode::MVE_VQRSHL_qrs32, + 1595 => Opcode::MVE_VQRSHL_qrs8, + 1596 => Opcode::MVE_VQRSHL_qru16, + 1597 => Opcode::MVE_VQRSHL_qru32, + 1598 => Opcode::MVE_VQRSHL_qru8, + 1599 => Opcode::MVE_VQRSHRNbhs16, + 1600 => Opcode::MVE_VQRSHRNbhs32, + 1601 => Opcode::MVE_VQRSHRNbhu16, + 1602 => Opcode::MVE_VQRSHRNbhu32, + 1603 => Opcode::MVE_VQRSHRNths16, + 1604 => Opcode::MVE_VQRSHRNths32, + 1605 => Opcode::MVE_VQRSHRNthu16, + 1606 => Opcode::MVE_VQRSHRNthu32, + 1607 => Opcode::MVE_VQRSHRUNs16bh, + 1608 => Opcode::MVE_VQRSHRUNs16th, + 1609 => Opcode::MVE_VQRSHRUNs32bh, + 1610 => Opcode::MVE_VQRSHRUNs32th, + 1611 => Opcode::MVE_VQSHLU_imms16, + 1612 => Opcode::MVE_VQSHLU_imms32, + 1613 => Opcode::MVE_VQSHLU_imms8, + 1614 => Opcode::MVE_VQSHL_by_vecs16, + 1615 => Opcode::MVE_VQSHL_by_vecs32, + 1616 => Opcode::MVE_VQSHL_by_vecs8, + 1617 => Opcode::MVE_VQSHL_by_vecu16, + 1618 => Opcode::MVE_VQSHL_by_vecu32, + 1619 => Opcode::MVE_VQSHL_by_vecu8, + 1620 => Opcode::MVE_VQSHL_qrs16, + 1621 => Opcode::MVE_VQSHL_qrs32, + 1622 => Opcode::MVE_VQSHL_qrs8, + 1623 => Opcode::MVE_VQSHL_qru16, + 1624 => Opcode::MVE_VQSHL_qru32, + 1625 => Opcode::MVE_VQSHL_qru8, + 1626 => Opcode::MVE_VQSHLimms16, + 1627 => Opcode::MVE_VQSHLimms32, + 1628 => Opcode::MVE_VQSHLimms8, + 1629 => Opcode::MVE_VQSHLimmu16, + 1630 => Opcode::MVE_VQSHLimmu32, + 1631 => Opcode::MVE_VQSHLimmu8, + 1632 => Opcode::MVE_VQSHRNbhs16, + 1633 => Opcode::MVE_VQSHRNbhs32, + 1634 => Opcode::MVE_VQSHRNbhu16, + 1635 => Opcode::MVE_VQSHRNbhu32, + 1636 => Opcode::MVE_VQSHRNths16, + 1637 => Opcode::MVE_VQSHRNths32, + 1638 => Opcode::MVE_VQSHRNthu16, + 1639 => Opcode::MVE_VQSHRNthu32, + 1640 => Opcode::MVE_VQSHRUNs16bh, + 1641 => Opcode::MVE_VQSHRUNs16th, + 1642 => Opcode::MVE_VQSHRUNs32bh, + 1643 => Opcode::MVE_VQSHRUNs32th, + 1644 => Opcode::MVE_VQSUB_qr_s16, + 1645 => Opcode::MVE_VQSUB_qr_s32, + 1646 => Opcode::MVE_VQSUB_qr_s8, + 1647 => Opcode::MVE_VQSUB_qr_u16, + 1648 => Opcode::MVE_VQSUB_qr_u32, + 1649 => Opcode::MVE_VQSUB_qr_u8, + 1650 => Opcode::MVE_VQSUBs16, + 1651 => Opcode::MVE_VQSUBs32, + 1652 => Opcode::MVE_VQSUBs8, + 1653 => Opcode::MVE_VQSUBu16, + 1654 => Opcode::MVE_VQSUBu32, + 1655 => Opcode::MVE_VQSUBu8, + 1656 => Opcode::MVE_VREV16_8, + 1657 => Opcode::MVE_VREV32_16, + 1658 => Opcode::MVE_VREV32_8, + 1659 => Opcode::MVE_VREV64_16, + 1660 => Opcode::MVE_VREV64_32, + 1661 => Opcode::MVE_VREV64_8, + 1662 => Opcode::MVE_VRHADDs16, + 1663 => Opcode::MVE_VRHADDs32, + 1664 => Opcode::MVE_VRHADDs8, + 1665 => Opcode::MVE_VRHADDu16, + 1666 => Opcode::MVE_VRHADDu32, + 1667 => Opcode::MVE_VRHADDu8, + 1668 => Opcode::MVE_VRINTf16A, + 1669 => Opcode::MVE_VRINTf16M, + 1670 => Opcode::MVE_VRINTf16N, + 1671 => Opcode::MVE_VRINTf16P, + 1672 => Opcode::MVE_VRINTf16X, + 1673 => Opcode::MVE_VRINTf16Z, + 1674 => Opcode::MVE_VRINTf32A, + 1675 => Opcode::MVE_VRINTf32M, + 1676 => Opcode::MVE_VRINTf32N, + 1677 => Opcode::MVE_VRINTf32P, + 1678 => Opcode::MVE_VRINTf32X, + 1679 => Opcode::MVE_VRINTf32Z, + 1680 => Opcode::MVE_VRMLALDAVHas32, + 1681 => Opcode::MVE_VRMLALDAVHau32, + 1682 => Opcode::MVE_VRMLALDAVHaxs32, + 1683 => Opcode::MVE_VRMLALDAVHs32, + 1684 => Opcode::MVE_VRMLALDAVHu32, + 1685 => Opcode::MVE_VRMLALDAVHxs32, + 1686 => Opcode::MVE_VRMLSLDAVHas32, + 1687 => Opcode::MVE_VRMLSLDAVHaxs32, + 1688 => Opcode::MVE_VRMLSLDAVHs32, + 1689 => Opcode::MVE_VRMLSLDAVHxs32, + 1690 => Opcode::MVE_VRMULHs16, + 1691 => Opcode::MVE_VRMULHs32, + 1692 => Opcode::MVE_VRMULHs8, + 1693 => Opcode::MVE_VRMULHu16, + 1694 => Opcode::MVE_VRMULHu32, + 1695 => Opcode::MVE_VRMULHu8, + 1696 => Opcode::MVE_VRSHL_by_vecs16, + 1697 => Opcode::MVE_VRSHL_by_vecs32, + 1698 => Opcode::MVE_VRSHL_by_vecs8, + 1699 => Opcode::MVE_VRSHL_by_vecu16, + 1700 => Opcode::MVE_VRSHL_by_vecu32, + 1701 => Opcode::MVE_VRSHL_by_vecu8, + 1702 => Opcode::MVE_VRSHL_qrs16, + 1703 => Opcode::MVE_VRSHL_qrs32, + 1704 => Opcode::MVE_VRSHL_qrs8, + 1705 => Opcode::MVE_VRSHL_qru16, + 1706 => Opcode::MVE_VRSHL_qru32, + 1707 => Opcode::MVE_VRSHL_qru8, + 1708 => Opcode::MVE_VRSHRNi16bh, + 1709 => Opcode::MVE_VRSHRNi16th, + 1710 => Opcode::MVE_VRSHRNi32bh, + 1711 => Opcode::MVE_VRSHRNi32th, + 1712 => Opcode::MVE_VRSHR_imms16, + 1713 => Opcode::MVE_VRSHR_imms32, + 1714 => Opcode::MVE_VRSHR_imms8, + 1715 => Opcode::MVE_VRSHR_immu16, + 1716 => Opcode::MVE_VRSHR_immu32, + 1717 => Opcode::MVE_VRSHR_immu8, + 1718 => Opcode::MVE_VSBC, + 1719 => Opcode::MVE_VSBCI, + 1720 => Opcode::MVE_VSHLC, + 1721 => Opcode::MVE_VSHLL_imms16bh, + 1722 => Opcode::MVE_VSHLL_imms16th, + 1723 => Opcode::MVE_VSHLL_imms8bh, + 1724 => Opcode::MVE_VSHLL_imms8th, + 1725 => Opcode::MVE_VSHLL_immu16bh, + 1726 => Opcode::MVE_VSHLL_immu16th, + 1727 => Opcode::MVE_VSHLL_immu8bh, + 1728 => Opcode::MVE_VSHLL_immu8th, + 1729 => Opcode::MVE_VSHLL_lws16bh, + 1730 => Opcode::MVE_VSHLL_lws16th, + 1731 => Opcode::MVE_VSHLL_lws8bh, + 1732 => Opcode::MVE_VSHLL_lws8th, + 1733 => Opcode::MVE_VSHLL_lwu16bh, + 1734 => Opcode::MVE_VSHLL_lwu16th, + 1735 => Opcode::MVE_VSHLL_lwu8bh, + 1736 => Opcode::MVE_VSHLL_lwu8th, + 1737 => Opcode::MVE_VSHL_by_vecs16, + 1738 => Opcode::MVE_VSHL_by_vecs32, + 1739 => Opcode::MVE_VSHL_by_vecs8, + 1740 => Opcode::MVE_VSHL_by_vecu16, + 1741 => Opcode::MVE_VSHL_by_vecu32, + 1742 => Opcode::MVE_VSHL_by_vecu8, + 1743 => Opcode::MVE_VSHL_immi16, + 1744 => Opcode::MVE_VSHL_immi32, + 1745 => Opcode::MVE_VSHL_immi8, + 1746 => Opcode::MVE_VSHL_qrs16, + 1747 => Opcode::MVE_VSHL_qrs32, + 1748 => Opcode::MVE_VSHL_qrs8, + 1749 => Opcode::MVE_VSHL_qru16, + 1750 => Opcode::MVE_VSHL_qru32, + 1751 => Opcode::MVE_VSHL_qru8, + 1752 => Opcode::MVE_VSHRNi16bh, + 1753 => Opcode::MVE_VSHRNi16th, + 1754 => Opcode::MVE_VSHRNi32bh, + 1755 => Opcode::MVE_VSHRNi32th, + 1756 => Opcode::MVE_VSHR_imms16, + 1757 => Opcode::MVE_VSHR_imms32, + 1758 => Opcode::MVE_VSHR_imms8, + 1759 => Opcode::MVE_VSHR_immu16, + 1760 => Opcode::MVE_VSHR_immu32, + 1761 => Opcode::MVE_VSHR_immu8, + 1762 => Opcode::MVE_VSLIimm16, + 1763 => Opcode::MVE_VSLIimm32, + 1764 => Opcode::MVE_VSLIimm8, + 1765 => Opcode::MVE_VSRIimm16, + 1766 => Opcode::MVE_VSRIimm32, + 1767 => Opcode::MVE_VSRIimm8, + 1768 => Opcode::MVE_VST20_16, + 1769 => Opcode::MVE_VST20_16_wb, + 1770 => Opcode::MVE_VST20_32, + 1771 => Opcode::MVE_VST20_32_wb, + 1772 => Opcode::MVE_VST20_8, + 1773 => Opcode::MVE_VST20_8_wb, + 1774 => Opcode::MVE_VST21_16, + 1775 => Opcode::MVE_VST21_16_wb, + 1776 => Opcode::MVE_VST21_32, + 1777 => Opcode::MVE_VST21_32_wb, + 1778 => Opcode::MVE_VST21_8, + 1779 => Opcode::MVE_VST21_8_wb, + 1780 => Opcode::MVE_VST40_16, + 1781 => Opcode::MVE_VST40_16_wb, + 1782 => Opcode::MVE_VST40_32, + 1783 => Opcode::MVE_VST40_32_wb, + 1784 => Opcode::MVE_VST40_8, + 1785 => Opcode::MVE_VST40_8_wb, + 1786 => Opcode::MVE_VST41_16, + 1787 => Opcode::MVE_VST41_16_wb, + 1788 => Opcode::MVE_VST41_32, + 1789 => Opcode::MVE_VST41_32_wb, + 1790 => Opcode::MVE_VST41_8, + 1791 => Opcode::MVE_VST41_8_wb, + 1792 => Opcode::MVE_VST42_16, + 1793 => Opcode::MVE_VST42_16_wb, + 1794 => Opcode::MVE_VST42_32, + 1795 => Opcode::MVE_VST42_32_wb, + 1796 => Opcode::MVE_VST42_8, + 1797 => Opcode::MVE_VST42_8_wb, + 1798 => Opcode::MVE_VST43_16, + 1799 => Opcode::MVE_VST43_16_wb, + 1800 => Opcode::MVE_VST43_32, + 1801 => Opcode::MVE_VST43_32_wb, + 1802 => Opcode::MVE_VST43_8, + 1803 => Opcode::MVE_VST43_8_wb, + 1804 => Opcode::MVE_VSTRB16, + 1805 => Opcode::MVE_VSTRB16_post, + 1806 => Opcode::MVE_VSTRB16_pre, + 1807 => Opcode::MVE_VSTRB16_rq, + 1808 => Opcode::MVE_VSTRB32, + 1809 => Opcode::MVE_VSTRB32_post, + 1810 => Opcode::MVE_VSTRB32_pre, + 1811 => Opcode::MVE_VSTRB32_rq, + 1812 => Opcode::MVE_VSTRB8_rq, + 1813 => Opcode::MVE_VSTRBU8, + 1814 => Opcode::MVE_VSTRBU8_post, + 1815 => Opcode::MVE_VSTRBU8_pre, + 1816 => Opcode::MVE_VSTRD64_qi, + 1817 => Opcode::MVE_VSTRD64_qi_pre, + 1818 => Opcode::MVE_VSTRD64_rq, + 1819 => Opcode::MVE_VSTRD64_rq_u, + 1820 => Opcode::MVE_VSTRH16_rq, + 1821 => Opcode::MVE_VSTRH16_rq_u, + 1822 => Opcode::MVE_VSTRH32, + 1823 => Opcode::MVE_VSTRH32_post, + 1824 => Opcode::MVE_VSTRH32_pre, + 1825 => Opcode::MVE_VSTRH32_rq, + 1826 => Opcode::MVE_VSTRH32_rq_u, + 1827 => Opcode::MVE_VSTRHU16, + 1828 => Opcode::MVE_VSTRHU16_post, + 1829 => Opcode::MVE_VSTRHU16_pre, + 1830 => Opcode::MVE_VSTRW32_qi, + 1831 => Opcode::MVE_VSTRW32_qi_pre, + 1832 => Opcode::MVE_VSTRW32_rq, + 1833 => Opcode::MVE_VSTRW32_rq_u, + 1834 => Opcode::MVE_VSTRWU32, + 1835 => Opcode::MVE_VSTRWU32_post, + 1836 => Opcode::MVE_VSTRWU32_pre, + 1837 => Opcode::MVE_VSUB_qr_f16, + 1838 => Opcode::MVE_VSUB_qr_f32, + 1839 => Opcode::MVE_VSUB_qr_i16, + 1840 => Opcode::MVE_VSUB_qr_i32, + 1841 => Opcode::MVE_VSUB_qr_i8, + 1842 => Opcode::MVE_VSUBf16, + 1843 => Opcode::MVE_VSUBf32, + 1844 => Opcode::MVE_VSUBi16, + 1845 => Opcode::MVE_VSUBi32, + 1846 => Opcode::MVE_VSUBi8, + 1847 => Opcode::MVE_WLSTP_16, + 1848 => Opcode::MVE_WLSTP_32, + 1849 => Opcode::MVE_WLSTP_64, + 1850 => Opcode::MVE_WLSTP_8, + 1851 => Opcode::MVNi, + 1852 => Opcode::MVNr, + 1853 => Opcode::MVNsi, + 1854 => Opcode::MVNsr, + 1855 => Opcode::NEON_VMAXNMNDf, + 1856 => Opcode::NEON_VMAXNMNDh, + 1857 => Opcode::NEON_VMAXNMNQf, + 1858 => Opcode::NEON_VMAXNMNQh, + 1859 => Opcode::NEON_VMINNMNDf, + 1860 => Opcode::NEON_VMINNMNDh, + 1861 => Opcode::NEON_VMINNMNQf, + 1862 => Opcode::NEON_VMINNMNQh, + 1863 => Opcode::ORRri, + 1864 => Opcode::ORRrr, + 1865 => Opcode::ORRrsi, + 1866 => Opcode::ORRrsr, + 1867 => Opcode::PKHBT, + 1868 => Opcode::PKHTB, + 1869 => Opcode::PLDWi12, + 1870 => Opcode::PLDWrs, + 1871 => Opcode::PLDi12, + 1872 => Opcode::PLDrs, + 1873 => Opcode::PLIi12, + 1874 => Opcode::PLIrs, + 1875 => Opcode::QADD, + 1876 => Opcode::QADD16, + 1877 => Opcode::QADD8, + 1878 => Opcode::QASX, + 1879 => Opcode::QDADD, + 1880 => Opcode::QDSUB, + 1881 => Opcode::QSAX, + 1882 => Opcode::QSUB, + 1883 => Opcode::QSUB16, + 1884 => Opcode::QSUB8, + 1885 => Opcode::RBIT, + 1886 => Opcode::REV, + 1887 => Opcode::REV16, + 1888 => Opcode::REVSH, + 1889 => Opcode::RFEDA, + 1890 => Opcode::RFEDA_UPD, + 1891 => Opcode::RFEDB, + 1892 => Opcode::RFEDB_UPD, + 1893 => Opcode::RFEIA, + 1894 => Opcode::RFEIA_UPD, + 1895 => Opcode::RFEIB, + 1896 => Opcode::RFEIB_UPD, + 1897 => Opcode::RSBri, + 1898 => Opcode::RSBrr, + 1899 => Opcode::RSBrsi, + 1900 => Opcode::RSBrsr, + 1901 => Opcode::RSCri, + 1902 => Opcode::RSCrr, + 1903 => Opcode::RSCrsi, + 1904 => Opcode::RSCrsr, + 1905 => Opcode::SADD16, + 1906 => Opcode::SADD8, + 1907 => Opcode::SASX, + 1908 => Opcode::SB, + 1909 => Opcode::SBCri, + 1910 => Opcode::SBCrr, + 1911 => Opcode::SBCrsi, + 1912 => Opcode::SBCrsr, + 1913 => Opcode::SBFX, + 1914 => Opcode::SDIV, + 1915 => Opcode::SEL, + 1916 => Opcode::SETEND, + 1917 => Opcode::SETPAN, + 1918 => Opcode::SHA1C, + 1919 => Opcode::SHA1H, + 1920 => Opcode::SHA1M, + 1921 => Opcode::SHA1P, + 1922 => Opcode::SHA1SU0, + 1923 => Opcode::SHA1SU1, + 1924 => Opcode::SHA256H, + 1925 => Opcode::SHA256H2, + 1926 => Opcode::SHA256SU0, + 1927 => Opcode::SHA256SU1, + 1928 => Opcode::SHADD16, + 1929 => Opcode::SHADD8, + 1930 => Opcode::SHASX, + 1931 => Opcode::SHSAX, + 1932 => Opcode::SHSUB16, + 1933 => Opcode::SHSUB8, + 1934 => Opcode::SMC, + 1935 => Opcode::SMLABB, + 1936 => Opcode::SMLABT, + 1937 => Opcode::SMLAD, + 1938 => Opcode::SMLADX, + 1939 => Opcode::SMLAL, + 1940 => Opcode::SMLALBB, + 1941 => Opcode::SMLALBT, + 1942 => Opcode::SMLALD, + 1943 => Opcode::SMLALDX, + 1944 => Opcode::SMLALTB, + 1945 => Opcode::SMLALTT, + 1946 => Opcode::SMLATB, + 1947 => Opcode::SMLATT, + 1948 => Opcode::SMLAWB, + 1949 => Opcode::SMLAWT, + 1950 => Opcode::SMLSD, + 1951 => Opcode::SMLSDX, + 1952 => Opcode::SMLSLD, + 1953 => Opcode::SMLSLDX, + 1954 => Opcode::SMMLA, + 1955 => Opcode::SMMLAR, + 1956 => Opcode::SMMLS, + 1957 => Opcode::SMMLSR, + 1958 => Opcode::SMMUL, + 1959 => Opcode::SMMULR, + 1960 => Opcode::SMUAD, + 1961 => Opcode::SMUADX, + 1962 => Opcode::SMULBB, + 1963 => Opcode::SMULBT, + 1964 => Opcode::SMULL, + 1965 => Opcode::SMULTB, + 1966 => Opcode::SMULTT, + 1967 => Opcode::SMULWB, + 1968 => Opcode::SMULWT, + 1969 => Opcode::SMUSD, + 1970 => Opcode::SMUSDX, + 1971 => Opcode::SRSDA, + 1972 => Opcode::SRSDA_UPD, + 1973 => Opcode::SRSDB, + 1974 => Opcode::SRSDB_UPD, + 1975 => Opcode::SRSIA, + 1976 => Opcode::SRSIA_UPD, + 1977 => Opcode::SRSIB, + 1978 => Opcode::SRSIB_UPD, + 1979 => Opcode::SSAT, + 1980 => Opcode::SSAT16, + 1981 => Opcode::SSAX, + 1982 => Opcode::SSUB16, + 1983 => Opcode::SSUB8, + 1984 => Opcode::STC2L_OFFSET, + 1985 => Opcode::STC2L_OPTION, + 1986 => Opcode::STC2L_POST, + 1987 => Opcode::STC2L_PRE, + 1988 => Opcode::STC2_OFFSET, + 1989 => Opcode::STC2_OPTION, + 1990 => Opcode::STC2_POST, + 1991 => Opcode::STC2_PRE, + 1992 => Opcode::STCL_OFFSET, + 1993 => Opcode::STCL_OPTION, + 1994 => Opcode::STCL_POST, + 1995 => Opcode::STCL_PRE, + 1996 => Opcode::STC_OFFSET, + 1997 => Opcode::STC_OPTION, + 1998 => Opcode::STC_POST, + 1999 => Opcode::STC_PRE, + 2000 => Opcode::STL, + 2001 => Opcode::STLB, + 2002 => Opcode::STLEX, + 2003 => Opcode::STLEXB, + 2004 => Opcode::STLEXD, + 2005 => Opcode::STLEXH, + 2006 => Opcode::STLH, + 2007 => Opcode::STMDA, + 2008 => Opcode::STMDA_UPD, + 2009 => Opcode::STMDB, + 2010 => Opcode::STMDB_UPD, + 2011 => Opcode::STMIA, + 2012 => Opcode::STMIA_UPD, + 2013 => Opcode::STMIB, + 2014 => Opcode::STMIB_UPD, + 2015 => Opcode::STRBT_POST_IMM, + 2016 => Opcode::STRBT_POST_REG, + 2017 => Opcode::STRB_POST_IMM, + 2018 => Opcode::STRB_POST_REG, + 2019 => Opcode::STRB_PRE_IMM, + 2020 => Opcode::STRB_PRE_REG, + 2021 => Opcode::STRBi12, + 2022 => Opcode::STRBrs, + 2023 => Opcode::STRD, + 2024 => Opcode::STRD_POST, + 2025 => Opcode::STRD_PRE, + 2026 => Opcode::STREX, + 2027 => Opcode::STREXB, + 2028 => Opcode::STREXD, + 2029 => Opcode::STREXH, + 2030 => Opcode::STRH, + 2031 => Opcode::STRHTi, + 2032 => Opcode::STRHTr, + 2033 => Opcode::STRH_POST, + 2034 => Opcode::STRH_PRE, + 2035 => Opcode::STRT_POST_IMM, + 2036 => Opcode::STRT_POST_REG, + 2037 => Opcode::STR_POST_IMM, + 2038 => Opcode::STR_POST_REG, + 2039 => Opcode::STR_PRE_IMM, + 2040 => Opcode::STR_PRE_REG, + 2041 => Opcode::STRi12, + 2042 => Opcode::STRrs, + 2043 => Opcode::SUBri, + 2044 => Opcode::SUBrr, + 2045 => Opcode::SUBrsi, + 2046 => Opcode::SUBrsr, + 2047 => Opcode::SVC, + 2048 => Opcode::SWP, + 2049 => Opcode::SWPB, + 2050 => Opcode::SXTAB, + 2051 => Opcode::SXTAB16, + 2052 => Opcode::SXTAH, + 2053 => Opcode::SXTB, + 2054 => Opcode::SXTB16, + 2055 => Opcode::SXTH, + 2056 => Opcode::TEQri, + 2057 => Opcode::TEQrr, + 2058 => Opcode::TEQrsi, + 2059 => Opcode::TEQrsr, + 2060 => Opcode::TRAP, + 2061 => Opcode::TSB, + 2062 => Opcode::TSTri, + 2063 => Opcode::TSTrr, + 2064 => Opcode::TSTrsi, + 2065 => Opcode::TSTrsr, + 2066 => Opcode::UADD16, + 2067 => Opcode::UADD8, + 2068 => Opcode::UASX, + 2069 => Opcode::UBFX, + 2070 => Opcode::UDF, + 2071 => Opcode::UDIV, + 2072 => Opcode::UHADD16, + 2073 => Opcode::UHADD8, + 2074 => Opcode::UHASX, + 2075 => Opcode::UHSAX, + 2076 => Opcode::UHSUB16, + 2077 => Opcode::UHSUB8, + 2078 => Opcode::UMAAL, + 2079 => Opcode::UMLAL, + 2080 => Opcode::UMULL, + 2081 => Opcode::UQADD16, + 2082 => Opcode::UQADD8, + 2083 => Opcode::UQASX, + 2084 => Opcode::UQSAX, + 2085 => Opcode::UQSUB16, + 2086 => Opcode::UQSUB8, + 2087 => Opcode::USAD8, + 2088 => Opcode::USADA8, + 2089 => Opcode::USAT, + 2090 => Opcode::USAT16, + 2091 => Opcode::USAX, + 2092 => Opcode::USUB16, + 2093 => Opcode::USUB8, + 2094 => Opcode::UXTAB, + 2095 => Opcode::UXTAB16, + 2096 => Opcode::UXTAH, + 2097 => Opcode::UXTB, + 2098 => Opcode::UXTB16, + 2099 => Opcode::UXTH, + 2100 => Opcode::VABALsv2i64, + 2101 => Opcode::VABALsv4i32, + 2102 => Opcode::VABALsv8i16, + 2103 => Opcode::VABALuv2i64, + 2104 => Opcode::VABALuv4i32, + 2105 => Opcode::VABALuv8i16, + 2106 => Opcode::VABAsv16i8, + 2107 => Opcode::VABAsv2i32, + 2108 => Opcode::VABAsv4i16, + 2109 => Opcode::VABAsv4i32, + 2110 => Opcode::VABAsv8i16, + 2111 => Opcode::VABAsv8i8, + 2112 => Opcode::VABAuv16i8, + 2113 => Opcode::VABAuv2i32, + 2114 => Opcode::VABAuv4i16, + 2115 => Opcode::VABAuv4i32, + 2116 => Opcode::VABAuv8i16, + 2117 => Opcode::VABAuv8i8, + 2118 => Opcode::VABDLsv2i64, + 2119 => Opcode::VABDLsv4i32, + 2120 => Opcode::VABDLsv8i16, + 2121 => Opcode::VABDLuv2i64, + 2122 => Opcode::VABDLuv4i32, + 2123 => Opcode::VABDLuv8i16, + 2124 => Opcode::VABDfd, + 2125 => Opcode::VABDfq, + 2126 => Opcode::VABDhd, + 2127 => Opcode::VABDhq, + 2128 => Opcode::VABDsv16i8, + 2129 => Opcode::VABDsv2i32, + 2130 => Opcode::VABDsv4i16, + 2131 => Opcode::VABDsv4i32, + 2132 => Opcode::VABDsv8i16, + 2133 => Opcode::VABDsv8i8, + 2134 => Opcode::VABDuv16i8, + 2135 => Opcode::VABDuv2i32, + 2136 => Opcode::VABDuv4i16, + 2137 => Opcode::VABDuv4i32, + 2138 => Opcode::VABDuv8i16, + 2139 => Opcode::VABDuv8i8, + 2140 => Opcode::VABSD, + 2141 => Opcode::VABSH, + 2142 => Opcode::VABSS, + 2143 => Opcode::VABSfd, + 2144 => Opcode::VABSfq, + 2145 => Opcode::VABShd, + 2146 => Opcode::VABShq, + 2147 => Opcode::VABSv16i8, + 2148 => Opcode::VABSv2i32, + 2149 => Opcode::VABSv4i16, + 2150 => Opcode::VABSv4i32, + 2151 => Opcode::VABSv8i16, + 2152 => Opcode::VABSv8i8, + 2153 => Opcode::VACGEfd, + 2154 => Opcode::VACGEfq, + 2155 => Opcode::VACGEhd, + 2156 => Opcode::VACGEhq, + 2157 => Opcode::VACGTfd, + 2158 => Opcode::VACGTfq, + 2159 => Opcode::VACGThd, + 2160 => Opcode::VACGThq, + 2161 => Opcode::VADDD, + 2162 => Opcode::VADDH, + 2163 => Opcode::VADDHNv2i32, + 2164 => Opcode::VADDHNv4i16, + 2165 => Opcode::VADDHNv8i8, + 2166 => Opcode::VADDLsv2i64, + 2167 => Opcode::VADDLsv4i32, + 2168 => Opcode::VADDLsv8i16, + 2169 => Opcode::VADDLuv2i64, + 2170 => Opcode::VADDLuv4i32, + 2171 => Opcode::VADDLuv8i16, + 2172 => Opcode::VADDS, + 2173 => Opcode::VADDWsv2i64, + 2174 => Opcode::VADDWsv4i32, + 2175 => Opcode::VADDWsv8i16, + 2176 => Opcode::VADDWuv2i64, + 2177 => Opcode::VADDWuv4i32, + 2178 => Opcode::VADDWuv8i16, + 2179 => Opcode::VADDfd, + 2180 => Opcode::VADDfq, + 2181 => Opcode::VADDhd, + 2182 => Opcode::VADDhq, + 2183 => Opcode::VADDv16i8, + 2184 => Opcode::VADDv1i64, + 2185 => Opcode::VADDv2i32, + 2186 => Opcode::VADDv2i64, + 2187 => Opcode::VADDv4i16, + 2188 => Opcode::VADDv4i32, + 2189 => Opcode::VADDv8i16, + 2190 => Opcode::VADDv8i8, + 2191 => Opcode::VANDd, + 2192 => Opcode::VANDq, + 2193 => Opcode::VBF16MALBQ, + 2194 => Opcode::VBF16MALBQI, + 2195 => Opcode::VBF16MALTQ, + 2196 => Opcode::VBF16MALTQI, + 2197 => Opcode::VBICd, + 2198 => Opcode::VBICiv2i32, + 2199 => Opcode::VBICiv4i16, + 2200 => Opcode::VBICiv4i32, + 2201 => Opcode::VBICiv8i16, + 2202 => Opcode::VBICq, + 2203 => Opcode::VBIFd, + 2204 => Opcode::VBIFq, + 2205 => Opcode::VBITd, + 2206 => Opcode::VBITq, + 2207 => Opcode::VBSLd, + 2208 => Opcode::VBSLq, + 2209 => Opcode::VBSPd, + 2210 => Opcode::VBSPq, + 2211 => Opcode::VCADDv2f32, + 2212 => Opcode::VCADDv4f16, + 2213 => Opcode::VCADDv4f32, + 2214 => Opcode::VCADDv8f16, + 2215 => Opcode::VCEQfd, + 2216 => Opcode::VCEQfq, + 2217 => Opcode::VCEQhd, + 2218 => Opcode::VCEQhq, + 2219 => Opcode::VCEQv16i8, + 2220 => Opcode::VCEQv2i32, + 2221 => Opcode::VCEQv4i16, + 2222 => Opcode::VCEQv4i32, + 2223 => Opcode::VCEQv8i16, + 2224 => Opcode::VCEQv8i8, + 2225 => Opcode::VCEQzv16i8, + 2226 => Opcode::VCEQzv2f32, + 2227 => Opcode::VCEQzv2i32, + 2228 => Opcode::VCEQzv4f16, + 2229 => Opcode::VCEQzv4f32, + 2230 => Opcode::VCEQzv4i16, + 2231 => Opcode::VCEQzv4i32, + 2232 => Opcode::VCEQzv8f16, + 2233 => Opcode::VCEQzv8i16, + 2234 => Opcode::VCEQzv8i8, + 2235 => Opcode::VCGEfd, + 2236 => Opcode::VCGEfq, + 2237 => Opcode::VCGEhd, + 2238 => Opcode::VCGEhq, + 2239 => Opcode::VCGEsv16i8, + 2240 => Opcode::VCGEsv2i32, + 2241 => Opcode::VCGEsv4i16, + 2242 => Opcode::VCGEsv4i32, + 2243 => Opcode::VCGEsv8i16, + 2244 => Opcode::VCGEsv8i8, + 2245 => Opcode::VCGEuv16i8, + 2246 => Opcode::VCGEuv2i32, + 2247 => Opcode::VCGEuv4i16, + 2248 => Opcode::VCGEuv4i32, + 2249 => Opcode::VCGEuv8i16, + 2250 => Opcode::VCGEuv8i8, + 2251 => Opcode::VCGEzv16i8, + 2252 => Opcode::VCGEzv2f32, + 2253 => Opcode::VCGEzv2i32, + 2254 => Opcode::VCGEzv4f16, + 2255 => Opcode::VCGEzv4f32, + 2256 => Opcode::VCGEzv4i16, + 2257 => Opcode::VCGEzv4i32, + 2258 => Opcode::VCGEzv8f16, + 2259 => Opcode::VCGEzv8i16, + 2260 => Opcode::VCGEzv8i8, + 2261 => Opcode::VCGTfd, + 2262 => Opcode::VCGTfq, + 2263 => Opcode::VCGThd, + 2264 => Opcode::VCGThq, + 2265 => Opcode::VCGTsv16i8, + 2266 => Opcode::VCGTsv2i32, + 2267 => Opcode::VCGTsv4i16, + 2268 => Opcode::VCGTsv4i32, + 2269 => Opcode::VCGTsv8i16, + 2270 => Opcode::VCGTsv8i8, + 2271 => Opcode::VCGTuv16i8, + 2272 => Opcode::VCGTuv2i32, + 2273 => Opcode::VCGTuv4i16, + 2274 => Opcode::VCGTuv4i32, + 2275 => Opcode::VCGTuv8i16, + 2276 => Opcode::VCGTuv8i8, + 2277 => Opcode::VCGTzv16i8, + 2278 => Opcode::VCGTzv2f32, + 2279 => Opcode::VCGTzv2i32, + 2280 => Opcode::VCGTzv4f16, + 2281 => Opcode::VCGTzv4f32, + 2282 => Opcode::VCGTzv4i16, + 2283 => Opcode::VCGTzv4i32, + 2284 => Opcode::VCGTzv8f16, + 2285 => Opcode::VCGTzv8i16, + 2286 => Opcode::VCGTzv8i8, + 2287 => Opcode::VCLEzv16i8, + 2288 => Opcode::VCLEzv2f32, + 2289 => Opcode::VCLEzv2i32, + 2290 => Opcode::VCLEzv4f16, + 2291 => Opcode::VCLEzv4f32, + 2292 => Opcode::VCLEzv4i16, + 2293 => Opcode::VCLEzv4i32, + 2294 => Opcode::VCLEzv8f16, + 2295 => Opcode::VCLEzv8i16, + 2296 => Opcode::VCLEzv8i8, + 2297 => Opcode::VCLSv16i8, + 2298 => Opcode::VCLSv2i32, + 2299 => Opcode::VCLSv4i16, + 2300 => Opcode::VCLSv4i32, + 2301 => Opcode::VCLSv8i16, + 2302 => Opcode::VCLSv8i8, + 2303 => Opcode::VCLTzv16i8, + 2304 => Opcode::VCLTzv2f32, + 2305 => Opcode::VCLTzv2i32, + 2306 => Opcode::VCLTzv4f16, + 2307 => Opcode::VCLTzv4f32, + 2308 => Opcode::VCLTzv4i16, + 2309 => Opcode::VCLTzv4i32, + 2310 => Opcode::VCLTzv8f16, + 2311 => Opcode::VCLTzv8i16, + 2312 => Opcode::VCLTzv8i8, + 2313 => Opcode::VCLZv16i8, + 2314 => Opcode::VCLZv2i32, + 2315 => Opcode::VCLZv4i16, + 2316 => Opcode::VCLZv4i32, + 2317 => Opcode::VCLZv8i16, + 2318 => Opcode::VCLZv8i8, + 2319 => Opcode::VCMLAv2f32, + 2320 => Opcode::VCMLAv2f32_indexed, + 2321 => Opcode::VCMLAv4f16, + 2322 => Opcode::VCMLAv4f16_indexed, + 2323 => Opcode::VCMLAv4f32, + 2324 => Opcode::VCMLAv4f32_indexed, + 2325 => Opcode::VCMLAv8f16, + 2326 => Opcode::VCMLAv8f16_indexed, + 2327 => Opcode::VCMPD, + 2328 => Opcode::VCMPED, + 2329 => Opcode::VCMPEH, + 2330 => Opcode::VCMPES, + 2331 => Opcode::VCMPEZD, + 2332 => Opcode::VCMPEZH, + 2333 => Opcode::VCMPEZS, + 2334 => Opcode::VCMPH, + 2335 => Opcode::VCMPS, + 2336 => Opcode::VCMPZD, + 2337 => Opcode::VCMPZH, + 2338 => Opcode::VCMPZS, + 2339 => Opcode::VCNTd, + 2340 => Opcode::VCNTq, + 2341 => Opcode::VCVTANSDf, + 2342 => Opcode::VCVTANSDh, + 2343 => Opcode::VCVTANSQf, + 2344 => Opcode::VCVTANSQh, + 2345 => Opcode::VCVTANUDf, + 2346 => Opcode::VCVTANUDh, + 2347 => Opcode::VCVTANUQf, + 2348 => Opcode::VCVTANUQh, + 2349 => Opcode::VCVTASD, + 2350 => Opcode::VCVTASH, + 2351 => Opcode::VCVTASS, + 2352 => Opcode::VCVTAUD, + 2353 => Opcode::VCVTAUH, + 2354 => Opcode::VCVTAUS, + 2355 => Opcode::VCVTBDH, + 2356 => Opcode::VCVTBHD, + 2357 => Opcode::VCVTBHS, + 2358 => Opcode::VCVTBSH, + 2359 => Opcode::VCVTDS, + 2360 => Opcode::VCVTMNSDf, + 2361 => Opcode::VCVTMNSDh, + 2362 => Opcode::VCVTMNSQf, + 2363 => Opcode::VCVTMNSQh, + 2364 => Opcode::VCVTMNUDf, + 2365 => Opcode::VCVTMNUDh, + 2366 => Opcode::VCVTMNUQf, + 2367 => Opcode::VCVTMNUQh, + 2368 => Opcode::VCVTMSD, + 2369 => Opcode::VCVTMSH, + 2370 => Opcode::VCVTMSS, + 2371 => Opcode::VCVTMUD, + 2372 => Opcode::VCVTMUH, + 2373 => Opcode::VCVTMUS, + 2374 => Opcode::VCVTNNSDf, + 2375 => Opcode::VCVTNNSDh, + 2376 => Opcode::VCVTNNSQf, + 2377 => Opcode::VCVTNNSQh, + 2378 => Opcode::VCVTNNUDf, + 2379 => Opcode::VCVTNNUDh, + 2380 => Opcode::VCVTNNUQf, + 2381 => Opcode::VCVTNNUQh, + 2382 => Opcode::VCVTNSD, + 2383 => Opcode::VCVTNSH, + 2384 => Opcode::VCVTNSS, + 2385 => Opcode::VCVTNUD, + 2386 => Opcode::VCVTNUH, + 2387 => Opcode::VCVTNUS, + 2388 => Opcode::VCVTPNSDf, + 2389 => Opcode::VCVTPNSDh, + 2390 => Opcode::VCVTPNSQf, + 2391 => Opcode::VCVTPNSQh, + 2392 => Opcode::VCVTPNUDf, + 2393 => Opcode::VCVTPNUDh, + 2394 => Opcode::VCVTPNUQf, + 2395 => Opcode::VCVTPNUQh, + 2396 => Opcode::VCVTPSD, + 2397 => Opcode::VCVTPSH, + 2398 => Opcode::VCVTPSS, + 2399 => Opcode::VCVTPUD, + 2400 => Opcode::VCVTPUH, + 2401 => Opcode::VCVTPUS, + 2402 => Opcode::VCVTSD, + 2403 => Opcode::VCVTTDH, + 2404 => Opcode::VCVTTHD, + 2405 => Opcode::VCVTTHS, + 2406 => Opcode::VCVTTSH, + 2407 => Opcode::VCVTf2h, + 2408 => Opcode::VCVTf2sd, + 2409 => Opcode::VCVTf2sq, + 2410 => Opcode::VCVTf2ud, + 2411 => Opcode::VCVTf2uq, + 2412 => Opcode::VCVTf2xsd, + 2413 => Opcode::VCVTf2xsq, + 2414 => Opcode::VCVTf2xud, + 2415 => Opcode::VCVTf2xuq, + 2416 => Opcode::VCVTh2f, + 2417 => Opcode::VCVTh2sd, + 2418 => Opcode::VCVTh2sq, + 2419 => Opcode::VCVTh2ud, + 2420 => Opcode::VCVTh2uq, + 2421 => Opcode::VCVTh2xsd, + 2422 => Opcode::VCVTh2xsq, + 2423 => Opcode::VCVTh2xud, + 2424 => Opcode::VCVTh2xuq, + 2425 => Opcode::VCVTs2fd, + 2426 => Opcode::VCVTs2fq, + 2427 => Opcode::VCVTs2hd, + 2428 => Opcode::VCVTs2hq, + 2429 => Opcode::VCVTu2fd, + 2430 => Opcode::VCVTu2fq, + 2431 => Opcode::VCVTu2hd, + 2432 => Opcode::VCVTu2hq, + 2433 => Opcode::VCVTxs2fd, + 2434 => Opcode::VCVTxs2fq, + 2435 => Opcode::VCVTxs2hd, + 2436 => Opcode::VCVTxs2hq, + 2437 => Opcode::VCVTxu2fd, + 2438 => Opcode::VCVTxu2fq, + 2439 => Opcode::VCVTxu2hd, + 2440 => Opcode::VCVTxu2hq, + 2441 => Opcode::VDIVD, + 2442 => Opcode::VDIVH, + 2443 => Opcode::VDIVS, + 2444 => Opcode::VDUP16d, + 2445 => Opcode::VDUP16q, + 2446 => Opcode::VDUP32d, + 2447 => Opcode::VDUP32q, + 2448 => Opcode::VDUP8d, + 2449 => Opcode::VDUP8q, + 2450 => Opcode::VDUPLN16d, + 2451 => Opcode::VDUPLN16q, + 2452 => Opcode::VDUPLN32d, + 2453 => Opcode::VDUPLN32q, + 2454 => Opcode::VDUPLN8d, + 2455 => Opcode::VDUPLN8q, + 2456 => Opcode::VEORd, + 2457 => Opcode::VEORq, + 2458 => Opcode::VEXTd16, + 2459 => Opcode::VEXTd32, + 2460 => Opcode::VEXTd8, + 2461 => Opcode::VEXTq16, + 2462 => Opcode::VEXTq32, + 2463 => Opcode::VEXTq64, + 2464 => Opcode::VEXTq8, + 2465 => Opcode::VFMAD, + 2466 => Opcode::VFMAH, + 2467 => Opcode::VFMALD, + 2468 => Opcode::VFMALDI, + 2469 => Opcode::VFMALQ, + 2470 => Opcode::VFMALQI, + 2471 => Opcode::VFMAS, + 2472 => Opcode::VFMAfd, + 2473 => Opcode::VFMAfq, + 2474 => Opcode::VFMAhd, + 2475 => Opcode::VFMAhq, + 2476 => Opcode::VFMSD, + 2477 => Opcode::VFMSH, + 2478 => Opcode::VFMSLD, + 2479 => Opcode::VFMSLDI, + 2480 => Opcode::VFMSLQ, + 2481 => Opcode::VFMSLQI, + 2482 => Opcode::VFMSS, + 2483 => Opcode::VFMSfd, + 2484 => Opcode::VFMSfq, + 2485 => Opcode::VFMShd, + 2486 => Opcode::VFMShq, + 2487 => Opcode::VFNMAD, + 2488 => Opcode::VFNMAH, + 2489 => Opcode::VFNMAS, + 2490 => Opcode::VFNMSD, + 2491 => Opcode::VFNMSH, + 2492 => Opcode::VFNMSS, + 2493 => Opcode::VFP_VMAXNMD, + 2494 => Opcode::VFP_VMAXNMH, + 2495 => Opcode::VFP_VMAXNMS, + 2496 => Opcode::VFP_VMINNMD, + 2497 => Opcode::VFP_VMINNMH, + 2498 => Opcode::VFP_VMINNMS, + 2499 => Opcode::VGETLNi32, + 2500 => Opcode::VGETLNs16, + 2501 => Opcode::VGETLNs8, + 2502 => Opcode::VGETLNu16, + 2503 => Opcode::VGETLNu8, + 2504 => Opcode::VHADDsv16i8, + 2505 => Opcode::VHADDsv2i32, + 2506 => Opcode::VHADDsv4i16, + 2507 => Opcode::VHADDsv4i32, + 2508 => Opcode::VHADDsv8i16, + 2509 => Opcode::VHADDsv8i8, + 2510 => Opcode::VHADDuv16i8, + 2511 => Opcode::VHADDuv2i32, + 2512 => Opcode::VHADDuv4i16, + 2513 => Opcode::VHADDuv4i32, + 2514 => Opcode::VHADDuv8i16, + 2515 => Opcode::VHADDuv8i8, + 2516 => Opcode::VHSUBsv16i8, + 2517 => Opcode::VHSUBsv2i32, + 2518 => Opcode::VHSUBsv4i16, + 2519 => Opcode::VHSUBsv4i32, + 2520 => Opcode::VHSUBsv8i16, + 2521 => Opcode::VHSUBsv8i8, + 2522 => Opcode::VHSUBuv16i8, + 2523 => Opcode::VHSUBuv2i32, + 2524 => Opcode::VHSUBuv4i16, + 2525 => Opcode::VHSUBuv4i32, + 2526 => Opcode::VHSUBuv8i16, + 2527 => Opcode::VHSUBuv8i8, + 2528 => Opcode::VINSH, + 2529 => Opcode::VJCVT, + 2530 => Opcode::VLD1DUPd16, + 2531 => Opcode::VLD1DUPd16wb_fixed, + 2532 => Opcode::VLD1DUPd16wb_register, + 2533 => Opcode::VLD1DUPd32, + 2534 => Opcode::VLD1DUPd32wb_fixed, + 2535 => Opcode::VLD1DUPd32wb_register, + 2536 => Opcode::VLD1DUPd8, + 2537 => Opcode::VLD1DUPd8wb_fixed, + 2538 => Opcode::VLD1DUPd8wb_register, + 2539 => Opcode::VLD1DUPq16, + 2540 => Opcode::VLD1DUPq16wb_fixed, + 2541 => Opcode::VLD1DUPq16wb_register, + 2542 => Opcode::VLD1DUPq32, + 2543 => Opcode::VLD1DUPq32wb_fixed, + 2544 => Opcode::VLD1DUPq32wb_register, + 2545 => Opcode::VLD1DUPq8, + 2546 => Opcode::VLD1DUPq8wb_fixed, + 2547 => Opcode::VLD1DUPq8wb_register, + 2548 => Opcode::VLD1LNd16, + 2549 => Opcode::VLD1LNd16_UPD, + 2550 => Opcode::VLD1LNd32, + 2551 => Opcode::VLD1LNd32_UPD, + 2552 => Opcode::VLD1LNd8, + 2553 => Opcode::VLD1LNd8_UPD, + 2554 => Opcode::VLD1LNq16Pseudo, + 2555 => Opcode::VLD1LNq16Pseudo_UPD, + 2556 => Opcode::VLD1LNq32Pseudo, + 2557 => Opcode::VLD1LNq32Pseudo_UPD, + 2558 => Opcode::VLD1LNq8Pseudo, + 2559 => Opcode::VLD1LNq8Pseudo_UPD, + 2560 => Opcode::VLD1d16, + 2561 => Opcode::VLD1d16Q, + 2562 => Opcode::VLD1d16QPseudo, + 2563 => Opcode::VLD1d16QPseudoWB_fixed, + 2564 => Opcode::VLD1d16QPseudoWB_register, + 2565 => Opcode::VLD1d16Qwb_fixed, + 2566 => Opcode::VLD1d16Qwb_register, + 2567 => Opcode::VLD1d16T, + 2568 => Opcode::VLD1d16TPseudo, + 2569 => Opcode::VLD1d16TPseudoWB_fixed, + 2570 => Opcode::VLD1d16TPseudoWB_register, + 2571 => Opcode::VLD1d16Twb_fixed, + 2572 => Opcode::VLD1d16Twb_register, + 2573 => Opcode::VLD1d16wb_fixed, + 2574 => Opcode::VLD1d16wb_register, + 2575 => Opcode::VLD1d32, + 2576 => Opcode::VLD1d32Q, + 2577 => Opcode::VLD1d32QPseudo, + 2578 => Opcode::VLD1d32QPseudoWB_fixed, + 2579 => Opcode::VLD1d32QPseudoWB_register, + 2580 => Opcode::VLD1d32Qwb_fixed, + 2581 => Opcode::VLD1d32Qwb_register, + 2582 => Opcode::VLD1d32T, + 2583 => Opcode::VLD1d32TPseudo, + 2584 => Opcode::VLD1d32TPseudoWB_fixed, + 2585 => Opcode::VLD1d32TPseudoWB_register, + 2586 => Opcode::VLD1d32Twb_fixed, + 2587 => Opcode::VLD1d32Twb_register, + 2588 => Opcode::VLD1d32wb_fixed, + 2589 => Opcode::VLD1d32wb_register, + 2590 => Opcode::VLD1d64, + 2591 => Opcode::VLD1d64Q, + 2592 => Opcode::VLD1d64QPseudo, + 2593 => Opcode::VLD1d64QPseudoWB_fixed, + 2594 => Opcode::VLD1d64QPseudoWB_register, + 2595 => Opcode::VLD1d64Qwb_fixed, + 2596 => Opcode::VLD1d64Qwb_register, + 2597 => Opcode::VLD1d64T, + 2598 => Opcode::VLD1d64TPseudo, + 2599 => Opcode::VLD1d64TPseudoWB_fixed, + 2600 => Opcode::VLD1d64TPseudoWB_register, + 2601 => Opcode::VLD1d64Twb_fixed, + 2602 => Opcode::VLD1d64Twb_register, + 2603 => Opcode::VLD1d64wb_fixed, + 2604 => Opcode::VLD1d64wb_register, + 2605 => Opcode::VLD1d8, + 2606 => Opcode::VLD1d8Q, + 2607 => Opcode::VLD1d8QPseudo, + 2608 => Opcode::VLD1d8QPseudoWB_fixed, + 2609 => Opcode::VLD1d8QPseudoWB_register, + 2610 => Opcode::VLD1d8Qwb_fixed, + 2611 => Opcode::VLD1d8Qwb_register, + 2612 => Opcode::VLD1d8T, + 2613 => Opcode::VLD1d8TPseudo, + 2614 => Opcode::VLD1d8TPseudoWB_fixed, + 2615 => Opcode::VLD1d8TPseudoWB_register, + 2616 => Opcode::VLD1d8Twb_fixed, + 2617 => Opcode::VLD1d8Twb_register, + 2618 => Opcode::VLD1d8wb_fixed, + 2619 => Opcode::VLD1d8wb_register, + 2620 => Opcode::VLD1q16, + 2621 => Opcode::VLD1q16HighQPseudo, + 2622 => Opcode::VLD1q16HighQPseudo_UPD, + 2623 => Opcode::VLD1q16HighTPseudo, + 2624 => Opcode::VLD1q16HighTPseudo_UPD, + 2625 => Opcode::VLD1q16LowQPseudo_UPD, + 2626 => Opcode::VLD1q16LowTPseudo_UPD, + 2627 => Opcode::VLD1q16wb_fixed, + 2628 => Opcode::VLD1q16wb_register, + 2629 => Opcode::VLD1q32, + 2630 => Opcode::VLD1q32HighQPseudo, + 2631 => Opcode::VLD1q32HighQPseudo_UPD, + 2632 => Opcode::VLD1q32HighTPseudo, + 2633 => Opcode::VLD1q32HighTPseudo_UPD, + 2634 => Opcode::VLD1q32LowQPseudo_UPD, + 2635 => Opcode::VLD1q32LowTPseudo_UPD, + 2636 => Opcode::VLD1q32wb_fixed, + 2637 => Opcode::VLD1q32wb_register, + 2638 => Opcode::VLD1q64, + 2639 => Opcode::VLD1q64HighQPseudo, + 2640 => Opcode::VLD1q64HighQPseudo_UPD, + 2641 => Opcode::VLD1q64HighTPseudo, + 2642 => Opcode::VLD1q64HighTPseudo_UPD, + 2643 => Opcode::VLD1q64LowQPseudo_UPD, + 2644 => Opcode::VLD1q64LowTPseudo_UPD, + 2645 => Opcode::VLD1q64wb_fixed, + 2646 => Opcode::VLD1q64wb_register, + 2647 => Opcode::VLD1q8, + 2648 => Opcode::VLD1q8HighQPseudo, + 2649 => Opcode::VLD1q8HighQPseudo_UPD, + 2650 => Opcode::VLD1q8HighTPseudo, + 2651 => Opcode::VLD1q8HighTPseudo_UPD, + 2652 => Opcode::VLD1q8LowQPseudo_UPD, + 2653 => Opcode::VLD1q8LowTPseudo_UPD, + 2654 => Opcode::VLD1q8wb_fixed, + 2655 => Opcode::VLD1q8wb_register, + 2656 => Opcode::VLD2DUPd16, + 2657 => Opcode::VLD2DUPd16wb_fixed, + 2658 => Opcode::VLD2DUPd16wb_register, + 2659 => Opcode::VLD2DUPd16x2, + 2660 => Opcode::VLD2DUPd16x2wb_fixed, + 2661 => Opcode::VLD2DUPd16x2wb_register, + 2662 => Opcode::VLD2DUPd32, + 2663 => Opcode::VLD2DUPd32wb_fixed, + 2664 => Opcode::VLD2DUPd32wb_register, + 2665 => Opcode::VLD2DUPd32x2, + 2666 => Opcode::VLD2DUPd32x2wb_fixed, + 2667 => Opcode::VLD2DUPd32x2wb_register, + 2668 => Opcode::VLD2DUPd8, + 2669 => Opcode::VLD2DUPd8wb_fixed, + 2670 => Opcode::VLD2DUPd8wb_register, + 2671 => Opcode::VLD2DUPd8x2, + 2672 => Opcode::VLD2DUPd8x2wb_fixed, + 2673 => Opcode::VLD2DUPd8x2wb_register, + 2674 => Opcode::VLD2DUPq16EvenPseudo, + 2675 => Opcode::VLD2DUPq16OddPseudo, + 2676 => Opcode::VLD2DUPq16OddPseudoWB_fixed, + 2677 => Opcode::VLD2DUPq16OddPseudoWB_register, + 2678 => Opcode::VLD2DUPq32EvenPseudo, + 2679 => Opcode::VLD2DUPq32OddPseudo, + 2680 => Opcode::VLD2DUPq32OddPseudoWB_fixed, + 2681 => Opcode::VLD2DUPq32OddPseudoWB_register, + 2682 => Opcode::VLD2DUPq8EvenPseudo, + 2683 => Opcode::VLD2DUPq8OddPseudo, + 2684 => Opcode::VLD2DUPq8OddPseudoWB_fixed, + 2685 => Opcode::VLD2DUPq8OddPseudoWB_register, + 2686 => Opcode::VLD2LNd16, + 2687 => Opcode::VLD2LNd16Pseudo, + 2688 => Opcode::VLD2LNd16Pseudo_UPD, + 2689 => Opcode::VLD2LNd16_UPD, + 2690 => Opcode::VLD2LNd32, + 2691 => Opcode::VLD2LNd32Pseudo, + 2692 => Opcode::VLD2LNd32Pseudo_UPD, + 2693 => Opcode::VLD2LNd32_UPD, + 2694 => Opcode::VLD2LNd8, + 2695 => Opcode::VLD2LNd8Pseudo, + 2696 => Opcode::VLD2LNd8Pseudo_UPD, + 2697 => Opcode::VLD2LNd8_UPD, + 2698 => Opcode::VLD2LNq16, + 2699 => Opcode::VLD2LNq16Pseudo, + 2700 => Opcode::VLD2LNq16Pseudo_UPD, + 2701 => Opcode::VLD2LNq16_UPD, + 2702 => Opcode::VLD2LNq32, + 2703 => Opcode::VLD2LNq32Pseudo, + 2704 => Opcode::VLD2LNq32Pseudo_UPD, + 2705 => Opcode::VLD2LNq32_UPD, + 2706 => Opcode::VLD2b16, + 2707 => Opcode::VLD2b16wb_fixed, + 2708 => Opcode::VLD2b16wb_register, + 2709 => Opcode::VLD2b32, + 2710 => Opcode::VLD2b32wb_fixed, + 2711 => Opcode::VLD2b32wb_register, + 2712 => Opcode::VLD2b8, + 2713 => Opcode::VLD2b8wb_fixed, + 2714 => Opcode::VLD2b8wb_register, + 2715 => Opcode::VLD2d16, + 2716 => Opcode::VLD2d16wb_fixed, + 2717 => Opcode::VLD2d16wb_register, + 2718 => Opcode::VLD2d32, + 2719 => Opcode::VLD2d32wb_fixed, + 2720 => Opcode::VLD2d32wb_register, + 2721 => Opcode::VLD2d8, + 2722 => Opcode::VLD2d8wb_fixed, + 2723 => Opcode::VLD2d8wb_register, + 2724 => Opcode::VLD2q16, + 2725 => Opcode::VLD2q16Pseudo, + 2726 => Opcode::VLD2q16PseudoWB_fixed, + 2727 => Opcode::VLD2q16PseudoWB_register, + 2728 => Opcode::VLD2q16wb_fixed, + 2729 => Opcode::VLD2q16wb_register, + 2730 => Opcode::VLD2q32, + 2731 => Opcode::VLD2q32Pseudo, + 2732 => Opcode::VLD2q32PseudoWB_fixed, + 2733 => Opcode::VLD2q32PseudoWB_register, + 2734 => Opcode::VLD2q32wb_fixed, + 2735 => Opcode::VLD2q32wb_register, + 2736 => Opcode::VLD2q8, + 2737 => Opcode::VLD2q8Pseudo, + 2738 => Opcode::VLD2q8PseudoWB_fixed, + 2739 => Opcode::VLD2q8PseudoWB_register, + 2740 => Opcode::VLD2q8wb_fixed, + 2741 => Opcode::VLD2q8wb_register, + 2742 => Opcode::VLD3DUPd16, + 2743 => Opcode::VLD3DUPd16Pseudo, + 2744 => Opcode::VLD3DUPd16Pseudo_UPD, + 2745 => Opcode::VLD3DUPd16_UPD, + 2746 => Opcode::VLD3DUPd32, + 2747 => Opcode::VLD3DUPd32Pseudo, + 2748 => Opcode::VLD3DUPd32Pseudo_UPD, + 2749 => Opcode::VLD3DUPd32_UPD, + 2750 => Opcode::VLD3DUPd8, + 2751 => Opcode::VLD3DUPd8Pseudo, + 2752 => Opcode::VLD3DUPd8Pseudo_UPD, + 2753 => Opcode::VLD3DUPd8_UPD, + 2754 => Opcode::VLD3DUPq16, + 2755 => Opcode::VLD3DUPq16EvenPseudo, + 2756 => Opcode::VLD3DUPq16OddPseudo, + 2757 => Opcode::VLD3DUPq16OddPseudo_UPD, + 2758 => Opcode::VLD3DUPq16_UPD, + 2759 => Opcode::VLD3DUPq32, + 2760 => Opcode::VLD3DUPq32EvenPseudo, + 2761 => Opcode::VLD3DUPq32OddPseudo, + 2762 => Opcode::VLD3DUPq32OddPseudo_UPD, + 2763 => Opcode::VLD3DUPq32_UPD, + 2764 => Opcode::VLD3DUPq8, + 2765 => Opcode::VLD3DUPq8EvenPseudo, + 2766 => Opcode::VLD3DUPq8OddPseudo, + 2767 => Opcode::VLD3DUPq8OddPseudo_UPD, + 2768 => Opcode::VLD3DUPq8_UPD, + 2769 => Opcode::VLD3LNd16, + 2770 => Opcode::VLD3LNd16Pseudo, + 2771 => Opcode::VLD3LNd16Pseudo_UPD, + 2772 => Opcode::VLD3LNd16_UPD, + 2773 => Opcode::VLD3LNd32, + 2774 => Opcode::VLD3LNd32Pseudo, + 2775 => Opcode::VLD3LNd32Pseudo_UPD, + 2776 => Opcode::VLD3LNd32_UPD, + 2777 => Opcode::VLD3LNd8, + 2778 => Opcode::VLD3LNd8Pseudo, + 2779 => Opcode::VLD3LNd8Pseudo_UPD, + 2780 => Opcode::VLD3LNd8_UPD, + 2781 => Opcode::VLD3LNq16, + 2782 => Opcode::VLD3LNq16Pseudo, + 2783 => Opcode::VLD3LNq16Pseudo_UPD, + 2784 => Opcode::VLD3LNq16_UPD, + 2785 => Opcode::VLD3LNq32, + 2786 => Opcode::VLD3LNq32Pseudo, + 2787 => Opcode::VLD3LNq32Pseudo_UPD, + 2788 => Opcode::VLD3LNq32_UPD, + 2789 => Opcode::VLD3d16, + 2790 => Opcode::VLD3d16Pseudo, + 2791 => Opcode::VLD3d16Pseudo_UPD, + 2792 => Opcode::VLD3d16_UPD, + 2793 => Opcode::VLD3d32, + 2794 => Opcode::VLD3d32Pseudo, + 2795 => Opcode::VLD3d32Pseudo_UPD, + 2796 => Opcode::VLD3d32_UPD, + 2797 => Opcode::VLD3d8, + 2798 => Opcode::VLD3d8Pseudo, + 2799 => Opcode::VLD3d8Pseudo_UPD, + 2800 => Opcode::VLD3d8_UPD, + 2801 => Opcode::VLD3q16, + 2802 => Opcode::VLD3q16Pseudo_UPD, + 2803 => Opcode::VLD3q16_UPD, + 2804 => Opcode::VLD3q16oddPseudo, + 2805 => Opcode::VLD3q16oddPseudo_UPD, + 2806 => Opcode::VLD3q32, + 2807 => Opcode::VLD3q32Pseudo_UPD, + 2808 => Opcode::VLD3q32_UPD, + 2809 => Opcode::VLD3q32oddPseudo, + 2810 => Opcode::VLD3q32oddPseudo_UPD, + 2811 => Opcode::VLD3q8, + 2812 => Opcode::VLD3q8Pseudo_UPD, + 2813 => Opcode::VLD3q8_UPD, + 2814 => Opcode::VLD3q8oddPseudo, + 2815 => Opcode::VLD3q8oddPseudo_UPD, + 2816 => Opcode::VLD4DUPd16, + 2817 => Opcode::VLD4DUPd16Pseudo, + 2818 => Opcode::VLD4DUPd16Pseudo_UPD, + 2819 => Opcode::VLD4DUPd16_UPD, + 2820 => Opcode::VLD4DUPd32, + 2821 => Opcode::VLD4DUPd32Pseudo, + 2822 => Opcode::VLD4DUPd32Pseudo_UPD, + 2823 => Opcode::VLD4DUPd32_UPD, + 2824 => Opcode::VLD4DUPd8, + 2825 => Opcode::VLD4DUPd8Pseudo, + 2826 => Opcode::VLD4DUPd8Pseudo_UPD, + 2827 => Opcode::VLD4DUPd8_UPD, + 2828 => Opcode::VLD4DUPq16, + 2829 => Opcode::VLD4DUPq16EvenPseudo, + 2830 => Opcode::VLD4DUPq16OddPseudo, + 2831 => Opcode::VLD4DUPq16OddPseudo_UPD, + 2832 => Opcode::VLD4DUPq16_UPD, + 2833 => Opcode::VLD4DUPq32, + 2834 => Opcode::VLD4DUPq32EvenPseudo, + 2835 => Opcode::VLD4DUPq32OddPseudo, + 2836 => Opcode::VLD4DUPq32OddPseudo_UPD, + 2837 => Opcode::VLD4DUPq32_UPD, + 2838 => Opcode::VLD4DUPq8, + 2839 => Opcode::VLD4DUPq8EvenPseudo, + 2840 => Opcode::VLD4DUPq8OddPseudo, + 2841 => Opcode::VLD4DUPq8OddPseudo_UPD, + 2842 => Opcode::VLD4DUPq8_UPD, + 2843 => Opcode::VLD4LNd16, + 2844 => Opcode::VLD4LNd16Pseudo, + 2845 => Opcode::VLD4LNd16Pseudo_UPD, + 2846 => Opcode::VLD4LNd16_UPD, + 2847 => Opcode::VLD4LNd32, + 2848 => Opcode::VLD4LNd32Pseudo, + 2849 => Opcode::VLD4LNd32Pseudo_UPD, + 2850 => Opcode::VLD4LNd32_UPD, + 2851 => Opcode::VLD4LNd8, + 2852 => Opcode::VLD4LNd8Pseudo, + 2853 => Opcode::VLD4LNd8Pseudo_UPD, + 2854 => Opcode::VLD4LNd8_UPD, + 2855 => Opcode::VLD4LNq16, + 2856 => Opcode::VLD4LNq16Pseudo, + 2857 => Opcode::VLD4LNq16Pseudo_UPD, + 2858 => Opcode::VLD4LNq16_UPD, + 2859 => Opcode::VLD4LNq32, + 2860 => Opcode::VLD4LNq32Pseudo, + 2861 => Opcode::VLD4LNq32Pseudo_UPD, + 2862 => Opcode::VLD4LNq32_UPD, + 2863 => Opcode::VLD4d16, + 2864 => Opcode::VLD4d16Pseudo, + 2865 => Opcode::VLD4d16Pseudo_UPD, + 2866 => Opcode::VLD4d16_UPD, + 2867 => Opcode::VLD4d32, + 2868 => Opcode::VLD4d32Pseudo, + 2869 => Opcode::VLD4d32Pseudo_UPD, + 2870 => Opcode::VLD4d32_UPD, + 2871 => Opcode::VLD4d8, + 2872 => Opcode::VLD4d8Pseudo, + 2873 => Opcode::VLD4d8Pseudo_UPD, + 2874 => Opcode::VLD4d8_UPD, + 2875 => Opcode::VLD4q16, + 2876 => Opcode::VLD4q16Pseudo_UPD, + 2877 => Opcode::VLD4q16_UPD, + 2878 => Opcode::VLD4q16oddPseudo, + 2879 => Opcode::VLD4q16oddPseudo_UPD, + 2880 => Opcode::VLD4q32, + 2881 => Opcode::VLD4q32Pseudo_UPD, + 2882 => Opcode::VLD4q32_UPD, + 2883 => Opcode::VLD4q32oddPseudo, + 2884 => Opcode::VLD4q32oddPseudo_UPD, + 2885 => Opcode::VLD4q8, + 2886 => Opcode::VLD4q8Pseudo_UPD, + 2887 => Opcode::VLD4q8_UPD, + 2888 => Opcode::VLD4q8oddPseudo, + 2889 => Opcode::VLD4q8oddPseudo_UPD, + 2890 => Opcode::VLDMDDB_UPD, + 2891 => Opcode::VLDMDIA, + 2892 => Opcode::VLDMDIA_UPD, + 2893 => Opcode::VLDMQIA, + 2894 => Opcode::VLDMSDB_UPD, + 2895 => Opcode::VLDMSIA, + 2896 => Opcode::VLDMSIA_UPD, + 2897 => Opcode::VLDRD, + 2898 => Opcode::VLDRH, + 2899 => Opcode::VLDRS, + 2900 => Opcode::VLDR_FPCXTNS_off, + 2901 => Opcode::VLDR_FPCXTNS_post, + 2902 => Opcode::VLDR_FPCXTNS_pre, + 2903 => Opcode::VLDR_FPCXTS_off, + 2904 => Opcode::VLDR_FPCXTS_post, + 2905 => Opcode::VLDR_FPCXTS_pre, + 2906 => Opcode::VLDR_FPSCR_NZCVQC_off, + 2907 => Opcode::VLDR_FPSCR_NZCVQC_post, + 2908 => Opcode::VLDR_FPSCR_NZCVQC_pre, + 2909 => Opcode::VLDR_FPSCR_off, + 2910 => Opcode::VLDR_FPSCR_post, + 2911 => Opcode::VLDR_FPSCR_pre, + 2912 => Opcode::VLDR_P0_off, + 2913 => Opcode::VLDR_P0_post, + 2914 => Opcode::VLDR_P0_pre, + 2915 => Opcode::VLDR_VPR_off, + 2916 => Opcode::VLDR_VPR_post, + 2917 => Opcode::VLDR_VPR_pre, + 2918 => Opcode::VLLDM, + 2919 => Opcode::VLLDM_T2, + 2920 => Opcode::VLSTM, + 2921 => Opcode::VLSTM_T2, + 2922 => Opcode::VMAXfd, + 2923 => Opcode::VMAXfq, + 2924 => Opcode::VMAXhd, + 2925 => Opcode::VMAXhq, + 2926 => Opcode::VMAXsv16i8, + 2927 => Opcode::VMAXsv2i32, + 2928 => Opcode::VMAXsv4i16, + 2929 => Opcode::VMAXsv4i32, + 2930 => Opcode::VMAXsv8i16, + 2931 => Opcode::VMAXsv8i8, + 2932 => Opcode::VMAXuv16i8, + 2933 => Opcode::VMAXuv2i32, + 2934 => Opcode::VMAXuv4i16, + 2935 => Opcode::VMAXuv4i32, + 2936 => Opcode::VMAXuv8i16, + 2937 => Opcode::VMAXuv8i8, + 2938 => Opcode::VMINfd, + 2939 => Opcode::VMINfq, + 2940 => Opcode::VMINhd, + 2941 => Opcode::VMINhq, + 2942 => Opcode::VMINsv16i8, + 2943 => Opcode::VMINsv2i32, + 2944 => Opcode::VMINsv4i16, + 2945 => Opcode::VMINsv4i32, + 2946 => Opcode::VMINsv8i16, + 2947 => Opcode::VMINsv8i8, + 2948 => Opcode::VMINuv16i8, + 2949 => Opcode::VMINuv2i32, + 2950 => Opcode::VMINuv4i16, + 2951 => Opcode::VMINuv4i32, + 2952 => Opcode::VMINuv8i16, + 2953 => Opcode::VMINuv8i8, + 2954 => Opcode::VMLAD, + 2955 => Opcode::VMLAH, + 2956 => Opcode::VMLALslsv2i32, + 2957 => Opcode::VMLALslsv4i16, + 2958 => Opcode::VMLALsluv2i32, + 2959 => Opcode::VMLALsluv4i16, + 2960 => Opcode::VMLALsv2i64, + 2961 => Opcode::VMLALsv4i32, + 2962 => Opcode::VMLALsv8i16, + 2963 => Opcode::VMLALuv2i64, + 2964 => Opcode::VMLALuv4i32, + 2965 => Opcode::VMLALuv8i16, + 2966 => Opcode::VMLAS, + 2967 => Opcode::VMLAfd, + 2968 => Opcode::VMLAfq, + 2969 => Opcode::VMLAhd, + 2970 => Opcode::VMLAhq, + 2971 => Opcode::VMLAslfd, + 2972 => Opcode::VMLAslfq, + 2973 => Opcode::VMLAslhd, + 2974 => Opcode::VMLAslhq, + 2975 => Opcode::VMLAslv2i32, + 2976 => Opcode::VMLAslv4i16, + 2977 => Opcode::VMLAslv4i32, + 2978 => Opcode::VMLAslv8i16, + 2979 => Opcode::VMLAv16i8, + 2980 => Opcode::VMLAv2i32, + 2981 => Opcode::VMLAv4i16, + 2982 => Opcode::VMLAv4i32, + 2983 => Opcode::VMLAv8i16, + 2984 => Opcode::VMLAv8i8, + 2985 => Opcode::VMLSD, + 2986 => Opcode::VMLSH, + 2987 => Opcode::VMLSLslsv2i32, + 2988 => Opcode::VMLSLslsv4i16, + 2989 => Opcode::VMLSLsluv2i32, + 2990 => Opcode::VMLSLsluv4i16, + 2991 => Opcode::VMLSLsv2i64, + 2992 => Opcode::VMLSLsv4i32, + 2993 => Opcode::VMLSLsv8i16, + 2994 => Opcode::VMLSLuv2i64, + 2995 => Opcode::VMLSLuv4i32, + 2996 => Opcode::VMLSLuv8i16, + 2997 => Opcode::VMLSS, + 2998 => Opcode::VMLSfd, + 2999 => Opcode::VMLSfq, + 3000 => Opcode::VMLShd, + 3001 => Opcode::VMLShq, + 3002 => Opcode::VMLSslfd, + 3003 => Opcode::VMLSslfq, + 3004 => Opcode::VMLSslhd, + 3005 => Opcode::VMLSslhq, + 3006 => Opcode::VMLSslv2i32, + 3007 => Opcode::VMLSslv4i16, + 3008 => Opcode::VMLSslv4i32, + 3009 => Opcode::VMLSslv8i16, + 3010 => Opcode::VMLSv16i8, + 3011 => Opcode::VMLSv2i32, + 3012 => Opcode::VMLSv4i16, + 3013 => Opcode::VMLSv4i32, + 3014 => Opcode::VMLSv8i16, + 3015 => Opcode::VMLSv8i8, + 3016 => Opcode::VMMLA, + 3017 => Opcode::VMOVD, + 3018 => Opcode::VMOVDRR, + 3019 => Opcode::VMOVH, + 3020 => Opcode::VMOVHR, + 3021 => Opcode::VMOVLsv2i64, + 3022 => Opcode::VMOVLsv4i32, + 3023 => Opcode::VMOVLsv8i16, + 3024 => Opcode::VMOVLuv2i64, + 3025 => Opcode::VMOVLuv4i32, + 3026 => Opcode::VMOVLuv8i16, + 3027 => Opcode::VMOVNv2i32, + 3028 => Opcode::VMOVNv4i16, + 3029 => Opcode::VMOVNv8i8, + 3030 => Opcode::VMOVRH, + 3031 => Opcode::VMOVRRD, + 3032 => Opcode::VMOVRRS, + 3033 => Opcode::VMOVRS, + 3034 => Opcode::VMOVS, + 3035 => Opcode::VMOVSR, + 3036 => Opcode::VMOVSRR, + 3037 => Opcode::VMOVv16i8, + 3038 => Opcode::VMOVv1i64, + 3039 => Opcode::VMOVv2f32, + 3040 => Opcode::VMOVv2i32, + 3041 => Opcode::VMOVv2i64, + 3042 => Opcode::VMOVv4f32, + 3043 => Opcode::VMOVv4i16, + 3044 => Opcode::VMOVv4i32, + 3045 => Opcode::VMOVv8i16, + 3046 => Opcode::VMOVv8i8, + 3047 => Opcode::VMRS, + 3048 => Opcode::VMRS_FPCXTNS, + 3049 => Opcode::VMRS_FPCXTS, + 3050 => Opcode::VMRS_FPEXC, + 3051 => Opcode::VMRS_FPINST, + 3052 => Opcode::VMRS_FPINST2, + 3053 => Opcode::VMRS_FPSCR_NZCVQC, + 3054 => Opcode::VMRS_FPSID, + 3055 => Opcode::VMRS_MVFR0, + 3056 => Opcode::VMRS_MVFR1, + 3057 => Opcode::VMRS_MVFR2, + 3058 => Opcode::VMRS_P0, + 3059 => Opcode::VMRS_VPR, + 3060 => Opcode::VMSR, + 3061 => Opcode::VMSR_FPCXTNS, + 3062 => Opcode::VMSR_FPCXTS, + 3063 => Opcode::VMSR_FPEXC, + 3064 => Opcode::VMSR_FPINST, + 3065 => Opcode::VMSR_FPINST2, + 3066 => Opcode::VMSR_FPSCR_NZCVQC, + 3067 => Opcode::VMSR_FPSID, + 3068 => Opcode::VMSR_P0, + 3069 => Opcode::VMSR_VPR, + 3070 => Opcode::VMULD, + 3071 => Opcode::VMULH, + 3072 => Opcode::VMULLp64, + 3073 => Opcode::VMULLp8, + 3074 => Opcode::VMULLslsv2i32, + 3075 => Opcode::VMULLslsv4i16, + 3076 => Opcode::VMULLsluv2i32, + 3077 => Opcode::VMULLsluv4i16, + 3078 => Opcode::VMULLsv2i64, + 3079 => Opcode::VMULLsv4i32, + 3080 => Opcode::VMULLsv8i16, + 3081 => Opcode::VMULLuv2i64, + 3082 => Opcode::VMULLuv4i32, + 3083 => Opcode::VMULLuv8i16, + 3084 => Opcode::VMULS, + 3085 => Opcode::VMULfd, + 3086 => Opcode::VMULfq, + 3087 => Opcode::VMULhd, + 3088 => Opcode::VMULhq, + 3089 => Opcode::VMULpd, + 3090 => Opcode::VMULpq, + 3091 => Opcode::VMULslfd, + 3092 => Opcode::VMULslfq, + 3093 => Opcode::VMULslhd, + 3094 => Opcode::VMULslhq, + 3095 => Opcode::VMULslv2i32, + 3096 => Opcode::VMULslv4i16, + 3097 => Opcode::VMULslv4i32, + 3098 => Opcode::VMULslv8i16, + 3099 => Opcode::VMULv16i8, + 3100 => Opcode::VMULv2i32, + 3101 => Opcode::VMULv4i16, + 3102 => Opcode::VMULv4i32, + 3103 => Opcode::VMULv8i16, + 3104 => Opcode::VMULv8i8, + 3105 => Opcode::VMVNd, + 3106 => Opcode::VMVNq, + 3107 => Opcode::VMVNv2i32, + 3108 => Opcode::VMVNv4i16, + 3109 => Opcode::VMVNv4i32, + 3110 => Opcode::VMVNv8i16, + 3111 => Opcode::VNEGD, + 3112 => Opcode::VNEGH, + 3113 => Opcode::VNEGS, + 3114 => Opcode::VNEGf32q, + 3115 => Opcode::VNEGfd, + 3116 => Opcode::VNEGhd, + 3117 => Opcode::VNEGhq, + 3118 => Opcode::VNEGs16d, + 3119 => Opcode::VNEGs16q, + 3120 => Opcode::VNEGs32d, + 3121 => Opcode::VNEGs32q, + 3122 => Opcode::VNEGs8d, + 3123 => Opcode::VNEGs8q, + 3124 => Opcode::VNMLAD, + 3125 => Opcode::VNMLAH, + 3126 => Opcode::VNMLAS, + 3127 => Opcode::VNMLSD, + 3128 => Opcode::VNMLSH, + 3129 => Opcode::VNMLSS, + 3130 => Opcode::VNMULD, + 3131 => Opcode::VNMULH, + 3132 => Opcode::VNMULS, + 3133 => Opcode::VORNd, + 3134 => Opcode::VORNq, + 3135 => Opcode::VORRd, + 3136 => Opcode::VORRiv2i32, + 3137 => Opcode::VORRiv4i16, + 3138 => Opcode::VORRiv4i32, + 3139 => Opcode::VORRiv8i16, + 3140 => Opcode::VORRq, + 3141 => Opcode::VPADALsv16i8, + 3142 => Opcode::VPADALsv2i32, + 3143 => Opcode::VPADALsv4i16, + 3144 => Opcode::VPADALsv4i32, + 3145 => Opcode::VPADALsv8i16, + 3146 => Opcode::VPADALsv8i8, + 3147 => Opcode::VPADALuv16i8, + 3148 => Opcode::VPADALuv2i32, + 3149 => Opcode::VPADALuv4i16, + 3150 => Opcode::VPADALuv4i32, + 3151 => Opcode::VPADALuv8i16, + 3152 => Opcode::VPADALuv8i8, + 3153 => Opcode::VPADDLsv16i8, + 3154 => Opcode::VPADDLsv2i32, + 3155 => Opcode::VPADDLsv4i16, + 3156 => Opcode::VPADDLsv4i32, + 3157 => Opcode::VPADDLsv8i16, + 3158 => Opcode::VPADDLsv8i8, + 3159 => Opcode::VPADDLuv16i8, + 3160 => Opcode::VPADDLuv2i32, + 3161 => Opcode::VPADDLuv4i16, + 3162 => Opcode::VPADDLuv4i32, + 3163 => Opcode::VPADDLuv8i16, + 3164 => Opcode::VPADDLuv8i8, + 3165 => Opcode::VPADDf, + 3166 => Opcode::VPADDh, + 3167 => Opcode::VPADDi16, + 3168 => Opcode::VPADDi32, + 3169 => Opcode::VPADDi8, + 3170 => Opcode::VPMAXf, + 3171 => Opcode::VPMAXh, + 3172 => Opcode::VPMAXs16, + 3173 => Opcode::VPMAXs32, + 3174 => Opcode::VPMAXs8, + 3175 => Opcode::VPMAXu16, + 3176 => Opcode::VPMAXu32, + 3177 => Opcode::VPMAXu8, + 3178 => Opcode::VPMINf, + 3179 => Opcode::VPMINh, + 3180 => Opcode::VPMINs16, + 3181 => Opcode::VPMINs32, + 3182 => Opcode::VPMINs8, + 3183 => Opcode::VPMINu16, + 3184 => Opcode::VPMINu32, + 3185 => Opcode::VPMINu8, + 3186 => Opcode::VQABSv16i8, + 3187 => Opcode::VQABSv2i32, + 3188 => Opcode::VQABSv4i16, + 3189 => Opcode::VQABSv4i32, + 3190 => Opcode::VQABSv8i16, + 3191 => Opcode::VQABSv8i8, + 3192 => Opcode::VQADDsv16i8, + 3193 => Opcode::VQADDsv1i64, + 3194 => Opcode::VQADDsv2i32, + 3195 => Opcode::VQADDsv2i64, + 3196 => Opcode::VQADDsv4i16, + 3197 => Opcode::VQADDsv4i32, + 3198 => Opcode::VQADDsv8i16, + 3199 => Opcode::VQADDsv8i8, + 3200 => Opcode::VQADDuv16i8, + 3201 => Opcode::VQADDuv1i64, + 3202 => Opcode::VQADDuv2i32, + 3203 => Opcode::VQADDuv2i64, + 3204 => Opcode::VQADDuv4i16, + 3205 => Opcode::VQADDuv4i32, + 3206 => Opcode::VQADDuv8i16, + 3207 => Opcode::VQADDuv8i8, + 3208 => Opcode::VQDMLALslv2i32, + 3209 => Opcode::VQDMLALslv4i16, + 3210 => Opcode::VQDMLALv2i64, + 3211 => Opcode::VQDMLALv4i32, + 3212 => Opcode::VQDMLSLslv2i32, + 3213 => Opcode::VQDMLSLslv4i16, + 3214 => Opcode::VQDMLSLv2i64, + 3215 => Opcode::VQDMLSLv4i32, + 3216 => Opcode::VQDMULHslv2i32, + 3217 => Opcode::VQDMULHslv4i16, + 3218 => Opcode::VQDMULHslv4i32, + 3219 => Opcode::VQDMULHslv8i16, + 3220 => Opcode::VQDMULHv2i32, + 3221 => Opcode::VQDMULHv4i16, + 3222 => Opcode::VQDMULHv4i32, + 3223 => Opcode::VQDMULHv8i16, + 3224 => Opcode::VQDMULLslv2i32, + 3225 => Opcode::VQDMULLslv4i16, + 3226 => Opcode::VQDMULLv2i64, + 3227 => Opcode::VQDMULLv4i32, + 3228 => Opcode::VQMOVNsuv2i32, + 3229 => Opcode::VQMOVNsuv4i16, + 3230 => Opcode::VQMOVNsuv8i8, + 3231 => Opcode::VQMOVNsv2i32, + 3232 => Opcode::VQMOVNsv4i16, + 3233 => Opcode::VQMOVNsv8i8, + 3234 => Opcode::VQMOVNuv2i32, + 3235 => Opcode::VQMOVNuv4i16, + 3236 => Opcode::VQMOVNuv8i8, + 3237 => Opcode::VQNEGv16i8, + 3238 => Opcode::VQNEGv2i32, + 3239 => Opcode::VQNEGv4i16, + 3240 => Opcode::VQNEGv4i32, + 3241 => Opcode::VQNEGv8i16, + 3242 => Opcode::VQNEGv8i8, + 3243 => Opcode::VQRDMLAHslv2i32, + 3244 => Opcode::VQRDMLAHslv4i16, + 3245 => Opcode::VQRDMLAHslv4i32, + 3246 => Opcode::VQRDMLAHslv8i16, + 3247 => Opcode::VQRDMLAHv2i32, + 3248 => Opcode::VQRDMLAHv4i16, + 3249 => Opcode::VQRDMLAHv4i32, + 3250 => Opcode::VQRDMLAHv8i16, + 3251 => Opcode::VQRDMLSHslv2i32, + 3252 => Opcode::VQRDMLSHslv4i16, + 3253 => Opcode::VQRDMLSHslv4i32, + 3254 => Opcode::VQRDMLSHslv8i16, + 3255 => Opcode::VQRDMLSHv2i32, + 3256 => Opcode::VQRDMLSHv4i16, + 3257 => Opcode::VQRDMLSHv4i32, + 3258 => Opcode::VQRDMLSHv8i16, + 3259 => Opcode::VQRDMULHslv2i32, + 3260 => Opcode::VQRDMULHslv4i16, + 3261 => Opcode::VQRDMULHslv4i32, + 3262 => Opcode::VQRDMULHslv8i16, + 3263 => Opcode::VQRDMULHv2i32, + 3264 => Opcode::VQRDMULHv4i16, + 3265 => Opcode::VQRDMULHv4i32, + 3266 => Opcode::VQRDMULHv8i16, + 3267 => Opcode::VQRSHLsv16i8, + 3268 => Opcode::VQRSHLsv1i64, + 3269 => Opcode::VQRSHLsv2i32, + 3270 => Opcode::VQRSHLsv2i64, + 3271 => Opcode::VQRSHLsv4i16, + 3272 => Opcode::VQRSHLsv4i32, + 3273 => Opcode::VQRSHLsv8i16, + 3274 => Opcode::VQRSHLsv8i8, + 3275 => Opcode::VQRSHLuv16i8, + 3276 => Opcode::VQRSHLuv1i64, + 3277 => Opcode::VQRSHLuv2i32, + 3278 => Opcode::VQRSHLuv2i64, + 3279 => Opcode::VQRSHLuv4i16, + 3280 => Opcode::VQRSHLuv4i32, + 3281 => Opcode::VQRSHLuv8i16, + 3282 => Opcode::VQRSHLuv8i8, + 3283 => Opcode::VQRSHRNsv2i32, + 3284 => Opcode::VQRSHRNsv4i16, + 3285 => Opcode::VQRSHRNsv8i8, + 3286 => Opcode::VQRSHRNuv2i32, + 3287 => Opcode::VQRSHRNuv4i16, + 3288 => Opcode::VQRSHRNuv8i8, + 3289 => Opcode::VQRSHRUNv2i32, + 3290 => Opcode::VQRSHRUNv4i16, + 3291 => Opcode::VQRSHRUNv8i8, + 3292 => Opcode::VQSHLsiv16i8, + 3293 => Opcode::VQSHLsiv1i64, + 3294 => Opcode::VQSHLsiv2i32, + 3295 => Opcode::VQSHLsiv2i64, + 3296 => Opcode::VQSHLsiv4i16, + 3297 => Opcode::VQSHLsiv4i32, + 3298 => Opcode::VQSHLsiv8i16, + 3299 => Opcode::VQSHLsiv8i8, + 3300 => Opcode::VQSHLsuv16i8, + 3301 => Opcode::VQSHLsuv1i64, + 3302 => Opcode::VQSHLsuv2i32, + 3303 => Opcode::VQSHLsuv2i64, + 3304 => Opcode::VQSHLsuv4i16, + 3305 => Opcode::VQSHLsuv4i32, + 3306 => Opcode::VQSHLsuv8i16, + 3307 => Opcode::VQSHLsuv8i8, + 3308 => Opcode::VQSHLsv16i8, + 3309 => Opcode::VQSHLsv1i64, + 3310 => Opcode::VQSHLsv2i32, + 3311 => Opcode::VQSHLsv2i64, + 3312 => Opcode::VQSHLsv4i16, + 3313 => Opcode::VQSHLsv4i32, + 3314 => Opcode::VQSHLsv8i16, + 3315 => Opcode::VQSHLsv8i8, + 3316 => Opcode::VQSHLuiv16i8, + 3317 => Opcode::VQSHLuiv1i64, + 3318 => Opcode::VQSHLuiv2i32, + 3319 => Opcode::VQSHLuiv2i64, + 3320 => Opcode::VQSHLuiv4i16, + 3321 => Opcode::VQSHLuiv4i32, + 3322 => Opcode::VQSHLuiv8i16, + 3323 => Opcode::VQSHLuiv8i8, + 3324 => Opcode::VQSHLuv16i8, + 3325 => Opcode::VQSHLuv1i64, + 3326 => Opcode::VQSHLuv2i32, + 3327 => Opcode::VQSHLuv2i64, + 3328 => Opcode::VQSHLuv4i16, + 3329 => Opcode::VQSHLuv4i32, + 3330 => Opcode::VQSHLuv8i16, + 3331 => Opcode::VQSHLuv8i8, + 3332 => Opcode::VQSHRNsv2i32, + 3333 => Opcode::VQSHRNsv4i16, + 3334 => Opcode::VQSHRNsv8i8, + 3335 => Opcode::VQSHRNuv2i32, + 3336 => Opcode::VQSHRNuv4i16, + 3337 => Opcode::VQSHRNuv8i8, + 3338 => Opcode::VQSHRUNv2i32, + 3339 => Opcode::VQSHRUNv4i16, + 3340 => Opcode::VQSHRUNv8i8, + 3341 => Opcode::VQSUBsv16i8, + 3342 => Opcode::VQSUBsv1i64, + 3343 => Opcode::VQSUBsv2i32, + 3344 => Opcode::VQSUBsv2i64, + 3345 => Opcode::VQSUBsv4i16, + 3346 => Opcode::VQSUBsv4i32, + 3347 => Opcode::VQSUBsv8i16, + 3348 => Opcode::VQSUBsv8i8, + 3349 => Opcode::VQSUBuv16i8, + 3350 => Opcode::VQSUBuv1i64, + 3351 => Opcode::VQSUBuv2i32, + 3352 => Opcode::VQSUBuv2i64, + 3353 => Opcode::VQSUBuv4i16, + 3354 => Opcode::VQSUBuv4i32, + 3355 => Opcode::VQSUBuv8i16, + 3356 => Opcode::VQSUBuv8i8, + 3357 => Opcode::VRADDHNv2i32, + 3358 => Opcode::VRADDHNv4i16, + 3359 => Opcode::VRADDHNv8i8, + 3360 => Opcode::VRECPEd, + 3361 => Opcode::VRECPEfd, + 3362 => Opcode::VRECPEfq, + 3363 => Opcode::VRECPEhd, + 3364 => Opcode::VRECPEhq, + 3365 => Opcode::VRECPEq, + 3366 => Opcode::VRECPSfd, + 3367 => Opcode::VRECPSfq, + 3368 => Opcode::VRECPShd, + 3369 => Opcode::VRECPShq, + 3370 => Opcode::VREV16d8, + 3371 => Opcode::VREV16q8, + 3372 => Opcode::VREV32d16, + 3373 => Opcode::VREV32d8, + 3374 => Opcode::VREV32q16, + 3375 => Opcode::VREV32q8, + 3376 => Opcode::VREV64d16, + 3377 => Opcode::VREV64d32, + 3378 => Opcode::VREV64d8, + 3379 => Opcode::VREV64q16, + 3380 => Opcode::VREV64q32, + 3381 => Opcode::VREV64q8, + 3382 => Opcode::VRHADDsv16i8, + 3383 => Opcode::VRHADDsv2i32, + 3384 => Opcode::VRHADDsv4i16, + 3385 => Opcode::VRHADDsv4i32, + 3386 => Opcode::VRHADDsv8i16, + 3387 => Opcode::VRHADDsv8i8, + 3388 => Opcode::VRHADDuv16i8, + 3389 => Opcode::VRHADDuv2i32, + 3390 => Opcode::VRHADDuv4i16, + 3391 => Opcode::VRHADDuv4i32, + 3392 => Opcode::VRHADDuv8i16, + 3393 => Opcode::VRHADDuv8i8, + 3394 => Opcode::VRINTAD, + 3395 => Opcode::VRINTAH, + 3396 => Opcode::VRINTANDf, + 3397 => Opcode::VRINTANDh, + 3398 => Opcode::VRINTANQf, + 3399 => Opcode::VRINTANQh, + 3400 => Opcode::VRINTAS, + 3401 => Opcode::VRINTMD, + 3402 => Opcode::VRINTMH, + 3403 => Opcode::VRINTMNDf, + 3404 => Opcode::VRINTMNDh, + 3405 => Opcode::VRINTMNQf, + 3406 => Opcode::VRINTMNQh, + 3407 => Opcode::VRINTMS, + 3408 => Opcode::VRINTND, + 3409 => Opcode::VRINTNH, + 3410 => Opcode::VRINTNNDf, + 3411 => Opcode::VRINTNNDh, + 3412 => Opcode::VRINTNNQf, + 3413 => Opcode::VRINTNNQh, + 3414 => Opcode::VRINTNS, + 3415 => Opcode::VRINTPD, + 3416 => Opcode::VRINTPH, + 3417 => Opcode::VRINTPNDf, + 3418 => Opcode::VRINTPNDh, + 3419 => Opcode::VRINTPNQf, + 3420 => Opcode::VRINTPNQh, + 3421 => Opcode::VRINTPS, + 3422 => Opcode::VRINTRD, + 3423 => Opcode::VRINTRH, + 3424 => Opcode::VRINTRS, + 3425 => Opcode::VRINTXD, + 3426 => Opcode::VRINTXH, + 3427 => Opcode::VRINTXNDf, + 3428 => Opcode::VRINTXNDh, + 3429 => Opcode::VRINTXNQf, + 3430 => Opcode::VRINTXNQh, + 3431 => Opcode::VRINTXS, + 3432 => Opcode::VRINTZD, + 3433 => Opcode::VRINTZH, + 3434 => Opcode::VRINTZNDf, + 3435 => Opcode::VRINTZNDh, + 3436 => Opcode::VRINTZNQf, + 3437 => Opcode::VRINTZNQh, + 3438 => Opcode::VRINTZS, + 3439 => Opcode::VRSHLsv16i8, + 3440 => Opcode::VRSHLsv1i64, + 3441 => Opcode::VRSHLsv2i32, + 3442 => Opcode::VRSHLsv2i64, + 3443 => Opcode::VRSHLsv4i16, + 3444 => Opcode::VRSHLsv4i32, + 3445 => Opcode::VRSHLsv8i16, + 3446 => Opcode::VRSHLsv8i8, + 3447 => Opcode::VRSHLuv16i8, + 3448 => Opcode::VRSHLuv1i64, + 3449 => Opcode::VRSHLuv2i32, + 3450 => Opcode::VRSHLuv2i64, + 3451 => Opcode::VRSHLuv4i16, + 3452 => Opcode::VRSHLuv4i32, + 3453 => Opcode::VRSHLuv8i16, + 3454 => Opcode::VRSHLuv8i8, + 3455 => Opcode::VRSHRNv2i32, + 3456 => Opcode::VRSHRNv4i16, + 3457 => Opcode::VRSHRNv8i8, + 3458 => Opcode::VRSHRsv16i8, + 3459 => Opcode::VRSHRsv1i64, + 3460 => Opcode::VRSHRsv2i32, + 3461 => Opcode::VRSHRsv2i64, + 3462 => Opcode::VRSHRsv4i16, + 3463 => Opcode::VRSHRsv4i32, + 3464 => Opcode::VRSHRsv8i16, + 3465 => Opcode::VRSHRsv8i8, + 3466 => Opcode::VRSHRuv16i8, + 3467 => Opcode::VRSHRuv1i64, + 3468 => Opcode::VRSHRuv2i32, + 3469 => Opcode::VRSHRuv2i64, + 3470 => Opcode::VRSHRuv4i16, + 3471 => Opcode::VRSHRuv4i32, + 3472 => Opcode::VRSHRuv8i16, + 3473 => Opcode::VRSHRuv8i8, + 3474 => Opcode::VRSQRTEd, + 3475 => Opcode::VRSQRTEfd, + 3476 => Opcode::VRSQRTEfq, + 3477 => Opcode::VRSQRTEhd, + 3478 => Opcode::VRSQRTEhq, + 3479 => Opcode::VRSQRTEq, + 3480 => Opcode::VRSQRTSfd, + 3481 => Opcode::VRSQRTSfq, + 3482 => Opcode::VRSQRTShd, + 3483 => Opcode::VRSQRTShq, + 3484 => Opcode::VRSRAsv16i8, + 3485 => Opcode::VRSRAsv1i64, + 3486 => Opcode::VRSRAsv2i32, + 3487 => Opcode::VRSRAsv2i64, + 3488 => Opcode::VRSRAsv4i16, + 3489 => Opcode::VRSRAsv4i32, + 3490 => Opcode::VRSRAsv8i16, + 3491 => Opcode::VRSRAsv8i8, + 3492 => Opcode::VRSRAuv16i8, + 3493 => Opcode::VRSRAuv1i64, + 3494 => Opcode::VRSRAuv2i32, + 3495 => Opcode::VRSRAuv2i64, + 3496 => Opcode::VRSRAuv4i16, + 3497 => Opcode::VRSRAuv4i32, + 3498 => Opcode::VRSRAuv8i16, + 3499 => Opcode::VRSRAuv8i8, + 3500 => Opcode::VRSUBHNv2i32, + 3501 => Opcode::VRSUBHNv4i16, + 3502 => Opcode::VRSUBHNv8i8, + 3503 => Opcode::VSCCLRMD, + 3504 => Opcode::VSCCLRMS, + 3505 => Opcode::VSDOTD, + 3506 => Opcode::VSDOTDI, + 3507 => Opcode::VSDOTQ, + 3508 => Opcode::VSDOTQI, + 3509 => Opcode::VSELEQD, + 3510 => Opcode::VSELEQH, + 3511 => Opcode::VSELEQS, + 3512 => Opcode::VSELGED, + 3513 => Opcode::VSELGEH, + 3514 => Opcode::VSELGES, + 3515 => Opcode::VSELGTD, + 3516 => Opcode::VSELGTH, + 3517 => Opcode::VSELGTS, + 3518 => Opcode::VSELVSD, + 3519 => Opcode::VSELVSH, + 3520 => Opcode::VSELVSS, + 3521 => Opcode::VSETLNi16, + 3522 => Opcode::VSETLNi32, + 3523 => Opcode::VSETLNi8, + 3524 => Opcode::VSHLLi16, + 3525 => Opcode::VSHLLi32, + 3526 => Opcode::VSHLLi8, + 3527 => Opcode::VSHLLsv2i64, + 3528 => Opcode::VSHLLsv4i32, + 3529 => Opcode::VSHLLsv8i16, + 3530 => Opcode::VSHLLuv2i64, + 3531 => Opcode::VSHLLuv4i32, + 3532 => Opcode::VSHLLuv8i16, + 3533 => Opcode::VSHLiv16i8, + 3534 => Opcode::VSHLiv1i64, + 3535 => Opcode::VSHLiv2i32, + 3536 => Opcode::VSHLiv2i64, + 3537 => Opcode::VSHLiv4i16, + 3538 => Opcode::VSHLiv4i32, + 3539 => Opcode::VSHLiv8i16, + 3540 => Opcode::VSHLiv8i8, + 3541 => Opcode::VSHLsv16i8, + 3542 => Opcode::VSHLsv1i64, + 3543 => Opcode::VSHLsv2i32, + 3544 => Opcode::VSHLsv2i64, + 3545 => Opcode::VSHLsv4i16, + 3546 => Opcode::VSHLsv4i32, + 3547 => Opcode::VSHLsv8i16, + 3548 => Opcode::VSHLsv8i8, + 3549 => Opcode::VSHLuv16i8, + 3550 => Opcode::VSHLuv1i64, + 3551 => Opcode::VSHLuv2i32, + 3552 => Opcode::VSHLuv2i64, + 3553 => Opcode::VSHLuv4i16, + 3554 => Opcode::VSHLuv4i32, + 3555 => Opcode::VSHLuv8i16, + 3556 => Opcode::VSHLuv8i8, + 3557 => Opcode::VSHRNv2i32, + 3558 => Opcode::VSHRNv4i16, + 3559 => Opcode::VSHRNv8i8, + 3560 => Opcode::VSHRsv16i8, + 3561 => Opcode::VSHRsv1i64, + 3562 => Opcode::VSHRsv2i32, + 3563 => Opcode::VSHRsv2i64, + 3564 => Opcode::VSHRsv4i16, + 3565 => Opcode::VSHRsv4i32, + 3566 => Opcode::VSHRsv8i16, + 3567 => Opcode::VSHRsv8i8, + 3568 => Opcode::VSHRuv16i8, + 3569 => Opcode::VSHRuv1i64, + 3570 => Opcode::VSHRuv2i32, + 3571 => Opcode::VSHRuv2i64, + 3572 => Opcode::VSHRuv4i16, + 3573 => Opcode::VSHRuv4i32, + 3574 => Opcode::VSHRuv8i16, + 3575 => Opcode::VSHRuv8i8, + 3576 => Opcode::VSHTOD, + 3577 => Opcode::VSHTOH, + 3578 => Opcode::VSHTOS, + 3579 => Opcode::VSITOD, + 3580 => Opcode::VSITOH, + 3581 => Opcode::VSITOS, + 3582 => Opcode::VSLIv16i8, + 3583 => Opcode::VSLIv1i64, + 3584 => Opcode::VSLIv2i32, + 3585 => Opcode::VSLIv2i64, + 3586 => Opcode::VSLIv4i16, + 3587 => Opcode::VSLIv4i32, + 3588 => Opcode::VSLIv8i16, + 3589 => Opcode::VSLIv8i8, + 3590 => Opcode::VSLTOD, + 3591 => Opcode::VSLTOH, + 3592 => Opcode::VSLTOS, + 3593 => Opcode::VSMMLA, + 3594 => Opcode::VSQRTD, + 3595 => Opcode::VSQRTH, + 3596 => Opcode::VSQRTS, + 3597 => Opcode::VSRAsv16i8, + 3598 => Opcode::VSRAsv1i64, + 3599 => Opcode::VSRAsv2i32, + 3600 => Opcode::VSRAsv2i64, + 3601 => Opcode::VSRAsv4i16, + 3602 => Opcode::VSRAsv4i32, + 3603 => Opcode::VSRAsv8i16, + 3604 => Opcode::VSRAsv8i8, + 3605 => Opcode::VSRAuv16i8, + 3606 => Opcode::VSRAuv1i64, + 3607 => Opcode::VSRAuv2i32, + 3608 => Opcode::VSRAuv2i64, + 3609 => Opcode::VSRAuv4i16, + 3610 => Opcode::VSRAuv4i32, + 3611 => Opcode::VSRAuv8i16, + 3612 => Opcode::VSRAuv8i8, + 3613 => Opcode::VSRIv16i8, + 3614 => Opcode::VSRIv1i64, + 3615 => Opcode::VSRIv2i32, + 3616 => Opcode::VSRIv2i64, + 3617 => Opcode::VSRIv4i16, + 3618 => Opcode::VSRIv4i32, + 3619 => Opcode::VSRIv8i16, + 3620 => Opcode::VSRIv8i8, + 3621 => Opcode::VST1LNd16, + 3622 => Opcode::VST1LNd16_UPD, + 3623 => Opcode::VST1LNd32, + 3624 => Opcode::VST1LNd32_UPD, + 3625 => Opcode::VST1LNd8, + 3626 => Opcode::VST1LNd8_UPD, + 3627 => Opcode::VST1LNq16Pseudo, + 3628 => Opcode::VST1LNq16Pseudo_UPD, + 3629 => Opcode::VST1LNq32Pseudo, + 3630 => Opcode::VST1LNq32Pseudo_UPD, + 3631 => Opcode::VST1LNq8Pseudo, + 3632 => Opcode::VST1LNq8Pseudo_UPD, + 3633 => Opcode::VST1d16, + 3634 => Opcode::VST1d16Q, + 3635 => Opcode::VST1d16QPseudo, + 3636 => Opcode::VST1d16QPseudoWB_fixed, + 3637 => Opcode::VST1d16QPseudoWB_register, + 3638 => Opcode::VST1d16Qwb_fixed, + 3639 => Opcode::VST1d16Qwb_register, + 3640 => Opcode::VST1d16T, + 3641 => Opcode::VST1d16TPseudo, + 3642 => Opcode::VST1d16TPseudoWB_fixed, + 3643 => Opcode::VST1d16TPseudoWB_register, + 3644 => Opcode::VST1d16Twb_fixed, + 3645 => Opcode::VST1d16Twb_register, + 3646 => Opcode::VST1d16wb_fixed, + 3647 => Opcode::VST1d16wb_register, + 3648 => Opcode::VST1d32, + 3649 => Opcode::VST1d32Q, + 3650 => Opcode::VST1d32QPseudo, + 3651 => Opcode::VST1d32QPseudoWB_fixed, + 3652 => Opcode::VST1d32QPseudoWB_register, + 3653 => Opcode::VST1d32Qwb_fixed, + 3654 => Opcode::VST1d32Qwb_register, + 3655 => Opcode::VST1d32T, + 3656 => Opcode::VST1d32TPseudo, + 3657 => Opcode::VST1d32TPseudoWB_fixed, + 3658 => Opcode::VST1d32TPseudoWB_register, + 3659 => Opcode::VST1d32Twb_fixed, + 3660 => Opcode::VST1d32Twb_register, + 3661 => Opcode::VST1d32wb_fixed, + 3662 => Opcode::VST1d32wb_register, + 3663 => Opcode::VST1d64, + 3664 => Opcode::VST1d64Q, + 3665 => Opcode::VST1d64QPseudo, + 3666 => Opcode::VST1d64QPseudoWB_fixed, + 3667 => Opcode::VST1d64QPseudoWB_register, + 3668 => Opcode::VST1d64Qwb_fixed, + 3669 => Opcode::VST1d64Qwb_register, + 3670 => Opcode::VST1d64T, + 3671 => Opcode::VST1d64TPseudo, + 3672 => Opcode::VST1d64TPseudoWB_fixed, + 3673 => Opcode::VST1d64TPseudoWB_register, + 3674 => Opcode::VST1d64Twb_fixed, + 3675 => Opcode::VST1d64Twb_register, + 3676 => Opcode::VST1d64wb_fixed, + 3677 => Opcode::VST1d64wb_register, + 3678 => Opcode::VST1d8, + 3679 => Opcode::VST1d8Q, + 3680 => Opcode::VST1d8QPseudo, + 3681 => Opcode::VST1d8QPseudoWB_fixed, + 3682 => Opcode::VST1d8QPseudoWB_register, + 3683 => Opcode::VST1d8Qwb_fixed, + 3684 => Opcode::VST1d8Qwb_register, + 3685 => Opcode::VST1d8T, + 3686 => Opcode::VST1d8TPseudo, + 3687 => Opcode::VST1d8TPseudoWB_fixed, + 3688 => Opcode::VST1d8TPseudoWB_register, + 3689 => Opcode::VST1d8Twb_fixed, + 3690 => Opcode::VST1d8Twb_register, + 3691 => Opcode::VST1d8wb_fixed, + 3692 => Opcode::VST1d8wb_register, + 3693 => Opcode::VST1q16, + 3694 => Opcode::VST1q16HighQPseudo, + 3695 => Opcode::VST1q16HighQPseudo_UPD, + 3696 => Opcode::VST1q16HighTPseudo, + 3697 => Opcode::VST1q16HighTPseudo_UPD, + 3698 => Opcode::VST1q16LowQPseudo_UPD, + 3699 => Opcode::VST1q16LowTPseudo_UPD, + 3700 => Opcode::VST1q16wb_fixed, + 3701 => Opcode::VST1q16wb_register, + 3702 => Opcode::VST1q32, + 3703 => Opcode::VST1q32HighQPseudo, + 3704 => Opcode::VST1q32HighQPseudo_UPD, + 3705 => Opcode::VST1q32HighTPseudo, + 3706 => Opcode::VST1q32HighTPseudo_UPD, + 3707 => Opcode::VST1q32LowQPseudo_UPD, + 3708 => Opcode::VST1q32LowTPseudo_UPD, + 3709 => Opcode::VST1q32wb_fixed, + 3710 => Opcode::VST1q32wb_register, + 3711 => Opcode::VST1q64, + 3712 => Opcode::VST1q64HighQPseudo, + 3713 => Opcode::VST1q64HighQPseudo_UPD, + 3714 => Opcode::VST1q64HighTPseudo, + 3715 => Opcode::VST1q64HighTPseudo_UPD, + 3716 => Opcode::VST1q64LowQPseudo_UPD, + 3717 => Opcode::VST1q64LowTPseudo_UPD, + 3718 => Opcode::VST1q64wb_fixed, + 3719 => Opcode::VST1q64wb_register, + 3720 => Opcode::VST1q8, + 3721 => Opcode::VST1q8HighQPseudo, + 3722 => Opcode::VST1q8HighQPseudo_UPD, + 3723 => Opcode::VST1q8HighTPseudo, + 3724 => Opcode::VST1q8HighTPseudo_UPD, + 3725 => Opcode::VST1q8LowQPseudo_UPD, + 3726 => Opcode::VST1q8LowTPseudo_UPD, + 3727 => Opcode::VST1q8wb_fixed, + 3728 => Opcode::VST1q8wb_register, + 3729 => Opcode::VST2LNd16, + 3730 => Opcode::VST2LNd16Pseudo, + 3731 => Opcode::VST2LNd16Pseudo_UPD, + 3732 => Opcode::VST2LNd16_UPD, + 3733 => Opcode::VST2LNd32, + 3734 => Opcode::VST2LNd32Pseudo, + 3735 => Opcode::VST2LNd32Pseudo_UPD, + 3736 => Opcode::VST2LNd32_UPD, + 3737 => Opcode::VST2LNd8, + 3738 => Opcode::VST2LNd8Pseudo, + 3739 => Opcode::VST2LNd8Pseudo_UPD, + 3740 => Opcode::VST2LNd8_UPD, + 3741 => Opcode::VST2LNq16, + 3742 => Opcode::VST2LNq16Pseudo, + 3743 => Opcode::VST2LNq16Pseudo_UPD, + 3744 => Opcode::VST2LNq16_UPD, + 3745 => Opcode::VST2LNq32, + 3746 => Opcode::VST2LNq32Pseudo, + 3747 => Opcode::VST2LNq32Pseudo_UPD, + 3748 => Opcode::VST2LNq32_UPD, + 3749 => Opcode::VST2b16, + 3750 => Opcode::VST2b16wb_fixed, + 3751 => Opcode::VST2b16wb_register, + 3752 => Opcode::VST2b32, + 3753 => Opcode::VST2b32wb_fixed, + 3754 => Opcode::VST2b32wb_register, + 3755 => Opcode::VST2b8, + 3756 => Opcode::VST2b8wb_fixed, + 3757 => Opcode::VST2b8wb_register, + 3758 => Opcode::VST2d16, + 3759 => Opcode::VST2d16wb_fixed, + 3760 => Opcode::VST2d16wb_register, + 3761 => Opcode::VST2d32, + 3762 => Opcode::VST2d32wb_fixed, + 3763 => Opcode::VST2d32wb_register, + 3764 => Opcode::VST2d8, + 3765 => Opcode::VST2d8wb_fixed, + 3766 => Opcode::VST2d8wb_register, + 3767 => Opcode::VST2q16, + 3768 => Opcode::VST2q16Pseudo, + 3769 => Opcode::VST2q16PseudoWB_fixed, + 3770 => Opcode::VST2q16PseudoWB_register, + 3771 => Opcode::VST2q16wb_fixed, + 3772 => Opcode::VST2q16wb_register, + 3773 => Opcode::VST2q32, + 3774 => Opcode::VST2q32Pseudo, + 3775 => Opcode::VST2q32PseudoWB_fixed, + 3776 => Opcode::VST2q32PseudoWB_register, + 3777 => Opcode::VST2q32wb_fixed, + 3778 => Opcode::VST2q32wb_register, + 3779 => Opcode::VST2q8, + 3780 => Opcode::VST2q8Pseudo, + 3781 => Opcode::VST2q8PseudoWB_fixed, + 3782 => Opcode::VST2q8PseudoWB_register, + 3783 => Opcode::VST2q8wb_fixed, + 3784 => Opcode::VST2q8wb_register, + 3785 => Opcode::VST3LNd16, + 3786 => Opcode::VST3LNd16Pseudo, + 3787 => Opcode::VST3LNd16Pseudo_UPD, + 3788 => Opcode::VST3LNd16_UPD, + 3789 => Opcode::VST3LNd32, + 3790 => Opcode::VST3LNd32Pseudo, + 3791 => Opcode::VST3LNd32Pseudo_UPD, + 3792 => Opcode::VST3LNd32_UPD, + 3793 => Opcode::VST3LNd8, + 3794 => Opcode::VST3LNd8Pseudo, + 3795 => Opcode::VST3LNd8Pseudo_UPD, + 3796 => Opcode::VST3LNd8_UPD, + 3797 => Opcode::VST3LNq16, + 3798 => Opcode::VST3LNq16Pseudo, + 3799 => Opcode::VST3LNq16Pseudo_UPD, + 3800 => Opcode::VST3LNq16_UPD, + 3801 => Opcode::VST3LNq32, + 3802 => Opcode::VST3LNq32Pseudo, + 3803 => Opcode::VST3LNq32Pseudo_UPD, + 3804 => Opcode::VST3LNq32_UPD, + 3805 => Opcode::VST3d16, + 3806 => Opcode::VST3d16Pseudo, + 3807 => Opcode::VST3d16Pseudo_UPD, + 3808 => Opcode::VST3d16_UPD, + 3809 => Opcode::VST3d32, + 3810 => Opcode::VST3d32Pseudo, + 3811 => Opcode::VST3d32Pseudo_UPD, + 3812 => Opcode::VST3d32_UPD, + 3813 => Opcode::VST3d8, + 3814 => Opcode::VST3d8Pseudo, + 3815 => Opcode::VST3d8Pseudo_UPD, + 3816 => Opcode::VST3d8_UPD, + 3817 => Opcode::VST3q16, + 3818 => Opcode::VST3q16Pseudo_UPD, + 3819 => Opcode::VST3q16_UPD, + 3820 => Opcode::VST3q16oddPseudo, + 3821 => Opcode::VST3q16oddPseudo_UPD, + 3822 => Opcode::VST3q32, + 3823 => Opcode::VST3q32Pseudo_UPD, + 3824 => Opcode::VST3q32_UPD, + 3825 => Opcode::VST3q32oddPseudo, + 3826 => Opcode::VST3q32oddPseudo_UPD, + 3827 => Opcode::VST3q8, + 3828 => Opcode::VST3q8Pseudo_UPD, + 3829 => Opcode::VST3q8_UPD, + 3830 => Opcode::VST3q8oddPseudo, + 3831 => Opcode::VST3q8oddPseudo_UPD, + 3832 => Opcode::VST4LNd16, + 3833 => Opcode::VST4LNd16Pseudo, + 3834 => Opcode::VST4LNd16Pseudo_UPD, + 3835 => Opcode::VST4LNd16_UPD, + 3836 => Opcode::VST4LNd32, + 3837 => Opcode::VST4LNd32Pseudo, + 3838 => Opcode::VST4LNd32Pseudo_UPD, + 3839 => Opcode::VST4LNd32_UPD, + 3840 => Opcode::VST4LNd8, + 3841 => Opcode::VST4LNd8Pseudo, + 3842 => Opcode::VST4LNd8Pseudo_UPD, + 3843 => Opcode::VST4LNd8_UPD, + 3844 => Opcode::VST4LNq16, + 3845 => Opcode::VST4LNq16Pseudo, + 3846 => Opcode::VST4LNq16Pseudo_UPD, + 3847 => Opcode::VST4LNq16_UPD, + 3848 => Opcode::VST4LNq32, + 3849 => Opcode::VST4LNq32Pseudo, + 3850 => Opcode::VST4LNq32Pseudo_UPD, + 3851 => Opcode::VST4LNq32_UPD, + 3852 => Opcode::VST4d16, + 3853 => Opcode::VST4d16Pseudo, + 3854 => Opcode::VST4d16Pseudo_UPD, + 3855 => Opcode::VST4d16_UPD, + 3856 => Opcode::VST4d32, + 3857 => Opcode::VST4d32Pseudo, + 3858 => Opcode::VST4d32Pseudo_UPD, + 3859 => Opcode::VST4d32_UPD, + 3860 => Opcode::VST4d8, + 3861 => Opcode::VST4d8Pseudo, + 3862 => Opcode::VST4d8Pseudo_UPD, + 3863 => Opcode::VST4d8_UPD, + 3864 => Opcode::VST4q16, + 3865 => Opcode::VST4q16Pseudo_UPD, + 3866 => Opcode::VST4q16_UPD, + 3867 => Opcode::VST4q16oddPseudo, + 3868 => Opcode::VST4q16oddPseudo_UPD, + 3869 => Opcode::VST4q32, + 3870 => Opcode::VST4q32Pseudo_UPD, + 3871 => Opcode::VST4q32_UPD, + 3872 => Opcode::VST4q32oddPseudo, + 3873 => Opcode::VST4q32oddPseudo_UPD, + 3874 => Opcode::VST4q8, + 3875 => Opcode::VST4q8Pseudo_UPD, + 3876 => Opcode::VST4q8_UPD, + 3877 => Opcode::VST4q8oddPseudo, + 3878 => Opcode::VST4q8oddPseudo_UPD, + 3879 => Opcode::VSTMDDB_UPD, + 3880 => Opcode::VSTMDIA, + 3881 => Opcode::VSTMDIA_UPD, + 3882 => Opcode::VSTMQIA, + 3883 => Opcode::VSTMSDB_UPD, + 3884 => Opcode::VSTMSIA, + 3885 => Opcode::VSTMSIA_UPD, + 3886 => Opcode::VSTRD, + 3887 => Opcode::VSTRH, + 3888 => Opcode::VSTRS, + 3889 => Opcode::VSTR_FPCXTNS_off, + 3890 => Opcode::VSTR_FPCXTNS_post, + 3891 => Opcode::VSTR_FPCXTNS_pre, + 3892 => Opcode::VSTR_FPCXTS_off, + 3893 => Opcode::VSTR_FPCXTS_post, + 3894 => Opcode::VSTR_FPCXTS_pre, + 3895 => Opcode::VSTR_FPSCR_NZCVQC_off, + 3896 => Opcode::VSTR_FPSCR_NZCVQC_post, + 3897 => Opcode::VSTR_FPSCR_NZCVQC_pre, + 3898 => Opcode::VSTR_FPSCR_off, + 3899 => Opcode::VSTR_FPSCR_post, + 3900 => Opcode::VSTR_FPSCR_pre, + 3901 => Opcode::VSTR_P0_off, + 3902 => Opcode::VSTR_P0_post, + 3903 => Opcode::VSTR_P0_pre, + 3904 => Opcode::VSTR_VPR_off, + 3905 => Opcode::VSTR_VPR_post, + 3906 => Opcode::VSTR_VPR_pre, + 3907 => Opcode::VSUBD, + 3908 => Opcode::VSUBH, + 3909 => Opcode::VSUBHNv2i32, + 3910 => Opcode::VSUBHNv4i16, + 3911 => Opcode::VSUBHNv8i8, + 3912 => Opcode::VSUBLsv2i64, + 3913 => Opcode::VSUBLsv4i32, + 3914 => Opcode::VSUBLsv8i16, + 3915 => Opcode::VSUBLuv2i64, + 3916 => Opcode::VSUBLuv4i32, + 3917 => Opcode::VSUBLuv8i16, + 3918 => Opcode::VSUBS, + 3919 => Opcode::VSUBWsv2i64, + 3920 => Opcode::VSUBWsv4i32, + 3921 => Opcode::VSUBWsv8i16, + 3922 => Opcode::VSUBWuv2i64, + 3923 => Opcode::VSUBWuv4i32, + 3924 => Opcode::VSUBWuv8i16, + 3925 => Opcode::VSUBfd, + 3926 => Opcode::VSUBfq, + 3927 => Opcode::VSUBhd, + 3928 => Opcode::VSUBhq, + 3929 => Opcode::VSUBv16i8, + 3930 => Opcode::VSUBv1i64, + 3931 => Opcode::VSUBv2i32, + 3932 => Opcode::VSUBv2i64, + 3933 => Opcode::VSUBv4i16, + 3934 => Opcode::VSUBv4i32, + 3935 => Opcode::VSUBv8i16, + 3936 => Opcode::VSUBv8i8, + 3937 => Opcode::VSUDOTDI, + 3938 => Opcode::VSUDOTQI, + 3939 => Opcode::VSWPd, + 3940 => Opcode::VSWPq, + 3941 => Opcode::VTBL1, + 3942 => Opcode::VTBL2, + 3943 => Opcode::VTBL3, + 3944 => Opcode::VTBL3Pseudo, + 3945 => Opcode::VTBL4, + 3946 => Opcode::VTBL4Pseudo, + 3947 => Opcode::VTBX1, + 3948 => Opcode::VTBX2, + 3949 => Opcode::VTBX3, + 3950 => Opcode::VTBX3Pseudo, + 3951 => Opcode::VTBX4, + 3952 => Opcode::VTBX4Pseudo, + 3953 => Opcode::VTOSHD, + 3954 => Opcode::VTOSHH, + 3955 => Opcode::VTOSHS, + 3956 => Opcode::VTOSIRD, + 3957 => Opcode::VTOSIRH, + 3958 => Opcode::VTOSIRS, + 3959 => Opcode::VTOSIZD, + 3960 => Opcode::VTOSIZH, + 3961 => Opcode::VTOSIZS, + 3962 => Opcode::VTOSLD, + 3963 => Opcode::VTOSLH, + 3964 => Opcode::VTOSLS, + 3965 => Opcode::VTOUHD, + 3966 => Opcode::VTOUHH, + 3967 => Opcode::VTOUHS, + 3968 => Opcode::VTOUIRD, + 3969 => Opcode::VTOUIRH, + 3970 => Opcode::VTOUIRS, + 3971 => Opcode::VTOUIZD, + 3972 => Opcode::VTOUIZH, + 3973 => Opcode::VTOUIZS, + 3974 => Opcode::VTOULD, + 3975 => Opcode::VTOULH, + 3976 => Opcode::VTOULS, + 3977 => Opcode::VTRNd16, + 3978 => Opcode::VTRNd32, + 3979 => Opcode::VTRNd8, + 3980 => Opcode::VTRNq16, + 3981 => Opcode::VTRNq32, + 3982 => Opcode::VTRNq8, + 3983 => Opcode::VTSTv16i8, + 3984 => Opcode::VTSTv2i32, + 3985 => Opcode::VTSTv4i16, + 3986 => Opcode::VTSTv4i32, + 3987 => Opcode::VTSTv8i16, + 3988 => Opcode::VTSTv8i8, + 3989 => Opcode::VUDOTD, + 3990 => Opcode::VUDOTDI, + 3991 => Opcode::VUDOTQ, + 3992 => Opcode::VUDOTQI, + 3993 => Opcode::VUHTOD, + 3994 => Opcode::VUHTOH, + 3995 => Opcode::VUHTOS, + 3996 => Opcode::VUITOD, + 3997 => Opcode::VUITOH, + 3998 => Opcode::VUITOS, + 3999 => Opcode::VULTOD, + 4000 => Opcode::VULTOH, + 4001 => Opcode::VULTOS, + 4002 => Opcode::VUMMLA, + 4003 => Opcode::VUSDOTD, + 4004 => Opcode::VUSDOTDI, + 4005 => Opcode::VUSDOTQ, + 4006 => Opcode::VUSDOTQI, + 4007 => Opcode::VUSMMLA, + 4008 => Opcode::VUZPd16, + 4009 => Opcode::VUZPd8, + 4010 => Opcode::VUZPq16, + 4011 => Opcode::VUZPq32, + 4012 => Opcode::VUZPq8, + 4013 => Opcode::VZIPd16, + 4014 => Opcode::VZIPd8, + 4015 => Opcode::VZIPq16, + 4016 => Opcode::VZIPq32, + 4017 => Opcode::VZIPq8, + 4018 => Opcode::sysLDMDA, + 4019 => Opcode::sysLDMDA_UPD, + 4020 => Opcode::sysLDMDB, + 4021 => Opcode::sysLDMDB_UPD, + 4022 => Opcode::sysLDMIA, + 4023 => Opcode::sysLDMIA_UPD, + 4024 => Opcode::sysLDMIB, + 4025 => Opcode::sysLDMIB_UPD, + 4026 => Opcode::sysSTMDA, + 4027 => Opcode::sysSTMDA_UPD, + 4028 => Opcode::sysSTMDB, + 4029 => Opcode::sysSTMDB_UPD, + 4030 => Opcode::sysSTMIA, + 4031 => Opcode::sysSTMIA_UPD, + 4032 => Opcode::sysSTMIB, + 4033 => Opcode::sysSTMIB_UPD, + 4034 => Opcode::t2ADCri, + 4035 => Opcode::t2ADCrr, + 4036 => Opcode::t2ADCrs, + 4037 => Opcode::t2ADDri, + 4038 => Opcode::t2ADDri12, + 4039 => Opcode::t2ADDrr, + 4040 => Opcode::t2ADDrs, + 4041 => Opcode::t2ADDspImm, + 4042 => Opcode::t2ADDspImm12, + 4043 => Opcode::t2ADR, + 4044 => Opcode::t2ANDri, + 4045 => Opcode::t2ANDrr, + 4046 => Opcode::t2ANDrs, + 4047 => Opcode::t2ASRri, + 4048 => Opcode::t2ASRrr, + 4049 => Opcode::t2ASRs1, + 4050 => Opcode::t2AUT, + 4051 => Opcode::t2AUTG, + 4052 => Opcode::t2B, + 4053 => Opcode::t2BFC, + 4054 => Opcode::t2BFI, + 4055 => Opcode::t2BFLi, + 4056 => Opcode::t2BFLr, + 4057 => Opcode::t2BFi, + 4058 => Opcode::t2BFic, + 4059 => Opcode::t2BFr, + 4060 => Opcode::t2BICri, + 4061 => Opcode::t2BICrr, + 4062 => Opcode::t2BICrs, + 4063 => Opcode::t2BTI, + 4064 => Opcode::t2BXAUT, + 4065 => Opcode::t2BXJ, + 4066 => Opcode::t2Bcc, + 4067 => Opcode::t2CDP, + 4068 => Opcode::t2CDP2, + 4069 => Opcode::t2CLREX, + 4070 => Opcode::t2CLRM, + 4071 => Opcode::t2CLZ, + 4072 => Opcode::t2CMNri, + 4073 => Opcode::t2CMNzrr, + 4074 => Opcode::t2CMNzrs, + 4075 => Opcode::t2CMPri, + 4076 => Opcode::t2CMPrr, + 4077 => Opcode::t2CMPrs, + 4078 => Opcode::t2CPS1p, + 4079 => Opcode::t2CPS2p, + 4080 => Opcode::t2CPS3p, + 4081 => Opcode::t2CRC32B, + 4082 => Opcode::t2CRC32CB, + 4083 => Opcode::t2CRC32CH, + 4084 => Opcode::t2CRC32CW, + 4085 => Opcode::t2CRC32H, + 4086 => Opcode::t2CRC32W, + 4087 => Opcode::t2CSEL, + 4088 => Opcode::t2CSINC, + 4089 => Opcode::t2CSINV, + 4090 => Opcode::t2CSNEG, + 4091 => Opcode::t2DBG, + 4092 => Opcode::t2DCPS1, + 4093 => Opcode::t2DCPS2, + 4094 => Opcode::t2DCPS3, + 4095 => Opcode::t2DLS, + 4096 => Opcode::t2DMB, + 4097 => Opcode::t2DSB, + 4098 => Opcode::t2EORri, + 4099 => Opcode::t2EORrr, + 4100 => Opcode::t2EORrs, + 4101 => Opcode::t2HINT, + 4102 => Opcode::t2HVC, + 4103 => Opcode::t2ISB, + 4104 => Opcode::t2IT, + 4105 => Opcode::t2Int_eh_sjlj_setjmp, + 4106 => Opcode::t2Int_eh_sjlj_setjmp_nofp, + 4107 => Opcode::t2LDA, + 4108 => Opcode::t2LDAB, + 4109 => Opcode::t2LDAEX, + 4110 => Opcode::t2LDAEXB, + 4111 => Opcode::t2LDAEXD, + 4112 => Opcode::t2LDAEXH, + 4113 => Opcode::t2LDAH, + 4114 => Opcode::t2LDC2L_OFFSET, + 4115 => Opcode::t2LDC2L_OPTION, + 4116 => Opcode::t2LDC2L_POST, + 4117 => Opcode::t2LDC2L_PRE, + 4118 => Opcode::t2LDC2_OFFSET, + 4119 => Opcode::t2LDC2_OPTION, + 4120 => Opcode::t2LDC2_POST, + 4121 => Opcode::t2LDC2_PRE, + 4122 => Opcode::t2LDCL_OFFSET, + 4123 => Opcode::t2LDCL_OPTION, + 4124 => Opcode::t2LDCL_POST, + 4125 => Opcode::t2LDCL_PRE, + 4126 => Opcode::t2LDC_OFFSET, + 4127 => Opcode::t2LDC_OPTION, + 4128 => Opcode::t2LDC_POST, + 4129 => Opcode::t2LDC_PRE, + 4130 => Opcode::t2LDMDB, + 4131 => Opcode::t2LDMDB_UPD, + 4132 => Opcode::t2LDMIA, + 4133 => Opcode::t2LDMIA_UPD, + 4134 => Opcode::t2LDRBT, + 4135 => Opcode::t2LDRB_POST, + 4136 => Opcode::t2LDRB_PRE, + 4137 => Opcode::t2LDRBi12, + 4138 => Opcode::t2LDRBi8, + 4139 => Opcode::t2LDRBpci, + 4140 => Opcode::t2LDRBs, + 4141 => Opcode::t2LDRD_POST, + 4142 => Opcode::t2LDRD_PRE, + 4143 => Opcode::t2LDRDi8, + 4144 => Opcode::t2LDREX, + 4145 => Opcode::t2LDREXB, + 4146 => Opcode::t2LDREXD, + 4147 => Opcode::t2LDREXH, + 4148 => Opcode::t2LDRHT, + 4149 => Opcode::t2LDRH_POST, + 4150 => Opcode::t2LDRH_PRE, + 4151 => Opcode::t2LDRHi12, + 4152 => Opcode::t2LDRHi8, + 4153 => Opcode::t2LDRHpci, + 4154 => Opcode::t2LDRHs, + 4155 => Opcode::t2LDRSBT, + 4156 => Opcode::t2LDRSB_POST, + 4157 => Opcode::t2LDRSB_PRE, + 4158 => Opcode::t2LDRSBi12, + 4159 => Opcode::t2LDRSBi8, + 4160 => Opcode::t2LDRSBpci, + 4161 => Opcode::t2LDRSBs, + 4162 => Opcode::t2LDRSHT, + 4163 => Opcode::t2LDRSH_POST, + 4164 => Opcode::t2LDRSH_PRE, + 4165 => Opcode::t2LDRSHi12, + 4166 => Opcode::t2LDRSHi8, + 4167 => Opcode::t2LDRSHpci, + 4168 => Opcode::t2LDRSHs, + 4169 => Opcode::t2LDRT, + 4170 => Opcode::t2LDR_POST, + 4171 => Opcode::t2LDR_PRE, + 4172 => Opcode::t2LDRi12, + 4173 => Opcode::t2LDRi8, + 4174 => Opcode::t2LDRpci, + 4175 => Opcode::t2LDRs, + 4176 => Opcode::t2LE, + 4177 => Opcode::t2LEUpdate, + 4178 => Opcode::t2LSLri, + 4179 => Opcode::t2LSLrr, + 4180 => Opcode::t2LSRri, + 4181 => Opcode::t2LSRrr, + 4182 => Opcode::t2LSRs1, + 4183 => Opcode::t2MCR, + 4184 => Opcode::t2MCR2, + 4185 => Opcode::t2MCRR, + 4186 => Opcode::t2MCRR2, + 4187 => Opcode::t2MLA, + 4188 => Opcode::t2MLS, + 4189 => Opcode::t2MOVTi16, + 4190 => Opcode::t2MOVi, + 4191 => Opcode::t2MOVi16, + 4192 => Opcode::t2MOVr, + 4193 => Opcode::t2MRC, + 4194 => Opcode::t2MRC2, + 4195 => Opcode::t2MRRC, + 4196 => Opcode::t2MRRC2, + 4197 => Opcode::t2MRS_AR, + 4198 => Opcode::t2MRS_M, + 4199 => Opcode::t2MRSbanked, + 4200 => Opcode::t2MRSsys_AR, + 4201 => Opcode::t2MSR_AR, + 4202 => Opcode::t2MSR_M, + 4203 => Opcode::t2MSRbanked, + 4204 => Opcode::t2MUL, + 4205 => Opcode::t2MVNi, + 4206 => Opcode::t2MVNr, + 4207 => Opcode::t2MVNs, + 4208 => Opcode::t2ORNri, + 4209 => Opcode::t2ORNrr, + 4210 => Opcode::t2ORNrs, + 4211 => Opcode::t2ORRri, + 4212 => Opcode::t2ORRrr, + 4213 => Opcode::t2ORRrs, + 4214 => Opcode::t2PAC, + 4215 => Opcode::t2PACBTI, + 4216 => Opcode::t2PACG, + 4217 => Opcode::t2PKHBT, + 4218 => Opcode::t2PKHTB, + 4219 => Opcode::t2PLDWi12, + 4220 => Opcode::t2PLDWi8, + 4221 => Opcode::t2PLDWs, + 4222 => Opcode::t2PLDi12, + 4223 => Opcode::t2PLDi8, + 4224 => Opcode::t2PLDpci, + 4225 => Opcode::t2PLDs, + 4226 => Opcode::t2PLIi12, + 4227 => Opcode::t2PLIi8, + 4228 => Opcode::t2PLIpci, + 4229 => Opcode::t2PLIs, + 4230 => Opcode::t2QADD, + 4231 => Opcode::t2QADD16, + 4232 => Opcode::t2QADD8, + 4233 => Opcode::t2QASX, + 4234 => Opcode::t2QDADD, + 4235 => Opcode::t2QDSUB, + 4236 => Opcode::t2QSAX, + 4237 => Opcode::t2QSUB, + 4238 => Opcode::t2QSUB16, + 4239 => Opcode::t2QSUB8, + 4240 => Opcode::t2RBIT, + 4241 => Opcode::t2REV, + 4242 => Opcode::t2REV16, + 4243 => Opcode::t2REVSH, + 4244 => Opcode::t2RFEDB, + 4245 => Opcode::t2RFEDBW, + 4246 => Opcode::t2RFEIA, + 4247 => Opcode::t2RFEIAW, + 4248 => Opcode::t2RORri, + 4249 => Opcode::t2RORrr, + 4250 => Opcode::t2RRX, + 4251 => Opcode::t2RSBri, + 4252 => Opcode::t2RSBrr, + 4253 => Opcode::t2RSBrs, + 4254 => Opcode::t2SADD16, + 4255 => Opcode::t2SADD8, + 4256 => Opcode::t2SASX, + 4257 => Opcode::t2SB, + 4258 => Opcode::t2SBCri, + 4259 => Opcode::t2SBCrr, + 4260 => Opcode::t2SBCrs, + 4261 => Opcode::t2SBFX, + 4262 => Opcode::t2SDIV, + 4263 => Opcode::t2SEL, + 4264 => Opcode::t2SETPAN, + 4265 => Opcode::t2SG, + 4266 => Opcode::t2SHADD16, + 4267 => Opcode::t2SHADD8, + 4268 => Opcode::t2SHASX, + 4269 => Opcode::t2SHSAX, + 4270 => Opcode::t2SHSUB16, + 4271 => Opcode::t2SHSUB8, + 4272 => Opcode::t2SMC, + 4273 => Opcode::t2SMLABB, + 4274 => Opcode::t2SMLABT, + 4275 => Opcode::t2SMLAD, + 4276 => Opcode::t2SMLADX, + 4277 => Opcode::t2SMLAL, + 4278 => Opcode::t2SMLALBB, + 4279 => Opcode::t2SMLALBT, + 4280 => Opcode::t2SMLALD, + 4281 => Opcode::t2SMLALDX, + 4282 => Opcode::t2SMLALTB, + 4283 => Opcode::t2SMLALTT, + 4284 => Opcode::t2SMLATB, + 4285 => Opcode::t2SMLATT, + 4286 => Opcode::t2SMLAWB, + 4287 => Opcode::t2SMLAWT, + 4288 => Opcode::t2SMLSD, + 4289 => Opcode::t2SMLSDX, + 4290 => Opcode::t2SMLSLD, + 4291 => Opcode::t2SMLSLDX, + 4292 => Opcode::t2SMMLA, + 4293 => Opcode::t2SMMLAR, + 4294 => Opcode::t2SMMLS, + 4295 => Opcode::t2SMMLSR, + 4296 => Opcode::t2SMMUL, + 4297 => Opcode::t2SMMULR, + 4298 => Opcode::t2SMUAD, + 4299 => Opcode::t2SMUADX, + 4300 => Opcode::t2SMULBB, + 4301 => Opcode::t2SMULBT, + 4302 => Opcode::t2SMULL, + 4303 => Opcode::t2SMULTB, + 4304 => Opcode::t2SMULTT, + 4305 => Opcode::t2SMULWB, + 4306 => Opcode::t2SMULWT, + 4307 => Opcode::t2SMUSD, + 4308 => Opcode::t2SMUSDX, + 4309 => Opcode::t2SRSDB, + 4310 => Opcode::t2SRSDB_UPD, + 4311 => Opcode::t2SRSIA, + 4312 => Opcode::t2SRSIA_UPD, + 4313 => Opcode::t2SSAT, + 4314 => Opcode::t2SSAT16, + 4315 => Opcode::t2SSAX, + 4316 => Opcode::t2SSUB16, + 4317 => Opcode::t2SSUB8, + 4318 => Opcode::t2STC2L_OFFSET, + 4319 => Opcode::t2STC2L_OPTION, + 4320 => Opcode::t2STC2L_POST, + 4321 => Opcode::t2STC2L_PRE, + 4322 => Opcode::t2STC2_OFFSET, + 4323 => Opcode::t2STC2_OPTION, + 4324 => Opcode::t2STC2_POST, + 4325 => Opcode::t2STC2_PRE, + 4326 => Opcode::t2STCL_OFFSET, + 4327 => Opcode::t2STCL_OPTION, + 4328 => Opcode::t2STCL_POST, + 4329 => Opcode::t2STCL_PRE, + 4330 => Opcode::t2STC_OFFSET, + 4331 => Opcode::t2STC_OPTION, + 4332 => Opcode::t2STC_POST, + 4333 => Opcode::t2STC_PRE, + 4334 => Opcode::t2STL, + 4335 => Opcode::t2STLB, + 4336 => Opcode::t2STLEX, + 4337 => Opcode::t2STLEXB, + 4338 => Opcode::t2STLEXD, + 4339 => Opcode::t2STLEXH, + 4340 => Opcode::t2STLH, + 4341 => Opcode::t2STMDB, + 4342 => Opcode::t2STMDB_UPD, + 4343 => Opcode::t2STMIA, + 4344 => Opcode::t2STMIA_UPD, + 4345 => Opcode::t2STRBT, + 4346 => Opcode::t2STRB_POST, + 4347 => Opcode::t2STRB_PRE, + 4348 => Opcode::t2STRBi12, + 4349 => Opcode::t2STRBi8, + 4350 => Opcode::t2STRBs, + 4351 => Opcode::t2STRD_POST, + 4352 => Opcode::t2STRD_PRE, + 4353 => Opcode::t2STRDi8, + 4354 => Opcode::t2STREX, + 4355 => Opcode::t2STREXB, + 4356 => Opcode::t2STREXD, + 4357 => Opcode::t2STREXH, + 4358 => Opcode::t2STRHT, + 4359 => Opcode::t2STRH_POST, + 4360 => Opcode::t2STRH_PRE, + 4361 => Opcode::t2STRHi12, + 4362 => Opcode::t2STRHi8, + 4363 => Opcode::t2STRHs, + 4364 => Opcode::t2STRT, + 4365 => Opcode::t2STR_POST, + 4366 => Opcode::t2STR_PRE, + 4367 => Opcode::t2STRi12, + 4368 => Opcode::t2STRi8, + 4369 => Opcode::t2STRs, + 4370 => Opcode::t2SUBS_PC_LR, + 4371 => Opcode::t2SUBri, + 4372 => Opcode::t2SUBri12, + 4373 => Opcode::t2SUBrr, + 4374 => Opcode::t2SUBrs, + 4375 => Opcode::t2SUBspImm, + 4376 => Opcode::t2SUBspImm12, + 4377 => Opcode::t2SXTAB, + 4378 => Opcode::t2SXTAB16, + 4379 => Opcode::t2SXTAH, + 4380 => Opcode::t2SXTB, + 4381 => Opcode::t2SXTB16, + 4382 => Opcode::t2SXTH, + 4383 => Opcode::t2TBB, + 4384 => Opcode::t2TBH, + 4385 => Opcode::t2TEQri, + 4386 => Opcode::t2TEQrr, + 4387 => Opcode::t2TEQrs, + 4388 => Opcode::t2TSB, + 4389 => Opcode::t2TSTri, + 4390 => Opcode::t2TSTrr, + 4391 => Opcode::t2TSTrs, + 4392 => Opcode::t2TT, + 4393 => Opcode::t2TTA, + 4394 => Opcode::t2TTAT, + 4395 => Opcode::t2TTT, + 4396 => Opcode::t2UADD16, + 4397 => Opcode::t2UADD8, + 4398 => Opcode::t2UASX, + 4399 => Opcode::t2UBFX, + 4400 => Opcode::t2UDF, + 4401 => Opcode::t2UDIV, + 4402 => Opcode::t2UHADD16, + 4403 => Opcode::t2UHADD8, + 4404 => Opcode::t2UHASX, + 4405 => Opcode::t2UHSAX, + 4406 => Opcode::t2UHSUB16, + 4407 => Opcode::t2UHSUB8, + 4408 => Opcode::t2UMAAL, + 4409 => Opcode::t2UMLAL, + 4410 => Opcode::t2UMULL, + 4411 => Opcode::t2UQADD16, + 4412 => Opcode::t2UQADD8, + 4413 => Opcode::t2UQASX, + 4414 => Opcode::t2UQSAX, + 4415 => Opcode::t2UQSUB16, + 4416 => Opcode::t2UQSUB8, + 4417 => Opcode::t2USAD8, + 4418 => Opcode::t2USADA8, + 4419 => Opcode::t2USAT, + 4420 => Opcode::t2USAT16, + 4421 => Opcode::t2USAX, + 4422 => Opcode::t2USUB16, + 4423 => Opcode::t2USUB8, + 4424 => Opcode::t2UXTAB, + 4425 => Opcode::t2UXTAB16, + 4426 => Opcode::t2UXTAH, + 4427 => Opcode::t2UXTB, + 4428 => Opcode::t2UXTB16, + 4429 => Opcode::t2UXTH, + 4430 => Opcode::t2WLS, + 4431 => Opcode::tADC, + 4432 => Opcode::tADDhirr, + 4433 => Opcode::tADDi3, + 4434 => Opcode::tADDi8, + 4435 => Opcode::tADDrSP, + 4436 => Opcode::tADDrSPi, + 4437 => Opcode::tADDrr, + 4438 => Opcode::tADDspi, + 4439 => Opcode::tADDspr, + 4440 => Opcode::tADR, + 4441 => Opcode::tAND, + 4442 => Opcode::tASRri, + 4443 => Opcode::tASRrr, + 4444 => Opcode::tB, + 4445 => Opcode::tBIC, + 4446 => Opcode::tBKPT, + 4447 => Opcode::tBL, + 4448 => Opcode::tBLXNSr, + 4449 => Opcode::tBLXi, + 4450 => Opcode::tBLXr, + 4451 => Opcode::tBX, + 4452 => Opcode::tBXNS, + 4453 => Opcode::tBcc, + 4454 => Opcode::tCBNZ, + 4455 => Opcode::tCBZ, + 4456 => Opcode::tCMNz, + 4457 => Opcode::tCMPhir, + 4458 => Opcode::tCMPi8, + 4459 => Opcode::tCMPr, + 4460 => Opcode::tCPS, + 4461 => Opcode::tEOR, + 4462 => Opcode::tHINT, + 4463 => Opcode::tHLT, + 4464 => Opcode::tInt_WIN_eh_sjlj_longjmp, + 4465 => Opcode::tInt_eh_sjlj_longjmp, + 4466 => Opcode::tInt_eh_sjlj_setjmp, + 4467 => Opcode::tLDMIA, + 4468 => Opcode::tLDRBi, + 4469 => Opcode::tLDRBr, + 4470 => Opcode::tLDRHi, + 4471 => Opcode::tLDRHr, + 4472 => Opcode::tLDRSB, + 4473 => Opcode::tLDRSH, + 4474 => Opcode::tLDRi, + 4475 => Opcode::tLDRpci, + 4476 => Opcode::tLDRr, + 4477 => Opcode::tLDRspi, + 4478 => Opcode::tLSLri, + 4479 => Opcode::tLSLrr, + 4480 => Opcode::tLSRri, + 4481 => Opcode::tLSRrr, + 4482 => Opcode::tMOVSr, + 4483 => Opcode::tMOVi8, + 4484 => Opcode::tMOVr, + 4485 => Opcode::tMUL, + 4486 => Opcode::tMVN, + 4487 => Opcode::tORR, + 4488 => Opcode::tPICADD, + 4489 => Opcode::tPOP, + 4490 => Opcode::tPUSH, + 4491 => Opcode::tREV, + 4492 => Opcode::tREV16, + 4493 => Opcode::tREVSH, + 4494 => Opcode::tROR, + 4495 => Opcode::tRSB, + 4496 => Opcode::tSBC, + 4497 => Opcode::tSETEND, + 4498 => Opcode::tSTMIA_UPD, + 4499 => Opcode::tSTRBi, + 4500 => Opcode::tSTRBr, + 4501 => Opcode::tSTRHi, + 4502 => Opcode::tSTRHr, + 4503 => Opcode::tSTRi, + 4504 => Opcode::tSTRr, + 4505 => Opcode::tSTRspi, + 4506 => Opcode::tSUBi3, + 4507 => Opcode::tSUBi8, + 4508 => Opcode::tSUBrr, + 4509 => Opcode::tSUBspi, + 4510 => Opcode::tSVC, + 4511 => Opcode::tSXTB, + 4512 => Opcode::tSXTH, + 4513 => Opcode::tTRAP, + 4514 => Opcode::tTST, + 4515 => Opcode::tUDF, + 4516 => Opcode::tUXTB, + 4517 => Opcode::tUXTH, + 4518 => Opcode::t__brkdiv0, + 4519 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/arm/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/arm/registers.rs new file mode 100644 index 0000000..4d7d2a8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/arm/registers.rs @@ -0,0 +1,609 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + APSR, + APSR_NZCV, + CPSR, + FPCXTNS, + FPCXTS, + FPEXC, + FPINST, + FPSCR, + FPSCR_NZCV, + FPSCR_NZCVQC, + FPSCR_RM, + FPSID, + ITSTATE, + LR, + PC, + RA_AUTH_CODE, + SP, + SPSR, + VPR, + ZR, + D0, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + D9, + D10, + D11, + D12, + D13, + D14, + D15, + D16, + D17, + D18, + D19, + D20, + D21, + D22, + D23, + D24, + D25, + D26, + D27, + D28, + D29, + D30, + D31, + FPINST2, + MVFR0, + MVFR1, + MVFR2, + P0, + Q0, + Q1, + Q2, + Q3, + Q4, + Q5, + Q6, + Q7, + Q8, + Q9, + Q10, + Q11, + Q12, + Q13, + Q14, + Q15, + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + S0, + S1, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + S12, + S13, + S14, + S15, + S16, + S17, + S18, + S19, + S20, + S21, + S22, + S23, + S24, + S25, + S26, + S27, + S28, + S29, + S30, + S31, + D0_D2, + D1_D3, + D2_D4, + D3_D5, + D4_D6, + D5_D7, + D6_D8, + D7_D9, + D8_D10, + D9_D11, + D10_D12, + D11_D13, + D12_D14, + D13_D15, + D14_D16, + D15_D17, + D16_D18, + D17_D19, + D18_D20, + D19_D21, + D20_D22, + D21_D23, + D22_D24, + D23_D25, + D24_D26, + D25_D27, + D26_D28, + D27_D29, + D28_D30, + D29_D31, + Q0_Q1, + Q1_Q2, + Q2_Q3, + Q3_Q4, + Q4_Q5, + Q5_Q6, + Q6_Q7, + Q7_Q8, + Q8_Q9, + Q9_Q10, + Q10_Q11, + Q11_Q12, + Q12_Q13, + Q13_Q14, + Q14_Q15, + Q0_Q1_Q2_Q3, + Q1_Q2_Q3_Q4, + Q2_Q3_Q4_Q5, + Q3_Q4_Q5_Q6, + Q4_Q5_Q6_Q7, + Q5_Q6_Q7_Q8, + Q6_Q7_Q8_Q9, + Q7_Q8_Q9_Q10, + Q8_Q9_Q10_Q11, + Q9_Q10_Q11_Q12, + Q10_Q11_Q12_Q13, + Q11_Q12_Q13_Q14, + Q12_Q13_Q14_Q15, + R0_R1, + R2_R3, + R4_R5, + R6_R7, + R8_R9, + R10_R11, + R12_SP, + D0_D1_D2, + D1_D2_D3, + D2_D3_D4, + D3_D4_D5, + D4_D5_D6, + D5_D6_D7, + D6_D7_D8, + D7_D8_D9, + D8_D9_D10, + D9_D10_D11, + D10_D11_D12, + D11_D12_D13, + D12_D13_D14, + D13_D14_D15, + D14_D15_D16, + D15_D16_D17, + D16_D17_D18, + D17_D18_D19, + D18_D19_D20, + D19_D20_D21, + D20_D21_D22, + D21_D22_D23, + D22_D23_D24, + D23_D24_D25, + D24_D25_D26, + D25_D26_D27, + D26_D27_D28, + D27_D28_D29, + D28_D29_D30, + D29_D30_D31, + D0_D2_D4, + D1_D3_D5, + D2_D4_D6, + D3_D5_D7, + D4_D6_D8, + D5_D7_D9, + D6_D8_D10, + D7_D9_D11, + D8_D10_D12, + D9_D11_D13, + D10_D12_D14, + D11_D13_D15, + D12_D14_D16, + D13_D15_D17, + D14_D16_D18, + D15_D17_D19, + D16_D18_D20, + D17_D19_D21, + D18_D20_D22, + D19_D21_D23, + D20_D22_D24, + D21_D23_D25, + D22_D24_D26, + D23_D25_D27, + D24_D26_D28, + D25_D27_D29, + D26_D28_D30, + D27_D29_D31, + D0_D2_D4_D6, + D1_D3_D5_D7, + D2_D4_D6_D8, + D3_D5_D7_D9, + D4_D6_D8_D10, + D5_D7_D9_D11, + D6_D8_D10_D12, + D7_D9_D11_D13, + D8_D10_D12_D14, + D9_D11_D13_D15, + D10_D12_D14_D16, + D11_D13_D15_D17, + D12_D14_D16_D18, + D13_D15_D17_D19, + D14_D16_D18_D20, + D15_D17_D19_D21, + D16_D18_D20_D22, + D17_D19_D21_D23, + D18_D20_D22_D24, + D19_D21_D23_D25, + D20_D22_D24_D26, + D21_D23_D25_D27, + D22_D24_D26_D28, + D23_D25_D27_D29, + D24_D26_D28_D30, + D25_D27_D29_D31, + D1_D2, + D3_D4, + D5_D6, + D7_D8, + D9_D10, + D11_D12, + D13_D14, + D15_D16, + D17_D18, + D19_D20, + D21_D22, + D23_D24, + D25_D26, + D27_D28, + D29_D30, + D1_D2_D3_D4, + D3_D4_D5_D6, + D5_D6_D7_D8, + D7_D8_D9_D10, + D9_D10_D11_D12, + D11_D12_D13_D14, + D13_D14_D15_D16, + D15_D16_D17_D18, + D17_D18_D19_D20, + D19_D20_D21_D22, + D21_D22_D23_D24, + D23_D24_D25_D26, + D25_D26_D27_D28, + D27_D28_D29_D30, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::APSR, + 2 => Reg::APSR_NZCV, + 3 => Reg::CPSR, + 4 => Reg::FPCXTNS, + 5 => Reg::FPCXTS, + 6 => Reg::FPEXC, + 7 => Reg::FPINST, + 8 => Reg::FPSCR, + 9 => Reg::FPSCR_NZCV, + 10 => Reg::FPSCR_NZCVQC, + 11 => Reg::FPSCR_RM, + 12 => Reg::FPSID, + 13 => Reg::ITSTATE, + 14 => Reg::LR, + 15 => Reg::PC, + 16 => Reg::RA_AUTH_CODE, + 17 => Reg::SP, + 18 => Reg::SPSR, + 19 => Reg::VPR, + 20 => Reg::ZR, + 21 => Reg::D0, + 22 => Reg::D1, + 23 => Reg::D2, + 24 => Reg::D3, + 25 => Reg::D4, + 26 => Reg::D5, + 27 => Reg::D6, + 28 => Reg::D7, + 29 => Reg::D8, + 30 => Reg::D9, + 31 => Reg::D10, + 32 => Reg::D11, + 33 => Reg::D12, + 34 => Reg::D13, + 35 => Reg::D14, + 36 => Reg::D15, + 37 => Reg::D16, + 38 => Reg::D17, + 39 => Reg::D18, + 40 => Reg::D19, + 41 => Reg::D20, + 42 => Reg::D21, + 43 => Reg::D22, + 44 => Reg::D23, + 45 => Reg::D24, + 46 => Reg::D25, + 47 => Reg::D26, + 48 => Reg::D27, + 49 => Reg::D28, + 50 => Reg::D29, + 51 => Reg::D30, + 52 => Reg::D31, + 53 => Reg::FPINST2, + 54 => Reg::MVFR0, + 55 => Reg::MVFR1, + 56 => Reg::MVFR2, + 57 => Reg::P0, + 58 => Reg::Q0, + 59 => Reg::Q1, + 60 => Reg::Q2, + 61 => Reg::Q3, + 62 => Reg::Q4, + 63 => Reg::Q5, + 64 => Reg::Q6, + 65 => Reg::Q7, + 66 => Reg::Q8, + 67 => Reg::Q9, + 68 => Reg::Q10, + 69 => Reg::Q11, + 70 => Reg::Q12, + 71 => Reg::Q13, + 72 => Reg::Q14, + 73 => Reg::Q15, + 74 => Reg::R0, + 75 => Reg::R1, + 76 => Reg::R2, + 77 => Reg::R3, + 78 => Reg::R4, + 79 => Reg::R5, + 80 => Reg::R6, + 81 => Reg::R7, + 82 => Reg::R8, + 83 => Reg::R9, + 84 => Reg::R10, + 85 => Reg::R11, + 86 => Reg::R12, + 87 => Reg::S0, + 88 => Reg::S1, + 89 => Reg::S2, + 90 => Reg::S3, + 91 => Reg::S4, + 92 => Reg::S5, + 93 => Reg::S6, + 94 => Reg::S7, + 95 => Reg::S8, + 96 => Reg::S9, + 97 => Reg::S10, + 98 => Reg::S11, + 99 => Reg::S12, + 100 => Reg::S13, + 101 => Reg::S14, + 102 => Reg::S15, + 103 => Reg::S16, + 104 => Reg::S17, + 105 => Reg::S18, + 106 => Reg::S19, + 107 => Reg::S20, + 108 => Reg::S21, + 109 => Reg::S22, + 110 => Reg::S23, + 111 => Reg::S24, + 112 => Reg::S25, + 113 => Reg::S26, + 114 => Reg::S27, + 115 => Reg::S28, + 116 => Reg::S29, + 117 => Reg::S30, + 118 => Reg::S31, + 119 => Reg::D0_D2, + 120 => Reg::D1_D3, + 121 => Reg::D2_D4, + 122 => Reg::D3_D5, + 123 => Reg::D4_D6, + 124 => Reg::D5_D7, + 125 => Reg::D6_D8, + 126 => Reg::D7_D9, + 127 => Reg::D8_D10, + 128 => Reg::D9_D11, + 129 => Reg::D10_D12, + 130 => Reg::D11_D13, + 131 => Reg::D12_D14, + 132 => Reg::D13_D15, + 133 => Reg::D14_D16, + 134 => Reg::D15_D17, + 135 => Reg::D16_D18, + 136 => Reg::D17_D19, + 137 => Reg::D18_D20, + 138 => Reg::D19_D21, + 139 => Reg::D20_D22, + 140 => Reg::D21_D23, + 141 => Reg::D22_D24, + 142 => Reg::D23_D25, + 143 => Reg::D24_D26, + 144 => Reg::D25_D27, + 145 => Reg::D26_D28, + 146 => Reg::D27_D29, + 147 => Reg::D28_D30, + 148 => Reg::D29_D31, + 149 => Reg::Q0_Q1, + 150 => Reg::Q1_Q2, + 151 => Reg::Q2_Q3, + 152 => Reg::Q3_Q4, + 153 => Reg::Q4_Q5, + 154 => Reg::Q5_Q6, + 155 => Reg::Q6_Q7, + 156 => Reg::Q7_Q8, + 157 => Reg::Q8_Q9, + 158 => Reg::Q9_Q10, + 159 => Reg::Q10_Q11, + 160 => Reg::Q11_Q12, + 161 => Reg::Q12_Q13, + 162 => Reg::Q13_Q14, + 163 => Reg::Q14_Q15, + 164 => Reg::Q0_Q1_Q2_Q3, + 165 => Reg::Q1_Q2_Q3_Q4, + 166 => Reg::Q2_Q3_Q4_Q5, + 167 => Reg::Q3_Q4_Q5_Q6, + 168 => Reg::Q4_Q5_Q6_Q7, + 169 => Reg::Q5_Q6_Q7_Q8, + 170 => Reg::Q6_Q7_Q8_Q9, + 171 => Reg::Q7_Q8_Q9_Q10, + 172 => Reg::Q8_Q9_Q10_Q11, + 173 => Reg::Q9_Q10_Q11_Q12, + 174 => Reg::Q10_Q11_Q12_Q13, + 175 => Reg::Q11_Q12_Q13_Q14, + 176 => Reg::Q12_Q13_Q14_Q15, + 177 => Reg::R0_R1, + 178 => Reg::R2_R3, + 179 => Reg::R4_R5, + 180 => Reg::R6_R7, + 181 => Reg::R8_R9, + 182 => Reg::R10_R11, + 183 => Reg::R12_SP, + 184 => Reg::D0_D1_D2, + 185 => Reg::D1_D2_D3, + 186 => Reg::D2_D3_D4, + 187 => Reg::D3_D4_D5, + 188 => Reg::D4_D5_D6, + 189 => Reg::D5_D6_D7, + 190 => Reg::D6_D7_D8, + 191 => Reg::D7_D8_D9, + 192 => Reg::D8_D9_D10, + 193 => Reg::D9_D10_D11, + 194 => Reg::D10_D11_D12, + 195 => Reg::D11_D12_D13, + 196 => Reg::D12_D13_D14, + 197 => Reg::D13_D14_D15, + 198 => Reg::D14_D15_D16, + 199 => Reg::D15_D16_D17, + 200 => Reg::D16_D17_D18, + 201 => Reg::D17_D18_D19, + 202 => Reg::D18_D19_D20, + 203 => Reg::D19_D20_D21, + 204 => Reg::D20_D21_D22, + 205 => Reg::D21_D22_D23, + 206 => Reg::D22_D23_D24, + 207 => Reg::D23_D24_D25, + 208 => Reg::D24_D25_D26, + 209 => Reg::D25_D26_D27, + 210 => Reg::D26_D27_D28, + 211 => Reg::D27_D28_D29, + 212 => Reg::D28_D29_D30, + 213 => Reg::D29_D30_D31, + 214 => Reg::D0_D2_D4, + 215 => Reg::D1_D3_D5, + 216 => Reg::D2_D4_D6, + 217 => Reg::D3_D5_D7, + 218 => Reg::D4_D6_D8, + 219 => Reg::D5_D7_D9, + 220 => Reg::D6_D8_D10, + 221 => Reg::D7_D9_D11, + 222 => Reg::D8_D10_D12, + 223 => Reg::D9_D11_D13, + 224 => Reg::D10_D12_D14, + 225 => Reg::D11_D13_D15, + 226 => Reg::D12_D14_D16, + 227 => Reg::D13_D15_D17, + 228 => Reg::D14_D16_D18, + 229 => Reg::D15_D17_D19, + 230 => Reg::D16_D18_D20, + 231 => Reg::D17_D19_D21, + 232 => Reg::D18_D20_D22, + 233 => Reg::D19_D21_D23, + 234 => Reg::D20_D22_D24, + 235 => Reg::D21_D23_D25, + 236 => Reg::D22_D24_D26, + 237 => Reg::D23_D25_D27, + 238 => Reg::D24_D26_D28, + 239 => Reg::D25_D27_D29, + 240 => Reg::D26_D28_D30, + 241 => Reg::D27_D29_D31, + 242 => Reg::D0_D2_D4_D6, + 243 => Reg::D1_D3_D5_D7, + 244 => Reg::D2_D4_D6_D8, + 245 => Reg::D3_D5_D7_D9, + 246 => Reg::D4_D6_D8_D10, + 247 => Reg::D5_D7_D9_D11, + 248 => Reg::D6_D8_D10_D12, + 249 => Reg::D7_D9_D11_D13, + 250 => Reg::D8_D10_D12_D14, + 251 => Reg::D9_D11_D13_D15, + 252 => Reg::D10_D12_D14_D16, + 253 => Reg::D11_D13_D15_D17, + 254 => Reg::D12_D14_D16_D18, + 255 => Reg::D13_D15_D17_D19, + 256 => Reg::D14_D16_D18_D20, + 257 => Reg::D15_D17_D19_D21, + 258 => Reg::D16_D18_D20_D22, + 259 => Reg::D17_D19_D21_D23, + 260 => Reg::D18_D20_D22_D24, + 261 => Reg::D19_D21_D23_D25, + 262 => Reg::D20_D22_D24_D26, + 263 => Reg::D21_D23_D25_D27, + 264 => Reg::D22_D24_D26_D28, + 265 => Reg::D23_D25_D27_D29, + 266 => Reg::D24_D26_D28_D30, + 267 => Reg::D25_D27_D29_D31, + 268 => Reg::D1_D2, + 269 => Reg::D3_D4, + 270 => Reg::D5_D6, + 271 => Reg::D7_D8, + 272 => Reg::D9_D10, + 273 => Reg::D11_D12, + 274 => Reg::D13_D14, + 275 => Reg::D15_D16, + 276 => Reg::D17_D18, + 277 => Reg::D19_D20, + 278 => Reg::D21_D22, + 279 => Reg::D23_D24, + 280 => Reg::D25_D26, + 281 => Reg::D27_D28, + 282 => Reg::D29_D30, + 283 => Reg::D1_D2_D3_D4, + 284 => Reg::D3_D4_D5_D6, + 285 => Reg::D5_D6_D7_D8, + 286 => Reg::D7_D8_D9_D10, + 287 => Reg::D9_D10_D11_D12, + 288 => Reg::D11_D12_D13_D14, + 289 => Reg::D13_D14_D15_D16, + 290 => Reg::D15_D16_D17_D18, + 291 => Reg::D17_D18_D19_D20, + 292 => Reg::D19_D20_D21_D22, + 293 => Reg::D21_D22_D23_D24, + 294 => Reg::D23_D24_D25_D26, + 295 => Reg::D25_D26_D27_D28, + 296 => Reg::D27_D28_D29_D30, + 297 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/config.rs b/vendor/lief/api/rust/crates/lief/src/assembly/config.rs new file mode 100644 index 0000000..2412c28 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/config.rs @@ -0,0 +1,92 @@ +use lief_ffi as ffi; +use std::sync::Arc; + +pub type SymbolResolver = dyn Fn(&str) -> Option + Send + Sync + 'static; + +#[derive(Clone)] +/// This structure exposes the different elements that can be configured to assemble +/// code. +pub struct AssemblerConfig { + /// Default configuration + pub dialect: Dialect, + + /// This attribute aims to store a function for resolving symbols in the assembly listing. + /// + /// For instance, given this assembly code: + /// + /// ```text + /// 0x1000: mov rdi, rbx + /// 0x1003: call _my_function + /// ``` + /// + /// The function `_my_function` will remain undefined unless we return its address + /// in a callback defined in this attribute [`AssemblerConfig::symbol_resolver`]: + /// + /// ```rust + /// let mut config = AssemblerConfig::default(); + /// + /// let resolver = Arc::new(move |symbol: &str| { + /// return Some(0x4000); + /// }); + /// + /// config.symbol_resolver = Some(resolver); + /// ``` + pub symbol_resolver: Option>, +} + +impl Default for AssemblerConfig { + fn default() -> AssemblerConfig { + AssemblerConfig { + dialect: Dialect::DEFAULT_DIALECT, + symbol_resolver: None, + } + } +} + +impl AssemblerConfig { + #[doc(hidden)] + pub fn into_ffi(&self) -> Box { + if let Some(ref resolver) = self.symbol_resolver { + let closure = resolver.clone(); + ffi::AssemblerConfig_r::new(move |s| closure(s)) + } else { + ffi::AssemblerConfig_r::new(|_| None) + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// The different supported dialects +pub enum Dialect { + DEFAULT_DIALECT, + + /// Intel syntax + X86_INTEL, + + /// Intel syntax + X86_ATT, + UNKNOWN(u32), +} + +impl From for Dialect { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Dialect::DEFAULT_DIALECT, + 0x00000001 => Dialect::X86_INTEL, + 0x00000002 => Dialect::X86_ATT, + _ => Dialect::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Dialect) -> u32 { + match value { + Dialect::DEFAULT_DIALECT => 0x00000000, + Dialect::X86_INTEL => 0x00000001, + Dialect::X86_ATT => 0x00000002, + Dialect::UNKNOWN(value) => value, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf.rs new file mode 100644 index 0000000..6118a15 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf.rs @@ -0,0 +1,18 @@ +//! eBPF architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/instruction.rs new file mode 100644 index 0000000..0cbf0b8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/instruction.rs @@ -0,0 +1,52 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +use crate::assembly::ebpf; +use crate::declare_fwd_iterator; + +/// This structure represents an eBPF instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`ebpf::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } +} + +declare_fwd_iterator!( + Operands, + ebpf::Operands, + ffi::asm_Instruction, + ffi::asm_ebpf_Operand, + ffi::asm_ebpf_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/opcodes.rs new file mode 100644 index 0000000..b57f8d8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/opcodes.rs @@ -0,0 +1,1061 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + FI_ri, + LDIMM64, + MEMCPY, + Select, + Select_32, + Select_32_64, + Select_64_32, + Select_Ri, + Select_Ri_32, + Select_Ri_32_64, + Select_Ri_64_32, + ADDR_SPACE_CAST, + ADD_ri, + ADD_ri_32, + ADD_rr, + ADD_rr_32, + AND_ri, + AND_ri_32, + AND_rr, + AND_rr_32, + BE16, + BE32, + BE64, + BSWAP16, + BSWAP32, + BSWAP64, + CMPXCHGD, + CMPXCHGW32, + CORE_LD32, + CORE_LD64, + CORE_SHIFT, + CORE_ST, + DIV_ri, + DIV_ri_32, + DIV_rr, + DIV_rr_32, + JAL, + JALX, + JCOND, + JEQ_ri, + JEQ_ri_32, + JEQ_rr, + JEQ_rr_32, + JMP, + JMPL, + JNE_ri, + JNE_ri_32, + JNE_rr, + JNE_rr_32, + JSET_ri, + JSET_ri_32, + JSET_rr, + JSET_rr_32, + JSGE_ri, + JSGE_ri_32, + JSGE_rr, + JSGE_rr_32, + JSGT_ri, + JSGT_ri_32, + JSGT_rr, + JSGT_rr_32, + JSLE_ri, + JSLE_ri_32, + JSLE_rr, + JSLE_rr_32, + JSLT_ri, + JSLT_ri_32, + JSLT_rr, + JSLT_rr_32, + JUGE_ri, + JUGE_ri_32, + JUGE_rr, + JUGE_rr_32, + JUGT_ri, + JUGT_ri_32, + JUGT_rr, + JUGT_rr_32, + JULE_ri, + JULE_ri_32, + JULE_rr, + JULE_rr_32, + JULT_ri, + JULT_ri_32, + JULT_rr, + JULT_rr_32, + JX, + LDB, + LDB32, + LDBACQ32, + LDBSX, + LDD, + LDDACQ, + LDH, + LDH32, + LDHACQ32, + LDHSX, + LDW, + LDW32, + LDWACQ32, + LDWSX, + LD_ABS_B, + LD_ABS_H, + LD_ABS_W, + LD_IND_B, + LD_IND_H, + LD_IND_W, + LD_imm64, + LD_pseudo, + LE16, + LE32, + LE64, + MOD_ri, + MOD_ri_32, + MOD_rr, + MOD_rr_32, + MOVSX_rr_16, + MOVSX_rr_32, + MOVSX_rr_32_16, + MOVSX_rr_32_8, + MOVSX_rr_8, + MOV_32_64, + MOV_ri, + MOV_ri_32, + MOV_rr, + MOV_rr_32, + MUL_ri, + MUL_ri_32, + MUL_rr, + MUL_rr_32, + NEG_32, + NEG_64, + NOP, + OR_ri, + OR_ri_32, + OR_rr, + OR_rr_32, + RET, + SDIV_ri, + SDIV_ri_32, + SDIV_rr, + SDIV_rr_32, + SLL_ri, + SLL_ri_32, + SLL_rr, + SLL_rr_32, + SMOD_ri, + SMOD_ri_32, + SMOD_rr, + SMOD_rr_32, + SRA_ri, + SRA_ri_32, + SRA_rr, + SRA_rr_32, + SRL_ri, + SRL_ri_32, + SRL_rr, + SRL_rr_32, + STB, + STB32, + STBREL32, + STB_imm, + STD, + STDREL, + STD_imm, + STH, + STH32, + STHREL32, + STH_imm, + STW, + STW32, + STWREL32, + STW_imm, + SUB_ri, + SUB_ri_32, + SUB_rr, + SUB_rr_32, + XADDD, + XADDW, + XADDW32, + XANDD, + XANDW32, + XCHGD, + XCHGW32, + XFADDD, + XFADDW32, + XFANDD, + XFANDW32, + XFORD, + XFORW32, + XFXORD, + XFXORW32, + XORD, + XORW32, + XOR_ri, + XOR_ri_32, + XOR_rr, + XOR_rr_32, + XXORD, + XXORW32, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ADJCALLSTACKDOWN, + 323 => Opcode::ADJCALLSTACKUP, + 324 => Opcode::FI_ri, + 325 => Opcode::LDIMM64, + 326 => Opcode::MEMCPY, + 327 => Opcode::Select, + 328 => Opcode::Select_32, + 329 => Opcode::Select_32_64, + 330 => Opcode::Select_64_32, + 331 => Opcode::Select_Ri, + 332 => Opcode::Select_Ri_32, + 333 => Opcode::Select_Ri_32_64, + 334 => Opcode::Select_Ri_64_32, + 335 => Opcode::ADDR_SPACE_CAST, + 336 => Opcode::ADD_ri, + 337 => Opcode::ADD_ri_32, + 338 => Opcode::ADD_rr, + 339 => Opcode::ADD_rr_32, + 340 => Opcode::AND_ri, + 341 => Opcode::AND_ri_32, + 342 => Opcode::AND_rr, + 343 => Opcode::AND_rr_32, + 344 => Opcode::BE16, + 345 => Opcode::BE32, + 346 => Opcode::BE64, + 347 => Opcode::BSWAP16, + 348 => Opcode::BSWAP32, + 349 => Opcode::BSWAP64, + 350 => Opcode::CMPXCHGD, + 351 => Opcode::CMPXCHGW32, + 352 => Opcode::CORE_LD32, + 353 => Opcode::CORE_LD64, + 354 => Opcode::CORE_SHIFT, + 355 => Opcode::CORE_ST, + 356 => Opcode::DIV_ri, + 357 => Opcode::DIV_ri_32, + 358 => Opcode::DIV_rr, + 359 => Opcode::DIV_rr_32, + 360 => Opcode::JAL, + 361 => Opcode::JALX, + 362 => Opcode::JCOND, + 363 => Opcode::JEQ_ri, + 364 => Opcode::JEQ_ri_32, + 365 => Opcode::JEQ_rr, + 366 => Opcode::JEQ_rr_32, + 367 => Opcode::JMP, + 368 => Opcode::JMPL, + 369 => Opcode::JNE_ri, + 370 => Opcode::JNE_ri_32, + 371 => Opcode::JNE_rr, + 372 => Opcode::JNE_rr_32, + 373 => Opcode::JSET_ri, + 374 => Opcode::JSET_ri_32, + 375 => Opcode::JSET_rr, + 376 => Opcode::JSET_rr_32, + 377 => Opcode::JSGE_ri, + 378 => Opcode::JSGE_ri_32, + 379 => Opcode::JSGE_rr, + 380 => Opcode::JSGE_rr_32, + 381 => Opcode::JSGT_ri, + 382 => Opcode::JSGT_ri_32, + 383 => Opcode::JSGT_rr, + 384 => Opcode::JSGT_rr_32, + 385 => Opcode::JSLE_ri, + 386 => Opcode::JSLE_ri_32, + 387 => Opcode::JSLE_rr, + 388 => Opcode::JSLE_rr_32, + 389 => Opcode::JSLT_ri, + 390 => Opcode::JSLT_ri_32, + 391 => Opcode::JSLT_rr, + 392 => Opcode::JSLT_rr_32, + 393 => Opcode::JUGE_ri, + 394 => Opcode::JUGE_ri_32, + 395 => Opcode::JUGE_rr, + 396 => Opcode::JUGE_rr_32, + 397 => Opcode::JUGT_ri, + 398 => Opcode::JUGT_ri_32, + 399 => Opcode::JUGT_rr, + 400 => Opcode::JUGT_rr_32, + 401 => Opcode::JULE_ri, + 402 => Opcode::JULE_ri_32, + 403 => Opcode::JULE_rr, + 404 => Opcode::JULE_rr_32, + 405 => Opcode::JULT_ri, + 406 => Opcode::JULT_ri_32, + 407 => Opcode::JULT_rr, + 408 => Opcode::JULT_rr_32, + 409 => Opcode::JX, + 410 => Opcode::LDB, + 411 => Opcode::LDB32, + 412 => Opcode::LDBACQ32, + 413 => Opcode::LDBSX, + 414 => Opcode::LDD, + 415 => Opcode::LDDACQ, + 416 => Opcode::LDH, + 417 => Opcode::LDH32, + 418 => Opcode::LDHACQ32, + 419 => Opcode::LDHSX, + 420 => Opcode::LDW, + 421 => Opcode::LDW32, + 422 => Opcode::LDWACQ32, + 423 => Opcode::LDWSX, + 424 => Opcode::LD_ABS_B, + 425 => Opcode::LD_ABS_H, + 426 => Opcode::LD_ABS_W, + 427 => Opcode::LD_IND_B, + 428 => Opcode::LD_IND_H, + 429 => Opcode::LD_IND_W, + 430 => Opcode::LD_imm64, + 431 => Opcode::LD_pseudo, + 432 => Opcode::LE16, + 433 => Opcode::LE32, + 434 => Opcode::LE64, + 435 => Opcode::MOD_ri, + 436 => Opcode::MOD_ri_32, + 437 => Opcode::MOD_rr, + 438 => Opcode::MOD_rr_32, + 439 => Opcode::MOVSX_rr_16, + 440 => Opcode::MOVSX_rr_32, + 441 => Opcode::MOVSX_rr_32_16, + 442 => Opcode::MOVSX_rr_32_8, + 443 => Opcode::MOVSX_rr_8, + 444 => Opcode::MOV_32_64, + 445 => Opcode::MOV_ri, + 446 => Opcode::MOV_ri_32, + 447 => Opcode::MOV_rr, + 448 => Opcode::MOV_rr_32, + 449 => Opcode::MUL_ri, + 450 => Opcode::MUL_ri_32, + 451 => Opcode::MUL_rr, + 452 => Opcode::MUL_rr_32, + 453 => Opcode::NEG_32, + 454 => Opcode::NEG_64, + 455 => Opcode::NOP, + 456 => Opcode::OR_ri, + 457 => Opcode::OR_ri_32, + 458 => Opcode::OR_rr, + 459 => Opcode::OR_rr_32, + 460 => Opcode::RET, + 461 => Opcode::SDIV_ri, + 462 => Opcode::SDIV_ri_32, + 463 => Opcode::SDIV_rr, + 464 => Opcode::SDIV_rr_32, + 465 => Opcode::SLL_ri, + 466 => Opcode::SLL_ri_32, + 467 => Opcode::SLL_rr, + 468 => Opcode::SLL_rr_32, + 469 => Opcode::SMOD_ri, + 470 => Opcode::SMOD_ri_32, + 471 => Opcode::SMOD_rr, + 472 => Opcode::SMOD_rr_32, + 473 => Opcode::SRA_ri, + 474 => Opcode::SRA_ri_32, + 475 => Opcode::SRA_rr, + 476 => Opcode::SRA_rr_32, + 477 => Opcode::SRL_ri, + 478 => Opcode::SRL_ri_32, + 479 => Opcode::SRL_rr, + 480 => Opcode::SRL_rr_32, + 481 => Opcode::STB, + 482 => Opcode::STB32, + 483 => Opcode::STBREL32, + 484 => Opcode::STB_imm, + 485 => Opcode::STD, + 486 => Opcode::STDREL, + 487 => Opcode::STD_imm, + 488 => Opcode::STH, + 489 => Opcode::STH32, + 490 => Opcode::STHREL32, + 491 => Opcode::STH_imm, + 492 => Opcode::STW, + 493 => Opcode::STW32, + 494 => Opcode::STWREL32, + 495 => Opcode::STW_imm, + 496 => Opcode::SUB_ri, + 497 => Opcode::SUB_ri_32, + 498 => Opcode::SUB_rr, + 499 => Opcode::SUB_rr_32, + 500 => Opcode::XADDD, + 501 => Opcode::XADDW, + 502 => Opcode::XADDW32, + 503 => Opcode::XANDD, + 504 => Opcode::XANDW32, + 505 => Opcode::XCHGD, + 506 => Opcode::XCHGW32, + 507 => Opcode::XFADDD, + 508 => Opcode::XFADDW32, + 509 => Opcode::XFANDD, + 510 => Opcode::XFANDW32, + 511 => Opcode::XFORD, + 512 => Opcode::XFORW32, + 513 => Opcode::XFXORD, + 514 => Opcode::XFXORW32, + 515 => Opcode::XORD, + 516 => Opcode::XORW32, + 517 => Opcode::XOR_ri, + 518 => Opcode::XOR_ri_32, + 519 => Opcode::XOR_rr, + 520 => Opcode::XOR_rr_32, + 521 => Opcode::XXORD, + 522 => Opcode::XXORW32, + 523 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands.rs new file mode 100644 index 0000000..34a995d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand + Reg(Register), + + /// A PC-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_ebpf_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_ebpf_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_ebpf_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_ebpf_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/immediate.rs new file mode 100644 index 0000000..e865734 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// r1 = 8 +/// | +/// +---> Immediate(8) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/memory.rs new file mode 100644 index 0000000..daacda5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/memory.rs @@ -0,0 +1,47 @@ +use lief_ffi as ffi; + +use crate::{assembly::ebpf::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// ```text +/// *(u64 *)(r1 + 8) = r2 +/// | | +/// | +-----> Displacement: 8 +/// | +/// +----------> Base: r1 +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Memory { + /// The base register. + /// + /// For `*(u64 *)(r1 + 8)` it would return `r1` + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The displacement value. + /// + /// For `*(u64 *)(r1 + 8)` it would return `8` + pub fn displacement(&self) -> i64 { + self.ptr.displacement() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/pc_relative.rs new file mode 100644 index 0000000..8a50d26 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/pc_relative.rs @@ -0,0 +1,37 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a PC-relative operand. +/// +/// ```text +/// if r1 == 0 goto +5 +/// | +/// v +/// PC Relative operand +/// ``` +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `pc` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/register.rs new file mode 100644 index 0000000..a220f22 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/operands/register.rs @@ -0,0 +1,41 @@ +use lief_ffi as ffi; + +use crate::assembly::ebpf::registers::Reg; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// For instance: +/// +/// ```text +/// r0 = r1 +/// | | +/// | +---------> Register(r1) +/// | +/// +--------------> Register(r0) +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_ebpf_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Register { + /// The effective register wrapped by this operand + pub fn value(&self) -> Reg { + Reg::from(self.ptr.value()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/registers.rs new file mode 100644 index 0000000..a6705e4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/ebpf/registers.rs @@ -0,0 +1,65 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + W0, + W1, + W2, + W3, + W4, + W5, + W6, + W7, + W8, + W9, + W10, + W11, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::R0, + 2 => Reg::R1, + 3 => Reg::R2, + 4 => Reg::R3, + 5 => Reg::R4, + 6 => Reg::R5, + 7 => Reg::R6, + 8 => Reg::R7, + 9 => Reg::R8, + 10 => Reg::R9, + 11 => Reg::R10, + 12 => Reg::R11, + 13 => Reg::W0, + 14 => Reg::W1, + 15 => Reg::W2, + 16 => Reg::W3, + 17 => Reg::W4, + 18 => Reg::W5, + 19 => Reg::W6, + 20 => Reg::W7, + 21 => Reg::W8, + 22 => Reg::W9, + 23 => Reg::W10, + 24 => Reg::W11, + 25 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/instruction.rs new file mode 100644 index 0000000..c9685ba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/instruction.rs @@ -0,0 +1,297 @@ +//! Module related to assembly instructions + +use lief_ffi as ffi; + +use bitflags::bitflags; + +use crate::to_slice; + +use crate::Error; +use crate::common::FromFFI; +use crate::to_conv_result; + +use super::aarch64; +use super::arm; +use super::ebpf; +use super::mips; +use super::powerpc; +use super::riscv; +use super::x86; + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct MemoryAccess: u64 { + const NONE = 0; + const READ = 1 << 0; + const WRITE = 1 << 1; + } +} + +/// This trait is shared by all [`Instructions`] supported by LIEF +pub trait Instruction: std::fmt::Display { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction; + + /// Address of the instruction + fn address(&self) -> u64 { + self.as_generic().address() + } + + /// Size of the instruction in bytes + fn size(&self) -> u64 { + self.as_generic().size() + } + + /// Raw bytes of the current instruction + fn raw(&self) -> &[u8] { + to_slice!(self.as_generic().raw()); + } + + /// Instruction mnemonic (e.g. `br`) + fn mnemonic(&self) -> String { + self.as_generic().mnemonic().to_string() + } + + /// Same as the [`Display`](std::fmt::Display) representation (i.e. + /// [`ToString::to_string`]) but without the address as prefix + fn to_string_no_address(&self) -> String { + self.as_generic().to_string_no_address().to_string() + } + + /// True if the instruction is a call + fn is_call(&self) -> bool { + self.as_generic().is_call() + } + + /// True if the instruction marks the end of a basic block + fn is_terminator(&self) -> bool { + self.as_generic().is_terminator() + } + + /// True if the instruction is a branch + fn is_branch(&self) -> bool { + self.as_generic().is_branch() + } + + /// True if the instruction is a syscall + fn is_syscall(&self) -> bool { + self.as_generic().is_syscall() + } + + /// True if the instruction performs a memory access + fn is_memory_access(&self) -> bool { + self.as_generic().is_memory_access() + } + + /// True if the instruction is a register to register move. + fn is_move_reg(&self) -> bool { + self.as_generic().is_move_reg() + } + + /// True if the instruction performs an arithmetic addition. + fn is_add(&self) -> bool { + self.as_generic().is_add() + } + + /// True if the instruction is a trap. + /// + /// - On `x86/x86-64` this includes the `ud1/ud2` instructions + /// - On `AArch64` this includes the `brk/udf` instructions + fn is_trap(&self) -> bool { + self.as_generic().is_trap() + } + + /// True if the instruction prevents executing the instruction + /// that immediatly follows the current. This includes return + /// or unconditional branch instructions + fn is_barrier(&self) -> bool { + self.as_generic().is_barrier() + } + + /// True if the instruction is a return + fn is_return(&self) -> bool { + self.as_generic().is_return() + } + + /// True if the instruction is and indirect branch. + /// + /// This includes instructions that branch through a register (e.g. `jmp rax`, + /// `br x1`). + fn is_indirect_branch(&self) -> bool { + self.as_generic().is_indirect_branch() + } + + /// True if the instruction is **conditionally** jumping to the next + /// instruction **or** an instruction into some other basic block. + fn is_conditional_branch(&self) -> bool { + self.as_generic().is_conditional_branch() + } + + /// True if the instruction is jumping (**unconditionally**) to some other + /// basic block. + fn is_unconditional_branch(&self) -> bool { + self.as_generic().is_unconditional_branch() + } + + /// True if the instruction is a comparison + fn is_compare(&self) -> bool { + self.as_generic().is_compare() + } + + /// True if the instruction is moving an immediate + fn is_move_immediate(&self) -> bool { + self.as_generic().is_move_immediate() + } + + /// True if the instruction is doing a bitcast + fn is_bitcast(&self) -> bool { + self.as_generic().is_bitcast() + } + + /// Memory access flags + fn memory_access(&self) -> MemoryAccess { + MemoryAccess::from_bits_truncate(self.as_generic().memory_access()) + } + + /// Given a [`Instruction::is_branch`] instruction, try to evaluate the address of the + /// destination. + fn branch_target(&self) -> Result { + to_conv_result!( + ffi::asm_Instruction::branch_target, + self.as_generic(), + |value| value + ); + } +} + +/// All instruction variants supported by LIEF +pub enum Instructions { + /// An AArch64 instruction + AArch64(aarch64::Instruction), + + /// A x86/x86-64 instruction + X86(x86::Instruction), + + /// An ARM/thumb instruction + ARM(arm::Instruction), + + /// An eBPF instruction + EBPF(ebpf::Instruction), + + /// A PowerPC (ppc64/ppc32) instruction + PowerPC(powerpc::Instruction), + + /// A Mips (mips32/mips64) instruction + Mips(mips::Instruction), + + /// A RISC-V (32 or 64 bit) instruction + RiscV(riscv::Instruction), + + /// A generic instruction that doesn't have an extended structure + Generic(Generic), +} + +impl FromFFI for Instructions { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let inst_ref = ptr.as_ref().unwrap(); + if ffi::asm_aarch64_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::AArch64(aarch64::Instruction::from_ffi(raw)); + } else if ffi::asm_x86_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::X86(x86::Instruction::from_ffi(raw)); + } else if ffi::asm_arm_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::ARM(arm::Instruction::from_ffi(raw)); + } else if ffi::asm_mips_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::Mips(mips::Instruction::from_ffi(raw)); + } else if ffi::asm_powerpc_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::PowerPC(powerpc::Instruction::from_ffi(raw)); + } else if ffi::asm_riscv_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::RiscV(riscv::Instruction::from_ffi(raw)); + } else if ffi::asm_ebpf_Instruction::classof(inst_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Instructions::EBPF(ebpf::Instruction::from_ffi(raw)); + } + Instructions::Generic(Generic::from_ffi(ptr)) + } + } +} + +impl Instruction for Instructions { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + match &self { + Instructions::Generic(inst) => inst.as_generic(), + Instructions::AArch64(inst) => inst.as_generic(), + Instructions::X86(inst) => inst.as_generic(), + Instructions::ARM(inst) => inst.as_generic(), + Instructions::Mips(inst) => inst.as_generic(), + Instructions::PowerPC(inst) => inst.as_generic(), + Instructions::EBPF(inst) => inst.as_generic(), + Instructions::RiscV(inst) => inst.as_generic(), + } + } +} + +impl std::fmt::Display for Instructions { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +/// Generic Instruction +pub struct Generic { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Generic { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Instruction for Generic { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap() + } +} + +impl std::fmt::Display for Generic { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips.rs new file mode 100644 index 0000000..53fb620 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips.rs @@ -0,0 +1,18 @@ +//! Mips architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/instruction.rs new file mode 100644 index 0000000..3dc0b7c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/instruction.rs @@ -0,0 +1,52 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +use crate::assembly::mips; +use crate::declare_fwd_iterator; + +/// This structure represents a Mips instruction (including mips64, mips32) +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`mips::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } +} + +declare_fwd_iterator!( + Operands, + mips::Operands, + ffi::asm_Instruction, + ffi::asm_mips_Operand, + ffi::asm_mips_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/opcodes.rs new file mode 100644 index 0000000..87efd95 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/opcodes.rs @@ -0,0 +1,5855 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ABSMacro, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + AND_V_D_PSEUDO, + AND_V_H_PSEUDO, + AND_V_W_PSEUDO, + ATOMIC_CMP_SWAP_I16, + ATOMIC_CMP_SWAP_I16_POSTRA, + ATOMIC_CMP_SWAP_I32, + ATOMIC_CMP_SWAP_I32_POSTRA, + ATOMIC_CMP_SWAP_I64, + ATOMIC_CMP_SWAP_I64_POSTRA, + ATOMIC_CMP_SWAP_I8, + ATOMIC_CMP_SWAP_I8_POSTRA, + ATOMIC_LOAD_ADD_I16, + ATOMIC_LOAD_ADD_I16_POSTRA, + ATOMIC_LOAD_ADD_I32, + ATOMIC_LOAD_ADD_I32_POSTRA, + ATOMIC_LOAD_ADD_I64, + ATOMIC_LOAD_ADD_I64_POSTRA, + ATOMIC_LOAD_ADD_I8, + ATOMIC_LOAD_ADD_I8_POSTRA, + ATOMIC_LOAD_AND_I16, + ATOMIC_LOAD_AND_I16_POSTRA, + ATOMIC_LOAD_AND_I32, + ATOMIC_LOAD_AND_I32_POSTRA, + ATOMIC_LOAD_AND_I64, + ATOMIC_LOAD_AND_I64_POSTRA, + ATOMIC_LOAD_AND_I8, + ATOMIC_LOAD_AND_I8_POSTRA, + ATOMIC_LOAD_MAX_I16, + ATOMIC_LOAD_MAX_I16_POSTRA, + ATOMIC_LOAD_MAX_I32, + ATOMIC_LOAD_MAX_I32_POSTRA, + ATOMIC_LOAD_MAX_I64, + ATOMIC_LOAD_MAX_I64_POSTRA, + ATOMIC_LOAD_MAX_I8, + ATOMIC_LOAD_MAX_I8_POSTRA, + ATOMIC_LOAD_MIN_I16, + ATOMIC_LOAD_MIN_I16_POSTRA, + ATOMIC_LOAD_MIN_I32, + ATOMIC_LOAD_MIN_I32_POSTRA, + ATOMIC_LOAD_MIN_I64, + ATOMIC_LOAD_MIN_I64_POSTRA, + ATOMIC_LOAD_MIN_I8, + ATOMIC_LOAD_MIN_I8_POSTRA, + ATOMIC_LOAD_NAND_I16, + ATOMIC_LOAD_NAND_I16_POSTRA, + ATOMIC_LOAD_NAND_I32, + ATOMIC_LOAD_NAND_I32_POSTRA, + ATOMIC_LOAD_NAND_I64, + ATOMIC_LOAD_NAND_I64_POSTRA, + ATOMIC_LOAD_NAND_I8, + ATOMIC_LOAD_NAND_I8_POSTRA, + ATOMIC_LOAD_OR_I16, + ATOMIC_LOAD_OR_I16_POSTRA, + ATOMIC_LOAD_OR_I32, + ATOMIC_LOAD_OR_I32_POSTRA, + ATOMIC_LOAD_OR_I64, + ATOMIC_LOAD_OR_I64_POSTRA, + ATOMIC_LOAD_OR_I8, + ATOMIC_LOAD_OR_I8_POSTRA, + ATOMIC_LOAD_SUB_I16, + ATOMIC_LOAD_SUB_I16_POSTRA, + ATOMIC_LOAD_SUB_I32, + ATOMIC_LOAD_SUB_I32_POSTRA, + ATOMIC_LOAD_SUB_I64, + ATOMIC_LOAD_SUB_I64_POSTRA, + ATOMIC_LOAD_SUB_I8, + ATOMIC_LOAD_SUB_I8_POSTRA, + ATOMIC_LOAD_UMAX_I16, + ATOMIC_LOAD_UMAX_I16_POSTRA, + ATOMIC_LOAD_UMAX_I32, + ATOMIC_LOAD_UMAX_I32_POSTRA, + ATOMIC_LOAD_UMAX_I64, + ATOMIC_LOAD_UMAX_I64_POSTRA, + ATOMIC_LOAD_UMAX_I8, + ATOMIC_LOAD_UMAX_I8_POSTRA, + ATOMIC_LOAD_UMIN_I16, + ATOMIC_LOAD_UMIN_I16_POSTRA, + ATOMIC_LOAD_UMIN_I32, + ATOMIC_LOAD_UMIN_I32_POSTRA, + ATOMIC_LOAD_UMIN_I64, + ATOMIC_LOAD_UMIN_I64_POSTRA, + ATOMIC_LOAD_UMIN_I8, + ATOMIC_LOAD_UMIN_I8_POSTRA, + ATOMIC_LOAD_XOR_I16, + ATOMIC_LOAD_XOR_I16_POSTRA, + ATOMIC_LOAD_XOR_I32, + ATOMIC_LOAD_XOR_I32_POSTRA, + ATOMIC_LOAD_XOR_I64, + ATOMIC_LOAD_XOR_I64_POSTRA, + ATOMIC_LOAD_XOR_I8, + ATOMIC_LOAD_XOR_I8_POSTRA, + ATOMIC_SWAP_I16, + ATOMIC_SWAP_I16_POSTRA, + ATOMIC_SWAP_I32, + ATOMIC_SWAP_I32_POSTRA, + ATOMIC_SWAP_I64, + ATOMIC_SWAP_I64_POSTRA, + ATOMIC_SWAP_I8, + ATOMIC_SWAP_I8_POSTRA, + B, + BAL_BR, + BAL_BR_MM, + BEQLImmMacro, + BGE, + BGEImmMacro, + BGEL, + BGELImmMacro, + BGEU, + BGEUImmMacro, + BGEUL, + BGEULImmMacro, + BGT, + BGTImmMacro, + BGTL, + BGTLImmMacro, + BGTU, + BGTUImmMacro, + BGTUL, + BGTULImmMacro, + BLE, + BLEImmMacro, + BLEL, + BLELImmMacro, + BLEU, + BLEUImmMacro, + BLEUL, + BLEULImmMacro, + BLT, + BLTImmMacro, + BLTL, + BLTLImmMacro, + BLTU, + BLTUImmMacro, + BLTUL, + BLTULImmMacro, + BNELImmMacro, + BPOSGE32_PSEUDO, + BSEL_D_PSEUDO, + BSEL_FD_PSEUDO, + BSEL_FW_PSEUDO, + BSEL_H_PSEUDO, + BSEL_W_PSEUDO, + B_MM, + B_MMR6_Pseudo, + B_MM_Pseudo, + BeqImm, + BneImm, + BteqzT8CmpX16, + BteqzT8CmpiX16, + BteqzT8SltX16, + BteqzT8SltiX16, + BteqzT8SltiuX16, + BteqzT8SltuX16, + BtnezT8CmpX16, + BtnezT8CmpiX16, + BtnezT8SltX16, + BtnezT8SltiX16, + BtnezT8SltiuX16, + BtnezT8SltuX16, + BuildPairF64, + BuildPairF64_64, + CFTC1, + CONSTPOOL_ENTRY, + COPY_FD_PSEUDO, + COPY_FW_PSEUDO, + CTTC1, + Constant32, + DMULImmMacro, + DMULMacro, + DMULOMacro, + DMULOUMacro, + DROL, + DROLImm, + DROR, + DRORImm, + DSDivIMacro, + DSDivMacro, + DSRemIMacro, + DSRemMacro, + DUDivIMacro, + DUDivMacro, + DURemIMacro, + DURemMacro, + ERet, + ExtractElementF64, + ExtractElementF64_64, + FABS_D, + FABS_W, + FEXP2_D_1_PSEUDO, + FEXP2_W_1_PSEUDO, + FILL_FD_PSEUDO, + FILL_FW_PSEUDO, + GotPrologue16, + INSERT_B_VIDX64_PSEUDO, + INSERT_B_VIDX_PSEUDO, + INSERT_D_VIDX64_PSEUDO, + INSERT_D_VIDX_PSEUDO, + INSERT_FD_PSEUDO, + INSERT_FD_VIDX64_PSEUDO, + INSERT_FD_VIDX_PSEUDO, + INSERT_FW_PSEUDO, + INSERT_FW_VIDX64_PSEUDO, + INSERT_FW_VIDX_PSEUDO, + INSERT_H_VIDX64_PSEUDO, + INSERT_H_VIDX_PSEUDO, + INSERT_W_VIDX64_PSEUDO, + INSERT_W_VIDX_PSEUDO, + JALR64Pseudo, + JALRHB64Pseudo, + JALRHBPseudo, + JALRPseudo, + JAL_MMR6, + JalOneReg, + JalTwoReg, + LDMacro, + LDR_D, + LDR_W, + LD_F16, + LOAD_ACC128, + LOAD_ACC64, + LOAD_ACC64DSP, + LOAD_CCOND_DSP, + LONG_BRANCH_ADDiu, + LONG_BRANCH_ADDiu2Op, + LONG_BRANCH_DADDiu, + LONG_BRANCH_DADDiu2Op, + LONG_BRANCH_LUi, + LONG_BRANCH_LUi2Op, + LONG_BRANCH_LUi2Op_64, + LWM_MM, + LoadAddrImm32, + LoadAddrImm64, + LoadAddrReg32, + LoadAddrReg64, + LoadImm32, + LoadImm64, + LoadImmDoubleFGR, + LoadImmDoubleFGR_32, + LoadImmDoubleGPR, + LoadImmSingleFGR, + LoadImmSingleGPR, + LwConstant32, + MFTACX, + MFTC0, + MFTC1, + MFTDSP, + MFTGPR, + MFTHC1, + MFTHI, + MFTLO, + MIPSeh_return32, + MIPSeh_return64, + MSA_FP_EXTEND_D_PSEUDO, + MSA_FP_EXTEND_W_PSEUDO, + MSA_FP_ROUND_D_PSEUDO, + MSA_FP_ROUND_W_PSEUDO, + MTTACX, + MTTC0, + MTTC1, + MTTDSP, + MTTGPR, + MTTHC1, + MTTHI, + MTTLO, + MULImmMacro, + MULOMacro, + MULOUMacro, + MultRxRy16, + MultRxRyRz16, + MultuRxRy16, + MultuRxRyRz16, + NOP, + NORImm, + NORImm64, + NOR_V_D_PSEUDO, + NOR_V_H_PSEUDO, + NOR_V_W_PSEUDO, + OR_V_D_PSEUDO, + OR_V_H_PSEUDO, + OR_V_W_PSEUDO, + PseudoCMPU_EQ_QB, + PseudoCMPU_LE_QB, + PseudoCMPU_LT_QB, + PseudoCMP_EQ_PH, + PseudoCMP_LE_PH, + PseudoCMP_LT_PH, + PseudoCVT_D32_W, + PseudoCVT_D64_L, + PseudoCVT_D64_W, + PseudoCVT_S_L, + PseudoCVT_S_W, + PseudoDMULT, + PseudoDMULTu, + PseudoDSDIV, + PseudoDUDIV, + PseudoD_SELECT_I, + PseudoD_SELECT_I64, + PseudoIndirectBranch, + PseudoIndirectBranch64, + PseudoIndirectBranch64R6, + PseudoIndirectBranchR6, + PseudoIndirectBranch_MM, + PseudoIndirectBranch_MMR6, + PseudoIndirectHazardBranch, + PseudoIndirectHazardBranch64, + PseudoIndrectHazardBranch64R6, + PseudoIndrectHazardBranchR6, + PseudoMADD, + PseudoMADDU, + PseudoMADDU_MM, + PseudoMADD_MM, + PseudoMFHI, + PseudoMFHI64, + PseudoMFHI_MM, + PseudoMFLO, + PseudoMFLO64, + PseudoMFLO_MM, + PseudoMSUB, + PseudoMSUBU, + PseudoMSUBU_MM, + PseudoMSUB_MM, + PseudoMTLOHI, + PseudoMTLOHI64, + PseudoMTLOHI_DSP, + PseudoMTLOHI_MM, + PseudoMULT, + PseudoMULT_MM, + PseudoMULTu, + PseudoMULTu_MM, + PseudoPICK_PH, + PseudoPICK_QB, + PseudoReturn, + PseudoReturn64, + PseudoSDIV, + PseudoSELECTFP_F_D32, + PseudoSELECTFP_F_D64, + PseudoSELECTFP_F_I, + PseudoSELECTFP_F_I64, + PseudoSELECTFP_F_S, + PseudoSELECTFP_T_D32, + PseudoSELECTFP_T_D64, + PseudoSELECTFP_T_I, + PseudoSELECTFP_T_I64, + PseudoSELECTFP_T_S, + PseudoSELECT_D32, + PseudoSELECT_D64, + PseudoSELECT_I, + PseudoSELECT_I64, + PseudoSELECT_S, + PseudoTRUNC_W_D, + PseudoTRUNC_W_D32, + PseudoTRUNC_W_S, + PseudoUDIV, + ROL, + ROLImm, + ROR, + RORImm, + RetRA, + RetRA16, + SDC1_M1, + SDIV_MM_Pseudo, + SDMacro, + SDivIMacro, + SDivMacro, + SEQIMacro, + SEQMacro, + SGE, + SGEImm, + SGEImm64, + SGEU, + SGEUImm, + SGEUImm64, + SGTImm, + SGTImm64, + SGTUImm, + SGTUImm64, + SLE, + SLEImm, + SLEImm64, + SLEU, + SLEUImm, + SLEUImm64, + SLTImm64, + SLTUImm64, + SNEIMacro, + SNEMacro, + SNZ_B_PSEUDO, + SNZ_D_PSEUDO, + SNZ_H_PSEUDO, + SNZ_V_PSEUDO, + SNZ_W_PSEUDO, + SRemIMacro, + SRemMacro, + STORE_ACC128, + STORE_ACC64, + STORE_ACC64DSP, + STORE_CCOND_DSP, + STR_D, + STR_W, + ST_F16, + SWM_MM, + SZ_B_PSEUDO, + SZ_D_PSEUDO, + SZ_H_PSEUDO, + SZ_V_PSEUDO, + SZ_W_PSEUDO, + SaaAddr, + SaadAddr, + SelBeqZ, + SelBneZ, + SelTBteqZCmp, + SelTBteqZCmpi, + SelTBteqZSlt, + SelTBteqZSlti, + SelTBteqZSltiu, + SelTBteqZSltu, + SelTBtneZCmp, + SelTBtneZCmpi, + SelTBtneZSlt, + SelTBtneZSlti, + SelTBtneZSltiu, + SelTBtneZSltu, + SltCCRxRy16, + SltiCCRxImmX16, + SltiuCCRxImmX16, + SltuCCRxRy16, + SltuRxRyRz16, + TAILCALL, + TAILCALL64R6REG, + TAILCALLHB64R6REG, + TAILCALLHBR6REG, + TAILCALLR6REG, + TAILCALLREG, + TAILCALLREG64, + TAILCALLREGHB, + TAILCALLREGHB64, + TAILCALLREG_MM, + TAILCALLREG_MMR6, + TAILCALL_MM, + TAILCALL_MMR6, + TRAP, + TRAP_MM, + UDIV_MM_Pseudo, + UDivIMacro, + UDivMacro, + URemIMacro, + URemMacro, + Ulh, + Ulhu, + Ulw, + Ush, + Usw, + XOR_V_D_PSEUDO, + XOR_V_H_PSEUDO, + XOR_V_W_PSEUDO, + ABSQ_S_PH, + ABSQ_S_PH_MM, + ABSQ_S_QB, + ABSQ_S_QB_MMR2, + ABSQ_S_W, + ABSQ_S_W_MM, + ADD, + ADDIUPC, + ADDIUPC_MM, + ADDIUPC_MMR6, + ADDIUR1SP_MM, + ADDIUR2_MM, + ADDIUS5_MM, + ADDIUSP_MM, + ADDIU_MMR6, + ADDQH_PH, + ADDQH_PH_MMR2, + ADDQH_R_PH, + ADDQH_R_PH_MMR2, + ADDQH_R_W, + ADDQH_R_W_MMR2, + ADDQH_W, + ADDQH_W_MMR2, + ADDQ_PH, + ADDQ_PH_MM, + ADDQ_S_PH, + ADDQ_S_PH_MM, + ADDQ_S_W, + ADDQ_S_W_MM, + ADDR_PS64, + ADDSC, + ADDSC_MM, + ADDS_A_B, + ADDS_A_D, + ADDS_A_H, + ADDS_A_W, + ADDS_S_B, + ADDS_S_D, + ADDS_S_H, + ADDS_S_W, + ADDS_U_B, + ADDS_U_D, + ADDS_U_H, + ADDS_U_W, + ADDU16_MM, + ADDU16_MMR6, + ADDUH_QB, + ADDUH_QB_MMR2, + ADDUH_R_QB, + ADDUH_R_QB_MMR2, + ADDU_MMR6, + ADDU_PH, + ADDU_PH_MMR2, + ADDU_QB, + ADDU_QB_MM, + ADDU_S_PH, + ADDU_S_PH_MMR2, + ADDU_S_QB, + ADDU_S_QB_MM, + ADDVI_B, + ADDVI_D, + ADDVI_H, + ADDVI_W, + ADDV_B, + ADDV_D, + ADDV_H, + ADDV_W, + ADDWC, + ADDWC_MM, + ADD_A_B, + ADD_A_D, + ADD_A_H, + ADD_A_W, + ADD_MM, + ADD_MMR6, + ADDi, + ADDi_MM, + ADDiu, + ADDiu_MM, + ADDu, + ADDu_MM, + ALIGN, + ALIGN_MMR6, + ALUIPC, + ALUIPC_MMR6, + AND, + AND16_MM, + AND16_MMR6, + AND64, + ANDI16_MM, + ANDI16_MMR6, + ANDI_B, + ANDI_MMR6, + AND_MM, + AND_MMR6, + AND_V, + ANDi, + ANDi64, + ANDi_MM, + APPEND, + APPEND_MMR2, + ASUB_S_B, + ASUB_S_D, + ASUB_S_H, + ASUB_S_W, + ASUB_U_B, + ASUB_U_D, + ASUB_U_H, + ASUB_U_W, + AUI, + AUIPC, + AUIPC_MMR6, + AUI_MMR6, + AVER_S_B, + AVER_S_D, + AVER_S_H, + AVER_S_W, + AVER_U_B, + AVER_U_D, + AVER_U_H, + AVER_U_W, + AVE_S_B, + AVE_S_D, + AVE_S_H, + AVE_S_W, + AVE_U_B, + AVE_U_D, + AVE_U_H, + AVE_U_W, + AddiuRxImmX16, + AddiuRxPcImmX16, + AddiuRxRxImm16, + AddiuRxRxImmX16, + AddiuRxRyOffMemX16, + AddiuSpImm16, + AddiuSpImmX16, + AdduRxRyRz16, + AndRxRxRy16, + B16_MM, + BADDu, + BAL, + BALC, + BALC_MMR6, + BALIGN, + BALIGN_MMR2, + BBIT0, + BBIT032, + BBIT1, + BBIT132, + BC, + BC16_MMR6, + BC1EQZ, + BC1EQZC_MMR6, + BC1F, + BC1FL, + BC1F_MM, + BC1NEZ, + BC1NEZC_MMR6, + BC1T, + BC1TL, + BC1T_MM, + BC2EQZ, + BC2EQZC_MMR6, + BC2NEZ, + BC2NEZC_MMR6, + BCLRI_B, + BCLRI_D, + BCLRI_H, + BCLRI_W, + BCLR_B, + BCLR_D, + BCLR_H, + BCLR_W, + BC_MMR6, + BEQ, + BEQ64, + BEQC, + BEQC64, + BEQC_MMR6, + BEQL, + BEQZ16_MM, + BEQZALC, + BEQZALC_MMR6, + BEQZC, + BEQZC16_MMR6, + BEQZC64, + BEQZC_MM, + BEQZC_MMR6, + BEQ_MM, + BGEC, + BGEC64, + BGEC_MMR6, + BGEUC, + BGEUC64, + BGEUC_MMR6, + BGEZ, + BGEZ64, + BGEZAL, + BGEZALC, + BGEZALC_MMR6, + BGEZALL, + BGEZALS_MM, + BGEZAL_MM, + BGEZC, + BGEZC64, + BGEZC_MMR6, + BGEZL, + BGEZ_MM, + BGTZ, + BGTZ64, + BGTZALC, + BGTZALC_MMR6, + BGTZC, + BGTZC64, + BGTZC_MMR6, + BGTZL, + BGTZ_MM, + BINSLI_B, + BINSLI_D, + BINSLI_H, + BINSLI_W, + BINSL_B, + BINSL_D, + BINSL_H, + BINSL_W, + BINSRI_B, + BINSRI_D, + BINSRI_H, + BINSRI_W, + BINSR_B, + BINSR_D, + BINSR_H, + BINSR_W, + BITREV, + BITREV_MM, + BITSWAP, + BITSWAP_MMR6, + BLEZ, + BLEZ64, + BLEZALC, + BLEZALC_MMR6, + BLEZC, + BLEZC64, + BLEZC_MMR6, + BLEZL, + BLEZ_MM, + BLTC, + BLTC64, + BLTC_MMR6, + BLTUC, + BLTUC64, + BLTUC_MMR6, + BLTZ, + BLTZ64, + BLTZAL, + BLTZALC, + BLTZALC_MMR6, + BLTZALL, + BLTZALS_MM, + BLTZAL_MM, + BLTZC, + BLTZC64, + BLTZC_MMR6, + BLTZL, + BLTZ_MM, + BMNZI_B, + BMNZ_V, + BMZI_B, + BMZ_V, + BNE, + BNE64, + BNEC, + BNEC64, + BNEC_MMR6, + BNEGI_B, + BNEGI_D, + BNEGI_H, + BNEGI_W, + BNEG_B, + BNEG_D, + BNEG_H, + BNEG_W, + BNEL, + BNEZ16_MM, + BNEZALC, + BNEZALC_MMR6, + BNEZC, + BNEZC16_MMR6, + BNEZC64, + BNEZC_MM, + BNEZC_MMR6, + BNE_MM, + BNVC, + BNVC_MMR6, + BNZ_B, + BNZ_D, + BNZ_H, + BNZ_V, + BNZ_W, + BOVC, + BOVC_MMR6, + BPOSGE32, + BPOSGE32C_MMR3, + BPOSGE32_MM, + BREAK, + BREAK16_MM, + BREAK16_MMR6, + BREAK_MM, + BREAK_MMR6, + BSELI_B, + BSEL_V, + BSETI_B, + BSETI_D, + BSETI_H, + BSETI_W, + BSET_B, + BSET_D, + BSET_H, + BSET_W, + BZ_B, + BZ_D, + BZ_H, + BZ_V, + BZ_W, + BeqzRxImm16, + BeqzRxImmX16, + Bimm16, + BimmX16, + BnezRxImm16, + BnezRxImmX16, + Break16, + Bteqz16, + BteqzX16, + Btnez16, + BtnezX16, + CACHE, + CACHEE, + CACHEE_MM, + CACHE_MM, + CACHE_MMR6, + CACHE_R6, + CEIL_L_D64, + CEIL_L_D_MMR6, + CEIL_L_S, + CEIL_L_S_MMR6, + CEIL_W_D32, + CEIL_W_D64, + CEIL_W_D_MMR6, + CEIL_W_MM, + CEIL_W_S, + CEIL_W_S_MM, + CEIL_W_S_MMR6, + CEQI_B, + CEQI_D, + CEQI_H, + CEQI_W, + CEQ_B, + CEQ_D, + CEQ_H, + CEQ_W, + CFC1, + CFC1_MM, + CFC2_MM, + CFCMSA, + CINS, + CINS32, + CINS64_32, + CINS_i32, + CLASS_D, + CLASS_D_MMR6, + CLASS_S, + CLASS_S_MMR6, + CLEI_S_B, + CLEI_S_D, + CLEI_S_H, + CLEI_S_W, + CLEI_U_B, + CLEI_U_D, + CLEI_U_H, + CLEI_U_W, + CLE_S_B, + CLE_S_D, + CLE_S_H, + CLE_S_W, + CLE_U_B, + CLE_U_D, + CLE_U_H, + CLE_U_W, + CLO, + CLO_MM, + CLO_MMR6, + CLO_R6, + CLTI_S_B, + CLTI_S_D, + CLTI_S_H, + CLTI_S_W, + CLTI_U_B, + CLTI_U_D, + CLTI_U_H, + CLTI_U_W, + CLT_S_B, + CLT_S_D, + CLT_S_H, + CLT_S_W, + CLT_U_B, + CLT_U_D, + CLT_U_H, + CLT_U_W, + CLZ, + CLZ_MM, + CLZ_MMR6, + CLZ_R6, + CMPGDU_EQ_QB, + CMPGDU_EQ_QB_MMR2, + CMPGDU_LE_QB, + CMPGDU_LE_QB_MMR2, + CMPGDU_LT_QB, + CMPGDU_LT_QB_MMR2, + CMPGU_EQ_QB, + CMPGU_EQ_QB_MM, + CMPGU_LE_QB, + CMPGU_LE_QB_MM, + CMPGU_LT_QB, + CMPGU_LT_QB_MM, + CMPU_EQ_QB, + CMPU_EQ_QB_MM, + CMPU_LE_QB, + CMPU_LE_QB_MM, + CMPU_LT_QB, + CMPU_LT_QB_MM, + CMP_AF_D_MMR6, + CMP_AF_S_MMR6, + CMP_EQ_D, + CMP_EQ_D_MMR6, + CMP_EQ_PH, + CMP_EQ_PH_MM, + CMP_EQ_S, + CMP_EQ_S_MMR6, + CMP_F_D, + CMP_F_S, + CMP_LE_D, + CMP_LE_D_MMR6, + CMP_LE_PH, + CMP_LE_PH_MM, + CMP_LE_S, + CMP_LE_S_MMR6, + CMP_LT_D, + CMP_LT_D_MMR6, + CMP_LT_PH, + CMP_LT_PH_MM, + CMP_LT_S, + CMP_LT_S_MMR6, + CMP_SAF_D, + CMP_SAF_D_MMR6, + CMP_SAF_S, + CMP_SAF_S_MMR6, + CMP_SEQ_D, + CMP_SEQ_D_MMR6, + CMP_SEQ_S, + CMP_SEQ_S_MMR6, + CMP_SLE_D, + CMP_SLE_D_MMR6, + CMP_SLE_S, + CMP_SLE_S_MMR6, + CMP_SLT_D, + CMP_SLT_D_MMR6, + CMP_SLT_S, + CMP_SLT_S_MMR6, + CMP_SUEQ_D, + CMP_SUEQ_D_MMR6, + CMP_SUEQ_S, + CMP_SUEQ_S_MMR6, + CMP_SULE_D, + CMP_SULE_D_MMR6, + CMP_SULE_S, + CMP_SULE_S_MMR6, + CMP_SULT_D, + CMP_SULT_D_MMR6, + CMP_SULT_S, + CMP_SULT_S_MMR6, + CMP_SUN_D, + CMP_SUN_D_MMR6, + CMP_SUN_S, + CMP_SUN_S_MMR6, + CMP_UEQ_D, + CMP_UEQ_D_MMR6, + CMP_UEQ_S, + CMP_UEQ_S_MMR6, + CMP_ULE_D, + CMP_ULE_D_MMR6, + CMP_ULE_S, + CMP_ULE_S_MMR6, + CMP_ULT_D, + CMP_ULT_D_MMR6, + CMP_ULT_S, + CMP_ULT_S_MMR6, + CMP_UN_D, + CMP_UN_D_MMR6, + CMP_UN_S, + CMP_UN_S_MMR6, + COPY_S_B, + COPY_S_D, + COPY_S_H, + COPY_S_W, + COPY_U_B, + COPY_U_H, + COPY_U_W, + CRC32B, + CRC32CB, + CRC32CD, + CRC32CH, + CRC32CW, + CRC32D, + CRC32H, + CRC32W, + CTC1, + CTC1_MM, + CTC2_MM, + CTCMSA, + CVT_D32_S, + CVT_D32_S_MM, + CVT_D32_W, + CVT_D32_W_MM, + CVT_D64_L, + CVT_D64_S, + CVT_D64_S_MM, + CVT_D64_W, + CVT_D64_W_MM, + CVT_D_L_MMR6, + CVT_L_D64, + CVT_L_D64_MM, + CVT_L_D_MMR6, + CVT_L_S, + CVT_L_S_MM, + CVT_L_S_MMR6, + CVT_PS_PW64, + CVT_PS_S64, + CVT_PW_PS64, + CVT_S_D32, + CVT_S_D32_MM, + CVT_S_D64, + CVT_S_D64_MM, + CVT_S_L, + CVT_S_L_MMR6, + CVT_S_PL64, + CVT_S_PU64, + CVT_S_W, + CVT_S_W_MM, + CVT_S_W_MMR6, + CVT_W_D32, + CVT_W_D32_MM, + CVT_W_D64, + CVT_W_D64_MM, + CVT_W_S, + CVT_W_S_MM, + CVT_W_S_MMR6, + C_EQ_D32, + C_EQ_D32_MM, + C_EQ_D64, + C_EQ_D64_MM, + C_EQ_S, + C_EQ_S_MM, + C_F_D32, + C_F_D32_MM, + C_F_D64, + C_F_D64_MM, + C_F_S, + C_F_S_MM, + C_LE_D32, + C_LE_D32_MM, + C_LE_D64, + C_LE_D64_MM, + C_LE_S, + C_LE_S_MM, + C_LT_D32, + C_LT_D32_MM, + C_LT_D64, + C_LT_D64_MM, + C_LT_S, + C_LT_S_MM, + C_NGE_D32, + C_NGE_D32_MM, + C_NGE_D64, + C_NGE_D64_MM, + C_NGE_S, + C_NGE_S_MM, + C_NGLE_D32, + C_NGLE_D32_MM, + C_NGLE_D64, + C_NGLE_D64_MM, + C_NGLE_S, + C_NGLE_S_MM, + C_NGL_D32, + C_NGL_D32_MM, + C_NGL_D64, + C_NGL_D64_MM, + C_NGL_S, + C_NGL_S_MM, + C_NGT_D32, + C_NGT_D32_MM, + C_NGT_D64, + C_NGT_D64_MM, + C_NGT_S, + C_NGT_S_MM, + C_OLE_D32, + C_OLE_D32_MM, + C_OLE_D64, + C_OLE_D64_MM, + C_OLE_S, + C_OLE_S_MM, + C_OLT_D32, + C_OLT_D32_MM, + C_OLT_D64, + C_OLT_D64_MM, + C_OLT_S, + C_OLT_S_MM, + C_SEQ_D32, + C_SEQ_D32_MM, + C_SEQ_D64, + C_SEQ_D64_MM, + C_SEQ_S, + C_SEQ_S_MM, + C_SF_D32, + C_SF_D32_MM, + C_SF_D64, + C_SF_D64_MM, + C_SF_S, + C_SF_S_MM, + C_UEQ_D32, + C_UEQ_D32_MM, + C_UEQ_D64, + C_UEQ_D64_MM, + C_UEQ_S, + C_UEQ_S_MM, + C_ULE_D32, + C_ULE_D32_MM, + C_ULE_D64, + C_ULE_D64_MM, + C_ULE_S, + C_ULE_S_MM, + C_ULT_D32, + C_ULT_D32_MM, + C_ULT_D64, + C_ULT_D64_MM, + C_ULT_S, + C_ULT_S_MM, + C_UN_D32, + C_UN_D32_MM, + C_UN_D64, + C_UN_D64_MM, + C_UN_S, + C_UN_S_MM, + CmpRxRy16, + CmpiRxImm16, + CmpiRxImmX16, + DADD, + DADDi, + DADDiu, + DADDu, + DAHI, + DALIGN, + DATI, + DAUI, + DBITSWAP, + DCLO, + DCLO_R6, + DCLZ, + DCLZ_R6, + DDIV, + DDIVU, + DERET, + DERET_MM, + DERET_MMR6, + DEXT, + DEXT64_32, + DEXTM, + DEXTU, + DI, + DINS, + DINSM, + DINSU, + DIV, + DIVU, + DIVU_MMR6, + DIV_MMR6, + DIV_S_B, + DIV_S_D, + DIV_S_H, + DIV_S_W, + DIV_U_B, + DIV_U_D, + DIV_U_H, + DIV_U_W, + DI_MM, + DI_MMR6, + DLSA, + DLSA_R6, + DMFC0, + DMFC1, + DMFC2, + DMFC2_OCTEON, + DMFGC0, + DMOD, + DMODU, + DMT, + DMTC0, + DMTC1, + DMTC2, + DMTC2_OCTEON, + DMTGC0, + DMUH, + DMUHU, + DMUL, + DMULT, + DMULTu, + DMULU, + DMUL_R6, + DOTP_S_D, + DOTP_S_H, + DOTP_S_W, + DOTP_U_D, + DOTP_U_H, + DOTP_U_W, + DPADD_S_D, + DPADD_S_H, + DPADD_S_W, + DPADD_U_D, + DPADD_U_H, + DPADD_U_W, + DPAQX_SA_W_PH, + DPAQX_SA_W_PH_MMR2, + DPAQX_S_W_PH, + DPAQX_S_W_PH_MMR2, + DPAQ_SA_L_W, + DPAQ_SA_L_W_MM, + DPAQ_S_W_PH, + DPAQ_S_W_PH_MM, + DPAU_H_QBL, + DPAU_H_QBL_MM, + DPAU_H_QBR, + DPAU_H_QBR_MM, + DPAX_W_PH, + DPAX_W_PH_MMR2, + DPA_W_PH, + DPA_W_PH_MMR2, + DPOP, + DPSQX_SA_W_PH, + DPSQX_SA_W_PH_MMR2, + DPSQX_S_W_PH, + DPSQX_S_W_PH_MMR2, + DPSQ_SA_L_W, + DPSQ_SA_L_W_MM, + DPSQ_S_W_PH, + DPSQ_S_W_PH_MM, + DPSUB_S_D, + DPSUB_S_H, + DPSUB_S_W, + DPSUB_U_D, + DPSUB_U_H, + DPSUB_U_W, + DPSU_H_QBL, + DPSU_H_QBL_MM, + DPSU_H_QBR, + DPSU_H_QBR_MM, + DPSX_W_PH, + DPSX_W_PH_MMR2, + DPS_W_PH, + DPS_W_PH_MMR2, + DROTR, + DROTR32, + DROTRV, + DSBH, + DSDIV, + DSHD, + DSLL, + DSLL32, + DSLL64_32, + DSLLV, + DSRA, + DSRA32, + DSRAV, + DSRL, + DSRL32, + DSRLV, + DSUB, + DSUBu, + DUDIV, + DVP, + DVPE, + DVP_MMR6, + DivRxRy16, + DivuRxRy16, + EHB, + EHB_MM, + EHB_MMR6, + EI, + EI_MM, + EI_MMR6, + EMT, + ERET, + ERETNC, + ERETNC_MMR6, + ERET_MM, + ERET_MMR6, + EVP, + EVPE, + EVP_MMR6, + EXT, + EXTP, + EXTPDP, + EXTPDPV, + EXTPDPV_MM, + EXTPDP_MM, + EXTPV, + EXTPV_MM, + EXTP_MM, + EXTRV_RS_W, + EXTRV_RS_W_MM, + EXTRV_R_W, + EXTRV_R_W_MM, + EXTRV_S_H, + EXTRV_S_H_MM, + EXTRV_W, + EXTRV_W_MM, + EXTR_RS_W, + EXTR_RS_W_MM, + EXTR_R_W, + EXTR_R_W_MM, + EXTR_S_H, + EXTR_S_H_MM, + EXTR_W, + EXTR_W_MM, + EXTS, + EXTS32, + EXT_MM, + EXT_MMR6, + FABS_D32, + FABS_D32_MM, + FABS_D64, + FABS_D64_MM, + FABS_S, + FABS_S_MM, + FADD_D, + FADD_D32, + FADD_D32_MM, + FADD_D64, + FADD_D64_MM, + FADD_PS64, + FADD_S, + FADD_S_MM, + FADD_S_MMR6, + FADD_W, + FCAF_D, + FCAF_W, + FCEQ_D, + FCEQ_W, + FCLASS_D, + FCLASS_W, + FCLE_D, + FCLE_W, + FCLT_D, + FCLT_W, + FCMP_D32, + FCMP_D32_MM, + FCMP_D64, + FCMP_S32, + FCMP_S32_MM, + FCNE_D, + FCNE_W, + FCOR_D, + FCOR_W, + FCUEQ_D, + FCUEQ_W, + FCULE_D, + FCULE_W, + FCULT_D, + FCULT_W, + FCUNE_D, + FCUNE_W, + FCUN_D, + FCUN_W, + FDIV_D, + FDIV_D32, + FDIV_D32_MM, + FDIV_D64, + FDIV_D64_MM, + FDIV_S, + FDIV_S_MM, + FDIV_S_MMR6, + FDIV_W, + FEXDO_H, + FEXDO_W, + FEXP2_D, + FEXP2_W, + FEXUPL_D, + FEXUPL_W, + FEXUPR_D, + FEXUPR_W, + FFINT_S_D, + FFINT_S_W, + FFINT_U_D, + FFINT_U_W, + FFQL_D, + FFQL_W, + FFQR_D, + FFQR_W, + FILL_B, + FILL_D, + FILL_H, + FILL_W, + FLOG2_D, + FLOG2_W, + FLOOR_L_D64, + FLOOR_L_D_MMR6, + FLOOR_L_S, + FLOOR_L_S_MMR6, + FLOOR_W_D32, + FLOOR_W_D64, + FLOOR_W_D_MMR6, + FLOOR_W_MM, + FLOOR_W_S, + FLOOR_W_S_MM, + FLOOR_W_S_MMR6, + FMADD_D, + FMADD_W, + FMAX_A_D, + FMAX_A_W, + FMAX_D, + FMAX_W, + FMIN_A_D, + FMIN_A_W, + FMIN_D, + FMIN_W, + FMOV_D32, + FMOV_D32_MM, + FMOV_D64, + FMOV_D64_MM, + FMOV_D_MMR6, + FMOV_S, + FMOV_S_MM, + FMOV_S_MMR6, + FMSUB_D, + FMSUB_W, + FMUL_D, + FMUL_D32, + FMUL_D32_MM, + FMUL_D64, + FMUL_D64_MM, + FMUL_PS64, + FMUL_S, + FMUL_S_MM, + FMUL_S_MMR6, + FMUL_W, + FNEG_D32, + FNEG_D32_MM, + FNEG_D64, + FNEG_D64_MM, + FNEG_S, + FNEG_S_MM, + FNEG_S_MMR6, + FORK, + FRCP_D, + FRCP_W, + FRINT_D, + FRINT_W, + FRSQRT_D, + FRSQRT_W, + FSAF_D, + FSAF_W, + FSEQ_D, + FSEQ_W, + FSLE_D, + FSLE_W, + FSLT_D, + FSLT_W, + FSNE_D, + FSNE_W, + FSOR_D, + FSOR_W, + FSQRT_D, + FSQRT_D32, + FSQRT_D32_MM, + FSQRT_D64, + FSQRT_D64_MM, + FSQRT_S, + FSQRT_S_MM, + FSQRT_W, + FSUB_D, + FSUB_D32, + FSUB_D32_MM, + FSUB_D64, + FSUB_D64_MM, + FSUB_PS64, + FSUB_S, + FSUB_S_MM, + FSUB_S_MMR6, + FSUB_W, + FSUEQ_D, + FSUEQ_W, + FSULE_D, + FSULE_W, + FSULT_D, + FSULT_W, + FSUNE_D, + FSUNE_W, + FSUN_D, + FSUN_W, + FTINT_S_D, + FTINT_S_W, + FTINT_U_D, + FTINT_U_W, + FTQ_H, + FTQ_W, + FTRUNC_S_D, + FTRUNC_S_W, + FTRUNC_U_D, + FTRUNC_U_W, + GINVI, + GINVI_MMR6, + GINVT, + GINVT_MMR6, + HADD_S_D, + HADD_S_H, + HADD_S_W, + HADD_U_D, + HADD_U_H, + HADD_U_W, + HSUB_S_D, + HSUB_S_H, + HSUB_S_W, + HSUB_U_D, + HSUB_U_H, + HSUB_U_W, + HYPCALL, + HYPCALL_MM, + ILVEV_B, + ILVEV_D, + ILVEV_H, + ILVEV_W, + ILVL_B, + ILVL_D, + ILVL_H, + ILVL_W, + ILVOD_B, + ILVOD_D, + ILVOD_H, + ILVOD_W, + ILVR_B, + ILVR_D, + ILVR_H, + ILVR_W, + INS, + INSERT_B, + INSERT_D, + INSERT_H, + INSERT_W, + INSV, + INSVE_B, + INSVE_D, + INSVE_H, + INSVE_W, + INSV_MM, + INS_MM, + INS_MMR6, + J, + JAL, + JALR, + JALR16_MM, + JALR64, + JALRC16_MMR6, + JALRC_HB_MMR6, + JALRC_MMR6, + JALRS16_MM, + JALRS_MM, + JALR_HB, + JALR_HB64, + JALR_MM, + JALS_MM, + JALX, + JALX_MM, + JAL_MM, + JIALC, + JIALC64, + JIALC_MMR6, + JIC, + JIC64, + JIC_MMR6, + JR, + JR16_MM, + JR64, + JRADDIUSP, + JRC16_MM, + JRC16_MMR6, + JRCADDIUSP_MMR6, + JR_HB, + JR_HB64, + JR_HB64_R6, + JR_HB_R6, + JR_MM, + J_MM, + Jal16, + JalB16, + JrRa16, + JrcRa16, + JrcRx16, + JumpLinkReg16, + LB, + LB64, + LBE, + LBE_MM, + LBU16_MM, + LBUX, + LBUX_MM, + LBU_MMR6, + LB_MM, + LB_MMR6, + LBu, + LBu64, + LBuE, + LBuE_MM, + LBu_MM, + LD, + LDC1, + LDC164, + LDC1_D64_MMR6, + LDC1_MM_D32, + LDC1_MM_D64, + LDC2, + LDC2_MMR6, + LDC2_R6, + LDC3, + LDI_B, + LDI_D, + LDI_H, + LDI_W, + LDL, + LDPC, + LDR, + LDXC1, + LDXC164, + LD_B, + LD_D, + LD_H, + LD_W, + LEA_ADDiu, + LEA_ADDiu64, + LEA_ADDiu_MM, + LH, + LH64, + LHE, + LHE_MM, + LHU16_MM, + LHX, + LHX_MM, + LH_MM, + LHu, + LHu64, + LHuE, + LHuE_MM, + LHu_MM, + LI16_MM, + LI16_MMR6, + LL, + LL64, + LL64_R6, + LLD, + LLD_R6, + LLE, + LLE_MM, + LL_MM, + LL_MMR6, + LL_R6, + LSA, + LSA_MMR6, + LSA_R6, + LUI_MMR6, + LUXC1, + LUXC164, + LUXC1_MM, + LUi, + LUi64, + LUi_MM, + LW, + LW16_MM, + LW64, + LWC1, + LWC1_MM, + LWC2, + LWC2_MMR6, + LWC2_R6, + LWC3, + LWDSP, + LWDSP_MM, + LWE, + LWE_MM, + LWGP_MM, + LWL, + LWL64, + LWLE, + LWLE_MM, + LWL_MM, + LWM16_MM, + LWM16_MMR6, + LWM32_MM, + LWPC, + LWPC_MMR6, + LWP_MM, + LWR, + LWR64, + LWRE, + LWRE_MM, + LWR_MM, + LWSP_MM, + LWUPC, + LWU_MM, + LWX, + LWXC1, + LWXC1_MM, + LWXS_MM, + LWX_MM, + LW_MM, + LW_MMR6, + LWu, + LbRxRyOffMemX16, + LbuRxRyOffMemX16, + LhRxRyOffMemX16, + LhuRxRyOffMemX16, + LiRxImm16, + LiRxImmAlignX16, + LiRxImmX16, + LwRxPcTcp16, + LwRxPcTcpX16, + LwRxRyOffMemX16, + LwRxSpImmX16, + MADD, + MADDF_D, + MADDF_D_MMR6, + MADDF_S, + MADDF_S_MMR6, + MADDR_Q_H, + MADDR_Q_W, + MADDU, + MADDU_DSP, + MADDU_DSP_MM, + MADDU_MM, + MADDV_B, + MADDV_D, + MADDV_H, + MADDV_W, + MADD_D32, + MADD_D32_MM, + MADD_D64, + MADD_DSP, + MADD_DSP_MM, + MADD_MM, + MADD_Q_H, + MADD_Q_W, + MADD_S, + MADD_S_MM, + MAQ_SA_W_PHL, + MAQ_SA_W_PHL_MM, + MAQ_SA_W_PHR, + MAQ_SA_W_PHR_MM, + MAQ_S_W_PHL, + MAQ_S_W_PHL_MM, + MAQ_S_W_PHR, + MAQ_S_W_PHR_MM, + MAXA_D, + MAXA_D_MMR6, + MAXA_S, + MAXA_S_MMR6, + MAXI_S_B, + MAXI_S_D, + MAXI_S_H, + MAXI_S_W, + MAXI_U_B, + MAXI_U_D, + MAXI_U_H, + MAXI_U_W, + MAX_A_B, + MAX_A_D, + MAX_A_H, + MAX_A_W, + MAX_D, + MAX_D_MMR6, + MAX_S, + MAX_S_B, + MAX_S_D, + MAX_S_H, + MAX_S_MMR6, + MAX_S_W, + MAX_U_B, + MAX_U_D, + MAX_U_H, + MAX_U_W, + MFC0, + MFC0_MMR6, + MFC1, + MFC1_D64, + MFC1_MM, + MFC1_MMR6, + MFC2, + MFC2_MMR6, + MFGC0, + MFGC0_MM, + MFHC0_MMR6, + MFHC1_D32, + MFHC1_D32_MM, + MFHC1_D64, + MFHC1_D64_MM, + MFHC2_MMR6, + MFHGC0, + MFHGC0_MM, + MFHI, + MFHI16_MM, + MFHI64, + MFHI_DSP, + MFHI_DSP_MM, + MFHI_MM, + MFLO, + MFLO16_MM, + MFLO64, + MFLO_DSP, + MFLO_DSP_MM, + MFLO_MM, + MFTR, + MINA_D, + MINA_D_MMR6, + MINA_S, + MINA_S_MMR6, + MINI_S_B, + MINI_S_D, + MINI_S_H, + MINI_S_W, + MINI_U_B, + MINI_U_D, + MINI_U_H, + MINI_U_W, + MIN_A_B, + MIN_A_D, + MIN_A_H, + MIN_A_W, + MIN_D, + MIN_D_MMR6, + MIN_S, + MIN_S_B, + MIN_S_D, + MIN_S_H, + MIN_S_MMR6, + MIN_S_W, + MIN_U_B, + MIN_U_D, + MIN_U_H, + MIN_U_W, + MOD, + MODSUB, + MODSUB_MM, + MODU, + MODU_MMR6, + MOD_MMR6, + MOD_S_B, + MOD_S_D, + MOD_S_H, + MOD_S_W, + MOD_U_B, + MOD_U_D, + MOD_U_H, + MOD_U_W, + MOVE16_MM, + MOVE16_MMR6, + MOVEP_MM, + MOVEP_MMR6, + MOVE_V, + MOVF_D32, + MOVF_D32_MM, + MOVF_D64, + MOVF_I, + MOVF_I64, + MOVF_I_MM, + MOVF_S, + MOVF_S_MM, + MOVN_I64_D64, + MOVN_I64_I, + MOVN_I64_I64, + MOVN_I64_S, + MOVN_I_D32, + MOVN_I_D32_MM, + MOVN_I_D64, + MOVN_I_I, + MOVN_I_I64, + MOVN_I_MM, + MOVN_I_S, + MOVN_I_S_MM, + MOVT_D32, + MOVT_D32_MM, + MOVT_D64, + MOVT_I, + MOVT_I64, + MOVT_I_MM, + MOVT_S, + MOVT_S_MM, + MOVZ_I64_D64, + MOVZ_I64_I, + MOVZ_I64_I64, + MOVZ_I64_S, + MOVZ_I_D32, + MOVZ_I_D32_MM, + MOVZ_I_D64, + MOVZ_I_I, + MOVZ_I_I64, + MOVZ_I_MM, + MOVZ_I_S, + MOVZ_I_S_MM, + MSUB, + MSUBF_D, + MSUBF_D_MMR6, + MSUBF_S, + MSUBF_S_MMR6, + MSUBR_Q_H, + MSUBR_Q_W, + MSUBU, + MSUBU_DSP, + MSUBU_DSP_MM, + MSUBU_MM, + MSUBV_B, + MSUBV_D, + MSUBV_H, + MSUBV_W, + MSUB_D32, + MSUB_D32_MM, + MSUB_D64, + MSUB_DSP, + MSUB_DSP_MM, + MSUB_MM, + MSUB_Q_H, + MSUB_Q_W, + MSUB_S, + MSUB_S_MM, + MTC0, + MTC0_MMR6, + MTC1, + MTC1_D64, + MTC1_D64_MM, + MTC1_MM, + MTC1_MMR6, + MTC2, + MTC2_MMR6, + MTGC0, + MTGC0_MM, + MTHC0_MMR6, + MTHC1_D32, + MTHC1_D32_MM, + MTHC1_D64, + MTHC1_D64_MM, + MTHC2_MMR6, + MTHGC0, + MTHGC0_MM, + MTHI, + MTHI64, + MTHI_DSP, + MTHI_DSP_MM, + MTHI_MM, + MTHLIP, + MTHLIP_MM, + MTLO, + MTLO64, + MTLO_DSP, + MTLO_DSP_MM, + MTLO_MM, + MTM0, + MTM1, + MTM2, + MTP0, + MTP1, + MTP2, + MTTR, + MUH, + MUHU, + MUHU_MMR6, + MUH_MMR6, + MUL, + MULEQ_S_W_PHL, + MULEQ_S_W_PHL_MM, + MULEQ_S_W_PHR, + MULEQ_S_W_PHR_MM, + MULEU_S_PH_QBL, + MULEU_S_PH_QBL_MM, + MULEU_S_PH_QBR, + MULEU_S_PH_QBR_MM, + MULQ_RS_PH, + MULQ_RS_PH_MM, + MULQ_RS_W, + MULQ_RS_W_MMR2, + MULQ_S_PH, + MULQ_S_PH_MMR2, + MULQ_S_W, + MULQ_S_W_MMR2, + MULR_PS64, + MULR_Q_H, + MULR_Q_W, + MULSAQ_S_W_PH, + MULSAQ_S_W_PH_MM, + MULSA_W_PH, + MULSA_W_PH_MMR2, + MULT, + MULTU_DSP, + MULTU_DSP_MM, + MULT_DSP, + MULT_DSP_MM, + MULT_MM, + MULTu, + MULTu_MM, + MULU, + MULU_MMR6, + MULV_B, + MULV_D, + MULV_H, + MULV_W, + MUL_MM, + MUL_MMR6, + MUL_PH, + MUL_PH_MMR2, + MUL_Q_H, + MUL_Q_W, + MUL_R6, + MUL_S_PH, + MUL_S_PH_MMR2, + Mfhi16, + Mflo16, + Move32R16, + MoveR3216, + NAL, + NLOC_B, + NLOC_D, + NLOC_H, + NLOC_W, + NLZC_B, + NLZC_D, + NLZC_H, + NLZC_W, + NMADD_D32, + NMADD_D32_MM, + NMADD_D64, + NMADD_S, + NMADD_S_MM, + NMSUB_D32, + NMSUB_D32_MM, + NMSUB_D64, + NMSUB_S, + NMSUB_S_MM, + NOR, + NOR64, + NORI_B, + NOR_MM, + NOR_MMR6, + NOR_V, + NOT16_MM, + NOT16_MMR6, + NegRxRy16, + NotRxRy16, + OR, + OR16_MM, + OR16_MMR6, + OR64, + ORI_B, + ORI_MMR6, + OR_MM, + OR_MMR6, + OR_V, + ORi, + ORi64, + ORi_MM, + OrRxRxRy16, + PACKRL_PH, + PACKRL_PH_MM, + PAUSE, + PAUSE_MM, + PAUSE_MMR6, + PCKEV_B, + PCKEV_D, + PCKEV_H, + PCKEV_W, + PCKOD_B, + PCKOD_D, + PCKOD_H, + PCKOD_W, + PCNT_B, + PCNT_D, + PCNT_H, + PCNT_W, + PICK_PH, + PICK_PH_MM, + PICK_QB, + PICK_QB_MM, + PLL_PS64, + PLU_PS64, + POP, + PRECEQU_PH_QBL, + PRECEQU_PH_QBLA, + PRECEQU_PH_QBLA_MM, + PRECEQU_PH_QBL_MM, + PRECEQU_PH_QBR, + PRECEQU_PH_QBRA, + PRECEQU_PH_QBRA_MM, + PRECEQU_PH_QBR_MM, + PRECEQ_W_PHL, + PRECEQ_W_PHL_MM, + PRECEQ_W_PHR, + PRECEQ_W_PHR_MM, + PRECEU_PH_QBL, + PRECEU_PH_QBLA, + PRECEU_PH_QBLA_MM, + PRECEU_PH_QBL_MM, + PRECEU_PH_QBR, + PRECEU_PH_QBRA, + PRECEU_PH_QBRA_MM, + PRECEU_PH_QBR_MM, + PRECRQU_S_QB_PH, + PRECRQU_S_QB_PH_MM, + PRECRQ_PH_W, + PRECRQ_PH_W_MM, + PRECRQ_QB_PH, + PRECRQ_QB_PH_MM, + PRECRQ_RS_PH_W, + PRECRQ_RS_PH_W_MM, + PRECR_QB_PH, + PRECR_QB_PH_MMR2, + PRECR_SRA_PH_W, + PRECR_SRA_PH_W_MMR2, + PRECR_SRA_R_PH_W, + PRECR_SRA_R_PH_W_MMR2, + PREF, + PREFE, + PREFE_MM, + PREFX_MM, + PREF_MM, + PREF_MMR6, + PREF_R6, + PREPEND, + PREPEND_MMR2, + PUL_PS64, + PUU_PS64, + RADDU_W_QB, + RADDU_W_QB_MM, + RDDSP, + RDDSP_MM, + RDHWR, + RDHWR64, + RDHWR_MM, + RDHWR_MMR6, + RDPGPR_MMR6, + RECIP_D32, + RECIP_D32_MM, + RECIP_D64, + RECIP_D64_MM, + RECIP_S, + RECIP_S_MM, + REPLV_PH, + REPLV_PH_MM, + REPLV_QB, + REPLV_QB_MM, + REPL_PH, + REPL_PH_MM, + REPL_QB, + REPL_QB_MM, + RINT_D, + RINT_D_MMR6, + RINT_S, + RINT_S_MMR6, + ROTR, + ROTRV, + ROTRV_MM, + ROTR_MM, + ROUND_L_D64, + ROUND_L_D_MMR6, + ROUND_L_S, + ROUND_L_S_MMR6, + ROUND_W_D32, + ROUND_W_D64, + ROUND_W_D_MMR6, + ROUND_W_MM, + ROUND_W_S, + ROUND_W_S_MM, + ROUND_W_S_MMR6, + RSQRT_D32, + RSQRT_D32_MM, + RSQRT_D64, + RSQRT_D64_MM, + RSQRT_S, + RSQRT_S_MM, + Restore16, + RestoreX16, + SAA, + SAAD, + SAT_S_B, + SAT_S_D, + SAT_S_H, + SAT_S_W, + SAT_U_B, + SAT_U_D, + SAT_U_H, + SAT_U_W, + SB, + SB16_MM, + SB16_MMR6, + SB64, + SBE, + SBE_MM, + SB_MM, + SB_MMR6, + SC, + SC64, + SC64_R6, + SCD, + SCD_R6, + SCE, + SCE_MM, + SC_MM, + SC_MMR6, + SC_R6, + SD, + SDBBP, + SDBBP16_MM, + SDBBP16_MMR6, + SDBBP_MM, + SDBBP_MMR6, + SDBBP_R6, + SDC1, + SDC164, + SDC1_D64_MMR6, + SDC1_MM_D32, + SDC1_MM_D64, + SDC2, + SDC2_MMR6, + SDC2_R6, + SDC3, + SDIV, + SDIV_MM, + SDL, + SDR, + SDXC1, + SDXC164, + SEB, + SEB64, + SEB_MM, + SEH, + SEH64, + SEH_MM, + SELEQZ, + SELEQZ64, + SELEQZ_D, + SELEQZ_D_MMR6, + SELEQZ_MMR6, + SELEQZ_S, + SELEQZ_S_MMR6, + SELNEZ, + SELNEZ64, + SELNEZ_D, + SELNEZ_D_MMR6, + SELNEZ_MMR6, + SELNEZ_S, + SELNEZ_S_MMR6, + SEL_D, + SEL_D_MMR6, + SEL_S, + SEL_S_MMR6, + SEQ, + SEQi, + SH, + SH16_MM, + SH16_MMR6, + SH64, + SHE, + SHE_MM, + SHF_B, + SHF_H, + SHF_W, + SHILO, + SHILOV, + SHILOV_MM, + SHILO_MM, + SHLLV_PH, + SHLLV_PH_MM, + SHLLV_QB, + SHLLV_QB_MM, + SHLLV_S_PH, + SHLLV_S_PH_MM, + SHLLV_S_W, + SHLLV_S_W_MM, + SHLL_PH, + SHLL_PH_MM, + SHLL_QB, + SHLL_QB_MM, + SHLL_S_PH, + SHLL_S_PH_MM, + SHLL_S_W, + SHLL_S_W_MM, + SHRAV_PH, + SHRAV_PH_MM, + SHRAV_QB, + SHRAV_QB_MMR2, + SHRAV_R_PH, + SHRAV_R_PH_MM, + SHRAV_R_QB, + SHRAV_R_QB_MMR2, + SHRAV_R_W, + SHRAV_R_W_MM, + SHRA_PH, + SHRA_PH_MM, + SHRA_QB, + SHRA_QB_MMR2, + SHRA_R_PH, + SHRA_R_PH_MM, + SHRA_R_QB, + SHRA_R_QB_MMR2, + SHRA_R_W, + SHRA_R_W_MM, + SHRLV_PH, + SHRLV_PH_MMR2, + SHRLV_QB, + SHRLV_QB_MM, + SHRL_PH, + SHRL_PH_MMR2, + SHRL_QB, + SHRL_QB_MM, + SH_MM, + SH_MMR6, + SIGRIE, + SIGRIE_MMR6, + SLDI_B, + SLDI_D, + SLDI_H, + SLDI_W, + SLD_B, + SLD_D, + SLD_H, + SLD_W, + SLL, + SLL16_MM, + SLL16_MMR6, + SLL64_32, + SLL64_64, + SLLI_B, + SLLI_D, + SLLI_H, + SLLI_W, + SLLV, + SLLV_MM, + SLL_B, + SLL_D, + SLL_H, + SLL_MM, + SLL_MMR6, + SLL_W, + SLT, + SLT64, + SLT_MM, + SLTi, + SLTi64, + SLTi_MM, + SLTiu, + SLTiu64, + SLTiu_MM, + SLTu, + SLTu64, + SLTu_MM, + SNE, + SNEi, + SPLATI_B, + SPLATI_D, + SPLATI_H, + SPLATI_W, + SPLAT_B, + SPLAT_D, + SPLAT_H, + SPLAT_W, + SRA, + SRAI_B, + SRAI_D, + SRAI_H, + SRAI_W, + SRARI_B, + SRARI_D, + SRARI_H, + SRARI_W, + SRAR_B, + SRAR_D, + SRAR_H, + SRAR_W, + SRAV, + SRAV_MM, + SRA_B, + SRA_D, + SRA_H, + SRA_MM, + SRA_W, + SRL, + SRL16_MM, + SRL16_MMR6, + SRLI_B, + SRLI_D, + SRLI_H, + SRLI_W, + SRLRI_B, + SRLRI_D, + SRLRI_H, + SRLRI_W, + SRLR_B, + SRLR_D, + SRLR_H, + SRLR_W, + SRLV, + SRLV_MM, + SRL_B, + SRL_D, + SRL_H, + SRL_MM, + SRL_W, + SSNOP, + SSNOP_MM, + SSNOP_MMR6, + ST_B, + ST_D, + ST_H, + ST_W, + SUB, + SUBQH_PH, + SUBQH_PH_MMR2, + SUBQH_R_PH, + SUBQH_R_PH_MMR2, + SUBQH_R_W, + SUBQH_R_W_MMR2, + SUBQH_W, + SUBQH_W_MMR2, + SUBQ_PH, + SUBQ_PH_MM, + SUBQ_S_PH, + SUBQ_S_PH_MM, + SUBQ_S_W, + SUBQ_S_W_MM, + SUBSUS_U_B, + SUBSUS_U_D, + SUBSUS_U_H, + SUBSUS_U_W, + SUBSUU_S_B, + SUBSUU_S_D, + SUBSUU_S_H, + SUBSUU_S_W, + SUBS_S_B, + SUBS_S_D, + SUBS_S_H, + SUBS_S_W, + SUBS_U_B, + SUBS_U_D, + SUBS_U_H, + SUBS_U_W, + SUBU16_MM, + SUBU16_MMR6, + SUBUH_QB, + SUBUH_QB_MMR2, + SUBUH_R_QB, + SUBUH_R_QB_MMR2, + SUBU_MMR6, + SUBU_PH, + SUBU_PH_MMR2, + SUBU_QB, + SUBU_QB_MM, + SUBU_S_PH, + SUBU_S_PH_MMR2, + SUBU_S_QB, + SUBU_S_QB_MM, + SUBVI_B, + SUBVI_D, + SUBVI_H, + SUBVI_W, + SUBV_B, + SUBV_D, + SUBV_H, + SUBV_W, + SUB_MM, + SUB_MMR6, + SUBu, + SUBu_MM, + SUXC1, + SUXC164, + SUXC1_MM, + SW, + SW16_MM, + SW16_MMR6, + SW64, + SWC1, + SWC1_MM, + SWC2, + SWC2_MMR6, + SWC2_R6, + SWC3, + SWDSP, + SWDSP_MM, + SWE, + SWE_MM, + SWL, + SWL64, + SWLE, + SWLE_MM, + SWL_MM, + SWM16_MM, + SWM16_MMR6, + SWM32_MM, + SWP_MM, + SWR, + SWR64, + SWRE, + SWRE_MM, + SWR_MM, + SWSP_MM, + SWSP_MMR6, + SWXC1, + SWXC1_MM, + SW_MM, + SW_MMR6, + SYNC, + SYNCI, + SYNCI_MM, + SYNCI_MMR6, + SYNC_MM, + SYNC_MMR6, + SYSCALL, + SYSCALL_MM, + Save16, + SaveX16, + SbRxRyOffMemX16, + SebRx16, + SehRx16, + ShRxRyOffMemX16, + SllX16, + SllvRxRy16, + SltRxRy16, + SltiRxImm16, + SltiRxImmX16, + SltiuRxImm16, + SltiuRxImmX16, + SltuRxRy16, + SraX16, + SravRxRy16, + SrlX16, + SrlvRxRy16, + SubuRxRyRz16, + SwRxRyOffMemX16, + SwRxSpImmX16, + TEQ, + TEQI, + TEQI_MM, + TEQ_MM, + TGE, + TGEI, + TGEIU, + TGEIU_MM, + TGEI_MM, + TGEU, + TGEU_MM, + TGE_MM, + TLBGINV, + TLBGINVF, + TLBGINVF_MM, + TLBGINV_MM, + TLBGP, + TLBGP_MM, + TLBGR, + TLBGR_MM, + TLBGWI, + TLBGWI_MM, + TLBGWR, + TLBGWR_MM, + TLBINV, + TLBINVF, + TLBINVF_MMR6, + TLBINV_MMR6, + TLBP, + TLBP_MM, + TLBR, + TLBR_MM, + TLBWI, + TLBWI_MM, + TLBWR, + TLBWR_MM, + TLT, + TLTI, + TLTIU_MM, + TLTI_MM, + TLTU, + TLTU_MM, + TLT_MM, + TNE, + TNEI, + TNEI_MM, + TNE_MM, + TRUNC_L_D64, + TRUNC_L_D_MMR6, + TRUNC_L_S, + TRUNC_L_S_MMR6, + TRUNC_W_D32, + TRUNC_W_D64, + TRUNC_W_D_MMR6, + TRUNC_W_MM, + TRUNC_W_S, + TRUNC_W_S_MM, + TRUNC_W_S_MMR6, + TTLTIU, + UDIV, + UDIV_MM, + V3MULU, + VMM0, + VMULU, + VSHF_B, + VSHF_D, + VSHF_H, + VSHF_W, + WAIT, + WAIT_MM, + WAIT_MMR6, + WRDSP, + WRDSP_MM, + WRPGPR_MMR6, + WSBH, + WSBH_MM, + WSBH_MMR6, + XOR, + XOR16_MM, + XOR16_MMR6, + XOR64, + XORI_B, + XORI_MMR6, + XOR_MM, + XOR_MMR6, + XOR_V, + XORi, + XORi64, + XORi_MM, + XorRxRxRy16, + YIELD, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ABSMacro, + 323 => Opcode::ADJCALLSTACKDOWN, + 324 => Opcode::ADJCALLSTACKUP, + 325 => Opcode::AND_V_D_PSEUDO, + 326 => Opcode::AND_V_H_PSEUDO, + 327 => Opcode::AND_V_W_PSEUDO, + 328 => Opcode::ATOMIC_CMP_SWAP_I16, + 329 => Opcode::ATOMIC_CMP_SWAP_I16_POSTRA, + 330 => Opcode::ATOMIC_CMP_SWAP_I32, + 331 => Opcode::ATOMIC_CMP_SWAP_I32_POSTRA, + 332 => Opcode::ATOMIC_CMP_SWAP_I64, + 333 => Opcode::ATOMIC_CMP_SWAP_I64_POSTRA, + 334 => Opcode::ATOMIC_CMP_SWAP_I8, + 335 => Opcode::ATOMIC_CMP_SWAP_I8_POSTRA, + 336 => Opcode::ATOMIC_LOAD_ADD_I16, + 337 => Opcode::ATOMIC_LOAD_ADD_I16_POSTRA, + 338 => Opcode::ATOMIC_LOAD_ADD_I32, + 339 => Opcode::ATOMIC_LOAD_ADD_I32_POSTRA, + 340 => Opcode::ATOMIC_LOAD_ADD_I64, + 341 => Opcode::ATOMIC_LOAD_ADD_I64_POSTRA, + 342 => Opcode::ATOMIC_LOAD_ADD_I8, + 343 => Opcode::ATOMIC_LOAD_ADD_I8_POSTRA, + 344 => Opcode::ATOMIC_LOAD_AND_I16, + 345 => Opcode::ATOMIC_LOAD_AND_I16_POSTRA, + 346 => Opcode::ATOMIC_LOAD_AND_I32, + 347 => Opcode::ATOMIC_LOAD_AND_I32_POSTRA, + 348 => Opcode::ATOMIC_LOAD_AND_I64, + 349 => Opcode::ATOMIC_LOAD_AND_I64_POSTRA, + 350 => Opcode::ATOMIC_LOAD_AND_I8, + 351 => Opcode::ATOMIC_LOAD_AND_I8_POSTRA, + 352 => Opcode::ATOMIC_LOAD_MAX_I16, + 353 => Opcode::ATOMIC_LOAD_MAX_I16_POSTRA, + 354 => Opcode::ATOMIC_LOAD_MAX_I32, + 355 => Opcode::ATOMIC_LOAD_MAX_I32_POSTRA, + 356 => Opcode::ATOMIC_LOAD_MAX_I64, + 357 => Opcode::ATOMIC_LOAD_MAX_I64_POSTRA, + 358 => Opcode::ATOMIC_LOAD_MAX_I8, + 359 => Opcode::ATOMIC_LOAD_MAX_I8_POSTRA, + 360 => Opcode::ATOMIC_LOAD_MIN_I16, + 361 => Opcode::ATOMIC_LOAD_MIN_I16_POSTRA, + 362 => Opcode::ATOMIC_LOAD_MIN_I32, + 363 => Opcode::ATOMIC_LOAD_MIN_I32_POSTRA, + 364 => Opcode::ATOMIC_LOAD_MIN_I64, + 365 => Opcode::ATOMIC_LOAD_MIN_I64_POSTRA, + 366 => Opcode::ATOMIC_LOAD_MIN_I8, + 367 => Opcode::ATOMIC_LOAD_MIN_I8_POSTRA, + 368 => Opcode::ATOMIC_LOAD_NAND_I16, + 369 => Opcode::ATOMIC_LOAD_NAND_I16_POSTRA, + 370 => Opcode::ATOMIC_LOAD_NAND_I32, + 371 => Opcode::ATOMIC_LOAD_NAND_I32_POSTRA, + 372 => Opcode::ATOMIC_LOAD_NAND_I64, + 373 => Opcode::ATOMIC_LOAD_NAND_I64_POSTRA, + 374 => Opcode::ATOMIC_LOAD_NAND_I8, + 375 => Opcode::ATOMIC_LOAD_NAND_I8_POSTRA, + 376 => Opcode::ATOMIC_LOAD_OR_I16, + 377 => Opcode::ATOMIC_LOAD_OR_I16_POSTRA, + 378 => Opcode::ATOMIC_LOAD_OR_I32, + 379 => Opcode::ATOMIC_LOAD_OR_I32_POSTRA, + 380 => Opcode::ATOMIC_LOAD_OR_I64, + 381 => Opcode::ATOMIC_LOAD_OR_I64_POSTRA, + 382 => Opcode::ATOMIC_LOAD_OR_I8, + 383 => Opcode::ATOMIC_LOAD_OR_I8_POSTRA, + 384 => Opcode::ATOMIC_LOAD_SUB_I16, + 385 => Opcode::ATOMIC_LOAD_SUB_I16_POSTRA, + 386 => Opcode::ATOMIC_LOAD_SUB_I32, + 387 => Opcode::ATOMIC_LOAD_SUB_I32_POSTRA, + 388 => Opcode::ATOMIC_LOAD_SUB_I64, + 389 => Opcode::ATOMIC_LOAD_SUB_I64_POSTRA, + 390 => Opcode::ATOMIC_LOAD_SUB_I8, + 391 => Opcode::ATOMIC_LOAD_SUB_I8_POSTRA, + 392 => Opcode::ATOMIC_LOAD_UMAX_I16, + 393 => Opcode::ATOMIC_LOAD_UMAX_I16_POSTRA, + 394 => Opcode::ATOMIC_LOAD_UMAX_I32, + 395 => Opcode::ATOMIC_LOAD_UMAX_I32_POSTRA, + 396 => Opcode::ATOMIC_LOAD_UMAX_I64, + 397 => Opcode::ATOMIC_LOAD_UMAX_I64_POSTRA, + 398 => Opcode::ATOMIC_LOAD_UMAX_I8, + 399 => Opcode::ATOMIC_LOAD_UMAX_I8_POSTRA, + 400 => Opcode::ATOMIC_LOAD_UMIN_I16, + 401 => Opcode::ATOMIC_LOAD_UMIN_I16_POSTRA, + 402 => Opcode::ATOMIC_LOAD_UMIN_I32, + 403 => Opcode::ATOMIC_LOAD_UMIN_I32_POSTRA, + 404 => Opcode::ATOMIC_LOAD_UMIN_I64, + 405 => Opcode::ATOMIC_LOAD_UMIN_I64_POSTRA, + 406 => Opcode::ATOMIC_LOAD_UMIN_I8, + 407 => Opcode::ATOMIC_LOAD_UMIN_I8_POSTRA, + 408 => Opcode::ATOMIC_LOAD_XOR_I16, + 409 => Opcode::ATOMIC_LOAD_XOR_I16_POSTRA, + 410 => Opcode::ATOMIC_LOAD_XOR_I32, + 411 => Opcode::ATOMIC_LOAD_XOR_I32_POSTRA, + 412 => Opcode::ATOMIC_LOAD_XOR_I64, + 413 => Opcode::ATOMIC_LOAD_XOR_I64_POSTRA, + 414 => Opcode::ATOMIC_LOAD_XOR_I8, + 415 => Opcode::ATOMIC_LOAD_XOR_I8_POSTRA, + 416 => Opcode::ATOMIC_SWAP_I16, + 417 => Opcode::ATOMIC_SWAP_I16_POSTRA, + 418 => Opcode::ATOMIC_SWAP_I32, + 419 => Opcode::ATOMIC_SWAP_I32_POSTRA, + 420 => Opcode::ATOMIC_SWAP_I64, + 421 => Opcode::ATOMIC_SWAP_I64_POSTRA, + 422 => Opcode::ATOMIC_SWAP_I8, + 423 => Opcode::ATOMIC_SWAP_I8_POSTRA, + 424 => Opcode::B, + 425 => Opcode::BAL_BR, + 426 => Opcode::BAL_BR_MM, + 427 => Opcode::BEQLImmMacro, + 428 => Opcode::BGE, + 429 => Opcode::BGEImmMacro, + 430 => Opcode::BGEL, + 431 => Opcode::BGELImmMacro, + 432 => Opcode::BGEU, + 433 => Opcode::BGEUImmMacro, + 434 => Opcode::BGEUL, + 435 => Opcode::BGEULImmMacro, + 436 => Opcode::BGT, + 437 => Opcode::BGTImmMacro, + 438 => Opcode::BGTL, + 439 => Opcode::BGTLImmMacro, + 440 => Opcode::BGTU, + 441 => Opcode::BGTUImmMacro, + 442 => Opcode::BGTUL, + 443 => Opcode::BGTULImmMacro, + 444 => Opcode::BLE, + 445 => Opcode::BLEImmMacro, + 446 => Opcode::BLEL, + 447 => Opcode::BLELImmMacro, + 448 => Opcode::BLEU, + 449 => Opcode::BLEUImmMacro, + 450 => Opcode::BLEUL, + 451 => Opcode::BLEULImmMacro, + 452 => Opcode::BLT, + 453 => Opcode::BLTImmMacro, + 454 => Opcode::BLTL, + 455 => Opcode::BLTLImmMacro, + 456 => Opcode::BLTU, + 457 => Opcode::BLTUImmMacro, + 458 => Opcode::BLTUL, + 459 => Opcode::BLTULImmMacro, + 460 => Opcode::BNELImmMacro, + 461 => Opcode::BPOSGE32_PSEUDO, + 462 => Opcode::BSEL_D_PSEUDO, + 463 => Opcode::BSEL_FD_PSEUDO, + 464 => Opcode::BSEL_FW_PSEUDO, + 465 => Opcode::BSEL_H_PSEUDO, + 466 => Opcode::BSEL_W_PSEUDO, + 467 => Opcode::B_MM, + 468 => Opcode::B_MMR6_Pseudo, + 469 => Opcode::B_MM_Pseudo, + 470 => Opcode::BeqImm, + 471 => Opcode::BneImm, + 472 => Opcode::BteqzT8CmpX16, + 473 => Opcode::BteqzT8CmpiX16, + 474 => Opcode::BteqzT8SltX16, + 475 => Opcode::BteqzT8SltiX16, + 476 => Opcode::BteqzT8SltiuX16, + 477 => Opcode::BteqzT8SltuX16, + 478 => Opcode::BtnezT8CmpX16, + 479 => Opcode::BtnezT8CmpiX16, + 480 => Opcode::BtnezT8SltX16, + 481 => Opcode::BtnezT8SltiX16, + 482 => Opcode::BtnezT8SltiuX16, + 483 => Opcode::BtnezT8SltuX16, + 484 => Opcode::BuildPairF64, + 485 => Opcode::BuildPairF64_64, + 486 => Opcode::CFTC1, + 487 => Opcode::CONSTPOOL_ENTRY, + 488 => Opcode::COPY_FD_PSEUDO, + 489 => Opcode::COPY_FW_PSEUDO, + 490 => Opcode::CTTC1, + 491 => Opcode::Constant32, + 492 => Opcode::DMULImmMacro, + 493 => Opcode::DMULMacro, + 494 => Opcode::DMULOMacro, + 495 => Opcode::DMULOUMacro, + 496 => Opcode::DROL, + 497 => Opcode::DROLImm, + 498 => Opcode::DROR, + 499 => Opcode::DRORImm, + 500 => Opcode::DSDivIMacro, + 501 => Opcode::DSDivMacro, + 502 => Opcode::DSRemIMacro, + 503 => Opcode::DSRemMacro, + 504 => Opcode::DUDivIMacro, + 505 => Opcode::DUDivMacro, + 506 => Opcode::DURemIMacro, + 507 => Opcode::DURemMacro, + 508 => Opcode::ERet, + 509 => Opcode::ExtractElementF64, + 510 => Opcode::ExtractElementF64_64, + 511 => Opcode::FABS_D, + 512 => Opcode::FABS_W, + 513 => Opcode::FEXP2_D_1_PSEUDO, + 514 => Opcode::FEXP2_W_1_PSEUDO, + 515 => Opcode::FILL_FD_PSEUDO, + 516 => Opcode::FILL_FW_PSEUDO, + 517 => Opcode::GotPrologue16, + 518 => Opcode::INSERT_B_VIDX64_PSEUDO, + 519 => Opcode::INSERT_B_VIDX_PSEUDO, + 520 => Opcode::INSERT_D_VIDX64_PSEUDO, + 521 => Opcode::INSERT_D_VIDX_PSEUDO, + 522 => Opcode::INSERT_FD_PSEUDO, + 523 => Opcode::INSERT_FD_VIDX64_PSEUDO, + 524 => Opcode::INSERT_FD_VIDX_PSEUDO, + 525 => Opcode::INSERT_FW_PSEUDO, + 526 => Opcode::INSERT_FW_VIDX64_PSEUDO, + 527 => Opcode::INSERT_FW_VIDX_PSEUDO, + 528 => Opcode::INSERT_H_VIDX64_PSEUDO, + 529 => Opcode::INSERT_H_VIDX_PSEUDO, + 530 => Opcode::INSERT_W_VIDX64_PSEUDO, + 531 => Opcode::INSERT_W_VIDX_PSEUDO, + 532 => Opcode::JALR64Pseudo, + 533 => Opcode::JALRHB64Pseudo, + 534 => Opcode::JALRHBPseudo, + 535 => Opcode::JALRPseudo, + 536 => Opcode::JAL_MMR6, + 537 => Opcode::JalOneReg, + 538 => Opcode::JalTwoReg, + 539 => Opcode::LDMacro, + 540 => Opcode::LDR_D, + 541 => Opcode::LDR_W, + 542 => Opcode::LD_F16, + 543 => Opcode::LOAD_ACC128, + 544 => Opcode::LOAD_ACC64, + 545 => Opcode::LOAD_ACC64DSP, + 546 => Opcode::LOAD_CCOND_DSP, + 547 => Opcode::LONG_BRANCH_ADDiu, + 548 => Opcode::LONG_BRANCH_ADDiu2Op, + 549 => Opcode::LONG_BRANCH_DADDiu, + 550 => Opcode::LONG_BRANCH_DADDiu2Op, + 551 => Opcode::LONG_BRANCH_LUi, + 552 => Opcode::LONG_BRANCH_LUi2Op, + 553 => Opcode::LONG_BRANCH_LUi2Op_64, + 554 => Opcode::LWM_MM, + 555 => Opcode::LoadAddrImm32, + 556 => Opcode::LoadAddrImm64, + 557 => Opcode::LoadAddrReg32, + 558 => Opcode::LoadAddrReg64, + 559 => Opcode::LoadImm32, + 560 => Opcode::LoadImm64, + 561 => Opcode::LoadImmDoubleFGR, + 562 => Opcode::LoadImmDoubleFGR_32, + 563 => Opcode::LoadImmDoubleGPR, + 564 => Opcode::LoadImmSingleFGR, + 565 => Opcode::LoadImmSingleGPR, + 566 => Opcode::LwConstant32, + 567 => Opcode::MFTACX, + 568 => Opcode::MFTC0, + 569 => Opcode::MFTC1, + 570 => Opcode::MFTDSP, + 571 => Opcode::MFTGPR, + 572 => Opcode::MFTHC1, + 573 => Opcode::MFTHI, + 574 => Opcode::MFTLO, + 575 => Opcode::MIPSeh_return32, + 576 => Opcode::MIPSeh_return64, + 577 => Opcode::MSA_FP_EXTEND_D_PSEUDO, + 578 => Opcode::MSA_FP_EXTEND_W_PSEUDO, + 579 => Opcode::MSA_FP_ROUND_D_PSEUDO, + 580 => Opcode::MSA_FP_ROUND_W_PSEUDO, + 581 => Opcode::MTTACX, + 582 => Opcode::MTTC0, + 583 => Opcode::MTTC1, + 584 => Opcode::MTTDSP, + 585 => Opcode::MTTGPR, + 586 => Opcode::MTTHC1, + 587 => Opcode::MTTHI, + 588 => Opcode::MTTLO, + 589 => Opcode::MULImmMacro, + 590 => Opcode::MULOMacro, + 591 => Opcode::MULOUMacro, + 592 => Opcode::MultRxRy16, + 593 => Opcode::MultRxRyRz16, + 594 => Opcode::MultuRxRy16, + 595 => Opcode::MultuRxRyRz16, + 596 => Opcode::NOP, + 597 => Opcode::NORImm, + 598 => Opcode::NORImm64, + 599 => Opcode::NOR_V_D_PSEUDO, + 600 => Opcode::NOR_V_H_PSEUDO, + 601 => Opcode::NOR_V_W_PSEUDO, + 602 => Opcode::OR_V_D_PSEUDO, + 603 => Opcode::OR_V_H_PSEUDO, + 604 => Opcode::OR_V_W_PSEUDO, + 605 => Opcode::PseudoCMPU_EQ_QB, + 606 => Opcode::PseudoCMPU_LE_QB, + 607 => Opcode::PseudoCMPU_LT_QB, + 608 => Opcode::PseudoCMP_EQ_PH, + 609 => Opcode::PseudoCMP_LE_PH, + 610 => Opcode::PseudoCMP_LT_PH, + 611 => Opcode::PseudoCVT_D32_W, + 612 => Opcode::PseudoCVT_D64_L, + 613 => Opcode::PseudoCVT_D64_W, + 614 => Opcode::PseudoCVT_S_L, + 615 => Opcode::PseudoCVT_S_W, + 616 => Opcode::PseudoDMULT, + 617 => Opcode::PseudoDMULTu, + 618 => Opcode::PseudoDSDIV, + 619 => Opcode::PseudoDUDIV, + 620 => Opcode::PseudoD_SELECT_I, + 621 => Opcode::PseudoD_SELECT_I64, + 622 => Opcode::PseudoIndirectBranch, + 623 => Opcode::PseudoIndirectBranch64, + 624 => Opcode::PseudoIndirectBranch64R6, + 625 => Opcode::PseudoIndirectBranchR6, + 626 => Opcode::PseudoIndirectBranch_MM, + 627 => Opcode::PseudoIndirectBranch_MMR6, + 628 => Opcode::PseudoIndirectHazardBranch, + 629 => Opcode::PseudoIndirectHazardBranch64, + 630 => Opcode::PseudoIndrectHazardBranch64R6, + 631 => Opcode::PseudoIndrectHazardBranchR6, + 632 => Opcode::PseudoMADD, + 633 => Opcode::PseudoMADDU, + 634 => Opcode::PseudoMADDU_MM, + 635 => Opcode::PseudoMADD_MM, + 636 => Opcode::PseudoMFHI, + 637 => Opcode::PseudoMFHI64, + 638 => Opcode::PseudoMFHI_MM, + 639 => Opcode::PseudoMFLO, + 640 => Opcode::PseudoMFLO64, + 641 => Opcode::PseudoMFLO_MM, + 642 => Opcode::PseudoMSUB, + 643 => Opcode::PseudoMSUBU, + 644 => Opcode::PseudoMSUBU_MM, + 645 => Opcode::PseudoMSUB_MM, + 646 => Opcode::PseudoMTLOHI, + 647 => Opcode::PseudoMTLOHI64, + 648 => Opcode::PseudoMTLOHI_DSP, + 649 => Opcode::PseudoMTLOHI_MM, + 650 => Opcode::PseudoMULT, + 651 => Opcode::PseudoMULT_MM, + 652 => Opcode::PseudoMULTu, + 653 => Opcode::PseudoMULTu_MM, + 654 => Opcode::PseudoPICK_PH, + 655 => Opcode::PseudoPICK_QB, + 656 => Opcode::PseudoReturn, + 657 => Opcode::PseudoReturn64, + 658 => Opcode::PseudoSDIV, + 659 => Opcode::PseudoSELECTFP_F_D32, + 660 => Opcode::PseudoSELECTFP_F_D64, + 661 => Opcode::PseudoSELECTFP_F_I, + 662 => Opcode::PseudoSELECTFP_F_I64, + 663 => Opcode::PseudoSELECTFP_F_S, + 664 => Opcode::PseudoSELECTFP_T_D32, + 665 => Opcode::PseudoSELECTFP_T_D64, + 666 => Opcode::PseudoSELECTFP_T_I, + 667 => Opcode::PseudoSELECTFP_T_I64, + 668 => Opcode::PseudoSELECTFP_T_S, + 669 => Opcode::PseudoSELECT_D32, + 670 => Opcode::PseudoSELECT_D64, + 671 => Opcode::PseudoSELECT_I, + 672 => Opcode::PseudoSELECT_I64, + 673 => Opcode::PseudoSELECT_S, + 674 => Opcode::PseudoTRUNC_W_D, + 675 => Opcode::PseudoTRUNC_W_D32, + 676 => Opcode::PseudoTRUNC_W_S, + 677 => Opcode::PseudoUDIV, + 678 => Opcode::ROL, + 679 => Opcode::ROLImm, + 680 => Opcode::ROR, + 681 => Opcode::RORImm, + 682 => Opcode::RetRA, + 683 => Opcode::RetRA16, + 684 => Opcode::SDC1_M1, + 685 => Opcode::SDIV_MM_Pseudo, + 686 => Opcode::SDMacro, + 687 => Opcode::SDivIMacro, + 688 => Opcode::SDivMacro, + 689 => Opcode::SEQIMacro, + 690 => Opcode::SEQMacro, + 691 => Opcode::SGE, + 692 => Opcode::SGEImm, + 693 => Opcode::SGEImm64, + 694 => Opcode::SGEU, + 695 => Opcode::SGEUImm, + 696 => Opcode::SGEUImm64, + 697 => Opcode::SGTImm, + 698 => Opcode::SGTImm64, + 699 => Opcode::SGTUImm, + 700 => Opcode::SGTUImm64, + 701 => Opcode::SLE, + 702 => Opcode::SLEImm, + 703 => Opcode::SLEImm64, + 704 => Opcode::SLEU, + 705 => Opcode::SLEUImm, + 706 => Opcode::SLEUImm64, + 707 => Opcode::SLTImm64, + 708 => Opcode::SLTUImm64, + 709 => Opcode::SNEIMacro, + 710 => Opcode::SNEMacro, + 711 => Opcode::SNZ_B_PSEUDO, + 712 => Opcode::SNZ_D_PSEUDO, + 713 => Opcode::SNZ_H_PSEUDO, + 714 => Opcode::SNZ_V_PSEUDO, + 715 => Opcode::SNZ_W_PSEUDO, + 716 => Opcode::SRemIMacro, + 717 => Opcode::SRemMacro, + 718 => Opcode::STORE_ACC128, + 719 => Opcode::STORE_ACC64, + 720 => Opcode::STORE_ACC64DSP, + 721 => Opcode::STORE_CCOND_DSP, + 722 => Opcode::STR_D, + 723 => Opcode::STR_W, + 724 => Opcode::ST_F16, + 725 => Opcode::SWM_MM, + 726 => Opcode::SZ_B_PSEUDO, + 727 => Opcode::SZ_D_PSEUDO, + 728 => Opcode::SZ_H_PSEUDO, + 729 => Opcode::SZ_V_PSEUDO, + 730 => Opcode::SZ_W_PSEUDO, + 731 => Opcode::SaaAddr, + 732 => Opcode::SaadAddr, + 733 => Opcode::SelBeqZ, + 734 => Opcode::SelBneZ, + 735 => Opcode::SelTBteqZCmp, + 736 => Opcode::SelTBteqZCmpi, + 737 => Opcode::SelTBteqZSlt, + 738 => Opcode::SelTBteqZSlti, + 739 => Opcode::SelTBteqZSltiu, + 740 => Opcode::SelTBteqZSltu, + 741 => Opcode::SelTBtneZCmp, + 742 => Opcode::SelTBtneZCmpi, + 743 => Opcode::SelTBtneZSlt, + 744 => Opcode::SelTBtneZSlti, + 745 => Opcode::SelTBtneZSltiu, + 746 => Opcode::SelTBtneZSltu, + 747 => Opcode::SltCCRxRy16, + 748 => Opcode::SltiCCRxImmX16, + 749 => Opcode::SltiuCCRxImmX16, + 750 => Opcode::SltuCCRxRy16, + 751 => Opcode::SltuRxRyRz16, + 752 => Opcode::TAILCALL, + 753 => Opcode::TAILCALL64R6REG, + 754 => Opcode::TAILCALLHB64R6REG, + 755 => Opcode::TAILCALLHBR6REG, + 756 => Opcode::TAILCALLR6REG, + 757 => Opcode::TAILCALLREG, + 758 => Opcode::TAILCALLREG64, + 759 => Opcode::TAILCALLREGHB, + 760 => Opcode::TAILCALLREGHB64, + 761 => Opcode::TAILCALLREG_MM, + 762 => Opcode::TAILCALLREG_MMR6, + 763 => Opcode::TAILCALL_MM, + 764 => Opcode::TAILCALL_MMR6, + 765 => Opcode::TRAP, + 766 => Opcode::TRAP_MM, + 767 => Opcode::UDIV_MM_Pseudo, + 768 => Opcode::UDivIMacro, + 769 => Opcode::UDivMacro, + 770 => Opcode::URemIMacro, + 771 => Opcode::URemMacro, + 772 => Opcode::Ulh, + 773 => Opcode::Ulhu, + 774 => Opcode::Ulw, + 775 => Opcode::Ush, + 776 => Opcode::Usw, + 777 => Opcode::XOR_V_D_PSEUDO, + 778 => Opcode::XOR_V_H_PSEUDO, + 779 => Opcode::XOR_V_W_PSEUDO, + 780 => Opcode::ABSQ_S_PH, + 781 => Opcode::ABSQ_S_PH_MM, + 782 => Opcode::ABSQ_S_QB, + 783 => Opcode::ABSQ_S_QB_MMR2, + 784 => Opcode::ABSQ_S_W, + 785 => Opcode::ABSQ_S_W_MM, + 786 => Opcode::ADD, + 787 => Opcode::ADDIUPC, + 788 => Opcode::ADDIUPC_MM, + 789 => Opcode::ADDIUPC_MMR6, + 790 => Opcode::ADDIUR1SP_MM, + 791 => Opcode::ADDIUR2_MM, + 792 => Opcode::ADDIUS5_MM, + 793 => Opcode::ADDIUSP_MM, + 794 => Opcode::ADDIU_MMR6, + 795 => Opcode::ADDQH_PH, + 796 => Opcode::ADDQH_PH_MMR2, + 797 => Opcode::ADDQH_R_PH, + 798 => Opcode::ADDQH_R_PH_MMR2, + 799 => Opcode::ADDQH_R_W, + 800 => Opcode::ADDQH_R_W_MMR2, + 801 => Opcode::ADDQH_W, + 802 => Opcode::ADDQH_W_MMR2, + 803 => Opcode::ADDQ_PH, + 804 => Opcode::ADDQ_PH_MM, + 805 => Opcode::ADDQ_S_PH, + 806 => Opcode::ADDQ_S_PH_MM, + 807 => Opcode::ADDQ_S_W, + 808 => Opcode::ADDQ_S_W_MM, + 809 => Opcode::ADDR_PS64, + 810 => Opcode::ADDSC, + 811 => Opcode::ADDSC_MM, + 812 => Opcode::ADDS_A_B, + 813 => Opcode::ADDS_A_D, + 814 => Opcode::ADDS_A_H, + 815 => Opcode::ADDS_A_W, + 816 => Opcode::ADDS_S_B, + 817 => Opcode::ADDS_S_D, + 818 => Opcode::ADDS_S_H, + 819 => Opcode::ADDS_S_W, + 820 => Opcode::ADDS_U_B, + 821 => Opcode::ADDS_U_D, + 822 => Opcode::ADDS_U_H, + 823 => Opcode::ADDS_U_W, + 824 => Opcode::ADDU16_MM, + 825 => Opcode::ADDU16_MMR6, + 826 => Opcode::ADDUH_QB, + 827 => Opcode::ADDUH_QB_MMR2, + 828 => Opcode::ADDUH_R_QB, + 829 => Opcode::ADDUH_R_QB_MMR2, + 830 => Opcode::ADDU_MMR6, + 831 => Opcode::ADDU_PH, + 832 => Opcode::ADDU_PH_MMR2, + 833 => Opcode::ADDU_QB, + 834 => Opcode::ADDU_QB_MM, + 835 => Opcode::ADDU_S_PH, + 836 => Opcode::ADDU_S_PH_MMR2, + 837 => Opcode::ADDU_S_QB, + 838 => Opcode::ADDU_S_QB_MM, + 839 => Opcode::ADDVI_B, + 840 => Opcode::ADDVI_D, + 841 => Opcode::ADDVI_H, + 842 => Opcode::ADDVI_W, + 843 => Opcode::ADDV_B, + 844 => Opcode::ADDV_D, + 845 => Opcode::ADDV_H, + 846 => Opcode::ADDV_W, + 847 => Opcode::ADDWC, + 848 => Opcode::ADDWC_MM, + 849 => Opcode::ADD_A_B, + 850 => Opcode::ADD_A_D, + 851 => Opcode::ADD_A_H, + 852 => Opcode::ADD_A_W, + 853 => Opcode::ADD_MM, + 854 => Opcode::ADD_MMR6, + 855 => Opcode::ADDi, + 856 => Opcode::ADDi_MM, + 857 => Opcode::ADDiu, + 858 => Opcode::ADDiu_MM, + 859 => Opcode::ADDu, + 860 => Opcode::ADDu_MM, + 861 => Opcode::ALIGN, + 862 => Opcode::ALIGN_MMR6, + 863 => Opcode::ALUIPC, + 864 => Opcode::ALUIPC_MMR6, + 865 => Opcode::AND, + 866 => Opcode::AND16_MM, + 867 => Opcode::AND16_MMR6, + 868 => Opcode::AND64, + 869 => Opcode::ANDI16_MM, + 870 => Opcode::ANDI16_MMR6, + 871 => Opcode::ANDI_B, + 872 => Opcode::ANDI_MMR6, + 873 => Opcode::AND_MM, + 874 => Opcode::AND_MMR6, + 875 => Opcode::AND_V, + 876 => Opcode::ANDi, + 877 => Opcode::ANDi64, + 878 => Opcode::ANDi_MM, + 879 => Opcode::APPEND, + 880 => Opcode::APPEND_MMR2, + 881 => Opcode::ASUB_S_B, + 882 => Opcode::ASUB_S_D, + 883 => Opcode::ASUB_S_H, + 884 => Opcode::ASUB_S_W, + 885 => Opcode::ASUB_U_B, + 886 => Opcode::ASUB_U_D, + 887 => Opcode::ASUB_U_H, + 888 => Opcode::ASUB_U_W, + 889 => Opcode::AUI, + 890 => Opcode::AUIPC, + 891 => Opcode::AUIPC_MMR6, + 892 => Opcode::AUI_MMR6, + 893 => Opcode::AVER_S_B, + 894 => Opcode::AVER_S_D, + 895 => Opcode::AVER_S_H, + 896 => Opcode::AVER_S_W, + 897 => Opcode::AVER_U_B, + 898 => Opcode::AVER_U_D, + 899 => Opcode::AVER_U_H, + 900 => Opcode::AVER_U_W, + 901 => Opcode::AVE_S_B, + 902 => Opcode::AVE_S_D, + 903 => Opcode::AVE_S_H, + 904 => Opcode::AVE_S_W, + 905 => Opcode::AVE_U_B, + 906 => Opcode::AVE_U_D, + 907 => Opcode::AVE_U_H, + 908 => Opcode::AVE_U_W, + 909 => Opcode::AddiuRxImmX16, + 910 => Opcode::AddiuRxPcImmX16, + 911 => Opcode::AddiuRxRxImm16, + 912 => Opcode::AddiuRxRxImmX16, + 913 => Opcode::AddiuRxRyOffMemX16, + 914 => Opcode::AddiuSpImm16, + 915 => Opcode::AddiuSpImmX16, + 916 => Opcode::AdduRxRyRz16, + 917 => Opcode::AndRxRxRy16, + 918 => Opcode::B16_MM, + 919 => Opcode::BADDu, + 920 => Opcode::BAL, + 921 => Opcode::BALC, + 922 => Opcode::BALC_MMR6, + 923 => Opcode::BALIGN, + 924 => Opcode::BALIGN_MMR2, + 925 => Opcode::BBIT0, + 926 => Opcode::BBIT032, + 927 => Opcode::BBIT1, + 928 => Opcode::BBIT132, + 929 => Opcode::BC, + 930 => Opcode::BC16_MMR6, + 931 => Opcode::BC1EQZ, + 932 => Opcode::BC1EQZC_MMR6, + 933 => Opcode::BC1F, + 934 => Opcode::BC1FL, + 935 => Opcode::BC1F_MM, + 936 => Opcode::BC1NEZ, + 937 => Opcode::BC1NEZC_MMR6, + 938 => Opcode::BC1T, + 939 => Opcode::BC1TL, + 940 => Opcode::BC1T_MM, + 941 => Opcode::BC2EQZ, + 942 => Opcode::BC2EQZC_MMR6, + 943 => Opcode::BC2NEZ, + 944 => Opcode::BC2NEZC_MMR6, + 945 => Opcode::BCLRI_B, + 946 => Opcode::BCLRI_D, + 947 => Opcode::BCLRI_H, + 948 => Opcode::BCLRI_W, + 949 => Opcode::BCLR_B, + 950 => Opcode::BCLR_D, + 951 => Opcode::BCLR_H, + 952 => Opcode::BCLR_W, + 953 => Opcode::BC_MMR6, + 954 => Opcode::BEQ, + 955 => Opcode::BEQ64, + 956 => Opcode::BEQC, + 957 => Opcode::BEQC64, + 958 => Opcode::BEQC_MMR6, + 959 => Opcode::BEQL, + 960 => Opcode::BEQZ16_MM, + 961 => Opcode::BEQZALC, + 962 => Opcode::BEQZALC_MMR6, + 963 => Opcode::BEQZC, + 964 => Opcode::BEQZC16_MMR6, + 965 => Opcode::BEQZC64, + 966 => Opcode::BEQZC_MM, + 967 => Opcode::BEQZC_MMR6, + 968 => Opcode::BEQ_MM, + 969 => Opcode::BGEC, + 970 => Opcode::BGEC64, + 971 => Opcode::BGEC_MMR6, + 972 => Opcode::BGEUC, + 973 => Opcode::BGEUC64, + 974 => Opcode::BGEUC_MMR6, + 975 => Opcode::BGEZ, + 976 => Opcode::BGEZ64, + 977 => Opcode::BGEZAL, + 978 => Opcode::BGEZALC, + 979 => Opcode::BGEZALC_MMR6, + 980 => Opcode::BGEZALL, + 981 => Opcode::BGEZALS_MM, + 982 => Opcode::BGEZAL_MM, + 983 => Opcode::BGEZC, + 984 => Opcode::BGEZC64, + 985 => Opcode::BGEZC_MMR6, + 986 => Opcode::BGEZL, + 987 => Opcode::BGEZ_MM, + 988 => Opcode::BGTZ, + 989 => Opcode::BGTZ64, + 990 => Opcode::BGTZALC, + 991 => Opcode::BGTZALC_MMR6, + 992 => Opcode::BGTZC, + 993 => Opcode::BGTZC64, + 994 => Opcode::BGTZC_MMR6, + 995 => Opcode::BGTZL, + 996 => Opcode::BGTZ_MM, + 997 => Opcode::BINSLI_B, + 998 => Opcode::BINSLI_D, + 999 => Opcode::BINSLI_H, + 1000 => Opcode::BINSLI_W, + 1001 => Opcode::BINSL_B, + 1002 => Opcode::BINSL_D, + 1003 => Opcode::BINSL_H, + 1004 => Opcode::BINSL_W, + 1005 => Opcode::BINSRI_B, + 1006 => Opcode::BINSRI_D, + 1007 => Opcode::BINSRI_H, + 1008 => Opcode::BINSRI_W, + 1009 => Opcode::BINSR_B, + 1010 => Opcode::BINSR_D, + 1011 => Opcode::BINSR_H, + 1012 => Opcode::BINSR_W, + 1013 => Opcode::BITREV, + 1014 => Opcode::BITREV_MM, + 1015 => Opcode::BITSWAP, + 1016 => Opcode::BITSWAP_MMR6, + 1017 => Opcode::BLEZ, + 1018 => Opcode::BLEZ64, + 1019 => Opcode::BLEZALC, + 1020 => Opcode::BLEZALC_MMR6, + 1021 => Opcode::BLEZC, + 1022 => Opcode::BLEZC64, + 1023 => Opcode::BLEZC_MMR6, + 1024 => Opcode::BLEZL, + 1025 => Opcode::BLEZ_MM, + 1026 => Opcode::BLTC, + 1027 => Opcode::BLTC64, + 1028 => Opcode::BLTC_MMR6, + 1029 => Opcode::BLTUC, + 1030 => Opcode::BLTUC64, + 1031 => Opcode::BLTUC_MMR6, + 1032 => Opcode::BLTZ, + 1033 => Opcode::BLTZ64, + 1034 => Opcode::BLTZAL, + 1035 => Opcode::BLTZALC, + 1036 => Opcode::BLTZALC_MMR6, + 1037 => Opcode::BLTZALL, + 1038 => Opcode::BLTZALS_MM, + 1039 => Opcode::BLTZAL_MM, + 1040 => Opcode::BLTZC, + 1041 => Opcode::BLTZC64, + 1042 => Opcode::BLTZC_MMR6, + 1043 => Opcode::BLTZL, + 1044 => Opcode::BLTZ_MM, + 1045 => Opcode::BMNZI_B, + 1046 => Opcode::BMNZ_V, + 1047 => Opcode::BMZI_B, + 1048 => Opcode::BMZ_V, + 1049 => Opcode::BNE, + 1050 => Opcode::BNE64, + 1051 => Opcode::BNEC, + 1052 => Opcode::BNEC64, + 1053 => Opcode::BNEC_MMR6, + 1054 => Opcode::BNEGI_B, + 1055 => Opcode::BNEGI_D, + 1056 => Opcode::BNEGI_H, + 1057 => Opcode::BNEGI_W, + 1058 => Opcode::BNEG_B, + 1059 => Opcode::BNEG_D, + 1060 => Opcode::BNEG_H, + 1061 => Opcode::BNEG_W, + 1062 => Opcode::BNEL, + 1063 => Opcode::BNEZ16_MM, + 1064 => Opcode::BNEZALC, + 1065 => Opcode::BNEZALC_MMR6, + 1066 => Opcode::BNEZC, + 1067 => Opcode::BNEZC16_MMR6, + 1068 => Opcode::BNEZC64, + 1069 => Opcode::BNEZC_MM, + 1070 => Opcode::BNEZC_MMR6, + 1071 => Opcode::BNE_MM, + 1072 => Opcode::BNVC, + 1073 => Opcode::BNVC_MMR6, + 1074 => Opcode::BNZ_B, + 1075 => Opcode::BNZ_D, + 1076 => Opcode::BNZ_H, + 1077 => Opcode::BNZ_V, + 1078 => Opcode::BNZ_W, + 1079 => Opcode::BOVC, + 1080 => Opcode::BOVC_MMR6, + 1081 => Opcode::BPOSGE32, + 1082 => Opcode::BPOSGE32C_MMR3, + 1083 => Opcode::BPOSGE32_MM, + 1084 => Opcode::BREAK, + 1085 => Opcode::BREAK16_MM, + 1086 => Opcode::BREAK16_MMR6, + 1087 => Opcode::BREAK_MM, + 1088 => Opcode::BREAK_MMR6, + 1089 => Opcode::BSELI_B, + 1090 => Opcode::BSEL_V, + 1091 => Opcode::BSETI_B, + 1092 => Opcode::BSETI_D, + 1093 => Opcode::BSETI_H, + 1094 => Opcode::BSETI_W, + 1095 => Opcode::BSET_B, + 1096 => Opcode::BSET_D, + 1097 => Opcode::BSET_H, + 1098 => Opcode::BSET_W, + 1099 => Opcode::BZ_B, + 1100 => Opcode::BZ_D, + 1101 => Opcode::BZ_H, + 1102 => Opcode::BZ_V, + 1103 => Opcode::BZ_W, + 1104 => Opcode::BeqzRxImm16, + 1105 => Opcode::BeqzRxImmX16, + 1106 => Opcode::Bimm16, + 1107 => Opcode::BimmX16, + 1108 => Opcode::BnezRxImm16, + 1109 => Opcode::BnezRxImmX16, + 1110 => Opcode::Break16, + 1111 => Opcode::Bteqz16, + 1112 => Opcode::BteqzX16, + 1113 => Opcode::Btnez16, + 1114 => Opcode::BtnezX16, + 1115 => Opcode::CACHE, + 1116 => Opcode::CACHEE, + 1117 => Opcode::CACHEE_MM, + 1118 => Opcode::CACHE_MM, + 1119 => Opcode::CACHE_MMR6, + 1120 => Opcode::CACHE_R6, + 1121 => Opcode::CEIL_L_D64, + 1122 => Opcode::CEIL_L_D_MMR6, + 1123 => Opcode::CEIL_L_S, + 1124 => Opcode::CEIL_L_S_MMR6, + 1125 => Opcode::CEIL_W_D32, + 1126 => Opcode::CEIL_W_D64, + 1127 => Opcode::CEIL_W_D_MMR6, + 1128 => Opcode::CEIL_W_MM, + 1129 => Opcode::CEIL_W_S, + 1130 => Opcode::CEIL_W_S_MM, + 1131 => Opcode::CEIL_W_S_MMR6, + 1132 => Opcode::CEQI_B, + 1133 => Opcode::CEQI_D, + 1134 => Opcode::CEQI_H, + 1135 => Opcode::CEQI_W, + 1136 => Opcode::CEQ_B, + 1137 => Opcode::CEQ_D, + 1138 => Opcode::CEQ_H, + 1139 => Opcode::CEQ_W, + 1140 => Opcode::CFC1, + 1141 => Opcode::CFC1_MM, + 1142 => Opcode::CFC2_MM, + 1143 => Opcode::CFCMSA, + 1144 => Opcode::CINS, + 1145 => Opcode::CINS32, + 1146 => Opcode::CINS64_32, + 1147 => Opcode::CINS_i32, + 1148 => Opcode::CLASS_D, + 1149 => Opcode::CLASS_D_MMR6, + 1150 => Opcode::CLASS_S, + 1151 => Opcode::CLASS_S_MMR6, + 1152 => Opcode::CLEI_S_B, + 1153 => Opcode::CLEI_S_D, + 1154 => Opcode::CLEI_S_H, + 1155 => Opcode::CLEI_S_W, + 1156 => Opcode::CLEI_U_B, + 1157 => Opcode::CLEI_U_D, + 1158 => Opcode::CLEI_U_H, + 1159 => Opcode::CLEI_U_W, + 1160 => Opcode::CLE_S_B, + 1161 => Opcode::CLE_S_D, + 1162 => Opcode::CLE_S_H, + 1163 => Opcode::CLE_S_W, + 1164 => Opcode::CLE_U_B, + 1165 => Opcode::CLE_U_D, + 1166 => Opcode::CLE_U_H, + 1167 => Opcode::CLE_U_W, + 1168 => Opcode::CLO, + 1169 => Opcode::CLO_MM, + 1170 => Opcode::CLO_MMR6, + 1171 => Opcode::CLO_R6, + 1172 => Opcode::CLTI_S_B, + 1173 => Opcode::CLTI_S_D, + 1174 => Opcode::CLTI_S_H, + 1175 => Opcode::CLTI_S_W, + 1176 => Opcode::CLTI_U_B, + 1177 => Opcode::CLTI_U_D, + 1178 => Opcode::CLTI_U_H, + 1179 => Opcode::CLTI_U_W, + 1180 => Opcode::CLT_S_B, + 1181 => Opcode::CLT_S_D, + 1182 => Opcode::CLT_S_H, + 1183 => Opcode::CLT_S_W, + 1184 => Opcode::CLT_U_B, + 1185 => Opcode::CLT_U_D, + 1186 => Opcode::CLT_U_H, + 1187 => Opcode::CLT_U_W, + 1188 => Opcode::CLZ, + 1189 => Opcode::CLZ_MM, + 1190 => Opcode::CLZ_MMR6, + 1191 => Opcode::CLZ_R6, + 1192 => Opcode::CMPGDU_EQ_QB, + 1193 => Opcode::CMPGDU_EQ_QB_MMR2, + 1194 => Opcode::CMPGDU_LE_QB, + 1195 => Opcode::CMPGDU_LE_QB_MMR2, + 1196 => Opcode::CMPGDU_LT_QB, + 1197 => Opcode::CMPGDU_LT_QB_MMR2, + 1198 => Opcode::CMPGU_EQ_QB, + 1199 => Opcode::CMPGU_EQ_QB_MM, + 1200 => Opcode::CMPGU_LE_QB, + 1201 => Opcode::CMPGU_LE_QB_MM, + 1202 => Opcode::CMPGU_LT_QB, + 1203 => Opcode::CMPGU_LT_QB_MM, + 1204 => Opcode::CMPU_EQ_QB, + 1205 => Opcode::CMPU_EQ_QB_MM, + 1206 => Opcode::CMPU_LE_QB, + 1207 => Opcode::CMPU_LE_QB_MM, + 1208 => Opcode::CMPU_LT_QB, + 1209 => Opcode::CMPU_LT_QB_MM, + 1210 => Opcode::CMP_AF_D_MMR6, + 1211 => Opcode::CMP_AF_S_MMR6, + 1212 => Opcode::CMP_EQ_D, + 1213 => Opcode::CMP_EQ_D_MMR6, + 1214 => Opcode::CMP_EQ_PH, + 1215 => Opcode::CMP_EQ_PH_MM, + 1216 => Opcode::CMP_EQ_S, + 1217 => Opcode::CMP_EQ_S_MMR6, + 1218 => Opcode::CMP_F_D, + 1219 => Opcode::CMP_F_S, + 1220 => Opcode::CMP_LE_D, + 1221 => Opcode::CMP_LE_D_MMR6, + 1222 => Opcode::CMP_LE_PH, + 1223 => Opcode::CMP_LE_PH_MM, + 1224 => Opcode::CMP_LE_S, + 1225 => Opcode::CMP_LE_S_MMR6, + 1226 => Opcode::CMP_LT_D, + 1227 => Opcode::CMP_LT_D_MMR6, + 1228 => Opcode::CMP_LT_PH, + 1229 => Opcode::CMP_LT_PH_MM, + 1230 => Opcode::CMP_LT_S, + 1231 => Opcode::CMP_LT_S_MMR6, + 1232 => Opcode::CMP_SAF_D, + 1233 => Opcode::CMP_SAF_D_MMR6, + 1234 => Opcode::CMP_SAF_S, + 1235 => Opcode::CMP_SAF_S_MMR6, + 1236 => Opcode::CMP_SEQ_D, + 1237 => Opcode::CMP_SEQ_D_MMR6, + 1238 => Opcode::CMP_SEQ_S, + 1239 => Opcode::CMP_SEQ_S_MMR6, + 1240 => Opcode::CMP_SLE_D, + 1241 => Opcode::CMP_SLE_D_MMR6, + 1242 => Opcode::CMP_SLE_S, + 1243 => Opcode::CMP_SLE_S_MMR6, + 1244 => Opcode::CMP_SLT_D, + 1245 => Opcode::CMP_SLT_D_MMR6, + 1246 => Opcode::CMP_SLT_S, + 1247 => Opcode::CMP_SLT_S_MMR6, + 1248 => Opcode::CMP_SUEQ_D, + 1249 => Opcode::CMP_SUEQ_D_MMR6, + 1250 => Opcode::CMP_SUEQ_S, + 1251 => Opcode::CMP_SUEQ_S_MMR6, + 1252 => Opcode::CMP_SULE_D, + 1253 => Opcode::CMP_SULE_D_MMR6, + 1254 => Opcode::CMP_SULE_S, + 1255 => Opcode::CMP_SULE_S_MMR6, + 1256 => Opcode::CMP_SULT_D, + 1257 => Opcode::CMP_SULT_D_MMR6, + 1258 => Opcode::CMP_SULT_S, + 1259 => Opcode::CMP_SULT_S_MMR6, + 1260 => Opcode::CMP_SUN_D, + 1261 => Opcode::CMP_SUN_D_MMR6, + 1262 => Opcode::CMP_SUN_S, + 1263 => Opcode::CMP_SUN_S_MMR6, + 1264 => Opcode::CMP_UEQ_D, + 1265 => Opcode::CMP_UEQ_D_MMR6, + 1266 => Opcode::CMP_UEQ_S, + 1267 => Opcode::CMP_UEQ_S_MMR6, + 1268 => Opcode::CMP_ULE_D, + 1269 => Opcode::CMP_ULE_D_MMR6, + 1270 => Opcode::CMP_ULE_S, + 1271 => Opcode::CMP_ULE_S_MMR6, + 1272 => Opcode::CMP_ULT_D, + 1273 => Opcode::CMP_ULT_D_MMR6, + 1274 => Opcode::CMP_ULT_S, + 1275 => Opcode::CMP_ULT_S_MMR6, + 1276 => Opcode::CMP_UN_D, + 1277 => Opcode::CMP_UN_D_MMR6, + 1278 => Opcode::CMP_UN_S, + 1279 => Opcode::CMP_UN_S_MMR6, + 1280 => Opcode::COPY_S_B, + 1281 => Opcode::COPY_S_D, + 1282 => Opcode::COPY_S_H, + 1283 => Opcode::COPY_S_W, + 1284 => Opcode::COPY_U_B, + 1285 => Opcode::COPY_U_H, + 1286 => Opcode::COPY_U_W, + 1287 => Opcode::CRC32B, + 1288 => Opcode::CRC32CB, + 1289 => Opcode::CRC32CD, + 1290 => Opcode::CRC32CH, + 1291 => Opcode::CRC32CW, + 1292 => Opcode::CRC32D, + 1293 => Opcode::CRC32H, + 1294 => Opcode::CRC32W, + 1295 => Opcode::CTC1, + 1296 => Opcode::CTC1_MM, + 1297 => Opcode::CTC2_MM, + 1298 => Opcode::CTCMSA, + 1299 => Opcode::CVT_D32_S, + 1300 => Opcode::CVT_D32_S_MM, + 1301 => Opcode::CVT_D32_W, + 1302 => Opcode::CVT_D32_W_MM, + 1303 => Opcode::CVT_D64_L, + 1304 => Opcode::CVT_D64_S, + 1305 => Opcode::CVT_D64_S_MM, + 1306 => Opcode::CVT_D64_W, + 1307 => Opcode::CVT_D64_W_MM, + 1308 => Opcode::CVT_D_L_MMR6, + 1309 => Opcode::CVT_L_D64, + 1310 => Opcode::CVT_L_D64_MM, + 1311 => Opcode::CVT_L_D_MMR6, + 1312 => Opcode::CVT_L_S, + 1313 => Opcode::CVT_L_S_MM, + 1314 => Opcode::CVT_L_S_MMR6, + 1315 => Opcode::CVT_PS_PW64, + 1316 => Opcode::CVT_PS_S64, + 1317 => Opcode::CVT_PW_PS64, + 1318 => Opcode::CVT_S_D32, + 1319 => Opcode::CVT_S_D32_MM, + 1320 => Opcode::CVT_S_D64, + 1321 => Opcode::CVT_S_D64_MM, + 1322 => Opcode::CVT_S_L, + 1323 => Opcode::CVT_S_L_MMR6, + 1324 => Opcode::CVT_S_PL64, + 1325 => Opcode::CVT_S_PU64, + 1326 => Opcode::CVT_S_W, + 1327 => Opcode::CVT_S_W_MM, + 1328 => Opcode::CVT_S_W_MMR6, + 1329 => Opcode::CVT_W_D32, + 1330 => Opcode::CVT_W_D32_MM, + 1331 => Opcode::CVT_W_D64, + 1332 => Opcode::CVT_W_D64_MM, + 1333 => Opcode::CVT_W_S, + 1334 => Opcode::CVT_W_S_MM, + 1335 => Opcode::CVT_W_S_MMR6, + 1336 => Opcode::C_EQ_D32, + 1337 => Opcode::C_EQ_D32_MM, + 1338 => Opcode::C_EQ_D64, + 1339 => Opcode::C_EQ_D64_MM, + 1340 => Opcode::C_EQ_S, + 1341 => Opcode::C_EQ_S_MM, + 1342 => Opcode::C_F_D32, + 1343 => Opcode::C_F_D32_MM, + 1344 => Opcode::C_F_D64, + 1345 => Opcode::C_F_D64_MM, + 1346 => Opcode::C_F_S, + 1347 => Opcode::C_F_S_MM, + 1348 => Opcode::C_LE_D32, + 1349 => Opcode::C_LE_D32_MM, + 1350 => Opcode::C_LE_D64, + 1351 => Opcode::C_LE_D64_MM, + 1352 => Opcode::C_LE_S, + 1353 => Opcode::C_LE_S_MM, + 1354 => Opcode::C_LT_D32, + 1355 => Opcode::C_LT_D32_MM, + 1356 => Opcode::C_LT_D64, + 1357 => Opcode::C_LT_D64_MM, + 1358 => Opcode::C_LT_S, + 1359 => Opcode::C_LT_S_MM, + 1360 => Opcode::C_NGE_D32, + 1361 => Opcode::C_NGE_D32_MM, + 1362 => Opcode::C_NGE_D64, + 1363 => Opcode::C_NGE_D64_MM, + 1364 => Opcode::C_NGE_S, + 1365 => Opcode::C_NGE_S_MM, + 1366 => Opcode::C_NGLE_D32, + 1367 => Opcode::C_NGLE_D32_MM, + 1368 => Opcode::C_NGLE_D64, + 1369 => Opcode::C_NGLE_D64_MM, + 1370 => Opcode::C_NGLE_S, + 1371 => Opcode::C_NGLE_S_MM, + 1372 => Opcode::C_NGL_D32, + 1373 => Opcode::C_NGL_D32_MM, + 1374 => Opcode::C_NGL_D64, + 1375 => Opcode::C_NGL_D64_MM, + 1376 => Opcode::C_NGL_S, + 1377 => Opcode::C_NGL_S_MM, + 1378 => Opcode::C_NGT_D32, + 1379 => Opcode::C_NGT_D32_MM, + 1380 => Opcode::C_NGT_D64, + 1381 => Opcode::C_NGT_D64_MM, + 1382 => Opcode::C_NGT_S, + 1383 => Opcode::C_NGT_S_MM, + 1384 => Opcode::C_OLE_D32, + 1385 => Opcode::C_OLE_D32_MM, + 1386 => Opcode::C_OLE_D64, + 1387 => Opcode::C_OLE_D64_MM, + 1388 => Opcode::C_OLE_S, + 1389 => Opcode::C_OLE_S_MM, + 1390 => Opcode::C_OLT_D32, + 1391 => Opcode::C_OLT_D32_MM, + 1392 => Opcode::C_OLT_D64, + 1393 => Opcode::C_OLT_D64_MM, + 1394 => Opcode::C_OLT_S, + 1395 => Opcode::C_OLT_S_MM, + 1396 => Opcode::C_SEQ_D32, + 1397 => Opcode::C_SEQ_D32_MM, + 1398 => Opcode::C_SEQ_D64, + 1399 => Opcode::C_SEQ_D64_MM, + 1400 => Opcode::C_SEQ_S, + 1401 => Opcode::C_SEQ_S_MM, + 1402 => Opcode::C_SF_D32, + 1403 => Opcode::C_SF_D32_MM, + 1404 => Opcode::C_SF_D64, + 1405 => Opcode::C_SF_D64_MM, + 1406 => Opcode::C_SF_S, + 1407 => Opcode::C_SF_S_MM, + 1408 => Opcode::C_UEQ_D32, + 1409 => Opcode::C_UEQ_D32_MM, + 1410 => Opcode::C_UEQ_D64, + 1411 => Opcode::C_UEQ_D64_MM, + 1412 => Opcode::C_UEQ_S, + 1413 => Opcode::C_UEQ_S_MM, + 1414 => Opcode::C_ULE_D32, + 1415 => Opcode::C_ULE_D32_MM, + 1416 => Opcode::C_ULE_D64, + 1417 => Opcode::C_ULE_D64_MM, + 1418 => Opcode::C_ULE_S, + 1419 => Opcode::C_ULE_S_MM, + 1420 => Opcode::C_ULT_D32, + 1421 => Opcode::C_ULT_D32_MM, + 1422 => Opcode::C_ULT_D64, + 1423 => Opcode::C_ULT_D64_MM, + 1424 => Opcode::C_ULT_S, + 1425 => Opcode::C_ULT_S_MM, + 1426 => Opcode::C_UN_D32, + 1427 => Opcode::C_UN_D32_MM, + 1428 => Opcode::C_UN_D64, + 1429 => Opcode::C_UN_D64_MM, + 1430 => Opcode::C_UN_S, + 1431 => Opcode::C_UN_S_MM, + 1432 => Opcode::CmpRxRy16, + 1433 => Opcode::CmpiRxImm16, + 1434 => Opcode::CmpiRxImmX16, + 1435 => Opcode::DADD, + 1436 => Opcode::DADDi, + 1437 => Opcode::DADDiu, + 1438 => Opcode::DADDu, + 1439 => Opcode::DAHI, + 1440 => Opcode::DALIGN, + 1441 => Opcode::DATI, + 1442 => Opcode::DAUI, + 1443 => Opcode::DBITSWAP, + 1444 => Opcode::DCLO, + 1445 => Opcode::DCLO_R6, + 1446 => Opcode::DCLZ, + 1447 => Opcode::DCLZ_R6, + 1448 => Opcode::DDIV, + 1449 => Opcode::DDIVU, + 1450 => Opcode::DERET, + 1451 => Opcode::DERET_MM, + 1452 => Opcode::DERET_MMR6, + 1453 => Opcode::DEXT, + 1454 => Opcode::DEXT64_32, + 1455 => Opcode::DEXTM, + 1456 => Opcode::DEXTU, + 1457 => Opcode::DI, + 1458 => Opcode::DINS, + 1459 => Opcode::DINSM, + 1460 => Opcode::DINSU, + 1461 => Opcode::DIV, + 1462 => Opcode::DIVU, + 1463 => Opcode::DIVU_MMR6, + 1464 => Opcode::DIV_MMR6, + 1465 => Opcode::DIV_S_B, + 1466 => Opcode::DIV_S_D, + 1467 => Opcode::DIV_S_H, + 1468 => Opcode::DIV_S_W, + 1469 => Opcode::DIV_U_B, + 1470 => Opcode::DIV_U_D, + 1471 => Opcode::DIV_U_H, + 1472 => Opcode::DIV_U_W, + 1473 => Opcode::DI_MM, + 1474 => Opcode::DI_MMR6, + 1475 => Opcode::DLSA, + 1476 => Opcode::DLSA_R6, + 1477 => Opcode::DMFC0, + 1478 => Opcode::DMFC1, + 1479 => Opcode::DMFC2, + 1480 => Opcode::DMFC2_OCTEON, + 1481 => Opcode::DMFGC0, + 1482 => Opcode::DMOD, + 1483 => Opcode::DMODU, + 1484 => Opcode::DMT, + 1485 => Opcode::DMTC0, + 1486 => Opcode::DMTC1, + 1487 => Opcode::DMTC2, + 1488 => Opcode::DMTC2_OCTEON, + 1489 => Opcode::DMTGC0, + 1490 => Opcode::DMUH, + 1491 => Opcode::DMUHU, + 1492 => Opcode::DMUL, + 1493 => Opcode::DMULT, + 1494 => Opcode::DMULTu, + 1495 => Opcode::DMULU, + 1496 => Opcode::DMUL_R6, + 1497 => Opcode::DOTP_S_D, + 1498 => Opcode::DOTP_S_H, + 1499 => Opcode::DOTP_S_W, + 1500 => Opcode::DOTP_U_D, + 1501 => Opcode::DOTP_U_H, + 1502 => Opcode::DOTP_U_W, + 1503 => Opcode::DPADD_S_D, + 1504 => Opcode::DPADD_S_H, + 1505 => Opcode::DPADD_S_W, + 1506 => Opcode::DPADD_U_D, + 1507 => Opcode::DPADD_U_H, + 1508 => Opcode::DPADD_U_W, + 1509 => Opcode::DPAQX_SA_W_PH, + 1510 => Opcode::DPAQX_SA_W_PH_MMR2, + 1511 => Opcode::DPAQX_S_W_PH, + 1512 => Opcode::DPAQX_S_W_PH_MMR2, + 1513 => Opcode::DPAQ_SA_L_W, + 1514 => Opcode::DPAQ_SA_L_W_MM, + 1515 => Opcode::DPAQ_S_W_PH, + 1516 => Opcode::DPAQ_S_W_PH_MM, + 1517 => Opcode::DPAU_H_QBL, + 1518 => Opcode::DPAU_H_QBL_MM, + 1519 => Opcode::DPAU_H_QBR, + 1520 => Opcode::DPAU_H_QBR_MM, + 1521 => Opcode::DPAX_W_PH, + 1522 => Opcode::DPAX_W_PH_MMR2, + 1523 => Opcode::DPA_W_PH, + 1524 => Opcode::DPA_W_PH_MMR2, + 1525 => Opcode::DPOP, + 1526 => Opcode::DPSQX_SA_W_PH, + 1527 => Opcode::DPSQX_SA_W_PH_MMR2, + 1528 => Opcode::DPSQX_S_W_PH, + 1529 => Opcode::DPSQX_S_W_PH_MMR2, + 1530 => Opcode::DPSQ_SA_L_W, + 1531 => Opcode::DPSQ_SA_L_W_MM, + 1532 => Opcode::DPSQ_S_W_PH, + 1533 => Opcode::DPSQ_S_W_PH_MM, + 1534 => Opcode::DPSUB_S_D, + 1535 => Opcode::DPSUB_S_H, + 1536 => Opcode::DPSUB_S_W, + 1537 => Opcode::DPSUB_U_D, + 1538 => Opcode::DPSUB_U_H, + 1539 => Opcode::DPSUB_U_W, + 1540 => Opcode::DPSU_H_QBL, + 1541 => Opcode::DPSU_H_QBL_MM, + 1542 => Opcode::DPSU_H_QBR, + 1543 => Opcode::DPSU_H_QBR_MM, + 1544 => Opcode::DPSX_W_PH, + 1545 => Opcode::DPSX_W_PH_MMR2, + 1546 => Opcode::DPS_W_PH, + 1547 => Opcode::DPS_W_PH_MMR2, + 1548 => Opcode::DROTR, + 1549 => Opcode::DROTR32, + 1550 => Opcode::DROTRV, + 1551 => Opcode::DSBH, + 1552 => Opcode::DSDIV, + 1553 => Opcode::DSHD, + 1554 => Opcode::DSLL, + 1555 => Opcode::DSLL32, + 1556 => Opcode::DSLL64_32, + 1557 => Opcode::DSLLV, + 1558 => Opcode::DSRA, + 1559 => Opcode::DSRA32, + 1560 => Opcode::DSRAV, + 1561 => Opcode::DSRL, + 1562 => Opcode::DSRL32, + 1563 => Opcode::DSRLV, + 1564 => Opcode::DSUB, + 1565 => Opcode::DSUBu, + 1566 => Opcode::DUDIV, + 1567 => Opcode::DVP, + 1568 => Opcode::DVPE, + 1569 => Opcode::DVP_MMR6, + 1570 => Opcode::DivRxRy16, + 1571 => Opcode::DivuRxRy16, + 1572 => Opcode::EHB, + 1573 => Opcode::EHB_MM, + 1574 => Opcode::EHB_MMR6, + 1575 => Opcode::EI, + 1576 => Opcode::EI_MM, + 1577 => Opcode::EI_MMR6, + 1578 => Opcode::EMT, + 1579 => Opcode::ERET, + 1580 => Opcode::ERETNC, + 1581 => Opcode::ERETNC_MMR6, + 1582 => Opcode::ERET_MM, + 1583 => Opcode::ERET_MMR6, + 1584 => Opcode::EVP, + 1585 => Opcode::EVPE, + 1586 => Opcode::EVP_MMR6, + 1587 => Opcode::EXT, + 1588 => Opcode::EXTP, + 1589 => Opcode::EXTPDP, + 1590 => Opcode::EXTPDPV, + 1591 => Opcode::EXTPDPV_MM, + 1592 => Opcode::EXTPDP_MM, + 1593 => Opcode::EXTPV, + 1594 => Opcode::EXTPV_MM, + 1595 => Opcode::EXTP_MM, + 1596 => Opcode::EXTRV_RS_W, + 1597 => Opcode::EXTRV_RS_W_MM, + 1598 => Opcode::EXTRV_R_W, + 1599 => Opcode::EXTRV_R_W_MM, + 1600 => Opcode::EXTRV_S_H, + 1601 => Opcode::EXTRV_S_H_MM, + 1602 => Opcode::EXTRV_W, + 1603 => Opcode::EXTRV_W_MM, + 1604 => Opcode::EXTR_RS_W, + 1605 => Opcode::EXTR_RS_W_MM, + 1606 => Opcode::EXTR_R_W, + 1607 => Opcode::EXTR_R_W_MM, + 1608 => Opcode::EXTR_S_H, + 1609 => Opcode::EXTR_S_H_MM, + 1610 => Opcode::EXTR_W, + 1611 => Opcode::EXTR_W_MM, + 1612 => Opcode::EXTS, + 1613 => Opcode::EXTS32, + 1614 => Opcode::EXT_MM, + 1615 => Opcode::EXT_MMR6, + 1616 => Opcode::FABS_D32, + 1617 => Opcode::FABS_D32_MM, + 1618 => Opcode::FABS_D64, + 1619 => Opcode::FABS_D64_MM, + 1620 => Opcode::FABS_S, + 1621 => Opcode::FABS_S_MM, + 1622 => Opcode::FADD_D, + 1623 => Opcode::FADD_D32, + 1624 => Opcode::FADD_D32_MM, + 1625 => Opcode::FADD_D64, + 1626 => Opcode::FADD_D64_MM, + 1627 => Opcode::FADD_PS64, + 1628 => Opcode::FADD_S, + 1629 => Opcode::FADD_S_MM, + 1630 => Opcode::FADD_S_MMR6, + 1631 => Opcode::FADD_W, + 1632 => Opcode::FCAF_D, + 1633 => Opcode::FCAF_W, + 1634 => Opcode::FCEQ_D, + 1635 => Opcode::FCEQ_W, + 1636 => Opcode::FCLASS_D, + 1637 => Opcode::FCLASS_W, + 1638 => Opcode::FCLE_D, + 1639 => Opcode::FCLE_W, + 1640 => Opcode::FCLT_D, + 1641 => Opcode::FCLT_W, + 1642 => Opcode::FCMP_D32, + 1643 => Opcode::FCMP_D32_MM, + 1644 => Opcode::FCMP_D64, + 1645 => Opcode::FCMP_S32, + 1646 => Opcode::FCMP_S32_MM, + 1647 => Opcode::FCNE_D, + 1648 => Opcode::FCNE_W, + 1649 => Opcode::FCOR_D, + 1650 => Opcode::FCOR_W, + 1651 => Opcode::FCUEQ_D, + 1652 => Opcode::FCUEQ_W, + 1653 => Opcode::FCULE_D, + 1654 => Opcode::FCULE_W, + 1655 => Opcode::FCULT_D, + 1656 => Opcode::FCULT_W, + 1657 => Opcode::FCUNE_D, + 1658 => Opcode::FCUNE_W, + 1659 => Opcode::FCUN_D, + 1660 => Opcode::FCUN_W, + 1661 => Opcode::FDIV_D, + 1662 => Opcode::FDIV_D32, + 1663 => Opcode::FDIV_D32_MM, + 1664 => Opcode::FDIV_D64, + 1665 => Opcode::FDIV_D64_MM, + 1666 => Opcode::FDIV_S, + 1667 => Opcode::FDIV_S_MM, + 1668 => Opcode::FDIV_S_MMR6, + 1669 => Opcode::FDIV_W, + 1670 => Opcode::FEXDO_H, + 1671 => Opcode::FEXDO_W, + 1672 => Opcode::FEXP2_D, + 1673 => Opcode::FEXP2_W, + 1674 => Opcode::FEXUPL_D, + 1675 => Opcode::FEXUPL_W, + 1676 => Opcode::FEXUPR_D, + 1677 => Opcode::FEXUPR_W, + 1678 => Opcode::FFINT_S_D, + 1679 => Opcode::FFINT_S_W, + 1680 => Opcode::FFINT_U_D, + 1681 => Opcode::FFINT_U_W, + 1682 => Opcode::FFQL_D, + 1683 => Opcode::FFQL_W, + 1684 => Opcode::FFQR_D, + 1685 => Opcode::FFQR_W, + 1686 => Opcode::FILL_B, + 1687 => Opcode::FILL_D, + 1688 => Opcode::FILL_H, + 1689 => Opcode::FILL_W, + 1690 => Opcode::FLOG2_D, + 1691 => Opcode::FLOG2_W, + 1692 => Opcode::FLOOR_L_D64, + 1693 => Opcode::FLOOR_L_D_MMR6, + 1694 => Opcode::FLOOR_L_S, + 1695 => Opcode::FLOOR_L_S_MMR6, + 1696 => Opcode::FLOOR_W_D32, + 1697 => Opcode::FLOOR_W_D64, + 1698 => Opcode::FLOOR_W_D_MMR6, + 1699 => Opcode::FLOOR_W_MM, + 1700 => Opcode::FLOOR_W_S, + 1701 => Opcode::FLOOR_W_S_MM, + 1702 => Opcode::FLOOR_W_S_MMR6, + 1703 => Opcode::FMADD_D, + 1704 => Opcode::FMADD_W, + 1705 => Opcode::FMAX_A_D, + 1706 => Opcode::FMAX_A_W, + 1707 => Opcode::FMAX_D, + 1708 => Opcode::FMAX_W, + 1709 => Opcode::FMIN_A_D, + 1710 => Opcode::FMIN_A_W, + 1711 => Opcode::FMIN_D, + 1712 => Opcode::FMIN_W, + 1713 => Opcode::FMOV_D32, + 1714 => Opcode::FMOV_D32_MM, + 1715 => Opcode::FMOV_D64, + 1716 => Opcode::FMOV_D64_MM, + 1717 => Opcode::FMOV_D_MMR6, + 1718 => Opcode::FMOV_S, + 1719 => Opcode::FMOV_S_MM, + 1720 => Opcode::FMOV_S_MMR6, + 1721 => Opcode::FMSUB_D, + 1722 => Opcode::FMSUB_W, + 1723 => Opcode::FMUL_D, + 1724 => Opcode::FMUL_D32, + 1725 => Opcode::FMUL_D32_MM, + 1726 => Opcode::FMUL_D64, + 1727 => Opcode::FMUL_D64_MM, + 1728 => Opcode::FMUL_PS64, + 1729 => Opcode::FMUL_S, + 1730 => Opcode::FMUL_S_MM, + 1731 => Opcode::FMUL_S_MMR6, + 1732 => Opcode::FMUL_W, + 1733 => Opcode::FNEG_D32, + 1734 => Opcode::FNEG_D32_MM, + 1735 => Opcode::FNEG_D64, + 1736 => Opcode::FNEG_D64_MM, + 1737 => Opcode::FNEG_S, + 1738 => Opcode::FNEG_S_MM, + 1739 => Opcode::FNEG_S_MMR6, + 1740 => Opcode::FORK, + 1741 => Opcode::FRCP_D, + 1742 => Opcode::FRCP_W, + 1743 => Opcode::FRINT_D, + 1744 => Opcode::FRINT_W, + 1745 => Opcode::FRSQRT_D, + 1746 => Opcode::FRSQRT_W, + 1747 => Opcode::FSAF_D, + 1748 => Opcode::FSAF_W, + 1749 => Opcode::FSEQ_D, + 1750 => Opcode::FSEQ_W, + 1751 => Opcode::FSLE_D, + 1752 => Opcode::FSLE_W, + 1753 => Opcode::FSLT_D, + 1754 => Opcode::FSLT_W, + 1755 => Opcode::FSNE_D, + 1756 => Opcode::FSNE_W, + 1757 => Opcode::FSOR_D, + 1758 => Opcode::FSOR_W, + 1759 => Opcode::FSQRT_D, + 1760 => Opcode::FSQRT_D32, + 1761 => Opcode::FSQRT_D32_MM, + 1762 => Opcode::FSQRT_D64, + 1763 => Opcode::FSQRT_D64_MM, + 1764 => Opcode::FSQRT_S, + 1765 => Opcode::FSQRT_S_MM, + 1766 => Opcode::FSQRT_W, + 1767 => Opcode::FSUB_D, + 1768 => Opcode::FSUB_D32, + 1769 => Opcode::FSUB_D32_MM, + 1770 => Opcode::FSUB_D64, + 1771 => Opcode::FSUB_D64_MM, + 1772 => Opcode::FSUB_PS64, + 1773 => Opcode::FSUB_S, + 1774 => Opcode::FSUB_S_MM, + 1775 => Opcode::FSUB_S_MMR6, + 1776 => Opcode::FSUB_W, + 1777 => Opcode::FSUEQ_D, + 1778 => Opcode::FSUEQ_W, + 1779 => Opcode::FSULE_D, + 1780 => Opcode::FSULE_W, + 1781 => Opcode::FSULT_D, + 1782 => Opcode::FSULT_W, + 1783 => Opcode::FSUNE_D, + 1784 => Opcode::FSUNE_W, + 1785 => Opcode::FSUN_D, + 1786 => Opcode::FSUN_W, + 1787 => Opcode::FTINT_S_D, + 1788 => Opcode::FTINT_S_W, + 1789 => Opcode::FTINT_U_D, + 1790 => Opcode::FTINT_U_W, + 1791 => Opcode::FTQ_H, + 1792 => Opcode::FTQ_W, + 1793 => Opcode::FTRUNC_S_D, + 1794 => Opcode::FTRUNC_S_W, + 1795 => Opcode::FTRUNC_U_D, + 1796 => Opcode::FTRUNC_U_W, + 1797 => Opcode::GINVI, + 1798 => Opcode::GINVI_MMR6, + 1799 => Opcode::GINVT, + 1800 => Opcode::GINVT_MMR6, + 1801 => Opcode::HADD_S_D, + 1802 => Opcode::HADD_S_H, + 1803 => Opcode::HADD_S_W, + 1804 => Opcode::HADD_U_D, + 1805 => Opcode::HADD_U_H, + 1806 => Opcode::HADD_U_W, + 1807 => Opcode::HSUB_S_D, + 1808 => Opcode::HSUB_S_H, + 1809 => Opcode::HSUB_S_W, + 1810 => Opcode::HSUB_U_D, + 1811 => Opcode::HSUB_U_H, + 1812 => Opcode::HSUB_U_W, + 1813 => Opcode::HYPCALL, + 1814 => Opcode::HYPCALL_MM, + 1815 => Opcode::ILVEV_B, + 1816 => Opcode::ILVEV_D, + 1817 => Opcode::ILVEV_H, + 1818 => Opcode::ILVEV_W, + 1819 => Opcode::ILVL_B, + 1820 => Opcode::ILVL_D, + 1821 => Opcode::ILVL_H, + 1822 => Opcode::ILVL_W, + 1823 => Opcode::ILVOD_B, + 1824 => Opcode::ILVOD_D, + 1825 => Opcode::ILVOD_H, + 1826 => Opcode::ILVOD_W, + 1827 => Opcode::ILVR_B, + 1828 => Opcode::ILVR_D, + 1829 => Opcode::ILVR_H, + 1830 => Opcode::ILVR_W, + 1831 => Opcode::INS, + 1832 => Opcode::INSERT_B, + 1833 => Opcode::INSERT_D, + 1834 => Opcode::INSERT_H, + 1835 => Opcode::INSERT_W, + 1836 => Opcode::INSV, + 1837 => Opcode::INSVE_B, + 1838 => Opcode::INSVE_D, + 1839 => Opcode::INSVE_H, + 1840 => Opcode::INSVE_W, + 1841 => Opcode::INSV_MM, + 1842 => Opcode::INS_MM, + 1843 => Opcode::INS_MMR6, + 1844 => Opcode::J, + 1845 => Opcode::JAL, + 1846 => Opcode::JALR, + 1847 => Opcode::JALR16_MM, + 1848 => Opcode::JALR64, + 1849 => Opcode::JALRC16_MMR6, + 1850 => Opcode::JALRC_HB_MMR6, + 1851 => Opcode::JALRC_MMR6, + 1852 => Opcode::JALRS16_MM, + 1853 => Opcode::JALRS_MM, + 1854 => Opcode::JALR_HB, + 1855 => Opcode::JALR_HB64, + 1856 => Opcode::JALR_MM, + 1857 => Opcode::JALS_MM, + 1858 => Opcode::JALX, + 1859 => Opcode::JALX_MM, + 1860 => Opcode::JAL_MM, + 1861 => Opcode::JIALC, + 1862 => Opcode::JIALC64, + 1863 => Opcode::JIALC_MMR6, + 1864 => Opcode::JIC, + 1865 => Opcode::JIC64, + 1866 => Opcode::JIC_MMR6, + 1867 => Opcode::JR, + 1868 => Opcode::JR16_MM, + 1869 => Opcode::JR64, + 1870 => Opcode::JRADDIUSP, + 1871 => Opcode::JRC16_MM, + 1872 => Opcode::JRC16_MMR6, + 1873 => Opcode::JRCADDIUSP_MMR6, + 1874 => Opcode::JR_HB, + 1875 => Opcode::JR_HB64, + 1876 => Opcode::JR_HB64_R6, + 1877 => Opcode::JR_HB_R6, + 1878 => Opcode::JR_MM, + 1879 => Opcode::J_MM, + 1880 => Opcode::Jal16, + 1881 => Opcode::JalB16, + 1882 => Opcode::JrRa16, + 1883 => Opcode::JrcRa16, + 1884 => Opcode::JrcRx16, + 1885 => Opcode::JumpLinkReg16, + 1886 => Opcode::LB, + 1887 => Opcode::LB64, + 1888 => Opcode::LBE, + 1889 => Opcode::LBE_MM, + 1890 => Opcode::LBU16_MM, + 1891 => Opcode::LBUX, + 1892 => Opcode::LBUX_MM, + 1893 => Opcode::LBU_MMR6, + 1894 => Opcode::LB_MM, + 1895 => Opcode::LB_MMR6, + 1896 => Opcode::LBu, + 1897 => Opcode::LBu64, + 1898 => Opcode::LBuE, + 1899 => Opcode::LBuE_MM, + 1900 => Opcode::LBu_MM, + 1901 => Opcode::LD, + 1902 => Opcode::LDC1, + 1903 => Opcode::LDC164, + 1904 => Opcode::LDC1_D64_MMR6, + 1905 => Opcode::LDC1_MM_D32, + 1906 => Opcode::LDC1_MM_D64, + 1907 => Opcode::LDC2, + 1908 => Opcode::LDC2_MMR6, + 1909 => Opcode::LDC2_R6, + 1910 => Opcode::LDC3, + 1911 => Opcode::LDI_B, + 1912 => Opcode::LDI_D, + 1913 => Opcode::LDI_H, + 1914 => Opcode::LDI_W, + 1915 => Opcode::LDL, + 1916 => Opcode::LDPC, + 1917 => Opcode::LDR, + 1918 => Opcode::LDXC1, + 1919 => Opcode::LDXC164, + 1920 => Opcode::LD_B, + 1921 => Opcode::LD_D, + 1922 => Opcode::LD_H, + 1923 => Opcode::LD_W, + 1924 => Opcode::LEA_ADDiu, + 1925 => Opcode::LEA_ADDiu64, + 1926 => Opcode::LEA_ADDiu_MM, + 1927 => Opcode::LH, + 1928 => Opcode::LH64, + 1929 => Opcode::LHE, + 1930 => Opcode::LHE_MM, + 1931 => Opcode::LHU16_MM, + 1932 => Opcode::LHX, + 1933 => Opcode::LHX_MM, + 1934 => Opcode::LH_MM, + 1935 => Opcode::LHu, + 1936 => Opcode::LHu64, + 1937 => Opcode::LHuE, + 1938 => Opcode::LHuE_MM, + 1939 => Opcode::LHu_MM, + 1940 => Opcode::LI16_MM, + 1941 => Opcode::LI16_MMR6, + 1942 => Opcode::LL, + 1943 => Opcode::LL64, + 1944 => Opcode::LL64_R6, + 1945 => Opcode::LLD, + 1946 => Opcode::LLD_R6, + 1947 => Opcode::LLE, + 1948 => Opcode::LLE_MM, + 1949 => Opcode::LL_MM, + 1950 => Opcode::LL_MMR6, + 1951 => Opcode::LL_R6, + 1952 => Opcode::LSA, + 1953 => Opcode::LSA_MMR6, + 1954 => Opcode::LSA_R6, + 1955 => Opcode::LUI_MMR6, + 1956 => Opcode::LUXC1, + 1957 => Opcode::LUXC164, + 1958 => Opcode::LUXC1_MM, + 1959 => Opcode::LUi, + 1960 => Opcode::LUi64, + 1961 => Opcode::LUi_MM, + 1962 => Opcode::LW, + 1963 => Opcode::LW16_MM, + 1964 => Opcode::LW64, + 1965 => Opcode::LWC1, + 1966 => Opcode::LWC1_MM, + 1967 => Opcode::LWC2, + 1968 => Opcode::LWC2_MMR6, + 1969 => Opcode::LWC2_R6, + 1970 => Opcode::LWC3, + 1971 => Opcode::LWDSP, + 1972 => Opcode::LWDSP_MM, + 1973 => Opcode::LWE, + 1974 => Opcode::LWE_MM, + 1975 => Opcode::LWGP_MM, + 1976 => Opcode::LWL, + 1977 => Opcode::LWL64, + 1978 => Opcode::LWLE, + 1979 => Opcode::LWLE_MM, + 1980 => Opcode::LWL_MM, + 1981 => Opcode::LWM16_MM, + 1982 => Opcode::LWM16_MMR6, + 1983 => Opcode::LWM32_MM, + 1984 => Opcode::LWPC, + 1985 => Opcode::LWPC_MMR6, + 1986 => Opcode::LWP_MM, + 1987 => Opcode::LWR, + 1988 => Opcode::LWR64, + 1989 => Opcode::LWRE, + 1990 => Opcode::LWRE_MM, + 1991 => Opcode::LWR_MM, + 1992 => Opcode::LWSP_MM, + 1993 => Opcode::LWUPC, + 1994 => Opcode::LWU_MM, + 1995 => Opcode::LWX, + 1996 => Opcode::LWXC1, + 1997 => Opcode::LWXC1_MM, + 1998 => Opcode::LWXS_MM, + 1999 => Opcode::LWX_MM, + 2000 => Opcode::LW_MM, + 2001 => Opcode::LW_MMR6, + 2002 => Opcode::LWu, + 2003 => Opcode::LbRxRyOffMemX16, + 2004 => Opcode::LbuRxRyOffMemX16, + 2005 => Opcode::LhRxRyOffMemX16, + 2006 => Opcode::LhuRxRyOffMemX16, + 2007 => Opcode::LiRxImm16, + 2008 => Opcode::LiRxImmAlignX16, + 2009 => Opcode::LiRxImmX16, + 2010 => Opcode::LwRxPcTcp16, + 2011 => Opcode::LwRxPcTcpX16, + 2012 => Opcode::LwRxRyOffMemX16, + 2013 => Opcode::LwRxSpImmX16, + 2014 => Opcode::MADD, + 2015 => Opcode::MADDF_D, + 2016 => Opcode::MADDF_D_MMR6, + 2017 => Opcode::MADDF_S, + 2018 => Opcode::MADDF_S_MMR6, + 2019 => Opcode::MADDR_Q_H, + 2020 => Opcode::MADDR_Q_W, + 2021 => Opcode::MADDU, + 2022 => Opcode::MADDU_DSP, + 2023 => Opcode::MADDU_DSP_MM, + 2024 => Opcode::MADDU_MM, + 2025 => Opcode::MADDV_B, + 2026 => Opcode::MADDV_D, + 2027 => Opcode::MADDV_H, + 2028 => Opcode::MADDV_W, + 2029 => Opcode::MADD_D32, + 2030 => Opcode::MADD_D32_MM, + 2031 => Opcode::MADD_D64, + 2032 => Opcode::MADD_DSP, + 2033 => Opcode::MADD_DSP_MM, + 2034 => Opcode::MADD_MM, + 2035 => Opcode::MADD_Q_H, + 2036 => Opcode::MADD_Q_W, + 2037 => Opcode::MADD_S, + 2038 => Opcode::MADD_S_MM, + 2039 => Opcode::MAQ_SA_W_PHL, + 2040 => Opcode::MAQ_SA_W_PHL_MM, + 2041 => Opcode::MAQ_SA_W_PHR, + 2042 => Opcode::MAQ_SA_W_PHR_MM, + 2043 => Opcode::MAQ_S_W_PHL, + 2044 => Opcode::MAQ_S_W_PHL_MM, + 2045 => Opcode::MAQ_S_W_PHR, + 2046 => Opcode::MAQ_S_W_PHR_MM, + 2047 => Opcode::MAXA_D, + 2048 => Opcode::MAXA_D_MMR6, + 2049 => Opcode::MAXA_S, + 2050 => Opcode::MAXA_S_MMR6, + 2051 => Opcode::MAXI_S_B, + 2052 => Opcode::MAXI_S_D, + 2053 => Opcode::MAXI_S_H, + 2054 => Opcode::MAXI_S_W, + 2055 => Opcode::MAXI_U_B, + 2056 => Opcode::MAXI_U_D, + 2057 => Opcode::MAXI_U_H, + 2058 => Opcode::MAXI_U_W, + 2059 => Opcode::MAX_A_B, + 2060 => Opcode::MAX_A_D, + 2061 => Opcode::MAX_A_H, + 2062 => Opcode::MAX_A_W, + 2063 => Opcode::MAX_D, + 2064 => Opcode::MAX_D_MMR6, + 2065 => Opcode::MAX_S, + 2066 => Opcode::MAX_S_B, + 2067 => Opcode::MAX_S_D, + 2068 => Opcode::MAX_S_H, + 2069 => Opcode::MAX_S_MMR6, + 2070 => Opcode::MAX_S_W, + 2071 => Opcode::MAX_U_B, + 2072 => Opcode::MAX_U_D, + 2073 => Opcode::MAX_U_H, + 2074 => Opcode::MAX_U_W, + 2075 => Opcode::MFC0, + 2076 => Opcode::MFC0_MMR6, + 2077 => Opcode::MFC1, + 2078 => Opcode::MFC1_D64, + 2079 => Opcode::MFC1_MM, + 2080 => Opcode::MFC1_MMR6, + 2081 => Opcode::MFC2, + 2082 => Opcode::MFC2_MMR6, + 2083 => Opcode::MFGC0, + 2084 => Opcode::MFGC0_MM, + 2085 => Opcode::MFHC0_MMR6, + 2086 => Opcode::MFHC1_D32, + 2087 => Opcode::MFHC1_D32_MM, + 2088 => Opcode::MFHC1_D64, + 2089 => Opcode::MFHC1_D64_MM, + 2090 => Opcode::MFHC2_MMR6, + 2091 => Opcode::MFHGC0, + 2092 => Opcode::MFHGC0_MM, + 2093 => Opcode::MFHI, + 2094 => Opcode::MFHI16_MM, + 2095 => Opcode::MFHI64, + 2096 => Opcode::MFHI_DSP, + 2097 => Opcode::MFHI_DSP_MM, + 2098 => Opcode::MFHI_MM, + 2099 => Opcode::MFLO, + 2100 => Opcode::MFLO16_MM, + 2101 => Opcode::MFLO64, + 2102 => Opcode::MFLO_DSP, + 2103 => Opcode::MFLO_DSP_MM, + 2104 => Opcode::MFLO_MM, + 2105 => Opcode::MFTR, + 2106 => Opcode::MINA_D, + 2107 => Opcode::MINA_D_MMR6, + 2108 => Opcode::MINA_S, + 2109 => Opcode::MINA_S_MMR6, + 2110 => Opcode::MINI_S_B, + 2111 => Opcode::MINI_S_D, + 2112 => Opcode::MINI_S_H, + 2113 => Opcode::MINI_S_W, + 2114 => Opcode::MINI_U_B, + 2115 => Opcode::MINI_U_D, + 2116 => Opcode::MINI_U_H, + 2117 => Opcode::MINI_U_W, + 2118 => Opcode::MIN_A_B, + 2119 => Opcode::MIN_A_D, + 2120 => Opcode::MIN_A_H, + 2121 => Opcode::MIN_A_W, + 2122 => Opcode::MIN_D, + 2123 => Opcode::MIN_D_MMR6, + 2124 => Opcode::MIN_S, + 2125 => Opcode::MIN_S_B, + 2126 => Opcode::MIN_S_D, + 2127 => Opcode::MIN_S_H, + 2128 => Opcode::MIN_S_MMR6, + 2129 => Opcode::MIN_S_W, + 2130 => Opcode::MIN_U_B, + 2131 => Opcode::MIN_U_D, + 2132 => Opcode::MIN_U_H, + 2133 => Opcode::MIN_U_W, + 2134 => Opcode::MOD, + 2135 => Opcode::MODSUB, + 2136 => Opcode::MODSUB_MM, + 2137 => Opcode::MODU, + 2138 => Opcode::MODU_MMR6, + 2139 => Opcode::MOD_MMR6, + 2140 => Opcode::MOD_S_B, + 2141 => Opcode::MOD_S_D, + 2142 => Opcode::MOD_S_H, + 2143 => Opcode::MOD_S_W, + 2144 => Opcode::MOD_U_B, + 2145 => Opcode::MOD_U_D, + 2146 => Opcode::MOD_U_H, + 2147 => Opcode::MOD_U_W, + 2148 => Opcode::MOVE16_MM, + 2149 => Opcode::MOVE16_MMR6, + 2150 => Opcode::MOVEP_MM, + 2151 => Opcode::MOVEP_MMR6, + 2152 => Opcode::MOVE_V, + 2153 => Opcode::MOVF_D32, + 2154 => Opcode::MOVF_D32_MM, + 2155 => Opcode::MOVF_D64, + 2156 => Opcode::MOVF_I, + 2157 => Opcode::MOVF_I64, + 2158 => Opcode::MOVF_I_MM, + 2159 => Opcode::MOVF_S, + 2160 => Opcode::MOVF_S_MM, + 2161 => Opcode::MOVN_I64_D64, + 2162 => Opcode::MOVN_I64_I, + 2163 => Opcode::MOVN_I64_I64, + 2164 => Opcode::MOVN_I64_S, + 2165 => Opcode::MOVN_I_D32, + 2166 => Opcode::MOVN_I_D32_MM, + 2167 => Opcode::MOVN_I_D64, + 2168 => Opcode::MOVN_I_I, + 2169 => Opcode::MOVN_I_I64, + 2170 => Opcode::MOVN_I_MM, + 2171 => Opcode::MOVN_I_S, + 2172 => Opcode::MOVN_I_S_MM, + 2173 => Opcode::MOVT_D32, + 2174 => Opcode::MOVT_D32_MM, + 2175 => Opcode::MOVT_D64, + 2176 => Opcode::MOVT_I, + 2177 => Opcode::MOVT_I64, + 2178 => Opcode::MOVT_I_MM, + 2179 => Opcode::MOVT_S, + 2180 => Opcode::MOVT_S_MM, + 2181 => Opcode::MOVZ_I64_D64, + 2182 => Opcode::MOVZ_I64_I, + 2183 => Opcode::MOVZ_I64_I64, + 2184 => Opcode::MOVZ_I64_S, + 2185 => Opcode::MOVZ_I_D32, + 2186 => Opcode::MOVZ_I_D32_MM, + 2187 => Opcode::MOVZ_I_D64, + 2188 => Opcode::MOVZ_I_I, + 2189 => Opcode::MOVZ_I_I64, + 2190 => Opcode::MOVZ_I_MM, + 2191 => Opcode::MOVZ_I_S, + 2192 => Opcode::MOVZ_I_S_MM, + 2193 => Opcode::MSUB, + 2194 => Opcode::MSUBF_D, + 2195 => Opcode::MSUBF_D_MMR6, + 2196 => Opcode::MSUBF_S, + 2197 => Opcode::MSUBF_S_MMR6, + 2198 => Opcode::MSUBR_Q_H, + 2199 => Opcode::MSUBR_Q_W, + 2200 => Opcode::MSUBU, + 2201 => Opcode::MSUBU_DSP, + 2202 => Opcode::MSUBU_DSP_MM, + 2203 => Opcode::MSUBU_MM, + 2204 => Opcode::MSUBV_B, + 2205 => Opcode::MSUBV_D, + 2206 => Opcode::MSUBV_H, + 2207 => Opcode::MSUBV_W, + 2208 => Opcode::MSUB_D32, + 2209 => Opcode::MSUB_D32_MM, + 2210 => Opcode::MSUB_D64, + 2211 => Opcode::MSUB_DSP, + 2212 => Opcode::MSUB_DSP_MM, + 2213 => Opcode::MSUB_MM, + 2214 => Opcode::MSUB_Q_H, + 2215 => Opcode::MSUB_Q_W, + 2216 => Opcode::MSUB_S, + 2217 => Opcode::MSUB_S_MM, + 2218 => Opcode::MTC0, + 2219 => Opcode::MTC0_MMR6, + 2220 => Opcode::MTC1, + 2221 => Opcode::MTC1_D64, + 2222 => Opcode::MTC1_D64_MM, + 2223 => Opcode::MTC1_MM, + 2224 => Opcode::MTC1_MMR6, + 2225 => Opcode::MTC2, + 2226 => Opcode::MTC2_MMR6, + 2227 => Opcode::MTGC0, + 2228 => Opcode::MTGC0_MM, + 2229 => Opcode::MTHC0_MMR6, + 2230 => Opcode::MTHC1_D32, + 2231 => Opcode::MTHC1_D32_MM, + 2232 => Opcode::MTHC1_D64, + 2233 => Opcode::MTHC1_D64_MM, + 2234 => Opcode::MTHC2_MMR6, + 2235 => Opcode::MTHGC0, + 2236 => Opcode::MTHGC0_MM, + 2237 => Opcode::MTHI, + 2238 => Opcode::MTHI64, + 2239 => Opcode::MTHI_DSP, + 2240 => Opcode::MTHI_DSP_MM, + 2241 => Opcode::MTHI_MM, + 2242 => Opcode::MTHLIP, + 2243 => Opcode::MTHLIP_MM, + 2244 => Opcode::MTLO, + 2245 => Opcode::MTLO64, + 2246 => Opcode::MTLO_DSP, + 2247 => Opcode::MTLO_DSP_MM, + 2248 => Opcode::MTLO_MM, + 2249 => Opcode::MTM0, + 2250 => Opcode::MTM1, + 2251 => Opcode::MTM2, + 2252 => Opcode::MTP0, + 2253 => Opcode::MTP1, + 2254 => Opcode::MTP2, + 2255 => Opcode::MTTR, + 2256 => Opcode::MUH, + 2257 => Opcode::MUHU, + 2258 => Opcode::MUHU_MMR6, + 2259 => Opcode::MUH_MMR6, + 2260 => Opcode::MUL, + 2261 => Opcode::MULEQ_S_W_PHL, + 2262 => Opcode::MULEQ_S_W_PHL_MM, + 2263 => Opcode::MULEQ_S_W_PHR, + 2264 => Opcode::MULEQ_S_W_PHR_MM, + 2265 => Opcode::MULEU_S_PH_QBL, + 2266 => Opcode::MULEU_S_PH_QBL_MM, + 2267 => Opcode::MULEU_S_PH_QBR, + 2268 => Opcode::MULEU_S_PH_QBR_MM, + 2269 => Opcode::MULQ_RS_PH, + 2270 => Opcode::MULQ_RS_PH_MM, + 2271 => Opcode::MULQ_RS_W, + 2272 => Opcode::MULQ_RS_W_MMR2, + 2273 => Opcode::MULQ_S_PH, + 2274 => Opcode::MULQ_S_PH_MMR2, + 2275 => Opcode::MULQ_S_W, + 2276 => Opcode::MULQ_S_W_MMR2, + 2277 => Opcode::MULR_PS64, + 2278 => Opcode::MULR_Q_H, + 2279 => Opcode::MULR_Q_W, + 2280 => Opcode::MULSAQ_S_W_PH, + 2281 => Opcode::MULSAQ_S_W_PH_MM, + 2282 => Opcode::MULSA_W_PH, + 2283 => Opcode::MULSA_W_PH_MMR2, + 2284 => Opcode::MULT, + 2285 => Opcode::MULTU_DSP, + 2286 => Opcode::MULTU_DSP_MM, + 2287 => Opcode::MULT_DSP, + 2288 => Opcode::MULT_DSP_MM, + 2289 => Opcode::MULT_MM, + 2290 => Opcode::MULTu, + 2291 => Opcode::MULTu_MM, + 2292 => Opcode::MULU, + 2293 => Opcode::MULU_MMR6, + 2294 => Opcode::MULV_B, + 2295 => Opcode::MULV_D, + 2296 => Opcode::MULV_H, + 2297 => Opcode::MULV_W, + 2298 => Opcode::MUL_MM, + 2299 => Opcode::MUL_MMR6, + 2300 => Opcode::MUL_PH, + 2301 => Opcode::MUL_PH_MMR2, + 2302 => Opcode::MUL_Q_H, + 2303 => Opcode::MUL_Q_W, + 2304 => Opcode::MUL_R6, + 2305 => Opcode::MUL_S_PH, + 2306 => Opcode::MUL_S_PH_MMR2, + 2307 => Opcode::Mfhi16, + 2308 => Opcode::Mflo16, + 2309 => Opcode::Move32R16, + 2310 => Opcode::MoveR3216, + 2311 => Opcode::NAL, + 2312 => Opcode::NLOC_B, + 2313 => Opcode::NLOC_D, + 2314 => Opcode::NLOC_H, + 2315 => Opcode::NLOC_W, + 2316 => Opcode::NLZC_B, + 2317 => Opcode::NLZC_D, + 2318 => Opcode::NLZC_H, + 2319 => Opcode::NLZC_W, + 2320 => Opcode::NMADD_D32, + 2321 => Opcode::NMADD_D32_MM, + 2322 => Opcode::NMADD_D64, + 2323 => Opcode::NMADD_S, + 2324 => Opcode::NMADD_S_MM, + 2325 => Opcode::NMSUB_D32, + 2326 => Opcode::NMSUB_D32_MM, + 2327 => Opcode::NMSUB_D64, + 2328 => Opcode::NMSUB_S, + 2329 => Opcode::NMSUB_S_MM, + 2330 => Opcode::NOR, + 2331 => Opcode::NOR64, + 2332 => Opcode::NORI_B, + 2333 => Opcode::NOR_MM, + 2334 => Opcode::NOR_MMR6, + 2335 => Opcode::NOR_V, + 2336 => Opcode::NOT16_MM, + 2337 => Opcode::NOT16_MMR6, + 2338 => Opcode::NegRxRy16, + 2339 => Opcode::NotRxRy16, + 2340 => Opcode::OR, + 2341 => Opcode::OR16_MM, + 2342 => Opcode::OR16_MMR6, + 2343 => Opcode::OR64, + 2344 => Opcode::ORI_B, + 2345 => Opcode::ORI_MMR6, + 2346 => Opcode::OR_MM, + 2347 => Opcode::OR_MMR6, + 2348 => Opcode::OR_V, + 2349 => Opcode::ORi, + 2350 => Opcode::ORi64, + 2351 => Opcode::ORi_MM, + 2352 => Opcode::OrRxRxRy16, + 2353 => Opcode::PACKRL_PH, + 2354 => Opcode::PACKRL_PH_MM, + 2355 => Opcode::PAUSE, + 2356 => Opcode::PAUSE_MM, + 2357 => Opcode::PAUSE_MMR6, + 2358 => Opcode::PCKEV_B, + 2359 => Opcode::PCKEV_D, + 2360 => Opcode::PCKEV_H, + 2361 => Opcode::PCKEV_W, + 2362 => Opcode::PCKOD_B, + 2363 => Opcode::PCKOD_D, + 2364 => Opcode::PCKOD_H, + 2365 => Opcode::PCKOD_W, + 2366 => Opcode::PCNT_B, + 2367 => Opcode::PCNT_D, + 2368 => Opcode::PCNT_H, + 2369 => Opcode::PCNT_W, + 2370 => Opcode::PICK_PH, + 2371 => Opcode::PICK_PH_MM, + 2372 => Opcode::PICK_QB, + 2373 => Opcode::PICK_QB_MM, + 2374 => Opcode::PLL_PS64, + 2375 => Opcode::PLU_PS64, + 2376 => Opcode::POP, + 2377 => Opcode::PRECEQU_PH_QBL, + 2378 => Opcode::PRECEQU_PH_QBLA, + 2379 => Opcode::PRECEQU_PH_QBLA_MM, + 2380 => Opcode::PRECEQU_PH_QBL_MM, + 2381 => Opcode::PRECEQU_PH_QBR, + 2382 => Opcode::PRECEQU_PH_QBRA, + 2383 => Opcode::PRECEQU_PH_QBRA_MM, + 2384 => Opcode::PRECEQU_PH_QBR_MM, + 2385 => Opcode::PRECEQ_W_PHL, + 2386 => Opcode::PRECEQ_W_PHL_MM, + 2387 => Opcode::PRECEQ_W_PHR, + 2388 => Opcode::PRECEQ_W_PHR_MM, + 2389 => Opcode::PRECEU_PH_QBL, + 2390 => Opcode::PRECEU_PH_QBLA, + 2391 => Opcode::PRECEU_PH_QBLA_MM, + 2392 => Opcode::PRECEU_PH_QBL_MM, + 2393 => Opcode::PRECEU_PH_QBR, + 2394 => Opcode::PRECEU_PH_QBRA, + 2395 => Opcode::PRECEU_PH_QBRA_MM, + 2396 => Opcode::PRECEU_PH_QBR_MM, + 2397 => Opcode::PRECRQU_S_QB_PH, + 2398 => Opcode::PRECRQU_S_QB_PH_MM, + 2399 => Opcode::PRECRQ_PH_W, + 2400 => Opcode::PRECRQ_PH_W_MM, + 2401 => Opcode::PRECRQ_QB_PH, + 2402 => Opcode::PRECRQ_QB_PH_MM, + 2403 => Opcode::PRECRQ_RS_PH_W, + 2404 => Opcode::PRECRQ_RS_PH_W_MM, + 2405 => Opcode::PRECR_QB_PH, + 2406 => Opcode::PRECR_QB_PH_MMR2, + 2407 => Opcode::PRECR_SRA_PH_W, + 2408 => Opcode::PRECR_SRA_PH_W_MMR2, + 2409 => Opcode::PRECR_SRA_R_PH_W, + 2410 => Opcode::PRECR_SRA_R_PH_W_MMR2, + 2411 => Opcode::PREF, + 2412 => Opcode::PREFE, + 2413 => Opcode::PREFE_MM, + 2414 => Opcode::PREFX_MM, + 2415 => Opcode::PREF_MM, + 2416 => Opcode::PREF_MMR6, + 2417 => Opcode::PREF_R6, + 2418 => Opcode::PREPEND, + 2419 => Opcode::PREPEND_MMR2, + 2420 => Opcode::PUL_PS64, + 2421 => Opcode::PUU_PS64, + 2422 => Opcode::RADDU_W_QB, + 2423 => Opcode::RADDU_W_QB_MM, + 2424 => Opcode::RDDSP, + 2425 => Opcode::RDDSP_MM, + 2426 => Opcode::RDHWR, + 2427 => Opcode::RDHWR64, + 2428 => Opcode::RDHWR_MM, + 2429 => Opcode::RDHWR_MMR6, + 2430 => Opcode::RDPGPR_MMR6, + 2431 => Opcode::RECIP_D32, + 2432 => Opcode::RECIP_D32_MM, + 2433 => Opcode::RECIP_D64, + 2434 => Opcode::RECIP_D64_MM, + 2435 => Opcode::RECIP_S, + 2436 => Opcode::RECIP_S_MM, + 2437 => Opcode::REPLV_PH, + 2438 => Opcode::REPLV_PH_MM, + 2439 => Opcode::REPLV_QB, + 2440 => Opcode::REPLV_QB_MM, + 2441 => Opcode::REPL_PH, + 2442 => Opcode::REPL_PH_MM, + 2443 => Opcode::REPL_QB, + 2444 => Opcode::REPL_QB_MM, + 2445 => Opcode::RINT_D, + 2446 => Opcode::RINT_D_MMR6, + 2447 => Opcode::RINT_S, + 2448 => Opcode::RINT_S_MMR6, + 2449 => Opcode::ROTR, + 2450 => Opcode::ROTRV, + 2451 => Opcode::ROTRV_MM, + 2452 => Opcode::ROTR_MM, + 2453 => Opcode::ROUND_L_D64, + 2454 => Opcode::ROUND_L_D_MMR6, + 2455 => Opcode::ROUND_L_S, + 2456 => Opcode::ROUND_L_S_MMR6, + 2457 => Opcode::ROUND_W_D32, + 2458 => Opcode::ROUND_W_D64, + 2459 => Opcode::ROUND_W_D_MMR6, + 2460 => Opcode::ROUND_W_MM, + 2461 => Opcode::ROUND_W_S, + 2462 => Opcode::ROUND_W_S_MM, + 2463 => Opcode::ROUND_W_S_MMR6, + 2464 => Opcode::RSQRT_D32, + 2465 => Opcode::RSQRT_D32_MM, + 2466 => Opcode::RSQRT_D64, + 2467 => Opcode::RSQRT_D64_MM, + 2468 => Opcode::RSQRT_S, + 2469 => Opcode::RSQRT_S_MM, + 2470 => Opcode::Restore16, + 2471 => Opcode::RestoreX16, + 2472 => Opcode::SAA, + 2473 => Opcode::SAAD, + 2474 => Opcode::SAT_S_B, + 2475 => Opcode::SAT_S_D, + 2476 => Opcode::SAT_S_H, + 2477 => Opcode::SAT_S_W, + 2478 => Opcode::SAT_U_B, + 2479 => Opcode::SAT_U_D, + 2480 => Opcode::SAT_U_H, + 2481 => Opcode::SAT_U_W, + 2482 => Opcode::SB, + 2483 => Opcode::SB16_MM, + 2484 => Opcode::SB16_MMR6, + 2485 => Opcode::SB64, + 2486 => Opcode::SBE, + 2487 => Opcode::SBE_MM, + 2488 => Opcode::SB_MM, + 2489 => Opcode::SB_MMR6, + 2490 => Opcode::SC, + 2491 => Opcode::SC64, + 2492 => Opcode::SC64_R6, + 2493 => Opcode::SCD, + 2494 => Opcode::SCD_R6, + 2495 => Opcode::SCE, + 2496 => Opcode::SCE_MM, + 2497 => Opcode::SC_MM, + 2498 => Opcode::SC_MMR6, + 2499 => Opcode::SC_R6, + 2500 => Opcode::SD, + 2501 => Opcode::SDBBP, + 2502 => Opcode::SDBBP16_MM, + 2503 => Opcode::SDBBP16_MMR6, + 2504 => Opcode::SDBBP_MM, + 2505 => Opcode::SDBBP_MMR6, + 2506 => Opcode::SDBBP_R6, + 2507 => Opcode::SDC1, + 2508 => Opcode::SDC164, + 2509 => Opcode::SDC1_D64_MMR6, + 2510 => Opcode::SDC1_MM_D32, + 2511 => Opcode::SDC1_MM_D64, + 2512 => Opcode::SDC2, + 2513 => Opcode::SDC2_MMR6, + 2514 => Opcode::SDC2_R6, + 2515 => Opcode::SDC3, + 2516 => Opcode::SDIV, + 2517 => Opcode::SDIV_MM, + 2518 => Opcode::SDL, + 2519 => Opcode::SDR, + 2520 => Opcode::SDXC1, + 2521 => Opcode::SDXC164, + 2522 => Opcode::SEB, + 2523 => Opcode::SEB64, + 2524 => Opcode::SEB_MM, + 2525 => Opcode::SEH, + 2526 => Opcode::SEH64, + 2527 => Opcode::SEH_MM, + 2528 => Opcode::SELEQZ, + 2529 => Opcode::SELEQZ64, + 2530 => Opcode::SELEQZ_D, + 2531 => Opcode::SELEQZ_D_MMR6, + 2532 => Opcode::SELEQZ_MMR6, + 2533 => Opcode::SELEQZ_S, + 2534 => Opcode::SELEQZ_S_MMR6, + 2535 => Opcode::SELNEZ, + 2536 => Opcode::SELNEZ64, + 2537 => Opcode::SELNEZ_D, + 2538 => Opcode::SELNEZ_D_MMR6, + 2539 => Opcode::SELNEZ_MMR6, + 2540 => Opcode::SELNEZ_S, + 2541 => Opcode::SELNEZ_S_MMR6, + 2542 => Opcode::SEL_D, + 2543 => Opcode::SEL_D_MMR6, + 2544 => Opcode::SEL_S, + 2545 => Opcode::SEL_S_MMR6, + 2546 => Opcode::SEQ, + 2547 => Opcode::SEQi, + 2548 => Opcode::SH, + 2549 => Opcode::SH16_MM, + 2550 => Opcode::SH16_MMR6, + 2551 => Opcode::SH64, + 2552 => Opcode::SHE, + 2553 => Opcode::SHE_MM, + 2554 => Opcode::SHF_B, + 2555 => Opcode::SHF_H, + 2556 => Opcode::SHF_W, + 2557 => Opcode::SHILO, + 2558 => Opcode::SHILOV, + 2559 => Opcode::SHILOV_MM, + 2560 => Opcode::SHILO_MM, + 2561 => Opcode::SHLLV_PH, + 2562 => Opcode::SHLLV_PH_MM, + 2563 => Opcode::SHLLV_QB, + 2564 => Opcode::SHLLV_QB_MM, + 2565 => Opcode::SHLLV_S_PH, + 2566 => Opcode::SHLLV_S_PH_MM, + 2567 => Opcode::SHLLV_S_W, + 2568 => Opcode::SHLLV_S_W_MM, + 2569 => Opcode::SHLL_PH, + 2570 => Opcode::SHLL_PH_MM, + 2571 => Opcode::SHLL_QB, + 2572 => Opcode::SHLL_QB_MM, + 2573 => Opcode::SHLL_S_PH, + 2574 => Opcode::SHLL_S_PH_MM, + 2575 => Opcode::SHLL_S_W, + 2576 => Opcode::SHLL_S_W_MM, + 2577 => Opcode::SHRAV_PH, + 2578 => Opcode::SHRAV_PH_MM, + 2579 => Opcode::SHRAV_QB, + 2580 => Opcode::SHRAV_QB_MMR2, + 2581 => Opcode::SHRAV_R_PH, + 2582 => Opcode::SHRAV_R_PH_MM, + 2583 => Opcode::SHRAV_R_QB, + 2584 => Opcode::SHRAV_R_QB_MMR2, + 2585 => Opcode::SHRAV_R_W, + 2586 => Opcode::SHRAV_R_W_MM, + 2587 => Opcode::SHRA_PH, + 2588 => Opcode::SHRA_PH_MM, + 2589 => Opcode::SHRA_QB, + 2590 => Opcode::SHRA_QB_MMR2, + 2591 => Opcode::SHRA_R_PH, + 2592 => Opcode::SHRA_R_PH_MM, + 2593 => Opcode::SHRA_R_QB, + 2594 => Opcode::SHRA_R_QB_MMR2, + 2595 => Opcode::SHRA_R_W, + 2596 => Opcode::SHRA_R_W_MM, + 2597 => Opcode::SHRLV_PH, + 2598 => Opcode::SHRLV_PH_MMR2, + 2599 => Opcode::SHRLV_QB, + 2600 => Opcode::SHRLV_QB_MM, + 2601 => Opcode::SHRL_PH, + 2602 => Opcode::SHRL_PH_MMR2, + 2603 => Opcode::SHRL_QB, + 2604 => Opcode::SHRL_QB_MM, + 2605 => Opcode::SH_MM, + 2606 => Opcode::SH_MMR6, + 2607 => Opcode::SIGRIE, + 2608 => Opcode::SIGRIE_MMR6, + 2609 => Opcode::SLDI_B, + 2610 => Opcode::SLDI_D, + 2611 => Opcode::SLDI_H, + 2612 => Opcode::SLDI_W, + 2613 => Opcode::SLD_B, + 2614 => Opcode::SLD_D, + 2615 => Opcode::SLD_H, + 2616 => Opcode::SLD_W, + 2617 => Opcode::SLL, + 2618 => Opcode::SLL16_MM, + 2619 => Opcode::SLL16_MMR6, + 2620 => Opcode::SLL64_32, + 2621 => Opcode::SLL64_64, + 2622 => Opcode::SLLI_B, + 2623 => Opcode::SLLI_D, + 2624 => Opcode::SLLI_H, + 2625 => Opcode::SLLI_W, + 2626 => Opcode::SLLV, + 2627 => Opcode::SLLV_MM, + 2628 => Opcode::SLL_B, + 2629 => Opcode::SLL_D, + 2630 => Opcode::SLL_H, + 2631 => Opcode::SLL_MM, + 2632 => Opcode::SLL_MMR6, + 2633 => Opcode::SLL_W, + 2634 => Opcode::SLT, + 2635 => Opcode::SLT64, + 2636 => Opcode::SLT_MM, + 2637 => Opcode::SLTi, + 2638 => Opcode::SLTi64, + 2639 => Opcode::SLTi_MM, + 2640 => Opcode::SLTiu, + 2641 => Opcode::SLTiu64, + 2642 => Opcode::SLTiu_MM, + 2643 => Opcode::SLTu, + 2644 => Opcode::SLTu64, + 2645 => Opcode::SLTu_MM, + 2646 => Opcode::SNE, + 2647 => Opcode::SNEi, + 2648 => Opcode::SPLATI_B, + 2649 => Opcode::SPLATI_D, + 2650 => Opcode::SPLATI_H, + 2651 => Opcode::SPLATI_W, + 2652 => Opcode::SPLAT_B, + 2653 => Opcode::SPLAT_D, + 2654 => Opcode::SPLAT_H, + 2655 => Opcode::SPLAT_W, + 2656 => Opcode::SRA, + 2657 => Opcode::SRAI_B, + 2658 => Opcode::SRAI_D, + 2659 => Opcode::SRAI_H, + 2660 => Opcode::SRAI_W, + 2661 => Opcode::SRARI_B, + 2662 => Opcode::SRARI_D, + 2663 => Opcode::SRARI_H, + 2664 => Opcode::SRARI_W, + 2665 => Opcode::SRAR_B, + 2666 => Opcode::SRAR_D, + 2667 => Opcode::SRAR_H, + 2668 => Opcode::SRAR_W, + 2669 => Opcode::SRAV, + 2670 => Opcode::SRAV_MM, + 2671 => Opcode::SRA_B, + 2672 => Opcode::SRA_D, + 2673 => Opcode::SRA_H, + 2674 => Opcode::SRA_MM, + 2675 => Opcode::SRA_W, + 2676 => Opcode::SRL, + 2677 => Opcode::SRL16_MM, + 2678 => Opcode::SRL16_MMR6, + 2679 => Opcode::SRLI_B, + 2680 => Opcode::SRLI_D, + 2681 => Opcode::SRLI_H, + 2682 => Opcode::SRLI_W, + 2683 => Opcode::SRLRI_B, + 2684 => Opcode::SRLRI_D, + 2685 => Opcode::SRLRI_H, + 2686 => Opcode::SRLRI_W, + 2687 => Opcode::SRLR_B, + 2688 => Opcode::SRLR_D, + 2689 => Opcode::SRLR_H, + 2690 => Opcode::SRLR_W, + 2691 => Opcode::SRLV, + 2692 => Opcode::SRLV_MM, + 2693 => Opcode::SRL_B, + 2694 => Opcode::SRL_D, + 2695 => Opcode::SRL_H, + 2696 => Opcode::SRL_MM, + 2697 => Opcode::SRL_W, + 2698 => Opcode::SSNOP, + 2699 => Opcode::SSNOP_MM, + 2700 => Opcode::SSNOP_MMR6, + 2701 => Opcode::ST_B, + 2702 => Opcode::ST_D, + 2703 => Opcode::ST_H, + 2704 => Opcode::ST_W, + 2705 => Opcode::SUB, + 2706 => Opcode::SUBQH_PH, + 2707 => Opcode::SUBQH_PH_MMR2, + 2708 => Opcode::SUBQH_R_PH, + 2709 => Opcode::SUBQH_R_PH_MMR2, + 2710 => Opcode::SUBQH_R_W, + 2711 => Opcode::SUBQH_R_W_MMR2, + 2712 => Opcode::SUBQH_W, + 2713 => Opcode::SUBQH_W_MMR2, + 2714 => Opcode::SUBQ_PH, + 2715 => Opcode::SUBQ_PH_MM, + 2716 => Opcode::SUBQ_S_PH, + 2717 => Opcode::SUBQ_S_PH_MM, + 2718 => Opcode::SUBQ_S_W, + 2719 => Opcode::SUBQ_S_W_MM, + 2720 => Opcode::SUBSUS_U_B, + 2721 => Opcode::SUBSUS_U_D, + 2722 => Opcode::SUBSUS_U_H, + 2723 => Opcode::SUBSUS_U_W, + 2724 => Opcode::SUBSUU_S_B, + 2725 => Opcode::SUBSUU_S_D, + 2726 => Opcode::SUBSUU_S_H, + 2727 => Opcode::SUBSUU_S_W, + 2728 => Opcode::SUBS_S_B, + 2729 => Opcode::SUBS_S_D, + 2730 => Opcode::SUBS_S_H, + 2731 => Opcode::SUBS_S_W, + 2732 => Opcode::SUBS_U_B, + 2733 => Opcode::SUBS_U_D, + 2734 => Opcode::SUBS_U_H, + 2735 => Opcode::SUBS_U_W, + 2736 => Opcode::SUBU16_MM, + 2737 => Opcode::SUBU16_MMR6, + 2738 => Opcode::SUBUH_QB, + 2739 => Opcode::SUBUH_QB_MMR2, + 2740 => Opcode::SUBUH_R_QB, + 2741 => Opcode::SUBUH_R_QB_MMR2, + 2742 => Opcode::SUBU_MMR6, + 2743 => Opcode::SUBU_PH, + 2744 => Opcode::SUBU_PH_MMR2, + 2745 => Opcode::SUBU_QB, + 2746 => Opcode::SUBU_QB_MM, + 2747 => Opcode::SUBU_S_PH, + 2748 => Opcode::SUBU_S_PH_MMR2, + 2749 => Opcode::SUBU_S_QB, + 2750 => Opcode::SUBU_S_QB_MM, + 2751 => Opcode::SUBVI_B, + 2752 => Opcode::SUBVI_D, + 2753 => Opcode::SUBVI_H, + 2754 => Opcode::SUBVI_W, + 2755 => Opcode::SUBV_B, + 2756 => Opcode::SUBV_D, + 2757 => Opcode::SUBV_H, + 2758 => Opcode::SUBV_W, + 2759 => Opcode::SUB_MM, + 2760 => Opcode::SUB_MMR6, + 2761 => Opcode::SUBu, + 2762 => Opcode::SUBu_MM, + 2763 => Opcode::SUXC1, + 2764 => Opcode::SUXC164, + 2765 => Opcode::SUXC1_MM, + 2766 => Opcode::SW, + 2767 => Opcode::SW16_MM, + 2768 => Opcode::SW16_MMR6, + 2769 => Opcode::SW64, + 2770 => Opcode::SWC1, + 2771 => Opcode::SWC1_MM, + 2772 => Opcode::SWC2, + 2773 => Opcode::SWC2_MMR6, + 2774 => Opcode::SWC2_R6, + 2775 => Opcode::SWC3, + 2776 => Opcode::SWDSP, + 2777 => Opcode::SWDSP_MM, + 2778 => Opcode::SWE, + 2779 => Opcode::SWE_MM, + 2780 => Opcode::SWL, + 2781 => Opcode::SWL64, + 2782 => Opcode::SWLE, + 2783 => Opcode::SWLE_MM, + 2784 => Opcode::SWL_MM, + 2785 => Opcode::SWM16_MM, + 2786 => Opcode::SWM16_MMR6, + 2787 => Opcode::SWM32_MM, + 2788 => Opcode::SWP_MM, + 2789 => Opcode::SWR, + 2790 => Opcode::SWR64, + 2791 => Opcode::SWRE, + 2792 => Opcode::SWRE_MM, + 2793 => Opcode::SWR_MM, + 2794 => Opcode::SWSP_MM, + 2795 => Opcode::SWSP_MMR6, + 2796 => Opcode::SWXC1, + 2797 => Opcode::SWXC1_MM, + 2798 => Opcode::SW_MM, + 2799 => Opcode::SW_MMR6, + 2800 => Opcode::SYNC, + 2801 => Opcode::SYNCI, + 2802 => Opcode::SYNCI_MM, + 2803 => Opcode::SYNCI_MMR6, + 2804 => Opcode::SYNC_MM, + 2805 => Opcode::SYNC_MMR6, + 2806 => Opcode::SYSCALL, + 2807 => Opcode::SYSCALL_MM, + 2808 => Opcode::Save16, + 2809 => Opcode::SaveX16, + 2810 => Opcode::SbRxRyOffMemX16, + 2811 => Opcode::SebRx16, + 2812 => Opcode::SehRx16, + 2813 => Opcode::ShRxRyOffMemX16, + 2814 => Opcode::SllX16, + 2815 => Opcode::SllvRxRy16, + 2816 => Opcode::SltRxRy16, + 2817 => Opcode::SltiRxImm16, + 2818 => Opcode::SltiRxImmX16, + 2819 => Opcode::SltiuRxImm16, + 2820 => Opcode::SltiuRxImmX16, + 2821 => Opcode::SltuRxRy16, + 2822 => Opcode::SraX16, + 2823 => Opcode::SravRxRy16, + 2824 => Opcode::SrlX16, + 2825 => Opcode::SrlvRxRy16, + 2826 => Opcode::SubuRxRyRz16, + 2827 => Opcode::SwRxRyOffMemX16, + 2828 => Opcode::SwRxSpImmX16, + 2829 => Opcode::TEQ, + 2830 => Opcode::TEQI, + 2831 => Opcode::TEQI_MM, + 2832 => Opcode::TEQ_MM, + 2833 => Opcode::TGE, + 2834 => Opcode::TGEI, + 2835 => Opcode::TGEIU, + 2836 => Opcode::TGEIU_MM, + 2837 => Opcode::TGEI_MM, + 2838 => Opcode::TGEU, + 2839 => Opcode::TGEU_MM, + 2840 => Opcode::TGE_MM, + 2841 => Opcode::TLBGINV, + 2842 => Opcode::TLBGINVF, + 2843 => Opcode::TLBGINVF_MM, + 2844 => Opcode::TLBGINV_MM, + 2845 => Opcode::TLBGP, + 2846 => Opcode::TLBGP_MM, + 2847 => Opcode::TLBGR, + 2848 => Opcode::TLBGR_MM, + 2849 => Opcode::TLBGWI, + 2850 => Opcode::TLBGWI_MM, + 2851 => Opcode::TLBGWR, + 2852 => Opcode::TLBGWR_MM, + 2853 => Opcode::TLBINV, + 2854 => Opcode::TLBINVF, + 2855 => Opcode::TLBINVF_MMR6, + 2856 => Opcode::TLBINV_MMR6, + 2857 => Opcode::TLBP, + 2858 => Opcode::TLBP_MM, + 2859 => Opcode::TLBR, + 2860 => Opcode::TLBR_MM, + 2861 => Opcode::TLBWI, + 2862 => Opcode::TLBWI_MM, + 2863 => Opcode::TLBWR, + 2864 => Opcode::TLBWR_MM, + 2865 => Opcode::TLT, + 2866 => Opcode::TLTI, + 2867 => Opcode::TLTIU_MM, + 2868 => Opcode::TLTI_MM, + 2869 => Opcode::TLTU, + 2870 => Opcode::TLTU_MM, + 2871 => Opcode::TLT_MM, + 2872 => Opcode::TNE, + 2873 => Opcode::TNEI, + 2874 => Opcode::TNEI_MM, + 2875 => Opcode::TNE_MM, + 2876 => Opcode::TRUNC_L_D64, + 2877 => Opcode::TRUNC_L_D_MMR6, + 2878 => Opcode::TRUNC_L_S, + 2879 => Opcode::TRUNC_L_S_MMR6, + 2880 => Opcode::TRUNC_W_D32, + 2881 => Opcode::TRUNC_W_D64, + 2882 => Opcode::TRUNC_W_D_MMR6, + 2883 => Opcode::TRUNC_W_MM, + 2884 => Opcode::TRUNC_W_S, + 2885 => Opcode::TRUNC_W_S_MM, + 2886 => Opcode::TRUNC_W_S_MMR6, + 2887 => Opcode::TTLTIU, + 2888 => Opcode::UDIV, + 2889 => Opcode::UDIV_MM, + 2890 => Opcode::V3MULU, + 2891 => Opcode::VMM0, + 2892 => Opcode::VMULU, + 2893 => Opcode::VSHF_B, + 2894 => Opcode::VSHF_D, + 2895 => Opcode::VSHF_H, + 2896 => Opcode::VSHF_W, + 2897 => Opcode::WAIT, + 2898 => Opcode::WAIT_MM, + 2899 => Opcode::WAIT_MMR6, + 2900 => Opcode::WRDSP, + 2901 => Opcode::WRDSP_MM, + 2902 => Opcode::WRPGPR_MMR6, + 2903 => Opcode::WSBH, + 2904 => Opcode::WSBH_MM, + 2905 => Opcode::WSBH_MMR6, + 2906 => Opcode::XOR, + 2907 => Opcode::XOR16_MM, + 2908 => Opcode::XOR16_MMR6, + 2909 => Opcode::XOR64, + 2910 => Opcode::XORI_B, + 2911 => Opcode::XORI_MMR6, + 2912 => Opcode::XOR_MM, + 2913 => Opcode::XOR_MMR6, + 2914 => Opcode::XOR_V, + 2915 => Opcode::XORi, + 2916 => Opcode::XORi64, + 2917 => Opcode::XORi_MM, + 2918 => Opcode::XorRxRxRy16, + 2919 => Opcode::YIELD, + 2920 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands.rs new file mode 100644 index 0000000..b961a1f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand + Reg(Register), + + /// A PC-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_mips_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_mips_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_mips_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_mips_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/immediate.rs new file mode 100644 index 0000000..a085e16 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// addiu $4, $5, 8 +/// | +/// +---> Immediate(8) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/memory.rs new file mode 100644 index 0000000..311dc86 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/memory.rs @@ -0,0 +1,64 @@ +use lief_ffi as ffi; + +use crate::{assembly::mips::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// ```text +/// lw $4, 8($5) ldxc1 $f2, $4($7) +/// | | | | | | +/// +------+ | +---+ +-------+ | +-----+ +/// | | | | | | +/// v v v v v v +/// Reg Disp Base Reg Index Base +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Wraps a memory offset as an integer displacement or as an index register +#[derive(Debug)] +pub enum Offset { + /// Index register offset + Reg(Reg), + /// Integer displacement + Displacement(i64), +} + +impl Memory { + /// The base register. + /// + /// For `lw $4, 8($5)` it would return `$5` + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The addressing offset. + /// + /// It can be either: + /// - A register (e.g. `ldxc1 $f2, $4($7)`) + /// - A displacement (e.g. `lw $4, 8($5)`) + pub fn offset(&self) -> Option { + let ffi_offset = self.ptr.offset(); + match ffi_offset.enum_type { + 1 => Some(Offset::Reg(Reg::from(ffi_offset.value))), + 2 => Some(Offset::Displacement(ffi_offset.value as i64)), + _ => None, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/pc_relative.rs new file mode 100644 index 0000000..ad5226a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/pc_relative.rs @@ -0,0 +1,37 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a PC-relative operand. +/// +/// ```text +/// bal 0x100 +/// | +/// v +/// PC Relative operand +/// ``` +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `pc` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/register.rs new file mode 100644 index 0000000..b956bf5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/operands/register.rs @@ -0,0 +1,41 @@ +use lief_ffi as ffi; + +use crate::assembly::mips::registers::Reg; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// For instance: +/// +/// ```text +/// move $4, $5 +/// | | +/// | +---------> Register($5) +/// | +/// +-------------> Register($4) +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_mips_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Register { + /// The effective register wrapped by this operand + pub fn value(&self) -> Reg { + Reg::from(self.ptr.value()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/mips/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/mips/registers.rs new file mode 100644 index 0000000..2ccad34 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/mips/registers.rs @@ -0,0 +1,899 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + AT, + DSPCCond, + DSPCarry, + DSPEFI, + DSPOutFlag, + DSPPos, + DSPSCount, + FP, + GP, + MSAAccess, + MSACSR, + MSAIR, + MSAMap, + MSAModify, + MSARequest, + MSASave, + MSAUnmap, + PC, + RA, + SP, + ZERO, + A0, + A1, + A2, + A3, + AC0, + AC1, + AC2, + AC3, + AT_64, + COP00, + COP01, + COP02, + COP03, + COP04, + COP05, + COP06, + COP07, + COP08, + COP09, + COP20, + COP21, + COP22, + COP23, + COP24, + COP25, + COP26, + COP27, + COP28, + COP29, + COP30, + COP31, + COP32, + COP33, + COP34, + COP35, + COP36, + COP37, + COP38, + COP39, + COP010, + COP011, + COP012, + COP013, + COP014, + COP015, + COP016, + COP017, + COP018, + COP019, + COP020, + COP021, + COP022, + COP023, + COP024, + COP025, + COP026, + COP027, + COP028, + COP029, + COP030, + COP031, + COP210, + COP211, + COP212, + COP213, + COP214, + COP215, + COP216, + COP217, + COP218, + COP219, + COP220, + COP221, + COP222, + COP223, + COP224, + COP225, + COP226, + COP227, + COP228, + COP229, + COP230, + COP231, + COP310, + COP311, + COP312, + COP313, + COP314, + COP315, + COP316, + COP317, + COP318, + COP319, + COP320, + COP321, + COP322, + COP323, + COP324, + COP325, + COP326, + COP327, + COP328, + COP329, + COP330, + COP331, + D0, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + D9, + D10, + D11, + D12, + D13, + D14, + D15, + DSPOutFlag20, + DSPOutFlag21, + DSPOutFlag22, + DSPOutFlag23, + F0, + F1, + F2, + F3, + F4, + F5, + F6, + F7, + F8, + F9, + F10, + F11, + F12, + F13, + F14, + F15, + F16, + F17, + F18, + F19, + F20, + F21, + F22, + F23, + F24, + F25, + F26, + F27, + F28, + F29, + F30, + F31, + FCC0, + FCC1, + FCC2, + FCC3, + FCC4, + FCC5, + FCC6, + FCC7, + FCR0, + FCR1, + FCR2, + FCR3, + FCR4, + FCR5, + FCR6, + FCR7, + FCR8, + FCR9, + FCR10, + FCR11, + FCR12, + FCR13, + FCR14, + FCR15, + FCR16, + FCR17, + FCR18, + FCR19, + FCR20, + FCR21, + FCR22, + FCR23, + FCR24, + FCR25, + FCR26, + FCR27, + FCR28, + FCR29, + FCR30, + FCR31, + FP_64, + F_HI0, + F_HI1, + F_HI2, + F_HI3, + F_HI4, + F_HI5, + F_HI6, + F_HI7, + F_HI8, + F_HI9, + F_HI10, + F_HI11, + F_HI12, + F_HI13, + F_HI14, + F_HI15, + F_HI16, + F_HI17, + F_HI18, + F_HI19, + F_HI20, + F_HI21, + F_HI22, + F_HI23, + F_HI24, + F_HI25, + F_HI26, + F_HI27, + F_HI28, + F_HI29, + F_HI30, + F_HI31, + GP_64, + HI0, + HI1, + HI2, + HI3, + HWR0, + HWR1, + HWR2, + HWR3, + HWR4, + HWR5, + HWR6, + HWR7, + HWR8, + HWR9, + HWR10, + HWR11, + HWR12, + HWR13, + HWR14, + HWR15, + HWR16, + HWR17, + HWR18, + HWR19, + HWR20, + HWR21, + HWR22, + HWR23, + HWR24, + HWR25, + HWR26, + HWR27, + HWR28, + HWR29, + HWR30, + HWR31, + K0, + K1, + LO0, + LO1, + LO2, + LO3, + MPL0, + MPL1, + MPL2, + MSA8, + MSA9, + MSA10, + MSA11, + MSA12, + MSA13, + MSA14, + MSA15, + MSA16, + MSA17, + MSA18, + MSA19, + MSA20, + MSA21, + MSA22, + MSA23, + MSA24, + MSA25, + MSA26, + MSA27, + MSA28, + MSA29, + MSA30, + MSA31, + P0, + P1, + P2, + RA_64, + S0, + S1, + S2, + S3, + S4, + S5, + S6, + S7, + SP_64, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + V0, + V1, + W0, + W1, + W2, + W3, + W4, + W5, + W6, + W7, + W8, + W9, + W10, + W11, + W12, + W13, + W14, + W15, + W16, + W17, + W18, + W19, + W20, + W21, + W22, + W23, + W24, + W25, + W26, + W27, + W28, + W29, + W30, + W31, + ZERO_64, + A0_64, + A1_64, + A2_64, + A3_64, + AC0_64, + D0_64, + D1_64, + D2_64, + D3_64, + D4_64, + D5_64, + D6_64, + D7_64, + D8_64, + D9_64, + D10_64, + D11_64, + D12_64, + D13_64, + D14_64, + D15_64, + D16_64, + D17_64, + D18_64, + D19_64, + D20_64, + D21_64, + D22_64, + D23_64, + D24_64, + D25_64, + D26_64, + D27_64, + D28_64, + D29_64, + D30_64, + D31_64, + DSPOutFlag16_19, + HI0_64, + K0_64, + K1_64, + LO0_64, + S0_64, + S1_64, + S2_64, + S3_64, + S4_64, + S5_64, + S6_64, + S7_64, + T0_64, + T1_64, + T2_64, + T3_64, + T4_64, + T5_64, + T6_64, + T7_64, + T8_64, + T9_64, + V0_64, + V1_64, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::AT, + 2 => Reg::DSPCCond, + 3 => Reg::DSPCarry, + 4 => Reg::DSPEFI, + 5 => Reg::DSPOutFlag, + 6 => Reg::DSPPos, + 7 => Reg::DSPSCount, + 8 => Reg::FP, + 9 => Reg::GP, + 10 => Reg::MSAAccess, + 11 => Reg::MSACSR, + 12 => Reg::MSAIR, + 13 => Reg::MSAMap, + 14 => Reg::MSAModify, + 15 => Reg::MSARequest, + 16 => Reg::MSASave, + 17 => Reg::MSAUnmap, + 18 => Reg::PC, + 19 => Reg::RA, + 20 => Reg::SP, + 21 => Reg::ZERO, + 22 => Reg::A0, + 23 => Reg::A1, + 24 => Reg::A2, + 25 => Reg::A3, + 26 => Reg::AC0, + 27 => Reg::AC1, + 28 => Reg::AC2, + 29 => Reg::AC3, + 30 => Reg::AT_64, + 31 => Reg::COP00, + 32 => Reg::COP01, + 33 => Reg::COP02, + 34 => Reg::COP03, + 35 => Reg::COP04, + 36 => Reg::COP05, + 37 => Reg::COP06, + 38 => Reg::COP07, + 39 => Reg::COP08, + 40 => Reg::COP09, + 41 => Reg::COP20, + 42 => Reg::COP21, + 43 => Reg::COP22, + 44 => Reg::COP23, + 45 => Reg::COP24, + 46 => Reg::COP25, + 47 => Reg::COP26, + 48 => Reg::COP27, + 49 => Reg::COP28, + 50 => Reg::COP29, + 51 => Reg::COP30, + 52 => Reg::COP31, + 53 => Reg::COP32, + 54 => Reg::COP33, + 55 => Reg::COP34, + 56 => Reg::COP35, + 57 => Reg::COP36, + 58 => Reg::COP37, + 59 => Reg::COP38, + 60 => Reg::COP39, + 61 => Reg::COP010, + 62 => Reg::COP011, + 63 => Reg::COP012, + 64 => Reg::COP013, + 65 => Reg::COP014, + 66 => Reg::COP015, + 67 => Reg::COP016, + 68 => Reg::COP017, + 69 => Reg::COP018, + 70 => Reg::COP019, + 71 => Reg::COP020, + 72 => Reg::COP021, + 73 => Reg::COP022, + 74 => Reg::COP023, + 75 => Reg::COP024, + 76 => Reg::COP025, + 77 => Reg::COP026, + 78 => Reg::COP027, + 79 => Reg::COP028, + 80 => Reg::COP029, + 81 => Reg::COP030, + 82 => Reg::COP031, + 83 => Reg::COP210, + 84 => Reg::COP211, + 85 => Reg::COP212, + 86 => Reg::COP213, + 87 => Reg::COP214, + 88 => Reg::COP215, + 89 => Reg::COP216, + 90 => Reg::COP217, + 91 => Reg::COP218, + 92 => Reg::COP219, + 93 => Reg::COP220, + 94 => Reg::COP221, + 95 => Reg::COP222, + 96 => Reg::COP223, + 97 => Reg::COP224, + 98 => Reg::COP225, + 99 => Reg::COP226, + 100 => Reg::COP227, + 101 => Reg::COP228, + 102 => Reg::COP229, + 103 => Reg::COP230, + 104 => Reg::COP231, + 105 => Reg::COP310, + 106 => Reg::COP311, + 107 => Reg::COP312, + 108 => Reg::COP313, + 109 => Reg::COP314, + 110 => Reg::COP315, + 111 => Reg::COP316, + 112 => Reg::COP317, + 113 => Reg::COP318, + 114 => Reg::COP319, + 115 => Reg::COP320, + 116 => Reg::COP321, + 117 => Reg::COP322, + 118 => Reg::COP323, + 119 => Reg::COP324, + 120 => Reg::COP325, + 121 => Reg::COP326, + 122 => Reg::COP327, + 123 => Reg::COP328, + 124 => Reg::COP329, + 125 => Reg::COP330, + 126 => Reg::COP331, + 127 => Reg::D0, + 128 => Reg::D1, + 129 => Reg::D2, + 130 => Reg::D3, + 131 => Reg::D4, + 132 => Reg::D5, + 133 => Reg::D6, + 134 => Reg::D7, + 135 => Reg::D8, + 136 => Reg::D9, + 137 => Reg::D10, + 138 => Reg::D11, + 139 => Reg::D12, + 140 => Reg::D13, + 141 => Reg::D14, + 142 => Reg::D15, + 143 => Reg::DSPOutFlag20, + 144 => Reg::DSPOutFlag21, + 145 => Reg::DSPOutFlag22, + 146 => Reg::DSPOutFlag23, + 147 => Reg::F0, + 148 => Reg::F1, + 149 => Reg::F2, + 150 => Reg::F3, + 151 => Reg::F4, + 152 => Reg::F5, + 153 => Reg::F6, + 154 => Reg::F7, + 155 => Reg::F8, + 156 => Reg::F9, + 157 => Reg::F10, + 158 => Reg::F11, + 159 => Reg::F12, + 160 => Reg::F13, + 161 => Reg::F14, + 162 => Reg::F15, + 163 => Reg::F16, + 164 => Reg::F17, + 165 => Reg::F18, + 166 => Reg::F19, + 167 => Reg::F20, + 168 => Reg::F21, + 169 => Reg::F22, + 170 => Reg::F23, + 171 => Reg::F24, + 172 => Reg::F25, + 173 => Reg::F26, + 174 => Reg::F27, + 175 => Reg::F28, + 176 => Reg::F29, + 177 => Reg::F30, + 178 => Reg::F31, + 179 => Reg::FCC0, + 180 => Reg::FCC1, + 181 => Reg::FCC2, + 182 => Reg::FCC3, + 183 => Reg::FCC4, + 184 => Reg::FCC5, + 185 => Reg::FCC6, + 186 => Reg::FCC7, + 187 => Reg::FCR0, + 188 => Reg::FCR1, + 189 => Reg::FCR2, + 190 => Reg::FCR3, + 191 => Reg::FCR4, + 192 => Reg::FCR5, + 193 => Reg::FCR6, + 194 => Reg::FCR7, + 195 => Reg::FCR8, + 196 => Reg::FCR9, + 197 => Reg::FCR10, + 198 => Reg::FCR11, + 199 => Reg::FCR12, + 200 => Reg::FCR13, + 201 => Reg::FCR14, + 202 => Reg::FCR15, + 203 => Reg::FCR16, + 204 => Reg::FCR17, + 205 => Reg::FCR18, + 206 => Reg::FCR19, + 207 => Reg::FCR20, + 208 => Reg::FCR21, + 209 => Reg::FCR22, + 210 => Reg::FCR23, + 211 => Reg::FCR24, + 212 => Reg::FCR25, + 213 => Reg::FCR26, + 214 => Reg::FCR27, + 215 => Reg::FCR28, + 216 => Reg::FCR29, + 217 => Reg::FCR30, + 218 => Reg::FCR31, + 219 => Reg::FP_64, + 220 => Reg::F_HI0, + 221 => Reg::F_HI1, + 222 => Reg::F_HI2, + 223 => Reg::F_HI3, + 224 => Reg::F_HI4, + 225 => Reg::F_HI5, + 226 => Reg::F_HI6, + 227 => Reg::F_HI7, + 228 => Reg::F_HI8, + 229 => Reg::F_HI9, + 230 => Reg::F_HI10, + 231 => Reg::F_HI11, + 232 => Reg::F_HI12, + 233 => Reg::F_HI13, + 234 => Reg::F_HI14, + 235 => Reg::F_HI15, + 236 => Reg::F_HI16, + 237 => Reg::F_HI17, + 238 => Reg::F_HI18, + 239 => Reg::F_HI19, + 240 => Reg::F_HI20, + 241 => Reg::F_HI21, + 242 => Reg::F_HI22, + 243 => Reg::F_HI23, + 244 => Reg::F_HI24, + 245 => Reg::F_HI25, + 246 => Reg::F_HI26, + 247 => Reg::F_HI27, + 248 => Reg::F_HI28, + 249 => Reg::F_HI29, + 250 => Reg::F_HI30, + 251 => Reg::F_HI31, + 252 => Reg::GP_64, + 253 => Reg::HI0, + 254 => Reg::HI1, + 255 => Reg::HI2, + 256 => Reg::HI3, + 257 => Reg::HWR0, + 258 => Reg::HWR1, + 259 => Reg::HWR2, + 260 => Reg::HWR3, + 261 => Reg::HWR4, + 262 => Reg::HWR5, + 263 => Reg::HWR6, + 264 => Reg::HWR7, + 265 => Reg::HWR8, + 266 => Reg::HWR9, + 267 => Reg::HWR10, + 268 => Reg::HWR11, + 269 => Reg::HWR12, + 270 => Reg::HWR13, + 271 => Reg::HWR14, + 272 => Reg::HWR15, + 273 => Reg::HWR16, + 274 => Reg::HWR17, + 275 => Reg::HWR18, + 276 => Reg::HWR19, + 277 => Reg::HWR20, + 278 => Reg::HWR21, + 279 => Reg::HWR22, + 280 => Reg::HWR23, + 281 => Reg::HWR24, + 282 => Reg::HWR25, + 283 => Reg::HWR26, + 284 => Reg::HWR27, + 285 => Reg::HWR28, + 286 => Reg::HWR29, + 287 => Reg::HWR30, + 288 => Reg::HWR31, + 289 => Reg::K0, + 290 => Reg::K1, + 291 => Reg::LO0, + 292 => Reg::LO1, + 293 => Reg::LO2, + 294 => Reg::LO3, + 295 => Reg::MPL0, + 296 => Reg::MPL1, + 297 => Reg::MPL2, + 298 => Reg::MSA8, + 299 => Reg::MSA9, + 300 => Reg::MSA10, + 301 => Reg::MSA11, + 302 => Reg::MSA12, + 303 => Reg::MSA13, + 304 => Reg::MSA14, + 305 => Reg::MSA15, + 306 => Reg::MSA16, + 307 => Reg::MSA17, + 308 => Reg::MSA18, + 309 => Reg::MSA19, + 310 => Reg::MSA20, + 311 => Reg::MSA21, + 312 => Reg::MSA22, + 313 => Reg::MSA23, + 314 => Reg::MSA24, + 315 => Reg::MSA25, + 316 => Reg::MSA26, + 317 => Reg::MSA27, + 318 => Reg::MSA28, + 319 => Reg::MSA29, + 320 => Reg::MSA30, + 321 => Reg::MSA31, + 322 => Reg::P0, + 323 => Reg::P1, + 324 => Reg::P2, + 325 => Reg::RA_64, + 326 => Reg::S0, + 327 => Reg::S1, + 328 => Reg::S2, + 329 => Reg::S3, + 330 => Reg::S4, + 331 => Reg::S5, + 332 => Reg::S6, + 333 => Reg::S7, + 334 => Reg::SP_64, + 335 => Reg::T0, + 336 => Reg::T1, + 337 => Reg::T2, + 338 => Reg::T3, + 339 => Reg::T4, + 340 => Reg::T5, + 341 => Reg::T6, + 342 => Reg::T7, + 343 => Reg::T8, + 344 => Reg::T9, + 345 => Reg::V0, + 346 => Reg::V1, + 347 => Reg::W0, + 348 => Reg::W1, + 349 => Reg::W2, + 350 => Reg::W3, + 351 => Reg::W4, + 352 => Reg::W5, + 353 => Reg::W6, + 354 => Reg::W7, + 355 => Reg::W8, + 356 => Reg::W9, + 357 => Reg::W10, + 358 => Reg::W11, + 359 => Reg::W12, + 360 => Reg::W13, + 361 => Reg::W14, + 362 => Reg::W15, + 363 => Reg::W16, + 364 => Reg::W17, + 365 => Reg::W18, + 366 => Reg::W19, + 367 => Reg::W20, + 368 => Reg::W21, + 369 => Reg::W22, + 370 => Reg::W23, + 371 => Reg::W24, + 372 => Reg::W25, + 373 => Reg::W26, + 374 => Reg::W27, + 375 => Reg::W28, + 376 => Reg::W29, + 377 => Reg::W30, + 378 => Reg::W31, + 379 => Reg::ZERO_64, + 380 => Reg::A0_64, + 381 => Reg::A1_64, + 382 => Reg::A2_64, + 383 => Reg::A3_64, + 384 => Reg::AC0_64, + 385 => Reg::D0_64, + 386 => Reg::D1_64, + 387 => Reg::D2_64, + 388 => Reg::D3_64, + 389 => Reg::D4_64, + 390 => Reg::D5_64, + 391 => Reg::D6_64, + 392 => Reg::D7_64, + 393 => Reg::D8_64, + 394 => Reg::D9_64, + 395 => Reg::D10_64, + 396 => Reg::D11_64, + 397 => Reg::D12_64, + 398 => Reg::D13_64, + 399 => Reg::D14_64, + 400 => Reg::D15_64, + 401 => Reg::D16_64, + 402 => Reg::D17_64, + 403 => Reg::D18_64, + 404 => Reg::D19_64, + 405 => Reg::D20_64, + 406 => Reg::D21_64, + 407 => Reg::D22_64, + 408 => Reg::D23_64, + 409 => Reg::D24_64, + 410 => Reg::D25_64, + 411 => Reg::D26_64, + 412 => Reg::D27_64, + 413 => Reg::D28_64, + 414 => Reg::D29_64, + 415 => Reg::D30_64, + 416 => Reg::D31_64, + 417 => Reg::DSPOutFlag16_19, + 418 => Reg::HI0_64, + 419 => Reg::K0_64, + 420 => Reg::K1_64, + 421 => Reg::LO0_64, + 422 => Reg::S0_64, + 423 => Reg::S1_64, + 424 => Reg::S2_64, + 425 => Reg::S3_64, + 426 => Reg::S4_64, + 427 => Reg::S5_64, + 428 => Reg::S6_64, + 429 => Reg::S7_64, + 430 => Reg::T0_64, + 431 => Reg::T1_64, + 432 => Reg::T2_64, + 433 => Reg::T3_64, + 434 => Reg::T4_64, + 435 => Reg::T5_64, + 436 => Reg::T6_64, + 437 => Reg::T7_64, + 438 => Reg::T8_64, + 439 => Reg::T9_64, + 440 => Reg::V0_64, + 441 => Reg::V1_64, + 442 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc.rs new file mode 100644 index 0000000..8822108 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc.rs @@ -0,0 +1,18 @@ +//! PowerPC architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/instruction.rs new file mode 100644 index 0000000..113c32f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/instruction.rs @@ -0,0 +1,52 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +use crate::assembly::powerpc; +use crate::declare_fwd_iterator; + +/// This structure represents a PowerPC (ppc64/ppc32) instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`powerpc::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } +} + +declare_fwd_iterator!( + Operands, + powerpc::Operands, + ffi::asm_Instruction, + ffi::asm_powerpc_Operand, + ffi::asm_powerpc_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/opcodes.rs new file mode 100644 index 0000000..ef79904 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/opcodes.rs @@ -0,0 +1,6007 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ATOMIC_CMP_SWAP_I128, + ATOMIC_LOAD_ADD_I128, + ATOMIC_LOAD_AND_I128, + ATOMIC_LOAD_NAND_I128, + ATOMIC_LOAD_OR_I128, + ATOMIC_LOAD_SUB_I128, + ATOMIC_LOAD_XOR_I128, + ATOMIC_SWAP_I128, + BUILD_QUADWORD, + BUILD_UACC, + CFENCE, + CFENCE8, + CLRLSLDI, + CLRLSLDI_rec, + CLRLSLWI, + CLRLSLWI_rec, + CLRRDI, + CLRRDI_rec, + CLRRWI, + CLRRWI_rec, + DCBFL, + DCBFLP, + DCBFPS, + DCBFx, + DCBSTPS, + DCBTCT, + DCBTDS, + DCBTSTCT, + DCBTSTDS, + DCBTSTT, + DCBTSTx, + DCBTT, + DCBTx, + DFLOADf32, + DFLOADf64, + DFSTOREf32, + DFSTOREf64, + EXTLDI, + EXTLDI_rec, + EXTLWI, + EXTLWI_rec, + EXTRDI, + EXTRDI_rec, + EXTRWI, + EXTRWI_rec, + INSLWI, + INSLWI_rec, + INSRDI, + INSRDI_rec, + INSRWI, + INSRWI_rec, + KILL_PAIR, + LAx, + LIWAX, + LIWZX, + PPCLdFixedAddr, + PSUBI, + RLWIMIbm, + RLWIMIbm_rec, + RLWINMbm, + RLWINMbm_rec, + RLWNMbm, + RLWNMbm_rec, + ROTRDI, + ROTRDI_rec, + ROTRWI, + ROTRWI_rec, + SLDI, + SLDI_rec, + SLWI, + SLWI_rec, + SPILLTOVSR_LD, + SPILLTOVSR_LDX, + SPILLTOVSR_ST, + SPILLTOVSR_STX, + SRDI, + SRDI_rec, + SRWI, + SRWI_rec, + STIWX, + SUBI, + SUBIC, + SUBIC_rec, + SUBIS, + SUBPCIS, + XFLOADf32, + XFLOADf64, + XFSTOREf32, + XFSTOREf64, + ADD4, + ADD4O, + ADD4O_rec, + ADD4TLS, + ADD4_rec, + ADD8, + ADD8O, + ADD8O_rec, + ADD8TLS, + ADD8TLS_, + ADD8_rec, + ADDC, + ADDC8, + ADDC8O, + ADDC8O_rec, + ADDC8_rec, + ADDCO, + ADDCO_rec, + ADDC_rec, + ADDE, + ADDE8, + ADDE8O, + ADDE8O_rec, + ADDE8_rec, + ADDEO, + ADDEO_rec, + ADDEX, + ADDEX8, + ADDE_rec, + ADDG6S, + ADDG6S8, + ADDI, + ADDI8, + ADDIC, + ADDIC8, + ADDIC_rec, + ADDIS, + ADDIS8, + ADDISdtprelHA, + ADDISdtprelHA32, + ADDISgotTprelHA, + ADDIStlsgdHA, + ADDIStlsldHA, + ADDIStocHA, + ADDIStocHA8, + ADDIdtprelL, + ADDIdtprelL32, + ADDItlsgdL, + ADDItlsgdL32, + ADDItlsgdLADDR, + ADDItlsgdLADDR32, + ADDItlsldL, + ADDItlsldL32, + ADDItlsldLADDR, + ADDItlsldLADDR32, + ADDItoc, + ADDItoc8, + ADDItocL, + ADDItocL8, + ADDME, + ADDME8, + ADDME8O, + ADDME8O_rec, + ADDME8_rec, + ADDMEO, + ADDMEO_rec, + ADDME_rec, + ADDPCIS, + ADDZE, + ADDZE8, + ADDZE8O, + ADDZE8O_rec, + ADDZE8_rec, + ADDZEO, + ADDZEO_rec, + ADDZE_rec, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + AND, + AND8, + AND8_rec, + ANDC, + ANDC8, + ANDC8_rec, + ANDC_rec, + ANDI8_rec, + ANDIS8_rec, + ANDIS_rec, + ANDI_rec, + ANDI_rec_1_EQ_BIT, + ANDI_rec_1_EQ_BIT8, + ANDI_rec_1_GT_BIT, + ANDI_rec_1_GT_BIT8, + AND_rec, + ATOMIC_CMP_SWAP_I16, + ATOMIC_CMP_SWAP_I32, + ATOMIC_CMP_SWAP_I64, + ATOMIC_CMP_SWAP_I8, + ATOMIC_LOAD_ADD_I16, + ATOMIC_LOAD_ADD_I32, + ATOMIC_LOAD_ADD_I64, + ATOMIC_LOAD_ADD_I8, + ATOMIC_LOAD_AND_I16, + ATOMIC_LOAD_AND_I32, + ATOMIC_LOAD_AND_I64, + ATOMIC_LOAD_AND_I8, + ATOMIC_LOAD_MAX_I16, + ATOMIC_LOAD_MAX_I32, + ATOMIC_LOAD_MAX_I64, + ATOMIC_LOAD_MAX_I8, + ATOMIC_LOAD_MIN_I16, + ATOMIC_LOAD_MIN_I32, + ATOMIC_LOAD_MIN_I64, + ATOMIC_LOAD_MIN_I8, + ATOMIC_LOAD_NAND_I16, + ATOMIC_LOAD_NAND_I32, + ATOMIC_LOAD_NAND_I64, + ATOMIC_LOAD_NAND_I8, + ATOMIC_LOAD_OR_I16, + ATOMIC_LOAD_OR_I32, + ATOMIC_LOAD_OR_I64, + ATOMIC_LOAD_OR_I8, + ATOMIC_LOAD_SUB_I16, + ATOMIC_LOAD_SUB_I32, + ATOMIC_LOAD_SUB_I64, + ATOMIC_LOAD_SUB_I8, + ATOMIC_LOAD_UMAX_I16, + ATOMIC_LOAD_UMAX_I32, + ATOMIC_LOAD_UMAX_I64, + ATOMIC_LOAD_UMAX_I8, + ATOMIC_LOAD_UMIN_I16, + ATOMIC_LOAD_UMIN_I32, + ATOMIC_LOAD_UMIN_I64, + ATOMIC_LOAD_UMIN_I8, + ATOMIC_LOAD_XOR_I16, + ATOMIC_LOAD_XOR_I32, + ATOMIC_LOAD_XOR_I64, + ATOMIC_LOAD_XOR_I8, + ATOMIC_SWAP_I16, + ATOMIC_SWAP_I32, + ATOMIC_SWAP_I64, + ATOMIC_SWAP_I8, + ATTN, + B, + BA, + BC, + BCC, + BCCA, + BCCCTR, + BCCCTR8, + BCCCTRL, + BCCCTRL8, + BCCL, + BCCLA, + BCCLR, + BCCLRL, + BCCTR, + BCCTR8, + BCCTR8n, + BCCTRL, + BCCTRL8, + BCCTRL8n, + BCCTRLn, + BCCTRn, + BCDADD_rec, + BCDCFN_rec, + BCDCFSQ_rec, + BCDCFZ_rec, + BCDCPSGN_rec, + BCDCTN_rec, + BCDCTSQ_rec, + BCDCTZ_rec, + BCDSETSGN_rec, + BCDSR_rec, + BCDSUB_rec, + BCDS_rec, + BCDTRUNC_rec, + BCDUS_rec, + BCDUTRUNC_rec, + BCL, + BCLR, + BCLRL, + BCLRLn, + BCLRn, + BCLalways, + BCLn, + BCTR, + BCTR8, + BCTRL, + BCTRL8, + BCTRL8_LDinto_toc, + BCTRL8_LDinto_toc_RM, + BCTRL8_RM, + BCTRL_LWZinto_toc, + BCTRL_LWZinto_toc_RM, + BCTRL_RM, + BCn, + BDNZ, + BDNZ8, + BDNZA, + BDNZAm, + BDNZAp, + BDNZL, + BDNZLA, + BDNZLAm, + BDNZLAp, + BDNZLR, + BDNZLR8, + BDNZLRL, + BDNZLRLm, + BDNZLRLp, + BDNZLRm, + BDNZLRp, + BDNZLm, + BDNZLp, + BDNZm, + BDNZp, + BDZ, + BDZ8, + BDZA, + BDZAm, + BDZAp, + BDZL, + BDZLA, + BDZLAm, + BDZLAp, + BDZLR, + BDZLR8, + BDZLRL, + BDZLRLm, + BDZLRLp, + BDZLRm, + BDZLRp, + BDZLm, + BDZLp, + BDZm, + BDZp, + BL, + BL8, + BL8_NOP, + BL8_NOP_RM, + BL8_NOP_TLS, + BL8_NOTOC, + BL8_NOTOC_RM, + BL8_NOTOC_TLS, + BL8_RM, + BL8_TLS, + BL8_TLS_, + BLA, + BLA8, + BLA8_NOP, + BLA8_NOP_RM, + BLA8_RM, + BLA_RM, + BLR, + BLR8, + BLRL, + BL_NOP, + BL_NOP_RM, + BL_RM, + BL_TLS, + BPERMD, + BRD, + BRH, + BRH8, + BRINC, + BRW, + BRW8, + CBCDTD, + CBCDTD8, + CDTBCD, + CDTBCD8, + CFUGED, + CLRBHRB, + CMPB, + CMPB8, + CMPD, + CMPDI, + CMPEQB, + CMPLD, + CMPLDI, + CMPLW, + CMPLWI, + CMPRB, + CMPRB8, + CMPW, + CMPWI, + CNTLZD, + CNTLZDM, + CNTLZD_rec, + CNTLZW, + CNTLZW8, + CNTLZW8_rec, + CNTLZW_rec, + CNTTZD, + CNTTZDM, + CNTTZD_rec, + CNTTZW, + CNTTZW8, + CNTTZW8_rec, + CNTTZW_rec, + CP_ABORT, + CP_COPY, + CP_COPY8, + CP_PASTE8_rec, + CP_PASTE_rec, + CR6SET, + CR6UNSET, + CRAND, + CRANDC, + CREQV, + CRNAND, + CRNOR, + CRNOT, + CROR, + CRORC, + CRSET, + CRUNSET, + CRXOR, + CTRL_DEP, + DADD, + DADDQ, + DADDQ_rec, + DADD_rec, + DARN, + DCBA, + DCBF, + DCBFEP, + DCBI, + DCBST, + DCBSTEP, + DCBT, + DCBTEP, + DCBTST, + DCBTSTEP, + DCBZ, + DCBZEP, + DCBZL, + DCBZLEP, + DCCCI, + DCFFIX, + DCFFIXQ, + DCFFIXQQ, + DCFFIXQ_rec, + DCFFIX_rec, + DCMPO, + DCMPOQ, + DCMPU, + DCMPUQ, + DCTDP, + DCTDP_rec, + DCTFIX, + DCTFIXQ, + DCTFIXQQ, + DCTFIXQ_rec, + DCTFIX_rec, + DCTQPQ, + DCTQPQ_rec, + DDEDPD, + DDEDPDQ, + DDEDPDQ_rec, + DDEDPD_rec, + DDIV, + DDIVQ, + DDIVQ_rec, + DDIV_rec, + DENBCD, + DENBCDQ, + DENBCDQ_rec, + DENBCD_rec, + DIEX, + DIEXQ, + DIEXQ_rec, + DIEX_rec, + DIVD, + DIVDE, + DIVDEO, + DIVDEO_rec, + DIVDEU, + DIVDEUO, + DIVDEUO_rec, + DIVDEU_rec, + DIVDE_rec, + DIVDO, + DIVDO_rec, + DIVDU, + DIVDUO, + DIVDUO_rec, + DIVDU_rec, + DIVD_rec, + DIVW, + DIVWE, + DIVWEO, + DIVWEO_rec, + DIVWEU, + DIVWEUO, + DIVWEUO_rec, + DIVWEU_rec, + DIVWE_rec, + DIVWO, + DIVWO_rec, + DIVWU, + DIVWUO, + DIVWUO_rec, + DIVWU_rec, + DIVW_rec, + DMMR, + DMSETDMRZ, + DMSHA2HASH, + DMSHA3HASH, + DMUL, + DMULQ, + DMULQ_rec, + DMUL_rec, + DMXOR, + DMXVBF16GERX2, + DMXVBF16GERX2NN, + DMXVBF16GERX2NP, + DMXVBF16GERX2PN, + DMXVBF16GERX2PP, + DMXVF16GERX2, + DMXVF16GERX2NN, + DMXVF16GERX2NP, + DMXVF16GERX2PN, + DMXVF16GERX2PP, + DMXVI8GERX4, + DMXVI8GERX4PP, + DMXVI8GERX4SPP, + DMXXEXTFDMR256, + DMXXEXTFDMR512, + DMXXEXTFDMR512_HI, + DMXXINSTDMR256, + DMXXINSTDMR512, + DMXXINSTDMR512_HI, + DMXXSETACCZ, + DMXXSHAPAD, + DQUA, + DQUAI, + DQUAIQ, + DQUAIQ_rec, + DQUAI_rec, + DQUAQ, + DQUAQ_rec, + DQUA_rec, + DRDPQ, + DRDPQ_rec, + DRINTN, + DRINTNQ, + DRINTNQ_rec, + DRINTN_rec, + DRINTX, + DRINTXQ, + DRINTXQ_rec, + DRINTX_rec, + DRRND, + DRRNDQ, + DRRNDQ_rec, + DRRND_rec, + DRSP, + DRSP_rec, + DSCLI, + DSCLIQ, + DSCLIQ_rec, + DSCLI_rec, + DSCRI, + DSCRIQ, + DSCRIQ_rec, + DSCRI_rec, + DSS, + DSSALL, + DST, + DST64, + DSTST, + DSTST64, + DSTSTT, + DSTSTT64, + DSTT, + DSTT64, + DSUB, + DSUBQ, + DSUBQ_rec, + DSUB_rec, + DTSTDC, + DTSTDCQ, + DTSTDG, + DTSTDGQ, + DTSTEX, + DTSTEXQ, + DTSTSF, + DTSTSFI, + DTSTSFIQ, + DTSTSFQ, + DXEX, + DXEXQ, + DXEXQ_rec, + DXEX_rec, + DYNALLOC, + DYNALLOC8, + DYNAREAOFFSET, + DYNAREAOFFSET8, + DecreaseCTR8loop, + DecreaseCTRloop, + EFDABS, + EFDADD, + EFDCFS, + EFDCFSF, + EFDCFSI, + EFDCFSID, + EFDCFUF, + EFDCFUI, + EFDCFUID, + EFDCMPEQ, + EFDCMPGT, + EFDCMPLT, + EFDCTSF, + EFDCTSI, + EFDCTSIDZ, + EFDCTSIZ, + EFDCTUF, + EFDCTUI, + EFDCTUIDZ, + EFDCTUIZ, + EFDDIV, + EFDMUL, + EFDNABS, + EFDNEG, + EFDSUB, + EFDTSTEQ, + EFDTSTGT, + EFDTSTLT, + EFSABS, + EFSADD, + EFSCFD, + EFSCFSF, + EFSCFSI, + EFSCFUF, + EFSCFUI, + EFSCMPEQ, + EFSCMPGT, + EFSCMPLT, + EFSCTSF, + EFSCTSI, + EFSCTSIZ, + EFSCTUF, + EFSCTUI, + EFSCTUIZ, + EFSDIV, + EFSMUL, + EFSNABS, + EFSNEG, + EFSSUB, + EFSTSTEQ, + EFSTSTGT, + EFSTSTLT, + EH_SjLj_LongJmp32, + EH_SjLj_LongJmp64, + EH_SjLj_SetJmp32, + EH_SjLj_SetJmp64, + EH_SjLj_Setup, + EQV, + EQV8, + EQV8_rec, + EQV_rec, + EVABS, + EVADDIW, + EVADDSMIAAW, + EVADDSSIAAW, + EVADDUMIAAW, + EVADDUSIAAW, + EVADDW, + EVAND, + EVANDC, + EVCMPEQ, + EVCMPGTS, + EVCMPGTU, + EVCMPLTS, + EVCMPLTU, + EVCNTLSW, + EVCNTLZW, + EVDIVWS, + EVDIVWU, + EVEQV, + EVEXTSB, + EVEXTSH, + EVFSABS, + EVFSADD, + EVFSCFSF, + EVFSCFSI, + EVFSCFUF, + EVFSCFUI, + EVFSCMPEQ, + EVFSCMPGT, + EVFSCMPLT, + EVFSCTSF, + EVFSCTSI, + EVFSCTSIZ, + EVFSCTUF, + EVFSCTUI, + EVFSCTUIZ, + EVFSDIV, + EVFSMUL, + EVFSNABS, + EVFSNEG, + EVFSSUB, + EVFSTSTEQ, + EVFSTSTGT, + EVFSTSTLT, + EVLDD, + EVLDDX, + EVLDH, + EVLDHX, + EVLDW, + EVLDWX, + EVLHHESPLAT, + EVLHHESPLATX, + EVLHHOSSPLAT, + EVLHHOSSPLATX, + EVLHHOUSPLAT, + EVLHHOUSPLATX, + EVLWHE, + EVLWHEX, + EVLWHOS, + EVLWHOSX, + EVLWHOU, + EVLWHOUX, + EVLWHSPLAT, + EVLWHSPLATX, + EVLWWSPLAT, + EVLWWSPLATX, + EVMERGEHI, + EVMERGEHILO, + EVMERGELO, + EVMERGELOHI, + EVMHEGSMFAA, + EVMHEGSMFAN, + EVMHEGSMIAA, + EVMHEGSMIAN, + EVMHEGUMIAA, + EVMHEGUMIAN, + EVMHESMF, + EVMHESMFA, + EVMHESMFAAW, + EVMHESMFANW, + EVMHESMI, + EVMHESMIA, + EVMHESMIAAW, + EVMHESMIANW, + EVMHESSF, + EVMHESSFA, + EVMHESSFAAW, + EVMHESSFANW, + EVMHESSIAAW, + EVMHESSIANW, + EVMHEUMI, + EVMHEUMIA, + EVMHEUMIAAW, + EVMHEUMIANW, + EVMHEUSIAAW, + EVMHEUSIANW, + EVMHOGSMFAA, + EVMHOGSMFAN, + EVMHOGSMIAA, + EVMHOGSMIAN, + EVMHOGUMIAA, + EVMHOGUMIAN, + EVMHOSMF, + EVMHOSMFA, + EVMHOSMFAAW, + EVMHOSMFANW, + EVMHOSMI, + EVMHOSMIA, + EVMHOSMIAAW, + EVMHOSMIANW, + EVMHOSSF, + EVMHOSSFA, + EVMHOSSFAAW, + EVMHOSSFANW, + EVMHOSSIAAW, + EVMHOSSIANW, + EVMHOUMI, + EVMHOUMIA, + EVMHOUMIAAW, + EVMHOUMIANW, + EVMHOUSIAAW, + EVMHOUSIANW, + EVMRA, + EVMWHSMF, + EVMWHSMFA, + EVMWHSMI, + EVMWHSMIA, + EVMWHSSF, + EVMWHSSFA, + EVMWHUMI, + EVMWHUMIA, + EVMWLSMIAAW, + EVMWLSMIANW, + EVMWLSSIAAW, + EVMWLSSIANW, + EVMWLUMI, + EVMWLUMIA, + EVMWLUMIAAW, + EVMWLUMIANW, + EVMWLUSIAAW, + EVMWLUSIANW, + EVMWSMF, + EVMWSMFA, + EVMWSMFAA, + EVMWSMFAN, + EVMWSMI, + EVMWSMIA, + EVMWSMIAA, + EVMWSMIAN, + EVMWSSF, + EVMWSSFA, + EVMWSSFAA, + EVMWSSFAN, + EVMWUMI, + EVMWUMIA, + EVMWUMIAA, + EVMWUMIAN, + EVNAND, + EVNEG, + EVNOR, + EVOR, + EVORC, + EVRLW, + EVRLWI, + EVRNDW, + EVSEL, + EVSLW, + EVSLWI, + EVSPLATFI, + EVSPLATI, + EVSRWIS, + EVSRWIU, + EVSRWS, + EVSRWU, + EVSTDD, + EVSTDDX, + EVSTDH, + EVSTDHX, + EVSTDW, + EVSTDWX, + EVSTWHE, + EVSTWHEX, + EVSTWHO, + EVSTWHOX, + EVSTWWE, + EVSTWWEX, + EVSTWWO, + EVSTWWOX, + EVSUBFSMIAAW, + EVSUBFSSIAAW, + EVSUBFUMIAAW, + EVSUBFUSIAAW, + EVSUBFW, + EVSUBIFW, + EVXOR, + EXTSB, + EXTSB8, + EXTSB8_32_64, + EXTSB8_rec, + EXTSB_rec, + EXTSH, + EXTSH8, + EXTSH8_32_64, + EXTSH8_rec, + EXTSH_rec, + EXTSW, + EXTSWSLI, + EXTSWSLI_32_64, + EXTSWSLI_32_64_rec, + EXTSWSLI_rec, + EXTSW_32, + EXTSW_32_64, + EXTSW_32_64_rec, + EXTSW_rec, + EnforceIEIO, + FABSD, + FABSD_rec, + FABSS, + FABSS_rec, + FADD, + FADDS, + FADDS_rec, + FADD_rec, + FADDrtz, + FCFID, + FCFIDS, + FCFIDS_rec, + FCFIDU, + FCFIDUS, + FCFIDUS_rec, + FCFIDU_rec, + FCFID_rec, + FCMPOD, + FCMPOS, + FCMPUD, + FCMPUS, + FCPSGND, + FCPSGND_rec, + FCPSGNS, + FCPSGNS_rec, + FCTID, + FCTIDU, + FCTIDUZ, + FCTIDUZ_rec, + FCTIDU_rec, + FCTIDZ, + FCTIDZ_rec, + FCTID_rec, + FCTIW, + FCTIWU, + FCTIWUZ, + FCTIWUZ_rec, + FCTIWU_rec, + FCTIWZ, + FCTIWZ_rec, + FCTIW_rec, + FDIV, + FDIVS, + FDIVS_rec, + FDIV_rec, + FENCE, + FMADD, + FMADDS, + FMADDS_rec, + FMADD_rec, + FMR, + FMR_rec, + FMSUB, + FMSUBS, + FMSUBS_rec, + FMSUB_rec, + FMUL, + FMULS, + FMULS_rec, + FMUL_rec, + FNABSD, + FNABSD_rec, + FNABSS, + FNABSS_rec, + FNEGD, + FNEGD_rec, + FNEGS, + FNEGS_rec, + FNMADD, + FNMADDS, + FNMADDS_rec, + FNMADD_rec, + FNMSUB, + FNMSUBS, + FNMSUBS_rec, + FNMSUB_rec, + FRE, + FRES, + FRES_rec, + FRE_rec, + FRIMD, + FRIMD_rec, + FRIMS, + FRIMS_rec, + FRIND, + FRIND_rec, + FRINS, + FRINS_rec, + FRIPD, + FRIPD_rec, + FRIPS, + FRIPS_rec, + FRIZD, + FRIZD_rec, + FRIZS, + FRIZS_rec, + FRSP, + FRSP_rec, + FRSQRTE, + FRSQRTES, + FRSQRTES_rec, + FRSQRTE_rec, + FSELD, + FSELD_rec, + FSELS, + FSELS_rec, + FSQRT, + FSQRTS, + FSQRTS_rec, + FSQRT_rec, + FSUB, + FSUBS, + FSUBS_rec, + FSUB_rec, + FTDIV, + FTSQRT, + GETtlsADDR, + GETtlsADDR32, + GETtlsADDR32AIX, + GETtlsADDR64AIX, + GETtlsADDRPCREL, + GETtlsMOD32AIX, + GETtlsMOD64AIX, + GETtlsTpointer32AIX, + GETtlsldADDR, + GETtlsldADDR32, + GETtlsldADDRPCREL, + HASHCHK, + HASHCHK8, + HASHCHKP, + HASHCHKP8, + HASHST, + HASHST8, + HASHSTP, + HASHSTP8, + HRFID, + ICBI, + ICBIEP, + ICBLC, + ICBLQ, + ICBT, + ICBTLS, + ICCCI, + ISEL, + ISEL8, + ISYNC, + LA, + LA8, + LBARX, + LBARXL, + LBEPX, + LBZ, + LBZ8, + LBZCIX, + LBZU, + LBZU8, + LBZUX, + LBZUX8, + LBZX, + LBZX8, + LBZXTLS, + LBZXTLS_, + LBZXTLS_32, + LD, + LDARX, + LDARXL, + LDAT, + LDAT_PSEUDO, + LDBRX, + LDCIX, + LDU, + LDUX, + LDX, + LDXTLS, + LDXTLS_, + LDgotTprelL, + LDgotTprelL32, + LDtoc, + LDtocBA, + LDtocCPT, + LDtocJTI, + LDtocL, + LFD, + LFDEPX, + LFDU, + LFDUX, + LFDX, + LFDXTLS, + LFDXTLS_, + LFIWAX, + LFIWZX, + LFS, + LFSU, + LFSUX, + LFSX, + LFSXTLS, + LFSXTLS_, + LHA, + LHA8, + LHARX, + LHARXL, + LHAU, + LHAU8, + LHAUX, + LHAUX8, + LHAX, + LHAX8, + LHAXTLS, + LHAXTLS_, + LHAXTLS_32, + LHBRX, + LHBRX8, + LHEPX, + LHZ, + LHZ8, + LHZCIX, + LHZU, + LHZU8, + LHZUX, + LHZUX8, + LHZX, + LHZX8, + LHZXTLS, + LHZXTLS_, + LHZXTLS_32, + LI, + LI8, + LIS, + LIS8, + LMW, + LQ, + LQARX, + LQARXL, + LQX_PSEUDO, + LSWI, + LVEBX, + LVEHX, + LVEWX, + LVSL, + LVSR, + LVX, + LVXL, + LWA, + LWARX, + LWARXL, + LWAT, + LWAT_PSEUDO, + LWAUX, + LWAX, + LWAXTLS, + LWAXTLS_, + LWAXTLS_32, + LWAX_32, + LWA_32, + LWBRX, + LWBRX8, + LWEPX, + LWZ, + LWZ8, + LWZCIX, + LWZU, + LWZU8, + LWZUX, + LWZUX8, + LWZX, + LWZX8, + LWZXTLS, + LWZXTLS_, + LWZXTLS_32, + LWZtoc, + LWZtocL, + LXSD, + LXSDX, + LXSIBZX, + LXSIHZX, + LXSIWAX, + LXSIWZX, + LXSSP, + LXSSPX, + LXV, + LXVB16X, + LXVD2X, + LXVDSX, + LXVH8X, + LXVKQ, + LXVL, + LXVLL, + LXVP, + LXVPB32X, + LXVPRL, + LXVPRLL, + LXVPX, + LXVRBX, + LXVRDX, + LXVRHX, + LXVRL, + LXVRLL, + LXVRWX, + LXVW4X, + LXVWSX, + LXVX, + MADDHD, + MADDHDU, + MADDLD, + MADDLD8, + MBAR, + MCRF, + MCRFS, + MCRXRX, + MFBHRBE, + MFCR, + MFCR8, + MFCTR, + MFCTR8, + MFDCR, + MFFS, + MFFSCDRN, + MFFSCDRNI, + MFFSCE, + MFFSCRN, + MFFSCRNI, + MFFSL, + MFFS_rec, + MFLR, + MFLR8, + MFMSR, + MFOCRF, + MFOCRF8, + MFPMR, + MFSPR, + MFSPR8, + MFSR, + MFSRIN, + MFTB, + MFTB8, + MFUDSCR, + MFVRD, + MFVRSAVE, + MFVRSAVEv, + MFVRWZ, + MFVSCR, + MFVSRD, + MFVSRLD, + MFVSRWZ, + MODSD, + MODSW, + MODUD, + MODUW, + MSGSYNC, + MSYNC, + MTCRF, + MTCRF8, + MTCTR, + MTCTR8, + MTCTR8loop, + MTCTRloop, + MTDCR, + MTFSB0, + MTFSB1, + MTFSF, + MTFSFI, + MTFSFI_rec, + MTFSFIb, + MTFSF_rec, + MTFSFb, + MTLPL, + MTLPL8, + MTLR, + MTLR8, + MTMSR, + MTMSRD, + MTOCRF, + MTOCRF8, + MTPMR, + MTSPR, + MTSPR8, + MTSR, + MTSRIN, + MTUDSCR, + MTVRD, + MTVRSAVE, + MTVRSAVEv, + MTVRWA, + MTVRWZ, + MTVSCR, + MTVSRBM, + MTVSRBMI, + MTVSRD, + MTVSRDD, + MTVSRDM, + MTVSRHM, + MTVSRQM, + MTVSRWA, + MTVSRWM, + MTVSRWS, + MTVSRWZ, + MULHD, + MULHDU, + MULHDU_rec, + MULHD_rec, + MULHW, + MULHWU, + MULHWU_rec, + MULHW_rec, + MULLD, + MULLDO, + MULLDO_rec, + MULLD_rec, + MULLI, + MULLI8, + MULLW, + MULLWO, + MULLWO_rec, + MULLW_rec, + MoveGOTtoLR, + MovePCtoLR, + MovePCtoLR8, + NAND, + NAND8, + NAND8_rec, + NAND_rec, + NAP, + NEG, + NEG8, + NEG8O, + NEG8O_rec, + NEG8_rec, + NEGO, + NEGO_rec, + NEG_rec, + NOP, + NOP_GT_PWR6, + NOP_GT_PWR7, + NOR, + NOR8, + NOR8_rec, + NOR_rec, + OR, + OR8, + OR8_rec, + ORC, + ORC8, + ORC8_rec, + ORC_rec, + ORI, + ORI8, + ORIS, + ORIS8, + OR_rec, + PADDI, + PADDI8, + PADDI8pc, + PADDIS, + PADDIS8, + PADDIS8pc, + PADDISpc, + PADDIdtprel, + PADDIpc, + PDEPD, + PEXTD, + PLA, + PLA8, + PLA8pc, + PLApc, + PLBZ, + PLBZ8, + PLBZ8nopc, + PLBZ8onlypc, + PLBZ8pc, + PLBZnopc, + PLBZonlypc, + PLBZpc, + PLD, + PLDnopc, + PLDonlypc, + PLDpc, + PLFD, + PLFDnopc, + PLFDonlypc, + PLFDpc, + PLFS, + PLFSnopc, + PLFSonlypc, + PLFSpc, + PLHA, + PLHA8, + PLHA8nopc, + PLHA8onlypc, + PLHA8pc, + PLHAnopc, + PLHAonlypc, + PLHApc, + PLHZ, + PLHZ8, + PLHZ8nopc, + PLHZ8onlypc, + PLHZ8pc, + PLHZnopc, + PLHZonlypc, + PLHZpc, + PLI, + PLI8, + PLWA, + PLWA8, + PLWA8nopc, + PLWA8onlypc, + PLWA8pc, + PLWAnopc, + PLWAonlypc, + PLWApc, + PLWZ, + PLWZ8, + PLWZ8nopc, + PLWZ8onlypc, + PLWZ8pc, + PLWZnopc, + PLWZonlypc, + PLWZpc, + PLXSD, + PLXSDnopc, + PLXSDonlypc, + PLXSDpc, + PLXSSP, + PLXSSPnopc, + PLXSSPonlypc, + PLXSSPpc, + PLXV, + PLXVP, + PLXVPnopc, + PLXVPonlypc, + PLXVPpc, + PLXVnopc, + PLXVonlypc, + PLXVpc, + PMDMXVBF16GERX2, + PMDMXVBF16GERX2NN, + PMDMXVBF16GERX2NP, + PMDMXVBF16GERX2PN, + PMDMXVBF16GERX2PP, + PMDMXVF16GERX2, + PMDMXVF16GERX2NN, + PMDMXVF16GERX2NP, + PMDMXVF16GERX2PN, + PMDMXVF16GERX2PP, + PMDMXVI8GERX4, + PMDMXVI8GERX4PP, + PMDMXVI8GERX4SPP, + PMXVBF16GER2, + PMXVBF16GER2NN, + PMXVBF16GER2NP, + PMXVBF16GER2PN, + PMXVBF16GER2PP, + PMXVBF16GER2W, + PMXVBF16GER2WNN, + PMXVBF16GER2WNP, + PMXVBF16GER2WPN, + PMXVBF16GER2WPP, + PMXVF16GER2, + PMXVF16GER2NN, + PMXVF16GER2NP, + PMXVF16GER2PN, + PMXVF16GER2PP, + PMXVF16GER2W, + PMXVF16GER2WNN, + PMXVF16GER2WNP, + PMXVF16GER2WPN, + PMXVF16GER2WPP, + PMXVF32GER, + PMXVF32GERNN, + PMXVF32GERNP, + PMXVF32GERPN, + PMXVF32GERPP, + PMXVF32GERW, + PMXVF32GERWNN, + PMXVF32GERWNP, + PMXVF32GERWPN, + PMXVF32GERWPP, + PMXVF64GER, + PMXVF64GERNN, + PMXVF64GERNP, + PMXVF64GERPN, + PMXVF64GERPP, + PMXVF64GERW, + PMXVF64GERWNN, + PMXVF64GERWNP, + PMXVF64GERWPN, + PMXVF64GERWPP, + PMXVI16GER2, + PMXVI16GER2PP, + PMXVI16GER2S, + PMXVI16GER2SPP, + PMXVI16GER2SW, + PMXVI16GER2SWPP, + PMXVI16GER2W, + PMXVI16GER2WPP, + PMXVI4GER8, + PMXVI4GER8PP, + PMXVI4GER8W, + PMXVI4GER8WPP, + PMXVI8GER4, + PMXVI8GER4PP, + PMXVI8GER4SPP, + PMXVI8GER4W, + PMXVI8GER4WPP, + PMXVI8GER4WSPP, + POPCNTB, + POPCNTB8, + POPCNTD, + POPCNTW, + PPC32GOT, + PPC32PICGOT, + PREPARE_PROBED_ALLOCA_32, + PREPARE_PROBED_ALLOCA_64, + PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32, + PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64, + PROBED_ALLOCA_32, + PROBED_ALLOCA_64, + PROBED_STACKALLOC_32, + PROBED_STACKALLOC_64, + PSTB, + PSTB8, + PSTB8nopc, + PSTB8onlypc, + PSTB8pc, + PSTBnopc, + PSTBonlypc, + PSTBpc, + PSTD, + PSTDnopc, + PSTDonlypc, + PSTDpc, + PSTFD, + PSTFDnopc, + PSTFDonlypc, + PSTFDpc, + PSTFS, + PSTFSnopc, + PSTFSonlypc, + PSTFSpc, + PSTH, + PSTH8, + PSTH8nopc, + PSTH8onlypc, + PSTH8pc, + PSTHnopc, + PSTHonlypc, + PSTHpc, + PSTW, + PSTW8, + PSTW8nopc, + PSTW8onlypc, + PSTW8pc, + PSTWnopc, + PSTWonlypc, + PSTWpc, + PSTXSD, + PSTXSDnopc, + PSTXSDonlypc, + PSTXSDpc, + PSTXSSP, + PSTXSSPnopc, + PSTXSSPonlypc, + PSTXSSPpc, + PSTXV, + PSTXVP, + PSTXVPnopc, + PSTXVPonlypc, + PSTXVPpc, + PSTXVnopc, + PSTXVonlypc, + PSTXVpc, + PTESYNCIO, + PseudoEIEIO, + RESTORE_ACC, + RESTORE_CR, + RESTORE_CRBIT, + RESTORE_DMR, + RESTORE_DMRP, + RESTORE_QUADWORD, + RESTORE_UACC, + RESTORE_WACC, + RFCI, + RFDI, + RFEBB, + RFI, + RFID, + RFMCI, + RLDCL, + RLDCL_rec, + RLDCR, + RLDCR_rec, + RLDIC, + RLDICL, + RLDICL_32, + RLDICL_32_64, + RLDICL_32_rec, + RLDICL_rec, + RLDICR, + RLDICR_32, + RLDICR_rec, + RLDIC_rec, + RLDIMI, + RLDIMI_rec, + RLWIMI, + RLWIMI8, + RLWIMI8_rec, + RLWIMI_rec, + RLWINM, + RLWINM8, + RLWINM8_rec, + RLWINM_rec, + RLWNM, + RLWNM8, + RLWNM8_rec, + RLWNM_rec, + ReadTB, + SC, + SCV, + SELECT_CC_F16, + SELECT_CC_F4, + SELECT_CC_F8, + SELECT_CC_I4, + SELECT_CC_I8, + SELECT_CC_SPE, + SELECT_CC_SPE4, + SELECT_CC_VRRC, + SELECT_CC_VSFRC, + SELECT_CC_VSRC, + SELECT_CC_VSSRC, + SELECT_F16, + SELECT_F4, + SELECT_F8, + SELECT_I4, + SELECT_I8, + SELECT_SPE, + SELECT_SPE4, + SELECT_VRRC, + SELECT_VSFRC, + SELECT_VSRC, + SELECT_VSSRC, + SETB, + SETB8, + SETBC, + SETBC8, + SETBCR, + SETBCR8, + SETFLM, + SETNBC, + SETNBC8, + SETNBCR, + SETNBCR8, + SETRND, + SETRNDi, + SLBFEE_rec, + SLBIA, + SLBIE, + SLBIEG, + SLBMFEE, + SLBMFEV, + SLBMTE, + SLBSYNC, + SLD, + SLD_rec, + SLW, + SLW8, + SLW8_rec, + SLW_rec, + SPELWZ, + SPELWZX, + SPESTW, + SPESTWX, + SPILL_ACC, + SPILL_CR, + SPILL_CRBIT, + SPILL_DMR, + SPILL_DMRP, + SPILL_QUADWORD, + SPILL_UACC, + SPILL_WACC, + SPLIT_QUADWORD, + SRAD, + SRADI, + SRADI_32, + SRADI_rec, + SRAD_rec, + SRAW, + SRAW8, + SRAW8_rec, + SRAWI, + SRAWI8, + SRAWI8_rec, + SRAWI_rec, + SRAW_rec, + SRD, + SRD_rec, + SRW, + SRW8, + SRW8_rec, + SRW_rec, + STB, + STB8, + STBCIX, + STBCX, + STBEPX, + STBU, + STBU8, + STBUX, + STBUX8, + STBX, + STBX8, + STBXTLS, + STBXTLS_, + STBXTLS_32, + STD, + STDAT, + STDBRX, + STDCIX, + STDCX, + STDU, + STDUX, + STDX, + STDXTLS, + STDXTLS_, + STFD, + STFDEPX, + STFDU, + STFDUX, + STFDX, + STFDXTLS, + STFDXTLS_, + STFIWX, + STFS, + STFSU, + STFSUX, + STFSX, + STFSXTLS, + STFSXTLS_, + STH, + STH8, + STHBRX, + STHCIX, + STHCX, + STHEPX, + STHU, + STHU8, + STHUX, + STHUX8, + STHX, + STHX8, + STHXTLS, + STHXTLS_, + STHXTLS_32, + STMW, + STOP, + STQ, + STQCX, + STQX_PSEUDO, + STSWI, + STVEBX, + STVEHX, + STVEWX, + STVX, + STVXL, + STW, + STW8, + STWAT, + STWBRX, + STWCIX, + STWCX, + STWEPX, + STWU, + STWU8, + STWUX, + STWUX8, + STWX, + STWX8, + STWXTLS, + STWXTLS_, + STWXTLS_32, + STXSD, + STXSDX, + STXSIBX, + STXSIBXv, + STXSIHX, + STXSIHXv, + STXSIWX, + STXSSP, + STXSSPX, + STXV, + STXVB16X, + STXVD2X, + STXVH8X, + STXVL, + STXVLL, + STXVP, + STXVPB32X, + STXVPRL, + STXVPRLL, + STXVPX, + STXVRBX, + STXVRDX, + STXVRHX, + STXVRL, + STXVRLL, + STXVRWX, + STXVW4X, + STXVX, + SUBF, + SUBF8, + SUBF8O, + SUBF8O_rec, + SUBF8_rec, + SUBFC, + SUBFC8, + SUBFC8O, + SUBFC8O_rec, + SUBFC8_rec, + SUBFCO, + SUBFCO_rec, + SUBFC_rec, + SUBFE, + SUBFE8, + SUBFE8O, + SUBFE8O_rec, + SUBFE8_rec, + SUBFEO, + SUBFEO_rec, + SUBFE_rec, + SUBFIC, + SUBFIC8, + SUBFME, + SUBFME8, + SUBFME8O, + SUBFME8O_rec, + SUBFME8_rec, + SUBFMEO, + SUBFMEO_rec, + SUBFME_rec, + SUBFO, + SUBFO_rec, + SUBFUS, + SUBFUS_rec, + SUBFZE, + SUBFZE8, + SUBFZE8O, + SUBFZE8O_rec, + SUBFZE8_rec, + SUBFZEO, + SUBFZEO_rec, + SUBFZE_rec, + SUBF_rec, + SYNC, + SYNCP10, + TABORT, + TABORTDC, + TABORTDCI, + TABORTWC, + TABORTWCI, + TAILB, + TAILB8, + TAILBA, + TAILBA8, + TAILBCTR, + TAILBCTR8, + TBEGIN, + TBEGIN_RET, + TCHECK, + TCHECK_RET, + TCRETURNai, + TCRETURNai8, + TCRETURNdi, + TCRETURNdi8, + TCRETURNri, + TCRETURNri8, + TD, + TDI, + TEND, + TLBIA, + TLBIE, + TLBIE8P9, + TLBIEIO, + TLBIEL, + TLBIEP, + TLBIEP8, + TLBIEP9, + TLBILX, + TLBIVAX, + TLBLD, + TLBLI, + TLBRE, + TLBRE2, + TLBSX, + TLBSX2, + TLBSX2D, + TLBSYNC, + TLBSYNCIO, + TLBWE, + TLBWE2, + TLSGDAIX, + TLSGDAIX8, + TLSLDAIX, + TLSLDAIX8, + TRAP, + TRECHKPT, + TRECLAIM, + TSR, + TW, + TWI, + UNENCODED_NOP, + UpdateGBR, + VABSDUB, + VABSDUH, + VABSDUW, + VADDCUQ, + VADDCUW, + VADDECUQ, + VADDEUQM, + VADDFP, + VADDSBS, + VADDSHS, + VADDSWS, + VADDUBM, + VADDUBS, + VADDUDM, + VADDUHM, + VADDUHS, + VADDUQM, + VADDUWM, + VADDUWS, + VAND, + VANDC, + VAVGSB, + VAVGSH, + VAVGSW, + VAVGUB, + VAVGUH, + VAVGUW, + VBPERMD, + VBPERMQ, + VCFSX, + VCFSX_0, + VCFUGED, + VCFUX, + VCFUX_0, + VCIPHER, + VCIPHERLAST, + VCLRLB, + VCLRRB, + VCLZB, + VCLZD, + VCLZDM, + VCLZH, + VCLZLSBB, + VCLZW, + VCMPBFP, + VCMPBFP_rec, + VCMPEQFP, + VCMPEQFP_rec, + VCMPEQUB, + VCMPEQUB_rec, + VCMPEQUD, + VCMPEQUD_rec, + VCMPEQUH, + VCMPEQUH_rec, + VCMPEQUQ, + VCMPEQUQ_rec, + VCMPEQUW, + VCMPEQUW_rec, + VCMPGEFP, + VCMPGEFP_rec, + VCMPGTFP, + VCMPGTFP_rec, + VCMPGTSB, + VCMPGTSB_rec, + VCMPGTSD, + VCMPGTSD_rec, + VCMPGTSH, + VCMPGTSH_rec, + VCMPGTSQ, + VCMPGTSQ_rec, + VCMPGTSW, + VCMPGTSW_rec, + VCMPGTUB, + VCMPGTUB_rec, + VCMPGTUD, + VCMPGTUD_rec, + VCMPGTUH, + VCMPGTUH_rec, + VCMPGTUQ, + VCMPGTUQ_rec, + VCMPGTUW, + VCMPGTUW_rec, + VCMPNEB, + VCMPNEB_rec, + VCMPNEH, + VCMPNEH_rec, + VCMPNEW, + VCMPNEW_rec, + VCMPNEZB, + VCMPNEZB_rec, + VCMPNEZH, + VCMPNEZH_rec, + VCMPNEZW, + VCMPNEZW_rec, + VCMPSQ, + VCMPUQ, + VCNTMBB, + VCNTMBD, + VCNTMBH, + VCNTMBW, + VCTSXS, + VCTSXS_0, + VCTUXS, + VCTUXS_0, + VCTZB, + VCTZD, + VCTZDM, + VCTZH, + VCTZLSBB, + VCTZW, + VDIVESD, + VDIVESQ, + VDIVESW, + VDIVEUD, + VDIVEUQ, + VDIVEUW, + VDIVSD, + VDIVSQ, + VDIVSW, + VDIVUD, + VDIVUQ, + VDIVUW, + VEQV, + VEXPANDBM, + VEXPANDDM, + VEXPANDHM, + VEXPANDQM, + VEXPANDWM, + VEXPTEFP, + VEXTDDVLX, + VEXTDDVRX, + VEXTDUBVLX, + VEXTDUBVRX, + VEXTDUHVLX, + VEXTDUHVRX, + VEXTDUWVLX, + VEXTDUWVRX, + VEXTRACTBM, + VEXTRACTD, + VEXTRACTDM, + VEXTRACTHM, + VEXTRACTQM, + VEXTRACTUB, + VEXTRACTUH, + VEXTRACTUW, + VEXTRACTWM, + VEXTSB2D, + VEXTSB2Ds, + VEXTSB2W, + VEXTSB2Ws, + VEXTSD2Q, + VEXTSH2D, + VEXTSH2Ds, + VEXTSH2W, + VEXTSH2Ws, + VEXTSW2D, + VEXTSW2Ds, + VEXTUBLX, + VEXTUBRX, + VEXTUHLX, + VEXTUHRX, + VEXTUWLX, + VEXTUWRX, + VGBBD, + VGNB, + VINSBLX, + VINSBRX, + VINSBVLX, + VINSBVRX, + VINSD, + VINSDLX, + VINSDRX, + VINSERTB, + VINSERTD, + VINSERTH, + VINSERTW, + VINSHLX, + VINSHRX, + VINSHVLX, + VINSHVRX, + VINSW, + VINSWLX, + VINSWRX, + VINSWVLX, + VINSWVRX, + VLOGEFP, + VMADDFP, + VMAXFP, + VMAXSB, + VMAXSD, + VMAXSH, + VMAXSW, + VMAXUB, + VMAXUD, + VMAXUH, + VMAXUW, + VMHADDSHS, + VMHRADDSHS, + VMINFP, + VMINSB, + VMINSD, + VMINSH, + VMINSW, + VMINUB, + VMINUD, + VMINUH, + VMINUW, + VMLADDUHM, + VMODSD, + VMODSQ, + VMODSW, + VMODUD, + VMODUQ, + VMODUW, + VMRGEW, + VMRGHB, + VMRGHH, + VMRGHW, + VMRGLB, + VMRGLH, + VMRGLW, + VMRGOW, + VMSUMCUD, + VMSUMMBM, + VMSUMSHM, + VMSUMSHS, + VMSUMUBM, + VMSUMUDM, + VMSUMUHM, + VMSUMUHS, + VMUL10CUQ, + VMUL10ECUQ, + VMUL10EUQ, + VMUL10UQ, + VMULESB, + VMULESD, + VMULESH, + VMULESW, + VMULEUB, + VMULEUD, + VMULEUH, + VMULEUW, + VMULHSD, + VMULHSW, + VMULHUD, + VMULHUW, + VMULLD, + VMULOSB, + VMULOSD, + VMULOSH, + VMULOSW, + VMULOUB, + VMULOUD, + VMULOUH, + VMULOUW, + VMULUWM, + VNAND, + VNCIPHER, + VNCIPHERLAST, + VNEGD, + VNEGW, + VNMSUBFP, + VNOR, + VOR, + VORC, + VPDEPD, + VPERM, + VPERMR, + VPERMXOR, + VPEXTD, + VPKPX, + VPKSDSS, + VPKSDUS, + VPKSHSS, + VPKSHUS, + VPKSWSS, + VPKSWUS, + VPKUDUM, + VPKUDUS, + VPKUHUM, + VPKUHUS, + VPKUWUM, + VPKUWUS, + VPMSUMB, + VPMSUMD, + VPMSUMH, + VPMSUMW, + VPOPCNTB, + VPOPCNTD, + VPOPCNTH, + VPOPCNTW, + VPRTYBD, + VPRTYBQ, + VPRTYBW, + VREFP, + VRFIM, + VRFIN, + VRFIP, + VRFIZ, + VRLB, + VRLD, + VRLDMI, + VRLDNM, + VRLH, + VRLQ, + VRLQMI, + VRLQNM, + VRLW, + VRLWMI, + VRLWNM, + VRSQRTEFP, + VSBOX, + VSEL, + VSHASIGMAD, + VSHASIGMAW, + VSL, + VSLB, + VSLD, + VSLDBI, + VSLDOI, + VSLH, + VSLO, + VSLQ, + VSLV, + VSLW, + VSPLTB, + VSPLTBs, + VSPLTH, + VSPLTHs, + VSPLTISB, + VSPLTISH, + VSPLTISW, + VSPLTW, + VSR, + VSRAB, + VSRAD, + VSRAH, + VSRAQ, + VSRAW, + VSRB, + VSRD, + VSRDBI, + VSRH, + VSRO, + VSRQ, + VSRV, + VSRW, + VSTRIBL, + VSTRIBL_rec, + VSTRIBR, + VSTRIBR_rec, + VSTRIHL, + VSTRIHL_rec, + VSTRIHR, + VSTRIHR_rec, + VSUBCUQ, + VSUBCUW, + VSUBECUQ, + VSUBEUQM, + VSUBFP, + VSUBSBS, + VSUBSHS, + VSUBSWS, + VSUBUBM, + VSUBUBS, + VSUBUDM, + VSUBUHM, + VSUBUHS, + VSUBUQM, + VSUBUWM, + VSUBUWS, + VSUM2SWS, + VSUM4SBS, + VSUM4SHS, + VSUM4UBS, + VSUMSWS, + VUCMPRHB, + VUCMPRHH, + VUCMPRHN, + VUCMPRLB, + VUCMPRLH, + VUCMPRLN, + VUPKHPX, + VUPKHSB, + VUPKHSH, + VUPKHSNTOB, + VUPKHSW, + VUPKINT4TOBF16, + VUPKINT4TOFP32, + VUPKINT8TOBF16, + VUPKINT8TOFP32, + VUPKLPX, + VUPKLSB, + VUPKLSH, + VUPKLSNTOB, + VUPKLSW, + VXOR, + V_SET0, + V_SET0B, + V_SET0H, + V_SETALLONES, + V_SETALLONESB, + V_SETALLONESH, + WAIT, + WAITP10, + WRTEE, + WRTEEI, + XOR, + XOR8, + XOR8_rec, + XORI, + XORI8, + XORIS, + XORIS8, + XOR_rec, + XSABSDP, + XSABSQP, + XSADDADDSUQM, + XSADDADDUQM, + XSADDDP, + XSADDQP, + XSADDQPO, + XSADDSP, + XSADDSUBSUQM, + XSADDSUBUQM, + XSCMPEQDP, + XSCMPEQQP, + XSCMPEXPDP, + XSCMPEXPQP, + XSCMPGEDP, + XSCMPGEQP, + XSCMPGTDP, + XSCMPGTQP, + XSCMPODP, + XSCMPOQP, + XSCMPUDP, + XSCMPUQP, + XSCPSGNDP, + XSCPSGNQP, + XSCVDPHP, + XSCVDPQP, + XSCVDPSP, + XSCVDPSPN, + XSCVDPSXDS, + XSCVDPSXDSs, + XSCVDPSXWS, + XSCVDPSXWSs, + XSCVDPUXDS, + XSCVDPUXDSs, + XSCVDPUXWS, + XSCVDPUXWSs, + XSCVHPDP, + XSCVQPDP, + XSCVQPDPO, + XSCVQPSDZ, + XSCVQPSQZ, + XSCVQPSWZ, + XSCVQPUDZ, + XSCVQPUQZ, + XSCVQPUWZ, + XSCVSDQP, + XSCVSPDP, + XSCVSPDPN, + XSCVSQQP, + XSCVSXDDP, + XSCVSXDSP, + XSCVUDQP, + XSCVUQQP, + XSCVUXDDP, + XSCVUXDSP, + XSDIVDP, + XSDIVQP, + XSDIVQPO, + XSDIVSP, + XSIEXPDP, + XSIEXPQP, + XSMADDADP, + XSMADDASP, + XSMADDMDP, + XSMADDMSP, + XSMADDQP, + XSMADDQPO, + XSMAXCDP, + XSMAXCQP, + XSMAXDP, + XSMAXJDP, + XSMERGE2T1UQM, + XSMERGE2T2UQM, + XSMERGE2T3UQM, + XSMERGE3T1UQM, + XSMINCDP, + XSMINCQP, + XSMINDP, + XSMINJDP, + XSMSUBADP, + XSMSUBASP, + XSMSUBMDP, + XSMSUBMSP, + XSMSUBQP, + XSMSUBQPO, + XSMULDP, + XSMULQP, + XSMULQPO, + XSMULSP, + XSNABSDP, + XSNABSDPs, + XSNABSQP, + XSNEGDP, + XSNEGQP, + XSNMADDADP, + XSNMADDASP, + XSNMADDMDP, + XSNMADDMSP, + XSNMADDQP, + XSNMADDQPO, + XSNMSUBADP, + XSNMSUBASP, + XSNMSUBMDP, + XSNMSUBMSP, + XSNMSUBQP, + XSNMSUBQPO, + XSRDPI, + XSRDPIC, + XSRDPIM, + XSRDPIP, + XSRDPIZ, + XSREBASE2T1UQM, + XSREBASE2T2UQM, + XSREBASE2T3UQM, + XSREBASE2T4UQM, + XSREBASE3T1UQM, + XSREBASE3T2UQM, + XSREBASE3T3UQM, + XSREDP, + XSRESP, + XSRQPI, + XSRQPIX, + XSRQPXP, + XSRSP, + XSRSQRTEDP, + XSRSQRTESP, + XSSQRTDP, + XSSQRTQP, + XSSQRTQPO, + XSSQRTSP, + XSSUBDP, + XSSUBQP, + XSSUBQPO, + XSSUBSP, + XSTDIVDP, + XSTSQRTDP, + XSTSTDCDP, + XSTSTDCQP, + XSTSTDCSP, + XSXEXPDP, + XSXEXPQP, + XSXSIGDP, + XSXSIGQP, + XVABSDP, + XVABSSP, + XVADDDP, + XVADDSP, + XVADDUHM, + XVADDUWM, + XVBF16GER2, + XVBF16GER2NN, + XVBF16GER2NP, + XVBF16GER2PN, + XVBF16GER2PP, + XVBF16GER2W, + XVBF16GER2WNN, + XVBF16GER2WNP, + XVBF16GER2WPN, + XVBF16GER2WPP, + XVCMPEQDP, + XVCMPEQDP_rec, + XVCMPEQSP, + XVCMPEQSP_rec, + XVCMPGEDP, + XVCMPGEDP_rec, + XVCMPGESP, + XVCMPGESP_rec, + XVCMPGTDP, + XVCMPGTDP_rec, + XVCMPGTSP, + XVCMPGTSP_rec, + XVCPSGNDP, + XVCPSGNSP, + XVCVBF16SPN, + XVCVDPSP, + XVCVDPSXDS, + XVCVDPSXWS, + XVCVDPUXDS, + XVCVDPUXWS, + XVCVHPSP, + XVCVSPBF16, + XVCVSPDP, + XVCVSPHP, + XVCVSPSXDS, + XVCVSPSXWS, + XVCVSPUXDS, + XVCVSPUXWS, + XVCVSXDDP, + XVCVSXDSP, + XVCVSXWDP, + XVCVSXWSP, + XVCVUXDDP, + XVCVUXDSP, + XVCVUXWDP, + XVCVUXWSP, + XVDIVDP, + XVDIVSP, + XVF16GER2, + XVF16GER2NN, + XVF16GER2NP, + XVF16GER2PN, + XVF16GER2PP, + XVF16GER2W, + XVF16GER2WNN, + XVF16GER2WNP, + XVF16GER2WPN, + XVF16GER2WPP, + XVF32GER, + XVF32GERNN, + XVF32GERNP, + XVF32GERPN, + XVF32GERPP, + XVF32GERW, + XVF32GERWNN, + XVF32GERWNP, + XVF32GERWPN, + XVF32GERWPP, + XVF64GER, + XVF64GERNN, + XVF64GERNP, + XVF64GERPN, + XVF64GERPP, + XVF64GERW, + XVF64GERWNN, + XVF64GERWNP, + XVF64GERWPN, + XVF64GERWPP, + XVI16GER2, + XVI16GER2PP, + XVI16GER2S, + XVI16GER2SPP, + XVI16GER2SW, + XVI16GER2SWPP, + XVI16GER2W, + XVI16GER2WPP, + XVI4GER8, + XVI4GER8PP, + XVI4GER8W, + XVI4GER8WPP, + XVI8GER4, + XVI8GER4PP, + XVI8GER4SPP, + XVI8GER4W, + XVI8GER4WPP, + XVI8GER4WSPP, + XVIEXPDP, + XVIEXPSP, + XVMADDADP, + XVMADDASP, + XVMADDMDP, + XVMADDMSP, + XVMAXDP, + XVMAXSP, + XVMINDP, + XVMINSP, + XVMSUBADP, + XVMSUBASP, + XVMSUBMDP, + XVMSUBMSP, + XVMULDP, + XVMULHSH, + XVMULHSW, + XVMULHUH, + XVMULHUW, + XVMULSP, + XVMULUHM, + XVMULUWM, + XVNABSDP, + XVNABSSP, + XVNEGDP, + XVNEGSP, + XVNMADDADP, + XVNMADDASP, + XVNMADDMDP, + XVNMADDMSP, + XVNMSUBADP, + XVNMSUBASP, + XVNMSUBMDP, + XVNMSUBMSP, + XVRDPI, + XVRDPIC, + XVRDPIM, + XVRDPIP, + XVRDPIZ, + XVREDP, + XVRESP, + XVRLW, + XVRSPI, + XVRSPIC, + XVRSPIM, + XVRSPIP, + XVRSPIZ, + XVRSQRTEDP, + XVRSQRTESP, + XVSQRTDP, + XVSQRTSP, + XVSUBDP, + XVSUBSP, + XVSUBUHM, + XVSUBUWM, + XVTDIVDP, + XVTDIVSP, + XVTLSBB, + XVTSQRTDP, + XVTSQRTSP, + XVTSTDCDP, + XVTSTDCSP, + XVXEXPDP, + XVXEXPSP, + XVXSIGDP, + XVXSIGSP, + XXAESDECP, + XXAESENCP, + XXAESGENLKP, + XXBLENDVB, + XXBLENDVD, + XXBLENDVH, + XXBLENDVW, + XXBRD, + XXBRH, + XXBRQ, + XXBRW, + XXEVAL, + XXEXTRACTUW, + XXGENPCVBM, + XXGENPCVDM, + XXGENPCVHM, + XXGENPCVWM, + XXGFMUL128, + XXINSERTW, + XXLAND, + XXLANDC, + XXLEQV, + XXLEQVOnes, + XXLNAND, + XXLNOR, + XXLOR, + XXLORC, + XXLORf, + XXLXOR, + XXLXORdpz, + XXLXORspz, + XXLXORz, + XXMFACC, + XXMFACCW, + XXMRGHW, + XXMRGLW, + XXMTACC, + XXMTACCW, + XXMULMUL, + XXMULMULHIADD, + XXMULMULLOADD, + XXPERM, + XXPERMDI, + XXPERMDIs, + XXPERMR, + XXPERMX, + XXSEL, + XXSETACCZ, + XXSLDWI, + XXSLDWIs, + XXSPLTI32DX, + XXSPLTIB, + XXSPLTIDP, + XXSPLTIW, + XXSPLTW, + XXSPLTWs, + XXSSUMUDM, + XXSSUMUDMC, + XXSSUMUDMCEXT, + gBC, + gBCA, + gBCAat, + gBCCTR, + gBCCTRL, + gBCL, + gBCLA, + gBCLAat, + gBCLR, + gBCLRL, + gBCLat, + gBCat, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ATOMIC_CMP_SWAP_I128, + 323 => Opcode::ATOMIC_LOAD_ADD_I128, + 324 => Opcode::ATOMIC_LOAD_AND_I128, + 325 => Opcode::ATOMIC_LOAD_NAND_I128, + 326 => Opcode::ATOMIC_LOAD_OR_I128, + 327 => Opcode::ATOMIC_LOAD_SUB_I128, + 328 => Opcode::ATOMIC_LOAD_XOR_I128, + 329 => Opcode::ATOMIC_SWAP_I128, + 330 => Opcode::BUILD_QUADWORD, + 331 => Opcode::BUILD_UACC, + 332 => Opcode::CFENCE, + 333 => Opcode::CFENCE8, + 334 => Opcode::CLRLSLDI, + 335 => Opcode::CLRLSLDI_rec, + 336 => Opcode::CLRLSLWI, + 337 => Opcode::CLRLSLWI_rec, + 338 => Opcode::CLRRDI, + 339 => Opcode::CLRRDI_rec, + 340 => Opcode::CLRRWI, + 341 => Opcode::CLRRWI_rec, + 342 => Opcode::DCBFL, + 343 => Opcode::DCBFLP, + 344 => Opcode::DCBFPS, + 345 => Opcode::DCBFx, + 346 => Opcode::DCBSTPS, + 347 => Opcode::DCBTCT, + 348 => Opcode::DCBTDS, + 349 => Opcode::DCBTSTCT, + 350 => Opcode::DCBTSTDS, + 351 => Opcode::DCBTSTT, + 352 => Opcode::DCBTSTx, + 353 => Opcode::DCBTT, + 354 => Opcode::DCBTx, + 355 => Opcode::DFLOADf32, + 356 => Opcode::DFLOADf64, + 357 => Opcode::DFSTOREf32, + 358 => Opcode::DFSTOREf64, + 359 => Opcode::EXTLDI, + 360 => Opcode::EXTLDI_rec, + 361 => Opcode::EXTLWI, + 362 => Opcode::EXTLWI_rec, + 363 => Opcode::EXTRDI, + 364 => Opcode::EXTRDI_rec, + 365 => Opcode::EXTRWI, + 366 => Opcode::EXTRWI_rec, + 367 => Opcode::INSLWI, + 368 => Opcode::INSLWI_rec, + 369 => Opcode::INSRDI, + 370 => Opcode::INSRDI_rec, + 371 => Opcode::INSRWI, + 372 => Opcode::INSRWI_rec, + 373 => Opcode::KILL_PAIR, + 374 => Opcode::LAx, + 375 => Opcode::LIWAX, + 376 => Opcode::LIWZX, + 377 => Opcode::PPCLdFixedAddr, + 378 => Opcode::PSUBI, + 379 => Opcode::RLWIMIbm, + 380 => Opcode::RLWIMIbm_rec, + 381 => Opcode::RLWINMbm, + 382 => Opcode::RLWINMbm_rec, + 383 => Opcode::RLWNMbm, + 384 => Opcode::RLWNMbm_rec, + 385 => Opcode::ROTRDI, + 386 => Opcode::ROTRDI_rec, + 387 => Opcode::ROTRWI, + 388 => Opcode::ROTRWI_rec, + 389 => Opcode::SLDI, + 390 => Opcode::SLDI_rec, + 391 => Opcode::SLWI, + 392 => Opcode::SLWI_rec, + 393 => Opcode::SPILLTOVSR_LD, + 394 => Opcode::SPILLTOVSR_LDX, + 395 => Opcode::SPILLTOVSR_ST, + 396 => Opcode::SPILLTOVSR_STX, + 397 => Opcode::SRDI, + 398 => Opcode::SRDI_rec, + 399 => Opcode::SRWI, + 400 => Opcode::SRWI_rec, + 401 => Opcode::STIWX, + 402 => Opcode::SUBI, + 403 => Opcode::SUBIC, + 404 => Opcode::SUBIC_rec, + 405 => Opcode::SUBIS, + 406 => Opcode::SUBPCIS, + 407 => Opcode::XFLOADf32, + 408 => Opcode::XFLOADf64, + 409 => Opcode::XFSTOREf32, + 410 => Opcode::XFSTOREf64, + 411 => Opcode::ADD4, + 412 => Opcode::ADD4O, + 413 => Opcode::ADD4O_rec, + 414 => Opcode::ADD4TLS, + 415 => Opcode::ADD4_rec, + 416 => Opcode::ADD8, + 417 => Opcode::ADD8O, + 418 => Opcode::ADD8O_rec, + 419 => Opcode::ADD8TLS, + 420 => Opcode::ADD8TLS_, + 421 => Opcode::ADD8_rec, + 422 => Opcode::ADDC, + 423 => Opcode::ADDC8, + 424 => Opcode::ADDC8O, + 425 => Opcode::ADDC8O_rec, + 426 => Opcode::ADDC8_rec, + 427 => Opcode::ADDCO, + 428 => Opcode::ADDCO_rec, + 429 => Opcode::ADDC_rec, + 430 => Opcode::ADDE, + 431 => Opcode::ADDE8, + 432 => Opcode::ADDE8O, + 433 => Opcode::ADDE8O_rec, + 434 => Opcode::ADDE8_rec, + 435 => Opcode::ADDEO, + 436 => Opcode::ADDEO_rec, + 437 => Opcode::ADDEX, + 438 => Opcode::ADDEX8, + 439 => Opcode::ADDE_rec, + 440 => Opcode::ADDG6S, + 441 => Opcode::ADDG6S8, + 442 => Opcode::ADDI, + 443 => Opcode::ADDI8, + 444 => Opcode::ADDIC, + 445 => Opcode::ADDIC8, + 446 => Opcode::ADDIC_rec, + 447 => Opcode::ADDIS, + 448 => Opcode::ADDIS8, + 449 => Opcode::ADDISdtprelHA, + 450 => Opcode::ADDISdtprelHA32, + 451 => Opcode::ADDISgotTprelHA, + 452 => Opcode::ADDIStlsgdHA, + 453 => Opcode::ADDIStlsldHA, + 454 => Opcode::ADDIStocHA, + 455 => Opcode::ADDIStocHA8, + 456 => Opcode::ADDIdtprelL, + 457 => Opcode::ADDIdtprelL32, + 458 => Opcode::ADDItlsgdL, + 459 => Opcode::ADDItlsgdL32, + 460 => Opcode::ADDItlsgdLADDR, + 461 => Opcode::ADDItlsgdLADDR32, + 462 => Opcode::ADDItlsldL, + 463 => Opcode::ADDItlsldL32, + 464 => Opcode::ADDItlsldLADDR, + 465 => Opcode::ADDItlsldLADDR32, + 466 => Opcode::ADDItoc, + 467 => Opcode::ADDItoc8, + 468 => Opcode::ADDItocL, + 469 => Opcode::ADDItocL8, + 470 => Opcode::ADDME, + 471 => Opcode::ADDME8, + 472 => Opcode::ADDME8O, + 473 => Opcode::ADDME8O_rec, + 474 => Opcode::ADDME8_rec, + 475 => Opcode::ADDMEO, + 476 => Opcode::ADDMEO_rec, + 477 => Opcode::ADDME_rec, + 478 => Opcode::ADDPCIS, + 479 => Opcode::ADDZE, + 480 => Opcode::ADDZE8, + 481 => Opcode::ADDZE8O, + 482 => Opcode::ADDZE8O_rec, + 483 => Opcode::ADDZE8_rec, + 484 => Opcode::ADDZEO, + 485 => Opcode::ADDZEO_rec, + 486 => Opcode::ADDZE_rec, + 487 => Opcode::ADJCALLSTACKDOWN, + 488 => Opcode::ADJCALLSTACKUP, + 489 => Opcode::AND, + 490 => Opcode::AND8, + 491 => Opcode::AND8_rec, + 492 => Opcode::ANDC, + 493 => Opcode::ANDC8, + 494 => Opcode::ANDC8_rec, + 495 => Opcode::ANDC_rec, + 496 => Opcode::ANDI8_rec, + 497 => Opcode::ANDIS8_rec, + 498 => Opcode::ANDIS_rec, + 499 => Opcode::ANDI_rec, + 500 => Opcode::ANDI_rec_1_EQ_BIT, + 501 => Opcode::ANDI_rec_1_EQ_BIT8, + 502 => Opcode::ANDI_rec_1_GT_BIT, + 503 => Opcode::ANDI_rec_1_GT_BIT8, + 504 => Opcode::AND_rec, + 505 => Opcode::ATOMIC_CMP_SWAP_I16, + 506 => Opcode::ATOMIC_CMP_SWAP_I32, + 507 => Opcode::ATOMIC_CMP_SWAP_I64, + 508 => Opcode::ATOMIC_CMP_SWAP_I8, + 509 => Opcode::ATOMIC_LOAD_ADD_I16, + 510 => Opcode::ATOMIC_LOAD_ADD_I32, + 511 => Opcode::ATOMIC_LOAD_ADD_I64, + 512 => Opcode::ATOMIC_LOAD_ADD_I8, + 513 => Opcode::ATOMIC_LOAD_AND_I16, + 514 => Opcode::ATOMIC_LOAD_AND_I32, + 515 => Opcode::ATOMIC_LOAD_AND_I64, + 516 => Opcode::ATOMIC_LOAD_AND_I8, + 517 => Opcode::ATOMIC_LOAD_MAX_I16, + 518 => Opcode::ATOMIC_LOAD_MAX_I32, + 519 => Opcode::ATOMIC_LOAD_MAX_I64, + 520 => Opcode::ATOMIC_LOAD_MAX_I8, + 521 => Opcode::ATOMIC_LOAD_MIN_I16, + 522 => Opcode::ATOMIC_LOAD_MIN_I32, + 523 => Opcode::ATOMIC_LOAD_MIN_I64, + 524 => Opcode::ATOMIC_LOAD_MIN_I8, + 525 => Opcode::ATOMIC_LOAD_NAND_I16, + 526 => Opcode::ATOMIC_LOAD_NAND_I32, + 527 => Opcode::ATOMIC_LOAD_NAND_I64, + 528 => Opcode::ATOMIC_LOAD_NAND_I8, + 529 => Opcode::ATOMIC_LOAD_OR_I16, + 530 => Opcode::ATOMIC_LOAD_OR_I32, + 531 => Opcode::ATOMIC_LOAD_OR_I64, + 532 => Opcode::ATOMIC_LOAD_OR_I8, + 533 => Opcode::ATOMIC_LOAD_SUB_I16, + 534 => Opcode::ATOMIC_LOAD_SUB_I32, + 535 => Opcode::ATOMIC_LOAD_SUB_I64, + 536 => Opcode::ATOMIC_LOAD_SUB_I8, + 537 => Opcode::ATOMIC_LOAD_UMAX_I16, + 538 => Opcode::ATOMIC_LOAD_UMAX_I32, + 539 => Opcode::ATOMIC_LOAD_UMAX_I64, + 540 => Opcode::ATOMIC_LOAD_UMAX_I8, + 541 => Opcode::ATOMIC_LOAD_UMIN_I16, + 542 => Opcode::ATOMIC_LOAD_UMIN_I32, + 543 => Opcode::ATOMIC_LOAD_UMIN_I64, + 544 => Opcode::ATOMIC_LOAD_UMIN_I8, + 545 => Opcode::ATOMIC_LOAD_XOR_I16, + 546 => Opcode::ATOMIC_LOAD_XOR_I32, + 547 => Opcode::ATOMIC_LOAD_XOR_I64, + 548 => Opcode::ATOMIC_LOAD_XOR_I8, + 549 => Opcode::ATOMIC_SWAP_I16, + 550 => Opcode::ATOMIC_SWAP_I32, + 551 => Opcode::ATOMIC_SWAP_I64, + 552 => Opcode::ATOMIC_SWAP_I8, + 553 => Opcode::ATTN, + 554 => Opcode::B, + 555 => Opcode::BA, + 556 => Opcode::BC, + 557 => Opcode::BCC, + 558 => Opcode::BCCA, + 559 => Opcode::BCCCTR, + 560 => Opcode::BCCCTR8, + 561 => Opcode::BCCCTRL, + 562 => Opcode::BCCCTRL8, + 563 => Opcode::BCCL, + 564 => Opcode::BCCLA, + 565 => Opcode::BCCLR, + 566 => Opcode::BCCLRL, + 567 => Opcode::BCCTR, + 568 => Opcode::BCCTR8, + 569 => Opcode::BCCTR8n, + 570 => Opcode::BCCTRL, + 571 => Opcode::BCCTRL8, + 572 => Opcode::BCCTRL8n, + 573 => Opcode::BCCTRLn, + 574 => Opcode::BCCTRn, + 575 => Opcode::BCDADD_rec, + 576 => Opcode::BCDCFN_rec, + 577 => Opcode::BCDCFSQ_rec, + 578 => Opcode::BCDCFZ_rec, + 579 => Opcode::BCDCPSGN_rec, + 580 => Opcode::BCDCTN_rec, + 581 => Opcode::BCDCTSQ_rec, + 582 => Opcode::BCDCTZ_rec, + 583 => Opcode::BCDSETSGN_rec, + 584 => Opcode::BCDSR_rec, + 585 => Opcode::BCDSUB_rec, + 586 => Opcode::BCDS_rec, + 587 => Opcode::BCDTRUNC_rec, + 588 => Opcode::BCDUS_rec, + 589 => Opcode::BCDUTRUNC_rec, + 590 => Opcode::BCL, + 591 => Opcode::BCLR, + 592 => Opcode::BCLRL, + 593 => Opcode::BCLRLn, + 594 => Opcode::BCLRn, + 595 => Opcode::BCLalways, + 596 => Opcode::BCLn, + 597 => Opcode::BCTR, + 598 => Opcode::BCTR8, + 599 => Opcode::BCTRL, + 600 => Opcode::BCTRL8, + 601 => Opcode::BCTRL8_LDinto_toc, + 602 => Opcode::BCTRL8_LDinto_toc_RM, + 603 => Opcode::BCTRL8_RM, + 604 => Opcode::BCTRL_LWZinto_toc, + 605 => Opcode::BCTRL_LWZinto_toc_RM, + 606 => Opcode::BCTRL_RM, + 607 => Opcode::BCn, + 608 => Opcode::BDNZ, + 609 => Opcode::BDNZ8, + 610 => Opcode::BDNZA, + 611 => Opcode::BDNZAm, + 612 => Opcode::BDNZAp, + 613 => Opcode::BDNZL, + 614 => Opcode::BDNZLA, + 615 => Opcode::BDNZLAm, + 616 => Opcode::BDNZLAp, + 617 => Opcode::BDNZLR, + 618 => Opcode::BDNZLR8, + 619 => Opcode::BDNZLRL, + 620 => Opcode::BDNZLRLm, + 621 => Opcode::BDNZLRLp, + 622 => Opcode::BDNZLRm, + 623 => Opcode::BDNZLRp, + 624 => Opcode::BDNZLm, + 625 => Opcode::BDNZLp, + 626 => Opcode::BDNZm, + 627 => Opcode::BDNZp, + 628 => Opcode::BDZ, + 629 => Opcode::BDZ8, + 630 => Opcode::BDZA, + 631 => Opcode::BDZAm, + 632 => Opcode::BDZAp, + 633 => Opcode::BDZL, + 634 => Opcode::BDZLA, + 635 => Opcode::BDZLAm, + 636 => Opcode::BDZLAp, + 637 => Opcode::BDZLR, + 638 => Opcode::BDZLR8, + 639 => Opcode::BDZLRL, + 640 => Opcode::BDZLRLm, + 641 => Opcode::BDZLRLp, + 642 => Opcode::BDZLRm, + 643 => Opcode::BDZLRp, + 644 => Opcode::BDZLm, + 645 => Opcode::BDZLp, + 646 => Opcode::BDZm, + 647 => Opcode::BDZp, + 648 => Opcode::BL, + 649 => Opcode::BL8, + 650 => Opcode::BL8_NOP, + 651 => Opcode::BL8_NOP_RM, + 652 => Opcode::BL8_NOP_TLS, + 653 => Opcode::BL8_NOTOC, + 654 => Opcode::BL8_NOTOC_RM, + 655 => Opcode::BL8_NOTOC_TLS, + 656 => Opcode::BL8_RM, + 657 => Opcode::BL8_TLS, + 658 => Opcode::BL8_TLS_, + 659 => Opcode::BLA, + 660 => Opcode::BLA8, + 661 => Opcode::BLA8_NOP, + 662 => Opcode::BLA8_NOP_RM, + 663 => Opcode::BLA8_RM, + 664 => Opcode::BLA_RM, + 665 => Opcode::BLR, + 666 => Opcode::BLR8, + 667 => Opcode::BLRL, + 668 => Opcode::BL_NOP, + 669 => Opcode::BL_NOP_RM, + 670 => Opcode::BL_RM, + 671 => Opcode::BL_TLS, + 672 => Opcode::BPERMD, + 673 => Opcode::BRD, + 674 => Opcode::BRH, + 675 => Opcode::BRH8, + 676 => Opcode::BRINC, + 677 => Opcode::BRW, + 678 => Opcode::BRW8, + 679 => Opcode::CBCDTD, + 680 => Opcode::CBCDTD8, + 681 => Opcode::CDTBCD, + 682 => Opcode::CDTBCD8, + 683 => Opcode::CFUGED, + 684 => Opcode::CLRBHRB, + 685 => Opcode::CMPB, + 686 => Opcode::CMPB8, + 687 => Opcode::CMPD, + 688 => Opcode::CMPDI, + 689 => Opcode::CMPEQB, + 690 => Opcode::CMPLD, + 691 => Opcode::CMPLDI, + 692 => Opcode::CMPLW, + 693 => Opcode::CMPLWI, + 694 => Opcode::CMPRB, + 695 => Opcode::CMPRB8, + 696 => Opcode::CMPW, + 697 => Opcode::CMPWI, + 698 => Opcode::CNTLZD, + 699 => Opcode::CNTLZDM, + 700 => Opcode::CNTLZD_rec, + 701 => Opcode::CNTLZW, + 702 => Opcode::CNTLZW8, + 703 => Opcode::CNTLZW8_rec, + 704 => Opcode::CNTLZW_rec, + 705 => Opcode::CNTTZD, + 706 => Opcode::CNTTZDM, + 707 => Opcode::CNTTZD_rec, + 708 => Opcode::CNTTZW, + 709 => Opcode::CNTTZW8, + 710 => Opcode::CNTTZW8_rec, + 711 => Opcode::CNTTZW_rec, + 712 => Opcode::CP_ABORT, + 713 => Opcode::CP_COPY, + 714 => Opcode::CP_COPY8, + 715 => Opcode::CP_PASTE8_rec, + 716 => Opcode::CP_PASTE_rec, + 717 => Opcode::CR6SET, + 718 => Opcode::CR6UNSET, + 719 => Opcode::CRAND, + 720 => Opcode::CRANDC, + 721 => Opcode::CREQV, + 722 => Opcode::CRNAND, + 723 => Opcode::CRNOR, + 724 => Opcode::CRNOT, + 725 => Opcode::CROR, + 726 => Opcode::CRORC, + 727 => Opcode::CRSET, + 728 => Opcode::CRUNSET, + 729 => Opcode::CRXOR, + 730 => Opcode::CTRL_DEP, + 731 => Opcode::DADD, + 732 => Opcode::DADDQ, + 733 => Opcode::DADDQ_rec, + 734 => Opcode::DADD_rec, + 735 => Opcode::DARN, + 736 => Opcode::DCBA, + 737 => Opcode::DCBF, + 738 => Opcode::DCBFEP, + 739 => Opcode::DCBI, + 740 => Opcode::DCBST, + 741 => Opcode::DCBSTEP, + 742 => Opcode::DCBT, + 743 => Opcode::DCBTEP, + 744 => Opcode::DCBTST, + 745 => Opcode::DCBTSTEP, + 746 => Opcode::DCBZ, + 747 => Opcode::DCBZEP, + 748 => Opcode::DCBZL, + 749 => Opcode::DCBZLEP, + 750 => Opcode::DCCCI, + 751 => Opcode::DCFFIX, + 752 => Opcode::DCFFIXQ, + 753 => Opcode::DCFFIXQQ, + 754 => Opcode::DCFFIXQ_rec, + 755 => Opcode::DCFFIX_rec, + 756 => Opcode::DCMPO, + 757 => Opcode::DCMPOQ, + 758 => Opcode::DCMPU, + 759 => Opcode::DCMPUQ, + 760 => Opcode::DCTDP, + 761 => Opcode::DCTDP_rec, + 762 => Opcode::DCTFIX, + 763 => Opcode::DCTFIXQ, + 764 => Opcode::DCTFIXQQ, + 765 => Opcode::DCTFIXQ_rec, + 766 => Opcode::DCTFIX_rec, + 767 => Opcode::DCTQPQ, + 768 => Opcode::DCTQPQ_rec, + 769 => Opcode::DDEDPD, + 770 => Opcode::DDEDPDQ, + 771 => Opcode::DDEDPDQ_rec, + 772 => Opcode::DDEDPD_rec, + 773 => Opcode::DDIV, + 774 => Opcode::DDIVQ, + 775 => Opcode::DDIVQ_rec, + 776 => Opcode::DDIV_rec, + 777 => Opcode::DENBCD, + 778 => Opcode::DENBCDQ, + 779 => Opcode::DENBCDQ_rec, + 780 => Opcode::DENBCD_rec, + 781 => Opcode::DIEX, + 782 => Opcode::DIEXQ, + 783 => Opcode::DIEXQ_rec, + 784 => Opcode::DIEX_rec, + 785 => Opcode::DIVD, + 786 => Opcode::DIVDE, + 787 => Opcode::DIVDEO, + 788 => Opcode::DIVDEO_rec, + 789 => Opcode::DIVDEU, + 790 => Opcode::DIVDEUO, + 791 => Opcode::DIVDEUO_rec, + 792 => Opcode::DIVDEU_rec, + 793 => Opcode::DIVDE_rec, + 794 => Opcode::DIVDO, + 795 => Opcode::DIVDO_rec, + 796 => Opcode::DIVDU, + 797 => Opcode::DIVDUO, + 798 => Opcode::DIVDUO_rec, + 799 => Opcode::DIVDU_rec, + 800 => Opcode::DIVD_rec, + 801 => Opcode::DIVW, + 802 => Opcode::DIVWE, + 803 => Opcode::DIVWEO, + 804 => Opcode::DIVWEO_rec, + 805 => Opcode::DIVWEU, + 806 => Opcode::DIVWEUO, + 807 => Opcode::DIVWEUO_rec, + 808 => Opcode::DIVWEU_rec, + 809 => Opcode::DIVWE_rec, + 810 => Opcode::DIVWO, + 811 => Opcode::DIVWO_rec, + 812 => Opcode::DIVWU, + 813 => Opcode::DIVWUO, + 814 => Opcode::DIVWUO_rec, + 815 => Opcode::DIVWU_rec, + 816 => Opcode::DIVW_rec, + 817 => Opcode::DMMR, + 818 => Opcode::DMSETDMRZ, + 819 => Opcode::DMSHA2HASH, + 820 => Opcode::DMSHA3HASH, + 821 => Opcode::DMUL, + 822 => Opcode::DMULQ, + 823 => Opcode::DMULQ_rec, + 824 => Opcode::DMUL_rec, + 825 => Opcode::DMXOR, + 826 => Opcode::DMXVBF16GERX2, + 827 => Opcode::DMXVBF16GERX2NN, + 828 => Opcode::DMXVBF16GERX2NP, + 829 => Opcode::DMXVBF16GERX2PN, + 830 => Opcode::DMXVBF16GERX2PP, + 831 => Opcode::DMXVF16GERX2, + 832 => Opcode::DMXVF16GERX2NN, + 833 => Opcode::DMXVF16GERX2NP, + 834 => Opcode::DMXVF16GERX2PN, + 835 => Opcode::DMXVF16GERX2PP, + 836 => Opcode::DMXVI8GERX4, + 837 => Opcode::DMXVI8GERX4PP, + 838 => Opcode::DMXVI8GERX4SPP, + 839 => Opcode::DMXXEXTFDMR256, + 840 => Opcode::DMXXEXTFDMR512, + 841 => Opcode::DMXXEXTFDMR512_HI, + 842 => Opcode::DMXXINSTDMR256, + 843 => Opcode::DMXXINSTDMR512, + 844 => Opcode::DMXXINSTDMR512_HI, + 845 => Opcode::DMXXSETACCZ, + 846 => Opcode::DMXXSHAPAD, + 847 => Opcode::DQUA, + 848 => Opcode::DQUAI, + 849 => Opcode::DQUAIQ, + 850 => Opcode::DQUAIQ_rec, + 851 => Opcode::DQUAI_rec, + 852 => Opcode::DQUAQ, + 853 => Opcode::DQUAQ_rec, + 854 => Opcode::DQUA_rec, + 855 => Opcode::DRDPQ, + 856 => Opcode::DRDPQ_rec, + 857 => Opcode::DRINTN, + 858 => Opcode::DRINTNQ, + 859 => Opcode::DRINTNQ_rec, + 860 => Opcode::DRINTN_rec, + 861 => Opcode::DRINTX, + 862 => Opcode::DRINTXQ, + 863 => Opcode::DRINTXQ_rec, + 864 => Opcode::DRINTX_rec, + 865 => Opcode::DRRND, + 866 => Opcode::DRRNDQ, + 867 => Opcode::DRRNDQ_rec, + 868 => Opcode::DRRND_rec, + 869 => Opcode::DRSP, + 870 => Opcode::DRSP_rec, + 871 => Opcode::DSCLI, + 872 => Opcode::DSCLIQ, + 873 => Opcode::DSCLIQ_rec, + 874 => Opcode::DSCLI_rec, + 875 => Opcode::DSCRI, + 876 => Opcode::DSCRIQ, + 877 => Opcode::DSCRIQ_rec, + 878 => Opcode::DSCRI_rec, + 879 => Opcode::DSS, + 880 => Opcode::DSSALL, + 881 => Opcode::DST, + 882 => Opcode::DST64, + 883 => Opcode::DSTST, + 884 => Opcode::DSTST64, + 885 => Opcode::DSTSTT, + 886 => Opcode::DSTSTT64, + 887 => Opcode::DSTT, + 888 => Opcode::DSTT64, + 889 => Opcode::DSUB, + 890 => Opcode::DSUBQ, + 891 => Opcode::DSUBQ_rec, + 892 => Opcode::DSUB_rec, + 893 => Opcode::DTSTDC, + 894 => Opcode::DTSTDCQ, + 895 => Opcode::DTSTDG, + 896 => Opcode::DTSTDGQ, + 897 => Opcode::DTSTEX, + 898 => Opcode::DTSTEXQ, + 899 => Opcode::DTSTSF, + 900 => Opcode::DTSTSFI, + 901 => Opcode::DTSTSFIQ, + 902 => Opcode::DTSTSFQ, + 903 => Opcode::DXEX, + 904 => Opcode::DXEXQ, + 905 => Opcode::DXEXQ_rec, + 906 => Opcode::DXEX_rec, + 907 => Opcode::DYNALLOC, + 908 => Opcode::DYNALLOC8, + 909 => Opcode::DYNAREAOFFSET, + 910 => Opcode::DYNAREAOFFSET8, + 911 => Opcode::DecreaseCTR8loop, + 912 => Opcode::DecreaseCTRloop, + 913 => Opcode::EFDABS, + 914 => Opcode::EFDADD, + 915 => Opcode::EFDCFS, + 916 => Opcode::EFDCFSF, + 917 => Opcode::EFDCFSI, + 918 => Opcode::EFDCFSID, + 919 => Opcode::EFDCFUF, + 920 => Opcode::EFDCFUI, + 921 => Opcode::EFDCFUID, + 922 => Opcode::EFDCMPEQ, + 923 => Opcode::EFDCMPGT, + 924 => Opcode::EFDCMPLT, + 925 => Opcode::EFDCTSF, + 926 => Opcode::EFDCTSI, + 927 => Opcode::EFDCTSIDZ, + 928 => Opcode::EFDCTSIZ, + 929 => Opcode::EFDCTUF, + 930 => Opcode::EFDCTUI, + 931 => Opcode::EFDCTUIDZ, + 932 => Opcode::EFDCTUIZ, + 933 => Opcode::EFDDIV, + 934 => Opcode::EFDMUL, + 935 => Opcode::EFDNABS, + 936 => Opcode::EFDNEG, + 937 => Opcode::EFDSUB, + 938 => Opcode::EFDTSTEQ, + 939 => Opcode::EFDTSTGT, + 940 => Opcode::EFDTSTLT, + 941 => Opcode::EFSABS, + 942 => Opcode::EFSADD, + 943 => Opcode::EFSCFD, + 944 => Opcode::EFSCFSF, + 945 => Opcode::EFSCFSI, + 946 => Opcode::EFSCFUF, + 947 => Opcode::EFSCFUI, + 948 => Opcode::EFSCMPEQ, + 949 => Opcode::EFSCMPGT, + 950 => Opcode::EFSCMPLT, + 951 => Opcode::EFSCTSF, + 952 => Opcode::EFSCTSI, + 953 => Opcode::EFSCTSIZ, + 954 => Opcode::EFSCTUF, + 955 => Opcode::EFSCTUI, + 956 => Opcode::EFSCTUIZ, + 957 => Opcode::EFSDIV, + 958 => Opcode::EFSMUL, + 959 => Opcode::EFSNABS, + 960 => Opcode::EFSNEG, + 961 => Opcode::EFSSUB, + 962 => Opcode::EFSTSTEQ, + 963 => Opcode::EFSTSTGT, + 964 => Opcode::EFSTSTLT, + 965 => Opcode::EH_SjLj_LongJmp32, + 966 => Opcode::EH_SjLj_LongJmp64, + 967 => Opcode::EH_SjLj_SetJmp32, + 968 => Opcode::EH_SjLj_SetJmp64, + 969 => Opcode::EH_SjLj_Setup, + 970 => Opcode::EQV, + 971 => Opcode::EQV8, + 972 => Opcode::EQV8_rec, + 973 => Opcode::EQV_rec, + 974 => Opcode::EVABS, + 975 => Opcode::EVADDIW, + 976 => Opcode::EVADDSMIAAW, + 977 => Opcode::EVADDSSIAAW, + 978 => Opcode::EVADDUMIAAW, + 979 => Opcode::EVADDUSIAAW, + 980 => Opcode::EVADDW, + 981 => Opcode::EVAND, + 982 => Opcode::EVANDC, + 983 => Opcode::EVCMPEQ, + 984 => Opcode::EVCMPGTS, + 985 => Opcode::EVCMPGTU, + 986 => Opcode::EVCMPLTS, + 987 => Opcode::EVCMPLTU, + 988 => Opcode::EVCNTLSW, + 989 => Opcode::EVCNTLZW, + 990 => Opcode::EVDIVWS, + 991 => Opcode::EVDIVWU, + 992 => Opcode::EVEQV, + 993 => Opcode::EVEXTSB, + 994 => Opcode::EVEXTSH, + 995 => Opcode::EVFSABS, + 996 => Opcode::EVFSADD, + 997 => Opcode::EVFSCFSF, + 998 => Opcode::EVFSCFSI, + 999 => Opcode::EVFSCFUF, + 1000 => Opcode::EVFSCFUI, + 1001 => Opcode::EVFSCMPEQ, + 1002 => Opcode::EVFSCMPGT, + 1003 => Opcode::EVFSCMPLT, + 1004 => Opcode::EVFSCTSF, + 1005 => Opcode::EVFSCTSI, + 1006 => Opcode::EVFSCTSIZ, + 1007 => Opcode::EVFSCTUF, + 1008 => Opcode::EVFSCTUI, + 1009 => Opcode::EVFSCTUIZ, + 1010 => Opcode::EVFSDIV, + 1011 => Opcode::EVFSMUL, + 1012 => Opcode::EVFSNABS, + 1013 => Opcode::EVFSNEG, + 1014 => Opcode::EVFSSUB, + 1015 => Opcode::EVFSTSTEQ, + 1016 => Opcode::EVFSTSTGT, + 1017 => Opcode::EVFSTSTLT, + 1018 => Opcode::EVLDD, + 1019 => Opcode::EVLDDX, + 1020 => Opcode::EVLDH, + 1021 => Opcode::EVLDHX, + 1022 => Opcode::EVLDW, + 1023 => Opcode::EVLDWX, + 1024 => Opcode::EVLHHESPLAT, + 1025 => Opcode::EVLHHESPLATX, + 1026 => Opcode::EVLHHOSSPLAT, + 1027 => Opcode::EVLHHOSSPLATX, + 1028 => Opcode::EVLHHOUSPLAT, + 1029 => Opcode::EVLHHOUSPLATX, + 1030 => Opcode::EVLWHE, + 1031 => Opcode::EVLWHEX, + 1032 => Opcode::EVLWHOS, + 1033 => Opcode::EVLWHOSX, + 1034 => Opcode::EVLWHOU, + 1035 => Opcode::EVLWHOUX, + 1036 => Opcode::EVLWHSPLAT, + 1037 => Opcode::EVLWHSPLATX, + 1038 => Opcode::EVLWWSPLAT, + 1039 => Opcode::EVLWWSPLATX, + 1040 => Opcode::EVMERGEHI, + 1041 => Opcode::EVMERGEHILO, + 1042 => Opcode::EVMERGELO, + 1043 => Opcode::EVMERGELOHI, + 1044 => Opcode::EVMHEGSMFAA, + 1045 => Opcode::EVMHEGSMFAN, + 1046 => Opcode::EVMHEGSMIAA, + 1047 => Opcode::EVMHEGSMIAN, + 1048 => Opcode::EVMHEGUMIAA, + 1049 => Opcode::EVMHEGUMIAN, + 1050 => Opcode::EVMHESMF, + 1051 => Opcode::EVMHESMFA, + 1052 => Opcode::EVMHESMFAAW, + 1053 => Opcode::EVMHESMFANW, + 1054 => Opcode::EVMHESMI, + 1055 => Opcode::EVMHESMIA, + 1056 => Opcode::EVMHESMIAAW, + 1057 => Opcode::EVMHESMIANW, + 1058 => Opcode::EVMHESSF, + 1059 => Opcode::EVMHESSFA, + 1060 => Opcode::EVMHESSFAAW, + 1061 => Opcode::EVMHESSFANW, + 1062 => Opcode::EVMHESSIAAW, + 1063 => Opcode::EVMHESSIANW, + 1064 => Opcode::EVMHEUMI, + 1065 => Opcode::EVMHEUMIA, + 1066 => Opcode::EVMHEUMIAAW, + 1067 => Opcode::EVMHEUMIANW, + 1068 => Opcode::EVMHEUSIAAW, + 1069 => Opcode::EVMHEUSIANW, + 1070 => Opcode::EVMHOGSMFAA, + 1071 => Opcode::EVMHOGSMFAN, + 1072 => Opcode::EVMHOGSMIAA, + 1073 => Opcode::EVMHOGSMIAN, + 1074 => Opcode::EVMHOGUMIAA, + 1075 => Opcode::EVMHOGUMIAN, + 1076 => Opcode::EVMHOSMF, + 1077 => Opcode::EVMHOSMFA, + 1078 => Opcode::EVMHOSMFAAW, + 1079 => Opcode::EVMHOSMFANW, + 1080 => Opcode::EVMHOSMI, + 1081 => Opcode::EVMHOSMIA, + 1082 => Opcode::EVMHOSMIAAW, + 1083 => Opcode::EVMHOSMIANW, + 1084 => Opcode::EVMHOSSF, + 1085 => Opcode::EVMHOSSFA, + 1086 => Opcode::EVMHOSSFAAW, + 1087 => Opcode::EVMHOSSFANW, + 1088 => Opcode::EVMHOSSIAAW, + 1089 => Opcode::EVMHOSSIANW, + 1090 => Opcode::EVMHOUMI, + 1091 => Opcode::EVMHOUMIA, + 1092 => Opcode::EVMHOUMIAAW, + 1093 => Opcode::EVMHOUMIANW, + 1094 => Opcode::EVMHOUSIAAW, + 1095 => Opcode::EVMHOUSIANW, + 1096 => Opcode::EVMRA, + 1097 => Opcode::EVMWHSMF, + 1098 => Opcode::EVMWHSMFA, + 1099 => Opcode::EVMWHSMI, + 1100 => Opcode::EVMWHSMIA, + 1101 => Opcode::EVMWHSSF, + 1102 => Opcode::EVMWHSSFA, + 1103 => Opcode::EVMWHUMI, + 1104 => Opcode::EVMWHUMIA, + 1105 => Opcode::EVMWLSMIAAW, + 1106 => Opcode::EVMWLSMIANW, + 1107 => Opcode::EVMWLSSIAAW, + 1108 => Opcode::EVMWLSSIANW, + 1109 => Opcode::EVMWLUMI, + 1110 => Opcode::EVMWLUMIA, + 1111 => Opcode::EVMWLUMIAAW, + 1112 => Opcode::EVMWLUMIANW, + 1113 => Opcode::EVMWLUSIAAW, + 1114 => Opcode::EVMWLUSIANW, + 1115 => Opcode::EVMWSMF, + 1116 => Opcode::EVMWSMFA, + 1117 => Opcode::EVMWSMFAA, + 1118 => Opcode::EVMWSMFAN, + 1119 => Opcode::EVMWSMI, + 1120 => Opcode::EVMWSMIA, + 1121 => Opcode::EVMWSMIAA, + 1122 => Opcode::EVMWSMIAN, + 1123 => Opcode::EVMWSSF, + 1124 => Opcode::EVMWSSFA, + 1125 => Opcode::EVMWSSFAA, + 1126 => Opcode::EVMWSSFAN, + 1127 => Opcode::EVMWUMI, + 1128 => Opcode::EVMWUMIA, + 1129 => Opcode::EVMWUMIAA, + 1130 => Opcode::EVMWUMIAN, + 1131 => Opcode::EVNAND, + 1132 => Opcode::EVNEG, + 1133 => Opcode::EVNOR, + 1134 => Opcode::EVOR, + 1135 => Opcode::EVORC, + 1136 => Opcode::EVRLW, + 1137 => Opcode::EVRLWI, + 1138 => Opcode::EVRNDW, + 1139 => Opcode::EVSEL, + 1140 => Opcode::EVSLW, + 1141 => Opcode::EVSLWI, + 1142 => Opcode::EVSPLATFI, + 1143 => Opcode::EVSPLATI, + 1144 => Opcode::EVSRWIS, + 1145 => Opcode::EVSRWIU, + 1146 => Opcode::EVSRWS, + 1147 => Opcode::EVSRWU, + 1148 => Opcode::EVSTDD, + 1149 => Opcode::EVSTDDX, + 1150 => Opcode::EVSTDH, + 1151 => Opcode::EVSTDHX, + 1152 => Opcode::EVSTDW, + 1153 => Opcode::EVSTDWX, + 1154 => Opcode::EVSTWHE, + 1155 => Opcode::EVSTWHEX, + 1156 => Opcode::EVSTWHO, + 1157 => Opcode::EVSTWHOX, + 1158 => Opcode::EVSTWWE, + 1159 => Opcode::EVSTWWEX, + 1160 => Opcode::EVSTWWO, + 1161 => Opcode::EVSTWWOX, + 1162 => Opcode::EVSUBFSMIAAW, + 1163 => Opcode::EVSUBFSSIAAW, + 1164 => Opcode::EVSUBFUMIAAW, + 1165 => Opcode::EVSUBFUSIAAW, + 1166 => Opcode::EVSUBFW, + 1167 => Opcode::EVSUBIFW, + 1168 => Opcode::EVXOR, + 1169 => Opcode::EXTSB, + 1170 => Opcode::EXTSB8, + 1171 => Opcode::EXTSB8_32_64, + 1172 => Opcode::EXTSB8_rec, + 1173 => Opcode::EXTSB_rec, + 1174 => Opcode::EXTSH, + 1175 => Opcode::EXTSH8, + 1176 => Opcode::EXTSH8_32_64, + 1177 => Opcode::EXTSH8_rec, + 1178 => Opcode::EXTSH_rec, + 1179 => Opcode::EXTSW, + 1180 => Opcode::EXTSWSLI, + 1181 => Opcode::EXTSWSLI_32_64, + 1182 => Opcode::EXTSWSLI_32_64_rec, + 1183 => Opcode::EXTSWSLI_rec, + 1184 => Opcode::EXTSW_32, + 1185 => Opcode::EXTSW_32_64, + 1186 => Opcode::EXTSW_32_64_rec, + 1187 => Opcode::EXTSW_rec, + 1188 => Opcode::EnforceIEIO, + 1189 => Opcode::FABSD, + 1190 => Opcode::FABSD_rec, + 1191 => Opcode::FABSS, + 1192 => Opcode::FABSS_rec, + 1193 => Opcode::FADD, + 1194 => Opcode::FADDS, + 1195 => Opcode::FADDS_rec, + 1196 => Opcode::FADD_rec, + 1197 => Opcode::FADDrtz, + 1198 => Opcode::FCFID, + 1199 => Opcode::FCFIDS, + 1200 => Opcode::FCFIDS_rec, + 1201 => Opcode::FCFIDU, + 1202 => Opcode::FCFIDUS, + 1203 => Opcode::FCFIDUS_rec, + 1204 => Opcode::FCFIDU_rec, + 1205 => Opcode::FCFID_rec, + 1206 => Opcode::FCMPOD, + 1207 => Opcode::FCMPOS, + 1208 => Opcode::FCMPUD, + 1209 => Opcode::FCMPUS, + 1210 => Opcode::FCPSGND, + 1211 => Opcode::FCPSGND_rec, + 1212 => Opcode::FCPSGNS, + 1213 => Opcode::FCPSGNS_rec, + 1214 => Opcode::FCTID, + 1215 => Opcode::FCTIDU, + 1216 => Opcode::FCTIDUZ, + 1217 => Opcode::FCTIDUZ_rec, + 1218 => Opcode::FCTIDU_rec, + 1219 => Opcode::FCTIDZ, + 1220 => Opcode::FCTIDZ_rec, + 1221 => Opcode::FCTID_rec, + 1222 => Opcode::FCTIW, + 1223 => Opcode::FCTIWU, + 1224 => Opcode::FCTIWUZ, + 1225 => Opcode::FCTIWUZ_rec, + 1226 => Opcode::FCTIWU_rec, + 1227 => Opcode::FCTIWZ, + 1228 => Opcode::FCTIWZ_rec, + 1229 => Opcode::FCTIW_rec, + 1230 => Opcode::FDIV, + 1231 => Opcode::FDIVS, + 1232 => Opcode::FDIVS_rec, + 1233 => Opcode::FDIV_rec, + 1234 => Opcode::FENCE, + 1235 => Opcode::FMADD, + 1236 => Opcode::FMADDS, + 1237 => Opcode::FMADDS_rec, + 1238 => Opcode::FMADD_rec, + 1239 => Opcode::FMR, + 1240 => Opcode::FMR_rec, + 1241 => Opcode::FMSUB, + 1242 => Opcode::FMSUBS, + 1243 => Opcode::FMSUBS_rec, + 1244 => Opcode::FMSUB_rec, + 1245 => Opcode::FMUL, + 1246 => Opcode::FMULS, + 1247 => Opcode::FMULS_rec, + 1248 => Opcode::FMUL_rec, + 1249 => Opcode::FNABSD, + 1250 => Opcode::FNABSD_rec, + 1251 => Opcode::FNABSS, + 1252 => Opcode::FNABSS_rec, + 1253 => Opcode::FNEGD, + 1254 => Opcode::FNEGD_rec, + 1255 => Opcode::FNEGS, + 1256 => Opcode::FNEGS_rec, + 1257 => Opcode::FNMADD, + 1258 => Opcode::FNMADDS, + 1259 => Opcode::FNMADDS_rec, + 1260 => Opcode::FNMADD_rec, + 1261 => Opcode::FNMSUB, + 1262 => Opcode::FNMSUBS, + 1263 => Opcode::FNMSUBS_rec, + 1264 => Opcode::FNMSUB_rec, + 1265 => Opcode::FRE, + 1266 => Opcode::FRES, + 1267 => Opcode::FRES_rec, + 1268 => Opcode::FRE_rec, + 1269 => Opcode::FRIMD, + 1270 => Opcode::FRIMD_rec, + 1271 => Opcode::FRIMS, + 1272 => Opcode::FRIMS_rec, + 1273 => Opcode::FRIND, + 1274 => Opcode::FRIND_rec, + 1275 => Opcode::FRINS, + 1276 => Opcode::FRINS_rec, + 1277 => Opcode::FRIPD, + 1278 => Opcode::FRIPD_rec, + 1279 => Opcode::FRIPS, + 1280 => Opcode::FRIPS_rec, + 1281 => Opcode::FRIZD, + 1282 => Opcode::FRIZD_rec, + 1283 => Opcode::FRIZS, + 1284 => Opcode::FRIZS_rec, + 1285 => Opcode::FRSP, + 1286 => Opcode::FRSP_rec, + 1287 => Opcode::FRSQRTE, + 1288 => Opcode::FRSQRTES, + 1289 => Opcode::FRSQRTES_rec, + 1290 => Opcode::FRSQRTE_rec, + 1291 => Opcode::FSELD, + 1292 => Opcode::FSELD_rec, + 1293 => Opcode::FSELS, + 1294 => Opcode::FSELS_rec, + 1295 => Opcode::FSQRT, + 1296 => Opcode::FSQRTS, + 1297 => Opcode::FSQRTS_rec, + 1298 => Opcode::FSQRT_rec, + 1299 => Opcode::FSUB, + 1300 => Opcode::FSUBS, + 1301 => Opcode::FSUBS_rec, + 1302 => Opcode::FSUB_rec, + 1303 => Opcode::FTDIV, + 1304 => Opcode::FTSQRT, + 1305 => Opcode::GETtlsADDR, + 1306 => Opcode::GETtlsADDR32, + 1307 => Opcode::GETtlsADDR32AIX, + 1308 => Opcode::GETtlsADDR64AIX, + 1309 => Opcode::GETtlsADDRPCREL, + 1310 => Opcode::GETtlsMOD32AIX, + 1311 => Opcode::GETtlsMOD64AIX, + 1312 => Opcode::GETtlsTpointer32AIX, + 1313 => Opcode::GETtlsldADDR, + 1314 => Opcode::GETtlsldADDR32, + 1315 => Opcode::GETtlsldADDRPCREL, + 1316 => Opcode::HASHCHK, + 1317 => Opcode::HASHCHK8, + 1318 => Opcode::HASHCHKP, + 1319 => Opcode::HASHCHKP8, + 1320 => Opcode::HASHST, + 1321 => Opcode::HASHST8, + 1322 => Opcode::HASHSTP, + 1323 => Opcode::HASHSTP8, + 1324 => Opcode::HRFID, + 1325 => Opcode::ICBI, + 1326 => Opcode::ICBIEP, + 1327 => Opcode::ICBLC, + 1328 => Opcode::ICBLQ, + 1329 => Opcode::ICBT, + 1330 => Opcode::ICBTLS, + 1331 => Opcode::ICCCI, + 1332 => Opcode::ISEL, + 1333 => Opcode::ISEL8, + 1334 => Opcode::ISYNC, + 1335 => Opcode::LA, + 1336 => Opcode::LA8, + 1337 => Opcode::LBARX, + 1338 => Opcode::LBARXL, + 1339 => Opcode::LBEPX, + 1340 => Opcode::LBZ, + 1341 => Opcode::LBZ8, + 1342 => Opcode::LBZCIX, + 1343 => Opcode::LBZU, + 1344 => Opcode::LBZU8, + 1345 => Opcode::LBZUX, + 1346 => Opcode::LBZUX8, + 1347 => Opcode::LBZX, + 1348 => Opcode::LBZX8, + 1349 => Opcode::LBZXTLS, + 1350 => Opcode::LBZXTLS_, + 1351 => Opcode::LBZXTLS_32, + 1352 => Opcode::LD, + 1353 => Opcode::LDARX, + 1354 => Opcode::LDARXL, + 1355 => Opcode::LDAT, + 1356 => Opcode::LDAT_PSEUDO, + 1357 => Opcode::LDBRX, + 1358 => Opcode::LDCIX, + 1359 => Opcode::LDU, + 1360 => Opcode::LDUX, + 1361 => Opcode::LDX, + 1362 => Opcode::LDXTLS, + 1363 => Opcode::LDXTLS_, + 1364 => Opcode::LDgotTprelL, + 1365 => Opcode::LDgotTprelL32, + 1366 => Opcode::LDtoc, + 1367 => Opcode::LDtocBA, + 1368 => Opcode::LDtocCPT, + 1369 => Opcode::LDtocJTI, + 1370 => Opcode::LDtocL, + 1371 => Opcode::LFD, + 1372 => Opcode::LFDEPX, + 1373 => Opcode::LFDU, + 1374 => Opcode::LFDUX, + 1375 => Opcode::LFDX, + 1376 => Opcode::LFDXTLS, + 1377 => Opcode::LFDXTLS_, + 1378 => Opcode::LFIWAX, + 1379 => Opcode::LFIWZX, + 1380 => Opcode::LFS, + 1381 => Opcode::LFSU, + 1382 => Opcode::LFSUX, + 1383 => Opcode::LFSX, + 1384 => Opcode::LFSXTLS, + 1385 => Opcode::LFSXTLS_, + 1386 => Opcode::LHA, + 1387 => Opcode::LHA8, + 1388 => Opcode::LHARX, + 1389 => Opcode::LHARXL, + 1390 => Opcode::LHAU, + 1391 => Opcode::LHAU8, + 1392 => Opcode::LHAUX, + 1393 => Opcode::LHAUX8, + 1394 => Opcode::LHAX, + 1395 => Opcode::LHAX8, + 1396 => Opcode::LHAXTLS, + 1397 => Opcode::LHAXTLS_, + 1398 => Opcode::LHAXTLS_32, + 1399 => Opcode::LHBRX, + 1400 => Opcode::LHBRX8, + 1401 => Opcode::LHEPX, + 1402 => Opcode::LHZ, + 1403 => Opcode::LHZ8, + 1404 => Opcode::LHZCIX, + 1405 => Opcode::LHZU, + 1406 => Opcode::LHZU8, + 1407 => Opcode::LHZUX, + 1408 => Opcode::LHZUX8, + 1409 => Opcode::LHZX, + 1410 => Opcode::LHZX8, + 1411 => Opcode::LHZXTLS, + 1412 => Opcode::LHZXTLS_, + 1413 => Opcode::LHZXTLS_32, + 1414 => Opcode::LI, + 1415 => Opcode::LI8, + 1416 => Opcode::LIS, + 1417 => Opcode::LIS8, + 1418 => Opcode::LMW, + 1419 => Opcode::LQ, + 1420 => Opcode::LQARX, + 1421 => Opcode::LQARXL, + 1422 => Opcode::LQX_PSEUDO, + 1423 => Opcode::LSWI, + 1424 => Opcode::LVEBX, + 1425 => Opcode::LVEHX, + 1426 => Opcode::LVEWX, + 1427 => Opcode::LVSL, + 1428 => Opcode::LVSR, + 1429 => Opcode::LVX, + 1430 => Opcode::LVXL, + 1431 => Opcode::LWA, + 1432 => Opcode::LWARX, + 1433 => Opcode::LWARXL, + 1434 => Opcode::LWAT, + 1435 => Opcode::LWAT_PSEUDO, + 1436 => Opcode::LWAUX, + 1437 => Opcode::LWAX, + 1438 => Opcode::LWAXTLS, + 1439 => Opcode::LWAXTLS_, + 1440 => Opcode::LWAXTLS_32, + 1441 => Opcode::LWAX_32, + 1442 => Opcode::LWA_32, + 1443 => Opcode::LWBRX, + 1444 => Opcode::LWBRX8, + 1445 => Opcode::LWEPX, + 1446 => Opcode::LWZ, + 1447 => Opcode::LWZ8, + 1448 => Opcode::LWZCIX, + 1449 => Opcode::LWZU, + 1450 => Opcode::LWZU8, + 1451 => Opcode::LWZUX, + 1452 => Opcode::LWZUX8, + 1453 => Opcode::LWZX, + 1454 => Opcode::LWZX8, + 1455 => Opcode::LWZXTLS, + 1456 => Opcode::LWZXTLS_, + 1457 => Opcode::LWZXTLS_32, + 1458 => Opcode::LWZtoc, + 1459 => Opcode::LWZtocL, + 1460 => Opcode::LXSD, + 1461 => Opcode::LXSDX, + 1462 => Opcode::LXSIBZX, + 1463 => Opcode::LXSIHZX, + 1464 => Opcode::LXSIWAX, + 1465 => Opcode::LXSIWZX, + 1466 => Opcode::LXSSP, + 1467 => Opcode::LXSSPX, + 1468 => Opcode::LXV, + 1469 => Opcode::LXVB16X, + 1470 => Opcode::LXVD2X, + 1471 => Opcode::LXVDSX, + 1472 => Opcode::LXVH8X, + 1473 => Opcode::LXVKQ, + 1474 => Opcode::LXVL, + 1475 => Opcode::LXVLL, + 1476 => Opcode::LXVP, + 1477 => Opcode::LXVPB32X, + 1478 => Opcode::LXVPRL, + 1479 => Opcode::LXVPRLL, + 1480 => Opcode::LXVPX, + 1481 => Opcode::LXVRBX, + 1482 => Opcode::LXVRDX, + 1483 => Opcode::LXVRHX, + 1484 => Opcode::LXVRL, + 1485 => Opcode::LXVRLL, + 1486 => Opcode::LXVRWX, + 1487 => Opcode::LXVW4X, + 1488 => Opcode::LXVWSX, + 1489 => Opcode::LXVX, + 1490 => Opcode::MADDHD, + 1491 => Opcode::MADDHDU, + 1492 => Opcode::MADDLD, + 1493 => Opcode::MADDLD8, + 1494 => Opcode::MBAR, + 1495 => Opcode::MCRF, + 1496 => Opcode::MCRFS, + 1497 => Opcode::MCRXRX, + 1498 => Opcode::MFBHRBE, + 1499 => Opcode::MFCR, + 1500 => Opcode::MFCR8, + 1501 => Opcode::MFCTR, + 1502 => Opcode::MFCTR8, + 1503 => Opcode::MFDCR, + 1504 => Opcode::MFFS, + 1505 => Opcode::MFFSCDRN, + 1506 => Opcode::MFFSCDRNI, + 1507 => Opcode::MFFSCE, + 1508 => Opcode::MFFSCRN, + 1509 => Opcode::MFFSCRNI, + 1510 => Opcode::MFFSL, + 1511 => Opcode::MFFS_rec, + 1512 => Opcode::MFLR, + 1513 => Opcode::MFLR8, + 1514 => Opcode::MFMSR, + 1515 => Opcode::MFOCRF, + 1516 => Opcode::MFOCRF8, + 1517 => Opcode::MFPMR, + 1518 => Opcode::MFSPR, + 1519 => Opcode::MFSPR8, + 1520 => Opcode::MFSR, + 1521 => Opcode::MFSRIN, + 1522 => Opcode::MFTB, + 1523 => Opcode::MFTB8, + 1524 => Opcode::MFUDSCR, + 1525 => Opcode::MFVRD, + 1526 => Opcode::MFVRSAVE, + 1527 => Opcode::MFVRSAVEv, + 1528 => Opcode::MFVRWZ, + 1529 => Opcode::MFVSCR, + 1530 => Opcode::MFVSRD, + 1531 => Opcode::MFVSRLD, + 1532 => Opcode::MFVSRWZ, + 1533 => Opcode::MODSD, + 1534 => Opcode::MODSW, + 1535 => Opcode::MODUD, + 1536 => Opcode::MODUW, + 1537 => Opcode::MSGSYNC, + 1538 => Opcode::MSYNC, + 1539 => Opcode::MTCRF, + 1540 => Opcode::MTCRF8, + 1541 => Opcode::MTCTR, + 1542 => Opcode::MTCTR8, + 1543 => Opcode::MTCTR8loop, + 1544 => Opcode::MTCTRloop, + 1545 => Opcode::MTDCR, + 1546 => Opcode::MTFSB0, + 1547 => Opcode::MTFSB1, + 1548 => Opcode::MTFSF, + 1549 => Opcode::MTFSFI, + 1550 => Opcode::MTFSFI_rec, + 1551 => Opcode::MTFSFIb, + 1552 => Opcode::MTFSF_rec, + 1553 => Opcode::MTFSFb, + 1554 => Opcode::MTLPL, + 1555 => Opcode::MTLPL8, + 1556 => Opcode::MTLR, + 1557 => Opcode::MTLR8, + 1558 => Opcode::MTMSR, + 1559 => Opcode::MTMSRD, + 1560 => Opcode::MTOCRF, + 1561 => Opcode::MTOCRF8, + 1562 => Opcode::MTPMR, + 1563 => Opcode::MTSPR, + 1564 => Opcode::MTSPR8, + 1565 => Opcode::MTSR, + 1566 => Opcode::MTSRIN, + 1567 => Opcode::MTUDSCR, + 1568 => Opcode::MTVRD, + 1569 => Opcode::MTVRSAVE, + 1570 => Opcode::MTVRSAVEv, + 1571 => Opcode::MTVRWA, + 1572 => Opcode::MTVRWZ, + 1573 => Opcode::MTVSCR, + 1574 => Opcode::MTVSRBM, + 1575 => Opcode::MTVSRBMI, + 1576 => Opcode::MTVSRD, + 1577 => Opcode::MTVSRDD, + 1578 => Opcode::MTVSRDM, + 1579 => Opcode::MTVSRHM, + 1580 => Opcode::MTVSRQM, + 1581 => Opcode::MTVSRWA, + 1582 => Opcode::MTVSRWM, + 1583 => Opcode::MTVSRWS, + 1584 => Opcode::MTVSRWZ, + 1585 => Opcode::MULHD, + 1586 => Opcode::MULHDU, + 1587 => Opcode::MULHDU_rec, + 1588 => Opcode::MULHD_rec, + 1589 => Opcode::MULHW, + 1590 => Opcode::MULHWU, + 1591 => Opcode::MULHWU_rec, + 1592 => Opcode::MULHW_rec, + 1593 => Opcode::MULLD, + 1594 => Opcode::MULLDO, + 1595 => Opcode::MULLDO_rec, + 1596 => Opcode::MULLD_rec, + 1597 => Opcode::MULLI, + 1598 => Opcode::MULLI8, + 1599 => Opcode::MULLW, + 1600 => Opcode::MULLWO, + 1601 => Opcode::MULLWO_rec, + 1602 => Opcode::MULLW_rec, + 1603 => Opcode::MoveGOTtoLR, + 1604 => Opcode::MovePCtoLR, + 1605 => Opcode::MovePCtoLR8, + 1606 => Opcode::NAND, + 1607 => Opcode::NAND8, + 1608 => Opcode::NAND8_rec, + 1609 => Opcode::NAND_rec, + 1610 => Opcode::NAP, + 1611 => Opcode::NEG, + 1612 => Opcode::NEG8, + 1613 => Opcode::NEG8O, + 1614 => Opcode::NEG8O_rec, + 1615 => Opcode::NEG8_rec, + 1616 => Opcode::NEGO, + 1617 => Opcode::NEGO_rec, + 1618 => Opcode::NEG_rec, + 1619 => Opcode::NOP, + 1620 => Opcode::NOP_GT_PWR6, + 1621 => Opcode::NOP_GT_PWR7, + 1622 => Opcode::NOR, + 1623 => Opcode::NOR8, + 1624 => Opcode::NOR8_rec, + 1625 => Opcode::NOR_rec, + 1626 => Opcode::OR, + 1627 => Opcode::OR8, + 1628 => Opcode::OR8_rec, + 1629 => Opcode::ORC, + 1630 => Opcode::ORC8, + 1631 => Opcode::ORC8_rec, + 1632 => Opcode::ORC_rec, + 1633 => Opcode::ORI, + 1634 => Opcode::ORI8, + 1635 => Opcode::ORIS, + 1636 => Opcode::ORIS8, + 1637 => Opcode::OR_rec, + 1638 => Opcode::PADDI, + 1639 => Opcode::PADDI8, + 1640 => Opcode::PADDI8pc, + 1641 => Opcode::PADDIS, + 1642 => Opcode::PADDIS8, + 1643 => Opcode::PADDIS8pc, + 1644 => Opcode::PADDISpc, + 1645 => Opcode::PADDIdtprel, + 1646 => Opcode::PADDIpc, + 1647 => Opcode::PDEPD, + 1648 => Opcode::PEXTD, + 1649 => Opcode::PLA, + 1650 => Opcode::PLA8, + 1651 => Opcode::PLA8pc, + 1652 => Opcode::PLApc, + 1653 => Opcode::PLBZ, + 1654 => Opcode::PLBZ8, + 1655 => Opcode::PLBZ8nopc, + 1656 => Opcode::PLBZ8onlypc, + 1657 => Opcode::PLBZ8pc, + 1658 => Opcode::PLBZnopc, + 1659 => Opcode::PLBZonlypc, + 1660 => Opcode::PLBZpc, + 1661 => Opcode::PLD, + 1662 => Opcode::PLDnopc, + 1663 => Opcode::PLDonlypc, + 1664 => Opcode::PLDpc, + 1665 => Opcode::PLFD, + 1666 => Opcode::PLFDnopc, + 1667 => Opcode::PLFDonlypc, + 1668 => Opcode::PLFDpc, + 1669 => Opcode::PLFS, + 1670 => Opcode::PLFSnopc, + 1671 => Opcode::PLFSonlypc, + 1672 => Opcode::PLFSpc, + 1673 => Opcode::PLHA, + 1674 => Opcode::PLHA8, + 1675 => Opcode::PLHA8nopc, + 1676 => Opcode::PLHA8onlypc, + 1677 => Opcode::PLHA8pc, + 1678 => Opcode::PLHAnopc, + 1679 => Opcode::PLHAonlypc, + 1680 => Opcode::PLHApc, + 1681 => Opcode::PLHZ, + 1682 => Opcode::PLHZ8, + 1683 => Opcode::PLHZ8nopc, + 1684 => Opcode::PLHZ8onlypc, + 1685 => Opcode::PLHZ8pc, + 1686 => Opcode::PLHZnopc, + 1687 => Opcode::PLHZonlypc, + 1688 => Opcode::PLHZpc, + 1689 => Opcode::PLI, + 1690 => Opcode::PLI8, + 1691 => Opcode::PLWA, + 1692 => Opcode::PLWA8, + 1693 => Opcode::PLWA8nopc, + 1694 => Opcode::PLWA8onlypc, + 1695 => Opcode::PLWA8pc, + 1696 => Opcode::PLWAnopc, + 1697 => Opcode::PLWAonlypc, + 1698 => Opcode::PLWApc, + 1699 => Opcode::PLWZ, + 1700 => Opcode::PLWZ8, + 1701 => Opcode::PLWZ8nopc, + 1702 => Opcode::PLWZ8onlypc, + 1703 => Opcode::PLWZ8pc, + 1704 => Opcode::PLWZnopc, + 1705 => Opcode::PLWZonlypc, + 1706 => Opcode::PLWZpc, + 1707 => Opcode::PLXSD, + 1708 => Opcode::PLXSDnopc, + 1709 => Opcode::PLXSDonlypc, + 1710 => Opcode::PLXSDpc, + 1711 => Opcode::PLXSSP, + 1712 => Opcode::PLXSSPnopc, + 1713 => Opcode::PLXSSPonlypc, + 1714 => Opcode::PLXSSPpc, + 1715 => Opcode::PLXV, + 1716 => Opcode::PLXVP, + 1717 => Opcode::PLXVPnopc, + 1718 => Opcode::PLXVPonlypc, + 1719 => Opcode::PLXVPpc, + 1720 => Opcode::PLXVnopc, + 1721 => Opcode::PLXVonlypc, + 1722 => Opcode::PLXVpc, + 1723 => Opcode::PMDMXVBF16GERX2, + 1724 => Opcode::PMDMXVBF16GERX2NN, + 1725 => Opcode::PMDMXVBF16GERX2NP, + 1726 => Opcode::PMDMXVBF16GERX2PN, + 1727 => Opcode::PMDMXVBF16GERX2PP, + 1728 => Opcode::PMDMXVF16GERX2, + 1729 => Opcode::PMDMXVF16GERX2NN, + 1730 => Opcode::PMDMXVF16GERX2NP, + 1731 => Opcode::PMDMXVF16GERX2PN, + 1732 => Opcode::PMDMXVF16GERX2PP, + 1733 => Opcode::PMDMXVI8GERX4, + 1734 => Opcode::PMDMXVI8GERX4PP, + 1735 => Opcode::PMDMXVI8GERX4SPP, + 1736 => Opcode::PMXVBF16GER2, + 1737 => Opcode::PMXVBF16GER2NN, + 1738 => Opcode::PMXVBF16GER2NP, + 1739 => Opcode::PMXVBF16GER2PN, + 1740 => Opcode::PMXVBF16GER2PP, + 1741 => Opcode::PMXVBF16GER2W, + 1742 => Opcode::PMXVBF16GER2WNN, + 1743 => Opcode::PMXVBF16GER2WNP, + 1744 => Opcode::PMXVBF16GER2WPN, + 1745 => Opcode::PMXVBF16GER2WPP, + 1746 => Opcode::PMXVF16GER2, + 1747 => Opcode::PMXVF16GER2NN, + 1748 => Opcode::PMXVF16GER2NP, + 1749 => Opcode::PMXVF16GER2PN, + 1750 => Opcode::PMXVF16GER2PP, + 1751 => Opcode::PMXVF16GER2W, + 1752 => Opcode::PMXVF16GER2WNN, + 1753 => Opcode::PMXVF16GER2WNP, + 1754 => Opcode::PMXVF16GER2WPN, + 1755 => Opcode::PMXVF16GER2WPP, + 1756 => Opcode::PMXVF32GER, + 1757 => Opcode::PMXVF32GERNN, + 1758 => Opcode::PMXVF32GERNP, + 1759 => Opcode::PMXVF32GERPN, + 1760 => Opcode::PMXVF32GERPP, + 1761 => Opcode::PMXVF32GERW, + 1762 => Opcode::PMXVF32GERWNN, + 1763 => Opcode::PMXVF32GERWNP, + 1764 => Opcode::PMXVF32GERWPN, + 1765 => Opcode::PMXVF32GERWPP, + 1766 => Opcode::PMXVF64GER, + 1767 => Opcode::PMXVF64GERNN, + 1768 => Opcode::PMXVF64GERNP, + 1769 => Opcode::PMXVF64GERPN, + 1770 => Opcode::PMXVF64GERPP, + 1771 => Opcode::PMXVF64GERW, + 1772 => Opcode::PMXVF64GERWNN, + 1773 => Opcode::PMXVF64GERWNP, + 1774 => Opcode::PMXVF64GERWPN, + 1775 => Opcode::PMXVF64GERWPP, + 1776 => Opcode::PMXVI16GER2, + 1777 => Opcode::PMXVI16GER2PP, + 1778 => Opcode::PMXVI16GER2S, + 1779 => Opcode::PMXVI16GER2SPP, + 1780 => Opcode::PMXVI16GER2SW, + 1781 => Opcode::PMXVI16GER2SWPP, + 1782 => Opcode::PMXVI16GER2W, + 1783 => Opcode::PMXVI16GER2WPP, + 1784 => Opcode::PMXVI4GER8, + 1785 => Opcode::PMXVI4GER8PP, + 1786 => Opcode::PMXVI4GER8W, + 1787 => Opcode::PMXVI4GER8WPP, + 1788 => Opcode::PMXVI8GER4, + 1789 => Opcode::PMXVI8GER4PP, + 1790 => Opcode::PMXVI8GER4SPP, + 1791 => Opcode::PMXVI8GER4W, + 1792 => Opcode::PMXVI8GER4WPP, + 1793 => Opcode::PMXVI8GER4WSPP, + 1794 => Opcode::POPCNTB, + 1795 => Opcode::POPCNTB8, + 1796 => Opcode::POPCNTD, + 1797 => Opcode::POPCNTW, + 1798 => Opcode::PPC32GOT, + 1799 => Opcode::PPC32PICGOT, + 1800 => Opcode::PREPARE_PROBED_ALLOCA_32, + 1801 => Opcode::PREPARE_PROBED_ALLOCA_64, + 1802 => Opcode::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32, + 1803 => Opcode::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64, + 1804 => Opcode::PROBED_ALLOCA_32, + 1805 => Opcode::PROBED_ALLOCA_64, + 1806 => Opcode::PROBED_STACKALLOC_32, + 1807 => Opcode::PROBED_STACKALLOC_64, + 1808 => Opcode::PSTB, + 1809 => Opcode::PSTB8, + 1810 => Opcode::PSTB8nopc, + 1811 => Opcode::PSTB8onlypc, + 1812 => Opcode::PSTB8pc, + 1813 => Opcode::PSTBnopc, + 1814 => Opcode::PSTBonlypc, + 1815 => Opcode::PSTBpc, + 1816 => Opcode::PSTD, + 1817 => Opcode::PSTDnopc, + 1818 => Opcode::PSTDonlypc, + 1819 => Opcode::PSTDpc, + 1820 => Opcode::PSTFD, + 1821 => Opcode::PSTFDnopc, + 1822 => Opcode::PSTFDonlypc, + 1823 => Opcode::PSTFDpc, + 1824 => Opcode::PSTFS, + 1825 => Opcode::PSTFSnopc, + 1826 => Opcode::PSTFSonlypc, + 1827 => Opcode::PSTFSpc, + 1828 => Opcode::PSTH, + 1829 => Opcode::PSTH8, + 1830 => Opcode::PSTH8nopc, + 1831 => Opcode::PSTH8onlypc, + 1832 => Opcode::PSTH8pc, + 1833 => Opcode::PSTHnopc, + 1834 => Opcode::PSTHonlypc, + 1835 => Opcode::PSTHpc, + 1836 => Opcode::PSTW, + 1837 => Opcode::PSTW8, + 1838 => Opcode::PSTW8nopc, + 1839 => Opcode::PSTW8onlypc, + 1840 => Opcode::PSTW8pc, + 1841 => Opcode::PSTWnopc, + 1842 => Opcode::PSTWonlypc, + 1843 => Opcode::PSTWpc, + 1844 => Opcode::PSTXSD, + 1845 => Opcode::PSTXSDnopc, + 1846 => Opcode::PSTXSDonlypc, + 1847 => Opcode::PSTXSDpc, + 1848 => Opcode::PSTXSSP, + 1849 => Opcode::PSTXSSPnopc, + 1850 => Opcode::PSTXSSPonlypc, + 1851 => Opcode::PSTXSSPpc, + 1852 => Opcode::PSTXV, + 1853 => Opcode::PSTXVP, + 1854 => Opcode::PSTXVPnopc, + 1855 => Opcode::PSTXVPonlypc, + 1856 => Opcode::PSTXVPpc, + 1857 => Opcode::PSTXVnopc, + 1858 => Opcode::PSTXVonlypc, + 1859 => Opcode::PSTXVpc, + 1860 => Opcode::PTESYNCIO, + 1861 => Opcode::PseudoEIEIO, + 1862 => Opcode::RESTORE_ACC, + 1863 => Opcode::RESTORE_CR, + 1864 => Opcode::RESTORE_CRBIT, + 1865 => Opcode::RESTORE_DMR, + 1866 => Opcode::RESTORE_DMRP, + 1867 => Opcode::RESTORE_QUADWORD, + 1868 => Opcode::RESTORE_UACC, + 1869 => Opcode::RESTORE_WACC, + 1870 => Opcode::RFCI, + 1871 => Opcode::RFDI, + 1872 => Opcode::RFEBB, + 1873 => Opcode::RFI, + 1874 => Opcode::RFID, + 1875 => Opcode::RFMCI, + 1876 => Opcode::RLDCL, + 1877 => Opcode::RLDCL_rec, + 1878 => Opcode::RLDCR, + 1879 => Opcode::RLDCR_rec, + 1880 => Opcode::RLDIC, + 1881 => Opcode::RLDICL, + 1882 => Opcode::RLDICL_32, + 1883 => Opcode::RLDICL_32_64, + 1884 => Opcode::RLDICL_32_rec, + 1885 => Opcode::RLDICL_rec, + 1886 => Opcode::RLDICR, + 1887 => Opcode::RLDICR_32, + 1888 => Opcode::RLDICR_rec, + 1889 => Opcode::RLDIC_rec, + 1890 => Opcode::RLDIMI, + 1891 => Opcode::RLDIMI_rec, + 1892 => Opcode::RLWIMI, + 1893 => Opcode::RLWIMI8, + 1894 => Opcode::RLWIMI8_rec, + 1895 => Opcode::RLWIMI_rec, + 1896 => Opcode::RLWINM, + 1897 => Opcode::RLWINM8, + 1898 => Opcode::RLWINM8_rec, + 1899 => Opcode::RLWINM_rec, + 1900 => Opcode::RLWNM, + 1901 => Opcode::RLWNM8, + 1902 => Opcode::RLWNM8_rec, + 1903 => Opcode::RLWNM_rec, + 1904 => Opcode::ReadTB, + 1905 => Opcode::SC, + 1906 => Opcode::SCV, + 1907 => Opcode::SELECT_CC_F16, + 1908 => Opcode::SELECT_CC_F4, + 1909 => Opcode::SELECT_CC_F8, + 1910 => Opcode::SELECT_CC_I4, + 1911 => Opcode::SELECT_CC_I8, + 1912 => Opcode::SELECT_CC_SPE, + 1913 => Opcode::SELECT_CC_SPE4, + 1914 => Opcode::SELECT_CC_VRRC, + 1915 => Opcode::SELECT_CC_VSFRC, + 1916 => Opcode::SELECT_CC_VSRC, + 1917 => Opcode::SELECT_CC_VSSRC, + 1918 => Opcode::SELECT_F16, + 1919 => Opcode::SELECT_F4, + 1920 => Opcode::SELECT_F8, + 1921 => Opcode::SELECT_I4, + 1922 => Opcode::SELECT_I8, + 1923 => Opcode::SELECT_SPE, + 1924 => Opcode::SELECT_SPE4, + 1925 => Opcode::SELECT_VRRC, + 1926 => Opcode::SELECT_VSFRC, + 1927 => Opcode::SELECT_VSRC, + 1928 => Opcode::SELECT_VSSRC, + 1929 => Opcode::SETB, + 1930 => Opcode::SETB8, + 1931 => Opcode::SETBC, + 1932 => Opcode::SETBC8, + 1933 => Opcode::SETBCR, + 1934 => Opcode::SETBCR8, + 1935 => Opcode::SETFLM, + 1936 => Opcode::SETNBC, + 1937 => Opcode::SETNBC8, + 1938 => Opcode::SETNBCR, + 1939 => Opcode::SETNBCR8, + 1940 => Opcode::SETRND, + 1941 => Opcode::SETRNDi, + 1942 => Opcode::SLBFEE_rec, + 1943 => Opcode::SLBIA, + 1944 => Opcode::SLBIE, + 1945 => Opcode::SLBIEG, + 1946 => Opcode::SLBMFEE, + 1947 => Opcode::SLBMFEV, + 1948 => Opcode::SLBMTE, + 1949 => Opcode::SLBSYNC, + 1950 => Opcode::SLD, + 1951 => Opcode::SLD_rec, + 1952 => Opcode::SLW, + 1953 => Opcode::SLW8, + 1954 => Opcode::SLW8_rec, + 1955 => Opcode::SLW_rec, + 1956 => Opcode::SPELWZ, + 1957 => Opcode::SPELWZX, + 1958 => Opcode::SPESTW, + 1959 => Opcode::SPESTWX, + 1960 => Opcode::SPILL_ACC, + 1961 => Opcode::SPILL_CR, + 1962 => Opcode::SPILL_CRBIT, + 1963 => Opcode::SPILL_DMR, + 1964 => Opcode::SPILL_DMRP, + 1965 => Opcode::SPILL_QUADWORD, + 1966 => Opcode::SPILL_UACC, + 1967 => Opcode::SPILL_WACC, + 1968 => Opcode::SPLIT_QUADWORD, + 1969 => Opcode::SRAD, + 1970 => Opcode::SRADI, + 1971 => Opcode::SRADI_32, + 1972 => Opcode::SRADI_rec, + 1973 => Opcode::SRAD_rec, + 1974 => Opcode::SRAW, + 1975 => Opcode::SRAW8, + 1976 => Opcode::SRAW8_rec, + 1977 => Opcode::SRAWI, + 1978 => Opcode::SRAWI8, + 1979 => Opcode::SRAWI8_rec, + 1980 => Opcode::SRAWI_rec, + 1981 => Opcode::SRAW_rec, + 1982 => Opcode::SRD, + 1983 => Opcode::SRD_rec, + 1984 => Opcode::SRW, + 1985 => Opcode::SRW8, + 1986 => Opcode::SRW8_rec, + 1987 => Opcode::SRW_rec, + 1988 => Opcode::STB, + 1989 => Opcode::STB8, + 1990 => Opcode::STBCIX, + 1991 => Opcode::STBCX, + 1992 => Opcode::STBEPX, + 1993 => Opcode::STBU, + 1994 => Opcode::STBU8, + 1995 => Opcode::STBUX, + 1996 => Opcode::STBUX8, + 1997 => Opcode::STBX, + 1998 => Opcode::STBX8, + 1999 => Opcode::STBXTLS, + 2000 => Opcode::STBXTLS_, + 2001 => Opcode::STBXTLS_32, + 2002 => Opcode::STD, + 2003 => Opcode::STDAT, + 2004 => Opcode::STDBRX, + 2005 => Opcode::STDCIX, + 2006 => Opcode::STDCX, + 2007 => Opcode::STDU, + 2008 => Opcode::STDUX, + 2009 => Opcode::STDX, + 2010 => Opcode::STDXTLS, + 2011 => Opcode::STDXTLS_, + 2012 => Opcode::STFD, + 2013 => Opcode::STFDEPX, + 2014 => Opcode::STFDU, + 2015 => Opcode::STFDUX, + 2016 => Opcode::STFDX, + 2017 => Opcode::STFDXTLS, + 2018 => Opcode::STFDXTLS_, + 2019 => Opcode::STFIWX, + 2020 => Opcode::STFS, + 2021 => Opcode::STFSU, + 2022 => Opcode::STFSUX, + 2023 => Opcode::STFSX, + 2024 => Opcode::STFSXTLS, + 2025 => Opcode::STFSXTLS_, + 2026 => Opcode::STH, + 2027 => Opcode::STH8, + 2028 => Opcode::STHBRX, + 2029 => Opcode::STHCIX, + 2030 => Opcode::STHCX, + 2031 => Opcode::STHEPX, + 2032 => Opcode::STHU, + 2033 => Opcode::STHU8, + 2034 => Opcode::STHUX, + 2035 => Opcode::STHUX8, + 2036 => Opcode::STHX, + 2037 => Opcode::STHX8, + 2038 => Opcode::STHXTLS, + 2039 => Opcode::STHXTLS_, + 2040 => Opcode::STHXTLS_32, + 2041 => Opcode::STMW, + 2042 => Opcode::STOP, + 2043 => Opcode::STQ, + 2044 => Opcode::STQCX, + 2045 => Opcode::STQX_PSEUDO, + 2046 => Opcode::STSWI, + 2047 => Opcode::STVEBX, + 2048 => Opcode::STVEHX, + 2049 => Opcode::STVEWX, + 2050 => Opcode::STVX, + 2051 => Opcode::STVXL, + 2052 => Opcode::STW, + 2053 => Opcode::STW8, + 2054 => Opcode::STWAT, + 2055 => Opcode::STWBRX, + 2056 => Opcode::STWCIX, + 2057 => Opcode::STWCX, + 2058 => Opcode::STWEPX, + 2059 => Opcode::STWU, + 2060 => Opcode::STWU8, + 2061 => Opcode::STWUX, + 2062 => Opcode::STWUX8, + 2063 => Opcode::STWX, + 2064 => Opcode::STWX8, + 2065 => Opcode::STWXTLS, + 2066 => Opcode::STWXTLS_, + 2067 => Opcode::STWXTLS_32, + 2068 => Opcode::STXSD, + 2069 => Opcode::STXSDX, + 2070 => Opcode::STXSIBX, + 2071 => Opcode::STXSIBXv, + 2072 => Opcode::STXSIHX, + 2073 => Opcode::STXSIHXv, + 2074 => Opcode::STXSIWX, + 2075 => Opcode::STXSSP, + 2076 => Opcode::STXSSPX, + 2077 => Opcode::STXV, + 2078 => Opcode::STXVB16X, + 2079 => Opcode::STXVD2X, + 2080 => Opcode::STXVH8X, + 2081 => Opcode::STXVL, + 2082 => Opcode::STXVLL, + 2083 => Opcode::STXVP, + 2084 => Opcode::STXVPB32X, + 2085 => Opcode::STXVPRL, + 2086 => Opcode::STXVPRLL, + 2087 => Opcode::STXVPX, + 2088 => Opcode::STXVRBX, + 2089 => Opcode::STXVRDX, + 2090 => Opcode::STXVRHX, + 2091 => Opcode::STXVRL, + 2092 => Opcode::STXVRLL, + 2093 => Opcode::STXVRWX, + 2094 => Opcode::STXVW4X, + 2095 => Opcode::STXVX, + 2096 => Opcode::SUBF, + 2097 => Opcode::SUBF8, + 2098 => Opcode::SUBF8O, + 2099 => Opcode::SUBF8O_rec, + 2100 => Opcode::SUBF8_rec, + 2101 => Opcode::SUBFC, + 2102 => Opcode::SUBFC8, + 2103 => Opcode::SUBFC8O, + 2104 => Opcode::SUBFC8O_rec, + 2105 => Opcode::SUBFC8_rec, + 2106 => Opcode::SUBFCO, + 2107 => Opcode::SUBFCO_rec, + 2108 => Opcode::SUBFC_rec, + 2109 => Opcode::SUBFE, + 2110 => Opcode::SUBFE8, + 2111 => Opcode::SUBFE8O, + 2112 => Opcode::SUBFE8O_rec, + 2113 => Opcode::SUBFE8_rec, + 2114 => Opcode::SUBFEO, + 2115 => Opcode::SUBFEO_rec, + 2116 => Opcode::SUBFE_rec, + 2117 => Opcode::SUBFIC, + 2118 => Opcode::SUBFIC8, + 2119 => Opcode::SUBFME, + 2120 => Opcode::SUBFME8, + 2121 => Opcode::SUBFME8O, + 2122 => Opcode::SUBFME8O_rec, + 2123 => Opcode::SUBFME8_rec, + 2124 => Opcode::SUBFMEO, + 2125 => Opcode::SUBFMEO_rec, + 2126 => Opcode::SUBFME_rec, + 2127 => Opcode::SUBFO, + 2128 => Opcode::SUBFO_rec, + 2129 => Opcode::SUBFUS, + 2130 => Opcode::SUBFUS_rec, + 2131 => Opcode::SUBFZE, + 2132 => Opcode::SUBFZE8, + 2133 => Opcode::SUBFZE8O, + 2134 => Opcode::SUBFZE8O_rec, + 2135 => Opcode::SUBFZE8_rec, + 2136 => Opcode::SUBFZEO, + 2137 => Opcode::SUBFZEO_rec, + 2138 => Opcode::SUBFZE_rec, + 2139 => Opcode::SUBF_rec, + 2140 => Opcode::SYNC, + 2141 => Opcode::SYNCP10, + 2142 => Opcode::TABORT, + 2143 => Opcode::TABORTDC, + 2144 => Opcode::TABORTDCI, + 2145 => Opcode::TABORTWC, + 2146 => Opcode::TABORTWCI, + 2147 => Opcode::TAILB, + 2148 => Opcode::TAILB8, + 2149 => Opcode::TAILBA, + 2150 => Opcode::TAILBA8, + 2151 => Opcode::TAILBCTR, + 2152 => Opcode::TAILBCTR8, + 2153 => Opcode::TBEGIN, + 2154 => Opcode::TBEGIN_RET, + 2155 => Opcode::TCHECK, + 2156 => Opcode::TCHECK_RET, + 2157 => Opcode::TCRETURNai, + 2158 => Opcode::TCRETURNai8, + 2159 => Opcode::TCRETURNdi, + 2160 => Opcode::TCRETURNdi8, + 2161 => Opcode::TCRETURNri, + 2162 => Opcode::TCRETURNri8, + 2163 => Opcode::TD, + 2164 => Opcode::TDI, + 2165 => Opcode::TEND, + 2166 => Opcode::TLBIA, + 2167 => Opcode::TLBIE, + 2168 => Opcode::TLBIE8P9, + 2169 => Opcode::TLBIEIO, + 2170 => Opcode::TLBIEL, + 2171 => Opcode::TLBIEP, + 2172 => Opcode::TLBIEP8, + 2173 => Opcode::TLBIEP9, + 2174 => Opcode::TLBILX, + 2175 => Opcode::TLBIVAX, + 2176 => Opcode::TLBLD, + 2177 => Opcode::TLBLI, + 2178 => Opcode::TLBRE, + 2179 => Opcode::TLBRE2, + 2180 => Opcode::TLBSX, + 2181 => Opcode::TLBSX2, + 2182 => Opcode::TLBSX2D, + 2183 => Opcode::TLBSYNC, + 2184 => Opcode::TLBSYNCIO, + 2185 => Opcode::TLBWE, + 2186 => Opcode::TLBWE2, + 2187 => Opcode::TLSGDAIX, + 2188 => Opcode::TLSGDAIX8, + 2189 => Opcode::TLSLDAIX, + 2190 => Opcode::TLSLDAIX8, + 2191 => Opcode::TRAP, + 2192 => Opcode::TRECHKPT, + 2193 => Opcode::TRECLAIM, + 2194 => Opcode::TSR, + 2195 => Opcode::TW, + 2196 => Opcode::TWI, + 2197 => Opcode::UNENCODED_NOP, + 2198 => Opcode::UpdateGBR, + 2199 => Opcode::VABSDUB, + 2200 => Opcode::VABSDUH, + 2201 => Opcode::VABSDUW, + 2202 => Opcode::VADDCUQ, + 2203 => Opcode::VADDCUW, + 2204 => Opcode::VADDECUQ, + 2205 => Opcode::VADDEUQM, + 2206 => Opcode::VADDFP, + 2207 => Opcode::VADDSBS, + 2208 => Opcode::VADDSHS, + 2209 => Opcode::VADDSWS, + 2210 => Opcode::VADDUBM, + 2211 => Opcode::VADDUBS, + 2212 => Opcode::VADDUDM, + 2213 => Opcode::VADDUHM, + 2214 => Opcode::VADDUHS, + 2215 => Opcode::VADDUQM, + 2216 => Opcode::VADDUWM, + 2217 => Opcode::VADDUWS, + 2218 => Opcode::VAND, + 2219 => Opcode::VANDC, + 2220 => Opcode::VAVGSB, + 2221 => Opcode::VAVGSH, + 2222 => Opcode::VAVGSW, + 2223 => Opcode::VAVGUB, + 2224 => Opcode::VAVGUH, + 2225 => Opcode::VAVGUW, + 2226 => Opcode::VBPERMD, + 2227 => Opcode::VBPERMQ, + 2228 => Opcode::VCFSX, + 2229 => Opcode::VCFSX_0, + 2230 => Opcode::VCFUGED, + 2231 => Opcode::VCFUX, + 2232 => Opcode::VCFUX_0, + 2233 => Opcode::VCIPHER, + 2234 => Opcode::VCIPHERLAST, + 2235 => Opcode::VCLRLB, + 2236 => Opcode::VCLRRB, + 2237 => Opcode::VCLZB, + 2238 => Opcode::VCLZD, + 2239 => Opcode::VCLZDM, + 2240 => Opcode::VCLZH, + 2241 => Opcode::VCLZLSBB, + 2242 => Opcode::VCLZW, + 2243 => Opcode::VCMPBFP, + 2244 => Opcode::VCMPBFP_rec, + 2245 => Opcode::VCMPEQFP, + 2246 => Opcode::VCMPEQFP_rec, + 2247 => Opcode::VCMPEQUB, + 2248 => Opcode::VCMPEQUB_rec, + 2249 => Opcode::VCMPEQUD, + 2250 => Opcode::VCMPEQUD_rec, + 2251 => Opcode::VCMPEQUH, + 2252 => Opcode::VCMPEQUH_rec, + 2253 => Opcode::VCMPEQUQ, + 2254 => Opcode::VCMPEQUQ_rec, + 2255 => Opcode::VCMPEQUW, + 2256 => Opcode::VCMPEQUW_rec, + 2257 => Opcode::VCMPGEFP, + 2258 => Opcode::VCMPGEFP_rec, + 2259 => Opcode::VCMPGTFP, + 2260 => Opcode::VCMPGTFP_rec, + 2261 => Opcode::VCMPGTSB, + 2262 => Opcode::VCMPGTSB_rec, + 2263 => Opcode::VCMPGTSD, + 2264 => Opcode::VCMPGTSD_rec, + 2265 => Opcode::VCMPGTSH, + 2266 => Opcode::VCMPGTSH_rec, + 2267 => Opcode::VCMPGTSQ, + 2268 => Opcode::VCMPGTSQ_rec, + 2269 => Opcode::VCMPGTSW, + 2270 => Opcode::VCMPGTSW_rec, + 2271 => Opcode::VCMPGTUB, + 2272 => Opcode::VCMPGTUB_rec, + 2273 => Opcode::VCMPGTUD, + 2274 => Opcode::VCMPGTUD_rec, + 2275 => Opcode::VCMPGTUH, + 2276 => Opcode::VCMPGTUH_rec, + 2277 => Opcode::VCMPGTUQ, + 2278 => Opcode::VCMPGTUQ_rec, + 2279 => Opcode::VCMPGTUW, + 2280 => Opcode::VCMPGTUW_rec, + 2281 => Opcode::VCMPNEB, + 2282 => Opcode::VCMPNEB_rec, + 2283 => Opcode::VCMPNEH, + 2284 => Opcode::VCMPNEH_rec, + 2285 => Opcode::VCMPNEW, + 2286 => Opcode::VCMPNEW_rec, + 2287 => Opcode::VCMPNEZB, + 2288 => Opcode::VCMPNEZB_rec, + 2289 => Opcode::VCMPNEZH, + 2290 => Opcode::VCMPNEZH_rec, + 2291 => Opcode::VCMPNEZW, + 2292 => Opcode::VCMPNEZW_rec, + 2293 => Opcode::VCMPSQ, + 2294 => Opcode::VCMPUQ, + 2295 => Opcode::VCNTMBB, + 2296 => Opcode::VCNTMBD, + 2297 => Opcode::VCNTMBH, + 2298 => Opcode::VCNTMBW, + 2299 => Opcode::VCTSXS, + 2300 => Opcode::VCTSXS_0, + 2301 => Opcode::VCTUXS, + 2302 => Opcode::VCTUXS_0, + 2303 => Opcode::VCTZB, + 2304 => Opcode::VCTZD, + 2305 => Opcode::VCTZDM, + 2306 => Opcode::VCTZH, + 2307 => Opcode::VCTZLSBB, + 2308 => Opcode::VCTZW, + 2309 => Opcode::VDIVESD, + 2310 => Opcode::VDIVESQ, + 2311 => Opcode::VDIVESW, + 2312 => Opcode::VDIVEUD, + 2313 => Opcode::VDIVEUQ, + 2314 => Opcode::VDIVEUW, + 2315 => Opcode::VDIVSD, + 2316 => Opcode::VDIVSQ, + 2317 => Opcode::VDIVSW, + 2318 => Opcode::VDIVUD, + 2319 => Opcode::VDIVUQ, + 2320 => Opcode::VDIVUW, + 2321 => Opcode::VEQV, + 2322 => Opcode::VEXPANDBM, + 2323 => Opcode::VEXPANDDM, + 2324 => Opcode::VEXPANDHM, + 2325 => Opcode::VEXPANDQM, + 2326 => Opcode::VEXPANDWM, + 2327 => Opcode::VEXPTEFP, + 2328 => Opcode::VEXTDDVLX, + 2329 => Opcode::VEXTDDVRX, + 2330 => Opcode::VEXTDUBVLX, + 2331 => Opcode::VEXTDUBVRX, + 2332 => Opcode::VEXTDUHVLX, + 2333 => Opcode::VEXTDUHVRX, + 2334 => Opcode::VEXTDUWVLX, + 2335 => Opcode::VEXTDUWVRX, + 2336 => Opcode::VEXTRACTBM, + 2337 => Opcode::VEXTRACTD, + 2338 => Opcode::VEXTRACTDM, + 2339 => Opcode::VEXTRACTHM, + 2340 => Opcode::VEXTRACTQM, + 2341 => Opcode::VEXTRACTUB, + 2342 => Opcode::VEXTRACTUH, + 2343 => Opcode::VEXTRACTUW, + 2344 => Opcode::VEXTRACTWM, + 2345 => Opcode::VEXTSB2D, + 2346 => Opcode::VEXTSB2Ds, + 2347 => Opcode::VEXTSB2W, + 2348 => Opcode::VEXTSB2Ws, + 2349 => Opcode::VEXTSD2Q, + 2350 => Opcode::VEXTSH2D, + 2351 => Opcode::VEXTSH2Ds, + 2352 => Opcode::VEXTSH2W, + 2353 => Opcode::VEXTSH2Ws, + 2354 => Opcode::VEXTSW2D, + 2355 => Opcode::VEXTSW2Ds, + 2356 => Opcode::VEXTUBLX, + 2357 => Opcode::VEXTUBRX, + 2358 => Opcode::VEXTUHLX, + 2359 => Opcode::VEXTUHRX, + 2360 => Opcode::VEXTUWLX, + 2361 => Opcode::VEXTUWRX, + 2362 => Opcode::VGBBD, + 2363 => Opcode::VGNB, + 2364 => Opcode::VINSBLX, + 2365 => Opcode::VINSBRX, + 2366 => Opcode::VINSBVLX, + 2367 => Opcode::VINSBVRX, + 2368 => Opcode::VINSD, + 2369 => Opcode::VINSDLX, + 2370 => Opcode::VINSDRX, + 2371 => Opcode::VINSERTB, + 2372 => Opcode::VINSERTD, + 2373 => Opcode::VINSERTH, + 2374 => Opcode::VINSERTW, + 2375 => Opcode::VINSHLX, + 2376 => Opcode::VINSHRX, + 2377 => Opcode::VINSHVLX, + 2378 => Opcode::VINSHVRX, + 2379 => Opcode::VINSW, + 2380 => Opcode::VINSWLX, + 2381 => Opcode::VINSWRX, + 2382 => Opcode::VINSWVLX, + 2383 => Opcode::VINSWVRX, + 2384 => Opcode::VLOGEFP, + 2385 => Opcode::VMADDFP, + 2386 => Opcode::VMAXFP, + 2387 => Opcode::VMAXSB, + 2388 => Opcode::VMAXSD, + 2389 => Opcode::VMAXSH, + 2390 => Opcode::VMAXSW, + 2391 => Opcode::VMAXUB, + 2392 => Opcode::VMAXUD, + 2393 => Opcode::VMAXUH, + 2394 => Opcode::VMAXUW, + 2395 => Opcode::VMHADDSHS, + 2396 => Opcode::VMHRADDSHS, + 2397 => Opcode::VMINFP, + 2398 => Opcode::VMINSB, + 2399 => Opcode::VMINSD, + 2400 => Opcode::VMINSH, + 2401 => Opcode::VMINSW, + 2402 => Opcode::VMINUB, + 2403 => Opcode::VMINUD, + 2404 => Opcode::VMINUH, + 2405 => Opcode::VMINUW, + 2406 => Opcode::VMLADDUHM, + 2407 => Opcode::VMODSD, + 2408 => Opcode::VMODSQ, + 2409 => Opcode::VMODSW, + 2410 => Opcode::VMODUD, + 2411 => Opcode::VMODUQ, + 2412 => Opcode::VMODUW, + 2413 => Opcode::VMRGEW, + 2414 => Opcode::VMRGHB, + 2415 => Opcode::VMRGHH, + 2416 => Opcode::VMRGHW, + 2417 => Opcode::VMRGLB, + 2418 => Opcode::VMRGLH, + 2419 => Opcode::VMRGLW, + 2420 => Opcode::VMRGOW, + 2421 => Opcode::VMSUMCUD, + 2422 => Opcode::VMSUMMBM, + 2423 => Opcode::VMSUMSHM, + 2424 => Opcode::VMSUMSHS, + 2425 => Opcode::VMSUMUBM, + 2426 => Opcode::VMSUMUDM, + 2427 => Opcode::VMSUMUHM, + 2428 => Opcode::VMSUMUHS, + 2429 => Opcode::VMUL10CUQ, + 2430 => Opcode::VMUL10ECUQ, + 2431 => Opcode::VMUL10EUQ, + 2432 => Opcode::VMUL10UQ, + 2433 => Opcode::VMULESB, + 2434 => Opcode::VMULESD, + 2435 => Opcode::VMULESH, + 2436 => Opcode::VMULESW, + 2437 => Opcode::VMULEUB, + 2438 => Opcode::VMULEUD, + 2439 => Opcode::VMULEUH, + 2440 => Opcode::VMULEUW, + 2441 => Opcode::VMULHSD, + 2442 => Opcode::VMULHSW, + 2443 => Opcode::VMULHUD, + 2444 => Opcode::VMULHUW, + 2445 => Opcode::VMULLD, + 2446 => Opcode::VMULOSB, + 2447 => Opcode::VMULOSD, + 2448 => Opcode::VMULOSH, + 2449 => Opcode::VMULOSW, + 2450 => Opcode::VMULOUB, + 2451 => Opcode::VMULOUD, + 2452 => Opcode::VMULOUH, + 2453 => Opcode::VMULOUW, + 2454 => Opcode::VMULUWM, + 2455 => Opcode::VNAND, + 2456 => Opcode::VNCIPHER, + 2457 => Opcode::VNCIPHERLAST, + 2458 => Opcode::VNEGD, + 2459 => Opcode::VNEGW, + 2460 => Opcode::VNMSUBFP, + 2461 => Opcode::VNOR, + 2462 => Opcode::VOR, + 2463 => Opcode::VORC, + 2464 => Opcode::VPDEPD, + 2465 => Opcode::VPERM, + 2466 => Opcode::VPERMR, + 2467 => Opcode::VPERMXOR, + 2468 => Opcode::VPEXTD, + 2469 => Opcode::VPKPX, + 2470 => Opcode::VPKSDSS, + 2471 => Opcode::VPKSDUS, + 2472 => Opcode::VPKSHSS, + 2473 => Opcode::VPKSHUS, + 2474 => Opcode::VPKSWSS, + 2475 => Opcode::VPKSWUS, + 2476 => Opcode::VPKUDUM, + 2477 => Opcode::VPKUDUS, + 2478 => Opcode::VPKUHUM, + 2479 => Opcode::VPKUHUS, + 2480 => Opcode::VPKUWUM, + 2481 => Opcode::VPKUWUS, + 2482 => Opcode::VPMSUMB, + 2483 => Opcode::VPMSUMD, + 2484 => Opcode::VPMSUMH, + 2485 => Opcode::VPMSUMW, + 2486 => Opcode::VPOPCNTB, + 2487 => Opcode::VPOPCNTD, + 2488 => Opcode::VPOPCNTH, + 2489 => Opcode::VPOPCNTW, + 2490 => Opcode::VPRTYBD, + 2491 => Opcode::VPRTYBQ, + 2492 => Opcode::VPRTYBW, + 2493 => Opcode::VREFP, + 2494 => Opcode::VRFIM, + 2495 => Opcode::VRFIN, + 2496 => Opcode::VRFIP, + 2497 => Opcode::VRFIZ, + 2498 => Opcode::VRLB, + 2499 => Opcode::VRLD, + 2500 => Opcode::VRLDMI, + 2501 => Opcode::VRLDNM, + 2502 => Opcode::VRLH, + 2503 => Opcode::VRLQ, + 2504 => Opcode::VRLQMI, + 2505 => Opcode::VRLQNM, + 2506 => Opcode::VRLW, + 2507 => Opcode::VRLWMI, + 2508 => Opcode::VRLWNM, + 2509 => Opcode::VRSQRTEFP, + 2510 => Opcode::VSBOX, + 2511 => Opcode::VSEL, + 2512 => Opcode::VSHASIGMAD, + 2513 => Opcode::VSHASIGMAW, + 2514 => Opcode::VSL, + 2515 => Opcode::VSLB, + 2516 => Opcode::VSLD, + 2517 => Opcode::VSLDBI, + 2518 => Opcode::VSLDOI, + 2519 => Opcode::VSLH, + 2520 => Opcode::VSLO, + 2521 => Opcode::VSLQ, + 2522 => Opcode::VSLV, + 2523 => Opcode::VSLW, + 2524 => Opcode::VSPLTB, + 2525 => Opcode::VSPLTBs, + 2526 => Opcode::VSPLTH, + 2527 => Opcode::VSPLTHs, + 2528 => Opcode::VSPLTISB, + 2529 => Opcode::VSPLTISH, + 2530 => Opcode::VSPLTISW, + 2531 => Opcode::VSPLTW, + 2532 => Opcode::VSR, + 2533 => Opcode::VSRAB, + 2534 => Opcode::VSRAD, + 2535 => Opcode::VSRAH, + 2536 => Opcode::VSRAQ, + 2537 => Opcode::VSRAW, + 2538 => Opcode::VSRB, + 2539 => Opcode::VSRD, + 2540 => Opcode::VSRDBI, + 2541 => Opcode::VSRH, + 2542 => Opcode::VSRO, + 2543 => Opcode::VSRQ, + 2544 => Opcode::VSRV, + 2545 => Opcode::VSRW, + 2546 => Opcode::VSTRIBL, + 2547 => Opcode::VSTRIBL_rec, + 2548 => Opcode::VSTRIBR, + 2549 => Opcode::VSTRIBR_rec, + 2550 => Opcode::VSTRIHL, + 2551 => Opcode::VSTRIHL_rec, + 2552 => Opcode::VSTRIHR, + 2553 => Opcode::VSTRIHR_rec, + 2554 => Opcode::VSUBCUQ, + 2555 => Opcode::VSUBCUW, + 2556 => Opcode::VSUBECUQ, + 2557 => Opcode::VSUBEUQM, + 2558 => Opcode::VSUBFP, + 2559 => Opcode::VSUBSBS, + 2560 => Opcode::VSUBSHS, + 2561 => Opcode::VSUBSWS, + 2562 => Opcode::VSUBUBM, + 2563 => Opcode::VSUBUBS, + 2564 => Opcode::VSUBUDM, + 2565 => Opcode::VSUBUHM, + 2566 => Opcode::VSUBUHS, + 2567 => Opcode::VSUBUQM, + 2568 => Opcode::VSUBUWM, + 2569 => Opcode::VSUBUWS, + 2570 => Opcode::VSUM2SWS, + 2571 => Opcode::VSUM4SBS, + 2572 => Opcode::VSUM4SHS, + 2573 => Opcode::VSUM4UBS, + 2574 => Opcode::VSUMSWS, + 2575 => Opcode::VUCMPRHB, + 2576 => Opcode::VUCMPRHH, + 2577 => Opcode::VUCMPRHN, + 2578 => Opcode::VUCMPRLB, + 2579 => Opcode::VUCMPRLH, + 2580 => Opcode::VUCMPRLN, + 2581 => Opcode::VUPKHPX, + 2582 => Opcode::VUPKHSB, + 2583 => Opcode::VUPKHSH, + 2584 => Opcode::VUPKHSNTOB, + 2585 => Opcode::VUPKHSW, + 2586 => Opcode::VUPKINT4TOBF16, + 2587 => Opcode::VUPKINT4TOFP32, + 2588 => Opcode::VUPKINT8TOBF16, + 2589 => Opcode::VUPKINT8TOFP32, + 2590 => Opcode::VUPKLPX, + 2591 => Opcode::VUPKLSB, + 2592 => Opcode::VUPKLSH, + 2593 => Opcode::VUPKLSNTOB, + 2594 => Opcode::VUPKLSW, + 2595 => Opcode::VXOR, + 2596 => Opcode::V_SET0, + 2597 => Opcode::V_SET0B, + 2598 => Opcode::V_SET0H, + 2599 => Opcode::V_SETALLONES, + 2600 => Opcode::V_SETALLONESB, + 2601 => Opcode::V_SETALLONESH, + 2602 => Opcode::WAIT, + 2603 => Opcode::WAITP10, + 2604 => Opcode::WRTEE, + 2605 => Opcode::WRTEEI, + 2606 => Opcode::XOR, + 2607 => Opcode::XOR8, + 2608 => Opcode::XOR8_rec, + 2609 => Opcode::XORI, + 2610 => Opcode::XORI8, + 2611 => Opcode::XORIS, + 2612 => Opcode::XORIS8, + 2613 => Opcode::XOR_rec, + 2614 => Opcode::XSABSDP, + 2615 => Opcode::XSABSQP, + 2616 => Opcode::XSADDADDSUQM, + 2617 => Opcode::XSADDADDUQM, + 2618 => Opcode::XSADDDP, + 2619 => Opcode::XSADDQP, + 2620 => Opcode::XSADDQPO, + 2621 => Opcode::XSADDSP, + 2622 => Opcode::XSADDSUBSUQM, + 2623 => Opcode::XSADDSUBUQM, + 2624 => Opcode::XSCMPEQDP, + 2625 => Opcode::XSCMPEQQP, + 2626 => Opcode::XSCMPEXPDP, + 2627 => Opcode::XSCMPEXPQP, + 2628 => Opcode::XSCMPGEDP, + 2629 => Opcode::XSCMPGEQP, + 2630 => Opcode::XSCMPGTDP, + 2631 => Opcode::XSCMPGTQP, + 2632 => Opcode::XSCMPODP, + 2633 => Opcode::XSCMPOQP, + 2634 => Opcode::XSCMPUDP, + 2635 => Opcode::XSCMPUQP, + 2636 => Opcode::XSCPSGNDP, + 2637 => Opcode::XSCPSGNQP, + 2638 => Opcode::XSCVDPHP, + 2639 => Opcode::XSCVDPQP, + 2640 => Opcode::XSCVDPSP, + 2641 => Opcode::XSCVDPSPN, + 2642 => Opcode::XSCVDPSXDS, + 2643 => Opcode::XSCVDPSXDSs, + 2644 => Opcode::XSCVDPSXWS, + 2645 => Opcode::XSCVDPSXWSs, + 2646 => Opcode::XSCVDPUXDS, + 2647 => Opcode::XSCVDPUXDSs, + 2648 => Opcode::XSCVDPUXWS, + 2649 => Opcode::XSCVDPUXWSs, + 2650 => Opcode::XSCVHPDP, + 2651 => Opcode::XSCVQPDP, + 2652 => Opcode::XSCVQPDPO, + 2653 => Opcode::XSCVQPSDZ, + 2654 => Opcode::XSCVQPSQZ, + 2655 => Opcode::XSCVQPSWZ, + 2656 => Opcode::XSCVQPUDZ, + 2657 => Opcode::XSCVQPUQZ, + 2658 => Opcode::XSCVQPUWZ, + 2659 => Opcode::XSCVSDQP, + 2660 => Opcode::XSCVSPDP, + 2661 => Opcode::XSCVSPDPN, + 2662 => Opcode::XSCVSQQP, + 2663 => Opcode::XSCVSXDDP, + 2664 => Opcode::XSCVSXDSP, + 2665 => Opcode::XSCVUDQP, + 2666 => Opcode::XSCVUQQP, + 2667 => Opcode::XSCVUXDDP, + 2668 => Opcode::XSCVUXDSP, + 2669 => Opcode::XSDIVDP, + 2670 => Opcode::XSDIVQP, + 2671 => Opcode::XSDIVQPO, + 2672 => Opcode::XSDIVSP, + 2673 => Opcode::XSIEXPDP, + 2674 => Opcode::XSIEXPQP, + 2675 => Opcode::XSMADDADP, + 2676 => Opcode::XSMADDASP, + 2677 => Opcode::XSMADDMDP, + 2678 => Opcode::XSMADDMSP, + 2679 => Opcode::XSMADDQP, + 2680 => Opcode::XSMADDQPO, + 2681 => Opcode::XSMAXCDP, + 2682 => Opcode::XSMAXCQP, + 2683 => Opcode::XSMAXDP, + 2684 => Opcode::XSMAXJDP, + 2685 => Opcode::XSMERGE2T1UQM, + 2686 => Opcode::XSMERGE2T2UQM, + 2687 => Opcode::XSMERGE2T3UQM, + 2688 => Opcode::XSMERGE3T1UQM, + 2689 => Opcode::XSMINCDP, + 2690 => Opcode::XSMINCQP, + 2691 => Opcode::XSMINDP, + 2692 => Opcode::XSMINJDP, + 2693 => Opcode::XSMSUBADP, + 2694 => Opcode::XSMSUBASP, + 2695 => Opcode::XSMSUBMDP, + 2696 => Opcode::XSMSUBMSP, + 2697 => Opcode::XSMSUBQP, + 2698 => Opcode::XSMSUBQPO, + 2699 => Opcode::XSMULDP, + 2700 => Opcode::XSMULQP, + 2701 => Opcode::XSMULQPO, + 2702 => Opcode::XSMULSP, + 2703 => Opcode::XSNABSDP, + 2704 => Opcode::XSNABSDPs, + 2705 => Opcode::XSNABSQP, + 2706 => Opcode::XSNEGDP, + 2707 => Opcode::XSNEGQP, + 2708 => Opcode::XSNMADDADP, + 2709 => Opcode::XSNMADDASP, + 2710 => Opcode::XSNMADDMDP, + 2711 => Opcode::XSNMADDMSP, + 2712 => Opcode::XSNMADDQP, + 2713 => Opcode::XSNMADDQPO, + 2714 => Opcode::XSNMSUBADP, + 2715 => Opcode::XSNMSUBASP, + 2716 => Opcode::XSNMSUBMDP, + 2717 => Opcode::XSNMSUBMSP, + 2718 => Opcode::XSNMSUBQP, + 2719 => Opcode::XSNMSUBQPO, + 2720 => Opcode::XSRDPI, + 2721 => Opcode::XSRDPIC, + 2722 => Opcode::XSRDPIM, + 2723 => Opcode::XSRDPIP, + 2724 => Opcode::XSRDPIZ, + 2725 => Opcode::XSREBASE2T1UQM, + 2726 => Opcode::XSREBASE2T2UQM, + 2727 => Opcode::XSREBASE2T3UQM, + 2728 => Opcode::XSREBASE2T4UQM, + 2729 => Opcode::XSREBASE3T1UQM, + 2730 => Opcode::XSREBASE3T2UQM, + 2731 => Opcode::XSREBASE3T3UQM, + 2732 => Opcode::XSREDP, + 2733 => Opcode::XSRESP, + 2734 => Opcode::XSRQPI, + 2735 => Opcode::XSRQPIX, + 2736 => Opcode::XSRQPXP, + 2737 => Opcode::XSRSP, + 2738 => Opcode::XSRSQRTEDP, + 2739 => Opcode::XSRSQRTESP, + 2740 => Opcode::XSSQRTDP, + 2741 => Opcode::XSSQRTQP, + 2742 => Opcode::XSSQRTQPO, + 2743 => Opcode::XSSQRTSP, + 2744 => Opcode::XSSUBDP, + 2745 => Opcode::XSSUBQP, + 2746 => Opcode::XSSUBQPO, + 2747 => Opcode::XSSUBSP, + 2748 => Opcode::XSTDIVDP, + 2749 => Opcode::XSTSQRTDP, + 2750 => Opcode::XSTSTDCDP, + 2751 => Opcode::XSTSTDCQP, + 2752 => Opcode::XSTSTDCSP, + 2753 => Opcode::XSXEXPDP, + 2754 => Opcode::XSXEXPQP, + 2755 => Opcode::XSXSIGDP, + 2756 => Opcode::XSXSIGQP, + 2757 => Opcode::XVABSDP, + 2758 => Opcode::XVABSSP, + 2759 => Opcode::XVADDDP, + 2760 => Opcode::XVADDSP, + 2761 => Opcode::XVADDUHM, + 2762 => Opcode::XVADDUWM, + 2763 => Opcode::XVBF16GER2, + 2764 => Opcode::XVBF16GER2NN, + 2765 => Opcode::XVBF16GER2NP, + 2766 => Opcode::XVBF16GER2PN, + 2767 => Opcode::XVBF16GER2PP, + 2768 => Opcode::XVBF16GER2W, + 2769 => Opcode::XVBF16GER2WNN, + 2770 => Opcode::XVBF16GER2WNP, + 2771 => Opcode::XVBF16GER2WPN, + 2772 => Opcode::XVBF16GER2WPP, + 2773 => Opcode::XVCMPEQDP, + 2774 => Opcode::XVCMPEQDP_rec, + 2775 => Opcode::XVCMPEQSP, + 2776 => Opcode::XVCMPEQSP_rec, + 2777 => Opcode::XVCMPGEDP, + 2778 => Opcode::XVCMPGEDP_rec, + 2779 => Opcode::XVCMPGESP, + 2780 => Opcode::XVCMPGESP_rec, + 2781 => Opcode::XVCMPGTDP, + 2782 => Opcode::XVCMPGTDP_rec, + 2783 => Opcode::XVCMPGTSP, + 2784 => Opcode::XVCMPGTSP_rec, + 2785 => Opcode::XVCPSGNDP, + 2786 => Opcode::XVCPSGNSP, + 2787 => Opcode::XVCVBF16SPN, + 2788 => Opcode::XVCVDPSP, + 2789 => Opcode::XVCVDPSXDS, + 2790 => Opcode::XVCVDPSXWS, + 2791 => Opcode::XVCVDPUXDS, + 2792 => Opcode::XVCVDPUXWS, + 2793 => Opcode::XVCVHPSP, + 2794 => Opcode::XVCVSPBF16, + 2795 => Opcode::XVCVSPDP, + 2796 => Opcode::XVCVSPHP, + 2797 => Opcode::XVCVSPSXDS, + 2798 => Opcode::XVCVSPSXWS, + 2799 => Opcode::XVCVSPUXDS, + 2800 => Opcode::XVCVSPUXWS, + 2801 => Opcode::XVCVSXDDP, + 2802 => Opcode::XVCVSXDSP, + 2803 => Opcode::XVCVSXWDP, + 2804 => Opcode::XVCVSXWSP, + 2805 => Opcode::XVCVUXDDP, + 2806 => Opcode::XVCVUXDSP, + 2807 => Opcode::XVCVUXWDP, + 2808 => Opcode::XVCVUXWSP, + 2809 => Opcode::XVDIVDP, + 2810 => Opcode::XVDIVSP, + 2811 => Opcode::XVF16GER2, + 2812 => Opcode::XVF16GER2NN, + 2813 => Opcode::XVF16GER2NP, + 2814 => Opcode::XVF16GER2PN, + 2815 => Opcode::XVF16GER2PP, + 2816 => Opcode::XVF16GER2W, + 2817 => Opcode::XVF16GER2WNN, + 2818 => Opcode::XVF16GER2WNP, + 2819 => Opcode::XVF16GER2WPN, + 2820 => Opcode::XVF16GER2WPP, + 2821 => Opcode::XVF32GER, + 2822 => Opcode::XVF32GERNN, + 2823 => Opcode::XVF32GERNP, + 2824 => Opcode::XVF32GERPN, + 2825 => Opcode::XVF32GERPP, + 2826 => Opcode::XVF32GERW, + 2827 => Opcode::XVF32GERWNN, + 2828 => Opcode::XVF32GERWNP, + 2829 => Opcode::XVF32GERWPN, + 2830 => Opcode::XVF32GERWPP, + 2831 => Opcode::XVF64GER, + 2832 => Opcode::XVF64GERNN, + 2833 => Opcode::XVF64GERNP, + 2834 => Opcode::XVF64GERPN, + 2835 => Opcode::XVF64GERPP, + 2836 => Opcode::XVF64GERW, + 2837 => Opcode::XVF64GERWNN, + 2838 => Opcode::XVF64GERWNP, + 2839 => Opcode::XVF64GERWPN, + 2840 => Opcode::XVF64GERWPP, + 2841 => Opcode::XVI16GER2, + 2842 => Opcode::XVI16GER2PP, + 2843 => Opcode::XVI16GER2S, + 2844 => Opcode::XVI16GER2SPP, + 2845 => Opcode::XVI16GER2SW, + 2846 => Opcode::XVI16GER2SWPP, + 2847 => Opcode::XVI16GER2W, + 2848 => Opcode::XVI16GER2WPP, + 2849 => Opcode::XVI4GER8, + 2850 => Opcode::XVI4GER8PP, + 2851 => Opcode::XVI4GER8W, + 2852 => Opcode::XVI4GER8WPP, + 2853 => Opcode::XVI8GER4, + 2854 => Opcode::XVI8GER4PP, + 2855 => Opcode::XVI8GER4SPP, + 2856 => Opcode::XVI8GER4W, + 2857 => Opcode::XVI8GER4WPP, + 2858 => Opcode::XVI8GER4WSPP, + 2859 => Opcode::XVIEXPDP, + 2860 => Opcode::XVIEXPSP, + 2861 => Opcode::XVMADDADP, + 2862 => Opcode::XVMADDASP, + 2863 => Opcode::XVMADDMDP, + 2864 => Opcode::XVMADDMSP, + 2865 => Opcode::XVMAXDP, + 2866 => Opcode::XVMAXSP, + 2867 => Opcode::XVMINDP, + 2868 => Opcode::XVMINSP, + 2869 => Opcode::XVMSUBADP, + 2870 => Opcode::XVMSUBASP, + 2871 => Opcode::XVMSUBMDP, + 2872 => Opcode::XVMSUBMSP, + 2873 => Opcode::XVMULDP, + 2874 => Opcode::XVMULHSH, + 2875 => Opcode::XVMULHSW, + 2876 => Opcode::XVMULHUH, + 2877 => Opcode::XVMULHUW, + 2878 => Opcode::XVMULSP, + 2879 => Opcode::XVMULUHM, + 2880 => Opcode::XVMULUWM, + 2881 => Opcode::XVNABSDP, + 2882 => Opcode::XVNABSSP, + 2883 => Opcode::XVNEGDP, + 2884 => Opcode::XVNEGSP, + 2885 => Opcode::XVNMADDADP, + 2886 => Opcode::XVNMADDASP, + 2887 => Opcode::XVNMADDMDP, + 2888 => Opcode::XVNMADDMSP, + 2889 => Opcode::XVNMSUBADP, + 2890 => Opcode::XVNMSUBASP, + 2891 => Opcode::XVNMSUBMDP, + 2892 => Opcode::XVNMSUBMSP, + 2893 => Opcode::XVRDPI, + 2894 => Opcode::XVRDPIC, + 2895 => Opcode::XVRDPIM, + 2896 => Opcode::XVRDPIP, + 2897 => Opcode::XVRDPIZ, + 2898 => Opcode::XVREDP, + 2899 => Opcode::XVRESP, + 2900 => Opcode::XVRLW, + 2901 => Opcode::XVRSPI, + 2902 => Opcode::XVRSPIC, + 2903 => Opcode::XVRSPIM, + 2904 => Opcode::XVRSPIP, + 2905 => Opcode::XVRSPIZ, + 2906 => Opcode::XVRSQRTEDP, + 2907 => Opcode::XVRSQRTESP, + 2908 => Opcode::XVSQRTDP, + 2909 => Opcode::XVSQRTSP, + 2910 => Opcode::XVSUBDP, + 2911 => Opcode::XVSUBSP, + 2912 => Opcode::XVSUBUHM, + 2913 => Opcode::XVSUBUWM, + 2914 => Opcode::XVTDIVDP, + 2915 => Opcode::XVTDIVSP, + 2916 => Opcode::XVTLSBB, + 2917 => Opcode::XVTSQRTDP, + 2918 => Opcode::XVTSQRTSP, + 2919 => Opcode::XVTSTDCDP, + 2920 => Opcode::XVTSTDCSP, + 2921 => Opcode::XVXEXPDP, + 2922 => Opcode::XVXEXPSP, + 2923 => Opcode::XVXSIGDP, + 2924 => Opcode::XVXSIGSP, + 2925 => Opcode::XXAESDECP, + 2926 => Opcode::XXAESENCP, + 2927 => Opcode::XXAESGENLKP, + 2928 => Opcode::XXBLENDVB, + 2929 => Opcode::XXBLENDVD, + 2930 => Opcode::XXBLENDVH, + 2931 => Opcode::XXBLENDVW, + 2932 => Opcode::XXBRD, + 2933 => Opcode::XXBRH, + 2934 => Opcode::XXBRQ, + 2935 => Opcode::XXBRW, + 2936 => Opcode::XXEVAL, + 2937 => Opcode::XXEXTRACTUW, + 2938 => Opcode::XXGENPCVBM, + 2939 => Opcode::XXGENPCVDM, + 2940 => Opcode::XXGENPCVHM, + 2941 => Opcode::XXGENPCVWM, + 2942 => Opcode::XXGFMUL128, + 2943 => Opcode::XXINSERTW, + 2944 => Opcode::XXLAND, + 2945 => Opcode::XXLANDC, + 2946 => Opcode::XXLEQV, + 2947 => Opcode::XXLEQVOnes, + 2948 => Opcode::XXLNAND, + 2949 => Opcode::XXLNOR, + 2950 => Opcode::XXLOR, + 2951 => Opcode::XXLORC, + 2952 => Opcode::XXLORf, + 2953 => Opcode::XXLXOR, + 2954 => Opcode::XXLXORdpz, + 2955 => Opcode::XXLXORspz, + 2956 => Opcode::XXLXORz, + 2957 => Opcode::XXMFACC, + 2958 => Opcode::XXMFACCW, + 2959 => Opcode::XXMRGHW, + 2960 => Opcode::XXMRGLW, + 2961 => Opcode::XXMTACC, + 2962 => Opcode::XXMTACCW, + 2963 => Opcode::XXMULMUL, + 2964 => Opcode::XXMULMULHIADD, + 2965 => Opcode::XXMULMULLOADD, + 2966 => Opcode::XXPERM, + 2967 => Opcode::XXPERMDI, + 2968 => Opcode::XXPERMDIs, + 2969 => Opcode::XXPERMR, + 2970 => Opcode::XXPERMX, + 2971 => Opcode::XXSEL, + 2972 => Opcode::XXSETACCZ, + 2973 => Opcode::XXSLDWI, + 2974 => Opcode::XXSLDWIs, + 2975 => Opcode::XXSPLTI32DX, + 2976 => Opcode::XXSPLTIB, + 2977 => Opcode::XXSPLTIDP, + 2978 => Opcode::XXSPLTIW, + 2979 => Opcode::XXSPLTW, + 2980 => Opcode::XXSPLTWs, + 2981 => Opcode::XXSSUMUDM, + 2982 => Opcode::XXSSUMUDMC, + 2983 => Opcode::XXSSUMUDMCEXT, + 2984 => Opcode::gBC, + 2985 => Opcode::gBCA, + 2986 => Opcode::gBCAat, + 2987 => Opcode::gBCCTR, + 2988 => Opcode::gBCCTRL, + 2989 => Opcode::gBCL, + 2990 => Opcode::gBCLA, + 2991 => Opcode::gBCLAat, + 2992 => Opcode::gBCLR, + 2993 => Opcode::gBCLRL, + 2994 => Opcode::gBCLat, + 2995 => Opcode::gBCat, + 2996 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands.rs new file mode 100644 index 0000000..78eb331 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand + Reg(Register), + + /// A PC-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_powerpc_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_powerpc_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_powerpc_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_powerpc_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/immediate.rs new file mode 100644 index 0000000..31fb0ba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// li 3, 8 +/// | +/// +---> Immediate(8) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/memory.rs new file mode 100644 index 0000000..793d502 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/memory.rs @@ -0,0 +1,64 @@ +use lief_ffi as ffi; + +use crate::{assembly::powerpc::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// ```text +/// lwz 3, 8(4) lwzx 3, 4, 5 +/// | | | | | +/// +------+ +---+ +------+ | +---+ +/// | | | | | +/// v v v v v +/// Disp Base Reg Base Index +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Wraps a memory offset as an integer displacement or as an index register +#[derive(Debug)] +pub enum Offset { + /// Index register offset + Reg(Reg), + /// Integer displacement + Displacement(i64), +} + +impl Memory { + /// The base register. + /// + /// For `lwz 3, 8(4)` it would return `4` + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The addressing offset. + /// + /// It can be either: + /// - An index register (e.g. `lwzx 3, 4, 5`) + /// - A displacement (e.g. `lwz 3, 8(4)`) + pub fn offset(&self) -> Option { + let ffi_offset = self.ptr.offset(); + match ffi_offset.enum_type { + 1 => Some(Offset::Reg(Reg::from(ffi_offset.value))), + 2 => Some(Offset::Displacement(ffi_offset.value as i64)), + _ => None, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/pc_relative.rs new file mode 100644 index 0000000..52ff7b4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/pc_relative.rs @@ -0,0 +1,37 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a PC-relative operand. +/// +/// ```text +/// bl 0x100 +/// | +/// v +/// PC Relative operand +/// ``` +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `pc` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/register.rs new file mode 100644 index 0000000..993a1f7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/operands/register.rs @@ -0,0 +1,41 @@ +use lief_ffi as ffi; + +use crate::assembly::powerpc::registers::Reg; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// For instance: +/// +/// ```text +/// add 3, 4, 5 +/// | | | +/// | | +---------> Register(5) +/// | +------------> Register(4) +/// +---------------> Register(3) +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_powerpc_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Register { + /// The effective register wrapped by this operand + pub fn value(&self) -> Reg { + Reg::from(self.ptr.value()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/registers.rs new file mode 100644 index 0000000..e654a76 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/powerpc/registers.rs @@ -0,0 +1,1239 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + BP, + CARRY, + CTR, + FP, + LR, + RM, + SPEFSCR, + VRSAVE, + XER, + ZERO, + ACC0, + ACC1, + ACC2, + ACC3, + ACC4, + ACC5, + ACC6, + ACC7, + BP8, + CR0, + CR1, + CR2, + CR3, + CR4, + CR5, + CR6, + CR7, + CTR8, + DMR0, + DMR1, + DMR2, + DMR3, + DMR4, + DMR5, + DMR6, + DMR7, + DMRROW0, + DMRROW1, + DMRROW2, + DMRROW3, + DMRROW4, + DMRROW5, + DMRROW6, + DMRROW7, + DMRROW8, + DMRROW9, + DMRROW10, + DMRROW11, + DMRROW12, + DMRROW13, + DMRROW14, + DMRROW15, + DMRROW16, + DMRROW17, + DMRROW18, + DMRROW19, + DMRROW20, + DMRROW21, + DMRROW22, + DMRROW23, + DMRROW24, + DMRROW25, + DMRROW26, + DMRROW27, + DMRROW28, + DMRROW29, + DMRROW30, + DMRROW31, + DMRROW32, + DMRROW33, + DMRROW34, + DMRROW35, + DMRROW36, + DMRROW37, + DMRROW38, + DMRROW39, + DMRROW40, + DMRROW41, + DMRROW42, + DMRROW43, + DMRROW44, + DMRROW45, + DMRROW46, + DMRROW47, + DMRROW48, + DMRROW49, + DMRROW50, + DMRROW51, + DMRROW52, + DMRROW53, + DMRROW54, + DMRROW55, + DMRROW56, + DMRROW57, + DMRROW58, + DMRROW59, + DMRROW60, + DMRROW61, + DMRROW62, + DMRROW63, + DMRROWp0, + DMRROWp1, + DMRROWp2, + DMRROWp3, + DMRROWp4, + DMRROWp5, + DMRROWp6, + DMRROWp7, + DMRROWp8, + DMRROWp9, + DMRROWp10, + DMRROWp11, + DMRROWp12, + DMRROWp13, + DMRROWp14, + DMRROWp15, + DMRROWp16, + DMRROWp17, + DMRROWp18, + DMRROWp19, + DMRROWp20, + DMRROWp21, + DMRROWp22, + DMRROWp23, + DMRROWp24, + DMRROWp25, + DMRROWp26, + DMRROWp27, + DMRROWp28, + DMRROWp29, + DMRROWp30, + DMRROWp31, + DMRp0, + DMRp1, + DMRp2, + DMRp3, + F0, + F1, + F2, + F3, + F4, + F5, + F6, + F7, + F8, + F9, + F10, + F11, + F12, + F13, + F14, + F15, + F16, + F17, + F18, + F19, + F20, + F21, + F22, + F23, + F24, + F25, + F26, + F27, + F28, + F29, + F30, + F31, + FH0, + FH1, + FH2, + FH3, + FH4, + FH5, + FH6, + FH7, + FH8, + FH9, + FH10, + FH11, + FH12, + FH13, + FH14, + FH15, + FH16, + FH17, + FH18, + FH19, + FH20, + FH21, + FH22, + FH23, + FH24, + FH25, + FH26, + FH27, + FH28, + FH29, + FH30, + FH31, + FP8, + Fpair0, + Fpair2, + Fpair4, + Fpair6, + Fpair8, + Fpair10, + Fpair12, + Fpair14, + Fpair16, + Fpair18, + Fpair20, + Fpair22, + Fpair24, + Fpair26, + Fpair28, + Fpair30, + H0, + H1, + H2, + H3, + H4, + H5, + H6, + H7, + H8, + H9, + H10, + H11, + H12, + H13, + H14, + H15, + H16, + H17, + H18, + H19, + H20, + H21, + H22, + H23, + H24, + H25, + H26, + H27, + H28, + H29, + H30, + H31, + LR8, + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + R16, + R17, + R18, + R19, + R20, + R21, + R22, + R23, + R24, + R25, + R26, + R27, + R28, + R29, + R30, + R31, + S0, + S1, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + S12, + S13, + S14, + S15, + S16, + S17, + S18, + S19, + S20, + S21, + S22, + S23, + S24, + S25, + S26, + S27, + S28, + S29, + S30, + S31, + UACC0, + UACC1, + UACC2, + UACC3, + UACC4, + UACC5, + UACC6, + UACC7, + V0, + V1, + V2, + V3, + V4, + V5, + V6, + V7, + V8, + V9, + V10, + V11, + V12, + V13, + V14, + V15, + V16, + V17, + V18, + V19, + V20, + V21, + V22, + V23, + V24, + V25, + V26, + V27, + V28, + V29, + V30, + V31, + VF0, + VF1, + VF2, + VF3, + VF4, + VF5, + VF6, + VF7, + VF8, + VF9, + VF10, + VF11, + VF12, + VF13, + VF14, + VF15, + VF16, + VF17, + VF18, + VF19, + VF20, + VF21, + VF22, + VF23, + VF24, + VF25, + VF26, + VF27, + VF28, + VF29, + VF30, + VF31, + VFH0, + VFH1, + VFH2, + VFH3, + VFH4, + VFH5, + VFH6, + VFH7, + VFH8, + VFH9, + VFH10, + VFH11, + VFH12, + VFH13, + VFH14, + VFH15, + VFH16, + VFH17, + VFH18, + VFH19, + VFH20, + VFH21, + VFH22, + VFH23, + VFH24, + VFH25, + VFH26, + VFH27, + VFH28, + VFH29, + VFH30, + VFH31, + VSL0, + VSL1, + VSL2, + VSL3, + VSL4, + VSL5, + VSL6, + VSL7, + VSL8, + VSL9, + VSL10, + VSL11, + VSL12, + VSL13, + VSL14, + VSL15, + VSL16, + VSL17, + VSL18, + VSL19, + VSL20, + VSL21, + VSL22, + VSL23, + VSL24, + VSL25, + VSL26, + VSL27, + VSL28, + VSL29, + VSL30, + VSL31, + VSRp0, + VSRp1, + VSRp2, + VSRp3, + VSRp4, + VSRp5, + VSRp6, + VSRp7, + VSRp8, + VSRp9, + VSRp10, + VSRp11, + VSRp12, + VSRp13, + VSRp14, + VSRp15, + VSRp16, + VSRp17, + VSRp18, + VSRp19, + VSRp20, + VSRp21, + VSRp22, + VSRp23, + VSRp24, + VSRp25, + VSRp26, + VSRp27, + VSRp28, + VSRp29, + VSRp30, + VSRp31, + VSX32, + VSX33, + VSX34, + VSX35, + VSX36, + VSX37, + VSX38, + VSX39, + VSX40, + VSX41, + VSX42, + VSX43, + VSX44, + VSX45, + VSX46, + VSX47, + VSX48, + VSX49, + VSX50, + VSX51, + VSX52, + VSX53, + VSX54, + VSX55, + VSX56, + VSX57, + VSX58, + VSX59, + VSX60, + VSX61, + VSX62, + VSX63, + WACC0, + WACC1, + WACC2, + WACC3, + WACC4, + WACC5, + WACC6, + WACC7, + WACC_HI0, + WACC_HI1, + WACC_HI2, + WACC_HI3, + WACC_HI4, + WACC_HI5, + WACC_HI6, + WACC_HI7, + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + X29, + X30, + X31, + ZERO8, + CR0EQ, + CR1EQ, + CR2EQ, + CR3EQ, + CR4EQ, + CR5EQ, + CR6EQ, + CR7EQ, + CR0GT, + CR1GT, + CR2GT, + CR3GT, + CR4GT, + CR5GT, + CR6GT, + CR7GT, + CR0LT, + CR1LT, + CR2LT, + CR3LT, + CR4LT, + CR5LT, + CR6LT, + CR7LT, + CR0UN, + CR1UN, + CR2UN, + CR3UN, + CR4UN, + CR5UN, + CR6UN, + CR7UN, + G8p0, + G8p1, + G8p2, + G8p3, + G8p4, + G8p5, + G8p6, + G8p7, + G8p8, + G8p9, + G8p10, + G8p11, + G8p12, + G8p13, + G8p14, + G8p15, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::BP, + 2 => Reg::CARRY, + 3 => Reg::CTR, + 4 => Reg::FP, + 5 => Reg::LR, + 6 => Reg::RM, + 7 => Reg::SPEFSCR, + 8 => Reg::VRSAVE, + 9 => Reg::XER, + 10 => Reg::ZERO, + 11 => Reg::ACC0, + 12 => Reg::ACC1, + 13 => Reg::ACC2, + 14 => Reg::ACC3, + 15 => Reg::ACC4, + 16 => Reg::ACC5, + 17 => Reg::ACC6, + 18 => Reg::ACC7, + 19 => Reg::BP8, + 20 => Reg::CR0, + 21 => Reg::CR1, + 22 => Reg::CR2, + 23 => Reg::CR3, + 24 => Reg::CR4, + 25 => Reg::CR5, + 26 => Reg::CR6, + 27 => Reg::CR7, + 28 => Reg::CTR8, + 29 => Reg::DMR0, + 30 => Reg::DMR1, + 31 => Reg::DMR2, + 32 => Reg::DMR3, + 33 => Reg::DMR4, + 34 => Reg::DMR5, + 35 => Reg::DMR6, + 36 => Reg::DMR7, + 37 => Reg::DMRROW0, + 38 => Reg::DMRROW1, + 39 => Reg::DMRROW2, + 40 => Reg::DMRROW3, + 41 => Reg::DMRROW4, + 42 => Reg::DMRROW5, + 43 => Reg::DMRROW6, + 44 => Reg::DMRROW7, + 45 => Reg::DMRROW8, + 46 => Reg::DMRROW9, + 47 => Reg::DMRROW10, + 48 => Reg::DMRROW11, + 49 => Reg::DMRROW12, + 50 => Reg::DMRROW13, + 51 => Reg::DMRROW14, + 52 => Reg::DMRROW15, + 53 => Reg::DMRROW16, + 54 => Reg::DMRROW17, + 55 => Reg::DMRROW18, + 56 => Reg::DMRROW19, + 57 => Reg::DMRROW20, + 58 => Reg::DMRROW21, + 59 => Reg::DMRROW22, + 60 => Reg::DMRROW23, + 61 => Reg::DMRROW24, + 62 => Reg::DMRROW25, + 63 => Reg::DMRROW26, + 64 => Reg::DMRROW27, + 65 => Reg::DMRROW28, + 66 => Reg::DMRROW29, + 67 => Reg::DMRROW30, + 68 => Reg::DMRROW31, + 69 => Reg::DMRROW32, + 70 => Reg::DMRROW33, + 71 => Reg::DMRROW34, + 72 => Reg::DMRROW35, + 73 => Reg::DMRROW36, + 74 => Reg::DMRROW37, + 75 => Reg::DMRROW38, + 76 => Reg::DMRROW39, + 77 => Reg::DMRROW40, + 78 => Reg::DMRROW41, + 79 => Reg::DMRROW42, + 80 => Reg::DMRROW43, + 81 => Reg::DMRROW44, + 82 => Reg::DMRROW45, + 83 => Reg::DMRROW46, + 84 => Reg::DMRROW47, + 85 => Reg::DMRROW48, + 86 => Reg::DMRROW49, + 87 => Reg::DMRROW50, + 88 => Reg::DMRROW51, + 89 => Reg::DMRROW52, + 90 => Reg::DMRROW53, + 91 => Reg::DMRROW54, + 92 => Reg::DMRROW55, + 93 => Reg::DMRROW56, + 94 => Reg::DMRROW57, + 95 => Reg::DMRROW58, + 96 => Reg::DMRROW59, + 97 => Reg::DMRROW60, + 98 => Reg::DMRROW61, + 99 => Reg::DMRROW62, + 100 => Reg::DMRROW63, + 101 => Reg::DMRROWp0, + 102 => Reg::DMRROWp1, + 103 => Reg::DMRROWp2, + 104 => Reg::DMRROWp3, + 105 => Reg::DMRROWp4, + 106 => Reg::DMRROWp5, + 107 => Reg::DMRROWp6, + 108 => Reg::DMRROWp7, + 109 => Reg::DMRROWp8, + 110 => Reg::DMRROWp9, + 111 => Reg::DMRROWp10, + 112 => Reg::DMRROWp11, + 113 => Reg::DMRROWp12, + 114 => Reg::DMRROWp13, + 115 => Reg::DMRROWp14, + 116 => Reg::DMRROWp15, + 117 => Reg::DMRROWp16, + 118 => Reg::DMRROWp17, + 119 => Reg::DMRROWp18, + 120 => Reg::DMRROWp19, + 121 => Reg::DMRROWp20, + 122 => Reg::DMRROWp21, + 123 => Reg::DMRROWp22, + 124 => Reg::DMRROWp23, + 125 => Reg::DMRROWp24, + 126 => Reg::DMRROWp25, + 127 => Reg::DMRROWp26, + 128 => Reg::DMRROWp27, + 129 => Reg::DMRROWp28, + 130 => Reg::DMRROWp29, + 131 => Reg::DMRROWp30, + 132 => Reg::DMRROWp31, + 133 => Reg::DMRp0, + 134 => Reg::DMRp1, + 135 => Reg::DMRp2, + 136 => Reg::DMRp3, + 137 => Reg::F0, + 138 => Reg::F1, + 139 => Reg::F2, + 140 => Reg::F3, + 141 => Reg::F4, + 142 => Reg::F5, + 143 => Reg::F6, + 144 => Reg::F7, + 145 => Reg::F8, + 146 => Reg::F9, + 147 => Reg::F10, + 148 => Reg::F11, + 149 => Reg::F12, + 150 => Reg::F13, + 151 => Reg::F14, + 152 => Reg::F15, + 153 => Reg::F16, + 154 => Reg::F17, + 155 => Reg::F18, + 156 => Reg::F19, + 157 => Reg::F20, + 158 => Reg::F21, + 159 => Reg::F22, + 160 => Reg::F23, + 161 => Reg::F24, + 162 => Reg::F25, + 163 => Reg::F26, + 164 => Reg::F27, + 165 => Reg::F28, + 166 => Reg::F29, + 167 => Reg::F30, + 168 => Reg::F31, + 169 => Reg::FH0, + 170 => Reg::FH1, + 171 => Reg::FH2, + 172 => Reg::FH3, + 173 => Reg::FH4, + 174 => Reg::FH5, + 175 => Reg::FH6, + 176 => Reg::FH7, + 177 => Reg::FH8, + 178 => Reg::FH9, + 179 => Reg::FH10, + 180 => Reg::FH11, + 181 => Reg::FH12, + 182 => Reg::FH13, + 183 => Reg::FH14, + 184 => Reg::FH15, + 185 => Reg::FH16, + 186 => Reg::FH17, + 187 => Reg::FH18, + 188 => Reg::FH19, + 189 => Reg::FH20, + 190 => Reg::FH21, + 191 => Reg::FH22, + 192 => Reg::FH23, + 193 => Reg::FH24, + 194 => Reg::FH25, + 195 => Reg::FH26, + 196 => Reg::FH27, + 197 => Reg::FH28, + 198 => Reg::FH29, + 199 => Reg::FH30, + 200 => Reg::FH31, + 201 => Reg::FP8, + 202 => Reg::Fpair0, + 203 => Reg::Fpair2, + 204 => Reg::Fpair4, + 205 => Reg::Fpair6, + 206 => Reg::Fpair8, + 207 => Reg::Fpair10, + 208 => Reg::Fpair12, + 209 => Reg::Fpair14, + 210 => Reg::Fpair16, + 211 => Reg::Fpair18, + 212 => Reg::Fpair20, + 213 => Reg::Fpair22, + 214 => Reg::Fpair24, + 215 => Reg::Fpair26, + 216 => Reg::Fpair28, + 217 => Reg::Fpair30, + 218 => Reg::H0, + 219 => Reg::H1, + 220 => Reg::H2, + 221 => Reg::H3, + 222 => Reg::H4, + 223 => Reg::H5, + 224 => Reg::H6, + 225 => Reg::H7, + 226 => Reg::H8, + 227 => Reg::H9, + 228 => Reg::H10, + 229 => Reg::H11, + 230 => Reg::H12, + 231 => Reg::H13, + 232 => Reg::H14, + 233 => Reg::H15, + 234 => Reg::H16, + 235 => Reg::H17, + 236 => Reg::H18, + 237 => Reg::H19, + 238 => Reg::H20, + 239 => Reg::H21, + 240 => Reg::H22, + 241 => Reg::H23, + 242 => Reg::H24, + 243 => Reg::H25, + 244 => Reg::H26, + 245 => Reg::H27, + 246 => Reg::H28, + 247 => Reg::H29, + 248 => Reg::H30, + 249 => Reg::H31, + 250 => Reg::LR8, + 251 => Reg::R0, + 252 => Reg::R1, + 253 => Reg::R2, + 254 => Reg::R3, + 255 => Reg::R4, + 256 => Reg::R5, + 257 => Reg::R6, + 258 => Reg::R7, + 259 => Reg::R8, + 260 => Reg::R9, + 261 => Reg::R10, + 262 => Reg::R11, + 263 => Reg::R12, + 264 => Reg::R13, + 265 => Reg::R14, + 266 => Reg::R15, + 267 => Reg::R16, + 268 => Reg::R17, + 269 => Reg::R18, + 270 => Reg::R19, + 271 => Reg::R20, + 272 => Reg::R21, + 273 => Reg::R22, + 274 => Reg::R23, + 275 => Reg::R24, + 276 => Reg::R25, + 277 => Reg::R26, + 278 => Reg::R27, + 279 => Reg::R28, + 280 => Reg::R29, + 281 => Reg::R30, + 282 => Reg::R31, + 283 => Reg::S0, + 284 => Reg::S1, + 285 => Reg::S2, + 286 => Reg::S3, + 287 => Reg::S4, + 288 => Reg::S5, + 289 => Reg::S6, + 290 => Reg::S7, + 291 => Reg::S8, + 292 => Reg::S9, + 293 => Reg::S10, + 294 => Reg::S11, + 295 => Reg::S12, + 296 => Reg::S13, + 297 => Reg::S14, + 298 => Reg::S15, + 299 => Reg::S16, + 300 => Reg::S17, + 301 => Reg::S18, + 302 => Reg::S19, + 303 => Reg::S20, + 304 => Reg::S21, + 305 => Reg::S22, + 306 => Reg::S23, + 307 => Reg::S24, + 308 => Reg::S25, + 309 => Reg::S26, + 310 => Reg::S27, + 311 => Reg::S28, + 312 => Reg::S29, + 313 => Reg::S30, + 314 => Reg::S31, + 315 => Reg::UACC0, + 316 => Reg::UACC1, + 317 => Reg::UACC2, + 318 => Reg::UACC3, + 319 => Reg::UACC4, + 320 => Reg::UACC5, + 321 => Reg::UACC6, + 322 => Reg::UACC7, + 323 => Reg::V0, + 324 => Reg::V1, + 325 => Reg::V2, + 326 => Reg::V3, + 327 => Reg::V4, + 328 => Reg::V5, + 329 => Reg::V6, + 330 => Reg::V7, + 331 => Reg::V8, + 332 => Reg::V9, + 333 => Reg::V10, + 334 => Reg::V11, + 335 => Reg::V12, + 336 => Reg::V13, + 337 => Reg::V14, + 338 => Reg::V15, + 339 => Reg::V16, + 340 => Reg::V17, + 341 => Reg::V18, + 342 => Reg::V19, + 343 => Reg::V20, + 344 => Reg::V21, + 345 => Reg::V22, + 346 => Reg::V23, + 347 => Reg::V24, + 348 => Reg::V25, + 349 => Reg::V26, + 350 => Reg::V27, + 351 => Reg::V28, + 352 => Reg::V29, + 353 => Reg::V30, + 354 => Reg::V31, + 355 => Reg::VF0, + 356 => Reg::VF1, + 357 => Reg::VF2, + 358 => Reg::VF3, + 359 => Reg::VF4, + 360 => Reg::VF5, + 361 => Reg::VF6, + 362 => Reg::VF7, + 363 => Reg::VF8, + 364 => Reg::VF9, + 365 => Reg::VF10, + 366 => Reg::VF11, + 367 => Reg::VF12, + 368 => Reg::VF13, + 369 => Reg::VF14, + 370 => Reg::VF15, + 371 => Reg::VF16, + 372 => Reg::VF17, + 373 => Reg::VF18, + 374 => Reg::VF19, + 375 => Reg::VF20, + 376 => Reg::VF21, + 377 => Reg::VF22, + 378 => Reg::VF23, + 379 => Reg::VF24, + 380 => Reg::VF25, + 381 => Reg::VF26, + 382 => Reg::VF27, + 383 => Reg::VF28, + 384 => Reg::VF29, + 385 => Reg::VF30, + 386 => Reg::VF31, + 387 => Reg::VFH0, + 388 => Reg::VFH1, + 389 => Reg::VFH2, + 390 => Reg::VFH3, + 391 => Reg::VFH4, + 392 => Reg::VFH5, + 393 => Reg::VFH6, + 394 => Reg::VFH7, + 395 => Reg::VFH8, + 396 => Reg::VFH9, + 397 => Reg::VFH10, + 398 => Reg::VFH11, + 399 => Reg::VFH12, + 400 => Reg::VFH13, + 401 => Reg::VFH14, + 402 => Reg::VFH15, + 403 => Reg::VFH16, + 404 => Reg::VFH17, + 405 => Reg::VFH18, + 406 => Reg::VFH19, + 407 => Reg::VFH20, + 408 => Reg::VFH21, + 409 => Reg::VFH22, + 410 => Reg::VFH23, + 411 => Reg::VFH24, + 412 => Reg::VFH25, + 413 => Reg::VFH26, + 414 => Reg::VFH27, + 415 => Reg::VFH28, + 416 => Reg::VFH29, + 417 => Reg::VFH30, + 418 => Reg::VFH31, + 419 => Reg::VSL0, + 420 => Reg::VSL1, + 421 => Reg::VSL2, + 422 => Reg::VSL3, + 423 => Reg::VSL4, + 424 => Reg::VSL5, + 425 => Reg::VSL6, + 426 => Reg::VSL7, + 427 => Reg::VSL8, + 428 => Reg::VSL9, + 429 => Reg::VSL10, + 430 => Reg::VSL11, + 431 => Reg::VSL12, + 432 => Reg::VSL13, + 433 => Reg::VSL14, + 434 => Reg::VSL15, + 435 => Reg::VSL16, + 436 => Reg::VSL17, + 437 => Reg::VSL18, + 438 => Reg::VSL19, + 439 => Reg::VSL20, + 440 => Reg::VSL21, + 441 => Reg::VSL22, + 442 => Reg::VSL23, + 443 => Reg::VSL24, + 444 => Reg::VSL25, + 445 => Reg::VSL26, + 446 => Reg::VSL27, + 447 => Reg::VSL28, + 448 => Reg::VSL29, + 449 => Reg::VSL30, + 450 => Reg::VSL31, + 451 => Reg::VSRp0, + 452 => Reg::VSRp1, + 453 => Reg::VSRp2, + 454 => Reg::VSRp3, + 455 => Reg::VSRp4, + 456 => Reg::VSRp5, + 457 => Reg::VSRp6, + 458 => Reg::VSRp7, + 459 => Reg::VSRp8, + 460 => Reg::VSRp9, + 461 => Reg::VSRp10, + 462 => Reg::VSRp11, + 463 => Reg::VSRp12, + 464 => Reg::VSRp13, + 465 => Reg::VSRp14, + 466 => Reg::VSRp15, + 467 => Reg::VSRp16, + 468 => Reg::VSRp17, + 469 => Reg::VSRp18, + 470 => Reg::VSRp19, + 471 => Reg::VSRp20, + 472 => Reg::VSRp21, + 473 => Reg::VSRp22, + 474 => Reg::VSRp23, + 475 => Reg::VSRp24, + 476 => Reg::VSRp25, + 477 => Reg::VSRp26, + 478 => Reg::VSRp27, + 479 => Reg::VSRp28, + 480 => Reg::VSRp29, + 481 => Reg::VSRp30, + 482 => Reg::VSRp31, + 483 => Reg::VSX32, + 484 => Reg::VSX33, + 485 => Reg::VSX34, + 486 => Reg::VSX35, + 487 => Reg::VSX36, + 488 => Reg::VSX37, + 489 => Reg::VSX38, + 490 => Reg::VSX39, + 491 => Reg::VSX40, + 492 => Reg::VSX41, + 493 => Reg::VSX42, + 494 => Reg::VSX43, + 495 => Reg::VSX44, + 496 => Reg::VSX45, + 497 => Reg::VSX46, + 498 => Reg::VSX47, + 499 => Reg::VSX48, + 500 => Reg::VSX49, + 501 => Reg::VSX50, + 502 => Reg::VSX51, + 503 => Reg::VSX52, + 504 => Reg::VSX53, + 505 => Reg::VSX54, + 506 => Reg::VSX55, + 507 => Reg::VSX56, + 508 => Reg::VSX57, + 509 => Reg::VSX58, + 510 => Reg::VSX59, + 511 => Reg::VSX60, + 512 => Reg::VSX61, + 513 => Reg::VSX62, + 514 => Reg::VSX63, + 515 => Reg::WACC0, + 516 => Reg::WACC1, + 517 => Reg::WACC2, + 518 => Reg::WACC3, + 519 => Reg::WACC4, + 520 => Reg::WACC5, + 521 => Reg::WACC6, + 522 => Reg::WACC7, + 523 => Reg::WACC_HI0, + 524 => Reg::WACC_HI1, + 525 => Reg::WACC_HI2, + 526 => Reg::WACC_HI3, + 527 => Reg::WACC_HI4, + 528 => Reg::WACC_HI5, + 529 => Reg::WACC_HI6, + 530 => Reg::WACC_HI7, + 531 => Reg::X0, + 532 => Reg::X1, + 533 => Reg::X2, + 534 => Reg::X3, + 535 => Reg::X4, + 536 => Reg::X5, + 537 => Reg::X6, + 538 => Reg::X7, + 539 => Reg::X8, + 540 => Reg::X9, + 541 => Reg::X10, + 542 => Reg::X11, + 543 => Reg::X12, + 544 => Reg::X13, + 545 => Reg::X14, + 546 => Reg::X15, + 547 => Reg::X16, + 548 => Reg::X17, + 549 => Reg::X18, + 550 => Reg::X19, + 551 => Reg::X20, + 552 => Reg::X21, + 553 => Reg::X22, + 554 => Reg::X23, + 555 => Reg::X24, + 556 => Reg::X25, + 557 => Reg::X26, + 558 => Reg::X27, + 559 => Reg::X28, + 560 => Reg::X29, + 561 => Reg::X30, + 562 => Reg::X31, + 563 => Reg::ZERO8, + 564 => Reg::CR0EQ, + 565 => Reg::CR1EQ, + 566 => Reg::CR2EQ, + 567 => Reg::CR3EQ, + 568 => Reg::CR4EQ, + 569 => Reg::CR5EQ, + 570 => Reg::CR6EQ, + 571 => Reg::CR7EQ, + 572 => Reg::CR0GT, + 573 => Reg::CR1GT, + 574 => Reg::CR2GT, + 575 => Reg::CR3GT, + 576 => Reg::CR4GT, + 577 => Reg::CR5GT, + 578 => Reg::CR6GT, + 579 => Reg::CR7GT, + 580 => Reg::CR0LT, + 581 => Reg::CR1LT, + 582 => Reg::CR2LT, + 583 => Reg::CR3LT, + 584 => Reg::CR4LT, + 585 => Reg::CR5LT, + 586 => Reg::CR6LT, + 587 => Reg::CR7LT, + 588 => Reg::CR0UN, + 589 => Reg::CR1UN, + 590 => Reg::CR2UN, + 591 => Reg::CR3UN, + 592 => Reg::CR4UN, + 593 => Reg::CR5UN, + 594 => Reg::CR6UN, + 595 => Reg::CR7UN, + 596 => Reg::G8p0, + 597 => Reg::G8p1, + 598 => Reg::G8p2, + 599 => Reg::G8p3, + 600 => Reg::G8p4, + 601 => Reg::G8p5, + 602 => Reg::G8p6, + 603 => Reg::G8p7, + 604 => Reg::G8p8, + 605 => Reg::G8p9, + 606 => Reg::G8p10, + 607 => Reg::G8p11, + 608 => Reg::G8p12, + 609 => Reg::G8p13, + 610 => Reg::G8p14, + 611 => Reg::G8p15, + 612 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv.rs new file mode 100644 index 0000000..26b929e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv.rs @@ -0,0 +1,18 @@ +//! RISC-V architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/instruction.rs new file mode 100644 index 0000000..bc8ffe0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/instruction.rs @@ -0,0 +1,52 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::FromFFI; + +use crate::assembly::riscv; +use crate::declare_fwd_iterator; + +/// This structure represents a RISC-V (32 or 64 bit) instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`riscv::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } +} + +declare_fwd_iterator!( + Operands, + riscv::Operands, + ffi::asm_Instruction, + ffi::asm_riscv_Operand, + ffi::asm_riscv_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/opcodes.rs new file mode 100644 index 0000000..def004b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/opcodes.rs @@ -0,0 +1,32457 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ADJCALLSTACKDOWN, + ADJCALLSTACKUP, + BuildPairF64Pseudo, + ClearFCSR, + ClearFCSRImm, + G_CLZW, + G_CTZW, + G_DIVUW, + G_DIVW, + G_FCLASS, + G_FCVT_WU_RV64, + G_FCVT_W_RV64, + G_READ_VLENB, + G_REMUW, + G_ROLW, + G_RORW, + G_SLLW, + G_SPLAT_VECTOR_SPLIT_I64_VL, + G_SRAW, + G_SRLW, + G_VMCLR_VL, + G_VMSET_VL, + G_VMV_V_V_VL, + G_VSLIDEDOWN_VL, + G_VSLIDEUP_VL, + HWASAN_CHECK_MEMACCESS_SHORTGRANULES, + KCFI_CHECK, + PROBED_STACKALLOC, + PROBED_STACKALLOC_DYN, + PROBED_STACKALLOC_RVV, + PseudoAddTPRel, + PseudoAtomicLoadAdd32, + PseudoAtomicLoadAdd64, + PseudoAtomicLoadAnd32, + PseudoAtomicLoadAnd64, + PseudoAtomicLoadMax32, + PseudoAtomicLoadMax64, + PseudoAtomicLoadMin32, + PseudoAtomicLoadMin64, + PseudoAtomicLoadNand32, + PseudoAtomicLoadNand64, + PseudoAtomicLoadOr32, + PseudoAtomicLoadOr64, + PseudoAtomicLoadSub32, + PseudoAtomicLoadSub64, + PseudoAtomicLoadUMax32, + PseudoAtomicLoadUMax64, + PseudoAtomicLoadUMin32, + PseudoAtomicLoadUMin64, + PseudoAtomicLoadXor32, + PseudoAtomicLoadXor64, + PseudoAtomicSwap32, + PseudoAtomicSwap64, + PseudoBR, + PseudoBRIND, + PseudoBRINDNonX7, + PseudoBRINDX7, + PseudoCALL, + PseudoCALLIndirect, + PseudoCALLIndirectNonX7, + PseudoCALLIndirectX7, + PseudoCALLReg, + PseudoCCADD, + PseudoCCADDI, + PseudoCCADDIW, + PseudoCCADDW, + PseudoCCAND, + PseudoCCANDI, + PseudoCCANDN, + PseudoCCLB, + PseudoCCLBU, + PseudoCCLD, + PseudoCCLH, + PseudoCCLHU, + PseudoCCLUI, + PseudoCCLW, + PseudoCCLWU, + PseudoCCMAX, + PseudoCCMAXU, + PseudoCCMIN, + PseudoCCMINU, + PseudoCCMOVGPR, + PseudoCCMOVGPRNoX0, + PseudoCCMUL, + PseudoCCNDS_BFOS, + PseudoCCNDS_BFOZ, + PseudoCCOR, + PseudoCCORI, + PseudoCCORN, + PseudoCCQC_E_LB, + PseudoCCQC_E_LBU, + PseudoCCQC_E_LH, + PseudoCCQC_E_LHU, + PseudoCCQC_E_LI, + PseudoCCQC_E_LW, + PseudoCCQC_LI, + PseudoCCSLL, + PseudoCCSLLI, + PseudoCCSLLIW, + PseudoCCSLLW, + PseudoCCSRA, + PseudoCCSRAI, + PseudoCCSRAIW, + PseudoCCSRAW, + PseudoCCSRL, + PseudoCCSRLI, + PseudoCCSRLIW, + PseudoCCSRLW, + PseudoCCSUB, + PseudoCCSUBW, + PseudoCCXNOR, + PseudoCCXOR, + PseudoCCXORI, + PseudoCV_ELW, + PseudoC_ADDI_NOP, + PseudoCmpXchg32, + PseudoCmpXchg64, + PseudoFLD, + PseudoFLH, + PseudoFLQ, + PseudoFLW, + PseudoFROUND_D, + PseudoFROUND_D_IN32X, + PseudoFROUND_D_INX, + PseudoFROUND_H, + PseudoFROUND_H_INX, + PseudoFROUND_S, + PseudoFROUND_S_INX, + PseudoFSD, + PseudoFSH, + PseudoFSQ, + PseudoFSW, + PseudoJump, + PseudoLA, + PseudoLAImm, + PseudoLA_TLSDESC, + PseudoLA_TLS_GD, + PseudoLA_TLS_IE, + PseudoLB, + PseudoLBU, + PseudoLD, + PseudoLD_RV32, + PseudoLD_RV32_OPT, + PseudoLGA, + PseudoLH, + PseudoLHU, + PseudoLI, + PseudoLLA, + PseudoLLAImm, + PseudoLW, + PseudoLWU, + PseudoLongBEQ, + PseudoLongBEQI, + PseudoLongBGE, + PseudoLongBGEU, + PseudoLongBLT, + PseudoLongBLTU, + PseudoLongBNE, + PseudoLongBNEI, + PseudoLongQC_BEQI, + PseudoLongQC_BGEI, + PseudoLongQC_BGEUI, + PseudoLongQC_BLTI, + PseudoLongQC_BLTUI, + PseudoLongQC_BNEI, + PseudoLongQC_E_BEQI, + PseudoLongQC_E_BGEI, + PseudoLongQC_E_BGEUI, + PseudoLongQC_E_BLTI, + PseudoLongQC_E_BLTUI, + PseudoLongQC_E_BNEI, + PseudoMOP_C_SSPUSH, + PseudoMOP_SSPOPCHK, + PseudoMOP_SSPUSH, + PseudoMV_FPR16INX, + PseudoMV_FPR32INX, + PseudoMaskedAtomicLoadAdd32, + PseudoMaskedAtomicLoadMax32, + PseudoMaskedAtomicLoadMin32, + PseudoMaskedAtomicLoadNand32, + PseudoMaskedAtomicLoadSub32, + PseudoMaskedAtomicLoadUMax32, + PseudoMaskedAtomicLoadUMin32, + PseudoMaskedAtomicSwap32, + PseudoMaskedCmpXchg32, + PseudoMovAddr, + PseudoMovImm, + PseudoNDS_VD4DOTSU_VV_M1, + PseudoNDS_VD4DOTSU_VV_M1_MASK, + PseudoNDS_VD4DOTSU_VV_M2, + PseudoNDS_VD4DOTSU_VV_M2_MASK, + PseudoNDS_VD4DOTSU_VV_M4, + PseudoNDS_VD4DOTSU_VV_M4_MASK, + PseudoNDS_VD4DOTSU_VV_M8, + PseudoNDS_VD4DOTSU_VV_M8_MASK, + PseudoNDS_VD4DOTSU_VV_MF2, + PseudoNDS_VD4DOTSU_VV_MF2_MASK, + PseudoNDS_VD4DOTS_VV_M1, + PseudoNDS_VD4DOTS_VV_M1_MASK, + PseudoNDS_VD4DOTS_VV_M2, + PseudoNDS_VD4DOTS_VV_M2_MASK, + PseudoNDS_VD4DOTS_VV_M4, + PseudoNDS_VD4DOTS_VV_M4_MASK, + PseudoNDS_VD4DOTS_VV_M8, + PseudoNDS_VD4DOTS_VV_M8_MASK, + PseudoNDS_VD4DOTS_VV_MF2, + PseudoNDS_VD4DOTS_VV_MF2_MASK, + PseudoNDS_VD4DOTU_VV_M1, + PseudoNDS_VD4DOTU_VV_M1_MASK, + PseudoNDS_VD4DOTU_VV_M2, + PseudoNDS_VD4DOTU_VV_M2_MASK, + PseudoNDS_VD4DOTU_VV_M4, + PseudoNDS_VD4DOTU_VV_M4_MASK, + PseudoNDS_VD4DOTU_VV_M8, + PseudoNDS_VD4DOTU_VV_M8_MASK, + PseudoNDS_VD4DOTU_VV_MF2, + PseudoNDS_VD4DOTU_VV_MF2_MASK, + PseudoNDS_VFNCVT_BF16_S_M1, + PseudoNDS_VFNCVT_BF16_S_M2, + PseudoNDS_VFNCVT_BF16_S_M4, + PseudoNDS_VFNCVT_BF16_S_MF2, + PseudoNDS_VFNCVT_BF16_S_MF4, + PseudoNDS_VFPMADB_VFPR16_M1, + PseudoNDS_VFPMADB_VFPR16_M1_MASK, + PseudoNDS_VFPMADB_VFPR16_M2, + PseudoNDS_VFPMADB_VFPR16_M2_MASK, + PseudoNDS_VFPMADB_VFPR16_M4, + PseudoNDS_VFPMADB_VFPR16_M4_MASK, + PseudoNDS_VFPMADB_VFPR16_M8, + PseudoNDS_VFPMADB_VFPR16_M8_MASK, + PseudoNDS_VFPMADB_VFPR16_MF2, + PseudoNDS_VFPMADB_VFPR16_MF2_MASK, + PseudoNDS_VFPMADB_VFPR16_MF4, + PseudoNDS_VFPMADB_VFPR16_MF4_MASK, + PseudoNDS_VFPMADT_VFPR16_M1, + PseudoNDS_VFPMADT_VFPR16_M1_MASK, + PseudoNDS_VFPMADT_VFPR16_M2, + PseudoNDS_VFPMADT_VFPR16_M2_MASK, + PseudoNDS_VFPMADT_VFPR16_M4, + PseudoNDS_VFPMADT_VFPR16_M4_MASK, + PseudoNDS_VFPMADT_VFPR16_M8, + PseudoNDS_VFPMADT_VFPR16_M8_MASK, + PseudoNDS_VFPMADT_VFPR16_MF2, + PseudoNDS_VFPMADT_VFPR16_MF2_MASK, + PseudoNDS_VFPMADT_VFPR16_MF4, + PseudoNDS_VFPMADT_VFPR16_MF4_MASK, + PseudoNDS_VFWCVT_S_BF16_M1, + PseudoNDS_VFWCVT_S_BF16_M2, + PseudoNDS_VFWCVT_S_BF16_M4, + PseudoNDS_VFWCVT_S_BF16_MF2, + PseudoNDS_VFWCVT_S_BF16_MF4, + PseudoNDS_VLN8_V_M1, + PseudoNDS_VLN8_V_M1_MASK, + PseudoNDS_VLN8_V_M2, + PseudoNDS_VLN8_V_M2_MASK, + PseudoNDS_VLN8_V_M4, + PseudoNDS_VLN8_V_M4_MASK, + PseudoNDS_VLN8_V_M8, + PseudoNDS_VLN8_V_M8_MASK, + PseudoNDS_VLN8_V_MF2, + PseudoNDS_VLN8_V_MF2_MASK, + PseudoNDS_VLN8_V_MF4, + PseudoNDS_VLN8_V_MF4_MASK, + PseudoNDS_VLN8_V_MF8, + PseudoNDS_VLN8_V_MF8_MASK, + PseudoNDS_VLNU8_V_M1, + PseudoNDS_VLNU8_V_M1_MASK, + PseudoNDS_VLNU8_V_M2, + PseudoNDS_VLNU8_V_M2_MASK, + PseudoNDS_VLNU8_V_M4, + PseudoNDS_VLNU8_V_M4_MASK, + PseudoNDS_VLNU8_V_M8, + PseudoNDS_VLNU8_V_M8_MASK, + PseudoNDS_VLNU8_V_MF2, + PseudoNDS_VLNU8_V_MF2_MASK, + PseudoNDS_VLNU8_V_MF4, + PseudoNDS_VLNU8_V_MF4_MASK, + PseudoNDS_VLNU8_V_MF8, + PseudoNDS_VLNU8_V_MF8_MASK, + PseudoQC_E_LB, + PseudoQC_E_LBU, + PseudoQC_E_LH, + PseudoQC_E_LHU, + PseudoQC_E_LW, + PseudoQC_E_SB, + PseudoQC_E_SH, + PseudoQC_E_SW, + PseudoQuietFLE_D, + PseudoQuietFLE_D_IN32X, + PseudoQuietFLE_D_INX, + PseudoQuietFLE_H, + PseudoQuietFLE_H_INX, + PseudoQuietFLE_S, + PseudoQuietFLE_S_INX, + PseudoQuietFLT_D, + PseudoQuietFLT_D_IN32X, + PseudoQuietFLT_D_INX, + PseudoQuietFLT_H, + PseudoQuietFLT_H_INX, + PseudoQuietFLT_S, + PseudoQuietFLT_S_INX, + PseudoRET, + PseudoRI_VEXTRACT_M1, + PseudoRI_VEXTRACT_M2, + PseudoRI_VEXTRACT_M4, + PseudoRI_VEXTRACT_M8, + PseudoRI_VEXTRACT_MF2, + PseudoRI_VEXTRACT_MF4, + PseudoRI_VEXTRACT_MF8, + PseudoRI_VINSERT_M1, + PseudoRI_VINSERT_M2, + PseudoRI_VINSERT_M4, + PseudoRI_VINSERT_M8, + PseudoRI_VINSERT_MF2, + PseudoRI_VINSERT_MF4, + PseudoRI_VINSERT_MF8, + PseudoRI_VUNZIP2A_VV_M1, + PseudoRI_VUNZIP2A_VV_M1_MASK, + PseudoRI_VUNZIP2A_VV_M2, + PseudoRI_VUNZIP2A_VV_M2_MASK, + PseudoRI_VUNZIP2A_VV_M4, + PseudoRI_VUNZIP2A_VV_M4_MASK, + PseudoRI_VUNZIP2A_VV_M8, + PseudoRI_VUNZIP2A_VV_M8_MASK, + PseudoRI_VUNZIP2A_VV_MF2, + PseudoRI_VUNZIP2A_VV_MF2_MASK, + PseudoRI_VUNZIP2A_VV_MF4, + PseudoRI_VUNZIP2A_VV_MF4_MASK, + PseudoRI_VUNZIP2A_VV_MF8, + PseudoRI_VUNZIP2A_VV_MF8_MASK, + PseudoRI_VUNZIP2B_VV_M1, + PseudoRI_VUNZIP2B_VV_M1_MASK, + PseudoRI_VUNZIP2B_VV_M2, + PseudoRI_VUNZIP2B_VV_M2_MASK, + PseudoRI_VUNZIP2B_VV_M4, + PseudoRI_VUNZIP2B_VV_M4_MASK, + PseudoRI_VUNZIP2B_VV_M8, + PseudoRI_VUNZIP2B_VV_M8_MASK, + PseudoRI_VUNZIP2B_VV_MF2, + PseudoRI_VUNZIP2B_VV_MF2_MASK, + PseudoRI_VUNZIP2B_VV_MF4, + PseudoRI_VUNZIP2B_VV_MF4_MASK, + PseudoRI_VUNZIP2B_VV_MF8, + PseudoRI_VUNZIP2B_VV_MF8_MASK, + PseudoRI_VZIP2A_VV_M1, + PseudoRI_VZIP2A_VV_M1_MASK, + PseudoRI_VZIP2A_VV_M2, + PseudoRI_VZIP2A_VV_M2_MASK, + PseudoRI_VZIP2A_VV_M4, + PseudoRI_VZIP2A_VV_M4_MASK, + PseudoRI_VZIP2A_VV_M8, + PseudoRI_VZIP2A_VV_M8_MASK, + PseudoRI_VZIP2A_VV_MF2, + PseudoRI_VZIP2A_VV_MF2_MASK, + PseudoRI_VZIP2A_VV_MF4, + PseudoRI_VZIP2A_VV_MF4_MASK, + PseudoRI_VZIP2A_VV_MF8, + PseudoRI_VZIP2A_VV_MF8_MASK, + PseudoRI_VZIP2B_VV_M1, + PseudoRI_VZIP2B_VV_M1_MASK, + PseudoRI_VZIP2B_VV_M2, + PseudoRI_VZIP2B_VV_M2_MASK, + PseudoRI_VZIP2B_VV_M4, + PseudoRI_VZIP2B_VV_M4_MASK, + PseudoRI_VZIP2B_VV_M8, + PseudoRI_VZIP2B_VV_M8_MASK, + PseudoRI_VZIP2B_VV_MF2, + PseudoRI_VZIP2B_VV_MF2_MASK, + PseudoRI_VZIP2B_VV_MF4, + PseudoRI_VZIP2B_VV_MF4_MASK, + PseudoRI_VZIP2B_VV_MF8, + PseudoRI_VZIP2B_VV_MF8_MASK, + PseudoRI_VZIPEVEN_VV_M1, + PseudoRI_VZIPEVEN_VV_M1_MASK, + PseudoRI_VZIPEVEN_VV_M2, + PseudoRI_VZIPEVEN_VV_M2_MASK, + PseudoRI_VZIPEVEN_VV_M4, + PseudoRI_VZIPEVEN_VV_M4_MASK, + PseudoRI_VZIPEVEN_VV_M8, + PseudoRI_VZIPEVEN_VV_M8_MASK, + PseudoRI_VZIPEVEN_VV_MF2, + PseudoRI_VZIPEVEN_VV_MF2_MASK, + PseudoRI_VZIPEVEN_VV_MF4, + PseudoRI_VZIPEVEN_VV_MF4_MASK, + PseudoRI_VZIPEVEN_VV_MF8, + PseudoRI_VZIPEVEN_VV_MF8_MASK, + PseudoRI_VZIPODD_VV_M1, + PseudoRI_VZIPODD_VV_M1_MASK, + PseudoRI_VZIPODD_VV_M2, + PseudoRI_VZIPODD_VV_M2_MASK, + PseudoRI_VZIPODD_VV_M4, + PseudoRI_VZIPODD_VV_M4_MASK, + PseudoRI_VZIPODD_VV_M8, + PseudoRI_VZIPODD_VV_M8_MASK, + PseudoRI_VZIPODD_VV_MF2, + PseudoRI_VZIPODD_VV_MF2_MASK, + PseudoRI_VZIPODD_VV_MF4, + PseudoRI_VZIPODD_VV_MF4_MASK, + PseudoRI_VZIPODD_VV_MF8, + PseudoRI_VZIPODD_VV_MF8_MASK, + PseudoRV32ZdinxLD, + PseudoRV32ZdinxSD, + PseudoReadVL, + PseudoReadVLENB, + PseudoReadVLENBViaVSETVLIX0, + PseudoSB, + PseudoSD, + PseudoSD_RV32, + PseudoSD_RV32_OPT, + PseudoSEXT_B, + PseudoSEXT_H, + PseudoSF_MM_E4M3_E4M3, + PseudoSF_MM_E4M3_E5M2, + PseudoSF_MM_E5M2_E4M3, + PseudoSF_MM_E5M2_E5M2, + PseudoSF_MM_F_F, + PseudoSF_MM_F_F_ALT, + PseudoSF_MM_S_S, + PseudoSF_MM_S_U, + PseudoSF_MM_U_S, + PseudoSF_MM_U_U, + PseudoSF_VC_FPR16VV_SE_M1, + PseudoSF_VC_FPR16VV_SE_M2, + PseudoSF_VC_FPR16VV_SE_M4, + PseudoSF_VC_FPR16VV_SE_M8, + PseudoSF_VC_FPR16VV_SE_MF2, + PseudoSF_VC_FPR16VV_SE_MF4, + PseudoSF_VC_FPR16VW_SE_M1, + PseudoSF_VC_FPR16VW_SE_M2, + PseudoSF_VC_FPR16VW_SE_M4, + PseudoSF_VC_FPR16VW_SE_M8, + PseudoSF_VC_FPR16VW_SE_MF2, + PseudoSF_VC_FPR16VW_SE_MF4, + PseudoSF_VC_FPR16V_SE_M1, + PseudoSF_VC_FPR16V_SE_M2, + PseudoSF_VC_FPR16V_SE_M4, + PseudoSF_VC_FPR16V_SE_M8, + PseudoSF_VC_FPR16V_SE_MF2, + PseudoSF_VC_FPR16V_SE_MF4, + PseudoSF_VC_FPR32VV_SE_M1, + PseudoSF_VC_FPR32VV_SE_M2, + PseudoSF_VC_FPR32VV_SE_M4, + PseudoSF_VC_FPR32VV_SE_M8, + PseudoSF_VC_FPR32VV_SE_MF2, + PseudoSF_VC_FPR32VW_SE_M1, + PseudoSF_VC_FPR32VW_SE_M2, + PseudoSF_VC_FPR32VW_SE_M4, + PseudoSF_VC_FPR32VW_SE_M8, + PseudoSF_VC_FPR32VW_SE_MF2, + PseudoSF_VC_FPR32V_SE_M1, + PseudoSF_VC_FPR32V_SE_M2, + PseudoSF_VC_FPR32V_SE_M4, + PseudoSF_VC_FPR32V_SE_M8, + PseudoSF_VC_FPR32V_SE_MF2, + PseudoSF_VC_FPR64VV_SE_M1, + PseudoSF_VC_FPR64VV_SE_M2, + PseudoSF_VC_FPR64VV_SE_M4, + PseudoSF_VC_FPR64VV_SE_M8, + PseudoSF_VC_FPR64V_SE_M1, + PseudoSF_VC_FPR64V_SE_M2, + PseudoSF_VC_FPR64V_SE_M4, + PseudoSF_VC_FPR64V_SE_M8, + PseudoSF_VC_IVV_SE_M1, + PseudoSF_VC_IVV_SE_M2, + PseudoSF_VC_IVV_SE_M4, + PseudoSF_VC_IVV_SE_M8, + PseudoSF_VC_IVV_SE_MF2, + PseudoSF_VC_IVV_SE_MF4, + PseudoSF_VC_IVV_SE_MF8, + PseudoSF_VC_IVW_SE_M1, + PseudoSF_VC_IVW_SE_M2, + PseudoSF_VC_IVW_SE_M4, + PseudoSF_VC_IVW_SE_MF2, + PseudoSF_VC_IVW_SE_MF4, + PseudoSF_VC_IVW_SE_MF8, + PseudoSF_VC_IV_SE_M1, + PseudoSF_VC_IV_SE_M2, + PseudoSF_VC_IV_SE_M4, + PseudoSF_VC_IV_SE_M8, + PseudoSF_VC_IV_SE_MF2, + PseudoSF_VC_IV_SE_MF4, + PseudoSF_VC_IV_SE_MF8, + PseudoSF_VC_I_SE_M1, + PseudoSF_VC_I_SE_M2, + PseudoSF_VC_I_SE_M4, + PseudoSF_VC_I_SE_M8, + PseudoSF_VC_I_SE_MF2, + PseudoSF_VC_I_SE_MF4, + PseudoSF_VC_I_SE_MF8, + PseudoSF_VC_VVV_SE_M1, + PseudoSF_VC_VVV_SE_M2, + PseudoSF_VC_VVV_SE_M4, + PseudoSF_VC_VVV_SE_M8, + PseudoSF_VC_VVV_SE_MF2, + PseudoSF_VC_VVV_SE_MF4, + PseudoSF_VC_VVV_SE_MF8, + PseudoSF_VC_VVW_SE_M1, + PseudoSF_VC_VVW_SE_M2, + PseudoSF_VC_VVW_SE_M4, + PseudoSF_VC_VVW_SE_MF2, + PseudoSF_VC_VVW_SE_MF4, + PseudoSF_VC_VVW_SE_MF8, + PseudoSF_VC_VV_SE_M1, + PseudoSF_VC_VV_SE_M2, + PseudoSF_VC_VV_SE_M4, + PseudoSF_VC_VV_SE_M8, + PseudoSF_VC_VV_SE_MF2, + PseudoSF_VC_VV_SE_MF4, + PseudoSF_VC_VV_SE_MF8, + PseudoSF_VC_V_FPR16VV_M1, + PseudoSF_VC_V_FPR16VV_M2, + PseudoSF_VC_V_FPR16VV_M4, + PseudoSF_VC_V_FPR16VV_M8, + PseudoSF_VC_V_FPR16VV_MF2, + PseudoSF_VC_V_FPR16VV_MF4, + PseudoSF_VC_V_FPR16VV_SE_M1, + PseudoSF_VC_V_FPR16VV_SE_M2, + PseudoSF_VC_V_FPR16VV_SE_M4, + PseudoSF_VC_V_FPR16VV_SE_M8, + PseudoSF_VC_V_FPR16VV_SE_MF2, + PseudoSF_VC_V_FPR16VV_SE_MF4, + PseudoSF_VC_V_FPR16VW_M1, + PseudoSF_VC_V_FPR16VW_M2, + PseudoSF_VC_V_FPR16VW_M4, + PseudoSF_VC_V_FPR16VW_M8, + PseudoSF_VC_V_FPR16VW_MF2, + PseudoSF_VC_V_FPR16VW_MF4, + PseudoSF_VC_V_FPR16VW_SE_M1, + PseudoSF_VC_V_FPR16VW_SE_M2, + PseudoSF_VC_V_FPR16VW_SE_M4, + PseudoSF_VC_V_FPR16VW_SE_M8, + PseudoSF_VC_V_FPR16VW_SE_MF2, + PseudoSF_VC_V_FPR16VW_SE_MF4, + PseudoSF_VC_V_FPR16V_M1, + PseudoSF_VC_V_FPR16V_M2, + PseudoSF_VC_V_FPR16V_M4, + PseudoSF_VC_V_FPR16V_M8, + PseudoSF_VC_V_FPR16V_MF2, + PseudoSF_VC_V_FPR16V_MF4, + PseudoSF_VC_V_FPR16V_SE_M1, + PseudoSF_VC_V_FPR16V_SE_M2, + PseudoSF_VC_V_FPR16V_SE_M4, + PseudoSF_VC_V_FPR16V_SE_M8, + PseudoSF_VC_V_FPR16V_SE_MF2, + PseudoSF_VC_V_FPR16V_SE_MF4, + PseudoSF_VC_V_FPR32VV_M1, + PseudoSF_VC_V_FPR32VV_M2, + PseudoSF_VC_V_FPR32VV_M4, + PseudoSF_VC_V_FPR32VV_M8, + PseudoSF_VC_V_FPR32VV_MF2, + PseudoSF_VC_V_FPR32VV_SE_M1, + PseudoSF_VC_V_FPR32VV_SE_M2, + PseudoSF_VC_V_FPR32VV_SE_M4, + PseudoSF_VC_V_FPR32VV_SE_M8, + PseudoSF_VC_V_FPR32VV_SE_MF2, + PseudoSF_VC_V_FPR32VW_M1, + PseudoSF_VC_V_FPR32VW_M2, + PseudoSF_VC_V_FPR32VW_M4, + PseudoSF_VC_V_FPR32VW_M8, + PseudoSF_VC_V_FPR32VW_MF2, + PseudoSF_VC_V_FPR32VW_SE_M1, + PseudoSF_VC_V_FPR32VW_SE_M2, + PseudoSF_VC_V_FPR32VW_SE_M4, + PseudoSF_VC_V_FPR32VW_SE_M8, + PseudoSF_VC_V_FPR32VW_SE_MF2, + PseudoSF_VC_V_FPR32V_M1, + PseudoSF_VC_V_FPR32V_M2, + PseudoSF_VC_V_FPR32V_M4, + PseudoSF_VC_V_FPR32V_M8, + PseudoSF_VC_V_FPR32V_MF2, + PseudoSF_VC_V_FPR32V_SE_M1, + PseudoSF_VC_V_FPR32V_SE_M2, + PseudoSF_VC_V_FPR32V_SE_M4, + PseudoSF_VC_V_FPR32V_SE_M8, + PseudoSF_VC_V_FPR32V_SE_MF2, + PseudoSF_VC_V_FPR64VV_M1, + PseudoSF_VC_V_FPR64VV_M2, + PseudoSF_VC_V_FPR64VV_M4, + PseudoSF_VC_V_FPR64VV_M8, + PseudoSF_VC_V_FPR64VV_SE_M1, + PseudoSF_VC_V_FPR64VV_SE_M2, + PseudoSF_VC_V_FPR64VV_SE_M4, + PseudoSF_VC_V_FPR64VV_SE_M8, + PseudoSF_VC_V_FPR64V_M1, + PseudoSF_VC_V_FPR64V_M2, + PseudoSF_VC_V_FPR64V_M4, + PseudoSF_VC_V_FPR64V_M8, + PseudoSF_VC_V_FPR64V_SE_M1, + PseudoSF_VC_V_FPR64V_SE_M2, + PseudoSF_VC_V_FPR64V_SE_M4, + PseudoSF_VC_V_FPR64V_SE_M8, + PseudoSF_VC_V_IVV_M1, + PseudoSF_VC_V_IVV_M2, + PseudoSF_VC_V_IVV_M4, + PseudoSF_VC_V_IVV_M8, + PseudoSF_VC_V_IVV_MF2, + PseudoSF_VC_V_IVV_MF4, + PseudoSF_VC_V_IVV_MF8, + PseudoSF_VC_V_IVV_SE_M1, + PseudoSF_VC_V_IVV_SE_M2, + PseudoSF_VC_V_IVV_SE_M4, + PseudoSF_VC_V_IVV_SE_M8, + PseudoSF_VC_V_IVV_SE_MF2, + PseudoSF_VC_V_IVV_SE_MF4, + PseudoSF_VC_V_IVV_SE_MF8, + PseudoSF_VC_V_IVW_M1, + PseudoSF_VC_V_IVW_M2, + PseudoSF_VC_V_IVW_M4, + PseudoSF_VC_V_IVW_MF2, + PseudoSF_VC_V_IVW_MF4, + PseudoSF_VC_V_IVW_MF8, + PseudoSF_VC_V_IVW_SE_M1, + PseudoSF_VC_V_IVW_SE_M2, + PseudoSF_VC_V_IVW_SE_M4, + PseudoSF_VC_V_IVW_SE_MF2, + PseudoSF_VC_V_IVW_SE_MF4, + PseudoSF_VC_V_IVW_SE_MF8, + PseudoSF_VC_V_IV_M1, + PseudoSF_VC_V_IV_M2, + PseudoSF_VC_V_IV_M4, + PseudoSF_VC_V_IV_M8, + PseudoSF_VC_V_IV_MF2, + PseudoSF_VC_V_IV_MF4, + PseudoSF_VC_V_IV_MF8, + PseudoSF_VC_V_IV_SE_M1, + PseudoSF_VC_V_IV_SE_M2, + PseudoSF_VC_V_IV_SE_M4, + PseudoSF_VC_V_IV_SE_M8, + PseudoSF_VC_V_IV_SE_MF2, + PseudoSF_VC_V_IV_SE_MF4, + PseudoSF_VC_V_IV_SE_MF8, + PseudoSF_VC_V_I_M1, + PseudoSF_VC_V_I_M2, + PseudoSF_VC_V_I_M4, + PseudoSF_VC_V_I_M8, + PseudoSF_VC_V_I_MF2, + PseudoSF_VC_V_I_MF4, + PseudoSF_VC_V_I_MF8, + PseudoSF_VC_V_I_SE_M1, + PseudoSF_VC_V_I_SE_M2, + PseudoSF_VC_V_I_SE_M4, + PseudoSF_VC_V_I_SE_M8, + PseudoSF_VC_V_I_SE_MF2, + PseudoSF_VC_V_I_SE_MF4, + PseudoSF_VC_V_I_SE_MF8, + PseudoSF_VC_V_VVV_M1, + PseudoSF_VC_V_VVV_M2, + PseudoSF_VC_V_VVV_M4, + PseudoSF_VC_V_VVV_M8, + PseudoSF_VC_V_VVV_MF2, + PseudoSF_VC_V_VVV_MF4, + PseudoSF_VC_V_VVV_MF8, + PseudoSF_VC_V_VVV_SE_M1, + PseudoSF_VC_V_VVV_SE_M2, + PseudoSF_VC_V_VVV_SE_M4, + PseudoSF_VC_V_VVV_SE_M8, + PseudoSF_VC_V_VVV_SE_MF2, + PseudoSF_VC_V_VVV_SE_MF4, + PseudoSF_VC_V_VVV_SE_MF8, + PseudoSF_VC_V_VVW_M1, + PseudoSF_VC_V_VVW_M2, + PseudoSF_VC_V_VVW_M4, + PseudoSF_VC_V_VVW_MF2, + PseudoSF_VC_V_VVW_MF4, + PseudoSF_VC_V_VVW_MF8, + PseudoSF_VC_V_VVW_SE_M1, + PseudoSF_VC_V_VVW_SE_M2, + PseudoSF_VC_V_VVW_SE_M4, + PseudoSF_VC_V_VVW_SE_MF2, + PseudoSF_VC_V_VVW_SE_MF4, + PseudoSF_VC_V_VVW_SE_MF8, + PseudoSF_VC_V_VV_M1, + PseudoSF_VC_V_VV_M2, + PseudoSF_VC_V_VV_M4, + PseudoSF_VC_V_VV_M8, + PseudoSF_VC_V_VV_MF2, + PseudoSF_VC_V_VV_MF4, + PseudoSF_VC_V_VV_MF8, + PseudoSF_VC_V_VV_SE_M1, + PseudoSF_VC_V_VV_SE_M2, + PseudoSF_VC_V_VV_SE_M4, + PseudoSF_VC_V_VV_SE_M8, + PseudoSF_VC_V_VV_SE_MF2, + PseudoSF_VC_V_VV_SE_MF4, + PseudoSF_VC_V_VV_SE_MF8, + PseudoSF_VC_V_XVV_M1, + PseudoSF_VC_V_XVV_M2, + PseudoSF_VC_V_XVV_M4, + PseudoSF_VC_V_XVV_M8, + PseudoSF_VC_V_XVV_MF2, + PseudoSF_VC_V_XVV_MF4, + PseudoSF_VC_V_XVV_MF8, + PseudoSF_VC_V_XVV_SE_M1, + PseudoSF_VC_V_XVV_SE_M2, + PseudoSF_VC_V_XVV_SE_M4, + PseudoSF_VC_V_XVV_SE_M8, + PseudoSF_VC_V_XVV_SE_MF2, + PseudoSF_VC_V_XVV_SE_MF4, + PseudoSF_VC_V_XVV_SE_MF8, + PseudoSF_VC_V_XVW_M1, + PseudoSF_VC_V_XVW_M2, + PseudoSF_VC_V_XVW_M4, + PseudoSF_VC_V_XVW_MF2, + PseudoSF_VC_V_XVW_MF4, + PseudoSF_VC_V_XVW_MF8, + PseudoSF_VC_V_XVW_SE_M1, + PseudoSF_VC_V_XVW_SE_M2, + PseudoSF_VC_V_XVW_SE_M4, + PseudoSF_VC_V_XVW_SE_MF2, + PseudoSF_VC_V_XVW_SE_MF4, + PseudoSF_VC_V_XVW_SE_MF8, + PseudoSF_VC_V_XV_M1, + PseudoSF_VC_V_XV_M2, + PseudoSF_VC_V_XV_M4, + PseudoSF_VC_V_XV_M8, + PseudoSF_VC_V_XV_MF2, + PseudoSF_VC_V_XV_MF4, + PseudoSF_VC_V_XV_MF8, + PseudoSF_VC_V_XV_SE_M1, + PseudoSF_VC_V_XV_SE_M2, + PseudoSF_VC_V_XV_SE_M4, + PseudoSF_VC_V_XV_SE_M8, + PseudoSF_VC_V_XV_SE_MF2, + PseudoSF_VC_V_XV_SE_MF4, + PseudoSF_VC_V_XV_SE_MF8, + PseudoSF_VC_V_X_M1, + PseudoSF_VC_V_X_M2, + PseudoSF_VC_V_X_M4, + PseudoSF_VC_V_X_M8, + PseudoSF_VC_V_X_MF2, + PseudoSF_VC_V_X_MF4, + PseudoSF_VC_V_X_MF8, + PseudoSF_VC_V_X_SE_M1, + PseudoSF_VC_V_X_SE_M2, + PseudoSF_VC_V_X_SE_M4, + PseudoSF_VC_V_X_SE_M8, + PseudoSF_VC_V_X_SE_MF2, + PseudoSF_VC_V_X_SE_MF4, + PseudoSF_VC_V_X_SE_MF8, + PseudoSF_VC_XVV_SE_M1, + PseudoSF_VC_XVV_SE_M2, + PseudoSF_VC_XVV_SE_M4, + PseudoSF_VC_XVV_SE_M8, + PseudoSF_VC_XVV_SE_MF2, + PseudoSF_VC_XVV_SE_MF4, + PseudoSF_VC_XVV_SE_MF8, + PseudoSF_VC_XVW_SE_M1, + PseudoSF_VC_XVW_SE_M2, + PseudoSF_VC_XVW_SE_M4, + PseudoSF_VC_XVW_SE_MF2, + PseudoSF_VC_XVW_SE_MF4, + PseudoSF_VC_XVW_SE_MF8, + PseudoSF_VC_XV_SE_M1, + PseudoSF_VC_XV_SE_M2, + PseudoSF_VC_XV_SE_M4, + PseudoSF_VC_XV_SE_M8, + PseudoSF_VC_XV_SE_MF2, + PseudoSF_VC_XV_SE_MF4, + PseudoSF_VC_XV_SE_MF8, + PseudoSF_VC_X_SE_M1, + PseudoSF_VC_X_SE_M2, + PseudoSF_VC_X_SE_M4, + PseudoSF_VC_X_SE_M8, + PseudoSF_VC_X_SE_MF2, + PseudoSF_VC_X_SE_MF4, + PseudoSF_VC_X_SE_MF8, + PseudoSF_VFEXPA_V_M1_E16, + PseudoSF_VFEXPA_V_M1_E16_MASK, + PseudoSF_VFEXPA_V_M1_E32, + PseudoSF_VFEXPA_V_M1_E32_MASK, + PseudoSF_VFEXPA_V_M1_E64, + PseudoSF_VFEXPA_V_M1_E64_MASK, + PseudoSF_VFEXPA_V_M2_E16, + PseudoSF_VFEXPA_V_M2_E16_MASK, + PseudoSF_VFEXPA_V_M2_E32, + PseudoSF_VFEXPA_V_M2_E32_MASK, + PseudoSF_VFEXPA_V_M2_E64, + PseudoSF_VFEXPA_V_M2_E64_MASK, + PseudoSF_VFEXPA_V_M4_E16, + PseudoSF_VFEXPA_V_M4_E16_MASK, + PseudoSF_VFEXPA_V_M4_E32, + PseudoSF_VFEXPA_V_M4_E32_MASK, + PseudoSF_VFEXPA_V_M4_E64, + PseudoSF_VFEXPA_V_M4_E64_MASK, + PseudoSF_VFEXPA_V_M8_E16, + PseudoSF_VFEXPA_V_M8_E16_MASK, + PseudoSF_VFEXPA_V_M8_E32, + PseudoSF_VFEXPA_V_M8_E32_MASK, + PseudoSF_VFEXPA_V_M8_E64, + PseudoSF_VFEXPA_V_M8_E64_MASK, + PseudoSF_VFEXPA_V_MF2_E16, + PseudoSF_VFEXPA_V_MF2_E16_MASK, + PseudoSF_VFEXPA_V_MF2_E32, + PseudoSF_VFEXPA_V_MF2_E32_MASK, + PseudoSF_VFEXPA_V_MF4_E16, + PseudoSF_VFEXPA_V_MF4_E16_MASK, + PseudoSF_VFEXP_ALT_V_M1_E16, + PseudoSF_VFEXP_ALT_V_M1_E16_MASK, + PseudoSF_VFEXP_ALT_V_M2_E16, + PseudoSF_VFEXP_ALT_V_M2_E16_MASK, + PseudoSF_VFEXP_ALT_V_M4_E16, + PseudoSF_VFEXP_ALT_V_M4_E16_MASK, + PseudoSF_VFEXP_ALT_V_M8_E16, + PseudoSF_VFEXP_ALT_V_M8_E16_MASK, + PseudoSF_VFEXP_ALT_V_MF2_E16, + PseudoSF_VFEXP_ALT_V_MF2_E16_MASK, + PseudoSF_VFEXP_ALT_V_MF4_E16, + PseudoSF_VFEXP_ALT_V_MF4_E16_MASK, + PseudoSF_VFEXP_V_M1_E16, + PseudoSF_VFEXP_V_M1_E16_MASK, + PseudoSF_VFEXP_V_M1_E32, + PseudoSF_VFEXP_V_M1_E32_MASK, + PseudoSF_VFEXP_V_M2_E16, + PseudoSF_VFEXP_V_M2_E16_MASK, + PseudoSF_VFEXP_V_M2_E32, + PseudoSF_VFEXP_V_M2_E32_MASK, + PseudoSF_VFEXP_V_M4_E16, + PseudoSF_VFEXP_V_M4_E16_MASK, + PseudoSF_VFEXP_V_M4_E32, + PseudoSF_VFEXP_V_M4_E32_MASK, + PseudoSF_VFEXP_V_M8_E16, + PseudoSF_VFEXP_V_M8_E16_MASK, + PseudoSF_VFEXP_V_M8_E32, + PseudoSF_VFEXP_V_M8_E32_MASK, + PseudoSF_VFEXP_V_MF2_E16, + PseudoSF_VFEXP_V_MF2_E16_MASK, + PseudoSF_VFEXP_V_MF2_E32, + PseudoSF_VFEXP_V_MF2_E32_MASK, + PseudoSF_VFEXP_V_MF4_E16, + PseudoSF_VFEXP_V_MF4_E16_MASK, + PseudoSF_VFNRCLIP_XU_F_QF_M1, + PseudoSF_VFNRCLIP_XU_F_QF_M1_MASK, + PseudoSF_VFNRCLIP_XU_F_QF_M2, + PseudoSF_VFNRCLIP_XU_F_QF_M2_MASK, + PseudoSF_VFNRCLIP_XU_F_QF_MF2, + PseudoSF_VFNRCLIP_XU_F_QF_MF2_MASK, + PseudoSF_VFNRCLIP_XU_F_QF_MF4, + PseudoSF_VFNRCLIP_XU_F_QF_MF4_MASK, + PseudoSF_VFNRCLIP_XU_F_QF_MF8, + PseudoSF_VFNRCLIP_XU_F_QF_MF8_MASK, + PseudoSF_VFNRCLIP_X_F_QF_M1, + PseudoSF_VFNRCLIP_X_F_QF_M1_MASK, + PseudoSF_VFNRCLIP_X_F_QF_M2, + PseudoSF_VFNRCLIP_X_F_QF_M2_MASK, + PseudoSF_VFNRCLIP_X_F_QF_MF2, + PseudoSF_VFNRCLIP_X_F_QF_MF2_MASK, + PseudoSF_VFNRCLIP_X_F_QF_MF4, + PseudoSF_VFNRCLIP_X_F_QF_MF4_MASK, + PseudoSF_VFNRCLIP_X_F_QF_MF8, + PseudoSF_VFNRCLIP_X_F_QF_MF8_MASK, + PseudoSF_VFWMACC_4x4x4_M1, + PseudoSF_VFWMACC_4x4x4_M2, + PseudoSF_VFWMACC_4x4x4_M4, + PseudoSF_VFWMACC_4x4x4_MF2, + PseudoSF_VFWMACC_4x4x4_MF4, + PseudoSF_VLTE16, + PseudoSF_VLTE32, + PseudoSF_VLTE64, + PseudoSF_VLTE8, + PseudoSF_VQMACCSU_2x8x2_M1, + PseudoSF_VQMACCSU_2x8x2_M2, + PseudoSF_VQMACCSU_2x8x2_M4, + PseudoSF_VQMACCSU_2x8x2_M8, + PseudoSF_VQMACCSU_4x8x4_M1, + PseudoSF_VQMACCSU_4x8x4_M2, + PseudoSF_VQMACCSU_4x8x4_M4, + PseudoSF_VQMACCSU_4x8x4_MF2, + PseudoSF_VQMACCUS_2x8x2_M1, + PseudoSF_VQMACCUS_2x8x2_M2, + PseudoSF_VQMACCUS_2x8x2_M4, + PseudoSF_VQMACCUS_2x8x2_M8, + PseudoSF_VQMACCUS_4x8x4_M1, + PseudoSF_VQMACCUS_4x8x4_M2, + PseudoSF_VQMACCUS_4x8x4_M4, + PseudoSF_VQMACCUS_4x8x4_MF2, + PseudoSF_VQMACCU_2x8x2_M1, + PseudoSF_VQMACCU_2x8x2_M2, + PseudoSF_VQMACCU_2x8x2_M4, + PseudoSF_VQMACCU_2x8x2_M8, + PseudoSF_VQMACCU_4x8x4_M1, + PseudoSF_VQMACCU_4x8x4_M2, + PseudoSF_VQMACCU_4x8x4_M4, + PseudoSF_VQMACCU_4x8x4_MF2, + PseudoSF_VQMACC_2x8x2_M1, + PseudoSF_VQMACC_2x8x2_M2, + PseudoSF_VQMACC_2x8x2_M4, + PseudoSF_VQMACC_2x8x2_M8, + PseudoSF_VQMACC_4x8x4_M1, + PseudoSF_VQMACC_4x8x4_M2, + PseudoSF_VQMACC_4x8x4_M4, + PseudoSF_VQMACC_4x8x4_MF2, + PseudoSF_VSETTK, + PseudoSF_VSETTM, + PseudoSF_VSETTNT, + PseudoSF_VSETTNTX0, + PseudoSF_VSETTNTX0X0, + PseudoSF_VSTE16, + PseudoSF_VSTE32, + PseudoSF_VSTE64, + PseudoSF_VSTE8, + PseudoSF_VTDISCARD, + PseudoSF_VTMV_T_V, + PseudoSF_VTMV_V_T, + PseudoSF_VTZERO_T, + PseudoSH, + PseudoSW, + PseudoTAIL, + PseudoTAILIndirect, + PseudoTAILIndirectNonX7, + PseudoTAILIndirectX7, + PseudoTH_VMAQASU_VV_M1, + PseudoTH_VMAQASU_VV_M1_MASK, + PseudoTH_VMAQASU_VV_M2, + PseudoTH_VMAQASU_VV_M2_MASK, + PseudoTH_VMAQASU_VV_M4, + PseudoTH_VMAQASU_VV_M4_MASK, + PseudoTH_VMAQASU_VV_M8, + PseudoTH_VMAQASU_VV_M8_MASK, + PseudoTH_VMAQASU_VV_MF2, + PseudoTH_VMAQASU_VV_MF2_MASK, + PseudoTH_VMAQASU_VX_M1, + PseudoTH_VMAQASU_VX_M1_MASK, + PseudoTH_VMAQASU_VX_M2, + PseudoTH_VMAQASU_VX_M2_MASK, + PseudoTH_VMAQASU_VX_M4, + PseudoTH_VMAQASU_VX_M4_MASK, + PseudoTH_VMAQASU_VX_M8, + PseudoTH_VMAQASU_VX_M8_MASK, + PseudoTH_VMAQASU_VX_MF2, + PseudoTH_VMAQASU_VX_MF2_MASK, + PseudoTH_VMAQAUS_VX_M1, + PseudoTH_VMAQAUS_VX_M1_MASK, + PseudoTH_VMAQAUS_VX_M2, + PseudoTH_VMAQAUS_VX_M2_MASK, + PseudoTH_VMAQAUS_VX_M4, + PseudoTH_VMAQAUS_VX_M4_MASK, + PseudoTH_VMAQAUS_VX_M8, + PseudoTH_VMAQAUS_VX_M8_MASK, + PseudoTH_VMAQAUS_VX_MF2, + PseudoTH_VMAQAUS_VX_MF2_MASK, + PseudoTH_VMAQAU_VV_M1, + PseudoTH_VMAQAU_VV_M1_MASK, + PseudoTH_VMAQAU_VV_M2, + PseudoTH_VMAQAU_VV_M2_MASK, + PseudoTH_VMAQAU_VV_M4, + PseudoTH_VMAQAU_VV_M4_MASK, + PseudoTH_VMAQAU_VV_M8, + PseudoTH_VMAQAU_VV_M8_MASK, + PseudoTH_VMAQAU_VV_MF2, + PseudoTH_VMAQAU_VV_MF2_MASK, + PseudoTH_VMAQAU_VX_M1, + PseudoTH_VMAQAU_VX_M1_MASK, + PseudoTH_VMAQAU_VX_M2, + PseudoTH_VMAQAU_VX_M2_MASK, + PseudoTH_VMAQAU_VX_M4, + PseudoTH_VMAQAU_VX_M4_MASK, + PseudoTH_VMAQAU_VX_M8, + PseudoTH_VMAQAU_VX_M8_MASK, + PseudoTH_VMAQAU_VX_MF2, + PseudoTH_VMAQAU_VX_MF2_MASK, + PseudoTH_VMAQA_VV_M1, + PseudoTH_VMAQA_VV_M1_MASK, + PseudoTH_VMAQA_VV_M2, + PseudoTH_VMAQA_VV_M2_MASK, + PseudoTH_VMAQA_VV_M4, + PseudoTH_VMAQA_VV_M4_MASK, + PseudoTH_VMAQA_VV_M8, + PseudoTH_VMAQA_VV_M8_MASK, + PseudoTH_VMAQA_VV_MF2, + PseudoTH_VMAQA_VV_MF2_MASK, + PseudoTH_VMAQA_VX_M1, + PseudoTH_VMAQA_VX_M1_MASK, + PseudoTH_VMAQA_VX_M2, + PseudoTH_VMAQA_VX_M2_MASK, + PseudoTH_VMAQA_VX_M4, + PseudoTH_VMAQA_VX_M4_MASK, + PseudoTH_VMAQA_VX_M8, + PseudoTH_VMAQA_VX_M8_MASK, + PseudoTH_VMAQA_VX_MF2, + PseudoTH_VMAQA_VX_MF2_MASK, + PseudoTLSDESCCall, + PseudoVAADDU_VV_M1, + PseudoVAADDU_VV_M1_MASK, + PseudoVAADDU_VV_M2, + PseudoVAADDU_VV_M2_MASK, + PseudoVAADDU_VV_M4, + PseudoVAADDU_VV_M4_MASK, + PseudoVAADDU_VV_M8, + PseudoVAADDU_VV_M8_MASK, + PseudoVAADDU_VV_MF2, + PseudoVAADDU_VV_MF2_MASK, + PseudoVAADDU_VV_MF4, + PseudoVAADDU_VV_MF4_MASK, + PseudoVAADDU_VV_MF8, + PseudoVAADDU_VV_MF8_MASK, + PseudoVAADDU_VX_M1, + PseudoVAADDU_VX_M1_MASK, + PseudoVAADDU_VX_M2, + PseudoVAADDU_VX_M2_MASK, + PseudoVAADDU_VX_M4, + PseudoVAADDU_VX_M4_MASK, + PseudoVAADDU_VX_M8, + PseudoVAADDU_VX_M8_MASK, + PseudoVAADDU_VX_MF2, + PseudoVAADDU_VX_MF2_MASK, + PseudoVAADDU_VX_MF4, + PseudoVAADDU_VX_MF4_MASK, + PseudoVAADDU_VX_MF8, + PseudoVAADDU_VX_MF8_MASK, + PseudoVAADD_VV_M1, + PseudoVAADD_VV_M1_MASK, + PseudoVAADD_VV_M2, + PseudoVAADD_VV_M2_MASK, + PseudoVAADD_VV_M4, + PseudoVAADD_VV_M4_MASK, + PseudoVAADD_VV_M8, + PseudoVAADD_VV_M8_MASK, + PseudoVAADD_VV_MF2, + PseudoVAADD_VV_MF2_MASK, + PseudoVAADD_VV_MF4, + PseudoVAADD_VV_MF4_MASK, + PseudoVAADD_VV_MF8, + PseudoVAADD_VV_MF8_MASK, + PseudoVAADD_VX_M1, + PseudoVAADD_VX_M1_MASK, + PseudoVAADD_VX_M2, + PseudoVAADD_VX_M2_MASK, + PseudoVAADD_VX_M4, + PseudoVAADD_VX_M4_MASK, + PseudoVAADD_VX_M8, + PseudoVAADD_VX_M8_MASK, + PseudoVAADD_VX_MF2, + PseudoVAADD_VX_MF2_MASK, + PseudoVAADD_VX_MF4, + PseudoVAADD_VX_MF4_MASK, + PseudoVAADD_VX_MF8, + PseudoVAADD_VX_MF8_MASK, + PseudoVADC_VIM_M1, + PseudoVADC_VIM_M2, + PseudoVADC_VIM_M4, + PseudoVADC_VIM_M8, + PseudoVADC_VIM_MF2, + PseudoVADC_VIM_MF4, + PseudoVADC_VIM_MF8, + PseudoVADC_VVM_M1, + PseudoVADC_VVM_M2, + PseudoVADC_VVM_M4, + PseudoVADC_VVM_M8, + PseudoVADC_VVM_MF2, + PseudoVADC_VVM_MF4, + PseudoVADC_VVM_MF8, + PseudoVADC_VXM_M1, + PseudoVADC_VXM_M2, + PseudoVADC_VXM_M4, + PseudoVADC_VXM_M8, + PseudoVADC_VXM_MF2, + PseudoVADC_VXM_MF4, + PseudoVADC_VXM_MF8, + PseudoVADD_VI_M1, + PseudoVADD_VI_M1_MASK, + PseudoVADD_VI_M2, + PseudoVADD_VI_M2_MASK, + PseudoVADD_VI_M4, + PseudoVADD_VI_M4_MASK, + PseudoVADD_VI_M8, + PseudoVADD_VI_M8_MASK, + PseudoVADD_VI_MF2, + PseudoVADD_VI_MF2_MASK, + PseudoVADD_VI_MF4, + PseudoVADD_VI_MF4_MASK, + PseudoVADD_VI_MF8, + PseudoVADD_VI_MF8_MASK, + PseudoVADD_VV_M1, + PseudoVADD_VV_M1_MASK, + PseudoVADD_VV_M2, + PseudoVADD_VV_M2_MASK, + PseudoVADD_VV_M4, + PseudoVADD_VV_M4_MASK, + PseudoVADD_VV_M8, + PseudoVADD_VV_M8_MASK, + PseudoVADD_VV_MF2, + PseudoVADD_VV_MF2_MASK, + PseudoVADD_VV_MF4, + PseudoVADD_VV_MF4_MASK, + PseudoVADD_VV_MF8, + PseudoVADD_VV_MF8_MASK, + PseudoVADD_VX_M1, + PseudoVADD_VX_M1_MASK, + PseudoVADD_VX_M2, + PseudoVADD_VX_M2_MASK, + PseudoVADD_VX_M4, + PseudoVADD_VX_M4_MASK, + PseudoVADD_VX_M8, + PseudoVADD_VX_M8_MASK, + PseudoVADD_VX_MF2, + PseudoVADD_VX_MF2_MASK, + PseudoVADD_VX_MF4, + PseudoVADD_VX_MF4_MASK, + PseudoVADD_VX_MF8, + PseudoVADD_VX_MF8_MASK, + PseudoVAESDF_VS_M1_M1, + PseudoVAESDF_VS_M1_MF2, + PseudoVAESDF_VS_M1_MF4, + PseudoVAESDF_VS_M1_MF8, + PseudoVAESDF_VS_M2_M1, + PseudoVAESDF_VS_M2_M2, + PseudoVAESDF_VS_M2_MF2, + PseudoVAESDF_VS_M2_MF4, + PseudoVAESDF_VS_M2_MF8, + PseudoVAESDF_VS_M4_M1, + PseudoVAESDF_VS_M4_M2, + PseudoVAESDF_VS_M4_M4, + PseudoVAESDF_VS_M4_MF2, + PseudoVAESDF_VS_M4_MF4, + PseudoVAESDF_VS_M4_MF8, + PseudoVAESDF_VS_M8_M1, + PseudoVAESDF_VS_M8_M2, + PseudoVAESDF_VS_M8_M4, + PseudoVAESDF_VS_M8_MF2, + PseudoVAESDF_VS_M8_MF4, + PseudoVAESDF_VS_M8_MF8, + PseudoVAESDF_VS_MF2_MF2, + PseudoVAESDF_VS_MF2_MF4, + PseudoVAESDF_VS_MF2_MF8, + PseudoVAESDF_VV_M1, + PseudoVAESDF_VV_M2, + PseudoVAESDF_VV_M4, + PseudoVAESDF_VV_M8, + PseudoVAESDF_VV_MF2, + PseudoVAESDM_VS_M1_M1, + PseudoVAESDM_VS_M1_MF2, + PseudoVAESDM_VS_M1_MF4, + PseudoVAESDM_VS_M1_MF8, + PseudoVAESDM_VS_M2_M1, + PseudoVAESDM_VS_M2_M2, + PseudoVAESDM_VS_M2_MF2, + PseudoVAESDM_VS_M2_MF4, + PseudoVAESDM_VS_M2_MF8, + PseudoVAESDM_VS_M4_M1, + PseudoVAESDM_VS_M4_M2, + PseudoVAESDM_VS_M4_M4, + PseudoVAESDM_VS_M4_MF2, + PseudoVAESDM_VS_M4_MF4, + PseudoVAESDM_VS_M4_MF8, + PseudoVAESDM_VS_M8_M1, + PseudoVAESDM_VS_M8_M2, + PseudoVAESDM_VS_M8_M4, + PseudoVAESDM_VS_M8_MF2, + PseudoVAESDM_VS_M8_MF4, + PseudoVAESDM_VS_M8_MF8, + PseudoVAESDM_VS_MF2_MF2, + PseudoVAESDM_VS_MF2_MF4, + PseudoVAESDM_VS_MF2_MF8, + PseudoVAESDM_VV_M1, + PseudoVAESDM_VV_M2, + PseudoVAESDM_VV_M4, + PseudoVAESDM_VV_M8, + PseudoVAESDM_VV_MF2, + PseudoVAESEF_VS_M1_M1, + PseudoVAESEF_VS_M1_MF2, + PseudoVAESEF_VS_M1_MF4, + PseudoVAESEF_VS_M1_MF8, + PseudoVAESEF_VS_M2_M1, + PseudoVAESEF_VS_M2_M2, + PseudoVAESEF_VS_M2_MF2, + PseudoVAESEF_VS_M2_MF4, + PseudoVAESEF_VS_M2_MF8, + PseudoVAESEF_VS_M4_M1, + PseudoVAESEF_VS_M4_M2, + PseudoVAESEF_VS_M4_M4, + PseudoVAESEF_VS_M4_MF2, + PseudoVAESEF_VS_M4_MF4, + PseudoVAESEF_VS_M4_MF8, + PseudoVAESEF_VS_M8_M1, + PseudoVAESEF_VS_M8_M2, + PseudoVAESEF_VS_M8_M4, + PseudoVAESEF_VS_M8_MF2, + PseudoVAESEF_VS_M8_MF4, + PseudoVAESEF_VS_M8_MF8, + PseudoVAESEF_VS_MF2_MF2, + PseudoVAESEF_VS_MF2_MF4, + PseudoVAESEF_VS_MF2_MF8, + PseudoVAESEF_VV_M1, + PseudoVAESEF_VV_M2, + PseudoVAESEF_VV_M4, + PseudoVAESEF_VV_M8, + PseudoVAESEF_VV_MF2, + PseudoVAESEM_VS_M1_M1, + PseudoVAESEM_VS_M1_MF2, + PseudoVAESEM_VS_M1_MF4, + PseudoVAESEM_VS_M1_MF8, + PseudoVAESEM_VS_M2_M1, + PseudoVAESEM_VS_M2_M2, + PseudoVAESEM_VS_M2_MF2, + PseudoVAESEM_VS_M2_MF4, + PseudoVAESEM_VS_M2_MF8, + PseudoVAESEM_VS_M4_M1, + PseudoVAESEM_VS_M4_M2, + PseudoVAESEM_VS_M4_M4, + PseudoVAESEM_VS_M4_MF2, + PseudoVAESEM_VS_M4_MF4, + PseudoVAESEM_VS_M4_MF8, + PseudoVAESEM_VS_M8_M1, + PseudoVAESEM_VS_M8_M2, + PseudoVAESEM_VS_M8_M4, + PseudoVAESEM_VS_M8_MF2, + PseudoVAESEM_VS_M8_MF4, + PseudoVAESEM_VS_M8_MF8, + PseudoVAESEM_VS_MF2_MF2, + PseudoVAESEM_VS_MF2_MF4, + PseudoVAESEM_VS_MF2_MF8, + PseudoVAESEM_VV_M1, + PseudoVAESEM_VV_M2, + PseudoVAESEM_VV_M4, + PseudoVAESEM_VV_M8, + PseudoVAESEM_VV_MF2, + PseudoVAESKF1_VI_M1, + PseudoVAESKF1_VI_M2, + PseudoVAESKF1_VI_M4, + PseudoVAESKF1_VI_M8, + PseudoVAESKF1_VI_MF2, + PseudoVAESKF2_VI_M1, + PseudoVAESKF2_VI_M2, + PseudoVAESKF2_VI_M4, + PseudoVAESKF2_VI_M8, + PseudoVAESKF2_VI_MF2, + PseudoVAESZ_VS_M1_M1, + PseudoVAESZ_VS_M1_MF2, + PseudoVAESZ_VS_M1_MF4, + PseudoVAESZ_VS_M1_MF8, + PseudoVAESZ_VS_M2_M1, + PseudoVAESZ_VS_M2_M2, + PseudoVAESZ_VS_M2_MF2, + PseudoVAESZ_VS_M2_MF4, + PseudoVAESZ_VS_M2_MF8, + PseudoVAESZ_VS_M4_M1, + PseudoVAESZ_VS_M4_M2, + PseudoVAESZ_VS_M4_M4, + PseudoVAESZ_VS_M4_MF2, + PseudoVAESZ_VS_M4_MF4, + PseudoVAESZ_VS_M4_MF8, + PseudoVAESZ_VS_M8_M1, + PseudoVAESZ_VS_M8_M2, + PseudoVAESZ_VS_M8_M4, + PseudoVAESZ_VS_M8_MF2, + PseudoVAESZ_VS_M8_MF4, + PseudoVAESZ_VS_M8_MF8, + PseudoVAESZ_VS_MF2_MF2, + PseudoVAESZ_VS_MF2_MF4, + PseudoVAESZ_VS_MF2_MF8, + PseudoVANDN_VV_M1, + PseudoVANDN_VV_M1_MASK, + PseudoVANDN_VV_M2, + PseudoVANDN_VV_M2_MASK, + PseudoVANDN_VV_M4, + PseudoVANDN_VV_M4_MASK, + PseudoVANDN_VV_M8, + PseudoVANDN_VV_M8_MASK, + PseudoVANDN_VV_MF2, + PseudoVANDN_VV_MF2_MASK, + PseudoVANDN_VV_MF4, + PseudoVANDN_VV_MF4_MASK, + PseudoVANDN_VV_MF8, + PseudoVANDN_VV_MF8_MASK, + PseudoVANDN_VX_M1, + PseudoVANDN_VX_M1_MASK, + PseudoVANDN_VX_M2, + PseudoVANDN_VX_M2_MASK, + PseudoVANDN_VX_M4, + PseudoVANDN_VX_M4_MASK, + PseudoVANDN_VX_M8, + PseudoVANDN_VX_M8_MASK, + PseudoVANDN_VX_MF2, + PseudoVANDN_VX_MF2_MASK, + PseudoVANDN_VX_MF4, + PseudoVANDN_VX_MF4_MASK, + PseudoVANDN_VX_MF8, + PseudoVANDN_VX_MF8_MASK, + PseudoVAND_VI_M1, + PseudoVAND_VI_M1_MASK, + PseudoVAND_VI_M2, + PseudoVAND_VI_M2_MASK, + PseudoVAND_VI_M4, + PseudoVAND_VI_M4_MASK, + PseudoVAND_VI_M8, + PseudoVAND_VI_M8_MASK, + PseudoVAND_VI_MF2, + PseudoVAND_VI_MF2_MASK, + PseudoVAND_VI_MF4, + PseudoVAND_VI_MF4_MASK, + PseudoVAND_VI_MF8, + PseudoVAND_VI_MF8_MASK, + PseudoVAND_VV_M1, + PseudoVAND_VV_M1_MASK, + PseudoVAND_VV_M2, + PseudoVAND_VV_M2_MASK, + PseudoVAND_VV_M4, + PseudoVAND_VV_M4_MASK, + PseudoVAND_VV_M8, + PseudoVAND_VV_M8_MASK, + PseudoVAND_VV_MF2, + PseudoVAND_VV_MF2_MASK, + PseudoVAND_VV_MF4, + PseudoVAND_VV_MF4_MASK, + PseudoVAND_VV_MF8, + PseudoVAND_VV_MF8_MASK, + PseudoVAND_VX_M1, + PseudoVAND_VX_M1_MASK, + PseudoVAND_VX_M2, + PseudoVAND_VX_M2_MASK, + PseudoVAND_VX_M4, + PseudoVAND_VX_M4_MASK, + PseudoVAND_VX_M8, + PseudoVAND_VX_M8_MASK, + PseudoVAND_VX_MF2, + PseudoVAND_VX_MF2_MASK, + PseudoVAND_VX_MF4, + PseudoVAND_VX_MF4_MASK, + PseudoVAND_VX_MF8, + PseudoVAND_VX_MF8_MASK, + PseudoVASUBU_VV_M1, + PseudoVASUBU_VV_M1_MASK, + PseudoVASUBU_VV_M2, + PseudoVASUBU_VV_M2_MASK, + PseudoVASUBU_VV_M4, + PseudoVASUBU_VV_M4_MASK, + PseudoVASUBU_VV_M8, + PseudoVASUBU_VV_M8_MASK, + PseudoVASUBU_VV_MF2, + PseudoVASUBU_VV_MF2_MASK, + PseudoVASUBU_VV_MF4, + PseudoVASUBU_VV_MF4_MASK, + PseudoVASUBU_VV_MF8, + PseudoVASUBU_VV_MF8_MASK, + PseudoVASUBU_VX_M1, + PseudoVASUBU_VX_M1_MASK, + PseudoVASUBU_VX_M2, + PseudoVASUBU_VX_M2_MASK, + PseudoVASUBU_VX_M4, + PseudoVASUBU_VX_M4_MASK, + PseudoVASUBU_VX_M8, + PseudoVASUBU_VX_M8_MASK, + PseudoVASUBU_VX_MF2, + PseudoVASUBU_VX_MF2_MASK, + PseudoVASUBU_VX_MF4, + PseudoVASUBU_VX_MF4_MASK, + PseudoVASUBU_VX_MF8, + PseudoVASUBU_VX_MF8_MASK, + PseudoVASUB_VV_M1, + PseudoVASUB_VV_M1_MASK, + PseudoVASUB_VV_M2, + PseudoVASUB_VV_M2_MASK, + PseudoVASUB_VV_M4, + PseudoVASUB_VV_M4_MASK, + PseudoVASUB_VV_M8, + PseudoVASUB_VV_M8_MASK, + PseudoVASUB_VV_MF2, + PseudoVASUB_VV_MF2_MASK, + PseudoVASUB_VV_MF4, + PseudoVASUB_VV_MF4_MASK, + PseudoVASUB_VV_MF8, + PseudoVASUB_VV_MF8_MASK, + PseudoVASUB_VX_M1, + PseudoVASUB_VX_M1_MASK, + PseudoVASUB_VX_M2, + PseudoVASUB_VX_M2_MASK, + PseudoVASUB_VX_M4, + PseudoVASUB_VX_M4_MASK, + PseudoVASUB_VX_M8, + PseudoVASUB_VX_M8_MASK, + PseudoVASUB_VX_MF2, + PseudoVASUB_VX_MF2_MASK, + PseudoVASUB_VX_MF4, + PseudoVASUB_VX_MF4_MASK, + PseudoVASUB_VX_MF8, + PseudoVASUB_VX_MF8_MASK, + PseudoVBREV8_V_M1, + PseudoVBREV8_V_M1_MASK, + PseudoVBREV8_V_M2, + PseudoVBREV8_V_M2_MASK, + PseudoVBREV8_V_M4, + PseudoVBREV8_V_M4_MASK, + PseudoVBREV8_V_M8, + PseudoVBREV8_V_M8_MASK, + PseudoVBREV8_V_MF2, + PseudoVBREV8_V_MF2_MASK, + PseudoVBREV8_V_MF4, + PseudoVBREV8_V_MF4_MASK, + PseudoVBREV8_V_MF8, + PseudoVBREV8_V_MF8_MASK, + PseudoVBREV_V_M1, + PseudoVBREV_V_M1_MASK, + PseudoVBREV_V_M2, + PseudoVBREV_V_M2_MASK, + PseudoVBREV_V_M4, + PseudoVBREV_V_M4_MASK, + PseudoVBREV_V_M8, + PseudoVBREV_V_M8_MASK, + PseudoVBREV_V_MF2, + PseudoVBREV_V_MF2_MASK, + PseudoVBREV_V_MF4, + PseudoVBREV_V_MF4_MASK, + PseudoVBREV_V_MF8, + PseudoVBREV_V_MF8_MASK, + PseudoVCLMULH_VV_M1, + PseudoVCLMULH_VV_M1_MASK, + PseudoVCLMULH_VV_M2, + PseudoVCLMULH_VV_M2_MASK, + PseudoVCLMULH_VV_M4, + PseudoVCLMULH_VV_M4_MASK, + PseudoVCLMULH_VV_M8, + PseudoVCLMULH_VV_M8_MASK, + PseudoVCLMULH_VV_MF2, + PseudoVCLMULH_VV_MF2_MASK, + PseudoVCLMULH_VV_MF4, + PseudoVCLMULH_VV_MF4_MASK, + PseudoVCLMULH_VV_MF8, + PseudoVCLMULH_VV_MF8_MASK, + PseudoVCLMULH_VX_M1, + PseudoVCLMULH_VX_M1_MASK, + PseudoVCLMULH_VX_M2, + PseudoVCLMULH_VX_M2_MASK, + PseudoVCLMULH_VX_M4, + PseudoVCLMULH_VX_M4_MASK, + PseudoVCLMULH_VX_M8, + PseudoVCLMULH_VX_M8_MASK, + PseudoVCLMULH_VX_MF2, + PseudoVCLMULH_VX_MF2_MASK, + PseudoVCLMULH_VX_MF4, + PseudoVCLMULH_VX_MF4_MASK, + PseudoVCLMULH_VX_MF8, + PseudoVCLMULH_VX_MF8_MASK, + PseudoVCLMUL_VV_M1, + PseudoVCLMUL_VV_M1_MASK, + PseudoVCLMUL_VV_M2, + PseudoVCLMUL_VV_M2_MASK, + PseudoVCLMUL_VV_M4, + PseudoVCLMUL_VV_M4_MASK, + PseudoVCLMUL_VV_M8, + PseudoVCLMUL_VV_M8_MASK, + PseudoVCLMUL_VV_MF2, + PseudoVCLMUL_VV_MF2_MASK, + PseudoVCLMUL_VV_MF4, + PseudoVCLMUL_VV_MF4_MASK, + PseudoVCLMUL_VV_MF8, + PseudoVCLMUL_VV_MF8_MASK, + PseudoVCLMUL_VX_M1, + PseudoVCLMUL_VX_M1_MASK, + PseudoVCLMUL_VX_M2, + PseudoVCLMUL_VX_M2_MASK, + PseudoVCLMUL_VX_M4, + PseudoVCLMUL_VX_M4_MASK, + PseudoVCLMUL_VX_M8, + PseudoVCLMUL_VX_M8_MASK, + PseudoVCLMUL_VX_MF2, + PseudoVCLMUL_VX_MF2_MASK, + PseudoVCLMUL_VX_MF4, + PseudoVCLMUL_VX_MF4_MASK, + PseudoVCLMUL_VX_MF8, + PseudoVCLMUL_VX_MF8_MASK, + PseudoVCLZ_V_M1, + PseudoVCLZ_V_M1_MASK, + PseudoVCLZ_V_M2, + PseudoVCLZ_V_M2_MASK, + PseudoVCLZ_V_M4, + PseudoVCLZ_V_M4_MASK, + PseudoVCLZ_V_M8, + PseudoVCLZ_V_M8_MASK, + PseudoVCLZ_V_MF2, + PseudoVCLZ_V_MF2_MASK, + PseudoVCLZ_V_MF4, + PseudoVCLZ_V_MF4_MASK, + PseudoVCLZ_V_MF8, + PseudoVCLZ_V_MF8_MASK, + PseudoVCOMPRESS_VM_M1_E16, + PseudoVCOMPRESS_VM_M1_E32, + PseudoVCOMPRESS_VM_M1_E64, + PseudoVCOMPRESS_VM_M1_E8, + PseudoVCOMPRESS_VM_M2_E16, + PseudoVCOMPRESS_VM_M2_E32, + PseudoVCOMPRESS_VM_M2_E64, + PseudoVCOMPRESS_VM_M2_E8, + PseudoVCOMPRESS_VM_M4_E16, + PseudoVCOMPRESS_VM_M4_E32, + PseudoVCOMPRESS_VM_M4_E64, + PseudoVCOMPRESS_VM_M4_E8, + PseudoVCOMPRESS_VM_M8_E16, + PseudoVCOMPRESS_VM_M8_E32, + PseudoVCOMPRESS_VM_M8_E64, + PseudoVCOMPRESS_VM_M8_E8, + PseudoVCOMPRESS_VM_MF2_E16, + PseudoVCOMPRESS_VM_MF2_E32, + PseudoVCOMPRESS_VM_MF2_E8, + PseudoVCOMPRESS_VM_MF4_E16, + PseudoVCOMPRESS_VM_MF4_E8, + PseudoVCOMPRESS_VM_MF8_E8, + PseudoVCPOP_M_B1, + PseudoVCPOP_M_B16, + PseudoVCPOP_M_B16_MASK, + PseudoVCPOP_M_B1_MASK, + PseudoVCPOP_M_B2, + PseudoVCPOP_M_B2_MASK, + PseudoVCPOP_M_B32, + PseudoVCPOP_M_B32_MASK, + PseudoVCPOP_M_B4, + PseudoVCPOP_M_B4_MASK, + PseudoVCPOP_M_B64, + PseudoVCPOP_M_B64_MASK, + PseudoVCPOP_M_B8, + PseudoVCPOP_M_B8_MASK, + PseudoVCPOP_V_M1, + PseudoVCPOP_V_M1_MASK, + PseudoVCPOP_V_M2, + PseudoVCPOP_V_M2_MASK, + PseudoVCPOP_V_M4, + PseudoVCPOP_V_M4_MASK, + PseudoVCPOP_V_M8, + PseudoVCPOP_V_M8_MASK, + PseudoVCPOP_V_MF2, + PseudoVCPOP_V_MF2_MASK, + PseudoVCPOP_V_MF4, + PseudoVCPOP_V_MF4_MASK, + PseudoVCPOP_V_MF8, + PseudoVCPOP_V_MF8_MASK, + PseudoVCTZ_V_M1, + PseudoVCTZ_V_M1_MASK, + PseudoVCTZ_V_M2, + PseudoVCTZ_V_M2_MASK, + PseudoVCTZ_V_M4, + PseudoVCTZ_V_M4_MASK, + PseudoVCTZ_V_M8, + PseudoVCTZ_V_M8_MASK, + PseudoVCTZ_V_MF2, + PseudoVCTZ_V_MF2_MASK, + PseudoVCTZ_V_MF4, + PseudoVCTZ_V_MF4_MASK, + PseudoVCTZ_V_MF8, + PseudoVCTZ_V_MF8_MASK, + PseudoVDIVU_VV_M1_E16, + PseudoVDIVU_VV_M1_E16_MASK, + PseudoVDIVU_VV_M1_E32, + PseudoVDIVU_VV_M1_E32_MASK, + PseudoVDIVU_VV_M1_E64, + PseudoVDIVU_VV_M1_E64_MASK, + PseudoVDIVU_VV_M1_E8, + PseudoVDIVU_VV_M1_E8_MASK, + PseudoVDIVU_VV_M2_E16, + PseudoVDIVU_VV_M2_E16_MASK, + PseudoVDIVU_VV_M2_E32, + PseudoVDIVU_VV_M2_E32_MASK, + PseudoVDIVU_VV_M2_E64, + PseudoVDIVU_VV_M2_E64_MASK, + PseudoVDIVU_VV_M2_E8, + PseudoVDIVU_VV_M2_E8_MASK, + PseudoVDIVU_VV_M4_E16, + PseudoVDIVU_VV_M4_E16_MASK, + PseudoVDIVU_VV_M4_E32, + PseudoVDIVU_VV_M4_E32_MASK, + PseudoVDIVU_VV_M4_E64, + PseudoVDIVU_VV_M4_E64_MASK, + PseudoVDIVU_VV_M4_E8, + PseudoVDIVU_VV_M4_E8_MASK, + PseudoVDIVU_VV_M8_E16, + PseudoVDIVU_VV_M8_E16_MASK, + PseudoVDIVU_VV_M8_E32, + PseudoVDIVU_VV_M8_E32_MASK, + PseudoVDIVU_VV_M8_E64, + PseudoVDIVU_VV_M8_E64_MASK, + PseudoVDIVU_VV_M8_E8, + PseudoVDIVU_VV_M8_E8_MASK, + PseudoVDIVU_VV_MF2_E16, + PseudoVDIVU_VV_MF2_E16_MASK, + PseudoVDIVU_VV_MF2_E32, + PseudoVDIVU_VV_MF2_E32_MASK, + PseudoVDIVU_VV_MF2_E8, + PseudoVDIVU_VV_MF2_E8_MASK, + PseudoVDIVU_VV_MF4_E16, + PseudoVDIVU_VV_MF4_E16_MASK, + PseudoVDIVU_VV_MF4_E8, + PseudoVDIVU_VV_MF4_E8_MASK, + PseudoVDIVU_VV_MF8_E8, + PseudoVDIVU_VV_MF8_E8_MASK, + PseudoVDIVU_VX_M1_E16, + PseudoVDIVU_VX_M1_E16_MASK, + PseudoVDIVU_VX_M1_E32, + PseudoVDIVU_VX_M1_E32_MASK, + PseudoVDIVU_VX_M1_E64, + PseudoVDIVU_VX_M1_E64_MASK, + PseudoVDIVU_VX_M1_E8, + PseudoVDIVU_VX_M1_E8_MASK, + PseudoVDIVU_VX_M2_E16, + PseudoVDIVU_VX_M2_E16_MASK, + PseudoVDIVU_VX_M2_E32, + PseudoVDIVU_VX_M2_E32_MASK, + PseudoVDIVU_VX_M2_E64, + PseudoVDIVU_VX_M2_E64_MASK, + PseudoVDIVU_VX_M2_E8, + PseudoVDIVU_VX_M2_E8_MASK, + PseudoVDIVU_VX_M4_E16, + PseudoVDIVU_VX_M4_E16_MASK, + PseudoVDIVU_VX_M4_E32, + PseudoVDIVU_VX_M4_E32_MASK, + PseudoVDIVU_VX_M4_E64, + PseudoVDIVU_VX_M4_E64_MASK, + PseudoVDIVU_VX_M4_E8, + PseudoVDIVU_VX_M4_E8_MASK, + PseudoVDIVU_VX_M8_E16, + PseudoVDIVU_VX_M8_E16_MASK, + PseudoVDIVU_VX_M8_E32, + PseudoVDIVU_VX_M8_E32_MASK, + PseudoVDIVU_VX_M8_E64, + PseudoVDIVU_VX_M8_E64_MASK, + PseudoVDIVU_VX_M8_E8, + PseudoVDIVU_VX_M8_E8_MASK, + PseudoVDIVU_VX_MF2_E16, + PseudoVDIVU_VX_MF2_E16_MASK, + PseudoVDIVU_VX_MF2_E32, + PseudoVDIVU_VX_MF2_E32_MASK, + PseudoVDIVU_VX_MF2_E8, + PseudoVDIVU_VX_MF2_E8_MASK, + PseudoVDIVU_VX_MF4_E16, + PseudoVDIVU_VX_MF4_E16_MASK, + PseudoVDIVU_VX_MF4_E8, + PseudoVDIVU_VX_MF4_E8_MASK, + PseudoVDIVU_VX_MF8_E8, + PseudoVDIVU_VX_MF8_E8_MASK, + PseudoVDIV_VV_M1_E16, + PseudoVDIV_VV_M1_E16_MASK, + PseudoVDIV_VV_M1_E32, + PseudoVDIV_VV_M1_E32_MASK, + PseudoVDIV_VV_M1_E64, + PseudoVDIV_VV_M1_E64_MASK, + PseudoVDIV_VV_M1_E8, + PseudoVDIV_VV_M1_E8_MASK, + PseudoVDIV_VV_M2_E16, + PseudoVDIV_VV_M2_E16_MASK, + PseudoVDIV_VV_M2_E32, + PseudoVDIV_VV_M2_E32_MASK, + PseudoVDIV_VV_M2_E64, + PseudoVDIV_VV_M2_E64_MASK, + PseudoVDIV_VV_M2_E8, + PseudoVDIV_VV_M2_E8_MASK, + PseudoVDIV_VV_M4_E16, + PseudoVDIV_VV_M4_E16_MASK, + PseudoVDIV_VV_M4_E32, + PseudoVDIV_VV_M4_E32_MASK, + PseudoVDIV_VV_M4_E64, + PseudoVDIV_VV_M4_E64_MASK, + PseudoVDIV_VV_M4_E8, + PseudoVDIV_VV_M4_E8_MASK, + PseudoVDIV_VV_M8_E16, + PseudoVDIV_VV_M8_E16_MASK, + PseudoVDIV_VV_M8_E32, + PseudoVDIV_VV_M8_E32_MASK, + PseudoVDIV_VV_M8_E64, + PseudoVDIV_VV_M8_E64_MASK, + PseudoVDIV_VV_M8_E8, + PseudoVDIV_VV_M8_E8_MASK, + PseudoVDIV_VV_MF2_E16, + PseudoVDIV_VV_MF2_E16_MASK, + PseudoVDIV_VV_MF2_E32, + PseudoVDIV_VV_MF2_E32_MASK, + PseudoVDIV_VV_MF2_E8, + PseudoVDIV_VV_MF2_E8_MASK, + PseudoVDIV_VV_MF4_E16, + PseudoVDIV_VV_MF4_E16_MASK, + PseudoVDIV_VV_MF4_E8, + PseudoVDIV_VV_MF4_E8_MASK, + PseudoVDIV_VV_MF8_E8, + PseudoVDIV_VV_MF8_E8_MASK, + PseudoVDIV_VX_M1_E16, + PseudoVDIV_VX_M1_E16_MASK, + PseudoVDIV_VX_M1_E32, + PseudoVDIV_VX_M1_E32_MASK, + PseudoVDIV_VX_M1_E64, + PseudoVDIV_VX_M1_E64_MASK, + PseudoVDIV_VX_M1_E8, + PseudoVDIV_VX_M1_E8_MASK, + PseudoVDIV_VX_M2_E16, + PseudoVDIV_VX_M2_E16_MASK, + PseudoVDIV_VX_M2_E32, + PseudoVDIV_VX_M2_E32_MASK, + PseudoVDIV_VX_M2_E64, + PseudoVDIV_VX_M2_E64_MASK, + PseudoVDIV_VX_M2_E8, + PseudoVDIV_VX_M2_E8_MASK, + PseudoVDIV_VX_M4_E16, + PseudoVDIV_VX_M4_E16_MASK, + PseudoVDIV_VX_M4_E32, + PseudoVDIV_VX_M4_E32_MASK, + PseudoVDIV_VX_M4_E64, + PseudoVDIV_VX_M4_E64_MASK, + PseudoVDIV_VX_M4_E8, + PseudoVDIV_VX_M4_E8_MASK, + PseudoVDIV_VX_M8_E16, + PseudoVDIV_VX_M8_E16_MASK, + PseudoVDIV_VX_M8_E32, + PseudoVDIV_VX_M8_E32_MASK, + PseudoVDIV_VX_M8_E64, + PseudoVDIV_VX_M8_E64_MASK, + PseudoVDIV_VX_M8_E8, + PseudoVDIV_VX_M8_E8_MASK, + PseudoVDIV_VX_MF2_E16, + PseudoVDIV_VX_MF2_E16_MASK, + PseudoVDIV_VX_MF2_E32, + PseudoVDIV_VX_MF2_E32_MASK, + PseudoVDIV_VX_MF2_E8, + PseudoVDIV_VX_MF2_E8_MASK, + PseudoVDIV_VX_MF4_E16, + PseudoVDIV_VX_MF4_E16_MASK, + PseudoVDIV_VX_MF4_E8, + PseudoVDIV_VX_MF4_E8_MASK, + PseudoVDIV_VX_MF8_E8, + PseudoVDIV_VX_MF8_E8_MASK, + PseudoVFADD_ALT_VFPR16_M1_E16, + PseudoVFADD_ALT_VFPR16_M1_E16_MASK, + PseudoVFADD_ALT_VFPR16_M2_E16, + PseudoVFADD_ALT_VFPR16_M2_E16_MASK, + PseudoVFADD_ALT_VFPR16_M4_E16, + PseudoVFADD_ALT_VFPR16_M4_E16_MASK, + PseudoVFADD_ALT_VFPR16_M8_E16, + PseudoVFADD_ALT_VFPR16_M8_E16_MASK, + PseudoVFADD_ALT_VFPR16_MF2_E16, + PseudoVFADD_ALT_VFPR16_MF2_E16_MASK, + PseudoVFADD_ALT_VFPR16_MF4_E16, + PseudoVFADD_ALT_VFPR16_MF4_E16_MASK, + PseudoVFADD_ALT_VV_M1_E16, + PseudoVFADD_ALT_VV_M1_E16_MASK, + PseudoVFADD_ALT_VV_M2_E16, + PseudoVFADD_ALT_VV_M2_E16_MASK, + PseudoVFADD_ALT_VV_M4_E16, + PseudoVFADD_ALT_VV_M4_E16_MASK, + PseudoVFADD_ALT_VV_M8_E16, + PseudoVFADD_ALT_VV_M8_E16_MASK, + PseudoVFADD_ALT_VV_MF2_E16, + PseudoVFADD_ALT_VV_MF2_E16_MASK, + PseudoVFADD_ALT_VV_MF4_E16, + PseudoVFADD_ALT_VV_MF4_E16_MASK, + PseudoVFADD_VFPR16_M1_E16, + PseudoVFADD_VFPR16_M1_E16_MASK, + PseudoVFADD_VFPR16_M2_E16, + PseudoVFADD_VFPR16_M2_E16_MASK, + PseudoVFADD_VFPR16_M4_E16, + PseudoVFADD_VFPR16_M4_E16_MASK, + PseudoVFADD_VFPR16_M8_E16, + PseudoVFADD_VFPR16_M8_E16_MASK, + PseudoVFADD_VFPR16_MF2_E16, + PseudoVFADD_VFPR16_MF2_E16_MASK, + PseudoVFADD_VFPR16_MF4_E16, + PseudoVFADD_VFPR16_MF4_E16_MASK, + PseudoVFADD_VFPR32_M1_E32, + PseudoVFADD_VFPR32_M1_E32_MASK, + PseudoVFADD_VFPR32_M2_E32, + PseudoVFADD_VFPR32_M2_E32_MASK, + PseudoVFADD_VFPR32_M4_E32, + PseudoVFADD_VFPR32_M4_E32_MASK, + PseudoVFADD_VFPR32_M8_E32, + PseudoVFADD_VFPR32_M8_E32_MASK, + PseudoVFADD_VFPR32_MF2_E32, + PseudoVFADD_VFPR32_MF2_E32_MASK, + PseudoVFADD_VFPR64_M1_E64, + PseudoVFADD_VFPR64_M1_E64_MASK, + PseudoVFADD_VFPR64_M2_E64, + PseudoVFADD_VFPR64_M2_E64_MASK, + PseudoVFADD_VFPR64_M4_E64, + PseudoVFADD_VFPR64_M4_E64_MASK, + PseudoVFADD_VFPR64_M8_E64, + PseudoVFADD_VFPR64_M8_E64_MASK, + PseudoVFADD_VV_M1_E16, + PseudoVFADD_VV_M1_E16_MASK, + PseudoVFADD_VV_M1_E32, + PseudoVFADD_VV_M1_E32_MASK, + PseudoVFADD_VV_M1_E64, + PseudoVFADD_VV_M1_E64_MASK, + PseudoVFADD_VV_M2_E16, + PseudoVFADD_VV_M2_E16_MASK, + PseudoVFADD_VV_M2_E32, + PseudoVFADD_VV_M2_E32_MASK, + PseudoVFADD_VV_M2_E64, + PseudoVFADD_VV_M2_E64_MASK, + PseudoVFADD_VV_M4_E16, + PseudoVFADD_VV_M4_E16_MASK, + PseudoVFADD_VV_M4_E32, + PseudoVFADD_VV_M4_E32_MASK, + PseudoVFADD_VV_M4_E64, + PseudoVFADD_VV_M4_E64_MASK, + PseudoVFADD_VV_M8_E16, + PseudoVFADD_VV_M8_E16_MASK, + PseudoVFADD_VV_M8_E32, + PseudoVFADD_VV_M8_E32_MASK, + PseudoVFADD_VV_M8_E64, + PseudoVFADD_VV_M8_E64_MASK, + PseudoVFADD_VV_MF2_E16, + PseudoVFADD_VV_MF2_E16_MASK, + PseudoVFADD_VV_MF2_E32, + PseudoVFADD_VV_MF2_E32_MASK, + PseudoVFADD_VV_MF4_E16, + PseudoVFADD_VV_MF4_E16_MASK, + PseudoVFCLASS_ALT_V_M1, + PseudoVFCLASS_ALT_V_M1_MASK, + PseudoVFCLASS_ALT_V_M2, + PseudoVFCLASS_ALT_V_M2_MASK, + PseudoVFCLASS_ALT_V_M4, + PseudoVFCLASS_ALT_V_M4_MASK, + PseudoVFCLASS_ALT_V_M8, + PseudoVFCLASS_ALT_V_M8_MASK, + PseudoVFCLASS_ALT_V_MF2, + PseudoVFCLASS_ALT_V_MF2_MASK, + PseudoVFCLASS_ALT_V_MF4, + PseudoVFCLASS_ALT_V_MF4_MASK, + PseudoVFCLASS_V_M1, + PseudoVFCLASS_V_M1_MASK, + PseudoVFCLASS_V_M2, + PseudoVFCLASS_V_M2_MASK, + PseudoVFCLASS_V_M4, + PseudoVFCLASS_V_M4_MASK, + PseudoVFCLASS_V_M8, + PseudoVFCLASS_V_M8_MASK, + PseudoVFCLASS_V_MF2, + PseudoVFCLASS_V_MF2_MASK, + PseudoVFCLASS_V_MF4, + PseudoVFCLASS_V_MF4_MASK, + PseudoVFCVT_F_XU_V_M1_E16, + PseudoVFCVT_F_XU_V_M1_E16_MASK, + PseudoVFCVT_F_XU_V_M1_E32, + PseudoVFCVT_F_XU_V_M1_E32_MASK, + PseudoVFCVT_F_XU_V_M1_E64, + PseudoVFCVT_F_XU_V_M1_E64_MASK, + PseudoVFCVT_F_XU_V_M2_E16, + PseudoVFCVT_F_XU_V_M2_E16_MASK, + PseudoVFCVT_F_XU_V_M2_E32, + PseudoVFCVT_F_XU_V_M2_E32_MASK, + PseudoVFCVT_F_XU_V_M2_E64, + PseudoVFCVT_F_XU_V_M2_E64_MASK, + PseudoVFCVT_F_XU_V_M4_E16, + PseudoVFCVT_F_XU_V_M4_E16_MASK, + PseudoVFCVT_F_XU_V_M4_E32, + PseudoVFCVT_F_XU_V_M4_E32_MASK, + PseudoVFCVT_F_XU_V_M4_E64, + PseudoVFCVT_F_XU_V_M4_E64_MASK, + PseudoVFCVT_F_XU_V_M8_E16, + PseudoVFCVT_F_XU_V_M8_E16_MASK, + PseudoVFCVT_F_XU_V_M8_E32, + PseudoVFCVT_F_XU_V_M8_E32_MASK, + PseudoVFCVT_F_XU_V_M8_E64, + PseudoVFCVT_F_XU_V_M8_E64_MASK, + PseudoVFCVT_F_XU_V_MF2_E16, + PseudoVFCVT_F_XU_V_MF2_E16_MASK, + PseudoVFCVT_F_XU_V_MF2_E32, + PseudoVFCVT_F_XU_V_MF2_E32_MASK, + PseudoVFCVT_F_XU_V_MF4_E16, + PseudoVFCVT_F_XU_V_MF4_E16_MASK, + PseudoVFCVT_F_X_V_M1_E16, + PseudoVFCVT_F_X_V_M1_E16_MASK, + PseudoVFCVT_F_X_V_M1_E32, + PseudoVFCVT_F_X_V_M1_E32_MASK, + PseudoVFCVT_F_X_V_M1_E64, + PseudoVFCVT_F_X_V_M1_E64_MASK, + PseudoVFCVT_F_X_V_M2_E16, + PseudoVFCVT_F_X_V_M2_E16_MASK, + PseudoVFCVT_F_X_V_M2_E32, + PseudoVFCVT_F_X_V_M2_E32_MASK, + PseudoVFCVT_F_X_V_M2_E64, + PseudoVFCVT_F_X_V_M2_E64_MASK, + PseudoVFCVT_F_X_V_M4_E16, + PseudoVFCVT_F_X_V_M4_E16_MASK, + PseudoVFCVT_F_X_V_M4_E32, + PseudoVFCVT_F_X_V_M4_E32_MASK, + PseudoVFCVT_F_X_V_M4_E64, + PseudoVFCVT_F_X_V_M4_E64_MASK, + PseudoVFCVT_F_X_V_M8_E16, + PseudoVFCVT_F_X_V_M8_E16_MASK, + PseudoVFCVT_F_X_V_M8_E32, + PseudoVFCVT_F_X_V_M8_E32_MASK, + PseudoVFCVT_F_X_V_M8_E64, + PseudoVFCVT_F_X_V_M8_E64_MASK, + PseudoVFCVT_F_X_V_MF2_E16, + PseudoVFCVT_F_X_V_MF2_E16_MASK, + PseudoVFCVT_F_X_V_MF2_E32, + PseudoVFCVT_F_X_V_MF2_E32_MASK, + PseudoVFCVT_F_X_V_MF4_E16, + PseudoVFCVT_F_X_V_MF4_E16_MASK, + PseudoVFCVT_RTZ_XU_F_V_M1, + PseudoVFCVT_RTZ_XU_F_V_M1_MASK, + PseudoVFCVT_RTZ_XU_F_V_M2, + PseudoVFCVT_RTZ_XU_F_V_M2_MASK, + PseudoVFCVT_RTZ_XU_F_V_M4, + PseudoVFCVT_RTZ_XU_F_V_M4_MASK, + PseudoVFCVT_RTZ_XU_F_V_M8, + PseudoVFCVT_RTZ_XU_F_V_M8_MASK, + PseudoVFCVT_RTZ_XU_F_V_MF2, + PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, + PseudoVFCVT_RTZ_XU_F_V_MF4, + PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, + PseudoVFCVT_RTZ_X_F_V_M1, + PseudoVFCVT_RTZ_X_F_V_M1_MASK, + PseudoVFCVT_RTZ_X_F_V_M2, + PseudoVFCVT_RTZ_X_F_V_M2_MASK, + PseudoVFCVT_RTZ_X_F_V_M4, + PseudoVFCVT_RTZ_X_F_V_M4_MASK, + PseudoVFCVT_RTZ_X_F_V_M8, + PseudoVFCVT_RTZ_X_F_V_M8_MASK, + PseudoVFCVT_RTZ_X_F_V_MF2, + PseudoVFCVT_RTZ_X_F_V_MF2_MASK, + PseudoVFCVT_RTZ_X_F_V_MF4, + PseudoVFCVT_RTZ_X_F_V_MF4_MASK, + PseudoVFCVT_XU_F_V_M1, + PseudoVFCVT_XU_F_V_M1_MASK, + PseudoVFCVT_XU_F_V_M2, + PseudoVFCVT_XU_F_V_M2_MASK, + PseudoVFCVT_XU_F_V_M4, + PseudoVFCVT_XU_F_V_M4_MASK, + PseudoVFCVT_XU_F_V_M8, + PseudoVFCVT_XU_F_V_M8_MASK, + PseudoVFCVT_XU_F_V_MF2, + PseudoVFCVT_XU_F_V_MF2_MASK, + PseudoVFCVT_XU_F_V_MF4, + PseudoVFCVT_XU_F_V_MF4_MASK, + PseudoVFCVT_X_F_V_M1, + PseudoVFCVT_X_F_V_M1_MASK, + PseudoVFCVT_X_F_V_M2, + PseudoVFCVT_X_F_V_M2_MASK, + PseudoVFCVT_X_F_V_M4, + PseudoVFCVT_X_F_V_M4_MASK, + PseudoVFCVT_X_F_V_M8, + PseudoVFCVT_X_F_V_M8_MASK, + PseudoVFCVT_X_F_V_MF2, + PseudoVFCVT_X_F_V_MF2_MASK, + PseudoVFCVT_X_F_V_MF4, + PseudoVFCVT_X_F_V_MF4_MASK, + PseudoVFDIV_VFPR16_M1_E16, + PseudoVFDIV_VFPR16_M1_E16_MASK, + PseudoVFDIV_VFPR16_M2_E16, + PseudoVFDIV_VFPR16_M2_E16_MASK, + PseudoVFDIV_VFPR16_M4_E16, + PseudoVFDIV_VFPR16_M4_E16_MASK, + PseudoVFDIV_VFPR16_M8_E16, + PseudoVFDIV_VFPR16_M8_E16_MASK, + PseudoVFDIV_VFPR16_MF2_E16, + PseudoVFDIV_VFPR16_MF2_E16_MASK, + PseudoVFDIV_VFPR16_MF4_E16, + PseudoVFDIV_VFPR16_MF4_E16_MASK, + PseudoVFDIV_VFPR32_M1_E32, + PseudoVFDIV_VFPR32_M1_E32_MASK, + PseudoVFDIV_VFPR32_M2_E32, + PseudoVFDIV_VFPR32_M2_E32_MASK, + PseudoVFDIV_VFPR32_M4_E32, + PseudoVFDIV_VFPR32_M4_E32_MASK, + PseudoVFDIV_VFPR32_M8_E32, + PseudoVFDIV_VFPR32_M8_E32_MASK, + PseudoVFDIV_VFPR32_MF2_E32, + PseudoVFDIV_VFPR32_MF2_E32_MASK, + PseudoVFDIV_VFPR64_M1_E64, + PseudoVFDIV_VFPR64_M1_E64_MASK, + PseudoVFDIV_VFPR64_M2_E64, + PseudoVFDIV_VFPR64_M2_E64_MASK, + PseudoVFDIV_VFPR64_M4_E64, + PseudoVFDIV_VFPR64_M4_E64_MASK, + PseudoVFDIV_VFPR64_M8_E64, + PseudoVFDIV_VFPR64_M8_E64_MASK, + PseudoVFDIV_VV_M1_E16, + PseudoVFDIV_VV_M1_E16_MASK, + PseudoVFDIV_VV_M1_E32, + PseudoVFDIV_VV_M1_E32_MASK, + PseudoVFDIV_VV_M1_E64, + PseudoVFDIV_VV_M1_E64_MASK, + PseudoVFDIV_VV_M2_E16, + PseudoVFDIV_VV_M2_E16_MASK, + PseudoVFDIV_VV_M2_E32, + PseudoVFDIV_VV_M2_E32_MASK, + PseudoVFDIV_VV_M2_E64, + PseudoVFDIV_VV_M2_E64_MASK, + PseudoVFDIV_VV_M4_E16, + PseudoVFDIV_VV_M4_E16_MASK, + PseudoVFDIV_VV_M4_E32, + PseudoVFDIV_VV_M4_E32_MASK, + PseudoVFDIV_VV_M4_E64, + PseudoVFDIV_VV_M4_E64_MASK, + PseudoVFDIV_VV_M8_E16, + PseudoVFDIV_VV_M8_E16_MASK, + PseudoVFDIV_VV_M8_E32, + PseudoVFDIV_VV_M8_E32_MASK, + PseudoVFDIV_VV_M8_E64, + PseudoVFDIV_VV_M8_E64_MASK, + PseudoVFDIV_VV_MF2_E16, + PseudoVFDIV_VV_MF2_E16_MASK, + PseudoVFDIV_VV_MF2_E32, + PseudoVFDIV_VV_MF2_E32_MASK, + PseudoVFDIV_VV_MF4_E16, + PseudoVFDIV_VV_MF4_E16_MASK, + PseudoVFIRST_M_B1, + PseudoVFIRST_M_B16, + PseudoVFIRST_M_B16_MASK, + PseudoVFIRST_M_B1_MASK, + PseudoVFIRST_M_B2, + PseudoVFIRST_M_B2_MASK, + PseudoVFIRST_M_B32, + PseudoVFIRST_M_B32_MASK, + PseudoVFIRST_M_B4, + PseudoVFIRST_M_B4_MASK, + PseudoVFIRST_M_B64, + PseudoVFIRST_M_B64_MASK, + PseudoVFIRST_M_B8, + PseudoVFIRST_M_B8_MASK, + PseudoVFMACC_ALT_VFPR16_M1_E16, + PseudoVFMACC_ALT_VFPR16_M1_E16_MASK, + PseudoVFMACC_ALT_VFPR16_M2_E16, + PseudoVFMACC_ALT_VFPR16_M2_E16_MASK, + PseudoVFMACC_ALT_VFPR16_M4_E16, + PseudoVFMACC_ALT_VFPR16_M4_E16_MASK, + PseudoVFMACC_ALT_VFPR16_M8_E16, + PseudoVFMACC_ALT_VFPR16_M8_E16_MASK, + PseudoVFMACC_ALT_VFPR16_MF2_E16, + PseudoVFMACC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMACC_ALT_VFPR16_MF4_E16, + PseudoVFMACC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMACC_ALT_VV_M1_E16, + PseudoVFMACC_ALT_VV_M1_E16_MASK, + PseudoVFMACC_ALT_VV_M2_E16, + PseudoVFMACC_ALT_VV_M2_E16_MASK, + PseudoVFMACC_ALT_VV_M4_E16, + PseudoVFMACC_ALT_VV_M4_E16_MASK, + PseudoVFMACC_ALT_VV_M8_E16, + PseudoVFMACC_ALT_VV_M8_E16_MASK, + PseudoVFMACC_ALT_VV_MF2_E16, + PseudoVFMACC_ALT_VV_MF2_E16_MASK, + PseudoVFMACC_ALT_VV_MF4_E16, + PseudoVFMACC_ALT_VV_MF4_E16_MASK, + PseudoVFMACC_VFPR16_M1_E16, + PseudoVFMACC_VFPR16_M1_E16_MASK, + PseudoVFMACC_VFPR16_M2_E16, + PseudoVFMACC_VFPR16_M2_E16_MASK, + PseudoVFMACC_VFPR16_M4_E16, + PseudoVFMACC_VFPR16_M4_E16_MASK, + PseudoVFMACC_VFPR16_M8_E16, + PseudoVFMACC_VFPR16_M8_E16_MASK, + PseudoVFMACC_VFPR16_MF2_E16, + PseudoVFMACC_VFPR16_MF2_E16_MASK, + PseudoVFMACC_VFPR16_MF4_E16, + PseudoVFMACC_VFPR16_MF4_E16_MASK, + PseudoVFMACC_VFPR32_M1_E32, + PseudoVFMACC_VFPR32_M1_E32_MASK, + PseudoVFMACC_VFPR32_M2_E32, + PseudoVFMACC_VFPR32_M2_E32_MASK, + PseudoVFMACC_VFPR32_M4_E32, + PseudoVFMACC_VFPR32_M4_E32_MASK, + PseudoVFMACC_VFPR32_M8_E32, + PseudoVFMACC_VFPR32_M8_E32_MASK, + PseudoVFMACC_VFPR32_MF2_E32, + PseudoVFMACC_VFPR32_MF2_E32_MASK, + PseudoVFMACC_VFPR64_M1_E64, + PseudoVFMACC_VFPR64_M1_E64_MASK, + PseudoVFMACC_VFPR64_M2_E64, + PseudoVFMACC_VFPR64_M2_E64_MASK, + PseudoVFMACC_VFPR64_M4_E64, + PseudoVFMACC_VFPR64_M4_E64_MASK, + PseudoVFMACC_VFPR64_M8_E64, + PseudoVFMACC_VFPR64_M8_E64_MASK, + PseudoVFMACC_VV_M1_E16, + PseudoVFMACC_VV_M1_E16_MASK, + PseudoVFMACC_VV_M1_E32, + PseudoVFMACC_VV_M1_E32_MASK, + PseudoVFMACC_VV_M1_E64, + PseudoVFMACC_VV_M1_E64_MASK, + PseudoVFMACC_VV_M2_E16, + PseudoVFMACC_VV_M2_E16_MASK, + PseudoVFMACC_VV_M2_E32, + PseudoVFMACC_VV_M2_E32_MASK, + PseudoVFMACC_VV_M2_E64, + PseudoVFMACC_VV_M2_E64_MASK, + PseudoVFMACC_VV_M4_E16, + PseudoVFMACC_VV_M4_E16_MASK, + PseudoVFMACC_VV_M4_E32, + PseudoVFMACC_VV_M4_E32_MASK, + PseudoVFMACC_VV_M4_E64, + PseudoVFMACC_VV_M4_E64_MASK, + PseudoVFMACC_VV_M8_E16, + PseudoVFMACC_VV_M8_E16_MASK, + PseudoVFMACC_VV_M8_E32, + PseudoVFMACC_VV_M8_E32_MASK, + PseudoVFMACC_VV_M8_E64, + PseudoVFMACC_VV_M8_E64_MASK, + PseudoVFMACC_VV_MF2_E16, + PseudoVFMACC_VV_MF2_E16_MASK, + PseudoVFMACC_VV_MF2_E32, + PseudoVFMACC_VV_MF2_E32_MASK, + PseudoVFMACC_VV_MF4_E16, + PseudoVFMACC_VV_MF4_E16_MASK, + PseudoVFMADD_ALT_VFPR16_M1_E16, + PseudoVFMADD_ALT_VFPR16_M1_E16_MASK, + PseudoVFMADD_ALT_VFPR16_M2_E16, + PseudoVFMADD_ALT_VFPR16_M2_E16_MASK, + PseudoVFMADD_ALT_VFPR16_M4_E16, + PseudoVFMADD_ALT_VFPR16_M4_E16_MASK, + PseudoVFMADD_ALT_VFPR16_M8_E16, + PseudoVFMADD_ALT_VFPR16_M8_E16_MASK, + PseudoVFMADD_ALT_VFPR16_MF2_E16, + PseudoVFMADD_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMADD_ALT_VFPR16_MF4_E16, + PseudoVFMADD_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMADD_ALT_VV_M1_E16, + PseudoVFMADD_ALT_VV_M1_E16_MASK, + PseudoVFMADD_ALT_VV_M2_E16, + PseudoVFMADD_ALT_VV_M2_E16_MASK, + PseudoVFMADD_ALT_VV_M4_E16, + PseudoVFMADD_ALT_VV_M4_E16_MASK, + PseudoVFMADD_ALT_VV_M8_E16, + PseudoVFMADD_ALT_VV_M8_E16_MASK, + PseudoVFMADD_ALT_VV_MF2_E16, + PseudoVFMADD_ALT_VV_MF2_E16_MASK, + PseudoVFMADD_ALT_VV_MF4_E16, + PseudoVFMADD_ALT_VV_MF4_E16_MASK, + PseudoVFMADD_VFPR16_M1_E16, + PseudoVFMADD_VFPR16_M1_E16_MASK, + PseudoVFMADD_VFPR16_M2_E16, + PseudoVFMADD_VFPR16_M2_E16_MASK, + PseudoVFMADD_VFPR16_M4_E16, + PseudoVFMADD_VFPR16_M4_E16_MASK, + PseudoVFMADD_VFPR16_M8_E16, + PseudoVFMADD_VFPR16_M8_E16_MASK, + PseudoVFMADD_VFPR16_MF2_E16, + PseudoVFMADD_VFPR16_MF2_E16_MASK, + PseudoVFMADD_VFPR16_MF4_E16, + PseudoVFMADD_VFPR16_MF4_E16_MASK, + PseudoVFMADD_VFPR32_M1_E32, + PseudoVFMADD_VFPR32_M1_E32_MASK, + PseudoVFMADD_VFPR32_M2_E32, + PseudoVFMADD_VFPR32_M2_E32_MASK, + PseudoVFMADD_VFPR32_M4_E32, + PseudoVFMADD_VFPR32_M4_E32_MASK, + PseudoVFMADD_VFPR32_M8_E32, + PseudoVFMADD_VFPR32_M8_E32_MASK, + PseudoVFMADD_VFPR32_MF2_E32, + PseudoVFMADD_VFPR32_MF2_E32_MASK, + PseudoVFMADD_VFPR64_M1_E64, + PseudoVFMADD_VFPR64_M1_E64_MASK, + PseudoVFMADD_VFPR64_M2_E64, + PseudoVFMADD_VFPR64_M2_E64_MASK, + PseudoVFMADD_VFPR64_M4_E64, + PseudoVFMADD_VFPR64_M4_E64_MASK, + PseudoVFMADD_VFPR64_M8_E64, + PseudoVFMADD_VFPR64_M8_E64_MASK, + PseudoVFMADD_VV_M1_E16, + PseudoVFMADD_VV_M1_E16_MASK, + PseudoVFMADD_VV_M1_E32, + PseudoVFMADD_VV_M1_E32_MASK, + PseudoVFMADD_VV_M1_E64, + PseudoVFMADD_VV_M1_E64_MASK, + PseudoVFMADD_VV_M2_E16, + PseudoVFMADD_VV_M2_E16_MASK, + PseudoVFMADD_VV_M2_E32, + PseudoVFMADD_VV_M2_E32_MASK, + PseudoVFMADD_VV_M2_E64, + PseudoVFMADD_VV_M2_E64_MASK, + PseudoVFMADD_VV_M4_E16, + PseudoVFMADD_VV_M4_E16_MASK, + PseudoVFMADD_VV_M4_E32, + PseudoVFMADD_VV_M4_E32_MASK, + PseudoVFMADD_VV_M4_E64, + PseudoVFMADD_VV_M4_E64_MASK, + PseudoVFMADD_VV_M8_E16, + PseudoVFMADD_VV_M8_E16_MASK, + PseudoVFMADD_VV_M8_E32, + PseudoVFMADD_VV_M8_E32_MASK, + PseudoVFMADD_VV_M8_E64, + PseudoVFMADD_VV_M8_E64_MASK, + PseudoVFMADD_VV_MF2_E16, + PseudoVFMADD_VV_MF2_E16_MASK, + PseudoVFMADD_VV_MF2_E32, + PseudoVFMADD_VV_MF2_E32_MASK, + PseudoVFMADD_VV_MF4_E16, + PseudoVFMADD_VV_MF4_E16_MASK, + PseudoVFMAX_ALT_VFPR16_M1_E16, + PseudoVFMAX_ALT_VFPR16_M1_E16_MASK, + PseudoVFMAX_ALT_VFPR16_M2_E16, + PseudoVFMAX_ALT_VFPR16_M2_E16_MASK, + PseudoVFMAX_ALT_VFPR16_M4_E16, + PseudoVFMAX_ALT_VFPR16_M4_E16_MASK, + PseudoVFMAX_ALT_VFPR16_M8_E16, + PseudoVFMAX_ALT_VFPR16_M8_E16_MASK, + PseudoVFMAX_ALT_VFPR16_MF2_E16, + PseudoVFMAX_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMAX_ALT_VFPR16_MF4_E16, + PseudoVFMAX_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMAX_ALT_VV_M1_E16, + PseudoVFMAX_ALT_VV_M1_E16_MASK, + PseudoVFMAX_ALT_VV_M2_E16, + PseudoVFMAX_ALT_VV_M2_E16_MASK, + PseudoVFMAX_ALT_VV_M4_E16, + PseudoVFMAX_ALT_VV_M4_E16_MASK, + PseudoVFMAX_ALT_VV_M8_E16, + PseudoVFMAX_ALT_VV_M8_E16_MASK, + PseudoVFMAX_ALT_VV_MF2_E16, + PseudoVFMAX_ALT_VV_MF2_E16_MASK, + PseudoVFMAX_ALT_VV_MF4_E16, + PseudoVFMAX_ALT_VV_MF4_E16_MASK, + PseudoVFMAX_VFPR16_M1_E16, + PseudoVFMAX_VFPR16_M1_E16_MASK, + PseudoVFMAX_VFPR16_M2_E16, + PseudoVFMAX_VFPR16_M2_E16_MASK, + PseudoVFMAX_VFPR16_M4_E16, + PseudoVFMAX_VFPR16_M4_E16_MASK, + PseudoVFMAX_VFPR16_M8_E16, + PseudoVFMAX_VFPR16_M8_E16_MASK, + PseudoVFMAX_VFPR16_MF2_E16, + PseudoVFMAX_VFPR16_MF2_E16_MASK, + PseudoVFMAX_VFPR16_MF4_E16, + PseudoVFMAX_VFPR16_MF4_E16_MASK, + PseudoVFMAX_VFPR32_M1_E32, + PseudoVFMAX_VFPR32_M1_E32_MASK, + PseudoVFMAX_VFPR32_M2_E32, + PseudoVFMAX_VFPR32_M2_E32_MASK, + PseudoVFMAX_VFPR32_M4_E32, + PseudoVFMAX_VFPR32_M4_E32_MASK, + PseudoVFMAX_VFPR32_M8_E32, + PseudoVFMAX_VFPR32_M8_E32_MASK, + PseudoVFMAX_VFPR32_MF2_E32, + PseudoVFMAX_VFPR32_MF2_E32_MASK, + PseudoVFMAX_VFPR64_M1_E64, + PseudoVFMAX_VFPR64_M1_E64_MASK, + PseudoVFMAX_VFPR64_M2_E64, + PseudoVFMAX_VFPR64_M2_E64_MASK, + PseudoVFMAX_VFPR64_M4_E64, + PseudoVFMAX_VFPR64_M4_E64_MASK, + PseudoVFMAX_VFPR64_M8_E64, + PseudoVFMAX_VFPR64_M8_E64_MASK, + PseudoVFMAX_VV_M1_E16, + PseudoVFMAX_VV_M1_E16_MASK, + PseudoVFMAX_VV_M1_E32, + PseudoVFMAX_VV_M1_E32_MASK, + PseudoVFMAX_VV_M1_E64, + PseudoVFMAX_VV_M1_E64_MASK, + PseudoVFMAX_VV_M2_E16, + PseudoVFMAX_VV_M2_E16_MASK, + PseudoVFMAX_VV_M2_E32, + PseudoVFMAX_VV_M2_E32_MASK, + PseudoVFMAX_VV_M2_E64, + PseudoVFMAX_VV_M2_E64_MASK, + PseudoVFMAX_VV_M4_E16, + PseudoVFMAX_VV_M4_E16_MASK, + PseudoVFMAX_VV_M4_E32, + PseudoVFMAX_VV_M4_E32_MASK, + PseudoVFMAX_VV_M4_E64, + PseudoVFMAX_VV_M4_E64_MASK, + PseudoVFMAX_VV_M8_E16, + PseudoVFMAX_VV_M8_E16_MASK, + PseudoVFMAX_VV_M8_E32, + PseudoVFMAX_VV_M8_E32_MASK, + PseudoVFMAX_VV_M8_E64, + PseudoVFMAX_VV_M8_E64_MASK, + PseudoVFMAX_VV_MF2_E16, + PseudoVFMAX_VV_MF2_E16_MASK, + PseudoVFMAX_VV_MF2_E32, + PseudoVFMAX_VV_MF2_E32_MASK, + PseudoVFMAX_VV_MF4_E16, + PseudoVFMAX_VV_MF4_E16_MASK, + PseudoVFMERGE_ALT_VFPR16M_M1, + PseudoVFMERGE_ALT_VFPR16M_M2, + PseudoVFMERGE_ALT_VFPR16M_M4, + PseudoVFMERGE_ALT_VFPR16M_M8, + PseudoVFMERGE_ALT_VFPR16M_MF2, + PseudoVFMERGE_ALT_VFPR16M_MF4, + PseudoVFMERGE_ALT_VFPR32M_M1, + PseudoVFMERGE_ALT_VFPR32M_M2, + PseudoVFMERGE_ALT_VFPR32M_M4, + PseudoVFMERGE_ALT_VFPR32M_M8, + PseudoVFMERGE_ALT_VFPR32M_MF2, + PseudoVFMERGE_ALT_VFPR64M_M1, + PseudoVFMERGE_ALT_VFPR64M_M2, + PseudoVFMERGE_ALT_VFPR64M_M4, + PseudoVFMERGE_ALT_VFPR64M_M8, + PseudoVFMERGE_VFPR16M_M1, + PseudoVFMERGE_VFPR16M_M2, + PseudoVFMERGE_VFPR16M_M4, + PseudoVFMERGE_VFPR16M_M8, + PseudoVFMERGE_VFPR16M_MF2, + PseudoVFMERGE_VFPR16M_MF4, + PseudoVFMERGE_VFPR32M_M1, + PseudoVFMERGE_VFPR32M_M2, + PseudoVFMERGE_VFPR32M_M4, + PseudoVFMERGE_VFPR32M_M8, + PseudoVFMERGE_VFPR32M_MF2, + PseudoVFMERGE_VFPR64M_M1, + PseudoVFMERGE_VFPR64M_M2, + PseudoVFMERGE_VFPR64M_M4, + PseudoVFMERGE_VFPR64M_M8, + PseudoVFMIN_ALT_VFPR16_M1_E16, + PseudoVFMIN_ALT_VFPR16_M1_E16_MASK, + PseudoVFMIN_ALT_VFPR16_M2_E16, + PseudoVFMIN_ALT_VFPR16_M2_E16_MASK, + PseudoVFMIN_ALT_VFPR16_M4_E16, + PseudoVFMIN_ALT_VFPR16_M4_E16_MASK, + PseudoVFMIN_ALT_VFPR16_M8_E16, + PseudoVFMIN_ALT_VFPR16_M8_E16_MASK, + PseudoVFMIN_ALT_VFPR16_MF2_E16, + PseudoVFMIN_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMIN_ALT_VFPR16_MF4_E16, + PseudoVFMIN_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMIN_ALT_VV_M1_E16, + PseudoVFMIN_ALT_VV_M1_E16_MASK, + PseudoVFMIN_ALT_VV_M2_E16, + PseudoVFMIN_ALT_VV_M2_E16_MASK, + PseudoVFMIN_ALT_VV_M4_E16, + PseudoVFMIN_ALT_VV_M4_E16_MASK, + PseudoVFMIN_ALT_VV_M8_E16, + PseudoVFMIN_ALT_VV_M8_E16_MASK, + PseudoVFMIN_ALT_VV_MF2_E16, + PseudoVFMIN_ALT_VV_MF2_E16_MASK, + PseudoVFMIN_ALT_VV_MF4_E16, + PseudoVFMIN_ALT_VV_MF4_E16_MASK, + PseudoVFMIN_VFPR16_M1_E16, + PseudoVFMIN_VFPR16_M1_E16_MASK, + PseudoVFMIN_VFPR16_M2_E16, + PseudoVFMIN_VFPR16_M2_E16_MASK, + PseudoVFMIN_VFPR16_M4_E16, + PseudoVFMIN_VFPR16_M4_E16_MASK, + PseudoVFMIN_VFPR16_M8_E16, + PseudoVFMIN_VFPR16_M8_E16_MASK, + PseudoVFMIN_VFPR16_MF2_E16, + PseudoVFMIN_VFPR16_MF2_E16_MASK, + PseudoVFMIN_VFPR16_MF4_E16, + PseudoVFMIN_VFPR16_MF4_E16_MASK, + PseudoVFMIN_VFPR32_M1_E32, + PseudoVFMIN_VFPR32_M1_E32_MASK, + PseudoVFMIN_VFPR32_M2_E32, + PseudoVFMIN_VFPR32_M2_E32_MASK, + PseudoVFMIN_VFPR32_M4_E32, + PseudoVFMIN_VFPR32_M4_E32_MASK, + PseudoVFMIN_VFPR32_M8_E32, + PseudoVFMIN_VFPR32_M8_E32_MASK, + PseudoVFMIN_VFPR32_MF2_E32, + PseudoVFMIN_VFPR32_MF2_E32_MASK, + PseudoVFMIN_VFPR64_M1_E64, + PseudoVFMIN_VFPR64_M1_E64_MASK, + PseudoVFMIN_VFPR64_M2_E64, + PseudoVFMIN_VFPR64_M2_E64_MASK, + PseudoVFMIN_VFPR64_M4_E64, + PseudoVFMIN_VFPR64_M4_E64_MASK, + PseudoVFMIN_VFPR64_M8_E64, + PseudoVFMIN_VFPR64_M8_E64_MASK, + PseudoVFMIN_VV_M1_E16, + PseudoVFMIN_VV_M1_E16_MASK, + PseudoVFMIN_VV_M1_E32, + PseudoVFMIN_VV_M1_E32_MASK, + PseudoVFMIN_VV_M1_E64, + PseudoVFMIN_VV_M1_E64_MASK, + PseudoVFMIN_VV_M2_E16, + PseudoVFMIN_VV_M2_E16_MASK, + PseudoVFMIN_VV_M2_E32, + PseudoVFMIN_VV_M2_E32_MASK, + PseudoVFMIN_VV_M2_E64, + PseudoVFMIN_VV_M2_E64_MASK, + PseudoVFMIN_VV_M4_E16, + PseudoVFMIN_VV_M4_E16_MASK, + PseudoVFMIN_VV_M4_E32, + PseudoVFMIN_VV_M4_E32_MASK, + PseudoVFMIN_VV_M4_E64, + PseudoVFMIN_VV_M4_E64_MASK, + PseudoVFMIN_VV_M8_E16, + PseudoVFMIN_VV_M8_E16_MASK, + PseudoVFMIN_VV_M8_E32, + PseudoVFMIN_VV_M8_E32_MASK, + PseudoVFMIN_VV_M8_E64, + PseudoVFMIN_VV_M8_E64_MASK, + PseudoVFMIN_VV_MF2_E16, + PseudoVFMIN_VV_MF2_E16_MASK, + PseudoVFMIN_VV_MF2_E32, + PseudoVFMIN_VV_MF2_E32_MASK, + PseudoVFMIN_VV_MF4_E16, + PseudoVFMIN_VV_MF4_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_M1_E16, + PseudoVFMSAC_ALT_VFPR16_M1_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_M2_E16, + PseudoVFMSAC_ALT_VFPR16_M2_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_M4_E16, + PseudoVFMSAC_ALT_VFPR16_M4_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_M8_E16, + PseudoVFMSAC_ALT_VFPR16_M8_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_MF2_E16, + PseudoVFMSAC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMSAC_ALT_VFPR16_MF4_E16, + PseudoVFMSAC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMSAC_ALT_VV_M1_E16, + PseudoVFMSAC_ALT_VV_M1_E16_MASK, + PseudoVFMSAC_ALT_VV_M2_E16, + PseudoVFMSAC_ALT_VV_M2_E16_MASK, + PseudoVFMSAC_ALT_VV_M4_E16, + PseudoVFMSAC_ALT_VV_M4_E16_MASK, + PseudoVFMSAC_ALT_VV_M8_E16, + PseudoVFMSAC_ALT_VV_M8_E16_MASK, + PseudoVFMSAC_ALT_VV_MF2_E16, + PseudoVFMSAC_ALT_VV_MF2_E16_MASK, + PseudoVFMSAC_ALT_VV_MF4_E16, + PseudoVFMSAC_ALT_VV_MF4_E16_MASK, + PseudoVFMSAC_VFPR16_M1_E16, + PseudoVFMSAC_VFPR16_M1_E16_MASK, + PseudoVFMSAC_VFPR16_M2_E16, + PseudoVFMSAC_VFPR16_M2_E16_MASK, + PseudoVFMSAC_VFPR16_M4_E16, + PseudoVFMSAC_VFPR16_M4_E16_MASK, + PseudoVFMSAC_VFPR16_M8_E16, + PseudoVFMSAC_VFPR16_M8_E16_MASK, + PseudoVFMSAC_VFPR16_MF2_E16, + PseudoVFMSAC_VFPR16_MF2_E16_MASK, + PseudoVFMSAC_VFPR16_MF4_E16, + PseudoVFMSAC_VFPR16_MF4_E16_MASK, + PseudoVFMSAC_VFPR32_M1_E32, + PseudoVFMSAC_VFPR32_M1_E32_MASK, + PseudoVFMSAC_VFPR32_M2_E32, + PseudoVFMSAC_VFPR32_M2_E32_MASK, + PseudoVFMSAC_VFPR32_M4_E32, + PseudoVFMSAC_VFPR32_M4_E32_MASK, + PseudoVFMSAC_VFPR32_M8_E32, + PseudoVFMSAC_VFPR32_M8_E32_MASK, + PseudoVFMSAC_VFPR32_MF2_E32, + PseudoVFMSAC_VFPR32_MF2_E32_MASK, + PseudoVFMSAC_VFPR64_M1_E64, + PseudoVFMSAC_VFPR64_M1_E64_MASK, + PseudoVFMSAC_VFPR64_M2_E64, + PseudoVFMSAC_VFPR64_M2_E64_MASK, + PseudoVFMSAC_VFPR64_M4_E64, + PseudoVFMSAC_VFPR64_M4_E64_MASK, + PseudoVFMSAC_VFPR64_M8_E64, + PseudoVFMSAC_VFPR64_M8_E64_MASK, + PseudoVFMSAC_VV_M1_E16, + PseudoVFMSAC_VV_M1_E16_MASK, + PseudoVFMSAC_VV_M1_E32, + PseudoVFMSAC_VV_M1_E32_MASK, + PseudoVFMSAC_VV_M1_E64, + PseudoVFMSAC_VV_M1_E64_MASK, + PseudoVFMSAC_VV_M2_E16, + PseudoVFMSAC_VV_M2_E16_MASK, + PseudoVFMSAC_VV_M2_E32, + PseudoVFMSAC_VV_M2_E32_MASK, + PseudoVFMSAC_VV_M2_E64, + PseudoVFMSAC_VV_M2_E64_MASK, + PseudoVFMSAC_VV_M4_E16, + PseudoVFMSAC_VV_M4_E16_MASK, + PseudoVFMSAC_VV_M4_E32, + PseudoVFMSAC_VV_M4_E32_MASK, + PseudoVFMSAC_VV_M4_E64, + PseudoVFMSAC_VV_M4_E64_MASK, + PseudoVFMSAC_VV_M8_E16, + PseudoVFMSAC_VV_M8_E16_MASK, + PseudoVFMSAC_VV_M8_E32, + PseudoVFMSAC_VV_M8_E32_MASK, + PseudoVFMSAC_VV_M8_E64, + PseudoVFMSAC_VV_M8_E64_MASK, + PseudoVFMSAC_VV_MF2_E16, + PseudoVFMSAC_VV_MF2_E16_MASK, + PseudoVFMSAC_VV_MF2_E32, + PseudoVFMSAC_VV_MF2_E32_MASK, + PseudoVFMSAC_VV_MF4_E16, + PseudoVFMSAC_VV_MF4_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_M1_E16, + PseudoVFMSUB_ALT_VFPR16_M1_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_M2_E16, + PseudoVFMSUB_ALT_VFPR16_M2_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_M4_E16, + PseudoVFMSUB_ALT_VFPR16_M4_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_M8_E16, + PseudoVFMSUB_ALT_VFPR16_M8_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_MF2_E16, + PseudoVFMSUB_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMSUB_ALT_VFPR16_MF4_E16, + PseudoVFMSUB_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMSUB_ALT_VV_M1_E16, + PseudoVFMSUB_ALT_VV_M1_E16_MASK, + PseudoVFMSUB_ALT_VV_M2_E16, + PseudoVFMSUB_ALT_VV_M2_E16_MASK, + PseudoVFMSUB_ALT_VV_M4_E16, + PseudoVFMSUB_ALT_VV_M4_E16_MASK, + PseudoVFMSUB_ALT_VV_M8_E16, + PseudoVFMSUB_ALT_VV_M8_E16_MASK, + PseudoVFMSUB_ALT_VV_MF2_E16, + PseudoVFMSUB_ALT_VV_MF2_E16_MASK, + PseudoVFMSUB_ALT_VV_MF4_E16, + PseudoVFMSUB_ALT_VV_MF4_E16_MASK, + PseudoVFMSUB_VFPR16_M1_E16, + PseudoVFMSUB_VFPR16_M1_E16_MASK, + PseudoVFMSUB_VFPR16_M2_E16, + PseudoVFMSUB_VFPR16_M2_E16_MASK, + PseudoVFMSUB_VFPR16_M4_E16, + PseudoVFMSUB_VFPR16_M4_E16_MASK, + PseudoVFMSUB_VFPR16_M8_E16, + PseudoVFMSUB_VFPR16_M8_E16_MASK, + PseudoVFMSUB_VFPR16_MF2_E16, + PseudoVFMSUB_VFPR16_MF2_E16_MASK, + PseudoVFMSUB_VFPR16_MF4_E16, + PseudoVFMSUB_VFPR16_MF4_E16_MASK, + PseudoVFMSUB_VFPR32_M1_E32, + PseudoVFMSUB_VFPR32_M1_E32_MASK, + PseudoVFMSUB_VFPR32_M2_E32, + PseudoVFMSUB_VFPR32_M2_E32_MASK, + PseudoVFMSUB_VFPR32_M4_E32, + PseudoVFMSUB_VFPR32_M4_E32_MASK, + PseudoVFMSUB_VFPR32_M8_E32, + PseudoVFMSUB_VFPR32_M8_E32_MASK, + PseudoVFMSUB_VFPR32_MF2_E32, + PseudoVFMSUB_VFPR32_MF2_E32_MASK, + PseudoVFMSUB_VFPR64_M1_E64, + PseudoVFMSUB_VFPR64_M1_E64_MASK, + PseudoVFMSUB_VFPR64_M2_E64, + PseudoVFMSUB_VFPR64_M2_E64_MASK, + PseudoVFMSUB_VFPR64_M4_E64, + PseudoVFMSUB_VFPR64_M4_E64_MASK, + PseudoVFMSUB_VFPR64_M8_E64, + PseudoVFMSUB_VFPR64_M8_E64_MASK, + PseudoVFMSUB_VV_M1_E16, + PseudoVFMSUB_VV_M1_E16_MASK, + PseudoVFMSUB_VV_M1_E32, + PseudoVFMSUB_VV_M1_E32_MASK, + PseudoVFMSUB_VV_M1_E64, + PseudoVFMSUB_VV_M1_E64_MASK, + PseudoVFMSUB_VV_M2_E16, + PseudoVFMSUB_VV_M2_E16_MASK, + PseudoVFMSUB_VV_M2_E32, + PseudoVFMSUB_VV_M2_E32_MASK, + PseudoVFMSUB_VV_M2_E64, + PseudoVFMSUB_VV_M2_E64_MASK, + PseudoVFMSUB_VV_M4_E16, + PseudoVFMSUB_VV_M4_E16_MASK, + PseudoVFMSUB_VV_M4_E32, + PseudoVFMSUB_VV_M4_E32_MASK, + PseudoVFMSUB_VV_M4_E64, + PseudoVFMSUB_VV_M4_E64_MASK, + PseudoVFMSUB_VV_M8_E16, + PseudoVFMSUB_VV_M8_E16_MASK, + PseudoVFMSUB_VV_M8_E32, + PseudoVFMSUB_VV_M8_E32_MASK, + PseudoVFMSUB_VV_M8_E64, + PseudoVFMSUB_VV_M8_E64_MASK, + PseudoVFMSUB_VV_MF2_E16, + PseudoVFMSUB_VV_MF2_E16_MASK, + PseudoVFMSUB_VV_MF2_E32, + PseudoVFMSUB_VV_MF2_E32_MASK, + PseudoVFMSUB_VV_MF4_E16, + PseudoVFMSUB_VV_MF4_E16_MASK, + PseudoVFMUL_ALT_VFPR16_M1_E16, + PseudoVFMUL_ALT_VFPR16_M1_E16_MASK, + PseudoVFMUL_ALT_VFPR16_M2_E16, + PseudoVFMUL_ALT_VFPR16_M2_E16_MASK, + PseudoVFMUL_ALT_VFPR16_M4_E16, + PseudoVFMUL_ALT_VFPR16_M4_E16_MASK, + PseudoVFMUL_ALT_VFPR16_M8_E16, + PseudoVFMUL_ALT_VFPR16_M8_E16_MASK, + PseudoVFMUL_ALT_VFPR16_MF2_E16, + PseudoVFMUL_ALT_VFPR16_MF2_E16_MASK, + PseudoVFMUL_ALT_VFPR16_MF4_E16, + PseudoVFMUL_ALT_VFPR16_MF4_E16_MASK, + PseudoVFMUL_ALT_VV_M1_E16, + PseudoVFMUL_ALT_VV_M1_E16_MASK, + PseudoVFMUL_ALT_VV_M2_E16, + PseudoVFMUL_ALT_VV_M2_E16_MASK, + PseudoVFMUL_ALT_VV_M4_E16, + PseudoVFMUL_ALT_VV_M4_E16_MASK, + PseudoVFMUL_ALT_VV_M8_E16, + PseudoVFMUL_ALT_VV_M8_E16_MASK, + PseudoVFMUL_ALT_VV_MF2_E16, + PseudoVFMUL_ALT_VV_MF2_E16_MASK, + PseudoVFMUL_ALT_VV_MF4_E16, + PseudoVFMUL_ALT_VV_MF4_E16_MASK, + PseudoVFMUL_VFPR16_M1_E16, + PseudoVFMUL_VFPR16_M1_E16_MASK, + PseudoVFMUL_VFPR16_M2_E16, + PseudoVFMUL_VFPR16_M2_E16_MASK, + PseudoVFMUL_VFPR16_M4_E16, + PseudoVFMUL_VFPR16_M4_E16_MASK, + PseudoVFMUL_VFPR16_M8_E16, + PseudoVFMUL_VFPR16_M8_E16_MASK, + PseudoVFMUL_VFPR16_MF2_E16, + PseudoVFMUL_VFPR16_MF2_E16_MASK, + PseudoVFMUL_VFPR16_MF4_E16, + PseudoVFMUL_VFPR16_MF4_E16_MASK, + PseudoVFMUL_VFPR32_M1_E32, + PseudoVFMUL_VFPR32_M1_E32_MASK, + PseudoVFMUL_VFPR32_M2_E32, + PseudoVFMUL_VFPR32_M2_E32_MASK, + PseudoVFMUL_VFPR32_M4_E32, + PseudoVFMUL_VFPR32_M4_E32_MASK, + PseudoVFMUL_VFPR32_M8_E32, + PseudoVFMUL_VFPR32_M8_E32_MASK, + PseudoVFMUL_VFPR32_MF2_E32, + PseudoVFMUL_VFPR32_MF2_E32_MASK, + PseudoVFMUL_VFPR64_M1_E64, + PseudoVFMUL_VFPR64_M1_E64_MASK, + PseudoVFMUL_VFPR64_M2_E64, + PseudoVFMUL_VFPR64_M2_E64_MASK, + PseudoVFMUL_VFPR64_M4_E64, + PseudoVFMUL_VFPR64_M4_E64_MASK, + PseudoVFMUL_VFPR64_M8_E64, + PseudoVFMUL_VFPR64_M8_E64_MASK, + PseudoVFMUL_VV_M1_E16, + PseudoVFMUL_VV_M1_E16_MASK, + PseudoVFMUL_VV_M1_E32, + PseudoVFMUL_VV_M1_E32_MASK, + PseudoVFMUL_VV_M1_E64, + PseudoVFMUL_VV_M1_E64_MASK, + PseudoVFMUL_VV_M2_E16, + PseudoVFMUL_VV_M2_E16_MASK, + PseudoVFMUL_VV_M2_E32, + PseudoVFMUL_VV_M2_E32_MASK, + PseudoVFMUL_VV_M2_E64, + PseudoVFMUL_VV_M2_E64_MASK, + PseudoVFMUL_VV_M4_E16, + PseudoVFMUL_VV_M4_E16_MASK, + PseudoVFMUL_VV_M4_E32, + PseudoVFMUL_VV_M4_E32_MASK, + PseudoVFMUL_VV_M4_E64, + PseudoVFMUL_VV_M4_E64_MASK, + PseudoVFMUL_VV_M8_E16, + PseudoVFMUL_VV_M8_E16_MASK, + PseudoVFMUL_VV_M8_E32, + PseudoVFMUL_VV_M8_E32_MASK, + PseudoVFMUL_VV_M8_E64, + PseudoVFMUL_VV_M8_E64_MASK, + PseudoVFMUL_VV_MF2_E16, + PseudoVFMUL_VV_MF2_E16_MASK, + PseudoVFMUL_VV_MF2_E32, + PseudoVFMUL_VV_MF2_E32_MASK, + PseudoVFMUL_VV_MF4_E16, + PseudoVFMUL_VV_MF4_E16_MASK, + PseudoVFMV_FPR16_S, + PseudoVFMV_FPR16_S_ALT, + PseudoVFMV_FPR32_S, + PseudoVFMV_FPR64_S, + PseudoVFMV_S_FPR16, + PseudoVFMV_S_FPR16_ALT, + PseudoVFMV_S_FPR32, + PseudoVFMV_S_FPR64, + PseudoVFMV_V_ALT_FPR16_M1, + PseudoVFMV_V_ALT_FPR16_M2, + PseudoVFMV_V_ALT_FPR16_M4, + PseudoVFMV_V_ALT_FPR16_M8, + PseudoVFMV_V_ALT_FPR16_MF2, + PseudoVFMV_V_ALT_FPR16_MF4, + PseudoVFMV_V_ALT_FPR32_M1, + PseudoVFMV_V_ALT_FPR32_M2, + PseudoVFMV_V_ALT_FPR32_M4, + PseudoVFMV_V_ALT_FPR32_M8, + PseudoVFMV_V_ALT_FPR32_MF2, + PseudoVFMV_V_ALT_FPR64_M1, + PseudoVFMV_V_ALT_FPR64_M2, + PseudoVFMV_V_ALT_FPR64_M4, + PseudoVFMV_V_ALT_FPR64_M8, + PseudoVFMV_V_FPR16_M1, + PseudoVFMV_V_FPR16_M2, + PseudoVFMV_V_FPR16_M4, + PseudoVFMV_V_FPR16_M8, + PseudoVFMV_V_FPR16_MF2, + PseudoVFMV_V_FPR16_MF4, + PseudoVFMV_V_FPR32_M1, + PseudoVFMV_V_FPR32_M2, + PseudoVFMV_V_FPR32_M4, + PseudoVFMV_V_FPR32_M8, + PseudoVFMV_V_FPR32_MF2, + PseudoVFMV_V_FPR64_M1, + PseudoVFMV_V_FPR64_M2, + PseudoVFMV_V_FPR64_M4, + PseudoVFMV_V_FPR64_M8, + PseudoVFNCVTBF16_F_F_ALT_W_M1_E8, + PseudoVFNCVTBF16_F_F_ALT_W_M1_E8_MASK, + PseudoVFNCVTBF16_F_F_ALT_W_M2_E8, + PseudoVFNCVTBF16_F_F_ALT_W_M2_E8_MASK, + PseudoVFNCVTBF16_F_F_ALT_W_M4_E8, + PseudoVFNCVTBF16_F_F_ALT_W_M4_E8_MASK, + PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8, + PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8_MASK, + PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8, + PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8_MASK, + PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8, + PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8_MASK, + PseudoVFNCVTBF16_F_F_W_M1_E16, + PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, + PseudoVFNCVTBF16_F_F_W_M1_E32, + PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, + PseudoVFNCVTBF16_F_F_W_M1_E8, + PseudoVFNCVTBF16_F_F_W_M1_E8_MASK, + PseudoVFNCVTBF16_F_F_W_M2_E16, + PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, + PseudoVFNCVTBF16_F_F_W_M2_E32, + PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, + PseudoVFNCVTBF16_F_F_W_M2_E8, + PseudoVFNCVTBF16_F_F_W_M2_E8_MASK, + PseudoVFNCVTBF16_F_F_W_M4_E16, + PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, + PseudoVFNCVTBF16_F_F_W_M4_E32, + PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, + PseudoVFNCVTBF16_F_F_W_M4_E8, + PseudoVFNCVTBF16_F_F_W_M4_E8_MASK, + PseudoVFNCVTBF16_F_F_W_MF2_E16, + PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, + PseudoVFNCVTBF16_F_F_W_MF2_E32, + PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, + PseudoVFNCVTBF16_F_F_W_MF2_E8, + PseudoVFNCVTBF16_F_F_W_MF2_E8_MASK, + PseudoVFNCVTBF16_F_F_W_MF4_E16, + PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, + PseudoVFNCVTBF16_F_F_W_MF4_E8, + PseudoVFNCVTBF16_F_F_W_MF4_E8_MASK, + PseudoVFNCVTBF16_F_F_W_MF8_E8, + PseudoVFNCVTBF16_F_F_W_MF8_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8, + PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_M1_E8, + PseudoVFNCVTBF16_SAT_F_F_W_M1_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_M2_E8, + PseudoVFNCVTBF16_SAT_F_F_W_M2_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_M4_E8, + PseudoVFNCVTBF16_SAT_F_F_W_M4_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8, + PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8, + PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8_MASK, + PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8, + PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8_MASK, + PseudoVFNCVT_F_F_ALT_Q_M1_E8, + PseudoVFNCVT_F_F_ALT_Q_M1_E8_MASK, + PseudoVFNCVT_F_F_ALT_Q_M2_E8, + PseudoVFNCVT_F_F_ALT_Q_M2_E8_MASK, + PseudoVFNCVT_F_F_ALT_Q_MF2_E8, + PseudoVFNCVT_F_F_ALT_Q_MF2_E8_MASK, + PseudoVFNCVT_F_F_ALT_Q_MF4_E8, + PseudoVFNCVT_F_F_ALT_Q_MF4_E8_MASK, + PseudoVFNCVT_F_F_ALT_Q_MF8_E8, + PseudoVFNCVT_F_F_ALT_Q_MF8_E8_MASK, + PseudoVFNCVT_F_F_ALT_W_M1_E16, + PseudoVFNCVT_F_F_ALT_W_M1_E16_MASK, + PseudoVFNCVT_F_F_ALT_W_M2_E16, + PseudoVFNCVT_F_F_ALT_W_M2_E16_MASK, + PseudoVFNCVT_F_F_ALT_W_M4_E16, + PseudoVFNCVT_F_F_ALT_W_M4_E16_MASK, + PseudoVFNCVT_F_F_ALT_W_MF2_E16, + PseudoVFNCVT_F_F_ALT_W_MF2_E16_MASK, + PseudoVFNCVT_F_F_ALT_W_MF4_E16, + PseudoVFNCVT_F_F_ALT_W_MF4_E16_MASK, + PseudoVFNCVT_F_F_Q_M1_E8, + PseudoVFNCVT_F_F_Q_M1_E8_MASK, + PseudoVFNCVT_F_F_Q_M2_E8, + PseudoVFNCVT_F_F_Q_M2_E8_MASK, + PseudoVFNCVT_F_F_Q_MF2_E8, + PseudoVFNCVT_F_F_Q_MF2_E8_MASK, + PseudoVFNCVT_F_F_Q_MF4_E8, + PseudoVFNCVT_F_F_Q_MF4_E8_MASK, + PseudoVFNCVT_F_F_Q_MF8_E8, + PseudoVFNCVT_F_F_Q_MF8_E8_MASK, + PseudoVFNCVT_F_F_W_M1_E16, + PseudoVFNCVT_F_F_W_M1_E16_MASK, + PseudoVFNCVT_F_F_W_M1_E32, + PseudoVFNCVT_F_F_W_M1_E32_MASK, + PseudoVFNCVT_F_F_W_M2_E16, + PseudoVFNCVT_F_F_W_M2_E16_MASK, + PseudoVFNCVT_F_F_W_M2_E32, + PseudoVFNCVT_F_F_W_M2_E32_MASK, + PseudoVFNCVT_F_F_W_M4_E16, + PseudoVFNCVT_F_F_W_M4_E16_MASK, + PseudoVFNCVT_F_F_W_M4_E32, + PseudoVFNCVT_F_F_W_M4_E32_MASK, + PseudoVFNCVT_F_F_W_MF2_E16, + PseudoVFNCVT_F_F_W_MF2_E16_MASK, + PseudoVFNCVT_F_F_W_MF2_E32, + PseudoVFNCVT_F_F_W_MF2_E32_MASK, + PseudoVFNCVT_F_F_W_MF4_E16, + PseudoVFNCVT_F_F_W_MF4_E16_MASK, + PseudoVFNCVT_F_XU_W_M1_E16, + PseudoVFNCVT_F_XU_W_M1_E16_MASK, + PseudoVFNCVT_F_XU_W_M1_E32, + PseudoVFNCVT_F_XU_W_M1_E32_MASK, + PseudoVFNCVT_F_XU_W_M2_E16, + PseudoVFNCVT_F_XU_W_M2_E16_MASK, + PseudoVFNCVT_F_XU_W_M2_E32, + PseudoVFNCVT_F_XU_W_M2_E32_MASK, + PseudoVFNCVT_F_XU_W_M4_E16, + PseudoVFNCVT_F_XU_W_M4_E16_MASK, + PseudoVFNCVT_F_XU_W_M4_E32, + PseudoVFNCVT_F_XU_W_M4_E32_MASK, + PseudoVFNCVT_F_XU_W_MF2_E16, + PseudoVFNCVT_F_XU_W_MF2_E16_MASK, + PseudoVFNCVT_F_XU_W_MF2_E32, + PseudoVFNCVT_F_XU_W_MF2_E32_MASK, + PseudoVFNCVT_F_XU_W_MF4_E16, + PseudoVFNCVT_F_XU_W_MF4_E16_MASK, + PseudoVFNCVT_F_X_W_M1_E16, + PseudoVFNCVT_F_X_W_M1_E16_MASK, + PseudoVFNCVT_F_X_W_M1_E32, + PseudoVFNCVT_F_X_W_M1_E32_MASK, + PseudoVFNCVT_F_X_W_M2_E16, + PseudoVFNCVT_F_X_W_M2_E16_MASK, + PseudoVFNCVT_F_X_W_M2_E32, + PseudoVFNCVT_F_X_W_M2_E32_MASK, + PseudoVFNCVT_F_X_W_M4_E16, + PseudoVFNCVT_F_X_W_M4_E16_MASK, + PseudoVFNCVT_F_X_W_M4_E32, + PseudoVFNCVT_F_X_W_M4_E32_MASK, + PseudoVFNCVT_F_X_W_MF2_E16, + PseudoVFNCVT_F_X_W_MF2_E16_MASK, + PseudoVFNCVT_F_X_W_MF2_E32, + PseudoVFNCVT_F_X_W_MF2_E32_MASK, + PseudoVFNCVT_F_X_W_MF4_E16, + PseudoVFNCVT_F_X_W_MF4_E16_MASK, + PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16, + PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16_MASK, + PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16, + PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16_MASK, + PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16, + PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16_MASK, + PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16, + PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16_MASK, + PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16, + PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16_MASK, + PseudoVFNCVT_ROD_F_F_W_M1_E16, + PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, + PseudoVFNCVT_ROD_F_F_W_M1_E32, + PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, + PseudoVFNCVT_ROD_F_F_W_M2_E16, + PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, + PseudoVFNCVT_ROD_F_F_W_M2_E32, + PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, + PseudoVFNCVT_ROD_F_F_W_M4_E16, + PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, + PseudoVFNCVT_ROD_F_F_W_M4_E32, + PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, + PseudoVFNCVT_ROD_F_F_W_MF2_E16, + PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, + PseudoVFNCVT_ROD_F_F_W_MF2_E32, + PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, + PseudoVFNCVT_ROD_F_F_W_MF4_E16, + PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M1, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M1_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M2, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M2_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M4, + PseudoVFNCVT_RTZ_XU_F_ALT_W_M4_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4_MASK, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8, + PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8_MASK, + PseudoVFNCVT_RTZ_XU_F_W_M1, + PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, + PseudoVFNCVT_RTZ_XU_F_W_M2, + PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, + PseudoVFNCVT_RTZ_XU_F_W_M4, + PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, + PseudoVFNCVT_RTZ_XU_F_W_MF2, + PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, + PseudoVFNCVT_RTZ_XU_F_W_MF4, + PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, + PseudoVFNCVT_RTZ_XU_F_W_MF8, + PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_M1, + PseudoVFNCVT_RTZ_X_F_ALT_W_M1_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_M2, + PseudoVFNCVT_RTZ_X_F_ALT_W_M2_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_M4, + PseudoVFNCVT_RTZ_X_F_ALT_W_M4_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF2, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF2_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF4, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF4_MASK, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF8, + PseudoVFNCVT_RTZ_X_F_ALT_W_MF8_MASK, + PseudoVFNCVT_RTZ_X_F_W_M1, + PseudoVFNCVT_RTZ_X_F_W_M1_MASK, + PseudoVFNCVT_RTZ_X_F_W_M2, + PseudoVFNCVT_RTZ_X_F_W_M2_MASK, + PseudoVFNCVT_RTZ_X_F_W_M4, + PseudoVFNCVT_RTZ_X_F_W_M4_MASK, + PseudoVFNCVT_RTZ_X_F_W_MF2, + PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, + PseudoVFNCVT_RTZ_X_F_W_MF4, + PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, + PseudoVFNCVT_RTZ_X_F_W_MF8, + PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, + PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8, + PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8_MASK, + PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8, + PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8_MASK, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8_MASK, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8_MASK, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8, + PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8_MASK, + PseudoVFNCVT_SAT_F_F_Q_M1_E8, + PseudoVFNCVT_SAT_F_F_Q_M1_E8_MASK, + PseudoVFNCVT_SAT_F_F_Q_M2_E8, + PseudoVFNCVT_SAT_F_F_Q_M2_E8_MASK, + PseudoVFNCVT_SAT_F_F_Q_MF2_E8, + PseudoVFNCVT_SAT_F_F_Q_MF2_E8_MASK, + PseudoVFNCVT_SAT_F_F_Q_MF4_E8, + PseudoVFNCVT_SAT_F_F_Q_MF4_E8_MASK, + PseudoVFNCVT_SAT_F_F_Q_MF8_E8, + PseudoVFNCVT_SAT_F_F_Q_MF8_E8_MASK, + PseudoVFNCVT_XU_F_ALT_W_M1, + PseudoVFNCVT_XU_F_ALT_W_M1_MASK, + PseudoVFNCVT_XU_F_ALT_W_M2, + PseudoVFNCVT_XU_F_ALT_W_M2_MASK, + PseudoVFNCVT_XU_F_ALT_W_M4, + PseudoVFNCVT_XU_F_ALT_W_M4_MASK, + PseudoVFNCVT_XU_F_ALT_W_MF2, + PseudoVFNCVT_XU_F_ALT_W_MF2_MASK, + PseudoVFNCVT_XU_F_ALT_W_MF4, + PseudoVFNCVT_XU_F_ALT_W_MF4_MASK, + PseudoVFNCVT_XU_F_ALT_W_MF8, + PseudoVFNCVT_XU_F_ALT_W_MF8_MASK, + PseudoVFNCVT_XU_F_W_M1, + PseudoVFNCVT_XU_F_W_M1_MASK, + PseudoVFNCVT_XU_F_W_M2, + PseudoVFNCVT_XU_F_W_M2_MASK, + PseudoVFNCVT_XU_F_W_M4, + PseudoVFNCVT_XU_F_W_M4_MASK, + PseudoVFNCVT_XU_F_W_MF2, + PseudoVFNCVT_XU_F_W_MF2_MASK, + PseudoVFNCVT_XU_F_W_MF4, + PseudoVFNCVT_XU_F_W_MF4_MASK, + PseudoVFNCVT_XU_F_W_MF8, + PseudoVFNCVT_XU_F_W_MF8_MASK, + PseudoVFNCVT_X_F_ALT_W_M1, + PseudoVFNCVT_X_F_ALT_W_M1_MASK, + PseudoVFNCVT_X_F_ALT_W_M2, + PseudoVFNCVT_X_F_ALT_W_M2_MASK, + PseudoVFNCVT_X_F_ALT_W_M4, + PseudoVFNCVT_X_F_ALT_W_M4_MASK, + PseudoVFNCVT_X_F_ALT_W_MF2, + PseudoVFNCVT_X_F_ALT_W_MF2_MASK, + PseudoVFNCVT_X_F_ALT_W_MF4, + PseudoVFNCVT_X_F_ALT_W_MF4_MASK, + PseudoVFNCVT_X_F_ALT_W_MF8, + PseudoVFNCVT_X_F_ALT_W_MF8_MASK, + PseudoVFNCVT_X_F_W_M1, + PseudoVFNCVT_X_F_W_M1_MASK, + PseudoVFNCVT_X_F_W_M2, + PseudoVFNCVT_X_F_W_M2_MASK, + PseudoVFNCVT_X_F_W_M4, + PseudoVFNCVT_X_F_W_M4_MASK, + PseudoVFNCVT_X_F_W_MF2, + PseudoVFNCVT_X_F_W_MF2_MASK, + PseudoVFNCVT_X_F_W_MF4, + PseudoVFNCVT_X_F_W_MF4_MASK, + PseudoVFNCVT_X_F_W_MF8, + PseudoVFNCVT_X_F_W_MF8_MASK, + PseudoVFNMACC_ALT_VFPR16_M1_E16, + PseudoVFNMACC_ALT_VFPR16_M1_E16_MASK, + PseudoVFNMACC_ALT_VFPR16_M2_E16, + PseudoVFNMACC_ALT_VFPR16_M2_E16_MASK, + PseudoVFNMACC_ALT_VFPR16_M4_E16, + PseudoVFNMACC_ALT_VFPR16_M4_E16_MASK, + PseudoVFNMACC_ALT_VFPR16_M8_E16, + PseudoVFNMACC_ALT_VFPR16_M8_E16_MASK, + PseudoVFNMACC_ALT_VFPR16_MF2_E16, + PseudoVFNMACC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFNMACC_ALT_VFPR16_MF4_E16, + PseudoVFNMACC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFNMACC_ALT_VV_M1_E16, + PseudoVFNMACC_ALT_VV_M1_E16_MASK, + PseudoVFNMACC_ALT_VV_M2_E16, + PseudoVFNMACC_ALT_VV_M2_E16_MASK, + PseudoVFNMACC_ALT_VV_M4_E16, + PseudoVFNMACC_ALT_VV_M4_E16_MASK, + PseudoVFNMACC_ALT_VV_M8_E16, + PseudoVFNMACC_ALT_VV_M8_E16_MASK, + PseudoVFNMACC_ALT_VV_MF2_E16, + PseudoVFNMACC_ALT_VV_MF2_E16_MASK, + PseudoVFNMACC_ALT_VV_MF4_E16, + PseudoVFNMACC_ALT_VV_MF4_E16_MASK, + PseudoVFNMACC_VFPR16_M1_E16, + PseudoVFNMACC_VFPR16_M1_E16_MASK, + PseudoVFNMACC_VFPR16_M2_E16, + PseudoVFNMACC_VFPR16_M2_E16_MASK, + PseudoVFNMACC_VFPR16_M4_E16, + PseudoVFNMACC_VFPR16_M4_E16_MASK, + PseudoVFNMACC_VFPR16_M8_E16, + PseudoVFNMACC_VFPR16_M8_E16_MASK, + PseudoVFNMACC_VFPR16_MF2_E16, + PseudoVFNMACC_VFPR16_MF2_E16_MASK, + PseudoVFNMACC_VFPR16_MF4_E16, + PseudoVFNMACC_VFPR16_MF4_E16_MASK, + PseudoVFNMACC_VFPR32_M1_E32, + PseudoVFNMACC_VFPR32_M1_E32_MASK, + PseudoVFNMACC_VFPR32_M2_E32, + PseudoVFNMACC_VFPR32_M2_E32_MASK, + PseudoVFNMACC_VFPR32_M4_E32, + PseudoVFNMACC_VFPR32_M4_E32_MASK, + PseudoVFNMACC_VFPR32_M8_E32, + PseudoVFNMACC_VFPR32_M8_E32_MASK, + PseudoVFNMACC_VFPR32_MF2_E32, + PseudoVFNMACC_VFPR32_MF2_E32_MASK, + PseudoVFNMACC_VFPR64_M1_E64, + PseudoVFNMACC_VFPR64_M1_E64_MASK, + PseudoVFNMACC_VFPR64_M2_E64, + PseudoVFNMACC_VFPR64_M2_E64_MASK, + PseudoVFNMACC_VFPR64_M4_E64, + PseudoVFNMACC_VFPR64_M4_E64_MASK, + PseudoVFNMACC_VFPR64_M8_E64, + PseudoVFNMACC_VFPR64_M8_E64_MASK, + PseudoVFNMACC_VV_M1_E16, + PseudoVFNMACC_VV_M1_E16_MASK, + PseudoVFNMACC_VV_M1_E32, + PseudoVFNMACC_VV_M1_E32_MASK, + PseudoVFNMACC_VV_M1_E64, + PseudoVFNMACC_VV_M1_E64_MASK, + PseudoVFNMACC_VV_M2_E16, + PseudoVFNMACC_VV_M2_E16_MASK, + PseudoVFNMACC_VV_M2_E32, + PseudoVFNMACC_VV_M2_E32_MASK, + PseudoVFNMACC_VV_M2_E64, + PseudoVFNMACC_VV_M2_E64_MASK, + PseudoVFNMACC_VV_M4_E16, + PseudoVFNMACC_VV_M4_E16_MASK, + PseudoVFNMACC_VV_M4_E32, + PseudoVFNMACC_VV_M4_E32_MASK, + PseudoVFNMACC_VV_M4_E64, + PseudoVFNMACC_VV_M4_E64_MASK, + PseudoVFNMACC_VV_M8_E16, + PseudoVFNMACC_VV_M8_E16_MASK, + PseudoVFNMACC_VV_M8_E32, + PseudoVFNMACC_VV_M8_E32_MASK, + PseudoVFNMACC_VV_M8_E64, + PseudoVFNMACC_VV_M8_E64_MASK, + PseudoVFNMACC_VV_MF2_E16, + PseudoVFNMACC_VV_MF2_E16_MASK, + PseudoVFNMACC_VV_MF2_E32, + PseudoVFNMACC_VV_MF2_E32_MASK, + PseudoVFNMACC_VV_MF4_E16, + PseudoVFNMACC_VV_MF4_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_M1_E16, + PseudoVFNMADD_ALT_VFPR16_M1_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_M2_E16, + PseudoVFNMADD_ALT_VFPR16_M2_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_M4_E16, + PseudoVFNMADD_ALT_VFPR16_M4_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_M8_E16, + PseudoVFNMADD_ALT_VFPR16_M8_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_MF2_E16, + PseudoVFNMADD_ALT_VFPR16_MF2_E16_MASK, + PseudoVFNMADD_ALT_VFPR16_MF4_E16, + PseudoVFNMADD_ALT_VFPR16_MF4_E16_MASK, + PseudoVFNMADD_ALT_VV_M1_E16, + PseudoVFNMADD_ALT_VV_M1_E16_MASK, + PseudoVFNMADD_ALT_VV_M2_E16, + PseudoVFNMADD_ALT_VV_M2_E16_MASK, + PseudoVFNMADD_ALT_VV_M4_E16, + PseudoVFNMADD_ALT_VV_M4_E16_MASK, + PseudoVFNMADD_ALT_VV_M8_E16, + PseudoVFNMADD_ALT_VV_M8_E16_MASK, + PseudoVFNMADD_ALT_VV_MF2_E16, + PseudoVFNMADD_ALT_VV_MF2_E16_MASK, + PseudoVFNMADD_ALT_VV_MF4_E16, + PseudoVFNMADD_ALT_VV_MF4_E16_MASK, + PseudoVFNMADD_VFPR16_M1_E16, + PseudoVFNMADD_VFPR16_M1_E16_MASK, + PseudoVFNMADD_VFPR16_M2_E16, + PseudoVFNMADD_VFPR16_M2_E16_MASK, + PseudoVFNMADD_VFPR16_M4_E16, + PseudoVFNMADD_VFPR16_M4_E16_MASK, + PseudoVFNMADD_VFPR16_M8_E16, + PseudoVFNMADD_VFPR16_M8_E16_MASK, + PseudoVFNMADD_VFPR16_MF2_E16, + PseudoVFNMADD_VFPR16_MF2_E16_MASK, + PseudoVFNMADD_VFPR16_MF4_E16, + PseudoVFNMADD_VFPR16_MF4_E16_MASK, + PseudoVFNMADD_VFPR32_M1_E32, + PseudoVFNMADD_VFPR32_M1_E32_MASK, + PseudoVFNMADD_VFPR32_M2_E32, + PseudoVFNMADD_VFPR32_M2_E32_MASK, + PseudoVFNMADD_VFPR32_M4_E32, + PseudoVFNMADD_VFPR32_M4_E32_MASK, + PseudoVFNMADD_VFPR32_M8_E32, + PseudoVFNMADD_VFPR32_M8_E32_MASK, + PseudoVFNMADD_VFPR32_MF2_E32, + PseudoVFNMADD_VFPR32_MF2_E32_MASK, + PseudoVFNMADD_VFPR64_M1_E64, + PseudoVFNMADD_VFPR64_M1_E64_MASK, + PseudoVFNMADD_VFPR64_M2_E64, + PseudoVFNMADD_VFPR64_M2_E64_MASK, + PseudoVFNMADD_VFPR64_M4_E64, + PseudoVFNMADD_VFPR64_M4_E64_MASK, + PseudoVFNMADD_VFPR64_M8_E64, + PseudoVFNMADD_VFPR64_M8_E64_MASK, + PseudoVFNMADD_VV_M1_E16, + PseudoVFNMADD_VV_M1_E16_MASK, + PseudoVFNMADD_VV_M1_E32, + PseudoVFNMADD_VV_M1_E32_MASK, + PseudoVFNMADD_VV_M1_E64, + PseudoVFNMADD_VV_M1_E64_MASK, + PseudoVFNMADD_VV_M2_E16, + PseudoVFNMADD_VV_M2_E16_MASK, + PseudoVFNMADD_VV_M2_E32, + PseudoVFNMADD_VV_M2_E32_MASK, + PseudoVFNMADD_VV_M2_E64, + PseudoVFNMADD_VV_M2_E64_MASK, + PseudoVFNMADD_VV_M4_E16, + PseudoVFNMADD_VV_M4_E16_MASK, + PseudoVFNMADD_VV_M4_E32, + PseudoVFNMADD_VV_M4_E32_MASK, + PseudoVFNMADD_VV_M4_E64, + PseudoVFNMADD_VV_M4_E64_MASK, + PseudoVFNMADD_VV_M8_E16, + PseudoVFNMADD_VV_M8_E16_MASK, + PseudoVFNMADD_VV_M8_E32, + PseudoVFNMADD_VV_M8_E32_MASK, + PseudoVFNMADD_VV_M8_E64, + PseudoVFNMADD_VV_M8_E64_MASK, + PseudoVFNMADD_VV_MF2_E16, + PseudoVFNMADD_VV_MF2_E16_MASK, + PseudoVFNMADD_VV_MF2_E32, + PseudoVFNMADD_VV_MF2_E32_MASK, + PseudoVFNMADD_VV_MF4_E16, + PseudoVFNMADD_VV_MF4_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_M1_E16, + PseudoVFNMSAC_ALT_VFPR16_M1_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_M2_E16, + PseudoVFNMSAC_ALT_VFPR16_M2_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_M4_E16, + PseudoVFNMSAC_ALT_VFPR16_M4_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_M8_E16, + PseudoVFNMSAC_ALT_VFPR16_M8_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_MF2_E16, + PseudoVFNMSAC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFNMSAC_ALT_VFPR16_MF4_E16, + PseudoVFNMSAC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFNMSAC_ALT_VV_M1_E16, + PseudoVFNMSAC_ALT_VV_M1_E16_MASK, + PseudoVFNMSAC_ALT_VV_M2_E16, + PseudoVFNMSAC_ALT_VV_M2_E16_MASK, + PseudoVFNMSAC_ALT_VV_M4_E16, + PseudoVFNMSAC_ALT_VV_M4_E16_MASK, + PseudoVFNMSAC_ALT_VV_M8_E16, + PseudoVFNMSAC_ALT_VV_M8_E16_MASK, + PseudoVFNMSAC_ALT_VV_MF2_E16, + PseudoVFNMSAC_ALT_VV_MF2_E16_MASK, + PseudoVFNMSAC_ALT_VV_MF4_E16, + PseudoVFNMSAC_ALT_VV_MF4_E16_MASK, + PseudoVFNMSAC_VFPR16_M1_E16, + PseudoVFNMSAC_VFPR16_M1_E16_MASK, + PseudoVFNMSAC_VFPR16_M2_E16, + PseudoVFNMSAC_VFPR16_M2_E16_MASK, + PseudoVFNMSAC_VFPR16_M4_E16, + PseudoVFNMSAC_VFPR16_M4_E16_MASK, + PseudoVFNMSAC_VFPR16_M8_E16, + PseudoVFNMSAC_VFPR16_M8_E16_MASK, + PseudoVFNMSAC_VFPR16_MF2_E16, + PseudoVFNMSAC_VFPR16_MF2_E16_MASK, + PseudoVFNMSAC_VFPR16_MF4_E16, + PseudoVFNMSAC_VFPR16_MF4_E16_MASK, + PseudoVFNMSAC_VFPR32_M1_E32, + PseudoVFNMSAC_VFPR32_M1_E32_MASK, + PseudoVFNMSAC_VFPR32_M2_E32, + PseudoVFNMSAC_VFPR32_M2_E32_MASK, + PseudoVFNMSAC_VFPR32_M4_E32, + PseudoVFNMSAC_VFPR32_M4_E32_MASK, + PseudoVFNMSAC_VFPR32_M8_E32, + PseudoVFNMSAC_VFPR32_M8_E32_MASK, + PseudoVFNMSAC_VFPR32_MF2_E32, + PseudoVFNMSAC_VFPR32_MF2_E32_MASK, + PseudoVFNMSAC_VFPR64_M1_E64, + PseudoVFNMSAC_VFPR64_M1_E64_MASK, + PseudoVFNMSAC_VFPR64_M2_E64, + PseudoVFNMSAC_VFPR64_M2_E64_MASK, + PseudoVFNMSAC_VFPR64_M4_E64, + PseudoVFNMSAC_VFPR64_M4_E64_MASK, + PseudoVFNMSAC_VFPR64_M8_E64, + PseudoVFNMSAC_VFPR64_M8_E64_MASK, + PseudoVFNMSAC_VV_M1_E16, + PseudoVFNMSAC_VV_M1_E16_MASK, + PseudoVFNMSAC_VV_M1_E32, + PseudoVFNMSAC_VV_M1_E32_MASK, + PseudoVFNMSAC_VV_M1_E64, + PseudoVFNMSAC_VV_M1_E64_MASK, + PseudoVFNMSAC_VV_M2_E16, + PseudoVFNMSAC_VV_M2_E16_MASK, + PseudoVFNMSAC_VV_M2_E32, + PseudoVFNMSAC_VV_M2_E32_MASK, + PseudoVFNMSAC_VV_M2_E64, + PseudoVFNMSAC_VV_M2_E64_MASK, + PseudoVFNMSAC_VV_M4_E16, + PseudoVFNMSAC_VV_M4_E16_MASK, + PseudoVFNMSAC_VV_M4_E32, + PseudoVFNMSAC_VV_M4_E32_MASK, + PseudoVFNMSAC_VV_M4_E64, + PseudoVFNMSAC_VV_M4_E64_MASK, + PseudoVFNMSAC_VV_M8_E16, + PseudoVFNMSAC_VV_M8_E16_MASK, + PseudoVFNMSAC_VV_M8_E32, + PseudoVFNMSAC_VV_M8_E32_MASK, + PseudoVFNMSAC_VV_M8_E64, + PseudoVFNMSAC_VV_M8_E64_MASK, + PseudoVFNMSAC_VV_MF2_E16, + PseudoVFNMSAC_VV_MF2_E16_MASK, + PseudoVFNMSAC_VV_MF2_E32, + PseudoVFNMSAC_VV_MF2_E32_MASK, + PseudoVFNMSAC_VV_MF4_E16, + PseudoVFNMSAC_VV_MF4_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_M1_E16, + PseudoVFNMSUB_ALT_VFPR16_M1_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_M2_E16, + PseudoVFNMSUB_ALT_VFPR16_M2_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_M4_E16, + PseudoVFNMSUB_ALT_VFPR16_M4_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_M8_E16, + PseudoVFNMSUB_ALT_VFPR16_M8_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_MF2_E16, + PseudoVFNMSUB_ALT_VFPR16_MF2_E16_MASK, + PseudoVFNMSUB_ALT_VFPR16_MF4_E16, + PseudoVFNMSUB_ALT_VFPR16_MF4_E16_MASK, + PseudoVFNMSUB_ALT_VV_M1_E16, + PseudoVFNMSUB_ALT_VV_M1_E16_MASK, + PseudoVFNMSUB_ALT_VV_M2_E16, + PseudoVFNMSUB_ALT_VV_M2_E16_MASK, + PseudoVFNMSUB_ALT_VV_M4_E16, + PseudoVFNMSUB_ALT_VV_M4_E16_MASK, + PseudoVFNMSUB_ALT_VV_M8_E16, + PseudoVFNMSUB_ALT_VV_M8_E16_MASK, + PseudoVFNMSUB_ALT_VV_MF2_E16, + PseudoVFNMSUB_ALT_VV_MF2_E16_MASK, + PseudoVFNMSUB_ALT_VV_MF4_E16, + PseudoVFNMSUB_ALT_VV_MF4_E16_MASK, + PseudoVFNMSUB_VFPR16_M1_E16, + PseudoVFNMSUB_VFPR16_M1_E16_MASK, + PseudoVFNMSUB_VFPR16_M2_E16, + PseudoVFNMSUB_VFPR16_M2_E16_MASK, + PseudoVFNMSUB_VFPR16_M4_E16, + PseudoVFNMSUB_VFPR16_M4_E16_MASK, + PseudoVFNMSUB_VFPR16_M8_E16, + PseudoVFNMSUB_VFPR16_M8_E16_MASK, + PseudoVFNMSUB_VFPR16_MF2_E16, + PseudoVFNMSUB_VFPR16_MF2_E16_MASK, + PseudoVFNMSUB_VFPR16_MF4_E16, + PseudoVFNMSUB_VFPR16_MF4_E16_MASK, + PseudoVFNMSUB_VFPR32_M1_E32, + PseudoVFNMSUB_VFPR32_M1_E32_MASK, + PseudoVFNMSUB_VFPR32_M2_E32, + PseudoVFNMSUB_VFPR32_M2_E32_MASK, + PseudoVFNMSUB_VFPR32_M4_E32, + PseudoVFNMSUB_VFPR32_M4_E32_MASK, + PseudoVFNMSUB_VFPR32_M8_E32, + PseudoVFNMSUB_VFPR32_M8_E32_MASK, + PseudoVFNMSUB_VFPR32_MF2_E32, + PseudoVFNMSUB_VFPR32_MF2_E32_MASK, + PseudoVFNMSUB_VFPR64_M1_E64, + PseudoVFNMSUB_VFPR64_M1_E64_MASK, + PseudoVFNMSUB_VFPR64_M2_E64, + PseudoVFNMSUB_VFPR64_M2_E64_MASK, + PseudoVFNMSUB_VFPR64_M4_E64, + PseudoVFNMSUB_VFPR64_M4_E64_MASK, + PseudoVFNMSUB_VFPR64_M8_E64, + PseudoVFNMSUB_VFPR64_M8_E64_MASK, + PseudoVFNMSUB_VV_M1_E16, + PseudoVFNMSUB_VV_M1_E16_MASK, + PseudoVFNMSUB_VV_M1_E32, + PseudoVFNMSUB_VV_M1_E32_MASK, + PseudoVFNMSUB_VV_M1_E64, + PseudoVFNMSUB_VV_M1_E64_MASK, + PseudoVFNMSUB_VV_M2_E16, + PseudoVFNMSUB_VV_M2_E16_MASK, + PseudoVFNMSUB_VV_M2_E32, + PseudoVFNMSUB_VV_M2_E32_MASK, + PseudoVFNMSUB_VV_M2_E64, + PseudoVFNMSUB_VV_M2_E64_MASK, + PseudoVFNMSUB_VV_M4_E16, + PseudoVFNMSUB_VV_M4_E16_MASK, + PseudoVFNMSUB_VV_M4_E32, + PseudoVFNMSUB_VV_M4_E32_MASK, + PseudoVFNMSUB_VV_M4_E64, + PseudoVFNMSUB_VV_M4_E64_MASK, + PseudoVFNMSUB_VV_M8_E16, + PseudoVFNMSUB_VV_M8_E16_MASK, + PseudoVFNMSUB_VV_M8_E32, + PseudoVFNMSUB_VV_M8_E32_MASK, + PseudoVFNMSUB_VV_M8_E64, + PseudoVFNMSUB_VV_M8_E64_MASK, + PseudoVFNMSUB_VV_MF2_E16, + PseudoVFNMSUB_VV_MF2_E16_MASK, + PseudoVFNMSUB_VV_MF2_E32, + PseudoVFNMSUB_VV_MF2_E32_MASK, + PseudoVFNMSUB_VV_MF4_E16, + PseudoVFNMSUB_VV_MF4_E16_MASK, + PseudoVFRDIV_VFPR16_M1_E16, + PseudoVFRDIV_VFPR16_M1_E16_MASK, + PseudoVFRDIV_VFPR16_M2_E16, + PseudoVFRDIV_VFPR16_M2_E16_MASK, + PseudoVFRDIV_VFPR16_M4_E16, + PseudoVFRDIV_VFPR16_M4_E16_MASK, + PseudoVFRDIV_VFPR16_M8_E16, + PseudoVFRDIV_VFPR16_M8_E16_MASK, + PseudoVFRDIV_VFPR16_MF2_E16, + PseudoVFRDIV_VFPR16_MF2_E16_MASK, + PseudoVFRDIV_VFPR16_MF4_E16, + PseudoVFRDIV_VFPR16_MF4_E16_MASK, + PseudoVFRDIV_VFPR32_M1_E32, + PseudoVFRDIV_VFPR32_M1_E32_MASK, + PseudoVFRDIV_VFPR32_M2_E32, + PseudoVFRDIV_VFPR32_M2_E32_MASK, + PseudoVFRDIV_VFPR32_M4_E32, + PseudoVFRDIV_VFPR32_M4_E32_MASK, + PseudoVFRDIV_VFPR32_M8_E32, + PseudoVFRDIV_VFPR32_M8_E32_MASK, + PseudoVFRDIV_VFPR32_MF2_E32, + PseudoVFRDIV_VFPR32_MF2_E32_MASK, + PseudoVFRDIV_VFPR64_M1_E64, + PseudoVFRDIV_VFPR64_M1_E64_MASK, + PseudoVFRDIV_VFPR64_M2_E64, + PseudoVFRDIV_VFPR64_M2_E64_MASK, + PseudoVFRDIV_VFPR64_M4_E64, + PseudoVFRDIV_VFPR64_M4_E64_MASK, + PseudoVFRDIV_VFPR64_M8_E64, + PseudoVFRDIV_VFPR64_M8_E64_MASK, + PseudoVFREC7_ALT_V_M1_E16, + PseudoVFREC7_ALT_V_M1_E16_MASK, + PseudoVFREC7_ALT_V_M2_E16, + PseudoVFREC7_ALT_V_M2_E16_MASK, + PseudoVFREC7_ALT_V_M4_E16, + PseudoVFREC7_ALT_V_M4_E16_MASK, + PseudoVFREC7_ALT_V_M8_E16, + PseudoVFREC7_ALT_V_M8_E16_MASK, + PseudoVFREC7_ALT_V_MF2_E16, + PseudoVFREC7_ALT_V_MF2_E16_MASK, + PseudoVFREC7_ALT_V_MF4_E16, + PseudoVFREC7_ALT_V_MF4_E16_MASK, + PseudoVFREC7_V_M1_E16, + PseudoVFREC7_V_M1_E16_MASK, + PseudoVFREC7_V_M1_E32, + PseudoVFREC7_V_M1_E32_MASK, + PseudoVFREC7_V_M1_E64, + PseudoVFREC7_V_M1_E64_MASK, + PseudoVFREC7_V_M2_E16, + PseudoVFREC7_V_M2_E16_MASK, + PseudoVFREC7_V_M2_E32, + PseudoVFREC7_V_M2_E32_MASK, + PseudoVFREC7_V_M2_E64, + PseudoVFREC7_V_M2_E64_MASK, + PseudoVFREC7_V_M4_E16, + PseudoVFREC7_V_M4_E16_MASK, + PseudoVFREC7_V_M4_E32, + PseudoVFREC7_V_M4_E32_MASK, + PseudoVFREC7_V_M4_E64, + PseudoVFREC7_V_M4_E64_MASK, + PseudoVFREC7_V_M8_E16, + PseudoVFREC7_V_M8_E16_MASK, + PseudoVFREC7_V_M8_E32, + PseudoVFREC7_V_M8_E32_MASK, + PseudoVFREC7_V_M8_E64, + PseudoVFREC7_V_M8_E64_MASK, + PseudoVFREC7_V_MF2_E16, + PseudoVFREC7_V_MF2_E16_MASK, + PseudoVFREC7_V_MF2_E32, + PseudoVFREC7_V_MF2_E32_MASK, + PseudoVFREC7_V_MF4_E16, + PseudoVFREC7_V_MF4_E16_MASK, + PseudoVFREDMAX_VS_M1_E16, + PseudoVFREDMAX_VS_M1_E16_MASK, + PseudoVFREDMAX_VS_M1_E32, + PseudoVFREDMAX_VS_M1_E32_MASK, + PseudoVFREDMAX_VS_M1_E64, + PseudoVFREDMAX_VS_M1_E64_MASK, + PseudoVFREDMAX_VS_M2_E16, + PseudoVFREDMAX_VS_M2_E16_MASK, + PseudoVFREDMAX_VS_M2_E32, + PseudoVFREDMAX_VS_M2_E32_MASK, + PseudoVFREDMAX_VS_M2_E64, + PseudoVFREDMAX_VS_M2_E64_MASK, + PseudoVFREDMAX_VS_M4_E16, + PseudoVFREDMAX_VS_M4_E16_MASK, + PseudoVFREDMAX_VS_M4_E32, + PseudoVFREDMAX_VS_M4_E32_MASK, + PseudoVFREDMAX_VS_M4_E64, + PseudoVFREDMAX_VS_M4_E64_MASK, + PseudoVFREDMAX_VS_M8_E16, + PseudoVFREDMAX_VS_M8_E16_MASK, + PseudoVFREDMAX_VS_M8_E32, + PseudoVFREDMAX_VS_M8_E32_MASK, + PseudoVFREDMAX_VS_M8_E64, + PseudoVFREDMAX_VS_M8_E64_MASK, + PseudoVFREDMAX_VS_MF2_E16, + PseudoVFREDMAX_VS_MF2_E16_MASK, + PseudoVFREDMAX_VS_MF2_E32, + PseudoVFREDMAX_VS_MF2_E32_MASK, + PseudoVFREDMAX_VS_MF4_E16, + PseudoVFREDMAX_VS_MF4_E16_MASK, + PseudoVFREDMIN_VS_M1_E16, + PseudoVFREDMIN_VS_M1_E16_MASK, + PseudoVFREDMIN_VS_M1_E32, + PseudoVFREDMIN_VS_M1_E32_MASK, + PseudoVFREDMIN_VS_M1_E64, + PseudoVFREDMIN_VS_M1_E64_MASK, + PseudoVFREDMIN_VS_M2_E16, + PseudoVFREDMIN_VS_M2_E16_MASK, + PseudoVFREDMIN_VS_M2_E32, + PseudoVFREDMIN_VS_M2_E32_MASK, + PseudoVFREDMIN_VS_M2_E64, + PseudoVFREDMIN_VS_M2_E64_MASK, + PseudoVFREDMIN_VS_M4_E16, + PseudoVFREDMIN_VS_M4_E16_MASK, + PseudoVFREDMIN_VS_M4_E32, + PseudoVFREDMIN_VS_M4_E32_MASK, + PseudoVFREDMIN_VS_M4_E64, + PseudoVFREDMIN_VS_M4_E64_MASK, + PseudoVFREDMIN_VS_M8_E16, + PseudoVFREDMIN_VS_M8_E16_MASK, + PseudoVFREDMIN_VS_M8_E32, + PseudoVFREDMIN_VS_M8_E32_MASK, + PseudoVFREDMIN_VS_M8_E64, + PseudoVFREDMIN_VS_M8_E64_MASK, + PseudoVFREDMIN_VS_MF2_E16, + PseudoVFREDMIN_VS_MF2_E16_MASK, + PseudoVFREDMIN_VS_MF2_E32, + PseudoVFREDMIN_VS_MF2_E32_MASK, + PseudoVFREDMIN_VS_MF4_E16, + PseudoVFREDMIN_VS_MF4_E16_MASK, + PseudoVFREDOSUM_VS_M1_E16, + PseudoVFREDOSUM_VS_M1_E16_MASK, + PseudoVFREDOSUM_VS_M1_E32, + PseudoVFREDOSUM_VS_M1_E32_MASK, + PseudoVFREDOSUM_VS_M1_E64, + PseudoVFREDOSUM_VS_M1_E64_MASK, + PseudoVFREDOSUM_VS_M2_E16, + PseudoVFREDOSUM_VS_M2_E16_MASK, + PseudoVFREDOSUM_VS_M2_E32, + PseudoVFREDOSUM_VS_M2_E32_MASK, + PseudoVFREDOSUM_VS_M2_E64, + PseudoVFREDOSUM_VS_M2_E64_MASK, + PseudoVFREDOSUM_VS_M4_E16, + PseudoVFREDOSUM_VS_M4_E16_MASK, + PseudoVFREDOSUM_VS_M4_E32, + PseudoVFREDOSUM_VS_M4_E32_MASK, + PseudoVFREDOSUM_VS_M4_E64, + PseudoVFREDOSUM_VS_M4_E64_MASK, + PseudoVFREDOSUM_VS_M8_E16, + PseudoVFREDOSUM_VS_M8_E16_MASK, + PseudoVFREDOSUM_VS_M8_E32, + PseudoVFREDOSUM_VS_M8_E32_MASK, + PseudoVFREDOSUM_VS_M8_E64, + PseudoVFREDOSUM_VS_M8_E64_MASK, + PseudoVFREDOSUM_VS_MF2_E16, + PseudoVFREDOSUM_VS_MF2_E16_MASK, + PseudoVFREDOSUM_VS_MF2_E32, + PseudoVFREDOSUM_VS_MF2_E32_MASK, + PseudoVFREDOSUM_VS_MF4_E16, + PseudoVFREDOSUM_VS_MF4_E16_MASK, + PseudoVFREDUSUM_VS_M1_E16, + PseudoVFREDUSUM_VS_M1_E16_MASK, + PseudoVFREDUSUM_VS_M1_E32, + PseudoVFREDUSUM_VS_M1_E32_MASK, + PseudoVFREDUSUM_VS_M1_E64, + PseudoVFREDUSUM_VS_M1_E64_MASK, + PseudoVFREDUSUM_VS_M2_E16, + PseudoVFREDUSUM_VS_M2_E16_MASK, + PseudoVFREDUSUM_VS_M2_E32, + PseudoVFREDUSUM_VS_M2_E32_MASK, + PseudoVFREDUSUM_VS_M2_E64, + PseudoVFREDUSUM_VS_M2_E64_MASK, + PseudoVFREDUSUM_VS_M4_E16, + PseudoVFREDUSUM_VS_M4_E16_MASK, + PseudoVFREDUSUM_VS_M4_E32, + PseudoVFREDUSUM_VS_M4_E32_MASK, + PseudoVFREDUSUM_VS_M4_E64, + PseudoVFREDUSUM_VS_M4_E64_MASK, + PseudoVFREDUSUM_VS_M8_E16, + PseudoVFREDUSUM_VS_M8_E16_MASK, + PseudoVFREDUSUM_VS_M8_E32, + PseudoVFREDUSUM_VS_M8_E32_MASK, + PseudoVFREDUSUM_VS_M8_E64, + PseudoVFREDUSUM_VS_M8_E64_MASK, + PseudoVFREDUSUM_VS_MF2_E16, + PseudoVFREDUSUM_VS_MF2_E16_MASK, + PseudoVFREDUSUM_VS_MF2_E32, + PseudoVFREDUSUM_VS_MF2_E32_MASK, + PseudoVFREDUSUM_VS_MF4_E16, + PseudoVFREDUSUM_VS_MF4_E16_MASK, + PseudoVFROUND_NOEXCEPT_V_M1_MASK, + PseudoVFROUND_NOEXCEPT_V_M2_MASK, + PseudoVFROUND_NOEXCEPT_V_M4_MASK, + PseudoVFROUND_NOEXCEPT_V_M8_MASK, + PseudoVFROUND_NOEXCEPT_V_MF2_MASK, + PseudoVFROUND_NOEXCEPT_V_MF4_MASK, + PseudoVFRSQRT7_ALT_V_M1_E16, + PseudoVFRSQRT7_ALT_V_M1_E16_MASK, + PseudoVFRSQRT7_ALT_V_M2_E16, + PseudoVFRSQRT7_ALT_V_M2_E16_MASK, + PseudoVFRSQRT7_ALT_V_M4_E16, + PseudoVFRSQRT7_ALT_V_M4_E16_MASK, + PseudoVFRSQRT7_ALT_V_M8_E16, + PseudoVFRSQRT7_ALT_V_M8_E16_MASK, + PseudoVFRSQRT7_ALT_V_MF2_E16, + PseudoVFRSQRT7_ALT_V_MF2_E16_MASK, + PseudoVFRSQRT7_ALT_V_MF4_E16, + PseudoVFRSQRT7_ALT_V_MF4_E16_MASK, + PseudoVFRSQRT7_V_M1_E16, + PseudoVFRSQRT7_V_M1_E16_MASK, + PseudoVFRSQRT7_V_M1_E32, + PseudoVFRSQRT7_V_M1_E32_MASK, + PseudoVFRSQRT7_V_M1_E64, + PseudoVFRSQRT7_V_M1_E64_MASK, + PseudoVFRSQRT7_V_M2_E16, + PseudoVFRSQRT7_V_M2_E16_MASK, + PseudoVFRSQRT7_V_M2_E32, + PseudoVFRSQRT7_V_M2_E32_MASK, + PseudoVFRSQRT7_V_M2_E64, + PseudoVFRSQRT7_V_M2_E64_MASK, + PseudoVFRSQRT7_V_M4_E16, + PseudoVFRSQRT7_V_M4_E16_MASK, + PseudoVFRSQRT7_V_M4_E32, + PseudoVFRSQRT7_V_M4_E32_MASK, + PseudoVFRSQRT7_V_M4_E64, + PseudoVFRSQRT7_V_M4_E64_MASK, + PseudoVFRSQRT7_V_M8_E16, + PseudoVFRSQRT7_V_M8_E16_MASK, + PseudoVFRSQRT7_V_M8_E32, + PseudoVFRSQRT7_V_M8_E32_MASK, + PseudoVFRSQRT7_V_M8_E64, + PseudoVFRSQRT7_V_M8_E64_MASK, + PseudoVFRSQRT7_V_MF2_E16, + PseudoVFRSQRT7_V_MF2_E16_MASK, + PseudoVFRSQRT7_V_MF2_E32, + PseudoVFRSQRT7_V_MF2_E32_MASK, + PseudoVFRSQRT7_V_MF4_E16, + PseudoVFRSQRT7_V_MF4_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_M1_E16, + PseudoVFRSUB_ALT_VFPR16_M1_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_M2_E16, + PseudoVFRSUB_ALT_VFPR16_M2_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_M4_E16, + PseudoVFRSUB_ALT_VFPR16_M4_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_M8_E16, + PseudoVFRSUB_ALT_VFPR16_M8_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_MF2_E16, + PseudoVFRSUB_ALT_VFPR16_MF2_E16_MASK, + PseudoVFRSUB_ALT_VFPR16_MF4_E16, + PseudoVFRSUB_ALT_VFPR16_MF4_E16_MASK, + PseudoVFRSUB_VFPR16_M1_E16, + PseudoVFRSUB_VFPR16_M1_E16_MASK, + PseudoVFRSUB_VFPR16_M2_E16, + PseudoVFRSUB_VFPR16_M2_E16_MASK, + PseudoVFRSUB_VFPR16_M4_E16, + PseudoVFRSUB_VFPR16_M4_E16_MASK, + PseudoVFRSUB_VFPR16_M8_E16, + PseudoVFRSUB_VFPR16_M8_E16_MASK, + PseudoVFRSUB_VFPR16_MF2_E16, + PseudoVFRSUB_VFPR16_MF2_E16_MASK, + PseudoVFRSUB_VFPR16_MF4_E16, + PseudoVFRSUB_VFPR16_MF4_E16_MASK, + PseudoVFRSUB_VFPR32_M1_E32, + PseudoVFRSUB_VFPR32_M1_E32_MASK, + PseudoVFRSUB_VFPR32_M2_E32, + PseudoVFRSUB_VFPR32_M2_E32_MASK, + PseudoVFRSUB_VFPR32_M4_E32, + PseudoVFRSUB_VFPR32_M4_E32_MASK, + PseudoVFRSUB_VFPR32_M8_E32, + PseudoVFRSUB_VFPR32_M8_E32_MASK, + PseudoVFRSUB_VFPR32_MF2_E32, + PseudoVFRSUB_VFPR32_MF2_E32_MASK, + PseudoVFRSUB_VFPR64_M1_E64, + PseudoVFRSUB_VFPR64_M1_E64_MASK, + PseudoVFRSUB_VFPR64_M2_E64, + PseudoVFRSUB_VFPR64_M2_E64_MASK, + PseudoVFRSUB_VFPR64_M4_E64, + PseudoVFRSUB_VFPR64_M4_E64_MASK, + PseudoVFRSUB_VFPR64_M8_E64, + PseudoVFRSUB_VFPR64_M8_E64_MASK, + PseudoVFSGNJN_ALT_VFPR16_M1_E16, + PseudoVFSGNJN_ALT_VFPR16_M1_E16_MASK, + PseudoVFSGNJN_ALT_VFPR16_M2_E16, + PseudoVFSGNJN_ALT_VFPR16_M2_E16_MASK, + PseudoVFSGNJN_ALT_VFPR16_M4_E16, + PseudoVFSGNJN_ALT_VFPR16_M4_E16_MASK, + PseudoVFSGNJN_ALT_VFPR16_M8_E16, + PseudoVFSGNJN_ALT_VFPR16_M8_E16_MASK, + PseudoVFSGNJN_ALT_VFPR16_MF2_E16, + PseudoVFSGNJN_ALT_VFPR16_MF2_E16_MASK, + PseudoVFSGNJN_ALT_VFPR16_MF4_E16, + PseudoVFSGNJN_ALT_VFPR16_MF4_E16_MASK, + PseudoVFSGNJN_ALT_VV_M1_E16, + PseudoVFSGNJN_ALT_VV_M1_E16_MASK, + PseudoVFSGNJN_ALT_VV_M2_E16, + PseudoVFSGNJN_ALT_VV_M2_E16_MASK, + PseudoVFSGNJN_ALT_VV_M4_E16, + PseudoVFSGNJN_ALT_VV_M4_E16_MASK, + PseudoVFSGNJN_ALT_VV_M8_E16, + PseudoVFSGNJN_ALT_VV_M8_E16_MASK, + PseudoVFSGNJN_ALT_VV_MF2_E16, + PseudoVFSGNJN_ALT_VV_MF2_E16_MASK, + PseudoVFSGNJN_ALT_VV_MF4_E16, + PseudoVFSGNJN_ALT_VV_MF4_E16_MASK, + PseudoVFSGNJN_VFPR16_M1_E16, + PseudoVFSGNJN_VFPR16_M1_E16_MASK, + PseudoVFSGNJN_VFPR16_M2_E16, + PseudoVFSGNJN_VFPR16_M2_E16_MASK, + PseudoVFSGNJN_VFPR16_M4_E16, + PseudoVFSGNJN_VFPR16_M4_E16_MASK, + PseudoVFSGNJN_VFPR16_M8_E16, + PseudoVFSGNJN_VFPR16_M8_E16_MASK, + PseudoVFSGNJN_VFPR16_MF2_E16, + PseudoVFSGNJN_VFPR16_MF2_E16_MASK, + PseudoVFSGNJN_VFPR16_MF4_E16, + PseudoVFSGNJN_VFPR16_MF4_E16_MASK, + PseudoVFSGNJN_VFPR32_M1_E32, + PseudoVFSGNJN_VFPR32_M1_E32_MASK, + PseudoVFSGNJN_VFPR32_M2_E32, + PseudoVFSGNJN_VFPR32_M2_E32_MASK, + PseudoVFSGNJN_VFPR32_M4_E32, + PseudoVFSGNJN_VFPR32_M4_E32_MASK, + PseudoVFSGNJN_VFPR32_M8_E32, + PseudoVFSGNJN_VFPR32_M8_E32_MASK, + PseudoVFSGNJN_VFPR32_MF2_E32, + PseudoVFSGNJN_VFPR32_MF2_E32_MASK, + PseudoVFSGNJN_VFPR64_M1_E64, + PseudoVFSGNJN_VFPR64_M1_E64_MASK, + PseudoVFSGNJN_VFPR64_M2_E64, + PseudoVFSGNJN_VFPR64_M2_E64_MASK, + PseudoVFSGNJN_VFPR64_M4_E64, + PseudoVFSGNJN_VFPR64_M4_E64_MASK, + PseudoVFSGNJN_VFPR64_M8_E64, + PseudoVFSGNJN_VFPR64_M8_E64_MASK, + PseudoVFSGNJN_VV_M1_E16, + PseudoVFSGNJN_VV_M1_E16_MASK, + PseudoVFSGNJN_VV_M1_E32, + PseudoVFSGNJN_VV_M1_E32_MASK, + PseudoVFSGNJN_VV_M1_E64, + PseudoVFSGNJN_VV_M1_E64_MASK, + PseudoVFSGNJN_VV_M2_E16, + PseudoVFSGNJN_VV_M2_E16_MASK, + PseudoVFSGNJN_VV_M2_E32, + PseudoVFSGNJN_VV_M2_E32_MASK, + PseudoVFSGNJN_VV_M2_E64, + PseudoVFSGNJN_VV_M2_E64_MASK, + PseudoVFSGNJN_VV_M4_E16, + PseudoVFSGNJN_VV_M4_E16_MASK, + PseudoVFSGNJN_VV_M4_E32, + PseudoVFSGNJN_VV_M4_E32_MASK, + PseudoVFSGNJN_VV_M4_E64, + PseudoVFSGNJN_VV_M4_E64_MASK, + PseudoVFSGNJN_VV_M8_E16, + PseudoVFSGNJN_VV_M8_E16_MASK, + PseudoVFSGNJN_VV_M8_E32, + PseudoVFSGNJN_VV_M8_E32_MASK, + PseudoVFSGNJN_VV_M8_E64, + PseudoVFSGNJN_VV_M8_E64_MASK, + PseudoVFSGNJN_VV_MF2_E16, + PseudoVFSGNJN_VV_MF2_E16_MASK, + PseudoVFSGNJN_VV_MF2_E32, + PseudoVFSGNJN_VV_MF2_E32_MASK, + PseudoVFSGNJN_VV_MF4_E16, + PseudoVFSGNJN_VV_MF4_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_M1_E16, + PseudoVFSGNJX_ALT_VFPR16_M1_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_M2_E16, + PseudoVFSGNJX_ALT_VFPR16_M2_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_M4_E16, + PseudoVFSGNJX_ALT_VFPR16_M4_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_M8_E16, + PseudoVFSGNJX_ALT_VFPR16_M8_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_MF2_E16, + PseudoVFSGNJX_ALT_VFPR16_MF2_E16_MASK, + PseudoVFSGNJX_ALT_VFPR16_MF4_E16, + PseudoVFSGNJX_ALT_VFPR16_MF4_E16_MASK, + PseudoVFSGNJX_ALT_VV_M1_E16, + PseudoVFSGNJX_ALT_VV_M1_E16_MASK, + PseudoVFSGNJX_ALT_VV_M2_E16, + PseudoVFSGNJX_ALT_VV_M2_E16_MASK, + PseudoVFSGNJX_ALT_VV_M4_E16, + PseudoVFSGNJX_ALT_VV_M4_E16_MASK, + PseudoVFSGNJX_ALT_VV_M8_E16, + PseudoVFSGNJX_ALT_VV_M8_E16_MASK, + PseudoVFSGNJX_ALT_VV_MF2_E16, + PseudoVFSGNJX_ALT_VV_MF2_E16_MASK, + PseudoVFSGNJX_ALT_VV_MF4_E16, + PseudoVFSGNJX_ALT_VV_MF4_E16_MASK, + PseudoVFSGNJX_VFPR16_M1_E16, + PseudoVFSGNJX_VFPR16_M1_E16_MASK, + PseudoVFSGNJX_VFPR16_M2_E16, + PseudoVFSGNJX_VFPR16_M2_E16_MASK, + PseudoVFSGNJX_VFPR16_M4_E16, + PseudoVFSGNJX_VFPR16_M4_E16_MASK, + PseudoVFSGNJX_VFPR16_M8_E16, + PseudoVFSGNJX_VFPR16_M8_E16_MASK, + PseudoVFSGNJX_VFPR16_MF2_E16, + PseudoVFSGNJX_VFPR16_MF2_E16_MASK, + PseudoVFSGNJX_VFPR16_MF4_E16, + PseudoVFSGNJX_VFPR16_MF4_E16_MASK, + PseudoVFSGNJX_VFPR32_M1_E32, + PseudoVFSGNJX_VFPR32_M1_E32_MASK, + PseudoVFSGNJX_VFPR32_M2_E32, + PseudoVFSGNJX_VFPR32_M2_E32_MASK, + PseudoVFSGNJX_VFPR32_M4_E32, + PseudoVFSGNJX_VFPR32_M4_E32_MASK, + PseudoVFSGNJX_VFPR32_M8_E32, + PseudoVFSGNJX_VFPR32_M8_E32_MASK, + PseudoVFSGNJX_VFPR32_MF2_E32, + PseudoVFSGNJX_VFPR32_MF2_E32_MASK, + PseudoVFSGNJX_VFPR64_M1_E64, + PseudoVFSGNJX_VFPR64_M1_E64_MASK, + PseudoVFSGNJX_VFPR64_M2_E64, + PseudoVFSGNJX_VFPR64_M2_E64_MASK, + PseudoVFSGNJX_VFPR64_M4_E64, + PseudoVFSGNJX_VFPR64_M4_E64_MASK, + PseudoVFSGNJX_VFPR64_M8_E64, + PseudoVFSGNJX_VFPR64_M8_E64_MASK, + PseudoVFSGNJX_VV_M1_E16, + PseudoVFSGNJX_VV_M1_E16_MASK, + PseudoVFSGNJX_VV_M1_E32, + PseudoVFSGNJX_VV_M1_E32_MASK, + PseudoVFSGNJX_VV_M1_E64, + PseudoVFSGNJX_VV_M1_E64_MASK, + PseudoVFSGNJX_VV_M2_E16, + PseudoVFSGNJX_VV_M2_E16_MASK, + PseudoVFSGNJX_VV_M2_E32, + PseudoVFSGNJX_VV_M2_E32_MASK, + PseudoVFSGNJX_VV_M2_E64, + PseudoVFSGNJX_VV_M2_E64_MASK, + PseudoVFSGNJX_VV_M4_E16, + PseudoVFSGNJX_VV_M4_E16_MASK, + PseudoVFSGNJX_VV_M4_E32, + PseudoVFSGNJX_VV_M4_E32_MASK, + PseudoVFSGNJX_VV_M4_E64, + PseudoVFSGNJX_VV_M4_E64_MASK, + PseudoVFSGNJX_VV_M8_E16, + PseudoVFSGNJX_VV_M8_E16_MASK, + PseudoVFSGNJX_VV_M8_E32, + PseudoVFSGNJX_VV_M8_E32_MASK, + PseudoVFSGNJX_VV_M8_E64, + PseudoVFSGNJX_VV_M8_E64_MASK, + PseudoVFSGNJX_VV_MF2_E16, + PseudoVFSGNJX_VV_MF2_E16_MASK, + PseudoVFSGNJX_VV_MF2_E32, + PseudoVFSGNJX_VV_MF2_E32_MASK, + PseudoVFSGNJX_VV_MF4_E16, + PseudoVFSGNJX_VV_MF4_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_M1_E16, + PseudoVFSGNJ_ALT_VFPR16_M1_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_M2_E16, + PseudoVFSGNJ_ALT_VFPR16_M2_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_M4_E16, + PseudoVFSGNJ_ALT_VFPR16_M4_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_M8_E16, + PseudoVFSGNJ_ALT_VFPR16_M8_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_MF2_E16, + PseudoVFSGNJ_ALT_VFPR16_MF2_E16_MASK, + PseudoVFSGNJ_ALT_VFPR16_MF4_E16, + PseudoVFSGNJ_ALT_VFPR16_MF4_E16_MASK, + PseudoVFSGNJ_ALT_VV_M1_E16, + PseudoVFSGNJ_ALT_VV_M1_E16_MASK, + PseudoVFSGNJ_ALT_VV_M2_E16, + PseudoVFSGNJ_ALT_VV_M2_E16_MASK, + PseudoVFSGNJ_ALT_VV_M4_E16, + PseudoVFSGNJ_ALT_VV_M4_E16_MASK, + PseudoVFSGNJ_ALT_VV_M8_E16, + PseudoVFSGNJ_ALT_VV_M8_E16_MASK, + PseudoVFSGNJ_ALT_VV_MF2_E16, + PseudoVFSGNJ_ALT_VV_MF2_E16_MASK, + PseudoVFSGNJ_ALT_VV_MF4_E16, + PseudoVFSGNJ_ALT_VV_MF4_E16_MASK, + PseudoVFSGNJ_VFPR16_M1_E16, + PseudoVFSGNJ_VFPR16_M1_E16_MASK, + PseudoVFSGNJ_VFPR16_M2_E16, + PseudoVFSGNJ_VFPR16_M2_E16_MASK, + PseudoVFSGNJ_VFPR16_M4_E16, + PseudoVFSGNJ_VFPR16_M4_E16_MASK, + PseudoVFSGNJ_VFPR16_M8_E16, + PseudoVFSGNJ_VFPR16_M8_E16_MASK, + PseudoVFSGNJ_VFPR16_MF2_E16, + PseudoVFSGNJ_VFPR16_MF2_E16_MASK, + PseudoVFSGNJ_VFPR16_MF4_E16, + PseudoVFSGNJ_VFPR16_MF4_E16_MASK, + PseudoVFSGNJ_VFPR32_M1_E32, + PseudoVFSGNJ_VFPR32_M1_E32_MASK, + PseudoVFSGNJ_VFPR32_M2_E32, + PseudoVFSGNJ_VFPR32_M2_E32_MASK, + PseudoVFSGNJ_VFPR32_M4_E32, + PseudoVFSGNJ_VFPR32_M4_E32_MASK, + PseudoVFSGNJ_VFPR32_M8_E32, + PseudoVFSGNJ_VFPR32_M8_E32_MASK, + PseudoVFSGNJ_VFPR32_MF2_E32, + PseudoVFSGNJ_VFPR32_MF2_E32_MASK, + PseudoVFSGNJ_VFPR64_M1_E64, + PseudoVFSGNJ_VFPR64_M1_E64_MASK, + PseudoVFSGNJ_VFPR64_M2_E64, + PseudoVFSGNJ_VFPR64_M2_E64_MASK, + PseudoVFSGNJ_VFPR64_M4_E64, + PseudoVFSGNJ_VFPR64_M4_E64_MASK, + PseudoVFSGNJ_VFPR64_M8_E64, + PseudoVFSGNJ_VFPR64_M8_E64_MASK, + PseudoVFSGNJ_VV_M1_E16, + PseudoVFSGNJ_VV_M1_E16_MASK, + PseudoVFSGNJ_VV_M1_E32, + PseudoVFSGNJ_VV_M1_E32_MASK, + PseudoVFSGNJ_VV_M1_E64, + PseudoVFSGNJ_VV_M1_E64_MASK, + PseudoVFSGNJ_VV_M2_E16, + PseudoVFSGNJ_VV_M2_E16_MASK, + PseudoVFSGNJ_VV_M2_E32, + PseudoVFSGNJ_VV_M2_E32_MASK, + PseudoVFSGNJ_VV_M2_E64, + PseudoVFSGNJ_VV_M2_E64_MASK, + PseudoVFSGNJ_VV_M4_E16, + PseudoVFSGNJ_VV_M4_E16_MASK, + PseudoVFSGNJ_VV_M4_E32, + PseudoVFSGNJ_VV_M4_E32_MASK, + PseudoVFSGNJ_VV_M4_E64, + PseudoVFSGNJ_VV_M4_E64_MASK, + PseudoVFSGNJ_VV_M8_E16, + PseudoVFSGNJ_VV_M8_E16_MASK, + PseudoVFSGNJ_VV_M8_E32, + PseudoVFSGNJ_VV_M8_E32_MASK, + PseudoVFSGNJ_VV_M8_E64, + PseudoVFSGNJ_VV_M8_E64_MASK, + PseudoVFSGNJ_VV_MF2_E16, + PseudoVFSGNJ_VV_MF2_E16_MASK, + PseudoVFSGNJ_VV_MF2_E32, + PseudoVFSGNJ_VV_MF2_E32_MASK, + PseudoVFSGNJ_VV_MF4_E16, + PseudoVFSGNJ_VV_MF4_E16_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M1, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M1_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M2, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M2_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M4, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M4_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M8, + PseudoVFSLIDE1DOWN_ALT_VFPR16_M8_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2, + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4, + PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M1, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M1_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M2, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M2_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M4, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M4_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M8, + PseudoVFSLIDE1DOWN_ALT_VFPR32_M8_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2, + PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M1, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M1_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M2, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M2_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M4, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M4_MASK, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M8, + PseudoVFSLIDE1DOWN_ALT_VFPR64_M8_MASK, + PseudoVFSLIDE1DOWN_VFPR16_M1, + PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, + PseudoVFSLIDE1DOWN_VFPR16_M2, + PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, + PseudoVFSLIDE1DOWN_VFPR16_M4, + PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, + PseudoVFSLIDE1DOWN_VFPR16_M8, + PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, + PseudoVFSLIDE1DOWN_VFPR16_MF2, + PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, + PseudoVFSLIDE1DOWN_VFPR16_MF4, + PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, + PseudoVFSLIDE1DOWN_VFPR32_M1, + PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, + PseudoVFSLIDE1DOWN_VFPR32_M2, + PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, + PseudoVFSLIDE1DOWN_VFPR32_M4, + PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, + PseudoVFSLIDE1DOWN_VFPR32_M8, + PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, + PseudoVFSLIDE1DOWN_VFPR32_MF2, + PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, + PseudoVFSLIDE1DOWN_VFPR64_M1, + PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, + PseudoVFSLIDE1DOWN_VFPR64_M2, + PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, + PseudoVFSLIDE1DOWN_VFPR64_M4, + PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, + PseudoVFSLIDE1DOWN_VFPR64_M8, + PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_M1, + PseudoVFSLIDE1UP_ALT_VFPR16_M1_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_M2, + PseudoVFSLIDE1UP_ALT_VFPR16_M2_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_M4, + PseudoVFSLIDE1UP_ALT_VFPR16_M4_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_M8, + PseudoVFSLIDE1UP_ALT_VFPR16_M8_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_MF2, + PseudoVFSLIDE1UP_ALT_VFPR16_MF2_MASK, + PseudoVFSLIDE1UP_ALT_VFPR16_MF4, + PseudoVFSLIDE1UP_ALT_VFPR16_MF4_MASK, + PseudoVFSLIDE1UP_ALT_VFPR32_M1, + PseudoVFSLIDE1UP_ALT_VFPR32_M1_MASK, + PseudoVFSLIDE1UP_ALT_VFPR32_M2, + PseudoVFSLIDE1UP_ALT_VFPR32_M2_MASK, + PseudoVFSLIDE1UP_ALT_VFPR32_M4, + PseudoVFSLIDE1UP_ALT_VFPR32_M4_MASK, + PseudoVFSLIDE1UP_ALT_VFPR32_M8, + PseudoVFSLIDE1UP_ALT_VFPR32_M8_MASK, + PseudoVFSLIDE1UP_ALT_VFPR32_MF2, + PseudoVFSLIDE1UP_ALT_VFPR32_MF2_MASK, + PseudoVFSLIDE1UP_ALT_VFPR64_M1, + PseudoVFSLIDE1UP_ALT_VFPR64_M1_MASK, + PseudoVFSLIDE1UP_ALT_VFPR64_M2, + PseudoVFSLIDE1UP_ALT_VFPR64_M2_MASK, + PseudoVFSLIDE1UP_ALT_VFPR64_M4, + PseudoVFSLIDE1UP_ALT_VFPR64_M4_MASK, + PseudoVFSLIDE1UP_ALT_VFPR64_M8, + PseudoVFSLIDE1UP_ALT_VFPR64_M8_MASK, + PseudoVFSLIDE1UP_VFPR16_M1, + PseudoVFSLIDE1UP_VFPR16_M1_MASK, + PseudoVFSLIDE1UP_VFPR16_M2, + PseudoVFSLIDE1UP_VFPR16_M2_MASK, + PseudoVFSLIDE1UP_VFPR16_M4, + PseudoVFSLIDE1UP_VFPR16_M4_MASK, + PseudoVFSLIDE1UP_VFPR16_M8, + PseudoVFSLIDE1UP_VFPR16_M8_MASK, + PseudoVFSLIDE1UP_VFPR16_MF2, + PseudoVFSLIDE1UP_VFPR16_MF2_MASK, + PseudoVFSLIDE1UP_VFPR16_MF4, + PseudoVFSLIDE1UP_VFPR16_MF4_MASK, + PseudoVFSLIDE1UP_VFPR32_M1, + PseudoVFSLIDE1UP_VFPR32_M1_MASK, + PseudoVFSLIDE1UP_VFPR32_M2, + PseudoVFSLIDE1UP_VFPR32_M2_MASK, + PseudoVFSLIDE1UP_VFPR32_M4, + PseudoVFSLIDE1UP_VFPR32_M4_MASK, + PseudoVFSLIDE1UP_VFPR32_M8, + PseudoVFSLIDE1UP_VFPR32_M8_MASK, + PseudoVFSLIDE1UP_VFPR32_MF2, + PseudoVFSLIDE1UP_VFPR32_MF2_MASK, + PseudoVFSLIDE1UP_VFPR64_M1, + PseudoVFSLIDE1UP_VFPR64_M1_MASK, + PseudoVFSLIDE1UP_VFPR64_M2, + PseudoVFSLIDE1UP_VFPR64_M2_MASK, + PseudoVFSLIDE1UP_VFPR64_M4, + PseudoVFSLIDE1UP_VFPR64_M4_MASK, + PseudoVFSLIDE1UP_VFPR64_M8, + PseudoVFSLIDE1UP_VFPR64_M8_MASK, + PseudoVFSQRT_V_M1_E16, + PseudoVFSQRT_V_M1_E16_MASK, + PseudoVFSQRT_V_M1_E32, + PseudoVFSQRT_V_M1_E32_MASK, + PseudoVFSQRT_V_M1_E64, + PseudoVFSQRT_V_M1_E64_MASK, + PseudoVFSQRT_V_M2_E16, + PseudoVFSQRT_V_M2_E16_MASK, + PseudoVFSQRT_V_M2_E32, + PseudoVFSQRT_V_M2_E32_MASK, + PseudoVFSQRT_V_M2_E64, + PseudoVFSQRT_V_M2_E64_MASK, + PseudoVFSQRT_V_M4_E16, + PseudoVFSQRT_V_M4_E16_MASK, + PseudoVFSQRT_V_M4_E32, + PseudoVFSQRT_V_M4_E32_MASK, + PseudoVFSQRT_V_M4_E64, + PseudoVFSQRT_V_M4_E64_MASK, + PseudoVFSQRT_V_M8_E16, + PseudoVFSQRT_V_M8_E16_MASK, + PseudoVFSQRT_V_M8_E32, + PseudoVFSQRT_V_M8_E32_MASK, + PseudoVFSQRT_V_M8_E64, + PseudoVFSQRT_V_M8_E64_MASK, + PseudoVFSQRT_V_MF2_E16, + PseudoVFSQRT_V_MF2_E16_MASK, + PseudoVFSQRT_V_MF2_E32, + PseudoVFSQRT_V_MF2_E32_MASK, + PseudoVFSQRT_V_MF4_E16, + PseudoVFSQRT_V_MF4_E16_MASK, + PseudoVFSUB_ALT_VFPR16_M1_E16, + PseudoVFSUB_ALT_VFPR16_M1_E16_MASK, + PseudoVFSUB_ALT_VFPR16_M2_E16, + PseudoVFSUB_ALT_VFPR16_M2_E16_MASK, + PseudoVFSUB_ALT_VFPR16_M4_E16, + PseudoVFSUB_ALT_VFPR16_M4_E16_MASK, + PseudoVFSUB_ALT_VFPR16_M8_E16, + PseudoVFSUB_ALT_VFPR16_M8_E16_MASK, + PseudoVFSUB_ALT_VFPR16_MF2_E16, + PseudoVFSUB_ALT_VFPR16_MF2_E16_MASK, + PseudoVFSUB_ALT_VFPR16_MF4_E16, + PseudoVFSUB_ALT_VFPR16_MF4_E16_MASK, + PseudoVFSUB_ALT_VV_M1_E16, + PseudoVFSUB_ALT_VV_M1_E16_MASK, + PseudoVFSUB_ALT_VV_M2_E16, + PseudoVFSUB_ALT_VV_M2_E16_MASK, + PseudoVFSUB_ALT_VV_M4_E16, + PseudoVFSUB_ALT_VV_M4_E16_MASK, + PseudoVFSUB_ALT_VV_M8_E16, + PseudoVFSUB_ALT_VV_M8_E16_MASK, + PseudoVFSUB_ALT_VV_MF2_E16, + PseudoVFSUB_ALT_VV_MF2_E16_MASK, + PseudoVFSUB_ALT_VV_MF4_E16, + PseudoVFSUB_ALT_VV_MF4_E16_MASK, + PseudoVFSUB_VFPR16_M1_E16, + PseudoVFSUB_VFPR16_M1_E16_MASK, + PseudoVFSUB_VFPR16_M2_E16, + PseudoVFSUB_VFPR16_M2_E16_MASK, + PseudoVFSUB_VFPR16_M4_E16, + PseudoVFSUB_VFPR16_M4_E16_MASK, + PseudoVFSUB_VFPR16_M8_E16, + PseudoVFSUB_VFPR16_M8_E16_MASK, + PseudoVFSUB_VFPR16_MF2_E16, + PseudoVFSUB_VFPR16_MF2_E16_MASK, + PseudoVFSUB_VFPR16_MF4_E16, + PseudoVFSUB_VFPR16_MF4_E16_MASK, + PseudoVFSUB_VFPR32_M1_E32, + PseudoVFSUB_VFPR32_M1_E32_MASK, + PseudoVFSUB_VFPR32_M2_E32, + PseudoVFSUB_VFPR32_M2_E32_MASK, + PseudoVFSUB_VFPR32_M4_E32, + PseudoVFSUB_VFPR32_M4_E32_MASK, + PseudoVFSUB_VFPR32_M8_E32, + PseudoVFSUB_VFPR32_M8_E32_MASK, + PseudoVFSUB_VFPR32_MF2_E32, + PseudoVFSUB_VFPR32_MF2_E32_MASK, + PseudoVFSUB_VFPR64_M1_E64, + PseudoVFSUB_VFPR64_M1_E64_MASK, + PseudoVFSUB_VFPR64_M2_E64, + PseudoVFSUB_VFPR64_M2_E64_MASK, + PseudoVFSUB_VFPR64_M4_E64, + PseudoVFSUB_VFPR64_M4_E64_MASK, + PseudoVFSUB_VFPR64_M8_E64, + PseudoVFSUB_VFPR64_M8_E64_MASK, + PseudoVFSUB_VV_M1_E16, + PseudoVFSUB_VV_M1_E16_MASK, + PseudoVFSUB_VV_M1_E32, + PseudoVFSUB_VV_M1_E32_MASK, + PseudoVFSUB_VV_M1_E64, + PseudoVFSUB_VV_M1_E64_MASK, + PseudoVFSUB_VV_M2_E16, + PseudoVFSUB_VV_M2_E16_MASK, + PseudoVFSUB_VV_M2_E32, + PseudoVFSUB_VV_M2_E32_MASK, + PseudoVFSUB_VV_M2_E64, + PseudoVFSUB_VV_M2_E64_MASK, + PseudoVFSUB_VV_M4_E16, + PseudoVFSUB_VV_M4_E16_MASK, + PseudoVFSUB_VV_M4_E32, + PseudoVFSUB_VV_M4_E32_MASK, + PseudoVFSUB_VV_M4_E64, + PseudoVFSUB_VV_M4_E64_MASK, + PseudoVFSUB_VV_M8_E16, + PseudoVFSUB_VV_M8_E16_MASK, + PseudoVFSUB_VV_M8_E32, + PseudoVFSUB_VV_M8_E32_MASK, + PseudoVFSUB_VV_M8_E64, + PseudoVFSUB_VV_M8_E64_MASK, + PseudoVFSUB_VV_MF2_E16, + PseudoVFSUB_VV_MF2_E16_MASK, + PseudoVFSUB_VV_MF2_E32, + PseudoVFSUB_VV_MF2_E32_MASK, + PseudoVFSUB_VV_MF4_E16, + PseudoVFSUB_VV_MF4_E16_MASK, + PseudoVFWADD_ALT_VFPR16_M1_E16, + PseudoVFWADD_ALT_VFPR16_M1_E16_MASK, + PseudoVFWADD_ALT_VFPR16_M2_E16, + PseudoVFWADD_ALT_VFPR16_M2_E16_MASK, + PseudoVFWADD_ALT_VFPR16_M4_E16, + PseudoVFWADD_ALT_VFPR16_M4_E16_MASK, + PseudoVFWADD_ALT_VFPR16_MF2_E16, + PseudoVFWADD_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWADD_ALT_VFPR16_MF4_E16, + PseudoVFWADD_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWADD_ALT_VV_M1_E16, + PseudoVFWADD_ALT_VV_M1_E16_MASK, + PseudoVFWADD_ALT_VV_M2_E16, + PseudoVFWADD_ALT_VV_M2_E16_MASK, + PseudoVFWADD_ALT_VV_M4_E16, + PseudoVFWADD_ALT_VV_M4_E16_MASK, + PseudoVFWADD_ALT_VV_MF2_E16, + PseudoVFWADD_ALT_VV_MF2_E16_MASK, + PseudoVFWADD_ALT_VV_MF4_E16, + PseudoVFWADD_ALT_VV_MF4_E16_MASK, + PseudoVFWADD_ALT_WFPR16_M1_E16, + PseudoVFWADD_ALT_WFPR16_M1_E16_MASK, + PseudoVFWADD_ALT_WFPR16_M2_E16, + PseudoVFWADD_ALT_WFPR16_M2_E16_MASK, + PseudoVFWADD_ALT_WFPR16_M4_E16, + PseudoVFWADD_ALT_WFPR16_M4_E16_MASK, + PseudoVFWADD_ALT_WFPR16_MF2_E16, + PseudoVFWADD_ALT_WFPR16_MF2_E16_MASK, + PseudoVFWADD_ALT_WFPR16_MF4_E16, + PseudoVFWADD_ALT_WFPR16_MF4_E16_MASK, + PseudoVFWADD_ALT_WV_M1_E16, + PseudoVFWADD_ALT_WV_M1_E16_MASK, + PseudoVFWADD_ALT_WV_M1_E16_MASK_TIED, + PseudoVFWADD_ALT_WV_M1_E16_TIED, + PseudoVFWADD_ALT_WV_M2_E16, + PseudoVFWADD_ALT_WV_M2_E16_MASK, + PseudoVFWADD_ALT_WV_M2_E16_MASK_TIED, + PseudoVFWADD_ALT_WV_M2_E16_TIED, + PseudoVFWADD_ALT_WV_M4_E16, + PseudoVFWADD_ALT_WV_M4_E16_MASK, + PseudoVFWADD_ALT_WV_M4_E16_MASK_TIED, + PseudoVFWADD_ALT_WV_M4_E16_TIED, + PseudoVFWADD_ALT_WV_MF2_E16, + PseudoVFWADD_ALT_WV_MF2_E16_MASK, + PseudoVFWADD_ALT_WV_MF2_E16_MASK_TIED, + PseudoVFWADD_ALT_WV_MF2_E16_TIED, + PseudoVFWADD_ALT_WV_MF4_E16, + PseudoVFWADD_ALT_WV_MF4_E16_MASK, + PseudoVFWADD_ALT_WV_MF4_E16_MASK_TIED, + PseudoVFWADD_ALT_WV_MF4_E16_TIED, + PseudoVFWADD_VFPR16_M1_E16, + PseudoVFWADD_VFPR16_M1_E16_MASK, + PseudoVFWADD_VFPR16_M2_E16, + PseudoVFWADD_VFPR16_M2_E16_MASK, + PseudoVFWADD_VFPR16_M4_E16, + PseudoVFWADD_VFPR16_M4_E16_MASK, + PseudoVFWADD_VFPR16_MF2_E16, + PseudoVFWADD_VFPR16_MF2_E16_MASK, + PseudoVFWADD_VFPR16_MF4_E16, + PseudoVFWADD_VFPR16_MF4_E16_MASK, + PseudoVFWADD_VFPR32_M1_E32, + PseudoVFWADD_VFPR32_M1_E32_MASK, + PseudoVFWADD_VFPR32_M2_E32, + PseudoVFWADD_VFPR32_M2_E32_MASK, + PseudoVFWADD_VFPR32_M4_E32, + PseudoVFWADD_VFPR32_M4_E32_MASK, + PseudoVFWADD_VFPR32_MF2_E32, + PseudoVFWADD_VFPR32_MF2_E32_MASK, + PseudoVFWADD_VV_M1_E16, + PseudoVFWADD_VV_M1_E16_MASK, + PseudoVFWADD_VV_M1_E32, + PseudoVFWADD_VV_M1_E32_MASK, + PseudoVFWADD_VV_M2_E16, + PseudoVFWADD_VV_M2_E16_MASK, + PseudoVFWADD_VV_M2_E32, + PseudoVFWADD_VV_M2_E32_MASK, + PseudoVFWADD_VV_M4_E16, + PseudoVFWADD_VV_M4_E16_MASK, + PseudoVFWADD_VV_M4_E32, + PseudoVFWADD_VV_M4_E32_MASK, + PseudoVFWADD_VV_MF2_E16, + PseudoVFWADD_VV_MF2_E16_MASK, + PseudoVFWADD_VV_MF2_E32, + PseudoVFWADD_VV_MF2_E32_MASK, + PseudoVFWADD_VV_MF4_E16, + PseudoVFWADD_VV_MF4_E16_MASK, + PseudoVFWADD_WFPR16_M1_E16, + PseudoVFWADD_WFPR16_M1_E16_MASK, + PseudoVFWADD_WFPR16_M2_E16, + PseudoVFWADD_WFPR16_M2_E16_MASK, + PseudoVFWADD_WFPR16_M4_E16, + PseudoVFWADD_WFPR16_M4_E16_MASK, + PseudoVFWADD_WFPR16_MF2_E16, + PseudoVFWADD_WFPR16_MF2_E16_MASK, + PseudoVFWADD_WFPR16_MF4_E16, + PseudoVFWADD_WFPR16_MF4_E16_MASK, + PseudoVFWADD_WFPR32_M1_E32, + PseudoVFWADD_WFPR32_M1_E32_MASK, + PseudoVFWADD_WFPR32_M2_E32, + PseudoVFWADD_WFPR32_M2_E32_MASK, + PseudoVFWADD_WFPR32_M4_E32, + PseudoVFWADD_WFPR32_M4_E32_MASK, + PseudoVFWADD_WFPR32_MF2_E32, + PseudoVFWADD_WFPR32_MF2_E32_MASK, + PseudoVFWADD_WV_M1_E16, + PseudoVFWADD_WV_M1_E16_MASK, + PseudoVFWADD_WV_M1_E16_MASK_TIED, + PseudoVFWADD_WV_M1_E16_TIED, + PseudoVFWADD_WV_M1_E32, + PseudoVFWADD_WV_M1_E32_MASK, + PseudoVFWADD_WV_M1_E32_MASK_TIED, + PseudoVFWADD_WV_M1_E32_TIED, + PseudoVFWADD_WV_M2_E16, + PseudoVFWADD_WV_M2_E16_MASK, + PseudoVFWADD_WV_M2_E16_MASK_TIED, + PseudoVFWADD_WV_M2_E16_TIED, + PseudoVFWADD_WV_M2_E32, + PseudoVFWADD_WV_M2_E32_MASK, + PseudoVFWADD_WV_M2_E32_MASK_TIED, + PseudoVFWADD_WV_M2_E32_TIED, + PseudoVFWADD_WV_M4_E16, + PseudoVFWADD_WV_M4_E16_MASK, + PseudoVFWADD_WV_M4_E16_MASK_TIED, + PseudoVFWADD_WV_M4_E16_TIED, + PseudoVFWADD_WV_M4_E32, + PseudoVFWADD_WV_M4_E32_MASK, + PseudoVFWADD_WV_M4_E32_MASK_TIED, + PseudoVFWADD_WV_M4_E32_TIED, + PseudoVFWADD_WV_MF2_E16, + PseudoVFWADD_WV_MF2_E16_MASK, + PseudoVFWADD_WV_MF2_E16_MASK_TIED, + PseudoVFWADD_WV_MF2_E16_TIED, + PseudoVFWADD_WV_MF2_E32, + PseudoVFWADD_WV_MF2_E32_MASK, + PseudoVFWADD_WV_MF2_E32_MASK_TIED, + PseudoVFWADD_WV_MF2_E32_TIED, + PseudoVFWADD_WV_MF4_E16, + PseudoVFWADD_WV_MF4_E16_MASK, + PseudoVFWADD_WV_MF4_E16_MASK_TIED, + PseudoVFWADD_WV_MF4_E16_TIED, + PseudoVFWCVTBF16_F_F_ALT_V_M1_E8, + PseudoVFWCVTBF16_F_F_ALT_V_M1_E8_MASK, + PseudoVFWCVTBF16_F_F_ALT_V_M2_E8, + PseudoVFWCVTBF16_F_F_ALT_V_M2_E8_MASK, + PseudoVFWCVTBF16_F_F_ALT_V_M4_E8, + PseudoVFWCVTBF16_F_F_ALT_V_M4_E8_MASK, + PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8, + PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8_MASK, + PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8, + PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8_MASK, + PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8, + PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8_MASK, + PseudoVFWCVTBF16_F_F_V_M1_E16, + PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, + PseudoVFWCVTBF16_F_F_V_M1_E32, + PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, + PseudoVFWCVTBF16_F_F_V_M1_E8, + PseudoVFWCVTBF16_F_F_V_M1_E8_MASK, + PseudoVFWCVTBF16_F_F_V_M2_E16, + PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, + PseudoVFWCVTBF16_F_F_V_M2_E32, + PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, + PseudoVFWCVTBF16_F_F_V_M2_E8, + PseudoVFWCVTBF16_F_F_V_M2_E8_MASK, + PseudoVFWCVTBF16_F_F_V_M4_E16, + PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, + PseudoVFWCVTBF16_F_F_V_M4_E32, + PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, + PseudoVFWCVTBF16_F_F_V_M4_E8, + PseudoVFWCVTBF16_F_F_V_M4_E8_MASK, + PseudoVFWCVTBF16_F_F_V_MF2_E16, + PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, + PseudoVFWCVTBF16_F_F_V_MF2_E32, + PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, + PseudoVFWCVTBF16_F_F_V_MF2_E8, + PseudoVFWCVTBF16_F_F_V_MF2_E8_MASK, + PseudoVFWCVTBF16_F_F_V_MF4_E16, + PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, + PseudoVFWCVTBF16_F_F_V_MF4_E8, + PseudoVFWCVTBF16_F_F_V_MF4_E8_MASK, + PseudoVFWCVTBF16_F_F_V_MF8_E8, + PseudoVFWCVTBF16_F_F_V_MF8_E8_MASK, + PseudoVFWCVT_F_F_ALT_V_M1_E16, + PseudoVFWCVT_F_F_ALT_V_M1_E16_MASK, + PseudoVFWCVT_F_F_ALT_V_M2_E16, + PseudoVFWCVT_F_F_ALT_V_M2_E16_MASK, + PseudoVFWCVT_F_F_ALT_V_M4_E16, + PseudoVFWCVT_F_F_ALT_V_M4_E16_MASK, + PseudoVFWCVT_F_F_ALT_V_MF2_E16, + PseudoVFWCVT_F_F_ALT_V_MF2_E16_MASK, + PseudoVFWCVT_F_F_ALT_V_MF4_E16, + PseudoVFWCVT_F_F_ALT_V_MF4_E16_MASK, + PseudoVFWCVT_F_F_V_M1_E16, + PseudoVFWCVT_F_F_V_M1_E16_MASK, + PseudoVFWCVT_F_F_V_M1_E32, + PseudoVFWCVT_F_F_V_M1_E32_MASK, + PseudoVFWCVT_F_F_V_M2_E16, + PseudoVFWCVT_F_F_V_M2_E16_MASK, + PseudoVFWCVT_F_F_V_M2_E32, + PseudoVFWCVT_F_F_V_M2_E32_MASK, + PseudoVFWCVT_F_F_V_M4_E16, + PseudoVFWCVT_F_F_V_M4_E16_MASK, + PseudoVFWCVT_F_F_V_M4_E32, + PseudoVFWCVT_F_F_V_M4_E32_MASK, + PseudoVFWCVT_F_F_V_MF2_E16, + PseudoVFWCVT_F_F_V_MF2_E16_MASK, + PseudoVFWCVT_F_F_V_MF2_E32, + PseudoVFWCVT_F_F_V_MF2_E32_MASK, + PseudoVFWCVT_F_F_V_MF4_E16, + PseudoVFWCVT_F_F_V_MF4_E16_MASK, + PseudoVFWCVT_F_XU_ALT_V_M1_E8, + PseudoVFWCVT_F_XU_ALT_V_M1_E8_MASK, + PseudoVFWCVT_F_XU_ALT_V_M2_E8, + PseudoVFWCVT_F_XU_ALT_V_M2_E8_MASK, + PseudoVFWCVT_F_XU_ALT_V_M4_E8, + PseudoVFWCVT_F_XU_ALT_V_M4_E8_MASK, + PseudoVFWCVT_F_XU_ALT_V_MF2_E8, + PseudoVFWCVT_F_XU_ALT_V_MF2_E8_MASK, + PseudoVFWCVT_F_XU_ALT_V_MF4_E8, + PseudoVFWCVT_F_XU_ALT_V_MF4_E8_MASK, + PseudoVFWCVT_F_XU_ALT_V_MF8_E8, + PseudoVFWCVT_F_XU_ALT_V_MF8_E8_MASK, + PseudoVFWCVT_F_XU_V_M1_E16, + PseudoVFWCVT_F_XU_V_M1_E16_MASK, + PseudoVFWCVT_F_XU_V_M1_E32, + PseudoVFWCVT_F_XU_V_M1_E32_MASK, + PseudoVFWCVT_F_XU_V_M1_E8, + PseudoVFWCVT_F_XU_V_M1_E8_MASK, + PseudoVFWCVT_F_XU_V_M2_E16, + PseudoVFWCVT_F_XU_V_M2_E16_MASK, + PseudoVFWCVT_F_XU_V_M2_E32, + PseudoVFWCVT_F_XU_V_M2_E32_MASK, + PseudoVFWCVT_F_XU_V_M2_E8, + PseudoVFWCVT_F_XU_V_M2_E8_MASK, + PseudoVFWCVT_F_XU_V_M4_E16, + PseudoVFWCVT_F_XU_V_M4_E16_MASK, + PseudoVFWCVT_F_XU_V_M4_E32, + PseudoVFWCVT_F_XU_V_M4_E32_MASK, + PseudoVFWCVT_F_XU_V_M4_E8, + PseudoVFWCVT_F_XU_V_M4_E8_MASK, + PseudoVFWCVT_F_XU_V_MF2_E16, + PseudoVFWCVT_F_XU_V_MF2_E16_MASK, + PseudoVFWCVT_F_XU_V_MF2_E32, + PseudoVFWCVT_F_XU_V_MF2_E32_MASK, + PseudoVFWCVT_F_XU_V_MF2_E8, + PseudoVFWCVT_F_XU_V_MF2_E8_MASK, + PseudoVFWCVT_F_XU_V_MF4_E16, + PseudoVFWCVT_F_XU_V_MF4_E16_MASK, + PseudoVFWCVT_F_XU_V_MF4_E8, + PseudoVFWCVT_F_XU_V_MF4_E8_MASK, + PseudoVFWCVT_F_XU_V_MF8_E8, + PseudoVFWCVT_F_XU_V_MF8_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_M1_E8, + PseudoVFWCVT_F_X_ALT_V_M1_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_M2_E8, + PseudoVFWCVT_F_X_ALT_V_M2_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_M4_E8, + PseudoVFWCVT_F_X_ALT_V_M4_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_MF2_E8, + PseudoVFWCVT_F_X_ALT_V_MF2_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_MF4_E8, + PseudoVFWCVT_F_X_ALT_V_MF4_E8_MASK, + PseudoVFWCVT_F_X_ALT_V_MF8_E8, + PseudoVFWCVT_F_X_ALT_V_MF8_E8_MASK, + PseudoVFWCVT_F_X_V_M1_E16, + PseudoVFWCVT_F_X_V_M1_E16_MASK, + PseudoVFWCVT_F_X_V_M1_E32, + PseudoVFWCVT_F_X_V_M1_E32_MASK, + PseudoVFWCVT_F_X_V_M1_E8, + PseudoVFWCVT_F_X_V_M1_E8_MASK, + PseudoVFWCVT_F_X_V_M2_E16, + PseudoVFWCVT_F_X_V_M2_E16_MASK, + PseudoVFWCVT_F_X_V_M2_E32, + PseudoVFWCVT_F_X_V_M2_E32_MASK, + PseudoVFWCVT_F_X_V_M2_E8, + PseudoVFWCVT_F_X_V_M2_E8_MASK, + PseudoVFWCVT_F_X_V_M4_E16, + PseudoVFWCVT_F_X_V_M4_E16_MASK, + PseudoVFWCVT_F_X_V_M4_E32, + PseudoVFWCVT_F_X_V_M4_E32_MASK, + PseudoVFWCVT_F_X_V_M4_E8, + PseudoVFWCVT_F_X_V_M4_E8_MASK, + PseudoVFWCVT_F_X_V_MF2_E16, + PseudoVFWCVT_F_X_V_MF2_E16_MASK, + PseudoVFWCVT_F_X_V_MF2_E32, + PseudoVFWCVT_F_X_V_MF2_E32_MASK, + PseudoVFWCVT_F_X_V_MF2_E8, + PseudoVFWCVT_F_X_V_MF2_E8_MASK, + PseudoVFWCVT_F_X_V_MF4_E16, + PseudoVFWCVT_F_X_V_MF4_E16_MASK, + PseudoVFWCVT_F_X_V_MF4_E8, + PseudoVFWCVT_F_X_V_MF4_E8_MASK, + PseudoVFWCVT_F_X_V_MF8_E8, + PseudoVFWCVT_F_X_V_MF8_E8_MASK, + PseudoVFWCVT_RTZ_XU_F_V_M1, + PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, + PseudoVFWCVT_RTZ_XU_F_V_M2, + PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, + PseudoVFWCVT_RTZ_XU_F_V_M4, + PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, + PseudoVFWCVT_RTZ_XU_F_V_MF2, + PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, + PseudoVFWCVT_RTZ_XU_F_V_MF4, + PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, + PseudoVFWCVT_RTZ_X_F_V_M1, + PseudoVFWCVT_RTZ_X_F_V_M1_MASK, + PseudoVFWCVT_RTZ_X_F_V_M2, + PseudoVFWCVT_RTZ_X_F_V_M2_MASK, + PseudoVFWCVT_RTZ_X_F_V_M4, + PseudoVFWCVT_RTZ_X_F_V_M4_MASK, + PseudoVFWCVT_RTZ_X_F_V_MF2, + PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, + PseudoVFWCVT_RTZ_X_F_V_MF4, + PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, + PseudoVFWCVT_XU_F_V_M1, + PseudoVFWCVT_XU_F_V_M1_MASK, + PseudoVFWCVT_XU_F_V_M2, + PseudoVFWCVT_XU_F_V_M2_MASK, + PseudoVFWCVT_XU_F_V_M4, + PseudoVFWCVT_XU_F_V_M4_MASK, + PseudoVFWCVT_XU_F_V_MF2, + PseudoVFWCVT_XU_F_V_MF2_MASK, + PseudoVFWCVT_XU_F_V_MF4, + PseudoVFWCVT_XU_F_V_MF4_MASK, + PseudoVFWCVT_X_F_V_M1, + PseudoVFWCVT_X_F_V_M1_MASK, + PseudoVFWCVT_X_F_V_M2, + PseudoVFWCVT_X_F_V_M2_MASK, + PseudoVFWCVT_X_F_V_M4, + PseudoVFWCVT_X_F_V_M4_MASK, + PseudoVFWCVT_X_F_V_MF2, + PseudoVFWCVT_X_F_V_MF2_MASK, + PseudoVFWCVT_X_F_V_MF4, + PseudoVFWCVT_X_F_V_MF4_MASK, + PseudoVFWMACCBF16_VFPR16_M1_E16, + PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, + PseudoVFWMACCBF16_VFPR16_M2_E16, + PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, + PseudoVFWMACCBF16_VFPR16_M4_E16, + PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, + PseudoVFWMACCBF16_VFPR16_MF2_E16, + PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, + PseudoVFWMACCBF16_VFPR16_MF4_E16, + PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, + PseudoVFWMACCBF16_VV_M1_E16, + PseudoVFWMACCBF16_VV_M1_E16_MASK, + PseudoVFWMACCBF16_VV_M1_E32, + PseudoVFWMACCBF16_VV_M1_E32_MASK, + PseudoVFWMACCBF16_VV_M2_E16, + PseudoVFWMACCBF16_VV_M2_E16_MASK, + PseudoVFWMACCBF16_VV_M2_E32, + PseudoVFWMACCBF16_VV_M2_E32_MASK, + PseudoVFWMACCBF16_VV_M4_E16, + PseudoVFWMACCBF16_VV_M4_E16_MASK, + PseudoVFWMACCBF16_VV_M4_E32, + PseudoVFWMACCBF16_VV_M4_E32_MASK, + PseudoVFWMACCBF16_VV_MF2_E16, + PseudoVFWMACCBF16_VV_MF2_E16_MASK, + PseudoVFWMACCBF16_VV_MF2_E32, + PseudoVFWMACCBF16_VV_MF2_E32_MASK, + PseudoVFWMACCBF16_VV_MF4_E16, + PseudoVFWMACCBF16_VV_MF4_E16_MASK, + PseudoVFWMACC_ALT_VFPR16_M1_E16, + PseudoVFWMACC_ALT_VFPR16_M1_E16_MASK, + PseudoVFWMACC_ALT_VFPR16_M2_E16, + PseudoVFWMACC_ALT_VFPR16_M2_E16_MASK, + PseudoVFWMACC_ALT_VFPR16_M4_E16, + PseudoVFWMACC_ALT_VFPR16_M4_E16_MASK, + PseudoVFWMACC_ALT_VFPR16_MF2_E16, + PseudoVFWMACC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWMACC_ALT_VFPR16_MF4_E16, + PseudoVFWMACC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWMACC_ALT_VV_M1_E16, + PseudoVFWMACC_ALT_VV_M1_E16_MASK, + PseudoVFWMACC_ALT_VV_M2_E16, + PseudoVFWMACC_ALT_VV_M2_E16_MASK, + PseudoVFWMACC_ALT_VV_M4_E16, + PseudoVFWMACC_ALT_VV_M4_E16_MASK, + PseudoVFWMACC_ALT_VV_MF2_E16, + PseudoVFWMACC_ALT_VV_MF2_E16_MASK, + PseudoVFWMACC_ALT_VV_MF4_E16, + PseudoVFWMACC_ALT_VV_MF4_E16_MASK, + PseudoVFWMACC_VFPR16_M1_E16, + PseudoVFWMACC_VFPR16_M1_E16_MASK, + PseudoVFWMACC_VFPR16_M2_E16, + PseudoVFWMACC_VFPR16_M2_E16_MASK, + PseudoVFWMACC_VFPR16_M4_E16, + PseudoVFWMACC_VFPR16_M4_E16_MASK, + PseudoVFWMACC_VFPR16_MF2_E16, + PseudoVFWMACC_VFPR16_MF2_E16_MASK, + PseudoVFWMACC_VFPR16_MF4_E16, + PseudoVFWMACC_VFPR16_MF4_E16_MASK, + PseudoVFWMACC_VFPR32_M1_E32, + PseudoVFWMACC_VFPR32_M1_E32_MASK, + PseudoVFWMACC_VFPR32_M2_E32, + PseudoVFWMACC_VFPR32_M2_E32_MASK, + PseudoVFWMACC_VFPR32_M4_E32, + PseudoVFWMACC_VFPR32_M4_E32_MASK, + PseudoVFWMACC_VFPR32_MF2_E32, + PseudoVFWMACC_VFPR32_MF2_E32_MASK, + PseudoVFWMACC_VV_M1_E16, + PseudoVFWMACC_VV_M1_E16_MASK, + PseudoVFWMACC_VV_M1_E32, + PseudoVFWMACC_VV_M1_E32_MASK, + PseudoVFWMACC_VV_M2_E16, + PseudoVFWMACC_VV_M2_E16_MASK, + PseudoVFWMACC_VV_M2_E32, + PseudoVFWMACC_VV_M2_E32_MASK, + PseudoVFWMACC_VV_M4_E16, + PseudoVFWMACC_VV_M4_E16_MASK, + PseudoVFWMACC_VV_M4_E32, + PseudoVFWMACC_VV_M4_E32_MASK, + PseudoVFWMACC_VV_MF2_E16, + PseudoVFWMACC_VV_MF2_E16_MASK, + PseudoVFWMACC_VV_MF2_E32, + PseudoVFWMACC_VV_MF2_E32_MASK, + PseudoVFWMACC_VV_MF4_E16, + PseudoVFWMACC_VV_MF4_E16_MASK, + PseudoVFWMSAC_ALT_VFPR16_M1_E16, + PseudoVFWMSAC_ALT_VFPR16_M1_E16_MASK, + PseudoVFWMSAC_ALT_VFPR16_M2_E16, + PseudoVFWMSAC_ALT_VFPR16_M2_E16_MASK, + PseudoVFWMSAC_ALT_VFPR16_M4_E16, + PseudoVFWMSAC_ALT_VFPR16_M4_E16_MASK, + PseudoVFWMSAC_ALT_VFPR16_MF2_E16, + PseudoVFWMSAC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWMSAC_ALT_VFPR16_MF4_E16, + PseudoVFWMSAC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWMSAC_ALT_VV_M1_E16, + PseudoVFWMSAC_ALT_VV_M1_E16_MASK, + PseudoVFWMSAC_ALT_VV_M2_E16, + PseudoVFWMSAC_ALT_VV_M2_E16_MASK, + PseudoVFWMSAC_ALT_VV_M4_E16, + PseudoVFWMSAC_ALT_VV_M4_E16_MASK, + PseudoVFWMSAC_ALT_VV_MF2_E16, + PseudoVFWMSAC_ALT_VV_MF2_E16_MASK, + PseudoVFWMSAC_ALT_VV_MF4_E16, + PseudoVFWMSAC_ALT_VV_MF4_E16_MASK, + PseudoVFWMSAC_VFPR16_M1_E16, + PseudoVFWMSAC_VFPR16_M1_E16_MASK, + PseudoVFWMSAC_VFPR16_M2_E16, + PseudoVFWMSAC_VFPR16_M2_E16_MASK, + PseudoVFWMSAC_VFPR16_M4_E16, + PseudoVFWMSAC_VFPR16_M4_E16_MASK, + PseudoVFWMSAC_VFPR16_MF2_E16, + PseudoVFWMSAC_VFPR16_MF2_E16_MASK, + PseudoVFWMSAC_VFPR16_MF4_E16, + PseudoVFWMSAC_VFPR16_MF4_E16_MASK, + PseudoVFWMSAC_VFPR32_M1_E32, + PseudoVFWMSAC_VFPR32_M1_E32_MASK, + PseudoVFWMSAC_VFPR32_M2_E32, + PseudoVFWMSAC_VFPR32_M2_E32_MASK, + PseudoVFWMSAC_VFPR32_M4_E32, + PseudoVFWMSAC_VFPR32_M4_E32_MASK, + PseudoVFWMSAC_VFPR32_MF2_E32, + PseudoVFWMSAC_VFPR32_MF2_E32_MASK, + PseudoVFWMSAC_VV_M1_E16, + PseudoVFWMSAC_VV_M1_E16_MASK, + PseudoVFWMSAC_VV_M1_E32, + PseudoVFWMSAC_VV_M1_E32_MASK, + PseudoVFWMSAC_VV_M2_E16, + PseudoVFWMSAC_VV_M2_E16_MASK, + PseudoVFWMSAC_VV_M2_E32, + PseudoVFWMSAC_VV_M2_E32_MASK, + PseudoVFWMSAC_VV_M4_E16, + PseudoVFWMSAC_VV_M4_E16_MASK, + PseudoVFWMSAC_VV_M4_E32, + PseudoVFWMSAC_VV_M4_E32_MASK, + PseudoVFWMSAC_VV_MF2_E16, + PseudoVFWMSAC_VV_MF2_E16_MASK, + PseudoVFWMSAC_VV_MF2_E32, + PseudoVFWMSAC_VV_MF2_E32_MASK, + PseudoVFWMSAC_VV_MF4_E16, + PseudoVFWMSAC_VV_MF4_E16_MASK, + PseudoVFWMUL_ALT_VFPR16_M1_E16, + PseudoVFWMUL_ALT_VFPR16_M1_E16_MASK, + PseudoVFWMUL_ALT_VFPR16_M2_E16, + PseudoVFWMUL_ALT_VFPR16_M2_E16_MASK, + PseudoVFWMUL_ALT_VFPR16_M4_E16, + PseudoVFWMUL_ALT_VFPR16_M4_E16_MASK, + PseudoVFWMUL_ALT_VFPR16_MF2_E16, + PseudoVFWMUL_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWMUL_ALT_VFPR16_MF4_E16, + PseudoVFWMUL_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWMUL_ALT_VV_M1_E16, + PseudoVFWMUL_ALT_VV_M1_E16_MASK, + PseudoVFWMUL_ALT_VV_M2_E16, + PseudoVFWMUL_ALT_VV_M2_E16_MASK, + PseudoVFWMUL_ALT_VV_M4_E16, + PseudoVFWMUL_ALT_VV_M4_E16_MASK, + PseudoVFWMUL_ALT_VV_MF2_E16, + PseudoVFWMUL_ALT_VV_MF2_E16_MASK, + PseudoVFWMUL_ALT_VV_MF4_E16, + PseudoVFWMUL_ALT_VV_MF4_E16_MASK, + PseudoVFWMUL_VFPR16_M1_E16, + PseudoVFWMUL_VFPR16_M1_E16_MASK, + PseudoVFWMUL_VFPR16_M2_E16, + PseudoVFWMUL_VFPR16_M2_E16_MASK, + PseudoVFWMUL_VFPR16_M4_E16, + PseudoVFWMUL_VFPR16_M4_E16_MASK, + PseudoVFWMUL_VFPR16_MF2_E16, + PseudoVFWMUL_VFPR16_MF2_E16_MASK, + PseudoVFWMUL_VFPR16_MF4_E16, + PseudoVFWMUL_VFPR16_MF4_E16_MASK, + PseudoVFWMUL_VFPR32_M1_E32, + PseudoVFWMUL_VFPR32_M1_E32_MASK, + PseudoVFWMUL_VFPR32_M2_E32, + PseudoVFWMUL_VFPR32_M2_E32_MASK, + PseudoVFWMUL_VFPR32_M4_E32, + PseudoVFWMUL_VFPR32_M4_E32_MASK, + PseudoVFWMUL_VFPR32_MF2_E32, + PseudoVFWMUL_VFPR32_MF2_E32_MASK, + PseudoVFWMUL_VV_M1_E16, + PseudoVFWMUL_VV_M1_E16_MASK, + PseudoVFWMUL_VV_M1_E32, + PseudoVFWMUL_VV_M1_E32_MASK, + PseudoVFWMUL_VV_M2_E16, + PseudoVFWMUL_VV_M2_E16_MASK, + PseudoVFWMUL_VV_M2_E32, + PseudoVFWMUL_VV_M2_E32_MASK, + PseudoVFWMUL_VV_M4_E16, + PseudoVFWMUL_VV_M4_E16_MASK, + PseudoVFWMUL_VV_M4_E32, + PseudoVFWMUL_VV_M4_E32_MASK, + PseudoVFWMUL_VV_MF2_E16, + PseudoVFWMUL_VV_MF2_E16_MASK, + PseudoVFWMUL_VV_MF2_E32, + PseudoVFWMUL_VV_MF2_E32_MASK, + PseudoVFWMUL_VV_MF4_E16, + PseudoVFWMUL_VV_MF4_E16_MASK, + PseudoVFWNMACC_ALT_VFPR16_M1_E16, + PseudoVFWNMACC_ALT_VFPR16_M1_E16_MASK, + PseudoVFWNMACC_ALT_VFPR16_M2_E16, + PseudoVFWNMACC_ALT_VFPR16_M2_E16_MASK, + PseudoVFWNMACC_ALT_VFPR16_M4_E16, + PseudoVFWNMACC_ALT_VFPR16_M4_E16_MASK, + PseudoVFWNMACC_ALT_VFPR16_MF2_E16, + PseudoVFWNMACC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWNMACC_ALT_VFPR16_MF4_E16, + PseudoVFWNMACC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWNMACC_ALT_VV_M1_E16, + PseudoVFWNMACC_ALT_VV_M1_E16_MASK, + PseudoVFWNMACC_ALT_VV_M2_E16, + PseudoVFWNMACC_ALT_VV_M2_E16_MASK, + PseudoVFWNMACC_ALT_VV_M4_E16, + PseudoVFWNMACC_ALT_VV_M4_E16_MASK, + PseudoVFWNMACC_ALT_VV_MF2_E16, + PseudoVFWNMACC_ALT_VV_MF2_E16_MASK, + PseudoVFWNMACC_ALT_VV_MF4_E16, + PseudoVFWNMACC_ALT_VV_MF4_E16_MASK, + PseudoVFWNMACC_VFPR16_M1_E16, + PseudoVFWNMACC_VFPR16_M1_E16_MASK, + PseudoVFWNMACC_VFPR16_M2_E16, + PseudoVFWNMACC_VFPR16_M2_E16_MASK, + PseudoVFWNMACC_VFPR16_M4_E16, + PseudoVFWNMACC_VFPR16_M4_E16_MASK, + PseudoVFWNMACC_VFPR16_MF2_E16, + PseudoVFWNMACC_VFPR16_MF2_E16_MASK, + PseudoVFWNMACC_VFPR16_MF4_E16, + PseudoVFWNMACC_VFPR16_MF4_E16_MASK, + PseudoVFWNMACC_VFPR32_M1_E32, + PseudoVFWNMACC_VFPR32_M1_E32_MASK, + PseudoVFWNMACC_VFPR32_M2_E32, + PseudoVFWNMACC_VFPR32_M2_E32_MASK, + PseudoVFWNMACC_VFPR32_M4_E32, + PseudoVFWNMACC_VFPR32_M4_E32_MASK, + PseudoVFWNMACC_VFPR32_MF2_E32, + PseudoVFWNMACC_VFPR32_MF2_E32_MASK, + PseudoVFWNMACC_VV_M1_E16, + PseudoVFWNMACC_VV_M1_E16_MASK, + PseudoVFWNMACC_VV_M1_E32, + PseudoVFWNMACC_VV_M1_E32_MASK, + PseudoVFWNMACC_VV_M2_E16, + PseudoVFWNMACC_VV_M2_E16_MASK, + PseudoVFWNMACC_VV_M2_E32, + PseudoVFWNMACC_VV_M2_E32_MASK, + PseudoVFWNMACC_VV_M4_E16, + PseudoVFWNMACC_VV_M4_E16_MASK, + PseudoVFWNMACC_VV_M4_E32, + PseudoVFWNMACC_VV_M4_E32_MASK, + PseudoVFWNMACC_VV_MF2_E16, + PseudoVFWNMACC_VV_MF2_E16_MASK, + PseudoVFWNMACC_VV_MF2_E32, + PseudoVFWNMACC_VV_MF2_E32_MASK, + PseudoVFWNMACC_VV_MF4_E16, + PseudoVFWNMACC_VV_MF4_E16_MASK, + PseudoVFWNMSAC_ALT_VFPR16_M1_E16, + PseudoVFWNMSAC_ALT_VFPR16_M1_E16_MASK, + PseudoVFWNMSAC_ALT_VFPR16_M2_E16, + PseudoVFWNMSAC_ALT_VFPR16_M2_E16_MASK, + PseudoVFWNMSAC_ALT_VFPR16_M4_E16, + PseudoVFWNMSAC_ALT_VFPR16_M4_E16_MASK, + PseudoVFWNMSAC_ALT_VFPR16_MF2_E16, + PseudoVFWNMSAC_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWNMSAC_ALT_VFPR16_MF4_E16, + PseudoVFWNMSAC_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWNMSAC_ALT_VV_M1_E16, + PseudoVFWNMSAC_ALT_VV_M1_E16_MASK, + PseudoVFWNMSAC_ALT_VV_M2_E16, + PseudoVFWNMSAC_ALT_VV_M2_E16_MASK, + PseudoVFWNMSAC_ALT_VV_M4_E16, + PseudoVFWNMSAC_ALT_VV_M4_E16_MASK, + PseudoVFWNMSAC_ALT_VV_MF2_E16, + PseudoVFWNMSAC_ALT_VV_MF2_E16_MASK, + PseudoVFWNMSAC_ALT_VV_MF4_E16, + PseudoVFWNMSAC_ALT_VV_MF4_E16_MASK, + PseudoVFWNMSAC_VFPR16_M1_E16, + PseudoVFWNMSAC_VFPR16_M1_E16_MASK, + PseudoVFWNMSAC_VFPR16_M2_E16, + PseudoVFWNMSAC_VFPR16_M2_E16_MASK, + PseudoVFWNMSAC_VFPR16_M4_E16, + PseudoVFWNMSAC_VFPR16_M4_E16_MASK, + PseudoVFWNMSAC_VFPR16_MF2_E16, + PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, + PseudoVFWNMSAC_VFPR16_MF4_E16, + PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, + PseudoVFWNMSAC_VFPR32_M1_E32, + PseudoVFWNMSAC_VFPR32_M1_E32_MASK, + PseudoVFWNMSAC_VFPR32_M2_E32, + PseudoVFWNMSAC_VFPR32_M2_E32_MASK, + PseudoVFWNMSAC_VFPR32_M4_E32, + PseudoVFWNMSAC_VFPR32_M4_E32_MASK, + PseudoVFWNMSAC_VFPR32_MF2_E32, + PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, + PseudoVFWNMSAC_VV_M1_E16, + PseudoVFWNMSAC_VV_M1_E16_MASK, + PseudoVFWNMSAC_VV_M1_E32, + PseudoVFWNMSAC_VV_M1_E32_MASK, + PseudoVFWNMSAC_VV_M2_E16, + PseudoVFWNMSAC_VV_M2_E16_MASK, + PseudoVFWNMSAC_VV_M2_E32, + PseudoVFWNMSAC_VV_M2_E32_MASK, + PseudoVFWNMSAC_VV_M4_E16, + PseudoVFWNMSAC_VV_M4_E16_MASK, + PseudoVFWNMSAC_VV_M4_E32, + PseudoVFWNMSAC_VV_M4_E32_MASK, + PseudoVFWNMSAC_VV_MF2_E16, + PseudoVFWNMSAC_VV_MF2_E16_MASK, + PseudoVFWNMSAC_VV_MF2_E32, + PseudoVFWNMSAC_VV_MF2_E32_MASK, + PseudoVFWNMSAC_VV_MF4_E16, + PseudoVFWNMSAC_VV_MF4_E16_MASK, + PseudoVFWREDOSUM_VS_M1_E16, + PseudoVFWREDOSUM_VS_M1_E16_MASK, + PseudoVFWREDOSUM_VS_M1_E32, + PseudoVFWREDOSUM_VS_M1_E32_MASK, + PseudoVFWREDOSUM_VS_M2_E16, + PseudoVFWREDOSUM_VS_M2_E16_MASK, + PseudoVFWREDOSUM_VS_M2_E32, + PseudoVFWREDOSUM_VS_M2_E32_MASK, + PseudoVFWREDOSUM_VS_M4_E16, + PseudoVFWREDOSUM_VS_M4_E16_MASK, + PseudoVFWREDOSUM_VS_M4_E32, + PseudoVFWREDOSUM_VS_M4_E32_MASK, + PseudoVFWREDOSUM_VS_M8_E16, + PseudoVFWREDOSUM_VS_M8_E16_MASK, + PseudoVFWREDOSUM_VS_M8_E32, + PseudoVFWREDOSUM_VS_M8_E32_MASK, + PseudoVFWREDOSUM_VS_MF2_E16, + PseudoVFWREDOSUM_VS_MF2_E16_MASK, + PseudoVFWREDOSUM_VS_MF2_E32, + PseudoVFWREDOSUM_VS_MF2_E32_MASK, + PseudoVFWREDOSUM_VS_MF4_E16, + PseudoVFWREDOSUM_VS_MF4_E16_MASK, + PseudoVFWREDUSUM_VS_M1_E16, + PseudoVFWREDUSUM_VS_M1_E16_MASK, + PseudoVFWREDUSUM_VS_M1_E32, + PseudoVFWREDUSUM_VS_M1_E32_MASK, + PseudoVFWREDUSUM_VS_M2_E16, + PseudoVFWREDUSUM_VS_M2_E16_MASK, + PseudoVFWREDUSUM_VS_M2_E32, + PseudoVFWREDUSUM_VS_M2_E32_MASK, + PseudoVFWREDUSUM_VS_M4_E16, + PseudoVFWREDUSUM_VS_M4_E16_MASK, + PseudoVFWREDUSUM_VS_M4_E32, + PseudoVFWREDUSUM_VS_M4_E32_MASK, + PseudoVFWREDUSUM_VS_M8_E16, + PseudoVFWREDUSUM_VS_M8_E16_MASK, + PseudoVFWREDUSUM_VS_M8_E32, + PseudoVFWREDUSUM_VS_M8_E32_MASK, + PseudoVFWREDUSUM_VS_MF2_E16, + PseudoVFWREDUSUM_VS_MF2_E16_MASK, + PseudoVFWREDUSUM_VS_MF2_E32, + PseudoVFWREDUSUM_VS_MF2_E32_MASK, + PseudoVFWREDUSUM_VS_MF4_E16, + PseudoVFWREDUSUM_VS_MF4_E16_MASK, + PseudoVFWSUB_ALT_VFPR16_M1_E16, + PseudoVFWSUB_ALT_VFPR16_M1_E16_MASK, + PseudoVFWSUB_ALT_VFPR16_M2_E16, + PseudoVFWSUB_ALT_VFPR16_M2_E16_MASK, + PseudoVFWSUB_ALT_VFPR16_M4_E16, + PseudoVFWSUB_ALT_VFPR16_M4_E16_MASK, + PseudoVFWSUB_ALT_VFPR16_MF2_E16, + PseudoVFWSUB_ALT_VFPR16_MF2_E16_MASK, + PseudoVFWSUB_ALT_VFPR16_MF4_E16, + PseudoVFWSUB_ALT_VFPR16_MF4_E16_MASK, + PseudoVFWSUB_ALT_VV_M1_E16, + PseudoVFWSUB_ALT_VV_M1_E16_MASK, + PseudoVFWSUB_ALT_VV_M2_E16, + PseudoVFWSUB_ALT_VV_M2_E16_MASK, + PseudoVFWSUB_ALT_VV_M4_E16, + PseudoVFWSUB_ALT_VV_M4_E16_MASK, + PseudoVFWSUB_ALT_VV_MF2_E16, + PseudoVFWSUB_ALT_VV_MF2_E16_MASK, + PseudoVFWSUB_ALT_VV_MF4_E16, + PseudoVFWSUB_ALT_VV_MF4_E16_MASK, + PseudoVFWSUB_ALT_WFPR16_M1_E16, + PseudoVFWSUB_ALT_WFPR16_M1_E16_MASK, + PseudoVFWSUB_ALT_WFPR16_M2_E16, + PseudoVFWSUB_ALT_WFPR16_M2_E16_MASK, + PseudoVFWSUB_ALT_WFPR16_M4_E16, + PseudoVFWSUB_ALT_WFPR16_M4_E16_MASK, + PseudoVFWSUB_ALT_WFPR16_MF2_E16, + PseudoVFWSUB_ALT_WFPR16_MF2_E16_MASK, + PseudoVFWSUB_ALT_WFPR16_MF4_E16, + PseudoVFWSUB_ALT_WFPR16_MF4_E16_MASK, + PseudoVFWSUB_ALT_WV_M1_E16, + PseudoVFWSUB_ALT_WV_M1_E16_MASK, + PseudoVFWSUB_ALT_WV_M1_E16_MASK_TIED, + PseudoVFWSUB_ALT_WV_M1_E16_TIED, + PseudoVFWSUB_ALT_WV_M2_E16, + PseudoVFWSUB_ALT_WV_M2_E16_MASK, + PseudoVFWSUB_ALT_WV_M2_E16_MASK_TIED, + PseudoVFWSUB_ALT_WV_M2_E16_TIED, + PseudoVFWSUB_ALT_WV_M4_E16, + PseudoVFWSUB_ALT_WV_M4_E16_MASK, + PseudoVFWSUB_ALT_WV_M4_E16_MASK_TIED, + PseudoVFWSUB_ALT_WV_M4_E16_TIED, + PseudoVFWSUB_ALT_WV_MF2_E16, + PseudoVFWSUB_ALT_WV_MF2_E16_MASK, + PseudoVFWSUB_ALT_WV_MF2_E16_MASK_TIED, + PseudoVFWSUB_ALT_WV_MF2_E16_TIED, + PseudoVFWSUB_ALT_WV_MF4_E16, + PseudoVFWSUB_ALT_WV_MF4_E16_MASK, + PseudoVFWSUB_ALT_WV_MF4_E16_MASK_TIED, + PseudoVFWSUB_ALT_WV_MF4_E16_TIED, + PseudoVFWSUB_VFPR16_M1_E16, + PseudoVFWSUB_VFPR16_M1_E16_MASK, + PseudoVFWSUB_VFPR16_M2_E16, + PseudoVFWSUB_VFPR16_M2_E16_MASK, + PseudoVFWSUB_VFPR16_M4_E16, + PseudoVFWSUB_VFPR16_M4_E16_MASK, + PseudoVFWSUB_VFPR16_MF2_E16, + PseudoVFWSUB_VFPR16_MF2_E16_MASK, + PseudoVFWSUB_VFPR16_MF4_E16, + PseudoVFWSUB_VFPR16_MF4_E16_MASK, + PseudoVFWSUB_VFPR32_M1_E32, + PseudoVFWSUB_VFPR32_M1_E32_MASK, + PseudoVFWSUB_VFPR32_M2_E32, + PseudoVFWSUB_VFPR32_M2_E32_MASK, + PseudoVFWSUB_VFPR32_M4_E32, + PseudoVFWSUB_VFPR32_M4_E32_MASK, + PseudoVFWSUB_VFPR32_MF2_E32, + PseudoVFWSUB_VFPR32_MF2_E32_MASK, + PseudoVFWSUB_VV_M1_E16, + PseudoVFWSUB_VV_M1_E16_MASK, + PseudoVFWSUB_VV_M1_E32, + PseudoVFWSUB_VV_M1_E32_MASK, + PseudoVFWSUB_VV_M2_E16, + PseudoVFWSUB_VV_M2_E16_MASK, + PseudoVFWSUB_VV_M2_E32, + PseudoVFWSUB_VV_M2_E32_MASK, + PseudoVFWSUB_VV_M4_E16, + PseudoVFWSUB_VV_M4_E16_MASK, + PseudoVFWSUB_VV_M4_E32, + PseudoVFWSUB_VV_M4_E32_MASK, + PseudoVFWSUB_VV_MF2_E16, + PseudoVFWSUB_VV_MF2_E16_MASK, + PseudoVFWSUB_VV_MF2_E32, + PseudoVFWSUB_VV_MF2_E32_MASK, + PseudoVFWSUB_VV_MF4_E16, + PseudoVFWSUB_VV_MF4_E16_MASK, + PseudoVFWSUB_WFPR16_M1_E16, + PseudoVFWSUB_WFPR16_M1_E16_MASK, + PseudoVFWSUB_WFPR16_M2_E16, + PseudoVFWSUB_WFPR16_M2_E16_MASK, + PseudoVFWSUB_WFPR16_M4_E16, + PseudoVFWSUB_WFPR16_M4_E16_MASK, + PseudoVFWSUB_WFPR16_MF2_E16, + PseudoVFWSUB_WFPR16_MF2_E16_MASK, + PseudoVFWSUB_WFPR16_MF4_E16, + PseudoVFWSUB_WFPR16_MF4_E16_MASK, + PseudoVFWSUB_WFPR32_M1_E32, + PseudoVFWSUB_WFPR32_M1_E32_MASK, + PseudoVFWSUB_WFPR32_M2_E32, + PseudoVFWSUB_WFPR32_M2_E32_MASK, + PseudoVFWSUB_WFPR32_M4_E32, + PseudoVFWSUB_WFPR32_M4_E32_MASK, + PseudoVFWSUB_WFPR32_MF2_E32, + PseudoVFWSUB_WFPR32_MF2_E32_MASK, + PseudoVFWSUB_WV_M1_E16, + PseudoVFWSUB_WV_M1_E16_MASK, + PseudoVFWSUB_WV_M1_E16_MASK_TIED, + PseudoVFWSUB_WV_M1_E16_TIED, + PseudoVFWSUB_WV_M1_E32, + PseudoVFWSUB_WV_M1_E32_MASK, + PseudoVFWSUB_WV_M1_E32_MASK_TIED, + PseudoVFWSUB_WV_M1_E32_TIED, + PseudoVFWSUB_WV_M2_E16, + PseudoVFWSUB_WV_M2_E16_MASK, + PseudoVFWSUB_WV_M2_E16_MASK_TIED, + PseudoVFWSUB_WV_M2_E16_TIED, + PseudoVFWSUB_WV_M2_E32, + PseudoVFWSUB_WV_M2_E32_MASK, + PseudoVFWSUB_WV_M2_E32_MASK_TIED, + PseudoVFWSUB_WV_M2_E32_TIED, + PseudoVFWSUB_WV_M4_E16, + PseudoVFWSUB_WV_M4_E16_MASK, + PseudoVFWSUB_WV_M4_E16_MASK_TIED, + PseudoVFWSUB_WV_M4_E16_TIED, + PseudoVFWSUB_WV_M4_E32, + PseudoVFWSUB_WV_M4_E32_MASK, + PseudoVFWSUB_WV_M4_E32_MASK_TIED, + PseudoVFWSUB_WV_M4_E32_TIED, + PseudoVFWSUB_WV_MF2_E16, + PseudoVFWSUB_WV_MF2_E16_MASK, + PseudoVFWSUB_WV_MF2_E16_MASK_TIED, + PseudoVFWSUB_WV_MF2_E16_TIED, + PseudoVFWSUB_WV_MF2_E32, + PseudoVFWSUB_WV_MF2_E32_MASK, + PseudoVFWSUB_WV_MF2_E32_MASK_TIED, + PseudoVFWSUB_WV_MF2_E32_TIED, + PseudoVFWSUB_WV_MF4_E16, + PseudoVFWSUB_WV_MF4_E16_MASK, + PseudoVFWSUB_WV_MF4_E16_MASK_TIED, + PseudoVFWSUB_WV_MF4_E16_TIED, + PseudoVGHSH_VV_M1, + PseudoVGHSH_VV_M2, + PseudoVGHSH_VV_M4, + PseudoVGHSH_VV_M8, + PseudoVGHSH_VV_MF2, + PseudoVGMUL_VV_M1, + PseudoVGMUL_VV_M2, + PseudoVGMUL_VV_M4, + PseudoVGMUL_VV_M8, + PseudoVGMUL_VV_MF2, + PseudoVID_V_M1, + PseudoVID_V_M1_MASK, + PseudoVID_V_M2, + PseudoVID_V_M2_MASK, + PseudoVID_V_M4, + PseudoVID_V_M4_MASK, + PseudoVID_V_M8, + PseudoVID_V_M8_MASK, + PseudoVID_V_MF2, + PseudoVID_V_MF2_MASK, + PseudoVID_V_MF4, + PseudoVID_V_MF4_MASK, + PseudoVID_V_MF8, + PseudoVID_V_MF8_MASK, + PseudoVIOTA_M_M1, + PseudoVIOTA_M_M1_MASK, + PseudoVIOTA_M_M2, + PseudoVIOTA_M_M2_MASK, + PseudoVIOTA_M_M4, + PseudoVIOTA_M_M4_MASK, + PseudoVIOTA_M_M8, + PseudoVIOTA_M_M8_MASK, + PseudoVIOTA_M_MF2, + PseudoVIOTA_M_MF2_MASK, + PseudoVIOTA_M_MF4, + PseudoVIOTA_M_MF4_MASK, + PseudoVIOTA_M_MF8, + PseudoVIOTA_M_MF8_MASK, + PseudoVLE16FF_V_M1, + PseudoVLE16FF_V_M1_MASK, + PseudoVLE16FF_V_M2, + PseudoVLE16FF_V_M2_MASK, + PseudoVLE16FF_V_M4, + PseudoVLE16FF_V_M4_MASK, + PseudoVLE16FF_V_M8, + PseudoVLE16FF_V_M8_MASK, + PseudoVLE16FF_V_MF2, + PseudoVLE16FF_V_MF2_MASK, + PseudoVLE16FF_V_MF4, + PseudoVLE16FF_V_MF4_MASK, + PseudoVLE16_V_M1, + PseudoVLE16_V_M1_MASK, + PseudoVLE16_V_M2, + PseudoVLE16_V_M2_MASK, + PseudoVLE16_V_M4, + PseudoVLE16_V_M4_MASK, + PseudoVLE16_V_M8, + PseudoVLE16_V_M8_MASK, + PseudoVLE16_V_MF2, + PseudoVLE16_V_MF2_MASK, + PseudoVLE16_V_MF4, + PseudoVLE16_V_MF4_MASK, + PseudoVLE32FF_V_M1, + PseudoVLE32FF_V_M1_MASK, + PseudoVLE32FF_V_M2, + PseudoVLE32FF_V_M2_MASK, + PseudoVLE32FF_V_M4, + PseudoVLE32FF_V_M4_MASK, + PseudoVLE32FF_V_M8, + PseudoVLE32FF_V_M8_MASK, + PseudoVLE32FF_V_MF2, + PseudoVLE32FF_V_MF2_MASK, + PseudoVLE32_V_M1, + PseudoVLE32_V_M1_MASK, + PseudoVLE32_V_M2, + PseudoVLE32_V_M2_MASK, + PseudoVLE32_V_M4, + PseudoVLE32_V_M4_MASK, + PseudoVLE32_V_M8, + PseudoVLE32_V_M8_MASK, + PseudoVLE32_V_MF2, + PseudoVLE32_V_MF2_MASK, + PseudoVLE64FF_V_M1, + PseudoVLE64FF_V_M1_MASK, + PseudoVLE64FF_V_M2, + PseudoVLE64FF_V_M2_MASK, + PseudoVLE64FF_V_M4, + PseudoVLE64FF_V_M4_MASK, + PseudoVLE64FF_V_M8, + PseudoVLE64FF_V_M8_MASK, + PseudoVLE64_V_M1, + PseudoVLE64_V_M1_MASK, + PseudoVLE64_V_M2, + PseudoVLE64_V_M2_MASK, + PseudoVLE64_V_M4, + PseudoVLE64_V_M4_MASK, + PseudoVLE64_V_M8, + PseudoVLE64_V_M8_MASK, + PseudoVLE8FF_V_M1, + PseudoVLE8FF_V_M1_MASK, + PseudoVLE8FF_V_M2, + PseudoVLE8FF_V_M2_MASK, + PseudoVLE8FF_V_M4, + PseudoVLE8FF_V_M4_MASK, + PseudoVLE8FF_V_M8, + PseudoVLE8FF_V_M8_MASK, + PseudoVLE8FF_V_MF2, + PseudoVLE8FF_V_MF2_MASK, + PseudoVLE8FF_V_MF4, + PseudoVLE8FF_V_MF4_MASK, + PseudoVLE8FF_V_MF8, + PseudoVLE8FF_V_MF8_MASK, + PseudoVLE8_V_M1, + PseudoVLE8_V_M1_MASK, + PseudoVLE8_V_M2, + PseudoVLE8_V_M2_MASK, + PseudoVLE8_V_M4, + PseudoVLE8_V_M4_MASK, + PseudoVLE8_V_M8, + PseudoVLE8_V_M8_MASK, + PseudoVLE8_V_MF2, + PseudoVLE8_V_MF2_MASK, + PseudoVLE8_V_MF4, + PseudoVLE8_V_MF4_MASK, + PseudoVLE8_V_MF8, + PseudoVLE8_V_MF8_MASK, + PseudoVLM_V_B1, + PseudoVLM_V_B16, + PseudoVLM_V_B2, + PseudoVLM_V_B32, + PseudoVLM_V_B4, + PseudoVLM_V_B64, + PseudoVLM_V_B8, + PseudoVLOXEI16_V_M1_M1, + PseudoVLOXEI16_V_M1_M1_MASK, + PseudoVLOXEI16_V_M1_M2, + PseudoVLOXEI16_V_M1_M2_MASK, + PseudoVLOXEI16_V_M1_M4, + PseudoVLOXEI16_V_M1_M4_MASK, + PseudoVLOXEI16_V_M1_MF2, + PseudoVLOXEI16_V_M1_MF2_MASK, + PseudoVLOXEI16_V_M2_M1, + PseudoVLOXEI16_V_M2_M1_MASK, + PseudoVLOXEI16_V_M2_M2, + PseudoVLOXEI16_V_M2_M2_MASK, + PseudoVLOXEI16_V_M2_M4, + PseudoVLOXEI16_V_M2_M4_MASK, + PseudoVLOXEI16_V_M2_M8, + PseudoVLOXEI16_V_M2_M8_MASK, + PseudoVLOXEI16_V_M4_M2, + PseudoVLOXEI16_V_M4_M2_MASK, + PseudoVLOXEI16_V_M4_M4, + PseudoVLOXEI16_V_M4_M4_MASK, + PseudoVLOXEI16_V_M4_M8, + PseudoVLOXEI16_V_M4_M8_MASK, + PseudoVLOXEI16_V_M8_M4, + PseudoVLOXEI16_V_M8_M4_MASK, + PseudoVLOXEI16_V_M8_M8, + PseudoVLOXEI16_V_M8_M8_MASK, + PseudoVLOXEI16_V_MF2_M1, + PseudoVLOXEI16_V_MF2_M1_MASK, + PseudoVLOXEI16_V_MF2_M2, + PseudoVLOXEI16_V_MF2_M2_MASK, + PseudoVLOXEI16_V_MF2_MF2, + PseudoVLOXEI16_V_MF2_MF2_MASK, + PseudoVLOXEI16_V_MF2_MF4, + PseudoVLOXEI16_V_MF2_MF4_MASK, + PseudoVLOXEI16_V_MF4_M1, + PseudoVLOXEI16_V_MF4_M1_MASK, + PseudoVLOXEI16_V_MF4_MF2, + PseudoVLOXEI16_V_MF4_MF2_MASK, + PseudoVLOXEI16_V_MF4_MF4, + PseudoVLOXEI16_V_MF4_MF4_MASK, + PseudoVLOXEI16_V_MF4_MF8, + PseudoVLOXEI16_V_MF4_MF8_MASK, + PseudoVLOXEI32_V_M1_M1, + PseudoVLOXEI32_V_M1_M1_MASK, + PseudoVLOXEI32_V_M1_M2, + PseudoVLOXEI32_V_M1_M2_MASK, + PseudoVLOXEI32_V_M1_MF2, + PseudoVLOXEI32_V_M1_MF2_MASK, + PseudoVLOXEI32_V_M1_MF4, + PseudoVLOXEI32_V_M1_MF4_MASK, + PseudoVLOXEI32_V_M2_M1, + PseudoVLOXEI32_V_M2_M1_MASK, + PseudoVLOXEI32_V_M2_M2, + PseudoVLOXEI32_V_M2_M2_MASK, + PseudoVLOXEI32_V_M2_M4, + PseudoVLOXEI32_V_M2_M4_MASK, + PseudoVLOXEI32_V_M2_MF2, + PseudoVLOXEI32_V_M2_MF2_MASK, + PseudoVLOXEI32_V_M4_M1, + PseudoVLOXEI32_V_M4_M1_MASK, + PseudoVLOXEI32_V_M4_M2, + PseudoVLOXEI32_V_M4_M2_MASK, + PseudoVLOXEI32_V_M4_M4, + PseudoVLOXEI32_V_M4_M4_MASK, + PseudoVLOXEI32_V_M4_M8, + PseudoVLOXEI32_V_M4_M8_MASK, + PseudoVLOXEI32_V_M8_M2, + PseudoVLOXEI32_V_M8_M2_MASK, + PseudoVLOXEI32_V_M8_M4, + PseudoVLOXEI32_V_M8_M4_MASK, + PseudoVLOXEI32_V_M8_M8, + PseudoVLOXEI32_V_M8_M8_MASK, + PseudoVLOXEI32_V_MF2_M1, + PseudoVLOXEI32_V_MF2_M1_MASK, + PseudoVLOXEI32_V_MF2_MF2, + PseudoVLOXEI32_V_MF2_MF2_MASK, + PseudoVLOXEI32_V_MF2_MF4, + PseudoVLOXEI32_V_MF2_MF4_MASK, + PseudoVLOXEI32_V_MF2_MF8, + PseudoVLOXEI32_V_MF2_MF8_MASK, + PseudoVLOXEI64_V_M1_M1, + PseudoVLOXEI64_V_M1_M1_MASK, + PseudoVLOXEI64_V_M1_MF2, + PseudoVLOXEI64_V_M1_MF2_MASK, + PseudoVLOXEI64_V_M1_MF4, + PseudoVLOXEI64_V_M1_MF4_MASK, + PseudoVLOXEI64_V_M1_MF8, + PseudoVLOXEI64_V_M1_MF8_MASK, + PseudoVLOXEI64_V_M2_M1, + PseudoVLOXEI64_V_M2_M1_MASK, + PseudoVLOXEI64_V_M2_M2, + PseudoVLOXEI64_V_M2_M2_MASK, + PseudoVLOXEI64_V_M2_MF2, + PseudoVLOXEI64_V_M2_MF2_MASK, + PseudoVLOXEI64_V_M2_MF4, + PseudoVLOXEI64_V_M2_MF4_MASK, + PseudoVLOXEI64_V_M4_M1, + PseudoVLOXEI64_V_M4_M1_MASK, + PseudoVLOXEI64_V_M4_M2, + PseudoVLOXEI64_V_M4_M2_MASK, + PseudoVLOXEI64_V_M4_M4, + PseudoVLOXEI64_V_M4_M4_MASK, + PseudoVLOXEI64_V_M4_MF2, + PseudoVLOXEI64_V_M4_MF2_MASK, + PseudoVLOXEI64_V_M8_M1, + PseudoVLOXEI64_V_M8_M1_MASK, + PseudoVLOXEI64_V_M8_M2, + PseudoVLOXEI64_V_M8_M2_MASK, + PseudoVLOXEI64_V_M8_M4, + PseudoVLOXEI64_V_M8_M4_MASK, + PseudoVLOXEI64_V_M8_M8, + PseudoVLOXEI64_V_M8_M8_MASK, + PseudoVLOXEI8_V_M1_M1, + PseudoVLOXEI8_V_M1_M1_MASK, + PseudoVLOXEI8_V_M1_M2, + PseudoVLOXEI8_V_M1_M2_MASK, + PseudoVLOXEI8_V_M1_M4, + PseudoVLOXEI8_V_M1_M4_MASK, + PseudoVLOXEI8_V_M1_M8, + PseudoVLOXEI8_V_M1_M8_MASK, + PseudoVLOXEI8_V_M2_M2, + PseudoVLOXEI8_V_M2_M2_MASK, + PseudoVLOXEI8_V_M2_M4, + PseudoVLOXEI8_V_M2_M4_MASK, + PseudoVLOXEI8_V_M2_M8, + PseudoVLOXEI8_V_M2_M8_MASK, + PseudoVLOXEI8_V_M4_M4, + PseudoVLOXEI8_V_M4_M4_MASK, + PseudoVLOXEI8_V_M4_M8, + PseudoVLOXEI8_V_M4_M8_MASK, + PseudoVLOXEI8_V_M8_M8, + PseudoVLOXEI8_V_M8_M8_MASK, + PseudoVLOXEI8_V_MF2_M1, + PseudoVLOXEI8_V_MF2_M1_MASK, + PseudoVLOXEI8_V_MF2_M2, + PseudoVLOXEI8_V_MF2_M2_MASK, + PseudoVLOXEI8_V_MF2_M4, + PseudoVLOXEI8_V_MF2_M4_MASK, + PseudoVLOXEI8_V_MF2_MF2, + PseudoVLOXEI8_V_MF2_MF2_MASK, + PseudoVLOXEI8_V_MF4_M1, + PseudoVLOXEI8_V_MF4_M1_MASK, + PseudoVLOXEI8_V_MF4_M2, + PseudoVLOXEI8_V_MF4_M2_MASK, + PseudoVLOXEI8_V_MF4_MF2, + PseudoVLOXEI8_V_MF4_MF2_MASK, + PseudoVLOXEI8_V_MF4_MF4, + PseudoVLOXEI8_V_MF4_MF4_MASK, + PseudoVLOXEI8_V_MF8_M1, + PseudoVLOXEI8_V_MF8_M1_MASK, + PseudoVLOXEI8_V_MF8_MF2, + PseudoVLOXEI8_V_MF8_MF2_MASK, + PseudoVLOXEI8_V_MF8_MF4, + PseudoVLOXEI8_V_MF8_MF4_MASK, + PseudoVLOXEI8_V_MF8_MF8, + PseudoVLOXEI8_V_MF8_MF8_MASK, + PseudoVLOXSEG2EI16_V_M1_M1, + PseudoVLOXSEG2EI16_V_M1_M1_MASK, + PseudoVLOXSEG2EI16_V_M1_M2, + PseudoVLOXSEG2EI16_V_M1_M2_MASK, + PseudoVLOXSEG2EI16_V_M1_M4, + PseudoVLOXSEG2EI16_V_M1_M4_MASK, + PseudoVLOXSEG2EI16_V_M1_MF2, + PseudoVLOXSEG2EI16_V_M1_MF2_MASK, + PseudoVLOXSEG2EI16_V_M2_M1, + PseudoVLOXSEG2EI16_V_M2_M1_MASK, + PseudoVLOXSEG2EI16_V_M2_M2, + PseudoVLOXSEG2EI16_V_M2_M2_MASK, + PseudoVLOXSEG2EI16_V_M2_M4, + PseudoVLOXSEG2EI16_V_M2_M4_MASK, + PseudoVLOXSEG2EI16_V_M4_M2, + PseudoVLOXSEG2EI16_V_M4_M2_MASK, + PseudoVLOXSEG2EI16_V_M4_M4, + PseudoVLOXSEG2EI16_V_M4_M4_MASK, + PseudoVLOXSEG2EI16_V_M8_M4, + PseudoVLOXSEG2EI16_V_M8_M4_MASK, + PseudoVLOXSEG2EI16_V_MF2_M1, + PseudoVLOXSEG2EI16_V_MF2_M1_MASK, + PseudoVLOXSEG2EI16_V_MF2_M2, + PseudoVLOXSEG2EI16_V_MF2_M2_MASK, + PseudoVLOXSEG2EI16_V_MF2_MF2, + PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG2EI16_V_MF2_MF4, + PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG2EI16_V_MF4_M1, + PseudoVLOXSEG2EI16_V_MF4_M1_MASK, + PseudoVLOXSEG2EI16_V_MF4_MF2, + PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG2EI16_V_MF4_MF4, + PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG2EI16_V_MF4_MF8, + PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG2EI32_V_M1_M1, + PseudoVLOXSEG2EI32_V_M1_M1_MASK, + PseudoVLOXSEG2EI32_V_M1_M2, + PseudoVLOXSEG2EI32_V_M1_M2_MASK, + PseudoVLOXSEG2EI32_V_M1_MF2, + PseudoVLOXSEG2EI32_V_M1_MF2_MASK, + PseudoVLOXSEG2EI32_V_M1_MF4, + PseudoVLOXSEG2EI32_V_M1_MF4_MASK, + PseudoVLOXSEG2EI32_V_M2_M1, + PseudoVLOXSEG2EI32_V_M2_M1_MASK, + PseudoVLOXSEG2EI32_V_M2_M2, + PseudoVLOXSEG2EI32_V_M2_M2_MASK, + PseudoVLOXSEG2EI32_V_M2_M4, + PseudoVLOXSEG2EI32_V_M2_M4_MASK, + PseudoVLOXSEG2EI32_V_M2_MF2, + PseudoVLOXSEG2EI32_V_M2_MF2_MASK, + PseudoVLOXSEG2EI32_V_M4_M1, + PseudoVLOXSEG2EI32_V_M4_M1_MASK, + PseudoVLOXSEG2EI32_V_M4_M2, + PseudoVLOXSEG2EI32_V_M4_M2_MASK, + PseudoVLOXSEG2EI32_V_M4_M4, + PseudoVLOXSEG2EI32_V_M4_M4_MASK, + PseudoVLOXSEG2EI32_V_M8_M2, + PseudoVLOXSEG2EI32_V_M8_M2_MASK, + PseudoVLOXSEG2EI32_V_M8_M4, + PseudoVLOXSEG2EI32_V_M8_M4_MASK, + PseudoVLOXSEG2EI32_V_MF2_M1, + PseudoVLOXSEG2EI32_V_MF2_M1_MASK, + PseudoVLOXSEG2EI32_V_MF2_MF2, + PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG2EI32_V_MF2_MF4, + PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG2EI32_V_MF2_MF8, + PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG2EI64_V_M1_M1, + PseudoVLOXSEG2EI64_V_M1_M1_MASK, + PseudoVLOXSEG2EI64_V_M1_MF2, + PseudoVLOXSEG2EI64_V_M1_MF2_MASK, + PseudoVLOXSEG2EI64_V_M1_MF4, + PseudoVLOXSEG2EI64_V_M1_MF4_MASK, + PseudoVLOXSEG2EI64_V_M1_MF8, + PseudoVLOXSEG2EI64_V_M1_MF8_MASK, + PseudoVLOXSEG2EI64_V_M2_M1, + PseudoVLOXSEG2EI64_V_M2_M1_MASK, + PseudoVLOXSEG2EI64_V_M2_M2, + PseudoVLOXSEG2EI64_V_M2_M2_MASK, + PseudoVLOXSEG2EI64_V_M2_MF2, + PseudoVLOXSEG2EI64_V_M2_MF2_MASK, + PseudoVLOXSEG2EI64_V_M2_MF4, + PseudoVLOXSEG2EI64_V_M2_MF4_MASK, + PseudoVLOXSEG2EI64_V_M4_M1, + PseudoVLOXSEG2EI64_V_M4_M1_MASK, + PseudoVLOXSEG2EI64_V_M4_M2, + PseudoVLOXSEG2EI64_V_M4_M2_MASK, + PseudoVLOXSEG2EI64_V_M4_M4, + PseudoVLOXSEG2EI64_V_M4_M4_MASK, + PseudoVLOXSEG2EI64_V_M4_MF2, + PseudoVLOXSEG2EI64_V_M4_MF2_MASK, + PseudoVLOXSEG2EI64_V_M8_M1, + PseudoVLOXSEG2EI64_V_M8_M1_MASK, + PseudoVLOXSEG2EI64_V_M8_M2, + PseudoVLOXSEG2EI64_V_M8_M2_MASK, + PseudoVLOXSEG2EI64_V_M8_M4, + PseudoVLOXSEG2EI64_V_M8_M4_MASK, + PseudoVLOXSEG2EI8_V_M1_M1, + PseudoVLOXSEG2EI8_V_M1_M1_MASK, + PseudoVLOXSEG2EI8_V_M1_M2, + PseudoVLOXSEG2EI8_V_M1_M2_MASK, + PseudoVLOXSEG2EI8_V_M1_M4, + PseudoVLOXSEG2EI8_V_M1_M4_MASK, + PseudoVLOXSEG2EI8_V_M2_M2, + PseudoVLOXSEG2EI8_V_M2_M2_MASK, + PseudoVLOXSEG2EI8_V_M2_M4, + PseudoVLOXSEG2EI8_V_M2_M4_MASK, + PseudoVLOXSEG2EI8_V_M4_M4, + PseudoVLOXSEG2EI8_V_M4_M4_MASK, + PseudoVLOXSEG2EI8_V_MF2_M1, + PseudoVLOXSEG2EI8_V_MF2_M1_MASK, + PseudoVLOXSEG2EI8_V_MF2_M2, + PseudoVLOXSEG2EI8_V_MF2_M2_MASK, + PseudoVLOXSEG2EI8_V_MF2_M4, + PseudoVLOXSEG2EI8_V_MF2_M4_MASK, + PseudoVLOXSEG2EI8_V_MF2_MF2, + PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG2EI8_V_MF4_M1, + PseudoVLOXSEG2EI8_V_MF4_M1_MASK, + PseudoVLOXSEG2EI8_V_MF4_M2, + PseudoVLOXSEG2EI8_V_MF4_M2_MASK, + PseudoVLOXSEG2EI8_V_MF4_MF2, + PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG2EI8_V_MF4_MF4, + PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG2EI8_V_MF8_M1, + PseudoVLOXSEG2EI8_V_MF8_M1_MASK, + PseudoVLOXSEG2EI8_V_MF8_MF2, + PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG2EI8_V_MF8_MF4, + PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG2EI8_V_MF8_MF8, + PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG3EI16_V_M1_M1, + PseudoVLOXSEG3EI16_V_M1_M1_MASK, + PseudoVLOXSEG3EI16_V_M1_M2, + PseudoVLOXSEG3EI16_V_M1_M2_MASK, + PseudoVLOXSEG3EI16_V_M1_MF2, + PseudoVLOXSEG3EI16_V_M1_MF2_MASK, + PseudoVLOXSEG3EI16_V_M2_M1, + PseudoVLOXSEG3EI16_V_M2_M1_MASK, + PseudoVLOXSEG3EI16_V_M2_M2, + PseudoVLOXSEG3EI16_V_M2_M2_MASK, + PseudoVLOXSEG3EI16_V_M4_M2, + PseudoVLOXSEG3EI16_V_M4_M2_MASK, + PseudoVLOXSEG3EI16_V_MF2_M1, + PseudoVLOXSEG3EI16_V_MF2_M1_MASK, + PseudoVLOXSEG3EI16_V_MF2_M2, + PseudoVLOXSEG3EI16_V_MF2_M2_MASK, + PseudoVLOXSEG3EI16_V_MF2_MF2, + PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG3EI16_V_MF2_MF4, + PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG3EI16_V_MF4_M1, + PseudoVLOXSEG3EI16_V_MF4_M1_MASK, + PseudoVLOXSEG3EI16_V_MF4_MF2, + PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG3EI16_V_MF4_MF4, + PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG3EI16_V_MF4_MF8, + PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG3EI32_V_M1_M1, + PseudoVLOXSEG3EI32_V_M1_M1_MASK, + PseudoVLOXSEG3EI32_V_M1_M2, + PseudoVLOXSEG3EI32_V_M1_M2_MASK, + PseudoVLOXSEG3EI32_V_M1_MF2, + PseudoVLOXSEG3EI32_V_M1_MF2_MASK, + PseudoVLOXSEG3EI32_V_M1_MF4, + PseudoVLOXSEG3EI32_V_M1_MF4_MASK, + PseudoVLOXSEG3EI32_V_M2_M1, + PseudoVLOXSEG3EI32_V_M2_M1_MASK, + PseudoVLOXSEG3EI32_V_M2_M2, + PseudoVLOXSEG3EI32_V_M2_M2_MASK, + PseudoVLOXSEG3EI32_V_M2_MF2, + PseudoVLOXSEG3EI32_V_M2_MF2_MASK, + PseudoVLOXSEG3EI32_V_M4_M1, + PseudoVLOXSEG3EI32_V_M4_M1_MASK, + PseudoVLOXSEG3EI32_V_M4_M2, + PseudoVLOXSEG3EI32_V_M4_M2_MASK, + PseudoVLOXSEG3EI32_V_M8_M2, + PseudoVLOXSEG3EI32_V_M8_M2_MASK, + PseudoVLOXSEG3EI32_V_MF2_M1, + PseudoVLOXSEG3EI32_V_MF2_M1_MASK, + PseudoVLOXSEG3EI32_V_MF2_MF2, + PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG3EI32_V_MF2_MF4, + PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG3EI32_V_MF2_MF8, + PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG3EI64_V_M1_M1, + PseudoVLOXSEG3EI64_V_M1_M1_MASK, + PseudoVLOXSEG3EI64_V_M1_MF2, + PseudoVLOXSEG3EI64_V_M1_MF2_MASK, + PseudoVLOXSEG3EI64_V_M1_MF4, + PseudoVLOXSEG3EI64_V_M1_MF4_MASK, + PseudoVLOXSEG3EI64_V_M1_MF8, + PseudoVLOXSEG3EI64_V_M1_MF8_MASK, + PseudoVLOXSEG3EI64_V_M2_M1, + PseudoVLOXSEG3EI64_V_M2_M1_MASK, + PseudoVLOXSEG3EI64_V_M2_M2, + PseudoVLOXSEG3EI64_V_M2_M2_MASK, + PseudoVLOXSEG3EI64_V_M2_MF2, + PseudoVLOXSEG3EI64_V_M2_MF2_MASK, + PseudoVLOXSEG3EI64_V_M2_MF4, + PseudoVLOXSEG3EI64_V_M2_MF4_MASK, + PseudoVLOXSEG3EI64_V_M4_M1, + PseudoVLOXSEG3EI64_V_M4_M1_MASK, + PseudoVLOXSEG3EI64_V_M4_M2, + PseudoVLOXSEG3EI64_V_M4_M2_MASK, + PseudoVLOXSEG3EI64_V_M4_MF2, + PseudoVLOXSEG3EI64_V_M4_MF2_MASK, + PseudoVLOXSEG3EI64_V_M8_M1, + PseudoVLOXSEG3EI64_V_M8_M1_MASK, + PseudoVLOXSEG3EI64_V_M8_M2, + PseudoVLOXSEG3EI64_V_M8_M2_MASK, + PseudoVLOXSEG3EI8_V_M1_M1, + PseudoVLOXSEG3EI8_V_M1_M1_MASK, + PseudoVLOXSEG3EI8_V_M1_M2, + PseudoVLOXSEG3EI8_V_M1_M2_MASK, + PseudoVLOXSEG3EI8_V_M2_M2, + PseudoVLOXSEG3EI8_V_M2_M2_MASK, + PseudoVLOXSEG3EI8_V_MF2_M1, + PseudoVLOXSEG3EI8_V_MF2_M1_MASK, + PseudoVLOXSEG3EI8_V_MF2_M2, + PseudoVLOXSEG3EI8_V_MF2_M2_MASK, + PseudoVLOXSEG3EI8_V_MF2_MF2, + PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG3EI8_V_MF4_M1, + PseudoVLOXSEG3EI8_V_MF4_M1_MASK, + PseudoVLOXSEG3EI8_V_MF4_M2, + PseudoVLOXSEG3EI8_V_MF4_M2_MASK, + PseudoVLOXSEG3EI8_V_MF4_MF2, + PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG3EI8_V_MF4_MF4, + PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG3EI8_V_MF8_M1, + PseudoVLOXSEG3EI8_V_MF8_M1_MASK, + PseudoVLOXSEG3EI8_V_MF8_MF2, + PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG3EI8_V_MF8_MF4, + PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG3EI8_V_MF8_MF8, + PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG4EI16_V_M1_M1, + PseudoVLOXSEG4EI16_V_M1_M1_MASK, + PseudoVLOXSEG4EI16_V_M1_M2, + PseudoVLOXSEG4EI16_V_M1_M2_MASK, + PseudoVLOXSEG4EI16_V_M1_MF2, + PseudoVLOXSEG4EI16_V_M1_MF2_MASK, + PseudoVLOXSEG4EI16_V_M2_M1, + PseudoVLOXSEG4EI16_V_M2_M1_MASK, + PseudoVLOXSEG4EI16_V_M2_M2, + PseudoVLOXSEG4EI16_V_M2_M2_MASK, + PseudoVLOXSEG4EI16_V_M4_M2, + PseudoVLOXSEG4EI16_V_M4_M2_MASK, + PseudoVLOXSEG4EI16_V_MF2_M1, + PseudoVLOXSEG4EI16_V_MF2_M1_MASK, + PseudoVLOXSEG4EI16_V_MF2_M2, + PseudoVLOXSEG4EI16_V_MF2_M2_MASK, + PseudoVLOXSEG4EI16_V_MF2_MF2, + PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG4EI16_V_MF2_MF4, + PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG4EI16_V_MF4_M1, + PseudoVLOXSEG4EI16_V_MF4_M1_MASK, + PseudoVLOXSEG4EI16_V_MF4_MF2, + PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG4EI16_V_MF4_MF4, + PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG4EI16_V_MF4_MF8, + PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG4EI32_V_M1_M1, + PseudoVLOXSEG4EI32_V_M1_M1_MASK, + PseudoVLOXSEG4EI32_V_M1_M2, + PseudoVLOXSEG4EI32_V_M1_M2_MASK, + PseudoVLOXSEG4EI32_V_M1_MF2, + PseudoVLOXSEG4EI32_V_M1_MF2_MASK, + PseudoVLOXSEG4EI32_V_M1_MF4, + PseudoVLOXSEG4EI32_V_M1_MF4_MASK, + PseudoVLOXSEG4EI32_V_M2_M1, + PseudoVLOXSEG4EI32_V_M2_M1_MASK, + PseudoVLOXSEG4EI32_V_M2_M2, + PseudoVLOXSEG4EI32_V_M2_M2_MASK, + PseudoVLOXSEG4EI32_V_M2_MF2, + PseudoVLOXSEG4EI32_V_M2_MF2_MASK, + PseudoVLOXSEG4EI32_V_M4_M1, + PseudoVLOXSEG4EI32_V_M4_M1_MASK, + PseudoVLOXSEG4EI32_V_M4_M2, + PseudoVLOXSEG4EI32_V_M4_M2_MASK, + PseudoVLOXSEG4EI32_V_M8_M2, + PseudoVLOXSEG4EI32_V_M8_M2_MASK, + PseudoVLOXSEG4EI32_V_MF2_M1, + PseudoVLOXSEG4EI32_V_MF2_M1_MASK, + PseudoVLOXSEG4EI32_V_MF2_MF2, + PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG4EI32_V_MF2_MF4, + PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG4EI32_V_MF2_MF8, + PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG4EI64_V_M1_M1, + PseudoVLOXSEG4EI64_V_M1_M1_MASK, + PseudoVLOXSEG4EI64_V_M1_MF2, + PseudoVLOXSEG4EI64_V_M1_MF2_MASK, + PseudoVLOXSEG4EI64_V_M1_MF4, + PseudoVLOXSEG4EI64_V_M1_MF4_MASK, + PseudoVLOXSEG4EI64_V_M1_MF8, + PseudoVLOXSEG4EI64_V_M1_MF8_MASK, + PseudoVLOXSEG4EI64_V_M2_M1, + PseudoVLOXSEG4EI64_V_M2_M1_MASK, + PseudoVLOXSEG4EI64_V_M2_M2, + PseudoVLOXSEG4EI64_V_M2_M2_MASK, + PseudoVLOXSEG4EI64_V_M2_MF2, + PseudoVLOXSEG4EI64_V_M2_MF2_MASK, + PseudoVLOXSEG4EI64_V_M2_MF4, + PseudoVLOXSEG4EI64_V_M2_MF4_MASK, + PseudoVLOXSEG4EI64_V_M4_M1, + PseudoVLOXSEG4EI64_V_M4_M1_MASK, + PseudoVLOXSEG4EI64_V_M4_M2, + PseudoVLOXSEG4EI64_V_M4_M2_MASK, + PseudoVLOXSEG4EI64_V_M4_MF2, + PseudoVLOXSEG4EI64_V_M4_MF2_MASK, + PseudoVLOXSEG4EI64_V_M8_M1, + PseudoVLOXSEG4EI64_V_M8_M1_MASK, + PseudoVLOXSEG4EI64_V_M8_M2, + PseudoVLOXSEG4EI64_V_M8_M2_MASK, + PseudoVLOXSEG4EI8_V_M1_M1, + PseudoVLOXSEG4EI8_V_M1_M1_MASK, + PseudoVLOXSEG4EI8_V_M1_M2, + PseudoVLOXSEG4EI8_V_M1_M2_MASK, + PseudoVLOXSEG4EI8_V_M2_M2, + PseudoVLOXSEG4EI8_V_M2_M2_MASK, + PseudoVLOXSEG4EI8_V_MF2_M1, + PseudoVLOXSEG4EI8_V_MF2_M1_MASK, + PseudoVLOXSEG4EI8_V_MF2_M2, + PseudoVLOXSEG4EI8_V_MF2_M2_MASK, + PseudoVLOXSEG4EI8_V_MF2_MF2, + PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG4EI8_V_MF4_M1, + PseudoVLOXSEG4EI8_V_MF4_M1_MASK, + PseudoVLOXSEG4EI8_V_MF4_M2, + PseudoVLOXSEG4EI8_V_MF4_M2_MASK, + PseudoVLOXSEG4EI8_V_MF4_MF2, + PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG4EI8_V_MF4_MF4, + PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG4EI8_V_MF8_M1, + PseudoVLOXSEG4EI8_V_MF8_M1_MASK, + PseudoVLOXSEG4EI8_V_MF8_MF2, + PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG4EI8_V_MF8_MF4, + PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG4EI8_V_MF8_MF8, + PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG5EI16_V_M1_M1, + PseudoVLOXSEG5EI16_V_M1_M1_MASK, + PseudoVLOXSEG5EI16_V_M1_MF2, + PseudoVLOXSEG5EI16_V_M1_MF2_MASK, + PseudoVLOXSEG5EI16_V_M2_M1, + PseudoVLOXSEG5EI16_V_M2_M1_MASK, + PseudoVLOXSEG5EI16_V_MF2_M1, + PseudoVLOXSEG5EI16_V_MF2_M1_MASK, + PseudoVLOXSEG5EI16_V_MF2_MF2, + PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG5EI16_V_MF2_MF4, + PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG5EI16_V_MF4_M1, + PseudoVLOXSEG5EI16_V_MF4_M1_MASK, + PseudoVLOXSEG5EI16_V_MF4_MF2, + PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG5EI16_V_MF4_MF4, + PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG5EI16_V_MF4_MF8, + PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG5EI32_V_M1_M1, + PseudoVLOXSEG5EI32_V_M1_M1_MASK, + PseudoVLOXSEG5EI32_V_M1_MF2, + PseudoVLOXSEG5EI32_V_M1_MF2_MASK, + PseudoVLOXSEG5EI32_V_M1_MF4, + PseudoVLOXSEG5EI32_V_M1_MF4_MASK, + PseudoVLOXSEG5EI32_V_M2_M1, + PseudoVLOXSEG5EI32_V_M2_M1_MASK, + PseudoVLOXSEG5EI32_V_M2_MF2, + PseudoVLOXSEG5EI32_V_M2_MF2_MASK, + PseudoVLOXSEG5EI32_V_M4_M1, + PseudoVLOXSEG5EI32_V_M4_M1_MASK, + PseudoVLOXSEG5EI32_V_MF2_M1, + PseudoVLOXSEG5EI32_V_MF2_M1_MASK, + PseudoVLOXSEG5EI32_V_MF2_MF2, + PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG5EI32_V_MF2_MF4, + PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG5EI32_V_MF2_MF8, + PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG5EI64_V_M1_M1, + PseudoVLOXSEG5EI64_V_M1_M1_MASK, + PseudoVLOXSEG5EI64_V_M1_MF2, + PseudoVLOXSEG5EI64_V_M1_MF2_MASK, + PseudoVLOXSEG5EI64_V_M1_MF4, + PseudoVLOXSEG5EI64_V_M1_MF4_MASK, + PseudoVLOXSEG5EI64_V_M1_MF8, + PseudoVLOXSEG5EI64_V_M1_MF8_MASK, + PseudoVLOXSEG5EI64_V_M2_M1, + PseudoVLOXSEG5EI64_V_M2_M1_MASK, + PseudoVLOXSEG5EI64_V_M2_MF2, + PseudoVLOXSEG5EI64_V_M2_MF2_MASK, + PseudoVLOXSEG5EI64_V_M2_MF4, + PseudoVLOXSEG5EI64_V_M2_MF4_MASK, + PseudoVLOXSEG5EI64_V_M4_M1, + PseudoVLOXSEG5EI64_V_M4_M1_MASK, + PseudoVLOXSEG5EI64_V_M4_MF2, + PseudoVLOXSEG5EI64_V_M4_MF2_MASK, + PseudoVLOXSEG5EI64_V_M8_M1, + PseudoVLOXSEG5EI64_V_M8_M1_MASK, + PseudoVLOXSEG5EI8_V_M1_M1, + PseudoVLOXSEG5EI8_V_M1_M1_MASK, + PseudoVLOXSEG5EI8_V_MF2_M1, + PseudoVLOXSEG5EI8_V_MF2_M1_MASK, + PseudoVLOXSEG5EI8_V_MF2_MF2, + PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG5EI8_V_MF4_M1, + PseudoVLOXSEG5EI8_V_MF4_M1_MASK, + PseudoVLOXSEG5EI8_V_MF4_MF2, + PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG5EI8_V_MF4_MF4, + PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG5EI8_V_MF8_M1, + PseudoVLOXSEG5EI8_V_MF8_M1_MASK, + PseudoVLOXSEG5EI8_V_MF8_MF2, + PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG5EI8_V_MF8_MF4, + PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG5EI8_V_MF8_MF8, + PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG6EI16_V_M1_M1, + PseudoVLOXSEG6EI16_V_M1_M1_MASK, + PseudoVLOXSEG6EI16_V_M1_MF2, + PseudoVLOXSEG6EI16_V_M1_MF2_MASK, + PseudoVLOXSEG6EI16_V_M2_M1, + PseudoVLOXSEG6EI16_V_M2_M1_MASK, + PseudoVLOXSEG6EI16_V_MF2_M1, + PseudoVLOXSEG6EI16_V_MF2_M1_MASK, + PseudoVLOXSEG6EI16_V_MF2_MF2, + PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG6EI16_V_MF2_MF4, + PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG6EI16_V_MF4_M1, + PseudoVLOXSEG6EI16_V_MF4_M1_MASK, + PseudoVLOXSEG6EI16_V_MF4_MF2, + PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG6EI16_V_MF4_MF4, + PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG6EI16_V_MF4_MF8, + PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG6EI32_V_M1_M1, + PseudoVLOXSEG6EI32_V_M1_M1_MASK, + PseudoVLOXSEG6EI32_V_M1_MF2, + PseudoVLOXSEG6EI32_V_M1_MF2_MASK, + PseudoVLOXSEG6EI32_V_M1_MF4, + PseudoVLOXSEG6EI32_V_M1_MF4_MASK, + PseudoVLOXSEG6EI32_V_M2_M1, + PseudoVLOXSEG6EI32_V_M2_M1_MASK, + PseudoVLOXSEG6EI32_V_M2_MF2, + PseudoVLOXSEG6EI32_V_M2_MF2_MASK, + PseudoVLOXSEG6EI32_V_M4_M1, + PseudoVLOXSEG6EI32_V_M4_M1_MASK, + PseudoVLOXSEG6EI32_V_MF2_M1, + PseudoVLOXSEG6EI32_V_MF2_M1_MASK, + PseudoVLOXSEG6EI32_V_MF2_MF2, + PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG6EI32_V_MF2_MF4, + PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG6EI32_V_MF2_MF8, + PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG6EI64_V_M1_M1, + PseudoVLOXSEG6EI64_V_M1_M1_MASK, + PseudoVLOXSEG6EI64_V_M1_MF2, + PseudoVLOXSEG6EI64_V_M1_MF2_MASK, + PseudoVLOXSEG6EI64_V_M1_MF4, + PseudoVLOXSEG6EI64_V_M1_MF4_MASK, + PseudoVLOXSEG6EI64_V_M1_MF8, + PseudoVLOXSEG6EI64_V_M1_MF8_MASK, + PseudoVLOXSEG6EI64_V_M2_M1, + PseudoVLOXSEG6EI64_V_M2_M1_MASK, + PseudoVLOXSEG6EI64_V_M2_MF2, + PseudoVLOXSEG6EI64_V_M2_MF2_MASK, + PseudoVLOXSEG6EI64_V_M2_MF4, + PseudoVLOXSEG6EI64_V_M2_MF4_MASK, + PseudoVLOXSEG6EI64_V_M4_M1, + PseudoVLOXSEG6EI64_V_M4_M1_MASK, + PseudoVLOXSEG6EI64_V_M4_MF2, + PseudoVLOXSEG6EI64_V_M4_MF2_MASK, + PseudoVLOXSEG6EI64_V_M8_M1, + PseudoVLOXSEG6EI64_V_M8_M1_MASK, + PseudoVLOXSEG6EI8_V_M1_M1, + PseudoVLOXSEG6EI8_V_M1_M1_MASK, + PseudoVLOXSEG6EI8_V_MF2_M1, + PseudoVLOXSEG6EI8_V_MF2_M1_MASK, + PseudoVLOXSEG6EI8_V_MF2_MF2, + PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG6EI8_V_MF4_M1, + PseudoVLOXSEG6EI8_V_MF4_M1_MASK, + PseudoVLOXSEG6EI8_V_MF4_MF2, + PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG6EI8_V_MF4_MF4, + PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG6EI8_V_MF8_M1, + PseudoVLOXSEG6EI8_V_MF8_M1_MASK, + PseudoVLOXSEG6EI8_V_MF8_MF2, + PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG6EI8_V_MF8_MF4, + PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG6EI8_V_MF8_MF8, + PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG7EI16_V_M1_M1, + PseudoVLOXSEG7EI16_V_M1_M1_MASK, + PseudoVLOXSEG7EI16_V_M1_MF2, + PseudoVLOXSEG7EI16_V_M1_MF2_MASK, + PseudoVLOXSEG7EI16_V_M2_M1, + PseudoVLOXSEG7EI16_V_M2_M1_MASK, + PseudoVLOXSEG7EI16_V_MF2_M1, + PseudoVLOXSEG7EI16_V_MF2_M1_MASK, + PseudoVLOXSEG7EI16_V_MF2_MF2, + PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG7EI16_V_MF2_MF4, + PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG7EI16_V_MF4_M1, + PseudoVLOXSEG7EI16_V_MF4_M1_MASK, + PseudoVLOXSEG7EI16_V_MF4_MF2, + PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG7EI16_V_MF4_MF4, + PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG7EI16_V_MF4_MF8, + PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG7EI32_V_M1_M1, + PseudoVLOXSEG7EI32_V_M1_M1_MASK, + PseudoVLOXSEG7EI32_V_M1_MF2, + PseudoVLOXSEG7EI32_V_M1_MF2_MASK, + PseudoVLOXSEG7EI32_V_M1_MF4, + PseudoVLOXSEG7EI32_V_M1_MF4_MASK, + PseudoVLOXSEG7EI32_V_M2_M1, + PseudoVLOXSEG7EI32_V_M2_M1_MASK, + PseudoVLOXSEG7EI32_V_M2_MF2, + PseudoVLOXSEG7EI32_V_M2_MF2_MASK, + PseudoVLOXSEG7EI32_V_M4_M1, + PseudoVLOXSEG7EI32_V_M4_M1_MASK, + PseudoVLOXSEG7EI32_V_MF2_M1, + PseudoVLOXSEG7EI32_V_MF2_M1_MASK, + PseudoVLOXSEG7EI32_V_MF2_MF2, + PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG7EI32_V_MF2_MF4, + PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG7EI32_V_MF2_MF8, + PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG7EI64_V_M1_M1, + PseudoVLOXSEG7EI64_V_M1_M1_MASK, + PseudoVLOXSEG7EI64_V_M1_MF2, + PseudoVLOXSEG7EI64_V_M1_MF2_MASK, + PseudoVLOXSEG7EI64_V_M1_MF4, + PseudoVLOXSEG7EI64_V_M1_MF4_MASK, + PseudoVLOXSEG7EI64_V_M1_MF8, + PseudoVLOXSEG7EI64_V_M1_MF8_MASK, + PseudoVLOXSEG7EI64_V_M2_M1, + PseudoVLOXSEG7EI64_V_M2_M1_MASK, + PseudoVLOXSEG7EI64_V_M2_MF2, + PseudoVLOXSEG7EI64_V_M2_MF2_MASK, + PseudoVLOXSEG7EI64_V_M2_MF4, + PseudoVLOXSEG7EI64_V_M2_MF4_MASK, + PseudoVLOXSEG7EI64_V_M4_M1, + PseudoVLOXSEG7EI64_V_M4_M1_MASK, + PseudoVLOXSEG7EI64_V_M4_MF2, + PseudoVLOXSEG7EI64_V_M4_MF2_MASK, + PseudoVLOXSEG7EI64_V_M8_M1, + PseudoVLOXSEG7EI64_V_M8_M1_MASK, + PseudoVLOXSEG7EI8_V_M1_M1, + PseudoVLOXSEG7EI8_V_M1_M1_MASK, + PseudoVLOXSEG7EI8_V_MF2_M1, + PseudoVLOXSEG7EI8_V_MF2_M1_MASK, + PseudoVLOXSEG7EI8_V_MF2_MF2, + PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG7EI8_V_MF4_M1, + PseudoVLOXSEG7EI8_V_MF4_M1_MASK, + PseudoVLOXSEG7EI8_V_MF4_MF2, + PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG7EI8_V_MF4_MF4, + PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG7EI8_V_MF8_M1, + PseudoVLOXSEG7EI8_V_MF8_M1_MASK, + PseudoVLOXSEG7EI8_V_MF8_MF2, + PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG7EI8_V_MF8_MF4, + PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG7EI8_V_MF8_MF8, + PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, + PseudoVLOXSEG8EI16_V_M1_M1, + PseudoVLOXSEG8EI16_V_M1_M1_MASK, + PseudoVLOXSEG8EI16_V_M1_MF2, + PseudoVLOXSEG8EI16_V_M1_MF2_MASK, + PseudoVLOXSEG8EI16_V_M2_M1, + PseudoVLOXSEG8EI16_V_M2_M1_MASK, + PseudoVLOXSEG8EI16_V_MF2_M1, + PseudoVLOXSEG8EI16_V_MF2_M1_MASK, + PseudoVLOXSEG8EI16_V_MF2_MF2, + PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, + PseudoVLOXSEG8EI16_V_MF2_MF4, + PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, + PseudoVLOXSEG8EI16_V_MF4_M1, + PseudoVLOXSEG8EI16_V_MF4_M1_MASK, + PseudoVLOXSEG8EI16_V_MF4_MF2, + PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, + PseudoVLOXSEG8EI16_V_MF4_MF4, + PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, + PseudoVLOXSEG8EI16_V_MF4_MF8, + PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, + PseudoVLOXSEG8EI32_V_M1_M1, + PseudoVLOXSEG8EI32_V_M1_M1_MASK, + PseudoVLOXSEG8EI32_V_M1_MF2, + PseudoVLOXSEG8EI32_V_M1_MF2_MASK, + PseudoVLOXSEG8EI32_V_M1_MF4, + PseudoVLOXSEG8EI32_V_M1_MF4_MASK, + PseudoVLOXSEG8EI32_V_M2_M1, + PseudoVLOXSEG8EI32_V_M2_M1_MASK, + PseudoVLOXSEG8EI32_V_M2_MF2, + PseudoVLOXSEG8EI32_V_M2_MF2_MASK, + PseudoVLOXSEG8EI32_V_M4_M1, + PseudoVLOXSEG8EI32_V_M4_M1_MASK, + PseudoVLOXSEG8EI32_V_MF2_M1, + PseudoVLOXSEG8EI32_V_MF2_M1_MASK, + PseudoVLOXSEG8EI32_V_MF2_MF2, + PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, + PseudoVLOXSEG8EI32_V_MF2_MF4, + PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, + PseudoVLOXSEG8EI32_V_MF2_MF8, + PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, + PseudoVLOXSEG8EI64_V_M1_M1, + PseudoVLOXSEG8EI64_V_M1_M1_MASK, + PseudoVLOXSEG8EI64_V_M1_MF2, + PseudoVLOXSEG8EI64_V_M1_MF2_MASK, + PseudoVLOXSEG8EI64_V_M1_MF4, + PseudoVLOXSEG8EI64_V_M1_MF4_MASK, + PseudoVLOXSEG8EI64_V_M1_MF8, + PseudoVLOXSEG8EI64_V_M1_MF8_MASK, + PseudoVLOXSEG8EI64_V_M2_M1, + PseudoVLOXSEG8EI64_V_M2_M1_MASK, + PseudoVLOXSEG8EI64_V_M2_MF2, + PseudoVLOXSEG8EI64_V_M2_MF2_MASK, + PseudoVLOXSEG8EI64_V_M2_MF4, + PseudoVLOXSEG8EI64_V_M2_MF4_MASK, + PseudoVLOXSEG8EI64_V_M4_M1, + PseudoVLOXSEG8EI64_V_M4_M1_MASK, + PseudoVLOXSEG8EI64_V_M4_MF2, + PseudoVLOXSEG8EI64_V_M4_MF2_MASK, + PseudoVLOXSEG8EI64_V_M8_M1, + PseudoVLOXSEG8EI64_V_M8_M1_MASK, + PseudoVLOXSEG8EI8_V_M1_M1, + PseudoVLOXSEG8EI8_V_M1_M1_MASK, + PseudoVLOXSEG8EI8_V_MF2_M1, + PseudoVLOXSEG8EI8_V_MF2_M1_MASK, + PseudoVLOXSEG8EI8_V_MF2_MF2, + PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, + PseudoVLOXSEG8EI8_V_MF4_M1, + PseudoVLOXSEG8EI8_V_MF4_M1_MASK, + PseudoVLOXSEG8EI8_V_MF4_MF2, + PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, + PseudoVLOXSEG8EI8_V_MF4_MF4, + PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, + PseudoVLOXSEG8EI8_V_MF8_M1, + PseudoVLOXSEG8EI8_V_MF8_M1_MASK, + PseudoVLOXSEG8EI8_V_MF8_MF2, + PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, + PseudoVLOXSEG8EI8_V_MF8_MF4, + PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, + PseudoVLOXSEG8EI8_V_MF8_MF8, + PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, + PseudoVLSE16_V_M1, + PseudoVLSE16_V_M1_MASK, + PseudoVLSE16_V_M2, + PseudoVLSE16_V_M2_MASK, + PseudoVLSE16_V_M4, + PseudoVLSE16_V_M4_MASK, + PseudoVLSE16_V_M8, + PseudoVLSE16_V_M8_MASK, + PseudoVLSE16_V_MF2, + PseudoVLSE16_V_MF2_MASK, + PseudoVLSE16_V_MF4, + PseudoVLSE16_V_MF4_MASK, + PseudoVLSE32_V_M1, + PseudoVLSE32_V_M1_MASK, + PseudoVLSE32_V_M2, + PseudoVLSE32_V_M2_MASK, + PseudoVLSE32_V_M4, + PseudoVLSE32_V_M4_MASK, + PseudoVLSE32_V_M8, + PseudoVLSE32_V_M8_MASK, + PseudoVLSE32_V_MF2, + PseudoVLSE32_V_MF2_MASK, + PseudoVLSE64_V_M1, + PseudoVLSE64_V_M1_MASK, + PseudoVLSE64_V_M2, + PseudoVLSE64_V_M2_MASK, + PseudoVLSE64_V_M4, + PseudoVLSE64_V_M4_MASK, + PseudoVLSE64_V_M8, + PseudoVLSE64_V_M8_MASK, + PseudoVLSE8_V_M1, + PseudoVLSE8_V_M1_MASK, + PseudoVLSE8_V_M2, + PseudoVLSE8_V_M2_MASK, + PseudoVLSE8_V_M4, + PseudoVLSE8_V_M4_MASK, + PseudoVLSE8_V_M8, + PseudoVLSE8_V_M8_MASK, + PseudoVLSE8_V_MF2, + PseudoVLSE8_V_MF2_MASK, + PseudoVLSE8_V_MF4, + PseudoVLSE8_V_MF4_MASK, + PseudoVLSE8_V_MF8, + PseudoVLSE8_V_MF8_MASK, + PseudoVLSEG2E16FF_V_M1, + PseudoVLSEG2E16FF_V_M1_MASK, + PseudoVLSEG2E16FF_V_M2, + PseudoVLSEG2E16FF_V_M2_MASK, + PseudoVLSEG2E16FF_V_M4, + PseudoVLSEG2E16FF_V_M4_MASK, + PseudoVLSEG2E16FF_V_MF2, + PseudoVLSEG2E16FF_V_MF2_MASK, + PseudoVLSEG2E16FF_V_MF4, + PseudoVLSEG2E16FF_V_MF4_MASK, + PseudoVLSEG2E16_V_M1, + PseudoVLSEG2E16_V_M1_MASK, + PseudoVLSEG2E16_V_M2, + PseudoVLSEG2E16_V_M2_MASK, + PseudoVLSEG2E16_V_M4, + PseudoVLSEG2E16_V_M4_MASK, + PseudoVLSEG2E16_V_MF2, + PseudoVLSEG2E16_V_MF2_MASK, + PseudoVLSEG2E16_V_MF4, + PseudoVLSEG2E16_V_MF4_MASK, + PseudoVLSEG2E32FF_V_M1, + PseudoVLSEG2E32FF_V_M1_MASK, + PseudoVLSEG2E32FF_V_M2, + PseudoVLSEG2E32FF_V_M2_MASK, + PseudoVLSEG2E32FF_V_M4, + PseudoVLSEG2E32FF_V_M4_MASK, + PseudoVLSEG2E32FF_V_MF2, + PseudoVLSEG2E32FF_V_MF2_MASK, + PseudoVLSEG2E32_V_M1, + PseudoVLSEG2E32_V_M1_MASK, + PseudoVLSEG2E32_V_M2, + PseudoVLSEG2E32_V_M2_MASK, + PseudoVLSEG2E32_V_M4, + PseudoVLSEG2E32_V_M4_MASK, + PseudoVLSEG2E32_V_MF2, + PseudoVLSEG2E32_V_MF2_MASK, + PseudoVLSEG2E64FF_V_M1, + PseudoVLSEG2E64FF_V_M1_MASK, + PseudoVLSEG2E64FF_V_M2, + PseudoVLSEG2E64FF_V_M2_MASK, + PseudoVLSEG2E64FF_V_M4, + PseudoVLSEG2E64FF_V_M4_MASK, + PseudoVLSEG2E64_V_M1, + PseudoVLSEG2E64_V_M1_MASK, + PseudoVLSEG2E64_V_M2, + PseudoVLSEG2E64_V_M2_MASK, + PseudoVLSEG2E64_V_M4, + PseudoVLSEG2E64_V_M4_MASK, + PseudoVLSEG2E8FF_V_M1, + PseudoVLSEG2E8FF_V_M1_MASK, + PseudoVLSEG2E8FF_V_M2, + PseudoVLSEG2E8FF_V_M2_MASK, + PseudoVLSEG2E8FF_V_M4, + PseudoVLSEG2E8FF_V_M4_MASK, + PseudoVLSEG2E8FF_V_MF2, + PseudoVLSEG2E8FF_V_MF2_MASK, + PseudoVLSEG2E8FF_V_MF4, + PseudoVLSEG2E8FF_V_MF4_MASK, + PseudoVLSEG2E8FF_V_MF8, + PseudoVLSEG2E8FF_V_MF8_MASK, + PseudoVLSEG2E8_V_M1, + PseudoVLSEG2E8_V_M1_MASK, + PseudoVLSEG2E8_V_M2, + PseudoVLSEG2E8_V_M2_MASK, + PseudoVLSEG2E8_V_M4, + PseudoVLSEG2E8_V_M4_MASK, + PseudoVLSEG2E8_V_MF2, + PseudoVLSEG2E8_V_MF2_MASK, + PseudoVLSEG2E8_V_MF4, + PseudoVLSEG2E8_V_MF4_MASK, + PseudoVLSEG2E8_V_MF8, + PseudoVLSEG2E8_V_MF8_MASK, + PseudoVLSEG3E16FF_V_M1, + PseudoVLSEG3E16FF_V_M1_MASK, + PseudoVLSEG3E16FF_V_M2, + PseudoVLSEG3E16FF_V_M2_MASK, + PseudoVLSEG3E16FF_V_MF2, + PseudoVLSEG3E16FF_V_MF2_MASK, + PseudoVLSEG3E16FF_V_MF4, + PseudoVLSEG3E16FF_V_MF4_MASK, + PseudoVLSEG3E16_V_M1, + PseudoVLSEG3E16_V_M1_MASK, + PseudoVLSEG3E16_V_M2, + PseudoVLSEG3E16_V_M2_MASK, + PseudoVLSEG3E16_V_MF2, + PseudoVLSEG3E16_V_MF2_MASK, + PseudoVLSEG3E16_V_MF4, + PseudoVLSEG3E16_V_MF4_MASK, + PseudoVLSEG3E32FF_V_M1, + PseudoVLSEG3E32FF_V_M1_MASK, + PseudoVLSEG3E32FF_V_M2, + PseudoVLSEG3E32FF_V_M2_MASK, + PseudoVLSEG3E32FF_V_MF2, + PseudoVLSEG3E32FF_V_MF2_MASK, + PseudoVLSEG3E32_V_M1, + PseudoVLSEG3E32_V_M1_MASK, + PseudoVLSEG3E32_V_M2, + PseudoVLSEG3E32_V_M2_MASK, + PseudoVLSEG3E32_V_MF2, + PseudoVLSEG3E32_V_MF2_MASK, + PseudoVLSEG3E64FF_V_M1, + PseudoVLSEG3E64FF_V_M1_MASK, + PseudoVLSEG3E64FF_V_M2, + PseudoVLSEG3E64FF_V_M2_MASK, + PseudoVLSEG3E64_V_M1, + PseudoVLSEG3E64_V_M1_MASK, + PseudoVLSEG3E64_V_M2, + PseudoVLSEG3E64_V_M2_MASK, + PseudoVLSEG3E8FF_V_M1, + PseudoVLSEG3E8FF_V_M1_MASK, + PseudoVLSEG3E8FF_V_M2, + PseudoVLSEG3E8FF_V_M2_MASK, + PseudoVLSEG3E8FF_V_MF2, + PseudoVLSEG3E8FF_V_MF2_MASK, + PseudoVLSEG3E8FF_V_MF4, + PseudoVLSEG3E8FF_V_MF4_MASK, + PseudoVLSEG3E8FF_V_MF8, + PseudoVLSEG3E8FF_V_MF8_MASK, + PseudoVLSEG3E8_V_M1, + PseudoVLSEG3E8_V_M1_MASK, + PseudoVLSEG3E8_V_M2, + PseudoVLSEG3E8_V_M2_MASK, + PseudoVLSEG3E8_V_MF2, + PseudoVLSEG3E8_V_MF2_MASK, + PseudoVLSEG3E8_V_MF4, + PseudoVLSEG3E8_V_MF4_MASK, + PseudoVLSEG3E8_V_MF8, + PseudoVLSEG3E8_V_MF8_MASK, + PseudoVLSEG4E16FF_V_M1, + PseudoVLSEG4E16FF_V_M1_MASK, + PseudoVLSEG4E16FF_V_M2, + PseudoVLSEG4E16FF_V_M2_MASK, + PseudoVLSEG4E16FF_V_MF2, + PseudoVLSEG4E16FF_V_MF2_MASK, + PseudoVLSEG4E16FF_V_MF4, + PseudoVLSEG4E16FF_V_MF4_MASK, + PseudoVLSEG4E16_V_M1, + PseudoVLSEG4E16_V_M1_MASK, + PseudoVLSEG4E16_V_M2, + PseudoVLSEG4E16_V_M2_MASK, + PseudoVLSEG4E16_V_MF2, + PseudoVLSEG4E16_V_MF2_MASK, + PseudoVLSEG4E16_V_MF4, + PseudoVLSEG4E16_V_MF4_MASK, + PseudoVLSEG4E32FF_V_M1, + PseudoVLSEG4E32FF_V_M1_MASK, + PseudoVLSEG4E32FF_V_M2, + PseudoVLSEG4E32FF_V_M2_MASK, + PseudoVLSEG4E32FF_V_MF2, + PseudoVLSEG4E32FF_V_MF2_MASK, + PseudoVLSEG4E32_V_M1, + PseudoVLSEG4E32_V_M1_MASK, + PseudoVLSEG4E32_V_M2, + PseudoVLSEG4E32_V_M2_MASK, + PseudoVLSEG4E32_V_MF2, + PseudoVLSEG4E32_V_MF2_MASK, + PseudoVLSEG4E64FF_V_M1, + PseudoVLSEG4E64FF_V_M1_MASK, + PseudoVLSEG4E64FF_V_M2, + PseudoVLSEG4E64FF_V_M2_MASK, + PseudoVLSEG4E64_V_M1, + PseudoVLSEG4E64_V_M1_MASK, + PseudoVLSEG4E64_V_M2, + PseudoVLSEG4E64_V_M2_MASK, + PseudoVLSEG4E8FF_V_M1, + PseudoVLSEG4E8FF_V_M1_MASK, + PseudoVLSEG4E8FF_V_M2, + PseudoVLSEG4E8FF_V_M2_MASK, + PseudoVLSEG4E8FF_V_MF2, + PseudoVLSEG4E8FF_V_MF2_MASK, + PseudoVLSEG4E8FF_V_MF4, + PseudoVLSEG4E8FF_V_MF4_MASK, + PseudoVLSEG4E8FF_V_MF8, + PseudoVLSEG4E8FF_V_MF8_MASK, + PseudoVLSEG4E8_V_M1, + PseudoVLSEG4E8_V_M1_MASK, + PseudoVLSEG4E8_V_M2, + PseudoVLSEG4E8_V_M2_MASK, + PseudoVLSEG4E8_V_MF2, + PseudoVLSEG4E8_V_MF2_MASK, + PseudoVLSEG4E8_V_MF4, + PseudoVLSEG4E8_V_MF4_MASK, + PseudoVLSEG4E8_V_MF8, + PseudoVLSEG4E8_V_MF8_MASK, + PseudoVLSEG5E16FF_V_M1, + PseudoVLSEG5E16FF_V_M1_MASK, + PseudoVLSEG5E16FF_V_MF2, + PseudoVLSEG5E16FF_V_MF2_MASK, + PseudoVLSEG5E16FF_V_MF4, + PseudoVLSEG5E16FF_V_MF4_MASK, + PseudoVLSEG5E16_V_M1, + PseudoVLSEG5E16_V_M1_MASK, + PseudoVLSEG5E16_V_MF2, + PseudoVLSEG5E16_V_MF2_MASK, + PseudoVLSEG5E16_V_MF4, + PseudoVLSEG5E16_V_MF4_MASK, + PseudoVLSEG5E32FF_V_M1, + PseudoVLSEG5E32FF_V_M1_MASK, + PseudoVLSEG5E32FF_V_MF2, + PseudoVLSEG5E32FF_V_MF2_MASK, + PseudoVLSEG5E32_V_M1, + PseudoVLSEG5E32_V_M1_MASK, + PseudoVLSEG5E32_V_MF2, + PseudoVLSEG5E32_V_MF2_MASK, + PseudoVLSEG5E64FF_V_M1, + PseudoVLSEG5E64FF_V_M1_MASK, + PseudoVLSEG5E64_V_M1, + PseudoVLSEG5E64_V_M1_MASK, + PseudoVLSEG5E8FF_V_M1, + PseudoVLSEG5E8FF_V_M1_MASK, + PseudoVLSEG5E8FF_V_MF2, + PseudoVLSEG5E8FF_V_MF2_MASK, + PseudoVLSEG5E8FF_V_MF4, + PseudoVLSEG5E8FF_V_MF4_MASK, + PseudoVLSEG5E8FF_V_MF8, + PseudoVLSEG5E8FF_V_MF8_MASK, + PseudoVLSEG5E8_V_M1, + PseudoVLSEG5E8_V_M1_MASK, + PseudoVLSEG5E8_V_MF2, + PseudoVLSEG5E8_V_MF2_MASK, + PseudoVLSEG5E8_V_MF4, + PseudoVLSEG5E8_V_MF4_MASK, + PseudoVLSEG5E8_V_MF8, + PseudoVLSEG5E8_V_MF8_MASK, + PseudoVLSEG6E16FF_V_M1, + PseudoVLSEG6E16FF_V_M1_MASK, + PseudoVLSEG6E16FF_V_MF2, + PseudoVLSEG6E16FF_V_MF2_MASK, + PseudoVLSEG6E16FF_V_MF4, + PseudoVLSEG6E16FF_V_MF4_MASK, + PseudoVLSEG6E16_V_M1, + PseudoVLSEG6E16_V_M1_MASK, + PseudoVLSEG6E16_V_MF2, + PseudoVLSEG6E16_V_MF2_MASK, + PseudoVLSEG6E16_V_MF4, + PseudoVLSEG6E16_V_MF4_MASK, + PseudoVLSEG6E32FF_V_M1, + PseudoVLSEG6E32FF_V_M1_MASK, + PseudoVLSEG6E32FF_V_MF2, + PseudoVLSEG6E32FF_V_MF2_MASK, + PseudoVLSEG6E32_V_M1, + PseudoVLSEG6E32_V_M1_MASK, + PseudoVLSEG6E32_V_MF2, + PseudoVLSEG6E32_V_MF2_MASK, + PseudoVLSEG6E64FF_V_M1, + PseudoVLSEG6E64FF_V_M1_MASK, + PseudoVLSEG6E64_V_M1, + PseudoVLSEG6E64_V_M1_MASK, + PseudoVLSEG6E8FF_V_M1, + PseudoVLSEG6E8FF_V_M1_MASK, + PseudoVLSEG6E8FF_V_MF2, + PseudoVLSEG6E8FF_V_MF2_MASK, + PseudoVLSEG6E8FF_V_MF4, + PseudoVLSEG6E8FF_V_MF4_MASK, + PseudoVLSEG6E8FF_V_MF8, + PseudoVLSEG6E8FF_V_MF8_MASK, + PseudoVLSEG6E8_V_M1, + PseudoVLSEG6E8_V_M1_MASK, + PseudoVLSEG6E8_V_MF2, + PseudoVLSEG6E8_V_MF2_MASK, + PseudoVLSEG6E8_V_MF4, + PseudoVLSEG6E8_V_MF4_MASK, + PseudoVLSEG6E8_V_MF8, + PseudoVLSEG6E8_V_MF8_MASK, + PseudoVLSEG7E16FF_V_M1, + PseudoVLSEG7E16FF_V_M1_MASK, + PseudoVLSEG7E16FF_V_MF2, + PseudoVLSEG7E16FF_V_MF2_MASK, + PseudoVLSEG7E16FF_V_MF4, + PseudoVLSEG7E16FF_V_MF4_MASK, + PseudoVLSEG7E16_V_M1, + PseudoVLSEG7E16_V_M1_MASK, + PseudoVLSEG7E16_V_MF2, + PseudoVLSEG7E16_V_MF2_MASK, + PseudoVLSEG7E16_V_MF4, + PseudoVLSEG7E16_V_MF4_MASK, + PseudoVLSEG7E32FF_V_M1, + PseudoVLSEG7E32FF_V_M1_MASK, + PseudoVLSEG7E32FF_V_MF2, + PseudoVLSEG7E32FF_V_MF2_MASK, + PseudoVLSEG7E32_V_M1, + PseudoVLSEG7E32_V_M1_MASK, + PseudoVLSEG7E32_V_MF2, + PseudoVLSEG7E32_V_MF2_MASK, + PseudoVLSEG7E64FF_V_M1, + PseudoVLSEG7E64FF_V_M1_MASK, + PseudoVLSEG7E64_V_M1, + PseudoVLSEG7E64_V_M1_MASK, + PseudoVLSEG7E8FF_V_M1, + PseudoVLSEG7E8FF_V_M1_MASK, + PseudoVLSEG7E8FF_V_MF2, + PseudoVLSEG7E8FF_V_MF2_MASK, + PseudoVLSEG7E8FF_V_MF4, + PseudoVLSEG7E8FF_V_MF4_MASK, + PseudoVLSEG7E8FF_V_MF8, + PseudoVLSEG7E8FF_V_MF8_MASK, + PseudoVLSEG7E8_V_M1, + PseudoVLSEG7E8_V_M1_MASK, + PseudoVLSEG7E8_V_MF2, + PseudoVLSEG7E8_V_MF2_MASK, + PseudoVLSEG7E8_V_MF4, + PseudoVLSEG7E8_V_MF4_MASK, + PseudoVLSEG7E8_V_MF8, + PseudoVLSEG7E8_V_MF8_MASK, + PseudoVLSEG8E16FF_V_M1, + PseudoVLSEG8E16FF_V_M1_MASK, + PseudoVLSEG8E16FF_V_MF2, + PseudoVLSEG8E16FF_V_MF2_MASK, + PseudoVLSEG8E16FF_V_MF4, + PseudoVLSEG8E16FF_V_MF4_MASK, + PseudoVLSEG8E16_V_M1, + PseudoVLSEG8E16_V_M1_MASK, + PseudoVLSEG8E16_V_MF2, + PseudoVLSEG8E16_V_MF2_MASK, + PseudoVLSEG8E16_V_MF4, + PseudoVLSEG8E16_V_MF4_MASK, + PseudoVLSEG8E32FF_V_M1, + PseudoVLSEG8E32FF_V_M1_MASK, + PseudoVLSEG8E32FF_V_MF2, + PseudoVLSEG8E32FF_V_MF2_MASK, + PseudoVLSEG8E32_V_M1, + PseudoVLSEG8E32_V_M1_MASK, + PseudoVLSEG8E32_V_MF2, + PseudoVLSEG8E32_V_MF2_MASK, + PseudoVLSEG8E64FF_V_M1, + PseudoVLSEG8E64FF_V_M1_MASK, + PseudoVLSEG8E64_V_M1, + PseudoVLSEG8E64_V_M1_MASK, + PseudoVLSEG8E8FF_V_M1, + PseudoVLSEG8E8FF_V_M1_MASK, + PseudoVLSEG8E8FF_V_MF2, + PseudoVLSEG8E8FF_V_MF2_MASK, + PseudoVLSEG8E8FF_V_MF4, + PseudoVLSEG8E8FF_V_MF4_MASK, + PseudoVLSEG8E8FF_V_MF8, + PseudoVLSEG8E8FF_V_MF8_MASK, + PseudoVLSEG8E8_V_M1, + PseudoVLSEG8E8_V_M1_MASK, + PseudoVLSEG8E8_V_MF2, + PseudoVLSEG8E8_V_MF2_MASK, + PseudoVLSEG8E8_V_MF4, + PseudoVLSEG8E8_V_MF4_MASK, + PseudoVLSEG8E8_V_MF8, + PseudoVLSEG8E8_V_MF8_MASK, + PseudoVLSSEG2E16_V_M1, + PseudoVLSSEG2E16_V_M1_MASK, + PseudoVLSSEG2E16_V_M2, + PseudoVLSSEG2E16_V_M2_MASK, + PseudoVLSSEG2E16_V_M4, + PseudoVLSSEG2E16_V_M4_MASK, + PseudoVLSSEG2E16_V_MF2, + PseudoVLSSEG2E16_V_MF2_MASK, + PseudoVLSSEG2E16_V_MF4, + PseudoVLSSEG2E16_V_MF4_MASK, + PseudoVLSSEG2E32_V_M1, + PseudoVLSSEG2E32_V_M1_MASK, + PseudoVLSSEG2E32_V_M2, + PseudoVLSSEG2E32_V_M2_MASK, + PseudoVLSSEG2E32_V_M4, + PseudoVLSSEG2E32_V_M4_MASK, + PseudoVLSSEG2E32_V_MF2, + PseudoVLSSEG2E32_V_MF2_MASK, + PseudoVLSSEG2E64_V_M1, + PseudoVLSSEG2E64_V_M1_MASK, + PseudoVLSSEG2E64_V_M2, + PseudoVLSSEG2E64_V_M2_MASK, + PseudoVLSSEG2E64_V_M4, + PseudoVLSSEG2E64_V_M4_MASK, + PseudoVLSSEG2E8_V_M1, + PseudoVLSSEG2E8_V_M1_MASK, + PseudoVLSSEG2E8_V_M2, + PseudoVLSSEG2E8_V_M2_MASK, + PseudoVLSSEG2E8_V_M4, + PseudoVLSSEG2E8_V_M4_MASK, + PseudoVLSSEG2E8_V_MF2, + PseudoVLSSEG2E8_V_MF2_MASK, + PseudoVLSSEG2E8_V_MF4, + PseudoVLSSEG2E8_V_MF4_MASK, + PseudoVLSSEG2E8_V_MF8, + PseudoVLSSEG2E8_V_MF8_MASK, + PseudoVLSSEG3E16_V_M1, + PseudoVLSSEG3E16_V_M1_MASK, + PseudoVLSSEG3E16_V_M2, + PseudoVLSSEG3E16_V_M2_MASK, + PseudoVLSSEG3E16_V_MF2, + PseudoVLSSEG3E16_V_MF2_MASK, + PseudoVLSSEG3E16_V_MF4, + PseudoVLSSEG3E16_V_MF4_MASK, + PseudoVLSSEG3E32_V_M1, + PseudoVLSSEG3E32_V_M1_MASK, + PseudoVLSSEG3E32_V_M2, + PseudoVLSSEG3E32_V_M2_MASK, + PseudoVLSSEG3E32_V_MF2, + PseudoVLSSEG3E32_V_MF2_MASK, + PseudoVLSSEG3E64_V_M1, + PseudoVLSSEG3E64_V_M1_MASK, + PseudoVLSSEG3E64_V_M2, + PseudoVLSSEG3E64_V_M2_MASK, + PseudoVLSSEG3E8_V_M1, + PseudoVLSSEG3E8_V_M1_MASK, + PseudoVLSSEG3E8_V_M2, + PseudoVLSSEG3E8_V_M2_MASK, + PseudoVLSSEG3E8_V_MF2, + PseudoVLSSEG3E8_V_MF2_MASK, + PseudoVLSSEG3E8_V_MF4, + PseudoVLSSEG3E8_V_MF4_MASK, + PseudoVLSSEG3E8_V_MF8, + PseudoVLSSEG3E8_V_MF8_MASK, + PseudoVLSSEG4E16_V_M1, + PseudoVLSSEG4E16_V_M1_MASK, + PseudoVLSSEG4E16_V_M2, + PseudoVLSSEG4E16_V_M2_MASK, + PseudoVLSSEG4E16_V_MF2, + PseudoVLSSEG4E16_V_MF2_MASK, + PseudoVLSSEG4E16_V_MF4, + PseudoVLSSEG4E16_V_MF4_MASK, + PseudoVLSSEG4E32_V_M1, + PseudoVLSSEG4E32_V_M1_MASK, + PseudoVLSSEG4E32_V_M2, + PseudoVLSSEG4E32_V_M2_MASK, + PseudoVLSSEG4E32_V_MF2, + PseudoVLSSEG4E32_V_MF2_MASK, + PseudoVLSSEG4E64_V_M1, + PseudoVLSSEG4E64_V_M1_MASK, + PseudoVLSSEG4E64_V_M2, + PseudoVLSSEG4E64_V_M2_MASK, + PseudoVLSSEG4E8_V_M1, + PseudoVLSSEG4E8_V_M1_MASK, + PseudoVLSSEG4E8_V_M2, + PseudoVLSSEG4E8_V_M2_MASK, + PseudoVLSSEG4E8_V_MF2, + PseudoVLSSEG4E8_V_MF2_MASK, + PseudoVLSSEG4E8_V_MF4, + PseudoVLSSEG4E8_V_MF4_MASK, + PseudoVLSSEG4E8_V_MF8, + PseudoVLSSEG4E8_V_MF8_MASK, + PseudoVLSSEG5E16_V_M1, + PseudoVLSSEG5E16_V_M1_MASK, + PseudoVLSSEG5E16_V_MF2, + PseudoVLSSEG5E16_V_MF2_MASK, + PseudoVLSSEG5E16_V_MF4, + PseudoVLSSEG5E16_V_MF4_MASK, + PseudoVLSSEG5E32_V_M1, + PseudoVLSSEG5E32_V_M1_MASK, + PseudoVLSSEG5E32_V_MF2, + PseudoVLSSEG5E32_V_MF2_MASK, + PseudoVLSSEG5E64_V_M1, + PseudoVLSSEG5E64_V_M1_MASK, + PseudoVLSSEG5E8_V_M1, + PseudoVLSSEG5E8_V_M1_MASK, + PseudoVLSSEG5E8_V_MF2, + PseudoVLSSEG5E8_V_MF2_MASK, + PseudoVLSSEG5E8_V_MF4, + PseudoVLSSEG5E8_V_MF4_MASK, + PseudoVLSSEG5E8_V_MF8, + PseudoVLSSEG5E8_V_MF8_MASK, + PseudoVLSSEG6E16_V_M1, + PseudoVLSSEG6E16_V_M1_MASK, + PseudoVLSSEG6E16_V_MF2, + PseudoVLSSEG6E16_V_MF2_MASK, + PseudoVLSSEG6E16_V_MF4, + PseudoVLSSEG6E16_V_MF4_MASK, + PseudoVLSSEG6E32_V_M1, + PseudoVLSSEG6E32_V_M1_MASK, + PseudoVLSSEG6E32_V_MF2, + PseudoVLSSEG6E32_V_MF2_MASK, + PseudoVLSSEG6E64_V_M1, + PseudoVLSSEG6E64_V_M1_MASK, + PseudoVLSSEG6E8_V_M1, + PseudoVLSSEG6E8_V_M1_MASK, + PseudoVLSSEG6E8_V_MF2, + PseudoVLSSEG6E8_V_MF2_MASK, + PseudoVLSSEG6E8_V_MF4, + PseudoVLSSEG6E8_V_MF4_MASK, + PseudoVLSSEG6E8_V_MF8, + PseudoVLSSEG6E8_V_MF8_MASK, + PseudoVLSSEG7E16_V_M1, + PseudoVLSSEG7E16_V_M1_MASK, + PseudoVLSSEG7E16_V_MF2, + PseudoVLSSEG7E16_V_MF2_MASK, + PseudoVLSSEG7E16_V_MF4, + PseudoVLSSEG7E16_V_MF4_MASK, + PseudoVLSSEG7E32_V_M1, + PseudoVLSSEG7E32_V_M1_MASK, + PseudoVLSSEG7E32_V_MF2, + PseudoVLSSEG7E32_V_MF2_MASK, + PseudoVLSSEG7E64_V_M1, + PseudoVLSSEG7E64_V_M1_MASK, + PseudoVLSSEG7E8_V_M1, + PseudoVLSSEG7E8_V_M1_MASK, + PseudoVLSSEG7E8_V_MF2, + PseudoVLSSEG7E8_V_MF2_MASK, + PseudoVLSSEG7E8_V_MF4, + PseudoVLSSEG7E8_V_MF4_MASK, + PseudoVLSSEG7E8_V_MF8, + PseudoVLSSEG7E8_V_MF8_MASK, + PseudoVLSSEG8E16_V_M1, + PseudoVLSSEG8E16_V_M1_MASK, + PseudoVLSSEG8E16_V_MF2, + PseudoVLSSEG8E16_V_MF2_MASK, + PseudoVLSSEG8E16_V_MF4, + PseudoVLSSEG8E16_V_MF4_MASK, + PseudoVLSSEG8E32_V_M1, + PseudoVLSSEG8E32_V_M1_MASK, + PseudoVLSSEG8E32_V_MF2, + PseudoVLSSEG8E32_V_MF2_MASK, + PseudoVLSSEG8E64_V_M1, + PseudoVLSSEG8E64_V_M1_MASK, + PseudoVLSSEG8E8_V_M1, + PseudoVLSSEG8E8_V_M1_MASK, + PseudoVLSSEG8E8_V_MF2, + PseudoVLSSEG8E8_V_MF2_MASK, + PseudoVLSSEG8E8_V_MF4, + PseudoVLSSEG8E8_V_MF4_MASK, + PseudoVLSSEG8E8_V_MF8, + PseudoVLSSEG8E8_V_MF8_MASK, + PseudoVLUXEI16_V_M1_M1, + PseudoVLUXEI16_V_M1_M1_MASK, + PseudoVLUXEI16_V_M1_M2, + PseudoVLUXEI16_V_M1_M2_MASK, + PseudoVLUXEI16_V_M1_M4, + PseudoVLUXEI16_V_M1_M4_MASK, + PseudoVLUXEI16_V_M1_MF2, + PseudoVLUXEI16_V_M1_MF2_MASK, + PseudoVLUXEI16_V_M2_M1, + PseudoVLUXEI16_V_M2_M1_MASK, + PseudoVLUXEI16_V_M2_M2, + PseudoVLUXEI16_V_M2_M2_MASK, + PseudoVLUXEI16_V_M2_M4, + PseudoVLUXEI16_V_M2_M4_MASK, + PseudoVLUXEI16_V_M2_M8, + PseudoVLUXEI16_V_M2_M8_MASK, + PseudoVLUXEI16_V_M4_M2, + PseudoVLUXEI16_V_M4_M2_MASK, + PseudoVLUXEI16_V_M4_M4, + PseudoVLUXEI16_V_M4_M4_MASK, + PseudoVLUXEI16_V_M4_M8, + PseudoVLUXEI16_V_M4_M8_MASK, + PseudoVLUXEI16_V_M8_M4, + PseudoVLUXEI16_V_M8_M4_MASK, + PseudoVLUXEI16_V_M8_M8, + PseudoVLUXEI16_V_M8_M8_MASK, + PseudoVLUXEI16_V_MF2_M1, + PseudoVLUXEI16_V_MF2_M1_MASK, + PseudoVLUXEI16_V_MF2_M2, + PseudoVLUXEI16_V_MF2_M2_MASK, + PseudoVLUXEI16_V_MF2_MF2, + PseudoVLUXEI16_V_MF2_MF2_MASK, + PseudoVLUXEI16_V_MF2_MF4, + PseudoVLUXEI16_V_MF2_MF4_MASK, + PseudoVLUXEI16_V_MF4_M1, + PseudoVLUXEI16_V_MF4_M1_MASK, + PseudoVLUXEI16_V_MF4_MF2, + PseudoVLUXEI16_V_MF4_MF2_MASK, + PseudoVLUXEI16_V_MF4_MF4, + PseudoVLUXEI16_V_MF4_MF4_MASK, + PseudoVLUXEI16_V_MF4_MF8, + PseudoVLUXEI16_V_MF4_MF8_MASK, + PseudoVLUXEI32_V_M1_M1, + PseudoVLUXEI32_V_M1_M1_MASK, + PseudoVLUXEI32_V_M1_M2, + PseudoVLUXEI32_V_M1_M2_MASK, + PseudoVLUXEI32_V_M1_MF2, + PseudoVLUXEI32_V_M1_MF2_MASK, + PseudoVLUXEI32_V_M1_MF4, + PseudoVLUXEI32_V_M1_MF4_MASK, + PseudoVLUXEI32_V_M2_M1, + PseudoVLUXEI32_V_M2_M1_MASK, + PseudoVLUXEI32_V_M2_M2, + PseudoVLUXEI32_V_M2_M2_MASK, + PseudoVLUXEI32_V_M2_M4, + PseudoVLUXEI32_V_M2_M4_MASK, + PseudoVLUXEI32_V_M2_MF2, + PseudoVLUXEI32_V_M2_MF2_MASK, + PseudoVLUXEI32_V_M4_M1, + PseudoVLUXEI32_V_M4_M1_MASK, + PseudoVLUXEI32_V_M4_M2, + PseudoVLUXEI32_V_M4_M2_MASK, + PseudoVLUXEI32_V_M4_M4, + PseudoVLUXEI32_V_M4_M4_MASK, + PseudoVLUXEI32_V_M4_M8, + PseudoVLUXEI32_V_M4_M8_MASK, + PseudoVLUXEI32_V_M8_M2, + PseudoVLUXEI32_V_M8_M2_MASK, + PseudoVLUXEI32_V_M8_M4, + PseudoVLUXEI32_V_M8_M4_MASK, + PseudoVLUXEI32_V_M8_M8, + PseudoVLUXEI32_V_M8_M8_MASK, + PseudoVLUXEI32_V_MF2_M1, + PseudoVLUXEI32_V_MF2_M1_MASK, + PseudoVLUXEI32_V_MF2_MF2, + PseudoVLUXEI32_V_MF2_MF2_MASK, + PseudoVLUXEI32_V_MF2_MF4, + PseudoVLUXEI32_V_MF2_MF4_MASK, + PseudoVLUXEI32_V_MF2_MF8, + PseudoVLUXEI32_V_MF2_MF8_MASK, + PseudoVLUXEI64_V_M1_M1, + PseudoVLUXEI64_V_M1_M1_MASK, + PseudoVLUXEI64_V_M1_MF2, + PseudoVLUXEI64_V_M1_MF2_MASK, + PseudoVLUXEI64_V_M1_MF4, + PseudoVLUXEI64_V_M1_MF4_MASK, + PseudoVLUXEI64_V_M1_MF8, + PseudoVLUXEI64_V_M1_MF8_MASK, + PseudoVLUXEI64_V_M2_M1, + PseudoVLUXEI64_V_M2_M1_MASK, + PseudoVLUXEI64_V_M2_M2, + PseudoVLUXEI64_V_M2_M2_MASK, + PseudoVLUXEI64_V_M2_MF2, + PseudoVLUXEI64_V_M2_MF2_MASK, + PseudoVLUXEI64_V_M2_MF4, + PseudoVLUXEI64_V_M2_MF4_MASK, + PseudoVLUXEI64_V_M4_M1, + PseudoVLUXEI64_V_M4_M1_MASK, + PseudoVLUXEI64_V_M4_M2, + PseudoVLUXEI64_V_M4_M2_MASK, + PseudoVLUXEI64_V_M4_M4, + PseudoVLUXEI64_V_M4_M4_MASK, + PseudoVLUXEI64_V_M4_MF2, + PseudoVLUXEI64_V_M4_MF2_MASK, + PseudoVLUXEI64_V_M8_M1, + PseudoVLUXEI64_V_M8_M1_MASK, + PseudoVLUXEI64_V_M8_M2, + PseudoVLUXEI64_V_M8_M2_MASK, + PseudoVLUXEI64_V_M8_M4, + PseudoVLUXEI64_V_M8_M4_MASK, + PseudoVLUXEI64_V_M8_M8, + PseudoVLUXEI64_V_M8_M8_MASK, + PseudoVLUXEI8_V_M1_M1, + PseudoVLUXEI8_V_M1_M1_MASK, + PseudoVLUXEI8_V_M1_M2, + PseudoVLUXEI8_V_M1_M2_MASK, + PseudoVLUXEI8_V_M1_M4, + PseudoVLUXEI8_V_M1_M4_MASK, + PseudoVLUXEI8_V_M1_M8, + PseudoVLUXEI8_V_M1_M8_MASK, + PseudoVLUXEI8_V_M2_M2, + PseudoVLUXEI8_V_M2_M2_MASK, + PseudoVLUXEI8_V_M2_M4, + PseudoVLUXEI8_V_M2_M4_MASK, + PseudoVLUXEI8_V_M2_M8, + PseudoVLUXEI8_V_M2_M8_MASK, + PseudoVLUXEI8_V_M4_M4, + PseudoVLUXEI8_V_M4_M4_MASK, + PseudoVLUXEI8_V_M4_M8, + PseudoVLUXEI8_V_M4_M8_MASK, + PseudoVLUXEI8_V_M8_M8, + PseudoVLUXEI8_V_M8_M8_MASK, + PseudoVLUXEI8_V_MF2_M1, + PseudoVLUXEI8_V_MF2_M1_MASK, + PseudoVLUXEI8_V_MF2_M2, + PseudoVLUXEI8_V_MF2_M2_MASK, + PseudoVLUXEI8_V_MF2_M4, + PseudoVLUXEI8_V_MF2_M4_MASK, + PseudoVLUXEI8_V_MF2_MF2, + PseudoVLUXEI8_V_MF2_MF2_MASK, + PseudoVLUXEI8_V_MF4_M1, + PseudoVLUXEI8_V_MF4_M1_MASK, + PseudoVLUXEI8_V_MF4_M2, + PseudoVLUXEI8_V_MF4_M2_MASK, + PseudoVLUXEI8_V_MF4_MF2, + PseudoVLUXEI8_V_MF4_MF2_MASK, + PseudoVLUXEI8_V_MF4_MF4, + PseudoVLUXEI8_V_MF4_MF4_MASK, + PseudoVLUXEI8_V_MF8_M1, + PseudoVLUXEI8_V_MF8_M1_MASK, + PseudoVLUXEI8_V_MF8_MF2, + PseudoVLUXEI8_V_MF8_MF2_MASK, + PseudoVLUXEI8_V_MF8_MF4, + PseudoVLUXEI8_V_MF8_MF4_MASK, + PseudoVLUXEI8_V_MF8_MF8, + PseudoVLUXEI8_V_MF8_MF8_MASK, + PseudoVLUXSEG2EI16_V_M1_M1, + PseudoVLUXSEG2EI16_V_M1_M1_MASK, + PseudoVLUXSEG2EI16_V_M1_M2, + PseudoVLUXSEG2EI16_V_M1_M2_MASK, + PseudoVLUXSEG2EI16_V_M1_M4, + PseudoVLUXSEG2EI16_V_M1_M4_MASK, + PseudoVLUXSEG2EI16_V_M1_MF2, + PseudoVLUXSEG2EI16_V_M1_MF2_MASK, + PseudoVLUXSEG2EI16_V_M2_M1, + PseudoVLUXSEG2EI16_V_M2_M1_MASK, + PseudoVLUXSEG2EI16_V_M2_M2, + PseudoVLUXSEG2EI16_V_M2_M2_MASK, + PseudoVLUXSEG2EI16_V_M2_M4, + PseudoVLUXSEG2EI16_V_M2_M4_MASK, + PseudoVLUXSEG2EI16_V_M4_M2, + PseudoVLUXSEG2EI16_V_M4_M2_MASK, + PseudoVLUXSEG2EI16_V_M4_M4, + PseudoVLUXSEG2EI16_V_M4_M4_MASK, + PseudoVLUXSEG2EI16_V_M8_M4, + PseudoVLUXSEG2EI16_V_M8_M4_MASK, + PseudoVLUXSEG2EI16_V_MF2_M1, + PseudoVLUXSEG2EI16_V_MF2_M1_MASK, + PseudoVLUXSEG2EI16_V_MF2_M2, + PseudoVLUXSEG2EI16_V_MF2_M2_MASK, + PseudoVLUXSEG2EI16_V_MF2_MF2, + PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG2EI16_V_MF2_MF4, + PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG2EI16_V_MF4_M1, + PseudoVLUXSEG2EI16_V_MF4_M1_MASK, + PseudoVLUXSEG2EI16_V_MF4_MF2, + PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG2EI16_V_MF4_MF4, + PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG2EI16_V_MF4_MF8, + PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG2EI32_V_M1_M1, + PseudoVLUXSEG2EI32_V_M1_M1_MASK, + PseudoVLUXSEG2EI32_V_M1_M2, + PseudoVLUXSEG2EI32_V_M1_M2_MASK, + PseudoVLUXSEG2EI32_V_M1_MF2, + PseudoVLUXSEG2EI32_V_M1_MF2_MASK, + PseudoVLUXSEG2EI32_V_M1_MF4, + PseudoVLUXSEG2EI32_V_M1_MF4_MASK, + PseudoVLUXSEG2EI32_V_M2_M1, + PseudoVLUXSEG2EI32_V_M2_M1_MASK, + PseudoVLUXSEG2EI32_V_M2_M2, + PseudoVLUXSEG2EI32_V_M2_M2_MASK, + PseudoVLUXSEG2EI32_V_M2_M4, + PseudoVLUXSEG2EI32_V_M2_M4_MASK, + PseudoVLUXSEG2EI32_V_M2_MF2, + PseudoVLUXSEG2EI32_V_M2_MF2_MASK, + PseudoVLUXSEG2EI32_V_M4_M1, + PseudoVLUXSEG2EI32_V_M4_M1_MASK, + PseudoVLUXSEG2EI32_V_M4_M2, + PseudoVLUXSEG2EI32_V_M4_M2_MASK, + PseudoVLUXSEG2EI32_V_M4_M4, + PseudoVLUXSEG2EI32_V_M4_M4_MASK, + PseudoVLUXSEG2EI32_V_M8_M2, + PseudoVLUXSEG2EI32_V_M8_M2_MASK, + PseudoVLUXSEG2EI32_V_M8_M4, + PseudoVLUXSEG2EI32_V_M8_M4_MASK, + PseudoVLUXSEG2EI32_V_MF2_M1, + PseudoVLUXSEG2EI32_V_MF2_M1_MASK, + PseudoVLUXSEG2EI32_V_MF2_MF2, + PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG2EI32_V_MF2_MF4, + PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG2EI32_V_MF2_MF8, + PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG2EI64_V_M1_M1, + PseudoVLUXSEG2EI64_V_M1_M1_MASK, + PseudoVLUXSEG2EI64_V_M1_MF2, + PseudoVLUXSEG2EI64_V_M1_MF2_MASK, + PseudoVLUXSEG2EI64_V_M1_MF4, + PseudoVLUXSEG2EI64_V_M1_MF4_MASK, + PseudoVLUXSEG2EI64_V_M1_MF8, + PseudoVLUXSEG2EI64_V_M1_MF8_MASK, + PseudoVLUXSEG2EI64_V_M2_M1, + PseudoVLUXSEG2EI64_V_M2_M1_MASK, + PseudoVLUXSEG2EI64_V_M2_M2, + PseudoVLUXSEG2EI64_V_M2_M2_MASK, + PseudoVLUXSEG2EI64_V_M2_MF2, + PseudoVLUXSEG2EI64_V_M2_MF2_MASK, + PseudoVLUXSEG2EI64_V_M2_MF4, + PseudoVLUXSEG2EI64_V_M2_MF4_MASK, + PseudoVLUXSEG2EI64_V_M4_M1, + PseudoVLUXSEG2EI64_V_M4_M1_MASK, + PseudoVLUXSEG2EI64_V_M4_M2, + PseudoVLUXSEG2EI64_V_M4_M2_MASK, + PseudoVLUXSEG2EI64_V_M4_M4, + PseudoVLUXSEG2EI64_V_M4_M4_MASK, + PseudoVLUXSEG2EI64_V_M4_MF2, + PseudoVLUXSEG2EI64_V_M4_MF2_MASK, + PseudoVLUXSEG2EI64_V_M8_M1, + PseudoVLUXSEG2EI64_V_M8_M1_MASK, + PseudoVLUXSEG2EI64_V_M8_M2, + PseudoVLUXSEG2EI64_V_M8_M2_MASK, + PseudoVLUXSEG2EI64_V_M8_M4, + PseudoVLUXSEG2EI64_V_M8_M4_MASK, + PseudoVLUXSEG2EI8_V_M1_M1, + PseudoVLUXSEG2EI8_V_M1_M1_MASK, + PseudoVLUXSEG2EI8_V_M1_M2, + PseudoVLUXSEG2EI8_V_M1_M2_MASK, + PseudoVLUXSEG2EI8_V_M1_M4, + PseudoVLUXSEG2EI8_V_M1_M4_MASK, + PseudoVLUXSEG2EI8_V_M2_M2, + PseudoVLUXSEG2EI8_V_M2_M2_MASK, + PseudoVLUXSEG2EI8_V_M2_M4, + PseudoVLUXSEG2EI8_V_M2_M4_MASK, + PseudoVLUXSEG2EI8_V_M4_M4, + PseudoVLUXSEG2EI8_V_M4_M4_MASK, + PseudoVLUXSEG2EI8_V_MF2_M1, + PseudoVLUXSEG2EI8_V_MF2_M1_MASK, + PseudoVLUXSEG2EI8_V_MF2_M2, + PseudoVLUXSEG2EI8_V_MF2_M2_MASK, + PseudoVLUXSEG2EI8_V_MF2_M4, + PseudoVLUXSEG2EI8_V_MF2_M4_MASK, + PseudoVLUXSEG2EI8_V_MF2_MF2, + PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG2EI8_V_MF4_M1, + PseudoVLUXSEG2EI8_V_MF4_M1_MASK, + PseudoVLUXSEG2EI8_V_MF4_M2, + PseudoVLUXSEG2EI8_V_MF4_M2_MASK, + PseudoVLUXSEG2EI8_V_MF4_MF2, + PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG2EI8_V_MF4_MF4, + PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG2EI8_V_MF8_M1, + PseudoVLUXSEG2EI8_V_MF8_M1_MASK, + PseudoVLUXSEG2EI8_V_MF8_MF2, + PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG2EI8_V_MF8_MF4, + PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG2EI8_V_MF8_MF8, + PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG3EI16_V_M1_M1, + PseudoVLUXSEG3EI16_V_M1_M1_MASK, + PseudoVLUXSEG3EI16_V_M1_M2, + PseudoVLUXSEG3EI16_V_M1_M2_MASK, + PseudoVLUXSEG3EI16_V_M1_MF2, + PseudoVLUXSEG3EI16_V_M1_MF2_MASK, + PseudoVLUXSEG3EI16_V_M2_M1, + PseudoVLUXSEG3EI16_V_M2_M1_MASK, + PseudoVLUXSEG3EI16_V_M2_M2, + PseudoVLUXSEG3EI16_V_M2_M2_MASK, + PseudoVLUXSEG3EI16_V_M4_M2, + PseudoVLUXSEG3EI16_V_M4_M2_MASK, + PseudoVLUXSEG3EI16_V_MF2_M1, + PseudoVLUXSEG3EI16_V_MF2_M1_MASK, + PseudoVLUXSEG3EI16_V_MF2_M2, + PseudoVLUXSEG3EI16_V_MF2_M2_MASK, + PseudoVLUXSEG3EI16_V_MF2_MF2, + PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG3EI16_V_MF2_MF4, + PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG3EI16_V_MF4_M1, + PseudoVLUXSEG3EI16_V_MF4_M1_MASK, + PseudoVLUXSEG3EI16_V_MF4_MF2, + PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG3EI16_V_MF4_MF4, + PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG3EI16_V_MF4_MF8, + PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG3EI32_V_M1_M1, + PseudoVLUXSEG3EI32_V_M1_M1_MASK, + PseudoVLUXSEG3EI32_V_M1_M2, + PseudoVLUXSEG3EI32_V_M1_M2_MASK, + PseudoVLUXSEG3EI32_V_M1_MF2, + PseudoVLUXSEG3EI32_V_M1_MF2_MASK, + PseudoVLUXSEG3EI32_V_M1_MF4, + PseudoVLUXSEG3EI32_V_M1_MF4_MASK, + PseudoVLUXSEG3EI32_V_M2_M1, + PseudoVLUXSEG3EI32_V_M2_M1_MASK, + PseudoVLUXSEG3EI32_V_M2_M2, + PseudoVLUXSEG3EI32_V_M2_M2_MASK, + PseudoVLUXSEG3EI32_V_M2_MF2, + PseudoVLUXSEG3EI32_V_M2_MF2_MASK, + PseudoVLUXSEG3EI32_V_M4_M1, + PseudoVLUXSEG3EI32_V_M4_M1_MASK, + PseudoVLUXSEG3EI32_V_M4_M2, + PseudoVLUXSEG3EI32_V_M4_M2_MASK, + PseudoVLUXSEG3EI32_V_M8_M2, + PseudoVLUXSEG3EI32_V_M8_M2_MASK, + PseudoVLUXSEG3EI32_V_MF2_M1, + PseudoVLUXSEG3EI32_V_MF2_M1_MASK, + PseudoVLUXSEG3EI32_V_MF2_MF2, + PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG3EI32_V_MF2_MF4, + PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG3EI32_V_MF2_MF8, + PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG3EI64_V_M1_M1, + PseudoVLUXSEG3EI64_V_M1_M1_MASK, + PseudoVLUXSEG3EI64_V_M1_MF2, + PseudoVLUXSEG3EI64_V_M1_MF2_MASK, + PseudoVLUXSEG3EI64_V_M1_MF4, + PseudoVLUXSEG3EI64_V_M1_MF4_MASK, + PseudoVLUXSEG3EI64_V_M1_MF8, + PseudoVLUXSEG3EI64_V_M1_MF8_MASK, + PseudoVLUXSEG3EI64_V_M2_M1, + PseudoVLUXSEG3EI64_V_M2_M1_MASK, + PseudoVLUXSEG3EI64_V_M2_M2, + PseudoVLUXSEG3EI64_V_M2_M2_MASK, + PseudoVLUXSEG3EI64_V_M2_MF2, + PseudoVLUXSEG3EI64_V_M2_MF2_MASK, + PseudoVLUXSEG3EI64_V_M2_MF4, + PseudoVLUXSEG3EI64_V_M2_MF4_MASK, + PseudoVLUXSEG3EI64_V_M4_M1, + PseudoVLUXSEG3EI64_V_M4_M1_MASK, + PseudoVLUXSEG3EI64_V_M4_M2, + PseudoVLUXSEG3EI64_V_M4_M2_MASK, + PseudoVLUXSEG3EI64_V_M4_MF2, + PseudoVLUXSEG3EI64_V_M4_MF2_MASK, + PseudoVLUXSEG3EI64_V_M8_M1, + PseudoVLUXSEG3EI64_V_M8_M1_MASK, + PseudoVLUXSEG3EI64_V_M8_M2, + PseudoVLUXSEG3EI64_V_M8_M2_MASK, + PseudoVLUXSEG3EI8_V_M1_M1, + PseudoVLUXSEG3EI8_V_M1_M1_MASK, + PseudoVLUXSEG3EI8_V_M1_M2, + PseudoVLUXSEG3EI8_V_M1_M2_MASK, + PseudoVLUXSEG3EI8_V_M2_M2, + PseudoVLUXSEG3EI8_V_M2_M2_MASK, + PseudoVLUXSEG3EI8_V_MF2_M1, + PseudoVLUXSEG3EI8_V_MF2_M1_MASK, + PseudoVLUXSEG3EI8_V_MF2_M2, + PseudoVLUXSEG3EI8_V_MF2_M2_MASK, + PseudoVLUXSEG3EI8_V_MF2_MF2, + PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG3EI8_V_MF4_M1, + PseudoVLUXSEG3EI8_V_MF4_M1_MASK, + PseudoVLUXSEG3EI8_V_MF4_M2, + PseudoVLUXSEG3EI8_V_MF4_M2_MASK, + PseudoVLUXSEG3EI8_V_MF4_MF2, + PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG3EI8_V_MF4_MF4, + PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG3EI8_V_MF8_M1, + PseudoVLUXSEG3EI8_V_MF8_M1_MASK, + PseudoVLUXSEG3EI8_V_MF8_MF2, + PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG3EI8_V_MF8_MF4, + PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG3EI8_V_MF8_MF8, + PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG4EI16_V_M1_M1, + PseudoVLUXSEG4EI16_V_M1_M1_MASK, + PseudoVLUXSEG4EI16_V_M1_M2, + PseudoVLUXSEG4EI16_V_M1_M2_MASK, + PseudoVLUXSEG4EI16_V_M1_MF2, + PseudoVLUXSEG4EI16_V_M1_MF2_MASK, + PseudoVLUXSEG4EI16_V_M2_M1, + PseudoVLUXSEG4EI16_V_M2_M1_MASK, + PseudoVLUXSEG4EI16_V_M2_M2, + PseudoVLUXSEG4EI16_V_M2_M2_MASK, + PseudoVLUXSEG4EI16_V_M4_M2, + PseudoVLUXSEG4EI16_V_M4_M2_MASK, + PseudoVLUXSEG4EI16_V_MF2_M1, + PseudoVLUXSEG4EI16_V_MF2_M1_MASK, + PseudoVLUXSEG4EI16_V_MF2_M2, + PseudoVLUXSEG4EI16_V_MF2_M2_MASK, + PseudoVLUXSEG4EI16_V_MF2_MF2, + PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG4EI16_V_MF2_MF4, + PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG4EI16_V_MF4_M1, + PseudoVLUXSEG4EI16_V_MF4_M1_MASK, + PseudoVLUXSEG4EI16_V_MF4_MF2, + PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG4EI16_V_MF4_MF4, + PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG4EI16_V_MF4_MF8, + PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG4EI32_V_M1_M1, + PseudoVLUXSEG4EI32_V_M1_M1_MASK, + PseudoVLUXSEG4EI32_V_M1_M2, + PseudoVLUXSEG4EI32_V_M1_M2_MASK, + PseudoVLUXSEG4EI32_V_M1_MF2, + PseudoVLUXSEG4EI32_V_M1_MF2_MASK, + PseudoVLUXSEG4EI32_V_M1_MF4, + PseudoVLUXSEG4EI32_V_M1_MF4_MASK, + PseudoVLUXSEG4EI32_V_M2_M1, + PseudoVLUXSEG4EI32_V_M2_M1_MASK, + PseudoVLUXSEG4EI32_V_M2_M2, + PseudoVLUXSEG4EI32_V_M2_M2_MASK, + PseudoVLUXSEG4EI32_V_M2_MF2, + PseudoVLUXSEG4EI32_V_M2_MF2_MASK, + PseudoVLUXSEG4EI32_V_M4_M1, + PseudoVLUXSEG4EI32_V_M4_M1_MASK, + PseudoVLUXSEG4EI32_V_M4_M2, + PseudoVLUXSEG4EI32_V_M4_M2_MASK, + PseudoVLUXSEG4EI32_V_M8_M2, + PseudoVLUXSEG4EI32_V_M8_M2_MASK, + PseudoVLUXSEG4EI32_V_MF2_M1, + PseudoVLUXSEG4EI32_V_MF2_M1_MASK, + PseudoVLUXSEG4EI32_V_MF2_MF2, + PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG4EI32_V_MF2_MF4, + PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG4EI32_V_MF2_MF8, + PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG4EI64_V_M1_M1, + PseudoVLUXSEG4EI64_V_M1_M1_MASK, + PseudoVLUXSEG4EI64_V_M1_MF2, + PseudoVLUXSEG4EI64_V_M1_MF2_MASK, + PseudoVLUXSEG4EI64_V_M1_MF4, + PseudoVLUXSEG4EI64_V_M1_MF4_MASK, + PseudoVLUXSEG4EI64_V_M1_MF8, + PseudoVLUXSEG4EI64_V_M1_MF8_MASK, + PseudoVLUXSEG4EI64_V_M2_M1, + PseudoVLUXSEG4EI64_V_M2_M1_MASK, + PseudoVLUXSEG4EI64_V_M2_M2, + PseudoVLUXSEG4EI64_V_M2_M2_MASK, + PseudoVLUXSEG4EI64_V_M2_MF2, + PseudoVLUXSEG4EI64_V_M2_MF2_MASK, + PseudoVLUXSEG4EI64_V_M2_MF4, + PseudoVLUXSEG4EI64_V_M2_MF4_MASK, + PseudoVLUXSEG4EI64_V_M4_M1, + PseudoVLUXSEG4EI64_V_M4_M1_MASK, + PseudoVLUXSEG4EI64_V_M4_M2, + PseudoVLUXSEG4EI64_V_M4_M2_MASK, + PseudoVLUXSEG4EI64_V_M4_MF2, + PseudoVLUXSEG4EI64_V_M4_MF2_MASK, + PseudoVLUXSEG4EI64_V_M8_M1, + PseudoVLUXSEG4EI64_V_M8_M1_MASK, + PseudoVLUXSEG4EI64_V_M8_M2, + PseudoVLUXSEG4EI64_V_M8_M2_MASK, + PseudoVLUXSEG4EI8_V_M1_M1, + PseudoVLUXSEG4EI8_V_M1_M1_MASK, + PseudoVLUXSEG4EI8_V_M1_M2, + PseudoVLUXSEG4EI8_V_M1_M2_MASK, + PseudoVLUXSEG4EI8_V_M2_M2, + PseudoVLUXSEG4EI8_V_M2_M2_MASK, + PseudoVLUXSEG4EI8_V_MF2_M1, + PseudoVLUXSEG4EI8_V_MF2_M1_MASK, + PseudoVLUXSEG4EI8_V_MF2_M2, + PseudoVLUXSEG4EI8_V_MF2_M2_MASK, + PseudoVLUXSEG4EI8_V_MF2_MF2, + PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG4EI8_V_MF4_M1, + PseudoVLUXSEG4EI8_V_MF4_M1_MASK, + PseudoVLUXSEG4EI8_V_MF4_M2, + PseudoVLUXSEG4EI8_V_MF4_M2_MASK, + PseudoVLUXSEG4EI8_V_MF4_MF2, + PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG4EI8_V_MF4_MF4, + PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG4EI8_V_MF8_M1, + PseudoVLUXSEG4EI8_V_MF8_M1_MASK, + PseudoVLUXSEG4EI8_V_MF8_MF2, + PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG4EI8_V_MF8_MF4, + PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG4EI8_V_MF8_MF8, + PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG5EI16_V_M1_M1, + PseudoVLUXSEG5EI16_V_M1_M1_MASK, + PseudoVLUXSEG5EI16_V_M1_MF2, + PseudoVLUXSEG5EI16_V_M1_MF2_MASK, + PseudoVLUXSEG5EI16_V_M2_M1, + PseudoVLUXSEG5EI16_V_M2_M1_MASK, + PseudoVLUXSEG5EI16_V_MF2_M1, + PseudoVLUXSEG5EI16_V_MF2_M1_MASK, + PseudoVLUXSEG5EI16_V_MF2_MF2, + PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG5EI16_V_MF2_MF4, + PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG5EI16_V_MF4_M1, + PseudoVLUXSEG5EI16_V_MF4_M1_MASK, + PseudoVLUXSEG5EI16_V_MF4_MF2, + PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG5EI16_V_MF4_MF4, + PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG5EI16_V_MF4_MF8, + PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG5EI32_V_M1_M1, + PseudoVLUXSEG5EI32_V_M1_M1_MASK, + PseudoVLUXSEG5EI32_V_M1_MF2, + PseudoVLUXSEG5EI32_V_M1_MF2_MASK, + PseudoVLUXSEG5EI32_V_M1_MF4, + PseudoVLUXSEG5EI32_V_M1_MF4_MASK, + PseudoVLUXSEG5EI32_V_M2_M1, + PseudoVLUXSEG5EI32_V_M2_M1_MASK, + PseudoVLUXSEG5EI32_V_M2_MF2, + PseudoVLUXSEG5EI32_V_M2_MF2_MASK, + PseudoVLUXSEG5EI32_V_M4_M1, + PseudoVLUXSEG5EI32_V_M4_M1_MASK, + PseudoVLUXSEG5EI32_V_MF2_M1, + PseudoVLUXSEG5EI32_V_MF2_M1_MASK, + PseudoVLUXSEG5EI32_V_MF2_MF2, + PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG5EI32_V_MF2_MF4, + PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG5EI32_V_MF2_MF8, + PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG5EI64_V_M1_M1, + PseudoVLUXSEG5EI64_V_M1_M1_MASK, + PseudoVLUXSEG5EI64_V_M1_MF2, + PseudoVLUXSEG5EI64_V_M1_MF2_MASK, + PseudoVLUXSEG5EI64_V_M1_MF4, + PseudoVLUXSEG5EI64_V_M1_MF4_MASK, + PseudoVLUXSEG5EI64_V_M1_MF8, + PseudoVLUXSEG5EI64_V_M1_MF8_MASK, + PseudoVLUXSEG5EI64_V_M2_M1, + PseudoVLUXSEG5EI64_V_M2_M1_MASK, + PseudoVLUXSEG5EI64_V_M2_MF2, + PseudoVLUXSEG5EI64_V_M2_MF2_MASK, + PseudoVLUXSEG5EI64_V_M2_MF4, + PseudoVLUXSEG5EI64_V_M2_MF4_MASK, + PseudoVLUXSEG5EI64_V_M4_M1, + PseudoVLUXSEG5EI64_V_M4_M1_MASK, + PseudoVLUXSEG5EI64_V_M4_MF2, + PseudoVLUXSEG5EI64_V_M4_MF2_MASK, + PseudoVLUXSEG5EI64_V_M8_M1, + PseudoVLUXSEG5EI64_V_M8_M1_MASK, + PseudoVLUXSEG5EI8_V_M1_M1, + PseudoVLUXSEG5EI8_V_M1_M1_MASK, + PseudoVLUXSEG5EI8_V_MF2_M1, + PseudoVLUXSEG5EI8_V_MF2_M1_MASK, + PseudoVLUXSEG5EI8_V_MF2_MF2, + PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG5EI8_V_MF4_M1, + PseudoVLUXSEG5EI8_V_MF4_M1_MASK, + PseudoVLUXSEG5EI8_V_MF4_MF2, + PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG5EI8_V_MF4_MF4, + PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG5EI8_V_MF8_M1, + PseudoVLUXSEG5EI8_V_MF8_M1_MASK, + PseudoVLUXSEG5EI8_V_MF8_MF2, + PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG5EI8_V_MF8_MF4, + PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG5EI8_V_MF8_MF8, + PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG6EI16_V_M1_M1, + PseudoVLUXSEG6EI16_V_M1_M1_MASK, + PseudoVLUXSEG6EI16_V_M1_MF2, + PseudoVLUXSEG6EI16_V_M1_MF2_MASK, + PseudoVLUXSEG6EI16_V_M2_M1, + PseudoVLUXSEG6EI16_V_M2_M1_MASK, + PseudoVLUXSEG6EI16_V_MF2_M1, + PseudoVLUXSEG6EI16_V_MF2_M1_MASK, + PseudoVLUXSEG6EI16_V_MF2_MF2, + PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG6EI16_V_MF2_MF4, + PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG6EI16_V_MF4_M1, + PseudoVLUXSEG6EI16_V_MF4_M1_MASK, + PseudoVLUXSEG6EI16_V_MF4_MF2, + PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG6EI16_V_MF4_MF4, + PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG6EI16_V_MF4_MF8, + PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG6EI32_V_M1_M1, + PseudoVLUXSEG6EI32_V_M1_M1_MASK, + PseudoVLUXSEG6EI32_V_M1_MF2, + PseudoVLUXSEG6EI32_V_M1_MF2_MASK, + PseudoVLUXSEG6EI32_V_M1_MF4, + PseudoVLUXSEG6EI32_V_M1_MF4_MASK, + PseudoVLUXSEG6EI32_V_M2_M1, + PseudoVLUXSEG6EI32_V_M2_M1_MASK, + PseudoVLUXSEG6EI32_V_M2_MF2, + PseudoVLUXSEG6EI32_V_M2_MF2_MASK, + PseudoVLUXSEG6EI32_V_M4_M1, + PseudoVLUXSEG6EI32_V_M4_M1_MASK, + PseudoVLUXSEG6EI32_V_MF2_M1, + PseudoVLUXSEG6EI32_V_MF2_M1_MASK, + PseudoVLUXSEG6EI32_V_MF2_MF2, + PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG6EI32_V_MF2_MF4, + PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG6EI32_V_MF2_MF8, + PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG6EI64_V_M1_M1, + PseudoVLUXSEG6EI64_V_M1_M1_MASK, + PseudoVLUXSEG6EI64_V_M1_MF2, + PseudoVLUXSEG6EI64_V_M1_MF2_MASK, + PseudoVLUXSEG6EI64_V_M1_MF4, + PseudoVLUXSEG6EI64_V_M1_MF4_MASK, + PseudoVLUXSEG6EI64_V_M1_MF8, + PseudoVLUXSEG6EI64_V_M1_MF8_MASK, + PseudoVLUXSEG6EI64_V_M2_M1, + PseudoVLUXSEG6EI64_V_M2_M1_MASK, + PseudoVLUXSEG6EI64_V_M2_MF2, + PseudoVLUXSEG6EI64_V_M2_MF2_MASK, + PseudoVLUXSEG6EI64_V_M2_MF4, + PseudoVLUXSEG6EI64_V_M2_MF4_MASK, + PseudoVLUXSEG6EI64_V_M4_M1, + PseudoVLUXSEG6EI64_V_M4_M1_MASK, + PseudoVLUXSEG6EI64_V_M4_MF2, + PseudoVLUXSEG6EI64_V_M4_MF2_MASK, + PseudoVLUXSEG6EI64_V_M8_M1, + PseudoVLUXSEG6EI64_V_M8_M1_MASK, + PseudoVLUXSEG6EI8_V_M1_M1, + PseudoVLUXSEG6EI8_V_M1_M1_MASK, + PseudoVLUXSEG6EI8_V_MF2_M1, + PseudoVLUXSEG6EI8_V_MF2_M1_MASK, + PseudoVLUXSEG6EI8_V_MF2_MF2, + PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG6EI8_V_MF4_M1, + PseudoVLUXSEG6EI8_V_MF4_M1_MASK, + PseudoVLUXSEG6EI8_V_MF4_MF2, + PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG6EI8_V_MF4_MF4, + PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG6EI8_V_MF8_M1, + PseudoVLUXSEG6EI8_V_MF8_M1_MASK, + PseudoVLUXSEG6EI8_V_MF8_MF2, + PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG6EI8_V_MF8_MF4, + PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG6EI8_V_MF8_MF8, + PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG7EI16_V_M1_M1, + PseudoVLUXSEG7EI16_V_M1_M1_MASK, + PseudoVLUXSEG7EI16_V_M1_MF2, + PseudoVLUXSEG7EI16_V_M1_MF2_MASK, + PseudoVLUXSEG7EI16_V_M2_M1, + PseudoVLUXSEG7EI16_V_M2_M1_MASK, + PseudoVLUXSEG7EI16_V_MF2_M1, + PseudoVLUXSEG7EI16_V_MF2_M1_MASK, + PseudoVLUXSEG7EI16_V_MF2_MF2, + PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG7EI16_V_MF2_MF4, + PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG7EI16_V_MF4_M1, + PseudoVLUXSEG7EI16_V_MF4_M1_MASK, + PseudoVLUXSEG7EI16_V_MF4_MF2, + PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG7EI16_V_MF4_MF4, + PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG7EI16_V_MF4_MF8, + PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG7EI32_V_M1_M1, + PseudoVLUXSEG7EI32_V_M1_M1_MASK, + PseudoVLUXSEG7EI32_V_M1_MF2, + PseudoVLUXSEG7EI32_V_M1_MF2_MASK, + PseudoVLUXSEG7EI32_V_M1_MF4, + PseudoVLUXSEG7EI32_V_M1_MF4_MASK, + PseudoVLUXSEG7EI32_V_M2_M1, + PseudoVLUXSEG7EI32_V_M2_M1_MASK, + PseudoVLUXSEG7EI32_V_M2_MF2, + PseudoVLUXSEG7EI32_V_M2_MF2_MASK, + PseudoVLUXSEG7EI32_V_M4_M1, + PseudoVLUXSEG7EI32_V_M4_M1_MASK, + PseudoVLUXSEG7EI32_V_MF2_M1, + PseudoVLUXSEG7EI32_V_MF2_M1_MASK, + PseudoVLUXSEG7EI32_V_MF2_MF2, + PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG7EI32_V_MF2_MF4, + PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG7EI32_V_MF2_MF8, + PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG7EI64_V_M1_M1, + PseudoVLUXSEG7EI64_V_M1_M1_MASK, + PseudoVLUXSEG7EI64_V_M1_MF2, + PseudoVLUXSEG7EI64_V_M1_MF2_MASK, + PseudoVLUXSEG7EI64_V_M1_MF4, + PseudoVLUXSEG7EI64_V_M1_MF4_MASK, + PseudoVLUXSEG7EI64_V_M1_MF8, + PseudoVLUXSEG7EI64_V_M1_MF8_MASK, + PseudoVLUXSEG7EI64_V_M2_M1, + PseudoVLUXSEG7EI64_V_M2_M1_MASK, + PseudoVLUXSEG7EI64_V_M2_MF2, + PseudoVLUXSEG7EI64_V_M2_MF2_MASK, + PseudoVLUXSEG7EI64_V_M2_MF4, + PseudoVLUXSEG7EI64_V_M2_MF4_MASK, + PseudoVLUXSEG7EI64_V_M4_M1, + PseudoVLUXSEG7EI64_V_M4_M1_MASK, + PseudoVLUXSEG7EI64_V_M4_MF2, + PseudoVLUXSEG7EI64_V_M4_MF2_MASK, + PseudoVLUXSEG7EI64_V_M8_M1, + PseudoVLUXSEG7EI64_V_M8_M1_MASK, + PseudoVLUXSEG7EI8_V_M1_M1, + PseudoVLUXSEG7EI8_V_M1_M1_MASK, + PseudoVLUXSEG7EI8_V_MF2_M1, + PseudoVLUXSEG7EI8_V_MF2_M1_MASK, + PseudoVLUXSEG7EI8_V_MF2_MF2, + PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG7EI8_V_MF4_M1, + PseudoVLUXSEG7EI8_V_MF4_M1_MASK, + PseudoVLUXSEG7EI8_V_MF4_MF2, + PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG7EI8_V_MF4_MF4, + PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG7EI8_V_MF8_M1, + PseudoVLUXSEG7EI8_V_MF8_M1_MASK, + PseudoVLUXSEG7EI8_V_MF8_MF2, + PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG7EI8_V_MF8_MF4, + PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG7EI8_V_MF8_MF8, + PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, + PseudoVLUXSEG8EI16_V_M1_M1, + PseudoVLUXSEG8EI16_V_M1_M1_MASK, + PseudoVLUXSEG8EI16_V_M1_MF2, + PseudoVLUXSEG8EI16_V_M1_MF2_MASK, + PseudoVLUXSEG8EI16_V_M2_M1, + PseudoVLUXSEG8EI16_V_M2_M1_MASK, + PseudoVLUXSEG8EI16_V_MF2_M1, + PseudoVLUXSEG8EI16_V_MF2_M1_MASK, + PseudoVLUXSEG8EI16_V_MF2_MF2, + PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, + PseudoVLUXSEG8EI16_V_MF2_MF4, + PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, + PseudoVLUXSEG8EI16_V_MF4_M1, + PseudoVLUXSEG8EI16_V_MF4_M1_MASK, + PseudoVLUXSEG8EI16_V_MF4_MF2, + PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, + PseudoVLUXSEG8EI16_V_MF4_MF4, + PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, + PseudoVLUXSEG8EI16_V_MF4_MF8, + PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, + PseudoVLUXSEG8EI32_V_M1_M1, + PseudoVLUXSEG8EI32_V_M1_M1_MASK, + PseudoVLUXSEG8EI32_V_M1_MF2, + PseudoVLUXSEG8EI32_V_M1_MF2_MASK, + PseudoVLUXSEG8EI32_V_M1_MF4, + PseudoVLUXSEG8EI32_V_M1_MF4_MASK, + PseudoVLUXSEG8EI32_V_M2_M1, + PseudoVLUXSEG8EI32_V_M2_M1_MASK, + PseudoVLUXSEG8EI32_V_M2_MF2, + PseudoVLUXSEG8EI32_V_M2_MF2_MASK, + PseudoVLUXSEG8EI32_V_M4_M1, + PseudoVLUXSEG8EI32_V_M4_M1_MASK, + PseudoVLUXSEG8EI32_V_MF2_M1, + PseudoVLUXSEG8EI32_V_MF2_M1_MASK, + PseudoVLUXSEG8EI32_V_MF2_MF2, + PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, + PseudoVLUXSEG8EI32_V_MF2_MF4, + PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, + PseudoVLUXSEG8EI32_V_MF2_MF8, + PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, + PseudoVLUXSEG8EI64_V_M1_M1, + PseudoVLUXSEG8EI64_V_M1_M1_MASK, + PseudoVLUXSEG8EI64_V_M1_MF2, + PseudoVLUXSEG8EI64_V_M1_MF2_MASK, + PseudoVLUXSEG8EI64_V_M1_MF4, + PseudoVLUXSEG8EI64_V_M1_MF4_MASK, + PseudoVLUXSEG8EI64_V_M1_MF8, + PseudoVLUXSEG8EI64_V_M1_MF8_MASK, + PseudoVLUXSEG8EI64_V_M2_M1, + PseudoVLUXSEG8EI64_V_M2_M1_MASK, + PseudoVLUXSEG8EI64_V_M2_MF2, + PseudoVLUXSEG8EI64_V_M2_MF2_MASK, + PseudoVLUXSEG8EI64_V_M2_MF4, + PseudoVLUXSEG8EI64_V_M2_MF4_MASK, + PseudoVLUXSEG8EI64_V_M4_M1, + PseudoVLUXSEG8EI64_V_M4_M1_MASK, + PseudoVLUXSEG8EI64_V_M4_MF2, + PseudoVLUXSEG8EI64_V_M4_MF2_MASK, + PseudoVLUXSEG8EI64_V_M8_M1, + PseudoVLUXSEG8EI64_V_M8_M1_MASK, + PseudoVLUXSEG8EI8_V_M1_M1, + PseudoVLUXSEG8EI8_V_M1_M1_MASK, + PseudoVLUXSEG8EI8_V_MF2_M1, + PseudoVLUXSEG8EI8_V_MF2_M1_MASK, + PseudoVLUXSEG8EI8_V_MF2_MF2, + PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, + PseudoVLUXSEG8EI8_V_MF4_M1, + PseudoVLUXSEG8EI8_V_MF4_M1_MASK, + PseudoVLUXSEG8EI8_V_MF4_MF2, + PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, + PseudoVLUXSEG8EI8_V_MF4_MF4, + PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, + PseudoVLUXSEG8EI8_V_MF8_M1, + PseudoVLUXSEG8EI8_V_MF8_M1_MASK, + PseudoVLUXSEG8EI8_V_MF8_MF2, + PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, + PseudoVLUXSEG8EI8_V_MF8_MF4, + PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, + PseudoVLUXSEG8EI8_V_MF8_MF8, + PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, + PseudoVMACC_VV_M1, + PseudoVMACC_VV_M1_MASK, + PseudoVMACC_VV_M2, + PseudoVMACC_VV_M2_MASK, + PseudoVMACC_VV_M4, + PseudoVMACC_VV_M4_MASK, + PseudoVMACC_VV_M8, + PseudoVMACC_VV_M8_MASK, + PseudoVMACC_VV_MF2, + PseudoVMACC_VV_MF2_MASK, + PseudoVMACC_VV_MF4, + PseudoVMACC_VV_MF4_MASK, + PseudoVMACC_VV_MF8, + PseudoVMACC_VV_MF8_MASK, + PseudoVMACC_VX_M1, + PseudoVMACC_VX_M1_MASK, + PseudoVMACC_VX_M2, + PseudoVMACC_VX_M2_MASK, + PseudoVMACC_VX_M4, + PseudoVMACC_VX_M4_MASK, + PseudoVMACC_VX_M8, + PseudoVMACC_VX_M8_MASK, + PseudoVMACC_VX_MF2, + PseudoVMACC_VX_MF2_MASK, + PseudoVMACC_VX_MF4, + PseudoVMACC_VX_MF4_MASK, + PseudoVMACC_VX_MF8, + PseudoVMACC_VX_MF8_MASK, + PseudoVMADC_VIM_M1, + PseudoVMADC_VIM_M2, + PseudoVMADC_VIM_M4, + PseudoVMADC_VIM_M8, + PseudoVMADC_VIM_MF2, + PseudoVMADC_VIM_MF4, + PseudoVMADC_VIM_MF8, + PseudoVMADC_VI_M1, + PseudoVMADC_VI_M2, + PseudoVMADC_VI_M4, + PseudoVMADC_VI_M8, + PseudoVMADC_VI_MF2, + PseudoVMADC_VI_MF4, + PseudoVMADC_VI_MF8, + PseudoVMADC_VVM_M1, + PseudoVMADC_VVM_M2, + PseudoVMADC_VVM_M4, + PseudoVMADC_VVM_M8, + PseudoVMADC_VVM_MF2, + PseudoVMADC_VVM_MF4, + PseudoVMADC_VVM_MF8, + PseudoVMADC_VV_M1, + PseudoVMADC_VV_M2, + PseudoVMADC_VV_M4, + PseudoVMADC_VV_M8, + PseudoVMADC_VV_MF2, + PseudoVMADC_VV_MF4, + PseudoVMADC_VV_MF8, + PseudoVMADC_VXM_M1, + PseudoVMADC_VXM_M2, + PseudoVMADC_VXM_M4, + PseudoVMADC_VXM_M8, + PseudoVMADC_VXM_MF2, + PseudoVMADC_VXM_MF4, + PseudoVMADC_VXM_MF8, + PseudoVMADC_VX_M1, + PseudoVMADC_VX_M2, + PseudoVMADC_VX_M4, + PseudoVMADC_VX_M8, + PseudoVMADC_VX_MF2, + PseudoVMADC_VX_MF4, + PseudoVMADC_VX_MF8, + PseudoVMADD_VV_M1, + PseudoVMADD_VV_M1_MASK, + PseudoVMADD_VV_M2, + PseudoVMADD_VV_M2_MASK, + PseudoVMADD_VV_M4, + PseudoVMADD_VV_M4_MASK, + PseudoVMADD_VV_M8, + PseudoVMADD_VV_M8_MASK, + PseudoVMADD_VV_MF2, + PseudoVMADD_VV_MF2_MASK, + PseudoVMADD_VV_MF4, + PseudoVMADD_VV_MF4_MASK, + PseudoVMADD_VV_MF8, + PseudoVMADD_VV_MF8_MASK, + PseudoVMADD_VX_M1, + PseudoVMADD_VX_M1_MASK, + PseudoVMADD_VX_M2, + PseudoVMADD_VX_M2_MASK, + PseudoVMADD_VX_M4, + PseudoVMADD_VX_M4_MASK, + PseudoVMADD_VX_M8, + PseudoVMADD_VX_M8_MASK, + PseudoVMADD_VX_MF2, + PseudoVMADD_VX_MF2_MASK, + PseudoVMADD_VX_MF4, + PseudoVMADD_VX_MF4_MASK, + PseudoVMADD_VX_MF8, + PseudoVMADD_VX_MF8_MASK, + PseudoVMANDN_MM_B1, + PseudoVMANDN_MM_B16, + PseudoVMANDN_MM_B2, + PseudoVMANDN_MM_B32, + PseudoVMANDN_MM_B4, + PseudoVMANDN_MM_B64, + PseudoVMANDN_MM_B8, + PseudoVMAND_MM_B1, + PseudoVMAND_MM_B16, + PseudoVMAND_MM_B2, + PseudoVMAND_MM_B32, + PseudoVMAND_MM_B4, + PseudoVMAND_MM_B64, + PseudoVMAND_MM_B8, + PseudoVMAXU_VV_M1, + PseudoVMAXU_VV_M1_MASK, + PseudoVMAXU_VV_M2, + PseudoVMAXU_VV_M2_MASK, + PseudoVMAXU_VV_M4, + PseudoVMAXU_VV_M4_MASK, + PseudoVMAXU_VV_M8, + PseudoVMAXU_VV_M8_MASK, + PseudoVMAXU_VV_MF2, + PseudoVMAXU_VV_MF2_MASK, + PseudoVMAXU_VV_MF4, + PseudoVMAXU_VV_MF4_MASK, + PseudoVMAXU_VV_MF8, + PseudoVMAXU_VV_MF8_MASK, + PseudoVMAXU_VX_M1, + PseudoVMAXU_VX_M1_MASK, + PseudoVMAXU_VX_M2, + PseudoVMAXU_VX_M2_MASK, + PseudoVMAXU_VX_M4, + PseudoVMAXU_VX_M4_MASK, + PseudoVMAXU_VX_M8, + PseudoVMAXU_VX_M8_MASK, + PseudoVMAXU_VX_MF2, + PseudoVMAXU_VX_MF2_MASK, + PseudoVMAXU_VX_MF4, + PseudoVMAXU_VX_MF4_MASK, + PseudoVMAXU_VX_MF8, + PseudoVMAXU_VX_MF8_MASK, + PseudoVMAX_VV_M1, + PseudoVMAX_VV_M1_MASK, + PseudoVMAX_VV_M2, + PseudoVMAX_VV_M2_MASK, + PseudoVMAX_VV_M4, + PseudoVMAX_VV_M4_MASK, + PseudoVMAX_VV_M8, + PseudoVMAX_VV_M8_MASK, + PseudoVMAX_VV_MF2, + PseudoVMAX_VV_MF2_MASK, + PseudoVMAX_VV_MF4, + PseudoVMAX_VV_MF4_MASK, + PseudoVMAX_VV_MF8, + PseudoVMAX_VV_MF8_MASK, + PseudoVMAX_VX_M1, + PseudoVMAX_VX_M1_MASK, + PseudoVMAX_VX_M2, + PseudoVMAX_VX_M2_MASK, + PseudoVMAX_VX_M4, + PseudoVMAX_VX_M4_MASK, + PseudoVMAX_VX_M8, + PseudoVMAX_VX_M8_MASK, + PseudoVMAX_VX_MF2, + PseudoVMAX_VX_MF2_MASK, + PseudoVMAX_VX_MF4, + PseudoVMAX_VX_MF4_MASK, + PseudoVMAX_VX_MF8, + PseudoVMAX_VX_MF8_MASK, + PseudoVMCLR_M_B1, + PseudoVMCLR_M_B16, + PseudoVMCLR_M_B2, + PseudoVMCLR_M_B32, + PseudoVMCLR_M_B4, + PseudoVMCLR_M_B64, + PseudoVMCLR_M_B8, + PseudoVMERGE_VIM_M1, + PseudoVMERGE_VIM_M2, + PseudoVMERGE_VIM_M4, + PseudoVMERGE_VIM_M8, + PseudoVMERGE_VIM_MF2, + PseudoVMERGE_VIM_MF4, + PseudoVMERGE_VIM_MF8, + PseudoVMERGE_VVM_M1, + PseudoVMERGE_VVM_M2, + PseudoVMERGE_VVM_M4, + PseudoVMERGE_VVM_M8, + PseudoVMERGE_VVM_MF2, + PseudoVMERGE_VVM_MF4, + PseudoVMERGE_VVM_MF8, + PseudoVMERGE_VXM_M1, + PseudoVMERGE_VXM_M2, + PseudoVMERGE_VXM_M4, + PseudoVMERGE_VXM_M8, + PseudoVMERGE_VXM_MF2, + PseudoVMERGE_VXM_MF4, + PseudoVMERGE_VXM_MF8, + PseudoVMFEQ_ALT_VFPR16_M1, + PseudoVMFEQ_ALT_VFPR16_M1_MASK, + PseudoVMFEQ_ALT_VFPR16_M2, + PseudoVMFEQ_ALT_VFPR16_M2_MASK, + PseudoVMFEQ_ALT_VFPR16_M4, + PseudoVMFEQ_ALT_VFPR16_M4_MASK, + PseudoVMFEQ_ALT_VFPR16_M8, + PseudoVMFEQ_ALT_VFPR16_M8_MASK, + PseudoVMFEQ_ALT_VFPR16_MF2, + PseudoVMFEQ_ALT_VFPR16_MF2_MASK, + PseudoVMFEQ_ALT_VFPR16_MF4, + PseudoVMFEQ_ALT_VFPR16_MF4_MASK, + PseudoVMFEQ_ALT_VFPR32_M1, + PseudoVMFEQ_ALT_VFPR32_M1_MASK, + PseudoVMFEQ_ALT_VFPR32_M2, + PseudoVMFEQ_ALT_VFPR32_M2_MASK, + PseudoVMFEQ_ALT_VFPR32_M4, + PseudoVMFEQ_ALT_VFPR32_M4_MASK, + PseudoVMFEQ_ALT_VFPR32_M8, + PseudoVMFEQ_ALT_VFPR32_M8_MASK, + PseudoVMFEQ_ALT_VFPR32_MF2, + PseudoVMFEQ_ALT_VFPR32_MF2_MASK, + PseudoVMFEQ_ALT_VFPR64_M1, + PseudoVMFEQ_ALT_VFPR64_M1_MASK, + PseudoVMFEQ_ALT_VFPR64_M2, + PseudoVMFEQ_ALT_VFPR64_M2_MASK, + PseudoVMFEQ_ALT_VFPR64_M4, + PseudoVMFEQ_ALT_VFPR64_M4_MASK, + PseudoVMFEQ_ALT_VFPR64_M8, + PseudoVMFEQ_ALT_VFPR64_M8_MASK, + PseudoVMFEQ_ALT_VV_M1, + PseudoVMFEQ_ALT_VV_M1_MASK, + PseudoVMFEQ_ALT_VV_M2, + PseudoVMFEQ_ALT_VV_M2_MASK, + PseudoVMFEQ_ALT_VV_M4, + PseudoVMFEQ_ALT_VV_M4_MASK, + PseudoVMFEQ_ALT_VV_M8, + PseudoVMFEQ_ALT_VV_M8_MASK, + PseudoVMFEQ_ALT_VV_MF2, + PseudoVMFEQ_ALT_VV_MF2_MASK, + PseudoVMFEQ_ALT_VV_MF4, + PseudoVMFEQ_ALT_VV_MF4_MASK, + PseudoVMFEQ_VFPR16_M1, + PseudoVMFEQ_VFPR16_M1_MASK, + PseudoVMFEQ_VFPR16_M2, + PseudoVMFEQ_VFPR16_M2_MASK, + PseudoVMFEQ_VFPR16_M4, + PseudoVMFEQ_VFPR16_M4_MASK, + PseudoVMFEQ_VFPR16_M8, + PseudoVMFEQ_VFPR16_M8_MASK, + PseudoVMFEQ_VFPR16_MF2, + PseudoVMFEQ_VFPR16_MF2_MASK, + PseudoVMFEQ_VFPR16_MF4, + PseudoVMFEQ_VFPR16_MF4_MASK, + PseudoVMFEQ_VFPR32_M1, + PseudoVMFEQ_VFPR32_M1_MASK, + PseudoVMFEQ_VFPR32_M2, + PseudoVMFEQ_VFPR32_M2_MASK, + PseudoVMFEQ_VFPR32_M4, + PseudoVMFEQ_VFPR32_M4_MASK, + PseudoVMFEQ_VFPR32_M8, + PseudoVMFEQ_VFPR32_M8_MASK, + PseudoVMFEQ_VFPR32_MF2, + PseudoVMFEQ_VFPR32_MF2_MASK, + PseudoVMFEQ_VFPR64_M1, + PseudoVMFEQ_VFPR64_M1_MASK, + PseudoVMFEQ_VFPR64_M2, + PseudoVMFEQ_VFPR64_M2_MASK, + PseudoVMFEQ_VFPR64_M4, + PseudoVMFEQ_VFPR64_M4_MASK, + PseudoVMFEQ_VFPR64_M8, + PseudoVMFEQ_VFPR64_M8_MASK, + PseudoVMFEQ_VV_M1, + PseudoVMFEQ_VV_M1_MASK, + PseudoVMFEQ_VV_M2, + PseudoVMFEQ_VV_M2_MASK, + PseudoVMFEQ_VV_M4, + PseudoVMFEQ_VV_M4_MASK, + PseudoVMFEQ_VV_M8, + PseudoVMFEQ_VV_M8_MASK, + PseudoVMFEQ_VV_MF2, + PseudoVMFEQ_VV_MF2_MASK, + PseudoVMFEQ_VV_MF4, + PseudoVMFEQ_VV_MF4_MASK, + PseudoVMFGE_ALT_VFPR16_M1, + PseudoVMFGE_ALT_VFPR16_M1_MASK, + PseudoVMFGE_ALT_VFPR16_M2, + PseudoVMFGE_ALT_VFPR16_M2_MASK, + PseudoVMFGE_ALT_VFPR16_M4, + PseudoVMFGE_ALT_VFPR16_M4_MASK, + PseudoVMFGE_ALT_VFPR16_M8, + PseudoVMFGE_ALT_VFPR16_M8_MASK, + PseudoVMFGE_ALT_VFPR16_MF2, + PseudoVMFGE_ALT_VFPR16_MF2_MASK, + PseudoVMFGE_ALT_VFPR16_MF4, + PseudoVMFGE_ALT_VFPR16_MF4_MASK, + PseudoVMFGE_ALT_VFPR32_M1, + PseudoVMFGE_ALT_VFPR32_M1_MASK, + PseudoVMFGE_ALT_VFPR32_M2, + PseudoVMFGE_ALT_VFPR32_M2_MASK, + PseudoVMFGE_ALT_VFPR32_M4, + PseudoVMFGE_ALT_VFPR32_M4_MASK, + PseudoVMFGE_ALT_VFPR32_M8, + PseudoVMFGE_ALT_VFPR32_M8_MASK, + PseudoVMFGE_ALT_VFPR32_MF2, + PseudoVMFGE_ALT_VFPR32_MF2_MASK, + PseudoVMFGE_ALT_VFPR64_M1, + PseudoVMFGE_ALT_VFPR64_M1_MASK, + PseudoVMFGE_ALT_VFPR64_M2, + PseudoVMFGE_ALT_VFPR64_M2_MASK, + PseudoVMFGE_ALT_VFPR64_M4, + PseudoVMFGE_ALT_VFPR64_M4_MASK, + PseudoVMFGE_ALT_VFPR64_M8, + PseudoVMFGE_ALT_VFPR64_M8_MASK, + PseudoVMFGE_VFPR16_M1, + PseudoVMFGE_VFPR16_M1_MASK, + PseudoVMFGE_VFPR16_M2, + PseudoVMFGE_VFPR16_M2_MASK, + PseudoVMFGE_VFPR16_M4, + PseudoVMFGE_VFPR16_M4_MASK, + PseudoVMFGE_VFPR16_M8, + PseudoVMFGE_VFPR16_M8_MASK, + PseudoVMFGE_VFPR16_MF2, + PseudoVMFGE_VFPR16_MF2_MASK, + PseudoVMFGE_VFPR16_MF4, + PseudoVMFGE_VFPR16_MF4_MASK, + PseudoVMFGE_VFPR32_M1, + PseudoVMFGE_VFPR32_M1_MASK, + PseudoVMFGE_VFPR32_M2, + PseudoVMFGE_VFPR32_M2_MASK, + PseudoVMFGE_VFPR32_M4, + PseudoVMFGE_VFPR32_M4_MASK, + PseudoVMFGE_VFPR32_M8, + PseudoVMFGE_VFPR32_M8_MASK, + PseudoVMFGE_VFPR32_MF2, + PseudoVMFGE_VFPR32_MF2_MASK, + PseudoVMFGE_VFPR64_M1, + PseudoVMFGE_VFPR64_M1_MASK, + PseudoVMFGE_VFPR64_M2, + PseudoVMFGE_VFPR64_M2_MASK, + PseudoVMFGE_VFPR64_M4, + PseudoVMFGE_VFPR64_M4_MASK, + PseudoVMFGE_VFPR64_M8, + PseudoVMFGE_VFPR64_M8_MASK, + PseudoVMFGT_ALT_VFPR16_M1, + PseudoVMFGT_ALT_VFPR16_M1_MASK, + PseudoVMFGT_ALT_VFPR16_M2, + PseudoVMFGT_ALT_VFPR16_M2_MASK, + PseudoVMFGT_ALT_VFPR16_M4, + PseudoVMFGT_ALT_VFPR16_M4_MASK, + PseudoVMFGT_ALT_VFPR16_M8, + PseudoVMFGT_ALT_VFPR16_M8_MASK, + PseudoVMFGT_ALT_VFPR16_MF2, + PseudoVMFGT_ALT_VFPR16_MF2_MASK, + PseudoVMFGT_ALT_VFPR16_MF4, + PseudoVMFGT_ALT_VFPR16_MF4_MASK, + PseudoVMFGT_ALT_VFPR32_M1, + PseudoVMFGT_ALT_VFPR32_M1_MASK, + PseudoVMFGT_ALT_VFPR32_M2, + PseudoVMFGT_ALT_VFPR32_M2_MASK, + PseudoVMFGT_ALT_VFPR32_M4, + PseudoVMFGT_ALT_VFPR32_M4_MASK, + PseudoVMFGT_ALT_VFPR32_M8, + PseudoVMFGT_ALT_VFPR32_M8_MASK, + PseudoVMFGT_ALT_VFPR32_MF2, + PseudoVMFGT_ALT_VFPR32_MF2_MASK, + PseudoVMFGT_ALT_VFPR64_M1, + PseudoVMFGT_ALT_VFPR64_M1_MASK, + PseudoVMFGT_ALT_VFPR64_M2, + PseudoVMFGT_ALT_VFPR64_M2_MASK, + PseudoVMFGT_ALT_VFPR64_M4, + PseudoVMFGT_ALT_VFPR64_M4_MASK, + PseudoVMFGT_ALT_VFPR64_M8, + PseudoVMFGT_ALT_VFPR64_M8_MASK, + PseudoVMFGT_VFPR16_M1, + PseudoVMFGT_VFPR16_M1_MASK, + PseudoVMFGT_VFPR16_M2, + PseudoVMFGT_VFPR16_M2_MASK, + PseudoVMFGT_VFPR16_M4, + PseudoVMFGT_VFPR16_M4_MASK, + PseudoVMFGT_VFPR16_M8, + PseudoVMFGT_VFPR16_M8_MASK, + PseudoVMFGT_VFPR16_MF2, + PseudoVMFGT_VFPR16_MF2_MASK, + PseudoVMFGT_VFPR16_MF4, + PseudoVMFGT_VFPR16_MF4_MASK, + PseudoVMFGT_VFPR32_M1, + PseudoVMFGT_VFPR32_M1_MASK, + PseudoVMFGT_VFPR32_M2, + PseudoVMFGT_VFPR32_M2_MASK, + PseudoVMFGT_VFPR32_M4, + PseudoVMFGT_VFPR32_M4_MASK, + PseudoVMFGT_VFPR32_M8, + PseudoVMFGT_VFPR32_M8_MASK, + PseudoVMFGT_VFPR32_MF2, + PseudoVMFGT_VFPR32_MF2_MASK, + PseudoVMFGT_VFPR64_M1, + PseudoVMFGT_VFPR64_M1_MASK, + PseudoVMFGT_VFPR64_M2, + PseudoVMFGT_VFPR64_M2_MASK, + PseudoVMFGT_VFPR64_M4, + PseudoVMFGT_VFPR64_M4_MASK, + PseudoVMFGT_VFPR64_M8, + PseudoVMFGT_VFPR64_M8_MASK, + PseudoVMFLE_ALT_VFPR16_M1, + PseudoVMFLE_ALT_VFPR16_M1_MASK, + PseudoVMFLE_ALT_VFPR16_M2, + PseudoVMFLE_ALT_VFPR16_M2_MASK, + PseudoVMFLE_ALT_VFPR16_M4, + PseudoVMFLE_ALT_VFPR16_M4_MASK, + PseudoVMFLE_ALT_VFPR16_M8, + PseudoVMFLE_ALT_VFPR16_M8_MASK, + PseudoVMFLE_ALT_VFPR16_MF2, + PseudoVMFLE_ALT_VFPR16_MF2_MASK, + PseudoVMFLE_ALT_VFPR16_MF4, + PseudoVMFLE_ALT_VFPR16_MF4_MASK, + PseudoVMFLE_ALT_VFPR32_M1, + PseudoVMFLE_ALT_VFPR32_M1_MASK, + PseudoVMFLE_ALT_VFPR32_M2, + PseudoVMFLE_ALT_VFPR32_M2_MASK, + PseudoVMFLE_ALT_VFPR32_M4, + PseudoVMFLE_ALT_VFPR32_M4_MASK, + PseudoVMFLE_ALT_VFPR32_M8, + PseudoVMFLE_ALT_VFPR32_M8_MASK, + PseudoVMFLE_ALT_VFPR32_MF2, + PseudoVMFLE_ALT_VFPR32_MF2_MASK, + PseudoVMFLE_ALT_VFPR64_M1, + PseudoVMFLE_ALT_VFPR64_M1_MASK, + PseudoVMFLE_ALT_VFPR64_M2, + PseudoVMFLE_ALT_VFPR64_M2_MASK, + PseudoVMFLE_ALT_VFPR64_M4, + PseudoVMFLE_ALT_VFPR64_M4_MASK, + PseudoVMFLE_ALT_VFPR64_M8, + PseudoVMFLE_ALT_VFPR64_M8_MASK, + PseudoVMFLE_ALT_VV_M1, + PseudoVMFLE_ALT_VV_M1_MASK, + PseudoVMFLE_ALT_VV_M2, + PseudoVMFLE_ALT_VV_M2_MASK, + PseudoVMFLE_ALT_VV_M4, + PseudoVMFLE_ALT_VV_M4_MASK, + PseudoVMFLE_ALT_VV_M8, + PseudoVMFLE_ALT_VV_M8_MASK, + PseudoVMFLE_ALT_VV_MF2, + PseudoVMFLE_ALT_VV_MF2_MASK, + PseudoVMFLE_ALT_VV_MF4, + PseudoVMFLE_ALT_VV_MF4_MASK, + PseudoVMFLE_VFPR16_M1, + PseudoVMFLE_VFPR16_M1_MASK, + PseudoVMFLE_VFPR16_M2, + PseudoVMFLE_VFPR16_M2_MASK, + PseudoVMFLE_VFPR16_M4, + PseudoVMFLE_VFPR16_M4_MASK, + PseudoVMFLE_VFPR16_M8, + PseudoVMFLE_VFPR16_M8_MASK, + PseudoVMFLE_VFPR16_MF2, + PseudoVMFLE_VFPR16_MF2_MASK, + PseudoVMFLE_VFPR16_MF4, + PseudoVMFLE_VFPR16_MF4_MASK, + PseudoVMFLE_VFPR32_M1, + PseudoVMFLE_VFPR32_M1_MASK, + PseudoVMFLE_VFPR32_M2, + PseudoVMFLE_VFPR32_M2_MASK, + PseudoVMFLE_VFPR32_M4, + PseudoVMFLE_VFPR32_M4_MASK, + PseudoVMFLE_VFPR32_M8, + PseudoVMFLE_VFPR32_M8_MASK, + PseudoVMFLE_VFPR32_MF2, + PseudoVMFLE_VFPR32_MF2_MASK, + PseudoVMFLE_VFPR64_M1, + PseudoVMFLE_VFPR64_M1_MASK, + PseudoVMFLE_VFPR64_M2, + PseudoVMFLE_VFPR64_M2_MASK, + PseudoVMFLE_VFPR64_M4, + PseudoVMFLE_VFPR64_M4_MASK, + PseudoVMFLE_VFPR64_M8, + PseudoVMFLE_VFPR64_M8_MASK, + PseudoVMFLE_VV_M1, + PseudoVMFLE_VV_M1_MASK, + PseudoVMFLE_VV_M2, + PseudoVMFLE_VV_M2_MASK, + PseudoVMFLE_VV_M4, + PseudoVMFLE_VV_M4_MASK, + PseudoVMFLE_VV_M8, + PseudoVMFLE_VV_M8_MASK, + PseudoVMFLE_VV_MF2, + PseudoVMFLE_VV_MF2_MASK, + PseudoVMFLE_VV_MF4, + PseudoVMFLE_VV_MF4_MASK, + PseudoVMFLT_ALT_VFPR16_M1, + PseudoVMFLT_ALT_VFPR16_M1_MASK, + PseudoVMFLT_ALT_VFPR16_M2, + PseudoVMFLT_ALT_VFPR16_M2_MASK, + PseudoVMFLT_ALT_VFPR16_M4, + PseudoVMFLT_ALT_VFPR16_M4_MASK, + PseudoVMFLT_ALT_VFPR16_M8, + PseudoVMFLT_ALT_VFPR16_M8_MASK, + PseudoVMFLT_ALT_VFPR16_MF2, + PseudoVMFLT_ALT_VFPR16_MF2_MASK, + PseudoVMFLT_ALT_VFPR16_MF4, + PseudoVMFLT_ALT_VFPR16_MF4_MASK, + PseudoVMFLT_ALT_VFPR32_M1, + PseudoVMFLT_ALT_VFPR32_M1_MASK, + PseudoVMFLT_ALT_VFPR32_M2, + PseudoVMFLT_ALT_VFPR32_M2_MASK, + PseudoVMFLT_ALT_VFPR32_M4, + PseudoVMFLT_ALT_VFPR32_M4_MASK, + PseudoVMFLT_ALT_VFPR32_M8, + PseudoVMFLT_ALT_VFPR32_M8_MASK, + PseudoVMFLT_ALT_VFPR32_MF2, + PseudoVMFLT_ALT_VFPR32_MF2_MASK, + PseudoVMFLT_ALT_VFPR64_M1, + PseudoVMFLT_ALT_VFPR64_M1_MASK, + PseudoVMFLT_ALT_VFPR64_M2, + PseudoVMFLT_ALT_VFPR64_M2_MASK, + PseudoVMFLT_ALT_VFPR64_M4, + PseudoVMFLT_ALT_VFPR64_M4_MASK, + PseudoVMFLT_ALT_VFPR64_M8, + PseudoVMFLT_ALT_VFPR64_M8_MASK, + PseudoVMFLT_ALT_VV_M1, + PseudoVMFLT_ALT_VV_M1_MASK, + PseudoVMFLT_ALT_VV_M2, + PseudoVMFLT_ALT_VV_M2_MASK, + PseudoVMFLT_ALT_VV_M4, + PseudoVMFLT_ALT_VV_M4_MASK, + PseudoVMFLT_ALT_VV_M8, + PseudoVMFLT_ALT_VV_M8_MASK, + PseudoVMFLT_ALT_VV_MF2, + PseudoVMFLT_ALT_VV_MF2_MASK, + PseudoVMFLT_ALT_VV_MF4, + PseudoVMFLT_ALT_VV_MF4_MASK, + PseudoVMFLT_VFPR16_M1, + PseudoVMFLT_VFPR16_M1_MASK, + PseudoVMFLT_VFPR16_M2, + PseudoVMFLT_VFPR16_M2_MASK, + PseudoVMFLT_VFPR16_M4, + PseudoVMFLT_VFPR16_M4_MASK, + PseudoVMFLT_VFPR16_M8, + PseudoVMFLT_VFPR16_M8_MASK, + PseudoVMFLT_VFPR16_MF2, + PseudoVMFLT_VFPR16_MF2_MASK, + PseudoVMFLT_VFPR16_MF4, + PseudoVMFLT_VFPR16_MF4_MASK, + PseudoVMFLT_VFPR32_M1, + PseudoVMFLT_VFPR32_M1_MASK, + PseudoVMFLT_VFPR32_M2, + PseudoVMFLT_VFPR32_M2_MASK, + PseudoVMFLT_VFPR32_M4, + PseudoVMFLT_VFPR32_M4_MASK, + PseudoVMFLT_VFPR32_M8, + PseudoVMFLT_VFPR32_M8_MASK, + PseudoVMFLT_VFPR32_MF2, + PseudoVMFLT_VFPR32_MF2_MASK, + PseudoVMFLT_VFPR64_M1, + PseudoVMFLT_VFPR64_M1_MASK, + PseudoVMFLT_VFPR64_M2, + PseudoVMFLT_VFPR64_M2_MASK, + PseudoVMFLT_VFPR64_M4, + PseudoVMFLT_VFPR64_M4_MASK, + PseudoVMFLT_VFPR64_M8, + PseudoVMFLT_VFPR64_M8_MASK, + PseudoVMFLT_VV_M1, + PseudoVMFLT_VV_M1_MASK, + PseudoVMFLT_VV_M2, + PseudoVMFLT_VV_M2_MASK, + PseudoVMFLT_VV_M4, + PseudoVMFLT_VV_M4_MASK, + PseudoVMFLT_VV_M8, + PseudoVMFLT_VV_M8_MASK, + PseudoVMFLT_VV_MF2, + PseudoVMFLT_VV_MF2_MASK, + PseudoVMFLT_VV_MF4, + PseudoVMFLT_VV_MF4_MASK, + PseudoVMFNE_ALT_VFPR16_M1, + PseudoVMFNE_ALT_VFPR16_M1_MASK, + PseudoVMFNE_ALT_VFPR16_M2, + PseudoVMFNE_ALT_VFPR16_M2_MASK, + PseudoVMFNE_ALT_VFPR16_M4, + PseudoVMFNE_ALT_VFPR16_M4_MASK, + PseudoVMFNE_ALT_VFPR16_M8, + PseudoVMFNE_ALT_VFPR16_M8_MASK, + PseudoVMFNE_ALT_VFPR16_MF2, + PseudoVMFNE_ALT_VFPR16_MF2_MASK, + PseudoVMFNE_ALT_VFPR16_MF4, + PseudoVMFNE_ALT_VFPR16_MF4_MASK, + PseudoVMFNE_ALT_VFPR32_M1, + PseudoVMFNE_ALT_VFPR32_M1_MASK, + PseudoVMFNE_ALT_VFPR32_M2, + PseudoVMFNE_ALT_VFPR32_M2_MASK, + PseudoVMFNE_ALT_VFPR32_M4, + PseudoVMFNE_ALT_VFPR32_M4_MASK, + PseudoVMFNE_ALT_VFPR32_M8, + PseudoVMFNE_ALT_VFPR32_M8_MASK, + PseudoVMFNE_ALT_VFPR32_MF2, + PseudoVMFNE_ALT_VFPR32_MF2_MASK, + PseudoVMFNE_ALT_VFPR64_M1, + PseudoVMFNE_ALT_VFPR64_M1_MASK, + PseudoVMFNE_ALT_VFPR64_M2, + PseudoVMFNE_ALT_VFPR64_M2_MASK, + PseudoVMFNE_ALT_VFPR64_M4, + PseudoVMFNE_ALT_VFPR64_M4_MASK, + PseudoVMFNE_ALT_VFPR64_M8, + PseudoVMFNE_ALT_VFPR64_M8_MASK, + PseudoVMFNE_ALT_VV_M1, + PseudoVMFNE_ALT_VV_M1_MASK, + PseudoVMFNE_ALT_VV_M2, + PseudoVMFNE_ALT_VV_M2_MASK, + PseudoVMFNE_ALT_VV_M4, + PseudoVMFNE_ALT_VV_M4_MASK, + PseudoVMFNE_ALT_VV_M8, + PseudoVMFNE_ALT_VV_M8_MASK, + PseudoVMFNE_ALT_VV_MF2, + PseudoVMFNE_ALT_VV_MF2_MASK, + PseudoVMFNE_ALT_VV_MF4, + PseudoVMFNE_ALT_VV_MF4_MASK, + PseudoVMFNE_VFPR16_M1, + PseudoVMFNE_VFPR16_M1_MASK, + PseudoVMFNE_VFPR16_M2, + PseudoVMFNE_VFPR16_M2_MASK, + PseudoVMFNE_VFPR16_M4, + PseudoVMFNE_VFPR16_M4_MASK, + PseudoVMFNE_VFPR16_M8, + PseudoVMFNE_VFPR16_M8_MASK, + PseudoVMFNE_VFPR16_MF2, + PseudoVMFNE_VFPR16_MF2_MASK, + PseudoVMFNE_VFPR16_MF4, + PseudoVMFNE_VFPR16_MF4_MASK, + PseudoVMFNE_VFPR32_M1, + PseudoVMFNE_VFPR32_M1_MASK, + PseudoVMFNE_VFPR32_M2, + PseudoVMFNE_VFPR32_M2_MASK, + PseudoVMFNE_VFPR32_M4, + PseudoVMFNE_VFPR32_M4_MASK, + PseudoVMFNE_VFPR32_M8, + PseudoVMFNE_VFPR32_M8_MASK, + PseudoVMFNE_VFPR32_MF2, + PseudoVMFNE_VFPR32_MF2_MASK, + PseudoVMFNE_VFPR64_M1, + PseudoVMFNE_VFPR64_M1_MASK, + PseudoVMFNE_VFPR64_M2, + PseudoVMFNE_VFPR64_M2_MASK, + PseudoVMFNE_VFPR64_M4, + PseudoVMFNE_VFPR64_M4_MASK, + PseudoVMFNE_VFPR64_M8, + PseudoVMFNE_VFPR64_M8_MASK, + PseudoVMFNE_VV_M1, + PseudoVMFNE_VV_M1_MASK, + PseudoVMFNE_VV_M2, + PseudoVMFNE_VV_M2_MASK, + PseudoVMFNE_VV_M4, + PseudoVMFNE_VV_M4_MASK, + PseudoVMFNE_VV_M8, + PseudoVMFNE_VV_M8_MASK, + PseudoVMFNE_VV_MF2, + PseudoVMFNE_VV_MF2_MASK, + PseudoVMFNE_VV_MF4, + PseudoVMFNE_VV_MF4_MASK, + PseudoVMINU_VV_M1, + PseudoVMINU_VV_M1_MASK, + PseudoVMINU_VV_M2, + PseudoVMINU_VV_M2_MASK, + PseudoVMINU_VV_M4, + PseudoVMINU_VV_M4_MASK, + PseudoVMINU_VV_M8, + PseudoVMINU_VV_M8_MASK, + PseudoVMINU_VV_MF2, + PseudoVMINU_VV_MF2_MASK, + PseudoVMINU_VV_MF4, + PseudoVMINU_VV_MF4_MASK, + PseudoVMINU_VV_MF8, + PseudoVMINU_VV_MF8_MASK, + PseudoVMINU_VX_M1, + PseudoVMINU_VX_M1_MASK, + PseudoVMINU_VX_M2, + PseudoVMINU_VX_M2_MASK, + PseudoVMINU_VX_M4, + PseudoVMINU_VX_M4_MASK, + PseudoVMINU_VX_M8, + PseudoVMINU_VX_M8_MASK, + PseudoVMINU_VX_MF2, + PseudoVMINU_VX_MF2_MASK, + PseudoVMINU_VX_MF4, + PseudoVMINU_VX_MF4_MASK, + PseudoVMINU_VX_MF8, + PseudoVMINU_VX_MF8_MASK, + PseudoVMIN_VV_M1, + PseudoVMIN_VV_M1_MASK, + PseudoVMIN_VV_M2, + PseudoVMIN_VV_M2_MASK, + PseudoVMIN_VV_M4, + PseudoVMIN_VV_M4_MASK, + PseudoVMIN_VV_M8, + PseudoVMIN_VV_M8_MASK, + PseudoVMIN_VV_MF2, + PseudoVMIN_VV_MF2_MASK, + PseudoVMIN_VV_MF4, + PseudoVMIN_VV_MF4_MASK, + PseudoVMIN_VV_MF8, + PseudoVMIN_VV_MF8_MASK, + PseudoVMIN_VX_M1, + PseudoVMIN_VX_M1_MASK, + PseudoVMIN_VX_M2, + PseudoVMIN_VX_M2_MASK, + PseudoVMIN_VX_M4, + PseudoVMIN_VX_M4_MASK, + PseudoVMIN_VX_M8, + PseudoVMIN_VX_M8_MASK, + PseudoVMIN_VX_MF2, + PseudoVMIN_VX_MF2_MASK, + PseudoVMIN_VX_MF4, + PseudoVMIN_VX_MF4_MASK, + PseudoVMIN_VX_MF8, + PseudoVMIN_VX_MF8_MASK, + PseudoVMNAND_MM_B1, + PseudoVMNAND_MM_B16, + PseudoVMNAND_MM_B2, + PseudoVMNAND_MM_B32, + PseudoVMNAND_MM_B4, + PseudoVMNAND_MM_B64, + PseudoVMNAND_MM_B8, + PseudoVMNOR_MM_B1, + PseudoVMNOR_MM_B16, + PseudoVMNOR_MM_B2, + PseudoVMNOR_MM_B32, + PseudoVMNOR_MM_B4, + PseudoVMNOR_MM_B64, + PseudoVMNOR_MM_B8, + PseudoVMORN_MM_B1, + PseudoVMORN_MM_B16, + PseudoVMORN_MM_B2, + PseudoVMORN_MM_B32, + PseudoVMORN_MM_B4, + PseudoVMORN_MM_B64, + PseudoVMORN_MM_B8, + PseudoVMOR_MM_B1, + PseudoVMOR_MM_B16, + PseudoVMOR_MM_B2, + PseudoVMOR_MM_B32, + PseudoVMOR_MM_B4, + PseudoVMOR_MM_B64, + PseudoVMOR_MM_B8, + PseudoVMSBC_VVM_M1, + PseudoVMSBC_VVM_M2, + PseudoVMSBC_VVM_M4, + PseudoVMSBC_VVM_M8, + PseudoVMSBC_VVM_MF2, + PseudoVMSBC_VVM_MF4, + PseudoVMSBC_VVM_MF8, + PseudoVMSBC_VV_M1, + PseudoVMSBC_VV_M2, + PseudoVMSBC_VV_M4, + PseudoVMSBC_VV_M8, + PseudoVMSBC_VV_MF2, + PseudoVMSBC_VV_MF4, + PseudoVMSBC_VV_MF8, + PseudoVMSBC_VXM_M1, + PseudoVMSBC_VXM_M2, + PseudoVMSBC_VXM_M4, + PseudoVMSBC_VXM_M8, + PseudoVMSBC_VXM_MF2, + PseudoVMSBC_VXM_MF4, + PseudoVMSBC_VXM_MF8, + PseudoVMSBC_VX_M1, + PseudoVMSBC_VX_M2, + PseudoVMSBC_VX_M4, + PseudoVMSBC_VX_M8, + PseudoVMSBC_VX_MF2, + PseudoVMSBC_VX_MF4, + PseudoVMSBC_VX_MF8, + PseudoVMSBF_M_B1, + PseudoVMSBF_M_B16, + PseudoVMSBF_M_B16_MASK, + PseudoVMSBF_M_B1_MASK, + PseudoVMSBF_M_B2, + PseudoVMSBF_M_B2_MASK, + PseudoVMSBF_M_B32, + PseudoVMSBF_M_B32_MASK, + PseudoVMSBF_M_B4, + PseudoVMSBF_M_B4_MASK, + PseudoVMSBF_M_B64, + PseudoVMSBF_M_B64_MASK, + PseudoVMSBF_M_B8, + PseudoVMSBF_M_B8_MASK, + PseudoVMSEQ_VI_M1, + PseudoVMSEQ_VI_M1_MASK, + PseudoVMSEQ_VI_M2, + PseudoVMSEQ_VI_M2_MASK, + PseudoVMSEQ_VI_M4, + PseudoVMSEQ_VI_M4_MASK, + PseudoVMSEQ_VI_M8, + PseudoVMSEQ_VI_M8_MASK, + PseudoVMSEQ_VI_MF2, + PseudoVMSEQ_VI_MF2_MASK, + PseudoVMSEQ_VI_MF4, + PseudoVMSEQ_VI_MF4_MASK, + PseudoVMSEQ_VI_MF8, + PseudoVMSEQ_VI_MF8_MASK, + PseudoVMSEQ_VV_M1, + PseudoVMSEQ_VV_M1_MASK, + PseudoVMSEQ_VV_M2, + PseudoVMSEQ_VV_M2_MASK, + PseudoVMSEQ_VV_M4, + PseudoVMSEQ_VV_M4_MASK, + PseudoVMSEQ_VV_M8, + PseudoVMSEQ_VV_M8_MASK, + PseudoVMSEQ_VV_MF2, + PseudoVMSEQ_VV_MF2_MASK, + PseudoVMSEQ_VV_MF4, + PseudoVMSEQ_VV_MF4_MASK, + PseudoVMSEQ_VV_MF8, + PseudoVMSEQ_VV_MF8_MASK, + PseudoVMSEQ_VX_M1, + PseudoVMSEQ_VX_M1_MASK, + PseudoVMSEQ_VX_M2, + PseudoVMSEQ_VX_M2_MASK, + PseudoVMSEQ_VX_M4, + PseudoVMSEQ_VX_M4_MASK, + PseudoVMSEQ_VX_M8, + PseudoVMSEQ_VX_M8_MASK, + PseudoVMSEQ_VX_MF2, + PseudoVMSEQ_VX_MF2_MASK, + PseudoVMSEQ_VX_MF4, + PseudoVMSEQ_VX_MF4_MASK, + PseudoVMSEQ_VX_MF8, + PseudoVMSEQ_VX_MF8_MASK, + PseudoVMSET_M_B1, + PseudoVMSET_M_B16, + PseudoVMSET_M_B2, + PseudoVMSET_M_B32, + PseudoVMSET_M_B4, + PseudoVMSET_M_B64, + PseudoVMSET_M_B8, + PseudoVMSGEU_VI, + PseudoVMSGEU_VX, + PseudoVMSGEU_VX_M, + PseudoVMSGEU_VX_M_T, + PseudoVMSGE_VI, + PseudoVMSGE_VX, + PseudoVMSGE_VX_M, + PseudoVMSGE_VX_M_T, + PseudoVMSGTU_VI_M1, + PseudoVMSGTU_VI_M1_MASK, + PseudoVMSGTU_VI_M2, + PseudoVMSGTU_VI_M2_MASK, + PseudoVMSGTU_VI_M4, + PseudoVMSGTU_VI_M4_MASK, + PseudoVMSGTU_VI_M8, + PseudoVMSGTU_VI_M8_MASK, + PseudoVMSGTU_VI_MF2, + PseudoVMSGTU_VI_MF2_MASK, + PseudoVMSGTU_VI_MF4, + PseudoVMSGTU_VI_MF4_MASK, + PseudoVMSGTU_VI_MF8, + PseudoVMSGTU_VI_MF8_MASK, + PseudoVMSGTU_VX_M1, + PseudoVMSGTU_VX_M1_MASK, + PseudoVMSGTU_VX_M2, + PseudoVMSGTU_VX_M2_MASK, + PseudoVMSGTU_VX_M4, + PseudoVMSGTU_VX_M4_MASK, + PseudoVMSGTU_VX_M8, + PseudoVMSGTU_VX_M8_MASK, + PseudoVMSGTU_VX_MF2, + PseudoVMSGTU_VX_MF2_MASK, + PseudoVMSGTU_VX_MF4, + PseudoVMSGTU_VX_MF4_MASK, + PseudoVMSGTU_VX_MF8, + PseudoVMSGTU_VX_MF8_MASK, + PseudoVMSGT_VI_M1, + PseudoVMSGT_VI_M1_MASK, + PseudoVMSGT_VI_M2, + PseudoVMSGT_VI_M2_MASK, + PseudoVMSGT_VI_M4, + PseudoVMSGT_VI_M4_MASK, + PseudoVMSGT_VI_M8, + PseudoVMSGT_VI_M8_MASK, + PseudoVMSGT_VI_MF2, + PseudoVMSGT_VI_MF2_MASK, + PseudoVMSGT_VI_MF4, + PseudoVMSGT_VI_MF4_MASK, + PseudoVMSGT_VI_MF8, + PseudoVMSGT_VI_MF8_MASK, + PseudoVMSGT_VX_M1, + PseudoVMSGT_VX_M1_MASK, + PseudoVMSGT_VX_M2, + PseudoVMSGT_VX_M2_MASK, + PseudoVMSGT_VX_M4, + PseudoVMSGT_VX_M4_MASK, + PseudoVMSGT_VX_M8, + PseudoVMSGT_VX_M8_MASK, + PseudoVMSGT_VX_MF2, + PseudoVMSGT_VX_MF2_MASK, + PseudoVMSGT_VX_MF4, + PseudoVMSGT_VX_MF4_MASK, + PseudoVMSGT_VX_MF8, + PseudoVMSGT_VX_MF8_MASK, + PseudoVMSIF_M_B1, + PseudoVMSIF_M_B16, + PseudoVMSIF_M_B16_MASK, + PseudoVMSIF_M_B1_MASK, + PseudoVMSIF_M_B2, + PseudoVMSIF_M_B2_MASK, + PseudoVMSIF_M_B32, + PseudoVMSIF_M_B32_MASK, + PseudoVMSIF_M_B4, + PseudoVMSIF_M_B4_MASK, + PseudoVMSIF_M_B64, + PseudoVMSIF_M_B64_MASK, + PseudoVMSIF_M_B8, + PseudoVMSIF_M_B8_MASK, + PseudoVMSLEU_VI_M1, + PseudoVMSLEU_VI_M1_MASK, + PseudoVMSLEU_VI_M2, + PseudoVMSLEU_VI_M2_MASK, + PseudoVMSLEU_VI_M4, + PseudoVMSLEU_VI_M4_MASK, + PseudoVMSLEU_VI_M8, + PseudoVMSLEU_VI_M8_MASK, + PseudoVMSLEU_VI_MF2, + PseudoVMSLEU_VI_MF2_MASK, + PseudoVMSLEU_VI_MF4, + PseudoVMSLEU_VI_MF4_MASK, + PseudoVMSLEU_VI_MF8, + PseudoVMSLEU_VI_MF8_MASK, + PseudoVMSLEU_VV_M1, + PseudoVMSLEU_VV_M1_MASK, + PseudoVMSLEU_VV_M2, + PseudoVMSLEU_VV_M2_MASK, + PseudoVMSLEU_VV_M4, + PseudoVMSLEU_VV_M4_MASK, + PseudoVMSLEU_VV_M8, + PseudoVMSLEU_VV_M8_MASK, + PseudoVMSLEU_VV_MF2, + PseudoVMSLEU_VV_MF2_MASK, + PseudoVMSLEU_VV_MF4, + PseudoVMSLEU_VV_MF4_MASK, + PseudoVMSLEU_VV_MF8, + PseudoVMSLEU_VV_MF8_MASK, + PseudoVMSLEU_VX_M1, + PseudoVMSLEU_VX_M1_MASK, + PseudoVMSLEU_VX_M2, + PseudoVMSLEU_VX_M2_MASK, + PseudoVMSLEU_VX_M4, + PseudoVMSLEU_VX_M4_MASK, + PseudoVMSLEU_VX_M8, + PseudoVMSLEU_VX_M8_MASK, + PseudoVMSLEU_VX_MF2, + PseudoVMSLEU_VX_MF2_MASK, + PseudoVMSLEU_VX_MF4, + PseudoVMSLEU_VX_MF4_MASK, + PseudoVMSLEU_VX_MF8, + PseudoVMSLEU_VX_MF8_MASK, + PseudoVMSLE_VI_M1, + PseudoVMSLE_VI_M1_MASK, + PseudoVMSLE_VI_M2, + PseudoVMSLE_VI_M2_MASK, + PseudoVMSLE_VI_M4, + PseudoVMSLE_VI_M4_MASK, + PseudoVMSLE_VI_M8, + PseudoVMSLE_VI_M8_MASK, + PseudoVMSLE_VI_MF2, + PseudoVMSLE_VI_MF2_MASK, + PseudoVMSLE_VI_MF4, + PseudoVMSLE_VI_MF4_MASK, + PseudoVMSLE_VI_MF8, + PseudoVMSLE_VI_MF8_MASK, + PseudoVMSLE_VV_M1, + PseudoVMSLE_VV_M1_MASK, + PseudoVMSLE_VV_M2, + PseudoVMSLE_VV_M2_MASK, + PseudoVMSLE_VV_M4, + PseudoVMSLE_VV_M4_MASK, + PseudoVMSLE_VV_M8, + PseudoVMSLE_VV_M8_MASK, + PseudoVMSLE_VV_MF2, + PseudoVMSLE_VV_MF2_MASK, + PseudoVMSLE_VV_MF4, + PseudoVMSLE_VV_MF4_MASK, + PseudoVMSLE_VV_MF8, + PseudoVMSLE_VV_MF8_MASK, + PseudoVMSLE_VX_M1, + PseudoVMSLE_VX_M1_MASK, + PseudoVMSLE_VX_M2, + PseudoVMSLE_VX_M2_MASK, + PseudoVMSLE_VX_M4, + PseudoVMSLE_VX_M4_MASK, + PseudoVMSLE_VX_M8, + PseudoVMSLE_VX_M8_MASK, + PseudoVMSLE_VX_MF2, + PseudoVMSLE_VX_MF2_MASK, + PseudoVMSLE_VX_MF4, + PseudoVMSLE_VX_MF4_MASK, + PseudoVMSLE_VX_MF8, + PseudoVMSLE_VX_MF8_MASK, + PseudoVMSLTU_VI, + PseudoVMSLTU_VV_M1, + PseudoVMSLTU_VV_M1_MASK, + PseudoVMSLTU_VV_M2, + PseudoVMSLTU_VV_M2_MASK, + PseudoVMSLTU_VV_M4, + PseudoVMSLTU_VV_M4_MASK, + PseudoVMSLTU_VV_M8, + PseudoVMSLTU_VV_M8_MASK, + PseudoVMSLTU_VV_MF2, + PseudoVMSLTU_VV_MF2_MASK, + PseudoVMSLTU_VV_MF4, + PseudoVMSLTU_VV_MF4_MASK, + PseudoVMSLTU_VV_MF8, + PseudoVMSLTU_VV_MF8_MASK, + PseudoVMSLTU_VX_M1, + PseudoVMSLTU_VX_M1_MASK, + PseudoVMSLTU_VX_M2, + PseudoVMSLTU_VX_M2_MASK, + PseudoVMSLTU_VX_M4, + PseudoVMSLTU_VX_M4_MASK, + PseudoVMSLTU_VX_M8, + PseudoVMSLTU_VX_M8_MASK, + PseudoVMSLTU_VX_MF2, + PseudoVMSLTU_VX_MF2_MASK, + PseudoVMSLTU_VX_MF4, + PseudoVMSLTU_VX_MF4_MASK, + PseudoVMSLTU_VX_MF8, + PseudoVMSLTU_VX_MF8_MASK, + PseudoVMSLT_VI, + PseudoVMSLT_VV_M1, + PseudoVMSLT_VV_M1_MASK, + PseudoVMSLT_VV_M2, + PseudoVMSLT_VV_M2_MASK, + PseudoVMSLT_VV_M4, + PseudoVMSLT_VV_M4_MASK, + PseudoVMSLT_VV_M8, + PseudoVMSLT_VV_M8_MASK, + PseudoVMSLT_VV_MF2, + PseudoVMSLT_VV_MF2_MASK, + PseudoVMSLT_VV_MF4, + PseudoVMSLT_VV_MF4_MASK, + PseudoVMSLT_VV_MF8, + PseudoVMSLT_VV_MF8_MASK, + PseudoVMSLT_VX_M1, + PseudoVMSLT_VX_M1_MASK, + PseudoVMSLT_VX_M2, + PseudoVMSLT_VX_M2_MASK, + PseudoVMSLT_VX_M4, + PseudoVMSLT_VX_M4_MASK, + PseudoVMSLT_VX_M8, + PseudoVMSLT_VX_M8_MASK, + PseudoVMSLT_VX_MF2, + PseudoVMSLT_VX_MF2_MASK, + PseudoVMSLT_VX_MF4, + PseudoVMSLT_VX_MF4_MASK, + PseudoVMSLT_VX_MF8, + PseudoVMSLT_VX_MF8_MASK, + PseudoVMSNE_VI_M1, + PseudoVMSNE_VI_M1_MASK, + PseudoVMSNE_VI_M2, + PseudoVMSNE_VI_M2_MASK, + PseudoVMSNE_VI_M4, + PseudoVMSNE_VI_M4_MASK, + PseudoVMSNE_VI_M8, + PseudoVMSNE_VI_M8_MASK, + PseudoVMSNE_VI_MF2, + PseudoVMSNE_VI_MF2_MASK, + PseudoVMSNE_VI_MF4, + PseudoVMSNE_VI_MF4_MASK, + PseudoVMSNE_VI_MF8, + PseudoVMSNE_VI_MF8_MASK, + PseudoVMSNE_VV_M1, + PseudoVMSNE_VV_M1_MASK, + PseudoVMSNE_VV_M2, + PseudoVMSNE_VV_M2_MASK, + PseudoVMSNE_VV_M4, + PseudoVMSNE_VV_M4_MASK, + PseudoVMSNE_VV_M8, + PseudoVMSNE_VV_M8_MASK, + PseudoVMSNE_VV_MF2, + PseudoVMSNE_VV_MF2_MASK, + PseudoVMSNE_VV_MF4, + PseudoVMSNE_VV_MF4_MASK, + PseudoVMSNE_VV_MF8, + PseudoVMSNE_VV_MF8_MASK, + PseudoVMSNE_VX_M1, + PseudoVMSNE_VX_M1_MASK, + PseudoVMSNE_VX_M2, + PseudoVMSNE_VX_M2_MASK, + PseudoVMSNE_VX_M4, + PseudoVMSNE_VX_M4_MASK, + PseudoVMSNE_VX_M8, + PseudoVMSNE_VX_M8_MASK, + PseudoVMSNE_VX_MF2, + PseudoVMSNE_VX_MF2_MASK, + PseudoVMSNE_VX_MF4, + PseudoVMSNE_VX_MF4_MASK, + PseudoVMSNE_VX_MF8, + PseudoVMSNE_VX_MF8_MASK, + PseudoVMSOF_M_B1, + PseudoVMSOF_M_B16, + PseudoVMSOF_M_B16_MASK, + PseudoVMSOF_M_B1_MASK, + PseudoVMSOF_M_B2, + PseudoVMSOF_M_B2_MASK, + PseudoVMSOF_M_B32, + PseudoVMSOF_M_B32_MASK, + PseudoVMSOF_M_B4, + PseudoVMSOF_M_B4_MASK, + PseudoVMSOF_M_B64, + PseudoVMSOF_M_B64_MASK, + PseudoVMSOF_M_B8, + PseudoVMSOF_M_B8_MASK, + PseudoVMULHSU_VV_M1, + PseudoVMULHSU_VV_M1_MASK, + PseudoVMULHSU_VV_M2, + PseudoVMULHSU_VV_M2_MASK, + PseudoVMULHSU_VV_M4, + PseudoVMULHSU_VV_M4_MASK, + PseudoVMULHSU_VV_M8, + PseudoVMULHSU_VV_M8_MASK, + PseudoVMULHSU_VV_MF2, + PseudoVMULHSU_VV_MF2_MASK, + PseudoVMULHSU_VV_MF4, + PseudoVMULHSU_VV_MF4_MASK, + PseudoVMULHSU_VV_MF8, + PseudoVMULHSU_VV_MF8_MASK, + PseudoVMULHSU_VX_M1, + PseudoVMULHSU_VX_M1_MASK, + PseudoVMULHSU_VX_M2, + PseudoVMULHSU_VX_M2_MASK, + PseudoVMULHSU_VX_M4, + PseudoVMULHSU_VX_M4_MASK, + PseudoVMULHSU_VX_M8, + PseudoVMULHSU_VX_M8_MASK, + PseudoVMULHSU_VX_MF2, + PseudoVMULHSU_VX_MF2_MASK, + PseudoVMULHSU_VX_MF4, + PseudoVMULHSU_VX_MF4_MASK, + PseudoVMULHSU_VX_MF8, + PseudoVMULHSU_VX_MF8_MASK, + PseudoVMULHU_VV_M1, + PseudoVMULHU_VV_M1_MASK, + PseudoVMULHU_VV_M2, + PseudoVMULHU_VV_M2_MASK, + PseudoVMULHU_VV_M4, + PseudoVMULHU_VV_M4_MASK, + PseudoVMULHU_VV_M8, + PseudoVMULHU_VV_M8_MASK, + PseudoVMULHU_VV_MF2, + PseudoVMULHU_VV_MF2_MASK, + PseudoVMULHU_VV_MF4, + PseudoVMULHU_VV_MF4_MASK, + PseudoVMULHU_VV_MF8, + PseudoVMULHU_VV_MF8_MASK, + PseudoVMULHU_VX_M1, + PseudoVMULHU_VX_M1_MASK, + PseudoVMULHU_VX_M2, + PseudoVMULHU_VX_M2_MASK, + PseudoVMULHU_VX_M4, + PseudoVMULHU_VX_M4_MASK, + PseudoVMULHU_VX_M8, + PseudoVMULHU_VX_M8_MASK, + PseudoVMULHU_VX_MF2, + PseudoVMULHU_VX_MF2_MASK, + PseudoVMULHU_VX_MF4, + PseudoVMULHU_VX_MF4_MASK, + PseudoVMULHU_VX_MF8, + PseudoVMULHU_VX_MF8_MASK, + PseudoVMULH_VV_M1, + PseudoVMULH_VV_M1_MASK, + PseudoVMULH_VV_M2, + PseudoVMULH_VV_M2_MASK, + PseudoVMULH_VV_M4, + PseudoVMULH_VV_M4_MASK, + PseudoVMULH_VV_M8, + PseudoVMULH_VV_M8_MASK, + PseudoVMULH_VV_MF2, + PseudoVMULH_VV_MF2_MASK, + PseudoVMULH_VV_MF4, + PseudoVMULH_VV_MF4_MASK, + PseudoVMULH_VV_MF8, + PseudoVMULH_VV_MF8_MASK, + PseudoVMULH_VX_M1, + PseudoVMULH_VX_M1_MASK, + PseudoVMULH_VX_M2, + PseudoVMULH_VX_M2_MASK, + PseudoVMULH_VX_M4, + PseudoVMULH_VX_M4_MASK, + PseudoVMULH_VX_M8, + PseudoVMULH_VX_M8_MASK, + PseudoVMULH_VX_MF2, + PseudoVMULH_VX_MF2_MASK, + PseudoVMULH_VX_MF4, + PseudoVMULH_VX_MF4_MASK, + PseudoVMULH_VX_MF8, + PseudoVMULH_VX_MF8_MASK, + PseudoVMUL_VV_M1, + PseudoVMUL_VV_M1_MASK, + PseudoVMUL_VV_M2, + PseudoVMUL_VV_M2_MASK, + PseudoVMUL_VV_M4, + PseudoVMUL_VV_M4_MASK, + PseudoVMUL_VV_M8, + PseudoVMUL_VV_M8_MASK, + PseudoVMUL_VV_MF2, + PseudoVMUL_VV_MF2_MASK, + PseudoVMUL_VV_MF4, + PseudoVMUL_VV_MF4_MASK, + PseudoVMUL_VV_MF8, + PseudoVMUL_VV_MF8_MASK, + PseudoVMUL_VX_M1, + PseudoVMUL_VX_M1_MASK, + PseudoVMUL_VX_M2, + PseudoVMUL_VX_M2_MASK, + PseudoVMUL_VX_M4, + PseudoVMUL_VX_M4_MASK, + PseudoVMUL_VX_M8, + PseudoVMUL_VX_M8_MASK, + PseudoVMUL_VX_MF2, + PseudoVMUL_VX_MF2_MASK, + PseudoVMUL_VX_MF4, + PseudoVMUL_VX_MF4_MASK, + PseudoVMUL_VX_MF8, + PseudoVMUL_VX_MF8_MASK, + PseudoVMV_S_X, + PseudoVMV_V_I_M1, + PseudoVMV_V_I_M2, + PseudoVMV_V_I_M4, + PseudoVMV_V_I_M8, + PseudoVMV_V_I_MF2, + PseudoVMV_V_I_MF4, + PseudoVMV_V_I_MF8, + PseudoVMV_V_V_M1, + PseudoVMV_V_V_M2, + PseudoVMV_V_V_M4, + PseudoVMV_V_V_M8, + PseudoVMV_V_V_MF2, + PseudoVMV_V_V_MF4, + PseudoVMV_V_V_MF8, + PseudoVMV_V_X_M1, + PseudoVMV_V_X_M2, + PseudoVMV_V_X_M4, + PseudoVMV_V_X_M8, + PseudoVMV_V_X_MF2, + PseudoVMV_V_X_MF4, + PseudoVMV_V_X_MF8, + PseudoVMV_X_S, + PseudoVMXNOR_MM_B1, + PseudoVMXNOR_MM_B16, + PseudoVMXNOR_MM_B2, + PseudoVMXNOR_MM_B32, + PseudoVMXNOR_MM_B4, + PseudoVMXNOR_MM_B64, + PseudoVMXNOR_MM_B8, + PseudoVMXOR_MM_B1, + PseudoVMXOR_MM_B16, + PseudoVMXOR_MM_B2, + PseudoVMXOR_MM_B32, + PseudoVMXOR_MM_B4, + PseudoVMXOR_MM_B64, + PseudoVMXOR_MM_B8, + PseudoVNCLIPU_WI_M1, + PseudoVNCLIPU_WI_M1_MASK, + PseudoVNCLIPU_WI_M2, + PseudoVNCLIPU_WI_M2_MASK, + PseudoVNCLIPU_WI_M4, + PseudoVNCLIPU_WI_M4_MASK, + PseudoVNCLIPU_WI_MF2, + PseudoVNCLIPU_WI_MF2_MASK, + PseudoVNCLIPU_WI_MF4, + PseudoVNCLIPU_WI_MF4_MASK, + PseudoVNCLIPU_WI_MF8, + PseudoVNCLIPU_WI_MF8_MASK, + PseudoVNCLIPU_WV_M1, + PseudoVNCLIPU_WV_M1_MASK, + PseudoVNCLIPU_WV_M2, + PseudoVNCLIPU_WV_M2_MASK, + PseudoVNCLIPU_WV_M4, + PseudoVNCLIPU_WV_M4_MASK, + PseudoVNCLIPU_WV_MF2, + PseudoVNCLIPU_WV_MF2_MASK, + PseudoVNCLIPU_WV_MF4, + PseudoVNCLIPU_WV_MF4_MASK, + PseudoVNCLIPU_WV_MF8, + PseudoVNCLIPU_WV_MF8_MASK, + PseudoVNCLIPU_WX_M1, + PseudoVNCLIPU_WX_M1_MASK, + PseudoVNCLIPU_WX_M2, + PseudoVNCLIPU_WX_M2_MASK, + PseudoVNCLIPU_WX_M4, + PseudoVNCLIPU_WX_M4_MASK, + PseudoVNCLIPU_WX_MF2, + PseudoVNCLIPU_WX_MF2_MASK, + PseudoVNCLIPU_WX_MF4, + PseudoVNCLIPU_WX_MF4_MASK, + PseudoVNCLIPU_WX_MF8, + PseudoVNCLIPU_WX_MF8_MASK, + PseudoVNCLIP_WI_M1, + PseudoVNCLIP_WI_M1_MASK, + PseudoVNCLIP_WI_M2, + PseudoVNCLIP_WI_M2_MASK, + PseudoVNCLIP_WI_M4, + PseudoVNCLIP_WI_M4_MASK, + PseudoVNCLIP_WI_MF2, + PseudoVNCLIP_WI_MF2_MASK, + PseudoVNCLIP_WI_MF4, + PseudoVNCLIP_WI_MF4_MASK, + PseudoVNCLIP_WI_MF8, + PseudoVNCLIP_WI_MF8_MASK, + PseudoVNCLIP_WV_M1, + PseudoVNCLIP_WV_M1_MASK, + PseudoVNCLIP_WV_M2, + PseudoVNCLIP_WV_M2_MASK, + PseudoVNCLIP_WV_M4, + PseudoVNCLIP_WV_M4_MASK, + PseudoVNCLIP_WV_MF2, + PseudoVNCLIP_WV_MF2_MASK, + PseudoVNCLIP_WV_MF4, + PseudoVNCLIP_WV_MF4_MASK, + PseudoVNCLIP_WV_MF8, + PseudoVNCLIP_WV_MF8_MASK, + PseudoVNCLIP_WX_M1, + PseudoVNCLIP_WX_M1_MASK, + PseudoVNCLIP_WX_M2, + PseudoVNCLIP_WX_M2_MASK, + PseudoVNCLIP_WX_M4, + PseudoVNCLIP_WX_M4_MASK, + PseudoVNCLIP_WX_MF2, + PseudoVNCLIP_WX_MF2_MASK, + PseudoVNCLIP_WX_MF4, + PseudoVNCLIP_WX_MF4_MASK, + PseudoVNCLIP_WX_MF8, + PseudoVNCLIP_WX_MF8_MASK, + PseudoVNMSAC_VV_M1, + PseudoVNMSAC_VV_M1_MASK, + PseudoVNMSAC_VV_M2, + PseudoVNMSAC_VV_M2_MASK, + PseudoVNMSAC_VV_M4, + PseudoVNMSAC_VV_M4_MASK, + PseudoVNMSAC_VV_M8, + PseudoVNMSAC_VV_M8_MASK, + PseudoVNMSAC_VV_MF2, + PseudoVNMSAC_VV_MF2_MASK, + PseudoVNMSAC_VV_MF4, + PseudoVNMSAC_VV_MF4_MASK, + PseudoVNMSAC_VV_MF8, + PseudoVNMSAC_VV_MF8_MASK, + PseudoVNMSAC_VX_M1, + PseudoVNMSAC_VX_M1_MASK, + PseudoVNMSAC_VX_M2, + PseudoVNMSAC_VX_M2_MASK, + PseudoVNMSAC_VX_M4, + PseudoVNMSAC_VX_M4_MASK, + PseudoVNMSAC_VX_M8, + PseudoVNMSAC_VX_M8_MASK, + PseudoVNMSAC_VX_MF2, + PseudoVNMSAC_VX_MF2_MASK, + PseudoVNMSAC_VX_MF4, + PseudoVNMSAC_VX_MF4_MASK, + PseudoVNMSAC_VX_MF8, + PseudoVNMSAC_VX_MF8_MASK, + PseudoVNMSUB_VV_M1, + PseudoVNMSUB_VV_M1_MASK, + PseudoVNMSUB_VV_M2, + PseudoVNMSUB_VV_M2_MASK, + PseudoVNMSUB_VV_M4, + PseudoVNMSUB_VV_M4_MASK, + PseudoVNMSUB_VV_M8, + PseudoVNMSUB_VV_M8_MASK, + PseudoVNMSUB_VV_MF2, + PseudoVNMSUB_VV_MF2_MASK, + PseudoVNMSUB_VV_MF4, + PseudoVNMSUB_VV_MF4_MASK, + PseudoVNMSUB_VV_MF8, + PseudoVNMSUB_VV_MF8_MASK, + PseudoVNMSUB_VX_M1, + PseudoVNMSUB_VX_M1_MASK, + PseudoVNMSUB_VX_M2, + PseudoVNMSUB_VX_M2_MASK, + PseudoVNMSUB_VX_M4, + PseudoVNMSUB_VX_M4_MASK, + PseudoVNMSUB_VX_M8, + PseudoVNMSUB_VX_M8_MASK, + PseudoVNMSUB_VX_MF2, + PseudoVNMSUB_VX_MF2_MASK, + PseudoVNMSUB_VX_MF4, + PseudoVNMSUB_VX_MF4_MASK, + PseudoVNMSUB_VX_MF8, + PseudoVNMSUB_VX_MF8_MASK, + PseudoVNSRA_WI_M1, + PseudoVNSRA_WI_M1_MASK, + PseudoVNSRA_WI_M2, + PseudoVNSRA_WI_M2_MASK, + PseudoVNSRA_WI_M4, + PseudoVNSRA_WI_M4_MASK, + PseudoVNSRA_WI_MF2, + PseudoVNSRA_WI_MF2_MASK, + PseudoVNSRA_WI_MF4, + PseudoVNSRA_WI_MF4_MASK, + PseudoVNSRA_WI_MF8, + PseudoVNSRA_WI_MF8_MASK, + PseudoVNSRA_WV_M1, + PseudoVNSRA_WV_M1_MASK, + PseudoVNSRA_WV_M2, + PseudoVNSRA_WV_M2_MASK, + PseudoVNSRA_WV_M4, + PseudoVNSRA_WV_M4_MASK, + PseudoVNSRA_WV_MF2, + PseudoVNSRA_WV_MF2_MASK, + PseudoVNSRA_WV_MF4, + PseudoVNSRA_WV_MF4_MASK, + PseudoVNSRA_WV_MF8, + PseudoVNSRA_WV_MF8_MASK, + PseudoVNSRA_WX_M1, + PseudoVNSRA_WX_M1_MASK, + PseudoVNSRA_WX_M2, + PseudoVNSRA_WX_M2_MASK, + PseudoVNSRA_WX_M4, + PseudoVNSRA_WX_M4_MASK, + PseudoVNSRA_WX_MF2, + PseudoVNSRA_WX_MF2_MASK, + PseudoVNSRA_WX_MF4, + PseudoVNSRA_WX_MF4_MASK, + PseudoVNSRA_WX_MF8, + PseudoVNSRA_WX_MF8_MASK, + PseudoVNSRL_WI_M1, + PseudoVNSRL_WI_M1_MASK, + PseudoVNSRL_WI_M2, + PseudoVNSRL_WI_M2_MASK, + PseudoVNSRL_WI_M4, + PseudoVNSRL_WI_M4_MASK, + PseudoVNSRL_WI_MF2, + PseudoVNSRL_WI_MF2_MASK, + PseudoVNSRL_WI_MF4, + PseudoVNSRL_WI_MF4_MASK, + PseudoVNSRL_WI_MF8, + PseudoVNSRL_WI_MF8_MASK, + PseudoVNSRL_WV_M1, + PseudoVNSRL_WV_M1_MASK, + PseudoVNSRL_WV_M2, + PseudoVNSRL_WV_M2_MASK, + PseudoVNSRL_WV_M4, + PseudoVNSRL_WV_M4_MASK, + PseudoVNSRL_WV_MF2, + PseudoVNSRL_WV_MF2_MASK, + PseudoVNSRL_WV_MF4, + PseudoVNSRL_WV_MF4_MASK, + PseudoVNSRL_WV_MF8, + PseudoVNSRL_WV_MF8_MASK, + PseudoVNSRL_WX_M1, + PseudoVNSRL_WX_M1_MASK, + PseudoVNSRL_WX_M2, + PseudoVNSRL_WX_M2_MASK, + PseudoVNSRL_WX_M4, + PseudoVNSRL_WX_M4_MASK, + PseudoVNSRL_WX_MF2, + PseudoVNSRL_WX_MF2_MASK, + PseudoVNSRL_WX_MF4, + PseudoVNSRL_WX_MF4_MASK, + PseudoVNSRL_WX_MF8, + PseudoVNSRL_WX_MF8_MASK, + PseudoVOR_VI_M1, + PseudoVOR_VI_M1_MASK, + PseudoVOR_VI_M2, + PseudoVOR_VI_M2_MASK, + PseudoVOR_VI_M4, + PseudoVOR_VI_M4_MASK, + PseudoVOR_VI_M8, + PseudoVOR_VI_M8_MASK, + PseudoVOR_VI_MF2, + PseudoVOR_VI_MF2_MASK, + PseudoVOR_VI_MF4, + PseudoVOR_VI_MF4_MASK, + PseudoVOR_VI_MF8, + PseudoVOR_VI_MF8_MASK, + PseudoVOR_VV_M1, + PseudoVOR_VV_M1_MASK, + PseudoVOR_VV_M2, + PseudoVOR_VV_M2_MASK, + PseudoVOR_VV_M4, + PseudoVOR_VV_M4_MASK, + PseudoVOR_VV_M8, + PseudoVOR_VV_M8_MASK, + PseudoVOR_VV_MF2, + PseudoVOR_VV_MF2_MASK, + PseudoVOR_VV_MF4, + PseudoVOR_VV_MF4_MASK, + PseudoVOR_VV_MF8, + PseudoVOR_VV_MF8_MASK, + PseudoVOR_VX_M1, + PseudoVOR_VX_M1_MASK, + PseudoVOR_VX_M2, + PseudoVOR_VX_M2_MASK, + PseudoVOR_VX_M4, + PseudoVOR_VX_M4_MASK, + PseudoVOR_VX_M8, + PseudoVOR_VX_M8_MASK, + PseudoVOR_VX_MF2, + PseudoVOR_VX_MF2_MASK, + PseudoVOR_VX_MF4, + PseudoVOR_VX_MF4_MASK, + PseudoVOR_VX_MF8, + PseudoVOR_VX_MF8_MASK, + PseudoVQDOTSU_VV_M1, + PseudoVQDOTSU_VV_M1_MASK, + PseudoVQDOTSU_VV_M2, + PseudoVQDOTSU_VV_M2_MASK, + PseudoVQDOTSU_VV_M4, + PseudoVQDOTSU_VV_M4_MASK, + PseudoVQDOTSU_VV_M8, + PseudoVQDOTSU_VV_M8_MASK, + PseudoVQDOTSU_VV_MF2, + PseudoVQDOTSU_VV_MF2_MASK, + PseudoVQDOTSU_VX_M1, + PseudoVQDOTSU_VX_M1_MASK, + PseudoVQDOTSU_VX_M2, + PseudoVQDOTSU_VX_M2_MASK, + PseudoVQDOTSU_VX_M4, + PseudoVQDOTSU_VX_M4_MASK, + PseudoVQDOTSU_VX_M8, + PseudoVQDOTSU_VX_M8_MASK, + PseudoVQDOTSU_VX_MF2, + PseudoVQDOTSU_VX_MF2_MASK, + PseudoVQDOTUS_VX_M1, + PseudoVQDOTUS_VX_M1_MASK, + PseudoVQDOTUS_VX_M2, + PseudoVQDOTUS_VX_M2_MASK, + PseudoVQDOTUS_VX_M4, + PseudoVQDOTUS_VX_M4_MASK, + PseudoVQDOTUS_VX_M8, + PseudoVQDOTUS_VX_M8_MASK, + PseudoVQDOTUS_VX_MF2, + PseudoVQDOTUS_VX_MF2_MASK, + PseudoVQDOTU_VV_M1, + PseudoVQDOTU_VV_M1_MASK, + PseudoVQDOTU_VV_M2, + PseudoVQDOTU_VV_M2_MASK, + PseudoVQDOTU_VV_M4, + PseudoVQDOTU_VV_M4_MASK, + PseudoVQDOTU_VV_M8, + PseudoVQDOTU_VV_M8_MASK, + PseudoVQDOTU_VV_MF2, + PseudoVQDOTU_VV_MF2_MASK, + PseudoVQDOTU_VX_M1, + PseudoVQDOTU_VX_M1_MASK, + PseudoVQDOTU_VX_M2, + PseudoVQDOTU_VX_M2_MASK, + PseudoVQDOTU_VX_M4, + PseudoVQDOTU_VX_M4_MASK, + PseudoVQDOTU_VX_M8, + PseudoVQDOTU_VX_M8_MASK, + PseudoVQDOTU_VX_MF2, + PseudoVQDOTU_VX_MF2_MASK, + PseudoVQDOT_VV_M1, + PseudoVQDOT_VV_M1_MASK, + PseudoVQDOT_VV_M2, + PseudoVQDOT_VV_M2_MASK, + PseudoVQDOT_VV_M4, + PseudoVQDOT_VV_M4_MASK, + PseudoVQDOT_VV_M8, + PseudoVQDOT_VV_M8_MASK, + PseudoVQDOT_VV_MF2, + PseudoVQDOT_VV_MF2_MASK, + PseudoVQDOT_VX_M1, + PseudoVQDOT_VX_M1_MASK, + PseudoVQDOT_VX_M2, + PseudoVQDOT_VX_M2_MASK, + PseudoVQDOT_VX_M4, + PseudoVQDOT_VX_M4_MASK, + PseudoVQDOT_VX_M8, + PseudoVQDOT_VX_M8_MASK, + PseudoVQDOT_VX_MF2, + PseudoVQDOT_VX_MF2_MASK, + PseudoVREDAND_VS_M1_E16, + PseudoVREDAND_VS_M1_E16_MASK, + PseudoVREDAND_VS_M1_E32, + PseudoVREDAND_VS_M1_E32_MASK, + PseudoVREDAND_VS_M1_E64, + PseudoVREDAND_VS_M1_E64_MASK, + PseudoVREDAND_VS_M1_E8, + PseudoVREDAND_VS_M1_E8_MASK, + PseudoVREDAND_VS_M2_E16, + PseudoVREDAND_VS_M2_E16_MASK, + PseudoVREDAND_VS_M2_E32, + PseudoVREDAND_VS_M2_E32_MASK, + PseudoVREDAND_VS_M2_E64, + PseudoVREDAND_VS_M2_E64_MASK, + PseudoVREDAND_VS_M2_E8, + PseudoVREDAND_VS_M2_E8_MASK, + PseudoVREDAND_VS_M4_E16, + PseudoVREDAND_VS_M4_E16_MASK, + PseudoVREDAND_VS_M4_E32, + PseudoVREDAND_VS_M4_E32_MASK, + PseudoVREDAND_VS_M4_E64, + PseudoVREDAND_VS_M4_E64_MASK, + PseudoVREDAND_VS_M4_E8, + PseudoVREDAND_VS_M4_E8_MASK, + PseudoVREDAND_VS_M8_E16, + PseudoVREDAND_VS_M8_E16_MASK, + PseudoVREDAND_VS_M8_E32, + PseudoVREDAND_VS_M8_E32_MASK, + PseudoVREDAND_VS_M8_E64, + PseudoVREDAND_VS_M8_E64_MASK, + PseudoVREDAND_VS_M8_E8, + PseudoVREDAND_VS_M8_E8_MASK, + PseudoVREDAND_VS_MF2_E16, + PseudoVREDAND_VS_MF2_E16_MASK, + PseudoVREDAND_VS_MF2_E32, + PseudoVREDAND_VS_MF2_E32_MASK, + PseudoVREDAND_VS_MF2_E8, + PseudoVREDAND_VS_MF2_E8_MASK, + PseudoVREDAND_VS_MF4_E16, + PseudoVREDAND_VS_MF4_E16_MASK, + PseudoVREDAND_VS_MF4_E8, + PseudoVREDAND_VS_MF4_E8_MASK, + PseudoVREDAND_VS_MF8_E8, + PseudoVREDAND_VS_MF8_E8_MASK, + PseudoVREDMAXU_VS_M1_E16, + PseudoVREDMAXU_VS_M1_E16_MASK, + PseudoVREDMAXU_VS_M1_E32, + PseudoVREDMAXU_VS_M1_E32_MASK, + PseudoVREDMAXU_VS_M1_E64, + PseudoVREDMAXU_VS_M1_E64_MASK, + PseudoVREDMAXU_VS_M1_E8, + PseudoVREDMAXU_VS_M1_E8_MASK, + PseudoVREDMAXU_VS_M2_E16, + PseudoVREDMAXU_VS_M2_E16_MASK, + PseudoVREDMAXU_VS_M2_E32, + PseudoVREDMAXU_VS_M2_E32_MASK, + PseudoVREDMAXU_VS_M2_E64, + PseudoVREDMAXU_VS_M2_E64_MASK, + PseudoVREDMAXU_VS_M2_E8, + PseudoVREDMAXU_VS_M2_E8_MASK, + PseudoVREDMAXU_VS_M4_E16, + PseudoVREDMAXU_VS_M4_E16_MASK, + PseudoVREDMAXU_VS_M4_E32, + PseudoVREDMAXU_VS_M4_E32_MASK, + PseudoVREDMAXU_VS_M4_E64, + PseudoVREDMAXU_VS_M4_E64_MASK, + PseudoVREDMAXU_VS_M4_E8, + PseudoVREDMAXU_VS_M4_E8_MASK, + PseudoVREDMAXU_VS_M8_E16, + PseudoVREDMAXU_VS_M8_E16_MASK, + PseudoVREDMAXU_VS_M8_E32, + PseudoVREDMAXU_VS_M8_E32_MASK, + PseudoVREDMAXU_VS_M8_E64, + PseudoVREDMAXU_VS_M8_E64_MASK, + PseudoVREDMAXU_VS_M8_E8, + PseudoVREDMAXU_VS_M8_E8_MASK, + PseudoVREDMAXU_VS_MF2_E16, + PseudoVREDMAXU_VS_MF2_E16_MASK, + PseudoVREDMAXU_VS_MF2_E32, + PseudoVREDMAXU_VS_MF2_E32_MASK, + PseudoVREDMAXU_VS_MF2_E8, + PseudoVREDMAXU_VS_MF2_E8_MASK, + PseudoVREDMAXU_VS_MF4_E16, + PseudoVREDMAXU_VS_MF4_E16_MASK, + PseudoVREDMAXU_VS_MF4_E8, + PseudoVREDMAXU_VS_MF4_E8_MASK, + PseudoVREDMAXU_VS_MF8_E8, + PseudoVREDMAXU_VS_MF8_E8_MASK, + PseudoVREDMAX_VS_M1_E16, + PseudoVREDMAX_VS_M1_E16_MASK, + PseudoVREDMAX_VS_M1_E32, + PseudoVREDMAX_VS_M1_E32_MASK, + PseudoVREDMAX_VS_M1_E64, + PseudoVREDMAX_VS_M1_E64_MASK, + PseudoVREDMAX_VS_M1_E8, + PseudoVREDMAX_VS_M1_E8_MASK, + PseudoVREDMAX_VS_M2_E16, + PseudoVREDMAX_VS_M2_E16_MASK, + PseudoVREDMAX_VS_M2_E32, + PseudoVREDMAX_VS_M2_E32_MASK, + PseudoVREDMAX_VS_M2_E64, + PseudoVREDMAX_VS_M2_E64_MASK, + PseudoVREDMAX_VS_M2_E8, + PseudoVREDMAX_VS_M2_E8_MASK, + PseudoVREDMAX_VS_M4_E16, + PseudoVREDMAX_VS_M4_E16_MASK, + PseudoVREDMAX_VS_M4_E32, + PseudoVREDMAX_VS_M4_E32_MASK, + PseudoVREDMAX_VS_M4_E64, + PseudoVREDMAX_VS_M4_E64_MASK, + PseudoVREDMAX_VS_M4_E8, + PseudoVREDMAX_VS_M4_E8_MASK, + PseudoVREDMAX_VS_M8_E16, + PseudoVREDMAX_VS_M8_E16_MASK, + PseudoVREDMAX_VS_M8_E32, + PseudoVREDMAX_VS_M8_E32_MASK, + PseudoVREDMAX_VS_M8_E64, + PseudoVREDMAX_VS_M8_E64_MASK, + PseudoVREDMAX_VS_M8_E8, + PseudoVREDMAX_VS_M8_E8_MASK, + PseudoVREDMAX_VS_MF2_E16, + PseudoVREDMAX_VS_MF2_E16_MASK, + PseudoVREDMAX_VS_MF2_E32, + PseudoVREDMAX_VS_MF2_E32_MASK, + PseudoVREDMAX_VS_MF2_E8, + PseudoVREDMAX_VS_MF2_E8_MASK, + PseudoVREDMAX_VS_MF4_E16, + PseudoVREDMAX_VS_MF4_E16_MASK, + PseudoVREDMAX_VS_MF4_E8, + PseudoVREDMAX_VS_MF4_E8_MASK, + PseudoVREDMAX_VS_MF8_E8, + PseudoVREDMAX_VS_MF8_E8_MASK, + PseudoVREDMINU_VS_M1_E16, + PseudoVREDMINU_VS_M1_E16_MASK, + PseudoVREDMINU_VS_M1_E32, + PseudoVREDMINU_VS_M1_E32_MASK, + PseudoVREDMINU_VS_M1_E64, + PseudoVREDMINU_VS_M1_E64_MASK, + PseudoVREDMINU_VS_M1_E8, + PseudoVREDMINU_VS_M1_E8_MASK, + PseudoVREDMINU_VS_M2_E16, + PseudoVREDMINU_VS_M2_E16_MASK, + PseudoVREDMINU_VS_M2_E32, + PseudoVREDMINU_VS_M2_E32_MASK, + PseudoVREDMINU_VS_M2_E64, + PseudoVREDMINU_VS_M2_E64_MASK, + PseudoVREDMINU_VS_M2_E8, + PseudoVREDMINU_VS_M2_E8_MASK, + PseudoVREDMINU_VS_M4_E16, + PseudoVREDMINU_VS_M4_E16_MASK, + PseudoVREDMINU_VS_M4_E32, + PseudoVREDMINU_VS_M4_E32_MASK, + PseudoVREDMINU_VS_M4_E64, + PseudoVREDMINU_VS_M4_E64_MASK, + PseudoVREDMINU_VS_M4_E8, + PseudoVREDMINU_VS_M4_E8_MASK, + PseudoVREDMINU_VS_M8_E16, + PseudoVREDMINU_VS_M8_E16_MASK, + PseudoVREDMINU_VS_M8_E32, + PseudoVREDMINU_VS_M8_E32_MASK, + PseudoVREDMINU_VS_M8_E64, + PseudoVREDMINU_VS_M8_E64_MASK, + PseudoVREDMINU_VS_M8_E8, + PseudoVREDMINU_VS_M8_E8_MASK, + PseudoVREDMINU_VS_MF2_E16, + PseudoVREDMINU_VS_MF2_E16_MASK, + PseudoVREDMINU_VS_MF2_E32, + PseudoVREDMINU_VS_MF2_E32_MASK, + PseudoVREDMINU_VS_MF2_E8, + PseudoVREDMINU_VS_MF2_E8_MASK, + PseudoVREDMINU_VS_MF4_E16, + PseudoVREDMINU_VS_MF4_E16_MASK, + PseudoVREDMINU_VS_MF4_E8, + PseudoVREDMINU_VS_MF4_E8_MASK, + PseudoVREDMINU_VS_MF8_E8, + PseudoVREDMINU_VS_MF8_E8_MASK, + PseudoVREDMIN_VS_M1_E16, + PseudoVREDMIN_VS_M1_E16_MASK, + PseudoVREDMIN_VS_M1_E32, + PseudoVREDMIN_VS_M1_E32_MASK, + PseudoVREDMIN_VS_M1_E64, + PseudoVREDMIN_VS_M1_E64_MASK, + PseudoVREDMIN_VS_M1_E8, + PseudoVREDMIN_VS_M1_E8_MASK, + PseudoVREDMIN_VS_M2_E16, + PseudoVREDMIN_VS_M2_E16_MASK, + PseudoVREDMIN_VS_M2_E32, + PseudoVREDMIN_VS_M2_E32_MASK, + PseudoVREDMIN_VS_M2_E64, + PseudoVREDMIN_VS_M2_E64_MASK, + PseudoVREDMIN_VS_M2_E8, + PseudoVREDMIN_VS_M2_E8_MASK, + PseudoVREDMIN_VS_M4_E16, + PseudoVREDMIN_VS_M4_E16_MASK, + PseudoVREDMIN_VS_M4_E32, + PseudoVREDMIN_VS_M4_E32_MASK, + PseudoVREDMIN_VS_M4_E64, + PseudoVREDMIN_VS_M4_E64_MASK, + PseudoVREDMIN_VS_M4_E8, + PseudoVREDMIN_VS_M4_E8_MASK, + PseudoVREDMIN_VS_M8_E16, + PseudoVREDMIN_VS_M8_E16_MASK, + PseudoVREDMIN_VS_M8_E32, + PseudoVREDMIN_VS_M8_E32_MASK, + PseudoVREDMIN_VS_M8_E64, + PseudoVREDMIN_VS_M8_E64_MASK, + PseudoVREDMIN_VS_M8_E8, + PseudoVREDMIN_VS_M8_E8_MASK, + PseudoVREDMIN_VS_MF2_E16, + PseudoVREDMIN_VS_MF2_E16_MASK, + PseudoVREDMIN_VS_MF2_E32, + PseudoVREDMIN_VS_MF2_E32_MASK, + PseudoVREDMIN_VS_MF2_E8, + PseudoVREDMIN_VS_MF2_E8_MASK, + PseudoVREDMIN_VS_MF4_E16, + PseudoVREDMIN_VS_MF4_E16_MASK, + PseudoVREDMIN_VS_MF4_E8, + PseudoVREDMIN_VS_MF4_E8_MASK, + PseudoVREDMIN_VS_MF8_E8, + PseudoVREDMIN_VS_MF8_E8_MASK, + PseudoVREDOR_VS_M1_E16, + PseudoVREDOR_VS_M1_E16_MASK, + PseudoVREDOR_VS_M1_E32, + PseudoVREDOR_VS_M1_E32_MASK, + PseudoVREDOR_VS_M1_E64, + PseudoVREDOR_VS_M1_E64_MASK, + PseudoVREDOR_VS_M1_E8, + PseudoVREDOR_VS_M1_E8_MASK, + PseudoVREDOR_VS_M2_E16, + PseudoVREDOR_VS_M2_E16_MASK, + PseudoVREDOR_VS_M2_E32, + PseudoVREDOR_VS_M2_E32_MASK, + PseudoVREDOR_VS_M2_E64, + PseudoVREDOR_VS_M2_E64_MASK, + PseudoVREDOR_VS_M2_E8, + PseudoVREDOR_VS_M2_E8_MASK, + PseudoVREDOR_VS_M4_E16, + PseudoVREDOR_VS_M4_E16_MASK, + PseudoVREDOR_VS_M4_E32, + PseudoVREDOR_VS_M4_E32_MASK, + PseudoVREDOR_VS_M4_E64, + PseudoVREDOR_VS_M4_E64_MASK, + PseudoVREDOR_VS_M4_E8, + PseudoVREDOR_VS_M4_E8_MASK, + PseudoVREDOR_VS_M8_E16, + PseudoVREDOR_VS_M8_E16_MASK, + PseudoVREDOR_VS_M8_E32, + PseudoVREDOR_VS_M8_E32_MASK, + PseudoVREDOR_VS_M8_E64, + PseudoVREDOR_VS_M8_E64_MASK, + PseudoVREDOR_VS_M8_E8, + PseudoVREDOR_VS_M8_E8_MASK, + PseudoVREDOR_VS_MF2_E16, + PseudoVREDOR_VS_MF2_E16_MASK, + PseudoVREDOR_VS_MF2_E32, + PseudoVREDOR_VS_MF2_E32_MASK, + PseudoVREDOR_VS_MF2_E8, + PseudoVREDOR_VS_MF2_E8_MASK, + PseudoVREDOR_VS_MF4_E16, + PseudoVREDOR_VS_MF4_E16_MASK, + PseudoVREDOR_VS_MF4_E8, + PseudoVREDOR_VS_MF4_E8_MASK, + PseudoVREDOR_VS_MF8_E8, + PseudoVREDOR_VS_MF8_E8_MASK, + PseudoVREDSUM_VS_M1_E16, + PseudoVREDSUM_VS_M1_E16_MASK, + PseudoVREDSUM_VS_M1_E32, + PseudoVREDSUM_VS_M1_E32_MASK, + PseudoVREDSUM_VS_M1_E64, + PseudoVREDSUM_VS_M1_E64_MASK, + PseudoVREDSUM_VS_M1_E8, + PseudoVREDSUM_VS_M1_E8_MASK, + PseudoVREDSUM_VS_M2_E16, + PseudoVREDSUM_VS_M2_E16_MASK, + PseudoVREDSUM_VS_M2_E32, + PseudoVREDSUM_VS_M2_E32_MASK, + PseudoVREDSUM_VS_M2_E64, + PseudoVREDSUM_VS_M2_E64_MASK, + PseudoVREDSUM_VS_M2_E8, + PseudoVREDSUM_VS_M2_E8_MASK, + PseudoVREDSUM_VS_M4_E16, + PseudoVREDSUM_VS_M4_E16_MASK, + PseudoVREDSUM_VS_M4_E32, + PseudoVREDSUM_VS_M4_E32_MASK, + PseudoVREDSUM_VS_M4_E64, + PseudoVREDSUM_VS_M4_E64_MASK, + PseudoVREDSUM_VS_M4_E8, + PseudoVREDSUM_VS_M4_E8_MASK, + PseudoVREDSUM_VS_M8_E16, + PseudoVREDSUM_VS_M8_E16_MASK, + PseudoVREDSUM_VS_M8_E32, + PseudoVREDSUM_VS_M8_E32_MASK, + PseudoVREDSUM_VS_M8_E64, + PseudoVREDSUM_VS_M8_E64_MASK, + PseudoVREDSUM_VS_M8_E8, + PseudoVREDSUM_VS_M8_E8_MASK, + PseudoVREDSUM_VS_MF2_E16, + PseudoVREDSUM_VS_MF2_E16_MASK, + PseudoVREDSUM_VS_MF2_E32, + PseudoVREDSUM_VS_MF2_E32_MASK, + PseudoVREDSUM_VS_MF2_E8, + PseudoVREDSUM_VS_MF2_E8_MASK, + PseudoVREDSUM_VS_MF4_E16, + PseudoVREDSUM_VS_MF4_E16_MASK, + PseudoVREDSUM_VS_MF4_E8, + PseudoVREDSUM_VS_MF4_E8_MASK, + PseudoVREDSUM_VS_MF8_E8, + PseudoVREDSUM_VS_MF8_E8_MASK, + PseudoVREDXOR_VS_M1_E16, + PseudoVREDXOR_VS_M1_E16_MASK, + PseudoVREDXOR_VS_M1_E32, + PseudoVREDXOR_VS_M1_E32_MASK, + PseudoVREDXOR_VS_M1_E64, + PseudoVREDXOR_VS_M1_E64_MASK, + PseudoVREDXOR_VS_M1_E8, + PseudoVREDXOR_VS_M1_E8_MASK, + PseudoVREDXOR_VS_M2_E16, + PseudoVREDXOR_VS_M2_E16_MASK, + PseudoVREDXOR_VS_M2_E32, + PseudoVREDXOR_VS_M2_E32_MASK, + PseudoVREDXOR_VS_M2_E64, + PseudoVREDXOR_VS_M2_E64_MASK, + PseudoVREDXOR_VS_M2_E8, + PseudoVREDXOR_VS_M2_E8_MASK, + PseudoVREDXOR_VS_M4_E16, + PseudoVREDXOR_VS_M4_E16_MASK, + PseudoVREDXOR_VS_M4_E32, + PseudoVREDXOR_VS_M4_E32_MASK, + PseudoVREDXOR_VS_M4_E64, + PseudoVREDXOR_VS_M4_E64_MASK, + PseudoVREDXOR_VS_M4_E8, + PseudoVREDXOR_VS_M4_E8_MASK, + PseudoVREDXOR_VS_M8_E16, + PseudoVREDXOR_VS_M8_E16_MASK, + PseudoVREDXOR_VS_M8_E32, + PseudoVREDXOR_VS_M8_E32_MASK, + PseudoVREDXOR_VS_M8_E64, + PseudoVREDXOR_VS_M8_E64_MASK, + PseudoVREDXOR_VS_M8_E8, + PseudoVREDXOR_VS_M8_E8_MASK, + PseudoVREDXOR_VS_MF2_E16, + PseudoVREDXOR_VS_MF2_E16_MASK, + PseudoVREDXOR_VS_MF2_E32, + PseudoVREDXOR_VS_MF2_E32_MASK, + PseudoVREDXOR_VS_MF2_E8, + PseudoVREDXOR_VS_MF2_E8_MASK, + PseudoVREDXOR_VS_MF4_E16, + PseudoVREDXOR_VS_MF4_E16_MASK, + PseudoVREDXOR_VS_MF4_E8, + PseudoVREDXOR_VS_MF4_E8_MASK, + PseudoVREDXOR_VS_MF8_E8, + PseudoVREDXOR_VS_MF8_E8_MASK, + PseudoVRELOAD2_M1, + PseudoVRELOAD2_M2, + PseudoVRELOAD2_M4, + PseudoVRELOAD2_MF2, + PseudoVRELOAD2_MF4, + PseudoVRELOAD2_MF8, + PseudoVRELOAD3_M1, + PseudoVRELOAD3_M2, + PseudoVRELOAD3_MF2, + PseudoVRELOAD3_MF4, + PseudoVRELOAD3_MF8, + PseudoVRELOAD4_M1, + PseudoVRELOAD4_M2, + PseudoVRELOAD4_MF2, + PseudoVRELOAD4_MF4, + PseudoVRELOAD4_MF8, + PseudoVRELOAD5_M1, + PseudoVRELOAD5_MF2, + PseudoVRELOAD5_MF4, + PseudoVRELOAD5_MF8, + PseudoVRELOAD6_M1, + PseudoVRELOAD6_MF2, + PseudoVRELOAD6_MF4, + PseudoVRELOAD6_MF8, + PseudoVRELOAD7_M1, + PseudoVRELOAD7_MF2, + PseudoVRELOAD7_MF4, + PseudoVRELOAD7_MF8, + PseudoVRELOAD8_M1, + PseudoVRELOAD8_MF2, + PseudoVRELOAD8_MF4, + PseudoVRELOAD8_MF8, + PseudoVREMU_VV_M1_E16, + PseudoVREMU_VV_M1_E16_MASK, + PseudoVREMU_VV_M1_E32, + PseudoVREMU_VV_M1_E32_MASK, + PseudoVREMU_VV_M1_E64, + PseudoVREMU_VV_M1_E64_MASK, + PseudoVREMU_VV_M1_E8, + PseudoVREMU_VV_M1_E8_MASK, + PseudoVREMU_VV_M2_E16, + PseudoVREMU_VV_M2_E16_MASK, + PseudoVREMU_VV_M2_E32, + PseudoVREMU_VV_M2_E32_MASK, + PseudoVREMU_VV_M2_E64, + PseudoVREMU_VV_M2_E64_MASK, + PseudoVREMU_VV_M2_E8, + PseudoVREMU_VV_M2_E8_MASK, + PseudoVREMU_VV_M4_E16, + PseudoVREMU_VV_M4_E16_MASK, + PseudoVREMU_VV_M4_E32, + PseudoVREMU_VV_M4_E32_MASK, + PseudoVREMU_VV_M4_E64, + PseudoVREMU_VV_M4_E64_MASK, + PseudoVREMU_VV_M4_E8, + PseudoVREMU_VV_M4_E8_MASK, + PseudoVREMU_VV_M8_E16, + PseudoVREMU_VV_M8_E16_MASK, + PseudoVREMU_VV_M8_E32, + PseudoVREMU_VV_M8_E32_MASK, + PseudoVREMU_VV_M8_E64, + PseudoVREMU_VV_M8_E64_MASK, + PseudoVREMU_VV_M8_E8, + PseudoVREMU_VV_M8_E8_MASK, + PseudoVREMU_VV_MF2_E16, + PseudoVREMU_VV_MF2_E16_MASK, + PseudoVREMU_VV_MF2_E32, + PseudoVREMU_VV_MF2_E32_MASK, + PseudoVREMU_VV_MF2_E8, + PseudoVREMU_VV_MF2_E8_MASK, + PseudoVREMU_VV_MF4_E16, + PseudoVREMU_VV_MF4_E16_MASK, + PseudoVREMU_VV_MF4_E8, + PseudoVREMU_VV_MF4_E8_MASK, + PseudoVREMU_VV_MF8_E8, + PseudoVREMU_VV_MF8_E8_MASK, + PseudoVREMU_VX_M1_E16, + PseudoVREMU_VX_M1_E16_MASK, + PseudoVREMU_VX_M1_E32, + PseudoVREMU_VX_M1_E32_MASK, + PseudoVREMU_VX_M1_E64, + PseudoVREMU_VX_M1_E64_MASK, + PseudoVREMU_VX_M1_E8, + PseudoVREMU_VX_M1_E8_MASK, + PseudoVREMU_VX_M2_E16, + PseudoVREMU_VX_M2_E16_MASK, + PseudoVREMU_VX_M2_E32, + PseudoVREMU_VX_M2_E32_MASK, + PseudoVREMU_VX_M2_E64, + PseudoVREMU_VX_M2_E64_MASK, + PseudoVREMU_VX_M2_E8, + PseudoVREMU_VX_M2_E8_MASK, + PseudoVREMU_VX_M4_E16, + PseudoVREMU_VX_M4_E16_MASK, + PseudoVREMU_VX_M4_E32, + PseudoVREMU_VX_M4_E32_MASK, + PseudoVREMU_VX_M4_E64, + PseudoVREMU_VX_M4_E64_MASK, + PseudoVREMU_VX_M4_E8, + PseudoVREMU_VX_M4_E8_MASK, + PseudoVREMU_VX_M8_E16, + PseudoVREMU_VX_M8_E16_MASK, + PseudoVREMU_VX_M8_E32, + PseudoVREMU_VX_M8_E32_MASK, + PseudoVREMU_VX_M8_E64, + PseudoVREMU_VX_M8_E64_MASK, + PseudoVREMU_VX_M8_E8, + PseudoVREMU_VX_M8_E8_MASK, + PseudoVREMU_VX_MF2_E16, + PseudoVREMU_VX_MF2_E16_MASK, + PseudoVREMU_VX_MF2_E32, + PseudoVREMU_VX_MF2_E32_MASK, + PseudoVREMU_VX_MF2_E8, + PseudoVREMU_VX_MF2_E8_MASK, + PseudoVREMU_VX_MF4_E16, + PseudoVREMU_VX_MF4_E16_MASK, + PseudoVREMU_VX_MF4_E8, + PseudoVREMU_VX_MF4_E8_MASK, + PseudoVREMU_VX_MF8_E8, + PseudoVREMU_VX_MF8_E8_MASK, + PseudoVREM_VV_M1_E16, + PseudoVREM_VV_M1_E16_MASK, + PseudoVREM_VV_M1_E32, + PseudoVREM_VV_M1_E32_MASK, + PseudoVREM_VV_M1_E64, + PseudoVREM_VV_M1_E64_MASK, + PseudoVREM_VV_M1_E8, + PseudoVREM_VV_M1_E8_MASK, + PseudoVREM_VV_M2_E16, + PseudoVREM_VV_M2_E16_MASK, + PseudoVREM_VV_M2_E32, + PseudoVREM_VV_M2_E32_MASK, + PseudoVREM_VV_M2_E64, + PseudoVREM_VV_M2_E64_MASK, + PseudoVREM_VV_M2_E8, + PseudoVREM_VV_M2_E8_MASK, + PseudoVREM_VV_M4_E16, + PseudoVREM_VV_M4_E16_MASK, + PseudoVREM_VV_M4_E32, + PseudoVREM_VV_M4_E32_MASK, + PseudoVREM_VV_M4_E64, + PseudoVREM_VV_M4_E64_MASK, + PseudoVREM_VV_M4_E8, + PseudoVREM_VV_M4_E8_MASK, + PseudoVREM_VV_M8_E16, + PseudoVREM_VV_M8_E16_MASK, + PseudoVREM_VV_M8_E32, + PseudoVREM_VV_M8_E32_MASK, + PseudoVREM_VV_M8_E64, + PseudoVREM_VV_M8_E64_MASK, + PseudoVREM_VV_M8_E8, + PseudoVREM_VV_M8_E8_MASK, + PseudoVREM_VV_MF2_E16, + PseudoVREM_VV_MF2_E16_MASK, + PseudoVREM_VV_MF2_E32, + PseudoVREM_VV_MF2_E32_MASK, + PseudoVREM_VV_MF2_E8, + PseudoVREM_VV_MF2_E8_MASK, + PseudoVREM_VV_MF4_E16, + PseudoVREM_VV_MF4_E16_MASK, + PseudoVREM_VV_MF4_E8, + PseudoVREM_VV_MF4_E8_MASK, + PseudoVREM_VV_MF8_E8, + PseudoVREM_VV_MF8_E8_MASK, + PseudoVREM_VX_M1_E16, + PseudoVREM_VX_M1_E16_MASK, + PseudoVREM_VX_M1_E32, + PseudoVREM_VX_M1_E32_MASK, + PseudoVREM_VX_M1_E64, + PseudoVREM_VX_M1_E64_MASK, + PseudoVREM_VX_M1_E8, + PseudoVREM_VX_M1_E8_MASK, + PseudoVREM_VX_M2_E16, + PseudoVREM_VX_M2_E16_MASK, + PseudoVREM_VX_M2_E32, + PseudoVREM_VX_M2_E32_MASK, + PseudoVREM_VX_M2_E64, + PseudoVREM_VX_M2_E64_MASK, + PseudoVREM_VX_M2_E8, + PseudoVREM_VX_M2_E8_MASK, + PseudoVREM_VX_M4_E16, + PseudoVREM_VX_M4_E16_MASK, + PseudoVREM_VX_M4_E32, + PseudoVREM_VX_M4_E32_MASK, + PseudoVREM_VX_M4_E64, + PseudoVREM_VX_M4_E64_MASK, + PseudoVREM_VX_M4_E8, + PseudoVREM_VX_M4_E8_MASK, + PseudoVREM_VX_M8_E16, + PseudoVREM_VX_M8_E16_MASK, + PseudoVREM_VX_M8_E32, + PseudoVREM_VX_M8_E32_MASK, + PseudoVREM_VX_M8_E64, + PseudoVREM_VX_M8_E64_MASK, + PseudoVREM_VX_M8_E8, + PseudoVREM_VX_M8_E8_MASK, + PseudoVREM_VX_MF2_E16, + PseudoVREM_VX_MF2_E16_MASK, + PseudoVREM_VX_MF2_E32, + PseudoVREM_VX_MF2_E32_MASK, + PseudoVREM_VX_MF2_E8, + PseudoVREM_VX_MF2_E8_MASK, + PseudoVREM_VX_MF4_E16, + PseudoVREM_VX_MF4_E16_MASK, + PseudoVREM_VX_MF4_E8, + PseudoVREM_VX_MF4_E8_MASK, + PseudoVREM_VX_MF8_E8, + PseudoVREM_VX_MF8_E8_MASK, + PseudoVREV8_V_M1, + PseudoVREV8_V_M1_MASK, + PseudoVREV8_V_M2, + PseudoVREV8_V_M2_MASK, + PseudoVREV8_V_M4, + PseudoVREV8_V_M4_MASK, + PseudoVREV8_V_M8, + PseudoVREV8_V_M8_MASK, + PseudoVREV8_V_MF2, + PseudoVREV8_V_MF2_MASK, + PseudoVREV8_V_MF4, + PseudoVREV8_V_MF4_MASK, + PseudoVREV8_V_MF8, + PseudoVREV8_V_MF8_MASK, + PseudoVRGATHEREI16_VV_M1_E16_M1, + PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, + PseudoVRGATHEREI16_VV_M1_E16_M2, + PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, + PseudoVRGATHEREI16_VV_M1_E16_MF2, + PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, + PseudoVRGATHEREI16_VV_M1_E16_MF4, + PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, + PseudoVRGATHEREI16_VV_M1_E32_M1, + PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, + PseudoVRGATHEREI16_VV_M1_E32_M2, + PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, + PseudoVRGATHEREI16_VV_M1_E32_MF2, + PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, + PseudoVRGATHEREI16_VV_M1_E32_MF4, + PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, + PseudoVRGATHEREI16_VV_M1_E64_M1, + PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, + PseudoVRGATHEREI16_VV_M1_E64_M2, + PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, + PseudoVRGATHEREI16_VV_M1_E64_MF2, + PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, + PseudoVRGATHEREI16_VV_M1_E64_MF4, + PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, + PseudoVRGATHEREI16_VV_M1_E8_M1, + PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, + PseudoVRGATHEREI16_VV_M1_E8_M2, + PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, + PseudoVRGATHEREI16_VV_M1_E8_MF2, + PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, + PseudoVRGATHEREI16_VV_M1_E8_MF4, + PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, + PseudoVRGATHEREI16_VV_M2_E16_M1, + PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, + PseudoVRGATHEREI16_VV_M2_E16_M2, + PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, + PseudoVRGATHEREI16_VV_M2_E16_M4, + PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, + PseudoVRGATHEREI16_VV_M2_E16_MF2, + PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, + PseudoVRGATHEREI16_VV_M2_E32_M1, + PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, + PseudoVRGATHEREI16_VV_M2_E32_M2, + PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, + PseudoVRGATHEREI16_VV_M2_E32_M4, + PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, + PseudoVRGATHEREI16_VV_M2_E32_MF2, + PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, + PseudoVRGATHEREI16_VV_M2_E64_M1, + PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, + PseudoVRGATHEREI16_VV_M2_E64_M2, + PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, + PseudoVRGATHEREI16_VV_M2_E64_M4, + PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, + PseudoVRGATHEREI16_VV_M2_E64_MF2, + PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, + PseudoVRGATHEREI16_VV_M2_E8_M1, + PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, + PseudoVRGATHEREI16_VV_M2_E8_M2, + PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, + PseudoVRGATHEREI16_VV_M2_E8_M4, + PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, + PseudoVRGATHEREI16_VV_M2_E8_MF2, + PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, + PseudoVRGATHEREI16_VV_M4_E16_M1, + PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, + PseudoVRGATHEREI16_VV_M4_E16_M2, + PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, + PseudoVRGATHEREI16_VV_M4_E16_M4, + PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, + PseudoVRGATHEREI16_VV_M4_E16_M8, + PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, + PseudoVRGATHEREI16_VV_M4_E32_M1, + PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, + PseudoVRGATHEREI16_VV_M4_E32_M2, + PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, + PseudoVRGATHEREI16_VV_M4_E32_M4, + PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, + PseudoVRGATHEREI16_VV_M4_E32_M8, + PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, + PseudoVRGATHEREI16_VV_M4_E64_M1, + PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, + PseudoVRGATHEREI16_VV_M4_E64_M2, + PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, + PseudoVRGATHEREI16_VV_M4_E64_M4, + PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, + PseudoVRGATHEREI16_VV_M4_E64_M8, + PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, + PseudoVRGATHEREI16_VV_M4_E8_M1, + PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, + PseudoVRGATHEREI16_VV_M4_E8_M2, + PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, + PseudoVRGATHEREI16_VV_M4_E8_M4, + PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, + PseudoVRGATHEREI16_VV_M4_E8_M8, + PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, + PseudoVRGATHEREI16_VV_M8_E16_M2, + PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, + PseudoVRGATHEREI16_VV_M8_E16_M4, + PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, + PseudoVRGATHEREI16_VV_M8_E16_M8, + PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, + PseudoVRGATHEREI16_VV_M8_E32_M2, + PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, + PseudoVRGATHEREI16_VV_M8_E32_M4, + PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, + PseudoVRGATHEREI16_VV_M8_E32_M8, + PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, + PseudoVRGATHEREI16_VV_M8_E64_M2, + PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, + PseudoVRGATHEREI16_VV_M8_E64_M4, + PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, + PseudoVRGATHEREI16_VV_M8_E64_M8, + PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, + PseudoVRGATHEREI16_VV_M8_E8_M2, + PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, + PseudoVRGATHEREI16_VV_M8_E8_M4, + PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, + PseudoVRGATHEREI16_VV_M8_E8_M8, + PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, + PseudoVRGATHEREI16_VV_MF2_E16_M1, + PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, + PseudoVRGATHEREI16_VV_MF2_E16_MF2, + PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, + PseudoVRGATHEREI16_VV_MF2_E16_MF4, + PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, + PseudoVRGATHEREI16_VV_MF2_E16_MF8, + PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, + PseudoVRGATHEREI16_VV_MF2_E32_M1, + PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, + PseudoVRGATHEREI16_VV_MF2_E32_MF2, + PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, + PseudoVRGATHEREI16_VV_MF2_E32_MF4, + PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, + PseudoVRGATHEREI16_VV_MF2_E32_MF8, + PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, + PseudoVRGATHEREI16_VV_MF2_E8_M1, + PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, + PseudoVRGATHEREI16_VV_MF2_E8_MF2, + PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, + PseudoVRGATHEREI16_VV_MF2_E8_MF4, + PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, + PseudoVRGATHEREI16_VV_MF2_E8_MF8, + PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, + PseudoVRGATHEREI16_VV_MF4_E16_MF2, + PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, + PseudoVRGATHEREI16_VV_MF4_E16_MF4, + PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, + PseudoVRGATHEREI16_VV_MF4_E16_MF8, + PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, + PseudoVRGATHEREI16_VV_MF4_E8_MF2, + PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, + PseudoVRGATHEREI16_VV_MF4_E8_MF4, + PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, + PseudoVRGATHEREI16_VV_MF4_E8_MF8, + PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, + PseudoVRGATHEREI16_VV_MF8_E8_MF4, + PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, + PseudoVRGATHEREI16_VV_MF8_E8_MF8, + PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, + PseudoVRGATHER_VI_M1, + PseudoVRGATHER_VI_M1_MASK, + PseudoVRGATHER_VI_M2, + PseudoVRGATHER_VI_M2_MASK, + PseudoVRGATHER_VI_M4, + PseudoVRGATHER_VI_M4_MASK, + PseudoVRGATHER_VI_M8, + PseudoVRGATHER_VI_M8_MASK, + PseudoVRGATHER_VI_MF2, + PseudoVRGATHER_VI_MF2_MASK, + PseudoVRGATHER_VI_MF4, + PseudoVRGATHER_VI_MF4_MASK, + PseudoVRGATHER_VI_MF8, + PseudoVRGATHER_VI_MF8_MASK, + PseudoVRGATHER_VV_M1_E16, + PseudoVRGATHER_VV_M1_E16_MASK, + PseudoVRGATHER_VV_M1_E32, + PseudoVRGATHER_VV_M1_E32_MASK, + PseudoVRGATHER_VV_M1_E64, + PseudoVRGATHER_VV_M1_E64_MASK, + PseudoVRGATHER_VV_M1_E8, + PseudoVRGATHER_VV_M1_E8_MASK, + PseudoVRGATHER_VV_M2_E16, + PseudoVRGATHER_VV_M2_E16_MASK, + PseudoVRGATHER_VV_M2_E32, + PseudoVRGATHER_VV_M2_E32_MASK, + PseudoVRGATHER_VV_M2_E64, + PseudoVRGATHER_VV_M2_E64_MASK, + PseudoVRGATHER_VV_M2_E8, + PseudoVRGATHER_VV_M2_E8_MASK, + PseudoVRGATHER_VV_M4_E16, + PseudoVRGATHER_VV_M4_E16_MASK, + PseudoVRGATHER_VV_M4_E32, + PseudoVRGATHER_VV_M4_E32_MASK, + PseudoVRGATHER_VV_M4_E64, + PseudoVRGATHER_VV_M4_E64_MASK, + PseudoVRGATHER_VV_M4_E8, + PseudoVRGATHER_VV_M4_E8_MASK, + PseudoVRGATHER_VV_M8_E16, + PseudoVRGATHER_VV_M8_E16_MASK, + PseudoVRGATHER_VV_M8_E32, + PseudoVRGATHER_VV_M8_E32_MASK, + PseudoVRGATHER_VV_M8_E64, + PseudoVRGATHER_VV_M8_E64_MASK, + PseudoVRGATHER_VV_M8_E8, + PseudoVRGATHER_VV_M8_E8_MASK, + PseudoVRGATHER_VV_MF2_E16, + PseudoVRGATHER_VV_MF2_E16_MASK, + PseudoVRGATHER_VV_MF2_E32, + PseudoVRGATHER_VV_MF2_E32_MASK, + PseudoVRGATHER_VV_MF2_E8, + PseudoVRGATHER_VV_MF2_E8_MASK, + PseudoVRGATHER_VV_MF4_E16, + PseudoVRGATHER_VV_MF4_E16_MASK, + PseudoVRGATHER_VV_MF4_E8, + PseudoVRGATHER_VV_MF4_E8_MASK, + PseudoVRGATHER_VV_MF8_E8, + PseudoVRGATHER_VV_MF8_E8_MASK, + PseudoVRGATHER_VX_M1, + PseudoVRGATHER_VX_M1_MASK, + PseudoVRGATHER_VX_M2, + PseudoVRGATHER_VX_M2_MASK, + PseudoVRGATHER_VX_M4, + PseudoVRGATHER_VX_M4_MASK, + PseudoVRGATHER_VX_M8, + PseudoVRGATHER_VX_M8_MASK, + PseudoVRGATHER_VX_MF2, + PseudoVRGATHER_VX_MF2_MASK, + PseudoVRGATHER_VX_MF4, + PseudoVRGATHER_VX_MF4_MASK, + PseudoVRGATHER_VX_MF8, + PseudoVRGATHER_VX_MF8_MASK, + PseudoVROL_VV_M1, + PseudoVROL_VV_M1_MASK, + PseudoVROL_VV_M2, + PseudoVROL_VV_M2_MASK, + PseudoVROL_VV_M4, + PseudoVROL_VV_M4_MASK, + PseudoVROL_VV_M8, + PseudoVROL_VV_M8_MASK, + PseudoVROL_VV_MF2, + PseudoVROL_VV_MF2_MASK, + PseudoVROL_VV_MF4, + PseudoVROL_VV_MF4_MASK, + PseudoVROL_VV_MF8, + PseudoVROL_VV_MF8_MASK, + PseudoVROL_VX_M1, + PseudoVROL_VX_M1_MASK, + PseudoVROL_VX_M2, + PseudoVROL_VX_M2_MASK, + PseudoVROL_VX_M4, + PseudoVROL_VX_M4_MASK, + PseudoVROL_VX_M8, + PseudoVROL_VX_M8_MASK, + PseudoVROL_VX_MF2, + PseudoVROL_VX_MF2_MASK, + PseudoVROL_VX_MF4, + PseudoVROL_VX_MF4_MASK, + PseudoVROL_VX_MF8, + PseudoVROL_VX_MF8_MASK, + PseudoVROR_VI_M1, + PseudoVROR_VI_M1_MASK, + PseudoVROR_VI_M2, + PseudoVROR_VI_M2_MASK, + PseudoVROR_VI_M4, + PseudoVROR_VI_M4_MASK, + PseudoVROR_VI_M8, + PseudoVROR_VI_M8_MASK, + PseudoVROR_VI_MF2, + PseudoVROR_VI_MF2_MASK, + PseudoVROR_VI_MF4, + PseudoVROR_VI_MF4_MASK, + PseudoVROR_VI_MF8, + PseudoVROR_VI_MF8_MASK, + PseudoVROR_VV_M1, + PseudoVROR_VV_M1_MASK, + PseudoVROR_VV_M2, + PseudoVROR_VV_M2_MASK, + PseudoVROR_VV_M4, + PseudoVROR_VV_M4_MASK, + PseudoVROR_VV_M8, + PseudoVROR_VV_M8_MASK, + PseudoVROR_VV_MF2, + PseudoVROR_VV_MF2_MASK, + PseudoVROR_VV_MF4, + PseudoVROR_VV_MF4_MASK, + PseudoVROR_VV_MF8, + PseudoVROR_VV_MF8_MASK, + PseudoVROR_VX_M1, + PseudoVROR_VX_M1_MASK, + PseudoVROR_VX_M2, + PseudoVROR_VX_M2_MASK, + PseudoVROR_VX_M4, + PseudoVROR_VX_M4_MASK, + PseudoVROR_VX_M8, + PseudoVROR_VX_M8_MASK, + PseudoVROR_VX_MF2, + PseudoVROR_VX_MF2_MASK, + PseudoVROR_VX_MF4, + PseudoVROR_VX_MF4_MASK, + PseudoVROR_VX_MF8, + PseudoVROR_VX_MF8_MASK, + PseudoVRSUB_VI_M1, + PseudoVRSUB_VI_M1_MASK, + PseudoVRSUB_VI_M2, + PseudoVRSUB_VI_M2_MASK, + PseudoVRSUB_VI_M4, + PseudoVRSUB_VI_M4_MASK, + PseudoVRSUB_VI_M8, + PseudoVRSUB_VI_M8_MASK, + PseudoVRSUB_VI_MF2, + PseudoVRSUB_VI_MF2_MASK, + PseudoVRSUB_VI_MF4, + PseudoVRSUB_VI_MF4_MASK, + PseudoVRSUB_VI_MF8, + PseudoVRSUB_VI_MF8_MASK, + PseudoVRSUB_VX_M1, + PseudoVRSUB_VX_M1_MASK, + PseudoVRSUB_VX_M2, + PseudoVRSUB_VX_M2_MASK, + PseudoVRSUB_VX_M4, + PseudoVRSUB_VX_M4_MASK, + PseudoVRSUB_VX_M8, + PseudoVRSUB_VX_M8_MASK, + PseudoVRSUB_VX_MF2, + PseudoVRSUB_VX_MF2_MASK, + PseudoVRSUB_VX_MF4, + PseudoVRSUB_VX_MF4_MASK, + PseudoVRSUB_VX_MF8, + PseudoVRSUB_VX_MF8_MASK, + PseudoVSADDU_VI_M1, + PseudoVSADDU_VI_M1_MASK, + PseudoVSADDU_VI_M2, + PseudoVSADDU_VI_M2_MASK, + PseudoVSADDU_VI_M4, + PseudoVSADDU_VI_M4_MASK, + PseudoVSADDU_VI_M8, + PseudoVSADDU_VI_M8_MASK, + PseudoVSADDU_VI_MF2, + PseudoVSADDU_VI_MF2_MASK, + PseudoVSADDU_VI_MF4, + PseudoVSADDU_VI_MF4_MASK, + PseudoVSADDU_VI_MF8, + PseudoVSADDU_VI_MF8_MASK, + PseudoVSADDU_VV_M1, + PseudoVSADDU_VV_M1_MASK, + PseudoVSADDU_VV_M2, + PseudoVSADDU_VV_M2_MASK, + PseudoVSADDU_VV_M4, + PseudoVSADDU_VV_M4_MASK, + PseudoVSADDU_VV_M8, + PseudoVSADDU_VV_M8_MASK, + PseudoVSADDU_VV_MF2, + PseudoVSADDU_VV_MF2_MASK, + PseudoVSADDU_VV_MF4, + PseudoVSADDU_VV_MF4_MASK, + PseudoVSADDU_VV_MF8, + PseudoVSADDU_VV_MF8_MASK, + PseudoVSADDU_VX_M1, + PseudoVSADDU_VX_M1_MASK, + PseudoVSADDU_VX_M2, + PseudoVSADDU_VX_M2_MASK, + PseudoVSADDU_VX_M4, + PseudoVSADDU_VX_M4_MASK, + PseudoVSADDU_VX_M8, + PseudoVSADDU_VX_M8_MASK, + PseudoVSADDU_VX_MF2, + PseudoVSADDU_VX_MF2_MASK, + PseudoVSADDU_VX_MF4, + PseudoVSADDU_VX_MF4_MASK, + PseudoVSADDU_VX_MF8, + PseudoVSADDU_VX_MF8_MASK, + PseudoVSADD_VI_M1, + PseudoVSADD_VI_M1_MASK, + PseudoVSADD_VI_M2, + PseudoVSADD_VI_M2_MASK, + PseudoVSADD_VI_M4, + PseudoVSADD_VI_M4_MASK, + PseudoVSADD_VI_M8, + PseudoVSADD_VI_M8_MASK, + PseudoVSADD_VI_MF2, + PseudoVSADD_VI_MF2_MASK, + PseudoVSADD_VI_MF4, + PseudoVSADD_VI_MF4_MASK, + PseudoVSADD_VI_MF8, + PseudoVSADD_VI_MF8_MASK, + PseudoVSADD_VV_M1, + PseudoVSADD_VV_M1_MASK, + PseudoVSADD_VV_M2, + PseudoVSADD_VV_M2_MASK, + PseudoVSADD_VV_M4, + PseudoVSADD_VV_M4_MASK, + PseudoVSADD_VV_M8, + PseudoVSADD_VV_M8_MASK, + PseudoVSADD_VV_MF2, + PseudoVSADD_VV_MF2_MASK, + PseudoVSADD_VV_MF4, + PseudoVSADD_VV_MF4_MASK, + PseudoVSADD_VV_MF8, + PseudoVSADD_VV_MF8_MASK, + PseudoVSADD_VX_M1, + PseudoVSADD_VX_M1_MASK, + PseudoVSADD_VX_M2, + PseudoVSADD_VX_M2_MASK, + PseudoVSADD_VX_M4, + PseudoVSADD_VX_M4_MASK, + PseudoVSADD_VX_M8, + PseudoVSADD_VX_M8_MASK, + PseudoVSADD_VX_MF2, + PseudoVSADD_VX_MF2_MASK, + PseudoVSADD_VX_MF4, + PseudoVSADD_VX_MF4_MASK, + PseudoVSADD_VX_MF8, + PseudoVSADD_VX_MF8_MASK, + PseudoVSBC_VVM_M1, + PseudoVSBC_VVM_M2, + PseudoVSBC_VVM_M4, + PseudoVSBC_VVM_M8, + PseudoVSBC_VVM_MF2, + PseudoVSBC_VVM_MF4, + PseudoVSBC_VVM_MF8, + PseudoVSBC_VXM_M1, + PseudoVSBC_VXM_M2, + PseudoVSBC_VXM_M4, + PseudoVSBC_VXM_M8, + PseudoVSBC_VXM_MF2, + PseudoVSBC_VXM_MF4, + PseudoVSBC_VXM_MF8, + PseudoVSE16_V_M1, + PseudoVSE16_V_M1_MASK, + PseudoVSE16_V_M2, + PseudoVSE16_V_M2_MASK, + PseudoVSE16_V_M4, + PseudoVSE16_V_M4_MASK, + PseudoVSE16_V_M8, + PseudoVSE16_V_M8_MASK, + PseudoVSE16_V_MF2, + PseudoVSE16_V_MF2_MASK, + PseudoVSE16_V_MF4, + PseudoVSE16_V_MF4_MASK, + PseudoVSE32_V_M1, + PseudoVSE32_V_M1_MASK, + PseudoVSE32_V_M2, + PseudoVSE32_V_M2_MASK, + PseudoVSE32_V_M4, + PseudoVSE32_V_M4_MASK, + PseudoVSE32_V_M8, + PseudoVSE32_V_M8_MASK, + PseudoVSE32_V_MF2, + PseudoVSE32_V_MF2_MASK, + PseudoVSE64_V_M1, + PseudoVSE64_V_M1_MASK, + PseudoVSE64_V_M2, + PseudoVSE64_V_M2_MASK, + PseudoVSE64_V_M4, + PseudoVSE64_V_M4_MASK, + PseudoVSE64_V_M8, + PseudoVSE64_V_M8_MASK, + PseudoVSE8_V_M1, + PseudoVSE8_V_M1_MASK, + PseudoVSE8_V_M2, + PseudoVSE8_V_M2_MASK, + PseudoVSE8_V_M4, + PseudoVSE8_V_M4_MASK, + PseudoVSE8_V_M8, + PseudoVSE8_V_M8_MASK, + PseudoVSE8_V_MF2, + PseudoVSE8_V_MF2_MASK, + PseudoVSE8_V_MF4, + PseudoVSE8_V_MF4_MASK, + PseudoVSE8_V_MF8, + PseudoVSE8_V_MF8_MASK, + PseudoVSETIVLI, + PseudoVSETVLI, + PseudoVSETVLIX0, + PseudoVSETVLIX0X0, + PseudoVSEXT_VF2_M1, + PseudoVSEXT_VF2_M1_MASK, + PseudoVSEXT_VF2_M2, + PseudoVSEXT_VF2_M2_MASK, + PseudoVSEXT_VF2_M4, + PseudoVSEXT_VF2_M4_MASK, + PseudoVSEXT_VF2_M8, + PseudoVSEXT_VF2_M8_MASK, + PseudoVSEXT_VF2_MF2, + PseudoVSEXT_VF2_MF2_MASK, + PseudoVSEXT_VF2_MF4, + PseudoVSEXT_VF2_MF4_MASK, + PseudoVSEXT_VF4_M1, + PseudoVSEXT_VF4_M1_MASK, + PseudoVSEXT_VF4_M2, + PseudoVSEXT_VF4_M2_MASK, + PseudoVSEXT_VF4_M4, + PseudoVSEXT_VF4_M4_MASK, + PseudoVSEXT_VF4_M8, + PseudoVSEXT_VF4_M8_MASK, + PseudoVSEXT_VF4_MF2, + PseudoVSEXT_VF4_MF2_MASK, + PseudoVSEXT_VF8_M1, + PseudoVSEXT_VF8_M1_MASK, + PseudoVSEXT_VF8_M2, + PseudoVSEXT_VF8_M2_MASK, + PseudoVSEXT_VF8_M4, + PseudoVSEXT_VF8_M4_MASK, + PseudoVSEXT_VF8_M8, + PseudoVSEXT_VF8_M8_MASK, + PseudoVSHA2CH_VV_M1, + PseudoVSHA2CH_VV_M2, + PseudoVSHA2CH_VV_M4, + PseudoVSHA2CH_VV_M8, + PseudoVSHA2CH_VV_MF2, + PseudoVSHA2CL_VV_M1, + PseudoVSHA2CL_VV_M2, + PseudoVSHA2CL_VV_M4, + PseudoVSHA2CL_VV_M8, + PseudoVSHA2CL_VV_MF2, + PseudoVSHA2MS_VV_M1_E32, + PseudoVSHA2MS_VV_M1_E64, + PseudoVSHA2MS_VV_M2_E32, + PseudoVSHA2MS_VV_M2_E64, + PseudoVSHA2MS_VV_M4_E32, + PseudoVSHA2MS_VV_M4_E64, + PseudoVSHA2MS_VV_M8_E32, + PseudoVSHA2MS_VV_M8_E64, + PseudoVSHA2MS_VV_MF2_E32, + PseudoVSLIDE1DOWN_VX_M1, + PseudoVSLIDE1DOWN_VX_M1_MASK, + PseudoVSLIDE1DOWN_VX_M2, + PseudoVSLIDE1DOWN_VX_M2_MASK, + PseudoVSLIDE1DOWN_VX_M4, + PseudoVSLIDE1DOWN_VX_M4_MASK, + PseudoVSLIDE1DOWN_VX_M8, + PseudoVSLIDE1DOWN_VX_M8_MASK, + PseudoVSLIDE1DOWN_VX_MF2, + PseudoVSLIDE1DOWN_VX_MF2_MASK, + PseudoVSLIDE1DOWN_VX_MF4, + PseudoVSLIDE1DOWN_VX_MF4_MASK, + PseudoVSLIDE1DOWN_VX_MF8, + PseudoVSLIDE1DOWN_VX_MF8_MASK, + PseudoVSLIDE1UP_VX_M1, + PseudoVSLIDE1UP_VX_M1_MASK, + PseudoVSLIDE1UP_VX_M2, + PseudoVSLIDE1UP_VX_M2_MASK, + PseudoVSLIDE1UP_VX_M4, + PseudoVSLIDE1UP_VX_M4_MASK, + PseudoVSLIDE1UP_VX_M8, + PseudoVSLIDE1UP_VX_M8_MASK, + PseudoVSLIDE1UP_VX_MF2, + PseudoVSLIDE1UP_VX_MF2_MASK, + PseudoVSLIDE1UP_VX_MF4, + PseudoVSLIDE1UP_VX_MF4_MASK, + PseudoVSLIDE1UP_VX_MF8, + PseudoVSLIDE1UP_VX_MF8_MASK, + PseudoVSLIDEDOWN_VI_M1, + PseudoVSLIDEDOWN_VI_M1_MASK, + PseudoVSLIDEDOWN_VI_M2, + PseudoVSLIDEDOWN_VI_M2_MASK, + PseudoVSLIDEDOWN_VI_M4, + PseudoVSLIDEDOWN_VI_M4_MASK, + PseudoVSLIDEDOWN_VI_M8, + PseudoVSLIDEDOWN_VI_M8_MASK, + PseudoVSLIDEDOWN_VI_MF2, + PseudoVSLIDEDOWN_VI_MF2_MASK, + PseudoVSLIDEDOWN_VI_MF4, + PseudoVSLIDEDOWN_VI_MF4_MASK, + PseudoVSLIDEDOWN_VI_MF8, + PseudoVSLIDEDOWN_VI_MF8_MASK, + PseudoVSLIDEDOWN_VX_M1, + PseudoVSLIDEDOWN_VX_M1_MASK, + PseudoVSLIDEDOWN_VX_M2, + PseudoVSLIDEDOWN_VX_M2_MASK, + PseudoVSLIDEDOWN_VX_M4, + PseudoVSLIDEDOWN_VX_M4_MASK, + PseudoVSLIDEDOWN_VX_M8, + PseudoVSLIDEDOWN_VX_M8_MASK, + PseudoVSLIDEDOWN_VX_MF2, + PseudoVSLIDEDOWN_VX_MF2_MASK, + PseudoVSLIDEDOWN_VX_MF4, + PseudoVSLIDEDOWN_VX_MF4_MASK, + PseudoVSLIDEDOWN_VX_MF8, + PseudoVSLIDEDOWN_VX_MF8_MASK, + PseudoVSLIDEUP_VI_M1, + PseudoVSLIDEUP_VI_M1_MASK, + PseudoVSLIDEUP_VI_M2, + PseudoVSLIDEUP_VI_M2_MASK, + PseudoVSLIDEUP_VI_M4, + PseudoVSLIDEUP_VI_M4_MASK, + PseudoVSLIDEUP_VI_M8, + PseudoVSLIDEUP_VI_M8_MASK, + PseudoVSLIDEUP_VI_MF2, + PseudoVSLIDEUP_VI_MF2_MASK, + PseudoVSLIDEUP_VI_MF4, + PseudoVSLIDEUP_VI_MF4_MASK, + PseudoVSLIDEUP_VI_MF8, + PseudoVSLIDEUP_VI_MF8_MASK, + PseudoVSLIDEUP_VX_M1, + PseudoVSLIDEUP_VX_M1_MASK, + PseudoVSLIDEUP_VX_M2, + PseudoVSLIDEUP_VX_M2_MASK, + PseudoVSLIDEUP_VX_M4, + PseudoVSLIDEUP_VX_M4_MASK, + PseudoVSLIDEUP_VX_M8, + PseudoVSLIDEUP_VX_M8_MASK, + PseudoVSLIDEUP_VX_MF2, + PseudoVSLIDEUP_VX_MF2_MASK, + PseudoVSLIDEUP_VX_MF4, + PseudoVSLIDEUP_VX_MF4_MASK, + PseudoVSLIDEUP_VX_MF8, + PseudoVSLIDEUP_VX_MF8_MASK, + PseudoVSLL_VI_M1, + PseudoVSLL_VI_M1_MASK, + PseudoVSLL_VI_M2, + PseudoVSLL_VI_M2_MASK, + PseudoVSLL_VI_M4, + PseudoVSLL_VI_M4_MASK, + PseudoVSLL_VI_M8, + PseudoVSLL_VI_M8_MASK, + PseudoVSLL_VI_MF2, + PseudoVSLL_VI_MF2_MASK, + PseudoVSLL_VI_MF4, + PseudoVSLL_VI_MF4_MASK, + PseudoVSLL_VI_MF8, + PseudoVSLL_VI_MF8_MASK, + PseudoVSLL_VV_M1, + PseudoVSLL_VV_M1_MASK, + PseudoVSLL_VV_M2, + PseudoVSLL_VV_M2_MASK, + PseudoVSLL_VV_M4, + PseudoVSLL_VV_M4_MASK, + PseudoVSLL_VV_M8, + PseudoVSLL_VV_M8_MASK, + PseudoVSLL_VV_MF2, + PseudoVSLL_VV_MF2_MASK, + PseudoVSLL_VV_MF4, + PseudoVSLL_VV_MF4_MASK, + PseudoVSLL_VV_MF8, + PseudoVSLL_VV_MF8_MASK, + PseudoVSLL_VX_M1, + PseudoVSLL_VX_M1_MASK, + PseudoVSLL_VX_M2, + PseudoVSLL_VX_M2_MASK, + PseudoVSLL_VX_M4, + PseudoVSLL_VX_M4_MASK, + PseudoVSLL_VX_M8, + PseudoVSLL_VX_M8_MASK, + PseudoVSLL_VX_MF2, + PseudoVSLL_VX_MF2_MASK, + PseudoVSLL_VX_MF4, + PseudoVSLL_VX_MF4_MASK, + PseudoVSLL_VX_MF8, + PseudoVSLL_VX_MF8_MASK, + PseudoVSM3C_VI_M1, + PseudoVSM3C_VI_M2, + PseudoVSM3C_VI_M4, + PseudoVSM3C_VI_M8, + PseudoVSM3C_VI_MF2, + PseudoVSM3ME_VV_M1, + PseudoVSM3ME_VV_M2, + PseudoVSM3ME_VV_M4, + PseudoVSM3ME_VV_M8, + PseudoVSM3ME_VV_MF2, + PseudoVSM4K_VI_M1, + PseudoVSM4K_VI_M2, + PseudoVSM4K_VI_M4, + PseudoVSM4K_VI_M8, + PseudoVSM4K_VI_MF2, + PseudoVSM4R_VS_M1_M1, + PseudoVSM4R_VS_M1_MF2, + PseudoVSM4R_VS_M1_MF4, + PseudoVSM4R_VS_M1_MF8, + PseudoVSM4R_VS_M2_M1, + PseudoVSM4R_VS_M2_M2, + PseudoVSM4R_VS_M2_MF2, + PseudoVSM4R_VS_M2_MF4, + PseudoVSM4R_VS_M2_MF8, + PseudoVSM4R_VS_M4_M1, + PseudoVSM4R_VS_M4_M2, + PseudoVSM4R_VS_M4_M4, + PseudoVSM4R_VS_M4_MF2, + PseudoVSM4R_VS_M4_MF4, + PseudoVSM4R_VS_M4_MF8, + PseudoVSM4R_VS_M8_M1, + PseudoVSM4R_VS_M8_M2, + PseudoVSM4R_VS_M8_M4, + PseudoVSM4R_VS_M8_MF2, + PseudoVSM4R_VS_M8_MF4, + PseudoVSM4R_VS_M8_MF8, + PseudoVSM4R_VS_MF2_MF2, + PseudoVSM4R_VS_MF2_MF4, + PseudoVSM4R_VS_MF2_MF8, + PseudoVSM4R_VV_M1, + PseudoVSM4R_VV_M2, + PseudoVSM4R_VV_M4, + PseudoVSM4R_VV_M8, + PseudoVSM4R_VV_MF2, + PseudoVSMUL_VV_M1, + PseudoVSMUL_VV_M1_MASK, + PseudoVSMUL_VV_M2, + PseudoVSMUL_VV_M2_MASK, + PseudoVSMUL_VV_M4, + PseudoVSMUL_VV_M4_MASK, + PseudoVSMUL_VV_M8, + PseudoVSMUL_VV_M8_MASK, + PseudoVSMUL_VV_MF2, + PseudoVSMUL_VV_MF2_MASK, + PseudoVSMUL_VV_MF4, + PseudoVSMUL_VV_MF4_MASK, + PseudoVSMUL_VV_MF8, + PseudoVSMUL_VV_MF8_MASK, + PseudoVSMUL_VX_M1, + PseudoVSMUL_VX_M1_MASK, + PseudoVSMUL_VX_M2, + PseudoVSMUL_VX_M2_MASK, + PseudoVSMUL_VX_M4, + PseudoVSMUL_VX_M4_MASK, + PseudoVSMUL_VX_M8, + PseudoVSMUL_VX_M8_MASK, + PseudoVSMUL_VX_MF2, + PseudoVSMUL_VX_MF2_MASK, + PseudoVSMUL_VX_MF4, + PseudoVSMUL_VX_MF4_MASK, + PseudoVSMUL_VX_MF8, + PseudoVSMUL_VX_MF8_MASK, + PseudoVSM_V_B1, + PseudoVSM_V_B16, + PseudoVSM_V_B2, + PseudoVSM_V_B32, + PseudoVSM_V_B4, + PseudoVSM_V_B64, + PseudoVSM_V_B8, + PseudoVSOXEI16_V_M1_M1, + PseudoVSOXEI16_V_M1_M1_MASK, + PseudoVSOXEI16_V_M1_M2, + PseudoVSOXEI16_V_M1_M2_MASK, + PseudoVSOXEI16_V_M1_M4, + PseudoVSOXEI16_V_M1_M4_MASK, + PseudoVSOXEI16_V_M1_MF2, + PseudoVSOXEI16_V_M1_MF2_MASK, + PseudoVSOXEI16_V_M2_M1, + PseudoVSOXEI16_V_M2_M1_MASK, + PseudoVSOXEI16_V_M2_M2, + PseudoVSOXEI16_V_M2_M2_MASK, + PseudoVSOXEI16_V_M2_M4, + PseudoVSOXEI16_V_M2_M4_MASK, + PseudoVSOXEI16_V_M2_M8, + PseudoVSOXEI16_V_M2_M8_MASK, + PseudoVSOXEI16_V_M4_M2, + PseudoVSOXEI16_V_M4_M2_MASK, + PseudoVSOXEI16_V_M4_M4, + PseudoVSOXEI16_V_M4_M4_MASK, + PseudoVSOXEI16_V_M4_M8, + PseudoVSOXEI16_V_M4_M8_MASK, + PseudoVSOXEI16_V_M8_M4, + PseudoVSOXEI16_V_M8_M4_MASK, + PseudoVSOXEI16_V_M8_M8, + PseudoVSOXEI16_V_M8_M8_MASK, + PseudoVSOXEI16_V_MF2_M1, + PseudoVSOXEI16_V_MF2_M1_MASK, + PseudoVSOXEI16_V_MF2_M2, + PseudoVSOXEI16_V_MF2_M2_MASK, + PseudoVSOXEI16_V_MF2_MF2, + PseudoVSOXEI16_V_MF2_MF2_MASK, + PseudoVSOXEI16_V_MF2_MF4, + PseudoVSOXEI16_V_MF2_MF4_MASK, + PseudoVSOXEI16_V_MF4_M1, + PseudoVSOXEI16_V_MF4_M1_MASK, + PseudoVSOXEI16_V_MF4_MF2, + PseudoVSOXEI16_V_MF4_MF2_MASK, + PseudoVSOXEI16_V_MF4_MF4, + PseudoVSOXEI16_V_MF4_MF4_MASK, + PseudoVSOXEI16_V_MF4_MF8, + PseudoVSOXEI16_V_MF4_MF8_MASK, + PseudoVSOXEI32_V_M1_M1, + PseudoVSOXEI32_V_M1_M1_MASK, + PseudoVSOXEI32_V_M1_M2, + PseudoVSOXEI32_V_M1_M2_MASK, + PseudoVSOXEI32_V_M1_MF2, + PseudoVSOXEI32_V_M1_MF2_MASK, + PseudoVSOXEI32_V_M1_MF4, + PseudoVSOXEI32_V_M1_MF4_MASK, + PseudoVSOXEI32_V_M2_M1, + PseudoVSOXEI32_V_M2_M1_MASK, + PseudoVSOXEI32_V_M2_M2, + PseudoVSOXEI32_V_M2_M2_MASK, + PseudoVSOXEI32_V_M2_M4, + PseudoVSOXEI32_V_M2_M4_MASK, + PseudoVSOXEI32_V_M2_MF2, + PseudoVSOXEI32_V_M2_MF2_MASK, + PseudoVSOXEI32_V_M4_M1, + PseudoVSOXEI32_V_M4_M1_MASK, + PseudoVSOXEI32_V_M4_M2, + PseudoVSOXEI32_V_M4_M2_MASK, + PseudoVSOXEI32_V_M4_M4, + PseudoVSOXEI32_V_M4_M4_MASK, + PseudoVSOXEI32_V_M4_M8, + PseudoVSOXEI32_V_M4_M8_MASK, + PseudoVSOXEI32_V_M8_M2, + PseudoVSOXEI32_V_M8_M2_MASK, + PseudoVSOXEI32_V_M8_M4, + PseudoVSOXEI32_V_M8_M4_MASK, + PseudoVSOXEI32_V_M8_M8, + PseudoVSOXEI32_V_M8_M8_MASK, + PseudoVSOXEI32_V_MF2_M1, + PseudoVSOXEI32_V_MF2_M1_MASK, + PseudoVSOXEI32_V_MF2_MF2, + PseudoVSOXEI32_V_MF2_MF2_MASK, + PseudoVSOXEI32_V_MF2_MF4, + PseudoVSOXEI32_V_MF2_MF4_MASK, + PseudoVSOXEI32_V_MF2_MF8, + PseudoVSOXEI32_V_MF2_MF8_MASK, + PseudoVSOXEI64_V_M1_M1, + PseudoVSOXEI64_V_M1_M1_MASK, + PseudoVSOXEI64_V_M1_MF2, + PseudoVSOXEI64_V_M1_MF2_MASK, + PseudoVSOXEI64_V_M1_MF4, + PseudoVSOXEI64_V_M1_MF4_MASK, + PseudoVSOXEI64_V_M1_MF8, + PseudoVSOXEI64_V_M1_MF8_MASK, + PseudoVSOXEI64_V_M2_M1, + PseudoVSOXEI64_V_M2_M1_MASK, + PseudoVSOXEI64_V_M2_M2, + PseudoVSOXEI64_V_M2_M2_MASK, + PseudoVSOXEI64_V_M2_MF2, + PseudoVSOXEI64_V_M2_MF2_MASK, + PseudoVSOXEI64_V_M2_MF4, + PseudoVSOXEI64_V_M2_MF4_MASK, + PseudoVSOXEI64_V_M4_M1, + PseudoVSOXEI64_V_M4_M1_MASK, + PseudoVSOXEI64_V_M4_M2, + PseudoVSOXEI64_V_M4_M2_MASK, + PseudoVSOXEI64_V_M4_M4, + PseudoVSOXEI64_V_M4_M4_MASK, + PseudoVSOXEI64_V_M4_MF2, + PseudoVSOXEI64_V_M4_MF2_MASK, + PseudoVSOXEI64_V_M8_M1, + PseudoVSOXEI64_V_M8_M1_MASK, + PseudoVSOXEI64_V_M8_M2, + PseudoVSOXEI64_V_M8_M2_MASK, + PseudoVSOXEI64_V_M8_M4, + PseudoVSOXEI64_V_M8_M4_MASK, + PseudoVSOXEI64_V_M8_M8, + PseudoVSOXEI64_V_M8_M8_MASK, + PseudoVSOXEI8_V_M1_M1, + PseudoVSOXEI8_V_M1_M1_MASK, + PseudoVSOXEI8_V_M1_M2, + PseudoVSOXEI8_V_M1_M2_MASK, + PseudoVSOXEI8_V_M1_M4, + PseudoVSOXEI8_V_M1_M4_MASK, + PseudoVSOXEI8_V_M1_M8, + PseudoVSOXEI8_V_M1_M8_MASK, + PseudoVSOXEI8_V_M2_M2, + PseudoVSOXEI8_V_M2_M2_MASK, + PseudoVSOXEI8_V_M2_M4, + PseudoVSOXEI8_V_M2_M4_MASK, + PseudoVSOXEI8_V_M2_M8, + PseudoVSOXEI8_V_M2_M8_MASK, + PseudoVSOXEI8_V_M4_M4, + PseudoVSOXEI8_V_M4_M4_MASK, + PseudoVSOXEI8_V_M4_M8, + PseudoVSOXEI8_V_M4_M8_MASK, + PseudoVSOXEI8_V_M8_M8, + PseudoVSOXEI8_V_M8_M8_MASK, + PseudoVSOXEI8_V_MF2_M1, + PseudoVSOXEI8_V_MF2_M1_MASK, + PseudoVSOXEI8_V_MF2_M2, + PseudoVSOXEI8_V_MF2_M2_MASK, + PseudoVSOXEI8_V_MF2_M4, + PseudoVSOXEI8_V_MF2_M4_MASK, + PseudoVSOXEI8_V_MF2_MF2, + PseudoVSOXEI8_V_MF2_MF2_MASK, + PseudoVSOXEI8_V_MF4_M1, + PseudoVSOXEI8_V_MF4_M1_MASK, + PseudoVSOXEI8_V_MF4_M2, + PseudoVSOXEI8_V_MF4_M2_MASK, + PseudoVSOXEI8_V_MF4_MF2, + PseudoVSOXEI8_V_MF4_MF2_MASK, + PseudoVSOXEI8_V_MF4_MF4, + PseudoVSOXEI8_V_MF4_MF4_MASK, + PseudoVSOXEI8_V_MF8_M1, + PseudoVSOXEI8_V_MF8_M1_MASK, + PseudoVSOXEI8_V_MF8_MF2, + PseudoVSOXEI8_V_MF8_MF2_MASK, + PseudoVSOXEI8_V_MF8_MF4, + PseudoVSOXEI8_V_MF8_MF4_MASK, + PseudoVSOXEI8_V_MF8_MF8, + PseudoVSOXEI8_V_MF8_MF8_MASK, + PseudoVSOXSEG2EI16_V_M1_M1, + PseudoVSOXSEG2EI16_V_M1_M1_MASK, + PseudoVSOXSEG2EI16_V_M1_M2, + PseudoVSOXSEG2EI16_V_M1_M2_MASK, + PseudoVSOXSEG2EI16_V_M1_M4, + PseudoVSOXSEG2EI16_V_M1_M4_MASK, + PseudoVSOXSEG2EI16_V_M1_MF2, + PseudoVSOXSEG2EI16_V_M1_MF2_MASK, + PseudoVSOXSEG2EI16_V_M2_M1, + PseudoVSOXSEG2EI16_V_M2_M1_MASK, + PseudoVSOXSEG2EI16_V_M2_M2, + PseudoVSOXSEG2EI16_V_M2_M2_MASK, + PseudoVSOXSEG2EI16_V_M2_M4, + PseudoVSOXSEG2EI16_V_M2_M4_MASK, + PseudoVSOXSEG2EI16_V_M4_M2, + PseudoVSOXSEG2EI16_V_M4_M2_MASK, + PseudoVSOXSEG2EI16_V_M4_M4, + PseudoVSOXSEG2EI16_V_M4_M4_MASK, + PseudoVSOXSEG2EI16_V_M8_M4, + PseudoVSOXSEG2EI16_V_M8_M4_MASK, + PseudoVSOXSEG2EI16_V_MF2_M1, + PseudoVSOXSEG2EI16_V_MF2_M1_MASK, + PseudoVSOXSEG2EI16_V_MF2_M2, + PseudoVSOXSEG2EI16_V_MF2_M2_MASK, + PseudoVSOXSEG2EI16_V_MF2_MF2, + PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG2EI16_V_MF2_MF4, + PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG2EI16_V_MF4_M1, + PseudoVSOXSEG2EI16_V_MF4_M1_MASK, + PseudoVSOXSEG2EI16_V_MF4_MF2, + PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG2EI16_V_MF4_MF4, + PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG2EI16_V_MF4_MF8, + PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG2EI32_V_M1_M1, + PseudoVSOXSEG2EI32_V_M1_M1_MASK, + PseudoVSOXSEG2EI32_V_M1_M2, + PseudoVSOXSEG2EI32_V_M1_M2_MASK, + PseudoVSOXSEG2EI32_V_M1_MF2, + PseudoVSOXSEG2EI32_V_M1_MF2_MASK, + PseudoVSOXSEG2EI32_V_M1_MF4, + PseudoVSOXSEG2EI32_V_M1_MF4_MASK, + PseudoVSOXSEG2EI32_V_M2_M1, + PseudoVSOXSEG2EI32_V_M2_M1_MASK, + PseudoVSOXSEG2EI32_V_M2_M2, + PseudoVSOXSEG2EI32_V_M2_M2_MASK, + PseudoVSOXSEG2EI32_V_M2_M4, + PseudoVSOXSEG2EI32_V_M2_M4_MASK, + PseudoVSOXSEG2EI32_V_M2_MF2, + PseudoVSOXSEG2EI32_V_M2_MF2_MASK, + PseudoVSOXSEG2EI32_V_M4_M1, + PseudoVSOXSEG2EI32_V_M4_M1_MASK, + PseudoVSOXSEG2EI32_V_M4_M2, + PseudoVSOXSEG2EI32_V_M4_M2_MASK, + PseudoVSOXSEG2EI32_V_M4_M4, + PseudoVSOXSEG2EI32_V_M4_M4_MASK, + PseudoVSOXSEG2EI32_V_M8_M2, + PseudoVSOXSEG2EI32_V_M8_M2_MASK, + PseudoVSOXSEG2EI32_V_M8_M4, + PseudoVSOXSEG2EI32_V_M8_M4_MASK, + PseudoVSOXSEG2EI32_V_MF2_M1, + PseudoVSOXSEG2EI32_V_MF2_M1_MASK, + PseudoVSOXSEG2EI32_V_MF2_MF2, + PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG2EI32_V_MF2_MF4, + PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG2EI32_V_MF2_MF8, + PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG2EI64_V_M1_M1, + PseudoVSOXSEG2EI64_V_M1_M1_MASK, + PseudoVSOXSEG2EI64_V_M1_MF2, + PseudoVSOXSEG2EI64_V_M1_MF2_MASK, + PseudoVSOXSEG2EI64_V_M1_MF4, + PseudoVSOXSEG2EI64_V_M1_MF4_MASK, + PseudoVSOXSEG2EI64_V_M1_MF8, + PseudoVSOXSEG2EI64_V_M1_MF8_MASK, + PseudoVSOXSEG2EI64_V_M2_M1, + PseudoVSOXSEG2EI64_V_M2_M1_MASK, + PseudoVSOXSEG2EI64_V_M2_M2, + PseudoVSOXSEG2EI64_V_M2_M2_MASK, + PseudoVSOXSEG2EI64_V_M2_MF2, + PseudoVSOXSEG2EI64_V_M2_MF2_MASK, + PseudoVSOXSEG2EI64_V_M2_MF4, + PseudoVSOXSEG2EI64_V_M2_MF4_MASK, + PseudoVSOXSEG2EI64_V_M4_M1, + PseudoVSOXSEG2EI64_V_M4_M1_MASK, + PseudoVSOXSEG2EI64_V_M4_M2, + PseudoVSOXSEG2EI64_V_M4_M2_MASK, + PseudoVSOXSEG2EI64_V_M4_M4, + PseudoVSOXSEG2EI64_V_M4_M4_MASK, + PseudoVSOXSEG2EI64_V_M4_MF2, + PseudoVSOXSEG2EI64_V_M4_MF2_MASK, + PseudoVSOXSEG2EI64_V_M8_M1, + PseudoVSOXSEG2EI64_V_M8_M1_MASK, + PseudoVSOXSEG2EI64_V_M8_M2, + PseudoVSOXSEG2EI64_V_M8_M2_MASK, + PseudoVSOXSEG2EI64_V_M8_M4, + PseudoVSOXSEG2EI64_V_M8_M4_MASK, + PseudoVSOXSEG2EI8_V_M1_M1, + PseudoVSOXSEG2EI8_V_M1_M1_MASK, + PseudoVSOXSEG2EI8_V_M1_M2, + PseudoVSOXSEG2EI8_V_M1_M2_MASK, + PseudoVSOXSEG2EI8_V_M1_M4, + PseudoVSOXSEG2EI8_V_M1_M4_MASK, + PseudoVSOXSEG2EI8_V_M2_M2, + PseudoVSOXSEG2EI8_V_M2_M2_MASK, + PseudoVSOXSEG2EI8_V_M2_M4, + PseudoVSOXSEG2EI8_V_M2_M4_MASK, + PseudoVSOXSEG2EI8_V_M4_M4, + PseudoVSOXSEG2EI8_V_M4_M4_MASK, + PseudoVSOXSEG2EI8_V_MF2_M1, + PseudoVSOXSEG2EI8_V_MF2_M1_MASK, + PseudoVSOXSEG2EI8_V_MF2_M2, + PseudoVSOXSEG2EI8_V_MF2_M2_MASK, + PseudoVSOXSEG2EI8_V_MF2_M4, + PseudoVSOXSEG2EI8_V_MF2_M4_MASK, + PseudoVSOXSEG2EI8_V_MF2_MF2, + PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG2EI8_V_MF4_M1, + PseudoVSOXSEG2EI8_V_MF4_M1_MASK, + PseudoVSOXSEG2EI8_V_MF4_M2, + PseudoVSOXSEG2EI8_V_MF4_M2_MASK, + PseudoVSOXSEG2EI8_V_MF4_MF2, + PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG2EI8_V_MF4_MF4, + PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG2EI8_V_MF8_M1, + PseudoVSOXSEG2EI8_V_MF8_M1_MASK, + PseudoVSOXSEG2EI8_V_MF8_MF2, + PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG2EI8_V_MF8_MF4, + PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG2EI8_V_MF8_MF8, + PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG3EI16_V_M1_M1, + PseudoVSOXSEG3EI16_V_M1_M1_MASK, + PseudoVSOXSEG3EI16_V_M1_M2, + PseudoVSOXSEG3EI16_V_M1_M2_MASK, + PseudoVSOXSEG3EI16_V_M1_MF2, + PseudoVSOXSEG3EI16_V_M1_MF2_MASK, + PseudoVSOXSEG3EI16_V_M2_M1, + PseudoVSOXSEG3EI16_V_M2_M1_MASK, + PseudoVSOXSEG3EI16_V_M2_M2, + PseudoVSOXSEG3EI16_V_M2_M2_MASK, + PseudoVSOXSEG3EI16_V_M4_M2, + PseudoVSOXSEG3EI16_V_M4_M2_MASK, + PseudoVSOXSEG3EI16_V_MF2_M1, + PseudoVSOXSEG3EI16_V_MF2_M1_MASK, + PseudoVSOXSEG3EI16_V_MF2_M2, + PseudoVSOXSEG3EI16_V_MF2_M2_MASK, + PseudoVSOXSEG3EI16_V_MF2_MF2, + PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG3EI16_V_MF2_MF4, + PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG3EI16_V_MF4_M1, + PseudoVSOXSEG3EI16_V_MF4_M1_MASK, + PseudoVSOXSEG3EI16_V_MF4_MF2, + PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG3EI16_V_MF4_MF4, + PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG3EI16_V_MF4_MF8, + PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG3EI32_V_M1_M1, + PseudoVSOXSEG3EI32_V_M1_M1_MASK, + PseudoVSOXSEG3EI32_V_M1_M2, + PseudoVSOXSEG3EI32_V_M1_M2_MASK, + PseudoVSOXSEG3EI32_V_M1_MF2, + PseudoVSOXSEG3EI32_V_M1_MF2_MASK, + PseudoVSOXSEG3EI32_V_M1_MF4, + PseudoVSOXSEG3EI32_V_M1_MF4_MASK, + PseudoVSOXSEG3EI32_V_M2_M1, + PseudoVSOXSEG3EI32_V_M2_M1_MASK, + PseudoVSOXSEG3EI32_V_M2_M2, + PseudoVSOXSEG3EI32_V_M2_M2_MASK, + PseudoVSOXSEG3EI32_V_M2_MF2, + PseudoVSOXSEG3EI32_V_M2_MF2_MASK, + PseudoVSOXSEG3EI32_V_M4_M1, + PseudoVSOXSEG3EI32_V_M4_M1_MASK, + PseudoVSOXSEG3EI32_V_M4_M2, + PseudoVSOXSEG3EI32_V_M4_M2_MASK, + PseudoVSOXSEG3EI32_V_M8_M2, + PseudoVSOXSEG3EI32_V_M8_M2_MASK, + PseudoVSOXSEG3EI32_V_MF2_M1, + PseudoVSOXSEG3EI32_V_MF2_M1_MASK, + PseudoVSOXSEG3EI32_V_MF2_MF2, + PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG3EI32_V_MF2_MF4, + PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG3EI32_V_MF2_MF8, + PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG3EI64_V_M1_M1, + PseudoVSOXSEG3EI64_V_M1_M1_MASK, + PseudoVSOXSEG3EI64_V_M1_MF2, + PseudoVSOXSEG3EI64_V_M1_MF2_MASK, + PseudoVSOXSEG3EI64_V_M1_MF4, + PseudoVSOXSEG3EI64_V_M1_MF4_MASK, + PseudoVSOXSEG3EI64_V_M1_MF8, + PseudoVSOXSEG3EI64_V_M1_MF8_MASK, + PseudoVSOXSEG3EI64_V_M2_M1, + PseudoVSOXSEG3EI64_V_M2_M1_MASK, + PseudoVSOXSEG3EI64_V_M2_M2, + PseudoVSOXSEG3EI64_V_M2_M2_MASK, + PseudoVSOXSEG3EI64_V_M2_MF2, + PseudoVSOXSEG3EI64_V_M2_MF2_MASK, + PseudoVSOXSEG3EI64_V_M2_MF4, + PseudoVSOXSEG3EI64_V_M2_MF4_MASK, + PseudoVSOXSEG3EI64_V_M4_M1, + PseudoVSOXSEG3EI64_V_M4_M1_MASK, + PseudoVSOXSEG3EI64_V_M4_M2, + PseudoVSOXSEG3EI64_V_M4_M2_MASK, + PseudoVSOXSEG3EI64_V_M4_MF2, + PseudoVSOXSEG3EI64_V_M4_MF2_MASK, + PseudoVSOXSEG3EI64_V_M8_M1, + PseudoVSOXSEG3EI64_V_M8_M1_MASK, + PseudoVSOXSEG3EI64_V_M8_M2, + PseudoVSOXSEG3EI64_V_M8_M2_MASK, + PseudoVSOXSEG3EI8_V_M1_M1, + PseudoVSOXSEG3EI8_V_M1_M1_MASK, + PseudoVSOXSEG3EI8_V_M1_M2, + PseudoVSOXSEG3EI8_V_M1_M2_MASK, + PseudoVSOXSEG3EI8_V_M2_M2, + PseudoVSOXSEG3EI8_V_M2_M2_MASK, + PseudoVSOXSEG3EI8_V_MF2_M1, + PseudoVSOXSEG3EI8_V_MF2_M1_MASK, + PseudoVSOXSEG3EI8_V_MF2_M2, + PseudoVSOXSEG3EI8_V_MF2_M2_MASK, + PseudoVSOXSEG3EI8_V_MF2_MF2, + PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG3EI8_V_MF4_M1, + PseudoVSOXSEG3EI8_V_MF4_M1_MASK, + PseudoVSOXSEG3EI8_V_MF4_M2, + PseudoVSOXSEG3EI8_V_MF4_M2_MASK, + PseudoVSOXSEG3EI8_V_MF4_MF2, + PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG3EI8_V_MF4_MF4, + PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG3EI8_V_MF8_M1, + PseudoVSOXSEG3EI8_V_MF8_M1_MASK, + PseudoVSOXSEG3EI8_V_MF8_MF2, + PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG3EI8_V_MF8_MF4, + PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG3EI8_V_MF8_MF8, + PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG4EI16_V_M1_M1, + PseudoVSOXSEG4EI16_V_M1_M1_MASK, + PseudoVSOXSEG4EI16_V_M1_M2, + PseudoVSOXSEG4EI16_V_M1_M2_MASK, + PseudoVSOXSEG4EI16_V_M1_MF2, + PseudoVSOXSEG4EI16_V_M1_MF2_MASK, + PseudoVSOXSEG4EI16_V_M2_M1, + PseudoVSOXSEG4EI16_V_M2_M1_MASK, + PseudoVSOXSEG4EI16_V_M2_M2, + PseudoVSOXSEG4EI16_V_M2_M2_MASK, + PseudoVSOXSEG4EI16_V_M4_M2, + PseudoVSOXSEG4EI16_V_M4_M2_MASK, + PseudoVSOXSEG4EI16_V_MF2_M1, + PseudoVSOXSEG4EI16_V_MF2_M1_MASK, + PseudoVSOXSEG4EI16_V_MF2_M2, + PseudoVSOXSEG4EI16_V_MF2_M2_MASK, + PseudoVSOXSEG4EI16_V_MF2_MF2, + PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG4EI16_V_MF2_MF4, + PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG4EI16_V_MF4_M1, + PseudoVSOXSEG4EI16_V_MF4_M1_MASK, + PseudoVSOXSEG4EI16_V_MF4_MF2, + PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG4EI16_V_MF4_MF4, + PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG4EI16_V_MF4_MF8, + PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG4EI32_V_M1_M1, + PseudoVSOXSEG4EI32_V_M1_M1_MASK, + PseudoVSOXSEG4EI32_V_M1_M2, + PseudoVSOXSEG4EI32_V_M1_M2_MASK, + PseudoVSOXSEG4EI32_V_M1_MF2, + PseudoVSOXSEG4EI32_V_M1_MF2_MASK, + PseudoVSOXSEG4EI32_V_M1_MF4, + PseudoVSOXSEG4EI32_V_M1_MF4_MASK, + PseudoVSOXSEG4EI32_V_M2_M1, + PseudoVSOXSEG4EI32_V_M2_M1_MASK, + PseudoVSOXSEG4EI32_V_M2_M2, + PseudoVSOXSEG4EI32_V_M2_M2_MASK, + PseudoVSOXSEG4EI32_V_M2_MF2, + PseudoVSOXSEG4EI32_V_M2_MF2_MASK, + PseudoVSOXSEG4EI32_V_M4_M1, + PseudoVSOXSEG4EI32_V_M4_M1_MASK, + PseudoVSOXSEG4EI32_V_M4_M2, + PseudoVSOXSEG4EI32_V_M4_M2_MASK, + PseudoVSOXSEG4EI32_V_M8_M2, + PseudoVSOXSEG4EI32_V_M8_M2_MASK, + PseudoVSOXSEG4EI32_V_MF2_M1, + PseudoVSOXSEG4EI32_V_MF2_M1_MASK, + PseudoVSOXSEG4EI32_V_MF2_MF2, + PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG4EI32_V_MF2_MF4, + PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG4EI32_V_MF2_MF8, + PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG4EI64_V_M1_M1, + PseudoVSOXSEG4EI64_V_M1_M1_MASK, + PseudoVSOXSEG4EI64_V_M1_MF2, + PseudoVSOXSEG4EI64_V_M1_MF2_MASK, + PseudoVSOXSEG4EI64_V_M1_MF4, + PseudoVSOXSEG4EI64_V_M1_MF4_MASK, + PseudoVSOXSEG4EI64_V_M1_MF8, + PseudoVSOXSEG4EI64_V_M1_MF8_MASK, + PseudoVSOXSEG4EI64_V_M2_M1, + PseudoVSOXSEG4EI64_V_M2_M1_MASK, + PseudoVSOXSEG4EI64_V_M2_M2, + PseudoVSOXSEG4EI64_V_M2_M2_MASK, + PseudoVSOXSEG4EI64_V_M2_MF2, + PseudoVSOXSEG4EI64_V_M2_MF2_MASK, + PseudoVSOXSEG4EI64_V_M2_MF4, + PseudoVSOXSEG4EI64_V_M2_MF4_MASK, + PseudoVSOXSEG4EI64_V_M4_M1, + PseudoVSOXSEG4EI64_V_M4_M1_MASK, + PseudoVSOXSEG4EI64_V_M4_M2, + PseudoVSOXSEG4EI64_V_M4_M2_MASK, + PseudoVSOXSEG4EI64_V_M4_MF2, + PseudoVSOXSEG4EI64_V_M4_MF2_MASK, + PseudoVSOXSEG4EI64_V_M8_M1, + PseudoVSOXSEG4EI64_V_M8_M1_MASK, + PseudoVSOXSEG4EI64_V_M8_M2, + PseudoVSOXSEG4EI64_V_M8_M2_MASK, + PseudoVSOXSEG4EI8_V_M1_M1, + PseudoVSOXSEG4EI8_V_M1_M1_MASK, + PseudoVSOXSEG4EI8_V_M1_M2, + PseudoVSOXSEG4EI8_V_M1_M2_MASK, + PseudoVSOXSEG4EI8_V_M2_M2, + PseudoVSOXSEG4EI8_V_M2_M2_MASK, + PseudoVSOXSEG4EI8_V_MF2_M1, + PseudoVSOXSEG4EI8_V_MF2_M1_MASK, + PseudoVSOXSEG4EI8_V_MF2_M2, + PseudoVSOXSEG4EI8_V_MF2_M2_MASK, + PseudoVSOXSEG4EI8_V_MF2_MF2, + PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG4EI8_V_MF4_M1, + PseudoVSOXSEG4EI8_V_MF4_M1_MASK, + PseudoVSOXSEG4EI8_V_MF4_M2, + PseudoVSOXSEG4EI8_V_MF4_M2_MASK, + PseudoVSOXSEG4EI8_V_MF4_MF2, + PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG4EI8_V_MF4_MF4, + PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG4EI8_V_MF8_M1, + PseudoVSOXSEG4EI8_V_MF8_M1_MASK, + PseudoVSOXSEG4EI8_V_MF8_MF2, + PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG4EI8_V_MF8_MF4, + PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG4EI8_V_MF8_MF8, + PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG5EI16_V_M1_M1, + PseudoVSOXSEG5EI16_V_M1_M1_MASK, + PseudoVSOXSEG5EI16_V_M1_MF2, + PseudoVSOXSEG5EI16_V_M1_MF2_MASK, + PseudoVSOXSEG5EI16_V_M2_M1, + PseudoVSOXSEG5EI16_V_M2_M1_MASK, + PseudoVSOXSEG5EI16_V_MF2_M1, + PseudoVSOXSEG5EI16_V_MF2_M1_MASK, + PseudoVSOXSEG5EI16_V_MF2_MF2, + PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG5EI16_V_MF2_MF4, + PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG5EI16_V_MF4_M1, + PseudoVSOXSEG5EI16_V_MF4_M1_MASK, + PseudoVSOXSEG5EI16_V_MF4_MF2, + PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG5EI16_V_MF4_MF4, + PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG5EI16_V_MF4_MF8, + PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG5EI32_V_M1_M1, + PseudoVSOXSEG5EI32_V_M1_M1_MASK, + PseudoVSOXSEG5EI32_V_M1_MF2, + PseudoVSOXSEG5EI32_V_M1_MF2_MASK, + PseudoVSOXSEG5EI32_V_M1_MF4, + PseudoVSOXSEG5EI32_V_M1_MF4_MASK, + PseudoVSOXSEG5EI32_V_M2_M1, + PseudoVSOXSEG5EI32_V_M2_M1_MASK, + PseudoVSOXSEG5EI32_V_M2_MF2, + PseudoVSOXSEG5EI32_V_M2_MF2_MASK, + PseudoVSOXSEG5EI32_V_M4_M1, + PseudoVSOXSEG5EI32_V_M4_M1_MASK, + PseudoVSOXSEG5EI32_V_MF2_M1, + PseudoVSOXSEG5EI32_V_MF2_M1_MASK, + PseudoVSOXSEG5EI32_V_MF2_MF2, + PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG5EI32_V_MF2_MF4, + PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG5EI32_V_MF2_MF8, + PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG5EI64_V_M1_M1, + PseudoVSOXSEG5EI64_V_M1_M1_MASK, + PseudoVSOXSEG5EI64_V_M1_MF2, + PseudoVSOXSEG5EI64_V_M1_MF2_MASK, + PseudoVSOXSEG5EI64_V_M1_MF4, + PseudoVSOXSEG5EI64_V_M1_MF4_MASK, + PseudoVSOXSEG5EI64_V_M1_MF8, + PseudoVSOXSEG5EI64_V_M1_MF8_MASK, + PseudoVSOXSEG5EI64_V_M2_M1, + PseudoVSOXSEG5EI64_V_M2_M1_MASK, + PseudoVSOXSEG5EI64_V_M2_MF2, + PseudoVSOXSEG5EI64_V_M2_MF2_MASK, + PseudoVSOXSEG5EI64_V_M2_MF4, + PseudoVSOXSEG5EI64_V_M2_MF4_MASK, + PseudoVSOXSEG5EI64_V_M4_M1, + PseudoVSOXSEG5EI64_V_M4_M1_MASK, + PseudoVSOXSEG5EI64_V_M4_MF2, + PseudoVSOXSEG5EI64_V_M4_MF2_MASK, + PseudoVSOXSEG5EI64_V_M8_M1, + PseudoVSOXSEG5EI64_V_M8_M1_MASK, + PseudoVSOXSEG5EI8_V_M1_M1, + PseudoVSOXSEG5EI8_V_M1_M1_MASK, + PseudoVSOXSEG5EI8_V_MF2_M1, + PseudoVSOXSEG5EI8_V_MF2_M1_MASK, + PseudoVSOXSEG5EI8_V_MF2_MF2, + PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG5EI8_V_MF4_M1, + PseudoVSOXSEG5EI8_V_MF4_M1_MASK, + PseudoVSOXSEG5EI8_V_MF4_MF2, + PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG5EI8_V_MF4_MF4, + PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG5EI8_V_MF8_M1, + PseudoVSOXSEG5EI8_V_MF8_M1_MASK, + PseudoVSOXSEG5EI8_V_MF8_MF2, + PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG5EI8_V_MF8_MF4, + PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG5EI8_V_MF8_MF8, + PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG6EI16_V_M1_M1, + PseudoVSOXSEG6EI16_V_M1_M1_MASK, + PseudoVSOXSEG6EI16_V_M1_MF2, + PseudoVSOXSEG6EI16_V_M1_MF2_MASK, + PseudoVSOXSEG6EI16_V_M2_M1, + PseudoVSOXSEG6EI16_V_M2_M1_MASK, + PseudoVSOXSEG6EI16_V_MF2_M1, + PseudoVSOXSEG6EI16_V_MF2_M1_MASK, + PseudoVSOXSEG6EI16_V_MF2_MF2, + PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG6EI16_V_MF2_MF4, + PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG6EI16_V_MF4_M1, + PseudoVSOXSEG6EI16_V_MF4_M1_MASK, + PseudoVSOXSEG6EI16_V_MF4_MF2, + PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG6EI16_V_MF4_MF4, + PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG6EI16_V_MF4_MF8, + PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG6EI32_V_M1_M1, + PseudoVSOXSEG6EI32_V_M1_M1_MASK, + PseudoVSOXSEG6EI32_V_M1_MF2, + PseudoVSOXSEG6EI32_V_M1_MF2_MASK, + PseudoVSOXSEG6EI32_V_M1_MF4, + PseudoVSOXSEG6EI32_V_M1_MF4_MASK, + PseudoVSOXSEG6EI32_V_M2_M1, + PseudoVSOXSEG6EI32_V_M2_M1_MASK, + PseudoVSOXSEG6EI32_V_M2_MF2, + PseudoVSOXSEG6EI32_V_M2_MF2_MASK, + PseudoVSOXSEG6EI32_V_M4_M1, + PseudoVSOXSEG6EI32_V_M4_M1_MASK, + PseudoVSOXSEG6EI32_V_MF2_M1, + PseudoVSOXSEG6EI32_V_MF2_M1_MASK, + PseudoVSOXSEG6EI32_V_MF2_MF2, + PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG6EI32_V_MF2_MF4, + PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG6EI32_V_MF2_MF8, + PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG6EI64_V_M1_M1, + PseudoVSOXSEG6EI64_V_M1_M1_MASK, + PseudoVSOXSEG6EI64_V_M1_MF2, + PseudoVSOXSEG6EI64_V_M1_MF2_MASK, + PseudoVSOXSEG6EI64_V_M1_MF4, + PseudoVSOXSEG6EI64_V_M1_MF4_MASK, + PseudoVSOXSEG6EI64_V_M1_MF8, + PseudoVSOXSEG6EI64_V_M1_MF8_MASK, + PseudoVSOXSEG6EI64_V_M2_M1, + PseudoVSOXSEG6EI64_V_M2_M1_MASK, + PseudoVSOXSEG6EI64_V_M2_MF2, + PseudoVSOXSEG6EI64_V_M2_MF2_MASK, + PseudoVSOXSEG6EI64_V_M2_MF4, + PseudoVSOXSEG6EI64_V_M2_MF4_MASK, + PseudoVSOXSEG6EI64_V_M4_M1, + PseudoVSOXSEG6EI64_V_M4_M1_MASK, + PseudoVSOXSEG6EI64_V_M4_MF2, + PseudoVSOXSEG6EI64_V_M4_MF2_MASK, + PseudoVSOXSEG6EI64_V_M8_M1, + PseudoVSOXSEG6EI64_V_M8_M1_MASK, + PseudoVSOXSEG6EI8_V_M1_M1, + PseudoVSOXSEG6EI8_V_M1_M1_MASK, + PseudoVSOXSEG6EI8_V_MF2_M1, + PseudoVSOXSEG6EI8_V_MF2_M1_MASK, + PseudoVSOXSEG6EI8_V_MF2_MF2, + PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG6EI8_V_MF4_M1, + PseudoVSOXSEG6EI8_V_MF4_M1_MASK, + PseudoVSOXSEG6EI8_V_MF4_MF2, + PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG6EI8_V_MF4_MF4, + PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG6EI8_V_MF8_M1, + PseudoVSOXSEG6EI8_V_MF8_M1_MASK, + PseudoVSOXSEG6EI8_V_MF8_MF2, + PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG6EI8_V_MF8_MF4, + PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG6EI8_V_MF8_MF8, + PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG7EI16_V_M1_M1, + PseudoVSOXSEG7EI16_V_M1_M1_MASK, + PseudoVSOXSEG7EI16_V_M1_MF2, + PseudoVSOXSEG7EI16_V_M1_MF2_MASK, + PseudoVSOXSEG7EI16_V_M2_M1, + PseudoVSOXSEG7EI16_V_M2_M1_MASK, + PseudoVSOXSEG7EI16_V_MF2_M1, + PseudoVSOXSEG7EI16_V_MF2_M1_MASK, + PseudoVSOXSEG7EI16_V_MF2_MF2, + PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG7EI16_V_MF2_MF4, + PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG7EI16_V_MF4_M1, + PseudoVSOXSEG7EI16_V_MF4_M1_MASK, + PseudoVSOXSEG7EI16_V_MF4_MF2, + PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG7EI16_V_MF4_MF4, + PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG7EI16_V_MF4_MF8, + PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG7EI32_V_M1_M1, + PseudoVSOXSEG7EI32_V_M1_M1_MASK, + PseudoVSOXSEG7EI32_V_M1_MF2, + PseudoVSOXSEG7EI32_V_M1_MF2_MASK, + PseudoVSOXSEG7EI32_V_M1_MF4, + PseudoVSOXSEG7EI32_V_M1_MF4_MASK, + PseudoVSOXSEG7EI32_V_M2_M1, + PseudoVSOXSEG7EI32_V_M2_M1_MASK, + PseudoVSOXSEG7EI32_V_M2_MF2, + PseudoVSOXSEG7EI32_V_M2_MF2_MASK, + PseudoVSOXSEG7EI32_V_M4_M1, + PseudoVSOXSEG7EI32_V_M4_M1_MASK, + PseudoVSOXSEG7EI32_V_MF2_M1, + PseudoVSOXSEG7EI32_V_MF2_M1_MASK, + PseudoVSOXSEG7EI32_V_MF2_MF2, + PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG7EI32_V_MF2_MF4, + PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG7EI32_V_MF2_MF8, + PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG7EI64_V_M1_M1, + PseudoVSOXSEG7EI64_V_M1_M1_MASK, + PseudoVSOXSEG7EI64_V_M1_MF2, + PseudoVSOXSEG7EI64_V_M1_MF2_MASK, + PseudoVSOXSEG7EI64_V_M1_MF4, + PseudoVSOXSEG7EI64_V_M1_MF4_MASK, + PseudoVSOXSEG7EI64_V_M1_MF8, + PseudoVSOXSEG7EI64_V_M1_MF8_MASK, + PseudoVSOXSEG7EI64_V_M2_M1, + PseudoVSOXSEG7EI64_V_M2_M1_MASK, + PseudoVSOXSEG7EI64_V_M2_MF2, + PseudoVSOXSEG7EI64_V_M2_MF2_MASK, + PseudoVSOXSEG7EI64_V_M2_MF4, + PseudoVSOXSEG7EI64_V_M2_MF4_MASK, + PseudoVSOXSEG7EI64_V_M4_M1, + PseudoVSOXSEG7EI64_V_M4_M1_MASK, + PseudoVSOXSEG7EI64_V_M4_MF2, + PseudoVSOXSEG7EI64_V_M4_MF2_MASK, + PseudoVSOXSEG7EI64_V_M8_M1, + PseudoVSOXSEG7EI64_V_M8_M1_MASK, + PseudoVSOXSEG7EI8_V_M1_M1, + PseudoVSOXSEG7EI8_V_M1_M1_MASK, + PseudoVSOXSEG7EI8_V_MF2_M1, + PseudoVSOXSEG7EI8_V_MF2_M1_MASK, + PseudoVSOXSEG7EI8_V_MF2_MF2, + PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG7EI8_V_MF4_M1, + PseudoVSOXSEG7EI8_V_MF4_M1_MASK, + PseudoVSOXSEG7EI8_V_MF4_MF2, + PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG7EI8_V_MF4_MF4, + PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG7EI8_V_MF8_M1, + PseudoVSOXSEG7EI8_V_MF8_M1_MASK, + PseudoVSOXSEG7EI8_V_MF8_MF2, + PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG7EI8_V_MF8_MF4, + PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG7EI8_V_MF8_MF8, + PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, + PseudoVSOXSEG8EI16_V_M1_M1, + PseudoVSOXSEG8EI16_V_M1_M1_MASK, + PseudoVSOXSEG8EI16_V_M1_MF2, + PseudoVSOXSEG8EI16_V_M1_MF2_MASK, + PseudoVSOXSEG8EI16_V_M2_M1, + PseudoVSOXSEG8EI16_V_M2_M1_MASK, + PseudoVSOXSEG8EI16_V_MF2_M1, + PseudoVSOXSEG8EI16_V_MF2_M1_MASK, + PseudoVSOXSEG8EI16_V_MF2_MF2, + PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, + PseudoVSOXSEG8EI16_V_MF2_MF4, + PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, + PseudoVSOXSEG8EI16_V_MF4_M1, + PseudoVSOXSEG8EI16_V_MF4_M1_MASK, + PseudoVSOXSEG8EI16_V_MF4_MF2, + PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, + PseudoVSOXSEG8EI16_V_MF4_MF4, + PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, + PseudoVSOXSEG8EI16_V_MF4_MF8, + PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, + PseudoVSOXSEG8EI32_V_M1_M1, + PseudoVSOXSEG8EI32_V_M1_M1_MASK, + PseudoVSOXSEG8EI32_V_M1_MF2, + PseudoVSOXSEG8EI32_V_M1_MF2_MASK, + PseudoVSOXSEG8EI32_V_M1_MF4, + PseudoVSOXSEG8EI32_V_M1_MF4_MASK, + PseudoVSOXSEG8EI32_V_M2_M1, + PseudoVSOXSEG8EI32_V_M2_M1_MASK, + PseudoVSOXSEG8EI32_V_M2_MF2, + PseudoVSOXSEG8EI32_V_M2_MF2_MASK, + PseudoVSOXSEG8EI32_V_M4_M1, + PseudoVSOXSEG8EI32_V_M4_M1_MASK, + PseudoVSOXSEG8EI32_V_MF2_M1, + PseudoVSOXSEG8EI32_V_MF2_M1_MASK, + PseudoVSOXSEG8EI32_V_MF2_MF2, + PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, + PseudoVSOXSEG8EI32_V_MF2_MF4, + PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, + PseudoVSOXSEG8EI32_V_MF2_MF8, + PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, + PseudoVSOXSEG8EI64_V_M1_M1, + PseudoVSOXSEG8EI64_V_M1_M1_MASK, + PseudoVSOXSEG8EI64_V_M1_MF2, + PseudoVSOXSEG8EI64_V_M1_MF2_MASK, + PseudoVSOXSEG8EI64_V_M1_MF4, + PseudoVSOXSEG8EI64_V_M1_MF4_MASK, + PseudoVSOXSEG8EI64_V_M1_MF8, + PseudoVSOXSEG8EI64_V_M1_MF8_MASK, + PseudoVSOXSEG8EI64_V_M2_M1, + PseudoVSOXSEG8EI64_V_M2_M1_MASK, + PseudoVSOXSEG8EI64_V_M2_MF2, + PseudoVSOXSEG8EI64_V_M2_MF2_MASK, + PseudoVSOXSEG8EI64_V_M2_MF4, + PseudoVSOXSEG8EI64_V_M2_MF4_MASK, + PseudoVSOXSEG8EI64_V_M4_M1, + PseudoVSOXSEG8EI64_V_M4_M1_MASK, + PseudoVSOXSEG8EI64_V_M4_MF2, + PseudoVSOXSEG8EI64_V_M4_MF2_MASK, + PseudoVSOXSEG8EI64_V_M8_M1, + PseudoVSOXSEG8EI64_V_M8_M1_MASK, + PseudoVSOXSEG8EI8_V_M1_M1, + PseudoVSOXSEG8EI8_V_M1_M1_MASK, + PseudoVSOXSEG8EI8_V_MF2_M1, + PseudoVSOXSEG8EI8_V_MF2_M1_MASK, + PseudoVSOXSEG8EI8_V_MF2_MF2, + PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, + PseudoVSOXSEG8EI8_V_MF4_M1, + PseudoVSOXSEG8EI8_V_MF4_M1_MASK, + PseudoVSOXSEG8EI8_V_MF4_MF2, + PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, + PseudoVSOXSEG8EI8_V_MF4_MF4, + PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, + PseudoVSOXSEG8EI8_V_MF8_M1, + PseudoVSOXSEG8EI8_V_MF8_M1_MASK, + PseudoVSOXSEG8EI8_V_MF8_MF2, + PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, + PseudoVSOXSEG8EI8_V_MF8_MF4, + PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, + PseudoVSOXSEG8EI8_V_MF8_MF8, + PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, + PseudoVSPILL2_M1, + PseudoVSPILL2_M2, + PseudoVSPILL2_M4, + PseudoVSPILL2_MF2, + PseudoVSPILL2_MF4, + PseudoVSPILL2_MF8, + PseudoVSPILL3_M1, + PseudoVSPILL3_M2, + PseudoVSPILL3_MF2, + PseudoVSPILL3_MF4, + PseudoVSPILL3_MF8, + PseudoVSPILL4_M1, + PseudoVSPILL4_M2, + PseudoVSPILL4_MF2, + PseudoVSPILL4_MF4, + PseudoVSPILL4_MF8, + PseudoVSPILL5_M1, + PseudoVSPILL5_MF2, + PseudoVSPILL5_MF4, + PseudoVSPILL5_MF8, + PseudoVSPILL6_M1, + PseudoVSPILL6_MF2, + PseudoVSPILL6_MF4, + PseudoVSPILL6_MF8, + PseudoVSPILL7_M1, + PseudoVSPILL7_MF2, + PseudoVSPILL7_MF4, + PseudoVSPILL7_MF8, + PseudoVSPILL8_M1, + PseudoVSPILL8_MF2, + PseudoVSPILL8_MF4, + PseudoVSPILL8_MF8, + PseudoVSRA_VI_M1, + PseudoVSRA_VI_M1_MASK, + PseudoVSRA_VI_M2, + PseudoVSRA_VI_M2_MASK, + PseudoVSRA_VI_M4, + PseudoVSRA_VI_M4_MASK, + PseudoVSRA_VI_M8, + PseudoVSRA_VI_M8_MASK, + PseudoVSRA_VI_MF2, + PseudoVSRA_VI_MF2_MASK, + PseudoVSRA_VI_MF4, + PseudoVSRA_VI_MF4_MASK, + PseudoVSRA_VI_MF8, + PseudoVSRA_VI_MF8_MASK, + PseudoVSRA_VV_M1, + PseudoVSRA_VV_M1_MASK, + PseudoVSRA_VV_M2, + PseudoVSRA_VV_M2_MASK, + PseudoVSRA_VV_M4, + PseudoVSRA_VV_M4_MASK, + PseudoVSRA_VV_M8, + PseudoVSRA_VV_M8_MASK, + PseudoVSRA_VV_MF2, + PseudoVSRA_VV_MF2_MASK, + PseudoVSRA_VV_MF4, + PseudoVSRA_VV_MF4_MASK, + PseudoVSRA_VV_MF8, + PseudoVSRA_VV_MF8_MASK, + PseudoVSRA_VX_M1, + PseudoVSRA_VX_M1_MASK, + PseudoVSRA_VX_M2, + PseudoVSRA_VX_M2_MASK, + PseudoVSRA_VX_M4, + PseudoVSRA_VX_M4_MASK, + PseudoVSRA_VX_M8, + PseudoVSRA_VX_M8_MASK, + PseudoVSRA_VX_MF2, + PseudoVSRA_VX_MF2_MASK, + PseudoVSRA_VX_MF4, + PseudoVSRA_VX_MF4_MASK, + PseudoVSRA_VX_MF8, + PseudoVSRA_VX_MF8_MASK, + PseudoVSRL_VI_M1, + PseudoVSRL_VI_M1_MASK, + PseudoVSRL_VI_M2, + PseudoVSRL_VI_M2_MASK, + PseudoVSRL_VI_M4, + PseudoVSRL_VI_M4_MASK, + PseudoVSRL_VI_M8, + PseudoVSRL_VI_M8_MASK, + PseudoVSRL_VI_MF2, + PseudoVSRL_VI_MF2_MASK, + PseudoVSRL_VI_MF4, + PseudoVSRL_VI_MF4_MASK, + PseudoVSRL_VI_MF8, + PseudoVSRL_VI_MF8_MASK, + PseudoVSRL_VV_M1, + PseudoVSRL_VV_M1_MASK, + PseudoVSRL_VV_M2, + PseudoVSRL_VV_M2_MASK, + PseudoVSRL_VV_M4, + PseudoVSRL_VV_M4_MASK, + PseudoVSRL_VV_M8, + PseudoVSRL_VV_M8_MASK, + PseudoVSRL_VV_MF2, + PseudoVSRL_VV_MF2_MASK, + PseudoVSRL_VV_MF4, + PseudoVSRL_VV_MF4_MASK, + PseudoVSRL_VV_MF8, + PseudoVSRL_VV_MF8_MASK, + PseudoVSRL_VX_M1, + PseudoVSRL_VX_M1_MASK, + PseudoVSRL_VX_M2, + PseudoVSRL_VX_M2_MASK, + PseudoVSRL_VX_M4, + PseudoVSRL_VX_M4_MASK, + PseudoVSRL_VX_M8, + PseudoVSRL_VX_M8_MASK, + PseudoVSRL_VX_MF2, + PseudoVSRL_VX_MF2_MASK, + PseudoVSRL_VX_MF4, + PseudoVSRL_VX_MF4_MASK, + PseudoVSRL_VX_MF8, + PseudoVSRL_VX_MF8_MASK, + PseudoVSSE16_V_M1, + PseudoVSSE16_V_M1_MASK, + PseudoVSSE16_V_M2, + PseudoVSSE16_V_M2_MASK, + PseudoVSSE16_V_M4, + PseudoVSSE16_V_M4_MASK, + PseudoVSSE16_V_M8, + PseudoVSSE16_V_M8_MASK, + PseudoVSSE16_V_MF2, + PseudoVSSE16_V_MF2_MASK, + PseudoVSSE16_V_MF4, + PseudoVSSE16_V_MF4_MASK, + PseudoVSSE32_V_M1, + PseudoVSSE32_V_M1_MASK, + PseudoVSSE32_V_M2, + PseudoVSSE32_V_M2_MASK, + PseudoVSSE32_V_M4, + PseudoVSSE32_V_M4_MASK, + PseudoVSSE32_V_M8, + PseudoVSSE32_V_M8_MASK, + PseudoVSSE32_V_MF2, + PseudoVSSE32_V_MF2_MASK, + PseudoVSSE64_V_M1, + PseudoVSSE64_V_M1_MASK, + PseudoVSSE64_V_M2, + PseudoVSSE64_V_M2_MASK, + PseudoVSSE64_V_M4, + PseudoVSSE64_V_M4_MASK, + PseudoVSSE64_V_M8, + PseudoVSSE64_V_M8_MASK, + PseudoVSSE8_V_M1, + PseudoVSSE8_V_M1_MASK, + PseudoVSSE8_V_M2, + PseudoVSSE8_V_M2_MASK, + PseudoVSSE8_V_M4, + PseudoVSSE8_V_M4_MASK, + PseudoVSSE8_V_M8, + PseudoVSSE8_V_M8_MASK, + PseudoVSSE8_V_MF2, + PseudoVSSE8_V_MF2_MASK, + PseudoVSSE8_V_MF4, + PseudoVSSE8_V_MF4_MASK, + PseudoVSSE8_V_MF8, + PseudoVSSE8_V_MF8_MASK, + PseudoVSSEG2E16_V_M1, + PseudoVSSEG2E16_V_M1_MASK, + PseudoVSSEG2E16_V_M2, + PseudoVSSEG2E16_V_M2_MASK, + PseudoVSSEG2E16_V_M4, + PseudoVSSEG2E16_V_M4_MASK, + PseudoVSSEG2E16_V_MF2, + PseudoVSSEG2E16_V_MF2_MASK, + PseudoVSSEG2E16_V_MF4, + PseudoVSSEG2E16_V_MF4_MASK, + PseudoVSSEG2E32_V_M1, + PseudoVSSEG2E32_V_M1_MASK, + PseudoVSSEG2E32_V_M2, + PseudoVSSEG2E32_V_M2_MASK, + PseudoVSSEG2E32_V_M4, + PseudoVSSEG2E32_V_M4_MASK, + PseudoVSSEG2E32_V_MF2, + PseudoVSSEG2E32_V_MF2_MASK, + PseudoVSSEG2E64_V_M1, + PseudoVSSEG2E64_V_M1_MASK, + PseudoVSSEG2E64_V_M2, + PseudoVSSEG2E64_V_M2_MASK, + PseudoVSSEG2E64_V_M4, + PseudoVSSEG2E64_V_M4_MASK, + PseudoVSSEG2E8_V_M1, + PseudoVSSEG2E8_V_M1_MASK, + PseudoVSSEG2E8_V_M2, + PseudoVSSEG2E8_V_M2_MASK, + PseudoVSSEG2E8_V_M4, + PseudoVSSEG2E8_V_M4_MASK, + PseudoVSSEG2E8_V_MF2, + PseudoVSSEG2E8_V_MF2_MASK, + PseudoVSSEG2E8_V_MF4, + PseudoVSSEG2E8_V_MF4_MASK, + PseudoVSSEG2E8_V_MF8, + PseudoVSSEG2E8_V_MF8_MASK, + PseudoVSSEG3E16_V_M1, + PseudoVSSEG3E16_V_M1_MASK, + PseudoVSSEG3E16_V_M2, + PseudoVSSEG3E16_V_M2_MASK, + PseudoVSSEG3E16_V_MF2, + PseudoVSSEG3E16_V_MF2_MASK, + PseudoVSSEG3E16_V_MF4, + PseudoVSSEG3E16_V_MF4_MASK, + PseudoVSSEG3E32_V_M1, + PseudoVSSEG3E32_V_M1_MASK, + PseudoVSSEG3E32_V_M2, + PseudoVSSEG3E32_V_M2_MASK, + PseudoVSSEG3E32_V_MF2, + PseudoVSSEG3E32_V_MF2_MASK, + PseudoVSSEG3E64_V_M1, + PseudoVSSEG3E64_V_M1_MASK, + PseudoVSSEG3E64_V_M2, + PseudoVSSEG3E64_V_M2_MASK, + PseudoVSSEG3E8_V_M1, + PseudoVSSEG3E8_V_M1_MASK, + PseudoVSSEG3E8_V_M2, + PseudoVSSEG3E8_V_M2_MASK, + PseudoVSSEG3E8_V_MF2, + PseudoVSSEG3E8_V_MF2_MASK, + PseudoVSSEG3E8_V_MF4, + PseudoVSSEG3E8_V_MF4_MASK, + PseudoVSSEG3E8_V_MF8, + PseudoVSSEG3E8_V_MF8_MASK, + PseudoVSSEG4E16_V_M1, + PseudoVSSEG4E16_V_M1_MASK, + PseudoVSSEG4E16_V_M2, + PseudoVSSEG4E16_V_M2_MASK, + PseudoVSSEG4E16_V_MF2, + PseudoVSSEG4E16_V_MF2_MASK, + PseudoVSSEG4E16_V_MF4, + PseudoVSSEG4E16_V_MF4_MASK, + PseudoVSSEG4E32_V_M1, + PseudoVSSEG4E32_V_M1_MASK, + PseudoVSSEG4E32_V_M2, + PseudoVSSEG4E32_V_M2_MASK, + PseudoVSSEG4E32_V_MF2, + PseudoVSSEG4E32_V_MF2_MASK, + PseudoVSSEG4E64_V_M1, + PseudoVSSEG4E64_V_M1_MASK, + PseudoVSSEG4E64_V_M2, + PseudoVSSEG4E64_V_M2_MASK, + PseudoVSSEG4E8_V_M1, + PseudoVSSEG4E8_V_M1_MASK, + PseudoVSSEG4E8_V_M2, + PseudoVSSEG4E8_V_M2_MASK, + PseudoVSSEG4E8_V_MF2, + PseudoVSSEG4E8_V_MF2_MASK, + PseudoVSSEG4E8_V_MF4, + PseudoVSSEG4E8_V_MF4_MASK, + PseudoVSSEG4E8_V_MF8, + PseudoVSSEG4E8_V_MF8_MASK, + PseudoVSSEG5E16_V_M1, + PseudoVSSEG5E16_V_M1_MASK, + PseudoVSSEG5E16_V_MF2, + PseudoVSSEG5E16_V_MF2_MASK, + PseudoVSSEG5E16_V_MF4, + PseudoVSSEG5E16_V_MF4_MASK, + PseudoVSSEG5E32_V_M1, + PseudoVSSEG5E32_V_M1_MASK, + PseudoVSSEG5E32_V_MF2, + PseudoVSSEG5E32_V_MF2_MASK, + PseudoVSSEG5E64_V_M1, + PseudoVSSEG5E64_V_M1_MASK, + PseudoVSSEG5E8_V_M1, + PseudoVSSEG5E8_V_M1_MASK, + PseudoVSSEG5E8_V_MF2, + PseudoVSSEG5E8_V_MF2_MASK, + PseudoVSSEG5E8_V_MF4, + PseudoVSSEG5E8_V_MF4_MASK, + PseudoVSSEG5E8_V_MF8, + PseudoVSSEG5E8_V_MF8_MASK, + PseudoVSSEG6E16_V_M1, + PseudoVSSEG6E16_V_M1_MASK, + PseudoVSSEG6E16_V_MF2, + PseudoVSSEG6E16_V_MF2_MASK, + PseudoVSSEG6E16_V_MF4, + PseudoVSSEG6E16_V_MF4_MASK, + PseudoVSSEG6E32_V_M1, + PseudoVSSEG6E32_V_M1_MASK, + PseudoVSSEG6E32_V_MF2, + PseudoVSSEG6E32_V_MF2_MASK, + PseudoVSSEG6E64_V_M1, + PseudoVSSEG6E64_V_M1_MASK, + PseudoVSSEG6E8_V_M1, + PseudoVSSEG6E8_V_M1_MASK, + PseudoVSSEG6E8_V_MF2, + PseudoVSSEG6E8_V_MF2_MASK, + PseudoVSSEG6E8_V_MF4, + PseudoVSSEG6E8_V_MF4_MASK, + PseudoVSSEG6E8_V_MF8, + PseudoVSSEG6E8_V_MF8_MASK, + PseudoVSSEG7E16_V_M1, + PseudoVSSEG7E16_V_M1_MASK, + PseudoVSSEG7E16_V_MF2, + PseudoVSSEG7E16_V_MF2_MASK, + PseudoVSSEG7E16_V_MF4, + PseudoVSSEG7E16_V_MF4_MASK, + PseudoVSSEG7E32_V_M1, + PseudoVSSEG7E32_V_M1_MASK, + PseudoVSSEG7E32_V_MF2, + PseudoVSSEG7E32_V_MF2_MASK, + PseudoVSSEG7E64_V_M1, + PseudoVSSEG7E64_V_M1_MASK, + PseudoVSSEG7E8_V_M1, + PseudoVSSEG7E8_V_M1_MASK, + PseudoVSSEG7E8_V_MF2, + PseudoVSSEG7E8_V_MF2_MASK, + PseudoVSSEG7E8_V_MF4, + PseudoVSSEG7E8_V_MF4_MASK, + PseudoVSSEG7E8_V_MF8, + PseudoVSSEG7E8_V_MF8_MASK, + PseudoVSSEG8E16_V_M1, + PseudoVSSEG8E16_V_M1_MASK, + PseudoVSSEG8E16_V_MF2, + PseudoVSSEG8E16_V_MF2_MASK, + PseudoVSSEG8E16_V_MF4, + PseudoVSSEG8E16_V_MF4_MASK, + PseudoVSSEG8E32_V_M1, + PseudoVSSEG8E32_V_M1_MASK, + PseudoVSSEG8E32_V_MF2, + PseudoVSSEG8E32_V_MF2_MASK, + PseudoVSSEG8E64_V_M1, + PseudoVSSEG8E64_V_M1_MASK, + PseudoVSSEG8E8_V_M1, + PseudoVSSEG8E8_V_M1_MASK, + PseudoVSSEG8E8_V_MF2, + PseudoVSSEG8E8_V_MF2_MASK, + PseudoVSSEG8E8_V_MF4, + PseudoVSSEG8E8_V_MF4_MASK, + PseudoVSSEG8E8_V_MF8, + PseudoVSSEG8E8_V_MF8_MASK, + PseudoVSSRA_VI_M1, + PseudoVSSRA_VI_M1_MASK, + PseudoVSSRA_VI_M2, + PseudoVSSRA_VI_M2_MASK, + PseudoVSSRA_VI_M4, + PseudoVSSRA_VI_M4_MASK, + PseudoVSSRA_VI_M8, + PseudoVSSRA_VI_M8_MASK, + PseudoVSSRA_VI_MF2, + PseudoVSSRA_VI_MF2_MASK, + PseudoVSSRA_VI_MF4, + PseudoVSSRA_VI_MF4_MASK, + PseudoVSSRA_VI_MF8, + PseudoVSSRA_VI_MF8_MASK, + PseudoVSSRA_VV_M1, + PseudoVSSRA_VV_M1_MASK, + PseudoVSSRA_VV_M2, + PseudoVSSRA_VV_M2_MASK, + PseudoVSSRA_VV_M4, + PseudoVSSRA_VV_M4_MASK, + PseudoVSSRA_VV_M8, + PseudoVSSRA_VV_M8_MASK, + PseudoVSSRA_VV_MF2, + PseudoVSSRA_VV_MF2_MASK, + PseudoVSSRA_VV_MF4, + PseudoVSSRA_VV_MF4_MASK, + PseudoVSSRA_VV_MF8, + PseudoVSSRA_VV_MF8_MASK, + PseudoVSSRA_VX_M1, + PseudoVSSRA_VX_M1_MASK, + PseudoVSSRA_VX_M2, + PseudoVSSRA_VX_M2_MASK, + PseudoVSSRA_VX_M4, + PseudoVSSRA_VX_M4_MASK, + PseudoVSSRA_VX_M8, + PseudoVSSRA_VX_M8_MASK, + PseudoVSSRA_VX_MF2, + PseudoVSSRA_VX_MF2_MASK, + PseudoVSSRA_VX_MF4, + PseudoVSSRA_VX_MF4_MASK, + PseudoVSSRA_VX_MF8, + PseudoVSSRA_VX_MF8_MASK, + PseudoVSSRL_VI_M1, + PseudoVSSRL_VI_M1_MASK, + PseudoVSSRL_VI_M2, + PseudoVSSRL_VI_M2_MASK, + PseudoVSSRL_VI_M4, + PseudoVSSRL_VI_M4_MASK, + PseudoVSSRL_VI_M8, + PseudoVSSRL_VI_M8_MASK, + PseudoVSSRL_VI_MF2, + PseudoVSSRL_VI_MF2_MASK, + PseudoVSSRL_VI_MF4, + PseudoVSSRL_VI_MF4_MASK, + PseudoVSSRL_VI_MF8, + PseudoVSSRL_VI_MF8_MASK, + PseudoVSSRL_VV_M1, + PseudoVSSRL_VV_M1_MASK, + PseudoVSSRL_VV_M2, + PseudoVSSRL_VV_M2_MASK, + PseudoVSSRL_VV_M4, + PseudoVSSRL_VV_M4_MASK, + PseudoVSSRL_VV_M8, + PseudoVSSRL_VV_M8_MASK, + PseudoVSSRL_VV_MF2, + PseudoVSSRL_VV_MF2_MASK, + PseudoVSSRL_VV_MF4, + PseudoVSSRL_VV_MF4_MASK, + PseudoVSSRL_VV_MF8, + PseudoVSSRL_VV_MF8_MASK, + PseudoVSSRL_VX_M1, + PseudoVSSRL_VX_M1_MASK, + PseudoVSSRL_VX_M2, + PseudoVSSRL_VX_M2_MASK, + PseudoVSSRL_VX_M4, + PseudoVSSRL_VX_M4_MASK, + PseudoVSSRL_VX_M8, + PseudoVSSRL_VX_M8_MASK, + PseudoVSSRL_VX_MF2, + PseudoVSSRL_VX_MF2_MASK, + PseudoVSSRL_VX_MF4, + PseudoVSSRL_VX_MF4_MASK, + PseudoVSSRL_VX_MF8, + PseudoVSSRL_VX_MF8_MASK, + PseudoVSSSEG2E16_V_M1, + PseudoVSSSEG2E16_V_M1_MASK, + PseudoVSSSEG2E16_V_M2, + PseudoVSSSEG2E16_V_M2_MASK, + PseudoVSSSEG2E16_V_M4, + PseudoVSSSEG2E16_V_M4_MASK, + PseudoVSSSEG2E16_V_MF2, + PseudoVSSSEG2E16_V_MF2_MASK, + PseudoVSSSEG2E16_V_MF4, + PseudoVSSSEG2E16_V_MF4_MASK, + PseudoVSSSEG2E32_V_M1, + PseudoVSSSEG2E32_V_M1_MASK, + PseudoVSSSEG2E32_V_M2, + PseudoVSSSEG2E32_V_M2_MASK, + PseudoVSSSEG2E32_V_M4, + PseudoVSSSEG2E32_V_M4_MASK, + PseudoVSSSEG2E32_V_MF2, + PseudoVSSSEG2E32_V_MF2_MASK, + PseudoVSSSEG2E64_V_M1, + PseudoVSSSEG2E64_V_M1_MASK, + PseudoVSSSEG2E64_V_M2, + PseudoVSSSEG2E64_V_M2_MASK, + PseudoVSSSEG2E64_V_M4, + PseudoVSSSEG2E64_V_M4_MASK, + PseudoVSSSEG2E8_V_M1, + PseudoVSSSEG2E8_V_M1_MASK, + PseudoVSSSEG2E8_V_M2, + PseudoVSSSEG2E8_V_M2_MASK, + PseudoVSSSEG2E8_V_M4, + PseudoVSSSEG2E8_V_M4_MASK, + PseudoVSSSEG2E8_V_MF2, + PseudoVSSSEG2E8_V_MF2_MASK, + PseudoVSSSEG2E8_V_MF4, + PseudoVSSSEG2E8_V_MF4_MASK, + PseudoVSSSEG2E8_V_MF8, + PseudoVSSSEG2E8_V_MF8_MASK, + PseudoVSSSEG3E16_V_M1, + PseudoVSSSEG3E16_V_M1_MASK, + PseudoVSSSEG3E16_V_M2, + PseudoVSSSEG3E16_V_M2_MASK, + PseudoVSSSEG3E16_V_MF2, + PseudoVSSSEG3E16_V_MF2_MASK, + PseudoVSSSEG3E16_V_MF4, + PseudoVSSSEG3E16_V_MF4_MASK, + PseudoVSSSEG3E32_V_M1, + PseudoVSSSEG3E32_V_M1_MASK, + PseudoVSSSEG3E32_V_M2, + PseudoVSSSEG3E32_V_M2_MASK, + PseudoVSSSEG3E32_V_MF2, + PseudoVSSSEG3E32_V_MF2_MASK, + PseudoVSSSEG3E64_V_M1, + PseudoVSSSEG3E64_V_M1_MASK, + PseudoVSSSEG3E64_V_M2, + PseudoVSSSEG3E64_V_M2_MASK, + PseudoVSSSEG3E8_V_M1, + PseudoVSSSEG3E8_V_M1_MASK, + PseudoVSSSEG3E8_V_M2, + PseudoVSSSEG3E8_V_M2_MASK, + PseudoVSSSEG3E8_V_MF2, + PseudoVSSSEG3E8_V_MF2_MASK, + PseudoVSSSEG3E8_V_MF4, + PseudoVSSSEG3E8_V_MF4_MASK, + PseudoVSSSEG3E8_V_MF8, + PseudoVSSSEG3E8_V_MF8_MASK, + PseudoVSSSEG4E16_V_M1, + PseudoVSSSEG4E16_V_M1_MASK, + PseudoVSSSEG4E16_V_M2, + PseudoVSSSEG4E16_V_M2_MASK, + PseudoVSSSEG4E16_V_MF2, + PseudoVSSSEG4E16_V_MF2_MASK, + PseudoVSSSEG4E16_V_MF4, + PseudoVSSSEG4E16_V_MF4_MASK, + PseudoVSSSEG4E32_V_M1, + PseudoVSSSEG4E32_V_M1_MASK, + PseudoVSSSEG4E32_V_M2, + PseudoVSSSEG4E32_V_M2_MASK, + PseudoVSSSEG4E32_V_MF2, + PseudoVSSSEG4E32_V_MF2_MASK, + PseudoVSSSEG4E64_V_M1, + PseudoVSSSEG4E64_V_M1_MASK, + PseudoVSSSEG4E64_V_M2, + PseudoVSSSEG4E64_V_M2_MASK, + PseudoVSSSEG4E8_V_M1, + PseudoVSSSEG4E8_V_M1_MASK, + PseudoVSSSEG4E8_V_M2, + PseudoVSSSEG4E8_V_M2_MASK, + PseudoVSSSEG4E8_V_MF2, + PseudoVSSSEG4E8_V_MF2_MASK, + PseudoVSSSEG4E8_V_MF4, + PseudoVSSSEG4E8_V_MF4_MASK, + PseudoVSSSEG4E8_V_MF8, + PseudoVSSSEG4E8_V_MF8_MASK, + PseudoVSSSEG5E16_V_M1, + PseudoVSSSEG5E16_V_M1_MASK, + PseudoVSSSEG5E16_V_MF2, + PseudoVSSSEG5E16_V_MF2_MASK, + PseudoVSSSEG5E16_V_MF4, + PseudoVSSSEG5E16_V_MF4_MASK, + PseudoVSSSEG5E32_V_M1, + PseudoVSSSEG5E32_V_M1_MASK, + PseudoVSSSEG5E32_V_MF2, + PseudoVSSSEG5E32_V_MF2_MASK, + PseudoVSSSEG5E64_V_M1, + PseudoVSSSEG5E64_V_M1_MASK, + PseudoVSSSEG5E8_V_M1, + PseudoVSSSEG5E8_V_M1_MASK, + PseudoVSSSEG5E8_V_MF2, + PseudoVSSSEG5E8_V_MF2_MASK, + PseudoVSSSEG5E8_V_MF4, + PseudoVSSSEG5E8_V_MF4_MASK, + PseudoVSSSEG5E8_V_MF8, + PseudoVSSSEG5E8_V_MF8_MASK, + PseudoVSSSEG6E16_V_M1, + PseudoVSSSEG6E16_V_M1_MASK, + PseudoVSSSEG6E16_V_MF2, + PseudoVSSSEG6E16_V_MF2_MASK, + PseudoVSSSEG6E16_V_MF4, + PseudoVSSSEG6E16_V_MF4_MASK, + PseudoVSSSEG6E32_V_M1, + PseudoVSSSEG6E32_V_M1_MASK, + PseudoVSSSEG6E32_V_MF2, + PseudoVSSSEG6E32_V_MF2_MASK, + PseudoVSSSEG6E64_V_M1, + PseudoVSSSEG6E64_V_M1_MASK, + PseudoVSSSEG6E8_V_M1, + PseudoVSSSEG6E8_V_M1_MASK, + PseudoVSSSEG6E8_V_MF2, + PseudoVSSSEG6E8_V_MF2_MASK, + PseudoVSSSEG6E8_V_MF4, + PseudoVSSSEG6E8_V_MF4_MASK, + PseudoVSSSEG6E8_V_MF8, + PseudoVSSSEG6E8_V_MF8_MASK, + PseudoVSSSEG7E16_V_M1, + PseudoVSSSEG7E16_V_M1_MASK, + PseudoVSSSEG7E16_V_MF2, + PseudoVSSSEG7E16_V_MF2_MASK, + PseudoVSSSEG7E16_V_MF4, + PseudoVSSSEG7E16_V_MF4_MASK, + PseudoVSSSEG7E32_V_M1, + PseudoVSSSEG7E32_V_M1_MASK, + PseudoVSSSEG7E32_V_MF2, + PseudoVSSSEG7E32_V_MF2_MASK, + PseudoVSSSEG7E64_V_M1, + PseudoVSSSEG7E64_V_M1_MASK, + PseudoVSSSEG7E8_V_M1, + PseudoVSSSEG7E8_V_M1_MASK, + PseudoVSSSEG7E8_V_MF2, + PseudoVSSSEG7E8_V_MF2_MASK, + PseudoVSSSEG7E8_V_MF4, + PseudoVSSSEG7E8_V_MF4_MASK, + PseudoVSSSEG7E8_V_MF8, + PseudoVSSSEG7E8_V_MF8_MASK, + PseudoVSSSEG8E16_V_M1, + PseudoVSSSEG8E16_V_M1_MASK, + PseudoVSSSEG8E16_V_MF2, + PseudoVSSSEG8E16_V_MF2_MASK, + PseudoVSSSEG8E16_V_MF4, + PseudoVSSSEG8E16_V_MF4_MASK, + PseudoVSSSEG8E32_V_M1, + PseudoVSSSEG8E32_V_M1_MASK, + PseudoVSSSEG8E32_V_MF2, + PseudoVSSSEG8E32_V_MF2_MASK, + PseudoVSSSEG8E64_V_M1, + PseudoVSSSEG8E64_V_M1_MASK, + PseudoVSSSEG8E8_V_M1, + PseudoVSSSEG8E8_V_M1_MASK, + PseudoVSSSEG8E8_V_MF2, + PseudoVSSSEG8E8_V_MF2_MASK, + PseudoVSSSEG8E8_V_MF4, + PseudoVSSSEG8E8_V_MF4_MASK, + PseudoVSSSEG8E8_V_MF8, + PseudoVSSSEG8E8_V_MF8_MASK, + PseudoVSSUBU_VV_M1, + PseudoVSSUBU_VV_M1_MASK, + PseudoVSSUBU_VV_M2, + PseudoVSSUBU_VV_M2_MASK, + PseudoVSSUBU_VV_M4, + PseudoVSSUBU_VV_M4_MASK, + PseudoVSSUBU_VV_M8, + PseudoVSSUBU_VV_M8_MASK, + PseudoVSSUBU_VV_MF2, + PseudoVSSUBU_VV_MF2_MASK, + PseudoVSSUBU_VV_MF4, + PseudoVSSUBU_VV_MF4_MASK, + PseudoVSSUBU_VV_MF8, + PseudoVSSUBU_VV_MF8_MASK, + PseudoVSSUBU_VX_M1, + PseudoVSSUBU_VX_M1_MASK, + PseudoVSSUBU_VX_M2, + PseudoVSSUBU_VX_M2_MASK, + PseudoVSSUBU_VX_M4, + PseudoVSSUBU_VX_M4_MASK, + PseudoVSSUBU_VX_M8, + PseudoVSSUBU_VX_M8_MASK, + PseudoVSSUBU_VX_MF2, + PseudoVSSUBU_VX_MF2_MASK, + PseudoVSSUBU_VX_MF4, + PseudoVSSUBU_VX_MF4_MASK, + PseudoVSSUBU_VX_MF8, + PseudoVSSUBU_VX_MF8_MASK, + PseudoVSSUB_VV_M1, + PseudoVSSUB_VV_M1_MASK, + PseudoVSSUB_VV_M2, + PseudoVSSUB_VV_M2_MASK, + PseudoVSSUB_VV_M4, + PseudoVSSUB_VV_M4_MASK, + PseudoVSSUB_VV_M8, + PseudoVSSUB_VV_M8_MASK, + PseudoVSSUB_VV_MF2, + PseudoVSSUB_VV_MF2_MASK, + PseudoVSSUB_VV_MF4, + PseudoVSSUB_VV_MF4_MASK, + PseudoVSSUB_VV_MF8, + PseudoVSSUB_VV_MF8_MASK, + PseudoVSSUB_VX_M1, + PseudoVSSUB_VX_M1_MASK, + PseudoVSSUB_VX_M2, + PseudoVSSUB_VX_M2_MASK, + PseudoVSSUB_VX_M4, + PseudoVSSUB_VX_M4_MASK, + PseudoVSSUB_VX_M8, + PseudoVSSUB_VX_M8_MASK, + PseudoVSSUB_VX_MF2, + PseudoVSSUB_VX_MF2_MASK, + PseudoVSSUB_VX_MF4, + PseudoVSSUB_VX_MF4_MASK, + PseudoVSSUB_VX_MF8, + PseudoVSSUB_VX_MF8_MASK, + PseudoVSUB_VV_M1, + PseudoVSUB_VV_M1_MASK, + PseudoVSUB_VV_M2, + PseudoVSUB_VV_M2_MASK, + PseudoVSUB_VV_M4, + PseudoVSUB_VV_M4_MASK, + PseudoVSUB_VV_M8, + PseudoVSUB_VV_M8_MASK, + PseudoVSUB_VV_MF2, + PseudoVSUB_VV_MF2_MASK, + PseudoVSUB_VV_MF4, + PseudoVSUB_VV_MF4_MASK, + PseudoVSUB_VV_MF8, + PseudoVSUB_VV_MF8_MASK, + PseudoVSUB_VX_M1, + PseudoVSUB_VX_M1_MASK, + PseudoVSUB_VX_M2, + PseudoVSUB_VX_M2_MASK, + PseudoVSUB_VX_M4, + PseudoVSUB_VX_M4_MASK, + PseudoVSUB_VX_M8, + PseudoVSUB_VX_M8_MASK, + PseudoVSUB_VX_MF2, + PseudoVSUB_VX_MF2_MASK, + PseudoVSUB_VX_MF4, + PseudoVSUB_VX_MF4_MASK, + PseudoVSUB_VX_MF8, + PseudoVSUB_VX_MF8_MASK, + PseudoVSUXEI16_V_M1_M1, + PseudoVSUXEI16_V_M1_M1_MASK, + PseudoVSUXEI16_V_M1_M2, + PseudoVSUXEI16_V_M1_M2_MASK, + PseudoVSUXEI16_V_M1_M4, + PseudoVSUXEI16_V_M1_M4_MASK, + PseudoVSUXEI16_V_M1_MF2, + PseudoVSUXEI16_V_M1_MF2_MASK, + PseudoVSUXEI16_V_M2_M1, + PseudoVSUXEI16_V_M2_M1_MASK, + PseudoVSUXEI16_V_M2_M2, + PseudoVSUXEI16_V_M2_M2_MASK, + PseudoVSUXEI16_V_M2_M4, + PseudoVSUXEI16_V_M2_M4_MASK, + PseudoVSUXEI16_V_M2_M8, + PseudoVSUXEI16_V_M2_M8_MASK, + PseudoVSUXEI16_V_M4_M2, + PseudoVSUXEI16_V_M4_M2_MASK, + PseudoVSUXEI16_V_M4_M4, + PseudoVSUXEI16_V_M4_M4_MASK, + PseudoVSUXEI16_V_M4_M8, + PseudoVSUXEI16_V_M4_M8_MASK, + PseudoVSUXEI16_V_M8_M4, + PseudoVSUXEI16_V_M8_M4_MASK, + PseudoVSUXEI16_V_M8_M8, + PseudoVSUXEI16_V_M8_M8_MASK, + PseudoVSUXEI16_V_MF2_M1, + PseudoVSUXEI16_V_MF2_M1_MASK, + PseudoVSUXEI16_V_MF2_M2, + PseudoVSUXEI16_V_MF2_M2_MASK, + PseudoVSUXEI16_V_MF2_MF2, + PseudoVSUXEI16_V_MF2_MF2_MASK, + PseudoVSUXEI16_V_MF2_MF4, + PseudoVSUXEI16_V_MF2_MF4_MASK, + PseudoVSUXEI16_V_MF4_M1, + PseudoVSUXEI16_V_MF4_M1_MASK, + PseudoVSUXEI16_V_MF4_MF2, + PseudoVSUXEI16_V_MF4_MF2_MASK, + PseudoVSUXEI16_V_MF4_MF4, + PseudoVSUXEI16_V_MF4_MF4_MASK, + PseudoVSUXEI16_V_MF4_MF8, + PseudoVSUXEI16_V_MF4_MF8_MASK, + PseudoVSUXEI32_V_M1_M1, + PseudoVSUXEI32_V_M1_M1_MASK, + PseudoVSUXEI32_V_M1_M2, + PseudoVSUXEI32_V_M1_M2_MASK, + PseudoVSUXEI32_V_M1_MF2, + PseudoVSUXEI32_V_M1_MF2_MASK, + PseudoVSUXEI32_V_M1_MF4, + PseudoVSUXEI32_V_M1_MF4_MASK, + PseudoVSUXEI32_V_M2_M1, + PseudoVSUXEI32_V_M2_M1_MASK, + PseudoVSUXEI32_V_M2_M2, + PseudoVSUXEI32_V_M2_M2_MASK, + PseudoVSUXEI32_V_M2_M4, + PseudoVSUXEI32_V_M2_M4_MASK, + PseudoVSUXEI32_V_M2_MF2, + PseudoVSUXEI32_V_M2_MF2_MASK, + PseudoVSUXEI32_V_M4_M1, + PseudoVSUXEI32_V_M4_M1_MASK, + PseudoVSUXEI32_V_M4_M2, + PseudoVSUXEI32_V_M4_M2_MASK, + PseudoVSUXEI32_V_M4_M4, + PseudoVSUXEI32_V_M4_M4_MASK, + PseudoVSUXEI32_V_M4_M8, + PseudoVSUXEI32_V_M4_M8_MASK, + PseudoVSUXEI32_V_M8_M2, + PseudoVSUXEI32_V_M8_M2_MASK, + PseudoVSUXEI32_V_M8_M4, + PseudoVSUXEI32_V_M8_M4_MASK, + PseudoVSUXEI32_V_M8_M8, + PseudoVSUXEI32_V_M8_M8_MASK, + PseudoVSUXEI32_V_MF2_M1, + PseudoVSUXEI32_V_MF2_M1_MASK, + PseudoVSUXEI32_V_MF2_MF2, + PseudoVSUXEI32_V_MF2_MF2_MASK, + PseudoVSUXEI32_V_MF2_MF4, + PseudoVSUXEI32_V_MF2_MF4_MASK, + PseudoVSUXEI32_V_MF2_MF8, + PseudoVSUXEI32_V_MF2_MF8_MASK, + PseudoVSUXEI64_V_M1_M1, + PseudoVSUXEI64_V_M1_M1_MASK, + PseudoVSUXEI64_V_M1_MF2, + PseudoVSUXEI64_V_M1_MF2_MASK, + PseudoVSUXEI64_V_M1_MF4, + PseudoVSUXEI64_V_M1_MF4_MASK, + PseudoVSUXEI64_V_M1_MF8, + PseudoVSUXEI64_V_M1_MF8_MASK, + PseudoVSUXEI64_V_M2_M1, + PseudoVSUXEI64_V_M2_M1_MASK, + PseudoVSUXEI64_V_M2_M2, + PseudoVSUXEI64_V_M2_M2_MASK, + PseudoVSUXEI64_V_M2_MF2, + PseudoVSUXEI64_V_M2_MF2_MASK, + PseudoVSUXEI64_V_M2_MF4, + PseudoVSUXEI64_V_M2_MF4_MASK, + PseudoVSUXEI64_V_M4_M1, + PseudoVSUXEI64_V_M4_M1_MASK, + PseudoVSUXEI64_V_M4_M2, + PseudoVSUXEI64_V_M4_M2_MASK, + PseudoVSUXEI64_V_M4_M4, + PseudoVSUXEI64_V_M4_M4_MASK, + PseudoVSUXEI64_V_M4_MF2, + PseudoVSUXEI64_V_M4_MF2_MASK, + PseudoVSUXEI64_V_M8_M1, + PseudoVSUXEI64_V_M8_M1_MASK, + PseudoVSUXEI64_V_M8_M2, + PseudoVSUXEI64_V_M8_M2_MASK, + PseudoVSUXEI64_V_M8_M4, + PseudoVSUXEI64_V_M8_M4_MASK, + PseudoVSUXEI64_V_M8_M8, + PseudoVSUXEI64_V_M8_M8_MASK, + PseudoVSUXEI8_V_M1_M1, + PseudoVSUXEI8_V_M1_M1_MASK, + PseudoVSUXEI8_V_M1_M2, + PseudoVSUXEI8_V_M1_M2_MASK, + PseudoVSUXEI8_V_M1_M4, + PseudoVSUXEI8_V_M1_M4_MASK, + PseudoVSUXEI8_V_M1_M8, + PseudoVSUXEI8_V_M1_M8_MASK, + PseudoVSUXEI8_V_M2_M2, + PseudoVSUXEI8_V_M2_M2_MASK, + PseudoVSUXEI8_V_M2_M4, + PseudoVSUXEI8_V_M2_M4_MASK, + PseudoVSUXEI8_V_M2_M8, + PseudoVSUXEI8_V_M2_M8_MASK, + PseudoVSUXEI8_V_M4_M4, + PseudoVSUXEI8_V_M4_M4_MASK, + PseudoVSUXEI8_V_M4_M8, + PseudoVSUXEI8_V_M4_M8_MASK, + PseudoVSUXEI8_V_M8_M8, + PseudoVSUXEI8_V_M8_M8_MASK, + PseudoVSUXEI8_V_MF2_M1, + PseudoVSUXEI8_V_MF2_M1_MASK, + PseudoVSUXEI8_V_MF2_M2, + PseudoVSUXEI8_V_MF2_M2_MASK, + PseudoVSUXEI8_V_MF2_M4, + PseudoVSUXEI8_V_MF2_M4_MASK, + PseudoVSUXEI8_V_MF2_MF2, + PseudoVSUXEI8_V_MF2_MF2_MASK, + PseudoVSUXEI8_V_MF4_M1, + PseudoVSUXEI8_V_MF4_M1_MASK, + PseudoVSUXEI8_V_MF4_M2, + PseudoVSUXEI8_V_MF4_M2_MASK, + PseudoVSUXEI8_V_MF4_MF2, + PseudoVSUXEI8_V_MF4_MF2_MASK, + PseudoVSUXEI8_V_MF4_MF4, + PseudoVSUXEI8_V_MF4_MF4_MASK, + PseudoVSUXEI8_V_MF8_M1, + PseudoVSUXEI8_V_MF8_M1_MASK, + PseudoVSUXEI8_V_MF8_MF2, + PseudoVSUXEI8_V_MF8_MF2_MASK, + PseudoVSUXEI8_V_MF8_MF4, + PseudoVSUXEI8_V_MF8_MF4_MASK, + PseudoVSUXEI8_V_MF8_MF8, + PseudoVSUXEI8_V_MF8_MF8_MASK, + PseudoVSUXSEG2EI16_V_M1_M1, + PseudoVSUXSEG2EI16_V_M1_M1_MASK, + PseudoVSUXSEG2EI16_V_M1_M2, + PseudoVSUXSEG2EI16_V_M1_M2_MASK, + PseudoVSUXSEG2EI16_V_M1_M4, + PseudoVSUXSEG2EI16_V_M1_M4_MASK, + PseudoVSUXSEG2EI16_V_M1_MF2, + PseudoVSUXSEG2EI16_V_M1_MF2_MASK, + PseudoVSUXSEG2EI16_V_M2_M1, + PseudoVSUXSEG2EI16_V_M2_M1_MASK, + PseudoVSUXSEG2EI16_V_M2_M2, + PseudoVSUXSEG2EI16_V_M2_M2_MASK, + PseudoVSUXSEG2EI16_V_M2_M4, + PseudoVSUXSEG2EI16_V_M2_M4_MASK, + PseudoVSUXSEG2EI16_V_M4_M2, + PseudoVSUXSEG2EI16_V_M4_M2_MASK, + PseudoVSUXSEG2EI16_V_M4_M4, + PseudoVSUXSEG2EI16_V_M4_M4_MASK, + PseudoVSUXSEG2EI16_V_M8_M4, + PseudoVSUXSEG2EI16_V_M8_M4_MASK, + PseudoVSUXSEG2EI16_V_MF2_M1, + PseudoVSUXSEG2EI16_V_MF2_M1_MASK, + PseudoVSUXSEG2EI16_V_MF2_M2, + PseudoVSUXSEG2EI16_V_MF2_M2_MASK, + PseudoVSUXSEG2EI16_V_MF2_MF2, + PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG2EI16_V_MF2_MF4, + PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG2EI16_V_MF4_M1, + PseudoVSUXSEG2EI16_V_MF4_M1_MASK, + PseudoVSUXSEG2EI16_V_MF4_MF2, + PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG2EI16_V_MF4_MF4, + PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG2EI16_V_MF4_MF8, + PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG2EI32_V_M1_M1, + PseudoVSUXSEG2EI32_V_M1_M1_MASK, + PseudoVSUXSEG2EI32_V_M1_M2, + PseudoVSUXSEG2EI32_V_M1_M2_MASK, + PseudoVSUXSEG2EI32_V_M1_MF2, + PseudoVSUXSEG2EI32_V_M1_MF2_MASK, + PseudoVSUXSEG2EI32_V_M1_MF4, + PseudoVSUXSEG2EI32_V_M1_MF4_MASK, + PseudoVSUXSEG2EI32_V_M2_M1, + PseudoVSUXSEG2EI32_V_M2_M1_MASK, + PseudoVSUXSEG2EI32_V_M2_M2, + PseudoVSUXSEG2EI32_V_M2_M2_MASK, + PseudoVSUXSEG2EI32_V_M2_M4, + PseudoVSUXSEG2EI32_V_M2_M4_MASK, + PseudoVSUXSEG2EI32_V_M2_MF2, + PseudoVSUXSEG2EI32_V_M2_MF2_MASK, + PseudoVSUXSEG2EI32_V_M4_M1, + PseudoVSUXSEG2EI32_V_M4_M1_MASK, + PseudoVSUXSEG2EI32_V_M4_M2, + PseudoVSUXSEG2EI32_V_M4_M2_MASK, + PseudoVSUXSEG2EI32_V_M4_M4, + PseudoVSUXSEG2EI32_V_M4_M4_MASK, + PseudoVSUXSEG2EI32_V_M8_M2, + PseudoVSUXSEG2EI32_V_M8_M2_MASK, + PseudoVSUXSEG2EI32_V_M8_M4, + PseudoVSUXSEG2EI32_V_M8_M4_MASK, + PseudoVSUXSEG2EI32_V_MF2_M1, + PseudoVSUXSEG2EI32_V_MF2_M1_MASK, + PseudoVSUXSEG2EI32_V_MF2_MF2, + PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG2EI32_V_MF2_MF4, + PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG2EI32_V_MF2_MF8, + PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG2EI64_V_M1_M1, + PseudoVSUXSEG2EI64_V_M1_M1_MASK, + PseudoVSUXSEG2EI64_V_M1_MF2, + PseudoVSUXSEG2EI64_V_M1_MF2_MASK, + PseudoVSUXSEG2EI64_V_M1_MF4, + PseudoVSUXSEG2EI64_V_M1_MF4_MASK, + PseudoVSUXSEG2EI64_V_M1_MF8, + PseudoVSUXSEG2EI64_V_M1_MF8_MASK, + PseudoVSUXSEG2EI64_V_M2_M1, + PseudoVSUXSEG2EI64_V_M2_M1_MASK, + PseudoVSUXSEG2EI64_V_M2_M2, + PseudoVSUXSEG2EI64_V_M2_M2_MASK, + PseudoVSUXSEG2EI64_V_M2_MF2, + PseudoVSUXSEG2EI64_V_M2_MF2_MASK, + PseudoVSUXSEG2EI64_V_M2_MF4, + PseudoVSUXSEG2EI64_V_M2_MF4_MASK, + PseudoVSUXSEG2EI64_V_M4_M1, + PseudoVSUXSEG2EI64_V_M4_M1_MASK, + PseudoVSUXSEG2EI64_V_M4_M2, + PseudoVSUXSEG2EI64_V_M4_M2_MASK, + PseudoVSUXSEG2EI64_V_M4_M4, + PseudoVSUXSEG2EI64_V_M4_M4_MASK, + PseudoVSUXSEG2EI64_V_M4_MF2, + PseudoVSUXSEG2EI64_V_M4_MF2_MASK, + PseudoVSUXSEG2EI64_V_M8_M1, + PseudoVSUXSEG2EI64_V_M8_M1_MASK, + PseudoVSUXSEG2EI64_V_M8_M2, + PseudoVSUXSEG2EI64_V_M8_M2_MASK, + PseudoVSUXSEG2EI64_V_M8_M4, + PseudoVSUXSEG2EI64_V_M8_M4_MASK, + PseudoVSUXSEG2EI8_V_M1_M1, + PseudoVSUXSEG2EI8_V_M1_M1_MASK, + PseudoVSUXSEG2EI8_V_M1_M2, + PseudoVSUXSEG2EI8_V_M1_M2_MASK, + PseudoVSUXSEG2EI8_V_M1_M4, + PseudoVSUXSEG2EI8_V_M1_M4_MASK, + PseudoVSUXSEG2EI8_V_M2_M2, + PseudoVSUXSEG2EI8_V_M2_M2_MASK, + PseudoVSUXSEG2EI8_V_M2_M4, + PseudoVSUXSEG2EI8_V_M2_M4_MASK, + PseudoVSUXSEG2EI8_V_M4_M4, + PseudoVSUXSEG2EI8_V_M4_M4_MASK, + PseudoVSUXSEG2EI8_V_MF2_M1, + PseudoVSUXSEG2EI8_V_MF2_M1_MASK, + PseudoVSUXSEG2EI8_V_MF2_M2, + PseudoVSUXSEG2EI8_V_MF2_M2_MASK, + PseudoVSUXSEG2EI8_V_MF2_M4, + PseudoVSUXSEG2EI8_V_MF2_M4_MASK, + PseudoVSUXSEG2EI8_V_MF2_MF2, + PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG2EI8_V_MF4_M1, + PseudoVSUXSEG2EI8_V_MF4_M1_MASK, + PseudoVSUXSEG2EI8_V_MF4_M2, + PseudoVSUXSEG2EI8_V_MF4_M2_MASK, + PseudoVSUXSEG2EI8_V_MF4_MF2, + PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG2EI8_V_MF4_MF4, + PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG2EI8_V_MF8_M1, + PseudoVSUXSEG2EI8_V_MF8_M1_MASK, + PseudoVSUXSEG2EI8_V_MF8_MF2, + PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG2EI8_V_MF8_MF4, + PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG2EI8_V_MF8_MF8, + PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG3EI16_V_M1_M1, + PseudoVSUXSEG3EI16_V_M1_M1_MASK, + PseudoVSUXSEG3EI16_V_M1_M2, + PseudoVSUXSEG3EI16_V_M1_M2_MASK, + PseudoVSUXSEG3EI16_V_M1_MF2, + PseudoVSUXSEG3EI16_V_M1_MF2_MASK, + PseudoVSUXSEG3EI16_V_M2_M1, + PseudoVSUXSEG3EI16_V_M2_M1_MASK, + PseudoVSUXSEG3EI16_V_M2_M2, + PseudoVSUXSEG3EI16_V_M2_M2_MASK, + PseudoVSUXSEG3EI16_V_M4_M2, + PseudoVSUXSEG3EI16_V_M4_M2_MASK, + PseudoVSUXSEG3EI16_V_MF2_M1, + PseudoVSUXSEG3EI16_V_MF2_M1_MASK, + PseudoVSUXSEG3EI16_V_MF2_M2, + PseudoVSUXSEG3EI16_V_MF2_M2_MASK, + PseudoVSUXSEG3EI16_V_MF2_MF2, + PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG3EI16_V_MF2_MF4, + PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG3EI16_V_MF4_M1, + PseudoVSUXSEG3EI16_V_MF4_M1_MASK, + PseudoVSUXSEG3EI16_V_MF4_MF2, + PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG3EI16_V_MF4_MF4, + PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG3EI16_V_MF4_MF8, + PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG3EI32_V_M1_M1, + PseudoVSUXSEG3EI32_V_M1_M1_MASK, + PseudoVSUXSEG3EI32_V_M1_M2, + PseudoVSUXSEG3EI32_V_M1_M2_MASK, + PseudoVSUXSEG3EI32_V_M1_MF2, + PseudoVSUXSEG3EI32_V_M1_MF2_MASK, + PseudoVSUXSEG3EI32_V_M1_MF4, + PseudoVSUXSEG3EI32_V_M1_MF4_MASK, + PseudoVSUXSEG3EI32_V_M2_M1, + PseudoVSUXSEG3EI32_V_M2_M1_MASK, + PseudoVSUXSEG3EI32_V_M2_M2, + PseudoVSUXSEG3EI32_V_M2_M2_MASK, + PseudoVSUXSEG3EI32_V_M2_MF2, + PseudoVSUXSEG3EI32_V_M2_MF2_MASK, + PseudoVSUXSEG3EI32_V_M4_M1, + PseudoVSUXSEG3EI32_V_M4_M1_MASK, + PseudoVSUXSEG3EI32_V_M4_M2, + PseudoVSUXSEG3EI32_V_M4_M2_MASK, + PseudoVSUXSEG3EI32_V_M8_M2, + PseudoVSUXSEG3EI32_V_M8_M2_MASK, + PseudoVSUXSEG3EI32_V_MF2_M1, + PseudoVSUXSEG3EI32_V_MF2_M1_MASK, + PseudoVSUXSEG3EI32_V_MF2_MF2, + PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG3EI32_V_MF2_MF4, + PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG3EI32_V_MF2_MF8, + PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG3EI64_V_M1_M1, + PseudoVSUXSEG3EI64_V_M1_M1_MASK, + PseudoVSUXSEG3EI64_V_M1_MF2, + PseudoVSUXSEG3EI64_V_M1_MF2_MASK, + PseudoVSUXSEG3EI64_V_M1_MF4, + PseudoVSUXSEG3EI64_V_M1_MF4_MASK, + PseudoVSUXSEG3EI64_V_M1_MF8, + PseudoVSUXSEG3EI64_V_M1_MF8_MASK, + PseudoVSUXSEG3EI64_V_M2_M1, + PseudoVSUXSEG3EI64_V_M2_M1_MASK, + PseudoVSUXSEG3EI64_V_M2_M2, + PseudoVSUXSEG3EI64_V_M2_M2_MASK, + PseudoVSUXSEG3EI64_V_M2_MF2, + PseudoVSUXSEG3EI64_V_M2_MF2_MASK, + PseudoVSUXSEG3EI64_V_M2_MF4, + PseudoVSUXSEG3EI64_V_M2_MF4_MASK, + PseudoVSUXSEG3EI64_V_M4_M1, + PseudoVSUXSEG3EI64_V_M4_M1_MASK, + PseudoVSUXSEG3EI64_V_M4_M2, + PseudoVSUXSEG3EI64_V_M4_M2_MASK, + PseudoVSUXSEG3EI64_V_M4_MF2, + PseudoVSUXSEG3EI64_V_M4_MF2_MASK, + PseudoVSUXSEG3EI64_V_M8_M1, + PseudoVSUXSEG3EI64_V_M8_M1_MASK, + PseudoVSUXSEG3EI64_V_M8_M2, + PseudoVSUXSEG3EI64_V_M8_M2_MASK, + PseudoVSUXSEG3EI8_V_M1_M1, + PseudoVSUXSEG3EI8_V_M1_M1_MASK, + PseudoVSUXSEG3EI8_V_M1_M2, + PseudoVSUXSEG3EI8_V_M1_M2_MASK, + PseudoVSUXSEG3EI8_V_M2_M2, + PseudoVSUXSEG3EI8_V_M2_M2_MASK, + PseudoVSUXSEG3EI8_V_MF2_M1, + PseudoVSUXSEG3EI8_V_MF2_M1_MASK, + PseudoVSUXSEG3EI8_V_MF2_M2, + PseudoVSUXSEG3EI8_V_MF2_M2_MASK, + PseudoVSUXSEG3EI8_V_MF2_MF2, + PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG3EI8_V_MF4_M1, + PseudoVSUXSEG3EI8_V_MF4_M1_MASK, + PseudoVSUXSEG3EI8_V_MF4_M2, + PseudoVSUXSEG3EI8_V_MF4_M2_MASK, + PseudoVSUXSEG3EI8_V_MF4_MF2, + PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG3EI8_V_MF4_MF4, + PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG3EI8_V_MF8_M1, + PseudoVSUXSEG3EI8_V_MF8_M1_MASK, + PseudoVSUXSEG3EI8_V_MF8_MF2, + PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG3EI8_V_MF8_MF4, + PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG3EI8_V_MF8_MF8, + PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG4EI16_V_M1_M1, + PseudoVSUXSEG4EI16_V_M1_M1_MASK, + PseudoVSUXSEG4EI16_V_M1_M2, + PseudoVSUXSEG4EI16_V_M1_M2_MASK, + PseudoVSUXSEG4EI16_V_M1_MF2, + PseudoVSUXSEG4EI16_V_M1_MF2_MASK, + PseudoVSUXSEG4EI16_V_M2_M1, + PseudoVSUXSEG4EI16_V_M2_M1_MASK, + PseudoVSUXSEG4EI16_V_M2_M2, + PseudoVSUXSEG4EI16_V_M2_M2_MASK, + PseudoVSUXSEG4EI16_V_M4_M2, + PseudoVSUXSEG4EI16_V_M4_M2_MASK, + PseudoVSUXSEG4EI16_V_MF2_M1, + PseudoVSUXSEG4EI16_V_MF2_M1_MASK, + PseudoVSUXSEG4EI16_V_MF2_M2, + PseudoVSUXSEG4EI16_V_MF2_M2_MASK, + PseudoVSUXSEG4EI16_V_MF2_MF2, + PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG4EI16_V_MF2_MF4, + PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG4EI16_V_MF4_M1, + PseudoVSUXSEG4EI16_V_MF4_M1_MASK, + PseudoVSUXSEG4EI16_V_MF4_MF2, + PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG4EI16_V_MF4_MF4, + PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG4EI16_V_MF4_MF8, + PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG4EI32_V_M1_M1, + PseudoVSUXSEG4EI32_V_M1_M1_MASK, + PseudoVSUXSEG4EI32_V_M1_M2, + PseudoVSUXSEG4EI32_V_M1_M2_MASK, + PseudoVSUXSEG4EI32_V_M1_MF2, + PseudoVSUXSEG4EI32_V_M1_MF2_MASK, + PseudoVSUXSEG4EI32_V_M1_MF4, + PseudoVSUXSEG4EI32_V_M1_MF4_MASK, + PseudoVSUXSEG4EI32_V_M2_M1, + PseudoVSUXSEG4EI32_V_M2_M1_MASK, + PseudoVSUXSEG4EI32_V_M2_M2, + PseudoVSUXSEG4EI32_V_M2_M2_MASK, + PseudoVSUXSEG4EI32_V_M2_MF2, + PseudoVSUXSEG4EI32_V_M2_MF2_MASK, + PseudoVSUXSEG4EI32_V_M4_M1, + PseudoVSUXSEG4EI32_V_M4_M1_MASK, + PseudoVSUXSEG4EI32_V_M4_M2, + PseudoVSUXSEG4EI32_V_M4_M2_MASK, + PseudoVSUXSEG4EI32_V_M8_M2, + PseudoVSUXSEG4EI32_V_M8_M2_MASK, + PseudoVSUXSEG4EI32_V_MF2_M1, + PseudoVSUXSEG4EI32_V_MF2_M1_MASK, + PseudoVSUXSEG4EI32_V_MF2_MF2, + PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG4EI32_V_MF2_MF4, + PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG4EI32_V_MF2_MF8, + PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG4EI64_V_M1_M1, + PseudoVSUXSEG4EI64_V_M1_M1_MASK, + PseudoVSUXSEG4EI64_V_M1_MF2, + PseudoVSUXSEG4EI64_V_M1_MF2_MASK, + PseudoVSUXSEG4EI64_V_M1_MF4, + PseudoVSUXSEG4EI64_V_M1_MF4_MASK, + PseudoVSUXSEG4EI64_V_M1_MF8, + PseudoVSUXSEG4EI64_V_M1_MF8_MASK, + PseudoVSUXSEG4EI64_V_M2_M1, + PseudoVSUXSEG4EI64_V_M2_M1_MASK, + PseudoVSUXSEG4EI64_V_M2_M2, + PseudoVSUXSEG4EI64_V_M2_M2_MASK, + PseudoVSUXSEG4EI64_V_M2_MF2, + PseudoVSUXSEG4EI64_V_M2_MF2_MASK, + PseudoVSUXSEG4EI64_V_M2_MF4, + PseudoVSUXSEG4EI64_V_M2_MF4_MASK, + PseudoVSUXSEG4EI64_V_M4_M1, + PseudoVSUXSEG4EI64_V_M4_M1_MASK, + PseudoVSUXSEG4EI64_V_M4_M2, + PseudoVSUXSEG4EI64_V_M4_M2_MASK, + PseudoVSUXSEG4EI64_V_M4_MF2, + PseudoVSUXSEG4EI64_V_M4_MF2_MASK, + PseudoVSUXSEG4EI64_V_M8_M1, + PseudoVSUXSEG4EI64_V_M8_M1_MASK, + PseudoVSUXSEG4EI64_V_M8_M2, + PseudoVSUXSEG4EI64_V_M8_M2_MASK, + PseudoVSUXSEG4EI8_V_M1_M1, + PseudoVSUXSEG4EI8_V_M1_M1_MASK, + PseudoVSUXSEG4EI8_V_M1_M2, + PseudoVSUXSEG4EI8_V_M1_M2_MASK, + PseudoVSUXSEG4EI8_V_M2_M2, + PseudoVSUXSEG4EI8_V_M2_M2_MASK, + PseudoVSUXSEG4EI8_V_MF2_M1, + PseudoVSUXSEG4EI8_V_MF2_M1_MASK, + PseudoVSUXSEG4EI8_V_MF2_M2, + PseudoVSUXSEG4EI8_V_MF2_M2_MASK, + PseudoVSUXSEG4EI8_V_MF2_MF2, + PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG4EI8_V_MF4_M1, + PseudoVSUXSEG4EI8_V_MF4_M1_MASK, + PseudoVSUXSEG4EI8_V_MF4_M2, + PseudoVSUXSEG4EI8_V_MF4_M2_MASK, + PseudoVSUXSEG4EI8_V_MF4_MF2, + PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG4EI8_V_MF4_MF4, + PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG4EI8_V_MF8_M1, + PseudoVSUXSEG4EI8_V_MF8_M1_MASK, + PseudoVSUXSEG4EI8_V_MF8_MF2, + PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG4EI8_V_MF8_MF4, + PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG4EI8_V_MF8_MF8, + PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG5EI16_V_M1_M1, + PseudoVSUXSEG5EI16_V_M1_M1_MASK, + PseudoVSUXSEG5EI16_V_M1_MF2, + PseudoVSUXSEG5EI16_V_M1_MF2_MASK, + PseudoVSUXSEG5EI16_V_M2_M1, + PseudoVSUXSEG5EI16_V_M2_M1_MASK, + PseudoVSUXSEG5EI16_V_MF2_M1, + PseudoVSUXSEG5EI16_V_MF2_M1_MASK, + PseudoVSUXSEG5EI16_V_MF2_MF2, + PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG5EI16_V_MF2_MF4, + PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG5EI16_V_MF4_M1, + PseudoVSUXSEG5EI16_V_MF4_M1_MASK, + PseudoVSUXSEG5EI16_V_MF4_MF2, + PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG5EI16_V_MF4_MF4, + PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG5EI16_V_MF4_MF8, + PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG5EI32_V_M1_M1, + PseudoVSUXSEG5EI32_V_M1_M1_MASK, + PseudoVSUXSEG5EI32_V_M1_MF2, + PseudoVSUXSEG5EI32_V_M1_MF2_MASK, + PseudoVSUXSEG5EI32_V_M1_MF4, + PseudoVSUXSEG5EI32_V_M1_MF4_MASK, + PseudoVSUXSEG5EI32_V_M2_M1, + PseudoVSUXSEG5EI32_V_M2_M1_MASK, + PseudoVSUXSEG5EI32_V_M2_MF2, + PseudoVSUXSEG5EI32_V_M2_MF2_MASK, + PseudoVSUXSEG5EI32_V_M4_M1, + PseudoVSUXSEG5EI32_V_M4_M1_MASK, + PseudoVSUXSEG5EI32_V_MF2_M1, + PseudoVSUXSEG5EI32_V_MF2_M1_MASK, + PseudoVSUXSEG5EI32_V_MF2_MF2, + PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG5EI32_V_MF2_MF4, + PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG5EI32_V_MF2_MF8, + PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG5EI64_V_M1_M1, + PseudoVSUXSEG5EI64_V_M1_M1_MASK, + PseudoVSUXSEG5EI64_V_M1_MF2, + PseudoVSUXSEG5EI64_V_M1_MF2_MASK, + PseudoVSUXSEG5EI64_V_M1_MF4, + PseudoVSUXSEG5EI64_V_M1_MF4_MASK, + PseudoVSUXSEG5EI64_V_M1_MF8, + PseudoVSUXSEG5EI64_V_M1_MF8_MASK, + PseudoVSUXSEG5EI64_V_M2_M1, + PseudoVSUXSEG5EI64_V_M2_M1_MASK, + PseudoVSUXSEG5EI64_V_M2_MF2, + PseudoVSUXSEG5EI64_V_M2_MF2_MASK, + PseudoVSUXSEG5EI64_V_M2_MF4, + PseudoVSUXSEG5EI64_V_M2_MF4_MASK, + PseudoVSUXSEG5EI64_V_M4_M1, + PseudoVSUXSEG5EI64_V_M4_M1_MASK, + PseudoVSUXSEG5EI64_V_M4_MF2, + PseudoVSUXSEG5EI64_V_M4_MF2_MASK, + PseudoVSUXSEG5EI64_V_M8_M1, + PseudoVSUXSEG5EI64_V_M8_M1_MASK, + PseudoVSUXSEG5EI8_V_M1_M1, + PseudoVSUXSEG5EI8_V_M1_M1_MASK, + PseudoVSUXSEG5EI8_V_MF2_M1, + PseudoVSUXSEG5EI8_V_MF2_M1_MASK, + PseudoVSUXSEG5EI8_V_MF2_MF2, + PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG5EI8_V_MF4_M1, + PseudoVSUXSEG5EI8_V_MF4_M1_MASK, + PseudoVSUXSEG5EI8_V_MF4_MF2, + PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG5EI8_V_MF4_MF4, + PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG5EI8_V_MF8_M1, + PseudoVSUXSEG5EI8_V_MF8_M1_MASK, + PseudoVSUXSEG5EI8_V_MF8_MF2, + PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG5EI8_V_MF8_MF4, + PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG5EI8_V_MF8_MF8, + PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG6EI16_V_M1_M1, + PseudoVSUXSEG6EI16_V_M1_M1_MASK, + PseudoVSUXSEG6EI16_V_M1_MF2, + PseudoVSUXSEG6EI16_V_M1_MF2_MASK, + PseudoVSUXSEG6EI16_V_M2_M1, + PseudoVSUXSEG6EI16_V_M2_M1_MASK, + PseudoVSUXSEG6EI16_V_MF2_M1, + PseudoVSUXSEG6EI16_V_MF2_M1_MASK, + PseudoVSUXSEG6EI16_V_MF2_MF2, + PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG6EI16_V_MF2_MF4, + PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG6EI16_V_MF4_M1, + PseudoVSUXSEG6EI16_V_MF4_M1_MASK, + PseudoVSUXSEG6EI16_V_MF4_MF2, + PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG6EI16_V_MF4_MF4, + PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG6EI16_V_MF4_MF8, + PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG6EI32_V_M1_M1, + PseudoVSUXSEG6EI32_V_M1_M1_MASK, + PseudoVSUXSEG6EI32_V_M1_MF2, + PseudoVSUXSEG6EI32_V_M1_MF2_MASK, + PseudoVSUXSEG6EI32_V_M1_MF4, + PseudoVSUXSEG6EI32_V_M1_MF4_MASK, + PseudoVSUXSEG6EI32_V_M2_M1, + PseudoVSUXSEG6EI32_V_M2_M1_MASK, + PseudoVSUXSEG6EI32_V_M2_MF2, + PseudoVSUXSEG6EI32_V_M2_MF2_MASK, + PseudoVSUXSEG6EI32_V_M4_M1, + PseudoVSUXSEG6EI32_V_M4_M1_MASK, + PseudoVSUXSEG6EI32_V_MF2_M1, + PseudoVSUXSEG6EI32_V_MF2_M1_MASK, + PseudoVSUXSEG6EI32_V_MF2_MF2, + PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG6EI32_V_MF2_MF4, + PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG6EI32_V_MF2_MF8, + PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG6EI64_V_M1_M1, + PseudoVSUXSEG6EI64_V_M1_M1_MASK, + PseudoVSUXSEG6EI64_V_M1_MF2, + PseudoVSUXSEG6EI64_V_M1_MF2_MASK, + PseudoVSUXSEG6EI64_V_M1_MF4, + PseudoVSUXSEG6EI64_V_M1_MF4_MASK, + PseudoVSUXSEG6EI64_V_M1_MF8, + PseudoVSUXSEG6EI64_V_M1_MF8_MASK, + PseudoVSUXSEG6EI64_V_M2_M1, + PseudoVSUXSEG6EI64_V_M2_M1_MASK, + PseudoVSUXSEG6EI64_V_M2_MF2, + PseudoVSUXSEG6EI64_V_M2_MF2_MASK, + PseudoVSUXSEG6EI64_V_M2_MF4, + PseudoVSUXSEG6EI64_V_M2_MF4_MASK, + PseudoVSUXSEG6EI64_V_M4_M1, + PseudoVSUXSEG6EI64_V_M4_M1_MASK, + PseudoVSUXSEG6EI64_V_M4_MF2, + PseudoVSUXSEG6EI64_V_M4_MF2_MASK, + PseudoVSUXSEG6EI64_V_M8_M1, + PseudoVSUXSEG6EI64_V_M8_M1_MASK, + PseudoVSUXSEG6EI8_V_M1_M1, + PseudoVSUXSEG6EI8_V_M1_M1_MASK, + PseudoVSUXSEG6EI8_V_MF2_M1, + PseudoVSUXSEG6EI8_V_MF2_M1_MASK, + PseudoVSUXSEG6EI8_V_MF2_MF2, + PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG6EI8_V_MF4_M1, + PseudoVSUXSEG6EI8_V_MF4_M1_MASK, + PseudoVSUXSEG6EI8_V_MF4_MF2, + PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG6EI8_V_MF4_MF4, + PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG6EI8_V_MF8_M1, + PseudoVSUXSEG6EI8_V_MF8_M1_MASK, + PseudoVSUXSEG6EI8_V_MF8_MF2, + PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG6EI8_V_MF8_MF4, + PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG6EI8_V_MF8_MF8, + PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG7EI16_V_M1_M1, + PseudoVSUXSEG7EI16_V_M1_M1_MASK, + PseudoVSUXSEG7EI16_V_M1_MF2, + PseudoVSUXSEG7EI16_V_M1_MF2_MASK, + PseudoVSUXSEG7EI16_V_M2_M1, + PseudoVSUXSEG7EI16_V_M2_M1_MASK, + PseudoVSUXSEG7EI16_V_MF2_M1, + PseudoVSUXSEG7EI16_V_MF2_M1_MASK, + PseudoVSUXSEG7EI16_V_MF2_MF2, + PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG7EI16_V_MF2_MF4, + PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG7EI16_V_MF4_M1, + PseudoVSUXSEG7EI16_V_MF4_M1_MASK, + PseudoVSUXSEG7EI16_V_MF4_MF2, + PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG7EI16_V_MF4_MF4, + PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG7EI16_V_MF4_MF8, + PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG7EI32_V_M1_M1, + PseudoVSUXSEG7EI32_V_M1_M1_MASK, + PseudoVSUXSEG7EI32_V_M1_MF2, + PseudoVSUXSEG7EI32_V_M1_MF2_MASK, + PseudoVSUXSEG7EI32_V_M1_MF4, + PseudoVSUXSEG7EI32_V_M1_MF4_MASK, + PseudoVSUXSEG7EI32_V_M2_M1, + PseudoVSUXSEG7EI32_V_M2_M1_MASK, + PseudoVSUXSEG7EI32_V_M2_MF2, + PseudoVSUXSEG7EI32_V_M2_MF2_MASK, + PseudoVSUXSEG7EI32_V_M4_M1, + PseudoVSUXSEG7EI32_V_M4_M1_MASK, + PseudoVSUXSEG7EI32_V_MF2_M1, + PseudoVSUXSEG7EI32_V_MF2_M1_MASK, + PseudoVSUXSEG7EI32_V_MF2_MF2, + PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG7EI32_V_MF2_MF4, + PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG7EI32_V_MF2_MF8, + PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG7EI64_V_M1_M1, + PseudoVSUXSEG7EI64_V_M1_M1_MASK, + PseudoVSUXSEG7EI64_V_M1_MF2, + PseudoVSUXSEG7EI64_V_M1_MF2_MASK, + PseudoVSUXSEG7EI64_V_M1_MF4, + PseudoVSUXSEG7EI64_V_M1_MF4_MASK, + PseudoVSUXSEG7EI64_V_M1_MF8, + PseudoVSUXSEG7EI64_V_M1_MF8_MASK, + PseudoVSUXSEG7EI64_V_M2_M1, + PseudoVSUXSEG7EI64_V_M2_M1_MASK, + PseudoVSUXSEG7EI64_V_M2_MF2, + PseudoVSUXSEG7EI64_V_M2_MF2_MASK, + PseudoVSUXSEG7EI64_V_M2_MF4, + PseudoVSUXSEG7EI64_V_M2_MF4_MASK, + PseudoVSUXSEG7EI64_V_M4_M1, + PseudoVSUXSEG7EI64_V_M4_M1_MASK, + PseudoVSUXSEG7EI64_V_M4_MF2, + PseudoVSUXSEG7EI64_V_M4_MF2_MASK, + PseudoVSUXSEG7EI64_V_M8_M1, + PseudoVSUXSEG7EI64_V_M8_M1_MASK, + PseudoVSUXSEG7EI8_V_M1_M1, + PseudoVSUXSEG7EI8_V_M1_M1_MASK, + PseudoVSUXSEG7EI8_V_MF2_M1, + PseudoVSUXSEG7EI8_V_MF2_M1_MASK, + PseudoVSUXSEG7EI8_V_MF2_MF2, + PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG7EI8_V_MF4_M1, + PseudoVSUXSEG7EI8_V_MF4_M1_MASK, + PseudoVSUXSEG7EI8_V_MF4_MF2, + PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG7EI8_V_MF4_MF4, + PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG7EI8_V_MF8_M1, + PseudoVSUXSEG7EI8_V_MF8_M1_MASK, + PseudoVSUXSEG7EI8_V_MF8_MF2, + PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG7EI8_V_MF8_MF4, + PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG7EI8_V_MF8_MF8, + PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, + PseudoVSUXSEG8EI16_V_M1_M1, + PseudoVSUXSEG8EI16_V_M1_M1_MASK, + PseudoVSUXSEG8EI16_V_M1_MF2, + PseudoVSUXSEG8EI16_V_M1_MF2_MASK, + PseudoVSUXSEG8EI16_V_M2_M1, + PseudoVSUXSEG8EI16_V_M2_M1_MASK, + PseudoVSUXSEG8EI16_V_MF2_M1, + PseudoVSUXSEG8EI16_V_MF2_M1_MASK, + PseudoVSUXSEG8EI16_V_MF2_MF2, + PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, + PseudoVSUXSEG8EI16_V_MF2_MF4, + PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, + PseudoVSUXSEG8EI16_V_MF4_M1, + PseudoVSUXSEG8EI16_V_MF4_M1_MASK, + PseudoVSUXSEG8EI16_V_MF4_MF2, + PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, + PseudoVSUXSEG8EI16_V_MF4_MF4, + PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, + PseudoVSUXSEG8EI16_V_MF4_MF8, + PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, + PseudoVSUXSEG8EI32_V_M1_M1, + PseudoVSUXSEG8EI32_V_M1_M1_MASK, + PseudoVSUXSEG8EI32_V_M1_MF2, + PseudoVSUXSEG8EI32_V_M1_MF2_MASK, + PseudoVSUXSEG8EI32_V_M1_MF4, + PseudoVSUXSEG8EI32_V_M1_MF4_MASK, + PseudoVSUXSEG8EI32_V_M2_M1, + PseudoVSUXSEG8EI32_V_M2_M1_MASK, + PseudoVSUXSEG8EI32_V_M2_MF2, + PseudoVSUXSEG8EI32_V_M2_MF2_MASK, + PseudoVSUXSEG8EI32_V_M4_M1, + PseudoVSUXSEG8EI32_V_M4_M1_MASK, + PseudoVSUXSEG8EI32_V_MF2_M1, + PseudoVSUXSEG8EI32_V_MF2_M1_MASK, + PseudoVSUXSEG8EI32_V_MF2_MF2, + PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, + PseudoVSUXSEG8EI32_V_MF2_MF4, + PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, + PseudoVSUXSEG8EI32_V_MF2_MF8, + PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, + PseudoVSUXSEG8EI64_V_M1_M1, + PseudoVSUXSEG8EI64_V_M1_M1_MASK, + PseudoVSUXSEG8EI64_V_M1_MF2, + PseudoVSUXSEG8EI64_V_M1_MF2_MASK, + PseudoVSUXSEG8EI64_V_M1_MF4, + PseudoVSUXSEG8EI64_V_M1_MF4_MASK, + PseudoVSUXSEG8EI64_V_M1_MF8, + PseudoVSUXSEG8EI64_V_M1_MF8_MASK, + PseudoVSUXSEG8EI64_V_M2_M1, + PseudoVSUXSEG8EI64_V_M2_M1_MASK, + PseudoVSUXSEG8EI64_V_M2_MF2, + PseudoVSUXSEG8EI64_V_M2_MF2_MASK, + PseudoVSUXSEG8EI64_V_M2_MF4, + PseudoVSUXSEG8EI64_V_M2_MF4_MASK, + PseudoVSUXSEG8EI64_V_M4_M1, + PseudoVSUXSEG8EI64_V_M4_M1_MASK, + PseudoVSUXSEG8EI64_V_M4_MF2, + PseudoVSUXSEG8EI64_V_M4_MF2_MASK, + PseudoVSUXSEG8EI64_V_M8_M1, + PseudoVSUXSEG8EI64_V_M8_M1_MASK, + PseudoVSUXSEG8EI8_V_M1_M1, + PseudoVSUXSEG8EI8_V_M1_M1_MASK, + PseudoVSUXSEG8EI8_V_MF2_M1, + PseudoVSUXSEG8EI8_V_MF2_M1_MASK, + PseudoVSUXSEG8EI8_V_MF2_MF2, + PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, + PseudoVSUXSEG8EI8_V_MF4_M1, + PseudoVSUXSEG8EI8_V_MF4_M1_MASK, + PseudoVSUXSEG8EI8_V_MF4_MF2, + PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, + PseudoVSUXSEG8EI8_V_MF4_MF4, + PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, + PseudoVSUXSEG8EI8_V_MF8_M1, + PseudoVSUXSEG8EI8_V_MF8_M1_MASK, + PseudoVSUXSEG8EI8_V_MF8_MF2, + PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, + PseudoVSUXSEG8EI8_V_MF8_MF4, + PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, + PseudoVSUXSEG8EI8_V_MF8_MF8, + PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, + PseudoVWADDU_VV_M1, + PseudoVWADDU_VV_M1_MASK, + PseudoVWADDU_VV_M2, + PseudoVWADDU_VV_M2_MASK, + PseudoVWADDU_VV_M4, + PseudoVWADDU_VV_M4_MASK, + PseudoVWADDU_VV_MF2, + PseudoVWADDU_VV_MF2_MASK, + PseudoVWADDU_VV_MF4, + PseudoVWADDU_VV_MF4_MASK, + PseudoVWADDU_VV_MF8, + PseudoVWADDU_VV_MF8_MASK, + PseudoVWADDU_VX_M1, + PseudoVWADDU_VX_M1_MASK, + PseudoVWADDU_VX_M2, + PseudoVWADDU_VX_M2_MASK, + PseudoVWADDU_VX_M4, + PseudoVWADDU_VX_M4_MASK, + PseudoVWADDU_VX_MF2, + PseudoVWADDU_VX_MF2_MASK, + PseudoVWADDU_VX_MF4, + PseudoVWADDU_VX_MF4_MASK, + PseudoVWADDU_VX_MF8, + PseudoVWADDU_VX_MF8_MASK, + PseudoVWADDU_WV_M1, + PseudoVWADDU_WV_M1_MASK, + PseudoVWADDU_WV_M1_MASK_TIED, + PseudoVWADDU_WV_M1_TIED, + PseudoVWADDU_WV_M2, + PseudoVWADDU_WV_M2_MASK, + PseudoVWADDU_WV_M2_MASK_TIED, + PseudoVWADDU_WV_M2_TIED, + PseudoVWADDU_WV_M4, + PseudoVWADDU_WV_M4_MASK, + PseudoVWADDU_WV_M4_MASK_TIED, + PseudoVWADDU_WV_M4_TIED, + PseudoVWADDU_WV_MF2, + PseudoVWADDU_WV_MF2_MASK, + PseudoVWADDU_WV_MF2_MASK_TIED, + PseudoVWADDU_WV_MF2_TIED, + PseudoVWADDU_WV_MF4, + PseudoVWADDU_WV_MF4_MASK, + PseudoVWADDU_WV_MF4_MASK_TIED, + PseudoVWADDU_WV_MF4_TIED, + PseudoVWADDU_WV_MF8, + PseudoVWADDU_WV_MF8_MASK, + PseudoVWADDU_WV_MF8_MASK_TIED, + PseudoVWADDU_WV_MF8_TIED, + PseudoVWADDU_WX_M1, + PseudoVWADDU_WX_M1_MASK, + PseudoVWADDU_WX_M2, + PseudoVWADDU_WX_M2_MASK, + PseudoVWADDU_WX_M4, + PseudoVWADDU_WX_M4_MASK, + PseudoVWADDU_WX_MF2, + PseudoVWADDU_WX_MF2_MASK, + PseudoVWADDU_WX_MF4, + PseudoVWADDU_WX_MF4_MASK, + PseudoVWADDU_WX_MF8, + PseudoVWADDU_WX_MF8_MASK, + PseudoVWADD_VV_M1, + PseudoVWADD_VV_M1_MASK, + PseudoVWADD_VV_M2, + PseudoVWADD_VV_M2_MASK, + PseudoVWADD_VV_M4, + PseudoVWADD_VV_M4_MASK, + PseudoVWADD_VV_MF2, + PseudoVWADD_VV_MF2_MASK, + PseudoVWADD_VV_MF4, + PseudoVWADD_VV_MF4_MASK, + PseudoVWADD_VV_MF8, + PseudoVWADD_VV_MF8_MASK, + PseudoVWADD_VX_M1, + PseudoVWADD_VX_M1_MASK, + PseudoVWADD_VX_M2, + PseudoVWADD_VX_M2_MASK, + PseudoVWADD_VX_M4, + PseudoVWADD_VX_M4_MASK, + PseudoVWADD_VX_MF2, + PseudoVWADD_VX_MF2_MASK, + PseudoVWADD_VX_MF4, + PseudoVWADD_VX_MF4_MASK, + PseudoVWADD_VX_MF8, + PseudoVWADD_VX_MF8_MASK, + PseudoVWADD_WV_M1, + PseudoVWADD_WV_M1_MASK, + PseudoVWADD_WV_M1_MASK_TIED, + PseudoVWADD_WV_M1_TIED, + PseudoVWADD_WV_M2, + PseudoVWADD_WV_M2_MASK, + PseudoVWADD_WV_M2_MASK_TIED, + PseudoVWADD_WV_M2_TIED, + PseudoVWADD_WV_M4, + PseudoVWADD_WV_M4_MASK, + PseudoVWADD_WV_M4_MASK_TIED, + PseudoVWADD_WV_M4_TIED, + PseudoVWADD_WV_MF2, + PseudoVWADD_WV_MF2_MASK, + PseudoVWADD_WV_MF2_MASK_TIED, + PseudoVWADD_WV_MF2_TIED, + PseudoVWADD_WV_MF4, + PseudoVWADD_WV_MF4_MASK, + PseudoVWADD_WV_MF4_MASK_TIED, + PseudoVWADD_WV_MF4_TIED, + PseudoVWADD_WV_MF8, + PseudoVWADD_WV_MF8_MASK, + PseudoVWADD_WV_MF8_MASK_TIED, + PseudoVWADD_WV_MF8_TIED, + PseudoVWADD_WX_M1, + PseudoVWADD_WX_M1_MASK, + PseudoVWADD_WX_M2, + PseudoVWADD_WX_M2_MASK, + PseudoVWADD_WX_M4, + PseudoVWADD_WX_M4_MASK, + PseudoVWADD_WX_MF2, + PseudoVWADD_WX_MF2_MASK, + PseudoVWADD_WX_MF4, + PseudoVWADD_WX_MF4_MASK, + PseudoVWADD_WX_MF8, + PseudoVWADD_WX_MF8_MASK, + PseudoVWMACCSU_VV_M1, + PseudoVWMACCSU_VV_M1_MASK, + PseudoVWMACCSU_VV_M2, + PseudoVWMACCSU_VV_M2_MASK, + PseudoVWMACCSU_VV_M4, + PseudoVWMACCSU_VV_M4_MASK, + PseudoVWMACCSU_VV_MF2, + PseudoVWMACCSU_VV_MF2_MASK, + PseudoVWMACCSU_VV_MF4, + PseudoVWMACCSU_VV_MF4_MASK, + PseudoVWMACCSU_VV_MF8, + PseudoVWMACCSU_VV_MF8_MASK, + PseudoVWMACCSU_VX_M1, + PseudoVWMACCSU_VX_M1_MASK, + PseudoVWMACCSU_VX_M2, + PseudoVWMACCSU_VX_M2_MASK, + PseudoVWMACCSU_VX_M4, + PseudoVWMACCSU_VX_M4_MASK, + PseudoVWMACCSU_VX_MF2, + PseudoVWMACCSU_VX_MF2_MASK, + PseudoVWMACCSU_VX_MF4, + PseudoVWMACCSU_VX_MF4_MASK, + PseudoVWMACCSU_VX_MF8, + PseudoVWMACCSU_VX_MF8_MASK, + PseudoVWMACCUS_VX_M1, + PseudoVWMACCUS_VX_M1_MASK, + PseudoVWMACCUS_VX_M2, + PseudoVWMACCUS_VX_M2_MASK, + PseudoVWMACCUS_VX_M4, + PseudoVWMACCUS_VX_M4_MASK, + PseudoVWMACCUS_VX_MF2, + PseudoVWMACCUS_VX_MF2_MASK, + PseudoVWMACCUS_VX_MF4, + PseudoVWMACCUS_VX_MF4_MASK, + PseudoVWMACCUS_VX_MF8, + PseudoVWMACCUS_VX_MF8_MASK, + PseudoVWMACCU_VV_M1, + PseudoVWMACCU_VV_M1_MASK, + PseudoVWMACCU_VV_M2, + PseudoVWMACCU_VV_M2_MASK, + PseudoVWMACCU_VV_M4, + PseudoVWMACCU_VV_M4_MASK, + PseudoVWMACCU_VV_MF2, + PseudoVWMACCU_VV_MF2_MASK, + PseudoVWMACCU_VV_MF4, + PseudoVWMACCU_VV_MF4_MASK, + PseudoVWMACCU_VV_MF8, + PseudoVWMACCU_VV_MF8_MASK, + PseudoVWMACCU_VX_M1, + PseudoVWMACCU_VX_M1_MASK, + PseudoVWMACCU_VX_M2, + PseudoVWMACCU_VX_M2_MASK, + PseudoVWMACCU_VX_M4, + PseudoVWMACCU_VX_M4_MASK, + PseudoVWMACCU_VX_MF2, + PseudoVWMACCU_VX_MF2_MASK, + PseudoVWMACCU_VX_MF4, + PseudoVWMACCU_VX_MF4_MASK, + PseudoVWMACCU_VX_MF8, + PseudoVWMACCU_VX_MF8_MASK, + PseudoVWMACC_VV_M1, + PseudoVWMACC_VV_M1_MASK, + PseudoVWMACC_VV_M2, + PseudoVWMACC_VV_M2_MASK, + PseudoVWMACC_VV_M4, + PseudoVWMACC_VV_M4_MASK, + PseudoVWMACC_VV_MF2, + PseudoVWMACC_VV_MF2_MASK, + PseudoVWMACC_VV_MF4, + PseudoVWMACC_VV_MF4_MASK, + PseudoVWMACC_VV_MF8, + PseudoVWMACC_VV_MF8_MASK, + PseudoVWMACC_VX_M1, + PseudoVWMACC_VX_M1_MASK, + PseudoVWMACC_VX_M2, + PseudoVWMACC_VX_M2_MASK, + PseudoVWMACC_VX_M4, + PseudoVWMACC_VX_M4_MASK, + PseudoVWMACC_VX_MF2, + PseudoVWMACC_VX_MF2_MASK, + PseudoVWMACC_VX_MF4, + PseudoVWMACC_VX_MF4_MASK, + PseudoVWMACC_VX_MF8, + PseudoVWMACC_VX_MF8_MASK, + PseudoVWMULSU_VV_M1, + PseudoVWMULSU_VV_M1_MASK, + PseudoVWMULSU_VV_M2, + PseudoVWMULSU_VV_M2_MASK, + PseudoVWMULSU_VV_M4, + PseudoVWMULSU_VV_M4_MASK, + PseudoVWMULSU_VV_MF2, + PseudoVWMULSU_VV_MF2_MASK, + PseudoVWMULSU_VV_MF4, + PseudoVWMULSU_VV_MF4_MASK, + PseudoVWMULSU_VV_MF8, + PseudoVWMULSU_VV_MF8_MASK, + PseudoVWMULSU_VX_M1, + PseudoVWMULSU_VX_M1_MASK, + PseudoVWMULSU_VX_M2, + PseudoVWMULSU_VX_M2_MASK, + PseudoVWMULSU_VX_M4, + PseudoVWMULSU_VX_M4_MASK, + PseudoVWMULSU_VX_MF2, + PseudoVWMULSU_VX_MF2_MASK, + PseudoVWMULSU_VX_MF4, + PseudoVWMULSU_VX_MF4_MASK, + PseudoVWMULSU_VX_MF8, + PseudoVWMULSU_VX_MF8_MASK, + PseudoVWMULU_VV_M1, + PseudoVWMULU_VV_M1_MASK, + PseudoVWMULU_VV_M2, + PseudoVWMULU_VV_M2_MASK, + PseudoVWMULU_VV_M4, + PseudoVWMULU_VV_M4_MASK, + PseudoVWMULU_VV_MF2, + PseudoVWMULU_VV_MF2_MASK, + PseudoVWMULU_VV_MF4, + PseudoVWMULU_VV_MF4_MASK, + PseudoVWMULU_VV_MF8, + PseudoVWMULU_VV_MF8_MASK, + PseudoVWMULU_VX_M1, + PseudoVWMULU_VX_M1_MASK, + PseudoVWMULU_VX_M2, + PseudoVWMULU_VX_M2_MASK, + PseudoVWMULU_VX_M4, + PseudoVWMULU_VX_M4_MASK, + PseudoVWMULU_VX_MF2, + PseudoVWMULU_VX_MF2_MASK, + PseudoVWMULU_VX_MF4, + PseudoVWMULU_VX_MF4_MASK, + PseudoVWMULU_VX_MF8, + PseudoVWMULU_VX_MF8_MASK, + PseudoVWMUL_VV_M1, + PseudoVWMUL_VV_M1_MASK, + PseudoVWMUL_VV_M2, + PseudoVWMUL_VV_M2_MASK, + PseudoVWMUL_VV_M4, + PseudoVWMUL_VV_M4_MASK, + PseudoVWMUL_VV_MF2, + PseudoVWMUL_VV_MF2_MASK, + PseudoVWMUL_VV_MF4, + PseudoVWMUL_VV_MF4_MASK, + PseudoVWMUL_VV_MF8, + PseudoVWMUL_VV_MF8_MASK, + PseudoVWMUL_VX_M1, + PseudoVWMUL_VX_M1_MASK, + PseudoVWMUL_VX_M2, + PseudoVWMUL_VX_M2_MASK, + PseudoVWMUL_VX_M4, + PseudoVWMUL_VX_M4_MASK, + PseudoVWMUL_VX_MF2, + PseudoVWMUL_VX_MF2_MASK, + PseudoVWMUL_VX_MF4, + PseudoVWMUL_VX_MF4_MASK, + PseudoVWMUL_VX_MF8, + PseudoVWMUL_VX_MF8_MASK, + PseudoVWREDSUMU_VS_M1_E16, + PseudoVWREDSUMU_VS_M1_E16_MASK, + PseudoVWREDSUMU_VS_M1_E32, + PseudoVWREDSUMU_VS_M1_E32_MASK, + PseudoVWREDSUMU_VS_M1_E8, + PseudoVWREDSUMU_VS_M1_E8_MASK, + PseudoVWREDSUMU_VS_M2_E16, + PseudoVWREDSUMU_VS_M2_E16_MASK, + PseudoVWREDSUMU_VS_M2_E32, + PseudoVWREDSUMU_VS_M2_E32_MASK, + PseudoVWREDSUMU_VS_M2_E8, + PseudoVWREDSUMU_VS_M2_E8_MASK, + PseudoVWREDSUMU_VS_M4_E16, + PseudoVWREDSUMU_VS_M4_E16_MASK, + PseudoVWREDSUMU_VS_M4_E32, + PseudoVWREDSUMU_VS_M4_E32_MASK, + PseudoVWREDSUMU_VS_M4_E8, + PseudoVWREDSUMU_VS_M4_E8_MASK, + PseudoVWREDSUMU_VS_M8_E16, + PseudoVWREDSUMU_VS_M8_E16_MASK, + PseudoVWREDSUMU_VS_M8_E32, + PseudoVWREDSUMU_VS_M8_E32_MASK, + PseudoVWREDSUMU_VS_M8_E8, + PseudoVWREDSUMU_VS_M8_E8_MASK, + PseudoVWREDSUMU_VS_MF2_E16, + PseudoVWREDSUMU_VS_MF2_E16_MASK, + PseudoVWREDSUMU_VS_MF2_E32, + PseudoVWREDSUMU_VS_MF2_E32_MASK, + PseudoVWREDSUMU_VS_MF2_E8, + PseudoVWREDSUMU_VS_MF2_E8_MASK, + PseudoVWREDSUMU_VS_MF4_E16, + PseudoVWREDSUMU_VS_MF4_E16_MASK, + PseudoVWREDSUMU_VS_MF4_E8, + PseudoVWREDSUMU_VS_MF4_E8_MASK, + PseudoVWREDSUMU_VS_MF8_E8, + PseudoVWREDSUMU_VS_MF8_E8_MASK, + PseudoVWREDSUM_VS_M1_E16, + PseudoVWREDSUM_VS_M1_E16_MASK, + PseudoVWREDSUM_VS_M1_E32, + PseudoVWREDSUM_VS_M1_E32_MASK, + PseudoVWREDSUM_VS_M1_E8, + PseudoVWREDSUM_VS_M1_E8_MASK, + PseudoVWREDSUM_VS_M2_E16, + PseudoVWREDSUM_VS_M2_E16_MASK, + PseudoVWREDSUM_VS_M2_E32, + PseudoVWREDSUM_VS_M2_E32_MASK, + PseudoVWREDSUM_VS_M2_E8, + PseudoVWREDSUM_VS_M2_E8_MASK, + PseudoVWREDSUM_VS_M4_E16, + PseudoVWREDSUM_VS_M4_E16_MASK, + PseudoVWREDSUM_VS_M4_E32, + PseudoVWREDSUM_VS_M4_E32_MASK, + PseudoVWREDSUM_VS_M4_E8, + PseudoVWREDSUM_VS_M4_E8_MASK, + PseudoVWREDSUM_VS_M8_E16, + PseudoVWREDSUM_VS_M8_E16_MASK, + PseudoVWREDSUM_VS_M8_E32, + PseudoVWREDSUM_VS_M8_E32_MASK, + PseudoVWREDSUM_VS_M8_E8, + PseudoVWREDSUM_VS_M8_E8_MASK, + PseudoVWREDSUM_VS_MF2_E16, + PseudoVWREDSUM_VS_MF2_E16_MASK, + PseudoVWREDSUM_VS_MF2_E32, + PseudoVWREDSUM_VS_MF2_E32_MASK, + PseudoVWREDSUM_VS_MF2_E8, + PseudoVWREDSUM_VS_MF2_E8_MASK, + PseudoVWREDSUM_VS_MF4_E16, + PseudoVWREDSUM_VS_MF4_E16_MASK, + PseudoVWREDSUM_VS_MF4_E8, + PseudoVWREDSUM_VS_MF4_E8_MASK, + PseudoVWREDSUM_VS_MF8_E8, + PseudoVWREDSUM_VS_MF8_E8_MASK, + PseudoVWSLL_VI_M1, + PseudoVWSLL_VI_M1_MASK, + PseudoVWSLL_VI_M2, + PseudoVWSLL_VI_M2_MASK, + PseudoVWSLL_VI_M4, + PseudoVWSLL_VI_M4_MASK, + PseudoVWSLL_VI_MF2, + PseudoVWSLL_VI_MF2_MASK, + PseudoVWSLL_VI_MF4, + PseudoVWSLL_VI_MF4_MASK, + PseudoVWSLL_VI_MF8, + PseudoVWSLL_VI_MF8_MASK, + PseudoVWSLL_VV_M1, + PseudoVWSLL_VV_M1_MASK, + PseudoVWSLL_VV_M2, + PseudoVWSLL_VV_M2_MASK, + PseudoVWSLL_VV_M4, + PseudoVWSLL_VV_M4_MASK, + PseudoVWSLL_VV_MF2, + PseudoVWSLL_VV_MF2_MASK, + PseudoVWSLL_VV_MF4, + PseudoVWSLL_VV_MF4_MASK, + PseudoVWSLL_VV_MF8, + PseudoVWSLL_VV_MF8_MASK, + PseudoVWSLL_VX_M1, + PseudoVWSLL_VX_M1_MASK, + PseudoVWSLL_VX_M2, + PseudoVWSLL_VX_M2_MASK, + PseudoVWSLL_VX_M4, + PseudoVWSLL_VX_M4_MASK, + PseudoVWSLL_VX_MF2, + PseudoVWSLL_VX_MF2_MASK, + PseudoVWSLL_VX_MF4, + PseudoVWSLL_VX_MF4_MASK, + PseudoVWSLL_VX_MF8, + PseudoVWSLL_VX_MF8_MASK, + PseudoVWSUBU_VV_M1, + PseudoVWSUBU_VV_M1_MASK, + PseudoVWSUBU_VV_M2, + PseudoVWSUBU_VV_M2_MASK, + PseudoVWSUBU_VV_M4, + PseudoVWSUBU_VV_M4_MASK, + PseudoVWSUBU_VV_MF2, + PseudoVWSUBU_VV_MF2_MASK, + PseudoVWSUBU_VV_MF4, + PseudoVWSUBU_VV_MF4_MASK, + PseudoVWSUBU_VV_MF8, + PseudoVWSUBU_VV_MF8_MASK, + PseudoVWSUBU_VX_M1, + PseudoVWSUBU_VX_M1_MASK, + PseudoVWSUBU_VX_M2, + PseudoVWSUBU_VX_M2_MASK, + PseudoVWSUBU_VX_M4, + PseudoVWSUBU_VX_M4_MASK, + PseudoVWSUBU_VX_MF2, + PseudoVWSUBU_VX_MF2_MASK, + PseudoVWSUBU_VX_MF4, + PseudoVWSUBU_VX_MF4_MASK, + PseudoVWSUBU_VX_MF8, + PseudoVWSUBU_VX_MF8_MASK, + PseudoVWSUBU_WV_M1, + PseudoVWSUBU_WV_M1_MASK, + PseudoVWSUBU_WV_M1_MASK_TIED, + PseudoVWSUBU_WV_M1_TIED, + PseudoVWSUBU_WV_M2, + PseudoVWSUBU_WV_M2_MASK, + PseudoVWSUBU_WV_M2_MASK_TIED, + PseudoVWSUBU_WV_M2_TIED, + PseudoVWSUBU_WV_M4, + PseudoVWSUBU_WV_M4_MASK, + PseudoVWSUBU_WV_M4_MASK_TIED, + PseudoVWSUBU_WV_M4_TIED, + PseudoVWSUBU_WV_MF2, + PseudoVWSUBU_WV_MF2_MASK, + PseudoVWSUBU_WV_MF2_MASK_TIED, + PseudoVWSUBU_WV_MF2_TIED, + PseudoVWSUBU_WV_MF4, + PseudoVWSUBU_WV_MF4_MASK, + PseudoVWSUBU_WV_MF4_MASK_TIED, + PseudoVWSUBU_WV_MF4_TIED, + PseudoVWSUBU_WV_MF8, + PseudoVWSUBU_WV_MF8_MASK, + PseudoVWSUBU_WV_MF8_MASK_TIED, + PseudoVWSUBU_WV_MF8_TIED, + PseudoVWSUBU_WX_M1, + PseudoVWSUBU_WX_M1_MASK, + PseudoVWSUBU_WX_M2, + PseudoVWSUBU_WX_M2_MASK, + PseudoVWSUBU_WX_M4, + PseudoVWSUBU_WX_M4_MASK, + PseudoVWSUBU_WX_MF2, + PseudoVWSUBU_WX_MF2_MASK, + PseudoVWSUBU_WX_MF4, + PseudoVWSUBU_WX_MF4_MASK, + PseudoVWSUBU_WX_MF8, + PseudoVWSUBU_WX_MF8_MASK, + PseudoVWSUB_VV_M1, + PseudoVWSUB_VV_M1_MASK, + PseudoVWSUB_VV_M2, + PseudoVWSUB_VV_M2_MASK, + PseudoVWSUB_VV_M4, + PseudoVWSUB_VV_M4_MASK, + PseudoVWSUB_VV_MF2, + PseudoVWSUB_VV_MF2_MASK, + PseudoVWSUB_VV_MF4, + PseudoVWSUB_VV_MF4_MASK, + PseudoVWSUB_VV_MF8, + PseudoVWSUB_VV_MF8_MASK, + PseudoVWSUB_VX_M1, + PseudoVWSUB_VX_M1_MASK, + PseudoVWSUB_VX_M2, + PseudoVWSUB_VX_M2_MASK, + PseudoVWSUB_VX_M4, + PseudoVWSUB_VX_M4_MASK, + PseudoVWSUB_VX_MF2, + PseudoVWSUB_VX_MF2_MASK, + PseudoVWSUB_VX_MF4, + PseudoVWSUB_VX_MF4_MASK, + PseudoVWSUB_VX_MF8, + PseudoVWSUB_VX_MF8_MASK, + PseudoVWSUB_WV_M1, + PseudoVWSUB_WV_M1_MASK, + PseudoVWSUB_WV_M1_MASK_TIED, + PseudoVWSUB_WV_M1_TIED, + PseudoVWSUB_WV_M2, + PseudoVWSUB_WV_M2_MASK, + PseudoVWSUB_WV_M2_MASK_TIED, + PseudoVWSUB_WV_M2_TIED, + PseudoVWSUB_WV_M4, + PseudoVWSUB_WV_M4_MASK, + PseudoVWSUB_WV_M4_MASK_TIED, + PseudoVWSUB_WV_M4_TIED, + PseudoVWSUB_WV_MF2, + PseudoVWSUB_WV_MF2_MASK, + PseudoVWSUB_WV_MF2_MASK_TIED, + PseudoVWSUB_WV_MF2_TIED, + PseudoVWSUB_WV_MF4, + PseudoVWSUB_WV_MF4_MASK, + PseudoVWSUB_WV_MF4_MASK_TIED, + PseudoVWSUB_WV_MF4_TIED, + PseudoVWSUB_WV_MF8, + PseudoVWSUB_WV_MF8_MASK, + PseudoVWSUB_WV_MF8_MASK_TIED, + PseudoVWSUB_WV_MF8_TIED, + PseudoVWSUB_WX_M1, + PseudoVWSUB_WX_M1_MASK, + PseudoVWSUB_WX_M2, + PseudoVWSUB_WX_M2_MASK, + PseudoVWSUB_WX_M4, + PseudoVWSUB_WX_M4_MASK, + PseudoVWSUB_WX_MF2, + PseudoVWSUB_WX_MF2_MASK, + PseudoVWSUB_WX_MF4, + PseudoVWSUB_WX_MF4_MASK, + PseudoVWSUB_WX_MF8, + PseudoVWSUB_WX_MF8_MASK, + PseudoVXOR_VI_M1, + PseudoVXOR_VI_M1_MASK, + PseudoVXOR_VI_M2, + PseudoVXOR_VI_M2_MASK, + PseudoVXOR_VI_M4, + PseudoVXOR_VI_M4_MASK, + PseudoVXOR_VI_M8, + PseudoVXOR_VI_M8_MASK, + PseudoVXOR_VI_MF2, + PseudoVXOR_VI_MF2_MASK, + PseudoVXOR_VI_MF4, + PseudoVXOR_VI_MF4_MASK, + PseudoVXOR_VI_MF8, + PseudoVXOR_VI_MF8_MASK, + PseudoVXOR_VV_M1, + PseudoVXOR_VV_M1_MASK, + PseudoVXOR_VV_M2, + PseudoVXOR_VV_M2_MASK, + PseudoVXOR_VV_M4, + PseudoVXOR_VV_M4_MASK, + PseudoVXOR_VV_M8, + PseudoVXOR_VV_M8_MASK, + PseudoVXOR_VV_MF2, + PseudoVXOR_VV_MF2_MASK, + PseudoVXOR_VV_MF4, + PseudoVXOR_VV_MF4_MASK, + PseudoVXOR_VV_MF8, + PseudoVXOR_VV_MF8_MASK, + PseudoVXOR_VX_M1, + PseudoVXOR_VX_M1_MASK, + PseudoVXOR_VX_M2, + PseudoVXOR_VX_M2_MASK, + PseudoVXOR_VX_M4, + PseudoVXOR_VX_M4_MASK, + PseudoVXOR_VX_M8, + PseudoVXOR_VX_M8_MASK, + PseudoVXOR_VX_MF2, + PseudoVXOR_VX_MF2_MASK, + PseudoVXOR_VX_MF4, + PseudoVXOR_VX_MF4_MASK, + PseudoVXOR_VX_MF8, + PseudoVXOR_VX_MF8_MASK, + PseudoVZEXT_VF2_M1, + PseudoVZEXT_VF2_M1_MASK, + PseudoVZEXT_VF2_M2, + PseudoVZEXT_VF2_M2_MASK, + PseudoVZEXT_VF2_M4, + PseudoVZEXT_VF2_M4_MASK, + PseudoVZEXT_VF2_M8, + PseudoVZEXT_VF2_M8_MASK, + PseudoVZEXT_VF2_MF2, + PseudoVZEXT_VF2_MF2_MASK, + PseudoVZEXT_VF2_MF4, + PseudoVZEXT_VF2_MF4_MASK, + PseudoVZEXT_VF4_M1, + PseudoVZEXT_VF4_M1_MASK, + PseudoVZEXT_VF4_M2, + PseudoVZEXT_VF4_M2_MASK, + PseudoVZEXT_VF4_M4, + PseudoVZEXT_VF4_M4_MASK, + PseudoVZEXT_VF4_M8, + PseudoVZEXT_VF4_M8_MASK, + PseudoVZEXT_VF4_MF2, + PseudoVZEXT_VF4_MF2_MASK, + PseudoVZEXT_VF8_M1, + PseudoVZEXT_VF8_M1_MASK, + PseudoVZEXT_VF8_M2, + PseudoVZEXT_VF8_M2_MASK, + PseudoVZEXT_VF8_M4, + PseudoVZEXT_VF8_M4_MASK, + PseudoVZEXT_VF8_M8, + PseudoVZEXT_VF8_M8_MASK, + PseudoZEXT_H, + PseudoZEXT_W, + ReadCounterWide, + ReadFCSR, + ReadFFLAGS, + ReadFRM, + Select_FPR16INX_Using_CC_GPR, + Select_FPR16_Using_CC_GPR, + Select_FPR32INX_Using_CC_GPR, + Select_FPR32_Using_CC_GPR, + Select_FPR64IN32X_Using_CC_GPR, + Select_FPR64INX_Using_CC_GPR, + Select_FPR64_Using_CC_GPR, + Select_GPRNoX0_Using_CC_SImm16NonZero_QC, + Select_GPRNoX0_Using_CC_SImm5NonZero_QC, + Select_GPRNoX0_Using_CC_UImm16NonZero_QC, + Select_GPRNoX0_Using_CC_UImm5NonZero_QC, + Select_GPR_Using_CC_GPR, + Select_GPR_Using_CC_Imm5_Zibi, + Select_GPR_Using_CC_SImm5_CV, + Select_GPR_Using_CC_UImm7_NDS, + Select_GPR_Using_CC_UImmLog2XLen_NDS, + SetFCSR, + SetFCSRImm, + SplitF64Pseudo, + SwapFRMImm, + WriteFCSR, + WriteFCSRImm, + WriteFFLAGS, + WriteFRM, + WriteFRMImm, + WriteVXRMImm, + AADD, + AADDU, + ABS, + ABSW, + ADD, + ADDD, + ADDI, + ADDIW, + ADDW, + ADD_UW, + AES32DSI, + AES32DSMI, + AES32ESI, + AES32ESMI, + AES64DS, + AES64DSM, + AES64ES, + AES64ESM, + AES64IM, + AES64KS1I, + AES64KS2, + AMOADD_B, + AMOADD_B_AQ, + AMOADD_B_AQRL, + AMOADD_B_RL, + AMOADD_D, + AMOADD_D_AQ, + AMOADD_D_AQRL, + AMOADD_D_RL, + AMOADD_H, + AMOADD_H_AQ, + AMOADD_H_AQRL, + AMOADD_H_RL, + AMOADD_W, + AMOADD_W_AQ, + AMOADD_W_AQRL, + AMOADD_W_RL, + AMOAND_B, + AMOAND_B_AQ, + AMOAND_B_AQRL, + AMOAND_B_RL, + AMOAND_D, + AMOAND_D_AQ, + AMOAND_D_AQRL, + AMOAND_D_RL, + AMOAND_H, + AMOAND_H_AQ, + AMOAND_H_AQRL, + AMOAND_H_RL, + AMOAND_W, + AMOAND_W_AQ, + AMOAND_W_AQRL, + AMOAND_W_RL, + AMOCAS_B, + AMOCAS_B_AQ, + AMOCAS_B_AQRL, + AMOCAS_B_RL, + AMOCAS_D_RV32, + AMOCAS_D_RV32_AQ, + AMOCAS_D_RV32_AQRL, + AMOCAS_D_RV32_RL, + AMOCAS_D_RV64, + AMOCAS_D_RV64_AQ, + AMOCAS_D_RV64_AQRL, + AMOCAS_D_RV64_RL, + AMOCAS_H, + AMOCAS_H_AQ, + AMOCAS_H_AQRL, + AMOCAS_H_RL, + AMOCAS_Q, + AMOCAS_Q_AQ, + AMOCAS_Q_AQRL, + AMOCAS_Q_RL, + AMOCAS_W, + AMOCAS_W_AQ, + AMOCAS_W_AQRL, + AMOCAS_W_RL, + AMOMAXU_B, + AMOMAXU_B_AQ, + AMOMAXU_B_AQRL, + AMOMAXU_B_RL, + AMOMAXU_D, + AMOMAXU_D_AQ, + AMOMAXU_D_AQRL, + AMOMAXU_D_RL, + AMOMAXU_H, + AMOMAXU_H_AQ, + AMOMAXU_H_AQRL, + AMOMAXU_H_RL, + AMOMAXU_W, + AMOMAXU_W_AQ, + AMOMAXU_W_AQRL, + AMOMAXU_W_RL, + AMOMAX_B, + AMOMAX_B_AQ, + AMOMAX_B_AQRL, + AMOMAX_B_RL, + AMOMAX_D, + AMOMAX_D_AQ, + AMOMAX_D_AQRL, + AMOMAX_D_RL, + AMOMAX_H, + AMOMAX_H_AQ, + AMOMAX_H_AQRL, + AMOMAX_H_RL, + AMOMAX_W, + AMOMAX_W_AQ, + AMOMAX_W_AQRL, + AMOMAX_W_RL, + AMOMINU_B, + AMOMINU_B_AQ, + AMOMINU_B_AQRL, + AMOMINU_B_RL, + AMOMINU_D, + AMOMINU_D_AQ, + AMOMINU_D_AQRL, + AMOMINU_D_RL, + AMOMINU_H, + AMOMINU_H_AQ, + AMOMINU_H_AQRL, + AMOMINU_H_RL, + AMOMINU_W, + AMOMINU_W_AQ, + AMOMINU_W_AQRL, + AMOMINU_W_RL, + AMOMIN_B, + AMOMIN_B_AQ, + AMOMIN_B_AQRL, + AMOMIN_B_RL, + AMOMIN_D, + AMOMIN_D_AQ, + AMOMIN_D_AQRL, + AMOMIN_D_RL, + AMOMIN_H, + AMOMIN_H_AQ, + AMOMIN_H_AQRL, + AMOMIN_H_RL, + AMOMIN_W, + AMOMIN_W_AQ, + AMOMIN_W_AQRL, + AMOMIN_W_RL, + AMOOR_B, + AMOOR_B_AQ, + AMOOR_B_AQRL, + AMOOR_B_RL, + AMOOR_D, + AMOOR_D_AQ, + AMOOR_D_AQRL, + AMOOR_D_RL, + AMOOR_H, + AMOOR_H_AQ, + AMOOR_H_AQRL, + AMOOR_H_RL, + AMOOR_W, + AMOOR_W_AQ, + AMOOR_W_AQRL, + AMOOR_W_RL, + AMOSWAP_B, + AMOSWAP_B_AQ, + AMOSWAP_B_AQRL, + AMOSWAP_B_RL, + AMOSWAP_D, + AMOSWAP_D_AQ, + AMOSWAP_D_AQRL, + AMOSWAP_D_RL, + AMOSWAP_H, + AMOSWAP_H_AQ, + AMOSWAP_H_AQRL, + AMOSWAP_H_RL, + AMOSWAP_W, + AMOSWAP_W_AQ, + AMOSWAP_W_AQRL, + AMOSWAP_W_RL, + AMOXOR_B, + AMOXOR_B_AQ, + AMOXOR_B_AQRL, + AMOXOR_B_RL, + AMOXOR_D, + AMOXOR_D_AQ, + AMOXOR_D_AQRL, + AMOXOR_D_RL, + AMOXOR_H, + AMOXOR_H_AQ, + AMOXOR_H_AQRL, + AMOXOR_H_RL, + AMOXOR_W, + AMOXOR_W_AQ, + AMOXOR_W_AQRL, + AMOXOR_W_RL, + AND, + ANDI, + ANDN, + ASUB, + ASUBU, + AUIPC, + BCLR, + BCLRI, + BEQ, + BEQI, + BEXT, + BEXTI, + BGE, + BGEU, + BINV, + BINVI, + BLT, + BLTU, + BNE, + BNEI, + BREV8, + BSET, + BSETI, + CBO_CLEAN, + CBO_FLUSH, + CBO_INVAL, + CBO_ZERO, + CLMUL, + CLMULH, + CLMULR, + CLS, + CLSW, + CLZ, + CLZW, + CM_JALT, + CM_JT, + CM_MVA01S, + CM_MVSA01, + CM_POP, + CM_POPRET, + CM_POPRETZ, + CM_PUSH, + CPOP, + CPOPW, + CSRRC, + CSRRCI, + CSRRS, + CSRRSI, + CSRRW, + CSRRWI, + CTZ, + CTZW, + CV_ABS, + CV_ABS_B, + CV_ABS_H, + CV_ADDN, + CV_ADDNR, + CV_ADDRN, + CV_ADDRNR, + CV_ADDUN, + CV_ADDUNR, + CV_ADDURN, + CV_ADDURNR, + CV_ADD_B, + CV_ADD_DIV2, + CV_ADD_DIV4, + CV_ADD_DIV8, + CV_ADD_H, + CV_ADD_SCI_B, + CV_ADD_SCI_H, + CV_ADD_SC_B, + CV_ADD_SC_H, + CV_AND_B, + CV_AND_H, + CV_AND_SCI_B, + CV_AND_SCI_H, + CV_AND_SC_B, + CV_AND_SC_H, + CV_AVGU_B, + CV_AVGU_H, + CV_AVGU_SCI_B, + CV_AVGU_SCI_H, + CV_AVGU_SC_B, + CV_AVGU_SC_H, + CV_AVG_B, + CV_AVG_H, + CV_AVG_SCI_B, + CV_AVG_SCI_H, + CV_AVG_SC_B, + CV_AVG_SC_H, + CV_BCLR, + CV_BCLRR, + CV_BEQIMM, + CV_BITREV, + CV_BNEIMM, + CV_BSET, + CV_BSETR, + CV_CLB, + CV_CLIP, + CV_CLIPR, + CV_CLIPU, + CV_CLIPUR, + CV_CMPEQ_B, + CV_CMPEQ_H, + CV_CMPEQ_SCI_B, + CV_CMPEQ_SCI_H, + CV_CMPEQ_SC_B, + CV_CMPEQ_SC_H, + CV_CMPGEU_B, + CV_CMPGEU_H, + CV_CMPGEU_SCI_B, + CV_CMPGEU_SCI_H, + CV_CMPGEU_SC_B, + CV_CMPGEU_SC_H, + CV_CMPGE_B, + CV_CMPGE_H, + CV_CMPGE_SCI_B, + CV_CMPGE_SCI_H, + CV_CMPGE_SC_B, + CV_CMPGE_SC_H, + CV_CMPGTU_B, + CV_CMPGTU_H, + CV_CMPGTU_SCI_B, + CV_CMPGTU_SCI_H, + CV_CMPGTU_SC_B, + CV_CMPGTU_SC_H, + CV_CMPGT_B, + CV_CMPGT_H, + CV_CMPGT_SCI_B, + CV_CMPGT_SCI_H, + CV_CMPGT_SC_B, + CV_CMPGT_SC_H, + CV_CMPLEU_B, + CV_CMPLEU_H, + CV_CMPLEU_SCI_B, + CV_CMPLEU_SCI_H, + CV_CMPLEU_SC_B, + CV_CMPLEU_SC_H, + CV_CMPLE_B, + CV_CMPLE_H, + CV_CMPLE_SCI_B, + CV_CMPLE_SCI_H, + CV_CMPLE_SC_B, + CV_CMPLE_SC_H, + CV_CMPLTU_B, + CV_CMPLTU_H, + CV_CMPLTU_SCI_B, + CV_CMPLTU_SCI_H, + CV_CMPLTU_SC_B, + CV_CMPLTU_SC_H, + CV_CMPLT_B, + CV_CMPLT_H, + CV_CMPLT_SCI_B, + CV_CMPLT_SCI_H, + CV_CMPLT_SC_B, + CV_CMPLT_SC_H, + CV_CMPNE_B, + CV_CMPNE_H, + CV_CMPNE_SCI_B, + CV_CMPNE_SCI_H, + CV_CMPNE_SC_B, + CV_CMPNE_SC_H, + CV_CNT, + CV_CPLXCONJ, + CV_CPLXMUL_I, + CV_CPLXMUL_I_DIV2, + CV_CPLXMUL_I_DIV4, + CV_CPLXMUL_I_DIV8, + CV_CPLXMUL_R, + CV_CPLXMUL_R_DIV2, + CV_CPLXMUL_R_DIV4, + CV_CPLXMUL_R_DIV8, + CV_DOTSP_B, + CV_DOTSP_H, + CV_DOTSP_SCI_B, + CV_DOTSP_SCI_H, + CV_DOTSP_SC_B, + CV_DOTSP_SC_H, + CV_DOTUP_B, + CV_DOTUP_H, + CV_DOTUP_SCI_B, + CV_DOTUP_SCI_H, + CV_DOTUP_SC_B, + CV_DOTUP_SC_H, + CV_DOTUSP_B, + CV_DOTUSP_H, + CV_DOTUSP_SCI_B, + CV_DOTUSP_SCI_H, + CV_DOTUSP_SC_B, + CV_DOTUSP_SC_H, + CV_ELW, + CV_EXTBS, + CV_EXTBZ, + CV_EXTHS, + CV_EXTHZ, + CV_EXTRACT, + CV_EXTRACTR, + CV_EXTRACTU, + CV_EXTRACTUR, + CV_EXTRACTU_B, + CV_EXTRACTU_H, + CV_EXTRACT_B, + CV_EXTRACT_H, + CV_FF1, + CV_FL1, + CV_INSERT, + CV_INSERTR, + CV_INSERT_B, + CV_INSERT_H, + CV_LBU_ri_inc, + CV_LBU_rr, + CV_LBU_rr_inc, + CV_LB_ri_inc, + CV_LB_rr, + CV_LB_rr_inc, + CV_LHU_ri_inc, + CV_LHU_rr, + CV_LHU_rr_inc, + CV_LH_ri_inc, + CV_LH_rr, + CV_LH_rr_inc, + CV_LW_ri_inc, + CV_LW_rr, + CV_LW_rr_inc, + CV_MAC, + CV_MACHHSN, + CV_MACHHSRN, + CV_MACHHUN, + CV_MACHHURN, + CV_MACSN, + CV_MACSRN, + CV_MACUN, + CV_MACURN, + CV_MAX, + CV_MAXU, + CV_MAXU_B, + CV_MAXU_H, + CV_MAXU_SCI_B, + CV_MAXU_SCI_H, + CV_MAXU_SC_B, + CV_MAXU_SC_H, + CV_MAX_B, + CV_MAX_H, + CV_MAX_SCI_B, + CV_MAX_SCI_H, + CV_MAX_SC_B, + CV_MAX_SC_H, + CV_MIN, + CV_MINU, + CV_MINU_B, + CV_MINU_H, + CV_MINU_SCI_B, + CV_MINU_SCI_H, + CV_MINU_SC_B, + CV_MINU_SC_H, + CV_MIN_B, + CV_MIN_H, + CV_MIN_SCI_B, + CV_MIN_SCI_H, + CV_MIN_SC_B, + CV_MIN_SC_H, + CV_MSU, + CV_MULHHSN, + CV_MULHHSRN, + CV_MULHHUN, + CV_MULHHURN, + CV_MULSN, + CV_MULSRN, + CV_MULUN, + CV_MULURN, + CV_OR_B, + CV_OR_H, + CV_OR_SCI_B, + CV_OR_SCI_H, + CV_OR_SC_B, + CV_OR_SC_H, + CV_PACK, + CV_PACKHI_B, + CV_PACKLO_B, + CV_PACK_H, + CV_ROR, + CV_SB_ri_inc, + CV_SB_rr, + CV_SB_rr_inc, + CV_SDOTSP_B, + CV_SDOTSP_H, + CV_SDOTSP_SCI_B, + CV_SDOTSP_SCI_H, + CV_SDOTSP_SC_B, + CV_SDOTSP_SC_H, + CV_SDOTUP_B, + CV_SDOTUP_H, + CV_SDOTUP_SCI_B, + CV_SDOTUP_SCI_H, + CV_SDOTUP_SC_B, + CV_SDOTUP_SC_H, + CV_SDOTUSP_B, + CV_SDOTUSP_H, + CV_SDOTUSP_SCI_B, + CV_SDOTUSP_SCI_H, + CV_SDOTUSP_SC_B, + CV_SDOTUSP_SC_H, + CV_SHUFFLE2_B, + CV_SHUFFLE2_H, + CV_SHUFFLEI0_SCI_B, + CV_SHUFFLEI1_SCI_B, + CV_SHUFFLEI2_SCI_B, + CV_SHUFFLEI3_SCI_B, + CV_SHUFFLE_B, + CV_SHUFFLE_H, + CV_SHUFFLE_SCI_H, + CV_SH_ri_inc, + CV_SH_rr, + CV_SH_rr_inc, + CV_SLE, + CV_SLEU, + CV_SLL_B, + CV_SLL_H, + CV_SLL_SCI_B, + CV_SLL_SCI_H, + CV_SLL_SC_B, + CV_SLL_SC_H, + CV_SRA_B, + CV_SRA_H, + CV_SRA_SCI_B, + CV_SRA_SCI_H, + CV_SRA_SC_B, + CV_SRA_SC_H, + CV_SRL_B, + CV_SRL_H, + CV_SRL_SCI_B, + CV_SRL_SCI_H, + CV_SRL_SC_B, + CV_SRL_SC_H, + CV_SUBN, + CV_SUBNR, + CV_SUBRN, + CV_SUBRNR, + CV_SUBROTMJ, + CV_SUBROTMJ_DIV2, + CV_SUBROTMJ_DIV4, + CV_SUBROTMJ_DIV8, + CV_SUBUN, + CV_SUBUNR, + CV_SUBURN, + CV_SUBURNR, + CV_SUB_B, + CV_SUB_DIV2, + CV_SUB_DIV4, + CV_SUB_DIV8, + CV_SUB_H, + CV_SUB_SCI_B, + CV_SUB_SCI_H, + CV_SUB_SC_B, + CV_SUB_SC_H, + CV_SW_ri_inc, + CV_SW_rr, + CV_SW_rr_inc, + CV_XOR_B, + CV_XOR_H, + CV_XOR_SCI_B, + CV_XOR_SCI_H, + CV_XOR_SC_B, + CV_XOR_SC_H, + CZERO_EQZ, + CZERO_NEZ, + C_ADD, + C_ADDI, + C_ADDI16SP, + C_ADDI4SPN, + C_ADDIW, + C_ADDW, + C_AND, + C_ANDI, + C_BEQZ, + C_BNEZ, + C_EBREAK, + C_FLD, + C_FLDSP, + C_FLW, + C_FLWSP, + C_FSD, + C_FSDSP, + C_FSW, + C_FSWSP, + C_J, + C_JAL, + C_JALR, + C_JR, + C_LBU, + C_LD, + C_LDSP, + C_LDSP_RV32, + C_LD_RV32, + C_LH, + C_LHU, + C_LH_INX, + C_LI, + C_LUI, + C_LW, + C_LWSP, + C_LWSP_INX, + C_LW_INX, + C_MOP_1, + C_MOP_11, + C_MOP_13, + C_MOP_15, + C_MOP_3, + C_MOP_5, + C_MOP_7, + C_MOP_9, + C_MUL, + C_MV, + C_NOP, + C_NOP_HINT, + C_NOT, + C_OR, + C_SB, + C_SD, + C_SDSP, + C_SDSP_RV32, + C_SD_RV32, + C_SEXT_B, + C_SEXT_H, + C_SH, + C_SH_INX, + C_SLLI, + C_SRAI, + C_SRLI, + C_SSPOPCHK, + C_SSPUSH, + C_SUB, + C_SUBW, + C_SW, + C_SWSP, + C_SWSP_INX, + C_SW_INX, + C_UNIMP, + C_XOR, + C_ZEXT_B, + C_ZEXT_H, + C_ZEXT_W, + DIV, + DIVU, + DIVUW, + DIVW, + DRET, + EBREAK, + ECALL, + FADD_D, + FADD_D_IN32X, + FADD_D_INX, + FADD_H, + FADD_H_INX, + FADD_Q, + FADD_S, + FADD_S_INX, + FCLASS_D, + FCLASS_D_IN32X, + FCLASS_D_INX, + FCLASS_H, + FCLASS_H_INX, + FCLASS_Q, + FCLASS_S, + FCLASS_S_INX, + FCVTMOD_W_D, + FCVT_BF16_S, + FCVT_D_H, + FCVT_D_H_IN32X, + FCVT_D_H_INX, + FCVT_D_L, + FCVT_D_LU, + FCVT_D_LU_INX, + FCVT_D_L_INX, + FCVT_D_Q, + FCVT_D_S, + FCVT_D_S_IN32X, + FCVT_D_S_INX, + FCVT_D_W, + FCVT_D_WU, + FCVT_D_WU_IN32X, + FCVT_D_WU_INX, + FCVT_D_W_IN32X, + FCVT_D_W_INX, + FCVT_H_D, + FCVT_H_D_IN32X, + FCVT_H_D_INX, + FCVT_H_L, + FCVT_H_LU, + FCVT_H_LU_INX, + FCVT_H_L_INX, + FCVT_H_S, + FCVT_H_S_INX, + FCVT_H_W, + FCVT_H_WU, + FCVT_H_WU_INX, + FCVT_H_W_INX, + FCVT_LU_D, + FCVT_LU_D_INX, + FCVT_LU_H, + FCVT_LU_H_INX, + FCVT_LU_Q, + FCVT_LU_S, + FCVT_LU_S_INX, + FCVT_L_D, + FCVT_L_D_INX, + FCVT_L_H, + FCVT_L_H_INX, + FCVT_L_Q, + FCVT_L_S, + FCVT_L_S_INX, + FCVT_Q_D, + FCVT_Q_L, + FCVT_Q_LU, + FCVT_Q_S, + FCVT_Q_W, + FCVT_Q_WU, + FCVT_S_BF16, + FCVT_S_D, + FCVT_S_D_IN32X, + FCVT_S_D_INX, + FCVT_S_H, + FCVT_S_H_INX, + FCVT_S_L, + FCVT_S_LU, + FCVT_S_LU_INX, + FCVT_S_L_INX, + FCVT_S_Q, + FCVT_S_W, + FCVT_S_WU, + FCVT_S_WU_INX, + FCVT_S_W_INX, + FCVT_WU_D, + FCVT_WU_D_IN32X, + FCVT_WU_D_INX, + FCVT_WU_H, + FCVT_WU_H_INX, + FCVT_WU_Q, + FCVT_WU_S, + FCVT_WU_S_INX, + FCVT_W_D, + FCVT_W_D_IN32X, + FCVT_W_D_INX, + FCVT_W_H, + FCVT_W_H_INX, + FCVT_W_Q, + FCVT_W_S, + FCVT_W_S_INX, + FDIV_D, + FDIV_D_IN32X, + FDIV_D_INX, + FDIV_H, + FDIV_H_INX, + FDIV_Q, + FDIV_S, + FDIV_S_INX, + FENCE, + FENCE_I, + FENCE_TSO, + FEQ_D, + FEQ_D_IN32X, + FEQ_D_INX, + FEQ_H, + FEQ_H_INX, + FEQ_Q, + FEQ_S, + FEQ_S_INX, + FLD, + FLEQ_D, + FLEQ_H, + FLEQ_Q, + FLEQ_S, + FLE_D, + FLE_D_IN32X, + FLE_D_INX, + FLE_H, + FLE_H_INX, + FLE_Q, + FLE_S, + FLE_S_INX, + FLH, + FLI_D, + FLI_H, + FLI_Q, + FLI_S, + FLQ, + FLTQ_D, + FLTQ_H, + FLTQ_Q, + FLTQ_S, + FLT_D, + FLT_D_IN32X, + FLT_D_INX, + FLT_H, + FLT_H_INX, + FLT_Q, + FLT_S, + FLT_S_INX, + FLW, + FMADD_D, + FMADD_D_IN32X, + FMADD_D_INX, + FMADD_H, + FMADD_H_INX, + FMADD_Q, + FMADD_S, + FMADD_S_INX, + FMAXM_D, + FMAXM_H, + FMAXM_Q, + FMAXM_S, + FMAX_D, + FMAX_D_IN32X, + FMAX_D_INX, + FMAX_H, + FMAX_H_INX, + FMAX_Q, + FMAX_S, + FMAX_S_INX, + FMINM_D, + FMINM_H, + FMINM_Q, + FMINM_S, + FMIN_D, + FMIN_D_IN32X, + FMIN_D_INX, + FMIN_H, + FMIN_H_INX, + FMIN_Q, + FMIN_S, + FMIN_S_INX, + FMSUB_D, + FMSUB_D_IN32X, + FMSUB_D_INX, + FMSUB_H, + FMSUB_H_INX, + FMSUB_Q, + FMSUB_S, + FMSUB_S_INX, + FMUL_D, + FMUL_D_IN32X, + FMUL_D_INX, + FMUL_H, + FMUL_H_INX, + FMUL_Q, + FMUL_S, + FMUL_S_INX, + FMVH_X_D, + FMVH_X_Q, + FMVP_D_X, + FMVP_Q_X, + FMV_D_X, + FMV_H_X, + FMV_W_X, + FMV_X_D, + FMV_X_H, + FMV_X_W, + FMV_X_W_FPR64, + FNMADD_D, + FNMADD_D_IN32X, + FNMADD_D_INX, + FNMADD_H, + FNMADD_H_INX, + FNMADD_Q, + FNMADD_S, + FNMADD_S_INX, + FNMSUB_D, + FNMSUB_D_IN32X, + FNMSUB_D_INX, + FNMSUB_H, + FNMSUB_H_INX, + FNMSUB_Q, + FNMSUB_S, + FNMSUB_S_INX, + FROUNDNX_D, + FROUNDNX_H, + FROUNDNX_Q, + FROUNDNX_S, + FROUND_D, + FROUND_H, + FROUND_Q, + FROUND_S, + FSD, + FSGNJN_D, + FSGNJN_D_IN32X, + FSGNJN_D_INX, + FSGNJN_H, + FSGNJN_H_INX, + FSGNJN_Q, + FSGNJN_S, + FSGNJN_S_INX, + FSGNJX_D, + FSGNJX_D_IN32X, + FSGNJX_D_INX, + FSGNJX_H, + FSGNJX_H_INX, + FSGNJX_Q, + FSGNJX_S, + FSGNJX_S_INX, + FSGNJ_D, + FSGNJ_D_IN32X, + FSGNJ_D_INX, + FSGNJ_H, + FSGNJ_H_INX, + FSGNJ_Q, + FSGNJ_S, + FSGNJ_S_INX, + FSH, + FSQ, + FSQRT_D, + FSQRT_D_IN32X, + FSQRT_D_INX, + FSQRT_H, + FSQRT_H_INX, + FSQRT_Q, + FSQRT_S, + FSQRT_S_INX, + FSUB_D, + FSUB_D_IN32X, + FSUB_D_INX, + FSUB_H, + FSUB_H_INX, + FSUB_Q, + FSUB_S, + FSUB_S_INX, + FSW, + HFENCE_GVMA, + HFENCE_VVMA, + HINVAL_GVMA, + HINVAL_VVMA, + HLVX_HU, + HLVX_WU, + HLV_B, + HLV_BU, + HLV_D, + HLV_H, + HLV_HU, + HLV_W, + HLV_WU, + HSV_B, + HSV_D, + HSV_H, + HSV_W, + Insn16, + Insn32, + Insn48, + Insn64, + InsnB, + InsnCA, + InsnCB, + InsnCI, + InsnCIW, + InsnCJ, + InsnCL, + InsnCR, + InsnCS, + InsnCSS, + InsnI, + InsnI_Mem, + InsnJ, + InsnQC_EAI, + InsnQC_EB, + InsnQC_EI, + InsnQC_EI_Mem, + InsnQC_EJ, + InsnQC_ES, + InsnR, + InsnR4, + InsnS, + InsnU, + JAL, + JALR, + LB, + LBU, + LB_AQ, + LB_AQRL, + LD, + LD_AQ, + LD_AQRL, + LD_RV32, + LH, + LHU, + LH_AQ, + LH_AQRL, + LH_INX, + LR_D, + LR_D_AQ, + LR_D_AQRL, + LR_D_RL, + LR_W, + LR_W_AQ, + LR_W_AQRL, + LR_W_RL, + LUI, + LW, + LWU, + LW_AQ, + LW_AQRL, + LW_INX, + MACCSU_H00, + MACCSU_H11, + MACCSU_W00, + MACCSU_W11, + MACCU_H00, + MACCU_H01, + MACCU_H11, + MACCU_W00, + MACCU_W01, + MACCU_W11, + MACC_H00, + MACC_H01, + MACC_H11, + MACC_W00, + MACC_W01, + MACC_W11, + MAX, + MAXU, + MERGE, + MHACC, + MHACCSU, + MHACCSU_H0, + MHACCSU_H1, + MHACCU, + MHACC_H0, + MHACC_H1, + MHRACC, + MHRACCSU, + MHRACCU, + MIN, + MINU, + MIPS_CCMOV, + MIPS_EHB, + MIPS_IHB, + MIPS_LDP, + MIPS_LWP, + MIPS_PAUSE, + MIPS_PREF, + MIPS_SDP, + MIPS_SWP, + MNRET, + MOP_RR_0, + MOP_RR_1, + MOP_RR_2, + MOP_RR_3, + MOP_RR_4, + MOP_RR_5, + MOP_RR_6, + MOP_RR_7, + MOP_R_0, + MOP_R_1, + MOP_R_10, + MOP_R_11, + MOP_R_12, + MOP_R_13, + MOP_R_14, + MOP_R_15, + MOP_R_16, + MOP_R_17, + MOP_R_18, + MOP_R_19, + MOP_R_2, + MOP_R_20, + MOP_R_21, + MOP_R_22, + MOP_R_23, + MOP_R_24, + MOP_R_25, + MOP_R_26, + MOP_R_27, + MOP_R_28, + MOP_R_29, + MOP_R_3, + MOP_R_30, + MOP_R_31, + MOP_R_4, + MOP_R_5, + MOP_R_6, + MOP_R_7, + MOP_R_8, + MOP_R_9, + MQACC_H00, + MQACC_H01, + MQACC_H11, + MQACC_W00, + MQACC_W01, + MQACC_W11, + MQRACC_H00, + MQRACC_H01, + MQRACC_H11, + MQRACC_W00, + MQRACC_W01, + MQRACC_W11, + MRET, + MSEQ, + MSLT, + MSLTU, + MUL, + MULH, + MULHR, + MULHRSU, + MULHRU, + MULHSU, + MULHSU_H0, + MULHSU_H1, + MULHU, + MULH_H0, + MULH_H1, + MULQ, + MULQR, + MULSU_H00, + MULSU_H11, + MULSU_W00, + MULSU_W11, + MULU_H00, + MULU_H01, + MULU_H11, + MULU_W00, + MULU_W01, + MULU_W11, + MULW, + MUL_H00, + MUL_H01, + MUL_H11, + MUL_W00, + MUL_W01, + MUL_W11, + MVM, + MVMN, + NCLIP, + NCLIPI, + NCLIPIU, + NCLIPR, + NCLIPRI, + NCLIPRIU, + NCLIPRU, + NCLIPU, + NDS_ADDIGP, + NDS_BBC, + NDS_BBS, + NDS_BEQC, + NDS_BFOS, + NDS_BFOZ, + NDS_BNEC, + NDS_FCVT_BF16_S, + NDS_FCVT_S_BF16, + NDS_FFB, + NDS_FFMISM, + NDS_FFZMISM, + NDS_FLMISM, + NDS_FMV_BF16_X, + NDS_FMV_X_BF16, + NDS_LBGP, + NDS_LBUGP, + NDS_LDGP, + NDS_LEA_B_ZE, + NDS_LEA_D, + NDS_LEA_D_ZE, + NDS_LEA_H, + NDS_LEA_H_ZE, + NDS_LEA_W, + NDS_LEA_W_ZE, + NDS_LHGP, + NDS_LHUGP, + NDS_LWGP, + NDS_LWUGP, + NDS_SBGP, + NDS_SDGP, + NDS_SHGP, + NDS_SWGP, + NDS_VD4DOTSU_VV, + NDS_VD4DOTS_VV, + NDS_VD4DOTU_VV, + NDS_VFNCVT_BF16_S, + NDS_VFPMADB_VF, + NDS_VFPMADT_VF, + NDS_VFWCVT_F_B, + NDS_VFWCVT_F_BU, + NDS_VFWCVT_F_N, + NDS_VFWCVT_F_NU, + NDS_VFWCVT_S_BF16, + NDS_VLE4_V, + NDS_VLN8_V, + NDS_VLNU8_V, + NSARI, + NSRA, + NSRAI, + NSRAR, + NSRL, + NSRLI, + OR, + ORC_B, + ORI, + ORN, + PAADDU_B, + PAADDU_DB, + PAADDU_DH, + PAADDU_DW, + PAADDU_H, + PAADDU_W, + PAADD_B, + PAADD_DB, + PAADD_DH, + PAADD_DW, + PAADD_H, + PAADD_W, + PAAS_HX, + PAAS_WX, + PAAX_DHX, + PABDSUMAU_B, + PABDSUMU_B, + PABDU_B, + PABDU_DB, + PABDU_DH, + PABDU_H, + PABD_B, + PABD_DB, + PABD_DH, + PABD_H, + PACK, + PACKH, + PACKW, + PADD_B, + PADD_BS, + PADD_DB, + PADD_DBS, + PADD_DH, + PADD_DHS, + PADD_DW, + PADD_DWS, + PADD_H, + PADD_HS, + PADD_W, + PADD_WS, + PASA_DHX, + PASA_HX, + PASA_WX, + PASUBU_B, + PASUBU_DB, + PASUBU_DH, + PASUBU_DW, + PASUBU_H, + PASUBU_W, + PASUB_B, + PASUB_DB, + PASUB_DH, + PASUB_DW, + PASUB_H, + PASUB_W, + PAS_DHX, + PAS_HX, + PAS_WX, + PLI_B, + PLI_DB, + PLI_DH, + PLI_H, + PLI_W, + PLUI_DH, + PLUI_H, + PLUI_W, + PM2ADDASU_H, + PM2ADDASU_W, + PM2ADDAU_H, + PM2ADDAU_W, + PM2ADDA_H, + PM2ADDA_HX, + PM2ADDA_W, + PM2ADDA_WX, + PM2ADDSU_H, + PM2ADDSU_W, + PM2ADDU_H, + PM2ADDU_W, + PM2ADD_H, + PM2ADD_HX, + PM2ADD_W, + PM2ADD_WX, + PM2SADD_H, + PM2SADD_HX, + PM2SUBA_H, + PM2SUBA_HX, + PM2SUBA_W, + PM2SUBA_WX, + PM2SUB_H, + PM2SUB_HX, + PM2SUB_W, + PM2SUB_WX, + PM2WADDASU_H, + PM2WADDAU_H, + PM2WADDA_H, + PM2WADDA_HX, + PM2WADDSU_H, + PM2WADDU_H, + PM2WADD_H, + PM2WADD_HX, + PM2WSUBA_H, + PM2WSUBA_HX, + PM2WSUB_H, + PM2WSUB_HX, + PM4ADDASU_B, + PM4ADDASU_H, + PM4ADDAU_B, + PM4ADDAU_H, + PM4ADDA_B, + PM4ADDA_H, + PM4ADDSU_B, + PM4ADDSU_H, + PM4ADDU_B, + PM4ADDU_H, + PM4ADD_B, + PM4ADD_H, + PMACCSU_W_H00, + PMACCSU_W_H11, + PMACCU_W_H00, + PMACCU_W_H01, + PMACCU_W_H11, + PMACC_W_H00, + PMACC_W_H01, + PMACC_W_H11, + PMAXU_B, + PMAXU_DB, + PMAXU_DH, + PMAXU_DW, + PMAXU_H, + PMAXU_W, + PMAX_B, + PMAX_DB, + PMAX_DH, + PMAX_DW, + PMAX_H, + PMAX_W, + PMHACCSU_H, + PMHACCSU_H_B0, + PMHACCSU_H_B1, + PMHACCSU_W, + PMHACCSU_W_H0, + PMHACCSU_W_H1, + PMHACCU_H, + PMHACCU_W, + PMHACC_H, + PMHACC_H_B0, + PMHACC_H_B1, + PMHACC_W, + PMHACC_W_H0, + PMHACC_W_H1, + PMHRACCSU_H, + PMHRACCSU_W, + PMHRACCU_H, + PMHRACCU_W, + PMHRACC_H, + PMHRACC_W, + PMINU_B, + PMINU_DB, + PMINU_DH, + PMINU_DW, + PMINU_H, + PMINU_W, + PMIN_B, + PMIN_DB, + PMIN_DH, + PMIN_DW, + PMIN_H, + PMIN_W, + PMQ2ADDA_H, + PMQ2ADDA_W, + PMQ2ADD_H, + PMQ2ADD_W, + PMQACC_W_H00, + PMQACC_W_H01, + PMQACC_W_H11, + PMQR2ADDA_H, + PMQR2ADDA_W, + PMQR2ADD_H, + PMQR2ADD_W, + PMQRACC_W_H00, + PMQRACC_W_H01, + PMQRACC_W_H11, + PMQRWACC, + PMQRWACC_H, + PMQWACC, + PMQWACC_H, + PMSEQ_B, + PMSEQ_DB, + PMSEQ_DH, + PMSEQ_DW, + PMSEQ_H, + PMSEQ_W, + PMSLTU_B, + PMSLTU_DB, + PMSLTU_DH, + PMSLTU_DW, + PMSLTU_H, + PMSLTU_W, + PMSLT_B, + PMSLT_DB, + PMSLT_DH, + PMSLT_DW, + PMSLT_H, + PMSLT_W, + PMULHRSU_H, + PMULHRSU_W, + PMULHRU_H, + PMULHRU_W, + PMULHR_H, + PMULHR_W, + PMULHSU_H, + PMULHSU_H_B0, + PMULHSU_H_B1, + PMULHSU_W, + PMULHSU_W_H0, + PMULHSU_W_H1, + PMULHU_H, + PMULHU_W, + PMULH_H, + PMULH_H_B0, + PMULH_H_B1, + PMULH_W, + PMULH_W_H0, + PMULH_W_H1, + PMULQR_H, + PMULQR_W, + PMULQ_H, + PMULQ_W, + PMULSU_H_B00, + PMULSU_H_B11, + PMULSU_W_H00, + PMULSU_W_H11, + PMULU_H_B00, + PMULU_H_B01, + PMULU_H_B11, + PMULU_W_H00, + PMULU_W_H01, + PMULU_W_H11, + PMUL_H_B00, + PMUL_H_B01, + PMUL_H_B11, + PMUL_W_H00, + PMUL_W_H01, + PMUL_W_H11, + PNCLIPIU_B, + PNCLIPIU_H, + PNCLIPI_B, + PNCLIPI_H, + PNCLIPRIU_B, + PNCLIPRIU_H, + PNCLIPRI_B, + PNCLIPRI_H, + PNCLIPRU_BS, + PNCLIPRU_HS, + PNCLIPR_BS, + PNCLIPR_HS, + PNCLIPU_BS, + PNCLIPU_HS, + PNCLIP_BS, + PNCLIP_HS, + PNSARI_B, + PNSARI_H, + PNSRAI_B, + PNSRAI_H, + PNSRAR_BS, + PNSRAR_HS, + PNSRA_BS, + PNSRA_HS, + PNSRLI_B, + PNSRLI_H, + PNSRL_BS, + PNSRL_HS, + PPAIREO_B, + PPAIREO_DB, + PPAIREO_DH, + PPAIREO_H, + PPAIREO_W, + PPAIRE_B, + PPAIRE_DB, + PPAIRE_DH, + PPAIRE_H, + PPAIROE_B, + PPAIROE_DB, + PPAIROE_DH, + PPAIROE_H, + PPAIROE_W, + PPAIRO_B, + PPAIRO_DB, + PPAIRO_DH, + PPAIRO_H, + PPAIRO_W, + PREDSUMU_BS, + PREDSUMU_DBS, + PREDSUMU_DHS, + PREDSUMU_HS, + PREDSUMU_WS, + PREDSUM_BS, + PREDSUM_DBS, + PREDSUM_DHS, + PREDSUM_HS, + PREDSUM_WS, + PREFETCH_I, + PREFETCH_R, + PREFETCH_W, + PSABS_B, + PSABS_DB, + PSABS_DH, + PSABS_H, + PSADDU_B, + PSADDU_DB, + PSADDU_DH, + PSADDU_DW, + PSADDU_H, + PSADDU_W, + PSADD_B, + PSADD_DB, + PSADD_DH, + PSADD_DW, + PSADD_H, + PSADD_W, + PSAS_DHX, + PSAS_HX, + PSAS_WX, + PSATI_DH, + PSATI_DW, + PSATI_H, + PSATI_W, + PSA_DHX, + PSA_HX, + PSA_WX, + PSEXT_DH_B, + PSEXT_DW_B, + PSEXT_DW_H, + PSEXT_H_B, + PSEXT_W_B, + PSEXT_W_H, + PSH1ADD_DH, + PSH1ADD_DW, + PSH1ADD_H, + PSH1ADD_W, + PSLLI_B, + PSLLI_DB, + PSLLI_DH, + PSLLI_DW, + PSLLI_H, + PSLLI_W, + PSLL_BS, + PSLL_DBS, + PSLL_DHS, + PSLL_DWS, + PSLL_HS, + PSLL_WS, + PSRAI_B, + PSRAI_DB, + PSRAI_DH, + PSRAI_DW, + PSRAI_H, + PSRAI_W, + PSRARI_DH, + PSRARI_DW, + PSRARI_H, + PSRARI_W, + PSRA_BS, + PSRA_DBS, + PSRA_DHS, + PSRA_DWS, + PSRA_HS, + PSRA_WS, + PSRLI_B, + PSRLI_DB, + PSRLI_DH, + PSRLI_DW, + PSRLI_H, + PSRLI_W, + PSRL_BS, + PSRL_DBS, + PSRL_DHS, + PSRL_DWS, + PSRL_HS, + PSRL_WS, + PSSA_DHX, + PSSA_HX, + PSSA_WX, + PSSH1SADD_DH, + PSSH1SADD_DW, + PSSH1SADD_H, + PSSH1SADD_W, + PSSHAR_DHS, + PSSHAR_DWS, + PSSHAR_HS, + PSSHAR_WS, + PSSHA_DHS, + PSSHA_DWS, + PSSHA_HS, + PSSHA_WS, + PSSLAI_DH, + PSSLAI_DW, + PSSLAI_H, + PSSLAI_W, + PSSUBU_B, + PSSUBU_DB, + PSSUBU_DH, + PSSUBU_DW, + PSSUBU_H, + PSSUBU_W, + PSSUB_B, + PSSUB_DB, + PSSUB_DH, + PSSUB_DW, + PSSUB_H, + PSSUB_W, + PSUB_B, + PSUB_DB, + PSUB_DH, + PSUB_DW, + PSUB_H, + PSUB_W, + PUSATI_DH, + PUSATI_DW, + PUSATI_H, + PUSATI_W, + PWADDAU_B, + PWADDAU_H, + PWADDA_B, + PWADDA_H, + PWADDU_B, + PWADDU_H, + PWADD_B, + PWADD_H, + PWMACCSU_H, + PWMACCU_H, + PWMACC_H, + PWMULSU_B, + PWMULSU_H, + PWMULU_B, + PWMULU_H, + PWMUL_B, + PWMUL_H, + PWSLAI_B, + PWSLAI_H, + PWSLA_BS, + PWSLA_HS, + PWSLLI_B, + PWSLLI_H, + PWSLL_BS, + PWSLL_HS, + PWSUBAU_B, + PWSUBAU_H, + PWSUBA_B, + PWSUBA_H, + PWSUBU_B, + PWSUBU_H, + PWSUB_B, + PWSUB_H, + QC_ADDSAT, + QC_ADDUSAT, + QC_BEQI, + QC_BGEI, + QC_BGEUI, + QC_BLTI, + QC_BLTUI, + QC_BNEI, + QC_BREV32, + QC_CLO, + QC_CLRINTI, + QC_CM_MVA01S, + QC_CM_MVSA01, + QC_CM_POP, + QC_CM_POPRET, + QC_CM_POPRETZ, + QC_CM_PUSH, + QC_CM_PUSHFP, + QC_COMPRESS2, + QC_COMPRESS3, + QC_CSRRWR, + QC_CSRRWRI, + QC_CTO, + QC_C_BEXTI, + QC_C_BSETI, + QC_C_CLRINT, + QC_C_DI, + QC_C_DIR, + QC_C_EI, + QC_C_EIR, + QC_C_EXTU, + QC_C_MIENTER, + QC_C_MIENTER_NEST, + QC_C_MILEAVERET, + QC_C_MNRET, + QC_C_MRET, + QC_C_MULIADD, + QC_C_MVEQZ, + QC_C_SETINT, + QC_C_SYNC, + QC_C_SYNCR, + QC_C_SYNCWF, + QC_C_SYNCWL, + QC_EXPAND2, + QC_EXPAND3, + QC_EXT, + QC_EXTD, + QC_EXTDPR, + QC_EXTDPRH, + QC_EXTDR, + QC_EXTDU, + QC_EXTDUPR, + QC_EXTDUPRH, + QC_EXTDUR, + QC_EXTU, + QC_E_ADDAI, + QC_E_ADDI, + QC_E_ANDAI, + QC_E_ANDI, + QC_E_BEQI, + QC_E_BGEI, + QC_E_BGEUI, + QC_E_BLTI, + QC_E_BLTUI, + QC_E_BNEI, + QC_E_J, + QC_E_JAL, + QC_E_LB, + QC_E_LBU, + QC_E_LH, + QC_E_LHU, + QC_E_LI, + QC_E_LW, + QC_E_ORAI, + QC_E_ORI, + QC_E_SB, + QC_E_SH, + QC_E_SW, + QC_E_XORAI, + QC_E_XORI, + QC_INSB, + QC_INSBH, + QC_INSBHR, + QC_INSBI, + QC_INSBPR, + QC_INSBPRH, + QC_INSBR, + QC_INSBRI, + QC_INW, + QC_LI, + QC_LIEQ, + QC_LIEQI, + QC_LIGE, + QC_LIGEI, + QC_LIGEU, + QC_LIGEUI, + QC_LILT, + QC_LILTI, + QC_LILTU, + QC_LILTUI, + QC_LINE, + QC_LINEI, + QC_LRB, + QC_LRBU, + QC_LRH, + QC_LRHU, + QC_LRW, + QC_LWM, + QC_LWMI, + QC_MULIADD, + QC_MVEQ, + QC_MVEQI, + QC_MVGE, + QC_MVGEI, + QC_MVGEU, + QC_MVGEUI, + QC_MVLT, + QC_MVLTI, + QC_MVLTU, + QC_MVLTUI, + QC_MVNE, + QC_MVNEI, + QC_NORM, + QC_NORMEU, + QC_NORMU, + QC_OUTW, + QC_PPUTCI, + QC_SELECTEQI, + QC_SELECTIEQ, + QC_SELECTIEQI, + QC_SELECTIIEQ, + QC_SELECTIINE, + QC_SELECTINE, + QC_SELECTINEI, + QC_SELECTNEI, + QC_SETINTI, + QC_SETWM, + QC_SETWMI, + QC_SHLADD, + QC_SHLSAT, + QC_SHLUSAT, + QC_SRB, + QC_SRH, + QC_SRW, + QC_SUBSAT, + QC_SUBUSAT, + QC_SWM, + QC_SWMI, + QC_SYNC, + QC_SYNCR, + QC_SYNCWF, + QC_SYNCWL, + QC_WRAP, + QC_WRAPI, + QK_C_LBU, + QK_C_LBUSP, + QK_C_LHU, + QK_C_LHUSP, + QK_C_SB, + QK_C_SBSP, + QK_C_SH, + QK_C_SHSP, + REM, + REMU, + REMUW, + REMW, + REV16, + REV8_RV32, + REV8_RV64, + REV_RV32, + REV_RV64, + RI_VEXTRACT, + RI_VINSERT, + RI_VUNZIP2A_VV, + RI_VUNZIP2B_VV, + RI_VZERO, + RI_VZIP2A_VV, + RI_VZIP2B_VV, + RI_VZIPEVEN_VV, + RI_VZIPODD_VV, + ROL, + ROLW, + ROR, + RORI, + RORIW, + RORW, + SADD, + SADDU, + SATI_RV32, + SATI_RV64, + SB, + SB_AQRL, + SB_RL, + SCTRCLR, + SC_D, + SC_D_AQ, + SC_D_AQRL, + SC_D_RL, + SC_W, + SC_W_AQ, + SC_W_AQRL, + SC_W_RL, + SD, + SD_AQRL, + SD_RL, + SD_RV32, + SEXT_B, + SEXT_H, + SFENCE_INVAL_IR, + SFENCE_VMA, + SFENCE_W_INVAL, + SF_CDISCARD_D_L1, + SF_CEASE, + SF_CFLUSH_D_L1, + SF_MM_E4M3_E4M3, + SF_MM_E4M3_E5M2, + SF_MM_E5M2_E4M3, + SF_MM_E5M2_E5M2, + SF_MM_F_F, + SF_MM_S_S, + SF_MM_S_U, + SF_MM_U_S, + SF_MM_U_U, + SF_VC_FV, + SF_VC_FVV, + SF_VC_FVW, + SF_VC_I, + SF_VC_IV, + SF_VC_IVV, + SF_VC_IVW, + SF_VC_VV, + SF_VC_VVV, + SF_VC_VVW, + SF_VC_V_FV, + SF_VC_V_FVV, + SF_VC_V_FVW, + SF_VC_V_I, + SF_VC_V_IV, + SF_VC_V_IVV, + SF_VC_V_IVW, + SF_VC_V_VV, + SF_VC_V_VVV, + SF_VC_V_VVW, + SF_VC_V_X, + SF_VC_V_XV, + SF_VC_V_XVV, + SF_VC_V_XVW, + SF_VC_X, + SF_VC_XV, + SF_VC_XVV, + SF_VC_XVW, + SF_VFEXPA_V, + SF_VFEXP_V, + SF_VFNRCLIP_XU_F_QF, + SF_VFNRCLIP_X_F_QF, + SF_VFWMACC_4x4x4, + SF_VLTE16, + SF_VLTE32, + SF_VLTE64, + SF_VLTE8, + SF_VQMACCSU_2x8x2, + SF_VQMACCSU_4x8x4, + SF_VQMACCUS_2x8x2, + SF_VQMACCUS_4x8x4, + SF_VQMACCU_2x8x2, + SF_VQMACCU_4x8x4, + SF_VQMACC_2x8x2, + SF_VQMACC_4x8x4, + SF_VSETTK, + SF_VSETTM, + SF_VSETTN, + SF_VSTE16, + SF_VSTE32, + SF_VSTE64, + SF_VSTE8, + SF_VTDISCARD, + SF_VTMV_T_V, + SF_VTMV_V_T, + SF_VTZERO_T, + SH, + SH1ADD, + SH1ADD_UW, + SH2ADD, + SH2ADD_UW, + SH3ADD, + SH3ADD_UW, + SHA, + SHA256SIG0, + SHA256SIG1, + SHA256SUM0, + SHA256SUM1, + SHA512SIG0, + SHA512SIG0H, + SHA512SIG0L, + SHA512SIG1, + SHA512SIG1H, + SHA512SIG1L, + SHA512SUM0, + SHA512SUM0R, + SHA512SUM1, + SHA512SUM1R, + SHAR, + SH_AQRL, + SH_INX, + SH_RL, + SINVAL_VMA, + SLL, + SLLI, + SLLIW, + SLLI_UW, + SLLW, + SLT, + SLTI, + SLTIU, + SLTU, + SLX, + SM3P0, + SM3P1, + SM4ED, + SM4KS, + SMT_VMADOT, + SMT_VMADOT1, + SMT_VMADOT1SU, + SMT_VMADOT1U, + SMT_VMADOT1US, + SMT_VMADOT2, + SMT_VMADOT2SU, + SMT_VMADOT2U, + SMT_VMADOT2US, + SMT_VMADOT3, + SMT_VMADOT3SU, + SMT_VMADOT3U, + SMT_VMADOT3US, + SMT_VMADOTSU, + SMT_VMADOTU, + SMT_VMADOTUS, + SRA, + SRAI, + SRAIW, + SRARI_RV32, + SRARI_RV64, + SRAW, + SRET, + SRL, + SRLI, + SRLIW, + SRLW, + SRX, + SSAMOSWAP_D, + SSAMOSWAP_D_AQ, + SSAMOSWAP_D_AQRL, + SSAMOSWAP_D_RL, + SSAMOSWAP_W, + SSAMOSWAP_W_AQ, + SSAMOSWAP_W_AQRL, + SSAMOSWAP_W_RL, + SSH1SADD, + SSHA, + SSHAR, + SSLAI, + SSPOPCHK, + SSPUSH, + SSRDP, + SSUB, + SSUBU, + SUB, + SUBD, + SUBW, + SW, + SW_AQRL, + SW_INX, + SW_RL, + TH_ADDSL, + TH_DCACHE_CALL, + TH_DCACHE_CIALL, + TH_DCACHE_CIPA, + TH_DCACHE_CISW, + TH_DCACHE_CIVA, + TH_DCACHE_CPA, + TH_DCACHE_CPAL1, + TH_DCACHE_CSW, + TH_DCACHE_CVA, + TH_DCACHE_CVAL1, + TH_DCACHE_IALL, + TH_DCACHE_IPA, + TH_DCACHE_ISW, + TH_DCACHE_IVA, + TH_EXT, + TH_EXTU, + TH_FF0, + TH_FF1, + TH_FLRD, + TH_FLRW, + TH_FLURD, + TH_FLURW, + TH_FSRD, + TH_FSRW, + TH_FSURD, + TH_FSURW, + TH_ICACHE_IALL, + TH_ICACHE_IALLS, + TH_ICACHE_IPA, + TH_ICACHE_IVA, + TH_L2CACHE_CALL, + TH_L2CACHE_CIALL, + TH_L2CACHE_IALL, + TH_LBIA, + TH_LBIB, + TH_LBUIA, + TH_LBUIB, + TH_LDD, + TH_LDIA, + TH_LDIB, + TH_LHIA, + TH_LHIB, + TH_LHUIA, + TH_LHUIB, + TH_LRB, + TH_LRBU, + TH_LRD, + TH_LRH, + TH_LRHU, + TH_LRW, + TH_LRWU, + TH_LURB, + TH_LURBU, + TH_LURD, + TH_LURH, + TH_LURHU, + TH_LURW, + TH_LURWU, + TH_LWD, + TH_LWIA, + TH_LWIB, + TH_LWUD, + TH_LWUIA, + TH_LWUIB, + TH_MULA, + TH_MULAH, + TH_MULAW, + TH_MULS, + TH_MULSH, + TH_MULSW, + TH_MVEQZ, + TH_MVNEZ, + TH_REV, + TH_REVW, + TH_SBIA, + TH_SBIB, + TH_SDD, + TH_SDIA, + TH_SDIB, + TH_SFENCE_VMAS, + TH_SHIA, + TH_SHIB, + TH_SRB, + TH_SRD, + TH_SRH, + TH_SRRI, + TH_SRRIW, + TH_SRW, + TH_SURB, + TH_SURD, + TH_SURH, + TH_SURW, + TH_SWD, + TH_SWIA, + TH_SWIB, + TH_SYNC, + TH_SYNC_I, + TH_SYNC_IS, + TH_SYNC_S, + TH_TST, + TH_TSTNBZ, + TH_VMAQASU_VV, + TH_VMAQASU_VX, + TH_VMAQAUS_VX, + TH_VMAQAU_VV, + TH_VMAQAU_VX, + TH_VMAQA_VV, + TH_VMAQA_VX, + UNIMP, + UNZIP16HP, + UNZIP16P, + UNZIP8HP, + UNZIP8P, + UNZIP_RV32, + USATI_RV32, + USATI_RV64, + VAADDU_VV, + VAADDU_VX, + VAADD_VV, + VAADD_VX, + VADC_VIM, + VADC_VVM, + VADC_VXM, + VADD_VI, + VADD_VV, + VADD_VX, + VAESDF_VS, + VAESDF_VV, + VAESDM_VS, + VAESDM_VV, + VAESEF_VS, + VAESEF_VV, + VAESEM_VS, + VAESEM_VV, + VAESKF1_VI, + VAESKF2_VI, + VAESZ_VS, + VANDN_VV, + VANDN_VX, + VAND_VI, + VAND_VV, + VAND_VX, + VASUBU_VV, + VASUBU_VX, + VASUB_VV, + VASUB_VX, + VBREV8_V, + VBREV_V, + VCLMULH_VV, + VCLMULH_VX, + VCLMUL_VV, + VCLMUL_VX, + VCLZ_V, + VCOMPRESS_VM, + VCPOP_M, + VCPOP_V, + VCTZ_V, + VDIVU_VV, + VDIVU_VX, + VDIV_VV, + VDIV_VX, + VFADD_VF, + VFADD_VV, + VFCLASS_V, + VFCVT_F_XU_V, + VFCVT_F_X_V, + VFCVT_RTZ_XU_F_V, + VFCVT_RTZ_X_F_V, + VFCVT_XU_F_V, + VFCVT_X_F_V, + VFDIV_VF, + VFDIV_VV, + VFIRST_M, + VFMACC_VF, + VFMACC_VV, + VFMADD_VF, + VFMADD_VV, + VFMAX_VF, + VFMAX_VV, + VFMERGE_VFM, + VFMIN_VF, + VFMIN_VV, + VFMSAC_VF, + VFMSAC_VV, + VFMSUB_VF, + VFMSUB_VV, + VFMUL_VF, + VFMUL_VV, + VFMV_F_S, + VFMV_S_F, + VFMV_V_F, + VFNCVTBF16_F_F_W, + VFNCVTBF16_SAT_F_F_W, + VFNCVT_F_F_Q, + VFNCVT_F_F_W, + VFNCVT_F_XU_W, + VFNCVT_F_X_W, + VFNCVT_ROD_F_F_W, + VFNCVT_RTZ_XU_F_W, + VFNCVT_RTZ_X_F_W, + VFNCVT_SAT_F_F_Q, + VFNCVT_XU_F_W, + VFNCVT_X_F_W, + VFNMACC_VF, + VFNMACC_VV, + VFNMADD_VF, + VFNMADD_VV, + VFNMSAC_VF, + VFNMSAC_VV, + VFNMSUB_VF, + VFNMSUB_VV, + VFRDIV_VF, + VFREC7_V, + VFREDMAX_VS, + VFREDMIN_VS, + VFREDOSUM_VS, + VFREDUSUM_VS, + VFRSQRT7_V, + VFRSUB_VF, + VFSGNJN_VF, + VFSGNJN_VV, + VFSGNJX_VF, + VFSGNJX_VV, + VFSGNJ_VF, + VFSGNJ_VV, + VFSLIDE1DOWN_VF, + VFSLIDE1UP_VF, + VFSQRT_V, + VFSUB_VF, + VFSUB_VV, + VFWADD_VF, + VFWADD_VV, + VFWADD_WF, + VFWADD_WV, + VFWCVTBF16_F_F_V, + VFWCVT_F_F_V, + VFWCVT_F_XU_V, + VFWCVT_F_X_V, + VFWCVT_RTZ_XU_F_V, + VFWCVT_RTZ_X_F_V, + VFWCVT_XU_F_V, + VFWCVT_X_F_V, + VFWMACCBF16_VF, + VFWMACCBF16_VV, + VFWMACC_VF, + VFWMACC_VV, + VFWMSAC_VF, + VFWMSAC_VV, + VFWMUL_VF, + VFWMUL_VV, + VFWNMACC_VF, + VFWNMACC_VV, + VFWNMSAC_VF, + VFWNMSAC_VV, + VFWREDOSUM_VS, + VFWREDUSUM_VS, + VFWSUB_VF, + VFWSUB_VV, + VFWSUB_WF, + VFWSUB_WV, + VGHSH_VS, + VGHSH_VV, + VGMUL_VS, + VGMUL_VV, + VID_V, + VIOTA_M, + VL1RE16_V, + VL1RE32_V, + VL1RE64_V, + VL1RE8_V, + VL2RE16_V, + VL2RE32_V, + VL2RE64_V, + VL2RE8_V, + VL4RE16_V, + VL4RE32_V, + VL4RE64_V, + VL4RE8_V, + VL8RE16_V, + VL8RE32_V, + VL8RE64_V, + VL8RE8_V, + VLE16FF_V, + VLE16_V, + VLE32FF_V, + VLE32_V, + VLE64FF_V, + VLE64_V, + VLE8FF_V, + VLE8_V, + VLM_V, + VLOXEI16_V, + VLOXEI32_V, + VLOXEI64_V, + VLOXEI8_V, + VLOXSEG2EI16_V, + VLOXSEG2EI32_V, + VLOXSEG2EI64_V, + VLOXSEG2EI8_V, + VLOXSEG3EI16_V, + VLOXSEG3EI32_V, + VLOXSEG3EI64_V, + VLOXSEG3EI8_V, + VLOXSEG4EI16_V, + VLOXSEG4EI32_V, + VLOXSEG4EI64_V, + VLOXSEG4EI8_V, + VLOXSEG5EI16_V, + VLOXSEG5EI32_V, + VLOXSEG5EI64_V, + VLOXSEG5EI8_V, + VLOXSEG6EI16_V, + VLOXSEG6EI32_V, + VLOXSEG6EI64_V, + VLOXSEG6EI8_V, + VLOXSEG7EI16_V, + VLOXSEG7EI32_V, + VLOXSEG7EI64_V, + VLOXSEG7EI8_V, + VLOXSEG8EI16_V, + VLOXSEG8EI32_V, + VLOXSEG8EI64_V, + VLOXSEG8EI8_V, + VLSE16_V, + VLSE32_V, + VLSE64_V, + VLSE8_V, + VLSEG2E16FF_V, + VLSEG2E16_V, + VLSEG2E32FF_V, + VLSEG2E32_V, + VLSEG2E64FF_V, + VLSEG2E64_V, + VLSEG2E8FF_V, + VLSEG2E8_V, + VLSEG3E16FF_V, + VLSEG3E16_V, + VLSEG3E32FF_V, + VLSEG3E32_V, + VLSEG3E64FF_V, + VLSEG3E64_V, + VLSEG3E8FF_V, + VLSEG3E8_V, + VLSEG4E16FF_V, + VLSEG4E16_V, + VLSEG4E32FF_V, + VLSEG4E32_V, + VLSEG4E64FF_V, + VLSEG4E64_V, + VLSEG4E8FF_V, + VLSEG4E8_V, + VLSEG5E16FF_V, + VLSEG5E16_V, + VLSEG5E32FF_V, + VLSEG5E32_V, + VLSEG5E64FF_V, + VLSEG5E64_V, + VLSEG5E8FF_V, + VLSEG5E8_V, + VLSEG6E16FF_V, + VLSEG6E16_V, + VLSEG6E32FF_V, + VLSEG6E32_V, + VLSEG6E64FF_V, + VLSEG6E64_V, + VLSEG6E8FF_V, + VLSEG6E8_V, + VLSEG7E16FF_V, + VLSEG7E16_V, + VLSEG7E32FF_V, + VLSEG7E32_V, + VLSEG7E64FF_V, + VLSEG7E64_V, + VLSEG7E8FF_V, + VLSEG7E8_V, + VLSEG8E16FF_V, + VLSEG8E16_V, + VLSEG8E32FF_V, + VLSEG8E32_V, + VLSEG8E64FF_V, + VLSEG8E64_V, + VLSEG8E8FF_V, + VLSEG8E8_V, + VLSSEG2E16_V, + VLSSEG2E32_V, + VLSSEG2E64_V, + VLSSEG2E8_V, + VLSSEG3E16_V, + VLSSEG3E32_V, + VLSSEG3E64_V, + VLSSEG3E8_V, + VLSSEG4E16_V, + VLSSEG4E32_V, + VLSSEG4E64_V, + VLSSEG4E8_V, + VLSSEG5E16_V, + VLSSEG5E32_V, + VLSSEG5E64_V, + VLSSEG5E8_V, + VLSSEG6E16_V, + VLSSEG6E32_V, + VLSSEG6E64_V, + VLSSEG6E8_V, + VLSSEG7E16_V, + VLSSEG7E32_V, + VLSSEG7E64_V, + VLSSEG7E8_V, + VLSSEG8E16_V, + VLSSEG8E32_V, + VLSSEG8E64_V, + VLSSEG8E8_V, + VLUXEI16_V, + VLUXEI32_V, + VLUXEI64_V, + VLUXEI8_V, + VLUXSEG2EI16_V, + VLUXSEG2EI32_V, + VLUXSEG2EI64_V, + VLUXSEG2EI8_V, + VLUXSEG3EI16_V, + VLUXSEG3EI32_V, + VLUXSEG3EI64_V, + VLUXSEG3EI8_V, + VLUXSEG4EI16_V, + VLUXSEG4EI32_V, + VLUXSEG4EI64_V, + VLUXSEG4EI8_V, + VLUXSEG5EI16_V, + VLUXSEG5EI32_V, + VLUXSEG5EI64_V, + VLUXSEG5EI8_V, + VLUXSEG6EI16_V, + VLUXSEG6EI32_V, + VLUXSEG6EI64_V, + VLUXSEG6EI8_V, + VLUXSEG7EI16_V, + VLUXSEG7EI32_V, + VLUXSEG7EI64_V, + VLUXSEG7EI8_V, + VLUXSEG8EI16_V, + VLUXSEG8EI32_V, + VLUXSEG8EI64_V, + VLUXSEG8EI8_V, + VMACC_VV, + VMACC_VX, + VMADC_VI, + VMADC_VIM, + VMADC_VV, + VMADC_VVM, + VMADC_VX, + VMADC_VXM, + VMADD_VV, + VMADD_VX, + VMANDN_MM, + VMAND_MM, + VMAXU_VV, + VMAXU_VX, + VMAX_VV, + VMAX_VX, + VMERGE_VIM, + VMERGE_VVM, + VMERGE_VXM, + VMFEQ_VF, + VMFEQ_VV, + VMFGE_VF, + VMFGT_VF, + VMFLE_VF, + VMFLE_VV, + VMFLT_VF, + VMFLT_VV, + VMFNE_VF, + VMFNE_VV, + VMINU_VV, + VMINU_VX, + VMIN_VV, + VMIN_VX, + VMNAND_MM, + VMNOR_MM, + VMORN_MM, + VMOR_MM, + VMSBC_VV, + VMSBC_VVM, + VMSBC_VX, + VMSBC_VXM, + VMSBF_M, + VMSEQ_VI, + VMSEQ_VV, + VMSEQ_VX, + VMSGTU_VI, + VMSGTU_VX, + VMSGT_VI, + VMSGT_VX, + VMSIF_M, + VMSLEU_VI, + VMSLEU_VV, + VMSLEU_VX, + VMSLE_VI, + VMSLE_VV, + VMSLE_VX, + VMSLTU_VV, + VMSLTU_VX, + VMSLT_VV, + VMSLT_VX, + VMSNE_VI, + VMSNE_VV, + VMSNE_VX, + VMSOF_M, + VMULHSU_VV, + VMULHSU_VX, + VMULHU_VV, + VMULHU_VX, + VMULH_VV, + VMULH_VX, + VMUL_VV, + VMUL_VX, + VMV1R_V, + VMV2R_V, + VMV4R_V, + VMV8R_V, + VMV_S_X, + VMV_V_I, + VMV_V_V, + VMV_V_X, + VMV_X_S, + VMXNOR_MM, + VMXOR_MM, + VNCLIPU_WI, + VNCLIPU_WV, + VNCLIPU_WX, + VNCLIP_WI, + VNCLIP_WV, + VNCLIP_WX, + VNMSAC_VV, + VNMSAC_VX, + VNMSUB_VV, + VNMSUB_VX, + VNSRA_WI, + VNSRA_WV, + VNSRA_WX, + VNSRL_WI, + VNSRL_WV, + VNSRL_WX, + VOR_VI, + VOR_VV, + VOR_VX, + VQDOTSU_VV, + VQDOTSU_VX, + VQDOTUS_VX, + VQDOTU_VV, + VQDOTU_VX, + VQDOT_VV, + VQDOT_VX, + VREDAND_VS, + VREDMAXU_VS, + VREDMAX_VS, + VREDMINU_VS, + VREDMIN_VS, + VREDOR_VS, + VREDSUM_VS, + VREDXOR_VS, + VREMU_VV, + VREMU_VX, + VREM_VV, + VREM_VX, + VREV8_V, + VRGATHEREI16_VV, + VRGATHER_VI, + VRGATHER_VV, + VRGATHER_VX, + VROL_VV, + VROL_VX, + VROR_VI, + VROR_VV, + VROR_VX, + VRSUB_VI, + VRSUB_VX, + VS1R_V, + VS2R_V, + VS4R_V, + VS8R_V, + VSADDU_VI, + VSADDU_VV, + VSADDU_VX, + VSADD_VI, + VSADD_VV, + VSADD_VX, + VSBC_VVM, + VSBC_VXM, + VSE16_V, + VSE32_V, + VSE64_V, + VSE8_V, + VSETIVLI, + VSETVL, + VSETVLI, + VSEXT_VF2, + VSEXT_VF4, + VSEXT_VF8, + VSHA2CH_VV, + VSHA2CL_VV, + VSHA2MS_VV, + VSLIDE1DOWN_VX, + VSLIDE1UP_VX, + VSLIDEDOWN_VI, + VSLIDEDOWN_VX, + VSLIDEUP_VI, + VSLIDEUP_VX, + VSLL_VI, + VSLL_VV, + VSLL_VX, + VSM3C_VI, + VSM3ME_VV, + VSM4K_VI, + VSM4R_VS, + VSM4R_VV, + VSMUL_VV, + VSMUL_VX, + VSM_V, + VSOXEI16_V, + VSOXEI32_V, + VSOXEI64_V, + VSOXEI8_V, + VSOXSEG2EI16_V, + VSOXSEG2EI32_V, + VSOXSEG2EI64_V, + VSOXSEG2EI8_V, + VSOXSEG3EI16_V, + VSOXSEG3EI32_V, + VSOXSEG3EI64_V, + VSOXSEG3EI8_V, + VSOXSEG4EI16_V, + VSOXSEG4EI32_V, + VSOXSEG4EI64_V, + VSOXSEG4EI8_V, + VSOXSEG5EI16_V, + VSOXSEG5EI32_V, + VSOXSEG5EI64_V, + VSOXSEG5EI8_V, + VSOXSEG6EI16_V, + VSOXSEG6EI32_V, + VSOXSEG6EI64_V, + VSOXSEG6EI8_V, + VSOXSEG7EI16_V, + VSOXSEG7EI32_V, + VSOXSEG7EI64_V, + VSOXSEG7EI8_V, + VSOXSEG8EI16_V, + VSOXSEG8EI32_V, + VSOXSEG8EI64_V, + VSOXSEG8EI8_V, + VSRA_VI, + VSRA_VV, + VSRA_VX, + VSRL_VI, + VSRL_VV, + VSRL_VX, + VSSE16_V, + VSSE32_V, + VSSE64_V, + VSSE8_V, + VSSEG2E16_V, + VSSEG2E32_V, + VSSEG2E64_V, + VSSEG2E8_V, + VSSEG3E16_V, + VSSEG3E32_V, + VSSEG3E64_V, + VSSEG3E8_V, + VSSEG4E16_V, + VSSEG4E32_V, + VSSEG4E64_V, + VSSEG4E8_V, + VSSEG5E16_V, + VSSEG5E32_V, + VSSEG5E64_V, + VSSEG5E8_V, + VSSEG6E16_V, + VSSEG6E32_V, + VSSEG6E64_V, + VSSEG6E8_V, + VSSEG7E16_V, + VSSEG7E32_V, + VSSEG7E64_V, + VSSEG7E8_V, + VSSEG8E16_V, + VSSEG8E32_V, + VSSEG8E64_V, + VSSEG8E8_V, + VSSRA_VI, + VSSRA_VV, + VSSRA_VX, + VSSRL_VI, + VSSRL_VV, + VSSRL_VX, + VSSSEG2E16_V, + VSSSEG2E32_V, + VSSSEG2E64_V, + VSSSEG2E8_V, + VSSSEG3E16_V, + VSSSEG3E32_V, + VSSSEG3E64_V, + VSSSEG3E8_V, + VSSSEG4E16_V, + VSSSEG4E32_V, + VSSSEG4E64_V, + VSSSEG4E8_V, + VSSSEG5E16_V, + VSSSEG5E32_V, + VSSSEG5E64_V, + VSSSEG5E8_V, + VSSSEG6E16_V, + VSSSEG6E32_V, + VSSSEG6E64_V, + VSSSEG6E8_V, + VSSSEG7E16_V, + VSSSEG7E32_V, + VSSSEG7E64_V, + VSSSEG7E8_V, + VSSSEG8E16_V, + VSSSEG8E32_V, + VSSSEG8E64_V, + VSSSEG8E8_V, + VSSUBU_VV, + VSSUBU_VX, + VSSUB_VV, + VSSUB_VX, + VSUB_VV, + VSUB_VX, + VSUXEI16_V, + VSUXEI32_V, + VSUXEI64_V, + VSUXEI8_V, + VSUXSEG2EI16_V, + VSUXSEG2EI32_V, + VSUXSEG2EI64_V, + VSUXSEG2EI8_V, + VSUXSEG3EI16_V, + VSUXSEG3EI32_V, + VSUXSEG3EI64_V, + VSUXSEG3EI8_V, + VSUXSEG4EI16_V, + VSUXSEG4EI32_V, + VSUXSEG4EI64_V, + VSUXSEG4EI8_V, + VSUXSEG5EI16_V, + VSUXSEG5EI32_V, + VSUXSEG5EI64_V, + VSUXSEG5EI8_V, + VSUXSEG6EI16_V, + VSUXSEG6EI32_V, + VSUXSEG6EI64_V, + VSUXSEG6EI8_V, + VSUXSEG7EI16_V, + VSUXSEG7EI32_V, + VSUXSEG7EI64_V, + VSUXSEG7EI8_V, + VSUXSEG8EI16_V, + VSUXSEG8EI32_V, + VSUXSEG8EI64_V, + VSUXSEG8EI8_V, + VT_MASKC, + VT_MASKCN, + VWADDU_VV, + VWADDU_VX, + VWADDU_WV, + VWADDU_WX, + VWADD_VV, + VWADD_VX, + VWADD_WV, + VWADD_WX, + VWMACCSU_VV, + VWMACCSU_VX, + VWMACCUS_VX, + VWMACCU_VV, + VWMACCU_VX, + VWMACC_VV, + VWMACC_VX, + VWMULSU_VV, + VWMULSU_VX, + VWMULU_VV, + VWMULU_VX, + VWMUL_VV, + VWMUL_VX, + VWREDSUMU_VS, + VWREDSUM_VS, + VWSLL_VI, + VWSLL_VV, + VWSLL_VX, + VWSUBU_VV, + VWSUBU_VX, + VWSUBU_WV, + VWSUBU_WX, + VWSUB_VV, + VWSUB_VX, + VWSUB_WV, + VWSUB_WX, + VXOR_VI, + VXOR_VV, + VXOR_VX, + VZEXT_VF2, + VZEXT_VF4, + VZEXT_VF8, + WADD, + WADDA, + WADDAU, + WADDU, + WFI, + WMACC, + WMACCSU, + WMACCU, + WMUL, + WMULSU, + WMULU, + WRS_NTO, + WRS_STO, + WSLA, + WSLAI, + WSLL, + WSLLI, + WSUB, + WSUBA, + WSUBAU, + WSUBU, + WZIP16P, + WZIP8P, + XNOR, + XOR, + XORI, + XPERM4, + XPERM8, + ZEXT_H_RV32, + ZEXT_H_RV64, + ZIP16HP, + ZIP16P, + ZIP8HP, + ZIP8P, + ZIP_RV32, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ADJCALLSTACKDOWN, + 323 => Opcode::ADJCALLSTACKUP, + 324 => Opcode::BuildPairF64Pseudo, + 325 => Opcode::ClearFCSR, + 326 => Opcode::ClearFCSRImm, + 327 => Opcode::G_CLZW, + 328 => Opcode::G_CTZW, + 329 => Opcode::G_DIVUW, + 330 => Opcode::G_DIVW, + 331 => Opcode::G_FCLASS, + 332 => Opcode::G_FCVT_WU_RV64, + 333 => Opcode::G_FCVT_W_RV64, + 334 => Opcode::G_READ_VLENB, + 335 => Opcode::G_REMUW, + 336 => Opcode::G_ROLW, + 337 => Opcode::G_RORW, + 338 => Opcode::G_SLLW, + 339 => Opcode::G_SPLAT_VECTOR_SPLIT_I64_VL, + 340 => Opcode::G_SRAW, + 341 => Opcode::G_SRLW, + 342 => Opcode::G_VMCLR_VL, + 343 => Opcode::G_VMSET_VL, + 344 => Opcode::G_VMV_V_V_VL, + 345 => Opcode::G_VSLIDEDOWN_VL, + 346 => Opcode::G_VSLIDEUP_VL, + 347 => Opcode::HWASAN_CHECK_MEMACCESS_SHORTGRANULES, + 348 => Opcode::KCFI_CHECK, + 349 => Opcode::PROBED_STACKALLOC, + 350 => Opcode::PROBED_STACKALLOC_DYN, + 351 => Opcode::PROBED_STACKALLOC_RVV, + 352 => Opcode::PseudoAddTPRel, + 353 => Opcode::PseudoAtomicLoadAdd32, + 354 => Opcode::PseudoAtomicLoadAdd64, + 355 => Opcode::PseudoAtomicLoadAnd32, + 356 => Opcode::PseudoAtomicLoadAnd64, + 357 => Opcode::PseudoAtomicLoadMax32, + 358 => Opcode::PseudoAtomicLoadMax64, + 359 => Opcode::PseudoAtomicLoadMin32, + 360 => Opcode::PseudoAtomicLoadMin64, + 361 => Opcode::PseudoAtomicLoadNand32, + 362 => Opcode::PseudoAtomicLoadNand64, + 363 => Opcode::PseudoAtomicLoadOr32, + 364 => Opcode::PseudoAtomicLoadOr64, + 365 => Opcode::PseudoAtomicLoadSub32, + 366 => Opcode::PseudoAtomicLoadSub64, + 367 => Opcode::PseudoAtomicLoadUMax32, + 368 => Opcode::PseudoAtomicLoadUMax64, + 369 => Opcode::PseudoAtomicLoadUMin32, + 370 => Opcode::PseudoAtomicLoadUMin64, + 371 => Opcode::PseudoAtomicLoadXor32, + 372 => Opcode::PseudoAtomicLoadXor64, + 373 => Opcode::PseudoAtomicSwap32, + 374 => Opcode::PseudoAtomicSwap64, + 375 => Opcode::PseudoBR, + 376 => Opcode::PseudoBRIND, + 377 => Opcode::PseudoBRINDNonX7, + 378 => Opcode::PseudoBRINDX7, + 379 => Opcode::PseudoCALL, + 380 => Opcode::PseudoCALLIndirect, + 381 => Opcode::PseudoCALLIndirectNonX7, + 382 => Opcode::PseudoCALLIndirectX7, + 383 => Opcode::PseudoCALLReg, + 384 => Opcode::PseudoCCADD, + 385 => Opcode::PseudoCCADDI, + 386 => Opcode::PseudoCCADDIW, + 387 => Opcode::PseudoCCADDW, + 388 => Opcode::PseudoCCAND, + 389 => Opcode::PseudoCCANDI, + 390 => Opcode::PseudoCCANDN, + 391 => Opcode::PseudoCCLB, + 392 => Opcode::PseudoCCLBU, + 393 => Opcode::PseudoCCLD, + 394 => Opcode::PseudoCCLH, + 395 => Opcode::PseudoCCLHU, + 396 => Opcode::PseudoCCLUI, + 397 => Opcode::PseudoCCLW, + 398 => Opcode::PseudoCCLWU, + 399 => Opcode::PseudoCCMAX, + 400 => Opcode::PseudoCCMAXU, + 401 => Opcode::PseudoCCMIN, + 402 => Opcode::PseudoCCMINU, + 403 => Opcode::PseudoCCMOVGPR, + 404 => Opcode::PseudoCCMOVGPRNoX0, + 405 => Opcode::PseudoCCMUL, + 406 => Opcode::PseudoCCNDS_BFOS, + 407 => Opcode::PseudoCCNDS_BFOZ, + 408 => Opcode::PseudoCCOR, + 409 => Opcode::PseudoCCORI, + 410 => Opcode::PseudoCCORN, + 411 => Opcode::PseudoCCQC_E_LB, + 412 => Opcode::PseudoCCQC_E_LBU, + 413 => Opcode::PseudoCCQC_E_LH, + 414 => Opcode::PseudoCCQC_E_LHU, + 415 => Opcode::PseudoCCQC_E_LI, + 416 => Opcode::PseudoCCQC_E_LW, + 417 => Opcode::PseudoCCQC_LI, + 418 => Opcode::PseudoCCSLL, + 419 => Opcode::PseudoCCSLLI, + 420 => Opcode::PseudoCCSLLIW, + 421 => Opcode::PseudoCCSLLW, + 422 => Opcode::PseudoCCSRA, + 423 => Opcode::PseudoCCSRAI, + 424 => Opcode::PseudoCCSRAIW, + 425 => Opcode::PseudoCCSRAW, + 426 => Opcode::PseudoCCSRL, + 427 => Opcode::PseudoCCSRLI, + 428 => Opcode::PseudoCCSRLIW, + 429 => Opcode::PseudoCCSRLW, + 430 => Opcode::PseudoCCSUB, + 431 => Opcode::PseudoCCSUBW, + 432 => Opcode::PseudoCCXNOR, + 433 => Opcode::PseudoCCXOR, + 434 => Opcode::PseudoCCXORI, + 435 => Opcode::PseudoCV_ELW, + 436 => Opcode::PseudoC_ADDI_NOP, + 437 => Opcode::PseudoCmpXchg32, + 438 => Opcode::PseudoCmpXchg64, + 439 => Opcode::PseudoFLD, + 440 => Opcode::PseudoFLH, + 441 => Opcode::PseudoFLQ, + 442 => Opcode::PseudoFLW, + 443 => Opcode::PseudoFROUND_D, + 444 => Opcode::PseudoFROUND_D_IN32X, + 445 => Opcode::PseudoFROUND_D_INX, + 446 => Opcode::PseudoFROUND_H, + 447 => Opcode::PseudoFROUND_H_INX, + 448 => Opcode::PseudoFROUND_S, + 449 => Opcode::PseudoFROUND_S_INX, + 450 => Opcode::PseudoFSD, + 451 => Opcode::PseudoFSH, + 452 => Opcode::PseudoFSQ, + 453 => Opcode::PseudoFSW, + 454 => Opcode::PseudoJump, + 455 => Opcode::PseudoLA, + 456 => Opcode::PseudoLAImm, + 457 => Opcode::PseudoLA_TLSDESC, + 458 => Opcode::PseudoLA_TLS_GD, + 459 => Opcode::PseudoLA_TLS_IE, + 460 => Opcode::PseudoLB, + 461 => Opcode::PseudoLBU, + 462 => Opcode::PseudoLD, + 463 => Opcode::PseudoLD_RV32, + 464 => Opcode::PseudoLD_RV32_OPT, + 465 => Opcode::PseudoLGA, + 466 => Opcode::PseudoLH, + 467 => Opcode::PseudoLHU, + 468 => Opcode::PseudoLI, + 469 => Opcode::PseudoLLA, + 470 => Opcode::PseudoLLAImm, + 471 => Opcode::PseudoLW, + 472 => Opcode::PseudoLWU, + 473 => Opcode::PseudoLongBEQ, + 474 => Opcode::PseudoLongBEQI, + 475 => Opcode::PseudoLongBGE, + 476 => Opcode::PseudoLongBGEU, + 477 => Opcode::PseudoLongBLT, + 478 => Opcode::PseudoLongBLTU, + 479 => Opcode::PseudoLongBNE, + 480 => Opcode::PseudoLongBNEI, + 481 => Opcode::PseudoLongQC_BEQI, + 482 => Opcode::PseudoLongQC_BGEI, + 483 => Opcode::PseudoLongQC_BGEUI, + 484 => Opcode::PseudoLongQC_BLTI, + 485 => Opcode::PseudoLongQC_BLTUI, + 486 => Opcode::PseudoLongQC_BNEI, + 487 => Opcode::PseudoLongQC_E_BEQI, + 488 => Opcode::PseudoLongQC_E_BGEI, + 489 => Opcode::PseudoLongQC_E_BGEUI, + 490 => Opcode::PseudoLongQC_E_BLTI, + 491 => Opcode::PseudoLongQC_E_BLTUI, + 492 => Opcode::PseudoLongQC_E_BNEI, + 493 => Opcode::PseudoMOP_C_SSPUSH, + 494 => Opcode::PseudoMOP_SSPOPCHK, + 495 => Opcode::PseudoMOP_SSPUSH, + 496 => Opcode::PseudoMV_FPR16INX, + 497 => Opcode::PseudoMV_FPR32INX, + 498 => Opcode::PseudoMaskedAtomicLoadAdd32, + 499 => Opcode::PseudoMaskedAtomicLoadMax32, + 500 => Opcode::PseudoMaskedAtomicLoadMin32, + 501 => Opcode::PseudoMaskedAtomicLoadNand32, + 502 => Opcode::PseudoMaskedAtomicLoadSub32, + 503 => Opcode::PseudoMaskedAtomicLoadUMax32, + 504 => Opcode::PseudoMaskedAtomicLoadUMin32, + 505 => Opcode::PseudoMaskedAtomicSwap32, + 506 => Opcode::PseudoMaskedCmpXchg32, + 507 => Opcode::PseudoMovAddr, + 508 => Opcode::PseudoMovImm, + 509 => Opcode::PseudoNDS_VD4DOTSU_VV_M1, + 510 => Opcode::PseudoNDS_VD4DOTSU_VV_M1_MASK, + 511 => Opcode::PseudoNDS_VD4DOTSU_VV_M2, + 512 => Opcode::PseudoNDS_VD4DOTSU_VV_M2_MASK, + 513 => Opcode::PseudoNDS_VD4DOTSU_VV_M4, + 514 => Opcode::PseudoNDS_VD4DOTSU_VV_M4_MASK, + 515 => Opcode::PseudoNDS_VD4DOTSU_VV_M8, + 516 => Opcode::PseudoNDS_VD4DOTSU_VV_M8_MASK, + 517 => Opcode::PseudoNDS_VD4DOTSU_VV_MF2, + 518 => Opcode::PseudoNDS_VD4DOTSU_VV_MF2_MASK, + 519 => Opcode::PseudoNDS_VD4DOTS_VV_M1, + 520 => Opcode::PseudoNDS_VD4DOTS_VV_M1_MASK, + 521 => Opcode::PseudoNDS_VD4DOTS_VV_M2, + 522 => Opcode::PseudoNDS_VD4DOTS_VV_M2_MASK, + 523 => Opcode::PseudoNDS_VD4DOTS_VV_M4, + 524 => Opcode::PseudoNDS_VD4DOTS_VV_M4_MASK, + 525 => Opcode::PseudoNDS_VD4DOTS_VV_M8, + 526 => Opcode::PseudoNDS_VD4DOTS_VV_M8_MASK, + 527 => Opcode::PseudoNDS_VD4DOTS_VV_MF2, + 528 => Opcode::PseudoNDS_VD4DOTS_VV_MF2_MASK, + 529 => Opcode::PseudoNDS_VD4DOTU_VV_M1, + 530 => Opcode::PseudoNDS_VD4DOTU_VV_M1_MASK, + 531 => Opcode::PseudoNDS_VD4DOTU_VV_M2, + 532 => Opcode::PseudoNDS_VD4DOTU_VV_M2_MASK, + 533 => Opcode::PseudoNDS_VD4DOTU_VV_M4, + 534 => Opcode::PseudoNDS_VD4DOTU_VV_M4_MASK, + 535 => Opcode::PseudoNDS_VD4DOTU_VV_M8, + 536 => Opcode::PseudoNDS_VD4DOTU_VV_M8_MASK, + 537 => Opcode::PseudoNDS_VD4DOTU_VV_MF2, + 538 => Opcode::PseudoNDS_VD4DOTU_VV_MF2_MASK, + 539 => Opcode::PseudoNDS_VFNCVT_BF16_S_M1, + 540 => Opcode::PseudoNDS_VFNCVT_BF16_S_M2, + 541 => Opcode::PseudoNDS_VFNCVT_BF16_S_M4, + 542 => Opcode::PseudoNDS_VFNCVT_BF16_S_MF2, + 543 => Opcode::PseudoNDS_VFNCVT_BF16_S_MF4, + 544 => Opcode::PseudoNDS_VFPMADB_VFPR16_M1, + 545 => Opcode::PseudoNDS_VFPMADB_VFPR16_M1_MASK, + 546 => Opcode::PseudoNDS_VFPMADB_VFPR16_M2, + 547 => Opcode::PseudoNDS_VFPMADB_VFPR16_M2_MASK, + 548 => Opcode::PseudoNDS_VFPMADB_VFPR16_M4, + 549 => Opcode::PseudoNDS_VFPMADB_VFPR16_M4_MASK, + 550 => Opcode::PseudoNDS_VFPMADB_VFPR16_M8, + 551 => Opcode::PseudoNDS_VFPMADB_VFPR16_M8_MASK, + 552 => Opcode::PseudoNDS_VFPMADB_VFPR16_MF2, + 553 => Opcode::PseudoNDS_VFPMADB_VFPR16_MF2_MASK, + 554 => Opcode::PseudoNDS_VFPMADB_VFPR16_MF4, + 555 => Opcode::PseudoNDS_VFPMADB_VFPR16_MF4_MASK, + 556 => Opcode::PseudoNDS_VFPMADT_VFPR16_M1, + 557 => Opcode::PseudoNDS_VFPMADT_VFPR16_M1_MASK, + 558 => Opcode::PseudoNDS_VFPMADT_VFPR16_M2, + 559 => Opcode::PseudoNDS_VFPMADT_VFPR16_M2_MASK, + 560 => Opcode::PseudoNDS_VFPMADT_VFPR16_M4, + 561 => Opcode::PseudoNDS_VFPMADT_VFPR16_M4_MASK, + 562 => Opcode::PseudoNDS_VFPMADT_VFPR16_M8, + 563 => Opcode::PseudoNDS_VFPMADT_VFPR16_M8_MASK, + 564 => Opcode::PseudoNDS_VFPMADT_VFPR16_MF2, + 565 => Opcode::PseudoNDS_VFPMADT_VFPR16_MF2_MASK, + 566 => Opcode::PseudoNDS_VFPMADT_VFPR16_MF4, + 567 => Opcode::PseudoNDS_VFPMADT_VFPR16_MF4_MASK, + 568 => Opcode::PseudoNDS_VFWCVT_S_BF16_M1, + 569 => Opcode::PseudoNDS_VFWCVT_S_BF16_M2, + 570 => Opcode::PseudoNDS_VFWCVT_S_BF16_M4, + 571 => Opcode::PseudoNDS_VFWCVT_S_BF16_MF2, + 572 => Opcode::PseudoNDS_VFWCVT_S_BF16_MF4, + 573 => Opcode::PseudoNDS_VLN8_V_M1, + 574 => Opcode::PseudoNDS_VLN8_V_M1_MASK, + 575 => Opcode::PseudoNDS_VLN8_V_M2, + 576 => Opcode::PseudoNDS_VLN8_V_M2_MASK, + 577 => Opcode::PseudoNDS_VLN8_V_M4, + 578 => Opcode::PseudoNDS_VLN8_V_M4_MASK, + 579 => Opcode::PseudoNDS_VLN8_V_M8, + 580 => Opcode::PseudoNDS_VLN8_V_M8_MASK, + 581 => Opcode::PseudoNDS_VLN8_V_MF2, + 582 => Opcode::PseudoNDS_VLN8_V_MF2_MASK, + 583 => Opcode::PseudoNDS_VLN8_V_MF4, + 584 => Opcode::PseudoNDS_VLN8_V_MF4_MASK, + 585 => Opcode::PseudoNDS_VLN8_V_MF8, + 586 => Opcode::PseudoNDS_VLN8_V_MF8_MASK, + 587 => Opcode::PseudoNDS_VLNU8_V_M1, + 588 => Opcode::PseudoNDS_VLNU8_V_M1_MASK, + 589 => Opcode::PseudoNDS_VLNU8_V_M2, + 590 => Opcode::PseudoNDS_VLNU8_V_M2_MASK, + 591 => Opcode::PseudoNDS_VLNU8_V_M4, + 592 => Opcode::PseudoNDS_VLNU8_V_M4_MASK, + 593 => Opcode::PseudoNDS_VLNU8_V_M8, + 594 => Opcode::PseudoNDS_VLNU8_V_M8_MASK, + 595 => Opcode::PseudoNDS_VLNU8_V_MF2, + 596 => Opcode::PseudoNDS_VLNU8_V_MF2_MASK, + 597 => Opcode::PseudoNDS_VLNU8_V_MF4, + 598 => Opcode::PseudoNDS_VLNU8_V_MF4_MASK, + 599 => Opcode::PseudoNDS_VLNU8_V_MF8, + 600 => Opcode::PseudoNDS_VLNU8_V_MF8_MASK, + 601 => Opcode::PseudoQC_E_LB, + 602 => Opcode::PseudoQC_E_LBU, + 603 => Opcode::PseudoQC_E_LH, + 604 => Opcode::PseudoQC_E_LHU, + 605 => Opcode::PseudoQC_E_LW, + 606 => Opcode::PseudoQC_E_SB, + 607 => Opcode::PseudoQC_E_SH, + 608 => Opcode::PseudoQC_E_SW, + 609 => Opcode::PseudoQuietFLE_D, + 610 => Opcode::PseudoQuietFLE_D_IN32X, + 611 => Opcode::PseudoQuietFLE_D_INX, + 612 => Opcode::PseudoQuietFLE_H, + 613 => Opcode::PseudoQuietFLE_H_INX, + 614 => Opcode::PseudoQuietFLE_S, + 615 => Opcode::PseudoQuietFLE_S_INX, + 616 => Opcode::PseudoQuietFLT_D, + 617 => Opcode::PseudoQuietFLT_D_IN32X, + 618 => Opcode::PseudoQuietFLT_D_INX, + 619 => Opcode::PseudoQuietFLT_H, + 620 => Opcode::PseudoQuietFLT_H_INX, + 621 => Opcode::PseudoQuietFLT_S, + 622 => Opcode::PseudoQuietFLT_S_INX, + 623 => Opcode::PseudoRET, + 624 => Opcode::PseudoRI_VEXTRACT_M1, + 625 => Opcode::PseudoRI_VEXTRACT_M2, + 626 => Opcode::PseudoRI_VEXTRACT_M4, + 627 => Opcode::PseudoRI_VEXTRACT_M8, + 628 => Opcode::PseudoRI_VEXTRACT_MF2, + 629 => Opcode::PseudoRI_VEXTRACT_MF4, + 630 => Opcode::PseudoRI_VEXTRACT_MF8, + 631 => Opcode::PseudoRI_VINSERT_M1, + 632 => Opcode::PseudoRI_VINSERT_M2, + 633 => Opcode::PseudoRI_VINSERT_M4, + 634 => Opcode::PseudoRI_VINSERT_M8, + 635 => Opcode::PseudoRI_VINSERT_MF2, + 636 => Opcode::PseudoRI_VINSERT_MF4, + 637 => Opcode::PseudoRI_VINSERT_MF8, + 638 => Opcode::PseudoRI_VUNZIP2A_VV_M1, + 639 => Opcode::PseudoRI_VUNZIP2A_VV_M1_MASK, + 640 => Opcode::PseudoRI_VUNZIP2A_VV_M2, + 641 => Opcode::PseudoRI_VUNZIP2A_VV_M2_MASK, + 642 => Opcode::PseudoRI_VUNZIP2A_VV_M4, + 643 => Opcode::PseudoRI_VUNZIP2A_VV_M4_MASK, + 644 => Opcode::PseudoRI_VUNZIP2A_VV_M8, + 645 => Opcode::PseudoRI_VUNZIP2A_VV_M8_MASK, + 646 => Opcode::PseudoRI_VUNZIP2A_VV_MF2, + 647 => Opcode::PseudoRI_VUNZIP2A_VV_MF2_MASK, + 648 => Opcode::PseudoRI_VUNZIP2A_VV_MF4, + 649 => Opcode::PseudoRI_VUNZIP2A_VV_MF4_MASK, + 650 => Opcode::PseudoRI_VUNZIP2A_VV_MF8, + 651 => Opcode::PseudoRI_VUNZIP2A_VV_MF8_MASK, + 652 => Opcode::PseudoRI_VUNZIP2B_VV_M1, + 653 => Opcode::PseudoRI_VUNZIP2B_VV_M1_MASK, + 654 => Opcode::PseudoRI_VUNZIP2B_VV_M2, + 655 => Opcode::PseudoRI_VUNZIP2B_VV_M2_MASK, + 656 => Opcode::PseudoRI_VUNZIP2B_VV_M4, + 657 => Opcode::PseudoRI_VUNZIP2B_VV_M4_MASK, + 658 => Opcode::PseudoRI_VUNZIP2B_VV_M8, + 659 => Opcode::PseudoRI_VUNZIP2B_VV_M8_MASK, + 660 => Opcode::PseudoRI_VUNZIP2B_VV_MF2, + 661 => Opcode::PseudoRI_VUNZIP2B_VV_MF2_MASK, + 662 => Opcode::PseudoRI_VUNZIP2B_VV_MF4, + 663 => Opcode::PseudoRI_VUNZIP2B_VV_MF4_MASK, + 664 => Opcode::PseudoRI_VUNZIP2B_VV_MF8, + 665 => Opcode::PseudoRI_VUNZIP2B_VV_MF8_MASK, + 666 => Opcode::PseudoRI_VZIP2A_VV_M1, + 667 => Opcode::PseudoRI_VZIP2A_VV_M1_MASK, + 668 => Opcode::PseudoRI_VZIP2A_VV_M2, + 669 => Opcode::PseudoRI_VZIP2A_VV_M2_MASK, + 670 => Opcode::PseudoRI_VZIP2A_VV_M4, + 671 => Opcode::PseudoRI_VZIP2A_VV_M4_MASK, + 672 => Opcode::PseudoRI_VZIP2A_VV_M8, + 673 => Opcode::PseudoRI_VZIP2A_VV_M8_MASK, + 674 => Opcode::PseudoRI_VZIP2A_VV_MF2, + 675 => Opcode::PseudoRI_VZIP2A_VV_MF2_MASK, + 676 => Opcode::PseudoRI_VZIP2A_VV_MF4, + 677 => Opcode::PseudoRI_VZIP2A_VV_MF4_MASK, + 678 => Opcode::PseudoRI_VZIP2A_VV_MF8, + 679 => Opcode::PseudoRI_VZIP2A_VV_MF8_MASK, + 680 => Opcode::PseudoRI_VZIP2B_VV_M1, + 681 => Opcode::PseudoRI_VZIP2B_VV_M1_MASK, + 682 => Opcode::PseudoRI_VZIP2B_VV_M2, + 683 => Opcode::PseudoRI_VZIP2B_VV_M2_MASK, + 684 => Opcode::PseudoRI_VZIP2B_VV_M4, + 685 => Opcode::PseudoRI_VZIP2B_VV_M4_MASK, + 686 => Opcode::PseudoRI_VZIP2B_VV_M8, + 687 => Opcode::PseudoRI_VZIP2B_VV_M8_MASK, + 688 => Opcode::PseudoRI_VZIP2B_VV_MF2, + 689 => Opcode::PseudoRI_VZIP2B_VV_MF2_MASK, + 690 => Opcode::PseudoRI_VZIP2B_VV_MF4, + 691 => Opcode::PseudoRI_VZIP2B_VV_MF4_MASK, + 692 => Opcode::PseudoRI_VZIP2B_VV_MF8, + 693 => Opcode::PseudoRI_VZIP2B_VV_MF8_MASK, + 694 => Opcode::PseudoRI_VZIPEVEN_VV_M1, + 695 => Opcode::PseudoRI_VZIPEVEN_VV_M1_MASK, + 696 => Opcode::PseudoRI_VZIPEVEN_VV_M2, + 697 => Opcode::PseudoRI_VZIPEVEN_VV_M2_MASK, + 698 => Opcode::PseudoRI_VZIPEVEN_VV_M4, + 699 => Opcode::PseudoRI_VZIPEVEN_VV_M4_MASK, + 700 => Opcode::PseudoRI_VZIPEVEN_VV_M8, + 701 => Opcode::PseudoRI_VZIPEVEN_VV_M8_MASK, + 702 => Opcode::PseudoRI_VZIPEVEN_VV_MF2, + 703 => Opcode::PseudoRI_VZIPEVEN_VV_MF2_MASK, + 704 => Opcode::PseudoRI_VZIPEVEN_VV_MF4, + 705 => Opcode::PseudoRI_VZIPEVEN_VV_MF4_MASK, + 706 => Opcode::PseudoRI_VZIPEVEN_VV_MF8, + 707 => Opcode::PseudoRI_VZIPEVEN_VV_MF8_MASK, + 708 => Opcode::PseudoRI_VZIPODD_VV_M1, + 709 => Opcode::PseudoRI_VZIPODD_VV_M1_MASK, + 710 => Opcode::PseudoRI_VZIPODD_VV_M2, + 711 => Opcode::PseudoRI_VZIPODD_VV_M2_MASK, + 712 => Opcode::PseudoRI_VZIPODD_VV_M4, + 713 => Opcode::PseudoRI_VZIPODD_VV_M4_MASK, + 714 => Opcode::PseudoRI_VZIPODD_VV_M8, + 715 => Opcode::PseudoRI_VZIPODD_VV_M8_MASK, + 716 => Opcode::PseudoRI_VZIPODD_VV_MF2, + 717 => Opcode::PseudoRI_VZIPODD_VV_MF2_MASK, + 718 => Opcode::PseudoRI_VZIPODD_VV_MF4, + 719 => Opcode::PseudoRI_VZIPODD_VV_MF4_MASK, + 720 => Opcode::PseudoRI_VZIPODD_VV_MF8, + 721 => Opcode::PseudoRI_VZIPODD_VV_MF8_MASK, + 722 => Opcode::PseudoRV32ZdinxLD, + 723 => Opcode::PseudoRV32ZdinxSD, + 724 => Opcode::PseudoReadVL, + 725 => Opcode::PseudoReadVLENB, + 726 => Opcode::PseudoReadVLENBViaVSETVLIX0, + 727 => Opcode::PseudoSB, + 728 => Opcode::PseudoSD, + 729 => Opcode::PseudoSD_RV32, + 730 => Opcode::PseudoSD_RV32_OPT, + 731 => Opcode::PseudoSEXT_B, + 732 => Opcode::PseudoSEXT_H, + 733 => Opcode::PseudoSF_MM_E4M3_E4M3, + 734 => Opcode::PseudoSF_MM_E4M3_E5M2, + 735 => Opcode::PseudoSF_MM_E5M2_E4M3, + 736 => Opcode::PseudoSF_MM_E5M2_E5M2, + 737 => Opcode::PseudoSF_MM_F_F, + 738 => Opcode::PseudoSF_MM_F_F_ALT, + 739 => Opcode::PseudoSF_MM_S_S, + 740 => Opcode::PseudoSF_MM_S_U, + 741 => Opcode::PseudoSF_MM_U_S, + 742 => Opcode::PseudoSF_MM_U_U, + 743 => Opcode::PseudoSF_VC_FPR16VV_SE_M1, + 744 => Opcode::PseudoSF_VC_FPR16VV_SE_M2, + 745 => Opcode::PseudoSF_VC_FPR16VV_SE_M4, + 746 => Opcode::PseudoSF_VC_FPR16VV_SE_M8, + 747 => Opcode::PseudoSF_VC_FPR16VV_SE_MF2, + 748 => Opcode::PseudoSF_VC_FPR16VV_SE_MF4, + 749 => Opcode::PseudoSF_VC_FPR16VW_SE_M1, + 750 => Opcode::PseudoSF_VC_FPR16VW_SE_M2, + 751 => Opcode::PseudoSF_VC_FPR16VW_SE_M4, + 752 => Opcode::PseudoSF_VC_FPR16VW_SE_M8, + 753 => Opcode::PseudoSF_VC_FPR16VW_SE_MF2, + 754 => Opcode::PseudoSF_VC_FPR16VW_SE_MF4, + 755 => Opcode::PseudoSF_VC_FPR16V_SE_M1, + 756 => Opcode::PseudoSF_VC_FPR16V_SE_M2, + 757 => Opcode::PseudoSF_VC_FPR16V_SE_M4, + 758 => Opcode::PseudoSF_VC_FPR16V_SE_M8, + 759 => Opcode::PseudoSF_VC_FPR16V_SE_MF2, + 760 => Opcode::PseudoSF_VC_FPR16V_SE_MF4, + 761 => Opcode::PseudoSF_VC_FPR32VV_SE_M1, + 762 => Opcode::PseudoSF_VC_FPR32VV_SE_M2, + 763 => Opcode::PseudoSF_VC_FPR32VV_SE_M4, + 764 => Opcode::PseudoSF_VC_FPR32VV_SE_M8, + 765 => Opcode::PseudoSF_VC_FPR32VV_SE_MF2, + 766 => Opcode::PseudoSF_VC_FPR32VW_SE_M1, + 767 => Opcode::PseudoSF_VC_FPR32VW_SE_M2, + 768 => Opcode::PseudoSF_VC_FPR32VW_SE_M4, + 769 => Opcode::PseudoSF_VC_FPR32VW_SE_M8, + 770 => Opcode::PseudoSF_VC_FPR32VW_SE_MF2, + 771 => Opcode::PseudoSF_VC_FPR32V_SE_M1, + 772 => Opcode::PseudoSF_VC_FPR32V_SE_M2, + 773 => Opcode::PseudoSF_VC_FPR32V_SE_M4, + 774 => Opcode::PseudoSF_VC_FPR32V_SE_M8, + 775 => Opcode::PseudoSF_VC_FPR32V_SE_MF2, + 776 => Opcode::PseudoSF_VC_FPR64VV_SE_M1, + 777 => Opcode::PseudoSF_VC_FPR64VV_SE_M2, + 778 => Opcode::PseudoSF_VC_FPR64VV_SE_M4, + 779 => Opcode::PseudoSF_VC_FPR64VV_SE_M8, + 780 => Opcode::PseudoSF_VC_FPR64V_SE_M1, + 781 => Opcode::PseudoSF_VC_FPR64V_SE_M2, + 782 => Opcode::PseudoSF_VC_FPR64V_SE_M4, + 783 => Opcode::PseudoSF_VC_FPR64V_SE_M8, + 784 => Opcode::PseudoSF_VC_IVV_SE_M1, + 785 => Opcode::PseudoSF_VC_IVV_SE_M2, + 786 => Opcode::PseudoSF_VC_IVV_SE_M4, + 787 => Opcode::PseudoSF_VC_IVV_SE_M8, + 788 => Opcode::PseudoSF_VC_IVV_SE_MF2, + 789 => Opcode::PseudoSF_VC_IVV_SE_MF4, + 790 => Opcode::PseudoSF_VC_IVV_SE_MF8, + 791 => Opcode::PseudoSF_VC_IVW_SE_M1, + 792 => Opcode::PseudoSF_VC_IVW_SE_M2, + 793 => Opcode::PseudoSF_VC_IVW_SE_M4, + 794 => Opcode::PseudoSF_VC_IVW_SE_MF2, + 795 => Opcode::PseudoSF_VC_IVW_SE_MF4, + 796 => Opcode::PseudoSF_VC_IVW_SE_MF8, + 797 => Opcode::PseudoSF_VC_IV_SE_M1, + 798 => Opcode::PseudoSF_VC_IV_SE_M2, + 799 => Opcode::PseudoSF_VC_IV_SE_M4, + 800 => Opcode::PseudoSF_VC_IV_SE_M8, + 801 => Opcode::PseudoSF_VC_IV_SE_MF2, + 802 => Opcode::PseudoSF_VC_IV_SE_MF4, + 803 => Opcode::PseudoSF_VC_IV_SE_MF8, + 804 => Opcode::PseudoSF_VC_I_SE_M1, + 805 => Opcode::PseudoSF_VC_I_SE_M2, + 806 => Opcode::PseudoSF_VC_I_SE_M4, + 807 => Opcode::PseudoSF_VC_I_SE_M8, + 808 => Opcode::PseudoSF_VC_I_SE_MF2, + 809 => Opcode::PseudoSF_VC_I_SE_MF4, + 810 => Opcode::PseudoSF_VC_I_SE_MF8, + 811 => Opcode::PseudoSF_VC_VVV_SE_M1, + 812 => Opcode::PseudoSF_VC_VVV_SE_M2, + 813 => Opcode::PseudoSF_VC_VVV_SE_M4, + 814 => Opcode::PseudoSF_VC_VVV_SE_M8, + 815 => Opcode::PseudoSF_VC_VVV_SE_MF2, + 816 => Opcode::PseudoSF_VC_VVV_SE_MF4, + 817 => Opcode::PseudoSF_VC_VVV_SE_MF8, + 818 => Opcode::PseudoSF_VC_VVW_SE_M1, + 819 => Opcode::PseudoSF_VC_VVW_SE_M2, + 820 => Opcode::PseudoSF_VC_VVW_SE_M4, + 821 => Opcode::PseudoSF_VC_VVW_SE_MF2, + 822 => Opcode::PseudoSF_VC_VVW_SE_MF4, + 823 => Opcode::PseudoSF_VC_VVW_SE_MF8, + 824 => Opcode::PseudoSF_VC_VV_SE_M1, + 825 => Opcode::PseudoSF_VC_VV_SE_M2, + 826 => Opcode::PseudoSF_VC_VV_SE_M4, + 827 => Opcode::PseudoSF_VC_VV_SE_M8, + 828 => Opcode::PseudoSF_VC_VV_SE_MF2, + 829 => Opcode::PseudoSF_VC_VV_SE_MF4, + 830 => Opcode::PseudoSF_VC_VV_SE_MF8, + 831 => Opcode::PseudoSF_VC_V_FPR16VV_M1, + 832 => Opcode::PseudoSF_VC_V_FPR16VV_M2, + 833 => Opcode::PseudoSF_VC_V_FPR16VV_M4, + 834 => Opcode::PseudoSF_VC_V_FPR16VV_M8, + 835 => Opcode::PseudoSF_VC_V_FPR16VV_MF2, + 836 => Opcode::PseudoSF_VC_V_FPR16VV_MF4, + 837 => Opcode::PseudoSF_VC_V_FPR16VV_SE_M1, + 838 => Opcode::PseudoSF_VC_V_FPR16VV_SE_M2, + 839 => Opcode::PseudoSF_VC_V_FPR16VV_SE_M4, + 840 => Opcode::PseudoSF_VC_V_FPR16VV_SE_M8, + 841 => Opcode::PseudoSF_VC_V_FPR16VV_SE_MF2, + 842 => Opcode::PseudoSF_VC_V_FPR16VV_SE_MF4, + 843 => Opcode::PseudoSF_VC_V_FPR16VW_M1, + 844 => Opcode::PseudoSF_VC_V_FPR16VW_M2, + 845 => Opcode::PseudoSF_VC_V_FPR16VW_M4, + 846 => Opcode::PseudoSF_VC_V_FPR16VW_M8, + 847 => Opcode::PseudoSF_VC_V_FPR16VW_MF2, + 848 => Opcode::PseudoSF_VC_V_FPR16VW_MF4, + 849 => Opcode::PseudoSF_VC_V_FPR16VW_SE_M1, + 850 => Opcode::PseudoSF_VC_V_FPR16VW_SE_M2, + 851 => Opcode::PseudoSF_VC_V_FPR16VW_SE_M4, + 852 => Opcode::PseudoSF_VC_V_FPR16VW_SE_M8, + 853 => Opcode::PseudoSF_VC_V_FPR16VW_SE_MF2, + 854 => Opcode::PseudoSF_VC_V_FPR16VW_SE_MF4, + 855 => Opcode::PseudoSF_VC_V_FPR16V_M1, + 856 => Opcode::PseudoSF_VC_V_FPR16V_M2, + 857 => Opcode::PseudoSF_VC_V_FPR16V_M4, + 858 => Opcode::PseudoSF_VC_V_FPR16V_M8, + 859 => Opcode::PseudoSF_VC_V_FPR16V_MF2, + 860 => Opcode::PseudoSF_VC_V_FPR16V_MF4, + 861 => Opcode::PseudoSF_VC_V_FPR16V_SE_M1, + 862 => Opcode::PseudoSF_VC_V_FPR16V_SE_M2, + 863 => Opcode::PseudoSF_VC_V_FPR16V_SE_M4, + 864 => Opcode::PseudoSF_VC_V_FPR16V_SE_M8, + 865 => Opcode::PseudoSF_VC_V_FPR16V_SE_MF2, + 866 => Opcode::PseudoSF_VC_V_FPR16V_SE_MF4, + 867 => Opcode::PseudoSF_VC_V_FPR32VV_M1, + 868 => Opcode::PseudoSF_VC_V_FPR32VV_M2, + 869 => Opcode::PseudoSF_VC_V_FPR32VV_M4, + 870 => Opcode::PseudoSF_VC_V_FPR32VV_M8, + 871 => Opcode::PseudoSF_VC_V_FPR32VV_MF2, + 872 => Opcode::PseudoSF_VC_V_FPR32VV_SE_M1, + 873 => Opcode::PseudoSF_VC_V_FPR32VV_SE_M2, + 874 => Opcode::PseudoSF_VC_V_FPR32VV_SE_M4, + 875 => Opcode::PseudoSF_VC_V_FPR32VV_SE_M8, + 876 => Opcode::PseudoSF_VC_V_FPR32VV_SE_MF2, + 877 => Opcode::PseudoSF_VC_V_FPR32VW_M1, + 878 => Opcode::PseudoSF_VC_V_FPR32VW_M2, + 879 => Opcode::PseudoSF_VC_V_FPR32VW_M4, + 880 => Opcode::PseudoSF_VC_V_FPR32VW_M8, + 881 => Opcode::PseudoSF_VC_V_FPR32VW_MF2, + 882 => Opcode::PseudoSF_VC_V_FPR32VW_SE_M1, + 883 => Opcode::PseudoSF_VC_V_FPR32VW_SE_M2, + 884 => Opcode::PseudoSF_VC_V_FPR32VW_SE_M4, + 885 => Opcode::PseudoSF_VC_V_FPR32VW_SE_M8, + 886 => Opcode::PseudoSF_VC_V_FPR32VW_SE_MF2, + 887 => Opcode::PseudoSF_VC_V_FPR32V_M1, + 888 => Opcode::PseudoSF_VC_V_FPR32V_M2, + 889 => Opcode::PseudoSF_VC_V_FPR32V_M4, + 890 => Opcode::PseudoSF_VC_V_FPR32V_M8, + 891 => Opcode::PseudoSF_VC_V_FPR32V_MF2, + 892 => Opcode::PseudoSF_VC_V_FPR32V_SE_M1, + 893 => Opcode::PseudoSF_VC_V_FPR32V_SE_M2, + 894 => Opcode::PseudoSF_VC_V_FPR32V_SE_M4, + 895 => Opcode::PseudoSF_VC_V_FPR32V_SE_M8, + 896 => Opcode::PseudoSF_VC_V_FPR32V_SE_MF2, + 897 => Opcode::PseudoSF_VC_V_FPR64VV_M1, + 898 => Opcode::PseudoSF_VC_V_FPR64VV_M2, + 899 => Opcode::PseudoSF_VC_V_FPR64VV_M4, + 900 => Opcode::PseudoSF_VC_V_FPR64VV_M8, + 901 => Opcode::PseudoSF_VC_V_FPR64VV_SE_M1, + 902 => Opcode::PseudoSF_VC_V_FPR64VV_SE_M2, + 903 => Opcode::PseudoSF_VC_V_FPR64VV_SE_M4, + 904 => Opcode::PseudoSF_VC_V_FPR64VV_SE_M8, + 905 => Opcode::PseudoSF_VC_V_FPR64V_M1, + 906 => Opcode::PseudoSF_VC_V_FPR64V_M2, + 907 => Opcode::PseudoSF_VC_V_FPR64V_M4, + 908 => Opcode::PseudoSF_VC_V_FPR64V_M8, + 909 => Opcode::PseudoSF_VC_V_FPR64V_SE_M1, + 910 => Opcode::PseudoSF_VC_V_FPR64V_SE_M2, + 911 => Opcode::PseudoSF_VC_V_FPR64V_SE_M4, + 912 => Opcode::PseudoSF_VC_V_FPR64V_SE_M8, + 913 => Opcode::PseudoSF_VC_V_IVV_M1, + 914 => Opcode::PseudoSF_VC_V_IVV_M2, + 915 => Opcode::PseudoSF_VC_V_IVV_M4, + 916 => Opcode::PseudoSF_VC_V_IVV_M8, + 917 => Opcode::PseudoSF_VC_V_IVV_MF2, + 918 => Opcode::PseudoSF_VC_V_IVV_MF4, + 919 => Opcode::PseudoSF_VC_V_IVV_MF8, + 920 => Opcode::PseudoSF_VC_V_IVV_SE_M1, + 921 => Opcode::PseudoSF_VC_V_IVV_SE_M2, + 922 => Opcode::PseudoSF_VC_V_IVV_SE_M4, + 923 => Opcode::PseudoSF_VC_V_IVV_SE_M8, + 924 => Opcode::PseudoSF_VC_V_IVV_SE_MF2, + 925 => Opcode::PseudoSF_VC_V_IVV_SE_MF4, + 926 => Opcode::PseudoSF_VC_V_IVV_SE_MF8, + 927 => Opcode::PseudoSF_VC_V_IVW_M1, + 928 => Opcode::PseudoSF_VC_V_IVW_M2, + 929 => Opcode::PseudoSF_VC_V_IVW_M4, + 930 => Opcode::PseudoSF_VC_V_IVW_MF2, + 931 => Opcode::PseudoSF_VC_V_IVW_MF4, + 932 => Opcode::PseudoSF_VC_V_IVW_MF8, + 933 => Opcode::PseudoSF_VC_V_IVW_SE_M1, + 934 => Opcode::PseudoSF_VC_V_IVW_SE_M2, + 935 => Opcode::PseudoSF_VC_V_IVW_SE_M4, + 936 => Opcode::PseudoSF_VC_V_IVW_SE_MF2, + 937 => Opcode::PseudoSF_VC_V_IVW_SE_MF4, + 938 => Opcode::PseudoSF_VC_V_IVW_SE_MF8, + 939 => Opcode::PseudoSF_VC_V_IV_M1, + 940 => Opcode::PseudoSF_VC_V_IV_M2, + 941 => Opcode::PseudoSF_VC_V_IV_M4, + 942 => Opcode::PseudoSF_VC_V_IV_M8, + 943 => Opcode::PseudoSF_VC_V_IV_MF2, + 944 => Opcode::PseudoSF_VC_V_IV_MF4, + 945 => Opcode::PseudoSF_VC_V_IV_MF8, + 946 => Opcode::PseudoSF_VC_V_IV_SE_M1, + 947 => Opcode::PseudoSF_VC_V_IV_SE_M2, + 948 => Opcode::PseudoSF_VC_V_IV_SE_M4, + 949 => Opcode::PseudoSF_VC_V_IV_SE_M8, + 950 => Opcode::PseudoSF_VC_V_IV_SE_MF2, + 951 => Opcode::PseudoSF_VC_V_IV_SE_MF4, + 952 => Opcode::PseudoSF_VC_V_IV_SE_MF8, + 953 => Opcode::PseudoSF_VC_V_I_M1, + 954 => Opcode::PseudoSF_VC_V_I_M2, + 955 => Opcode::PseudoSF_VC_V_I_M4, + 956 => Opcode::PseudoSF_VC_V_I_M8, + 957 => Opcode::PseudoSF_VC_V_I_MF2, + 958 => Opcode::PseudoSF_VC_V_I_MF4, + 959 => Opcode::PseudoSF_VC_V_I_MF8, + 960 => Opcode::PseudoSF_VC_V_I_SE_M1, + 961 => Opcode::PseudoSF_VC_V_I_SE_M2, + 962 => Opcode::PseudoSF_VC_V_I_SE_M4, + 963 => Opcode::PseudoSF_VC_V_I_SE_M8, + 964 => Opcode::PseudoSF_VC_V_I_SE_MF2, + 965 => Opcode::PseudoSF_VC_V_I_SE_MF4, + 966 => Opcode::PseudoSF_VC_V_I_SE_MF8, + 967 => Opcode::PseudoSF_VC_V_VVV_M1, + 968 => Opcode::PseudoSF_VC_V_VVV_M2, + 969 => Opcode::PseudoSF_VC_V_VVV_M4, + 970 => Opcode::PseudoSF_VC_V_VVV_M8, + 971 => Opcode::PseudoSF_VC_V_VVV_MF2, + 972 => Opcode::PseudoSF_VC_V_VVV_MF4, + 973 => Opcode::PseudoSF_VC_V_VVV_MF8, + 974 => Opcode::PseudoSF_VC_V_VVV_SE_M1, + 975 => Opcode::PseudoSF_VC_V_VVV_SE_M2, + 976 => Opcode::PseudoSF_VC_V_VVV_SE_M4, + 977 => Opcode::PseudoSF_VC_V_VVV_SE_M8, + 978 => Opcode::PseudoSF_VC_V_VVV_SE_MF2, + 979 => Opcode::PseudoSF_VC_V_VVV_SE_MF4, + 980 => Opcode::PseudoSF_VC_V_VVV_SE_MF8, + 981 => Opcode::PseudoSF_VC_V_VVW_M1, + 982 => Opcode::PseudoSF_VC_V_VVW_M2, + 983 => Opcode::PseudoSF_VC_V_VVW_M4, + 984 => Opcode::PseudoSF_VC_V_VVW_MF2, + 985 => Opcode::PseudoSF_VC_V_VVW_MF4, + 986 => Opcode::PseudoSF_VC_V_VVW_MF8, + 987 => Opcode::PseudoSF_VC_V_VVW_SE_M1, + 988 => Opcode::PseudoSF_VC_V_VVW_SE_M2, + 989 => Opcode::PseudoSF_VC_V_VVW_SE_M4, + 990 => Opcode::PseudoSF_VC_V_VVW_SE_MF2, + 991 => Opcode::PseudoSF_VC_V_VVW_SE_MF4, + 992 => Opcode::PseudoSF_VC_V_VVW_SE_MF8, + 993 => Opcode::PseudoSF_VC_V_VV_M1, + 994 => Opcode::PseudoSF_VC_V_VV_M2, + 995 => Opcode::PseudoSF_VC_V_VV_M4, + 996 => Opcode::PseudoSF_VC_V_VV_M8, + 997 => Opcode::PseudoSF_VC_V_VV_MF2, + 998 => Opcode::PseudoSF_VC_V_VV_MF4, + 999 => Opcode::PseudoSF_VC_V_VV_MF8, + 1000 => Opcode::PseudoSF_VC_V_VV_SE_M1, + 1001 => Opcode::PseudoSF_VC_V_VV_SE_M2, + 1002 => Opcode::PseudoSF_VC_V_VV_SE_M4, + 1003 => Opcode::PseudoSF_VC_V_VV_SE_M8, + 1004 => Opcode::PseudoSF_VC_V_VV_SE_MF2, + 1005 => Opcode::PseudoSF_VC_V_VV_SE_MF4, + 1006 => Opcode::PseudoSF_VC_V_VV_SE_MF8, + 1007 => Opcode::PseudoSF_VC_V_XVV_M1, + 1008 => Opcode::PseudoSF_VC_V_XVV_M2, + 1009 => Opcode::PseudoSF_VC_V_XVV_M4, + 1010 => Opcode::PseudoSF_VC_V_XVV_M8, + 1011 => Opcode::PseudoSF_VC_V_XVV_MF2, + 1012 => Opcode::PseudoSF_VC_V_XVV_MF4, + 1013 => Opcode::PseudoSF_VC_V_XVV_MF8, + 1014 => Opcode::PseudoSF_VC_V_XVV_SE_M1, + 1015 => Opcode::PseudoSF_VC_V_XVV_SE_M2, + 1016 => Opcode::PseudoSF_VC_V_XVV_SE_M4, + 1017 => Opcode::PseudoSF_VC_V_XVV_SE_M8, + 1018 => Opcode::PseudoSF_VC_V_XVV_SE_MF2, + 1019 => Opcode::PseudoSF_VC_V_XVV_SE_MF4, + 1020 => Opcode::PseudoSF_VC_V_XVV_SE_MF8, + 1021 => Opcode::PseudoSF_VC_V_XVW_M1, + 1022 => Opcode::PseudoSF_VC_V_XVW_M2, + 1023 => Opcode::PseudoSF_VC_V_XVW_M4, + 1024 => Opcode::PseudoSF_VC_V_XVW_MF2, + 1025 => Opcode::PseudoSF_VC_V_XVW_MF4, + 1026 => Opcode::PseudoSF_VC_V_XVW_MF8, + 1027 => Opcode::PseudoSF_VC_V_XVW_SE_M1, + 1028 => Opcode::PseudoSF_VC_V_XVW_SE_M2, + 1029 => Opcode::PseudoSF_VC_V_XVW_SE_M4, + 1030 => Opcode::PseudoSF_VC_V_XVW_SE_MF2, + 1031 => Opcode::PseudoSF_VC_V_XVW_SE_MF4, + 1032 => Opcode::PseudoSF_VC_V_XVW_SE_MF8, + 1033 => Opcode::PseudoSF_VC_V_XV_M1, + 1034 => Opcode::PseudoSF_VC_V_XV_M2, + 1035 => Opcode::PseudoSF_VC_V_XV_M4, + 1036 => Opcode::PseudoSF_VC_V_XV_M8, + 1037 => Opcode::PseudoSF_VC_V_XV_MF2, + 1038 => Opcode::PseudoSF_VC_V_XV_MF4, + 1039 => Opcode::PseudoSF_VC_V_XV_MF8, + 1040 => Opcode::PseudoSF_VC_V_XV_SE_M1, + 1041 => Opcode::PseudoSF_VC_V_XV_SE_M2, + 1042 => Opcode::PseudoSF_VC_V_XV_SE_M4, + 1043 => Opcode::PseudoSF_VC_V_XV_SE_M8, + 1044 => Opcode::PseudoSF_VC_V_XV_SE_MF2, + 1045 => Opcode::PseudoSF_VC_V_XV_SE_MF4, + 1046 => Opcode::PseudoSF_VC_V_XV_SE_MF8, + 1047 => Opcode::PseudoSF_VC_V_X_M1, + 1048 => Opcode::PseudoSF_VC_V_X_M2, + 1049 => Opcode::PseudoSF_VC_V_X_M4, + 1050 => Opcode::PseudoSF_VC_V_X_M8, + 1051 => Opcode::PseudoSF_VC_V_X_MF2, + 1052 => Opcode::PseudoSF_VC_V_X_MF4, + 1053 => Opcode::PseudoSF_VC_V_X_MF8, + 1054 => Opcode::PseudoSF_VC_V_X_SE_M1, + 1055 => Opcode::PseudoSF_VC_V_X_SE_M2, + 1056 => Opcode::PseudoSF_VC_V_X_SE_M4, + 1057 => Opcode::PseudoSF_VC_V_X_SE_M8, + 1058 => Opcode::PseudoSF_VC_V_X_SE_MF2, + 1059 => Opcode::PseudoSF_VC_V_X_SE_MF4, + 1060 => Opcode::PseudoSF_VC_V_X_SE_MF8, + 1061 => Opcode::PseudoSF_VC_XVV_SE_M1, + 1062 => Opcode::PseudoSF_VC_XVV_SE_M2, + 1063 => Opcode::PseudoSF_VC_XVV_SE_M4, + 1064 => Opcode::PseudoSF_VC_XVV_SE_M8, + 1065 => Opcode::PseudoSF_VC_XVV_SE_MF2, + 1066 => Opcode::PseudoSF_VC_XVV_SE_MF4, + 1067 => Opcode::PseudoSF_VC_XVV_SE_MF8, + 1068 => Opcode::PseudoSF_VC_XVW_SE_M1, + 1069 => Opcode::PseudoSF_VC_XVW_SE_M2, + 1070 => Opcode::PseudoSF_VC_XVW_SE_M4, + 1071 => Opcode::PseudoSF_VC_XVW_SE_MF2, + 1072 => Opcode::PseudoSF_VC_XVW_SE_MF4, + 1073 => Opcode::PseudoSF_VC_XVW_SE_MF8, + 1074 => Opcode::PseudoSF_VC_XV_SE_M1, + 1075 => Opcode::PseudoSF_VC_XV_SE_M2, + 1076 => Opcode::PseudoSF_VC_XV_SE_M4, + 1077 => Opcode::PseudoSF_VC_XV_SE_M8, + 1078 => Opcode::PseudoSF_VC_XV_SE_MF2, + 1079 => Opcode::PseudoSF_VC_XV_SE_MF4, + 1080 => Opcode::PseudoSF_VC_XV_SE_MF8, + 1081 => Opcode::PseudoSF_VC_X_SE_M1, + 1082 => Opcode::PseudoSF_VC_X_SE_M2, + 1083 => Opcode::PseudoSF_VC_X_SE_M4, + 1084 => Opcode::PseudoSF_VC_X_SE_M8, + 1085 => Opcode::PseudoSF_VC_X_SE_MF2, + 1086 => Opcode::PseudoSF_VC_X_SE_MF4, + 1087 => Opcode::PseudoSF_VC_X_SE_MF8, + 1088 => Opcode::PseudoSF_VFEXPA_V_M1_E16, + 1089 => Opcode::PseudoSF_VFEXPA_V_M1_E16_MASK, + 1090 => Opcode::PseudoSF_VFEXPA_V_M1_E32, + 1091 => Opcode::PseudoSF_VFEXPA_V_M1_E32_MASK, + 1092 => Opcode::PseudoSF_VFEXPA_V_M1_E64, + 1093 => Opcode::PseudoSF_VFEXPA_V_M1_E64_MASK, + 1094 => Opcode::PseudoSF_VFEXPA_V_M2_E16, + 1095 => Opcode::PseudoSF_VFEXPA_V_M2_E16_MASK, + 1096 => Opcode::PseudoSF_VFEXPA_V_M2_E32, + 1097 => Opcode::PseudoSF_VFEXPA_V_M2_E32_MASK, + 1098 => Opcode::PseudoSF_VFEXPA_V_M2_E64, + 1099 => Opcode::PseudoSF_VFEXPA_V_M2_E64_MASK, + 1100 => Opcode::PseudoSF_VFEXPA_V_M4_E16, + 1101 => Opcode::PseudoSF_VFEXPA_V_M4_E16_MASK, + 1102 => Opcode::PseudoSF_VFEXPA_V_M4_E32, + 1103 => Opcode::PseudoSF_VFEXPA_V_M4_E32_MASK, + 1104 => Opcode::PseudoSF_VFEXPA_V_M4_E64, + 1105 => Opcode::PseudoSF_VFEXPA_V_M4_E64_MASK, + 1106 => Opcode::PseudoSF_VFEXPA_V_M8_E16, + 1107 => Opcode::PseudoSF_VFEXPA_V_M8_E16_MASK, + 1108 => Opcode::PseudoSF_VFEXPA_V_M8_E32, + 1109 => Opcode::PseudoSF_VFEXPA_V_M8_E32_MASK, + 1110 => Opcode::PseudoSF_VFEXPA_V_M8_E64, + 1111 => Opcode::PseudoSF_VFEXPA_V_M8_E64_MASK, + 1112 => Opcode::PseudoSF_VFEXPA_V_MF2_E16, + 1113 => Opcode::PseudoSF_VFEXPA_V_MF2_E16_MASK, + 1114 => Opcode::PseudoSF_VFEXPA_V_MF2_E32, + 1115 => Opcode::PseudoSF_VFEXPA_V_MF2_E32_MASK, + 1116 => Opcode::PseudoSF_VFEXPA_V_MF4_E16, + 1117 => Opcode::PseudoSF_VFEXPA_V_MF4_E16_MASK, + 1118 => Opcode::PseudoSF_VFEXP_ALT_V_M1_E16, + 1119 => Opcode::PseudoSF_VFEXP_ALT_V_M1_E16_MASK, + 1120 => Opcode::PseudoSF_VFEXP_ALT_V_M2_E16, + 1121 => Opcode::PseudoSF_VFEXP_ALT_V_M2_E16_MASK, + 1122 => Opcode::PseudoSF_VFEXP_ALT_V_M4_E16, + 1123 => Opcode::PseudoSF_VFEXP_ALT_V_M4_E16_MASK, + 1124 => Opcode::PseudoSF_VFEXP_ALT_V_M8_E16, + 1125 => Opcode::PseudoSF_VFEXP_ALT_V_M8_E16_MASK, + 1126 => Opcode::PseudoSF_VFEXP_ALT_V_MF2_E16, + 1127 => Opcode::PseudoSF_VFEXP_ALT_V_MF2_E16_MASK, + 1128 => Opcode::PseudoSF_VFEXP_ALT_V_MF4_E16, + 1129 => Opcode::PseudoSF_VFEXP_ALT_V_MF4_E16_MASK, + 1130 => Opcode::PseudoSF_VFEXP_V_M1_E16, + 1131 => Opcode::PseudoSF_VFEXP_V_M1_E16_MASK, + 1132 => Opcode::PseudoSF_VFEXP_V_M1_E32, + 1133 => Opcode::PseudoSF_VFEXP_V_M1_E32_MASK, + 1134 => Opcode::PseudoSF_VFEXP_V_M2_E16, + 1135 => Opcode::PseudoSF_VFEXP_V_M2_E16_MASK, + 1136 => Opcode::PseudoSF_VFEXP_V_M2_E32, + 1137 => Opcode::PseudoSF_VFEXP_V_M2_E32_MASK, + 1138 => Opcode::PseudoSF_VFEXP_V_M4_E16, + 1139 => Opcode::PseudoSF_VFEXP_V_M4_E16_MASK, + 1140 => Opcode::PseudoSF_VFEXP_V_M4_E32, + 1141 => Opcode::PseudoSF_VFEXP_V_M4_E32_MASK, + 1142 => Opcode::PseudoSF_VFEXP_V_M8_E16, + 1143 => Opcode::PseudoSF_VFEXP_V_M8_E16_MASK, + 1144 => Opcode::PseudoSF_VFEXP_V_M8_E32, + 1145 => Opcode::PseudoSF_VFEXP_V_M8_E32_MASK, + 1146 => Opcode::PseudoSF_VFEXP_V_MF2_E16, + 1147 => Opcode::PseudoSF_VFEXP_V_MF2_E16_MASK, + 1148 => Opcode::PseudoSF_VFEXP_V_MF2_E32, + 1149 => Opcode::PseudoSF_VFEXP_V_MF2_E32_MASK, + 1150 => Opcode::PseudoSF_VFEXP_V_MF4_E16, + 1151 => Opcode::PseudoSF_VFEXP_V_MF4_E16_MASK, + 1152 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_M1, + 1153 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_M1_MASK, + 1154 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_M2, + 1155 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_M2_MASK, + 1156 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF2, + 1157 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF2_MASK, + 1158 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF4, + 1159 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF4_MASK, + 1160 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF8, + 1161 => Opcode::PseudoSF_VFNRCLIP_XU_F_QF_MF8_MASK, + 1162 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_M1, + 1163 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_M1_MASK, + 1164 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_M2, + 1165 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_M2_MASK, + 1166 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF2, + 1167 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF2_MASK, + 1168 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF4, + 1169 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF4_MASK, + 1170 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF8, + 1171 => Opcode::PseudoSF_VFNRCLIP_X_F_QF_MF8_MASK, + 1172 => Opcode::PseudoSF_VFWMACC_4x4x4_M1, + 1173 => Opcode::PseudoSF_VFWMACC_4x4x4_M2, + 1174 => Opcode::PseudoSF_VFWMACC_4x4x4_M4, + 1175 => Opcode::PseudoSF_VFWMACC_4x4x4_MF2, + 1176 => Opcode::PseudoSF_VFWMACC_4x4x4_MF4, + 1177 => Opcode::PseudoSF_VLTE16, + 1178 => Opcode::PseudoSF_VLTE32, + 1179 => Opcode::PseudoSF_VLTE64, + 1180 => Opcode::PseudoSF_VLTE8, + 1181 => Opcode::PseudoSF_VQMACCSU_2x8x2_M1, + 1182 => Opcode::PseudoSF_VQMACCSU_2x8x2_M2, + 1183 => Opcode::PseudoSF_VQMACCSU_2x8x2_M4, + 1184 => Opcode::PseudoSF_VQMACCSU_2x8x2_M8, + 1185 => Opcode::PseudoSF_VQMACCSU_4x8x4_M1, + 1186 => Opcode::PseudoSF_VQMACCSU_4x8x4_M2, + 1187 => Opcode::PseudoSF_VQMACCSU_4x8x4_M4, + 1188 => Opcode::PseudoSF_VQMACCSU_4x8x4_MF2, + 1189 => Opcode::PseudoSF_VQMACCUS_2x8x2_M1, + 1190 => Opcode::PseudoSF_VQMACCUS_2x8x2_M2, + 1191 => Opcode::PseudoSF_VQMACCUS_2x8x2_M4, + 1192 => Opcode::PseudoSF_VQMACCUS_2x8x2_M8, + 1193 => Opcode::PseudoSF_VQMACCUS_4x8x4_M1, + 1194 => Opcode::PseudoSF_VQMACCUS_4x8x4_M2, + 1195 => Opcode::PseudoSF_VQMACCUS_4x8x4_M4, + 1196 => Opcode::PseudoSF_VQMACCUS_4x8x4_MF2, + 1197 => Opcode::PseudoSF_VQMACCU_2x8x2_M1, + 1198 => Opcode::PseudoSF_VQMACCU_2x8x2_M2, + 1199 => Opcode::PseudoSF_VQMACCU_2x8x2_M4, + 1200 => Opcode::PseudoSF_VQMACCU_2x8x2_M8, + 1201 => Opcode::PseudoSF_VQMACCU_4x8x4_M1, + 1202 => Opcode::PseudoSF_VQMACCU_4x8x4_M2, + 1203 => Opcode::PseudoSF_VQMACCU_4x8x4_M4, + 1204 => Opcode::PseudoSF_VQMACCU_4x8x4_MF2, + 1205 => Opcode::PseudoSF_VQMACC_2x8x2_M1, + 1206 => Opcode::PseudoSF_VQMACC_2x8x2_M2, + 1207 => Opcode::PseudoSF_VQMACC_2x8x2_M4, + 1208 => Opcode::PseudoSF_VQMACC_2x8x2_M8, + 1209 => Opcode::PseudoSF_VQMACC_4x8x4_M1, + 1210 => Opcode::PseudoSF_VQMACC_4x8x4_M2, + 1211 => Opcode::PseudoSF_VQMACC_4x8x4_M4, + 1212 => Opcode::PseudoSF_VQMACC_4x8x4_MF2, + 1213 => Opcode::PseudoSF_VSETTK, + 1214 => Opcode::PseudoSF_VSETTM, + 1215 => Opcode::PseudoSF_VSETTNT, + 1216 => Opcode::PseudoSF_VSETTNTX0, + 1217 => Opcode::PseudoSF_VSETTNTX0X0, + 1218 => Opcode::PseudoSF_VSTE16, + 1219 => Opcode::PseudoSF_VSTE32, + 1220 => Opcode::PseudoSF_VSTE64, + 1221 => Opcode::PseudoSF_VSTE8, + 1222 => Opcode::PseudoSF_VTDISCARD, + 1223 => Opcode::PseudoSF_VTMV_T_V, + 1224 => Opcode::PseudoSF_VTMV_V_T, + 1225 => Opcode::PseudoSF_VTZERO_T, + 1226 => Opcode::PseudoSH, + 1227 => Opcode::PseudoSW, + 1228 => Opcode::PseudoTAIL, + 1229 => Opcode::PseudoTAILIndirect, + 1230 => Opcode::PseudoTAILIndirectNonX7, + 1231 => Opcode::PseudoTAILIndirectX7, + 1232 => Opcode::PseudoTH_VMAQASU_VV_M1, + 1233 => Opcode::PseudoTH_VMAQASU_VV_M1_MASK, + 1234 => Opcode::PseudoTH_VMAQASU_VV_M2, + 1235 => Opcode::PseudoTH_VMAQASU_VV_M2_MASK, + 1236 => Opcode::PseudoTH_VMAQASU_VV_M4, + 1237 => Opcode::PseudoTH_VMAQASU_VV_M4_MASK, + 1238 => Opcode::PseudoTH_VMAQASU_VV_M8, + 1239 => Opcode::PseudoTH_VMAQASU_VV_M8_MASK, + 1240 => Opcode::PseudoTH_VMAQASU_VV_MF2, + 1241 => Opcode::PseudoTH_VMAQASU_VV_MF2_MASK, + 1242 => Opcode::PseudoTH_VMAQASU_VX_M1, + 1243 => Opcode::PseudoTH_VMAQASU_VX_M1_MASK, + 1244 => Opcode::PseudoTH_VMAQASU_VX_M2, + 1245 => Opcode::PseudoTH_VMAQASU_VX_M2_MASK, + 1246 => Opcode::PseudoTH_VMAQASU_VX_M4, + 1247 => Opcode::PseudoTH_VMAQASU_VX_M4_MASK, + 1248 => Opcode::PseudoTH_VMAQASU_VX_M8, + 1249 => Opcode::PseudoTH_VMAQASU_VX_M8_MASK, + 1250 => Opcode::PseudoTH_VMAQASU_VX_MF2, + 1251 => Opcode::PseudoTH_VMAQASU_VX_MF2_MASK, + 1252 => Opcode::PseudoTH_VMAQAUS_VX_M1, + 1253 => Opcode::PseudoTH_VMAQAUS_VX_M1_MASK, + 1254 => Opcode::PseudoTH_VMAQAUS_VX_M2, + 1255 => Opcode::PseudoTH_VMAQAUS_VX_M2_MASK, + 1256 => Opcode::PseudoTH_VMAQAUS_VX_M4, + 1257 => Opcode::PseudoTH_VMAQAUS_VX_M4_MASK, + 1258 => Opcode::PseudoTH_VMAQAUS_VX_M8, + 1259 => Opcode::PseudoTH_VMAQAUS_VX_M8_MASK, + 1260 => Opcode::PseudoTH_VMAQAUS_VX_MF2, + 1261 => Opcode::PseudoTH_VMAQAUS_VX_MF2_MASK, + 1262 => Opcode::PseudoTH_VMAQAU_VV_M1, + 1263 => Opcode::PseudoTH_VMAQAU_VV_M1_MASK, + 1264 => Opcode::PseudoTH_VMAQAU_VV_M2, + 1265 => Opcode::PseudoTH_VMAQAU_VV_M2_MASK, + 1266 => Opcode::PseudoTH_VMAQAU_VV_M4, + 1267 => Opcode::PseudoTH_VMAQAU_VV_M4_MASK, + 1268 => Opcode::PseudoTH_VMAQAU_VV_M8, + 1269 => Opcode::PseudoTH_VMAQAU_VV_M8_MASK, + 1270 => Opcode::PseudoTH_VMAQAU_VV_MF2, + 1271 => Opcode::PseudoTH_VMAQAU_VV_MF2_MASK, + 1272 => Opcode::PseudoTH_VMAQAU_VX_M1, + 1273 => Opcode::PseudoTH_VMAQAU_VX_M1_MASK, + 1274 => Opcode::PseudoTH_VMAQAU_VX_M2, + 1275 => Opcode::PseudoTH_VMAQAU_VX_M2_MASK, + 1276 => Opcode::PseudoTH_VMAQAU_VX_M4, + 1277 => Opcode::PseudoTH_VMAQAU_VX_M4_MASK, + 1278 => Opcode::PseudoTH_VMAQAU_VX_M8, + 1279 => Opcode::PseudoTH_VMAQAU_VX_M8_MASK, + 1280 => Opcode::PseudoTH_VMAQAU_VX_MF2, + 1281 => Opcode::PseudoTH_VMAQAU_VX_MF2_MASK, + 1282 => Opcode::PseudoTH_VMAQA_VV_M1, + 1283 => Opcode::PseudoTH_VMAQA_VV_M1_MASK, + 1284 => Opcode::PseudoTH_VMAQA_VV_M2, + 1285 => Opcode::PseudoTH_VMAQA_VV_M2_MASK, + 1286 => Opcode::PseudoTH_VMAQA_VV_M4, + 1287 => Opcode::PseudoTH_VMAQA_VV_M4_MASK, + 1288 => Opcode::PseudoTH_VMAQA_VV_M8, + 1289 => Opcode::PseudoTH_VMAQA_VV_M8_MASK, + 1290 => Opcode::PseudoTH_VMAQA_VV_MF2, + 1291 => Opcode::PseudoTH_VMAQA_VV_MF2_MASK, + 1292 => Opcode::PseudoTH_VMAQA_VX_M1, + 1293 => Opcode::PseudoTH_VMAQA_VX_M1_MASK, + 1294 => Opcode::PseudoTH_VMAQA_VX_M2, + 1295 => Opcode::PseudoTH_VMAQA_VX_M2_MASK, + 1296 => Opcode::PseudoTH_VMAQA_VX_M4, + 1297 => Opcode::PseudoTH_VMAQA_VX_M4_MASK, + 1298 => Opcode::PseudoTH_VMAQA_VX_M8, + 1299 => Opcode::PseudoTH_VMAQA_VX_M8_MASK, + 1300 => Opcode::PseudoTH_VMAQA_VX_MF2, + 1301 => Opcode::PseudoTH_VMAQA_VX_MF2_MASK, + 1302 => Opcode::PseudoTLSDESCCall, + 1303 => Opcode::PseudoVAADDU_VV_M1, + 1304 => Opcode::PseudoVAADDU_VV_M1_MASK, + 1305 => Opcode::PseudoVAADDU_VV_M2, + 1306 => Opcode::PseudoVAADDU_VV_M2_MASK, + 1307 => Opcode::PseudoVAADDU_VV_M4, + 1308 => Opcode::PseudoVAADDU_VV_M4_MASK, + 1309 => Opcode::PseudoVAADDU_VV_M8, + 1310 => Opcode::PseudoVAADDU_VV_M8_MASK, + 1311 => Opcode::PseudoVAADDU_VV_MF2, + 1312 => Opcode::PseudoVAADDU_VV_MF2_MASK, + 1313 => Opcode::PseudoVAADDU_VV_MF4, + 1314 => Opcode::PseudoVAADDU_VV_MF4_MASK, + 1315 => Opcode::PseudoVAADDU_VV_MF8, + 1316 => Opcode::PseudoVAADDU_VV_MF8_MASK, + 1317 => Opcode::PseudoVAADDU_VX_M1, + 1318 => Opcode::PseudoVAADDU_VX_M1_MASK, + 1319 => Opcode::PseudoVAADDU_VX_M2, + 1320 => Opcode::PseudoVAADDU_VX_M2_MASK, + 1321 => Opcode::PseudoVAADDU_VX_M4, + 1322 => Opcode::PseudoVAADDU_VX_M4_MASK, + 1323 => Opcode::PseudoVAADDU_VX_M8, + 1324 => Opcode::PseudoVAADDU_VX_M8_MASK, + 1325 => Opcode::PseudoVAADDU_VX_MF2, + 1326 => Opcode::PseudoVAADDU_VX_MF2_MASK, + 1327 => Opcode::PseudoVAADDU_VX_MF4, + 1328 => Opcode::PseudoVAADDU_VX_MF4_MASK, + 1329 => Opcode::PseudoVAADDU_VX_MF8, + 1330 => Opcode::PseudoVAADDU_VX_MF8_MASK, + 1331 => Opcode::PseudoVAADD_VV_M1, + 1332 => Opcode::PseudoVAADD_VV_M1_MASK, + 1333 => Opcode::PseudoVAADD_VV_M2, + 1334 => Opcode::PseudoVAADD_VV_M2_MASK, + 1335 => Opcode::PseudoVAADD_VV_M4, + 1336 => Opcode::PseudoVAADD_VV_M4_MASK, + 1337 => Opcode::PseudoVAADD_VV_M8, + 1338 => Opcode::PseudoVAADD_VV_M8_MASK, + 1339 => Opcode::PseudoVAADD_VV_MF2, + 1340 => Opcode::PseudoVAADD_VV_MF2_MASK, + 1341 => Opcode::PseudoVAADD_VV_MF4, + 1342 => Opcode::PseudoVAADD_VV_MF4_MASK, + 1343 => Opcode::PseudoVAADD_VV_MF8, + 1344 => Opcode::PseudoVAADD_VV_MF8_MASK, + 1345 => Opcode::PseudoVAADD_VX_M1, + 1346 => Opcode::PseudoVAADD_VX_M1_MASK, + 1347 => Opcode::PseudoVAADD_VX_M2, + 1348 => Opcode::PseudoVAADD_VX_M2_MASK, + 1349 => Opcode::PseudoVAADD_VX_M4, + 1350 => Opcode::PseudoVAADD_VX_M4_MASK, + 1351 => Opcode::PseudoVAADD_VX_M8, + 1352 => Opcode::PseudoVAADD_VX_M8_MASK, + 1353 => Opcode::PseudoVAADD_VX_MF2, + 1354 => Opcode::PseudoVAADD_VX_MF2_MASK, + 1355 => Opcode::PseudoVAADD_VX_MF4, + 1356 => Opcode::PseudoVAADD_VX_MF4_MASK, + 1357 => Opcode::PseudoVAADD_VX_MF8, + 1358 => Opcode::PseudoVAADD_VX_MF8_MASK, + 1359 => Opcode::PseudoVADC_VIM_M1, + 1360 => Opcode::PseudoVADC_VIM_M2, + 1361 => Opcode::PseudoVADC_VIM_M4, + 1362 => Opcode::PseudoVADC_VIM_M8, + 1363 => Opcode::PseudoVADC_VIM_MF2, + 1364 => Opcode::PseudoVADC_VIM_MF4, + 1365 => Opcode::PseudoVADC_VIM_MF8, + 1366 => Opcode::PseudoVADC_VVM_M1, + 1367 => Opcode::PseudoVADC_VVM_M2, + 1368 => Opcode::PseudoVADC_VVM_M4, + 1369 => Opcode::PseudoVADC_VVM_M8, + 1370 => Opcode::PseudoVADC_VVM_MF2, + 1371 => Opcode::PseudoVADC_VVM_MF4, + 1372 => Opcode::PseudoVADC_VVM_MF8, + 1373 => Opcode::PseudoVADC_VXM_M1, + 1374 => Opcode::PseudoVADC_VXM_M2, + 1375 => Opcode::PseudoVADC_VXM_M4, + 1376 => Opcode::PseudoVADC_VXM_M8, + 1377 => Opcode::PseudoVADC_VXM_MF2, + 1378 => Opcode::PseudoVADC_VXM_MF4, + 1379 => Opcode::PseudoVADC_VXM_MF8, + 1380 => Opcode::PseudoVADD_VI_M1, + 1381 => Opcode::PseudoVADD_VI_M1_MASK, + 1382 => Opcode::PseudoVADD_VI_M2, + 1383 => Opcode::PseudoVADD_VI_M2_MASK, + 1384 => Opcode::PseudoVADD_VI_M4, + 1385 => Opcode::PseudoVADD_VI_M4_MASK, + 1386 => Opcode::PseudoVADD_VI_M8, + 1387 => Opcode::PseudoVADD_VI_M8_MASK, + 1388 => Opcode::PseudoVADD_VI_MF2, + 1389 => Opcode::PseudoVADD_VI_MF2_MASK, + 1390 => Opcode::PseudoVADD_VI_MF4, + 1391 => Opcode::PseudoVADD_VI_MF4_MASK, + 1392 => Opcode::PseudoVADD_VI_MF8, + 1393 => Opcode::PseudoVADD_VI_MF8_MASK, + 1394 => Opcode::PseudoVADD_VV_M1, + 1395 => Opcode::PseudoVADD_VV_M1_MASK, + 1396 => Opcode::PseudoVADD_VV_M2, + 1397 => Opcode::PseudoVADD_VV_M2_MASK, + 1398 => Opcode::PseudoVADD_VV_M4, + 1399 => Opcode::PseudoVADD_VV_M4_MASK, + 1400 => Opcode::PseudoVADD_VV_M8, + 1401 => Opcode::PseudoVADD_VV_M8_MASK, + 1402 => Opcode::PseudoVADD_VV_MF2, + 1403 => Opcode::PseudoVADD_VV_MF2_MASK, + 1404 => Opcode::PseudoVADD_VV_MF4, + 1405 => Opcode::PseudoVADD_VV_MF4_MASK, + 1406 => Opcode::PseudoVADD_VV_MF8, + 1407 => Opcode::PseudoVADD_VV_MF8_MASK, + 1408 => Opcode::PseudoVADD_VX_M1, + 1409 => Opcode::PseudoVADD_VX_M1_MASK, + 1410 => Opcode::PseudoVADD_VX_M2, + 1411 => Opcode::PseudoVADD_VX_M2_MASK, + 1412 => Opcode::PseudoVADD_VX_M4, + 1413 => Opcode::PseudoVADD_VX_M4_MASK, + 1414 => Opcode::PseudoVADD_VX_M8, + 1415 => Opcode::PseudoVADD_VX_M8_MASK, + 1416 => Opcode::PseudoVADD_VX_MF2, + 1417 => Opcode::PseudoVADD_VX_MF2_MASK, + 1418 => Opcode::PseudoVADD_VX_MF4, + 1419 => Opcode::PseudoVADD_VX_MF4_MASK, + 1420 => Opcode::PseudoVADD_VX_MF8, + 1421 => Opcode::PseudoVADD_VX_MF8_MASK, + 1422 => Opcode::PseudoVAESDF_VS_M1_M1, + 1423 => Opcode::PseudoVAESDF_VS_M1_MF2, + 1424 => Opcode::PseudoVAESDF_VS_M1_MF4, + 1425 => Opcode::PseudoVAESDF_VS_M1_MF8, + 1426 => Opcode::PseudoVAESDF_VS_M2_M1, + 1427 => Opcode::PseudoVAESDF_VS_M2_M2, + 1428 => Opcode::PseudoVAESDF_VS_M2_MF2, + 1429 => Opcode::PseudoVAESDF_VS_M2_MF4, + 1430 => Opcode::PseudoVAESDF_VS_M2_MF8, + 1431 => Opcode::PseudoVAESDF_VS_M4_M1, + 1432 => Opcode::PseudoVAESDF_VS_M4_M2, + 1433 => Opcode::PseudoVAESDF_VS_M4_M4, + 1434 => Opcode::PseudoVAESDF_VS_M4_MF2, + 1435 => Opcode::PseudoVAESDF_VS_M4_MF4, + 1436 => Opcode::PseudoVAESDF_VS_M4_MF8, + 1437 => Opcode::PseudoVAESDF_VS_M8_M1, + 1438 => Opcode::PseudoVAESDF_VS_M8_M2, + 1439 => Opcode::PseudoVAESDF_VS_M8_M4, + 1440 => Opcode::PseudoVAESDF_VS_M8_MF2, + 1441 => Opcode::PseudoVAESDF_VS_M8_MF4, + 1442 => Opcode::PseudoVAESDF_VS_M8_MF8, + 1443 => Opcode::PseudoVAESDF_VS_MF2_MF2, + 1444 => Opcode::PseudoVAESDF_VS_MF2_MF4, + 1445 => Opcode::PseudoVAESDF_VS_MF2_MF8, + 1446 => Opcode::PseudoVAESDF_VV_M1, + 1447 => Opcode::PseudoVAESDF_VV_M2, + 1448 => Opcode::PseudoVAESDF_VV_M4, + 1449 => Opcode::PseudoVAESDF_VV_M8, + 1450 => Opcode::PseudoVAESDF_VV_MF2, + 1451 => Opcode::PseudoVAESDM_VS_M1_M1, + 1452 => Opcode::PseudoVAESDM_VS_M1_MF2, + 1453 => Opcode::PseudoVAESDM_VS_M1_MF4, + 1454 => Opcode::PseudoVAESDM_VS_M1_MF8, + 1455 => Opcode::PseudoVAESDM_VS_M2_M1, + 1456 => Opcode::PseudoVAESDM_VS_M2_M2, + 1457 => Opcode::PseudoVAESDM_VS_M2_MF2, + 1458 => Opcode::PseudoVAESDM_VS_M2_MF4, + 1459 => Opcode::PseudoVAESDM_VS_M2_MF8, + 1460 => Opcode::PseudoVAESDM_VS_M4_M1, + 1461 => Opcode::PseudoVAESDM_VS_M4_M2, + 1462 => Opcode::PseudoVAESDM_VS_M4_M4, + 1463 => Opcode::PseudoVAESDM_VS_M4_MF2, + 1464 => Opcode::PseudoVAESDM_VS_M4_MF4, + 1465 => Opcode::PseudoVAESDM_VS_M4_MF8, + 1466 => Opcode::PseudoVAESDM_VS_M8_M1, + 1467 => Opcode::PseudoVAESDM_VS_M8_M2, + 1468 => Opcode::PseudoVAESDM_VS_M8_M4, + 1469 => Opcode::PseudoVAESDM_VS_M8_MF2, + 1470 => Opcode::PseudoVAESDM_VS_M8_MF4, + 1471 => Opcode::PseudoVAESDM_VS_M8_MF8, + 1472 => Opcode::PseudoVAESDM_VS_MF2_MF2, + 1473 => Opcode::PseudoVAESDM_VS_MF2_MF4, + 1474 => Opcode::PseudoVAESDM_VS_MF2_MF8, + 1475 => Opcode::PseudoVAESDM_VV_M1, + 1476 => Opcode::PseudoVAESDM_VV_M2, + 1477 => Opcode::PseudoVAESDM_VV_M4, + 1478 => Opcode::PseudoVAESDM_VV_M8, + 1479 => Opcode::PseudoVAESDM_VV_MF2, + 1480 => Opcode::PseudoVAESEF_VS_M1_M1, + 1481 => Opcode::PseudoVAESEF_VS_M1_MF2, + 1482 => Opcode::PseudoVAESEF_VS_M1_MF4, + 1483 => Opcode::PseudoVAESEF_VS_M1_MF8, + 1484 => Opcode::PseudoVAESEF_VS_M2_M1, + 1485 => Opcode::PseudoVAESEF_VS_M2_M2, + 1486 => Opcode::PseudoVAESEF_VS_M2_MF2, + 1487 => Opcode::PseudoVAESEF_VS_M2_MF4, + 1488 => Opcode::PseudoVAESEF_VS_M2_MF8, + 1489 => Opcode::PseudoVAESEF_VS_M4_M1, + 1490 => Opcode::PseudoVAESEF_VS_M4_M2, + 1491 => Opcode::PseudoVAESEF_VS_M4_M4, + 1492 => Opcode::PseudoVAESEF_VS_M4_MF2, + 1493 => Opcode::PseudoVAESEF_VS_M4_MF4, + 1494 => Opcode::PseudoVAESEF_VS_M4_MF8, + 1495 => Opcode::PseudoVAESEF_VS_M8_M1, + 1496 => Opcode::PseudoVAESEF_VS_M8_M2, + 1497 => Opcode::PseudoVAESEF_VS_M8_M4, + 1498 => Opcode::PseudoVAESEF_VS_M8_MF2, + 1499 => Opcode::PseudoVAESEF_VS_M8_MF4, + 1500 => Opcode::PseudoVAESEF_VS_M8_MF8, + 1501 => Opcode::PseudoVAESEF_VS_MF2_MF2, + 1502 => Opcode::PseudoVAESEF_VS_MF2_MF4, + 1503 => Opcode::PseudoVAESEF_VS_MF2_MF8, + 1504 => Opcode::PseudoVAESEF_VV_M1, + 1505 => Opcode::PseudoVAESEF_VV_M2, + 1506 => Opcode::PseudoVAESEF_VV_M4, + 1507 => Opcode::PseudoVAESEF_VV_M8, + 1508 => Opcode::PseudoVAESEF_VV_MF2, + 1509 => Opcode::PseudoVAESEM_VS_M1_M1, + 1510 => Opcode::PseudoVAESEM_VS_M1_MF2, + 1511 => Opcode::PseudoVAESEM_VS_M1_MF4, + 1512 => Opcode::PseudoVAESEM_VS_M1_MF8, + 1513 => Opcode::PseudoVAESEM_VS_M2_M1, + 1514 => Opcode::PseudoVAESEM_VS_M2_M2, + 1515 => Opcode::PseudoVAESEM_VS_M2_MF2, + 1516 => Opcode::PseudoVAESEM_VS_M2_MF4, + 1517 => Opcode::PseudoVAESEM_VS_M2_MF8, + 1518 => Opcode::PseudoVAESEM_VS_M4_M1, + 1519 => Opcode::PseudoVAESEM_VS_M4_M2, + 1520 => Opcode::PseudoVAESEM_VS_M4_M4, + 1521 => Opcode::PseudoVAESEM_VS_M4_MF2, + 1522 => Opcode::PseudoVAESEM_VS_M4_MF4, + 1523 => Opcode::PseudoVAESEM_VS_M4_MF8, + 1524 => Opcode::PseudoVAESEM_VS_M8_M1, + 1525 => Opcode::PseudoVAESEM_VS_M8_M2, + 1526 => Opcode::PseudoVAESEM_VS_M8_M4, + 1527 => Opcode::PseudoVAESEM_VS_M8_MF2, + 1528 => Opcode::PseudoVAESEM_VS_M8_MF4, + 1529 => Opcode::PseudoVAESEM_VS_M8_MF8, + 1530 => Opcode::PseudoVAESEM_VS_MF2_MF2, + 1531 => Opcode::PseudoVAESEM_VS_MF2_MF4, + 1532 => Opcode::PseudoVAESEM_VS_MF2_MF8, + 1533 => Opcode::PseudoVAESEM_VV_M1, + 1534 => Opcode::PseudoVAESEM_VV_M2, + 1535 => Opcode::PseudoVAESEM_VV_M4, + 1536 => Opcode::PseudoVAESEM_VV_M8, + 1537 => Opcode::PseudoVAESEM_VV_MF2, + 1538 => Opcode::PseudoVAESKF1_VI_M1, + 1539 => Opcode::PseudoVAESKF1_VI_M2, + 1540 => Opcode::PseudoVAESKF1_VI_M4, + 1541 => Opcode::PseudoVAESKF1_VI_M8, + 1542 => Opcode::PseudoVAESKF1_VI_MF2, + 1543 => Opcode::PseudoVAESKF2_VI_M1, + 1544 => Opcode::PseudoVAESKF2_VI_M2, + 1545 => Opcode::PseudoVAESKF2_VI_M4, + 1546 => Opcode::PseudoVAESKF2_VI_M8, + 1547 => Opcode::PseudoVAESKF2_VI_MF2, + 1548 => Opcode::PseudoVAESZ_VS_M1_M1, + 1549 => Opcode::PseudoVAESZ_VS_M1_MF2, + 1550 => Opcode::PseudoVAESZ_VS_M1_MF4, + 1551 => Opcode::PseudoVAESZ_VS_M1_MF8, + 1552 => Opcode::PseudoVAESZ_VS_M2_M1, + 1553 => Opcode::PseudoVAESZ_VS_M2_M2, + 1554 => Opcode::PseudoVAESZ_VS_M2_MF2, + 1555 => Opcode::PseudoVAESZ_VS_M2_MF4, + 1556 => Opcode::PseudoVAESZ_VS_M2_MF8, + 1557 => Opcode::PseudoVAESZ_VS_M4_M1, + 1558 => Opcode::PseudoVAESZ_VS_M4_M2, + 1559 => Opcode::PseudoVAESZ_VS_M4_M4, + 1560 => Opcode::PseudoVAESZ_VS_M4_MF2, + 1561 => Opcode::PseudoVAESZ_VS_M4_MF4, + 1562 => Opcode::PseudoVAESZ_VS_M4_MF8, + 1563 => Opcode::PseudoVAESZ_VS_M8_M1, + 1564 => Opcode::PseudoVAESZ_VS_M8_M2, + 1565 => Opcode::PseudoVAESZ_VS_M8_M4, + 1566 => Opcode::PseudoVAESZ_VS_M8_MF2, + 1567 => Opcode::PseudoVAESZ_VS_M8_MF4, + 1568 => Opcode::PseudoVAESZ_VS_M8_MF8, + 1569 => Opcode::PseudoVAESZ_VS_MF2_MF2, + 1570 => Opcode::PseudoVAESZ_VS_MF2_MF4, + 1571 => Opcode::PseudoVAESZ_VS_MF2_MF8, + 1572 => Opcode::PseudoVANDN_VV_M1, + 1573 => Opcode::PseudoVANDN_VV_M1_MASK, + 1574 => Opcode::PseudoVANDN_VV_M2, + 1575 => Opcode::PseudoVANDN_VV_M2_MASK, + 1576 => Opcode::PseudoVANDN_VV_M4, + 1577 => Opcode::PseudoVANDN_VV_M4_MASK, + 1578 => Opcode::PseudoVANDN_VV_M8, + 1579 => Opcode::PseudoVANDN_VV_M8_MASK, + 1580 => Opcode::PseudoVANDN_VV_MF2, + 1581 => Opcode::PseudoVANDN_VV_MF2_MASK, + 1582 => Opcode::PseudoVANDN_VV_MF4, + 1583 => Opcode::PseudoVANDN_VV_MF4_MASK, + 1584 => Opcode::PseudoVANDN_VV_MF8, + 1585 => Opcode::PseudoVANDN_VV_MF8_MASK, + 1586 => Opcode::PseudoVANDN_VX_M1, + 1587 => Opcode::PseudoVANDN_VX_M1_MASK, + 1588 => Opcode::PseudoVANDN_VX_M2, + 1589 => Opcode::PseudoVANDN_VX_M2_MASK, + 1590 => Opcode::PseudoVANDN_VX_M4, + 1591 => Opcode::PseudoVANDN_VX_M4_MASK, + 1592 => Opcode::PseudoVANDN_VX_M8, + 1593 => Opcode::PseudoVANDN_VX_M8_MASK, + 1594 => Opcode::PseudoVANDN_VX_MF2, + 1595 => Opcode::PseudoVANDN_VX_MF2_MASK, + 1596 => Opcode::PseudoVANDN_VX_MF4, + 1597 => Opcode::PseudoVANDN_VX_MF4_MASK, + 1598 => Opcode::PseudoVANDN_VX_MF8, + 1599 => Opcode::PseudoVANDN_VX_MF8_MASK, + 1600 => Opcode::PseudoVAND_VI_M1, + 1601 => Opcode::PseudoVAND_VI_M1_MASK, + 1602 => Opcode::PseudoVAND_VI_M2, + 1603 => Opcode::PseudoVAND_VI_M2_MASK, + 1604 => Opcode::PseudoVAND_VI_M4, + 1605 => Opcode::PseudoVAND_VI_M4_MASK, + 1606 => Opcode::PseudoVAND_VI_M8, + 1607 => Opcode::PseudoVAND_VI_M8_MASK, + 1608 => Opcode::PseudoVAND_VI_MF2, + 1609 => Opcode::PseudoVAND_VI_MF2_MASK, + 1610 => Opcode::PseudoVAND_VI_MF4, + 1611 => Opcode::PseudoVAND_VI_MF4_MASK, + 1612 => Opcode::PseudoVAND_VI_MF8, + 1613 => Opcode::PseudoVAND_VI_MF8_MASK, + 1614 => Opcode::PseudoVAND_VV_M1, + 1615 => Opcode::PseudoVAND_VV_M1_MASK, + 1616 => Opcode::PseudoVAND_VV_M2, + 1617 => Opcode::PseudoVAND_VV_M2_MASK, + 1618 => Opcode::PseudoVAND_VV_M4, + 1619 => Opcode::PseudoVAND_VV_M4_MASK, + 1620 => Opcode::PseudoVAND_VV_M8, + 1621 => Opcode::PseudoVAND_VV_M8_MASK, + 1622 => Opcode::PseudoVAND_VV_MF2, + 1623 => Opcode::PseudoVAND_VV_MF2_MASK, + 1624 => Opcode::PseudoVAND_VV_MF4, + 1625 => Opcode::PseudoVAND_VV_MF4_MASK, + 1626 => Opcode::PseudoVAND_VV_MF8, + 1627 => Opcode::PseudoVAND_VV_MF8_MASK, + 1628 => Opcode::PseudoVAND_VX_M1, + 1629 => Opcode::PseudoVAND_VX_M1_MASK, + 1630 => Opcode::PseudoVAND_VX_M2, + 1631 => Opcode::PseudoVAND_VX_M2_MASK, + 1632 => Opcode::PseudoVAND_VX_M4, + 1633 => Opcode::PseudoVAND_VX_M4_MASK, + 1634 => Opcode::PseudoVAND_VX_M8, + 1635 => Opcode::PseudoVAND_VX_M8_MASK, + 1636 => Opcode::PseudoVAND_VX_MF2, + 1637 => Opcode::PseudoVAND_VX_MF2_MASK, + 1638 => Opcode::PseudoVAND_VX_MF4, + 1639 => Opcode::PseudoVAND_VX_MF4_MASK, + 1640 => Opcode::PseudoVAND_VX_MF8, + 1641 => Opcode::PseudoVAND_VX_MF8_MASK, + 1642 => Opcode::PseudoVASUBU_VV_M1, + 1643 => Opcode::PseudoVASUBU_VV_M1_MASK, + 1644 => Opcode::PseudoVASUBU_VV_M2, + 1645 => Opcode::PseudoVASUBU_VV_M2_MASK, + 1646 => Opcode::PseudoVASUBU_VV_M4, + 1647 => Opcode::PseudoVASUBU_VV_M4_MASK, + 1648 => Opcode::PseudoVASUBU_VV_M8, + 1649 => Opcode::PseudoVASUBU_VV_M8_MASK, + 1650 => Opcode::PseudoVASUBU_VV_MF2, + 1651 => Opcode::PseudoVASUBU_VV_MF2_MASK, + 1652 => Opcode::PseudoVASUBU_VV_MF4, + 1653 => Opcode::PseudoVASUBU_VV_MF4_MASK, + 1654 => Opcode::PseudoVASUBU_VV_MF8, + 1655 => Opcode::PseudoVASUBU_VV_MF8_MASK, + 1656 => Opcode::PseudoVASUBU_VX_M1, + 1657 => Opcode::PseudoVASUBU_VX_M1_MASK, + 1658 => Opcode::PseudoVASUBU_VX_M2, + 1659 => Opcode::PseudoVASUBU_VX_M2_MASK, + 1660 => Opcode::PseudoVASUBU_VX_M4, + 1661 => Opcode::PseudoVASUBU_VX_M4_MASK, + 1662 => Opcode::PseudoVASUBU_VX_M8, + 1663 => Opcode::PseudoVASUBU_VX_M8_MASK, + 1664 => Opcode::PseudoVASUBU_VX_MF2, + 1665 => Opcode::PseudoVASUBU_VX_MF2_MASK, + 1666 => Opcode::PseudoVASUBU_VX_MF4, + 1667 => Opcode::PseudoVASUBU_VX_MF4_MASK, + 1668 => Opcode::PseudoVASUBU_VX_MF8, + 1669 => Opcode::PseudoVASUBU_VX_MF8_MASK, + 1670 => Opcode::PseudoVASUB_VV_M1, + 1671 => Opcode::PseudoVASUB_VV_M1_MASK, + 1672 => Opcode::PseudoVASUB_VV_M2, + 1673 => Opcode::PseudoVASUB_VV_M2_MASK, + 1674 => Opcode::PseudoVASUB_VV_M4, + 1675 => Opcode::PseudoVASUB_VV_M4_MASK, + 1676 => Opcode::PseudoVASUB_VV_M8, + 1677 => Opcode::PseudoVASUB_VV_M8_MASK, + 1678 => Opcode::PseudoVASUB_VV_MF2, + 1679 => Opcode::PseudoVASUB_VV_MF2_MASK, + 1680 => Opcode::PseudoVASUB_VV_MF4, + 1681 => Opcode::PseudoVASUB_VV_MF4_MASK, + 1682 => Opcode::PseudoVASUB_VV_MF8, + 1683 => Opcode::PseudoVASUB_VV_MF8_MASK, + 1684 => Opcode::PseudoVASUB_VX_M1, + 1685 => Opcode::PseudoVASUB_VX_M1_MASK, + 1686 => Opcode::PseudoVASUB_VX_M2, + 1687 => Opcode::PseudoVASUB_VX_M2_MASK, + 1688 => Opcode::PseudoVASUB_VX_M4, + 1689 => Opcode::PseudoVASUB_VX_M4_MASK, + 1690 => Opcode::PseudoVASUB_VX_M8, + 1691 => Opcode::PseudoVASUB_VX_M8_MASK, + 1692 => Opcode::PseudoVASUB_VX_MF2, + 1693 => Opcode::PseudoVASUB_VX_MF2_MASK, + 1694 => Opcode::PseudoVASUB_VX_MF4, + 1695 => Opcode::PseudoVASUB_VX_MF4_MASK, + 1696 => Opcode::PseudoVASUB_VX_MF8, + 1697 => Opcode::PseudoVASUB_VX_MF8_MASK, + 1698 => Opcode::PseudoVBREV8_V_M1, + 1699 => Opcode::PseudoVBREV8_V_M1_MASK, + 1700 => Opcode::PseudoVBREV8_V_M2, + 1701 => Opcode::PseudoVBREV8_V_M2_MASK, + 1702 => Opcode::PseudoVBREV8_V_M4, + 1703 => Opcode::PseudoVBREV8_V_M4_MASK, + 1704 => Opcode::PseudoVBREV8_V_M8, + 1705 => Opcode::PseudoVBREV8_V_M8_MASK, + 1706 => Opcode::PseudoVBREV8_V_MF2, + 1707 => Opcode::PseudoVBREV8_V_MF2_MASK, + 1708 => Opcode::PseudoVBREV8_V_MF4, + 1709 => Opcode::PseudoVBREV8_V_MF4_MASK, + 1710 => Opcode::PseudoVBREV8_V_MF8, + 1711 => Opcode::PseudoVBREV8_V_MF8_MASK, + 1712 => Opcode::PseudoVBREV_V_M1, + 1713 => Opcode::PseudoVBREV_V_M1_MASK, + 1714 => Opcode::PseudoVBREV_V_M2, + 1715 => Opcode::PseudoVBREV_V_M2_MASK, + 1716 => Opcode::PseudoVBREV_V_M4, + 1717 => Opcode::PseudoVBREV_V_M4_MASK, + 1718 => Opcode::PseudoVBREV_V_M8, + 1719 => Opcode::PseudoVBREV_V_M8_MASK, + 1720 => Opcode::PseudoVBREV_V_MF2, + 1721 => Opcode::PseudoVBREV_V_MF2_MASK, + 1722 => Opcode::PseudoVBREV_V_MF4, + 1723 => Opcode::PseudoVBREV_V_MF4_MASK, + 1724 => Opcode::PseudoVBREV_V_MF8, + 1725 => Opcode::PseudoVBREV_V_MF8_MASK, + 1726 => Opcode::PseudoVCLMULH_VV_M1, + 1727 => Opcode::PseudoVCLMULH_VV_M1_MASK, + 1728 => Opcode::PseudoVCLMULH_VV_M2, + 1729 => Opcode::PseudoVCLMULH_VV_M2_MASK, + 1730 => Opcode::PseudoVCLMULH_VV_M4, + 1731 => Opcode::PseudoVCLMULH_VV_M4_MASK, + 1732 => Opcode::PseudoVCLMULH_VV_M8, + 1733 => Opcode::PseudoVCLMULH_VV_M8_MASK, + 1734 => Opcode::PseudoVCLMULH_VV_MF2, + 1735 => Opcode::PseudoVCLMULH_VV_MF2_MASK, + 1736 => Opcode::PseudoVCLMULH_VV_MF4, + 1737 => Opcode::PseudoVCLMULH_VV_MF4_MASK, + 1738 => Opcode::PseudoVCLMULH_VV_MF8, + 1739 => Opcode::PseudoVCLMULH_VV_MF8_MASK, + 1740 => Opcode::PseudoVCLMULH_VX_M1, + 1741 => Opcode::PseudoVCLMULH_VX_M1_MASK, + 1742 => Opcode::PseudoVCLMULH_VX_M2, + 1743 => Opcode::PseudoVCLMULH_VX_M2_MASK, + 1744 => Opcode::PseudoVCLMULH_VX_M4, + 1745 => Opcode::PseudoVCLMULH_VX_M4_MASK, + 1746 => Opcode::PseudoVCLMULH_VX_M8, + 1747 => Opcode::PseudoVCLMULH_VX_M8_MASK, + 1748 => Opcode::PseudoVCLMULH_VX_MF2, + 1749 => Opcode::PseudoVCLMULH_VX_MF2_MASK, + 1750 => Opcode::PseudoVCLMULH_VX_MF4, + 1751 => Opcode::PseudoVCLMULH_VX_MF4_MASK, + 1752 => Opcode::PseudoVCLMULH_VX_MF8, + 1753 => Opcode::PseudoVCLMULH_VX_MF8_MASK, + 1754 => Opcode::PseudoVCLMUL_VV_M1, + 1755 => Opcode::PseudoVCLMUL_VV_M1_MASK, + 1756 => Opcode::PseudoVCLMUL_VV_M2, + 1757 => Opcode::PseudoVCLMUL_VV_M2_MASK, + 1758 => Opcode::PseudoVCLMUL_VV_M4, + 1759 => Opcode::PseudoVCLMUL_VV_M4_MASK, + 1760 => Opcode::PseudoVCLMUL_VV_M8, + 1761 => Opcode::PseudoVCLMUL_VV_M8_MASK, + 1762 => Opcode::PseudoVCLMUL_VV_MF2, + 1763 => Opcode::PseudoVCLMUL_VV_MF2_MASK, + 1764 => Opcode::PseudoVCLMUL_VV_MF4, + 1765 => Opcode::PseudoVCLMUL_VV_MF4_MASK, + 1766 => Opcode::PseudoVCLMUL_VV_MF8, + 1767 => Opcode::PseudoVCLMUL_VV_MF8_MASK, + 1768 => Opcode::PseudoVCLMUL_VX_M1, + 1769 => Opcode::PseudoVCLMUL_VX_M1_MASK, + 1770 => Opcode::PseudoVCLMUL_VX_M2, + 1771 => Opcode::PseudoVCLMUL_VX_M2_MASK, + 1772 => Opcode::PseudoVCLMUL_VX_M4, + 1773 => Opcode::PseudoVCLMUL_VX_M4_MASK, + 1774 => Opcode::PseudoVCLMUL_VX_M8, + 1775 => Opcode::PseudoVCLMUL_VX_M8_MASK, + 1776 => Opcode::PseudoVCLMUL_VX_MF2, + 1777 => Opcode::PseudoVCLMUL_VX_MF2_MASK, + 1778 => Opcode::PseudoVCLMUL_VX_MF4, + 1779 => Opcode::PseudoVCLMUL_VX_MF4_MASK, + 1780 => Opcode::PseudoVCLMUL_VX_MF8, + 1781 => Opcode::PseudoVCLMUL_VX_MF8_MASK, + 1782 => Opcode::PseudoVCLZ_V_M1, + 1783 => Opcode::PseudoVCLZ_V_M1_MASK, + 1784 => Opcode::PseudoVCLZ_V_M2, + 1785 => Opcode::PseudoVCLZ_V_M2_MASK, + 1786 => Opcode::PseudoVCLZ_V_M4, + 1787 => Opcode::PseudoVCLZ_V_M4_MASK, + 1788 => Opcode::PseudoVCLZ_V_M8, + 1789 => Opcode::PseudoVCLZ_V_M8_MASK, + 1790 => Opcode::PseudoVCLZ_V_MF2, + 1791 => Opcode::PseudoVCLZ_V_MF2_MASK, + 1792 => Opcode::PseudoVCLZ_V_MF4, + 1793 => Opcode::PseudoVCLZ_V_MF4_MASK, + 1794 => Opcode::PseudoVCLZ_V_MF8, + 1795 => Opcode::PseudoVCLZ_V_MF8_MASK, + 1796 => Opcode::PseudoVCOMPRESS_VM_M1_E16, + 1797 => Opcode::PseudoVCOMPRESS_VM_M1_E32, + 1798 => Opcode::PseudoVCOMPRESS_VM_M1_E64, + 1799 => Opcode::PseudoVCOMPRESS_VM_M1_E8, + 1800 => Opcode::PseudoVCOMPRESS_VM_M2_E16, + 1801 => Opcode::PseudoVCOMPRESS_VM_M2_E32, + 1802 => Opcode::PseudoVCOMPRESS_VM_M2_E64, + 1803 => Opcode::PseudoVCOMPRESS_VM_M2_E8, + 1804 => Opcode::PseudoVCOMPRESS_VM_M4_E16, + 1805 => Opcode::PseudoVCOMPRESS_VM_M4_E32, + 1806 => Opcode::PseudoVCOMPRESS_VM_M4_E64, + 1807 => Opcode::PseudoVCOMPRESS_VM_M4_E8, + 1808 => Opcode::PseudoVCOMPRESS_VM_M8_E16, + 1809 => Opcode::PseudoVCOMPRESS_VM_M8_E32, + 1810 => Opcode::PseudoVCOMPRESS_VM_M8_E64, + 1811 => Opcode::PseudoVCOMPRESS_VM_M8_E8, + 1812 => Opcode::PseudoVCOMPRESS_VM_MF2_E16, + 1813 => Opcode::PseudoVCOMPRESS_VM_MF2_E32, + 1814 => Opcode::PseudoVCOMPRESS_VM_MF2_E8, + 1815 => Opcode::PseudoVCOMPRESS_VM_MF4_E16, + 1816 => Opcode::PseudoVCOMPRESS_VM_MF4_E8, + 1817 => Opcode::PseudoVCOMPRESS_VM_MF8_E8, + 1818 => Opcode::PseudoVCPOP_M_B1, + 1819 => Opcode::PseudoVCPOP_M_B16, + 1820 => Opcode::PseudoVCPOP_M_B16_MASK, + 1821 => Opcode::PseudoVCPOP_M_B1_MASK, + 1822 => Opcode::PseudoVCPOP_M_B2, + 1823 => Opcode::PseudoVCPOP_M_B2_MASK, + 1824 => Opcode::PseudoVCPOP_M_B32, + 1825 => Opcode::PseudoVCPOP_M_B32_MASK, + 1826 => Opcode::PseudoVCPOP_M_B4, + 1827 => Opcode::PseudoVCPOP_M_B4_MASK, + 1828 => Opcode::PseudoVCPOP_M_B64, + 1829 => Opcode::PseudoVCPOP_M_B64_MASK, + 1830 => Opcode::PseudoVCPOP_M_B8, + 1831 => Opcode::PseudoVCPOP_M_B8_MASK, + 1832 => Opcode::PseudoVCPOP_V_M1, + 1833 => Opcode::PseudoVCPOP_V_M1_MASK, + 1834 => Opcode::PseudoVCPOP_V_M2, + 1835 => Opcode::PseudoVCPOP_V_M2_MASK, + 1836 => Opcode::PseudoVCPOP_V_M4, + 1837 => Opcode::PseudoVCPOP_V_M4_MASK, + 1838 => Opcode::PseudoVCPOP_V_M8, + 1839 => Opcode::PseudoVCPOP_V_M8_MASK, + 1840 => Opcode::PseudoVCPOP_V_MF2, + 1841 => Opcode::PseudoVCPOP_V_MF2_MASK, + 1842 => Opcode::PseudoVCPOP_V_MF4, + 1843 => Opcode::PseudoVCPOP_V_MF4_MASK, + 1844 => Opcode::PseudoVCPOP_V_MF8, + 1845 => Opcode::PseudoVCPOP_V_MF8_MASK, + 1846 => Opcode::PseudoVCTZ_V_M1, + 1847 => Opcode::PseudoVCTZ_V_M1_MASK, + 1848 => Opcode::PseudoVCTZ_V_M2, + 1849 => Opcode::PseudoVCTZ_V_M2_MASK, + 1850 => Opcode::PseudoVCTZ_V_M4, + 1851 => Opcode::PseudoVCTZ_V_M4_MASK, + 1852 => Opcode::PseudoVCTZ_V_M8, + 1853 => Opcode::PseudoVCTZ_V_M8_MASK, + 1854 => Opcode::PseudoVCTZ_V_MF2, + 1855 => Opcode::PseudoVCTZ_V_MF2_MASK, + 1856 => Opcode::PseudoVCTZ_V_MF4, + 1857 => Opcode::PseudoVCTZ_V_MF4_MASK, + 1858 => Opcode::PseudoVCTZ_V_MF8, + 1859 => Opcode::PseudoVCTZ_V_MF8_MASK, + 1860 => Opcode::PseudoVDIVU_VV_M1_E16, + 1861 => Opcode::PseudoVDIVU_VV_M1_E16_MASK, + 1862 => Opcode::PseudoVDIVU_VV_M1_E32, + 1863 => Opcode::PseudoVDIVU_VV_M1_E32_MASK, + 1864 => Opcode::PseudoVDIVU_VV_M1_E64, + 1865 => Opcode::PseudoVDIVU_VV_M1_E64_MASK, + 1866 => Opcode::PseudoVDIVU_VV_M1_E8, + 1867 => Opcode::PseudoVDIVU_VV_M1_E8_MASK, + 1868 => Opcode::PseudoVDIVU_VV_M2_E16, + 1869 => Opcode::PseudoVDIVU_VV_M2_E16_MASK, + 1870 => Opcode::PseudoVDIVU_VV_M2_E32, + 1871 => Opcode::PseudoVDIVU_VV_M2_E32_MASK, + 1872 => Opcode::PseudoVDIVU_VV_M2_E64, + 1873 => Opcode::PseudoVDIVU_VV_M2_E64_MASK, + 1874 => Opcode::PseudoVDIVU_VV_M2_E8, + 1875 => Opcode::PseudoVDIVU_VV_M2_E8_MASK, + 1876 => Opcode::PseudoVDIVU_VV_M4_E16, + 1877 => Opcode::PseudoVDIVU_VV_M4_E16_MASK, + 1878 => Opcode::PseudoVDIVU_VV_M4_E32, + 1879 => Opcode::PseudoVDIVU_VV_M4_E32_MASK, + 1880 => Opcode::PseudoVDIVU_VV_M4_E64, + 1881 => Opcode::PseudoVDIVU_VV_M4_E64_MASK, + 1882 => Opcode::PseudoVDIVU_VV_M4_E8, + 1883 => Opcode::PseudoVDIVU_VV_M4_E8_MASK, + 1884 => Opcode::PseudoVDIVU_VV_M8_E16, + 1885 => Opcode::PseudoVDIVU_VV_M8_E16_MASK, + 1886 => Opcode::PseudoVDIVU_VV_M8_E32, + 1887 => Opcode::PseudoVDIVU_VV_M8_E32_MASK, + 1888 => Opcode::PseudoVDIVU_VV_M8_E64, + 1889 => Opcode::PseudoVDIVU_VV_M8_E64_MASK, + 1890 => Opcode::PseudoVDIVU_VV_M8_E8, + 1891 => Opcode::PseudoVDIVU_VV_M8_E8_MASK, + 1892 => Opcode::PseudoVDIVU_VV_MF2_E16, + 1893 => Opcode::PseudoVDIVU_VV_MF2_E16_MASK, + 1894 => Opcode::PseudoVDIVU_VV_MF2_E32, + 1895 => Opcode::PseudoVDIVU_VV_MF2_E32_MASK, + 1896 => Opcode::PseudoVDIVU_VV_MF2_E8, + 1897 => Opcode::PseudoVDIVU_VV_MF2_E8_MASK, + 1898 => Opcode::PseudoVDIVU_VV_MF4_E16, + 1899 => Opcode::PseudoVDIVU_VV_MF4_E16_MASK, + 1900 => Opcode::PseudoVDIVU_VV_MF4_E8, + 1901 => Opcode::PseudoVDIVU_VV_MF4_E8_MASK, + 1902 => Opcode::PseudoVDIVU_VV_MF8_E8, + 1903 => Opcode::PseudoVDIVU_VV_MF8_E8_MASK, + 1904 => Opcode::PseudoVDIVU_VX_M1_E16, + 1905 => Opcode::PseudoVDIVU_VX_M1_E16_MASK, + 1906 => Opcode::PseudoVDIVU_VX_M1_E32, + 1907 => Opcode::PseudoVDIVU_VX_M1_E32_MASK, + 1908 => Opcode::PseudoVDIVU_VX_M1_E64, + 1909 => Opcode::PseudoVDIVU_VX_M1_E64_MASK, + 1910 => Opcode::PseudoVDIVU_VX_M1_E8, + 1911 => Opcode::PseudoVDIVU_VX_M1_E8_MASK, + 1912 => Opcode::PseudoVDIVU_VX_M2_E16, + 1913 => Opcode::PseudoVDIVU_VX_M2_E16_MASK, + 1914 => Opcode::PseudoVDIVU_VX_M2_E32, + 1915 => Opcode::PseudoVDIVU_VX_M2_E32_MASK, + 1916 => Opcode::PseudoVDIVU_VX_M2_E64, + 1917 => Opcode::PseudoVDIVU_VX_M2_E64_MASK, + 1918 => Opcode::PseudoVDIVU_VX_M2_E8, + 1919 => Opcode::PseudoVDIVU_VX_M2_E8_MASK, + 1920 => Opcode::PseudoVDIVU_VX_M4_E16, + 1921 => Opcode::PseudoVDIVU_VX_M4_E16_MASK, + 1922 => Opcode::PseudoVDIVU_VX_M4_E32, + 1923 => Opcode::PseudoVDIVU_VX_M4_E32_MASK, + 1924 => Opcode::PseudoVDIVU_VX_M4_E64, + 1925 => Opcode::PseudoVDIVU_VX_M4_E64_MASK, + 1926 => Opcode::PseudoVDIVU_VX_M4_E8, + 1927 => Opcode::PseudoVDIVU_VX_M4_E8_MASK, + 1928 => Opcode::PseudoVDIVU_VX_M8_E16, + 1929 => Opcode::PseudoVDIVU_VX_M8_E16_MASK, + 1930 => Opcode::PseudoVDIVU_VX_M8_E32, + 1931 => Opcode::PseudoVDIVU_VX_M8_E32_MASK, + 1932 => Opcode::PseudoVDIVU_VX_M8_E64, + 1933 => Opcode::PseudoVDIVU_VX_M8_E64_MASK, + 1934 => Opcode::PseudoVDIVU_VX_M8_E8, + 1935 => Opcode::PseudoVDIVU_VX_M8_E8_MASK, + 1936 => Opcode::PseudoVDIVU_VX_MF2_E16, + 1937 => Opcode::PseudoVDIVU_VX_MF2_E16_MASK, + 1938 => Opcode::PseudoVDIVU_VX_MF2_E32, + 1939 => Opcode::PseudoVDIVU_VX_MF2_E32_MASK, + 1940 => Opcode::PseudoVDIVU_VX_MF2_E8, + 1941 => Opcode::PseudoVDIVU_VX_MF2_E8_MASK, + 1942 => Opcode::PseudoVDIVU_VX_MF4_E16, + 1943 => Opcode::PseudoVDIVU_VX_MF4_E16_MASK, + 1944 => Opcode::PseudoVDIVU_VX_MF4_E8, + 1945 => Opcode::PseudoVDIVU_VX_MF4_E8_MASK, + 1946 => Opcode::PseudoVDIVU_VX_MF8_E8, + 1947 => Opcode::PseudoVDIVU_VX_MF8_E8_MASK, + 1948 => Opcode::PseudoVDIV_VV_M1_E16, + 1949 => Opcode::PseudoVDIV_VV_M1_E16_MASK, + 1950 => Opcode::PseudoVDIV_VV_M1_E32, + 1951 => Opcode::PseudoVDIV_VV_M1_E32_MASK, + 1952 => Opcode::PseudoVDIV_VV_M1_E64, + 1953 => Opcode::PseudoVDIV_VV_M1_E64_MASK, + 1954 => Opcode::PseudoVDIV_VV_M1_E8, + 1955 => Opcode::PseudoVDIV_VV_M1_E8_MASK, + 1956 => Opcode::PseudoVDIV_VV_M2_E16, + 1957 => Opcode::PseudoVDIV_VV_M2_E16_MASK, + 1958 => Opcode::PseudoVDIV_VV_M2_E32, + 1959 => Opcode::PseudoVDIV_VV_M2_E32_MASK, + 1960 => Opcode::PseudoVDIV_VV_M2_E64, + 1961 => Opcode::PseudoVDIV_VV_M2_E64_MASK, + 1962 => Opcode::PseudoVDIV_VV_M2_E8, + 1963 => Opcode::PseudoVDIV_VV_M2_E8_MASK, + 1964 => Opcode::PseudoVDIV_VV_M4_E16, + 1965 => Opcode::PseudoVDIV_VV_M4_E16_MASK, + 1966 => Opcode::PseudoVDIV_VV_M4_E32, + 1967 => Opcode::PseudoVDIV_VV_M4_E32_MASK, + 1968 => Opcode::PseudoVDIV_VV_M4_E64, + 1969 => Opcode::PseudoVDIV_VV_M4_E64_MASK, + 1970 => Opcode::PseudoVDIV_VV_M4_E8, + 1971 => Opcode::PseudoVDIV_VV_M4_E8_MASK, + 1972 => Opcode::PseudoVDIV_VV_M8_E16, + 1973 => Opcode::PseudoVDIV_VV_M8_E16_MASK, + 1974 => Opcode::PseudoVDIV_VV_M8_E32, + 1975 => Opcode::PseudoVDIV_VV_M8_E32_MASK, + 1976 => Opcode::PseudoVDIV_VV_M8_E64, + 1977 => Opcode::PseudoVDIV_VV_M8_E64_MASK, + 1978 => Opcode::PseudoVDIV_VV_M8_E8, + 1979 => Opcode::PseudoVDIV_VV_M8_E8_MASK, + 1980 => Opcode::PseudoVDIV_VV_MF2_E16, + 1981 => Opcode::PseudoVDIV_VV_MF2_E16_MASK, + 1982 => Opcode::PseudoVDIV_VV_MF2_E32, + 1983 => Opcode::PseudoVDIV_VV_MF2_E32_MASK, + 1984 => Opcode::PseudoVDIV_VV_MF2_E8, + 1985 => Opcode::PseudoVDIV_VV_MF2_E8_MASK, + 1986 => Opcode::PseudoVDIV_VV_MF4_E16, + 1987 => Opcode::PseudoVDIV_VV_MF4_E16_MASK, + 1988 => Opcode::PseudoVDIV_VV_MF4_E8, + 1989 => Opcode::PseudoVDIV_VV_MF4_E8_MASK, + 1990 => Opcode::PseudoVDIV_VV_MF8_E8, + 1991 => Opcode::PseudoVDIV_VV_MF8_E8_MASK, + 1992 => Opcode::PseudoVDIV_VX_M1_E16, + 1993 => Opcode::PseudoVDIV_VX_M1_E16_MASK, + 1994 => Opcode::PseudoVDIV_VX_M1_E32, + 1995 => Opcode::PseudoVDIV_VX_M1_E32_MASK, + 1996 => Opcode::PseudoVDIV_VX_M1_E64, + 1997 => Opcode::PseudoVDIV_VX_M1_E64_MASK, + 1998 => Opcode::PseudoVDIV_VX_M1_E8, + 1999 => Opcode::PseudoVDIV_VX_M1_E8_MASK, + 2000 => Opcode::PseudoVDIV_VX_M2_E16, + 2001 => Opcode::PseudoVDIV_VX_M2_E16_MASK, + 2002 => Opcode::PseudoVDIV_VX_M2_E32, + 2003 => Opcode::PseudoVDIV_VX_M2_E32_MASK, + 2004 => Opcode::PseudoVDIV_VX_M2_E64, + 2005 => Opcode::PseudoVDIV_VX_M2_E64_MASK, + 2006 => Opcode::PseudoVDIV_VX_M2_E8, + 2007 => Opcode::PseudoVDIV_VX_M2_E8_MASK, + 2008 => Opcode::PseudoVDIV_VX_M4_E16, + 2009 => Opcode::PseudoVDIV_VX_M4_E16_MASK, + 2010 => Opcode::PseudoVDIV_VX_M4_E32, + 2011 => Opcode::PseudoVDIV_VX_M4_E32_MASK, + 2012 => Opcode::PseudoVDIV_VX_M4_E64, + 2013 => Opcode::PseudoVDIV_VX_M4_E64_MASK, + 2014 => Opcode::PseudoVDIV_VX_M4_E8, + 2015 => Opcode::PseudoVDIV_VX_M4_E8_MASK, + 2016 => Opcode::PseudoVDIV_VX_M8_E16, + 2017 => Opcode::PseudoVDIV_VX_M8_E16_MASK, + 2018 => Opcode::PseudoVDIV_VX_M8_E32, + 2019 => Opcode::PseudoVDIV_VX_M8_E32_MASK, + 2020 => Opcode::PseudoVDIV_VX_M8_E64, + 2021 => Opcode::PseudoVDIV_VX_M8_E64_MASK, + 2022 => Opcode::PseudoVDIV_VX_M8_E8, + 2023 => Opcode::PseudoVDIV_VX_M8_E8_MASK, + 2024 => Opcode::PseudoVDIV_VX_MF2_E16, + 2025 => Opcode::PseudoVDIV_VX_MF2_E16_MASK, + 2026 => Opcode::PseudoVDIV_VX_MF2_E32, + 2027 => Opcode::PseudoVDIV_VX_MF2_E32_MASK, + 2028 => Opcode::PseudoVDIV_VX_MF2_E8, + 2029 => Opcode::PseudoVDIV_VX_MF2_E8_MASK, + 2030 => Opcode::PseudoVDIV_VX_MF4_E16, + 2031 => Opcode::PseudoVDIV_VX_MF4_E16_MASK, + 2032 => Opcode::PseudoVDIV_VX_MF4_E8, + 2033 => Opcode::PseudoVDIV_VX_MF4_E8_MASK, + 2034 => Opcode::PseudoVDIV_VX_MF8_E8, + 2035 => Opcode::PseudoVDIV_VX_MF8_E8_MASK, + 2036 => Opcode::PseudoVFADD_ALT_VFPR16_M1_E16, + 2037 => Opcode::PseudoVFADD_ALT_VFPR16_M1_E16_MASK, + 2038 => Opcode::PseudoVFADD_ALT_VFPR16_M2_E16, + 2039 => Opcode::PseudoVFADD_ALT_VFPR16_M2_E16_MASK, + 2040 => Opcode::PseudoVFADD_ALT_VFPR16_M4_E16, + 2041 => Opcode::PseudoVFADD_ALT_VFPR16_M4_E16_MASK, + 2042 => Opcode::PseudoVFADD_ALT_VFPR16_M8_E16, + 2043 => Opcode::PseudoVFADD_ALT_VFPR16_M8_E16_MASK, + 2044 => Opcode::PseudoVFADD_ALT_VFPR16_MF2_E16, + 2045 => Opcode::PseudoVFADD_ALT_VFPR16_MF2_E16_MASK, + 2046 => Opcode::PseudoVFADD_ALT_VFPR16_MF4_E16, + 2047 => Opcode::PseudoVFADD_ALT_VFPR16_MF4_E16_MASK, + 2048 => Opcode::PseudoVFADD_ALT_VV_M1_E16, + 2049 => Opcode::PseudoVFADD_ALT_VV_M1_E16_MASK, + 2050 => Opcode::PseudoVFADD_ALT_VV_M2_E16, + 2051 => Opcode::PseudoVFADD_ALT_VV_M2_E16_MASK, + 2052 => Opcode::PseudoVFADD_ALT_VV_M4_E16, + 2053 => Opcode::PseudoVFADD_ALT_VV_M4_E16_MASK, + 2054 => Opcode::PseudoVFADD_ALT_VV_M8_E16, + 2055 => Opcode::PseudoVFADD_ALT_VV_M8_E16_MASK, + 2056 => Opcode::PseudoVFADD_ALT_VV_MF2_E16, + 2057 => Opcode::PseudoVFADD_ALT_VV_MF2_E16_MASK, + 2058 => Opcode::PseudoVFADD_ALT_VV_MF4_E16, + 2059 => Opcode::PseudoVFADD_ALT_VV_MF4_E16_MASK, + 2060 => Opcode::PseudoVFADD_VFPR16_M1_E16, + 2061 => Opcode::PseudoVFADD_VFPR16_M1_E16_MASK, + 2062 => Opcode::PseudoVFADD_VFPR16_M2_E16, + 2063 => Opcode::PseudoVFADD_VFPR16_M2_E16_MASK, + 2064 => Opcode::PseudoVFADD_VFPR16_M4_E16, + 2065 => Opcode::PseudoVFADD_VFPR16_M4_E16_MASK, + 2066 => Opcode::PseudoVFADD_VFPR16_M8_E16, + 2067 => Opcode::PseudoVFADD_VFPR16_M8_E16_MASK, + 2068 => Opcode::PseudoVFADD_VFPR16_MF2_E16, + 2069 => Opcode::PseudoVFADD_VFPR16_MF2_E16_MASK, + 2070 => Opcode::PseudoVFADD_VFPR16_MF4_E16, + 2071 => Opcode::PseudoVFADD_VFPR16_MF4_E16_MASK, + 2072 => Opcode::PseudoVFADD_VFPR32_M1_E32, + 2073 => Opcode::PseudoVFADD_VFPR32_M1_E32_MASK, + 2074 => Opcode::PseudoVFADD_VFPR32_M2_E32, + 2075 => Opcode::PseudoVFADD_VFPR32_M2_E32_MASK, + 2076 => Opcode::PseudoVFADD_VFPR32_M4_E32, + 2077 => Opcode::PseudoVFADD_VFPR32_M4_E32_MASK, + 2078 => Opcode::PseudoVFADD_VFPR32_M8_E32, + 2079 => Opcode::PseudoVFADD_VFPR32_M8_E32_MASK, + 2080 => Opcode::PseudoVFADD_VFPR32_MF2_E32, + 2081 => Opcode::PseudoVFADD_VFPR32_MF2_E32_MASK, + 2082 => Opcode::PseudoVFADD_VFPR64_M1_E64, + 2083 => Opcode::PseudoVFADD_VFPR64_M1_E64_MASK, + 2084 => Opcode::PseudoVFADD_VFPR64_M2_E64, + 2085 => Opcode::PseudoVFADD_VFPR64_M2_E64_MASK, + 2086 => Opcode::PseudoVFADD_VFPR64_M4_E64, + 2087 => Opcode::PseudoVFADD_VFPR64_M4_E64_MASK, + 2088 => Opcode::PseudoVFADD_VFPR64_M8_E64, + 2089 => Opcode::PseudoVFADD_VFPR64_M8_E64_MASK, + 2090 => Opcode::PseudoVFADD_VV_M1_E16, + 2091 => Opcode::PseudoVFADD_VV_M1_E16_MASK, + 2092 => Opcode::PseudoVFADD_VV_M1_E32, + 2093 => Opcode::PseudoVFADD_VV_M1_E32_MASK, + 2094 => Opcode::PseudoVFADD_VV_M1_E64, + 2095 => Opcode::PseudoVFADD_VV_M1_E64_MASK, + 2096 => Opcode::PseudoVFADD_VV_M2_E16, + 2097 => Opcode::PseudoVFADD_VV_M2_E16_MASK, + 2098 => Opcode::PseudoVFADD_VV_M2_E32, + 2099 => Opcode::PseudoVFADD_VV_M2_E32_MASK, + 2100 => Opcode::PseudoVFADD_VV_M2_E64, + 2101 => Opcode::PseudoVFADD_VV_M2_E64_MASK, + 2102 => Opcode::PseudoVFADD_VV_M4_E16, + 2103 => Opcode::PseudoVFADD_VV_M4_E16_MASK, + 2104 => Opcode::PseudoVFADD_VV_M4_E32, + 2105 => Opcode::PseudoVFADD_VV_M4_E32_MASK, + 2106 => Opcode::PseudoVFADD_VV_M4_E64, + 2107 => Opcode::PseudoVFADD_VV_M4_E64_MASK, + 2108 => Opcode::PseudoVFADD_VV_M8_E16, + 2109 => Opcode::PseudoVFADD_VV_M8_E16_MASK, + 2110 => Opcode::PseudoVFADD_VV_M8_E32, + 2111 => Opcode::PseudoVFADD_VV_M8_E32_MASK, + 2112 => Opcode::PseudoVFADD_VV_M8_E64, + 2113 => Opcode::PseudoVFADD_VV_M8_E64_MASK, + 2114 => Opcode::PseudoVFADD_VV_MF2_E16, + 2115 => Opcode::PseudoVFADD_VV_MF2_E16_MASK, + 2116 => Opcode::PseudoVFADD_VV_MF2_E32, + 2117 => Opcode::PseudoVFADD_VV_MF2_E32_MASK, + 2118 => Opcode::PseudoVFADD_VV_MF4_E16, + 2119 => Opcode::PseudoVFADD_VV_MF4_E16_MASK, + 2120 => Opcode::PseudoVFCLASS_ALT_V_M1, + 2121 => Opcode::PseudoVFCLASS_ALT_V_M1_MASK, + 2122 => Opcode::PseudoVFCLASS_ALT_V_M2, + 2123 => Opcode::PseudoVFCLASS_ALT_V_M2_MASK, + 2124 => Opcode::PseudoVFCLASS_ALT_V_M4, + 2125 => Opcode::PseudoVFCLASS_ALT_V_M4_MASK, + 2126 => Opcode::PseudoVFCLASS_ALT_V_M8, + 2127 => Opcode::PseudoVFCLASS_ALT_V_M8_MASK, + 2128 => Opcode::PseudoVFCLASS_ALT_V_MF2, + 2129 => Opcode::PseudoVFCLASS_ALT_V_MF2_MASK, + 2130 => Opcode::PseudoVFCLASS_ALT_V_MF4, + 2131 => Opcode::PseudoVFCLASS_ALT_V_MF4_MASK, + 2132 => Opcode::PseudoVFCLASS_V_M1, + 2133 => Opcode::PseudoVFCLASS_V_M1_MASK, + 2134 => Opcode::PseudoVFCLASS_V_M2, + 2135 => Opcode::PseudoVFCLASS_V_M2_MASK, + 2136 => Opcode::PseudoVFCLASS_V_M4, + 2137 => Opcode::PseudoVFCLASS_V_M4_MASK, + 2138 => Opcode::PseudoVFCLASS_V_M8, + 2139 => Opcode::PseudoVFCLASS_V_M8_MASK, + 2140 => Opcode::PseudoVFCLASS_V_MF2, + 2141 => Opcode::PseudoVFCLASS_V_MF2_MASK, + 2142 => Opcode::PseudoVFCLASS_V_MF4, + 2143 => Opcode::PseudoVFCLASS_V_MF4_MASK, + 2144 => Opcode::PseudoVFCVT_F_XU_V_M1_E16, + 2145 => Opcode::PseudoVFCVT_F_XU_V_M1_E16_MASK, + 2146 => Opcode::PseudoVFCVT_F_XU_V_M1_E32, + 2147 => Opcode::PseudoVFCVT_F_XU_V_M1_E32_MASK, + 2148 => Opcode::PseudoVFCVT_F_XU_V_M1_E64, + 2149 => Opcode::PseudoVFCVT_F_XU_V_M1_E64_MASK, + 2150 => Opcode::PseudoVFCVT_F_XU_V_M2_E16, + 2151 => Opcode::PseudoVFCVT_F_XU_V_M2_E16_MASK, + 2152 => Opcode::PseudoVFCVT_F_XU_V_M2_E32, + 2153 => Opcode::PseudoVFCVT_F_XU_V_M2_E32_MASK, + 2154 => Opcode::PseudoVFCVT_F_XU_V_M2_E64, + 2155 => Opcode::PseudoVFCVT_F_XU_V_M2_E64_MASK, + 2156 => Opcode::PseudoVFCVT_F_XU_V_M4_E16, + 2157 => Opcode::PseudoVFCVT_F_XU_V_M4_E16_MASK, + 2158 => Opcode::PseudoVFCVT_F_XU_V_M4_E32, + 2159 => Opcode::PseudoVFCVT_F_XU_V_M4_E32_MASK, + 2160 => Opcode::PseudoVFCVT_F_XU_V_M4_E64, + 2161 => Opcode::PseudoVFCVT_F_XU_V_M4_E64_MASK, + 2162 => Opcode::PseudoVFCVT_F_XU_V_M8_E16, + 2163 => Opcode::PseudoVFCVT_F_XU_V_M8_E16_MASK, + 2164 => Opcode::PseudoVFCVT_F_XU_V_M8_E32, + 2165 => Opcode::PseudoVFCVT_F_XU_V_M8_E32_MASK, + 2166 => Opcode::PseudoVFCVT_F_XU_V_M8_E64, + 2167 => Opcode::PseudoVFCVT_F_XU_V_M8_E64_MASK, + 2168 => Opcode::PseudoVFCVT_F_XU_V_MF2_E16, + 2169 => Opcode::PseudoVFCVT_F_XU_V_MF2_E16_MASK, + 2170 => Opcode::PseudoVFCVT_F_XU_V_MF2_E32, + 2171 => Opcode::PseudoVFCVT_F_XU_V_MF2_E32_MASK, + 2172 => Opcode::PseudoVFCVT_F_XU_V_MF4_E16, + 2173 => Opcode::PseudoVFCVT_F_XU_V_MF4_E16_MASK, + 2174 => Opcode::PseudoVFCVT_F_X_V_M1_E16, + 2175 => Opcode::PseudoVFCVT_F_X_V_M1_E16_MASK, + 2176 => Opcode::PseudoVFCVT_F_X_V_M1_E32, + 2177 => Opcode::PseudoVFCVT_F_X_V_M1_E32_MASK, + 2178 => Opcode::PseudoVFCVT_F_X_V_M1_E64, + 2179 => Opcode::PseudoVFCVT_F_X_V_M1_E64_MASK, + 2180 => Opcode::PseudoVFCVT_F_X_V_M2_E16, + 2181 => Opcode::PseudoVFCVT_F_X_V_M2_E16_MASK, + 2182 => Opcode::PseudoVFCVT_F_X_V_M2_E32, + 2183 => Opcode::PseudoVFCVT_F_X_V_M2_E32_MASK, + 2184 => Opcode::PseudoVFCVT_F_X_V_M2_E64, + 2185 => Opcode::PseudoVFCVT_F_X_V_M2_E64_MASK, + 2186 => Opcode::PseudoVFCVT_F_X_V_M4_E16, + 2187 => Opcode::PseudoVFCVT_F_X_V_M4_E16_MASK, + 2188 => Opcode::PseudoVFCVT_F_X_V_M4_E32, + 2189 => Opcode::PseudoVFCVT_F_X_V_M4_E32_MASK, + 2190 => Opcode::PseudoVFCVT_F_X_V_M4_E64, + 2191 => Opcode::PseudoVFCVT_F_X_V_M4_E64_MASK, + 2192 => Opcode::PseudoVFCVT_F_X_V_M8_E16, + 2193 => Opcode::PseudoVFCVT_F_X_V_M8_E16_MASK, + 2194 => Opcode::PseudoVFCVT_F_X_V_M8_E32, + 2195 => Opcode::PseudoVFCVT_F_X_V_M8_E32_MASK, + 2196 => Opcode::PseudoVFCVT_F_X_V_M8_E64, + 2197 => Opcode::PseudoVFCVT_F_X_V_M8_E64_MASK, + 2198 => Opcode::PseudoVFCVT_F_X_V_MF2_E16, + 2199 => Opcode::PseudoVFCVT_F_X_V_MF2_E16_MASK, + 2200 => Opcode::PseudoVFCVT_F_X_V_MF2_E32, + 2201 => Opcode::PseudoVFCVT_F_X_V_MF2_E32_MASK, + 2202 => Opcode::PseudoVFCVT_F_X_V_MF4_E16, + 2203 => Opcode::PseudoVFCVT_F_X_V_MF4_E16_MASK, + 2204 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M1, + 2205 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M1_MASK, + 2206 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M2, + 2207 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M2_MASK, + 2208 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M4, + 2209 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M4_MASK, + 2210 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M8, + 2211 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M8_MASK, + 2212 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF2, + 2213 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, + 2214 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF4, + 2215 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, + 2216 => Opcode::PseudoVFCVT_RTZ_X_F_V_M1, + 2217 => Opcode::PseudoVFCVT_RTZ_X_F_V_M1_MASK, + 2218 => Opcode::PseudoVFCVT_RTZ_X_F_V_M2, + 2219 => Opcode::PseudoVFCVT_RTZ_X_F_V_M2_MASK, + 2220 => Opcode::PseudoVFCVT_RTZ_X_F_V_M4, + 2221 => Opcode::PseudoVFCVT_RTZ_X_F_V_M4_MASK, + 2222 => Opcode::PseudoVFCVT_RTZ_X_F_V_M8, + 2223 => Opcode::PseudoVFCVT_RTZ_X_F_V_M8_MASK, + 2224 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF2, + 2225 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF2_MASK, + 2226 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF4, + 2227 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF4_MASK, + 2228 => Opcode::PseudoVFCVT_XU_F_V_M1, + 2229 => Opcode::PseudoVFCVT_XU_F_V_M1_MASK, + 2230 => Opcode::PseudoVFCVT_XU_F_V_M2, + 2231 => Opcode::PseudoVFCVT_XU_F_V_M2_MASK, + 2232 => Opcode::PseudoVFCVT_XU_F_V_M4, + 2233 => Opcode::PseudoVFCVT_XU_F_V_M4_MASK, + 2234 => Opcode::PseudoVFCVT_XU_F_V_M8, + 2235 => Opcode::PseudoVFCVT_XU_F_V_M8_MASK, + 2236 => Opcode::PseudoVFCVT_XU_F_V_MF2, + 2237 => Opcode::PseudoVFCVT_XU_F_V_MF2_MASK, + 2238 => Opcode::PseudoVFCVT_XU_F_V_MF4, + 2239 => Opcode::PseudoVFCVT_XU_F_V_MF4_MASK, + 2240 => Opcode::PseudoVFCVT_X_F_V_M1, + 2241 => Opcode::PseudoVFCVT_X_F_V_M1_MASK, + 2242 => Opcode::PseudoVFCVT_X_F_V_M2, + 2243 => Opcode::PseudoVFCVT_X_F_V_M2_MASK, + 2244 => Opcode::PseudoVFCVT_X_F_V_M4, + 2245 => Opcode::PseudoVFCVT_X_F_V_M4_MASK, + 2246 => Opcode::PseudoVFCVT_X_F_V_M8, + 2247 => Opcode::PseudoVFCVT_X_F_V_M8_MASK, + 2248 => Opcode::PseudoVFCVT_X_F_V_MF2, + 2249 => Opcode::PseudoVFCVT_X_F_V_MF2_MASK, + 2250 => Opcode::PseudoVFCVT_X_F_V_MF4, + 2251 => Opcode::PseudoVFCVT_X_F_V_MF4_MASK, + 2252 => Opcode::PseudoVFDIV_VFPR16_M1_E16, + 2253 => Opcode::PseudoVFDIV_VFPR16_M1_E16_MASK, + 2254 => Opcode::PseudoVFDIV_VFPR16_M2_E16, + 2255 => Opcode::PseudoVFDIV_VFPR16_M2_E16_MASK, + 2256 => Opcode::PseudoVFDIV_VFPR16_M4_E16, + 2257 => Opcode::PseudoVFDIV_VFPR16_M4_E16_MASK, + 2258 => Opcode::PseudoVFDIV_VFPR16_M8_E16, + 2259 => Opcode::PseudoVFDIV_VFPR16_M8_E16_MASK, + 2260 => Opcode::PseudoVFDIV_VFPR16_MF2_E16, + 2261 => Opcode::PseudoVFDIV_VFPR16_MF2_E16_MASK, + 2262 => Opcode::PseudoVFDIV_VFPR16_MF4_E16, + 2263 => Opcode::PseudoVFDIV_VFPR16_MF4_E16_MASK, + 2264 => Opcode::PseudoVFDIV_VFPR32_M1_E32, + 2265 => Opcode::PseudoVFDIV_VFPR32_M1_E32_MASK, + 2266 => Opcode::PseudoVFDIV_VFPR32_M2_E32, + 2267 => Opcode::PseudoVFDIV_VFPR32_M2_E32_MASK, + 2268 => Opcode::PseudoVFDIV_VFPR32_M4_E32, + 2269 => Opcode::PseudoVFDIV_VFPR32_M4_E32_MASK, + 2270 => Opcode::PseudoVFDIV_VFPR32_M8_E32, + 2271 => Opcode::PseudoVFDIV_VFPR32_M8_E32_MASK, + 2272 => Opcode::PseudoVFDIV_VFPR32_MF2_E32, + 2273 => Opcode::PseudoVFDIV_VFPR32_MF2_E32_MASK, + 2274 => Opcode::PseudoVFDIV_VFPR64_M1_E64, + 2275 => Opcode::PseudoVFDIV_VFPR64_M1_E64_MASK, + 2276 => Opcode::PseudoVFDIV_VFPR64_M2_E64, + 2277 => Opcode::PseudoVFDIV_VFPR64_M2_E64_MASK, + 2278 => Opcode::PseudoVFDIV_VFPR64_M4_E64, + 2279 => Opcode::PseudoVFDIV_VFPR64_M4_E64_MASK, + 2280 => Opcode::PseudoVFDIV_VFPR64_M8_E64, + 2281 => Opcode::PseudoVFDIV_VFPR64_M8_E64_MASK, + 2282 => Opcode::PseudoVFDIV_VV_M1_E16, + 2283 => Opcode::PseudoVFDIV_VV_M1_E16_MASK, + 2284 => Opcode::PseudoVFDIV_VV_M1_E32, + 2285 => Opcode::PseudoVFDIV_VV_M1_E32_MASK, + 2286 => Opcode::PseudoVFDIV_VV_M1_E64, + 2287 => Opcode::PseudoVFDIV_VV_M1_E64_MASK, + 2288 => Opcode::PseudoVFDIV_VV_M2_E16, + 2289 => Opcode::PseudoVFDIV_VV_M2_E16_MASK, + 2290 => Opcode::PseudoVFDIV_VV_M2_E32, + 2291 => Opcode::PseudoVFDIV_VV_M2_E32_MASK, + 2292 => Opcode::PseudoVFDIV_VV_M2_E64, + 2293 => Opcode::PseudoVFDIV_VV_M2_E64_MASK, + 2294 => Opcode::PseudoVFDIV_VV_M4_E16, + 2295 => Opcode::PseudoVFDIV_VV_M4_E16_MASK, + 2296 => Opcode::PseudoVFDIV_VV_M4_E32, + 2297 => Opcode::PseudoVFDIV_VV_M4_E32_MASK, + 2298 => Opcode::PseudoVFDIV_VV_M4_E64, + 2299 => Opcode::PseudoVFDIV_VV_M4_E64_MASK, + 2300 => Opcode::PseudoVFDIV_VV_M8_E16, + 2301 => Opcode::PseudoVFDIV_VV_M8_E16_MASK, + 2302 => Opcode::PseudoVFDIV_VV_M8_E32, + 2303 => Opcode::PseudoVFDIV_VV_M8_E32_MASK, + 2304 => Opcode::PseudoVFDIV_VV_M8_E64, + 2305 => Opcode::PseudoVFDIV_VV_M8_E64_MASK, + 2306 => Opcode::PseudoVFDIV_VV_MF2_E16, + 2307 => Opcode::PseudoVFDIV_VV_MF2_E16_MASK, + 2308 => Opcode::PseudoVFDIV_VV_MF2_E32, + 2309 => Opcode::PseudoVFDIV_VV_MF2_E32_MASK, + 2310 => Opcode::PseudoVFDIV_VV_MF4_E16, + 2311 => Opcode::PseudoVFDIV_VV_MF4_E16_MASK, + 2312 => Opcode::PseudoVFIRST_M_B1, + 2313 => Opcode::PseudoVFIRST_M_B16, + 2314 => Opcode::PseudoVFIRST_M_B16_MASK, + 2315 => Opcode::PseudoVFIRST_M_B1_MASK, + 2316 => Opcode::PseudoVFIRST_M_B2, + 2317 => Opcode::PseudoVFIRST_M_B2_MASK, + 2318 => Opcode::PseudoVFIRST_M_B32, + 2319 => Opcode::PseudoVFIRST_M_B32_MASK, + 2320 => Opcode::PseudoVFIRST_M_B4, + 2321 => Opcode::PseudoVFIRST_M_B4_MASK, + 2322 => Opcode::PseudoVFIRST_M_B64, + 2323 => Opcode::PseudoVFIRST_M_B64_MASK, + 2324 => Opcode::PseudoVFIRST_M_B8, + 2325 => Opcode::PseudoVFIRST_M_B8_MASK, + 2326 => Opcode::PseudoVFMACC_ALT_VFPR16_M1_E16, + 2327 => Opcode::PseudoVFMACC_ALT_VFPR16_M1_E16_MASK, + 2328 => Opcode::PseudoVFMACC_ALT_VFPR16_M2_E16, + 2329 => Opcode::PseudoVFMACC_ALT_VFPR16_M2_E16_MASK, + 2330 => Opcode::PseudoVFMACC_ALT_VFPR16_M4_E16, + 2331 => Opcode::PseudoVFMACC_ALT_VFPR16_M4_E16_MASK, + 2332 => Opcode::PseudoVFMACC_ALT_VFPR16_M8_E16, + 2333 => Opcode::PseudoVFMACC_ALT_VFPR16_M8_E16_MASK, + 2334 => Opcode::PseudoVFMACC_ALT_VFPR16_MF2_E16, + 2335 => Opcode::PseudoVFMACC_ALT_VFPR16_MF2_E16_MASK, + 2336 => Opcode::PseudoVFMACC_ALT_VFPR16_MF4_E16, + 2337 => Opcode::PseudoVFMACC_ALT_VFPR16_MF4_E16_MASK, + 2338 => Opcode::PseudoVFMACC_ALT_VV_M1_E16, + 2339 => Opcode::PseudoVFMACC_ALT_VV_M1_E16_MASK, + 2340 => Opcode::PseudoVFMACC_ALT_VV_M2_E16, + 2341 => Opcode::PseudoVFMACC_ALT_VV_M2_E16_MASK, + 2342 => Opcode::PseudoVFMACC_ALT_VV_M4_E16, + 2343 => Opcode::PseudoVFMACC_ALT_VV_M4_E16_MASK, + 2344 => Opcode::PseudoVFMACC_ALT_VV_M8_E16, + 2345 => Opcode::PseudoVFMACC_ALT_VV_M8_E16_MASK, + 2346 => Opcode::PseudoVFMACC_ALT_VV_MF2_E16, + 2347 => Opcode::PseudoVFMACC_ALT_VV_MF2_E16_MASK, + 2348 => Opcode::PseudoVFMACC_ALT_VV_MF4_E16, + 2349 => Opcode::PseudoVFMACC_ALT_VV_MF4_E16_MASK, + 2350 => Opcode::PseudoVFMACC_VFPR16_M1_E16, + 2351 => Opcode::PseudoVFMACC_VFPR16_M1_E16_MASK, + 2352 => Opcode::PseudoVFMACC_VFPR16_M2_E16, + 2353 => Opcode::PseudoVFMACC_VFPR16_M2_E16_MASK, + 2354 => Opcode::PseudoVFMACC_VFPR16_M4_E16, + 2355 => Opcode::PseudoVFMACC_VFPR16_M4_E16_MASK, + 2356 => Opcode::PseudoVFMACC_VFPR16_M8_E16, + 2357 => Opcode::PseudoVFMACC_VFPR16_M8_E16_MASK, + 2358 => Opcode::PseudoVFMACC_VFPR16_MF2_E16, + 2359 => Opcode::PseudoVFMACC_VFPR16_MF2_E16_MASK, + 2360 => Opcode::PseudoVFMACC_VFPR16_MF4_E16, + 2361 => Opcode::PseudoVFMACC_VFPR16_MF4_E16_MASK, + 2362 => Opcode::PseudoVFMACC_VFPR32_M1_E32, + 2363 => Opcode::PseudoVFMACC_VFPR32_M1_E32_MASK, + 2364 => Opcode::PseudoVFMACC_VFPR32_M2_E32, + 2365 => Opcode::PseudoVFMACC_VFPR32_M2_E32_MASK, + 2366 => Opcode::PseudoVFMACC_VFPR32_M4_E32, + 2367 => Opcode::PseudoVFMACC_VFPR32_M4_E32_MASK, + 2368 => Opcode::PseudoVFMACC_VFPR32_M8_E32, + 2369 => Opcode::PseudoVFMACC_VFPR32_M8_E32_MASK, + 2370 => Opcode::PseudoVFMACC_VFPR32_MF2_E32, + 2371 => Opcode::PseudoVFMACC_VFPR32_MF2_E32_MASK, + 2372 => Opcode::PseudoVFMACC_VFPR64_M1_E64, + 2373 => Opcode::PseudoVFMACC_VFPR64_M1_E64_MASK, + 2374 => Opcode::PseudoVFMACC_VFPR64_M2_E64, + 2375 => Opcode::PseudoVFMACC_VFPR64_M2_E64_MASK, + 2376 => Opcode::PseudoVFMACC_VFPR64_M4_E64, + 2377 => Opcode::PseudoVFMACC_VFPR64_M4_E64_MASK, + 2378 => Opcode::PseudoVFMACC_VFPR64_M8_E64, + 2379 => Opcode::PseudoVFMACC_VFPR64_M8_E64_MASK, + 2380 => Opcode::PseudoVFMACC_VV_M1_E16, + 2381 => Opcode::PseudoVFMACC_VV_M1_E16_MASK, + 2382 => Opcode::PseudoVFMACC_VV_M1_E32, + 2383 => Opcode::PseudoVFMACC_VV_M1_E32_MASK, + 2384 => Opcode::PseudoVFMACC_VV_M1_E64, + 2385 => Opcode::PseudoVFMACC_VV_M1_E64_MASK, + 2386 => Opcode::PseudoVFMACC_VV_M2_E16, + 2387 => Opcode::PseudoVFMACC_VV_M2_E16_MASK, + 2388 => Opcode::PseudoVFMACC_VV_M2_E32, + 2389 => Opcode::PseudoVFMACC_VV_M2_E32_MASK, + 2390 => Opcode::PseudoVFMACC_VV_M2_E64, + 2391 => Opcode::PseudoVFMACC_VV_M2_E64_MASK, + 2392 => Opcode::PseudoVFMACC_VV_M4_E16, + 2393 => Opcode::PseudoVFMACC_VV_M4_E16_MASK, + 2394 => Opcode::PseudoVFMACC_VV_M4_E32, + 2395 => Opcode::PseudoVFMACC_VV_M4_E32_MASK, + 2396 => Opcode::PseudoVFMACC_VV_M4_E64, + 2397 => Opcode::PseudoVFMACC_VV_M4_E64_MASK, + 2398 => Opcode::PseudoVFMACC_VV_M8_E16, + 2399 => Opcode::PseudoVFMACC_VV_M8_E16_MASK, + 2400 => Opcode::PseudoVFMACC_VV_M8_E32, + 2401 => Opcode::PseudoVFMACC_VV_M8_E32_MASK, + 2402 => Opcode::PseudoVFMACC_VV_M8_E64, + 2403 => Opcode::PseudoVFMACC_VV_M8_E64_MASK, + 2404 => Opcode::PseudoVFMACC_VV_MF2_E16, + 2405 => Opcode::PseudoVFMACC_VV_MF2_E16_MASK, + 2406 => Opcode::PseudoVFMACC_VV_MF2_E32, + 2407 => Opcode::PseudoVFMACC_VV_MF2_E32_MASK, + 2408 => Opcode::PseudoVFMACC_VV_MF4_E16, + 2409 => Opcode::PseudoVFMACC_VV_MF4_E16_MASK, + 2410 => Opcode::PseudoVFMADD_ALT_VFPR16_M1_E16, + 2411 => Opcode::PseudoVFMADD_ALT_VFPR16_M1_E16_MASK, + 2412 => Opcode::PseudoVFMADD_ALT_VFPR16_M2_E16, + 2413 => Opcode::PseudoVFMADD_ALT_VFPR16_M2_E16_MASK, + 2414 => Opcode::PseudoVFMADD_ALT_VFPR16_M4_E16, + 2415 => Opcode::PseudoVFMADD_ALT_VFPR16_M4_E16_MASK, + 2416 => Opcode::PseudoVFMADD_ALT_VFPR16_M8_E16, + 2417 => Opcode::PseudoVFMADD_ALT_VFPR16_M8_E16_MASK, + 2418 => Opcode::PseudoVFMADD_ALT_VFPR16_MF2_E16, + 2419 => Opcode::PseudoVFMADD_ALT_VFPR16_MF2_E16_MASK, + 2420 => Opcode::PseudoVFMADD_ALT_VFPR16_MF4_E16, + 2421 => Opcode::PseudoVFMADD_ALT_VFPR16_MF4_E16_MASK, + 2422 => Opcode::PseudoVFMADD_ALT_VV_M1_E16, + 2423 => Opcode::PseudoVFMADD_ALT_VV_M1_E16_MASK, + 2424 => Opcode::PseudoVFMADD_ALT_VV_M2_E16, + 2425 => Opcode::PseudoVFMADD_ALT_VV_M2_E16_MASK, + 2426 => Opcode::PseudoVFMADD_ALT_VV_M4_E16, + 2427 => Opcode::PseudoVFMADD_ALT_VV_M4_E16_MASK, + 2428 => Opcode::PseudoVFMADD_ALT_VV_M8_E16, + 2429 => Opcode::PseudoVFMADD_ALT_VV_M8_E16_MASK, + 2430 => Opcode::PseudoVFMADD_ALT_VV_MF2_E16, + 2431 => Opcode::PseudoVFMADD_ALT_VV_MF2_E16_MASK, + 2432 => Opcode::PseudoVFMADD_ALT_VV_MF4_E16, + 2433 => Opcode::PseudoVFMADD_ALT_VV_MF4_E16_MASK, + 2434 => Opcode::PseudoVFMADD_VFPR16_M1_E16, + 2435 => Opcode::PseudoVFMADD_VFPR16_M1_E16_MASK, + 2436 => Opcode::PseudoVFMADD_VFPR16_M2_E16, + 2437 => Opcode::PseudoVFMADD_VFPR16_M2_E16_MASK, + 2438 => Opcode::PseudoVFMADD_VFPR16_M4_E16, + 2439 => Opcode::PseudoVFMADD_VFPR16_M4_E16_MASK, + 2440 => Opcode::PseudoVFMADD_VFPR16_M8_E16, + 2441 => Opcode::PseudoVFMADD_VFPR16_M8_E16_MASK, + 2442 => Opcode::PseudoVFMADD_VFPR16_MF2_E16, + 2443 => Opcode::PseudoVFMADD_VFPR16_MF2_E16_MASK, + 2444 => Opcode::PseudoVFMADD_VFPR16_MF4_E16, + 2445 => Opcode::PseudoVFMADD_VFPR16_MF4_E16_MASK, + 2446 => Opcode::PseudoVFMADD_VFPR32_M1_E32, + 2447 => Opcode::PseudoVFMADD_VFPR32_M1_E32_MASK, + 2448 => Opcode::PseudoVFMADD_VFPR32_M2_E32, + 2449 => Opcode::PseudoVFMADD_VFPR32_M2_E32_MASK, + 2450 => Opcode::PseudoVFMADD_VFPR32_M4_E32, + 2451 => Opcode::PseudoVFMADD_VFPR32_M4_E32_MASK, + 2452 => Opcode::PseudoVFMADD_VFPR32_M8_E32, + 2453 => Opcode::PseudoVFMADD_VFPR32_M8_E32_MASK, + 2454 => Opcode::PseudoVFMADD_VFPR32_MF2_E32, + 2455 => Opcode::PseudoVFMADD_VFPR32_MF2_E32_MASK, + 2456 => Opcode::PseudoVFMADD_VFPR64_M1_E64, + 2457 => Opcode::PseudoVFMADD_VFPR64_M1_E64_MASK, + 2458 => Opcode::PseudoVFMADD_VFPR64_M2_E64, + 2459 => Opcode::PseudoVFMADD_VFPR64_M2_E64_MASK, + 2460 => Opcode::PseudoVFMADD_VFPR64_M4_E64, + 2461 => Opcode::PseudoVFMADD_VFPR64_M4_E64_MASK, + 2462 => Opcode::PseudoVFMADD_VFPR64_M8_E64, + 2463 => Opcode::PseudoVFMADD_VFPR64_M8_E64_MASK, + 2464 => Opcode::PseudoVFMADD_VV_M1_E16, + 2465 => Opcode::PseudoVFMADD_VV_M1_E16_MASK, + 2466 => Opcode::PseudoVFMADD_VV_M1_E32, + 2467 => Opcode::PseudoVFMADD_VV_M1_E32_MASK, + 2468 => Opcode::PseudoVFMADD_VV_M1_E64, + 2469 => Opcode::PseudoVFMADD_VV_M1_E64_MASK, + 2470 => Opcode::PseudoVFMADD_VV_M2_E16, + 2471 => Opcode::PseudoVFMADD_VV_M2_E16_MASK, + 2472 => Opcode::PseudoVFMADD_VV_M2_E32, + 2473 => Opcode::PseudoVFMADD_VV_M2_E32_MASK, + 2474 => Opcode::PseudoVFMADD_VV_M2_E64, + 2475 => Opcode::PseudoVFMADD_VV_M2_E64_MASK, + 2476 => Opcode::PseudoVFMADD_VV_M4_E16, + 2477 => Opcode::PseudoVFMADD_VV_M4_E16_MASK, + 2478 => Opcode::PseudoVFMADD_VV_M4_E32, + 2479 => Opcode::PseudoVFMADD_VV_M4_E32_MASK, + 2480 => Opcode::PseudoVFMADD_VV_M4_E64, + 2481 => Opcode::PseudoVFMADD_VV_M4_E64_MASK, + 2482 => Opcode::PseudoVFMADD_VV_M8_E16, + 2483 => Opcode::PseudoVFMADD_VV_M8_E16_MASK, + 2484 => Opcode::PseudoVFMADD_VV_M8_E32, + 2485 => Opcode::PseudoVFMADD_VV_M8_E32_MASK, + 2486 => Opcode::PseudoVFMADD_VV_M8_E64, + 2487 => Opcode::PseudoVFMADD_VV_M8_E64_MASK, + 2488 => Opcode::PseudoVFMADD_VV_MF2_E16, + 2489 => Opcode::PseudoVFMADD_VV_MF2_E16_MASK, + 2490 => Opcode::PseudoVFMADD_VV_MF2_E32, + 2491 => Opcode::PseudoVFMADD_VV_MF2_E32_MASK, + 2492 => Opcode::PseudoVFMADD_VV_MF4_E16, + 2493 => Opcode::PseudoVFMADD_VV_MF4_E16_MASK, + 2494 => Opcode::PseudoVFMAX_ALT_VFPR16_M1_E16, + 2495 => Opcode::PseudoVFMAX_ALT_VFPR16_M1_E16_MASK, + 2496 => Opcode::PseudoVFMAX_ALT_VFPR16_M2_E16, + 2497 => Opcode::PseudoVFMAX_ALT_VFPR16_M2_E16_MASK, + 2498 => Opcode::PseudoVFMAX_ALT_VFPR16_M4_E16, + 2499 => Opcode::PseudoVFMAX_ALT_VFPR16_M4_E16_MASK, + 2500 => Opcode::PseudoVFMAX_ALT_VFPR16_M8_E16, + 2501 => Opcode::PseudoVFMAX_ALT_VFPR16_M8_E16_MASK, + 2502 => Opcode::PseudoVFMAX_ALT_VFPR16_MF2_E16, + 2503 => Opcode::PseudoVFMAX_ALT_VFPR16_MF2_E16_MASK, + 2504 => Opcode::PseudoVFMAX_ALT_VFPR16_MF4_E16, + 2505 => Opcode::PseudoVFMAX_ALT_VFPR16_MF4_E16_MASK, + 2506 => Opcode::PseudoVFMAX_ALT_VV_M1_E16, + 2507 => Opcode::PseudoVFMAX_ALT_VV_M1_E16_MASK, + 2508 => Opcode::PseudoVFMAX_ALT_VV_M2_E16, + 2509 => Opcode::PseudoVFMAX_ALT_VV_M2_E16_MASK, + 2510 => Opcode::PseudoVFMAX_ALT_VV_M4_E16, + 2511 => Opcode::PseudoVFMAX_ALT_VV_M4_E16_MASK, + 2512 => Opcode::PseudoVFMAX_ALT_VV_M8_E16, + 2513 => Opcode::PseudoVFMAX_ALT_VV_M8_E16_MASK, + 2514 => Opcode::PseudoVFMAX_ALT_VV_MF2_E16, + 2515 => Opcode::PseudoVFMAX_ALT_VV_MF2_E16_MASK, + 2516 => Opcode::PseudoVFMAX_ALT_VV_MF4_E16, + 2517 => Opcode::PseudoVFMAX_ALT_VV_MF4_E16_MASK, + 2518 => Opcode::PseudoVFMAX_VFPR16_M1_E16, + 2519 => Opcode::PseudoVFMAX_VFPR16_M1_E16_MASK, + 2520 => Opcode::PseudoVFMAX_VFPR16_M2_E16, + 2521 => Opcode::PseudoVFMAX_VFPR16_M2_E16_MASK, + 2522 => Opcode::PseudoVFMAX_VFPR16_M4_E16, + 2523 => Opcode::PseudoVFMAX_VFPR16_M4_E16_MASK, + 2524 => Opcode::PseudoVFMAX_VFPR16_M8_E16, + 2525 => Opcode::PseudoVFMAX_VFPR16_M8_E16_MASK, + 2526 => Opcode::PseudoVFMAX_VFPR16_MF2_E16, + 2527 => Opcode::PseudoVFMAX_VFPR16_MF2_E16_MASK, + 2528 => Opcode::PseudoVFMAX_VFPR16_MF4_E16, + 2529 => Opcode::PseudoVFMAX_VFPR16_MF4_E16_MASK, + 2530 => Opcode::PseudoVFMAX_VFPR32_M1_E32, + 2531 => Opcode::PseudoVFMAX_VFPR32_M1_E32_MASK, + 2532 => Opcode::PseudoVFMAX_VFPR32_M2_E32, + 2533 => Opcode::PseudoVFMAX_VFPR32_M2_E32_MASK, + 2534 => Opcode::PseudoVFMAX_VFPR32_M4_E32, + 2535 => Opcode::PseudoVFMAX_VFPR32_M4_E32_MASK, + 2536 => Opcode::PseudoVFMAX_VFPR32_M8_E32, + 2537 => Opcode::PseudoVFMAX_VFPR32_M8_E32_MASK, + 2538 => Opcode::PseudoVFMAX_VFPR32_MF2_E32, + 2539 => Opcode::PseudoVFMAX_VFPR32_MF2_E32_MASK, + 2540 => Opcode::PseudoVFMAX_VFPR64_M1_E64, + 2541 => Opcode::PseudoVFMAX_VFPR64_M1_E64_MASK, + 2542 => Opcode::PseudoVFMAX_VFPR64_M2_E64, + 2543 => Opcode::PseudoVFMAX_VFPR64_M2_E64_MASK, + 2544 => Opcode::PseudoVFMAX_VFPR64_M4_E64, + 2545 => Opcode::PseudoVFMAX_VFPR64_M4_E64_MASK, + 2546 => Opcode::PseudoVFMAX_VFPR64_M8_E64, + 2547 => Opcode::PseudoVFMAX_VFPR64_M8_E64_MASK, + 2548 => Opcode::PseudoVFMAX_VV_M1_E16, + 2549 => Opcode::PseudoVFMAX_VV_M1_E16_MASK, + 2550 => Opcode::PseudoVFMAX_VV_M1_E32, + 2551 => Opcode::PseudoVFMAX_VV_M1_E32_MASK, + 2552 => Opcode::PseudoVFMAX_VV_M1_E64, + 2553 => Opcode::PseudoVFMAX_VV_M1_E64_MASK, + 2554 => Opcode::PseudoVFMAX_VV_M2_E16, + 2555 => Opcode::PseudoVFMAX_VV_M2_E16_MASK, + 2556 => Opcode::PseudoVFMAX_VV_M2_E32, + 2557 => Opcode::PseudoVFMAX_VV_M2_E32_MASK, + 2558 => Opcode::PseudoVFMAX_VV_M2_E64, + 2559 => Opcode::PseudoVFMAX_VV_M2_E64_MASK, + 2560 => Opcode::PseudoVFMAX_VV_M4_E16, + 2561 => Opcode::PseudoVFMAX_VV_M4_E16_MASK, + 2562 => Opcode::PseudoVFMAX_VV_M4_E32, + 2563 => Opcode::PseudoVFMAX_VV_M4_E32_MASK, + 2564 => Opcode::PseudoVFMAX_VV_M4_E64, + 2565 => Opcode::PseudoVFMAX_VV_M4_E64_MASK, + 2566 => Opcode::PseudoVFMAX_VV_M8_E16, + 2567 => Opcode::PseudoVFMAX_VV_M8_E16_MASK, + 2568 => Opcode::PseudoVFMAX_VV_M8_E32, + 2569 => Opcode::PseudoVFMAX_VV_M8_E32_MASK, + 2570 => Opcode::PseudoVFMAX_VV_M8_E64, + 2571 => Opcode::PseudoVFMAX_VV_M8_E64_MASK, + 2572 => Opcode::PseudoVFMAX_VV_MF2_E16, + 2573 => Opcode::PseudoVFMAX_VV_MF2_E16_MASK, + 2574 => Opcode::PseudoVFMAX_VV_MF2_E32, + 2575 => Opcode::PseudoVFMAX_VV_MF2_E32_MASK, + 2576 => Opcode::PseudoVFMAX_VV_MF4_E16, + 2577 => Opcode::PseudoVFMAX_VV_MF4_E16_MASK, + 2578 => Opcode::PseudoVFMERGE_ALT_VFPR16M_M1, + 2579 => Opcode::PseudoVFMERGE_ALT_VFPR16M_M2, + 2580 => Opcode::PseudoVFMERGE_ALT_VFPR16M_M4, + 2581 => Opcode::PseudoVFMERGE_ALT_VFPR16M_M8, + 2582 => Opcode::PseudoVFMERGE_ALT_VFPR16M_MF2, + 2583 => Opcode::PseudoVFMERGE_ALT_VFPR16M_MF4, + 2584 => Opcode::PseudoVFMERGE_ALT_VFPR32M_M1, + 2585 => Opcode::PseudoVFMERGE_ALT_VFPR32M_M2, + 2586 => Opcode::PseudoVFMERGE_ALT_VFPR32M_M4, + 2587 => Opcode::PseudoVFMERGE_ALT_VFPR32M_M8, + 2588 => Opcode::PseudoVFMERGE_ALT_VFPR32M_MF2, + 2589 => Opcode::PseudoVFMERGE_ALT_VFPR64M_M1, + 2590 => Opcode::PseudoVFMERGE_ALT_VFPR64M_M2, + 2591 => Opcode::PseudoVFMERGE_ALT_VFPR64M_M4, + 2592 => Opcode::PseudoVFMERGE_ALT_VFPR64M_M8, + 2593 => Opcode::PseudoVFMERGE_VFPR16M_M1, + 2594 => Opcode::PseudoVFMERGE_VFPR16M_M2, + 2595 => Opcode::PseudoVFMERGE_VFPR16M_M4, + 2596 => Opcode::PseudoVFMERGE_VFPR16M_M8, + 2597 => Opcode::PseudoVFMERGE_VFPR16M_MF2, + 2598 => Opcode::PseudoVFMERGE_VFPR16M_MF4, + 2599 => Opcode::PseudoVFMERGE_VFPR32M_M1, + 2600 => Opcode::PseudoVFMERGE_VFPR32M_M2, + 2601 => Opcode::PseudoVFMERGE_VFPR32M_M4, + 2602 => Opcode::PseudoVFMERGE_VFPR32M_M8, + 2603 => Opcode::PseudoVFMERGE_VFPR32M_MF2, + 2604 => Opcode::PseudoVFMERGE_VFPR64M_M1, + 2605 => Opcode::PseudoVFMERGE_VFPR64M_M2, + 2606 => Opcode::PseudoVFMERGE_VFPR64M_M4, + 2607 => Opcode::PseudoVFMERGE_VFPR64M_M8, + 2608 => Opcode::PseudoVFMIN_ALT_VFPR16_M1_E16, + 2609 => Opcode::PseudoVFMIN_ALT_VFPR16_M1_E16_MASK, + 2610 => Opcode::PseudoVFMIN_ALT_VFPR16_M2_E16, + 2611 => Opcode::PseudoVFMIN_ALT_VFPR16_M2_E16_MASK, + 2612 => Opcode::PseudoVFMIN_ALT_VFPR16_M4_E16, + 2613 => Opcode::PseudoVFMIN_ALT_VFPR16_M4_E16_MASK, + 2614 => Opcode::PseudoVFMIN_ALT_VFPR16_M8_E16, + 2615 => Opcode::PseudoVFMIN_ALT_VFPR16_M8_E16_MASK, + 2616 => Opcode::PseudoVFMIN_ALT_VFPR16_MF2_E16, + 2617 => Opcode::PseudoVFMIN_ALT_VFPR16_MF2_E16_MASK, + 2618 => Opcode::PseudoVFMIN_ALT_VFPR16_MF4_E16, + 2619 => Opcode::PseudoVFMIN_ALT_VFPR16_MF4_E16_MASK, + 2620 => Opcode::PseudoVFMIN_ALT_VV_M1_E16, + 2621 => Opcode::PseudoVFMIN_ALT_VV_M1_E16_MASK, + 2622 => Opcode::PseudoVFMIN_ALT_VV_M2_E16, + 2623 => Opcode::PseudoVFMIN_ALT_VV_M2_E16_MASK, + 2624 => Opcode::PseudoVFMIN_ALT_VV_M4_E16, + 2625 => Opcode::PseudoVFMIN_ALT_VV_M4_E16_MASK, + 2626 => Opcode::PseudoVFMIN_ALT_VV_M8_E16, + 2627 => Opcode::PseudoVFMIN_ALT_VV_M8_E16_MASK, + 2628 => Opcode::PseudoVFMIN_ALT_VV_MF2_E16, + 2629 => Opcode::PseudoVFMIN_ALT_VV_MF2_E16_MASK, + 2630 => Opcode::PseudoVFMIN_ALT_VV_MF4_E16, + 2631 => Opcode::PseudoVFMIN_ALT_VV_MF4_E16_MASK, + 2632 => Opcode::PseudoVFMIN_VFPR16_M1_E16, + 2633 => Opcode::PseudoVFMIN_VFPR16_M1_E16_MASK, + 2634 => Opcode::PseudoVFMIN_VFPR16_M2_E16, + 2635 => Opcode::PseudoVFMIN_VFPR16_M2_E16_MASK, + 2636 => Opcode::PseudoVFMIN_VFPR16_M4_E16, + 2637 => Opcode::PseudoVFMIN_VFPR16_M4_E16_MASK, + 2638 => Opcode::PseudoVFMIN_VFPR16_M8_E16, + 2639 => Opcode::PseudoVFMIN_VFPR16_M8_E16_MASK, + 2640 => Opcode::PseudoVFMIN_VFPR16_MF2_E16, + 2641 => Opcode::PseudoVFMIN_VFPR16_MF2_E16_MASK, + 2642 => Opcode::PseudoVFMIN_VFPR16_MF4_E16, + 2643 => Opcode::PseudoVFMIN_VFPR16_MF4_E16_MASK, + 2644 => Opcode::PseudoVFMIN_VFPR32_M1_E32, + 2645 => Opcode::PseudoVFMIN_VFPR32_M1_E32_MASK, + 2646 => Opcode::PseudoVFMIN_VFPR32_M2_E32, + 2647 => Opcode::PseudoVFMIN_VFPR32_M2_E32_MASK, + 2648 => Opcode::PseudoVFMIN_VFPR32_M4_E32, + 2649 => Opcode::PseudoVFMIN_VFPR32_M4_E32_MASK, + 2650 => Opcode::PseudoVFMIN_VFPR32_M8_E32, + 2651 => Opcode::PseudoVFMIN_VFPR32_M8_E32_MASK, + 2652 => Opcode::PseudoVFMIN_VFPR32_MF2_E32, + 2653 => Opcode::PseudoVFMIN_VFPR32_MF2_E32_MASK, + 2654 => Opcode::PseudoVFMIN_VFPR64_M1_E64, + 2655 => Opcode::PseudoVFMIN_VFPR64_M1_E64_MASK, + 2656 => Opcode::PseudoVFMIN_VFPR64_M2_E64, + 2657 => Opcode::PseudoVFMIN_VFPR64_M2_E64_MASK, + 2658 => Opcode::PseudoVFMIN_VFPR64_M4_E64, + 2659 => Opcode::PseudoVFMIN_VFPR64_M4_E64_MASK, + 2660 => Opcode::PseudoVFMIN_VFPR64_M8_E64, + 2661 => Opcode::PseudoVFMIN_VFPR64_M8_E64_MASK, + 2662 => Opcode::PseudoVFMIN_VV_M1_E16, + 2663 => Opcode::PseudoVFMIN_VV_M1_E16_MASK, + 2664 => Opcode::PseudoVFMIN_VV_M1_E32, + 2665 => Opcode::PseudoVFMIN_VV_M1_E32_MASK, + 2666 => Opcode::PseudoVFMIN_VV_M1_E64, + 2667 => Opcode::PseudoVFMIN_VV_M1_E64_MASK, + 2668 => Opcode::PseudoVFMIN_VV_M2_E16, + 2669 => Opcode::PseudoVFMIN_VV_M2_E16_MASK, + 2670 => Opcode::PseudoVFMIN_VV_M2_E32, + 2671 => Opcode::PseudoVFMIN_VV_M2_E32_MASK, + 2672 => Opcode::PseudoVFMIN_VV_M2_E64, + 2673 => Opcode::PseudoVFMIN_VV_M2_E64_MASK, + 2674 => Opcode::PseudoVFMIN_VV_M4_E16, + 2675 => Opcode::PseudoVFMIN_VV_M4_E16_MASK, + 2676 => Opcode::PseudoVFMIN_VV_M4_E32, + 2677 => Opcode::PseudoVFMIN_VV_M4_E32_MASK, + 2678 => Opcode::PseudoVFMIN_VV_M4_E64, + 2679 => Opcode::PseudoVFMIN_VV_M4_E64_MASK, + 2680 => Opcode::PseudoVFMIN_VV_M8_E16, + 2681 => Opcode::PseudoVFMIN_VV_M8_E16_MASK, + 2682 => Opcode::PseudoVFMIN_VV_M8_E32, + 2683 => Opcode::PseudoVFMIN_VV_M8_E32_MASK, + 2684 => Opcode::PseudoVFMIN_VV_M8_E64, + 2685 => Opcode::PseudoVFMIN_VV_M8_E64_MASK, + 2686 => Opcode::PseudoVFMIN_VV_MF2_E16, + 2687 => Opcode::PseudoVFMIN_VV_MF2_E16_MASK, + 2688 => Opcode::PseudoVFMIN_VV_MF2_E32, + 2689 => Opcode::PseudoVFMIN_VV_MF2_E32_MASK, + 2690 => Opcode::PseudoVFMIN_VV_MF4_E16, + 2691 => Opcode::PseudoVFMIN_VV_MF4_E16_MASK, + 2692 => Opcode::PseudoVFMSAC_ALT_VFPR16_M1_E16, + 2693 => Opcode::PseudoVFMSAC_ALT_VFPR16_M1_E16_MASK, + 2694 => Opcode::PseudoVFMSAC_ALT_VFPR16_M2_E16, + 2695 => Opcode::PseudoVFMSAC_ALT_VFPR16_M2_E16_MASK, + 2696 => Opcode::PseudoVFMSAC_ALT_VFPR16_M4_E16, + 2697 => Opcode::PseudoVFMSAC_ALT_VFPR16_M4_E16_MASK, + 2698 => Opcode::PseudoVFMSAC_ALT_VFPR16_M8_E16, + 2699 => Opcode::PseudoVFMSAC_ALT_VFPR16_M8_E16_MASK, + 2700 => Opcode::PseudoVFMSAC_ALT_VFPR16_MF2_E16, + 2701 => Opcode::PseudoVFMSAC_ALT_VFPR16_MF2_E16_MASK, + 2702 => Opcode::PseudoVFMSAC_ALT_VFPR16_MF4_E16, + 2703 => Opcode::PseudoVFMSAC_ALT_VFPR16_MF4_E16_MASK, + 2704 => Opcode::PseudoVFMSAC_ALT_VV_M1_E16, + 2705 => Opcode::PseudoVFMSAC_ALT_VV_M1_E16_MASK, + 2706 => Opcode::PseudoVFMSAC_ALT_VV_M2_E16, + 2707 => Opcode::PseudoVFMSAC_ALT_VV_M2_E16_MASK, + 2708 => Opcode::PseudoVFMSAC_ALT_VV_M4_E16, + 2709 => Opcode::PseudoVFMSAC_ALT_VV_M4_E16_MASK, + 2710 => Opcode::PseudoVFMSAC_ALT_VV_M8_E16, + 2711 => Opcode::PseudoVFMSAC_ALT_VV_M8_E16_MASK, + 2712 => Opcode::PseudoVFMSAC_ALT_VV_MF2_E16, + 2713 => Opcode::PseudoVFMSAC_ALT_VV_MF2_E16_MASK, + 2714 => Opcode::PseudoVFMSAC_ALT_VV_MF4_E16, + 2715 => Opcode::PseudoVFMSAC_ALT_VV_MF4_E16_MASK, + 2716 => Opcode::PseudoVFMSAC_VFPR16_M1_E16, + 2717 => Opcode::PseudoVFMSAC_VFPR16_M1_E16_MASK, + 2718 => Opcode::PseudoVFMSAC_VFPR16_M2_E16, + 2719 => Opcode::PseudoVFMSAC_VFPR16_M2_E16_MASK, + 2720 => Opcode::PseudoVFMSAC_VFPR16_M4_E16, + 2721 => Opcode::PseudoVFMSAC_VFPR16_M4_E16_MASK, + 2722 => Opcode::PseudoVFMSAC_VFPR16_M8_E16, + 2723 => Opcode::PseudoVFMSAC_VFPR16_M8_E16_MASK, + 2724 => Opcode::PseudoVFMSAC_VFPR16_MF2_E16, + 2725 => Opcode::PseudoVFMSAC_VFPR16_MF2_E16_MASK, + 2726 => Opcode::PseudoVFMSAC_VFPR16_MF4_E16, + 2727 => Opcode::PseudoVFMSAC_VFPR16_MF4_E16_MASK, + 2728 => Opcode::PseudoVFMSAC_VFPR32_M1_E32, + 2729 => Opcode::PseudoVFMSAC_VFPR32_M1_E32_MASK, + 2730 => Opcode::PseudoVFMSAC_VFPR32_M2_E32, + 2731 => Opcode::PseudoVFMSAC_VFPR32_M2_E32_MASK, + 2732 => Opcode::PseudoVFMSAC_VFPR32_M4_E32, + 2733 => Opcode::PseudoVFMSAC_VFPR32_M4_E32_MASK, + 2734 => Opcode::PseudoVFMSAC_VFPR32_M8_E32, + 2735 => Opcode::PseudoVFMSAC_VFPR32_M8_E32_MASK, + 2736 => Opcode::PseudoVFMSAC_VFPR32_MF2_E32, + 2737 => Opcode::PseudoVFMSAC_VFPR32_MF2_E32_MASK, + 2738 => Opcode::PseudoVFMSAC_VFPR64_M1_E64, + 2739 => Opcode::PseudoVFMSAC_VFPR64_M1_E64_MASK, + 2740 => Opcode::PseudoVFMSAC_VFPR64_M2_E64, + 2741 => Opcode::PseudoVFMSAC_VFPR64_M2_E64_MASK, + 2742 => Opcode::PseudoVFMSAC_VFPR64_M4_E64, + 2743 => Opcode::PseudoVFMSAC_VFPR64_M4_E64_MASK, + 2744 => Opcode::PseudoVFMSAC_VFPR64_M8_E64, + 2745 => Opcode::PseudoVFMSAC_VFPR64_M8_E64_MASK, + 2746 => Opcode::PseudoVFMSAC_VV_M1_E16, + 2747 => Opcode::PseudoVFMSAC_VV_M1_E16_MASK, + 2748 => Opcode::PseudoVFMSAC_VV_M1_E32, + 2749 => Opcode::PseudoVFMSAC_VV_M1_E32_MASK, + 2750 => Opcode::PseudoVFMSAC_VV_M1_E64, + 2751 => Opcode::PseudoVFMSAC_VV_M1_E64_MASK, + 2752 => Opcode::PseudoVFMSAC_VV_M2_E16, + 2753 => Opcode::PseudoVFMSAC_VV_M2_E16_MASK, + 2754 => Opcode::PseudoVFMSAC_VV_M2_E32, + 2755 => Opcode::PseudoVFMSAC_VV_M2_E32_MASK, + 2756 => Opcode::PseudoVFMSAC_VV_M2_E64, + 2757 => Opcode::PseudoVFMSAC_VV_M2_E64_MASK, + 2758 => Opcode::PseudoVFMSAC_VV_M4_E16, + 2759 => Opcode::PseudoVFMSAC_VV_M4_E16_MASK, + 2760 => Opcode::PseudoVFMSAC_VV_M4_E32, + 2761 => Opcode::PseudoVFMSAC_VV_M4_E32_MASK, + 2762 => Opcode::PseudoVFMSAC_VV_M4_E64, + 2763 => Opcode::PseudoVFMSAC_VV_M4_E64_MASK, + 2764 => Opcode::PseudoVFMSAC_VV_M8_E16, + 2765 => Opcode::PseudoVFMSAC_VV_M8_E16_MASK, + 2766 => Opcode::PseudoVFMSAC_VV_M8_E32, + 2767 => Opcode::PseudoVFMSAC_VV_M8_E32_MASK, + 2768 => Opcode::PseudoVFMSAC_VV_M8_E64, + 2769 => Opcode::PseudoVFMSAC_VV_M8_E64_MASK, + 2770 => Opcode::PseudoVFMSAC_VV_MF2_E16, + 2771 => Opcode::PseudoVFMSAC_VV_MF2_E16_MASK, + 2772 => Opcode::PseudoVFMSAC_VV_MF2_E32, + 2773 => Opcode::PseudoVFMSAC_VV_MF2_E32_MASK, + 2774 => Opcode::PseudoVFMSAC_VV_MF4_E16, + 2775 => Opcode::PseudoVFMSAC_VV_MF4_E16_MASK, + 2776 => Opcode::PseudoVFMSUB_ALT_VFPR16_M1_E16, + 2777 => Opcode::PseudoVFMSUB_ALT_VFPR16_M1_E16_MASK, + 2778 => Opcode::PseudoVFMSUB_ALT_VFPR16_M2_E16, + 2779 => Opcode::PseudoVFMSUB_ALT_VFPR16_M2_E16_MASK, + 2780 => Opcode::PseudoVFMSUB_ALT_VFPR16_M4_E16, + 2781 => Opcode::PseudoVFMSUB_ALT_VFPR16_M4_E16_MASK, + 2782 => Opcode::PseudoVFMSUB_ALT_VFPR16_M8_E16, + 2783 => Opcode::PseudoVFMSUB_ALT_VFPR16_M8_E16_MASK, + 2784 => Opcode::PseudoVFMSUB_ALT_VFPR16_MF2_E16, + 2785 => Opcode::PseudoVFMSUB_ALT_VFPR16_MF2_E16_MASK, + 2786 => Opcode::PseudoVFMSUB_ALT_VFPR16_MF4_E16, + 2787 => Opcode::PseudoVFMSUB_ALT_VFPR16_MF4_E16_MASK, + 2788 => Opcode::PseudoVFMSUB_ALT_VV_M1_E16, + 2789 => Opcode::PseudoVFMSUB_ALT_VV_M1_E16_MASK, + 2790 => Opcode::PseudoVFMSUB_ALT_VV_M2_E16, + 2791 => Opcode::PseudoVFMSUB_ALT_VV_M2_E16_MASK, + 2792 => Opcode::PseudoVFMSUB_ALT_VV_M4_E16, + 2793 => Opcode::PseudoVFMSUB_ALT_VV_M4_E16_MASK, + 2794 => Opcode::PseudoVFMSUB_ALT_VV_M8_E16, + 2795 => Opcode::PseudoVFMSUB_ALT_VV_M8_E16_MASK, + 2796 => Opcode::PseudoVFMSUB_ALT_VV_MF2_E16, + 2797 => Opcode::PseudoVFMSUB_ALT_VV_MF2_E16_MASK, + 2798 => Opcode::PseudoVFMSUB_ALT_VV_MF4_E16, + 2799 => Opcode::PseudoVFMSUB_ALT_VV_MF4_E16_MASK, + 2800 => Opcode::PseudoVFMSUB_VFPR16_M1_E16, + 2801 => Opcode::PseudoVFMSUB_VFPR16_M1_E16_MASK, + 2802 => Opcode::PseudoVFMSUB_VFPR16_M2_E16, + 2803 => Opcode::PseudoVFMSUB_VFPR16_M2_E16_MASK, + 2804 => Opcode::PseudoVFMSUB_VFPR16_M4_E16, + 2805 => Opcode::PseudoVFMSUB_VFPR16_M4_E16_MASK, + 2806 => Opcode::PseudoVFMSUB_VFPR16_M8_E16, + 2807 => Opcode::PseudoVFMSUB_VFPR16_M8_E16_MASK, + 2808 => Opcode::PseudoVFMSUB_VFPR16_MF2_E16, + 2809 => Opcode::PseudoVFMSUB_VFPR16_MF2_E16_MASK, + 2810 => Opcode::PseudoVFMSUB_VFPR16_MF4_E16, + 2811 => Opcode::PseudoVFMSUB_VFPR16_MF4_E16_MASK, + 2812 => Opcode::PseudoVFMSUB_VFPR32_M1_E32, + 2813 => Opcode::PseudoVFMSUB_VFPR32_M1_E32_MASK, + 2814 => Opcode::PseudoVFMSUB_VFPR32_M2_E32, + 2815 => Opcode::PseudoVFMSUB_VFPR32_M2_E32_MASK, + 2816 => Opcode::PseudoVFMSUB_VFPR32_M4_E32, + 2817 => Opcode::PseudoVFMSUB_VFPR32_M4_E32_MASK, + 2818 => Opcode::PseudoVFMSUB_VFPR32_M8_E32, + 2819 => Opcode::PseudoVFMSUB_VFPR32_M8_E32_MASK, + 2820 => Opcode::PseudoVFMSUB_VFPR32_MF2_E32, + 2821 => Opcode::PseudoVFMSUB_VFPR32_MF2_E32_MASK, + 2822 => Opcode::PseudoVFMSUB_VFPR64_M1_E64, + 2823 => Opcode::PseudoVFMSUB_VFPR64_M1_E64_MASK, + 2824 => Opcode::PseudoVFMSUB_VFPR64_M2_E64, + 2825 => Opcode::PseudoVFMSUB_VFPR64_M2_E64_MASK, + 2826 => Opcode::PseudoVFMSUB_VFPR64_M4_E64, + 2827 => Opcode::PseudoVFMSUB_VFPR64_M4_E64_MASK, + 2828 => Opcode::PseudoVFMSUB_VFPR64_M8_E64, + 2829 => Opcode::PseudoVFMSUB_VFPR64_M8_E64_MASK, + 2830 => Opcode::PseudoVFMSUB_VV_M1_E16, + 2831 => Opcode::PseudoVFMSUB_VV_M1_E16_MASK, + 2832 => Opcode::PseudoVFMSUB_VV_M1_E32, + 2833 => Opcode::PseudoVFMSUB_VV_M1_E32_MASK, + 2834 => Opcode::PseudoVFMSUB_VV_M1_E64, + 2835 => Opcode::PseudoVFMSUB_VV_M1_E64_MASK, + 2836 => Opcode::PseudoVFMSUB_VV_M2_E16, + 2837 => Opcode::PseudoVFMSUB_VV_M2_E16_MASK, + 2838 => Opcode::PseudoVFMSUB_VV_M2_E32, + 2839 => Opcode::PseudoVFMSUB_VV_M2_E32_MASK, + 2840 => Opcode::PseudoVFMSUB_VV_M2_E64, + 2841 => Opcode::PseudoVFMSUB_VV_M2_E64_MASK, + 2842 => Opcode::PseudoVFMSUB_VV_M4_E16, + 2843 => Opcode::PseudoVFMSUB_VV_M4_E16_MASK, + 2844 => Opcode::PseudoVFMSUB_VV_M4_E32, + 2845 => Opcode::PseudoVFMSUB_VV_M4_E32_MASK, + 2846 => Opcode::PseudoVFMSUB_VV_M4_E64, + 2847 => Opcode::PseudoVFMSUB_VV_M4_E64_MASK, + 2848 => Opcode::PseudoVFMSUB_VV_M8_E16, + 2849 => Opcode::PseudoVFMSUB_VV_M8_E16_MASK, + 2850 => Opcode::PseudoVFMSUB_VV_M8_E32, + 2851 => Opcode::PseudoVFMSUB_VV_M8_E32_MASK, + 2852 => Opcode::PseudoVFMSUB_VV_M8_E64, + 2853 => Opcode::PseudoVFMSUB_VV_M8_E64_MASK, + 2854 => Opcode::PseudoVFMSUB_VV_MF2_E16, + 2855 => Opcode::PseudoVFMSUB_VV_MF2_E16_MASK, + 2856 => Opcode::PseudoVFMSUB_VV_MF2_E32, + 2857 => Opcode::PseudoVFMSUB_VV_MF2_E32_MASK, + 2858 => Opcode::PseudoVFMSUB_VV_MF4_E16, + 2859 => Opcode::PseudoVFMSUB_VV_MF4_E16_MASK, + 2860 => Opcode::PseudoVFMUL_ALT_VFPR16_M1_E16, + 2861 => Opcode::PseudoVFMUL_ALT_VFPR16_M1_E16_MASK, + 2862 => Opcode::PseudoVFMUL_ALT_VFPR16_M2_E16, + 2863 => Opcode::PseudoVFMUL_ALT_VFPR16_M2_E16_MASK, + 2864 => Opcode::PseudoVFMUL_ALT_VFPR16_M4_E16, + 2865 => Opcode::PseudoVFMUL_ALT_VFPR16_M4_E16_MASK, + 2866 => Opcode::PseudoVFMUL_ALT_VFPR16_M8_E16, + 2867 => Opcode::PseudoVFMUL_ALT_VFPR16_M8_E16_MASK, + 2868 => Opcode::PseudoVFMUL_ALT_VFPR16_MF2_E16, + 2869 => Opcode::PseudoVFMUL_ALT_VFPR16_MF2_E16_MASK, + 2870 => Opcode::PseudoVFMUL_ALT_VFPR16_MF4_E16, + 2871 => Opcode::PseudoVFMUL_ALT_VFPR16_MF4_E16_MASK, + 2872 => Opcode::PseudoVFMUL_ALT_VV_M1_E16, + 2873 => Opcode::PseudoVFMUL_ALT_VV_M1_E16_MASK, + 2874 => Opcode::PseudoVFMUL_ALT_VV_M2_E16, + 2875 => Opcode::PseudoVFMUL_ALT_VV_M2_E16_MASK, + 2876 => Opcode::PseudoVFMUL_ALT_VV_M4_E16, + 2877 => Opcode::PseudoVFMUL_ALT_VV_M4_E16_MASK, + 2878 => Opcode::PseudoVFMUL_ALT_VV_M8_E16, + 2879 => Opcode::PseudoVFMUL_ALT_VV_M8_E16_MASK, + 2880 => Opcode::PseudoVFMUL_ALT_VV_MF2_E16, + 2881 => Opcode::PseudoVFMUL_ALT_VV_MF2_E16_MASK, + 2882 => Opcode::PseudoVFMUL_ALT_VV_MF4_E16, + 2883 => Opcode::PseudoVFMUL_ALT_VV_MF4_E16_MASK, + 2884 => Opcode::PseudoVFMUL_VFPR16_M1_E16, + 2885 => Opcode::PseudoVFMUL_VFPR16_M1_E16_MASK, + 2886 => Opcode::PseudoVFMUL_VFPR16_M2_E16, + 2887 => Opcode::PseudoVFMUL_VFPR16_M2_E16_MASK, + 2888 => Opcode::PseudoVFMUL_VFPR16_M4_E16, + 2889 => Opcode::PseudoVFMUL_VFPR16_M4_E16_MASK, + 2890 => Opcode::PseudoVFMUL_VFPR16_M8_E16, + 2891 => Opcode::PseudoVFMUL_VFPR16_M8_E16_MASK, + 2892 => Opcode::PseudoVFMUL_VFPR16_MF2_E16, + 2893 => Opcode::PseudoVFMUL_VFPR16_MF2_E16_MASK, + 2894 => Opcode::PseudoVFMUL_VFPR16_MF4_E16, + 2895 => Opcode::PseudoVFMUL_VFPR16_MF4_E16_MASK, + 2896 => Opcode::PseudoVFMUL_VFPR32_M1_E32, + 2897 => Opcode::PseudoVFMUL_VFPR32_M1_E32_MASK, + 2898 => Opcode::PseudoVFMUL_VFPR32_M2_E32, + 2899 => Opcode::PseudoVFMUL_VFPR32_M2_E32_MASK, + 2900 => Opcode::PseudoVFMUL_VFPR32_M4_E32, + 2901 => Opcode::PseudoVFMUL_VFPR32_M4_E32_MASK, + 2902 => Opcode::PseudoVFMUL_VFPR32_M8_E32, + 2903 => Opcode::PseudoVFMUL_VFPR32_M8_E32_MASK, + 2904 => Opcode::PseudoVFMUL_VFPR32_MF2_E32, + 2905 => Opcode::PseudoVFMUL_VFPR32_MF2_E32_MASK, + 2906 => Opcode::PseudoVFMUL_VFPR64_M1_E64, + 2907 => Opcode::PseudoVFMUL_VFPR64_M1_E64_MASK, + 2908 => Opcode::PseudoVFMUL_VFPR64_M2_E64, + 2909 => Opcode::PseudoVFMUL_VFPR64_M2_E64_MASK, + 2910 => Opcode::PseudoVFMUL_VFPR64_M4_E64, + 2911 => Opcode::PseudoVFMUL_VFPR64_M4_E64_MASK, + 2912 => Opcode::PseudoVFMUL_VFPR64_M8_E64, + 2913 => Opcode::PseudoVFMUL_VFPR64_M8_E64_MASK, + 2914 => Opcode::PseudoVFMUL_VV_M1_E16, + 2915 => Opcode::PseudoVFMUL_VV_M1_E16_MASK, + 2916 => Opcode::PseudoVFMUL_VV_M1_E32, + 2917 => Opcode::PseudoVFMUL_VV_M1_E32_MASK, + 2918 => Opcode::PseudoVFMUL_VV_M1_E64, + 2919 => Opcode::PseudoVFMUL_VV_M1_E64_MASK, + 2920 => Opcode::PseudoVFMUL_VV_M2_E16, + 2921 => Opcode::PseudoVFMUL_VV_M2_E16_MASK, + 2922 => Opcode::PseudoVFMUL_VV_M2_E32, + 2923 => Opcode::PseudoVFMUL_VV_M2_E32_MASK, + 2924 => Opcode::PseudoVFMUL_VV_M2_E64, + 2925 => Opcode::PseudoVFMUL_VV_M2_E64_MASK, + 2926 => Opcode::PseudoVFMUL_VV_M4_E16, + 2927 => Opcode::PseudoVFMUL_VV_M4_E16_MASK, + 2928 => Opcode::PseudoVFMUL_VV_M4_E32, + 2929 => Opcode::PseudoVFMUL_VV_M4_E32_MASK, + 2930 => Opcode::PseudoVFMUL_VV_M4_E64, + 2931 => Opcode::PseudoVFMUL_VV_M4_E64_MASK, + 2932 => Opcode::PseudoVFMUL_VV_M8_E16, + 2933 => Opcode::PseudoVFMUL_VV_M8_E16_MASK, + 2934 => Opcode::PseudoVFMUL_VV_M8_E32, + 2935 => Opcode::PseudoVFMUL_VV_M8_E32_MASK, + 2936 => Opcode::PseudoVFMUL_VV_M8_E64, + 2937 => Opcode::PseudoVFMUL_VV_M8_E64_MASK, + 2938 => Opcode::PseudoVFMUL_VV_MF2_E16, + 2939 => Opcode::PseudoVFMUL_VV_MF2_E16_MASK, + 2940 => Opcode::PseudoVFMUL_VV_MF2_E32, + 2941 => Opcode::PseudoVFMUL_VV_MF2_E32_MASK, + 2942 => Opcode::PseudoVFMUL_VV_MF4_E16, + 2943 => Opcode::PseudoVFMUL_VV_MF4_E16_MASK, + 2944 => Opcode::PseudoVFMV_FPR16_S, + 2945 => Opcode::PseudoVFMV_FPR16_S_ALT, + 2946 => Opcode::PseudoVFMV_FPR32_S, + 2947 => Opcode::PseudoVFMV_FPR64_S, + 2948 => Opcode::PseudoVFMV_S_FPR16, + 2949 => Opcode::PseudoVFMV_S_FPR16_ALT, + 2950 => Opcode::PseudoVFMV_S_FPR32, + 2951 => Opcode::PseudoVFMV_S_FPR64, + 2952 => Opcode::PseudoVFMV_V_ALT_FPR16_M1, + 2953 => Opcode::PseudoVFMV_V_ALT_FPR16_M2, + 2954 => Opcode::PseudoVFMV_V_ALT_FPR16_M4, + 2955 => Opcode::PseudoVFMV_V_ALT_FPR16_M8, + 2956 => Opcode::PseudoVFMV_V_ALT_FPR16_MF2, + 2957 => Opcode::PseudoVFMV_V_ALT_FPR16_MF4, + 2958 => Opcode::PseudoVFMV_V_ALT_FPR32_M1, + 2959 => Opcode::PseudoVFMV_V_ALT_FPR32_M2, + 2960 => Opcode::PseudoVFMV_V_ALT_FPR32_M4, + 2961 => Opcode::PseudoVFMV_V_ALT_FPR32_M8, + 2962 => Opcode::PseudoVFMV_V_ALT_FPR32_MF2, + 2963 => Opcode::PseudoVFMV_V_ALT_FPR64_M1, + 2964 => Opcode::PseudoVFMV_V_ALT_FPR64_M2, + 2965 => Opcode::PseudoVFMV_V_ALT_FPR64_M4, + 2966 => Opcode::PseudoVFMV_V_ALT_FPR64_M8, + 2967 => Opcode::PseudoVFMV_V_FPR16_M1, + 2968 => Opcode::PseudoVFMV_V_FPR16_M2, + 2969 => Opcode::PseudoVFMV_V_FPR16_M4, + 2970 => Opcode::PseudoVFMV_V_FPR16_M8, + 2971 => Opcode::PseudoVFMV_V_FPR16_MF2, + 2972 => Opcode::PseudoVFMV_V_FPR16_MF4, + 2973 => Opcode::PseudoVFMV_V_FPR32_M1, + 2974 => Opcode::PseudoVFMV_V_FPR32_M2, + 2975 => Opcode::PseudoVFMV_V_FPR32_M4, + 2976 => Opcode::PseudoVFMV_V_FPR32_M8, + 2977 => Opcode::PseudoVFMV_V_FPR32_MF2, + 2978 => Opcode::PseudoVFMV_V_FPR64_M1, + 2979 => Opcode::PseudoVFMV_V_FPR64_M2, + 2980 => Opcode::PseudoVFMV_V_FPR64_M4, + 2981 => Opcode::PseudoVFMV_V_FPR64_M8, + 2982 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M1_E8, + 2983 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M1_E8_MASK, + 2984 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M2_E8, + 2985 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M2_E8_MASK, + 2986 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M4_E8, + 2987 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_M4_E8_MASK, + 2988 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8, + 2989 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF2_E8_MASK, + 2990 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8, + 2991 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF4_E8_MASK, + 2992 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8, + 2993 => Opcode::PseudoVFNCVTBF16_F_F_ALT_W_MF8_E8_MASK, + 2994 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E16, + 2995 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, + 2996 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E32, + 2997 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, + 2998 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E8, + 2999 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E8_MASK, + 3000 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E16, + 3001 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, + 3002 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E32, + 3003 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, + 3004 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E8, + 3005 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E8_MASK, + 3006 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E16, + 3007 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, + 3008 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E32, + 3009 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, + 3010 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E8, + 3011 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E8_MASK, + 3012 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E16, + 3013 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, + 3014 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E32, + 3015 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, + 3016 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E8, + 3017 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E8_MASK, + 3018 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E16, + 3019 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, + 3020 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E8, + 3021 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E8_MASK, + 3022 => Opcode::PseudoVFNCVTBF16_F_F_W_MF8_E8, + 3023 => Opcode::PseudoVFNCVTBF16_F_F_W_MF8_E8_MASK, + 3024 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8, + 3025 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M1_E8_MASK, + 3026 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8, + 3027 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M2_E8_MASK, + 3028 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8, + 3029 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_M4_E8_MASK, + 3030 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8, + 3031 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF2_E8_MASK, + 3032 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8, + 3033 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF4_E8_MASK, + 3034 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8, + 3035 => Opcode::PseudoVFNCVTBF16_SAT_F_F_ALT_W_MF8_E8_MASK, + 3036 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M1_E8, + 3037 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M1_E8_MASK, + 3038 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M2_E8, + 3039 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M2_E8_MASK, + 3040 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M4_E8, + 3041 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_M4_E8_MASK, + 3042 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8, + 3043 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF2_E8_MASK, + 3044 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8, + 3045 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF4_E8_MASK, + 3046 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8, + 3047 => Opcode::PseudoVFNCVTBF16_SAT_F_F_W_MF8_E8_MASK, + 3048 => Opcode::PseudoVFNCVT_F_F_ALT_Q_M1_E8, + 3049 => Opcode::PseudoVFNCVT_F_F_ALT_Q_M1_E8_MASK, + 3050 => Opcode::PseudoVFNCVT_F_F_ALT_Q_M2_E8, + 3051 => Opcode::PseudoVFNCVT_F_F_ALT_Q_M2_E8_MASK, + 3052 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF2_E8, + 3053 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF2_E8_MASK, + 3054 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF4_E8, + 3055 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF4_E8_MASK, + 3056 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF8_E8, + 3057 => Opcode::PseudoVFNCVT_F_F_ALT_Q_MF8_E8_MASK, + 3058 => Opcode::PseudoVFNCVT_F_F_ALT_W_M1_E16, + 3059 => Opcode::PseudoVFNCVT_F_F_ALT_W_M1_E16_MASK, + 3060 => Opcode::PseudoVFNCVT_F_F_ALT_W_M2_E16, + 3061 => Opcode::PseudoVFNCVT_F_F_ALT_W_M2_E16_MASK, + 3062 => Opcode::PseudoVFNCVT_F_F_ALT_W_M4_E16, + 3063 => Opcode::PseudoVFNCVT_F_F_ALT_W_M4_E16_MASK, + 3064 => Opcode::PseudoVFNCVT_F_F_ALT_W_MF2_E16, + 3065 => Opcode::PseudoVFNCVT_F_F_ALT_W_MF2_E16_MASK, + 3066 => Opcode::PseudoVFNCVT_F_F_ALT_W_MF4_E16, + 3067 => Opcode::PseudoVFNCVT_F_F_ALT_W_MF4_E16_MASK, + 3068 => Opcode::PseudoVFNCVT_F_F_Q_M1_E8, + 3069 => Opcode::PseudoVFNCVT_F_F_Q_M1_E8_MASK, + 3070 => Opcode::PseudoVFNCVT_F_F_Q_M2_E8, + 3071 => Opcode::PseudoVFNCVT_F_F_Q_M2_E8_MASK, + 3072 => Opcode::PseudoVFNCVT_F_F_Q_MF2_E8, + 3073 => Opcode::PseudoVFNCVT_F_F_Q_MF2_E8_MASK, + 3074 => Opcode::PseudoVFNCVT_F_F_Q_MF4_E8, + 3075 => Opcode::PseudoVFNCVT_F_F_Q_MF4_E8_MASK, + 3076 => Opcode::PseudoVFNCVT_F_F_Q_MF8_E8, + 3077 => Opcode::PseudoVFNCVT_F_F_Q_MF8_E8_MASK, + 3078 => Opcode::PseudoVFNCVT_F_F_W_M1_E16, + 3079 => Opcode::PseudoVFNCVT_F_F_W_M1_E16_MASK, + 3080 => Opcode::PseudoVFNCVT_F_F_W_M1_E32, + 3081 => Opcode::PseudoVFNCVT_F_F_W_M1_E32_MASK, + 3082 => Opcode::PseudoVFNCVT_F_F_W_M2_E16, + 3083 => Opcode::PseudoVFNCVT_F_F_W_M2_E16_MASK, + 3084 => Opcode::PseudoVFNCVT_F_F_W_M2_E32, + 3085 => Opcode::PseudoVFNCVT_F_F_W_M2_E32_MASK, + 3086 => Opcode::PseudoVFNCVT_F_F_W_M4_E16, + 3087 => Opcode::PseudoVFNCVT_F_F_W_M4_E16_MASK, + 3088 => Opcode::PseudoVFNCVT_F_F_W_M4_E32, + 3089 => Opcode::PseudoVFNCVT_F_F_W_M4_E32_MASK, + 3090 => Opcode::PseudoVFNCVT_F_F_W_MF2_E16, + 3091 => Opcode::PseudoVFNCVT_F_F_W_MF2_E16_MASK, + 3092 => Opcode::PseudoVFNCVT_F_F_W_MF2_E32, + 3093 => Opcode::PseudoVFNCVT_F_F_W_MF2_E32_MASK, + 3094 => Opcode::PseudoVFNCVT_F_F_W_MF4_E16, + 3095 => Opcode::PseudoVFNCVT_F_F_W_MF4_E16_MASK, + 3096 => Opcode::PseudoVFNCVT_F_XU_W_M1_E16, + 3097 => Opcode::PseudoVFNCVT_F_XU_W_M1_E16_MASK, + 3098 => Opcode::PseudoVFNCVT_F_XU_W_M1_E32, + 3099 => Opcode::PseudoVFNCVT_F_XU_W_M1_E32_MASK, + 3100 => Opcode::PseudoVFNCVT_F_XU_W_M2_E16, + 3101 => Opcode::PseudoVFNCVT_F_XU_W_M2_E16_MASK, + 3102 => Opcode::PseudoVFNCVT_F_XU_W_M2_E32, + 3103 => Opcode::PseudoVFNCVT_F_XU_W_M2_E32_MASK, + 3104 => Opcode::PseudoVFNCVT_F_XU_W_M4_E16, + 3105 => Opcode::PseudoVFNCVT_F_XU_W_M4_E16_MASK, + 3106 => Opcode::PseudoVFNCVT_F_XU_W_M4_E32, + 3107 => Opcode::PseudoVFNCVT_F_XU_W_M4_E32_MASK, + 3108 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E16, + 3109 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E16_MASK, + 3110 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E32, + 3111 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E32_MASK, + 3112 => Opcode::PseudoVFNCVT_F_XU_W_MF4_E16, + 3113 => Opcode::PseudoVFNCVT_F_XU_W_MF4_E16_MASK, + 3114 => Opcode::PseudoVFNCVT_F_X_W_M1_E16, + 3115 => Opcode::PseudoVFNCVT_F_X_W_M1_E16_MASK, + 3116 => Opcode::PseudoVFNCVT_F_X_W_M1_E32, + 3117 => Opcode::PseudoVFNCVT_F_X_W_M1_E32_MASK, + 3118 => Opcode::PseudoVFNCVT_F_X_W_M2_E16, + 3119 => Opcode::PseudoVFNCVT_F_X_W_M2_E16_MASK, + 3120 => Opcode::PseudoVFNCVT_F_X_W_M2_E32, + 3121 => Opcode::PseudoVFNCVT_F_X_W_M2_E32_MASK, + 3122 => Opcode::PseudoVFNCVT_F_X_W_M4_E16, + 3123 => Opcode::PseudoVFNCVT_F_X_W_M4_E16_MASK, + 3124 => Opcode::PseudoVFNCVT_F_X_W_M4_E32, + 3125 => Opcode::PseudoVFNCVT_F_X_W_M4_E32_MASK, + 3126 => Opcode::PseudoVFNCVT_F_X_W_MF2_E16, + 3127 => Opcode::PseudoVFNCVT_F_X_W_MF2_E16_MASK, + 3128 => Opcode::PseudoVFNCVT_F_X_W_MF2_E32, + 3129 => Opcode::PseudoVFNCVT_F_X_W_MF2_E32_MASK, + 3130 => Opcode::PseudoVFNCVT_F_X_W_MF4_E16, + 3131 => Opcode::PseudoVFNCVT_F_X_W_MF4_E16_MASK, + 3132 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16, + 3133 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M1_E16_MASK, + 3134 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16, + 3135 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M2_E16_MASK, + 3136 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16, + 3137 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_M4_E16_MASK, + 3138 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16, + 3139 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_MF2_E16_MASK, + 3140 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16, + 3141 => Opcode::PseudoVFNCVT_ROD_F_F_ALT_W_MF4_E16_MASK, + 3142 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E16, + 3143 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, + 3144 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E32, + 3145 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, + 3146 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E16, + 3147 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, + 3148 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E32, + 3149 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, + 3150 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E16, + 3151 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, + 3152 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E32, + 3153 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, + 3154 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E16, + 3155 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, + 3156 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E32, + 3157 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, + 3158 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF4_E16, + 3159 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, + 3160 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M1, + 3161 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M1_MASK, + 3162 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M2, + 3163 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M2_MASK, + 3164 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M4, + 3165 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_M4_MASK, + 3166 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2, + 3167 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF2_MASK, + 3168 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4, + 3169 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF4_MASK, + 3170 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8, + 3171 => Opcode::PseudoVFNCVT_RTZ_XU_F_ALT_W_MF8_MASK, + 3172 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M1, + 3173 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, + 3174 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M2, + 3175 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, + 3176 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M4, + 3177 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, + 3178 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF2, + 3179 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, + 3180 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF4, + 3181 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, + 3182 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF8, + 3183 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, + 3184 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M1, + 3185 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M1_MASK, + 3186 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M2, + 3187 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M2_MASK, + 3188 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M4, + 3189 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_M4_MASK, + 3190 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF2, + 3191 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF2_MASK, + 3192 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF4, + 3193 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF4_MASK, + 3194 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF8, + 3195 => Opcode::PseudoVFNCVT_RTZ_X_F_ALT_W_MF8_MASK, + 3196 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M1, + 3197 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M1_MASK, + 3198 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M2, + 3199 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M2_MASK, + 3200 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M4, + 3201 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M4_MASK, + 3202 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF2, + 3203 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, + 3204 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF4, + 3205 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, + 3206 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF8, + 3207 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, + 3208 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8, + 3209 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_M1_E8_MASK, + 3210 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8, + 3211 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_M2_E8_MASK, + 3212 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8, + 3213 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF2_E8_MASK, + 3214 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8, + 3215 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF4_E8_MASK, + 3216 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8, + 3217 => Opcode::PseudoVFNCVT_SAT_F_F_ALT_Q_MF8_E8_MASK, + 3218 => Opcode::PseudoVFNCVT_SAT_F_F_Q_M1_E8, + 3219 => Opcode::PseudoVFNCVT_SAT_F_F_Q_M1_E8_MASK, + 3220 => Opcode::PseudoVFNCVT_SAT_F_F_Q_M2_E8, + 3221 => Opcode::PseudoVFNCVT_SAT_F_F_Q_M2_E8_MASK, + 3222 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF2_E8, + 3223 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF2_E8_MASK, + 3224 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF4_E8, + 3225 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF4_E8_MASK, + 3226 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF8_E8, + 3227 => Opcode::PseudoVFNCVT_SAT_F_F_Q_MF8_E8_MASK, + 3228 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M1, + 3229 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M1_MASK, + 3230 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M2, + 3231 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M2_MASK, + 3232 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M4, + 3233 => Opcode::PseudoVFNCVT_XU_F_ALT_W_M4_MASK, + 3234 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF2, + 3235 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF2_MASK, + 3236 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF4, + 3237 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF4_MASK, + 3238 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF8, + 3239 => Opcode::PseudoVFNCVT_XU_F_ALT_W_MF8_MASK, + 3240 => Opcode::PseudoVFNCVT_XU_F_W_M1, + 3241 => Opcode::PseudoVFNCVT_XU_F_W_M1_MASK, + 3242 => Opcode::PseudoVFNCVT_XU_F_W_M2, + 3243 => Opcode::PseudoVFNCVT_XU_F_W_M2_MASK, + 3244 => Opcode::PseudoVFNCVT_XU_F_W_M4, + 3245 => Opcode::PseudoVFNCVT_XU_F_W_M4_MASK, + 3246 => Opcode::PseudoVFNCVT_XU_F_W_MF2, + 3247 => Opcode::PseudoVFNCVT_XU_F_W_MF2_MASK, + 3248 => Opcode::PseudoVFNCVT_XU_F_W_MF4, + 3249 => Opcode::PseudoVFNCVT_XU_F_W_MF4_MASK, + 3250 => Opcode::PseudoVFNCVT_XU_F_W_MF8, + 3251 => Opcode::PseudoVFNCVT_XU_F_W_MF8_MASK, + 3252 => Opcode::PseudoVFNCVT_X_F_ALT_W_M1, + 3253 => Opcode::PseudoVFNCVT_X_F_ALT_W_M1_MASK, + 3254 => Opcode::PseudoVFNCVT_X_F_ALT_W_M2, + 3255 => Opcode::PseudoVFNCVT_X_F_ALT_W_M2_MASK, + 3256 => Opcode::PseudoVFNCVT_X_F_ALT_W_M4, + 3257 => Opcode::PseudoVFNCVT_X_F_ALT_W_M4_MASK, + 3258 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF2, + 3259 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF2_MASK, + 3260 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF4, + 3261 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF4_MASK, + 3262 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF8, + 3263 => Opcode::PseudoVFNCVT_X_F_ALT_W_MF8_MASK, + 3264 => Opcode::PseudoVFNCVT_X_F_W_M1, + 3265 => Opcode::PseudoVFNCVT_X_F_W_M1_MASK, + 3266 => Opcode::PseudoVFNCVT_X_F_W_M2, + 3267 => Opcode::PseudoVFNCVT_X_F_W_M2_MASK, + 3268 => Opcode::PseudoVFNCVT_X_F_W_M4, + 3269 => Opcode::PseudoVFNCVT_X_F_W_M4_MASK, + 3270 => Opcode::PseudoVFNCVT_X_F_W_MF2, + 3271 => Opcode::PseudoVFNCVT_X_F_W_MF2_MASK, + 3272 => Opcode::PseudoVFNCVT_X_F_W_MF4, + 3273 => Opcode::PseudoVFNCVT_X_F_W_MF4_MASK, + 3274 => Opcode::PseudoVFNCVT_X_F_W_MF8, + 3275 => Opcode::PseudoVFNCVT_X_F_W_MF8_MASK, + 3276 => Opcode::PseudoVFNMACC_ALT_VFPR16_M1_E16, + 3277 => Opcode::PseudoVFNMACC_ALT_VFPR16_M1_E16_MASK, + 3278 => Opcode::PseudoVFNMACC_ALT_VFPR16_M2_E16, + 3279 => Opcode::PseudoVFNMACC_ALT_VFPR16_M2_E16_MASK, + 3280 => Opcode::PseudoVFNMACC_ALT_VFPR16_M4_E16, + 3281 => Opcode::PseudoVFNMACC_ALT_VFPR16_M4_E16_MASK, + 3282 => Opcode::PseudoVFNMACC_ALT_VFPR16_M8_E16, + 3283 => Opcode::PseudoVFNMACC_ALT_VFPR16_M8_E16_MASK, + 3284 => Opcode::PseudoVFNMACC_ALT_VFPR16_MF2_E16, + 3285 => Opcode::PseudoVFNMACC_ALT_VFPR16_MF2_E16_MASK, + 3286 => Opcode::PseudoVFNMACC_ALT_VFPR16_MF4_E16, + 3287 => Opcode::PseudoVFNMACC_ALT_VFPR16_MF4_E16_MASK, + 3288 => Opcode::PseudoVFNMACC_ALT_VV_M1_E16, + 3289 => Opcode::PseudoVFNMACC_ALT_VV_M1_E16_MASK, + 3290 => Opcode::PseudoVFNMACC_ALT_VV_M2_E16, + 3291 => Opcode::PseudoVFNMACC_ALT_VV_M2_E16_MASK, + 3292 => Opcode::PseudoVFNMACC_ALT_VV_M4_E16, + 3293 => Opcode::PseudoVFNMACC_ALT_VV_M4_E16_MASK, + 3294 => Opcode::PseudoVFNMACC_ALT_VV_M8_E16, + 3295 => Opcode::PseudoVFNMACC_ALT_VV_M8_E16_MASK, + 3296 => Opcode::PseudoVFNMACC_ALT_VV_MF2_E16, + 3297 => Opcode::PseudoVFNMACC_ALT_VV_MF2_E16_MASK, + 3298 => Opcode::PseudoVFNMACC_ALT_VV_MF4_E16, + 3299 => Opcode::PseudoVFNMACC_ALT_VV_MF4_E16_MASK, + 3300 => Opcode::PseudoVFNMACC_VFPR16_M1_E16, + 3301 => Opcode::PseudoVFNMACC_VFPR16_M1_E16_MASK, + 3302 => Opcode::PseudoVFNMACC_VFPR16_M2_E16, + 3303 => Opcode::PseudoVFNMACC_VFPR16_M2_E16_MASK, + 3304 => Opcode::PseudoVFNMACC_VFPR16_M4_E16, + 3305 => Opcode::PseudoVFNMACC_VFPR16_M4_E16_MASK, + 3306 => Opcode::PseudoVFNMACC_VFPR16_M8_E16, + 3307 => Opcode::PseudoVFNMACC_VFPR16_M8_E16_MASK, + 3308 => Opcode::PseudoVFNMACC_VFPR16_MF2_E16, + 3309 => Opcode::PseudoVFNMACC_VFPR16_MF2_E16_MASK, + 3310 => Opcode::PseudoVFNMACC_VFPR16_MF4_E16, + 3311 => Opcode::PseudoVFNMACC_VFPR16_MF4_E16_MASK, + 3312 => Opcode::PseudoVFNMACC_VFPR32_M1_E32, + 3313 => Opcode::PseudoVFNMACC_VFPR32_M1_E32_MASK, + 3314 => Opcode::PseudoVFNMACC_VFPR32_M2_E32, + 3315 => Opcode::PseudoVFNMACC_VFPR32_M2_E32_MASK, + 3316 => Opcode::PseudoVFNMACC_VFPR32_M4_E32, + 3317 => Opcode::PseudoVFNMACC_VFPR32_M4_E32_MASK, + 3318 => Opcode::PseudoVFNMACC_VFPR32_M8_E32, + 3319 => Opcode::PseudoVFNMACC_VFPR32_M8_E32_MASK, + 3320 => Opcode::PseudoVFNMACC_VFPR32_MF2_E32, + 3321 => Opcode::PseudoVFNMACC_VFPR32_MF2_E32_MASK, + 3322 => Opcode::PseudoVFNMACC_VFPR64_M1_E64, + 3323 => Opcode::PseudoVFNMACC_VFPR64_M1_E64_MASK, + 3324 => Opcode::PseudoVFNMACC_VFPR64_M2_E64, + 3325 => Opcode::PseudoVFNMACC_VFPR64_M2_E64_MASK, + 3326 => Opcode::PseudoVFNMACC_VFPR64_M4_E64, + 3327 => Opcode::PseudoVFNMACC_VFPR64_M4_E64_MASK, + 3328 => Opcode::PseudoVFNMACC_VFPR64_M8_E64, + 3329 => Opcode::PseudoVFNMACC_VFPR64_M8_E64_MASK, + 3330 => Opcode::PseudoVFNMACC_VV_M1_E16, + 3331 => Opcode::PseudoVFNMACC_VV_M1_E16_MASK, + 3332 => Opcode::PseudoVFNMACC_VV_M1_E32, + 3333 => Opcode::PseudoVFNMACC_VV_M1_E32_MASK, + 3334 => Opcode::PseudoVFNMACC_VV_M1_E64, + 3335 => Opcode::PseudoVFNMACC_VV_M1_E64_MASK, + 3336 => Opcode::PseudoVFNMACC_VV_M2_E16, + 3337 => Opcode::PseudoVFNMACC_VV_M2_E16_MASK, + 3338 => Opcode::PseudoVFNMACC_VV_M2_E32, + 3339 => Opcode::PseudoVFNMACC_VV_M2_E32_MASK, + 3340 => Opcode::PseudoVFNMACC_VV_M2_E64, + 3341 => Opcode::PseudoVFNMACC_VV_M2_E64_MASK, + 3342 => Opcode::PseudoVFNMACC_VV_M4_E16, + 3343 => Opcode::PseudoVFNMACC_VV_M4_E16_MASK, + 3344 => Opcode::PseudoVFNMACC_VV_M4_E32, + 3345 => Opcode::PseudoVFNMACC_VV_M4_E32_MASK, + 3346 => Opcode::PseudoVFNMACC_VV_M4_E64, + 3347 => Opcode::PseudoVFNMACC_VV_M4_E64_MASK, + 3348 => Opcode::PseudoVFNMACC_VV_M8_E16, + 3349 => Opcode::PseudoVFNMACC_VV_M8_E16_MASK, + 3350 => Opcode::PseudoVFNMACC_VV_M8_E32, + 3351 => Opcode::PseudoVFNMACC_VV_M8_E32_MASK, + 3352 => Opcode::PseudoVFNMACC_VV_M8_E64, + 3353 => Opcode::PseudoVFNMACC_VV_M8_E64_MASK, + 3354 => Opcode::PseudoVFNMACC_VV_MF2_E16, + 3355 => Opcode::PseudoVFNMACC_VV_MF2_E16_MASK, + 3356 => Opcode::PseudoVFNMACC_VV_MF2_E32, + 3357 => Opcode::PseudoVFNMACC_VV_MF2_E32_MASK, + 3358 => Opcode::PseudoVFNMACC_VV_MF4_E16, + 3359 => Opcode::PseudoVFNMACC_VV_MF4_E16_MASK, + 3360 => Opcode::PseudoVFNMADD_ALT_VFPR16_M1_E16, + 3361 => Opcode::PseudoVFNMADD_ALT_VFPR16_M1_E16_MASK, + 3362 => Opcode::PseudoVFNMADD_ALT_VFPR16_M2_E16, + 3363 => Opcode::PseudoVFNMADD_ALT_VFPR16_M2_E16_MASK, + 3364 => Opcode::PseudoVFNMADD_ALT_VFPR16_M4_E16, + 3365 => Opcode::PseudoVFNMADD_ALT_VFPR16_M4_E16_MASK, + 3366 => Opcode::PseudoVFNMADD_ALT_VFPR16_M8_E16, + 3367 => Opcode::PseudoVFNMADD_ALT_VFPR16_M8_E16_MASK, + 3368 => Opcode::PseudoVFNMADD_ALT_VFPR16_MF2_E16, + 3369 => Opcode::PseudoVFNMADD_ALT_VFPR16_MF2_E16_MASK, + 3370 => Opcode::PseudoVFNMADD_ALT_VFPR16_MF4_E16, + 3371 => Opcode::PseudoVFNMADD_ALT_VFPR16_MF4_E16_MASK, + 3372 => Opcode::PseudoVFNMADD_ALT_VV_M1_E16, + 3373 => Opcode::PseudoVFNMADD_ALT_VV_M1_E16_MASK, + 3374 => Opcode::PseudoVFNMADD_ALT_VV_M2_E16, + 3375 => Opcode::PseudoVFNMADD_ALT_VV_M2_E16_MASK, + 3376 => Opcode::PseudoVFNMADD_ALT_VV_M4_E16, + 3377 => Opcode::PseudoVFNMADD_ALT_VV_M4_E16_MASK, + 3378 => Opcode::PseudoVFNMADD_ALT_VV_M8_E16, + 3379 => Opcode::PseudoVFNMADD_ALT_VV_M8_E16_MASK, + 3380 => Opcode::PseudoVFNMADD_ALT_VV_MF2_E16, + 3381 => Opcode::PseudoVFNMADD_ALT_VV_MF2_E16_MASK, + 3382 => Opcode::PseudoVFNMADD_ALT_VV_MF4_E16, + 3383 => Opcode::PseudoVFNMADD_ALT_VV_MF4_E16_MASK, + 3384 => Opcode::PseudoVFNMADD_VFPR16_M1_E16, + 3385 => Opcode::PseudoVFNMADD_VFPR16_M1_E16_MASK, + 3386 => Opcode::PseudoVFNMADD_VFPR16_M2_E16, + 3387 => Opcode::PseudoVFNMADD_VFPR16_M2_E16_MASK, + 3388 => Opcode::PseudoVFNMADD_VFPR16_M4_E16, + 3389 => Opcode::PseudoVFNMADD_VFPR16_M4_E16_MASK, + 3390 => Opcode::PseudoVFNMADD_VFPR16_M8_E16, + 3391 => Opcode::PseudoVFNMADD_VFPR16_M8_E16_MASK, + 3392 => Opcode::PseudoVFNMADD_VFPR16_MF2_E16, + 3393 => Opcode::PseudoVFNMADD_VFPR16_MF2_E16_MASK, + 3394 => Opcode::PseudoVFNMADD_VFPR16_MF4_E16, + 3395 => Opcode::PseudoVFNMADD_VFPR16_MF4_E16_MASK, + 3396 => Opcode::PseudoVFNMADD_VFPR32_M1_E32, + 3397 => Opcode::PseudoVFNMADD_VFPR32_M1_E32_MASK, + 3398 => Opcode::PseudoVFNMADD_VFPR32_M2_E32, + 3399 => Opcode::PseudoVFNMADD_VFPR32_M2_E32_MASK, + 3400 => Opcode::PseudoVFNMADD_VFPR32_M4_E32, + 3401 => Opcode::PseudoVFNMADD_VFPR32_M4_E32_MASK, + 3402 => Opcode::PseudoVFNMADD_VFPR32_M8_E32, + 3403 => Opcode::PseudoVFNMADD_VFPR32_M8_E32_MASK, + 3404 => Opcode::PseudoVFNMADD_VFPR32_MF2_E32, + 3405 => Opcode::PseudoVFNMADD_VFPR32_MF2_E32_MASK, + 3406 => Opcode::PseudoVFNMADD_VFPR64_M1_E64, + 3407 => Opcode::PseudoVFNMADD_VFPR64_M1_E64_MASK, + 3408 => Opcode::PseudoVFNMADD_VFPR64_M2_E64, + 3409 => Opcode::PseudoVFNMADD_VFPR64_M2_E64_MASK, + 3410 => Opcode::PseudoVFNMADD_VFPR64_M4_E64, + 3411 => Opcode::PseudoVFNMADD_VFPR64_M4_E64_MASK, + 3412 => Opcode::PseudoVFNMADD_VFPR64_M8_E64, + 3413 => Opcode::PseudoVFNMADD_VFPR64_M8_E64_MASK, + 3414 => Opcode::PseudoVFNMADD_VV_M1_E16, + 3415 => Opcode::PseudoVFNMADD_VV_M1_E16_MASK, + 3416 => Opcode::PseudoVFNMADD_VV_M1_E32, + 3417 => Opcode::PseudoVFNMADD_VV_M1_E32_MASK, + 3418 => Opcode::PseudoVFNMADD_VV_M1_E64, + 3419 => Opcode::PseudoVFNMADD_VV_M1_E64_MASK, + 3420 => Opcode::PseudoVFNMADD_VV_M2_E16, + 3421 => Opcode::PseudoVFNMADD_VV_M2_E16_MASK, + 3422 => Opcode::PseudoVFNMADD_VV_M2_E32, + 3423 => Opcode::PseudoVFNMADD_VV_M2_E32_MASK, + 3424 => Opcode::PseudoVFNMADD_VV_M2_E64, + 3425 => Opcode::PseudoVFNMADD_VV_M2_E64_MASK, + 3426 => Opcode::PseudoVFNMADD_VV_M4_E16, + 3427 => Opcode::PseudoVFNMADD_VV_M4_E16_MASK, + 3428 => Opcode::PseudoVFNMADD_VV_M4_E32, + 3429 => Opcode::PseudoVFNMADD_VV_M4_E32_MASK, + 3430 => Opcode::PseudoVFNMADD_VV_M4_E64, + 3431 => Opcode::PseudoVFNMADD_VV_M4_E64_MASK, + 3432 => Opcode::PseudoVFNMADD_VV_M8_E16, + 3433 => Opcode::PseudoVFNMADD_VV_M8_E16_MASK, + 3434 => Opcode::PseudoVFNMADD_VV_M8_E32, + 3435 => Opcode::PseudoVFNMADD_VV_M8_E32_MASK, + 3436 => Opcode::PseudoVFNMADD_VV_M8_E64, + 3437 => Opcode::PseudoVFNMADD_VV_M8_E64_MASK, + 3438 => Opcode::PseudoVFNMADD_VV_MF2_E16, + 3439 => Opcode::PseudoVFNMADD_VV_MF2_E16_MASK, + 3440 => Opcode::PseudoVFNMADD_VV_MF2_E32, + 3441 => Opcode::PseudoVFNMADD_VV_MF2_E32_MASK, + 3442 => Opcode::PseudoVFNMADD_VV_MF4_E16, + 3443 => Opcode::PseudoVFNMADD_VV_MF4_E16_MASK, + 3444 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M1_E16, + 3445 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M1_E16_MASK, + 3446 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M2_E16, + 3447 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M2_E16_MASK, + 3448 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M4_E16, + 3449 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M4_E16_MASK, + 3450 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M8_E16, + 3451 => Opcode::PseudoVFNMSAC_ALT_VFPR16_M8_E16_MASK, + 3452 => Opcode::PseudoVFNMSAC_ALT_VFPR16_MF2_E16, + 3453 => Opcode::PseudoVFNMSAC_ALT_VFPR16_MF2_E16_MASK, + 3454 => Opcode::PseudoVFNMSAC_ALT_VFPR16_MF4_E16, + 3455 => Opcode::PseudoVFNMSAC_ALT_VFPR16_MF4_E16_MASK, + 3456 => Opcode::PseudoVFNMSAC_ALT_VV_M1_E16, + 3457 => Opcode::PseudoVFNMSAC_ALT_VV_M1_E16_MASK, + 3458 => Opcode::PseudoVFNMSAC_ALT_VV_M2_E16, + 3459 => Opcode::PseudoVFNMSAC_ALT_VV_M2_E16_MASK, + 3460 => Opcode::PseudoVFNMSAC_ALT_VV_M4_E16, + 3461 => Opcode::PseudoVFNMSAC_ALT_VV_M4_E16_MASK, + 3462 => Opcode::PseudoVFNMSAC_ALT_VV_M8_E16, + 3463 => Opcode::PseudoVFNMSAC_ALT_VV_M8_E16_MASK, + 3464 => Opcode::PseudoVFNMSAC_ALT_VV_MF2_E16, + 3465 => Opcode::PseudoVFNMSAC_ALT_VV_MF2_E16_MASK, + 3466 => Opcode::PseudoVFNMSAC_ALT_VV_MF4_E16, + 3467 => Opcode::PseudoVFNMSAC_ALT_VV_MF4_E16_MASK, + 3468 => Opcode::PseudoVFNMSAC_VFPR16_M1_E16, + 3469 => Opcode::PseudoVFNMSAC_VFPR16_M1_E16_MASK, + 3470 => Opcode::PseudoVFNMSAC_VFPR16_M2_E16, + 3471 => Opcode::PseudoVFNMSAC_VFPR16_M2_E16_MASK, + 3472 => Opcode::PseudoVFNMSAC_VFPR16_M4_E16, + 3473 => Opcode::PseudoVFNMSAC_VFPR16_M4_E16_MASK, + 3474 => Opcode::PseudoVFNMSAC_VFPR16_M8_E16, + 3475 => Opcode::PseudoVFNMSAC_VFPR16_M8_E16_MASK, + 3476 => Opcode::PseudoVFNMSAC_VFPR16_MF2_E16, + 3477 => Opcode::PseudoVFNMSAC_VFPR16_MF2_E16_MASK, + 3478 => Opcode::PseudoVFNMSAC_VFPR16_MF4_E16, + 3479 => Opcode::PseudoVFNMSAC_VFPR16_MF4_E16_MASK, + 3480 => Opcode::PseudoVFNMSAC_VFPR32_M1_E32, + 3481 => Opcode::PseudoVFNMSAC_VFPR32_M1_E32_MASK, + 3482 => Opcode::PseudoVFNMSAC_VFPR32_M2_E32, + 3483 => Opcode::PseudoVFNMSAC_VFPR32_M2_E32_MASK, + 3484 => Opcode::PseudoVFNMSAC_VFPR32_M4_E32, + 3485 => Opcode::PseudoVFNMSAC_VFPR32_M4_E32_MASK, + 3486 => Opcode::PseudoVFNMSAC_VFPR32_M8_E32, + 3487 => Opcode::PseudoVFNMSAC_VFPR32_M8_E32_MASK, + 3488 => Opcode::PseudoVFNMSAC_VFPR32_MF2_E32, + 3489 => Opcode::PseudoVFNMSAC_VFPR32_MF2_E32_MASK, + 3490 => Opcode::PseudoVFNMSAC_VFPR64_M1_E64, + 3491 => Opcode::PseudoVFNMSAC_VFPR64_M1_E64_MASK, + 3492 => Opcode::PseudoVFNMSAC_VFPR64_M2_E64, + 3493 => Opcode::PseudoVFNMSAC_VFPR64_M2_E64_MASK, + 3494 => Opcode::PseudoVFNMSAC_VFPR64_M4_E64, + 3495 => Opcode::PseudoVFNMSAC_VFPR64_M4_E64_MASK, + 3496 => Opcode::PseudoVFNMSAC_VFPR64_M8_E64, + 3497 => Opcode::PseudoVFNMSAC_VFPR64_M8_E64_MASK, + 3498 => Opcode::PseudoVFNMSAC_VV_M1_E16, + 3499 => Opcode::PseudoVFNMSAC_VV_M1_E16_MASK, + 3500 => Opcode::PseudoVFNMSAC_VV_M1_E32, + 3501 => Opcode::PseudoVFNMSAC_VV_M1_E32_MASK, + 3502 => Opcode::PseudoVFNMSAC_VV_M1_E64, + 3503 => Opcode::PseudoVFNMSAC_VV_M1_E64_MASK, + 3504 => Opcode::PseudoVFNMSAC_VV_M2_E16, + 3505 => Opcode::PseudoVFNMSAC_VV_M2_E16_MASK, + 3506 => Opcode::PseudoVFNMSAC_VV_M2_E32, + 3507 => Opcode::PseudoVFNMSAC_VV_M2_E32_MASK, + 3508 => Opcode::PseudoVFNMSAC_VV_M2_E64, + 3509 => Opcode::PseudoVFNMSAC_VV_M2_E64_MASK, + 3510 => Opcode::PseudoVFNMSAC_VV_M4_E16, + 3511 => Opcode::PseudoVFNMSAC_VV_M4_E16_MASK, + 3512 => Opcode::PseudoVFNMSAC_VV_M4_E32, + 3513 => Opcode::PseudoVFNMSAC_VV_M4_E32_MASK, + 3514 => Opcode::PseudoVFNMSAC_VV_M4_E64, + 3515 => Opcode::PseudoVFNMSAC_VV_M4_E64_MASK, + 3516 => Opcode::PseudoVFNMSAC_VV_M8_E16, + 3517 => Opcode::PseudoVFNMSAC_VV_M8_E16_MASK, + 3518 => Opcode::PseudoVFNMSAC_VV_M8_E32, + 3519 => Opcode::PseudoVFNMSAC_VV_M8_E32_MASK, + 3520 => Opcode::PseudoVFNMSAC_VV_M8_E64, + 3521 => Opcode::PseudoVFNMSAC_VV_M8_E64_MASK, + 3522 => Opcode::PseudoVFNMSAC_VV_MF2_E16, + 3523 => Opcode::PseudoVFNMSAC_VV_MF2_E16_MASK, + 3524 => Opcode::PseudoVFNMSAC_VV_MF2_E32, + 3525 => Opcode::PseudoVFNMSAC_VV_MF2_E32_MASK, + 3526 => Opcode::PseudoVFNMSAC_VV_MF4_E16, + 3527 => Opcode::PseudoVFNMSAC_VV_MF4_E16_MASK, + 3528 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M1_E16, + 3529 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M1_E16_MASK, + 3530 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M2_E16, + 3531 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M2_E16_MASK, + 3532 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M4_E16, + 3533 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M4_E16_MASK, + 3534 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M8_E16, + 3535 => Opcode::PseudoVFNMSUB_ALT_VFPR16_M8_E16_MASK, + 3536 => Opcode::PseudoVFNMSUB_ALT_VFPR16_MF2_E16, + 3537 => Opcode::PseudoVFNMSUB_ALT_VFPR16_MF2_E16_MASK, + 3538 => Opcode::PseudoVFNMSUB_ALT_VFPR16_MF4_E16, + 3539 => Opcode::PseudoVFNMSUB_ALT_VFPR16_MF4_E16_MASK, + 3540 => Opcode::PseudoVFNMSUB_ALT_VV_M1_E16, + 3541 => Opcode::PseudoVFNMSUB_ALT_VV_M1_E16_MASK, + 3542 => Opcode::PseudoVFNMSUB_ALT_VV_M2_E16, + 3543 => Opcode::PseudoVFNMSUB_ALT_VV_M2_E16_MASK, + 3544 => Opcode::PseudoVFNMSUB_ALT_VV_M4_E16, + 3545 => Opcode::PseudoVFNMSUB_ALT_VV_M4_E16_MASK, + 3546 => Opcode::PseudoVFNMSUB_ALT_VV_M8_E16, + 3547 => Opcode::PseudoVFNMSUB_ALT_VV_M8_E16_MASK, + 3548 => Opcode::PseudoVFNMSUB_ALT_VV_MF2_E16, + 3549 => Opcode::PseudoVFNMSUB_ALT_VV_MF2_E16_MASK, + 3550 => Opcode::PseudoVFNMSUB_ALT_VV_MF4_E16, + 3551 => Opcode::PseudoVFNMSUB_ALT_VV_MF4_E16_MASK, + 3552 => Opcode::PseudoVFNMSUB_VFPR16_M1_E16, + 3553 => Opcode::PseudoVFNMSUB_VFPR16_M1_E16_MASK, + 3554 => Opcode::PseudoVFNMSUB_VFPR16_M2_E16, + 3555 => Opcode::PseudoVFNMSUB_VFPR16_M2_E16_MASK, + 3556 => Opcode::PseudoVFNMSUB_VFPR16_M4_E16, + 3557 => Opcode::PseudoVFNMSUB_VFPR16_M4_E16_MASK, + 3558 => Opcode::PseudoVFNMSUB_VFPR16_M8_E16, + 3559 => Opcode::PseudoVFNMSUB_VFPR16_M8_E16_MASK, + 3560 => Opcode::PseudoVFNMSUB_VFPR16_MF2_E16, + 3561 => Opcode::PseudoVFNMSUB_VFPR16_MF2_E16_MASK, + 3562 => Opcode::PseudoVFNMSUB_VFPR16_MF4_E16, + 3563 => Opcode::PseudoVFNMSUB_VFPR16_MF4_E16_MASK, + 3564 => Opcode::PseudoVFNMSUB_VFPR32_M1_E32, + 3565 => Opcode::PseudoVFNMSUB_VFPR32_M1_E32_MASK, + 3566 => Opcode::PseudoVFNMSUB_VFPR32_M2_E32, + 3567 => Opcode::PseudoVFNMSUB_VFPR32_M2_E32_MASK, + 3568 => Opcode::PseudoVFNMSUB_VFPR32_M4_E32, + 3569 => Opcode::PseudoVFNMSUB_VFPR32_M4_E32_MASK, + 3570 => Opcode::PseudoVFNMSUB_VFPR32_M8_E32, + 3571 => Opcode::PseudoVFNMSUB_VFPR32_M8_E32_MASK, + 3572 => Opcode::PseudoVFNMSUB_VFPR32_MF2_E32, + 3573 => Opcode::PseudoVFNMSUB_VFPR32_MF2_E32_MASK, + 3574 => Opcode::PseudoVFNMSUB_VFPR64_M1_E64, + 3575 => Opcode::PseudoVFNMSUB_VFPR64_M1_E64_MASK, + 3576 => Opcode::PseudoVFNMSUB_VFPR64_M2_E64, + 3577 => Opcode::PseudoVFNMSUB_VFPR64_M2_E64_MASK, + 3578 => Opcode::PseudoVFNMSUB_VFPR64_M4_E64, + 3579 => Opcode::PseudoVFNMSUB_VFPR64_M4_E64_MASK, + 3580 => Opcode::PseudoVFNMSUB_VFPR64_M8_E64, + 3581 => Opcode::PseudoVFNMSUB_VFPR64_M8_E64_MASK, + 3582 => Opcode::PseudoVFNMSUB_VV_M1_E16, + 3583 => Opcode::PseudoVFNMSUB_VV_M1_E16_MASK, + 3584 => Opcode::PseudoVFNMSUB_VV_M1_E32, + 3585 => Opcode::PseudoVFNMSUB_VV_M1_E32_MASK, + 3586 => Opcode::PseudoVFNMSUB_VV_M1_E64, + 3587 => Opcode::PseudoVFNMSUB_VV_M1_E64_MASK, + 3588 => Opcode::PseudoVFNMSUB_VV_M2_E16, + 3589 => Opcode::PseudoVFNMSUB_VV_M2_E16_MASK, + 3590 => Opcode::PseudoVFNMSUB_VV_M2_E32, + 3591 => Opcode::PseudoVFNMSUB_VV_M2_E32_MASK, + 3592 => Opcode::PseudoVFNMSUB_VV_M2_E64, + 3593 => Opcode::PseudoVFNMSUB_VV_M2_E64_MASK, + 3594 => Opcode::PseudoVFNMSUB_VV_M4_E16, + 3595 => Opcode::PseudoVFNMSUB_VV_M4_E16_MASK, + 3596 => Opcode::PseudoVFNMSUB_VV_M4_E32, + 3597 => Opcode::PseudoVFNMSUB_VV_M4_E32_MASK, + 3598 => Opcode::PseudoVFNMSUB_VV_M4_E64, + 3599 => Opcode::PseudoVFNMSUB_VV_M4_E64_MASK, + 3600 => Opcode::PseudoVFNMSUB_VV_M8_E16, + 3601 => Opcode::PseudoVFNMSUB_VV_M8_E16_MASK, + 3602 => Opcode::PseudoVFNMSUB_VV_M8_E32, + 3603 => Opcode::PseudoVFNMSUB_VV_M8_E32_MASK, + 3604 => Opcode::PseudoVFNMSUB_VV_M8_E64, + 3605 => Opcode::PseudoVFNMSUB_VV_M8_E64_MASK, + 3606 => Opcode::PseudoVFNMSUB_VV_MF2_E16, + 3607 => Opcode::PseudoVFNMSUB_VV_MF2_E16_MASK, + 3608 => Opcode::PseudoVFNMSUB_VV_MF2_E32, + 3609 => Opcode::PseudoVFNMSUB_VV_MF2_E32_MASK, + 3610 => Opcode::PseudoVFNMSUB_VV_MF4_E16, + 3611 => Opcode::PseudoVFNMSUB_VV_MF4_E16_MASK, + 3612 => Opcode::PseudoVFRDIV_VFPR16_M1_E16, + 3613 => Opcode::PseudoVFRDIV_VFPR16_M1_E16_MASK, + 3614 => Opcode::PseudoVFRDIV_VFPR16_M2_E16, + 3615 => Opcode::PseudoVFRDIV_VFPR16_M2_E16_MASK, + 3616 => Opcode::PseudoVFRDIV_VFPR16_M4_E16, + 3617 => Opcode::PseudoVFRDIV_VFPR16_M4_E16_MASK, + 3618 => Opcode::PseudoVFRDIV_VFPR16_M8_E16, + 3619 => Opcode::PseudoVFRDIV_VFPR16_M8_E16_MASK, + 3620 => Opcode::PseudoVFRDIV_VFPR16_MF2_E16, + 3621 => Opcode::PseudoVFRDIV_VFPR16_MF2_E16_MASK, + 3622 => Opcode::PseudoVFRDIV_VFPR16_MF4_E16, + 3623 => Opcode::PseudoVFRDIV_VFPR16_MF4_E16_MASK, + 3624 => Opcode::PseudoVFRDIV_VFPR32_M1_E32, + 3625 => Opcode::PseudoVFRDIV_VFPR32_M1_E32_MASK, + 3626 => Opcode::PseudoVFRDIV_VFPR32_M2_E32, + 3627 => Opcode::PseudoVFRDIV_VFPR32_M2_E32_MASK, + 3628 => Opcode::PseudoVFRDIV_VFPR32_M4_E32, + 3629 => Opcode::PseudoVFRDIV_VFPR32_M4_E32_MASK, + 3630 => Opcode::PseudoVFRDIV_VFPR32_M8_E32, + 3631 => Opcode::PseudoVFRDIV_VFPR32_M8_E32_MASK, + 3632 => Opcode::PseudoVFRDIV_VFPR32_MF2_E32, + 3633 => Opcode::PseudoVFRDIV_VFPR32_MF2_E32_MASK, + 3634 => Opcode::PseudoVFRDIV_VFPR64_M1_E64, + 3635 => Opcode::PseudoVFRDIV_VFPR64_M1_E64_MASK, + 3636 => Opcode::PseudoVFRDIV_VFPR64_M2_E64, + 3637 => Opcode::PseudoVFRDIV_VFPR64_M2_E64_MASK, + 3638 => Opcode::PseudoVFRDIV_VFPR64_M4_E64, + 3639 => Opcode::PseudoVFRDIV_VFPR64_M4_E64_MASK, + 3640 => Opcode::PseudoVFRDIV_VFPR64_M8_E64, + 3641 => Opcode::PseudoVFRDIV_VFPR64_M8_E64_MASK, + 3642 => Opcode::PseudoVFREC7_ALT_V_M1_E16, + 3643 => Opcode::PseudoVFREC7_ALT_V_M1_E16_MASK, + 3644 => Opcode::PseudoVFREC7_ALT_V_M2_E16, + 3645 => Opcode::PseudoVFREC7_ALT_V_M2_E16_MASK, + 3646 => Opcode::PseudoVFREC7_ALT_V_M4_E16, + 3647 => Opcode::PseudoVFREC7_ALT_V_M4_E16_MASK, + 3648 => Opcode::PseudoVFREC7_ALT_V_M8_E16, + 3649 => Opcode::PseudoVFREC7_ALT_V_M8_E16_MASK, + 3650 => Opcode::PseudoVFREC7_ALT_V_MF2_E16, + 3651 => Opcode::PseudoVFREC7_ALT_V_MF2_E16_MASK, + 3652 => Opcode::PseudoVFREC7_ALT_V_MF4_E16, + 3653 => Opcode::PseudoVFREC7_ALT_V_MF4_E16_MASK, + 3654 => Opcode::PseudoVFREC7_V_M1_E16, + 3655 => Opcode::PseudoVFREC7_V_M1_E16_MASK, + 3656 => Opcode::PseudoVFREC7_V_M1_E32, + 3657 => Opcode::PseudoVFREC7_V_M1_E32_MASK, + 3658 => Opcode::PseudoVFREC7_V_M1_E64, + 3659 => Opcode::PseudoVFREC7_V_M1_E64_MASK, + 3660 => Opcode::PseudoVFREC7_V_M2_E16, + 3661 => Opcode::PseudoVFREC7_V_M2_E16_MASK, + 3662 => Opcode::PseudoVFREC7_V_M2_E32, + 3663 => Opcode::PseudoVFREC7_V_M2_E32_MASK, + 3664 => Opcode::PseudoVFREC7_V_M2_E64, + 3665 => Opcode::PseudoVFREC7_V_M2_E64_MASK, + 3666 => Opcode::PseudoVFREC7_V_M4_E16, + 3667 => Opcode::PseudoVFREC7_V_M4_E16_MASK, + 3668 => Opcode::PseudoVFREC7_V_M4_E32, + 3669 => Opcode::PseudoVFREC7_V_M4_E32_MASK, + 3670 => Opcode::PseudoVFREC7_V_M4_E64, + 3671 => Opcode::PseudoVFREC7_V_M4_E64_MASK, + 3672 => Opcode::PseudoVFREC7_V_M8_E16, + 3673 => Opcode::PseudoVFREC7_V_M8_E16_MASK, + 3674 => Opcode::PseudoVFREC7_V_M8_E32, + 3675 => Opcode::PseudoVFREC7_V_M8_E32_MASK, + 3676 => Opcode::PseudoVFREC7_V_M8_E64, + 3677 => Opcode::PseudoVFREC7_V_M8_E64_MASK, + 3678 => Opcode::PseudoVFREC7_V_MF2_E16, + 3679 => Opcode::PseudoVFREC7_V_MF2_E16_MASK, + 3680 => Opcode::PseudoVFREC7_V_MF2_E32, + 3681 => Opcode::PseudoVFREC7_V_MF2_E32_MASK, + 3682 => Opcode::PseudoVFREC7_V_MF4_E16, + 3683 => Opcode::PseudoVFREC7_V_MF4_E16_MASK, + 3684 => Opcode::PseudoVFREDMAX_VS_M1_E16, + 3685 => Opcode::PseudoVFREDMAX_VS_M1_E16_MASK, + 3686 => Opcode::PseudoVFREDMAX_VS_M1_E32, + 3687 => Opcode::PseudoVFREDMAX_VS_M1_E32_MASK, + 3688 => Opcode::PseudoVFREDMAX_VS_M1_E64, + 3689 => Opcode::PseudoVFREDMAX_VS_M1_E64_MASK, + 3690 => Opcode::PseudoVFREDMAX_VS_M2_E16, + 3691 => Opcode::PseudoVFREDMAX_VS_M2_E16_MASK, + 3692 => Opcode::PseudoVFREDMAX_VS_M2_E32, + 3693 => Opcode::PseudoVFREDMAX_VS_M2_E32_MASK, + 3694 => Opcode::PseudoVFREDMAX_VS_M2_E64, + 3695 => Opcode::PseudoVFREDMAX_VS_M2_E64_MASK, + 3696 => Opcode::PseudoVFREDMAX_VS_M4_E16, + 3697 => Opcode::PseudoVFREDMAX_VS_M4_E16_MASK, + 3698 => Opcode::PseudoVFREDMAX_VS_M4_E32, + 3699 => Opcode::PseudoVFREDMAX_VS_M4_E32_MASK, + 3700 => Opcode::PseudoVFREDMAX_VS_M4_E64, + 3701 => Opcode::PseudoVFREDMAX_VS_M4_E64_MASK, + 3702 => Opcode::PseudoVFREDMAX_VS_M8_E16, + 3703 => Opcode::PseudoVFREDMAX_VS_M8_E16_MASK, + 3704 => Opcode::PseudoVFREDMAX_VS_M8_E32, + 3705 => Opcode::PseudoVFREDMAX_VS_M8_E32_MASK, + 3706 => Opcode::PseudoVFREDMAX_VS_M8_E64, + 3707 => Opcode::PseudoVFREDMAX_VS_M8_E64_MASK, + 3708 => Opcode::PseudoVFREDMAX_VS_MF2_E16, + 3709 => Opcode::PseudoVFREDMAX_VS_MF2_E16_MASK, + 3710 => Opcode::PseudoVFREDMAX_VS_MF2_E32, + 3711 => Opcode::PseudoVFREDMAX_VS_MF2_E32_MASK, + 3712 => Opcode::PseudoVFREDMAX_VS_MF4_E16, + 3713 => Opcode::PseudoVFREDMAX_VS_MF4_E16_MASK, + 3714 => Opcode::PseudoVFREDMIN_VS_M1_E16, + 3715 => Opcode::PseudoVFREDMIN_VS_M1_E16_MASK, + 3716 => Opcode::PseudoVFREDMIN_VS_M1_E32, + 3717 => Opcode::PseudoVFREDMIN_VS_M1_E32_MASK, + 3718 => Opcode::PseudoVFREDMIN_VS_M1_E64, + 3719 => Opcode::PseudoVFREDMIN_VS_M1_E64_MASK, + 3720 => Opcode::PseudoVFREDMIN_VS_M2_E16, + 3721 => Opcode::PseudoVFREDMIN_VS_M2_E16_MASK, + 3722 => Opcode::PseudoVFREDMIN_VS_M2_E32, + 3723 => Opcode::PseudoVFREDMIN_VS_M2_E32_MASK, + 3724 => Opcode::PseudoVFREDMIN_VS_M2_E64, + 3725 => Opcode::PseudoVFREDMIN_VS_M2_E64_MASK, + 3726 => Opcode::PseudoVFREDMIN_VS_M4_E16, + 3727 => Opcode::PseudoVFREDMIN_VS_M4_E16_MASK, + 3728 => Opcode::PseudoVFREDMIN_VS_M4_E32, + 3729 => Opcode::PseudoVFREDMIN_VS_M4_E32_MASK, + 3730 => Opcode::PseudoVFREDMIN_VS_M4_E64, + 3731 => Opcode::PseudoVFREDMIN_VS_M4_E64_MASK, + 3732 => Opcode::PseudoVFREDMIN_VS_M8_E16, + 3733 => Opcode::PseudoVFREDMIN_VS_M8_E16_MASK, + 3734 => Opcode::PseudoVFREDMIN_VS_M8_E32, + 3735 => Opcode::PseudoVFREDMIN_VS_M8_E32_MASK, + 3736 => Opcode::PseudoVFREDMIN_VS_M8_E64, + 3737 => Opcode::PseudoVFREDMIN_VS_M8_E64_MASK, + 3738 => Opcode::PseudoVFREDMIN_VS_MF2_E16, + 3739 => Opcode::PseudoVFREDMIN_VS_MF2_E16_MASK, + 3740 => Opcode::PseudoVFREDMIN_VS_MF2_E32, + 3741 => Opcode::PseudoVFREDMIN_VS_MF2_E32_MASK, + 3742 => Opcode::PseudoVFREDMIN_VS_MF4_E16, + 3743 => Opcode::PseudoVFREDMIN_VS_MF4_E16_MASK, + 3744 => Opcode::PseudoVFREDOSUM_VS_M1_E16, + 3745 => Opcode::PseudoVFREDOSUM_VS_M1_E16_MASK, + 3746 => Opcode::PseudoVFREDOSUM_VS_M1_E32, + 3747 => Opcode::PseudoVFREDOSUM_VS_M1_E32_MASK, + 3748 => Opcode::PseudoVFREDOSUM_VS_M1_E64, + 3749 => Opcode::PseudoVFREDOSUM_VS_M1_E64_MASK, + 3750 => Opcode::PseudoVFREDOSUM_VS_M2_E16, + 3751 => Opcode::PseudoVFREDOSUM_VS_M2_E16_MASK, + 3752 => Opcode::PseudoVFREDOSUM_VS_M2_E32, + 3753 => Opcode::PseudoVFREDOSUM_VS_M2_E32_MASK, + 3754 => Opcode::PseudoVFREDOSUM_VS_M2_E64, + 3755 => Opcode::PseudoVFREDOSUM_VS_M2_E64_MASK, + 3756 => Opcode::PseudoVFREDOSUM_VS_M4_E16, + 3757 => Opcode::PseudoVFREDOSUM_VS_M4_E16_MASK, + 3758 => Opcode::PseudoVFREDOSUM_VS_M4_E32, + 3759 => Opcode::PseudoVFREDOSUM_VS_M4_E32_MASK, + 3760 => Opcode::PseudoVFREDOSUM_VS_M4_E64, + 3761 => Opcode::PseudoVFREDOSUM_VS_M4_E64_MASK, + 3762 => Opcode::PseudoVFREDOSUM_VS_M8_E16, + 3763 => Opcode::PseudoVFREDOSUM_VS_M8_E16_MASK, + 3764 => Opcode::PseudoVFREDOSUM_VS_M8_E32, + 3765 => Opcode::PseudoVFREDOSUM_VS_M8_E32_MASK, + 3766 => Opcode::PseudoVFREDOSUM_VS_M8_E64, + 3767 => Opcode::PseudoVFREDOSUM_VS_M8_E64_MASK, + 3768 => Opcode::PseudoVFREDOSUM_VS_MF2_E16, + 3769 => Opcode::PseudoVFREDOSUM_VS_MF2_E16_MASK, + 3770 => Opcode::PseudoVFREDOSUM_VS_MF2_E32, + 3771 => Opcode::PseudoVFREDOSUM_VS_MF2_E32_MASK, + 3772 => Opcode::PseudoVFREDOSUM_VS_MF4_E16, + 3773 => Opcode::PseudoVFREDOSUM_VS_MF4_E16_MASK, + 3774 => Opcode::PseudoVFREDUSUM_VS_M1_E16, + 3775 => Opcode::PseudoVFREDUSUM_VS_M1_E16_MASK, + 3776 => Opcode::PseudoVFREDUSUM_VS_M1_E32, + 3777 => Opcode::PseudoVFREDUSUM_VS_M1_E32_MASK, + 3778 => Opcode::PseudoVFREDUSUM_VS_M1_E64, + 3779 => Opcode::PseudoVFREDUSUM_VS_M1_E64_MASK, + 3780 => Opcode::PseudoVFREDUSUM_VS_M2_E16, + 3781 => Opcode::PseudoVFREDUSUM_VS_M2_E16_MASK, + 3782 => Opcode::PseudoVFREDUSUM_VS_M2_E32, + 3783 => Opcode::PseudoVFREDUSUM_VS_M2_E32_MASK, + 3784 => Opcode::PseudoVFREDUSUM_VS_M2_E64, + 3785 => Opcode::PseudoVFREDUSUM_VS_M2_E64_MASK, + 3786 => Opcode::PseudoVFREDUSUM_VS_M4_E16, + 3787 => Opcode::PseudoVFREDUSUM_VS_M4_E16_MASK, + 3788 => Opcode::PseudoVFREDUSUM_VS_M4_E32, + 3789 => Opcode::PseudoVFREDUSUM_VS_M4_E32_MASK, + 3790 => Opcode::PseudoVFREDUSUM_VS_M4_E64, + 3791 => Opcode::PseudoVFREDUSUM_VS_M4_E64_MASK, + 3792 => Opcode::PseudoVFREDUSUM_VS_M8_E16, + 3793 => Opcode::PseudoVFREDUSUM_VS_M8_E16_MASK, + 3794 => Opcode::PseudoVFREDUSUM_VS_M8_E32, + 3795 => Opcode::PseudoVFREDUSUM_VS_M8_E32_MASK, + 3796 => Opcode::PseudoVFREDUSUM_VS_M8_E64, + 3797 => Opcode::PseudoVFREDUSUM_VS_M8_E64_MASK, + 3798 => Opcode::PseudoVFREDUSUM_VS_MF2_E16, + 3799 => Opcode::PseudoVFREDUSUM_VS_MF2_E16_MASK, + 3800 => Opcode::PseudoVFREDUSUM_VS_MF2_E32, + 3801 => Opcode::PseudoVFREDUSUM_VS_MF2_E32_MASK, + 3802 => Opcode::PseudoVFREDUSUM_VS_MF4_E16, + 3803 => Opcode::PseudoVFREDUSUM_VS_MF4_E16_MASK, + 3804 => Opcode::PseudoVFROUND_NOEXCEPT_V_M1_MASK, + 3805 => Opcode::PseudoVFROUND_NOEXCEPT_V_M2_MASK, + 3806 => Opcode::PseudoVFROUND_NOEXCEPT_V_M4_MASK, + 3807 => Opcode::PseudoVFROUND_NOEXCEPT_V_M8_MASK, + 3808 => Opcode::PseudoVFROUND_NOEXCEPT_V_MF2_MASK, + 3809 => Opcode::PseudoVFROUND_NOEXCEPT_V_MF4_MASK, + 3810 => Opcode::PseudoVFRSQRT7_ALT_V_M1_E16, + 3811 => Opcode::PseudoVFRSQRT7_ALT_V_M1_E16_MASK, + 3812 => Opcode::PseudoVFRSQRT7_ALT_V_M2_E16, + 3813 => Opcode::PseudoVFRSQRT7_ALT_V_M2_E16_MASK, + 3814 => Opcode::PseudoVFRSQRT7_ALT_V_M4_E16, + 3815 => Opcode::PseudoVFRSQRT7_ALT_V_M4_E16_MASK, + 3816 => Opcode::PseudoVFRSQRT7_ALT_V_M8_E16, + 3817 => Opcode::PseudoVFRSQRT7_ALT_V_M8_E16_MASK, + 3818 => Opcode::PseudoVFRSQRT7_ALT_V_MF2_E16, + 3819 => Opcode::PseudoVFRSQRT7_ALT_V_MF2_E16_MASK, + 3820 => Opcode::PseudoVFRSQRT7_ALT_V_MF4_E16, + 3821 => Opcode::PseudoVFRSQRT7_ALT_V_MF4_E16_MASK, + 3822 => Opcode::PseudoVFRSQRT7_V_M1_E16, + 3823 => Opcode::PseudoVFRSQRT7_V_M1_E16_MASK, + 3824 => Opcode::PseudoVFRSQRT7_V_M1_E32, + 3825 => Opcode::PseudoVFRSQRT7_V_M1_E32_MASK, + 3826 => Opcode::PseudoVFRSQRT7_V_M1_E64, + 3827 => Opcode::PseudoVFRSQRT7_V_M1_E64_MASK, + 3828 => Opcode::PseudoVFRSQRT7_V_M2_E16, + 3829 => Opcode::PseudoVFRSQRT7_V_M2_E16_MASK, + 3830 => Opcode::PseudoVFRSQRT7_V_M2_E32, + 3831 => Opcode::PseudoVFRSQRT7_V_M2_E32_MASK, + 3832 => Opcode::PseudoVFRSQRT7_V_M2_E64, + 3833 => Opcode::PseudoVFRSQRT7_V_M2_E64_MASK, + 3834 => Opcode::PseudoVFRSQRT7_V_M4_E16, + 3835 => Opcode::PseudoVFRSQRT7_V_M4_E16_MASK, + 3836 => Opcode::PseudoVFRSQRT7_V_M4_E32, + 3837 => Opcode::PseudoVFRSQRT7_V_M4_E32_MASK, + 3838 => Opcode::PseudoVFRSQRT7_V_M4_E64, + 3839 => Opcode::PseudoVFRSQRT7_V_M4_E64_MASK, + 3840 => Opcode::PseudoVFRSQRT7_V_M8_E16, + 3841 => Opcode::PseudoVFRSQRT7_V_M8_E16_MASK, + 3842 => Opcode::PseudoVFRSQRT7_V_M8_E32, + 3843 => Opcode::PseudoVFRSQRT7_V_M8_E32_MASK, + 3844 => Opcode::PseudoVFRSQRT7_V_M8_E64, + 3845 => Opcode::PseudoVFRSQRT7_V_M8_E64_MASK, + 3846 => Opcode::PseudoVFRSQRT7_V_MF2_E16, + 3847 => Opcode::PseudoVFRSQRT7_V_MF2_E16_MASK, + 3848 => Opcode::PseudoVFRSQRT7_V_MF2_E32, + 3849 => Opcode::PseudoVFRSQRT7_V_MF2_E32_MASK, + 3850 => Opcode::PseudoVFRSQRT7_V_MF4_E16, + 3851 => Opcode::PseudoVFRSQRT7_V_MF4_E16_MASK, + 3852 => Opcode::PseudoVFRSUB_ALT_VFPR16_M1_E16, + 3853 => Opcode::PseudoVFRSUB_ALT_VFPR16_M1_E16_MASK, + 3854 => Opcode::PseudoVFRSUB_ALT_VFPR16_M2_E16, + 3855 => Opcode::PseudoVFRSUB_ALT_VFPR16_M2_E16_MASK, + 3856 => Opcode::PseudoVFRSUB_ALT_VFPR16_M4_E16, + 3857 => Opcode::PseudoVFRSUB_ALT_VFPR16_M4_E16_MASK, + 3858 => Opcode::PseudoVFRSUB_ALT_VFPR16_M8_E16, + 3859 => Opcode::PseudoVFRSUB_ALT_VFPR16_M8_E16_MASK, + 3860 => Opcode::PseudoVFRSUB_ALT_VFPR16_MF2_E16, + 3861 => Opcode::PseudoVFRSUB_ALT_VFPR16_MF2_E16_MASK, + 3862 => Opcode::PseudoVFRSUB_ALT_VFPR16_MF4_E16, + 3863 => Opcode::PseudoVFRSUB_ALT_VFPR16_MF4_E16_MASK, + 3864 => Opcode::PseudoVFRSUB_VFPR16_M1_E16, + 3865 => Opcode::PseudoVFRSUB_VFPR16_M1_E16_MASK, + 3866 => Opcode::PseudoVFRSUB_VFPR16_M2_E16, + 3867 => Opcode::PseudoVFRSUB_VFPR16_M2_E16_MASK, + 3868 => Opcode::PseudoVFRSUB_VFPR16_M4_E16, + 3869 => Opcode::PseudoVFRSUB_VFPR16_M4_E16_MASK, + 3870 => Opcode::PseudoVFRSUB_VFPR16_M8_E16, + 3871 => Opcode::PseudoVFRSUB_VFPR16_M8_E16_MASK, + 3872 => Opcode::PseudoVFRSUB_VFPR16_MF2_E16, + 3873 => Opcode::PseudoVFRSUB_VFPR16_MF2_E16_MASK, + 3874 => Opcode::PseudoVFRSUB_VFPR16_MF4_E16, + 3875 => Opcode::PseudoVFRSUB_VFPR16_MF4_E16_MASK, + 3876 => Opcode::PseudoVFRSUB_VFPR32_M1_E32, + 3877 => Opcode::PseudoVFRSUB_VFPR32_M1_E32_MASK, + 3878 => Opcode::PseudoVFRSUB_VFPR32_M2_E32, + 3879 => Opcode::PseudoVFRSUB_VFPR32_M2_E32_MASK, + 3880 => Opcode::PseudoVFRSUB_VFPR32_M4_E32, + 3881 => Opcode::PseudoVFRSUB_VFPR32_M4_E32_MASK, + 3882 => Opcode::PseudoVFRSUB_VFPR32_M8_E32, + 3883 => Opcode::PseudoVFRSUB_VFPR32_M8_E32_MASK, + 3884 => Opcode::PseudoVFRSUB_VFPR32_MF2_E32, + 3885 => Opcode::PseudoVFRSUB_VFPR32_MF2_E32_MASK, + 3886 => Opcode::PseudoVFRSUB_VFPR64_M1_E64, + 3887 => Opcode::PseudoVFRSUB_VFPR64_M1_E64_MASK, + 3888 => Opcode::PseudoVFRSUB_VFPR64_M2_E64, + 3889 => Opcode::PseudoVFRSUB_VFPR64_M2_E64_MASK, + 3890 => Opcode::PseudoVFRSUB_VFPR64_M4_E64, + 3891 => Opcode::PseudoVFRSUB_VFPR64_M4_E64_MASK, + 3892 => Opcode::PseudoVFRSUB_VFPR64_M8_E64, + 3893 => Opcode::PseudoVFRSUB_VFPR64_M8_E64_MASK, + 3894 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M1_E16, + 3895 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M1_E16_MASK, + 3896 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M2_E16, + 3897 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M2_E16_MASK, + 3898 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M4_E16, + 3899 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M4_E16_MASK, + 3900 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M8_E16, + 3901 => Opcode::PseudoVFSGNJN_ALT_VFPR16_M8_E16_MASK, + 3902 => Opcode::PseudoVFSGNJN_ALT_VFPR16_MF2_E16, + 3903 => Opcode::PseudoVFSGNJN_ALT_VFPR16_MF2_E16_MASK, + 3904 => Opcode::PseudoVFSGNJN_ALT_VFPR16_MF4_E16, + 3905 => Opcode::PseudoVFSGNJN_ALT_VFPR16_MF4_E16_MASK, + 3906 => Opcode::PseudoVFSGNJN_ALT_VV_M1_E16, + 3907 => Opcode::PseudoVFSGNJN_ALT_VV_M1_E16_MASK, + 3908 => Opcode::PseudoVFSGNJN_ALT_VV_M2_E16, + 3909 => Opcode::PseudoVFSGNJN_ALT_VV_M2_E16_MASK, + 3910 => Opcode::PseudoVFSGNJN_ALT_VV_M4_E16, + 3911 => Opcode::PseudoVFSGNJN_ALT_VV_M4_E16_MASK, + 3912 => Opcode::PseudoVFSGNJN_ALT_VV_M8_E16, + 3913 => Opcode::PseudoVFSGNJN_ALT_VV_M8_E16_MASK, + 3914 => Opcode::PseudoVFSGNJN_ALT_VV_MF2_E16, + 3915 => Opcode::PseudoVFSGNJN_ALT_VV_MF2_E16_MASK, + 3916 => Opcode::PseudoVFSGNJN_ALT_VV_MF4_E16, + 3917 => Opcode::PseudoVFSGNJN_ALT_VV_MF4_E16_MASK, + 3918 => Opcode::PseudoVFSGNJN_VFPR16_M1_E16, + 3919 => Opcode::PseudoVFSGNJN_VFPR16_M1_E16_MASK, + 3920 => Opcode::PseudoVFSGNJN_VFPR16_M2_E16, + 3921 => Opcode::PseudoVFSGNJN_VFPR16_M2_E16_MASK, + 3922 => Opcode::PseudoVFSGNJN_VFPR16_M4_E16, + 3923 => Opcode::PseudoVFSGNJN_VFPR16_M4_E16_MASK, + 3924 => Opcode::PseudoVFSGNJN_VFPR16_M8_E16, + 3925 => Opcode::PseudoVFSGNJN_VFPR16_M8_E16_MASK, + 3926 => Opcode::PseudoVFSGNJN_VFPR16_MF2_E16, + 3927 => Opcode::PseudoVFSGNJN_VFPR16_MF2_E16_MASK, + 3928 => Opcode::PseudoVFSGNJN_VFPR16_MF4_E16, + 3929 => Opcode::PseudoVFSGNJN_VFPR16_MF4_E16_MASK, + 3930 => Opcode::PseudoVFSGNJN_VFPR32_M1_E32, + 3931 => Opcode::PseudoVFSGNJN_VFPR32_M1_E32_MASK, + 3932 => Opcode::PseudoVFSGNJN_VFPR32_M2_E32, + 3933 => Opcode::PseudoVFSGNJN_VFPR32_M2_E32_MASK, + 3934 => Opcode::PseudoVFSGNJN_VFPR32_M4_E32, + 3935 => Opcode::PseudoVFSGNJN_VFPR32_M4_E32_MASK, + 3936 => Opcode::PseudoVFSGNJN_VFPR32_M8_E32, + 3937 => Opcode::PseudoVFSGNJN_VFPR32_M8_E32_MASK, + 3938 => Opcode::PseudoVFSGNJN_VFPR32_MF2_E32, + 3939 => Opcode::PseudoVFSGNJN_VFPR32_MF2_E32_MASK, + 3940 => Opcode::PseudoVFSGNJN_VFPR64_M1_E64, + 3941 => Opcode::PseudoVFSGNJN_VFPR64_M1_E64_MASK, + 3942 => Opcode::PseudoVFSGNJN_VFPR64_M2_E64, + 3943 => Opcode::PseudoVFSGNJN_VFPR64_M2_E64_MASK, + 3944 => Opcode::PseudoVFSGNJN_VFPR64_M4_E64, + 3945 => Opcode::PseudoVFSGNJN_VFPR64_M4_E64_MASK, + 3946 => Opcode::PseudoVFSGNJN_VFPR64_M8_E64, + 3947 => Opcode::PseudoVFSGNJN_VFPR64_M8_E64_MASK, + 3948 => Opcode::PseudoVFSGNJN_VV_M1_E16, + 3949 => Opcode::PseudoVFSGNJN_VV_M1_E16_MASK, + 3950 => Opcode::PseudoVFSGNJN_VV_M1_E32, + 3951 => Opcode::PseudoVFSGNJN_VV_M1_E32_MASK, + 3952 => Opcode::PseudoVFSGNJN_VV_M1_E64, + 3953 => Opcode::PseudoVFSGNJN_VV_M1_E64_MASK, + 3954 => Opcode::PseudoVFSGNJN_VV_M2_E16, + 3955 => Opcode::PseudoVFSGNJN_VV_M2_E16_MASK, + 3956 => Opcode::PseudoVFSGNJN_VV_M2_E32, + 3957 => Opcode::PseudoVFSGNJN_VV_M2_E32_MASK, + 3958 => Opcode::PseudoVFSGNJN_VV_M2_E64, + 3959 => Opcode::PseudoVFSGNJN_VV_M2_E64_MASK, + 3960 => Opcode::PseudoVFSGNJN_VV_M4_E16, + 3961 => Opcode::PseudoVFSGNJN_VV_M4_E16_MASK, + 3962 => Opcode::PseudoVFSGNJN_VV_M4_E32, + 3963 => Opcode::PseudoVFSGNJN_VV_M4_E32_MASK, + 3964 => Opcode::PseudoVFSGNJN_VV_M4_E64, + 3965 => Opcode::PseudoVFSGNJN_VV_M4_E64_MASK, + 3966 => Opcode::PseudoVFSGNJN_VV_M8_E16, + 3967 => Opcode::PseudoVFSGNJN_VV_M8_E16_MASK, + 3968 => Opcode::PseudoVFSGNJN_VV_M8_E32, + 3969 => Opcode::PseudoVFSGNJN_VV_M8_E32_MASK, + 3970 => Opcode::PseudoVFSGNJN_VV_M8_E64, + 3971 => Opcode::PseudoVFSGNJN_VV_M8_E64_MASK, + 3972 => Opcode::PseudoVFSGNJN_VV_MF2_E16, + 3973 => Opcode::PseudoVFSGNJN_VV_MF2_E16_MASK, + 3974 => Opcode::PseudoVFSGNJN_VV_MF2_E32, + 3975 => Opcode::PseudoVFSGNJN_VV_MF2_E32_MASK, + 3976 => Opcode::PseudoVFSGNJN_VV_MF4_E16, + 3977 => Opcode::PseudoVFSGNJN_VV_MF4_E16_MASK, + 3978 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M1_E16, + 3979 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M1_E16_MASK, + 3980 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M2_E16, + 3981 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M2_E16_MASK, + 3982 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M4_E16, + 3983 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M4_E16_MASK, + 3984 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M8_E16, + 3985 => Opcode::PseudoVFSGNJX_ALT_VFPR16_M8_E16_MASK, + 3986 => Opcode::PseudoVFSGNJX_ALT_VFPR16_MF2_E16, + 3987 => Opcode::PseudoVFSGNJX_ALT_VFPR16_MF2_E16_MASK, + 3988 => Opcode::PseudoVFSGNJX_ALT_VFPR16_MF4_E16, + 3989 => Opcode::PseudoVFSGNJX_ALT_VFPR16_MF4_E16_MASK, + 3990 => Opcode::PseudoVFSGNJX_ALT_VV_M1_E16, + 3991 => Opcode::PseudoVFSGNJX_ALT_VV_M1_E16_MASK, + 3992 => Opcode::PseudoVFSGNJX_ALT_VV_M2_E16, + 3993 => Opcode::PseudoVFSGNJX_ALT_VV_M2_E16_MASK, + 3994 => Opcode::PseudoVFSGNJX_ALT_VV_M4_E16, + 3995 => Opcode::PseudoVFSGNJX_ALT_VV_M4_E16_MASK, + 3996 => Opcode::PseudoVFSGNJX_ALT_VV_M8_E16, + 3997 => Opcode::PseudoVFSGNJX_ALT_VV_M8_E16_MASK, + 3998 => Opcode::PseudoVFSGNJX_ALT_VV_MF2_E16, + 3999 => Opcode::PseudoVFSGNJX_ALT_VV_MF2_E16_MASK, + 4000 => Opcode::PseudoVFSGNJX_ALT_VV_MF4_E16, + 4001 => Opcode::PseudoVFSGNJX_ALT_VV_MF4_E16_MASK, + 4002 => Opcode::PseudoVFSGNJX_VFPR16_M1_E16, + 4003 => Opcode::PseudoVFSGNJX_VFPR16_M1_E16_MASK, + 4004 => Opcode::PseudoVFSGNJX_VFPR16_M2_E16, + 4005 => Opcode::PseudoVFSGNJX_VFPR16_M2_E16_MASK, + 4006 => Opcode::PseudoVFSGNJX_VFPR16_M4_E16, + 4007 => Opcode::PseudoVFSGNJX_VFPR16_M4_E16_MASK, + 4008 => Opcode::PseudoVFSGNJX_VFPR16_M8_E16, + 4009 => Opcode::PseudoVFSGNJX_VFPR16_M8_E16_MASK, + 4010 => Opcode::PseudoVFSGNJX_VFPR16_MF2_E16, + 4011 => Opcode::PseudoVFSGNJX_VFPR16_MF2_E16_MASK, + 4012 => Opcode::PseudoVFSGNJX_VFPR16_MF4_E16, + 4013 => Opcode::PseudoVFSGNJX_VFPR16_MF4_E16_MASK, + 4014 => Opcode::PseudoVFSGNJX_VFPR32_M1_E32, + 4015 => Opcode::PseudoVFSGNJX_VFPR32_M1_E32_MASK, + 4016 => Opcode::PseudoVFSGNJX_VFPR32_M2_E32, + 4017 => Opcode::PseudoVFSGNJX_VFPR32_M2_E32_MASK, + 4018 => Opcode::PseudoVFSGNJX_VFPR32_M4_E32, + 4019 => Opcode::PseudoVFSGNJX_VFPR32_M4_E32_MASK, + 4020 => Opcode::PseudoVFSGNJX_VFPR32_M8_E32, + 4021 => Opcode::PseudoVFSGNJX_VFPR32_M8_E32_MASK, + 4022 => Opcode::PseudoVFSGNJX_VFPR32_MF2_E32, + 4023 => Opcode::PseudoVFSGNJX_VFPR32_MF2_E32_MASK, + 4024 => Opcode::PseudoVFSGNJX_VFPR64_M1_E64, + 4025 => Opcode::PseudoVFSGNJX_VFPR64_M1_E64_MASK, + 4026 => Opcode::PseudoVFSGNJX_VFPR64_M2_E64, + 4027 => Opcode::PseudoVFSGNJX_VFPR64_M2_E64_MASK, + 4028 => Opcode::PseudoVFSGNJX_VFPR64_M4_E64, + 4029 => Opcode::PseudoVFSGNJX_VFPR64_M4_E64_MASK, + 4030 => Opcode::PseudoVFSGNJX_VFPR64_M8_E64, + 4031 => Opcode::PseudoVFSGNJX_VFPR64_M8_E64_MASK, + 4032 => Opcode::PseudoVFSGNJX_VV_M1_E16, + 4033 => Opcode::PseudoVFSGNJX_VV_M1_E16_MASK, + 4034 => Opcode::PseudoVFSGNJX_VV_M1_E32, + 4035 => Opcode::PseudoVFSGNJX_VV_M1_E32_MASK, + 4036 => Opcode::PseudoVFSGNJX_VV_M1_E64, + 4037 => Opcode::PseudoVFSGNJX_VV_M1_E64_MASK, + 4038 => Opcode::PseudoVFSGNJX_VV_M2_E16, + 4039 => Opcode::PseudoVFSGNJX_VV_M2_E16_MASK, + 4040 => Opcode::PseudoVFSGNJX_VV_M2_E32, + 4041 => Opcode::PseudoVFSGNJX_VV_M2_E32_MASK, + 4042 => Opcode::PseudoVFSGNJX_VV_M2_E64, + 4043 => Opcode::PseudoVFSGNJX_VV_M2_E64_MASK, + 4044 => Opcode::PseudoVFSGNJX_VV_M4_E16, + 4045 => Opcode::PseudoVFSGNJX_VV_M4_E16_MASK, + 4046 => Opcode::PseudoVFSGNJX_VV_M4_E32, + 4047 => Opcode::PseudoVFSGNJX_VV_M4_E32_MASK, + 4048 => Opcode::PseudoVFSGNJX_VV_M4_E64, + 4049 => Opcode::PseudoVFSGNJX_VV_M4_E64_MASK, + 4050 => Opcode::PseudoVFSGNJX_VV_M8_E16, + 4051 => Opcode::PseudoVFSGNJX_VV_M8_E16_MASK, + 4052 => Opcode::PseudoVFSGNJX_VV_M8_E32, + 4053 => Opcode::PseudoVFSGNJX_VV_M8_E32_MASK, + 4054 => Opcode::PseudoVFSGNJX_VV_M8_E64, + 4055 => Opcode::PseudoVFSGNJX_VV_M8_E64_MASK, + 4056 => Opcode::PseudoVFSGNJX_VV_MF2_E16, + 4057 => Opcode::PseudoVFSGNJX_VV_MF2_E16_MASK, + 4058 => Opcode::PseudoVFSGNJX_VV_MF2_E32, + 4059 => Opcode::PseudoVFSGNJX_VV_MF2_E32_MASK, + 4060 => Opcode::PseudoVFSGNJX_VV_MF4_E16, + 4061 => Opcode::PseudoVFSGNJX_VV_MF4_E16_MASK, + 4062 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M1_E16, + 4063 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M1_E16_MASK, + 4064 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M2_E16, + 4065 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M2_E16_MASK, + 4066 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M4_E16, + 4067 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M4_E16_MASK, + 4068 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M8_E16, + 4069 => Opcode::PseudoVFSGNJ_ALT_VFPR16_M8_E16_MASK, + 4070 => Opcode::PseudoVFSGNJ_ALT_VFPR16_MF2_E16, + 4071 => Opcode::PseudoVFSGNJ_ALT_VFPR16_MF2_E16_MASK, + 4072 => Opcode::PseudoVFSGNJ_ALT_VFPR16_MF4_E16, + 4073 => Opcode::PseudoVFSGNJ_ALT_VFPR16_MF4_E16_MASK, + 4074 => Opcode::PseudoVFSGNJ_ALT_VV_M1_E16, + 4075 => Opcode::PseudoVFSGNJ_ALT_VV_M1_E16_MASK, + 4076 => Opcode::PseudoVFSGNJ_ALT_VV_M2_E16, + 4077 => Opcode::PseudoVFSGNJ_ALT_VV_M2_E16_MASK, + 4078 => Opcode::PseudoVFSGNJ_ALT_VV_M4_E16, + 4079 => Opcode::PseudoVFSGNJ_ALT_VV_M4_E16_MASK, + 4080 => Opcode::PseudoVFSGNJ_ALT_VV_M8_E16, + 4081 => Opcode::PseudoVFSGNJ_ALT_VV_M8_E16_MASK, + 4082 => Opcode::PseudoVFSGNJ_ALT_VV_MF2_E16, + 4083 => Opcode::PseudoVFSGNJ_ALT_VV_MF2_E16_MASK, + 4084 => Opcode::PseudoVFSGNJ_ALT_VV_MF4_E16, + 4085 => Opcode::PseudoVFSGNJ_ALT_VV_MF4_E16_MASK, + 4086 => Opcode::PseudoVFSGNJ_VFPR16_M1_E16, + 4087 => Opcode::PseudoVFSGNJ_VFPR16_M1_E16_MASK, + 4088 => Opcode::PseudoVFSGNJ_VFPR16_M2_E16, + 4089 => Opcode::PseudoVFSGNJ_VFPR16_M2_E16_MASK, + 4090 => Opcode::PseudoVFSGNJ_VFPR16_M4_E16, + 4091 => Opcode::PseudoVFSGNJ_VFPR16_M4_E16_MASK, + 4092 => Opcode::PseudoVFSGNJ_VFPR16_M8_E16, + 4093 => Opcode::PseudoVFSGNJ_VFPR16_M8_E16_MASK, + 4094 => Opcode::PseudoVFSGNJ_VFPR16_MF2_E16, + 4095 => Opcode::PseudoVFSGNJ_VFPR16_MF2_E16_MASK, + 4096 => Opcode::PseudoVFSGNJ_VFPR16_MF4_E16, + 4097 => Opcode::PseudoVFSGNJ_VFPR16_MF4_E16_MASK, + 4098 => Opcode::PseudoVFSGNJ_VFPR32_M1_E32, + 4099 => Opcode::PseudoVFSGNJ_VFPR32_M1_E32_MASK, + 4100 => Opcode::PseudoVFSGNJ_VFPR32_M2_E32, + 4101 => Opcode::PseudoVFSGNJ_VFPR32_M2_E32_MASK, + 4102 => Opcode::PseudoVFSGNJ_VFPR32_M4_E32, + 4103 => Opcode::PseudoVFSGNJ_VFPR32_M4_E32_MASK, + 4104 => Opcode::PseudoVFSGNJ_VFPR32_M8_E32, + 4105 => Opcode::PseudoVFSGNJ_VFPR32_M8_E32_MASK, + 4106 => Opcode::PseudoVFSGNJ_VFPR32_MF2_E32, + 4107 => Opcode::PseudoVFSGNJ_VFPR32_MF2_E32_MASK, + 4108 => Opcode::PseudoVFSGNJ_VFPR64_M1_E64, + 4109 => Opcode::PseudoVFSGNJ_VFPR64_M1_E64_MASK, + 4110 => Opcode::PseudoVFSGNJ_VFPR64_M2_E64, + 4111 => Opcode::PseudoVFSGNJ_VFPR64_M2_E64_MASK, + 4112 => Opcode::PseudoVFSGNJ_VFPR64_M4_E64, + 4113 => Opcode::PseudoVFSGNJ_VFPR64_M4_E64_MASK, + 4114 => Opcode::PseudoVFSGNJ_VFPR64_M8_E64, + 4115 => Opcode::PseudoVFSGNJ_VFPR64_M8_E64_MASK, + 4116 => Opcode::PseudoVFSGNJ_VV_M1_E16, + 4117 => Opcode::PseudoVFSGNJ_VV_M1_E16_MASK, + 4118 => Opcode::PseudoVFSGNJ_VV_M1_E32, + 4119 => Opcode::PseudoVFSGNJ_VV_M1_E32_MASK, + 4120 => Opcode::PseudoVFSGNJ_VV_M1_E64, + 4121 => Opcode::PseudoVFSGNJ_VV_M1_E64_MASK, + 4122 => Opcode::PseudoVFSGNJ_VV_M2_E16, + 4123 => Opcode::PseudoVFSGNJ_VV_M2_E16_MASK, + 4124 => Opcode::PseudoVFSGNJ_VV_M2_E32, + 4125 => Opcode::PseudoVFSGNJ_VV_M2_E32_MASK, + 4126 => Opcode::PseudoVFSGNJ_VV_M2_E64, + 4127 => Opcode::PseudoVFSGNJ_VV_M2_E64_MASK, + 4128 => Opcode::PseudoVFSGNJ_VV_M4_E16, + 4129 => Opcode::PseudoVFSGNJ_VV_M4_E16_MASK, + 4130 => Opcode::PseudoVFSGNJ_VV_M4_E32, + 4131 => Opcode::PseudoVFSGNJ_VV_M4_E32_MASK, + 4132 => Opcode::PseudoVFSGNJ_VV_M4_E64, + 4133 => Opcode::PseudoVFSGNJ_VV_M4_E64_MASK, + 4134 => Opcode::PseudoVFSGNJ_VV_M8_E16, + 4135 => Opcode::PseudoVFSGNJ_VV_M8_E16_MASK, + 4136 => Opcode::PseudoVFSGNJ_VV_M8_E32, + 4137 => Opcode::PseudoVFSGNJ_VV_M8_E32_MASK, + 4138 => Opcode::PseudoVFSGNJ_VV_M8_E64, + 4139 => Opcode::PseudoVFSGNJ_VV_M8_E64_MASK, + 4140 => Opcode::PseudoVFSGNJ_VV_MF2_E16, + 4141 => Opcode::PseudoVFSGNJ_VV_MF2_E16_MASK, + 4142 => Opcode::PseudoVFSGNJ_VV_MF2_E32, + 4143 => Opcode::PseudoVFSGNJ_VV_MF2_E32_MASK, + 4144 => Opcode::PseudoVFSGNJ_VV_MF4_E16, + 4145 => Opcode::PseudoVFSGNJ_VV_MF4_E16_MASK, + 4146 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M1, + 4147 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M1_MASK, + 4148 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M2, + 4149 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M2_MASK, + 4150 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M4, + 4151 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M4_MASK, + 4152 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M8, + 4153 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_M8_MASK, + 4154 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2, + 4155 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF2_MASK, + 4156 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4, + 4157 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR16_MF4_MASK, + 4158 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M1, + 4159 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M1_MASK, + 4160 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M2, + 4161 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M2_MASK, + 4162 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M4, + 4163 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M4_MASK, + 4164 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M8, + 4165 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_M8_MASK, + 4166 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2, + 4167 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR32_MF2_MASK, + 4168 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M1, + 4169 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M1_MASK, + 4170 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M2, + 4171 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M2_MASK, + 4172 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M4, + 4173 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M4_MASK, + 4174 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M8, + 4175 => Opcode::PseudoVFSLIDE1DOWN_ALT_VFPR64_M8_MASK, + 4176 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M1, + 4177 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, + 4178 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M2, + 4179 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, + 4180 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M4, + 4181 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, + 4182 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M8, + 4183 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, + 4184 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF2, + 4185 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, + 4186 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF4, + 4187 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, + 4188 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M1, + 4189 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, + 4190 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M2, + 4191 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, + 4192 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M4, + 4193 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, + 4194 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M8, + 4195 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, + 4196 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_MF2, + 4197 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, + 4198 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M1, + 4199 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, + 4200 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M2, + 4201 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, + 4202 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M4, + 4203 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, + 4204 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M8, + 4205 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, + 4206 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M1, + 4207 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M1_MASK, + 4208 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M2, + 4209 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M2_MASK, + 4210 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M4, + 4211 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M4_MASK, + 4212 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M8, + 4213 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_M8_MASK, + 4214 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_MF2, + 4215 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_MF2_MASK, + 4216 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_MF4, + 4217 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR16_MF4_MASK, + 4218 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M1, + 4219 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M1_MASK, + 4220 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M2, + 4221 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M2_MASK, + 4222 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M4, + 4223 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M4_MASK, + 4224 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M8, + 4225 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_M8_MASK, + 4226 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_MF2, + 4227 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR32_MF2_MASK, + 4228 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M1, + 4229 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M1_MASK, + 4230 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M2, + 4231 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M2_MASK, + 4232 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M4, + 4233 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M4_MASK, + 4234 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M8, + 4235 => Opcode::PseudoVFSLIDE1UP_ALT_VFPR64_M8_MASK, + 4236 => Opcode::PseudoVFSLIDE1UP_VFPR16_M1, + 4237 => Opcode::PseudoVFSLIDE1UP_VFPR16_M1_MASK, + 4238 => Opcode::PseudoVFSLIDE1UP_VFPR16_M2, + 4239 => Opcode::PseudoVFSLIDE1UP_VFPR16_M2_MASK, + 4240 => Opcode::PseudoVFSLIDE1UP_VFPR16_M4, + 4241 => Opcode::PseudoVFSLIDE1UP_VFPR16_M4_MASK, + 4242 => Opcode::PseudoVFSLIDE1UP_VFPR16_M8, + 4243 => Opcode::PseudoVFSLIDE1UP_VFPR16_M8_MASK, + 4244 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF2, + 4245 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF2_MASK, + 4246 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF4, + 4247 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF4_MASK, + 4248 => Opcode::PseudoVFSLIDE1UP_VFPR32_M1, + 4249 => Opcode::PseudoVFSLIDE1UP_VFPR32_M1_MASK, + 4250 => Opcode::PseudoVFSLIDE1UP_VFPR32_M2, + 4251 => Opcode::PseudoVFSLIDE1UP_VFPR32_M2_MASK, + 4252 => Opcode::PseudoVFSLIDE1UP_VFPR32_M4, + 4253 => Opcode::PseudoVFSLIDE1UP_VFPR32_M4_MASK, + 4254 => Opcode::PseudoVFSLIDE1UP_VFPR32_M8, + 4255 => Opcode::PseudoVFSLIDE1UP_VFPR32_M8_MASK, + 4256 => Opcode::PseudoVFSLIDE1UP_VFPR32_MF2, + 4257 => Opcode::PseudoVFSLIDE1UP_VFPR32_MF2_MASK, + 4258 => Opcode::PseudoVFSLIDE1UP_VFPR64_M1, + 4259 => Opcode::PseudoVFSLIDE1UP_VFPR64_M1_MASK, + 4260 => Opcode::PseudoVFSLIDE1UP_VFPR64_M2, + 4261 => Opcode::PseudoVFSLIDE1UP_VFPR64_M2_MASK, + 4262 => Opcode::PseudoVFSLIDE1UP_VFPR64_M4, + 4263 => Opcode::PseudoVFSLIDE1UP_VFPR64_M4_MASK, + 4264 => Opcode::PseudoVFSLIDE1UP_VFPR64_M8, + 4265 => Opcode::PseudoVFSLIDE1UP_VFPR64_M8_MASK, + 4266 => Opcode::PseudoVFSQRT_V_M1_E16, + 4267 => Opcode::PseudoVFSQRT_V_M1_E16_MASK, + 4268 => Opcode::PseudoVFSQRT_V_M1_E32, + 4269 => Opcode::PseudoVFSQRT_V_M1_E32_MASK, + 4270 => Opcode::PseudoVFSQRT_V_M1_E64, + 4271 => Opcode::PseudoVFSQRT_V_M1_E64_MASK, + 4272 => Opcode::PseudoVFSQRT_V_M2_E16, + 4273 => Opcode::PseudoVFSQRT_V_M2_E16_MASK, + 4274 => Opcode::PseudoVFSQRT_V_M2_E32, + 4275 => Opcode::PseudoVFSQRT_V_M2_E32_MASK, + 4276 => Opcode::PseudoVFSQRT_V_M2_E64, + 4277 => Opcode::PseudoVFSQRT_V_M2_E64_MASK, + 4278 => Opcode::PseudoVFSQRT_V_M4_E16, + 4279 => Opcode::PseudoVFSQRT_V_M4_E16_MASK, + 4280 => Opcode::PseudoVFSQRT_V_M4_E32, + 4281 => Opcode::PseudoVFSQRT_V_M4_E32_MASK, + 4282 => Opcode::PseudoVFSQRT_V_M4_E64, + 4283 => Opcode::PseudoVFSQRT_V_M4_E64_MASK, + 4284 => Opcode::PseudoVFSQRT_V_M8_E16, + 4285 => Opcode::PseudoVFSQRT_V_M8_E16_MASK, + 4286 => Opcode::PseudoVFSQRT_V_M8_E32, + 4287 => Opcode::PseudoVFSQRT_V_M8_E32_MASK, + 4288 => Opcode::PseudoVFSQRT_V_M8_E64, + 4289 => Opcode::PseudoVFSQRT_V_M8_E64_MASK, + 4290 => Opcode::PseudoVFSQRT_V_MF2_E16, + 4291 => Opcode::PseudoVFSQRT_V_MF2_E16_MASK, + 4292 => Opcode::PseudoVFSQRT_V_MF2_E32, + 4293 => Opcode::PseudoVFSQRT_V_MF2_E32_MASK, + 4294 => Opcode::PseudoVFSQRT_V_MF4_E16, + 4295 => Opcode::PseudoVFSQRT_V_MF4_E16_MASK, + 4296 => Opcode::PseudoVFSUB_ALT_VFPR16_M1_E16, + 4297 => Opcode::PseudoVFSUB_ALT_VFPR16_M1_E16_MASK, + 4298 => Opcode::PseudoVFSUB_ALT_VFPR16_M2_E16, + 4299 => Opcode::PseudoVFSUB_ALT_VFPR16_M2_E16_MASK, + 4300 => Opcode::PseudoVFSUB_ALT_VFPR16_M4_E16, + 4301 => Opcode::PseudoVFSUB_ALT_VFPR16_M4_E16_MASK, + 4302 => Opcode::PseudoVFSUB_ALT_VFPR16_M8_E16, + 4303 => Opcode::PseudoVFSUB_ALT_VFPR16_M8_E16_MASK, + 4304 => Opcode::PseudoVFSUB_ALT_VFPR16_MF2_E16, + 4305 => Opcode::PseudoVFSUB_ALT_VFPR16_MF2_E16_MASK, + 4306 => Opcode::PseudoVFSUB_ALT_VFPR16_MF4_E16, + 4307 => Opcode::PseudoVFSUB_ALT_VFPR16_MF4_E16_MASK, + 4308 => Opcode::PseudoVFSUB_ALT_VV_M1_E16, + 4309 => Opcode::PseudoVFSUB_ALT_VV_M1_E16_MASK, + 4310 => Opcode::PseudoVFSUB_ALT_VV_M2_E16, + 4311 => Opcode::PseudoVFSUB_ALT_VV_M2_E16_MASK, + 4312 => Opcode::PseudoVFSUB_ALT_VV_M4_E16, + 4313 => Opcode::PseudoVFSUB_ALT_VV_M4_E16_MASK, + 4314 => Opcode::PseudoVFSUB_ALT_VV_M8_E16, + 4315 => Opcode::PseudoVFSUB_ALT_VV_M8_E16_MASK, + 4316 => Opcode::PseudoVFSUB_ALT_VV_MF2_E16, + 4317 => Opcode::PseudoVFSUB_ALT_VV_MF2_E16_MASK, + 4318 => Opcode::PseudoVFSUB_ALT_VV_MF4_E16, + 4319 => Opcode::PseudoVFSUB_ALT_VV_MF4_E16_MASK, + 4320 => Opcode::PseudoVFSUB_VFPR16_M1_E16, + 4321 => Opcode::PseudoVFSUB_VFPR16_M1_E16_MASK, + 4322 => Opcode::PseudoVFSUB_VFPR16_M2_E16, + 4323 => Opcode::PseudoVFSUB_VFPR16_M2_E16_MASK, + 4324 => Opcode::PseudoVFSUB_VFPR16_M4_E16, + 4325 => Opcode::PseudoVFSUB_VFPR16_M4_E16_MASK, + 4326 => Opcode::PseudoVFSUB_VFPR16_M8_E16, + 4327 => Opcode::PseudoVFSUB_VFPR16_M8_E16_MASK, + 4328 => Opcode::PseudoVFSUB_VFPR16_MF2_E16, + 4329 => Opcode::PseudoVFSUB_VFPR16_MF2_E16_MASK, + 4330 => Opcode::PseudoVFSUB_VFPR16_MF4_E16, + 4331 => Opcode::PseudoVFSUB_VFPR16_MF4_E16_MASK, + 4332 => Opcode::PseudoVFSUB_VFPR32_M1_E32, + 4333 => Opcode::PseudoVFSUB_VFPR32_M1_E32_MASK, + 4334 => Opcode::PseudoVFSUB_VFPR32_M2_E32, + 4335 => Opcode::PseudoVFSUB_VFPR32_M2_E32_MASK, + 4336 => Opcode::PseudoVFSUB_VFPR32_M4_E32, + 4337 => Opcode::PseudoVFSUB_VFPR32_M4_E32_MASK, + 4338 => Opcode::PseudoVFSUB_VFPR32_M8_E32, + 4339 => Opcode::PseudoVFSUB_VFPR32_M8_E32_MASK, + 4340 => Opcode::PseudoVFSUB_VFPR32_MF2_E32, + 4341 => Opcode::PseudoVFSUB_VFPR32_MF2_E32_MASK, + 4342 => Opcode::PseudoVFSUB_VFPR64_M1_E64, + 4343 => Opcode::PseudoVFSUB_VFPR64_M1_E64_MASK, + 4344 => Opcode::PseudoVFSUB_VFPR64_M2_E64, + 4345 => Opcode::PseudoVFSUB_VFPR64_M2_E64_MASK, + 4346 => Opcode::PseudoVFSUB_VFPR64_M4_E64, + 4347 => Opcode::PseudoVFSUB_VFPR64_M4_E64_MASK, + 4348 => Opcode::PseudoVFSUB_VFPR64_M8_E64, + 4349 => Opcode::PseudoVFSUB_VFPR64_M8_E64_MASK, + 4350 => Opcode::PseudoVFSUB_VV_M1_E16, + 4351 => Opcode::PseudoVFSUB_VV_M1_E16_MASK, + 4352 => Opcode::PseudoVFSUB_VV_M1_E32, + 4353 => Opcode::PseudoVFSUB_VV_M1_E32_MASK, + 4354 => Opcode::PseudoVFSUB_VV_M1_E64, + 4355 => Opcode::PseudoVFSUB_VV_M1_E64_MASK, + 4356 => Opcode::PseudoVFSUB_VV_M2_E16, + 4357 => Opcode::PseudoVFSUB_VV_M2_E16_MASK, + 4358 => Opcode::PseudoVFSUB_VV_M2_E32, + 4359 => Opcode::PseudoVFSUB_VV_M2_E32_MASK, + 4360 => Opcode::PseudoVFSUB_VV_M2_E64, + 4361 => Opcode::PseudoVFSUB_VV_M2_E64_MASK, + 4362 => Opcode::PseudoVFSUB_VV_M4_E16, + 4363 => Opcode::PseudoVFSUB_VV_M4_E16_MASK, + 4364 => Opcode::PseudoVFSUB_VV_M4_E32, + 4365 => Opcode::PseudoVFSUB_VV_M4_E32_MASK, + 4366 => Opcode::PseudoVFSUB_VV_M4_E64, + 4367 => Opcode::PseudoVFSUB_VV_M4_E64_MASK, + 4368 => Opcode::PseudoVFSUB_VV_M8_E16, + 4369 => Opcode::PseudoVFSUB_VV_M8_E16_MASK, + 4370 => Opcode::PseudoVFSUB_VV_M8_E32, + 4371 => Opcode::PseudoVFSUB_VV_M8_E32_MASK, + 4372 => Opcode::PseudoVFSUB_VV_M8_E64, + 4373 => Opcode::PseudoVFSUB_VV_M8_E64_MASK, + 4374 => Opcode::PseudoVFSUB_VV_MF2_E16, + 4375 => Opcode::PseudoVFSUB_VV_MF2_E16_MASK, + 4376 => Opcode::PseudoVFSUB_VV_MF2_E32, + 4377 => Opcode::PseudoVFSUB_VV_MF2_E32_MASK, + 4378 => Opcode::PseudoVFSUB_VV_MF4_E16, + 4379 => Opcode::PseudoVFSUB_VV_MF4_E16_MASK, + 4380 => Opcode::PseudoVFWADD_ALT_VFPR16_M1_E16, + 4381 => Opcode::PseudoVFWADD_ALT_VFPR16_M1_E16_MASK, + 4382 => Opcode::PseudoVFWADD_ALT_VFPR16_M2_E16, + 4383 => Opcode::PseudoVFWADD_ALT_VFPR16_M2_E16_MASK, + 4384 => Opcode::PseudoVFWADD_ALT_VFPR16_M4_E16, + 4385 => Opcode::PseudoVFWADD_ALT_VFPR16_M4_E16_MASK, + 4386 => Opcode::PseudoVFWADD_ALT_VFPR16_MF2_E16, + 4387 => Opcode::PseudoVFWADD_ALT_VFPR16_MF2_E16_MASK, + 4388 => Opcode::PseudoVFWADD_ALT_VFPR16_MF4_E16, + 4389 => Opcode::PseudoVFWADD_ALT_VFPR16_MF4_E16_MASK, + 4390 => Opcode::PseudoVFWADD_ALT_VV_M1_E16, + 4391 => Opcode::PseudoVFWADD_ALT_VV_M1_E16_MASK, + 4392 => Opcode::PseudoVFWADD_ALT_VV_M2_E16, + 4393 => Opcode::PseudoVFWADD_ALT_VV_M2_E16_MASK, + 4394 => Opcode::PseudoVFWADD_ALT_VV_M4_E16, + 4395 => Opcode::PseudoVFWADD_ALT_VV_M4_E16_MASK, + 4396 => Opcode::PseudoVFWADD_ALT_VV_MF2_E16, + 4397 => Opcode::PseudoVFWADD_ALT_VV_MF2_E16_MASK, + 4398 => Opcode::PseudoVFWADD_ALT_VV_MF4_E16, + 4399 => Opcode::PseudoVFWADD_ALT_VV_MF4_E16_MASK, + 4400 => Opcode::PseudoVFWADD_ALT_WFPR16_M1_E16, + 4401 => Opcode::PseudoVFWADD_ALT_WFPR16_M1_E16_MASK, + 4402 => Opcode::PseudoVFWADD_ALT_WFPR16_M2_E16, + 4403 => Opcode::PseudoVFWADD_ALT_WFPR16_M2_E16_MASK, + 4404 => Opcode::PseudoVFWADD_ALT_WFPR16_M4_E16, + 4405 => Opcode::PseudoVFWADD_ALT_WFPR16_M4_E16_MASK, + 4406 => Opcode::PseudoVFWADD_ALT_WFPR16_MF2_E16, + 4407 => Opcode::PseudoVFWADD_ALT_WFPR16_MF2_E16_MASK, + 4408 => Opcode::PseudoVFWADD_ALT_WFPR16_MF4_E16, + 4409 => Opcode::PseudoVFWADD_ALT_WFPR16_MF4_E16_MASK, + 4410 => Opcode::PseudoVFWADD_ALT_WV_M1_E16, + 4411 => Opcode::PseudoVFWADD_ALT_WV_M1_E16_MASK, + 4412 => Opcode::PseudoVFWADD_ALT_WV_M1_E16_MASK_TIED, + 4413 => Opcode::PseudoVFWADD_ALT_WV_M1_E16_TIED, + 4414 => Opcode::PseudoVFWADD_ALT_WV_M2_E16, + 4415 => Opcode::PseudoVFWADD_ALT_WV_M2_E16_MASK, + 4416 => Opcode::PseudoVFWADD_ALT_WV_M2_E16_MASK_TIED, + 4417 => Opcode::PseudoVFWADD_ALT_WV_M2_E16_TIED, + 4418 => Opcode::PseudoVFWADD_ALT_WV_M4_E16, + 4419 => Opcode::PseudoVFWADD_ALT_WV_M4_E16_MASK, + 4420 => Opcode::PseudoVFWADD_ALT_WV_M4_E16_MASK_TIED, + 4421 => Opcode::PseudoVFWADD_ALT_WV_M4_E16_TIED, + 4422 => Opcode::PseudoVFWADD_ALT_WV_MF2_E16, + 4423 => Opcode::PseudoVFWADD_ALT_WV_MF2_E16_MASK, + 4424 => Opcode::PseudoVFWADD_ALT_WV_MF2_E16_MASK_TIED, + 4425 => Opcode::PseudoVFWADD_ALT_WV_MF2_E16_TIED, + 4426 => Opcode::PseudoVFWADD_ALT_WV_MF4_E16, + 4427 => Opcode::PseudoVFWADD_ALT_WV_MF4_E16_MASK, + 4428 => Opcode::PseudoVFWADD_ALT_WV_MF4_E16_MASK_TIED, + 4429 => Opcode::PseudoVFWADD_ALT_WV_MF4_E16_TIED, + 4430 => Opcode::PseudoVFWADD_VFPR16_M1_E16, + 4431 => Opcode::PseudoVFWADD_VFPR16_M1_E16_MASK, + 4432 => Opcode::PseudoVFWADD_VFPR16_M2_E16, + 4433 => Opcode::PseudoVFWADD_VFPR16_M2_E16_MASK, + 4434 => Opcode::PseudoVFWADD_VFPR16_M4_E16, + 4435 => Opcode::PseudoVFWADD_VFPR16_M4_E16_MASK, + 4436 => Opcode::PseudoVFWADD_VFPR16_MF2_E16, + 4437 => Opcode::PseudoVFWADD_VFPR16_MF2_E16_MASK, + 4438 => Opcode::PseudoVFWADD_VFPR16_MF4_E16, + 4439 => Opcode::PseudoVFWADD_VFPR16_MF4_E16_MASK, + 4440 => Opcode::PseudoVFWADD_VFPR32_M1_E32, + 4441 => Opcode::PseudoVFWADD_VFPR32_M1_E32_MASK, + 4442 => Opcode::PseudoVFWADD_VFPR32_M2_E32, + 4443 => Opcode::PseudoVFWADD_VFPR32_M2_E32_MASK, + 4444 => Opcode::PseudoVFWADD_VFPR32_M4_E32, + 4445 => Opcode::PseudoVFWADD_VFPR32_M4_E32_MASK, + 4446 => Opcode::PseudoVFWADD_VFPR32_MF2_E32, + 4447 => Opcode::PseudoVFWADD_VFPR32_MF2_E32_MASK, + 4448 => Opcode::PseudoVFWADD_VV_M1_E16, + 4449 => Opcode::PseudoVFWADD_VV_M1_E16_MASK, + 4450 => Opcode::PseudoVFWADD_VV_M1_E32, + 4451 => Opcode::PseudoVFWADD_VV_M1_E32_MASK, + 4452 => Opcode::PseudoVFWADD_VV_M2_E16, + 4453 => Opcode::PseudoVFWADD_VV_M2_E16_MASK, + 4454 => Opcode::PseudoVFWADD_VV_M2_E32, + 4455 => Opcode::PseudoVFWADD_VV_M2_E32_MASK, + 4456 => Opcode::PseudoVFWADD_VV_M4_E16, + 4457 => Opcode::PseudoVFWADD_VV_M4_E16_MASK, + 4458 => Opcode::PseudoVFWADD_VV_M4_E32, + 4459 => Opcode::PseudoVFWADD_VV_M4_E32_MASK, + 4460 => Opcode::PseudoVFWADD_VV_MF2_E16, + 4461 => Opcode::PseudoVFWADD_VV_MF2_E16_MASK, + 4462 => Opcode::PseudoVFWADD_VV_MF2_E32, + 4463 => Opcode::PseudoVFWADD_VV_MF2_E32_MASK, + 4464 => Opcode::PseudoVFWADD_VV_MF4_E16, + 4465 => Opcode::PseudoVFWADD_VV_MF4_E16_MASK, + 4466 => Opcode::PseudoVFWADD_WFPR16_M1_E16, + 4467 => Opcode::PseudoVFWADD_WFPR16_M1_E16_MASK, + 4468 => Opcode::PseudoVFWADD_WFPR16_M2_E16, + 4469 => Opcode::PseudoVFWADD_WFPR16_M2_E16_MASK, + 4470 => Opcode::PseudoVFWADD_WFPR16_M4_E16, + 4471 => Opcode::PseudoVFWADD_WFPR16_M4_E16_MASK, + 4472 => Opcode::PseudoVFWADD_WFPR16_MF2_E16, + 4473 => Opcode::PseudoVFWADD_WFPR16_MF2_E16_MASK, + 4474 => Opcode::PseudoVFWADD_WFPR16_MF4_E16, + 4475 => Opcode::PseudoVFWADD_WFPR16_MF4_E16_MASK, + 4476 => Opcode::PseudoVFWADD_WFPR32_M1_E32, + 4477 => Opcode::PseudoVFWADD_WFPR32_M1_E32_MASK, + 4478 => Opcode::PseudoVFWADD_WFPR32_M2_E32, + 4479 => Opcode::PseudoVFWADD_WFPR32_M2_E32_MASK, + 4480 => Opcode::PseudoVFWADD_WFPR32_M4_E32, + 4481 => Opcode::PseudoVFWADD_WFPR32_M4_E32_MASK, + 4482 => Opcode::PseudoVFWADD_WFPR32_MF2_E32, + 4483 => Opcode::PseudoVFWADD_WFPR32_MF2_E32_MASK, + 4484 => Opcode::PseudoVFWADD_WV_M1_E16, + 4485 => Opcode::PseudoVFWADD_WV_M1_E16_MASK, + 4486 => Opcode::PseudoVFWADD_WV_M1_E16_MASK_TIED, + 4487 => Opcode::PseudoVFWADD_WV_M1_E16_TIED, + 4488 => Opcode::PseudoVFWADD_WV_M1_E32, + 4489 => Opcode::PseudoVFWADD_WV_M1_E32_MASK, + 4490 => Opcode::PseudoVFWADD_WV_M1_E32_MASK_TIED, + 4491 => Opcode::PseudoVFWADD_WV_M1_E32_TIED, + 4492 => Opcode::PseudoVFWADD_WV_M2_E16, + 4493 => Opcode::PseudoVFWADD_WV_M2_E16_MASK, + 4494 => Opcode::PseudoVFWADD_WV_M2_E16_MASK_TIED, + 4495 => Opcode::PseudoVFWADD_WV_M2_E16_TIED, + 4496 => Opcode::PseudoVFWADD_WV_M2_E32, + 4497 => Opcode::PseudoVFWADD_WV_M2_E32_MASK, + 4498 => Opcode::PseudoVFWADD_WV_M2_E32_MASK_TIED, + 4499 => Opcode::PseudoVFWADD_WV_M2_E32_TIED, + 4500 => Opcode::PseudoVFWADD_WV_M4_E16, + 4501 => Opcode::PseudoVFWADD_WV_M4_E16_MASK, + 4502 => Opcode::PseudoVFWADD_WV_M4_E16_MASK_TIED, + 4503 => Opcode::PseudoVFWADD_WV_M4_E16_TIED, + 4504 => Opcode::PseudoVFWADD_WV_M4_E32, + 4505 => Opcode::PseudoVFWADD_WV_M4_E32_MASK, + 4506 => Opcode::PseudoVFWADD_WV_M4_E32_MASK_TIED, + 4507 => Opcode::PseudoVFWADD_WV_M4_E32_TIED, + 4508 => Opcode::PseudoVFWADD_WV_MF2_E16, + 4509 => Opcode::PseudoVFWADD_WV_MF2_E16_MASK, + 4510 => Opcode::PseudoVFWADD_WV_MF2_E16_MASK_TIED, + 4511 => Opcode::PseudoVFWADD_WV_MF2_E16_TIED, + 4512 => Opcode::PseudoVFWADD_WV_MF2_E32, + 4513 => Opcode::PseudoVFWADD_WV_MF2_E32_MASK, + 4514 => Opcode::PseudoVFWADD_WV_MF2_E32_MASK_TIED, + 4515 => Opcode::PseudoVFWADD_WV_MF2_E32_TIED, + 4516 => Opcode::PseudoVFWADD_WV_MF4_E16, + 4517 => Opcode::PseudoVFWADD_WV_MF4_E16_MASK, + 4518 => Opcode::PseudoVFWADD_WV_MF4_E16_MASK_TIED, + 4519 => Opcode::PseudoVFWADD_WV_MF4_E16_TIED, + 4520 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M1_E8, + 4521 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M1_E8_MASK, + 4522 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M2_E8, + 4523 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M2_E8_MASK, + 4524 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M4_E8, + 4525 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_M4_E8_MASK, + 4526 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8, + 4527 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF2_E8_MASK, + 4528 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8, + 4529 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF4_E8_MASK, + 4530 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8, + 4531 => Opcode::PseudoVFWCVTBF16_F_F_ALT_V_MF8_E8_MASK, + 4532 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E16, + 4533 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, + 4534 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E32, + 4535 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, + 4536 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E8, + 4537 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E8_MASK, + 4538 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E16, + 4539 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, + 4540 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E32, + 4541 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, + 4542 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E8, + 4543 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E8_MASK, + 4544 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E16, + 4545 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, + 4546 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E32, + 4547 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, + 4548 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E8, + 4549 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E8_MASK, + 4550 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E16, + 4551 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, + 4552 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E32, + 4553 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, + 4554 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E8, + 4555 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E8_MASK, + 4556 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E16, + 4557 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, + 4558 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E8, + 4559 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E8_MASK, + 4560 => Opcode::PseudoVFWCVTBF16_F_F_V_MF8_E8, + 4561 => Opcode::PseudoVFWCVTBF16_F_F_V_MF8_E8_MASK, + 4562 => Opcode::PseudoVFWCVT_F_F_ALT_V_M1_E16, + 4563 => Opcode::PseudoVFWCVT_F_F_ALT_V_M1_E16_MASK, + 4564 => Opcode::PseudoVFWCVT_F_F_ALT_V_M2_E16, + 4565 => Opcode::PseudoVFWCVT_F_F_ALT_V_M2_E16_MASK, + 4566 => Opcode::PseudoVFWCVT_F_F_ALT_V_M4_E16, + 4567 => Opcode::PseudoVFWCVT_F_F_ALT_V_M4_E16_MASK, + 4568 => Opcode::PseudoVFWCVT_F_F_ALT_V_MF2_E16, + 4569 => Opcode::PseudoVFWCVT_F_F_ALT_V_MF2_E16_MASK, + 4570 => Opcode::PseudoVFWCVT_F_F_ALT_V_MF4_E16, + 4571 => Opcode::PseudoVFWCVT_F_F_ALT_V_MF4_E16_MASK, + 4572 => Opcode::PseudoVFWCVT_F_F_V_M1_E16, + 4573 => Opcode::PseudoVFWCVT_F_F_V_M1_E16_MASK, + 4574 => Opcode::PseudoVFWCVT_F_F_V_M1_E32, + 4575 => Opcode::PseudoVFWCVT_F_F_V_M1_E32_MASK, + 4576 => Opcode::PseudoVFWCVT_F_F_V_M2_E16, + 4577 => Opcode::PseudoVFWCVT_F_F_V_M2_E16_MASK, + 4578 => Opcode::PseudoVFWCVT_F_F_V_M2_E32, + 4579 => Opcode::PseudoVFWCVT_F_F_V_M2_E32_MASK, + 4580 => Opcode::PseudoVFWCVT_F_F_V_M4_E16, + 4581 => Opcode::PseudoVFWCVT_F_F_V_M4_E16_MASK, + 4582 => Opcode::PseudoVFWCVT_F_F_V_M4_E32, + 4583 => Opcode::PseudoVFWCVT_F_F_V_M4_E32_MASK, + 4584 => Opcode::PseudoVFWCVT_F_F_V_MF2_E16, + 4585 => Opcode::PseudoVFWCVT_F_F_V_MF2_E16_MASK, + 4586 => Opcode::PseudoVFWCVT_F_F_V_MF2_E32, + 4587 => Opcode::PseudoVFWCVT_F_F_V_MF2_E32_MASK, + 4588 => Opcode::PseudoVFWCVT_F_F_V_MF4_E16, + 4589 => Opcode::PseudoVFWCVT_F_F_V_MF4_E16_MASK, + 4590 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M1_E8, + 4591 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M1_E8_MASK, + 4592 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M2_E8, + 4593 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M2_E8_MASK, + 4594 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M4_E8, + 4595 => Opcode::PseudoVFWCVT_F_XU_ALT_V_M4_E8_MASK, + 4596 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF2_E8, + 4597 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF2_E8_MASK, + 4598 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF4_E8, + 4599 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF4_E8_MASK, + 4600 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF8_E8, + 4601 => Opcode::PseudoVFWCVT_F_XU_ALT_V_MF8_E8_MASK, + 4602 => Opcode::PseudoVFWCVT_F_XU_V_M1_E16, + 4603 => Opcode::PseudoVFWCVT_F_XU_V_M1_E16_MASK, + 4604 => Opcode::PseudoVFWCVT_F_XU_V_M1_E32, + 4605 => Opcode::PseudoVFWCVT_F_XU_V_M1_E32_MASK, + 4606 => Opcode::PseudoVFWCVT_F_XU_V_M1_E8, + 4607 => Opcode::PseudoVFWCVT_F_XU_V_M1_E8_MASK, + 4608 => Opcode::PseudoVFWCVT_F_XU_V_M2_E16, + 4609 => Opcode::PseudoVFWCVT_F_XU_V_M2_E16_MASK, + 4610 => Opcode::PseudoVFWCVT_F_XU_V_M2_E32, + 4611 => Opcode::PseudoVFWCVT_F_XU_V_M2_E32_MASK, + 4612 => Opcode::PseudoVFWCVT_F_XU_V_M2_E8, + 4613 => Opcode::PseudoVFWCVT_F_XU_V_M2_E8_MASK, + 4614 => Opcode::PseudoVFWCVT_F_XU_V_M4_E16, + 4615 => Opcode::PseudoVFWCVT_F_XU_V_M4_E16_MASK, + 4616 => Opcode::PseudoVFWCVT_F_XU_V_M4_E32, + 4617 => Opcode::PseudoVFWCVT_F_XU_V_M4_E32_MASK, + 4618 => Opcode::PseudoVFWCVT_F_XU_V_M4_E8, + 4619 => Opcode::PseudoVFWCVT_F_XU_V_M4_E8_MASK, + 4620 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E16, + 4621 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E16_MASK, + 4622 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E32, + 4623 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E32_MASK, + 4624 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E8, + 4625 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E8_MASK, + 4626 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E16, + 4627 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E16_MASK, + 4628 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E8, + 4629 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E8_MASK, + 4630 => Opcode::PseudoVFWCVT_F_XU_V_MF8_E8, + 4631 => Opcode::PseudoVFWCVT_F_XU_V_MF8_E8_MASK, + 4632 => Opcode::PseudoVFWCVT_F_X_ALT_V_M1_E8, + 4633 => Opcode::PseudoVFWCVT_F_X_ALT_V_M1_E8_MASK, + 4634 => Opcode::PseudoVFWCVT_F_X_ALT_V_M2_E8, + 4635 => Opcode::PseudoVFWCVT_F_X_ALT_V_M2_E8_MASK, + 4636 => Opcode::PseudoVFWCVT_F_X_ALT_V_M4_E8, + 4637 => Opcode::PseudoVFWCVT_F_X_ALT_V_M4_E8_MASK, + 4638 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF2_E8, + 4639 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF2_E8_MASK, + 4640 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF4_E8, + 4641 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF4_E8_MASK, + 4642 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF8_E8, + 4643 => Opcode::PseudoVFWCVT_F_X_ALT_V_MF8_E8_MASK, + 4644 => Opcode::PseudoVFWCVT_F_X_V_M1_E16, + 4645 => Opcode::PseudoVFWCVT_F_X_V_M1_E16_MASK, + 4646 => Opcode::PseudoVFWCVT_F_X_V_M1_E32, + 4647 => Opcode::PseudoVFWCVT_F_X_V_M1_E32_MASK, + 4648 => Opcode::PseudoVFWCVT_F_X_V_M1_E8, + 4649 => Opcode::PseudoVFWCVT_F_X_V_M1_E8_MASK, + 4650 => Opcode::PseudoVFWCVT_F_X_V_M2_E16, + 4651 => Opcode::PseudoVFWCVT_F_X_V_M2_E16_MASK, + 4652 => Opcode::PseudoVFWCVT_F_X_V_M2_E32, + 4653 => Opcode::PseudoVFWCVT_F_X_V_M2_E32_MASK, + 4654 => Opcode::PseudoVFWCVT_F_X_V_M2_E8, + 4655 => Opcode::PseudoVFWCVT_F_X_V_M2_E8_MASK, + 4656 => Opcode::PseudoVFWCVT_F_X_V_M4_E16, + 4657 => Opcode::PseudoVFWCVT_F_X_V_M4_E16_MASK, + 4658 => Opcode::PseudoVFWCVT_F_X_V_M4_E32, + 4659 => Opcode::PseudoVFWCVT_F_X_V_M4_E32_MASK, + 4660 => Opcode::PseudoVFWCVT_F_X_V_M4_E8, + 4661 => Opcode::PseudoVFWCVT_F_X_V_M4_E8_MASK, + 4662 => Opcode::PseudoVFWCVT_F_X_V_MF2_E16, + 4663 => Opcode::PseudoVFWCVT_F_X_V_MF2_E16_MASK, + 4664 => Opcode::PseudoVFWCVT_F_X_V_MF2_E32, + 4665 => Opcode::PseudoVFWCVT_F_X_V_MF2_E32_MASK, + 4666 => Opcode::PseudoVFWCVT_F_X_V_MF2_E8, + 4667 => Opcode::PseudoVFWCVT_F_X_V_MF2_E8_MASK, + 4668 => Opcode::PseudoVFWCVT_F_X_V_MF4_E16, + 4669 => Opcode::PseudoVFWCVT_F_X_V_MF4_E16_MASK, + 4670 => Opcode::PseudoVFWCVT_F_X_V_MF4_E8, + 4671 => Opcode::PseudoVFWCVT_F_X_V_MF4_E8_MASK, + 4672 => Opcode::PseudoVFWCVT_F_X_V_MF8_E8, + 4673 => Opcode::PseudoVFWCVT_F_X_V_MF8_E8_MASK, + 4674 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M1, + 4675 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, + 4676 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M2, + 4677 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, + 4678 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M4, + 4679 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, + 4680 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF2, + 4681 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, + 4682 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF4, + 4683 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, + 4684 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M1, + 4685 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M1_MASK, + 4686 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M2, + 4687 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M2_MASK, + 4688 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M4, + 4689 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M4_MASK, + 4690 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF2, + 4691 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, + 4692 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF4, + 4693 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, + 4694 => Opcode::PseudoVFWCVT_XU_F_V_M1, + 4695 => Opcode::PseudoVFWCVT_XU_F_V_M1_MASK, + 4696 => Opcode::PseudoVFWCVT_XU_F_V_M2, + 4697 => Opcode::PseudoVFWCVT_XU_F_V_M2_MASK, + 4698 => Opcode::PseudoVFWCVT_XU_F_V_M4, + 4699 => Opcode::PseudoVFWCVT_XU_F_V_M4_MASK, + 4700 => Opcode::PseudoVFWCVT_XU_F_V_MF2, + 4701 => Opcode::PseudoVFWCVT_XU_F_V_MF2_MASK, + 4702 => Opcode::PseudoVFWCVT_XU_F_V_MF4, + 4703 => Opcode::PseudoVFWCVT_XU_F_V_MF4_MASK, + 4704 => Opcode::PseudoVFWCVT_X_F_V_M1, + 4705 => Opcode::PseudoVFWCVT_X_F_V_M1_MASK, + 4706 => Opcode::PseudoVFWCVT_X_F_V_M2, + 4707 => Opcode::PseudoVFWCVT_X_F_V_M2_MASK, + 4708 => Opcode::PseudoVFWCVT_X_F_V_M4, + 4709 => Opcode::PseudoVFWCVT_X_F_V_M4_MASK, + 4710 => Opcode::PseudoVFWCVT_X_F_V_MF2, + 4711 => Opcode::PseudoVFWCVT_X_F_V_MF2_MASK, + 4712 => Opcode::PseudoVFWCVT_X_F_V_MF4, + 4713 => Opcode::PseudoVFWCVT_X_F_V_MF4_MASK, + 4714 => Opcode::PseudoVFWMACCBF16_VFPR16_M1_E16, + 4715 => Opcode::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, + 4716 => Opcode::PseudoVFWMACCBF16_VFPR16_M2_E16, + 4717 => Opcode::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, + 4718 => Opcode::PseudoVFWMACCBF16_VFPR16_M4_E16, + 4719 => Opcode::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, + 4720 => Opcode::PseudoVFWMACCBF16_VFPR16_MF2_E16, + 4721 => Opcode::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, + 4722 => Opcode::PseudoVFWMACCBF16_VFPR16_MF4_E16, + 4723 => Opcode::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, + 4724 => Opcode::PseudoVFWMACCBF16_VV_M1_E16, + 4725 => Opcode::PseudoVFWMACCBF16_VV_M1_E16_MASK, + 4726 => Opcode::PseudoVFWMACCBF16_VV_M1_E32, + 4727 => Opcode::PseudoVFWMACCBF16_VV_M1_E32_MASK, + 4728 => Opcode::PseudoVFWMACCBF16_VV_M2_E16, + 4729 => Opcode::PseudoVFWMACCBF16_VV_M2_E16_MASK, + 4730 => Opcode::PseudoVFWMACCBF16_VV_M2_E32, + 4731 => Opcode::PseudoVFWMACCBF16_VV_M2_E32_MASK, + 4732 => Opcode::PseudoVFWMACCBF16_VV_M4_E16, + 4733 => Opcode::PseudoVFWMACCBF16_VV_M4_E16_MASK, + 4734 => Opcode::PseudoVFWMACCBF16_VV_M4_E32, + 4735 => Opcode::PseudoVFWMACCBF16_VV_M4_E32_MASK, + 4736 => Opcode::PseudoVFWMACCBF16_VV_MF2_E16, + 4737 => Opcode::PseudoVFWMACCBF16_VV_MF2_E16_MASK, + 4738 => Opcode::PseudoVFWMACCBF16_VV_MF2_E32, + 4739 => Opcode::PseudoVFWMACCBF16_VV_MF2_E32_MASK, + 4740 => Opcode::PseudoVFWMACCBF16_VV_MF4_E16, + 4741 => Opcode::PseudoVFWMACCBF16_VV_MF4_E16_MASK, + 4742 => Opcode::PseudoVFWMACC_ALT_VFPR16_M1_E16, + 4743 => Opcode::PseudoVFWMACC_ALT_VFPR16_M1_E16_MASK, + 4744 => Opcode::PseudoVFWMACC_ALT_VFPR16_M2_E16, + 4745 => Opcode::PseudoVFWMACC_ALT_VFPR16_M2_E16_MASK, + 4746 => Opcode::PseudoVFWMACC_ALT_VFPR16_M4_E16, + 4747 => Opcode::PseudoVFWMACC_ALT_VFPR16_M4_E16_MASK, + 4748 => Opcode::PseudoVFWMACC_ALT_VFPR16_MF2_E16, + 4749 => Opcode::PseudoVFWMACC_ALT_VFPR16_MF2_E16_MASK, + 4750 => Opcode::PseudoVFWMACC_ALT_VFPR16_MF4_E16, + 4751 => Opcode::PseudoVFWMACC_ALT_VFPR16_MF4_E16_MASK, + 4752 => Opcode::PseudoVFWMACC_ALT_VV_M1_E16, + 4753 => Opcode::PseudoVFWMACC_ALT_VV_M1_E16_MASK, + 4754 => Opcode::PseudoVFWMACC_ALT_VV_M2_E16, + 4755 => Opcode::PseudoVFWMACC_ALT_VV_M2_E16_MASK, + 4756 => Opcode::PseudoVFWMACC_ALT_VV_M4_E16, + 4757 => Opcode::PseudoVFWMACC_ALT_VV_M4_E16_MASK, + 4758 => Opcode::PseudoVFWMACC_ALT_VV_MF2_E16, + 4759 => Opcode::PseudoVFWMACC_ALT_VV_MF2_E16_MASK, + 4760 => Opcode::PseudoVFWMACC_ALT_VV_MF4_E16, + 4761 => Opcode::PseudoVFWMACC_ALT_VV_MF4_E16_MASK, + 4762 => Opcode::PseudoVFWMACC_VFPR16_M1_E16, + 4763 => Opcode::PseudoVFWMACC_VFPR16_M1_E16_MASK, + 4764 => Opcode::PseudoVFWMACC_VFPR16_M2_E16, + 4765 => Opcode::PseudoVFWMACC_VFPR16_M2_E16_MASK, + 4766 => Opcode::PseudoVFWMACC_VFPR16_M4_E16, + 4767 => Opcode::PseudoVFWMACC_VFPR16_M4_E16_MASK, + 4768 => Opcode::PseudoVFWMACC_VFPR16_MF2_E16, + 4769 => Opcode::PseudoVFWMACC_VFPR16_MF2_E16_MASK, + 4770 => Opcode::PseudoVFWMACC_VFPR16_MF4_E16, + 4771 => Opcode::PseudoVFWMACC_VFPR16_MF4_E16_MASK, + 4772 => Opcode::PseudoVFWMACC_VFPR32_M1_E32, + 4773 => Opcode::PseudoVFWMACC_VFPR32_M1_E32_MASK, + 4774 => Opcode::PseudoVFWMACC_VFPR32_M2_E32, + 4775 => Opcode::PseudoVFWMACC_VFPR32_M2_E32_MASK, + 4776 => Opcode::PseudoVFWMACC_VFPR32_M4_E32, + 4777 => Opcode::PseudoVFWMACC_VFPR32_M4_E32_MASK, + 4778 => Opcode::PseudoVFWMACC_VFPR32_MF2_E32, + 4779 => Opcode::PseudoVFWMACC_VFPR32_MF2_E32_MASK, + 4780 => Opcode::PseudoVFWMACC_VV_M1_E16, + 4781 => Opcode::PseudoVFWMACC_VV_M1_E16_MASK, + 4782 => Opcode::PseudoVFWMACC_VV_M1_E32, + 4783 => Opcode::PseudoVFWMACC_VV_M1_E32_MASK, + 4784 => Opcode::PseudoVFWMACC_VV_M2_E16, + 4785 => Opcode::PseudoVFWMACC_VV_M2_E16_MASK, + 4786 => Opcode::PseudoVFWMACC_VV_M2_E32, + 4787 => Opcode::PseudoVFWMACC_VV_M2_E32_MASK, + 4788 => Opcode::PseudoVFWMACC_VV_M4_E16, + 4789 => Opcode::PseudoVFWMACC_VV_M4_E16_MASK, + 4790 => Opcode::PseudoVFWMACC_VV_M4_E32, + 4791 => Opcode::PseudoVFWMACC_VV_M4_E32_MASK, + 4792 => Opcode::PseudoVFWMACC_VV_MF2_E16, + 4793 => Opcode::PseudoVFWMACC_VV_MF2_E16_MASK, + 4794 => Opcode::PseudoVFWMACC_VV_MF2_E32, + 4795 => Opcode::PseudoVFWMACC_VV_MF2_E32_MASK, + 4796 => Opcode::PseudoVFWMACC_VV_MF4_E16, + 4797 => Opcode::PseudoVFWMACC_VV_MF4_E16_MASK, + 4798 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M1_E16, + 4799 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M1_E16_MASK, + 4800 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M2_E16, + 4801 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M2_E16_MASK, + 4802 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M4_E16, + 4803 => Opcode::PseudoVFWMSAC_ALT_VFPR16_M4_E16_MASK, + 4804 => Opcode::PseudoVFWMSAC_ALT_VFPR16_MF2_E16, + 4805 => Opcode::PseudoVFWMSAC_ALT_VFPR16_MF2_E16_MASK, + 4806 => Opcode::PseudoVFWMSAC_ALT_VFPR16_MF4_E16, + 4807 => Opcode::PseudoVFWMSAC_ALT_VFPR16_MF4_E16_MASK, + 4808 => Opcode::PseudoVFWMSAC_ALT_VV_M1_E16, + 4809 => Opcode::PseudoVFWMSAC_ALT_VV_M1_E16_MASK, + 4810 => Opcode::PseudoVFWMSAC_ALT_VV_M2_E16, + 4811 => Opcode::PseudoVFWMSAC_ALT_VV_M2_E16_MASK, + 4812 => Opcode::PseudoVFWMSAC_ALT_VV_M4_E16, + 4813 => Opcode::PseudoVFWMSAC_ALT_VV_M4_E16_MASK, + 4814 => Opcode::PseudoVFWMSAC_ALT_VV_MF2_E16, + 4815 => Opcode::PseudoVFWMSAC_ALT_VV_MF2_E16_MASK, + 4816 => Opcode::PseudoVFWMSAC_ALT_VV_MF4_E16, + 4817 => Opcode::PseudoVFWMSAC_ALT_VV_MF4_E16_MASK, + 4818 => Opcode::PseudoVFWMSAC_VFPR16_M1_E16, + 4819 => Opcode::PseudoVFWMSAC_VFPR16_M1_E16_MASK, + 4820 => Opcode::PseudoVFWMSAC_VFPR16_M2_E16, + 4821 => Opcode::PseudoVFWMSAC_VFPR16_M2_E16_MASK, + 4822 => Opcode::PseudoVFWMSAC_VFPR16_M4_E16, + 4823 => Opcode::PseudoVFWMSAC_VFPR16_M4_E16_MASK, + 4824 => Opcode::PseudoVFWMSAC_VFPR16_MF2_E16, + 4825 => Opcode::PseudoVFWMSAC_VFPR16_MF2_E16_MASK, + 4826 => Opcode::PseudoVFWMSAC_VFPR16_MF4_E16, + 4827 => Opcode::PseudoVFWMSAC_VFPR16_MF4_E16_MASK, + 4828 => Opcode::PseudoVFWMSAC_VFPR32_M1_E32, + 4829 => Opcode::PseudoVFWMSAC_VFPR32_M1_E32_MASK, + 4830 => Opcode::PseudoVFWMSAC_VFPR32_M2_E32, + 4831 => Opcode::PseudoVFWMSAC_VFPR32_M2_E32_MASK, + 4832 => Opcode::PseudoVFWMSAC_VFPR32_M4_E32, + 4833 => Opcode::PseudoVFWMSAC_VFPR32_M4_E32_MASK, + 4834 => Opcode::PseudoVFWMSAC_VFPR32_MF2_E32, + 4835 => Opcode::PseudoVFWMSAC_VFPR32_MF2_E32_MASK, + 4836 => Opcode::PseudoVFWMSAC_VV_M1_E16, + 4837 => Opcode::PseudoVFWMSAC_VV_M1_E16_MASK, + 4838 => Opcode::PseudoVFWMSAC_VV_M1_E32, + 4839 => Opcode::PseudoVFWMSAC_VV_M1_E32_MASK, + 4840 => Opcode::PseudoVFWMSAC_VV_M2_E16, + 4841 => Opcode::PseudoVFWMSAC_VV_M2_E16_MASK, + 4842 => Opcode::PseudoVFWMSAC_VV_M2_E32, + 4843 => Opcode::PseudoVFWMSAC_VV_M2_E32_MASK, + 4844 => Opcode::PseudoVFWMSAC_VV_M4_E16, + 4845 => Opcode::PseudoVFWMSAC_VV_M4_E16_MASK, + 4846 => Opcode::PseudoVFWMSAC_VV_M4_E32, + 4847 => Opcode::PseudoVFWMSAC_VV_M4_E32_MASK, + 4848 => Opcode::PseudoVFWMSAC_VV_MF2_E16, + 4849 => Opcode::PseudoVFWMSAC_VV_MF2_E16_MASK, + 4850 => Opcode::PseudoVFWMSAC_VV_MF2_E32, + 4851 => Opcode::PseudoVFWMSAC_VV_MF2_E32_MASK, + 4852 => Opcode::PseudoVFWMSAC_VV_MF4_E16, + 4853 => Opcode::PseudoVFWMSAC_VV_MF4_E16_MASK, + 4854 => Opcode::PseudoVFWMUL_ALT_VFPR16_M1_E16, + 4855 => Opcode::PseudoVFWMUL_ALT_VFPR16_M1_E16_MASK, + 4856 => Opcode::PseudoVFWMUL_ALT_VFPR16_M2_E16, + 4857 => Opcode::PseudoVFWMUL_ALT_VFPR16_M2_E16_MASK, + 4858 => Opcode::PseudoVFWMUL_ALT_VFPR16_M4_E16, + 4859 => Opcode::PseudoVFWMUL_ALT_VFPR16_M4_E16_MASK, + 4860 => Opcode::PseudoVFWMUL_ALT_VFPR16_MF2_E16, + 4861 => Opcode::PseudoVFWMUL_ALT_VFPR16_MF2_E16_MASK, + 4862 => Opcode::PseudoVFWMUL_ALT_VFPR16_MF4_E16, + 4863 => Opcode::PseudoVFWMUL_ALT_VFPR16_MF4_E16_MASK, + 4864 => Opcode::PseudoVFWMUL_ALT_VV_M1_E16, + 4865 => Opcode::PseudoVFWMUL_ALT_VV_M1_E16_MASK, + 4866 => Opcode::PseudoVFWMUL_ALT_VV_M2_E16, + 4867 => Opcode::PseudoVFWMUL_ALT_VV_M2_E16_MASK, + 4868 => Opcode::PseudoVFWMUL_ALT_VV_M4_E16, + 4869 => Opcode::PseudoVFWMUL_ALT_VV_M4_E16_MASK, + 4870 => Opcode::PseudoVFWMUL_ALT_VV_MF2_E16, + 4871 => Opcode::PseudoVFWMUL_ALT_VV_MF2_E16_MASK, + 4872 => Opcode::PseudoVFWMUL_ALT_VV_MF4_E16, + 4873 => Opcode::PseudoVFWMUL_ALT_VV_MF4_E16_MASK, + 4874 => Opcode::PseudoVFWMUL_VFPR16_M1_E16, + 4875 => Opcode::PseudoVFWMUL_VFPR16_M1_E16_MASK, + 4876 => Opcode::PseudoVFWMUL_VFPR16_M2_E16, + 4877 => Opcode::PseudoVFWMUL_VFPR16_M2_E16_MASK, + 4878 => Opcode::PseudoVFWMUL_VFPR16_M4_E16, + 4879 => Opcode::PseudoVFWMUL_VFPR16_M4_E16_MASK, + 4880 => Opcode::PseudoVFWMUL_VFPR16_MF2_E16, + 4881 => Opcode::PseudoVFWMUL_VFPR16_MF2_E16_MASK, + 4882 => Opcode::PseudoVFWMUL_VFPR16_MF4_E16, + 4883 => Opcode::PseudoVFWMUL_VFPR16_MF4_E16_MASK, + 4884 => Opcode::PseudoVFWMUL_VFPR32_M1_E32, + 4885 => Opcode::PseudoVFWMUL_VFPR32_M1_E32_MASK, + 4886 => Opcode::PseudoVFWMUL_VFPR32_M2_E32, + 4887 => Opcode::PseudoVFWMUL_VFPR32_M2_E32_MASK, + 4888 => Opcode::PseudoVFWMUL_VFPR32_M4_E32, + 4889 => Opcode::PseudoVFWMUL_VFPR32_M4_E32_MASK, + 4890 => Opcode::PseudoVFWMUL_VFPR32_MF2_E32, + 4891 => Opcode::PseudoVFWMUL_VFPR32_MF2_E32_MASK, + 4892 => Opcode::PseudoVFWMUL_VV_M1_E16, + 4893 => Opcode::PseudoVFWMUL_VV_M1_E16_MASK, + 4894 => Opcode::PseudoVFWMUL_VV_M1_E32, + 4895 => Opcode::PseudoVFWMUL_VV_M1_E32_MASK, + 4896 => Opcode::PseudoVFWMUL_VV_M2_E16, + 4897 => Opcode::PseudoVFWMUL_VV_M2_E16_MASK, + 4898 => Opcode::PseudoVFWMUL_VV_M2_E32, + 4899 => Opcode::PseudoVFWMUL_VV_M2_E32_MASK, + 4900 => Opcode::PseudoVFWMUL_VV_M4_E16, + 4901 => Opcode::PseudoVFWMUL_VV_M4_E16_MASK, + 4902 => Opcode::PseudoVFWMUL_VV_M4_E32, + 4903 => Opcode::PseudoVFWMUL_VV_M4_E32_MASK, + 4904 => Opcode::PseudoVFWMUL_VV_MF2_E16, + 4905 => Opcode::PseudoVFWMUL_VV_MF2_E16_MASK, + 4906 => Opcode::PseudoVFWMUL_VV_MF2_E32, + 4907 => Opcode::PseudoVFWMUL_VV_MF2_E32_MASK, + 4908 => Opcode::PseudoVFWMUL_VV_MF4_E16, + 4909 => Opcode::PseudoVFWMUL_VV_MF4_E16_MASK, + 4910 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M1_E16, + 4911 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M1_E16_MASK, + 4912 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M2_E16, + 4913 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M2_E16_MASK, + 4914 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M4_E16, + 4915 => Opcode::PseudoVFWNMACC_ALT_VFPR16_M4_E16_MASK, + 4916 => Opcode::PseudoVFWNMACC_ALT_VFPR16_MF2_E16, + 4917 => Opcode::PseudoVFWNMACC_ALT_VFPR16_MF2_E16_MASK, + 4918 => Opcode::PseudoVFWNMACC_ALT_VFPR16_MF4_E16, + 4919 => Opcode::PseudoVFWNMACC_ALT_VFPR16_MF4_E16_MASK, + 4920 => Opcode::PseudoVFWNMACC_ALT_VV_M1_E16, + 4921 => Opcode::PseudoVFWNMACC_ALT_VV_M1_E16_MASK, + 4922 => Opcode::PseudoVFWNMACC_ALT_VV_M2_E16, + 4923 => Opcode::PseudoVFWNMACC_ALT_VV_M2_E16_MASK, + 4924 => Opcode::PseudoVFWNMACC_ALT_VV_M4_E16, + 4925 => Opcode::PseudoVFWNMACC_ALT_VV_M4_E16_MASK, + 4926 => Opcode::PseudoVFWNMACC_ALT_VV_MF2_E16, + 4927 => Opcode::PseudoVFWNMACC_ALT_VV_MF2_E16_MASK, + 4928 => Opcode::PseudoVFWNMACC_ALT_VV_MF4_E16, + 4929 => Opcode::PseudoVFWNMACC_ALT_VV_MF4_E16_MASK, + 4930 => Opcode::PseudoVFWNMACC_VFPR16_M1_E16, + 4931 => Opcode::PseudoVFWNMACC_VFPR16_M1_E16_MASK, + 4932 => Opcode::PseudoVFWNMACC_VFPR16_M2_E16, + 4933 => Opcode::PseudoVFWNMACC_VFPR16_M2_E16_MASK, + 4934 => Opcode::PseudoVFWNMACC_VFPR16_M4_E16, + 4935 => Opcode::PseudoVFWNMACC_VFPR16_M4_E16_MASK, + 4936 => Opcode::PseudoVFWNMACC_VFPR16_MF2_E16, + 4937 => Opcode::PseudoVFWNMACC_VFPR16_MF2_E16_MASK, + 4938 => Opcode::PseudoVFWNMACC_VFPR16_MF4_E16, + 4939 => Opcode::PseudoVFWNMACC_VFPR16_MF4_E16_MASK, + 4940 => Opcode::PseudoVFWNMACC_VFPR32_M1_E32, + 4941 => Opcode::PseudoVFWNMACC_VFPR32_M1_E32_MASK, + 4942 => Opcode::PseudoVFWNMACC_VFPR32_M2_E32, + 4943 => Opcode::PseudoVFWNMACC_VFPR32_M2_E32_MASK, + 4944 => Opcode::PseudoVFWNMACC_VFPR32_M4_E32, + 4945 => Opcode::PseudoVFWNMACC_VFPR32_M4_E32_MASK, + 4946 => Opcode::PseudoVFWNMACC_VFPR32_MF2_E32, + 4947 => Opcode::PseudoVFWNMACC_VFPR32_MF2_E32_MASK, + 4948 => Opcode::PseudoVFWNMACC_VV_M1_E16, + 4949 => Opcode::PseudoVFWNMACC_VV_M1_E16_MASK, + 4950 => Opcode::PseudoVFWNMACC_VV_M1_E32, + 4951 => Opcode::PseudoVFWNMACC_VV_M1_E32_MASK, + 4952 => Opcode::PseudoVFWNMACC_VV_M2_E16, + 4953 => Opcode::PseudoVFWNMACC_VV_M2_E16_MASK, + 4954 => Opcode::PseudoVFWNMACC_VV_M2_E32, + 4955 => Opcode::PseudoVFWNMACC_VV_M2_E32_MASK, + 4956 => Opcode::PseudoVFWNMACC_VV_M4_E16, + 4957 => Opcode::PseudoVFWNMACC_VV_M4_E16_MASK, + 4958 => Opcode::PseudoVFWNMACC_VV_M4_E32, + 4959 => Opcode::PseudoVFWNMACC_VV_M4_E32_MASK, + 4960 => Opcode::PseudoVFWNMACC_VV_MF2_E16, + 4961 => Opcode::PseudoVFWNMACC_VV_MF2_E16_MASK, + 4962 => Opcode::PseudoVFWNMACC_VV_MF2_E32, + 4963 => Opcode::PseudoVFWNMACC_VV_MF2_E32_MASK, + 4964 => Opcode::PseudoVFWNMACC_VV_MF4_E16, + 4965 => Opcode::PseudoVFWNMACC_VV_MF4_E16_MASK, + 4966 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M1_E16, + 4967 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M1_E16_MASK, + 4968 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M2_E16, + 4969 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M2_E16_MASK, + 4970 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M4_E16, + 4971 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_M4_E16_MASK, + 4972 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_MF2_E16, + 4973 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_MF2_E16_MASK, + 4974 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_MF4_E16, + 4975 => Opcode::PseudoVFWNMSAC_ALT_VFPR16_MF4_E16_MASK, + 4976 => Opcode::PseudoVFWNMSAC_ALT_VV_M1_E16, + 4977 => Opcode::PseudoVFWNMSAC_ALT_VV_M1_E16_MASK, + 4978 => Opcode::PseudoVFWNMSAC_ALT_VV_M2_E16, + 4979 => Opcode::PseudoVFWNMSAC_ALT_VV_M2_E16_MASK, + 4980 => Opcode::PseudoVFWNMSAC_ALT_VV_M4_E16, + 4981 => Opcode::PseudoVFWNMSAC_ALT_VV_M4_E16_MASK, + 4982 => Opcode::PseudoVFWNMSAC_ALT_VV_MF2_E16, + 4983 => Opcode::PseudoVFWNMSAC_ALT_VV_MF2_E16_MASK, + 4984 => Opcode::PseudoVFWNMSAC_ALT_VV_MF4_E16, + 4985 => Opcode::PseudoVFWNMSAC_ALT_VV_MF4_E16_MASK, + 4986 => Opcode::PseudoVFWNMSAC_VFPR16_M1_E16, + 4987 => Opcode::PseudoVFWNMSAC_VFPR16_M1_E16_MASK, + 4988 => Opcode::PseudoVFWNMSAC_VFPR16_M2_E16, + 4989 => Opcode::PseudoVFWNMSAC_VFPR16_M2_E16_MASK, + 4990 => Opcode::PseudoVFWNMSAC_VFPR16_M4_E16, + 4991 => Opcode::PseudoVFWNMSAC_VFPR16_M4_E16_MASK, + 4992 => Opcode::PseudoVFWNMSAC_VFPR16_MF2_E16, + 4993 => Opcode::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, + 4994 => Opcode::PseudoVFWNMSAC_VFPR16_MF4_E16, + 4995 => Opcode::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, + 4996 => Opcode::PseudoVFWNMSAC_VFPR32_M1_E32, + 4997 => Opcode::PseudoVFWNMSAC_VFPR32_M1_E32_MASK, + 4998 => Opcode::PseudoVFWNMSAC_VFPR32_M2_E32, + 4999 => Opcode::PseudoVFWNMSAC_VFPR32_M2_E32_MASK, + 5000 => Opcode::PseudoVFWNMSAC_VFPR32_M4_E32, + 5001 => Opcode::PseudoVFWNMSAC_VFPR32_M4_E32_MASK, + 5002 => Opcode::PseudoVFWNMSAC_VFPR32_MF2_E32, + 5003 => Opcode::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, + 5004 => Opcode::PseudoVFWNMSAC_VV_M1_E16, + 5005 => Opcode::PseudoVFWNMSAC_VV_M1_E16_MASK, + 5006 => Opcode::PseudoVFWNMSAC_VV_M1_E32, + 5007 => Opcode::PseudoVFWNMSAC_VV_M1_E32_MASK, + 5008 => Opcode::PseudoVFWNMSAC_VV_M2_E16, + 5009 => Opcode::PseudoVFWNMSAC_VV_M2_E16_MASK, + 5010 => Opcode::PseudoVFWNMSAC_VV_M2_E32, + 5011 => Opcode::PseudoVFWNMSAC_VV_M2_E32_MASK, + 5012 => Opcode::PseudoVFWNMSAC_VV_M4_E16, + 5013 => Opcode::PseudoVFWNMSAC_VV_M4_E16_MASK, + 5014 => Opcode::PseudoVFWNMSAC_VV_M4_E32, + 5015 => Opcode::PseudoVFWNMSAC_VV_M4_E32_MASK, + 5016 => Opcode::PseudoVFWNMSAC_VV_MF2_E16, + 5017 => Opcode::PseudoVFWNMSAC_VV_MF2_E16_MASK, + 5018 => Opcode::PseudoVFWNMSAC_VV_MF2_E32, + 5019 => Opcode::PseudoVFWNMSAC_VV_MF2_E32_MASK, + 5020 => Opcode::PseudoVFWNMSAC_VV_MF4_E16, + 5021 => Opcode::PseudoVFWNMSAC_VV_MF4_E16_MASK, + 5022 => Opcode::PseudoVFWREDOSUM_VS_M1_E16, + 5023 => Opcode::PseudoVFWREDOSUM_VS_M1_E16_MASK, + 5024 => Opcode::PseudoVFWREDOSUM_VS_M1_E32, + 5025 => Opcode::PseudoVFWREDOSUM_VS_M1_E32_MASK, + 5026 => Opcode::PseudoVFWREDOSUM_VS_M2_E16, + 5027 => Opcode::PseudoVFWREDOSUM_VS_M2_E16_MASK, + 5028 => Opcode::PseudoVFWREDOSUM_VS_M2_E32, + 5029 => Opcode::PseudoVFWREDOSUM_VS_M2_E32_MASK, + 5030 => Opcode::PseudoVFWREDOSUM_VS_M4_E16, + 5031 => Opcode::PseudoVFWREDOSUM_VS_M4_E16_MASK, + 5032 => Opcode::PseudoVFWREDOSUM_VS_M4_E32, + 5033 => Opcode::PseudoVFWREDOSUM_VS_M4_E32_MASK, + 5034 => Opcode::PseudoVFWREDOSUM_VS_M8_E16, + 5035 => Opcode::PseudoVFWREDOSUM_VS_M8_E16_MASK, + 5036 => Opcode::PseudoVFWREDOSUM_VS_M8_E32, + 5037 => Opcode::PseudoVFWREDOSUM_VS_M8_E32_MASK, + 5038 => Opcode::PseudoVFWREDOSUM_VS_MF2_E16, + 5039 => Opcode::PseudoVFWREDOSUM_VS_MF2_E16_MASK, + 5040 => Opcode::PseudoVFWREDOSUM_VS_MF2_E32, + 5041 => Opcode::PseudoVFWREDOSUM_VS_MF2_E32_MASK, + 5042 => Opcode::PseudoVFWREDOSUM_VS_MF4_E16, + 5043 => Opcode::PseudoVFWREDOSUM_VS_MF4_E16_MASK, + 5044 => Opcode::PseudoVFWREDUSUM_VS_M1_E16, + 5045 => Opcode::PseudoVFWREDUSUM_VS_M1_E16_MASK, + 5046 => Opcode::PseudoVFWREDUSUM_VS_M1_E32, + 5047 => Opcode::PseudoVFWREDUSUM_VS_M1_E32_MASK, + 5048 => Opcode::PseudoVFWREDUSUM_VS_M2_E16, + 5049 => Opcode::PseudoVFWREDUSUM_VS_M2_E16_MASK, + 5050 => Opcode::PseudoVFWREDUSUM_VS_M2_E32, + 5051 => Opcode::PseudoVFWREDUSUM_VS_M2_E32_MASK, + 5052 => Opcode::PseudoVFWREDUSUM_VS_M4_E16, + 5053 => Opcode::PseudoVFWREDUSUM_VS_M4_E16_MASK, + 5054 => Opcode::PseudoVFWREDUSUM_VS_M4_E32, + 5055 => Opcode::PseudoVFWREDUSUM_VS_M4_E32_MASK, + 5056 => Opcode::PseudoVFWREDUSUM_VS_M8_E16, + 5057 => Opcode::PseudoVFWREDUSUM_VS_M8_E16_MASK, + 5058 => Opcode::PseudoVFWREDUSUM_VS_M8_E32, + 5059 => Opcode::PseudoVFWREDUSUM_VS_M8_E32_MASK, + 5060 => Opcode::PseudoVFWREDUSUM_VS_MF2_E16, + 5061 => Opcode::PseudoVFWREDUSUM_VS_MF2_E16_MASK, + 5062 => Opcode::PseudoVFWREDUSUM_VS_MF2_E32, + 5063 => Opcode::PseudoVFWREDUSUM_VS_MF2_E32_MASK, + 5064 => Opcode::PseudoVFWREDUSUM_VS_MF4_E16, + 5065 => Opcode::PseudoVFWREDUSUM_VS_MF4_E16_MASK, + 5066 => Opcode::PseudoVFWSUB_ALT_VFPR16_M1_E16, + 5067 => Opcode::PseudoVFWSUB_ALT_VFPR16_M1_E16_MASK, + 5068 => Opcode::PseudoVFWSUB_ALT_VFPR16_M2_E16, + 5069 => Opcode::PseudoVFWSUB_ALT_VFPR16_M2_E16_MASK, + 5070 => Opcode::PseudoVFWSUB_ALT_VFPR16_M4_E16, + 5071 => Opcode::PseudoVFWSUB_ALT_VFPR16_M4_E16_MASK, + 5072 => Opcode::PseudoVFWSUB_ALT_VFPR16_MF2_E16, + 5073 => Opcode::PseudoVFWSUB_ALT_VFPR16_MF2_E16_MASK, + 5074 => Opcode::PseudoVFWSUB_ALT_VFPR16_MF4_E16, + 5075 => Opcode::PseudoVFWSUB_ALT_VFPR16_MF4_E16_MASK, + 5076 => Opcode::PseudoVFWSUB_ALT_VV_M1_E16, + 5077 => Opcode::PseudoVFWSUB_ALT_VV_M1_E16_MASK, + 5078 => Opcode::PseudoVFWSUB_ALT_VV_M2_E16, + 5079 => Opcode::PseudoVFWSUB_ALT_VV_M2_E16_MASK, + 5080 => Opcode::PseudoVFWSUB_ALT_VV_M4_E16, + 5081 => Opcode::PseudoVFWSUB_ALT_VV_M4_E16_MASK, + 5082 => Opcode::PseudoVFWSUB_ALT_VV_MF2_E16, + 5083 => Opcode::PseudoVFWSUB_ALT_VV_MF2_E16_MASK, + 5084 => Opcode::PseudoVFWSUB_ALT_VV_MF4_E16, + 5085 => Opcode::PseudoVFWSUB_ALT_VV_MF4_E16_MASK, + 5086 => Opcode::PseudoVFWSUB_ALT_WFPR16_M1_E16, + 5087 => Opcode::PseudoVFWSUB_ALT_WFPR16_M1_E16_MASK, + 5088 => Opcode::PseudoVFWSUB_ALT_WFPR16_M2_E16, + 5089 => Opcode::PseudoVFWSUB_ALT_WFPR16_M2_E16_MASK, + 5090 => Opcode::PseudoVFWSUB_ALT_WFPR16_M4_E16, + 5091 => Opcode::PseudoVFWSUB_ALT_WFPR16_M4_E16_MASK, + 5092 => Opcode::PseudoVFWSUB_ALT_WFPR16_MF2_E16, + 5093 => Opcode::PseudoVFWSUB_ALT_WFPR16_MF2_E16_MASK, + 5094 => Opcode::PseudoVFWSUB_ALT_WFPR16_MF4_E16, + 5095 => Opcode::PseudoVFWSUB_ALT_WFPR16_MF4_E16_MASK, + 5096 => Opcode::PseudoVFWSUB_ALT_WV_M1_E16, + 5097 => Opcode::PseudoVFWSUB_ALT_WV_M1_E16_MASK, + 5098 => Opcode::PseudoVFWSUB_ALT_WV_M1_E16_MASK_TIED, + 5099 => Opcode::PseudoVFWSUB_ALT_WV_M1_E16_TIED, + 5100 => Opcode::PseudoVFWSUB_ALT_WV_M2_E16, + 5101 => Opcode::PseudoVFWSUB_ALT_WV_M2_E16_MASK, + 5102 => Opcode::PseudoVFWSUB_ALT_WV_M2_E16_MASK_TIED, + 5103 => Opcode::PseudoVFWSUB_ALT_WV_M2_E16_TIED, + 5104 => Opcode::PseudoVFWSUB_ALT_WV_M4_E16, + 5105 => Opcode::PseudoVFWSUB_ALT_WV_M4_E16_MASK, + 5106 => Opcode::PseudoVFWSUB_ALT_WV_M4_E16_MASK_TIED, + 5107 => Opcode::PseudoVFWSUB_ALT_WV_M4_E16_TIED, + 5108 => Opcode::PseudoVFWSUB_ALT_WV_MF2_E16, + 5109 => Opcode::PseudoVFWSUB_ALT_WV_MF2_E16_MASK, + 5110 => Opcode::PseudoVFWSUB_ALT_WV_MF2_E16_MASK_TIED, + 5111 => Opcode::PseudoVFWSUB_ALT_WV_MF2_E16_TIED, + 5112 => Opcode::PseudoVFWSUB_ALT_WV_MF4_E16, + 5113 => Opcode::PseudoVFWSUB_ALT_WV_MF4_E16_MASK, + 5114 => Opcode::PseudoVFWSUB_ALT_WV_MF4_E16_MASK_TIED, + 5115 => Opcode::PseudoVFWSUB_ALT_WV_MF4_E16_TIED, + 5116 => Opcode::PseudoVFWSUB_VFPR16_M1_E16, + 5117 => Opcode::PseudoVFWSUB_VFPR16_M1_E16_MASK, + 5118 => Opcode::PseudoVFWSUB_VFPR16_M2_E16, + 5119 => Opcode::PseudoVFWSUB_VFPR16_M2_E16_MASK, + 5120 => Opcode::PseudoVFWSUB_VFPR16_M4_E16, + 5121 => Opcode::PseudoVFWSUB_VFPR16_M4_E16_MASK, + 5122 => Opcode::PseudoVFWSUB_VFPR16_MF2_E16, + 5123 => Opcode::PseudoVFWSUB_VFPR16_MF2_E16_MASK, + 5124 => Opcode::PseudoVFWSUB_VFPR16_MF4_E16, + 5125 => Opcode::PseudoVFWSUB_VFPR16_MF4_E16_MASK, + 5126 => Opcode::PseudoVFWSUB_VFPR32_M1_E32, + 5127 => Opcode::PseudoVFWSUB_VFPR32_M1_E32_MASK, + 5128 => Opcode::PseudoVFWSUB_VFPR32_M2_E32, + 5129 => Opcode::PseudoVFWSUB_VFPR32_M2_E32_MASK, + 5130 => Opcode::PseudoVFWSUB_VFPR32_M4_E32, + 5131 => Opcode::PseudoVFWSUB_VFPR32_M4_E32_MASK, + 5132 => Opcode::PseudoVFWSUB_VFPR32_MF2_E32, + 5133 => Opcode::PseudoVFWSUB_VFPR32_MF2_E32_MASK, + 5134 => Opcode::PseudoVFWSUB_VV_M1_E16, + 5135 => Opcode::PseudoVFWSUB_VV_M1_E16_MASK, + 5136 => Opcode::PseudoVFWSUB_VV_M1_E32, + 5137 => Opcode::PseudoVFWSUB_VV_M1_E32_MASK, + 5138 => Opcode::PseudoVFWSUB_VV_M2_E16, + 5139 => Opcode::PseudoVFWSUB_VV_M2_E16_MASK, + 5140 => Opcode::PseudoVFWSUB_VV_M2_E32, + 5141 => Opcode::PseudoVFWSUB_VV_M2_E32_MASK, + 5142 => Opcode::PseudoVFWSUB_VV_M4_E16, + 5143 => Opcode::PseudoVFWSUB_VV_M4_E16_MASK, + 5144 => Opcode::PseudoVFWSUB_VV_M4_E32, + 5145 => Opcode::PseudoVFWSUB_VV_M4_E32_MASK, + 5146 => Opcode::PseudoVFWSUB_VV_MF2_E16, + 5147 => Opcode::PseudoVFWSUB_VV_MF2_E16_MASK, + 5148 => Opcode::PseudoVFWSUB_VV_MF2_E32, + 5149 => Opcode::PseudoVFWSUB_VV_MF2_E32_MASK, + 5150 => Opcode::PseudoVFWSUB_VV_MF4_E16, + 5151 => Opcode::PseudoVFWSUB_VV_MF4_E16_MASK, + 5152 => Opcode::PseudoVFWSUB_WFPR16_M1_E16, + 5153 => Opcode::PseudoVFWSUB_WFPR16_M1_E16_MASK, + 5154 => Opcode::PseudoVFWSUB_WFPR16_M2_E16, + 5155 => Opcode::PseudoVFWSUB_WFPR16_M2_E16_MASK, + 5156 => Opcode::PseudoVFWSUB_WFPR16_M4_E16, + 5157 => Opcode::PseudoVFWSUB_WFPR16_M4_E16_MASK, + 5158 => Opcode::PseudoVFWSUB_WFPR16_MF2_E16, + 5159 => Opcode::PseudoVFWSUB_WFPR16_MF2_E16_MASK, + 5160 => Opcode::PseudoVFWSUB_WFPR16_MF4_E16, + 5161 => Opcode::PseudoVFWSUB_WFPR16_MF4_E16_MASK, + 5162 => Opcode::PseudoVFWSUB_WFPR32_M1_E32, + 5163 => Opcode::PseudoVFWSUB_WFPR32_M1_E32_MASK, + 5164 => Opcode::PseudoVFWSUB_WFPR32_M2_E32, + 5165 => Opcode::PseudoVFWSUB_WFPR32_M2_E32_MASK, + 5166 => Opcode::PseudoVFWSUB_WFPR32_M4_E32, + 5167 => Opcode::PseudoVFWSUB_WFPR32_M4_E32_MASK, + 5168 => Opcode::PseudoVFWSUB_WFPR32_MF2_E32, + 5169 => Opcode::PseudoVFWSUB_WFPR32_MF2_E32_MASK, + 5170 => Opcode::PseudoVFWSUB_WV_M1_E16, + 5171 => Opcode::PseudoVFWSUB_WV_M1_E16_MASK, + 5172 => Opcode::PseudoVFWSUB_WV_M1_E16_MASK_TIED, + 5173 => Opcode::PseudoVFWSUB_WV_M1_E16_TIED, + 5174 => Opcode::PseudoVFWSUB_WV_M1_E32, + 5175 => Opcode::PseudoVFWSUB_WV_M1_E32_MASK, + 5176 => Opcode::PseudoVFWSUB_WV_M1_E32_MASK_TIED, + 5177 => Opcode::PseudoVFWSUB_WV_M1_E32_TIED, + 5178 => Opcode::PseudoVFWSUB_WV_M2_E16, + 5179 => Opcode::PseudoVFWSUB_WV_M2_E16_MASK, + 5180 => Opcode::PseudoVFWSUB_WV_M2_E16_MASK_TIED, + 5181 => Opcode::PseudoVFWSUB_WV_M2_E16_TIED, + 5182 => Opcode::PseudoVFWSUB_WV_M2_E32, + 5183 => Opcode::PseudoVFWSUB_WV_M2_E32_MASK, + 5184 => Opcode::PseudoVFWSUB_WV_M2_E32_MASK_TIED, + 5185 => Opcode::PseudoVFWSUB_WV_M2_E32_TIED, + 5186 => Opcode::PseudoVFWSUB_WV_M4_E16, + 5187 => Opcode::PseudoVFWSUB_WV_M4_E16_MASK, + 5188 => Opcode::PseudoVFWSUB_WV_M4_E16_MASK_TIED, + 5189 => Opcode::PseudoVFWSUB_WV_M4_E16_TIED, + 5190 => Opcode::PseudoVFWSUB_WV_M4_E32, + 5191 => Opcode::PseudoVFWSUB_WV_M4_E32_MASK, + 5192 => Opcode::PseudoVFWSUB_WV_M4_E32_MASK_TIED, + 5193 => Opcode::PseudoVFWSUB_WV_M4_E32_TIED, + 5194 => Opcode::PseudoVFWSUB_WV_MF2_E16, + 5195 => Opcode::PseudoVFWSUB_WV_MF2_E16_MASK, + 5196 => Opcode::PseudoVFWSUB_WV_MF2_E16_MASK_TIED, + 5197 => Opcode::PseudoVFWSUB_WV_MF2_E16_TIED, + 5198 => Opcode::PseudoVFWSUB_WV_MF2_E32, + 5199 => Opcode::PseudoVFWSUB_WV_MF2_E32_MASK, + 5200 => Opcode::PseudoVFWSUB_WV_MF2_E32_MASK_TIED, + 5201 => Opcode::PseudoVFWSUB_WV_MF2_E32_TIED, + 5202 => Opcode::PseudoVFWSUB_WV_MF4_E16, + 5203 => Opcode::PseudoVFWSUB_WV_MF4_E16_MASK, + 5204 => Opcode::PseudoVFWSUB_WV_MF4_E16_MASK_TIED, + 5205 => Opcode::PseudoVFWSUB_WV_MF4_E16_TIED, + 5206 => Opcode::PseudoVGHSH_VV_M1, + 5207 => Opcode::PseudoVGHSH_VV_M2, + 5208 => Opcode::PseudoVGHSH_VV_M4, + 5209 => Opcode::PseudoVGHSH_VV_M8, + 5210 => Opcode::PseudoVGHSH_VV_MF2, + 5211 => Opcode::PseudoVGMUL_VV_M1, + 5212 => Opcode::PseudoVGMUL_VV_M2, + 5213 => Opcode::PseudoVGMUL_VV_M4, + 5214 => Opcode::PseudoVGMUL_VV_M8, + 5215 => Opcode::PseudoVGMUL_VV_MF2, + 5216 => Opcode::PseudoVID_V_M1, + 5217 => Opcode::PseudoVID_V_M1_MASK, + 5218 => Opcode::PseudoVID_V_M2, + 5219 => Opcode::PseudoVID_V_M2_MASK, + 5220 => Opcode::PseudoVID_V_M4, + 5221 => Opcode::PseudoVID_V_M4_MASK, + 5222 => Opcode::PseudoVID_V_M8, + 5223 => Opcode::PseudoVID_V_M8_MASK, + 5224 => Opcode::PseudoVID_V_MF2, + 5225 => Opcode::PseudoVID_V_MF2_MASK, + 5226 => Opcode::PseudoVID_V_MF4, + 5227 => Opcode::PseudoVID_V_MF4_MASK, + 5228 => Opcode::PseudoVID_V_MF8, + 5229 => Opcode::PseudoVID_V_MF8_MASK, + 5230 => Opcode::PseudoVIOTA_M_M1, + 5231 => Opcode::PseudoVIOTA_M_M1_MASK, + 5232 => Opcode::PseudoVIOTA_M_M2, + 5233 => Opcode::PseudoVIOTA_M_M2_MASK, + 5234 => Opcode::PseudoVIOTA_M_M4, + 5235 => Opcode::PseudoVIOTA_M_M4_MASK, + 5236 => Opcode::PseudoVIOTA_M_M8, + 5237 => Opcode::PseudoVIOTA_M_M8_MASK, + 5238 => Opcode::PseudoVIOTA_M_MF2, + 5239 => Opcode::PseudoVIOTA_M_MF2_MASK, + 5240 => Opcode::PseudoVIOTA_M_MF4, + 5241 => Opcode::PseudoVIOTA_M_MF4_MASK, + 5242 => Opcode::PseudoVIOTA_M_MF8, + 5243 => Opcode::PseudoVIOTA_M_MF8_MASK, + 5244 => Opcode::PseudoVLE16FF_V_M1, + 5245 => Opcode::PseudoVLE16FF_V_M1_MASK, + 5246 => Opcode::PseudoVLE16FF_V_M2, + 5247 => Opcode::PseudoVLE16FF_V_M2_MASK, + 5248 => Opcode::PseudoVLE16FF_V_M4, + 5249 => Opcode::PseudoVLE16FF_V_M4_MASK, + 5250 => Opcode::PseudoVLE16FF_V_M8, + 5251 => Opcode::PseudoVLE16FF_V_M8_MASK, + 5252 => Opcode::PseudoVLE16FF_V_MF2, + 5253 => Opcode::PseudoVLE16FF_V_MF2_MASK, + 5254 => Opcode::PseudoVLE16FF_V_MF4, + 5255 => Opcode::PseudoVLE16FF_V_MF4_MASK, + 5256 => Opcode::PseudoVLE16_V_M1, + 5257 => Opcode::PseudoVLE16_V_M1_MASK, + 5258 => Opcode::PseudoVLE16_V_M2, + 5259 => Opcode::PseudoVLE16_V_M2_MASK, + 5260 => Opcode::PseudoVLE16_V_M4, + 5261 => Opcode::PseudoVLE16_V_M4_MASK, + 5262 => Opcode::PseudoVLE16_V_M8, + 5263 => Opcode::PseudoVLE16_V_M8_MASK, + 5264 => Opcode::PseudoVLE16_V_MF2, + 5265 => Opcode::PseudoVLE16_V_MF2_MASK, + 5266 => Opcode::PseudoVLE16_V_MF4, + 5267 => Opcode::PseudoVLE16_V_MF4_MASK, + 5268 => Opcode::PseudoVLE32FF_V_M1, + 5269 => Opcode::PseudoVLE32FF_V_M1_MASK, + 5270 => Opcode::PseudoVLE32FF_V_M2, + 5271 => Opcode::PseudoVLE32FF_V_M2_MASK, + 5272 => Opcode::PseudoVLE32FF_V_M4, + 5273 => Opcode::PseudoVLE32FF_V_M4_MASK, + 5274 => Opcode::PseudoVLE32FF_V_M8, + 5275 => Opcode::PseudoVLE32FF_V_M8_MASK, + 5276 => Opcode::PseudoVLE32FF_V_MF2, + 5277 => Opcode::PseudoVLE32FF_V_MF2_MASK, + 5278 => Opcode::PseudoVLE32_V_M1, + 5279 => Opcode::PseudoVLE32_V_M1_MASK, + 5280 => Opcode::PseudoVLE32_V_M2, + 5281 => Opcode::PseudoVLE32_V_M2_MASK, + 5282 => Opcode::PseudoVLE32_V_M4, + 5283 => Opcode::PseudoVLE32_V_M4_MASK, + 5284 => Opcode::PseudoVLE32_V_M8, + 5285 => Opcode::PseudoVLE32_V_M8_MASK, + 5286 => Opcode::PseudoVLE32_V_MF2, + 5287 => Opcode::PseudoVLE32_V_MF2_MASK, + 5288 => Opcode::PseudoVLE64FF_V_M1, + 5289 => Opcode::PseudoVLE64FF_V_M1_MASK, + 5290 => Opcode::PseudoVLE64FF_V_M2, + 5291 => Opcode::PseudoVLE64FF_V_M2_MASK, + 5292 => Opcode::PseudoVLE64FF_V_M4, + 5293 => Opcode::PseudoVLE64FF_V_M4_MASK, + 5294 => Opcode::PseudoVLE64FF_V_M8, + 5295 => Opcode::PseudoVLE64FF_V_M8_MASK, + 5296 => Opcode::PseudoVLE64_V_M1, + 5297 => Opcode::PseudoVLE64_V_M1_MASK, + 5298 => Opcode::PseudoVLE64_V_M2, + 5299 => Opcode::PseudoVLE64_V_M2_MASK, + 5300 => Opcode::PseudoVLE64_V_M4, + 5301 => Opcode::PseudoVLE64_V_M4_MASK, + 5302 => Opcode::PseudoVLE64_V_M8, + 5303 => Opcode::PseudoVLE64_V_M8_MASK, + 5304 => Opcode::PseudoVLE8FF_V_M1, + 5305 => Opcode::PseudoVLE8FF_V_M1_MASK, + 5306 => Opcode::PseudoVLE8FF_V_M2, + 5307 => Opcode::PseudoVLE8FF_V_M2_MASK, + 5308 => Opcode::PseudoVLE8FF_V_M4, + 5309 => Opcode::PseudoVLE8FF_V_M4_MASK, + 5310 => Opcode::PseudoVLE8FF_V_M8, + 5311 => Opcode::PseudoVLE8FF_V_M8_MASK, + 5312 => Opcode::PseudoVLE8FF_V_MF2, + 5313 => Opcode::PseudoVLE8FF_V_MF2_MASK, + 5314 => Opcode::PseudoVLE8FF_V_MF4, + 5315 => Opcode::PseudoVLE8FF_V_MF4_MASK, + 5316 => Opcode::PseudoVLE8FF_V_MF8, + 5317 => Opcode::PseudoVLE8FF_V_MF8_MASK, + 5318 => Opcode::PseudoVLE8_V_M1, + 5319 => Opcode::PseudoVLE8_V_M1_MASK, + 5320 => Opcode::PseudoVLE8_V_M2, + 5321 => Opcode::PseudoVLE8_V_M2_MASK, + 5322 => Opcode::PseudoVLE8_V_M4, + 5323 => Opcode::PseudoVLE8_V_M4_MASK, + 5324 => Opcode::PseudoVLE8_V_M8, + 5325 => Opcode::PseudoVLE8_V_M8_MASK, + 5326 => Opcode::PseudoVLE8_V_MF2, + 5327 => Opcode::PseudoVLE8_V_MF2_MASK, + 5328 => Opcode::PseudoVLE8_V_MF4, + 5329 => Opcode::PseudoVLE8_V_MF4_MASK, + 5330 => Opcode::PseudoVLE8_V_MF8, + 5331 => Opcode::PseudoVLE8_V_MF8_MASK, + 5332 => Opcode::PseudoVLM_V_B1, + 5333 => Opcode::PseudoVLM_V_B16, + 5334 => Opcode::PseudoVLM_V_B2, + 5335 => Opcode::PseudoVLM_V_B32, + 5336 => Opcode::PseudoVLM_V_B4, + 5337 => Opcode::PseudoVLM_V_B64, + 5338 => Opcode::PseudoVLM_V_B8, + 5339 => Opcode::PseudoVLOXEI16_V_M1_M1, + 5340 => Opcode::PseudoVLOXEI16_V_M1_M1_MASK, + 5341 => Opcode::PseudoVLOXEI16_V_M1_M2, + 5342 => Opcode::PseudoVLOXEI16_V_M1_M2_MASK, + 5343 => Opcode::PseudoVLOXEI16_V_M1_M4, + 5344 => Opcode::PseudoVLOXEI16_V_M1_M4_MASK, + 5345 => Opcode::PseudoVLOXEI16_V_M1_MF2, + 5346 => Opcode::PseudoVLOXEI16_V_M1_MF2_MASK, + 5347 => Opcode::PseudoVLOXEI16_V_M2_M1, + 5348 => Opcode::PseudoVLOXEI16_V_M2_M1_MASK, + 5349 => Opcode::PseudoVLOXEI16_V_M2_M2, + 5350 => Opcode::PseudoVLOXEI16_V_M2_M2_MASK, + 5351 => Opcode::PseudoVLOXEI16_V_M2_M4, + 5352 => Opcode::PseudoVLOXEI16_V_M2_M4_MASK, + 5353 => Opcode::PseudoVLOXEI16_V_M2_M8, + 5354 => Opcode::PseudoVLOXEI16_V_M2_M8_MASK, + 5355 => Opcode::PseudoVLOXEI16_V_M4_M2, + 5356 => Opcode::PseudoVLOXEI16_V_M4_M2_MASK, + 5357 => Opcode::PseudoVLOXEI16_V_M4_M4, + 5358 => Opcode::PseudoVLOXEI16_V_M4_M4_MASK, + 5359 => Opcode::PseudoVLOXEI16_V_M4_M8, + 5360 => Opcode::PseudoVLOXEI16_V_M4_M8_MASK, + 5361 => Opcode::PseudoVLOXEI16_V_M8_M4, + 5362 => Opcode::PseudoVLOXEI16_V_M8_M4_MASK, + 5363 => Opcode::PseudoVLOXEI16_V_M8_M8, + 5364 => Opcode::PseudoVLOXEI16_V_M8_M8_MASK, + 5365 => Opcode::PseudoVLOXEI16_V_MF2_M1, + 5366 => Opcode::PseudoVLOXEI16_V_MF2_M1_MASK, + 5367 => Opcode::PseudoVLOXEI16_V_MF2_M2, + 5368 => Opcode::PseudoVLOXEI16_V_MF2_M2_MASK, + 5369 => Opcode::PseudoVLOXEI16_V_MF2_MF2, + 5370 => Opcode::PseudoVLOXEI16_V_MF2_MF2_MASK, + 5371 => Opcode::PseudoVLOXEI16_V_MF2_MF4, + 5372 => Opcode::PseudoVLOXEI16_V_MF2_MF4_MASK, + 5373 => Opcode::PseudoVLOXEI16_V_MF4_M1, + 5374 => Opcode::PseudoVLOXEI16_V_MF4_M1_MASK, + 5375 => Opcode::PseudoVLOXEI16_V_MF4_MF2, + 5376 => Opcode::PseudoVLOXEI16_V_MF4_MF2_MASK, + 5377 => Opcode::PseudoVLOXEI16_V_MF4_MF4, + 5378 => Opcode::PseudoVLOXEI16_V_MF4_MF4_MASK, + 5379 => Opcode::PseudoVLOXEI16_V_MF4_MF8, + 5380 => Opcode::PseudoVLOXEI16_V_MF4_MF8_MASK, + 5381 => Opcode::PseudoVLOXEI32_V_M1_M1, + 5382 => Opcode::PseudoVLOXEI32_V_M1_M1_MASK, + 5383 => Opcode::PseudoVLOXEI32_V_M1_M2, + 5384 => Opcode::PseudoVLOXEI32_V_M1_M2_MASK, + 5385 => Opcode::PseudoVLOXEI32_V_M1_MF2, + 5386 => Opcode::PseudoVLOXEI32_V_M1_MF2_MASK, + 5387 => Opcode::PseudoVLOXEI32_V_M1_MF4, + 5388 => Opcode::PseudoVLOXEI32_V_M1_MF4_MASK, + 5389 => Opcode::PseudoVLOXEI32_V_M2_M1, + 5390 => Opcode::PseudoVLOXEI32_V_M2_M1_MASK, + 5391 => Opcode::PseudoVLOXEI32_V_M2_M2, + 5392 => Opcode::PseudoVLOXEI32_V_M2_M2_MASK, + 5393 => Opcode::PseudoVLOXEI32_V_M2_M4, + 5394 => Opcode::PseudoVLOXEI32_V_M2_M4_MASK, + 5395 => Opcode::PseudoVLOXEI32_V_M2_MF2, + 5396 => Opcode::PseudoVLOXEI32_V_M2_MF2_MASK, + 5397 => Opcode::PseudoVLOXEI32_V_M4_M1, + 5398 => Opcode::PseudoVLOXEI32_V_M4_M1_MASK, + 5399 => Opcode::PseudoVLOXEI32_V_M4_M2, + 5400 => Opcode::PseudoVLOXEI32_V_M4_M2_MASK, + 5401 => Opcode::PseudoVLOXEI32_V_M4_M4, + 5402 => Opcode::PseudoVLOXEI32_V_M4_M4_MASK, + 5403 => Opcode::PseudoVLOXEI32_V_M4_M8, + 5404 => Opcode::PseudoVLOXEI32_V_M4_M8_MASK, + 5405 => Opcode::PseudoVLOXEI32_V_M8_M2, + 5406 => Opcode::PseudoVLOXEI32_V_M8_M2_MASK, + 5407 => Opcode::PseudoVLOXEI32_V_M8_M4, + 5408 => Opcode::PseudoVLOXEI32_V_M8_M4_MASK, + 5409 => Opcode::PseudoVLOXEI32_V_M8_M8, + 5410 => Opcode::PseudoVLOXEI32_V_M8_M8_MASK, + 5411 => Opcode::PseudoVLOXEI32_V_MF2_M1, + 5412 => Opcode::PseudoVLOXEI32_V_MF2_M1_MASK, + 5413 => Opcode::PseudoVLOXEI32_V_MF2_MF2, + 5414 => Opcode::PseudoVLOXEI32_V_MF2_MF2_MASK, + 5415 => Opcode::PseudoVLOXEI32_V_MF2_MF4, + 5416 => Opcode::PseudoVLOXEI32_V_MF2_MF4_MASK, + 5417 => Opcode::PseudoVLOXEI32_V_MF2_MF8, + 5418 => Opcode::PseudoVLOXEI32_V_MF2_MF8_MASK, + 5419 => Opcode::PseudoVLOXEI64_V_M1_M1, + 5420 => Opcode::PseudoVLOXEI64_V_M1_M1_MASK, + 5421 => Opcode::PseudoVLOXEI64_V_M1_MF2, + 5422 => Opcode::PseudoVLOXEI64_V_M1_MF2_MASK, + 5423 => Opcode::PseudoVLOXEI64_V_M1_MF4, + 5424 => Opcode::PseudoVLOXEI64_V_M1_MF4_MASK, + 5425 => Opcode::PseudoVLOXEI64_V_M1_MF8, + 5426 => Opcode::PseudoVLOXEI64_V_M1_MF8_MASK, + 5427 => Opcode::PseudoVLOXEI64_V_M2_M1, + 5428 => Opcode::PseudoVLOXEI64_V_M2_M1_MASK, + 5429 => Opcode::PseudoVLOXEI64_V_M2_M2, + 5430 => Opcode::PseudoVLOXEI64_V_M2_M2_MASK, + 5431 => Opcode::PseudoVLOXEI64_V_M2_MF2, + 5432 => Opcode::PseudoVLOXEI64_V_M2_MF2_MASK, + 5433 => Opcode::PseudoVLOXEI64_V_M2_MF4, + 5434 => Opcode::PseudoVLOXEI64_V_M2_MF4_MASK, + 5435 => Opcode::PseudoVLOXEI64_V_M4_M1, + 5436 => Opcode::PseudoVLOXEI64_V_M4_M1_MASK, + 5437 => Opcode::PseudoVLOXEI64_V_M4_M2, + 5438 => Opcode::PseudoVLOXEI64_V_M4_M2_MASK, + 5439 => Opcode::PseudoVLOXEI64_V_M4_M4, + 5440 => Opcode::PseudoVLOXEI64_V_M4_M4_MASK, + 5441 => Opcode::PseudoVLOXEI64_V_M4_MF2, + 5442 => Opcode::PseudoVLOXEI64_V_M4_MF2_MASK, + 5443 => Opcode::PseudoVLOXEI64_V_M8_M1, + 5444 => Opcode::PseudoVLOXEI64_V_M8_M1_MASK, + 5445 => Opcode::PseudoVLOXEI64_V_M8_M2, + 5446 => Opcode::PseudoVLOXEI64_V_M8_M2_MASK, + 5447 => Opcode::PseudoVLOXEI64_V_M8_M4, + 5448 => Opcode::PseudoVLOXEI64_V_M8_M4_MASK, + 5449 => Opcode::PseudoVLOXEI64_V_M8_M8, + 5450 => Opcode::PseudoVLOXEI64_V_M8_M8_MASK, + 5451 => Opcode::PseudoVLOXEI8_V_M1_M1, + 5452 => Opcode::PseudoVLOXEI8_V_M1_M1_MASK, + 5453 => Opcode::PseudoVLOXEI8_V_M1_M2, + 5454 => Opcode::PseudoVLOXEI8_V_M1_M2_MASK, + 5455 => Opcode::PseudoVLOXEI8_V_M1_M4, + 5456 => Opcode::PseudoVLOXEI8_V_M1_M4_MASK, + 5457 => Opcode::PseudoVLOXEI8_V_M1_M8, + 5458 => Opcode::PseudoVLOXEI8_V_M1_M8_MASK, + 5459 => Opcode::PseudoVLOXEI8_V_M2_M2, + 5460 => Opcode::PseudoVLOXEI8_V_M2_M2_MASK, + 5461 => Opcode::PseudoVLOXEI8_V_M2_M4, + 5462 => Opcode::PseudoVLOXEI8_V_M2_M4_MASK, + 5463 => Opcode::PseudoVLOXEI8_V_M2_M8, + 5464 => Opcode::PseudoVLOXEI8_V_M2_M8_MASK, + 5465 => Opcode::PseudoVLOXEI8_V_M4_M4, + 5466 => Opcode::PseudoVLOXEI8_V_M4_M4_MASK, + 5467 => Opcode::PseudoVLOXEI8_V_M4_M8, + 5468 => Opcode::PseudoVLOXEI8_V_M4_M8_MASK, + 5469 => Opcode::PseudoVLOXEI8_V_M8_M8, + 5470 => Opcode::PseudoVLOXEI8_V_M8_M8_MASK, + 5471 => Opcode::PseudoVLOXEI8_V_MF2_M1, + 5472 => Opcode::PseudoVLOXEI8_V_MF2_M1_MASK, + 5473 => Opcode::PseudoVLOXEI8_V_MF2_M2, + 5474 => Opcode::PseudoVLOXEI8_V_MF2_M2_MASK, + 5475 => Opcode::PseudoVLOXEI8_V_MF2_M4, + 5476 => Opcode::PseudoVLOXEI8_V_MF2_M4_MASK, + 5477 => Opcode::PseudoVLOXEI8_V_MF2_MF2, + 5478 => Opcode::PseudoVLOXEI8_V_MF2_MF2_MASK, + 5479 => Opcode::PseudoVLOXEI8_V_MF4_M1, + 5480 => Opcode::PseudoVLOXEI8_V_MF4_M1_MASK, + 5481 => Opcode::PseudoVLOXEI8_V_MF4_M2, + 5482 => Opcode::PseudoVLOXEI8_V_MF4_M2_MASK, + 5483 => Opcode::PseudoVLOXEI8_V_MF4_MF2, + 5484 => Opcode::PseudoVLOXEI8_V_MF4_MF2_MASK, + 5485 => Opcode::PseudoVLOXEI8_V_MF4_MF4, + 5486 => Opcode::PseudoVLOXEI8_V_MF4_MF4_MASK, + 5487 => Opcode::PseudoVLOXEI8_V_MF8_M1, + 5488 => Opcode::PseudoVLOXEI8_V_MF8_M1_MASK, + 5489 => Opcode::PseudoVLOXEI8_V_MF8_MF2, + 5490 => Opcode::PseudoVLOXEI8_V_MF8_MF2_MASK, + 5491 => Opcode::PseudoVLOXEI8_V_MF8_MF4, + 5492 => Opcode::PseudoVLOXEI8_V_MF8_MF4_MASK, + 5493 => Opcode::PseudoVLOXEI8_V_MF8_MF8, + 5494 => Opcode::PseudoVLOXEI8_V_MF8_MF8_MASK, + 5495 => Opcode::PseudoVLOXSEG2EI16_V_M1_M1, + 5496 => Opcode::PseudoVLOXSEG2EI16_V_M1_M1_MASK, + 5497 => Opcode::PseudoVLOXSEG2EI16_V_M1_M2, + 5498 => Opcode::PseudoVLOXSEG2EI16_V_M1_M2_MASK, + 5499 => Opcode::PseudoVLOXSEG2EI16_V_M1_M4, + 5500 => Opcode::PseudoVLOXSEG2EI16_V_M1_M4_MASK, + 5501 => Opcode::PseudoVLOXSEG2EI16_V_M1_MF2, + 5502 => Opcode::PseudoVLOXSEG2EI16_V_M1_MF2_MASK, + 5503 => Opcode::PseudoVLOXSEG2EI16_V_M2_M1, + 5504 => Opcode::PseudoVLOXSEG2EI16_V_M2_M1_MASK, + 5505 => Opcode::PseudoVLOXSEG2EI16_V_M2_M2, + 5506 => Opcode::PseudoVLOXSEG2EI16_V_M2_M2_MASK, + 5507 => Opcode::PseudoVLOXSEG2EI16_V_M2_M4, + 5508 => Opcode::PseudoVLOXSEG2EI16_V_M2_M4_MASK, + 5509 => Opcode::PseudoVLOXSEG2EI16_V_M4_M2, + 5510 => Opcode::PseudoVLOXSEG2EI16_V_M4_M2_MASK, + 5511 => Opcode::PseudoVLOXSEG2EI16_V_M4_M4, + 5512 => Opcode::PseudoVLOXSEG2EI16_V_M4_M4_MASK, + 5513 => Opcode::PseudoVLOXSEG2EI16_V_M8_M4, + 5514 => Opcode::PseudoVLOXSEG2EI16_V_M8_M4_MASK, + 5515 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M1, + 5516 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M1_MASK, + 5517 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M2, + 5518 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M2_MASK, + 5519 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF2, + 5520 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, + 5521 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF4, + 5522 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, + 5523 => Opcode::PseudoVLOXSEG2EI16_V_MF4_M1, + 5524 => Opcode::PseudoVLOXSEG2EI16_V_MF4_M1_MASK, + 5525 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF2, + 5526 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, + 5527 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF4, + 5528 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, + 5529 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF8, + 5530 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, + 5531 => Opcode::PseudoVLOXSEG2EI32_V_M1_M1, + 5532 => Opcode::PseudoVLOXSEG2EI32_V_M1_M1_MASK, + 5533 => Opcode::PseudoVLOXSEG2EI32_V_M1_M2, + 5534 => Opcode::PseudoVLOXSEG2EI32_V_M1_M2_MASK, + 5535 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF2, + 5536 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF2_MASK, + 5537 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF4, + 5538 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF4_MASK, + 5539 => Opcode::PseudoVLOXSEG2EI32_V_M2_M1, + 5540 => Opcode::PseudoVLOXSEG2EI32_V_M2_M1_MASK, + 5541 => Opcode::PseudoVLOXSEG2EI32_V_M2_M2, + 5542 => Opcode::PseudoVLOXSEG2EI32_V_M2_M2_MASK, + 5543 => Opcode::PseudoVLOXSEG2EI32_V_M2_M4, + 5544 => Opcode::PseudoVLOXSEG2EI32_V_M2_M4_MASK, + 5545 => Opcode::PseudoVLOXSEG2EI32_V_M2_MF2, + 5546 => Opcode::PseudoVLOXSEG2EI32_V_M2_MF2_MASK, + 5547 => Opcode::PseudoVLOXSEG2EI32_V_M4_M1, + 5548 => Opcode::PseudoVLOXSEG2EI32_V_M4_M1_MASK, + 5549 => Opcode::PseudoVLOXSEG2EI32_V_M4_M2, + 5550 => Opcode::PseudoVLOXSEG2EI32_V_M4_M2_MASK, + 5551 => Opcode::PseudoVLOXSEG2EI32_V_M4_M4, + 5552 => Opcode::PseudoVLOXSEG2EI32_V_M4_M4_MASK, + 5553 => Opcode::PseudoVLOXSEG2EI32_V_M8_M2, + 5554 => Opcode::PseudoVLOXSEG2EI32_V_M8_M2_MASK, + 5555 => Opcode::PseudoVLOXSEG2EI32_V_M8_M4, + 5556 => Opcode::PseudoVLOXSEG2EI32_V_M8_M4_MASK, + 5557 => Opcode::PseudoVLOXSEG2EI32_V_MF2_M1, + 5558 => Opcode::PseudoVLOXSEG2EI32_V_MF2_M1_MASK, + 5559 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF2, + 5560 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, + 5561 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF4, + 5562 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, + 5563 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF8, + 5564 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, + 5565 => Opcode::PseudoVLOXSEG2EI64_V_M1_M1, + 5566 => Opcode::PseudoVLOXSEG2EI64_V_M1_M1_MASK, + 5567 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF2, + 5568 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF2_MASK, + 5569 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF4, + 5570 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF4_MASK, + 5571 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF8, + 5572 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF8_MASK, + 5573 => Opcode::PseudoVLOXSEG2EI64_V_M2_M1, + 5574 => Opcode::PseudoVLOXSEG2EI64_V_M2_M1_MASK, + 5575 => Opcode::PseudoVLOXSEG2EI64_V_M2_M2, + 5576 => Opcode::PseudoVLOXSEG2EI64_V_M2_M2_MASK, + 5577 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF2, + 5578 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF2_MASK, + 5579 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF4, + 5580 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF4_MASK, + 5581 => Opcode::PseudoVLOXSEG2EI64_V_M4_M1, + 5582 => Opcode::PseudoVLOXSEG2EI64_V_M4_M1_MASK, + 5583 => Opcode::PseudoVLOXSEG2EI64_V_M4_M2, + 5584 => Opcode::PseudoVLOXSEG2EI64_V_M4_M2_MASK, + 5585 => Opcode::PseudoVLOXSEG2EI64_V_M4_M4, + 5586 => Opcode::PseudoVLOXSEG2EI64_V_M4_M4_MASK, + 5587 => Opcode::PseudoVLOXSEG2EI64_V_M4_MF2, + 5588 => Opcode::PseudoVLOXSEG2EI64_V_M4_MF2_MASK, + 5589 => Opcode::PseudoVLOXSEG2EI64_V_M8_M1, + 5590 => Opcode::PseudoVLOXSEG2EI64_V_M8_M1_MASK, + 5591 => Opcode::PseudoVLOXSEG2EI64_V_M8_M2, + 5592 => Opcode::PseudoVLOXSEG2EI64_V_M8_M2_MASK, + 5593 => Opcode::PseudoVLOXSEG2EI64_V_M8_M4, + 5594 => Opcode::PseudoVLOXSEG2EI64_V_M8_M4_MASK, + 5595 => Opcode::PseudoVLOXSEG2EI8_V_M1_M1, + 5596 => Opcode::PseudoVLOXSEG2EI8_V_M1_M1_MASK, + 5597 => Opcode::PseudoVLOXSEG2EI8_V_M1_M2, + 5598 => Opcode::PseudoVLOXSEG2EI8_V_M1_M2_MASK, + 5599 => Opcode::PseudoVLOXSEG2EI8_V_M1_M4, + 5600 => Opcode::PseudoVLOXSEG2EI8_V_M1_M4_MASK, + 5601 => Opcode::PseudoVLOXSEG2EI8_V_M2_M2, + 5602 => Opcode::PseudoVLOXSEG2EI8_V_M2_M2_MASK, + 5603 => Opcode::PseudoVLOXSEG2EI8_V_M2_M4, + 5604 => Opcode::PseudoVLOXSEG2EI8_V_M2_M4_MASK, + 5605 => Opcode::PseudoVLOXSEG2EI8_V_M4_M4, + 5606 => Opcode::PseudoVLOXSEG2EI8_V_M4_M4_MASK, + 5607 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M1, + 5608 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M1_MASK, + 5609 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M2, + 5610 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M2_MASK, + 5611 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M4, + 5612 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M4_MASK, + 5613 => Opcode::PseudoVLOXSEG2EI8_V_MF2_MF2, + 5614 => Opcode::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, + 5615 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M1, + 5616 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M1_MASK, + 5617 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M2, + 5618 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M2_MASK, + 5619 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF2, + 5620 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, + 5621 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF4, + 5622 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, + 5623 => Opcode::PseudoVLOXSEG2EI8_V_MF8_M1, + 5624 => Opcode::PseudoVLOXSEG2EI8_V_MF8_M1_MASK, + 5625 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF2, + 5626 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, + 5627 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF4, + 5628 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, + 5629 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF8, + 5630 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, + 5631 => Opcode::PseudoVLOXSEG3EI16_V_M1_M1, + 5632 => Opcode::PseudoVLOXSEG3EI16_V_M1_M1_MASK, + 5633 => Opcode::PseudoVLOXSEG3EI16_V_M1_M2, + 5634 => Opcode::PseudoVLOXSEG3EI16_V_M1_M2_MASK, + 5635 => Opcode::PseudoVLOXSEG3EI16_V_M1_MF2, + 5636 => Opcode::PseudoVLOXSEG3EI16_V_M1_MF2_MASK, + 5637 => Opcode::PseudoVLOXSEG3EI16_V_M2_M1, + 5638 => Opcode::PseudoVLOXSEG3EI16_V_M2_M1_MASK, + 5639 => Opcode::PseudoVLOXSEG3EI16_V_M2_M2, + 5640 => Opcode::PseudoVLOXSEG3EI16_V_M2_M2_MASK, + 5641 => Opcode::PseudoVLOXSEG3EI16_V_M4_M2, + 5642 => Opcode::PseudoVLOXSEG3EI16_V_M4_M2_MASK, + 5643 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M1, + 5644 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M1_MASK, + 5645 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M2, + 5646 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M2_MASK, + 5647 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF2, + 5648 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, + 5649 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF4, + 5650 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, + 5651 => Opcode::PseudoVLOXSEG3EI16_V_MF4_M1, + 5652 => Opcode::PseudoVLOXSEG3EI16_V_MF4_M1_MASK, + 5653 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF2, + 5654 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, + 5655 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF4, + 5656 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, + 5657 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF8, + 5658 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, + 5659 => Opcode::PseudoVLOXSEG3EI32_V_M1_M1, + 5660 => Opcode::PseudoVLOXSEG3EI32_V_M1_M1_MASK, + 5661 => Opcode::PseudoVLOXSEG3EI32_V_M1_M2, + 5662 => Opcode::PseudoVLOXSEG3EI32_V_M1_M2_MASK, + 5663 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF2, + 5664 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF2_MASK, + 5665 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF4, + 5666 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF4_MASK, + 5667 => Opcode::PseudoVLOXSEG3EI32_V_M2_M1, + 5668 => Opcode::PseudoVLOXSEG3EI32_V_M2_M1_MASK, + 5669 => Opcode::PseudoVLOXSEG3EI32_V_M2_M2, + 5670 => Opcode::PseudoVLOXSEG3EI32_V_M2_M2_MASK, + 5671 => Opcode::PseudoVLOXSEG3EI32_V_M2_MF2, + 5672 => Opcode::PseudoVLOXSEG3EI32_V_M2_MF2_MASK, + 5673 => Opcode::PseudoVLOXSEG3EI32_V_M4_M1, + 5674 => Opcode::PseudoVLOXSEG3EI32_V_M4_M1_MASK, + 5675 => Opcode::PseudoVLOXSEG3EI32_V_M4_M2, + 5676 => Opcode::PseudoVLOXSEG3EI32_V_M4_M2_MASK, + 5677 => Opcode::PseudoVLOXSEG3EI32_V_M8_M2, + 5678 => Opcode::PseudoVLOXSEG3EI32_V_M8_M2_MASK, + 5679 => Opcode::PseudoVLOXSEG3EI32_V_MF2_M1, + 5680 => Opcode::PseudoVLOXSEG3EI32_V_MF2_M1_MASK, + 5681 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF2, + 5682 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, + 5683 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF4, + 5684 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, + 5685 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF8, + 5686 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, + 5687 => Opcode::PseudoVLOXSEG3EI64_V_M1_M1, + 5688 => Opcode::PseudoVLOXSEG3EI64_V_M1_M1_MASK, + 5689 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF2, + 5690 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF2_MASK, + 5691 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF4, + 5692 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF4_MASK, + 5693 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF8, + 5694 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF8_MASK, + 5695 => Opcode::PseudoVLOXSEG3EI64_V_M2_M1, + 5696 => Opcode::PseudoVLOXSEG3EI64_V_M2_M1_MASK, + 5697 => Opcode::PseudoVLOXSEG3EI64_V_M2_M2, + 5698 => Opcode::PseudoVLOXSEG3EI64_V_M2_M2_MASK, + 5699 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF2, + 5700 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF2_MASK, + 5701 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF4, + 5702 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF4_MASK, + 5703 => Opcode::PseudoVLOXSEG3EI64_V_M4_M1, + 5704 => Opcode::PseudoVLOXSEG3EI64_V_M4_M1_MASK, + 5705 => Opcode::PseudoVLOXSEG3EI64_V_M4_M2, + 5706 => Opcode::PseudoVLOXSEG3EI64_V_M4_M2_MASK, + 5707 => Opcode::PseudoVLOXSEG3EI64_V_M4_MF2, + 5708 => Opcode::PseudoVLOXSEG3EI64_V_M4_MF2_MASK, + 5709 => Opcode::PseudoVLOXSEG3EI64_V_M8_M1, + 5710 => Opcode::PseudoVLOXSEG3EI64_V_M8_M1_MASK, + 5711 => Opcode::PseudoVLOXSEG3EI64_V_M8_M2, + 5712 => Opcode::PseudoVLOXSEG3EI64_V_M8_M2_MASK, + 5713 => Opcode::PseudoVLOXSEG3EI8_V_M1_M1, + 5714 => Opcode::PseudoVLOXSEG3EI8_V_M1_M1_MASK, + 5715 => Opcode::PseudoVLOXSEG3EI8_V_M1_M2, + 5716 => Opcode::PseudoVLOXSEG3EI8_V_M1_M2_MASK, + 5717 => Opcode::PseudoVLOXSEG3EI8_V_M2_M2, + 5718 => Opcode::PseudoVLOXSEG3EI8_V_M2_M2_MASK, + 5719 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M1, + 5720 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M1_MASK, + 5721 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M2, + 5722 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M2_MASK, + 5723 => Opcode::PseudoVLOXSEG3EI8_V_MF2_MF2, + 5724 => Opcode::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, + 5725 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M1, + 5726 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M1_MASK, + 5727 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M2, + 5728 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M2_MASK, + 5729 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF2, + 5730 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, + 5731 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF4, + 5732 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, + 5733 => Opcode::PseudoVLOXSEG3EI8_V_MF8_M1, + 5734 => Opcode::PseudoVLOXSEG3EI8_V_MF8_M1_MASK, + 5735 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF2, + 5736 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, + 5737 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF4, + 5738 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, + 5739 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF8, + 5740 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, + 5741 => Opcode::PseudoVLOXSEG4EI16_V_M1_M1, + 5742 => Opcode::PseudoVLOXSEG4EI16_V_M1_M1_MASK, + 5743 => Opcode::PseudoVLOXSEG4EI16_V_M1_M2, + 5744 => Opcode::PseudoVLOXSEG4EI16_V_M1_M2_MASK, + 5745 => Opcode::PseudoVLOXSEG4EI16_V_M1_MF2, + 5746 => Opcode::PseudoVLOXSEG4EI16_V_M1_MF2_MASK, + 5747 => Opcode::PseudoVLOXSEG4EI16_V_M2_M1, + 5748 => Opcode::PseudoVLOXSEG4EI16_V_M2_M1_MASK, + 5749 => Opcode::PseudoVLOXSEG4EI16_V_M2_M2, + 5750 => Opcode::PseudoVLOXSEG4EI16_V_M2_M2_MASK, + 5751 => Opcode::PseudoVLOXSEG4EI16_V_M4_M2, + 5752 => Opcode::PseudoVLOXSEG4EI16_V_M4_M2_MASK, + 5753 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M1, + 5754 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M1_MASK, + 5755 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M2, + 5756 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M2_MASK, + 5757 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF2, + 5758 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, + 5759 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF4, + 5760 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, + 5761 => Opcode::PseudoVLOXSEG4EI16_V_MF4_M1, + 5762 => Opcode::PseudoVLOXSEG4EI16_V_MF4_M1_MASK, + 5763 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF2, + 5764 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, + 5765 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF4, + 5766 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, + 5767 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF8, + 5768 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, + 5769 => Opcode::PseudoVLOXSEG4EI32_V_M1_M1, + 5770 => Opcode::PseudoVLOXSEG4EI32_V_M1_M1_MASK, + 5771 => Opcode::PseudoVLOXSEG4EI32_V_M1_M2, + 5772 => Opcode::PseudoVLOXSEG4EI32_V_M1_M2_MASK, + 5773 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF2, + 5774 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF2_MASK, + 5775 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF4, + 5776 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF4_MASK, + 5777 => Opcode::PseudoVLOXSEG4EI32_V_M2_M1, + 5778 => Opcode::PseudoVLOXSEG4EI32_V_M2_M1_MASK, + 5779 => Opcode::PseudoVLOXSEG4EI32_V_M2_M2, + 5780 => Opcode::PseudoVLOXSEG4EI32_V_M2_M2_MASK, + 5781 => Opcode::PseudoVLOXSEG4EI32_V_M2_MF2, + 5782 => Opcode::PseudoVLOXSEG4EI32_V_M2_MF2_MASK, + 5783 => Opcode::PseudoVLOXSEG4EI32_V_M4_M1, + 5784 => Opcode::PseudoVLOXSEG4EI32_V_M4_M1_MASK, + 5785 => Opcode::PseudoVLOXSEG4EI32_V_M4_M2, + 5786 => Opcode::PseudoVLOXSEG4EI32_V_M4_M2_MASK, + 5787 => Opcode::PseudoVLOXSEG4EI32_V_M8_M2, + 5788 => Opcode::PseudoVLOXSEG4EI32_V_M8_M2_MASK, + 5789 => Opcode::PseudoVLOXSEG4EI32_V_MF2_M1, + 5790 => Opcode::PseudoVLOXSEG4EI32_V_MF2_M1_MASK, + 5791 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF2, + 5792 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, + 5793 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF4, + 5794 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, + 5795 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF8, + 5796 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, + 5797 => Opcode::PseudoVLOXSEG4EI64_V_M1_M1, + 5798 => Opcode::PseudoVLOXSEG4EI64_V_M1_M1_MASK, + 5799 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF2, + 5800 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF2_MASK, + 5801 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF4, + 5802 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF4_MASK, + 5803 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF8, + 5804 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF8_MASK, + 5805 => Opcode::PseudoVLOXSEG4EI64_V_M2_M1, + 5806 => Opcode::PseudoVLOXSEG4EI64_V_M2_M1_MASK, + 5807 => Opcode::PseudoVLOXSEG4EI64_V_M2_M2, + 5808 => Opcode::PseudoVLOXSEG4EI64_V_M2_M2_MASK, + 5809 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF2, + 5810 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF2_MASK, + 5811 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF4, + 5812 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF4_MASK, + 5813 => Opcode::PseudoVLOXSEG4EI64_V_M4_M1, + 5814 => Opcode::PseudoVLOXSEG4EI64_V_M4_M1_MASK, + 5815 => Opcode::PseudoVLOXSEG4EI64_V_M4_M2, + 5816 => Opcode::PseudoVLOXSEG4EI64_V_M4_M2_MASK, + 5817 => Opcode::PseudoVLOXSEG4EI64_V_M4_MF2, + 5818 => Opcode::PseudoVLOXSEG4EI64_V_M4_MF2_MASK, + 5819 => Opcode::PseudoVLOXSEG4EI64_V_M8_M1, + 5820 => Opcode::PseudoVLOXSEG4EI64_V_M8_M1_MASK, + 5821 => Opcode::PseudoVLOXSEG4EI64_V_M8_M2, + 5822 => Opcode::PseudoVLOXSEG4EI64_V_M8_M2_MASK, + 5823 => Opcode::PseudoVLOXSEG4EI8_V_M1_M1, + 5824 => Opcode::PseudoVLOXSEG4EI8_V_M1_M1_MASK, + 5825 => Opcode::PseudoVLOXSEG4EI8_V_M1_M2, + 5826 => Opcode::PseudoVLOXSEG4EI8_V_M1_M2_MASK, + 5827 => Opcode::PseudoVLOXSEG4EI8_V_M2_M2, + 5828 => Opcode::PseudoVLOXSEG4EI8_V_M2_M2_MASK, + 5829 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M1, + 5830 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M1_MASK, + 5831 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M2, + 5832 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M2_MASK, + 5833 => Opcode::PseudoVLOXSEG4EI8_V_MF2_MF2, + 5834 => Opcode::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, + 5835 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M1, + 5836 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M1_MASK, + 5837 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M2, + 5838 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M2_MASK, + 5839 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF2, + 5840 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, + 5841 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF4, + 5842 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, + 5843 => Opcode::PseudoVLOXSEG4EI8_V_MF8_M1, + 5844 => Opcode::PseudoVLOXSEG4EI8_V_MF8_M1_MASK, + 5845 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF2, + 5846 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, + 5847 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF4, + 5848 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, + 5849 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF8, + 5850 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, + 5851 => Opcode::PseudoVLOXSEG5EI16_V_M1_M1, + 5852 => Opcode::PseudoVLOXSEG5EI16_V_M1_M1_MASK, + 5853 => Opcode::PseudoVLOXSEG5EI16_V_M1_MF2, + 5854 => Opcode::PseudoVLOXSEG5EI16_V_M1_MF2_MASK, + 5855 => Opcode::PseudoVLOXSEG5EI16_V_M2_M1, + 5856 => Opcode::PseudoVLOXSEG5EI16_V_M2_M1_MASK, + 5857 => Opcode::PseudoVLOXSEG5EI16_V_MF2_M1, + 5858 => Opcode::PseudoVLOXSEG5EI16_V_MF2_M1_MASK, + 5859 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF2, + 5860 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, + 5861 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF4, + 5862 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, + 5863 => Opcode::PseudoVLOXSEG5EI16_V_MF4_M1, + 5864 => Opcode::PseudoVLOXSEG5EI16_V_MF4_M1_MASK, + 5865 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF2, + 5866 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, + 5867 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF4, + 5868 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, + 5869 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF8, + 5870 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, + 5871 => Opcode::PseudoVLOXSEG5EI32_V_M1_M1, + 5872 => Opcode::PseudoVLOXSEG5EI32_V_M1_M1_MASK, + 5873 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF2, + 5874 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF2_MASK, + 5875 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF4, + 5876 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF4_MASK, + 5877 => Opcode::PseudoVLOXSEG5EI32_V_M2_M1, + 5878 => Opcode::PseudoVLOXSEG5EI32_V_M2_M1_MASK, + 5879 => Opcode::PseudoVLOXSEG5EI32_V_M2_MF2, + 5880 => Opcode::PseudoVLOXSEG5EI32_V_M2_MF2_MASK, + 5881 => Opcode::PseudoVLOXSEG5EI32_V_M4_M1, + 5882 => Opcode::PseudoVLOXSEG5EI32_V_M4_M1_MASK, + 5883 => Opcode::PseudoVLOXSEG5EI32_V_MF2_M1, + 5884 => Opcode::PseudoVLOXSEG5EI32_V_MF2_M1_MASK, + 5885 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF2, + 5886 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, + 5887 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF4, + 5888 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, + 5889 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF8, + 5890 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, + 5891 => Opcode::PseudoVLOXSEG5EI64_V_M1_M1, + 5892 => Opcode::PseudoVLOXSEG5EI64_V_M1_M1_MASK, + 5893 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF2, + 5894 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF2_MASK, + 5895 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF4, + 5896 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF4_MASK, + 5897 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF8, + 5898 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF8_MASK, + 5899 => Opcode::PseudoVLOXSEG5EI64_V_M2_M1, + 5900 => Opcode::PseudoVLOXSEG5EI64_V_M2_M1_MASK, + 5901 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF2, + 5902 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF2_MASK, + 5903 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF4, + 5904 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF4_MASK, + 5905 => Opcode::PseudoVLOXSEG5EI64_V_M4_M1, + 5906 => Opcode::PseudoVLOXSEG5EI64_V_M4_M1_MASK, + 5907 => Opcode::PseudoVLOXSEG5EI64_V_M4_MF2, + 5908 => Opcode::PseudoVLOXSEG5EI64_V_M4_MF2_MASK, + 5909 => Opcode::PseudoVLOXSEG5EI64_V_M8_M1, + 5910 => Opcode::PseudoVLOXSEG5EI64_V_M8_M1_MASK, + 5911 => Opcode::PseudoVLOXSEG5EI8_V_M1_M1, + 5912 => Opcode::PseudoVLOXSEG5EI8_V_M1_M1_MASK, + 5913 => Opcode::PseudoVLOXSEG5EI8_V_MF2_M1, + 5914 => Opcode::PseudoVLOXSEG5EI8_V_MF2_M1_MASK, + 5915 => Opcode::PseudoVLOXSEG5EI8_V_MF2_MF2, + 5916 => Opcode::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, + 5917 => Opcode::PseudoVLOXSEG5EI8_V_MF4_M1, + 5918 => Opcode::PseudoVLOXSEG5EI8_V_MF4_M1_MASK, + 5919 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF2, + 5920 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, + 5921 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF4, + 5922 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, + 5923 => Opcode::PseudoVLOXSEG5EI8_V_MF8_M1, + 5924 => Opcode::PseudoVLOXSEG5EI8_V_MF8_M1_MASK, + 5925 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF2, + 5926 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, + 5927 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF4, + 5928 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, + 5929 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF8, + 5930 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, + 5931 => Opcode::PseudoVLOXSEG6EI16_V_M1_M1, + 5932 => Opcode::PseudoVLOXSEG6EI16_V_M1_M1_MASK, + 5933 => Opcode::PseudoVLOXSEG6EI16_V_M1_MF2, + 5934 => Opcode::PseudoVLOXSEG6EI16_V_M1_MF2_MASK, + 5935 => Opcode::PseudoVLOXSEG6EI16_V_M2_M1, + 5936 => Opcode::PseudoVLOXSEG6EI16_V_M2_M1_MASK, + 5937 => Opcode::PseudoVLOXSEG6EI16_V_MF2_M1, + 5938 => Opcode::PseudoVLOXSEG6EI16_V_MF2_M1_MASK, + 5939 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF2, + 5940 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, + 5941 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF4, + 5942 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, + 5943 => Opcode::PseudoVLOXSEG6EI16_V_MF4_M1, + 5944 => Opcode::PseudoVLOXSEG6EI16_V_MF4_M1_MASK, + 5945 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF2, + 5946 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, + 5947 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF4, + 5948 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, + 5949 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF8, + 5950 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, + 5951 => Opcode::PseudoVLOXSEG6EI32_V_M1_M1, + 5952 => Opcode::PseudoVLOXSEG6EI32_V_M1_M1_MASK, + 5953 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF2, + 5954 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF2_MASK, + 5955 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF4, + 5956 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF4_MASK, + 5957 => Opcode::PseudoVLOXSEG6EI32_V_M2_M1, + 5958 => Opcode::PseudoVLOXSEG6EI32_V_M2_M1_MASK, + 5959 => Opcode::PseudoVLOXSEG6EI32_V_M2_MF2, + 5960 => Opcode::PseudoVLOXSEG6EI32_V_M2_MF2_MASK, + 5961 => Opcode::PseudoVLOXSEG6EI32_V_M4_M1, + 5962 => Opcode::PseudoVLOXSEG6EI32_V_M4_M1_MASK, + 5963 => Opcode::PseudoVLOXSEG6EI32_V_MF2_M1, + 5964 => Opcode::PseudoVLOXSEG6EI32_V_MF2_M1_MASK, + 5965 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF2, + 5966 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, + 5967 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF4, + 5968 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, + 5969 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF8, + 5970 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, + 5971 => Opcode::PseudoVLOXSEG6EI64_V_M1_M1, + 5972 => Opcode::PseudoVLOXSEG6EI64_V_M1_M1_MASK, + 5973 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF2, + 5974 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF2_MASK, + 5975 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF4, + 5976 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF4_MASK, + 5977 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF8, + 5978 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF8_MASK, + 5979 => Opcode::PseudoVLOXSEG6EI64_V_M2_M1, + 5980 => Opcode::PseudoVLOXSEG6EI64_V_M2_M1_MASK, + 5981 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF2, + 5982 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF2_MASK, + 5983 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF4, + 5984 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF4_MASK, + 5985 => Opcode::PseudoVLOXSEG6EI64_V_M4_M1, + 5986 => Opcode::PseudoVLOXSEG6EI64_V_M4_M1_MASK, + 5987 => Opcode::PseudoVLOXSEG6EI64_V_M4_MF2, + 5988 => Opcode::PseudoVLOXSEG6EI64_V_M4_MF2_MASK, + 5989 => Opcode::PseudoVLOXSEG6EI64_V_M8_M1, + 5990 => Opcode::PseudoVLOXSEG6EI64_V_M8_M1_MASK, + 5991 => Opcode::PseudoVLOXSEG6EI8_V_M1_M1, + 5992 => Opcode::PseudoVLOXSEG6EI8_V_M1_M1_MASK, + 5993 => Opcode::PseudoVLOXSEG6EI8_V_MF2_M1, + 5994 => Opcode::PseudoVLOXSEG6EI8_V_MF2_M1_MASK, + 5995 => Opcode::PseudoVLOXSEG6EI8_V_MF2_MF2, + 5996 => Opcode::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, + 5997 => Opcode::PseudoVLOXSEG6EI8_V_MF4_M1, + 5998 => Opcode::PseudoVLOXSEG6EI8_V_MF4_M1_MASK, + 5999 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF2, + 6000 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, + 6001 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF4, + 6002 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, + 6003 => Opcode::PseudoVLOXSEG6EI8_V_MF8_M1, + 6004 => Opcode::PseudoVLOXSEG6EI8_V_MF8_M1_MASK, + 6005 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF2, + 6006 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, + 6007 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF4, + 6008 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, + 6009 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF8, + 6010 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, + 6011 => Opcode::PseudoVLOXSEG7EI16_V_M1_M1, + 6012 => Opcode::PseudoVLOXSEG7EI16_V_M1_M1_MASK, + 6013 => Opcode::PseudoVLOXSEG7EI16_V_M1_MF2, + 6014 => Opcode::PseudoVLOXSEG7EI16_V_M1_MF2_MASK, + 6015 => Opcode::PseudoVLOXSEG7EI16_V_M2_M1, + 6016 => Opcode::PseudoVLOXSEG7EI16_V_M2_M1_MASK, + 6017 => Opcode::PseudoVLOXSEG7EI16_V_MF2_M1, + 6018 => Opcode::PseudoVLOXSEG7EI16_V_MF2_M1_MASK, + 6019 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF2, + 6020 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, + 6021 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF4, + 6022 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, + 6023 => Opcode::PseudoVLOXSEG7EI16_V_MF4_M1, + 6024 => Opcode::PseudoVLOXSEG7EI16_V_MF4_M1_MASK, + 6025 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF2, + 6026 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, + 6027 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF4, + 6028 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, + 6029 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF8, + 6030 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, + 6031 => Opcode::PseudoVLOXSEG7EI32_V_M1_M1, + 6032 => Opcode::PseudoVLOXSEG7EI32_V_M1_M1_MASK, + 6033 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF2, + 6034 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF2_MASK, + 6035 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF4, + 6036 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF4_MASK, + 6037 => Opcode::PseudoVLOXSEG7EI32_V_M2_M1, + 6038 => Opcode::PseudoVLOXSEG7EI32_V_M2_M1_MASK, + 6039 => Opcode::PseudoVLOXSEG7EI32_V_M2_MF2, + 6040 => Opcode::PseudoVLOXSEG7EI32_V_M2_MF2_MASK, + 6041 => Opcode::PseudoVLOXSEG7EI32_V_M4_M1, + 6042 => Opcode::PseudoVLOXSEG7EI32_V_M4_M1_MASK, + 6043 => Opcode::PseudoVLOXSEG7EI32_V_MF2_M1, + 6044 => Opcode::PseudoVLOXSEG7EI32_V_MF2_M1_MASK, + 6045 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF2, + 6046 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, + 6047 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF4, + 6048 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, + 6049 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF8, + 6050 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, + 6051 => Opcode::PseudoVLOXSEG7EI64_V_M1_M1, + 6052 => Opcode::PseudoVLOXSEG7EI64_V_M1_M1_MASK, + 6053 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF2, + 6054 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF2_MASK, + 6055 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF4, + 6056 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF4_MASK, + 6057 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF8, + 6058 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF8_MASK, + 6059 => Opcode::PseudoVLOXSEG7EI64_V_M2_M1, + 6060 => Opcode::PseudoVLOXSEG7EI64_V_M2_M1_MASK, + 6061 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF2, + 6062 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF2_MASK, + 6063 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF4, + 6064 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF4_MASK, + 6065 => Opcode::PseudoVLOXSEG7EI64_V_M4_M1, + 6066 => Opcode::PseudoVLOXSEG7EI64_V_M4_M1_MASK, + 6067 => Opcode::PseudoVLOXSEG7EI64_V_M4_MF2, + 6068 => Opcode::PseudoVLOXSEG7EI64_V_M4_MF2_MASK, + 6069 => Opcode::PseudoVLOXSEG7EI64_V_M8_M1, + 6070 => Opcode::PseudoVLOXSEG7EI64_V_M8_M1_MASK, + 6071 => Opcode::PseudoVLOXSEG7EI8_V_M1_M1, + 6072 => Opcode::PseudoVLOXSEG7EI8_V_M1_M1_MASK, + 6073 => Opcode::PseudoVLOXSEG7EI8_V_MF2_M1, + 6074 => Opcode::PseudoVLOXSEG7EI8_V_MF2_M1_MASK, + 6075 => Opcode::PseudoVLOXSEG7EI8_V_MF2_MF2, + 6076 => Opcode::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, + 6077 => Opcode::PseudoVLOXSEG7EI8_V_MF4_M1, + 6078 => Opcode::PseudoVLOXSEG7EI8_V_MF4_M1_MASK, + 6079 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF2, + 6080 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, + 6081 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF4, + 6082 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, + 6083 => Opcode::PseudoVLOXSEG7EI8_V_MF8_M1, + 6084 => Opcode::PseudoVLOXSEG7EI8_V_MF8_M1_MASK, + 6085 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF2, + 6086 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, + 6087 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF4, + 6088 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, + 6089 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF8, + 6090 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, + 6091 => Opcode::PseudoVLOXSEG8EI16_V_M1_M1, + 6092 => Opcode::PseudoVLOXSEG8EI16_V_M1_M1_MASK, + 6093 => Opcode::PseudoVLOXSEG8EI16_V_M1_MF2, + 6094 => Opcode::PseudoVLOXSEG8EI16_V_M1_MF2_MASK, + 6095 => Opcode::PseudoVLOXSEG8EI16_V_M2_M1, + 6096 => Opcode::PseudoVLOXSEG8EI16_V_M2_M1_MASK, + 6097 => Opcode::PseudoVLOXSEG8EI16_V_MF2_M1, + 6098 => Opcode::PseudoVLOXSEG8EI16_V_MF2_M1_MASK, + 6099 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF2, + 6100 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, + 6101 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF4, + 6102 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, + 6103 => Opcode::PseudoVLOXSEG8EI16_V_MF4_M1, + 6104 => Opcode::PseudoVLOXSEG8EI16_V_MF4_M1_MASK, + 6105 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF2, + 6106 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, + 6107 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF4, + 6108 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, + 6109 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF8, + 6110 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, + 6111 => Opcode::PseudoVLOXSEG8EI32_V_M1_M1, + 6112 => Opcode::PseudoVLOXSEG8EI32_V_M1_M1_MASK, + 6113 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF2, + 6114 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF2_MASK, + 6115 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF4, + 6116 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF4_MASK, + 6117 => Opcode::PseudoVLOXSEG8EI32_V_M2_M1, + 6118 => Opcode::PseudoVLOXSEG8EI32_V_M2_M1_MASK, + 6119 => Opcode::PseudoVLOXSEG8EI32_V_M2_MF2, + 6120 => Opcode::PseudoVLOXSEG8EI32_V_M2_MF2_MASK, + 6121 => Opcode::PseudoVLOXSEG8EI32_V_M4_M1, + 6122 => Opcode::PseudoVLOXSEG8EI32_V_M4_M1_MASK, + 6123 => Opcode::PseudoVLOXSEG8EI32_V_MF2_M1, + 6124 => Opcode::PseudoVLOXSEG8EI32_V_MF2_M1_MASK, + 6125 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF2, + 6126 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, + 6127 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF4, + 6128 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, + 6129 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF8, + 6130 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, + 6131 => Opcode::PseudoVLOXSEG8EI64_V_M1_M1, + 6132 => Opcode::PseudoVLOXSEG8EI64_V_M1_M1_MASK, + 6133 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF2, + 6134 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF2_MASK, + 6135 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF4, + 6136 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF4_MASK, + 6137 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF8, + 6138 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF8_MASK, + 6139 => Opcode::PseudoVLOXSEG8EI64_V_M2_M1, + 6140 => Opcode::PseudoVLOXSEG8EI64_V_M2_M1_MASK, + 6141 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF2, + 6142 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF2_MASK, + 6143 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF4, + 6144 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF4_MASK, + 6145 => Opcode::PseudoVLOXSEG8EI64_V_M4_M1, + 6146 => Opcode::PseudoVLOXSEG8EI64_V_M4_M1_MASK, + 6147 => Opcode::PseudoVLOXSEG8EI64_V_M4_MF2, + 6148 => Opcode::PseudoVLOXSEG8EI64_V_M4_MF2_MASK, + 6149 => Opcode::PseudoVLOXSEG8EI64_V_M8_M1, + 6150 => Opcode::PseudoVLOXSEG8EI64_V_M8_M1_MASK, + 6151 => Opcode::PseudoVLOXSEG8EI8_V_M1_M1, + 6152 => Opcode::PseudoVLOXSEG8EI8_V_M1_M1_MASK, + 6153 => Opcode::PseudoVLOXSEG8EI8_V_MF2_M1, + 6154 => Opcode::PseudoVLOXSEG8EI8_V_MF2_M1_MASK, + 6155 => Opcode::PseudoVLOXSEG8EI8_V_MF2_MF2, + 6156 => Opcode::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, + 6157 => Opcode::PseudoVLOXSEG8EI8_V_MF4_M1, + 6158 => Opcode::PseudoVLOXSEG8EI8_V_MF4_M1_MASK, + 6159 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF2, + 6160 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, + 6161 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF4, + 6162 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, + 6163 => Opcode::PseudoVLOXSEG8EI8_V_MF8_M1, + 6164 => Opcode::PseudoVLOXSEG8EI8_V_MF8_M1_MASK, + 6165 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF2, + 6166 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, + 6167 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF4, + 6168 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, + 6169 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF8, + 6170 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, + 6171 => Opcode::PseudoVLSE16_V_M1, + 6172 => Opcode::PseudoVLSE16_V_M1_MASK, + 6173 => Opcode::PseudoVLSE16_V_M2, + 6174 => Opcode::PseudoVLSE16_V_M2_MASK, + 6175 => Opcode::PseudoVLSE16_V_M4, + 6176 => Opcode::PseudoVLSE16_V_M4_MASK, + 6177 => Opcode::PseudoVLSE16_V_M8, + 6178 => Opcode::PseudoVLSE16_V_M8_MASK, + 6179 => Opcode::PseudoVLSE16_V_MF2, + 6180 => Opcode::PseudoVLSE16_V_MF2_MASK, + 6181 => Opcode::PseudoVLSE16_V_MF4, + 6182 => Opcode::PseudoVLSE16_V_MF4_MASK, + 6183 => Opcode::PseudoVLSE32_V_M1, + 6184 => Opcode::PseudoVLSE32_V_M1_MASK, + 6185 => Opcode::PseudoVLSE32_V_M2, + 6186 => Opcode::PseudoVLSE32_V_M2_MASK, + 6187 => Opcode::PseudoVLSE32_V_M4, + 6188 => Opcode::PseudoVLSE32_V_M4_MASK, + 6189 => Opcode::PseudoVLSE32_V_M8, + 6190 => Opcode::PseudoVLSE32_V_M8_MASK, + 6191 => Opcode::PseudoVLSE32_V_MF2, + 6192 => Opcode::PseudoVLSE32_V_MF2_MASK, + 6193 => Opcode::PseudoVLSE64_V_M1, + 6194 => Opcode::PseudoVLSE64_V_M1_MASK, + 6195 => Opcode::PseudoVLSE64_V_M2, + 6196 => Opcode::PseudoVLSE64_V_M2_MASK, + 6197 => Opcode::PseudoVLSE64_V_M4, + 6198 => Opcode::PseudoVLSE64_V_M4_MASK, + 6199 => Opcode::PseudoVLSE64_V_M8, + 6200 => Opcode::PseudoVLSE64_V_M8_MASK, + 6201 => Opcode::PseudoVLSE8_V_M1, + 6202 => Opcode::PseudoVLSE8_V_M1_MASK, + 6203 => Opcode::PseudoVLSE8_V_M2, + 6204 => Opcode::PseudoVLSE8_V_M2_MASK, + 6205 => Opcode::PseudoVLSE8_V_M4, + 6206 => Opcode::PseudoVLSE8_V_M4_MASK, + 6207 => Opcode::PseudoVLSE8_V_M8, + 6208 => Opcode::PseudoVLSE8_V_M8_MASK, + 6209 => Opcode::PseudoVLSE8_V_MF2, + 6210 => Opcode::PseudoVLSE8_V_MF2_MASK, + 6211 => Opcode::PseudoVLSE8_V_MF4, + 6212 => Opcode::PseudoVLSE8_V_MF4_MASK, + 6213 => Opcode::PseudoVLSE8_V_MF8, + 6214 => Opcode::PseudoVLSE8_V_MF8_MASK, + 6215 => Opcode::PseudoVLSEG2E16FF_V_M1, + 6216 => Opcode::PseudoVLSEG2E16FF_V_M1_MASK, + 6217 => Opcode::PseudoVLSEG2E16FF_V_M2, + 6218 => Opcode::PseudoVLSEG2E16FF_V_M2_MASK, + 6219 => Opcode::PseudoVLSEG2E16FF_V_M4, + 6220 => Opcode::PseudoVLSEG2E16FF_V_M4_MASK, + 6221 => Opcode::PseudoVLSEG2E16FF_V_MF2, + 6222 => Opcode::PseudoVLSEG2E16FF_V_MF2_MASK, + 6223 => Opcode::PseudoVLSEG2E16FF_V_MF4, + 6224 => Opcode::PseudoVLSEG2E16FF_V_MF4_MASK, + 6225 => Opcode::PseudoVLSEG2E16_V_M1, + 6226 => Opcode::PseudoVLSEG2E16_V_M1_MASK, + 6227 => Opcode::PseudoVLSEG2E16_V_M2, + 6228 => Opcode::PseudoVLSEG2E16_V_M2_MASK, + 6229 => Opcode::PseudoVLSEG2E16_V_M4, + 6230 => Opcode::PseudoVLSEG2E16_V_M4_MASK, + 6231 => Opcode::PseudoVLSEG2E16_V_MF2, + 6232 => Opcode::PseudoVLSEG2E16_V_MF2_MASK, + 6233 => Opcode::PseudoVLSEG2E16_V_MF4, + 6234 => Opcode::PseudoVLSEG2E16_V_MF4_MASK, + 6235 => Opcode::PseudoVLSEG2E32FF_V_M1, + 6236 => Opcode::PseudoVLSEG2E32FF_V_M1_MASK, + 6237 => Opcode::PseudoVLSEG2E32FF_V_M2, + 6238 => Opcode::PseudoVLSEG2E32FF_V_M2_MASK, + 6239 => Opcode::PseudoVLSEG2E32FF_V_M4, + 6240 => Opcode::PseudoVLSEG2E32FF_V_M4_MASK, + 6241 => Opcode::PseudoVLSEG2E32FF_V_MF2, + 6242 => Opcode::PseudoVLSEG2E32FF_V_MF2_MASK, + 6243 => Opcode::PseudoVLSEG2E32_V_M1, + 6244 => Opcode::PseudoVLSEG2E32_V_M1_MASK, + 6245 => Opcode::PseudoVLSEG2E32_V_M2, + 6246 => Opcode::PseudoVLSEG2E32_V_M2_MASK, + 6247 => Opcode::PseudoVLSEG2E32_V_M4, + 6248 => Opcode::PseudoVLSEG2E32_V_M4_MASK, + 6249 => Opcode::PseudoVLSEG2E32_V_MF2, + 6250 => Opcode::PseudoVLSEG2E32_V_MF2_MASK, + 6251 => Opcode::PseudoVLSEG2E64FF_V_M1, + 6252 => Opcode::PseudoVLSEG2E64FF_V_M1_MASK, + 6253 => Opcode::PseudoVLSEG2E64FF_V_M2, + 6254 => Opcode::PseudoVLSEG2E64FF_V_M2_MASK, + 6255 => Opcode::PseudoVLSEG2E64FF_V_M4, + 6256 => Opcode::PseudoVLSEG2E64FF_V_M4_MASK, + 6257 => Opcode::PseudoVLSEG2E64_V_M1, + 6258 => Opcode::PseudoVLSEG2E64_V_M1_MASK, + 6259 => Opcode::PseudoVLSEG2E64_V_M2, + 6260 => Opcode::PseudoVLSEG2E64_V_M2_MASK, + 6261 => Opcode::PseudoVLSEG2E64_V_M4, + 6262 => Opcode::PseudoVLSEG2E64_V_M4_MASK, + 6263 => Opcode::PseudoVLSEG2E8FF_V_M1, + 6264 => Opcode::PseudoVLSEG2E8FF_V_M1_MASK, + 6265 => Opcode::PseudoVLSEG2E8FF_V_M2, + 6266 => Opcode::PseudoVLSEG2E8FF_V_M2_MASK, + 6267 => Opcode::PseudoVLSEG2E8FF_V_M4, + 6268 => Opcode::PseudoVLSEG2E8FF_V_M4_MASK, + 6269 => Opcode::PseudoVLSEG2E8FF_V_MF2, + 6270 => Opcode::PseudoVLSEG2E8FF_V_MF2_MASK, + 6271 => Opcode::PseudoVLSEG2E8FF_V_MF4, + 6272 => Opcode::PseudoVLSEG2E8FF_V_MF4_MASK, + 6273 => Opcode::PseudoVLSEG2E8FF_V_MF8, + 6274 => Opcode::PseudoVLSEG2E8FF_V_MF8_MASK, + 6275 => Opcode::PseudoVLSEG2E8_V_M1, + 6276 => Opcode::PseudoVLSEG2E8_V_M1_MASK, + 6277 => Opcode::PseudoVLSEG2E8_V_M2, + 6278 => Opcode::PseudoVLSEG2E8_V_M2_MASK, + 6279 => Opcode::PseudoVLSEG2E8_V_M4, + 6280 => Opcode::PseudoVLSEG2E8_V_M4_MASK, + 6281 => Opcode::PseudoVLSEG2E8_V_MF2, + 6282 => Opcode::PseudoVLSEG2E8_V_MF2_MASK, + 6283 => Opcode::PseudoVLSEG2E8_V_MF4, + 6284 => Opcode::PseudoVLSEG2E8_V_MF4_MASK, + 6285 => Opcode::PseudoVLSEG2E8_V_MF8, + 6286 => Opcode::PseudoVLSEG2E8_V_MF8_MASK, + 6287 => Opcode::PseudoVLSEG3E16FF_V_M1, + 6288 => Opcode::PseudoVLSEG3E16FF_V_M1_MASK, + 6289 => Opcode::PseudoVLSEG3E16FF_V_M2, + 6290 => Opcode::PseudoVLSEG3E16FF_V_M2_MASK, + 6291 => Opcode::PseudoVLSEG3E16FF_V_MF2, + 6292 => Opcode::PseudoVLSEG3E16FF_V_MF2_MASK, + 6293 => Opcode::PseudoVLSEG3E16FF_V_MF4, + 6294 => Opcode::PseudoVLSEG3E16FF_V_MF4_MASK, + 6295 => Opcode::PseudoVLSEG3E16_V_M1, + 6296 => Opcode::PseudoVLSEG3E16_V_M1_MASK, + 6297 => Opcode::PseudoVLSEG3E16_V_M2, + 6298 => Opcode::PseudoVLSEG3E16_V_M2_MASK, + 6299 => Opcode::PseudoVLSEG3E16_V_MF2, + 6300 => Opcode::PseudoVLSEG3E16_V_MF2_MASK, + 6301 => Opcode::PseudoVLSEG3E16_V_MF4, + 6302 => Opcode::PseudoVLSEG3E16_V_MF4_MASK, + 6303 => Opcode::PseudoVLSEG3E32FF_V_M1, + 6304 => Opcode::PseudoVLSEG3E32FF_V_M1_MASK, + 6305 => Opcode::PseudoVLSEG3E32FF_V_M2, + 6306 => Opcode::PseudoVLSEG3E32FF_V_M2_MASK, + 6307 => Opcode::PseudoVLSEG3E32FF_V_MF2, + 6308 => Opcode::PseudoVLSEG3E32FF_V_MF2_MASK, + 6309 => Opcode::PseudoVLSEG3E32_V_M1, + 6310 => Opcode::PseudoVLSEG3E32_V_M1_MASK, + 6311 => Opcode::PseudoVLSEG3E32_V_M2, + 6312 => Opcode::PseudoVLSEG3E32_V_M2_MASK, + 6313 => Opcode::PseudoVLSEG3E32_V_MF2, + 6314 => Opcode::PseudoVLSEG3E32_V_MF2_MASK, + 6315 => Opcode::PseudoVLSEG3E64FF_V_M1, + 6316 => Opcode::PseudoVLSEG3E64FF_V_M1_MASK, + 6317 => Opcode::PseudoVLSEG3E64FF_V_M2, + 6318 => Opcode::PseudoVLSEG3E64FF_V_M2_MASK, + 6319 => Opcode::PseudoVLSEG3E64_V_M1, + 6320 => Opcode::PseudoVLSEG3E64_V_M1_MASK, + 6321 => Opcode::PseudoVLSEG3E64_V_M2, + 6322 => Opcode::PseudoVLSEG3E64_V_M2_MASK, + 6323 => Opcode::PseudoVLSEG3E8FF_V_M1, + 6324 => Opcode::PseudoVLSEG3E8FF_V_M1_MASK, + 6325 => Opcode::PseudoVLSEG3E8FF_V_M2, + 6326 => Opcode::PseudoVLSEG3E8FF_V_M2_MASK, + 6327 => Opcode::PseudoVLSEG3E8FF_V_MF2, + 6328 => Opcode::PseudoVLSEG3E8FF_V_MF2_MASK, + 6329 => Opcode::PseudoVLSEG3E8FF_V_MF4, + 6330 => Opcode::PseudoVLSEG3E8FF_V_MF4_MASK, + 6331 => Opcode::PseudoVLSEG3E8FF_V_MF8, + 6332 => Opcode::PseudoVLSEG3E8FF_V_MF8_MASK, + 6333 => Opcode::PseudoVLSEG3E8_V_M1, + 6334 => Opcode::PseudoVLSEG3E8_V_M1_MASK, + 6335 => Opcode::PseudoVLSEG3E8_V_M2, + 6336 => Opcode::PseudoVLSEG3E8_V_M2_MASK, + 6337 => Opcode::PseudoVLSEG3E8_V_MF2, + 6338 => Opcode::PseudoVLSEG3E8_V_MF2_MASK, + 6339 => Opcode::PseudoVLSEG3E8_V_MF4, + 6340 => Opcode::PseudoVLSEG3E8_V_MF4_MASK, + 6341 => Opcode::PseudoVLSEG3E8_V_MF8, + 6342 => Opcode::PseudoVLSEG3E8_V_MF8_MASK, + 6343 => Opcode::PseudoVLSEG4E16FF_V_M1, + 6344 => Opcode::PseudoVLSEG4E16FF_V_M1_MASK, + 6345 => Opcode::PseudoVLSEG4E16FF_V_M2, + 6346 => Opcode::PseudoVLSEG4E16FF_V_M2_MASK, + 6347 => Opcode::PseudoVLSEG4E16FF_V_MF2, + 6348 => Opcode::PseudoVLSEG4E16FF_V_MF2_MASK, + 6349 => Opcode::PseudoVLSEG4E16FF_V_MF4, + 6350 => Opcode::PseudoVLSEG4E16FF_V_MF4_MASK, + 6351 => Opcode::PseudoVLSEG4E16_V_M1, + 6352 => Opcode::PseudoVLSEG4E16_V_M1_MASK, + 6353 => Opcode::PseudoVLSEG4E16_V_M2, + 6354 => Opcode::PseudoVLSEG4E16_V_M2_MASK, + 6355 => Opcode::PseudoVLSEG4E16_V_MF2, + 6356 => Opcode::PseudoVLSEG4E16_V_MF2_MASK, + 6357 => Opcode::PseudoVLSEG4E16_V_MF4, + 6358 => Opcode::PseudoVLSEG4E16_V_MF4_MASK, + 6359 => Opcode::PseudoVLSEG4E32FF_V_M1, + 6360 => Opcode::PseudoVLSEG4E32FF_V_M1_MASK, + 6361 => Opcode::PseudoVLSEG4E32FF_V_M2, + 6362 => Opcode::PseudoVLSEG4E32FF_V_M2_MASK, + 6363 => Opcode::PseudoVLSEG4E32FF_V_MF2, + 6364 => Opcode::PseudoVLSEG4E32FF_V_MF2_MASK, + 6365 => Opcode::PseudoVLSEG4E32_V_M1, + 6366 => Opcode::PseudoVLSEG4E32_V_M1_MASK, + 6367 => Opcode::PseudoVLSEG4E32_V_M2, + 6368 => Opcode::PseudoVLSEG4E32_V_M2_MASK, + 6369 => Opcode::PseudoVLSEG4E32_V_MF2, + 6370 => Opcode::PseudoVLSEG4E32_V_MF2_MASK, + 6371 => Opcode::PseudoVLSEG4E64FF_V_M1, + 6372 => Opcode::PseudoVLSEG4E64FF_V_M1_MASK, + 6373 => Opcode::PseudoVLSEG4E64FF_V_M2, + 6374 => Opcode::PseudoVLSEG4E64FF_V_M2_MASK, + 6375 => Opcode::PseudoVLSEG4E64_V_M1, + 6376 => Opcode::PseudoVLSEG4E64_V_M1_MASK, + 6377 => Opcode::PseudoVLSEG4E64_V_M2, + 6378 => Opcode::PseudoVLSEG4E64_V_M2_MASK, + 6379 => Opcode::PseudoVLSEG4E8FF_V_M1, + 6380 => Opcode::PseudoVLSEG4E8FF_V_M1_MASK, + 6381 => Opcode::PseudoVLSEG4E8FF_V_M2, + 6382 => Opcode::PseudoVLSEG4E8FF_V_M2_MASK, + 6383 => Opcode::PseudoVLSEG4E8FF_V_MF2, + 6384 => Opcode::PseudoVLSEG4E8FF_V_MF2_MASK, + 6385 => Opcode::PseudoVLSEG4E8FF_V_MF4, + 6386 => Opcode::PseudoVLSEG4E8FF_V_MF4_MASK, + 6387 => Opcode::PseudoVLSEG4E8FF_V_MF8, + 6388 => Opcode::PseudoVLSEG4E8FF_V_MF8_MASK, + 6389 => Opcode::PseudoVLSEG4E8_V_M1, + 6390 => Opcode::PseudoVLSEG4E8_V_M1_MASK, + 6391 => Opcode::PseudoVLSEG4E8_V_M2, + 6392 => Opcode::PseudoVLSEG4E8_V_M2_MASK, + 6393 => Opcode::PseudoVLSEG4E8_V_MF2, + 6394 => Opcode::PseudoVLSEG4E8_V_MF2_MASK, + 6395 => Opcode::PseudoVLSEG4E8_V_MF4, + 6396 => Opcode::PseudoVLSEG4E8_V_MF4_MASK, + 6397 => Opcode::PseudoVLSEG4E8_V_MF8, + 6398 => Opcode::PseudoVLSEG4E8_V_MF8_MASK, + 6399 => Opcode::PseudoVLSEG5E16FF_V_M1, + 6400 => Opcode::PseudoVLSEG5E16FF_V_M1_MASK, + 6401 => Opcode::PseudoVLSEG5E16FF_V_MF2, + 6402 => Opcode::PseudoVLSEG5E16FF_V_MF2_MASK, + 6403 => Opcode::PseudoVLSEG5E16FF_V_MF4, + 6404 => Opcode::PseudoVLSEG5E16FF_V_MF4_MASK, + 6405 => Opcode::PseudoVLSEG5E16_V_M1, + 6406 => Opcode::PseudoVLSEG5E16_V_M1_MASK, + 6407 => Opcode::PseudoVLSEG5E16_V_MF2, + 6408 => Opcode::PseudoVLSEG5E16_V_MF2_MASK, + 6409 => Opcode::PseudoVLSEG5E16_V_MF4, + 6410 => Opcode::PseudoVLSEG5E16_V_MF4_MASK, + 6411 => Opcode::PseudoVLSEG5E32FF_V_M1, + 6412 => Opcode::PseudoVLSEG5E32FF_V_M1_MASK, + 6413 => Opcode::PseudoVLSEG5E32FF_V_MF2, + 6414 => Opcode::PseudoVLSEG5E32FF_V_MF2_MASK, + 6415 => Opcode::PseudoVLSEG5E32_V_M1, + 6416 => Opcode::PseudoVLSEG5E32_V_M1_MASK, + 6417 => Opcode::PseudoVLSEG5E32_V_MF2, + 6418 => Opcode::PseudoVLSEG5E32_V_MF2_MASK, + 6419 => Opcode::PseudoVLSEG5E64FF_V_M1, + 6420 => Opcode::PseudoVLSEG5E64FF_V_M1_MASK, + 6421 => Opcode::PseudoVLSEG5E64_V_M1, + 6422 => Opcode::PseudoVLSEG5E64_V_M1_MASK, + 6423 => Opcode::PseudoVLSEG5E8FF_V_M1, + 6424 => Opcode::PseudoVLSEG5E8FF_V_M1_MASK, + 6425 => Opcode::PseudoVLSEG5E8FF_V_MF2, + 6426 => Opcode::PseudoVLSEG5E8FF_V_MF2_MASK, + 6427 => Opcode::PseudoVLSEG5E8FF_V_MF4, + 6428 => Opcode::PseudoVLSEG5E8FF_V_MF4_MASK, + 6429 => Opcode::PseudoVLSEG5E8FF_V_MF8, + 6430 => Opcode::PseudoVLSEG5E8FF_V_MF8_MASK, + 6431 => Opcode::PseudoVLSEG5E8_V_M1, + 6432 => Opcode::PseudoVLSEG5E8_V_M1_MASK, + 6433 => Opcode::PseudoVLSEG5E8_V_MF2, + 6434 => Opcode::PseudoVLSEG5E8_V_MF2_MASK, + 6435 => Opcode::PseudoVLSEG5E8_V_MF4, + 6436 => Opcode::PseudoVLSEG5E8_V_MF4_MASK, + 6437 => Opcode::PseudoVLSEG5E8_V_MF8, + 6438 => Opcode::PseudoVLSEG5E8_V_MF8_MASK, + 6439 => Opcode::PseudoVLSEG6E16FF_V_M1, + 6440 => Opcode::PseudoVLSEG6E16FF_V_M1_MASK, + 6441 => Opcode::PseudoVLSEG6E16FF_V_MF2, + 6442 => Opcode::PseudoVLSEG6E16FF_V_MF2_MASK, + 6443 => Opcode::PseudoVLSEG6E16FF_V_MF4, + 6444 => Opcode::PseudoVLSEG6E16FF_V_MF4_MASK, + 6445 => Opcode::PseudoVLSEG6E16_V_M1, + 6446 => Opcode::PseudoVLSEG6E16_V_M1_MASK, + 6447 => Opcode::PseudoVLSEG6E16_V_MF2, + 6448 => Opcode::PseudoVLSEG6E16_V_MF2_MASK, + 6449 => Opcode::PseudoVLSEG6E16_V_MF4, + 6450 => Opcode::PseudoVLSEG6E16_V_MF4_MASK, + 6451 => Opcode::PseudoVLSEG6E32FF_V_M1, + 6452 => Opcode::PseudoVLSEG6E32FF_V_M1_MASK, + 6453 => Opcode::PseudoVLSEG6E32FF_V_MF2, + 6454 => Opcode::PseudoVLSEG6E32FF_V_MF2_MASK, + 6455 => Opcode::PseudoVLSEG6E32_V_M1, + 6456 => Opcode::PseudoVLSEG6E32_V_M1_MASK, + 6457 => Opcode::PseudoVLSEG6E32_V_MF2, + 6458 => Opcode::PseudoVLSEG6E32_V_MF2_MASK, + 6459 => Opcode::PseudoVLSEG6E64FF_V_M1, + 6460 => Opcode::PseudoVLSEG6E64FF_V_M1_MASK, + 6461 => Opcode::PseudoVLSEG6E64_V_M1, + 6462 => Opcode::PseudoVLSEG6E64_V_M1_MASK, + 6463 => Opcode::PseudoVLSEG6E8FF_V_M1, + 6464 => Opcode::PseudoVLSEG6E8FF_V_M1_MASK, + 6465 => Opcode::PseudoVLSEG6E8FF_V_MF2, + 6466 => Opcode::PseudoVLSEG6E8FF_V_MF2_MASK, + 6467 => Opcode::PseudoVLSEG6E8FF_V_MF4, + 6468 => Opcode::PseudoVLSEG6E8FF_V_MF4_MASK, + 6469 => Opcode::PseudoVLSEG6E8FF_V_MF8, + 6470 => Opcode::PseudoVLSEG6E8FF_V_MF8_MASK, + 6471 => Opcode::PseudoVLSEG6E8_V_M1, + 6472 => Opcode::PseudoVLSEG6E8_V_M1_MASK, + 6473 => Opcode::PseudoVLSEG6E8_V_MF2, + 6474 => Opcode::PseudoVLSEG6E8_V_MF2_MASK, + 6475 => Opcode::PseudoVLSEG6E8_V_MF4, + 6476 => Opcode::PseudoVLSEG6E8_V_MF4_MASK, + 6477 => Opcode::PseudoVLSEG6E8_V_MF8, + 6478 => Opcode::PseudoVLSEG6E8_V_MF8_MASK, + 6479 => Opcode::PseudoVLSEG7E16FF_V_M1, + 6480 => Opcode::PseudoVLSEG7E16FF_V_M1_MASK, + 6481 => Opcode::PseudoVLSEG7E16FF_V_MF2, + 6482 => Opcode::PseudoVLSEG7E16FF_V_MF2_MASK, + 6483 => Opcode::PseudoVLSEG7E16FF_V_MF4, + 6484 => Opcode::PseudoVLSEG7E16FF_V_MF4_MASK, + 6485 => Opcode::PseudoVLSEG7E16_V_M1, + 6486 => Opcode::PseudoVLSEG7E16_V_M1_MASK, + 6487 => Opcode::PseudoVLSEG7E16_V_MF2, + 6488 => Opcode::PseudoVLSEG7E16_V_MF2_MASK, + 6489 => Opcode::PseudoVLSEG7E16_V_MF4, + 6490 => Opcode::PseudoVLSEG7E16_V_MF4_MASK, + 6491 => Opcode::PseudoVLSEG7E32FF_V_M1, + 6492 => Opcode::PseudoVLSEG7E32FF_V_M1_MASK, + 6493 => Opcode::PseudoVLSEG7E32FF_V_MF2, + 6494 => Opcode::PseudoVLSEG7E32FF_V_MF2_MASK, + 6495 => Opcode::PseudoVLSEG7E32_V_M1, + 6496 => Opcode::PseudoVLSEG7E32_V_M1_MASK, + 6497 => Opcode::PseudoVLSEG7E32_V_MF2, + 6498 => Opcode::PseudoVLSEG7E32_V_MF2_MASK, + 6499 => Opcode::PseudoVLSEG7E64FF_V_M1, + 6500 => Opcode::PseudoVLSEG7E64FF_V_M1_MASK, + 6501 => Opcode::PseudoVLSEG7E64_V_M1, + 6502 => Opcode::PseudoVLSEG7E64_V_M1_MASK, + 6503 => Opcode::PseudoVLSEG7E8FF_V_M1, + 6504 => Opcode::PseudoVLSEG7E8FF_V_M1_MASK, + 6505 => Opcode::PseudoVLSEG7E8FF_V_MF2, + 6506 => Opcode::PseudoVLSEG7E8FF_V_MF2_MASK, + 6507 => Opcode::PseudoVLSEG7E8FF_V_MF4, + 6508 => Opcode::PseudoVLSEG7E8FF_V_MF4_MASK, + 6509 => Opcode::PseudoVLSEG7E8FF_V_MF8, + 6510 => Opcode::PseudoVLSEG7E8FF_V_MF8_MASK, + 6511 => Opcode::PseudoVLSEG7E8_V_M1, + 6512 => Opcode::PseudoVLSEG7E8_V_M1_MASK, + 6513 => Opcode::PseudoVLSEG7E8_V_MF2, + 6514 => Opcode::PseudoVLSEG7E8_V_MF2_MASK, + 6515 => Opcode::PseudoVLSEG7E8_V_MF4, + 6516 => Opcode::PseudoVLSEG7E8_V_MF4_MASK, + 6517 => Opcode::PseudoVLSEG7E8_V_MF8, + 6518 => Opcode::PseudoVLSEG7E8_V_MF8_MASK, + 6519 => Opcode::PseudoVLSEG8E16FF_V_M1, + 6520 => Opcode::PseudoVLSEG8E16FF_V_M1_MASK, + 6521 => Opcode::PseudoVLSEG8E16FF_V_MF2, + 6522 => Opcode::PseudoVLSEG8E16FF_V_MF2_MASK, + 6523 => Opcode::PseudoVLSEG8E16FF_V_MF4, + 6524 => Opcode::PseudoVLSEG8E16FF_V_MF4_MASK, + 6525 => Opcode::PseudoVLSEG8E16_V_M1, + 6526 => Opcode::PseudoVLSEG8E16_V_M1_MASK, + 6527 => Opcode::PseudoVLSEG8E16_V_MF2, + 6528 => Opcode::PseudoVLSEG8E16_V_MF2_MASK, + 6529 => Opcode::PseudoVLSEG8E16_V_MF4, + 6530 => Opcode::PseudoVLSEG8E16_V_MF4_MASK, + 6531 => Opcode::PseudoVLSEG8E32FF_V_M1, + 6532 => Opcode::PseudoVLSEG8E32FF_V_M1_MASK, + 6533 => Opcode::PseudoVLSEG8E32FF_V_MF2, + 6534 => Opcode::PseudoVLSEG8E32FF_V_MF2_MASK, + 6535 => Opcode::PseudoVLSEG8E32_V_M1, + 6536 => Opcode::PseudoVLSEG8E32_V_M1_MASK, + 6537 => Opcode::PseudoVLSEG8E32_V_MF2, + 6538 => Opcode::PseudoVLSEG8E32_V_MF2_MASK, + 6539 => Opcode::PseudoVLSEG8E64FF_V_M1, + 6540 => Opcode::PseudoVLSEG8E64FF_V_M1_MASK, + 6541 => Opcode::PseudoVLSEG8E64_V_M1, + 6542 => Opcode::PseudoVLSEG8E64_V_M1_MASK, + 6543 => Opcode::PseudoVLSEG8E8FF_V_M1, + 6544 => Opcode::PseudoVLSEG8E8FF_V_M1_MASK, + 6545 => Opcode::PseudoVLSEG8E8FF_V_MF2, + 6546 => Opcode::PseudoVLSEG8E8FF_V_MF2_MASK, + 6547 => Opcode::PseudoVLSEG8E8FF_V_MF4, + 6548 => Opcode::PseudoVLSEG8E8FF_V_MF4_MASK, + 6549 => Opcode::PseudoVLSEG8E8FF_V_MF8, + 6550 => Opcode::PseudoVLSEG8E8FF_V_MF8_MASK, + 6551 => Opcode::PseudoVLSEG8E8_V_M1, + 6552 => Opcode::PseudoVLSEG8E8_V_M1_MASK, + 6553 => Opcode::PseudoVLSEG8E8_V_MF2, + 6554 => Opcode::PseudoVLSEG8E8_V_MF2_MASK, + 6555 => Opcode::PseudoVLSEG8E8_V_MF4, + 6556 => Opcode::PseudoVLSEG8E8_V_MF4_MASK, + 6557 => Opcode::PseudoVLSEG8E8_V_MF8, + 6558 => Opcode::PseudoVLSEG8E8_V_MF8_MASK, + 6559 => Opcode::PseudoVLSSEG2E16_V_M1, + 6560 => Opcode::PseudoVLSSEG2E16_V_M1_MASK, + 6561 => Opcode::PseudoVLSSEG2E16_V_M2, + 6562 => Opcode::PseudoVLSSEG2E16_V_M2_MASK, + 6563 => Opcode::PseudoVLSSEG2E16_V_M4, + 6564 => Opcode::PseudoVLSSEG2E16_V_M4_MASK, + 6565 => Opcode::PseudoVLSSEG2E16_V_MF2, + 6566 => Opcode::PseudoVLSSEG2E16_V_MF2_MASK, + 6567 => Opcode::PseudoVLSSEG2E16_V_MF4, + 6568 => Opcode::PseudoVLSSEG2E16_V_MF4_MASK, + 6569 => Opcode::PseudoVLSSEG2E32_V_M1, + 6570 => Opcode::PseudoVLSSEG2E32_V_M1_MASK, + 6571 => Opcode::PseudoVLSSEG2E32_V_M2, + 6572 => Opcode::PseudoVLSSEG2E32_V_M2_MASK, + 6573 => Opcode::PseudoVLSSEG2E32_V_M4, + 6574 => Opcode::PseudoVLSSEG2E32_V_M4_MASK, + 6575 => Opcode::PseudoVLSSEG2E32_V_MF2, + 6576 => Opcode::PseudoVLSSEG2E32_V_MF2_MASK, + 6577 => Opcode::PseudoVLSSEG2E64_V_M1, + 6578 => Opcode::PseudoVLSSEG2E64_V_M1_MASK, + 6579 => Opcode::PseudoVLSSEG2E64_V_M2, + 6580 => Opcode::PseudoVLSSEG2E64_V_M2_MASK, + 6581 => Opcode::PseudoVLSSEG2E64_V_M4, + 6582 => Opcode::PseudoVLSSEG2E64_V_M4_MASK, + 6583 => Opcode::PseudoVLSSEG2E8_V_M1, + 6584 => Opcode::PseudoVLSSEG2E8_V_M1_MASK, + 6585 => Opcode::PseudoVLSSEG2E8_V_M2, + 6586 => Opcode::PseudoVLSSEG2E8_V_M2_MASK, + 6587 => Opcode::PseudoVLSSEG2E8_V_M4, + 6588 => Opcode::PseudoVLSSEG2E8_V_M4_MASK, + 6589 => Opcode::PseudoVLSSEG2E8_V_MF2, + 6590 => Opcode::PseudoVLSSEG2E8_V_MF2_MASK, + 6591 => Opcode::PseudoVLSSEG2E8_V_MF4, + 6592 => Opcode::PseudoVLSSEG2E8_V_MF4_MASK, + 6593 => Opcode::PseudoVLSSEG2E8_V_MF8, + 6594 => Opcode::PseudoVLSSEG2E8_V_MF8_MASK, + 6595 => Opcode::PseudoVLSSEG3E16_V_M1, + 6596 => Opcode::PseudoVLSSEG3E16_V_M1_MASK, + 6597 => Opcode::PseudoVLSSEG3E16_V_M2, + 6598 => Opcode::PseudoVLSSEG3E16_V_M2_MASK, + 6599 => Opcode::PseudoVLSSEG3E16_V_MF2, + 6600 => Opcode::PseudoVLSSEG3E16_V_MF2_MASK, + 6601 => Opcode::PseudoVLSSEG3E16_V_MF4, + 6602 => Opcode::PseudoVLSSEG3E16_V_MF4_MASK, + 6603 => Opcode::PseudoVLSSEG3E32_V_M1, + 6604 => Opcode::PseudoVLSSEG3E32_V_M1_MASK, + 6605 => Opcode::PseudoVLSSEG3E32_V_M2, + 6606 => Opcode::PseudoVLSSEG3E32_V_M2_MASK, + 6607 => Opcode::PseudoVLSSEG3E32_V_MF2, + 6608 => Opcode::PseudoVLSSEG3E32_V_MF2_MASK, + 6609 => Opcode::PseudoVLSSEG3E64_V_M1, + 6610 => Opcode::PseudoVLSSEG3E64_V_M1_MASK, + 6611 => Opcode::PseudoVLSSEG3E64_V_M2, + 6612 => Opcode::PseudoVLSSEG3E64_V_M2_MASK, + 6613 => Opcode::PseudoVLSSEG3E8_V_M1, + 6614 => Opcode::PseudoVLSSEG3E8_V_M1_MASK, + 6615 => Opcode::PseudoVLSSEG3E8_V_M2, + 6616 => Opcode::PseudoVLSSEG3E8_V_M2_MASK, + 6617 => Opcode::PseudoVLSSEG3E8_V_MF2, + 6618 => Opcode::PseudoVLSSEG3E8_V_MF2_MASK, + 6619 => Opcode::PseudoVLSSEG3E8_V_MF4, + 6620 => Opcode::PseudoVLSSEG3E8_V_MF4_MASK, + 6621 => Opcode::PseudoVLSSEG3E8_V_MF8, + 6622 => Opcode::PseudoVLSSEG3E8_V_MF8_MASK, + 6623 => Opcode::PseudoVLSSEG4E16_V_M1, + 6624 => Opcode::PseudoVLSSEG4E16_V_M1_MASK, + 6625 => Opcode::PseudoVLSSEG4E16_V_M2, + 6626 => Opcode::PseudoVLSSEG4E16_V_M2_MASK, + 6627 => Opcode::PseudoVLSSEG4E16_V_MF2, + 6628 => Opcode::PseudoVLSSEG4E16_V_MF2_MASK, + 6629 => Opcode::PseudoVLSSEG4E16_V_MF4, + 6630 => Opcode::PseudoVLSSEG4E16_V_MF4_MASK, + 6631 => Opcode::PseudoVLSSEG4E32_V_M1, + 6632 => Opcode::PseudoVLSSEG4E32_V_M1_MASK, + 6633 => Opcode::PseudoVLSSEG4E32_V_M2, + 6634 => Opcode::PseudoVLSSEG4E32_V_M2_MASK, + 6635 => Opcode::PseudoVLSSEG4E32_V_MF2, + 6636 => Opcode::PseudoVLSSEG4E32_V_MF2_MASK, + 6637 => Opcode::PseudoVLSSEG4E64_V_M1, + 6638 => Opcode::PseudoVLSSEG4E64_V_M1_MASK, + 6639 => Opcode::PseudoVLSSEG4E64_V_M2, + 6640 => Opcode::PseudoVLSSEG4E64_V_M2_MASK, + 6641 => Opcode::PseudoVLSSEG4E8_V_M1, + 6642 => Opcode::PseudoVLSSEG4E8_V_M1_MASK, + 6643 => Opcode::PseudoVLSSEG4E8_V_M2, + 6644 => Opcode::PseudoVLSSEG4E8_V_M2_MASK, + 6645 => Opcode::PseudoVLSSEG4E8_V_MF2, + 6646 => Opcode::PseudoVLSSEG4E8_V_MF2_MASK, + 6647 => Opcode::PseudoVLSSEG4E8_V_MF4, + 6648 => Opcode::PseudoVLSSEG4E8_V_MF4_MASK, + 6649 => Opcode::PseudoVLSSEG4E8_V_MF8, + 6650 => Opcode::PseudoVLSSEG4E8_V_MF8_MASK, + 6651 => Opcode::PseudoVLSSEG5E16_V_M1, + 6652 => Opcode::PseudoVLSSEG5E16_V_M1_MASK, + 6653 => Opcode::PseudoVLSSEG5E16_V_MF2, + 6654 => Opcode::PseudoVLSSEG5E16_V_MF2_MASK, + 6655 => Opcode::PseudoVLSSEG5E16_V_MF4, + 6656 => Opcode::PseudoVLSSEG5E16_V_MF4_MASK, + 6657 => Opcode::PseudoVLSSEG5E32_V_M1, + 6658 => Opcode::PseudoVLSSEG5E32_V_M1_MASK, + 6659 => Opcode::PseudoVLSSEG5E32_V_MF2, + 6660 => Opcode::PseudoVLSSEG5E32_V_MF2_MASK, + 6661 => Opcode::PseudoVLSSEG5E64_V_M1, + 6662 => Opcode::PseudoVLSSEG5E64_V_M1_MASK, + 6663 => Opcode::PseudoVLSSEG5E8_V_M1, + 6664 => Opcode::PseudoVLSSEG5E8_V_M1_MASK, + 6665 => Opcode::PseudoVLSSEG5E8_V_MF2, + 6666 => Opcode::PseudoVLSSEG5E8_V_MF2_MASK, + 6667 => Opcode::PseudoVLSSEG5E8_V_MF4, + 6668 => Opcode::PseudoVLSSEG5E8_V_MF4_MASK, + 6669 => Opcode::PseudoVLSSEG5E8_V_MF8, + 6670 => Opcode::PseudoVLSSEG5E8_V_MF8_MASK, + 6671 => Opcode::PseudoVLSSEG6E16_V_M1, + 6672 => Opcode::PseudoVLSSEG6E16_V_M1_MASK, + 6673 => Opcode::PseudoVLSSEG6E16_V_MF2, + 6674 => Opcode::PseudoVLSSEG6E16_V_MF2_MASK, + 6675 => Opcode::PseudoVLSSEG6E16_V_MF4, + 6676 => Opcode::PseudoVLSSEG6E16_V_MF4_MASK, + 6677 => Opcode::PseudoVLSSEG6E32_V_M1, + 6678 => Opcode::PseudoVLSSEG6E32_V_M1_MASK, + 6679 => Opcode::PseudoVLSSEG6E32_V_MF2, + 6680 => Opcode::PseudoVLSSEG6E32_V_MF2_MASK, + 6681 => Opcode::PseudoVLSSEG6E64_V_M1, + 6682 => Opcode::PseudoVLSSEG6E64_V_M1_MASK, + 6683 => Opcode::PseudoVLSSEG6E8_V_M1, + 6684 => Opcode::PseudoVLSSEG6E8_V_M1_MASK, + 6685 => Opcode::PseudoVLSSEG6E8_V_MF2, + 6686 => Opcode::PseudoVLSSEG6E8_V_MF2_MASK, + 6687 => Opcode::PseudoVLSSEG6E8_V_MF4, + 6688 => Opcode::PseudoVLSSEG6E8_V_MF4_MASK, + 6689 => Opcode::PseudoVLSSEG6E8_V_MF8, + 6690 => Opcode::PseudoVLSSEG6E8_V_MF8_MASK, + 6691 => Opcode::PseudoVLSSEG7E16_V_M1, + 6692 => Opcode::PseudoVLSSEG7E16_V_M1_MASK, + 6693 => Opcode::PseudoVLSSEG7E16_V_MF2, + 6694 => Opcode::PseudoVLSSEG7E16_V_MF2_MASK, + 6695 => Opcode::PseudoVLSSEG7E16_V_MF4, + 6696 => Opcode::PseudoVLSSEG7E16_V_MF4_MASK, + 6697 => Opcode::PseudoVLSSEG7E32_V_M1, + 6698 => Opcode::PseudoVLSSEG7E32_V_M1_MASK, + 6699 => Opcode::PseudoVLSSEG7E32_V_MF2, + 6700 => Opcode::PseudoVLSSEG7E32_V_MF2_MASK, + 6701 => Opcode::PseudoVLSSEG7E64_V_M1, + 6702 => Opcode::PseudoVLSSEG7E64_V_M1_MASK, + 6703 => Opcode::PseudoVLSSEG7E8_V_M1, + 6704 => Opcode::PseudoVLSSEG7E8_V_M1_MASK, + 6705 => Opcode::PseudoVLSSEG7E8_V_MF2, + 6706 => Opcode::PseudoVLSSEG7E8_V_MF2_MASK, + 6707 => Opcode::PseudoVLSSEG7E8_V_MF4, + 6708 => Opcode::PseudoVLSSEG7E8_V_MF4_MASK, + 6709 => Opcode::PseudoVLSSEG7E8_V_MF8, + 6710 => Opcode::PseudoVLSSEG7E8_V_MF8_MASK, + 6711 => Opcode::PseudoVLSSEG8E16_V_M1, + 6712 => Opcode::PseudoVLSSEG8E16_V_M1_MASK, + 6713 => Opcode::PseudoVLSSEG8E16_V_MF2, + 6714 => Opcode::PseudoVLSSEG8E16_V_MF2_MASK, + 6715 => Opcode::PseudoVLSSEG8E16_V_MF4, + 6716 => Opcode::PseudoVLSSEG8E16_V_MF4_MASK, + 6717 => Opcode::PseudoVLSSEG8E32_V_M1, + 6718 => Opcode::PseudoVLSSEG8E32_V_M1_MASK, + 6719 => Opcode::PseudoVLSSEG8E32_V_MF2, + 6720 => Opcode::PseudoVLSSEG8E32_V_MF2_MASK, + 6721 => Opcode::PseudoVLSSEG8E64_V_M1, + 6722 => Opcode::PseudoVLSSEG8E64_V_M1_MASK, + 6723 => Opcode::PseudoVLSSEG8E8_V_M1, + 6724 => Opcode::PseudoVLSSEG8E8_V_M1_MASK, + 6725 => Opcode::PseudoVLSSEG8E8_V_MF2, + 6726 => Opcode::PseudoVLSSEG8E8_V_MF2_MASK, + 6727 => Opcode::PseudoVLSSEG8E8_V_MF4, + 6728 => Opcode::PseudoVLSSEG8E8_V_MF4_MASK, + 6729 => Opcode::PseudoVLSSEG8E8_V_MF8, + 6730 => Opcode::PseudoVLSSEG8E8_V_MF8_MASK, + 6731 => Opcode::PseudoVLUXEI16_V_M1_M1, + 6732 => Opcode::PseudoVLUXEI16_V_M1_M1_MASK, + 6733 => Opcode::PseudoVLUXEI16_V_M1_M2, + 6734 => Opcode::PseudoVLUXEI16_V_M1_M2_MASK, + 6735 => Opcode::PseudoVLUXEI16_V_M1_M4, + 6736 => Opcode::PseudoVLUXEI16_V_M1_M4_MASK, + 6737 => Opcode::PseudoVLUXEI16_V_M1_MF2, + 6738 => Opcode::PseudoVLUXEI16_V_M1_MF2_MASK, + 6739 => Opcode::PseudoVLUXEI16_V_M2_M1, + 6740 => Opcode::PseudoVLUXEI16_V_M2_M1_MASK, + 6741 => Opcode::PseudoVLUXEI16_V_M2_M2, + 6742 => Opcode::PseudoVLUXEI16_V_M2_M2_MASK, + 6743 => Opcode::PseudoVLUXEI16_V_M2_M4, + 6744 => Opcode::PseudoVLUXEI16_V_M2_M4_MASK, + 6745 => Opcode::PseudoVLUXEI16_V_M2_M8, + 6746 => Opcode::PseudoVLUXEI16_V_M2_M8_MASK, + 6747 => Opcode::PseudoVLUXEI16_V_M4_M2, + 6748 => Opcode::PseudoVLUXEI16_V_M4_M2_MASK, + 6749 => Opcode::PseudoVLUXEI16_V_M4_M4, + 6750 => Opcode::PseudoVLUXEI16_V_M4_M4_MASK, + 6751 => Opcode::PseudoVLUXEI16_V_M4_M8, + 6752 => Opcode::PseudoVLUXEI16_V_M4_M8_MASK, + 6753 => Opcode::PseudoVLUXEI16_V_M8_M4, + 6754 => Opcode::PseudoVLUXEI16_V_M8_M4_MASK, + 6755 => Opcode::PseudoVLUXEI16_V_M8_M8, + 6756 => Opcode::PseudoVLUXEI16_V_M8_M8_MASK, + 6757 => Opcode::PseudoVLUXEI16_V_MF2_M1, + 6758 => Opcode::PseudoVLUXEI16_V_MF2_M1_MASK, + 6759 => Opcode::PseudoVLUXEI16_V_MF2_M2, + 6760 => Opcode::PseudoVLUXEI16_V_MF2_M2_MASK, + 6761 => Opcode::PseudoVLUXEI16_V_MF2_MF2, + 6762 => Opcode::PseudoVLUXEI16_V_MF2_MF2_MASK, + 6763 => Opcode::PseudoVLUXEI16_V_MF2_MF4, + 6764 => Opcode::PseudoVLUXEI16_V_MF2_MF4_MASK, + 6765 => Opcode::PseudoVLUXEI16_V_MF4_M1, + 6766 => Opcode::PseudoVLUXEI16_V_MF4_M1_MASK, + 6767 => Opcode::PseudoVLUXEI16_V_MF4_MF2, + 6768 => Opcode::PseudoVLUXEI16_V_MF4_MF2_MASK, + 6769 => Opcode::PseudoVLUXEI16_V_MF4_MF4, + 6770 => Opcode::PseudoVLUXEI16_V_MF4_MF4_MASK, + 6771 => Opcode::PseudoVLUXEI16_V_MF4_MF8, + 6772 => Opcode::PseudoVLUXEI16_V_MF4_MF8_MASK, + 6773 => Opcode::PseudoVLUXEI32_V_M1_M1, + 6774 => Opcode::PseudoVLUXEI32_V_M1_M1_MASK, + 6775 => Opcode::PseudoVLUXEI32_V_M1_M2, + 6776 => Opcode::PseudoVLUXEI32_V_M1_M2_MASK, + 6777 => Opcode::PseudoVLUXEI32_V_M1_MF2, + 6778 => Opcode::PseudoVLUXEI32_V_M1_MF2_MASK, + 6779 => Opcode::PseudoVLUXEI32_V_M1_MF4, + 6780 => Opcode::PseudoVLUXEI32_V_M1_MF4_MASK, + 6781 => Opcode::PseudoVLUXEI32_V_M2_M1, + 6782 => Opcode::PseudoVLUXEI32_V_M2_M1_MASK, + 6783 => Opcode::PseudoVLUXEI32_V_M2_M2, + 6784 => Opcode::PseudoVLUXEI32_V_M2_M2_MASK, + 6785 => Opcode::PseudoVLUXEI32_V_M2_M4, + 6786 => Opcode::PseudoVLUXEI32_V_M2_M4_MASK, + 6787 => Opcode::PseudoVLUXEI32_V_M2_MF2, + 6788 => Opcode::PseudoVLUXEI32_V_M2_MF2_MASK, + 6789 => Opcode::PseudoVLUXEI32_V_M4_M1, + 6790 => Opcode::PseudoVLUXEI32_V_M4_M1_MASK, + 6791 => Opcode::PseudoVLUXEI32_V_M4_M2, + 6792 => Opcode::PseudoVLUXEI32_V_M4_M2_MASK, + 6793 => Opcode::PseudoVLUXEI32_V_M4_M4, + 6794 => Opcode::PseudoVLUXEI32_V_M4_M4_MASK, + 6795 => Opcode::PseudoVLUXEI32_V_M4_M8, + 6796 => Opcode::PseudoVLUXEI32_V_M4_M8_MASK, + 6797 => Opcode::PseudoVLUXEI32_V_M8_M2, + 6798 => Opcode::PseudoVLUXEI32_V_M8_M2_MASK, + 6799 => Opcode::PseudoVLUXEI32_V_M8_M4, + 6800 => Opcode::PseudoVLUXEI32_V_M8_M4_MASK, + 6801 => Opcode::PseudoVLUXEI32_V_M8_M8, + 6802 => Opcode::PseudoVLUXEI32_V_M8_M8_MASK, + 6803 => Opcode::PseudoVLUXEI32_V_MF2_M1, + 6804 => Opcode::PseudoVLUXEI32_V_MF2_M1_MASK, + 6805 => Opcode::PseudoVLUXEI32_V_MF2_MF2, + 6806 => Opcode::PseudoVLUXEI32_V_MF2_MF2_MASK, + 6807 => Opcode::PseudoVLUXEI32_V_MF2_MF4, + 6808 => Opcode::PseudoVLUXEI32_V_MF2_MF4_MASK, + 6809 => Opcode::PseudoVLUXEI32_V_MF2_MF8, + 6810 => Opcode::PseudoVLUXEI32_V_MF2_MF8_MASK, + 6811 => Opcode::PseudoVLUXEI64_V_M1_M1, + 6812 => Opcode::PseudoVLUXEI64_V_M1_M1_MASK, + 6813 => Opcode::PseudoVLUXEI64_V_M1_MF2, + 6814 => Opcode::PseudoVLUXEI64_V_M1_MF2_MASK, + 6815 => Opcode::PseudoVLUXEI64_V_M1_MF4, + 6816 => Opcode::PseudoVLUXEI64_V_M1_MF4_MASK, + 6817 => Opcode::PseudoVLUXEI64_V_M1_MF8, + 6818 => Opcode::PseudoVLUXEI64_V_M1_MF8_MASK, + 6819 => Opcode::PseudoVLUXEI64_V_M2_M1, + 6820 => Opcode::PseudoVLUXEI64_V_M2_M1_MASK, + 6821 => Opcode::PseudoVLUXEI64_V_M2_M2, + 6822 => Opcode::PseudoVLUXEI64_V_M2_M2_MASK, + 6823 => Opcode::PseudoVLUXEI64_V_M2_MF2, + 6824 => Opcode::PseudoVLUXEI64_V_M2_MF2_MASK, + 6825 => Opcode::PseudoVLUXEI64_V_M2_MF4, + 6826 => Opcode::PseudoVLUXEI64_V_M2_MF4_MASK, + 6827 => Opcode::PseudoVLUXEI64_V_M4_M1, + 6828 => Opcode::PseudoVLUXEI64_V_M4_M1_MASK, + 6829 => Opcode::PseudoVLUXEI64_V_M4_M2, + 6830 => Opcode::PseudoVLUXEI64_V_M4_M2_MASK, + 6831 => Opcode::PseudoVLUXEI64_V_M4_M4, + 6832 => Opcode::PseudoVLUXEI64_V_M4_M4_MASK, + 6833 => Opcode::PseudoVLUXEI64_V_M4_MF2, + 6834 => Opcode::PseudoVLUXEI64_V_M4_MF2_MASK, + 6835 => Opcode::PseudoVLUXEI64_V_M8_M1, + 6836 => Opcode::PseudoVLUXEI64_V_M8_M1_MASK, + 6837 => Opcode::PseudoVLUXEI64_V_M8_M2, + 6838 => Opcode::PseudoVLUXEI64_V_M8_M2_MASK, + 6839 => Opcode::PseudoVLUXEI64_V_M8_M4, + 6840 => Opcode::PseudoVLUXEI64_V_M8_M4_MASK, + 6841 => Opcode::PseudoVLUXEI64_V_M8_M8, + 6842 => Opcode::PseudoVLUXEI64_V_M8_M8_MASK, + 6843 => Opcode::PseudoVLUXEI8_V_M1_M1, + 6844 => Opcode::PseudoVLUXEI8_V_M1_M1_MASK, + 6845 => Opcode::PseudoVLUXEI8_V_M1_M2, + 6846 => Opcode::PseudoVLUXEI8_V_M1_M2_MASK, + 6847 => Opcode::PseudoVLUXEI8_V_M1_M4, + 6848 => Opcode::PseudoVLUXEI8_V_M1_M4_MASK, + 6849 => Opcode::PseudoVLUXEI8_V_M1_M8, + 6850 => Opcode::PseudoVLUXEI8_V_M1_M8_MASK, + 6851 => Opcode::PseudoVLUXEI8_V_M2_M2, + 6852 => Opcode::PseudoVLUXEI8_V_M2_M2_MASK, + 6853 => Opcode::PseudoVLUXEI8_V_M2_M4, + 6854 => Opcode::PseudoVLUXEI8_V_M2_M4_MASK, + 6855 => Opcode::PseudoVLUXEI8_V_M2_M8, + 6856 => Opcode::PseudoVLUXEI8_V_M2_M8_MASK, + 6857 => Opcode::PseudoVLUXEI8_V_M4_M4, + 6858 => Opcode::PseudoVLUXEI8_V_M4_M4_MASK, + 6859 => Opcode::PseudoVLUXEI8_V_M4_M8, + 6860 => Opcode::PseudoVLUXEI8_V_M4_M8_MASK, + 6861 => Opcode::PseudoVLUXEI8_V_M8_M8, + 6862 => Opcode::PseudoVLUXEI8_V_M8_M8_MASK, + 6863 => Opcode::PseudoVLUXEI8_V_MF2_M1, + 6864 => Opcode::PseudoVLUXEI8_V_MF2_M1_MASK, + 6865 => Opcode::PseudoVLUXEI8_V_MF2_M2, + 6866 => Opcode::PseudoVLUXEI8_V_MF2_M2_MASK, + 6867 => Opcode::PseudoVLUXEI8_V_MF2_M4, + 6868 => Opcode::PseudoVLUXEI8_V_MF2_M4_MASK, + 6869 => Opcode::PseudoVLUXEI8_V_MF2_MF2, + 6870 => Opcode::PseudoVLUXEI8_V_MF2_MF2_MASK, + 6871 => Opcode::PseudoVLUXEI8_V_MF4_M1, + 6872 => Opcode::PseudoVLUXEI8_V_MF4_M1_MASK, + 6873 => Opcode::PseudoVLUXEI8_V_MF4_M2, + 6874 => Opcode::PseudoVLUXEI8_V_MF4_M2_MASK, + 6875 => Opcode::PseudoVLUXEI8_V_MF4_MF2, + 6876 => Opcode::PseudoVLUXEI8_V_MF4_MF2_MASK, + 6877 => Opcode::PseudoVLUXEI8_V_MF4_MF4, + 6878 => Opcode::PseudoVLUXEI8_V_MF4_MF4_MASK, + 6879 => Opcode::PseudoVLUXEI8_V_MF8_M1, + 6880 => Opcode::PseudoVLUXEI8_V_MF8_M1_MASK, + 6881 => Opcode::PseudoVLUXEI8_V_MF8_MF2, + 6882 => Opcode::PseudoVLUXEI8_V_MF8_MF2_MASK, + 6883 => Opcode::PseudoVLUXEI8_V_MF8_MF4, + 6884 => Opcode::PseudoVLUXEI8_V_MF8_MF4_MASK, + 6885 => Opcode::PseudoVLUXEI8_V_MF8_MF8, + 6886 => Opcode::PseudoVLUXEI8_V_MF8_MF8_MASK, + 6887 => Opcode::PseudoVLUXSEG2EI16_V_M1_M1, + 6888 => Opcode::PseudoVLUXSEG2EI16_V_M1_M1_MASK, + 6889 => Opcode::PseudoVLUXSEG2EI16_V_M1_M2, + 6890 => Opcode::PseudoVLUXSEG2EI16_V_M1_M2_MASK, + 6891 => Opcode::PseudoVLUXSEG2EI16_V_M1_M4, + 6892 => Opcode::PseudoVLUXSEG2EI16_V_M1_M4_MASK, + 6893 => Opcode::PseudoVLUXSEG2EI16_V_M1_MF2, + 6894 => Opcode::PseudoVLUXSEG2EI16_V_M1_MF2_MASK, + 6895 => Opcode::PseudoVLUXSEG2EI16_V_M2_M1, + 6896 => Opcode::PseudoVLUXSEG2EI16_V_M2_M1_MASK, + 6897 => Opcode::PseudoVLUXSEG2EI16_V_M2_M2, + 6898 => Opcode::PseudoVLUXSEG2EI16_V_M2_M2_MASK, + 6899 => Opcode::PseudoVLUXSEG2EI16_V_M2_M4, + 6900 => Opcode::PseudoVLUXSEG2EI16_V_M2_M4_MASK, + 6901 => Opcode::PseudoVLUXSEG2EI16_V_M4_M2, + 6902 => Opcode::PseudoVLUXSEG2EI16_V_M4_M2_MASK, + 6903 => Opcode::PseudoVLUXSEG2EI16_V_M4_M4, + 6904 => Opcode::PseudoVLUXSEG2EI16_V_M4_M4_MASK, + 6905 => Opcode::PseudoVLUXSEG2EI16_V_M8_M4, + 6906 => Opcode::PseudoVLUXSEG2EI16_V_M8_M4_MASK, + 6907 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M1, + 6908 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M1_MASK, + 6909 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M2, + 6910 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M2_MASK, + 6911 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF2, + 6912 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, + 6913 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF4, + 6914 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, + 6915 => Opcode::PseudoVLUXSEG2EI16_V_MF4_M1, + 6916 => Opcode::PseudoVLUXSEG2EI16_V_MF4_M1_MASK, + 6917 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF2, + 6918 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, + 6919 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF4, + 6920 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, + 6921 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF8, + 6922 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, + 6923 => Opcode::PseudoVLUXSEG2EI32_V_M1_M1, + 6924 => Opcode::PseudoVLUXSEG2EI32_V_M1_M1_MASK, + 6925 => Opcode::PseudoVLUXSEG2EI32_V_M1_M2, + 6926 => Opcode::PseudoVLUXSEG2EI32_V_M1_M2_MASK, + 6927 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF2, + 6928 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF2_MASK, + 6929 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF4, + 6930 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF4_MASK, + 6931 => Opcode::PseudoVLUXSEG2EI32_V_M2_M1, + 6932 => Opcode::PseudoVLUXSEG2EI32_V_M2_M1_MASK, + 6933 => Opcode::PseudoVLUXSEG2EI32_V_M2_M2, + 6934 => Opcode::PseudoVLUXSEG2EI32_V_M2_M2_MASK, + 6935 => Opcode::PseudoVLUXSEG2EI32_V_M2_M4, + 6936 => Opcode::PseudoVLUXSEG2EI32_V_M2_M4_MASK, + 6937 => Opcode::PseudoVLUXSEG2EI32_V_M2_MF2, + 6938 => Opcode::PseudoVLUXSEG2EI32_V_M2_MF2_MASK, + 6939 => Opcode::PseudoVLUXSEG2EI32_V_M4_M1, + 6940 => Opcode::PseudoVLUXSEG2EI32_V_M4_M1_MASK, + 6941 => Opcode::PseudoVLUXSEG2EI32_V_M4_M2, + 6942 => Opcode::PseudoVLUXSEG2EI32_V_M4_M2_MASK, + 6943 => Opcode::PseudoVLUXSEG2EI32_V_M4_M4, + 6944 => Opcode::PseudoVLUXSEG2EI32_V_M4_M4_MASK, + 6945 => Opcode::PseudoVLUXSEG2EI32_V_M8_M2, + 6946 => Opcode::PseudoVLUXSEG2EI32_V_M8_M2_MASK, + 6947 => Opcode::PseudoVLUXSEG2EI32_V_M8_M4, + 6948 => Opcode::PseudoVLUXSEG2EI32_V_M8_M4_MASK, + 6949 => Opcode::PseudoVLUXSEG2EI32_V_MF2_M1, + 6950 => Opcode::PseudoVLUXSEG2EI32_V_MF2_M1_MASK, + 6951 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF2, + 6952 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, + 6953 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF4, + 6954 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, + 6955 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF8, + 6956 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, + 6957 => Opcode::PseudoVLUXSEG2EI64_V_M1_M1, + 6958 => Opcode::PseudoVLUXSEG2EI64_V_M1_M1_MASK, + 6959 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF2, + 6960 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF2_MASK, + 6961 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF4, + 6962 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF4_MASK, + 6963 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF8, + 6964 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF8_MASK, + 6965 => Opcode::PseudoVLUXSEG2EI64_V_M2_M1, + 6966 => Opcode::PseudoVLUXSEG2EI64_V_M2_M1_MASK, + 6967 => Opcode::PseudoVLUXSEG2EI64_V_M2_M2, + 6968 => Opcode::PseudoVLUXSEG2EI64_V_M2_M2_MASK, + 6969 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF2, + 6970 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF2_MASK, + 6971 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF4, + 6972 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF4_MASK, + 6973 => Opcode::PseudoVLUXSEG2EI64_V_M4_M1, + 6974 => Opcode::PseudoVLUXSEG2EI64_V_M4_M1_MASK, + 6975 => Opcode::PseudoVLUXSEG2EI64_V_M4_M2, + 6976 => Opcode::PseudoVLUXSEG2EI64_V_M4_M2_MASK, + 6977 => Opcode::PseudoVLUXSEG2EI64_V_M4_M4, + 6978 => Opcode::PseudoVLUXSEG2EI64_V_M4_M4_MASK, + 6979 => Opcode::PseudoVLUXSEG2EI64_V_M4_MF2, + 6980 => Opcode::PseudoVLUXSEG2EI64_V_M4_MF2_MASK, + 6981 => Opcode::PseudoVLUXSEG2EI64_V_M8_M1, + 6982 => Opcode::PseudoVLUXSEG2EI64_V_M8_M1_MASK, + 6983 => Opcode::PseudoVLUXSEG2EI64_V_M8_M2, + 6984 => Opcode::PseudoVLUXSEG2EI64_V_M8_M2_MASK, + 6985 => Opcode::PseudoVLUXSEG2EI64_V_M8_M4, + 6986 => Opcode::PseudoVLUXSEG2EI64_V_M8_M4_MASK, + 6987 => Opcode::PseudoVLUXSEG2EI8_V_M1_M1, + 6988 => Opcode::PseudoVLUXSEG2EI8_V_M1_M1_MASK, + 6989 => Opcode::PseudoVLUXSEG2EI8_V_M1_M2, + 6990 => Opcode::PseudoVLUXSEG2EI8_V_M1_M2_MASK, + 6991 => Opcode::PseudoVLUXSEG2EI8_V_M1_M4, + 6992 => Opcode::PseudoVLUXSEG2EI8_V_M1_M4_MASK, + 6993 => Opcode::PseudoVLUXSEG2EI8_V_M2_M2, + 6994 => Opcode::PseudoVLUXSEG2EI8_V_M2_M2_MASK, + 6995 => Opcode::PseudoVLUXSEG2EI8_V_M2_M4, + 6996 => Opcode::PseudoVLUXSEG2EI8_V_M2_M4_MASK, + 6997 => Opcode::PseudoVLUXSEG2EI8_V_M4_M4, + 6998 => Opcode::PseudoVLUXSEG2EI8_V_M4_M4_MASK, + 6999 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M1, + 7000 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M1_MASK, + 7001 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M2, + 7002 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M2_MASK, + 7003 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M4, + 7004 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M4_MASK, + 7005 => Opcode::PseudoVLUXSEG2EI8_V_MF2_MF2, + 7006 => Opcode::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, + 7007 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M1, + 7008 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M1_MASK, + 7009 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M2, + 7010 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M2_MASK, + 7011 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF2, + 7012 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, + 7013 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF4, + 7014 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, + 7015 => Opcode::PseudoVLUXSEG2EI8_V_MF8_M1, + 7016 => Opcode::PseudoVLUXSEG2EI8_V_MF8_M1_MASK, + 7017 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF2, + 7018 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, + 7019 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF4, + 7020 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, + 7021 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF8, + 7022 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, + 7023 => Opcode::PseudoVLUXSEG3EI16_V_M1_M1, + 7024 => Opcode::PseudoVLUXSEG3EI16_V_M1_M1_MASK, + 7025 => Opcode::PseudoVLUXSEG3EI16_V_M1_M2, + 7026 => Opcode::PseudoVLUXSEG3EI16_V_M1_M2_MASK, + 7027 => Opcode::PseudoVLUXSEG3EI16_V_M1_MF2, + 7028 => Opcode::PseudoVLUXSEG3EI16_V_M1_MF2_MASK, + 7029 => Opcode::PseudoVLUXSEG3EI16_V_M2_M1, + 7030 => Opcode::PseudoVLUXSEG3EI16_V_M2_M1_MASK, + 7031 => Opcode::PseudoVLUXSEG3EI16_V_M2_M2, + 7032 => Opcode::PseudoVLUXSEG3EI16_V_M2_M2_MASK, + 7033 => Opcode::PseudoVLUXSEG3EI16_V_M4_M2, + 7034 => Opcode::PseudoVLUXSEG3EI16_V_M4_M2_MASK, + 7035 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M1, + 7036 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M1_MASK, + 7037 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M2, + 7038 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M2_MASK, + 7039 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF2, + 7040 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, + 7041 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF4, + 7042 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, + 7043 => Opcode::PseudoVLUXSEG3EI16_V_MF4_M1, + 7044 => Opcode::PseudoVLUXSEG3EI16_V_MF4_M1_MASK, + 7045 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF2, + 7046 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, + 7047 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF4, + 7048 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, + 7049 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF8, + 7050 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, + 7051 => Opcode::PseudoVLUXSEG3EI32_V_M1_M1, + 7052 => Opcode::PseudoVLUXSEG3EI32_V_M1_M1_MASK, + 7053 => Opcode::PseudoVLUXSEG3EI32_V_M1_M2, + 7054 => Opcode::PseudoVLUXSEG3EI32_V_M1_M2_MASK, + 7055 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF2, + 7056 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF2_MASK, + 7057 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF4, + 7058 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF4_MASK, + 7059 => Opcode::PseudoVLUXSEG3EI32_V_M2_M1, + 7060 => Opcode::PseudoVLUXSEG3EI32_V_M2_M1_MASK, + 7061 => Opcode::PseudoVLUXSEG3EI32_V_M2_M2, + 7062 => Opcode::PseudoVLUXSEG3EI32_V_M2_M2_MASK, + 7063 => Opcode::PseudoVLUXSEG3EI32_V_M2_MF2, + 7064 => Opcode::PseudoVLUXSEG3EI32_V_M2_MF2_MASK, + 7065 => Opcode::PseudoVLUXSEG3EI32_V_M4_M1, + 7066 => Opcode::PseudoVLUXSEG3EI32_V_M4_M1_MASK, + 7067 => Opcode::PseudoVLUXSEG3EI32_V_M4_M2, + 7068 => Opcode::PseudoVLUXSEG3EI32_V_M4_M2_MASK, + 7069 => Opcode::PseudoVLUXSEG3EI32_V_M8_M2, + 7070 => Opcode::PseudoVLUXSEG3EI32_V_M8_M2_MASK, + 7071 => Opcode::PseudoVLUXSEG3EI32_V_MF2_M1, + 7072 => Opcode::PseudoVLUXSEG3EI32_V_MF2_M1_MASK, + 7073 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF2, + 7074 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, + 7075 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF4, + 7076 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, + 7077 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF8, + 7078 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, + 7079 => Opcode::PseudoVLUXSEG3EI64_V_M1_M1, + 7080 => Opcode::PseudoVLUXSEG3EI64_V_M1_M1_MASK, + 7081 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF2, + 7082 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF2_MASK, + 7083 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF4, + 7084 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF4_MASK, + 7085 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF8, + 7086 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF8_MASK, + 7087 => Opcode::PseudoVLUXSEG3EI64_V_M2_M1, + 7088 => Opcode::PseudoVLUXSEG3EI64_V_M2_M1_MASK, + 7089 => Opcode::PseudoVLUXSEG3EI64_V_M2_M2, + 7090 => Opcode::PseudoVLUXSEG3EI64_V_M2_M2_MASK, + 7091 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF2, + 7092 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF2_MASK, + 7093 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF4, + 7094 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF4_MASK, + 7095 => Opcode::PseudoVLUXSEG3EI64_V_M4_M1, + 7096 => Opcode::PseudoVLUXSEG3EI64_V_M4_M1_MASK, + 7097 => Opcode::PseudoVLUXSEG3EI64_V_M4_M2, + 7098 => Opcode::PseudoVLUXSEG3EI64_V_M4_M2_MASK, + 7099 => Opcode::PseudoVLUXSEG3EI64_V_M4_MF2, + 7100 => Opcode::PseudoVLUXSEG3EI64_V_M4_MF2_MASK, + 7101 => Opcode::PseudoVLUXSEG3EI64_V_M8_M1, + 7102 => Opcode::PseudoVLUXSEG3EI64_V_M8_M1_MASK, + 7103 => Opcode::PseudoVLUXSEG3EI64_V_M8_M2, + 7104 => Opcode::PseudoVLUXSEG3EI64_V_M8_M2_MASK, + 7105 => Opcode::PseudoVLUXSEG3EI8_V_M1_M1, + 7106 => Opcode::PseudoVLUXSEG3EI8_V_M1_M1_MASK, + 7107 => Opcode::PseudoVLUXSEG3EI8_V_M1_M2, + 7108 => Opcode::PseudoVLUXSEG3EI8_V_M1_M2_MASK, + 7109 => Opcode::PseudoVLUXSEG3EI8_V_M2_M2, + 7110 => Opcode::PseudoVLUXSEG3EI8_V_M2_M2_MASK, + 7111 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M1, + 7112 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M1_MASK, + 7113 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M2, + 7114 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M2_MASK, + 7115 => Opcode::PseudoVLUXSEG3EI8_V_MF2_MF2, + 7116 => Opcode::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, + 7117 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M1, + 7118 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M1_MASK, + 7119 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M2, + 7120 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M2_MASK, + 7121 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF2, + 7122 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, + 7123 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF4, + 7124 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, + 7125 => Opcode::PseudoVLUXSEG3EI8_V_MF8_M1, + 7126 => Opcode::PseudoVLUXSEG3EI8_V_MF8_M1_MASK, + 7127 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF2, + 7128 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, + 7129 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF4, + 7130 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, + 7131 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF8, + 7132 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, + 7133 => Opcode::PseudoVLUXSEG4EI16_V_M1_M1, + 7134 => Opcode::PseudoVLUXSEG4EI16_V_M1_M1_MASK, + 7135 => Opcode::PseudoVLUXSEG4EI16_V_M1_M2, + 7136 => Opcode::PseudoVLUXSEG4EI16_V_M1_M2_MASK, + 7137 => Opcode::PseudoVLUXSEG4EI16_V_M1_MF2, + 7138 => Opcode::PseudoVLUXSEG4EI16_V_M1_MF2_MASK, + 7139 => Opcode::PseudoVLUXSEG4EI16_V_M2_M1, + 7140 => Opcode::PseudoVLUXSEG4EI16_V_M2_M1_MASK, + 7141 => Opcode::PseudoVLUXSEG4EI16_V_M2_M2, + 7142 => Opcode::PseudoVLUXSEG4EI16_V_M2_M2_MASK, + 7143 => Opcode::PseudoVLUXSEG4EI16_V_M4_M2, + 7144 => Opcode::PseudoVLUXSEG4EI16_V_M4_M2_MASK, + 7145 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M1, + 7146 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M1_MASK, + 7147 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M2, + 7148 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M2_MASK, + 7149 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF2, + 7150 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, + 7151 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF4, + 7152 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, + 7153 => Opcode::PseudoVLUXSEG4EI16_V_MF4_M1, + 7154 => Opcode::PseudoVLUXSEG4EI16_V_MF4_M1_MASK, + 7155 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF2, + 7156 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, + 7157 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF4, + 7158 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, + 7159 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF8, + 7160 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, + 7161 => Opcode::PseudoVLUXSEG4EI32_V_M1_M1, + 7162 => Opcode::PseudoVLUXSEG4EI32_V_M1_M1_MASK, + 7163 => Opcode::PseudoVLUXSEG4EI32_V_M1_M2, + 7164 => Opcode::PseudoVLUXSEG4EI32_V_M1_M2_MASK, + 7165 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF2, + 7166 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF2_MASK, + 7167 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF4, + 7168 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF4_MASK, + 7169 => Opcode::PseudoVLUXSEG4EI32_V_M2_M1, + 7170 => Opcode::PseudoVLUXSEG4EI32_V_M2_M1_MASK, + 7171 => Opcode::PseudoVLUXSEG4EI32_V_M2_M2, + 7172 => Opcode::PseudoVLUXSEG4EI32_V_M2_M2_MASK, + 7173 => Opcode::PseudoVLUXSEG4EI32_V_M2_MF2, + 7174 => Opcode::PseudoVLUXSEG4EI32_V_M2_MF2_MASK, + 7175 => Opcode::PseudoVLUXSEG4EI32_V_M4_M1, + 7176 => Opcode::PseudoVLUXSEG4EI32_V_M4_M1_MASK, + 7177 => Opcode::PseudoVLUXSEG4EI32_V_M4_M2, + 7178 => Opcode::PseudoVLUXSEG4EI32_V_M4_M2_MASK, + 7179 => Opcode::PseudoVLUXSEG4EI32_V_M8_M2, + 7180 => Opcode::PseudoVLUXSEG4EI32_V_M8_M2_MASK, + 7181 => Opcode::PseudoVLUXSEG4EI32_V_MF2_M1, + 7182 => Opcode::PseudoVLUXSEG4EI32_V_MF2_M1_MASK, + 7183 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF2, + 7184 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, + 7185 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF4, + 7186 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, + 7187 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF8, + 7188 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, + 7189 => Opcode::PseudoVLUXSEG4EI64_V_M1_M1, + 7190 => Opcode::PseudoVLUXSEG4EI64_V_M1_M1_MASK, + 7191 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF2, + 7192 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF2_MASK, + 7193 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF4, + 7194 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF4_MASK, + 7195 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF8, + 7196 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF8_MASK, + 7197 => Opcode::PseudoVLUXSEG4EI64_V_M2_M1, + 7198 => Opcode::PseudoVLUXSEG4EI64_V_M2_M1_MASK, + 7199 => Opcode::PseudoVLUXSEG4EI64_V_M2_M2, + 7200 => Opcode::PseudoVLUXSEG4EI64_V_M2_M2_MASK, + 7201 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF2, + 7202 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF2_MASK, + 7203 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF4, + 7204 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF4_MASK, + 7205 => Opcode::PseudoVLUXSEG4EI64_V_M4_M1, + 7206 => Opcode::PseudoVLUXSEG4EI64_V_M4_M1_MASK, + 7207 => Opcode::PseudoVLUXSEG4EI64_V_M4_M2, + 7208 => Opcode::PseudoVLUXSEG4EI64_V_M4_M2_MASK, + 7209 => Opcode::PseudoVLUXSEG4EI64_V_M4_MF2, + 7210 => Opcode::PseudoVLUXSEG4EI64_V_M4_MF2_MASK, + 7211 => Opcode::PseudoVLUXSEG4EI64_V_M8_M1, + 7212 => Opcode::PseudoVLUXSEG4EI64_V_M8_M1_MASK, + 7213 => Opcode::PseudoVLUXSEG4EI64_V_M8_M2, + 7214 => Opcode::PseudoVLUXSEG4EI64_V_M8_M2_MASK, + 7215 => Opcode::PseudoVLUXSEG4EI8_V_M1_M1, + 7216 => Opcode::PseudoVLUXSEG4EI8_V_M1_M1_MASK, + 7217 => Opcode::PseudoVLUXSEG4EI8_V_M1_M2, + 7218 => Opcode::PseudoVLUXSEG4EI8_V_M1_M2_MASK, + 7219 => Opcode::PseudoVLUXSEG4EI8_V_M2_M2, + 7220 => Opcode::PseudoVLUXSEG4EI8_V_M2_M2_MASK, + 7221 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M1, + 7222 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M1_MASK, + 7223 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M2, + 7224 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M2_MASK, + 7225 => Opcode::PseudoVLUXSEG4EI8_V_MF2_MF2, + 7226 => Opcode::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, + 7227 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M1, + 7228 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M1_MASK, + 7229 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M2, + 7230 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M2_MASK, + 7231 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF2, + 7232 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, + 7233 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF4, + 7234 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, + 7235 => Opcode::PseudoVLUXSEG4EI8_V_MF8_M1, + 7236 => Opcode::PseudoVLUXSEG4EI8_V_MF8_M1_MASK, + 7237 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF2, + 7238 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, + 7239 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF4, + 7240 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, + 7241 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF8, + 7242 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, + 7243 => Opcode::PseudoVLUXSEG5EI16_V_M1_M1, + 7244 => Opcode::PseudoVLUXSEG5EI16_V_M1_M1_MASK, + 7245 => Opcode::PseudoVLUXSEG5EI16_V_M1_MF2, + 7246 => Opcode::PseudoVLUXSEG5EI16_V_M1_MF2_MASK, + 7247 => Opcode::PseudoVLUXSEG5EI16_V_M2_M1, + 7248 => Opcode::PseudoVLUXSEG5EI16_V_M2_M1_MASK, + 7249 => Opcode::PseudoVLUXSEG5EI16_V_MF2_M1, + 7250 => Opcode::PseudoVLUXSEG5EI16_V_MF2_M1_MASK, + 7251 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF2, + 7252 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, + 7253 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF4, + 7254 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, + 7255 => Opcode::PseudoVLUXSEG5EI16_V_MF4_M1, + 7256 => Opcode::PseudoVLUXSEG5EI16_V_MF4_M1_MASK, + 7257 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF2, + 7258 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, + 7259 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF4, + 7260 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, + 7261 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF8, + 7262 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, + 7263 => Opcode::PseudoVLUXSEG5EI32_V_M1_M1, + 7264 => Opcode::PseudoVLUXSEG5EI32_V_M1_M1_MASK, + 7265 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF2, + 7266 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF2_MASK, + 7267 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF4, + 7268 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF4_MASK, + 7269 => Opcode::PseudoVLUXSEG5EI32_V_M2_M1, + 7270 => Opcode::PseudoVLUXSEG5EI32_V_M2_M1_MASK, + 7271 => Opcode::PseudoVLUXSEG5EI32_V_M2_MF2, + 7272 => Opcode::PseudoVLUXSEG5EI32_V_M2_MF2_MASK, + 7273 => Opcode::PseudoVLUXSEG5EI32_V_M4_M1, + 7274 => Opcode::PseudoVLUXSEG5EI32_V_M4_M1_MASK, + 7275 => Opcode::PseudoVLUXSEG5EI32_V_MF2_M1, + 7276 => Opcode::PseudoVLUXSEG5EI32_V_MF2_M1_MASK, + 7277 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF2, + 7278 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, + 7279 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF4, + 7280 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, + 7281 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF8, + 7282 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, + 7283 => Opcode::PseudoVLUXSEG5EI64_V_M1_M1, + 7284 => Opcode::PseudoVLUXSEG5EI64_V_M1_M1_MASK, + 7285 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF2, + 7286 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF2_MASK, + 7287 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF4, + 7288 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF4_MASK, + 7289 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF8, + 7290 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF8_MASK, + 7291 => Opcode::PseudoVLUXSEG5EI64_V_M2_M1, + 7292 => Opcode::PseudoVLUXSEG5EI64_V_M2_M1_MASK, + 7293 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF2, + 7294 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF2_MASK, + 7295 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF4, + 7296 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF4_MASK, + 7297 => Opcode::PseudoVLUXSEG5EI64_V_M4_M1, + 7298 => Opcode::PseudoVLUXSEG5EI64_V_M4_M1_MASK, + 7299 => Opcode::PseudoVLUXSEG5EI64_V_M4_MF2, + 7300 => Opcode::PseudoVLUXSEG5EI64_V_M4_MF2_MASK, + 7301 => Opcode::PseudoVLUXSEG5EI64_V_M8_M1, + 7302 => Opcode::PseudoVLUXSEG5EI64_V_M8_M1_MASK, + 7303 => Opcode::PseudoVLUXSEG5EI8_V_M1_M1, + 7304 => Opcode::PseudoVLUXSEG5EI8_V_M1_M1_MASK, + 7305 => Opcode::PseudoVLUXSEG5EI8_V_MF2_M1, + 7306 => Opcode::PseudoVLUXSEG5EI8_V_MF2_M1_MASK, + 7307 => Opcode::PseudoVLUXSEG5EI8_V_MF2_MF2, + 7308 => Opcode::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, + 7309 => Opcode::PseudoVLUXSEG5EI8_V_MF4_M1, + 7310 => Opcode::PseudoVLUXSEG5EI8_V_MF4_M1_MASK, + 7311 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF2, + 7312 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, + 7313 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF4, + 7314 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, + 7315 => Opcode::PseudoVLUXSEG5EI8_V_MF8_M1, + 7316 => Opcode::PseudoVLUXSEG5EI8_V_MF8_M1_MASK, + 7317 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF2, + 7318 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, + 7319 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF4, + 7320 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, + 7321 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF8, + 7322 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, + 7323 => Opcode::PseudoVLUXSEG6EI16_V_M1_M1, + 7324 => Opcode::PseudoVLUXSEG6EI16_V_M1_M1_MASK, + 7325 => Opcode::PseudoVLUXSEG6EI16_V_M1_MF2, + 7326 => Opcode::PseudoVLUXSEG6EI16_V_M1_MF2_MASK, + 7327 => Opcode::PseudoVLUXSEG6EI16_V_M2_M1, + 7328 => Opcode::PseudoVLUXSEG6EI16_V_M2_M1_MASK, + 7329 => Opcode::PseudoVLUXSEG6EI16_V_MF2_M1, + 7330 => Opcode::PseudoVLUXSEG6EI16_V_MF2_M1_MASK, + 7331 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF2, + 7332 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, + 7333 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF4, + 7334 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, + 7335 => Opcode::PseudoVLUXSEG6EI16_V_MF4_M1, + 7336 => Opcode::PseudoVLUXSEG6EI16_V_MF4_M1_MASK, + 7337 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF2, + 7338 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, + 7339 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF4, + 7340 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, + 7341 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF8, + 7342 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, + 7343 => Opcode::PseudoVLUXSEG6EI32_V_M1_M1, + 7344 => Opcode::PseudoVLUXSEG6EI32_V_M1_M1_MASK, + 7345 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF2, + 7346 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF2_MASK, + 7347 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF4, + 7348 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF4_MASK, + 7349 => Opcode::PseudoVLUXSEG6EI32_V_M2_M1, + 7350 => Opcode::PseudoVLUXSEG6EI32_V_M2_M1_MASK, + 7351 => Opcode::PseudoVLUXSEG6EI32_V_M2_MF2, + 7352 => Opcode::PseudoVLUXSEG6EI32_V_M2_MF2_MASK, + 7353 => Opcode::PseudoVLUXSEG6EI32_V_M4_M1, + 7354 => Opcode::PseudoVLUXSEG6EI32_V_M4_M1_MASK, + 7355 => Opcode::PseudoVLUXSEG6EI32_V_MF2_M1, + 7356 => Opcode::PseudoVLUXSEG6EI32_V_MF2_M1_MASK, + 7357 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF2, + 7358 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, + 7359 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF4, + 7360 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, + 7361 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF8, + 7362 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, + 7363 => Opcode::PseudoVLUXSEG6EI64_V_M1_M1, + 7364 => Opcode::PseudoVLUXSEG6EI64_V_M1_M1_MASK, + 7365 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF2, + 7366 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF2_MASK, + 7367 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF4, + 7368 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF4_MASK, + 7369 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF8, + 7370 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF8_MASK, + 7371 => Opcode::PseudoVLUXSEG6EI64_V_M2_M1, + 7372 => Opcode::PseudoVLUXSEG6EI64_V_M2_M1_MASK, + 7373 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF2, + 7374 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF2_MASK, + 7375 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF4, + 7376 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF4_MASK, + 7377 => Opcode::PseudoVLUXSEG6EI64_V_M4_M1, + 7378 => Opcode::PseudoVLUXSEG6EI64_V_M4_M1_MASK, + 7379 => Opcode::PseudoVLUXSEG6EI64_V_M4_MF2, + 7380 => Opcode::PseudoVLUXSEG6EI64_V_M4_MF2_MASK, + 7381 => Opcode::PseudoVLUXSEG6EI64_V_M8_M1, + 7382 => Opcode::PseudoVLUXSEG6EI64_V_M8_M1_MASK, + 7383 => Opcode::PseudoVLUXSEG6EI8_V_M1_M1, + 7384 => Opcode::PseudoVLUXSEG6EI8_V_M1_M1_MASK, + 7385 => Opcode::PseudoVLUXSEG6EI8_V_MF2_M1, + 7386 => Opcode::PseudoVLUXSEG6EI8_V_MF2_M1_MASK, + 7387 => Opcode::PseudoVLUXSEG6EI8_V_MF2_MF2, + 7388 => Opcode::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, + 7389 => Opcode::PseudoVLUXSEG6EI8_V_MF4_M1, + 7390 => Opcode::PseudoVLUXSEG6EI8_V_MF4_M1_MASK, + 7391 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF2, + 7392 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, + 7393 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF4, + 7394 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, + 7395 => Opcode::PseudoVLUXSEG6EI8_V_MF8_M1, + 7396 => Opcode::PseudoVLUXSEG6EI8_V_MF8_M1_MASK, + 7397 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF2, + 7398 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, + 7399 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF4, + 7400 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, + 7401 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF8, + 7402 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, + 7403 => Opcode::PseudoVLUXSEG7EI16_V_M1_M1, + 7404 => Opcode::PseudoVLUXSEG7EI16_V_M1_M1_MASK, + 7405 => Opcode::PseudoVLUXSEG7EI16_V_M1_MF2, + 7406 => Opcode::PseudoVLUXSEG7EI16_V_M1_MF2_MASK, + 7407 => Opcode::PseudoVLUXSEG7EI16_V_M2_M1, + 7408 => Opcode::PseudoVLUXSEG7EI16_V_M2_M1_MASK, + 7409 => Opcode::PseudoVLUXSEG7EI16_V_MF2_M1, + 7410 => Opcode::PseudoVLUXSEG7EI16_V_MF2_M1_MASK, + 7411 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF2, + 7412 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, + 7413 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF4, + 7414 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, + 7415 => Opcode::PseudoVLUXSEG7EI16_V_MF4_M1, + 7416 => Opcode::PseudoVLUXSEG7EI16_V_MF4_M1_MASK, + 7417 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF2, + 7418 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, + 7419 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF4, + 7420 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, + 7421 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF8, + 7422 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, + 7423 => Opcode::PseudoVLUXSEG7EI32_V_M1_M1, + 7424 => Opcode::PseudoVLUXSEG7EI32_V_M1_M1_MASK, + 7425 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF2, + 7426 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF2_MASK, + 7427 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF4, + 7428 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF4_MASK, + 7429 => Opcode::PseudoVLUXSEG7EI32_V_M2_M1, + 7430 => Opcode::PseudoVLUXSEG7EI32_V_M2_M1_MASK, + 7431 => Opcode::PseudoVLUXSEG7EI32_V_M2_MF2, + 7432 => Opcode::PseudoVLUXSEG7EI32_V_M2_MF2_MASK, + 7433 => Opcode::PseudoVLUXSEG7EI32_V_M4_M1, + 7434 => Opcode::PseudoVLUXSEG7EI32_V_M4_M1_MASK, + 7435 => Opcode::PseudoVLUXSEG7EI32_V_MF2_M1, + 7436 => Opcode::PseudoVLUXSEG7EI32_V_MF2_M1_MASK, + 7437 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF2, + 7438 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, + 7439 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF4, + 7440 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, + 7441 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF8, + 7442 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, + 7443 => Opcode::PseudoVLUXSEG7EI64_V_M1_M1, + 7444 => Opcode::PseudoVLUXSEG7EI64_V_M1_M1_MASK, + 7445 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF2, + 7446 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF2_MASK, + 7447 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF4, + 7448 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF4_MASK, + 7449 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF8, + 7450 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF8_MASK, + 7451 => Opcode::PseudoVLUXSEG7EI64_V_M2_M1, + 7452 => Opcode::PseudoVLUXSEG7EI64_V_M2_M1_MASK, + 7453 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF2, + 7454 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF2_MASK, + 7455 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF4, + 7456 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF4_MASK, + 7457 => Opcode::PseudoVLUXSEG7EI64_V_M4_M1, + 7458 => Opcode::PseudoVLUXSEG7EI64_V_M4_M1_MASK, + 7459 => Opcode::PseudoVLUXSEG7EI64_V_M4_MF2, + 7460 => Opcode::PseudoVLUXSEG7EI64_V_M4_MF2_MASK, + 7461 => Opcode::PseudoVLUXSEG7EI64_V_M8_M1, + 7462 => Opcode::PseudoVLUXSEG7EI64_V_M8_M1_MASK, + 7463 => Opcode::PseudoVLUXSEG7EI8_V_M1_M1, + 7464 => Opcode::PseudoVLUXSEG7EI8_V_M1_M1_MASK, + 7465 => Opcode::PseudoVLUXSEG7EI8_V_MF2_M1, + 7466 => Opcode::PseudoVLUXSEG7EI8_V_MF2_M1_MASK, + 7467 => Opcode::PseudoVLUXSEG7EI8_V_MF2_MF2, + 7468 => Opcode::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, + 7469 => Opcode::PseudoVLUXSEG7EI8_V_MF4_M1, + 7470 => Opcode::PseudoVLUXSEG7EI8_V_MF4_M1_MASK, + 7471 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF2, + 7472 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, + 7473 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF4, + 7474 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, + 7475 => Opcode::PseudoVLUXSEG7EI8_V_MF8_M1, + 7476 => Opcode::PseudoVLUXSEG7EI8_V_MF8_M1_MASK, + 7477 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF2, + 7478 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, + 7479 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF4, + 7480 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, + 7481 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF8, + 7482 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, + 7483 => Opcode::PseudoVLUXSEG8EI16_V_M1_M1, + 7484 => Opcode::PseudoVLUXSEG8EI16_V_M1_M1_MASK, + 7485 => Opcode::PseudoVLUXSEG8EI16_V_M1_MF2, + 7486 => Opcode::PseudoVLUXSEG8EI16_V_M1_MF2_MASK, + 7487 => Opcode::PseudoVLUXSEG8EI16_V_M2_M1, + 7488 => Opcode::PseudoVLUXSEG8EI16_V_M2_M1_MASK, + 7489 => Opcode::PseudoVLUXSEG8EI16_V_MF2_M1, + 7490 => Opcode::PseudoVLUXSEG8EI16_V_MF2_M1_MASK, + 7491 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF2, + 7492 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, + 7493 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF4, + 7494 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, + 7495 => Opcode::PseudoVLUXSEG8EI16_V_MF4_M1, + 7496 => Opcode::PseudoVLUXSEG8EI16_V_MF4_M1_MASK, + 7497 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF2, + 7498 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, + 7499 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF4, + 7500 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, + 7501 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF8, + 7502 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, + 7503 => Opcode::PseudoVLUXSEG8EI32_V_M1_M1, + 7504 => Opcode::PseudoVLUXSEG8EI32_V_M1_M1_MASK, + 7505 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF2, + 7506 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF2_MASK, + 7507 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF4, + 7508 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF4_MASK, + 7509 => Opcode::PseudoVLUXSEG8EI32_V_M2_M1, + 7510 => Opcode::PseudoVLUXSEG8EI32_V_M2_M1_MASK, + 7511 => Opcode::PseudoVLUXSEG8EI32_V_M2_MF2, + 7512 => Opcode::PseudoVLUXSEG8EI32_V_M2_MF2_MASK, + 7513 => Opcode::PseudoVLUXSEG8EI32_V_M4_M1, + 7514 => Opcode::PseudoVLUXSEG8EI32_V_M4_M1_MASK, + 7515 => Opcode::PseudoVLUXSEG8EI32_V_MF2_M1, + 7516 => Opcode::PseudoVLUXSEG8EI32_V_MF2_M1_MASK, + 7517 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF2, + 7518 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, + 7519 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF4, + 7520 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, + 7521 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF8, + 7522 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, + 7523 => Opcode::PseudoVLUXSEG8EI64_V_M1_M1, + 7524 => Opcode::PseudoVLUXSEG8EI64_V_M1_M1_MASK, + 7525 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF2, + 7526 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF2_MASK, + 7527 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF4, + 7528 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF4_MASK, + 7529 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF8, + 7530 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF8_MASK, + 7531 => Opcode::PseudoVLUXSEG8EI64_V_M2_M1, + 7532 => Opcode::PseudoVLUXSEG8EI64_V_M2_M1_MASK, + 7533 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF2, + 7534 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF2_MASK, + 7535 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF4, + 7536 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF4_MASK, + 7537 => Opcode::PseudoVLUXSEG8EI64_V_M4_M1, + 7538 => Opcode::PseudoVLUXSEG8EI64_V_M4_M1_MASK, + 7539 => Opcode::PseudoVLUXSEG8EI64_V_M4_MF2, + 7540 => Opcode::PseudoVLUXSEG8EI64_V_M4_MF2_MASK, + 7541 => Opcode::PseudoVLUXSEG8EI64_V_M8_M1, + 7542 => Opcode::PseudoVLUXSEG8EI64_V_M8_M1_MASK, + 7543 => Opcode::PseudoVLUXSEG8EI8_V_M1_M1, + 7544 => Opcode::PseudoVLUXSEG8EI8_V_M1_M1_MASK, + 7545 => Opcode::PseudoVLUXSEG8EI8_V_MF2_M1, + 7546 => Opcode::PseudoVLUXSEG8EI8_V_MF2_M1_MASK, + 7547 => Opcode::PseudoVLUXSEG8EI8_V_MF2_MF2, + 7548 => Opcode::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, + 7549 => Opcode::PseudoVLUXSEG8EI8_V_MF4_M1, + 7550 => Opcode::PseudoVLUXSEG8EI8_V_MF4_M1_MASK, + 7551 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF2, + 7552 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, + 7553 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF4, + 7554 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, + 7555 => Opcode::PseudoVLUXSEG8EI8_V_MF8_M1, + 7556 => Opcode::PseudoVLUXSEG8EI8_V_MF8_M1_MASK, + 7557 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF2, + 7558 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, + 7559 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF4, + 7560 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, + 7561 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF8, + 7562 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, + 7563 => Opcode::PseudoVMACC_VV_M1, + 7564 => Opcode::PseudoVMACC_VV_M1_MASK, + 7565 => Opcode::PseudoVMACC_VV_M2, + 7566 => Opcode::PseudoVMACC_VV_M2_MASK, + 7567 => Opcode::PseudoVMACC_VV_M4, + 7568 => Opcode::PseudoVMACC_VV_M4_MASK, + 7569 => Opcode::PseudoVMACC_VV_M8, + 7570 => Opcode::PseudoVMACC_VV_M8_MASK, + 7571 => Opcode::PseudoVMACC_VV_MF2, + 7572 => Opcode::PseudoVMACC_VV_MF2_MASK, + 7573 => Opcode::PseudoVMACC_VV_MF4, + 7574 => Opcode::PseudoVMACC_VV_MF4_MASK, + 7575 => Opcode::PseudoVMACC_VV_MF8, + 7576 => Opcode::PseudoVMACC_VV_MF8_MASK, + 7577 => Opcode::PseudoVMACC_VX_M1, + 7578 => Opcode::PseudoVMACC_VX_M1_MASK, + 7579 => Opcode::PseudoVMACC_VX_M2, + 7580 => Opcode::PseudoVMACC_VX_M2_MASK, + 7581 => Opcode::PseudoVMACC_VX_M4, + 7582 => Opcode::PseudoVMACC_VX_M4_MASK, + 7583 => Opcode::PseudoVMACC_VX_M8, + 7584 => Opcode::PseudoVMACC_VX_M8_MASK, + 7585 => Opcode::PseudoVMACC_VX_MF2, + 7586 => Opcode::PseudoVMACC_VX_MF2_MASK, + 7587 => Opcode::PseudoVMACC_VX_MF4, + 7588 => Opcode::PseudoVMACC_VX_MF4_MASK, + 7589 => Opcode::PseudoVMACC_VX_MF8, + 7590 => Opcode::PseudoVMACC_VX_MF8_MASK, + 7591 => Opcode::PseudoVMADC_VIM_M1, + 7592 => Opcode::PseudoVMADC_VIM_M2, + 7593 => Opcode::PseudoVMADC_VIM_M4, + 7594 => Opcode::PseudoVMADC_VIM_M8, + 7595 => Opcode::PseudoVMADC_VIM_MF2, + 7596 => Opcode::PseudoVMADC_VIM_MF4, + 7597 => Opcode::PseudoVMADC_VIM_MF8, + 7598 => Opcode::PseudoVMADC_VI_M1, + 7599 => Opcode::PseudoVMADC_VI_M2, + 7600 => Opcode::PseudoVMADC_VI_M4, + 7601 => Opcode::PseudoVMADC_VI_M8, + 7602 => Opcode::PseudoVMADC_VI_MF2, + 7603 => Opcode::PseudoVMADC_VI_MF4, + 7604 => Opcode::PseudoVMADC_VI_MF8, + 7605 => Opcode::PseudoVMADC_VVM_M1, + 7606 => Opcode::PseudoVMADC_VVM_M2, + 7607 => Opcode::PseudoVMADC_VVM_M4, + 7608 => Opcode::PseudoVMADC_VVM_M8, + 7609 => Opcode::PseudoVMADC_VVM_MF2, + 7610 => Opcode::PseudoVMADC_VVM_MF4, + 7611 => Opcode::PseudoVMADC_VVM_MF8, + 7612 => Opcode::PseudoVMADC_VV_M1, + 7613 => Opcode::PseudoVMADC_VV_M2, + 7614 => Opcode::PseudoVMADC_VV_M4, + 7615 => Opcode::PseudoVMADC_VV_M8, + 7616 => Opcode::PseudoVMADC_VV_MF2, + 7617 => Opcode::PseudoVMADC_VV_MF4, + 7618 => Opcode::PseudoVMADC_VV_MF8, + 7619 => Opcode::PseudoVMADC_VXM_M1, + 7620 => Opcode::PseudoVMADC_VXM_M2, + 7621 => Opcode::PseudoVMADC_VXM_M4, + 7622 => Opcode::PseudoVMADC_VXM_M8, + 7623 => Opcode::PseudoVMADC_VXM_MF2, + 7624 => Opcode::PseudoVMADC_VXM_MF4, + 7625 => Opcode::PseudoVMADC_VXM_MF8, + 7626 => Opcode::PseudoVMADC_VX_M1, + 7627 => Opcode::PseudoVMADC_VX_M2, + 7628 => Opcode::PseudoVMADC_VX_M4, + 7629 => Opcode::PseudoVMADC_VX_M8, + 7630 => Opcode::PseudoVMADC_VX_MF2, + 7631 => Opcode::PseudoVMADC_VX_MF4, + 7632 => Opcode::PseudoVMADC_VX_MF8, + 7633 => Opcode::PseudoVMADD_VV_M1, + 7634 => Opcode::PseudoVMADD_VV_M1_MASK, + 7635 => Opcode::PseudoVMADD_VV_M2, + 7636 => Opcode::PseudoVMADD_VV_M2_MASK, + 7637 => Opcode::PseudoVMADD_VV_M4, + 7638 => Opcode::PseudoVMADD_VV_M4_MASK, + 7639 => Opcode::PseudoVMADD_VV_M8, + 7640 => Opcode::PseudoVMADD_VV_M8_MASK, + 7641 => Opcode::PseudoVMADD_VV_MF2, + 7642 => Opcode::PseudoVMADD_VV_MF2_MASK, + 7643 => Opcode::PseudoVMADD_VV_MF4, + 7644 => Opcode::PseudoVMADD_VV_MF4_MASK, + 7645 => Opcode::PseudoVMADD_VV_MF8, + 7646 => Opcode::PseudoVMADD_VV_MF8_MASK, + 7647 => Opcode::PseudoVMADD_VX_M1, + 7648 => Opcode::PseudoVMADD_VX_M1_MASK, + 7649 => Opcode::PseudoVMADD_VX_M2, + 7650 => Opcode::PseudoVMADD_VX_M2_MASK, + 7651 => Opcode::PseudoVMADD_VX_M4, + 7652 => Opcode::PseudoVMADD_VX_M4_MASK, + 7653 => Opcode::PseudoVMADD_VX_M8, + 7654 => Opcode::PseudoVMADD_VX_M8_MASK, + 7655 => Opcode::PseudoVMADD_VX_MF2, + 7656 => Opcode::PseudoVMADD_VX_MF2_MASK, + 7657 => Opcode::PseudoVMADD_VX_MF4, + 7658 => Opcode::PseudoVMADD_VX_MF4_MASK, + 7659 => Opcode::PseudoVMADD_VX_MF8, + 7660 => Opcode::PseudoVMADD_VX_MF8_MASK, + 7661 => Opcode::PseudoVMANDN_MM_B1, + 7662 => Opcode::PseudoVMANDN_MM_B16, + 7663 => Opcode::PseudoVMANDN_MM_B2, + 7664 => Opcode::PseudoVMANDN_MM_B32, + 7665 => Opcode::PseudoVMANDN_MM_B4, + 7666 => Opcode::PseudoVMANDN_MM_B64, + 7667 => Opcode::PseudoVMANDN_MM_B8, + 7668 => Opcode::PseudoVMAND_MM_B1, + 7669 => Opcode::PseudoVMAND_MM_B16, + 7670 => Opcode::PseudoVMAND_MM_B2, + 7671 => Opcode::PseudoVMAND_MM_B32, + 7672 => Opcode::PseudoVMAND_MM_B4, + 7673 => Opcode::PseudoVMAND_MM_B64, + 7674 => Opcode::PseudoVMAND_MM_B8, + 7675 => Opcode::PseudoVMAXU_VV_M1, + 7676 => Opcode::PseudoVMAXU_VV_M1_MASK, + 7677 => Opcode::PseudoVMAXU_VV_M2, + 7678 => Opcode::PseudoVMAXU_VV_M2_MASK, + 7679 => Opcode::PseudoVMAXU_VV_M4, + 7680 => Opcode::PseudoVMAXU_VV_M4_MASK, + 7681 => Opcode::PseudoVMAXU_VV_M8, + 7682 => Opcode::PseudoVMAXU_VV_M8_MASK, + 7683 => Opcode::PseudoVMAXU_VV_MF2, + 7684 => Opcode::PseudoVMAXU_VV_MF2_MASK, + 7685 => Opcode::PseudoVMAXU_VV_MF4, + 7686 => Opcode::PseudoVMAXU_VV_MF4_MASK, + 7687 => Opcode::PseudoVMAXU_VV_MF8, + 7688 => Opcode::PseudoVMAXU_VV_MF8_MASK, + 7689 => Opcode::PseudoVMAXU_VX_M1, + 7690 => Opcode::PseudoVMAXU_VX_M1_MASK, + 7691 => Opcode::PseudoVMAXU_VX_M2, + 7692 => Opcode::PseudoVMAXU_VX_M2_MASK, + 7693 => Opcode::PseudoVMAXU_VX_M4, + 7694 => Opcode::PseudoVMAXU_VX_M4_MASK, + 7695 => Opcode::PseudoVMAXU_VX_M8, + 7696 => Opcode::PseudoVMAXU_VX_M8_MASK, + 7697 => Opcode::PseudoVMAXU_VX_MF2, + 7698 => Opcode::PseudoVMAXU_VX_MF2_MASK, + 7699 => Opcode::PseudoVMAXU_VX_MF4, + 7700 => Opcode::PseudoVMAXU_VX_MF4_MASK, + 7701 => Opcode::PseudoVMAXU_VX_MF8, + 7702 => Opcode::PseudoVMAXU_VX_MF8_MASK, + 7703 => Opcode::PseudoVMAX_VV_M1, + 7704 => Opcode::PseudoVMAX_VV_M1_MASK, + 7705 => Opcode::PseudoVMAX_VV_M2, + 7706 => Opcode::PseudoVMAX_VV_M2_MASK, + 7707 => Opcode::PseudoVMAX_VV_M4, + 7708 => Opcode::PseudoVMAX_VV_M4_MASK, + 7709 => Opcode::PseudoVMAX_VV_M8, + 7710 => Opcode::PseudoVMAX_VV_M8_MASK, + 7711 => Opcode::PseudoVMAX_VV_MF2, + 7712 => Opcode::PseudoVMAX_VV_MF2_MASK, + 7713 => Opcode::PseudoVMAX_VV_MF4, + 7714 => Opcode::PseudoVMAX_VV_MF4_MASK, + 7715 => Opcode::PseudoVMAX_VV_MF8, + 7716 => Opcode::PseudoVMAX_VV_MF8_MASK, + 7717 => Opcode::PseudoVMAX_VX_M1, + 7718 => Opcode::PseudoVMAX_VX_M1_MASK, + 7719 => Opcode::PseudoVMAX_VX_M2, + 7720 => Opcode::PseudoVMAX_VX_M2_MASK, + 7721 => Opcode::PseudoVMAX_VX_M4, + 7722 => Opcode::PseudoVMAX_VX_M4_MASK, + 7723 => Opcode::PseudoVMAX_VX_M8, + 7724 => Opcode::PseudoVMAX_VX_M8_MASK, + 7725 => Opcode::PseudoVMAX_VX_MF2, + 7726 => Opcode::PseudoVMAX_VX_MF2_MASK, + 7727 => Opcode::PseudoVMAX_VX_MF4, + 7728 => Opcode::PseudoVMAX_VX_MF4_MASK, + 7729 => Opcode::PseudoVMAX_VX_MF8, + 7730 => Opcode::PseudoVMAX_VX_MF8_MASK, + 7731 => Opcode::PseudoVMCLR_M_B1, + 7732 => Opcode::PseudoVMCLR_M_B16, + 7733 => Opcode::PseudoVMCLR_M_B2, + 7734 => Opcode::PseudoVMCLR_M_B32, + 7735 => Opcode::PseudoVMCLR_M_B4, + 7736 => Opcode::PseudoVMCLR_M_B64, + 7737 => Opcode::PseudoVMCLR_M_B8, + 7738 => Opcode::PseudoVMERGE_VIM_M1, + 7739 => Opcode::PseudoVMERGE_VIM_M2, + 7740 => Opcode::PseudoVMERGE_VIM_M4, + 7741 => Opcode::PseudoVMERGE_VIM_M8, + 7742 => Opcode::PseudoVMERGE_VIM_MF2, + 7743 => Opcode::PseudoVMERGE_VIM_MF4, + 7744 => Opcode::PseudoVMERGE_VIM_MF8, + 7745 => Opcode::PseudoVMERGE_VVM_M1, + 7746 => Opcode::PseudoVMERGE_VVM_M2, + 7747 => Opcode::PseudoVMERGE_VVM_M4, + 7748 => Opcode::PseudoVMERGE_VVM_M8, + 7749 => Opcode::PseudoVMERGE_VVM_MF2, + 7750 => Opcode::PseudoVMERGE_VVM_MF4, + 7751 => Opcode::PseudoVMERGE_VVM_MF8, + 7752 => Opcode::PseudoVMERGE_VXM_M1, + 7753 => Opcode::PseudoVMERGE_VXM_M2, + 7754 => Opcode::PseudoVMERGE_VXM_M4, + 7755 => Opcode::PseudoVMERGE_VXM_M8, + 7756 => Opcode::PseudoVMERGE_VXM_MF2, + 7757 => Opcode::PseudoVMERGE_VXM_MF4, + 7758 => Opcode::PseudoVMERGE_VXM_MF8, + 7759 => Opcode::PseudoVMFEQ_ALT_VFPR16_M1, + 7760 => Opcode::PseudoVMFEQ_ALT_VFPR16_M1_MASK, + 7761 => Opcode::PseudoVMFEQ_ALT_VFPR16_M2, + 7762 => Opcode::PseudoVMFEQ_ALT_VFPR16_M2_MASK, + 7763 => Opcode::PseudoVMFEQ_ALT_VFPR16_M4, + 7764 => Opcode::PseudoVMFEQ_ALT_VFPR16_M4_MASK, + 7765 => Opcode::PseudoVMFEQ_ALT_VFPR16_M8, + 7766 => Opcode::PseudoVMFEQ_ALT_VFPR16_M8_MASK, + 7767 => Opcode::PseudoVMFEQ_ALT_VFPR16_MF2, + 7768 => Opcode::PseudoVMFEQ_ALT_VFPR16_MF2_MASK, + 7769 => Opcode::PseudoVMFEQ_ALT_VFPR16_MF4, + 7770 => Opcode::PseudoVMFEQ_ALT_VFPR16_MF4_MASK, + 7771 => Opcode::PseudoVMFEQ_ALT_VFPR32_M1, + 7772 => Opcode::PseudoVMFEQ_ALT_VFPR32_M1_MASK, + 7773 => Opcode::PseudoVMFEQ_ALT_VFPR32_M2, + 7774 => Opcode::PseudoVMFEQ_ALT_VFPR32_M2_MASK, + 7775 => Opcode::PseudoVMFEQ_ALT_VFPR32_M4, + 7776 => Opcode::PseudoVMFEQ_ALT_VFPR32_M4_MASK, + 7777 => Opcode::PseudoVMFEQ_ALT_VFPR32_M8, + 7778 => Opcode::PseudoVMFEQ_ALT_VFPR32_M8_MASK, + 7779 => Opcode::PseudoVMFEQ_ALT_VFPR32_MF2, + 7780 => Opcode::PseudoVMFEQ_ALT_VFPR32_MF2_MASK, + 7781 => Opcode::PseudoVMFEQ_ALT_VFPR64_M1, + 7782 => Opcode::PseudoVMFEQ_ALT_VFPR64_M1_MASK, + 7783 => Opcode::PseudoVMFEQ_ALT_VFPR64_M2, + 7784 => Opcode::PseudoVMFEQ_ALT_VFPR64_M2_MASK, + 7785 => Opcode::PseudoVMFEQ_ALT_VFPR64_M4, + 7786 => Opcode::PseudoVMFEQ_ALT_VFPR64_M4_MASK, + 7787 => Opcode::PseudoVMFEQ_ALT_VFPR64_M8, + 7788 => Opcode::PseudoVMFEQ_ALT_VFPR64_M8_MASK, + 7789 => Opcode::PseudoVMFEQ_ALT_VV_M1, + 7790 => Opcode::PseudoVMFEQ_ALT_VV_M1_MASK, + 7791 => Opcode::PseudoVMFEQ_ALT_VV_M2, + 7792 => Opcode::PseudoVMFEQ_ALT_VV_M2_MASK, + 7793 => Opcode::PseudoVMFEQ_ALT_VV_M4, + 7794 => Opcode::PseudoVMFEQ_ALT_VV_M4_MASK, + 7795 => Opcode::PseudoVMFEQ_ALT_VV_M8, + 7796 => Opcode::PseudoVMFEQ_ALT_VV_M8_MASK, + 7797 => Opcode::PseudoVMFEQ_ALT_VV_MF2, + 7798 => Opcode::PseudoVMFEQ_ALT_VV_MF2_MASK, + 7799 => Opcode::PseudoVMFEQ_ALT_VV_MF4, + 7800 => Opcode::PseudoVMFEQ_ALT_VV_MF4_MASK, + 7801 => Opcode::PseudoVMFEQ_VFPR16_M1, + 7802 => Opcode::PseudoVMFEQ_VFPR16_M1_MASK, + 7803 => Opcode::PseudoVMFEQ_VFPR16_M2, + 7804 => Opcode::PseudoVMFEQ_VFPR16_M2_MASK, + 7805 => Opcode::PseudoVMFEQ_VFPR16_M4, + 7806 => Opcode::PseudoVMFEQ_VFPR16_M4_MASK, + 7807 => Opcode::PseudoVMFEQ_VFPR16_M8, + 7808 => Opcode::PseudoVMFEQ_VFPR16_M8_MASK, + 7809 => Opcode::PseudoVMFEQ_VFPR16_MF2, + 7810 => Opcode::PseudoVMFEQ_VFPR16_MF2_MASK, + 7811 => Opcode::PseudoVMFEQ_VFPR16_MF4, + 7812 => Opcode::PseudoVMFEQ_VFPR16_MF4_MASK, + 7813 => Opcode::PseudoVMFEQ_VFPR32_M1, + 7814 => Opcode::PseudoVMFEQ_VFPR32_M1_MASK, + 7815 => Opcode::PseudoVMFEQ_VFPR32_M2, + 7816 => Opcode::PseudoVMFEQ_VFPR32_M2_MASK, + 7817 => Opcode::PseudoVMFEQ_VFPR32_M4, + 7818 => Opcode::PseudoVMFEQ_VFPR32_M4_MASK, + 7819 => Opcode::PseudoVMFEQ_VFPR32_M8, + 7820 => Opcode::PseudoVMFEQ_VFPR32_M8_MASK, + 7821 => Opcode::PseudoVMFEQ_VFPR32_MF2, + 7822 => Opcode::PseudoVMFEQ_VFPR32_MF2_MASK, + 7823 => Opcode::PseudoVMFEQ_VFPR64_M1, + 7824 => Opcode::PseudoVMFEQ_VFPR64_M1_MASK, + 7825 => Opcode::PseudoVMFEQ_VFPR64_M2, + 7826 => Opcode::PseudoVMFEQ_VFPR64_M2_MASK, + 7827 => Opcode::PseudoVMFEQ_VFPR64_M4, + 7828 => Opcode::PseudoVMFEQ_VFPR64_M4_MASK, + 7829 => Opcode::PseudoVMFEQ_VFPR64_M8, + 7830 => Opcode::PseudoVMFEQ_VFPR64_M8_MASK, + 7831 => Opcode::PseudoVMFEQ_VV_M1, + 7832 => Opcode::PseudoVMFEQ_VV_M1_MASK, + 7833 => Opcode::PseudoVMFEQ_VV_M2, + 7834 => Opcode::PseudoVMFEQ_VV_M2_MASK, + 7835 => Opcode::PseudoVMFEQ_VV_M4, + 7836 => Opcode::PseudoVMFEQ_VV_M4_MASK, + 7837 => Opcode::PseudoVMFEQ_VV_M8, + 7838 => Opcode::PseudoVMFEQ_VV_M8_MASK, + 7839 => Opcode::PseudoVMFEQ_VV_MF2, + 7840 => Opcode::PseudoVMFEQ_VV_MF2_MASK, + 7841 => Opcode::PseudoVMFEQ_VV_MF4, + 7842 => Opcode::PseudoVMFEQ_VV_MF4_MASK, + 7843 => Opcode::PseudoVMFGE_ALT_VFPR16_M1, + 7844 => Opcode::PseudoVMFGE_ALT_VFPR16_M1_MASK, + 7845 => Opcode::PseudoVMFGE_ALT_VFPR16_M2, + 7846 => Opcode::PseudoVMFGE_ALT_VFPR16_M2_MASK, + 7847 => Opcode::PseudoVMFGE_ALT_VFPR16_M4, + 7848 => Opcode::PseudoVMFGE_ALT_VFPR16_M4_MASK, + 7849 => Opcode::PseudoVMFGE_ALT_VFPR16_M8, + 7850 => Opcode::PseudoVMFGE_ALT_VFPR16_M8_MASK, + 7851 => Opcode::PseudoVMFGE_ALT_VFPR16_MF2, + 7852 => Opcode::PseudoVMFGE_ALT_VFPR16_MF2_MASK, + 7853 => Opcode::PseudoVMFGE_ALT_VFPR16_MF4, + 7854 => Opcode::PseudoVMFGE_ALT_VFPR16_MF4_MASK, + 7855 => Opcode::PseudoVMFGE_ALT_VFPR32_M1, + 7856 => Opcode::PseudoVMFGE_ALT_VFPR32_M1_MASK, + 7857 => Opcode::PseudoVMFGE_ALT_VFPR32_M2, + 7858 => Opcode::PseudoVMFGE_ALT_VFPR32_M2_MASK, + 7859 => Opcode::PseudoVMFGE_ALT_VFPR32_M4, + 7860 => Opcode::PseudoVMFGE_ALT_VFPR32_M4_MASK, + 7861 => Opcode::PseudoVMFGE_ALT_VFPR32_M8, + 7862 => Opcode::PseudoVMFGE_ALT_VFPR32_M8_MASK, + 7863 => Opcode::PseudoVMFGE_ALT_VFPR32_MF2, + 7864 => Opcode::PseudoVMFGE_ALT_VFPR32_MF2_MASK, + 7865 => Opcode::PseudoVMFGE_ALT_VFPR64_M1, + 7866 => Opcode::PseudoVMFGE_ALT_VFPR64_M1_MASK, + 7867 => Opcode::PseudoVMFGE_ALT_VFPR64_M2, + 7868 => Opcode::PseudoVMFGE_ALT_VFPR64_M2_MASK, + 7869 => Opcode::PseudoVMFGE_ALT_VFPR64_M4, + 7870 => Opcode::PseudoVMFGE_ALT_VFPR64_M4_MASK, + 7871 => Opcode::PseudoVMFGE_ALT_VFPR64_M8, + 7872 => Opcode::PseudoVMFGE_ALT_VFPR64_M8_MASK, + 7873 => Opcode::PseudoVMFGE_VFPR16_M1, + 7874 => Opcode::PseudoVMFGE_VFPR16_M1_MASK, + 7875 => Opcode::PseudoVMFGE_VFPR16_M2, + 7876 => Opcode::PseudoVMFGE_VFPR16_M2_MASK, + 7877 => Opcode::PseudoVMFGE_VFPR16_M4, + 7878 => Opcode::PseudoVMFGE_VFPR16_M4_MASK, + 7879 => Opcode::PseudoVMFGE_VFPR16_M8, + 7880 => Opcode::PseudoVMFGE_VFPR16_M8_MASK, + 7881 => Opcode::PseudoVMFGE_VFPR16_MF2, + 7882 => Opcode::PseudoVMFGE_VFPR16_MF2_MASK, + 7883 => Opcode::PseudoVMFGE_VFPR16_MF4, + 7884 => Opcode::PseudoVMFGE_VFPR16_MF4_MASK, + 7885 => Opcode::PseudoVMFGE_VFPR32_M1, + 7886 => Opcode::PseudoVMFGE_VFPR32_M1_MASK, + 7887 => Opcode::PseudoVMFGE_VFPR32_M2, + 7888 => Opcode::PseudoVMFGE_VFPR32_M2_MASK, + 7889 => Opcode::PseudoVMFGE_VFPR32_M4, + 7890 => Opcode::PseudoVMFGE_VFPR32_M4_MASK, + 7891 => Opcode::PseudoVMFGE_VFPR32_M8, + 7892 => Opcode::PseudoVMFGE_VFPR32_M8_MASK, + 7893 => Opcode::PseudoVMFGE_VFPR32_MF2, + 7894 => Opcode::PseudoVMFGE_VFPR32_MF2_MASK, + 7895 => Opcode::PseudoVMFGE_VFPR64_M1, + 7896 => Opcode::PseudoVMFGE_VFPR64_M1_MASK, + 7897 => Opcode::PseudoVMFGE_VFPR64_M2, + 7898 => Opcode::PseudoVMFGE_VFPR64_M2_MASK, + 7899 => Opcode::PseudoVMFGE_VFPR64_M4, + 7900 => Opcode::PseudoVMFGE_VFPR64_M4_MASK, + 7901 => Opcode::PseudoVMFGE_VFPR64_M8, + 7902 => Opcode::PseudoVMFGE_VFPR64_M8_MASK, + 7903 => Opcode::PseudoVMFGT_ALT_VFPR16_M1, + 7904 => Opcode::PseudoVMFGT_ALT_VFPR16_M1_MASK, + 7905 => Opcode::PseudoVMFGT_ALT_VFPR16_M2, + 7906 => Opcode::PseudoVMFGT_ALT_VFPR16_M2_MASK, + 7907 => Opcode::PseudoVMFGT_ALT_VFPR16_M4, + 7908 => Opcode::PseudoVMFGT_ALT_VFPR16_M4_MASK, + 7909 => Opcode::PseudoVMFGT_ALT_VFPR16_M8, + 7910 => Opcode::PseudoVMFGT_ALT_VFPR16_M8_MASK, + 7911 => Opcode::PseudoVMFGT_ALT_VFPR16_MF2, + 7912 => Opcode::PseudoVMFGT_ALT_VFPR16_MF2_MASK, + 7913 => Opcode::PseudoVMFGT_ALT_VFPR16_MF4, + 7914 => Opcode::PseudoVMFGT_ALT_VFPR16_MF4_MASK, + 7915 => Opcode::PseudoVMFGT_ALT_VFPR32_M1, + 7916 => Opcode::PseudoVMFGT_ALT_VFPR32_M1_MASK, + 7917 => Opcode::PseudoVMFGT_ALT_VFPR32_M2, + 7918 => Opcode::PseudoVMFGT_ALT_VFPR32_M2_MASK, + 7919 => Opcode::PseudoVMFGT_ALT_VFPR32_M4, + 7920 => Opcode::PseudoVMFGT_ALT_VFPR32_M4_MASK, + 7921 => Opcode::PseudoVMFGT_ALT_VFPR32_M8, + 7922 => Opcode::PseudoVMFGT_ALT_VFPR32_M8_MASK, + 7923 => Opcode::PseudoVMFGT_ALT_VFPR32_MF2, + 7924 => Opcode::PseudoVMFGT_ALT_VFPR32_MF2_MASK, + 7925 => Opcode::PseudoVMFGT_ALT_VFPR64_M1, + 7926 => Opcode::PseudoVMFGT_ALT_VFPR64_M1_MASK, + 7927 => Opcode::PseudoVMFGT_ALT_VFPR64_M2, + 7928 => Opcode::PseudoVMFGT_ALT_VFPR64_M2_MASK, + 7929 => Opcode::PseudoVMFGT_ALT_VFPR64_M4, + 7930 => Opcode::PseudoVMFGT_ALT_VFPR64_M4_MASK, + 7931 => Opcode::PseudoVMFGT_ALT_VFPR64_M8, + 7932 => Opcode::PseudoVMFGT_ALT_VFPR64_M8_MASK, + 7933 => Opcode::PseudoVMFGT_VFPR16_M1, + 7934 => Opcode::PseudoVMFGT_VFPR16_M1_MASK, + 7935 => Opcode::PseudoVMFGT_VFPR16_M2, + 7936 => Opcode::PseudoVMFGT_VFPR16_M2_MASK, + 7937 => Opcode::PseudoVMFGT_VFPR16_M4, + 7938 => Opcode::PseudoVMFGT_VFPR16_M4_MASK, + 7939 => Opcode::PseudoVMFGT_VFPR16_M8, + 7940 => Opcode::PseudoVMFGT_VFPR16_M8_MASK, + 7941 => Opcode::PseudoVMFGT_VFPR16_MF2, + 7942 => Opcode::PseudoVMFGT_VFPR16_MF2_MASK, + 7943 => Opcode::PseudoVMFGT_VFPR16_MF4, + 7944 => Opcode::PseudoVMFGT_VFPR16_MF4_MASK, + 7945 => Opcode::PseudoVMFGT_VFPR32_M1, + 7946 => Opcode::PseudoVMFGT_VFPR32_M1_MASK, + 7947 => Opcode::PseudoVMFGT_VFPR32_M2, + 7948 => Opcode::PseudoVMFGT_VFPR32_M2_MASK, + 7949 => Opcode::PseudoVMFGT_VFPR32_M4, + 7950 => Opcode::PseudoVMFGT_VFPR32_M4_MASK, + 7951 => Opcode::PseudoVMFGT_VFPR32_M8, + 7952 => Opcode::PseudoVMFGT_VFPR32_M8_MASK, + 7953 => Opcode::PseudoVMFGT_VFPR32_MF2, + 7954 => Opcode::PseudoVMFGT_VFPR32_MF2_MASK, + 7955 => Opcode::PseudoVMFGT_VFPR64_M1, + 7956 => Opcode::PseudoVMFGT_VFPR64_M1_MASK, + 7957 => Opcode::PseudoVMFGT_VFPR64_M2, + 7958 => Opcode::PseudoVMFGT_VFPR64_M2_MASK, + 7959 => Opcode::PseudoVMFGT_VFPR64_M4, + 7960 => Opcode::PseudoVMFGT_VFPR64_M4_MASK, + 7961 => Opcode::PseudoVMFGT_VFPR64_M8, + 7962 => Opcode::PseudoVMFGT_VFPR64_M8_MASK, + 7963 => Opcode::PseudoVMFLE_ALT_VFPR16_M1, + 7964 => Opcode::PseudoVMFLE_ALT_VFPR16_M1_MASK, + 7965 => Opcode::PseudoVMFLE_ALT_VFPR16_M2, + 7966 => Opcode::PseudoVMFLE_ALT_VFPR16_M2_MASK, + 7967 => Opcode::PseudoVMFLE_ALT_VFPR16_M4, + 7968 => Opcode::PseudoVMFLE_ALT_VFPR16_M4_MASK, + 7969 => Opcode::PseudoVMFLE_ALT_VFPR16_M8, + 7970 => Opcode::PseudoVMFLE_ALT_VFPR16_M8_MASK, + 7971 => Opcode::PseudoVMFLE_ALT_VFPR16_MF2, + 7972 => Opcode::PseudoVMFLE_ALT_VFPR16_MF2_MASK, + 7973 => Opcode::PseudoVMFLE_ALT_VFPR16_MF4, + 7974 => Opcode::PseudoVMFLE_ALT_VFPR16_MF4_MASK, + 7975 => Opcode::PseudoVMFLE_ALT_VFPR32_M1, + 7976 => Opcode::PseudoVMFLE_ALT_VFPR32_M1_MASK, + 7977 => Opcode::PseudoVMFLE_ALT_VFPR32_M2, + 7978 => Opcode::PseudoVMFLE_ALT_VFPR32_M2_MASK, + 7979 => Opcode::PseudoVMFLE_ALT_VFPR32_M4, + 7980 => Opcode::PseudoVMFLE_ALT_VFPR32_M4_MASK, + 7981 => Opcode::PseudoVMFLE_ALT_VFPR32_M8, + 7982 => Opcode::PseudoVMFLE_ALT_VFPR32_M8_MASK, + 7983 => Opcode::PseudoVMFLE_ALT_VFPR32_MF2, + 7984 => Opcode::PseudoVMFLE_ALT_VFPR32_MF2_MASK, + 7985 => Opcode::PseudoVMFLE_ALT_VFPR64_M1, + 7986 => Opcode::PseudoVMFLE_ALT_VFPR64_M1_MASK, + 7987 => Opcode::PseudoVMFLE_ALT_VFPR64_M2, + 7988 => Opcode::PseudoVMFLE_ALT_VFPR64_M2_MASK, + 7989 => Opcode::PseudoVMFLE_ALT_VFPR64_M4, + 7990 => Opcode::PseudoVMFLE_ALT_VFPR64_M4_MASK, + 7991 => Opcode::PseudoVMFLE_ALT_VFPR64_M8, + 7992 => Opcode::PseudoVMFLE_ALT_VFPR64_M8_MASK, + 7993 => Opcode::PseudoVMFLE_ALT_VV_M1, + 7994 => Opcode::PseudoVMFLE_ALT_VV_M1_MASK, + 7995 => Opcode::PseudoVMFLE_ALT_VV_M2, + 7996 => Opcode::PseudoVMFLE_ALT_VV_M2_MASK, + 7997 => Opcode::PseudoVMFLE_ALT_VV_M4, + 7998 => Opcode::PseudoVMFLE_ALT_VV_M4_MASK, + 7999 => Opcode::PseudoVMFLE_ALT_VV_M8, + 8000 => Opcode::PseudoVMFLE_ALT_VV_M8_MASK, + 8001 => Opcode::PseudoVMFLE_ALT_VV_MF2, + 8002 => Opcode::PseudoVMFLE_ALT_VV_MF2_MASK, + 8003 => Opcode::PseudoVMFLE_ALT_VV_MF4, + 8004 => Opcode::PseudoVMFLE_ALT_VV_MF4_MASK, + 8005 => Opcode::PseudoVMFLE_VFPR16_M1, + 8006 => Opcode::PseudoVMFLE_VFPR16_M1_MASK, + 8007 => Opcode::PseudoVMFLE_VFPR16_M2, + 8008 => Opcode::PseudoVMFLE_VFPR16_M2_MASK, + 8009 => Opcode::PseudoVMFLE_VFPR16_M4, + 8010 => Opcode::PseudoVMFLE_VFPR16_M4_MASK, + 8011 => Opcode::PseudoVMFLE_VFPR16_M8, + 8012 => Opcode::PseudoVMFLE_VFPR16_M8_MASK, + 8013 => Opcode::PseudoVMFLE_VFPR16_MF2, + 8014 => Opcode::PseudoVMFLE_VFPR16_MF2_MASK, + 8015 => Opcode::PseudoVMFLE_VFPR16_MF4, + 8016 => Opcode::PseudoVMFLE_VFPR16_MF4_MASK, + 8017 => Opcode::PseudoVMFLE_VFPR32_M1, + 8018 => Opcode::PseudoVMFLE_VFPR32_M1_MASK, + 8019 => Opcode::PseudoVMFLE_VFPR32_M2, + 8020 => Opcode::PseudoVMFLE_VFPR32_M2_MASK, + 8021 => Opcode::PseudoVMFLE_VFPR32_M4, + 8022 => Opcode::PseudoVMFLE_VFPR32_M4_MASK, + 8023 => Opcode::PseudoVMFLE_VFPR32_M8, + 8024 => Opcode::PseudoVMFLE_VFPR32_M8_MASK, + 8025 => Opcode::PseudoVMFLE_VFPR32_MF2, + 8026 => Opcode::PseudoVMFLE_VFPR32_MF2_MASK, + 8027 => Opcode::PseudoVMFLE_VFPR64_M1, + 8028 => Opcode::PseudoVMFLE_VFPR64_M1_MASK, + 8029 => Opcode::PseudoVMFLE_VFPR64_M2, + 8030 => Opcode::PseudoVMFLE_VFPR64_M2_MASK, + 8031 => Opcode::PseudoVMFLE_VFPR64_M4, + 8032 => Opcode::PseudoVMFLE_VFPR64_M4_MASK, + 8033 => Opcode::PseudoVMFLE_VFPR64_M8, + 8034 => Opcode::PseudoVMFLE_VFPR64_M8_MASK, + 8035 => Opcode::PseudoVMFLE_VV_M1, + 8036 => Opcode::PseudoVMFLE_VV_M1_MASK, + 8037 => Opcode::PseudoVMFLE_VV_M2, + 8038 => Opcode::PseudoVMFLE_VV_M2_MASK, + 8039 => Opcode::PseudoVMFLE_VV_M4, + 8040 => Opcode::PseudoVMFLE_VV_M4_MASK, + 8041 => Opcode::PseudoVMFLE_VV_M8, + 8042 => Opcode::PseudoVMFLE_VV_M8_MASK, + 8043 => Opcode::PseudoVMFLE_VV_MF2, + 8044 => Opcode::PseudoVMFLE_VV_MF2_MASK, + 8045 => Opcode::PseudoVMFLE_VV_MF4, + 8046 => Opcode::PseudoVMFLE_VV_MF4_MASK, + 8047 => Opcode::PseudoVMFLT_ALT_VFPR16_M1, + 8048 => Opcode::PseudoVMFLT_ALT_VFPR16_M1_MASK, + 8049 => Opcode::PseudoVMFLT_ALT_VFPR16_M2, + 8050 => Opcode::PseudoVMFLT_ALT_VFPR16_M2_MASK, + 8051 => Opcode::PseudoVMFLT_ALT_VFPR16_M4, + 8052 => Opcode::PseudoVMFLT_ALT_VFPR16_M4_MASK, + 8053 => Opcode::PseudoVMFLT_ALT_VFPR16_M8, + 8054 => Opcode::PseudoVMFLT_ALT_VFPR16_M8_MASK, + 8055 => Opcode::PseudoVMFLT_ALT_VFPR16_MF2, + 8056 => Opcode::PseudoVMFLT_ALT_VFPR16_MF2_MASK, + 8057 => Opcode::PseudoVMFLT_ALT_VFPR16_MF4, + 8058 => Opcode::PseudoVMFLT_ALT_VFPR16_MF4_MASK, + 8059 => Opcode::PseudoVMFLT_ALT_VFPR32_M1, + 8060 => Opcode::PseudoVMFLT_ALT_VFPR32_M1_MASK, + 8061 => Opcode::PseudoVMFLT_ALT_VFPR32_M2, + 8062 => Opcode::PseudoVMFLT_ALT_VFPR32_M2_MASK, + 8063 => Opcode::PseudoVMFLT_ALT_VFPR32_M4, + 8064 => Opcode::PseudoVMFLT_ALT_VFPR32_M4_MASK, + 8065 => Opcode::PseudoVMFLT_ALT_VFPR32_M8, + 8066 => Opcode::PseudoVMFLT_ALT_VFPR32_M8_MASK, + 8067 => Opcode::PseudoVMFLT_ALT_VFPR32_MF2, + 8068 => Opcode::PseudoVMFLT_ALT_VFPR32_MF2_MASK, + 8069 => Opcode::PseudoVMFLT_ALT_VFPR64_M1, + 8070 => Opcode::PseudoVMFLT_ALT_VFPR64_M1_MASK, + 8071 => Opcode::PseudoVMFLT_ALT_VFPR64_M2, + 8072 => Opcode::PseudoVMFLT_ALT_VFPR64_M2_MASK, + 8073 => Opcode::PseudoVMFLT_ALT_VFPR64_M4, + 8074 => Opcode::PseudoVMFLT_ALT_VFPR64_M4_MASK, + 8075 => Opcode::PseudoVMFLT_ALT_VFPR64_M8, + 8076 => Opcode::PseudoVMFLT_ALT_VFPR64_M8_MASK, + 8077 => Opcode::PseudoVMFLT_ALT_VV_M1, + 8078 => Opcode::PseudoVMFLT_ALT_VV_M1_MASK, + 8079 => Opcode::PseudoVMFLT_ALT_VV_M2, + 8080 => Opcode::PseudoVMFLT_ALT_VV_M2_MASK, + 8081 => Opcode::PseudoVMFLT_ALT_VV_M4, + 8082 => Opcode::PseudoVMFLT_ALT_VV_M4_MASK, + 8083 => Opcode::PseudoVMFLT_ALT_VV_M8, + 8084 => Opcode::PseudoVMFLT_ALT_VV_M8_MASK, + 8085 => Opcode::PseudoVMFLT_ALT_VV_MF2, + 8086 => Opcode::PseudoVMFLT_ALT_VV_MF2_MASK, + 8087 => Opcode::PseudoVMFLT_ALT_VV_MF4, + 8088 => Opcode::PseudoVMFLT_ALT_VV_MF4_MASK, + 8089 => Opcode::PseudoVMFLT_VFPR16_M1, + 8090 => Opcode::PseudoVMFLT_VFPR16_M1_MASK, + 8091 => Opcode::PseudoVMFLT_VFPR16_M2, + 8092 => Opcode::PseudoVMFLT_VFPR16_M2_MASK, + 8093 => Opcode::PseudoVMFLT_VFPR16_M4, + 8094 => Opcode::PseudoVMFLT_VFPR16_M4_MASK, + 8095 => Opcode::PseudoVMFLT_VFPR16_M8, + 8096 => Opcode::PseudoVMFLT_VFPR16_M8_MASK, + 8097 => Opcode::PseudoVMFLT_VFPR16_MF2, + 8098 => Opcode::PseudoVMFLT_VFPR16_MF2_MASK, + 8099 => Opcode::PseudoVMFLT_VFPR16_MF4, + 8100 => Opcode::PseudoVMFLT_VFPR16_MF4_MASK, + 8101 => Opcode::PseudoVMFLT_VFPR32_M1, + 8102 => Opcode::PseudoVMFLT_VFPR32_M1_MASK, + 8103 => Opcode::PseudoVMFLT_VFPR32_M2, + 8104 => Opcode::PseudoVMFLT_VFPR32_M2_MASK, + 8105 => Opcode::PseudoVMFLT_VFPR32_M4, + 8106 => Opcode::PseudoVMFLT_VFPR32_M4_MASK, + 8107 => Opcode::PseudoVMFLT_VFPR32_M8, + 8108 => Opcode::PseudoVMFLT_VFPR32_M8_MASK, + 8109 => Opcode::PseudoVMFLT_VFPR32_MF2, + 8110 => Opcode::PseudoVMFLT_VFPR32_MF2_MASK, + 8111 => Opcode::PseudoVMFLT_VFPR64_M1, + 8112 => Opcode::PseudoVMFLT_VFPR64_M1_MASK, + 8113 => Opcode::PseudoVMFLT_VFPR64_M2, + 8114 => Opcode::PseudoVMFLT_VFPR64_M2_MASK, + 8115 => Opcode::PseudoVMFLT_VFPR64_M4, + 8116 => Opcode::PseudoVMFLT_VFPR64_M4_MASK, + 8117 => Opcode::PseudoVMFLT_VFPR64_M8, + 8118 => Opcode::PseudoVMFLT_VFPR64_M8_MASK, + 8119 => Opcode::PseudoVMFLT_VV_M1, + 8120 => Opcode::PseudoVMFLT_VV_M1_MASK, + 8121 => Opcode::PseudoVMFLT_VV_M2, + 8122 => Opcode::PseudoVMFLT_VV_M2_MASK, + 8123 => Opcode::PseudoVMFLT_VV_M4, + 8124 => Opcode::PseudoVMFLT_VV_M4_MASK, + 8125 => Opcode::PseudoVMFLT_VV_M8, + 8126 => Opcode::PseudoVMFLT_VV_M8_MASK, + 8127 => Opcode::PseudoVMFLT_VV_MF2, + 8128 => Opcode::PseudoVMFLT_VV_MF2_MASK, + 8129 => Opcode::PseudoVMFLT_VV_MF4, + 8130 => Opcode::PseudoVMFLT_VV_MF4_MASK, + 8131 => Opcode::PseudoVMFNE_ALT_VFPR16_M1, + 8132 => Opcode::PseudoVMFNE_ALT_VFPR16_M1_MASK, + 8133 => Opcode::PseudoVMFNE_ALT_VFPR16_M2, + 8134 => Opcode::PseudoVMFNE_ALT_VFPR16_M2_MASK, + 8135 => Opcode::PseudoVMFNE_ALT_VFPR16_M4, + 8136 => Opcode::PseudoVMFNE_ALT_VFPR16_M4_MASK, + 8137 => Opcode::PseudoVMFNE_ALT_VFPR16_M8, + 8138 => Opcode::PseudoVMFNE_ALT_VFPR16_M8_MASK, + 8139 => Opcode::PseudoVMFNE_ALT_VFPR16_MF2, + 8140 => Opcode::PseudoVMFNE_ALT_VFPR16_MF2_MASK, + 8141 => Opcode::PseudoVMFNE_ALT_VFPR16_MF4, + 8142 => Opcode::PseudoVMFNE_ALT_VFPR16_MF4_MASK, + 8143 => Opcode::PseudoVMFNE_ALT_VFPR32_M1, + 8144 => Opcode::PseudoVMFNE_ALT_VFPR32_M1_MASK, + 8145 => Opcode::PseudoVMFNE_ALT_VFPR32_M2, + 8146 => Opcode::PseudoVMFNE_ALT_VFPR32_M2_MASK, + 8147 => Opcode::PseudoVMFNE_ALT_VFPR32_M4, + 8148 => Opcode::PseudoVMFNE_ALT_VFPR32_M4_MASK, + 8149 => Opcode::PseudoVMFNE_ALT_VFPR32_M8, + 8150 => Opcode::PseudoVMFNE_ALT_VFPR32_M8_MASK, + 8151 => Opcode::PseudoVMFNE_ALT_VFPR32_MF2, + 8152 => Opcode::PseudoVMFNE_ALT_VFPR32_MF2_MASK, + 8153 => Opcode::PseudoVMFNE_ALT_VFPR64_M1, + 8154 => Opcode::PseudoVMFNE_ALT_VFPR64_M1_MASK, + 8155 => Opcode::PseudoVMFNE_ALT_VFPR64_M2, + 8156 => Opcode::PseudoVMFNE_ALT_VFPR64_M2_MASK, + 8157 => Opcode::PseudoVMFNE_ALT_VFPR64_M4, + 8158 => Opcode::PseudoVMFNE_ALT_VFPR64_M4_MASK, + 8159 => Opcode::PseudoVMFNE_ALT_VFPR64_M8, + 8160 => Opcode::PseudoVMFNE_ALT_VFPR64_M8_MASK, + 8161 => Opcode::PseudoVMFNE_ALT_VV_M1, + 8162 => Opcode::PseudoVMFNE_ALT_VV_M1_MASK, + 8163 => Opcode::PseudoVMFNE_ALT_VV_M2, + 8164 => Opcode::PseudoVMFNE_ALT_VV_M2_MASK, + 8165 => Opcode::PseudoVMFNE_ALT_VV_M4, + 8166 => Opcode::PseudoVMFNE_ALT_VV_M4_MASK, + 8167 => Opcode::PseudoVMFNE_ALT_VV_M8, + 8168 => Opcode::PseudoVMFNE_ALT_VV_M8_MASK, + 8169 => Opcode::PseudoVMFNE_ALT_VV_MF2, + 8170 => Opcode::PseudoVMFNE_ALT_VV_MF2_MASK, + 8171 => Opcode::PseudoVMFNE_ALT_VV_MF4, + 8172 => Opcode::PseudoVMFNE_ALT_VV_MF4_MASK, + 8173 => Opcode::PseudoVMFNE_VFPR16_M1, + 8174 => Opcode::PseudoVMFNE_VFPR16_M1_MASK, + 8175 => Opcode::PseudoVMFNE_VFPR16_M2, + 8176 => Opcode::PseudoVMFNE_VFPR16_M2_MASK, + 8177 => Opcode::PseudoVMFNE_VFPR16_M4, + 8178 => Opcode::PseudoVMFNE_VFPR16_M4_MASK, + 8179 => Opcode::PseudoVMFNE_VFPR16_M8, + 8180 => Opcode::PseudoVMFNE_VFPR16_M8_MASK, + 8181 => Opcode::PseudoVMFNE_VFPR16_MF2, + 8182 => Opcode::PseudoVMFNE_VFPR16_MF2_MASK, + 8183 => Opcode::PseudoVMFNE_VFPR16_MF4, + 8184 => Opcode::PseudoVMFNE_VFPR16_MF4_MASK, + 8185 => Opcode::PseudoVMFNE_VFPR32_M1, + 8186 => Opcode::PseudoVMFNE_VFPR32_M1_MASK, + 8187 => Opcode::PseudoVMFNE_VFPR32_M2, + 8188 => Opcode::PseudoVMFNE_VFPR32_M2_MASK, + 8189 => Opcode::PseudoVMFNE_VFPR32_M4, + 8190 => Opcode::PseudoVMFNE_VFPR32_M4_MASK, + 8191 => Opcode::PseudoVMFNE_VFPR32_M8, + 8192 => Opcode::PseudoVMFNE_VFPR32_M8_MASK, + 8193 => Opcode::PseudoVMFNE_VFPR32_MF2, + 8194 => Opcode::PseudoVMFNE_VFPR32_MF2_MASK, + 8195 => Opcode::PseudoVMFNE_VFPR64_M1, + 8196 => Opcode::PseudoVMFNE_VFPR64_M1_MASK, + 8197 => Opcode::PseudoVMFNE_VFPR64_M2, + 8198 => Opcode::PseudoVMFNE_VFPR64_M2_MASK, + 8199 => Opcode::PseudoVMFNE_VFPR64_M4, + 8200 => Opcode::PseudoVMFNE_VFPR64_M4_MASK, + 8201 => Opcode::PseudoVMFNE_VFPR64_M8, + 8202 => Opcode::PseudoVMFNE_VFPR64_M8_MASK, + 8203 => Opcode::PseudoVMFNE_VV_M1, + 8204 => Opcode::PseudoVMFNE_VV_M1_MASK, + 8205 => Opcode::PseudoVMFNE_VV_M2, + 8206 => Opcode::PseudoVMFNE_VV_M2_MASK, + 8207 => Opcode::PseudoVMFNE_VV_M4, + 8208 => Opcode::PseudoVMFNE_VV_M4_MASK, + 8209 => Opcode::PseudoVMFNE_VV_M8, + 8210 => Opcode::PseudoVMFNE_VV_M8_MASK, + 8211 => Opcode::PseudoVMFNE_VV_MF2, + 8212 => Opcode::PseudoVMFNE_VV_MF2_MASK, + 8213 => Opcode::PseudoVMFNE_VV_MF4, + 8214 => Opcode::PseudoVMFNE_VV_MF4_MASK, + 8215 => Opcode::PseudoVMINU_VV_M1, + 8216 => Opcode::PseudoVMINU_VV_M1_MASK, + 8217 => Opcode::PseudoVMINU_VV_M2, + 8218 => Opcode::PseudoVMINU_VV_M2_MASK, + 8219 => Opcode::PseudoVMINU_VV_M4, + 8220 => Opcode::PseudoVMINU_VV_M4_MASK, + 8221 => Opcode::PseudoVMINU_VV_M8, + 8222 => Opcode::PseudoVMINU_VV_M8_MASK, + 8223 => Opcode::PseudoVMINU_VV_MF2, + 8224 => Opcode::PseudoVMINU_VV_MF2_MASK, + 8225 => Opcode::PseudoVMINU_VV_MF4, + 8226 => Opcode::PseudoVMINU_VV_MF4_MASK, + 8227 => Opcode::PseudoVMINU_VV_MF8, + 8228 => Opcode::PseudoVMINU_VV_MF8_MASK, + 8229 => Opcode::PseudoVMINU_VX_M1, + 8230 => Opcode::PseudoVMINU_VX_M1_MASK, + 8231 => Opcode::PseudoVMINU_VX_M2, + 8232 => Opcode::PseudoVMINU_VX_M2_MASK, + 8233 => Opcode::PseudoVMINU_VX_M4, + 8234 => Opcode::PseudoVMINU_VX_M4_MASK, + 8235 => Opcode::PseudoVMINU_VX_M8, + 8236 => Opcode::PseudoVMINU_VX_M8_MASK, + 8237 => Opcode::PseudoVMINU_VX_MF2, + 8238 => Opcode::PseudoVMINU_VX_MF2_MASK, + 8239 => Opcode::PseudoVMINU_VX_MF4, + 8240 => Opcode::PseudoVMINU_VX_MF4_MASK, + 8241 => Opcode::PseudoVMINU_VX_MF8, + 8242 => Opcode::PseudoVMINU_VX_MF8_MASK, + 8243 => Opcode::PseudoVMIN_VV_M1, + 8244 => Opcode::PseudoVMIN_VV_M1_MASK, + 8245 => Opcode::PseudoVMIN_VV_M2, + 8246 => Opcode::PseudoVMIN_VV_M2_MASK, + 8247 => Opcode::PseudoVMIN_VV_M4, + 8248 => Opcode::PseudoVMIN_VV_M4_MASK, + 8249 => Opcode::PseudoVMIN_VV_M8, + 8250 => Opcode::PseudoVMIN_VV_M8_MASK, + 8251 => Opcode::PseudoVMIN_VV_MF2, + 8252 => Opcode::PseudoVMIN_VV_MF2_MASK, + 8253 => Opcode::PseudoVMIN_VV_MF4, + 8254 => Opcode::PseudoVMIN_VV_MF4_MASK, + 8255 => Opcode::PseudoVMIN_VV_MF8, + 8256 => Opcode::PseudoVMIN_VV_MF8_MASK, + 8257 => Opcode::PseudoVMIN_VX_M1, + 8258 => Opcode::PseudoVMIN_VX_M1_MASK, + 8259 => Opcode::PseudoVMIN_VX_M2, + 8260 => Opcode::PseudoVMIN_VX_M2_MASK, + 8261 => Opcode::PseudoVMIN_VX_M4, + 8262 => Opcode::PseudoVMIN_VX_M4_MASK, + 8263 => Opcode::PseudoVMIN_VX_M8, + 8264 => Opcode::PseudoVMIN_VX_M8_MASK, + 8265 => Opcode::PseudoVMIN_VX_MF2, + 8266 => Opcode::PseudoVMIN_VX_MF2_MASK, + 8267 => Opcode::PseudoVMIN_VX_MF4, + 8268 => Opcode::PseudoVMIN_VX_MF4_MASK, + 8269 => Opcode::PseudoVMIN_VX_MF8, + 8270 => Opcode::PseudoVMIN_VX_MF8_MASK, + 8271 => Opcode::PseudoVMNAND_MM_B1, + 8272 => Opcode::PseudoVMNAND_MM_B16, + 8273 => Opcode::PseudoVMNAND_MM_B2, + 8274 => Opcode::PseudoVMNAND_MM_B32, + 8275 => Opcode::PseudoVMNAND_MM_B4, + 8276 => Opcode::PseudoVMNAND_MM_B64, + 8277 => Opcode::PseudoVMNAND_MM_B8, + 8278 => Opcode::PseudoVMNOR_MM_B1, + 8279 => Opcode::PseudoVMNOR_MM_B16, + 8280 => Opcode::PseudoVMNOR_MM_B2, + 8281 => Opcode::PseudoVMNOR_MM_B32, + 8282 => Opcode::PseudoVMNOR_MM_B4, + 8283 => Opcode::PseudoVMNOR_MM_B64, + 8284 => Opcode::PseudoVMNOR_MM_B8, + 8285 => Opcode::PseudoVMORN_MM_B1, + 8286 => Opcode::PseudoVMORN_MM_B16, + 8287 => Opcode::PseudoVMORN_MM_B2, + 8288 => Opcode::PseudoVMORN_MM_B32, + 8289 => Opcode::PseudoVMORN_MM_B4, + 8290 => Opcode::PseudoVMORN_MM_B64, + 8291 => Opcode::PseudoVMORN_MM_B8, + 8292 => Opcode::PseudoVMOR_MM_B1, + 8293 => Opcode::PseudoVMOR_MM_B16, + 8294 => Opcode::PseudoVMOR_MM_B2, + 8295 => Opcode::PseudoVMOR_MM_B32, + 8296 => Opcode::PseudoVMOR_MM_B4, + 8297 => Opcode::PseudoVMOR_MM_B64, + 8298 => Opcode::PseudoVMOR_MM_B8, + 8299 => Opcode::PseudoVMSBC_VVM_M1, + 8300 => Opcode::PseudoVMSBC_VVM_M2, + 8301 => Opcode::PseudoVMSBC_VVM_M4, + 8302 => Opcode::PseudoVMSBC_VVM_M8, + 8303 => Opcode::PseudoVMSBC_VVM_MF2, + 8304 => Opcode::PseudoVMSBC_VVM_MF4, + 8305 => Opcode::PseudoVMSBC_VVM_MF8, + 8306 => Opcode::PseudoVMSBC_VV_M1, + 8307 => Opcode::PseudoVMSBC_VV_M2, + 8308 => Opcode::PseudoVMSBC_VV_M4, + 8309 => Opcode::PseudoVMSBC_VV_M8, + 8310 => Opcode::PseudoVMSBC_VV_MF2, + 8311 => Opcode::PseudoVMSBC_VV_MF4, + 8312 => Opcode::PseudoVMSBC_VV_MF8, + 8313 => Opcode::PseudoVMSBC_VXM_M1, + 8314 => Opcode::PseudoVMSBC_VXM_M2, + 8315 => Opcode::PseudoVMSBC_VXM_M4, + 8316 => Opcode::PseudoVMSBC_VXM_M8, + 8317 => Opcode::PseudoVMSBC_VXM_MF2, + 8318 => Opcode::PseudoVMSBC_VXM_MF4, + 8319 => Opcode::PseudoVMSBC_VXM_MF8, + 8320 => Opcode::PseudoVMSBC_VX_M1, + 8321 => Opcode::PseudoVMSBC_VX_M2, + 8322 => Opcode::PseudoVMSBC_VX_M4, + 8323 => Opcode::PseudoVMSBC_VX_M8, + 8324 => Opcode::PseudoVMSBC_VX_MF2, + 8325 => Opcode::PseudoVMSBC_VX_MF4, + 8326 => Opcode::PseudoVMSBC_VX_MF8, + 8327 => Opcode::PseudoVMSBF_M_B1, + 8328 => Opcode::PseudoVMSBF_M_B16, + 8329 => Opcode::PseudoVMSBF_M_B16_MASK, + 8330 => Opcode::PseudoVMSBF_M_B1_MASK, + 8331 => Opcode::PseudoVMSBF_M_B2, + 8332 => Opcode::PseudoVMSBF_M_B2_MASK, + 8333 => Opcode::PseudoVMSBF_M_B32, + 8334 => Opcode::PseudoVMSBF_M_B32_MASK, + 8335 => Opcode::PseudoVMSBF_M_B4, + 8336 => Opcode::PseudoVMSBF_M_B4_MASK, + 8337 => Opcode::PseudoVMSBF_M_B64, + 8338 => Opcode::PseudoVMSBF_M_B64_MASK, + 8339 => Opcode::PseudoVMSBF_M_B8, + 8340 => Opcode::PseudoVMSBF_M_B8_MASK, + 8341 => Opcode::PseudoVMSEQ_VI_M1, + 8342 => Opcode::PseudoVMSEQ_VI_M1_MASK, + 8343 => Opcode::PseudoVMSEQ_VI_M2, + 8344 => Opcode::PseudoVMSEQ_VI_M2_MASK, + 8345 => Opcode::PseudoVMSEQ_VI_M4, + 8346 => Opcode::PseudoVMSEQ_VI_M4_MASK, + 8347 => Opcode::PseudoVMSEQ_VI_M8, + 8348 => Opcode::PseudoVMSEQ_VI_M8_MASK, + 8349 => Opcode::PseudoVMSEQ_VI_MF2, + 8350 => Opcode::PseudoVMSEQ_VI_MF2_MASK, + 8351 => Opcode::PseudoVMSEQ_VI_MF4, + 8352 => Opcode::PseudoVMSEQ_VI_MF4_MASK, + 8353 => Opcode::PseudoVMSEQ_VI_MF8, + 8354 => Opcode::PseudoVMSEQ_VI_MF8_MASK, + 8355 => Opcode::PseudoVMSEQ_VV_M1, + 8356 => Opcode::PseudoVMSEQ_VV_M1_MASK, + 8357 => Opcode::PseudoVMSEQ_VV_M2, + 8358 => Opcode::PseudoVMSEQ_VV_M2_MASK, + 8359 => Opcode::PseudoVMSEQ_VV_M4, + 8360 => Opcode::PseudoVMSEQ_VV_M4_MASK, + 8361 => Opcode::PseudoVMSEQ_VV_M8, + 8362 => Opcode::PseudoVMSEQ_VV_M8_MASK, + 8363 => Opcode::PseudoVMSEQ_VV_MF2, + 8364 => Opcode::PseudoVMSEQ_VV_MF2_MASK, + 8365 => Opcode::PseudoVMSEQ_VV_MF4, + 8366 => Opcode::PseudoVMSEQ_VV_MF4_MASK, + 8367 => Opcode::PseudoVMSEQ_VV_MF8, + 8368 => Opcode::PseudoVMSEQ_VV_MF8_MASK, + 8369 => Opcode::PseudoVMSEQ_VX_M1, + 8370 => Opcode::PseudoVMSEQ_VX_M1_MASK, + 8371 => Opcode::PseudoVMSEQ_VX_M2, + 8372 => Opcode::PseudoVMSEQ_VX_M2_MASK, + 8373 => Opcode::PseudoVMSEQ_VX_M4, + 8374 => Opcode::PseudoVMSEQ_VX_M4_MASK, + 8375 => Opcode::PseudoVMSEQ_VX_M8, + 8376 => Opcode::PseudoVMSEQ_VX_M8_MASK, + 8377 => Opcode::PseudoVMSEQ_VX_MF2, + 8378 => Opcode::PseudoVMSEQ_VX_MF2_MASK, + 8379 => Opcode::PseudoVMSEQ_VX_MF4, + 8380 => Opcode::PseudoVMSEQ_VX_MF4_MASK, + 8381 => Opcode::PseudoVMSEQ_VX_MF8, + 8382 => Opcode::PseudoVMSEQ_VX_MF8_MASK, + 8383 => Opcode::PseudoVMSET_M_B1, + 8384 => Opcode::PseudoVMSET_M_B16, + 8385 => Opcode::PseudoVMSET_M_B2, + 8386 => Opcode::PseudoVMSET_M_B32, + 8387 => Opcode::PseudoVMSET_M_B4, + 8388 => Opcode::PseudoVMSET_M_B64, + 8389 => Opcode::PseudoVMSET_M_B8, + 8390 => Opcode::PseudoVMSGEU_VI, + 8391 => Opcode::PseudoVMSGEU_VX, + 8392 => Opcode::PseudoVMSGEU_VX_M, + 8393 => Opcode::PseudoVMSGEU_VX_M_T, + 8394 => Opcode::PseudoVMSGE_VI, + 8395 => Opcode::PseudoVMSGE_VX, + 8396 => Opcode::PseudoVMSGE_VX_M, + 8397 => Opcode::PseudoVMSGE_VX_M_T, + 8398 => Opcode::PseudoVMSGTU_VI_M1, + 8399 => Opcode::PseudoVMSGTU_VI_M1_MASK, + 8400 => Opcode::PseudoVMSGTU_VI_M2, + 8401 => Opcode::PseudoVMSGTU_VI_M2_MASK, + 8402 => Opcode::PseudoVMSGTU_VI_M4, + 8403 => Opcode::PseudoVMSGTU_VI_M4_MASK, + 8404 => Opcode::PseudoVMSGTU_VI_M8, + 8405 => Opcode::PseudoVMSGTU_VI_M8_MASK, + 8406 => Opcode::PseudoVMSGTU_VI_MF2, + 8407 => Opcode::PseudoVMSGTU_VI_MF2_MASK, + 8408 => Opcode::PseudoVMSGTU_VI_MF4, + 8409 => Opcode::PseudoVMSGTU_VI_MF4_MASK, + 8410 => Opcode::PseudoVMSGTU_VI_MF8, + 8411 => Opcode::PseudoVMSGTU_VI_MF8_MASK, + 8412 => Opcode::PseudoVMSGTU_VX_M1, + 8413 => Opcode::PseudoVMSGTU_VX_M1_MASK, + 8414 => Opcode::PseudoVMSGTU_VX_M2, + 8415 => Opcode::PseudoVMSGTU_VX_M2_MASK, + 8416 => Opcode::PseudoVMSGTU_VX_M4, + 8417 => Opcode::PseudoVMSGTU_VX_M4_MASK, + 8418 => Opcode::PseudoVMSGTU_VX_M8, + 8419 => Opcode::PseudoVMSGTU_VX_M8_MASK, + 8420 => Opcode::PseudoVMSGTU_VX_MF2, + 8421 => Opcode::PseudoVMSGTU_VX_MF2_MASK, + 8422 => Opcode::PseudoVMSGTU_VX_MF4, + 8423 => Opcode::PseudoVMSGTU_VX_MF4_MASK, + 8424 => Opcode::PseudoVMSGTU_VX_MF8, + 8425 => Opcode::PseudoVMSGTU_VX_MF8_MASK, + 8426 => Opcode::PseudoVMSGT_VI_M1, + 8427 => Opcode::PseudoVMSGT_VI_M1_MASK, + 8428 => Opcode::PseudoVMSGT_VI_M2, + 8429 => Opcode::PseudoVMSGT_VI_M2_MASK, + 8430 => Opcode::PseudoVMSGT_VI_M4, + 8431 => Opcode::PseudoVMSGT_VI_M4_MASK, + 8432 => Opcode::PseudoVMSGT_VI_M8, + 8433 => Opcode::PseudoVMSGT_VI_M8_MASK, + 8434 => Opcode::PseudoVMSGT_VI_MF2, + 8435 => Opcode::PseudoVMSGT_VI_MF2_MASK, + 8436 => Opcode::PseudoVMSGT_VI_MF4, + 8437 => Opcode::PseudoVMSGT_VI_MF4_MASK, + 8438 => Opcode::PseudoVMSGT_VI_MF8, + 8439 => Opcode::PseudoVMSGT_VI_MF8_MASK, + 8440 => Opcode::PseudoVMSGT_VX_M1, + 8441 => Opcode::PseudoVMSGT_VX_M1_MASK, + 8442 => Opcode::PseudoVMSGT_VX_M2, + 8443 => Opcode::PseudoVMSGT_VX_M2_MASK, + 8444 => Opcode::PseudoVMSGT_VX_M4, + 8445 => Opcode::PseudoVMSGT_VX_M4_MASK, + 8446 => Opcode::PseudoVMSGT_VX_M8, + 8447 => Opcode::PseudoVMSGT_VX_M8_MASK, + 8448 => Opcode::PseudoVMSGT_VX_MF2, + 8449 => Opcode::PseudoVMSGT_VX_MF2_MASK, + 8450 => Opcode::PseudoVMSGT_VX_MF4, + 8451 => Opcode::PseudoVMSGT_VX_MF4_MASK, + 8452 => Opcode::PseudoVMSGT_VX_MF8, + 8453 => Opcode::PseudoVMSGT_VX_MF8_MASK, + 8454 => Opcode::PseudoVMSIF_M_B1, + 8455 => Opcode::PseudoVMSIF_M_B16, + 8456 => Opcode::PseudoVMSIF_M_B16_MASK, + 8457 => Opcode::PseudoVMSIF_M_B1_MASK, + 8458 => Opcode::PseudoVMSIF_M_B2, + 8459 => Opcode::PseudoVMSIF_M_B2_MASK, + 8460 => Opcode::PseudoVMSIF_M_B32, + 8461 => Opcode::PseudoVMSIF_M_B32_MASK, + 8462 => Opcode::PseudoVMSIF_M_B4, + 8463 => Opcode::PseudoVMSIF_M_B4_MASK, + 8464 => Opcode::PseudoVMSIF_M_B64, + 8465 => Opcode::PseudoVMSIF_M_B64_MASK, + 8466 => Opcode::PseudoVMSIF_M_B8, + 8467 => Opcode::PseudoVMSIF_M_B8_MASK, + 8468 => Opcode::PseudoVMSLEU_VI_M1, + 8469 => Opcode::PseudoVMSLEU_VI_M1_MASK, + 8470 => Opcode::PseudoVMSLEU_VI_M2, + 8471 => Opcode::PseudoVMSLEU_VI_M2_MASK, + 8472 => Opcode::PseudoVMSLEU_VI_M4, + 8473 => Opcode::PseudoVMSLEU_VI_M4_MASK, + 8474 => Opcode::PseudoVMSLEU_VI_M8, + 8475 => Opcode::PseudoVMSLEU_VI_M8_MASK, + 8476 => Opcode::PseudoVMSLEU_VI_MF2, + 8477 => Opcode::PseudoVMSLEU_VI_MF2_MASK, + 8478 => Opcode::PseudoVMSLEU_VI_MF4, + 8479 => Opcode::PseudoVMSLEU_VI_MF4_MASK, + 8480 => Opcode::PseudoVMSLEU_VI_MF8, + 8481 => Opcode::PseudoVMSLEU_VI_MF8_MASK, + 8482 => Opcode::PseudoVMSLEU_VV_M1, + 8483 => Opcode::PseudoVMSLEU_VV_M1_MASK, + 8484 => Opcode::PseudoVMSLEU_VV_M2, + 8485 => Opcode::PseudoVMSLEU_VV_M2_MASK, + 8486 => Opcode::PseudoVMSLEU_VV_M4, + 8487 => Opcode::PseudoVMSLEU_VV_M4_MASK, + 8488 => Opcode::PseudoVMSLEU_VV_M8, + 8489 => Opcode::PseudoVMSLEU_VV_M8_MASK, + 8490 => Opcode::PseudoVMSLEU_VV_MF2, + 8491 => Opcode::PseudoVMSLEU_VV_MF2_MASK, + 8492 => Opcode::PseudoVMSLEU_VV_MF4, + 8493 => Opcode::PseudoVMSLEU_VV_MF4_MASK, + 8494 => Opcode::PseudoVMSLEU_VV_MF8, + 8495 => Opcode::PseudoVMSLEU_VV_MF8_MASK, + 8496 => Opcode::PseudoVMSLEU_VX_M1, + 8497 => Opcode::PseudoVMSLEU_VX_M1_MASK, + 8498 => Opcode::PseudoVMSLEU_VX_M2, + 8499 => Opcode::PseudoVMSLEU_VX_M2_MASK, + 8500 => Opcode::PseudoVMSLEU_VX_M4, + 8501 => Opcode::PseudoVMSLEU_VX_M4_MASK, + 8502 => Opcode::PseudoVMSLEU_VX_M8, + 8503 => Opcode::PseudoVMSLEU_VX_M8_MASK, + 8504 => Opcode::PseudoVMSLEU_VX_MF2, + 8505 => Opcode::PseudoVMSLEU_VX_MF2_MASK, + 8506 => Opcode::PseudoVMSLEU_VX_MF4, + 8507 => Opcode::PseudoVMSLEU_VX_MF4_MASK, + 8508 => Opcode::PseudoVMSLEU_VX_MF8, + 8509 => Opcode::PseudoVMSLEU_VX_MF8_MASK, + 8510 => Opcode::PseudoVMSLE_VI_M1, + 8511 => Opcode::PseudoVMSLE_VI_M1_MASK, + 8512 => Opcode::PseudoVMSLE_VI_M2, + 8513 => Opcode::PseudoVMSLE_VI_M2_MASK, + 8514 => Opcode::PseudoVMSLE_VI_M4, + 8515 => Opcode::PseudoVMSLE_VI_M4_MASK, + 8516 => Opcode::PseudoVMSLE_VI_M8, + 8517 => Opcode::PseudoVMSLE_VI_M8_MASK, + 8518 => Opcode::PseudoVMSLE_VI_MF2, + 8519 => Opcode::PseudoVMSLE_VI_MF2_MASK, + 8520 => Opcode::PseudoVMSLE_VI_MF4, + 8521 => Opcode::PseudoVMSLE_VI_MF4_MASK, + 8522 => Opcode::PseudoVMSLE_VI_MF8, + 8523 => Opcode::PseudoVMSLE_VI_MF8_MASK, + 8524 => Opcode::PseudoVMSLE_VV_M1, + 8525 => Opcode::PseudoVMSLE_VV_M1_MASK, + 8526 => Opcode::PseudoVMSLE_VV_M2, + 8527 => Opcode::PseudoVMSLE_VV_M2_MASK, + 8528 => Opcode::PseudoVMSLE_VV_M4, + 8529 => Opcode::PseudoVMSLE_VV_M4_MASK, + 8530 => Opcode::PseudoVMSLE_VV_M8, + 8531 => Opcode::PseudoVMSLE_VV_M8_MASK, + 8532 => Opcode::PseudoVMSLE_VV_MF2, + 8533 => Opcode::PseudoVMSLE_VV_MF2_MASK, + 8534 => Opcode::PseudoVMSLE_VV_MF4, + 8535 => Opcode::PseudoVMSLE_VV_MF4_MASK, + 8536 => Opcode::PseudoVMSLE_VV_MF8, + 8537 => Opcode::PseudoVMSLE_VV_MF8_MASK, + 8538 => Opcode::PseudoVMSLE_VX_M1, + 8539 => Opcode::PseudoVMSLE_VX_M1_MASK, + 8540 => Opcode::PseudoVMSLE_VX_M2, + 8541 => Opcode::PseudoVMSLE_VX_M2_MASK, + 8542 => Opcode::PseudoVMSLE_VX_M4, + 8543 => Opcode::PseudoVMSLE_VX_M4_MASK, + 8544 => Opcode::PseudoVMSLE_VX_M8, + 8545 => Opcode::PseudoVMSLE_VX_M8_MASK, + 8546 => Opcode::PseudoVMSLE_VX_MF2, + 8547 => Opcode::PseudoVMSLE_VX_MF2_MASK, + 8548 => Opcode::PseudoVMSLE_VX_MF4, + 8549 => Opcode::PseudoVMSLE_VX_MF4_MASK, + 8550 => Opcode::PseudoVMSLE_VX_MF8, + 8551 => Opcode::PseudoVMSLE_VX_MF8_MASK, + 8552 => Opcode::PseudoVMSLTU_VI, + 8553 => Opcode::PseudoVMSLTU_VV_M1, + 8554 => Opcode::PseudoVMSLTU_VV_M1_MASK, + 8555 => Opcode::PseudoVMSLTU_VV_M2, + 8556 => Opcode::PseudoVMSLTU_VV_M2_MASK, + 8557 => Opcode::PseudoVMSLTU_VV_M4, + 8558 => Opcode::PseudoVMSLTU_VV_M4_MASK, + 8559 => Opcode::PseudoVMSLTU_VV_M8, + 8560 => Opcode::PseudoVMSLTU_VV_M8_MASK, + 8561 => Opcode::PseudoVMSLTU_VV_MF2, + 8562 => Opcode::PseudoVMSLTU_VV_MF2_MASK, + 8563 => Opcode::PseudoVMSLTU_VV_MF4, + 8564 => Opcode::PseudoVMSLTU_VV_MF4_MASK, + 8565 => Opcode::PseudoVMSLTU_VV_MF8, + 8566 => Opcode::PseudoVMSLTU_VV_MF8_MASK, + 8567 => Opcode::PseudoVMSLTU_VX_M1, + 8568 => Opcode::PseudoVMSLTU_VX_M1_MASK, + 8569 => Opcode::PseudoVMSLTU_VX_M2, + 8570 => Opcode::PseudoVMSLTU_VX_M2_MASK, + 8571 => Opcode::PseudoVMSLTU_VX_M4, + 8572 => Opcode::PseudoVMSLTU_VX_M4_MASK, + 8573 => Opcode::PseudoVMSLTU_VX_M8, + 8574 => Opcode::PseudoVMSLTU_VX_M8_MASK, + 8575 => Opcode::PseudoVMSLTU_VX_MF2, + 8576 => Opcode::PseudoVMSLTU_VX_MF2_MASK, + 8577 => Opcode::PseudoVMSLTU_VX_MF4, + 8578 => Opcode::PseudoVMSLTU_VX_MF4_MASK, + 8579 => Opcode::PseudoVMSLTU_VX_MF8, + 8580 => Opcode::PseudoVMSLTU_VX_MF8_MASK, + 8581 => Opcode::PseudoVMSLT_VI, + 8582 => Opcode::PseudoVMSLT_VV_M1, + 8583 => Opcode::PseudoVMSLT_VV_M1_MASK, + 8584 => Opcode::PseudoVMSLT_VV_M2, + 8585 => Opcode::PseudoVMSLT_VV_M2_MASK, + 8586 => Opcode::PseudoVMSLT_VV_M4, + 8587 => Opcode::PseudoVMSLT_VV_M4_MASK, + 8588 => Opcode::PseudoVMSLT_VV_M8, + 8589 => Opcode::PseudoVMSLT_VV_M8_MASK, + 8590 => Opcode::PseudoVMSLT_VV_MF2, + 8591 => Opcode::PseudoVMSLT_VV_MF2_MASK, + 8592 => Opcode::PseudoVMSLT_VV_MF4, + 8593 => Opcode::PseudoVMSLT_VV_MF4_MASK, + 8594 => Opcode::PseudoVMSLT_VV_MF8, + 8595 => Opcode::PseudoVMSLT_VV_MF8_MASK, + 8596 => Opcode::PseudoVMSLT_VX_M1, + 8597 => Opcode::PseudoVMSLT_VX_M1_MASK, + 8598 => Opcode::PseudoVMSLT_VX_M2, + 8599 => Opcode::PseudoVMSLT_VX_M2_MASK, + 8600 => Opcode::PseudoVMSLT_VX_M4, + 8601 => Opcode::PseudoVMSLT_VX_M4_MASK, + 8602 => Opcode::PseudoVMSLT_VX_M8, + 8603 => Opcode::PseudoVMSLT_VX_M8_MASK, + 8604 => Opcode::PseudoVMSLT_VX_MF2, + 8605 => Opcode::PseudoVMSLT_VX_MF2_MASK, + 8606 => Opcode::PseudoVMSLT_VX_MF4, + 8607 => Opcode::PseudoVMSLT_VX_MF4_MASK, + 8608 => Opcode::PseudoVMSLT_VX_MF8, + 8609 => Opcode::PseudoVMSLT_VX_MF8_MASK, + 8610 => Opcode::PseudoVMSNE_VI_M1, + 8611 => Opcode::PseudoVMSNE_VI_M1_MASK, + 8612 => Opcode::PseudoVMSNE_VI_M2, + 8613 => Opcode::PseudoVMSNE_VI_M2_MASK, + 8614 => Opcode::PseudoVMSNE_VI_M4, + 8615 => Opcode::PseudoVMSNE_VI_M4_MASK, + 8616 => Opcode::PseudoVMSNE_VI_M8, + 8617 => Opcode::PseudoVMSNE_VI_M8_MASK, + 8618 => Opcode::PseudoVMSNE_VI_MF2, + 8619 => Opcode::PseudoVMSNE_VI_MF2_MASK, + 8620 => Opcode::PseudoVMSNE_VI_MF4, + 8621 => Opcode::PseudoVMSNE_VI_MF4_MASK, + 8622 => Opcode::PseudoVMSNE_VI_MF8, + 8623 => Opcode::PseudoVMSNE_VI_MF8_MASK, + 8624 => Opcode::PseudoVMSNE_VV_M1, + 8625 => Opcode::PseudoVMSNE_VV_M1_MASK, + 8626 => Opcode::PseudoVMSNE_VV_M2, + 8627 => Opcode::PseudoVMSNE_VV_M2_MASK, + 8628 => Opcode::PseudoVMSNE_VV_M4, + 8629 => Opcode::PseudoVMSNE_VV_M4_MASK, + 8630 => Opcode::PseudoVMSNE_VV_M8, + 8631 => Opcode::PseudoVMSNE_VV_M8_MASK, + 8632 => Opcode::PseudoVMSNE_VV_MF2, + 8633 => Opcode::PseudoVMSNE_VV_MF2_MASK, + 8634 => Opcode::PseudoVMSNE_VV_MF4, + 8635 => Opcode::PseudoVMSNE_VV_MF4_MASK, + 8636 => Opcode::PseudoVMSNE_VV_MF8, + 8637 => Opcode::PseudoVMSNE_VV_MF8_MASK, + 8638 => Opcode::PseudoVMSNE_VX_M1, + 8639 => Opcode::PseudoVMSNE_VX_M1_MASK, + 8640 => Opcode::PseudoVMSNE_VX_M2, + 8641 => Opcode::PseudoVMSNE_VX_M2_MASK, + 8642 => Opcode::PseudoVMSNE_VX_M4, + 8643 => Opcode::PseudoVMSNE_VX_M4_MASK, + 8644 => Opcode::PseudoVMSNE_VX_M8, + 8645 => Opcode::PseudoVMSNE_VX_M8_MASK, + 8646 => Opcode::PseudoVMSNE_VX_MF2, + 8647 => Opcode::PseudoVMSNE_VX_MF2_MASK, + 8648 => Opcode::PseudoVMSNE_VX_MF4, + 8649 => Opcode::PseudoVMSNE_VX_MF4_MASK, + 8650 => Opcode::PseudoVMSNE_VX_MF8, + 8651 => Opcode::PseudoVMSNE_VX_MF8_MASK, + 8652 => Opcode::PseudoVMSOF_M_B1, + 8653 => Opcode::PseudoVMSOF_M_B16, + 8654 => Opcode::PseudoVMSOF_M_B16_MASK, + 8655 => Opcode::PseudoVMSOF_M_B1_MASK, + 8656 => Opcode::PseudoVMSOF_M_B2, + 8657 => Opcode::PseudoVMSOF_M_B2_MASK, + 8658 => Opcode::PseudoVMSOF_M_B32, + 8659 => Opcode::PseudoVMSOF_M_B32_MASK, + 8660 => Opcode::PseudoVMSOF_M_B4, + 8661 => Opcode::PseudoVMSOF_M_B4_MASK, + 8662 => Opcode::PseudoVMSOF_M_B64, + 8663 => Opcode::PseudoVMSOF_M_B64_MASK, + 8664 => Opcode::PseudoVMSOF_M_B8, + 8665 => Opcode::PseudoVMSOF_M_B8_MASK, + 8666 => Opcode::PseudoVMULHSU_VV_M1, + 8667 => Opcode::PseudoVMULHSU_VV_M1_MASK, + 8668 => Opcode::PseudoVMULHSU_VV_M2, + 8669 => Opcode::PseudoVMULHSU_VV_M2_MASK, + 8670 => Opcode::PseudoVMULHSU_VV_M4, + 8671 => Opcode::PseudoVMULHSU_VV_M4_MASK, + 8672 => Opcode::PseudoVMULHSU_VV_M8, + 8673 => Opcode::PseudoVMULHSU_VV_M8_MASK, + 8674 => Opcode::PseudoVMULHSU_VV_MF2, + 8675 => Opcode::PseudoVMULHSU_VV_MF2_MASK, + 8676 => Opcode::PseudoVMULHSU_VV_MF4, + 8677 => Opcode::PseudoVMULHSU_VV_MF4_MASK, + 8678 => Opcode::PseudoVMULHSU_VV_MF8, + 8679 => Opcode::PseudoVMULHSU_VV_MF8_MASK, + 8680 => Opcode::PseudoVMULHSU_VX_M1, + 8681 => Opcode::PseudoVMULHSU_VX_M1_MASK, + 8682 => Opcode::PseudoVMULHSU_VX_M2, + 8683 => Opcode::PseudoVMULHSU_VX_M2_MASK, + 8684 => Opcode::PseudoVMULHSU_VX_M4, + 8685 => Opcode::PseudoVMULHSU_VX_M4_MASK, + 8686 => Opcode::PseudoVMULHSU_VX_M8, + 8687 => Opcode::PseudoVMULHSU_VX_M8_MASK, + 8688 => Opcode::PseudoVMULHSU_VX_MF2, + 8689 => Opcode::PseudoVMULHSU_VX_MF2_MASK, + 8690 => Opcode::PseudoVMULHSU_VX_MF4, + 8691 => Opcode::PseudoVMULHSU_VX_MF4_MASK, + 8692 => Opcode::PseudoVMULHSU_VX_MF8, + 8693 => Opcode::PseudoVMULHSU_VX_MF8_MASK, + 8694 => Opcode::PseudoVMULHU_VV_M1, + 8695 => Opcode::PseudoVMULHU_VV_M1_MASK, + 8696 => Opcode::PseudoVMULHU_VV_M2, + 8697 => Opcode::PseudoVMULHU_VV_M2_MASK, + 8698 => Opcode::PseudoVMULHU_VV_M4, + 8699 => Opcode::PseudoVMULHU_VV_M4_MASK, + 8700 => Opcode::PseudoVMULHU_VV_M8, + 8701 => Opcode::PseudoVMULHU_VV_M8_MASK, + 8702 => Opcode::PseudoVMULHU_VV_MF2, + 8703 => Opcode::PseudoVMULHU_VV_MF2_MASK, + 8704 => Opcode::PseudoVMULHU_VV_MF4, + 8705 => Opcode::PseudoVMULHU_VV_MF4_MASK, + 8706 => Opcode::PseudoVMULHU_VV_MF8, + 8707 => Opcode::PseudoVMULHU_VV_MF8_MASK, + 8708 => Opcode::PseudoVMULHU_VX_M1, + 8709 => Opcode::PseudoVMULHU_VX_M1_MASK, + 8710 => Opcode::PseudoVMULHU_VX_M2, + 8711 => Opcode::PseudoVMULHU_VX_M2_MASK, + 8712 => Opcode::PseudoVMULHU_VX_M4, + 8713 => Opcode::PseudoVMULHU_VX_M4_MASK, + 8714 => Opcode::PseudoVMULHU_VX_M8, + 8715 => Opcode::PseudoVMULHU_VX_M8_MASK, + 8716 => Opcode::PseudoVMULHU_VX_MF2, + 8717 => Opcode::PseudoVMULHU_VX_MF2_MASK, + 8718 => Opcode::PseudoVMULHU_VX_MF4, + 8719 => Opcode::PseudoVMULHU_VX_MF4_MASK, + 8720 => Opcode::PseudoVMULHU_VX_MF8, + 8721 => Opcode::PseudoVMULHU_VX_MF8_MASK, + 8722 => Opcode::PseudoVMULH_VV_M1, + 8723 => Opcode::PseudoVMULH_VV_M1_MASK, + 8724 => Opcode::PseudoVMULH_VV_M2, + 8725 => Opcode::PseudoVMULH_VV_M2_MASK, + 8726 => Opcode::PseudoVMULH_VV_M4, + 8727 => Opcode::PseudoVMULH_VV_M4_MASK, + 8728 => Opcode::PseudoVMULH_VV_M8, + 8729 => Opcode::PseudoVMULH_VV_M8_MASK, + 8730 => Opcode::PseudoVMULH_VV_MF2, + 8731 => Opcode::PseudoVMULH_VV_MF2_MASK, + 8732 => Opcode::PseudoVMULH_VV_MF4, + 8733 => Opcode::PseudoVMULH_VV_MF4_MASK, + 8734 => Opcode::PseudoVMULH_VV_MF8, + 8735 => Opcode::PseudoVMULH_VV_MF8_MASK, + 8736 => Opcode::PseudoVMULH_VX_M1, + 8737 => Opcode::PseudoVMULH_VX_M1_MASK, + 8738 => Opcode::PseudoVMULH_VX_M2, + 8739 => Opcode::PseudoVMULH_VX_M2_MASK, + 8740 => Opcode::PseudoVMULH_VX_M4, + 8741 => Opcode::PseudoVMULH_VX_M4_MASK, + 8742 => Opcode::PseudoVMULH_VX_M8, + 8743 => Opcode::PseudoVMULH_VX_M8_MASK, + 8744 => Opcode::PseudoVMULH_VX_MF2, + 8745 => Opcode::PseudoVMULH_VX_MF2_MASK, + 8746 => Opcode::PseudoVMULH_VX_MF4, + 8747 => Opcode::PseudoVMULH_VX_MF4_MASK, + 8748 => Opcode::PseudoVMULH_VX_MF8, + 8749 => Opcode::PseudoVMULH_VX_MF8_MASK, + 8750 => Opcode::PseudoVMUL_VV_M1, + 8751 => Opcode::PseudoVMUL_VV_M1_MASK, + 8752 => Opcode::PseudoVMUL_VV_M2, + 8753 => Opcode::PseudoVMUL_VV_M2_MASK, + 8754 => Opcode::PseudoVMUL_VV_M4, + 8755 => Opcode::PseudoVMUL_VV_M4_MASK, + 8756 => Opcode::PseudoVMUL_VV_M8, + 8757 => Opcode::PseudoVMUL_VV_M8_MASK, + 8758 => Opcode::PseudoVMUL_VV_MF2, + 8759 => Opcode::PseudoVMUL_VV_MF2_MASK, + 8760 => Opcode::PseudoVMUL_VV_MF4, + 8761 => Opcode::PseudoVMUL_VV_MF4_MASK, + 8762 => Opcode::PseudoVMUL_VV_MF8, + 8763 => Opcode::PseudoVMUL_VV_MF8_MASK, + 8764 => Opcode::PseudoVMUL_VX_M1, + 8765 => Opcode::PseudoVMUL_VX_M1_MASK, + 8766 => Opcode::PseudoVMUL_VX_M2, + 8767 => Opcode::PseudoVMUL_VX_M2_MASK, + 8768 => Opcode::PseudoVMUL_VX_M4, + 8769 => Opcode::PseudoVMUL_VX_M4_MASK, + 8770 => Opcode::PseudoVMUL_VX_M8, + 8771 => Opcode::PseudoVMUL_VX_M8_MASK, + 8772 => Opcode::PseudoVMUL_VX_MF2, + 8773 => Opcode::PseudoVMUL_VX_MF2_MASK, + 8774 => Opcode::PseudoVMUL_VX_MF4, + 8775 => Opcode::PseudoVMUL_VX_MF4_MASK, + 8776 => Opcode::PseudoVMUL_VX_MF8, + 8777 => Opcode::PseudoVMUL_VX_MF8_MASK, + 8778 => Opcode::PseudoVMV_S_X, + 8779 => Opcode::PseudoVMV_V_I_M1, + 8780 => Opcode::PseudoVMV_V_I_M2, + 8781 => Opcode::PseudoVMV_V_I_M4, + 8782 => Opcode::PseudoVMV_V_I_M8, + 8783 => Opcode::PseudoVMV_V_I_MF2, + 8784 => Opcode::PseudoVMV_V_I_MF4, + 8785 => Opcode::PseudoVMV_V_I_MF8, + 8786 => Opcode::PseudoVMV_V_V_M1, + 8787 => Opcode::PseudoVMV_V_V_M2, + 8788 => Opcode::PseudoVMV_V_V_M4, + 8789 => Opcode::PseudoVMV_V_V_M8, + 8790 => Opcode::PseudoVMV_V_V_MF2, + 8791 => Opcode::PseudoVMV_V_V_MF4, + 8792 => Opcode::PseudoVMV_V_V_MF8, + 8793 => Opcode::PseudoVMV_V_X_M1, + 8794 => Opcode::PseudoVMV_V_X_M2, + 8795 => Opcode::PseudoVMV_V_X_M4, + 8796 => Opcode::PseudoVMV_V_X_M8, + 8797 => Opcode::PseudoVMV_V_X_MF2, + 8798 => Opcode::PseudoVMV_V_X_MF4, + 8799 => Opcode::PseudoVMV_V_X_MF8, + 8800 => Opcode::PseudoVMV_X_S, + 8801 => Opcode::PseudoVMXNOR_MM_B1, + 8802 => Opcode::PseudoVMXNOR_MM_B16, + 8803 => Opcode::PseudoVMXNOR_MM_B2, + 8804 => Opcode::PseudoVMXNOR_MM_B32, + 8805 => Opcode::PseudoVMXNOR_MM_B4, + 8806 => Opcode::PseudoVMXNOR_MM_B64, + 8807 => Opcode::PseudoVMXNOR_MM_B8, + 8808 => Opcode::PseudoVMXOR_MM_B1, + 8809 => Opcode::PseudoVMXOR_MM_B16, + 8810 => Opcode::PseudoVMXOR_MM_B2, + 8811 => Opcode::PseudoVMXOR_MM_B32, + 8812 => Opcode::PseudoVMXOR_MM_B4, + 8813 => Opcode::PseudoVMXOR_MM_B64, + 8814 => Opcode::PseudoVMXOR_MM_B8, + 8815 => Opcode::PseudoVNCLIPU_WI_M1, + 8816 => Opcode::PseudoVNCLIPU_WI_M1_MASK, + 8817 => Opcode::PseudoVNCLIPU_WI_M2, + 8818 => Opcode::PseudoVNCLIPU_WI_M2_MASK, + 8819 => Opcode::PseudoVNCLIPU_WI_M4, + 8820 => Opcode::PseudoVNCLIPU_WI_M4_MASK, + 8821 => Opcode::PseudoVNCLIPU_WI_MF2, + 8822 => Opcode::PseudoVNCLIPU_WI_MF2_MASK, + 8823 => Opcode::PseudoVNCLIPU_WI_MF4, + 8824 => Opcode::PseudoVNCLIPU_WI_MF4_MASK, + 8825 => Opcode::PseudoVNCLIPU_WI_MF8, + 8826 => Opcode::PseudoVNCLIPU_WI_MF8_MASK, + 8827 => Opcode::PseudoVNCLIPU_WV_M1, + 8828 => Opcode::PseudoVNCLIPU_WV_M1_MASK, + 8829 => Opcode::PseudoVNCLIPU_WV_M2, + 8830 => Opcode::PseudoVNCLIPU_WV_M2_MASK, + 8831 => Opcode::PseudoVNCLIPU_WV_M4, + 8832 => Opcode::PseudoVNCLIPU_WV_M4_MASK, + 8833 => Opcode::PseudoVNCLIPU_WV_MF2, + 8834 => Opcode::PseudoVNCLIPU_WV_MF2_MASK, + 8835 => Opcode::PseudoVNCLIPU_WV_MF4, + 8836 => Opcode::PseudoVNCLIPU_WV_MF4_MASK, + 8837 => Opcode::PseudoVNCLIPU_WV_MF8, + 8838 => Opcode::PseudoVNCLIPU_WV_MF8_MASK, + 8839 => Opcode::PseudoVNCLIPU_WX_M1, + 8840 => Opcode::PseudoVNCLIPU_WX_M1_MASK, + 8841 => Opcode::PseudoVNCLIPU_WX_M2, + 8842 => Opcode::PseudoVNCLIPU_WX_M2_MASK, + 8843 => Opcode::PseudoVNCLIPU_WX_M4, + 8844 => Opcode::PseudoVNCLIPU_WX_M4_MASK, + 8845 => Opcode::PseudoVNCLIPU_WX_MF2, + 8846 => Opcode::PseudoVNCLIPU_WX_MF2_MASK, + 8847 => Opcode::PseudoVNCLIPU_WX_MF4, + 8848 => Opcode::PseudoVNCLIPU_WX_MF4_MASK, + 8849 => Opcode::PseudoVNCLIPU_WX_MF8, + 8850 => Opcode::PseudoVNCLIPU_WX_MF8_MASK, + 8851 => Opcode::PseudoVNCLIP_WI_M1, + 8852 => Opcode::PseudoVNCLIP_WI_M1_MASK, + 8853 => Opcode::PseudoVNCLIP_WI_M2, + 8854 => Opcode::PseudoVNCLIP_WI_M2_MASK, + 8855 => Opcode::PseudoVNCLIP_WI_M4, + 8856 => Opcode::PseudoVNCLIP_WI_M4_MASK, + 8857 => Opcode::PseudoVNCLIP_WI_MF2, + 8858 => Opcode::PseudoVNCLIP_WI_MF2_MASK, + 8859 => Opcode::PseudoVNCLIP_WI_MF4, + 8860 => Opcode::PseudoVNCLIP_WI_MF4_MASK, + 8861 => Opcode::PseudoVNCLIP_WI_MF8, + 8862 => Opcode::PseudoVNCLIP_WI_MF8_MASK, + 8863 => Opcode::PseudoVNCLIP_WV_M1, + 8864 => Opcode::PseudoVNCLIP_WV_M1_MASK, + 8865 => Opcode::PseudoVNCLIP_WV_M2, + 8866 => Opcode::PseudoVNCLIP_WV_M2_MASK, + 8867 => Opcode::PseudoVNCLIP_WV_M4, + 8868 => Opcode::PseudoVNCLIP_WV_M4_MASK, + 8869 => Opcode::PseudoVNCLIP_WV_MF2, + 8870 => Opcode::PseudoVNCLIP_WV_MF2_MASK, + 8871 => Opcode::PseudoVNCLIP_WV_MF4, + 8872 => Opcode::PseudoVNCLIP_WV_MF4_MASK, + 8873 => Opcode::PseudoVNCLIP_WV_MF8, + 8874 => Opcode::PseudoVNCLIP_WV_MF8_MASK, + 8875 => Opcode::PseudoVNCLIP_WX_M1, + 8876 => Opcode::PseudoVNCLIP_WX_M1_MASK, + 8877 => Opcode::PseudoVNCLIP_WX_M2, + 8878 => Opcode::PseudoVNCLIP_WX_M2_MASK, + 8879 => Opcode::PseudoVNCLIP_WX_M4, + 8880 => Opcode::PseudoVNCLIP_WX_M4_MASK, + 8881 => Opcode::PseudoVNCLIP_WX_MF2, + 8882 => Opcode::PseudoVNCLIP_WX_MF2_MASK, + 8883 => Opcode::PseudoVNCLIP_WX_MF4, + 8884 => Opcode::PseudoVNCLIP_WX_MF4_MASK, + 8885 => Opcode::PseudoVNCLIP_WX_MF8, + 8886 => Opcode::PseudoVNCLIP_WX_MF8_MASK, + 8887 => Opcode::PseudoVNMSAC_VV_M1, + 8888 => Opcode::PseudoVNMSAC_VV_M1_MASK, + 8889 => Opcode::PseudoVNMSAC_VV_M2, + 8890 => Opcode::PseudoVNMSAC_VV_M2_MASK, + 8891 => Opcode::PseudoVNMSAC_VV_M4, + 8892 => Opcode::PseudoVNMSAC_VV_M4_MASK, + 8893 => Opcode::PseudoVNMSAC_VV_M8, + 8894 => Opcode::PseudoVNMSAC_VV_M8_MASK, + 8895 => Opcode::PseudoVNMSAC_VV_MF2, + 8896 => Opcode::PseudoVNMSAC_VV_MF2_MASK, + 8897 => Opcode::PseudoVNMSAC_VV_MF4, + 8898 => Opcode::PseudoVNMSAC_VV_MF4_MASK, + 8899 => Opcode::PseudoVNMSAC_VV_MF8, + 8900 => Opcode::PseudoVNMSAC_VV_MF8_MASK, + 8901 => Opcode::PseudoVNMSAC_VX_M1, + 8902 => Opcode::PseudoVNMSAC_VX_M1_MASK, + 8903 => Opcode::PseudoVNMSAC_VX_M2, + 8904 => Opcode::PseudoVNMSAC_VX_M2_MASK, + 8905 => Opcode::PseudoVNMSAC_VX_M4, + 8906 => Opcode::PseudoVNMSAC_VX_M4_MASK, + 8907 => Opcode::PseudoVNMSAC_VX_M8, + 8908 => Opcode::PseudoVNMSAC_VX_M8_MASK, + 8909 => Opcode::PseudoVNMSAC_VX_MF2, + 8910 => Opcode::PseudoVNMSAC_VX_MF2_MASK, + 8911 => Opcode::PseudoVNMSAC_VX_MF4, + 8912 => Opcode::PseudoVNMSAC_VX_MF4_MASK, + 8913 => Opcode::PseudoVNMSAC_VX_MF8, + 8914 => Opcode::PseudoVNMSAC_VX_MF8_MASK, + 8915 => Opcode::PseudoVNMSUB_VV_M1, + 8916 => Opcode::PseudoVNMSUB_VV_M1_MASK, + 8917 => Opcode::PseudoVNMSUB_VV_M2, + 8918 => Opcode::PseudoVNMSUB_VV_M2_MASK, + 8919 => Opcode::PseudoVNMSUB_VV_M4, + 8920 => Opcode::PseudoVNMSUB_VV_M4_MASK, + 8921 => Opcode::PseudoVNMSUB_VV_M8, + 8922 => Opcode::PseudoVNMSUB_VV_M8_MASK, + 8923 => Opcode::PseudoVNMSUB_VV_MF2, + 8924 => Opcode::PseudoVNMSUB_VV_MF2_MASK, + 8925 => Opcode::PseudoVNMSUB_VV_MF4, + 8926 => Opcode::PseudoVNMSUB_VV_MF4_MASK, + 8927 => Opcode::PseudoVNMSUB_VV_MF8, + 8928 => Opcode::PseudoVNMSUB_VV_MF8_MASK, + 8929 => Opcode::PseudoVNMSUB_VX_M1, + 8930 => Opcode::PseudoVNMSUB_VX_M1_MASK, + 8931 => Opcode::PseudoVNMSUB_VX_M2, + 8932 => Opcode::PseudoVNMSUB_VX_M2_MASK, + 8933 => Opcode::PseudoVNMSUB_VX_M4, + 8934 => Opcode::PseudoVNMSUB_VX_M4_MASK, + 8935 => Opcode::PseudoVNMSUB_VX_M8, + 8936 => Opcode::PseudoVNMSUB_VX_M8_MASK, + 8937 => Opcode::PseudoVNMSUB_VX_MF2, + 8938 => Opcode::PseudoVNMSUB_VX_MF2_MASK, + 8939 => Opcode::PseudoVNMSUB_VX_MF4, + 8940 => Opcode::PseudoVNMSUB_VX_MF4_MASK, + 8941 => Opcode::PseudoVNMSUB_VX_MF8, + 8942 => Opcode::PseudoVNMSUB_VX_MF8_MASK, + 8943 => Opcode::PseudoVNSRA_WI_M1, + 8944 => Opcode::PseudoVNSRA_WI_M1_MASK, + 8945 => Opcode::PseudoVNSRA_WI_M2, + 8946 => Opcode::PseudoVNSRA_WI_M2_MASK, + 8947 => Opcode::PseudoVNSRA_WI_M4, + 8948 => Opcode::PseudoVNSRA_WI_M4_MASK, + 8949 => Opcode::PseudoVNSRA_WI_MF2, + 8950 => Opcode::PseudoVNSRA_WI_MF2_MASK, + 8951 => Opcode::PseudoVNSRA_WI_MF4, + 8952 => Opcode::PseudoVNSRA_WI_MF4_MASK, + 8953 => Opcode::PseudoVNSRA_WI_MF8, + 8954 => Opcode::PseudoVNSRA_WI_MF8_MASK, + 8955 => Opcode::PseudoVNSRA_WV_M1, + 8956 => Opcode::PseudoVNSRA_WV_M1_MASK, + 8957 => Opcode::PseudoVNSRA_WV_M2, + 8958 => Opcode::PseudoVNSRA_WV_M2_MASK, + 8959 => Opcode::PseudoVNSRA_WV_M4, + 8960 => Opcode::PseudoVNSRA_WV_M4_MASK, + 8961 => Opcode::PseudoVNSRA_WV_MF2, + 8962 => Opcode::PseudoVNSRA_WV_MF2_MASK, + 8963 => Opcode::PseudoVNSRA_WV_MF4, + 8964 => Opcode::PseudoVNSRA_WV_MF4_MASK, + 8965 => Opcode::PseudoVNSRA_WV_MF8, + 8966 => Opcode::PseudoVNSRA_WV_MF8_MASK, + 8967 => Opcode::PseudoVNSRA_WX_M1, + 8968 => Opcode::PseudoVNSRA_WX_M1_MASK, + 8969 => Opcode::PseudoVNSRA_WX_M2, + 8970 => Opcode::PseudoVNSRA_WX_M2_MASK, + 8971 => Opcode::PseudoVNSRA_WX_M4, + 8972 => Opcode::PseudoVNSRA_WX_M4_MASK, + 8973 => Opcode::PseudoVNSRA_WX_MF2, + 8974 => Opcode::PseudoVNSRA_WX_MF2_MASK, + 8975 => Opcode::PseudoVNSRA_WX_MF4, + 8976 => Opcode::PseudoVNSRA_WX_MF4_MASK, + 8977 => Opcode::PseudoVNSRA_WX_MF8, + 8978 => Opcode::PseudoVNSRA_WX_MF8_MASK, + 8979 => Opcode::PseudoVNSRL_WI_M1, + 8980 => Opcode::PseudoVNSRL_WI_M1_MASK, + 8981 => Opcode::PseudoVNSRL_WI_M2, + 8982 => Opcode::PseudoVNSRL_WI_M2_MASK, + 8983 => Opcode::PseudoVNSRL_WI_M4, + 8984 => Opcode::PseudoVNSRL_WI_M4_MASK, + 8985 => Opcode::PseudoVNSRL_WI_MF2, + 8986 => Opcode::PseudoVNSRL_WI_MF2_MASK, + 8987 => Opcode::PseudoVNSRL_WI_MF4, + 8988 => Opcode::PseudoVNSRL_WI_MF4_MASK, + 8989 => Opcode::PseudoVNSRL_WI_MF8, + 8990 => Opcode::PseudoVNSRL_WI_MF8_MASK, + 8991 => Opcode::PseudoVNSRL_WV_M1, + 8992 => Opcode::PseudoVNSRL_WV_M1_MASK, + 8993 => Opcode::PseudoVNSRL_WV_M2, + 8994 => Opcode::PseudoVNSRL_WV_M2_MASK, + 8995 => Opcode::PseudoVNSRL_WV_M4, + 8996 => Opcode::PseudoVNSRL_WV_M4_MASK, + 8997 => Opcode::PseudoVNSRL_WV_MF2, + 8998 => Opcode::PseudoVNSRL_WV_MF2_MASK, + 8999 => Opcode::PseudoVNSRL_WV_MF4, + 9000 => Opcode::PseudoVNSRL_WV_MF4_MASK, + 9001 => Opcode::PseudoVNSRL_WV_MF8, + 9002 => Opcode::PseudoVNSRL_WV_MF8_MASK, + 9003 => Opcode::PseudoVNSRL_WX_M1, + 9004 => Opcode::PseudoVNSRL_WX_M1_MASK, + 9005 => Opcode::PseudoVNSRL_WX_M2, + 9006 => Opcode::PseudoVNSRL_WX_M2_MASK, + 9007 => Opcode::PseudoVNSRL_WX_M4, + 9008 => Opcode::PseudoVNSRL_WX_M4_MASK, + 9009 => Opcode::PseudoVNSRL_WX_MF2, + 9010 => Opcode::PseudoVNSRL_WX_MF2_MASK, + 9011 => Opcode::PseudoVNSRL_WX_MF4, + 9012 => Opcode::PseudoVNSRL_WX_MF4_MASK, + 9013 => Opcode::PseudoVNSRL_WX_MF8, + 9014 => Opcode::PseudoVNSRL_WX_MF8_MASK, + 9015 => Opcode::PseudoVOR_VI_M1, + 9016 => Opcode::PseudoVOR_VI_M1_MASK, + 9017 => Opcode::PseudoVOR_VI_M2, + 9018 => Opcode::PseudoVOR_VI_M2_MASK, + 9019 => Opcode::PseudoVOR_VI_M4, + 9020 => Opcode::PseudoVOR_VI_M4_MASK, + 9021 => Opcode::PseudoVOR_VI_M8, + 9022 => Opcode::PseudoVOR_VI_M8_MASK, + 9023 => Opcode::PseudoVOR_VI_MF2, + 9024 => Opcode::PseudoVOR_VI_MF2_MASK, + 9025 => Opcode::PseudoVOR_VI_MF4, + 9026 => Opcode::PseudoVOR_VI_MF4_MASK, + 9027 => Opcode::PseudoVOR_VI_MF8, + 9028 => Opcode::PseudoVOR_VI_MF8_MASK, + 9029 => Opcode::PseudoVOR_VV_M1, + 9030 => Opcode::PseudoVOR_VV_M1_MASK, + 9031 => Opcode::PseudoVOR_VV_M2, + 9032 => Opcode::PseudoVOR_VV_M2_MASK, + 9033 => Opcode::PseudoVOR_VV_M4, + 9034 => Opcode::PseudoVOR_VV_M4_MASK, + 9035 => Opcode::PseudoVOR_VV_M8, + 9036 => Opcode::PseudoVOR_VV_M8_MASK, + 9037 => Opcode::PseudoVOR_VV_MF2, + 9038 => Opcode::PseudoVOR_VV_MF2_MASK, + 9039 => Opcode::PseudoVOR_VV_MF4, + 9040 => Opcode::PseudoVOR_VV_MF4_MASK, + 9041 => Opcode::PseudoVOR_VV_MF8, + 9042 => Opcode::PseudoVOR_VV_MF8_MASK, + 9043 => Opcode::PseudoVOR_VX_M1, + 9044 => Opcode::PseudoVOR_VX_M1_MASK, + 9045 => Opcode::PseudoVOR_VX_M2, + 9046 => Opcode::PseudoVOR_VX_M2_MASK, + 9047 => Opcode::PseudoVOR_VX_M4, + 9048 => Opcode::PseudoVOR_VX_M4_MASK, + 9049 => Opcode::PseudoVOR_VX_M8, + 9050 => Opcode::PseudoVOR_VX_M8_MASK, + 9051 => Opcode::PseudoVOR_VX_MF2, + 9052 => Opcode::PseudoVOR_VX_MF2_MASK, + 9053 => Opcode::PseudoVOR_VX_MF4, + 9054 => Opcode::PseudoVOR_VX_MF4_MASK, + 9055 => Opcode::PseudoVOR_VX_MF8, + 9056 => Opcode::PseudoVOR_VX_MF8_MASK, + 9057 => Opcode::PseudoVQDOTSU_VV_M1, + 9058 => Opcode::PseudoVQDOTSU_VV_M1_MASK, + 9059 => Opcode::PseudoVQDOTSU_VV_M2, + 9060 => Opcode::PseudoVQDOTSU_VV_M2_MASK, + 9061 => Opcode::PseudoVQDOTSU_VV_M4, + 9062 => Opcode::PseudoVQDOTSU_VV_M4_MASK, + 9063 => Opcode::PseudoVQDOTSU_VV_M8, + 9064 => Opcode::PseudoVQDOTSU_VV_M8_MASK, + 9065 => Opcode::PseudoVQDOTSU_VV_MF2, + 9066 => Opcode::PseudoVQDOTSU_VV_MF2_MASK, + 9067 => Opcode::PseudoVQDOTSU_VX_M1, + 9068 => Opcode::PseudoVQDOTSU_VX_M1_MASK, + 9069 => Opcode::PseudoVQDOTSU_VX_M2, + 9070 => Opcode::PseudoVQDOTSU_VX_M2_MASK, + 9071 => Opcode::PseudoVQDOTSU_VX_M4, + 9072 => Opcode::PseudoVQDOTSU_VX_M4_MASK, + 9073 => Opcode::PseudoVQDOTSU_VX_M8, + 9074 => Opcode::PseudoVQDOTSU_VX_M8_MASK, + 9075 => Opcode::PseudoVQDOTSU_VX_MF2, + 9076 => Opcode::PseudoVQDOTSU_VX_MF2_MASK, + 9077 => Opcode::PseudoVQDOTUS_VX_M1, + 9078 => Opcode::PseudoVQDOTUS_VX_M1_MASK, + 9079 => Opcode::PseudoVQDOTUS_VX_M2, + 9080 => Opcode::PseudoVQDOTUS_VX_M2_MASK, + 9081 => Opcode::PseudoVQDOTUS_VX_M4, + 9082 => Opcode::PseudoVQDOTUS_VX_M4_MASK, + 9083 => Opcode::PseudoVQDOTUS_VX_M8, + 9084 => Opcode::PseudoVQDOTUS_VX_M8_MASK, + 9085 => Opcode::PseudoVQDOTUS_VX_MF2, + 9086 => Opcode::PseudoVQDOTUS_VX_MF2_MASK, + 9087 => Opcode::PseudoVQDOTU_VV_M1, + 9088 => Opcode::PseudoVQDOTU_VV_M1_MASK, + 9089 => Opcode::PseudoVQDOTU_VV_M2, + 9090 => Opcode::PseudoVQDOTU_VV_M2_MASK, + 9091 => Opcode::PseudoVQDOTU_VV_M4, + 9092 => Opcode::PseudoVQDOTU_VV_M4_MASK, + 9093 => Opcode::PseudoVQDOTU_VV_M8, + 9094 => Opcode::PseudoVQDOTU_VV_M8_MASK, + 9095 => Opcode::PseudoVQDOTU_VV_MF2, + 9096 => Opcode::PseudoVQDOTU_VV_MF2_MASK, + 9097 => Opcode::PseudoVQDOTU_VX_M1, + 9098 => Opcode::PseudoVQDOTU_VX_M1_MASK, + 9099 => Opcode::PseudoVQDOTU_VX_M2, + 9100 => Opcode::PseudoVQDOTU_VX_M2_MASK, + 9101 => Opcode::PseudoVQDOTU_VX_M4, + 9102 => Opcode::PseudoVQDOTU_VX_M4_MASK, + 9103 => Opcode::PseudoVQDOTU_VX_M8, + 9104 => Opcode::PseudoVQDOTU_VX_M8_MASK, + 9105 => Opcode::PseudoVQDOTU_VX_MF2, + 9106 => Opcode::PseudoVQDOTU_VX_MF2_MASK, + 9107 => Opcode::PseudoVQDOT_VV_M1, + 9108 => Opcode::PseudoVQDOT_VV_M1_MASK, + 9109 => Opcode::PseudoVQDOT_VV_M2, + 9110 => Opcode::PseudoVQDOT_VV_M2_MASK, + 9111 => Opcode::PseudoVQDOT_VV_M4, + 9112 => Opcode::PseudoVQDOT_VV_M4_MASK, + 9113 => Opcode::PseudoVQDOT_VV_M8, + 9114 => Opcode::PseudoVQDOT_VV_M8_MASK, + 9115 => Opcode::PseudoVQDOT_VV_MF2, + 9116 => Opcode::PseudoVQDOT_VV_MF2_MASK, + 9117 => Opcode::PseudoVQDOT_VX_M1, + 9118 => Opcode::PseudoVQDOT_VX_M1_MASK, + 9119 => Opcode::PseudoVQDOT_VX_M2, + 9120 => Opcode::PseudoVQDOT_VX_M2_MASK, + 9121 => Opcode::PseudoVQDOT_VX_M4, + 9122 => Opcode::PseudoVQDOT_VX_M4_MASK, + 9123 => Opcode::PseudoVQDOT_VX_M8, + 9124 => Opcode::PseudoVQDOT_VX_M8_MASK, + 9125 => Opcode::PseudoVQDOT_VX_MF2, + 9126 => Opcode::PseudoVQDOT_VX_MF2_MASK, + 9127 => Opcode::PseudoVREDAND_VS_M1_E16, + 9128 => Opcode::PseudoVREDAND_VS_M1_E16_MASK, + 9129 => Opcode::PseudoVREDAND_VS_M1_E32, + 9130 => Opcode::PseudoVREDAND_VS_M1_E32_MASK, + 9131 => Opcode::PseudoVREDAND_VS_M1_E64, + 9132 => Opcode::PseudoVREDAND_VS_M1_E64_MASK, + 9133 => Opcode::PseudoVREDAND_VS_M1_E8, + 9134 => Opcode::PseudoVREDAND_VS_M1_E8_MASK, + 9135 => Opcode::PseudoVREDAND_VS_M2_E16, + 9136 => Opcode::PseudoVREDAND_VS_M2_E16_MASK, + 9137 => Opcode::PseudoVREDAND_VS_M2_E32, + 9138 => Opcode::PseudoVREDAND_VS_M2_E32_MASK, + 9139 => Opcode::PseudoVREDAND_VS_M2_E64, + 9140 => Opcode::PseudoVREDAND_VS_M2_E64_MASK, + 9141 => Opcode::PseudoVREDAND_VS_M2_E8, + 9142 => Opcode::PseudoVREDAND_VS_M2_E8_MASK, + 9143 => Opcode::PseudoVREDAND_VS_M4_E16, + 9144 => Opcode::PseudoVREDAND_VS_M4_E16_MASK, + 9145 => Opcode::PseudoVREDAND_VS_M4_E32, + 9146 => Opcode::PseudoVREDAND_VS_M4_E32_MASK, + 9147 => Opcode::PseudoVREDAND_VS_M4_E64, + 9148 => Opcode::PseudoVREDAND_VS_M4_E64_MASK, + 9149 => Opcode::PseudoVREDAND_VS_M4_E8, + 9150 => Opcode::PseudoVREDAND_VS_M4_E8_MASK, + 9151 => Opcode::PseudoVREDAND_VS_M8_E16, + 9152 => Opcode::PseudoVREDAND_VS_M8_E16_MASK, + 9153 => Opcode::PseudoVREDAND_VS_M8_E32, + 9154 => Opcode::PseudoVREDAND_VS_M8_E32_MASK, + 9155 => Opcode::PseudoVREDAND_VS_M8_E64, + 9156 => Opcode::PseudoVREDAND_VS_M8_E64_MASK, + 9157 => Opcode::PseudoVREDAND_VS_M8_E8, + 9158 => Opcode::PseudoVREDAND_VS_M8_E8_MASK, + 9159 => Opcode::PseudoVREDAND_VS_MF2_E16, + 9160 => Opcode::PseudoVREDAND_VS_MF2_E16_MASK, + 9161 => Opcode::PseudoVREDAND_VS_MF2_E32, + 9162 => Opcode::PseudoVREDAND_VS_MF2_E32_MASK, + 9163 => Opcode::PseudoVREDAND_VS_MF2_E8, + 9164 => Opcode::PseudoVREDAND_VS_MF2_E8_MASK, + 9165 => Opcode::PseudoVREDAND_VS_MF4_E16, + 9166 => Opcode::PseudoVREDAND_VS_MF4_E16_MASK, + 9167 => Opcode::PseudoVREDAND_VS_MF4_E8, + 9168 => Opcode::PseudoVREDAND_VS_MF4_E8_MASK, + 9169 => Opcode::PseudoVREDAND_VS_MF8_E8, + 9170 => Opcode::PseudoVREDAND_VS_MF8_E8_MASK, + 9171 => Opcode::PseudoVREDMAXU_VS_M1_E16, + 9172 => Opcode::PseudoVREDMAXU_VS_M1_E16_MASK, + 9173 => Opcode::PseudoVREDMAXU_VS_M1_E32, + 9174 => Opcode::PseudoVREDMAXU_VS_M1_E32_MASK, + 9175 => Opcode::PseudoVREDMAXU_VS_M1_E64, + 9176 => Opcode::PseudoVREDMAXU_VS_M1_E64_MASK, + 9177 => Opcode::PseudoVREDMAXU_VS_M1_E8, + 9178 => Opcode::PseudoVREDMAXU_VS_M1_E8_MASK, + 9179 => Opcode::PseudoVREDMAXU_VS_M2_E16, + 9180 => Opcode::PseudoVREDMAXU_VS_M2_E16_MASK, + 9181 => Opcode::PseudoVREDMAXU_VS_M2_E32, + 9182 => Opcode::PseudoVREDMAXU_VS_M2_E32_MASK, + 9183 => Opcode::PseudoVREDMAXU_VS_M2_E64, + 9184 => Opcode::PseudoVREDMAXU_VS_M2_E64_MASK, + 9185 => Opcode::PseudoVREDMAXU_VS_M2_E8, + 9186 => Opcode::PseudoVREDMAXU_VS_M2_E8_MASK, + 9187 => Opcode::PseudoVREDMAXU_VS_M4_E16, + 9188 => Opcode::PseudoVREDMAXU_VS_M4_E16_MASK, + 9189 => Opcode::PseudoVREDMAXU_VS_M4_E32, + 9190 => Opcode::PseudoVREDMAXU_VS_M4_E32_MASK, + 9191 => Opcode::PseudoVREDMAXU_VS_M4_E64, + 9192 => Opcode::PseudoVREDMAXU_VS_M4_E64_MASK, + 9193 => Opcode::PseudoVREDMAXU_VS_M4_E8, + 9194 => Opcode::PseudoVREDMAXU_VS_M4_E8_MASK, + 9195 => Opcode::PseudoVREDMAXU_VS_M8_E16, + 9196 => Opcode::PseudoVREDMAXU_VS_M8_E16_MASK, + 9197 => Opcode::PseudoVREDMAXU_VS_M8_E32, + 9198 => Opcode::PseudoVREDMAXU_VS_M8_E32_MASK, + 9199 => Opcode::PseudoVREDMAXU_VS_M8_E64, + 9200 => Opcode::PseudoVREDMAXU_VS_M8_E64_MASK, + 9201 => Opcode::PseudoVREDMAXU_VS_M8_E8, + 9202 => Opcode::PseudoVREDMAXU_VS_M8_E8_MASK, + 9203 => Opcode::PseudoVREDMAXU_VS_MF2_E16, + 9204 => Opcode::PseudoVREDMAXU_VS_MF2_E16_MASK, + 9205 => Opcode::PseudoVREDMAXU_VS_MF2_E32, + 9206 => Opcode::PseudoVREDMAXU_VS_MF2_E32_MASK, + 9207 => Opcode::PseudoVREDMAXU_VS_MF2_E8, + 9208 => Opcode::PseudoVREDMAXU_VS_MF2_E8_MASK, + 9209 => Opcode::PseudoVREDMAXU_VS_MF4_E16, + 9210 => Opcode::PseudoVREDMAXU_VS_MF4_E16_MASK, + 9211 => Opcode::PseudoVREDMAXU_VS_MF4_E8, + 9212 => Opcode::PseudoVREDMAXU_VS_MF4_E8_MASK, + 9213 => Opcode::PseudoVREDMAXU_VS_MF8_E8, + 9214 => Opcode::PseudoVREDMAXU_VS_MF8_E8_MASK, + 9215 => Opcode::PseudoVREDMAX_VS_M1_E16, + 9216 => Opcode::PseudoVREDMAX_VS_M1_E16_MASK, + 9217 => Opcode::PseudoVREDMAX_VS_M1_E32, + 9218 => Opcode::PseudoVREDMAX_VS_M1_E32_MASK, + 9219 => Opcode::PseudoVREDMAX_VS_M1_E64, + 9220 => Opcode::PseudoVREDMAX_VS_M1_E64_MASK, + 9221 => Opcode::PseudoVREDMAX_VS_M1_E8, + 9222 => Opcode::PseudoVREDMAX_VS_M1_E8_MASK, + 9223 => Opcode::PseudoVREDMAX_VS_M2_E16, + 9224 => Opcode::PseudoVREDMAX_VS_M2_E16_MASK, + 9225 => Opcode::PseudoVREDMAX_VS_M2_E32, + 9226 => Opcode::PseudoVREDMAX_VS_M2_E32_MASK, + 9227 => Opcode::PseudoVREDMAX_VS_M2_E64, + 9228 => Opcode::PseudoVREDMAX_VS_M2_E64_MASK, + 9229 => Opcode::PseudoVREDMAX_VS_M2_E8, + 9230 => Opcode::PseudoVREDMAX_VS_M2_E8_MASK, + 9231 => Opcode::PseudoVREDMAX_VS_M4_E16, + 9232 => Opcode::PseudoVREDMAX_VS_M4_E16_MASK, + 9233 => Opcode::PseudoVREDMAX_VS_M4_E32, + 9234 => Opcode::PseudoVREDMAX_VS_M4_E32_MASK, + 9235 => Opcode::PseudoVREDMAX_VS_M4_E64, + 9236 => Opcode::PseudoVREDMAX_VS_M4_E64_MASK, + 9237 => Opcode::PseudoVREDMAX_VS_M4_E8, + 9238 => Opcode::PseudoVREDMAX_VS_M4_E8_MASK, + 9239 => Opcode::PseudoVREDMAX_VS_M8_E16, + 9240 => Opcode::PseudoVREDMAX_VS_M8_E16_MASK, + 9241 => Opcode::PseudoVREDMAX_VS_M8_E32, + 9242 => Opcode::PseudoVREDMAX_VS_M8_E32_MASK, + 9243 => Opcode::PseudoVREDMAX_VS_M8_E64, + 9244 => Opcode::PseudoVREDMAX_VS_M8_E64_MASK, + 9245 => Opcode::PseudoVREDMAX_VS_M8_E8, + 9246 => Opcode::PseudoVREDMAX_VS_M8_E8_MASK, + 9247 => Opcode::PseudoVREDMAX_VS_MF2_E16, + 9248 => Opcode::PseudoVREDMAX_VS_MF2_E16_MASK, + 9249 => Opcode::PseudoVREDMAX_VS_MF2_E32, + 9250 => Opcode::PseudoVREDMAX_VS_MF2_E32_MASK, + 9251 => Opcode::PseudoVREDMAX_VS_MF2_E8, + 9252 => Opcode::PseudoVREDMAX_VS_MF2_E8_MASK, + 9253 => Opcode::PseudoVREDMAX_VS_MF4_E16, + 9254 => Opcode::PseudoVREDMAX_VS_MF4_E16_MASK, + 9255 => Opcode::PseudoVREDMAX_VS_MF4_E8, + 9256 => Opcode::PseudoVREDMAX_VS_MF4_E8_MASK, + 9257 => Opcode::PseudoVREDMAX_VS_MF8_E8, + 9258 => Opcode::PseudoVREDMAX_VS_MF8_E8_MASK, + 9259 => Opcode::PseudoVREDMINU_VS_M1_E16, + 9260 => Opcode::PseudoVREDMINU_VS_M1_E16_MASK, + 9261 => Opcode::PseudoVREDMINU_VS_M1_E32, + 9262 => Opcode::PseudoVREDMINU_VS_M1_E32_MASK, + 9263 => Opcode::PseudoVREDMINU_VS_M1_E64, + 9264 => Opcode::PseudoVREDMINU_VS_M1_E64_MASK, + 9265 => Opcode::PseudoVREDMINU_VS_M1_E8, + 9266 => Opcode::PseudoVREDMINU_VS_M1_E8_MASK, + 9267 => Opcode::PseudoVREDMINU_VS_M2_E16, + 9268 => Opcode::PseudoVREDMINU_VS_M2_E16_MASK, + 9269 => Opcode::PseudoVREDMINU_VS_M2_E32, + 9270 => Opcode::PseudoVREDMINU_VS_M2_E32_MASK, + 9271 => Opcode::PseudoVREDMINU_VS_M2_E64, + 9272 => Opcode::PseudoVREDMINU_VS_M2_E64_MASK, + 9273 => Opcode::PseudoVREDMINU_VS_M2_E8, + 9274 => Opcode::PseudoVREDMINU_VS_M2_E8_MASK, + 9275 => Opcode::PseudoVREDMINU_VS_M4_E16, + 9276 => Opcode::PseudoVREDMINU_VS_M4_E16_MASK, + 9277 => Opcode::PseudoVREDMINU_VS_M4_E32, + 9278 => Opcode::PseudoVREDMINU_VS_M4_E32_MASK, + 9279 => Opcode::PseudoVREDMINU_VS_M4_E64, + 9280 => Opcode::PseudoVREDMINU_VS_M4_E64_MASK, + 9281 => Opcode::PseudoVREDMINU_VS_M4_E8, + 9282 => Opcode::PseudoVREDMINU_VS_M4_E8_MASK, + 9283 => Opcode::PseudoVREDMINU_VS_M8_E16, + 9284 => Opcode::PseudoVREDMINU_VS_M8_E16_MASK, + 9285 => Opcode::PseudoVREDMINU_VS_M8_E32, + 9286 => Opcode::PseudoVREDMINU_VS_M8_E32_MASK, + 9287 => Opcode::PseudoVREDMINU_VS_M8_E64, + 9288 => Opcode::PseudoVREDMINU_VS_M8_E64_MASK, + 9289 => Opcode::PseudoVREDMINU_VS_M8_E8, + 9290 => Opcode::PseudoVREDMINU_VS_M8_E8_MASK, + 9291 => Opcode::PseudoVREDMINU_VS_MF2_E16, + 9292 => Opcode::PseudoVREDMINU_VS_MF2_E16_MASK, + 9293 => Opcode::PseudoVREDMINU_VS_MF2_E32, + 9294 => Opcode::PseudoVREDMINU_VS_MF2_E32_MASK, + 9295 => Opcode::PseudoVREDMINU_VS_MF2_E8, + 9296 => Opcode::PseudoVREDMINU_VS_MF2_E8_MASK, + 9297 => Opcode::PseudoVREDMINU_VS_MF4_E16, + 9298 => Opcode::PseudoVREDMINU_VS_MF4_E16_MASK, + 9299 => Opcode::PseudoVREDMINU_VS_MF4_E8, + 9300 => Opcode::PseudoVREDMINU_VS_MF4_E8_MASK, + 9301 => Opcode::PseudoVREDMINU_VS_MF8_E8, + 9302 => Opcode::PseudoVREDMINU_VS_MF8_E8_MASK, + 9303 => Opcode::PseudoVREDMIN_VS_M1_E16, + 9304 => Opcode::PseudoVREDMIN_VS_M1_E16_MASK, + 9305 => Opcode::PseudoVREDMIN_VS_M1_E32, + 9306 => Opcode::PseudoVREDMIN_VS_M1_E32_MASK, + 9307 => Opcode::PseudoVREDMIN_VS_M1_E64, + 9308 => Opcode::PseudoVREDMIN_VS_M1_E64_MASK, + 9309 => Opcode::PseudoVREDMIN_VS_M1_E8, + 9310 => Opcode::PseudoVREDMIN_VS_M1_E8_MASK, + 9311 => Opcode::PseudoVREDMIN_VS_M2_E16, + 9312 => Opcode::PseudoVREDMIN_VS_M2_E16_MASK, + 9313 => Opcode::PseudoVREDMIN_VS_M2_E32, + 9314 => Opcode::PseudoVREDMIN_VS_M2_E32_MASK, + 9315 => Opcode::PseudoVREDMIN_VS_M2_E64, + 9316 => Opcode::PseudoVREDMIN_VS_M2_E64_MASK, + 9317 => Opcode::PseudoVREDMIN_VS_M2_E8, + 9318 => Opcode::PseudoVREDMIN_VS_M2_E8_MASK, + 9319 => Opcode::PseudoVREDMIN_VS_M4_E16, + 9320 => Opcode::PseudoVREDMIN_VS_M4_E16_MASK, + 9321 => Opcode::PseudoVREDMIN_VS_M4_E32, + 9322 => Opcode::PseudoVREDMIN_VS_M4_E32_MASK, + 9323 => Opcode::PseudoVREDMIN_VS_M4_E64, + 9324 => Opcode::PseudoVREDMIN_VS_M4_E64_MASK, + 9325 => Opcode::PseudoVREDMIN_VS_M4_E8, + 9326 => Opcode::PseudoVREDMIN_VS_M4_E8_MASK, + 9327 => Opcode::PseudoVREDMIN_VS_M8_E16, + 9328 => Opcode::PseudoVREDMIN_VS_M8_E16_MASK, + 9329 => Opcode::PseudoVREDMIN_VS_M8_E32, + 9330 => Opcode::PseudoVREDMIN_VS_M8_E32_MASK, + 9331 => Opcode::PseudoVREDMIN_VS_M8_E64, + 9332 => Opcode::PseudoVREDMIN_VS_M8_E64_MASK, + 9333 => Opcode::PseudoVREDMIN_VS_M8_E8, + 9334 => Opcode::PseudoVREDMIN_VS_M8_E8_MASK, + 9335 => Opcode::PseudoVREDMIN_VS_MF2_E16, + 9336 => Opcode::PseudoVREDMIN_VS_MF2_E16_MASK, + 9337 => Opcode::PseudoVREDMIN_VS_MF2_E32, + 9338 => Opcode::PseudoVREDMIN_VS_MF2_E32_MASK, + 9339 => Opcode::PseudoVREDMIN_VS_MF2_E8, + 9340 => Opcode::PseudoVREDMIN_VS_MF2_E8_MASK, + 9341 => Opcode::PseudoVREDMIN_VS_MF4_E16, + 9342 => Opcode::PseudoVREDMIN_VS_MF4_E16_MASK, + 9343 => Opcode::PseudoVREDMIN_VS_MF4_E8, + 9344 => Opcode::PseudoVREDMIN_VS_MF4_E8_MASK, + 9345 => Opcode::PseudoVREDMIN_VS_MF8_E8, + 9346 => Opcode::PseudoVREDMIN_VS_MF8_E8_MASK, + 9347 => Opcode::PseudoVREDOR_VS_M1_E16, + 9348 => Opcode::PseudoVREDOR_VS_M1_E16_MASK, + 9349 => Opcode::PseudoVREDOR_VS_M1_E32, + 9350 => Opcode::PseudoVREDOR_VS_M1_E32_MASK, + 9351 => Opcode::PseudoVREDOR_VS_M1_E64, + 9352 => Opcode::PseudoVREDOR_VS_M1_E64_MASK, + 9353 => Opcode::PseudoVREDOR_VS_M1_E8, + 9354 => Opcode::PseudoVREDOR_VS_M1_E8_MASK, + 9355 => Opcode::PseudoVREDOR_VS_M2_E16, + 9356 => Opcode::PseudoVREDOR_VS_M2_E16_MASK, + 9357 => Opcode::PseudoVREDOR_VS_M2_E32, + 9358 => Opcode::PseudoVREDOR_VS_M2_E32_MASK, + 9359 => Opcode::PseudoVREDOR_VS_M2_E64, + 9360 => Opcode::PseudoVREDOR_VS_M2_E64_MASK, + 9361 => Opcode::PseudoVREDOR_VS_M2_E8, + 9362 => Opcode::PseudoVREDOR_VS_M2_E8_MASK, + 9363 => Opcode::PseudoVREDOR_VS_M4_E16, + 9364 => Opcode::PseudoVREDOR_VS_M4_E16_MASK, + 9365 => Opcode::PseudoVREDOR_VS_M4_E32, + 9366 => Opcode::PseudoVREDOR_VS_M4_E32_MASK, + 9367 => Opcode::PseudoVREDOR_VS_M4_E64, + 9368 => Opcode::PseudoVREDOR_VS_M4_E64_MASK, + 9369 => Opcode::PseudoVREDOR_VS_M4_E8, + 9370 => Opcode::PseudoVREDOR_VS_M4_E8_MASK, + 9371 => Opcode::PseudoVREDOR_VS_M8_E16, + 9372 => Opcode::PseudoVREDOR_VS_M8_E16_MASK, + 9373 => Opcode::PseudoVREDOR_VS_M8_E32, + 9374 => Opcode::PseudoVREDOR_VS_M8_E32_MASK, + 9375 => Opcode::PseudoVREDOR_VS_M8_E64, + 9376 => Opcode::PseudoVREDOR_VS_M8_E64_MASK, + 9377 => Opcode::PseudoVREDOR_VS_M8_E8, + 9378 => Opcode::PseudoVREDOR_VS_M8_E8_MASK, + 9379 => Opcode::PseudoVREDOR_VS_MF2_E16, + 9380 => Opcode::PseudoVREDOR_VS_MF2_E16_MASK, + 9381 => Opcode::PseudoVREDOR_VS_MF2_E32, + 9382 => Opcode::PseudoVREDOR_VS_MF2_E32_MASK, + 9383 => Opcode::PseudoVREDOR_VS_MF2_E8, + 9384 => Opcode::PseudoVREDOR_VS_MF2_E8_MASK, + 9385 => Opcode::PseudoVREDOR_VS_MF4_E16, + 9386 => Opcode::PseudoVREDOR_VS_MF4_E16_MASK, + 9387 => Opcode::PseudoVREDOR_VS_MF4_E8, + 9388 => Opcode::PseudoVREDOR_VS_MF4_E8_MASK, + 9389 => Opcode::PseudoVREDOR_VS_MF8_E8, + 9390 => Opcode::PseudoVREDOR_VS_MF8_E8_MASK, + 9391 => Opcode::PseudoVREDSUM_VS_M1_E16, + 9392 => Opcode::PseudoVREDSUM_VS_M1_E16_MASK, + 9393 => Opcode::PseudoVREDSUM_VS_M1_E32, + 9394 => Opcode::PseudoVREDSUM_VS_M1_E32_MASK, + 9395 => Opcode::PseudoVREDSUM_VS_M1_E64, + 9396 => Opcode::PseudoVREDSUM_VS_M1_E64_MASK, + 9397 => Opcode::PseudoVREDSUM_VS_M1_E8, + 9398 => Opcode::PseudoVREDSUM_VS_M1_E8_MASK, + 9399 => Opcode::PseudoVREDSUM_VS_M2_E16, + 9400 => Opcode::PseudoVREDSUM_VS_M2_E16_MASK, + 9401 => Opcode::PseudoVREDSUM_VS_M2_E32, + 9402 => Opcode::PseudoVREDSUM_VS_M2_E32_MASK, + 9403 => Opcode::PseudoVREDSUM_VS_M2_E64, + 9404 => Opcode::PseudoVREDSUM_VS_M2_E64_MASK, + 9405 => Opcode::PseudoVREDSUM_VS_M2_E8, + 9406 => Opcode::PseudoVREDSUM_VS_M2_E8_MASK, + 9407 => Opcode::PseudoVREDSUM_VS_M4_E16, + 9408 => Opcode::PseudoVREDSUM_VS_M4_E16_MASK, + 9409 => Opcode::PseudoVREDSUM_VS_M4_E32, + 9410 => Opcode::PseudoVREDSUM_VS_M4_E32_MASK, + 9411 => Opcode::PseudoVREDSUM_VS_M4_E64, + 9412 => Opcode::PseudoVREDSUM_VS_M4_E64_MASK, + 9413 => Opcode::PseudoVREDSUM_VS_M4_E8, + 9414 => Opcode::PseudoVREDSUM_VS_M4_E8_MASK, + 9415 => Opcode::PseudoVREDSUM_VS_M8_E16, + 9416 => Opcode::PseudoVREDSUM_VS_M8_E16_MASK, + 9417 => Opcode::PseudoVREDSUM_VS_M8_E32, + 9418 => Opcode::PseudoVREDSUM_VS_M8_E32_MASK, + 9419 => Opcode::PseudoVREDSUM_VS_M8_E64, + 9420 => Opcode::PseudoVREDSUM_VS_M8_E64_MASK, + 9421 => Opcode::PseudoVREDSUM_VS_M8_E8, + 9422 => Opcode::PseudoVREDSUM_VS_M8_E8_MASK, + 9423 => Opcode::PseudoVREDSUM_VS_MF2_E16, + 9424 => Opcode::PseudoVREDSUM_VS_MF2_E16_MASK, + 9425 => Opcode::PseudoVREDSUM_VS_MF2_E32, + 9426 => Opcode::PseudoVREDSUM_VS_MF2_E32_MASK, + 9427 => Opcode::PseudoVREDSUM_VS_MF2_E8, + 9428 => Opcode::PseudoVREDSUM_VS_MF2_E8_MASK, + 9429 => Opcode::PseudoVREDSUM_VS_MF4_E16, + 9430 => Opcode::PseudoVREDSUM_VS_MF4_E16_MASK, + 9431 => Opcode::PseudoVREDSUM_VS_MF4_E8, + 9432 => Opcode::PseudoVREDSUM_VS_MF4_E8_MASK, + 9433 => Opcode::PseudoVREDSUM_VS_MF8_E8, + 9434 => Opcode::PseudoVREDSUM_VS_MF8_E8_MASK, + 9435 => Opcode::PseudoVREDXOR_VS_M1_E16, + 9436 => Opcode::PseudoVREDXOR_VS_M1_E16_MASK, + 9437 => Opcode::PseudoVREDXOR_VS_M1_E32, + 9438 => Opcode::PseudoVREDXOR_VS_M1_E32_MASK, + 9439 => Opcode::PseudoVREDXOR_VS_M1_E64, + 9440 => Opcode::PseudoVREDXOR_VS_M1_E64_MASK, + 9441 => Opcode::PseudoVREDXOR_VS_M1_E8, + 9442 => Opcode::PseudoVREDXOR_VS_M1_E8_MASK, + 9443 => Opcode::PseudoVREDXOR_VS_M2_E16, + 9444 => Opcode::PseudoVREDXOR_VS_M2_E16_MASK, + 9445 => Opcode::PseudoVREDXOR_VS_M2_E32, + 9446 => Opcode::PseudoVREDXOR_VS_M2_E32_MASK, + 9447 => Opcode::PseudoVREDXOR_VS_M2_E64, + 9448 => Opcode::PseudoVREDXOR_VS_M2_E64_MASK, + 9449 => Opcode::PseudoVREDXOR_VS_M2_E8, + 9450 => Opcode::PseudoVREDXOR_VS_M2_E8_MASK, + 9451 => Opcode::PseudoVREDXOR_VS_M4_E16, + 9452 => Opcode::PseudoVREDXOR_VS_M4_E16_MASK, + 9453 => Opcode::PseudoVREDXOR_VS_M4_E32, + 9454 => Opcode::PseudoVREDXOR_VS_M4_E32_MASK, + 9455 => Opcode::PseudoVREDXOR_VS_M4_E64, + 9456 => Opcode::PseudoVREDXOR_VS_M4_E64_MASK, + 9457 => Opcode::PseudoVREDXOR_VS_M4_E8, + 9458 => Opcode::PseudoVREDXOR_VS_M4_E8_MASK, + 9459 => Opcode::PseudoVREDXOR_VS_M8_E16, + 9460 => Opcode::PseudoVREDXOR_VS_M8_E16_MASK, + 9461 => Opcode::PseudoVREDXOR_VS_M8_E32, + 9462 => Opcode::PseudoVREDXOR_VS_M8_E32_MASK, + 9463 => Opcode::PseudoVREDXOR_VS_M8_E64, + 9464 => Opcode::PseudoVREDXOR_VS_M8_E64_MASK, + 9465 => Opcode::PseudoVREDXOR_VS_M8_E8, + 9466 => Opcode::PseudoVREDXOR_VS_M8_E8_MASK, + 9467 => Opcode::PseudoVREDXOR_VS_MF2_E16, + 9468 => Opcode::PseudoVREDXOR_VS_MF2_E16_MASK, + 9469 => Opcode::PseudoVREDXOR_VS_MF2_E32, + 9470 => Opcode::PseudoVREDXOR_VS_MF2_E32_MASK, + 9471 => Opcode::PseudoVREDXOR_VS_MF2_E8, + 9472 => Opcode::PseudoVREDXOR_VS_MF2_E8_MASK, + 9473 => Opcode::PseudoVREDXOR_VS_MF4_E16, + 9474 => Opcode::PseudoVREDXOR_VS_MF4_E16_MASK, + 9475 => Opcode::PseudoVREDXOR_VS_MF4_E8, + 9476 => Opcode::PseudoVREDXOR_VS_MF4_E8_MASK, + 9477 => Opcode::PseudoVREDXOR_VS_MF8_E8, + 9478 => Opcode::PseudoVREDXOR_VS_MF8_E8_MASK, + 9479 => Opcode::PseudoVRELOAD2_M1, + 9480 => Opcode::PseudoVRELOAD2_M2, + 9481 => Opcode::PseudoVRELOAD2_M4, + 9482 => Opcode::PseudoVRELOAD2_MF2, + 9483 => Opcode::PseudoVRELOAD2_MF4, + 9484 => Opcode::PseudoVRELOAD2_MF8, + 9485 => Opcode::PseudoVRELOAD3_M1, + 9486 => Opcode::PseudoVRELOAD3_M2, + 9487 => Opcode::PseudoVRELOAD3_MF2, + 9488 => Opcode::PseudoVRELOAD3_MF4, + 9489 => Opcode::PseudoVRELOAD3_MF8, + 9490 => Opcode::PseudoVRELOAD4_M1, + 9491 => Opcode::PseudoVRELOAD4_M2, + 9492 => Opcode::PseudoVRELOAD4_MF2, + 9493 => Opcode::PseudoVRELOAD4_MF4, + 9494 => Opcode::PseudoVRELOAD4_MF8, + 9495 => Opcode::PseudoVRELOAD5_M1, + 9496 => Opcode::PseudoVRELOAD5_MF2, + 9497 => Opcode::PseudoVRELOAD5_MF4, + 9498 => Opcode::PseudoVRELOAD5_MF8, + 9499 => Opcode::PseudoVRELOAD6_M1, + 9500 => Opcode::PseudoVRELOAD6_MF2, + 9501 => Opcode::PseudoVRELOAD6_MF4, + 9502 => Opcode::PseudoVRELOAD6_MF8, + 9503 => Opcode::PseudoVRELOAD7_M1, + 9504 => Opcode::PseudoVRELOAD7_MF2, + 9505 => Opcode::PseudoVRELOAD7_MF4, + 9506 => Opcode::PseudoVRELOAD7_MF8, + 9507 => Opcode::PseudoVRELOAD8_M1, + 9508 => Opcode::PseudoVRELOAD8_MF2, + 9509 => Opcode::PseudoVRELOAD8_MF4, + 9510 => Opcode::PseudoVRELOAD8_MF8, + 9511 => Opcode::PseudoVREMU_VV_M1_E16, + 9512 => Opcode::PseudoVREMU_VV_M1_E16_MASK, + 9513 => Opcode::PseudoVREMU_VV_M1_E32, + 9514 => Opcode::PseudoVREMU_VV_M1_E32_MASK, + 9515 => Opcode::PseudoVREMU_VV_M1_E64, + 9516 => Opcode::PseudoVREMU_VV_M1_E64_MASK, + 9517 => Opcode::PseudoVREMU_VV_M1_E8, + 9518 => Opcode::PseudoVREMU_VV_M1_E8_MASK, + 9519 => Opcode::PseudoVREMU_VV_M2_E16, + 9520 => Opcode::PseudoVREMU_VV_M2_E16_MASK, + 9521 => Opcode::PseudoVREMU_VV_M2_E32, + 9522 => Opcode::PseudoVREMU_VV_M2_E32_MASK, + 9523 => Opcode::PseudoVREMU_VV_M2_E64, + 9524 => Opcode::PseudoVREMU_VV_M2_E64_MASK, + 9525 => Opcode::PseudoVREMU_VV_M2_E8, + 9526 => Opcode::PseudoVREMU_VV_M2_E8_MASK, + 9527 => Opcode::PseudoVREMU_VV_M4_E16, + 9528 => Opcode::PseudoVREMU_VV_M4_E16_MASK, + 9529 => Opcode::PseudoVREMU_VV_M4_E32, + 9530 => Opcode::PseudoVREMU_VV_M4_E32_MASK, + 9531 => Opcode::PseudoVREMU_VV_M4_E64, + 9532 => Opcode::PseudoVREMU_VV_M4_E64_MASK, + 9533 => Opcode::PseudoVREMU_VV_M4_E8, + 9534 => Opcode::PseudoVREMU_VV_M4_E8_MASK, + 9535 => Opcode::PseudoVREMU_VV_M8_E16, + 9536 => Opcode::PseudoVREMU_VV_M8_E16_MASK, + 9537 => Opcode::PseudoVREMU_VV_M8_E32, + 9538 => Opcode::PseudoVREMU_VV_M8_E32_MASK, + 9539 => Opcode::PseudoVREMU_VV_M8_E64, + 9540 => Opcode::PseudoVREMU_VV_M8_E64_MASK, + 9541 => Opcode::PseudoVREMU_VV_M8_E8, + 9542 => Opcode::PseudoVREMU_VV_M8_E8_MASK, + 9543 => Opcode::PseudoVREMU_VV_MF2_E16, + 9544 => Opcode::PseudoVREMU_VV_MF2_E16_MASK, + 9545 => Opcode::PseudoVREMU_VV_MF2_E32, + 9546 => Opcode::PseudoVREMU_VV_MF2_E32_MASK, + 9547 => Opcode::PseudoVREMU_VV_MF2_E8, + 9548 => Opcode::PseudoVREMU_VV_MF2_E8_MASK, + 9549 => Opcode::PseudoVREMU_VV_MF4_E16, + 9550 => Opcode::PseudoVREMU_VV_MF4_E16_MASK, + 9551 => Opcode::PseudoVREMU_VV_MF4_E8, + 9552 => Opcode::PseudoVREMU_VV_MF4_E8_MASK, + 9553 => Opcode::PseudoVREMU_VV_MF8_E8, + 9554 => Opcode::PseudoVREMU_VV_MF8_E8_MASK, + 9555 => Opcode::PseudoVREMU_VX_M1_E16, + 9556 => Opcode::PseudoVREMU_VX_M1_E16_MASK, + 9557 => Opcode::PseudoVREMU_VX_M1_E32, + 9558 => Opcode::PseudoVREMU_VX_M1_E32_MASK, + 9559 => Opcode::PseudoVREMU_VX_M1_E64, + 9560 => Opcode::PseudoVREMU_VX_M1_E64_MASK, + 9561 => Opcode::PseudoVREMU_VX_M1_E8, + 9562 => Opcode::PseudoVREMU_VX_M1_E8_MASK, + 9563 => Opcode::PseudoVREMU_VX_M2_E16, + 9564 => Opcode::PseudoVREMU_VX_M2_E16_MASK, + 9565 => Opcode::PseudoVREMU_VX_M2_E32, + 9566 => Opcode::PseudoVREMU_VX_M2_E32_MASK, + 9567 => Opcode::PseudoVREMU_VX_M2_E64, + 9568 => Opcode::PseudoVREMU_VX_M2_E64_MASK, + 9569 => Opcode::PseudoVREMU_VX_M2_E8, + 9570 => Opcode::PseudoVREMU_VX_M2_E8_MASK, + 9571 => Opcode::PseudoVREMU_VX_M4_E16, + 9572 => Opcode::PseudoVREMU_VX_M4_E16_MASK, + 9573 => Opcode::PseudoVREMU_VX_M4_E32, + 9574 => Opcode::PseudoVREMU_VX_M4_E32_MASK, + 9575 => Opcode::PseudoVREMU_VX_M4_E64, + 9576 => Opcode::PseudoVREMU_VX_M4_E64_MASK, + 9577 => Opcode::PseudoVREMU_VX_M4_E8, + 9578 => Opcode::PseudoVREMU_VX_M4_E8_MASK, + 9579 => Opcode::PseudoVREMU_VX_M8_E16, + 9580 => Opcode::PseudoVREMU_VX_M8_E16_MASK, + 9581 => Opcode::PseudoVREMU_VX_M8_E32, + 9582 => Opcode::PseudoVREMU_VX_M8_E32_MASK, + 9583 => Opcode::PseudoVREMU_VX_M8_E64, + 9584 => Opcode::PseudoVREMU_VX_M8_E64_MASK, + 9585 => Opcode::PseudoVREMU_VX_M8_E8, + 9586 => Opcode::PseudoVREMU_VX_M8_E8_MASK, + 9587 => Opcode::PseudoVREMU_VX_MF2_E16, + 9588 => Opcode::PseudoVREMU_VX_MF2_E16_MASK, + 9589 => Opcode::PseudoVREMU_VX_MF2_E32, + 9590 => Opcode::PseudoVREMU_VX_MF2_E32_MASK, + 9591 => Opcode::PseudoVREMU_VX_MF2_E8, + 9592 => Opcode::PseudoVREMU_VX_MF2_E8_MASK, + 9593 => Opcode::PseudoVREMU_VX_MF4_E16, + 9594 => Opcode::PseudoVREMU_VX_MF4_E16_MASK, + 9595 => Opcode::PseudoVREMU_VX_MF4_E8, + 9596 => Opcode::PseudoVREMU_VX_MF4_E8_MASK, + 9597 => Opcode::PseudoVREMU_VX_MF8_E8, + 9598 => Opcode::PseudoVREMU_VX_MF8_E8_MASK, + 9599 => Opcode::PseudoVREM_VV_M1_E16, + 9600 => Opcode::PseudoVREM_VV_M1_E16_MASK, + 9601 => Opcode::PseudoVREM_VV_M1_E32, + 9602 => Opcode::PseudoVREM_VV_M1_E32_MASK, + 9603 => Opcode::PseudoVREM_VV_M1_E64, + 9604 => Opcode::PseudoVREM_VV_M1_E64_MASK, + 9605 => Opcode::PseudoVREM_VV_M1_E8, + 9606 => Opcode::PseudoVREM_VV_M1_E8_MASK, + 9607 => Opcode::PseudoVREM_VV_M2_E16, + 9608 => Opcode::PseudoVREM_VV_M2_E16_MASK, + 9609 => Opcode::PseudoVREM_VV_M2_E32, + 9610 => Opcode::PseudoVREM_VV_M2_E32_MASK, + 9611 => Opcode::PseudoVREM_VV_M2_E64, + 9612 => Opcode::PseudoVREM_VV_M2_E64_MASK, + 9613 => Opcode::PseudoVREM_VV_M2_E8, + 9614 => Opcode::PseudoVREM_VV_M2_E8_MASK, + 9615 => Opcode::PseudoVREM_VV_M4_E16, + 9616 => Opcode::PseudoVREM_VV_M4_E16_MASK, + 9617 => Opcode::PseudoVREM_VV_M4_E32, + 9618 => Opcode::PseudoVREM_VV_M4_E32_MASK, + 9619 => Opcode::PseudoVREM_VV_M4_E64, + 9620 => Opcode::PseudoVREM_VV_M4_E64_MASK, + 9621 => Opcode::PseudoVREM_VV_M4_E8, + 9622 => Opcode::PseudoVREM_VV_M4_E8_MASK, + 9623 => Opcode::PseudoVREM_VV_M8_E16, + 9624 => Opcode::PseudoVREM_VV_M8_E16_MASK, + 9625 => Opcode::PseudoVREM_VV_M8_E32, + 9626 => Opcode::PseudoVREM_VV_M8_E32_MASK, + 9627 => Opcode::PseudoVREM_VV_M8_E64, + 9628 => Opcode::PseudoVREM_VV_M8_E64_MASK, + 9629 => Opcode::PseudoVREM_VV_M8_E8, + 9630 => Opcode::PseudoVREM_VV_M8_E8_MASK, + 9631 => Opcode::PseudoVREM_VV_MF2_E16, + 9632 => Opcode::PseudoVREM_VV_MF2_E16_MASK, + 9633 => Opcode::PseudoVREM_VV_MF2_E32, + 9634 => Opcode::PseudoVREM_VV_MF2_E32_MASK, + 9635 => Opcode::PseudoVREM_VV_MF2_E8, + 9636 => Opcode::PseudoVREM_VV_MF2_E8_MASK, + 9637 => Opcode::PseudoVREM_VV_MF4_E16, + 9638 => Opcode::PseudoVREM_VV_MF4_E16_MASK, + 9639 => Opcode::PseudoVREM_VV_MF4_E8, + 9640 => Opcode::PseudoVREM_VV_MF4_E8_MASK, + 9641 => Opcode::PseudoVREM_VV_MF8_E8, + 9642 => Opcode::PseudoVREM_VV_MF8_E8_MASK, + 9643 => Opcode::PseudoVREM_VX_M1_E16, + 9644 => Opcode::PseudoVREM_VX_M1_E16_MASK, + 9645 => Opcode::PseudoVREM_VX_M1_E32, + 9646 => Opcode::PseudoVREM_VX_M1_E32_MASK, + 9647 => Opcode::PseudoVREM_VX_M1_E64, + 9648 => Opcode::PseudoVREM_VX_M1_E64_MASK, + 9649 => Opcode::PseudoVREM_VX_M1_E8, + 9650 => Opcode::PseudoVREM_VX_M1_E8_MASK, + 9651 => Opcode::PseudoVREM_VX_M2_E16, + 9652 => Opcode::PseudoVREM_VX_M2_E16_MASK, + 9653 => Opcode::PseudoVREM_VX_M2_E32, + 9654 => Opcode::PseudoVREM_VX_M2_E32_MASK, + 9655 => Opcode::PseudoVREM_VX_M2_E64, + 9656 => Opcode::PseudoVREM_VX_M2_E64_MASK, + 9657 => Opcode::PseudoVREM_VX_M2_E8, + 9658 => Opcode::PseudoVREM_VX_M2_E8_MASK, + 9659 => Opcode::PseudoVREM_VX_M4_E16, + 9660 => Opcode::PseudoVREM_VX_M4_E16_MASK, + 9661 => Opcode::PseudoVREM_VX_M4_E32, + 9662 => Opcode::PseudoVREM_VX_M4_E32_MASK, + 9663 => Opcode::PseudoVREM_VX_M4_E64, + 9664 => Opcode::PseudoVREM_VX_M4_E64_MASK, + 9665 => Opcode::PseudoVREM_VX_M4_E8, + 9666 => Opcode::PseudoVREM_VX_M4_E8_MASK, + 9667 => Opcode::PseudoVREM_VX_M8_E16, + 9668 => Opcode::PseudoVREM_VX_M8_E16_MASK, + 9669 => Opcode::PseudoVREM_VX_M8_E32, + 9670 => Opcode::PseudoVREM_VX_M8_E32_MASK, + 9671 => Opcode::PseudoVREM_VX_M8_E64, + 9672 => Opcode::PseudoVREM_VX_M8_E64_MASK, + 9673 => Opcode::PseudoVREM_VX_M8_E8, + 9674 => Opcode::PseudoVREM_VX_M8_E8_MASK, + 9675 => Opcode::PseudoVREM_VX_MF2_E16, + 9676 => Opcode::PseudoVREM_VX_MF2_E16_MASK, + 9677 => Opcode::PseudoVREM_VX_MF2_E32, + 9678 => Opcode::PseudoVREM_VX_MF2_E32_MASK, + 9679 => Opcode::PseudoVREM_VX_MF2_E8, + 9680 => Opcode::PseudoVREM_VX_MF2_E8_MASK, + 9681 => Opcode::PseudoVREM_VX_MF4_E16, + 9682 => Opcode::PseudoVREM_VX_MF4_E16_MASK, + 9683 => Opcode::PseudoVREM_VX_MF4_E8, + 9684 => Opcode::PseudoVREM_VX_MF4_E8_MASK, + 9685 => Opcode::PseudoVREM_VX_MF8_E8, + 9686 => Opcode::PseudoVREM_VX_MF8_E8_MASK, + 9687 => Opcode::PseudoVREV8_V_M1, + 9688 => Opcode::PseudoVREV8_V_M1_MASK, + 9689 => Opcode::PseudoVREV8_V_M2, + 9690 => Opcode::PseudoVREV8_V_M2_MASK, + 9691 => Opcode::PseudoVREV8_V_M4, + 9692 => Opcode::PseudoVREV8_V_M4_MASK, + 9693 => Opcode::PseudoVREV8_V_M8, + 9694 => Opcode::PseudoVREV8_V_M8_MASK, + 9695 => Opcode::PseudoVREV8_V_MF2, + 9696 => Opcode::PseudoVREV8_V_MF2_MASK, + 9697 => Opcode::PseudoVREV8_V_MF4, + 9698 => Opcode::PseudoVREV8_V_MF4_MASK, + 9699 => Opcode::PseudoVREV8_V_MF8, + 9700 => Opcode::PseudoVREV8_V_MF8_MASK, + 9701 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M1, + 9702 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, + 9703 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M2, + 9704 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, + 9705 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF2, + 9706 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, + 9707 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF4, + 9708 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, + 9709 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M1, + 9710 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, + 9711 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M2, + 9712 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, + 9713 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF2, + 9714 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, + 9715 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF4, + 9716 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, + 9717 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M1, + 9718 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, + 9719 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M2, + 9720 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, + 9721 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF2, + 9722 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, + 9723 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF4, + 9724 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, + 9725 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M1, + 9726 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, + 9727 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M2, + 9728 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, + 9729 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF2, + 9730 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, + 9731 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF4, + 9732 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, + 9733 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M1, + 9734 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, + 9735 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M2, + 9736 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, + 9737 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M4, + 9738 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, + 9739 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_MF2, + 9740 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, + 9741 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M1, + 9742 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, + 9743 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M2, + 9744 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, + 9745 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M4, + 9746 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, + 9747 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_MF2, + 9748 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, + 9749 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M1, + 9750 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, + 9751 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M2, + 9752 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, + 9753 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M4, + 9754 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, + 9755 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_MF2, + 9756 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, + 9757 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M1, + 9758 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, + 9759 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M2, + 9760 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, + 9761 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M4, + 9762 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, + 9763 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_MF2, + 9764 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, + 9765 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M1, + 9766 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, + 9767 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M2, + 9768 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, + 9769 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M4, + 9770 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, + 9771 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M8, + 9772 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, + 9773 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M1, + 9774 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, + 9775 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M2, + 9776 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, + 9777 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M4, + 9778 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, + 9779 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M8, + 9780 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, + 9781 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M1, + 9782 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, + 9783 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M2, + 9784 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, + 9785 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M4, + 9786 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, + 9787 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M8, + 9788 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, + 9789 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M1, + 9790 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, + 9791 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M2, + 9792 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, + 9793 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M4, + 9794 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, + 9795 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M8, + 9796 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, + 9797 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M2, + 9798 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, + 9799 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M4, + 9800 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, + 9801 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M8, + 9802 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, + 9803 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M2, + 9804 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, + 9805 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M4, + 9806 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, + 9807 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M8, + 9808 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, + 9809 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M2, + 9810 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, + 9811 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M4, + 9812 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, + 9813 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M8, + 9814 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, + 9815 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M2, + 9816 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, + 9817 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M4, + 9818 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, + 9819 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M8, + 9820 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, + 9821 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_M1, + 9822 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, + 9823 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF2, + 9824 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, + 9825 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF4, + 9826 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, + 9827 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF8, + 9828 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, + 9829 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_M1, + 9830 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, + 9831 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF2, + 9832 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, + 9833 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF4, + 9834 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, + 9835 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF8, + 9836 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, + 9837 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_M1, + 9838 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, + 9839 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF2, + 9840 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, + 9841 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF4, + 9842 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, + 9843 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF8, + 9844 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, + 9845 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF2, + 9846 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, + 9847 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF4, + 9848 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, + 9849 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF8, + 9850 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, + 9851 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF2, + 9852 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, + 9853 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF4, + 9854 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, + 9855 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF8, + 9856 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, + 9857 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF4, + 9858 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, + 9859 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF8, + 9860 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, + 9861 => Opcode::PseudoVRGATHER_VI_M1, + 9862 => Opcode::PseudoVRGATHER_VI_M1_MASK, + 9863 => Opcode::PseudoVRGATHER_VI_M2, + 9864 => Opcode::PseudoVRGATHER_VI_M2_MASK, + 9865 => Opcode::PseudoVRGATHER_VI_M4, + 9866 => Opcode::PseudoVRGATHER_VI_M4_MASK, + 9867 => Opcode::PseudoVRGATHER_VI_M8, + 9868 => Opcode::PseudoVRGATHER_VI_M8_MASK, + 9869 => Opcode::PseudoVRGATHER_VI_MF2, + 9870 => Opcode::PseudoVRGATHER_VI_MF2_MASK, + 9871 => Opcode::PseudoVRGATHER_VI_MF4, + 9872 => Opcode::PseudoVRGATHER_VI_MF4_MASK, + 9873 => Opcode::PseudoVRGATHER_VI_MF8, + 9874 => Opcode::PseudoVRGATHER_VI_MF8_MASK, + 9875 => Opcode::PseudoVRGATHER_VV_M1_E16, + 9876 => Opcode::PseudoVRGATHER_VV_M1_E16_MASK, + 9877 => Opcode::PseudoVRGATHER_VV_M1_E32, + 9878 => Opcode::PseudoVRGATHER_VV_M1_E32_MASK, + 9879 => Opcode::PseudoVRGATHER_VV_M1_E64, + 9880 => Opcode::PseudoVRGATHER_VV_M1_E64_MASK, + 9881 => Opcode::PseudoVRGATHER_VV_M1_E8, + 9882 => Opcode::PseudoVRGATHER_VV_M1_E8_MASK, + 9883 => Opcode::PseudoVRGATHER_VV_M2_E16, + 9884 => Opcode::PseudoVRGATHER_VV_M2_E16_MASK, + 9885 => Opcode::PseudoVRGATHER_VV_M2_E32, + 9886 => Opcode::PseudoVRGATHER_VV_M2_E32_MASK, + 9887 => Opcode::PseudoVRGATHER_VV_M2_E64, + 9888 => Opcode::PseudoVRGATHER_VV_M2_E64_MASK, + 9889 => Opcode::PseudoVRGATHER_VV_M2_E8, + 9890 => Opcode::PseudoVRGATHER_VV_M2_E8_MASK, + 9891 => Opcode::PseudoVRGATHER_VV_M4_E16, + 9892 => Opcode::PseudoVRGATHER_VV_M4_E16_MASK, + 9893 => Opcode::PseudoVRGATHER_VV_M4_E32, + 9894 => Opcode::PseudoVRGATHER_VV_M4_E32_MASK, + 9895 => Opcode::PseudoVRGATHER_VV_M4_E64, + 9896 => Opcode::PseudoVRGATHER_VV_M4_E64_MASK, + 9897 => Opcode::PseudoVRGATHER_VV_M4_E8, + 9898 => Opcode::PseudoVRGATHER_VV_M4_E8_MASK, + 9899 => Opcode::PseudoVRGATHER_VV_M8_E16, + 9900 => Opcode::PseudoVRGATHER_VV_M8_E16_MASK, + 9901 => Opcode::PseudoVRGATHER_VV_M8_E32, + 9902 => Opcode::PseudoVRGATHER_VV_M8_E32_MASK, + 9903 => Opcode::PseudoVRGATHER_VV_M8_E64, + 9904 => Opcode::PseudoVRGATHER_VV_M8_E64_MASK, + 9905 => Opcode::PseudoVRGATHER_VV_M8_E8, + 9906 => Opcode::PseudoVRGATHER_VV_M8_E8_MASK, + 9907 => Opcode::PseudoVRGATHER_VV_MF2_E16, + 9908 => Opcode::PseudoVRGATHER_VV_MF2_E16_MASK, + 9909 => Opcode::PseudoVRGATHER_VV_MF2_E32, + 9910 => Opcode::PseudoVRGATHER_VV_MF2_E32_MASK, + 9911 => Opcode::PseudoVRGATHER_VV_MF2_E8, + 9912 => Opcode::PseudoVRGATHER_VV_MF2_E8_MASK, + 9913 => Opcode::PseudoVRGATHER_VV_MF4_E16, + 9914 => Opcode::PseudoVRGATHER_VV_MF4_E16_MASK, + 9915 => Opcode::PseudoVRGATHER_VV_MF4_E8, + 9916 => Opcode::PseudoVRGATHER_VV_MF4_E8_MASK, + 9917 => Opcode::PseudoVRGATHER_VV_MF8_E8, + 9918 => Opcode::PseudoVRGATHER_VV_MF8_E8_MASK, + 9919 => Opcode::PseudoVRGATHER_VX_M1, + 9920 => Opcode::PseudoVRGATHER_VX_M1_MASK, + 9921 => Opcode::PseudoVRGATHER_VX_M2, + 9922 => Opcode::PseudoVRGATHER_VX_M2_MASK, + 9923 => Opcode::PseudoVRGATHER_VX_M4, + 9924 => Opcode::PseudoVRGATHER_VX_M4_MASK, + 9925 => Opcode::PseudoVRGATHER_VX_M8, + 9926 => Opcode::PseudoVRGATHER_VX_M8_MASK, + 9927 => Opcode::PseudoVRGATHER_VX_MF2, + 9928 => Opcode::PseudoVRGATHER_VX_MF2_MASK, + 9929 => Opcode::PseudoVRGATHER_VX_MF4, + 9930 => Opcode::PseudoVRGATHER_VX_MF4_MASK, + 9931 => Opcode::PseudoVRGATHER_VX_MF8, + 9932 => Opcode::PseudoVRGATHER_VX_MF8_MASK, + 9933 => Opcode::PseudoVROL_VV_M1, + 9934 => Opcode::PseudoVROL_VV_M1_MASK, + 9935 => Opcode::PseudoVROL_VV_M2, + 9936 => Opcode::PseudoVROL_VV_M2_MASK, + 9937 => Opcode::PseudoVROL_VV_M4, + 9938 => Opcode::PseudoVROL_VV_M4_MASK, + 9939 => Opcode::PseudoVROL_VV_M8, + 9940 => Opcode::PseudoVROL_VV_M8_MASK, + 9941 => Opcode::PseudoVROL_VV_MF2, + 9942 => Opcode::PseudoVROL_VV_MF2_MASK, + 9943 => Opcode::PseudoVROL_VV_MF4, + 9944 => Opcode::PseudoVROL_VV_MF4_MASK, + 9945 => Opcode::PseudoVROL_VV_MF8, + 9946 => Opcode::PseudoVROL_VV_MF8_MASK, + 9947 => Opcode::PseudoVROL_VX_M1, + 9948 => Opcode::PseudoVROL_VX_M1_MASK, + 9949 => Opcode::PseudoVROL_VX_M2, + 9950 => Opcode::PseudoVROL_VX_M2_MASK, + 9951 => Opcode::PseudoVROL_VX_M4, + 9952 => Opcode::PseudoVROL_VX_M4_MASK, + 9953 => Opcode::PseudoVROL_VX_M8, + 9954 => Opcode::PseudoVROL_VX_M8_MASK, + 9955 => Opcode::PseudoVROL_VX_MF2, + 9956 => Opcode::PseudoVROL_VX_MF2_MASK, + 9957 => Opcode::PseudoVROL_VX_MF4, + 9958 => Opcode::PseudoVROL_VX_MF4_MASK, + 9959 => Opcode::PseudoVROL_VX_MF8, + 9960 => Opcode::PseudoVROL_VX_MF8_MASK, + 9961 => Opcode::PseudoVROR_VI_M1, + 9962 => Opcode::PseudoVROR_VI_M1_MASK, + 9963 => Opcode::PseudoVROR_VI_M2, + 9964 => Opcode::PseudoVROR_VI_M2_MASK, + 9965 => Opcode::PseudoVROR_VI_M4, + 9966 => Opcode::PseudoVROR_VI_M4_MASK, + 9967 => Opcode::PseudoVROR_VI_M8, + 9968 => Opcode::PseudoVROR_VI_M8_MASK, + 9969 => Opcode::PseudoVROR_VI_MF2, + 9970 => Opcode::PseudoVROR_VI_MF2_MASK, + 9971 => Opcode::PseudoVROR_VI_MF4, + 9972 => Opcode::PseudoVROR_VI_MF4_MASK, + 9973 => Opcode::PseudoVROR_VI_MF8, + 9974 => Opcode::PseudoVROR_VI_MF8_MASK, + 9975 => Opcode::PseudoVROR_VV_M1, + 9976 => Opcode::PseudoVROR_VV_M1_MASK, + 9977 => Opcode::PseudoVROR_VV_M2, + 9978 => Opcode::PseudoVROR_VV_M2_MASK, + 9979 => Opcode::PseudoVROR_VV_M4, + 9980 => Opcode::PseudoVROR_VV_M4_MASK, + 9981 => Opcode::PseudoVROR_VV_M8, + 9982 => Opcode::PseudoVROR_VV_M8_MASK, + 9983 => Opcode::PseudoVROR_VV_MF2, + 9984 => Opcode::PseudoVROR_VV_MF2_MASK, + 9985 => Opcode::PseudoVROR_VV_MF4, + 9986 => Opcode::PseudoVROR_VV_MF4_MASK, + 9987 => Opcode::PseudoVROR_VV_MF8, + 9988 => Opcode::PseudoVROR_VV_MF8_MASK, + 9989 => Opcode::PseudoVROR_VX_M1, + 9990 => Opcode::PseudoVROR_VX_M1_MASK, + 9991 => Opcode::PseudoVROR_VX_M2, + 9992 => Opcode::PseudoVROR_VX_M2_MASK, + 9993 => Opcode::PseudoVROR_VX_M4, + 9994 => Opcode::PseudoVROR_VX_M4_MASK, + 9995 => Opcode::PseudoVROR_VX_M8, + 9996 => Opcode::PseudoVROR_VX_M8_MASK, + 9997 => Opcode::PseudoVROR_VX_MF2, + 9998 => Opcode::PseudoVROR_VX_MF2_MASK, + 9999 => Opcode::PseudoVROR_VX_MF4, + 10000 => Opcode::PseudoVROR_VX_MF4_MASK, + 10001 => Opcode::PseudoVROR_VX_MF8, + 10002 => Opcode::PseudoVROR_VX_MF8_MASK, + 10003 => Opcode::PseudoVRSUB_VI_M1, + 10004 => Opcode::PseudoVRSUB_VI_M1_MASK, + 10005 => Opcode::PseudoVRSUB_VI_M2, + 10006 => Opcode::PseudoVRSUB_VI_M2_MASK, + 10007 => Opcode::PseudoVRSUB_VI_M4, + 10008 => Opcode::PseudoVRSUB_VI_M4_MASK, + 10009 => Opcode::PseudoVRSUB_VI_M8, + 10010 => Opcode::PseudoVRSUB_VI_M8_MASK, + 10011 => Opcode::PseudoVRSUB_VI_MF2, + 10012 => Opcode::PseudoVRSUB_VI_MF2_MASK, + 10013 => Opcode::PseudoVRSUB_VI_MF4, + 10014 => Opcode::PseudoVRSUB_VI_MF4_MASK, + 10015 => Opcode::PseudoVRSUB_VI_MF8, + 10016 => Opcode::PseudoVRSUB_VI_MF8_MASK, + 10017 => Opcode::PseudoVRSUB_VX_M1, + 10018 => Opcode::PseudoVRSUB_VX_M1_MASK, + 10019 => Opcode::PseudoVRSUB_VX_M2, + 10020 => Opcode::PseudoVRSUB_VX_M2_MASK, + 10021 => Opcode::PseudoVRSUB_VX_M4, + 10022 => Opcode::PseudoVRSUB_VX_M4_MASK, + 10023 => Opcode::PseudoVRSUB_VX_M8, + 10024 => Opcode::PseudoVRSUB_VX_M8_MASK, + 10025 => Opcode::PseudoVRSUB_VX_MF2, + 10026 => Opcode::PseudoVRSUB_VX_MF2_MASK, + 10027 => Opcode::PseudoVRSUB_VX_MF4, + 10028 => Opcode::PseudoVRSUB_VX_MF4_MASK, + 10029 => Opcode::PseudoVRSUB_VX_MF8, + 10030 => Opcode::PseudoVRSUB_VX_MF8_MASK, + 10031 => Opcode::PseudoVSADDU_VI_M1, + 10032 => Opcode::PseudoVSADDU_VI_M1_MASK, + 10033 => Opcode::PseudoVSADDU_VI_M2, + 10034 => Opcode::PseudoVSADDU_VI_M2_MASK, + 10035 => Opcode::PseudoVSADDU_VI_M4, + 10036 => Opcode::PseudoVSADDU_VI_M4_MASK, + 10037 => Opcode::PseudoVSADDU_VI_M8, + 10038 => Opcode::PseudoVSADDU_VI_M8_MASK, + 10039 => Opcode::PseudoVSADDU_VI_MF2, + 10040 => Opcode::PseudoVSADDU_VI_MF2_MASK, + 10041 => Opcode::PseudoVSADDU_VI_MF4, + 10042 => Opcode::PseudoVSADDU_VI_MF4_MASK, + 10043 => Opcode::PseudoVSADDU_VI_MF8, + 10044 => Opcode::PseudoVSADDU_VI_MF8_MASK, + 10045 => Opcode::PseudoVSADDU_VV_M1, + 10046 => Opcode::PseudoVSADDU_VV_M1_MASK, + 10047 => Opcode::PseudoVSADDU_VV_M2, + 10048 => Opcode::PseudoVSADDU_VV_M2_MASK, + 10049 => Opcode::PseudoVSADDU_VV_M4, + 10050 => Opcode::PseudoVSADDU_VV_M4_MASK, + 10051 => Opcode::PseudoVSADDU_VV_M8, + 10052 => Opcode::PseudoVSADDU_VV_M8_MASK, + 10053 => Opcode::PseudoVSADDU_VV_MF2, + 10054 => Opcode::PseudoVSADDU_VV_MF2_MASK, + 10055 => Opcode::PseudoVSADDU_VV_MF4, + 10056 => Opcode::PseudoVSADDU_VV_MF4_MASK, + 10057 => Opcode::PseudoVSADDU_VV_MF8, + 10058 => Opcode::PseudoVSADDU_VV_MF8_MASK, + 10059 => Opcode::PseudoVSADDU_VX_M1, + 10060 => Opcode::PseudoVSADDU_VX_M1_MASK, + 10061 => Opcode::PseudoVSADDU_VX_M2, + 10062 => Opcode::PseudoVSADDU_VX_M2_MASK, + 10063 => Opcode::PseudoVSADDU_VX_M4, + 10064 => Opcode::PseudoVSADDU_VX_M4_MASK, + 10065 => Opcode::PseudoVSADDU_VX_M8, + 10066 => Opcode::PseudoVSADDU_VX_M8_MASK, + 10067 => Opcode::PseudoVSADDU_VX_MF2, + 10068 => Opcode::PseudoVSADDU_VX_MF2_MASK, + 10069 => Opcode::PseudoVSADDU_VX_MF4, + 10070 => Opcode::PseudoVSADDU_VX_MF4_MASK, + 10071 => Opcode::PseudoVSADDU_VX_MF8, + 10072 => Opcode::PseudoVSADDU_VX_MF8_MASK, + 10073 => Opcode::PseudoVSADD_VI_M1, + 10074 => Opcode::PseudoVSADD_VI_M1_MASK, + 10075 => Opcode::PseudoVSADD_VI_M2, + 10076 => Opcode::PseudoVSADD_VI_M2_MASK, + 10077 => Opcode::PseudoVSADD_VI_M4, + 10078 => Opcode::PseudoVSADD_VI_M4_MASK, + 10079 => Opcode::PseudoVSADD_VI_M8, + 10080 => Opcode::PseudoVSADD_VI_M8_MASK, + 10081 => Opcode::PseudoVSADD_VI_MF2, + 10082 => Opcode::PseudoVSADD_VI_MF2_MASK, + 10083 => Opcode::PseudoVSADD_VI_MF4, + 10084 => Opcode::PseudoVSADD_VI_MF4_MASK, + 10085 => Opcode::PseudoVSADD_VI_MF8, + 10086 => Opcode::PseudoVSADD_VI_MF8_MASK, + 10087 => Opcode::PseudoVSADD_VV_M1, + 10088 => Opcode::PseudoVSADD_VV_M1_MASK, + 10089 => Opcode::PseudoVSADD_VV_M2, + 10090 => Opcode::PseudoVSADD_VV_M2_MASK, + 10091 => Opcode::PseudoVSADD_VV_M4, + 10092 => Opcode::PseudoVSADD_VV_M4_MASK, + 10093 => Opcode::PseudoVSADD_VV_M8, + 10094 => Opcode::PseudoVSADD_VV_M8_MASK, + 10095 => Opcode::PseudoVSADD_VV_MF2, + 10096 => Opcode::PseudoVSADD_VV_MF2_MASK, + 10097 => Opcode::PseudoVSADD_VV_MF4, + 10098 => Opcode::PseudoVSADD_VV_MF4_MASK, + 10099 => Opcode::PseudoVSADD_VV_MF8, + 10100 => Opcode::PseudoVSADD_VV_MF8_MASK, + 10101 => Opcode::PseudoVSADD_VX_M1, + 10102 => Opcode::PseudoVSADD_VX_M1_MASK, + 10103 => Opcode::PseudoVSADD_VX_M2, + 10104 => Opcode::PseudoVSADD_VX_M2_MASK, + 10105 => Opcode::PseudoVSADD_VX_M4, + 10106 => Opcode::PseudoVSADD_VX_M4_MASK, + 10107 => Opcode::PseudoVSADD_VX_M8, + 10108 => Opcode::PseudoVSADD_VX_M8_MASK, + 10109 => Opcode::PseudoVSADD_VX_MF2, + 10110 => Opcode::PseudoVSADD_VX_MF2_MASK, + 10111 => Opcode::PseudoVSADD_VX_MF4, + 10112 => Opcode::PseudoVSADD_VX_MF4_MASK, + 10113 => Opcode::PseudoVSADD_VX_MF8, + 10114 => Opcode::PseudoVSADD_VX_MF8_MASK, + 10115 => Opcode::PseudoVSBC_VVM_M1, + 10116 => Opcode::PseudoVSBC_VVM_M2, + 10117 => Opcode::PseudoVSBC_VVM_M4, + 10118 => Opcode::PseudoVSBC_VVM_M8, + 10119 => Opcode::PseudoVSBC_VVM_MF2, + 10120 => Opcode::PseudoVSBC_VVM_MF4, + 10121 => Opcode::PseudoVSBC_VVM_MF8, + 10122 => Opcode::PseudoVSBC_VXM_M1, + 10123 => Opcode::PseudoVSBC_VXM_M2, + 10124 => Opcode::PseudoVSBC_VXM_M4, + 10125 => Opcode::PseudoVSBC_VXM_M8, + 10126 => Opcode::PseudoVSBC_VXM_MF2, + 10127 => Opcode::PseudoVSBC_VXM_MF4, + 10128 => Opcode::PseudoVSBC_VXM_MF8, + 10129 => Opcode::PseudoVSE16_V_M1, + 10130 => Opcode::PseudoVSE16_V_M1_MASK, + 10131 => Opcode::PseudoVSE16_V_M2, + 10132 => Opcode::PseudoVSE16_V_M2_MASK, + 10133 => Opcode::PseudoVSE16_V_M4, + 10134 => Opcode::PseudoVSE16_V_M4_MASK, + 10135 => Opcode::PseudoVSE16_V_M8, + 10136 => Opcode::PseudoVSE16_V_M8_MASK, + 10137 => Opcode::PseudoVSE16_V_MF2, + 10138 => Opcode::PseudoVSE16_V_MF2_MASK, + 10139 => Opcode::PseudoVSE16_V_MF4, + 10140 => Opcode::PseudoVSE16_V_MF4_MASK, + 10141 => Opcode::PseudoVSE32_V_M1, + 10142 => Opcode::PseudoVSE32_V_M1_MASK, + 10143 => Opcode::PseudoVSE32_V_M2, + 10144 => Opcode::PseudoVSE32_V_M2_MASK, + 10145 => Opcode::PseudoVSE32_V_M4, + 10146 => Opcode::PseudoVSE32_V_M4_MASK, + 10147 => Opcode::PseudoVSE32_V_M8, + 10148 => Opcode::PseudoVSE32_V_M8_MASK, + 10149 => Opcode::PseudoVSE32_V_MF2, + 10150 => Opcode::PseudoVSE32_V_MF2_MASK, + 10151 => Opcode::PseudoVSE64_V_M1, + 10152 => Opcode::PseudoVSE64_V_M1_MASK, + 10153 => Opcode::PseudoVSE64_V_M2, + 10154 => Opcode::PseudoVSE64_V_M2_MASK, + 10155 => Opcode::PseudoVSE64_V_M4, + 10156 => Opcode::PseudoVSE64_V_M4_MASK, + 10157 => Opcode::PseudoVSE64_V_M8, + 10158 => Opcode::PseudoVSE64_V_M8_MASK, + 10159 => Opcode::PseudoVSE8_V_M1, + 10160 => Opcode::PseudoVSE8_V_M1_MASK, + 10161 => Opcode::PseudoVSE8_V_M2, + 10162 => Opcode::PseudoVSE8_V_M2_MASK, + 10163 => Opcode::PseudoVSE8_V_M4, + 10164 => Opcode::PseudoVSE8_V_M4_MASK, + 10165 => Opcode::PseudoVSE8_V_M8, + 10166 => Opcode::PseudoVSE8_V_M8_MASK, + 10167 => Opcode::PseudoVSE8_V_MF2, + 10168 => Opcode::PseudoVSE8_V_MF2_MASK, + 10169 => Opcode::PseudoVSE8_V_MF4, + 10170 => Opcode::PseudoVSE8_V_MF4_MASK, + 10171 => Opcode::PseudoVSE8_V_MF8, + 10172 => Opcode::PseudoVSE8_V_MF8_MASK, + 10173 => Opcode::PseudoVSETIVLI, + 10174 => Opcode::PseudoVSETVLI, + 10175 => Opcode::PseudoVSETVLIX0, + 10176 => Opcode::PseudoVSETVLIX0X0, + 10177 => Opcode::PseudoVSEXT_VF2_M1, + 10178 => Opcode::PseudoVSEXT_VF2_M1_MASK, + 10179 => Opcode::PseudoVSEXT_VF2_M2, + 10180 => Opcode::PseudoVSEXT_VF2_M2_MASK, + 10181 => Opcode::PseudoVSEXT_VF2_M4, + 10182 => Opcode::PseudoVSEXT_VF2_M4_MASK, + 10183 => Opcode::PseudoVSEXT_VF2_M8, + 10184 => Opcode::PseudoVSEXT_VF2_M8_MASK, + 10185 => Opcode::PseudoVSEXT_VF2_MF2, + 10186 => Opcode::PseudoVSEXT_VF2_MF2_MASK, + 10187 => Opcode::PseudoVSEXT_VF2_MF4, + 10188 => Opcode::PseudoVSEXT_VF2_MF4_MASK, + 10189 => Opcode::PseudoVSEXT_VF4_M1, + 10190 => Opcode::PseudoVSEXT_VF4_M1_MASK, + 10191 => Opcode::PseudoVSEXT_VF4_M2, + 10192 => Opcode::PseudoVSEXT_VF4_M2_MASK, + 10193 => Opcode::PseudoVSEXT_VF4_M4, + 10194 => Opcode::PseudoVSEXT_VF4_M4_MASK, + 10195 => Opcode::PseudoVSEXT_VF4_M8, + 10196 => Opcode::PseudoVSEXT_VF4_M8_MASK, + 10197 => Opcode::PseudoVSEXT_VF4_MF2, + 10198 => Opcode::PseudoVSEXT_VF4_MF2_MASK, + 10199 => Opcode::PseudoVSEXT_VF8_M1, + 10200 => Opcode::PseudoVSEXT_VF8_M1_MASK, + 10201 => Opcode::PseudoVSEXT_VF8_M2, + 10202 => Opcode::PseudoVSEXT_VF8_M2_MASK, + 10203 => Opcode::PseudoVSEXT_VF8_M4, + 10204 => Opcode::PseudoVSEXT_VF8_M4_MASK, + 10205 => Opcode::PseudoVSEXT_VF8_M8, + 10206 => Opcode::PseudoVSEXT_VF8_M8_MASK, + 10207 => Opcode::PseudoVSHA2CH_VV_M1, + 10208 => Opcode::PseudoVSHA2CH_VV_M2, + 10209 => Opcode::PseudoVSHA2CH_VV_M4, + 10210 => Opcode::PseudoVSHA2CH_VV_M8, + 10211 => Opcode::PseudoVSHA2CH_VV_MF2, + 10212 => Opcode::PseudoVSHA2CL_VV_M1, + 10213 => Opcode::PseudoVSHA2CL_VV_M2, + 10214 => Opcode::PseudoVSHA2CL_VV_M4, + 10215 => Opcode::PseudoVSHA2CL_VV_M8, + 10216 => Opcode::PseudoVSHA2CL_VV_MF2, + 10217 => Opcode::PseudoVSHA2MS_VV_M1_E32, + 10218 => Opcode::PseudoVSHA2MS_VV_M1_E64, + 10219 => Opcode::PseudoVSHA2MS_VV_M2_E32, + 10220 => Opcode::PseudoVSHA2MS_VV_M2_E64, + 10221 => Opcode::PseudoVSHA2MS_VV_M4_E32, + 10222 => Opcode::PseudoVSHA2MS_VV_M4_E64, + 10223 => Opcode::PseudoVSHA2MS_VV_M8_E32, + 10224 => Opcode::PseudoVSHA2MS_VV_M8_E64, + 10225 => Opcode::PseudoVSHA2MS_VV_MF2_E32, + 10226 => Opcode::PseudoVSLIDE1DOWN_VX_M1, + 10227 => Opcode::PseudoVSLIDE1DOWN_VX_M1_MASK, + 10228 => Opcode::PseudoVSLIDE1DOWN_VX_M2, + 10229 => Opcode::PseudoVSLIDE1DOWN_VX_M2_MASK, + 10230 => Opcode::PseudoVSLIDE1DOWN_VX_M4, + 10231 => Opcode::PseudoVSLIDE1DOWN_VX_M4_MASK, + 10232 => Opcode::PseudoVSLIDE1DOWN_VX_M8, + 10233 => Opcode::PseudoVSLIDE1DOWN_VX_M8_MASK, + 10234 => Opcode::PseudoVSLIDE1DOWN_VX_MF2, + 10235 => Opcode::PseudoVSLIDE1DOWN_VX_MF2_MASK, + 10236 => Opcode::PseudoVSLIDE1DOWN_VX_MF4, + 10237 => Opcode::PseudoVSLIDE1DOWN_VX_MF4_MASK, + 10238 => Opcode::PseudoVSLIDE1DOWN_VX_MF8, + 10239 => Opcode::PseudoVSLIDE1DOWN_VX_MF8_MASK, + 10240 => Opcode::PseudoVSLIDE1UP_VX_M1, + 10241 => Opcode::PseudoVSLIDE1UP_VX_M1_MASK, + 10242 => Opcode::PseudoVSLIDE1UP_VX_M2, + 10243 => Opcode::PseudoVSLIDE1UP_VX_M2_MASK, + 10244 => Opcode::PseudoVSLIDE1UP_VX_M4, + 10245 => Opcode::PseudoVSLIDE1UP_VX_M4_MASK, + 10246 => Opcode::PseudoVSLIDE1UP_VX_M8, + 10247 => Opcode::PseudoVSLIDE1UP_VX_M8_MASK, + 10248 => Opcode::PseudoVSLIDE1UP_VX_MF2, + 10249 => Opcode::PseudoVSLIDE1UP_VX_MF2_MASK, + 10250 => Opcode::PseudoVSLIDE1UP_VX_MF4, + 10251 => Opcode::PseudoVSLIDE1UP_VX_MF4_MASK, + 10252 => Opcode::PseudoVSLIDE1UP_VX_MF8, + 10253 => Opcode::PseudoVSLIDE1UP_VX_MF8_MASK, + 10254 => Opcode::PseudoVSLIDEDOWN_VI_M1, + 10255 => Opcode::PseudoVSLIDEDOWN_VI_M1_MASK, + 10256 => Opcode::PseudoVSLIDEDOWN_VI_M2, + 10257 => Opcode::PseudoVSLIDEDOWN_VI_M2_MASK, + 10258 => Opcode::PseudoVSLIDEDOWN_VI_M4, + 10259 => Opcode::PseudoVSLIDEDOWN_VI_M4_MASK, + 10260 => Opcode::PseudoVSLIDEDOWN_VI_M8, + 10261 => Opcode::PseudoVSLIDEDOWN_VI_M8_MASK, + 10262 => Opcode::PseudoVSLIDEDOWN_VI_MF2, + 10263 => Opcode::PseudoVSLIDEDOWN_VI_MF2_MASK, + 10264 => Opcode::PseudoVSLIDEDOWN_VI_MF4, + 10265 => Opcode::PseudoVSLIDEDOWN_VI_MF4_MASK, + 10266 => Opcode::PseudoVSLIDEDOWN_VI_MF8, + 10267 => Opcode::PseudoVSLIDEDOWN_VI_MF8_MASK, + 10268 => Opcode::PseudoVSLIDEDOWN_VX_M1, + 10269 => Opcode::PseudoVSLIDEDOWN_VX_M1_MASK, + 10270 => Opcode::PseudoVSLIDEDOWN_VX_M2, + 10271 => Opcode::PseudoVSLIDEDOWN_VX_M2_MASK, + 10272 => Opcode::PseudoVSLIDEDOWN_VX_M4, + 10273 => Opcode::PseudoVSLIDEDOWN_VX_M4_MASK, + 10274 => Opcode::PseudoVSLIDEDOWN_VX_M8, + 10275 => Opcode::PseudoVSLIDEDOWN_VX_M8_MASK, + 10276 => Opcode::PseudoVSLIDEDOWN_VX_MF2, + 10277 => Opcode::PseudoVSLIDEDOWN_VX_MF2_MASK, + 10278 => Opcode::PseudoVSLIDEDOWN_VX_MF4, + 10279 => Opcode::PseudoVSLIDEDOWN_VX_MF4_MASK, + 10280 => Opcode::PseudoVSLIDEDOWN_VX_MF8, + 10281 => Opcode::PseudoVSLIDEDOWN_VX_MF8_MASK, + 10282 => Opcode::PseudoVSLIDEUP_VI_M1, + 10283 => Opcode::PseudoVSLIDEUP_VI_M1_MASK, + 10284 => Opcode::PseudoVSLIDEUP_VI_M2, + 10285 => Opcode::PseudoVSLIDEUP_VI_M2_MASK, + 10286 => Opcode::PseudoVSLIDEUP_VI_M4, + 10287 => Opcode::PseudoVSLIDEUP_VI_M4_MASK, + 10288 => Opcode::PseudoVSLIDEUP_VI_M8, + 10289 => Opcode::PseudoVSLIDEUP_VI_M8_MASK, + 10290 => Opcode::PseudoVSLIDEUP_VI_MF2, + 10291 => Opcode::PseudoVSLIDEUP_VI_MF2_MASK, + 10292 => Opcode::PseudoVSLIDEUP_VI_MF4, + 10293 => Opcode::PseudoVSLIDEUP_VI_MF4_MASK, + 10294 => Opcode::PseudoVSLIDEUP_VI_MF8, + 10295 => Opcode::PseudoVSLIDEUP_VI_MF8_MASK, + 10296 => Opcode::PseudoVSLIDEUP_VX_M1, + 10297 => Opcode::PseudoVSLIDEUP_VX_M1_MASK, + 10298 => Opcode::PseudoVSLIDEUP_VX_M2, + 10299 => Opcode::PseudoVSLIDEUP_VX_M2_MASK, + 10300 => Opcode::PseudoVSLIDEUP_VX_M4, + 10301 => Opcode::PseudoVSLIDEUP_VX_M4_MASK, + 10302 => Opcode::PseudoVSLIDEUP_VX_M8, + 10303 => Opcode::PseudoVSLIDEUP_VX_M8_MASK, + 10304 => Opcode::PseudoVSLIDEUP_VX_MF2, + 10305 => Opcode::PseudoVSLIDEUP_VX_MF2_MASK, + 10306 => Opcode::PseudoVSLIDEUP_VX_MF4, + 10307 => Opcode::PseudoVSLIDEUP_VX_MF4_MASK, + 10308 => Opcode::PseudoVSLIDEUP_VX_MF8, + 10309 => Opcode::PseudoVSLIDEUP_VX_MF8_MASK, + 10310 => Opcode::PseudoVSLL_VI_M1, + 10311 => Opcode::PseudoVSLL_VI_M1_MASK, + 10312 => Opcode::PseudoVSLL_VI_M2, + 10313 => Opcode::PseudoVSLL_VI_M2_MASK, + 10314 => Opcode::PseudoVSLL_VI_M4, + 10315 => Opcode::PseudoVSLL_VI_M4_MASK, + 10316 => Opcode::PseudoVSLL_VI_M8, + 10317 => Opcode::PseudoVSLL_VI_M8_MASK, + 10318 => Opcode::PseudoVSLL_VI_MF2, + 10319 => Opcode::PseudoVSLL_VI_MF2_MASK, + 10320 => Opcode::PseudoVSLL_VI_MF4, + 10321 => Opcode::PseudoVSLL_VI_MF4_MASK, + 10322 => Opcode::PseudoVSLL_VI_MF8, + 10323 => Opcode::PseudoVSLL_VI_MF8_MASK, + 10324 => Opcode::PseudoVSLL_VV_M1, + 10325 => Opcode::PseudoVSLL_VV_M1_MASK, + 10326 => Opcode::PseudoVSLL_VV_M2, + 10327 => Opcode::PseudoVSLL_VV_M2_MASK, + 10328 => Opcode::PseudoVSLL_VV_M4, + 10329 => Opcode::PseudoVSLL_VV_M4_MASK, + 10330 => Opcode::PseudoVSLL_VV_M8, + 10331 => Opcode::PseudoVSLL_VV_M8_MASK, + 10332 => Opcode::PseudoVSLL_VV_MF2, + 10333 => Opcode::PseudoVSLL_VV_MF2_MASK, + 10334 => Opcode::PseudoVSLL_VV_MF4, + 10335 => Opcode::PseudoVSLL_VV_MF4_MASK, + 10336 => Opcode::PseudoVSLL_VV_MF8, + 10337 => Opcode::PseudoVSLL_VV_MF8_MASK, + 10338 => Opcode::PseudoVSLL_VX_M1, + 10339 => Opcode::PseudoVSLL_VX_M1_MASK, + 10340 => Opcode::PseudoVSLL_VX_M2, + 10341 => Opcode::PseudoVSLL_VX_M2_MASK, + 10342 => Opcode::PseudoVSLL_VX_M4, + 10343 => Opcode::PseudoVSLL_VX_M4_MASK, + 10344 => Opcode::PseudoVSLL_VX_M8, + 10345 => Opcode::PseudoVSLL_VX_M8_MASK, + 10346 => Opcode::PseudoVSLL_VX_MF2, + 10347 => Opcode::PseudoVSLL_VX_MF2_MASK, + 10348 => Opcode::PseudoVSLL_VX_MF4, + 10349 => Opcode::PseudoVSLL_VX_MF4_MASK, + 10350 => Opcode::PseudoVSLL_VX_MF8, + 10351 => Opcode::PseudoVSLL_VX_MF8_MASK, + 10352 => Opcode::PseudoVSM3C_VI_M1, + 10353 => Opcode::PseudoVSM3C_VI_M2, + 10354 => Opcode::PseudoVSM3C_VI_M4, + 10355 => Opcode::PseudoVSM3C_VI_M8, + 10356 => Opcode::PseudoVSM3C_VI_MF2, + 10357 => Opcode::PseudoVSM3ME_VV_M1, + 10358 => Opcode::PseudoVSM3ME_VV_M2, + 10359 => Opcode::PseudoVSM3ME_VV_M4, + 10360 => Opcode::PseudoVSM3ME_VV_M8, + 10361 => Opcode::PseudoVSM3ME_VV_MF2, + 10362 => Opcode::PseudoVSM4K_VI_M1, + 10363 => Opcode::PseudoVSM4K_VI_M2, + 10364 => Opcode::PseudoVSM4K_VI_M4, + 10365 => Opcode::PseudoVSM4K_VI_M8, + 10366 => Opcode::PseudoVSM4K_VI_MF2, + 10367 => Opcode::PseudoVSM4R_VS_M1_M1, + 10368 => Opcode::PseudoVSM4R_VS_M1_MF2, + 10369 => Opcode::PseudoVSM4R_VS_M1_MF4, + 10370 => Opcode::PseudoVSM4R_VS_M1_MF8, + 10371 => Opcode::PseudoVSM4R_VS_M2_M1, + 10372 => Opcode::PseudoVSM4R_VS_M2_M2, + 10373 => Opcode::PseudoVSM4R_VS_M2_MF2, + 10374 => Opcode::PseudoVSM4R_VS_M2_MF4, + 10375 => Opcode::PseudoVSM4R_VS_M2_MF8, + 10376 => Opcode::PseudoVSM4R_VS_M4_M1, + 10377 => Opcode::PseudoVSM4R_VS_M4_M2, + 10378 => Opcode::PseudoVSM4R_VS_M4_M4, + 10379 => Opcode::PseudoVSM4R_VS_M4_MF2, + 10380 => Opcode::PseudoVSM4R_VS_M4_MF4, + 10381 => Opcode::PseudoVSM4R_VS_M4_MF8, + 10382 => Opcode::PseudoVSM4R_VS_M8_M1, + 10383 => Opcode::PseudoVSM4R_VS_M8_M2, + 10384 => Opcode::PseudoVSM4R_VS_M8_M4, + 10385 => Opcode::PseudoVSM4R_VS_M8_MF2, + 10386 => Opcode::PseudoVSM4R_VS_M8_MF4, + 10387 => Opcode::PseudoVSM4R_VS_M8_MF8, + 10388 => Opcode::PseudoVSM4R_VS_MF2_MF2, + 10389 => Opcode::PseudoVSM4R_VS_MF2_MF4, + 10390 => Opcode::PseudoVSM4R_VS_MF2_MF8, + 10391 => Opcode::PseudoVSM4R_VV_M1, + 10392 => Opcode::PseudoVSM4R_VV_M2, + 10393 => Opcode::PseudoVSM4R_VV_M4, + 10394 => Opcode::PseudoVSM4R_VV_M8, + 10395 => Opcode::PseudoVSM4R_VV_MF2, + 10396 => Opcode::PseudoVSMUL_VV_M1, + 10397 => Opcode::PseudoVSMUL_VV_M1_MASK, + 10398 => Opcode::PseudoVSMUL_VV_M2, + 10399 => Opcode::PseudoVSMUL_VV_M2_MASK, + 10400 => Opcode::PseudoVSMUL_VV_M4, + 10401 => Opcode::PseudoVSMUL_VV_M4_MASK, + 10402 => Opcode::PseudoVSMUL_VV_M8, + 10403 => Opcode::PseudoVSMUL_VV_M8_MASK, + 10404 => Opcode::PseudoVSMUL_VV_MF2, + 10405 => Opcode::PseudoVSMUL_VV_MF2_MASK, + 10406 => Opcode::PseudoVSMUL_VV_MF4, + 10407 => Opcode::PseudoVSMUL_VV_MF4_MASK, + 10408 => Opcode::PseudoVSMUL_VV_MF8, + 10409 => Opcode::PseudoVSMUL_VV_MF8_MASK, + 10410 => Opcode::PseudoVSMUL_VX_M1, + 10411 => Opcode::PseudoVSMUL_VX_M1_MASK, + 10412 => Opcode::PseudoVSMUL_VX_M2, + 10413 => Opcode::PseudoVSMUL_VX_M2_MASK, + 10414 => Opcode::PseudoVSMUL_VX_M4, + 10415 => Opcode::PseudoVSMUL_VX_M4_MASK, + 10416 => Opcode::PseudoVSMUL_VX_M8, + 10417 => Opcode::PseudoVSMUL_VX_M8_MASK, + 10418 => Opcode::PseudoVSMUL_VX_MF2, + 10419 => Opcode::PseudoVSMUL_VX_MF2_MASK, + 10420 => Opcode::PseudoVSMUL_VX_MF4, + 10421 => Opcode::PseudoVSMUL_VX_MF4_MASK, + 10422 => Opcode::PseudoVSMUL_VX_MF8, + 10423 => Opcode::PseudoVSMUL_VX_MF8_MASK, + 10424 => Opcode::PseudoVSM_V_B1, + 10425 => Opcode::PseudoVSM_V_B16, + 10426 => Opcode::PseudoVSM_V_B2, + 10427 => Opcode::PseudoVSM_V_B32, + 10428 => Opcode::PseudoVSM_V_B4, + 10429 => Opcode::PseudoVSM_V_B64, + 10430 => Opcode::PseudoVSM_V_B8, + 10431 => Opcode::PseudoVSOXEI16_V_M1_M1, + 10432 => Opcode::PseudoVSOXEI16_V_M1_M1_MASK, + 10433 => Opcode::PseudoVSOXEI16_V_M1_M2, + 10434 => Opcode::PseudoVSOXEI16_V_M1_M2_MASK, + 10435 => Opcode::PseudoVSOXEI16_V_M1_M4, + 10436 => Opcode::PseudoVSOXEI16_V_M1_M4_MASK, + 10437 => Opcode::PseudoVSOXEI16_V_M1_MF2, + 10438 => Opcode::PseudoVSOXEI16_V_M1_MF2_MASK, + 10439 => Opcode::PseudoVSOXEI16_V_M2_M1, + 10440 => Opcode::PseudoVSOXEI16_V_M2_M1_MASK, + 10441 => Opcode::PseudoVSOXEI16_V_M2_M2, + 10442 => Opcode::PseudoVSOXEI16_V_M2_M2_MASK, + 10443 => Opcode::PseudoVSOXEI16_V_M2_M4, + 10444 => Opcode::PseudoVSOXEI16_V_M2_M4_MASK, + 10445 => Opcode::PseudoVSOXEI16_V_M2_M8, + 10446 => Opcode::PseudoVSOXEI16_V_M2_M8_MASK, + 10447 => Opcode::PseudoVSOXEI16_V_M4_M2, + 10448 => Opcode::PseudoVSOXEI16_V_M4_M2_MASK, + 10449 => Opcode::PseudoVSOXEI16_V_M4_M4, + 10450 => Opcode::PseudoVSOXEI16_V_M4_M4_MASK, + 10451 => Opcode::PseudoVSOXEI16_V_M4_M8, + 10452 => Opcode::PseudoVSOXEI16_V_M4_M8_MASK, + 10453 => Opcode::PseudoVSOXEI16_V_M8_M4, + 10454 => Opcode::PseudoVSOXEI16_V_M8_M4_MASK, + 10455 => Opcode::PseudoVSOXEI16_V_M8_M8, + 10456 => Opcode::PseudoVSOXEI16_V_M8_M8_MASK, + 10457 => Opcode::PseudoVSOXEI16_V_MF2_M1, + 10458 => Opcode::PseudoVSOXEI16_V_MF2_M1_MASK, + 10459 => Opcode::PseudoVSOXEI16_V_MF2_M2, + 10460 => Opcode::PseudoVSOXEI16_V_MF2_M2_MASK, + 10461 => Opcode::PseudoVSOXEI16_V_MF2_MF2, + 10462 => Opcode::PseudoVSOXEI16_V_MF2_MF2_MASK, + 10463 => Opcode::PseudoVSOXEI16_V_MF2_MF4, + 10464 => Opcode::PseudoVSOXEI16_V_MF2_MF4_MASK, + 10465 => Opcode::PseudoVSOXEI16_V_MF4_M1, + 10466 => Opcode::PseudoVSOXEI16_V_MF4_M1_MASK, + 10467 => Opcode::PseudoVSOXEI16_V_MF4_MF2, + 10468 => Opcode::PseudoVSOXEI16_V_MF4_MF2_MASK, + 10469 => Opcode::PseudoVSOXEI16_V_MF4_MF4, + 10470 => Opcode::PseudoVSOXEI16_V_MF4_MF4_MASK, + 10471 => Opcode::PseudoVSOXEI16_V_MF4_MF8, + 10472 => Opcode::PseudoVSOXEI16_V_MF4_MF8_MASK, + 10473 => Opcode::PseudoVSOXEI32_V_M1_M1, + 10474 => Opcode::PseudoVSOXEI32_V_M1_M1_MASK, + 10475 => Opcode::PseudoVSOXEI32_V_M1_M2, + 10476 => Opcode::PseudoVSOXEI32_V_M1_M2_MASK, + 10477 => Opcode::PseudoVSOXEI32_V_M1_MF2, + 10478 => Opcode::PseudoVSOXEI32_V_M1_MF2_MASK, + 10479 => Opcode::PseudoVSOXEI32_V_M1_MF4, + 10480 => Opcode::PseudoVSOXEI32_V_M1_MF4_MASK, + 10481 => Opcode::PseudoVSOXEI32_V_M2_M1, + 10482 => Opcode::PseudoVSOXEI32_V_M2_M1_MASK, + 10483 => Opcode::PseudoVSOXEI32_V_M2_M2, + 10484 => Opcode::PseudoVSOXEI32_V_M2_M2_MASK, + 10485 => Opcode::PseudoVSOXEI32_V_M2_M4, + 10486 => Opcode::PseudoVSOXEI32_V_M2_M4_MASK, + 10487 => Opcode::PseudoVSOXEI32_V_M2_MF2, + 10488 => Opcode::PseudoVSOXEI32_V_M2_MF2_MASK, + 10489 => Opcode::PseudoVSOXEI32_V_M4_M1, + 10490 => Opcode::PseudoVSOXEI32_V_M4_M1_MASK, + 10491 => Opcode::PseudoVSOXEI32_V_M4_M2, + 10492 => Opcode::PseudoVSOXEI32_V_M4_M2_MASK, + 10493 => Opcode::PseudoVSOXEI32_V_M4_M4, + 10494 => Opcode::PseudoVSOXEI32_V_M4_M4_MASK, + 10495 => Opcode::PseudoVSOXEI32_V_M4_M8, + 10496 => Opcode::PseudoVSOXEI32_V_M4_M8_MASK, + 10497 => Opcode::PseudoVSOXEI32_V_M8_M2, + 10498 => Opcode::PseudoVSOXEI32_V_M8_M2_MASK, + 10499 => Opcode::PseudoVSOXEI32_V_M8_M4, + 10500 => Opcode::PseudoVSOXEI32_V_M8_M4_MASK, + 10501 => Opcode::PseudoVSOXEI32_V_M8_M8, + 10502 => Opcode::PseudoVSOXEI32_V_M8_M8_MASK, + 10503 => Opcode::PseudoVSOXEI32_V_MF2_M1, + 10504 => Opcode::PseudoVSOXEI32_V_MF2_M1_MASK, + 10505 => Opcode::PseudoVSOXEI32_V_MF2_MF2, + 10506 => Opcode::PseudoVSOXEI32_V_MF2_MF2_MASK, + 10507 => Opcode::PseudoVSOXEI32_V_MF2_MF4, + 10508 => Opcode::PseudoVSOXEI32_V_MF2_MF4_MASK, + 10509 => Opcode::PseudoVSOXEI32_V_MF2_MF8, + 10510 => Opcode::PseudoVSOXEI32_V_MF2_MF8_MASK, + 10511 => Opcode::PseudoVSOXEI64_V_M1_M1, + 10512 => Opcode::PseudoVSOXEI64_V_M1_M1_MASK, + 10513 => Opcode::PseudoVSOXEI64_V_M1_MF2, + 10514 => Opcode::PseudoVSOXEI64_V_M1_MF2_MASK, + 10515 => Opcode::PseudoVSOXEI64_V_M1_MF4, + 10516 => Opcode::PseudoVSOXEI64_V_M1_MF4_MASK, + 10517 => Opcode::PseudoVSOXEI64_V_M1_MF8, + 10518 => Opcode::PseudoVSOXEI64_V_M1_MF8_MASK, + 10519 => Opcode::PseudoVSOXEI64_V_M2_M1, + 10520 => Opcode::PseudoVSOXEI64_V_M2_M1_MASK, + 10521 => Opcode::PseudoVSOXEI64_V_M2_M2, + 10522 => Opcode::PseudoVSOXEI64_V_M2_M2_MASK, + 10523 => Opcode::PseudoVSOXEI64_V_M2_MF2, + 10524 => Opcode::PseudoVSOXEI64_V_M2_MF2_MASK, + 10525 => Opcode::PseudoVSOXEI64_V_M2_MF4, + 10526 => Opcode::PseudoVSOXEI64_V_M2_MF4_MASK, + 10527 => Opcode::PseudoVSOXEI64_V_M4_M1, + 10528 => Opcode::PseudoVSOXEI64_V_M4_M1_MASK, + 10529 => Opcode::PseudoVSOXEI64_V_M4_M2, + 10530 => Opcode::PseudoVSOXEI64_V_M4_M2_MASK, + 10531 => Opcode::PseudoVSOXEI64_V_M4_M4, + 10532 => Opcode::PseudoVSOXEI64_V_M4_M4_MASK, + 10533 => Opcode::PseudoVSOXEI64_V_M4_MF2, + 10534 => Opcode::PseudoVSOXEI64_V_M4_MF2_MASK, + 10535 => Opcode::PseudoVSOXEI64_V_M8_M1, + 10536 => Opcode::PseudoVSOXEI64_V_M8_M1_MASK, + 10537 => Opcode::PseudoVSOXEI64_V_M8_M2, + 10538 => Opcode::PseudoVSOXEI64_V_M8_M2_MASK, + 10539 => Opcode::PseudoVSOXEI64_V_M8_M4, + 10540 => Opcode::PseudoVSOXEI64_V_M8_M4_MASK, + 10541 => Opcode::PseudoVSOXEI64_V_M8_M8, + 10542 => Opcode::PseudoVSOXEI64_V_M8_M8_MASK, + 10543 => Opcode::PseudoVSOXEI8_V_M1_M1, + 10544 => Opcode::PseudoVSOXEI8_V_M1_M1_MASK, + 10545 => Opcode::PseudoVSOXEI8_V_M1_M2, + 10546 => Opcode::PseudoVSOXEI8_V_M1_M2_MASK, + 10547 => Opcode::PseudoVSOXEI8_V_M1_M4, + 10548 => Opcode::PseudoVSOXEI8_V_M1_M4_MASK, + 10549 => Opcode::PseudoVSOXEI8_V_M1_M8, + 10550 => Opcode::PseudoVSOXEI8_V_M1_M8_MASK, + 10551 => Opcode::PseudoVSOXEI8_V_M2_M2, + 10552 => Opcode::PseudoVSOXEI8_V_M2_M2_MASK, + 10553 => Opcode::PseudoVSOXEI8_V_M2_M4, + 10554 => Opcode::PseudoVSOXEI8_V_M2_M4_MASK, + 10555 => Opcode::PseudoVSOXEI8_V_M2_M8, + 10556 => Opcode::PseudoVSOXEI8_V_M2_M8_MASK, + 10557 => Opcode::PseudoVSOXEI8_V_M4_M4, + 10558 => Opcode::PseudoVSOXEI8_V_M4_M4_MASK, + 10559 => Opcode::PseudoVSOXEI8_V_M4_M8, + 10560 => Opcode::PseudoVSOXEI8_V_M4_M8_MASK, + 10561 => Opcode::PseudoVSOXEI8_V_M8_M8, + 10562 => Opcode::PseudoVSOXEI8_V_M8_M8_MASK, + 10563 => Opcode::PseudoVSOXEI8_V_MF2_M1, + 10564 => Opcode::PseudoVSOXEI8_V_MF2_M1_MASK, + 10565 => Opcode::PseudoVSOXEI8_V_MF2_M2, + 10566 => Opcode::PseudoVSOXEI8_V_MF2_M2_MASK, + 10567 => Opcode::PseudoVSOXEI8_V_MF2_M4, + 10568 => Opcode::PseudoVSOXEI8_V_MF2_M4_MASK, + 10569 => Opcode::PseudoVSOXEI8_V_MF2_MF2, + 10570 => Opcode::PseudoVSOXEI8_V_MF2_MF2_MASK, + 10571 => Opcode::PseudoVSOXEI8_V_MF4_M1, + 10572 => Opcode::PseudoVSOXEI8_V_MF4_M1_MASK, + 10573 => Opcode::PseudoVSOXEI8_V_MF4_M2, + 10574 => Opcode::PseudoVSOXEI8_V_MF4_M2_MASK, + 10575 => Opcode::PseudoVSOXEI8_V_MF4_MF2, + 10576 => Opcode::PseudoVSOXEI8_V_MF4_MF2_MASK, + 10577 => Opcode::PseudoVSOXEI8_V_MF4_MF4, + 10578 => Opcode::PseudoVSOXEI8_V_MF4_MF4_MASK, + 10579 => Opcode::PseudoVSOXEI8_V_MF8_M1, + 10580 => Opcode::PseudoVSOXEI8_V_MF8_M1_MASK, + 10581 => Opcode::PseudoVSOXEI8_V_MF8_MF2, + 10582 => Opcode::PseudoVSOXEI8_V_MF8_MF2_MASK, + 10583 => Opcode::PseudoVSOXEI8_V_MF8_MF4, + 10584 => Opcode::PseudoVSOXEI8_V_MF8_MF4_MASK, + 10585 => Opcode::PseudoVSOXEI8_V_MF8_MF8, + 10586 => Opcode::PseudoVSOXEI8_V_MF8_MF8_MASK, + 10587 => Opcode::PseudoVSOXSEG2EI16_V_M1_M1, + 10588 => Opcode::PseudoVSOXSEG2EI16_V_M1_M1_MASK, + 10589 => Opcode::PseudoVSOXSEG2EI16_V_M1_M2, + 10590 => Opcode::PseudoVSOXSEG2EI16_V_M1_M2_MASK, + 10591 => Opcode::PseudoVSOXSEG2EI16_V_M1_M4, + 10592 => Opcode::PseudoVSOXSEG2EI16_V_M1_M4_MASK, + 10593 => Opcode::PseudoVSOXSEG2EI16_V_M1_MF2, + 10594 => Opcode::PseudoVSOXSEG2EI16_V_M1_MF2_MASK, + 10595 => Opcode::PseudoVSOXSEG2EI16_V_M2_M1, + 10596 => Opcode::PseudoVSOXSEG2EI16_V_M2_M1_MASK, + 10597 => Opcode::PseudoVSOXSEG2EI16_V_M2_M2, + 10598 => Opcode::PseudoVSOXSEG2EI16_V_M2_M2_MASK, + 10599 => Opcode::PseudoVSOXSEG2EI16_V_M2_M4, + 10600 => Opcode::PseudoVSOXSEG2EI16_V_M2_M4_MASK, + 10601 => Opcode::PseudoVSOXSEG2EI16_V_M4_M2, + 10602 => Opcode::PseudoVSOXSEG2EI16_V_M4_M2_MASK, + 10603 => Opcode::PseudoVSOXSEG2EI16_V_M4_M4, + 10604 => Opcode::PseudoVSOXSEG2EI16_V_M4_M4_MASK, + 10605 => Opcode::PseudoVSOXSEG2EI16_V_M8_M4, + 10606 => Opcode::PseudoVSOXSEG2EI16_V_M8_M4_MASK, + 10607 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M1, + 10608 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M1_MASK, + 10609 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M2, + 10610 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M2_MASK, + 10611 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF2, + 10612 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, + 10613 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF4, + 10614 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, + 10615 => Opcode::PseudoVSOXSEG2EI16_V_MF4_M1, + 10616 => Opcode::PseudoVSOXSEG2EI16_V_MF4_M1_MASK, + 10617 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF2, + 10618 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, + 10619 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF4, + 10620 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, + 10621 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF8, + 10622 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, + 10623 => Opcode::PseudoVSOXSEG2EI32_V_M1_M1, + 10624 => Opcode::PseudoVSOXSEG2EI32_V_M1_M1_MASK, + 10625 => Opcode::PseudoVSOXSEG2EI32_V_M1_M2, + 10626 => Opcode::PseudoVSOXSEG2EI32_V_M1_M2_MASK, + 10627 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF2, + 10628 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF2_MASK, + 10629 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF4, + 10630 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF4_MASK, + 10631 => Opcode::PseudoVSOXSEG2EI32_V_M2_M1, + 10632 => Opcode::PseudoVSOXSEG2EI32_V_M2_M1_MASK, + 10633 => Opcode::PseudoVSOXSEG2EI32_V_M2_M2, + 10634 => Opcode::PseudoVSOXSEG2EI32_V_M2_M2_MASK, + 10635 => Opcode::PseudoVSOXSEG2EI32_V_M2_M4, + 10636 => Opcode::PseudoVSOXSEG2EI32_V_M2_M4_MASK, + 10637 => Opcode::PseudoVSOXSEG2EI32_V_M2_MF2, + 10638 => Opcode::PseudoVSOXSEG2EI32_V_M2_MF2_MASK, + 10639 => Opcode::PseudoVSOXSEG2EI32_V_M4_M1, + 10640 => Opcode::PseudoVSOXSEG2EI32_V_M4_M1_MASK, + 10641 => Opcode::PseudoVSOXSEG2EI32_V_M4_M2, + 10642 => Opcode::PseudoVSOXSEG2EI32_V_M4_M2_MASK, + 10643 => Opcode::PseudoVSOXSEG2EI32_V_M4_M4, + 10644 => Opcode::PseudoVSOXSEG2EI32_V_M4_M4_MASK, + 10645 => Opcode::PseudoVSOXSEG2EI32_V_M8_M2, + 10646 => Opcode::PseudoVSOXSEG2EI32_V_M8_M2_MASK, + 10647 => Opcode::PseudoVSOXSEG2EI32_V_M8_M4, + 10648 => Opcode::PseudoVSOXSEG2EI32_V_M8_M4_MASK, + 10649 => Opcode::PseudoVSOXSEG2EI32_V_MF2_M1, + 10650 => Opcode::PseudoVSOXSEG2EI32_V_MF2_M1_MASK, + 10651 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF2, + 10652 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, + 10653 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF4, + 10654 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, + 10655 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF8, + 10656 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, + 10657 => Opcode::PseudoVSOXSEG2EI64_V_M1_M1, + 10658 => Opcode::PseudoVSOXSEG2EI64_V_M1_M1_MASK, + 10659 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF2, + 10660 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF2_MASK, + 10661 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF4, + 10662 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF4_MASK, + 10663 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF8, + 10664 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF8_MASK, + 10665 => Opcode::PseudoVSOXSEG2EI64_V_M2_M1, + 10666 => Opcode::PseudoVSOXSEG2EI64_V_M2_M1_MASK, + 10667 => Opcode::PseudoVSOXSEG2EI64_V_M2_M2, + 10668 => Opcode::PseudoVSOXSEG2EI64_V_M2_M2_MASK, + 10669 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF2, + 10670 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF2_MASK, + 10671 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF4, + 10672 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF4_MASK, + 10673 => Opcode::PseudoVSOXSEG2EI64_V_M4_M1, + 10674 => Opcode::PseudoVSOXSEG2EI64_V_M4_M1_MASK, + 10675 => Opcode::PseudoVSOXSEG2EI64_V_M4_M2, + 10676 => Opcode::PseudoVSOXSEG2EI64_V_M4_M2_MASK, + 10677 => Opcode::PseudoVSOXSEG2EI64_V_M4_M4, + 10678 => Opcode::PseudoVSOXSEG2EI64_V_M4_M4_MASK, + 10679 => Opcode::PseudoVSOXSEG2EI64_V_M4_MF2, + 10680 => Opcode::PseudoVSOXSEG2EI64_V_M4_MF2_MASK, + 10681 => Opcode::PseudoVSOXSEG2EI64_V_M8_M1, + 10682 => Opcode::PseudoVSOXSEG2EI64_V_M8_M1_MASK, + 10683 => Opcode::PseudoVSOXSEG2EI64_V_M8_M2, + 10684 => Opcode::PseudoVSOXSEG2EI64_V_M8_M2_MASK, + 10685 => Opcode::PseudoVSOXSEG2EI64_V_M8_M4, + 10686 => Opcode::PseudoVSOXSEG2EI64_V_M8_M4_MASK, + 10687 => Opcode::PseudoVSOXSEG2EI8_V_M1_M1, + 10688 => Opcode::PseudoVSOXSEG2EI8_V_M1_M1_MASK, + 10689 => Opcode::PseudoVSOXSEG2EI8_V_M1_M2, + 10690 => Opcode::PseudoVSOXSEG2EI8_V_M1_M2_MASK, + 10691 => Opcode::PseudoVSOXSEG2EI8_V_M1_M4, + 10692 => Opcode::PseudoVSOXSEG2EI8_V_M1_M4_MASK, + 10693 => Opcode::PseudoVSOXSEG2EI8_V_M2_M2, + 10694 => Opcode::PseudoVSOXSEG2EI8_V_M2_M2_MASK, + 10695 => Opcode::PseudoVSOXSEG2EI8_V_M2_M4, + 10696 => Opcode::PseudoVSOXSEG2EI8_V_M2_M4_MASK, + 10697 => Opcode::PseudoVSOXSEG2EI8_V_M4_M4, + 10698 => Opcode::PseudoVSOXSEG2EI8_V_M4_M4_MASK, + 10699 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M1, + 10700 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M1_MASK, + 10701 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M2, + 10702 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M2_MASK, + 10703 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M4, + 10704 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M4_MASK, + 10705 => Opcode::PseudoVSOXSEG2EI8_V_MF2_MF2, + 10706 => Opcode::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, + 10707 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M1, + 10708 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M1_MASK, + 10709 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M2, + 10710 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M2_MASK, + 10711 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF2, + 10712 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, + 10713 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF4, + 10714 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, + 10715 => Opcode::PseudoVSOXSEG2EI8_V_MF8_M1, + 10716 => Opcode::PseudoVSOXSEG2EI8_V_MF8_M1_MASK, + 10717 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF2, + 10718 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, + 10719 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF4, + 10720 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, + 10721 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF8, + 10722 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, + 10723 => Opcode::PseudoVSOXSEG3EI16_V_M1_M1, + 10724 => Opcode::PseudoVSOXSEG3EI16_V_M1_M1_MASK, + 10725 => Opcode::PseudoVSOXSEG3EI16_V_M1_M2, + 10726 => Opcode::PseudoVSOXSEG3EI16_V_M1_M2_MASK, + 10727 => Opcode::PseudoVSOXSEG3EI16_V_M1_MF2, + 10728 => Opcode::PseudoVSOXSEG3EI16_V_M1_MF2_MASK, + 10729 => Opcode::PseudoVSOXSEG3EI16_V_M2_M1, + 10730 => Opcode::PseudoVSOXSEG3EI16_V_M2_M1_MASK, + 10731 => Opcode::PseudoVSOXSEG3EI16_V_M2_M2, + 10732 => Opcode::PseudoVSOXSEG3EI16_V_M2_M2_MASK, + 10733 => Opcode::PseudoVSOXSEG3EI16_V_M4_M2, + 10734 => Opcode::PseudoVSOXSEG3EI16_V_M4_M2_MASK, + 10735 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M1, + 10736 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M1_MASK, + 10737 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M2, + 10738 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M2_MASK, + 10739 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF2, + 10740 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, + 10741 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF4, + 10742 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, + 10743 => Opcode::PseudoVSOXSEG3EI16_V_MF4_M1, + 10744 => Opcode::PseudoVSOXSEG3EI16_V_MF4_M1_MASK, + 10745 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF2, + 10746 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, + 10747 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF4, + 10748 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, + 10749 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF8, + 10750 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, + 10751 => Opcode::PseudoVSOXSEG3EI32_V_M1_M1, + 10752 => Opcode::PseudoVSOXSEG3EI32_V_M1_M1_MASK, + 10753 => Opcode::PseudoVSOXSEG3EI32_V_M1_M2, + 10754 => Opcode::PseudoVSOXSEG3EI32_V_M1_M2_MASK, + 10755 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF2, + 10756 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF2_MASK, + 10757 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF4, + 10758 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF4_MASK, + 10759 => Opcode::PseudoVSOXSEG3EI32_V_M2_M1, + 10760 => Opcode::PseudoVSOXSEG3EI32_V_M2_M1_MASK, + 10761 => Opcode::PseudoVSOXSEG3EI32_V_M2_M2, + 10762 => Opcode::PseudoVSOXSEG3EI32_V_M2_M2_MASK, + 10763 => Opcode::PseudoVSOXSEG3EI32_V_M2_MF2, + 10764 => Opcode::PseudoVSOXSEG3EI32_V_M2_MF2_MASK, + 10765 => Opcode::PseudoVSOXSEG3EI32_V_M4_M1, + 10766 => Opcode::PseudoVSOXSEG3EI32_V_M4_M1_MASK, + 10767 => Opcode::PseudoVSOXSEG3EI32_V_M4_M2, + 10768 => Opcode::PseudoVSOXSEG3EI32_V_M4_M2_MASK, + 10769 => Opcode::PseudoVSOXSEG3EI32_V_M8_M2, + 10770 => Opcode::PseudoVSOXSEG3EI32_V_M8_M2_MASK, + 10771 => Opcode::PseudoVSOXSEG3EI32_V_MF2_M1, + 10772 => Opcode::PseudoVSOXSEG3EI32_V_MF2_M1_MASK, + 10773 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF2, + 10774 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, + 10775 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF4, + 10776 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, + 10777 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF8, + 10778 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, + 10779 => Opcode::PseudoVSOXSEG3EI64_V_M1_M1, + 10780 => Opcode::PseudoVSOXSEG3EI64_V_M1_M1_MASK, + 10781 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF2, + 10782 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF2_MASK, + 10783 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF4, + 10784 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF4_MASK, + 10785 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF8, + 10786 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF8_MASK, + 10787 => Opcode::PseudoVSOXSEG3EI64_V_M2_M1, + 10788 => Opcode::PseudoVSOXSEG3EI64_V_M2_M1_MASK, + 10789 => Opcode::PseudoVSOXSEG3EI64_V_M2_M2, + 10790 => Opcode::PseudoVSOXSEG3EI64_V_M2_M2_MASK, + 10791 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF2, + 10792 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF2_MASK, + 10793 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF4, + 10794 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF4_MASK, + 10795 => Opcode::PseudoVSOXSEG3EI64_V_M4_M1, + 10796 => Opcode::PseudoVSOXSEG3EI64_V_M4_M1_MASK, + 10797 => Opcode::PseudoVSOXSEG3EI64_V_M4_M2, + 10798 => Opcode::PseudoVSOXSEG3EI64_V_M4_M2_MASK, + 10799 => Opcode::PseudoVSOXSEG3EI64_V_M4_MF2, + 10800 => Opcode::PseudoVSOXSEG3EI64_V_M4_MF2_MASK, + 10801 => Opcode::PseudoVSOXSEG3EI64_V_M8_M1, + 10802 => Opcode::PseudoVSOXSEG3EI64_V_M8_M1_MASK, + 10803 => Opcode::PseudoVSOXSEG3EI64_V_M8_M2, + 10804 => Opcode::PseudoVSOXSEG3EI64_V_M8_M2_MASK, + 10805 => Opcode::PseudoVSOXSEG3EI8_V_M1_M1, + 10806 => Opcode::PseudoVSOXSEG3EI8_V_M1_M1_MASK, + 10807 => Opcode::PseudoVSOXSEG3EI8_V_M1_M2, + 10808 => Opcode::PseudoVSOXSEG3EI8_V_M1_M2_MASK, + 10809 => Opcode::PseudoVSOXSEG3EI8_V_M2_M2, + 10810 => Opcode::PseudoVSOXSEG3EI8_V_M2_M2_MASK, + 10811 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M1, + 10812 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M1_MASK, + 10813 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M2, + 10814 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M2_MASK, + 10815 => Opcode::PseudoVSOXSEG3EI8_V_MF2_MF2, + 10816 => Opcode::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, + 10817 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M1, + 10818 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M1_MASK, + 10819 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M2, + 10820 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M2_MASK, + 10821 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF2, + 10822 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, + 10823 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF4, + 10824 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, + 10825 => Opcode::PseudoVSOXSEG3EI8_V_MF8_M1, + 10826 => Opcode::PseudoVSOXSEG3EI8_V_MF8_M1_MASK, + 10827 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF2, + 10828 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, + 10829 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF4, + 10830 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, + 10831 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF8, + 10832 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, + 10833 => Opcode::PseudoVSOXSEG4EI16_V_M1_M1, + 10834 => Opcode::PseudoVSOXSEG4EI16_V_M1_M1_MASK, + 10835 => Opcode::PseudoVSOXSEG4EI16_V_M1_M2, + 10836 => Opcode::PseudoVSOXSEG4EI16_V_M1_M2_MASK, + 10837 => Opcode::PseudoVSOXSEG4EI16_V_M1_MF2, + 10838 => Opcode::PseudoVSOXSEG4EI16_V_M1_MF2_MASK, + 10839 => Opcode::PseudoVSOXSEG4EI16_V_M2_M1, + 10840 => Opcode::PseudoVSOXSEG4EI16_V_M2_M1_MASK, + 10841 => Opcode::PseudoVSOXSEG4EI16_V_M2_M2, + 10842 => Opcode::PseudoVSOXSEG4EI16_V_M2_M2_MASK, + 10843 => Opcode::PseudoVSOXSEG4EI16_V_M4_M2, + 10844 => Opcode::PseudoVSOXSEG4EI16_V_M4_M2_MASK, + 10845 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M1, + 10846 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M1_MASK, + 10847 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M2, + 10848 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M2_MASK, + 10849 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF2, + 10850 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, + 10851 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF4, + 10852 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, + 10853 => Opcode::PseudoVSOXSEG4EI16_V_MF4_M1, + 10854 => Opcode::PseudoVSOXSEG4EI16_V_MF4_M1_MASK, + 10855 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF2, + 10856 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, + 10857 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF4, + 10858 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, + 10859 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF8, + 10860 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, + 10861 => Opcode::PseudoVSOXSEG4EI32_V_M1_M1, + 10862 => Opcode::PseudoVSOXSEG4EI32_V_M1_M1_MASK, + 10863 => Opcode::PseudoVSOXSEG4EI32_V_M1_M2, + 10864 => Opcode::PseudoVSOXSEG4EI32_V_M1_M2_MASK, + 10865 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF2, + 10866 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF2_MASK, + 10867 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF4, + 10868 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF4_MASK, + 10869 => Opcode::PseudoVSOXSEG4EI32_V_M2_M1, + 10870 => Opcode::PseudoVSOXSEG4EI32_V_M2_M1_MASK, + 10871 => Opcode::PseudoVSOXSEG4EI32_V_M2_M2, + 10872 => Opcode::PseudoVSOXSEG4EI32_V_M2_M2_MASK, + 10873 => Opcode::PseudoVSOXSEG4EI32_V_M2_MF2, + 10874 => Opcode::PseudoVSOXSEG4EI32_V_M2_MF2_MASK, + 10875 => Opcode::PseudoVSOXSEG4EI32_V_M4_M1, + 10876 => Opcode::PseudoVSOXSEG4EI32_V_M4_M1_MASK, + 10877 => Opcode::PseudoVSOXSEG4EI32_V_M4_M2, + 10878 => Opcode::PseudoVSOXSEG4EI32_V_M4_M2_MASK, + 10879 => Opcode::PseudoVSOXSEG4EI32_V_M8_M2, + 10880 => Opcode::PseudoVSOXSEG4EI32_V_M8_M2_MASK, + 10881 => Opcode::PseudoVSOXSEG4EI32_V_MF2_M1, + 10882 => Opcode::PseudoVSOXSEG4EI32_V_MF2_M1_MASK, + 10883 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF2, + 10884 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, + 10885 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF4, + 10886 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, + 10887 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF8, + 10888 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, + 10889 => Opcode::PseudoVSOXSEG4EI64_V_M1_M1, + 10890 => Opcode::PseudoVSOXSEG4EI64_V_M1_M1_MASK, + 10891 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF2, + 10892 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF2_MASK, + 10893 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF4, + 10894 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF4_MASK, + 10895 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF8, + 10896 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF8_MASK, + 10897 => Opcode::PseudoVSOXSEG4EI64_V_M2_M1, + 10898 => Opcode::PseudoVSOXSEG4EI64_V_M2_M1_MASK, + 10899 => Opcode::PseudoVSOXSEG4EI64_V_M2_M2, + 10900 => Opcode::PseudoVSOXSEG4EI64_V_M2_M2_MASK, + 10901 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF2, + 10902 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF2_MASK, + 10903 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF4, + 10904 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF4_MASK, + 10905 => Opcode::PseudoVSOXSEG4EI64_V_M4_M1, + 10906 => Opcode::PseudoVSOXSEG4EI64_V_M4_M1_MASK, + 10907 => Opcode::PseudoVSOXSEG4EI64_V_M4_M2, + 10908 => Opcode::PseudoVSOXSEG4EI64_V_M4_M2_MASK, + 10909 => Opcode::PseudoVSOXSEG4EI64_V_M4_MF2, + 10910 => Opcode::PseudoVSOXSEG4EI64_V_M4_MF2_MASK, + 10911 => Opcode::PseudoVSOXSEG4EI64_V_M8_M1, + 10912 => Opcode::PseudoVSOXSEG4EI64_V_M8_M1_MASK, + 10913 => Opcode::PseudoVSOXSEG4EI64_V_M8_M2, + 10914 => Opcode::PseudoVSOXSEG4EI64_V_M8_M2_MASK, + 10915 => Opcode::PseudoVSOXSEG4EI8_V_M1_M1, + 10916 => Opcode::PseudoVSOXSEG4EI8_V_M1_M1_MASK, + 10917 => Opcode::PseudoVSOXSEG4EI8_V_M1_M2, + 10918 => Opcode::PseudoVSOXSEG4EI8_V_M1_M2_MASK, + 10919 => Opcode::PseudoVSOXSEG4EI8_V_M2_M2, + 10920 => Opcode::PseudoVSOXSEG4EI8_V_M2_M2_MASK, + 10921 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M1, + 10922 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M1_MASK, + 10923 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M2, + 10924 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M2_MASK, + 10925 => Opcode::PseudoVSOXSEG4EI8_V_MF2_MF2, + 10926 => Opcode::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, + 10927 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M1, + 10928 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M1_MASK, + 10929 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M2, + 10930 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M2_MASK, + 10931 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF2, + 10932 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, + 10933 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF4, + 10934 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, + 10935 => Opcode::PseudoVSOXSEG4EI8_V_MF8_M1, + 10936 => Opcode::PseudoVSOXSEG4EI8_V_MF8_M1_MASK, + 10937 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF2, + 10938 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, + 10939 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF4, + 10940 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, + 10941 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF8, + 10942 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, + 10943 => Opcode::PseudoVSOXSEG5EI16_V_M1_M1, + 10944 => Opcode::PseudoVSOXSEG5EI16_V_M1_M1_MASK, + 10945 => Opcode::PseudoVSOXSEG5EI16_V_M1_MF2, + 10946 => Opcode::PseudoVSOXSEG5EI16_V_M1_MF2_MASK, + 10947 => Opcode::PseudoVSOXSEG5EI16_V_M2_M1, + 10948 => Opcode::PseudoVSOXSEG5EI16_V_M2_M1_MASK, + 10949 => Opcode::PseudoVSOXSEG5EI16_V_MF2_M1, + 10950 => Opcode::PseudoVSOXSEG5EI16_V_MF2_M1_MASK, + 10951 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF2, + 10952 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, + 10953 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF4, + 10954 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, + 10955 => Opcode::PseudoVSOXSEG5EI16_V_MF4_M1, + 10956 => Opcode::PseudoVSOXSEG5EI16_V_MF4_M1_MASK, + 10957 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF2, + 10958 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, + 10959 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF4, + 10960 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, + 10961 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF8, + 10962 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, + 10963 => Opcode::PseudoVSOXSEG5EI32_V_M1_M1, + 10964 => Opcode::PseudoVSOXSEG5EI32_V_M1_M1_MASK, + 10965 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF2, + 10966 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF2_MASK, + 10967 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF4, + 10968 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF4_MASK, + 10969 => Opcode::PseudoVSOXSEG5EI32_V_M2_M1, + 10970 => Opcode::PseudoVSOXSEG5EI32_V_M2_M1_MASK, + 10971 => Opcode::PseudoVSOXSEG5EI32_V_M2_MF2, + 10972 => Opcode::PseudoVSOXSEG5EI32_V_M2_MF2_MASK, + 10973 => Opcode::PseudoVSOXSEG5EI32_V_M4_M1, + 10974 => Opcode::PseudoVSOXSEG5EI32_V_M4_M1_MASK, + 10975 => Opcode::PseudoVSOXSEG5EI32_V_MF2_M1, + 10976 => Opcode::PseudoVSOXSEG5EI32_V_MF2_M1_MASK, + 10977 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF2, + 10978 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, + 10979 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF4, + 10980 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, + 10981 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF8, + 10982 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, + 10983 => Opcode::PseudoVSOXSEG5EI64_V_M1_M1, + 10984 => Opcode::PseudoVSOXSEG5EI64_V_M1_M1_MASK, + 10985 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF2, + 10986 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF2_MASK, + 10987 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF4, + 10988 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF4_MASK, + 10989 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF8, + 10990 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF8_MASK, + 10991 => Opcode::PseudoVSOXSEG5EI64_V_M2_M1, + 10992 => Opcode::PseudoVSOXSEG5EI64_V_M2_M1_MASK, + 10993 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF2, + 10994 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF2_MASK, + 10995 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF4, + 10996 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF4_MASK, + 10997 => Opcode::PseudoVSOXSEG5EI64_V_M4_M1, + 10998 => Opcode::PseudoVSOXSEG5EI64_V_M4_M1_MASK, + 10999 => Opcode::PseudoVSOXSEG5EI64_V_M4_MF2, + 11000 => Opcode::PseudoVSOXSEG5EI64_V_M4_MF2_MASK, + 11001 => Opcode::PseudoVSOXSEG5EI64_V_M8_M1, + 11002 => Opcode::PseudoVSOXSEG5EI64_V_M8_M1_MASK, + 11003 => Opcode::PseudoVSOXSEG5EI8_V_M1_M1, + 11004 => Opcode::PseudoVSOXSEG5EI8_V_M1_M1_MASK, + 11005 => Opcode::PseudoVSOXSEG5EI8_V_MF2_M1, + 11006 => Opcode::PseudoVSOXSEG5EI8_V_MF2_M1_MASK, + 11007 => Opcode::PseudoVSOXSEG5EI8_V_MF2_MF2, + 11008 => Opcode::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, + 11009 => Opcode::PseudoVSOXSEG5EI8_V_MF4_M1, + 11010 => Opcode::PseudoVSOXSEG5EI8_V_MF4_M1_MASK, + 11011 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF2, + 11012 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, + 11013 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF4, + 11014 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, + 11015 => Opcode::PseudoVSOXSEG5EI8_V_MF8_M1, + 11016 => Opcode::PseudoVSOXSEG5EI8_V_MF8_M1_MASK, + 11017 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF2, + 11018 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, + 11019 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF4, + 11020 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, + 11021 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF8, + 11022 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, + 11023 => Opcode::PseudoVSOXSEG6EI16_V_M1_M1, + 11024 => Opcode::PseudoVSOXSEG6EI16_V_M1_M1_MASK, + 11025 => Opcode::PseudoVSOXSEG6EI16_V_M1_MF2, + 11026 => Opcode::PseudoVSOXSEG6EI16_V_M1_MF2_MASK, + 11027 => Opcode::PseudoVSOXSEG6EI16_V_M2_M1, + 11028 => Opcode::PseudoVSOXSEG6EI16_V_M2_M1_MASK, + 11029 => Opcode::PseudoVSOXSEG6EI16_V_MF2_M1, + 11030 => Opcode::PseudoVSOXSEG6EI16_V_MF2_M1_MASK, + 11031 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF2, + 11032 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, + 11033 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF4, + 11034 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, + 11035 => Opcode::PseudoVSOXSEG6EI16_V_MF4_M1, + 11036 => Opcode::PseudoVSOXSEG6EI16_V_MF4_M1_MASK, + 11037 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF2, + 11038 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, + 11039 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF4, + 11040 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, + 11041 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF8, + 11042 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, + 11043 => Opcode::PseudoVSOXSEG6EI32_V_M1_M1, + 11044 => Opcode::PseudoVSOXSEG6EI32_V_M1_M1_MASK, + 11045 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF2, + 11046 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF2_MASK, + 11047 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF4, + 11048 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF4_MASK, + 11049 => Opcode::PseudoVSOXSEG6EI32_V_M2_M1, + 11050 => Opcode::PseudoVSOXSEG6EI32_V_M2_M1_MASK, + 11051 => Opcode::PseudoVSOXSEG6EI32_V_M2_MF2, + 11052 => Opcode::PseudoVSOXSEG6EI32_V_M2_MF2_MASK, + 11053 => Opcode::PseudoVSOXSEG6EI32_V_M4_M1, + 11054 => Opcode::PseudoVSOXSEG6EI32_V_M4_M1_MASK, + 11055 => Opcode::PseudoVSOXSEG6EI32_V_MF2_M1, + 11056 => Opcode::PseudoVSOXSEG6EI32_V_MF2_M1_MASK, + 11057 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF2, + 11058 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, + 11059 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF4, + 11060 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, + 11061 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF8, + 11062 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, + 11063 => Opcode::PseudoVSOXSEG6EI64_V_M1_M1, + 11064 => Opcode::PseudoVSOXSEG6EI64_V_M1_M1_MASK, + 11065 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF2, + 11066 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF2_MASK, + 11067 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF4, + 11068 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF4_MASK, + 11069 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF8, + 11070 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF8_MASK, + 11071 => Opcode::PseudoVSOXSEG6EI64_V_M2_M1, + 11072 => Opcode::PseudoVSOXSEG6EI64_V_M2_M1_MASK, + 11073 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF2, + 11074 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF2_MASK, + 11075 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF4, + 11076 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF4_MASK, + 11077 => Opcode::PseudoVSOXSEG6EI64_V_M4_M1, + 11078 => Opcode::PseudoVSOXSEG6EI64_V_M4_M1_MASK, + 11079 => Opcode::PseudoVSOXSEG6EI64_V_M4_MF2, + 11080 => Opcode::PseudoVSOXSEG6EI64_V_M4_MF2_MASK, + 11081 => Opcode::PseudoVSOXSEG6EI64_V_M8_M1, + 11082 => Opcode::PseudoVSOXSEG6EI64_V_M8_M1_MASK, + 11083 => Opcode::PseudoVSOXSEG6EI8_V_M1_M1, + 11084 => Opcode::PseudoVSOXSEG6EI8_V_M1_M1_MASK, + 11085 => Opcode::PseudoVSOXSEG6EI8_V_MF2_M1, + 11086 => Opcode::PseudoVSOXSEG6EI8_V_MF2_M1_MASK, + 11087 => Opcode::PseudoVSOXSEG6EI8_V_MF2_MF2, + 11088 => Opcode::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, + 11089 => Opcode::PseudoVSOXSEG6EI8_V_MF4_M1, + 11090 => Opcode::PseudoVSOXSEG6EI8_V_MF4_M1_MASK, + 11091 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF2, + 11092 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, + 11093 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF4, + 11094 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, + 11095 => Opcode::PseudoVSOXSEG6EI8_V_MF8_M1, + 11096 => Opcode::PseudoVSOXSEG6EI8_V_MF8_M1_MASK, + 11097 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF2, + 11098 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, + 11099 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF4, + 11100 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, + 11101 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF8, + 11102 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, + 11103 => Opcode::PseudoVSOXSEG7EI16_V_M1_M1, + 11104 => Opcode::PseudoVSOXSEG7EI16_V_M1_M1_MASK, + 11105 => Opcode::PseudoVSOXSEG7EI16_V_M1_MF2, + 11106 => Opcode::PseudoVSOXSEG7EI16_V_M1_MF2_MASK, + 11107 => Opcode::PseudoVSOXSEG7EI16_V_M2_M1, + 11108 => Opcode::PseudoVSOXSEG7EI16_V_M2_M1_MASK, + 11109 => Opcode::PseudoVSOXSEG7EI16_V_MF2_M1, + 11110 => Opcode::PseudoVSOXSEG7EI16_V_MF2_M1_MASK, + 11111 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF2, + 11112 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, + 11113 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF4, + 11114 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, + 11115 => Opcode::PseudoVSOXSEG7EI16_V_MF4_M1, + 11116 => Opcode::PseudoVSOXSEG7EI16_V_MF4_M1_MASK, + 11117 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF2, + 11118 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, + 11119 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF4, + 11120 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, + 11121 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF8, + 11122 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, + 11123 => Opcode::PseudoVSOXSEG7EI32_V_M1_M1, + 11124 => Opcode::PseudoVSOXSEG7EI32_V_M1_M1_MASK, + 11125 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF2, + 11126 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF2_MASK, + 11127 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF4, + 11128 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF4_MASK, + 11129 => Opcode::PseudoVSOXSEG7EI32_V_M2_M1, + 11130 => Opcode::PseudoVSOXSEG7EI32_V_M2_M1_MASK, + 11131 => Opcode::PseudoVSOXSEG7EI32_V_M2_MF2, + 11132 => Opcode::PseudoVSOXSEG7EI32_V_M2_MF2_MASK, + 11133 => Opcode::PseudoVSOXSEG7EI32_V_M4_M1, + 11134 => Opcode::PseudoVSOXSEG7EI32_V_M4_M1_MASK, + 11135 => Opcode::PseudoVSOXSEG7EI32_V_MF2_M1, + 11136 => Opcode::PseudoVSOXSEG7EI32_V_MF2_M1_MASK, + 11137 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF2, + 11138 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, + 11139 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF4, + 11140 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, + 11141 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF8, + 11142 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, + 11143 => Opcode::PseudoVSOXSEG7EI64_V_M1_M1, + 11144 => Opcode::PseudoVSOXSEG7EI64_V_M1_M1_MASK, + 11145 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF2, + 11146 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF2_MASK, + 11147 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF4, + 11148 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF4_MASK, + 11149 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF8, + 11150 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF8_MASK, + 11151 => Opcode::PseudoVSOXSEG7EI64_V_M2_M1, + 11152 => Opcode::PseudoVSOXSEG7EI64_V_M2_M1_MASK, + 11153 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF2, + 11154 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF2_MASK, + 11155 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF4, + 11156 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF4_MASK, + 11157 => Opcode::PseudoVSOXSEG7EI64_V_M4_M1, + 11158 => Opcode::PseudoVSOXSEG7EI64_V_M4_M1_MASK, + 11159 => Opcode::PseudoVSOXSEG7EI64_V_M4_MF2, + 11160 => Opcode::PseudoVSOXSEG7EI64_V_M4_MF2_MASK, + 11161 => Opcode::PseudoVSOXSEG7EI64_V_M8_M1, + 11162 => Opcode::PseudoVSOXSEG7EI64_V_M8_M1_MASK, + 11163 => Opcode::PseudoVSOXSEG7EI8_V_M1_M1, + 11164 => Opcode::PseudoVSOXSEG7EI8_V_M1_M1_MASK, + 11165 => Opcode::PseudoVSOXSEG7EI8_V_MF2_M1, + 11166 => Opcode::PseudoVSOXSEG7EI8_V_MF2_M1_MASK, + 11167 => Opcode::PseudoVSOXSEG7EI8_V_MF2_MF2, + 11168 => Opcode::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, + 11169 => Opcode::PseudoVSOXSEG7EI8_V_MF4_M1, + 11170 => Opcode::PseudoVSOXSEG7EI8_V_MF4_M1_MASK, + 11171 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF2, + 11172 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, + 11173 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF4, + 11174 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, + 11175 => Opcode::PseudoVSOXSEG7EI8_V_MF8_M1, + 11176 => Opcode::PseudoVSOXSEG7EI8_V_MF8_M1_MASK, + 11177 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF2, + 11178 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, + 11179 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF4, + 11180 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, + 11181 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF8, + 11182 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, + 11183 => Opcode::PseudoVSOXSEG8EI16_V_M1_M1, + 11184 => Opcode::PseudoVSOXSEG8EI16_V_M1_M1_MASK, + 11185 => Opcode::PseudoVSOXSEG8EI16_V_M1_MF2, + 11186 => Opcode::PseudoVSOXSEG8EI16_V_M1_MF2_MASK, + 11187 => Opcode::PseudoVSOXSEG8EI16_V_M2_M1, + 11188 => Opcode::PseudoVSOXSEG8EI16_V_M2_M1_MASK, + 11189 => Opcode::PseudoVSOXSEG8EI16_V_MF2_M1, + 11190 => Opcode::PseudoVSOXSEG8EI16_V_MF2_M1_MASK, + 11191 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF2, + 11192 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, + 11193 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF4, + 11194 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, + 11195 => Opcode::PseudoVSOXSEG8EI16_V_MF4_M1, + 11196 => Opcode::PseudoVSOXSEG8EI16_V_MF4_M1_MASK, + 11197 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF2, + 11198 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, + 11199 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF4, + 11200 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, + 11201 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF8, + 11202 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, + 11203 => Opcode::PseudoVSOXSEG8EI32_V_M1_M1, + 11204 => Opcode::PseudoVSOXSEG8EI32_V_M1_M1_MASK, + 11205 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF2, + 11206 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF2_MASK, + 11207 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF4, + 11208 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF4_MASK, + 11209 => Opcode::PseudoVSOXSEG8EI32_V_M2_M1, + 11210 => Opcode::PseudoVSOXSEG8EI32_V_M2_M1_MASK, + 11211 => Opcode::PseudoVSOXSEG8EI32_V_M2_MF2, + 11212 => Opcode::PseudoVSOXSEG8EI32_V_M2_MF2_MASK, + 11213 => Opcode::PseudoVSOXSEG8EI32_V_M4_M1, + 11214 => Opcode::PseudoVSOXSEG8EI32_V_M4_M1_MASK, + 11215 => Opcode::PseudoVSOXSEG8EI32_V_MF2_M1, + 11216 => Opcode::PseudoVSOXSEG8EI32_V_MF2_M1_MASK, + 11217 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF2, + 11218 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, + 11219 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF4, + 11220 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, + 11221 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF8, + 11222 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, + 11223 => Opcode::PseudoVSOXSEG8EI64_V_M1_M1, + 11224 => Opcode::PseudoVSOXSEG8EI64_V_M1_M1_MASK, + 11225 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF2, + 11226 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF2_MASK, + 11227 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF4, + 11228 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF4_MASK, + 11229 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF8, + 11230 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF8_MASK, + 11231 => Opcode::PseudoVSOXSEG8EI64_V_M2_M1, + 11232 => Opcode::PseudoVSOXSEG8EI64_V_M2_M1_MASK, + 11233 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF2, + 11234 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF2_MASK, + 11235 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF4, + 11236 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF4_MASK, + 11237 => Opcode::PseudoVSOXSEG8EI64_V_M4_M1, + 11238 => Opcode::PseudoVSOXSEG8EI64_V_M4_M1_MASK, + 11239 => Opcode::PseudoVSOXSEG8EI64_V_M4_MF2, + 11240 => Opcode::PseudoVSOXSEG8EI64_V_M4_MF2_MASK, + 11241 => Opcode::PseudoVSOXSEG8EI64_V_M8_M1, + 11242 => Opcode::PseudoVSOXSEG8EI64_V_M8_M1_MASK, + 11243 => Opcode::PseudoVSOXSEG8EI8_V_M1_M1, + 11244 => Opcode::PseudoVSOXSEG8EI8_V_M1_M1_MASK, + 11245 => Opcode::PseudoVSOXSEG8EI8_V_MF2_M1, + 11246 => Opcode::PseudoVSOXSEG8EI8_V_MF2_M1_MASK, + 11247 => Opcode::PseudoVSOXSEG8EI8_V_MF2_MF2, + 11248 => Opcode::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, + 11249 => Opcode::PseudoVSOXSEG8EI8_V_MF4_M1, + 11250 => Opcode::PseudoVSOXSEG8EI8_V_MF4_M1_MASK, + 11251 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF2, + 11252 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, + 11253 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF4, + 11254 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, + 11255 => Opcode::PseudoVSOXSEG8EI8_V_MF8_M1, + 11256 => Opcode::PseudoVSOXSEG8EI8_V_MF8_M1_MASK, + 11257 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF2, + 11258 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, + 11259 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF4, + 11260 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, + 11261 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF8, + 11262 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, + 11263 => Opcode::PseudoVSPILL2_M1, + 11264 => Opcode::PseudoVSPILL2_M2, + 11265 => Opcode::PseudoVSPILL2_M4, + 11266 => Opcode::PseudoVSPILL2_MF2, + 11267 => Opcode::PseudoVSPILL2_MF4, + 11268 => Opcode::PseudoVSPILL2_MF8, + 11269 => Opcode::PseudoVSPILL3_M1, + 11270 => Opcode::PseudoVSPILL3_M2, + 11271 => Opcode::PseudoVSPILL3_MF2, + 11272 => Opcode::PseudoVSPILL3_MF4, + 11273 => Opcode::PseudoVSPILL3_MF8, + 11274 => Opcode::PseudoVSPILL4_M1, + 11275 => Opcode::PseudoVSPILL4_M2, + 11276 => Opcode::PseudoVSPILL4_MF2, + 11277 => Opcode::PseudoVSPILL4_MF4, + 11278 => Opcode::PseudoVSPILL4_MF8, + 11279 => Opcode::PseudoVSPILL5_M1, + 11280 => Opcode::PseudoVSPILL5_MF2, + 11281 => Opcode::PseudoVSPILL5_MF4, + 11282 => Opcode::PseudoVSPILL5_MF8, + 11283 => Opcode::PseudoVSPILL6_M1, + 11284 => Opcode::PseudoVSPILL6_MF2, + 11285 => Opcode::PseudoVSPILL6_MF4, + 11286 => Opcode::PseudoVSPILL6_MF8, + 11287 => Opcode::PseudoVSPILL7_M1, + 11288 => Opcode::PseudoVSPILL7_MF2, + 11289 => Opcode::PseudoVSPILL7_MF4, + 11290 => Opcode::PseudoVSPILL7_MF8, + 11291 => Opcode::PseudoVSPILL8_M1, + 11292 => Opcode::PseudoVSPILL8_MF2, + 11293 => Opcode::PseudoVSPILL8_MF4, + 11294 => Opcode::PseudoVSPILL8_MF8, + 11295 => Opcode::PseudoVSRA_VI_M1, + 11296 => Opcode::PseudoVSRA_VI_M1_MASK, + 11297 => Opcode::PseudoVSRA_VI_M2, + 11298 => Opcode::PseudoVSRA_VI_M2_MASK, + 11299 => Opcode::PseudoVSRA_VI_M4, + 11300 => Opcode::PseudoVSRA_VI_M4_MASK, + 11301 => Opcode::PseudoVSRA_VI_M8, + 11302 => Opcode::PseudoVSRA_VI_M8_MASK, + 11303 => Opcode::PseudoVSRA_VI_MF2, + 11304 => Opcode::PseudoVSRA_VI_MF2_MASK, + 11305 => Opcode::PseudoVSRA_VI_MF4, + 11306 => Opcode::PseudoVSRA_VI_MF4_MASK, + 11307 => Opcode::PseudoVSRA_VI_MF8, + 11308 => Opcode::PseudoVSRA_VI_MF8_MASK, + 11309 => Opcode::PseudoVSRA_VV_M1, + 11310 => Opcode::PseudoVSRA_VV_M1_MASK, + 11311 => Opcode::PseudoVSRA_VV_M2, + 11312 => Opcode::PseudoVSRA_VV_M2_MASK, + 11313 => Opcode::PseudoVSRA_VV_M4, + 11314 => Opcode::PseudoVSRA_VV_M4_MASK, + 11315 => Opcode::PseudoVSRA_VV_M8, + 11316 => Opcode::PseudoVSRA_VV_M8_MASK, + 11317 => Opcode::PseudoVSRA_VV_MF2, + 11318 => Opcode::PseudoVSRA_VV_MF2_MASK, + 11319 => Opcode::PseudoVSRA_VV_MF4, + 11320 => Opcode::PseudoVSRA_VV_MF4_MASK, + 11321 => Opcode::PseudoVSRA_VV_MF8, + 11322 => Opcode::PseudoVSRA_VV_MF8_MASK, + 11323 => Opcode::PseudoVSRA_VX_M1, + 11324 => Opcode::PseudoVSRA_VX_M1_MASK, + 11325 => Opcode::PseudoVSRA_VX_M2, + 11326 => Opcode::PseudoVSRA_VX_M2_MASK, + 11327 => Opcode::PseudoVSRA_VX_M4, + 11328 => Opcode::PseudoVSRA_VX_M4_MASK, + 11329 => Opcode::PseudoVSRA_VX_M8, + 11330 => Opcode::PseudoVSRA_VX_M8_MASK, + 11331 => Opcode::PseudoVSRA_VX_MF2, + 11332 => Opcode::PseudoVSRA_VX_MF2_MASK, + 11333 => Opcode::PseudoVSRA_VX_MF4, + 11334 => Opcode::PseudoVSRA_VX_MF4_MASK, + 11335 => Opcode::PseudoVSRA_VX_MF8, + 11336 => Opcode::PseudoVSRA_VX_MF8_MASK, + 11337 => Opcode::PseudoVSRL_VI_M1, + 11338 => Opcode::PseudoVSRL_VI_M1_MASK, + 11339 => Opcode::PseudoVSRL_VI_M2, + 11340 => Opcode::PseudoVSRL_VI_M2_MASK, + 11341 => Opcode::PseudoVSRL_VI_M4, + 11342 => Opcode::PseudoVSRL_VI_M4_MASK, + 11343 => Opcode::PseudoVSRL_VI_M8, + 11344 => Opcode::PseudoVSRL_VI_M8_MASK, + 11345 => Opcode::PseudoVSRL_VI_MF2, + 11346 => Opcode::PseudoVSRL_VI_MF2_MASK, + 11347 => Opcode::PseudoVSRL_VI_MF4, + 11348 => Opcode::PseudoVSRL_VI_MF4_MASK, + 11349 => Opcode::PseudoVSRL_VI_MF8, + 11350 => Opcode::PseudoVSRL_VI_MF8_MASK, + 11351 => Opcode::PseudoVSRL_VV_M1, + 11352 => Opcode::PseudoVSRL_VV_M1_MASK, + 11353 => Opcode::PseudoVSRL_VV_M2, + 11354 => Opcode::PseudoVSRL_VV_M2_MASK, + 11355 => Opcode::PseudoVSRL_VV_M4, + 11356 => Opcode::PseudoVSRL_VV_M4_MASK, + 11357 => Opcode::PseudoVSRL_VV_M8, + 11358 => Opcode::PseudoVSRL_VV_M8_MASK, + 11359 => Opcode::PseudoVSRL_VV_MF2, + 11360 => Opcode::PseudoVSRL_VV_MF2_MASK, + 11361 => Opcode::PseudoVSRL_VV_MF4, + 11362 => Opcode::PseudoVSRL_VV_MF4_MASK, + 11363 => Opcode::PseudoVSRL_VV_MF8, + 11364 => Opcode::PseudoVSRL_VV_MF8_MASK, + 11365 => Opcode::PseudoVSRL_VX_M1, + 11366 => Opcode::PseudoVSRL_VX_M1_MASK, + 11367 => Opcode::PseudoVSRL_VX_M2, + 11368 => Opcode::PseudoVSRL_VX_M2_MASK, + 11369 => Opcode::PseudoVSRL_VX_M4, + 11370 => Opcode::PseudoVSRL_VX_M4_MASK, + 11371 => Opcode::PseudoVSRL_VX_M8, + 11372 => Opcode::PseudoVSRL_VX_M8_MASK, + 11373 => Opcode::PseudoVSRL_VX_MF2, + 11374 => Opcode::PseudoVSRL_VX_MF2_MASK, + 11375 => Opcode::PseudoVSRL_VX_MF4, + 11376 => Opcode::PseudoVSRL_VX_MF4_MASK, + 11377 => Opcode::PseudoVSRL_VX_MF8, + 11378 => Opcode::PseudoVSRL_VX_MF8_MASK, + 11379 => Opcode::PseudoVSSE16_V_M1, + 11380 => Opcode::PseudoVSSE16_V_M1_MASK, + 11381 => Opcode::PseudoVSSE16_V_M2, + 11382 => Opcode::PseudoVSSE16_V_M2_MASK, + 11383 => Opcode::PseudoVSSE16_V_M4, + 11384 => Opcode::PseudoVSSE16_V_M4_MASK, + 11385 => Opcode::PseudoVSSE16_V_M8, + 11386 => Opcode::PseudoVSSE16_V_M8_MASK, + 11387 => Opcode::PseudoVSSE16_V_MF2, + 11388 => Opcode::PseudoVSSE16_V_MF2_MASK, + 11389 => Opcode::PseudoVSSE16_V_MF4, + 11390 => Opcode::PseudoVSSE16_V_MF4_MASK, + 11391 => Opcode::PseudoVSSE32_V_M1, + 11392 => Opcode::PseudoVSSE32_V_M1_MASK, + 11393 => Opcode::PseudoVSSE32_V_M2, + 11394 => Opcode::PseudoVSSE32_V_M2_MASK, + 11395 => Opcode::PseudoVSSE32_V_M4, + 11396 => Opcode::PseudoVSSE32_V_M4_MASK, + 11397 => Opcode::PseudoVSSE32_V_M8, + 11398 => Opcode::PseudoVSSE32_V_M8_MASK, + 11399 => Opcode::PseudoVSSE32_V_MF2, + 11400 => Opcode::PseudoVSSE32_V_MF2_MASK, + 11401 => Opcode::PseudoVSSE64_V_M1, + 11402 => Opcode::PseudoVSSE64_V_M1_MASK, + 11403 => Opcode::PseudoVSSE64_V_M2, + 11404 => Opcode::PseudoVSSE64_V_M2_MASK, + 11405 => Opcode::PseudoVSSE64_V_M4, + 11406 => Opcode::PseudoVSSE64_V_M4_MASK, + 11407 => Opcode::PseudoVSSE64_V_M8, + 11408 => Opcode::PseudoVSSE64_V_M8_MASK, + 11409 => Opcode::PseudoVSSE8_V_M1, + 11410 => Opcode::PseudoVSSE8_V_M1_MASK, + 11411 => Opcode::PseudoVSSE8_V_M2, + 11412 => Opcode::PseudoVSSE8_V_M2_MASK, + 11413 => Opcode::PseudoVSSE8_V_M4, + 11414 => Opcode::PseudoVSSE8_V_M4_MASK, + 11415 => Opcode::PseudoVSSE8_V_M8, + 11416 => Opcode::PseudoVSSE8_V_M8_MASK, + 11417 => Opcode::PseudoVSSE8_V_MF2, + 11418 => Opcode::PseudoVSSE8_V_MF2_MASK, + 11419 => Opcode::PseudoVSSE8_V_MF4, + 11420 => Opcode::PseudoVSSE8_V_MF4_MASK, + 11421 => Opcode::PseudoVSSE8_V_MF8, + 11422 => Opcode::PseudoVSSE8_V_MF8_MASK, + 11423 => Opcode::PseudoVSSEG2E16_V_M1, + 11424 => Opcode::PseudoVSSEG2E16_V_M1_MASK, + 11425 => Opcode::PseudoVSSEG2E16_V_M2, + 11426 => Opcode::PseudoVSSEG2E16_V_M2_MASK, + 11427 => Opcode::PseudoVSSEG2E16_V_M4, + 11428 => Opcode::PseudoVSSEG2E16_V_M4_MASK, + 11429 => Opcode::PseudoVSSEG2E16_V_MF2, + 11430 => Opcode::PseudoVSSEG2E16_V_MF2_MASK, + 11431 => Opcode::PseudoVSSEG2E16_V_MF4, + 11432 => Opcode::PseudoVSSEG2E16_V_MF4_MASK, + 11433 => Opcode::PseudoVSSEG2E32_V_M1, + 11434 => Opcode::PseudoVSSEG2E32_V_M1_MASK, + 11435 => Opcode::PseudoVSSEG2E32_V_M2, + 11436 => Opcode::PseudoVSSEG2E32_V_M2_MASK, + 11437 => Opcode::PseudoVSSEG2E32_V_M4, + 11438 => Opcode::PseudoVSSEG2E32_V_M4_MASK, + 11439 => Opcode::PseudoVSSEG2E32_V_MF2, + 11440 => Opcode::PseudoVSSEG2E32_V_MF2_MASK, + 11441 => Opcode::PseudoVSSEG2E64_V_M1, + 11442 => Opcode::PseudoVSSEG2E64_V_M1_MASK, + 11443 => Opcode::PseudoVSSEG2E64_V_M2, + 11444 => Opcode::PseudoVSSEG2E64_V_M2_MASK, + 11445 => Opcode::PseudoVSSEG2E64_V_M4, + 11446 => Opcode::PseudoVSSEG2E64_V_M4_MASK, + 11447 => Opcode::PseudoVSSEG2E8_V_M1, + 11448 => Opcode::PseudoVSSEG2E8_V_M1_MASK, + 11449 => Opcode::PseudoVSSEG2E8_V_M2, + 11450 => Opcode::PseudoVSSEG2E8_V_M2_MASK, + 11451 => Opcode::PseudoVSSEG2E8_V_M4, + 11452 => Opcode::PseudoVSSEG2E8_V_M4_MASK, + 11453 => Opcode::PseudoVSSEG2E8_V_MF2, + 11454 => Opcode::PseudoVSSEG2E8_V_MF2_MASK, + 11455 => Opcode::PseudoVSSEG2E8_V_MF4, + 11456 => Opcode::PseudoVSSEG2E8_V_MF4_MASK, + 11457 => Opcode::PseudoVSSEG2E8_V_MF8, + 11458 => Opcode::PseudoVSSEG2E8_V_MF8_MASK, + 11459 => Opcode::PseudoVSSEG3E16_V_M1, + 11460 => Opcode::PseudoVSSEG3E16_V_M1_MASK, + 11461 => Opcode::PseudoVSSEG3E16_V_M2, + 11462 => Opcode::PseudoVSSEG3E16_V_M2_MASK, + 11463 => Opcode::PseudoVSSEG3E16_V_MF2, + 11464 => Opcode::PseudoVSSEG3E16_V_MF2_MASK, + 11465 => Opcode::PseudoVSSEG3E16_V_MF4, + 11466 => Opcode::PseudoVSSEG3E16_V_MF4_MASK, + 11467 => Opcode::PseudoVSSEG3E32_V_M1, + 11468 => Opcode::PseudoVSSEG3E32_V_M1_MASK, + 11469 => Opcode::PseudoVSSEG3E32_V_M2, + 11470 => Opcode::PseudoVSSEG3E32_V_M2_MASK, + 11471 => Opcode::PseudoVSSEG3E32_V_MF2, + 11472 => Opcode::PseudoVSSEG3E32_V_MF2_MASK, + 11473 => Opcode::PseudoVSSEG3E64_V_M1, + 11474 => Opcode::PseudoVSSEG3E64_V_M1_MASK, + 11475 => Opcode::PseudoVSSEG3E64_V_M2, + 11476 => Opcode::PseudoVSSEG3E64_V_M2_MASK, + 11477 => Opcode::PseudoVSSEG3E8_V_M1, + 11478 => Opcode::PseudoVSSEG3E8_V_M1_MASK, + 11479 => Opcode::PseudoVSSEG3E8_V_M2, + 11480 => Opcode::PseudoVSSEG3E8_V_M2_MASK, + 11481 => Opcode::PseudoVSSEG3E8_V_MF2, + 11482 => Opcode::PseudoVSSEG3E8_V_MF2_MASK, + 11483 => Opcode::PseudoVSSEG3E8_V_MF4, + 11484 => Opcode::PseudoVSSEG3E8_V_MF4_MASK, + 11485 => Opcode::PseudoVSSEG3E8_V_MF8, + 11486 => Opcode::PseudoVSSEG3E8_V_MF8_MASK, + 11487 => Opcode::PseudoVSSEG4E16_V_M1, + 11488 => Opcode::PseudoVSSEG4E16_V_M1_MASK, + 11489 => Opcode::PseudoVSSEG4E16_V_M2, + 11490 => Opcode::PseudoVSSEG4E16_V_M2_MASK, + 11491 => Opcode::PseudoVSSEG4E16_V_MF2, + 11492 => Opcode::PseudoVSSEG4E16_V_MF2_MASK, + 11493 => Opcode::PseudoVSSEG4E16_V_MF4, + 11494 => Opcode::PseudoVSSEG4E16_V_MF4_MASK, + 11495 => Opcode::PseudoVSSEG4E32_V_M1, + 11496 => Opcode::PseudoVSSEG4E32_V_M1_MASK, + 11497 => Opcode::PseudoVSSEG4E32_V_M2, + 11498 => Opcode::PseudoVSSEG4E32_V_M2_MASK, + 11499 => Opcode::PseudoVSSEG4E32_V_MF2, + 11500 => Opcode::PseudoVSSEG4E32_V_MF2_MASK, + 11501 => Opcode::PseudoVSSEG4E64_V_M1, + 11502 => Opcode::PseudoVSSEG4E64_V_M1_MASK, + 11503 => Opcode::PseudoVSSEG4E64_V_M2, + 11504 => Opcode::PseudoVSSEG4E64_V_M2_MASK, + 11505 => Opcode::PseudoVSSEG4E8_V_M1, + 11506 => Opcode::PseudoVSSEG4E8_V_M1_MASK, + 11507 => Opcode::PseudoVSSEG4E8_V_M2, + 11508 => Opcode::PseudoVSSEG4E8_V_M2_MASK, + 11509 => Opcode::PseudoVSSEG4E8_V_MF2, + 11510 => Opcode::PseudoVSSEG4E8_V_MF2_MASK, + 11511 => Opcode::PseudoVSSEG4E8_V_MF4, + 11512 => Opcode::PseudoVSSEG4E8_V_MF4_MASK, + 11513 => Opcode::PseudoVSSEG4E8_V_MF8, + 11514 => Opcode::PseudoVSSEG4E8_V_MF8_MASK, + 11515 => Opcode::PseudoVSSEG5E16_V_M1, + 11516 => Opcode::PseudoVSSEG5E16_V_M1_MASK, + 11517 => Opcode::PseudoVSSEG5E16_V_MF2, + 11518 => Opcode::PseudoVSSEG5E16_V_MF2_MASK, + 11519 => Opcode::PseudoVSSEG5E16_V_MF4, + 11520 => Opcode::PseudoVSSEG5E16_V_MF4_MASK, + 11521 => Opcode::PseudoVSSEG5E32_V_M1, + 11522 => Opcode::PseudoVSSEG5E32_V_M1_MASK, + 11523 => Opcode::PseudoVSSEG5E32_V_MF2, + 11524 => Opcode::PseudoVSSEG5E32_V_MF2_MASK, + 11525 => Opcode::PseudoVSSEG5E64_V_M1, + 11526 => Opcode::PseudoVSSEG5E64_V_M1_MASK, + 11527 => Opcode::PseudoVSSEG5E8_V_M1, + 11528 => Opcode::PseudoVSSEG5E8_V_M1_MASK, + 11529 => Opcode::PseudoVSSEG5E8_V_MF2, + 11530 => Opcode::PseudoVSSEG5E8_V_MF2_MASK, + 11531 => Opcode::PseudoVSSEG5E8_V_MF4, + 11532 => Opcode::PseudoVSSEG5E8_V_MF4_MASK, + 11533 => Opcode::PseudoVSSEG5E8_V_MF8, + 11534 => Opcode::PseudoVSSEG5E8_V_MF8_MASK, + 11535 => Opcode::PseudoVSSEG6E16_V_M1, + 11536 => Opcode::PseudoVSSEG6E16_V_M1_MASK, + 11537 => Opcode::PseudoVSSEG6E16_V_MF2, + 11538 => Opcode::PseudoVSSEG6E16_V_MF2_MASK, + 11539 => Opcode::PseudoVSSEG6E16_V_MF4, + 11540 => Opcode::PseudoVSSEG6E16_V_MF4_MASK, + 11541 => Opcode::PseudoVSSEG6E32_V_M1, + 11542 => Opcode::PseudoVSSEG6E32_V_M1_MASK, + 11543 => Opcode::PseudoVSSEG6E32_V_MF2, + 11544 => Opcode::PseudoVSSEG6E32_V_MF2_MASK, + 11545 => Opcode::PseudoVSSEG6E64_V_M1, + 11546 => Opcode::PseudoVSSEG6E64_V_M1_MASK, + 11547 => Opcode::PseudoVSSEG6E8_V_M1, + 11548 => Opcode::PseudoVSSEG6E8_V_M1_MASK, + 11549 => Opcode::PseudoVSSEG6E8_V_MF2, + 11550 => Opcode::PseudoVSSEG6E8_V_MF2_MASK, + 11551 => Opcode::PseudoVSSEG6E8_V_MF4, + 11552 => Opcode::PseudoVSSEG6E8_V_MF4_MASK, + 11553 => Opcode::PseudoVSSEG6E8_V_MF8, + 11554 => Opcode::PseudoVSSEG6E8_V_MF8_MASK, + 11555 => Opcode::PseudoVSSEG7E16_V_M1, + 11556 => Opcode::PseudoVSSEG7E16_V_M1_MASK, + 11557 => Opcode::PseudoVSSEG7E16_V_MF2, + 11558 => Opcode::PseudoVSSEG7E16_V_MF2_MASK, + 11559 => Opcode::PseudoVSSEG7E16_V_MF4, + 11560 => Opcode::PseudoVSSEG7E16_V_MF4_MASK, + 11561 => Opcode::PseudoVSSEG7E32_V_M1, + 11562 => Opcode::PseudoVSSEG7E32_V_M1_MASK, + 11563 => Opcode::PseudoVSSEG7E32_V_MF2, + 11564 => Opcode::PseudoVSSEG7E32_V_MF2_MASK, + 11565 => Opcode::PseudoVSSEG7E64_V_M1, + 11566 => Opcode::PseudoVSSEG7E64_V_M1_MASK, + 11567 => Opcode::PseudoVSSEG7E8_V_M1, + 11568 => Opcode::PseudoVSSEG7E8_V_M1_MASK, + 11569 => Opcode::PseudoVSSEG7E8_V_MF2, + 11570 => Opcode::PseudoVSSEG7E8_V_MF2_MASK, + 11571 => Opcode::PseudoVSSEG7E8_V_MF4, + 11572 => Opcode::PseudoVSSEG7E8_V_MF4_MASK, + 11573 => Opcode::PseudoVSSEG7E8_V_MF8, + 11574 => Opcode::PseudoVSSEG7E8_V_MF8_MASK, + 11575 => Opcode::PseudoVSSEG8E16_V_M1, + 11576 => Opcode::PseudoVSSEG8E16_V_M1_MASK, + 11577 => Opcode::PseudoVSSEG8E16_V_MF2, + 11578 => Opcode::PseudoVSSEG8E16_V_MF2_MASK, + 11579 => Opcode::PseudoVSSEG8E16_V_MF4, + 11580 => Opcode::PseudoVSSEG8E16_V_MF4_MASK, + 11581 => Opcode::PseudoVSSEG8E32_V_M1, + 11582 => Opcode::PseudoVSSEG8E32_V_M1_MASK, + 11583 => Opcode::PseudoVSSEG8E32_V_MF2, + 11584 => Opcode::PseudoVSSEG8E32_V_MF2_MASK, + 11585 => Opcode::PseudoVSSEG8E64_V_M1, + 11586 => Opcode::PseudoVSSEG8E64_V_M1_MASK, + 11587 => Opcode::PseudoVSSEG8E8_V_M1, + 11588 => Opcode::PseudoVSSEG8E8_V_M1_MASK, + 11589 => Opcode::PseudoVSSEG8E8_V_MF2, + 11590 => Opcode::PseudoVSSEG8E8_V_MF2_MASK, + 11591 => Opcode::PseudoVSSEG8E8_V_MF4, + 11592 => Opcode::PseudoVSSEG8E8_V_MF4_MASK, + 11593 => Opcode::PseudoVSSEG8E8_V_MF8, + 11594 => Opcode::PseudoVSSEG8E8_V_MF8_MASK, + 11595 => Opcode::PseudoVSSRA_VI_M1, + 11596 => Opcode::PseudoVSSRA_VI_M1_MASK, + 11597 => Opcode::PseudoVSSRA_VI_M2, + 11598 => Opcode::PseudoVSSRA_VI_M2_MASK, + 11599 => Opcode::PseudoVSSRA_VI_M4, + 11600 => Opcode::PseudoVSSRA_VI_M4_MASK, + 11601 => Opcode::PseudoVSSRA_VI_M8, + 11602 => Opcode::PseudoVSSRA_VI_M8_MASK, + 11603 => Opcode::PseudoVSSRA_VI_MF2, + 11604 => Opcode::PseudoVSSRA_VI_MF2_MASK, + 11605 => Opcode::PseudoVSSRA_VI_MF4, + 11606 => Opcode::PseudoVSSRA_VI_MF4_MASK, + 11607 => Opcode::PseudoVSSRA_VI_MF8, + 11608 => Opcode::PseudoVSSRA_VI_MF8_MASK, + 11609 => Opcode::PseudoVSSRA_VV_M1, + 11610 => Opcode::PseudoVSSRA_VV_M1_MASK, + 11611 => Opcode::PseudoVSSRA_VV_M2, + 11612 => Opcode::PseudoVSSRA_VV_M2_MASK, + 11613 => Opcode::PseudoVSSRA_VV_M4, + 11614 => Opcode::PseudoVSSRA_VV_M4_MASK, + 11615 => Opcode::PseudoVSSRA_VV_M8, + 11616 => Opcode::PseudoVSSRA_VV_M8_MASK, + 11617 => Opcode::PseudoVSSRA_VV_MF2, + 11618 => Opcode::PseudoVSSRA_VV_MF2_MASK, + 11619 => Opcode::PseudoVSSRA_VV_MF4, + 11620 => Opcode::PseudoVSSRA_VV_MF4_MASK, + 11621 => Opcode::PseudoVSSRA_VV_MF8, + 11622 => Opcode::PseudoVSSRA_VV_MF8_MASK, + 11623 => Opcode::PseudoVSSRA_VX_M1, + 11624 => Opcode::PseudoVSSRA_VX_M1_MASK, + 11625 => Opcode::PseudoVSSRA_VX_M2, + 11626 => Opcode::PseudoVSSRA_VX_M2_MASK, + 11627 => Opcode::PseudoVSSRA_VX_M4, + 11628 => Opcode::PseudoVSSRA_VX_M4_MASK, + 11629 => Opcode::PseudoVSSRA_VX_M8, + 11630 => Opcode::PseudoVSSRA_VX_M8_MASK, + 11631 => Opcode::PseudoVSSRA_VX_MF2, + 11632 => Opcode::PseudoVSSRA_VX_MF2_MASK, + 11633 => Opcode::PseudoVSSRA_VX_MF4, + 11634 => Opcode::PseudoVSSRA_VX_MF4_MASK, + 11635 => Opcode::PseudoVSSRA_VX_MF8, + 11636 => Opcode::PseudoVSSRA_VX_MF8_MASK, + 11637 => Opcode::PseudoVSSRL_VI_M1, + 11638 => Opcode::PseudoVSSRL_VI_M1_MASK, + 11639 => Opcode::PseudoVSSRL_VI_M2, + 11640 => Opcode::PseudoVSSRL_VI_M2_MASK, + 11641 => Opcode::PseudoVSSRL_VI_M4, + 11642 => Opcode::PseudoVSSRL_VI_M4_MASK, + 11643 => Opcode::PseudoVSSRL_VI_M8, + 11644 => Opcode::PseudoVSSRL_VI_M8_MASK, + 11645 => Opcode::PseudoVSSRL_VI_MF2, + 11646 => Opcode::PseudoVSSRL_VI_MF2_MASK, + 11647 => Opcode::PseudoVSSRL_VI_MF4, + 11648 => Opcode::PseudoVSSRL_VI_MF4_MASK, + 11649 => Opcode::PseudoVSSRL_VI_MF8, + 11650 => Opcode::PseudoVSSRL_VI_MF8_MASK, + 11651 => Opcode::PseudoVSSRL_VV_M1, + 11652 => Opcode::PseudoVSSRL_VV_M1_MASK, + 11653 => Opcode::PseudoVSSRL_VV_M2, + 11654 => Opcode::PseudoVSSRL_VV_M2_MASK, + 11655 => Opcode::PseudoVSSRL_VV_M4, + 11656 => Opcode::PseudoVSSRL_VV_M4_MASK, + 11657 => Opcode::PseudoVSSRL_VV_M8, + 11658 => Opcode::PseudoVSSRL_VV_M8_MASK, + 11659 => Opcode::PseudoVSSRL_VV_MF2, + 11660 => Opcode::PseudoVSSRL_VV_MF2_MASK, + 11661 => Opcode::PseudoVSSRL_VV_MF4, + 11662 => Opcode::PseudoVSSRL_VV_MF4_MASK, + 11663 => Opcode::PseudoVSSRL_VV_MF8, + 11664 => Opcode::PseudoVSSRL_VV_MF8_MASK, + 11665 => Opcode::PseudoVSSRL_VX_M1, + 11666 => Opcode::PseudoVSSRL_VX_M1_MASK, + 11667 => Opcode::PseudoVSSRL_VX_M2, + 11668 => Opcode::PseudoVSSRL_VX_M2_MASK, + 11669 => Opcode::PseudoVSSRL_VX_M4, + 11670 => Opcode::PseudoVSSRL_VX_M4_MASK, + 11671 => Opcode::PseudoVSSRL_VX_M8, + 11672 => Opcode::PseudoVSSRL_VX_M8_MASK, + 11673 => Opcode::PseudoVSSRL_VX_MF2, + 11674 => Opcode::PseudoVSSRL_VX_MF2_MASK, + 11675 => Opcode::PseudoVSSRL_VX_MF4, + 11676 => Opcode::PseudoVSSRL_VX_MF4_MASK, + 11677 => Opcode::PseudoVSSRL_VX_MF8, + 11678 => Opcode::PseudoVSSRL_VX_MF8_MASK, + 11679 => Opcode::PseudoVSSSEG2E16_V_M1, + 11680 => Opcode::PseudoVSSSEG2E16_V_M1_MASK, + 11681 => Opcode::PseudoVSSSEG2E16_V_M2, + 11682 => Opcode::PseudoVSSSEG2E16_V_M2_MASK, + 11683 => Opcode::PseudoVSSSEG2E16_V_M4, + 11684 => Opcode::PseudoVSSSEG2E16_V_M4_MASK, + 11685 => Opcode::PseudoVSSSEG2E16_V_MF2, + 11686 => Opcode::PseudoVSSSEG2E16_V_MF2_MASK, + 11687 => Opcode::PseudoVSSSEG2E16_V_MF4, + 11688 => Opcode::PseudoVSSSEG2E16_V_MF4_MASK, + 11689 => Opcode::PseudoVSSSEG2E32_V_M1, + 11690 => Opcode::PseudoVSSSEG2E32_V_M1_MASK, + 11691 => Opcode::PseudoVSSSEG2E32_V_M2, + 11692 => Opcode::PseudoVSSSEG2E32_V_M2_MASK, + 11693 => Opcode::PseudoVSSSEG2E32_V_M4, + 11694 => Opcode::PseudoVSSSEG2E32_V_M4_MASK, + 11695 => Opcode::PseudoVSSSEG2E32_V_MF2, + 11696 => Opcode::PseudoVSSSEG2E32_V_MF2_MASK, + 11697 => Opcode::PseudoVSSSEG2E64_V_M1, + 11698 => Opcode::PseudoVSSSEG2E64_V_M1_MASK, + 11699 => Opcode::PseudoVSSSEG2E64_V_M2, + 11700 => Opcode::PseudoVSSSEG2E64_V_M2_MASK, + 11701 => Opcode::PseudoVSSSEG2E64_V_M4, + 11702 => Opcode::PseudoVSSSEG2E64_V_M4_MASK, + 11703 => Opcode::PseudoVSSSEG2E8_V_M1, + 11704 => Opcode::PseudoVSSSEG2E8_V_M1_MASK, + 11705 => Opcode::PseudoVSSSEG2E8_V_M2, + 11706 => Opcode::PseudoVSSSEG2E8_V_M2_MASK, + 11707 => Opcode::PseudoVSSSEG2E8_V_M4, + 11708 => Opcode::PseudoVSSSEG2E8_V_M4_MASK, + 11709 => Opcode::PseudoVSSSEG2E8_V_MF2, + 11710 => Opcode::PseudoVSSSEG2E8_V_MF2_MASK, + 11711 => Opcode::PseudoVSSSEG2E8_V_MF4, + 11712 => Opcode::PseudoVSSSEG2E8_V_MF4_MASK, + 11713 => Opcode::PseudoVSSSEG2E8_V_MF8, + 11714 => Opcode::PseudoVSSSEG2E8_V_MF8_MASK, + 11715 => Opcode::PseudoVSSSEG3E16_V_M1, + 11716 => Opcode::PseudoVSSSEG3E16_V_M1_MASK, + 11717 => Opcode::PseudoVSSSEG3E16_V_M2, + 11718 => Opcode::PseudoVSSSEG3E16_V_M2_MASK, + 11719 => Opcode::PseudoVSSSEG3E16_V_MF2, + 11720 => Opcode::PseudoVSSSEG3E16_V_MF2_MASK, + 11721 => Opcode::PseudoVSSSEG3E16_V_MF4, + 11722 => Opcode::PseudoVSSSEG3E16_V_MF4_MASK, + 11723 => Opcode::PseudoVSSSEG3E32_V_M1, + 11724 => Opcode::PseudoVSSSEG3E32_V_M1_MASK, + 11725 => Opcode::PseudoVSSSEG3E32_V_M2, + 11726 => Opcode::PseudoVSSSEG3E32_V_M2_MASK, + 11727 => Opcode::PseudoVSSSEG3E32_V_MF2, + 11728 => Opcode::PseudoVSSSEG3E32_V_MF2_MASK, + 11729 => Opcode::PseudoVSSSEG3E64_V_M1, + 11730 => Opcode::PseudoVSSSEG3E64_V_M1_MASK, + 11731 => Opcode::PseudoVSSSEG3E64_V_M2, + 11732 => Opcode::PseudoVSSSEG3E64_V_M2_MASK, + 11733 => Opcode::PseudoVSSSEG3E8_V_M1, + 11734 => Opcode::PseudoVSSSEG3E8_V_M1_MASK, + 11735 => Opcode::PseudoVSSSEG3E8_V_M2, + 11736 => Opcode::PseudoVSSSEG3E8_V_M2_MASK, + 11737 => Opcode::PseudoVSSSEG3E8_V_MF2, + 11738 => Opcode::PseudoVSSSEG3E8_V_MF2_MASK, + 11739 => Opcode::PseudoVSSSEG3E8_V_MF4, + 11740 => Opcode::PseudoVSSSEG3E8_V_MF4_MASK, + 11741 => Opcode::PseudoVSSSEG3E8_V_MF8, + 11742 => Opcode::PseudoVSSSEG3E8_V_MF8_MASK, + 11743 => Opcode::PseudoVSSSEG4E16_V_M1, + 11744 => Opcode::PseudoVSSSEG4E16_V_M1_MASK, + 11745 => Opcode::PseudoVSSSEG4E16_V_M2, + 11746 => Opcode::PseudoVSSSEG4E16_V_M2_MASK, + 11747 => Opcode::PseudoVSSSEG4E16_V_MF2, + 11748 => Opcode::PseudoVSSSEG4E16_V_MF2_MASK, + 11749 => Opcode::PseudoVSSSEG4E16_V_MF4, + 11750 => Opcode::PseudoVSSSEG4E16_V_MF4_MASK, + 11751 => Opcode::PseudoVSSSEG4E32_V_M1, + 11752 => Opcode::PseudoVSSSEG4E32_V_M1_MASK, + 11753 => Opcode::PseudoVSSSEG4E32_V_M2, + 11754 => Opcode::PseudoVSSSEG4E32_V_M2_MASK, + 11755 => Opcode::PseudoVSSSEG4E32_V_MF2, + 11756 => Opcode::PseudoVSSSEG4E32_V_MF2_MASK, + 11757 => Opcode::PseudoVSSSEG4E64_V_M1, + 11758 => Opcode::PseudoVSSSEG4E64_V_M1_MASK, + 11759 => Opcode::PseudoVSSSEG4E64_V_M2, + 11760 => Opcode::PseudoVSSSEG4E64_V_M2_MASK, + 11761 => Opcode::PseudoVSSSEG4E8_V_M1, + 11762 => Opcode::PseudoVSSSEG4E8_V_M1_MASK, + 11763 => Opcode::PseudoVSSSEG4E8_V_M2, + 11764 => Opcode::PseudoVSSSEG4E8_V_M2_MASK, + 11765 => Opcode::PseudoVSSSEG4E8_V_MF2, + 11766 => Opcode::PseudoVSSSEG4E8_V_MF2_MASK, + 11767 => Opcode::PseudoVSSSEG4E8_V_MF4, + 11768 => Opcode::PseudoVSSSEG4E8_V_MF4_MASK, + 11769 => Opcode::PseudoVSSSEG4E8_V_MF8, + 11770 => Opcode::PseudoVSSSEG4E8_V_MF8_MASK, + 11771 => Opcode::PseudoVSSSEG5E16_V_M1, + 11772 => Opcode::PseudoVSSSEG5E16_V_M1_MASK, + 11773 => Opcode::PseudoVSSSEG5E16_V_MF2, + 11774 => Opcode::PseudoVSSSEG5E16_V_MF2_MASK, + 11775 => Opcode::PseudoVSSSEG5E16_V_MF4, + 11776 => Opcode::PseudoVSSSEG5E16_V_MF4_MASK, + 11777 => Opcode::PseudoVSSSEG5E32_V_M1, + 11778 => Opcode::PseudoVSSSEG5E32_V_M1_MASK, + 11779 => Opcode::PseudoVSSSEG5E32_V_MF2, + 11780 => Opcode::PseudoVSSSEG5E32_V_MF2_MASK, + 11781 => Opcode::PseudoVSSSEG5E64_V_M1, + 11782 => Opcode::PseudoVSSSEG5E64_V_M1_MASK, + 11783 => Opcode::PseudoVSSSEG5E8_V_M1, + 11784 => Opcode::PseudoVSSSEG5E8_V_M1_MASK, + 11785 => Opcode::PseudoVSSSEG5E8_V_MF2, + 11786 => Opcode::PseudoVSSSEG5E8_V_MF2_MASK, + 11787 => Opcode::PseudoVSSSEG5E8_V_MF4, + 11788 => Opcode::PseudoVSSSEG5E8_V_MF4_MASK, + 11789 => Opcode::PseudoVSSSEG5E8_V_MF8, + 11790 => Opcode::PseudoVSSSEG5E8_V_MF8_MASK, + 11791 => Opcode::PseudoVSSSEG6E16_V_M1, + 11792 => Opcode::PseudoVSSSEG6E16_V_M1_MASK, + 11793 => Opcode::PseudoVSSSEG6E16_V_MF2, + 11794 => Opcode::PseudoVSSSEG6E16_V_MF2_MASK, + 11795 => Opcode::PseudoVSSSEG6E16_V_MF4, + 11796 => Opcode::PseudoVSSSEG6E16_V_MF4_MASK, + 11797 => Opcode::PseudoVSSSEG6E32_V_M1, + 11798 => Opcode::PseudoVSSSEG6E32_V_M1_MASK, + 11799 => Opcode::PseudoVSSSEG6E32_V_MF2, + 11800 => Opcode::PseudoVSSSEG6E32_V_MF2_MASK, + 11801 => Opcode::PseudoVSSSEG6E64_V_M1, + 11802 => Opcode::PseudoVSSSEG6E64_V_M1_MASK, + 11803 => Opcode::PseudoVSSSEG6E8_V_M1, + 11804 => Opcode::PseudoVSSSEG6E8_V_M1_MASK, + 11805 => Opcode::PseudoVSSSEG6E8_V_MF2, + 11806 => Opcode::PseudoVSSSEG6E8_V_MF2_MASK, + 11807 => Opcode::PseudoVSSSEG6E8_V_MF4, + 11808 => Opcode::PseudoVSSSEG6E8_V_MF4_MASK, + 11809 => Opcode::PseudoVSSSEG6E8_V_MF8, + 11810 => Opcode::PseudoVSSSEG6E8_V_MF8_MASK, + 11811 => Opcode::PseudoVSSSEG7E16_V_M1, + 11812 => Opcode::PseudoVSSSEG7E16_V_M1_MASK, + 11813 => Opcode::PseudoVSSSEG7E16_V_MF2, + 11814 => Opcode::PseudoVSSSEG7E16_V_MF2_MASK, + 11815 => Opcode::PseudoVSSSEG7E16_V_MF4, + 11816 => Opcode::PseudoVSSSEG7E16_V_MF4_MASK, + 11817 => Opcode::PseudoVSSSEG7E32_V_M1, + 11818 => Opcode::PseudoVSSSEG7E32_V_M1_MASK, + 11819 => Opcode::PseudoVSSSEG7E32_V_MF2, + 11820 => Opcode::PseudoVSSSEG7E32_V_MF2_MASK, + 11821 => Opcode::PseudoVSSSEG7E64_V_M1, + 11822 => Opcode::PseudoVSSSEG7E64_V_M1_MASK, + 11823 => Opcode::PseudoVSSSEG7E8_V_M1, + 11824 => Opcode::PseudoVSSSEG7E8_V_M1_MASK, + 11825 => Opcode::PseudoVSSSEG7E8_V_MF2, + 11826 => Opcode::PseudoVSSSEG7E8_V_MF2_MASK, + 11827 => Opcode::PseudoVSSSEG7E8_V_MF4, + 11828 => Opcode::PseudoVSSSEG7E8_V_MF4_MASK, + 11829 => Opcode::PseudoVSSSEG7E8_V_MF8, + 11830 => Opcode::PseudoVSSSEG7E8_V_MF8_MASK, + 11831 => Opcode::PseudoVSSSEG8E16_V_M1, + 11832 => Opcode::PseudoVSSSEG8E16_V_M1_MASK, + 11833 => Opcode::PseudoVSSSEG8E16_V_MF2, + 11834 => Opcode::PseudoVSSSEG8E16_V_MF2_MASK, + 11835 => Opcode::PseudoVSSSEG8E16_V_MF4, + 11836 => Opcode::PseudoVSSSEG8E16_V_MF4_MASK, + 11837 => Opcode::PseudoVSSSEG8E32_V_M1, + 11838 => Opcode::PseudoVSSSEG8E32_V_M1_MASK, + 11839 => Opcode::PseudoVSSSEG8E32_V_MF2, + 11840 => Opcode::PseudoVSSSEG8E32_V_MF2_MASK, + 11841 => Opcode::PseudoVSSSEG8E64_V_M1, + 11842 => Opcode::PseudoVSSSEG8E64_V_M1_MASK, + 11843 => Opcode::PseudoVSSSEG8E8_V_M1, + 11844 => Opcode::PseudoVSSSEG8E8_V_M1_MASK, + 11845 => Opcode::PseudoVSSSEG8E8_V_MF2, + 11846 => Opcode::PseudoVSSSEG8E8_V_MF2_MASK, + 11847 => Opcode::PseudoVSSSEG8E8_V_MF4, + 11848 => Opcode::PseudoVSSSEG8E8_V_MF4_MASK, + 11849 => Opcode::PseudoVSSSEG8E8_V_MF8, + 11850 => Opcode::PseudoVSSSEG8E8_V_MF8_MASK, + 11851 => Opcode::PseudoVSSUBU_VV_M1, + 11852 => Opcode::PseudoVSSUBU_VV_M1_MASK, + 11853 => Opcode::PseudoVSSUBU_VV_M2, + 11854 => Opcode::PseudoVSSUBU_VV_M2_MASK, + 11855 => Opcode::PseudoVSSUBU_VV_M4, + 11856 => Opcode::PseudoVSSUBU_VV_M4_MASK, + 11857 => Opcode::PseudoVSSUBU_VV_M8, + 11858 => Opcode::PseudoVSSUBU_VV_M8_MASK, + 11859 => Opcode::PseudoVSSUBU_VV_MF2, + 11860 => Opcode::PseudoVSSUBU_VV_MF2_MASK, + 11861 => Opcode::PseudoVSSUBU_VV_MF4, + 11862 => Opcode::PseudoVSSUBU_VV_MF4_MASK, + 11863 => Opcode::PseudoVSSUBU_VV_MF8, + 11864 => Opcode::PseudoVSSUBU_VV_MF8_MASK, + 11865 => Opcode::PseudoVSSUBU_VX_M1, + 11866 => Opcode::PseudoVSSUBU_VX_M1_MASK, + 11867 => Opcode::PseudoVSSUBU_VX_M2, + 11868 => Opcode::PseudoVSSUBU_VX_M2_MASK, + 11869 => Opcode::PseudoVSSUBU_VX_M4, + 11870 => Opcode::PseudoVSSUBU_VX_M4_MASK, + 11871 => Opcode::PseudoVSSUBU_VX_M8, + 11872 => Opcode::PseudoVSSUBU_VX_M8_MASK, + 11873 => Opcode::PseudoVSSUBU_VX_MF2, + 11874 => Opcode::PseudoVSSUBU_VX_MF2_MASK, + 11875 => Opcode::PseudoVSSUBU_VX_MF4, + 11876 => Opcode::PseudoVSSUBU_VX_MF4_MASK, + 11877 => Opcode::PseudoVSSUBU_VX_MF8, + 11878 => Opcode::PseudoVSSUBU_VX_MF8_MASK, + 11879 => Opcode::PseudoVSSUB_VV_M1, + 11880 => Opcode::PseudoVSSUB_VV_M1_MASK, + 11881 => Opcode::PseudoVSSUB_VV_M2, + 11882 => Opcode::PseudoVSSUB_VV_M2_MASK, + 11883 => Opcode::PseudoVSSUB_VV_M4, + 11884 => Opcode::PseudoVSSUB_VV_M4_MASK, + 11885 => Opcode::PseudoVSSUB_VV_M8, + 11886 => Opcode::PseudoVSSUB_VV_M8_MASK, + 11887 => Opcode::PseudoVSSUB_VV_MF2, + 11888 => Opcode::PseudoVSSUB_VV_MF2_MASK, + 11889 => Opcode::PseudoVSSUB_VV_MF4, + 11890 => Opcode::PseudoVSSUB_VV_MF4_MASK, + 11891 => Opcode::PseudoVSSUB_VV_MF8, + 11892 => Opcode::PseudoVSSUB_VV_MF8_MASK, + 11893 => Opcode::PseudoVSSUB_VX_M1, + 11894 => Opcode::PseudoVSSUB_VX_M1_MASK, + 11895 => Opcode::PseudoVSSUB_VX_M2, + 11896 => Opcode::PseudoVSSUB_VX_M2_MASK, + 11897 => Opcode::PseudoVSSUB_VX_M4, + 11898 => Opcode::PseudoVSSUB_VX_M4_MASK, + 11899 => Opcode::PseudoVSSUB_VX_M8, + 11900 => Opcode::PseudoVSSUB_VX_M8_MASK, + 11901 => Opcode::PseudoVSSUB_VX_MF2, + 11902 => Opcode::PseudoVSSUB_VX_MF2_MASK, + 11903 => Opcode::PseudoVSSUB_VX_MF4, + 11904 => Opcode::PseudoVSSUB_VX_MF4_MASK, + 11905 => Opcode::PseudoVSSUB_VX_MF8, + 11906 => Opcode::PseudoVSSUB_VX_MF8_MASK, + 11907 => Opcode::PseudoVSUB_VV_M1, + 11908 => Opcode::PseudoVSUB_VV_M1_MASK, + 11909 => Opcode::PseudoVSUB_VV_M2, + 11910 => Opcode::PseudoVSUB_VV_M2_MASK, + 11911 => Opcode::PseudoVSUB_VV_M4, + 11912 => Opcode::PseudoVSUB_VV_M4_MASK, + 11913 => Opcode::PseudoVSUB_VV_M8, + 11914 => Opcode::PseudoVSUB_VV_M8_MASK, + 11915 => Opcode::PseudoVSUB_VV_MF2, + 11916 => Opcode::PseudoVSUB_VV_MF2_MASK, + 11917 => Opcode::PseudoVSUB_VV_MF4, + 11918 => Opcode::PseudoVSUB_VV_MF4_MASK, + 11919 => Opcode::PseudoVSUB_VV_MF8, + 11920 => Opcode::PseudoVSUB_VV_MF8_MASK, + 11921 => Opcode::PseudoVSUB_VX_M1, + 11922 => Opcode::PseudoVSUB_VX_M1_MASK, + 11923 => Opcode::PseudoVSUB_VX_M2, + 11924 => Opcode::PseudoVSUB_VX_M2_MASK, + 11925 => Opcode::PseudoVSUB_VX_M4, + 11926 => Opcode::PseudoVSUB_VX_M4_MASK, + 11927 => Opcode::PseudoVSUB_VX_M8, + 11928 => Opcode::PseudoVSUB_VX_M8_MASK, + 11929 => Opcode::PseudoVSUB_VX_MF2, + 11930 => Opcode::PseudoVSUB_VX_MF2_MASK, + 11931 => Opcode::PseudoVSUB_VX_MF4, + 11932 => Opcode::PseudoVSUB_VX_MF4_MASK, + 11933 => Opcode::PseudoVSUB_VX_MF8, + 11934 => Opcode::PseudoVSUB_VX_MF8_MASK, + 11935 => Opcode::PseudoVSUXEI16_V_M1_M1, + 11936 => Opcode::PseudoVSUXEI16_V_M1_M1_MASK, + 11937 => Opcode::PseudoVSUXEI16_V_M1_M2, + 11938 => Opcode::PseudoVSUXEI16_V_M1_M2_MASK, + 11939 => Opcode::PseudoVSUXEI16_V_M1_M4, + 11940 => Opcode::PseudoVSUXEI16_V_M1_M4_MASK, + 11941 => Opcode::PseudoVSUXEI16_V_M1_MF2, + 11942 => Opcode::PseudoVSUXEI16_V_M1_MF2_MASK, + 11943 => Opcode::PseudoVSUXEI16_V_M2_M1, + 11944 => Opcode::PseudoVSUXEI16_V_M2_M1_MASK, + 11945 => Opcode::PseudoVSUXEI16_V_M2_M2, + 11946 => Opcode::PseudoVSUXEI16_V_M2_M2_MASK, + 11947 => Opcode::PseudoVSUXEI16_V_M2_M4, + 11948 => Opcode::PseudoVSUXEI16_V_M2_M4_MASK, + 11949 => Opcode::PseudoVSUXEI16_V_M2_M8, + 11950 => Opcode::PseudoVSUXEI16_V_M2_M8_MASK, + 11951 => Opcode::PseudoVSUXEI16_V_M4_M2, + 11952 => Opcode::PseudoVSUXEI16_V_M4_M2_MASK, + 11953 => Opcode::PseudoVSUXEI16_V_M4_M4, + 11954 => Opcode::PseudoVSUXEI16_V_M4_M4_MASK, + 11955 => Opcode::PseudoVSUXEI16_V_M4_M8, + 11956 => Opcode::PseudoVSUXEI16_V_M4_M8_MASK, + 11957 => Opcode::PseudoVSUXEI16_V_M8_M4, + 11958 => Opcode::PseudoVSUXEI16_V_M8_M4_MASK, + 11959 => Opcode::PseudoVSUXEI16_V_M8_M8, + 11960 => Opcode::PseudoVSUXEI16_V_M8_M8_MASK, + 11961 => Opcode::PseudoVSUXEI16_V_MF2_M1, + 11962 => Opcode::PseudoVSUXEI16_V_MF2_M1_MASK, + 11963 => Opcode::PseudoVSUXEI16_V_MF2_M2, + 11964 => Opcode::PseudoVSUXEI16_V_MF2_M2_MASK, + 11965 => Opcode::PseudoVSUXEI16_V_MF2_MF2, + 11966 => Opcode::PseudoVSUXEI16_V_MF2_MF2_MASK, + 11967 => Opcode::PseudoVSUXEI16_V_MF2_MF4, + 11968 => Opcode::PseudoVSUXEI16_V_MF2_MF4_MASK, + 11969 => Opcode::PseudoVSUXEI16_V_MF4_M1, + 11970 => Opcode::PseudoVSUXEI16_V_MF4_M1_MASK, + 11971 => Opcode::PseudoVSUXEI16_V_MF4_MF2, + 11972 => Opcode::PseudoVSUXEI16_V_MF4_MF2_MASK, + 11973 => Opcode::PseudoVSUXEI16_V_MF4_MF4, + 11974 => Opcode::PseudoVSUXEI16_V_MF4_MF4_MASK, + 11975 => Opcode::PseudoVSUXEI16_V_MF4_MF8, + 11976 => Opcode::PseudoVSUXEI16_V_MF4_MF8_MASK, + 11977 => Opcode::PseudoVSUXEI32_V_M1_M1, + 11978 => Opcode::PseudoVSUXEI32_V_M1_M1_MASK, + 11979 => Opcode::PseudoVSUXEI32_V_M1_M2, + 11980 => Opcode::PseudoVSUXEI32_V_M1_M2_MASK, + 11981 => Opcode::PseudoVSUXEI32_V_M1_MF2, + 11982 => Opcode::PseudoVSUXEI32_V_M1_MF2_MASK, + 11983 => Opcode::PseudoVSUXEI32_V_M1_MF4, + 11984 => Opcode::PseudoVSUXEI32_V_M1_MF4_MASK, + 11985 => Opcode::PseudoVSUXEI32_V_M2_M1, + 11986 => Opcode::PseudoVSUXEI32_V_M2_M1_MASK, + 11987 => Opcode::PseudoVSUXEI32_V_M2_M2, + 11988 => Opcode::PseudoVSUXEI32_V_M2_M2_MASK, + 11989 => Opcode::PseudoVSUXEI32_V_M2_M4, + 11990 => Opcode::PseudoVSUXEI32_V_M2_M4_MASK, + 11991 => Opcode::PseudoVSUXEI32_V_M2_MF2, + 11992 => Opcode::PseudoVSUXEI32_V_M2_MF2_MASK, + 11993 => Opcode::PseudoVSUXEI32_V_M4_M1, + 11994 => Opcode::PseudoVSUXEI32_V_M4_M1_MASK, + 11995 => Opcode::PseudoVSUXEI32_V_M4_M2, + 11996 => Opcode::PseudoVSUXEI32_V_M4_M2_MASK, + 11997 => Opcode::PseudoVSUXEI32_V_M4_M4, + 11998 => Opcode::PseudoVSUXEI32_V_M4_M4_MASK, + 11999 => Opcode::PseudoVSUXEI32_V_M4_M8, + 12000 => Opcode::PseudoVSUXEI32_V_M4_M8_MASK, + 12001 => Opcode::PseudoVSUXEI32_V_M8_M2, + 12002 => Opcode::PseudoVSUXEI32_V_M8_M2_MASK, + 12003 => Opcode::PseudoVSUXEI32_V_M8_M4, + 12004 => Opcode::PseudoVSUXEI32_V_M8_M4_MASK, + 12005 => Opcode::PseudoVSUXEI32_V_M8_M8, + 12006 => Opcode::PseudoVSUXEI32_V_M8_M8_MASK, + 12007 => Opcode::PseudoVSUXEI32_V_MF2_M1, + 12008 => Opcode::PseudoVSUXEI32_V_MF2_M1_MASK, + 12009 => Opcode::PseudoVSUXEI32_V_MF2_MF2, + 12010 => Opcode::PseudoVSUXEI32_V_MF2_MF2_MASK, + 12011 => Opcode::PseudoVSUXEI32_V_MF2_MF4, + 12012 => Opcode::PseudoVSUXEI32_V_MF2_MF4_MASK, + 12013 => Opcode::PseudoVSUXEI32_V_MF2_MF8, + 12014 => Opcode::PseudoVSUXEI32_V_MF2_MF8_MASK, + 12015 => Opcode::PseudoVSUXEI64_V_M1_M1, + 12016 => Opcode::PseudoVSUXEI64_V_M1_M1_MASK, + 12017 => Opcode::PseudoVSUXEI64_V_M1_MF2, + 12018 => Opcode::PseudoVSUXEI64_V_M1_MF2_MASK, + 12019 => Opcode::PseudoVSUXEI64_V_M1_MF4, + 12020 => Opcode::PseudoVSUXEI64_V_M1_MF4_MASK, + 12021 => Opcode::PseudoVSUXEI64_V_M1_MF8, + 12022 => Opcode::PseudoVSUXEI64_V_M1_MF8_MASK, + 12023 => Opcode::PseudoVSUXEI64_V_M2_M1, + 12024 => Opcode::PseudoVSUXEI64_V_M2_M1_MASK, + 12025 => Opcode::PseudoVSUXEI64_V_M2_M2, + 12026 => Opcode::PseudoVSUXEI64_V_M2_M2_MASK, + 12027 => Opcode::PseudoVSUXEI64_V_M2_MF2, + 12028 => Opcode::PseudoVSUXEI64_V_M2_MF2_MASK, + 12029 => Opcode::PseudoVSUXEI64_V_M2_MF4, + 12030 => Opcode::PseudoVSUXEI64_V_M2_MF4_MASK, + 12031 => Opcode::PseudoVSUXEI64_V_M4_M1, + 12032 => Opcode::PseudoVSUXEI64_V_M4_M1_MASK, + 12033 => Opcode::PseudoVSUXEI64_V_M4_M2, + 12034 => Opcode::PseudoVSUXEI64_V_M4_M2_MASK, + 12035 => Opcode::PseudoVSUXEI64_V_M4_M4, + 12036 => Opcode::PseudoVSUXEI64_V_M4_M4_MASK, + 12037 => Opcode::PseudoVSUXEI64_V_M4_MF2, + 12038 => Opcode::PseudoVSUXEI64_V_M4_MF2_MASK, + 12039 => Opcode::PseudoVSUXEI64_V_M8_M1, + 12040 => Opcode::PseudoVSUXEI64_V_M8_M1_MASK, + 12041 => Opcode::PseudoVSUXEI64_V_M8_M2, + 12042 => Opcode::PseudoVSUXEI64_V_M8_M2_MASK, + 12043 => Opcode::PseudoVSUXEI64_V_M8_M4, + 12044 => Opcode::PseudoVSUXEI64_V_M8_M4_MASK, + 12045 => Opcode::PseudoVSUXEI64_V_M8_M8, + 12046 => Opcode::PseudoVSUXEI64_V_M8_M8_MASK, + 12047 => Opcode::PseudoVSUXEI8_V_M1_M1, + 12048 => Opcode::PseudoVSUXEI8_V_M1_M1_MASK, + 12049 => Opcode::PseudoVSUXEI8_V_M1_M2, + 12050 => Opcode::PseudoVSUXEI8_V_M1_M2_MASK, + 12051 => Opcode::PseudoVSUXEI8_V_M1_M4, + 12052 => Opcode::PseudoVSUXEI8_V_M1_M4_MASK, + 12053 => Opcode::PseudoVSUXEI8_V_M1_M8, + 12054 => Opcode::PseudoVSUXEI8_V_M1_M8_MASK, + 12055 => Opcode::PseudoVSUXEI8_V_M2_M2, + 12056 => Opcode::PseudoVSUXEI8_V_M2_M2_MASK, + 12057 => Opcode::PseudoVSUXEI8_V_M2_M4, + 12058 => Opcode::PseudoVSUXEI8_V_M2_M4_MASK, + 12059 => Opcode::PseudoVSUXEI8_V_M2_M8, + 12060 => Opcode::PseudoVSUXEI8_V_M2_M8_MASK, + 12061 => Opcode::PseudoVSUXEI8_V_M4_M4, + 12062 => Opcode::PseudoVSUXEI8_V_M4_M4_MASK, + 12063 => Opcode::PseudoVSUXEI8_V_M4_M8, + 12064 => Opcode::PseudoVSUXEI8_V_M4_M8_MASK, + 12065 => Opcode::PseudoVSUXEI8_V_M8_M8, + 12066 => Opcode::PseudoVSUXEI8_V_M8_M8_MASK, + 12067 => Opcode::PseudoVSUXEI8_V_MF2_M1, + 12068 => Opcode::PseudoVSUXEI8_V_MF2_M1_MASK, + 12069 => Opcode::PseudoVSUXEI8_V_MF2_M2, + 12070 => Opcode::PseudoVSUXEI8_V_MF2_M2_MASK, + 12071 => Opcode::PseudoVSUXEI8_V_MF2_M4, + 12072 => Opcode::PseudoVSUXEI8_V_MF2_M4_MASK, + 12073 => Opcode::PseudoVSUXEI8_V_MF2_MF2, + 12074 => Opcode::PseudoVSUXEI8_V_MF2_MF2_MASK, + 12075 => Opcode::PseudoVSUXEI8_V_MF4_M1, + 12076 => Opcode::PseudoVSUXEI8_V_MF4_M1_MASK, + 12077 => Opcode::PseudoVSUXEI8_V_MF4_M2, + 12078 => Opcode::PseudoVSUXEI8_V_MF4_M2_MASK, + 12079 => Opcode::PseudoVSUXEI8_V_MF4_MF2, + 12080 => Opcode::PseudoVSUXEI8_V_MF4_MF2_MASK, + 12081 => Opcode::PseudoVSUXEI8_V_MF4_MF4, + 12082 => Opcode::PseudoVSUXEI8_V_MF4_MF4_MASK, + 12083 => Opcode::PseudoVSUXEI8_V_MF8_M1, + 12084 => Opcode::PseudoVSUXEI8_V_MF8_M1_MASK, + 12085 => Opcode::PseudoVSUXEI8_V_MF8_MF2, + 12086 => Opcode::PseudoVSUXEI8_V_MF8_MF2_MASK, + 12087 => Opcode::PseudoVSUXEI8_V_MF8_MF4, + 12088 => Opcode::PseudoVSUXEI8_V_MF8_MF4_MASK, + 12089 => Opcode::PseudoVSUXEI8_V_MF8_MF8, + 12090 => Opcode::PseudoVSUXEI8_V_MF8_MF8_MASK, + 12091 => Opcode::PseudoVSUXSEG2EI16_V_M1_M1, + 12092 => Opcode::PseudoVSUXSEG2EI16_V_M1_M1_MASK, + 12093 => Opcode::PseudoVSUXSEG2EI16_V_M1_M2, + 12094 => Opcode::PseudoVSUXSEG2EI16_V_M1_M2_MASK, + 12095 => Opcode::PseudoVSUXSEG2EI16_V_M1_M4, + 12096 => Opcode::PseudoVSUXSEG2EI16_V_M1_M4_MASK, + 12097 => Opcode::PseudoVSUXSEG2EI16_V_M1_MF2, + 12098 => Opcode::PseudoVSUXSEG2EI16_V_M1_MF2_MASK, + 12099 => Opcode::PseudoVSUXSEG2EI16_V_M2_M1, + 12100 => Opcode::PseudoVSUXSEG2EI16_V_M2_M1_MASK, + 12101 => Opcode::PseudoVSUXSEG2EI16_V_M2_M2, + 12102 => Opcode::PseudoVSUXSEG2EI16_V_M2_M2_MASK, + 12103 => Opcode::PseudoVSUXSEG2EI16_V_M2_M4, + 12104 => Opcode::PseudoVSUXSEG2EI16_V_M2_M4_MASK, + 12105 => Opcode::PseudoVSUXSEG2EI16_V_M4_M2, + 12106 => Opcode::PseudoVSUXSEG2EI16_V_M4_M2_MASK, + 12107 => Opcode::PseudoVSUXSEG2EI16_V_M4_M4, + 12108 => Opcode::PseudoVSUXSEG2EI16_V_M4_M4_MASK, + 12109 => Opcode::PseudoVSUXSEG2EI16_V_M8_M4, + 12110 => Opcode::PseudoVSUXSEG2EI16_V_M8_M4_MASK, + 12111 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M1, + 12112 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M1_MASK, + 12113 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M2, + 12114 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M2_MASK, + 12115 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF2, + 12116 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, + 12117 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF4, + 12118 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, + 12119 => Opcode::PseudoVSUXSEG2EI16_V_MF4_M1, + 12120 => Opcode::PseudoVSUXSEG2EI16_V_MF4_M1_MASK, + 12121 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF2, + 12122 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, + 12123 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF4, + 12124 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, + 12125 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF8, + 12126 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, + 12127 => Opcode::PseudoVSUXSEG2EI32_V_M1_M1, + 12128 => Opcode::PseudoVSUXSEG2EI32_V_M1_M1_MASK, + 12129 => Opcode::PseudoVSUXSEG2EI32_V_M1_M2, + 12130 => Opcode::PseudoVSUXSEG2EI32_V_M1_M2_MASK, + 12131 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF2, + 12132 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF2_MASK, + 12133 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF4, + 12134 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF4_MASK, + 12135 => Opcode::PseudoVSUXSEG2EI32_V_M2_M1, + 12136 => Opcode::PseudoVSUXSEG2EI32_V_M2_M1_MASK, + 12137 => Opcode::PseudoVSUXSEG2EI32_V_M2_M2, + 12138 => Opcode::PseudoVSUXSEG2EI32_V_M2_M2_MASK, + 12139 => Opcode::PseudoVSUXSEG2EI32_V_M2_M4, + 12140 => Opcode::PseudoVSUXSEG2EI32_V_M2_M4_MASK, + 12141 => Opcode::PseudoVSUXSEG2EI32_V_M2_MF2, + 12142 => Opcode::PseudoVSUXSEG2EI32_V_M2_MF2_MASK, + 12143 => Opcode::PseudoVSUXSEG2EI32_V_M4_M1, + 12144 => Opcode::PseudoVSUXSEG2EI32_V_M4_M1_MASK, + 12145 => Opcode::PseudoVSUXSEG2EI32_V_M4_M2, + 12146 => Opcode::PseudoVSUXSEG2EI32_V_M4_M2_MASK, + 12147 => Opcode::PseudoVSUXSEG2EI32_V_M4_M4, + 12148 => Opcode::PseudoVSUXSEG2EI32_V_M4_M4_MASK, + 12149 => Opcode::PseudoVSUXSEG2EI32_V_M8_M2, + 12150 => Opcode::PseudoVSUXSEG2EI32_V_M8_M2_MASK, + 12151 => Opcode::PseudoVSUXSEG2EI32_V_M8_M4, + 12152 => Opcode::PseudoVSUXSEG2EI32_V_M8_M4_MASK, + 12153 => Opcode::PseudoVSUXSEG2EI32_V_MF2_M1, + 12154 => Opcode::PseudoVSUXSEG2EI32_V_MF2_M1_MASK, + 12155 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF2, + 12156 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, + 12157 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF4, + 12158 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, + 12159 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF8, + 12160 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, + 12161 => Opcode::PseudoVSUXSEG2EI64_V_M1_M1, + 12162 => Opcode::PseudoVSUXSEG2EI64_V_M1_M1_MASK, + 12163 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF2, + 12164 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF2_MASK, + 12165 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF4, + 12166 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF4_MASK, + 12167 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF8, + 12168 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF8_MASK, + 12169 => Opcode::PseudoVSUXSEG2EI64_V_M2_M1, + 12170 => Opcode::PseudoVSUXSEG2EI64_V_M2_M1_MASK, + 12171 => Opcode::PseudoVSUXSEG2EI64_V_M2_M2, + 12172 => Opcode::PseudoVSUXSEG2EI64_V_M2_M2_MASK, + 12173 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF2, + 12174 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF2_MASK, + 12175 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF4, + 12176 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF4_MASK, + 12177 => Opcode::PseudoVSUXSEG2EI64_V_M4_M1, + 12178 => Opcode::PseudoVSUXSEG2EI64_V_M4_M1_MASK, + 12179 => Opcode::PseudoVSUXSEG2EI64_V_M4_M2, + 12180 => Opcode::PseudoVSUXSEG2EI64_V_M4_M2_MASK, + 12181 => Opcode::PseudoVSUXSEG2EI64_V_M4_M4, + 12182 => Opcode::PseudoVSUXSEG2EI64_V_M4_M4_MASK, + 12183 => Opcode::PseudoVSUXSEG2EI64_V_M4_MF2, + 12184 => Opcode::PseudoVSUXSEG2EI64_V_M4_MF2_MASK, + 12185 => Opcode::PseudoVSUXSEG2EI64_V_M8_M1, + 12186 => Opcode::PseudoVSUXSEG2EI64_V_M8_M1_MASK, + 12187 => Opcode::PseudoVSUXSEG2EI64_V_M8_M2, + 12188 => Opcode::PseudoVSUXSEG2EI64_V_M8_M2_MASK, + 12189 => Opcode::PseudoVSUXSEG2EI64_V_M8_M4, + 12190 => Opcode::PseudoVSUXSEG2EI64_V_M8_M4_MASK, + 12191 => Opcode::PseudoVSUXSEG2EI8_V_M1_M1, + 12192 => Opcode::PseudoVSUXSEG2EI8_V_M1_M1_MASK, + 12193 => Opcode::PseudoVSUXSEG2EI8_V_M1_M2, + 12194 => Opcode::PseudoVSUXSEG2EI8_V_M1_M2_MASK, + 12195 => Opcode::PseudoVSUXSEG2EI8_V_M1_M4, + 12196 => Opcode::PseudoVSUXSEG2EI8_V_M1_M4_MASK, + 12197 => Opcode::PseudoVSUXSEG2EI8_V_M2_M2, + 12198 => Opcode::PseudoVSUXSEG2EI8_V_M2_M2_MASK, + 12199 => Opcode::PseudoVSUXSEG2EI8_V_M2_M4, + 12200 => Opcode::PseudoVSUXSEG2EI8_V_M2_M4_MASK, + 12201 => Opcode::PseudoVSUXSEG2EI8_V_M4_M4, + 12202 => Opcode::PseudoVSUXSEG2EI8_V_M4_M4_MASK, + 12203 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M1, + 12204 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M1_MASK, + 12205 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M2, + 12206 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M2_MASK, + 12207 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M4, + 12208 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M4_MASK, + 12209 => Opcode::PseudoVSUXSEG2EI8_V_MF2_MF2, + 12210 => Opcode::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, + 12211 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M1, + 12212 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M1_MASK, + 12213 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M2, + 12214 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M2_MASK, + 12215 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF2, + 12216 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, + 12217 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF4, + 12218 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, + 12219 => Opcode::PseudoVSUXSEG2EI8_V_MF8_M1, + 12220 => Opcode::PseudoVSUXSEG2EI8_V_MF8_M1_MASK, + 12221 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF2, + 12222 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, + 12223 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF4, + 12224 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, + 12225 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF8, + 12226 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, + 12227 => Opcode::PseudoVSUXSEG3EI16_V_M1_M1, + 12228 => Opcode::PseudoVSUXSEG3EI16_V_M1_M1_MASK, + 12229 => Opcode::PseudoVSUXSEG3EI16_V_M1_M2, + 12230 => Opcode::PseudoVSUXSEG3EI16_V_M1_M2_MASK, + 12231 => Opcode::PseudoVSUXSEG3EI16_V_M1_MF2, + 12232 => Opcode::PseudoVSUXSEG3EI16_V_M1_MF2_MASK, + 12233 => Opcode::PseudoVSUXSEG3EI16_V_M2_M1, + 12234 => Opcode::PseudoVSUXSEG3EI16_V_M2_M1_MASK, + 12235 => Opcode::PseudoVSUXSEG3EI16_V_M2_M2, + 12236 => Opcode::PseudoVSUXSEG3EI16_V_M2_M2_MASK, + 12237 => Opcode::PseudoVSUXSEG3EI16_V_M4_M2, + 12238 => Opcode::PseudoVSUXSEG3EI16_V_M4_M2_MASK, + 12239 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M1, + 12240 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M1_MASK, + 12241 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M2, + 12242 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M2_MASK, + 12243 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF2, + 12244 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, + 12245 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF4, + 12246 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, + 12247 => Opcode::PseudoVSUXSEG3EI16_V_MF4_M1, + 12248 => Opcode::PseudoVSUXSEG3EI16_V_MF4_M1_MASK, + 12249 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF2, + 12250 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, + 12251 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF4, + 12252 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, + 12253 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF8, + 12254 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, + 12255 => Opcode::PseudoVSUXSEG3EI32_V_M1_M1, + 12256 => Opcode::PseudoVSUXSEG3EI32_V_M1_M1_MASK, + 12257 => Opcode::PseudoVSUXSEG3EI32_V_M1_M2, + 12258 => Opcode::PseudoVSUXSEG3EI32_V_M1_M2_MASK, + 12259 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF2, + 12260 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF2_MASK, + 12261 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF4, + 12262 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF4_MASK, + 12263 => Opcode::PseudoVSUXSEG3EI32_V_M2_M1, + 12264 => Opcode::PseudoVSUXSEG3EI32_V_M2_M1_MASK, + 12265 => Opcode::PseudoVSUXSEG3EI32_V_M2_M2, + 12266 => Opcode::PseudoVSUXSEG3EI32_V_M2_M2_MASK, + 12267 => Opcode::PseudoVSUXSEG3EI32_V_M2_MF2, + 12268 => Opcode::PseudoVSUXSEG3EI32_V_M2_MF2_MASK, + 12269 => Opcode::PseudoVSUXSEG3EI32_V_M4_M1, + 12270 => Opcode::PseudoVSUXSEG3EI32_V_M4_M1_MASK, + 12271 => Opcode::PseudoVSUXSEG3EI32_V_M4_M2, + 12272 => Opcode::PseudoVSUXSEG3EI32_V_M4_M2_MASK, + 12273 => Opcode::PseudoVSUXSEG3EI32_V_M8_M2, + 12274 => Opcode::PseudoVSUXSEG3EI32_V_M8_M2_MASK, + 12275 => Opcode::PseudoVSUXSEG3EI32_V_MF2_M1, + 12276 => Opcode::PseudoVSUXSEG3EI32_V_MF2_M1_MASK, + 12277 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF2, + 12278 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, + 12279 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF4, + 12280 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, + 12281 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF8, + 12282 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, + 12283 => Opcode::PseudoVSUXSEG3EI64_V_M1_M1, + 12284 => Opcode::PseudoVSUXSEG3EI64_V_M1_M1_MASK, + 12285 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF2, + 12286 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF2_MASK, + 12287 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF4, + 12288 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF4_MASK, + 12289 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF8, + 12290 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF8_MASK, + 12291 => Opcode::PseudoVSUXSEG3EI64_V_M2_M1, + 12292 => Opcode::PseudoVSUXSEG3EI64_V_M2_M1_MASK, + 12293 => Opcode::PseudoVSUXSEG3EI64_V_M2_M2, + 12294 => Opcode::PseudoVSUXSEG3EI64_V_M2_M2_MASK, + 12295 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF2, + 12296 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF2_MASK, + 12297 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF4, + 12298 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF4_MASK, + 12299 => Opcode::PseudoVSUXSEG3EI64_V_M4_M1, + 12300 => Opcode::PseudoVSUXSEG3EI64_V_M4_M1_MASK, + 12301 => Opcode::PseudoVSUXSEG3EI64_V_M4_M2, + 12302 => Opcode::PseudoVSUXSEG3EI64_V_M4_M2_MASK, + 12303 => Opcode::PseudoVSUXSEG3EI64_V_M4_MF2, + 12304 => Opcode::PseudoVSUXSEG3EI64_V_M4_MF2_MASK, + 12305 => Opcode::PseudoVSUXSEG3EI64_V_M8_M1, + 12306 => Opcode::PseudoVSUXSEG3EI64_V_M8_M1_MASK, + 12307 => Opcode::PseudoVSUXSEG3EI64_V_M8_M2, + 12308 => Opcode::PseudoVSUXSEG3EI64_V_M8_M2_MASK, + 12309 => Opcode::PseudoVSUXSEG3EI8_V_M1_M1, + 12310 => Opcode::PseudoVSUXSEG3EI8_V_M1_M1_MASK, + 12311 => Opcode::PseudoVSUXSEG3EI8_V_M1_M2, + 12312 => Opcode::PseudoVSUXSEG3EI8_V_M1_M2_MASK, + 12313 => Opcode::PseudoVSUXSEG3EI8_V_M2_M2, + 12314 => Opcode::PseudoVSUXSEG3EI8_V_M2_M2_MASK, + 12315 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M1, + 12316 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M1_MASK, + 12317 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M2, + 12318 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M2_MASK, + 12319 => Opcode::PseudoVSUXSEG3EI8_V_MF2_MF2, + 12320 => Opcode::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, + 12321 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M1, + 12322 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M1_MASK, + 12323 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M2, + 12324 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M2_MASK, + 12325 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF2, + 12326 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, + 12327 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF4, + 12328 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, + 12329 => Opcode::PseudoVSUXSEG3EI8_V_MF8_M1, + 12330 => Opcode::PseudoVSUXSEG3EI8_V_MF8_M1_MASK, + 12331 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF2, + 12332 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, + 12333 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF4, + 12334 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, + 12335 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF8, + 12336 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, + 12337 => Opcode::PseudoVSUXSEG4EI16_V_M1_M1, + 12338 => Opcode::PseudoVSUXSEG4EI16_V_M1_M1_MASK, + 12339 => Opcode::PseudoVSUXSEG4EI16_V_M1_M2, + 12340 => Opcode::PseudoVSUXSEG4EI16_V_M1_M2_MASK, + 12341 => Opcode::PseudoVSUXSEG4EI16_V_M1_MF2, + 12342 => Opcode::PseudoVSUXSEG4EI16_V_M1_MF2_MASK, + 12343 => Opcode::PseudoVSUXSEG4EI16_V_M2_M1, + 12344 => Opcode::PseudoVSUXSEG4EI16_V_M2_M1_MASK, + 12345 => Opcode::PseudoVSUXSEG4EI16_V_M2_M2, + 12346 => Opcode::PseudoVSUXSEG4EI16_V_M2_M2_MASK, + 12347 => Opcode::PseudoVSUXSEG4EI16_V_M4_M2, + 12348 => Opcode::PseudoVSUXSEG4EI16_V_M4_M2_MASK, + 12349 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M1, + 12350 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M1_MASK, + 12351 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M2, + 12352 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M2_MASK, + 12353 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF2, + 12354 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, + 12355 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF4, + 12356 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, + 12357 => Opcode::PseudoVSUXSEG4EI16_V_MF4_M1, + 12358 => Opcode::PseudoVSUXSEG4EI16_V_MF4_M1_MASK, + 12359 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF2, + 12360 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, + 12361 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF4, + 12362 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, + 12363 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF8, + 12364 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, + 12365 => Opcode::PseudoVSUXSEG4EI32_V_M1_M1, + 12366 => Opcode::PseudoVSUXSEG4EI32_V_M1_M1_MASK, + 12367 => Opcode::PseudoVSUXSEG4EI32_V_M1_M2, + 12368 => Opcode::PseudoVSUXSEG4EI32_V_M1_M2_MASK, + 12369 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF2, + 12370 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF2_MASK, + 12371 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF4, + 12372 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF4_MASK, + 12373 => Opcode::PseudoVSUXSEG4EI32_V_M2_M1, + 12374 => Opcode::PseudoVSUXSEG4EI32_V_M2_M1_MASK, + 12375 => Opcode::PseudoVSUXSEG4EI32_V_M2_M2, + 12376 => Opcode::PseudoVSUXSEG4EI32_V_M2_M2_MASK, + 12377 => Opcode::PseudoVSUXSEG4EI32_V_M2_MF2, + 12378 => Opcode::PseudoVSUXSEG4EI32_V_M2_MF2_MASK, + 12379 => Opcode::PseudoVSUXSEG4EI32_V_M4_M1, + 12380 => Opcode::PseudoVSUXSEG4EI32_V_M4_M1_MASK, + 12381 => Opcode::PseudoVSUXSEG4EI32_V_M4_M2, + 12382 => Opcode::PseudoVSUXSEG4EI32_V_M4_M2_MASK, + 12383 => Opcode::PseudoVSUXSEG4EI32_V_M8_M2, + 12384 => Opcode::PseudoVSUXSEG4EI32_V_M8_M2_MASK, + 12385 => Opcode::PseudoVSUXSEG4EI32_V_MF2_M1, + 12386 => Opcode::PseudoVSUXSEG4EI32_V_MF2_M1_MASK, + 12387 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF2, + 12388 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, + 12389 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF4, + 12390 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, + 12391 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF8, + 12392 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, + 12393 => Opcode::PseudoVSUXSEG4EI64_V_M1_M1, + 12394 => Opcode::PseudoVSUXSEG4EI64_V_M1_M1_MASK, + 12395 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF2, + 12396 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF2_MASK, + 12397 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF4, + 12398 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF4_MASK, + 12399 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF8, + 12400 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF8_MASK, + 12401 => Opcode::PseudoVSUXSEG4EI64_V_M2_M1, + 12402 => Opcode::PseudoVSUXSEG4EI64_V_M2_M1_MASK, + 12403 => Opcode::PseudoVSUXSEG4EI64_V_M2_M2, + 12404 => Opcode::PseudoVSUXSEG4EI64_V_M2_M2_MASK, + 12405 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF2, + 12406 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF2_MASK, + 12407 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF4, + 12408 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF4_MASK, + 12409 => Opcode::PseudoVSUXSEG4EI64_V_M4_M1, + 12410 => Opcode::PseudoVSUXSEG4EI64_V_M4_M1_MASK, + 12411 => Opcode::PseudoVSUXSEG4EI64_V_M4_M2, + 12412 => Opcode::PseudoVSUXSEG4EI64_V_M4_M2_MASK, + 12413 => Opcode::PseudoVSUXSEG4EI64_V_M4_MF2, + 12414 => Opcode::PseudoVSUXSEG4EI64_V_M4_MF2_MASK, + 12415 => Opcode::PseudoVSUXSEG4EI64_V_M8_M1, + 12416 => Opcode::PseudoVSUXSEG4EI64_V_M8_M1_MASK, + 12417 => Opcode::PseudoVSUXSEG4EI64_V_M8_M2, + 12418 => Opcode::PseudoVSUXSEG4EI64_V_M8_M2_MASK, + 12419 => Opcode::PseudoVSUXSEG4EI8_V_M1_M1, + 12420 => Opcode::PseudoVSUXSEG4EI8_V_M1_M1_MASK, + 12421 => Opcode::PseudoVSUXSEG4EI8_V_M1_M2, + 12422 => Opcode::PseudoVSUXSEG4EI8_V_M1_M2_MASK, + 12423 => Opcode::PseudoVSUXSEG4EI8_V_M2_M2, + 12424 => Opcode::PseudoVSUXSEG4EI8_V_M2_M2_MASK, + 12425 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M1, + 12426 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M1_MASK, + 12427 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M2, + 12428 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M2_MASK, + 12429 => Opcode::PseudoVSUXSEG4EI8_V_MF2_MF2, + 12430 => Opcode::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, + 12431 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M1, + 12432 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M1_MASK, + 12433 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M2, + 12434 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M2_MASK, + 12435 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF2, + 12436 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, + 12437 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF4, + 12438 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, + 12439 => Opcode::PseudoVSUXSEG4EI8_V_MF8_M1, + 12440 => Opcode::PseudoVSUXSEG4EI8_V_MF8_M1_MASK, + 12441 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF2, + 12442 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, + 12443 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF4, + 12444 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, + 12445 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF8, + 12446 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, + 12447 => Opcode::PseudoVSUXSEG5EI16_V_M1_M1, + 12448 => Opcode::PseudoVSUXSEG5EI16_V_M1_M1_MASK, + 12449 => Opcode::PseudoVSUXSEG5EI16_V_M1_MF2, + 12450 => Opcode::PseudoVSUXSEG5EI16_V_M1_MF2_MASK, + 12451 => Opcode::PseudoVSUXSEG5EI16_V_M2_M1, + 12452 => Opcode::PseudoVSUXSEG5EI16_V_M2_M1_MASK, + 12453 => Opcode::PseudoVSUXSEG5EI16_V_MF2_M1, + 12454 => Opcode::PseudoVSUXSEG5EI16_V_MF2_M1_MASK, + 12455 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF2, + 12456 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, + 12457 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF4, + 12458 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, + 12459 => Opcode::PseudoVSUXSEG5EI16_V_MF4_M1, + 12460 => Opcode::PseudoVSUXSEG5EI16_V_MF4_M1_MASK, + 12461 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF2, + 12462 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, + 12463 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF4, + 12464 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, + 12465 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF8, + 12466 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, + 12467 => Opcode::PseudoVSUXSEG5EI32_V_M1_M1, + 12468 => Opcode::PseudoVSUXSEG5EI32_V_M1_M1_MASK, + 12469 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF2, + 12470 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF2_MASK, + 12471 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF4, + 12472 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF4_MASK, + 12473 => Opcode::PseudoVSUXSEG5EI32_V_M2_M1, + 12474 => Opcode::PseudoVSUXSEG5EI32_V_M2_M1_MASK, + 12475 => Opcode::PseudoVSUXSEG5EI32_V_M2_MF2, + 12476 => Opcode::PseudoVSUXSEG5EI32_V_M2_MF2_MASK, + 12477 => Opcode::PseudoVSUXSEG5EI32_V_M4_M1, + 12478 => Opcode::PseudoVSUXSEG5EI32_V_M4_M1_MASK, + 12479 => Opcode::PseudoVSUXSEG5EI32_V_MF2_M1, + 12480 => Opcode::PseudoVSUXSEG5EI32_V_MF2_M1_MASK, + 12481 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF2, + 12482 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, + 12483 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF4, + 12484 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, + 12485 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF8, + 12486 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, + 12487 => Opcode::PseudoVSUXSEG5EI64_V_M1_M1, + 12488 => Opcode::PseudoVSUXSEG5EI64_V_M1_M1_MASK, + 12489 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF2, + 12490 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF2_MASK, + 12491 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF4, + 12492 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF4_MASK, + 12493 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF8, + 12494 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF8_MASK, + 12495 => Opcode::PseudoVSUXSEG5EI64_V_M2_M1, + 12496 => Opcode::PseudoVSUXSEG5EI64_V_M2_M1_MASK, + 12497 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF2, + 12498 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF2_MASK, + 12499 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF4, + 12500 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF4_MASK, + 12501 => Opcode::PseudoVSUXSEG5EI64_V_M4_M1, + 12502 => Opcode::PseudoVSUXSEG5EI64_V_M4_M1_MASK, + 12503 => Opcode::PseudoVSUXSEG5EI64_V_M4_MF2, + 12504 => Opcode::PseudoVSUXSEG5EI64_V_M4_MF2_MASK, + 12505 => Opcode::PseudoVSUXSEG5EI64_V_M8_M1, + 12506 => Opcode::PseudoVSUXSEG5EI64_V_M8_M1_MASK, + 12507 => Opcode::PseudoVSUXSEG5EI8_V_M1_M1, + 12508 => Opcode::PseudoVSUXSEG5EI8_V_M1_M1_MASK, + 12509 => Opcode::PseudoVSUXSEG5EI8_V_MF2_M1, + 12510 => Opcode::PseudoVSUXSEG5EI8_V_MF2_M1_MASK, + 12511 => Opcode::PseudoVSUXSEG5EI8_V_MF2_MF2, + 12512 => Opcode::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, + 12513 => Opcode::PseudoVSUXSEG5EI8_V_MF4_M1, + 12514 => Opcode::PseudoVSUXSEG5EI8_V_MF4_M1_MASK, + 12515 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF2, + 12516 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, + 12517 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF4, + 12518 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, + 12519 => Opcode::PseudoVSUXSEG5EI8_V_MF8_M1, + 12520 => Opcode::PseudoVSUXSEG5EI8_V_MF8_M1_MASK, + 12521 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF2, + 12522 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, + 12523 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF4, + 12524 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, + 12525 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF8, + 12526 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, + 12527 => Opcode::PseudoVSUXSEG6EI16_V_M1_M1, + 12528 => Opcode::PseudoVSUXSEG6EI16_V_M1_M1_MASK, + 12529 => Opcode::PseudoVSUXSEG6EI16_V_M1_MF2, + 12530 => Opcode::PseudoVSUXSEG6EI16_V_M1_MF2_MASK, + 12531 => Opcode::PseudoVSUXSEG6EI16_V_M2_M1, + 12532 => Opcode::PseudoVSUXSEG6EI16_V_M2_M1_MASK, + 12533 => Opcode::PseudoVSUXSEG6EI16_V_MF2_M1, + 12534 => Opcode::PseudoVSUXSEG6EI16_V_MF2_M1_MASK, + 12535 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF2, + 12536 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, + 12537 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF4, + 12538 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, + 12539 => Opcode::PseudoVSUXSEG6EI16_V_MF4_M1, + 12540 => Opcode::PseudoVSUXSEG6EI16_V_MF4_M1_MASK, + 12541 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF2, + 12542 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, + 12543 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF4, + 12544 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, + 12545 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF8, + 12546 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, + 12547 => Opcode::PseudoVSUXSEG6EI32_V_M1_M1, + 12548 => Opcode::PseudoVSUXSEG6EI32_V_M1_M1_MASK, + 12549 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF2, + 12550 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF2_MASK, + 12551 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF4, + 12552 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF4_MASK, + 12553 => Opcode::PseudoVSUXSEG6EI32_V_M2_M1, + 12554 => Opcode::PseudoVSUXSEG6EI32_V_M2_M1_MASK, + 12555 => Opcode::PseudoVSUXSEG6EI32_V_M2_MF2, + 12556 => Opcode::PseudoVSUXSEG6EI32_V_M2_MF2_MASK, + 12557 => Opcode::PseudoVSUXSEG6EI32_V_M4_M1, + 12558 => Opcode::PseudoVSUXSEG6EI32_V_M4_M1_MASK, + 12559 => Opcode::PseudoVSUXSEG6EI32_V_MF2_M1, + 12560 => Opcode::PseudoVSUXSEG6EI32_V_MF2_M1_MASK, + 12561 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF2, + 12562 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, + 12563 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF4, + 12564 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, + 12565 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF8, + 12566 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, + 12567 => Opcode::PseudoVSUXSEG6EI64_V_M1_M1, + 12568 => Opcode::PseudoVSUXSEG6EI64_V_M1_M1_MASK, + 12569 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF2, + 12570 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF2_MASK, + 12571 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF4, + 12572 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF4_MASK, + 12573 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF8, + 12574 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF8_MASK, + 12575 => Opcode::PseudoVSUXSEG6EI64_V_M2_M1, + 12576 => Opcode::PseudoVSUXSEG6EI64_V_M2_M1_MASK, + 12577 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF2, + 12578 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF2_MASK, + 12579 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF4, + 12580 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF4_MASK, + 12581 => Opcode::PseudoVSUXSEG6EI64_V_M4_M1, + 12582 => Opcode::PseudoVSUXSEG6EI64_V_M4_M1_MASK, + 12583 => Opcode::PseudoVSUXSEG6EI64_V_M4_MF2, + 12584 => Opcode::PseudoVSUXSEG6EI64_V_M4_MF2_MASK, + 12585 => Opcode::PseudoVSUXSEG6EI64_V_M8_M1, + 12586 => Opcode::PseudoVSUXSEG6EI64_V_M8_M1_MASK, + 12587 => Opcode::PseudoVSUXSEG6EI8_V_M1_M1, + 12588 => Opcode::PseudoVSUXSEG6EI8_V_M1_M1_MASK, + 12589 => Opcode::PseudoVSUXSEG6EI8_V_MF2_M1, + 12590 => Opcode::PseudoVSUXSEG6EI8_V_MF2_M1_MASK, + 12591 => Opcode::PseudoVSUXSEG6EI8_V_MF2_MF2, + 12592 => Opcode::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, + 12593 => Opcode::PseudoVSUXSEG6EI8_V_MF4_M1, + 12594 => Opcode::PseudoVSUXSEG6EI8_V_MF4_M1_MASK, + 12595 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF2, + 12596 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, + 12597 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF4, + 12598 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, + 12599 => Opcode::PseudoVSUXSEG6EI8_V_MF8_M1, + 12600 => Opcode::PseudoVSUXSEG6EI8_V_MF8_M1_MASK, + 12601 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF2, + 12602 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, + 12603 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF4, + 12604 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, + 12605 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF8, + 12606 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, + 12607 => Opcode::PseudoVSUXSEG7EI16_V_M1_M1, + 12608 => Opcode::PseudoVSUXSEG7EI16_V_M1_M1_MASK, + 12609 => Opcode::PseudoVSUXSEG7EI16_V_M1_MF2, + 12610 => Opcode::PseudoVSUXSEG7EI16_V_M1_MF2_MASK, + 12611 => Opcode::PseudoVSUXSEG7EI16_V_M2_M1, + 12612 => Opcode::PseudoVSUXSEG7EI16_V_M2_M1_MASK, + 12613 => Opcode::PseudoVSUXSEG7EI16_V_MF2_M1, + 12614 => Opcode::PseudoVSUXSEG7EI16_V_MF2_M1_MASK, + 12615 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF2, + 12616 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, + 12617 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF4, + 12618 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, + 12619 => Opcode::PseudoVSUXSEG7EI16_V_MF4_M1, + 12620 => Opcode::PseudoVSUXSEG7EI16_V_MF4_M1_MASK, + 12621 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF2, + 12622 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, + 12623 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF4, + 12624 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, + 12625 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF8, + 12626 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, + 12627 => Opcode::PseudoVSUXSEG7EI32_V_M1_M1, + 12628 => Opcode::PseudoVSUXSEG7EI32_V_M1_M1_MASK, + 12629 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF2, + 12630 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF2_MASK, + 12631 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF4, + 12632 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF4_MASK, + 12633 => Opcode::PseudoVSUXSEG7EI32_V_M2_M1, + 12634 => Opcode::PseudoVSUXSEG7EI32_V_M2_M1_MASK, + 12635 => Opcode::PseudoVSUXSEG7EI32_V_M2_MF2, + 12636 => Opcode::PseudoVSUXSEG7EI32_V_M2_MF2_MASK, + 12637 => Opcode::PseudoVSUXSEG7EI32_V_M4_M1, + 12638 => Opcode::PseudoVSUXSEG7EI32_V_M4_M1_MASK, + 12639 => Opcode::PseudoVSUXSEG7EI32_V_MF2_M1, + 12640 => Opcode::PseudoVSUXSEG7EI32_V_MF2_M1_MASK, + 12641 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF2, + 12642 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, + 12643 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF4, + 12644 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, + 12645 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF8, + 12646 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, + 12647 => Opcode::PseudoVSUXSEG7EI64_V_M1_M1, + 12648 => Opcode::PseudoVSUXSEG7EI64_V_M1_M1_MASK, + 12649 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF2, + 12650 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF2_MASK, + 12651 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF4, + 12652 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF4_MASK, + 12653 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF8, + 12654 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF8_MASK, + 12655 => Opcode::PseudoVSUXSEG7EI64_V_M2_M1, + 12656 => Opcode::PseudoVSUXSEG7EI64_V_M2_M1_MASK, + 12657 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF2, + 12658 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF2_MASK, + 12659 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF4, + 12660 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF4_MASK, + 12661 => Opcode::PseudoVSUXSEG7EI64_V_M4_M1, + 12662 => Opcode::PseudoVSUXSEG7EI64_V_M4_M1_MASK, + 12663 => Opcode::PseudoVSUXSEG7EI64_V_M4_MF2, + 12664 => Opcode::PseudoVSUXSEG7EI64_V_M4_MF2_MASK, + 12665 => Opcode::PseudoVSUXSEG7EI64_V_M8_M1, + 12666 => Opcode::PseudoVSUXSEG7EI64_V_M8_M1_MASK, + 12667 => Opcode::PseudoVSUXSEG7EI8_V_M1_M1, + 12668 => Opcode::PseudoVSUXSEG7EI8_V_M1_M1_MASK, + 12669 => Opcode::PseudoVSUXSEG7EI8_V_MF2_M1, + 12670 => Opcode::PseudoVSUXSEG7EI8_V_MF2_M1_MASK, + 12671 => Opcode::PseudoVSUXSEG7EI8_V_MF2_MF2, + 12672 => Opcode::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, + 12673 => Opcode::PseudoVSUXSEG7EI8_V_MF4_M1, + 12674 => Opcode::PseudoVSUXSEG7EI8_V_MF4_M1_MASK, + 12675 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF2, + 12676 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, + 12677 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF4, + 12678 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, + 12679 => Opcode::PseudoVSUXSEG7EI8_V_MF8_M1, + 12680 => Opcode::PseudoVSUXSEG7EI8_V_MF8_M1_MASK, + 12681 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF2, + 12682 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, + 12683 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF4, + 12684 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, + 12685 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF8, + 12686 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, + 12687 => Opcode::PseudoVSUXSEG8EI16_V_M1_M1, + 12688 => Opcode::PseudoVSUXSEG8EI16_V_M1_M1_MASK, + 12689 => Opcode::PseudoVSUXSEG8EI16_V_M1_MF2, + 12690 => Opcode::PseudoVSUXSEG8EI16_V_M1_MF2_MASK, + 12691 => Opcode::PseudoVSUXSEG8EI16_V_M2_M1, + 12692 => Opcode::PseudoVSUXSEG8EI16_V_M2_M1_MASK, + 12693 => Opcode::PseudoVSUXSEG8EI16_V_MF2_M1, + 12694 => Opcode::PseudoVSUXSEG8EI16_V_MF2_M1_MASK, + 12695 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF2, + 12696 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, + 12697 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF4, + 12698 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, + 12699 => Opcode::PseudoVSUXSEG8EI16_V_MF4_M1, + 12700 => Opcode::PseudoVSUXSEG8EI16_V_MF4_M1_MASK, + 12701 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF2, + 12702 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, + 12703 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF4, + 12704 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, + 12705 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF8, + 12706 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, + 12707 => Opcode::PseudoVSUXSEG8EI32_V_M1_M1, + 12708 => Opcode::PseudoVSUXSEG8EI32_V_M1_M1_MASK, + 12709 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF2, + 12710 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF2_MASK, + 12711 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF4, + 12712 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF4_MASK, + 12713 => Opcode::PseudoVSUXSEG8EI32_V_M2_M1, + 12714 => Opcode::PseudoVSUXSEG8EI32_V_M2_M1_MASK, + 12715 => Opcode::PseudoVSUXSEG8EI32_V_M2_MF2, + 12716 => Opcode::PseudoVSUXSEG8EI32_V_M2_MF2_MASK, + 12717 => Opcode::PseudoVSUXSEG8EI32_V_M4_M1, + 12718 => Opcode::PseudoVSUXSEG8EI32_V_M4_M1_MASK, + 12719 => Opcode::PseudoVSUXSEG8EI32_V_MF2_M1, + 12720 => Opcode::PseudoVSUXSEG8EI32_V_MF2_M1_MASK, + 12721 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF2, + 12722 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, + 12723 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF4, + 12724 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, + 12725 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF8, + 12726 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, + 12727 => Opcode::PseudoVSUXSEG8EI64_V_M1_M1, + 12728 => Opcode::PseudoVSUXSEG8EI64_V_M1_M1_MASK, + 12729 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF2, + 12730 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF2_MASK, + 12731 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF4, + 12732 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF4_MASK, + 12733 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF8, + 12734 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF8_MASK, + 12735 => Opcode::PseudoVSUXSEG8EI64_V_M2_M1, + 12736 => Opcode::PseudoVSUXSEG8EI64_V_M2_M1_MASK, + 12737 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF2, + 12738 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF2_MASK, + 12739 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF4, + 12740 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF4_MASK, + 12741 => Opcode::PseudoVSUXSEG8EI64_V_M4_M1, + 12742 => Opcode::PseudoVSUXSEG8EI64_V_M4_M1_MASK, + 12743 => Opcode::PseudoVSUXSEG8EI64_V_M4_MF2, + 12744 => Opcode::PseudoVSUXSEG8EI64_V_M4_MF2_MASK, + 12745 => Opcode::PseudoVSUXSEG8EI64_V_M8_M1, + 12746 => Opcode::PseudoVSUXSEG8EI64_V_M8_M1_MASK, + 12747 => Opcode::PseudoVSUXSEG8EI8_V_M1_M1, + 12748 => Opcode::PseudoVSUXSEG8EI8_V_M1_M1_MASK, + 12749 => Opcode::PseudoVSUXSEG8EI8_V_MF2_M1, + 12750 => Opcode::PseudoVSUXSEG8EI8_V_MF2_M1_MASK, + 12751 => Opcode::PseudoVSUXSEG8EI8_V_MF2_MF2, + 12752 => Opcode::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, + 12753 => Opcode::PseudoVSUXSEG8EI8_V_MF4_M1, + 12754 => Opcode::PseudoVSUXSEG8EI8_V_MF4_M1_MASK, + 12755 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF2, + 12756 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, + 12757 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF4, + 12758 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, + 12759 => Opcode::PseudoVSUXSEG8EI8_V_MF8_M1, + 12760 => Opcode::PseudoVSUXSEG8EI8_V_MF8_M1_MASK, + 12761 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF2, + 12762 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, + 12763 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF4, + 12764 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, + 12765 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF8, + 12766 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, + 12767 => Opcode::PseudoVWADDU_VV_M1, + 12768 => Opcode::PseudoVWADDU_VV_M1_MASK, + 12769 => Opcode::PseudoVWADDU_VV_M2, + 12770 => Opcode::PseudoVWADDU_VV_M2_MASK, + 12771 => Opcode::PseudoVWADDU_VV_M4, + 12772 => Opcode::PseudoVWADDU_VV_M4_MASK, + 12773 => Opcode::PseudoVWADDU_VV_MF2, + 12774 => Opcode::PseudoVWADDU_VV_MF2_MASK, + 12775 => Opcode::PseudoVWADDU_VV_MF4, + 12776 => Opcode::PseudoVWADDU_VV_MF4_MASK, + 12777 => Opcode::PseudoVWADDU_VV_MF8, + 12778 => Opcode::PseudoVWADDU_VV_MF8_MASK, + 12779 => Opcode::PseudoVWADDU_VX_M1, + 12780 => Opcode::PseudoVWADDU_VX_M1_MASK, + 12781 => Opcode::PseudoVWADDU_VX_M2, + 12782 => Opcode::PseudoVWADDU_VX_M2_MASK, + 12783 => Opcode::PseudoVWADDU_VX_M4, + 12784 => Opcode::PseudoVWADDU_VX_M4_MASK, + 12785 => Opcode::PseudoVWADDU_VX_MF2, + 12786 => Opcode::PseudoVWADDU_VX_MF2_MASK, + 12787 => Opcode::PseudoVWADDU_VX_MF4, + 12788 => Opcode::PseudoVWADDU_VX_MF4_MASK, + 12789 => Opcode::PseudoVWADDU_VX_MF8, + 12790 => Opcode::PseudoVWADDU_VX_MF8_MASK, + 12791 => Opcode::PseudoVWADDU_WV_M1, + 12792 => Opcode::PseudoVWADDU_WV_M1_MASK, + 12793 => Opcode::PseudoVWADDU_WV_M1_MASK_TIED, + 12794 => Opcode::PseudoVWADDU_WV_M1_TIED, + 12795 => Opcode::PseudoVWADDU_WV_M2, + 12796 => Opcode::PseudoVWADDU_WV_M2_MASK, + 12797 => Opcode::PseudoVWADDU_WV_M2_MASK_TIED, + 12798 => Opcode::PseudoVWADDU_WV_M2_TIED, + 12799 => Opcode::PseudoVWADDU_WV_M4, + 12800 => Opcode::PseudoVWADDU_WV_M4_MASK, + 12801 => Opcode::PseudoVWADDU_WV_M4_MASK_TIED, + 12802 => Opcode::PseudoVWADDU_WV_M4_TIED, + 12803 => Opcode::PseudoVWADDU_WV_MF2, + 12804 => Opcode::PseudoVWADDU_WV_MF2_MASK, + 12805 => Opcode::PseudoVWADDU_WV_MF2_MASK_TIED, + 12806 => Opcode::PseudoVWADDU_WV_MF2_TIED, + 12807 => Opcode::PseudoVWADDU_WV_MF4, + 12808 => Opcode::PseudoVWADDU_WV_MF4_MASK, + 12809 => Opcode::PseudoVWADDU_WV_MF4_MASK_TIED, + 12810 => Opcode::PseudoVWADDU_WV_MF4_TIED, + 12811 => Opcode::PseudoVWADDU_WV_MF8, + 12812 => Opcode::PseudoVWADDU_WV_MF8_MASK, + 12813 => Opcode::PseudoVWADDU_WV_MF8_MASK_TIED, + 12814 => Opcode::PseudoVWADDU_WV_MF8_TIED, + 12815 => Opcode::PseudoVWADDU_WX_M1, + 12816 => Opcode::PseudoVWADDU_WX_M1_MASK, + 12817 => Opcode::PseudoVWADDU_WX_M2, + 12818 => Opcode::PseudoVWADDU_WX_M2_MASK, + 12819 => Opcode::PseudoVWADDU_WX_M4, + 12820 => Opcode::PseudoVWADDU_WX_M4_MASK, + 12821 => Opcode::PseudoVWADDU_WX_MF2, + 12822 => Opcode::PseudoVWADDU_WX_MF2_MASK, + 12823 => Opcode::PseudoVWADDU_WX_MF4, + 12824 => Opcode::PseudoVWADDU_WX_MF4_MASK, + 12825 => Opcode::PseudoVWADDU_WX_MF8, + 12826 => Opcode::PseudoVWADDU_WX_MF8_MASK, + 12827 => Opcode::PseudoVWADD_VV_M1, + 12828 => Opcode::PseudoVWADD_VV_M1_MASK, + 12829 => Opcode::PseudoVWADD_VV_M2, + 12830 => Opcode::PseudoVWADD_VV_M2_MASK, + 12831 => Opcode::PseudoVWADD_VV_M4, + 12832 => Opcode::PseudoVWADD_VV_M4_MASK, + 12833 => Opcode::PseudoVWADD_VV_MF2, + 12834 => Opcode::PseudoVWADD_VV_MF2_MASK, + 12835 => Opcode::PseudoVWADD_VV_MF4, + 12836 => Opcode::PseudoVWADD_VV_MF4_MASK, + 12837 => Opcode::PseudoVWADD_VV_MF8, + 12838 => Opcode::PseudoVWADD_VV_MF8_MASK, + 12839 => Opcode::PseudoVWADD_VX_M1, + 12840 => Opcode::PseudoVWADD_VX_M1_MASK, + 12841 => Opcode::PseudoVWADD_VX_M2, + 12842 => Opcode::PseudoVWADD_VX_M2_MASK, + 12843 => Opcode::PseudoVWADD_VX_M4, + 12844 => Opcode::PseudoVWADD_VX_M4_MASK, + 12845 => Opcode::PseudoVWADD_VX_MF2, + 12846 => Opcode::PseudoVWADD_VX_MF2_MASK, + 12847 => Opcode::PseudoVWADD_VX_MF4, + 12848 => Opcode::PseudoVWADD_VX_MF4_MASK, + 12849 => Opcode::PseudoVWADD_VX_MF8, + 12850 => Opcode::PseudoVWADD_VX_MF8_MASK, + 12851 => Opcode::PseudoVWADD_WV_M1, + 12852 => Opcode::PseudoVWADD_WV_M1_MASK, + 12853 => Opcode::PseudoVWADD_WV_M1_MASK_TIED, + 12854 => Opcode::PseudoVWADD_WV_M1_TIED, + 12855 => Opcode::PseudoVWADD_WV_M2, + 12856 => Opcode::PseudoVWADD_WV_M2_MASK, + 12857 => Opcode::PseudoVWADD_WV_M2_MASK_TIED, + 12858 => Opcode::PseudoVWADD_WV_M2_TIED, + 12859 => Opcode::PseudoVWADD_WV_M4, + 12860 => Opcode::PseudoVWADD_WV_M4_MASK, + 12861 => Opcode::PseudoVWADD_WV_M4_MASK_TIED, + 12862 => Opcode::PseudoVWADD_WV_M4_TIED, + 12863 => Opcode::PseudoVWADD_WV_MF2, + 12864 => Opcode::PseudoVWADD_WV_MF2_MASK, + 12865 => Opcode::PseudoVWADD_WV_MF2_MASK_TIED, + 12866 => Opcode::PseudoVWADD_WV_MF2_TIED, + 12867 => Opcode::PseudoVWADD_WV_MF4, + 12868 => Opcode::PseudoVWADD_WV_MF4_MASK, + 12869 => Opcode::PseudoVWADD_WV_MF4_MASK_TIED, + 12870 => Opcode::PseudoVWADD_WV_MF4_TIED, + 12871 => Opcode::PseudoVWADD_WV_MF8, + 12872 => Opcode::PseudoVWADD_WV_MF8_MASK, + 12873 => Opcode::PseudoVWADD_WV_MF8_MASK_TIED, + 12874 => Opcode::PseudoVWADD_WV_MF8_TIED, + 12875 => Opcode::PseudoVWADD_WX_M1, + 12876 => Opcode::PseudoVWADD_WX_M1_MASK, + 12877 => Opcode::PseudoVWADD_WX_M2, + 12878 => Opcode::PseudoVWADD_WX_M2_MASK, + 12879 => Opcode::PseudoVWADD_WX_M4, + 12880 => Opcode::PseudoVWADD_WX_M4_MASK, + 12881 => Opcode::PseudoVWADD_WX_MF2, + 12882 => Opcode::PseudoVWADD_WX_MF2_MASK, + 12883 => Opcode::PseudoVWADD_WX_MF4, + 12884 => Opcode::PseudoVWADD_WX_MF4_MASK, + 12885 => Opcode::PseudoVWADD_WX_MF8, + 12886 => Opcode::PseudoVWADD_WX_MF8_MASK, + 12887 => Opcode::PseudoVWMACCSU_VV_M1, + 12888 => Opcode::PseudoVWMACCSU_VV_M1_MASK, + 12889 => Opcode::PseudoVWMACCSU_VV_M2, + 12890 => Opcode::PseudoVWMACCSU_VV_M2_MASK, + 12891 => Opcode::PseudoVWMACCSU_VV_M4, + 12892 => Opcode::PseudoVWMACCSU_VV_M4_MASK, + 12893 => Opcode::PseudoVWMACCSU_VV_MF2, + 12894 => Opcode::PseudoVWMACCSU_VV_MF2_MASK, + 12895 => Opcode::PseudoVWMACCSU_VV_MF4, + 12896 => Opcode::PseudoVWMACCSU_VV_MF4_MASK, + 12897 => Opcode::PseudoVWMACCSU_VV_MF8, + 12898 => Opcode::PseudoVWMACCSU_VV_MF8_MASK, + 12899 => Opcode::PseudoVWMACCSU_VX_M1, + 12900 => Opcode::PseudoVWMACCSU_VX_M1_MASK, + 12901 => Opcode::PseudoVWMACCSU_VX_M2, + 12902 => Opcode::PseudoVWMACCSU_VX_M2_MASK, + 12903 => Opcode::PseudoVWMACCSU_VX_M4, + 12904 => Opcode::PseudoVWMACCSU_VX_M4_MASK, + 12905 => Opcode::PseudoVWMACCSU_VX_MF2, + 12906 => Opcode::PseudoVWMACCSU_VX_MF2_MASK, + 12907 => Opcode::PseudoVWMACCSU_VX_MF4, + 12908 => Opcode::PseudoVWMACCSU_VX_MF4_MASK, + 12909 => Opcode::PseudoVWMACCSU_VX_MF8, + 12910 => Opcode::PseudoVWMACCSU_VX_MF8_MASK, + 12911 => Opcode::PseudoVWMACCUS_VX_M1, + 12912 => Opcode::PseudoVWMACCUS_VX_M1_MASK, + 12913 => Opcode::PseudoVWMACCUS_VX_M2, + 12914 => Opcode::PseudoVWMACCUS_VX_M2_MASK, + 12915 => Opcode::PseudoVWMACCUS_VX_M4, + 12916 => Opcode::PseudoVWMACCUS_VX_M4_MASK, + 12917 => Opcode::PseudoVWMACCUS_VX_MF2, + 12918 => Opcode::PseudoVWMACCUS_VX_MF2_MASK, + 12919 => Opcode::PseudoVWMACCUS_VX_MF4, + 12920 => Opcode::PseudoVWMACCUS_VX_MF4_MASK, + 12921 => Opcode::PseudoVWMACCUS_VX_MF8, + 12922 => Opcode::PseudoVWMACCUS_VX_MF8_MASK, + 12923 => Opcode::PseudoVWMACCU_VV_M1, + 12924 => Opcode::PseudoVWMACCU_VV_M1_MASK, + 12925 => Opcode::PseudoVWMACCU_VV_M2, + 12926 => Opcode::PseudoVWMACCU_VV_M2_MASK, + 12927 => Opcode::PseudoVWMACCU_VV_M4, + 12928 => Opcode::PseudoVWMACCU_VV_M4_MASK, + 12929 => Opcode::PseudoVWMACCU_VV_MF2, + 12930 => Opcode::PseudoVWMACCU_VV_MF2_MASK, + 12931 => Opcode::PseudoVWMACCU_VV_MF4, + 12932 => Opcode::PseudoVWMACCU_VV_MF4_MASK, + 12933 => Opcode::PseudoVWMACCU_VV_MF8, + 12934 => Opcode::PseudoVWMACCU_VV_MF8_MASK, + 12935 => Opcode::PseudoVWMACCU_VX_M1, + 12936 => Opcode::PseudoVWMACCU_VX_M1_MASK, + 12937 => Opcode::PseudoVWMACCU_VX_M2, + 12938 => Opcode::PseudoVWMACCU_VX_M2_MASK, + 12939 => Opcode::PseudoVWMACCU_VX_M4, + 12940 => Opcode::PseudoVWMACCU_VX_M4_MASK, + 12941 => Opcode::PseudoVWMACCU_VX_MF2, + 12942 => Opcode::PseudoVWMACCU_VX_MF2_MASK, + 12943 => Opcode::PseudoVWMACCU_VX_MF4, + 12944 => Opcode::PseudoVWMACCU_VX_MF4_MASK, + 12945 => Opcode::PseudoVWMACCU_VX_MF8, + 12946 => Opcode::PseudoVWMACCU_VX_MF8_MASK, + 12947 => Opcode::PseudoVWMACC_VV_M1, + 12948 => Opcode::PseudoVWMACC_VV_M1_MASK, + 12949 => Opcode::PseudoVWMACC_VV_M2, + 12950 => Opcode::PseudoVWMACC_VV_M2_MASK, + 12951 => Opcode::PseudoVWMACC_VV_M4, + 12952 => Opcode::PseudoVWMACC_VV_M4_MASK, + 12953 => Opcode::PseudoVWMACC_VV_MF2, + 12954 => Opcode::PseudoVWMACC_VV_MF2_MASK, + 12955 => Opcode::PseudoVWMACC_VV_MF4, + 12956 => Opcode::PseudoVWMACC_VV_MF4_MASK, + 12957 => Opcode::PseudoVWMACC_VV_MF8, + 12958 => Opcode::PseudoVWMACC_VV_MF8_MASK, + 12959 => Opcode::PseudoVWMACC_VX_M1, + 12960 => Opcode::PseudoVWMACC_VX_M1_MASK, + 12961 => Opcode::PseudoVWMACC_VX_M2, + 12962 => Opcode::PseudoVWMACC_VX_M2_MASK, + 12963 => Opcode::PseudoVWMACC_VX_M4, + 12964 => Opcode::PseudoVWMACC_VX_M4_MASK, + 12965 => Opcode::PseudoVWMACC_VX_MF2, + 12966 => Opcode::PseudoVWMACC_VX_MF2_MASK, + 12967 => Opcode::PseudoVWMACC_VX_MF4, + 12968 => Opcode::PseudoVWMACC_VX_MF4_MASK, + 12969 => Opcode::PseudoVWMACC_VX_MF8, + 12970 => Opcode::PseudoVWMACC_VX_MF8_MASK, + 12971 => Opcode::PseudoVWMULSU_VV_M1, + 12972 => Opcode::PseudoVWMULSU_VV_M1_MASK, + 12973 => Opcode::PseudoVWMULSU_VV_M2, + 12974 => Opcode::PseudoVWMULSU_VV_M2_MASK, + 12975 => Opcode::PseudoVWMULSU_VV_M4, + 12976 => Opcode::PseudoVWMULSU_VV_M4_MASK, + 12977 => Opcode::PseudoVWMULSU_VV_MF2, + 12978 => Opcode::PseudoVWMULSU_VV_MF2_MASK, + 12979 => Opcode::PseudoVWMULSU_VV_MF4, + 12980 => Opcode::PseudoVWMULSU_VV_MF4_MASK, + 12981 => Opcode::PseudoVWMULSU_VV_MF8, + 12982 => Opcode::PseudoVWMULSU_VV_MF8_MASK, + 12983 => Opcode::PseudoVWMULSU_VX_M1, + 12984 => Opcode::PseudoVWMULSU_VX_M1_MASK, + 12985 => Opcode::PseudoVWMULSU_VX_M2, + 12986 => Opcode::PseudoVWMULSU_VX_M2_MASK, + 12987 => Opcode::PseudoVWMULSU_VX_M4, + 12988 => Opcode::PseudoVWMULSU_VX_M4_MASK, + 12989 => Opcode::PseudoVWMULSU_VX_MF2, + 12990 => Opcode::PseudoVWMULSU_VX_MF2_MASK, + 12991 => Opcode::PseudoVWMULSU_VX_MF4, + 12992 => Opcode::PseudoVWMULSU_VX_MF4_MASK, + 12993 => Opcode::PseudoVWMULSU_VX_MF8, + 12994 => Opcode::PseudoVWMULSU_VX_MF8_MASK, + 12995 => Opcode::PseudoVWMULU_VV_M1, + 12996 => Opcode::PseudoVWMULU_VV_M1_MASK, + 12997 => Opcode::PseudoVWMULU_VV_M2, + 12998 => Opcode::PseudoVWMULU_VV_M2_MASK, + 12999 => Opcode::PseudoVWMULU_VV_M4, + 13000 => Opcode::PseudoVWMULU_VV_M4_MASK, + 13001 => Opcode::PseudoVWMULU_VV_MF2, + 13002 => Opcode::PseudoVWMULU_VV_MF2_MASK, + 13003 => Opcode::PseudoVWMULU_VV_MF4, + 13004 => Opcode::PseudoVWMULU_VV_MF4_MASK, + 13005 => Opcode::PseudoVWMULU_VV_MF8, + 13006 => Opcode::PseudoVWMULU_VV_MF8_MASK, + 13007 => Opcode::PseudoVWMULU_VX_M1, + 13008 => Opcode::PseudoVWMULU_VX_M1_MASK, + 13009 => Opcode::PseudoVWMULU_VX_M2, + 13010 => Opcode::PseudoVWMULU_VX_M2_MASK, + 13011 => Opcode::PseudoVWMULU_VX_M4, + 13012 => Opcode::PseudoVWMULU_VX_M4_MASK, + 13013 => Opcode::PseudoVWMULU_VX_MF2, + 13014 => Opcode::PseudoVWMULU_VX_MF2_MASK, + 13015 => Opcode::PseudoVWMULU_VX_MF4, + 13016 => Opcode::PseudoVWMULU_VX_MF4_MASK, + 13017 => Opcode::PseudoVWMULU_VX_MF8, + 13018 => Opcode::PseudoVWMULU_VX_MF8_MASK, + 13019 => Opcode::PseudoVWMUL_VV_M1, + 13020 => Opcode::PseudoVWMUL_VV_M1_MASK, + 13021 => Opcode::PseudoVWMUL_VV_M2, + 13022 => Opcode::PseudoVWMUL_VV_M2_MASK, + 13023 => Opcode::PseudoVWMUL_VV_M4, + 13024 => Opcode::PseudoVWMUL_VV_M4_MASK, + 13025 => Opcode::PseudoVWMUL_VV_MF2, + 13026 => Opcode::PseudoVWMUL_VV_MF2_MASK, + 13027 => Opcode::PseudoVWMUL_VV_MF4, + 13028 => Opcode::PseudoVWMUL_VV_MF4_MASK, + 13029 => Opcode::PseudoVWMUL_VV_MF8, + 13030 => Opcode::PseudoVWMUL_VV_MF8_MASK, + 13031 => Opcode::PseudoVWMUL_VX_M1, + 13032 => Opcode::PseudoVWMUL_VX_M1_MASK, + 13033 => Opcode::PseudoVWMUL_VX_M2, + 13034 => Opcode::PseudoVWMUL_VX_M2_MASK, + 13035 => Opcode::PseudoVWMUL_VX_M4, + 13036 => Opcode::PseudoVWMUL_VX_M4_MASK, + 13037 => Opcode::PseudoVWMUL_VX_MF2, + 13038 => Opcode::PseudoVWMUL_VX_MF2_MASK, + 13039 => Opcode::PseudoVWMUL_VX_MF4, + 13040 => Opcode::PseudoVWMUL_VX_MF4_MASK, + 13041 => Opcode::PseudoVWMUL_VX_MF8, + 13042 => Opcode::PseudoVWMUL_VX_MF8_MASK, + 13043 => Opcode::PseudoVWREDSUMU_VS_M1_E16, + 13044 => Opcode::PseudoVWREDSUMU_VS_M1_E16_MASK, + 13045 => Opcode::PseudoVWREDSUMU_VS_M1_E32, + 13046 => Opcode::PseudoVWREDSUMU_VS_M1_E32_MASK, + 13047 => Opcode::PseudoVWREDSUMU_VS_M1_E8, + 13048 => Opcode::PseudoVWREDSUMU_VS_M1_E8_MASK, + 13049 => Opcode::PseudoVWREDSUMU_VS_M2_E16, + 13050 => Opcode::PseudoVWREDSUMU_VS_M2_E16_MASK, + 13051 => Opcode::PseudoVWREDSUMU_VS_M2_E32, + 13052 => Opcode::PseudoVWREDSUMU_VS_M2_E32_MASK, + 13053 => Opcode::PseudoVWREDSUMU_VS_M2_E8, + 13054 => Opcode::PseudoVWREDSUMU_VS_M2_E8_MASK, + 13055 => Opcode::PseudoVWREDSUMU_VS_M4_E16, + 13056 => Opcode::PseudoVWREDSUMU_VS_M4_E16_MASK, + 13057 => Opcode::PseudoVWREDSUMU_VS_M4_E32, + 13058 => Opcode::PseudoVWREDSUMU_VS_M4_E32_MASK, + 13059 => Opcode::PseudoVWREDSUMU_VS_M4_E8, + 13060 => Opcode::PseudoVWREDSUMU_VS_M4_E8_MASK, + 13061 => Opcode::PseudoVWREDSUMU_VS_M8_E16, + 13062 => Opcode::PseudoVWREDSUMU_VS_M8_E16_MASK, + 13063 => Opcode::PseudoVWREDSUMU_VS_M8_E32, + 13064 => Opcode::PseudoVWREDSUMU_VS_M8_E32_MASK, + 13065 => Opcode::PseudoVWREDSUMU_VS_M8_E8, + 13066 => Opcode::PseudoVWREDSUMU_VS_M8_E8_MASK, + 13067 => Opcode::PseudoVWREDSUMU_VS_MF2_E16, + 13068 => Opcode::PseudoVWREDSUMU_VS_MF2_E16_MASK, + 13069 => Opcode::PseudoVWREDSUMU_VS_MF2_E32, + 13070 => Opcode::PseudoVWREDSUMU_VS_MF2_E32_MASK, + 13071 => Opcode::PseudoVWREDSUMU_VS_MF2_E8, + 13072 => Opcode::PseudoVWREDSUMU_VS_MF2_E8_MASK, + 13073 => Opcode::PseudoVWREDSUMU_VS_MF4_E16, + 13074 => Opcode::PseudoVWREDSUMU_VS_MF4_E16_MASK, + 13075 => Opcode::PseudoVWREDSUMU_VS_MF4_E8, + 13076 => Opcode::PseudoVWREDSUMU_VS_MF4_E8_MASK, + 13077 => Opcode::PseudoVWREDSUMU_VS_MF8_E8, + 13078 => Opcode::PseudoVWREDSUMU_VS_MF8_E8_MASK, + 13079 => Opcode::PseudoVWREDSUM_VS_M1_E16, + 13080 => Opcode::PseudoVWREDSUM_VS_M1_E16_MASK, + 13081 => Opcode::PseudoVWREDSUM_VS_M1_E32, + 13082 => Opcode::PseudoVWREDSUM_VS_M1_E32_MASK, + 13083 => Opcode::PseudoVWREDSUM_VS_M1_E8, + 13084 => Opcode::PseudoVWREDSUM_VS_M1_E8_MASK, + 13085 => Opcode::PseudoVWREDSUM_VS_M2_E16, + 13086 => Opcode::PseudoVWREDSUM_VS_M2_E16_MASK, + 13087 => Opcode::PseudoVWREDSUM_VS_M2_E32, + 13088 => Opcode::PseudoVWREDSUM_VS_M2_E32_MASK, + 13089 => Opcode::PseudoVWREDSUM_VS_M2_E8, + 13090 => Opcode::PseudoVWREDSUM_VS_M2_E8_MASK, + 13091 => Opcode::PseudoVWREDSUM_VS_M4_E16, + 13092 => Opcode::PseudoVWREDSUM_VS_M4_E16_MASK, + 13093 => Opcode::PseudoVWREDSUM_VS_M4_E32, + 13094 => Opcode::PseudoVWREDSUM_VS_M4_E32_MASK, + 13095 => Opcode::PseudoVWREDSUM_VS_M4_E8, + 13096 => Opcode::PseudoVWREDSUM_VS_M4_E8_MASK, + 13097 => Opcode::PseudoVWREDSUM_VS_M8_E16, + 13098 => Opcode::PseudoVWREDSUM_VS_M8_E16_MASK, + 13099 => Opcode::PseudoVWREDSUM_VS_M8_E32, + 13100 => Opcode::PseudoVWREDSUM_VS_M8_E32_MASK, + 13101 => Opcode::PseudoVWREDSUM_VS_M8_E8, + 13102 => Opcode::PseudoVWREDSUM_VS_M8_E8_MASK, + 13103 => Opcode::PseudoVWREDSUM_VS_MF2_E16, + 13104 => Opcode::PseudoVWREDSUM_VS_MF2_E16_MASK, + 13105 => Opcode::PseudoVWREDSUM_VS_MF2_E32, + 13106 => Opcode::PseudoVWREDSUM_VS_MF2_E32_MASK, + 13107 => Opcode::PseudoVWREDSUM_VS_MF2_E8, + 13108 => Opcode::PseudoVWREDSUM_VS_MF2_E8_MASK, + 13109 => Opcode::PseudoVWREDSUM_VS_MF4_E16, + 13110 => Opcode::PseudoVWREDSUM_VS_MF4_E16_MASK, + 13111 => Opcode::PseudoVWREDSUM_VS_MF4_E8, + 13112 => Opcode::PseudoVWREDSUM_VS_MF4_E8_MASK, + 13113 => Opcode::PseudoVWREDSUM_VS_MF8_E8, + 13114 => Opcode::PseudoVWREDSUM_VS_MF8_E8_MASK, + 13115 => Opcode::PseudoVWSLL_VI_M1, + 13116 => Opcode::PseudoVWSLL_VI_M1_MASK, + 13117 => Opcode::PseudoVWSLL_VI_M2, + 13118 => Opcode::PseudoVWSLL_VI_M2_MASK, + 13119 => Opcode::PseudoVWSLL_VI_M4, + 13120 => Opcode::PseudoVWSLL_VI_M4_MASK, + 13121 => Opcode::PseudoVWSLL_VI_MF2, + 13122 => Opcode::PseudoVWSLL_VI_MF2_MASK, + 13123 => Opcode::PseudoVWSLL_VI_MF4, + 13124 => Opcode::PseudoVWSLL_VI_MF4_MASK, + 13125 => Opcode::PseudoVWSLL_VI_MF8, + 13126 => Opcode::PseudoVWSLL_VI_MF8_MASK, + 13127 => Opcode::PseudoVWSLL_VV_M1, + 13128 => Opcode::PseudoVWSLL_VV_M1_MASK, + 13129 => Opcode::PseudoVWSLL_VV_M2, + 13130 => Opcode::PseudoVWSLL_VV_M2_MASK, + 13131 => Opcode::PseudoVWSLL_VV_M4, + 13132 => Opcode::PseudoVWSLL_VV_M4_MASK, + 13133 => Opcode::PseudoVWSLL_VV_MF2, + 13134 => Opcode::PseudoVWSLL_VV_MF2_MASK, + 13135 => Opcode::PseudoVWSLL_VV_MF4, + 13136 => Opcode::PseudoVWSLL_VV_MF4_MASK, + 13137 => Opcode::PseudoVWSLL_VV_MF8, + 13138 => Opcode::PseudoVWSLL_VV_MF8_MASK, + 13139 => Opcode::PseudoVWSLL_VX_M1, + 13140 => Opcode::PseudoVWSLL_VX_M1_MASK, + 13141 => Opcode::PseudoVWSLL_VX_M2, + 13142 => Opcode::PseudoVWSLL_VX_M2_MASK, + 13143 => Opcode::PseudoVWSLL_VX_M4, + 13144 => Opcode::PseudoVWSLL_VX_M4_MASK, + 13145 => Opcode::PseudoVWSLL_VX_MF2, + 13146 => Opcode::PseudoVWSLL_VX_MF2_MASK, + 13147 => Opcode::PseudoVWSLL_VX_MF4, + 13148 => Opcode::PseudoVWSLL_VX_MF4_MASK, + 13149 => Opcode::PseudoVWSLL_VX_MF8, + 13150 => Opcode::PseudoVWSLL_VX_MF8_MASK, + 13151 => Opcode::PseudoVWSUBU_VV_M1, + 13152 => Opcode::PseudoVWSUBU_VV_M1_MASK, + 13153 => Opcode::PseudoVWSUBU_VV_M2, + 13154 => Opcode::PseudoVWSUBU_VV_M2_MASK, + 13155 => Opcode::PseudoVWSUBU_VV_M4, + 13156 => Opcode::PseudoVWSUBU_VV_M4_MASK, + 13157 => Opcode::PseudoVWSUBU_VV_MF2, + 13158 => Opcode::PseudoVWSUBU_VV_MF2_MASK, + 13159 => Opcode::PseudoVWSUBU_VV_MF4, + 13160 => Opcode::PseudoVWSUBU_VV_MF4_MASK, + 13161 => Opcode::PseudoVWSUBU_VV_MF8, + 13162 => Opcode::PseudoVWSUBU_VV_MF8_MASK, + 13163 => Opcode::PseudoVWSUBU_VX_M1, + 13164 => Opcode::PseudoVWSUBU_VX_M1_MASK, + 13165 => Opcode::PseudoVWSUBU_VX_M2, + 13166 => Opcode::PseudoVWSUBU_VX_M2_MASK, + 13167 => Opcode::PseudoVWSUBU_VX_M4, + 13168 => Opcode::PseudoVWSUBU_VX_M4_MASK, + 13169 => Opcode::PseudoVWSUBU_VX_MF2, + 13170 => Opcode::PseudoVWSUBU_VX_MF2_MASK, + 13171 => Opcode::PseudoVWSUBU_VX_MF4, + 13172 => Opcode::PseudoVWSUBU_VX_MF4_MASK, + 13173 => Opcode::PseudoVWSUBU_VX_MF8, + 13174 => Opcode::PseudoVWSUBU_VX_MF8_MASK, + 13175 => Opcode::PseudoVWSUBU_WV_M1, + 13176 => Opcode::PseudoVWSUBU_WV_M1_MASK, + 13177 => Opcode::PseudoVWSUBU_WV_M1_MASK_TIED, + 13178 => Opcode::PseudoVWSUBU_WV_M1_TIED, + 13179 => Opcode::PseudoVWSUBU_WV_M2, + 13180 => Opcode::PseudoVWSUBU_WV_M2_MASK, + 13181 => Opcode::PseudoVWSUBU_WV_M2_MASK_TIED, + 13182 => Opcode::PseudoVWSUBU_WV_M2_TIED, + 13183 => Opcode::PseudoVWSUBU_WV_M4, + 13184 => Opcode::PseudoVWSUBU_WV_M4_MASK, + 13185 => Opcode::PseudoVWSUBU_WV_M4_MASK_TIED, + 13186 => Opcode::PseudoVWSUBU_WV_M4_TIED, + 13187 => Opcode::PseudoVWSUBU_WV_MF2, + 13188 => Opcode::PseudoVWSUBU_WV_MF2_MASK, + 13189 => Opcode::PseudoVWSUBU_WV_MF2_MASK_TIED, + 13190 => Opcode::PseudoVWSUBU_WV_MF2_TIED, + 13191 => Opcode::PseudoVWSUBU_WV_MF4, + 13192 => Opcode::PseudoVWSUBU_WV_MF4_MASK, + 13193 => Opcode::PseudoVWSUBU_WV_MF4_MASK_TIED, + 13194 => Opcode::PseudoVWSUBU_WV_MF4_TIED, + 13195 => Opcode::PseudoVWSUBU_WV_MF8, + 13196 => Opcode::PseudoVWSUBU_WV_MF8_MASK, + 13197 => Opcode::PseudoVWSUBU_WV_MF8_MASK_TIED, + 13198 => Opcode::PseudoVWSUBU_WV_MF8_TIED, + 13199 => Opcode::PseudoVWSUBU_WX_M1, + 13200 => Opcode::PseudoVWSUBU_WX_M1_MASK, + 13201 => Opcode::PseudoVWSUBU_WX_M2, + 13202 => Opcode::PseudoVWSUBU_WX_M2_MASK, + 13203 => Opcode::PseudoVWSUBU_WX_M4, + 13204 => Opcode::PseudoVWSUBU_WX_M4_MASK, + 13205 => Opcode::PseudoVWSUBU_WX_MF2, + 13206 => Opcode::PseudoVWSUBU_WX_MF2_MASK, + 13207 => Opcode::PseudoVWSUBU_WX_MF4, + 13208 => Opcode::PseudoVWSUBU_WX_MF4_MASK, + 13209 => Opcode::PseudoVWSUBU_WX_MF8, + 13210 => Opcode::PseudoVWSUBU_WX_MF8_MASK, + 13211 => Opcode::PseudoVWSUB_VV_M1, + 13212 => Opcode::PseudoVWSUB_VV_M1_MASK, + 13213 => Opcode::PseudoVWSUB_VV_M2, + 13214 => Opcode::PseudoVWSUB_VV_M2_MASK, + 13215 => Opcode::PseudoVWSUB_VV_M4, + 13216 => Opcode::PseudoVWSUB_VV_M4_MASK, + 13217 => Opcode::PseudoVWSUB_VV_MF2, + 13218 => Opcode::PseudoVWSUB_VV_MF2_MASK, + 13219 => Opcode::PseudoVWSUB_VV_MF4, + 13220 => Opcode::PseudoVWSUB_VV_MF4_MASK, + 13221 => Opcode::PseudoVWSUB_VV_MF8, + 13222 => Opcode::PseudoVWSUB_VV_MF8_MASK, + 13223 => Opcode::PseudoVWSUB_VX_M1, + 13224 => Opcode::PseudoVWSUB_VX_M1_MASK, + 13225 => Opcode::PseudoVWSUB_VX_M2, + 13226 => Opcode::PseudoVWSUB_VX_M2_MASK, + 13227 => Opcode::PseudoVWSUB_VX_M4, + 13228 => Opcode::PseudoVWSUB_VX_M4_MASK, + 13229 => Opcode::PseudoVWSUB_VX_MF2, + 13230 => Opcode::PseudoVWSUB_VX_MF2_MASK, + 13231 => Opcode::PseudoVWSUB_VX_MF4, + 13232 => Opcode::PseudoVWSUB_VX_MF4_MASK, + 13233 => Opcode::PseudoVWSUB_VX_MF8, + 13234 => Opcode::PseudoVWSUB_VX_MF8_MASK, + 13235 => Opcode::PseudoVWSUB_WV_M1, + 13236 => Opcode::PseudoVWSUB_WV_M1_MASK, + 13237 => Opcode::PseudoVWSUB_WV_M1_MASK_TIED, + 13238 => Opcode::PseudoVWSUB_WV_M1_TIED, + 13239 => Opcode::PseudoVWSUB_WV_M2, + 13240 => Opcode::PseudoVWSUB_WV_M2_MASK, + 13241 => Opcode::PseudoVWSUB_WV_M2_MASK_TIED, + 13242 => Opcode::PseudoVWSUB_WV_M2_TIED, + 13243 => Opcode::PseudoVWSUB_WV_M4, + 13244 => Opcode::PseudoVWSUB_WV_M4_MASK, + 13245 => Opcode::PseudoVWSUB_WV_M4_MASK_TIED, + 13246 => Opcode::PseudoVWSUB_WV_M4_TIED, + 13247 => Opcode::PseudoVWSUB_WV_MF2, + 13248 => Opcode::PseudoVWSUB_WV_MF2_MASK, + 13249 => Opcode::PseudoVWSUB_WV_MF2_MASK_TIED, + 13250 => Opcode::PseudoVWSUB_WV_MF2_TIED, + 13251 => Opcode::PseudoVWSUB_WV_MF4, + 13252 => Opcode::PseudoVWSUB_WV_MF4_MASK, + 13253 => Opcode::PseudoVWSUB_WV_MF4_MASK_TIED, + 13254 => Opcode::PseudoVWSUB_WV_MF4_TIED, + 13255 => Opcode::PseudoVWSUB_WV_MF8, + 13256 => Opcode::PseudoVWSUB_WV_MF8_MASK, + 13257 => Opcode::PseudoVWSUB_WV_MF8_MASK_TIED, + 13258 => Opcode::PseudoVWSUB_WV_MF8_TIED, + 13259 => Opcode::PseudoVWSUB_WX_M1, + 13260 => Opcode::PseudoVWSUB_WX_M1_MASK, + 13261 => Opcode::PseudoVWSUB_WX_M2, + 13262 => Opcode::PseudoVWSUB_WX_M2_MASK, + 13263 => Opcode::PseudoVWSUB_WX_M4, + 13264 => Opcode::PseudoVWSUB_WX_M4_MASK, + 13265 => Opcode::PseudoVWSUB_WX_MF2, + 13266 => Opcode::PseudoVWSUB_WX_MF2_MASK, + 13267 => Opcode::PseudoVWSUB_WX_MF4, + 13268 => Opcode::PseudoVWSUB_WX_MF4_MASK, + 13269 => Opcode::PseudoVWSUB_WX_MF8, + 13270 => Opcode::PseudoVWSUB_WX_MF8_MASK, + 13271 => Opcode::PseudoVXOR_VI_M1, + 13272 => Opcode::PseudoVXOR_VI_M1_MASK, + 13273 => Opcode::PseudoVXOR_VI_M2, + 13274 => Opcode::PseudoVXOR_VI_M2_MASK, + 13275 => Opcode::PseudoVXOR_VI_M4, + 13276 => Opcode::PseudoVXOR_VI_M4_MASK, + 13277 => Opcode::PseudoVXOR_VI_M8, + 13278 => Opcode::PseudoVXOR_VI_M8_MASK, + 13279 => Opcode::PseudoVXOR_VI_MF2, + 13280 => Opcode::PseudoVXOR_VI_MF2_MASK, + 13281 => Opcode::PseudoVXOR_VI_MF4, + 13282 => Opcode::PseudoVXOR_VI_MF4_MASK, + 13283 => Opcode::PseudoVXOR_VI_MF8, + 13284 => Opcode::PseudoVXOR_VI_MF8_MASK, + 13285 => Opcode::PseudoVXOR_VV_M1, + 13286 => Opcode::PseudoVXOR_VV_M1_MASK, + 13287 => Opcode::PseudoVXOR_VV_M2, + 13288 => Opcode::PseudoVXOR_VV_M2_MASK, + 13289 => Opcode::PseudoVXOR_VV_M4, + 13290 => Opcode::PseudoVXOR_VV_M4_MASK, + 13291 => Opcode::PseudoVXOR_VV_M8, + 13292 => Opcode::PseudoVXOR_VV_M8_MASK, + 13293 => Opcode::PseudoVXOR_VV_MF2, + 13294 => Opcode::PseudoVXOR_VV_MF2_MASK, + 13295 => Opcode::PseudoVXOR_VV_MF4, + 13296 => Opcode::PseudoVXOR_VV_MF4_MASK, + 13297 => Opcode::PseudoVXOR_VV_MF8, + 13298 => Opcode::PseudoVXOR_VV_MF8_MASK, + 13299 => Opcode::PseudoVXOR_VX_M1, + 13300 => Opcode::PseudoVXOR_VX_M1_MASK, + 13301 => Opcode::PseudoVXOR_VX_M2, + 13302 => Opcode::PseudoVXOR_VX_M2_MASK, + 13303 => Opcode::PseudoVXOR_VX_M4, + 13304 => Opcode::PseudoVXOR_VX_M4_MASK, + 13305 => Opcode::PseudoVXOR_VX_M8, + 13306 => Opcode::PseudoVXOR_VX_M8_MASK, + 13307 => Opcode::PseudoVXOR_VX_MF2, + 13308 => Opcode::PseudoVXOR_VX_MF2_MASK, + 13309 => Opcode::PseudoVXOR_VX_MF4, + 13310 => Opcode::PseudoVXOR_VX_MF4_MASK, + 13311 => Opcode::PseudoVXOR_VX_MF8, + 13312 => Opcode::PseudoVXOR_VX_MF8_MASK, + 13313 => Opcode::PseudoVZEXT_VF2_M1, + 13314 => Opcode::PseudoVZEXT_VF2_M1_MASK, + 13315 => Opcode::PseudoVZEXT_VF2_M2, + 13316 => Opcode::PseudoVZEXT_VF2_M2_MASK, + 13317 => Opcode::PseudoVZEXT_VF2_M4, + 13318 => Opcode::PseudoVZEXT_VF2_M4_MASK, + 13319 => Opcode::PseudoVZEXT_VF2_M8, + 13320 => Opcode::PseudoVZEXT_VF2_M8_MASK, + 13321 => Opcode::PseudoVZEXT_VF2_MF2, + 13322 => Opcode::PseudoVZEXT_VF2_MF2_MASK, + 13323 => Opcode::PseudoVZEXT_VF2_MF4, + 13324 => Opcode::PseudoVZEXT_VF2_MF4_MASK, + 13325 => Opcode::PseudoVZEXT_VF4_M1, + 13326 => Opcode::PseudoVZEXT_VF4_M1_MASK, + 13327 => Opcode::PseudoVZEXT_VF4_M2, + 13328 => Opcode::PseudoVZEXT_VF4_M2_MASK, + 13329 => Opcode::PseudoVZEXT_VF4_M4, + 13330 => Opcode::PseudoVZEXT_VF4_M4_MASK, + 13331 => Opcode::PseudoVZEXT_VF4_M8, + 13332 => Opcode::PseudoVZEXT_VF4_M8_MASK, + 13333 => Opcode::PseudoVZEXT_VF4_MF2, + 13334 => Opcode::PseudoVZEXT_VF4_MF2_MASK, + 13335 => Opcode::PseudoVZEXT_VF8_M1, + 13336 => Opcode::PseudoVZEXT_VF8_M1_MASK, + 13337 => Opcode::PseudoVZEXT_VF8_M2, + 13338 => Opcode::PseudoVZEXT_VF8_M2_MASK, + 13339 => Opcode::PseudoVZEXT_VF8_M4, + 13340 => Opcode::PseudoVZEXT_VF8_M4_MASK, + 13341 => Opcode::PseudoVZEXT_VF8_M8, + 13342 => Opcode::PseudoVZEXT_VF8_M8_MASK, + 13343 => Opcode::PseudoZEXT_H, + 13344 => Opcode::PseudoZEXT_W, + 13345 => Opcode::ReadCounterWide, + 13346 => Opcode::ReadFCSR, + 13347 => Opcode::ReadFFLAGS, + 13348 => Opcode::ReadFRM, + 13349 => Opcode::Select_FPR16INX_Using_CC_GPR, + 13350 => Opcode::Select_FPR16_Using_CC_GPR, + 13351 => Opcode::Select_FPR32INX_Using_CC_GPR, + 13352 => Opcode::Select_FPR32_Using_CC_GPR, + 13353 => Opcode::Select_FPR64IN32X_Using_CC_GPR, + 13354 => Opcode::Select_FPR64INX_Using_CC_GPR, + 13355 => Opcode::Select_FPR64_Using_CC_GPR, + 13356 => Opcode::Select_GPRNoX0_Using_CC_SImm16NonZero_QC, + 13357 => Opcode::Select_GPRNoX0_Using_CC_SImm5NonZero_QC, + 13358 => Opcode::Select_GPRNoX0_Using_CC_UImm16NonZero_QC, + 13359 => Opcode::Select_GPRNoX0_Using_CC_UImm5NonZero_QC, + 13360 => Opcode::Select_GPR_Using_CC_GPR, + 13361 => Opcode::Select_GPR_Using_CC_Imm5_Zibi, + 13362 => Opcode::Select_GPR_Using_CC_SImm5_CV, + 13363 => Opcode::Select_GPR_Using_CC_UImm7_NDS, + 13364 => Opcode::Select_GPR_Using_CC_UImmLog2XLen_NDS, + 13365 => Opcode::SetFCSR, + 13366 => Opcode::SetFCSRImm, + 13367 => Opcode::SplitF64Pseudo, + 13368 => Opcode::SwapFRMImm, + 13369 => Opcode::WriteFCSR, + 13370 => Opcode::WriteFCSRImm, + 13371 => Opcode::WriteFFLAGS, + 13372 => Opcode::WriteFRM, + 13373 => Opcode::WriteFRMImm, + 13374 => Opcode::WriteVXRMImm, + 13375 => Opcode::AADD, + 13376 => Opcode::AADDU, + 13377 => Opcode::ABS, + 13378 => Opcode::ABSW, + 13379 => Opcode::ADD, + 13380 => Opcode::ADDD, + 13381 => Opcode::ADDI, + 13382 => Opcode::ADDIW, + 13383 => Opcode::ADDW, + 13384 => Opcode::ADD_UW, + 13385 => Opcode::AES32DSI, + 13386 => Opcode::AES32DSMI, + 13387 => Opcode::AES32ESI, + 13388 => Opcode::AES32ESMI, + 13389 => Opcode::AES64DS, + 13390 => Opcode::AES64DSM, + 13391 => Opcode::AES64ES, + 13392 => Opcode::AES64ESM, + 13393 => Opcode::AES64IM, + 13394 => Opcode::AES64KS1I, + 13395 => Opcode::AES64KS2, + 13396 => Opcode::AMOADD_B, + 13397 => Opcode::AMOADD_B_AQ, + 13398 => Opcode::AMOADD_B_AQRL, + 13399 => Opcode::AMOADD_B_RL, + 13400 => Opcode::AMOADD_D, + 13401 => Opcode::AMOADD_D_AQ, + 13402 => Opcode::AMOADD_D_AQRL, + 13403 => Opcode::AMOADD_D_RL, + 13404 => Opcode::AMOADD_H, + 13405 => Opcode::AMOADD_H_AQ, + 13406 => Opcode::AMOADD_H_AQRL, + 13407 => Opcode::AMOADD_H_RL, + 13408 => Opcode::AMOADD_W, + 13409 => Opcode::AMOADD_W_AQ, + 13410 => Opcode::AMOADD_W_AQRL, + 13411 => Opcode::AMOADD_W_RL, + 13412 => Opcode::AMOAND_B, + 13413 => Opcode::AMOAND_B_AQ, + 13414 => Opcode::AMOAND_B_AQRL, + 13415 => Opcode::AMOAND_B_RL, + 13416 => Opcode::AMOAND_D, + 13417 => Opcode::AMOAND_D_AQ, + 13418 => Opcode::AMOAND_D_AQRL, + 13419 => Opcode::AMOAND_D_RL, + 13420 => Opcode::AMOAND_H, + 13421 => Opcode::AMOAND_H_AQ, + 13422 => Opcode::AMOAND_H_AQRL, + 13423 => Opcode::AMOAND_H_RL, + 13424 => Opcode::AMOAND_W, + 13425 => Opcode::AMOAND_W_AQ, + 13426 => Opcode::AMOAND_W_AQRL, + 13427 => Opcode::AMOAND_W_RL, + 13428 => Opcode::AMOCAS_B, + 13429 => Opcode::AMOCAS_B_AQ, + 13430 => Opcode::AMOCAS_B_AQRL, + 13431 => Opcode::AMOCAS_B_RL, + 13432 => Opcode::AMOCAS_D_RV32, + 13433 => Opcode::AMOCAS_D_RV32_AQ, + 13434 => Opcode::AMOCAS_D_RV32_AQRL, + 13435 => Opcode::AMOCAS_D_RV32_RL, + 13436 => Opcode::AMOCAS_D_RV64, + 13437 => Opcode::AMOCAS_D_RV64_AQ, + 13438 => Opcode::AMOCAS_D_RV64_AQRL, + 13439 => Opcode::AMOCAS_D_RV64_RL, + 13440 => Opcode::AMOCAS_H, + 13441 => Opcode::AMOCAS_H_AQ, + 13442 => Opcode::AMOCAS_H_AQRL, + 13443 => Opcode::AMOCAS_H_RL, + 13444 => Opcode::AMOCAS_Q, + 13445 => Opcode::AMOCAS_Q_AQ, + 13446 => Opcode::AMOCAS_Q_AQRL, + 13447 => Opcode::AMOCAS_Q_RL, + 13448 => Opcode::AMOCAS_W, + 13449 => Opcode::AMOCAS_W_AQ, + 13450 => Opcode::AMOCAS_W_AQRL, + 13451 => Opcode::AMOCAS_W_RL, + 13452 => Opcode::AMOMAXU_B, + 13453 => Opcode::AMOMAXU_B_AQ, + 13454 => Opcode::AMOMAXU_B_AQRL, + 13455 => Opcode::AMOMAXU_B_RL, + 13456 => Opcode::AMOMAXU_D, + 13457 => Opcode::AMOMAXU_D_AQ, + 13458 => Opcode::AMOMAXU_D_AQRL, + 13459 => Opcode::AMOMAXU_D_RL, + 13460 => Opcode::AMOMAXU_H, + 13461 => Opcode::AMOMAXU_H_AQ, + 13462 => Opcode::AMOMAXU_H_AQRL, + 13463 => Opcode::AMOMAXU_H_RL, + 13464 => Opcode::AMOMAXU_W, + 13465 => Opcode::AMOMAXU_W_AQ, + 13466 => Opcode::AMOMAXU_W_AQRL, + 13467 => Opcode::AMOMAXU_W_RL, + 13468 => Opcode::AMOMAX_B, + 13469 => Opcode::AMOMAX_B_AQ, + 13470 => Opcode::AMOMAX_B_AQRL, + 13471 => Opcode::AMOMAX_B_RL, + 13472 => Opcode::AMOMAX_D, + 13473 => Opcode::AMOMAX_D_AQ, + 13474 => Opcode::AMOMAX_D_AQRL, + 13475 => Opcode::AMOMAX_D_RL, + 13476 => Opcode::AMOMAX_H, + 13477 => Opcode::AMOMAX_H_AQ, + 13478 => Opcode::AMOMAX_H_AQRL, + 13479 => Opcode::AMOMAX_H_RL, + 13480 => Opcode::AMOMAX_W, + 13481 => Opcode::AMOMAX_W_AQ, + 13482 => Opcode::AMOMAX_W_AQRL, + 13483 => Opcode::AMOMAX_W_RL, + 13484 => Opcode::AMOMINU_B, + 13485 => Opcode::AMOMINU_B_AQ, + 13486 => Opcode::AMOMINU_B_AQRL, + 13487 => Opcode::AMOMINU_B_RL, + 13488 => Opcode::AMOMINU_D, + 13489 => Opcode::AMOMINU_D_AQ, + 13490 => Opcode::AMOMINU_D_AQRL, + 13491 => Opcode::AMOMINU_D_RL, + 13492 => Opcode::AMOMINU_H, + 13493 => Opcode::AMOMINU_H_AQ, + 13494 => Opcode::AMOMINU_H_AQRL, + 13495 => Opcode::AMOMINU_H_RL, + 13496 => Opcode::AMOMINU_W, + 13497 => Opcode::AMOMINU_W_AQ, + 13498 => Opcode::AMOMINU_W_AQRL, + 13499 => Opcode::AMOMINU_W_RL, + 13500 => Opcode::AMOMIN_B, + 13501 => Opcode::AMOMIN_B_AQ, + 13502 => Opcode::AMOMIN_B_AQRL, + 13503 => Opcode::AMOMIN_B_RL, + 13504 => Opcode::AMOMIN_D, + 13505 => Opcode::AMOMIN_D_AQ, + 13506 => Opcode::AMOMIN_D_AQRL, + 13507 => Opcode::AMOMIN_D_RL, + 13508 => Opcode::AMOMIN_H, + 13509 => Opcode::AMOMIN_H_AQ, + 13510 => Opcode::AMOMIN_H_AQRL, + 13511 => Opcode::AMOMIN_H_RL, + 13512 => Opcode::AMOMIN_W, + 13513 => Opcode::AMOMIN_W_AQ, + 13514 => Opcode::AMOMIN_W_AQRL, + 13515 => Opcode::AMOMIN_W_RL, + 13516 => Opcode::AMOOR_B, + 13517 => Opcode::AMOOR_B_AQ, + 13518 => Opcode::AMOOR_B_AQRL, + 13519 => Opcode::AMOOR_B_RL, + 13520 => Opcode::AMOOR_D, + 13521 => Opcode::AMOOR_D_AQ, + 13522 => Opcode::AMOOR_D_AQRL, + 13523 => Opcode::AMOOR_D_RL, + 13524 => Opcode::AMOOR_H, + 13525 => Opcode::AMOOR_H_AQ, + 13526 => Opcode::AMOOR_H_AQRL, + 13527 => Opcode::AMOOR_H_RL, + 13528 => Opcode::AMOOR_W, + 13529 => Opcode::AMOOR_W_AQ, + 13530 => Opcode::AMOOR_W_AQRL, + 13531 => Opcode::AMOOR_W_RL, + 13532 => Opcode::AMOSWAP_B, + 13533 => Opcode::AMOSWAP_B_AQ, + 13534 => Opcode::AMOSWAP_B_AQRL, + 13535 => Opcode::AMOSWAP_B_RL, + 13536 => Opcode::AMOSWAP_D, + 13537 => Opcode::AMOSWAP_D_AQ, + 13538 => Opcode::AMOSWAP_D_AQRL, + 13539 => Opcode::AMOSWAP_D_RL, + 13540 => Opcode::AMOSWAP_H, + 13541 => Opcode::AMOSWAP_H_AQ, + 13542 => Opcode::AMOSWAP_H_AQRL, + 13543 => Opcode::AMOSWAP_H_RL, + 13544 => Opcode::AMOSWAP_W, + 13545 => Opcode::AMOSWAP_W_AQ, + 13546 => Opcode::AMOSWAP_W_AQRL, + 13547 => Opcode::AMOSWAP_W_RL, + 13548 => Opcode::AMOXOR_B, + 13549 => Opcode::AMOXOR_B_AQ, + 13550 => Opcode::AMOXOR_B_AQRL, + 13551 => Opcode::AMOXOR_B_RL, + 13552 => Opcode::AMOXOR_D, + 13553 => Opcode::AMOXOR_D_AQ, + 13554 => Opcode::AMOXOR_D_AQRL, + 13555 => Opcode::AMOXOR_D_RL, + 13556 => Opcode::AMOXOR_H, + 13557 => Opcode::AMOXOR_H_AQ, + 13558 => Opcode::AMOXOR_H_AQRL, + 13559 => Opcode::AMOXOR_H_RL, + 13560 => Opcode::AMOXOR_W, + 13561 => Opcode::AMOXOR_W_AQ, + 13562 => Opcode::AMOXOR_W_AQRL, + 13563 => Opcode::AMOXOR_W_RL, + 13564 => Opcode::AND, + 13565 => Opcode::ANDI, + 13566 => Opcode::ANDN, + 13567 => Opcode::ASUB, + 13568 => Opcode::ASUBU, + 13569 => Opcode::AUIPC, + 13570 => Opcode::BCLR, + 13571 => Opcode::BCLRI, + 13572 => Opcode::BEQ, + 13573 => Opcode::BEQI, + 13574 => Opcode::BEXT, + 13575 => Opcode::BEXTI, + 13576 => Opcode::BGE, + 13577 => Opcode::BGEU, + 13578 => Opcode::BINV, + 13579 => Opcode::BINVI, + 13580 => Opcode::BLT, + 13581 => Opcode::BLTU, + 13582 => Opcode::BNE, + 13583 => Opcode::BNEI, + 13584 => Opcode::BREV8, + 13585 => Opcode::BSET, + 13586 => Opcode::BSETI, + 13587 => Opcode::CBO_CLEAN, + 13588 => Opcode::CBO_FLUSH, + 13589 => Opcode::CBO_INVAL, + 13590 => Opcode::CBO_ZERO, + 13591 => Opcode::CLMUL, + 13592 => Opcode::CLMULH, + 13593 => Opcode::CLMULR, + 13594 => Opcode::CLS, + 13595 => Opcode::CLSW, + 13596 => Opcode::CLZ, + 13597 => Opcode::CLZW, + 13598 => Opcode::CM_JALT, + 13599 => Opcode::CM_JT, + 13600 => Opcode::CM_MVA01S, + 13601 => Opcode::CM_MVSA01, + 13602 => Opcode::CM_POP, + 13603 => Opcode::CM_POPRET, + 13604 => Opcode::CM_POPRETZ, + 13605 => Opcode::CM_PUSH, + 13606 => Opcode::CPOP, + 13607 => Opcode::CPOPW, + 13608 => Opcode::CSRRC, + 13609 => Opcode::CSRRCI, + 13610 => Opcode::CSRRS, + 13611 => Opcode::CSRRSI, + 13612 => Opcode::CSRRW, + 13613 => Opcode::CSRRWI, + 13614 => Opcode::CTZ, + 13615 => Opcode::CTZW, + 13616 => Opcode::CV_ABS, + 13617 => Opcode::CV_ABS_B, + 13618 => Opcode::CV_ABS_H, + 13619 => Opcode::CV_ADDN, + 13620 => Opcode::CV_ADDNR, + 13621 => Opcode::CV_ADDRN, + 13622 => Opcode::CV_ADDRNR, + 13623 => Opcode::CV_ADDUN, + 13624 => Opcode::CV_ADDUNR, + 13625 => Opcode::CV_ADDURN, + 13626 => Opcode::CV_ADDURNR, + 13627 => Opcode::CV_ADD_B, + 13628 => Opcode::CV_ADD_DIV2, + 13629 => Opcode::CV_ADD_DIV4, + 13630 => Opcode::CV_ADD_DIV8, + 13631 => Opcode::CV_ADD_H, + 13632 => Opcode::CV_ADD_SCI_B, + 13633 => Opcode::CV_ADD_SCI_H, + 13634 => Opcode::CV_ADD_SC_B, + 13635 => Opcode::CV_ADD_SC_H, + 13636 => Opcode::CV_AND_B, + 13637 => Opcode::CV_AND_H, + 13638 => Opcode::CV_AND_SCI_B, + 13639 => Opcode::CV_AND_SCI_H, + 13640 => Opcode::CV_AND_SC_B, + 13641 => Opcode::CV_AND_SC_H, + 13642 => Opcode::CV_AVGU_B, + 13643 => Opcode::CV_AVGU_H, + 13644 => Opcode::CV_AVGU_SCI_B, + 13645 => Opcode::CV_AVGU_SCI_H, + 13646 => Opcode::CV_AVGU_SC_B, + 13647 => Opcode::CV_AVGU_SC_H, + 13648 => Opcode::CV_AVG_B, + 13649 => Opcode::CV_AVG_H, + 13650 => Opcode::CV_AVG_SCI_B, + 13651 => Opcode::CV_AVG_SCI_H, + 13652 => Opcode::CV_AVG_SC_B, + 13653 => Opcode::CV_AVG_SC_H, + 13654 => Opcode::CV_BCLR, + 13655 => Opcode::CV_BCLRR, + 13656 => Opcode::CV_BEQIMM, + 13657 => Opcode::CV_BITREV, + 13658 => Opcode::CV_BNEIMM, + 13659 => Opcode::CV_BSET, + 13660 => Opcode::CV_BSETR, + 13661 => Opcode::CV_CLB, + 13662 => Opcode::CV_CLIP, + 13663 => Opcode::CV_CLIPR, + 13664 => Opcode::CV_CLIPU, + 13665 => Opcode::CV_CLIPUR, + 13666 => Opcode::CV_CMPEQ_B, + 13667 => Opcode::CV_CMPEQ_H, + 13668 => Opcode::CV_CMPEQ_SCI_B, + 13669 => Opcode::CV_CMPEQ_SCI_H, + 13670 => Opcode::CV_CMPEQ_SC_B, + 13671 => Opcode::CV_CMPEQ_SC_H, + 13672 => Opcode::CV_CMPGEU_B, + 13673 => Opcode::CV_CMPGEU_H, + 13674 => Opcode::CV_CMPGEU_SCI_B, + 13675 => Opcode::CV_CMPGEU_SCI_H, + 13676 => Opcode::CV_CMPGEU_SC_B, + 13677 => Opcode::CV_CMPGEU_SC_H, + 13678 => Opcode::CV_CMPGE_B, + 13679 => Opcode::CV_CMPGE_H, + 13680 => Opcode::CV_CMPGE_SCI_B, + 13681 => Opcode::CV_CMPGE_SCI_H, + 13682 => Opcode::CV_CMPGE_SC_B, + 13683 => Opcode::CV_CMPGE_SC_H, + 13684 => Opcode::CV_CMPGTU_B, + 13685 => Opcode::CV_CMPGTU_H, + 13686 => Opcode::CV_CMPGTU_SCI_B, + 13687 => Opcode::CV_CMPGTU_SCI_H, + 13688 => Opcode::CV_CMPGTU_SC_B, + 13689 => Opcode::CV_CMPGTU_SC_H, + 13690 => Opcode::CV_CMPGT_B, + 13691 => Opcode::CV_CMPGT_H, + 13692 => Opcode::CV_CMPGT_SCI_B, + 13693 => Opcode::CV_CMPGT_SCI_H, + 13694 => Opcode::CV_CMPGT_SC_B, + 13695 => Opcode::CV_CMPGT_SC_H, + 13696 => Opcode::CV_CMPLEU_B, + 13697 => Opcode::CV_CMPLEU_H, + 13698 => Opcode::CV_CMPLEU_SCI_B, + 13699 => Opcode::CV_CMPLEU_SCI_H, + 13700 => Opcode::CV_CMPLEU_SC_B, + 13701 => Opcode::CV_CMPLEU_SC_H, + 13702 => Opcode::CV_CMPLE_B, + 13703 => Opcode::CV_CMPLE_H, + 13704 => Opcode::CV_CMPLE_SCI_B, + 13705 => Opcode::CV_CMPLE_SCI_H, + 13706 => Opcode::CV_CMPLE_SC_B, + 13707 => Opcode::CV_CMPLE_SC_H, + 13708 => Opcode::CV_CMPLTU_B, + 13709 => Opcode::CV_CMPLTU_H, + 13710 => Opcode::CV_CMPLTU_SCI_B, + 13711 => Opcode::CV_CMPLTU_SCI_H, + 13712 => Opcode::CV_CMPLTU_SC_B, + 13713 => Opcode::CV_CMPLTU_SC_H, + 13714 => Opcode::CV_CMPLT_B, + 13715 => Opcode::CV_CMPLT_H, + 13716 => Opcode::CV_CMPLT_SCI_B, + 13717 => Opcode::CV_CMPLT_SCI_H, + 13718 => Opcode::CV_CMPLT_SC_B, + 13719 => Opcode::CV_CMPLT_SC_H, + 13720 => Opcode::CV_CMPNE_B, + 13721 => Opcode::CV_CMPNE_H, + 13722 => Opcode::CV_CMPNE_SCI_B, + 13723 => Opcode::CV_CMPNE_SCI_H, + 13724 => Opcode::CV_CMPNE_SC_B, + 13725 => Opcode::CV_CMPNE_SC_H, + 13726 => Opcode::CV_CNT, + 13727 => Opcode::CV_CPLXCONJ, + 13728 => Opcode::CV_CPLXMUL_I, + 13729 => Opcode::CV_CPLXMUL_I_DIV2, + 13730 => Opcode::CV_CPLXMUL_I_DIV4, + 13731 => Opcode::CV_CPLXMUL_I_DIV8, + 13732 => Opcode::CV_CPLXMUL_R, + 13733 => Opcode::CV_CPLXMUL_R_DIV2, + 13734 => Opcode::CV_CPLXMUL_R_DIV4, + 13735 => Opcode::CV_CPLXMUL_R_DIV8, + 13736 => Opcode::CV_DOTSP_B, + 13737 => Opcode::CV_DOTSP_H, + 13738 => Opcode::CV_DOTSP_SCI_B, + 13739 => Opcode::CV_DOTSP_SCI_H, + 13740 => Opcode::CV_DOTSP_SC_B, + 13741 => Opcode::CV_DOTSP_SC_H, + 13742 => Opcode::CV_DOTUP_B, + 13743 => Opcode::CV_DOTUP_H, + 13744 => Opcode::CV_DOTUP_SCI_B, + 13745 => Opcode::CV_DOTUP_SCI_H, + 13746 => Opcode::CV_DOTUP_SC_B, + 13747 => Opcode::CV_DOTUP_SC_H, + 13748 => Opcode::CV_DOTUSP_B, + 13749 => Opcode::CV_DOTUSP_H, + 13750 => Opcode::CV_DOTUSP_SCI_B, + 13751 => Opcode::CV_DOTUSP_SCI_H, + 13752 => Opcode::CV_DOTUSP_SC_B, + 13753 => Opcode::CV_DOTUSP_SC_H, + 13754 => Opcode::CV_ELW, + 13755 => Opcode::CV_EXTBS, + 13756 => Opcode::CV_EXTBZ, + 13757 => Opcode::CV_EXTHS, + 13758 => Opcode::CV_EXTHZ, + 13759 => Opcode::CV_EXTRACT, + 13760 => Opcode::CV_EXTRACTR, + 13761 => Opcode::CV_EXTRACTU, + 13762 => Opcode::CV_EXTRACTUR, + 13763 => Opcode::CV_EXTRACTU_B, + 13764 => Opcode::CV_EXTRACTU_H, + 13765 => Opcode::CV_EXTRACT_B, + 13766 => Opcode::CV_EXTRACT_H, + 13767 => Opcode::CV_FF1, + 13768 => Opcode::CV_FL1, + 13769 => Opcode::CV_INSERT, + 13770 => Opcode::CV_INSERTR, + 13771 => Opcode::CV_INSERT_B, + 13772 => Opcode::CV_INSERT_H, + 13773 => Opcode::CV_LBU_ri_inc, + 13774 => Opcode::CV_LBU_rr, + 13775 => Opcode::CV_LBU_rr_inc, + 13776 => Opcode::CV_LB_ri_inc, + 13777 => Opcode::CV_LB_rr, + 13778 => Opcode::CV_LB_rr_inc, + 13779 => Opcode::CV_LHU_ri_inc, + 13780 => Opcode::CV_LHU_rr, + 13781 => Opcode::CV_LHU_rr_inc, + 13782 => Opcode::CV_LH_ri_inc, + 13783 => Opcode::CV_LH_rr, + 13784 => Opcode::CV_LH_rr_inc, + 13785 => Opcode::CV_LW_ri_inc, + 13786 => Opcode::CV_LW_rr, + 13787 => Opcode::CV_LW_rr_inc, + 13788 => Opcode::CV_MAC, + 13789 => Opcode::CV_MACHHSN, + 13790 => Opcode::CV_MACHHSRN, + 13791 => Opcode::CV_MACHHUN, + 13792 => Opcode::CV_MACHHURN, + 13793 => Opcode::CV_MACSN, + 13794 => Opcode::CV_MACSRN, + 13795 => Opcode::CV_MACUN, + 13796 => Opcode::CV_MACURN, + 13797 => Opcode::CV_MAX, + 13798 => Opcode::CV_MAXU, + 13799 => Opcode::CV_MAXU_B, + 13800 => Opcode::CV_MAXU_H, + 13801 => Opcode::CV_MAXU_SCI_B, + 13802 => Opcode::CV_MAXU_SCI_H, + 13803 => Opcode::CV_MAXU_SC_B, + 13804 => Opcode::CV_MAXU_SC_H, + 13805 => Opcode::CV_MAX_B, + 13806 => Opcode::CV_MAX_H, + 13807 => Opcode::CV_MAX_SCI_B, + 13808 => Opcode::CV_MAX_SCI_H, + 13809 => Opcode::CV_MAX_SC_B, + 13810 => Opcode::CV_MAX_SC_H, + 13811 => Opcode::CV_MIN, + 13812 => Opcode::CV_MINU, + 13813 => Opcode::CV_MINU_B, + 13814 => Opcode::CV_MINU_H, + 13815 => Opcode::CV_MINU_SCI_B, + 13816 => Opcode::CV_MINU_SCI_H, + 13817 => Opcode::CV_MINU_SC_B, + 13818 => Opcode::CV_MINU_SC_H, + 13819 => Opcode::CV_MIN_B, + 13820 => Opcode::CV_MIN_H, + 13821 => Opcode::CV_MIN_SCI_B, + 13822 => Opcode::CV_MIN_SCI_H, + 13823 => Opcode::CV_MIN_SC_B, + 13824 => Opcode::CV_MIN_SC_H, + 13825 => Opcode::CV_MSU, + 13826 => Opcode::CV_MULHHSN, + 13827 => Opcode::CV_MULHHSRN, + 13828 => Opcode::CV_MULHHUN, + 13829 => Opcode::CV_MULHHURN, + 13830 => Opcode::CV_MULSN, + 13831 => Opcode::CV_MULSRN, + 13832 => Opcode::CV_MULUN, + 13833 => Opcode::CV_MULURN, + 13834 => Opcode::CV_OR_B, + 13835 => Opcode::CV_OR_H, + 13836 => Opcode::CV_OR_SCI_B, + 13837 => Opcode::CV_OR_SCI_H, + 13838 => Opcode::CV_OR_SC_B, + 13839 => Opcode::CV_OR_SC_H, + 13840 => Opcode::CV_PACK, + 13841 => Opcode::CV_PACKHI_B, + 13842 => Opcode::CV_PACKLO_B, + 13843 => Opcode::CV_PACK_H, + 13844 => Opcode::CV_ROR, + 13845 => Opcode::CV_SB_ri_inc, + 13846 => Opcode::CV_SB_rr, + 13847 => Opcode::CV_SB_rr_inc, + 13848 => Opcode::CV_SDOTSP_B, + 13849 => Opcode::CV_SDOTSP_H, + 13850 => Opcode::CV_SDOTSP_SCI_B, + 13851 => Opcode::CV_SDOTSP_SCI_H, + 13852 => Opcode::CV_SDOTSP_SC_B, + 13853 => Opcode::CV_SDOTSP_SC_H, + 13854 => Opcode::CV_SDOTUP_B, + 13855 => Opcode::CV_SDOTUP_H, + 13856 => Opcode::CV_SDOTUP_SCI_B, + 13857 => Opcode::CV_SDOTUP_SCI_H, + 13858 => Opcode::CV_SDOTUP_SC_B, + 13859 => Opcode::CV_SDOTUP_SC_H, + 13860 => Opcode::CV_SDOTUSP_B, + 13861 => Opcode::CV_SDOTUSP_H, + 13862 => Opcode::CV_SDOTUSP_SCI_B, + 13863 => Opcode::CV_SDOTUSP_SCI_H, + 13864 => Opcode::CV_SDOTUSP_SC_B, + 13865 => Opcode::CV_SDOTUSP_SC_H, + 13866 => Opcode::CV_SHUFFLE2_B, + 13867 => Opcode::CV_SHUFFLE2_H, + 13868 => Opcode::CV_SHUFFLEI0_SCI_B, + 13869 => Opcode::CV_SHUFFLEI1_SCI_B, + 13870 => Opcode::CV_SHUFFLEI2_SCI_B, + 13871 => Opcode::CV_SHUFFLEI3_SCI_B, + 13872 => Opcode::CV_SHUFFLE_B, + 13873 => Opcode::CV_SHUFFLE_H, + 13874 => Opcode::CV_SHUFFLE_SCI_H, + 13875 => Opcode::CV_SH_ri_inc, + 13876 => Opcode::CV_SH_rr, + 13877 => Opcode::CV_SH_rr_inc, + 13878 => Opcode::CV_SLE, + 13879 => Opcode::CV_SLEU, + 13880 => Opcode::CV_SLL_B, + 13881 => Opcode::CV_SLL_H, + 13882 => Opcode::CV_SLL_SCI_B, + 13883 => Opcode::CV_SLL_SCI_H, + 13884 => Opcode::CV_SLL_SC_B, + 13885 => Opcode::CV_SLL_SC_H, + 13886 => Opcode::CV_SRA_B, + 13887 => Opcode::CV_SRA_H, + 13888 => Opcode::CV_SRA_SCI_B, + 13889 => Opcode::CV_SRA_SCI_H, + 13890 => Opcode::CV_SRA_SC_B, + 13891 => Opcode::CV_SRA_SC_H, + 13892 => Opcode::CV_SRL_B, + 13893 => Opcode::CV_SRL_H, + 13894 => Opcode::CV_SRL_SCI_B, + 13895 => Opcode::CV_SRL_SCI_H, + 13896 => Opcode::CV_SRL_SC_B, + 13897 => Opcode::CV_SRL_SC_H, + 13898 => Opcode::CV_SUBN, + 13899 => Opcode::CV_SUBNR, + 13900 => Opcode::CV_SUBRN, + 13901 => Opcode::CV_SUBRNR, + 13902 => Opcode::CV_SUBROTMJ, + 13903 => Opcode::CV_SUBROTMJ_DIV2, + 13904 => Opcode::CV_SUBROTMJ_DIV4, + 13905 => Opcode::CV_SUBROTMJ_DIV8, + 13906 => Opcode::CV_SUBUN, + 13907 => Opcode::CV_SUBUNR, + 13908 => Opcode::CV_SUBURN, + 13909 => Opcode::CV_SUBURNR, + 13910 => Opcode::CV_SUB_B, + 13911 => Opcode::CV_SUB_DIV2, + 13912 => Opcode::CV_SUB_DIV4, + 13913 => Opcode::CV_SUB_DIV8, + 13914 => Opcode::CV_SUB_H, + 13915 => Opcode::CV_SUB_SCI_B, + 13916 => Opcode::CV_SUB_SCI_H, + 13917 => Opcode::CV_SUB_SC_B, + 13918 => Opcode::CV_SUB_SC_H, + 13919 => Opcode::CV_SW_ri_inc, + 13920 => Opcode::CV_SW_rr, + 13921 => Opcode::CV_SW_rr_inc, + 13922 => Opcode::CV_XOR_B, + 13923 => Opcode::CV_XOR_H, + 13924 => Opcode::CV_XOR_SCI_B, + 13925 => Opcode::CV_XOR_SCI_H, + 13926 => Opcode::CV_XOR_SC_B, + 13927 => Opcode::CV_XOR_SC_H, + 13928 => Opcode::CZERO_EQZ, + 13929 => Opcode::CZERO_NEZ, + 13930 => Opcode::C_ADD, + 13931 => Opcode::C_ADDI, + 13932 => Opcode::C_ADDI16SP, + 13933 => Opcode::C_ADDI4SPN, + 13934 => Opcode::C_ADDIW, + 13935 => Opcode::C_ADDW, + 13936 => Opcode::C_AND, + 13937 => Opcode::C_ANDI, + 13938 => Opcode::C_BEQZ, + 13939 => Opcode::C_BNEZ, + 13940 => Opcode::C_EBREAK, + 13941 => Opcode::C_FLD, + 13942 => Opcode::C_FLDSP, + 13943 => Opcode::C_FLW, + 13944 => Opcode::C_FLWSP, + 13945 => Opcode::C_FSD, + 13946 => Opcode::C_FSDSP, + 13947 => Opcode::C_FSW, + 13948 => Opcode::C_FSWSP, + 13949 => Opcode::C_J, + 13950 => Opcode::C_JAL, + 13951 => Opcode::C_JALR, + 13952 => Opcode::C_JR, + 13953 => Opcode::C_LBU, + 13954 => Opcode::C_LD, + 13955 => Opcode::C_LDSP, + 13956 => Opcode::C_LDSP_RV32, + 13957 => Opcode::C_LD_RV32, + 13958 => Opcode::C_LH, + 13959 => Opcode::C_LHU, + 13960 => Opcode::C_LH_INX, + 13961 => Opcode::C_LI, + 13962 => Opcode::C_LUI, + 13963 => Opcode::C_LW, + 13964 => Opcode::C_LWSP, + 13965 => Opcode::C_LWSP_INX, + 13966 => Opcode::C_LW_INX, + 13967 => Opcode::C_MOP_1, + 13968 => Opcode::C_MOP_11, + 13969 => Opcode::C_MOP_13, + 13970 => Opcode::C_MOP_15, + 13971 => Opcode::C_MOP_3, + 13972 => Opcode::C_MOP_5, + 13973 => Opcode::C_MOP_7, + 13974 => Opcode::C_MOP_9, + 13975 => Opcode::C_MUL, + 13976 => Opcode::C_MV, + 13977 => Opcode::C_NOP, + 13978 => Opcode::C_NOP_HINT, + 13979 => Opcode::C_NOT, + 13980 => Opcode::C_OR, + 13981 => Opcode::C_SB, + 13982 => Opcode::C_SD, + 13983 => Opcode::C_SDSP, + 13984 => Opcode::C_SDSP_RV32, + 13985 => Opcode::C_SD_RV32, + 13986 => Opcode::C_SEXT_B, + 13987 => Opcode::C_SEXT_H, + 13988 => Opcode::C_SH, + 13989 => Opcode::C_SH_INX, + 13990 => Opcode::C_SLLI, + 13991 => Opcode::C_SRAI, + 13992 => Opcode::C_SRLI, + 13993 => Opcode::C_SSPOPCHK, + 13994 => Opcode::C_SSPUSH, + 13995 => Opcode::C_SUB, + 13996 => Opcode::C_SUBW, + 13997 => Opcode::C_SW, + 13998 => Opcode::C_SWSP, + 13999 => Opcode::C_SWSP_INX, + 14000 => Opcode::C_SW_INX, + 14001 => Opcode::C_UNIMP, + 14002 => Opcode::C_XOR, + 14003 => Opcode::C_ZEXT_B, + 14004 => Opcode::C_ZEXT_H, + 14005 => Opcode::C_ZEXT_W, + 14006 => Opcode::DIV, + 14007 => Opcode::DIVU, + 14008 => Opcode::DIVUW, + 14009 => Opcode::DIVW, + 14010 => Opcode::DRET, + 14011 => Opcode::EBREAK, + 14012 => Opcode::ECALL, + 14013 => Opcode::FADD_D, + 14014 => Opcode::FADD_D_IN32X, + 14015 => Opcode::FADD_D_INX, + 14016 => Opcode::FADD_H, + 14017 => Opcode::FADD_H_INX, + 14018 => Opcode::FADD_Q, + 14019 => Opcode::FADD_S, + 14020 => Opcode::FADD_S_INX, + 14021 => Opcode::FCLASS_D, + 14022 => Opcode::FCLASS_D_IN32X, + 14023 => Opcode::FCLASS_D_INX, + 14024 => Opcode::FCLASS_H, + 14025 => Opcode::FCLASS_H_INX, + 14026 => Opcode::FCLASS_Q, + 14027 => Opcode::FCLASS_S, + 14028 => Opcode::FCLASS_S_INX, + 14029 => Opcode::FCVTMOD_W_D, + 14030 => Opcode::FCVT_BF16_S, + 14031 => Opcode::FCVT_D_H, + 14032 => Opcode::FCVT_D_H_IN32X, + 14033 => Opcode::FCVT_D_H_INX, + 14034 => Opcode::FCVT_D_L, + 14035 => Opcode::FCVT_D_LU, + 14036 => Opcode::FCVT_D_LU_INX, + 14037 => Opcode::FCVT_D_L_INX, + 14038 => Opcode::FCVT_D_Q, + 14039 => Opcode::FCVT_D_S, + 14040 => Opcode::FCVT_D_S_IN32X, + 14041 => Opcode::FCVT_D_S_INX, + 14042 => Opcode::FCVT_D_W, + 14043 => Opcode::FCVT_D_WU, + 14044 => Opcode::FCVT_D_WU_IN32X, + 14045 => Opcode::FCVT_D_WU_INX, + 14046 => Opcode::FCVT_D_W_IN32X, + 14047 => Opcode::FCVT_D_W_INX, + 14048 => Opcode::FCVT_H_D, + 14049 => Opcode::FCVT_H_D_IN32X, + 14050 => Opcode::FCVT_H_D_INX, + 14051 => Opcode::FCVT_H_L, + 14052 => Opcode::FCVT_H_LU, + 14053 => Opcode::FCVT_H_LU_INX, + 14054 => Opcode::FCVT_H_L_INX, + 14055 => Opcode::FCVT_H_S, + 14056 => Opcode::FCVT_H_S_INX, + 14057 => Opcode::FCVT_H_W, + 14058 => Opcode::FCVT_H_WU, + 14059 => Opcode::FCVT_H_WU_INX, + 14060 => Opcode::FCVT_H_W_INX, + 14061 => Opcode::FCVT_LU_D, + 14062 => Opcode::FCVT_LU_D_INX, + 14063 => Opcode::FCVT_LU_H, + 14064 => Opcode::FCVT_LU_H_INX, + 14065 => Opcode::FCVT_LU_Q, + 14066 => Opcode::FCVT_LU_S, + 14067 => Opcode::FCVT_LU_S_INX, + 14068 => Opcode::FCVT_L_D, + 14069 => Opcode::FCVT_L_D_INX, + 14070 => Opcode::FCVT_L_H, + 14071 => Opcode::FCVT_L_H_INX, + 14072 => Opcode::FCVT_L_Q, + 14073 => Opcode::FCVT_L_S, + 14074 => Opcode::FCVT_L_S_INX, + 14075 => Opcode::FCVT_Q_D, + 14076 => Opcode::FCVT_Q_L, + 14077 => Opcode::FCVT_Q_LU, + 14078 => Opcode::FCVT_Q_S, + 14079 => Opcode::FCVT_Q_W, + 14080 => Opcode::FCVT_Q_WU, + 14081 => Opcode::FCVT_S_BF16, + 14082 => Opcode::FCVT_S_D, + 14083 => Opcode::FCVT_S_D_IN32X, + 14084 => Opcode::FCVT_S_D_INX, + 14085 => Opcode::FCVT_S_H, + 14086 => Opcode::FCVT_S_H_INX, + 14087 => Opcode::FCVT_S_L, + 14088 => Opcode::FCVT_S_LU, + 14089 => Opcode::FCVT_S_LU_INX, + 14090 => Opcode::FCVT_S_L_INX, + 14091 => Opcode::FCVT_S_Q, + 14092 => Opcode::FCVT_S_W, + 14093 => Opcode::FCVT_S_WU, + 14094 => Opcode::FCVT_S_WU_INX, + 14095 => Opcode::FCVT_S_W_INX, + 14096 => Opcode::FCVT_WU_D, + 14097 => Opcode::FCVT_WU_D_IN32X, + 14098 => Opcode::FCVT_WU_D_INX, + 14099 => Opcode::FCVT_WU_H, + 14100 => Opcode::FCVT_WU_H_INX, + 14101 => Opcode::FCVT_WU_Q, + 14102 => Opcode::FCVT_WU_S, + 14103 => Opcode::FCVT_WU_S_INX, + 14104 => Opcode::FCVT_W_D, + 14105 => Opcode::FCVT_W_D_IN32X, + 14106 => Opcode::FCVT_W_D_INX, + 14107 => Opcode::FCVT_W_H, + 14108 => Opcode::FCVT_W_H_INX, + 14109 => Opcode::FCVT_W_Q, + 14110 => Opcode::FCVT_W_S, + 14111 => Opcode::FCVT_W_S_INX, + 14112 => Opcode::FDIV_D, + 14113 => Opcode::FDIV_D_IN32X, + 14114 => Opcode::FDIV_D_INX, + 14115 => Opcode::FDIV_H, + 14116 => Opcode::FDIV_H_INX, + 14117 => Opcode::FDIV_Q, + 14118 => Opcode::FDIV_S, + 14119 => Opcode::FDIV_S_INX, + 14120 => Opcode::FENCE, + 14121 => Opcode::FENCE_I, + 14122 => Opcode::FENCE_TSO, + 14123 => Opcode::FEQ_D, + 14124 => Opcode::FEQ_D_IN32X, + 14125 => Opcode::FEQ_D_INX, + 14126 => Opcode::FEQ_H, + 14127 => Opcode::FEQ_H_INX, + 14128 => Opcode::FEQ_Q, + 14129 => Opcode::FEQ_S, + 14130 => Opcode::FEQ_S_INX, + 14131 => Opcode::FLD, + 14132 => Opcode::FLEQ_D, + 14133 => Opcode::FLEQ_H, + 14134 => Opcode::FLEQ_Q, + 14135 => Opcode::FLEQ_S, + 14136 => Opcode::FLE_D, + 14137 => Opcode::FLE_D_IN32X, + 14138 => Opcode::FLE_D_INX, + 14139 => Opcode::FLE_H, + 14140 => Opcode::FLE_H_INX, + 14141 => Opcode::FLE_Q, + 14142 => Opcode::FLE_S, + 14143 => Opcode::FLE_S_INX, + 14144 => Opcode::FLH, + 14145 => Opcode::FLI_D, + 14146 => Opcode::FLI_H, + 14147 => Opcode::FLI_Q, + 14148 => Opcode::FLI_S, + 14149 => Opcode::FLQ, + 14150 => Opcode::FLTQ_D, + 14151 => Opcode::FLTQ_H, + 14152 => Opcode::FLTQ_Q, + 14153 => Opcode::FLTQ_S, + 14154 => Opcode::FLT_D, + 14155 => Opcode::FLT_D_IN32X, + 14156 => Opcode::FLT_D_INX, + 14157 => Opcode::FLT_H, + 14158 => Opcode::FLT_H_INX, + 14159 => Opcode::FLT_Q, + 14160 => Opcode::FLT_S, + 14161 => Opcode::FLT_S_INX, + 14162 => Opcode::FLW, + 14163 => Opcode::FMADD_D, + 14164 => Opcode::FMADD_D_IN32X, + 14165 => Opcode::FMADD_D_INX, + 14166 => Opcode::FMADD_H, + 14167 => Opcode::FMADD_H_INX, + 14168 => Opcode::FMADD_Q, + 14169 => Opcode::FMADD_S, + 14170 => Opcode::FMADD_S_INX, + 14171 => Opcode::FMAXM_D, + 14172 => Opcode::FMAXM_H, + 14173 => Opcode::FMAXM_Q, + 14174 => Opcode::FMAXM_S, + 14175 => Opcode::FMAX_D, + 14176 => Opcode::FMAX_D_IN32X, + 14177 => Opcode::FMAX_D_INX, + 14178 => Opcode::FMAX_H, + 14179 => Opcode::FMAX_H_INX, + 14180 => Opcode::FMAX_Q, + 14181 => Opcode::FMAX_S, + 14182 => Opcode::FMAX_S_INX, + 14183 => Opcode::FMINM_D, + 14184 => Opcode::FMINM_H, + 14185 => Opcode::FMINM_Q, + 14186 => Opcode::FMINM_S, + 14187 => Opcode::FMIN_D, + 14188 => Opcode::FMIN_D_IN32X, + 14189 => Opcode::FMIN_D_INX, + 14190 => Opcode::FMIN_H, + 14191 => Opcode::FMIN_H_INX, + 14192 => Opcode::FMIN_Q, + 14193 => Opcode::FMIN_S, + 14194 => Opcode::FMIN_S_INX, + 14195 => Opcode::FMSUB_D, + 14196 => Opcode::FMSUB_D_IN32X, + 14197 => Opcode::FMSUB_D_INX, + 14198 => Opcode::FMSUB_H, + 14199 => Opcode::FMSUB_H_INX, + 14200 => Opcode::FMSUB_Q, + 14201 => Opcode::FMSUB_S, + 14202 => Opcode::FMSUB_S_INX, + 14203 => Opcode::FMUL_D, + 14204 => Opcode::FMUL_D_IN32X, + 14205 => Opcode::FMUL_D_INX, + 14206 => Opcode::FMUL_H, + 14207 => Opcode::FMUL_H_INX, + 14208 => Opcode::FMUL_Q, + 14209 => Opcode::FMUL_S, + 14210 => Opcode::FMUL_S_INX, + 14211 => Opcode::FMVH_X_D, + 14212 => Opcode::FMVH_X_Q, + 14213 => Opcode::FMVP_D_X, + 14214 => Opcode::FMVP_Q_X, + 14215 => Opcode::FMV_D_X, + 14216 => Opcode::FMV_H_X, + 14217 => Opcode::FMV_W_X, + 14218 => Opcode::FMV_X_D, + 14219 => Opcode::FMV_X_H, + 14220 => Opcode::FMV_X_W, + 14221 => Opcode::FMV_X_W_FPR64, + 14222 => Opcode::FNMADD_D, + 14223 => Opcode::FNMADD_D_IN32X, + 14224 => Opcode::FNMADD_D_INX, + 14225 => Opcode::FNMADD_H, + 14226 => Opcode::FNMADD_H_INX, + 14227 => Opcode::FNMADD_Q, + 14228 => Opcode::FNMADD_S, + 14229 => Opcode::FNMADD_S_INX, + 14230 => Opcode::FNMSUB_D, + 14231 => Opcode::FNMSUB_D_IN32X, + 14232 => Opcode::FNMSUB_D_INX, + 14233 => Opcode::FNMSUB_H, + 14234 => Opcode::FNMSUB_H_INX, + 14235 => Opcode::FNMSUB_Q, + 14236 => Opcode::FNMSUB_S, + 14237 => Opcode::FNMSUB_S_INX, + 14238 => Opcode::FROUNDNX_D, + 14239 => Opcode::FROUNDNX_H, + 14240 => Opcode::FROUNDNX_Q, + 14241 => Opcode::FROUNDNX_S, + 14242 => Opcode::FROUND_D, + 14243 => Opcode::FROUND_H, + 14244 => Opcode::FROUND_Q, + 14245 => Opcode::FROUND_S, + 14246 => Opcode::FSD, + 14247 => Opcode::FSGNJN_D, + 14248 => Opcode::FSGNJN_D_IN32X, + 14249 => Opcode::FSGNJN_D_INX, + 14250 => Opcode::FSGNJN_H, + 14251 => Opcode::FSGNJN_H_INX, + 14252 => Opcode::FSGNJN_Q, + 14253 => Opcode::FSGNJN_S, + 14254 => Opcode::FSGNJN_S_INX, + 14255 => Opcode::FSGNJX_D, + 14256 => Opcode::FSGNJX_D_IN32X, + 14257 => Opcode::FSGNJX_D_INX, + 14258 => Opcode::FSGNJX_H, + 14259 => Opcode::FSGNJX_H_INX, + 14260 => Opcode::FSGNJX_Q, + 14261 => Opcode::FSGNJX_S, + 14262 => Opcode::FSGNJX_S_INX, + 14263 => Opcode::FSGNJ_D, + 14264 => Opcode::FSGNJ_D_IN32X, + 14265 => Opcode::FSGNJ_D_INX, + 14266 => Opcode::FSGNJ_H, + 14267 => Opcode::FSGNJ_H_INX, + 14268 => Opcode::FSGNJ_Q, + 14269 => Opcode::FSGNJ_S, + 14270 => Opcode::FSGNJ_S_INX, + 14271 => Opcode::FSH, + 14272 => Opcode::FSQ, + 14273 => Opcode::FSQRT_D, + 14274 => Opcode::FSQRT_D_IN32X, + 14275 => Opcode::FSQRT_D_INX, + 14276 => Opcode::FSQRT_H, + 14277 => Opcode::FSQRT_H_INX, + 14278 => Opcode::FSQRT_Q, + 14279 => Opcode::FSQRT_S, + 14280 => Opcode::FSQRT_S_INX, + 14281 => Opcode::FSUB_D, + 14282 => Opcode::FSUB_D_IN32X, + 14283 => Opcode::FSUB_D_INX, + 14284 => Opcode::FSUB_H, + 14285 => Opcode::FSUB_H_INX, + 14286 => Opcode::FSUB_Q, + 14287 => Opcode::FSUB_S, + 14288 => Opcode::FSUB_S_INX, + 14289 => Opcode::FSW, + 14290 => Opcode::HFENCE_GVMA, + 14291 => Opcode::HFENCE_VVMA, + 14292 => Opcode::HINVAL_GVMA, + 14293 => Opcode::HINVAL_VVMA, + 14294 => Opcode::HLVX_HU, + 14295 => Opcode::HLVX_WU, + 14296 => Opcode::HLV_B, + 14297 => Opcode::HLV_BU, + 14298 => Opcode::HLV_D, + 14299 => Opcode::HLV_H, + 14300 => Opcode::HLV_HU, + 14301 => Opcode::HLV_W, + 14302 => Opcode::HLV_WU, + 14303 => Opcode::HSV_B, + 14304 => Opcode::HSV_D, + 14305 => Opcode::HSV_H, + 14306 => Opcode::HSV_W, + 14307 => Opcode::Insn16, + 14308 => Opcode::Insn32, + 14309 => Opcode::Insn48, + 14310 => Opcode::Insn64, + 14311 => Opcode::InsnB, + 14312 => Opcode::InsnCA, + 14313 => Opcode::InsnCB, + 14314 => Opcode::InsnCI, + 14315 => Opcode::InsnCIW, + 14316 => Opcode::InsnCJ, + 14317 => Opcode::InsnCL, + 14318 => Opcode::InsnCR, + 14319 => Opcode::InsnCS, + 14320 => Opcode::InsnCSS, + 14321 => Opcode::InsnI, + 14322 => Opcode::InsnI_Mem, + 14323 => Opcode::InsnJ, + 14324 => Opcode::InsnQC_EAI, + 14325 => Opcode::InsnQC_EB, + 14326 => Opcode::InsnQC_EI, + 14327 => Opcode::InsnQC_EI_Mem, + 14328 => Opcode::InsnQC_EJ, + 14329 => Opcode::InsnQC_ES, + 14330 => Opcode::InsnR, + 14331 => Opcode::InsnR4, + 14332 => Opcode::InsnS, + 14333 => Opcode::InsnU, + 14334 => Opcode::JAL, + 14335 => Opcode::JALR, + 14336 => Opcode::LB, + 14337 => Opcode::LBU, + 14338 => Opcode::LB_AQ, + 14339 => Opcode::LB_AQRL, + 14340 => Opcode::LD, + 14341 => Opcode::LD_AQ, + 14342 => Opcode::LD_AQRL, + 14343 => Opcode::LD_RV32, + 14344 => Opcode::LH, + 14345 => Opcode::LHU, + 14346 => Opcode::LH_AQ, + 14347 => Opcode::LH_AQRL, + 14348 => Opcode::LH_INX, + 14349 => Opcode::LR_D, + 14350 => Opcode::LR_D_AQ, + 14351 => Opcode::LR_D_AQRL, + 14352 => Opcode::LR_D_RL, + 14353 => Opcode::LR_W, + 14354 => Opcode::LR_W_AQ, + 14355 => Opcode::LR_W_AQRL, + 14356 => Opcode::LR_W_RL, + 14357 => Opcode::LUI, + 14358 => Opcode::LW, + 14359 => Opcode::LWU, + 14360 => Opcode::LW_AQ, + 14361 => Opcode::LW_AQRL, + 14362 => Opcode::LW_INX, + 14363 => Opcode::MACCSU_H00, + 14364 => Opcode::MACCSU_H11, + 14365 => Opcode::MACCSU_W00, + 14366 => Opcode::MACCSU_W11, + 14367 => Opcode::MACCU_H00, + 14368 => Opcode::MACCU_H01, + 14369 => Opcode::MACCU_H11, + 14370 => Opcode::MACCU_W00, + 14371 => Opcode::MACCU_W01, + 14372 => Opcode::MACCU_W11, + 14373 => Opcode::MACC_H00, + 14374 => Opcode::MACC_H01, + 14375 => Opcode::MACC_H11, + 14376 => Opcode::MACC_W00, + 14377 => Opcode::MACC_W01, + 14378 => Opcode::MACC_W11, + 14379 => Opcode::MAX, + 14380 => Opcode::MAXU, + 14381 => Opcode::MERGE, + 14382 => Opcode::MHACC, + 14383 => Opcode::MHACCSU, + 14384 => Opcode::MHACCSU_H0, + 14385 => Opcode::MHACCSU_H1, + 14386 => Opcode::MHACCU, + 14387 => Opcode::MHACC_H0, + 14388 => Opcode::MHACC_H1, + 14389 => Opcode::MHRACC, + 14390 => Opcode::MHRACCSU, + 14391 => Opcode::MHRACCU, + 14392 => Opcode::MIN, + 14393 => Opcode::MINU, + 14394 => Opcode::MIPS_CCMOV, + 14395 => Opcode::MIPS_EHB, + 14396 => Opcode::MIPS_IHB, + 14397 => Opcode::MIPS_LDP, + 14398 => Opcode::MIPS_LWP, + 14399 => Opcode::MIPS_PAUSE, + 14400 => Opcode::MIPS_PREF, + 14401 => Opcode::MIPS_SDP, + 14402 => Opcode::MIPS_SWP, + 14403 => Opcode::MNRET, + 14404 => Opcode::MOP_RR_0, + 14405 => Opcode::MOP_RR_1, + 14406 => Opcode::MOP_RR_2, + 14407 => Opcode::MOP_RR_3, + 14408 => Opcode::MOP_RR_4, + 14409 => Opcode::MOP_RR_5, + 14410 => Opcode::MOP_RR_6, + 14411 => Opcode::MOP_RR_7, + 14412 => Opcode::MOP_R_0, + 14413 => Opcode::MOP_R_1, + 14414 => Opcode::MOP_R_10, + 14415 => Opcode::MOP_R_11, + 14416 => Opcode::MOP_R_12, + 14417 => Opcode::MOP_R_13, + 14418 => Opcode::MOP_R_14, + 14419 => Opcode::MOP_R_15, + 14420 => Opcode::MOP_R_16, + 14421 => Opcode::MOP_R_17, + 14422 => Opcode::MOP_R_18, + 14423 => Opcode::MOP_R_19, + 14424 => Opcode::MOP_R_2, + 14425 => Opcode::MOP_R_20, + 14426 => Opcode::MOP_R_21, + 14427 => Opcode::MOP_R_22, + 14428 => Opcode::MOP_R_23, + 14429 => Opcode::MOP_R_24, + 14430 => Opcode::MOP_R_25, + 14431 => Opcode::MOP_R_26, + 14432 => Opcode::MOP_R_27, + 14433 => Opcode::MOP_R_28, + 14434 => Opcode::MOP_R_29, + 14435 => Opcode::MOP_R_3, + 14436 => Opcode::MOP_R_30, + 14437 => Opcode::MOP_R_31, + 14438 => Opcode::MOP_R_4, + 14439 => Opcode::MOP_R_5, + 14440 => Opcode::MOP_R_6, + 14441 => Opcode::MOP_R_7, + 14442 => Opcode::MOP_R_8, + 14443 => Opcode::MOP_R_9, + 14444 => Opcode::MQACC_H00, + 14445 => Opcode::MQACC_H01, + 14446 => Opcode::MQACC_H11, + 14447 => Opcode::MQACC_W00, + 14448 => Opcode::MQACC_W01, + 14449 => Opcode::MQACC_W11, + 14450 => Opcode::MQRACC_H00, + 14451 => Opcode::MQRACC_H01, + 14452 => Opcode::MQRACC_H11, + 14453 => Opcode::MQRACC_W00, + 14454 => Opcode::MQRACC_W01, + 14455 => Opcode::MQRACC_W11, + 14456 => Opcode::MRET, + 14457 => Opcode::MSEQ, + 14458 => Opcode::MSLT, + 14459 => Opcode::MSLTU, + 14460 => Opcode::MUL, + 14461 => Opcode::MULH, + 14462 => Opcode::MULHR, + 14463 => Opcode::MULHRSU, + 14464 => Opcode::MULHRU, + 14465 => Opcode::MULHSU, + 14466 => Opcode::MULHSU_H0, + 14467 => Opcode::MULHSU_H1, + 14468 => Opcode::MULHU, + 14469 => Opcode::MULH_H0, + 14470 => Opcode::MULH_H1, + 14471 => Opcode::MULQ, + 14472 => Opcode::MULQR, + 14473 => Opcode::MULSU_H00, + 14474 => Opcode::MULSU_H11, + 14475 => Opcode::MULSU_W00, + 14476 => Opcode::MULSU_W11, + 14477 => Opcode::MULU_H00, + 14478 => Opcode::MULU_H01, + 14479 => Opcode::MULU_H11, + 14480 => Opcode::MULU_W00, + 14481 => Opcode::MULU_W01, + 14482 => Opcode::MULU_W11, + 14483 => Opcode::MULW, + 14484 => Opcode::MUL_H00, + 14485 => Opcode::MUL_H01, + 14486 => Opcode::MUL_H11, + 14487 => Opcode::MUL_W00, + 14488 => Opcode::MUL_W01, + 14489 => Opcode::MUL_W11, + 14490 => Opcode::MVM, + 14491 => Opcode::MVMN, + 14492 => Opcode::NCLIP, + 14493 => Opcode::NCLIPI, + 14494 => Opcode::NCLIPIU, + 14495 => Opcode::NCLIPR, + 14496 => Opcode::NCLIPRI, + 14497 => Opcode::NCLIPRIU, + 14498 => Opcode::NCLIPRU, + 14499 => Opcode::NCLIPU, + 14500 => Opcode::NDS_ADDIGP, + 14501 => Opcode::NDS_BBC, + 14502 => Opcode::NDS_BBS, + 14503 => Opcode::NDS_BEQC, + 14504 => Opcode::NDS_BFOS, + 14505 => Opcode::NDS_BFOZ, + 14506 => Opcode::NDS_BNEC, + 14507 => Opcode::NDS_FCVT_BF16_S, + 14508 => Opcode::NDS_FCVT_S_BF16, + 14509 => Opcode::NDS_FFB, + 14510 => Opcode::NDS_FFMISM, + 14511 => Opcode::NDS_FFZMISM, + 14512 => Opcode::NDS_FLMISM, + 14513 => Opcode::NDS_FMV_BF16_X, + 14514 => Opcode::NDS_FMV_X_BF16, + 14515 => Opcode::NDS_LBGP, + 14516 => Opcode::NDS_LBUGP, + 14517 => Opcode::NDS_LDGP, + 14518 => Opcode::NDS_LEA_B_ZE, + 14519 => Opcode::NDS_LEA_D, + 14520 => Opcode::NDS_LEA_D_ZE, + 14521 => Opcode::NDS_LEA_H, + 14522 => Opcode::NDS_LEA_H_ZE, + 14523 => Opcode::NDS_LEA_W, + 14524 => Opcode::NDS_LEA_W_ZE, + 14525 => Opcode::NDS_LHGP, + 14526 => Opcode::NDS_LHUGP, + 14527 => Opcode::NDS_LWGP, + 14528 => Opcode::NDS_LWUGP, + 14529 => Opcode::NDS_SBGP, + 14530 => Opcode::NDS_SDGP, + 14531 => Opcode::NDS_SHGP, + 14532 => Opcode::NDS_SWGP, + 14533 => Opcode::NDS_VD4DOTSU_VV, + 14534 => Opcode::NDS_VD4DOTS_VV, + 14535 => Opcode::NDS_VD4DOTU_VV, + 14536 => Opcode::NDS_VFNCVT_BF16_S, + 14537 => Opcode::NDS_VFPMADB_VF, + 14538 => Opcode::NDS_VFPMADT_VF, + 14539 => Opcode::NDS_VFWCVT_F_B, + 14540 => Opcode::NDS_VFWCVT_F_BU, + 14541 => Opcode::NDS_VFWCVT_F_N, + 14542 => Opcode::NDS_VFWCVT_F_NU, + 14543 => Opcode::NDS_VFWCVT_S_BF16, + 14544 => Opcode::NDS_VLE4_V, + 14545 => Opcode::NDS_VLN8_V, + 14546 => Opcode::NDS_VLNU8_V, + 14547 => Opcode::NSARI, + 14548 => Opcode::NSRA, + 14549 => Opcode::NSRAI, + 14550 => Opcode::NSRAR, + 14551 => Opcode::NSRL, + 14552 => Opcode::NSRLI, + 14553 => Opcode::OR, + 14554 => Opcode::ORC_B, + 14555 => Opcode::ORI, + 14556 => Opcode::ORN, + 14557 => Opcode::PAADDU_B, + 14558 => Opcode::PAADDU_DB, + 14559 => Opcode::PAADDU_DH, + 14560 => Opcode::PAADDU_DW, + 14561 => Opcode::PAADDU_H, + 14562 => Opcode::PAADDU_W, + 14563 => Opcode::PAADD_B, + 14564 => Opcode::PAADD_DB, + 14565 => Opcode::PAADD_DH, + 14566 => Opcode::PAADD_DW, + 14567 => Opcode::PAADD_H, + 14568 => Opcode::PAADD_W, + 14569 => Opcode::PAAS_HX, + 14570 => Opcode::PAAS_WX, + 14571 => Opcode::PAAX_DHX, + 14572 => Opcode::PABDSUMAU_B, + 14573 => Opcode::PABDSUMU_B, + 14574 => Opcode::PABDU_B, + 14575 => Opcode::PABDU_DB, + 14576 => Opcode::PABDU_DH, + 14577 => Opcode::PABDU_H, + 14578 => Opcode::PABD_B, + 14579 => Opcode::PABD_DB, + 14580 => Opcode::PABD_DH, + 14581 => Opcode::PABD_H, + 14582 => Opcode::PACK, + 14583 => Opcode::PACKH, + 14584 => Opcode::PACKW, + 14585 => Opcode::PADD_B, + 14586 => Opcode::PADD_BS, + 14587 => Opcode::PADD_DB, + 14588 => Opcode::PADD_DBS, + 14589 => Opcode::PADD_DH, + 14590 => Opcode::PADD_DHS, + 14591 => Opcode::PADD_DW, + 14592 => Opcode::PADD_DWS, + 14593 => Opcode::PADD_H, + 14594 => Opcode::PADD_HS, + 14595 => Opcode::PADD_W, + 14596 => Opcode::PADD_WS, + 14597 => Opcode::PASA_DHX, + 14598 => Opcode::PASA_HX, + 14599 => Opcode::PASA_WX, + 14600 => Opcode::PASUBU_B, + 14601 => Opcode::PASUBU_DB, + 14602 => Opcode::PASUBU_DH, + 14603 => Opcode::PASUBU_DW, + 14604 => Opcode::PASUBU_H, + 14605 => Opcode::PASUBU_W, + 14606 => Opcode::PASUB_B, + 14607 => Opcode::PASUB_DB, + 14608 => Opcode::PASUB_DH, + 14609 => Opcode::PASUB_DW, + 14610 => Opcode::PASUB_H, + 14611 => Opcode::PASUB_W, + 14612 => Opcode::PAS_DHX, + 14613 => Opcode::PAS_HX, + 14614 => Opcode::PAS_WX, + 14615 => Opcode::PLI_B, + 14616 => Opcode::PLI_DB, + 14617 => Opcode::PLI_DH, + 14618 => Opcode::PLI_H, + 14619 => Opcode::PLI_W, + 14620 => Opcode::PLUI_DH, + 14621 => Opcode::PLUI_H, + 14622 => Opcode::PLUI_W, + 14623 => Opcode::PM2ADDASU_H, + 14624 => Opcode::PM2ADDASU_W, + 14625 => Opcode::PM2ADDAU_H, + 14626 => Opcode::PM2ADDAU_W, + 14627 => Opcode::PM2ADDA_H, + 14628 => Opcode::PM2ADDA_HX, + 14629 => Opcode::PM2ADDA_W, + 14630 => Opcode::PM2ADDA_WX, + 14631 => Opcode::PM2ADDSU_H, + 14632 => Opcode::PM2ADDSU_W, + 14633 => Opcode::PM2ADDU_H, + 14634 => Opcode::PM2ADDU_W, + 14635 => Opcode::PM2ADD_H, + 14636 => Opcode::PM2ADD_HX, + 14637 => Opcode::PM2ADD_W, + 14638 => Opcode::PM2ADD_WX, + 14639 => Opcode::PM2SADD_H, + 14640 => Opcode::PM2SADD_HX, + 14641 => Opcode::PM2SUBA_H, + 14642 => Opcode::PM2SUBA_HX, + 14643 => Opcode::PM2SUBA_W, + 14644 => Opcode::PM2SUBA_WX, + 14645 => Opcode::PM2SUB_H, + 14646 => Opcode::PM2SUB_HX, + 14647 => Opcode::PM2SUB_W, + 14648 => Opcode::PM2SUB_WX, + 14649 => Opcode::PM2WADDASU_H, + 14650 => Opcode::PM2WADDAU_H, + 14651 => Opcode::PM2WADDA_H, + 14652 => Opcode::PM2WADDA_HX, + 14653 => Opcode::PM2WADDSU_H, + 14654 => Opcode::PM2WADDU_H, + 14655 => Opcode::PM2WADD_H, + 14656 => Opcode::PM2WADD_HX, + 14657 => Opcode::PM2WSUBA_H, + 14658 => Opcode::PM2WSUBA_HX, + 14659 => Opcode::PM2WSUB_H, + 14660 => Opcode::PM2WSUB_HX, + 14661 => Opcode::PM4ADDASU_B, + 14662 => Opcode::PM4ADDASU_H, + 14663 => Opcode::PM4ADDAU_B, + 14664 => Opcode::PM4ADDAU_H, + 14665 => Opcode::PM4ADDA_B, + 14666 => Opcode::PM4ADDA_H, + 14667 => Opcode::PM4ADDSU_B, + 14668 => Opcode::PM4ADDSU_H, + 14669 => Opcode::PM4ADDU_B, + 14670 => Opcode::PM4ADDU_H, + 14671 => Opcode::PM4ADD_B, + 14672 => Opcode::PM4ADD_H, + 14673 => Opcode::PMACCSU_W_H00, + 14674 => Opcode::PMACCSU_W_H11, + 14675 => Opcode::PMACCU_W_H00, + 14676 => Opcode::PMACCU_W_H01, + 14677 => Opcode::PMACCU_W_H11, + 14678 => Opcode::PMACC_W_H00, + 14679 => Opcode::PMACC_W_H01, + 14680 => Opcode::PMACC_W_H11, + 14681 => Opcode::PMAXU_B, + 14682 => Opcode::PMAXU_DB, + 14683 => Opcode::PMAXU_DH, + 14684 => Opcode::PMAXU_DW, + 14685 => Opcode::PMAXU_H, + 14686 => Opcode::PMAXU_W, + 14687 => Opcode::PMAX_B, + 14688 => Opcode::PMAX_DB, + 14689 => Opcode::PMAX_DH, + 14690 => Opcode::PMAX_DW, + 14691 => Opcode::PMAX_H, + 14692 => Opcode::PMAX_W, + 14693 => Opcode::PMHACCSU_H, + 14694 => Opcode::PMHACCSU_H_B0, + 14695 => Opcode::PMHACCSU_H_B1, + 14696 => Opcode::PMHACCSU_W, + 14697 => Opcode::PMHACCSU_W_H0, + 14698 => Opcode::PMHACCSU_W_H1, + 14699 => Opcode::PMHACCU_H, + 14700 => Opcode::PMHACCU_W, + 14701 => Opcode::PMHACC_H, + 14702 => Opcode::PMHACC_H_B0, + 14703 => Opcode::PMHACC_H_B1, + 14704 => Opcode::PMHACC_W, + 14705 => Opcode::PMHACC_W_H0, + 14706 => Opcode::PMHACC_W_H1, + 14707 => Opcode::PMHRACCSU_H, + 14708 => Opcode::PMHRACCSU_W, + 14709 => Opcode::PMHRACCU_H, + 14710 => Opcode::PMHRACCU_W, + 14711 => Opcode::PMHRACC_H, + 14712 => Opcode::PMHRACC_W, + 14713 => Opcode::PMINU_B, + 14714 => Opcode::PMINU_DB, + 14715 => Opcode::PMINU_DH, + 14716 => Opcode::PMINU_DW, + 14717 => Opcode::PMINU_H, + 14718 => Opcode::PMINU_W, + 14719 => Opcode::PMIN_B, + 14720 => Opcode::PMIN_DB, + 14721 => Opcode::PMIN_DH, + 14722 => Opcode::PMIN_DW, + 14723 => Opcode::PMIN_H, + 14724 => Opcode::PMIN_W, + 14725 => Opcode::PMQ2ADDA_H, + 14726 => Opcode::PMQ2ADDA_W, + 14727 => Opcode::PMQ2ADD_H, + 14728 => Opcode::PMQ2ADD_W, + 14729 => Opcode::PMQACC_W_H00, + 14730 => Opcode::PMQACC_W_H01, + 14731 => Opcode::PMQACC_W_H11, + 14732 => Opcode::PMQR2ADDA_H, + 14733 => Opcode::PMQR2ADDA_W, + 14734 => Opcode::PMQR2ADD_H, + 14735 => Opcode::PMQR2ADD_W, + 14736 => Opcode::PMQRACC_W_H00, + 14737 => Opcode::PMQRACC_W_H01, + 14738 => Opcode::PMQRACC_W_H11, + 14739 => Opcode::PMQRWACC, + 14740 => Opcode::PMQRWACC_H, + 14741 => Opcode::PMQWACC, + 14742 => Opcode::PMQWACC_H, + 14743 => Opcode::PMSEQ_B, + 14744 => Opcode::PMSEQ_DB, + 14745 => Opcode::PMSEQ_DH, + 14746 => Opcode::PMSEQ_DW, + 14747 => Opcode::PMSEQ_H, + 14748 => Opcode::PMSEQ_W, + 14749 => Opcode::PMSLTU_B, + 14750 => Opcode::PMSLTU_DB, + 14751 => Opcode::PMSLTU_DH, + 14752 => Opcode::PMSLTU_DW, + 14753 => Opcode::PMSLTU_H, + 14754 => Opcode::PMSLTU_W, + 14755 => Opcode::PMSLT_B, + 14756 => Opcode::PMSLT_DB, + 14757 => Opcode::PMSLT_DH, + 14758 => Opcode::PMSLT_DW, + 14759 => Opcode::PMSLT_H, + 14760 => Opcode::PMSLT_W, + 14761 => Opcode::PMULHRSU_H, + 14762 => Opcode::PMULHRSU_W, + 14763 => Opcode::PMULHRU_H, + 14764 => Opcode::PMULHRU_W, + 14765 => Opcode::PMULHR_H, + 14766 => Opcode::PMULHR_W, + 14767 => Opcode::PMULHSU_H, + 14768 => Opcode::PMULHSU_H_B0, + 14769 => Opcode::PMULHSU_H_B1, + 14770 => Opcode::PMULHSU_W, + 14771 => Opcode::PMULHSU_W_H0, + 14772 => Opcode::PMULHSU_W_H1, + 14773 => Opcode::PMULHU_H, + 14774 => Opcode::PMULHU_W, + 14775 => Opcode::PMULH_H, + 14776 => Opcode::PMULH_H_B0, + 14777 => Opcode::PMULH_H_B1, + 14778 => Opcode::PMULH_W, + 14779 => Opcode::PMULH_W_H0, + 14780 => Opcode::PMULH_W_H1, + 14781 => Opcode::PMULQR_H, + 14782 => Opcode::PMULQR_W, + 14783 => Opcode::PMULQ_H, + 14784 => Opcode::PMULQ_W, + 14785 => Opcode::PMULSU_H_B00, + 14786 => Opcode::PMULSU_H_B11, + 14787 => Opcode::PMULSU_W_H00, + 14788 => Opcode::PMULSU_W_H11, + 14789 => Opcode::PMULU_H_B00, + 14790 => Opcode::PMULU_H_B01, + 14791 => Opcode::PMULU_H_B11, + 14792 => Opcode::PMULU_W_H00, + 14793 => Opcode::PMULU_W_H01, + 14794 => Opcode::PMULU_W_H11, + 14795 => Opcode::PMUL_H_B00, + 14796 => Opcode::PMUL_H_B01, + 14797 => Opcode::PMUL_H_B11, + 14798 => Opcode::PMUL_W_H00, + 14799 => Opcode::PMUL_W_H01, + 14800 => Opcode::PMUL_W_H11, + 14801 => Opcode::PNCLIPIU_B, + 14802 => Opcode::PNCLIPIU_H, + 14803 => Opcode::PNCLIPI_B, + 14804 => Opcode::PNCLIPI_H, + 14805 => Opcode::PNCLIPRIU_B, + 14806 => Opcode::PNCLIPRIU_H, + 14807 => Opcode::PNCLIPRI_B, + 14808 => Opcode::PNCLIPRI_H, + 14809 => Opcode::PNCLIPRU_BS, + 14810 => Opcode::PNCLIPRU_HS, + 14811 => Opcode::PNCLIPR_BS, + 14812 => Opcode::PNCLIPR_HS, + 14813 => Opcode::PNCLIPU_BS, + 14814 => Opcode::PNCLIPU_HS, + 14815 => Opcode::PNCLIP_BS, + 14816 => Opcode::PNCLIP_HS, + 14817 => Opcode::PNSARI_B, + 14818 => Opcode::PNSARI_H, + 14819 => Opcode::PNSRAI_B, + 14820 => Opcode::PNSRAI_H, + 14821 => Opcode::PNSRAR_BS, + 14822 => Opcode::PNSRAR_HS, + 14823 => Opcode::PNSRA_BS, + 14824 => Opcode::PNSRA_HS, + 14825 => Opcode::PNSRLI_B, + 14826 => Opcode::PNSRLI_H, + 14827 => Opcode::PNSRL_BS, + 14828 => Opcode::PNSRL_HS, + 14829 => Opcode::PPAIREO_B, + 14830 => Opcode::PPAIREO_DB, + 14831 => Opcode::PPAIREO_DH, + 14832 => Opcode::PPAIREO_H, + 14833 => Opcode::PPAIREO_W, + 14834 => Opcode::PPAIRE_B, + 14835 => Opcode::PPAIRE_DB, + 14836 => Opcode::PPAIRE_DH, + 14837 => Opcode::PPAIRE_H, + 14838 => Opcode::PPAIROE_B, + 14839 => Opcode::PPAIROE_DB, + 14840 => Opcode::PPAIROE_DH, + 14841 => Opcode::PPAIROE_H, + 14842 => Opcode::PPAIROE_W, + 14843 => Opcode::PPAIRO_B, + 14844 => Opcode::PPAIRO_DB, + 14845 => Opcode::PPAIRO_DH, + 14846 => Opcode::PPAIRO_H, + 14847 => Opcode::PPAIRO_W, + 14848 => Opcode::PREDSUMU_BS, + 14849 => Opcode::PREDSUMU_DBS, + 14850 => Opcode::PREDSUMU_DHS, + 14851 => Opcode::PREDSUMU_HS, + 14852 => Opcode::PREDSUMU_WS, + 14853 => Opcode::PREDSUM_BS, + 14854 => Opcode::PREDSUM_DBS, + 14855 => Opcode::PREDSUM_DHS, + 14856 => Opcode::PREDSUM_HS, + 14857 => Opcode::PREDSUM_WS, + 14858 => Opcode::PREFETCH_I, + 14859 => Opcode::PREFETCH_R, + 14860 => Opcode::PREFETCH_W, + 14861 => Opcode::PSABS_B, + 14862 => Opcode::PSABS_DB, + 14863 => Opcode::PSABS_DH, + 14864 => Opcode::PSABS_H, + 14865 => Opcode::PSADDU_B, + 14866 => Opcode::PSADDU_DB, + 14867 => Opcode::PSADDU_DH, + 14868 => Opcode::PSADDU_DW, + 14869 => Opcode::PSADDU_H, + 14870 => Opcode::PSADDU_W, + 14871 => Opcode::PSADD_B, + 14872 => Opcode::PSADD_DB, + 14873 => Opcode::PSADD_DH, + 14874 => Opcode::PSADD_DW, + 14875 => Opcode::PSADD_H, + 14876 => Opcode::PSADD_W, + 14877 => Opcode::PSAS_DHX, + 14878 => Opcode::PSAS_HX, + 14879 => Opcode::PSAS_WX, + 14880 => Opcode::PSATI_DH, + 14881 => Opcode::PSATI_DW, + 14882 => Opcode::PSATI_H, + 14883 => Opcode::PSATI_W, + 14884 => Opcode::PSA_DHX, + 14885 => Opcode::PSA_HX, + 14886 => Opcode::PSA_WX, + 14887 => Opcode::PSEXT_DH_B, + 14888 => Opcode::PSEXT_DW_B, + 14889 => Opcode::PSEXT_DW_H, + 14890 => Opcode::PSEXT_H_B, + 14891 => Opcode::PSEXT_W_B, + 14892 => Opcode::PSEXT_W_H, + 14893 => Opcode::PSH1ADD_DH, + 14894 => Opcode::PSH1ADD_DW, + 14895 => Opcode::PSH1ADD_H, + 14896 => Opcode::PSH1ADD_W, + 14897 => Opcode::PSLLI_B, + 14898 => Opcode::PSLLI_DB, + 14899 => Opcode::PSLLI_DH, + 14900 => Opcode::PSLLI_DW, + 14901 => Opcode::PSLLI_H, + 14902 => Opcode::PSLLI_W, + 14903 => Opcode::PSLL_BS, + 14904 => Opcode::PSLL_DBS, + 14905 => Opcode::PSLL_DHS, + 14906 => Opcode::PSLL_DWS, + 14907 => Opcode::PSLL_HS, + 14908 => Opcode::PSLL_WS, + 14909 => Opcode::PSRAI_B, + 14910 => Opcode::PSRAI_DB, + 14911 => Opcode::PSRAI_DH, + 14912 => Opcode::PSRAI_DW, + 14913 => Opcode::PSRAI_H, + 14914 => Opcode::PSRAI_W, + 14915 => Opcode::PSRARI_DH, + 14916 => Opcode::PSRARI_DW, + 14917 => Opcode::PSRARI_H, + 14918 => Opcode::PSRARI_W, + 14919 => Opcode::PSRA_BS, + 14920 => Opcode::PSRA_DBS, + 14921 => Opcode::PSRA_DHS, + 14922 => Opcode::PSRA_DWS, + 14923 => Opcode::PSRA_HS, + 14924 => Opcode::PSRA_WS, + 14925 => Opcode::PSRLI_B, + 14926 => Opcode::PSRLI_DB, + 14927 => Opcode::PSRLI_DH, + 14928 => Opcode::PSRLI_DW, + 14929 => Opcode::PSRLI_H, + 14930 => Opcode::PSRLI_W, + 14931 => Opcode::PSRL_BS, + 14932 => Opcode::PSRL_DBS, + 14933 => Opcode::PSRL_DHS, + 14934 => Opcode::PSRL_DWS, + 14935 => Opcode::PSRL_HS, + 14936 => Opcode::PSRL_WS, + 14937 => Opcode::PSSA_DHX, + 14938 => Opcode::PSSA_HX, + 14939 => Opcode::PSSA_WX, + 14940 => Opcode::PSSH1SADD_DH, + 14941 => Opcode::PSSH1SADD_DW, + 14942 => Opcode::PSSH1SADD_H, + 14943 => Opcode::PSSH1SADD_W, + 14944 => Opcode::PSSHAR_DHS, + 14945 => Opcode::PSSHAR_DWS, + 14946 => Opcode::PSSHAR_HS, + 14947 => Opcode::PSSHAR_WS, + 14948 => Opcode::PSSHA_DHS, + 14949 => Opcode::PSSHA_DWS, + 14950 => Opcode::PSSHA_HS, + 14951 => Opcode::PSSHA_WS, + 14952 => Opcode::PSSLAI_DH, + 14953 => Opcode::PSSLAI_DW, + 14954 => Opcode::PSSLAI_H, + 14955 => Opcode::PSSLAI_W, + 14956 => Opcode::PSSUBU_B, + 14957 => Opcode::PSSUBU_DB, + 14958 => Opcode::PSSUBU_DH, + 14959 => Opcode::PSSUBU_DW, + 14960 => Opcode::PSSUBU_H, + 14961 => Opcode::PSSUBU_W, + 14962 => Opcode::PSSUB_B, + 14963 => Opcode::PSSUB_DB, + 14964 => Opcode::PSSUB_DH, + 14965 => Opcode::PSSUB_DW, + 14966 => Opcode::PSSUB_H, + 14967 => Opcode::PSSUB_W, + 14968 => Opcode::PSUB_B, + 14969 => Opcode::PSUB_DB, + 14970 => Opcode::PSUB_DH, + 14971 => Opcode::PSUB_DW, + 14972 => Opcode::PSUB_H, + 14973 => Opcode::PSUB_W, + 14974 => Opcode::PUSATI_DH, + 14975 => Opcode::PUSATI_DW, + 14976 => Opcode::PUSATI_H, + 14977 => Opcode::PUSATI_W, + 14978 => Opcode::PWADDAU_B, + 14979 => Opcode::PWADDAU_H, + 14980 => Opcode::PWADDA_B, + 14981 => Opcode::PWADDA_H, + 14982 => Opcode::PWADDU_B, + 14983 => Opcode::PWADDU_H, + 14984 => Opcode::PWADD_B, + 14985 => Opcode::PWADD_H, + 14986 => Opcode::PWMACCSU_H, + 14987 => Opcode::PWMACCU_H, + 14988 => Opcode::PWMACC_H, + 14989 => Opcode::PWMULSU_B, + 14990 => Opcode::PWMULSU_H, + 14991 => Opcode::PWMULU_B, + 14992 => Opcode::PWMULU_H, + 14993 => Opcode::PWMUL_B, + 14994 => Opcode::PWMUL_H, + 14995 => Opcode::PWSLAI_B, + 14996 => Opcode::PWSLAI_H, + 14997 => Opcode::PWSLA_BS, + 14998 => Opcode::PWSLA_HS, + 14999 => Opcode::PWSLLI_B, + 15000 => Opcode::PWSLLI_H, + 15001 => Opcode::PWSLL_BS, + 15002 => Opcode::PWSLL_HS, + 15003 => Opcode::PWSUBAU_B, + 15004 => Opcode::PWSUBAU_H, + 15005 => Opcode::PWSUBA_B, + 15006 => Opcode::PWSUBA_H, + 15007 => Opcode::PWSUBU_B, + 15008 => Opcode::PWSUBU_H, + 15009 => Opcode::PWSUB_B, + 15010 => Opcode::PWSUB_H, + 15011 => Opcode::QC_ADDSAT, + 15012 => Opcode::QC_ADDUSAT, + 15013 => Opcode::QC_BEQI, + 15014 => Opcode::QC_BGEI, + 15015 => Opcode::QC_BGEUI, + 15016 => Opcode::QC_BLTI, + 15017 => Opcode::QC_BLTUI, + 15018 => Opcode::QC_BNEI, + 15019 => Opcode::QC_BREV32, + 15020 => Opcode::QC_CLO, + 15021 => Opcode::QC_CLRINTI, + 15022 => Opcode::QC_CM_MVA01S, + 15023 => Opcode::QC_CM_MVSA01, + 15024 => Opcode::QC_CM_POP, + 15025 => Opcode::QC_CM_POPRET, + 15026 => Opcode::QC_CM_POPRETZ, + 15027 => Opcode::QC_CM_PUSH, + 15028 => Opcode::QC_CM_PUSHFP, + 15029 => Opcode::QC_COMPRESS2, + 15030 => Opcode::QC_COMPRESS3, + 15031 => Opcode::QC_CSRRWR, + 15032 => Opcode::QC_CSRRWRI, + 15033 => Opcode::QC_CTO, + 15034 => Opcode::QC_C_BEXTI, + 15035 => Opcode::QC_C_BSETI, + 15036 => Opcode::QC_C_CLRINT, + 15037 => Opcode::QC_C_DI, + 15038 => Opcode::QC_C_DIR, + 15039 => Opcode::QC_C_EI, + 15040 => Opcode::QC_C_EIR, + 15041 => Opcode::QC_C_EXTU, + 15042 => Opcode::QC_C_MIENTER, + 15043 => Opcode::QC_C_MIENTER_NEST, + 15044 => Opcode::QC_C_MILEAVERET, + 15045 => Opcode::QC_C_MNRET, + 15046 => Opcode::QC_C_MRET, + 15047 => Opcode::QC_C_MULIADD, + 15048 => Opcode::QC_C_MVEQZ, + 15049 => Opcode::QC_C_SETINT, + 15050 => Opcode::QC_C_SYNC, + 15051 => Opcode::QC_C_SYNCR, + 15052 => Opcode::QC_C_SYNCWF, + 15053 => Opcode::QC_C_SYNCWL, + 15054 => Opcode::QC_EXPAND2, + 15055 => Opcode::QC_EXPAND3, + 15056 => Opcode::QC_EXT, + 15057 => Opcode::QC_EXTD, + 15058 => Opcode::QC_EXTDPR, + 15059 => Opcode::QC_EXTDPRH, + 15060 => Opcode::QC_EXTDR, + 15061 => Opcode::QC_EXTDU, + 15062 => Opcode::QC_EXTDUPR, + 15063 => Opcode::QC_EXTDUPRH, + 15064 => Opcode::QC_EXTDUR, + 15065 => Opcode::QC_EXTU, + 15066 => Opcode::QC_E_ADDAI, + 15067 => Opcode::QC_E_ADDI, + 15068 => Opcode::QC_E_ANDAI, + 15069 => Opcode::QC_E_ANDI, + 15070 => Opcode::QC_E_BEQI, + 15071 => Opcode::QC_E_BGEI, + 15072 => Opcode::QC_E_BGEUI, + 15073 => Opcode::QC_E_BLTI, + 15074 => Opcode::QC_E_BLTUI, + 15075 => Opcode::QC_E_BNEI, + 15076 => Opcode::QC_E_J, + 15077 => Opcode::QC_E_JAL, + 15078 => Opcode::QC_E_LB, + 15079 => Opcode::QC_E_LBU, + 15080 => Opcode::QC_E_LH, + 15081 => Opcode::QC_E_LHU, + 15082 => Opcode::QC_E_LI, + 15083 => Opcode::QC_E_LW, + 15084 => Opcode::QC_E_ORAI, + 15085 => Opcode::QC_E_ORI, + 15086 => Opcode::QC_E_SB, + 15087 => Opcode::QC_E_SH, + 15088 => Opcode::QC_E_SW, + 15089 => Opcode::QC_E_XORAI, + 15090 => Opcode::QC_E_XORI, + 15091 => Opcode::QC_INSB, + 15092 => Opcode::QC_INSBH, + 15093 => Opcode::QC_INSBHR, + 15094 => Opcode::QC_INSBI, + 15095 => Opcode::QC_INSBPR, + 15096 => Opcode::QC_INSBPRH, + 15097 => Opcode::QC_INSBR, + 15098 => Opcode::QC_INSBRI, + 15099 => Opcode::QC_INW, + 15100 => Opcode::QC_LI, + 15101 => Opcode::QC_LIEQ, + 15102 => Opcode::QC_LIEQI, + 15103 => Opcode::QC_LIGE, + 15104 => Opcode::QC_LIGEI, + 15105 => Opcode::QC_LIGEU, + 15106 => Opcode::QC_LIGEUI, + 15107 => Opcode::QC_LILT, + 15108 => Opcode::QC_LILTI, + 15109 => Opcode::QC_LILTU, + 15110 => Opcode::QC_LILTUI, + 15111 => Opcode::QC_LINE, + 15112 => Opcode::QC_LINEI, + 15113 => Opcode::QC_LRB, + 15114 => Opcode::QC_LRBU, + 15115 => Opcode::QC_LRH, + 15116 => Opcode::QC_LRHU, + 15117 => Opcode::QC_LRW, + 15118 => Opcode::QC_LWM, + 15119 => Opcode::QC_LWMI, + 15120 => Opcode::QC_MULIADD, + 15121 => Opcode::QC_MVEQ, + 15122 => Opcode::QC_MVEQI, + 15123 => Opcode::QC_MVGE, + 15124 => Opcode::QC_MVGEI, + 15125 => Opcode::QC_MVGEU, + 15126 => Opcode::QC_MVGEUI, + 15127 => Opcode::QC_MVLT, + 15128 => Opcode::QC_MVLTI, + 15129 => Opcode::QC_MVLTU, + 15130 => Opcode::QC_MVLTUI, + 15131 => Opcode::QC_MVNE, + 15132 => Opcode::QC_MVNEI, + 15133 => Opcode::QC_NORM, + 15134 => Opcode::QC_NORMEU, + 15135 => Opcode::QC_NORMU, + 15136 => Opcode::QC_OUTW, + 15137 => Opcode::QC_PPUTCI, + 15138 => Opcode::QC_SELECTEQI, + 15139 => Opcode::QC_SELECTIEQ, + 15140 => Opcode::QC_SELECTIEQI, + 15141 => Opcode::QC_SELECTIIEQ, + 15142 => Opcode::QC_SELECTIINE, + 15143 => Opcode::QC_SELECTINE, + 15144 => Opcode::QC_SELECTINEI, + 15145 => Opcode::QC_SELECTNEI, + 15146 => Opcode::QC_SETINTI, + 15147 => Opcode::QC_SETWM, + 15148 => Opcode::QC_SETWMI, + 15149 => Opcode::QC_SHLADD, + 15150 => Opcode::QC_SHLSAT, + 15151 => Opcode::QC_SHLUSAT, + 15152 => Opcode::QC_SRB, + 15153 => Opcode::QC_SRH, + 15154 => Opcode::QC_SRW, + 15155 => Opcode::QC_SUBSAT, + 15156 => Opcode::QC_SUBUSAT, + 15157 => Opcode::QC_SWM, + 15158 => Opcode::QC_SWMI, + 15159 => Opcode::QC_SYNC, + 15160 => Opcode::QC_SYNCR, + 15161 => Opcode::QC_SYNCWF, + 15162 => Opcode::QC_SYNCWL, + 15163 => Opcode::QC_WRAP, + 15164 => Opcode::QC_WRAPI, + 15165 => Opcode::QK_C_LBU, + 15166 => Opcode::QK_C_LBUSP, + 15167 => Opcode::QK_C_LHU, + 15168 => Opcode::QK_C_LHUSP, + 15169 => Opcode::QK_C_SB, + 15170 => Opcode::QK_C_SBSP, + 15171 => Opcode::QK_C_SH, + 15172 => Opcode::QK_C_SHSP, + 15173 => Opcode::REM, + 15174 => Opcode::REMU, + 15175 => Opcode::REMUW, + 15176 => Opcode::REMW, + 15177 => Opcode::REV16, + 15178 => Opcode::REV8_RV32, + 15179 => Opcode::REV8_RV64, + 15180 => Opcode::REV_RV32, + 15181 => Opcode::REV_RV64, + 15182 => Opcode::RI_VEXTRACT, + 15183 => Opcode::RI_VINSERT, + 15184 => Opcode::RI_VUNZIP2A_VV, + 15185 => Opcode::RI_VUNZIP2B_VV, + 15186 => Opcode::RI_VZERO, + 15187 => Opcode::RI_VZIP2A_VV, + 15188 => Opcode::RI_VZIP2B_VV, + 15189 => Opcode::RI_VZIPEVEN_VV, + 15190 => Opcode::RI_VZIPODD_VV, + 15191 => Opcode::ROL, + 15192 => Opcode::ROLW, + 15193 => Opcode::ROR, + 15194 => Opcode::RORI, + 15195 => Opcode::RORIW, + 15196 => Opcode::RORW, + 15197 => Opcode::SADD, + 15198 => Opcode::SADDU, + 15199 => Opcode::SATI_RV32, + 15200 => Opcode::SATI_RV64, + 15201 => Opcode::SB, + 15202 => Opcode::SB_AQRL, + 15203 => Opcode::SB_RL, + 15204 => Opcode::SCTRCLR, + 15205 => Opcode::SC_D, + 15206 => Opcode::SC_D_AQ, + 15207 => Opcode::SC_D_AQRL, + 15208 => Opcode::SC_D_RL, + 15209 => Opcode::SC_W, + 15210 => Opcode::SC_W_AQ, + 15211 => Opcode::SC_W_AQRL, + 15212 => Opcode::SC_W_RL, + 15213 => Opcode::SD, + 15214 => Opcode::SD_AQRL, + 15215 => Opcode::SD_RL, + 15216 => Opcode::SD_RV32, + 15217 => Opcode::SEXT_B, + 15218 => Opcode::SEXT_H, + 15219 => Opcode::SFENCE_INVAL_IR, + 15220 => Opcode::SFENCE_VMA, + 15221 => Opcode::SFENCE_W_INVAL, + 15222 => Opcode::SF_CDISCARD_D_L1, + 15223 => Opcode::SF_CEASE, + 15224 => Opcode::SF_CFLUSH_D_L1, + 15225 => Opcode::SF_MM_E4M3_E4M3, + 15226 => Opcode::SF_MM_E4M3_E5M2, + 15227 => Opcode::SF_MM_E5M2_E4M3, + 15228 => Opcode::SF_MM_E5M2_E5M2, + 15229 => Opcode::SF_MM_F_F, + 15230 => Opcode::SF_MM_S_S, + 15231 => Opcode::SF_MM_S_U, + 15232 => Opcode::SF_MM_U_S, + 15233 => Opcode::SF_MM_U_U, + 15234 => Opcode::SF_VC_FV, + 15235 => Opcode::SF_VC_FVV, + 15236 => Opcode::SF_VC_FVW, + 15237 => Opcode::SF_VC_I, + 15238 => Opcode::SF_VC_IV, + 15239 => Opcode::SF_VC_IVV, + 15240 => Opcode::SF_VC_IVW, + 15241 => Opcode::SF_VC_VV, + 15242 => Opcode::SF_VC_VVV, + 15243 => Opcode::SF_VC_VVW, + 15244 => Opcode::SF_VC_V_FV, + 15245 => Opcode::SF_VC_V_FVV, + 15246 => Opcode::SF_VC_V_FVW, + 15247 => Opcode::SF_VC_V_I, + 15248 => Opcode::SF_VC_V_IV, + 15249 => Opcode::SF_VC_V_IVV, + 15250 => Opcode::SF_VC_V_IVW, + 15251 => Opcode::SF_VC_V_VV, + 15252 => Opcode::SF_VC_V_VVV, + 15253 => Opcode::SF_VC_V_VVW, + 15254 => Opcode::SF_VC_V_X, + 15255 => Opcode::SF_VC_V_XV, + 15256 => Opcode::SF_VC_V_XVV, + 15257 => Opcode::SF_VC_V_XVW, + 15258 => Opcode::SF_VC_X, + 15259 => Opcode::SF_VC_XV, + 15260 => Opcode::SF_VC_XVV, + 15261 => Opcode::SF_VC_XVW, + 15262 => Opcode::SF_VFEXPA_V, + 15263 => Opcode::SF_VFEXP_V, + 15264 => Opcode::SF_VFNRCLIP_XU_F_QF, + 15265 => Opcode::SF_VFNRCLIP_X_F_QF, + 15266 => Opcode::SF_VFWMACC_4x4x4, + 15267 => Opcode::SF_VLTE16, + 15268 => Opcode::SF_VLTE32, + 15269 => Opcode::SF_VLTE64, + 15270 => Opcode::SF_VLTE8, + 15271 => Opcode::SF_VQMACCSU_2x8x2, + 15272 => Opcode::SF_VQMACCSU_4x8x4, + 15273 => Opcode::SF_VQMACCUS_2x8x2, + 15274 => Opcode::SF_VQMACCUS_4x8x4, + 15275 => Opcode::SF_VQMACCU_2x8x2, + 15276 => Opcode::SF_VQMACCU_4x8x4, + 15277 => Opcode::SF_VQMACC_2x8x2, + 15278 => Opcode::SF_VQMACC_4x8x4, + 15279 => Opcode::SF_VSETTK, + 15280 => Opcode::SF_VSETTM, + 15281 => Opcode::SF_VSETTN, + 15282 => Opcode::SF_VSTE16, + 15283 => Opcode::SF_VSTE32, + 15284 => Opcode::SF_VSTE64, + 15285 => Opcode::SF_VSTE8, + 15286 => Opcode::SF_VTDISCARD, + 15287 => Opcode::SF_VTMV_T_V, + 15288 => Opcode::SF_VTMV_V_T, + 15289 => Opcode::SF_VTZERO_T, + 15290 => Opcode::SH, + 15291 => Opcode::SH1ADD, + 15292 => Opcode::SH1ADD_UW, + 15293 => Opcode::SH2ADD, + 15294 => Opcode::SH2ADD_UW, + 15295 => Opcode::SH3ADD, + 15296 => Opcode::SH3ADD_UW, + 15297 => Opcode::SHA, + 15298 => Opcode::SHA256SIG0, + 15299 => Opcode::SHA256SIG1, + 15300 => Opcode::SHA256SUM0, + 15301 => Opcode::SHA256SUM1, + 15302 => Opcode::SHA512SIG0, + 15303 => Opcode::SHA512SIG0H, + 15304 => Opcode::SHA512SIG0L, + 15305 => Opcode::SHA512SIG1, + 15306 => Opcode::SHA512SIG1H, + 15307 => Opcode::SHA512SIG1L, + 15308 => Opcode::SHA512SUM0, + 15309 => Opcode::SHA512SUM0R, + 15310 => Opcode::SHA512SUM1, + 15311 => Opcode::SHA512SUM1R, + 15312 => Opcode::SHAR, + 15313 => Opcode::SH_AQRL, + 15314 => Opcode::SH_INX, + 15315 => Opcode::SH_RL, + 15316 => Opcode::SINVAL_VMA, + 15317 => Opcode::SLL, + 15318 => Opcode::SLLI, + 15319 => Opcode::SLLIW, + 15320 => Opcode::SLLI_UW, + 15321 => Opcode::SLLW, + 15322 => Opcode::SLT, + 15323 => Opcode::SLTI, + 15324 => Opcode::SLTIU, + 15325 => Opcode::SLTU, + 15326 => Opcode::SLX, + 15327 => Opcode::SM3P0, + 15328 => Opcode::SM3P1, + 15329 => Opcode::SM4ED, + 15330 => Opcode::SM4KS, + 15331 => Opcode::SMT_VMADOT, + 15332 => Opcode::SMT_VMADOT1, + 15333 => Opcode::SMT_VMADOT1SU, + 15334 => Opcode::SMT_VMADOT1U, + 15335 => Opcode::SMT_VMADOT1US, + 15336 => Opcode::SMT_VMADOT2, + 15337 => Opcode::SMT_VMADOT2SU, + 15338 => Opcode::SMT_VMADOT2U, + 15339 => Opcode::SMT_VMADOT2US, + 15340 => Opcode::SMT_VMADOT3, + 15341 => Opcode::SMT_VMADOT3SU, + 15342 => Opcode::SMT_VMADOT3U, + 15343 => Opcode::SMT_VMADOT3US, + 15344 => Opcode::SMT_VMADOTSU, + 15345 => Opcode::SMT_VMADOTU, + 15346 => Opcode::SMT_VMADOTUS, + 15347 => Opcode::SRA, + 15348 => Opcode::SRAI, + 15349 => Opcode::SRAIW, + 15350 => Opcode::SRARI_RV32, + 15351 => Opcode::SRARI_RV64, + 15352 => Opcode::SRAW, + 15353 => Opcode::SRET, + 15354 => Opcode::SRL, + 15355 => Opcode::SRLI, + 15356 => Opcode::SRLIW, + 15357 => Opcode::SRLW, + 15358 => Opcode::SRX, + 15359 => Opcode::SSAMOSWAP_D, + 15360 => Opcode::SSAMOSWAP_D_AQ, + 15361 => Opcode::SSAMOSWAP_D_AQRL, + 15362 => Opcode::SSAMOSWAP_D_RL, + 15363 => Opcode::SSAMOSWAP_W, + 15364 => Opcode::SSAMOSWAP_W_AQ, + 15365 => Opcode::SSAMOSWAP_W_AQRL, + 15366 => Opcode::SSAMOSWAP_W_RL, + 15367 => Opcode::SSH1SADD, + 15368 => Opcode::SSHA, + 15369 => Opcode::SSHAR, + 15370 => Opcode::SSLAI, + 15371 => Opcode::SSPOPCHK, + 15372 => Opcode::SSPUSH, + 15373 => Opcode::SSRDP, + 15374 => Opcode::SSUB, + 15375 => Opcode::SSUBU, + 15376 => Opcode::SUB, + 15377 => Opcode::SUBD, + 15378 => Opcode::SUBW, + 15379 => Opcode::SW, + 15380 => Opcode::SW_AQRL, + 15381 => Opcode::SW_INX, + 15382 => Opcode::SW_RL, + 15383 => Opcode::TH_ADDSL, + 15384 => Opcode::TH_DCACHE_CALL, + 15385 => Opcode::TH_DCACHE_CIALL, + 15386 => Opcode::TH_DCACHE_CIPA, + 15387 => Opcode::TH_DCACHE_CISW, + 15388 => Opcode::TH_DCACHE_CIVA, + 15389 => Opcode::TH_DCACHE_CPA, + 15390 => Opcode::TH_DCACHE_CPAL1, + 15391 => Opcode::TH_DCACHE_CSW, + 15392 => Opcode::TH_DCACHE_CVA, + 15393 => Opcode::TH_DCACHE_CVAL1, + 15394 => Opcode::TH_DCACHE_IALL, + 15395 => Opcode::TH_DCACHE_IPA, + 15396 => Opcode::TH_DCACHE_ISW, + 15397 => Opcode::TH_DCACHE_IVA, + 15398 => Opcode::TH_EXT, + 15399 => Opcode::TH_EXTU, + 15400 => Opcode::TH_FF0, + 15401 => Opcode::TH_FF1, + 15402 => Opcode::TH_FLRD, + 15403 => Opcode::TH_FLRW, + 15404 => Opcode::TH_FLURD, + 15405 => Opcode::TH_FLURW, + 15406 => Opcode::TH_FSRD, + 15407 => Opcode::TH_FSRW, + 15408 => Opcode::TH_FSURD, + 15409 => Opcode::TH_FSURW, + 15410 => Opcode::TH_ICACHE_IALL, + 15411 => Opcode::TH_ICACHE_IALLS, + 15412 => Opcode::TH_ICACHE_IPA, + 15413 => Opcode::TH_ICACHE_IVA, + 15414 => Opcode::TH_L2CACHE_CALL, + 15415 => Opcode::TH_L2CACHE_CIALL, + 15416 => Opcode::TH_L2CACHE_IALL, + 15417 => Opcode::TH_LBIA, + 15418 => Opcode::TH_LBIB, + 15419 => Opcode::TH_LBUIA, + 15420 => Opcode::TH_LBUIB, + 15421 => Opcode::TH_LDD, + 15422 => Opcode::TH_LDIA, + 15423 => Opcode::TH_LDIB, + 15424 => Opcode::TH_LHIA, + 15425 => Opcode::TH_LHIB, + 15426 => Opcode::TH_LHUIA, + 15427 => Opcode::TH_LHUIB, + 15428 => Opcode::TH_LRB, + 15429 => Opcode::TH_LRBU, + 15430 => Opcode::TH_LRD, + 15431 => Opcode::TH_LRH, + 15432 => Opcode::TH_LRHU, + 15433 => Opcode::TH_LRW, + 15434 => Opcode::TH_LRWU, + 15435 => Opcode::TH_LURB, + 15436 => Opcode::TH_LURBU, + 15437 => Opcode::TH_LURD, + 15438 => Opcode::TH_LURH, + 15439 => Opcode::TH_LURHU, + 15440 => Opcode::TH_LURW, + 15441 => Opcode::TH_LURWU, + 15442 => Opcode::TH_LWD, + 15443 => Opcode::TH_LWIA, + 15444 => Opcode::TH_LWIB, + 15445 => Opcode::TH_LWUD, + 15446 => Opcode::TH_LWUIA, + 15447 => Opcode::TH_LWUIB, + 15448 => Opcode::TH_MULA, + 15449 => Opcode::TH_MULAH, + 15450 => Opcode::TH_MULAW, + 15451 => Opcode::TH_MULS, + 15452 => Opcode::TH_MULSH, + 15453 => Opcode::TH_MULSW, + 15454 => Opcode::TH_MVEQZ, + 15455 => Opcode::TH_MVNEZ, + 15456 => Opcode::TH_REV, + 15457 => Opcode::TH_REVW, + 15458 => Opcode::TH_SBIA, + 15459 => Opcode::TH_SBIB, + 15460 => Opcode::TH_SDD, + 15461 => Opcode::TH_SDIA, + 15462 => Opcode::TH_SDIB, + 15463 => Opcode::TH_SFENCE_VMAS, + 15464 => Opcode::TH_SHIA, + 15465 => Opcode::TH_SHIB, + 15466 => Opcode::TH_SRB, + 15467 => Opcode::TH_SRD, + 15468 => Opcode::TH_SRH, + 15469 => Opcode::TH_SRRI, + 15470 => Opcode::TH_SRRIW, + 15471 => Opcode::TH_SRW, + 15472 => Opcode::TH_SURB, + 15473 => Opcode::TH_SURD, + 15474 => Opcode::TH_SURH, + 15475 => Opcode::TH_SURW, + 15476 => Opcode::TH_SWD, + 15477 => Opcode::TH_SWIA, + 15478 => Opcode::TH_SWIB, + 15479 => Opcode::TH_SYNC, + 15480 => Opcode::TH_SYNC_I, + 15481 => Opcode::TH_SYNC_IS, + 15482 => Opcode::TH_SYNC_S, + 15483 => Opcode::TH_TST, + 15484 => Opcode::TH_TSTNBZ, + 15485 => Opcode::TH_VMAQASU_VV, + 15486 => Opcode::TH_VMAQASU_VX, + 15487 => Opcode::TH_VMAQAUS_VX, + 15488 => Opcode::TH_VMAQAU_VV, + 15489 => Opcode::TH_VMAQAU_VX, + 15490 => Opcode::TH_VMAQA_VV, + 15491 => Opcode::TH_VMAQA_VX, + 15492 => Opcode::UNIMP, + 15493 => Opcode::UNZIP16HP, + 15494 => Opcode::UNZIP16P, + 15495 => Opcode::UNZIP8HP, + 15496 => Opcode::UNZIP8P, + 15497 => Opcode::UNZIP_RV32, + 15498 => Opcode::USATI_RV32, + 15499 => Opcode::USATI_RV64, + 15500 => Opcode::VAADDU_VV, + 15501 => Opcode::VAADDU_VX, + 15502 => Opcode::VAADD_VV, + 15503 => Opcode::VAADD_VX, + 15504 => Opcode::VADC_VIM, + 15505 => Opcode::VADC_VVM, + 15506 => Opcode::VADC_VXM, + 15507 => Opcode::VADD_VI, + 15508 => Opcode::VADD_VV, + 15509 => Opcode::VADD_VX, + 15510 => Opcode::VAESDF_VS, + 15511 => Opcode::VAESDF_VV, + 15512 => Opcode::VAESDM_VS, + 15513 => Opcode::VAESDM_VV, + 15514 => Opcode::VAESEF_VS, + 15515 => Opcode::VAESEF_VV, + 15516 => Opcode::VAESEM_VS, + 15517 => Opcode::VAESEM_VV, + 15518 => Opcode::VAESKF1_VI, + 15519 => Opcode::VAESKF2_VI, + 15520 => Opcode::VAESZ_VS, + 15521 => Opcode::VANDN_VV, + 15522 => Opcode::VANDN_VX, + 15523 => Opcode::VAND_VI, + 15524 => Opcode::VAND_VV, + 15525 => Opcode::VAND_VX, + 15526 => Opcode::VASUBU_VV, + 15527 => Opcode::VASUBU_VX, + 15528 => Opcode::VASUB_VV, + 15529 => Opcode::VASUB_VX, + 15530 => Opcode::VBREV8_V, + 15531 => Opcode::VBREV_V, + 15532 => Opcode::VCLMULH_VV, + 15533 => Opcode::VCLMULH_VX, + 15534 => Opcode::VCLMUL_VV, + 15535 => Opcode::VCLMUL_VX, + 15536 => Opcode::VCLZ_V, + 15537 => Opcode::VCOMPRESS_VM, + 15538 => Opcode::VCPOP_M, + 15539 => Opcode::VCPOP_V, + 15540 => Opcode::VCTZ_V, + 15541 => Opcode::VDIVU_VV, + 15542 => Opcode::VDIVU_VX, + 15543 => Opcode::VDIV_VV, + 15544 => Opcode::VDIV_VX, + 15545 => Opcode::VFADD_VF, + 15546 => Opcode::VFADD_VV, + 15547 => Opcode::VFCLASS_V, + 15548 => Opcode::VFCVT_F_XU_V, + 15549 => Opcode::VFCVT_F_X_V, + 15550 => Opcode::VFCVT_RTZ_XU_F_V, + 15551 => Opcode::VFCVT_RTZ_X_F_V, + 15552 => Opcode::VFCVT_XU_F_V, + 15553 => Opcode::VFCVT_X_F_V, + 15554 => Opcode::VFDIV_VF, + 15555 => Opcode::VFDIV_VV, + 15556 => Opcode::VFIRST_M, + 15557 => Opcode::VFMACC_VF, + 15558 => Opcode::VFMACC_VV, + 15559 => Opcode::VFMADD_VF, + 15560 => Opcode::VFMADD_VV, + 15561 => Opcode::VFMAX_VF, + 15562 => Opcode::VFMAX_VV, + 15563 => Opcode::VFMERGE_VFM, + 15564 => Opcode::VFMIN_VF, + 15565 => Opcode::VFMIN_VV, + 15566 => Opcode::VFMSAC_VF, + 15567 => Opcode::VFMSAC_VV, + 15568 => Opcode::VFMSUB_VF, + 15569 => Opcode::VFMSUB_VV, + 15570 => Opcode::VFMUL_VF, + 15571 => Opcode::VFMUL_VV, + 15572 => Opcode::VFMV_F_S, + 15573 => Opcode::VFMV_S_F, + 15574 => Opcode::VFMV_V_F, + 15575 => Opcode::VFNCVTBF16_F_F_W, + 15576 => Opcode::VFNCVTBF16_SAT_F_F_W, + 15577 => Opcode::VFNCVT_F_F_Q, + 15578 => Opcode::VFNCVT_F_F_W, + 15579 => Opcode::VFNCVT_F_XU_W, + 15580 => Opcode::VFNCVT_F_X_W, + 15581 => Opcode::VFNCVT_ROD_F_F_W, + 15582 => Opcode::VFNCVT_RTZ_XU_F_W, + 15583 => Opcode::VFNCVT_RTZ_X_F_W, + 15584 => Opcode::VFNCVT_SAT_F_F_Q, + 15585 => Opcode::VFNCVT_XU_F_W, + 15586 => Opcode::VFNCVT_X_F_W, + 15587 => Opcode::VFNMACC_VF, + 15588 => Opcode::VFNMACC_VV, + 15589 => Opcode::VFNMADD_VF, + 15590 => Opcode::VFNMADD_VV, + 15591 => Opcode::VFNMSAC_VF, + 15592 => Opcode::VFNMSAC_VV, + 15593 => Opcode::VFNMSUB_VF, + 15594 => Opcode::VFNMSUB_VV, + 15595 => Opcode::VFRDIV_VF, + 15596 => Opcode::VFREC7_V, + 15597 => Opcode::VFREDMAX_VS, + 15598 => Opcode::VFREDMIN_VS, + 15599 => Opcode::VFREDOSUM_VS, + 15600 => Opcode::VFREDUSUM_VS, + 15601 => Opcode::VFRSQRT7_V, + 15602 => Opcode::VFRSUB_VF, + 15603 => Opcode::VFSGNJN_VF, + 15604 => Opcode::VFSGNJN_VV, + 15605 => Opcode::VFSGNJX_VF, + 15606 => Opcode::VFSGNJX_VV, + 15607 => Opcode::VFSGNJ_VF, + 15608 => Opcode::VFSGNJ_VV, + 15609 => Opcode::VFSLIDE1DOWN_VF, + 15610 => Opcode::VFSLIDE1UP_VF, + 15611 => Opcode::VFSQRT_V, + 15612 => Opcode::VFSUB_VF, + 15613 => Opcode::VFSUB_VV, + 15614 => Opcode::VFWADD_VF, + 15615 => Opcode::VFWADD_VV, + 15616 => Opcode::VFWADD_WF, + 15617 => Opcode::VFWADD_WV, + 15618 => Opcode::VFWCVTBF16_F_F_V, + 15619 => Opcode::VFWCVT_F_F_V, + 15620 => Opcode::VFWCVT_F_XU_V, + 15621 => Opcode::VFWCVT_F_X_V, + 15622 => Opcode::VFWCVT_RTZ_XU_F_V, + 15623 => Opcode::VFWCVT_RTZ_X_F_V, + 15624 => Opcode::VFWCVT_XU_F_V, + 15625 => Opcode::VFWCVT_X_F_V, + 15626 => Opcode::VFWMACCBF16_VF, + 15627 => Opcode::VFWMACCBF16_VV, + 15628 => Opcode::VFWMACC_VF, + 15629 => Opcode::VFWMACC_VV, + 15630 => Opcode::VFWMSAC_VF, + 15631 => Opcode::VFWMSAC_VV, + 15632 => Opcode::VFWMUL_VF, + 15633 => Opcode::VFWMUL_VV, + 15634 => Opcode::VFWNMACC_VF, + 15635 => Opcode::VFWNMACC_VV, + 15636 => Opcode::VFWNMSAC_VF, + 15637 => Opcode::VFWNMSAC_VV, + 15638 => Opcode::VFWREDOSUM_VS, + 15639 => Opcode::VFWREDUSUM_VS, + 15640 => Opcode::VFWSUB_VF, + 15641 => Opcode::VFWSUB_VV, + 15642 => Opcode::VFWSUB_WF, + 15643 => Opcode::VFWSUB_WV, + 15644 => Opcode::VGHSH_VS, + 15645 => Opcode::VGHSH_VV, + 15646 => Opcode::VGMUL_VS, + 15647 => Opcode::VGMUL_VV, + 15648 => Opcode::VID_V, + 15649 => Opcode::VIOTA_M, + 15650 => Opcode::VL1RE16_V, + 15651 => Opcode::VL1RE32_V, + 15652 => Opcode::VL1RE64_V, + 15653 => Opcode::VL1RE8_V, + 15654 => Opcode::VL2RE16_V, + 15655 => Opcode::VL2RE32_V, + 15656 => Opcode::VL2RE64_V, + 15657 => Opcode::VL2RE8_V, + 15658 => Opcode::VL4RE16_V, + 15659 => Opcode::VL4RE32_V, + 15660 => Opcode::VL4RE64_V, + 15661 => Opcode::VL4RE8_V, + 15662 => Opcode::VL8RE16_V, + 15663 => Opcode::VL8RE32_V, + 15664 => Opcode::VL8RE64_V, + 15665 => Opcode::VL8RE8_V, + 15666 => Opcode::VLE16FF_V, + 15667 => Opcode::VLE16_V, + 15668 => Opcode::VLE32FF_V, + 15669 => Opcode::VLE32_V, + 15670 => Opcode::VLE64FF_V, + 15671 => Opcode::VLE64_V, + 15672 => Opcode::VLE8FF_V, + 15673 => Opcode::VLE8_V, + 15674 => Opcode::VLM_V, + 15675 => Opcode::VLOXEI16_V, + 15676 => Opcode::VLOXEI32_V, + 15677 => Opcode::VLOXEI64_V, + 15678 => Opcode::VLOXEI8_V, + 15679 => Opcode::VLOXSEG2EI16_V, + 15680 => Opcode::VLOXSEG2EI32_V, + 15681 => Opcode::VLOXSEG2EI64_V, + 15682 => Opcode::VLOXSEG2EI8_V, + 15683 => Opcode::VLOXSEG3EI16_V, + 15684 => Opcode::VLOXSEG3EI32_V, + 15685 => Opcode::VLOXSEG3EI64_V, + 15686 => Opcode::VLOXSEG3EI8_V, + 15687 => Opcode::VLOXSEG4EI16_V, + 15688 => Opcode::VLOXSEG4EI32_V, + 15689 => Opcode::VLOXSEG4EI64_V, + 15690 => Opcode::VLOXSEG4EI8_V, + 15691 => Opcode::VLOXSEG5EI16_V, + 15692 => Opcode::VLOXSEG5EI32_V, + 15693 => Opcode::VLOXSEG5EI64_V, + 15694 => Opcode::VLOXSEG5EI8_V, + 15695 => Opcode::VLOXSEG6EI16_V, + 15696 => Opcode::VLOXSEG6EI32_V, + 15697 => Opcode::VLOXSEG6EI64_V, + 15698 => Opcode::VLOXSEG6EI8_V, + 15699 => Opcode::VLOXSEG7EI16_V, + 15700 => Opcode::VLOXSEG7EI32_V, + 15701 => Opcode::VLOXSEG7EI64_V, + 15702 => Opcode::VLOXSEG7EI8_V, + 15703 => Opcode::VLOXSEG8EI16_V, + 15704 => Opcode::VLOXSEG8EI32_V, + 15705 => Opcode::VLOXSEG8EI64_V, + 15706 => Opcode::VLOXSEG8EI8_V, + 15707 => Opcode::VLSE16_V, + 15708 => Opcode::VLSE32_V, + 15709 => Opcode::VLSE64_V, + 15710 => Opcode::VLSE8_V, + 15711 => Opcode::VLSEG2E16FF_V, + 15712 => Opcode::VLSEG2E16_V, + 15713 => Opcode::VLSEG2E32FF_V, + 15714 => Opcode::VLSEG2E32_V, + 15715 => Opcode::VLSEG2E64FF_V, + 15716 => Opcode::VLSEG2E64_V, + 15717 => Opcode::VLSEG2E8FF_V, + 15718 => Opcode::VLSEG2E8_V, + 15719 => Opcode::VLSEG3E16FF_V, + 15720 => Opcode::VLSEG3E16_V, + 15721 => Opcode::VLSEG3E32FF_V, + 15722 => Opcode::VLSEG3E32_V, + 15723 => Opcode::VLSEG3E64FF_V, + 15724 => Opcode::VLSEG3E64_V, + 15725 => Opcode::VLSEG3E8FF_V, + 15726 => Opcode::VLSEG3E8_V, + 15727 => Opcode::VLSEG4E16FF_V, + 15728 => Opcode::VLSEG4E16_V, + 15729 => Opcode::VLSEG4E32FF_V, + 15730 => Opcode::VLSEG4E32_V, + 15731 => Opcode::VLSEG4E64FF_V, + 15732 => Opcode::VLSEG4E64_V, + 15733 => Opcode::VLSEG4E8FF_V, + 15734 => Opcode::VLSEG4E8_V, + 15735 => Opcode::VLSEG5E16FF_V, + 15736 => Opcode::VLSEG5E16_V, + 15737 => Opcode::VLSEG5E32FF_V, + 15738 => Opcode::VLSEG5E32_V, + 15739 => Opcode::VLSEG5E64FF_V, + 15740 => Opcode::VLSEG5E64_V, + 15741 => Opcode::VLSEG5E8FF_V, + 15742 => Opcode::VLSEG5E8_V, + 15743 => Opcode::VLSEG6E16FF_V, + 15744 => Opcode::VLSEG6E16_V, + 15745 => Opcode::VLSEG6E32FF_V, + 15746 => Opcode::VLSEG6E32_V, + 15747 => Opcode::VLSEG6E64FF_V, + 15748 => Opcode::VLSEG6E64_V, + 15749 => Opcode::VLSEG6E8FF_V, + 15750 => Opcode::VLSEG6E8_V, + 15751 => Opcode::VLSEG7E16FF_V, + 15752 => Opcode::VLSEG7E16_V, + 15753 => Opcode::VLSEG7E32FF_V, + 15754 => Opcode::VLSEG7E32_V, + 15755 => Opcode::VLSEG7E64FF_V, + 15756 => Opcode::VLSEG7E64_V, + 15757 => Opcode::VLSEG7E8FF_V, + 15758 => Opcode::VLSEG7E8_V, + 15759 => Opcode::VLSEG8E16FF_V, + 15760 => Opcode::VLSEG8E16_V, + 15761 => Opcode::VLSEG8E32FF_V, + 15762 => Opcode::VLSEG8E32_V, + 15763 => Opcode::VLSEG8E64FF_V, + 15764 => Opcode::VLSEG8E64_V, + 15765 => Opcode::VLSEG8E8FF_V, + 15766 => Opcode::VLSEG8E8_V, + 15767 => Opcode::VLSSEG2E16_V, + 15768 => Opcode::VLSSEG2E32_V, + 15769 => Opcode::VLSSEG2E64_V, + 15770 => Opcode::VLSSEG2E8_V, + 15771 => Opcode::VLSSEG3E16_V, + 15772 => Opcode::VLSSEG3E32_V, + 15773 => Opcode::VLSSEG3E64_V, + 15774 => Opcode::VLSSEG3E8_V, + 15775 => Opcode::VLSSEG4E16_V, + 15776 => Opcode::VLSSEG4E32_V, + 15777 => Opcode::VLSSEG4E64_V, + 15778 => Opcode::VLSSEG4E8_V, + 15779 => Opcode::VLSSEG5E16_V, + 15780 => Opcode::VLSSEG5E32_V, + 15781 => Opcode::VLSSEG5E64_V, + 15782 => Opcode::VLSSEG5E8_V, + 15783 => Opcode::VLSSEG6E16_V, + 15784 => Opcode::VLSSEG6E32_V, + 15785 => Opcode::VLSSEG6E64_V, + 15786 => Opcode::VLSSEG6E8_V, + 15787 => Opcode::VLSSEG7E16_V, + 15788 => Opcode::VLSSEG7E32_V, + 15789 => Opcode::VLSSEG7E64_V, + 15790 => Opcode::VLSSEG7E8_V, + 15791 => Opcode::VLSSEG8E16_V, + 15792 => Opcode::VLSSEG8E32_V, + 15793 => Opcode::VLSSEG8E64_V, + 15794 => Opcode::VLSSEG8E8_V, + 15795 => Opcode::VLUXEI16_V, + 15796 => Opcode::VLUXEI32_V, + 15797 => Opcode::VLUXEI64_V, + 15798 => Opcode::VLUXEI8_V, + 15799 => Opcode::VLUXSEG2EI16_V, + 15800 => Opcode::VLUXSEG2EI32_V, + 15801 => Opcode::VLUXSEG2EI64_V, + 15802 => Opcode::VLUXSEG2EI8_V, + 15803 => Opcode::VLUXSEG3EI16_V, + 15804 => Opcode::VLUXSEG3EI32_V, + 15805 => Opcode::VLUXSEG3EI64_V, + 15806 => Opcode::VLUXSEG3EI8_V, + 15807 => Opcode::VLUXSEG4EI16_V, + 15808 => Opcode::VLUXSEG4EI32_V, + 15809 => Opcode::VLUXSEG4EI64_V, + 15810 => Opcode::VLUXSEG4EI8_V, + 15811 => Opcode::VLUXSEG5EI16_V, + 15812 => Opcode::VLUXSEG5EI32_V, + 15813 => Opcode::VLUXSEG5EI64_V, + 15814 => Opcode::VLUXSEG5EI8_V, + 15815 => Opcode::VLUXSEG6EI16_V, + 15816 => Opcode::VLUXSEG6EI32_V, + 15817 => Opcode::VLUXSEG6EI64_V, + 15818 => Opcode::VLUXSEG6EI8_V, + 15819 => Opcode::VLUXSEG7EI16_V, + 15820 => Opcode::VLUXSEG7EI32_V, + 15821 => Opcode::VLUXSEG7EI64_V, + 15822 => Opcode::VLUXSEG7EI8_V, + 15823 => Opcode::VLUXSEG8EI16_V, + 15824 => Opcode::VLUXSEG8EI32_V, + 15825 => Opcode::VLUXSEG8EI64_V, + 15826 => Opcode::VLUXSEG8EI8_V, + 15827 => Opcode::VMACC_VV, + 15828 => Opcode::VMACC_VX, + 15829 => Opcode::VMADC_VI, + 15830 => Opcode::VMADC_VIM, + 15831 => Opcode::VMADC_VV, + 15832 => Opcode::VMADC_VVM, + 15833 => Opcode::VMADC_VX, + 15834 => Opcode::VMADC_VXM, + 15835 => Opcode::VMADD_VV, + 15836 => Opcode::VMADD_VX, + 15837 => Opcode::VMANDN_MM, + 15838 => Opcode::VMAND_MM, + 15839 => Opcode::VMAXU_VV, + 15840 => Opcode::VMAXU_VX, + 15841 => Opcode::VMAX_VV, + 15842 => Opcode::VMAX_VX, + 15843 => Opcode::VMERGE_VIM, + 15844 => Opcode::VMERGE_VVM, + 15845 => Opcode::VMERGE_VXM, + 15846 => Opcode::VMFEQ_VF, + 15847 => Opcode::VMFEQ_VV, + 15848 => Opcode::VMFGE_VF, + 15849 => Opcode::VMFGT_VF, + 15850 => Opcode::VMFLE_VF, + 15851 => Opcode::VMFLE_VV, + 15852 => Opcode::VMFLT_VF, + 15853 => Opcode::VMFLT_VV, + 15854 => Opcode::VMFNE_VF, + 15855 => Opcode::VMFNE_VV, + 15856 => Opcode::VMINU_VV, + 15857 => Opcode::VMINU_VX, + 15858 => Opcode::VMIN_VV, + 15859 => Opcode::VMIN_VX, + 15860 => Opcode::VMNAND_MM, + 15861 => Opcode::VMNOR_MM, + 15862 => Opcode::VMORN_MM, + 15863 => Opcode::VMOR_MM, + 15864 => Opcode::VMSBC_VV, + 15865 => Opcode::VMSBC_VVM, + 15866 => Opcode::VMSBC_VX, + 15867 => Opcode::VMSBC_VXM, + 15868 => Opcode::VMSBF_M, + 15869 => Opcode::VMSEQ_VI, + 15870 => Opcode::VMSEQ_VV, + 15871 => Opcode::VMSEQ_VX, + 15872 => Opcode::VMSGTU_VI, + 15873 => Opcode::VMSGTU_VX, + 15874 => Opcode::VMSGT_VI, + 15875 => Opcode::VMSGT_VX, + 15876 => Opcode::VMSIF_M, + 15877 => Opcode::VMSLEU_VI, + 15878 => Opcode::VMSLEU_VV, + 15879 => Opcode::VMSLEU_VX, + 15880 => Opcode::VMSLE_VI, + 15881 => Opcode::VMSLE_VV, + 15882 => Opcode::VMSLE_VX, + 15883 => Opcode::VMSLTU_VV, + 15884 => Opcode::VMSLTU_VX, + 15885 => Opcode::VMSLT_VV, + 15886 => Opcode::VMSLT_VX, + 15887 => Opcode::VMSNE_VI, + 15888 => Opcode::VMSNE_VV, + 15889 => Opcode::VMSNE_VX, + 15890 => Opcode::VMSOF_M, + 15891 => Opcode::VMULHSU_VV, + 15892 => Opcode::VMULHSU_VX, + 15893 => Opcode::VMULHU_VV, + 15894 => Opcode::VMULHU_VX, + 15895 => Opcode::VMULH_VV, + 15896 => Opcode::VMULH_VX, + 15897 => Opcode::VMUL_VV, + 15898 => Opcode::VMUL_VX, + 15899 => Opcode::VMV1R_V, + 15900 => Opcode::VMV2R_V, + 15901 => Opcode::VMV4R_V, + 15902 => Opcode::VMV8R_V, + 15903 => Opcode::VMV_S_X, + 15904 => Opcode::VMV_V_I, + 15905 => Opcode::VMV_V_V, + 15906 => Opcode::VMV_V_X, + 15907 => Opcode::VMV_X_S, + 15908 => Opcode::VMXNOR_MM, + 15909 => Opcode::VMXOR_MM, + 15910 => Opcode::VNCLIPU_WI, + 15911 => Opcode::VNCLIPU_WV, + 15912 => Opcode::VNCLIPU_WX, + 15913 => Opcode::VNCLIP_WI, + 15914 => Opcode::VNCLIP_WV, + 15915 => Opcode::VNCLIP_WX, + 15916 => Opcode::VNMSAC_VV, + 15917 => Opcode::VNMSAC_VX, + 15918 => Opcode::VNMSUB_VV, + 15919 => Opcode::VNMSUB_VX, + 15920 => Opcode::VNSRA_WI, + 15921 => Opcode::VNSRA_WV, + 15922 => Opcode::VNSRA_WX, + 15923 => Opcode::VNSRL_WI, + 15924 => Opcode::VNSRL_WV, + 15925 => Opcode::VNSRL_WX, + 15926 => Opcode::VOR_VI, + 15927 => Opcode::VOR_VV, + 15928 => Opcode::VOR_VX, + 15929 => Opcode::VQDOTSU_VV, + 15930 => Opcode::VQDOTSU_VX, + 15931 => Opcode::VQDOTUS_VX, + 15932 => Opcode::VQDOTU_VV, + 15933 => Opcode::VQDOTU_VX, + 15934 => Opcode::VQDOT_VV, + 15935 => Opcode::VQDOT_VX, + 15936 => Opcode::VREDAND_VS, + 15937 => Opcode::VREDMAXU_VS, + 15938 => Opcode::VREDMAX_VS, + 15939 => Opcode::VREDMINU_VS, + 15940 => Opcode::VREDMIN_VS, + 15941 => Opcode::VREDOR_VS, + 15942 => Opcode::VREDSUM_VS, + 15943 => Opcode::VREDXOR_VS, + 15944 => Opcode::VREMU_VV, + 15945 => Opcode::VREMU_VX, + 15946 => Opcode::VREM_VV, + 15947 => Opcode::VREM_VX, + 15948 => Opcode::VREV8_V, + 15949 => Opcode::VRGATHEREI16_VV, + 15950 => Opcode::VRGATHER_VI, + 15951 => Opcode::VRGATHER_VV, + 15952 => Opcode::VRGATHER_VX, + 15953 => Opcode::VROL_VV, + 15954 => Opcode::VROL_VX, + 15955 => Opcode::VROR_VI, + 15956 => Opcode::VROR_VV, + 15957 => Opcode::VROR_VX, + 15958 => Opcode::VRSUB_VI, + 15959 => Opcode::VRSUB_VX, + 15960 => Opcode::VS1R_V, + 15961 => Opcode::VS2R_V, + 15962 => Opcode::VS4R_V, + 15963 => Opcode::VS8R_V, + 15964 => Opcode::VSADDU_VI, + 15965 => Opcode::VSADDU_VV, + 15966 => Opcode::VSADDU_VX, + 15967 => Opcode::VSADD_VI, + 15968 => Opcode::VSADD_VV, + 15969 => Opcode::VSADD_VX, + 15970 => Opcode::VSBC_VVM, + 15971 => Opcode::VSBC_VXM, + 15972 => Opcode::VSE16_V, + 15973 => Opcode::VSE32_V, + 15974 => Opcode::VSE64_V, + 15975 => Opcode::VSE8_V, + 15976 => Opcode::VSETIVLI, + 15977 => Opcode::VSETVL, + 15978 => Opcode::VSETVLI, + 15979 => Opcode::VSEXT_VF2, + 15980 => Opcode::VSEXT_VF4, + 15981 => Opcode::VSEXT_VF8, + 15982 => Opcode::VSHA2CH_VV, + 15983 => Opcode::VSHA2CL_VV, + 15984 => Opcode::VSHA2MS_VV, + 15985 => Opcode::VSLIDE1DOWN_VX, + 15986 => Opcode::VSLIDE1UP_VX, + 15987 => Opcode::VSLIDEDOWN_VI, + 15988 => Opcode::VSLIDEDOWN_VX, + 15989 => Opcode::VSLIDEUP_VI, + 15990 => Opcode::VSLIDEUP_VX, + 15991 => Opcode::VSLL_VI, + 15992 => Opcode::VSLL_VV, + 15993 => Opcode::VSLL_VX, + 15994 => Opcode::VSM3C_VI, + 15995 => Opcode::VSM3ME_VV, + 15996 => Opcode::VSM4K_VI, + 15997 => Opcode::VSM4R_VS, + 15998 => Opcode::VSM4R_VV, + 15999 => Opcode::VSMUL_VV, + 16000 => Opcode::VSMUL_VX, + 16001 => Opcode::VSM_V, + 16002 => Opcode::VSOXEI16_V, + 16003 => Opcode::VSOXEI32_V, + 16004 => Opcode::VSOXEI64_V, + 16005 => Opcode::VSOXEI8_V, + 16006 => Opcode::VSOXSEG2EI16_V, + 16007 => Opcode::VSOXSEG2EI32_V, + 16008 => Opcode::VSOXSEG2EI64_V, + 16009 => Opcode::VSOXSEG2EI8_V, + 16010 => Opcode::VSOXSEG3EI16_V, + 16011 => Opcode::VSOXSEG3EI32_V, + 16012 => Opcode::VSOXSEG3EI64_V, + 16013 => Opcode::VSOXSEG3EI8_V, + 16014 => Opcode::VSOXSEG4EI16_V, + 16015 => Opcode::VSOXSEG4EI32_V, + 16016 => Opcode::VSOXSEG4EI64_V, + 16017 => Opcode::VSOXSEG4EI8_V, + 16018 => Opcode::VSOXSEG5EI16_V, + 16019 => Opcode::VSOXSEG5EI32_V, + 16020 => Opcode::VSOXSEG5EI64_V, + 16021 => Opcode::VSOXSEG5EI8_V, + 16022 => Opcode::VSOXSEG6EI16_V, + 16023 => Opcode::VSOXSEG6EI32_V, + 16024 => Opcode::VSOXSEG6EI64_V, + 16025 => Opcode::VSOXSEG6EI8_V, + 16026 => Opcode::VSOXSEG7EI16_V, + 16027 => Opcode::VSOXSEG7EI32_V, + 16028 => Opcode::VSOXSEG7EI64_V, + 16029 => Opcode::VSOXSEG7EI8_V, + 16030 => Opcode::VSOXSEG8EI16_V, + 16031 => Opcode::VSOXSEG8EI32_V, + 16032 => Opcode::VSOXSEG8EI64_V, + 16033 => Opcode::VSOXSEG8EI8_V, + 16034 => Opcode::VSRA_VI, + 16035 => Opcode::VSRA_VV, + 16036 => Opcode::VSRA_VX, + 16037 => Opcode::VSRL_VI, + 16038 => Opcode::VSRL_VV, + 16039 => Opcode::VSRL_VX, + 16040 => Opcode::VSSE16_V, + 16041 => Opcode::VSSE32_V, + 16042 => Opcode::VSSE64_V, + 16043 => Opcode::VSSE8_V, + 16044 => Opcode::VSSEG2E16_V, + 16045 => Opcode::VSSEG2E32_V, + 16046 => Opcode::VSSEG2E64_V, + 16047 => Opcode::VSSEG2E8_V, + 16048 => Opcode::VSSEG3E16_V, + 16049 => Opcode::VSSEG3E32_V, + 16050 => Opcode::VSSEG3E64_V, + 16051 => Opcode::VSSEG3E8_V, + 16052 => Opcode::VSSEG4E16_V, + 16053 => Opcode::VSSEG4E32_V, + 16054 => Opcode::VSSEG4E64_V, + 16055 => Opcode::VSSEG4E8_V, + 16056 => Opcode::VSSEG5E16_V, + 16057 => Opcode::VSSEG5E32_V, + 16058 => Opcode::VSSEG5E64_V, + 16059 => Opcode::VSSEG5E8_V, + 16060 => Opcode::VSSEG6E16_V, + 16061 => Opcode::VSSEG6E32_V, + 16062 => Opcode::VSSEG6E64_V, + 16063 => Opcode::VSSEG6E8_V, + 16064 => Opcode::VSSEG7E16_V, + 16065 => Opcode::VSSEG7E32_V, + 16066 => Opcode::VSSEG7E64_V, + 16067 => Opcode::VSSEG7E8_V, + 16068 => Opcode::VSSEG8E16_V, + 16069 => Opcode::VSSEG8E32_V, + 16070 => Opcode::VSSEG8E64_V, + 16071 => Opcode::VSSEG8E8_V, + 16072 => Opcode::VSSRA_VI, + 16073 => Opcode::VSSRA_VV, + 16074 => Opcode::VSSRA_VX, + 16075 => Opcode::VSSRL_VI, + 16076 => Opcode::VSSRL_VV, + 16077 => Opcode::VSSRL_VX, + 16078 => Opcode::VSSSEG2E16_V, + 16079 => Opcode::VSSSEG2E32_V, + 16080 => Opcode::VSSSEG2E64_V, + 16081 => Opcode::VSSSEG2E8_V, + 16082 => Opcode::VSSSEG3E16_V, + 16083 => Opcode::VSSSEG3E32_V, + 16084 => Opcode::VSSSEG3E64_V, + 16085 => Opcode::VSSSEG3E8_V, + 16086 => Opcode::VSSSEG4E16_V, + 16087 => Opcode::VSSSEG4E32_V, + 16088 => Opcode::VSSSEG4E64_V, + 16089 => Opcode::VSSSEG4E8_V, + 16090 => Opcode::VSSSEG5E16_V, + 16091 => Opcode::VSSSEG5E32_V, + 16092 => Opcode::VSSSEG5E64_V, + 16093 => Opcode::VSSSEG5E8_V, + 16094 => Opcode::VSSSEG6E16_V, + 16095 => Opcode::VSSSEG6E32_V, + 16096 => Opcode::VSSSEG6E64_V, + 16097 => Opcode::VSSSEG6E8_V, + 16098 => Opcode::VSSSEG7E16_V, + 16099 => Opcode::VSSSEG7E32_V, + 16100 => Opcode::VSSSEG7E64_V, + 16101 => Opcode::VSSSEG7E8_V, + 16102 => Opcode::VSSSEG8E16_V, + 16103 => Opcode::VSSSEG8E32_V, + 16104 => Opcode::VSSSEG8E64_V, + 16105 => Opcode::VSSSEG8E8_V, + 16106 => Opcode::VSSUBU_VV, + 16107 => Opcode::VSSUBU_VX, + 16108 => Opcode::VSSUB_VV, + 16109 => Opcode::VSSUB_VX, + 16110 => Opcode::VSUB_VV, + 16111 => Opcode::VSUB_VX, + 16112 => Opcode::VSUXEI16_V, + 16113 => Opcode::VSUXEI32_V, + 16114 => Opcode::VSUXEI64_V, + 16115 => Opcode::VSUXEI8_V, + 16116 => Opcode::VSUXSEG2EI16_V, + 16117 => Opcode::VSUXSEG2EI32_V, + 16118 => Opcode::VSUXSEG2EI64_V, + 16119 => Opcode::VSUXSEG2EI8_V, + 16120 => Opcode::VSUXSEG3EI16_V, + 16121 => Opcode::VSUXSEG3EI32_V, + 16122 => Opcode::VSUXSEG3EI64_V, + 16123 => Opcode::VSUXSEG3EI8_V, + 16124 => Opcode::VSUXSEG4EI16_V, + 16125 => Opcode::VSUXSEG4EI32_V, + 16126 => Opcode::VSUXSEG4EI64_V, + 16127 => Opcode::VSUXSEG4EI8_V, + 16128 => Opcode::VSUXSEG5EI16_V, + 16129 => Opcode::VSUXSEG5EI32_V, + 16130 => Opcode::VSUXSEG5EI64_V, + 16131 => Opcode::VSUXSEG5EI8_V, + 16132 => Opcode::VSUXSEG6EI16_V, + 16133 => Opcode::VSUXSEG6EI32_V, + 16134 => Opcode::VSUXSEG6EI64_V, + 16135 => Opcode::VSUXSEG6EI8_V, + 16136 => Opcode::VSUXSEG7EI16_V, + 16137 => Opcode::VSUXSEG7EI32_V, + 16138 => Opcode::VSUXSEG7EI64_V, + 16139 => Opcode::VSUXSEG7EI8_V, + 16140 => Opcode::VSUXSEG8EI16_V, + 16141 => Opcode::VSUXSEG8EI32_V, + 16142 => Opcode::VSUXSEG8EI64_V, + 16143 => Opcode::VSUXSEG8EI8_V, + 16144 => Opcode::VT_MASKC, + 16145 => Opcode::VT_MASKCN, + 16146 => Opcode::VWADDU_VV, + 16147 => Opcode::VWADDU_VX, + 16148 => Opcode::VWADDU_WV, + 16149 => Opcode::VWADDU_WX, + 16150 => Opcode::VWADD_VV, + 16151 => Opcode::VWADD_VX, + 16152 => Opcode::VWADD_WV, + 16153 => Opcode::VWADD_WX, + 16154 => Opcode::VWMACCSU_VV, + 16155 => Opcode::VWMACCSU_VX, + 16156 => Opcode::VWMACCUS_VX, + 16157 => Opcode::VWMACCU_VV, + 16158 => Opcode::VWMACCU_VX, + 16159 => Opcode::VWMACC_VV, + 16160 => Opcode::VWMACC_VX, + 16161 => Opcode::VWMULSU_VV, + 16162 => Opcode::VWMULSU_VX, + 16163 => Opcode::VWMULU_VV, + 16164 => Opcode::VWMULU_VX, + 16165 => Opcode::VWMUL_VV, + 16166 => Opcode::VWMUL_VX, + 16167 => Opcode::VWREDSUMU_VS, + 16168 => Opcode::VWREDSUM_VS, + 16169 => Opcode::VWSLL_VI, + 16170 => Opcode::VWSLL_VV, + 16171 => Opcode::VWSLL_VX, + 16172 => Opcode::VWSUBU_VV, + 16173 => Opcode::VWSUBU_VX, + 16174 => Opcode::VWSUBU_WV, + 16175 => Opcode::VWSUBU_WX, + 16176 => Opcode::VWSUB_VV, + 16177 => Opcode::VWSUB_VX, + 16178 => Opcode::VWSUB_WV, + 16179 => Opcode::VWSUB_WX, + 16180 => Opcode::VXOR_VI, + 16181 => Opcode::VXOR_VV, + 16182 => Opcode::VXOR_VX, + 16183 => Opcode::VZEXT_VF2, + 16184 => Opcode::VZEXT_VF4, + 16185 => Opcode::VZEXT_VF8, + 16186 => Opcode::WADD, + 16187 => Opcode::WADDA, + 16188 => Opcode::WADDAU, + 16189 => Opcode::WADDU, + 16190 => Opcode::WFI, + 16191 => Opcode::WMACC, + 16192 => Opcode::WMACCSU, + 16193 => Opcode::WMACCU, + 16194 => Opcode::WMUL, + 16195 => Opcode::WMULSU, + 16196 => Opcode::WMULU, + 16197 => Opcode::WRS_NTO, + 16198 => Opcode::WRS_STO, + 16199 => Opcode::WSLA, + 16200 => Opcode::WSLAI, + 16201 => Opcode::WSLL, + 16202 => Opcode::WSLLI, + 16203 => Opcode::WSUB, + 16204 => Opcode::WSUBA, + 16205 => Opcode::WSUBAU, + 16206 => Opcode::WSUBU, + 16207 => Opcode::WZIP16P, + 16208 => Opcode::WZIP8P, + 16209 => Opcode::XNOR, + 16210 => Opcode::XOR, + 16211 => Opcode::XORI, + 16212 => Opcode::XPERM4, + 16213 => Opcode::XPERM8, + 16214 => Opcode::ZEXT_H_RV32, + 16215 => Opcode::ZEXT_H_RV64, + 16216 => Opcode::ZIP16HP, + 16217 => Opcode::ZIP16P, + 16218 => Opcode::ZIP8HP, + 16219 => Opcode::ZIP8P, + 16220 => Opcode::ZIP_RV32, + 16221 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands.rs new file mode 100644 index 0000000..3f3a039 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand + Reg(Register), + + /// A PC-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_riscv_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_riscv_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_riscv_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_riscv_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/immediate.rs new file mode 100644 index 0000000..3a007cd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// addi a0, a1, 8 +/// | +/// +---> Immediate(8) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/memory.rs new file mode 100644 index 0000000..bcb275f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/memory.rs @@ -0,0 +1,47 @@ +use lief_ffi as ffi; + +use crate::{assembly::riscv::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// ```text +/// lw a0, 8(sp) +/// | | +/// | +----> Base: sp +/// | +/// +-------> Displacement: 8 +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Memory { + /// The base register. + /// + /// For `lw a0, 8(sp)` it would return `sp` + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The displacement value. + /// + /// For `lw a0, 8(sp)` it would return `8` + pub fn displacement(&self) -> i64 { + self.ptr.displacement() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/pc_relative.rs new file mode 100644 index 0000000..675febb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/pc_relative.rs @@ -0,0 +1,37 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a PC-relative operand. +/// +/// ```text +/// auipc a0, 0x1 +/// | +/// v +/// PC Relative operand +/// ``` +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `pc` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/register.rs new file mode 100644 index 0000000..a72d32b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/operands/register.rs @@ -0,0 +1,51 @@ +use lief_ffi as ffi; + +use crate::assembly::riscv::registers::{Reg, SysReg}; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// ```text +/// csrr a0, mstatus +/// | | +/// +------+ +-------+ +/// | | +/// v v +/// REG SYSREG +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_riscv_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +#[derive(Debug)] +pub enum Value { + Reg(Reg), + SysReg(SysReg), +} + +impl Register { + /// The effective register as either: a [`Reg`] or a [`SysReg`] + pub fn value(&self) -> Option { + let ffi_value = self.ptr.value(); + match ffi_value.enum_type { + 1 => Some(Value::SysReg(SysReg::from(ffi_value.reg))), + 2 => Some(Value::Reg(Reg::from(ffi_value.reg))), + _ => None, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/riscv/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/registers.rs new file mode 100644 index 0000000..89cefa8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/riscv/registers.rs @@ -0,0 +1,2203 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + FCSR, + FFLAGS, + FRM, + SF_VCIX_STATE, + SSP, + VL, + VLENB, + VTYPE, + VXRM, + VXSAT, + DUMMY_REG_PAIR_WITH_X0, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + V0, + V1, + V2, + V3, + V4, + V5, + V6, + V7, + V8, + V9, + V10, + V11, + V12, + V13, + V14, + V15, + V16, + V17, + V18, + V19, + V20, + V21, + V22, + V23, + V24, + V25, + V26, + V27, + V28, + V29, + V30, + V31, + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + X29, + X30, + X31, + F0_D, + F1_D, + F2_D, + F3_D, + F4_D, + F5_D, + F6_D, + F7_D, + F8_D, + F9_D, + F10_D, + F11_D, + F12_D, + F13_D, + F14_D, + F15_D, + F16_D, + F17_D, + F18_D, + F19_D, + F20_D, + F21_D, + F22_D, + F23_D, + F24_D, + F25_D, + F26_D, + F27_D, + F28_D, + F29_D, + F30_D, + F31_D, + F0_F, + F1_F, + F2_F, + F3_F, + F4_F, + F5_F, + F6_F, + F7_F, + F8_F, + F9_F, + F10_F, + F11_F, + F12_F, + F13_F, + F14_F, + F15_F, + F16_F, + F17_F, + F18_F, + F19_F, + F20_F, + F21_F, + F22_F, + F23_F, + F24_F, + F25_F, + F26_F, + F27_F, + F28_F, + F29_F, + F30_F, + F31_F, + F0_H, + F1_H, + F2_H, + F3_H, + F4_H, + F5_H, + F6_H, + F7_H, + F8_H, + F9_H, + F10_H, + F11_H, + F12_H, + F13_H, + F14_H, + F15_H, + F16_H, + F17_H, + F18_H, + F19_H, + F20_H, + F21_H, + F22_H, + F23_H, + F24_H, + F25_H, + F26_H, + F27_H, + F28_H, + F29_H, + F30_H, + F31_H, + F0_Q, + F1_Q, + F2_Q, + F3_Q, + F4_Q, + F5_Q, + F6_Q, + F7_Q, + F8_Q, + F9_Q, + F10_Q, + F11_Q, + F12_Q, + F13_Q, + F14_Q, + F15_Q, + F16_Q, + F17_Q, + F18_Q, + F19_Q, + F20_Q, + F21_Q, + F22_Q, + F23_Q, + F24_Q, + F25_Q, + F26_Q, + F27_Q, + F28_Q, + F29_Q, + F30_Q, + F31_Q, + X0_H, + X1_H, + X2_H, + X3_H, + X4_H, + X5_H, + X6_H, + X7_H, + X8_H, + X9_H, + X10_H, + X11_H, + X12_H, + X13_H, + X14_H, + X15_H, + X16_H, + X17_H, + X18_H, + X19_H, + X20_H, + X21_H, + X22_H, + X23_H, + X24_H, + X25_H, + X26_H, + X27_H, + X28_H, + X29_H, + X30_H, + X31_H, + X0_Pair, + X0_W, + X1_W, + X2_W, + X3_W, + X4_W, + X5_W, + X6_W, + X7_W, + X8_W, + X9_W, + X10_W, + X11_W, + X12_W, + X13_W, + X14_W, + X15_W, + X16_W, + X17_W, + X18_W, + X19_W, + X20_W, + X21_W, + X22_W, + X23_W, + X24_W, + X25_W, + X26_W, + X27_W, + X28_W, + X29_W, + X30_W, + X31_W, + V0M2, + V0M4, + V0M8, + V2M2, + V4M2, + V4M4, + V6M2, + V8M2, + V8M4, + V8M8, + V10M2, + V12M2, + V12M4, + V14M2, + V16M2, + V16M4, + V16M8, + V18M2, + V20M2, + V20M4, + V22M2, + V24M2, + V24M4, + V24M8, + V26M2, + V28M2, + V28M4, + V30M2, + X2_X3, + X4_X5, + X6_X7, + X8_X9, + X10_X11, + X12_X13, + X14_X15, + X16_X17, + X18_X19, + X20_X21, + X22_X23, + X24_X25, + X26_X27, + X28_X29, + X30_X31, + V1_V2, + V2_V3, + V3_V4, + V4_V5, + V5_V6, + V6_V7, + V7_V8, + V8_V9, + V9_V10, + V10_V11, + V11_V12, + V12_V13, + V13_V14, + V14_V15, + V15_V16, + V16_V17, + V17_V18, + V18_V19, + V19_V20, + V20_V21, + V21_V22, + V22_V23, + V23_V24, + V24_V25, + V25_V26, + V26_V27, + V27_V28, + V28_V29, + V29_V30, + V30_V31, + V0_V1, + V2M2_V4M2, + V4M2_V6M2, + V6M2_V8M2, + V8M2_V10M2, + V10M2_V12M2, + V12M2_V14M2, + V14M2_V16M2, + V16M2_V18M2, + V18M2_V20M2, + V20M2_V22M2, + V22M2_V24M2, + V24M2_V26M2, + V26M2_V28M2, + V28M2_V30M2, + V0M2_V2M2, + V4M4_V8M4, + V8M4_V12M4, + V12M4_V16M4, + V16M4_V20M4, + V20M4_V24M4, + V24M4_V28M4, + V0M4_V4M4, + V1_V2_V3, + V2_V3_V4, + V3_V4_V5, + V4_V5_V6, + V5_V6_V7, + V6_V7_V8, + V7_V8_V9, + V8_V9_V10, + V9_V10_V11, + V10_V11_V12, + V11_V12_V13, + V12_V13_V14, + V13_V14_V15, + V14_V15_V16, + V15_V16_V17, + V16_V17_V18, + V17_V18_V19, + V18_V19_V20, + V19_V20_V21, + V20_V21_V22, + V21_V22_V23, + V22_V23_V24, + V23_V24_V25, + V24_V25_V26, + V25_V26_V27, + V26_V27_V28, + V27_V28_V29, + V28_V29_V30, + V29_V30_V31, + V0_V1_V2, + V2M2_V4M2_V6M2, + V4M2_V6M2_V8M2, + V6M2_V8M2_V10M2, + V8M2_V10M2_V12M2, + V10M2_V12M2_V14M2, + V12M2_V14M2_V16M2, + V14M2_V16M2_V18M2, + V16M2_V18M2_V20M2, + V18M2_V20M2_V22M2, + V20M2_V22M2_V24M2, + V22M2_V24M2_V26M2, + V24M2_V26M2_V28M2, + V26M2_V28M2_V30M2, + V0M2_V2M2_V4M2, + V1_V2_V3_V4, + V2_V3_V4_V5, + V3_V4_V5_V6, + V4_V5_V6_V7, + V5_V6_V7_V8, + V6_V7_V8_V9, + V7_V8_V9_V10, + V8_V9_V10_V11, + V9_V10_V11_V12, + V10_V11_V12_V13, + V11_V12_V13_V14, + V12_V13_V14_V15, + V13_V14_V15_V16, + V14_V15_V16_V17, + V15_V16_V17_V18, + V16_V17_V18_V19, + V17_V18_V19_V20, + V18_V19_V20_V21, + V19_V20_V21_V22, + V20_V21_V22_V23, + V21_V22_V23_V24, + V22_V23_V24_V25, + V23_V24_V25_V26, + V24_V25_V26_V27, + V25_V26_V27_V28, + V26_V27_V28_V29, + V27_V28_V29_V30, + V28_V29_V30_V31, + V0_V1_V2_V3, + V2M2_V4M2_V6M2_V8M2, + V4M2_V6M2_V8M2_V10M2, + V6M2_V8M2_V10M2_V12M2, + V8M2_V10M2_V12M2_V14M2, + V10M2_V12M2_V14M2_V16M2, + V12M2_V14M2_V16M2_V18M2, + V14M2_V16M2_V18M2_V20M2, + V16M2_V18M2_V20M2_V22M2, + V18M2_V20M2_V22M2_V24M2, + V20M2_V22M2_V24M2_V26M2, + V22M2_V24M2_V26M2_V28M2, + V24M2_V26M2_V28M2_V30M2, + V0M2_V2M2_V4M2_V6M2, + V1_V2_V3_V4_V5, + V2_V3_V4_V5_V6, + V3_V4_V5_V6_V7, + V4_V5_V6_V7_V8, + V5_V6_V7_V8_V9, + V6_V7_V8_V9_V10, + V7_V8_V9_V10_V11, + V8_V9_V10_V11_V12, + V9_V10_V11_V12_V13, + V10_V11_V12_V13_V14, + V11_V12_V13_V14_V15, + V12_V13_V14_V15_V16, + V13_V14_V15_V16_V17, + V14_V15_V16_V17_V18, + V15_V16_V17_V18_V19, + V16_V17_V18_V19_V20, + V17_V18_V19_V20_V21, + V18_V19_V20_V21_V22, + V19_V20_V21_V22_V23, + V20_V21_V22_V23_V24, + V21_V22_V23_V24_V25, + V22_V23_V24_V25_V26, + V23_V24_V25_V26_V27, + V24_V25_V26_V27_V28, + V25_V26_V27_V28_V29, + V26_V27_V28_V29_V30, + V27_V28_V29_V30_V31, + V0_V1_V2_V3_V4, + V1_V2_V3_V4_V5_V6, + V2_V3_V4_V5_V6_V7, + V3_V4_V5_V6_V7_V8, + V4_V5_V6_V7_V8_V9, + V5_V6_V7_V8_V9_V10, + V6_V7_V8_V9_V10_V11, + V7_V8_V9_V10_V11_V12, + V8_V9_V10_V11_V12_V13, + V9_V10_V11_V12_V13_V14, + V10_V11_V12_V13_V14_V15, + V11_V12_V13_V14_V15_V16, + V12_V13_V14_V15_V16_V17, + V13_V14_V15_V16_V17_V18, + V14_V15_V16_V17_V18_V19, + V15_V16_V17_V18_V19_V20, + V16_V17_V18_V19_V20_V21, + V17_V18_V19_V20_V21_V22, + V18_V19_V20_V21_V22_V23, + V19_V20_V21_V22_V23_V24, + V20_V21_V22_V23_V24_V25, + V21_V22_V23_V24_V25_V26, + V22_V23_V24_V25_V26_V27, + V23_V24_V25_V26_V27_V28, + V24_V25_V26_V27_V28_V29, + V25_V26_V27_V28_V29_V30, + V26_V27_V28_V29_V30_V31, + V0_V1_V2_V3_V4_V5, + V1_V2_V3_V4_V5_V6_V7, + V2_V3_V4_V5_V6_V7_V8, + V3_V4_V5_V6_V7_V8_V9, + V4_V5_V6_V7_V8_V9_V10, + V5_V6_V7_V8_V9_V10_V11, + V6_V7_V8_V9_V10_V11_V12, + V7_V8_V9_V10_V11_V12_V13, + V8_V9_V10_V11_V12_V13_V14, + V9_V10_V11_V12_V13_V14_V15, + V10_V11_V12_V13_V14_V15_V16, + V11_V12_V13_V14_V15_V16_V17, + V12_V13_V14_V15_V16_V17_V18, + V13_V14_V15_V16_V17_V18_V19, + V14_V15_V16_V17_V18_V19_V20, + V15_V16_V17_V18_V19_V20_V21, + V16_V17_V18_V19_V20_V21_V22, + V17_V18_V19_V20_V21_V22_V23, + V18_V19_V20_V21_V22_V23_V24, + V19_V20_V21_V22_V23_V24_V25, + V20_V21_V22_V23_V24_V25_V26, + V21_V22_V23_V24_V25_V26_V27, + V22_V23_V24_V25_V26_V27_V28, + V23_V24_V25_V26_V27_V28_V29, + V24_V25_V26_V27_V28_V29_V30, + V25_V26_V27_V28_V29_V30_V31, + V0_V1_V2_V3_V4_V5_V6, + V1_V2_V3_V4_V5_V6_V7_V8, + V2_V3_V4_V5_V6_V7_V8_V9, + V3_V4_V5_V6_V7_V8_V9_V10, + V4_V5_V6_V7_V8_V9_V10_V11, + V5_V6_V7_V8_V9_V10_V11_V12, + V6_V7_V8_V9_V10_V11_V12_V13, + V7_V8_V9_V10_V11_V12_V13_V14, + V8_V9_V10_V11_V12_V13_V14_V15, + V9_V10_V11_V12_V13_V14_V15_V16, + V10_V11_V12_V13_V14_V15_V16_V17, + V11_V12_V13_V14_V15_V16_V17_V18, + V12_V13_V14_V15_V16_V17_V18_V19, + V13_V14_V15_V16_V17_V18_V19_V20, + V14_V15_V16_V17_V18_V19_V20_V21, + V15_V16_V17_V18_V19_V20_V21_V22, + V16_V17_V18_V19_V20_V21_V22_V23, + V17_V18_V19_V20_V21_V22_V23_V24, + V18_V19_V20_V21_V22_V23_V24_V25, + V19_V20_V21_V22_V23_V24_V25_V26, + V20_V21_V22_V23_V24_V25_V26_V27, + V21_V22_V23_V24_V25_V26_V27_V28, + V22_V23_V24_V25_V26_V27_V28_V29, + V23_V24_V25_V26_V27_V28_V29_V30, + V24_V25_V26_V27_V28_V29_V30_V31, + V0_V1_V2_V3_V4_V5_V6_V7, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::FCSR, + 2 => Reg::FFLAGS, + 3 => Reg::FRM, + 4 => Reg::SF_VCIX_STATE, + 5 => Reg::SSP, + 6 => Reg::VL, + 7 => Reg::VLENB, + 8 => Reg::VTYPE, + 9 => Reg::VXRM, + 10 => Reg::VXSAT, + 11 => Reg::DUMMY_REG_PAIR_WITH_X0, + 12 => Reg::T0, + 13 => Reg::T1, + 14 => Reg::T2, + 15 => Reg::T3, + 16 => Reg::T4, + 17 => Reg::T5, + 18 => Reg::T6, + 19 => Reg::T7, + 20 => Reg::T8, + 21 => Reg::T9, + 22 => Reg::T10, + 23 => Reg::T11, + 24 => Reg::T12, + 25 => Reg::T13, + 26 => Reg::T14, + 27 => Reg::T15, + 28 => Reg::V0, + 29 => Reg::V1, + 30 => Reg::V2, + 31 => Reg::V3, + 32 => Reg::V4, + 33 => Reg::V5, + 34 => Reg::V6, + 35 => Reg::V7, + 36 => Reg::V8, + 37 => Reg::V9, + 38 => Reg::V10, + 39 => Reg::V11, + 40 => Reg::V12, + 41 => Reg::V13, + 42 => Reg::V14, + 43 => Reg::V15, + 44 => Reg::V16, + 45 => Reg::V17, + 46 => Reg::V18, + 47 => Reg::V19, + 48 => Reg::V20, + 49 => Reg::V21, + 50 => Reg::V22, + 51 => Reg::V23, + 52 => Reg::V24, + 53 => Reg::V25, + 54 => Reg::V26, + 55 => Reg::V27, + 56 => Reg::V28, + 57 => Reg::V29, + 58 => Reg::V30, + 59 => Reg::V31, + 60 => Reg::X0, + 61 => Reg::X1, + 62 => Reg::X2, + 63 => Reg::X3, + 64 => Reg::X4, + 65 => Reg::X5, + 66 => Reg::X6, + 67 => Reg::X7, + 68 => Reg::X8, + 69 => Reg::X9, + 70 => Reg::X10, + 71 => Reg::X11, + 72 => Reg::X12, + 73 => Reg::X13, + 74 => Reg::X14, + 75 => Reg::X15, + 76 => Reg::X16, + 77 => Reg::X17, + 78 => Reg::X18, + 79 => Reg::X19, + 80 => Reg::X20, + 81 => Reg::X21, + 82 => Reg::X22, + 83 => Reg::X23, + 84 => Reg::X24, + 85 => Reg::X25, + 86 => Reg::X26, + 87 => Reg::X27, + 88 => Reg::X28, + 89 => Reg::X29, + 90 => Reg::X30, + 91 => Reg::X31, + 92 => Reg::F0_D, + 93 => Reg::F1_D, + 94 => Reg::F2_D, + 95 => Reg::F3_D, + 96 => Reg::F4_D, + 97 => Reg::F5_D, + 98 => Reg::F6_D, + 99 => Reg::F7_D, + 100 => Reg::F8_D, + 101 => Reg::F9_D, + 102 => Reg::F10_D, + 103 => Reg::F11_D, + 104 => Reg::F12_D, + 105 => Reg::F13_D, + 106 => Reg::F14_D, + 107 => Reg::F15_D, + 108 => Reg::F16_D, + 109 => Reg::F17_D, + 110 => Reg::F18_D, + 111 => Reg::F19_D, + 112 => Reg::F20_D, + 113 => Reg::F21_D, + 114 => Reg::F22_D, + 115 => Reg::F23_D, + 116 => Reg::F24_D, + 117 => Reg::F25_D, + 118 => Reg::F26_D, + 119 => Reg::F27_D, + 120 => Reg::F28_D, + 121 => Reg::F29_D, + 122 => Reg::F30_D, + 123 => Reg::F31_D, + 124 => Reg::F0_F, + 125 => Reg::F1_F, + 126 => Reg::F2_F, + 127 => Reg::F3_F, + 128 => Reg::F4_F, + 129 => Reg::F5_F, + 130 => Reg::F6_F, + 131 => Reg::F7_F, + 132 => Reg::F8_F, + 133 => Reg::F9_F, + 134 => Reg::F10_F, + 135 => Reg::F11_F, + 136 => Reg::F12_F, + 137 => Reg::F13_F, + 138 => Reg::F14_F, + 139 => Reg::F15_F, + 140 => Reg::F16_F, + 141 => Reg::F17_F, + 142 => Reg::F18_F, + 143 => Reg::F19_F, + 144 => Reg::F20_F, + 145 => Reg::F21_F, + 146 => Reg::F22_F, + 147 => Reg::F23_F, + 148 => Reg::F24_F, + 149 => Reg::F25_F, + 150 => Reg::F26_F, + 151 => Reg::F27_F, + 152 => Reg::F28_F, + 153 => Reg::F29_F, + 154 => Reg::F30_F, + 155 => Reg::F31_F, + 156 => Reg::F0_H, + 157 => Reg::F1_H, + 158 => Reg::F2_H, + 159 => Reg::F3_H, + 160 => Reg::F4_H, + 161 => Reg::F5_H, + 162 => Reg::F6_H, + 163 => Reg::F7_H, + 164 => Reg::F8_H, + 165 => Reg::F9_H, + 166 => Reg::F10_H, + 167 => Reg::F11_H, + 168 => Reg::F12_H, + 169 => Reg::F13_H, + 170 => Reg::F14_H, + 171 => Reg::F15_H, + 172 => Reg::F16_H, + 173 => Reg::F17_H, + 174 => Reg::F18_H, + 175 => Reg::F19_H, + 176 => Reg::F20_H, + 177 => Reg::F21_H, + 178 => Reg::F22_H, + 179 => Reg::F23_H, + 180 => Reg::F24_H, + 181 => Reg::F25_H, + 182 => Reg::F26_H, + 183 => Reg::F27_H, + 184 => Reg::F28_H, + 185 => Reg::F29_H, + 186 => Reg::F30_H, + 187 => Reg::F31_H, + 188 => Reg::F0_Q, + 189 => Reg::F1_Q, + 190 => Reg::F2_Q, + 191 => Reg::F3_Q, + 192 => Reg::F4_Q, + 193 => Reg::F5_Q, + 194 => Reg::F6_Q, + 195 => Reg::F7_Q, + 196 => Reg::F8_Q, + 197 => Reg::F9_Q, + 198 => Reg::F10_Q, + 199 => Reg::F11_Q, + 200 => Reg::F12_Q, + 201 => Reg::F13_Q, + 202 => Reg::F14_Q, + 203 => Reg::F15_Q, + 204 => Reg::F16_Q, + 205 => Reg::F17_Q, + 206 => Reg::F18_Q, + 207 => Reg::F19_Q, + 208 => Reg::F20_Q, + 209 => Reg::F21_Q, + 210 => Reg::F22_Q, + 211 => Reg::F23_Q, + 212 => Reg::F24_Q, + 213 => Reg::F25_Q, + 214 => Reg::F26_Q, + 215 => Reg::F27_Q, + 216 => Reg::F28_Q, + 217 => Reg::F29_Q, + 218 => Reg::F30_Q, + 219 => Reg::F31_Q, + 220 => Reg::X0_H, + 221 => Reg::X1_H, + 222 => Reg::X2_H, + 223 => Reg::X3_H, + 224 => Reg::X4_H, + 225 => Reg::X5_H, + 226 => Reg::X6_H, + 227 => Reg::X7_H, + 228 => Reg::X8_H, + 229 => Reg::X9_H, + 230 => Reg::X10_H, + 231 => Reg::X11_H, + 232 => Reg::X12_H, + 233 => Reg::X13_H, + 234 => Reg::X14_H, + 235 => Reg::X15_H, + 236 => Reg::X16_H, + 237 => Reg::X17_H, + 238 => Reg::X18_H, + 239 => Reg::X19_H, + 240 => Reg::X20_H, + 241 => Reg::X21_H, + 242 => Reg::X22_H, + 243 => Reg::X23_H, + 244 => Reg::X24_H, + 245 => Reg::X25_H, + 246 => Reg::X26_H, + 247 => Reg::X27_H, + 248 => Reg::X28_H, + 249 => Reg::X29_H, + 250 => Reg::X30_H, + 251 => Reg::X31_H, + 252 => Reg::X0_Pair, + 253 => Reg::X0_W, + 254 => Reg::X1_W, + 255 => Reg::X2_W, + 256 => Reg::X3_W, + 257 => Reg::X4_W, + 258 => Reg::X5_W, + 259 => Reg::X6_W, + 260 => Reg::X7_W, + 261 => Reg::X8_W, + 262 => Reg::X9_W, + 263 => Reg::X10_W, + 264 => Reg::X11_W, + 265 => Reg::X12_W, + 266 => Reg::X13_W, + 267 => Reg::X14_W, + 268 => Reg::X15_W, + 269 => Reg::X16_W, + 270 => Reg::X17_W, + 271 => Reg::X18_W, + 272 => Reg::X19_W, + 273 => Reg::X20_W, + 274 => Reg::X21_W, + 275 => Reg::X22_W, + 276 => Reg::X23_W, + 277 => Reg::X24_W, + 278 => Reg::X25_W, + 279 => Reg::X26_W, + 280 => Reg::X27_W, + 281 => Reg::X28_W, + 282 => Reg::X29_W, + 283 => Reg::X30_W, + 284 => Reg::X31_W, + 285 => Reg::V0M2, + 286 => Reg::V0M4, + 287 => Reg::V0M8, + 288 => Reg::V2M2, + 289 => Reg::V4M2, + 290 => Reg::V4M4, + 291 => Reg::V6M2, + 292 => Reg::V8M2, + 293 => Reg::V8M4, + 294 => Reg::V8M8, + 295 => Reg::V10M2, + 296 => Reg::V12M2, + 297 => Reg::V12M4, + 298 => Reg::V14M2, + 299 => Reg::V16M2, + 300 => Reg::V16M4, + 301 => Reg::V16M8, + 302 => Reg::V18M2, + 303 => Reg::V20M2, + 304 => Reg::V20M4, + 305 => Reg::V22M2, + 306 => Reg::V24M2, + 307 => Reg::V24M4, + 308 => Reg::V24M8, + 309 => Reg::V26M2, + 310 => Reg::V28M2, + 311 => Reg::V28M4, + 312 => Reg::V30M2, + 313 => Reg::X2_X3, + 314 => Reg::X4_X5, + 315 => Reg::X6_X7, + 316 => Reg::X8_X9, + 317 => Reg::X10_X11, + 318 => Reg::X12_X13, + 319 => Reg::X14_X15, + 320 => Reg::X16_X17, + 321 => Reg::X18_X19, + 322 => Reg::X20_X21, + 323 => Reg::X22_X23, + 324 => Reg::X24_X25, + 325 => Reg::X26_X27, + 326 => Reg::X28_X29, + 327 => Reg::X30_X31, + 328 => Reg::V1_V2, + 329 => Reg::V2_V3, + 330 => Reg::V3_V4, + 331 => Reg::V4_V5, + 332 => Reg::V5_V6, + 333 => Reg::V6_V7, + 334 => Reg::V7_V8, + 335 => Reg::V8_V9, + 336 => Reg::V9_V10, + 337 => Reg::V10_V11, + 338 => Reg::V11_V12, + 339 => Reg::V12_V13, + 340 => Reg::V13_V14, + 341 => Reg::V14_V15, + 342 => Reg::V15_V16, + 343 => Reg::V16_V17, + 344 => Reg::V17_V18, + 345 => Reg::V18_V19, + 346 => Reg::V19_V20, + 347 => Reg::V20_V21, + 348 => Reg::V21_V22, + 349 => Reg::V22_V23, + 350 => Reg::V23_V24, + 351 => Reg::V24_V25, + 352 => Reg::V25_V26, + 353 => Reg::V26_V27, + 354 => Reg::V27_V28, + 355 => Reg::V28_V29, + 356 => Reg::V29_V30, + 357 => Reg::V30_V31, + 358 => Reg::V0_V1, + 359 => Reg::V2M2_V4M2, + 360 => Reg::V4M2_V6M2, + 361 => Reg::V6M2_V8M2, + 362 => Reg::V8M2_V10M2, + 363 => Reg::V10M2_V12M2, + 364 => Reg::V12M2_V14M2, + 365 => Reg::V14M2_V16M2, + 366 => Reg::V16M2_V18M2, + 367 => Reg::V18M2_V20M2, + 368 => Reg::V20M2_V22M2, + 369 => Reg::V22M2_V24M2, + 370 => Reg::V24M2_V26M2, + 371 => Reg::V26M2_V28M2, + 372 => Reg::V28M2_V30M2, + 373 => Reg::V0M2_V2M2, + 374 => Reg::V4M4_V8M4, + 375 => Reg::V8M4_V12M4, + 376 => Reg::V12M4_V16M4, + 377 => Reg::V16M4_V20M4, + 378 => Reg::V20M4_V24M4, + 379 => Reg::V24M4_V28M4, + 380 => Reg::V0M4_V4M4, + 381 => Reg::V1_V2_V3, + 382 => Reg::V2_V3_V4, + 383 => Reg::V3_V4_V5, + 384 => Reg::V4_V5_V6, + 385 => Reg::V5_V6_V7, + 386 => Reg::V6_V7_V8, + 387 => Reg::V7_V8_V9, + 388 => Reg::V8_V9_V10, + 389 => Reg::V9_V10_V11, + 390 => Reg::V10_V11_V12, + 391 => Reg::V11_V12_V13, + 392 => Reg::V12_V13_V14, + 393 => Reg::V13_V14_V15, + 394 => Reg::V14_V15_V16, + 395 => Reg::V15_V16_V17, + 396 => Reg::V16_V17_V18, + 397 => Reg::V17_V18_V19, + 398 => Reg::V18_V19_V20, + 399 => Reg::V19_V20_V21, + 400 => Reg::V20_V21_V22, + 401 => Reg::V21_V22_V23, + 402 => Reg::V22_V23_V24, + 403 => Reg::V23_V24_V25, + 404 => Reg::V24_V25_V26, + 405 => Reg::V25_V26_V27, + 406 => Reg::V26_V27_V28, + 407 => Reg::V27_V28_V29, + 408 => Reg::V28_V29_V30, + 409 => Reg::V29_V30_V31, + 410 => Reg::V0_V1_V2, + 411 => Reg::V2M2_V4M2_V6M2, + 412 => Reg::V4M2_V6M2_V8M2, + 413 => Reg::V6M2_V8M2_V10M2, + 414 => Reg::V8M2_V10M2_V12M2, + 415 => Reg::V10M2_V12M2_V14M2, + 416 => Reg::V12M2_V14M2_V16M2, + 417 => Reg::V14M2_V16M2_V18M2, + 418 => Reg::V16M2_V18M2_V20M2, + 419 => Reg::V18M2_V20M2_V22M2, + 420 => Reg::V20M2_V22M2_V24M2, + 421 => Reg::V22M2_V24M2_V26M2, + 422 => Reg::V24M2_V26M2_V28M2, + 423 => Reg::V26M2_V28M2_V30M2, + 424 => Reg::V0M2_V2M2_V4M2, + 425 => Reg::V1_V2_V3_V4, + 426 => Reg::V2_V3_V4_V5, + 427 => Reg::V3_V4_V5_V6, + 428 => Reg::V4_V5_V6_V7, + 429 => Reg::V5_V6_V7_V8, + 430 => Reg::V6_V7_V8_V9, + 431 => Reg::V7_V8_V9_V10, + 432 => Reg::V8_V9_V10_V11, + 433 => Reg::V9_V10_V11_V12, + 434 => Reg::V10_V11_V12_V13, + 435 => Reg::V11_V12_V13_V14, + 436 => Reg::V12_V13_V14_V15, + 437 => Reg::V13_V14_V15_V16, + 438 => Reg::V14_V15_V16_V17, + 439 => Reg::V15_V16_V17_V18, + 440 => Reg::V16_V17_V18_V19, + 441 => Reg::V17_V18_V19_V20, + 442 => Reg::V18_V19_V20_V21, + 443 => Reg::V19_V20_V21_V22, + 444 => Reg::V20_V21_V22_V23, + 445 => Reg::V21_V22_V23_V24, + 446 => Reg::V22_V23_V24_V25, + 447 => Reg::V23_V24_V25_V26, + 448 => Reg::V24_V25_V26_V27, + 449 => Reg::V25_V26_V27_V28, + 450 => Reg::V26_V27_V28_V29, + 451 => Reg::V27_V28_V29_V30, + 452 => Reg::V28_V29_V30_V31, + 453 => Reg::V0_V1_V2_V3, + 454 => Reg::V2M2_V4M2_V6M2_V8M2, + 455 => Reg::V4M2_V6M2_V8M2_V10M2, + 456 => Reg::V6M2_V8M2_V10M2_V12M2, + 457 => Reg::V8M2_V10M2_V12M2_V14M2, + 458 => Reg::V10M2_V12M2_V14M2_V16M2, + 459 => Reg::V12M2_V14M2_V16M2_V18M2, + 460 => Reg::V14M2_V16M2_V18M2_V20M2, + 461 => Reg::V16M2_V18M2_V20M2_V22M2, + 462 => Reg::V18M2_V20M2_V22M2_V24M2, + 463 => Reg::V20M2_V22M2_V24M2_V26M2, + 464 => Reg::V22M2_V24M2_V26M2_V28M2, + 465 => Reg::V24M2_V26M2_V28M2_V30M2, + 466 => Reg::V0M2_V2M2_V4M2_V6M2, + 467 => Reg::V1_V2_V3_V4_V5, + 468 => Reg::V2_V3_V4_V5_V6, + 469 => Reg::V3_V4_V5_V6_V7, + 470 => Reg::V4_V5_V6_V7_V8, + 471 => Reg::V5_V6_V7_V8_V9, + 472 => Reg::V6_V7_V8_V9_V10, + 473 => Reg::V7_V8_V9_V10_V11, + 474 => Reg::V8_V9_V10_V11_V12, + 475 => Reg::V9_V10_V11_V12_V13, + 476 => Reg::V10_V11_V12_V13_V14, + 477 => Reg::V11_V12_V13_V14_V15, + 478 => Reg::V12_V13_V14_V15_V16, + 479 => Reg::V13_V14_V15_V16_V17, + 480 => Reg::V14_V15_V16_V17_V18, + 481 => Reg::V15_V16_V17_V18_V19, + 482 => Reg::V16_V17_V18_V19_V20, + 483 => Reg::V17_V18_V19_V20_V21, + 484 => Reg::V18_V19_V20_V21_V22, + 485 => Reg::V19_V20_V21_V22_V23, + 486 => Reg::V20_V21_V22_V23_V24, + 487 => Reg::V21_V22_V23_V24_V25, + 488 => Reg::V22_V23_V24_V25_V26, + 489 => Reg::V23_V24_V25_V26_V27, + 490 => Reg::V24_V25_V26_V27_V28, + 491 => Reg::V25_V26_V27_V28_V29, + 492 => Reg::V26_V27_V28_V29_V30, + 493 => Reg::V27_V28_V29_V30_V31, + 494 => Reg::V0_V1_V2_V3_V4, + 495 => Reg::V1_V2_V3_V4_V5_V6, + 496 => Reg::V2_V3_V4_V5_V6_V7, + 497 => Reg::V3_V4_V5_V6_V7_V8, + 498 => Reg::V4_V5_V6_V7_V8_V9, + 499 => Reg::V5_V6_V7_V8_V9_V10, + 500 => Reg::V6_V7_V8_V9_V10_V11, + 501 => Reg::V7_V8_V9_V10_V11_V12, + 502 => Reg::V8_V9_V10_V11_V12_V13, + 503 => Reg::V9_V10_V11_V12_V13_V14, + 504 => Reg::V10_V11_V12_V13_V14_V15, + 505 => Reg::V11_V12_V13_V14_V15_V16, + 506 => Reg::V12_V13_V14_V15_V16_V17, + 507 => Reg::V13_V14_V15_V16_V17_V18, + 508 => Reg::V14_V15_V16_V17_V18_V19, + 509 => Reg::V15_V16_V17_V18_V19_V20, + 510 => Reg::V16_V17_V18_V19_V20_V21, + 511 => Reg::V17_V18_V19_V20_V21_V22, + 512 => Reg::V18_V19_V20_V21_V22_V23, + 513 => Reg::V19_V20_V21_V22_V23_V24, + 514 => Reg::V20_V21_V22_V23_V24_V25, + 515 => Reg::V21_V22_V23_V24_V25_V26, + 516 => Reg::V22_V23_V24_V25_V26_V27, + 517 => Reg::V23_V24_V25_V26_V27_V28, + 518 => Reg::V24_V25_V26_V27_V28_V29, + 519 => Reg::V25_V26_V27_V28_V29_V30, + 520 => Reg::V26_V27_V28_V29_V30_V31, + 521 => Reg::V0_V1_V2_V3_V4_V5, + 522 => Reg::V1_V2_V3_V4_V5_V6_V7, + 523 => Reg::V2_V3_V4_V5_V6_V7_V8, + 524 => Reg::V3_V4_V5_V6_V7_V8_V9, + 525 => Reg::V4_V5_V6_V7_V8_V9_V10, + 526 => Reg::V5_V6_V7_V8_V9_V10_V11, + 527 => Reg::V6_V7_V8_V9_V10_V11_V12, + 528 => Reg::V7_V8_V9_V10_V11_V12_V13, + 529 => Reg::V8_V9_V10_V11_V12_V13_V14, + 530 => Reg::V9_V10_V11_V12_V13_V14_V15, + 531 => Reg::V10_V11_V12_V13_V14_V15_V16, + 532 => Reg::V11_V12_V13_V14_V15_V16_V17, + 533 => Reg::V12_V13_V14_V15_V16_V17_V18, + 534 => Reg::V13_V14_V15_V16_V17_V18_V19, + 535 => Reg::V14_V15_V16_V17_V18_V19_V20, + 536 => Reg::V15_V16_V17_V18_V19_V20_V21, + 537 => Reg::V16_V17_V18_V19_V20_V21_V22, + 538 => Reg::V17_V18_V19_V20_V21_V22_V23, + 539 => Reg::V18_V19_V20_V21_V22_V23_V24, + 540 => Reg::V19_V20_V21_V22_V23_V24_V25, + 541 => Reg::V20_V21_V22_V23_V24_V25_V26, + 542 => Reg::V21_V22_V23_V24_V25_V26_V27, + 543 => Reg::V22_V23_V24_V25_V26_V27_V28, + 544 => Reg::V23_V24_V25_V26_V27_V28_V29, + 545 => Reg::V24_V25_V26_V27_V28_V29_V30, + 546 => Reg::V25_V26_V27_V28_V29_V30_V31, + 547 => Reg::V0_V1_V2_V3_V4_V5_V6, + 548 => Reg::V1_V2_V3_V4_V5_V6_V7_V8, + 549 => Reg::V2_V3_V4_V5_V6_V7_V8_V9, + 550 => Reg::V3_V4_V5_V6_V7_V8_V9_V10, + 551 => Reg::V4_V5_V6_V7_V8_V9_V10_V11, + 552 => Reg::V5_V6_V7_V8_V9_V10_V11_V12, + 553 => Reg::V6_V7_V8_V9_V10_V11_V12_V13, + 554 => Reg::V7_V8_V9_V10_V11_V12_V13_V14, + 555 => Reg::V8_V9_V10_V11_V12_V13_V14_V15, + 556 => Reg::V9_V10_V11_V12_V13_V14_V15_V16, + 557 => Reg::V10_V11_V12_V13_V14_V15_V16_V17, + 558 => Reg::V11_V12_V13_V14_V15_V16_V17_V18, + 559 => Reg::V12_V13_V14_V15_V16_V17_V18_V19, + 560 => Reg::V13_V14_V15_V16_V17_V18_V19_V20, + 561 => Reg::V14_V15_V16_V17_V18_V19_V20_V21, + 562 => Reg::V15_V16_V17_V18_V19_V20_V21_V22, + 563 => Reg::V16_V17_V18_V19_V20_V21_V22_V23, + 564 => Reg::V17_V18_V19_V20_V21_V22_V23_V24, + 565 => Reg::V18_V19_V20_V21_V22_V23_V24_V25, + 566 => Reg::V19_V20_V21_V22_V23_V24_V25_V26, + 567 => Reg::V20_V21_V22_V23_V24_V25_V26_V27, + 568 => Reg::V21_V22_V23_V24_V25_V26_V27_V28, + 569 => Reg::V22_V23_V24_V25_V26_V27_V28_V29, + 570 => Reg::V23_V24_V25_V26_V27_V28_V29_V30, + 571 => Reg::V24_V25_V26_V27_V28_V29_V30_V31, + 572 => Reg::V0_V1_V2_V3_V4_V5_V6_V7, + 573 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum SysReg { + fflags, + frm, + fcsr, + vstart, + vxsat, + vxrm, + vcsr, + ssp, + seed, + jvt, + sstatus, + sie, + stvec, + scounteren, + sf_stvt, + senvcfg, + sstateen0, + sstateen1, + sstateen2, + sstateen3, + sieh, + scountinhibit, + sscratch, + sepc, + scause, + sbadaddr, + sip, + sf_snxti, + sf_sintstatus, + sf_sscratchcsw, + sf_sscratchcswl, + stimecmp, + sctrctl, + sctrstatus, + siselect, + sireg, + sireg2, + sireg3, + siph, + sireg4, + sireg5, + sireg6, + stopei, + stimecmph, + sctrdepth, + satp, + srmcfg, + vsstatus, + vsie, + vstvec, + vsieh, + vsscratch, + vsepc, + vscause, + vstval, + vsip, + vstimecmp, + vsctrctl, + vsiselect, + vsireg, + vsireg2, + vsireg3, + vsiph, + vsireg4, + vsireg5, + vsireg6, + vstopei, + vstimecmph, + vsatp, + mstatus, + misa, + medeleg, + mideleg, + mie, + mtvec, + mcounteren, + sf_mtvt, + mvien, + mvip, + menvcfg, + mstateen0, + mstateen1, + mstateen2, + mstateen3, + mstatush, + medelegh, + midelegh, + mieh, + mvienh, + mviph, + menvcfgh, + mstateen0h, + mstateen1h, + mstateen2h, + mstateen3h, + mcountinhibit, + mcyclecfg, + minstretcfg, + mhpmevent3, + mhpmevent4, + mhpmevent5, + mhpmevent6, + mhpmevent7, + mhpmevent8, + mhpmevent9, + mhpmevent10, + mhpmevent11, + mhpmevent12, + mhpmevent13, + mhpmevent14, + mhpmevent15, + mhpmevent16, + mhpmevent17, + mhpmevent18, + mhpmevent19, + mhpmevent20, + mhpmevent21, + mhpmevent22, + mhpmevent23, + mhpmevent24, + mhpmevent25, + mhpmevent26, + mhpmevent27, + mhpmevent28, + mhpmevent29, + mhpmevent30, + mhpmevent31, + mscratch, + mepc, + mcause, + mbadaddr, + mip, + sf_mnxti, + sf_mintstatus, + sf_mscratchcsw, + sf_mscratchcswl, + mtinst, + mtval2, + mctrctl, + miselect, + mireg, + mireg2, + mireg3, + miph, + mireg4, + mireg5, + mireg6, + mtopei, + pmpcfg0, + pmpcfg1, + pmpcfg2, + pmpcfg3, + pmpcfg4, + pmpcfg5, + pmpcfg6, + pmpcfg7, + pmpcfg8, + pmpcfg9, + pmpcfg10, + pmpcfg11, + pmpcfg12, + pmpcfg13, + pmpcfg14, + pmpcfg15, + pmpaddr0, + pmpaddr1, + pmpaddr2, + pmpaddr3, + pmpaddr4, + pmpaddr5, + pmpaddr6, + pmpaddr7, + pmpaddr8, + pmpaddr9, + pmpaddr10, + pmpaddr11, + pmpaddr12, + pmpaddr13, + pmpaddr14, + pmpaddr15, + pmpaddr16, + pmpaddr17, + pmpaddr18, + pmpaddr19, + pmpaddr20, + pmpaddr21, + pmpaddr22, + pmpaddr23, + pmpaddr24, + pmpaddr25, + pmpaddr26, + pmpaddr27, + pmpaddr28, + pmpaddr29, + pmpaddr30, + pmpaddr31, + pmpaddr32, + pmpaddr33, + pmpaddr34, + pmpaddr35, + pmpaddr36, + pmpaddr37, + pmpaddr38, + pmpaddr39, + pmpaddr40, + pmpaddr41, + pmpaddr42, + pmpaddr43, + pmpaddr44, + pmpaddr45, + pmpaddr46, + pmpaddr47, + pmpaddr48, + pmpaddr49, + pmpaddr50, + pmpaddr51, + pmpaddr52, + pmpaddr53, + pmpaddr54, + pmpaddr55, + pmpaddr56, + pmpaddr57, + pmpaddr58, + pmpaddr59, + pmpaddr60, + pmpaddr61, + pmpaddr62, + pmpaddr63, + scontext, + hstatus, + hedeleg, + hideleg, + hie, + htimedelta, + hcounteren, + hgeie, + hvien, + hvictl, + henvcfg, + hstateen0, + hstateen1, + hstateen2, + hstateen3, + hedelegh, + hidelegh, + htimedeltah, + hvienh, + henvcfgh, + hstateen0h, + hstateen1h, + hstateen2h, + hstateen3h, + htval, + hip, + hvip, + hviprio1, + hviprio2, + htinst, + hviph, + hviprio1h, + hviprio2h, + hgatp, + hcontext, + mcyclecfgh, + minstretcfgh, + mhpmevent3h, + mhpmevent4h, + mhpmevent5h, + mhpmevent6h, + mhpmevent7h, + mhpmevent8h, + mhpmevent9h, + mhpmevent10h, + mhpmevent11h, + mhpmevent12h, + mhpmevent13h, + mhpmevent14h, + mhpmevent15h, + mhpmevent16h, + mhpmevent17h, + mhpmevent18h, + mhpmevent19h, + mhpmevent20h, + mhpmevent21h, + mhpmevent22h, + mhpmevent23h, + mhpmevent24h, + mhpmevent25h, + mhpmevent26h, + mhpmevent27h, + mhpmevent28h, + mhpmevent29h, + mhpmevent30h, + mhpmevent31h, + mnscratch, + mnepc, + mncause, + mnstatus, + mseccfg, + mseccfgh, + tselect, + etrigger, + tdata2, + tdata3, + tinfo, + tcontrol, + mcontext, + mscontext, + dcsr, + dpc, + dscratch, + dscratch1, + qc_mmcr, + qc_mntvec, + qc_mstktopaddr, + qc_mstkbottomaddr, + qc_mthreadptr, + qc_mcause, + qc_mwpstartaddr0, + qc_mwpstartaddr1, + qc_mwpstartaddr2, + qc_mwpstartaddr3, + qc_mwpendaddr0, + qc_mwpendaddr1, + qc_mwpendaddr2, + qc_mwpendaddr3, + qc_mclicip0, + qc_mclicip1, + qc_mclicip2, + qc_mclicip3, + qc_mclicip4, + qc_mclicip5, + qc_mclicip6, + qc_mclicip7, + qc_mclicie0, + qc_mclicie1, + qc_mclicie2, + qc_mclicie3, + qc_mclicie4, + qc_mclicie5, + qc_mclicie6, + qc_mclicie7, + mcycle, + minstret, + mhpmcounter3, + mhpmcounter4, + mhpmcounter5, + mhpmcounter6, + mhpmcounter7, + mhpmcounter8, + mhpmcounter9, + mhpmcounter10, + mhpmcounter11, + mhpmcounter12, + mhpmcounter13, + mhpmcounter14, + mhpmcounter15, + mhpmcounter16, + mhpmcounter17, + mhpmcounter18, + mhpmcounter19, + mhpmcounter20, + mhpmcounter21, + mhpmcounter22, + mhpmcounter23, + mhpmcounter24, + mhpmcounter25, + mhpmcounter26, + mhpmcounter27, + mhpmcounter28, + mhpmcounter29, + mhpmcounter30, + mhpmcounter31, + mcycleh, + minstreth, + mhpmcounter3h, + mhpmcounter4h, + mhpmcounter5h, + mhpmcounter6h, + mhpmcounter7h, + mhpmcounter8h, + mhpmcounter9h, + mhpmcounter10h, + mhpmcounter11h, + mhpmcounter12h, + mhpmcounter13h, + mhpmcounter14h, + mhpmcounter15h, + mhpmcounter16h, + mhpmcounter17h, + mhpmcounter18h, + mhpmcounter19h, + mhpmcounter20h, + mhpmcounter21h, + mhpmcounter22h, + mhpmcounter23h, + mhpmcounter24h, + mhpmcounter25h, + mhpmcounter26h, + mhpmcounter27h, + mhpmcounter28h, + mhpmcounter29h, + mhpmcounter30h, + mhpmcounter31h, + qc_mclicilvl00, + qc_mclicilvl01, + qc_mclicilvl02, + qc_mclicilvl03, + qc_mclicilvl04, + qc_mclicilvl05, + qc_mclicilvl06, + qc_mclicilvl07, + qc_mclicilvl08, + qc_mclicilvl09, + qc_mclicilvl10, + qc_mclicilvl11, + qc_mclicilvl12, + qc_mclicilvl13, + qc_mclicilvl14, + qc_mclicilvl15, + qc_mclicilvl16, + qc_mclicilvl17, + qc_mclicilvl18, + qc_mclicilvl19, + qc_mclicilvl20, + qc_mclicilvl21, + qc_mclicilvl22, + qc_mclicilvl23, + qc_mclicilvl24, + qc_mclicilvl25, + qc_mclicilvl26, + qc_mclicilvl27, + qc_mclicilvl28, + qc_mclicilvl29, + qc_mclicilvl30, + qc_mclicilvl31, + cycle, + time, + instret, + hpmcounter3, + hpmcounter4, + hpmcounter5, + hpmcounter6, + hpmcounter7, + hpmcounter8, + hpmcounter9, + hpmcounter10, + hpmcounter11, + hpmcounter12, + hpmcounter13, + hpmcounter14, + hpmcounter15, + hpmcounter16, + hpmcounter17, + hpmcounter18, + hpmcounter19, + hpmcounter20, + hpmcounter21, + hpmcounter22, + hpmcounter23, + hpmcounter24, + hpmcounter25, + hpmcounter26, + hpmcounter27, + hpmcounter28, + hpmcounter29, + hpmcounter30, + hpmcounter31, + vl, + vtype, + vlenb, + cycleh, + timeh, + instreth, + hpmcounter3h, + hpmcounter4h, + hpmcounter5h, + hpmcounter6h, + hpmcounter7h, + hpmcounter8h, + hpmcounter9h, + hpmcounter10h, + hpmcounter11h, + hpmcounter12h, + hpmcounter13h, + hpmcounter14h, + hpmcounter15h, + hpmcounter16h, + hpmcounter17h, + hpmcounter18h, + hpmcounter19h, + hpmcounter20h, + hpmcounter21h, + hpmcounter22h, + hpmcounter23h, + hpmcounter24h, + hpmcounter25h, + hpmcounter26h, + hpmcounter27h, + hpmcounter28h, + hpmcounter29h, + hpmcounter30h, + hpmcounter31h, + scountovf, + stopi, + hgeip, + vstopi, + mvendorid, + marchid, + mimpid, + mhartid, + mconfigptr, + mtopi, + NUM_TARGET_SYSREGS, + UNKNOWN(u64), +} + +impl From for SysReg { + fn from(value: u64) -> Self { + match value { + 1 => SysReg::fflags, + 2 => SysReg::frm, + 3 => SysReg::fcsr, + 8 => SysReg::vstart, + 9 => SysReg::vxsat, + 10 => SysReg::vxrm, + 15 => SysReg::vcsr, + 17 => SysReg::ssp, + 21 => SysReg::seed, + 23 => SysReg::jvt, + 256 => SysReg::sstatus, + 260 => SysReg::sie, + 261 => SysReg::stvec, + 262 => SysReg::scounteren, + 263 => SysReg::sf_stvt, + 266 => SysReg::senvcfg, + 268 => SysReg::sstateen0, + 269 => SysReg::sstateen1, + 270 => SysReg::sstateen2, + 271 => SysReg::sstateen3, + 276 => SysReg::sieh, + 288 => SysReg::scountinhibit, + 320 => SysReg::sscratch, + 321 => SysReg::sepc, + 322 => SysReg::scause, + 323 => SysReg::sbadaddr, + 324 => SysReg::sip, + 325 => SysReg::sf_snxti, + 326 => SysReg::sf_sintstatus, + 328 => SysReg::sf_sscratchcsw, + 329 => SysReg::sf_sscratchcswl, + 333 => SysReg::stimecmp, + 334 => SysReg::sctrctl, + 335 => SysReg::sctrstatus, + 336 => SysReg::siselect, + 337 => SysReg::sireg, + 338 => SysReg::sireg2, + 339 => SysReg::sireg3, + 340 => SysReg::siph, + 341 => SysReg::sireg4, + 342 => SysReg::sireg5, + 343 => SysReg::sireg6, + 348 => SysReg::stopei, + 349 => SysReg::stimecmph, + 351 => SysReg::sctrdepth, + 384 => SysReg::satp, + 385 => SysReg::srmcfg, + 512 => SysReg::vsstatus, + 516 => SysReg::vsie, + 517 => SysReg::vstvec, + 532 => SysReg::vsieh, + 576 => SysReg::vsscratch, + 577 => SysReg::vsepc, + 578 => SysReg::vscause, + 579 => SysReg::vstval, + 580 => SysReg::vsip, + 589 => SysReg::vstimecmp, + 590 => SysReg::vsctrctl, + 592 => SysReg::vsiselect, + 593 => SysReg::vsireg, + 594 => SysReg::vsireg2, + 595 => SysReg::vsireg3, + 596 => SysReg::vsiph, + 597 => SysReg::vsireg4, + 598 => SysReg::vsireg5, + 599 => SysReg::vsireg6, + 604 => SysReg::vstopei, + 605 => SysReg::vstimecmph, + 640 => SysReg::vsatp, + 768 => SysReg::mstatus, + 769 => SysReg::misa, + 770 => SysReg::medeleg, + 771 => SysReg::mideleg, + 772 => SysReg::mie, + 773 => SysReg::mtvec, + 774 => SysReg::mcounteren, + 775 => SysReg::sf_mtvt, + 776 => SysReg::mvien, + 777 => SysReg::mvip, + 778 => SysReg::menvcfg, + 780 => SysReg::mstateen0, + 781 => SysReg::mstateen1, + 782 => SysReg::mstateen2, + 783 => SysReg::mstateen3, + 784 => SysReg::mstatush, + 786 => SysReg::medelegh, + 787 => SysReg::midelegh, + 788 => SysReg::mieh, + 792 => SysReg::mvienh, + 793 => SysReg::mviph, + 794 => SysReg::menvcfgh, + 796 => SysReg::mstateen0h, + 797 => SysReg::mstateen1h, + 798 => SysReg::mstateen2h, + 799 => SysReg::mstateen3h, + 800 => SysReg::mcountinhibit, + 801 => SysReg::mcyclecfg, + 802 => SysReg::minstretcfg, + 803 => SysReg::mhpmevent3, + 804 => SysReg::mhpmevent4, + 805 => SysReg::mhpmevent5, + 806 => SysReg::mhpmevent6, + 807 => SysReg::mhpmevent7, + 808 => SysReg::mhpmevent8, + 809 => SysReg::mhpmevent9, + 810 => SysReg::mhpmevent10, + 811 => SysReg::mhpmevent11, + 812 => SysReg::mhpmevent12, + 813 => SysReg::mhpmevent13, + 814 => SysReg::mhpmevent14, + 815 => SysReg::mhpmevent15, + 816 => SysReg::mhpmevent16, + 817 => SysReg::mhpmevent17, + 818 => SysReg::mhpmevent18, + 819 => SysReg::mhpmevent19, + 820 => SysReg::mhpmevent20, + 821 => SysReg::mhpmevent21, + 822 => SysReg::mhpmevent22, + 823 => SysReg::mhpmevent23, + 824 => SysReg::mhpmevent24, + 825 => SysReg::mhpmevent25, + 826 => SysReg::mhpmevent26, + 827 => SysReg::mhpmevent27, + 828 => SysReg::mhpmevent28, + 829 => SysReg::mhpmevent29, + 830 => SysReg::mhpmevent30, + 831 => SysReg::mhpmevent31, + 832 => SysReg::mscratch, + 833 => SysReg::mepc, + 834 => SysReg::mcause, + 835 => SysReg::mbadaddr, + 836 => SysReg::mip, + 837 => SysReg::sf_mnxti, + 838 => SysReg::sf_mintstatus, + 840 => SysReg::sf_mscratchcsw, + 841 => SysReg::sf_mscratchcswl, + 842 => SysReg::mtinst, + 843 => SysReg::mtval2, + 846 => SysReg::mctrctl, + 848 => SysReg::miselect, + 849 => SysReg::mireg, + 850 => SysReg::mireg2, + 851 => SysReg::mireg3, + 852 => SysReg::miph, + 853 => SysReg::mireg4, + 854 => SysReg::mireg5, + 855 => SysReg::mireg6, + 860 => SysReg::mtopei, + 928 => SysReg::pmpcfg0, + 929 => SysReg::pmpcfg1, + 930 => SysReg::pmpcfg2, + 931 => SysReg::pmpcfg3, + 932 => SysReg::pmpcfg4, + 933 => SysReg::pmpcfg5, + 934 => SysReg::pmpcfg6, + 935 => SysReg::pmpcfg7, + 936 => SysReg::pmpcfg8, + 937 => SysReg::pmpcfg9, + 938 => SysReg::pmpcfg10, + 939 => SysReg::pmpcfg11, + 940 => SysReg::pmpcfg12, + 941 => SysReg::pmpcfg13, + 942 => SysReg::pmpcfg14, + 943 => SysReg::pmpcfg15, + 944 => SysReg::pmpaddr0, + 945 => SysReg::pmpaddr1, + 946 => SysReg::pmpaddr2, + 947 => SysReg::pmpaddr3, + 948 => SysReg::pmpaddr4, + 949 => SysReg::pmpaddr5, + 950 => SysReg::pmpaddr6, + 951 => SysReg::pmpaddr7, + 952 => SysReg::pmpaddr8, + 953 => SysReg::pmpaddr9, + 954 => SysReg::pmpaddr10, + 955 => SysReg::pmpaddr11, + 956 => SysReg::pmpaddr12, + 957 => SysReg::pmpaddr13, + 958 => SysReg::pmpaddr14, + 959 => SysReg::pmpaddr15, + 960 => SysReg::pmpaddr16, + 961 => SysReg::pmpaddr17, + 962 => SysReg::pmpaddr18, + 963 => SysReg::pmpaddr19, + 964 => SysReg::pmpaddr20, + 965 => SysReg::pmpaddr21, + 966 => SysReg::pmpaddr22, + 967 => SysReg::pmpaddr23, + 968 => SysReg::pmpaddr24, + 969 => SysReg::pmpaddr25, + 970 => SysReg::pmpaddr26, + 971 => SysReg::pmpaddr27, + 972 => SysReg::pmpaddr28, + 973 => SysReg::pmpaddr29, + 974 => SysReg::pmpaddr30, + 975 => SysReg::pmpaddr31, + 976 => SysReg::pmpaddr32, + 977 => SysReg::pmpaddr33, + 978 => SysReg::pmpaddr34, + 979 => SysReg::pmpaddr35, + 980 => SysReg::pmpaddr36, + 981 => SysReg::pmpaddr37, + 982 => SysReg::pmpaddr38, + 983 => SysReg::pmpaddr39, + 984 => SysReg::pmpaddr40, + 985 => SysReg::pmpaddr41, + 986 => SysReg::pmpaddr42, + 987 => SysReg::pmpaddr43, + 988 => SysReg::pmpaddr44, + 989 => SysReg::pmpaddr45, + 990 => SysReg::pmpaddr46, + 991 => SysReg::pmpaddr47, + 992 => SysReg::pmpaddr48, + 993 => SysReg::pmpaddr49, + 994 => SysReg::pmpaddr50, + 995 => SysReg::pmpaddr51, + 996 => SysReg::pmpaddr52, + 997 => SysReg::pmpaddr53, + 998 => SysReg::pmpaddr54, + 999 => SysReg::pmpaddr55, + 1000 => SysReg::pmpaddr56, + 1001 => SysReg::pmpaddr57, + 1002 => SysReg::pmpaddr58, + 1003 => SysReg::pmpaddr59, + 1004 => SysReg::pmpaddr60, + 1005 => SysReg::pmpaddr61, + 1006 => SysReg::pmpaddr62, + 1007 => SysReg::pmpaddr63, + 1448 => SysReg::scontext, + 1536 => SysReg::hstatus, + 1538 => SysReg::hedeleg, + 1539 => SysReg::hideleg, + 1540 => SysReg::hie, + 1541 => SysReg::htimedelta, + 1542 => SysReg::hcounteren, + 1543 => SysReg::hgeie, + 1544 => SysReg::hvien, + 1545 => SysReg::hvictl, + 1546 => SysReg::henvcfg, + 1548 => SysReg::hstateen0, + 1549 => SysReg::hstateen1, + 1550 => SysReg::hstateen2, + 1551 => SysReg::hstateen3, + 1554 => SysReg::hedelegh, + 1555 => SysReg::hidelegh, + 1557 => SysReg::htimedeltah, + 1560 => SysReg::hvienh, + 1562 => SysReg::henvcfgh, + 1564 => SysReg::hstateen0h, + 1565 => SysReg::hstateen1h, + 1566 => SysReg::hstateen2h, + 1567 => SysReg::hstateen3h, + 1603 => SysReg::htval, + 1604 => SysReg::hip, + 1605 => SysReg::hvip, + 1606 => SysReg::hviprio1, + 1607 => SysReg::hviprio2, + 1610 => SysReg::htinst, + 1621 => SysReg::hviph, + 1622 => SysReg::hviprio1h, + 1623 => SysReg::hviprio2h, + 1664 => SysReg::hgatp, + 1704 => SysReg::hcontext, + 1825 => SysReg::mcyclecfgh, + 1826 => SysReg::minstretcfgh, + 1827 => SysReg::mhpmevent3h, + 1828 => SysReg::mhpmevent4h, + 1829 => SysReg::mhpmevent5h, + 1830 => SysReg::mhpmevent6h, + 1831 => SysReg::mhpmevent7h, + 1832 => SysReg::mhpmevent8h, + 1833 => SysReg::mhpmevent9h, + 1834 => SysReg::mhpmevent10h, + 1835 => SysReg::mhpmevent11h, + 1836 => SysReg::mhpmevent12h, + 1837 => SysReg::mhpmevent13h, + 1838 => SysReg::mhpmevent14h, + 1839 => SysReg::mhpmevent15h, + 1840 => SysReg::mhpmevent16h, + 1841 => SysReg::mhpmevent17h, + 1842 => SysReg::mhpmevent18h, + 1843 => SysReg::mhpmevent19h, + 1844 => SysReg::mhpmevent20h, + 1845 => SysReg::mhpmevent21h, + 1846 => SysReg::mhpmevent22h, + 1847 => SysReg::mhpmevent23h, + 1848 => SysReg::mhpmevent24h, + 1849 => SysReg::mhpmevent25h, + 1850 => SysReg::mhpmevent26h, + 1851 => SysReg::mhpmevent27h, + 1852 => SysReg::mhpmevent28h, + 1853 => SysReg::mhpmevent29h, + 1854 => SysReg::mhpmevent30h, + 1855 => SysReg::mhpmevent31h, + 1856 => SysReg::mnscratch, + 1857 => SysReg::mnepc, + 1858 => SysReg::mncause, + 1860 => SysReg::mnstatus, + 1863 => SysReg::mseccfg, + 1879 => SysReg::mseccfgh, + 1952 => SysReg::tselect, + 1953 => SysReg::etrigger, + 1954 => SysReg::tdata2, + 1955 => SysReg::tdata3, + 1956 => SysReg::tinfo, + 1957 => SysReg::tcontrol, + 1960 => SysReg::mcontext, + 1962 => SysReg::mscontext, + 1968 => SysReg::dcsr, + 1969 => SysReg::dpc, + 1970 => SysReg::dscratch, + 1971 => SysReg::dscratch1, + 1984 => SysReg::qc_mmcr, + 1987 => SysReg::qc_mntvec, + 1988 => SysReg::qc_mstktopaddr, + 1989 => SysReg::qc_mstkbottomaddr, + 1992 => SysReg::qc_mthreadptr, + 1993 => SysReg::qc_mcause, + 2000 => SysReg::qc_mwpstartaddr0, + 2001 => SysReg::qc_mwpstartaddr1, + 2002 => SysReg::qc_mwpstartaddr2, + 2003 => SysReg::qc_mwpstartaddr3, + 2004 => SysReg::qc_mwpendaddr0, + 2005 => SysReg::qc_mwpendaddr1, + 2006 => SysReg::qc_mwpendaddr2, + 2007 => SysReg::qc_mwpendaddr3, + 2032 => SysReg::qc_mclicip0, + 2033 => SysReg::qc_mclicip1, + 2034 => SysReg::qc_mclicip2, + 2035 => SysReg::qc_mclicip3, + 2036 => SysReg::qc_mclicip4, + 2037 => SysReg::qc_mclicip5, + 2038 => SysReg::qc_mclicip6, + 2039 => SysReg::qc_mclicip7, + 2040 => SysReg::qc_mclicie0, + 2041 => SysReg::qc_mclicie1, + 2042 => SysReg::qc_mclicie2, + 2043 => SysReg::qc_mclicie3, + 2044 => SysReg::qc_mclicie4, + 2045 => SysReg::qc_mclicie5, + 2046 => SysReg::qc_mclicie6, + 2047 => SysReg::qc_mclicie7, + 2816 => SysReg::mcycle, + 2818 => SysReg::minstret, + 2819 => SysReg::mhpmcounter3, + 2820 => SysReg::mhpmcounter4, + 2821 => SysReg::mhpmcounter5, + 2822 => SysReg::mhpmcounter6, + 2823 => SysReg::mhpmcounter7, + 2824 => SysReg::mhpmcounter8, + 2825 => SysReg::mhpmcounter9, + 2826 => SysReg::mhpmcounter10, + 2827 => SysReg::mhpmcounter11, + 2828 => SysReg::mhpmcounter12, + 2829 => SysReg::mhpmcounter13, + 2830 => SysReg::mhpmcounter14, + 2831 => SysReg::mhpmcounter15, + 2832 => SysReg::mhpmcounter16, + 2833 => SysReg::mhpmcounter17, + 2834 => SysReg::mhpmcounter18, + 2835 => SysReg::mhpmcounter19, + 2836 => SysReg::mhpmcounter20, + 2837 => SysReg::mhpmcounter21, + 2838 => SysReg::mhpmcounter22, + 2839 => SysReg::mhpmcounter23, + 2840 => SysReg::mhpmcounter24, + 2841 => SysReg::mhpmcounter25, + 2842 => SysReg::mhpmcounter26, + 2843 => SysReg::mhpmcounter27, + 2844 => SysReg::mhpmcounter28, + 2845 => SysReg::mhpmcounter29, + 2846 => SysReg::mhpmcounter30, + 2847 => SysReg::mhpmcounter31, + 2944 => SysReg::mcycleh, + 2946 => SysReg::minstreth, + 2947 => SysReg::mhpmcounter3h, + 2948 => SysReg::mhpmcounter4h, + 2949 => SysReg::mhpmcounter5h, + 2950 => SysReg::mhpmcounter6h, + 2951 => SysReg::mhpmcounter7h, + 2952 => SysReg::mhpmcounter8h, + 2953 => SysReg::mhpmcounter9h, + 2954 => SysReg::mhpmcounter10h, + 2955 => SysReg::mhpmcounter11h, + 2956 => SysReg::mhpmcounter12h, + 2957 => SysReg::mhpmcounter13h, + 2958 => SysReg::mhpmcounter14h, + 2959 => SysReg::mhpmcounter15h, + 2960 => SysReg::mhpmcounter16h, + 2961 => SysReg::mhpmcounter17h, + 2962 => SysReg::mhpmcounter18h, + 2963 => SysReg::mhpmcounter19h, + 2964 => SysReg::mhpmcounter20h, + 2965 => SysReg::mhpmcounter21h, + 2966 => SysReg::mhpmcounter22h, + 2967 => SysReg::mhpmcounter23h, + 2968 => SysReg::mhpmcounter24h, + 2969 => SysReg::mhpmcounter25h, + 2970 => SysReg::mhpmcounter26h, + 2971 => SysReg::mhpmcounter27h, + 2972 => SysReg::mhpmcounter28h, + 2973 => SysReg::mhpmcounter29h, + 2974 => SysReg::mhpmcounter30h, + 2975 => SysReg::mhpmcounter31h, + 3008 => SysReg::qc_mclicilvl00, + 3009 => SysReg::qc_mclicilvl01, + 3010 => SysReg::qc_mclicilvl02, + 3011 => SysReg::qc_mclicilvl03, + 3012 => SysReg::qc_mclicilvl04, + 3013 => SysReg::qc_mclicilvl05, + 3014 => SysReg::qc_mclicilvl06, + 3015 => SysReg::qc_mclicilvl07, + 3016 => SysReg::qc_mclicilvl08, + 3017 => SysReg::qc_mclicilvl09, + 3018 => SysReg::qc_mclicilvl10, + 3019 => SysReg::qc_mclicilvl11, + 3020 => SysReg::qc_mclicilvl12, + 3021 => SysReg::qc_mclicilvl13, + 3022 => SysReg::qc_mclicilvl14, + 3023 => SysReg::qc_mclicilvl15, + 3024 => SysReg::qc_mclicilvl16, + 3025 => SysReg::qc_mclicilvl17, + 3026 => SysReg::qc_mclicilvl18, + 3027 => SysReg::qc_mclicilvl19, + 3028 => SysReg::qc_mclicilvl20, + 3029 => SysReg::qc_mclicilvl21, + 3030 => SysReg::qc_mclicilvl22, + 3031 => SysReg::qc_mclicilvl23, + 3032 => SysReg::qc_mclicilvl24, + 3033 => SysReg::qc_mclicilvl25, + 3034 => SysReg::qc_mclicilvl26, + 3035 => SysReg::qc_mclicilvl27, + 3036 => SysReg::qc_mclicilvl28, + 3037 => SysReg::qc_mclicilvl29, + 3038 => SysReg::qc_mclicilvl30, + 3039 => SysReg::qc_mclicilvl31, + 3072 => SysReg::cycle, + 3073 => SysReg::time, + 3074 => SysReg::instret, + 3075 => SysReg::hpmcounter3, + 3076 => SysReg::hpmcounter4, + 3077 => SysReg::hpmcounter5, + 3078 => SysReg::hpmcounter6, + 3079 => SysReg::hpmcounter7, + 3080 => SysReg::hpmcounter8, + 3081 => SysReg::hpmcounter9, + 3082 => SysReg::hpmcounter10, + 3083 => SysReg::hpmcounter11, + 3084 => SysReg::hpmcounter12, + 3085 => SysReg::hpmcounter13, + 3086 => SysReg::hpmcounter14, + 3087 => SysReg::hpmcounter15, + 3088 => SysReg::hpmcounter16, + 3089 => SysReg::hpmcounter17, + 3090 => SysReg::hpmcounter18, + 3091 => SysReg::hpmcounter19, + 3092 => SysReg::hpmcounter20, + 3093 => SysReg::hpmcounter21, + 3094 => SysReg::hpmcounter22, + 3095 => SysReg::hpmcounter23, + 3096 => SysReg::hpmcounter24, + 3097 => SysReg::hpmcounter25, + 3098 => SysReg::hpmcounter26, + 3099 => SysReg::hpmcounter27, + 3100 => SysReg::hpmcounter28, + 3101 => SysReg::hpmcounter29, + 3102 => SysReg::hpmcounter30, + 3103 => SysReg::hpmcounter31, + 3104 => SysReg::vl, + 3105 => SysReg::vtype, + 3106 => SysReg::vlenb, + 3200 => SysReg::cycleh, + 3201 => SysReg::timeh, + 3202 => SysReg::instreth, + 3203 => SysReg::hpmcounter3h, + 3204 => SysReg::hpmcounter4h, + 3205 => SysReg::hpmcounter5h, + 3206 => SysReg::hpmcounter6h, + 3207 => SysReg::hpmcounter7h, + 3208 => SysReg::hpmcounter8h, + 3209 => SysReg::hpmcounter9h, + 3210 => SysReg::hpmcounter10h, + 3211 => SysReg::hpmcounter11h, + 3212 => SysReg::hpmcounter12h, + 3213 => SysReg::hpmcounter13h, + 3214 => SysReg::hpmcounter14h, + 3215 => SysReg::hpmcounter15h, + 3216 => SysReg::hpmcounter16h, + 3217 => SysReg::hpmcounter17h, + 3218 => SysReg::hpmcounter18h, + 3219 => SysReg::hpmcounter19h, + 3220 => SysReg::hpmcounter20h, + 3221 => SysReg::hpmcounter21h, + 3222 => SysReg::hpmcounter22h, + 3223 => SysReg::hpmcounter23h, + 3224 => SysReg::hpmcounter24h, + 3225 => SysReg::hpmcounter25h, + 3226 => SysReg::hpmcounter26h, + 3227 => SysReg::hpmcounter27h, + 3228 => SysReg::hpmcounter28h, + 3229 => SysReg::hpmcounter29h, + 3230 => SysReg::hpmcounter30h, + 3231 => SysReg::hpmcounter31h, + 3488 => SysReg::scountovf, + 3504 => SysReg::stopi, + 3602 => SysReg::hgeip, + 3760 => SysReg::vstopi, + 3857 => SysReg::mvendorid, + 3858 => SysReg::marchid, + 3859 => SysReg::mimpid, + 3860 => SysReg::mhartid, + 3861 => SysReg::mconfigptr, + 4016 => SysReg::mtopi, + 513 => SysReg::NUM_TARGET_SYSREGS, + _ => SysReg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86.rs new file mode 100644 index 0000000..b6c7cf9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86.rs @@ -0,0 +1,18 @@ +//! x86/x86-64 architecture-related namespace + +pub mod instruction; +pub mod opcodes; +pub mod operands; +pub mod registers; + +#[doc(inline)] +pub use opcodes::Opcode; + +#[doc(inline)] +pub use instruction::Instruction; + +#[doc(inline)] +pub use operands::Operands; + +#[doc(inline)] +pub use operands::Operand; diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/instruction.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/instruction.rs new file mode 100644 index 0000000..177c976 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/instruction.rs @@ -0,0 +1,82 @@ +use lief_ffi as ffi; + +use super::Opcode; +use crate::assembly; +use crate::common::{FromFFI, into_optional}; + +use crate::assembly::x86; +use crate::declare_fwd_iterator; + +/// This structure represents a x86/x86-64 instruction +pub struct Instruction { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Instruction { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl assembly::Instruction for Instruction { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_Instruction { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for Instruction { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", assembly::Instruction::as_generic(self).to_string()) + } +} + +impl Instruction { + /// The instruction opcode as defined in LLVM + pub fn opcode(&self) -> Opcode { + Opcode::from(self.ptr.opcode()) + } + + /// Return an iterator over the [`x86::Operands`] operands + pub fn operands(&self) -> Operands<'_> { + Operands::new(self.ptr.operands()) + } + + /// True if this instruction has a `LOCK` prefix + pub fn has_lock_prefix(&self) -> bool { + self.ptr.has_lock_prefix() + } + + /// True if the `LOCK` prefix is architecturally valid on this instruction + pub fn is_lockable(&self) -> bool { + self.ptr.is_lockable() + } + + /// True if this instruction executes as an atomic read-modify-write + pub fn is_atomic(&self) -> bool { + self.ptr.is_atomic() + } + + /// Re-encoded copy of this instruction with a `LOCK` prefix added. + /// + /// If the instruction already has a `LOCK` prefix, it returns a plain copy. + pub fn lock(&self) -> Option { + into_optional(self.ptr.lock()) + } + + /// Re-encoded copy of this instruction with the `LOCK` prefix removed. + /// + /// If the instruction does not have a `LOCK` prefix, it returns a plain + /// copy or `None` if the `LOCK` semantic can't be removed. + pub fn unlock(&self) -> Option { + into_optional(self.ptr.unlock()) + } +} + +declare_fwd_iterator!( + Operands, + x86::Operands, + ffi::asm_Instruction, + ffi::asm_x86_Operand, + ffi::asm_x86_Instruction_it_operands +); diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/opcodes.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/opcodes.rs new file mode 100644 index 0000000..4924732 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/opcodes.rs @@ -0,0 +1,44605 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Opcode { + PHI, + INLINEASM, + INLINEASM_BR, + CFI_INSTRUCTION, + EH_LABEL, + GC_LABEL, + ANNOTATION_LABEL, + KILL, + EXTRACT_SUBREG, + INSERT_SUBREG, + IMPLICIT_DEF, + INIT_UNDEF, + SUBREG_TO_REG, + COPY_TO_REGCLASS, + DBG_VALUE, + DBG_VALUE_LIST, + DBG_INSTR_REF, + DBG_PHI, + DBG_LABEL, + REG_SEQUENCE, + COPY, + COPY_LANEMASK, + BUNDLE, + LIFETIME_START, + LIFETIME_END, + PSEUDO_PROBE, + ARITH_FENCE, + STACKMAP, + FENTRY_CALL, + PATCHPOINT, + LOAD_STACK_GUARD, + PREALLOCATED_SETUP, + PREALLOCATED_ARG, + STATEPOINT, + LOCAL_ESCAPE, + FAULTING_OP, + PATCHABLE_OP, + PATCHABLE_FUNCTION_ENTER, + PATCHABLE_RET, + PATCHABLE_FUNCTION_EXIT, + PATCHABLE_TAIL_CALL, + PATCHABLE_EVENT_CALL, + PATCHABLE_TYPED_EVENT_CALL, + ICALL_BRANCH_FUNNEL, + FAKE_USE, + MEMBARRIER, + JUMP_TABLE_DEBUG_INFO, + RELOC_NONE, + CONVERGENCECTRL_ENTRY, + CONVERGENCECTRL_ANCHOR, + CONVERGENCECTRL_LOOP, + CONVERGENCECTRL_GLUE, + G_ASSERT_SEXT, + G_ASSERT_ZEXT, + G_ASSERT_ALIGN, + G_ADD, + G_SUB, + G_MUL, + G_SDIV, + G_UDIV, + G_SREM, + G_UREM, + G_SDIVREM, + G_UDIVREM, + G_AND, + G_OR, + G_XOR, + G_ABDS, + G_ABDU, + G_UAVGFLOOR, + G_UAVGCEIL, + G_SAVGFLOOR, + G_SAVGCEIL, + G_IMPLICIT_DEF, + G_PHI, + G_FRAME_INDEX, + G_GLOBAL_VALUE, + G_PTRAUTH_GLOBAL_VALUE, + G_CONSTANT_POOL, + G_EXTRACT, + G_UNMERGE_VALUES, + G_INSERT, + G_MERGE_VALUES, + G_BUILD_VECTOR, + G_BUILD_VECTOR_TRUNC, + G_CONCAT_VECTORS, + G_PTRTOINT, + G_INTTOPTR, + G_BITCAST, + G_FREEZE, + G_CONSTANT_FOLD_BARRIER, + G_INTRINSIC_FPTRUNC_ROUND, + G_INTRINSIC_TRUNC, + G_INTRINSIC_ROUND, + G_INTRINSIC_LRINT, + G_INTRINSIC_LLRINT, + G_INTRINSIC_ROUNDEVEN, + G_READCYCLECOUNTER, + G_READSTEADYCOUNTER, + G_LOAD, + G_SEXTLOAD, + G_ZEXTLOAD, + G_INDEXED_LOAD, + G_INDEXED_SEXTLOAD, + G_INDEXED_ZEXTLOAD, + G_STORE, + G_INDEXED_STORE, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, + G_ATOMIC_CMPXCHG, + G_ATOMICRMW_XCHG, + G_ATOMICRMW_ADD, + G_ATOMICRMW_SUB, + G_ATOMICRMW_AND, + G_ATOMICRMW_NAND, + G_ATOMICRMW_OR, + G_ATOMICRMW_XOR, + G_ATOMICRMW_MAX, + G_ATOMICRMW_MIN, + G_ATOMICRMW_UMAX, + G_ATOMICRMW_UMIN, + G_ATOMICRMW_FADD, + G_ATOMICRMW_FSUB, + G_ATOMICRMW_FMAX, + G_ATOMICRMW_FMIN, + G_ATOMICRMW_FMAXIMUM, + G_ATOMICRMW_FMINIMUM, + G_ATOMICRMW_UINC_WRAP, + G_ATOMICRMW_UDEC_WRAP, + G_ATOMICRMW_USUB_COND, + G_ATOMICRMW_USUB_SAT, + G_FENCE, + G_PREFETCH, + G_BRCOND, + G_BRINDIRECT, + G_INVOKE_REGION_START, + G_INTRINSIC, + G_INTRINSIC_W_SIDE_EFFECTS, + G_INTRINSIC_CONVERGENT, + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + G_ANYEXT, + G_TRUNC, + G_TRUNC_SSAT_S, + G_TRUNC_SSAT_U, + G_TRUNC_USAT_U, + G_CONSTANT, + G_FCONSTANT, + G_VASTART, + G_VAARG, + G_SEXT, + G_SEXT_INREG, + G_ZEXT, + G_SHL, + G_LSHR, + G_ASHR, + G_FSHL, + G_FSHR, + G_ROTR, + G_ROTL, + G_ICMP, + G_FCMP, + G_SCMP, + G_UCMP, + G_SELECT, + G_UADDO, + G_UADDE, + G_USUBO, + G_USUBE, + G_SADDO, + G_SADDE, + G_SSUBO, + G_SSUBE, + G_UMULO, + G_SMULO, + G_UMULH, + G_SMULH, + G_UADDSAT, + G_SADDSAT, + G_USUBSAT, + G_SSUBSAT, + G_USHLSAT, + G_SSHLSAT, + G_SMULFIX, + G_UMULFIX, + G_SMULFIXSAT, + G_UMULFIXSAT, + G_SDIVFIX, + G_UDIVFIX, + G_SDIVFIXSAT, + G_UDIVFIXSAT, + G_FADD, + G_FSUB, + G_FMUL, + G_FMA, + G_FMAD, + G_FDIV, + G_FREM, + G_FMODF, + G_FPOW, + G_FPOWI, + G_FEXP, + G_FEXP2, + G_FEXP10, + G_FLOG, + G_FLOG2, + G_FLOG10, + G_FLDEXP, + G_FFREXP, + G_FNEG, + G_FPEXT, + G_FPTRUNC, + G_FPTOSI, + G_FPTOUI, + G_SITOFP, + G_UITOFP, + G_FPTOSI_SAT, + G_FPTOUI_SAT, + G_FABS, + G_FCOPYSIGN, + G_IS_FPCLASS, + G_FCANONICALIZE, + G_FMINNUM, + G_FMAXNUM, + G_FMINNUM_IEEE, + G_FMAXNUM_IEEE, + G_FMINIMUM, + G_FMAXIMUM, + G_FMINIMUMNUM, + G_FMAXIMUMNUM, + G_GET_FPENV, + G_SET_FPENV, + G_RESET_FPENV, + G_GET_FPMODE, + G_SET_FPMODE, + G_RESET_FPMODE, + G_GET_ROUNDING, + G_SET_ROUNDING, + G_PTR_ADD, + G_PTRMASK, + G_SMIN, + G_SMAX, + G_UMIN, + G_UMAX, + G_ABS, + G_LROUND, + G_LLROUND, + G_BR, + G_BRJT, + G_VSCALE, + G_INSERT_SUBVECTOR, + G_EXTRACT_SUBVECTOR, + G_INSERT_VECTOR_ELT, + G_EXTRACT_VECTOR_ELT, + G_SHUFFLE_VECTOR, + G_SPLAT_VECTOR, + G_STEP_VECTOR, + G_VECTOR_COMPRESS, + G_CTTZ, + G_CTTZ_ZERO_UNDEF, + G_CTLZ, + G_CTLZ_ZERO_UNDEF, + G_CTPOP, + G_BSWAP, + G_BITREVERSE, + G_FCEIL, + G_FCOS, + G_FSIN, + G_FSINCOS, + G_FTAN, + G_FACOS, + G_FASIN, + G_FATAN, + G_FATAN2, + G_FCOSH, + G_FSINH, + G_FTANH, + G_FSQRT, + G_FFLOOR, + G_FRINT, + G_FNEARBYINT, + G_ADDRSPACE_CAST, + G_BLOCK_ADDR, + G_JUMP_TABLE, + G_DYN_STACKALLOC, + G_STACKSAVE, + G_STACKRESTORE, + G_STRICT_FADD, + G_STRICT_FSUB, + G_STRICT_FMUL, + G_STRICT_FDIV, + G_STRICT_FREM, + G_STRICT_FMA, + G_STRICT_FSQRT, + G_STRICT_FLDEXP, + G_READ_REGISTER, + G_WRITE_REGISTER, + G_MEMCPY, + G_MEMCPY_INLINE, + G_MEMMOVE, + G_MEMSET, + G_BZERO, + G_TRAP, + G_DEBUGTRAP, + G_UBSANTRAP, + G_VECREDUCE_SEQ_FADD, + G_VECREDUCE_SEQ_FMUL, + G_VECREDUCE_FADD, + G_VECREDUCE_FMUL, + G_VECREDUCE_FMAX, + G_VECREDUCE_FMIN, + G_VECREDUCE_FMAXIMUM, + G_VECREDUCE_FMINIMUM, + G_VECREDUCE_ADD, + G_VECREDUCE_MUL, + G_VECREDUCE_AND, + G_VECREDUCE_OR, + G_VECREDUCE_XOR, + G_VECREDUCE_SMAX, + G_VECREDUCE_SMIN, + G_VECREDUCE_UMAX, + G_VECREDUCE_UMIN, + G_SBFX, + G_UBFX, + ADD16ri_DB, + ADD16rr_DB, + ADD32ri_DB, + ADD32rr_DB, + ADD64ri32_DB, + ADD64rr_DB, + ADD8ri_DB, + ADD8rr_DB, + AVX1_SETALLONES, + AVX2_SETALLONES, + AVX512_128_SET0, + AVX512_128_SETALLONES, + AVX512_256_SET0, + AVX512_256_SETALLONES, + AVX512_512_SET0, + AVX512_512_SETALLONES, + AVX512_512_SEXT_MASK_32, + AVX512_512_SEXT_MASK_64, + AVX512_FsFLD0F128, + AVX512_FsFLD0SD, + AVX512_FsFLD0SH, + AVX512_FsFLD0SS, + AVX_SET0, + CALL64m_RVMARKER, + CALL64pcrel32_RVMARKER, + CALL64r_ImpCall, + CALL64r_RVMARKER, + FsFLD0F128, + FsFLD0SD, + FsFLD0SH, + FsFLD0SS, + G_FILD, + G_FIST, + G_FLDCW16, + G_FNSTCW16, + INDIRECT_THUNK_CALL32, + INDIRECT_THUNK_CALL64, + INDIRECT_THUNK_TCRETURN32, + INDIRECT_THUNK_TCRETURN64, + KSET0B, + KSET0D, + KSET0Q, + KSET0W, + KSET1B, + KSET1D, + KSET1Q, + KSET1W, + LCMPXCHG16B_NO_RBX, + LCMPXCHG16B_SAVE_RBX, + MMX_SET0, + MORESTACK_RET, + MORESTACK_RET_RESTORE_R10, + MOV32ImmSExti8, + MOV32r0, + MOV32r1, + MOV32r_1, + MOV32ri64, + MOV64ImmSExti8, + MOVSHPmr, + MOVSHPrm, + MWAITX, + MWAITX_SAVE_RBX, + PLDTILECFGV, + PLEA32r, + PLEA64r, + PTDPBF16PSV, + PTDPBSSDV, + PTDPBSUDV, + PTDPBUSDV, + PTDPBUUDV, + PTDPFP16PSV, + PTILELOADDRST1V, + PTILELOADDRSV, + PTILELOADDT1V, + PTILELOADDV, + PTILESTOREDV, + PTILEZEROV, + RDFLAGS32, + RDFLAGS64, + SEH_BeginEpilogue, + SEH_EndEpilogue, + SEH_EndPrologue, + SEH_PushFrame, + SEH_PushReg, + SEH_SaveReg, + SEH_SaveXMM, + SEH_SetFrame, + SEH_StackAlign, + SEH_StackAlloc, + SEH_UnwindV2Start, + SEH_UnwindVersion, + SETB_C32r, + SETB_C64r, + SHLDROT32ri, + SHLDROT64ri, + SHRDROT32ri, + SHRDROT64ri, + VMOVAPSZ128mr_NOVLX, + VMOVAPSZ128rm_NOVLX, + VMOVAPSZ256mr_NOVLX, + VMOVAPSZ256rm_NOVLX, + VMOVUPSZ128mr_NOVLX, + VMOVUPSZ128rm_NOVLX, + VMOVUPSZ256mr_NOVLX, + VMOVUPSZ256rm_NOVLX, + V_SET0, + V_SETALLONES, + WRFLAGS32, + WRFLAGS64, + XABORT_DEF, + XOR32_FP, + XOR64_FP, + AAA, + AAD8i8, + AADD32mr, + AADD32mr_EVEX, + AADD64mr, + AADD64mr_EVEX, + AAM8i8, + AAND32mr, + AAND32mr_EVEX, + AAND64mr, + AAND64mr_EVEX, + AAS, + ABS_F, + ABS_Fp32, + ABS_Fp64, + ABS_Fp80, + ADC16i16, + ADC16mi, + ADC16mi8, + ADC16mi8_EVEX, + ADC16mi8_ND, + ADC16mi_EVEX, + ADC16mi_ND, + ADC16mr, + ADC16mr_EVEX, + ADC16mr_ND, + ADC16ri, + ADC16ri8, + ADC16ri8_EVEX, + ADC16ri8_ND, + ADC16ri_EVEX, + ADC16ri_ND, + ADC16rm, + ADC16rm_EVEX, + ADC16rm_ND, + ADC16rr, + ADC16rr_EVEX, + ADC16rr_EVEX_REV, + ADC16rr_ND, + ADC16rr_ND_REV, + ADC16rr_REV, + ADC32i32, + ADC32mi, + ADC32mi8, + ADC32mi8_EVEX, + ADC32mi8_ND, + ADC32mi_EVEX, + ADC32mi_ND, + ADC32mr, + ADC32mr_EVEX, + ADC32mr_ND, + ADC32ri, + ADC32ri8, + ADC32ri8_EVEX, + ADC32ri8_ND, + ADC32ri_EVEX, + ADC32ri_ND, + ADC32rm, + ADC32rm_EVEX, + ADC32rm_ND, + ADC32rr, + ADC32rr_EVEX, + ADC32rr_EVEX_REV, + ADC32rr_ND, + ADC32rr_ND_REV, + ADC32rr_REV, + ADC64i32, + ADC64mi32, + ADC64mi32_EVEX, + ADC64mi32_ND, + ADC64mi8, + ADC64mi8_EVEX, + ADC64mi8_ND, + ADC64mr, + ADC64mr_EVEX, + ADC64mr_ND, + ADC64ri32, + ADC64ri32_EVEX, + ADC64ri32_ND, + ADC64ri8, + ADC64ri8_EVEX, + ADC64ri8_ND, + ADC64rm, + ADC64rm_EVEX, + ADC64rm_ND, + ADC64rr, + ADC64rr_EVEX, + ADC64rr_EVEX_REV, + ADC64rr_ND, + ADC64rr_ND_REV, + ADC64rr_REV, + ADC8i8, + ADC8mi, + ADC8mi8, + ADC8mi_EVEX, + ADC8mi_ND, + ADC8mr, + ADC8mr_EVEX, + ADC8mr_ND, + ADC8ri, + ADC8ri8, + ADC8ri_EVEX, + ADC8ri_ND, + ADC8rm, + ADC8rm_EVEX, + ADC8rm_ND, + ADC8rr, + ADC8rr_EVEX, + ADC8rr_EVEX_REV, + ADC8rr_ND, + ADC8rr_ND_REV, + ADC8rr_REV, + ADCX32rm, + ADCX32rm_EVEX, + ADCX32rm_ND, + ADCX32rr, + ADCX32rr_EVEX, + ADCX32rr_ND, + ADCX64rm, + ADCX64rm_EVEX, + ADCX64rm_ND, + ADCX64rr, + ADCX64rr_EVEX, + ADCX64rr_ND, + ADD16i16, + ADD16mi, + ADD16mi8, + ADD16mi8_EVEX, + ADD16mi8_ND, + ADD16mi8_NF, + ADD16mi8_NF_ND, + ADD16mi_EVEX, + ADD16mi_ND, + ADD16mi_NF, + ADD16mi_NF_ND, + ADD16mr, + ADD16mr_EVEX, + ADD16mr_ND, + ADD16mr_NF, + ADD16mr_NF_ND, + ADD16ri, + ADD16ri8, + ADD16ri8_EVEX, + ADD16ri8_ND, + ADD16ri8_NF, + ADD16ri8_NF_ND, + ADD16ri_EVEX, + ADD16ri_ND, + ADD16ri_NF, + ADD16ri_NF_ND, + ADD16rm, + ADD16rm_EVEX, + ADD16rm_ND, + ADD16rm_NF, + ADD16rm_NF_ND, + ADD16rr, + ADD16rr_EVEX, + ADD16rr_EVEX_REV, + ADD16rr_ND, + ADD16rr_ND_REV, + ADD16rr_NF, + ADD16rr_NF_ND, + ADD16rr_NF_ND_REV, + ADD16rr_NF_REV, + ADD16rr_REV, + ADD32i32, + ADD32mi, + ADD32mi8, + ADD32mi8_EVEX, + ADD32mi8_ND, + ADD32mi8_NF, + ADD32mi8_NF_ND, + ADD32mi_EVEX, + ADD32mi_ND, + ADD32mi_NF, + ADD32mi_NF_ND, + ADD32mr, + ADD32mr_EVEX, + ADD32mr_ND, + ADD32mr_NF, + ADD32mr_NF_ND, + ADD32ri, + ADD32ri8, + ADD32ri8_EVEX, + ADD32ri8_ND, + ADD32ri8_NF, + ADD32ri8_NF_ND, + ADD32ri_EVEX, + ADD32ri_ND, + ADD32ri_NF, + ADD32ri_NF_ND, + ADD32rm, + ADD32rm_EVEX, + ADD32rm_ND, + ADD32rm_NF, + ADD32rm_NF_ND, + ADD32rr, + ADD32rr_EVEX, + ADD32rr_EVEX_REV, + ADD32rr_ND, + ADD32rr_ND_REV, + ADD32rr_NF, + ADD32rr_NF_ND, + ADD32rr_NF_ND_REV, + ADD32rr_NF_REV, + ADD32rr_REV, + ADD64i32, + ADD64mi32, + ADD64mi32_EVEX, + ADD64mi32_ND, + ADD64mi32_NF, + ADD64mi32_NF_ND, + ADD64mi8, + ADD64mi8_EVEX, + ADD64mi8_ND, + ADD64mi8_NF, + ADD64mi8_NF_ND, + ADD64mr, + ADD64mr_EVEX, + ADD64mr_ND, + ADD64mr_NF, + ADD64mr_NF_ND, + ADD64ri32, + ADD64ri32_EVEX, + ADD64ri32_ND, + ADD64ri32_NF, + ADD64ri32_NF_ND, + ADD64ri8, + ADD64ri8_EVEX, + ADD64ri8_ND, + ADD64ri8_NF, + ADD64ri8_NF_ND, + ADD64rm, + ADD64rm_EVEX, + ADD64rm_ND, + ADD64rm_NF, + ADD64rm_NF_ND, + ADD64rr, + ADD64rr_EVEX, + ADD64rr_EVEX_REV, + ADD64rr_ND, + ADD64rr_ND_REV, + ADD64rr_NF, + ADD64rr_NF_ND, + ADD64rr_NF_ND_REV, + ADD64rr_NF_REV, + ADD64rr_REV, + ADD8i8, + ADD8mi, + ADD8mi8, + ADD8mi_EVEX, + ADD8mi_ND, + ADD8mi_NF, + ADD8mi_NF_ND, + ADD8mr, + ADD8mr_EVEX, + ADD8mr_ND, + ADD8mr_NF, + ADD8mr_NF_ND, + ADD8ri, + ADD8ri8, + ADD8ri_EVEX, + ADD8ri_ND, + ADD8ri_NF, + ADD8ri_NF_ND, + ADD8rm, + ADD8rm_EVEX, + ADD8rm_ND, + ADD8rm_NF, + ADD8rm_NF_ND, + ADD8rr, + ADD8rr_EVEX, + ADD8rr_EVEX_REV, + ADD8rr_ND, + ADD8rr_ND_REV, + ADD8rr_NF, + ADD8rr_NF_ND, + ADD8rr_NF_ND_REV, + ADD8rr_NF_REV, + ADD8rr_REV, + ADDPDrm, + ADDPDrr, + ADDPSrm, + ADDPSrr, + ADDR16_PREFIX, + ADDR32_PREFIX, + ADDSDrm, + ADDSDrm_Int, + ADDSDrr, + ADDSDrr_Int, + ADDSSrm, + ADDSSrm_Int, + ADDSSrr, + ADDSSrr_Int, + ADDSUBPDrm, + ADDSUBPDrr, + ADDSUBPSrm, + ADDSUBPSrr, + ADD_F32m, + ADD_F64m, + ADD_FI16m, + ADD_FI32m, + ADD_FPrST0, + ADD_FST0r, + ADD_Fp32, + ADD_Fp32m, + ADD_Fp64, + ADD_Fp64m, + ADD_Fp64m32, + ADD_Fp80, + ADD_Fp80m32, + ADD_Fp80m64, + ADD_FpI16m32, + ADD_FpI16m64, + ADD_FpI16m80, + ADD_FpI32m32, + ADD_FpI32m64, + ADD_FpI32m80, + ADD_FrST0, + ADJCALLSTACKDOWN32, + ADJCALLSTACKDOWN64, + ADJCALLSTACKUP32, + ADJCALLSTACKUP64, + ADOX32rm, + ADOX32rm_EVEX, + ADOX32rm_ND, + ADOX32rr, + ADOX32rr_EVEX, + ADOX32rr_ND, + ADOX64rm, + ADOX64rm_EVEX, + ADOX64rm_ND, + ADOX64rr, + ADOX64rr_EVEX, + ADOX64rr_ND, + AESDEC128KL, + AESDEC256KL, + AESDECLASTrm, + AESDECLASTrr, + AESDECWIDE128KL, + AESDECWIDE256KL, + AESDECrm, + AESDECrr, + AESENC128KL, + AESENC256KL, + AESENCLASTrm, + AESENCLASTrr, + AESENCWIDE128KL, + AESENCWIDE256KL, + AESENCrm, + AESENCrr, + AESIMCrm, + AESIMCrr, + AESKEYGENASSISTrmi, + AESKEYGENASSISTrri, + AND16i16, + AND16mi, + AND16mi8, + AND16mi8_EVEX, + AND16mi8_ND, + AND16mi8_NF, + AND16mi8_NF_ND, + AND16mi_EVEX, + AND16mi_ND, + AND16mi_NF, + AND16mi_NF_ND, + AND16mr, + AND16mr_EVEX, + AND16mr_ND, + AND16mr_NF, + AND16mr_NF_ND, + AND16ri, + AND16ri8, + AND16ri8_EVEX, + AND16ri8_ND, + AND16ri8_NF, + AND16ri8_NF_ND, + AND16ri_EVEX, + AND16ri_ND, + AND16ri_NF, + AND16ri_NF_ND, + AND16rm, + AND16rm_EVEX, + AND16rm_ND, + AND16rm_NF, + AND16rm_NF_ND, + AND16rr, + AND16rr_EVEX, + AND16rr_EVEX_REV, + AND16rr_ND, + AND16rr_ND_REV, + AND16rr_NF, + AND16rr_NF_ND, + AND16rr_NF_ND_REV, + AND16rr_NF_REV, + AND16rr_REV, + AND32i32, + AND32mi, + AND32mi8, + AND32mi8_EVEX, + AND32mi8_ND, + AND32mi8_NF, + AND32mi8_NF_ND, + AND32mi_EVEX, + AND32mi_ND, + AND32mi_NF, + AND32mi_NF_ND, + AND32mr, + AND32mr_EVEX, + AND32mr_ND, + AND32mr_NF, + AND32mr_NF_ND, + AND32ri, + AND32ri8, + AND32ri8_EVEX, + AND32ri8_ND, + AND32ri8_NF, + AND32ri8_NF_ND, + AND32ri_EVEX, + AND32ri_ND, + AND32ri_NF, + AND32ri_NF_ND, + AND32rm, + AND32rm_EVEX, + AND32rm_ND, + AND32rm_NF, + AND32rm_NF_ND, + AND32rr, + AND32rr_EVEX, + AND32rr_EVEX_REV, + AND32rr_ND, + AND32rr_ND_REV, + AND32rr_NF, + AND32rr_NF_ND, + AND32rr_NF_ND_REV, + AND32rr_NF_REV, + AND32rr_REV, + AND64i32, + AND64mi32, + AND64mi32_EVEX, + AND64mi32_ND, + AND64mi32_NF, + AND64mi32_NF_ND, + AND64mi8, + AND64mi8_EVEX, + AND64mi8_ND, + AND64mi8_NF, + AND64mi8_NF_ND, + AND64mr, + AND64mr_EVEX, + AND64mr_ND, + AND64mr_NF, + AND64mr_NF_ND, + AND64ri32, + AND64ri32_EVEX, + AND64ri32_ND, + AND64ri32_NF, + AND64ri32_NF_ND, + AND64ri8, + AND64ri8_EVEX, + AND64ri8_ND, + AND64ri8_NF, + AND64ri8_NF_ND, + AND64rm, + AND64rm_EVEX, + AND64rm_ND, + AND64rm_NF, + AND64rm_NF_ND, + AND64rr, + AND64rr_EVEX, + AND64rr_EVEX_REV, + AND64rr_ND, + AND64rr_ND_REV, + AND64rr_NF, + AND64rr_NF_ND, + AND64rr_NF_ND_REV, + AND64rr_NF_REV, + AND64rr_REV, + AND8i8, + AND8mi, + AND8mi8, + AND8mi_EVEX, + AND8mi_ND, + AND8mi_NF, + AND8mi_NF_ND, + AND8mr, + AND8mr_EVEX, + AND8mr_ND, + AND8mr_NF, + AND8mr_NF_ND, + AND8ri, + AND8ri8, + AND8ri_EVEX, + AND8ri_ND, + AND8ri_NF, + AND8ri_NF_ND, + AND8rm, + AND8rm_EVEX, + AND8rm_ND, + AND8rm_NF, + AND8rm_NF_ND, + AND8rr, + AND8rr_EVEX, + AND8rr_EVEX_REV, + AND8rr_ND, + AND8rr_ND_REV, + AND8rr_NF, + AND8rr_NF_ND, + AND8rr_NF_ND_REV, + AND8rr_NF_REV, + AND8rr_REV, + ANDN32rm, + ANDN32rm_EVEX, + ANDN32rm_NF, + ANDN32rr, + ANDN32rr_EVEX, + ANDN32rr_NF, + ANDN64rm, + ANDN64rm_EVEX, + ANDN64rm_NF, + ANDN64rr, + ANDN64rr_EVEX, + ANDN64rr_NF, + ANDNPDrm, + ANDNPDrr, + ANDNPSrm, + ANDNPSrr, + ANDPDrm, + ANDPDrr, + ANDPSrm, + ANDPSrr, + AOR32mr, + AOR32mr_EVEX, + AOR64mr, + AOR64mr_EVEX, + ARPL16mr, + ARPL16rr, + ASAN_CHECK_MEMACCESS, + AXOR32mr, + AXOR32mr_EVEX, + AXOR64mr, + AXOR64mr_EVEX, + BEXTR32rm, + BEXTR32rm_EVEX, + BEXTR32rm_NF, + BEXTR32rr, + BEXTR32rr_EVEX, + BEXTR32rr_NF, + BEXTR64rm, + BEXTR64rm_EVEX, + BEXTR64rm_NF, + BEXTR64rr, + BEXTR64rr_EVEX, + BEXTR64rr_NF, + BEXTRI32mi, + BEXTRI32ri, + BEXTRI64mi, + BEXTRI64ri, + BLCFILL32rm, + BLCFILL32rr, + BLCFILL64rm, + BLCFILL64rr, + BLCI32rm, + BLCI32rr, + BLCI64rm, + BLCI64rr, + BLCIC32rm, + BLCIC32rr, + BLCIC64rm, + BLCIC64rr, + BLCMSK32rm, + BLCMSK32rr, + BLCMSK64rm, + BLCMSK64rr, + BLCS32rm, + BLCS32rr, + BLCS64rm, + BLCS64rr, + BLENDPDrmi, + BLENDPDrri, + BLENDPSrmi, + BLENDPSrri, + BLENDVPDrm0, + BLENDVPDrr0, + BLENDVPSrm0, + BLENDVPSrr0, + BLSFILL32rm, + BLSFILL32rr, + BLSFILL64rm, + BLSFILL64rr, + BLSI32rm, + BLSI32rm_EVEX, + BLSI32rm_NF, + BLSI32rr, + BLSI32rr_EVEX, + BLSI32rr_NF, + BLSI64rm, + BLSI64rm_EVEX, + BLSI64rm_NF, + BLSI64rr, + BLSI64rr_EVEX, + BLSI64rr_NF, + BLSIC32rm, + BLSIC32rr, + BLSIC64rm, + BLSIC64rr, + BLSMSK32rm, + BLSMSK32rm_EVEX, + BLSMSK32rm_NF, + BLSMSK32rr, + BLSMSK32rr_EVEX, + BLSMSK32rr_NF, + BLSMSK64rm, + BLSMSK64rm_EVEX, + BLSMSK64rm_NF, + BLSMSK64rr, + BLSMSK64rr_EVEX, + BLSMSK64rr_NF, + BLSR32rm, + BLSR32rm_EVEX, + BLSR32rm_NF, + BLSR32rr, + BLSR32rr_EVEX, + BLSR32rr_NF, + BLSR64rm, + BLSR64rm_EVEX, + BLSR64rm_NF, + BLSR64rr, + BLSR64rr_EVEX, + BLSR64rr_NF, + BOUNDS16rm, + BOUNDS32rm, + BSF16rm, + BSF16rr, + BSF32rm, + BSF32rr, + BSF64rm, + BSF64rr, + BSR16rm, + BSR16rr, + BSR32rm, + BSR32rr, + BSR64rm, + BSR64rr, + BSWAP16r_BAD, + BSWAP32r, + BSWAP64r, + BT16mi8, + BT16mr, + BT16ri8, + BT16rr, + BT32mi8, + BT32mr, + BT32ri8, + BT32rr, + BT64mi8, + BT64mr, + BT64ri8, + BT64rr, + BTC16mi8, + BTC16mr, + BTC16ri8, + BTC16rr, + BTC32mi8, + BTC32mr, + BTC32ri8, + BTC32rr, + BTC64mi8, + BTC64mr, + BTC64ri8, + BTC64rr, + BTR16mi8, + BTR16mr, + BTR16ri8, + BTR16rr, + BTR32mi8, + BTR32mr, + BTR32ri8, + BTR32rr, + BTR64mi8, + BTR64mr, + BTR64ri8, + BTR64rr, + BTS16mi8, + BTS16mr, + BTS16ri8, + BTS16rr, + BTS32mi8, + BTS32mr, + BTS32ri8, + BTS32rr, + BTS64mi8, + BTS64mr, + BTS64ri8, + BTS64rr, + BZHI32rm, + BZHI32rm_EVEX, + BZHI32rm_NF, + BZHI32rr, + BZHI32rr_EVEX, + BZHI32rr_NF, + BZHI64rm, + BZHI64rm_EVEX, + BZHI64rm_NF, + BZHI64rr, + BZHI64rr_EVEX, + BZHI64rr_NF, + CALL16m, + CALL16m_NT, + CALL16r, + CALL16r_NT, + CALL32m, + CALL32m_NT, + CALL32r, + CALL32r_NT, + CALL64m, + CALL64m_NT, + CALL64pcrel32, + CALL64r, + CALL64r_NT, + CALLpcrel16, + CALLpcrel32, + CATCHRET, + CBW, + CCMP16mi, + CCMP16mi8, + CCMP16mr, + CCMP16ri, + CCMP16ri8, + CCMP16rm, + CCMP16rr, + CCMP16rr_REV, + CCMP32mi, + CCMP32mi8, + CCMP32mr, + CCMP32ri, + CCMP32ri8, + CCMP32rm, + CCMP32rr, + CCMP32rr_REV, + CCMP64mi32, + CCMP64mi8, + CCMP64mr, + CCMP64ri32, + CCMP64ri8, + CCMP64rm, + CCMP64rr, + CCMP64rr_REV, + CCMP8mi, + CCMP8mr, + CCMP8ri, + CCMP8rm, + CCMP8rr, + CCMP8rr_REV, + CDQ, + CDQE, + CFCMOV16mr, + CFCMOV16rm, + CFCMOV16rm_ND, + CFCMOV16rr, + CFCMOV16rr_ND, + CFCMOV16rr_REV, + CFCMOV32mr, + CFCMOV32rm, + CFCMOV32rm_ND, + CFCMOV32rr, + CFCMOV32rr_ND, + CFCMOV32rr_REV, + CFCMOV64mr, + CFCMOV64rm, + CFCMOV64rm_ND, + CFCMOV64rr, + CFCMOV64rr_ND, + CFCMOV64rr_REV, + CHS_F, + CHS_Fp32, + CHS_Fp64, + CHS_Fp80, + CLAC, + CLC, + CLD, + CLDEMOTE, + CLEANUPRET, + CLFLUSH, + CLFLUSHOPT, + CLGI, + CLI, + CLRSSBSY, + CLTS, + CLUI, + CLWB, + CLZERO32r, + CLZERO64r, + CMC, + CMOV16rm, + CMOV16rm_ND, + CMOV16rr, + CMOV16rr_ND, + CMOV32rm, + CMOV32rm_ND, + CMOV32rr, + CMOV32rr_ND, + CMOV64rm, + CMOV64rm_ND, + CMOV64rr, + CMOV64rr_ND, + CMOVBE_F, + CMOVBE_Fp32, + CMOVBE_Fp64, + CMOVBE_Fp80, + CMOVB_F, + CMOVB_Fp32, + CMOVB_Fp64, + CMOVB_Fp80, + CMOVE_F, + CMOVE_Fp32, + CMOVE_Fp64, + CMOVE_Fp80, + CMOVNBE_F, + CMOVNBE_Fp32, + CMOVNBE_Fp64, + CMOVNBE_Fp80, + CMOVNB_F, + CMOVNB_Fp32, + CMOVNB_Fp64, + CMOVNB_Fp80, + CMOVNE_F, + CMOVNE_Fp32, + CMOVNE_Fp64, + CMOVNE_Fp80, + CMOVNP_F, + CMOVNP_Fp32, + CMOVNP_Fp64, + CMOVNP_Fp80, + CMOVP_F, + CMOVP_Fp32, + CMOVP_Fp64, + CMOVP_Fp80, + CMOV_FR16, + CMOV_FR16X, + CMOV_FR32, + CMOV_FR32X, + CMOV_FR64, + CMOV_FR64X, + CMOV_GR16, + CMOV_GR32, + CMOV_GR8, + CMOV_RFP32, + CMOV_RFP64, + CMOV_RFP80, + CMOV_VK1, + CMOV_VK16, + CMOV_VK2, + CMOV_VK32, + CMOV_VK4, + CMOV_VK64, + CMOV_VK8, + CMOV_VR128, + CMOV_VR128X, + CMOV_VR256, + CMOV_VR256X, + CMOV_VR512, + CMOV_VR64, + CMP16i16, + CMP16mi, + CMP16mi8, + CMP16mr, + CMP16ri, + CMP16ri8, + CMP16rm, + CMP16rr, + CMP16rr_REV, + CMP32i32, + CMP32mi, + CMP32mi8, + CMP32mr, + CMP32ri, + CMP32ri8, + CMP32rm, + CMP32rr, + CMP32rr_REV, + CMP64i32, + CMP64mi32, + CMP64mi8, + CMP64mr, + CMP64ri32, + CMP64ri8, + CMP64rm, + CMP64rr, + CMP64rr_REV, + CMP8i8, + CMP8mi, + CMP8mi8, + CMP8mr, + CMP8ri, + CMP8ri8, + CMP8rm, + CMP8rr, + CMP8rr_REV, + CMPCCXADDmr32, + CMPCCXADDmr32_EVEX, + CMPCCXADDmr64, + CMPCCXADDmr64_EVEX, + CMPPDrmi, + CMPPDrri, + CMPPSrmi, + CMPPSrri, + CMPSB, + CMPSDrmi, + CMPSDrmi_Int, + CMPSDrri, + CMPSDrri_Int, + CMPSL, + CMPSQ, + CMPSSrmi, + CMPSSrmi_Int, + CMPSSrri, + CMPSSrri_Int, + CMPSW, + CMPXCHG16B, + CMPXCHG16rm, + CMPXCHG16rr, + CMPXCHG32rm, + CMPXCHG32rr, + CMPXCHG64rm, + CMPXCHG64rr, + CMPXCHG8B, + CMPXCHG8rm, + CMPXCHG8rr, + COMISDrm, + COMISDrm_Int, + COMISDrr, + COMISDrr_Int, + COMISSrm, + COMISSrm_Int, + COMISSrr, + COMISSrr_Int, + COMP_FST0r, + COM_FIPr, + COM_FIr, + COM_FST0r, + COM_FpIr32, + COM_FpIr64, + COM_FpIr80, + COM_Fpr32, + COM_Fpr64, + COM_Fpr80, + CPUID, + CQO, + CRC32r32m16, + CRC32r32m16_EVEX, + CRC32r32m32, + CRC32r32m32_EVEX, + CRC32r32m8, + CRC32r32m8_EVEX, + CRC32r32r16, + CRC32r32r16_EVEX, + CRC32r32r32, + CRC32r32r32_EVEX, + CRC32r32r8, + CRC32r32r8_EVEX, + CRC32r64m64, + CRC32r64m64_EVEX, + CRC32r64m8, + CRC32r64m8_EVEX, + CRC32r64r64, + CRC32r64r64_EVEX, + CRC32r64r8, + CRC32r64r8_EVEX, + CS_PREFIX, + CTEST16mi, + CTEST16mr, + CTEST16ri, + CTEST16rr, + CTEST32mi, + CTEST32mr, + CTEST32ri, + CTEST32rr, + CTEST64mi32, + CTEST64mr, + CTEST64ri32, + CTEST64rr, + CTEST8mi, + CTEST8mr, + CTEST8ri, + CTEST8rr, + CVTDQ2PDrm, + CVTDQ2PDrr, + CVTDQ2PSrm, + CVTDQ2PSrr, + CVTPD2DQrm, + CVTPD2DQrr, + CVTPD2PSrm, + CVTPD2PSrr, + CVTPS2DQrm, + CVTPS2DQrr, + CVTPS2PDrm, + CVTPS2PDrr, + CVTSD2SI64rm, + CVTSD2SI64rm_Int, + CVTSD2SI64rr, + CVTSD2SI64rr_Int, + CVTSD2SIrm, + CVTSD2SIrm_Int, + CVTSD2SIrr, + CVTSD2SIrr_Int, + CVTSD2SSrm, + CVTSD2SSrm_Int, + CVTSD2SSrr, + CVTSD2SSrr_Int, + CVTSI2SDrm, + CVTSI2SDrm_Int, + CVTSI2SDrr, + CVTSI2SDrr_Int, + CVTSI2SSrm, + CVTSI2SSrm_Int, + CVTSI2SSrr, + CVTSI2SSrr_Int, + CVTSI642SDrm, + CVTSI642SDrm_Int, + CVTSI642SDrr, + CVTSI642SDrr_Int, + CVTSI642SSrm, + CVTSI642SSrm_Int, + CVTSI642SSrr, + CVTSI642SSrr_Int, + CVTSS2SDrm, + CVTSS2SDrm_Int, + CVTSS2SDrr, + CVTSS2SDrr_Int, + CVTSS2SI64rm, + CVTSS2SI64rm_Int, + CVTSS2SI64rr, + CVTSS2SI64rr_Int, + CVTSS2SIrm, + CVTSS2SIrm_Int, + CVTSS2SIrr, + CVTSS2SIrr_Int, + CVTTPD2DQrm, + CVTTPD2DQrr, + CVTTPS2DQrm, + CVTTPS2DQrr, + CVTTSD2SI64rm, + CVTTSD2SI64rm_Int, + CVTTSD2SI64rr, + CVTTSD2SI64rr_Int, + CVTTSD2SIrm, + CVTTSD2SIrm_Int, + CVTTSD2SIrr, + CVTTSD2SIrr_Int, + CVTTSS2SI64rm, + CVTTSS2SI64rm_Int, + CVTTSS2SI64rr, + CVTTSS2SI64rr_Int, + CVTTSS2SIrm, + CVTTSS2SIrm_Int, + CVTTSS2SIrr, + CVTTSS2SIrr_Int, + CWD, + CWDE, + DAA, + DAS, + DATA16_PREFIX, + DEC16m, + DEC16m_EVEX, + DEC16m_ND, + DEC16m_NF, + DEC16m_NF_ND, + DEC16r, + DEC16r_EVEX, + DEC16r_ND, + DEC16r_NF, + DEC16r_NF_ND, + DEC16r_alt, + DEC32m, + DEC32m_EVEX, + DEC32m_ND, + DEC32m_NF, + DEC32m_NF_ND, + DEC32r, + DEC32r_EVEX, + DEC32r_ND, + DEC32r_NF, + DEC32r_NF_ND, + DEC32r_alt, + DEC64m, + DEC64m_EVEX, + DEC64m_ND, + DEC64m_NF, + DEC64m_NF_ND, + DEC64r, + DEC64r_EVEX, + DEC64r_ND, + DEC64r_NF, + DEC64r_NF_ND, + DEC8m, + DEC8m_EVEX, + DEC8m_ND, + DEC8m_NF, + DEC8m_NF_ND, + DEC8r, + DEC8r_EVEX, + DEC8r_ND, + DEC8r_NF, + DEC8r_NF_ND, + DIV16m, + DIV16m_EVEX, + DIV16m_NF, + DIV16r, + DIV16r_EVEX, + DIV16r_NF, + DIV32m, + DIV32m_EVEX, + DIV32m_NF, + DIV32r, + DIV32r_EVEX, + DIV32r_NF, + DIV64m, + DIV64m_EVEX, + DIV64m_NF, + DIV64r, + DIV64r_EVEX, + DIV64r_NF, + DIV8m, + DIV8m_EVEX, + DIV8m_NF, + DIV8r, + DIV8r_EVEX, + DIV8r_NF, + DIVPDrm, + DIVPDrr, + DIVPSrm, + DIVPSrr, + DIVR_F32m, + DIVR_F64m, + DIVR_FI16m, + DIVR_FI32m, + DIVR_FPrST0, + DIVR_FST0r, + DIVR_Fp32m, + DIVR_Fp64m, + DIVR_Fp64m32, + DIVR_Fp80m32, + DIVR_Fp80m64, + DIVR_FpI16m32, + DIVR_FpI16m64, + DIVR_FpI16m80, + DIVR_FpI32m32, + DIVR_FpI32m64, + DIVR_FpI32m80, + DIVR_FrST0, + DIVSDrm, + DIVSDrm_Int, + DIVSDrr, + DIVSDrr_Int, + DIVSSrm, + DIVSSrm_Int, + DIVSSrr, + DIVSSrr_Int, + DIV_F32m, + DIV_F64m, + DIV_FI16m, + DIV_FI32m, + DIV_FPrST0, + DIV_FST0r, + DIV_Fp32, + DIV_Fp32m, + DIV_Fp64, + DIV_Fp64m, + DIV_Fp64m32, + DIV_Fp80, + DIV_Fp80m32, + DIV_Fp80m64, + DIV_FpI16m32, + DIV_FpI16m64, + DIV_FpI16m80, + DIV_FpI32m32, + DIV_FpI32m64, + DIV_FpI32m80, + DIV_FrST0, + DPPDrmi, + DPPDrri, + DPPSrmi, + DPPSrri, + DS_PREFIX, + DYN_ALLOCA_32, + DYN_ALLOCA_64, + EH_RETURN, + EH_RETURN64, + EH_SjLj_LongJmp32, + EH_SjLj_LongJmp64, + EH_SjLj_SetJmp32, + EH_SjLj_SetJmp64, + EH_SjLj_Setup, + ENCLS, + ENCLU, + ENCLV, + ENCODEKEY128, + ENCODEKEY256, + ENDBR32, + ENDBR64, + ENQCMD16, + ENQCMD32, + ENQCMD32_EVEX, + ENQCMD64, + ENQCMD64_EVEX, + ENQCMDS16, + ENQCMDS32, + ENQCMDS32_EVEX, + ENQCMDS64, + ENQCMDS64_EVEX, + ENTER, + ERETS, + ERETU, + ES_PREFIX, + EXTRACTPSmri, + EXTRACTPSrri, + EXTRQ, + EXTRQI, + F2XM1, + FARCALL16i, + FARCALL16m, + FARCALL32i, + FARCALL32m, + FARCALL64m, + FARJMP16i, + FARJMP16m, + FARJMP32i, + FARJMP32m, + FARJMP64m, + FBLDm, + FBSTPm, + FCOM32m, + FCOM64m, + FCOMP32m, + FCOMP64m, + FCOMPP, + FCOS, + FDECSTP, + FEMMS, + FFREE, + FFREEP, + FICOM16m, + FICOM32m, + FICOMP16m, + FICOMP32m, + FINCSTP, + FLDCW16m, + FLDENVm, + FLDL2E, + FLDL2T, + FLDLG2, + FLDLN2, + FLDPI, + FNCLEX, + FNINIT, + FNOP, + FNSTCW16m, + FNSTSW16r, + FNSTSWm, + FP32_TO_INT16_IN_MEM, + FP32_TO_INT32_IN_MEM, + FP32_TO_INT64_IN_MEM, + FP64_TO_INT16_IN_MEM, + FP64_TO_INT32_IN_MEM, + FP64_TO_INT64_IN_MEM, + FP80_ADDm32, + FP80_ADDr, + FP80_TO_INT16_IN_MEM, + FP80_TO_INT32_IN_MEM, + FP80_TO_INT64_IN_MEM, + FPATAN, + FPREM, + FPREM1, + FPTAN, + FRNDINT, + FRSTORm, + FSAVEm, + FSCALE_, + FSIN, + FSINCOS, + FSTENVm, + FS_PREFIX, + FXRSTOR, + FXRSTOR64, + FXSAVE, + FXSAVE64, + FXTRACT, + FYL2X, + FYL2XP1, + GETSEC, + GF2P8AFFINEINVQBrmi, + GF2P8AFFINEINVQBrri, + GF2P8AFFINEQBrmi, + GF2P8AFFINEQBrri, + GF2P8MULBrm, + GF2P8MULBrr, + GS_PREFIX, + HADDPDrm, + HADDPDrr, + HADDPSrm, + HADDPSrr, + HLT, + HRESET, + HSUBPDrm, + HSUBPDrr, + HSUBPSrm, + HSUBPSrr, + IDIV16m, + IDIV16m_EVEX, + IDIV16m_NF, + IDIV16r, + IDIV16r_EVEX, + IDIV16r_NF, + IDIV32m, + IDIV32m_EVEX, + IDIV32m_NF, + IDIV32r, + IDIV32r_EVEX, + IDIV32r_NF, + IDIV64m, + IDIV64m_EVEX, + IDIV64m_NF, + IDIV64r, + IDIV64r_EVEX, + IDIV64r_NF, + IDIV8m, + IDIV8m_EVEX, + IDIV8m_NF, + IDIV8r, + IDIV8r_EVEX, + IDIV8r_NF, + ILD_F16m, + ILD_F32m, + ILD_F64m, + ILD_Fp16m32, + ILD_Fp16m64, + ILD_Fp16m80, + ILD_Fp32m32, + ILD_Fp32m64, + ILD_Fp32m80, + ILD_Fp64m32, + ILD_Fp64m64, + ILD_Fp64m80, + IMUL16m, + IMUL16m_EVEX, + IMUL16m_NF, + IMUL16r, + IMUL16r_EVEX, + IMUL16r_NF, + IMUL16rm, + IMUL16rm_EVEX, + IMUL16rm_ND, + IMUL16rm_NF, + IMUL16rm_NF_ND, + IMUL16rmi, + IMUL16rmi8, + IMUL16rmi8_EVEX, + IMUL16rmi8_NF, + IMUL16rmi_EVEX, + IMUL16rmi_NF, + IMUL16rr, + IMUL16rr_EVEX, + IMUL16rr_ND, + IMUL16rr_NF, + IMUL16rr_NF_ND, + IMUL16rri, + IMUL16rri8, + IMUL16rri8_EVEX, + IMUL16rri8_NF, + IMUL16rri_EVEX, + IMUL16rri_NF, + IMUL32m, + IMUL32m_EVEX, + IMUL32m_NF, + IMUL32r, + IMUL32r_EVEX, + IMUL32r_NF, + IMUL32rm, + IMUL32rm_EVEX, + IMUL32rm_ND, + IMUL32rm_NF, + IMUL32rm_NF_ND, + IMUL32rmi, + IMUL32rmi8, + IMUL32rmi8_EVEX, + IMUL32rmi8_NF, + IMUL32rmi_EVEX, + IMUL32rmi_NF, + IMUL32rr, + IMUL32rr_EVEX, + IMUL32rr_ND, + IMUL32rr_NF, + IMUL32rr_NF_ND, + IMUL32rri, + IMUL32rri8, + IMUL32rri8_EVEX, + IMUL32rri8_NF, + IMUL32rri_EVEX, + IMUL32rri_NF, + IMUL64m, + IMUL64m_EVEX, + IMUL64m_NF, + IMUL64r, + IMUL64r_EVEX, + IMUL64r_NF, + IMUL64rm, + IMUL64rm_EVEX, + IMUL64rm_ND, + IMUL64rm_NF, + IMUL64rm_NF_ND, + IMUL64rmi32, + IMUL64rmi32_EVEX, + IMUL64rmi32_NF, + IMUL64rmi8, + IMUL64rmi8_EVEX, + IMUL64rmi8_NF, + IMUL64rr, + IMUL64rr_EVEX, + IMUL64rr_ND, + IMUL64rr_NF, + IMUL64rr_NF_ND, + IMUL64rri32, + IMUL64rri32_EVEX, + IMUL64rri32_NF, + IMUL64rri8, + IMUL64rri8_EVEX, + IMUL64rri8_NF, + IMUL8m, + IMUL8m_EVEX, + IMUL8m_NF, + IMUL8r, + IMUL8r_EVEX, + IMUL8r_NF, + IMULZU16rmi, + IMULZU16rmi8, + IMULZU16rri, + IMULZU16rri8, + IMULZU32rmi, + IMULZU32rmi8, + IMULZU32rri, + IMULZU32rri8, + IMULZU64rmi32, + IMULZU64rmi8, + IMULZU64rri32, + IMULZU64rri8, + IN16ri, + IN16rr, + IN32ri, + IN32rr, + IN8ri, + IN8rr, + INC16m, + INC16m_EVEX, + INC16m_ND, + INC16m_NF, + INC16m_NF_ND, + INC16r, + INC16r_EVEX, + INC16r_ND, + INC16r_NF, + INC16r_NF_ND, + INC16r_alt, + INC32m, + INC32m_EVEX, + INC32m_ND, + INC32m_NF, + INC32m_NF_ND, + INC32r, + INC32r_EVEX, + INC32r_ND, + INC32r_NF, + INC32r_NF_ND, + INC32r_alt, + INC64m, + INC64m_EVEX, + INC64m_ND, + INC64m_NF, + INC64m_NF_ND, + INC64r, + INC64r_EVEX, + INC64r_ND, + INC64r_NF, + INC64r_NF_ND, + INC8m, + INC8m_EVEX, + INC8m_ND, + INC8m_NF, + INC8m_NF_ND, + INC8r, + INC8r_EVEX, + INC8r_ND, + INC8r_NF, + INC8r_NF_ND, + INCSSPD, + INCSSPQ, + INSB, + INSERTPSrmi, + INSERTPSrri, + INSERTQ, + INSERTQI, + INSL, + INSW, + INT, + INT3, + INTO, + INVD, + INVEPT32, + INVEPT64, + INVEPT64_EVEX, + INVLPG, + INVLPGA32, + INVLPGA64, + INVLPGB32, + INVLPGB64, + INVPCID32, + INVPCID64, + INVPCID64_EVEX, + INVVPID32, + INVVPID64, + INVVPID64_EVEX, + IRET, + IRET16, + IRET32, + IRET64, + ISTT_FP16m, + ISTT_FP32m, + ISTT_FP64m, + ISTT_Fp16m32, + ISTT_Fp16m64, + ISTT_Fp16m80, + ISTT_Fp32m32, + ISTT_Fp32m64, + ISTT_Fp32m80, + ISTT_Fp64m32, + ISTT_Fp64m64, + ISTT_Fp64m80, + IST_F16m, + IST_F32m, + IST_FP16m, + IST_FP32m, + IST_FP64m, + IST_Fp16m32, + IST_Fp16m64, + IST_Fp16m80, + IST_Fp32m32, + IST_Fp32m64, + IST_Fp32m80, + IST_Fp64m32, + IST_Fp64m64, + IST_Fp64m80, + Int_eh_sjlj_setup_dispatch, + JCC_1, + JCC_2, + JCC_4, + JCXZ, + JECXZ, + JMP16m, + JMP16m_NT, + JMP16r, + JMP16r_NT, + JMP32m, + JMP32m_NT, + JMP32r, + JMP32r_NT, + JMP64m, + JMP64m_NT, + JMP64m_REX, + JMP64r, + JMP64r_NT, + JMP64r_REX, + JMPABS64i, + JMP_1, + JMP_2, + JMP_4, + JRCXZ, + KADDBkk, + KADDDkk, + KADDQkk, + KADDWkk, + KANDBkk, + KANDDkk, + KANDNBkk, + KANDNDkk, + KANDNQkk, + KANDNWkk, + KANDQkk, + KANDWkk, + KCFI_CHECK, + KMOVBkk, + KMOVBkk_EVEX, + KMOVBkm, + KMOVBkm_EVEX, + KMOVBkr, + KMOVBkr_EVEX, + KMOVBmk, + KMOVBmk_EVEX, + KMOVBrk, + KMOVBrk_EVEX, + KMOVDkk, + KMOVDkk_EVEX, + KMOVDkm, + KMOVDkm_EVEX, + KMOVDkr, + KMOVDkr_EVEX, + KMOVDmk, + KMOVDmk_EVEX, + KMOVDrk, + KMOVDrk_EVEX, + KMOVQkk, + KMOVQkk_EVEX, + KMOVQkm, + KMOVQkm_EVEX, + KMOVQkr, + KMOVQkr_EVEX, + KMOVQmk, + KMOVQmk_EVEX, + KMOVQrk, + KMOVQrk_EVEX, + KMOVWkk, + KMOVWkk_EVEX, + KMOVWkm, + KMOVWkm_EVEX, + KMOVWkr, + KMOVWkr_EVEX, + KMOVWmk, + KMOVWmk_EVEX, + KMOVWrk, + KMOVWrk_EVEX, + KNOTBkk, + KNOTDkk, + KNOTQkk, + KNOTWkk, + KORBkk, + KORDkk, + KORQkk, + KORTESTBkk, + KORTESTDkk, + KORTESTQkk, + KORTESTWkk, + KORWkk, + KSHIFTLBki, + KSHIFTLDki, + KSHIFTLQki, + KSHIFTLWki, + KSHIFTRBki, + KSHIFTRDki, + KSHIFTRQki, + KSHIFTRWki, + KTESTBkk, + KTESTDkk, + KTESTQkk, + KTESTWkk, + KUNPCKBWkk, + KUNPCKDQkk, + KUNPCKWDkk, + KXNORBkk, + KXNORDkk, + KXNORQkk, + KXNORWkk, + KXORBkk, + KXORDkk, + KXORQkk, + KXORWkk, + LAHF, + LAR16rm, + LAR16rr, + LAR32rm, + LAR32rr, + LAR64rm, + LAR64rr, + LCMPXCHG16, + LCMPXCHG16B, + LCMPXCHG32, + LCMPXCHG64, + LCMPXCHG8, + LCMPXCHG8B, + LDDQUrm, + LDMXCSR, + LDS16rm, + LDS32rm, + LDTILECFG, + LDTILECFG_EVEX, + LD_F0, + LD_F1, + LD_F32m, + LD_F64m, + LD_F80m, + LD_Fp032, + LD_Fp064, + LD_Fp080, + LD_Fp132, + LD_Fp164, + LD_Fp180, + LD_Fp32m, + LD_Fp32m64, + LD_Fp32m80, + LD_Fp64m, + LD_Fp64m80, + LD_Fp80m, + LD_Frr, + LEA16r, + LEA32r, + LEA64_16r, + LEA64_32r, + LEA64_8r, + LEA64r, + LEAVE, + LEAVE64, + LES16rm, + LES32rm, + LFENCE, + LFS16rm, + LFS32rm, + LFS64rm, + LGDT16m, + LGDT32m, + LGDT64m, + LGS16rm, + LGS32rm, + LGS64rm, + LIDT16m, + LIDT32m, + LIDT64m, + LKGS16m, + LKGS16r, + LLDT16m, + LLDT16r, + LLWPCB, + LLWPCB64, + LMSW16m, + LMSW16r, + LOADIWKEY, + LOCK_ADD16mi, + LOCK_ADD16mi8, + LOCK_ADD16mr, + LOCK_ADD32mi, + LOCK_ADD32mi8, + LOCK_ADD32mr, + LOCK_ADD64mi32, + LOCK_ADD64mi8, + LOCK_ADD64mr, + LOCK_ADD8mi, + LOCK_ADD8mr, + LOCK_AND16mi, + LOCK_AND16mi8, + LOCK_AND16mr, + LOCK_AND32mi, + LOCK_AND32mi8, + LOCK_AND32mr, + LOCK_AND64mi32, + LOCK_AND64mi8, + LOCK_AND64mr, + LOCK_AND8mi, + LOCK_AND8mr, + LOCK_BTC16m, + LOCK_BTC32m, + LOCK_BTC64m, + LOCK_BTC_RM16rm, + LOCK_BTC_RM32rm, + LOCK_BTC_RM64rm, + LOCK_BTR16m, + LOCK_BTR32m, + LOCK_BTR64m, + LOCK_BTR_RM16rm, + LOCK_BTR_RM32rm, + LOCK_BTR_RM64rm, + LOCK_BTS16m, + LOCK_BTS32m, + LOCK_BTS64m, + LOCK_BTS_RM16rm, + LOCK_BTS_RM32rm, + LOCK_BTS_RM64rm, + LOCK_DEC16m, + LOCK_DEC32m, + LOCK_DEC64m, + LOCK_DEC8m, + LOCK_INC16m, + LOCK_INC32m, + LOCK_INC64m, + LOCK_INC8m, + LOCK_OR16mi, + LOCK_OR16mi8, + LOCK_OR16mr, + LOCK_OR32mi, + LOCK_OR32mi8, + LOCK_OR32mr, + LOCK_OR64mi32, + LOCK_OR64mi8, + LOCK_OR64mr, + LOCK_OR8mi, + LOCK_OR8mr, + LOCK_PREFIX, + LOCK_SUB16mi, + LOCK_SUB16mi8, + LOCK_SUB16mr, + LOCK_SUB32mi, + LOCK_SUB32mi8, + LOCK_SUB32mr, + LOCK_SUB64mi32, + LOCK_SUB64mi8, + LOCK_SUB64mr, + LOCK_SUB8mi, + LOCK_SUB8mr, + LOCK_XOR16mi, + LOCK_XOR16mi8, + LOCK_XOR16mr, + LOCK_XOR32mi, + LOCK_XOR32mi8, + LOCK_XOR32mr, + LOCK_XOR64mi32, + LOCK_XOR64mi8, + LOCK_XOR64mr, + LOCK_XOR8mi, + LOCK_XOR8mr, + LODSB, + LODSL, + LODSQ, + LODSW, + LOOP, + LOOPE, + LOOPNE, + LRET16, + LRET32, + LRET64, + LRETI16, + LRETI32, + LRETI64, + LSL16rm, + LSL16rr, + LSL32rm, + LSL32rr, + LSL64rm, + LSL64rr, + LSS16rm, + LSS32rm, + LSS64rm, + LTRm, + LTRr, + LWPINS32rmi, + LWPINS32rri, + LWPINS64rmi, + LWPINS64rri, + LWPVAL32rmi, + LWPVAL32rri, + LWPVAL64rmi, + LWPVAL64rri, + LXADD16, + LXADD32, + LXADD64, + LXADD8, + LZCNT16rm, + LZCNT16rm_EVEX, + LZCNT16rm_NF, + LZCNT16rr, + LZCNT16rr_EVEX, + LZCNT16rr_NF, + LZCNT32rm, + LZCNT32rm_EVEX, + LZCNT32rm_NF, + LZCNT32rr, + LZCNT32rr_EVEX, + LZCNT32rr_NF, + LZCNT64rm, + LZCNT64rm_EVEX, + LZCNT64rm_NF, + LZCNT64rr, + LZCNT64rr_EVEX, + LZCNT64rr_NF, + MASKMOVDQU, + MASKMOVDQU64, + MASKPAIR16LOAD, + MASKPAIR16STORE, + MAXCPDrm, + MAXCPDrr, + MAXCPSrm, + MAXCPSrr, + MAXCSDrm, + MAXCSDrr, + MAXCSSrm, + MAXCSSrr, + MAXPDrm, + MAXPDrr, + MAXPSrm, + MAXPSrr, + MAXSDrm, + MAXSDrm_Int, + MAXSDrr, + MAXSDrr_Int, + MAXSSrm, + MAXSSrm_Int, + MAXSSrr, + MAXSSrr_Int, + MFENCE, + MINCPDrm, + MINCPDrr, + MINCPSrm, + MINCPSrr, + MINCSDrm, + MINCSDrr, + MINCSSrm, + MINCSSrr, + MINPDrm, + MINPDrr, + MINPSrm, + MINPSrr, + MINSDrm, + MINSDrm_Int, + MINSDrr, + MINSDrr_Int, + MINSSrm, + MINSSrm_Int, + MINSSrr, + MINSSrr_Int, + MMX_CVTPD2PIrm, + MMX_CVTPD2PIrr, + MMX_CVTPI2PDrm, + MMX_CVTPI2PDrr, + MMX_CVTPI2PSrm, + MMX_CVTPI2PSrr, + MMX_CVTPS2PIrm, + MMX_CVTPS2PIrr, + MMX_CVTTPD2PIrm, + MMX_CVTTPD2PIrr, + MMX_CVTTPS2PIrm, + MMX_CVTTPS2PIrr, + MMX_EMMS, + MMX_MASKMOVQ, + MMX_MASKMOVQ64, + MMX_MOVD64from64mr, + MMX_MOVD64from64rr, + MMX_MOVD64grr, + MMX_MOVD64mr, + MMX_MOVD64rm, + MMX_MOVD64rr, + MMX_MOVD64to64rm, + MMX_MOVD64to64rr, + MMX_MOVDQ2Qrr, + MMX_MOVFR642Qrr, + MMX_MOVNTQmr, + MMX_MOVQ2DQrr, + MMX_MOVQ2FR64rr, + MMX_MOVQ64mr, + MMX_MOVQ64rm, + MMX_MOVQ64rr, + MMX_MOVQ64rr_REV, + MMX_PABSBrm, + MMX_PABSBrr, + MMX_PABSDrm, + MMX_PABSDrr, + MMX_PABSWrm, + MMX_PABSWrr, + MMX_PACKSSDWrm, + MMX_PACKSSDWrr, + MMX_PACKSSWBrm, + MMX_PACKSSWBrr, + MMX_PACKUSWBrm, + MMX_PACKUSWBrr, + MMX_PADDBrm, + MMX_PADDBrr, + MMX_PADDDrm, + MMX_PADDDrr, + MMX_PADDQrm, + MMX_PADDQrr, + MMX_PADDSBrm, + MMX_PADDSBrr, + MMX_PADDSWrm, + MMX_PADDSWrr, + MMX_PADDUSBrm, + MMX_PADDUSBrr, + MMX_PADDUSWrm, + MMX_PADDUSWrr, + MMX_PADDWrm, + MMX_PADDWrr, + MMX_PALIGNRrmi, + MMX_PALIGNRrri, + MMX_PANDNrm, + MMX_PANDNrr, + MMX_PANDrm, + MMX_PANDrr, + MMX_PAVGBrm, + MMX_PAVGBrr, + MMX_PAVGWrm, + MMX_PAVGWrr, + MMX_PCMPEQBrm, + MMX_PCMPEQBrr, + MMX_PCMPEQDrm, + MMX_PCMPEQDrr, + MMX_PCMPEQWrm, + MMX_PCMPEQWrr, + MMX_PCMPGTBrm, + MMX_PCMPGTBrr, + MMX_PCMPGTDrm, + MMX_PCMPGTDrr, + MMX_PCMPGTWrm, + MMX_PCMPGTWrr, + MMX_PEXTRWrri, + MMX_PHADDDrm, + MMX_PHADDDrr, + MMX_PHADDSWrm, + MMX_PHADDSWrr, + MMX_PHADDWrm, + MMX_PHADDWrr, + MMX_PHSUBDrm, + MMX_PHSUBDrr, + MMX_PHSUBSWrm, + MMX_PHSUBSWrr, + MMX_PHSUBWrm, + MMX_PHSUBWrr, + MMX_PINSRWrmi, + MMX_PINSRWrri, + MMX_PMADDUBSWrm, + MMX_PMADDUBSWrr, + MMX_PMADDWDrm, + MMX_PMADDWDrr, + MMX_PMAXSWrm, + MMX_PMAXSWrr, + MMX_PMAXUBrm, + MMX_PMAXUBrr, + MMX_PMINSWrm, + MMX_PMINSWrr, + MMX_PMINUBrm, + MMX_PMINUBrr, + MMX_PMOVMSKBrr, + MMX_PMULHRSWrm, + MMX_PMULHRSWrr, + MMX_PMULHUWrm, + MMX_PMULHUWrr, + MMX_PMULHWrm, + MMX_PMULHWrr, + MMX_PMULLWrm, + MMX_PMULLWrr, + MMX_PMULUDQrm, + MMX_PMULUDQrr, + MMX_PORrm, + MMX_PORrr, + MMX_PSADBWrm, + MMX_PSADBWrr, + MMX_PSHUFBrm, + MMX_PSHUFBrr, + MMX_PSHUFWmi, + MMX_PSHUFWri, + MMX_PSIGNBrm, + MMX_PSIGNBrr, + MMX_PSIGNDrm, + MMX_PSIGNDrr, + MMX_PSIGNWrm, + MMX_PSIGNWrr, + MMX_PSLLDri, + MMX_PSLLDrm, + MMX_PSLLDrr, + MMX_PSLLQri, + MMX_PSLLQrm, + MMX_PSLLQrr, + MMX_PSLLWri, + MMX_PSLLWrm, + MMX_PSLLWrr, + MMX_PSRADri, + MMX_PSRADrm, + MMX_PSRADrr, + MMX_PSRAWri, + MMX_PSRAWrm, + MMX_PSRAWrr, + MMX_PSRLDri, + MMX_PSRLDrm, + MMX_PSRLDrr, + MMX_PSRLQri, + MMX_PSRLQrm, + MMX_PSRLQrr, + MMX_PSRLWri, + MMX_PSRLWrm, + MMX_PSRLWrr, + MMX_PSUBBrm, + MMX_PSUBBrr, + MMX_PSUBDrm, + MMX_PSUBDrr, + MMX_PSUBQrm, + MMX_PSUBQrr, + MMX_PSUBSBrm, + MMX_PSUBSBrr, + MMX_PSUBSWrm, + MMX_PSUBSWrr, + MMX_PSUBUSBrm, + MMX_PSUBUSBrr, + MMX_PSUBUSWrm, + MMX_PSUBUSWrr, + MMX_PSUBWrm, + MMX_PSUBWrr, + MMX_PUNPCKHBWrm, + MMX_PUNPCKHBWrr, + MMX_PUNPCKHDQrm, + MMX_PUNPCKHDQrr, + MMX_PUNPCKHWDrm, + MMX_PUNPCKHWDrr, + MMX_PUNPCKLBWrm, + MMX_PUNPCKLBWrr, + MMX_PUNPCKLDQrm, + MMX_PUNPCKLDQrr, + MMX_PUNPCKLWDrm, + MMX_PUNPCKLWDrr, + MMX_PXORrm, + MMX_PXORrr, + MONITOR32rrr, + MONITOR64rrr, + MONITORX32rrr, + MONITORX64rrr, + MONTMUL, + MOV16ao16, + MOV16ao32, + MOV16ao64, + MOV16mi, + MOV16mr, + MOV16ms, + MOV16o16a, + MOV16o32a, + MOV16o64a, + MOV16ri, + MOV16ri_alt, + MOV16rm, + MOV16rr, + MOV16rr_REV, + MOV16rs, + MOV16sm, + MOV16sr, + MOV32ao16, + MOV32ao32, + MOV32ao64, + MOV32cr, + MOV32dr, + MOV32mi, + MOV32mr, + MOV32o16a, + MOV32o32a, + MOV32o64a, + MOV32rc, + MOV32rd, + MOV32ri, + MOV32ri_alt, + MOV32rm, + MOV32rr, + MOV32rr_REV, + MOV32rs, + MOV32sr, + MOV64ao32, + MOV64ao64, + MOV64cr, + MOV64dr, + MOV64mi32, + MOV64mr, + MOV64o32a, + MOV64o64a, + MOV64rc, + MOV64rd, + MOV64ri, + MOV64ri32, + MOV64rm, + MOV64rr, + MOV64rr_REV, + MOV64rs, + MOV64sr, + MOV64toPQIrm, + MOV64toPQIrr, + MOV64toSDrr, + MOV8ao16, + MOV8ao32, + MOV8ao64, + MOV8mi, + MOV8mr, + MOV8mr_NOREX, + MOV8o16a, + MOV8o32a, + MOV8o64a, + MOV8ri, + MOV8ri_alt, + MOV8rm, + MOV8rm_NOREX, + MOV8rr, + MOV8rr_NOREX, + MOV8rr_REV, + MOVAPDmr, + MOVAPDrm, + MOVAPDrr, + MOVAPDrr_REV, + MOVAPSmr, + MOVAPSrm, + MOVAPSrr, + MOVAPSrr_REV, + MOVBE16mr, + MOVBE16mr_EVEX, + MOVBE16rm, + MOVBE16rm_EVEX, + MOVBE16rr, + MOVBE16rr_REV, + MOVBE32mr, + MOVBE32mr_EVEX, + MOVBE32rm, + MOVBE32rm_EVEX, + MOVBE32rr, + MOVBE32rr_REV, + MOVBE64mr, + MOVBE64mr_EVEX, + MOVBE64rm, + MOVBE64rm_EVEX, + MOVBE64rr, + MOVBE64rr_REV, + MOVDDUPrm, + MOVDDUPrr, + MOVDI2PDIrm, + MOVDI2PDIrr, + MOVDI2SSrr, + MOVDIR64B16, + MOVDIR64B32, + MOVDIR64B32_EVEX, + MOVDIR64B64, + MOVDIR64B64_EVEX, + MOVDIRI32, + MOVDIRI32_EVEX, + MOVDIRI64, + MOVDIRI64_EVEX, + MOVDQAmr, + MOVDQArm, + MOVDQArr, + MOVDQArr_REV, + MOVDQUmr, + MOVDQUrm, + MOVDQUrr, + MOVDQUrr_REV, + MOVHLPSrr, + MOVHPDmr, + MOVHPDrm, + MOVHPSmr, + MOVHPSrm, + MOVLHPSrr, + MOVLPDmr, + MOVLPDrm, + MOVLPSmr, + MOVLPSrm, + MOVMSKPDrr, + MOVMSKPSrr, + MOVNTDQArm, + MOVNTDQmr, + MOVNTI_64mr, + MOVNTImr, + MOVNTPDmr, + MOVNTPSmr, + MOVNTSD, + MOVNTSS, + MOVPC32r, + MOVPDI2DImr, + MOVPDI2DIrr, + MOVPQI2QImr, + MOVPQI2QIrr, + MOVPQIto64mr, + MOVPQIto64rr, + MOVQI2PQIrm, + MOVRS16rm, + MOVRS16rm_EVEX, + MOVRS32rm, + MOVRS32rm_EVEX, + MOVRS64rm, + MOVRS64rm_EVEX, + MOVRS8rm, + MOVRS8rm_EVEX, + MOVSB, + MOVSDmr, + MOVSDrm, + MOVSDrm_alt, + MOVSDrr, + MOVSDrr_REV, + MOVSDto64rr, + MOVSHDUPrm, + MOVSHDUPrr, + MOVSL, + MOVSLDUPrm, + MOVSLDUPrr, + MOVSQ, + MOVSS2DIrr, + MOVSSmr, + MOVSSrm, + MOVSSrm_alt, + MOVSSrr, + MOVSSrr_REV, + MOVSW, + MOVSX16rm16, + MOVSX16rm32, + MOVSX16rm8, + MOVSX16rr16, + MOVSX16rr32, + MOVSX16rr8, + MOVSX32rm16, + MOVSX32rm32, + MOVSX32rm8, + MOVSX32rm8_NOREX, + MOVSX32rr16, + MOVSX32rr32, + MOVSX32rr8, + MOVSX32rr8_NOREX, + MOVSX64rm16, + MOVSX64rm32, + MOVSX64rm8, + MOVSX64rr16, + MOVSX64rr32, + MOVSX64rr8, + MOVUPDmr, + MOVUPDrm, + MOVUPDrr, + MOVUPDrr_REV, + MOVUPSmr, + MOVUPSrm, + MOVUPSrr, + MOVUPSrr_REV, + MOVZPQILo2PQIrr, + MOVZX16rm16, + MOVZX16rm8, + MOVZX16rr16, + MOVZX16rr8, + MOVZX32rm16, + MOVZX32rm8, + MOVZX32rm8_NOREX, + MOVZX32rr16, + MOVZX32rr8, + MOVZX32rr8_NOREX, + MOVZX64rm16, + MOVZX64rm8, + MOVZX64rr16, + MOVZX64rr8, + MPSADBWrmi, + MPSADBWrri, + MUL16m, + MUL16m_EVEX, + MUL16m_NF, + MUL16r, + MUL16r_EVEX, + MUL16r_NF, + MUL32m, + MUL32m_EVEX, + MUL32m_NF, + MUL32r, + MUL32r_EVEX, + MUL32r_NF, + MUL64m, + MUL64m_EVEX, + MUL64m_NF, + MUL64r, + MUL64r_EVEX, + MUL64r_NF, + MUL8m, + MUL8m_EVEX, + MUL8m_NF, + MUL8r, + MUL8r_EVEX, + MUL8r_NF, + MULPDrm, + MULPDrr, + MULPSrm, + MULPSrr, + MULSDrm, + MULSDrm_Int, + MULSDrr, + MULSDrr_Int, + MULSSrm, + MULSSrm_Int, + MULSSrr, + MULSSrr_Int, + MULX32Hrm, + MULX32Hrr, + MULX32rm, + MULX32rm_EVEX, + MULX32rr, + MULX32rr_EVEX, + MULX64Hrm, + MULX64Hrr, + MULX64rm, + MULX64rm_EVEX, + MULX64rr, + MULX64rr_EVEX, + MUL_F32m, + MUL_F64m, + MUL_FI16m, + MUL_FI32m, + MUL_FPrST0, + MUL_FST0r, + MUL_Fp32, + MUL_Fp32m, + MUL_Fp64, + MUL_Fp64m, + MUL_Fp64m32, + MUL_Fp80, + MUL_Fp80m32, + MUL_Fp80m64, + MUL_FpI16m32, + MUL_FpI16m64, + MUL_FpI16m80, + MUL_FpI32m32, + MUL_FpI32m64, + MUL_FpI32m80, + MUL_FrST0, + MWAITXrrr, + MWAITrr, + NEG16m, + NEG16m_EVEX, + NEG16m_ND, + NEG16m_NF, + NEG16m_NF_ND, + NEG16r, + NEG16r_EVEX, + NEG16r_ND, + NEG16r_NF, + NEG16r_NF_ND, + NEG32m, + NEG32m_EVEX, + NEG32m_ND, + NEG32m_NF, + NEG32m_NF_ND, + NEG32r, + NEG32r_EVEX, + NEG32r_ND, + NEG32r_NF, + NEG32r_NF_ND, + NEG64m, + NEG64m_EVEX, + NEG64m_ND, + NEG64m_NF, + NEG64m_NF_ND, + NEG64r, + NEG64r_EVEX, + NEG64r_ND, + NEG64r_NF, + NEG64r_NF_ND, + NEG8m, + NEG8m_EVEX, + NEG8m_ND, + NEG8m_NF, + NEG8m_NF_ND, + NEG8r, + NEG8r_EVEX, + NEG8r_ND, + NEG8r_NF, + NEG8r_NF_ND, + NOOP, + NOOPL, + NOOPLr, + NOOPQ, + NOOPQr, + NOOPW, + NOOPWr, + NOT16m, + NOT16m_EVEX, + NOT16m_ND, + NOT16r, + NOT16r_EVEX, + NOT16r_ND, + NOT32m, + NOT32m_EVEX, + NOT32m_ND, + NOT32r, + NOT32r_EVEX, + NOT32r_ND, + NOT64m, + NOT64m_EVEX, + NOT64m_ND, + NOT64r, + NOT64r_EVEX, + NOT64r_ND, + NOT8m, + NOT8m_EVEX, + NOT8m_ND, + NOT8r, + NOT8r_EVEX, + NOT8r_ND, + OR16i16, + OR16mi, + OR16mi8, + OR16mi8_EVEX, + OR16mi8_ND, + OR16mi8_NF, + OR16mi8_NF_ND, + OR16mi_EVEX, + OR16mi_ND, + OR16mi_NF, + OR16mi_NF_ND, + OR16mr, + OR16mr_EVEX, + OR16mr_ND, + OR16mr_NF, + OR16mr_NF_ND, + OR16ri, + OR16ri8, + OR16ri8_EVEX, + OR16ri8_ND, + OR16ri8_NF, + OR16ri8_NF_ND, + OR16ri_EVEX, + OR16ri_ND, + OR16ri_NF, + OR16ri_NF_ND, + OR16rm, + OR16rm_EVEX, + OR16rm_ND, + OR16rm_NF, + OR16rm_NF_ND, + OR16rr, + OR16rr_EVEX, + OR16rr_EVEX_REV, + OR16rr_ND, + OR16rr_ND_REV, + OR16rr_NF, + OR16rr_NF_ND, + OR16rr_NF_ND_REV, + OR16rr_NF_REV, + OR16rr_REV, + OR32i32, + OR32mi, + OR32mi8, + OR32mi8Locked, + OR32mi8_EVEX, + OR32mi8_ND, + OR32mi8_NF, + OR32mi8_NF_ND, + OR32mi_EVEX, + OR32mi_ND, + OR32mi_NF, + OR32mi_NF_ND, + OR32mr, + OR32mr_EVEX, + OR32mr_ND, + OR32mr_NF, + OR32mr_NF_ND, + OR32ri, + OR32ri8, + OR32ri8_EVEX, + OR32ri8_ND, + OR32ri8_NF, + OR32ri8_NF_ND, + OR32ri_EVEX, + OR32ri_ND, + OR32ri_NF, + OR32ri_NF_ND, + OR32rm, + OR32rm_EVEX, + OR32rm_ND, + OR32rm_NF, + OR32rm_NF_ND, + OR32rr, + OR32rr_EVEX, + OR32rr_EVEX_REV, + OR32rr_ND, + OR32rr_ND_REV, + OR32rr_NF, + OR32rr_NF_ND, + OR32rr_NF_ND_REV, + OR32rr_NF_REV, + OR32rr_REV, + OR64i32, + OR64mi32, + OR64mi32_EVEX, + OR64mi32_ND, + OR64mi32_NF, + OR64mi32_NF_ND, + OR64mi8, + OR64mi8_EVEX, + OR64mi8_ND, + OR64mi8_NF, + OR64mi8_NF_ND, + OR64mr, + OR64mr_EVEX, + OR64mr_ND, + OR64mr_NF, + OR64mr_NF_ND, + OR64ri32, + OR64ri32_EVEX, + OR64ri32_ND, + OR64ri32_NF, + OR64ri32_NF_ND, + OR64ri8, + OR64ri8_EVEX, + OR64ri8_ND, + OR64ri8_NF, + OR64ri8_NF_ND, + OR64rm, + OR64rm_EVEX, + OR64rm_ND, + OR64rm_NF, + OR64rm_NF_ND, + OR64rr, + OR64rr_EVEX, + OR64rr_EVEX_REV, + OR64rr_ND, + OR64rr_ND_REV, + OR64rr_NF, + OR64rr_NF_ND, + OR64rr_NF_ND_REV, + OR64rr_NF_REV, + OR64rr_REV, + OR8i8, + OR8mi, + OR8mi8, + OR8mi_EVEX, + OR8mi_ND, + OR8mi_NF, + OR8mi_NF_ND, + OR8mr, + OR8mr_EVEX, + OR8mr_ND, + OR8mr_NF, + OR8mr_NF_ND, + OR8ri, + OR8ri8, + OR8ri_EVEX, + OR8ri_ND, + OR8ri_NF, + OR8ri_NF_ND, + OR8rm, + OR8rm_EVEX, + OR8rm_ND, + OR8rm_NF, + OR8rm_NF_ND, + OR8rr, + OR8rr_EVEX, + OR8rr_EVEX_REV, + OR8rr_ND, + OR8rr_ND_REV, + OR8rr_NF, + OR8rr_NF_ND, + OR8rr_NF_ND_REV, + OR8rr_NF_REV, + OR8rr_REV, + ORPDrm, + ORPDrr, + ORPSrm, + ORPSrr, + OUT16ir, + OUT16rr, + OUT32ir, + OUT32rr, + OUT8ir, + OUT8rr, + OUTSB, + OUTSL, + OUTSW, + PABSBrm, + PABSBrr, + PABSDrm, + PABSDrr, + PABSWrm, + PABSWrr, + PACKSSDWrm, + PACKSSDWrr, + PACKSSWBrm, + PACKSSWBrr, + PACKUSDWrm, + PACKUSDWrr, + PACKUSWBrm, + PACKUSWBrr, + PADDBrm, + PADDBrr, + PADDDrm, + PADDDrr, + PADDQrm, + PADDQrr, + PADDSBrm, + PADDSBrr, + PADDSWrm, + PADDSWrr, + PADDUSBrm, + PADDUSBrr, + PADDUSWrm, + PADDUSWrr, + PADDWrm, + PADDWrr, + PALIGNRrmi, + PALIGNRrri, + PANDNrm, + PANDNrr, + PANDrm, + PANDrr, + PAUSE, + PAVGBrm, + PAVGBrr, + PAVGUSBrm, + PAVGUSBrr, + PAVGWrm, + PAVGWrr, + PBLENDVBrm0, + PBLENDVBrr0, + PBLENDWrmi, + PBLENDWrri, + PBNDKB, + PCLMULQDQrmi, + PCLMULQDQrri, + PCMPEQBrm, + PCMPEQBrr, + PCMPEQDrm, + PCMPEQDrr, + PCMPEQQrm, + PCMPEQQrr, + PCMPEQWrm, + PCMPEQWrr, + PCMPESTRIrmi, + PCMPESTRIrri, + PCMPESTRMrmi, + PCMPESTRMrri, + PCMPGTBrm, + PCMPGTBrr, + PCMPGTDrm, + PCMPGTDrr, + PCMPGTQrm, + PCMPGTQrr, + PCMPGTWrm, + PCMPGTWrr, + PCMPISTRIrmi, + PCMPISTRIrri, + PCMPISTRMrmi, + PCMPISTRMrri, + PCONFIG, + PDEP32rm, + PDEP32rm_EVEX, + PDEP32rr, + PDEP32rr_EVEX, + PDEP64rm, + PDEP64rm_EVEX, + PDEP64rr, + PDEP64rr_EVEX, + PEXT32rm, + PEXT32rm_EVEX, + PEXT32rr, + PEXT32rr_EVEX, + PEXT64rm, + PEXT64rm_EVEX, + PEXT64rr, + PEXT64rr_EVEX, + PEXTRBmri, + PEXTRBrri, + PEXTRDmri, + PEXTRDrri, + PEXTRQmri, + PEXTRQrri, + PEXTRWmri, + PEXTRWrri, + PEXTRWrri_REV, + PF2IDrm, + PF2IDrr, + PF2IWrm, + PF2IWrr, + PFACCrm, + PFACCrr, + PFADDrm, + PFADDrr, + PFCMPEQrm, + PFCMPEQrr, + PFCMPGErm, + PFCMPGErr, + PFCMPGTrm, + PFCMPGTrr, + PFMAXrm, + PFMAXrr, + PFMINrm, + PFMINrr, + PFMULrm, + PFMULrr, + PFNACCrm, + PFNACCrr, + PFPNACCrm, + PFPNACCrr, + PFRCPIT1rm, + PFRCPIT1rr, + PFRCPIT2rm, + PFRCPIT2rr, + PFRCPrm, + PFRCPrr, + PFRSQIT1rm, + PFRSQIT1rr, + PFRSQRTrm, + PFRSQRTrr, + PFSUBRrm, + PFSUBRrr, + PFSUBrm, + PFSUBrr, + PHADDDrm, + PHADDDrr, + PHADDSWrm, + PHADDSWrr, + PHADDWrm, + PHADDWrr, + PHMINPOSUWrm, + PHMINPOSUWrr, + PHSUBDrm, + PHSUBDrr, + PHSUBSWrm, + PHSUBSWrr, + PHSUBWrm, + PHSUBWrr, + PI2FDrm, + PI2FDrr, + PI2FWrm, + PI2FWrr, + PINSRBrmi, + PINSRBrri, + PINSRDrmi, + PINSRDrri, + PINSRQrmi, + PINSRQrri, + PINSRWrmi, + PINSRWrri, + PMADDUBSWrm, + PMADDUBSWrr, + PMADDWDrm, + PMADDWDrr, + PMAXSBrm, + PMAXSBrr, + PMAXSDrm, + PMAXSDrr, + PMAXSWrm, + PMAXSWrr, + PMAXUBrm, + PMAXUBrr, + PMAXUDrm, + PMAXUDrr, + PMAXUWrm, + PMAXUWrr, + PMINSBrm, + PMINSBrr, + PMINSDrm, + PMINSDrr, + PMINSWrm, + PMINSWrr, + PMINUBrm, + PMINUBrr, + PMINUDrm, + PMINUDrr, + PMINUWrm, + PMINUWrr, + PMOVMSKBrr, + PMOVSXBDrm, + PMOVSXBDrr, + PMOVSXBQrm, + PMOVSXBQrr, + PMOVSXBWrm, + PMOVSXBWrr, + PMOVSXDQrm, + PMOVSXDQrr, + PMOVSXWDrm, + PMOVSXWDrr, + PMOVSXWQrm, + PMOVSXWQrr, + PMOVZXBDrm, + PMOVZXBDrr, + PMOVZXBQrm, + PMOVZXBQrr, + PMOVZXBWrm, + PMOVZXBWrr, + PMOVZXDQrm, + PMOVZXDQrr, + PMOVZXWDrm, + PMOVZXWDrr, + PMOVZXWQrm, + PMOVZXWQrr, + PMULDQrm, + PMULDQrr, + PMULHRSWrm, + PMULHRSWrr, + PMULHRWrm, + PMULHRWrr, + PMULHUWrm, + PMULHUWrr, + PMULHWrm, + PMULHWrr, + PMULLDrm, + PMULLDrr, + PMULLWrm, + PMULLWrr, + PMULUDQrm, + PMULUDQrr, + POP16r, + POP16rmm, + POP16rmr, + POP2, + POP2P, + POP32r, + POP32rmm, + POP32rmr, + POP64r, + POP64rmm, + POP64rmr, + POPA16, + POPA32, + POPCNT16rm, + POPCNT16rm_EVEX, + POPCNT16rm_NF, + POPCNT16rr, + POPCNT16rr_EVEX, + POPCNT16rr_NF, + POPCNT32rm, + POPCNT32rm_EVEX, + POPCNT32rm_NF, + POPCNT32rr, + POPCNT32rr_EVEX, + POPCNT32rr_NF, + POPCNT64rm, + POPCNT64rm_EVEX, + POPCNT64rm_NF, + POPCNT64rr, + POPCNT64rr_EVEX, + POPCNT64rr_NF, + POPDS16, + POPDS32, + POPES16, + POPES32, + POPF16, + POPF32, + POPF64, + POPFS16, + POPFS32, + POPFS64, + POPGS16, + POPGS32, + POPGS64, + POPP64r, + POPSS16, + POPSS32, + PORrm, + PORrr, + PREFETCH, + PREFETCHIT0, + PREFETCHIT1, + PREFETCHNTA, + PREFETCHRST2, + PREFETCHT0, + PREFETCHT1, + PREFETCHT2, + PREFETCHW, + PREFETCHWT1, + PROBED_ALLOCA_32, + PROBED_ALLOCA_64, + PSADBWrm, + PSADBWrr, + PSHUFBrm, + PSHUFBrr, + PSHUFDmi, + PSHUFDri, + PSHUFHWmi, + PSHUFHWri, + PSHUFLWmi, + PSHUFLWri, + PSIGNBrm, + PSIGNBrr, + PSIGNDrm, + PSIGNDrr, + PSIGNWrm, + PSIGNWrr, + PSLLDQri, + PSLLDri, + PSLLDrm, + PSLLDrr, + PSLLQri, + PSLLQrm, + PSLLQrr, + PSLLWri, + PSLLWrm, + PSLLWrr, + PSMASH, + PSRADri, + PSRADrm, + PSRADrr, + PSRAWri, + PSRAWrm, + PSRAWrr, + PSRLDQri, + PSRLDri, + PSRLDrm, + PSRLDrr, + PSRLQri, + PSRLQrm, + PSRLQrr, + PSRLWri, + PSRLWrm, + PSRLWrr, + PSUBBrm, + PSUBBrr, + PSUBDrm, + PSUBDrr, + PSUBQrm, + PSUBQrr, + PSUBSBrm, + PSUBSBrr, + PSUBSWrm, + PSUBSWrr, + PSUBUSBrm, + PSUBUSBrr, + PSUBUSWrm, + PSUBUSWrr, + PSUBWrm, + PSUBWrr, + PSWAPDrm, + PSWAPDrr, + PTCMMIMFP16PS, + PTCMMIMFP16PSV, + PTCMMRLFP16PS, + PTCMMRLFP16PSV, + PTCVTROWD2PSrre, + PTCVTROWD2PSrreV, + PTCVTROWD2PSrri, + PTCVTROWD2PSrriV, + PTCVTROWPS2BF16Hrre, + PTCVTROWPS2BF16HrreV, + PTCVTROWPS2BF16Hrri, + PTCVTROWPS2BF16HrriV, + PTCVTROWPS2BF16Lrre, + PTCVTROWPS2BF16LrreV, + PTCVTROWPS2BF16Lrri, + PTCVTROWPS2BF16LrriV, + PTCVTROWPS2PHHrre, + PTCVTROWPS2PHHrreV, + PTCVTROWPS2PHHrri, + PTCVTROWPS2PHHrriV, + PTCVTROWPS2PHLrre, + PTCVTROWPS2PHLrreV, + PTCVTROWPS2PHLrri, + PTCVTROWPS2PHLrriV, + PTDPBF16PS, + PTDPBF8PS, + PTDPBF8PSV, + PTDPBHF8PS, + PTDPBHF8PSV, + PTDPBSSD, + PTDPBSUD, + PTDPBUSD, + PTDPBUUD, + PTDPFP16PS, + PTDPHBF8PS, + PTDPHBF8PSV, + PTDPHF8PS, + PTDPHF8PSV, + PTESTrm, + PTESTrr, + PTILELOADD, + PTILELOADDRS, + PTILELOADDRST1, + PTILELOADDT1, + PTILEMOVROWrre, + PTILEMOVROWrreV, + PTILEMOVROWrri, + PTILEMOVROWrriV, + PTILESTORED, + PTILEZERO, + PTMMULTF32PS, + PTMMULTF32PSV, + PTWRITE64m, + PTWRITE64r, + PTWRITEm, + PTWRITEr, + PUNPCKHBWrm, + PUNPCKHBWrr, + PUNPCKHDQrm, + PUNPCKHDQrr, + PUNPCKHQDQrm, + PUNPCKHQDQrr, + PUNPCKHWDrm, + PUNPCKHWDrr, + PUNPCKLBWrm, + PUNPCKLBWrr, + PUNPCKLDQrm, + PUNPCKLDQrr, + PUNPCKLQDQrm, + PUNPCKLQDQrr, + PUNPCKLWDrm, + PUNPCKLWDrr, + PUSH16i, + PUSH16i8, + PUSH16r, + PUSH16rmm, + PUSH16rmr, + PUSH2, + PUSH2P, + PUSH32i, + PUSH32i8, + PUSH32r, + PUSH32rmm, + PUSH32rmr, + PUSH64i32, + PUSH64i8, + PUSH64r, + PUSH64rmm, + PUSH64rmr, + PUSHA16, + PUSHA32, + PUSHCS16, + PUSHCS32, + PUSHDS16, + PUSHDS32, + PUSHES16, + PUSHES32, + PUSHF16, + PUSHF32, + PUSHF64, + PUSHFS16, + PUSHFS32, + PUSHFS64, + PUSHGS16, + PUSHGS32, + PUSHGS64, + PUSHP64r, + PUSHSS16, + PUSHSS32, + PVALIDATE32, + PVALIDATE64, + PXORrm, + PXORrr, + RCL16m1, + RCL16m1_EVEX, + RCL16m1_ND, + RCL16mCL, + RCL16mCL_EVEX, + RCL16mCL_ND, + RCL16mi, + RCL16mi_EVEX, + RCL16mi_ND, + RCL16r1, + RCL16r1_EVEX, + RCL16r1_ND, + RCL16rCL, + RCL16rCL_EVEX, + RCL16rCL_ND, + RCL16ri, + RCL16ri_EVEX, + RCL16ri_ND, + RCL32m1, + RCL32m1_EVEX, + RCL32m1_ND, + RCL32mCL, + RCL32mCL_EVEX, + RCL32mCL_ND, + RCL32mi, + RCL32mi_EVEX, + RCL32mi_ND, + RCL32r1, + RCL32r1_EVEX, + RCL32r1_ND, + RCL32rCL, + RCL32rCL_EVEX, + RCL32rCL_ND, + RCL32ri, + RCL32ri_EVEX, + RCL32ri_ND, + RCL64m1, + RCL64m1_EVEX, + RCL64m1_ND, + RCL64mCL, + RCL64mCL_EVEX, + RCL64mCL_ND, + RCL64mi, + RCL64mi_EVEX, + RCL64mi_ND, + RCL64r1, + RCL64r1_EVEX, + RCL64r1_ND, + RCL64rCL, + RCL64rCL_EVEX, + RCL64rCL_ND, + RCL64ri, + RCL64ri_EVEX, + RCL64ri_ND, + RCL8m1, + RCL8m1_EVEX, + RCL8m1_ND, + RCL8mCL, + RCL8mCL_EVEX, + RCL8mCL_ND, + RCL8mi, + RCL8mi_EVEX, + RCL8mi_ND, + RCL8r1, + RCL8r1_EVEX, + RCL8r1_ND, + RCL8rCL, + RCL8rCL_EVEX, + RCL8rCL_ND, + RCL8ri, + RCL8ri_EVEX, + RCL8ri_ND, + RCPPSm, + RCPPSr, + RCPSSm, + RCPSSm_Int, + RCPSSr, + RCPSSr_Int, + RCR16m1, + RCR16m1_EVEX, + RCR16m1_ND, + RCR16mCL, + RCR16mCL_EVEX, + RCR16mCL_ND, + RCR16mi, + RCR16mi_EVEX, + RCR16mi_ND, + RCR16r1, + RCR16r1_EVEX, + RCR16r1_ND, + RCR16rCL, + RCR16rCL_EVEX, + RCR16rCL_ND, + RCR16ri, + RCR16ri_EVEX, + RCR16ri_ND, + RCR32m1, + RCR32m1_EVEX, + RCR32m1_ND, + RCR32mCL, + RCR32mCL_EVEX, + RCR32mCL_ND, + RCR32mi, + RCR32mi_EVEX, + RCR32mi_ND, + RCR32r1, + RCR32r1_EVEX, + RCR32r1_ND, + RCR32rCL, + RCR32rCL_EVEX, + RCR32rCL_ND, + RCR32ri, + RCR32ri_EVEX, + RCR32ri_ND, + RCR64m1, + RCR64m1_EVEX, + RCR64m1_ND, + RCR64mCL, + RCR64mCL_EVEX, + RCR64mCL_ND, + RCR64mi, + RCR64mi_EVEX, + RCR64mi_ND, + RCR64r1, + RCR64r1_EVEX, + RCR64r1_ND, + RCR64rCL, + RCR64rCL_EVEX, + RCR64rCL_ND, + RCR64ri, + RCR64ri_EVEX, + RCR64ri_ND, + RCR8m1, + RCR8m1_EVEX, + RCR8m1_ND, + RCR8mCL, + RCR8mCL_EVEX, + RCR8mCL_ND, + RCR8mi, + RCR8mi_EVEX, + RCR8mi_ND, + RCR8r1, + RCR8r1_EVEX, + RCR8r1_ND, + RCR8rCL, + RCR8rCL_EVEX, + RCR8rCL_ND, + RCR8ri, + RCR8ri_EVEX, + RCR8ri_ND, + RDFSBASE, + RDFSBASE64, + RDGSBASE, + RDGSBASE64, + RDMSR, + RDMSRLIST, + RDMSRri, + RDMSRri_EVEX, + RDPID32, + RDPID64, + RDPKRUr, + RDPMC, + RDPRU, + RDRAND16r, + RDRAND32r, + RDRAND64r, + RDSEED16r, + RDSEED32r, + RDSEED64r, + RDSSPD, + RDSSPQ, + RDTSC, + RDTSCP, + REPNE_PREFIX, + REP_MOVSB_32, + REP_MOVSB_64, + REP_MOVSD_32, + REP_MOVSD_64, + REP_MOVSQ_32, + REP_MOVSQ_64, + REP_MOVSW_32, + REP_MOVSW_64, + REP_PREFIX, + REP_STOSB_32, + REP_STOSB_64, + REP_STOSD_32, + REP_STOSD_64, + REP_STOSQ_32, + REP_STOSQ_64, + REP_STOSW_32, + REP_STOSW_64, + RET, + RET16, + RET32, + RET64, + RETI16, + RETI32, + RETI64, + REX64_PREFIX, + RMPADJUST, + RMPQUERY, + RMPUPDATE, + ROL16m1, + ROL16m1_EVEX, + ROL16m1_ND, + ROL16m1_NF, + ROL16m1_NF_ND, + ROL16mCL, + ROL16mCL_EVEX, + ROL16mCL_ND, + ROL16mCL_NF, + ROL16mCL_NF_ND, + ROL16mi, + ROL16mi_EVEX, + ROL16mi_ND, + ROL16mi_NF, + ROL16mi_NF_ND, + ROL16r1, + ROL16r1_EVEX, + ROL16r1_ND, + ROL16r1_NF, + ROL16r1_NF_ND, + ROL16rCL, + ROL16rCL_EVEX, + ROL16rCL_ND, + ROL16rCL_NF, + ROL16rCL_NF_ND, + ROL16ri, + ROL16ri_EVEX, + ROL16ri_ND, + ROL16ri_NF, + ROL16ri_NF_ND, + ROL32m1, + ROL32m1_EVEX, + ROL32m1_ND, + ROL32m1_NF, + ROL32m1_NF_ND, + ROL32mCL, + ROL32mCL_EVEX, + ROL32mCL_ND, + ROL32mCL_NF, + ROL32mCL_NF_ND, + ROL32mi, + ROL32mi_EVEX, + ROL32mi_ND, + ROL32mi_NF, + ROL32mi_NF_ND, + ROL32r1, + ROL32r1_EVEX, + ROL32r1_ND, + ROL32r1_NF, + ROL32r1_NF_ND, + ROL32rCL, + ROL32rCL_EVEX, + ROL32rCL_ND, + ROL32rCL_NF, + ROL32rCL_NF_ND, + ROL32ri, + ROL32ri_EVEX, + ROL32ri_ND, + ROL32ri_NF, + ROL32ri_NF_ND, + ROL64m1, + ROL64m1_EVEX, + ROL64m1_ND, + ROL64m1_NF, + ROL64m1_NF_ND, + ROL64mCL, + ROL64mCL_EVEX, + ROL64mCL_ND, + ROL64mCL_NF, + ROL64mCL_NF_ND, + ROL64mi, + ROL64mi_EVEX, + ROL64mi_ND, + ROL64mi_NF, + ROL64mi_NF_ND, + ROL64r1, + ROL64r1_EVEX, + ROL64r1_ND, + ROL64r1_NF, + ROL64r1_NF_ND, + ROL64rCL, + ROL64rCL_EVEX, + ROL64rCL_ND, + ROL64rCL_NF, + ROL64rCL_NF_ND, + ROL64ri, + ROL64ri_EVEX, + ROL64ri_ND, + ROL64ri_NF, + ROL64ri_NF_ND, + ROL8m1, + ROL8m1_EVEX, + ROL8m1_ND, + ROL8m1_NF, + ROL8m1_NF_ND, + ROL8mCL, + ROL8mCL_EVEX, + ROL8mCL_ND, + ROL8mCL_NF, + ROL8mCL_NF_ND, + ROL8mi, + ROL8mi_EVEX, + ROL8mi_ND, + ROL8mi_NF, + ROL8mi_NF_ND, + ROL8r1, + ROL8r1_EVEX, + ROL8r1_ND, + ROL8r1_NF, + ROL8r1_NF_ND, + ROL8rCL, + ROL8rCL_EVEX, + ROL8rCL_ND, + ROL8rCL_NF, + ROL8rCL_NF_ND, + ROL8ri, + ROL8ri_EVEX, + ROL8ri_ND, + ROL8ri_NF, + ROL8ri_NF_ND, + ROR16m1, + ROR16m1_EVEX, + ROR16m1_ND, + ROR16m1_NF, + ROR16m1_NF_ND, + ROR16mCL, + ROR16mCL_EVEX, + ROR16mCL_ND, + ROR16mCL_NF, + ROR16mCL_NF_ND, + ROR16mi, + ROR16mi_EVEX, + ROR16mi_ND, + ROR16mi_NF, + ROR16mi_NF_ND, + ROR16r1, + ROR16r1_EVEX, + ROR16r1_ND, + ROR16r1_NF, + ROR16r1_NF_ND, + ROR16rCL, + ROR16rCL_EVEX, + ROR16rCL_ND, + ROR16rCL_NF, + ROR16rCL_NF_ND, + ROR16ri, + ROR16ri_EVEX, + ROR16ri_ND, + ROR16ri_NF, + ROR16ri_NF_ND, + ROR32m1, + ROR32m1_EVEX, + ROR32m1_ND, + ROR32m1_NF, + ROR32m1_NF_ND, + ROR32mCL, + ROR32mCL_EVEX, + ROR32mCL_ND, + ROR32mCL_NF, + ROR32mCL_NF_ND, + ROR32mi, + ROR32mi_EVEX, + ROR32mi_ND, + ROR32mi_NF, + ROR32mi_NF_ND, + ROR32r1, + ROR32r1_EVEX, + ROR32r1_ND, + ROR32r1_NF, + ROR32r1_NF_ND, + ROR32rCL, + ROR32rCL_EVEX, + ROR32rCL_ND, + ROR32rCL_NF, + ROR32rCL_NF_ND, + ROR32ri, + ROR32ri_EVEX, + ROR32ri_ND, + ROR32ri_NF, + ROR32ri_NF_ND, + ROR64m1, + ROR64m1_EVEX, + ROR64m1_ND, + ROR64m1_NF, + ROR64m1_NF_ND, + ROR64mCL, + ROR64mCL_EVEX, + ROR64mCL_ND, + ROR64mCL_NF, + ROR64mCL_NF_ND, + ROR64mi, + ROR64mi_EVEX, + ROR64mi_ND, + ROR64mi_NF, + ROR64mi_NF_ND, + ROR64r1, + ROR64r1_EVEX, + ROR64r1_ND, + ROR64r1_NF, + ROR64r1_NF_ND, + ROR64rCL, + ROR64rCL_EVEX, + ROR64rCL_ND, + ROR64rCL_NF, + ROR64rCL_NF_ND, + ROR64ri, + ROR64ri_EVEX, + ROR64ri_ND, + ROR64ri_NF, + ROR64ri_NF_ND, + ROR8m1, + ROR8m1_EVEX, + ROR8m1_ND, + ROR8m1_NF, + ROR8m1_NF_ND, + ROR8mCL, + ROR8mCL_EVEX, + ROR8mCL_ND, + ROR8mCL_NF, + ROR8mCL_NF_ND, + ROR8mi, + ROR8mi_EVEX, + ROR8mi_ND, + ROR8mi_NF, + ROR8mi_NF_ND, + ROR8r1, + ROR8r1_EVEX, + ROR8r1_ND, + ROR8r1_NF, + ROR8r1_NF_ND, + ROR8rCL, + ROR8rCL_EVEX, + ROR8rCL_ND, + ROR8rCL_NF, + ROR8rCL_NF_ND, + ROR8ri, + ROR8ri_EVEX, + ROR8ri_ND, + ROR8ri_NF, + ROR8ri_NF_ND, + RORX32mi, + RORX32mi_EVEX, + RORX32ri, + RORX32ri_EVEX, + RORX64mi, + RORX64mi_EVEX, + RORX64ri, + RORX64ri_EVEX, + ROUNDPDmi, + ROUNDPDri, + ROUNDPSmi, + ROUNDPSri, + ROUNDSDmi, + ROUNDSDmi_Int, + ROUNDSDri, + ROUNDSDri_Int, + ROUNDSSmi, + ROUNDSSmi_Int, + ROUNDSSri, + ROUNDSSri_Int, + RSM, + RSQRTPSm, + RSQRTPSr, + RSQRTSSm, + RSQRTSSm_Int, + RSQRTSSr, + RSQRTSSr_Int, + RSTORSSP, + SAHF, + SALC, + SAR16m1, + SAR16m1_EVEX, + SAR16m1_ND, + SAR16m1_NF, + SAR16m1_NF_ND, + SAR16mCL, + SAR16mCL_EVEX, + SAR16mCL_ND, + SAR16mCL_NF, + SAR16mCL_NF_ND, + SAR16mi, + SAR16mi_EVEX, + SAR16mi_ND, + SAR16mi_NF, + SAR16mi_NF_ND, + SAR16r1, + SAR16r1_EVEX, + SAR16r1_ND, + SAR16r1_NF, + SAR16r1_NF_ND, + SAR16rCL, + SAR16rCL_EVEX, + SAR16rCL_ND, + SAR16rCL_NF, + SAR16rCL_NF_ND, + SAR16ri, + SAR16ri_EVEX, + SAR16ri_ND, + SAR16ri_NF, + SAR16ri_NF_ND, + SAR32m1, + SAR32m1_EVEX, + SAR32m1_ND, + SAR32m1_NF, + SAR32m1_NF_ND, + SAR32mCL, + SAR32mCL_EVEX, + SAR32mCL_ND, + SAR32mCL_NF, + SAR32mCL_NF_ND, + SAR32mi, + SAR32mi_EVEX, + SAR32mi_ND, + SAR32mi_NF, + SAR32mi_NF_ND, + SAR32r1, + SAR32r1_EVEX, + SAR32r1_ND, + SAR32r1_NF, + SAR32r1_NF_ND, + SAR32rCL, + SAR32rCL_EVEX, + SAR32rCL_ND, + SAR32rCL_NF, + SAR32rCL_NF_ND, + SAR32ri, + SAR32ri_EVEX, + SAR32ri_ND, + SAR32ri_NF, + SAR32ri_NF_ND, + SAR64m1, + SAR64m1_EVEX, + SAR64m1_ND, + SAR64m1_NF, + SAR64m1_NF_ND, + SAR64mCL, + SAR64mCL_EVEX, + SAR64mCL_ND, + SAR64mCL_NF, + SAR64mCL_NF_ND, + SAR64mi, + SAR64mi_EVEX, + SAR64mi_ND, + SAR64mi_NF, + SAR64mi_NF_ND, + SAR64r1, + SAR64r1_EVEX, + SAR64r1_ND, + SAR64r1_NF, + SAR64r1_NF_ND, + SAR64rCL, + SAR64rCL_EVEX, + SAR64rCL_ND, + SAR64rCL_NF, + SAR64rCL_NF_ND, + SAR64ri, + SAR64ri_EVEX, + SAR64ri_ND, + SAR64ri_NF, + SAR64ri_NF_ND, + SAR8m1, + SAR8m1_EVEX, + SAR8m1_ND, + SAR8m1_NF, + SAR8m1_NF_ND, + SAR8mCL, + SAR8mCL_EVEX, + SAR8mCL_ND, + SAR8mCL_NF, + SAR8mCL_NF_ND, + SAR8mi, + SAR8mi_EVEX, + SAR8mi_ND, + SAR8mi_NF, + SAR8mi_NF_ND, + SAR8r1, + SAR8r1_EVEX, + SAR8r1_ND, + SAR8r1_NF, + SAR8r1_NF_ND, + SAR8rCL, + SAR8rCL_EVEX, + SAR8rCL_ND, + SAR8rCL_NF, + SAR8rCL_NF_ND, + SAR8ri, + SAR8ri_EVEX, + SAR8ri_ND, + SAR8ri_NF, + SAR8ri_NF_ND, + SARX32rm, + SARX32rm_EVEX, + SARX32rr, + SARX32rr_EVEX, + SARX64rm, + SARX64rm_EVEX, + SARX64rr, + SARX64rr_EVEX, + SAVEPREVSSP, + SBB16i16, + SBB16mi, + SBB16mi8, + SBB16mi8_EVEX, + SBB16mi8_ND, + SBB16mi_EVEX, + SBB16mi_ND, + SBB16mr, + SBB16mr_EVEX, + SBB16mr_ND, + SBB16ri, + SBB16ri8, + SBB16ri8_EVEX, + SBB16ri8_ND, + SBB16ri_EVEX, + SBB16ri_ND, + SBB16rm, + SBB16rm_EVEX, + SBB16rm_ND, + SBB16rr, + SBB16rr_EVEX, + SBB16rr_EVEX_REV, + SBB16rr_ND, + SBB16rr_ND_REV, + SBB16rr_REV, + SBB32i32, + SBB32mi, + SBB32mi8, + SBB32mi8_EVEX, + SBB32mi8_ND, + SBB32mi_EVEX, + SBB32mi_ND, + SBB32mr, + SBB32mr_EVEX, + SBB32mr_ND, + SBB32ri, + SBB32ri8, + SBB32ri8_EVEX, + SBB32ri8_ND, + SBB32ri_EVEX, + SBB32ri_ND, + SBB32rm, + SBB32rm_EVEX, + SBB32rm_ND, + SBB32rr, + SBB32rr_EVEX, + SBB32rr_EVEX_REV, + SBB32rr_ND, + SBB32rr_ND_REV, + SBB32rr_REV, + SBB64i32, + SBB64mi32, + SBB64mi32_EVEX, + SBB64mi32_ND, + SBB64mi8, + SBB64mi8_EVEX, + SBB64mi8_ND, + SBB64mr, + SBB64mr_EVEX, + SBB64mr_ND, + SBB64ri32, + SBB64ri32_EVEX, + SBB64ri32_ND, + SBB64ri8, + SBB64ri8_EVEX, + SBB64ri8_ND, + SBB64rm, + SBB64rm_EVEX, + SBB64rm_ND, + SBB64rr, + SBB64rr_EVEX, + SBB64rr_EVEX_REV, + SBB64rr_ND, + SBB64rr_ND_REV, + SBB64rr_REV, + SBB8i8, + SBB8mi, + SBB8mi8, + SBB8mi_EVEX, + SBB8mi_ND, + SBB8mr, + SBB8mr_EVEX, + SBB8mr_ND, + SBB8ri, + SBB8ri8, + SBB8ri_EVEX, + SBB8ri_ND, + SBB8rm, + SBB8rm_EVEX, + SBB8rm_ND, + SBB8rr, + SBB8rr_EVEX, + SBB8rr_EVEX_REV, + SBB8rr_ND, + SBB8rr_ND_REV, + SBB8rr_REV, + SCASB, + SCASL, + SCASQ, + SCASW, + SEAMCALL, + SEAMOPS, + SEAMRET, + SEG_ALLOCA_32, + SEG_ALLOCA_64, + SENDUIPI, + SERIALIZE, + SETCCm, + SETCCm_EVEX, + SETCCr, + SETCCr_EVEX, + SETSSBSY, + SETZUCCm, + SETZUCCr, + SFENCE, + SGDT16m, + SGDT32m, + SGDT64m, + SHA1MSG1rm, + SHA1MSG1rr, + SHA1MSG2rm, + SHA1MSG2rr, + SHA1NEXTErm, + SHA1NEXTErr, + SHA1RNDS4rmi, + SHA1RNDS4rri, + SHA256MSG1rm, + SHA256MSG1rr, + SHA256MSG2rm, + SHA256MSG2rr, + SHA256RNDS2rm, + SHA256RNDS2rr, + SHL16m1, + SHL16m1_EVEX, + SHL16m1_ND, + SHL16m1_NF, + SHL16m1_NF_ND, + SHL16mCL, + SHL16mCL_EVEX, + SHL16mCL_ND, + SHL16mCL_NF, + SHL16mCL_NF_ND, + SHL16mi, + SHL16mi_EVEX, + SHL16mi_ND, + SHL16mi_NF, + SHL16mi_NF_ND, + SHL16r1, + SHL16r1_EVEX, + SHL16r1_ND, + SHL16r1_NF, + SHL16r1_NF_ND, + SHL16rCL, + SHL16rCL_EVEX, + SHL16rCL_ND, + SHL16rCL_NF, + SHL16rCL_NF_ND, + SHL16ri, + SHL16ri_EVEX, + SHL16ri_ND, + SHL16ri_NF, + SHL16ri_NF_ND, + SHL32m1, + SHL32m1_EVEX, + SHL32m1_ND, + SHL32m1_NF, + SHL32m1_NF_ND, + SHL32mCL, + SHL32mCL_EVEX, + SHL32mCL_ND, + SHL32mCL_NF, + SHL32mCL_NF_ND, + SHL32mi, + SHL32mi_EVEX, + SHL32mi_ND, + SHL32mi_NF, + SHL32mi_NF_ND, + SHL32r1, + SHL32r1_EVEX, + SHL32r1_ND, + SHL32r1_NF, + SHL32r1_NF_ND, + SHL32rCL, + SHL32rCL_EVEX, + SHL32rCL_ND, + SHL32rCL_NF, + SHL32rCL_NF_ND, + SHL32ri, + SHL32ri_EVEX, + SHL32ri_ND, + SHL32ri_NF, + SHL32ri_NF_ND, + SHL64m1, + SHL64m1_EVEX, + SHL64m1_ND, + SHL64m1_NF, + SHL64m1_NF_ND, + SHL64mCL, + SHL64mCL_EVEX, + SHL64mCL_ND, + SHL64mCL_NF, + SHL64mCL_NF_ND, + SHL64mi, + SHL64mi_EVEX, + SHL64mi_ND, + SHL64mi_NF, + SHL64mi_NF_ND, + SHL64r1, + SHL64r1_EVEX, + SHL64r1_ND, + SHL64r1_NF, + SHL64r1_NF_ND, + SHL64rCL, + SHL64rCL_EVEX, + SHL64rCL_ND, + SHL64rCL_NF, + SHL64rCL_NF_ND, + SHL64ri, + SHL64ri_EVEX, + SHL64ri_ND, + SHL64ri_NF, + SHL64ri_NF_ND, + SHL8m1, + SHL8m1_EVEX, + SHL8m1_ND, + SHL8m1_NF, + SHL8m1_NF_ND, + SHL8mCL, + SHL8mCL_EVEX, + SHL8mCL_ND, + SHL8mCL_NF, + SHL8mCL_NF_ND, + SHL8mi, + SHL8mi_EVEX, + SHL8mi_ND, + SHL8mi_NF, + SHL8mi_NF_ND, + SHL8r1, + SHL8r1_EVEX, + SHL8r1_ND, + SHL8r1_NF, + SHL8r1_NF_ND, + SHL8rCL, + SHL8rCL_EVEX, + SHL8rCL_ND, + SHL8rCL_NF, + SHL8rCL_NF_ND, + SHL8ri, + SHL8ri_EVEX, + SHL8ri_ND, + SHL8ri_NF, + SHL8ri_NF_ND, + SHLD16mrCL, + SHLD16mrCL_EVEX, + SHLD16mrCL_ND, + SHLD16mrCL_NF, + SHLD16mrCL_NF_ND, + SHLD16mri8, + SHLD16mri8_EVEX, + SHLD16mri8_ND, + SHLD16mri8_NF, + SHLD16mri8_NF_ND, + SHLD16rrCL, + SHLD16rrCL_EVEX, + SHLD16rrCL_ND, + SHLD16rrCL_NF, + SHLD16rrCL_NF_ND, + SHLD16rri8, + SHLD16rri8_EVEX, + SHLD16rri8_ND, + SHLD16rri8_NF, + SHLD16rri8_NF_ND, + SHLD32mrCL, + SHLD32mrCL_EVEX, + SHLD32mrCL_ND, + SHLD32mrCL_NF, + SHLD32mrCL_NF_ND, + SHLD32mri8, + SHLD32mri8_EVEX, + SHLD32mri8_ND, + SHLD32mri8_NF, + SHLD32mri8_NF_ND, + SHLD32rrCL, + SHLD32rrCL_EVEX, + SHLD32rrCL_ND, + SHLD32rrCL_NF, + SHLD32rrCL_NF_ND, + SHLD32rri8, + SHLD32rri8_EVEX, + SHLD32rri8_ND, + SHLD32rri8_NF, + SHLD32rri8_NF_ND, + SHLD64mrCL, + SHLD64mrCL_EVEX, + SHLD64mrCL_ND, + SHLD64mrCL_NF, + SHLD64mrCL_NF_ND, + SHLD64mri8, + SHLD64mri8_EVEX, + SHLD64mri8_ND, + SHLD64mri8_NF, + SHLD64mri8_NF_ND, + SHLD64rrCL, + SHLD64rrCL_EVEX, + SHLD64rrCL_ND, + SHLD64rrCL_NF, + SHLD64rrCL_NF_ND, + SHLD64rri8, + SHLD64rri8_EVEX, + SHLD64rri8_ND, + SHLD64rri8_NF, + SHLD64rri8_NF_ND, + SHLX32rm, + SHLX32rm_EVEX, + SHLX32rr, + SHLX32rr_EVEX, + SHLX64rm, + SHLX64rm_EVEX, + SHLX64rr, + SHLX64rr_EVEX, + SHR16m1, + SHR16m1_EVEX, + SHR16m1_ND, + SHR16m1_NF, + SHR16m1_NF_ND, + SHR16mCL, + SHR16mCL_EVEX, + SHR16mCL_ND, + SHR16mCL_NF, + SHR16mCL_NF_ND, + SHR16mi, + SHR16mi_EVEX, + SHR16mi_ND, + SHR16mi_NF, + SHR16mi_NF_ND, + SHR16r1, + SHR16r1_EVEX, + SHR16r1_ND, + SHR16r1_NF, + SHR16r1_NF_ND, + SHR16rCL, + SHR16rCL_EVEX, + SHR16rCL_ND, + SHR16rCL_NF, + SHR16rCL_NF_ND, + SHR16ri, + SHR16ri_EVEX, + SHR16ri_ND, + SHR16ri_NF, + SHR16ri_NF_ND, + SHR32m1, + SHR32m1_EVEX, + SHR32m1_ND, + SHR32m1_NF, + SHR32m1_NF_ND, + SHR32mCL, + SHR32mCL_EVEX, + SHR32mCL_ND, + SHR32mCL_NF, + SHR32mCL_NF_ND, + SHR32mi, + SHR32mi_EVEX, + SHR32mi_ND, + SHR32mi_NF, + SHR32mi_NF_ND, + SHR32r1, + SHR32r1_EVEX, + SHR32r1_ND, + SHR32r1_NF, + SHR32r1_NF_ND, + SHR32rCL, + SHR32rCL_EVEX, + SHR32rCL_ND, + SHR32rCL_NF, + SHR32rCL_NF_ND, + SHR32ri, + SHR32ri_EVEX, + SHR32ri_ND, + SHR32ri_NF, + SHR32ri_NF_ND, + SHR64m1, + SHR64m1_EVEX, + SHR64m1_ND, + SHR64m1_NF, + SHR64m1_NF_ND, + SHR64mCL, + SHR64mCL_EVEX, + SHR64mCL_ND, + SHR64mCL_NF, + SHR64mCL_NF_ND, + SHR64mi, + SHR64mi_EVEX, + SHR64mi_ND, + SHR64mi_NF, + SHR64mi_NF_ND, + SHR64r1, + SHR64r1_EVEX, + SHR64r1_ND, + SHR64r1_NF, + SHR64r1_NF_ND, + SHR64rCL, + SHR64rCL_EVEX, + SHR64rCL_ND, + SHR64rCL_NF, + SHR64rCL_NF_ND, + SHR64ri, + SHR64ri_EVEX, + SHR64ri_ND, + SHR64ri_NF, + SHR64ri_NF_ND, + SHR8m1, + SHR8m1_EVEX, + SHR8m1_ND, + SHR8m1_NF, + SHR8m1_NF_ND, + SHR8mCL, + SHR8mCL_EVEX, + SHR8mCL_ND, + SHR8mCL_NF, + SHR8mCL_NF_ND, + SHR8mi, + SHR8mi_EVEX, + SHR8mi_ND, + SHR8mi_NF, + SHR8mi_NF_ND, + SHR8r1, + SHR8r1_EVEX, + SHR8r1_ND, + SHR8r1_NF, + SHR8r1_NF_ND, + SHR8rCL, + SHR8rCL_EVEX, + SHR8rCL_ND, + SHR8rCL_NF, + SHR8rCL_NF_ND, + SHR8ri, + SHR8ri_EVEX, + SHR8ri_ND, + SHR8ri_NF, + SHR8ri_NF_ND, + SHRD16mrCL, + SHRD16mrCL_EVEX, + SHRD16mrCL_ND, + SHRD16mrCL_NF, + SHRD16mrCL_NF_ND, + SHRD16mri8, + SHRD16mri8_EVEX, + SHRD16mri8_ND, + SHRD16mri8_NF, + SHRD16mri8_NF_ND, + SHRD16rrCL, + SHRD16rrCL_EVEX, + SHRD16rrCL_ND, + SHRD16rrCL_NF, + SHRD16rrCL_NF_ND, + SHRD16rri8, + SHRD16rri8_EVEX, + SHRD16rri8_ND, + SHRD16rri8_NF, + SHRD16rri8_NF_ND, + SHRD32mrCL, + SHRD32mrCL_EVEX, + SHRD32mrCL_ND, + SHRD32mrCL_NF, + SHRD32mrCL_NF_ND, + SHRD32mri8, + SHRD32mri8_EVEX, + SHRD32mri8_ND, + SHRD32mri8_NF, + SHRD32mri8_NF_ND, + SHRD32rrCL, + SHRD32rrCL_EVEX, + SHRD32rrCL_ND, + SHRD32rrCL_NF, + SHRD32rrCL_NF_ND, + SHRD32rri8, + SHRD32rri8_EVEX, + SHRD32rri8_ND, + SHRD32rri8_NF, + SHRD32rri8_NF_ND, + SHRD64mrCL, + SHRD64mrCL_EVEX, + SHRD64mrCL_ND, + SHRD64mrCL_NF, + SHRD64mrCL_NF_ND, + SHRD64mri8, + SHRD64mri8_EVEX, + SHRD64mri8_ND, + SHRD64mri8_NF, + SHRD64mri8_NF_ND, + SHRD64rrCL, + SHRD64rrCL_EVEX, + SHRD64rrCL_ND, + SHRD64rrCL_NF, + SHRD64rrCL_NF_ND, + SHRD64rri8, + SHRD64rri8_EVEX, + SHRD64rri8_ND, + SHRD64rri8_NF, + SHRD64rri8_NF_ND, + SHRX32rm, + SHRX32rm_EVEX, + SHRX32rr, + SHRX32rr_EVEX, + SHRX64rm, + SHRX64rm_EVEX, + SHRX64rr, + SHRX64rr_EVEX, + SHUFPDrmi, + SHUFPDrri, + SHUFPSrmi, + SHUFPSrri, + SIDT16m, + SIDT32m, + SIDT64m, + SKINIT, + SLDT16m, + SLDT16r, + SLDT32r, + SLDT64r, + SLWPCB, + SLWPCB64, + SMSW16m, + SMSW16r, + SMSW32r, + SMSW64r, + SQRTPDm, + SQRTPDr, + SQRTPSm, + SQRTPSr, + SQRTSDm, + SQRTSDm_Int, + SQRTSDr, + SQRTSDr_Int, + SQRTSSm, + SQRTSSm_Int, + SQRTSSr, + SQRTSSr_Int, + SQRT_F, + SQRT_Fp32, + SQRT_Fp64, + SQRT_Fp80, + SS_PREFIX, + STAC, + STACKALLOC_W_PROBING, + STC, + STD, + STGI, + STI, + STMXCSR, + STOSB, + STOSL, + STOSQ, + STOSW, + STR16r, + STR32r, + STR64r, + STRm, + STTILECFG, + STTILECFG_EVEX, + STUI, + ST_F32m, + ST_F64m, + ST_FP32m, + ST_FP64m, + ST_FP80m, + ST_FPrr, + ST_Fp32m, + ST_Fp64m, + ST_Fp64m32, + ST_Fp80m32, + ST_Fp80m64, + ST_FpP32m, + ST_FpP64m, + ST_FpP64m32, + ST_FpP80m, + ST_FpP80m32, + ST_FpP80m64, + ST_Frr, + SUB16i16, + SUB16mi, + SUB16mi8, + SUB16mi8_EVEX, + SUB16mi8_ND, + SUB16mi8_NF, + SUB16mi8_NF_ND, + SUB16mi_EVEX, + SUB16mi_ND, + SUB16mi_NF, + SUB16mi_NF_ND, + SUB16mr, + SUB16mr_EVEX, + SUB16mr_ND, + SUB16mr_NF, + SUB16mr_NF_ND, + SUB16ri, + SUB16ri8, + SUB16ri8_EVEX, + SUB16ri8_ND, + SUB16ri8_NF, + SUB16ri8_NF_ND, + SUB16ri_EVEX, + SUB16ri_ND, + SUB16ri_NF, + SUB16ri_NF_ND, + SUB16rm, + SUB16rm_EVEX, + SUB16rm_ND, + SUB16rm_NF, + SUB16rm_NF_ND, + SUB16rr, + SUB16rr_EVEX, + SUB16rr_EVEX_REV, + SUB16rr_ND, + SUB16rr_ND_REV, + SUB16rr_NF, + SUB16rr_NF_ND, + SUB16rr_NF_ND_REV, + SUB16rr_NF_REV, + SUB16rr_REV, + SUB32i32, + SUB32mi, + SUB32mi8, + SUB32mi8_EVEX, + SUB32mi8_ND, + SUB32mi8_NF, + SUB32mi8_NF_ND, + SUB32mi_EVEX, + SUB32mi_ND, + SUB32mi_NF, + SUB32mi_NF_ND, + SUB32mr, + SUB32mr_EVEX, + SUB32mr_ND, + SUB32mr_NF, + SUB32mr_NF_ND, + SUB32ri, + SUB32ri8, + SUB32ri8_EVEX, + SUB32ri8_ND, + SUB32ri8_NF, + SUB32ri8_NF_ND, + SUB32ri_EVEX, + SUB32ri_ND, + SUB32ri_NF, + SUB32ri_NF_ND, + SUB32rm, + SUB32rm_EVEX, + SUB32rm_ND, + SUB32rm_NF, + SUB32rm_NF_ND, + SUB32rr, + SUB32rr_EVEX, + SUB32rr_EVEX_REV, + SUB32rr_ND, + SUB32rr_ND_REV, + SUB32rr_NF, + SUB32rr_NF_ND, + SUB32rr_NF_ND_REV, + SUB32rr_NF_REV, + SUB32rr_REV, + SUB64i32, + SUB64mi32, + SUB64mi32_EVEX, + SUB64mi32_ND, + SUB64mi32_NF, + SUB64mi32_NF_ND, + SUB64mi8, + SUB64mi8_EVEX, + SUB64mi8_ND, + SUB64mi8_NF, + SUB64mi8_NF_ND, + SUB64mr, + SUB64mr_EVEX, + SUB64mr_ND, + SUB64mr_NF, + SUB64mr_NF_ND, + SUB64ri32, + SUB64ri32_EVEX, + SUB64ri32_ND, + SUB64ri32_NF, + SUB64ri32_NF_ND, + SUB64ri8, + SUB64ri8_EVEX, + SUB64ri8_ND, + SUB64ri8_NF, + SUB64ri8_NF_ND, + SUB64rm, + SUB64rm_EVEX, + SUB64rm_ND, + SUB64rm_NF, + SUB64rm_NF_ND, + SUB64rr, + SUB64rr_EVEX, + SUB64rr_EVEX_REV, + SUB64rr_ND, + SUB64rr_ND_REV, + SUB64rr_NF, + SUB64rr_NF_ND, + SUB64rr_NF_ND_REV, + SUB64rr_NF_REV, + SUB64rr_REV, + SUB8i8, + SUB8mi, + SUB8mi8, + SUB8mi_EVEX, + SUB8mi_ND, + SUB8mi_NF, + SUB8mi_NF_ND, + SUB8mr, + SUB8mr_EVEX, + SUB8mr_ND, + SUB8mr_NF, + SUB8mr_NF_ND, + SUB8ri, + SUB8ri8, + SUB8ri_EVEX, + SUB8ri_ND, + SUB8ri_NF, + SUB8ri_NF_ND, + SUB8rm, + SUB8rm_EVEX, + SUB8rm_ND, + SUB8rm_NF, + SUB8rm_NF_ND, + SUB8rr, + SUB8rr_EVEX, + SUB8rr_EVEX_REV, + SUB8rr_ND, + SUB8rr_ND_REV, + SUB8rr_NF, + SUB8rr_NF_ND, + SUB8rr_NF_ND_REV, + SUB8rr_NF_REV, + SUB8rr_REV, + SUBPDrm, + SUBPDrr, + SUBPSrm, + SUBPSrr, + SUBR_F32m, + SUBR_F64m, + SUBR_FI16m, + SUBR_FI32m, + SUBR_FPrST0, + SUBR_FST0r, + SUBR_Fp32m, + SUBR_Fp64m, + SUBR_Fp64m32, + SUBR_Fp80m32, + SUBR_Fp80m64, + SUBR_FpI16m32, + SUBR_FpI16m64, + SUBR_FpI16m80, + SUBR_FpI32m32, + SUBR_FpI32m64, + SUBR_FpI32m80, + SUBR_FrST0, + SUBSDrm, + SUBSDrm_Int, + SUBSDrr, + SUBSDrr_Int, + SUBSSrm, + SUBSSrm_Int, + SUBSSrr, + SUBSSrr_Int, + SUB_F32m, + SUB_F64m, + SUB_FI16m, + SUB_FI32m, + SUB_FPrST0, + SUB_FST0r, + SUB_Fp32, + SUB_Fp32m, + SUB_Fp64, + SUB_Fp64m, + SUB_Fp64m32, + SUB_Fp80, + SUB_Fp80m32, + SUB_Fp80m64, + SUB_FpI16m32, + SUB_FpI16m64, + SUB_FpI16m80, + SUB_FpI32m32, + SUB_FpI32m64, + SUB_FpI32m80, + SUB_FrST0, + SWAPGS, + SYSCALL, + SYSENTER, + SYSEXIT, + SYSEXIT64, + SYSRET, + SYSRET64, + T1MSKC32rm, + T1MSKC32rr, + T1MSKC64rm, + T1MSKC64rr, + TAILJMPd, + TAILJMPd64, + TAILJMPd64_CC, + TAILJMPd_CC, + TAILJMPm, + TAILJMPm64, + TAILJMPm64_REX, + TAILJMPr, + TAILJMPr64, + TAILJMPr64_REX, + TCMMIMFP16PS, + TCMMRLFP16PS, + TCRETURN_HIPE32ri, + TCRETURN_WIN64ri, + TCRETURN_WINmi64, + TCRETURNdi, + TCRETURNdi64, + TCRETURNdi64cc, + TCRETURNdicc, + TCRETURNmi, + TCRETURNmi64, + TCRETURNri, + TCRETURNri64, + TCRETURNri64_ImpCall, + TCVTROWD2PSrte, + TCVTROWD2PSrti, + TCVTROWPS2BF16Hrte, + TCVTROWPS2BF16Hrti, + TCVTROWPS2BF16Lrte, + TCVTROWPS2BF16Lrti, + TCVTROWPS2PHHrte, + TCVTROWPS2PHHrti, + TCVTROWPS2PHLrte, + TCVTROWPS2PHLrti, + TDCALL, + TDPBF16PS, + TDPBF8PS, + TDPBHF8PS, + TDPBSSD, + TDPBSUD, + TDPBUSD, + TDPBUUD, + TDPFP16PS, + TDPHBF8PS, + TDPHF8PS, + TEST16i16, + TEST16mi, + TEST16mr, + TEST16ri, + TEST16rr, + TEST32i32, + TEST32mi, + TEST32mr, + TEST32ri, + TEST32rr, + TEST64i32, + TEST64mi32, + TEST64mr, + TEST64ri32, + TEST64rr, + TEST8i8, + TEST8mi, + TEST8mr, + TEST8ri, + TEST8rr, + TESTUI, + TILELOADD, + TILELOADDRS, + TILELOADDRST1, + TILELOADDRST1_EVEX, + TILELOADDRS_EVEX, + TILELOADDT1, + TILELOADDT1_EVEX, + TILELOADD_EVEX, + TILEMOVROWrte, + TILEMOVROWrti, + TILERELEASE, + TILESTORED, + TILESTORED_EVEX, + TILEZERO, + TLBSYNC, + TLSCall_32, + TLSCall_64, + TLS_addr32, + TLS_addr64, + TLS_addrX32, + TLS_base_addr32, + TLS_base_addr64, + TLS_base_addrX32, + TLS_desc32, + TLS_desc64, + TMMULTF32PS, + TPAUSE, + TRAP, + TST_F, + TST_Fp32, + TST_Fp64, + TST_Fp80, + TZCNT16rm, + TZCNT16rm_EVEX, + TZCNT16rm_NF, + TZCNT16rr, + TZCNT16rr_EVEX, + TZCNT16rr_NF, + TZCNT32rm, + TZCNT32rm_EVEX, + TZCNT32rm_NF, + TZCNT32rr, + TZCNT32rr_EVEX, + TZCNT32rr_NF, + TZCNT64rm, + TZCNT64rm_EVEX, + TZCNT64rm_NF, + TZCNT64rr, + TZCNT64rr_EVEX, + TZCNT64rr_NF, + TZMSK32rm, + TZMSK32rr, + TZMSK64rm, + TZMSK64rr, + UBSAN_UD1, + UCOMISDrm, + UCOMISDrm_Int, + UCOMISDrr, + UCOMISDrr_Int, + UCOMISSrm, + UCOMISSrm_Int, + UCOMISSrr, + UCOMISSrr_Int, + UCOM_FIPr, + UCOM_FIr, + UCOM_FPPr, + UCOM_FPr, + UCOM_FpIr32, + UCOM_FpIr64, + UCOM_FpIr80, + UCOM_Fpr32, + UCOM_Fpr64, + UCOM_Fpr80, + UCOM_Fr, + UD1Lm, + UD1Lr, + UD1Qm, + UD1Qr, + UD1Wm, + UD1Wr, + UIRET, + UMONITOR16, + UMONITOR32, + UMONITOR64, + UMWAIT, + UNPCKHPDrm, + UNPCKHPDrr, + UNPCKHPSrm, + UNPCKHPSrr, + UNPCKLPDrm, + UNPCKLPDrr, + UNPCKLPSrm, + UNPCKLPSrr, + URDMSRri, + URDMSRri_EVEX, + URDMSRrr, + URDMSRrr_EVEX, + UWRMSRir, + UWRMSRir_EVEX, + UWRMSRrr, + UWRMSRrr_EVEX, + V4FMADDPSrm, + V4FMADDPSrmk, + V4FMADDPSrmkz, + V4FMADDSSrm, + V4FMADDSSrmk, + V4FMADDSSrmkz, + V4FNMADDPSrm, + V4FNMADDPSrmk, + V4FNMADDPSrmkz, + V4FNMADDSSrm, + V4FNMADDSSrmk, + V4FNMADDSSrmkz, + VAARG_64, + VAARG_X32, + VADDBF16Z128rm, + VADDBF16Z128rmb, + VADDBF16Z128rmbk, + VADDBF16Z128rmbkz, + VADDBF16Z128rmk, + VADDBF16Z128rmkz, + VADDBF16Z128rr, + VADDBF16Z128rrk, + VADDBF16Z128rrkz, + VADDBF16Z256rm, + VADDBF16Z256rmb, + VADDBF16Z256rmbk, + VADDBF16Z256rmbkz, + VADDBF16Z256rmk, + VADDBF16Z256rmkz, + VADDBF16Z256rr, + VADDBF16Z256rrk, + VADDBF16Z256rrkz, + VADDBF16Zrm, + VADDBF16Zrmb, + VADDBF16Zrmbk, + VADDBF16Zrmbkz, + VADDBF16Zrmk, + VADDBF16Zrmkz, + VADDBF16Zrr, + VADDBF16Zrrk, + VADDBF16Zrrkz, + VADDPDYrm, + VADDPDYrr, + VADDPDZ128rm, + VADDPDZ128rmb, + VADDPDZ128rmbk, + VADDPDZ128rmbkz, + VADDPDZ128rmk, + VADDPDZ128rmkz, + VADDPDZ128rr, + VADDPDZ128rrk, + VADDPDZ128rrkz, + VADDPDZ256rm, + VADDPDZ256rmb, + VADDPDZ256rmbk, + VADDPDZ256rmbkz, + VADDPDZ256rmk, + VADDPDZ256rmkz, + VADDPDZ256rr, + VADDPDZ256rrk, + VADDPDZ256rrkz, + VADDPDZrm, + VADDPDZrmb, + VADDPDZrmbk, + VADDPDZrmbkz, + VADDPDZrmk, + VADDPDZrmkz, + VADDPDZrr, + VADDPDZrrb, + VADDPDZrrbk, + VADDPDZrrbkz, + VADDPDZrrk, + VADDPDZrrkz, + VADDPDrm, + VADDPDrr, + VADDPHZ128rm, + VADDPHZ128rmb, + VADDPHZ128rmbk, + VADDPHZ128rmbkz, + VADDPHZ128rmk, + VADDPHZ128rmkz, + VADDPHZ128rr, + VADDPHZ128rrk, + VADDPHZ128rrkz, + VADDPHZ256rm, + VADDPHZ256rmb, + VADDPHZ256rmbk, + VADDPHZ256rmbkz, + VADDPHZ256rmk, + VADDPHZ256rmkz, + VADDPHZ256rr, + VADDPHZ256rrk, + VADDPHZ256rrkz, + VADDPHZrm, + VADDPHZrmb, + VADDPHZrmbk, + VADDPHZrmbkz, + VADDPHZrmk, + VADDPHZrmkz, + VADDPHZrr, + VADDPHZrrb, + VADDPHZrrbk, + VADDPHZrrbkz, + VADDPHZrrk, + VADDPHZrrkz, + VADDPSYrm, + VADDPSYrr, + VADDPSZ128rm, + VADDPSZ128rmb, + VADDPSZ128rmbk, + VADDPSZ128rmbkz, + VADDPSZ128rmk, + VADDPSZ128rmkz, + VADDPSZ128rr, + VADDPSZ128rrk, + VADDPSZ128rrkz, + VADDPSZ256rm, + VADDPSZ256rmb, + VADDPSZ256rmbk, + VADDPSZ256rmbkz, + VADDPSZ256rmk, + VADDPSZ256rmkz, + VADDPSZ256rr, + VADDPSZ256rrk, + VADDPSZ256rrkz, + VADDPSZrm, + VADDPSZrmb, + VADDPSZrmbk, + VADDPSZrmbkz, + VADDPSZrmk, + VADDPSZrmkz, + VADDPSZrr, + VADDPSZrrb, + VADDPSZrrbk, + VADDPSZrrbkz, + VADDPSZrrk, + VADDPSZrrkz, + VADDPSrm, + VADDPSrr, + VADDSDZrm, + VADDSDZrm_Int, + VADDSDZrmk_Int, + VADDSDZrmkz_Int, + VADDSDZrr, + VADDSDZrr_Int, + VADDSDZrrb_Int, + VADDSDZrrbk_Int, + VADDSDZrrbkz_Int, + VADDSDZrrk_Int, + VADDSDZrrkz_Int, + VADDSDrm, + VADDSDrm_Int, + VADDSDrr, + VADDSDrr_Int, + VADDSHZrm, + VADDSHZrm_Int, + VADDSHZrmk_Int, + VADDSHZrmkz_Int, + VADDSHZrr, + VADDSHZrr_Int, + VADDSHZrrb_Int, + VADDSHZrrbk_Int, + VADDSHZrrbkz_Int, + VADDSHZrrk_Int, + VADDSHZrrkz_Int, + VADDSSZrm, + VADDSSZrm_Int, + VADDSSZrmk_Int, + VADDSSZrmkz_Int, + VADDSSZrr, + VADDSSZrr_Int, + VADDSSZrrb_Int, + VADDSSZrrbk_Int, + VADDSSZrrbkz_Int, + VADDSSZrrk_Int, + VADDSSZrrkz_Int, + VADDSSrm, + VADDSSrm_Int, + VADDSSrr, + VADDSSrr_Int, + VADDSUBPDYrm, + VADDSUBPDYrr, + VADDSUBPDrm, + VADDSUBPDrr, + VADDSUBPSYrm, + VADDSUBPSYrr, + VADDSUBPSrm, + VADDSUBPSrr, + VAESDECLASTYrm, + VAESDECLASTYrr, + VAESDECLASTZ128rm, + VAESDECLASTZ128rr, + VAESDECLASTZ256rm, + VAESDECLASTZ256rr, + VAESDECLASTZrm, + VAESDECLASTZrr, + VAESDECLASTrm, + VAESDECLASTrr, + VAESDECYrm, + VAESDECYrr, + VAESDECZ128rm, + VAESDECZ128rr, + VAESDECZ256rm, + VAESDECZ256rr, + VAESDECZrm, + VAESDECZrr, + VAESDECrm, + VAESDECrr, + VAESENCLASTYrm, + VAESENCLASTYrr, + VAESENCLASTZ128rm, + VAESENCLASTZ128rr, + VAESENCLASTZ256rm, + VAESENCLASTZ256rr, + VAESENCLASTZrm, + VAESENCLASTZrr, + VAESENCLASTrm, + VAESENCLASTrr, + VAESENCYrm, + VAESENCYrr, + VAESENCZ128rm, + VAESENCZ128rr, + VAESENCZ256rm, + VAESENCZ256rr, + VAESENCZrm, + VAESENCZrr, + VAESENCrm, + VAESENCrr, + VAESIMCrm, + VAESIMCrr, + VAESKEYGENASSISTrmi, + VAESKEYGENASSISTrri, + VALIGNDZ128rmbi, + VALIGNDZ128rmbik, + VALIGNDZ128rmbikz, + VALIGNDZ128rmi, + VALIGNDZ128rmik, + VALIGNDZ128rmikz, + VALIGNDZ128rri, + VALIGNDZ128rrik, + VALIGNDZ128rrikz, + VALIGNDZ256rmbi, + VALIGNDZ256rmbik, + VALIGNDZ256rmbikz, + VALIGNDZ256rmi, + VALIGNDZ256rmik, + VALIGNDZ256rmikz, + VALIGNDZ256rri, + VALIGNDZ256rrik, + VALIGNDZ256rrikz, + VALIGNDZrmbi, + VALIGNDZrmbik, + VALIGNDZrmbikz, + VALIGNDZrmi, + VALIGNDZrmik, + VALIGNDZrmikz, + VALIGNDZrri, + VALIGNDZrrik, + VALIGNDZrrikz, + VALIGNQZ128rmbi, + VALIGNQZ128rmbik, + VALIGNQZ128rmbikz, + VALIGNQZ128rmi, + VALIGNQZ128rmik, + VALIGNQZ128rmikz, + VALIGNQZ128rri, + VALIGNQZ128rrik, + VALIGNQZ128rrikz, + VALIGNQZ256rmbi, + VALIGNQZ256rmbik, + VALIGNQZ256rmbikz, + VALIGNQZ256rmi, + VALIGNQZ256rmik, + VALIGNQZ256rmikz, + VALIGNQZ256rri, + VALIGNQZ256rrik, + VALIGNQZ256rrikz, + VALIGNQZrmbi, + VALIGNQZrmbik, + VALIGNQZrmbikz, + VALIGNQZrmi, + VALIGNQZrmik, + VALIGNQZrmikz, + VALIGNQZrri, + VALIGNQZrrik, + VALIGNQZrrikz, + VANDNPDYrm, + VANDNPDYrr, + VANDNPDZ128rm, + VANDNPDZ128rmb, + VANDNPDZ128rmbk, + VANDNPDZ128rmbkz, + VANDNPDZ128rmk, + VANDNPDZ128rmkz, + VANDNPDZ128rr, + VANDNPDZ128rrk, + VANDNPDZ128rrkz, + VANDNPDZ256rm, + VANDNPDZ256rmb, + VANDNPDZ256rmbk, + VANDNPDZ256rmbkz, + VANDNPDZ256rmk, + VANDNPDZ256rmkz, + VANDNPDZ256rr, + VANDNPDZ256rrk, + VANDNPDZ256rrkz, + VANDNPDZrm, + VANDNPDZrmb, + VANDNPDZrmbk, + VANDNPDZrmbkz, + VANDNPDZrmk, + VANDNPDZrmkz, + VANDNPDZrr, + VANDNPDZrrk, + VANDNPDZrrkz, + VANDNPDrm, + VANDNPDrr, + VANDNPSYrm, + VANDNPSYrr, + VANDNPSZ128rm, + VANDNPSZ128rmb, + VANDNPSZ128rmbk, + VANDNPSZ128rmbkz, + VANDNPSZ128rmk, + VANDNPSZ128rmkz, + VANDNPSZ128rr, + VANDNPSZ128rrk, + VANDNPSZ128rrkz, + VANDNPSZ256rm, + VANDNPSZ256rmb, + VANDNPSZ256rmbk, + VANDNPSZ256rmbkz, + VANDNPSZ256rmk, + VANDNPSZ256rmkz, + VANDNPSZ256rr, + VANDNPSZ256rrk, + VANDNPSZ256rrkz, + VANDNPSZrm, + VANDNPSZrmb, + VANDNPSZrmbk, + VANDNPSZrmbkz, + VANDNPSZrmk, + VANDNPSZrmkz, + VANDNPSZrr, + VANDNPSZrrk, + VANDNPSZrrkz, + VANDNPSrm, + VANDNPSrr, + VANDPDYrm, + VANDPDYrr, + VANDPDZ128rm, + VANDPDZ128rmb, + VANDPDZ128rmbk, + VANDPDZ128rmbkz, + VANDPDZ128rmk, + VANDPDZ128rmkz, + VANDPDZ128rr, + VANDPDZ128rrk, + VANDPDZ128rrkz, + VANDPDZ256rm, + VANDPDZ256rmb, + VANDPDZ256rmbk, + VANDPDZ256rmbkz, + VANDPDZ256rmk, + VANDPDZ256rmkz, + VANDPDZ256rr, + VANDPDZ256rrk, + VANDPDZ256rrkz, + VANDPDZrm, + VANDPDZrmb, + VANDPDZrmbk, + VANDPDZrmbkz, + VANDPDZrmk, + VANDPDZrmkz, + VANDPDZrr, + VANDPDZrrk, + VANDPDZrrkz, + VANDPDrm, + VANDPDrr, + VANDPSYrm, + VANDPSYrr, + VANDPSZ128rm, + VANDPSZ128rmb, + VANDPSZ128rmbk, + VANDPSZ128rmbkz, + VANDPSZ128rmk, + VANDPSZ128rmkz, + VANDPSZ128rr, + VANDPSZ128rrk, + VANDPSZ128rrkz, + VANDPSZ256rm, + VANDPSZ256rmb, + VANDPSZ256rmbk, + VANDPSZ256rmbkz, + VANDPSZ256rmk, + VANDPSZ256rmkz, + VANDPSZ256rr, + VANDPSZ256rrk, + VANDPSZ256rrkz, + VANDPSZrm, + VANDPSZrmb, + VANDPSZrmbk, + VANDPSZrmbkz, + VANDPSZrmk, + VANDPSZrmkz, + VANDPSZrr, + VANDPSZrrk, + VANDPSZrrkz, + VANDPSrm, + VANDPSrr, + VASTART_SAVE_XMM_REGS, + VBCSTNEBF162PSYrm, + VBCSTNEBF162PSrm, + VBCSTNESH2PSYrm, + VBCSTNESH2PSrm, + VBLENDMPDZ128rm, + VBLENDMPDZ128rmb, + VBLENDMPDZ128rmbk, + VBLENDMPDZ128rmbkz, + VBLENDMPDZ128rmk, + VBLENDMPDZ128rmkz, + VBLENDMPDZ128rr, + VBLENDMPDZ128rrk, + VBLENDMPDZ128rrkz, + VBLENDMPDZ256rm, + VBLENDMPDZ256rmb, + VBLENDMPDZ256rmbk, + VBLENDMPDZ256rmbkz, + VBLENDMPDZ256rmk, + VBLENDMPDZ256rmkz, + VBLENDMPDZ256rr, + VBLENDMPDZ256rrk, + VBLENDMPDZ256rrkz, + VBLENDMPDZrm, + VBLENDMPDZrmb, + VBLENDMPDZrmbk, + VBLENDMPDZrmbkz, + VBLENDMPDZrmk, + VBLENDMPDZrmkz, + VBLENDMPDZrr, + VBLENDMPDZrrk, + VBLENDMPDZrrkz, + VBLENDMPSZ128rm, + VBLENDMPSZ128rmb, + VBLENDMPSZ128rmbk, + VBLENDMPSZ128rmbkz, + VBLENDMPSZ128rmk, + VBLENDMPSZ128rmkz, + VBLENDMPSZ128rr, + VBLENDMPSZ128rrk, + VBLENDMPSZ128rrkz, + VBLENDMPSZ256rm, + VBLENDMPSZ256rmb, + VBLENDMPSZ256rmbk, + VBLENDMPSZ256rmbkz, + VBLENDMPSZ256rmk, + VBLENDMPSZ256rmkz, + VBLENDMPSZ256rr, + VBLENDMPSZ256rrk, + VBLENDMPSZ256rrkz, + VBLENDMPSZrm, + VBLENDMPSZrmb, + VBLENDMPSZrmbk, + VBLENDMPSZrmbkz, + VBLENDMPSZrmk, + VBLENDMPSZrmkz, + VBLENDMPSZrr, + VBLENDMPSZrrk, + VBLENDMPSZrrkz, + VBLENDPDYrmi, + VBLENDPDYrri, + VBLENDPDrmi, + VBLENDPDrri, + VBLENDPSYrmi, + VBLENDPSYrri, + VBLENDPSrmi, + VBLENDPSrri, + VBLENDVPDYrmr, + VBLENDVPDYrrr, + VBLENDVPDrmr, + VBLENDVPDrrr, + VBLENDVPSYrmr, + VBLENDVPSYrrr, + VBLENDVPSrmr, + VBLENDVPSrrr, + VBROADCASTF128rm, + VBROADCASTF32X2Z256rm, + VBROADCASTF32X2Z256rmk, + VBROADCASTF32X2Z256rmkz, + VBROADCASTF32X2Z256rr, + VBROADCASTF32X2Z256rrk, + VBROADCASTF32X2Z256rrkz, + VBROADCASTF32X2Zrm, + VBROADCASTF32X2Zrmk, + VBROADCASTF32X2Zrmkz, + VBROADCASTF32X2Zrr, + VBROADCASTF32X2Zrrk, + VBROADCASTF32X2Zrrkz, + VBROADCASTF32X4Z256rm, + VBROADCASTF32X4Z256rmk, + VBROADCASTF32X4Z256rmkz, + VBROADCASTF32X4Zrm, + VBROADCASTF32X4Zrmk, + VBROADCASTF32X4Zrmkz, + VBROADCASTF32X8Zrm, + VBROADCASTF32X8Zrmk, + VBROADCASTF32X8Zrmkz, + VBROADCASTF64X2Z256rm, + VBROADCASTF64X2Z256rmk, + VBROADCASTF64X2Z256rmkz, + VBROADCASTF64X2Zrm, + VBROADCASTF64X2Zrmk, + VBROADCASTF64X2Zrmkz, + VBROADCASTF64X4Zrm, + VBROADCASTF64X4Zrmk, + VBROADCASTF64X4Zrmkz, + VBROADCASTI128rm, + VBROADCASTI32X2Z128rm, + VBROADCASTI32X2Z128rmk, + VBROADCASTI32X2Z128rmkz, + VBROADCASTI32X2Z128rr, + VBROADCASTI32X2Z128rrk, + VBROADCASTI32X2Z128rrkz, + VBROADCASTI32X2Z256rm, + VBROADCASTI32X2Z256rmk, + VBROADCASTI32X2Z256rmkz, + VBROADCASTI32X2Z256rr, + VBROADCASTI32X2Z256rrk, + VBROADCASTI32X2Z256rrkz, + VBROADCASTI32X2Zrm, + VBROADCASTI32X2Zrmk, + VBROADCASTI32X2Zrmkz, + VBROADCASTI32X2Zrr, + VBROADCASTI32X2Zrrk, + VBROADCASTI32X2Zrrkz, + VBROADCASTI32X4Z256rm, + VBROADCASTI32X4Z256rmk, + VBROADCASTI32X4Z256rmkz, + VBROADCASTI32X4Zrm, + VBROADCASTI32X4Zrmk, + VBROADCASTI32X4Zrmkz, + VBROADCASTI32X8Zrm, + VBROADCASTI32X8Zrmk, + VBROADCASTI32X8Zrmkz, + VBROADCASTI64X2Z256rm, + VBROADCASTI64X2Z256rmk, + VBROADCASTI64X2Z256rmkz, + VBROADCASTI64X2Zrm, + VBROADCASTI64X2Zrmk, + VBROADCASTI64X2Zrmkz, + VBROADCASTI64X4Zrm, + VBROADCASTI64X4Zrmk, + VBROADCASTI64X4Zrmkz, + VBROADCASTSDYrm, + VBROADCASTSDYrr, + VBROADCASTSDZ256rm, + VBROADCASTSDZ256rmk, + VBROADCASTSDZ256rmkz, + VBROADCASTSDZ256rr, + VBROADCASTSDZ256rrk, + VBROADCASTSDZ256rrkz, + VBROADCASTSDZrm, + VBROADCASTSDZrmk, + VBROADCASTSDZrmkz, + VBROADCASTSDZrr, + VBROADCASTSDZrrk, + VBROADCASTSDZrrkz, + VBROADCASTSSYrm, + VBROADCASTSSYrr, + VBROADCASTSSZ128rm, + VBROADCASTSSZ128rmk, + VBROADCASTSSZ128rmkz, + VBROADCASTSSZ128rr, + VBROADCASTSSZ128rrk, + VBROADCASTSSZ128rrkz, + VBROADCASTSSZ256rm, + VBROADCASTSSZ256rmk, + VBROADCASTSSZ256rmkz, + VBROADCASTSSZ256rr, + VBROADCASTSSZ256rrk, + VBROADCASTSSZ256rrkz, + VBROADCASTSSZrm, + VBROADCASTSSZrmk, + VBROADCASTSSZrmkz, + VBROADCASTSSZrr, + VBROADCASTSSZrrk, + VBROADCASTSSZrrkz, + VBROADCASTSSrm, + VBROADCASTSSrr, + VCMPBF16Z128rmbi, + VCMPBF16Z128rmbik, + VCMPBF16Z128rmi, + VCMPBF16Z128rmik, + VCMPBF16Z128rri, + VCMPBF16Z128rrik, + VCMPBF16Z256rmbi, + VCMPBF16Z256rmbik, + VCMPBF16Z256rmi, + VCMPBF16Z256rmik, + VCMPBF16Z256rri, + VCMPBF16Z256rrik, + VCMPBF16Zrmbi, + VCMPBF16Zrmbik, + VCMPBF16Zrmi, + VCMPBF16Zrmik, + VCMPBF16Zrri, + VCMPBF16Zrrik, + VCMPPDYrmi, + VCMPPDYrri, + VCMPPDZ128rmbi, + VCMPPDZ128rmbik, + VCMPPDZ128rmi, + VCMPPDZ128rmik, + VCMPPDZ128rri, + VCMPPDZ128rrik, + VCMPPDZ256rmbi, + VCMPPDZ256rmbik, + VCMPPDZ256rmi, + VCMPPDZ256rmik, + VCMPPDZ256rri, + VCMPPDZ256rrik, + VCMPPDZrmbi, + VCMPPDZrmbik, + VCMPPDZrmi, + VCMPPDZrmik, + VCMPPDZrri, + VCMPPDZrrib, + VCMPPDZrribk, + VCMPPDZrrik, + VCMPPDrmi, + VCMPPDrri, + VCMPPHZ128rmbi, + VCMPPHZ128rmbik, + VCMPPHZ128rmi, + VCMPPHZ128rmik, + VCMPPHZ128rri, + VCMPPHZ128rrik, + VCMPPHZ256rmbi, + VCMPPHZ256rmbik, + VCMPPHZ256rmi, + VCMPPHZ256rmik, + VCMPPHZ256rri, + VCMPPHZ256rrik, + VCMPPHZrmbi, + VCMPPHZrmbik, + VCMPPHZrmi, + VCMPPHZrmik, + VCMPPHZrri, + VCMPPHZrrib, + VCMPPHZrribk, + VCMPPHZrrik, + VCMPPSYrmi, + VCMPPSYrri, + VCMPPSZ128rmbi, + VCMPPSZ128rmbik, + VCMPPSZ128rmi, + VCMPPSZ128rmik, + VCMPPSZ128rri, + VCMPPSZ128rrik, + VCMPPSZ256rmbi, + VCMPPSZ256rmbik, + VCMPPSZ256rmi, + VCMPPSZ256rmik, + VCMPPSZ256rri, + VCMPPSZ256rrik, + VCMPPSZrmbi, + VCMPPSZrmbik, + VCMPPSZrmi, + VCMPPSZrmik, + VCMPPSZrri, + VCMPPSZrrib, + VCMPPSZrribk, + VCMPPSZrrik, + VCMPPSrmi, + VCMPPSrri, + VCMPSDZrmi, + VCMPSDZrmi_Int, + VCMPSDZrmik_Int, + VCMPSDZrri, + VCMPSDZrri_Int, + VCMPSDZrrib_Int, + VCMPSDZrribk_Int, + VCMPSDZrrik_Int, + VCMPSDrmi, + VCMPSDrmi_Int, + VCMPSDrri, + VCMPSDrri_Int, + VCMPSHZrmi, + VCMPSHZrmi_Int, + VCMPSHZrmik_Int, + VCMPSHZrri, + VCMPSHZrri_Int, + VCMPSHZrrib_Int, + VCMPSHZrribk_Int, + VCMPSHZrrik_Int, + VCMPSSZrmi, + VCMPSSZrmi_Int, + VCMPSSZrmik_Int, + VCMPSSZrri, + VCMPSSZrri_Int, + VCMPSSZrrib_Int, + VCMPSSZrribk_Int, + VCMPSSZrrik_Int, + VCMPSSrmi, + VCMPSSrmi_Int, + VCMPSSrri, + VCMPSSrri_Int, + VCOMISBF16Zrm, + VCOMISBF16Zrm_Int, + VCOMISBF16Zrr, + VCOMISBF16Zrr_Int, + VCOMISDZrm, + VCOMISDZrm_Int, + VCOMISDZrr, + VCOMISDZrr_Int, + VCOMISDZrrb, + VCOMISDrm, + VCOMISDrm_Int, + VCOMISDrr, + VCOMISDrr_Int, + VCOMISHZrm, + VCOMISHZrm_Int, + VCOMISHZrr, + VCOMISHZrr_Int, + VCOMISHZrrb, + VCOMISSZrm, + VCOMISSZrm_Int, + VCOMISSZrr, + VCOMISSZrr_Int, + VCOMISSZrrb, + VCOMISSrm, + VCOMISSrm_Int, + VCOMISSrr, + VCOMISSrr_Int, + VCOMPRESSPDZ128mr, + VCOMPRESSPDZ128mrk, + VCOMPRESSPDZ128rr, + VCOMPRESSPDZ128rrk, + VCOMPRESSPDZ128rrkz, + VCOMPRESSPDZ256mr, + VCOMPRESSPDZ256mrk, + VCOMPRESSPDZ256rr, + VCOMPRESSPDZ256rrk, + VCOMPRESSPDZ256rrkz, + VCOMPRESSPDZmr, + VCOMPRESSPDZmrk, + VCOMPRESSPDZrr, + VCOMPRESSPDZrrk, + VCOMPRESSPDZrrkz, + VCOMPRESSPSZ128mr, + VCOMPRESSPSZ128mrk, + VCOMPRESSPSZ128rr, + VCOMPRESSPSZ128rrk, + VCOMPRESSPSZ128rrkz, + VCOMPRESSPSZ256mr, + VCOMPRESSPSZ256mrk, + VCOMPRESSPSZ256rr, + VCOMPRESSPSZ256rrk, + VCOMPRESSPSZ256rrkz, + VCOMPRESSPSZmr, + VCOMPRESSPSZmrk, + VCOMPRESSPSZrr, + VCOMPRESSPSZrrk, + VCOMPRESSPSZrrkz, + VCOMXSDZrm_Int, + VCOMXSDZrr_Int, + VCOMXSDZrrb_Int, + VCOMXSHZrm_Int, + VCOMXSHZrr_Int, + VCOMXSHZrrb_Int, + VCOMXSSZrm_Int, + VCOMXSSZrr_Int, + VCOMXSSZrrb_Int, + VCVT2PH2BF8SZ128rm, + VCVT2PH2BF8SZ128rmb, + VCVT2PH2BF8SZ128rmbk, + VCVT2PH2BF8SZ128rmbkz, + VCVT2PH2BF8SZ128rmk, + VCVT2PH2BF8SZ128rmkz, + VCVT2PH2BF8SZ128rr, + VCVT2PH2BF8SZ128rrk, + VCVT2PH2BF8SZ128rrkz, + VCVT2PH2BF8SZ256rm, + VCVT2PH2BF8SZ256rmb, + VCVT2PH2BF8SZ256rmbk, + VCVT2PH2BF8SZ256rmbkz, + VCVT2PH2BF8SZ256rmk, + VCVT2PH2BF8SZ256rmkz, + VCVT2PH2BF8SZ256rr, + VCVT2PH2BF8SZ256rrk, + VCVT2PH2BF8SZ256rrkz, + VCVT2PH2BF8SZrm, + VCVT2PH2BF8SZrmb, + VCVT2PH2BF8SZrmbk, + VCVT2PH2BF8SZrmbkz, + VCVT2PH2BF8SZrmk, + VCVT2PH2BF8SZrmkz, + VCVT2PH2BF8SZrr, + VCVT2PH2BF8SZrrk, + VCVT2PH2BF8SZrrkz, + VCVT2PH2BF8Z128rm, + VCVT2PH2BF8Z128rmb, + VCVT2PH2BF8Z128rmbk, + VCVT2PH2BF8Z128rmbkz, + VCVT2PH2BF8Z128rmk, + VCVT2PH2BF8Z128rmkz, + VCVT2PH2BF8Z128rr, + VCVT2PH2BF8Z128rrk, + VCVT2PH2BF8Z128rrkz, + VCVT2PH2BF8Z256rm, + VCVT2PH2BF8Z256rmb, + VCVT2PH2BF8Z256rmbk, + VCVT2PH2BF8Z256rmbkz, + VCVT2PH2BF8Z256rmk, + VCVT2PH2BF8Z256rmkz, + VCVT2PH2BF8Z256rr, + VCVT2PH2BF8Z256rrk, + VCVT2PH2BF8Z256rrkz, + VCVT2PH2BF8Zrm, + VCVT2PH2BF8Zrmb, + VCVT2PH2BF8Zrmbk, + VCVT2PH2BF8Zrmbkz, + VCVT2PH2BF8Zrmk, + VCVT2PH2BF8Zrmkz, + VCVT2PH2BF8Zrr, + VCVT2PH2BF8Zrrk, + VCVT2PH2BF8Zrrkz, + VCVT2PH2HF8SZ128rm, + VCVT2PH2HF8SZ128rmb, + VCVT2PH2HF8SZ128rmbk, + VCVT2PH2HF8SZ128rmbkz, + VCVT2PH2HF8SZ128rmk, + VCVT2PH2HF8SZ128rmkz, + VCVT2PH2HF8SZ128rr, + VCVT2PH2HF8SZ128rrk, + VCVT2PH2HF8SZ128rrkz, + VCVT2PH2HF8SZ256rm, + VCVT2PH2HF8SZ256rmb, + VCVT2PH2HF8SZ256rmbk, + VCVT2PH2HF8SZ256rmbkz, + VCVT2PH2HF8SZ256rmk, + VCVT2PH2HF8SZ256rmkz, + VCVT2PH2HF8SZ256rr, + VCVT2PH2HF8SZ256rrk, + VCVT2PH2HF8SZ256rrkz, + VCVT2PH2HF8SZrm, + VCVT2PH2HF8SZrmb, + VCVT2PH2HF8SZrmbk, + VCVT2PH2HF8SZrmbkz, + VCVT2PH2HF8SZrmk, + VCVT2PH2HF8SZrmkz, + VCVT2PH2HF8SZrr, + VCVT2PH2HF8SZrrk, + VCVT2PH2HF8SZrrkz, + VCVT2PH2HF8Z128rm, + VCVT2PH2HF8Z128rmb, + VCVT2PH2HF8Z128rmbk, + VCVT2PH2HF8Z128rmbkz, + VCVT2PH2HF8Z128rmk, + VCVT2PH2HF8Z128rmkz, + VCVT2PH2HF8Z128rr, + VCVT2PH2HF8Z128rrk, + VCVT2PH2HF8Z128rrkz, + VCVT2PH2HF8Z256rm, + VCVT2PH2HF8Z256rmb, + VCVT2PH2HF8Z256rmbk, + VCVT2PH2HF8Z256rmbkz, + VCVT2PH2HF8Z256rmk, + VCVT2PH2HF8Z256rmkz, + VCVT2PH2HF8Z256rr, + VCVT2PH2HF8Z256rrk, + VCVT2PH2HF8Z256rrkz, + VCVT2PH2HF8Zrm, + VCVT2PH2HF8Zrmb, + VCVT2PH2HF8Zrmbk, + VCVT2PH2HF8Zrmbkz, + VCVT2PH2HF8Zrmk, + VCVT2PH2HF8Zrmkz, + VCVT2PH2HF8Zrr, + VCVT2PH2HF8Zrrk, + VCVT2PH2HF8Zrrkz, + VCVT2PS2PHXZ128rm, + VCVT2PS2PHXZ128rmb, + VCVT2PS2PHXZ128rmbk, + VCVT2PS2PHXZ128rmbkz, + VCVT2PS2PHXZ128rmk, + VCVT2PS2PHXZ128rmkz, + VCVT2PS2PHXZ128rr, + VCVT2PS2PHXZ128rrk, + VCVT2PS2PHXZ128rrkz, + VCVT2PS2PHXZ256rm, + VCVT2PS2PHXZ256rmb, + VCVT2PS2PHXZ256rmbk, + VCVT2PS2PHXZ256rmbkz, + VCVT2PS2PHXZ256rmk, + VCVT2PS2PHXZ256rmkz, + VCVT2PS2PHXZ256rr, + VCVT2PS2PHXZ256rrk, + VCVT2PS2PHXZ256rrkz, + VCVT2PS2PHXZrm, + VCVT2PS2PHXZrmb, + VCVT2PS2PHXZrmbk, + VCVT2PS2PHXZrmbkz, + VCVT2PS2PHXZrmk, + VCVT2PS2PHXZrmkz, + VCVT2PS2PHXZrr, + VCVT2PS2PHXZrrb, + VCVT2PS2PHXZrrbk, + VCVT2PS2PHXZrrbkz, + VCVT2PS2PHXZrrk, + VCVT2PS2PHXZrrkz, + VCVTBF162IBSZ128rm, + VCVTBF162IBSZ128rmb, + VCVTBF162IBSZ128rmbk, + VCVTBF162IBSZ128rmbkz, + VCVTBF162IBSZ128rmk, + VCVTBF162IBSZ128rmkz, + VCVTBF162IBSZ128rr, + VCVTBF162IBSZ128rrk, + VCVTBF162IBSZ128rrkz, + VCVTBF162IBSZ256rm, + VCVTBF162IBSZ256rmb, + VCVTBF162IBSZ256rmbk, + VCVTBF162IBSZ256rmbkz, + VCVTBF162IBSZ256rmk, + VCVTBF162IBSZ256rmkz, + VCVTBF162IBSZ256rr, + VCVTBF162IBSZ256rrk, + VCVTBF162IBSZ256rrkz, + VCVTBF162IBSZrm, + VCVTBF162IBSZrmb, + VCVTBF162IBSZrmbk, + VCVTBF162IBSZrmbkz, + VCVTBF162IBSZrmk, + VCVTBF162IBSZrmkz, + VCVTBF162IBSZrr, + VCVTBF162IBSZrrk, + VCVTBF162IBSZrrkz, + VCVTBF162IUBSZ128rm, + VCVTBF162IUBSZ128rmb, + VCVTBF162IUBSZ128rmbk, + VCVTBF162IUBSZ128rmbkz, + VCVTBF162IUBSZ128rmk, + VCVTBF162IUBSZ128rmkz, + VCVTBF162IUBSZ128rr, + VCVTBF162IUBSZ128rrk, + VCVTBF162IUBSZ128rrkz, + VCVTBF162IUBSZ256rm, + VCVTBF162IUBSZ256rmb, + VCVTBF162IUBSZ256rmbk, + VCVTBF162IUBSZ256rmbkz, + VCVTBF162IUBSZ256rmk, + VCVTBF162IUBSZ256rmkz, + VCVTBF162IUBSZ256rr, + VCVTBF162IUBSZ256rrk, + VCVTBF162IUBSZ256rrkz, + VCVTBF162IUBSZrm, + VCVTBF162IUBSZrmb, + VCVTBF162IUBSZrmbk, + VCVTBF162IUBSZrmbkz, + VCVTBF162IUBSZrmk, + VCVTBF162IUBSZrmkz, + VCVTBF162IUBSZrr, + VCVTBF162IUBSZrrk, + VCVTBF162IUBSZrrkz, + VCVTBIASPH2BF8SZ128rm, + VCVTBIASPH2BF8SZ128rmb, + VCVTBIASPH2BF8SZ128rmbk, + VCVTBIASPH2BF8SZ128rmbkz, + VCVTBIASPH2BF8SZ128rmk, + VCVTBIASPH2BF8SZ128rmkz, + VCVTBIASPH2BF8SZ128rr, + VCVTBIASPH2BF8SZ128rrk, + VCVTBIASPH2BF8SZ128rrkz, + VCVTBIASPH2BF8SZ256rm, + VCVTBIASPH2BF8SZ256rmb, + VCVTBIASPH2BF8SZ256rmbk, + VCVTBIASPH2BF8SZ256rmbkz, + VCVTBIASPH2BF8SZ256rmk, + VCVTBIASPH2BF8SZ256rmkz, + VCVTBIASPH2BF8SZ256rr, + VCVTBIASPH2BF8SZ256rrk, + VCVTBIASPH2BF8SZ256rrkz, + VCVTBIASPH2BF8SZrm, + VCVTBIASPH2BF8SZrmb, + VCVTBIASPH2BF8SZrmbk, + VCVTBIASPH2BF8SZrmbkz, + VCVTBIASPH2BF8SZrmk, + VCVTBIASPH2BF8SZrmkz, + VCVTBIASPH2BF8SZrr, + VCVTBIASPH2BF8SZrrk, + VCVTBIASPH2BF8SZrrkz, + VCVTBIASPH2BF8Z128rm, + VCVTBIASPH2BF8Z128rmb, + VCVTBIASPH2BF8Z128rmbk, + VCVTBIASPH2BF8Z128rmbkz, + VCVTBIASPH2BF8Z128rmk, + VCVTBIASPH2BF8Z128rmkz, + VCVTBIASPH2BF8Z128rr, + VCVTBIASPH2BF8Z128rrk, + VCVTBIASPH2BF8Z128rrkz, + VCVTBIASPH2BF8Z256rm, + VCVTBIASPH2BF8Z256rmb, + VCVTBIASPH2BF8Z256rmbk, + VCVTBIASPH2BF8Z256rmbkz, + VCVTBIASPH2BF8Z256rmk, + VCVTBIASPH2BF8Z256rmkz, + VCVTBIASPH2BF8Z256rr, + VCVTBIASPH2BF8Z256rrk, + VCVTBIASPH2BF8Z256rrkz, + VCVTBIASPH2BF8Zrm, + VCVTBIASPH2BF8Zrmb, + VCVTBIASPH2BF8Zrmbk, + VCVTBIASPH2BF8Zrmbkz, + VCVTBIASPH2BF8Zrmk, + VCVTBIASPH2BF8Zrmkz, + VCVTBIASPH2BF8Zrr, + VCVTBIASPH2BF8Zrrk, + VCVTBIASPH2BF8Zrrkz, + VCVTBIASPH2HF8SZ128rm, + VCVTBIASPH2HF8SZ128rmb, + VCVTBIASPH2HF8SZ128rmbk, + VCVTBIASPH2HF8SZ128rmbkz, + VCVTBIASPH2HF8SZ128rmk, + VCVTBIASPH2HF8SZ128rmkz, + VCVTBIASPH2HF8SZ128rr, + VCVTBIASPH2HF8SZ128rrk, + VCVTBIASPH2HF8SZ128rrkz, + VCVTBIASPH2HF8SZ256rm, + VCVTBIASPH2HF8SZ256rmb, + VCVTBIASPH2HF8SZ256rmbk, + VCVTBIASPH2HF8SZ256rmbkz, + VCVTBIASPH2HF8SZ256rmk, + VCVTBIASPH2HF8SZ256rmkz, + VCVTBIASPH2HF8SZ256rr, + VCVTBIASPH2HF8SZ256rrk, + VCVTBIASPH2HF8SZ256rrkz, + VCVTBIASPH2HF8SZrm, + VCVTBIASPH2HF8SZrmb, + VCVTBIASPH2HF8SZrmbk, + VCVTBIASPH2HF8SZrmbkz, + VCVTBIASPH2HF8SZrmk, + VCVTBIASPH2HF8SZrmkz, + VCVTBIASPH2HF8SZrr, + VCVTBIASPH2HF8SZrrk, + VCVTBIASPH2HF8SZrrkz, + VCVTBIASPH2HF8Z128rm, + VCVTBIASPH2HF8Z128rmb, + VCVTBIASPH2HF8Z128rmbk, + VCVTBIASPH2HF8Z128rmbkz, + VCVTBIASPH2HF8Z128rmk, + VCVTBIASPH2HF8Z128rmkz, + VCVTBIASPH2HF8Z128rr, + VCVTBIASPH2HF8Z128rrk, + VCVTBIASPH2HF8Z128rrkz, + VCVTBIASPH2HF8Z256rm, + VCVTBIASPH2HF8Z256rmb, + VCVTBIASPH2HF8Z256rmbk, + VCVTBIASPH2HF8Z256rmbkz, + VCVTBIASPH2HF8Z256rmk, + VCVTBIASPH2HF8Z256rmkz, + VCVTBIASPH2HF8Z256rr, + VCVTBIASPH2HF8Z256rrk, + VCVTBIASPH2HF8Z256rrkz, + VCVTBIASPH2HF8Zrm, + VCVTBIASPH2HF8Zrmb, + VCVTBIASPH2HF8Zrmbk, + VCVTBIASPH2HF8Zrmbkz, + VCVTBIASPH2HF8Zrmk, + VCVTBIASPH2HF8Zrmkz, + VCVTBIASPH2HF8Zrr, + VCVTBIASPH2HF8Zrrk, + VCVTBIASPH2HF8Zrrkz, + VCVTDQ2PDYrm, + VCVTDQ2PDYrr, + VCVTDQ2PDZ128rm, + VCVTDQ2PDZ128rmb, + VCVTDQ2PDZ128rmbk, + VCVTDQ2PDZ128rmbkz, + VCVTDQ2PDZ128rmk, + VCVTDQ2PDZ128rmkz, + VCVTDQ2PDZ128rr, + VCVTDQ2PDZ128rrk, + VCVTDQ2PDZ128rrkz, + VCVTDQ2PDZ256rm, + VCVTDQ2PDZ256rmb, + VCVTDQ2PDZ256rmbk, + VCVTDQ2PDZ256rmbkz, + VCVTDQ2PDZ256rmk, + VCVTDQ2PDZ256rmkz, + VCVTDQ2PDZ256rr, + VCVTDQ2PDZ256rrk, + VCVTDQ2PDZ256rrkz, + VCVTDQ2PDZrm, + VCVTDQ2PDZrmb, + VCVTDQ2PDZrmbk, + VCVTDQ2PDZrmbkz, + VCVTDQ2PDZrmk, + VCVTDQ2PDZrmkz, + VCVTDQ2PDZrr, + VCVTDQ2PDZrrk, + VCVTDQ2PDZrrkz, + VCVTDQ2PDrm, + VCVTDQ2PDrr, + VCVTDQ2PHZ128rm, + VCVTDQ2PHZ128rmb, + VCVTDQ2PHZ128rmbk, + VCVTDQ2PHZ128rmbkz, + VCVTDQ2PHZ128rmk, + VCVTDQ2PHZ128rmkz, + VCVTDQ2PHZ128rr, + VCVTDQ2PHZ128rrk, + VCVTDQ2PHZ128rrkz, + VCVTDQ2PHZ256rm, + VCVTDQ2PHZ256rmb, + VCVTDQ2PHZ256rmbk, + VCVTDQ2PHZ256rmbkz, + VCVTDQ2PHZ256rmk, + VCVTDQ2PHZ256rmkz, + VCVTDQ2PHZ256rr, + VCVTDQ2PHZ256rrk, + VCVTDQ2PHZ256rrkz, + VCVTDQ2PHZrm, + VCVTDQ2PHZrmb, + VCVTDQ2PHZrmbk, + VCVTDQ2PHZrmbkz, + VCVTDQ2PHZrmk, + VCVTDQ2PHZrmkz, + VCVTDQ2PHZrr, + VCVTDQ2PHZrrb, + VCVTDQ2PHZrrbk, + VCVTDQ2PHZrrbkz, + VCVTDQ2PHZrrk, + VCVTDQ2PHZrrkz, + VCVTDQ2PSYrm, + VCVTDQ2PSYrr, + VCVTDQ2PSZ128rm, + VCVTDQ2PSZ128rmb, + VCVTDQ2PSZ128rmbk, + VCVTDQ2PSZ128rmbkz, + VCVTDQ2PSZ128rmk, + VCVTDQ2PSZ128rmkz, + VCVTDQ2PSZ128rr, + VCVTDQ2PSZ128rrk, + VCVTDQ2PSZ128rrkz, + VCVTDQ2PSZ256rm, + VCVTDQ2PSZ256rmb, + VCVTDQ2PSZ256rmbk, + VCVTDQ2PSZ256rmbkz, + VCVTDQ2PSZ256rmk, + VCVTDQ2PSZ256rmkz, + VCVTDQ2PSZ256rr, + VCVTDQ2PSZ256rrk, + VCVTDQ2PSZ256rrkz, + VCVTDQ2PSZrm, + VCVTDQ2PSZrmb, + VCVTDQ2PSZrmbk, + VCVTDQ2PSZrmbkz, + VCVTDQ2PSZrmk, + VCVTDQ2PSZrmkz, + VCVTDQ2PSZrr, + VCVTDQ2PSZrrb, + VCVTDQ2PSZrrbk, + VCVTDQ2PSZrrbkz, + VCVTDQ2PSZrrk, + VCVTDQ2PSZrrkz, + VCVTDQ2PSrm, + VCVTDQ2PSrr, + VCVTHF82PHZ128rm, + VCVTHF82PHZ128rmk, + VCVTHF82PHZ128rmkz, + VCVTHF82PHZ128rr, + VCVTHF82PHZ128rrk, + VCVTHF82PHZ128rrkz, + VCVTHF82PHZ256rm, + VCVTHF82PHZ256rmk, + VCVTHF82PHZ256rmkz, + VCVTHF82PHZ256rr, + VCVTHF82PHZ256rrk, + VCVTHF82PHZ256rrkz, + VCVTHF82PHZrm, + VCVTHF82PHZrmk, + VCVTHF82PHZrmkz, + VCVTHF82PHZrr, + VCVTHF82PHZrrk, + VCVTHF82PHZrrkz, + VCVTNE2PS2BF16Z128rm, + VCVTNE2PS2BF16Z128rmb, + VCVTNE2PS2BF16Z128rmbk, + VCVTNE2PS2BF16Z128rmbkz, + VCVTNE2PS2BF16Z128rmk, + VCVTNE2PS2BF16Z128rmkz, + VCVTNE2PS2BF16Z128rr, + VCVTNE2PS2BF16Z128rrk, + VCVTNE2PS2BF16Z128rrkz, + VCVTNE2PS2BF16Z256rm, + VCVTNE2PS2BF16Z256rmb, + VCVTNE2PS2BF16Z256rmbk, + VCVTNE2PS2BF16Z256rmbkz, + VCVTNE2PS2BF16Z256rmk, + VCVTNE2PS2BF16Z256rmkz, + VCVTNE2PS2BF16Z256rr, + VCVTNE2PS2BF16Z256rrk, + VCVTNE2PS2BF16Z256rrkz, + VCVTNE2PS2BF16Zrm, + VCVTNE2PS2BF16Zrmb, + VCVTNE2PS2BF16Zrmbk, + VCVTNE2PS2BF16Zrmbkz, + VCVTNE2PS2BF16Zrmk, + VCVTNE2PS2BF16Zrmkz, + VCVTNE2PS2BF16Zrr, + VCVTNE2PS2BF16Zrrk, + VCVTNE2PS2BF16Zrrkz, + VCVTNEEBF162PSYrm, + VCVTNEEBF162PSrm, + VCVTNEEPH2PSYrm, + VCVTNEEPH2PSrm, + VCVTNEOBF162PSYrm, + VCVTNEOBF162PSrm, + VCVTNEOPH2PSYrm, + VCVTNEOPH2PSrm, + VCVTNEPS2BF16Yrm, + VCVTNEPS2BF16Yrr, + VCVTNEPS2BF16Z128rm, + VCVTNEPS2BF16Z128rmb, + VCVTNEPS2BF16Z128rmbk, + VCVTNEPS2BF16Z128rmbkz, + VCVTNEPS2BF16Z128rmk, + VCVTNEPS2BF16Z128rmkz, + VCVTNEPS2BF16Z128rr, + VCVTNEPS2BF16Z128rrk, + VCVTNEPS2BF16Z128rrkz, + VCVTNEPS2BF16Z256rm, + VCVTNEPS2BF16Z256rmb, + VCVTNEPS2BF16Z256rmbk, + VCVTNEPS2BF16Z256rmbkz, + VCVTNEPS2BF16Z256rmk, + VCVTNEPS2BF16Z256rmkz, + VCVTNEPS2BF16Z256rr, + VCVTNEPS2BF16Z256rrk, + VCVTNEPS2BF16Z256rrkz, + VCVTNEPS2BF16Zrm, + VCVTNEPS2BF16Zrmb, + VCVTNEPS2BF16Zrmbk, + VCVTNEPS2BF16Zrmbkz, + VCVTNEPS2BF16Zrmk, + VCVTNEPS2BF16Zrmkz, + VCVTNEPS2BF16Zrr, + VCVTNEPS2BF16Zrrk, + VCVTNEPS2BF16Zrrkz, + VCVTNEPS2BF16rm, + VCVTNEPS2BF16rr, + VCVTPD2DQYrm, + VCVTPD2DQYrr, + VCVTPD2DQZ128rm, + VCVTPD2DQZ128rmb, + VCVTPD2DQZ128rmbk, + VCVTPD2DQZ128rmbkz, + VCVTPD2DQZ128rmk, + VCVTPD2DQZ128rmkz, + VCVTPD2DQZ128rr, + VCVTPD2DQZ128rrk, + VCVTPD2DQZ128rrkz, + VCVTPD2DQZ256rm, + VCVTPD2DQZ256rmb, + VCVTPD2DQZ256rmbk, + VCVTPD2DQZ256rmbkz, + VCVTPD2DQZ256rmk, + VCVTPD2DQZ256rmkz, + VCVTPD2DQZ256rr, + VCVTPD2DQZ256rrk, + VCVTPD2DQZ256rrkz, + VCVTPD2DQZrm, + VCVTPD2DQZrmb, + VCVTPD2DQZrmbk, + VCVTPD2DQZrmbkz, + VCVTPD2DQZrmk, + VCVTPD2DQZrmkz, + VCVTPD2DQZrr, + VCVTPD2DQZrrb, + VCVTPD2DQZrrbk, + VCVTPD2DQZrrbkz, + VCVTPD2DQZrrk, + VCVTPD2DQZrrkz, + VCVTPD2DQrm, + VCVTPD2DQrr, + VCVTPD2PHZ128rm, + VCVTPD2PHZ128rmb, + VCVTPD2PHZ128rmbk, + VCVTPD2PHZ128rmbkz, + VCVTPD2PHZ128rmk, + VCVTPD2PHZ128rmkz, + VCVTPD2PHZ128rr, + VCVTPD2PHZ128rrk, + VCVTPD2PHZ128rrkz, + VCVTPD2PHZ256rm, + VCVTPD2PHZ256rmb, + VCVTPD2PHZ256rmbk, + VCVTPD2PHZ256rmbkz, + VCVTPD2PHZ256rmk, + VCVTPD2PHZ256rmkz, + VCVTPD2PHZ256rr, + VCVTPD2PHZ256rrk, + VCVTPD2PHZ256rrkz, + VCVTPD2PHZrm, + VCVTPD2PHZrmb, + VCVTPD2PHZrmbk, + VCVTPD2PHZrmbkz, + VCVTPD2PHZrmk, + VCVTPD2PHZrmkz, + VCVTPD2PHZrr, + VCVTPD2PHZrrb, + VCVTPD2PHZrrbk, + VCVTPD2PHZrrbkz, + VCVTPD2PHZrrk, + VCVTPD2PHZrrkz, + VCVTPD2PSYrm, + VCVTPD2PSYrr, + VCVTPD2PSZ128rm, + VCVTPD2PSZ128rmb, + VCVTPD2PSZ128rmbk, + VCVTPD2PSZ128rmbkz, + VCVTPD2PSZ128rmk, + VCVTPD2PSZ128rmkz, + VCVTPD2PSZ128rr, + VCVTPD2PSZ128rrk, + VCVTPD2PSZ128rrkz, + VCVTPD2PSZ256rm, + VCVTPD2PSZ256rmb, + VCVTPD2PSZ256rmbk, + VCVTPD2PSZ256rmbkz, + VCVTPD2PSZ256rmk, + VCVTPD2PSZ256rmkz, + VCVTPD2PSZ256rr, + VCVTPD2PSZ256rrk, + VCVTPD2PSZ256rrkz, + VCVTPD2PSZrm, + VCVTPD2PSZrmb, + VCVTPD2PSZrmbk, + VCVTPD2PSZrmbkz, + VCVTPD2PSZrmk, + VCVTPD2PSZrmkz, + VCVTPD2PSZrr, + VCVTPD2PSZrrb, + VCVTPD2PSZrrbk, + VCVTPD2PSZrrbkz, + VCVTPD2PSZrrk, + VCVTPD2PSZrrkz, + VCVTPD2PSrm, + VCVTPD2PSrr, + VCVTPD2QQZ128rm, + VCVTPD2QQZ128rmb, + VCVTPD2QQZ128rmbk, + VCVTPD2QQZ128rmbkz, + VCVTPD2QQZ128rmk, + VCVTPD2QQZ128rmkz, + VCVTPD2QQZ128rr, + VCVTPD2QQZ128rrk, + VCVTPD2QQZ128rrkz, + VCVTPD2QQZ256rm, + VCVTPD2QQZ256rmb, + VCVTPD2QQZ256rmbk, + VCVTPD2QQZ256rmbkz, + VCVTPD2QQZ256rmk, + VCVTPD2QQZ256rmkz, + VCVTPD2QQZ256rr, + VCVTPD2QQZ256rrk, + VCVTPD2QQZ256rrkz, + VCVTPD2QQZrm, + VCVTPD2QQZrmb, + VCVTPD2QQZrmbk, + VCVTPD2QQZrmbkz, + VCVTPD2QQZrmk, + VCVTPD2QQZrmkz, + VCVTPD2QQZrr, + VCVTPD2QQZrrb, + VCVTPD2QQZrrbk, + VCVTPD2QQZrrbkz, + VCVTPD2QQZrrk, + VCVTPD2QQZrrkz, + VCVTPD2UDQZ128rm, + VCVTPD2UDQZ128rmb, + VCVTPD2UDQZ128rmbk, + VCVTPD2UDQZ128rmbkz, + VCVTPD2UDQZ128rmk, + VCVTPD2UDQZ128rmkz, + VCVTPD2UDQZ128rr, + VCVTPD2UDQZ128rrk, + VCVTPD2UDQZ128rrkz, + VCVTPD2UDQZ256rm, + VCVTPD2UDQZ256rmb, + VCVTPD2UDQZ256rmbk, + VCVTPD2UDQZ256rmbkz, + VCVTPD2UDQZ256rmk, + VCVTPD2UDQZ256rmkz, + VCVTPD2UDQZ256rr, + VCVTPD2UDQZ256rrk, + VCVTPD2UDQZ256rrkz, + VCVTPD2UDQZrm, + VCVTPD2UDQZrmb, + VCVTPD2UDQZrmbk, + VCVTPD2UDQZrmbkz, + VCVTPD2UDQZrmk, + VCVTPD2UDQZrmkz, + VCVTPD2UDQZrr, + VCVTPD2UDQZrrb, + VCVTPD2UDQZrrbk, + VCVTPD2UDQZrrbkz, + VCVTPD2UDQZrrk, + VCVTPD2UDQZrrkz, + VCVTPD2UQQZ128rm, + VCVTPD2UQQZ128rmb, + VCVTPD2UQQZ128rmbk, + VCVTPD2UQQZ128rmbkz, + VCVTPD2UQQZ128rmk, + VCVTPD2UQQZ128rmkz, + VCVTPD2UQQZ128rr, + VCVTPD2UQQZ128rrk, + VCVTPD2UQQZ128rrkz, + VCVTPD2UQQZ256rm, + VCVTPD2UQQZ256rmb, + VCVTPD2UQQZ256rmbk, + VCVTPD2UQQZ256rmbkz, + VCVTPD2UQQZ256rmk, + VCVTPD2UQQZ256rmkz, + VCVTPD2UQQZ256rr, + VCVTPD2UQQZ256rrk, + VCVTPD2UQQZ256rrkz, + VCVTPD2UQQZrm, + VCVTPD2UQQZrmb, + VCVTPD2UQQZrmbk, + VCVTPD2UQQZrmbkz, + VCVTPD2UQQZrmk, + VCVTPD2UQQZrmkz, + VCVTPD2UQQZrr, + VCVTPD2UQQZrrb, + VCVTPD2UQQZrrbk, + VCVTPD2UQQZrrbkz, + VCVTPD2UQQZrrk, + VCVTPD2UQQZrrkz, + VCVTPH2BF8SZ128rm, + VCVTPH2BF8SZ128rmb, + VCVTPH2BF8SZ128rmbk, + VCVTPH2BF8SZ128rmbkz, + VCVTPH2BF8SZ128rmk, + VCVTPH2BF8SZ128rmkz, + VCVTPH2BF8SZ128rr, + VCVTPH2BF8SZ128rrk, + VCVTPH2BF8SZ128rrkz, + VCVTPH2BF8SZ256rm, + VCVTPH2BF8SZ256rmb, + VCVTPH2BF8SZ256rmbk, + VCVTPH2BF8SZ256rmbkz, + VCVTPH2BF8SZ256rmk, + VCVTPH2BF8SZ256rmkz, + VCVTPH2BF8SZ256rr, + VCVTPH2BF8SZ256rrk, + VCVTPH2BF8SZ256rrkz, + VCVTPH2BF8SZrm, + VCVTPH2BF8SZrmb, + VCVTPH2BF8SZrmbk, + VCVTPH2BF8SZrmbkz, + VCVTPH2BF8SZrmk, + VCVTPH2BF8SZrmkz, + VCVTPH2BF8SZrr, + VCVTPH2BF8SZrrk, + VCVTPH2BF8SZrrkz, + VCVTPH2BF8Z128rm, + VCVTPH2BF8Z128rmb, + VCVTPH2BF8Z128rmbk, + VCVTPH2BF8Z128rmbkz, + VCVTPH2BF8Z128rmk, + VCVTPH2BF8Z128rmkz, + VCVTPH2BF8Z128rr, + VCVTPH2BF8Z128rrk, + VCVTPH2BF8Z128rrkz, + VCVTPH2BF8Z256rm, + VCVTPH2BF8Z256rmb, + VCVTPH2BF8Z256rmbk, + VCVTPH2BF8Z256rmbkz, + VCVTPH2BF8Z256rmk, + VCVTPH2BF8Z256rmkz, + VCVTPH2BF8Z256rr, + VCVTPH2BF8Z256rrk, + VCVTPH2BF8Z256rrkz, + VCVTPH2BF8Zrm, + VCVTPH2BF8Zrmb, + VCVTPH2BF8Zrmbk, + VCVTPH2BF8Zrmbkz, + VCVTPH2BF8Zrmk, + VCVTPH2BF8Zrmkz, + VCVTPH2BF8Zrr, + VCVTPH2BF8Zrrk, + VCVTPH2BF8Zrrkz, + VCVTPH2DQZ128rm, + VCVTPH2DQZ128rmb, + VCVTPH2DQZ128rmbk, + VCVTPH2DQZ128rmbkz, + VCVTPH2DQZ128rmk, + VCVTPH2DQZ128rmkz, + VCVTPH2DQZ128rr, + VCVTPH2DQZ128rrk, + VCVTPH2DQZ128rrkz, + VCVTPH2DQZ256rm, + VCVTPH2DQZ256rmb, + VCVTPH2DQZ256rmbk, + VCVTPH2DQZ256rmbkz, + VCVTPH2DQZ256rmk, + VCVTPH2DQZ256rmkz, + VCVTPH2DQZ256rr, + VCVTPH2DQZ256rrk, + VCVTPH2DQZ256rrkz, + VCVTPH2DQZrm, + VCVTPH2DQZrmb, + VCVTPH2DQZrmbk, + VCVTPH2DQZrmbkz, + VCVTPH2DQZrmk, + VCVTPH2DQZrmkz, + VCVTPH2DQZrr, + VCVTPH2DQZrrb, + VCVTPH2DQZrrbk, + VCVTPH2DQZrrbkz, + VCVTPH2DQZrrk, + VCVTPH2DQZrrkz, + VCVTPH2HF8SZ128rm, + VCVTPH2HF8SZ128rmb, + VCVTPH2HF8SZ128rmbk, + VCVTPH2HF8SZ128rmbkz, + VCVTPH2HF8SZ128rmk, + VCVTPH2HF8SZ128rmkz, + VCVTPH2HF8SZ128rr, + VCVTPH2HF8SZ128rrk, + VCVTPH2HF8SZ128rrkz, + VCVTPH2HF8SZ256rm, + VCVTPH2HF8SZ256rmb, + VCVTPH2HF8SZ256rmbk, + VCVTPH2HF8SZ256rmbkz, + VCVTPH2HF8SZ256rmk, + VCVTPH2HF8SZ256rmkz, + VCVTPH2HF8SZ256rr, + VCVTPH2HF8SZ256rrk, + VCVTPH2HF8SZ256rrkz, + VCVTPH2HF8SZrm, + VCVTPH2HF8SZrmb, + VCVTPH2HF8SZrmbk, + VCVTPH2HF8SZrmbkz, + VCVTPH2HF8SZrmk, + VCVTPH2HF8SZrmkz, + VCVTPH2HF8SZrr, + VCVTPH2HF8SZrrk, + VCVTPH2HF8SZrrkz, + VCVTPH2HF8Z128rm, + VCVTPH2HF8Z128rmb, + VCVTPH2HF8Z128rmbk, + VCVTPH2HF8Z128rmbkz, + VCVTPH2HF8Z128rmk, + VCVTPH2HF8Z128rmkz, + VCVTPH2HF8Z128rr, + VCVTPH2HF8Z128rrk, + VCVTPH2HF8Z128rrkz, + VCVTPH2HF8Z256rm, + VCVTPH2HF8Z256rmb, + VCVTPH2HF8Z256rmbk, + VCVTPH2HF8Z256rmbkz, + VCVTPH2HF8Z256rmk, + VCVTPH2HF8Z256rmkz, + VCVTPH2HF8Z256rr, + VCVTPH2HF8Z256rrk, + VCVTPH2HF8Z256rrkz, + VCVTPH2HF8Zrm, + VCVTPH2HF8Zrmb, + VCVTPH2HF8Zrmbk, + VCVTPH2HF8Zrmbkz, + VCVTPH2HF8Zrmk, + VCVTPH2HF8Zrmkz, + VCVTPH2HF8Zrr, + VCVTPH2HF8Zrrk, + VCVTPH2HF8Zrrkz, + VCVTPH2IBSZ128rm, + VCVTPH2IBSZ128rmb, + VCVTPH2IBSZ128rmbk, + VCVTPH2IBSZ128rmbkz, + VCVTPH2IBSZ128rmk, + VCVTPH2IBSZ128rmkz, + VCVTPH2IBSZ128rr, + VCVTPH2IBSZ128rrk, + VCVTPH2IBSZ128rrkz, + VCVTPH2IBSZ256rm, + VCVTPH2IBSZ256rmb, + VCVTPH2IBSZ256rmbk, + VCVTPH2IBSZ256rmbkz, + VCVTPH2IBSZ256rmk, + VCVTPH2IBSZ256rmkz, + VCVTPH2IBSZ256rr, + VCVTPH2IBSZ256rrk, + VCVTPH2IBSZ256rrkz, + VCVTPH2IBSZrm, + VCVTPH2IBSZrmb, + VCVTPH2IBSZrmbk, + VCVTPH2IBSZrmbkz, + VCVTPH2IBSZrmk, + VCVTPH2IBSZrmkz, + VCVTPH2IBSZrr, + VCVTPH2IBSZrrb, + VCVTPH2IBSZrrbk, + VCVTPH2IBSZrrbkz, + VCVTPH2IBSZrrk, + VCVTPH2IBSZrrkz, + VCVTPH2IUBSZ128rm, + VCVTPH2IUBSZ128rmb, + VCVTPH2IUBSZ128rmbk, + VCVTPH2IUBSZ128rmbkz, + VCVTPH2IUBSZ128rmk, + VCVTPH2IUBSZ128rmkz, + VCVTPH2IUBSZ128rr, + VCVTPH2IUBSZ128rrk, + VCVTPH2IUBSZ128rrkz, + VCVTPH2IUBSZ256rm, + VCVTPH2IUBSZ256rmb, + VCVTPH2IUBSZ256rmbk, + VCVTPH2IUBSZ256rmbkz, + VCVTPH2IUBSZ256rmk, + VCVTPH2IUBSZ256rmkz, + VCVTPH2IUBSZ256rr, + VCVTPH2IUBSZ256rrk, + VCVTPH2IUBSZ256rrkz, + VCVTPH2IUBSZrm, + VCVTPH2IUBSZrmb, + VCVTPH2IUBSZrmbk, + VCVTPH2IUBSZrmbkz, + VCVTPH2IUBSZrmk, + VCVTPH2IUBSZrmkz, + VCVTPH2IUBSZrr, + VCVTPH2IUBSZrrb, + VCVTPH2IUBSZrrbk, + VCVTPH2IUBSZrrbkz, + VCVTPH2IUBSZrrk, + VCVTPH2IUBSZrrkz, + VCVTPH2PDZ128rm, + VCVTPH2PDZ128rmb, + VCVTPH2PDZ128rmbk, + VCVTPH2PDZ128rmbkz, + VCVTPH2PDZ128rmk, + VCVTPH2PDZ128rmkz, + VCVTPH2PDZ128rr, + VCVTPH2PDZ128rrk, + VCVTPH2PDZ128rrkz, + VCVTPH2PDZ256rm, + VCVTPH2PDZ256rmb, + VCVTPH2PDZ256rmbk, + VCVTPH2PDZ256rmbkz, + VCVTPH2PDZ256rmk, + VCVTPH2PDZ256rmkz, + VCVTPH2PDZ256rr, + VCVTPH2PDZ256rrk, + VCVTPH2PDZ256rrkz, + VCVTPH2PDZrm, + VCVTPH2PDZrmb, + VCVTPH2PDZrmbk, + VCVTPH2PDZrmbkz, + VCVTPH2PDZrmk, + VCVTPH2PDZrmkz, + VCVTPH2PDZrr, + VCVTPH2PDZrrb, + VCVTPH2PDZrrbk, + VCVTPH2PDZrrbkz, + VCVTPH2PDZrrk, + VCVTPH2PDZrrkz, + VCVTPH2PSXZ128rm, + VCVTPH2PSXZ128rmb, + VCVTPH2PSXZ128rmbk, + VCVTPH2PSXZ128rmbkz, + VCVTPH2PSXZ128rmk, + VCVTPH2PSXZ128rmkz, + VCVTPH2PSXZ128rr, + VCVTPH2PSXZ128rrk, + VCVTPH2PSXZ128rrkz, + VCVTPH2PSXZ256rm, + VCVTPH2PSXZ256rmb, + VCVTPH2PSXZ256rmbk, + VCVTPH2PSXZ256rmbkz, + VCVTPH2PSXZ256rmk, + VCVTPH2PSXZ256rmkz, + VCVTPH2PSXZ256rr, + VCVTPH2PSXZ256rrk, + VCVTPH2PSXZ256rrkz, + VCVTPH2PSXZrm, + VCVTPH2PSXZrmb, + VCVTPH2PSXZrmbk, + VCVTPH2PSXZrmbkz, + VCVTPH2PSXZrmk, + VCVTPH2PSXZrmkz, + VCVTPH2PSXZrr, + VCVTPH2PSXZrrb, + VCVTPH2PSXZrrbk, + VCVTPH2PSXZrrbkz, + VCVTPH2PSXZrrk, + VCVTPH2PSXZrrkz, + VCVTPH2PSYrm, + VCVTPH2PSYrr, + VCVTPH2PSZ128rm, + VCVTPH2PSZ128rmk, + VCVTPH2PSZ128rmkz, + VCVTPH2PSZ128rr, + VCVTPH2PSZ128rrk, + VCVTPH2PSZ128rrkz, + VCVTPH2PSZ256rm, + VCVTPH2PSZ256rmk, + VCVTPH2PSZ256rmkz, + VCVTPH2PSZ256rr, + VCVTPH2PSZ256rrk, + VCVTPH2PSZ256rrkz, + VCVTPH2PSZrm, + VCVTPH2PSZrmk, + VCVTPH2PSZrmkz, + VCVTPH2PSZrr, + VCVTPH2PSZrrb, + VCVTPH2PSZrrbk, + VCVTPH2PSZrrbkz, + VCVTPH2PSZrrk, + VCVTPH2PSZrrkz, + VCVTPH2PSrm, + VCVTPH2PSrr, + VCVTPH2QQZ128rm, + VCVTPH2QQZ128rmb, + VCVTPH2QQZ128rmbk, + VCVTPH2QQZ128rmbkz, + VCVTPH2QQZ128rmk, + VCVTPH2QQZ128rmkz, + VCVTPH2QQZ128rr, + VCVTPH2QQZ128rrk, + VCVTPH2QQZ128rrkz, + VCVTPH2QQZ256rm, + VCVTPH2QQZ256rmb, + VCVTPH2QQZ256rmbk, + VCVTPH2QQZ256rmbkz, + VCVTPH2QQZ256rmk, + VCVTPH2QQZ256rmkz, + VCVTPH2QQZ256rr, + VCVTPH2QQZ256rrk, + VCVTPH2QQZ256rrkz, + VCVTPH2QQZrm, + VCVTPH2QQZrmb, + VCVTPH2QQZrmbk, + VCVTPH2QQZrmbkz, + VCVTPH2QQZrmk, + VCVTPH2QQZrmkz, + VCVTPH2QQZrr, + VCVTPH2QQZrrb, + VCVTPH2QQZrrbk, + VCVTPH2QQZrrbkz, + VCVTPH2QQZrrk, + VCVTPH2QQZrrkz, + VCVTPH2UDQZ128rm, + VCVTPH2UDQZ128rmb, + VCVTPH2UDQZ128rmbk, + VCVTPH2UDQZ128rmbkz, + VCVTPH2UDQZ128rmk, + VCVTPH2UDQZ128rmkz, + VCVTPH2UDQZ128rr, + VCVTPH2UDQZ128rrk, + VCVTPH2UDQZ128rrkz, + VCVTPH2UDQZ256rm, + VCVTPH2UDQZ256rmb, + VCVTPH2UDQZ256rmbk, + VCVTPH2UDQZ256rmbkz, + VCVTPH2UDQZ256rmk, + VCVTPH2UDQZ256rmkz, + VCVTPH2UDQZ256rr, + VCVTPH2UDQZ256rrk, + VCVTPH2UDQZ256rrkz, + VCVTPH2UDQZrm, + VCVTPH2UDQZrmb, + VCVTPH2UDQZrmbk, + VCVTPH2UDQZrmbkz, + VCVTPH2UDQZrmk, + VCVTPH2UDQZrmkz, + VCVTPH2UDQZrr, + VCVTPH2UDQZrrb, + VCVTPH2UDQZrrbk, + VCVTPH2UDQZrrbkz, + VCVTPH2UDQZrrk, + VCVTPH2UDQZrrkz, + VCVTPH2UQQZ128rm, + VCVTPH2UQQZ128rmb, + VCVTPH2UQQZ128rmbk, + VCVTPH2UQQZ128rmbkz, + VCVTPH2UQQZ128rmk, + VCVTPH2UQQZ128rmkz, + VCVTPH2UQQZ128rr, + VCVTPH2UQQZ128rrk, + VCVTPH2UQQZ128rrkz, + VCVTPH2UQQZ256rm, + VCVTPH2UQQZ256rmb, + VCVTPH2UQQZ256rmbk, + VCVTPH2UQQZ256rmbkz, + VCVTPH2UQQZ256rmk, + VCVTPH2UQQZ256rmkz, + VCVTPH2UQQZ256rr, + VCVTPH2UQQZ256rrk, + VCVTPH2UQQZ256rrkz, + VCVTPH2UQQZrm, + VCVTPH2UQQZrmb, + VCVTPH2UQQZrmbk, + VCVTPH2UQQZrmbkz, + VCVTPH2UQQZrmk, + VCVTPH2UQQZrmkz, + VCVTPH2UQQZrr, + VCVTPH2UQQZrrb, + VCVTPH2UQQZrrbk, + VCVTPH2UQQZrrbkz, + VCVTPH2UQQZrrk, + VCVTPH2UQQZrrkz, + VCVTPH2UWZ128rm, + VCVTPH2UWZ128rmb, + VCVTPH2UWZ128rmbk, + VCVTPH2UWZ128rmbkz, + VCVTPH2UWZ128rmk, + VCVTPH2UWZ128rmkz, + VCVTPH2UWZ128rr, + VCVTPH2UWZ128rrk, + VCVTPH2UWZ128rrkz, + VCVTPH2UWZ256rm, + VCVTPH2UWZ256rmb, + VCVTPH2UWZ256rmbk, + VCVTPH2UWZ256rmbkz, + VCVTPH2UWZ256rmk, + VCVTPH2UWZ256rmkz, + VCVTPH2UWZ256rr, + VCVTPH2UWZ256rrk, + VCVTPH2UWZ256rrkz, + VCVTPH2UWZrm, + VCVTPH2UWZrmb, + VCVTPH2UWZrmbk, + VCVTPH2UWZrmbkz, + VCVTPH2UWZrmk, + VCVTPH2UWZrmkz, + VCVTPH2UWZrr, + VCVTPH2UWZrrb, + VCVTPH2UWZrrbk, + VCVTPH2UWZrrbkz, + VCVTPH2UWZrrk, + VCVTPH2UWZrrkz, + VCVTPH2WZ128rm, + VCVTPH2WZ128rmb, + VCVTPH2WZ128rmbk, + VCVTPH2WZ128rmbkz, + VCVTPH2WZ128rmk, + VCVTPH2WZ128rmkz, + VCVTPH2WZ128rr, + VCVTPH2WZ128rrk, + VCVTPH2WZ128rrkz, + VCVTPH2WZ256rm, + VCVTPH2WZ256rmb, + VCVTPH2WZ256rmbk, + VCVTPH2WZ256rmbkz, + VCVTPH2WZ256rmk, + VCVTPH2WZ256rmkz, + VCVTPH2WZ256rr, + VCVTPH2WZ256rrk, + VCVTPH2WZ256rrkz, + VCVTPH2WZrm, + VCVTPH2WZrmb, + VCVTPH2WZrmbk, + VCVTPH2WZrmbkz, + VCVTPH2WZrmk, + VCVTPH2WZrmkz, + VCVTPH2WZrr, + VCVTPH2WZrrb, + VCVTPH2WZrrbk, + VCVTPH2WZrrbkz, + VCVTPH2WZrrk, + VCVTPH2WZrrkz, + VCVTPS2DQYrm, + VCVTPS2DQYrr, + VCVTPS2DQZ128rm, + VCVTPS2DQZ128rmb, + VCVTPS2DQZ128rmbk, + VCVTPS2DQZ128rmbkz, + VCVTPS2DQZ128rmk, + VCVTPS2DQZ128rmkz, + VCVTPS2DQZ128rr, + VCVTPS2DQZ128rrk, + VCVTPS2DQZ128rrkz, + VCVTPS2DQZ256rm, + VCVTPS2DQZ256rmb, + VCVTPS2DQZ256rmbk, + VCVTPS2DQZ256rmbkz, + VCVTPS2DQZ256rmk, + VCVTPS2DQZ256rmkz, + VCVTPS2DQZ256rr, + VCVTPS2DQZ256rrk, + VCVTPS2DQZ256rrkz, + VCVTPS2DQZrm, + VCVTPS2DQZrmb, + VCVTPS2DQZrmbk, + VCVTPS2DQZrmbkz, + VCVTPS2DQZrmk, + VCVTPS2DQZrmkz, + VCVTPS2DQZrr, + VCVTPS2DQZrrb, + VCVTPS2DQZrrbk, + VCVTPS2DQZrrbkz, + VCVTPS2DQZrrk, + VCVTPS2DQZrrkz, + VCVTPS2DQrm, + VCVTPS2DQrr, + VCVTPS2IBSZ128rm, + VCVTPS2IBSZ128rmb, + VCVTPS2IBSZ128rmbk, + VCVTPS2IBSZ128rmbkz, + VCVTPS2IBSZ128rmk, + VCVTPS2IBSZ128rmkz, + VCVTPS2IBSZ128rr, + VCVTPS2IBSZ128rrk, + VCVTPS2IBSZ128rrkz, + VCVTPS2IBSZ256rm, + VCVTPS2IBSZ256rmb, + VCVTPS2IBSZ256rmbk, + VCVTPS2IBSZ256rmbkz, + VCVTPS2IBSZ256rmk, + VCVTPS2IBSZ256rmkz, + VCVTPS2IBSZ256rr, + VCVTPS2IBSZ256rrk, + VCVTPS2IBSZ256rrkz, + VCVTPS2IBSZrm, + VCVTPS2IBSZrmb, + VCVTPS2IBSZrmbk, + VCVTPS2IBSZrmbkz, + VCVTPS2IBSZrmk, + VCVTPS2IBSZrmkz, + VCVTPS2IBSZrr, + VCVTPS2IBSZrrb, + VCVTPS2IBSZrrbk, + VCVTPS2IBSZrrbkz, + VCVTPS2IBSZrrk, + VCVTPS2IBSZrrkz, + VCVTPS2IUBSZ128rm, + VCVTPS2IUBSZ128rmb, + VCVTPS2IUBSZ128rmbk, + VCVTPS2IUBSZ128rmbkz, + VCVTPS2IUBSZ128rmk, + VCVTPS2IUBSZ128rmkz, + VCVTPS2IUBSZ128rr, + VCVTPS2IUBSZ128rrk, + VCVTPS2IUBSZ128rrkz, + VCVTPS2IUBSZ256rm, + VCVTPS2IUBSZ256rmb, + VCVTPS2IUBSZ256rmbk, + VCVTPS2IUBSZ256rmbkz, + VCVTPS2IUBSZ256rmk, + VCVTPS2IUBSZ256rmkz, + VCVTPS2IUBSZ256rr, + VCVTPS2IUBSZ256rrk, + VCVTPS2IUBSZ256rrkz, + VCVTPS2IUBSZrm, + VCVTPS2IUBSZrmb, + VCVTPS2IUBSZrmbk, + VCVTPS2IUBSZrmbkz, + VCVTPS2IUBSZrmk, + VCVTPS2IUBSZrmkz, + VCVTPS2IUBSZrr, + VCVTPS2IUBSZrrb, + VCVTPS2IUBSZrrbk, + VCVTPS2IUBSZrrbkz, + VCVTPS2IUBSZrrk, + VCVTPS2IUBSZrrkz, + VCVTPS2PDYrm, + VCVTPS2PDYrr, + VCVTPS2PDZ128rm, + VCVTPS2PDZ128rmb, + VCVTPS2PDZ128rmbk, + VCVTPS2PDZ128rmbkz, + VCVTPS2PDZ128rmk, + VCVTPS2PDZ128rmkz, + VCVTPS2PDZ128rr, + VCVTPS2PDZ128rrk, + VCVTPS2PDZ128rrkz, + VCVTPS2PDZ256rm, + VCVTPS2PDZ256rmb, + VCVTPS2PDZ256rmbk, + VCVTPS2PDZ256rmbkz, + VCVTPS2PDZ256rmk, + VCVTPS2PDZ256rmkz, + VCVTPS2PDZ256rr, + VCVTPS2PDZ256rrk, + VCVTPS2PDZ256rrkz, + VCVTPS2PDZrm, + VCVTPS2PDZrmb, + VCVTPS2PDZrmbk, + VCVTPS2PDZrmbkz, + VCVTPS2PDZrmk, + VCVTPS2PDZrmkz, + VCVTPS2PDZrr, + VCVTPS2PDZrrb, + VCVTPS2PDZrrbk, + VCVTPS2PDZrrbkz, + VCVTPS2PDZrrk, + VCVTPS2PDZrrkz, + VCVTPS2PDrm, + VCVTPS2PDrr, + VCVTPS2PHXZ128rm, + VCVTPS2PHXZ128rmb, + VCVTPS2PHXZ128rmbk, + VCVTPS2PHXZ128rmbkz, + VCVTPS2PHXZ128rmk, + VCVTPS2PHXZ128rmkz, + VCVTPS2PHXZ128rr, + VCVTPS2PHXZ128rrk, + VCVTPS2PHXZ128rrkz, + VCVTPS2PHXZ256rm, + VCVTPS2PHXZ256rmb, + VCVTPS2PHXZ256rmbk, + VCVTPS2PHXZ256rmbkz, + VCVTPS2PHXZ256rmk, + VCVTPS2PHXZ256rmkz, + VCVTPS2PHXZ256rr, + VCVTPS2PHXZ256rrk, + VCVTPS2PHXZ256rrkz, + VCVTPS2PHXZrm, + VCVTPS2PHXZrmb, + VCVTPS2PHXZrmbk, + VCVTPS2PHXZrmbkz, + VCVTPS2PHXZrmk, + VCVTPS2PHXZrmkz, + VCVTPS2PHXZrr, + VCVTPS2PHXZrrb, + VCVTPS2PHXZrrbk, + VCVTPS2PHXZrrbkz, + VCVTPS2PHXZrrk, + VCVTPS2PHXZrrkz, + VCVTPS2PHYmr, + VCVTPS2PHYrr, + VCVTPS2PHZ128mr, + VCVTPS2PHZ128mrk, + VCVTPS2PHZ128rr, + VCVTPS2PHZ128rrk, + VCVTPS2PHZ128rrkz, + VCVTPS2PHZ256mr, + VCVTPS2PHZ256mrk, + VCVTPS2PHZ256rr, + VCVTPS2PHZ256rrk, + VCVTPS2PHZ256rrkz, + VCVTPS2PHZmr, + VCVTPS2PHZmrk, + VCVTPS2PHZrr, + VCVTPS2PHZrrb, + VCVTPS2PHZrrbk, + VCVTPS2PHZrrbkz, + VCVTPS2PHZrrk, + VCVTPS2PHZrrkz, + VCVTPS2PHmr, + VCVTPS2PHrr, + VCVTPS2QQZ128rm, + VCVTPS2QQZ128rmb, + VCVTPS2QQZ128rmbk, + VCVTPS2QQZ128rmbkz, + VCVTPS2QQZ128rmk, + VCVTPS2QQZ128rmkz, + VCVTPS2QQZ128rr, + VCVTPS2QQZ128rrk, + VCVTPS2QQZ128rrkz, + VCVTPS2QQZ256rm, + VCVTPS2QQZ256rmb, + VCVTPS2QQZ256rmbk, + VCVTPS2QQZ256rmbkz, + VCVTPS2QQZ256rmk, + VCVTPS2QQZ256rmkz, + VCVTPS2QQZ256rr, + VCVTPS2QQZ256rrk, + VCVTPS2QQZ256rrkz, + VCVTPS2QQZrm, + VCVTPS2QQZrmb, + VCVTPS2QQZrmbk, + VCVTPS2QQZrmbkz, + VCVTPS2QQZrmk, + VCVTPS2QQZrmkz, + VCVTPS2QQZrr, + VCVTPS2QQZrrb, + VCVTPS2QQZrrbk, + VCVTPS2QQZrrbkz, + VCVTPS2QQZrrk, + VCVTPS2QQZrrkz, + VCVTPS2UDQZ128rm, + VCVTPS2UDQZ128rmb, + VCVTPS2UDQZ128rmbk, + VCVTPS2UDQZ128rmbkz, + VCVTPS2UDQZ128rmk, + VCVTPS2UDQZ128rmkz, + VCVTPS2UDQZ128rr, + VCVTPS2UDQZ128rrk, + VCVTPS2UDQZ128rrkz, + VCVTPS2UDQZ256rm, + VCVTPS2UDQZ256rmb, + VCVTPS2UDQZ256rmbk, + VCVTPS2UDQZ256rmbkz, + VCVTPS2UDQZ256rmk, + VCVTPS2UDQZ256rmkz, + VCVTPS2UDQZ256rr, + VCVTPS2UDQZ256rrk, + VCVTPS2UDQZ256rrkz, + VCVTPS2UDQZrm, + VCVTPS2UDQZrmb, + VCVTPS2UDQZrmbk, + VCVTPS2UDQZrmbkz, + VCVTPS2UDQZrmk, + VCVTPS2UDQZrmkz, + VCVTPS2UDQZrr, + VCVTPS2UDQZrrb, + VCVTPS2UDQZrrbk, + VCVTPS2UDQZrrbkz, + VCVTPS2UDQZrrk, + VCVTPS2UDQZrrkz, + VCVTPS2UQQZ128rm, + VCVTPS2UQQZ128rmb, + VCVTPS2UQQZ128rmbk, + VCVTPS2UQQZ128rmbkz, + VCVTPS2UQQZ128rmk, + VCVTPS2UQQZ128rmkz, + VCVTPS2UQQZ128rr, + VCVTPS2UQQZ128rrk, + VCVTPS2UQQZ128rrkz, + VCVTPS2UQQZ256rm, + VCVTPS2UQQZ256rmb, + VCVTPS2UQQZ256rmbk, + VCVTPS2UQQZ256rmbkz, + VCVTPS2UQQZ256rmk, + VCVTPS2UQQZ256rmkz, + VCVTPS2UQQZ256rr, + VCVTPS2UQQZ256rrk, + VCVTPS2UQQZ256rrkz, + VCVTPS2UQQZrm, + VCVTPS2UQQZrmb, + VCVTPS2UQQZrmbk, + VCVTPS2UQQZrmbkz, + VCVTPS2UQQZrmk, + VCVTPS2UQQZrmkz, + VCVTPS2UQQZrr, + VCVTPS2UQQZrrb, + VCVTPS2UQQZrrbk, + VCVTPS2UQQZrrbkz, + VCVTPS2UQQZrrk, + VCVTPS2UQQZrrkz, + VCVTQQ2PDZ128rm, + VCVTQQ2PDZ128rmb, + VCVTQQ2PDZ128rmbk, + VCVTQQ2PDZ128rmbkz, + VCVTQQ2PDZ128rmk, + VCVTQQ2PDZ128rmkz, + VCVTQQ2PDZ128rr, + VCVTQQ2PDZ128rrk, + VCVTQQ2PDZ128rrkz, + VCVTQQ2PDZ256rm, + VCVTQQ2PDZ256rmb, + VCVTQQ2PDZ256rmbk, + VCVTQQ2PDZ256rmbkz, + VCVTQQ2PDZ256rmk, + VCVTQQ2PDZ256rmkz, + VCVTQQ2PDZ256rr, + VCVTQQ2PDZ256rrk, + VCVTQQ2PDZ256rrkz, + VCVTQQ2PDZrm, + VCVTQQ2PDZrmb, + VCVTQQ2PDZrmbk, + VCVTQQ2PDZrmbkz, + VCVTQQ2PDZrmk, + VCVTQQ2PDZrmkz, + VCVTQQ2PDZrr, + VCVTQQ2PDZrrb, + VCVTQQ2PDZrrbk, + VCVTQQ2PDZrrbkz, + VCVTQQ2PDZrrk, + VCVTQQ2PDZrrkz, + VCVTQQ2PHZ128rm, + VCVTQQ2PHZ128rmb, + VCVTQQ2PHZ128rmbk, + VCVTQQ2PHZ128rmbkz, + VCVTQQ2PHZ128rmk, + VCVTQQ2PHZ128rmkz, + VCVTQQ2PHZ128rr, + VCVTQQ2PHZ128rrk, + VCVTQQ2PHZ128rrkz, + VCVTQQ2PHZ256rm, + VCVTQQ2PHZ256rmb, + VCVTQQ2PHZ256rmbk, + VCVTQQ2PHZ256rmbkz, + VCVTQQ2PHZ256rmk, + VCVTQQ2PHZ256rmkz, + VCVTQQ2PHZ256rr, + VCVTQQ2PHZ256rrk, + VCVTQQ2PHZ256rrkz, + VCVTQQ2PHZrm, + VCVTQQ2PHZrmb, + VCVTQQ2PHZrmbk, + VCVTQQ2PHZrmbkz, + VCVTQQ2PHZrmk, + VCVTQQ2PHZrmkz, + VCVTQQ2PHZrr, + VCVTQQ2PHZrrb, + VCVTQQ2PHZrrbk, + VCVTQQ2PHZrrbkz, + VCVTQQ2PHZrrk, + VCVTQQ2PHZrrkz, + VCVTQQ2PSZ128rm, + VCVTQQ2PSZ128rmb, + VCVTQQ2PSZ128rmbk, + VCVTQQ2PSZ128rmbkz, + VCVTQQ2PSZ128rmk, + VCVTQQ2PSZ128rmkz, + VCVTQQ2PSZ128rr, + VCVTQQ2PSZ128rrk, + VCVTQQ2PSZ128rrkz, + VCVTQQ2PSZ256rm, + VCVTQQ2PSZ256rmb, + VCVTQQ2PSZ256rmbk, + VCVTQQ2PSZ256rmbkz, + VCVTQQ2PSZ256rmk, + VCVTQQ2PSZ256rmkz, + VCVTQQ2PSZ256rr, + VCVTQQ2PSZ256rrk, + VCVTQQ2PSZ256rrkz, + VCVTQQ2PSZrm, + VCVTQQ2PSZrmb, + VCVTQQ2PSZrmbk, + VCVTQQ2PSZrmbkz, + VCVTQQ2PSZrmk, + VCVTQQ2PSZrmkz, + VCVTQQ2PSZrr, + VCVTQQ2PSZrrb, + VCVTQQ2PSZrrbk, + VCVTQQ2PSZrrbkz, + VCVTQQ2PSZrrk, + VCVTQQ2PSZrrkz, + VCVTSD2SHZrm, + VCVTSD2SHZrm_Int, + VCVTSD2SHZrmk_Int, + VCVTSD2SHZrmkz_Int, + VCVTSD2SHZrr, + VCVTSD2SHZrr_Int, + VCVTSD2SHZrrb_Int, + VCVTSD2SHZrrbk_Int, + VCVTSD2SHZrrbkz_Int, + VCVTSD2SHZrrk_Int, + VCVTSD2SHZrrkz_Int, + VCVTSD2SI64Zrm, + VCVTSD2SI64Zrm_Int, + VCVTSD2SI64Zrr, + VCVTSD2SI64Zrr_Int, + VCVTSD2SI64Zrrb_Int, + VCVTSD2SI64rm, + VCVTSD2SI64rm_Int, + VCVTSD2SI64rr, + VCVTSD2SI64rr_Int, + VCVTSD2SIZrm, + VCVTSD2SIZrm_Int, + VCVTSD2SIZrr, + VCVTSD2SIZrr_Int, + VCVTSD2SIZrrb_Int, + VCVTSD2SIrm, + VCVTSD2SIrm_Int, + VCVTSD2SIrr, + VCVTSD2SIrr_Int, + VCVTSD2SSZrm, + VCVTSD2SSZrm_Int, + VCVTSD2SSZrmk_Int, + VCVTSD2SSZrmkz_Int, + VCVTSD2SSZrr, + VCVTSD2SSZrr_Int, + VCVTSD2SSZrrb_Int, + VCVTSD2SSZrrbk_Int, + VCVTSD2SSZrrbkz_Int, + VCVTSD2SSZrrk_Int, + VCVTSD2SSZrrkz_Int, + VCVTSD2SSrm, + VCVTSD2SSrm_Int, + VCVTSD2SSrr, + VCVTSD2SSrr_Int, + VCVTSD2USI64Zrm_Int, + VCVTSD2USI64Zrr_Int, + VCVTSD2USI64Zrrb_Int, + VCVTSD2USIZrm_Int, + VCVTSD2USIZrr_Int, + VCVTSD2USIZrrb_Int, + VCVTSH2SDZrm, + VCVTSH2SDZrm_Int, + VCVTSH2SDZrmk_Int, + VCVTSH2SDZrmkz_Int, + VCVTSH2SDZrr, + VCVTSH2SDZrr_Int, + VCVTSH2SDZrrb_Int, + VCVTSH2SDZrrbk_Int, + VCVTSH2SDZrrbkz_Int, + VCVTSH2SDZrrk_Int, + VCVTSH2SDZrrkz_Int, + VCVTSH2SI64Zrm_Int, + VCVTSH2SI64Zrr_Int, + VCVTSH2SI64Zrrb_Int, + VCVTSH2SIZrm_Int, + VCVTSH2SIZrr_Int, + VCVTSH2SIZrrb_Int, + VCVTSH2SSZrm, + VCVTSH2SSZrm_Int, + VCVTSH2SSZrmk_Int, + VCVTSH2SSZrmkz_Int, + VCVTSH2SSZrr, + VCVTSH2SSZrr_Int, + VCVTSH2SSZrrb_Int, + VCVTSH2SSZrrbk_Int, + VCVTSH2SSZrrbkz_Int, + VCVTSH2SSZrrk_Int, + VCVTSH2SSZrrkz_Int, + VCVTSH2USI64Zrm_Int, + VCVTSH2USI64Zrr_Int, + VCVTSH2USI64Zrrb_Int, + VCVTSH2USIZrm_Int, + VCVTSH2USIZrr_Int, + VCVTSH2USIZrrb_Int, + VCVTSI2SDZrm, + VCVTSI2SDZrm_Int, + VCVTSI2SDZrr, + VCVTSI2SDZrr_Int, + VCVTSI2SDrm, + VCVTSI2SDrm_Int, + VCVTSI2SDrr, + VCVTSI2SDrr_Int, + VCVTSI2SHZrm, + VCVTSI2SHZrm_Int, + VCVTSI2SHZrr, + VCVTSI2SHZrr_Int, + VCVTSI2SHZrrb_Int, + VCVTSI2SSZrm, + VCVTSI2SSZrm_Int, + VCVTSI2SSZrr, + VCVTSI2SSZrr_Int, + VCVTSI2SSZrrb_Int, + VCVTSI2SSrm, + VCVTSI2SSrm_Int, + VCVTSI2SSrr, + VCVTSI2SSrr_Int, + VCVTSI642SDZrm, + VCVTSI642SDZrm_Int, + VCVTSI642SDZrr, + VCVTSI642SDZrr_Int, + VCVTSI642SDZrrb_Int, + VCVTSI642SDrm, + VCVTSI642SDrm_Int, + VCVTSI642SDrr, + VCVTSI642SDrr_Int, + VCVTSI642SHZrm, + VCVTSI642SHZrm_Int, + VCVTSI642SHZrr, + VCVTSI642SHZrr_Int, + VCVTSI642SHZrrb_Int, + VCVTSI642SSZrm, + VCVTSI642SSZrm_Int, + VCVTSI642SSZrr, + VCVTSI642SSZrr_Int, + VCVTSI642SSZrrb_Int, + VCVTSI642SSrm, + VCVTSI642SSrm_Int, + VCVTSI642SSrr, + VCVTSI642SSrr_Int, + VCVTSS2SDZrm, + VCVTSS2SDZrm_Int, + VCVTSS2SDZrmk_Int, + VCVTSS2SDZrmkz_Int, + VCVTSS2SDZrr, + VCVTSS2SDZrr_Int, + VCVTSS2SDZrrb_Int, + VCVTSS2SDZrrbk_Int, + VCVTSS2SDZrrbkz_Int, + VCVTSS2SDZrrk_Int, + VCVTSS2SDZrrkz_Int, + VCVTSS2SDrm, + VCVTSS2SDrm_Int, + VCVTSS2SDrr, + VCVTSS2SDrr_Int, + VCVTSS2SHZrm, + VCVTSS2SHZrm_Int, + VCVTSS2SHZrmk_Int, + VCVTSS2SHZrmkz_Int, + VCVTSS2SHZrr, + VCVTSS2SHZrr_Int, + VCVTSS2SHZrrb_Int, + VCVTSS2SHZrrbk_Int, + VCVTSS2SHZrrbkz_Int, + VCVTSS2SHZrrk_Int, + VCVTSS2SHZrrkz_Int, + VCVTSS2SI64Zrm, + VCVTSS2SI64Zrm_Int, + VCVTSS2SI64Zrr, + VCVTSS2SI64Zrr_Int, + VCVTSS2SI64Zrrb_Int, + VCVTSS2SI64rm, + VCVTSS2SI64rm_Int, + VCVTSS2SI64rr, + VCVTSS2SI64rr_Int, + VCVTSS2SIZrm, + VCVTSS2SIZrm_Int, + VCVTSS2SIZrr, + VCVTSS2SIZrr_Int, + VCVTSS2SIZrrb_Int, + VCVTSS2SIrm, + VCVTSS2SIrm_Int, + VCVTSS2SIrr, + VCVTSS2SIrr_Int, + VCVTSS2USI64Zrm_Int, + VCVTSS2USI64Zrr_Int, + VCVTSS2USI64Zrrb_Int, + VCVTSS2USIZrm_Int, + VCVTSS2USIZrr_Int, + VCVTSS2USIZrrb_Int, + VCVTTBF162IBSZ128rm, + VCVTTBF162IBSZ128rmb, + VCVTTBF162IBSZ128rmbk, + VCVTTBF162IBSZ128rmbkz, + VCVTTBF162IBSZ128rmk, + VCVTTBF162IBSZ128rmkz, + VCVTTBF162IBSZ128rr, + VCVTTBF162IBSZ128rrk, + VCVTTBF162IBSZ128rrkz, + VCVTTBF162IBSZ256rm, + VCVTTBF162IBSZ256rmb, + VCVTTBF162IBSZ256rmbk, + VCVTTBF162IBSZ256rmbkz, + VCVTTBF162IBSZ256rmk, + VCVTTBF162IBSZ256rmkz, + VCVTTBF162IBSZ256rr, + VCVTTBF162IBSZ256rrk, + VCVTTBF162IBSZ256rrkz, + VCVTTBF162IBSZrm, + VCVTTBF162IBSZrmb, + VCVTTBF162IBSZrmbk, + VCVTTBF162IBSZrmbkz, + VCVTTBF162IBSZrmk, + VCVTTBF162IBSZrmkz, + VCVTTBF162IBSZrr, + VCVTTBF162IBSZrrk, + VCVTTBF162IBSZrrkz, + VCVTTBF162IUBSZ128rm, + VCVTTBF162IUBSZ128rmb, + VCVTTBF162IUBSZ128rmbk, + VCVTTBF162IUBSZ128rmbkz, + VCVTTBF162IUBSZ128rmk, + VCVTTBF162IUBSZ128rmkz, + VCVTTBF162IUBSZ128rr, + VCVTTBF162IUBSZ128rrk, + VCVTTBF162IUBSZ128rrkz, + VCVTTBF162IUBSZ256rm, + VCVTTBF162IUBSZ256rmb, + VCVTTBF162IUBSZ256rmbk, + VCVTTBF162IUBSZ256rmbkz, + VCVTTBF162IUBSZ256rmk, + VCVTTBF162IUBSZ256rmkz, + VCVTTBF162IUBSZ256rr, + VCVTTBF162IUBSZ256rrk, + VCVTTBF162IUBSZ256rrkz, + VCVTTBF162IUBSZrm, + VCVTTBF162IUBSZrmb, + VCVTTBF162IUBSZrmbk, + VCVTTBF162IUBSZrmbkz, + VCVTTBF162IUBSZrmk, + VCVTTBF162IUBSZrmkz, + VCVTTBF162IUBSZrr, + VCVTTBF162IUBSZrrk, + VCVTTBF162IUBSZrrkz, + VCVTTPD2DQSZ128rm, + VCVTTPD2DQSZ128rmb, + VCVTTPD2DQSZ128rmbk, + VCVTTPD2DQSZ128rmbkz, + VCVTTPD2DQSZ128rmk, + VCVTTPD2DQSZ128rmkz, + VCVTTPD2DQSZ128rr, + VCVTTPD2DQSZ128rrk, + VCVTTPD2DQSZ128rrkz, + VCVTTPD2DQSZ256rm, + VCVTTPD2DQSZ256rmb, + VCVTTPD2DQSZ256rmbk, + VCVTTPD2DQSZ256rmbkz, + VCVTTPD2DQSZ256rmk, + VCVTTPD2DQSZ256rmkz, + VCVTTPD2DQSZ256rr, + VCVTTPD2DQSZ256rrb, + VCVTTPD2DQSZ256rrbk, + VCVTTPD2DQSZ256rrbkz, + VCVTTPD2DQSZ256rrk, + VCVTTPD2DQSZ256rrkz, + VCVTTPD2DQSZrm, + VCVTTPD2DQSZrmb, + VCVTTPD2DQSZrmbk, + VCVTTPD2DQSZrmbkz, + VCVTTPD2DQSZrmk, + VCVTTPD2DQSZrmkz, + VCVTTPD2DQSZrr, + VCVTTPD2DQSZrrb, + VCVTTPD2DQSZrrbk, + VCVTTPD2DQSZrrbkz, + VCVTTPD2DQSZrrk, + VCVTTPD2DQSZrrkz, + VCVTTPD2DQYrm, + VCVTTPD2DQYrr, + VCVTTPD2DQZ128rm, + VCVTTPD2DQZ128rmb, + VCVTTPD2DQZ128rmbk, + VCVTTPD2DQZ128rmbkz, + VCVTTPD2DQZ128rmk, + VCVTTPD2DQZ128rmkz, + VCVTTPD2DQZ128rr, + VCVTTPD2DQZ128rrk, + VCVTTPD2DQZ128rrkz, + VCVTTPD2DQZ256rm, + VCVTTPD2DQZ256rmb, + VCVTTPD2DQZ256rmbk, + VCVTTPD2DQZ256rmbkz, + VCVTTPD2DQZ256rmk, + VCVTTPD2DQZ256rmkz, + VCVTTPD2DQZ256rr, + VCVTTPD2DQZ256rrk, + VCVTTPD2DQZ256rrkz, + VCVTTPD2DQZrm, + VCVTTPD2DQZrmb, + VCVTTPD2DQZrmbk, + VCVTTPD2DQZrmbkz, + VCVTTPD2DQZrmk, + VCVTTPD2DQZrmkz, + VCVTTPD2DQZrr, + VCVTTPD2DQZrrb, + VCVTTPD2DQZrrbk, + VCVTTPD2DQZrrbkz, + VCVTTPD2DQZrrk, + VCVTTPD2DQZrrkz, + VCVTTPD2DQrm, + VCVTTPD2DQrr, + VCVTTPD2QQSZ128rm, + VCVTTPD2QQSZ128rmb, + VCVTTPD2QQSZ128rmbk, + VCVTTPD2QQSZ128rmbkz, + VCVTTPD2QQSZ128rmk, + VCVTTPD2QQSZ128rmkz, + VCVTTPD2QQSZ128rr, + VCVTTPD2QQSZ128rrk, + VCVTTPD2QQSZ128rrkz, + VCVTTPD2QQSZ256rm, + VCVTTPD2QQSZ256rmb, + VCVTTPD2QQSZ256rmbk, + VCVTTPD2QQSZ256rmbkz, + VCVTTPD2QQSZ256rmk, + VCVTTPD2QQSZ256rmkz, + VCVTTPD2QQSZ256rr, + VCVTTPD2QQSZ256rrb, + VCVTTPD2QQSZ256rrbk, + VCVTTPD2QQSZ256rrbkz, + VCVTTPD2QQSZ256rrk, + VCVTTPD2QQSZ256rrkz, + VCVTTPD2QQSZrm, + VCVTTPD2QQSZrmb, + VCVTTPD2QQSZrmbk, + VCVTTPD2QQSZrmbkz, + VCVTTPD2QQSZrmk, + VCVTTPD2QQSZrmkz, + VCVTTPD2QQSZrr, + VCVTTPD2QQSZrrb, + VCVTTPD2QQSZrrbk, + VCVTTPD2QQSZrrbkz, + VCVTTPD2QQSZrrk, + VCVTTPD2QQSZrrkz, + VCVTTPD2QQZ128rm, + VCVTTPD2QQZ128rmb, + VCVTTPD2QQZ128rmbk, + VCVTTPD2QQZ128rmbkz, + VCVTTPD2QQZ128rmk, + VCVTTPD2QQZ128rmkz, + VCVTTPD2QQZ128rr, + VCVTTPD2QQZ128rrk, + VCVTTPD2QQZ128rrkz, + VCVTTPD2QQZ256rm, + VCVTTPD2QQZ256rmb, + VCVTTPD2QQZ256rmbk, + VCVTTPD2QQZ256rmbkz, + VCVTTPD2QQZ256rmk, + VCVTTPD2QQZ256rmkz, + VCVTTPD2QQZ256rr, + VCVTTPD2QQZ256rrk, + VCVTTPD2QQZ256rrkz, + VCVTTPD2QQZrm, + VCVTTPD2QQZrmb, + VCVTTPD2QQZrmbk, + VCVTTPD2QQZrmbkz, + VCVTTPD2QQZrmk, + VCVTTPD2QQZrmkz, + VCVTTPD2QQZrr, + VCVTTPD2QQZrrb, + VCVTTPD2QQZrrbk, + VCVTTPD2QQZrrbkz, + VCVTTPD2QQZrrk, + VCVTTPD2QQZrrkz, + VCVTTPD2UDQSZ128rm, + VCVTTPD2UDQSZ128rmb, + VCVTTPD2UDQSZ128rmbk, + VCVTTPD2UDQSZ128rmbkz, + VCVTTPD2UDQSZ128rmk, + VCVTTPD2UDQSZ128rmkz, + VCVTTPD2UDQSZ128rr, + VCVTTPD2UDQSZ128rrk, + VCVTTPD2UDQSZ128rrkz, + VCVTTPD2UDQSZ256rm, + VCVTTPD2UDQSZ256rmb, + VCVTTPD2UDQSZ256rmbk, + VCVTTPD2UDQSZ256rmbkz, + VCVTTPD2UDQSZ256rmk, + VCVTTPD2UDQSZ256rmkz, + VCVTTPD2UDQSZ256rr, + VCVTTPD2UDQSZ256rrb, + VCVTTPD2UDQSZ256rrbk, + VCVTTPD2UDQSZ256rrbkz, + VCVTTPD2UDQSZ256rrk, + VCVTTPD2UDQSZ256rrkz, + VCVTTPD2UDQSZrm, + VCVTTPD2UDQSZrmb, + VCVTTPD2UDQSZrmbk, + VCVTTPD2UDQSZrmbkz, + VCVTTPD2UDQSZrmk, + VCVTTPD2UDQSZrmkz, + VCVTTPD2UDQSZrr, + VCVTTPD2UDQSZrrb, + VCVTTPD2UDQSZrrbk, + VCVTTPD2UDQSZrrbkz, + VCVTTPD2UDQSZrrk, + VCVTTPD2UDQSZrrkz, + VCVTTPD2UDQZ128rm, + VCVTTPD2UDQZ128rmb, + VCVTTPD2UDQZ128rmbk, + VCVTTPD2UDQZ128rmbkz, + VCVTTPD2UDQZ128rmk, + VCVTTPD2UDQZ128rmkz, + VCVTTPD2UDQZ128rr, + VCVTTPD2UDQZ128rrk, + VCVTTPD2UDQZ128rrkz, + VCVTTPD2UDQZ256rm, + VCVTTPD2UDQZ256rmb, + VCVTTPD2UDQZ256rmbk, + VCVTTPD2UDQZ256rmbkz, + VCVTTPD2UDQZ256rmk, + VCVTTPD2UDQZ256rmkz, + VCVTTPD2UDQZ256rr, + VCVTTPD2UDQZ256rrk, + VCVTTPD2UDQZ256rrkz, + VCVTTPD2UDQZrm, + VCVTTPD2UDQZrmb, + VCVTTPD2UDQZrmbk, + VCVTTPD2UDQZrmbkz, + VCVTTPD2UDQZrmk, + VCVTTPD2UDQZrmkz, + VCVTTPD2UDQZrr, + VCVTTPD2UDQZrrb, + VCVTTPD2UDQZrrbk, + VCVTTPD2UDQZrrbkz, + VCVTTPD2UDQZrrk, + VCVTTPD2UDQZrrkz, + VCVTTPD2UQQSZ128rm, + VCVTTPD2UQQSZ128rmb, + VCVTTPD2UQQSZ128rmbk, + VCVTTPD2UQQSZ128rmbkz, + VCVTTPD2UQQSZ128rmk, + VCVTTPD2UQQSZ128rmkz, + VCVTTPD2UQQSZ128rr, + VCVTTPD2UQQSZ128rrk, + VCVTTPD2UQQSZ128rrkz, + VCVTTPD2UQQSZ256rm, + VCVTTPD2UQQSZ256rmb, + VCVTTPD2UQQSZ256rmbk, + VCVTTPD2UQQSZ256rmbkz, + VCVTTPD2UQQSZ256rmk, + VCVTTPD2UQQSZ256rmkz, + VCVTTPD2UQQSZ256rr, + VCVTTPD2UQQSZ256rrb, + VCVTTPD2UQQSZ256rrbk, + VCVTTPD2UQQSZ256rrbkz, + VCVTTPD2UQQSZ256rrk, + VCVTTPD2UQQSZ256rrkz, + VCVTTPD2UQQSZrm, + VCVTTPD2UQQSZrmb, + VCVTTPD2UQQSZrmbk, + VCVTTPD2UQQSZrmbkz, + VCVTTPD2UQQSZrmk, + VCVTTPD2UQQSZrmkz, + VCVTTPD2UQQSZrr, + VCVTTPD2UQQSZrrb, + VCVTTPD2UQQSZrrbk, + VCVTTPD2UQQSZrrbkz, + VCVTTPD2UQQSZrrk, + VCVTTPD2UQQSZrrkz, + VCVTTPD2UQQZ128rm, + VCVTTPD2UQQZ128rmb, + VCVTTPD2UQQZ128rmbk, + VCVTTPD2UQQZ128rmbkz, + VCVTTPD2UQQZ128rmk, + VCVTTPD2UQQZ128rmkz, + VCVTTPD2UQQZ128rr, + VCVTTPD2UQQZ128rrk, + VCVTTPD2UQQZ128rrkz, + VCVTTPD2UQQZ256rm, + VCVTTPD2UQQZ256rmb, + VCVTTPD2UQQZ256rmbk, + VCVTTPD2UQQZ256rmbkz, + VCVTTPD2UQQZ256rmk, + VCVTTPD2UQQZ256rmkz, + VCVTTPD2UQQZ256rr, + VCVTTPD2UQQZ256rrk, + VCVTTPD2UQQZ256rrkz, + VCVTTPD2UQQZrm, + VCVTTPD2UQQZrmb, + VCVTTPD2UQQZrmbk, + VCVTTPD2UQQZrmbkz, + VCVTTPD2UQQZrmk, + VCVTTPD2UQQZrmkz, + VCVTTPD2UQQZrr, + VCVTTPD2UQQZrrb, + VCVTTPD2UQQZrrbk, + VCVTTPD2UQQZrrbkz, + VCVTTPD2UQQZrrk, + VCVTTPD2UQQZrrkz, + VCVTTPH2DQZ128rm, + VCVTTPH2DQZ128rmb, + VCVTTPH2DQZ128rmbk, + VCVTTPH2DQZ128rmbkz, + VCVTTPH2DQZ128rmk, + VCVTTPH2DQZ128rmkz, + VCVTTPH2DQZ128rr, + VCVTTPH2DQZ128rrk, + VCVTTPH2DQZ128rrkz, + VCVTTPH2DQZ256rm, + VCVTTPH2DQZ256rmb, + VCVTTPH2DQZ256rmbk, + VCVTTPH2DQZ256rmbkz, + VCVTTPH2DQZ256rmk, + VCVTTPH2DQZ256rmkz, + VCVTTPH2DQZ256rr, + VCVTTPH2DQZ256rrk, + VCVTTPH2DQZ256rrkz, + VCVTTPH2DQZrm, + VCVTTPH2DQZrmb, + VCVTTPH2DQZrmbk, + VCVTTPH2DQZrmbkz, + VCVTTPH2DQZrmk, + VCVTTPH2DQZrmkz, + VCVTTPH2DQZrr, + VCVTTPH2DQZrrb, + VCVTTPH2DQZrrbk, + VCVTTPH2DQZrrbkz, + VCVTTPH2DQZrrk, + VCVTTPH2DQZrrkz, + VCVTTPH2IBSZ128rm, + VCVTTPH2IBSZ128rmb, + VCVTTPH2IBSZ128rmbk, + VCVTTPH2IBSZ128rmbkz, + VCVTTPH2IBSZ128rmk, + VCVTTPH2IBSZ128rmkz, + VCVTTPH2IBSZ128rr, + VCVTTPH2IBSZ128rrk, + VCVTTPH2IBSZ128rrkz, + VCVTTPH2IBSZ256rm, + VCVTTPH2IBSZ256rmb, + VCVTTPH2IBSZ256rmbk, + VCVTTPH2IBSZ256rmbkz, + VCVTTPH2IBSZ256rmk, + VCVTTPH2IBSZ256rmkz, + VCVTTPH2IBSZ256rr, + VCVTTPH2IBSZ256rrk, + VCVTTPH2IBSZ256rrkz, + VCVTTPH2IBSZrm, + VCVTTPH2IBSZrmb, + VCVTTPH2IBSZrmbk, + VCVTTPH2IBSZrmbkz, + VCVTTPH2IBSZrmk, + VCVTTPH2IBSZrmkz, + VCVTTPH2IBSZrr, + VCVTTPH2IBSZrrb, + VCVTTPH2IBSZrrbk, + VCVTTPH2IBSZrrbkz, + VCVTTPH2IBSZrrk, + VCVTTPH2IBSZrrkz, + VCVTTPH2IUBSZ128rm, + VCVTTPH2IUBSZ128rmb, + VCVTTPH2IUBSZ128rmbk, + VCVTTPH2IUBSZ128rmbkz, + VCVTTPH2IUBSZ128rmk, + VCVTTPH2IUBSZ128rmkz, + VCVTTPH2IUBSZ128rr, + VCVTTPH2IUBSZ128rrk, + VCVTTPH2IUBSZ128rrkz, + VCVTTPH2IUBSZ256rm, + VCVTTPH2IUBSZ256rmb, + VCVTTPH2IUBSZ256rmbk, + VCVTTPH2IUBSZ256rmbkz, + VCVTTPH2IUBSZ256rmk, + VCVTTPH2IUBSZ256rmkz, + VCVTTPH2IUBSZ256rr, + VCVTTPH2IUBSZ256rrk, + VCVTTPH2IUBSZ256rrkz, + VCVTTPH2IUBSZrm, + VCVTTPH2IUBSZrmb, + VCVTTPH2IUBSZrmbk, + VCVTTPH2IUBSZrmbkz, + VCVTTPH2IUBSZrmk, + VCVTTPH2IUBSZrmkz, + VCVTTPH2IUBSZrr, + VCVTTPH2IUBSZrrb, + VCVTTPH2IUBSZrrbk, + VCVTTPH2IUBSZrrbkz, + VCVTTPH2IUBSZrrk, + VCVTTPH2IUBSZrrkz, + VCVTTPH2QQZ128rm, + VCVTTPH2QQZ128rmb, + VCVTTPH2QQZ128rmbk, + VCVTTPH2QQZ128rmbkz, + VCVTTPH2QQZ128rmk, + VCVTTPH2QQZ128rmkz, + VCVTTPH2QQZ128rr, + VCVTTPH2QQZ128rrk, + VCVTTPH2QQZ128rrkz, + VCVTTPH2QQZ256rm, + VCVTTPH2QQZ256rmb, + VCVTTPH2QQZ256rmbk, + VCVTTPH2QQZ256rmbkz, + VCVTTPH2QQZ256rmk, + VCVTTPH2QQZ256rmkz, + VCVTTPH2QQZ256rr, + VCVTTPH2QQZ256rrk, + VCVTTPH2QQZ256rrkz, + VCVTTPH2QQZrm, + VCVTTPH2QQZrmb, + VCVTTPH2QQZrmbk, + VCVTTPH2QQZrmbkz, + VCVTTPH2QQZrmk, + VCVTTPH2QQZrmkz, + VCVTTPH2QQZrr, + VCVTTPH2QQZrrb, + VCVTTPH2QQZrrbk, + VCVTTPH2QQZrrbkz, + VCVTTPH2QQZrrk, + VCVTTPH2QQZrrkz, + VCVTTPH2UDQZ128rm, + VCVTTPH2UDQZ128rmb, + VCVTTPH2UDQZ128rmbk, + VCVTTPH2UDQZ128rmbkz, + VCVTTPH2UDQZ128rmk, + VCVTTPH2UDQZ128rmkz, + VCVTTPH2UDQZ128rr, + VCVTTPH2UDQZ128rrk, + VCVTTPH2UDQZ128rrkz, + VCVTTPH2UDQZ256rm, + VCVTTPH2UDQZ256rmb, + VCVTTPH2UDQZ256rmbk, + VCVTTPH2UDQZ256rmbkz, + VCVTTPH2UDQZ256rmk, + VCVTTPH2UDQZ256rmkz, + VCVTTPH2UDQZ256rr, + VCVTTPH2UDQZ256rrk, + VCVTTPH2UDQZ256rrkz, + VCVTTPH2UDQZrm, + VCVTTPH2UDQZrmb, + VCVTTPH2UDQZrmbk, + VCVTTPH2UDQZrmbkz, + VCVTTPH2UDQZrmk, + VCVTTPH2UDQZrmkz, + VCVTTPH2UDQZrr, + VCVTTPH2UDQZrrb, + VCVTTPH2UDQZrrbk, + VCVTTPH2UDQZrrbkz, + VCVTTPH2UDQZrrk, + VCVTTPH2UDQZrrkz, + VCVTTPH2UQQZ128rm, + VCVTTPH2UQQZ128rmb, + VCVTTPH2UQQZ128rmbk, + VCVTTPH2UQQZ128rmbkz, + VCVTTPH2UQQZ128rmk, + VCVTTPH2UQQZ128rmkz, + VCVTTPH2UQQZ128rr, + VCVTTPH2UQQZ128rrk, + VCVTTPH2UQQZ128rrkz, + VCVTTPH2UQQZ256rm, + VCVTTPH2UQQZ256rmb, + VCVTTPH2UQQZ256rmbk, + VCVTTPH2UQQZ256rmbkz, + VCVTTPH2UQQZ256rmk, + VCVTTPH2UQQZ256rmkz, + VCVTTPH2UQQZ256rr, + VCVTTPH2UQQZ256rrk, + VCVTTPH2UQQZ256rrkz, + VCVTTPH2UQQZrm, + VCVTTPH2UQQZrmb, + VCVTTPH2UQQZrmbk, + VCVTTPH2UQQZrmbkz, + VCVTTPH2UQQZrmk, + VCVTTPH2UQQZrmkz, + VCVTTPH2UQQZrr, + VCVTTPH2UQQZrrb, + VCVTTPH2UQQZrrbk, + VCVTTPH2UQQZrrbkz, + VCVTTPH2UQQZrrk, + VCVTTPH2UQQZrrkz, + VCVTTPH2UWZ128rm, + VCVTTPH2UWZ128rmb, + VCVTTPH2UWZ128rmbk, + VCVTTPH2UWZ128rmbkz, + VCVTTPH2UWZ128rmk, + VCVTTPH2UWZ128rmkz, + VCVTTPH2UWZ128rr, + VCVTTPH2UWZ128rrk, + VCVTTPH2UWZ128rrkz, + VCVTTPH2UWZ256rm, + VCVTTPH2UWZ256rmb, + VCVTTPH2UWZ256rmbk, + VCVTTPH2UWZ256rmbkz, + VCVTTPH2UWZ256rmk, + VCVTTPH2UWZ256rmkz, + VCVTTPH2UWZ256rr, + VCVTTPH2UWZ256rrk, + VCVTTPH2UWZ256rrkz, + VCVTTPH2UWZrm, + VCVTTPH2UWZrmb, + VCVTTPH2UWZrmbk, + VCVTTPH2UWZrmbkz, + VCVTTPH2UWZrmk, + VCVTTPH2UWZrmkz, + VCVTTPH2UWZrr, + VCVTTPH2UWZrrb, + VCVTTPH2UWZrrbk, + VCVTTPH2UWZrrbkz, + VCVTTPH2UWZrrk, + VCVTTPH2UWZrrkz, + VCVTTPH2WZ128rm, + VCVTTPH2WZ128rmb, + VCVTTPH2WZ128rmbk, + VCVTTPH2WZ128rmbkz, + VCVTTPH2WZ128rmk, + VCVTTPH2WZ128rmkz, + VCVTTPH2WZ128rr, + VCVTTPH2WZ128rrk, + VCVTTPH2WZ128rrkz, + VCVTTPH2WZ256rm, + VCVTTPH2WZ256rmb, + VCVTTPH2WZ256rmbk, + VCVTTPH2WZ256rmbkz, + VCVTTPH2WZ256rmk, + VCVTTPH2WZ256rmkz, + VCVTTPH2WZ256rr, + VCVTTPH2WZ256rrk, + VCVTTPH2WZ256rrkz, + VCVTTPH2WZrm, + VCVTTPH2WZrmb, + VCVTTPH2WZrmbk, + VCVTTPH2WZrmbkz, + VCVTTPH2WZrmk, + VCVTTPH2WZrmkz, + VCVTTPH2WZrr, + VCVTTPH2WZrrb, + VCVTTPH2WZrrbk, + VCVTTPH2WZrrbkz, + VCVTTPH2WZrrk, + VCVTTPH2WZrrkz, + VCVTTPS2DQSZ128rm, + VCVTTPS2DQSZ128rmb, + VCVTTPS2DQSZ128rmbk, + VCVTTPS2DQSZ128rmbkz, + VCVTTPS2DQSZ128rmk, + VCVTTPS2DQSZ128rmkz, + VCVTTPS2DQSZ128rr, + VCVTTPS2DQSZ128rrk, + VCVTTPS2DQSZ128rrkz, + VCVTTPS2DQSZ256rm, + VCVTTPS2DQSZ256rmb, + VCVTTPS2DQSZ256rmbk, + VCVTTPS2DQSZ256rmbkz, + VCVTTPS2DQSZ256rmk, + VCVTTPS2DQSZ256rmkz, + VCVTTPS2DQSZ256rr, + VCVTTPS2DQSZ256rrk, + VCVTTPS2DQSZ256rrkz, + VCVTTPS2DQSZrm, + VCVTTPS2DQSZrmb, + VCVTTPS2DQSZrmbk, + VCVTTPS2DQSZrmbkz, + VCVTTPS2DQSZrmk, + VCVTTPS2DQSZrmkz, + VCVTTPS2DQSZrr, + VCVTTPS2DQSZrrb, + VCVTTPS2DQSZrrbk, + VCVTTPS2DQSZrrbkz, + VCVTTPS2DQSZrrk, + VCVTTPS2DQSZrrkz, + VCVTTPS2DQYrm, + VCVTTPS2DQYrr, + VCVTTPS2DQZ128rm, + VCVTTPS2DQZ128rmb, + VCVTTPS2DQZ128rmbk, + VCVTTPS2DQZ128rmbkz, + VCVTTPS2DQZ128rmk, + VCVTTPS2DQZ128rmkz, + VCVTTPS2DQZ128rr, + VCVTTPS2DQZ128rrk, + VCVTTPS2DQZ128rrkz, + VCVTTPS2DQZ256rm, + VCVTTPS2DQZ256rmb, + VCVTTPS2DQZ256rmbk, + VCVTTPS2DQZ256rmbkz, + VCVTTPS2DQZ256rmk, + VCVTTPS2DQZ256rmkz, + VCVTTPS2DQZ256rr, + VCVTTPS2DQZ256rrk, + VCVTTPS2DQZ256rrkz, + VCVTTPS2DQZrm, + VCVTTPS2DQZrmb, + VCVTTPS2DQZrmbk, + VCVTTPS2DQZrmbkz, + VCVTTPS2DQZrmk, + VCVTTPS2DQZrmkz, + VCVTTPS2DQZrr, + VCVTTPS2DQZrrb, + VCVTTPS2DQZrrbk, + VCVTTPS2DQZrrbkz, + VCVTTPS2DQZrrk, + VCVTTPS2DQZrrkz, + VCVTTPS2DQrm, + VCVTTPS2DQrr, + VCVTTPS2IBSZ128rm, + VCVTTPS2IBSZ128rmb, + VCVTTPS2IBSZ128rmbk, + VCVTTPS2IBSZ128rmbkz, + VCVTTPS2IBSZ128rmk, + VCVTTPS2IBSZ128rmkz, + VCVTTPS2IBSZ128rr, + VCVTTPS2IBSZ128rrk, + VCVTTPS2IBSZ128rrkz, + VCVTTPS2IBSZ256rm, + VCVTTPS2IBSZ256rmb, + VCVTTPS2IBSZ256rmbk, + VCVTTPS2IBSZ256rmbkz, + VCVTTPS2IBSZ256rmk, + VCVTTPS2IBSZ256rmkz, + VCVTTPS2IBSZ256rr, + VCVTTPS2IBSZ256rrk, + VCVTTPS2IBSZ256rrkz, + VCVTTPS2IBSZrm, + VCVTTPS2IBSZrmb, + VCVTTPS2IBSZrmbk, + VCVTTPS2IBSZrmbkz, + VCVTTPS2IBSZrmk, + VCVTTPS2IBSZrmkz, + VCVTTPS2IBSZrr, + VCVTTPS2IBSZrrb, + VCVTTPS2IBSZrrbk, + VCVTTPS2IBSZrrbkz, + VCVTTPS2IBSZrrk, + VCVTTPS2IBSZrrkz, + VCVTTPS2IUBSZ128rm, + VCVTTPS2IUBSZ128rmb, + VCVTTPS2IUBSZ128rmbk, + VCVTTPS2IUBSZ128rmbkz, + VCVTTPS2IUBSZ128rmk, + VCVTTPS2IUBSZ128rmkz, + VCVTTPS2IUBSZ128rr, + VCVTTPS2IUBSZ128rrk, + VCVTTPS2IUBSZ128rrkz, + VCVTTPS2IUBSZ256rm, + VCVTTPS2IUBSZ256rmb, + VCVTTPS2IUBSZ256rmbk, + VCVTTPS2IUBSZ256rmbkz, + VCVTTPS2IUBSZ256rmk, + VCVTTPS2IUBSZ256rmkz, + VCVTTPS2IUBSZ256rr, + VCVTTPS2IUBSZ256rrk, + VCVTTPS2IUBSZ256rrkz, + VCVTTPS2IUBSZrm, + VCVTTPS2IUBSZrmb, + VCVTTPS2IUBSZrmbk, + VCVTTPS2IUBSZrmbkz, + VCVTTPS2IUBSZrmk, + VCVTTPS2IUBSZrmkz, + VCVTTPS2IUBSZrr, + VCVTTPS2IUBSZrrb, + VCVTTPS2IUBSZrrbk, + VCVTTPS2IUBSZrrbkz, + VCVTTPS2IUBSZrrk, + VCVTTPS2IUBSZrrkz, + VCVTTPS2QQSZ128rm, + VCVTTPS2QQSZ128rmb, + VCVTTPS2QQSZ128rmbk, + VCVTTPS2QQSZ128rmbkz, + VCVTTPS2QQSZ128rmk, + VCVTTPS2QQSZ128rmkz, + VCVTTPS2QQSZ128rr, + VCVTTPS2QQSZ128rrk, + VCVTTPS2QQSZ128rrkz, + VCVTTPS2QQSZ256rm, + VCVTTPS2QQSZ256rmb, + VCVTTPS2QQSZ256rmbk, + VCVTTPS2QQSZ256rmbkz, + VCVTTPS2QQSZ256rmk, + VCVTTPS2QQSZ256rmkz, + VCVTTPS2QQSZ256rr, + VCVTTPS2QQSZ256rrb, + VCVTTPS2QQSZ256rrbk, + VCVTTPS2QQSZ256rrbkz, + VCVTTPS2QQSZ256rrk, + VCVTTPS2QQSZ256rrkz, + VCVTTPS2QQSZrm, + VCVTTPS2QQSZrmb, + VCVTTPS2QQSZrmbk, + VCVTTPS2QQSZrmbkz, + VCVTTPS2QQSZrmk, + VCVTTPS2QQSZrmkz, + VCVTTPS2QQSZrr, + VCVTTPS2QQSZrrb, + VCVTTPS2QQSZrrbk, + VCVTTPS2QQSZrrbkz, + VCVTTPS2QQSZrrk, + VCVTTPS2QQSZrrkz, + VCVTTPS2QQZ128rm, + VCVTTPS2QQZ128rmb, + VCVTTPS2QQZ128rmbk, + VCVTTPS2QQZ128rmbkz, + VCVTTPS2QQZ128rmk, + VCVTTPS2QQZ128rmkz, + VCVTTPS2QQZ128rr, + VCVTTPS2QQZ128rrk, + VCVTTPS2QQZ128rrkz, + VCVTTPS2QQZ256rm, + VCVTTPS2QQZ256rmb, + VCVTTPS2QQZ256rmbk, + VCVTTPS2QQZ256rmbkz, + VCVTTPS2QQZ256rmk, + VCVTTPS2QQZ256rmkz, + VCVTTPS2QQZ256rr, + VCVTTPS2QQZ256rrk, + VCVTTPS2QQZ256rrkz, + VCVTTPS2QQZrm, + VCVTTPS2QQZrmb, + VCVTTPS2QQZrmbk, + VCVTTPS2QQZrmbkz, + VCVTTPS2QQZrmk, + VCVTTPS2QQZrmkz, + VCVTTPS2QQZrr, + VCVTTPS2QQZrrb, + VCVTTPS2QQZrrbk, + VCVTTPS2QQZrrbkz, + VCVTTPS2QQZrrk, + VCVTTPS2QQZrrkz, + VCVTTPS2UDQSZ128rm, + VCVTTPS2UDQSZ128rmb, + VCVTTPS2UDQSZ128rmbk, + VCVTTPS2UDQSZ128rmbkz, + VCVTTPS2UDQSZ128rmk, + VCVTTPS2UDQSZ128rmkz, + VCVTTPS2UDQSZ128rr, + VCVTTPS2UDQSZ128rrk, + VCVTTPS2UDQSZ128rrkz, + VCVTTPS2UDQSZ256rm, + VCVTTPS2UDQSZ256rmb, + VCVTTPS2UDQSZ256rmbk, + VCVTTPS2UDQSZ256rmbkz, + VCVTTPS2UDQSZ256rmk, + VCVTTPS2UDQSZ256rmkz, + VCVTTPS2UDQSZ256rr, + VCVTTPS2UDQSZ256rrk, + VCVTTPS2UDQSZ256rrkz, + VCVTTPS2UDQSZrm, + VCVTTPS2UDQSZrmb, + VCVTTPS2UDQSZrmbk, + VCVTTPS2UDQSZrmbkz, + VCVTTPS2UDQSZrmk, + VCVTTPS2UDQSZrmkz, + VCVTTPS2UDQSZrr, + VCVTTPS2UDQSZrrb, + VCVTTPS2UDQSZrrbk, + VCVTTPS2UDQSZrrbkz, + VCVTTPS2UDQSZrrk, + VCVTTPS2UDQSZrrkz, + VCVTTPS2UDQZ128rm, + VCVTTPS2UDQZ128rmb, + VCVTTPS2UDQZ128rmbk, + VCVTTPS2UDQZ128rmbkz, + VCVTTPS2UDQZ128rmk, + VCVTTPS2UDQZ128rmkz, + VCVTTPS2UDQZ128rr, + VCVTTPS2UDQZ128rrk, + VCVTTPS2UDQZ128rrkz, + VCVTTPS2UDQZ256rm, + VCVTTPS2UDQZ256rmb, + VCVTTPS2UDQZ256rmbk, + VCVTTPS2UDQZ256rmbkz, + VCVTTPS2UDQZ256rmk, + VCVTTPS2UDQZ256rmkz, + VCVTTPS2UDQZ256rr, + VCVTTPS2UDQZ256rrk, + VCVTTPS2UDQZ256rrkz, + VCVTTPS2UDQZrm, + VCVTTPS2UDQZrmb, + VCVTTPS2UDQZrmbk, + VCVTTPS2UDQZrmbkz, + VCVTTPS2UDQZrmk, + VCVTTPS2UDQZrmkz, + VCVTTPS2UDQZrr, + VCVTTPS2UDQZrrb, + VCVTTPS2UDQZrrbk, + VCVTTPS2UDQZrrbkz, + VCVTTPS2UDQZrrk, + VCVTTPS2UDQZrrkz, + VCVTTPS2UQQSZ128rm, + VCVTTPS2UQQSZ128rmb, + VCVTTPS2UQQSZ128rmbk, + VCVTTPS2UQQSZ128rmbkz, + VCVTTPS2UQQSZ128rmk, + VCVTTPS2UQQSZ128rmkz, + VCVTTPS2UQQSZ128rr, + VCVTTPS2UQQSZ128rrk, + VCVTTPS2UQQSZ128rrkz, + VCVTTPS2UQQSZ256rm, + VCVTTPS2UQQSZ256rmb, + VCVTTPS2UQQSZ256rmbk, + VCVTTPS2UQQSZ256rmbkz, + VCVTTPS2UQQSZ256rmk, + VCVTTPS2UQQSZ256rmkz, + VCVTTPS2UQQSZ256rr, + VCVTTPS2UQQSZ256rrb, + VCVTTPS2UQQSZ256rrbk, + VCVTTPS2UQQSZ256rrbkz, + VCVTTPS2UQQSZ256rrk, + VCVTTPS2UQQSZ256rrkz, + VCVTTPS2UQQSZrm, + VCVTTPS2UQQSZrmb, + VCVTTPS2UQQSZrmbk, + VCVTTPS2UQQSZrmbkz, + VCVTTPS2UQQSZrmk, + VCVTTPS2UQQSZrmkz, + VCVTTPS2UQQSZrr, + VCVTTPS2UQQSZrrb, + VCVTTPS2UQQSZrrbk, + VCVTTPS2UQQSZrrbkz, + VCVTTPS2UQQSZrrk, + VCVTTPS2UQQSZrrkz, + VCVTTPS2UQQZ128rm, + VCVTTPS2UQQZ128rmb, + VCVTTPS2UQQZ128rmbk, + VCVTTPS2UQQZ128rmbkz, + VCVTTPS2UQQZ128rmk, + VCVTTPS2UQQZ128rmkz, + VCVTTPS2UQQZ128rr, + VCVTTPS2UQQZ128rrk, + VCVTTPS2UQQZ128rrkz, + VCVTTPS2UQQZ256rm, + VCVTTPS2UQQZ256rmb, + VCVTTPS2UQQZ256rmbk, + VCVTTPS2UQQZ256rmbkz, + VCVTTPS2UQQZ256rmk, + VCVTTPS2UQQZ256rmkz, + VCVTTPS2UQQZ256rr, + VCVTTPS2UQQZ256rrk, + VCVTTPS2UQQZ256rrkz, + VCVTTPS2UQQZrm, + VCVTTPS2UQQZrmb, + VCVTTPS2UQQZrmbk, + VCVTTPS2UQQZrmbkz, + VCVTTPS2UQQZrmk, + VCVTTPS2UQQZrmkz, + VCVTTPS2UQQZrr, + VCVTTPS2UQQZrrb, + VCVTTPS2UQQZrrbk, + VCVTTPS2UQQZrrbkz, + VCVTTPS2UQQZrrk, + VCVTTPS2UQQZrrkz, + VCVTTSD2SI64Srm, + VCVTTSD2SI64Srm_Int, + VCVTTSD2SI64Srr, + VCVTTSD2SI64Srr_Int, + VCVTTSD2SI64Srrb_Int, + VCVTTSD2SI64Zrm, + VCVTTSD2SI64Zrm_Int, + VCVTTSD2SI64Zrr, + VCVTTSD2SI64Zrr_Int, + VCVTTSD2SI64Zrrb_Int, + VCVTTSD2SI64rm, + VCVTTSD2SI64rm_Int, + VCVTTSD2SI64rr, + VCVTTSD2SI64rr_Int, + VCVTTSD2SISrm, + VCVTTSD2SISrm_Int, + VCVTTSD2SISrr, + VCVTTSD2SISrr_Int, + VCVTTSD2SISrrb_Int, + VCVTTSD2SIZrm, + VCVTTSD2SIZrm_Int, + VCVTTSD2SIZrr, + VCVTTSD2SIZrr_Int, + VCVTTSD2SIZrrb_Int, + VCVTTSD2SIrm, + VCVTTSD2SIrm_Int, + VCVTTSD2SIrr, + VCVTTSD2SIrr_Int, + VCVTTSD2USI64Srm, + VCVTTSD2USI64Srm_Int, + VCVTTSD2USI64Srr, + VCVTTSD2USI64Srr_Int, + VCVTTSD2USI64Srrb_Int, + VCVTTSD2USI64Zrm, + VCVTTSD2USI64Zrm_Int, + VCVTTSD2USI64Zrr, + VCVTTSD2USI64Zrr_Int, + VCVTTSD2USI64Zrrb_Int, + VCVTTSD2USISrm, + VCVTTSD2USISrm_Int, + VCVTTSD2USISrr, + VCVTTSD2USISrr_Int, + VCVTTSD2USISrrb_Int, + VCVTTSD2USIZrm, + VCVTTSD2USIZrm_Int, + VCVTTSD2USIZrr, + VCVTTSD2USIZrr_Int, + VCVTTSD2USIZrrb_Int, + VCVTTSH2SI64Zrm, + VCVTTSH2SI64Zrm_Int, + VCVTTSH2SI64Zrr, + VCVTTSH2SI64Zrr_Int, + VCVTTSH2SI64Zrrb_Int, + VCVTTSH2SIZrm, + VCVTTSH2SIZrm_Int, + VCVTTSH2SIZrr, + VCVTTSH2SIZrr_Int, + VCVTTSH2SIZrrb_Int, + VCVTTSH2USI64Zrm, + VCVTTSH2USI64Zrm_Int, + VCVTTSH2USI64Zrr, + VCVTTSH2USI64Zrr_Int, + VCVTTSH2USI64Zrrb_Int, + VCVTTSH2USIZrm, + VCVTTSH2USIZrm_Int, + VCVTTSH2USIZrr, + VCVTTSH2USIZrr_Int, + VCVTTSH2USIZrrb_Int, + VCVTTSS2SI64Srm, + VCVTTSS2SI64Srm_Int, + VCVTTSS2SI64Srr, + VCVTTSS2SI64Srr_Int, + VCVTTSS2SI64Srrb_Int, + VCVTTSS2SI64Zrm, + VCVTTSS2SI64Zrm_Int, + VCVTTSS2SI64Zrr, + VCVTTSS2SI64Zrr_Int, + VCVTTSS2SI64Zrrb_Int, + VCVTTSS2SI64rm, + VCVTTSS2SI64rm_Int, + VCVTTSS2SI64rr, + VCVTTSS2SI64rr_Int, + VCVTTSS2SISrm, + VCVTTSS2SISrm_Int, + VCVTTSS2SISrr, + VCVTTSS2SISrr_Int, + VCVTTSS2SISrrb_Int, + VCVTTSS2SIZrm, + VCVTTSS2SIZrm_Int, + VCVTTSS2SIZrr, + VCVTTSS2SIZrr_Int, + VCVTTSS2SIZrrb_Int, + VCVTTSS2SIrm, + VCVTTSS2SIrm_Int, + VCVTTSS2SIrr, + VCVTTSS2SIrr_Int, + VCVTTSS2USI64Srm, + VCVTTSS2USI64Srm_Int, + VCVTTSS2USI64Srr, + VCVTTSS2USI64Srr_Int, + VCVTTSS2USI64Srrb_Int, + VCVTTSS2USI64Zrm, + VCVTTSS2USI64Zrm_Int, + VCVTTSS2USI64Zrr, + VCVTTSS2USI64Zrr_Int, + VCVTTSS2USI64Zrrb_Int, + VCVTTSS2USISrm, + VCVTTSS2USISrm_Int, + VCVTTSS2USISrr, + VCVTTSS2USISrr_Int, + VCVTTSS2USISrrb_Int, + VCVTTSS2USIZrm, + VCVTTSS2USIZrm_Int, + VCVTTSS2USIZrr, + VCVTTSS2USIZrr_Int, + VCVTTSS2USIZrrb_Int, + VCVTUDQ2PDZ128rm, + VCVTUDQ2PDZ128rmb, + VCVTUDQ2PDZ128rmbk, + VCVTUDQ2PDZ128rmbkz, + VCVTUDQ2PDZ128rmk, + VCVTUDQ2PDZ128rmkz, + VCVTUDQ2PDZ128rr, + VCVTUDQ2PDZ128rrk, + VCVTUDQ2PDZ128rrkz, + VCVTUDQ2PDZ256rm, + VCVTUDQ2PDZ256rmb, + VCVTUDQ2PDZ256rmbk, + VCVTUDQ2PDZ256rmbkz, + VCVTUDQ2PDZ256rmk, + VCVTUDQ2PDZ256rmkz, + VCVTUDQ2PDZ256rr, + VCVTUDQ2PDZ256rrk, + VCVTUDQ2PDZ256rrkz, + VCVTUDQ2PDZrm, + VCVTUDQ2PDZrmb, + VCVTUDQ2PDZrmbk, + VCVTUDQ2PDZrmbkz, + VCVTUDQ2PDZrmk, + VCVTUDQ2PDZrmkz, + VCVTUDQ2PDZrr, + VCVTUDQ2PDZrrk, + VCVTUDQ2PDZrrkz, + VCVTUDQ2PHZ128rm, + VCVTUDQ2PHZ128rmb, + VCVTUDQ2PHZ128rmbk, + VCVTUDQ2PHZ128rmbkz, + VCVTUDQ2PHZ128rmk, + VCVTUDQ2PHZ128rmkz, + VCVTUDQ2PHZ128rr, + VCVTUDQ2PHZ128rrk, + VCVTUDQ2PHZ128rrkz, + VCVTUDQ2PHZ256rm, + VCVTUDQ2PHZ256rmb, + VCVTUDQ2PHZ256rmbk, + VCVTUDQ2PHZ256rmbkz, + VCVTUDQ2PHZ256rmk, + VCVTUDQ2PHZ256rmkz, + VCVTUDQ2PHZ256rr, + VCVTUDQ2PHZ256rrk, + VCVTUDQ2PHZ256rrkz, + VCVTUDQ2PHZrm, + VCVTUDQ2PHZrmb, + VCVTUDQ2PHZrmbk, + VCVTUDQ2PHZrmbkz, + VCVTUDQ2PHZrmk, + VCVTUDQ2PHZrmkz, + VCVTUDQ2PHZrr, + VCVTUDQ2PHZrrb, + VCVTUDQ2PHZrrbk, + VCVTUDQ2PHZrrbkz, + VCVTUDQ2PHZrrk, + VCVTUDQ2PHZrrkz, + VCVTUDQ2PSZ128rm, + VCVTUDQ2PSZ128rmb, + VCVTUDQ2PSZ128rmbk, + VCVTUDQ2PSZ128rmbkz, + VCVTUDQ2PSZ128rmk, + VCVTUDQ2PSZ128rmkz, + VCVTUDQ2PSZ128rr, + VCVTUDQ2PSZ128rrk, + VCVTUDQ2PSZ128rrkz, + VCVTUDQ2PSZ256rm, + VCVTUDQ2PSZ256rmb, + VCVTUDQ2PSZ256rmbk, + VCVTUDQ2PSZ256rmbkz, + VCVTUDQ2PSZ256rmk, + VCVTUDQ2PSZ256rmkz, + VCVTUDQ2PSZ256rr, + VCVTUDQ2PSZ256rrk, + VCVTUDQ2PSZ256rrkz, + VCVTUDQ2PSZrm, + VCVTUDQ2PSZrmb, + VCVTUDQ2PSZrmbk, + VCVTUDQ2PSZrmbkz, + VCVTUDQ2PSZrmk, + VCVTUDQ2PSZrmkz, + VCVTUDQ2PSZrr, + VCVTUDQ2PSZrrb, + VCVTUDQ2PSZrrbk, + VCVTUDQ2PSZrrbkz, + VCVTUDQ2PSZrrk, + VCVTUDQ2PSZrrkz, + VCVTUQQ2PDZ128rm, + VCVTUQQ2PDZ128rmb, + VCVTUQQ2PDZ128rmbk, + VCVTUQQ2PDZ128rmbkz, + VCVTUQQ2PDZ128rmk, + VCVTUQQ2PDZ128rmkz, + VCVTUQQ2PDZ128rr, + VCVTUQQ2PDZ128rrk, + VCVTUQQ2PDZ128rrkz, + VCVTUQQ2PDZ256rm, + VCVTUQQ2PDZ256rmb, + VCVTUQQ2PDZ256rmbk, + VCVTUQQ2PDZ256rmbkz, + VCVTUQQ2PDZ256rmk, + VCVTUQQ2PDZ256rmkz, + VCVTUQQ2PDZ256rr, + VCVTUQQ2PDZ256rrk, + VCVTUQQ2PDZ256rrkz, + VCVTUQQ2PDZrm, + VCVTUQQ2PDZrmb, + VCVTUQQ2PDZrmbk, + VCVTUQQ2PDZrmbkz, + VCVTUQQ2PDZrmk, + VCVTUQQ2PDZrmkz, + VCVTUQQ2PDZrr, + VCVTUQQ2PDZrrb, + VCVTUQQ2PDZrrbk, + VCVTUQQ2PDZrrbkz, + VCVTUQQ2PDZrrk, + VCVTUQQ2PDZrrkz, + VCVTUQQ2PHZ128rm, + VCVTUQQ2PHZ128rmb, + VCVTUQQ2PHZ128rmbk, + VCVTUQQ2PHZ128rmbkz, + VCVTUQQ2PHZ128rmk, + VCVTUQQ2PHZ128rmkz, + VCVTUQQ2PHZ128rr, + VCVTUQQ2PHZ128rrk, + VCVTUQQ2PHZ128rrkz, + VCVTUQQ2PHZ256rm, + VCVTUQQ2PHZ256rmb, + VCVTUQQ2PHZ256rmbk, + VCVTUQQ2PHZ256rmbkz, + VCVTUQQ2PHZ256rmk, + VCVTUQQ2PHZ256rmkz, + VCVTUQQ2PHZ256rr, + VCVTUQQ2PHZ256rrk, + VCVTUQQ2PHZ256rrkz, + VCVTUQQ2PHZrm, + VCVTUQQ2PHZrmb, + VCVTUQQ2PHZrmbk, + VCVTUQQ2PHZrmbkz, + VCVTUQQ2PHZrmk, + VCVTUQQ2PHZrmkz, + VCVTUQQ2PHZrr, + VCVTUQQ2PHZrrb, + VCVTUQQ2PHZrrbk, + VCVTUQQ2PHZrrbkz, + VCVTUQQ2PHZrrk, + VCVTUQQ2PHZrrkz, + VCVTUQQ2PSZ128rm, + VCVTUQQ2PSZ128rmb, + VCVTUQQ2PSZ128rmbk, + VCVTUQQ2PSZ128rmbkz, + VCVTUQQ2PSZ128rmk, + VCVTUQQ2PSZ128rmkz, + VCVTUQQ2PSZ128rr, + VCVTUQQ2PSZ128rrk, + VCVTUQQ2PSZ128rrkz, + VCVTUQQ2PSZ256rm, + VCVTUQQ2PSZ256rmb, + VCVTUQQ2PSZ256rmbk, + VCVTUQQ2PSZ256rmbkz, + VCVTUQQ2PSZ256rmk, + VCVTUQQ2PSZ256rmkz, + VCVTUQQ2PSZ256rr, + VCVTUQQ2PSZ256rrk, + VCVTUQQ2PSZ256rrkz, + VCVTUQQ2PSZrm, + VCVTUQQ2PSZrmb, + VCVTUQQ2PSZrmbk, + VCVTUQQ2PSZrmbkz, + VCVTUQQ2PSZrmk, + VCVTUQQ2PSZrmkz, + VCVTUQQ2PSZrr, + VCVTUQQ2PSZrrb, + VCVTUQQ2PSZrrbk, + VCVTUQQ2PSZrrbkz, + VCVTUQQ2PSZrrk, + VCVTUQQ2PSZrrkz, + VCVTUSI2SDZrm, + VCVTUSI2SDZrm_Int, + VCVTUSI2SDZrr, + VCVTUSI2SDZrr_Int, + VCVTUSI2SHZrm, + VCVTUSI2SHZrm_Int, + VCVTUSI2SHZrr, + VCVTUSI2SHZrr_Int, + VCVTUSI2SHZrrb_Int, + VCVTUSI2SSZrm, + VCVTUSI2SSZrm_Int, + VCVTUSI2SSZrr, + VCVTUSI2SSZrr_Int, + VCVTUSI2SSZrrb_Int, + VCVTUSI642SDZrm, + VCVTUSI642SDZrm_Int, + VCVTUSI642SDZrr, + VCVTUSI642SDZrr_Int, + VCVTUSI642SDZrrb_Int, + VCVTUSI642SHZrm, + VCVTUSI642SHZrm_Int, + VCVTUSI642SHZrr, + VCVTUSI642SHZrr_Int, + VCVTUSI642SHZrrb_Int, + VCVTUSI642SSZrm, + VCVTUSI642SSZrm_Int, + VCVTUSI642SSZrr, + VCVTUSI642SSZrr_Int, + VCVTUSI642SSZrrb_Int, + VCVTUW2PHZ128rm, + VCVTUW2PHZ128rmb, + VCVTUW2PHZ128rmbk, + VCVTUW2PHZ128rmbkz, + VCVTUW2PHZ128rmk, + VCVTUW2PHZ128rmkz, + VCVTUW2PHZ128rr, + VCVTUW2PHZ128rrk, + VCVTUW2PHZ128rrkz, + VCVTUW2PHZ256rm, + VCVTUW2PHZ256rmb, + VCVTUW2PHZ256rmbk, + VCVTUW2PHZ256rmbkz, + VCVTUW2PHZ256rmk, + VCVTUW2PHZ256rmkz, + VCVTUW2PHZ256rr, + VCVTUW2PHZ256rrk, + VCVTUW2PHZ256rrkz, + VCVTUW2PHZrm, + VCVTUW2PHZrmb, + VCVTUW2PHZrmbk, + VCVTUW2PHZrmbkz, + VCVTUW2PHZrmk, + VCVTUW2PHZrmkz, + VCVTUW2PHZrr, + VCVTUW2PHZrrb, + VCVTUW2PHZrrbk, + VCVTUW2PHZrrbkz, + VCVTUW2PHZrrk, + VCVTUW2PHZrrkz, + VCVTW2PHZ128rm, + VCVTW2PHZ128rmb, + VCVTW2PHZ128rmbk, + VCVTW2PHZ128rmbkz, + VCVTW2PHZ128rmk, + VCVTW2PHZ128rmkz, + VCVTW2PHZ128rr, + VCVTW2PHZ128rrk, + VCVTW2PHZ128rrkz, + VCVTW2PHZ256rm, + VCVTW2PHZ256rmb, + VCVTW2PHZ256rmbk, + VCVTW2PHZ256rmbkz, + VCVTW2PHZ256rmk, + VCVTW2PHZ256rmkz, + VCVTW2PHZ256rr, + VCVTW2PHZ256rrk, + VCVTW2PHZ256rrkz, + VCVTW2PHZrm, + VCVTW2PHZrmb, + VCVTW2PHZrmbk, + VCVTW2PHZrmbkz, + VCVTW2PHZrmk, + VCVTW2PHZrmkz, + VCVTW2PHZrr, + VCVTW2PHZrrb, + VCVTW2PHZrrbk, + VCVTW2PHZrrbkz, + VCVTW2PHZrrk, + VCVTW2PHZrrkz, + VDBPSADBWZ128rmi, + VDBPSADBWZ128rmik, + VDBPSADBWZ128rmikz, + VDBPSADBWZ128rri, + VDBPSADBWZ128rrik, + VDBPSADBWZ128rrikz, + VDBPSADBWZ256rmi, + VDBPSADBWZ256rmik, + VDBPSADBWZ256rmikz, + VDBPSADBWZ256rri, + VDBPSADBWZ256rrik, + VDBPSADBWZ256rrikz, + VDBPSADBWZrmi, + VDBPSADBWZrmik, + VDBPSADBWZrmikz, + VDBPSADBWZrri, + VDBPSADBWZrrik, + VDBPSADBWZrrikz, + VDIVBF16Z128rm, + VDIVBF16Z128rmb, + VDIVBF16Z128rmbk, + VDIVBF16Z128rmbkz, + VDIVBF16Z128rmk, + VDIVBF16Z128rmkz, + VDIVBF16Z128rr, + VDIVBF16Z128rrk, + VDIVBF16Z128rrkz, + VDIVBF16Z256rm, + VDIVBF16Z256rmb, + VDIVBF16Z256rmbk, + VDIVBF16Z256rmbkz, + VDIVBF16Z256rmk, + VDIVBF16Z256rmkz, + VDIVBF16Z256rr, + VDIVBF16Z256rrk, + VDIVBF16Z256rrkz, + VDIVBF16Zrm, + VDIVBF16Zrmb, + VDIVBF16Zrmbk, + VDIVBF16Zrmbkz, + VDIVBF16Zrmk, + VDIVBF16Zrmkz, + VDIVBF16Zrr, + VDIVBF16Zrrk, + VDIVBF16Zrrkz, + VDIVPDYrm, + VDIVPDYrr, + VDIVPDZ128rm, + VDIVPDZ128rmb, + VDIVPDZ128rmbk, + VDIVPDZ128rmbkz, + VDIVPDZ128rmk, + VDIVPDZ128rmkz, + VDIVPDZ128rr, + VDIVPDZ128rrk, + VDIVPDZ128rrkz, + VDIVPDZ256rm, + VDIVPDZ256rmb, + VDIVPDZ256rmbk, + VDIVPDZ256rmbkz, + VDIVPDZ256rmk, + VDIVPDZ256rmkz, + VDIVPDZ256rr, + VDIVPDZ256rrk, + VDIVPDZ256rrkz, + VDIVPDZrm, + VDIVPDZrmb, + VDIVPDZrmbk, + VDIVPDZrmbkz, + VDIVPDZrmk, + VDIVPDZrmkz, + VDIVPDZrr, + VDIVPDZrrb, + VDIVPDZrrbk, + VDIVPDZrrbkz, + VDIVPDZrrk, + VDIVPDZrrkz, + VDIVPDrm, + VDIVPDrr, + VDIVPHZ128rm, + VDIVPHZ128rmb, + VDIVPHZ128rmbk, + VDIVPHZ128rmbkz, + VDIVPHZ128rmk, + VDIVPHZ128rmkz, + VDIVPHZ128rr, + VDIVPHZ128rrk, + VDIVPHZ128rrkz, + VDIVPHZ256rm, + VDIVPHZ256rmb, + VDIVPHZ256rmbk, + VDIVPHZ256rmbkz, + VDIVPHZ256rmk, + VDIVPHZ256rmkz, + VDIVPHZ256rr, + VDIVPHZ256rrk, + VDIVPHZ256rrkz, + VDIVPHZrm, + VDIVPHZrmb, + VDIVPHZrmbk, + VDIVPHZrmbkz, + VDIVPHZrmk, + VDIVPHZrmkz, + VDIVPHZrr, + VDIVPHZrrb, + VDIVPHZrrbk, + VDIVPHZrrbkz, + VDIVPHZrrk, + VDIVPHZrrkz, + VDIVPSYrm, + VDIVPSYrr, + VDIVPSZ128rm, + VDIVPSZ128rmb, + VDIVPSZ128rmbk, + VDIVPSZ128rmbkz, + VDIVPSZ128rmk, + VDIVPSZ128rmkz, + VDIVPSZ128rr, + VDIVPSZ128rrk, + VDIVPSZ128rrkz, + VDIVPSZ256rm, + VDIVPSZ256rmb, + VDIVPSZ256rmbk, + VDIVPSZ256rmbkz, + VDIVPSZ256rmk, + VDIVPSZ256rmkz, + VDIVPSZ256rr, + VDIVPSZ256rrk, + VDIVPSZ256rrkz, + VDIVPSZrm, + VDIVPSZrmb, + VDIVPSZrmbk, + VDIVPSZrmbkz, + VDIVPSZrmk, + VDIVPSZrmkz, + VDIVPSZrr, + VDIVPSZrrb, + VDIVPSZrrbk, + VDIVPSZrrbkz, + VDIVPSZrrk, + VDIVPSZrrkz, + VDIVPSrm, + VDIVPSrr, + VDIVSDZrm, + VDIVSDZrm_Int, + VDIVSDZrmk_Int, + VDIVSDZrmkz_Int, + VDIVSDZrr, + VDIVSDZrr_Int, + VDIVSDZrrb_Int, + VDIVSDZrrbk_Int, + VDIVSDZrrbkz_Int, + VDIVSDZrrk_Int, + VDIVSDZrrkz_Int, + VDIVSDrm, + VDIVSDrm_Int, + VDIVSDrr, + VDIVSDrr_Int, + VDIVSHZrm, + VDIVSHZrm_Int, + VDIVSHZrmk_Int, + VDIVSHZrmkz_Int, + VDIVSHZrr, + VDIVSHZrr_Int, + VDIVSHZrrb_Int, + VDIVSHZrrbk_Int, + VDIVSHZrrbkz_Int, + VDIVSHZrrk_Int, + VDIVSHZrrkz_Int, + VDIVSSZrm, + VDIVSSZrm_Int, + VDIVSSZrmk_Int, + VDIVSSZrmkz_Int, + VDIVSSZrr, + VDIVSSZrr_Int, + VDIVSSZrrb_Int, + VDIVSSZrrbk_Int, + VDIVSSZrrbkz_Int, + VDIVSSZrrk_Int, + VDIVSSZrrkz_Int, + VDIVSSrm, + VDIVSSrm_Int, + VDIVSSrr, + VDIVSSrr_Int, + VDPBF16PSZ128m, + VDPBF16PSZ128mb, + VDPBF16PSZ128mbk, + VDPBF16PSZ128mbkz, + VDPBF16PSZ128mk, + VDPBF16PSZ128mkz, + VDPBF16PSZ128r, + VDPBF16PSZ128rk, + VDPBF16PSZ128rkz, + VDPBF16PSZ256m, + VDPBF16PSZ256mb, + VDPBF16PSZ256mbk, + VDPBF16PSZ256mbkz, + VDPBF16PSZ256mk, + VDPBF16PSZ256mkz, + VDPBF16PSZ256r, + VDPBF16PSZ256rk, + VDPBF16PSZ256rkz, + VDPBF16PSZm, + VDPBF16PSZmb, + VDPBF16PSZmbk, + VDPBF16PSZmbkz, + VDPBF16PSZmk, + VDPBF16PSZmkz, + VDPBF16PSZr, + VDPBF16PSZrk, + VDPBF16PSZrkz, + VDPPDrmi, + VDPPDrri, + VDPPHPSZ128m, + VDPPHPSZ128mb, + VDPPHPSZ128mbk, + VDPPHPSZ128mbkz, + VDPPHPSZ128mk, + VDPPHPSZ128mkz, + VDPPHPSZ128r, + VDPPHPSZ128rk, + VDPPHPSZ128rkz, + VDPPHPSZ256m, + VDPPHPSZ256mb, + VDPPHPSZ256mbk, + VDPPHPSZ256mbkz, + VDPPHPSZ256mk, + VDPPHPSZ256mkz, + VDPPHPSZ256r, + VDPPHPSZ256rk, + VDPPHPSZ256rkz, + VDPPHPSZm, + VDPPHPSZmb, + VDPPHPSZmbk, + VDPPHPSZmbkz, + VDPPHPSZmk, + VDPPHPSZmkz, + VDPPHPSZr, + VDPPHPSZrk, + VDPPHPSZrkz, + VDPPSYrmi, + VDPPSYrri, + VDPPSrmi, + VDPPSrri, + VERRm, + VERRr, + VERWm, + VERWr, + VEXP2PDZm, + VEXP2PDZmb, + VEXP2PDZmbk, + VEXP2PDZmbkz, + VEXP2PDZmk, + VEXP2PDZmkz, + VEXP2PDZr, + VEXP2PDZrb, + VEXP2PDZrbk, + VEXP2PDZrbkz, + VEXP2PDZrk, + VEXP2PDZrkz, + VEXP2PSZm, + VEXP2PSZmb, + VEXP2PSZmbk, + VEXP2PSZmbkz, + VEXP2PSZmk, + VEXP2PSZmkz, + VEXP2PSZr, + VEXP2PSZrb, + VEXP2PSZrbk, + VEXP2PSZrbkz, + VEXP2PSZrk, + VEXP2PSZrkz, + VEXPANDPDZ128rm, + VEXPANDPDZ128rmk, + VEXPANDPDZ128rmkz, + VEXPANDPDZ128rr, + VEXPANDPDZ128rrk, + VEXPANDPDZ128rrkz, + VEXPANDPDZ256rm, + VEXPANDPDZ256rmk, + VEXPANDPDZ256rmkz, + VEXPANDPDZ256rr, + VEXPANDPDZ256rrk, + VEXPANDPDZ256rrkz, + VEXPANDPDZrm, + VEXPANDPDZrmk, + VEXPANDPDZrmkz, + VEXPANDPDZrr, + VEXPANDPDZrrk, + VEXPANDPDZrrkz, + VEXPANDPSZ128rm, + VEXPANDPSZ128rmk, + VEXPANDPSZ128rmkz, + VEXPANDPSZ128rr, + VEXPANDPSZ128rrk, + VEXPANDPSZ128rrkz, + VEXPANDPSZ256rm, + VEXPANDPSZ256rmk, + VEXPANDPSZ256rmkz, + VEXPANDPSZ256rr, + VEXPANDPSZ256rrk, + VEXPANDPSZ256rrkz, + VEXPANDPSZrm, + VEXPANDPSZrmk, + VEXPANDPSZrmkz, + VEXPANDPSZrr, + VEXPANDPSZrrk, + VEXPANDPSZrrkz, + VEXTRACTF128mri, + VEXTRACTF128rri, + VEXTRACTF32X4Z256mri, + VEXTRACTF32X4Z256mrik, + VEXTRACTF32X4Z256rri, + VEXTRACTF32X4Z256rrik, + VEXTRACTF32X4Z256rrikz, + VEXTRACTF32X4Zmri, + VEXTRACTF32X4Zmrik, + VEXTRACTF32X4Zrri, + VEXTRACTF32X4Zrrik, + VEXTRACTF32X4Zrrikz, + VEXTRACTF32X8Zmri, + VEXTRACTF32X8Zmrik, + VEXTRACTF32X8Zrri, + VEXTRACTF32X8Zrrik, + VEXTRACTF32X8Zrrikz, + VEXTRACTF64X2Z256mri, + VEXTRACTF64X2Z256mrik, + VEXTRACTF64X2Z256rri, + VEXTRACTF64X2Z256rrik, + VEXTRACTF64X2Z256rrikz, + VEXTRACTF64X2Zmri, + VEXTRACTF64X2Zmrik, + VEXTRACTF64X2Zrri, + VEXTRACTF64X2Zrrik, + VEXTRACTF64X2Zrrikz, + VEXTRACTF64X4Zmri, + VEXTRACTF64X4Zmrik, + VEXTRACTF64X4Zrri, + VEXTRACTF64X4Zrrik, + VEXTRACTF64X4Zrrikz, + VEXTRACTI128mri, + VEXTRACTI128rri, + VEXTRACTI32X4Z256mri, + VEXTRACTI32X4Z256mrik, + VEXTRACTI32X4Z256rri, + VEXTRACTI32X4Z256rrik, + VEXTRACTI32X4Z256rrikz, + VEXTRACTI32X4Zmri, + VEXTRACTI32X4Zmrik, + VEXTRACTI32X4Zrri, + VEXTRACTI32X4Zrrik, + VEXTRACTI32X4Zrrikz, + VEXTRACTI32X8Zmri, + VEXTRACTI32X8Zmrik, + VEXTRACTI32X8Zrri, + VEXTRACTI32X8Zrrik, + VEXTRACTI32X8Zrrikz, + VEXTRACTI64X2Z256mri, + VEXTRACTI64X2Z256mrik, + VEXTRACTI64X2Z256rri, + VEXTRACTI64X2Z256rrik, + VEXTRACTI64X2Z256rrikz, + VEXTRACTI64X2Zmri, + VEXTRACTI64X2Zmrik, + VEXTRACTI64X2Zrri, + VEXTRACTI64X2Zrrik, + VEXTRACTI64X2Zrrikz, + VEXTRACTI64X4Zmri, + VEXTRACTI64X4Zmrik, + VEXTRACTI64X4Zrri, + VEXTRACTI64X4Zrrik, + VEXTRACTI64X4Zrrikz, + VEXTRACTPSZmri, + VEXTRACTPSZrri, + VEXTRACTPSmri, + VEXTRACTPSrri, + VFCMADDCPHZ128m, + VFCMADDCPHZ128mb, + VFCMADDCPHZ128mbk, + VFCMADDCPHZ128mbkz, + VFCMADDCPHZ128mk, + VFCMADDCPHZ128mkz, + VFCMADDCPHZ128r, + VFCMADDCPHZ128rk, + VFCMADDCPHZ128rkz, + VFCMADDCPHZ256m, + VFCMADDCPHZ256mb, + VFCMADDCPHZ256mbk, + VFCMADDCPHZ256mbkz, + VFCMADDCPHZ256mk, + VFCMADDCPHZ256mkz, + VFCMADDCPHZ256r, + VFCMADDCPHZ256rk, + VFCMADDCPHZ256rkz, + VFCMADDCPHZm, + VFCMADDCPHZmb, + VFCMADDCPHZmbk, + VFCMADDCPHZmbkz, + VFCMADDCPHZmk, + VFCMADDCPHZmkz, + VFCMADDCPHZr, + VFCMADDCPHZrb, + VFCMADDCPHZrbk, + VFCMADDCPHZrbkz, + VFCMADDCPHZrk, + VFCMADDCPHZrkz, + VFCMADDCSHZm, + VFCMADDCSHZmk, + VFCMADDCSHZmkz, + VFCMADDCSHZr, + VFCMADDCSHZrb, + VFCMADDCSHZrbk, + VFCMADDCSHZrbkz, + VFCMADDCSHZrk, + VFCMADDCSHZrkz, + VFCMULCPHZ128rm, + VFCMULCPHZ128rmb, + VFCMULCPHZ128rmbk, + VFCMULCPHZ128rmbkz, + VFCMULCPHZ128rmk, + VFCMULCPHZ128rmkz, + VFCMULCPHZ128rr, + VFCMULCPHZ128rrk, + VFCMULCPHZ128rrkz, + VFCMULCPHZ256rm, + VFCMULCPHZ256rmb, + VFCMULCPHZ256rmbk, + VFCMULCPHZ256rmbkz, + VFCMULCPHZ256rmk, + VFCMULCPHZ256rmkz, + VFCMULCPHZ256rr, + VFCMULCPHZ256rrk, + VFCMULCPHZ256rrkz, + VFCMULCPHZrm, + VFCMULCPHZrmb, + VFCMULCPHZrmbk, + VFCMULCPHZrmbkz, + VFCMULCPHZrmk, + VFCMULCPHZrmkz, + VFCMULCPHZrr, + VFCMULCPHZrrb, + VFCMULCPHZrrbk, + VFCMULCPHZrrbkz, + VFCMULCPHZrrk, + VFCMULCPHZrrkz, + VFCMULCSHZrm, + VFCMULCSHZrmk, + VFCMULCSHZrmkz, + VFCMULCSHZrr, + VFCMULCSHZrrb, + VFCMULCSHZrrbk, + VFCMULCSHZrrbkz, + VFCMULCSHZrrk, + VFCMULCSHZrrkz, + VFIXUPIMMPDZ128rmbi, + VFIXUPIMMPDZ128rmbik, + VFIXUPIMMPDZ128rmbikz, + VFIXUPIMMPDZ128rmi, + VFIXUPIMMPDZ128rmik, + VFIXUPIMMPDZ128rmikz, + VFIXUPIMMPDZ128rri, + VFIXUPIMMPDZ128rrik, + VFIXUPIMMPDZ128rrikz, + VFIXUPIMMPDZ256rmbi, + VFIXUPIMMPDZ256rmbik, + VFIXUPIMMPDZ256rmbikz, + VFIXUPIMMPDZ256rmi, + VFIXUPIMMPDZ256rmik, + VFIXUPIMMPDZ256rmikz, + VFIXUPIMMPDZ256rri, + VFIXUPIMMPDZ256rrik, + VFIXUPIMMPDZ256rrikz, + VFIXUPIMMPDZrmbi, + VFIXUPIMMPDZrmbik, + VFIXUPIMMPDZrmbikz, + VFIXUPIMMPDZrmi, + VFIXUPIMMPDZrmik, + VFIXUPIMMPDZrmikz, + VFIXUPIMMPDZrri, + VFIXUPIMMPDZrrib, + VFIXUPIMMPDZrribk, + VFIXUPIMMPDZrribkz, + VFIXUPIMMPDZrrik, + VFIXUPIMMPDZrrikz, + VFIXUPIMMPSZ128rmbi, + VFIXUPIMMPSZ128rmbik, + VFIXUPIMMPSZ128rmbikz, + VFIXUPIMMPSZ128rmi, + VFIXUPIMMPSZ128rmik, + VFIXUPIMMPSZ128rmikz, + VFIXUPIMMPSZ128rri, + VFIXUPIMMPSZ128rrik, + VFIXUPIMMPSZ128rrikz, + VFIXUPIMMPSZ256rmbi, + VFIXUPIMMPSZ256rmbik, + VFIXUPIMMPSZ256rmbikz, + VFIXUPIMMPSZ256rmi, + VFIXUPIMMPSZ256rmik, + VFIXUPIMMPSZ256rmikz, + VFIXUPIMMPSZ256rri, + VFIXUPIMMPSZ256rrik, + VFIXUPIMMPSZ256rrikz, + VFIXUPIMMPSZrmbi, + VFIXUPIMMPSZrmbik, + VFIXUPIMMPSZrmbikz, + VFIXUPIMMPSZrmi, + VFIXUPIMMPSZrmik, + VFIXUPIMMPSZrmikz, + VFIXUPIMMPSZrri, + VFIXUPIMMPSZrrib, + VFIXUPIMMPSZrribk, + VFIXUPIMMPSZrribkz, + VFIXUPIMMPSZrrik, + VFIXUPIMMPSZrrikz, + VFIXUPIMMSDZrmi, + VFIXUPIMMSDZrmik, + VFIXUPIMMSDZrmikz, + VFIXUPIMMSDZrri, + VFIXUPIMMSDZrrib, + VFIXUPIMMSDZrribk, + VFIXUPIMMSDZrribkz, + VFIXUPIMMSDZrrik, + VFIXUPIMMSDZrrikz, + VFIXUPIMMSSZrmi, + VFIXUPIMMSSZrmik, + VFIXUPIMMSSZrmikz, + VFIXUPIMMSSZrri, + VFIXUPIMMSSZrrib, + VFIXUPIMMSSZrribk, + VFIXUPIMMSSZrribkz, + VFIXUPIMMSSZrrik, + VFIXUPIMMSSZrrikz, + VFMADD132BF16Z128m, + VFMADD132BF16Z128mb, + VFMADD132BF16Z128mbk, + VFMADD132BF16Z128mbkz, + VFMADD132BF16Z128mk, + VFMADD132BF16Z128mkz, + VFMADD132BF16Z128r, + VFMADD132BF16Z128rk, + VFMADD132BF16Z128rkz, + VFMADD132BF16Z256m, + VFMADD132BF16Z256mb, + VFMADD132BF16Z256mbk, + VFMADD132BF16Z256mbkz, + VFMADD132BF16Z256mk, + VFMADD132BF16Z256mkz, + VFMADD132BF16Z256r, + VFMADD132BF16Z256rk, + VFMADD132BF16Z256rkz, + VFMADD132BF16Zm, + VFMADD132BF16Zmb, + VFMADD132BF16Zmbk, + VFMADD132BF16Zmbkz, + VFMADD132BF16Zmk, + VFMADD132BF16Zmkz, + VFMADD132BF16Zr, + VFMADD132BF16Zrk, + VFMADD132BF16Zrkz, + VFMADD132PDYm, + VFMADD132PDYr, + VFMADD132PDZ128m, + VFMADD132PDZ128mb, + VFMADD132PDZ128mbk, + VFMADD132PDZ128mbkz, + VFMADD132PDZ128mk, + VFMADD132PDZ128mkz, + VFMADD132PDZ128r, + VFMADD132PDZ128rk, + VFMADD132PDZ128rkz, + VFMADD132PDZ256m, + VFMADD132PDZ256mb, + VFMADD132PDZ256mbk, + VFMADD132PDZ256mbkz, + VFMADD132PDZ256mk, + VFMADD132PDZ256mkz, + VFMADD132PDZ256r, + VFMADD132PDZ256rk, + VFMADD132PDZ256rkz, + VFMADD132PDZm, + VFMADD132PDZmb, + VFMADD132PDZmbk, + VFMADD132PDZmbkz, + VFMADD132PDZmk, + VFMADD132PDZmkz, + VFMADD132PDZr, + VFMADD132PDZrb, + VFMADD132PDZrbk, + VFMADD132PDZrbkz, + VFMADD132PDZrk, + VFMADD132PDZrkz, + VFMADD132PDm, + VFMADD132PDr, + VFMADD132PHZ128m, + VFMADD132PHZ128mb, + VFMADD132PHZ128mbk, + VFMADD132PHZ128mbkz, + VFMADD132PHZ128mk, + VFMADD132PHZ128mkz, + VFMADD132PHZ128r, + VFMADD132PHZ128rk, + VFMADD132PHZ128rkz, + VFMADD132PHZ256m, + VFMADD132PHZ256mb, + VFMADD132PHZ256mbk, + VFMADD132PHZ256mbkz, + VFMADD132PHZ256mk, + VFMADD132PHZ256mkz, + VFMADD132PHZ256r, + VFMADD132PHZ256rk, + VFMADD132PHZ256rkz, + VFMADD132PHZm, + VFMADD132PHZmb, + VFMADD132PHZmbk, + VFMADD132PHZmbkz, + VFMADD132PHZmk, + VFMADD132PHZmkz, + VFMADD132PHZr, + VFMADD132PHZrb, + VFMADD132PHZrbk, + VFMADD132PHZrbkz, + VFMADD132PHZrk, + VFMADD132PHZrkz, + VFMADD132PSYm, + VFMADD132PSYr, + VFMADD132PSZ128m, + VFMADD132PSZ128mb, + VFMADD132PSZ128mbk, + VFMADD132PSZ128mbkz, + VFMADD132PSZ128mk, + VFMADD132PSZ128mkz, + VFMADD132PSZ128r, + VFMADD132PSZ128rk, + VFMADD132PSZ128rkz, + VFMADD132PSZ256m, + VFMADD132PSZ256mb, + VFMADD132PSZ256mbk, + VFMADD132PSZ256mbkz, + VFMADD132PSZ256mk, + VFMADD132PSZ256mkz, + VFMADD132PSZ256r, + VFMADD132PSZ256rk, + VFMADD132PSZ256rkz, + VFMADD132PSZm, + VFMADD132PSZmb, + VFMADD132PSZmbk, + VFMADD132PSZmbkz, + VFMADD132PSZmk, + VFMADD132PSZmkz, + VFMADD132PSZr, + VFMADD132PSZrb, + VFMADD132PSZrbk, + VFMADD132PSZrbkz, + VFMADD132PSZrk, + VFMADD132PSZrkz, + VFMADD132PSm, + VFMADD132PSr, + VFMADD132SDZm, + VFMADD132SDZm_Int, + VFMADD132SDZmk_Int, + VFMADD132SDZmkz_Int, + VFMADD132SDZr, + VFMADD132SDZr_Int, + VFMADD132SDZrb, + VFMADD132SDZrb_Int, + VFMADD132SDZrbk_Int, + VFMADD132SDZrbkz_Int, + VFMADD132SDZrk_Int, + VFMADD132SDZrkz_Int, + VFMADD132SDm, + VFMADD132SDm_Int, + VFMADD132SDr, + VFMADD132SDr_Int, + VFMADD132SHZm, + VFMADD132SHZm_Int, + VFMADD132SHZmk_Int, + VFMADD132SHZmkz_Int, + VFMADD132SHZr, + VFMADD132SHZr_Int, + VFMADD132SHZrb, + VFMADD132SHZrb_Int, + VFMADD132SHZrbk_Int, + VFMADD132SHZrbkz_Int, + VFMADD132SHZrk_Int, + VFMADD132SHZrkz_Int, + VFMADD132SSZm, + VFMADD132SSZm_Int, + VFMADD132SSZmk_Int, + VFMADD132SSZmkz_Int, + VFMADD132SSZr, + VFMADD132SSZr_Int, + VFMADD132SSZrb, + VFMADD132SSZrb_Int, + VFMADD132SSZrbk_Int, + VFMADD132SSZrbkz_Int, + VFMADD132SSZrk_Int, + VFMADD132SSZrkz_Int, + VFMADD132SSm, + VFMADD132SSm_Int, + VFMADD132SSr, + VFMADD132SSr_Int, + VFMADD213BF16Z128m, + VFMADD213BF16Z128mb, + VFMADD213BF16Z128mbk, + VFMADD213BF16Z128mbkz, + VFMADD213BF16Z128mk, + VFMADD213BF16Z128mkz, + VFMADD213BF16Z128r, + VFMADD213BF16Z128rk, + VFMADD213BF16Z128rkz, + VFMADD213BF16Z256m, + VFMADD213BF16Z256mb, + VFMADD213BF16Z256mbk, + VFMADD213BF16Z256mbkz, + VFMADD213BF16Z256mk, + VFMADD213BF16Z256mkz, + VFMADD213BF16Z256r, + VFMADD213BF16Z256rk, + VFMADD213BF16Z256rkz, + VFMADD213BF16Zm, + VFMADD213BF16Zmb, + VFMADD213BF16Zmbk, + VFMADD213BF16Zmbkz, + VFMADD213BF16Zmk, + VFMADD213BF16Zmkz, + VFMADD213BF16Zr, + VFMADD213BF16Zrk, + VFMADD213BF16Zrkz, + VFMADD213PDYm, + VFMADD213PDYr, + VFMADD213PDZ128m, + VFMADD213PDZ128mb, + VFMADD213PDZ128mbk, + VFMADD213PDZ128mbkz, + VFMADD213PDZ128mk, + VFMADD213PDZ128mkz, + VFMADD213PDZ128r, + VFMADD213PDZ128rk, + VFMADD213PDZ128rkz, + VFMADD213PDZ256m, + VFMADD213PDZ256mb, + VFMADD213PDZ256mbk, + VFMADD213PDZ256mbkz, + VFMADD213PDZ256mk, + VFMADD213PDZ256mkz, + VFMADD213PDZ256r, + VFMADD213PDZ256rk, + VFMADD213PDZ256rkz, + VFMADD213PDZm, + VFMADD213PDZmb, + VFMADD213PDZmbk, + VFMADD213PDZmbkz, + VFMADD213PDZmk, + VFMADD213PDZmkz, + VFMADD213PDZr, + VFMADD213PDZrb, + VFMADD213PDZrbk, + VFMADD213PDZrbkz, + VFMADD213PDZrk, + VFMADD213PDZrkz, + VFMADD213PDm, + VFMADD213PDr, + VFMADD213PHZ128m, + VFMADD213PHZ128mb, + VFMADD213PHZ128mbk, + VFMADD213PHZ128mbkz, + VFMADD213PHZ128mk, + VFMADD213PHZ128mkz, + VFMADD213PHZ128r, + VFMADD213PHZ128rk, + VFMADD213PHZ128rkz, + VFMADD213PHZ256m, + VFMADD213PHZ256mb, + VFMADD213PHZ256mbk, + VFMADD213PHZ256mbkz, + VFMADD213PHZ256mk, + VFMADD213PHZ256mkz, + VFMADD213PHZ256r, + VFMADD213PHZ256rk, + VFMADD213PHZ256rkz, + VFMADD213PHZm, + VFMADD213PHZmb, + VFMADD213PHZmbk, + VFMADD213PHZmbkz, + VFMADD213PHZmk, + VFMADD213PHZmkz, + VFMADD213PHZr, + VFMADD213PHZrb, + VFMADD213PHZrbk, + VFMADD213PHZrbkz, + VFMADD213PHZrk, + VFMADD213PHZrkz, + VFMADD213PSYm, + VFMADD213PSYr, + VFMADD213PSZ128m, + VFMADD213PSZ128mb, + VFMADD213PSZ128mbk, + VFMADD213PSZ128mbkz, + VFMADD213PSZ128mk, + VFMADD213PSZ128mkz, + VFMADD213PSZ128r, + VFMADD213PSZ128rk, + VFMADD213PSZ128rkz, + VFMADD213PSZ256m, + VFMADD213PSZ256mb, + VFMADD213PSZ256mbk, + VFMADD213PSZ256mbkz, + VFMADD213PSZ256mk, + VFMADD213PSZ256mkz, + VFMADD213PSZ256r, + VFMADD213PSZ256rk, + VFMADD213PSZ256rkz, + VFMADD213PSZm, + VFMADD213PSZmb, + VFMADD213PSZmbk, + VFMADD213PSZmbkz, + VFMADD213PSZmk, + VFMADD213PSZmkz, + VFMADD213PSZr, + VFMADD213PSZrb, + VFMADD213PSZrbk, + VFMADD213PSZrbkz, + VFMADD213PSZrk, + VFMADD213PSZrkz, + VFMADD213PSm, + VFMADD213PSr, + VFMADD213SDZm, + VFMADD213SDZm_Int, + VFMADD213SDZmk_Int, + VFMADD213SDZmkz_Int, + VFMADD213SDZr, + VFMADD213SDZr_Int, + VFMADD213SDZrb, + VFMADD213SDZrb_Int, + VFMADD213SDZrbk_Int, + VFMADD213SDZrbkz_Int, + VFMADD213SDZrk_Int, + VFMADD213SDZrkz_Int, + VFMADD213SDm, + VFMADD213SDm_Int, + VFMADD213SDr, + VFMADD213SDr_Int, + VFMADD213SHZm, + VFMADD213SHZm_Int, + VFMADD213SHZmk_Int, + VFMADD213SHZmkz_Int, + VFMADD213SHZr, + VFMADD213SHZr_Int, + VFMADD213SHZrb, + VFMADD213SHZrb_Int, + VFMADD213SHZrbk_Int, + VFMADD213SHZrbkz_Int, + VFMADD213SHZrk_Int, + VFMADD213SHZrkz_Int, + VFMADD213SSZm, + VFMADD213SSZm_Int, + VFMADD213SSZmk_Int, + VFMADD213SSZmkz_Int, + VFMADD213SSZr, + VFMADD213SSZr_Int, + VFMADD213SSZrb, + VFMADD213SSZrb_Int, + VFMADD213SSZrbk_Int, + VFMADD213SSZrbkz_Int, + VFMADD213SSZrk_Int, + VFMADD213SSZrkz_Int, + VFMADD213SSm, + VFMADD213SSm_Int, + VFMADD213SSr, + VFMADD213SSr_Int, + VFMADD231BF16Z128m, + VFMADD231BF16Z128mb, + VFMADD231BF16Z128mbk, + VFMADD231BF16Z128mbkz, + VFMADD231BF16Z128mk, + VFMADD231BF16Z128mkz, + VFMADD231BF16Z128r, + VFMADD231BF16Z128rk, + VFMADD231BF16Z128rkz, + VFMADD231BF16Z256m, + VFMADD231BF16Z256mb, + VFMADD231BF16Z256mbk, + VFMADD231BF16Z256mbkz, + VFMADD231BF16Z256mk, + VFMADD231BF16Z256mkz, + VFMADD231BF16Z256r, + VFMADD231BF16Z256rk, + VFMADD231BF16Z256rkz, + VFMADD231BF16Zm, + VFMADD231BF16Zmb, + VFMADD231BF16Zmbk, + VFMADD231BF16Zmbkz, + VFMADD231BF16Zmk, + VFMADD231BF16Zmkz, + VFMADD231BF16Zr, + VFMADD231BF16Zrk, + VFMADD231BF16Zrkz, + VFMADD231PDYm, + VFMADD231PDYr, + VFMADD231PDZ128m, + VFMADD231PDZ128mb, + VFMADD231PDZ128mbk, + VFMADD231PDZ128mbkz, + VFMADD231PDZ128mk, + VFMADD231PDZ128mkz, + VFMADD231PDZ128r, + VFMADD231PDZ128rk, + VFMADD231PDZ128rkz, + VFMADD231PDZ256m, + VFMADD231PDZ256mb, + VFMADD231PDZ256mbk, + VFMADD231PDZ256mbkz, + VFMADD231PDZ256mk, + VFMADD231PDZ256mkz, + VFMADD231PDZ256r, + VFMADD231PDZ256rk, + VFMADD231PDZ256rkz, + VFMADD231PDZm, + VFMADD231PDZmb, + VFMADD231PDZmbk, + VFMADD231PDZmbkz, + VFMADD231PDZmk, + VFMADD231PDZmkz, + VFMADD231PDZr, + VFMADD231PDZrb, + VFMADD231PDZrbk, + VFMADD231PDZrbkz, + VFMADD231PDZrk, + VFMADD231PDZrkz, + VFMADD231PDm, + VFMADD231PDr, + VFMADD231PHZ128m, + VFMADD231PHZ128mb, + VFMADD231PHZ128mbk, + VFMADD231PHZ128mbkz, + VFMADD231PHZ128mk, + VFMADD231PHZ128mkz, + VFMADD231PHZ128r, + VFMADD231PHZ128rk, + VFMADD231PHZ128rkz, + VFMADD231PHZ256m, + VFMADD231PHZ256mb, + VFMADD231PHZ256mbk, + VFMADD231PHZ256mbkz, + VFMADD231PHZ256mk, + VFMADD231PHZ256mkz, + VFMADD231PHZ256r, + VFMADD231PHZ256rk, + VFMADD231PHZ256rkz, + VFMADD231PHZm, + VFMADD231PHZmb, + VFMADD231PHZmbk, + VFMADD231PHZmbkz, + VFMADD231PHZmk, + VFMADD231PHZmkz, + VFMADD231PHZr, + VFMADD231PHZrb, + VFMADD231PHZrbk, + VFMADD231PHZrbkz, + VFMADD231PHZrk, + VFMADD231PHZrkz, + VFMADD231PSYm, + VFMADD231PSYr, + VFMADD231PSZ128m, + VFMADD231PSZ128mb, + VFMADD231PSZ128mbk, + VFMADD231PSZ128mbkz, + VFMADD231PSZ128mk, + VFMADD231PSZ128mkz, + VFMADD231PSZ128r, + VFMADD231PSZ128rk, + VFMADD231PSZ128rkz, + VFMADD231PSZ256m, + VFMADD231PSZ256mb, + VFMADD231PSZ256mbk, + VFMADD231PSZ256mbkz, + VFMADD231PSZ256mk, + VFMADD231PSZ256mkz, + VFMADD231PSZ256r, + VFMADD231PSZ256rk, + VFMADD231PSZ256rkz, + VFMADD231PSZm, + VFMADD231PSZmb, + VFMADD231PSZmbk, + VFMADD231PSZmbkz, + VFMADD231PSZmk, + VFMADD231PSZmkz, + VFMADD231PSZr, + VFMADD231PSZrb, + VFMADD231PSZrbk, + VFMADD231PSZrbkz, + VFMADD231PSZrk, + VFMADD231PSZrkz, + VFMADD231PSm, + VFMADD231PSr, + VFMADD231SDZm, + VFMADD231SDZm_Int, + VFMADD231SDZmk_Int, + VFMADD231SDZmkz_Int, + VFMADD231SDZr, + VFMADD231SDZr_Int, + VFMADD231SDZrb, + VFMADD231SDZrb_Int, + VFMADD231SDZrbk_Int, + VFMADD231SDZrbkz_Int, + VFMADD231SDZrk_Int, + VFMADD231SDZrkz_Int, + VFMADD231SDm, + VFMADD231SDm_Int, + VFMADD231SDr, + VFMADD231SDr_Int, + VFMADD231SHZm, + VFMADD231SHZm_Int, + VFMADD231SHZmk_Int, + VFMADD231SHZmkz_Int, + VFMADD231SHZr, + VFMADD231SHZr_Int, + VFMADD231SHZrb, + VFMADD231SHZrb_Int, + VFMADD231SHZrbk_Int, + VFMADD231SHZrbkz_Int, + VFMADD231SHZrk_Int, + VFMADD231SHZrkz_Int, + VFMADD231SSZm, + VFMADD231SSZm_Int, + VFMADD231SSZmk_Int, + VFMADD231SSZmkz_Int, + VFMADD231SSZr, + VFMADD231SSZr_Int, + VFMADD231SSZrb, + VFMADD231SSZrb_Int, + VFMADD231SSZrbk_Int, + VFMADD231SSZrbkz_Int, + VFMADD231SSZrk_Int, + VFMADD231SSZrkz_Int, + VFMADD231SSm, + VFMADD231SSm_Int, + VFMADD231SSr, + VFMADD231SSr_Int, + VFMADDCPHZ128m, + VFMADDCPHZ128mb, + VFMADDCPHZ128mbk, + VFMADDCPHZ128mbkz, + VFMADDCPHZ128mk, + VFMADDCPHZ128mkz, + VFMADDCPHZ128r, + VFMADDCPHZ128rk, + VFMADDCPHZ128rkz, + VFMADDCPHZ256m, + VFMADDCPHZ256mb, + VFMADDCPHZ256mbk, + VFMADDCPHZ256mbkz, + VFMADDCPHZ256mk, + VFMADDCPHZ256mkz, + VFMADDCPHZ256r, + VFMADDCPHZ256rk, + VFMADDCPHZ256rkz, + VFMADDCPHZm, + VFMADDCPHZmb, + VFMADDCPHZmbk, + VFMADDCPHZmbkz, + VFMADDCPHZmk, + VFMADDCPHZmkz, + VFMADDCPHZr, + VFMADDCPHZrb, + VFMADDCPHZrbk, + VFMADDCPHZrbkz, + VFMADDCPHZrk, + VFMADDCPHZrkz, + VFMADDCSHZm, + VFMADDCSHZmk, + VFMADDCSHZmkz, + VFMADDCSHZr, + VFMADDCSHZrb, + VFMADDCSHZrbk, + VFMADDCSHZrbkz, + VFMADDCSHZrk, + VFMADDCSHZrkz, + VFMADDPD4Ymr, + VFMADDPD4Yrm, + VFMADDPD4Yrr, + VFMADDPD4Yrr_REV, + VFMADDPD4mr, + VFMADDPD4rm, + VFMADDPD4rr, + VFMADDPD4rr_REV, + VFMADDPS4Ymr, + VFMADDPS4Yrm, + VFMADDPS4Yrr, + VFMADDPS4Yrr_REV, + VFMADDPS4mr, + VFMADDPS4rm, + VFMADDPS4rr, + VFMADDPS4rr_REV, + VFMADDSD4mr, + VFMADDSD4mr_Int, + VFMADDSD4rm, + VFMADDSD4rm_Int, + VFMADDSD4rr, + VFMADDSD4rr_Int, + VFMADDSD4rr_Int_REV, + VFMADDSD4rr_REV, + VFMADDSS4mr, + VFMADDSS4mr_Int, + VFMADDSS4rm, + VFMADDSS4rm_Int, + VFMADDSS4rr, + VFMADDSS4rr_Int, + VFMADDSS4rr_Int_REV, + VFMADDSS4rr_REV, + VFMADDSUB132PDYm, + VFMADDSUB132PDYr, + VFMADDSUB132PDZ128m, + VFMADDSUB132PDZ128mb, + VFMADDSUB132PDZ128mbk, + VFMADDSUB132PDZ128mbkz, + VFMADDSUB132PDZ128mk, + VFMADDSUB132PDZ128mkz, + VFMADDSUB132PDZ128r, + VFMADDSUB132PDZ128rk, + VFMADDSUB132PDZ128rkz, + VFMADDSUB132PDZ256m, + VFMADDSUB132PDZ256mb, + VFMADDSUB132PDZ256mbk, + VFMADDSUB132PDZ256mbkz, + VFMADDSUB132PDZ256mk, + VFMADDSUB132PDZ256mkz, + VFMADDSUB132PDZ256r, + VFMADDSUB132PDZ256rk, + VFMADDSUB132PDZ256rkz, + VFMADDSUB132PDZm, + VFMADDSUB132PDZmb, + VFMADDSUB132PDZmbk, + VFMADDSUB132PDZmbkz, + VFMADDSUB132PDZmk, + VFMADDSUB132PDZmkz, + VFMADDSUB132PDZr, + VFMADDSUB132PDZrb, + VFMADDSUB132PDZrbk, + VFMADDSUB132PDZrbkz, + VFMADDSUB132PDZrk, + VFMADDSUB132PDZrkz, + VFMADDSUB132PDm, + VFMADDSUB132PDr, + VFMADDSUB132PHZ128m, + VFMADDSUB132PHZ128mb, + VFMADDSUB132PHZ128mbk, + VFMADDSUB132PHZ128mbkz, + VFMADDSUB132PHZ128mk, + VFMADDSUB132PHZ128mkz, + VFMADDSUB132PHZ128r, + VFMADDSUB132PHZ128rk, + VFMADDSUB132PHZ128rkz, + VFMADDSUB132PHZ256m, + VFMADDSUB132PHZ256mb, + VFMADDSUB132PHZ256mbk, + VFMADDSUB132PHZ256mbkz, + VFMADDSUB132PHZ256mk, + VFMADDSUB132PHZ256mkz, + VFMADDSUB132PHZ256r, + VFMADDSUB132PHZ256rk, + VFMADDSUB132PHZ256rkz, + VFMADDSUB132PHZm, + VFMADDSUB132PHZmb, + VFMADDSUB132PHZmbk, + VFMADDSUB132PHZmbkz, + VFMADDSUB132PHZmk, + VFMADDSUB132PHZmkz, + VFMADDSUB132PHZr, + VFMADDSUB132PHZrb, + VFMADDSUB132PHZrbk, + VFMADDSUB132PHZrbkz, + VFMADDSUB132PHZrk, + VFMADDSUB132PHZrkz, + VFMADDSUB132PSYm, + VFMADDSUB132PSYr, + VFMADDSUB132PSZ128m, + VFMADDSUB132PSZ128mb, + VFMADDSUB132PSZ128mbk, + VFMADDSUB132PSZ128mbkz, + VFMADDSUB132PSZ128mk, + VFMADDSUB132PSZ128mkz, + VFMADDSUB132PSZ128r, + VFMADDSUB132PSZ128rk, + VFMADDSUB132PSZ128rkz, + VFMADDSUB132PSZ256m, + VFMADDSUB132PSZ256mb, + VFMADDSUB132PSZ256mbk, + VFMADDSUB132PSZ256mbkz, + VFMADDSUB132PSZ256mk, + VFMADDSUB132PSZ256mkz, + VFMADDSUB132PSZ256r, + VFMADDSUB132PSZ256rk, + VFMADDSUB132PSZ256rkz, + VFMADDSUB132PSZm, + VFMADDSUB132PSZmb, + VFMADDSUB132PSZmbk, + VFMADDSUB132PSZmbkz, + VFMADDSUB132PSZmk, + VFMADDSUB132PSZmkz, + VFMADDSUB132PSZr, + VFMADDSUB132PSZrb, + VFMADDSUB132PSZrbk, + VFMADDSUB132PSZrbkz, + VFMADDSUB132PSZrk, + VFMADDSUB132PSZrkz, + VFMADDSUB132PSm, + VFMADDSUB132PSr, + VFMADDSUB213PDYm, + VFMADDSUB213PDYr, + VFMADDSUB213PDZ128m, + VFMADDSUB213PDZ128mb, + VFMADDSUB213PDZ128mbk, + VFMADDSUB213PDZ128mbkz, + VFMADDSUB213PDZ128mk, + VFMADDSUB213PDZ128mkz, + VFMADDSUB213PDZ128r, + VFMADDSUB213PDZ128rk, + VFMADDSUB213PDZ128rkz, + VFMADDSUB213PDZ256m, + VFMADDSUB213PDZ256mb, + VFMADDSUB213PDZ256mbk, + VFMADDSUB213PDZ256mbkz, + VFMADDSUB213PDZ256mk, + VFMADDSUB213PDZ256mkz, + VFMADDSUB213PDZ256r, + VFMADDSUB213PDZ256rk, + VFMADDSUB213PDZ256rkz, + VFMADDSUB213PDZm, + VFMADDSUB213PDZmb, + VFMADDSUB213PDZmbk, + VFMADDSUB213PDZmbkz, + VFMADDSUB213PDZmk, + VFMADDSUB213PDZmkz, + VFMADDSUB213PDZr, + VFMADDSUB213PDZrb, + VFMADDSUB213PDZrbk, + VFMADDSUB213PDZrbkz, + VFMADDSUB213PDZrk, + VFMADDSUB213PDZrkz, + VFMADDSUB213PDm, + VFMADDSUB213PDr, + VFMADDSUB213PHZ128m, + VFMADDSUB213PHZ128mb, + VFMADDSUB213PHZ128mbk, + VFMADDSUB213PHZ128mbkz, + VFMADDSUB213PHZ128mk, + VFMADDSUB213PHZ128mkz, + VFMADDSUB213PHZ128r, + VFMADDSUB213PHZ128rk, + VFMADDSUB213PHZ128rkz, + VFMADDSUB213PHZ256m, + VFMADDSUB213PHZ256mb, + VFMADDSUB213PHZ256mbk, + VFMADDSUB213PHZ256mbkz, + VFMADDSUB213PHZ256mk, + VFMADDSUB213PHZ256mkz, + VFMADDSUB213PHZ256r, + VFMADDSUB213PHZ256rk, + VFMADDSUB213PHZ256rkz, + VFMADDSUB213PHZm, + VFMADDSUB213PHZmb, + VFMADDSUB213PHZmbk, + VFMADDSUB213PHZmbkz, + VFMADDSUB213PHZmk, + VFMADDSUB213PHZmkz, + VFMADDSUB213PHZr, + VFMADDSUB213PHZrb, + VFMADDSUB213PHZrbk, + VFMADDSUB213PHZrbkz, + VFMADDSUB213PHZrk, + VFMADDSUB213PHZrkz, + VFMADDSUB213PSYm, + VFMADDSUB213PSYr, + VFMADDSUB213PSZ128m, + VFMADDSUB213PSZ128mb, + VFMADDSUB213PSZ128mbk, + VFMADDSUB213PSZ128mbkz, + VFMADDSUB213PSZ128mk, + VFMADDSUB213PSZ128mkz, + VFMADDSUB213PSZ128r, + VFMADDSUB213PSZ128rk, + VFMADDSUB213PSZ128rkz, + VFMADDSUB213PSZ256m, + VFMADDSUB213PSZ256mb, + VFMADDSUB213PSZ256mbk, + VFMADDSUB213PSZ256mbkz, + VFMADDSUB213PSZ256mk, + VFMADDSUB213PSZ256mkz, + VFMADDSUB213PSZ256r, + VFMADDSUB213PSZ256rk, + VFMADDSUB213PSZ256rkz, + VFMADDSUB213PSZm, + VFMADDSUB213PSZmb, + VFMADDSUB213PSZmbk, + VFMADDSUB213PSZmbkz, + VFMADDSUB213PSZmk, + VFMADDSUB213PSZmkz, + VFMADDSUB213PSZr, + VFMADDSUB213PSZrb, + VFMADDSUB213PSZrbk, + VFMADDSUB213PSZrbkz, + VFMADDSUB213PSZrk, + VFMADDSUB213PSZrkz, + VFMADDSUB213PSm, + VFMADDSUB213PSr, + VFMADDSUB231PDYm, + VFMADDSUB231PDYr, + VFMADDSUB231PDZ128m, + VFMADDSUB231PDZ128mb, + VFMADDSUB231PDZ128mbk, + VFMADDSUB231PDZ128mbkz, + VFMADDSUB231PDZ128mk, + VFMADDSUB231PDZ128mkz, + VFMADDSUB231PDZ128r, + VFMADDSUB231PDZ128rk, + VFMADDSUB231PDZ128rkz, + VFMADDSUB231PDZ256m, + VFMADDSUB231PDZ256mb, + VFMADDSUB231PDZ256mbk, + VFMADDSUB231PDZ256mbkz, + VFMADDSUB231PDZ256mk, + VFMADDSUB231PDZ256mkz, + VFMADDSUB231PDZ256r, + VFMADDSUB231PDZ256rk, + VFMADDSUB231PDZ256rkz, + VFMADDSUB231PDZm, + VFMADDSUB231PDZmb, + VFMADDSUB231PDZmbk, + VFMADDSUB231PDZmbkz, + VFMADDSUB231PDZmk, + VFMADDSUB231PDZmkz, + VFMADDSUB231PDZr, + VFMADDSUB231PDZrb, + VFMADDSUB231PDZrbk, + VFMADDSUB231PDZrbkz, + VFMADDSUB231PDZrk, + VFMADDSUB231PDZrkz, + VFMADDSUB231PDm, + VFMADDSUB231PDr, + VFMADDSUB231PHZ128m, + VFMADDSUB231PHZ128mb, + VFMADDSUB231PHZ128mbk, + VFMADDSUB231PHZ128mbkz, + VFMADDSUB231PHZ128mk, + VFMADDSUB231PHZ128mkz, + VFMADDSUB231PHZ128r, + VFMADDSUB231PHZ128rk, + VFMADDSUB231PHZ128rkz, + VFMADDSUB231PHZ256m, + VFMADDSUB231PHZ256mb, + VFMADDSUB231PHZ256mbk, + VFMADDSUB231PHZ256mbkz, + VFMADDSUB231PHZ256mk, + VFMADDSUB231PHZ256mkz, + VFMADDSUB231PHZ256r, + VFMADDSUB231PHZ256rk, + VFMADDSUB231PHZ256rkz, + VFMADDSUB231PHZm, + VFMADDSUB231PHZmb, + VFMADDSUB231PHZmbk, + VFMADDSUB231PHZmbkz, + VFMADDSUB231PHZmk, + VFMADDSUB231PHZmkz, + VFMADDSUB231PHZr, + VFMADDSUB231PHZrb, + VFMADDSUB231PHZrbk, + VFMADDSUB231PHZrbkz, + VFMADDSUB231PHZrk, + VFMADDSUB231PHZrkz, + VFMADDSUB231PSYm, + VFMADDSUB231PSYr, + VFMADDSUB231PSZ128m, + VFMADDSUB231PSZ128mb, + VFMADDSUB231PSZ128mbk, + VFMADDSUB231PSZ128mbkz, + VFMADDSUB231PSZ128mk, + VFMADDSUB231PSZ128mkz, + VFMADDSUB231PSZ128r, + VFMADDSUB231PSZ128rk, + VFMADDSUB231PSZ128rkz, + VFMADDSUB231PSZ256m, + VFMADDSUB231PSZ256mb, + VFMADDSUB231PSZ256mbk, + VFMADDSUB231PSZ256mbkz, + VFMADDSUB231PSZ256mk, + VFMADDSUB231PSZ256mkz, + VFMADDSUB231PSZ256r, + VFMADDSUB231PSZ256rk, + VFMADDSUB231PSZ256rkz, + VFMADDSUB231PSZm, + VFMADDSUB231PSZmb, + VFMADDSUB231PSZmbk, + VFMADDSUB231PSZmbkz, + VFMADDSUB231PSZmk, + VFMADDSUB231PSZmkz, + VFMADDSUB231PSZr, + VFMADDSUB231PSZrb, + VFMADDSUB231PSZrbk, + VFMADDSUB231PSZrbkz, + VFMADDSUB231PSZrk, + VFMADDSUB231PSZrkz, + VFMADDSUB231PSm, + VFMADDSUB231PSr, + VFMADDSUBPD4Ymr, + VFMADDSUBPD4Yrm, + VFMADDSUBPD4Yrr, + VFMADDSUBPD4Yrr_REV, + VFMADDSUBPD4mr, + VFMADDSUBPD4rm, + VFMADDSUBPD4rr, + VFMADDSUBPD4rr_REV, + VFMADDSUBPS4Ymr, + VFMADDSUBPS4Yrm, + VFMADDSUBPS4Yrr, + VFMADDSUBPS4Yrr_REV, + VFMADDSUBPS4mr, + VFMADDSUBPS4rm, + VFMADDSUBPS4rr, + VFMADDSUBPS4rr_REV, + VFMSUB132BF16Z128m, + VFMSUB132BF16Z128mb, + VFMSUB132BF16Z128mbk, + VFMSUB132BF16Z128mbkz, + VFMSUB132BF16Z128mk, + VFMSUB132BF16Z128mkz, + VFMSUB132BF16Z128r, + VFMSUB132BF16Z128rk, + VFMSUB132BF16Z128rkz, + VFMSUB132BF16Z256m, + VFMSUB132BF16Z256mb, + VFMSUB132BF16Z256mbk, + VFMSUB132BF16Z256mbkz, + VFMSUB132BF16Z256mk, + VFMSUB132BF16Z256mkz, + VFMSUB132BF16Z256r, + VFMSUB132BF16Z256rk, + VFMSUB132BF16Z256rkz, + VFMSUB132BF16Zm, + VFMSUB132BF16Zmb, + VFMSUB132BF16Zmbk, + VFMSUB132BF16Zmbkz, + VFMSUB132BF16Zmk, + VFMSUB132BF16Zmkz, + VFMSUB132BF16Zr, + VFMSUB132BF16Zrk, + VFMSUB132BF16Zrkz, + VFMSUB132PDYm, + VFMSUB132PDYr, + VFMSUB132PDZ128m, + VFMSUB132PDZ128mb, + VFMSUB132PDZ128mbk, + VFMSUB132PDZ128mbkz, + VFMSUB132PDZ128mk, + VFMSUB132PDZ128mkz, + VFMSUB132PDZ128r, + VFMSUB132PDZ128rk, + VFMSUB132PDZ128rkz, + VFMSUB132PDZ256m, + VFMSUB132PDZ256mb, + VFMSUB132PDZ256mbk, + VFMSUB132PDZ256mbkz, + VFMSUB132PDZ256mk, + VFMSUB132PDZ256mkz, + VFMSUB132PDZ256r, + VFMSUB132PDZ256rk, + VFMSUB132PDZ256rkz, + VFMSUB132PDZm, + VFMSUB132PDZmb, + VFMSUB132PDZmbk, + VFMSUB132PDZmbkz, + VFMSUB132PDZmk, + VFMSUB132PDZmkz, + VFMSUB132PDZr, + VFMSUB132PDZrb, + VFMSUB132PDZrbk, + VFMSUB132PDZrbkz, + VFMSUB132PDZrk, + VFMSUB132PDZrkz, + VFMSUB132PDm, + VFMSUB132PDr, + VFMSUB132PHZ128m, + VFMSUB132PHZ128mb, + VFMSUB132PHZ128mbk, + VFMSUB132PHZ128mbkz, + VFMSUB132PHZ128mk, + VFMSUB132PHZ128mkz, + VFMSUB132PHZ128r, + VFMSUB132PHZ128rk, + VFMSUB132PHZ128rkz, + VFMSUB132PHZ256m, + VFMSUB132PHZ256mb, + VFMSUB132PHZ256mbk, + VFMSUB132PHZ256mbkz, + VFMSUB132PHZ256mk, + VFMSUB132PHZ256mkz, + VFMSUB132PHZ256r, + VFMSUB132PHZ256rk, + VFMSUB132PHZ256rkz, + VFMSUB132PHZm, + VFMSUB132PHZmb, + VFMSUB132PHZmbk, + VFMSUB132PHZmbkz, + VFMSUB132PHZmk, + VFMSUB132PHZmkz, + VFMSUB132PHZr, + VFMSUB132PHZrb, + VFMSUB132PHZrbk, + VFMSUB132PHZrbkz, + VFMSUB132PHZrk, + VFMSUB132PHZrkz, + VFMSUB132PSYm, + VFMSUB132PSYr, + VFMSUB132PSZ128m, + VFMSUB132PSZ128mb, + VFMSUB132PSZ128mbk, + VFMSUB132PSZ128mbkz, + VFMSUB132PSZ128mk, + VFMSUB132PSZ128mkz, + VFMSUB132PSZ128r, + VFMSUB132PSZ128rk, + VFMSUB132PSZ128rkz, + VFMSUB132PSZ256m, + VFMSUB132PSZ256mb, + VFMSUB132PSZ256mbk, + VFMSUB132PSZ256mbkz, + VFMSUB132PSZ256mk, + VFMSUB132PSZ256mkz, + VFMSUB132PSZ256r, + VFMSUB132PSZ256rk, + VFMSUB132PSZ256rkz, + VFMSUB132PSZm, + VFMSUB132PSZmb, + VFMSUB132PSZmbk, + VFMSUB132PSZmbkz, + VFMSUB132PSZmk, + VFMSUB132PSZmkz, + VFMSUB132PSZr, + VFMSUB132PSZrb, + VFMSUB132PSZrbk, + VFMSUB132PSZrbkz, + VFMSUB132PSZrk, + VFMSUB132PSZrkz, + VFMSUB132PSm, + VFMSUB132PSr, + VFMSUB132SDZm, + VFMSUB132SDZm_Int, + VFMSUB132SDZmk_Int, + VFMSUB132SDZmkz_Int, + VFMSUB132SDZr, + VFMSUB132SDZr_Int, + VFMSUB132SDZrb, + VFMSUB132SDZrb_Int, + VFMSUB132SDZrbk_Int, + VFMSUB132SDZrbkz_Int, + VFMSUB132SDZrk_Int, + VFMSUB132SDZrkz_Int, + VFMSUB132SDm, + VFMSUB132SDm_Int, + VFMSUB132SDr, + VFMSUB132SDr_Int, + VFMSUB132SHZm, + VFMSUB132SHZm_Int, + VFMSUB132SHZmk_Int, + VFMSUB132SHZmkz_Int, + VFMSUB132SHZr, + VFMSUB132SHZr_Int, + VFMSUB132SHZrb, + VFMSUB132SHZrb_Int, + VFMSUB132SHZrbk_Int, + VFMSUB132SHZrbkz_Int, + VFMSUB132SHZrk_Int, + VFMSUB132SHZrkz_Int, + VFMSUB132SSZm, + VFMSUB132SSZm_Int, + VFMSUB132SSZmk_Int, + VFMSUB132SSZmkz_Int, + VFMSUB132SSZr, + VFMSUB132SSZr_Int, + VFMSUB132SSZrb, + VFMSUB132SSZrb_Int, + VFMSUB132SSZrbk_Int, + VFMSUB132SSZrbkz_Int, + VFMSUB132SSZrk_Int, + VFMSUB132SSZrkz_Int, + VFMSUB132SSm, + VFMSUB132SSm_Int, + VFMSUB132SSr, + VFMSUB132SSr_Int, + VFMSUB213BF16Z128m, + VFMSUB213BF16Z128mb, + VFMSUB213BF16Z128mbk, + VFMSUB213BF16Z128mbkz, + VFMSUB213BF16Z128mk, + VFMSUB213BF16Z128mkz, + VFMSUB213BF16Z128r, + VFMSUB213BF16Z128rk, + VFMSUB213BF16Z128rkz, + VFMSUB213BF16Z256m, + VFMSUB213BF16Z256mb, + VFMSUB213BF16Z256mbk, + VFMSUB213BF16Z256mbkz, + VFMSUB213BF16Z256mk, + VFMSUB213BF16Z256mkz, + VFMSUB213BF16Z256r, + VFMSUB213BF16Z256rk, + VFMSUB213BF16Z256rkz, + VFMSUB213BF16Zm, + VFMSUB213BF16Zmb, + VFMSUB213BF16Zmbk, + VFMSUB213BF16Zmbkz, + VFMSUB213BF16Zmk, + VFMSUB213BF16Zmkz, + VFMSUB213BF16Zr, + VFMSUB213BF16Zrk, + VFMSUB213BF16Zrkz, + VFMSUB213PDYm, + VFMSUB213PDYr, + VFMSUB213PDZ128m, + VFMSUB213PDZ128mb, + VFMSUB213PDZ128mbk, + VFMSUB213PDZ128mbkz, + VFMSUB213PDZ128mk, + VFMSUB213PDZ128mkz, + VFMSUB213PDZ128r, + VFMSUB213PDZ128rk, + VFMSUB213PDZ128rkz, + VFMSUB213PDZ256m, + VFMSUB213PDZ256mb, + VFMSUB213PDZ256mbk, + VFMSUB213PDZ256mbkz, + VFMSUB213PDZ256mk, + VFMSUB213PDZ256mkz, + VFMSUB213PDZ256r, + VFMSUB213PDZ256rk, + VFMSUB213PDZ256rkz, + VFMSUB213PDZm, + VFMSUB213PDZmb, + VFMSUB213PDZmbk, + VFMSUB213PDZmbkz, + VFMSUB213PDZmk, + VFMSUB213PDZmkz, + VFMSUB213PDZr, + VFMSUB213PDZrb, + VFMSUB213PDZrbk, + VFMSUB213PDZrbkz, + VFMSUB213PDZrk, + VFMSUB213PDZrkz, + VFMSUB213PDm, + VFMSUB213PDr, + VFMSUB213PHZ128m, + VFMSUB213PHZ128mb, + VFMSUB213PHZ128mbk, + VFMSUB213PHZ128mbkz, + VFMSUB213PHZ128mk, + VFMSUB213PHZ128mkz, + VFMSUB213PHZ128r, + VFMSUB213PHZ128rk, + VFMSUB213PHZ128rkz, + VFMSUB213PHZ256m, + VFMSUB213PHZ256mb, + VFMSUB213PHZ256mbk, + VFMSUB213PHZ256mbkz, + VFMSUB213PHZ256mk, + VFMSUB213PHZ256mkz, + VFMSUB213PHZ256r, + VFMSUB213PHZ256rk, + VFMSUB213PHZ256rkz, + VFMSUB213PHZm, + VFMSUB213PHZmb, + VFMSUB213PHZmbk, + VFMSUB213PHZmbkz, + VFMSUB213PHZmk, + VFMSUB213PHZmkz, + VFMSUB213PHZr, + VFMSUB213PHZrb, + VFMSUB213PHZrbk, + VFMSUB213PHZrbkz, + VFMSUB213PHZrk, + VFMSUB213PHZrkz, + VFMSUB213PSYm, + VFMSUB213PSYr, + VFMSUB213PSZ128m, + VFMSUB213PSZ128mb, + VFMSUB213PSZ128mbk, + VFMSUB213PSZ128mbkz, + VFMSUB213PSZ128mk, + VFMSUB213PSZ128mkz, + VFMSUB213PSZ128r, + VFMSUB213PSZ128rk, + VFMSUB213PSZ128rkz, + VFMSUB213PSZ256m, + VFMSUB213PSZ256mb, + VFMSUB213PSZ256mbk, + VFMSUB213PSZ256mbkz, + VFMSUB213PSZ256mk, + VFMSUB213PSZ256mkz, + VFMSUB213PSZ256r, + VFMSUB213PSZ256rk, + VFMSUB213PSZ256rkz, + VFMSUB213PSZm, + VFMSUB213PSZmb, + VFMSUB213PSZmbk, + VFMSUB213PSZmbkz, + VFMSUB213PSZmk, + VFMSUB213PSZmkz, + VFMSUB213PSZr, + VFMSUB213PSZrb, + VFMSUB213PSZrbk, + VFMSUB213PSZrbkz, + VFMSUB213PSZrk, + VFMSUB213PSZrkz, + VFMSUB213PSm, + VFMSUB213PSr, + VFMSUB213SDZm, + VFMSUB213SDZm_Int, + VFMSUB213SDZmk_Int, + VFMSUB213SDZmkz_Int, + VFMSUB213SDZr, + VFMSUB213SDZr_Int, + VFMSUB213SDZrb, + VFMSUB213SDZrb_Int, + VFMSUB213SDZrbk_Int, + VFMSUB213SDZrbkz_Int, + VFMSUB213SDZrk_Int, + VFMSUB213SDZrkz_Int, + VFMSUB213SDm, + VFMSUB213SDm_Int, + VFMSUB213SDr, + VFMSUB213SDr_Int, + VFMSUB213SHZm, + VFMSUB213SHZm_Int, + VFMSUB213SHZmk_Int, + VFMSUB213SHZmkz_Int, + VFMSUB213SHZr, + VFMSUB213SHZr_Int, + VFMSUB213SHZrb, + VFMSUB213SHZrb_Int, + VFMSUB213SHZrbk_Int, + VFMSUB213SHZrbkz_Int, + VFMSUB213SHZrk_Int, + VFMSUB213SHZrkz_Int, + VFMSUB213SSZm, + VFMSUB213SSZm_Int, + VFMSUB213SSZmk_Int, + VFMSUB213SSZmkz_Int, + VFMSUB213SSZr, + VFMSUB213SSZr_Int, + VFMSUB213SSZrb, + VFMSUB213SSZrb_Int, + VFMSUB213SSZrbk_Int, + VFMSUB213SSZrbkz_Int, + VFMSUB213SSZrk_Int, + VFMSUB213SSZrkz_Int, + VFMSUB213SSm, + VFMSUB213SSm_Int, + VFMSUB213SSr, + VFMSUB213SSr_Int, + VFMSUB231BF16Z128m, + VFMSUB231BF16Z128mb, + VFMSUB231BF16Z128mbk, + VFMSUB231BF16Z128mbkz, + VFMSUB231BF16Z128mk, + VFMSUB231BF16Z128mkz, + VFMSUB231BF16Z128r, + VFMSUB231BF16Z128rk, + VFMSUB231BF16Z128rkz, + VFMSUB231BF16Z256m, + VFMSUB231BF16Z256mb, + VFMSUB231BF16Z256mbk, + VFMSUB231BF16Z256mbkz, + VFMSUB231BF16Z256mk, + VFMSUB231BF16Z256mkz, + VFMSUB231BF16Z256r, + VFMSUB231BF16Z256rk, + VFMSUB231BF16Z256rkz, + VFMSUB231BF16Zm, + VFMSUB231BF16Zmb, + VFMSUB231BF16Zmbk, + VFMSUB231BF16Zmbkz, + VFMSUB231BF16Zmk, + VFMSUB231BF16Zmkz, + VFMSUB231BF16Zr, + VFMSUB231BF16Zrk, + VFMSUB231BF16Zrkz, + VFMSUB231PDYm, + VFMSUB231PDYr, + VFMSUB231PDZ128m, + VFMSUB231PDZ128mb, + VFMSUB231PDZ128mbk, + VFMSUB231PDZ128mbkz, + VFMSUB231PDZ128mk, + VFMSUB231PDZ128mkz, + VFMSUB231PDZ128r, + VFMSUB231PDZ128rk, + VFMSUB231PDZ128rkz, + VFMSUB231PDZ256m, + VFMSUB231PDZ256mb, + VFMSUB231PDZ256mbk, + VFMSUB231PDZ256mbkz, + VFMSUB231PDZ256mk, + VFMSUB231PDZ256mkz, + VFMSUB231PDZ256r, + VFMSUB231PDZ256rk, + VFMSUB231PDZ256rkz, + VFMSUB231PDZm, + VFMSUB231PDZmb, + VFMSUB231PDZmbk, + VFMSUB231PDZmbkz, + VFMSUB231PDZmk, + VFMSUB231PDZmkz, + VFMSUB231PDZr, + VFMSUB231PDZrb, + VFMSUB231PDZrbk, + VFMSUB231PDZrbkz, + VFMSUB231PDZrk, + VFMSUB231PDZrkz, + VFMSUB231PDm, + VFMSUB231PDr, + VFMSUB231PHZ128m, + VFMSUB231PHZ128mb, + VFMSUB231PHZ128mbk, + VFMSUB231PHZ128mbkz, + VFMSUB231PHZ128mk, + VFMSUB231PHZ128mkz, + VFMSUB231PHZ128r, + VFMSUB231PHZ128rk, + VFMSUB231PHZ128rkz, + VFMSUB231PHZ256m, + VFMSUB231PHZ256mb, + VFMSUB231PHZ256mbk, + VFMSUB231PHZ256mbkz, + VFMSUB231PHZ256mk, + VFMSUB231PHZ256mkz, + VFMSUB231PHZ256r, + VFMSUB231PHZ256rk, + VFMSUB231PHZ256rkz, + VFMSUB231PHZm, + VFMSUB231PHZmb, + VFMSUB231PHZmbk, + VFMSUB231PHZmbkz, + VFMSUB231PHZmk, + VFMSUB231PHZmkz, + VFMSUB231PHZr, + VFMSUB231PHZrb, + VFMSUB231PHZrbk, + VFMSUB231PHZrbkz, + VFMSUB231PHZrk, + VFMSUB231PHZrkz, + VFMSUB231PSYm, + VFMSUB231PSYr, + VFMSUB231PSZ128m, + VFMSUB231PSZ128mb, + VFMSUB231PSZ128mbk, + VFMSUB231PSZ128mbkz, + VFMSUB231PSZ128mk, + VFMSUB231PSZ128mkz, + VFMSUB231PSZ128r, + VFMSUB231PSZ128rk, + VFMSUB231PSZ128rkz, + VFMSUB231PSZ256m, + VFMSUB231PSZ256mb, + VFMSUB231PSZ256mbk, + VFMSUB231PSZ256mbkz, + VFMSUB231PSZ256mk, + VFMSUB231PSZ256mkz, + VFMSUB231PSZ256r, + VFMSUB231PSZ256rk, + VFMSUB231PSZ256rkz, + VFMSUB231PSZm, + VFMSUB231PSZmb, + VFMSUB231PSZmbk, + VFMSUB231PSZmbkz, + VFMSUB231PSZmk, + VFMSUB231PSZmkz, + VFMSUB231PSZr, + VFMSUB231PSZrb, + VFMSUB231PSZrbk, + VFMSUB231PSZrbkz, + VFMSUB231PSZrk, + VFMSUB231PSZrkz, + VFMSUB231PSm, + VFMSUB231PSr, + VFMSUB231SDZm, + VFMSUB231SDZm_Int, + VFMSUB231SDZmk_Int, + VFMSUB231SDZmkz_Int, + VFMSUB231SDZr, + VFMSUB231SDZr_Int, + VFMSUB231SDZrb, + VFMSUB231SDZrb_Int, + VFMSUB231SDZrbk_Int, + VFMSUB231SDZrbkz_Int, + VFMSUB231SDZrk_Int, + VFMSUB231SDZrkz_Int, + VFMSUB231SDm, + VFMSUB231SDm_Int, + VFMSUB231SDr, + VFMSUB231SDr_Int, + VFMSUB231SHZm, + VFMSUB231SHZm_Int, + VFMSUB231SHZmk_Int, + VFMSUB231SHZmkz_Int, + VFMSUB231SHZr, + VFMSUB231SHZr_Int, + VFMSUB231SHZrb, + VFMSUB231SHZrb_Int, + VFMSUB231SHZrbk_Int, + VFMSUB231SHZrbkz_Int, + VFMSUB231SHZrk_Int, + VFMSUB231SHZrkz_Int, + VFMSUB231SSZm, + VFMSUB231SSZm_Int, + VFMSUB231SSZmk_Int, + VFMSUB231SSZmkz_Int, + VFMSUB231SSZr, + VFMSUB231SSZr_Int, + VFMSUB231SSZrb, + VFMSUB231SSZrb_Int, + VFMSUB231SSZrbk_Int, + VFMSUB231SSZrbkz_Int, + VFMSUB231SSZrk_Int, + VFMSUB231SSZrkz_Int, + VFMSUB231SSm, + VFMSUB231SSm_Int, + VFMSUB231SSr, + VFMSUB231SSr_Int, + VFMSUBADD132PDYm, + VFMSUBADD132PDYr, + VFMSUBADD132PDZ128m, + VFMSUBADD132PDZ128mb, + VFMSUBADD132PDZ128mbk, + VFMSUBADD132PDZ128mbkz, + VFMSUBADD132PDZ128mk, + VFMSUBADD132PDZ128mkz, + VFMSUBADD132PDZ128r, + VFMSUBADD132PDZ128rk, + VFMSUBADD132PDZ128rkz, + VFMSUBADD132PDZ256m, + VFMSUBADD132PDZ256mb, + VFMSUBADD132PDZ256mbk, + VFMSUBADD132PDZ256mbkz, + VFMSUBADD132PDZ256mk, + VFMSUBADD132PDZ256mkz, + VFMSUBADD132PDZ256r, + VFMSUBADD132PDZ256rk, + VFMSUBADD132PDZ256rkz, + VFMSUBADD132PDZm, + VFMSUBADD132PDZmb, + VFMSUBADD132PDZmbk, + VFMSUBADD132PDZmbkz, + VFMSUBADD132PDZmk, + VFMSUBADD132PDZmkz, + VFMSUBADD132PDZr, + VFMSUBADD132PDZrb, + VFMSUBADD132PDZrbk, + VFMSUBADD132PDZrbkz, + VFMSUBADD132PDZrk, + VFMSUBADD132PDZrkz, + VFMSUBADD132PDm, + VFMSUBADD132PDr, + VFMSUBADD132PHZ128m, + VFMSUBADD132PHZ128mb, + VFMSUBADD132PHZ128mbk, + VFMSUBADD132PHZ128mbkz, + VFMSUBADD132PHZ128mk, + VFMSUBADD132PHZ128mkz, + VFMSUBADD132PHZ128r, + VFMSUBADD132PHZ128rk, + VFMSUBADD132PHZ128rkz, + VFMSUBADD132PHZ256m, + VFMSUBADD132PHZ256mb, + VFMSUBADD132PHZ256mbk, + VFMSUBADD132PHZ256mbkz, + VFMSUBADD132PHZ256mk, + VFMSUBADD132PHZ256mkz, + VFMSUBADD132PHZ256r, + VFMSUBADD132PHZ256rk, + VFMSUBADD132PHZ256rkz, + VFMSUBADD132PHZm, + VFMSUBADD132PHZmb, + VFMSUBADD132PHZmbk, + VFMSUBADD132PHZmbkz, + VFMSUBADD132PHZmk, + VFMSUBADD132PHZmkz, + VFMSUBADD132PHZr, + VFMSUBADD132PHZrb, + VFMSUBADD132PHZrbk, + VFMSUBADD132PHZrbkz, + VFMSUBADD132PHZrk, + VFMSUBADD132PHZrkz, + VFMSUBADD132PSYm, + VFMSUBADD132PSYr, + VFMSUBADD132PSZ128m, + VFMSUBADD132PSZ128mb, + VFMSUBADD132PSZ128mbk, + VFMSUBADD132PSZ128mbkz, + VFMSUBADD132PSZ128mk, + VFMSUBADD132PSZ128mkz, + VFMSUBADD132PSZ128r, + VFMSUBADD132PSZ128rk, + VFMSUBADD132PSZ128rkz, + VFMSUBADD132PSZ256m, + VFMSUBADD132PSZ256mb, + VFMSUBADD132PSZ256mbk, + VFMSUBADD132PSZ256mbkz, + VFMSUBADD132PSZ256mk, + VFMSUBADD132PSZ256mkz, + VFMSUBADD132PSZ256r, + VFMSUBADD132PSZ256rk, + VFMSUBADD132PSZ256rkz, + VFMSUBADD132PSZm, + VFMSUBADD132PSZmb, + VFMSUBADD132PSZmbk, + VFMSUBADD132PSZmbkz, + VFMSUBADD132PSZmk, + VFMSUBADD132PSZmkz, + VFMSUBADD132PSZr, + VFMSUBADD132PSZrb, + VFMSUBADD132PSZrbk, + VFMSUBADD132PSZrbkz, + VFMSUBADD132PSZrk, + VFMSUBADD132PSZrkz, + VFMSUBADD132PSm, + VFMSUBADD132PSr, + VFMSUBADD213PDYm, + VFMSUBADD213PDYr, + VFMSUBADD213PDZ128m, + VFMSUBADD213PDZ128mb, + VFMSUBADD213PDZ128mbk, + VFMSUBADD213PDZ128mbkz, + VFMSUBADD213PDZ128mk, + VFMSUBADD213PDZ128mkz, + VFMSUBADD213PDZ128r, + VFMSUBADD213PDZ128rk, + VFMSUBADD213PDZ128rkz, + VFMSUBADD213PDZ256m, + VFMSUBADD213PDZ256mb, + VFMSUBADD213PDZ256mbk, + VFMSUBADD213PDZ256mbkz, + VFMSUBADD213PDZ256mk, + VFMSUBADD213PDZ256mkz, + VFMSUBADD213PDZ256r, + VFMSUBADD213PDZ256rk, + VFMSUBADD213PDZ256rkz, + VFMSUBADD213PDZm, + VFMSUBADD213PDZmb, + VFMSUBADD213PDZmbk, + VFMSUBADD213PDZmbkz, + VFMSUBADD213PDZmk, + VFMSUBADD213PDZmkz, + VFMSUBADD213PDZr, + VFMSUBADD213PDZrb, + VFMSUBADD213PDZrbk, + VFMSUBADD213PDZrbkz, + VFMSUBADD213PDZrk, + VFMSUBADD213PDZrkz, + VFMSUBADD213PDm, + VFMSUBADD213PDr, + VFMSUBADD213PHZ128m, + VFMSUBADD213PHZ128mb, + VFMSUBADD213PHZ128mbk, + VFMSUBADD213PHZ128mbkz, + VFMSUBADD213PHZ128mk, + VFMSUBADD213PHZ128mkz, + VFMSUBADD213PHZ128r, + VFMSUBADD213PHZ128rk, + VFMSUBADD213PHZ128rkz, + VFMSUBADD213PHZ256m, + VFMSUBADD213PHZ256mb, + VFMSUBADD213PHZ256mbk, + VFMSUBADD213PHZ256mbkz, + VFMSUBADD213PHZ256mk, + VFMSUBADD213PHZ256mkz, + VFMSUBADD213PHZ256r, + VFMSUBADD213PHZ256rk, + VFMSUBADD213PHZ256rkz, + VFMSUBADD213PHZm, + VFMSUBADD213PHZmb, + VFMSUBADD213PHZmbk, + VFMSUBADD213PHZmbkz, + VFMSUBADD213PHZmk, + VFMSUBADD213PHZmkz, + VFMSUBADD213PHZr, + VFMSUBADD213PHZrb, + VFMSUBADD213PHZrbk, + VFMSUBADD213PHZrbkz, + VFMSUBADD213PHZrk, + VFMSUBADD213PHZrkz, + VFMSUBADD213PSYm, + VFMSUBADD213PSYr, + VFMSUBADD213PSZ128m, + VFMSUBADD213PSZ128mb, + VFMSUBADD213PSZ128mbk, + VFMSUBADD213PSZ128mbkz, + VFMSUBADD213PSZ128mk, + VFMSUBADD213PSZ128mkz, + VFMSUBADD213PSZ128r, + VFMSUBADD213PSZ128rk, + VFMSUBADD213PSZ128rkz, + VFMSUBADD213PSZ256m, + VFMSUBADD213PSZ256mb, + VFMSUBADD213PSZ256mbk, + VFMSUBADD213PSZ256mbkz, + VFMSUBADD213PSZ256mk, + VFMSUBADD213PSZ256mkz, + VFMSUBADD213PSZ256r, + VFMSUBADD213PSZ256rk, + VFMSUBADD213PSZ256rkz, + VFMSUBADD213PSZm, + VFMSUBADD213PSZmb, + VFMSUBADD213PSZmbk, + VFMSUBADD213PSZmbkz, + VFMSUBADD213PSZmk, + VFMSUBADD213PSZmkz, + VFMSUBADD213PSZr, + VFMSUBADD213PSZrb, + VFMSUBADD213PSZrbk, + VFMSUBADD213PSZrbkz, + VFMSUBADD213PSZrk, + VFMSUBADD213PSZrkz, + VFMSUBADD213PSm, + VFMSUBADD213PSr, + VFMSUBADD231PDYm, + VFMSUBADD231PDYr, + VFMSUBADD231PDZ128m, + VFMSUBADD231PDZ128mb, + VFMSUBADD231PDZ128mbk, + VFMSUBADD231PDZ128mbkz, + VFMSUBADD231PDZ128mk, + VFMSUBADD231PDZ128mkz, + VFMSUBADD231PDZ128r, + VFMSUBADD231PDZ128rk, + VFMSUBADD231PDZ128rkz, + VFMSUBADD231PDZ256m, + VFMSUBADD231PDZ256mb, + VFMSUBADD231PDZ256mbk, + VFMSUBADD231PDZ256mbkz, + VFMSUBADD231PDZ256mk, + VFMSUBADD231PDZ256mkz, + VFMSUBADD231PDZ256r, + VFMSUBADD231PDZ256rk, + VFMSUBADD231PDZ256rkz, + VFMSUBADD231PDZm, + VFMSUBADD231PDZmb, + VFMSUBADD231PDZmbk, + VFMSUBADD231PDZmbkz, + VFMSUBADD231PDZmk, + VFMSUBADD231PDZmkz, + VFMSUBADD231PDZr, + VFMSUBADD231PDZrb, + VFMSUBADD231PDZrbk, + VFMSUBADD231PDZrbkz, + VFMSUBADD231PDZrk, + VFMSUBADD231PDZrkz, + VFMSUBADD231PDm, + VFMSUBADD231PDr, + VFMSUBADD231PHZ128m, + VFMSUBADD231PHZ128mb, + VFMSUBADD231PHZ128mbk, + VFMSUBADD231PHZ128mbkz, + VFMSUBADD231PHZ128mk, + VFMSUBADD231PHZ128mkz, + VFMSUBADD231PHZ128r, + VFMSUBADD231PHZ128rk, + VFMSUBADD231PHZ128rkz, + VFMSUBADD231PHZ256m, + VFMSUBADD231PHZ256mb, + VFMSUBADD231PHZ256mbk, + VFMSUBADD231PHZ256mbkz, + VFMSUBADD231PHZ256mk, + VFMSUBADD231PHZ256mkz, + VFMSUBADD231PHZ256r, + VFMSUBADD231PHZ256rk, + VFMSUBADD231PHZ256rkz, + VFMSUBADD231PHZm, + VFMSUBADD231PHZmb, + VFMSUBADD231PHZmbk, + VFMSUBADD231PHZmbkz, + VFMSUBADD231PHZmk, + VFMSUBADD231PHZmkz, + VFMSUBADD231PHZr, + VFMSUBADD231PHZrb, + VFMSUBADD231PHZrbk, + VFMSUBADD231PHZrbkz, + VFMSUBADD231PHZrk, + VFMSUBADD231PHZrkz, + VFMSUBADD231PSYm, + VFMSUBADD231PSYr, + VFMSUBADD231PSZ128m, + VFMSUBADD231PSZ128mb, + VFMSUBADD231PSZ128mbk, + VFMSUBADD231PSZ128mbkz, + VFMSUBADD231PSZ128mk, + VFMSUBADD231PSZ128mkz, + VFMSUBADD231PSZ128r, + VFMSUBADD231PSZ128rk, + VFMSUBADD231PSZ128rkz, + VFMSUBADD231PSZ256m, + VFMSUBADD231PSZ256mb, + VFMSUBADD231PSZ256mbk, + VFMSUBADD231PSZ256mbkz, + VFMSUBADD231PSZ256mk, + VFMSUBADD231PSZ256mkz, + VFMSUBADD231PSZ256r, + VFMSUBADD231PSZ256rk, + VFMSUBADD231PSZ256rkz, + VFMSUBADD231PSZm, + VFMSUBADD231PSZmb, + VFMSUBADD231PSZmbk, + VFMSUBADD231PSZmbkz, + VFMSUBADD231PSZmk, + VFMSUBADD231PSZmkz, + VFMSUBADD231PSZr, + VFMSUBADD231PSZrb, + VFMSUBADD231PSZrbk, + VFMSUBADD231PSZrbkz, + VFMSUBADD231PSZrk, + VFMSUBADD231PSZrkz, + VFMSUBADD231PSm, + VFMSUBADD231PSr, + VFMSUBADDPD4Ymr, + VFMSUBADDPD4Yrm, + VFMSUBADDPD4Yrr, + VFMSUBADDPD4Yrr_REV, + VFMSUBADDPD4mr, + VFMSUBADDPD4rm, + VFMSUBADDPD4rr, + VFMSUBADDPD4rr_REV, + VFMSUBADDPS4Ymr, + VFMSUBADDPS4Yrm, + VFMSUBADDPS4Yrr, + VFMSUBADDPS4Yrr_REV, + VFMSUBADDPS4mr, + VFMSUBADDPS4rm, + VFMSUBADDPS4rr, + VFMSUBADDPS4rr_REV, + VFMSUBPD4Ymr, + VFMSUBPD4Yrm, + VFMSUBPD4Yrr, + VFMSUBPD4Yrr_REV, + VFMSUBPD4mr, + VFMSUBPD4rm, + VFMSUBPD4rr, + VFMSUBPD4rr_REV, + VFMSUBPS4Ymr, + VFMSUBPS4Yrm, + VFMSUBPS4Yrr, + VFMSUBPS4Yrr_REV, + VFMSUBPS4mr, + VFMSUBPS4rm, + VFMSUBPS4rr, + VFMSUBPS4rr_REV, + VFMSUBSD4mr, + VFMSUBSD4mr_Int, + VFMSUBSD4rm, + VFMSUBSD4rm_Int, + VFMSUBSD4rr, + VFMSUBSD4rr_Int, + VFMSUBSD4rr_Int_REV, + VFMSUBSD4rr_REV, + VFMSUBSS4mr, + VFMSUBSS4mr_Int, + VFMSUBSS4rm, + VFMSUBSS4rm_Int, + VFMSUBSS4rr, + VFMSUBSS4rr_Int, + VFMSUBSS4rr_Int_REV, + VFMSUBSS4rr_REV, + VFMULCPHZ128rm, + VFMULCPHZ128rmb, + VFMULCPHZ128rmbk, + VFMULCPHZ128rmbkz, + VFMULCPHZ128rmk, + VFMULCPHZ128rmkz, + VFMULCPHZ128rr, + VFMULCPHZ128rrk, + VFMULCPHZ128rrkz, + VFMULCPHZ256rm, + VFMULCPHZ256rmb, + VFMULCPHZ256rmbk, + VFMULCPHZ256rmbkz, + VFMULCPHZ256rmk, + VFMULCPHZ256rmkz, + VFMULCPHZ256rr, + VFMULCPHZ256rrk, + VFMULCPHZ256rrkz, + VFMULCPHZrm, + VFMULCPHZrmb, + VFMULCPHZrmbk, + VFMULCPHZrmbkz, + VFMULCPHZrmk, + VFMULCPHZrmkz, + VFMULCPHZrr, + VFMULCPHZrrb, + VFMULCPHZrrbk, + VFMULCPHZrrbkz, + VFMULCPHZrrk, + VFMULCPHZrrkz, + VFMULCSHZrm, + VFMULCSHZrmk, + VFMULCSHZrmkz, + VFMULCSHZrr, + VFMULCSHZrrb, + VFMULCSHZrrbk, + VFMULCSHZrrbkz, + VFMULCSHZrrk, + VFMULCSHZrrkz, + VFNMADD132BF16Z128m, + VFNMADD132BF16Z128mb, + VFNMADD132BF16Z128mbk, + VFNMADD132BF16Z128mbkz, + VFNMADD132BF16Z128mk, + VFNMADD132BF16Z128mkz, + VFNMADD132BF16Z128r, + VFNMADD132BF16Z128rk, + VFNMADD132BF16Z128rkz, + VFNMADD132BF16Z256m, + VFNMADD132BF16Z256mb, + VFNMADD132BF16Z256mbk, + VFNMADD132BF16Z256mbkz, + VFNMADD132BF16Z256mk, + VFNMADD132BF16Z256mkz, + VFNMADD132BF16Z256r, + VFNMADD132BF16Z256rk, + VFNMADD132BF16Z256rkz, + VFNMADD132BF16Zm, + VFNMADD132BF16Zmb, + VFNMADD132BF16Zmbk, + VFNMADD132BF16Zmbkz, + VFNMADD132BF16Zmk, + VFNMADD132BF16Zmkz, + VFNMADD132BF16Zr, + VFNMADD132BF16Zrk, + VFNMADD132BF16Zrkz, + VFNMADD132PDYm, + VFNMADD132PDYr, + VFNMADD132PDZ128m, + VFNMADD132PDZ128mb, + VFNMADD132PDZ128mbk, + VFNMADD132PDZ128mbkz, + VFNMADD132PDZ128mk, + VFNMADD132PDZ128mkz, + VFNMADD132PDZ128r, + VFNMADD132PDZ128rk, + VFNMADD132PDZ128rkz, + VFNMADD132PDZ256m, + VFNMADD132PDZ256mb, + VFNMADD132PDZ256mbk, + VFNMADD132PDZ256mbkz, + VFNMADD132PDZ256mk, + VFNMADD132PDZ256mkz, + VFNMADD132PDZ256r, + VFNMADD132PDZ256rk, + VFNMADD132PDZ256rkz, + VFNMADD132PDZm, + VFNMADD132PDZmb, + VFNMADD132PDZmbk, + VFNMADD132PDZmbkz, + VFNMADD132PDZmk, + VFNMADD132PDZmkz, + VFNMADD132PDZr, + VFNMADD132PDZrb, + VFNMADD132PDZrbk, + VFNMADD132PDZrbkz, + VFNMADD132PDZrk, + VFNMADD132PDZrkz, + VFNMADD132PDm, + VFNMADD132PDr, + VFNMADD132PHZ128m, + VFNMADD132PHZ128mb, + VFNMADD132PHZ128mbk, + VFNMADD132PHZ128mbkz, + VFNMADD132PHZ128mk, + VFNMADD132PHZ128mkz, + VFNMADD132PHZ128r, + VFNMADD132PHZ128rk, + VFNMADD132PHZ128rkz, + VFNMADD132PHZ256m, + VFNMADD132PHZ256mb, + VFNMADD132PHZ256mbk, + VFNMADD132PHZ256mbkz, + VFNMADD132PHZ256mk, + VFNMADD132PHZ256mkz, + VFNMADD132PHZ256r, + VFNMADD132PHZ256rk, + VFNMADD132PHZ256rkz, + VFNMADD132PHZm, + VFNMADD132PHZmb, + VFNMADD132PHZmbk, + VFNMADD132PHZmbkz, + VFNMADD132PHZmk, + VFNMADD132PHZmkz, + VFNMADD132PHZr, + VFNMADD132PHZrb, + VFNMADD132PHZrbk, + VFNMADD132PHZrbkz, + VFNMADD132PHZrk, + VFNMADD132PHZrkz, + VFNMADD132PSYm, + VFNMADD132PSYr, + VFNMADD132PSZ128m, + VFNMADD132PSZ128mb, + VFNMADD132PSZ128mbk, + VFNMADD132PSZ128mbkz, + VFNMADD132PSZ128mk, + VFNMADD132PSZ128mkz, + VFNMADD132PSZ128r, + VFNMADD132PSZ128rk, + VFNMADD132PSZ128rkz, + VFNMADD132PSZ256m, + VFNMADD132PSZ256mb, + VFNMADD132PSZ256mbk, + VFNMADD132PSZ256mbkz, + VFNMADD132PSZ256mk, + VFNMADD132PSZ256mkz, + VFNMADD132PSZ256r, + VFNMADD132PSZ256rk, + VFNMADD132PSZ256rkz, + VFNMADD132PSZm, + VFNMADD132PSZmb, + VFNMADD132PSZmbk, + VFNMADD132PSZmbkz, + VFNMADD132PSZmk, + VFNMADD132PSZmkz, + VFNMADD132PSZr, + VFNMADD132PSZrb, + VFNMADD132PSZrbk, + VFNMADD132PSZrbkz, + VFNMADD132PSZrk, + VFNMADD132PSZrkz, + VFNMADD132PSm, + VFNMADD132PSr, + VFNMADD132SDZm, + VFNMADD132SDZm_Int, + VFNMADD132SDZmk_Int, + VFNMADD132SDZmkz_Int, + VFNMADD132SDZr, + VFNMADD132SDZr_Int, + VFNMADD132SDZrb, + VFNMADD132SDZrb_Int, + VFNMADD132SDZrbk_Int, + VFNMADD132SDZrbkz_Int, + VFNMADD132SDZrk_Int, + VFNMADD132SDZrkz_Int, + VFNMADD132SDm, + VFNMADD132SDm_Int, + VFNMADD132SDr, + VFNMADD132SDr_Int, + VFNMADD132SHZm, + VFNMADD132SHZm_Int, + VFNMADD132SHZmk_Int, + VFNMADD132SHZmkz_Int, + VFNMADD132SHZr, + VFNMADD132SHZr_Int, + VFNMADD132SHZrb, + VFNMADD132SHZrb_Int, + VFNMADD132SHZrbk_Int, + VFNMADD132SHZrbkz_Int, + VFNMADD132SHZrk_Int, + VFNMADD132SHZrkz_Int, + VFNMADD132SSZm, + VFNMADD132SSZm_Int, + VFNMADD132SSZmk_Int, + VFNMADD132SSZmkz_Int, + VFNMADD132SSZr, + VFNMADD132SSZr_Int, + VFNMADD132SSZrb, + VFNMADD132SSZrb_Int, + VFNMADD132SSZrbk_Int, + VFNMADD132SSZrbkz_Int, + VFNMADD132SSZrk_Int, + VFNMADD132SSZrkz_Int, + VFNMADD132SSm, + VFNMADD132SSm_Int, + VFNMADD132SSr, + VFNMADD132SSr_Int, + VFNMADD213BF16Z128m, + VFNMADD213BF16Z128mb, + VFNMADD213BF16Z128mbk, + VFNMADD213BF16Z128mbkz, + VFNMADD213BF16Z128mk, + VFNMADD213BF16Z128mkz, + VFNMADD213BF16Z128r, + VFNMADD213BF16Z128rk, + VFNMADD213BF16Z128rkz, + VFNMADD213BF16Z256m, + VFNMADD213BF16Z256mb, + VFNMADD213BF16Z256mbk, + VFNMADD213BF16Z256mbkz, + VFNMADD213BF16Z256mk, + VFNMADD213BF16Z256mkz, + VFNMADD213BF16Z256r, + VFNMADD213BF16Z256rk, + VFNMADD213BF16Z256rkz, + VFNMADD213BF16Zm, + VFNMADD213BF16Zmb, + VFNMADD213BF16Zmbk, + VFNMADD213BF16Zmbkz, + VFNMADD213BF16Zmk, + VFNMADD213BF16Zmkz, + VFNMADD213BF16Zr, + VFNMADD213BF16Zrk, + VFNMADD213BF16Zrkz, + VFNMADD213PDYm, + VFNMADD213PDYr, + VFNMADD213PDZ128m, + VFNMADD213PDZ128mb, + VFNMADD213PDZ128mbk, + VFNMADD213PDZ128mbkz, + VFNMADD213PDZ128mk, + VFNMADD213PDZ128mkz, + VFNMADD213PDZ128r, + VFNMADD213PDZ128rk, + VFNMADD213PDZ128rkz, + VFNMADD213PDZ256m, + VFNMADD213PDZ256mb, + VFNMADD213PDZ256mbk, + VFNMADD213PDZ256mbkz, + VFNMADD213PDZ256mk, + VFNMADD213PDZ256mkz, + VFNMADD213PDZ256r, + VFNMADD213PDZ256rk, + VFNMADD213PDZ256rkz, + VFNMADD213PDZm, + VFNMADD213PDZmb, + VFNMADD213PDZmbk, + VFNMADD213PDZmbkz, + VFNMADD213PDZmk, + VFNMADD213PDZmkz, + VFNMADD213PDZr, + VFNMADD213PDZrb, + VFNMADD213PDZrbk, + VFNMADD213PDZrbkz, + VFNMADD213PDZrk, + VFNMADD213PDZrkz, + VFNMADD213PDm, + VFNMADD213PDr, + VFNMADD213PHZ128m, + VFNMADD213PHZ128mb, + VFNMADD213PHZ128mbk, + VFNMADD213PHZ128mbkz, + VFNMADD213PHZ128mk, + VFNMADD213PHZ128mkz, + VFNMADD213PHZ128r, + VFNMADD213PHZ128rk, + VFNMADD213PHZ128rkz, + VFNMADD213PHZ256m, + VFNMADD213PHZ256mb, + VFNMADD213PHZ256mbk, + VFNMADD213PHZ256mbkz, + VFNMADD213PHZ256mk, + VFNMADD213PHZ256mkz, + VFNMADD213PHZ256r, + VFNMADD213PHZ256rk, + VFNMADD213PHZ256rkz, + VFNMADD213PHZm, + VFNMADD213PHZmb, + VFNMADD213PHZmbk, + VFNMADD213PHZmbkz, + VFNMADD213PHZmk, + VFNMADD213PHZmkz, + VFNMADD213PHZr, + VFNMADD213PHZrb, + VFNMADD213PHZrbk, + VFNMADD213PHZrbkz, + VFNMADD213PHZrk, + VFNMADD213PHZrkz, + VFNMADD213PSYm, + VFNMADD213PSYr, + VFNMADD213PSZ128m, + VFNMADD213PSZ128mb, + VFNMADD213PSZ128mbk, + VFNMADD213PSZ128mbkz, + VFNMADD213PSZ128mk, + VFNMADD213PSZ128mkz, + VFNMADD213PSZ128r, + VFNMADD213PSZ128rk, + VFNMADD213PSZ128rkz, + VFNMADD213PSZ256m, + VFNMADD213PSZ256mb, + VFNMADD213PSZ256mbk, + VFNMADD213PSZ256mbkz, + VFNMADD213PSZ256mk, + VFNMADD213PSZ256mkz, + VFNMADD213PSZ256r, + VFNMADD213PSZ256rk, + VFNMADD213PSZ256rkz, + VFNMADD213PSZm, + VFNMADD213PSZmb, + VFNMADD213PSZmbk, + VFNMADD213PSZmbkz, + VFNMADD213PSZmk, + VFNMADD213PSZmkz, + VFNMADD213PSZr, + VFNMADD213PSZrb, + VFNMADD213PSZrbk, + VFNMADD213PSZrbkz, + VFNMADD213PSZrk, + VFNMADD213PSZrkz, + VFNMADD213PSm, + VFNMADD213PSr, + VFNMADD213SDZm, + VFNMADD213SDZm_Int, + VFNMADD213SDZmk_Int, + VFNMADD213SDZmkz_Int, + VFNMADD213SDZr, + VFNMADD213SDZr_Int, + VFNMADD213SDZrb, + VFNMADD213SDZrb_Int, + VFNMADD213SDZrbk_Int, + VFNMADD213SDZrbkz_Int, + VFNMADD213SDZrk_Int, + VFNMADD213SDZrkz_Int, + VFNMADD213SDm, + VFNMADD213SDm_Int, + VFNMADD213SDr, + VFNMADD213SDr_Int, + VFNMADD213SHZm, + VFNMADD213SHZm_Int, + VFNMADD213SHZmk_Int, + VFNMADD213SHZmkz_Int, + VFNMADD213SHZr, + VFNMADD213SHZr_Int, + VFNMADD213SHZrb, + VFNMADD213SHZrb_Int, + VFNMADD213SHZrbk_Int, + VFNMADD213SHZrbkz_Int, + VFNMADD213SHZrk_Int, + VFNMADD213SHZrkz_Int, + VFNMADD213SSZm, + VFNMADD213SSZm_Int, + VFNMADD213SSZmk_Int, + VFNMADD213SSZmkz_Int, + VFNMADD213SSZr, + VFNMADD213SSZr_Int, + VFNMADD213SSZrb, + VFNMADD213SSZrb_Int, + VFNMADD213SSZrbk_Int, + VFNMADD213SSZrbkz_Int, + VFNMADD213SSZrk_Int, + VFNMADD213SSZrkz_Int, + VFNMADD213SSm, + VFNMADD213SSm_Int, + VFNMADD213SSr, + VFNMADD213SSr_Int, + VFNMADD231BF16Z128m, + VFNMADD231BF16Z128mb, + VFNMADD231BF16Z128mbk, + VFNMADD231BF16Z128mbkz, + VFNMADD231BF16Z128mk, + VFNMADD231BF16Z128mkz, + VFNMADD231BF16Z128r, + VFNMADD231BF16Z128rk, + VFNMADD231BF16Z128rkz, + VFNMADD231BF16Z256m, + VFNMADD231BF16Z256mb, + VFNMADD231BF16Z256mbk, + VFNMADD231BF16Z256mbkz, + VFNMADD231BF16Z256mk, + VFNMADD231BF16Z256mkz, + VFNMADD231BF16Z256r, + VFNMADD231BF16Z256rk, + VFNMADD231BF16Z256rkz, + VFNMADD231BF16Zm, + VFNMADD231BF16Zmb, + VFNMADD231BF16Zmbk, + VFNMADD231BF16Zmbkz, + VFNMADD231BF16Zmk, + VFNMADD231BF16Zmkz, + VFNMADD231BF16Zr, + VFNMADD231BF16Zrk, + VFNMADD231BF16Zrkz, + VFNMADD231PDYm, + VFNMADD231PDYr, + VFNMADD231PDZ128m, + VFNMADD231PDZ128mb, + VFNMADD231PDZ128mbk, + VFNMADD231PDZ128mbkz, + VFNMADD231PDZ128mk, + VFNMADD231PDZ128mkz, + VFNMADD231PDZ128r, + VFNMADD231PDZ128rk, + VFNMADD231PDZ128rkz, + VFNMADD231PDZ256m, + VFNMADD231PDZ256mb, + VFNMADD231PDZ256mbk, + VFNMADD231PDZ256mbkz, + VFNMADD231PDZ256mk, + VFNMADD231PDZ256mkz, + VFNMADD231PDZ256r, + VFNMADD231PDZ256rk, + VFNMADD231PDZ256rkz, + VFNMADD231PDZm, + VFNMADD231PDZmb, + VFNMADD231PDZmbk, + VFNMADD231PDZmbkz, + VFNMADD231PDZmk, + VFNMADD231PDZmkz, + VFNMADD231PDZr, + VFNMADD231PDZrb, + VFNMADD231PDZrbk, + VFNMADD231PDZrbkz, + VFNMADD231PDZrk, + VFNMADD231PDZrkz, + VFNMADD231PDm, + VFNMADD231PDr, + VFNMADD231PHZ128m, + VFNMADD231PHZ128mb, + VFNMADD231PHZ128mbk, + VFNMADD231PHZ128mbkz, + VFNMADD231PHZ128mk, + VFNMADD231PHZ128mkz, + VFNMADD231PHZ128r, + VFNMADD231PHZ128rk, + VFNMADD231PHZ128rkz, + VFNMADD231PHZ256m, + VFNMADD231PHZ256mb, + VFNMADD231PHZ256mbk, + VFNMADD231PHZ256mbkz, + VFNMADD231PHZ256mk, + VFNMADD231PHZ256mkz, + VFNMADD231PHZ256r, + VFNMADD231PHZ256rk, + VFNMADD231PHZ256rkz, + VFNMADD231PHZm, + VFNMADD231PHZmb, + VFNMADD231PHZmbk, + VFNMADD231PHZmbkz, + VFNMADD231PHZmk, + VFNMADD231PHZmkz, + VFNMADD231PHZr, + VFNMADD231PHZrb, + VFNMADD231PHZrbk, + VFNMADD231PHZrbkz, + VFNMADD231PHZrk, + VFNMADD231PHZrkz, + VFNMADD231PSYm, + VFNMADD231PSYr, + VFNMADD231PSZ128m, + VFNMADD231PSZ128mb, + VFNMADD231PSZ128mbk, + VFNMADD231PSZ128mbkz, + VFNMADD231PSZ128mk, + VFNMADD231PSZ128mkz, + VFNMADD231PSZ128r, + VFNMADD231PSZ128rk, + VFNMADD231PSZ128rkz, + VFNMADD231PSZ256m, + VFNMADD231PSZ256mb, + VFNMADD231PSZ256mbk, + VFNMADD231PSZ256mbkz, + VFNMADD231PSZ256mk, + VFNMADD231PSZ256mkz, + VFNMADD231PSZ256r, + VFNMADD231PSZ256rk, + VFNMADD231PSZ256rkz, + VFNMADD231PSZm, + VFNMADD231PSZmb, + VFNMADD231PSZmbk, + VFNMADD231PSZmbkz, + VFNMADD231PSZmk, + VFNMADD231PSZmkz, + VFNMADD231PSZr, + VFNMADD231PSZrb, + VFNMADD231PSZrbk, + VFNMADD231PSZrbkz, + VFNMADD231PSZrk, + VFNMADD231PSZrkz, + VFNMADD231PSm, + VFNMADD231PSr, + VFNMADD231SDZm, + VFNMADD231SDZm_Int, + VFNMADD231SDZmk_Int, + VFNMADD231SDZmkz_Int, + VFNMADD231SDZr, + VFNMADD231SDZr_Int, + VFNMADD231SDZrb, + VFNMADD231SDZrb_Int, + VFNMADD231SDZrbk_Int, + VFNMADD231SDZrbkz_Int, + VFNMADD231SDZrk_Int, + VFNMADD231SDZrkz_Int, + VFNMADD231SDm, + VFNMADD231SDm_Int, + VFNMADD231SDr, + VFNMADD231SDr_Int, + VFNMADD231SHZm, + VFNMADD231SHZm_Int, + VFNMADD231SHZmk_Int, + VFNMADD231SHZmkz_Int, + VFNMADD231SHZr, + VFNMADD231SHZr_Int, + VFNMADD231SHZrb, + VFNMADD231SHZrb_Int, + VFNMADD231SHZrbk_Int, + VFNMADD231SHZrbkz_Int, + VFNMADD231SHZrk_Int, + VFNMADD231SHZrkz_Int, + VFNMADD231SSZm, + VFNMADD231SSZm_Int, + VFNMADD231SSZmk_Int, + VFNMADD231SSZmkz_Int, + VFNMADD231SSZr, + VFNMADD231SSZr_Int, + VFNMADD231SSZrb, + VFNMADD231SSZrb_Int, + VFNMADD231SSZrbk_Int, + VFNMADD231SSZrbkz_Int, + VFNMADD231SSZrk_Int, + VFNMADD231SSZrkz_Int, + VFNMADD231SSm, + VFNMADD231SSm_Int, + VFNMADD231SSr, + VFNMADD231SSr_Int, + VFNMADDPD4Ymr, + VFNMADDPD4Yrm, + VFNMADDPD4Yrr, + VFNMADDPD4Yrr_REV, + VFNMADDPD4mr, + VFNMADDPD4rm, + VFNMADDPD4rr, + VFNMADDPD4rr_REV, + VFNMADDPS4Ymr, + VFNMADDPS4Yrm, + VFNMADDPS4Yrr, + VFNMADDPS4Yrr_REV, + VFNMADDPS4mr, + VFNMADDPS4rm, + VFNMADDPS4rr, + VFNMADDPS4rr_REV, + VFNMADDSD4mr, + VFNMADDSD4mr_Int, + VFNMADDSD4rm, + VFNMADDSD4rm_Int, + VFNMADDSD4rr, + VFNMADDSD4rr_Int, + VFNMADDSD4rr_Int_REV, + VFNMADDSD4rr_REV, + VFNMADDSS4mr, + VFNMADDSS4mr_Int, + VFNMADDSS4rm, + VFNMADDSS4rm_Int, + VFNMADDSS4rr, + VFNMADDSS4rr_Int, + VFNMADDSS4rr_Int_REV, + VFNMADDSS4rr_REV, + VFNMSUB132BF16Z128m, + VFNMSUB132BF16Z128mb, + VFNMSUB132BF16Z128mbk, + VFNMSUB132BF16Z128mbkz, + VFNMSUB132BF16Z128mk, + VFNMSUB132BF16Z128mkz, + VFNMSUB132BF16Z128r, + VFNMSUB132BF16Z128rk, + VFNMSUB132BF16Z128rkz, + VFNMSUB132BF16Z256m, + VFNMSUB132BF16Z256mb, + VFNMSUB132BF16Z256mbk, + VFNMSUB132BF16Z256mbkz, + VFNMSUB132BF16Z256mk, + VFNMSUB132BF16Z256mkz, + VFNMSUB132BF16Z256r, + VFNMSUB132BF16Z256rk, + VFNMSUB132BF16Z256rkz, + VFNMSUB132BF16Zm, + VFNMSUB132BF16Zmb, + VFNMSUB132BF16Zmbk, + VFNMSUB132BF16Zmbkz, + VFNMSUB132BF16Zmk, + VFNMSUB132BF16Zmkz, + VFNMSUB132BF16Zr, + VFNMSUB132BF16Zrk, + VFNMSUB132BF16Zrkz, + VFNMSUB132PDYm, + VFNMSUB132PDYr, + VFNMSUB132PDZ128m, + VFNMSUB132PDZ128mb, + VFNMSUB132PDZ128mbk, + VFNMSUB132PDZ128mbkz, + VFNMSUB132PDZ128mk, + VFNMSUB132PDZ128mkz, + VFNMSUB132PDZ128r, + VFNMSUB132PDZ128rk, + VFNMSUB132PDZ128rkz, + VFNMSUB132PDZ256m, + VFNMSUB132PDZ256mb, + VFNMSUB132PDZ256mbk, + VFNMSUB132PDZ256mbkz, + VFNMSUB132PDZ256mk, + VFNMSUB132PDZ256mkz, + VFNMSUB132PDZ256r, + VFNMSUB132PDZ256rk, + VFNMSUB132PDZ256rkz, + VFNMSUB132PDZm, + VFNMSUB132PDZmb, + VFNMSUB132PDZmbk, + VFNMSUB132PDZmbkz, + VFNMSUB132PDZmk, + VFNMSUB132PDZmkz, + VFNMSUB132PDZr, + VFNMSUB132PDZrb, + VFNMSUB132PDZrbk, + VFNMSUB132PDZrbkz, + VFNMSUB132PDZrk, + VFNMSUB132PDZrkz, + VFNMSUB132PDm, + VFNMSUB132PDr, + VFNMSUB132PHZ128m, + VFNMSUB132PHZ128mb, + VFNMSUB132PHZ128mbk, + VFNMSUB132PHZ128mbkz, + VFNMSUB132PHZ128mk, + VFNMSUB132PHZ128mkz, + VFNMSUB132PHZ128r, + VFNMSUB132PHZ128rk, + VFNMSUB132PHZ128rkz, + VFNMSUB132PHZ256m, + VFNMSUB132PHZ256mb, + VFNMSUB132PHZ256mbk, + VFNMSUB132PHZ256mbkz, + VFNMSUB132PHZ256mk, + VFNMSUB132PHZ256mkz, + VFNMSUB132PHZ256r, + VFNMSUB132PHZ256rk, + VFNMSUB132PHZ256rkz, + VFNMSUB132PHZm, + VFNMSUB132PHZmb, + VFNMSUB132PHZmbk, + VFNMSUB132PHZmbkz, + VFNMSUB132PHZmk, + VFNMSUB132PHZmkz, + VFNMSUB132PHZr, + VFNMSUB132PHZrb, + VFNMSUB132PHZrbk, + VFNMSUB132PHZrbkz, + VFNMSUB132PHZrk, + VFNMSUB132PHZrkz, + VFNMSUB132PSYm, + VFNMSUB132PSYr, + VFNMSUB132PSZ128m, + VFNMSUB132PSZ128mb, + VFNMSUB132PSZ128mbk, + VFNMSUB132PSZ128mbkz, + VFNMSUB132PSZ128mk, + VFNMSUB132PSZ128mkz, + VFNMSUB132PSZ128r, + VFNMSUB132PSZ128rk, + VFNMSUB132PSZ128rkz, + VFNMSUB132PSZ256m, + VFNMSUB132PSZ256mb, + VFNMSUB132PSZ256mbk, + VFNMSUB132PSZ256mbkz, + VFNMSUB132PSZ256mk, + VFNMSUB132PSZ256mkz, + VFNMSUB132PSZ256r, + VFNMSUB132PSZ256rk, + VFNMSUB132PSZ256rkz, + VFNMSUB132PSZm, + VFNMSUB132PSZmb, + VFNMSUB132PSZmbk, + VFNMSUB132PSZmbkz, + VFNMSUB132PSZmk, + VFNMSUB132PSZmkz, + VFNMSUB132PSZr, + VFNMSUB132PSZrb, + VFNMSUB132PSZrbk, + VFNMSUB132PSZrbkz, + VFNMSUB132PSZrk, + VFNMSUB132PSZrkz, + VFNMSUB132PSm, + VFNMSUB132PSr, + VFNMSUB132SDZm, + VFNMSUB132SDZm_Int, + VFNMSUB132SDZmk_Int, + VFNMSUB132SDZmkz_Int, + VFNMSUB132SDZr, + VFNMSUB132SDZr_Int, + VFNMSUB132SDZrb, + VFNMSUB132SDZrb_Int, + VFNMSUB132SDZrbk_Int, + VFNMSUB132SDZrbkz_Int, + VFNMSUB132SDZrk_Int, + VFNMSUB132SDZrkz_Int, + VFNMSUB132SDm, + VFNMSUB132SDm_Int, + VFNMSUB132SDr, + VFNMSUB132SDr_Int, + VFNMSUB132SHZm, + VFNMSUB132SHZm_Int, + VFNMSUB132SHZmk_Int, + VFNMSUB132SHZmkz_Int, + VFNMSUB132SHZr, + VFNMSUB132SHZr_Int, + VFNMSUB132SHZrb, + VFNMSUB132SHZrb_Int, + VFNMSUB132SHZrbk_Int, + VFNMSUB132SHZrbkz_Int, + VFNMSUB132SHZrk_Int, + VFNMSUB132SHZrkz_Int, + VFNMSUB132SSZm, + VFNMSUB132SSZm_Int, + VFNMSUB132SSZmk_Int, + VFNMSUB132SSZmkz_Int, + VFNMSUB132SSZr, + VFNMSUB132SSZr_Int, + VFNMSUB132SSZrb, + VFNMSUB132SSZrb_Int, + VFNMSUB132SSZrbk_Int, + VFNMSUB132SSZrbkz_Int, + VFNMSUB132SSZrk_Int, + VFNMSUB132SSZrkz_Int, + VFNMSUB132SSm, + VFNMSUB132SSm_Int, + VFNMSUB132SSr, + VFNMSUB132SSr_Int, + VFNMSUB213BF16Z128m, + VFNMSUB213BF16Z128mb, + VFNMSUB213BF16Z128mbk, + VFNMSUB213BF16Z128mbkz, + VFNMSUB213BF16Z128mk, + VFNMSUB213BF16Z128mkz, + VFNMSUB213BF16Z128r, + VFNMSUB213BF16Z128rk, + VFNMSUB213BF16Z128rkz, + VFNMSUB213BF16Z256m, + VFNMSUB213BF16Z256mb, + VFNMSUB213BF16Z256mbk, + VFNMSUB213BF16Z256mbkz, + VFNMSUB213BF16Z256mk, + VFNMSUB213BF16Z256mkz, + VFNMSUB213BF16Z256r, + VFNMSUB213BF16Z256rk, + VFNMSUB213BF16Z256rkz, + VFNMSUB213BF16Zm, + VFNMSUB213BF16Zmb, + VFNMSUB213BF16Zmbk, + VFNMSUB213BF16Zmbkz, + VFNMSUB213BF16Zmk, + VFNMSUB213BF16Zmkz, + VFNMSUB213BF16Zr, + VFNMSUB213BF16Zrk, + VFNMSUB213BF16Zrkz, + VFNMSUB213PDYm, + VFNMSUB213PDYr, + VFNMSUB213PDZ128m, + VFNMSUB213PDZ128mb, + VFNMSUB213PDZ128mbk, + VFNMSUB213PDZ128mbkz, + VFNMSUB213PDZ128mk, + VFNMSUB213PDZ128mkz, + VFNMSUB213PDZ128r, + VFNMSUB213PDZ128rk, + VFNMSUB213PDZ128rkz, + VFNMSUB213PDZ256m, + VFNMSUB213PDZ256mb, + VFNMSUB213PDZ256mbk, + VFNMSUB213PDZ256mbkz, + VFNMSUB213PDZ256mk, + VFNMSUB213PDZ256mkz, + VFNMSUB213PDZ256r, + VFNMSUB213PDZ256rk, + VFNMSUB213PDZ256rkz, + VFNMSUB213PDZm, + VFNMSUB213PDZmb, + VFNMSUB213PDZmbk, + VFNMSUB213PDZmbkz, + VFNMSUB213PDZmk, + VFNMSUB213PDZmkz, + VFNMSUB213PDZr, + VFNMSUB213PDZrb, + VFNMSUB213PDZrbk, + VFNMSUB213PDZrbkz, + VFNMSUB213PDZrk, + VFNMSUB213PDZrkz, + VFNMSUB213PDm, + VFNMSUB213PDr, + VFNMSUB213PHZ128m, + VFNMSUB213PHZ128mb, + VFNMSUB213PHZ128mbk, + VFNMSUB213PHZ128mbkz, + VFNMSUB213PHZ128mk, + VFNMSUB213PHZ128mkz, + VFNMSUB213PHZ128r, + VFNMSUB213PHZ128rk, + VFNMSUB213PHZ128rkz, + VFNMSUB213PHZ256m, + VFNMSUB213PHZ256mb, + VFNMSUB213PHZ256mbk, + VFNMSUB213PHZ256mbkz, + VFNMSUB213PHZ256mk, + VFNMSUB213PHZ256mkz, + VFNMSUB213PHZ256r, + VFNMSUB213PHZ256rk, + VFNMSUB213PHZ256rkz, + VFNMSUB213PHZm, + VFNMSUB213PHZmb, + VFNMSUB213PHZmbk, + VFNMSUB213PHZmbkz, + VFNMSUB213PHZmk, + VFNMSUB213PHZmkz, + VFNMSUB213PHZr, + VFNMSUB213PHZrb, + VFNMSUB213PHZrbk, + VFNMSUB213PHZrbkz, + VFNMSUB213PHZrk, + VFNMSUB213PHZrkz, + VFNMSUB213PSYm, + VFNMSUB213PSYr, + VFNMSUB213PSZ128m, + VFNMSUB213PSZ128mb, + VFNMSUB213PSZ128mbk, + VFNMSUB213PSZ128mbkz, + VFNMSUB213PSZ128mk, + VFNMSUB213PSZ128mkz, + VFNMSUB213PSZ128r, + VFNMSUB213PSZ128rk, + VFNMSUB213PSZ128rkz, + VFNMSUB213PSZ256m, + VFNMSUB213PSZ256mb, + VFNMSUB213PSZ256mbk, + VFNMSUB213PSZ256mbkz, + VFNMSUB213PSZ256mk, + VFNMSUB213PSZ256mkz, + VFNMSUB213PSZ256r, + VFNMSUB213PSZ256rk, + VFNMSUB213PSZ256rkz, + VFNMSUB213PSZm, + VFNMSUB213PSZmb, + VFNMSUB213PSZmbk, + VFNMSUB213PSZmbkz, + VFNMSUB213PSZmk, + VFNMSUB213PSZmkz, + VFNMSUB213PSZr, + VFNMSUB213PSZrb, + VFNMSUB213PSZrbk, + VFNMSUB213PSZrbkz, + VFNMSUB213PSZrk, + VFNMSUB213PSZrkz, + VFNMSUB213PSm, + VFNMSUB213PSr, + VFNMSUB213SDZm, + VFNMSUB213SDZm_Int, + VFNMSUB213SDZmk_Int, + VFNMSUB213SDZmkz_Int, + VFNMSUB213SDZr, + VFNMSUB213SDZr_Int, + VFNMSUB213SDZrb, + VFNMSUB213SDZrb_Int, + VFNMSUB213SDZrbk_Int, + VFNMSUB213SDZrbkz_Int, + VFNMSUB213SDZrk_Int, + VFNMSUB213SDZrkz_Int, + VFNMSUB213SDm, + VFNMSUB213SDm_Int, + VFNMSUB213SDr, + VFNMSUB213SDr_Int, + VFNMSUB213SHZm, + VFNMSUB213SHZm_Int, + VFNMSUB213SHZmk_Int, + VFNMSUB213SHZmkz_Int, + VFNMSUB213SHZr, + VFNMSUB213SHZr_Int, + VFNMSUB213SHZrb, + VFNMSUB213SHZrb_Int, + VFNMSUB213SHZrbk_Int, + VFNMSUB213SHZrbkz_Int, + VFNMSUB213SHZrk_Int, + VFNMSUB213SHZrkz_Int, + VFNMSUB213SSZm, + VFNMSUB213SSZm_Int, + VFNMSUB213SSZmk_Int, + VFNMSUB213SSZmkz_Int, + VFNMSUB213SSZr, + VFNMSUB213SSZr_Int, + VFNMSUB213SSZrb, + VFNMSUB213SSZrb_Int, + VFNMSUB213SSZrbk_Int, + VFNMSUB213SSZrbkz_Int, + VFNMSUB213SSZrk_Int, + VFNMSUB213SSZrkz_Int, + VFNMSUB213SSm, + VFNMSUB213SSm_Int, + VFNMSUB213SSr, + VFNMSUB213SSr_Int, + VFNMSUB231BF16Z128m, + VFNMSUB231BF16Z128mb, + VFNMSUB231BF16Z128mbk, + VFNMSUB231BF16Z128mbkz, + VFNMSUB231BF16Z128mk, + VFNMSUB231BF16Z128mkz, + VFNMSUB231BF16Z128r, + VFNMSUB231BF16Z128rk, + VFNMSUB231BF16Z128rkz, + VFNMSUB231BF16Z256m, + VFNMSUB231BF16Z256mb, + VFNMSUB231BF16Z256mbk, + VFNMSUB231BF16Z256mbkz, + VFNMSUB231BF16Z256mk, + VFNMSUB231BF16Z256mkz, + VFNMSUB231BF16Z256r, + VFNMSUB231BF16Z256rk, + VFNMSUB231BF16Z256rkz, + VFNMSUB231BF16Zm, + VFNMSUB231BF16Zmb, + VFNMSUB231BF16Zmbk, + VFNMSUB231BF16Zmbkz, + VFNMSUB231BF16Zmk, + VFNMSUB231BF16Zmkz, + VFNMSUB231BF16Zr, + VFNMSUB231BF16Zrk, + VFNMSUB231BF16Zrkz, + VFNMSUB231PDYm, + VFNMSUB231PDYr, + VFNMSUB231PDZ128m, + VFNMSUB231PDZ128mb, + VFNMSUB231PDZ128mbk, + VFNMSUB231PDZ128mbkz, + VFNMSUB231PDZ128mk, + VFNMSUB231PDZ128mkz, + VFNMSUB231PDZ128r, + VFNMSUB231PDZ128rk, + VFNMSUB231PDZ128rkz, + VFNMSUB231PDZ256m, + VFNMSUB231PDZ256mb, + VFNMSUB231PDZ256mbk, + VFNMSUB231PDZ256mbkz, + VFNMSUB231PDZ256mk, + VFNMSUB231PDZ256mkz, + VFNMSUB231PDZ256r, + VFNMSUB231PDZ256rk, + VFNMSUB231PDZ256rkz, + VFNMSUB231PDZm, + VFNMSUB231PDZmb, + VFNMSUB231PDZmbk, + VFNMSUB231PDZmbkz, + VFNMSUB231PDZmk, + VFNMSUB231PDZmkz, + VFNMSUB231PDZr, + VFNMSUB231PDZrb, + VFNMSUB231PDZrbk, + VFNMSUB231PDZrbkz, + VFNMSUB231PDZrk, + VFNMSUB231PDZrkz, + VFNMSUB231PDm, + VFNMSUB231PDr, + VFNMSUB231PHZ128m, + VFNMSUB231PHZ128mb, + VFNMSUB231PHZ128mbk, + VFNMSUB231PHZ128mbkz, + VFNMSUB231PHZ128mk, + VFNMSUB231PHZ128mkz, + VFNMSUB231PHZ128r, + VFNMSUB231PHZ128rk, + VFNMSUB231PHZ128rkz, + VFNMSUB231PHZ256m, + VFNMSUB231PHZ256mb, + VFNMSUB231PHZ256mbk, + VFNMSUB231PHZ256mbkz, + VFNMSUB231PHZ256mk, + VFNMSUB231PHZ256mkz, + VFNMSUB231PHZ256r, + VFNMSUB231PHZ256rk, + VFNMSUB231PHZ256rkz, + VFNMSUB231PHZm, + VFNMSUB231PHZmb, + VFNMSUB231PHZmbk, + VFNMSUB231PHZmbkz, + VFNMSUB231PHZmk, + VFNMSUB231PHZmkz, + VFNMSUB231PHZr, + VFNMSUB231PHZrb, + VFNMSUB231PHZrbk, + VFNMSUB231PHZrbkz, + VFNMSUB231PHZrk, + VFNMSUB231PHZrkz, + VFNMSUB231PSYm, + VFNMSUB231PSYr, + VFNMSUB231PSZ128m, + VFNMSUB231PSZ128mb, + VFNMSUB231PSZ128mbk, + VFNMSUB231PSZ128mbkz, + VFNMSUB231PSZ128mk, + VFNMSUB231PSZ128mkz, + VFNMSUB231PSZ128r, + VFNMSUB231PSZ128rk, + VFNMSUB231PSZ128rkz, + VFNMSUB231PSZ256m, + VFNMSUB231PSZ256mb, + VFNMSUB231PSZ256mbk, + VFNMSUB231PSZ256mbkz, + VFNMSUB231PSZ256mk, + VFNMSUB231PSZ256mkz, + VFNMSUB231PSZ256r, + VFNMSUB231PSZ256rk, + VFNMSUB231PSZ256rkz, + VFNMSUB231PSZm, + VFNMSUB231PSZmb, + VFNMSUB231PSZmbk, + VFNMSUB231PSZmbkz, + VFNMSUB231PSZmk, + VFNMSUB231PSZmkz, + VFNMSUB231PSZr, + VFNMSUB231PSZrb, + VFNMSUB231PSZrbk, + VFNMSUB231PSZrbkz, + VFNMSUB231PSZrk, + VFNMSUB231PSZrkz, + VFNMSUB231PSm, + VFNMSUB231PSr, + VFNMSUB231SDZm, + VFNMSUB231SDZm_Int, + VFNMSUB231SDZmk_Int, + VFNMSUB231SDZmkz_Int, + VFNMSUB231SDZr, + VFNMSUB231SDZr_Int, + VFNMSUB231SDZrb, + VFNMSUB231SDZrb_Int, + VFNMSUB231SDZrbk_Int, + VFNMSUB231SDZrbkz_Int, + VFNMSUB231SDZrk_Int, + VFNMSUB231SDZrkz_Int, + VFNMSUB231SDm, + VFNMSUB231SDm_Int, + VFNMSUB231SDr, + VFNMSUB231SDr_Int, + VFNMSUB231SHZm, + VFNMSUB231SHZm_Int, + VFNMSUB231SHZmk_Int, + VFNMSUB231SHZmkz_Int, + VFNMSUB231SHZr, + VFNMSUB231SHZr_Int, + VFNMSUB231SHZrb, + VFNMSUB231SHZrb_Int, + VFNMSUB231SHZrbk_Int, + VFNMSUB231SHZrbkz_Int, + VFNMSUB231SHZrk_Int, + VFNMSUB231SHZrkz_Int, + VFNMSUB231SSZm, + VFNMSUB231SSZm_Int, + VFNMSUB231SSZmk_Int, + VFNMSUB231SSZmkz_Int, + VFNMSUB231SSZr, + VFNMSUB231SSZr_Int, + VFNMSUB231SSZrb, + VFNMSUB231SSZrb_Int, + VFNMSUB231SSZrbk_Int, + VFNMSUB231SSZrbkz_Int, + VFNMSUB231SSZrk_Int, + VFNMSUB231SSZrkz_Int, + VFNMSUB231SSm, + VFNMSUB231SSm_Int, + VFNMSUB231SSr, + VFNMSUB231SSr_Int, + VFNMSUBPD4Ymr, + VFNMSUBPD4Yrm, + VFNMSUBPD4Yrr, + VFNMSUBPD4Yrr_REV, + VFNMSUBPD4mr, + VFNMSUBPD4rm, + VFNMSUBPD4rr, + VFNMSUBPD4rr_REV, + VFNMSUBPS4Ymr, + VFNMSUBPS4Yrm, + VFNMSUBPS4Yrr, + VFNMSUBPS4Yrr_REV, + VFNMSUBPS4mr, + VFNMSUBPS4rm, + VFNMSUBPS4rr, + VFNMSUBPS4rr_REV, + VFNMSUBSD4mr, + VFNMSUBSD4mr_Int, + VFNMSUBSD4rm, + VFNMSUBSD4rm_Int, + VFNMSUBSD4rr, + VFNMSUBSD4rr_Int, + VFNMSUBSD4rr_Int_REV, + VFNMSUBSD4rr_REV, + VFNMSUBSS4mr, + VFNMSUBSS4mr_Int, + VFNMSUBSS4rm, + VFNMSUBSS4rm_Int, + VFNMSUBSS4rr, + VFNMSUBSS4rr_Int, + VFNMSUBSS4rr_Int_REV, + VFNMSUBSS4rr_REV, + VFPCLASSBF16Z128mbi, + VFPCLASSBF16Z128mbik, + VFPCLASSBF16Z128mi, + VFPCLASSBF16Z128mik, + VFPCLASSBF16Z128ri, + VFPCLASSBF16Z128rik, + VFPCLASSBF16Z256mbi, + VFPCLASSBF16Z256mbik, + VFPCLASSBF16Z256mi, + VFPCLASSBF16Z256mik, + VFPCLASSBF16Z256ri, + VFPCLASSBF16Z256rik, + VFPCLASSBF16Zmbi, + VFPCLASSBF16Zmbik, + VFPCLASSBF16Zmi, + VFPCLASSBF16Zmik, + VFPCLASSBF16Zri, + VFPCLASSBF16Zrik, + VFPCLASSPDZ128mbi, + VFPCLASSPDZ128mbik, + VFPCLASSPDZ128mi, + VFPCLASSPDZ128mik, + VFPCLASSPDZ128ri, + VFPCLASSPDZ128rik, + VFPCLASSPDZ256mbi, + VFPCLASSPDZ256mbik, + VFPCLASSPDZ256mi, + VFPCLASSPDZ256mik, + VFPCLASSPDZ256ri, + VFPCLASSPDZ256rik, + VFPCLASSPDZmbi, + VFPCLASSPDZmbik, + VFPCLASSPDZmi, + VFPCLASSPDZmik, + VFPCLASSPDZri, + VFPCLASSPDZrik, + VFPCLASSPHZ128mbi, + VFPCLASSPHZ128mbik, + VFPCLASSPHZ128mi, + VFPCLASSPHZ128mik, + VFPCLASSPHZ128ri, + VFPCLASSPHZ128rik, + VFPCLASSPHZ256mbi, + VFPCLASSPHZ256mbik, + VFPCLASSPHZ256mi, + VFPCLASSPHZ256mik, + VFPCLASSPHZ256ri, + VFPCLASSPHZ256rik, + VFPCLASSPHZmbi, + VFPCLASSPHZmbik, + VFPCLASSPHZmi, + VFPCLASSPHZmik, + VFPCLASSPHZri, + VFPCLASSPHZrik, + VFPCLASSPSZ128mbi, + VFPCLASSPSZ128mbik, + VFPCLASSPSZ128mi, + VFPCLASSPSZ128mik, + VFPCLASSPSZ128ri, + VFPCLASSPSZ128rik, + VFPCLASSPSZ256mbi, + VFPCLASSPSZ256mbik, + VFPCLASSPSZ256mi, + VFPCLASSPSZ256mik, + VFPCLASSPSZ256ri, + VFPCLASSPSZ256rik, + VFPCLASSPSZmbi, + VFPCLASSPSZmbik, + VFPCLASSPSZmi, + VFPCLASSPSZmik, + VFPCLASSPSZri, + VFPCLASSPSZrik, + VFPCLASSSDZmi, + VFPCLASSSDZmik, + VFPCLASSSDZri, + VFPCLASSSDZrik, + VFPCLASSSHZmi, + VFPCLASSSHZmik, + VFPCLASSSHZri, + VFPCLASSSHZrik, + VFPCLASSSSZmi, + VFPCLASSSSZmik, + VFPCLASSSSZri, + VFPCLASSSSZrik, + VFRCZPDYrm, + VFRCZPDYrr, + VFRCZPDrm, + VFRCZPDrr, + VFRCZPSYrm, + VFRCZPSYrr, + VFRCZPSrm, + VFRCZPSrr, + VFRCZSDrm, + VFRCZSDrr, + VFRCZSSrm, + VFRCZSSrr, + VGATHERDPDYrm, + VGATHERDPDZ128rm, + VGATHERDPDZ256rm, + VGATHERDPDZrm, + VGATHERDPDrm, + VGATHERDPSYrm, + VGATHERDPSZ128rm, + VGATHERDPSZ256rm, + VGATHERDPSZrm, + VGATHERDPSrm, + VGATHERPF0DPDm, + VGATHERPF0DPSm, + VGATHERPF0QPDm, + VGATHERPF0QPSm, + VGATHERPF1DPDm, + VGATHERPF1DPSm, + VGATHERPF1QPDm, + VGATHERPF1QPSm, + VGATHERQPDYrm, + VGATHERQPDZ128rm, + VGATHERQPDZ256rm, + VGATHERQPDZrm, + VGATHERQPDrm, + VGATHERQPSYrm, + VGATHERQPSZ128rm, + VGATHERQPSZ256rm, + VGATHERQPSZrm, + VGATHERQPSrm, + VGETEXPBF16Z128m, + VGETEXPBF16Z128mb, + VGETEXPBF16Z128mbk, + VGETEXPBF16Z128mbkz, + VGETEXPBF16Z128mk, + VGETEXPBF16Z128mkz, + VGETEXPBF16Z128r, + VGETEXPBF16Z128rk, + VGETEXPBF16Z128rkz, + VGETEXPBF16Z256m, + VGETEXPBF16Z256mb, + VGETEXPBF16Z256mbk, + VGETEXPBF16Z256mbkz, + VGETEXPBF16Z256mk, + VGETEXPBF16Z256mkz, + VGETEXPBF16Z256r, + VGETEXPBF16Z256rk, + VGETEXPBF16Z256rkz, + VGETEXPBF16Zm, + VGETEXPBF16Zmb, + VGETEXPBF16Zmbk, + VGETEXPBF16Zmbkz, + VGETEXPBF16Zmk, + VGETEXPBF16Zmkz, + VGETEXPBF16Zr, + VGETEXPBF16Zrk, + VGETEXPBF16Zrkz, + VGETEXPPDZ128m, + VGETEXPPDZ128mb, + VGETEXPPDZ128mbk, + VGETEXPPDZ128mbkz, + VGETEXPPDZ128mk, + VGETEXPPDZ128mkz, + VGETEXPPDZ128r, + VGETEXPPDZ128rk, + VGETEXPPDZ128rkz, + VGETEXPPDZ256m, + VGETEXPPDZ256mb, + VGETEXPPDZ256mbk, + VGETEXPPDZ256mbkz, + VGETEXPPDZ256mk, + VGETEXPPDZ256mkz, + VGETEXPPDZ256r, + VGETEXPPDZ256rk, + VGETEXPPDZ256rkz, + VGETEXPPDZm, + VGETEXPPDZmb, + VGETEXPPDZmbk, + VGETEXPPDZmbkz, + VGETEXPPDZmk, + VGETEXPPDZmkz, + VGETEXPPDZr, + VGETEXPPDZrb, + VGETEXPPDZrbk, + VGETEXPPDZrbkz, + VGETEXPPDZrk, + VGETEXPPDZrkz, + VGETEXPPHZ128m, + VGETEXPPHZ128mb, + VGETEXPPHZ128mbk, + VGETEXPPHZ128mbkz, + VGETEXPPHZ128mk, + VGETEXPPHZ128mkz, + VGETEXPPHZ128r, + VGETEXPPHZ128rk, + VGETEXPPHZ128rkz, + VGETEXPPHZ256m, + VGETEXPPHZ256mb, + VGETEXPPHZ256mbk, + VGETEXPPHZ256mbkz, + VGETEXPPHZ256mk, + VGETEXPPHZ256mkz, + VGETEXPPHZ256r, + VGETEXPPHZ256rk, + VGETEXPPHZ256rkz, + VGETEXPPHZm, + VGETEXPPHZmb, + VGETEXPPHZmbk, + VGETEXPPHZmbkz, + VGETEXPPHZmk, + VGETEXPPHZmkz, + VGETEXPPHZr, + VGETEXPPHZrb, + VGETEXPPHZrbk, + VGETEXPPHZrbkz, + VGETEXPPHZrk, + VGETEXPPHZrkz, + VGETEXPPSZ128m, + VGETEXPPSZ128mb, + VGETEXPPSZ128mbk, + VGETEXPPSZ128mbkz, + VGETEXPPSZ128mk, + VGETEXPPSZ128mkz, + VGETEXPPSZ128r, + VGETEXPPSZ128rk, + VGETEXPPSZ128rkz, + VGETEXPPSZ256m, + VGETEXPPSZ256mb, + VGETEXPPSZ256mbk, + VGETEXPPSZ256mbkz, + VGETEXPPSZ256mk, + VGETEXPPSZ256mkz, + VGETEXPPSZ256r, + VGETEXPPSZ256rk, + VGETEXPPSZ256rkz, + VGETEXPPSZm, + VGETEXPPSZmb, + VGETEXPPSZmbk, + VGETEXPPSZmbkz, + VGETEXPPSZmk, + VGETEXPPSZmkz, + VGETEXPPSZr, + VGETEXPPSZrb, + VGETEXPPSZrbk, + VGETEXPPSZrbkz, + VGETEXPPSZrk, + VGETEXPPSZrkz, + VGETEXPSDZm, + VGETEXPSDZmk, + VGETEXPSDZmkz, + VGETEXPSDZr, + VGETEXPSDZrb, + VGETEXPSDZrbk, + VGETEXPSDZrbkz, + VGETEXPSDZrk, + VGETEXPSDZrkz, + VGETEXPSHZm, + VGETEXPSHZmk, + VGETEXPSHZmkz, + VGETEXPSHZr, + VGETEXPSHZrb, + VGETEXPSHZrbk, + VGETEXPSHZrbkz, + VGETEXPSHZrk, + VGETEXPSHZrkz, + VGETEXPSSZm, + VGETEXPSSZmk, + VGETEXPSSZmkz, + VGETEXPSSZr, + VGETEXPSSZrb, + VGETEXPSSZrbk, + VGETEXPSSZrbkz, + VGETEXPSSZrk, + VGETEXPSSZrkz, + VGETMANTBF16Z128rmbi, + VGETMANTBF16Z128rmbik, + VGETMANTBF16Z128rmbikz, + VGETMANTBF16Z128rmi, + VGETMANTBF16Z128rmik, + VGETMANTBF16Z128rmikz, + VGETMANTBF16Z128rri, + VGETMANTBF16Z128rrik, + VGETMANTBF16Z128rrikz, + VGETMANTBF16Z256rmbi, + VGETMANTBF16Z256rmbik, + VGETMANTBF16Z256rmbikz, + VGETMANTBF16Z256rmi, + VGETMANTBF16Z256rmik, + VGETMANTBF16Z256rmikz, + VGETMANTBF16Z256rri, + VGETMANTBF16Z256rrik, + VGETMANTBF16Z256rrikz, + VGETMANTBF16Zrmbi, + VGETMANTBF16Zrmbik, + VGETMANTBF16Zrmbikz, + VGETMANTBF16Zrmi, + VGETMANTBF16Zrmik, + VGETMANTBF16Zrmikz, + VGETMANTBF16Zrri, + VGETMANTBF16Zrrik, + VGETMANTBF16Zrrikz, + VGETMANTPDZ128rmbi, + VGETMANTPDZ128rmbik, + VGETMANTPDZ128rmbikz, + VGETMANTPDZ128rmi, + VGETMANTPDZ128rmik, + VGETMANTPDZ128rmikz, + VGETMANTPDZ128rri, + VGETMANTPDZ128rrik, + VGETMANTPDZ128rrikz, + VGETMANTPDZ256rmbi, + VGETMANTPDZ256rmbik, + VGETMANTPDZ256rmbikz, + VGETMANTPDZ256rmi, + VGETMANTPDZ256rmik, + VGETMANTPDZ256rmikz, + VGETMANTPDZ256rri, + VGETMANTPDZ256rrik, + VGETMANTPDZ256rrikz, + VGETMANTPDZrmbi, + VGETMANTPDZrmbik, + VGETMANTPDZrmbikz, + VGETMANTPDZrmi, + VGETMANTPDZrmik, + VGETMANTPDZrmikz, + VGETMANTPDZrri, + VGETMANTPDZrrib, + VGETMANTPDZrribk, + VGETMANTPDZrribkz, + VGETMANTPDZrrik, + VGETMANTPDZrrikz, + VGETMANTPHZ128rmbi, + VGETMANTPHZ128rmbik, + VGETMANTPHZ128rmbikz, + VGETMANTPHZ128rmi, + VGETMANTPHZ128rmik, + VGETMANTPHZ128rmikz, + VGETMANTPHZ128rri, + VGETMANTPHZ128rrik, + VGETMANTPHZ128rrikz, + VGETMANTPHZ256rmbi, + VGETMANTPHZ256rmbik, + VGETMANTPHZ256rmbikz, + VGETMANTPHZ256rmi, + VGETMANTPHZ256rmik, + VGETMANTPHZ256rmikz, + VGETMANTPHZ256rri, + VGETMANTPHZ256rrik, + VGETMANTPHZ256rrikz, + VGETMANTPHZrmbi, + VGETMANTPHZrmbik, + VGETMANTPHZrmbikz, + VGETMANTPHZrmi, + VGETMANTPHZrmik, + VGETMANTPHZrmikz, + VGETMANTPHZrri, + VGETMANTPHZrrib, + VGETMANTPHZrribk, + VGETMANTPHZrribkz, + VGETMANTPHZrrik, + VGETMANTPHZrrikz, + VGETMANTPSZ128rmbi, + VGETMANTPSZ128rmbik, + VGETMANTPSZ128rmbikz, + VGETMANTPSZ128rmi, + VGETMANTPSZ128rmik, + VGETMANTPSZ128rmikz, + VGETMANTPSZ128rri, + VGETMANTPSZ128rrik, + VGETMANTPSZ128rrikz, + VGETMANTPSZ256rmbi, + VGETMANTPSZ256rmbik, + VGETMANTPSZ256rmbikz, + VGETMANTPSZ256rmi, + VGETMANTPSZ256rmik, + VGETMANTPSZ256rmikz, + VGETMANTPSZ256rri, + VGETMANTPSZ256rrik, + VGETMANTPSZ256rrikz, + VGETMANTPSZrmbi, + VGETMANTPSZrmbik, + VGETMANTPSZrmbikz, + VGETMANTPSZrmi, + VGETMANTPSZrmik, + VGETMANTPSZrmikz, + VGETMANTPSZrri, + VGETMANTPSZrrib, + VGETMANTPSZrribk, + VGETMANTPSZrribkz, + VGETMANTPSZrrik, + VGETMANTPSZrrikz, + VGETMANTSDZrmi, + VGETMANTSDZrmik, + VGETMANTSDZrmikz, + VGETMANTSDZrri, + VGETMANTSDZrrib, + VGETMANTSDZrribk, + VGETMANTSDZrribkz, + VGETMANTSDZrrik, + VGETMANTSDZrrikz, + VGETMANTSHZrmi, + VGETMANTSHZrmik, + VGETMANTSHZrmikz, + VGETMANTSHZrri, + VGETMANTSHZrrib, + VGETMANTSHZrribk, + VGETMANTSHZrribkz, + VGETMANTSHZrrik, + VGETMANTSHZrrikz, + VGETMANTSSZrmi, + VGETMANTSSZrmik, + VGETMANTSSZrmikz, + VGETMANTSSZrri, + VGETMANTSSZrrib, + VGETMANTSSZrribk, + VGETMANTSSZrribkz, + VGETMANTSSZrrik, + VGETMANTSSZrrikz, + VGF2P8AFFINEINVQBYrmi, + VGF2P8AFFINEINVQBYrri, + VGF2P8AFFINEINVQBZ128rmbi, + VGF2P8AFFINEINVQBZ128rmbik, + VGF2P8AFFINEINVQBZ128rmbikz, + VGF2P8AFFINEINVQBZ128rmi, + VGF2P8AFFINEINVQBZ128rmik, + VGF2P8AFFINEINVQBZ128rmikz, + VGF2P8AFFINEINVQBZ128rri, + VGF2P8AFFINEINVQBZ128rrik, + VGF2P8AFFINEINVQBZ128rrikz, + VGF2P8AFFINEINVQBZ256rmbi, + VGF2P8AFFINEINVQBZ256rmbik, + VGF2P8AFFINEINVQBZ256rmbikz, + VGF2P8AFFINEINVQBZ256rmi, + VGF2P8AFFINEINVQBZ256rmik, + VGF2P8AFFINEINVQBZ256rmikz, + VGF2P8AFFINEINVQBZ256rri, + VGF2P8AFFINEINVQBZ256rrik, + VGF2P8AFFINEINVQBZ256rrikz, + VGF2P8AFFINEINVQBZrmbi, + VGF2P8AFFINEINVQBZrmbik, + VGF2P8AFFINEINVQBZrmbikz, + VGF2P8AFFINEINVQBZrmi, + VGF2P8AFFINEINVQBZrmik, + VGF2P8AFFINEINVQBZrmikz, + VGF2P8AFFINEINVQBZrri, + VGF2P8AFFINEINVQBZrrik, + VGF2P8AFFINEINVQBZrrikz, + VGF2P8AFFINEINVQBrmi, + VGF2P8AFFINEINVQBrri, + VGF2P8AFFINEQBYrmi, + VGF2P8AFFINEQBYrri, + VGF2P8AFFINEQBZ128rmbi, + VGF2P8AFFINEQBZ128rmbik, + VGF2P8AFFINEQBZ128rmbikz, + VGF2P8AFFINEQBZ128rmi, + VGF2P8AFFINEQBZ128rmik, + VGF2P8AFFINEQBZ128rmikz, + VGF2P8AFFINEQBZ128rri, + VGF2P8AFFINEQBZ128rrik, + VGF2P8AFFINEQBZ128rrikz, + VGF2P8AFFINEQBZ256rmbi, + VGF2P8AFFINEQBZ256rmbik, + VGF2P8AFFINEQBZ256rmbikz, + VGF2P8AFFINEQBZ256rmi, + VGF2P8AFFINEQBZ256rmik, + VGF2P8AFFINEQBZ256rmikz, + VGF2P8AFFINEQBZ256rri, + VGF2P8AFFINEQBZ256rrik, + VGF2P8AFFINEQBZ256rrikz, + VGF2P8AFFINEQBZrmbi, + VGF2P8AFFINEQBZrmbik, + VGF2P8AFFINEQBZrmbikz, + VGF2P8AFFINEQBZrmi, + VGF2P8AFFINEQBZrmik, + VGF2P8AFFINEQBZrmikz, + VGF2P8AFFINEQBZrri, + VGF2P8AFFINEQBZrrik, + VGF2P8AFFINEQBZrrikz, + VGF2P8AFFINEQBrmi, + VGF2P8AFFINEQBrri, + VGF2P8MULBYrm, + VGF2P8MULBYrr, + VGF2P8MULBZ128rm, + VGF2P8MULBZ128rmk, + VGF2P8MULBZ128rmkz, + VGF2P8MULBZ128rr, + VGF2P8MULBZ128rrk, + VGF2P8MULBZ128rrkz, + VGF2P8MULBZ256rm, + VGF2P8MULBZ256rmk, + VGF2P8MULBZ256rmkz, + VGF2P8MULBZ256rr, + VGF2P8MULBZ256rrk, + VGF2P8MULBZ256rrkz, + VGF2P8MULBZrm, + VGF2P8MULBZrmk, + VGF2P8MULBZrmkz, + VGF2P8MULBZrr, + VGF2P8MULBZrrk, + VGF2P8MULBZrrkz, + VGF2P8MULBrm, + VGF2P8MULBrr, + VHADDPDYrm, + VHADDPDYrr, + VHADDPDrm, + VHADDPDrr, + VHADDPSYrm, + VHADDPSYrr, + VHADDPSrm, + VHADDPSrr, + VHSUBPDYrm, + VHSUBPDYrr, + VHSUBPDrm, + VHSUBPDrr, + VHSUBPSYrm, + VHSUBPSYrr, + VHSUBPSrm, + VHSUBPSrr, + VINSERTF128rmi, + VINSERTF128rri, + VINSERTF32X4Z256rmi, + VINSERTF32X4Z256rmik, + VINSERTF32X4Z256rmikz, + VINSERTF32X4Z256rri, + VINSERTF32X4Z256rrik, + VINSERTF32X4Z256rrikz, + VINSERTF32X4Zrmi, + VINSERTF32X4Zrmik, + VINSERTF32X4Zrmikz, + VINSERTF32X4Zrri, + VINSERTF32X4Zrrik, + VINSERTF32X4Zrrikz, + VINSERTF32X8Zrmi, + VINSERTF32X8Zrmik, + VINSERTF32X8Zrmikz, + VINSERTF32X8Zrri, + VINSERTF32X8Zrrik, + VINSERTF32X8Zrrikz, + VINSERTF64X2Z256rmi, + VINSERTF64X2Z256rmik, + VINSERTF64X2Z256rmikz, + VINSERTF64X2Z256rri, + VINSERTF64X2Z256rrik, + VINSERTF64X2Z256rrikz, + VINSERTF64X2Zrmi, + VINSERTF64X2Zrmik, + VINSERTF64X2Zrmikz, + VINSERTF64X2Zrri, + VINSERTF64X2Zrrik, + VINSERTF64X2Zrrikz, + VINSERTF64X4Zrmi, + VINSERTF64X4Zrmik, + VINSERTF64X4Zrmikz, + VINSERTF64X4Zrri, + VINSERTF64X4Zrrik, + VINSERTF64X4Zrrikz, + VINSERTI128rmi, + VINSERTI128rri, + VINSERTI32X4Z256rmi, + VINSERTI32X4Z256rmik, + VINSERTI32X4Z256rmikz, + VINSERTI32X4Z256rri, + VINSERTI32X4Z256rrik, + VINSERTI32X4Z256rrikz, + VINSERTI32X4Zrmi, + VINSERTI32X4Zrmik, + VINSERTI32X4Zrmikz, + VINSERTI32X4Zrri, + VINSERTI32X4Zrrik, + VINSERTI32X4Zrrikz, + VINSERTI32X8Zrmi, + VINSERTI32X8Zrmik, + VINSERTI32X8Zrmikz, + VINSERTI32X8Zrri, + VINSERTI32X8Zrrik, + VINSERTI32X8Zrrikz, + VINSERTI64X2Z256rmi, + VINSERTI64X2Z256rmik, + VINSERTI64X2Z256rmikz, + VINSERTI64X2Z256rri, + VINSERTI64X2Z256rrik, + VINSERTI64X2Z256rrikz, + VINSERTI64X2Zrmi, + VINSERTI64X2Zrmik, + VINSERTI64X2Zrmikz, + VINSERTI64X2Zrri, + VINSERTI64X2Zrrik, + VINSERTI64X2Zrrikz, + VINSERTI64X4Zrmi, + VINSERTI64X4Zrmik, + VINSERTI64X4Zrmikz, + VINSERTI64X4Zrri, + VINSERTI64X4Zrrik, + VINSERTI64X4Zrrikz, + VINSERTPSZrmi, + VINSERTPSZrri, + VINSERTPSrmi, + VINSERTPSrri, + VLDDQUYrm, + VLDDQUrm, + VLDMXCSR, + VMASKMOVDQU, + VMASKMOVDQU64, + VMASKMOVPDYmr, + VMASKMOVPDYrm, + VMASKMOVPDmr, + VMASKMOVPDrm, + VMASKMOVPSYmr, + VMASKMOVPSYrm, + VMASKMOVPSmr, + VMASKMOVPSrm, + VMAXBF16Z128rm, + VMAXBF16Z128rmb, + VMAXBF16Z128rmbk, + VMAXBF16Z128rmbkz, + VMAXBF16Z128rmk, + VMAXBF16Z128rmkz, + VMAXBF16Z128rr, + VMAXBF16Z128rrk, + VMAXBF16Z128rrkz, + VMAXBF16Z256rm, + VMAXBF16Z256rmb, + VMAXBF16Z256rmbk, + VMAXBF16Z256rmbkz, + VMAXBF16Z256rmk, + VMAXBF16Z256rmkz, + VMAXBF16Z256rr, + VMAXBF16Z256rrk, + VMAXBF16Z256rrkz, + VMAXBF16Zrm, + VMAXBF16Zrmb, + VMAXBF16Zrmbk, + VMAXBF16Zrmbkz, + VMAXBF16Zrmk, + VMAXBF16Zrmkz, + VMAXBF16Zrr, + VMAXBF16Zrrk, + VMAXBF16Zrrkz, + VMAXCPDYrm, + VMAXCPDYrr, + VMAXCPDZ128rm, + VMAXCPDZ128rmb, + VMAXCPDZ128rmbk, + VMAXCPDZ128rmbkz, + VMAXCPDZ128rmk, + VMAXCPDZ128rmkz, + VMAXCPDZ128rr, + VMAXCPDZ128rrk, + VMAXCPDZ128rrkz, + VMAXCPDZ256rm, + VMAXCPDZ256rmb, + VMAXCPDZ256rmbk, + VMAXCPDZ256rmbkz, + VMAXCPDZ256rmk, + VMAXCPDZ256rmkz, + VMAXCPDZ256rr, + VMAXCPDZ256rrk, + VMAXCPDZ256rrkz, + VMAXCPDZrm, + VMAXCPDZrmb, + VMAXCPDZrmbk, + VMAXCPDZrmbkz, + VMAXCPDZrmk, + VMAXCPDZrmkz, + VMAXCPDZrr, + VMAXCPDZrrk, + VMAXCPDZrrkz, + VMAXCPDrm, + VMAXCPDrr, + VMAXCPHZ128rm, + VMAXCPHZ128rmb, + VMAXCPHZ128rmbk, + VMAXCPHZ128rmbkz, + VMAXCPHZ128rmk, + VMAXCPHZ128rmkz, + VMAXCPHZ128rr, + VMAXCPHZ128rrk, + VMAXCPHZ128rrkz, + VMAXCPHZ256rm, + VMAXCPHZ256rmb, + VMAXCPHZ256rmbk, + VMAXCPHZ256rmbkz, + VMAXCPHZ256rmk, + VMAXCPHZ256rmkz, + VMAXCPHZ256rr, + VMAXCPHZ256rrk, + VMAXCPHZ256rrkz, + VMAXCPHZrm, + VMAXCPHZrmb, + VMAXCPHZrmbk, + VMAXCPHZrmbkz, + VMAXCPHZrmk, + VMAXCPHZrmkz, + VMAXCPHZrr, + VMAXCPHZrrk, + VMAXCPHZrrkz, + VMAXCPSYrm, + VMAXCPSYrr, + VMAXCPSZ128rm, + VMAXCPSZ128rmb, + VMAXCPSZ128rmbk, + VMAXCPSZ128rmbkz, + VMAXCPSZ128rmk, + VMAXCPSZ128rmkz, + VMAXCPSZ128rr, + VMAXCPSZ128rrk, + VMAXCPSZ128rrkz, + VMAXCPSZ256rm, + VMAXCPSZ256rmb, + VMAXCPSZ256rmbk, + VMAXCPSZ256rmbkz, + VMAXCPSZ256rmk, + VMAXCPSZ256rmkz, + VMAXCPSZ256rr, + VMAXCPSZ256rrk, + VMAXCPSZ256rrkz, + VMAXCPSZrm, + VMAXCPSZrmb, + VMAXCPSZrmbk, + VMAXCPSZrmbkz, + VMAXCPSZrmk, + VMAXCPSZrmkz, + VMAXCPSZrr, + VMAXCPSZrrk, + VMAXCPSZrrkz, + VMAXCPSrm, + VMAXCPSrr, + VMAXCSDZrm, + VMAXCSDZrr, + VMAXCSDrm, + VMAXCSDrr, + VMAXCSHZrm, + VMAXCSHZrr, + VMAXCSSZrm, + VMAXCSSZrr, + VMAXCSSrm, + VMAXCSSrr, + VMAXPDYrm, + VMAXPDYrr, + VMAXPDZ128rm, + VMAXPDZ128rmb, + VMAXPDZ128rmbk, + VMAXPDZ128rmbkz, + VMAXPDZ128rmk, + VMAXPDZ128rmkz, + VMAXPDZ128rr, + VMAXPDZ128rrk, + VMAXPDZ128rrkz, + VMAXPDZ256rm, + VMAXPDZ256rmb, + VMAXPDZ256rmbk, + VMAXPDZ256rmbkz, + VMAXPDZ256rmk, + VMAXPDZ256rmkz, + VMAXPDZ256rr, + VMAXPDZ256rrk, + VMAXPDZ256rrkz, + VMAXPDZrm, + VMAXPDZrmb, + VMAXPDZrmbk, + VMAXPDZrmbkz, + VMAXPDZrmk, + VMAXPDZrmkz, + VMAXPDZrr, + VMAXPDZrrb, + VMAXPDZrrbk, + VMAXPDZrrbkz, + VMAXPDZrrk, + VMAXPDZrrkz, + VMAXPDrm, + VMAXPDrr, + VMAXPHZ128rm, + VMAXPHZ128rmb, + VMAXPHZ128rmbk, + VMAXPHZ128rmbkz, + VMAXPHZ128rmk, + VMAXPHZ128rmkz, + VMAXPHZ128rr, + VMAXPHZ128rrk, + VMAXPHZ128rrkz, + VMAXPHZ256rm, + VMAXPHZ256rmb, + VMAXPHZ256rmbk, + VMAXPHZ256rmbkz, + VMAXPHZ256rmk, + VMAXPHZ256rmkz, + VMAXPHZ256rr, + VMAXPHZ256rrk, + VMAXPHZ256rrkz, + VMAXPHZrm, + VMAXPHZrmb, + VMAXPHZrmbk, + VMAXPHZrmbkz, + VMAXPHZrmk, + VMAXPHZrmkz, + VMAXPHZrr, + VMAXPHZrrb, + VMAXPHZrrbk, + VMAXPHZrrbkz, + VMAXPHZrrk, + VMAXPHZrrkz, + VMAXPSYrm, + VMAXPSYrr, + VMAXPSZ128rm, + VMAXPSZ128rmb, + VMAXPSZ128rmbk, + VMAXPSZ128rmbkz, + VMAXPSZ128rmk, + VMAXPSZ128rmkz, + VMAXPSZ128rr, + VMAXPSZ128rrk, + VMAXPSZ128rrkz, + VMAXPSZ256rm, + VMAXPSZ256rmb, + VMAXPSZ256rmbk, + VMAXPSZ256rmbkz, + VMAXPSZ256rmk, + VMAXPSZ256rmkz, + VMAXPSZ256rr, + VMAXPSZ256rrk, + VMAXPSZ256rrkz, + VMAXPSZrm, + VMAXPSZrmb, + VMAXPSZrmbk, + VMAXPSZrmbkz, + VMAXPSZrmk, + VMAXPSZrmkz, + VMAXPSZrr, + VMAXPSZrrb, + VMAXPSZrrbk, + VMAXPSZrrbkz, + VMAXPSZrrk, + VMAXPSZrrkz, + VMAXPSrm, + VMAXPSrr, + VMAXSDZrm, + VMAXSDZrm_Int, + VMAXSDZrmk_Int, + VMAXSDZrmkz_Int, + VMAXSDZrr, + VMAXSDZrr_Int, + VMAXSDZrrb_Int, + VMAXSDZrrbk_Int, + VMAXSDZrrbkz_Int, + VMAXSDZrrk_Int, + VMAXSDZrrkz_Int, + VMAXSDrm, + VMAXSDrm_Int, + VMAXSDrr, + VMAXSDrr_Int, + VMAXSHZrm, + VMAXSHZrm_Int, + VMAXSHZrmk_Int, + VMAXSHZrmkz_Int, + VMAXSHZrr, + VMAXSHZrr_Int, + VMAXSHZrrb_Int, + VMAXSHZrrbk_Int, + VMAXSHZrrbkz_Int, + VMAXSHZrrk_Int, + VMAXSHZrrkz_Int, + VMAXSSZrm, + VMAXSSZrm_Int, + VMAXSSZrmk_Int, + VMAXSSZrmkz_Int, + VMAXSSZrr, + VMAXSSZrr_Int, + VMAXSSZrrb_Int, + VMAXSSZrrbk_Int, + VMAXSSZrrbkz_Int, + VMAXSSZrrk_Int, + VMAXSSZrrkz_Int, + VMAXSSrm, + VMAXSSrm_Int, + VMAXSSrr, + VMAXSSrr_Int, + VMCALL, + VMCLEARm, + VMFUNC, + VMINBF16Z128rm, + VMINBF16Z128rmb, + VMINBF16Z128rmbk, + VMINBF16Z128rmbkz, + VMINBF16Z128rmk, + VMINBF16Z128rmkz, + VMINBF16Z128rr, + VMINBF16Z128rrk, + VMINBF16Z128rrkz, + VMINBF16Z256rm, + VMINBF16Z256rmb, + VMINBF16Z256rmbk, + VMINBF16Z256rmbkz, + VMINBF16Z256rmk, + VMINBF16Z256rmkz, + VMINBF16Z256rr, + VMINBF16Z256rrk, + VMINBF16Z256rrkz, + VMINBF16Zrm, + VMINBF16Zrmb, + VMINBF16Zrmbk, + VMINBF16Zrmbkz, + VMINBF16Zrmk, + VMINBF16Zrmkz, + VMINBF16Zrr, + VMINBF16Zrrk, + VMINBF16Zrrkz, + VMINCPDYrm, + VMINCPDYrr, + VMINCPDZ128rm, + VMINCPDZ128rmb, + VMINCPDZ128rmbk, + VMINCPDZ128rmbkz, + VMINCPDZ128rmk, + VMINCPDZ128rmkz, + VMINCPDZ128rr, + VMINCPDZ128rrk, + VMINCPDZ128rrkz, + VMINCPDZ256rm, + VMINCPDZ256rmb, + VMINCPDZ256rmbk, + VMINCPDZ256rmbkz, + VMINCPDZ256rmk, + VMINCPDZ256rmkz, + VMINCPDZ256rr, + VMINCPDZ256rrk, + VMINCPDZ256rrkz, + VMINCPDZrm, + VMINCPDZrmb, + VMINCPDZrmbk, + VMINCPDZrmbkz, + VMINCPDZrmk, + VMINCPDZrmkz, + VMINCPDZrr, + VMINCPDZrrk, + VMINCPDZrrkz, + VMINCPDrm, + VMINCPDrr, + VMINCPHZ128rm, + VMINCPHZ128rmb, + VMINCPHZ128rmbk, + VMINCPHZ128rmbkz, + VMINCPHZ128rmk, + VMINCPHZ128rmkz, + VMINCPHZ128rr, + VMINCPHZ128rrk, + VMINCPHZ128rrkz, + VMINCPHZ256rm, + VMINCPHZ256rmb, + VMINCPHZ256rmbk, + VMINCPHZ256rmbkz, + VMINCPHZ256rmk, + VMINCPHZ256rmkz, + VMINCPHZ256rr, + VMINCPHZ256rrk, + VMINCPHZ256rrkz, + VMINCPHZrm, + VMINCPHZrmb, + VMINCPHZrmbk, + VMINCPHZrmbkz, + VMINCPHZrmk, + VMINCPHZrmkz, + VMINCPHZrr, + VMINCPHZrrk, + VMINCPHZrrkz, + VMINCPSYrm, + VMINCPSYrr, + VMINCPSZ128rm, + VMINCPSZ128rmb, + VMINCPSZ128rmbk, + VMINCPSZ128rmbkz, + VMINCPSZ128rmk, + VMINCPSZ128rmkz, + VMINCPSZ128rr, + VMINCPSZ128rrk, + VMINCPSZ128rrkz, + VMINCPSZ256rm, + VMINCPSZ256rmb, + VMINCPSZ256rmbk, + VMINCPSZ256rmbkz, + VMINCPSZ256rmk, + VMINCPSZ256rmkz, + VMINCPSZ256rr, + VMINCPSZ256rrk, + VMINCPSZ256rrkz, + VMINCPSZrm, + VMINCPSZrmb, + VMINCPSZrmbk, + VMINCPSZrmbkz, + VMINCPSZrmk, + VMINCPSZrmkz, + VMINCPSZrr, + VMINCPSZrrk, + VMINCPSZrrkz, + VMINCPSrm, + VMINCPSrr, + VMINCSDZrm, + VMINCSDZrr, + VMINCSDrm, + VMINCSDrr, + VMINCSHZrm, + VMINCSHZrr, + VMINCSSZrm, + VMINCSSZrr, + VMINCSSrm, + VMINCSSrr, + VMINMAXBF16Z128rmbi, + VMINMAXBF16Z128rmbik, + VMINMAXBF16Z128rmbikz, + VMINMAXBF16Z128rmi, + VMINMAXBF16Z128rmik, + VMINMAXBF16Z128rmikz, + VMINMAXBF16Z128rri, + VMINMAXBF16Z128rrik, + VMINMAXBF16Z128rrikz, + VMINMAXBF16Z256rmbi, + VMINMAXBF16Z256rmbik, + VMINMAXBF16Z256rmbikz, + VMINMAXBF16Z256rmi, + VMINMAXBF16Z256rmik, + VMINMAXBF16Z256rmikz, + VMINMAXBF16Z256rri, + VMINMAXBF16Z256rrik, + VMINMAXBF16Z256rrikz, + VMINMAXBF16Zrmbi, + VMINMAXBF16Zrmbik, + VMINMAXBF16Zrmbikz, + VMINMAXBF16Zrmi, + VMINMAXBF16Zrmik, + VMINMAXBF16Zrmikz, + VMINMAXBF16Zrri, + VMINMAXBF16Zrrik, + VMINMAXBF16Zrrikz, + VMINMAXPDZ128rmbi, + VMINMAXPDZ128rmbik, + VMINMAXPDZ128rmbikz, + VMINMAXPDZ128rmi, + VMINMAXPDZ128rmik, + VMINMAXPDZ128rmikz, + VMINMAXPDZ128rri, + VMINMAXPDZ128rrik, + VMINMAXPDZ128rrikz, + VMINMAXPDZ256rmbi, + VMINMAXPDZ256rmbik, + VMINMAXPDZ256rmbikz, + VMINMAXPDZ256rmi, + VMINMAXPDZ256rmik, + VMINMAXPDZ256rmikz, + VMINMAXPDZ256rri, + VMINMAXPDZ256rrik, + VMINMAXPDZ256rrikz, + VMINMAXPDZrmbi, + VMINMAXPDZrmbik, + VMINMAXPDZrmbikz, + VMINMAXPDZrmi, + VMINMAXPDZrmik, + VMINMAXPDZrmikz, + VMINMAXPDZrri, + VMINMAXPDZrrib, + VMINMAXPDZrribk, + VMINMAXPDZrribkz, + VMINMAXPDZrrik, + VMINMAXPDZrrikz, + VMINMAXPHZ128rmbi, + VMINMAXPHZ128rmbik, + VMINMAXPHZ128rmbikz, + VMINMAXPHZ128rmi, + VMINMAXPHZ128rmik, + VMINMAXPHZ128rmikz, + VMINMAXPHZ128rri, + VMINMAXPHZ128rrik, + VMINMAXPHZ128rrikz, + VMINMAXPHZ256rmbi, + VMINMAXPHZ256rmbik, + VMINMAXPHZ256rmbikz, + VMINMAXPHZ256rmi, + VMINMAXPHZ256rmik, + VMINMAXPHZ256rmikz, + VMINMAXPHZ256rri, + VMINMAXPHZ256rrik, + VMINMAXPHZ256rrikz, + VMINMAXPHZrmbi, + VMINMAXPHZrmbik, + VMINMAXPHZrmbikz, + VMINMAXPHZrmi, + VMINMAXPHZrmik, + VMINMAXPHZrmikz, + VMINMAXPHZrri, + VMINMAXPHZrrib, + VMINMAXPHZrribk, + VMINMAXPHZrribkz, + VMINMAXPHZrrik, + VMINMAXPHZrrikz, + VMINMAXPSZ128rmbi, + VMINMAXPSZ128rmbik, + VMINMAXPSZ128rmbikz, + VMINMAXPSZ128rmi, + VMINMAXPSZ128rmik, + VMINMAXPSZ128rmikz, + VMINMAXPSZ128rri, + VMINMAXPSZ128rrik, + VMINMAXPSZ128rrikz, + VMINMAXPSZ256rmbi, + VMINMAXPSZ256rmbik, + VMINMAXPSZ256rmbikz, + VMINMAXPSZ256rmi, + VMINMAXPSZ256rmik, + VMINMAXPSZ256rmikz, + VMINMAXPSZ256rri, + VMINMAXPSZ256rrik, + VMINMAXPSZ256rrikz, + VMINMAXPSZrmbi, + VMINMAXPSZrmbik, + VMINMAXPSZrmbikz, + VMINMAXPSZrmi, + VMINMAXPSZrmik, + VMINMAXPSZrmikz, + VMINMAXPSZrri, + VMINMAXPSZrrib, + VMINMAXPSZrribk, + VMINMAXPSZrribkz, + VMINMAXPSZrrik, + VMINMAXPSZrrikz, + VMINMAXSDrmi, + VMINMAXSDrmi_Int, + VMINMAXSDrmik_Int, + VMINMAXSDrmikz_Int, + VMINMAXSDrri, + VMINMAXSDrri_Int, + VMINMAXSDrrib_Int, + VMINMAXSDrribk_Int, + VMINMAXSDrribkz_Int, + VMINMAXSDrrik_Int, + VMINMAXSDrrikz_Int, + VMINMAXSHrmi, + VMINMAXSHrmi_Int, + VMINMAXSHrmik_Int, + VMINMAXSHrmikz_Int, + VMINMAXSHrri, + VMINMAXSHrri_Int, + VMINMAXSHrrib_Int, + VMINMAXSHrribk_Int, + VMINMAXSHrribkz_Int, + VMINMAXSHrrik_Int, + VMINMAXSHrrikz_Int, + VMINMAXSSrmi, + VMINMAXSSrmi_Int, + VMINMAXSSrmik_Int, + VMINMAXSSrmikz_Int, + VMINMAXSSrri, + VMINMAXSSrri_Int, + VMINMAXSSrrib_Int, + VMINMAXSSrribk_Int, + VMINMAXSSrribkz_Int, + VMINMAXSSrrik_Int, + VMINMAXSSrrikz_Int, + VMINPDYrm, + VMINPDYrr, + VMINPDZ128rm, + VMINPDZ128rmb, + VMINPDZ128rmbk, + VMINPDZ128rmbkz, + VMINPDZ128rmk, + VMINPDZ128rmkz, + VMINPDZ128rr, + VMINPDZ128rrk, + VMINPDZ128rrkz, + VMINPDZ256rm, + VMINPDZ256rmb, + VMINPDZ256rmbk, + VMINPDZ256rmbkz, + VMINPDZ256rmk, + VMINPDZ256rmkz, + VMINPDZ256rr, + VMINPDZ256rrk, + VMINPDZ256rrkz, + VMINPDZrm, + VMINPDZrmb, + VMINPDZrmbk, + VMINPDZrmbkz, + VMINPDZrmk, + VMINPDZrmkz, + VMINPDZrr, + VMINPDZrrb, + VMINPDZrrbk, + VMINPDZrrbkz, + VMINPDZrrk, + VMINPDZrrkz, + VMINPDrm, + VMINPDrr, + VMINPHZ128rm, + VMINPHZ128rmb, + VMINPHZ128rmbk, + VMINPHZ128rmbkz, + VMINPHZ128rmk, + VMINPHZ128rmkz, + VMINPHZ128rr, + VMINPHZ128rrk, + VMINPHZ128rrkz, + VMINPHZ256rm, + VMINPHZ256rmb, + VMINPHZ256rmbk, + VMINPHZ256rmbkz, + VMINPHZ256rmk, + VMINPHZ256rmkz, + VMINPHZ256rr, + VMINPHZ256rrk, + VMINPHZ256rrkz, + VMINPHZrm, + VMINPHZrmb, + VMINPHZrmbk, + VMINPHZrmbkz, + VMINPHZrmk, + VMINPHZrmkz, + VMINPHZrr, + VMINPHZrrb, + VMINPHZrrbk, + VMINPHZrrbkz, + VMINPHZrrk, + VMINPHZrrkz, + VMINPSYrm, + VMINPSYrr, + VMINPSZ128rm, + VMINPSZ128rmb, + VMINPSZ128rmbk, + VMINPSZ128rmbkz, + VMINPSZ128rmk, + VMINPSZ128rmkz, + VMINPSZ128rr, + VMINPSZ128rrk, + VMINPSZ128rrkz, + VMINPSZ256rm, + VMINPSZ256rmb, + VMINPSZ256rmbk, + VMINPSZ256rmbkz, + VMINPSZ256rmk, + VMINPSZ256rmkz, + VMINPSZ256rr, + VMINPSZ256rrk, + VMINPSZ256rrkz, + VMINPSZrm, + VMINPSZrmb, + VMINPSZrmbk, + VMINPSZrmbkz, + VMINPSZrmk, + VMINPSZrmkz, + VMINPSZrr, + VMINPSZrrb, + VMINPSZrrbk, + VMINPSZrrbkz, + VMINPSZrrk, + VMINPSZrrkz, + VMINPSrm, + VMINPSrr, + VMINSDZrm, + VMINSDZrm_Int, + VMINSDZrmk_Int, + VMINSDZrmkz_Int, + VMINSDZrr, + VMINSDZrr_Int, + VMINSDZrrb_Int, + VMINSDZrrbk_Int, + VMINSDZrrbkz_Int, + VMINSDZrrk_Int, + VMINSDZrrkz_Int, + VMINSDrm, + VMINSDrm_Int, + VMINSDrr, + VMINSDrr_Int, + VMINSHZrm, + VMINSHZrm_Int, + VMINSHZrmk_Int, + VMINSHZrmkz_Int, + VMINSHZrr, + VMINSHZrr_Int, + VMINSHZrrb_Int, + VMINSHZrrbk_Int, + VMINSHZrrbkz_Int, + VMINSHZrrk_Int, + VMINSHZrrkz_Int, + VMINSSZrm, + VMINSSZrm_Int, + VMINSSZrmk_Int, + VMINSSZrmkz_Int, + VMINSSZrr, + VMINSSZrr_Int, + VMINSSZrrb_Int, + VMINSSZrrbk_Int, + VMINSSZrrbkz_Int, + VMINSSZrrk_Int, + VMINSSZrrkz_Int, + VMINSSrm, + VMINSSrm_Int, + VMINSSrr, + VMINSSrr_Int, + VMLAUNCH, + VMLOAD32, + VMLOAD64, + VMMCALL, + VMOV64toPQIZrm, + VMOV64toPQIZrr, + VMOV64toPQIrm, + VMOV64toPQIrr, + VMOV64toSDZrr, + VMOV64toSDrr, + VMOVAPDYmr, + VMOVAPDYrm, + VMOVAPDYrr, + VMOVAPDYrr_REV, + VMOVAPDZ128mr, + VMOVAPDZ128mrk, + VMOVAPDZ128rm, + VMOVAPDZ128rmk, + VMOVAPDZ128rmkz, + VMOVAPDZ128rr, + VMOVAPDZ128rr_REV, + VMOVAPDZ128rrk, + VMOVAPDZ128rrk_REV, + VMOVAPDZ128rrkz, + VMOVAPDZ128rrkz_REV, + VMOVAPDZ256mr, + VMOVAPDZ256mrk, + VMOVAPDZ256rm, + VMOVAPDZ256rmk, + VMOVAPDZ256rmkz, + VMOVAPDZ256rr, + VMOVAPDZ256rr_REV, + VMOVAPDZ256rrk, + VMOVAPDZ256rrk_REV, + VMOVAPDZ256rrkz, + VMOVAPDZ256rrkz_REV, + VMOVAPDZmr, + VMOVAPDZmrk, + VMOVAPDZrm, + VMOVAPDZrmk, + VMOVAPDZrmkz, + VMOVAPDZrr, + VMOVAPDZrr_REV, + VMOVAPDZrrk, + VMOVAPDZrrk_REV, + VMOVAPDZrrkz, + VMOVAPDZrrkz_REV, + VMOVAPDmr, + VMOVAPDrm, + VMOVAPDrr, + VMOVAPDrr_REV, + VMOVAPSYmr, + VMOVAPSYrm, + VMOVAPSYrr, + VMOVAPSYrr_REV, + VMOVAPSZ128mr, + VMOVAPSZ128mrk, + VMOVAPSZ128rm, + VMOVAPSZ128rmk, + VMOVAPSZ128rmkz, + VMOVAPSZ128rr, + VMOVAPSZ128rr_REV, + VMOVAPSZ128rrk, + VMOVAPSZ128rrk_REV, + VMOVAPSZ128rrkz, + VMOVAPSZ128rrkz_REV, + VMOVAPSZ256mr, + VMOVAPSZ256mrk, + VMOVAPSZ256rm, + VMOVAPSZ256rmk, + VMOVAPSZ256rmkz, + VMOVAPSZ256rr, + VMOVAPSZ256rr_REV, + VMOVAPSZ256rrk, + VMOVAPSZ256rrk_REV, + VMOVAPSZ256rrkz, + VMOVAPSZ256rrkz_REV, + VMOVAPSZmr, + VMOVAPSZmrk, + VMOVAPSZrm, + VMOVAPSZrmk, + VMOVAPSZrmkz, + VMOVAPSZrr, + VMOVAPSZrr_REV, + VMOVAPSZrrk, + VMOVAPSZrrk_REV, + VMOVAPSZrrkz, + VMOVAPSZrrkz_REV, + VMOVAPSmr, + VMOVAPSrm, + VMOVAPSrr, + VMOVAPSrr_REV, + VMOVDDUPYrm, + VMOVDDUPYrr, + VMOVDDUPZ128rm, + VMOVDDUPZ128rmk, + VMOVDDUPZ128rmkz, + VMOVDDUPZ128rr, + VMOVDDUPZ128rrk, + VMOVDDUPZ128rrkz, + VMOVDDUPZ256rm, + VMOVDDUPZ256rmk, + VMOVDDUPZ256rmkz, + VMOVDDUPZ256rr, + VMOVDDUPZ256rrk, + VMOVDDUPZ256rrkz, + VMOVDDUPZrm, + VMOVDDUPZrmk, + VMOVDDUPZrmkz, + VMOVDDUPZrr, + VMOVDDUPZrrk, + VMOVDDUPZrrkz, + VMOVDDUPrm, + VMOVDDUPrr, + VMOVDI2PDIZrm, + VMOVDI2PDIZrr, + VMOVDI2PDIrm, + VMOVDI2PDIrr, + VMOVDI2SSZrr, + VMOVDI2SSrr, + VMOVDQA32Z128mr, + VMOVDQA32Z128mrk, + VMOVDQA32Z128rm, + VMOVDQA32Z128rmk, + VMOVDQA32Z128rmkz, + VMOVDQA32Z128rr, + VMOVDQA32Z128rr_REV, + VMOVDQA32Z128rrk, + VMOVDQA32Z128rrk_REV, + VMOVDQA32Z128rrkz, + VMOVDQA32Z128rrkz_REV, + VMOVDQA32Z256mr, + VMOVDQA32Z256mrk, + VMOVDQA32Z256rm, + VMOVDQA32Z256rmk, + VMOVDQA32Z256rmkz, + VMOVDQA32Z256rr, + VMOVDQA32Z256rr_REV, + VMOVDQA32Z256rrk, + VMOVDQA32Z256rrk_REV, + VMOVDQA32Z256rrkz, + VMOVDQA32Z256rrkz_REV, + VMOVDQA32Zmr, + VMOVDQA32Zmrk, + VMOVDQA32Zrm, + VMOVDQA32Zrmk, + VMOVDQA32Zrmkz, + VMOVDQA32Zrr, + VMOVDQA32Zrr_REV, + VMOVDQA32Zrrk, + VMOVDQA32Zrrk_REV, + VMOVDQA32Zrrkz, + VMOVDQA32Zrrkz_REV, + VMOVDQA64Z128mr, + VMOVDQA64Z128mrk, + VMOVDQA64Z128rm, + VMOVDQA64Z128rmk, + VMOVDQA64Z128rmkz, + VMOVDQA64Z128rr, + VMOVDQA64Z128rr_REV, + VMOVDQA64Z128rrk, + VMOVDQA64Z128rrk_REV, + VMOVDQA64Z128rrkz, + VMOVDQA64Z128rrkz_REV, + VMOVDQA64Z256mr, + VMOVDQA64Z256mrk, + VMOVDQA64Z256rm, + VMOVDQA64Z256rmk, + VMOVDQA64Z256rmkz, + VMOVDQA64Z256rr, + VMOVDQA64Z256rr_REV, + VMOVDQA64Z256rrk, + VMOVDQA64Z256rrk_REV, + VMOVDQA64Z256rrkz, + VMOVDQA64Z256rrkz_REV, + VMOVDQA64Zmr, + VMOVDQA64Zmrk, + VMOVDQA64Zrm, + VMOVDQA64Zrmk, + VMOVDQA64Zrmkz, + VMOVDQA64Zrr, + VMOVDQA64Zrr_REV, + VMOVDQA64Zrrk, + VMOVDQA64Zrrk_REV, + VMOVDQA64Zrrkz, + VMOVDQA64Zrrkz_REV, + VMOVDQAYmr, + VMOVDQAYrm, + VMOVDQAYrr, + VMOVDQAYrr_REV, + VMOVDQAmr, + VMOVDQArm, + VMOVDQArr, + VMOVDQArr_REV, + VMOVDQU16Z128mr, + VMOVDQU16Z128mrk, + VMOVDQU16Z128rm, + VMOVDQU16Z128rmk, + VMOVDQU16Z128rmkz, + VMOVDQU16Z128rr, + VMOVDQU16Z128rr_REV, + VMOVDQU16Z128rrk, + VMOVDQU16Z128rrk_REV, + VMOVDQU16Z128rrkz, + VMOVDQU16Z128rrkz_REV, + VMOVDQU16Z256mr, + VMOVDQU16Z256mrk, + VMOVDQU16Z256rm, + VMOVDQU16Z256rmk, + VMOVDQU16Z256rmkz, + VMOVDQU16Z256rr, + VMOVDQU16Z256rr_REV, + VMOVDQU16Z256rrk, + VMOVDQU16Z256rrk_REV, + VMOVDQU16Z256rrkz, + VMOVDQU16Z256rrkz_REV, + VMOVDQU16Zmr, + VMOVDQU16Zmrk, + VMOVDQU16Zrm, + VMOVDQU16Zrmk, + VMOVDQU16Zrmkz, + VMOVDQU16Zrr, + VMOVDQU16Zrr_REV, + VMOVDQU16Zrrk, + VMOVDQU16Zrrk_REV, + VMOVDQU16Zrrkz, + VMOVDQU16Zrrkz_REV, + VMOVDQU32Z128mr, + VMOVDQU32Z128mrk, + VMOVDQU32Z128rm, + VMOVDQU32Z128rmk, + VMOVDQU32Z128rmkz, + VMOVDQU32Z128rr, + VMOVDQU32Z128rr_REV, + VMOVDQU32Z128rrk, + VMOVDQU32Z128rrk_REV, + VMOVDQU32Z128rrkz, + VMOVDQU32Z128rrkz_REV, + VMOVDQU32Z256mr, + VMOVDQU32Z256mrk, + VMOVDQU32Z256rm, + VMOVDQU32Z256rmk, + VMOVDQU32Z256rmkz, + VMOVDQU32Z256rr, + VMOVDQU32Z256rr_REV, + VMOVDQU32Z256rrk, + VMOVDQU32Z256rrk_REV, + VMOVDQU32Z256rrkz, + VMOVDQU32Z256rrkz_REV, + VMOVDQU32Zmr, + VMOVDQU32Zmrk, + VMOVDQU32Zrm, + VMOVDQU32Zrmk, + VMOVDQU32Zrmkz, + VMOVDQU32Zrr, + VMOVDQU32Zrr_REV, + VMOVDQU32Zrrk, + VMOVDQU32Zrrk_REV, + VMOVDQU32Zrrkz, + VMOVDQU32Zrrkz_REV, + VMOVDQU64Z128mr, + VMOVDQU64Z128mrk, + VMOVDQU64Z128rm, + VMOVDQU64Z128rmk, + VMOVDQU64Z128rmkz, + VMOVDQU64Z128rr, + VMOVDQU64Z128rr_REV, + VMOVDQU64Z128rrk, + VMOVDQU64Z128rrk_REV, + VMOVDQU64Z128rrkz, + VMOVDQU64Z128rrkz_REV, + VMOVDQU64Z256mr, + VMOVDQU64Z256mrk, + VMOVDQU64Z256rm, + VMOVDQU64Z256rmk, + VMOVDQU64Z256rmkz, + VMOVDQU64Z256rr, + VMOVDQU64Z256rr_REV, + VMOVDQU64Z256rrk, + VMOVDQU64Z256rrk_REV, + VMOVDQU64Z256rrkz, + VMOVDQU64Z256rrkz_REV, + VMOVDQU64Zmr, + VMOVDQU64Zmrk, + VMOVDQU64Zrm, + VMOVDQU64Zrmk, + VMOVDQU64Zrmkz, + VMOVDQU64Zrr, + VMOVDQU64Zrr_REV, + VMOVDQU64Zrrk, + VMOVDQU64Zrrk_REV, + VMOVDQU64Zrrkz, + VMOVDQU64Zrrkz_REV, + VMOVDQU8Z128mr, + VMOVDQU8Z128mrk, + VMOVDQU8Z128rm, + VMOVDQU8Z128rmk, + VMOVDQU8Z128rmkz, + VMOVDQU8Z128rr, + VMOVDQU8Z128rr_REV, + VMOVDQU8Z128rrk, + VMOVDQU8Z128rrk_REV, + VMOVDQU8Z128rrkz, + VMOVDQU8Z128rrkz_REV, + VMOVDQU8Z256mr, + VMOVDQU8Z256mrk, + VMOVDQU8Z256rm, + VMOVDQU8Z256rmk, + VMOVDQU8Z256rmkz, + VMOVDQU8Z256rr, + VMOVDQU8Z256rr_REV, + VMOVDQU8Z256rrk, + VMOVDQU8Z256rrk_REV, + VMOVDQU8Z256rrkz, + VMOVDQU8Z256rrkz_REV, + VMOVDQU8Zmr, + VMOVDQU8Zmrk, + VMOVDQU8Zrm, + VMOVDQU8Zrmk, + VMOVDQU8Zrmkz, + VMOVDQU8Zrr, + VMOVDQU8Zrr_REV, + VMOVDQU8Zrrk, + VMOVDQU8Zrrk_REV, + VMOVDQU8Zrrkz, + VMOVDQU8Zrrkz_REV, + VMOVDQUYmr, + VMOVDQUYrm, + VMOVDQUYrr, + VMOVDQUYrr_REV, + VMOVDQUmr, + VMOVDQUrm, + VMOVDQUrr, + VMOVDQUrr_REV, + VMOVHLPSZrr, + VMOVHLPSrr, + VMOVHPDZ128mr, + VMOVHPDZ128rm, + VMOVHPDmr, + VMOVHPDrm, + VMOVHPSZ128mr, + VMOVHPSZ128rm, + VMOVHPSmr, + VMOVHPSrm, + VMOVLHPSZrr, + VMOVLHPSrr, + VMOVLPDZ128mr, + VMOVLPDZ128rm, + VMOVLPDmr, + VMOVLPDrm, + VMOVLPSZ128mr, + VMOVLPSZ128rm, + VMOVLPSmr, + VMOVLPSrm, + VMOVMSKPDYrr, + VMOVMSKPDrr, + VMOVMSKPSYrr, + VMOVMSKPSrr, + VMOVNTDQAYrm, + VMOVNTDQAZ128rm, + VMOVNTDQAZ256rm, + VMOVNTDQAZrm, + VMOVNTDQArm, + VMOVNTDQYmr, + VMOVNTDQZ128mr, + VMOVNTDQZ256mr, + VMOVNTDQZmr, + VMOVNTDQmr, + VMOVNTPDYmr, + VMOVNTPDZ128mr, + VMOVNTPDZ256mr, + VMOVNTPDZmr, + VMOVNTPDmr, + VMOVNTPSYmr, + VMOVNTPSZ128mr, + VMOVNTPSZ256mr, + VMOVNTPSZmr, + VMOVNTPSmr, + VMOVPDI2DIZmr, + VMOVPDI2DIZrr, + VMOVPDI2DImr, + VMOVPDI2DIrr, + VMOVPQI2QIZmr, + VMOVPQI2QIZrr, + VMOVPQI2QImr, + VMOVPQI2QIrr, + VMOVPQIto64Zmr, + VMOVPQIto64Zrr, + VMOVPQIto64mr, + VMOVPQIto64rr, + VMOVQI2PQIZrm, + VMOVQI2PQIrm, + VMOVRSBZ128m, + VMOVRSBZ128mk, + VMOVRSBZ128mkz, + VMOVRSBZ256m, + VMOVRSBZ256mk, + VMOVRSBZ256mkz, + VMOVRSBZm, + VMOVRSBZmk, + VMOVRSBZmkz, + VMOVRSDZ128m, + VMOVRSDZ128mk, + VMOVRSDZ128mkz, + VMOVRSDZ256m, + VMOVRSDZ256mk, + VMOVRSDZ256mkz, + VMOVRSDZm, + VMOVRSDZmk, + VMOVRSDZmkz, + VMOVRSQZ128m, + VMOVRSQZ128mk, + VMOVRSQZ128mkz, + VMOVRSQZ256m, + VMOVRSQZ256mk, + VMOVRSQZ256mkz, + VMOVRSQZm, + VMOVRSQZmk, + VMOVRSQZmkz, + VMOVRSWZ128m, + VMOVRSWZ128mk, + VMOVRSWZ128mkz, + VMOVRSWZ256m, + VMOVRSWZ256mk, + VMOVRSWZ256mkz, + VMOVRSWZm, + VMOVRSWZmk, + VMOVRSWZmkz, + VMOVSDZmr, + VMOVSDZmrk, + VMOVSDZrm, + VMOVSDZrm_alt, + VMOVSDZrmk, + VMOVSDZrmkz, + VMOVSDZrr, + VMOVSDZrr_REV, + VMOVSDZrrk, + VMOVSDZrrk_REV, + VMOVSDZrrkz, + VMOVSDZrrkz_REV, + VMOVSDmr, + VMOVSDrm, + VMOVSDrm_alt, + VMOVSDrr, + VMOVSDrr_REV, + VMOVSDto64Zrr, + VMOVSDto64rr, + VMOVSH2Wrr, + VMOVSHDUPYrm, + VMOVSHDUPYrr, + VMOVSHDUPZ128rm, + VMOVSHDUPZ128rmk, + VMOVSHDUPZ128rmkz, + VMOVSHDUPZ128rr, + VMOVSHDUPZ128rrk, + VMOVSHDUPZ128rrkz, + VMOVSHDUPZ256rm, + VMOVSHDUPZ256rmk, + VMOVSHDUPZ256rmkz, + VMOVSHDUPZ256rr, + VMOVSHDUPZ256rrk, + VMOVSHDUPZ256rrkz, + VMOVSHDUPZrm, + VMOVSHDUPZrmk, + VMOVSHDUPZrmkz, + VMOVSHDUPZrr, + VMOVSHDUPZrrk, + VMOVSHDUPZrrkz, + VMOVSHDUPrm, + VMOVSHDUPrr, + VMOVSHZmr, + VMOVSHZmrk, + VMOVSHZrm, + VMOVSHZrm_alt, + VMOVSHZrmk, + VMOVSHZrmkz, + VMOVSHZrr, + VMOVSHZrr_REV, + VMOVSHZrrk, + VMOVSHZrrk_REV, + VMOVSHZrrkz, + VMOVSHZrrkz_REV, + VMOVSHtoW64rr, + VMOVSLDUPYrm, + VMOVSLDUPYrr, + VMOVSLDUPZ128rm, + VMOVSLDUPZ128rmk, + VMOVSLDUPZ128rmkz, + VMOVSLDUPZ128rr, + VMOVSLDUPZ128rrk, + VMOVSLDUPZ128rrkz, + VMOVSLDUPZ256rm, + VMOVSLDUPZ256rmk, + VMOVSLDUPZ256rmkz, + VMOVSLDUPZ256rr, + VMOVSLDUPZ256rrk, + VMOVSLDUPZ256rrkz, + VMOVSLDUPZrm, + VMOVSLDUPZrmk, + VMOVSLDUPZrmkz, + VMOVSLDUPZrr, + VMOVSLDUPZrrk, + VMOVSLDUPZrrkz, + VMOVSLDUPrm, + VMOVSLDUPrr, + VMOVSS2DIZrr, + VMOVSS2DIrr, + VMOVSSZmr, + VMOVSSZmrk, + VMOVSSZrm, + VMOVSSZrm_alt, + VMOVSSZrmk, + VMOVSSZrmkz, + VMOVSSZrr, + VMOVSSZrr_REV, + VMOVSSZrrk, + VMOVSSZrrk_REV, + VMOVSSZrrkz, + VMOVSSZrrkz_REV, + VMOVSSmr, + VMOVSSrm, + VMOVSSrm_alt, + VMOVSSrr, + VMOVSSrr_REV, + VMOVUPDYmr, + VMOVUPDYrm, + VMOVUPDYrr, + VMOVUPDYrr_REV, + VMOVUPDZ128mr, + VMOVUPDZ128mrk, + VMOVUPDZ128rm, + VMOVUPDZ128rmk, + VMOVUPDZ128rmkz, + VMOVUPDZ128rr, + VMOVUPDZ128rr_REV, + VMOVUPDZ128rrk, + VMOVUPDZ128rrk_REV, + VMOVUPDZ128rrkz, + VMOVUPDZ128rrkz_REV, + VMOVUPDZ256mr, + VMOVUPDZ256mrk, + VMOVUPDZ256rm, + VMOVUPDZ256rmk, + VMOVUPDZ256rmkz, + VMOVUPDZ256rr, + VMOVUPDZ256rr_REV, + VMOVUPDZ256rrk, + VMOVUPDZ256rrk_REV, + VMOVUPDZ256rrkz, + VMOVUPDZ256rrkz_REV, + VMOVUPDZmr, + VMOVUPDZmrk, + VMOVUPDZrm, + VMOVUPDZrmk, + VMOVUPDZrmkz, + VMOVUPDZrr, + VMOVUPDZrr_REV, + VMOVUPDZrrk, + VMOVUPDZrrk_REV, + VMOVUPDZrrkz, + VMOVUPDZrrkz_REV, + VMOVUPDmr, + VMOVUPDrm, + VMOVUPDrr, + VMOVUPDrr_REV, + VMOVUPSYmr, + VMOVUPSYrm, + VMOVUPSYrr, + VMOVUPSYrr_REV, + VMOVUPSZ128mr, + VMOVUPSZ128mrk, + VMOVUPSZ128rm, + VMOVUPSZ128rmk, + VMOVUPSZ128rmkz, + VMOVUPSZ128rr, + VMOVUPSZ128rr_REV, + VMOVUPSZ128rrk, + VMOVUPSZ128rrk_REV, + VMOVUPSZ128rrkz, + VMOVUPSZ128rrkz_REV, + VMOVUPSZ256mr, + VMOVUPSZ256mrk, + VMOVUPSZ256rm, + VMOVUPSZ256rmk, + VMOVUPSZ256rmkz, + VMOVUPSZ256rr, + VMOVUPSZ256rr_REV, + VMOVUPSZ256rrk, + VMOVUPSZ256rrk_REV, + VMOVUPSZ256rrkz, + VMOVUPSZ256rrkz_REV, + VMOVUPSZmr, + VMOVUPSZmrk, + VMOVUPSZrm, + VMOVUPSZrmk, + VMOVUPSZrmkz, + VMOVUPSZrr, + VMOVUPSZrr_REV, + VMOVUPSZrrk, + VMOVUPSZrrk_REV, + VMOVUPSZrrkz, + VMOVUPSZrrkz_REV, + VMOVUPSmr, + VMOVUPSrm, + VMOVUPSrr, + VMOVUPSrr_REV, + VMOVW2SHrr, + VMOVW64toSHrr, + VMOVWmr, + VMOVWrm, + VMOVZPDILo2PDIZmr, + VMOVZPDILo2PDIZrm, + VMOVZPDILo2PDIZrr, + VMOVZPDILo2PDIZrr2, + VMOVZPQILo2PQIZrr, + VMOVZPQILo2PQIrr, + VMOVZPWILo2PWIZmr, + VMOVZPWILo2PWIZrm, + VMOVZPWILo2PWIZrr, + VMOVZPWILo2PWIZrr2, + VMPSADBWYrmi, + VMPSADBWYrri, + VMPSADBWZ128rmi, + VMPSADBWZ128rmik, + VMPSADBWZ128rmikz, + VMPSADBWZ128rri, + VMPSADBWZ128rrik, + VMPSADBWZ128rrikz, + VMPSADBWZ256rmi, + VMPSADBWZ256rmik, + VMPSADBWZ256rmikz, + VMPSADBWZ256rri, + VMPSADBWZ256rrik, + VMPSADBWZ256rrikz, + VMPSADBWZrmi, + VMPSADBWZrmik, + VMPSADBWZrmikz, + VMPSADBWZrri, + VMPSADBWZrrik, + VMPSADBWZrrikz, + VMPSADBWrmi, + VMPSADBWrri, + VMPTRLDm, + VMPTRSTm, + VMREAD32mr, + VMREAD32rr, + VMREAD64mr, + VMREAD64rr, + VMRESUME, + VMRUN32, + VMRUN64, + VMSAVE32, + VMSAVE64, + VMULBF16Z128rm, + VMULBF16Z128rmb, + VMULBF16Z128rmbk, + VMULBF16Z128rmbkz, + VMULBF16Z128rmk, + VMULBF16Z128rmkz, + VMULBF16Z128rr, + VMULBF16Z128rrk, + VMULBF16Z128rrkz, + VMULBF16Z256rm, + VMULBF16Z256rmb, + VMULBF16Z256rmbk, + VMULBF16Z256rmbkz, + VMULBF16Z256rmk, + VMULBF16Z256rmkz, + VMULBF16Z256rr, + VMULBF16Z256rrk, + VMULBF16Z256rrkz, + VMULBF16Zrm, + VMULBF16Zrmb, + VMULBF16Zrmbk, + VMULBF16Zrmbkz, + VMULBF16Zrmk, + VMULBF16Zrmkz, + VMULBF16Zrr, + VMULBF16Zrrk, + VMULBF16Zrrkz, + VMULPDYrm, + VMULPDYrr, + VMULPDZ128rm, + VMULPDZ128rmb, + VMULPDZ128rmbk, + VMULPDZ128rmbkz, + VMULPDZ128rmk, + VMULPDZ128rmkz, + VMULPDZ128rr, + VMULPDZ128rrk, + VMULPDZ128rrkz, + VMULPDZ256rm, + VMULPDZ256rmb, + VMULPDZ256rmbk, + VMULPDZ256rmbkz, + VMULPDZ256rmk, + VMULPDZ256rmkz, + VMULPDZ256rr, + VMULPDZ256rrk, + VMULPDZ256rrkz, + VMULPDZrm, + VMULPDZrmb, + VMULPDZrmbk, + VMULPDZrmbkz, + VMULPDZrmk, + VMULPDZrmkz, + VMULPDZrr, + VMULPDZrrb, + VMULPDZrrbk, + VMULPDZrrbkz, + VMULPDZrrk, + VMULPDZrrkz, + VMULPDrm, + VMULPDrr, + VMULPHZ128rm, + VMULPHZ128rmb, + VMULPHZ128rmbk, + VMULPHZ128rmbkz, + VMULPHZ128rmk, + VMULPHZ128rmkz, + VMULPHZ128rr, + VMULPHZ128rrk, + VMULPHZ128rrkz, + VMULPHZ256rm, + VMULPHZ256rmb, + VMULPHZ256rmbk, + VMULPHZ256rmbkz, + VMULPHZ256rmk, + VMULPHZ256rmkz, + VMULPHZ256rr, + VMULPHZ256rrk, + VMULPHZ256rrkz, + VMULPHZrm, + VMULPHZrmb, + VMULPHZrmbk, + VMULPHZrmbkz, + VMULPHZrmk, + VMULPHZrmkz, + VMULPHZrr, + VMULPHZrrb, + VMULPHZrrbk, + VMULPHZrrbkz, + VMULPHZrrk, + VMULPHZrrkz, + VMULPSYrm, + VMULPSYrr, + VMULPSZ128rm, + VMULPSZ128rmb, + VMULPSZ128rmbk, + VMULPSZ128rmbkz, + VMULPSZ128rmk, + VMULPSZ128rmkz, + VMULPSZ128rr, + VMULPSZ128rrk, + VMULPSZ128rrkz, + VMULPSZ256rm, + VMULPSZ256rmb, + VMULPSZ256rmbk, + VMULPSZ256rmbkz, + VMULPSZ256rmk, + VMULPSZ256rmkz, + VMULPSZ256rr, + VMULPSZ256rrk, + VMULPSZ256rrkz, + VMULPSZrm, + VMULPSZrmb, + VMULPSZrmbk, + VMULPSZrmbkz, + VMULPSZrmk, + VMULPSZrmkz, + VMULPSZrr, + VMULPSZrrb, + VMULPSZrrbk, + VMULPSZrrbkz, + VMULPSZrrk, + VMULPSZrrkz, + VMULPSrm, + VMULPSrr, + VMULSDZrm, + VMULSDZrm_Int, + VMULSDZrmk_Int, + VMULSDZrmkz_Int, + VMULSDZrr, + VMULSDZrr_Int, + VMULSDZrrb_Int, + VMULSDZrrbk_Int, + VMULSDZrrbkz_Int, + VMULSDZrrk_Int, + VMULSDZrrkz_Int, + VMULSDrm, + VMULSDrm_Int, + VMULSDrr, + VMULSDrr_Int, + VMULSHZrm, + VMULSHZrm_Int, + VMULSHZrmk_Int, + VMULSHZrmkz_Int, + VMULSHZrr, + VMULSHZrr_Int, + VMULSHZrrb_Int, + VMULSHZrrbk_Int, + VMULSHZrrbkz_Int, + VMULSHZrrk_Int, + VMULSHZrrkz_Int, + VMULSSZrm, + VMULSSZrm_Int, + VMULSSZrmk_Int, + VMULSSZrmkz_Int, + VMULSSZrr, + VMULSSZrr_Int, + VMULSSZrrb_Int, + VMULSSZrrbk_Int, + VMULSSZrrbkz_Int, + VMULSSZrrk_Int, + VMULSSZrrkz_Int, + VMULSSrm, + VMULSSrm_Int, + VMULSSrr, + VMULSSrr_Int, + VMWRITE32rm, + VMWRITE32rr, + VMWRITE64rm, + VMWRITE64rr, + VMXOFF, + VMXON, + VORPDYrm, + VORPDYrr, + VORPDZ128rm, + VORPDZ128rmb, + VORPDZ128rmbk, + VORPDZ128rmbkz, + VORPDZ128rmk, + VORPDZ128rmkz, + VORPDZ128rr, + VORPDZ128rrk, + VORPDZ128rrkz, + VORPDZ256rm, + VORPDZ256rmb, + VORPDZ256rmbk, + VORPDZ256rmbkz, + VORPDZ256rmk, + VORPDZ256rmkz, + VORPDZ256rr, + VORPDZ256rrk, + VORPDZ256rrkz, + VORPDZrm, + VORPDZrmb, + VORPDZrmbk, + VORPDZrmbkz, + VORPDZrmk, + VORPDZrmkz, + VORPDZrr, + VORPDZrrk, + VORPDZrrkz, + VORPDrm, + VORPDrr, + VORPSYrm, + VORPSYrr, + VORPSZ128rm, + VORPSZ128rmb, + VORPSZ128rmbk, + VORPSZ128rmbkz, + VORPSZ128rmk, + VORPSZ128rmkz, + VORPSZ128rr, + VORPSZ128rrk, + VORPSZ128rrkz, + VORPSZ256rm, + VORPSZ256rmb, + VORPSZ256rmbk, + VORPSZ256rmbkz, + VORPSZ256rmk, + VORPSZ256rmkz, + VORPSZ256rr, + VORPSZ256rrk, + VORPSZ256rrkz, + VORPSZrm, + VORPSZrmb, + VORPSZrmbk, + VORPSZrmbkz, + VORPSZrmk, + VORPSZrmkz, + VORPSZrr, + VORPSZrrk, + VORPSZrrkz, + VORPSrm, + VORPSrr, + VP2INTERSECTDZ128rm, + VP2INTERSECTDZ128rmb, + VP2INTERSECTDZ128rr, + VP2INTERSECTDZ256rm, + VP2INTERSECTDZ256rmb, + VP2INTERSECTDZ256rr, + VP2INTERSECTDZrm, + VP2INTERSECTDZrmb, + VP2INTERSECTDZrr, + VP2INTERSECTQZ128rm, + VP2INTERSECTQZ128rmb, + VP2INTERSECTQZ128rr, + VP2INTERSECTQZ256rm, + VP2INTERSECTQZ256rmb, + VP2INTERSECTQZ256rr, + VP2INTERSECTQZrm, + VP2INTERSECTQZrmb, + VP2INTERSECTQZrr, + VP4DPWSSDSrm, + VP4DPWSSDSrmk, + VP4DPWSSDSrmkz, + VP4DPWSSDrm, + VP4DPWSSDrmk, + VP4DPWSSDrmkz, + VPABSBYrm, + VPABSBYrr, + VPABSBZ128rm, + VPABSBZ128rmk, + VPABSBZ128rmkz, + VPABSBZ128rr, + VPABSBZ128rrk, + VPABSBZ128rrkz, + VPABSBZ256rm, + VPABSBZ256rmk, + VPABSBZ256rmkz, + VPABSBZ256rr, + VPABSBZ256rrk, + VPABSBZ256rrkz, + VPABSBZrm, + VPABSBZrmk, + VPABSBZrmkz, + VPABSBZrr, + VPABSBZrrk, + VPABSBZrrkz, + VPABSBrm, + VPABSBrr, + VPABSDYrm, + VPABSDYrr, + VPABSDZ128rm, + VPABSDZ128rmb, + VPABSDZ128rmbk, + VPABSDZ128rmbkz, + VPABSDZ128rmk, + VPABSDZ128rmkz, + VPABSDZ128rr, + VPABSDZ128rrk, + VPABSDZ128rrkz, + VPABSDZ256rm, + VPABSDZ256rmb, + VPABSDZ256rmbk, + VPABSDZ256rmbkz, + VPABSDZ256rmk, + VPABSDZ256rmkz, + VPABSDZ256rr, + VPABSDZ256rrk, + VPABSDZ256rrkz, + VPABSDZrm, + VPABSDZrmb, + VPABSDZrmbk, + VPABSDZrmbkz, + VPABSDZrmk, + VPABSDZrmkz, + VPABSDZrr, + VPABSDZrrk, + VPABSDZrrkz, + VPABSDrm, + VPABSDrr, + VPABSQZ128rm, + VPABSQZ128rmb, + VPABSQZ128rmbk, + VPABSQZ128rmbkz, + VPABSQZ128rmk, + VPABSQZ128rmkz, + VPABSQZ128rr, + VPABSQZ128rrk, + VPABSQZ128rrkz, + VPABSQZ256rm, + VPABSQZ256rmb, + VPABSQZ256rmbk, + VPABSQZ256rmbkz, + VPABSQZ256rmk, + VPABSQZ256rmkz, + VPABSQZ256rr, + VPABSQZ256rrk, + VPABSQZ256rrkz, + VPABSQZrm, + VPABSQZrmb, + VPABSQZrmbk, + VPABSQZrmbkz, + VPABSQZrmk, + VPABSQZrmkz, + VPABSQZrr, + VPABSQZrrk, + VPABSQZrrkz, + VPABSWYrm, + VPABSWYrr, + VPABSWZ128rm, + VPABSWZ128rmk, + VPABSWZ128rmkz, + VPABSWZ128rr, + VPABSWZ128rrk, + VPABSWZ128rrkz, + VPABSWZ256rm, + VPABSWZ256rmk, + VPABSWZ256rmkz, + VPABSWZ256rr, + VPABSWZ256rrk, + VPABSWZ256rrkz, + VPABSWZrm, + VPABSWZrmk, + VPABSWZrmkz, + VPABSWZrr, + VPABSWZrrk, + VPABSWZrrkz, + VPABSWrm, + VPABSWrr, + VPACKSSDWYrm, + VPACKSSDWYrr, + VPACKSSDWZ128rm, + VPACKSSDWZ128rmb, + VPACKSSDWZ128rmbk, + VPACKSSDWZ128rmbkz, + VPACKSSDWZ128rmk, + VPACKSSDWZ128rmkz, + VPACKSSDWZ128rr, + VPACKSSDWZ128rrk, + VPACKSSDWZ128rrkz, + VPACKSSDWZ256rm, + VPACKSSDWZ256rmb, + VPACKSSDWZ256rmbk, + VPACKSSDWZ256rmbkz, + VPACKSSDWZ256rmk, + VPACKSSDWZ256rmkz, + VPACKSSDWZ256rr, + VPACKSSDWZ256rrk, + VPACKSSDWZ256rrkz, + VPACKSSDWZrm, + VPACKSSDWZrmb, + VPACKSSDWZrmbk, + VPACKSSDWZrmbkz, + VPACKSSDWZrmk, + VPACKSSDWZrmkz, + VPACKSSDWZrr, + VPACKSSDWZrrk, + VPACKSSDWZrrkz, + VPACKSSDWrm, + VPACKSSDWrr, + VPACKSSWBYrm, + VPACKSSWBYrr, + VPACKSSWBZ128rm, + VPACKSSWBZ128rmk, + VPACKSSWBZ128rmkz, + VPACKSSWBZ128rr, + VPACKSSWBZ128rrk, + VPACKSSWBZ128rrkz, + VPACKSSWBZ256rm, + VPACKSSWBZ256rmk, + VPACKSSWBZ256rmkz, + VPACKSSWBZ256rr, + VPACKSSWBZ256rrk, + VPACKSSWBZ256rrkz, + VPACKSSWBZrm, + VPACKSSWBZrmk, + VPACKSSWBZrmkz, + VPACKSSWBZrr, + VPACKSSWBZrrk, + VPACKSSWBZrrkz, + VPACKSSWBrm, + VPACKSSWBrr, + VPACKUSDWYrm, + VPACKUSDWYrr, + VPACKUSDWZ128rm, + VPACKUSDWZ128rmb, + VPACKUSDWZ128rmbk, + VPACKUSDWZ128rmbkz, + VPACKUSDWZ128rmk, + VPACKUSDWZ128rmkz, + VPACKUSDWZ128rr, + VPACKUSDWZ128rrk, + VPACKUSDWZ128rrkz, + VPACKUSDWZ256rm, + VPACKUSDWZ256rmb, + VPACKUSDWZ256rmbk, + VPACKUSDWZ256rmbkz, + VPACKUSDWZ256rmk, + VPACKUSDWZ256rmkz, + VPACKUSDWZ256rr, + VPACKUSDWZ256rrk, + VPACKUSDWZ256rrkz, + VPACKUSDWZrm, + VPACKUSDWZrmb, + VPACKUSDWZrmbk, + VPACKUSDWZrmbkz, + VPACKUSDWZrmk, + VPACKUSDWZrmkz, + VPACKUSDWZrr, + VPACKUSDWZrrk, + VPACKUSDWZrrkz, + VPACKUSDWrm, + VPACKUSDWrr, + VPACKUSWBYrm, + VPACKUSWBYrr, + VPACKUSWBZ128rm, + VPACKUSWBZ128rmk, + VPACKUSWBZ128rmkz, + VPACKUSWBZ128rr, + VPACKUSWBZ128rrk, + VPACKUSWBZ128rrkz, + VPACKUSWBZ256rm, + VPACKUSWBZ256rmk, + VPACKUSWBZ256rmkz, + VPACKUSWBZ256rr, + VPACKUSWBZ256rrk, + VPACKUSWBZ256rrkz, + VPACKUSWBZrm, + VPACKUSWBZrmk, + VPACKUSWBZrmkz, + VPACKUSWBZrr, + VPACKUSWBZrrk, + VPACKUSWBZrrkz, + VPACKUSWBrm, + VPACKUSWBrr, + VPADDBYrm, + VPADDBYrr, + VPADDBZ128rm, + VPADDBZ128rmk, + VPADDBZ128rmkz, + VPADDBZ128rr, + VPADDBZ128rrk, + VPADDBZ128rrkz, + VPADDBZ256rm, + VPADDBZ256rmk, + VPADDBZ256rmkz, + VPADDBZ256rr, + VPADDBZ256rrk, + VPADDBZ256rrkz, + VPADDBZrm, + VPADDBZrmk, + VPADDBZrmkz, + VPADDBZrr, + VPADDBZrrk, + VPADDBZrrkz, + VPADDBrm, + VPADDBrr, + VPADDDYrm, + VPADDDYrr, + VPADDDZ128rm, + VPADDDZ128rmb, + VPADDDZ128rmbk, + VPADDDZ128rmbkz, + VPADDDZ128rmk, + VPADDDZ128rmkz, + VPADDDZ128rr, + VPADDDZ128rrk, + VPADDDZ128rrkz, + VPADDDZ256rm, + VPADDDZ256rmb, + VPADDDZ256rmbk, + VPADDDZ256rmbkz, + VPADDDZ256rmk, + VPADDDZ256rmkz, + VPADDDZ256rr, + VPADDDZ256rrk, + VPADDDZ256rrkz, + VPADDDZrm, + VPADDDZrmb, + VPADDDZrmbk, + VPADDDZrmbkz, + VPADDDZrmk, + VPADDDZrmkz, + VPADDDZrr, + VPADDDZrrk, + VPADDDZrrkz, + VPADDDrm, + VPADDDrr, + VPADDQYrm, + VPADDQYrr, + VPADDQZ128rm, + VPADDQZ128rmb, + VPADDQZ128rmbk, + VPADDQZ128rmbkz, + VPADDQZ128rmk, + VPADDQZ128rmkz, + VPADDQZ128rr, + VPADDQZ128rrk, + VPADDQZ128rrkz, + VPADDQZ256rm, + VPADDQZ256rmb, + VPADDQZ256rmbk, + VPADDQZ256rmbkz, + VPADDQZ256rmk, + VPADDQZ256rmkz, + VPADDQZ256rr, + VPADDQZ256rrk, + VPADDQZ256rrkz, + VPADDQZrm, + VPADDQZrmb, + VPADDQZrmbk, + VPADDQZrmbkz, + VPADDQZrmk, + VPADDQZrmkz, + VPADDQZrr, + VPADDQZrrk, + VPADDQZrrkz, + VPADDQrm, + VPADDQrr, + VPADDSBYrm, + VPADDSBYrr, + VPADDSBZ128rm, + VPADDSBZ128rmk, + VPADDSBZ128rmkz, + VPADDSBZ128rr, + VPADDSBZ128rrk, + VPADDSBZ128rrkz, + VPADDSBZ256rm, + VPADDSBZ256rmk, + VPADDSBZ256rmkz, + VPADDSBZ256rr, + VPADDSBZ256rrk, + VPADDSBZ256rrkz, + VPADDSBZrm, + VPADDSBZrmk, + VPADDSBZrmkz, + VPADDSBZrr, + VPADDSBZrrk, + VPADDSBZrrkz, + VPADDSBrm, + VPADDSBrr, + VPADDSWYrm, + VPADDSWYrr, + VPADDSWZ128rm, + VPADDSWZ128rmk, + VPADDSWZ128rmkz, + VPADDSWZ128rr, + VPADDSWZ128rrk, + VPADDSWZ128rrkz, + VPADDSWZ256rm, + VPADDSWZ256rmk, + VPADDSWZ256rmkz, + VPADDSWZ256rr, + VPADDSWZ256rrk, + VPADDSWZ256rrkz, + VPADDSWZrm, + VPADDSWZrmk, + VPADDSWZrmkz, + VPADDSWZrr, + VPADDSWZrrk, + VPADDSWZrrkz, + VPADDSWrm, + VPADDSWrr, + VPADDUSBYrm, + VPADDUSBYrr, + VPADDUSBZ128rm, + VPADDUSBZ128rmk, + VPADDUSBZ128rmkz, + VPADDUSBZ128rr, + VPADDUSBZ128rrk, + VPADDUSBZ128rrkz, + VPADDUSBZ256rm, + VPADDUSBZ256rmk, + VPADDUSBZ256rmkz, + VPADDUSBZ256rr, + VPADDUSBZ256rrk, + VPADDUSBZ256rrkz, + VPADDUSBZrm, + VPADDUSBZrmk, + VPADDUSBZrmkz, + VPADDUSBZrr, + VPADDUSBZrrk, + VPADDUSBZrrkz, + VPADDUSBrm, + VPADDUSBrr, + VPADDUSWYrm, + VPADDUSWYrr, + VPADDUSWZ128rm, + VPADDUSWZ128rmk, + VPADDUSWZ128rmkz, + VPADDUSWZ128rr, + VPADDUSWZ128rrk, + VPADDUSWZ128rrkz, + VPADDUSWZ256rm, + VPADDUSWZ256rmk, + VPADDUSWZ256rmkz, + VPADDUSWZ256rr, + VPADDUSWZ256rrk, + VPADDUSWZ256rrkz, + VPADDUSWZrm, + VPADDUSWZrmk, + VPADDUSWZrmkz, + VPADDUSWZrr, + VPADDUSWZrrk, + VPADDUSWZrrkz, + VPADDUSWrm, + VPADDUSWrr, + VPADDWYrm, + VPADDWYrr, + VPADDWZ128rm, + VPADDWZ128rmk, + VPADDWZ128rmkz, + VPADDWZ128rr, + VPADDWZ128rrk, + VPADDWZ128rrkz, + VPADDWZ256rm, + VPADDWZ256rmk, + VPADDWZ256rmkz, + VPADDWZ256rr, + VPADDWZ256rrk, + VPADDWZ256rrkz, + VPADDWZrm, + VPADDWZrmk, + VPADDWZrmkz, + VPADDWZrr, + VPADDWZrrk, + VPADDWZrrkz, + VPADDWrm, + VPADDWrr, + VPALIGNRYrmi, + VPALIGNRYrri, + VPALIGNRZ128rmi, + VPALIGNRZ128rmik, + VPALIGNRZ128rmikz, + VPALIGNRZ128rri, + VPALIGNRZ128rrik, + VPALIGNRZ128rrikz, + VPALIGNRZ256rmi, + VPALIGNRZ256rmik, + VPALIGNRZ256rmikz, + VPALIGNRZ256rri, + VPALIGNRZ256rrik, + VPALIGNRZ256rrikz, + VPALIGNRZrmi, + VPALIGNRZrmik, + VPALIGNRZrmikz, + VPALIGNRZrri, + VPALIGNRZrrik, + VPALIGNRZrrikz, + VPALIGNRrmi, + VPALIGNRrri, + VPANDDZ128rm, + VPANDDZ128rmb, + VPANDDZ128rmbk, + VPANDDZ128rmbkz, + VPANDDZ128rmk, + VPANDDZ128rmkz, + VPANDDZ128rr, + VPANDDZ128rrk, + VPANDDZ128rrkz, + VPANDDZ256rm, + VPANDDZ256rmb, + VPANDDZ256rmbk, + VPANDDZ256rmbkz, + VPANDDZ256rmk, + VPANDDZ256rmkz, + VPANDDZ256rr, + VPANDDZ256rrk, + VPANDDZ256rrkz, + VPANDDZrm, + VPANDDZrmb, + VPANDDZrmbk, + VPANDDZrmbkz, + VPANDDZrmk, + VPANDDZrmkz, + VPANDDZrr, + VPANDDZrrk, + VPANDDZrrkz, + VPANDNDZ128rm, + VPANDNDZ128rmb, + VPANDNDZ128rmbk, + VPANDNDZ128rmbkz, + VPANDNDZ128rmk, + VPANDNDZ128rmkz, + VPANDNDZ128rr, + VPANDNDZ128rrk, + VPANDNDZ128rrkz, + VPANDNDZ256rm, + VPANDNDZ256rmb, + VPANDNDZ256rmbk, + VPANDNDZ256rmbkz, + VPANDNDZ256rmk, + VPANDNDZ256rmkz, + VPANDNDZ256rr, + VPANDNDZ256rrk, + VPANDNDZ256rrkz, + VPANDNDZrm, + VPANDNDZrmb, + VPANDNDZrmbk, + VPANDNDZrmbkz, + VPANDNDZrmk, + VPANDNDZrmkz, + VPANDNDZrr, + VPANDNDZrrk, + VPANDNDZrrkz, + VPANDNQZ128rm, + VPANDNQZ128rmb, + VPANDNQZ128rmbk, + VPANDNQZ128rmbkz, + VPANDNQZ128rmk, + VPANDNQZ128rmkz, + VPANDNQZ128rr, + VPANDNQZ128rrk, + VPANDNQZ128rrkz, + VPANDNQZ256rm, + VPANDNQZ256rmb, + VPANDNQZ256rmbk, + VPANDNQZ256rmbkz, + VPANDNQZ256rmk, + VPANDNQZ256rmkz, + VPANDNQZ256rr, + VPANDNQZ256rrk, + VPANDNQZ256rrkz, + VPANDNQZrm, + VPANDNQZrmb, + VPANDNQZrmbk, + VPANDNQZrmbkz, + VPANDNQZrmk, + VPANDNQZrmkz, + VPANDNQZrr, + VPANDNQZrrk, + VPANDNQZrrkz, + VPANDNYrm, + VPANDNYrr, + VPANDNrm, + VPANDNrr, + VPANDQZ128rm, + VPANDQZ128rmb, + VPANDQZ128rmbk, + VPANDQZ128rmbkz, + VPANDQZ128rmk, + VPANDQZ128rmkz, + VPANDQZ128rr, + VPANDQZ128rrk, + VPANDQZ128rrkz, + VPANDQZ256rm, + VPANDQZ256rmb, + VPANDQZ256rmbk, + VPANDQZ256rmbkz, + VPANDQZ256rmk, + VPANDQZ256rmkz, + VPANDQZ256rr, + VPANDQZ256rrk, + VPANDQZ256rrkz, + VPANDQZrm, + VPANDQZrmb, + VPANDQZrmbk, + VPANDQZrmbkz, + VPANDQZrmk, + VPANDQZrmkz, + VPANDQZrr, + VPANDQZrrk, + VPANDQZrrkz, + VPANDYrm, + VPANDYrr, + VPANDrm, + VPANDrr, + VPAVGBYrm, + VPAVGBYrr, + VPAVGBZ128rm, + VPAVGBZ128rmk, + VPAVGBZ128rmkz, + VPAVGBZ128rr, + VPAVGBZ128rrk, + VPAVGBZ128rrkz, + VPAVGBZ256rm, + VPAVGBZ256rmk, + VPAVGBZ256rmkz, + VPAVGBZ256rr, + VPAVGBZ256rrk, + VPAVGBZ256rrkz, + VPAVGBZrm, + VPAVGBZrmk, + VPAVGBZrmkz, + VPAVGBZrr, + VPAVGBZrrk, + VPAVGBZrrkz, + VPAVGBrm, + VPAVGBrr, + VPAVGWYrm, + VPAVGWYrr, + VPAVGWZ128rm, + VPAVGWZ128rmk, + VPAVGWZ128rmkz, + VPAVGWZ128rr, + VPAVGWZ128rrk, + VPAVGWZ128rrkz, + VPAVGWZ256rm, + VPAVGWZ256rmk, + VPAVGWZ256rmkz, + VPAVGWZ256rr, + VPAVGWZ256rrk, + VPAVGWZ256rrkz, + VPAVGWZrm, + VPAVGWZrmk, + VPAVGWZrmkz, + VPAVGWZrr, + VPAVGWZrrk, + VPAVGWZrrkz, + VPAVGWrm, + VPAVGWrr, + VPBLENDDYrmi, + VPBLENDDYrri, + VPBLENDDrmi, + VPBLENDDrri, + VPBLENDMBZ128rm, + VPBLENDMBZ128rmk, + VPBLENDMBZ128rmkz, + VPBLENDMBZ128rr, + VPBLENDMBZ128rrk, + VPBLENDMBZ128rrkz, + VPBLENDMBZ256rm, + VPBLENDMBZ256rmk, + VPBLENDMBZ256rmkz, + VPBLENDMBZ256rr, + VPBLENDMBZ256rrk, + VPBLENDMBZ256rrkz, + VPBLENDMBZrm, + VPBLENDMBZrmk, + VPBLENDMBZrmkz, + VPBLENDMBZrr, + VPBLENDMBZrrk, + VPBLENDMBZrrkz, + VPBLENDMDZ128rm, + VPBLENDMDZ128rmb, + VPBLENDMDZ128rmbk, + VPBLENDMDZ128rmbkz, + VPBLENDMDZ128rmk, + VPBLENDMDZ128rmkz, + VPBLENDMDZ128rr, + VPBLENDMDZ128rrk, + VPBLENDMDZ128rrkz, + VPBLENDMDZ256rm, + VPBLENDMDZ256rmb, + VPBLENDMDZ256rmbk, + VPBLENDMDZ256rmbkz, + VPBLENDMDZ256rmk, + VPBLENDMDZ256rmkz, + VPBLENDMDZ256rr, + VPBLENDMDZ256rrk, + VPBLENDMDZ256rrkz, + VPBLENDMDZrm, + VPBLENDMDZrmb, + VPBLENDMDZrmbk, + VPBLENDMDZrmbkz, + VPBLENDMDZrmk, + VPBLENDMDZrmkz, + VPBLENDMDZrr, + VPBLENDMDZrrk, + VPBLENDMDZrrkz, + VPBLENDMQZ128rm, + VPBLENDMQZ128rmb, + VPBLENDMQZ128rmbk, + VPBLENDMQZ128rmbkz, + VPBLENDMQZ128rmk, + VPBLENDMQZ128rmkz, + VPBLENDMQZ128rr, + VPBLENDMQZ128rrk, + VPBLENDMQZ128rrkz, + VPBLENDMQZ256rm, + VPBLENDMQZ256rmb, + VPBLENDMQZ256rmbk, + VPBLENDMQZ256rmbkz, + VPBLENDMQZ256rmk, + VPBLENDMQZ256rmkz, + VPBLENDMQZ256rr, + VPBLENDMQZ256rrk, + VPBLENDMQZ256rrkz, + VPBLENDMQZrm, + VPBLENDMQZrmb, + VPBLENDMQZrmbk, + VPBLENDMQZrmbkz, + VPBLENDMQZrmk, + VPBLENDMQZrmkz, + VPBLENDMQZrr, + VPBLENDMQZrrk, + VPBLENDMQZrrkz, + VPBLENDMWZ128rm, + VPBLENDMWZ128rmk, + VPBLENDMWZ128rmkz, + VPBLENDMWZ128rr, + VPBLENDMWZ128rrk, + VPBLENDMWZ128rrkz, + VPBLENDMWZ256rm, + VPBLENDMWZ256rmk, + VPBLENDMWZ256rmkz, + VPBLENDMWZ256rr, + VPBLENDMWZ256rrk, + VPBLENDMWZ256rrkz, + VPBLENDMWZrm, + VPBLENDMWZrmk, + VPBLENDMWZrmkz, + VPBLENDMWZrr, + VPBLENDMWZrrk, + VPBLENDMWZrrkz, + VPBLENDVBYrmr, + VPBLENDVBYrrr, + VPBLENDVBrmr, + VPBLENDVBrrr, + VPBLENDWYrmi, + VPBLENDWYrri, + VPBLENDWrmi, + VPBLENDWrri, + VPBROADCASTBYrm, + VPBROADCASTBYrr, + VPBROADCASTBZ128rm, + VPBROADCASTBZ128rmk, + VPBROADCASTBZ128rmkz, + VPBROADCASTBZ128rr, + VPBROADCASTBZ128rrk, + VPBROADCASTBZ128rrkz, + VPBROADCASTBZ256rm, + VPBROADCASTBZ256rmk, + VPBROADCASTBZ256rmkz, + VPBROADCASTBZ256rr, + VPBROADCASTBZ256rrk, + VPBROADCASTBZ256rrkz, + VPBROADCASTBZrm, + VPBROADCASTBZrmk, + VPBROADCASTBZrmkz, + VPBROADCASTBZrr, + VPBROADCASTBZrrk, + VPBROADCASTBZrrkz, + VPBROADCASTBrZ128rr, + VPBROADCASTBrZ128rrk, + VPBROADCASTBrZ128rrkz, + VPBROADCASTBrZ256rr, + VPBROADCASTBrZ256rrk, + VPBROADCASTBrZ256rrkz, + VPBROADCASTBrZrr, + VPBROADCASTBrZrrk, + VPBROADCASTBrZrrkz, + VPBROADCASTBrm, + VPBROADCASTBrr, + VPBROADCASTDYrm, + VPBROADCASTDYrr, + VPBROADCASTDZ128rm, + VPBROADCASTDZ128rmk, + VPBROADCASTDZ128rmkz, + VPBROADCASTDZ128rr, + VPBROADCASTDZ128rrk, + VPBROADCASTDZ128rrkz, + VPBROADCASTDZ256rm, + VPBROADCASTDZ256rmk, + VPBROADCASTDZ256rmkz, + VPBROADCASTDZ256rr, + VPBROADCASTDZ256rrk, + VPBROADCASTDZ256rrkz, + VPBROADCASTDZrm, + VPBROADCASTDZrmk, + VPBROADCASTDZrmkz, + VPBROADCASTDZrr, + VPBROADCASTDZrrk, + VPBROADCASTDZrrkz, + VPBROADCASTDrZ128rr, + VPBROADCASTDrZ128rrk, + VPBROADCASTDrZ128rrkz, + VPBROADCASTDrZ256rr, + VPBROADCASTDrZ256rrk, + VPBROADCASTDrZ256rrkz, + VPBROADCASTDrZrr, + VPBROADCASTDrZrrk, + VPBROADCASTDrZrrkz, + VPBROADCASTDrm, + VPBROADCASTDrr, + VPBROADCASTMB2QZ128rr, + VPBROADCASTMB2QZ256rr, + VPBROADCASTMB2QZrr, + VPBROADCASTMW2DZ128rr, + VPBROADCASTMW2DZ256rr, + VPBROADCASTMW2DZrr, + VPBROADCASTQYrm, + VPBROADCASTQYrr, + VPBROADCASTQZ128rm, + VPBROADCASTQZ128rmk, + VPBROADCASTQZ128rmkz, + VPBROADCASTQZ128rr, + VPBROADCASTQZ128rrk, + VPBROADCASTQZ128rrkz, + VPBROADCASTQZ256rm, + VPBROADCASTQZ256rmk, + VPBROADCASTQZ256rmkz, + VPBROADCASTQZ256rr, + VPBROADCASTQZ256rrk, + VPBROADCASTQZ256rrkz, + VPBROADCASTQZrm, + VPBROADCASTQZrmk, + VPBROADCASTQZrmkz, + VPBROADCASTQZrr, + VPBROADCASTQZrrk, + VPBROADCASTQZrrkz, + VPBROADCASTQrZ128rr, + VPBROADCASTQrZ128rrk, + VPBROADCASTQrZ128rrkz, + VPBROADCASTQrZ256rr, + VPBROADCASTQrZ256rrk, + VPBROADCASTQrZ256rrkz, + VPBROADCASTQrZrr, + VPBROADCASTQrZrrk, + VPBROADCASTQrZrrkz, + VPBROADCASTQrm, + VPBROADCASTQrr, + VPBROADCASTWYrm, + VPBROADCASTWYrr, + VPBROADCASTWZ128rm, + VPBROADCASTWZ128rmk, + VPBROADCASTWZ128rmkz, + VPBROADCASTWZ128rr, + VPBROADCASTWZ128rrk, + VPBROADCASTWZ128rrkz, + VPBROADCASTWZ256rm, + VPBROADCASTWZ256rmk, + VPBROADCASTWZ256rmkz, + VPBROADCASTWZ256rr, + VPBROADCASTWZ256rrk, + VPBROADCASTWZ256rrkz, + VPBROADCASTWZrm, + VPBROADCASTWZrmk, + VPBROADCASTWZrmkz, + VPBROADCASTWZrr, + VPBROADCASTWZrrk, + VPBROADCASTWZrrkz, + VPBROADCASTWrZ128rr, + VPBROADCASTWrZ128rrk, + VPBROADCASTWrZ128rrkz, + VPBROADCASTWrZ256rr, + VPBROADCASTWrZ256rrk, + VPBROADCASTWrZ256rrkz, + VPBROADCASTWrZrr, + VPBROADCASTWrZrrk, + VPBROADCASTWrZrrkz, + VPBROADCASTWrm, + VPBROADCASTWrr, + VPCLMULQDQYrmi, + VPCLMULQDQYrri, + VPCLMULQDQZ128rmi, + VPCLMULQDQZ128rri, + VPCLMULQDQZ256rmi, + VPCLMULQDQZ256rri, + VPCLMULQDQZrmi, + VPCLMULQDQZrri, + VPCLMULQDQrmi, + VPCLMULQDQrri, + VPCMOVYrmr, + VPCMOVYrrm, + VPCMOVYrrr, + VPCMOVYrrr_REV, + VPCMOVrmr, + VPCMOVrrm, + VPCMOVrrr, + VPCMOVrrr_REV, + VPCMPBZ128rmi, + VPCMPBZ128rmik, + VPCMPBZ128rri, + VPCMPBZ128rrik, + VPCMPBZ256rmi, + VPCMPBZ256rmik, + VPCMPBZ256rri, + VPCMPBZ256rrik, + VPCMPBZrmi, + VPCMPBZrmik, + VPCMPBZrri, + VPCMPBZrrik, + VPCMPDZ128rmbi, + VPCMPDZ128rmbik, + VPCMPDZ128rmi, + VPCMPDZ128rmik, + VPCMPDZ128rri, + VPCMPDZ128rrik, + VPCMPDZ256rmbi, + VPCMPDZ256rmbik, + VPCMPDZ256rmi, + VPCMPDZ256rmik, + VPCMPDZ256rri, + VPCMPDZ256rrik, + VPCMPDZrmbi, + VPCMPDZrmbik, + VPCMPDZrmi, + VPCMPDZrmik, + VPCMPDZrri, + VPCMPDZrrik, + VPCMPEQBYrm, + VPCMPEQBYrr, + VPCMPEQBZ128rm, + VPCMPEQBZ128rmk, + VPCMPEQBZ128rr, + VPCMPEQBZ128rrk, + VPCMPEQBZ256rm, + VPCMPEQBZ256rmk, + VPCMPEQBZ256rr, + VPCMPEQBZ256rrk, + VPCMPEQBZrm, + VPCMPEQBZrmk, + VPCMPEQBZrr, + VPCMPEQBZrrk, + VPCMPEQBrm, + VPCMPEQBrr, + VPCMPEQDYrm, + VPCMPEQDYrr, + VPCMPEQDZ128rm, + VPCMPEQDZ128rmb, + VPCMPEQDZ128rmbk, + VPCMPEQDZ128rmk, + VPCMPEQDZ128rr, + VPCMPEQDZ128rrk, + VPCMPEQDZ256rm, + VPCMPEQDZ256rmb, + VPCMPEQDZ256rmbk, + VPCMPEQDZ256rmk, + VPCMPEQDZ256rr, + VPCMPEQDZ256rrk, + VPCMPEQDZrm, + VPCMPEQDZrmb, + VPCMPEQDZrmbk, + VPCMPEQDZrmk, + VPCMPEQDZrr, + VPCMPEQDZrrk, + VPCMPEQDrm, + VPCMPEQDrr, + VPCMPEQQYrm, + VPCMPEQQYrr, + VPCMPEQQZ128rm, + VPCMPEQQZ128rmb, + VPCMPEQQZ128rmbk, + VPCMPEQQZ128rmk, + VPCMPEQQZ128rr, + VPCMPEQQZ128rrk, + VPCMPEQQZ256rm, + VPCMPEQQZ256rmb, + VPCMPEQQZ256rmbk, + VPCMPEQQZ256rmk, + VPCMPEQQZ256rr, + VPCMPEQQZ256rrk, + VPCMPEQQZrm, + VPCMPEQQZrmb, + VPCMPEQQZrmbk, + VPCMPEQQZrmk, + VPCMPEQQZrr, + VPCMPEQQZrrk, + VPCMPEQQrm, + VPCMPEQQrr, + VPCMPEQWYrm, + VPCMPEQWYrr, + VPCMPEQWZ128rm, + VPCMPEQWZ128rmk, + VPCMPEQWZ128rr, + VPCMPEQWZ128rrk, + VPCMPEQWZ256rm, + VPCMPEQWZ256rmk, + VPCMPEQWZ256rr, + VPCMPEQWZ256rrk, + VPCMPEQWZrm, + VPCMPEQWZrmk, + VPCMPEQWZrr, + VPCMPEQWZrrk, + VPCMPEQWrm, + VPCMPEQWrr, + VPCMPESTRIrmi, + VPCMPESTRIrri, + VPCMPESTRMrmi, + VPCMPESTRMrri, + VPCMPGTBYrm, + VPCMPGTBYrr, + VPCMPGTBZ128rm, + VPCMPGTBZ128rmk, + VPCMPGTBZ128rr, + VPCMPGTBZ128rrk, + VPCMPGTBZ256rm, + VPCMPGTBZ256rmk, + VPCMPGTBZ256rr, + VPCMPGTBZ256rrk, + VPCMPGTBZrm, + VPCMPGTBZrmk, + VPCMPGTBZrr, + VPCMPGTBZrrk, + VPCMPGTBrm, + VPCMPGTBrr, + VPCMPGTDYrm, + VPCMPGTDYrr, + VPCMPGTDZ128rm, + VPCMPGTDZ128rmb, + VPCMPGTDZ128rmbk, + VPCMPGTDZ128rmk, + VPCMPGTDZ128rr, + VPCMPGTDZ128rrk, + VPCMPGTDZ256rm, + VPCMPGTDZ256rmb, + VPCMPGTDZ256rmbk, + VPCMPGTDZ256rmk, + VPCMPGTDZ256rr, + VPCMPGTDZ256rrk, + VPCMPGTDZrm, + VPCMPGTDZrmb, + VPCMPGTDZrmbk, + VPCMPGTDZrmk, + VPCMPGTDZrr, + VPCMPGTDZrrk, + VPCMPGTDrm, + VPCMPGTDrr, + VPCMPGTQYrm, + VPCMPGTQYrr, + VPCMPGTQZ128rm, + VPCMPGTQZ128rmb, + VPCMPGTQZ128rmbk, + VPCMPGTQZ128rmk, + VPCMPGTQZ128rr, + VPCMPGTQZ128rrk, + VPCMPGTQZ256rm, + VPCMPGTQZ256rmb, + VPCMPGTQZ256rmbk, + VPCMPGTQZ256rmk, + VPCMPGTQZ256rr, + VPCMPGTQZ256rrk, + VPCMPGTQZrm, + VPCMPGTQZrmb, + VPCMPGTQZrmbk, + VPCMPGTQZrmk, + VPCMPGTQZrr, + VPCMPGTQZrrk, + VPCMPGTQrm, + VPCMPGTQrr, + VPCMPGTWYrm, + VPCMPGTWYrr, + VPCMPGTWZ128rm, + VPCMPGTWZ128rmk, + VPCMPGTWZ128rr, + VPCMPGTWZ128rrk, + VPCMPGTWZ256rm, + VPCMPGTWZ256rmk, + VPCMPGTWZ256rr, + VPCMPGTWZ256rrk, + VPCMPGTWZrm, + VPCMPGTWZrmk, + VPCMPGTWZrr, + VPCMPGTWZrrk, + VPCMPGTWrm, + VPCMPGTWrr, + VPCMPISTRIrmi, + VPCMPISTRIrri, + VPCMPISTRMrmi, + VPCMPISTRMrri, + VPCMPQZ128rmbi, + VPCMPQZ128rmbik, + VPCMPQZ128rmi, + VPCMPQZ128rmik, + VPCMPQZ128rri, + VPCMPQZ128rrik, + VPCMPQZ256rmbi, + VPCMPQZ256rmbik, + VPCMPQZ256rmi, + VPCMPQZ256rmik, + VPCMPQZ256rri, + VPCMPQZ256rrik, + VPCMPQZrmbi, + VPCMPQZrmbik, + VPCMPQZrmi, + VPCMPQZrmik, + VPCMPQZrri, + VPCMPQZrrik, + VPCMPUBZ128rmi, + VPCMPUBZ128rmik, + VPCMPUBZ128rri, + VPCMPUBZ128rrik, + VPCMPUBZ256rmi, + VPCMPUBZ256rmik, + VPCMPUBZ256rri, + VPCMPUBZ256rrik, + VPCMPUBZrmi, + VPCMPUBZrmik, + VPCMPUBZrri, + VPCMPUBZrrik, + VPCMPUDZ128rmbi, + VPCMPUDZ128rmbik, + VPCMPUDZ128rmi, + VPCMPUDZ128rmik, + VPCMPUDZ128rri, + VPCMPUDZ128rrik, + VPCMPUDZ256rmbi, + VPCMPUDZ256rmbik, + VPCMPUDZ256rmi, + VPCMPUDZ256rmik, + VPCMPUDZ256rri, + VPCMPUDZ256rrik, + VPCMPUDZrmbi, + VPCMPUDZrmbik, + VPCMPUDZrmi, + VPCMPUDZrmik, + VPCMPUDZrri, + VPCMPUDZrrik, + VPCMPUQZ128rmbi, + VPCMPUQZ128rmbik, + VPCMPUQZ128rmi, + VPCMPUQZ128rmik, + VPCMPUQZ128rri, + VPCMPUQZ128rrik, + VPCMPUQZ256rmbi, + VPCMPUQZ256rmbik, + VPCMPUQZ256rmi, + VPCMPUQZ256rmik, + VPCMPUQZ256rri, + VPCMPUQZ256rrik, + VPCMPUQZrmbi, + VPCMPUQZrmbik, + VPCMPUQZrmi, + VPCMPUQZrmik, + VPCMPUQZrri, + VPCMPUQZrrik, + VPCMPUWZ128rmi, + VPCMPUWZ128rmik, + VPCMPUWZ128rri, + VPCMPUWZ128rrik, + VPCMPUWZ256rmi, + VPCMPUWZ256rmik, + VPCMPUWZ256rri, + VPCMPUWZ256rrik, + VPCMPUWZrmi, + VPCMPUWZrmik, + VPCMPUWZrri, + VPCMPUWZrrik, + VPCMPWZ128rmi, + VPCMPWZ128rmik, + VPCMPWZ128rri, + VPCMPWZ128rrik, + VPCMPWZ256rmi, + VPCMPWZ256rmik, + VPCMPWZ256rri, + VPCMPWZ256rrik, + VPCMPWZrmi, + VPCMPWZrmik, + VPCMPWZrri, + VPCMPWZrrik, + VPCOMBmi, + VPCOMBri, + VPCOMDmi, + VPCOMDri, + VPCOMPRESSBZ128mr, + VPCOMPRESSBZ128mrk, + VPCOMPRESSBZ128rr, + VPCOMPRESSBZ128rrk, + VPCOMPRESSBZ128rrkz, + VPCOMPRESSBZ256mr, + VPCOMPRESSBZ256mrk, + VPCOMPRESSBZ256rr, + VPCOMPRESSBZ256rrk, + VPCOMPRESSBZ256rrkz, + VPCOMPRESSBZmr, + VPCOMPRESSBZmrk, + VPCOMPRESSBZrr, + VPCOMPRESSBZrrk, + VPCOMPRESSBZrrkz, + VPCOMPRESSDZ128mr, + VPCOMPRESSDZ128mrk, + VPCOMPRESSDZ128rr, + VPCOMPRESSDZ128rrk, + VPCOMPRESSDZ128rrkz, + VPCOMPRESSDZ256mr, + VPCOMPRESSDZ256mrk, + VPCOMPRESSDZ256rr, + VPCOMPRESSDZ256rrk, + VPCOMPRESSDZ256rrkz, + VPCOMPRESSDZmr, + VPCOMPRESSDZmrk, + VPCOMPRESSDZrr, + VPCOMPRESSDZrrk, + VPCOMPRESSDZrrkz, + VPCOMPRESSQZ128mr, + VPCOMPRESSQZ128mrk, + VPCOMPRESSQZ128rr, + VPCOMPRESSQZ128rrk, + VPCOMPRESSQZ128rrkz, + VPCOMPRESSQZ256mr, + VPCOMPRESSQZ256mrk, + VPCOMPRESSQZ256rr, + VPCOMPRESSQZ256rrk, + VPCOMPRESSQZ256rrkz, + VPCOMPRESSQZmr, + VPCOMPRESSQZmrk, + VPCOMPRESSQZrr, + VPCOMPRESSQZrrk, + VPCOMPRESSQZrrkz, + VPCOMPRESSWZ128mr, + VPCOMPRESSWZ128mrk, + VPCOMPRESSWZ128rr, + VPCOMPRESSWZ128rrk, + VPCOMPRESSWZ128rrkz, + VPCOMPRESSWZ256mr, + VPCOMPRESSWZ256mrk, + VPCOMPRESSWZ256rr, + VPCOMPRESSWZ256rrk, + VPCOMPRESSWZ256rrkz, + VPCOMPRESSWZmr, + VPCOMPRESSWZmrk, + VPCOMPRESSWZrr, + VPCOMPRESSWZrrk, + VPCOMPRESSWZrrkz, + VPCOMQmi, + VPCOMQri, + VPCOMUBmi, + VPCOMUBri, + VPCOMUDmi, + VPCOMUDri, + VPCOMUQmi, + VPCOMUQri, + VPCOMUWmi, + VPCOMUWri, + VPCOMWmi, + VPCOMWri, + VPCONFLICTDZ128rm, + VPCONFLICTDZ128rmb, + VPCONFLICTDZ128rmbk, + VPCONFLICTDZ128rmbkz, + VPCONFLICTDZ128rmk, + VPCONFLICTDZ128rmkz, + VPCONFLICTDZ128rr, + VPCONFLICTDZ128rrk, + VPCONFLICTDZ128rrkz, + VPCONFLICTDZ256rm, + VPCONFLICTDZ256rmb, + VPCONFLICTDZ256rmbk, + VPCONFLICTDZ256rmbkz, + VPCONFLICTDZ256rmk, + VPCONFLICTDZ256rmkz, + VPCONFLICTDZ256rr, + VPCONFLICTDZ256rrk, + VPCONFLICTDZ256rrkz, + VPCONFLICTDZrm, + VPCONFLICTDZrmb, + VPCONFLICTDZrmbk, + VPCONFLICTDZrmbkz, + VPCONFLICTDZrmk, + VPCONFLICTDZrmkz, + VPCONFLICTDZrr, + VPCONFLICTDZrrk, + VPCONFLICTDZrrkz, + VPCONFLICTQZ128rm, + VPCONFLICTQZ128rmb, + VPCONFLICTQZ128rmbk, + VPCONFLICTQZ128rmbkz, + VPCONFLICTQZ128rmk, + VPCONFLICTQZ128rmkz, + VPCONFLICTQZ128rr, + VPCONFLICTQZ128rrk, + VPCONFLICTQZ128rrkz, + VPCONFLICTQZ256rm, + VPCONFLICTQZ256rmb, + VPCONFLICTQZ256rmbk, + VPCONFLICTQZ256rmbkz, + VPCONFLICTQZ256rmk, + VPCONFLICTQZ256rmkz, + VPCONFLICTQZ256rr, + VPCONFLICTQZ256rrk, + VPCONFLICTQZ256rrkz, + VPCONFLICTQZrm, + VPCONFLICTQZrmb, + VPCONFLICTQZrmbk, + VPCONFLICTQZrmbkz, + VPCONFLICTQZrmk, + VPCONFLICTQZrmkz, + VPCONFLICTQZrr, + VPCONFLICTQZrrk, + VPCONFLICTQZrrkz, + VPDPBSSDSYrm, + VPDPBSSDSYrr, + VPDPBSSDSZ128rm, + VPDPBSSDSZ128rmb, + VPDPBSSDSZ128rmbk, + VPDPBSSDSZ128rmbkz, + VPDPBSSDSZ128rmk, + VPDPBSSDSZ128rmkz, + VPDPBSSDSZ128rr, + VPDPBSSDSZ128rrk, + VPDPBSSDSZ128rrkz, + VPDPBSSDSZ256rm, + VPDPBSSDSZ256rmb, + VPDPBSSDSZ256rmbk, + VPDPBSSDSZ256rmbkz, + VPDPBSSDSZ256rmk, + VPDPBSSDSZ256rmkz, + VPDPBSSDSZ256rr, + VPDPBSSDSZ256rrk, + VPDPBSSDSZ256rrkz, + VPDPBSSDSZrm, + VPDPBSSDSZrmb, + VPDPBSSDSZrmbk, + VPDPBSSDSZrmbkz, + VPDPBSSDSZrmk, + VPDPBSSDSZrmkz, + VPDPBSSDSZrr, + VPDPBSSDSZrrk, + VPDPBSSDSZrrkz, + VPDPBSSDSrm, + VPDPBSSDSrr, + VPDPBSSDYrm, + VPDPBSSDYrr, + VPDPBSSDZ128rm, + VPDPBSSDZ128rmb, + VPDPBSSDZ128rmbk, + VPDPBSSDZ128rmbkz, + VPDPBSSDZ128rmk, + VPDPBSSDZ128rmkz, + VPDPBSSDZ128rr, + VPDPBSSDZ128rrk, + VPDPBSSDZ128rrkz, + VPDPBSSDZ256rm, + VPDPBSSDZ256rmb, + VPDPBSSDZ256rmbk, + VPDPBSSDZ256rmbkz, + VPDPBSSDZ256rmk, + VPDPBSSDZ256rmkz, + VPDPBSSDZ256rr, + VPDPBSSDZ256rrk, + VPDPBSSDZ256rrkz, + VPDPBSSDZrm, + VPDPBSSDZrmb, + VPDPBSSDZrmbk, + VPDPBSSDZrmbkz, + VPDPBSSDZrmk, + VPDPBSSDZrmkz, + VPDPBSSDZrr, + VPDPBSSDZrrk, + VPDPBSSDZrrkz, + VPDPBSSDrm, + VPDPBSSDrr, + VPDPBSUDSYrm, + VPDPBSUDSYrr, + VPDPBSUDSZ128rm, + VPDPBSUDSZ128rmb, + VPDPBSUDSZ128rmbk, + VPDPBSUDSZ128rmbkz, + VPDPBSUDSZ128rmk, + VPDPBSUDSZ128rmkz, + VPDPBSUDSZ128rr, + VPDPBSUDSZ128rrk, + VPDPBSUDSZ128rrkz, + VPDPBSUDSZ256rm, + VPDPBSUDSZ256rmb, + VPDPBSUDSZ256rmbk, + VPDPBSUDSZ256rmbkz, + VPDPBSUDSZ256rmk, + VPDPBSUDSZ256rmkz, + VPDPBSUDSZ256rr, + VPDPBSUDSZ256rrk, + VPDPBSUDSZ256rrkz, + VPDPBSUDSZrm, + VPDPBSUDSZrmb, + VPDPBSUDSZrmbk, + VPDPBSUDSZrmbkz, + VPDPBSUDSZrmk, + VPDPBSUDSZrmkz, + VPDPBSUDSZrr, + VPDPBSUDSZrrk, + VPDPBSUDSZrrkz, + VPDPBSUDSrm, + VPDPBSUDSrr, + VPDPBSUDYrm, + VPDPBSUDYrr, + VPDPBSUDZ128rm, + VPDPBSUDZ128rmb, + VPDPBSUDZ128rmbk, + VPDPBSUDZ128rmbkz, + VPDPBSUDZ128rmk, + VPDPBSUDZ128rmkz, + VPDPBSUDZ128rr, + VPDPBSUDZ128rrk, + VPDPBSUDZ128rrkz, + VPDPBSUDZ256rm, + VPDPBSUDZ256rmb, + VPDPBSUDZ256rmbk, + VPDPBSUDZ256rmbkz, + VPDPBSUDZ256rmk, + VPDPBSUDZ256rmkz, + VPDPBSUDZ256rr, + VPDPBSUDZ256rrk, + VPDPBSUDZ256rrkz, + VPDPBSUDZrm, + VPDPBSUDZrmb, + VPDPBSUDZrmbk, + VPDPBSUDZrmbkz, + VPDPBSUDZrmk, + VPDPBSUDZrmkz, + VPDPBSUDZrr, + VPDPBSUDZrrk, + VPDPBSUDZrrkz, + VPDPBSUDrm, + VPDPBSUDrr, + VPDPBUSDSYrm, + VPDPBUSDSYrr, + VPDPBUSDSZ128rm, + VPDPBUSDSZ128rmb, + VPDPBUSDSZ128rmbk, + VPDPBUSDSZ128rmbkz, + VPDPBUSDSZ128rmk, + VPDPBUSDSZ128rmkz, + VPDPBUSDSZ128rr, + VPDPBUSDSZ128rrk, + VPDPBUSDSZ128rrkz, + VPDPBUSDSZ256rm, + VPDPBUSDSZ256rmb, + VPDPBUSDSZ256rmbk, + VPDPBUSDSZ256rmbkz, + VPDPBUSDSZ256rmk, + VPDPBUSDSZ256rmkz, + VPDPBUSDSZ256rr, + VPDPBUSDSZ256rrk, + VPDPBUSDSZ256rrkz, + VPDPBUSDSZrm, + VPDPBUSDSZrmb, + VPDPBUSDSZrmbk, + VPDPBUSDSZrmbkz, + VPDPBUSDSZrmk, + VPDPBUSDSZrmkz, + VPDPBUSDSZrr, + VPDPBUSDSZrrk, + VPDPBUSDSZrrkz, + VPDPBUSDSrm, + VPDPBUSDSrr, + VPDPBUSDYrm, + VPDPBUSDYrr, + VPDPBUSDZ128rm, + VPDPBUSDZ128rmb, + VPDPBUSDZ128rmbk, + VPDPBUSDZ128rmbkz, + VPDPBUSDZ128rmk, + VPDPBUSDZ128rmkz, + VPDPBUSDZ128rr, + VPDPBUSDZ128rrk, + VPDPBUSDZ128rrkz, + VPDPBUSDZ256rm, + VPDPBUSDZ256rmb, + VPDPBUSDZ256rmbk, + VPDPBUSDZ256rmbkz, + VPDPBUSDZ256rmk, + VPDPBUSDZ256rmkz, + VPDPBUSDZ256rr, + VPDPBUSDZ256rrk, + VPDPBUSDZ256rrkz, + VPDPBUSDZrm, + VPDPBUSDZrmb, + VPDPBUSDZrmbk, + VPDPBUSDZrmbkz, + VPDPBUSDZrmk, + VPDPBUSDZrmkz, + VPDPBUSDZrr, + VPDPBUSDZrrk, + VPDPBUSDZrrkz, + VPDPBUSDrm, + VPDPBUSDrr, + VPDPBUUDSYrm, + VPDPBUUDSYrr, + VPDPBUUDSZ128rm, + VPDPBUUDSZ128rmb, + VPDPBUUDSZ128rmbk, + VPDPBUUDSZ128rmbkz, + VPDPBUUDSZ128rmk, + VPDPBUUDSZ128rmkz, + VPDPBUUDSZ128rr, + VPDPBUUDSZ128rrk, + VPDPBUUDSZ128rrkz, + VPDPBUUDSZ256rm, + VPDPBUUDSZ256rmb, + VPDPBUUDSZ256rmbk, + VPDPBUUDSZ256rmbkz, + VPDPBUUDSZ256rmk, + VPDPBUUDSZ256rmkz, + VPDPBUUDSZ256rr, + VPDPBUUDSZ256rrk, + VPDPBUUDSZ256rrkz, + VPDPBUUDSZrm, + VPDPBUUDSZrmb, + VPDPBUUDSZrmbk, + VPDPBUUDSZrmbkz, + VPDPBUUDSZrmk, + VPDPBUUDSZrmkz, + VPDPBUUDSZrr, + VPDPBUUDSZrrk, + VPDPBUUDSZrrkz, + VPDPBUUDSrm, + VPDPBUUDSrr, + VPDPBUUDYrm, + VPDPBUUDYrr, + VPDPBUUDZ128rm, + VPDPBUUDZ128rmb, + VPDPBUUDZ128rmbk, + VPDPBUUDZ128rmbkz, + VPDPBUUDZ128rmk, + VPDPBUUDZ128rmkz, + VPDPBUUDZ128rr, + VPDPBUUDZ128rrk, + VPDPBUUDZ128rrkz, + VPDPBUUDZ256rm, + VPDPBUUDZ256rmb, + VPDPBUUDZ256rmbk, + VPDPBUUDZ256rmbkz, + VPDPBUUDZ256rmk, + VPDPBUUDZ256rmkz, + VPDPBUUDZ256rr, + VPDPBUUDZ256rrk, + VPDPBUUDZ256rrkz, + VPDPBUUDZrm, + VPDPBUUDZrmb, + VPDPBUUDZrmbk, + VPDPBUUDZrmbkz, + VPDPBUUDZrmk, + VPDPBUUDZrmkz, + VPDPBUUDZrr, + VPDPBUUDZrrk, + VPDPBUUDZrrkz, + VPDPBUUDrm, + VPDPBUUDrr, + VPDPWSSDSYrm, + VPDPWSSDSYrr, + VPDPWSSDSZ128rm, + VPDPWSSDSZ128rmb, + VPDPWSSDSZ128rmbk, + VPDPWSSDSZ128rmbkz, + VPDPWSSDSZ128rmk, + VPDPWSSDSZ128rmkz, + VPDPWSSDSZ128rr, + VPDPWSSDSZ128rrk, + VPDPWSSDSZ128rrkz, + VPDPWSSDSZ256rm, + VPDPWSSDSZ256rmb, + VPDPWSSDSZ256rmbk, + VPDPWSSDSZ256rmbkz, + VPDPWSSDSZ256rmk, + VPDPWSSDSZ256rmkz, + VPDPWSSDSZ256rr, + VPDPWSSDSZ256rrk, + VPDPWSSDSZ256rrkz, + VPDPWSSDSZrm, + VPDPWSSDSZrmb, + VPDPWSSDSZrmbk, + VPDPWSSDSZrmbkz, + VPDPWSSDSZrmk, + VPDPWSSDSZrmkz, + VPDPWSSDSZrr, + VPDPWSSDSZrrk, + VPDPWSSDSZrrkz, + VPDPWSSDSrm, + VPDPWSSDSrr, + VPDPWSSDYrm, + VPDPWSSDYrr, + VPDPWSSDZ128rm, + VPDPWSSDZ128rmb, + VPDPWSSDZ128rmbk, + VPDPWSSDZ128rmbkz, + VPDPWSSDZ128rmk, + VPDPWSSDZ128rmkz, + VPDPWSSDZ128rr, + VPDPWSSDZ128rrk, + VPDPWSSDZ128rrkz, + VPDPWSSDZ256rm, + VPDPWSSDZ256rmb, + VPDPWSSDZ256rmbk, + VPDPWSSDZ256rmbkz, + VPDPWSSDZ256rmk, + VPDPWSSDZ256rmkz, + VPDPWSSDZ256rr, + VPDPWSSDZ256rrk, + VPDPWSSDZ256rrkz, + VPDPWSSDZrm, + VPDPWSSDZrmb, + VPDPWSSDZrmbk, + VPDPWSSDZrmbkz, + VPDPWSSDZrmk, + VPDPWSSDZrmkz, + VPDPWSSDZrr, + VPDPWSSDZrrk, + VPDPWSSDZrrkz, + VPDPWSSDrm, + VPDPWSSDrr, + VPDPWSUDSYrm, + VPDPWSUDSYrr, + VPDPWSUDSZ128rm, + VPDPWSUDSZ128rmb, + VPDPWSUDSZ128rmbk, + VPDPWSUDSZ128rmbkz, + VPDPWSUDSZ128rmk, + VPDPWSUDSZ128rmkz, + VPDPWSUDSZ128rr, + VPDPWSUDSZ128rrk, + VPDPWSUDSZ128rrkz, + VPDPWSUDSZ256rm, + VPDPWSUDSZ256rmb, + VPDPWSUDSZ256rmbk, + VPDPWSUDSZ256rmbkz, + VPDPWSUDSZ256rmk, + VPDPWSUDSZ256rmkz, + VPDPWSUDSZ256rr, + VPDPWSUDSZ256rrk, + VPDPWSUDSZ256rrkz, + VPDPWSUDSZrm, + VPDPWSUDSZrmb, + VPDPWSUDSZrmbk, + VPDPWSUDSZrmbkz, + VPDPWSUDSZrmk, + VPDPWSUDSZrmkz, + VPDPWSUDSZrr, + VPDPWSUDSZrrk, + VPDPWSUDSZrrkz, + VPDPWSUDSrm, + VPDPWSUDSrr, + VPDPWSUDYrm, + VPDPWSUDYrr, + VPDPWSUDZ128rm, + VPDPWSUDZ128rmb, + VPDPWSUDZ128rmbk, + VPDPWSUDZ128rmbkz, + VPDPWSUDZ128rmk, + VPDPWSUDZ128rmkz, + VPDPWSUDZ128rr, + VPDPWSUDZ128rrk, + VPDPWSUDZ128rrkz, + VPDPWSUDZ256rm, + VPDPWSUDZ256rmb, + VPDPWSUDZ256rmbk, + VPDPWSUDZ256rmbkz, + VPDPWSUDZ256rmk, + VPDPWSUDZ256rmkz, + VPDPWSUDZ256rr, + VPDPWSUDZ256rrk, + VPDPWSUDZ256rrkz, + VPDPWSUDZrm, + VPDPWSUDZrmb, + VPDPWSUDZrmbk, + VPDPWSUDZrmbkz, + VPDPWSUDZrmk, + VPDPWSUDZrmkz, + VPDPWSUDZrr, + VPDPWSUDZrrk, + VPDPWSUDZrrkz, + VPDPWSUDrm, + VPDPWSUDrr, + VPDPWUSDSYrm, + VPDPWUSDSYrr, + VPDPWUSDSZ128rm, + VPDPWUSDSZ128rmb, + VPDPWUSDSZ128rmbk, + VPDPWUSDSZ128rmbkz, + VPDPWUSDSZ128rmk, + VPDPWUSDSZ128rmkz, + VPDPWUSDSZ128rr, + VPDPWUSDSZ128rrk, + VPDPWUSDSZ128rrkz, + VPDPWUSDSZ256rm, + VPDPWUSDSZ256rmb, + VPDPWUSDSZ256rmbk, + VPDPWUSDSZ256rmbkz, + VPDPWUSDSZ256rmk, + VPDPWUSDSZ256rmkz, + VPDPWUSDSZ256rr, + VPDPWUSDSZ256rrk, + VPDPWUSDSZ256rrkz, + VPDPWUSDSZrm, + VPDPWUSDSZrmb, + VPDPWUSDSZrmbk, + VPDPWUSDSZrmbkz, + VPDPWUSDSZrmk, + VPDPWUSDSZrmkz, + VPDPWUSDSZrr, + VPDPWUSDSZrrk, + VPDPWUSDSZrrkz, + VPDPWUSDSrm, + VPDPWUSDSrr, + VPDPWUSDYrm, + VPDPWUSDYrr, + VPDPWUSDZ128rm, + VPDPWUSDZ128rmb, + VPDPWUSDZ128rmbk, + VPDPWUSDZ128rmbkz, + VPDPWUSDZ128rmk, + VPDPWUSDZ128rmkz, + VPDPWUSDZ128rr, + VPDPWUSDZ128rrk, + VPDPWUSDZ128rrkz, + VPDPWUSDZ256rm, + VPDPWUSDZ256rmb, + VPDPWUSDZ256rmbk, + VPDPWUSDZ256rmbkz, + VPDPWUSDZ256rmk, + VPDPWUSDZ256rmkz, + VPDPWUSDZ256rr, + VPDPWUSDZ256rrk, + VPDPWUSDZ256rrkz, + VPDPWUSDZrm, + VPDPWUSDZrmb, + VPDPWUSDZrmbk, + VPDPWUSDZrmbkz, + VPDPWUSDZrmk, + VPDPWUSDZrmkz, + VPDPWUSDZrr, + VPDPWUSDZrrk, + VPDPWUSDZrrkz, + VPDPWUSDrm, + VPDPWUSDrr, + VPDPWUUDSYrm, + VPDPWUUDSYrr, + VPDPWUUDSZ128rm, + VPDPWUUDSZ128rmb, + VPDPWUUDSZ128rmbk, + VPDPWUUDSZ128rmbkz, + VPDPWUUDSZ128rmk, + VPDPWUUDSZ128rmkz, + VPDPWUUDSZ128rr, + VPDPWUUDSZ128rrk, + VPDPWUUDSZ128rrkz, + VPDPWUUDSZ256rm, + VPDPWUUDSZ256rmb, + VPDPWUUDSZ256rmbk, + VPDPWUUDSZ256rmbkz, + VPDPWUUDSZ256rmk, + VPDPWUUDSZ256rmkz, + VPDPWUUDSZ256rr, + VPDPWUUDSZ256rrk, + VPDPWUUDSZ256rrkz, + VPDPWUUDSZrm, + VPDPWUUDSZrmb, + VPDPWUUDSZrmbk, + VPDPWUUDSZrmbkz, + VPDPWUUDSZrmk, + VPDPWUUDSZrmkz, + VPDPWUUDSZrr, + VPDPWUUDSZrrk, + VPDPWUUDSZrrkz, + VPDPWUUDSrm, + VPDPWUUDSrr, + VPDPWUUDYrm, + VPDPWUUDYrr, + VPDPWUUDZ128rm, + VPDPWUUDZ128rmb, + VPDPWUUDZ128rmbk, + VPDPWUUDZ128rmbkz, + VPDPWUUDZ128rmk, + VPDPWUUDZ128rmkz, + VPDPWUUDZ128rr, + VPDPWUUDZ128rrk, + VPDPWUUDZ128rrkz, + VPDPWUUDZ256rm, + VPDPWUUDZ256rmb, + VPDPWUUDZ256rmbk, + VPDPWUUDZ256rmbkz, + VPDPWUUDZ256rmk, + VPDPWUUDZ256rmkz, + VPDPWUUDZ256rr, + VPDPWUUDZ256rrk, + VPDPWUUDZ256rrkz, + VPDPWUUDZrm, + VPDPWUUDZrmb, + VPDPWUUDZrmbk, + VPDPWUUDZrmbkz, + VPDPWUUDZrmk, + VPDPWUUDZrmkz, + VPDPWUUDZrr, + VPDPWUUDZrrk, + VPDPWUUDZrrkz, + VPDPWUUDrm, + VPDPWUUDrr, + VPERM2F128rmi, + VPERM2F128rri, + VPERM2I128rmi, + VPERM2I128rri, + VPERMBZ128rm, + VPERMBZ128rmk, + VPERMBZ128rmkz, + VPERMBZ128rr, + VPERMBZ128rrk, + VPERMBZ128rrkz, + VPERMBZ256rm, + VPERMBZ256rmk, + VPERMBZ256rmkz, + VPERMBZ256rr, + VPERMBZ256rrk, + VPERMBZ256rrkz, + VPERMBZrm, + VPERMBZrmk, + VPERMBZrmkz, + VPERMBZrr, + VPERMBZrrk, + VPERMBZrrkz, + VPERMDYrm, + VPERMDYrr, + VPERMDZ256rm, + VPERMDZ256rmb, + VPERMDZ256rmbk, + VPERMDZ256rmbkz, + VPERMDZ256rmk, + VPERMDZ256rmkz, + VPERMDZ256rr, + VPERMDZ256rrk, + VPERMDZ256rrkz, + VPERMDZrm, + VPERMDZrmb, + VPERMDZrmbk, + VPERMDZrmbkz, + VPERMDZrmk, + VPERMDZrmkz, + VPERMDZrr, + VPERMDZrrk, + VPERMDZrrkz, + VPERMI2BZ128rm, + VPERMI2BZ128rmk, + VPERMI2BZ128rmkz, + VPERMI2BZ128rr, + VPERMI2BZ128rrk, + VPERMI2BZ128rrkz, + VPERMI2BZ256rm, + VPERMI2BZ256rmk, + VPERMI2BZ256rmkz, + VPERMI2BZ256rr, + VPERMI2BZ256rrk, + VPERMI2BZ256rrkz, + VPERMI2BZrm, + VPERMI2BZrmk, + VPERMI2BZrmkz, + VPERMI2BZrr, + VPERMI2BZrrk, + VPERMI2BZrrkz, + VPERMI2DZ128rm, + VPERMI2DZ128rmb, + VPERMI2DZ128rmbk, + VPERMI2DZ128rmbkz, + VPERMI2DZ128rmk, + VPERMI2DZ128rmkz, + VPERMI2DZ128rr, + VPERMI2DZ128rrk, + VPERMI2DZ128rrkz, + VPERMI2DZ256rm, + VPERMI2DZ256rmb, + VPERMI2DZ256rmbk, + VPERMI2DZ256rmbkz, + VPERMI2DZ256rmk, + VPERMI2DZ256rmkz, + VPERMI2DZ256rr, + VPERMI2DZ256rrk, + VPERMI2DZ256rrkz, + VPERMI2DZrm, + VPERMI2DZrmb, + VPERMI2DZrmbk, + VPERMI2DZrmbkz, + VPERMI2DZrmk, + VPERMI2DZrmkz, + VPERMI2DZrr, + VPERMI2DZrrk, + VPERMI2DZrrkz, + VPERMI2PDZ128rm, + VPERMI2PDZ128rmb, + VPERMI2PDZ128rmbk, + VPERMI2PDZ128rmbkz, + VPERMI2PDZ128rmk, + VPERMI2PDZ128rmkz, + VPERMI2PDZ128rr, + VPERMI2PDZ128rrk, + VPERMI2PDZ128rrkz, + VPERMI2PDZ256rm, + VPERMI2PDZ256rmb, + VPERMI2PDZ256rmbk, + VPERMI2PDZ256rmbkz, + VPERMI2PDZ256rmk, + VPERMI2PDZ256rmkz, + VPERMI2PDZ256rr, + VPERMI2PDZ256rrk, + VPERMI2PDZ256rrkz, + VPERMI2PDZrm, + VPERMI2PDZrmb, + VPERMI2PDZrmbk, + VPERMI2PDZrmbkz, + VPERMI2PDZrmk, + VPERMI2PDZrmkz, + VPERMI2PDZrr, + VPERMI2PDZrrk, + VPERMI2PDZrrkz, + VPERMI2PSZ128rm, + VPERMI2PSZ128rmb, + VPERMI2PSZ128rmbk, + VPERMI2PSZ128rmbkz, + VPERMI2PSZ128rmk, + VPERMI2PSZ128rmkz, + VPERMI2PSZ128rr, + VPERMI2PSZ128rrk, + VPERMI2PSZ128rrkz, + VPERMI2PSZ256rm, + VPERMI2PSZ256rmb, + VPERMI2PSZ256rmbk, + VPERMI2PSZ256rmbkz, + VPERMI2PSZ256rmk, + VPERMI2PSZ256rmkz, + VPERMI2PSZ256rr, + VPERMI2PSZ256rrk, + VPERMI2PSZ256rrkz, + VPERMI2PSZrm, + VPERMI2PSZrmb, + VPERMI2PSZrmbk, + VPERMI2PSZrmbkz, + VPERMI2PSZrmk, + VPERMI2PSZrmkz, + VPERMI2PSZrr, + VPERMI2PSZrrk, + VPERMI2PSZrrkz, + VPERMI2QZ128rm, + VPERMI2QZ128rmb, + VPERMI2QZ128rmbk, + VPERMI2QZ128rmbkz, + VPERMI2QZ128rmk, + VPERMI2QZ128rmkz, + VPERMI2QZ128rr, + VPERMI2QZ128rrk, + VPERMI2QZ128rrkz, + VPERMI2QZ256rm, + VPERMI2QZ256rmb, + VPERMI2QZ256rmbk, + VPERMI2QZ256rmbkz, + VPERMI2QZ256rmk, + VPERMI2QZ256rmkz, + VPERMI2QZ256rr, + VPERMI2QZ256rrk, + VPERMI2QZ256rrkz, + VPERMI2QZrm, + VPERMI2QZrmb, + VPERMI2QZrmbk, + VPERMI2QZrmbkz, + VPERMI2QZrmk, + VPERMI2QZrmkz, + VPERMI2QZrr, + VPERMI2QZrrk, + VPERMI2QZrrkz, + VPERMI2WZ128rm, + VPERMI2WZ128rmk, + VPERMI2WZ128rmkz, + VPERMI2WZ128rr, + VPERMI2WZ128rrk, + VPERMI2WZ128rrkz, + VPERMI2WZ256rm, + VPERMI2WZ256rmk, + VPERMI2WZ256rmkz, + VPERMI2WZ256rr, + VPERMI2WZ256rrk, + VPERMI2WZ256rrkz, + VPERMI2WZrm, + VPERMI2WZrmk, + VPERMI2WZrmkz, + VPERMI2WZrr, + VPERMI2WZrrk, + VPERMI2WZrrkz, + VPERMIL2PDYmr, + VPERMIL2PDYrm, + VPERMIL2PDYrr, + VPERMIL2PDYrr_REV, + VPERMIL2PDmr, + VPERMIL2PDrm, + VPERMIL2PDrr, + VPERMIL2PDrr_REV, + VPERMIL2PSYmr, + VPERMIL2PSYrm, + VPERMIL2PSYrr, + VPERMIL2PSYrr_REV, + VPERMIL2PSmr, + VPERMIL2PSrm, + VPERMIL2PSrr, + VPERMIL2PSrr_REV, + VPERMILPDYmi, + VPERMILPDYri, + VPERMILPDYrm, + VPERMILPDYrr, + VPERMILPDZ128mbi, + VPERMILPDZ128mbik, + VPERMILPDZ128mbikz, + VPERMILPDZ128mi, + VPERMILPDZ128mik, + VPERMILPDZ128mikz, + VPERMILPDZ128ri, + VPERMILPDZ128rik, + VPERMILPDZ128rikz, + VPERMILPDZ128rm, + VPERMILPDZ128rmb, + VPERMILPDZ128rmbk, + VPERMILPDZ128rmbkz, + VPERMILPDZ128rmk, + VPERMILPDZ128rmkz, + VPERMILPDZ128rr, + VPERMILPDZ128rrk, + VPERMILPDZ128rrkz, + VPERMILPDZ256mbi, + VPERMILPDZ256mbik, + VPERMILPDZ256mbikz, + VPERMILPDZ256mi, + VPERMILPDZ256mik, + VPERMILPDZ256mikz, + VPERMILPDZ256ri, + VPERMILPDZ256rik, + VPERMILPDZ256rikz, + VPERMILPDZ256rm, + VPERMILPDZ256rmb, + VPERMILPDZ256rmbk, + VPERMILPDZ256rmbkz, + VPERMILPDZ256rmk, + VPERMILPDZ256rmkz, + VPERMILPDZ256rr, + VPERMILPDZ256rrk, + VPERMILPDZ256rrkz, + VPERMILPDZmbi, + VPERMILPDZmbik, + VPERMILPDZmbikz, + VPERMILPDZmi, + VPERMILPDZmik, + VPERMILPDZmikz, + VPERMILPDZri, + VPERMILPDZrik, + VPERMILPDZrikz, + VPERMILPDZrm, + VPERMILPDZrmb, + VPERMILPDZrmbk, + VPERMILPDZrmbkz, + VPERMILPDZrmk, + VPERMILPDZrmkz, + VPERMILPDZrr, + VPERMILPDZrrk, + VPERMILPDZrrkz, + VPERMILPDmi, + VPERMILPDri, + VPERMILPDrm, + VPERMILPDrr, + VPERMILPSYmi, + VPERMILPSYri, + VPERMILPSYrm, + VPERMILPSYrr, + VPERMILPSZ128mbi, + VPERMILPSZ128mbik, + VPERMILPSZ128mbikz, + VPERMILPSZ128mi, + VPERMILPSZ128mik, + VPERMILPSZ128mikz, + VPERMILPSZ128ri, + VPERMILPSZ128rik, + VPERMILPSZ128rikz, + VPERMILPSZ128rm, + VPERMILPSZ128rmb, + VPERMILPSZ128rmbk, + VPERMILPSZ128rmbkz, + VPERMILPSZ128rmk, + VPERMILPSZ128rmkz, + VPERMILPSZ128rr, + VPERMILPSZ128rrk, + VPERMILPSZ128rrkz, + VPERMILPSZ256mbi, + VPERMILPSZ256mbik, + VPERMILPSZ256mbikz, + VPERMILPSZ256mi, + VPERMILPSZ256mik, + VPERMILPSZ256mikz, + VPERMILPSZ256ri, + VPERMILPSZ256rik, + VPERMILPSZ256rikz, + VPERMILPSZ256rm, + VPERMILPSZ256rmb, + VPERMILPSZ256rmbk, + VPERMILPSZ256rmbkz, + VPERMILPSZ256rmk, + VPERMILPSZ256rmkz, + VPERMILPSZ256rr, + VPERMILPSZ256rrk, + VPERMILPSZ256rrkz, + VPERMILPSZmbi, + VPERMILPSZmbik, + VPERMILPSZmbikz, + VPERMILPSZmi, + VPERMILPSZmik, + VPERMILPSZmikz, + VPERMILPSZri, + VPERMILPSZrik, + VPERMILPSZrikz, + VPERMILPSZrm, + VPERMILPSZrmb, + VPERMILPSZrmbk, + VPERMILPSZrmbkz, + VPERMILPSZrmk, + VPERMILPSZrmkz, + VPERMILPSZrr, + VPERMILPSZrrk, + VPERMILPSZrrkz, + VPERMILPSmi, + VPERMILPSri, + VPERMILPSrm, + VPERMILPSrr, + VPERMPDYmi, + VPERMPDYri, + VPERMPDZ256mbi, + VPERMPDZ256mbik, + VPERMPDZ256mbikz, + VPERMPDZ256mi, + VPERMPDZ256mik, + VPERMPDZ256mikz, + VPERMPDZ256ri, + VPERMPDZ256rik, + VPERMPDZ256rikz, + VPERMPDZ256rm, + VPERMPDZ256rmb, + VPERMPDZ256rmbk, + VPERMPDZ256rmbkz, + VPERMPDZ256rmk, + VPERMPDZ256rmkz, + VPERMPDZ256rr, + VPERMPDZ256rrk, + VPERMPDZ256rrkz, + VPERMPDZmbi, + VPERMPDZmbik, + VPERMPDZmbikz, + VPERMPDZmi, + VPERMPDZmik, + VPERMPDZmikz, + VPERMPDZri, + VPERMPDZrik, + VPERMPDZrikz, + VPERMPDZrm, + VPERMPDZrmb, + VPERMPDZrmbk, + VPERMPDZrmbkz, + VPERMPDZrmk, + VPERMPDZrmkz, + VPERMPDZrr, + VPERMPDZrrk, + VPERMPDZrrkz, + VPERMPSYrm, + VPERMPSYrr, + VPERMPSZ256rm, + VPERMPSZ256rmb, + VPERMPSZ256rmbk, + VPERMPSZ256rmbkz, + VPERMPSZ256rmk, + VPERMPSZ256rmkz, + VPERMPSZ256rr, + VPERMPSZ256rrk, + VPERMPSZ256rrkz, + VPERMPSZrm, + VPERMPSZrmb, + VPERMPSZrmbk, + VPERMPSZrmbkz, + VPERMPSZrmk, + VPERMPSZrmkz, + VPERMPSZrr, + VPERMPSZrrk, + VPERMPSZrrkz, + VPERMQYmi, + VPERMQYri, + VPERMQZ256mbi, + VPERMQZ256mbik, + VPERMQZ256mbikz, + VPERMQZ256mi, + VPERMQZ256mik, + VPERMQZ256mikz, + VPERMQZ256ri, + VPERMQZ256rik, + VPERMQZ256rikz, + VPERMQZ256rm, + VPERMQZ256rmb, + VPERMQZ256rmbk, + VPERMQZ256rmbkz, + VPERMQZ256rmk, + VPERMQZ256rmkz, + VPERMQZ256rr, + VPERMQZ256rrk, + VPERMQZ256rrkz, + VPERMQZmbi, + VPERMQZmbik, + VPERMQZmbikz, + VPERMQZmi, + VPERMQZmik, + VPERMQZmikz, + VPERMQZri, + VPERMQZrik, + VPERMQZrikz, + VPERMQZrm, + VPERMQZrmb, + VPERMQZrmbk, + VPERMQZrmbkz, + VPERMQZrmk, + VPERMQZrmkz, + VPERMQZrr, + VPERMQZrrk, + VPERMQZrrkz, + VPERMT2BZ128rm, + VPERMT2BZ128rmk, + VPERMT2BZ128rmkz, + VPERMT2BZ128rr, + VPERMT2BZ128rrk, + VPERMT2BZ128rrkz, + VPERMT2BZ256rm, + VPERMT2BZ256rmk, + VPERMT2BZ256rmkz, + VPERMT2BZ256rr, + VPERMT2BZ256rrk, + VPERMT2BZ256rrkz, + VPERMT2BZrm, + VPERMT2BZrmk, + VPERMT2BZrmkz, + VPERMT2BZrr, + VPERMT2BZrrk, + VPERMT2BZrrkz, + VPERMT2DZ128rm, + VPERMT2DZ128rmb, + VPERMT2DZ128rmbk, + VPERMT2DZ128rmbkz, + VPERMT2DZ128rmk, + VPERMT2DZ128rmkz, + VPERMT2DZ128rr, + VPERMT2DZ128rrk, + VPERMT2DZ128rrkz, + VPERMT2DZ256rm, + VPERMT2DZ256rmb, + VPERMT2DZ256rmbk, + VPERMT2DZ256rmbkz, + VPERMT2DZ256rmk, + VPERMT2DZ256rmkz, + VPERMT2DZ256rr, + VPERMT2DZ256rrk, + VPERMT2DZ256rrkz, + VPERMT2DZrm, + VPERMT2DZrmb, + VPERMT2DZrmbk, + VPERMT2DZrmbkz, + VPERMT2DZrmk, + VPERMT2DZrmkz, + VPERMT2DZrr, + VPERMT2DZrrk, + VPERMT2DZrrkz, + VPERMT2PDZ128rm, + VPERMT2PDZ128rmb, + VPERMT2PDZ128rmbk, + VPERMT2PDZ128rmbkz, + VPERMT2PDZ128rmk, + VPERMT2PDZ128rmkz, + VPERMT2PDZ128rr, + VPERMT2PDZ128rrk, + VPERMT2PDZ128rrkz, + VPERMT2PDZ256rm, + VPERMT2PDZ256rmb, + VPERMT2PDZ256rmbk, + VPERMT2PDZ256rmbkz, + VPERMT2PDZ256rmk, + VPERMT2PDZ256rmkz, + VPERMT2PDZ256rr, + VPERMT2PDZ256rrk, + VPERMT2PDZ256rrkz, + VPERMT2PDZrm, + VPERMT2PDZrmb, + VPERMT2PDZrmbk, + VPERMT2PDZrmbkz, + VPERMT2PDZrmk, + VPERMT2PDZrmkz, + VPERMT2PDZrr, + VPERMT2PDZrrk, + VPERMT2PDZrrkz, + VPERMT2PSZ128rm, + VPERMT2PSZ128rmb, + VPERMT2PSZ128rmbk, + VPERMT2PSZ128rmbkz, + VPERMT2PSZ128rmk, + VPERMT2PSZ128rmkz, + VPERMT2PSZ128rr, + VPERMT2PSZ128rrk, + VPERMT2PSZ128rrkz, + VPERMT2PSZ256rm, + VPERMT2PSZ256rmb, + VPERMT2PSZ256rmbk, + VPERMT2PSZ256rmbkz, + VPERMT2PSZ256rmk, + VPERMT2PSZ256rmkz, + VPERMT2PSZ256rr, + VPERMT2PSZ256rrk, + VPERMT2PSZ256rrkz, + VPERMT2PSZrm, + VPERMT2PSZrmb, + VPERMT2PSZrmbk, + VPERMT2PSZrmbkz, + VPERMT2PSZrmk, + VPERMT2PSZrmkz, + VPERMT2PSZrr, + VPERMT2PSZrrk, + VPERMT2PSZrrkz, + VPERMT2QZ128rm, + VPERMT2QZ128rmb, + VPERMT2QZ128rmbk, + VPERMT2QZ128rmbkz, + VPERMT2QZ128rmk, + VPERMT2QZ128rmkz, + VPERMT2QZ128rr, + VPERMT2QZ128rrk, + VPERMT2QZ128rrkz, + VPERMT2QZ256rm, + VPERMT2QZ256rmb, + VPERMT2QZ256rmbk, + VPERMT2QZ256rmbkz, + VPERMT2QZ256rmk, + VPERMT2QZ256rmkz, + VPERMT2QZ256rr, + VPERMT2QZ256rrk, + VPERMT2QZ256rrkz, + VPERMT2QZrm, + VPERMT2QZrmb, + VPERMT2QZrmbk, + VPERMT2QZrmbkz, + VPERMT2QZrmk, + VPERMT2QZrmkz, + VPERMT2QZrr, + VPERMT2QZrrk, + VPERMT2QZrrkz, + VPERMT2WZ128rm, + VPERMT2WZ128rmk, + VPERMT2WZ128rmkz, + VPERMT2WZ128rr, + VPERMT2WZ128rrk, + VPERMT2WZ128rrkz, + VPERMT2WZ256rm, + VPERMT2WZ256rmk, + VPERMT2WZ256rmkz, + VPERMT2WZ256rr, + VPERMT2WZ256rrk, + VPERMT2WZ256rrkz, + VPERMT2WZrm, + VPERMT2WZrmk, + VPERMT2WZrmkz, + VPERMT2WZrr, + VPERMT2WZrrk, + VPERMT2WZrrkz, + VPERMWZ128rm, + VPERMWZ128rmk, + VPERMWZ128rmkz, + VPERMWZ128rr, + VPERMWZ128rrk, + VPERMWZ128rrkz, + VPERMWZ256rm, + VPERMWZ256rmk, + VPERMWZ256rmkz, + VPERMWZ256rr, + VPERMWZ256rrk, + VPERMWZ256rrkz, + VPERMWZrm, + VPERMWZrmk, + VPERMWZrmkz, + VPERMWZrr, + VPERMWZrrk, + VPERMWZrrkz, + VPEXPANDBZ128rm, + VPEXPANDBZ128rmk, + VPEXPANDBZ128rmkz, + VPEXPANDBZ128rr, + VPEXPANDBZ128rrk, + VPEXPANDBZ128rrkz, + VPEXPANDBZ256rm, + VPEXPANDBZ256rmk, + VPEXPANDBZ256rmkz, + VPEXPANDBZ256rr, + VPEXPANDBZ256rrk, + VPEXPANDBZ256rrkz, + VPEXPANDBZrm, + VPEXPANDBZrmk, + VPEXPANDBZrmkz, + VPEXPANDBZrr, + VPEXPANDBZrrk, + VPEXPANDBZrrkz, + VPEXPANDDZ128rm, + VPEXPANDDZ128rmk, + VPEXPANDDZ128rmkz, + VPEXPANDDZ128rr, + VPEXPANDDZ128rrk, + VPEXPANDDZ128rrkz, + VPEXPANDDZ256rm, + VPEXPANDDZ256rmk, + VPEXPANDDZ256rmkz, + VPEXPANDDZ256rr, + VPEXPANDDZ256rrk, + VPEXPANDDZ256rrkz, + VPEXPANDDZrm, + VPEXPANDDZrmk, + VPEXPANDDZrmkz, + VPEXPANDDZrr, + VPEXPANDDZrrk, + VPEXPANDDZrrkz, + VPEXPANDQZ128rm, + VPEXPANDQZ128rmk, + VPEXPANDQZ128rmkz, + VPEXPANDQZ128rr, + VPEXPANDQZ128rrk, + VPEXPANDQZ128rrkz, + VPEXPANDQZ256rm, + VPEXPANDQZ256rmk, + VPEXPANDQZ256rmkz, + VPEXPANDQZ256rr, + VPEXPANDQZ256rrk, + VPEXPANDQZ256rrkz, + VPEXPANDQZrm, + VPEXPANDQZrmk, + VPEXPANDQZrmkz, + VPEXPANDQZrr, + VPEXPANDQZrrk, + VPEXPANDQZrrkz, + VPEXPANDWZ128rm, + VPEXPANDWZ128rmk, + VPEXPANDWZ128rmkz, + VPEXPANDWZ128rr, + VPEXPANDWZ128rrk, + VPEXPANDWZ128rrkz, + VPEXPANDWZ256rm, + VPEXPANDWZ256rmk, + VPEXPANDWZ256rmkz, + VPEXPANDWZ256rr, + VPEXPANDWZ256rrk, + VPEXPANDWZ256rrkz, + VPEXPANDWZrm, + VPEXPANDWZrmk, + VPEXPANDWZrmkz, + VPEXPANDWZrr, + VPEXPANDWZrrk, + VPEXPANDWZrrkz, + VPEXTRBZmri, + VPEXTRBZrri, + VPEXTRBmri, + VPEXTRBrri, + VPEXTRDZmri, + VPEXTRDZrri, + VPEXTRDmri, + VPEXTRDrri, + VPEXTRQZmri, + VPEXTRQZrri, + VPEXTRQmri, + VPEXTRQrri, + VPEXTRWZmri, + VPEXTRWZrri, + VPEXTRWZrri_REV, + VPEXTRWmri, + VPEXTRWrri, + VPEXTRWrri_REV, + VPGATHERDDYrm, + VPGATHERDDZ128rm, + VPGATHERDDZ256rm, + VPGATHERDDZrm, + VPGATHERDDrm, + VPGATHERDQYrm, + VPGATHERDQZ128rm, + VPGATHERDQZ256rm, + VPGATHERDQZrm, + VPGATHERDQrm, + VPGATHERQDYrm, + VPGATHERQDZ128rm, + VPGATHERQDZ256rm, + VPGATHERQDZrm, + VPGATHERQDrm, + VPGATHERQQYrm, + VPGATHERQQZ128rm, + VPGATHERQQZ256rm, + VPGATHERQQZrm, + VPGATHERQQrm, + VPHADDBDrm, + VPHADDBDrr, + VPHADDBQrm, + VPHADDBQrr, + VPHADDBWrm, + VPHADDBWrr, + VPHADDDQrm, + VPHADDDQrr, + VPHADDDYrm, + VPHADDDYrr, + VPHADDDrm, + VPHADDDrr, + VPHADDSWYrm, + VPHADDSWYrr, + VPHADDSWrm, + VPHADDSWrr, + VPHADDUBDrm, + VPHADDUBDrr, + VPHADDUBQrm, + VPHADDUBQrr, + VPHADDUBWrm, + VPHADDUBWrr, + VPHADDUDQrm, + VPHADDUDQrr, + VPHADDUWDrm, + VPHADDUWDrr, + VPHADDUWQrm, + VPHADDUWQrr, + VPHADDWDrm, + VPHADDWDrr, + VPHADDWQrm, + VPHADDWQrr, + VPHADDWYrm, + VPHADDWYrr, + VPHADDWrm, + VPHADDWrr, + VPHMINPOSUWrm, + VPHMINPOSUWrr, + VPHSUBBWrm, + VPHSUBBWrr, + VPHSUBDQrm, + VPHSUBDQrr, + VPHSUBDYrm, + VPHSUBDYrr, + VPHSUBDrm, + VPHSUBDrr, + VPHSUBSWYrm, + VPHSUBSWYrr, + VPHSUBSWrm, + VPHSUBSWrr, + VPHSUBWDrm, + VPHSUBWDrr, + VPHSUBWYrm, + VPHSUBWYrr, + VPHSUBWrm, + VPHSUBWrr, + VPINSRBZrmi, + VPINSRBZrri, + VPINSRBrmi, + VPINSRBrri, + VPINSRDZrmi, + VPINSRDZrri, + VPINSRDrmi, + VPINSRDrri, + VPINSRQZrmi, + VPINSRQZrri, + VPINSRQrmi, + VPINSRQrri, + VPINSRWZrmi, + VPINSRWZrri, + VPINSRWrmi, + VPINSRWrri, + VPLZCNTDZ128rm, + VPLZCNTDZ128rmb, + VPLZCNTDZ128rmbk, + VPLZCNTDZ128rmbkz, + VPLZCNTDZ128rmk, + VPLZCNTDZ128rmkz, + VPLZCNTDZ128rr, + VPLZCNTDZ128rrk, + VPLZCNTDZ128rrkz, + VPLZCNTDZ256rm, + VPLZCNTDZ256rmb, + VPLZCNTDZ256rmbk, + VPLZCNTDZ256rmbkz, + VPLZCNTDZ256rmk, + VPLZCNTDZ256rmkz, + VPLZCNTDZ256rr, + VPLZCNTDZ256rrk, + VPLZCNTDZ256rrkz, + VPLZCNTDZrm, + VPLZCNTDZrmb, + VPLZCNTDZrmbk, + VPLZCNTDZrmbkz, + VPLZCNTDZrmk, + VPLZCNTDZrmkz, + VPLZCNTDZrr, + VPLZCNTDZrrk, + VPLZCNTDZrrkz, + VPLZCNTQZ128rm, + VPLZCNTQZ128rmb, + VPLZCNTQZ128rmbk, + VPLZCNTQZ128rmbkz, + VPLZCNTQZ128rmk, + VPLZCNTQZ128rmkz, + VPLZCNTQZ128rr, + VPLZCNTQZ128rrk, + VPLZCNTQZ128rrkz, + VPLZCNTQZ256rm, + VPLZCNTQZ256rmb, + VPLZCNTQZ256rmbk, + VPLZCNTQZ256rmbkz, + VPLZCNTQZ256rmk, + VPLZCNTQZ256rmkz, + VPLZCNTQZ256rr, + VPLZCNTQZ256rrk, + VPLZCNTQZ256rrkz, + VPLZCNTQZrm, + VPLZCNTQZrmb, + VPLZCNTQZrmbk, + VPLZCNTQZrmbkz, + VPLZCNTQZrmk, + VPLZCNTQZrmkz, + VPLZCNTQZrr, + VPLZCNTQZrrk, + VPLZCNTQZrrkz, + VPMACSDDrm, + VPMACSDDrr, + VPMACSDQHrm, + VPMACSDQHrr, + VPMACSDQLrm, + VPMACSDQLrr, + VPMACSSDDrm, + VPMACSSDDrr, + VPMACSSDQHrm, + VPMACSSDQHrr, + VPMACSSDQLrm, + VPMACSSDQLrr, + VPMACSSWDrm, + VPMACSSWDrr, + VPMACSSWWrm, + VPMACSSWWrr, + VPMACSWDrm, + VPMACSWDrr, + VPMACSWWrm, + VPMACSWWrr, + VPMADCSSWDrm, + VPMADCSSWDrr, + VPMADCSWDrm, + VPMADCSWDrr, + VPMADD52HUQYrm, + VPMADD52HUQYrr, + VPMADD52HUQZ128m, + VPMADD52HUQZ128mb, + VPMADD52HUQZ128mbk, + VPMADD52HUQZ128mbkz, + VPMADD52HUQZ128mk, + VPMADD52HUQZ128mkz, + VPMADD52HUQZ128r, + VPMADD52HUQZ128rk, + VPMADD52HUQZ128rkz, + VPMADD52HUQZ256m, + VPMADD52HUQZ256mb, + VPMADD52HUQZ256mbk, + VPMADD52HUQZ256mbkz, + VPMADD52HUQZ256mk, + VPMADD52HUQZ256mkz, + VPMADD52HUQZ256r, + VPMADD52HUQZ256rk, + VPMADD52HUQZ256rkz, + VPMADD52HUQZm, + VPMADD52HUQZmb, + VPMADD52HUQZmbk, + VPMADD52HUQZmbkz, + VPMADD52HUQZmk, + VPMADD52HUQZmkz, + VPMADD52HUQZr, + VPMADD52HUQZrk, + VPMADD52HUQZrkz, + VPMADD52HUQrm, + VPMADD52HUQrr, + VPMADD52LUQYrm, + VPMADD52LUQYrr, + VPMADD52LUQZ128m, + VPMADD52LUQZ128mb, + VPMADD52LUQZ128mbk, + VPMADD52LUQZ128mbkz, + VPMADD52LUQZ128mk, + VPMADD52LUQZ128mkz, + VPMADD52LUQZ128r, + VPMADD52LUQZ128rk, + VPMADD52LUQZ128rkz, + VPMADD52LUQZ256m, + VPMADD52LUQZ256mb, + VPMADD52LUQZ256mbk, + VPMADD52LUQZ256mbkz, + VPMADD52LUQZ256mk, + VPMADD52LUQZ256mkz, + VPMADD52LUQZ256r, + VPMADD52LUQZ256rk, + VPMADD52LUQZ256rkz, + VPMADD52LUQZm, + VPMADD52LUQZmb, + VPMADD52LUQZmbk, + VPMADD52LUQZmbkz, + VPMADD52LUQZmk, + VPMADD52LUQZmkz, + VPMADD52LUQZr, + VPMADD52LUQZrk, + VPMADD52LUQZrkz, + VPMADD52LUQrm, + VPMADD52LUQrr, + VPMADDUBSWYrm, + VPMADDUBSWYrr, + VPMADDUBSWZ128rm, + VPMADDUBSWZ128rmk, + VPMADDUBSWZ128rmkz, + VPMADDUBSWZ128rr, + VPMADDUBSWZ128rrk, + VPMADDUBSWZ128rrkz, + VPMADDUBSWZ256rm, + VPMADDUBSWZ256rmk, + VPMADDUBSWZ256rmkz, + VPMADDUBSWZ256rr, + VPMADDUBSWZ256rrk, + VPMADDUBSWZ256rrkz, + VPMADDUBSWZrm, + VPMADDUBSWZrmk, + VPMADDUBSWZrmkz, + VPMADDUBSWZrr, + VPMADDUBSWZrrk, + VPMADDUBSWZrrkz, + VPMADDUBSWrm, + VPMADDUBSWrr, + VPMADDWDYrm, + VPMADDWDYrr, + VPMADDWDZ128rm, + VPMADDWDZ128rmk, + VPMADDWDZ128rmkz, + VPMADDWDZ128rr, + VPMADDWDZ128rrk, + VPMADDWDZ128rrkz, + VPMADDWDZ256rm, + VPMADDWDZ256rmk, + VPMADDWDZ256rmkz, + VPMADDWDZ256rr, + VPMADDWDZ256rrk, + VPMADDWDZ256rrkz, + VPMADDWDZrm, + VPMADDWDZrmk, + VPMADDWDZrmkz, + VPMADDWDZrr, + VPMADDWDZrrk, + VPMADDWDZrrkz, + VPMADDWDrm, + VPMADDWDrr, + VPMASKMOVDYmr, + VPMASKMOVDYrm, + VPMASKMOVDmr, + VPMASKMOVDrm, + VPMASKMOVQYmr, + VPMASKMOVQYrm, + VPMASKMOVQmr, + VPMASKMOVQrm, + VPMAXSBYrm, + VPMAXSBYrr, + VPMAXSBZ128rm, + VPMAXSBZ128rmk, + VPMAXSBZ128rmkz, + VPMAXSBZ128rr, + VPMAXSBZ128rrk, + VPMAXSBZ128rrkz, + VPMAXSBZ256rm, + VPMAXSBZ256rmk, + VPMAXSBZ256rmkz, + VPMAXSBZ256rr, + VPMAXSBZ256rrk, + VPMAXSBZ256rrkz, + VPMAXSBZrm, + VPMAXSBZrmk, + VPMAXSBZrmkz, + VPMAXSBZrr, + VPMAXSBZrrk, + VPMAXSBZrrkz, + VPMAXSBrm, + VPMAXSBrr, + VPMAXSDYrm, + VPMAXSDYrr, + VPMAXSDZ128rm, + VPMAXSDZ128rmb, + VPMAXSDZ128rmbk, + VPMAXSDZ128rmbkz, + VPMAXSDZ128rmk, + VPMAXSDZ128rmkz, + VPMAXSDZ128rr, + VPMAXSDZ128rrk, + VPMAXSDZ128rrkz, + VPMAXSDZ256rm, + VPMAXSDZ256rmb, + VPMAXSDZ256rmbk, + VPMAXSDZ256rmbkz, + VPMAXSDZ256rmk, + VPMAXSDZ256rmkz, + VPMAXSDZ256rr, + VPMAXSDZ256rrk, + VPMAXSDZ256rrkz, + VPMAXSDZrm, + VPMAXSDZrmb, + VPMAXSDZrmbk, + VPMAXSDZrmbkz, + VPMAXSDZrmk, + VPMAXSDZrmkz, + VPMAXSDZrr, + VPMAXSDZrrk, + VPMAXSDZrrkz, + VPMAXSDrm, + VPMAXSDrr, + VPMAXSQZ128rm, + VPMAXSQZ128rmb, + VPMAXSQZ128rmbk, + VPMAXSQZ128rmbkz, + VPMAXSQZ128rmk, + VPMAXSQZ128rmkz, + VPMAXSQZ128rr, + VPMAXSQZ128rrk, + VPMAXSQZ128rrkz, + VPMAXSQZ256rm, + VPMAXSQZ256rmb, + VPMAXSQZ256rmbk, + VPMAXSQZ256rmbkz, + VPMAXSQZ256rmk, + VPMAXSQZ256rmkz, + VPMAXSQZ256rr, + VPMAXSQZ256rrk, + VPMAXSQZ256rrkz, + VPMAXSQZrm, + VPMAXSQZrmb, + VPMAXSQZrmbk, + VPMAXSQZrmbkz, + VPMAXSQZrmk, + VPMAXSQZrmkz, + VPMAXSQZrr, + VPMAXSQZrrk, + VPMAXSQZrrkz, + VPMAXSWYrm, + VPMAXSWYrr, + VPMAXSWZ128rm, + VPMAXSWZ128rmk, + VPMAXSWZ128rmkz, + VPMAXSWZ128rr, + VPMAXSWZ128rrk, + VPMAXSWZ128rrkz, + VPMAXSWZ256rm, + VPMAXSWZ256rmk, + VPMAXSWZ256rmkz, + VPMAXSWZ256rr, + VPMAXSWZ256rrk, + VPMAXSWZ256rrkz, + VPMAXSWZrm, + VPMAXSWZrmk, + VPMAXSWZrmkz, + VPMAXSWZrr, + VPMAXSWZrrk, + VPMAXSWZrrkz, + VPMAXSWrm, + VPMAXSWrr, + VPMAXUBYrm, + VPMAXUBYrr, + VPMAXUBZ128rm, + VPMAXUBZ128rmk, + VPMAXUBZ128rmkz, + VPMAXUBZ128rr, + VPMAXUBZ128rrk, + VPMAXUBZ128rrkz, + VPMAXUBZ256rm, + VPMAXUBZ256rmk, + VPMAXUBZ256rmkz, + VPMAXUBZ256rr, + VPMAXUBZ256rrk, + VPMAXUBZ256rrkz, + VPMAXUBZrm, + VPMAXUBZrmk, + VPMAXUBZrmkz, + VPMAXUBZrr, + VPMAXUBZrrk, + VPMAXUBZrrkz, + VPMAXUBrm, + VPMAXUBrr, + VPMAXUDYrm, + VPMAXUDYrr, + VPMAXUDZ128rm, + VPMAXUDZ128rmb, + VPMAXUDZ128rmbk, + VPMAXUDZ128rmbkz, + VPMAXUDZ128rmk, + VPMAXUDZ128rmkz, + VPMAXUDZ128rr, + VPMAXUDZ128rrk, + VPMAXUDZ128rrkz, + VPMAXUDZ256rm, + VPMAXUDZ256rmb, + VPMAXUDZ256rmbk, + VPMAXUDZ256rmbkz, + VPMAXUDZ256rmk, + VPMAXUDZ256rmkz, + VPMAXUDZ256rr, + VPMAXUDZ256rrk, + VPMAXUDZ256rrkz, + VPMAXUDZrm, + VPMAXUDZrmb, + VPMAXUDZrmbk, + VPMAXUDZrmbkz, + VPMAXUDZrmk, + VPMAXUDZrmkz, + VPMAXUDZrr, + VPMAXUDZrrk, + VPMAXUDZrrkz, + VPMAXUDrm, + VPMAXUDrr, + VPMAXUQZ128rm, + VPMAXUQZ128rmb, + VPMAXUQZ128rmbk, + VPMAXUQZ128rmbkz, + VPMAXUQZ128rmk, + VPMAXUQZ128rmkz, + VPMAXUQZ128rr, + VPMAXUQZ128rrk, + VPMAXUQZ128rrkz, + VPMAXUQZ256rm, + VPMAXUQZ256rmb, + VPMAXUQZ256rmbk, + VPMAXUQZ256rmbkz, + VPMAXUQZ256rmk, + VPMAXUQZ256rmkz, + VPMAXUQZ256rr, + VPMAXUQZ256rrk, + VPMAXUQZ256rrkz, + VPMAXUQZrm, + VPMAXUQZrmb, + VPMAXUQZrmbk, + VPMAXUQZrmbkz, + VPMAXUQZrmk, + VPMAXUQZrmkz, + VPMAXUQZrr, + VPMAXUQZrrk, + VPMAXUQZrrkz, + VPMAXUWYrm, + VPMAXUWYrr, + VPMAXUWZ128rm, + VPMAXUWZ128rmk, + VPMAXUWZ128rmkz, + VPMAXUWZ128rr, + VPMAXUWZ128rrk, + VPMAXUWZ128rrkz, + VPMAXUWZ256rm, + VPMAXUWZ256rmk, + VPMAXUWZ256rmkz, + VPMAXUWZ256rr, + VPMAXUWZ256rrk, + VPMAXUWZ256rrkz, + VPMAXUWZrm, + VPMAXUWZrmk, + VPMAXUWZrmkz, + VPMAXUWZrr, + VPMAXUWZrrk, + VPMAXUWZrrkz, + VPMAXUWrm, + VPMAXUWrr, + VPMINSBYrm, + VPMINSBYrr, + VPMINSBZ128rm, + VPMINSBZ128rmk, + VPMINSBZ128rmkz, + VPMINSBZ128rr, + VPMINSBZ128rrk, + VPMINSBZ128rrkz, + VPMINSBZ256rm, + VPMINSBZ256rmk, + VPMINSBZ256rmkz, + VPMINSBZ256rr, + VPMINSBZ256rrk, + VPMINSBZ256rrkz, + VPMINSBZrm, + VPMINSBZrmk, + VPMINSBZrmkz, + VPMINSBZrr, + VPMINSBZrrk, + VPMINSBZrrkz, + VPMINSBrm, + VPMINSBrr, + VPMINSDYrm, + VPMINSDYrr, + VPMINSDZ128rm, + VPMINSDZ128rmb, + VPMINSDZ128rmbk, + VPMINSDZ128rmbkz, + VPMINSDZ128rmk, + VPMINSDZ128rmkz, + VPMINSDZ128rr, + VPMINSDZ128rrk, + VPMINSDZ128rrkz, + VPMINSDZ256rm, + VPMINSDZ256rmb, + VPMINSDZ256rmbk, + VPMINSDZ256rmbkz, + VPMINSDZ256rmk, + VPMINSDZ256rmkz, + VPMINSDZ256rr, + VPMINSDZ256rrk, + VPMINSDZ256rrkz, + VPMINSDZrm, + VPMINSDZrmb, + VPMINSDZrmbk, + VPMINSDZrmbkz, + VPMINSDZrmk, + VPMINSDZrmkz, + VPMINSDZrr, + VPMINSDZrrk, + VPMINSDZrrkz, + VPMINSDrm, + VPMINSDrr, + VPMINSQZ128rm, + VPMINSQZ128rmb, + VPMINSQZ128rmbk, + VPMINSQZ128rmbkz, + VPMINSQZ128rmk, + VPMINSQZ128rmkz, + VPMINSQZ128rr, + VPMINSQZ128rrk, + VPMINSQZ128rrkz, + VPMINSQZ256rm, + VPMINSQZ256rmb, + VPMINSQZ256rmbk, + VPMINSQZ256rmbkz, + VPMINSQZ256rmk, + VPMINSQZ256rmkz, + VPMINSQZ256rr, + VPMINSQZ256rrk, + VPMINSQZ256rrkz, + VPMINSQZrm, + VPMINSQZrmb, + VPMINSQZrmbk, + VPMINSQZrmbkz, + VPMINSQZrmk, + VPMINSQZrmkz, + VPMINSQZrr, + VPMINSQZrrk, + VPMINSQZrrkz, + VPMINSWYrm, + VPMINSWYrr, + VPMINSWZ128rm, + VPMINSWZ128rmk, + VPMINSWZ128rmkz, + VPMINSWZ128rr, + VPMINSWZ128rrk, + VPMINSWZ128rrkz, + VPMINSWZ256rm, + VPMINSWZ256rmk, + VPMINSWZ256rmkz, + VPMINSWZ256rr, + VPMINSWZ256rrk, + VPMINSWZ256rrkz, + VPMINSWZrm, + VPMINSWZrmk, + VPMINSWZrmkz, + VPMINSWZrr, + VPMINSWZrrk, + VPMINSWZrrkz, + VPMINSWrm, + VPMINSWrr, + VPMINUBYrm, + VPMINUBYrr, + VPMINUBZ128rm, + VPMINUBZ128rmk, + VPMINUBZ128rmkz, + VPMINUBZ128rr, + VPMINUBZ128rrk, + VPMINUBZ128rrkz, + VPMINUBZ256rm, + VPMINUBZ256rmk, + VPMINUBZ256rmkz, + VPMINUBZ256rr, + VPMINUBZ256rrk, + VPMINUBZ256rrkz, + VPMINUBZrm, + VPMINUBZrmk, + VPMINUBZrmkz, + VPMINUBZrr, + VPMINUBZrrk, + VPMINUBZrrkz, + VPMINUBrm, + VPMINUBrr, + VPMINUDYrm, + VPMINUDYrr, + VPMINUDZ128rm, + VPMINUDZ128rmb, + VPMINUDZ128rmbk, + VPMINUDZ128rmbkz, + VPMINUDZ128rmk, + VPMINUDZ128rmkz, + VPMINUDZ128rr, + VPMINUDZ128rrk, + VPMINUDZ128rrkz, + VPMINUDZ256rm, + VPMINUDZ256rmb, + VPMINUDZ256rmbk, + VPMINUDZ256rmbkz, + VPMINUDZ256rmk, + VPMINUDZ256rmkz, + VPMINUDZ256rr, + VPMINUDZ256rrk, + VPMINUDZ256rrkz, + VPMINUDZrm, + VPMINUDZrmb, + VPMINUDZrmbk, + VPMINUDZrmbkz, + VPMINUDZrmk, + VPMINUDZrmkz, + VPMINUDZrr, + VPMINUDZrrk, + VPMINUDZrrkz, + VPMINUDrm, + VPMINUDrr, + VPMINUQZ128rm, + VPMINUQZ128rmb, + VPMINUQZ128rmbk, + VPMINUQZ128rmbkz, + VPMINUQZ128rmk, + VPMINUQZ128rmkz, + VPMINUQZ128rr, + VPMINUQZ128rrk, + VPMINUQZ128rrkz, + VPMINUQZ256rm, + VPMINUQZ256rmb, + VPMINUQZ256rmbk, + VPMINUQZ256rmbkz, + VPMINUQZ256rmk, + VPMINUQZ256rmkz, + VPMINUQZ256rr, + VPMINUQZ256rrk, + VPMINUQZ256rrkz, + VPMINUQZrm, + VPMINUQZrmb, + VPMINUQZrmbk, + VPMINUQZrmbkz, + VPMINUQZrmk, + VPMINUQZrmkz, + VPMINUQZrr, + VPMINUQZrrk, + VPMINUQZrrkz, + VPMINUWYrm, + VPMINUWYrr, + VPMINUWZ128rm, + VPMINUWZ128rmk, + VPMINUWZ128rmkz, + VPMINUWZ128rr, + VPMINUWZ128rrk, + VPMINUWZ128rrkz, + VPMINUWZ256rm, + VPMINUWZ256rmk, + VPMINUWZ256rmkz, + VPMINUWZ256rr, + VPMINUWZ256rrk, + VPMINUWZ256rrkz, + VPMINUWZrm, + VPMINUWZrmk, + VPMINUWZrmkz, + VPMINUWZrr, + VPMINUWZrrk, + VPMINUWZrrkz, + VPMINUWrm, + VPMINUWrr, + VPMOVB2MZ128kr, + VPMOVB2MZ256kr, + VPMOVB2MZkr, + VPMOVD2MZ128kr, + VPMOVD2MZ256kr, + VPMOVD2MZkr, + VPMOVDBZ128mr, + VPMOVDBZ128mrk, + VPMOVDBZ128rr, + VPMOVDBZ128rrk, + VPMOVDBZ128rrkz, + VPMOVDBZ256mr, + VPMOVDBZ256mrk, + VPMOVDBZ256rr, + VPMOVDBZ256rrk, + VPMOVDBZ256rrkz, + VPMOVDBZmr, + VPMOVDBZmrk, + VPMOVDBZrr, + VPMOVDBZrrk, + VPMOVDBZrrkz, + VPMOVDWZ128mr, + VPMOVDWZ128mrk, + VPMOVDWZ128rr, + VPMOVDWZ128rrk, + VPMOVDWZ128rrkz, + VPMOVDWZ256mr, + VPMOVDWZ256mrk, + VPMOVDWZ256rr, + VPMOVDWZ256rrk, + VPMOVDWZ256rrkz, + VPMOVDWZmr, + VPMOVDWZmrk, + VPMOVDWZrr, + VPMOVDWZrrk, + VPMOVDWZrrkz, + VPMOVM2BZ128rk, + VPMOVM2BZ256rk, + VPMOVM2BZrk, + VPMOVM2DZ128rk, + VPMOVM2DZ256rk, + VPMOVM2DZrk, + VPMOVM2QZ128rk, + VPMOVM2QZ256rk, + VPMOVM2QZrk, + VPMOVM2WZ128rk, + VPMOVM2WZ256rk, + VPMOVM2WZrk, + VPMOVMSKBYrr, + VPMOVMSKBrr, + VPMOVQ2MZ128kr, + VPMOVQ2MZ256kr, + VPMOVQ2MZkr, + VPMOVQBZ128mr, + VPMOVQBZ128mrk, + VPMOVQBZ128rr, + VPMOVQBZ128rrk, + VPMOVQBZ128rrkz, + VPMOVQBZ256mr, + VPMOVQBZ256mrk, + VPMOVQBZ256rr, + VPMOVQBZ256rrk, + VPMOVQBZ256rrkz, + VPMOVQBZmr, + VPMOVQBZmrk, + VPMOVQBZrr, + VPMOVQBZrrk, + VPMOVQBZrrkz, + VPMOVQDZ128mr, + VPMOVQDZ128mrk, + VPMOVQDZ128rr, + VPMOVQDZ128rrk, + VPMOVQDZ128rrkz, + VPMOVQDZ256mr, + VPMOVQDZ256mrk, + VPMOVQDZ256rr, + VPMOVQDZ256rrk, + VPMOVQDZ256rrkz, + VPMOVQDZmr, + VPMOVQDZmrk, + VPMOVQDZrr, + VPMOVQDZrrk, + VPMOVQDZrrkz, + VPMOVQWZ128mr, + VPMOVQWZ128mrk, + VPMOVQWZ128rr, + VPMOVQWZ128rrk, + VPMOVQWZ128rrkz, + VPMOVQWZ256mr, + VPMOVQWZ256mrk, + VPMOVQWZ256rr, + VPMOVQWZ256rrk, + VPMOVQWZ256rrkz, + VPMOVQWZmr, + VPMOVQWZmrk, + VPMOVQWZrr, + VPMOVQWZrrk, + VPMOVQWZrrkz, + VPMOVSDBZ128mr, + VPMOVSDBZ128mrk, + VPMOVSDBZ128rr, + VPMOVSDBZ128rrk, + VPMOVSDBZ128rrkz, + VPMOVSDBZ256mr, + VPMOVSDBZ256mrk, + VPMOVSDBZ256rr, + VPMOVSDBZ256rrk, + VPMOVSDBZ256rrkz, + VPMOVSDBZmr, + VPMOVSDBZmrk, + VPMOVSDBZrr, + VPMOVSDBZrrk, + VPMOVSDBZrrkz, + VPMOVSDWZ128mr, + VPMOVSDWZ128mrk, + VPMOVSDWZ128rr, + VPMOVSDWZ128rrk, + VPMOVSDWZ128rrkz, + VPMOVSDWZ256mr, + VPMOVSDWZ256mrk, + VPMOVSDWZ256rr, + VPMOVSDWZ256rrk, + VPMOVSDWZ256rrkz, + VPMOVSDWZmr, + VPMOVSDWZmrk, + VPMOVSDWZrr, + VPMOVSDWZrrk, + VPMOVSDWZrrkz, + VPMOVSQBZ128mr, + VPMOVSQBZ128mrk, + VPMOVSQBZ128rr, + VPMOVSQBZ128rrk, + VPMOVSQBZ128rrkz, + VPMOVSQBZ256mr, + VPMOVSQBZ256mrk, + VPMOVSQBZ256rr, + VPMOVSQBZ256rrk, + VPMOVSQBZ256rrkz, + VPMOVSQBZmr, + VPMOVSQBZmrk, + VPMOVSQBZrr, + VPMOVSQBZrrk, + VPMOVSQBZrrkz, + VPMOVSQDZ128mr, + VPMOVSQDZ128mrk, + VPMOVSQDZ128rr, + VPMOVSQDZ128rrk, + VPMOVSQDZ128rrkz, + VPMOVSQDZ256mr, + VPMOVSQDZ256mrk, + VPMOVSQDZ256rr, + VPMOVSQDZ256rrk, + VPMOVSQDZ256rrkz, + VPMOVSQDZmr, + VPMOVSQDZmrk, + VPMOVSQDZrr, + VPMOVSQDZrrk, + VPMOVSQDZrrkz, + VPMOVSQWZ128mr, + VPMOVSQWZ128mrk, + VPMOVSQWZ128rr, + VPMOVSQWZ128rrk, + VPMOVSQWZ128rrkz, + VPMOVSQWZ256mr, + VPMOVSQWZ256mrk, + VPMOVSQWZ256rr, + VPMOVSQWZ256rrk, + VPMOVSQWZ256rrkz, + VPMOVSQWZmr, + VPMOVSQWZmrk, + VPMOVSQWZrr, + VPMOVSQWZrrk, + VPMOVSQWZrrkz, + VPMOVSWBZ128mr, + VPMOVSWBZ128mrk, + VPMOVSWBZ128rr, + VPMOVSWBZ128rrk, + VPMOVSWBZ128rrkz, + VPMOVSWBZ256mr, + VPMOVSWBZ256mrk, + VPMOVSWBZ256rr, + VPMOVSWBZ256rrk, + VPMOVSWBZ256rrkz, + VPMOVSWBZmr, + VPMOVSWBZmrk, + VPMOVSWBZrr, + VPMOVSWBZrrk, + VPMOVSWBZrrkz, + VPMOVSXBDYrm, + VPMOVSXBDYrr, + VPMOVSXBDZ128rm, + VPMOVSXBDZ128rmk, + VPMOVSXBDZ128rmkz, + VPMOVSXBDZ128rr, + VPMOVSXBDZ128rrk, + VPMOVSXBDZ128rrkz, + VPMOVSXBDZ256rm, + VPMOVSXBDZ256rmk, + VPMOVSXBDZ256rmkz, + VPMOVSXBDZ256rr, + VPMOVSXBDZ256rrk, + VPMOVSXBDZ256rrkz, + VPMOVSXBDZrm, + VPMOVSXBDZrmk, + VPMOVSXBDZrmkz, + VPMOVSXBDZrr, + VPMOVSXBDZrrk, + VPMOVSXBDZrrkz, + VPMOVSXBDrm, + VPMOVSXBDrr, + VPMOVSXBQYrm, + VPMOVSXBQYrr, + VPMOVSXBQZ128rm, + VPMOVSXBQZ128rmk, + VPMOVSXBQZ128rmkz, + VPMOVSXBQZ128rr, + VPMOVSXBQZ128rrk, + VPMOVSXBQZ128rrkz, + VPMOVSXBQZ256rm, + VPMOVSXBQZ256rmk, + VPMOVSXBQZ256rmkz, + VPMOVSXBQZ256rr, + VPMOVSXBQZ256rrk, + VPMOVSXBQZ256rrkz, + VPMOVSXBQZrm, + VPMOVSXBQZrmk, + VPMOVSXBQZrmkz, + VPMOVSXBQZrr, + VPMOVSXBQZrrk, + VPMOVSXBQZrrkz, + VPMOVSXBQrm, + VPMOVSXBQrr, + VPMOVSXBWYrm, + VPMOVSXBWYrr, + VPMOVSXBWZ128rm, + VPMOVSXBWZ128rmk, + VPMOVSXBWZ128rmkz, + VPMOVSXBWZ128rr, + VPMOVSXBWZ128rrk, + VPMOVSXBWZ128rrkz, + VPMOVSXBWZ256rm, + VPMOVSXBWZ256rmk, + VPMOVSXBWZ256rmkz, + VPMOVSXBWZ256rr, + VPMOVSXBWZ256rrk, + VPMOVSXBWZ256rrkz, + VPMOVSXBWZrm, + VPMOVSXBWZrmk, + VPMOVSXBWZrmkz, + VPMOVSXBWZrr, + VPMOVSXBWZrrk, + VPMOVSXBWZrrkz, + VPMOVSXBWrm, + VPMOVSXBWrr, + VPMOVSXDQYrm, + VPMOVSXDQYrr, + VPMOVSXDQZ128rm, + VPMOVSXDQZ128rmk, + VPMOVSXDQZ128rmkz, + VPMOVSXDQZ128rr, + VPMOVSXDQZ128rrk, + VPMOVSXDQZ128rrkz, + VPMOVSXDQZ256rm, + VPMOVSXDQZ256rmk, + VPMOVSXDQZ256rmkz, + VPMOVSXDQZ256rr, + VPMOVSXDQZ256rrk, + VPMOVSXDQZ256rrkz, + VPMOVSXDQZrm, + VPMOVSXDQZrmk, + VPMOVSXDQZrmkz, + VPMOVSXDQZrr, + VPMOVSXDQZrrk, + VPMOVSXDQZrrkz, + VPMOVSXDQrm, + VPMOVSXDQrr, + VPMOVSXWDYrm, + VPMOVSXWDYrr, + VPMOVSXWDZ128rm, + VPMOVSXWDZ128rmk, + VPMOVSXWDZ128rmkz, + VPMOVSXWDZ128rr, + VPMOVSXWDZ128rrk, + VPMOVSXWDZ128rrkz, + VPMOVSXWDZ256rm, + VPMOVSXWDZ256rmk, + VPMOVSXWDZ256rmkz, + VPMOVSXWDZ256rr, + VPMOVSXWDZ256rrk, + VPMOVSXWDZ256rrkz, + VPMOVSXWDZrm, + VPMOVSXWDZrmk, + VPMOVSXWDZrmkz, + VPMOVSXWDZrr, + VPMOVSXWDZrrk, + VPMOVSXWDZrrkz, + VPMOVSXWDrm, + VPMOVSXWDrr, + VPMOVSXWQYrm, + VPMOVSXWQYrr, + VPMOVSXWQZ128rm, + VPMOVSXWQZ128rmk, + VPMOVSXWQZ128rmkz, + VPMOVSXWQZ128rr, + VPMOVSXWQZ128rrk, + VPMOVSXWQZ128rrkz, + VPMOVSXWQZ256rm, + VPMOVSXWQZ256rmk, + VPMOVSXWQZ256rmkz, + VPMOVSXWQZ256rr, + VPMOVSXWQZ256rrk, + VPMOVSXWQZ256rrkz, + VPMOVSXWQZrm, + VPMOVSXWQZrmk, + VPMOVSXWQZrmkz, + VPMOVSXWQZrr, + VPMOVSXWQZrrk, + VPMOVSXWQZrrkz, + VPMOVSXWQrm, + VPMOVSXWQrr, + VPMOVUSDBZ128mr, + VPMOVUSDBZ128mrk, + VPMOVUSDBZ128rr, + VPMOVUSDBZ128rrk, + VPMOVUSDBZ128rrkz, + VPMOVUSDBZ256mr, + VPMOVUSDBZ256mrk, + VPMOVUSDBZ256rr, + VPMOVUSDBZ256rrk, + VPMOVUSDBZ256rrkz, + VPMOVUSDBZmr, + VPMOVUSDBZmrk, + VPMOVUSDBZrr, + VPMOVUSDBZrrk, + VPMOVUSDBZrrkz, + VPMOVUSDWZ128mr, + VPMOVUSDWZ128mrk, + VPMOVUSDWZ128rr, + VPMOVUSDWZ128rrk, + VPMOVUSDWZ128rrkz, + VPMOVUSDWZ256mr, + VPMOVUSDWZ256mrk, + VPMOVUSDWZ256rr, + VPMOVUSDWZ256rrk, + VPMOVUSDWZ256rrkz, + VPMOVUSDWZmr, + VPMOVUSDWZmrk, + VPMOVUSDWZrr, + VPMOVUSDWZrrk, + VPMOVUSDWZrrkz, + VPMOVUSQBZ128mr, + VPMOVUSQBZ128mrk, + VPMOVUSQBZ128rr, + VPMOVUSQBZ128rrk, + VPMOVUSQBZ128rrkz, + VPMOVUSQBZ256mr, + VPMOVUSQBZ256mrk, + VPMOVUSQBZ256rr, + VPMOVUSQBZ256rrk, + VPMOVUSQBZ256rrkz, + VPMOVUSQBZmr, + VPMOVUSQBZmrk, + VPMOVUSQBZrr, + VPMOVUSQBZrrk, + VPMOVUSQBZrrkz, + VPMOVUSQDZ128mr, + VPMOVUSQDZ128mrk, + VPMOVUSQDZ128rr, + VPMOVUSQDZ128rrk, + VPMOVUSQDZ128rrkz, + VPMOVUSQDZ256mr, + VPMOVUSQDZ256mrk, + VPMOVUSQDZ256rr, + VPMOVUSQDZ256rrk, + VPMOVUSQDZ256rrkz, + VPMOVUSQDZmr, + VPMOVUSQDZmrk, + VPMOVUSQDZrr, + VPMOVUSQDZrrk, + VPMOVUSQDZrrkz, + VPMOVUSQWZ128mr, + VPMOVUSQWZ128mrk, + VPMOVUSQWZ128rr, + VPMOVUSQWZ128rrk, + VPMOVUSQWZ128rrkz, + VPMOVUSQWZ256mr, + VPMOVUSQWZ256mrk, + VPMOVUSQWZ256rr, + VPMOVUSQWZ256rrk, + VPMOVUSQWZ256rrkz, + VPMOVUSQWZmr, + VPMOVUSQWZmrk, + VPMOVUSQWZrr, + VPMOVUSQWZrrk, + VPMOVUSQWZrrkz, + VPMOVUSWBZ128mr, + VPMOVUSWBZ128mrk, + VPMOVUSWBZ128rr, + VPMOVUSWBZ128rrk, + VPMOVUSWBZ128rrkz, + VPMOVUSWBZ256mr, + VPMOVUSWBZ256mrk, + VPMOVUSWBZ256rr, + VPMOVUSWBZ256rrk, + VPMOVUSWBZ256rrkz, + VPMOVUSWBZmr, + VPMOVUSWBZmrk, + VPMOVUSWBZrr, + VPMOVUSWBZrrk, + VPMOVUSWBZrrkz, + VPMOVW2MZ128kr, + VPMOVW2MZ256kr, + VPMOVW2MZkr, + VPMOVWBZ128mr, + VPMOVWBZ128mrk, + VPMOVWBZ128rr, + VPMOVWBZ128rrk, + VPMOVWBZ128rrkz, + VPMOVWBZ256mr, + VPMOVWBZ256mrk, + VPMOVWBZ256rr, + VPMOVWBZ256rrk, + VPMOVWBZ256rrkz, + VPMOVWBZmr, + VPMOVWBZmrk, + VPMOVWBZrr, + VPMOVWBZrrk, + VPMOVWBZrrkz, + VPMOVZXBDYrm, + VPMOVZXBDYrr, + VPMOVZXBDZ128rm, + VPMOVZXBDZ128rmk, + VPMOVZXBDZ128rmkz, + VPMOVZXBDZ128rr, + VPMOVZXBDZ128rrk, + VPMOVZXBDZ128rrkz, + VPMOVZXBDZ256rm, + VPMOVZXBDZ256rmk, + VPMOVZXBDZ256rmkz, + VPMOVZXBDZ256rr, + VPMOVZXBDZ256rrk, + VPMOVZXBDZ256rrkz, + VPMOVZXBDZrm, + VPMOVZXBDZrmk, + VPMOVZXBDZrmkz, + VPMOVZXBDZrr, + VPMOVZXBDZrrk, + VPMOVZXBDZrrkz, + VPMOVZXBDrm, + VPMOVZXBDrr, + VPMOVZXBQYrm, + VPMOVZXBQYrr, + VPMOVZXBQZ128rm, + VPMOVZXBQZ128rmk, + VPMOVZXBQZ128rmkz, + VPMOVZXBQZ128rr, + VPMOVZXBQZ128rrk, + VPMOVZXBQZ128rrkz, + VPMOVZXBQZ256rm, + VPMOVZXBQZ256rmk, + VPMOVZXBQZ256rmkz, + VPMOVZXBQZ256rr, + VPMOVZXBQZ256rrk, + VPMOVZXBQZ256rrkz, + VPMOVZXBQZrm, + VPMOVZXBQZrmk, + VPMOVZXBQZrmkz, + VPMOVZXBQZrr, + VPMOVZXBQZrrk, + VPMOVZXBQZrrkz, + VPMOVZXBQrm, + VPMOVZXBQrr, + VPMOVZXBWYrm, + VPMOVZXBWYrr, + VPMOVZXBWZ128rm, + VPMOVZXBWZ128rmk, + VPMOVZXBWZ128rmkz, + VPMOVZXBWZ128rr, + VPMOVZXBWZ128rrk, + VPMOVZXBWZ128rrkz, + VPMOVZXBWZ256rm, + VPMOVZXBWZ256rmk, + VPMOVZXBWZ256rmkz, + VPMOVZXBWZ256rr, + VPMOVZXBWZ256rrk, + VPMOVZXBWZ256rrkz, + VPMOVZXBWZrm, + VPMOVZXBWZrmk, + VPMOVZXBWZrmkz, + VPMOVZXBWZrr, + VPMOVZXBWZrrk, + VPMOVZXBWZrrkz, + VPMOVZXBWrm, + VPMOVZXBWrr, + VPMOVZXDQYrm, + VPMOVZXDQYrr, + VPMOVZXDQZ128rm, + VPMOVZXDQZ128rmk, + VPMOVZXDQZ128rmkz, + VPMOVZXDQZ128rr, + VPMOVZXDQZ128rrk, + VPMOVZXDQZ128rrkz, + VPMOVZXDQZ256rm, + VPMOVZXDQZ256rmk, + VPMOVZXDQZ256rmkz, + VPMOVZXDQZ256rr, + VPMOVZXDQZ256rrk, + VPMOVZXDQZ256rrkz, + VPMOVZXDQZrm, + VPMOVZXDQZrmk, + VPMOVZXDQZrmkz, + VPMOVZXDQZrr, + VPMOVZXDQZrrk, + VPMOVZXDQZrrkz, + VPMOVZXDQrm, + VPMOVZXDQrr, + VPMOVZXWDYrm, + VPMOVZXWDYrr, + VPMOVZXWDZ128rm, + VPMOVZXWDZ128rmk, + VPMOVZXWDZ128rmkz, + VPMOVZXWDZ128rr, + VPMOVZXWDZ128rrk, + VPMOVZXWDZ128rrkz, + VPMOVZXWDZ256rm, + VPMOVZXWDZ256rmk, + VPMOVZXWDZ256rmkz, + VPMOVZXWDZ256rr, + VPMOVZXWDZ256rrk, + VPMOVZXWDZ256rrkz, + VPMOVZXWDZrm, + VPMOVZXWDZrmk, + VPMOVZXWDZrmkz, + VPMOVZXWDZrr, + VPMOVZXWDZrrk, + VPMOVZXWDZrrkz, + VPMOVZXWDrm, + VPMOVZXWDrr, + VPMOVZXWQYrm, + VPMOVZXWQYrr, + VPMOVZXWQZ128rm, + VPMOVZXWQZ128rmk, + VPMOVZXWQZ128rmkz, + VPMOVZXWQZ128rr, + VPMOVZXWQZ128rrk, + VPMOVZXWQZ128rrkz, + VPMOVZXWQZ256rm, + VPMOVZXWQZ256rmk, + VPMOVZXWQZ256rmkz, + VPMOVZXWQZ256rr, + VPMOVZXWQZ256rrk, + VPMOVZXWQZ256rrkz, + VPMOVZXWQZrm, + VPMOVZXWQZrmk, + VPMOVZXWQZrmkz, + VPMOVZXWQZrr, + VPMOVZXWQZrrk, + VPMOVZXWQZrrkz, + VPMOVZXWQrm, + VPMOVZXWQrr, + VPMULDQYrm, + VPMULDQYrr, + VPMULDQZ128rm, + VPMULDQZ128rmb, + VPMULDQZ128rmbk, + VPMULDQZ128rmbkz, + VPMULDQZ128rmk, + VPMULDQZ128rmkz, + VPMULDQZ128rr, + VPMULDQZ128rrk, + VPMULDQZ128rrkz, + VPMULDQZ256rm, + VPMULDQZ256rmb, + VPMULDQZ256rmbk, + VPMULDQZ256rmbkz, + VPMULDQZ256rmk, + VPMULDQZ256rmkz, + VPMULDQZ256rr, + VPMULDQZ256rrk, + VPMULDQZ256rrkz, + VPMULDQZrm, + VPMULDQZrmb, + VPMULDQZrmbk, + VPMULDQZrmbkz, + VPMULDQZrmk, + VPMULDQZrmkz, + VPMULDQZrr, + VPMULDQZrrk, + VPMULDQZrrkz, + VPMULDQrm, + VPMULDQrr, + VPMULHRSWYrm, + VPMULHRSWYrr, + VPMULHRSWZ128rm, + VPMULHRSWZ128rmk, + VPMULHRSWZ128rmkz, + VPMULHRSWZ128rr, + VPMULHRSWZ128rrk, + VPMULHRSWZ128rrkz, + VPMULHRSWZ256rm, + VPMULHRSWZ256rmk, + VPMULHRSWZ256rmkz, + VPMULHRSWZ256rr, + VPMULHRSWZ256rrk, + VPMULHRSWZ256rrkz, + VPMULHRSWZrm, + VPMULHRSWZrmk, + VPMULHRSWZrmkz, + VPMULHRSWZrr, + VPMULHRSWZrrk, + VPMULHRSWZrrkz, + VPMULHRSWrm, + VPMULHRSWrr, + VPMULHUWYrm, + VPMULHUWYrr, + VPMULHUWZ128rm, + VPMULHUWZ128rmk, + VPMULHUWZ128rmkz, + VPMULHUWZ128rr, + VPMULHUWZ128rrk, + VPMULHUWZ128rrkz, + VPMULHUWZ256rm, + VPMULHUWZ256rmk, + VPMULHUWZ256rmkz, + VPMULHUWZ256rr, + VPMULHUWZ256rrk, + VPMULHUWZ256rrkz, + VPMULHUWZrm, + VPMULHUWZrmk, + VPMULHUWZrmkz, + VPMULHUWZrr, + VPMULHUWZrrk, + VPMULHUWZrrkz, + VPMULHUWrm, + VPMULHUWrr, + VPMULHWYrm, + VPMULHWYrr, + VPMULHWZ128rm, + VPMULHWZ128rmk, + VPMULHWZ128rmkz, + VPMULHWZ128rr, + VPMULHWZ128rrk, + VPMULHWZ128rrkz, + VPMULHWZ256rm, + VPMULHWZ256rmk, + VPMULHWZ256rmkz, + VPMULHWZ256rr, + VPMULHWZ256rrk, + VPMULHWZ256rrkz, + VPMULHWZrm, + VPMULHWZrmk, + VPMULHWZrmkz, + VPMULHWZrr, + VPMULHWZrrk, + VPMULHWZrrkz, + VPMULHWrm, + VPMULHWrr, + VPMULLDYrm, + VPMULLDYrr, + VPMULLDZ128rm, + VPMULLDZ128rmb, + VPMULLDZ128rmbk, + VPMULLDZ128rmbkz, + VPMULLDZ128rmk, + VPMULLDZ128rmkz, + VPMULLDZ128rr, + VPMULLDZ128rrk, + VPMULLDZ128rrkz, + VPMULLDZ256rm, + VPMULLDZ256rmb, + VPMULLDZ256rmbk, + VPMULLDZ256rmbkz, + VPMULLDZ256rmk, + VPMULLDZ256rmkz, + VPMULLDZ256rr, + VPMULLDZ256rrk, + VPMULLDZ256rrkz, + VPMULLDZrm, + VPMULLDZrmb, + VPMULLDZrmbk, + VPMULLDZrmbkz, + VPMULLDZrmk, + VPMULLDZrmkz, + VPMULLDZrr, + VPMULLDZrrk, + VPMULLDZrrkz, + VPMULLDrm, + VPMULLDrr, + VPMULLQZ128rm, + VPMULLQZ128rmb, + VPMULLQZ128rmbk, + VPMULLQZ128rmbkz, + VPMULLQZ128rmk, + VPMULLQZ128rmkz, + VPMULLQZ128rr, + VPMULLQZ128rrk, + VPMULLQZ128rrkz, + VPMULLQZ256rm, + VPMULLQZ256rmb, + VPMULLQZ256rmbk, + VPMULLQZ256rmbkz, + VPMULLQZ256rmk, + VPMULLQZ256rmkz, + VPMULLQZ256rr, + VPMULLQZ256rrk, + VPMULLQZ256rrkz, + VPMULLQZrm, + VPMULLQZrmb, + VPMULLQZrmbk, + VPMULLQZrmbkz, + VPMULLQZrmk, + VPMULLQZrmkz, + VPMULLQZrr, + VPMULLQZrrk, + VPMULLQZrrkz, + VPMULLWYrm, + VPMULLWYrr, + VPMULLWZ128rm, + VPMULLWZ128rmk, + VPMULLWZ128rmkz, + VPMULLWZ128rr, + VPMULLWZ128rrk, + VPMULLWZ128rrkz, + VPMULLWZ256rm, + VPMULLWZ256rmk, + VPMULLWZ256rmkz, + VPMULLWZ256rr, + VPMULLWZ256rrk, + VPMULLWZ256rrkz, + VPMULLWZrm, + VPMULLWZrmk, + VPMULLWZrmkz, + VPMULLWZrr, + VPMULLWZrrk, + VPMULLWZrrkz, + VPMULLWrm, + VPMULLWrr, + VPMULTISHIFTQBZ128rm, + VPMULTISHIFTQBZ128rmb, + VPMULTISHIFTQBZ128rmbk, + VPMULTISHIFTQBZ128rmbkz, + VPMULTISHIFTQBZ128rmk, + VPMULTISHIFTQBZ128rmkz, + VPMULTISHIFTQBZ128rr, + VPMULTISHIFTQBZ128rrk, + VPMULTISHIFTQBZ128rrkz, + VPMULTISHIFTQBZ256rm, + VPMULTISHIFTQBZ256rmb, + VPMULTISHIFTQBZ256rmbk, + VPMULTISHIFTQBZ256rmbkz, + VPMULTISHIFTQBZ256rmk, + VPMULTISHIFTQBZ256rmkz, + VPMULTISHIFTQBZ256rr, + VPMULTISHIFTQBZ256rrk, + VPMULTISHIFTQBZ256rrkz, + VPMULTISHIFTQBZrm, + VPMULTISHIFTQBZrmb, + VPMULTISHIFTQBZrmbk, + VPMULTISHIFTQBZrmbkz, + VPMULTISHIFTQBZrmk, + VPMULTISHIFTQBZrmkz, + VPMULTISHIFTQBZrr, + VPMULTISHIFTQBZrrk, + VPMULTISHIFTQBZrrkz, + VPMULUDQYrm, + VPMULUDQYrr, + VPMULUDQZ128rm, + VPMULUDQZ128rmb, + VPMULUDQZ128rmbk, + VPMULUDQZ128rmbkz, + VPMULUDQZ128rmk, + VPMULUDQZ128rmkz, + VPMULUDQZ128rr, + VPMULUDQZ128rrk, + VPMULUDQZ128rrkz, + VPMULUDQZ256rm, + VPMULUDQZ256rmb, + VPMULUDQZ256rmbk, + VPMULUDQZ256rmbkz, + VPMULUDQZ256rmk, + VPMULUDQZ256rmkz, + VPMULUDQZ256rr, + VPMULUDQZ256rrk, + VPMULUDQZ256rrkz, + VPMULUDQZrm, + VPMULUDQZrmb, + VPMULUDQZrmbk, + VPMULUDQZrmbkz, + VPMULUDQZrmk, + VPMULUDQZrmkz, + VPMULUDQZrr, + VPMULUDQZrrk, + VPMULUDQZrrkz, + VPMULUDQrm, + VPMULUDQrr, + VPOPCNTBZ128rm, + VPOPCNTBZ128rmk, + VPOPCNTBZ128rmkz, + VPOPCNTBZ128rr, + VPOPCNTBZ128rrk, + VPOPCNTBZ128rrkz, + VPOPCNTBZ256rm, + VPOPCNTBZ256rmk, + VPOPCNTBZ256rmkz, + VPOPCNTBZ256rr, + VPOPCNTBZ256rrk, + VPOPCNTBZ256rrkz, + VPOPCNTBZrm, + VPOPCNTBZrmk, + VPOPCNTBZrmkz, + VPOPCNTBZrr, + VPOPCNTBZrrk, + VPOPCNTBZrrkz, + VPOPCNTDZ128rm, + VPOPCNTDZ128rmb, + VPOPCNTDZ128rmbk, + VPOPCNTDZ128rmbkz, + VPOPCNTDZ128rmk, + VPOPCNTDZ128rmkz, + VPOPCNTDZ128rr, + VPOPCNTDZ128rrk, + VPOPCNTDZ128rrkz, + VPOPCNTDZ256rm, + VPOPCNTDZ256rmb, + VPOPCNTDZ256rmbk, + VPOPCNTDZ256rmbkz, + VPOPCNTDZ256rmk, + VPOPCNTDZ256rmkz, + VPOPCNTDZ256rr, + VPOPCNTDZ256rrk, + VPOPCNTDZ256rrkz, + VPOPCNTDZrm, + VPOPCNTDZrmb, + VPOPCNTDZrmbk, + VPOPCNTDZrmbkz, + VPOPCNTDZrmk, + VPOPCNTDZrmkz, + VPOPCNTDZrr, + VPOPCNTDZrrk, + VPOPCNTDZrrkz, + VPOPCNTQZ128rm, + VPOPCNTQZ128rmb, + VPOPCNTQZ128rmbk, + VPOPCNTQZ128rmbkz, + VPOPCNTQZ128rmk, + VPOPCNTQZ128rmkz, + VPOPCNTQZ128rr, + VPOPCNTQZ128rrk, + VPOPCNTQZ128rrkz, + VPOPCNTQZ256rm, + VPOPCNTQZ256rmb, + VPOPCNTQZ256rmbk, + VPOPCNTQZ256rmbkz, + VPOPCNTQZ256rmk, + VPOPCNTQZ256rmkz, + VPOPCNTQZ256rr, + VPOPCNTQZ256rrk, + VPOPCNTQZ256rrkz, + VPOPCNTQZrm, + VPOPCNTQZrmb, + VPOPCNTQZrmbk, + VPOPCNTQZrmbkz, + VPOPCNTQZrmk, + VPOPCNTQZrmkz, + VPOPCNTQZrr, + VPOPCNTQZrrk, + VPOPCNTQZrrkz, + VPOPCNTWZ128rm, + VPOPCNTWZ128rmk, + VPOPCNTWZ128rmkz, + VPOPCNTWZ128rr, + VPOPCNTWZ128rrk, + VPOPCNTWZ128rrkz, + VPOPCNTWZ256rm, + VPOPCNTWZ256rmk, + VPOPCNTWZ256rmkz, + VPOPCNTWZ256rr, + VPOPCNTWZ256rrk, + VPOPCNTWZ256rrkz, + VPOPCNTWZrm, + VPOPCNTWZrmk, + VPOPCNTWZrmkz, + VPOPCNTWZrr, + VPOPCNTWZrrk, + VPOPCNTWZrrkz, + VPORDZ128rm, + VPORDZ128rmb, + VPORDZ128rmbk, + VPORDZ128rmbkz, + VPORDZ128rmk, + VPORDZ128rmkz, + VPORDZ128rr, + VPORDZ128rrk, + VPORDZ128rrkz, + VPORDZ256rm, + VPORDZ256rmb, + VPORDZ256rmbk, + VPORDZ256rmbkz, + VPORDZ256rmk, + VPORDZ256rmkz, + VPORDZ256rr, + VPORDZ256rrk, + VPORDZ256rrkz, + VPORDZrm, + VPORDZrmb, + VPORDZrmbk, + VPORDZrmbkz, + VPORDZrmk, + VPORDZrmkz, + VPORDZrr, + VPORDZrrk, + VPORDZrrkz, + VPORQZ128rm, + VPORQZ128rmb, + VPORQZ128rmbk, + VPORQZ128rmbkz, + VPORQZ128rmk, + VPORQZ128rmkz, + VPORQZ128rr, + VPORQZ128rrk, + VPORQZ128rrkz, + VPORQZ256rm, + VPORQZ256rmb, + VPORQZ256rmbk, + VPORQZ256rmbkz, + VPORQZ256rmk, + VPORQZ256rmkz, + VPORQZ256rr, + VPORQZ256rrk, + VPORQZ256rrkz, + VPORQZrm, + VPORQZrmb, + VPORQZrmbk, + VPORQZrmbkz, + VPORQZrmk, + VPORQZrmkz, + VPORQZrr, + VPORQZrrk, + VPORQZrrkz, + VPORYrm, + VPORYrr, + VPORrm, + VPORrr, + VPPERMrmr, + VPPERMrrm, + VPPERMrrr, + VPPERMrrr_REV, + VPROLDZ128mbi, + VPROLDZ128mbik, + VPROLDZ128mbikz, + VPROLDZ128mi, + VPROLDZ128mik, + VPROLDZ128mikz, + VPROLDZ128ri, + VPROLDZ128rik, + VPROLDZ128rikz, + VPROLDZ256mbi, + VPROLDZ256mbik, + VPROLDZ256mbikz, + VPROLDZ256mi, + VPROLDZ256mik, + VPROLDZ256mikz, + VPROLDZ256ri, + VPROLDZ256rik, + VPROLDZ256rikz, + VPROLDZmbi, + VPROLDZmbik, + VPROLDZmbikz, + VPROLDZmi, + VPROLDZmik, + VPROLDZmikz, + VPROLDZri, + VPROLDZrik, + VPROLDZrikz, + VPROLQZ128mbi, + VPROLQZ128mbik, + VPROLQZ128mbikz, + VPROLQZ128mi, + VPROLQZ128mik, + VPROLQZ128mikz, + VPROLQZ128ri, + VPROLQZ128rik, + VPROLQZ128rikz, + VPROLQZ256mbi, + VPROLQZ256mbik, + VPROLQZ256mbikz, + VPROLQZ256mi, + VPROLQZ256mik, + VPROLQZ256mikz, + VPROLQZ256ri, + VPROLQZ256rik, + VPROLQZ256rikz, + VPROLQZmbi, + VPROLQZmbik, + VPROLQZmbikz, + VPROLQZmi, + VPROLQZmik, + VPROLQZmikz, + VPROLQZri, + VPROLQZrik, + VPROLQZrikz, + VPROLVDZ128rm, + VPROLVDZ128rmb, + VPROLVDZ128rmbk, + VPROLVDZ128rmbkz, + VPROLVDZ128rmk, + VPROLVDZ128rmkz, + VPROLVDZ128rr, + VPROLVDZ128rrk, + VPROLVDZ128rrkz, + VPROLVDZ256rm, + VPROLVDZ256rmb, + VPROLVDZ256rmbk, + VPROLVDZ256rmbkz, + VPROLVDZ256rmk, + VPROLVDZ256rmkz, + VPROLVDZ256rr, + VPROLVDZ256rrk, + VPROLVDZ256rrkz, + VPROLVDZrm, + VPROLVDZrmb, + VPROLVDZrmbk, + VPROLVDZrmbkz, + VPROLVDZrmk, + VPROLVDZrmkz, + VPROLVDZrr, + VPROLVDZrrk, + VPROLVDZrrkz, + VPROLVQZ128rm, + VPROLVQZ128rmb, + VPROLVQZ128rmbk, + VPROLVQZ128rmbkz, + VPROLVQZ128rmk, + VPROLVQZ128rmkz, + VPROLVQZ128rr, + VPROLVQZ128rrk, + VPROLVQZ128rrkz, + VPROLVQZ256rm, + VPROLVQZ256rmb, + VPROLVQZ256rmbk, + VPROLVQZ256rmbkz, + VPROLVQZ256rmk, + VPROLVQZ256rmkz, + VPROLVQZ256rr, + VPROLVQZ256rrk, + VPROLVQZ256rrkz, + VPROLVQZrm, + VPROLVQZrmb, + VPROLVQZrmbk, + VPROLVQZrmbkz, + VPROLVQZrmk, + VPROLVQZrmkz, + VPROLVQZrr, + VPROLVQZrrk, + VPROLVQZrrkz, + VPRORDZ128mbi, + VPRORDZ128mbik, + VPRORDZ128mbikz, + VPRORDZ128mi, + VPRORDZ128mik, + VPRORDZ128mikz, + VPRORDZ128ri, + VPRORDZ128rik, + VPRORDZ128rikz, + VPRORDZ256mbi, + VPRORDZ256mbik, + VPRORDZ256mbikz, + VPRORDZ256mi, + VPRORDZ256mik, + VPRORDZ256mikz, + VPRORDZ256ri, + VPRORDZ256rik, + VPRORDZ256rikz, + VPRORDZmbi, + VPRORDZmbik, + VPRORDZmbikz, + VPRORDZmi, + VPRORDZmik, + VPRORDZmikz, + VPRORDZri, + VPRORDZrik, + VPRORDZrikz, + VPRORQZ128mbi, + VPRORQZ128mbik, + VPRORQZ128mbikz, + VPRORQZ128mi, + VPRORQZ128mik, + VPRORQZ128mikz, + VPRORQZ128ri, + VPRORQZ128rik, + VPRORQZ128rikz, + VPRORQZ256mbi, + VPRORQZ256mbik, + VPRORQZ256mbikz, + VPRORQZ256mi, + VPRORQZ256mik, + VPRORQZ256mikz, + VPRORQZ256ri, + VPRORQZ256rik, + VPRORQZ256rikz, + VPRORQZmbi, + VPRORQZmbik, + VPRORQZmbikz, + VPRORQZmi, + VPRORQZmik, + VPRORQZmikz, + VPRORQZri, + VPRORQZrik, + VPRORQZrikz, + VPRORVDZ128rm, + VPRORVDZ128rmb, + VPRORVDZ128rmbk, + VPRORVDZ128rmbkz, + VPRORVDZ128rmk, + VPRORVDZ128rmkz, + VPRORVDZ128rr, + VPRORVDZ128rrk, + VPRORVDZ128rrkz, + VPRORVDZ256rm, + VPRORVDZ256rmb, + VPRORVDZ256rmbk, + VPRORVDZ256rmbkz, + VPRORVDZ256rmk, + VPRORVDZ256rmkz, + VPRORVDZ256rr, + VPRORVDZ256rrk, + VPRORVDZ256rrkz, + VPRORVDZrm, + VPRORVDZrmb, + VPRORVDZrmbk, + VPRORVDZrmbkz, + VPRORVDZrmk, + VPRORVDZrmkz, + VPRORVDZrr, + VPRORVDZrrk, + VPRORVDZrrkz, + VPRORVQZ128rm, + VPRORVQZ128rmb, + VPRORVQZ128rmbk, + VPRORVQZ128rmbkz, + VPRORVQZ128rmk, + VPRORVQZ128rmkz, + VPRORVQZ128rr, + VPRORVQZ128rrk, + VPRORVQZ128rrkz, + VPRORVQZ256rm, + VPRORVQZ256rmb, + VPRORVQZ256rmbk, + VPRORVQZ256rmbkz, + VPRORVQZ256rmk, + VPRORVQZ256rmkz, + VPRORVQZ256rr, + VPRORVQZ256rrk, + VPRORVQZ256rrkz, + VPRORVQZrm, + VPRORVQZrmb, + VPRORVQZrmbk, + VPRORVQZrmbkz, + VPRORVQZrmk, + VPRORVQZrmkz, + VPRORVQZrr, + VPRORVQZrrk, + VPRORVQZrrkz, + VPROTBmi, + VPROTBmr, + VPROTBri, + VPROTBrm, + VPROTBrr, + VPROTBrr_REV, + VPROTDmi, + VPROTDmr, + VPROTDri, + VPROTDrm, + VPROTDrr, + VPROTDrr_REV, + VPROTQmi, + VPROTQmr, + VPROTQri, + VPROTQrm, + VPROTQrr, + VPROTQrr_REV, + VPROTWmi, + VPROTWmr, + VPROTWri, + VPROTWrm, + VPROTWrr, + VPROTWrr_REV, + VPSADBWYrm, + VPSADBWYrr, + VPSADBWZ128rm, + VPSADBWZ128rr, + VPSADBWZ256rm, + VPSADBWZ256rr, + VPSADBWZrm, + VPSADBWZrr, + VPSADBWrm, + VPSADBWrr, + VPSCATTERDDZ128mr, + VPSCATTERDDZ256mr, + VPSCATTERDDZmr, + VPSCATTERDQZ128mr, + VPSCATTERDQZ256mr, + VPSCATTERDQZmr, + VPSCATTERQDZ128mr, + VPSCATTERQDZ256mr, + VPSCATTERQDZmr, + VPSCATTERQQZ128mr, + VPSCATTERQQZ256mr, + VPSCATTERQQZmr, + VPSHABmr, + VPSHABrm, + VPSHABrr, + VPSHABrr_REV, + VPSHADmr, + VPSHADrm, + VPSHADrr, + VPSHADrr_REV, + VPSHAQmr, + VPSHAQrm, + VPSHAQrr, + VPSHAQrr_REV, + VPSHAWmr, + VPSHAWrm, + VPSHAWrr, + VPSHAWrr_REV, + VPSHLBmr, + VPSHLBrm, + VPSHLBrr, + VPSHLBrr_REV, + VPSHLDDZ128rmbi, + VPSHLDDZ128rmbik, + VPSHLDDZ128rmbikz, + VPSHLDDZ128rmi, + VPSHLDDZ128rmik, + VPSHLDDZ128rmikz, + VPSHLDDZ128rri, + VPSHLDDZ128rrik, + VPSHLDDZ128rrikz, + VPSHLDDZ256rmbi, + VPSHLDDZ256rmbik, + VPSHLDDZ256rmbikz, + VPSHLDDZ256rmi, + VPSHLDDZ256rmik, + VPSHLDDZ256rmikz, + VPSHLDDZ256rri, + VPSHLDDZ256rrik, + VPSHLDDZ256rrikz, + VPSHLDDZrmbi, + VPSHLDDZrmbik, + VPSHLDDZrmbikz, + VPSHLDDZrmi, + VPSHLDDZrmik, + VPSHLDDZrmikz, + VPSHLDDZrri, + VPSHLDDZrrik, + VPSHLDDZrrikz, + VPSHLDQZ128rmbi, + VPSHLDQZ128rmbik, + VPSHLDQZ128rmbikz, + VPSHLDQZ128rmi, + VPSHLDQZ128rmik, + VPSHLDQZ128rmikz, + VPSHLDQZ128rri, + VPSHLDQZ128rrik, + VPSHLDQZ128rrikz, + VPSHLDQZ256rmbi, + VPSHLDQZ256rmbik, + VPSHLDQZ256rmbikz, + VPSHLDQZ256rmi, + VPSHLDQZ256rmik, + VPSHLDQZ256rmikz, + VPSHLDQZ256rri, + VPSHLDQZ256rrik, + VPSHLDQZ256rrikz, + VPSHLDQZrmbi, + VPSHLDQZrmbik, + VPSHLDQZrmbikz, + VPSHLDQZrmi, + VPSHLDQZrmik, + VPSHLDQZrmikz, + VPSHLDQZrri, + VPSHLDQZrrik, + VPSHLDQZrrikz, + VPSHLDVDZ128m, + VPSHLDVDZ128mb, + VPSHLDVDZ128mbk, + VPSHLDVDZ128mbkz, + VPSHLDVDZ128mk, + VPSHLDVDZ128mkz, + VPSHLDVDZ128r, + VPSHLDVDZ128rk, + VPSHLDVDZ128rkz, + VPSHLDVDZ256m, + VPSHLDVDZ256mb, + VPSHLDVDZ256mbk, + VPSHLDVDZ256mbkz, + VPSHLDVDZ256mk, + VPSHLDVDZ256mkz, + VPSHLDVDZ256r, + VPSHLDVDZ256rk, + VPSHLDVDZ256rkz, + VPSHLDVDZm, + VPSHLDVDZmb, + VPSHLDVDZmbk, + VPSHLDVDZmbkz, + VPSHLDVDZmk, + VPSHLDVDZmkz, + VPSHLDVDZr, + VPSHLDVDZrk, + VPSHLDVDZrkz, + VPSHLDVQZ128m, + VPSHLDVQZ128mb, + VPSHLDVQZ128mbk, + VPSHLDVQZ128mbkz, + VPSHLDVQZ128mk, + VPSHLDVQZ128mkz, + VPSHLDVQZ128r, + VPSHLDVQZ128rk, + VPSHLDVQZ128rkz, + VPSHLDVQZ256m, + VPSHLDVQZ256mb, + VPSHLDVQZ256mbk, + VPSHLDVQZ256mbkz, + VPSHLDVQZ256mk, + VPSHLDVQZ256mkz, + VPSHLDVQZ256r, + VPSHLDVQZ256rk, + VPSHLDVQZ256rkz, + VPSHLDVQZm, + VPSHLDVQZmb, + VPSHLDVQZmbk, + VPSHLDVQZmbkz, + VPSHLDVQZmk, + VPSHLDVQZmkz, + VPSHLDVQZr, + VPSHLDVQZrk, + VPSHLDVQZrkz, + VPSHLDVWZ128m, + VPSHLDVWZ128mk, + VPSHLDVWZ128mkz, + VPSHLDVWZ128r, + VPSHLDVWZ128rk, + VPSHLDVWZ128rkz, + VPSHLDVWZ256m, + VPSHLDVWZ256mk, + VPSHLDVWZ256mkz, + VPSHLDVWZ256r, + VPSHLDVWZ256rk, + VPSHLDVWZ256rkz, + VPSHLDVWZm, + VPSHLDVWZmk, + VPSHLDVWZmkz, + VPSHLDVWZr, + VPSHLDVWZrk, + VPSHLDVWZrkz, + VPSHLDWZ128rmi, + VPSHLDWZ128rmik, + VPSHLDWZ128rmikz, + VPSHLDWZ128rri, + VPSHLDWZ128rrik, + VPSHLDWZ128rrikz, + VPSHLDWZ256rmi, + VPSHLDWZ256rmik, + VPSHLDWZ256rmikz, + VPSHLDWZ256rri, + VPSHLDWZ256rrik, + VPSHLDWZ256rrikz, + VPSHLDWZrmi, + VPSHLDWZrmik, + VPSHLDWZrmikz, + VPSHLDWZrri, + VPSHLDWZrrik, + VPSHLDWZrrikz, + VPSHLDmr, + VPSHLDrm, + VPSHLDrr, + VPSHLDrr_REV, + VPSHLQmr, + VPSHLQrm, + VPSHLQrr, + VPSHLQrr_REV, + VPSHLWmr, + VPSHLWrm, + VPSHLWrr, + VPSHLWrr_REV, + VPSHRDDZ128rmbi, + VPSHRDDZ128rmbik, + VPSHRDDZ128rmbikz, + VPSHRDDZ128rmi, + VPSHRDDZ128rmik, + VPSHRDDZ128rmikz, + VPSHRDDZ128rri, + VPSHRDDZ128rrik, + VPSHRDDZ128rrikz, + VPSHRDDZ256rmbi, + VPSHRDDZ256rmbik, + VPSHRDDZ256rmbikz, + VPSHRDDZ256rmi, + VPSHRDDZ256rmik, + VPSHRDDZ256rmikz, + VPSHRDDZ256rri, + VPSHRDDZ256rrik, + VPSHRDDZ256rrikz, + VPSHRDDZrmbi, + VPSHRDDZrmbik, + VPSHRDDZrmbikz, + VPSHRDDZrmi, + VPSHRDDZrmik, + VPSHRDDZrmikz, + VPSHRDDZrri, + VPSHRDDZrrik, + VPSHRDDZrrikz, + VPSHRDQZ128rmbi, + VPSHRDQZ128rmbik, + VPSHRDQZ128rmbikz, + VPSHRDQZ128rmi, + VPSHRDQZ128rmik, + VPSHRDQZ128rmikz, + VPSHRDQZ128rri, + VPSHRDQZ128rrik, + VPSHRDQZ128rrikz, + VPSHRDQZ256rmbi, + VPSHRDQZ256rmbik, + VPSHRDQZ256rmbikz, + VPSHRDQZ256rmi, + VPSHRDQZ256rmik, + VPSHRDQZ256rmikz, + VPSHRDQZ256rri, + VPSHRDQZ256rrik, + VPSHRDQZ256rrikz, + VPSHRDQZrmbi, + VPSHRDQZrmbik, + VPSHRDQZrmbikz, + VPSHRDQZrmi, + VPSHRDQZrmik, + VPSHRDQZrmikz, + VPSHRDQZrri, + VPSHRDQZrrik, + VPSHRDQZrrikz, + VPSHRDVDZ128m, + VPSHRDVDZ128mb, + VPSHRDVDZ128mbk, + VPSHRDVDZ128mbkz, + VPSHRDVDZ128mk, + VPSHRDVDZ128mkz, + VPSHRDVDZ128r, + VPSHRDVDZ128rk, + VPSHRDVDZ128rkz, + VPSHRDVDZ256m, + VPSHRDVDZ256mb, + VPSHRDVDZ256mbk, + VPSHRDVDZ256mbkz, + VPSHRDVDZ256mk, + VPSHRDVDZ256mkz, + VPSHRDVDZ256r, + VPSHRDVDZ256rk, + VPSHRDVDZ256rkz, + VPSHRDVDZm, + VPSHRDVDZmb, + VPSHRDVDZmbk, + VPSHRDVDZmbkz, + VPSHRDVDZmk, + VPSHRDVDZmkz, + VPSHRDVDZr, + VPSHRDVDZrk, + VPSHRDVDZrkz, + VPSHRDVQZ128m, + VPSHRDVQZ128mb, + VPSHRDVQZ128mbk, + VPSHRDVQZ128mbkz, + VPSHRDVQZ128mk, + VPSHRDVQZ128mkz, + VPSHRDVQZ128r, + VPSHRDVQZ128rk, + VPSHRDVQZ128rkz, + VPSHRDVQZ256m, + VPSHRDVQZ256mb, + VPSHRDVQZ256mbk, + VPSHRDVQZ256mbkz, + VPSHRDVQZ256mk, + VPSHRDVQZ256mkz, + VPSHRDVQZ256r, + VPSHRDVQZ256rk, + VPSHRDVQZ256rkz, + VPSHRDVQZm, + VPSHRDVQZmb, + VPSHRDVQZmbk, + VPSHRDVQZmbkz, + VPSHRDVQZmk, + VPSHRDVQZmkz, + VPSHRDVQZr, + VPSHRDVQZrk, + VPSHRDVQZrkz, + VPSHRDVWZ128m, + VPSHRDVWZ128mk, + VPSHRDVWZ128mkz, + VPSHRDVWZ128r, + VPSHRDVWZ128rk, + VPSHRDVWZ128rkz, + VPSHRDVWZ256m, + VPSHRDVWZ256mk, + VPSHRDVWZ256mkz, + VPSHRDVWZ256r, + VPSHRDVWZ256rk, + VPSHRDVWZ256rkz, + VPSHRDVWZm, + VPSHRDVWZmk, + VPSHRDVWZmkz, + VPSHRDVWZr, + VPSHRDVWZrk, + VPSHRDVWZrkz, + VPSHRDWZ128rmi, + VPSHRDWZ128rmik, + VPSHRDWZ128rmikz, + VPSHRDWZ128rri, + VPSHRDWZ128rrik, + VPSHRDWZ128rrikz, + VPSHRDWZ256rmi, + VPSHRDWZ256rmik, + VPSHRDWZ256rmikz, + VPSHRDWZ256rri, + VPSHRDWZ256rrik, + VPSHRDWZ256rrikz, + VPSHRDWZrmi, + VPSHRDWZrmik, + VPSHRDWZrmikz, + VPSHRDWZrri, + VPSHRDWZrrik, + VPSHRDWZrrikz, + VPSHUFBITQMBZ128rm, + VPSHUFBITQMBZ128rmk, + VPSHUFBITQMBZ128rr, + VPSHUFBITQMBZ128rrk, + VPSHUFBITQMBZ256rm, + VPSHUFBITQMBZ256rmk, + VPSHUFBITQMBZ256rr, + VPSHUFBITQMBZ256rrk, + VPSHUFBITQMBZrm, + VPSHUFBITQMBZrmk, + VPSHUFBITQMBZrr, + VPSHUFBITQMBZrrk, + VPSHUFBYrm, + VPSHUFBYrr, + VPSHUFBZ128rm, + VPSHUFBZ128rmk, + VPSHUFBZ128rmkz, + VPSHUFBZ128rr, + VPSHUFBZ128rrk, + VPSHUFBZ128rrkz, + VPSHUFBZ256rm, + VPSHUFBZ256rmk, + VPSHUFBZ256rmkz, + VPSHUFBZ256rr, + VPSHUFBZ256rrk, + VPSHUFBZ256rrkz, + VPSHUFBZrm, + VPSHUFBZrmk, + VPSHUFBZrmkz, + VPSHUFBZrr, + VPSHUFBZrrk, + VPSHUFBZrrkz, + VPSHUFBrm, + VPSHUFBrr, + VPSHUFDYmi, + VPSHUFDYri, + VPSHUFDZ128mbi, + VPSHUFDZ128mbik, + VPSHUFDZ128mbikz, + VPSHUFDZ128mi, + VPSHUFDZ128mik, + VPSHUFDZ128mikz, + VPSHUFDZ128ri, + VPSHUFDZ128rik, + VPSHUFDZ128rikz, + VPSHUFDZ256mbi, + VPSHUFDZ256mbik, + VPSHUFDZ256mbikz, + VPSHUFDZ256mi, + VPSHUFDZ256mik, + VPSHUFDZ256mikz, + VPSHUFDZ256ri, + VPSHUFDZ256rik, + VPSHUFDZ256rikz, + VPSHUFDZmbi, + VPSHUFDZmbik, + VPSHUFDZmbikz, + VPSHUFDZmi, + VPSHUFDZmik, + VPSHUFDZmikz, + VPSHUFDZri, + VPSHUFDZrik, + VPSHUFDZrikz, + VPSHUFDmi, + VPSHUFDri, + VPSHUFHWYmi, + VPSHUFHWYri, + VPSHUFHWZ128mi, + VPSHUFHWZ128mik, + VPSHUFHWZ128mikz, + VPSHUFHWZ128ri, + VPSHUFHWZ128rik, + VPSHUFHWZ128rikz, + VPSHUFHWZ256mi, + VPSHUFHWZ256mik, + VPSHUFHWZ256mikz, + VPSHUFHWZ256ri, + VPSHUFHWZ256rik, + VPSHUFHWZ256rikz, + VPSHUFHWZmi, + VPSHUFHWZmik, + VPSHUFHWZmikz, + VPSHUFHWZri, + VPSHUFHWZrik, + VPSHUFHWZrikz, + VPSHUFHWmi, + VPSHUFHWri, + VPSHUFLWYmi, + VPSHUFLWYri, + VPSHUFLWZ128mi, + VPSHUFLWZ128mik, + VPSHUFLWZ128mikz, + VPSHUFLWZ128ri, + VPSHUFLWZ128rik, + VPSHUFLWZ128rikz, + VPSHUFLWZ256mi, + VPSHUFLWZ256mik, + VPSHUFLWZ256mikz, + VPSHUFLWZ256ri, + VPSHUFLWZ256rik, + VPSHUFLWZ256rikz, + VPSHUFLWZmi, + VPSHUFLWZmik, + VPSHUFLWZmikz, + VPSHUFLWZri, + VPSHUFLWZrik, + VPSHUFLWZrikz, + VPSHUFLWmi, + VPSHUFLWri, + VPSIGNBYrm, + VPSIGNBYrr, + VPSIGNBrm, + VPSIGNBrr, + VPSIGNDYrm, + VPSIGNDYrr, + VPSIGNDrm, + VPSIGNDrr, + VPSIGNWYrm, + VPSIGNWYrr, + VPSIGNWrm, + VPSIGNWrr, + VPSLLDQYri, + VPSLLDQZ128mi, + VPSLLDQZ128ri, + VPSLLDQZ256mi, + VPSLLDQZ256ri, + VPSLLDQZmi, + VPSLLDQZri, + VPSLLDQri, + VPSLLDYri, + VPSLLDYrm, + VPSLLDYrr, + VPSLLDZ128mbi, + VPSLLDZ128mbik, + VPSLLDZ128mbikz, + VPSLLDZ128mi, + VPSLLDZ128mik, + VPSLLDZ128mikz, + VPSLLDZ128ri, + VPSLLDZ128rik, + VPSLLDZ128rikz, + VPSLLDZ128rm, + VPSLLDZ128rmk, + VPSLLDZ128rmkz, + VPSLLDZ128rr, + VPSLLDZ128rrk, + VPSLLDZ128rrkz, + VPSLLDZ256mbi, + VPSLLDZ256mbik, + VPSLLDZ256mbikz, + VPSLLDZ256mi, + VPSLLDZ256mik, + VPSLLDZ256mikz, + VPSLLDZ256ri, + VPSLLDZ256rik, + VPSLLDZ256rikz, + VPSLLDZ256rm, + VPSLLDZ256rmk, + VPSLLDZ256rmkz, + VPSLLDZ256rr, + VPSLLDZ256rrk, + VPSLLDZ256rrkz, + VPSLLDZmbi, + VPSLLDZmbik, + VPSLLDZmbikz, + VPSLLDZmi, + VPSLLDZmik, + VPSLLDZmikz, + VPSLLDZri, + VPSLLDZrik, + VPSLLDZrikz, + VPSLLDZrm, + VPSLLDZrmk, + VPSLLDZrmkz, + VPSLLDZrr, + VPSLLDZrrk, + VPSLLDZrrkz, + VPSLLDri, + VPSLLDrm, + VPSLLDrr, + VPSLLQYri, + VPSLLQYrm, + VPSLLQYrr, + VPSLLQZ128mbi, + VPSLLQZ128mbik, + VPSLLQZ128mbikz, + VPSLLQZ128mi, + VPSLLQZ128mik, + VPSLLQZ128mikz, + VPSLLQZ128ri, + VPSLLQZ128rik, + VPSLLQZ128rikz, + VPSLLQZ128rm, + VPSLLQZ128rmk, + VPSLLQZ128rmkz, + VPSLLQZ128rr, + VPSLLQZ128rrk, + VPSLLQZ128rrkz, + VPSLLQZ256mbi, + VPSLLQZ256mbik, + VPSLLQZ256mbikz, + VPSLLQZ256mi, + VPSLLQZ256mik, + VPSLLQZ256mikz, + VPSLLQZ256ri, + VPSLLQZ256rik, + VPSLLQZ256rikz, + VPSLLQZ256rm, + VPSLLQZ256rmk, + VPSLLQZ256rmkz, + VPSLLQZ256rr, + VPSLLQZ256rrk, + VPSLLQZ256rrkz, + VPSLLQZmbi, + VPSLLQZmbik, + VPSLLQZmbikz, + VPSLLQZmi, + VPSLLQZmik, + VPSLLQZmikz, + VPSLLQZri, + VPSLLQZrik, + VPSLLQZrikz, + VPSLLQZrm, + VPSLLQZrmk, + VPSLLQZrmkz, + VPSLLQZrr, + VPSLLQZrrk, + VPSLLQZrrkz, + VPSLLQri, + VPSLLQrm, + VPSLLQrr, + VPSLLVDYrm, + VPSLLVDYrr, + VPSLLVDZ128rm, + VPSLLVDZ128rmb, + VPSLLVDZ128rmbk, + VPSLLVDZ128rmbkz, + VPSLLVDZ128rmk, + VPSLLVDZ128rmkz, + VPSLLVDZ128rr, + VPSLLVDZ128rrk, + VPSLLVDZ128rrkz, + VPSLLVDZ256rm, + VPSLLVDZ256rmb, + VPSLLVDZ256rmbk, + VPSLLVDZ256rmbkz, + VPSLLVDZ256rmk, + VPSLLVDZ256rmkz, + VPSLLVDZ256rr, + VPSLLVDZ256rrk, + VPSLLVDZ256rrkz, + VPSLLVDZrm, + VPSLLVDZrmb, + VPSLLVDZrmbk, + VPSLLVDZrmbkz, + VPSLLVDZrmk, + VPSLLVDZrmkz, + VPSLLVDZrr, + VPSLLVDZrrk, + VPSLLVDZrrkz, + VPSLLVDrm, + VPSLLVDrr, + VPSLLVQYrm, + VPSLLVQYrr, + VPSLLVQZ128rm, + VPSLLVQZ128rmb, + VPSLLVQZ128rmbk, + VPSLLVQZ128rmbkz, + VPSLLVQZ128rmk, + VPSLLVQZ128rmkz, + VPSLLVQZ128rr, + VPSLLVQZ128rrk, + VPSLLVQZ128rrkz, + VPSLLVQZ256rm, + VPSLLVQZ256rmb, + VPSLLVQZ256rmbk, + VPSLLVQZ256rmbkz, + VPSLLVQZ256rmk, + VPSLLVQZ256rmkz, + VPSLLVQZ256rr, + VPSLLVQZ256rrk, + VPSLLVQZ256rrkz, + VPSLLVQZrm, + VPSLLVQZrmb, + VPSLLVQZrmbk, + VPSLLVQZrmbkz, + VPSLLVQZrmk, + VPSLLVQZrmkz, + VPSLLVQZrr, + VPSLLVQZrrk, + VPSLLVQZrrkz, + VPSLLVQrm, + VPSLLVQrr, + VPSLLVWZ128rm, + VPSLLVWZ128rmk, + VPSLLVWZ128rmkz, + VPSLLVWZ128rr, + VPSLLVWZ128rrk, + VPSLLVWZ128rrkz, + VPSLLVWZ256rm, + VPSLLVWZ256rmk, + VPSLLVWZ256rmkz, + VPSLLVWZ256rr, + VPSLLVWZ256rrk, + VPSLLVWZ256rrkz, + VPSLLVWZrm, + VPSLLVWZrmk, + VPSLLVWZrmkz, + VPSLLVWZrr, + VPSLLVWZrrk, + VPSLLVWZrrkz, + VPSLLWYri, + VPSLLWYrm, + VPSLLWYrr, + VPSLLWZ128mi, + VPSLLWZ128mik, + VPSLLWZ128mikz, + VPSLLWZ128ri, + VPSLLWZ128rik, + VPSLLWZ128rikz, + VPSLLWZ128rm, + VPSLLWZ128rmk, + VPSLLWZ128rmkz, + VPSLLWZ128rr, + VPSLLWZ128rrk, + VPSLLWZ128rrkz, + VPSLLWZ256mi, + VPSLLWZ256mik, + VPSLLWZ256mikz, + VPSLLWZ256ri, + VPSLLWZ256rik, + VPSLLWZ256rikz, + VPSLLWZ256rm, + VPSLLWZ256rmk, + VPSLLWZ256rmkz, + VPSLLWZ256rr, + VPSLLWZ256rrk, + VPSLLWZ256rrkz, + VPSLLWZmi, + VPSLLWZmik, + VPSLLWZmikz, + VPSLLWZri, + VPSLLWZrik, + VPSLLWZrikz, + VPSLLWZrm, + VPSLLWZrmk, + VPSLLWZrmkz, + VPSLLWZrr, + VPSLLWZrrk, + VPSLLWZrrkz, + VPSLLWri, + VPSLLWrm, + VPSLLWrr, + VPSRADYri, + VPSRADYrm, + VPSRADYrr, + VPSRADZ128mbi, + VPSRADZ128mbik, + VPSRADZ128mbikz, + VPSRADZ128mi, + VPSRADZ128mik, + VPSRADZ128mikz, + VPSRADZ128ri, + VPSRADZ128rik, + VPSRADZ128rikz, + VPSRADZ128rm, + VPSRADZ128rmk, + VPSRADZ128rmkz, + VPSRADZ128rr, + VPSRADZ128rrk, + VPSRADZ128rrkz, + VPSRADZ256mbi, + VPSRADZ256mbik, + VPSRADZ256mbikz, + VPSRADZ256mi, + VPSRADZ256mik, + VPSRADZ256mikz, + VPSRADZ256ri, + VPSRADZ256rik, + VPSRADZ256rikz, + VPSRADZ256rm, + VPSRADZ256rmk, + VPSRADZ256rmkz, + VPSRADZ256rr, + VPSRADZ256rrk, + VPSRADZ256rrkz, + VPSRADZmbi, + VPSRADZmbik, + VPSRADZmbikz, + VPSRADZmi, + VPSRADZmik, + VPSRADZmikz, + VPSRADZri, + VPSRADZrik, + VPSRADZrikz, + VPSRADZrm, + VPSRADZrmk, + VPSRADZrmkz, + VPSRADZrr, + VPSRADZrrk, + VPSRADZrrkz, + VPSRADri, + VPSRADrm, + VPSRADrr, + VPSRAQZ128mbi, + VPSRAQZ128mbik, + VPSRAQZ128mbikz, + VPSRAQZ128mi, + VPSRAQZ128mik, + VPSRAQZ128mikz, + VPSRAQZ128ri, + VPSRAQZ128rik, + VPSRAQZ128rikz, + VPSRAQZ128rm, + VPSRAQZ128rmk, + VPSRAQZ128rmkz, + VPSRAQZ128rr, + VPSRAQZ128rrk, + VPSRAQZ128rrkz, + VPSRAQZ256mbi, + VPSRAQZ256mbik, + VPSRAQZ256mbikz, + VPSRAQZ256mi, + VPSRAQZ256mik, + VPSRAQZ256mikz, + VPSRAQZ256ri, + VPSRAQZ256rik, + VPSRAQZ256rikz, + VPSRAQZ256rm, + VPSRAQZ256rmk, + VPSRAQZ256rmkz, + VPSRAQZ256rr, + VPSRAQZ256rrk, + VPSRAQZ256rrkz, + VPSRAQZmbi, + VPSRAQZmbik, + VPSRAQZmbikz, + VPSRAQZmi, + VPSRAQZmik, + VPSRAQZmikz, + VPSRAQZri, + VPSRAQZrik, + VPSRAQZrikz, + VPSRAQZrm, + VPSRAQZrmk, + VPSRAQZrmkz, + VPSRAQZrr, + VPSRAQZrrk, + VPSRAQZrrkz, + VPSRAVDYrm, + VPSRAVDYrr, + VPSRAVDZ128rm, + VPSRAVDZ128rmb, + VPSRAVDZ128rmbk, + VPSRAVDZ128rmbkz, + VPSRAVDZ128rmk, + VPSRAVDZ128rmkz, + VPSRAVDZ128rr, + VPSRAVDZ128rrk, + VPSRAVDZ128rrkz, + VPSRAVDZ256rm, + VPSRAVDZ256rmb, + VPSRAVDZ256rmbk, + VPSRAVDZ256rmbkz, + VPSRAVDZ256rmk, + VPSRAVDZ256rmkz, + VPSRAVDZ256rr, + VPSRAVDZ256rrk, + VPSRAVDZ256rrkz, + VPSRAVDZrm, + VPSRAVDZrmb, + VPSRAVDZrmbk, + VPSRAVDZrmbkz, + VPSRAVDZrmk, + VPSRAVDZrmkz, + VPSRAVDZrr, + VPSRAVDZrrk, + VPSRAVDZrrkz, + VPSRAVDrm, + VPSRAVDrr, + VPSRAVQZ128rm, + VPSRAVQZ128rmb, + VPSRAVQZ128rmbk, + VPSRAVQZ128rmbkz, + VPSRAVQZ128rmk, + VPSRAVQZ128rmkz, + VPSRAVQZ128rr, + VPSRAVQZ128rrk, + VPSRAVQZ128rrkz, + VPSRAVQZ256rm, + VPSRAVQZ256rmb, + VPSRAVQZ256rmbk, + VPSRAVQZ256rmbkz, + VPSRAVQZ256rmk, + VPSRAVQZ256rmkz, + VPSRAVQZ256rr, + VPSRAVQZ256rrk, + VPSRAVQZ256rrkz, + VPSRAVQZrm, + VPSRAVQZrmb, + VPSRAVQZrmbk, + VPSRAVQZrmbkz, + VPSRAVQZrmk, + VPSRAVQZrmkz, + VPSRAVQZrr, + VPSRAVQZrrk, + VPSRAVQZrrkz, + VPSRAVWZ128rm, + VPSRAVWZ128rmk, + VPSRAVWZ128rmkz, + VPSRAVWZ128rr, + VPSRAVWZ128rrk, + VPSRAVWZ128rrkz, + VPSRAVWZ256rm, + VPSRAVWZ256rmk, + VPSRAVWZ256rmkz, + VPSRAVWZ256rr, + VPSRAVWZ256rrk, + VPSRAVWZ256rrkz, + VPSRAVWZrm, + VPSRAVWZrmk, + VPSRAVWZrmkz, + VPSRAVWZrr, + VPSRAVWZrrk, + VPSRAVWZrrkz, + VPSRAWYri, + VPSRAWYrm, + VPSRAWYrr, + VPSRAWZ128mi, + VPSRAWZ128mik, + VPSRAWZ128mikz, + VPSRAWZ128ri, + VPSRAWZ128rik, + VPSRAWZ128rikz, + VPSRAWZ128rm, + VPSRAWZ128rmk, + VPSRAWZ128rmkz, + VPSRAWZ128rr, + VPSRAWZ128rrk, + VPSRAWZ128rrkz, + VPSRAWZ256mi, + VPSRAWZ256mik, + VPSRAWZ256mikz, + VPSRAWZ256ri, + VPSRAWZ256rik, + VPSRAWZ256rikz, + VPSRAWZ256rm, + VPSRAWZ256rmk, + VPSRAWZ256rmkz, + VPSRAWZ256rr, + VPSRAWZ256rrk, + VPSRAWZ256rrkz, + VPSRAWZmi, + VPSRAWZmik, + VPSRAWZmikz, + VPSRAWZri, + VPSRAWZrik, + VPSRAWZrikz, + VPSRAWZrm, + VPSRAWZrmk, + VPSRAWZrmkz, + VPSRAWZrr, + VPSRAWZrrk, + VPSRAWZrrkz, + VPSRAWri, + VPSRAWrm, + VPSRAWrr, + VPSRLDQYri, + VPSRLDQZ128mi, + VPSRLDQZ128ri, + VPSRLDQZ256mi, + VPSRLDQZ256ri, + VPSRLDQZmi, + VPSRLDQZri, + VPSRLDQri, + VPSRLDYri, + VPSRLDYrm, + VPSRLDYrr, + VPSRLDZ128mbi, + VPSRLDZ128mbik, + VPSRLDZ128mbikz, + VPSRLDZ128mi, + VPSRLDZ128mik, + VPSRLDZ128mikz, + VPSRLDZ128ri, + VPSRLDZ128rik, + VPSRLDZ128rikz, + VPSRLDZ128rm, + VPSRLDZ128rmk, + VPSRLDZ128rmkz, + VPSRLDZ128rr, + VPSRLDZ128rrk, + VPSRLDZ128rrkz, + VPSRLDZ256mbi, + VPSRLDZ256mbik, + VPSRLDZ256mbikz, + VPSRLDZ256mi, + VPSRLDZ256mik, + VPSRLDZ256mikz, + VPSRLDZ256ri, + VPSRLDZ256rik, + VPSRLDZ256rikz, + VPSRLDZ256rm, + VPSRLDZ256rmk, + VPSRLDZ256rmkz, + VPSRLDZ256rr, + VPSRLDZ256rrk, + VPSRLDZ256rrkz, + VPSRLDZmbi, + VPSRLDZmbik, + VPSRLDZmbikz, + VPSRLDZmi, + VPSRLDZmik, + VPSRLDZmikz, + VPSRLDZri, + VPSRLDZrik, + VPSRLDZrikz, + VPSRLDZrm, + VPSRLDZrmk, + VPSRLDZrmkz, + VPSRLDZrr, + VPSRLDZrrk, + VPSRLDZrrkz, + VPSRLDri, + VPSRLDrm, + VPSRLDrr, + VPSRLQYri, + VPSRLQYrm, + VPSRLQYrr, + VPSRLQZ128mbi, + VPSRLQZ128mbik, + VPSRLQZ128mbikz, + VPSRLQZ128mi, + VPSRLQZ128mik, + VPSRLQZ128mikz, + VPSRLQZ128ri, + VPSRLQZ128rik, + VPSRLQZ128rikz, + VPSRLQZ128rm, + VPSRLQZ128rmk, + VPSRLQZ128rmkz, + VPSRLQZ128rr, + VPSRLQZ128rrk, + VPSRLQZ128rrkz, + VPSRLQZ256mbi, + VPSRLQZ256mbik, + VPSRLQZ256mbikz, + VPSRLQZ256mi, + VPSRLQZ256mik, + VPSRLQZ256mikz, + VPSRLQZ256ri, + VPSRLQZ256rik, + VPSRLQZ256rikz, + VPSRLQZ256rm, + VPSRLQZ256rmk, + VPSRLQZ256rmkz, + VPSRLQZ256rr, + VPSRLQZ256rrk, + VPSRLQZ256rrkz, + VPSRLQZmbi, + VPSRLQZmbik, + VPSRLQZmbikz, + VPSRLQZmi, + VPSRLQZmik, + VPSRLQZmikz, + VPSRLQZri, + VPSRLQZrik, + VPSRLQZrikz, + VPSRLQZrm, + VPSRLQZrmk, + VPSRLQZrmkz, + VPSRLQZrr, + VPSRLQZrrk, + VPSRLQZrrkz, + VPSRLQri, + VPSRLQrm, + VPSRLQrr, + VPSRLVDYrm, + VPSRLVDYrr, + VPSRLVDZ128rm, + VPSRLVDZ128rmb, + VPSRLVDZ128rmbk, + VPSRLVDZ128rmbkz, + VPSRLVDZ128rmk, + VPSRLVDZ128rmkz, + VPSRLVDZ128rr, + VPSRLVDZ128rrk, + VPSRLVDZ128rrkz, + VPSRLVDZ256rm, + VPSRLVDZ256rmb, + VPSRLVDZ256rmbk, + VPSRLVDZ256rmbkz, + VPSRLVDZ256rmk, + VPSRLVDZ256rmkz, + VPSRLVDZ256rr, + VPSRLVDZ256rrk, + VPSRLVDZ256rrkz, + VPSRLVDZrm, + VPSRLVDZrmb, + VPSRLVDZrmbk, + VPSRLVDZrmbkz, + VPSRLVDZrmk, + VPSRLVDZrmkz, + VPSRLVDZrr, + VPSRLVDZrrk, + VPSRLVDZrrkz, + VPSRLVDrm, + VPSRLVDrr, + VPSRLVQYrm, + VPSRLVQYrr, + VPSRLVQZ128rm, + VPSRLVQZ128rmb, + VPSRLVQZ128rmbk, + VPSRLVQZ128rmbkz, + VPSRLVQZ128rmk, + VPSRLVQZ128rmkz, + VPSRLVQZ128rr, + VPSRLVQZ128rrk, + VPSRLVQZ128rrkz, + VPSRLVQZ256rm, + VPSRLVQZ256rmb, + VPSRLVQZ256rmbk, + VPSRLVQZ256rmbkz, + VPSRLVQZ256rmk, + VPSRLVQZ256rmkz, + VPSRLVQZ256rr, + VPSRLVQZ256rrk, + VPSRLVQZ256rrkz, + VPSRLVQZrm, + VPSRLVQZrmb, + VPSRLVQZrmbk, + VPSRLVQZrmbkz, + VPSRLVQZrmk, + VPSRLVQZrmkz, + VPSRLVQZrr, + VPSRLVQZrrk, + VPSRLVQZrrkz, + VPSRLVQrm, + VPSRLVQrr, + VPSRLVWZ128rm, + VPSRLVWZ128rmk, + VPSRLVWZ128rmkz, + VPSRLVWZ128rr, + VPSRLVWZ128rrk, + VPSRLVWZ128rrkz, + VPSRLVWZ256rm, + VPSRLVWZ256rmk, + VPSRLVWZ256rmkz, + VPSRLVWZ256rr, + VPSRLVWZ256rrk, + VPSRLVWZ256rrkz, + VPSRLVWZrm, + VPSRLVWZrmk, + VPSRLVWZrmkz, + VPSRLVWZrr, + VPSRLVWZrrk, + VPSRLVWZrrkz, + VPSRLWYri, + VPSRLWYrm, + VPSRLWYrr, + VPSRLWZ128mi, + VPSRLWZ128mik, + VPSRLWZ128mikz, + VPSRLWZ128ri, + VPSRLWZ128rik, + VPSRLWZ128rikz, + VPSRLWZ128rm, + VPSRLWZ128rmk, + VPSRLWZ128rmkz, + VPSRLWZ128rr, + VPSRLWZ128rrk, + VPSRLWZ128rrkz, + VPSRLWZ256mi, + VPSRLWZ256mik, + VPSRLWZ256mikz, + VPSRLWZ256ri, + VPSRLWZ256rik, + VPSRLWZ256rikz, + VPSRLWZ256rm, + VPSRLWZ256rmk, + VPSRLWZ256rmkz, + VPSRLWZ256rr, + VPSRLWZ256rrk, + VPSRLWZ256rrkz, + VPSRLWZmi, + VPSRLWZmik, + VPSRLWZmikz, + VPSRLWZri, + VPSRLWZrik, + VPSRLWZrikz, + VPSRLWZrm, + VPSRLWZrmk, + VPSRLWZrmkz, + VPSRLWZrr, + VPSRLWZrrk, + VPSRLWZrrkz, + VPSRLWri, + VPSRLWrm, + VPSRLWrr, + VPSUBBYrm, + VPSUBBYrr, + VPSUBBZ128rm, + VPSUBBZ128rmk, + VPSUBBZ128rmkz, + VPSUBBZ128rr, + VPSUBBZ128rrk, + VPSUBBZ128rrkz, + VPSUBBZ256rm, + VPSUBBZ256rmk, + VPSUBBZ256rmkz, + VPSUBBZ256rr, + VPSUBBZ256rrk, + VPSUBBZ256rrkz, + VPSUBBZrm, + VPSUBBZrmk, + VPSUBBZrmkz, + VPSUBBZrr, + VPSUBBZrrk, + VPSUBBZrrkz, + VPSUBBrm, + VPSUBBrr, + VPSUBDYrm, + VPSUBDYrr, + VPSUBDZ128rm, + VPSUBDZ128rmb, + VPSUBDZ128rmbk, + VPSUBDZ128rmbkz, + VPSUBDZ128rmk, + VPSUBDZ128rmkz, + VPSUBDZ128rr, + VPSUBDZ128rrk, + VPSUBDZ128rrkz, + VPSUBDZ256rm, + VPSUBDZ256rmb, + VPSUBDZ256rmbk, + VPSUBDZ256rmbkz, + VPSUBDZ256rmk, + VPSUBDZ256rmkz, + VPSUBDZ256rr, + VPSUBDZ256rrk, + VPSUBDZ256rrkz, + VPSUBDZrm, + VPSUBDZrmb, + VPSUBDZrmbk, + VPSUBDZrmbkz, + VPSUBDZrmk, + VPSUBDZrmkz, + VPSUBDZrr, + VPSUBDZrrk, + VPSUBDZrrkz, + VPSUBDrm, + VPSUBDrr, + VPSUBQYrm, + VPSUBQYrr, + VPSUBQZ128rm, + VPSUBQZ128rmb, + VPSUBQZ128rmbk, + VPSUBQZ128rmbkz, + VPSUBQZ128rmk, + VPSUBQZ128rmkz, + VPSUBQZ128rr, + VPSUBQZ128rrk, + VPSUBQZ128rrkz, + VPSUBQZ256rm, + VPSUBQZ256rmb, + VPSUBQZ256rmbk, + VPSUBQZ256rmbkz, + VPSUBQZ256rmk, + VPSUBQZ256rmkz, + VPSUBQZ256rr, + VPSUBQZ256rrk, + VPSUBQZ256rrkz, + VPSUBQZrm, + VPSUBQZrmb, + VPSUBQZrmbk, + VPSUBQZrmbkz, + VPSUBQZrmk, + VPSUBQZrmkz, + VPSUBQZrr, + VPSUBQZrrk, + VPSUBQZrrkz, + VPSUBQrm, + VPSUBQrr, + VPSUBSBYrm, + VPSUBSBYrr, + VPSUBSBZ128rm, + VPSUBSBZ128rmk, + VPSUBSBZ128rmkz, + VPSUBSBZ128rr, + VPSUBSBZ128rrk, + VPSUBSBZ128rrkz, + VPSUBSBZ256rm, + VPSUBSBZ256rmk, + VPSUBSBZ256rmkz, + VPSUBSBZ256rr, + VPSUBSBZ256rrk, + VPSUBSBZ256rrkz, + VPSUBSBZrm, + VPSUBSBZrmk, + VPSUBSBZrmkz, + VPSUBSBZrr, + VPSUBSBZrrk, + VPSUBSBZrrkz, + VPSUBSBrm, + VPSUBSBrr, + VPSUBSWYrm, + VPSUBSWYrr, + VPSUBSWZ128rm, + VPSUBSWZ128rmk, + VPSUBSWZ128rmkz, + VPSUBSWZ128rr, + VPSUBSWZ128rrk, + VPSUBSWZ128rrkz, + VPSUBSWZ256rm, + VPSUBSWZ256rmk, + VPSUBSWZ256rmkz, + VPSUBSWZ256rr, + VPSUBSWZ256rrk, + VPSUBSWZ256rrkz, + VPSUBSWZrm, + VPSUBSWZrmk, + VPSUBSWZrmkz, + VPSUBSWZrr, + VPSUBSWZrrk, + VPSUBSWZrrkz, + VPSUBSWrm, + VPSUBSWrr, + VPSUBUSBYrm, + VPSUBUSBYrr, + VPSUBUSBZ128rm, + VPSUBUSBZ128rmk, + VPSUBUSBZ128rmkz, + VPSUBUSBZ128rr, + VPSUBUSBZ128rrk, + VPSUBUSBZ128rrkz, + VPSUBUSBZ256rm, + VPSUBUSBZ256rmk, + VPSUBUSBZ256rmkz, + VPSUBUSBZ256rr, + VPSUBUSBZ256rrk, + VPSUBUSBZ256rrkz, + VPSUBUSBZrm, + VPSUBUSBZrmk, + VPSUBUSBZrmkz, + VPSUBUSBZrr, + VPSUBUSBZrrk, + VPSUBUSBZrrkz, + VPSUBUSBrm, + VPSUBUSBrr, + VPSUBUSWYrm, + VPSUBUSWYrr, + VPSUBUSWZ128rm, + VPSUBUSWZ128rmk, + VPSUBUSWZ128rmkz, + VPSUBUSWZ128rr, + VPSUBUSWZ128rrk, + VPSUBUSWZ128rrkz, + VPSUBUSWZ256rm, + VPSUBUSWZ256rmk, + VPSUBUSWZ256rmkz, + VPSUBUSWZ256rr, + VPSUBUSWZ256rrk, + VPSUBUSWZ256rrkz, + VPSUBUSWZrm, + VPSUBUSWZrmk, + VPSUBUSWZrmkz, + VPSUBUSWZrr, + VPSUBUSWZrrk, + VPSUBUSWZrrkz, + VPSUBUSWrm, + VPSUBUSWrr, + VPSUBWYrm, + VPSUBWYrr, + VPSUBWZ128rm, + VPSUBWZ128rmk, + VPSUBWZ128rmkz, + VPSUBWZ128rr, + VPSUBWZ128rrk, + VPSUBWZ128rrkz, + VPSUBWZ256rm, + VPSUBWZ256rmk, + VPSUBWZ256rmkz, + VPSUBWZ256rr, + VPSUBWZ256rrk, + VPSUBWZ256rrkz, + VPSUBWZrm, + VPSUBWZrmk, + VPSUBWZrmkz, + VPSUBWZrr, + VPSUBWZrrk, + VPSUBWZrrkz, + VPSUBWrm, + VPSUBWrr, + VPTERNLOGDZ128rmbi, + VPTERNLOGDZ128rmbik, + VPTERNLOGDZ128rmbikz, + VPTERNLOGDZ128rmi, + VPTERNLOGDZ128rmik, + VPTERNLOGDZ128rmikz, + VPTERNLOGDZ128rri, + VPTERNLOGDZ128rrik, + VPTERNLOGDZ128rrikz, + VPTERNLOGDZ256rmbi, + VPTERNLOGDZ256rmbik, + VPTERNLOGDZ256rmbikz, + VPTERNLOGDZ256rmi, + VPTERNLOGDZ256rmik, + VPTERNLOGDZ256rmikz, + VPTERNLOGDZ256rri, + VPTERNLOGDZ256rrik, + VPTERNLOGDZ256rrikz, + VPTERNLOGDZrmbi, + VPTERNLOGDZrmbik, + VPTERNLOGDZrmbikz, + VPTERNLOGDZrmi, + VPTERNLOGDZrmik, + VPTERNLOGDZrmikz, + VPTERNLOGDZrri, + VPTERNLOGDZrrik, + VPTERNLOGDZrrikz, + VPTERNLOGQZ128rmbi, + VPTERNLOGQZ128rmbik, + VPTERNLOGQZ128rmbikz, + VPTERNLOGQZ128rmi, + VPTERNLOGQZ128rmik, + VPTERNLOGQZ128rmikz, + VPTERNLOGQZ128rri, + VPTERNLOGQZ128rrik, + VPTERNLOGQZ128rrikz, + VPTERNLOGQZ256rmbi, + VPTERNLOGQZ256rmbik, + VPTERNLOGQZ256rmbikz, + VPTERNLOGQZ256rmi, + VPTERNLOGQZ256rmik, + VPTERNLOGQZ256rmikz, + VPTERNLOGQZ256rri, + VPTERNLOGQZ256rrik, + VPTERNLOGQZ256rrikz, + VPTERNLOGQZrmbi, + VPTERNLOGQZrmbik, + VPTERNLOGQZrmbikz, + VPTERNLOGQZrmi, + VPTERNLOGQZrmik, + VPTERNLOGQZrmikz, + VPTERNLOGQZrri, + VPTERNLOGQZrrik, + VPTERNLOGQZrrikz, + VPTESTMBZ128rm, + VPTESTMBZ128rmk, + VPTESTMBZ128rr, + VPTESTMBZ128rrk, + VPTESTMBZ256rm, + VPTESTMBZ256rmk, + VPTESTMBZ256rr, + VPTESTMBZ256rrk, + VPTESTMBZrm, + VPTESTMBZrmk, + VPTESTMBZrr, + VPTESTMBZrrk, + VPTESTMDZ128rm, + VPTESTMDZ128rmb, + VPTESTMDZ128rmbk, + VPTESTMDZ128rmk, + VPTESTMDZ128rr, + VPTESTMDZ128rrk, + VPTESTMDZ256rm, + VPTESTMDZ256rmb, + VPTESTMDZ256rmbk, + VPTESTMDZ256rmk, + VPTESTMDZ256rr, + VPTESTMDZ256rrk, + VPTESTMDZrm, + VPTESTMDZrmb, + VPTESTMDZrmbk, + VPTESTMDZrmk, + VPTESTMDZrr, + VPTESTMDZrrk, + VPTESTMQZ128rm, + VPTESTMQZ128rmb, + VPTESTMQZ128rmbk, + VPTESTMQZ128rmk, + VPTESTMQZ128rr, + VPTESTMQZ128rrk, + VPTESTMQZ256rm, + VPTESTMQZ256rmb, + VPTESTMQZ256rmbk, + VPTESTMQZ256rmk, + VPTESTMQZ256rr, + VPTESTMQZ256rrk, + VPTESTMQZrm, + VPTESTMQZrmb, + VPTESTMQZrmbk, + VPTESTMQZrmk, + VPTESTMQZrr, + VPTESTMQZrrk, + VPTESTMWZ128rm, + VPTESTMWZ128rmk, + VPTESTMWZ128rr, + VPTESTMWZ128rrk, + VPTESTMWZ256rm, + VPTESTMWZ256rmk, + VPTESTMWZ256rr, + VPTESTMWZ256rrk, + VPTESTMWZrm, + VPTESTMWZrmk, + VPTESTMWZrr, + VPTESTMWZrrk, + VPTESTNMBZ128rm, + VPTESTNMBZ128rmk, + VPTESTNMBZ128rr, + VPTESTNMBZ128rrk, + VPTESTNMBZ256rm, + VPTESTNMBZ256rmk, + VPTESTNMBZ256rr, + VPTESTNMBZ256rrk, + VPTESTNMBZrm, + VPTESTNMBZrmk, + VPTESTNMBZrr, + VPTESTNMBZrrk, + VPTESTNMDZ128rm, + VPTESTNMDZ128rmb, + VPTESTNMDZ128rmbk, + VPTESTNMDZ128rmk, + VPTESTNMDZ128rr, + VPTESTNMDZ128rrk, + VPTESTNMDZ256rm, + VPTESTNMDZ256rmb, + VPTESTNMDZ256rmbk, + VPTESTNMDZ256rmk, + VPTESTNMDZ256rr, + VPTESTNMDZ256rrk, + VPTESTNMDZrm, + VPTESTNMDZrmb, + VPTESTNMDZrmbk, + VPTESTNMDZrmk, + VPTESTNMDZrr, + VPTESTNMDZrrk, + VPTESTNMQZ128rm, + VPTESTNMQZ128rmb, + VPTESTNMQZ128rmbk, + VPTESTNMQZ128rmk, + VPTESTNMQZ128rr, + VPTESTNMQZ128rrk, + VPTESTNMQZ256rm, + VPTESTNMQZ256rmb, + VPTESTNMQZ256rmbk, + VPTESTNMQZ256rmk, + VPTESTNMQZ256rr, + VPTESTNMQZ256rrk, + VPTESTNMQZrm, + VPTESTNMQZrmb, + VPTESTNMQZrmbk, + VPTESTNMQZrmk, + VPTESTNMQZrr, + VPTESTNMQZrrk, + VPTESTNMWZ128rm, + VPTESTNMWZ128rmk, + VPTESTNMWZ128rr, + VPTESTNMWZ128rrk, + VPTESTNMWZ256rm, + VPTESTNMWZ256rmk, + VPTESTNMWZ256rr, + VPTESTNMWZ256rrk, + VPTESTNMWZrm, + VPTESTNMWZrmk, + VPTESTNMWZrr, + VPTESTNMWZrrk, + VPTESTYrm, + VPTESTYrr, + VPTESTrm, + VPTESTrr, + VPUNPCKHBWYrm, + VPUNPCKHBWYrr, + VPUNPCKHBWZ128rm, + VPUNPCKHBWZ128rmk, + VPUNPCKHBWZ128rmkz, + VPUNPCKHBWZ128rr, + VPUNPCKHBWZ128rrk, + VPUNPCKHBWZ128rrkz, + VPUNPCKHBWZ256rm, + VPUNPCKHBWZ256rmk, + VPUNPCKHBWZ256rmkz, + VPUNPCKHBWZ256rr, + VPUNPCKHBWZ256rrk, + VPUNPCKHBWZ256rrkz, + VPUNPCKHBWZrm, + VPUNPCKHBWZrmk, + VPUNPCKHBWZrmkz, + VPUNPCKHBWZrr, + VPUNPCKHBWZrrk, + VPUNPCKHBWZrrkz, + VPUNPCKHBWrm, + VPUNPCKHBWrr, + VPUNPCKHDQYrm, + VPUNPCKHDQYrr, + VPUNPCKHDQZ128rm, + VPUNPCKHDQZ128rmb, + VPUNPCKHDQZ128rmbk, + VPUNPCKHDQZ128rmbkz, + VPUNPCKHDQZ128rmk, + VPUNPCKHDQZ128rmkz, + VPUNPCKHDQZ128rr, + VPUNPCKHDQZ128rrk, + VPUNPCKHDQZ128rrkz, + VPUNPCKHDQZ256rm, + VPUNPCKHDQZ256rmb, + VPUNPCKHDQZ256rmbk, + VPUNPCKHDQZ256rmbkz, + VPUNPCKHDQZ256rmk, + VPUNPCKHDQZ256rmkz, + VPUNPCKHDQZ256rr, + VPUNPCKHDQZ256rrk, + VPUNPCKHDQZ256rrkz, + VPUNPCKHDQZrm, + VPUNPCKHDQZrmb, + VPUNPCKHDQZrmbk, + VPUNPCKHDQZrmbkz, + VPUNPCKHDQZrmk, + VPUNPCKHDQZrmkz, + VPUNPCKHDQZrr, + VPUNPCKHDQZrrk, + VPUNPCKHDQZrrkz, + VPUNPCKHDQrm, + VPUNPCKHDQrr, + VPUNPCKHQDQYrm, + VPUNPCKHQDQYrr, + VPUNPCKHQDQZ128rm, + VPUNPCKHQDQZ128rmb, + VPUNPCKHQDQZ128rmbk, + VPUNPCKHQDQZ128rmbkz, + VPUNPCKHQDQZ128rmk, + VPUNPCKHQDQZ128rmkz, + VPUNPCKHQDQZ128rr, + VPUNPCKHQDQZ128rrk, + VPUNPCKHQDQZ128rrkz, + VPUNPCKHQDQZ256rm, + VPUNPCKHQDQZ256rmb, + VPUNPCKHQDQZ256rmbk, + VPUNPCKHQDQZ256rmbkz, + VPUNPCKHQDQZ256rmk, + VPUNPCKHQDQZ256rmkz, + VPUNPCKHQDQZ256rr, + VPUNPCKHQDQZ256rrk, + VPUNPCKHQDQZ256rrkz, + VPUNPCKHQDQZrm, + VPUNPCKHQDQZrmb, + VPUNPCKHQDQZrmbk, + VPUNPCKHQDQZrmbkz, + VPUNPCKHQDQZrmk, + VPUNPCKHQDQZrmkz, + VPUNPCKHQDQZrr, + VPUNPCKHQDQZrrk, + VPUNPCKHQDQZrrkz, + VPUNPCKHQDQrm, + VPUNPCKHQDQrr, + VPUNPCKHWDYrm, + VPUNPCKHWDYrr, + VPUNPCKHWDZ128rm, + VPUNPCKHWDZ128rmk, + VPUNPCKHWDZ128rmkz, + VPUNPCKHWDZ128rr, + VPUNPCKHWDZ128rrk, + VPUNPCKHWDZ128rrkz, + VPUNPCKHWDZ256rm, + VPUNPCKHWDZ256rmk, + VPUNPCKHWDZ256rmkz, + VPUNPCKHWDZ256rr, + VPUNPCKHWDZ256rrk, + VPUNPCKHWDZ256rrkz, + VPUNPCKHWDZrm, + VPUNPCKHWDZrmk, + VPUNPCKHWDZrmkz, + VPUNPCKHWDZrr, + VPUNPCKHWDZrrk, + VPUNPCKHWDZrrkz, + VPUNPCKHWDrm, + VPUNPCKHWDrr, + VPUNPCKLBWYrm, + VPUNPCKLBWYrr, + VPUNPCKLBWZ128rm, + VPUNPCKLBWZ128rmk, + VPUNPCKLBWZ128rmkz, + VPUNPCKLBWZ128rr, + VPUNPCKLBWZ128rrk, + VPUNPCKLBWZ128rrkz, + VPUNPCKLBWZ256rm, + VPUNPCKLBWZ256rmk, + VPUNPCKLBWZ256rmkz, + VPUNPCKLBWZ256rr, + VPUNPCKLBWZ256rrk, + VPUNPCKLBWZ256rrkz, + VPUNPCKLBWZrm, + VPUNPCKLBWZrmk, + VPUNPCKLBWZrmkz, + VPUNPCKLBWZrr, + VPUNPCKLBWZrrk, + VPUNPCKLBWZrrkz, + VPUNPCKLBWrm, + VPUNPCKLBWrr, + VPUNPCKLDQYrm, + VPUNPCKLDQYrr, + VPUNPCKLDQZ128rm, + VPUNPCKLDQZ128rmb, + VPUNPCKLDQZ128rmbk, + VPUNPCKLDQZ128rmbkz, + VPUNPCKLDQZ128rmk, + VPUNPCKLDQZ128rmkz, + VPUNPCKLDQZ128rr, + VPUNPCKLDQZ128rrk, + VPUNPCKLDQZ128rrkz, + VPUNPCKLDQZ256rm, + VPUNPCKLDQZ256rmb, + VPUNPCKLDQZ256rmbk, + VPUNPCKLDQZ256rmbkz, + VPUNPCKLDQZ256rmk, + VPUNPCKLDQZ256rmkz, + VPUNPCKLDQZ256rr, + VPUNPCKLDQZ256rrk, + VPUNPCKLDQZ256rrkz, + VPUNPCKLDQZrm, + VPUNPCKLDQZrmb, + VPUNPCKLDQZrmbk, + VPUNPCKLDQZrmbkz, + VPUNPCKLDQZrmk, + VPUNPCKLDQZrmkz, + VPUNPCKLDQZrr, + VPUNPCKLDQZrrk, + VPUNPCKLDQZrrkz, + VPUNPCKLDQrm, + VPUNPCKLDQrr, + VPUNPCKLQDQYrm, + VPUNPCKLQDQYrr, + VPUNPCKLQDQZ128rm, + VPUNPCKLQDQZ128rmb, + VPUNPCKLQDQZ128rmbk, + VPUNPCKLQDQZ128rmbkz, + VPUNPCKLQDQZ128rmk, + VPUNPCKLQDQZ128rmkz, + VPUNPCKLQDQZ128rr, + VPUNPCKLQDQZ128rrk, + VPUNPCKLQDQZ128rrkz, + VPUNPCKLQDQZ256rm, + VPUNPCKLQDQZ256rmb, + VPUNPCKLQDQZ256rmbk, + VPUNPCKLQDQZ256rmbkz, + VPUNPCKLQDQZ256rmk, + VPUNPCKLQDQZ256rmkz, + VPUNPCKLQDQZ256rr, + VPUNPCKLQDQZ256rrk, + VPUNPCKLQDQZ256rrkz, + VPUNPCKLQDQZrm, + VPUNPCKLQDQZrmb, + VPUNPCKLQDQZrmbk, + VPUNPCKLQDQZrmbkz, + VPUNPCKLQDQZrmk, + VPUNPCKLQDQZrmkz, + VPUNPCKLQDQZrr, + VPUNPCKLQDQZrrk, + VPUNPCKLQDQZrrkz, + VPUNPCKLQDQrm, + VPUNPCKLQDQrr, + VPUNPCKLWDYrm, + VPUNPCKLWDYrr, + VPUNPCKLWDZ128rm, + VPUNPCKLWDZ128rmk, + VPUNPCKLWDZ128rmkz, + VPUNPCKLWDZ128rr, + VPUNPCKLWDZ128rrk, + VPUNPCKLWDZ128rrkz, + VPUNPCKLWDZ256rm, + VPUNPCKLWDZ256rmk, + VPUNPCKLWDZ256rmkz, + VPUNPCKLWDZ256rr, + VPUNPCKLWDZ256rrk, + VPUNPCKLWDZ256rrkz, + VPUNPCKLWDZrm, + VPUNPCKLWDZrmk, + VPUNPCKLWDZrmkz, + VPUNPCKLWDZrr, + VPUNPCKLWDZrrk, + VPUNPCKLWDZrrkz, + VPUNPCKLWDrm, + VPUNPCKLWDrr, + VPXORDZ128rm, + VPXORDZ128rmb, + VPXORDZ128rmbk, + VPXORDZ128rmbkz, + VPXORDZ128rmk, + VPXORDZ128rmkz, + VPXORDZ128rr, + VPXORDZ128rrk, + VPXORDZ128rrkz, + VPXORDZ256rm, + VPXORDZ256rmb, + VPXORDZ256rmbk, + VPXORDZ256rmbkz, + VPXORDZ256rmk, + VPXORDZ256rmkz, + VPXORDZ256rr, + VPXORDZ256rrk, + VPXORDZ256rrkz, + VPXORDZrm, + VPXORDZrmb, + VPXORDZrmbk, + VPXORDZrmbkz, + VPXORDZrmk, + VPXORDZrmkz, + VPXORDZrr, + VPXORDZrrk, + VPXORDZrrkz, + VPXORQZ128rm, + VPXORQZ128rmb, + VPXORQZ128rmbk, + VPXORQZ128rmbkz, + VPXORQZ128rmk, + VPXORQZ128rmkz, + VPXORQZ128rr, + VPXORQZ128rrk, + VPXORQZ128rrkz, + VPXORQZ256rm, + VPXORQZ256rmb, + VPXORQZ256rmbk, + VPXORQZ256rmbkz, + VPXORQZ256rmk, + VPXORQZ256rmkz, + VPXORQZ256rr, + VPXORQZ256rrk, + VPXORQZ256rrkz, + VPXORQZrm, + VPXORQZrmb, + VPXORQZrmbk, + VPXORQZrmbkz, + VPXORQZrmk, + VPXORQZrmkz, + VPXORQZrr, + VPXORQZrrk, + VPXORQZrrkz, + VPXORYrm, + VPXORYrr, + VPXORrm, + VPXORrr, + VRANGEPDZ128rmbi, + VRANGEPDZ128rmbik, + VRANGEPDZ128rmbikz, + VRANGEPDZ128rmi, + VRANGEPDZ128rmik, + VRANGEPDZ128rmikz, + VRANGEPDZ128rri, + VRANGEPDZ128rrik, + VRANGEPDZ128rrikz, + VRANGEPDZ256rmbi, + VRANGEPDZ256rmbik, + VRANGEPDZ256rmbikz, + VRANGEPDZ256rmi, + VRANGEPDZ256rmik, + VRANGEPDZ256rmikz, + VRANGEPDZ256rri, + VRANGEPDZ256rrik, + VRANGEPDZ256rrikz, + VRANGEPDZrmbi, + VRANGEPDZrmbik, + VRANGEPDZrmbikz, + VRANGEPDZrmi, + VRANGEPDZrmik, + VRANGEPDZrmikz, + VRANGEPDZrri, + VRANGEPDZrrib, + VRANGEPDZrribk, + VRANGEPDZrribkz, + VRANGEPDZrrik, + VRANGEPDZrrikz, + VRANGEPSZ128rmbi, + VRANGEPSZ128rmbik, + VRANGEPSZ128rmbikz, + VRANGEPSZ128rmi, + VRANGEPSZ128rmik, + VRANGEPSZ128rmikz, + VRANGEPSZ128rri, + VRANGEPSZ128rrik, + VRANGEPSZ128rrikz, + VRANGEPSZ256rmbi, + VRANGEPSZ256rmbik, + VRANGEPSZ256rmbikz, + VRANGEPSZ256rmi, + VRANGEPSZ256rmik, + VRANGEPSZ256rmikz, + VRANGEPSZ256rri, + VRANGEPSZ256rrik, + VRANGEPSZ256rrikz, + VRANGEPSZrmbi, + VRANGEPSZrmbik, + VRANGEPSZrmbikz, + VRANGEPSZrmi, + VRANGEPSZrmik, + VRANGEPSZrmikz, + VRANGEPSZrri, + VRANGEPSZrrib, + VRANGEPSZrribk, + VRANGEPSZrribkz, + VRANGEPSZrrik, + VRANGEPSZrrikz, + VRANGESDZrmi, + VRANGESDZrmik, + VRANGESDZrmikz, + VRANGESDZrri, + VRANGESDZrrib, + VRANGESDZrribk, + VRANGESDZrribkz, + VRANGESDZrrik, + VRANGESDZrrikz, + VRANGESSZrmi, + VRANGESSZrmik, + VRANGESSZrmikz, + VRANGESSZrri, + VRANGESSZrrib, + VRANGESSZrribk, + VRANGESSZrribkz, + VRANGESSZrrik, + VRANGESSZrrikz, + VRCP14PDZ128m, + VRCP14PDZ128mb, + VRCP14PDZ128mbk, + VRCP14PDZ128mbkz, + VRCP14PDZ128mk, + VRCP14PDZ128mkz, + VRCP14PDZ128r, + VRCP14PDZ128rk, + VRCP14PDZ128rkz, + VRCP14PDZ256m, + VRCP14PDZ256mb, + VRCP14PDZ256mbk, + VRCP14PDZ256mbkz, + VRCP14PDZ256mk, + VRCP14PDZ256mkz, + VRCP14PDZ256r, + VRCP14PDZ256rk, + VRCP14PDZ256rkz, + VRCP14PDZm, + VRCP14PDZmb, + VRCP14PDZmbk, + VRCP14PDZmbkz, + VRCP14PDZmk, + VRCP14PDZmkz, + VRCP14PDZr, + VRCP14PDZrk, + VRCP14PDZrkz, + VRCP14PSZ128m, + VRCP14PSZ128mb, + VRCP14PSZ128mbk, + VRCP14PSZ128mbkz, + VRCP14PSZ128mk, + VRCP14PSZ128mkz, + VRCP14PSZ128r, + VRCP14PSZ128rk, + VRCP14PSZ128rkz, + VRCP14PSZ256m, + VRCP14PSZ256mb, + VRCP14PSZ256mbk, + VRCP14PSZ256mbkz, + VRCP14PSZ256mk, + VRCP14PSZ256mkz, + VRCP14PSZ256r, + VRCP14PSZ256rk, + VRCP14PSZ256rkz, + VRCP14PSZm, + VRCP14PSZmb, + VRCP14PSZmbk, + VRCP14PSZmbkz, + VRCP14PSZmk, + VRCP14PSZmkz, + VRCP14PSZr, + VRCP14PSZrk, + VRCP14PSZrkz, + VRCP14SDZrm, + VRCP14SDZrmk, + VRCP14SDZrmkz, + VRCP14SDZrr, + VRCP14SDZrrk, + VRCP14SDZrrkz, + VRCP14SSZrm, + VRCP14SSZrmk, + VRCP14SSZrmkz, + VRCP14SSZrr, + VRCP14SSZrrk, + VRCP14SSZrrkz, + VRCP28PDZm, + VRCP28PDZmb, + VRCP28PDZmbk, + VRCP28PDZmbkz, + VRCP28PDZmk, + VRCP28PDZmkz, + VRCP28PDZr, + VRCP28PDZrb, + VRCP28PDZrbk, + VRCP28PDZrbkz, + VRCP28PDZrk, + VRCP28PDZrkz, + VRCP28PSZm, + VRCP28PSZmb, + VRCP28PSZmbk, + VRCP28PSZmbkz, + VRCP28PSZmk, + VRCP28PSZmkz, + VRCP28PSZr, + VRCP28PSZrb, + VRCP28PSZrbk, + VRCP28PSZrbkz, + VRCP28PSZrk, + VRCP28PSZrkz, + VRCP28SDZm, + VRCP28SDZmk, + VRCP28SDZmkz, + VRCP28SDZr, + VRCP28SDZrb, + VRCP28SDZrbk, + VRCP28SDZrbkz, + VRCP28SDZrk, + VRCP28SDZrkz, + VRCP28SSZm, + VRCP28SSZmk, + VRCP28SSZmkz, + VRCP28SSZr, + VRCP28SSZrb, + VRCP28SSZrbk, + VRCP28SSZrbkz, + VRCP28SSZrk, + VRCP28SSZrkz, + VRCPBF16Z128m, + VRCPBF16Z128mb, + VRCPBF16Z128mbk, + VRCPBF16Z128mbkz, + VRCPBF16Z128mk, + VRCPBF16Z128mkz, + VRCPBF16Z128r, + VRCPBF16Z128rk, + VRCPBF16Z128rkz, + VRCPBF16Z256m, + VRCPBF16Z256mb, + VRCPBF16Z256mbk, + VRCPBF16Z256mbkz, + VRCPBF16Z256mk, + VRCPBF16Z256mkz, + VRCPBF16Z256r, + VRCPBF16Z256rk, + VRCPBF16Z256rkz, + VRCPBF16Zm, + VRCPBF16Zmb, + VRCPBF16Zmbk, + VRCPBF16Zmbkz, + VRCPBF16Zmk, + VRCPBF16Zmkz, + VRCPBF16Zr, + VRCPBF16Zrk, + VRCPBF16Zrkz, + VRCPPHZ128m, + VRCPPHZ128mb, + VRCPPHZ128mbk, + VRCPPHZ128mbkz, + VRCPPHZ128mk, + VRCPPHZ128mkz, + VRCPPHZ128r, + VRCPPHZ128rk, + VRCPPHZ128rkz, + VRCPPHZ256m, + VRCPPHZ256mb, + VRCPPHZ256mbk, + VRCPPHZ256mbkz, + VRCPPHZ256mk, + VRCPPHZ256mkz, + VRCPPHZ256r, + VRCPPHZ256rk, + VRCPPHZ256rkz, + VRCPPHZm, + VRCPPHZmb, + VRCPPHZmbk, + VRCPPHZmbkz, + VRCPPHZmk, + VRCPPHZmkz, + VRCPPHZr, + VRCPPHZrk, + VRCPPHZrkz, + VRCPPSYm, + VRCPPSYr, + VRCPPSm, + VRCPPSr, + VRCPSHZrm, + VRCPSHZrmk, + VRCPSHZrmkz, + VRCPSHZrr, + VRCPSHZrrk, + VRCPSHZrrkz, + VRCPSSm, + VRCPSSm_Int, + VRCPSSr, + VRCPSSr_Int, + VREDUCEBF16Z128rmbi, + VREDUCEBF16Z128rmbik, + VREDUCEBF16Z128rmbikz, + VREDUCEBF16Z128rmi, + VREDUCEBF16Z128rmik, + VREDUCEBF16Z128rmikz, + VREDUCEBF16Z128rri, + VREDUCEBF16Z128rrik, + VREDUCEBF16Z128rrikz, + VREDUCEBF16Z256rmbi, + VREDUCEBF16Z256rmbik, + VREDUCEBF16Z256rmbikz, + VREDUCEBF16Z256rmi, + VREDUCEBF16Z256rmik, + VREDUCEBF16Z256rmikz, + VREDUCEBF16Z256rri, + VREDUCEBF16Z256rrik, + VREDUCEBF16Z256rrikz, + VREDUCEBF16Zrmbi, + VREDUCEBF16Zrmbik, + VREDUCEBF16Zrmbikz, + VREDUCEBF16Zrmi, + VREDUCEBF16Zrmik, + VREDUCEBF16Zrmikz, + VREDUCEBF16Zrri, + VREDUCEBF16Zrrik, + VREDUCEBF16Zrrikz, + VREDUCEPDZ128rmbi, + VREDUCEPDZ128rmbik, + VREDUCEPDZ128rmbikz, + VREDUCEPDZ128rmi, + VREDUCEPDZ128rmik, + VREDUCEPDZ128rmikz, + VREDUCEPDZ128rri, + VREDUCEPDZ128rrik, + VREDUCEPDZ128rrikz, + VREDUCEPDZ256rmbi, + VREDUCEPDZ256rmbik, + VREDUCEPDZ256rmbikz, + VREDUCEPDZ256rmi, + VREDUCEPDZ256rmik, + VREDUCEPDZ256rmikz, + VREDUCEPDZ256rri, + VREDUCEPDZ256rrik, + VREDUCEPDZ256rrikz, + VREDUCEPDZrmbi, + VREDUCEPDZrmbik, + VREDUCEPDZrmbikz, + VREDUCEPDZrmi, + VREDUCEPDZrmik, + VREDUCEPDZrmikz, + VREDUCEPDZrri, + VREDUCEPDZrrib, + VREDUCEPDZrribk, + VREDUCEPDZrribkz, + VREDUCEPDZrrik, + VREDUCEPDZrrikz, + VREDUCEPHZ128rmbi, + VREDUCEPHZ128rmbik, + VREDUCEPHZ128rmbikz, + VREDUCEPHZ128rmi, + VREDUCEPHZ128rmik, + VREDUCEPHZ128rmikz, + VREDUCEPHZ128rri, + VREDUCEPHZ128rrik, + VREDUCEPHZ128rrikz, + VREDUCEPHZ256rmbi, + VREDUCEPHZ256rmbik, + VREDUCEPHZ256rmbikz, + VREDUCEPHZ256rmi, + VREDUCEPHZ256rmik, + VREDUCEPHZ256rmikz, + VREDUCEPHZ256rri, + VREDUCEPHZ256rrik, + VREDUCEPHZ256rrikz, + VREDUCEPHZrmbi, + VREDUCEPHZrmbik, + VREDUCEPHZrmbikz, + VREDUCEPHZrmi, + VREDUCEPHZrmik, + VREDUCEPHZrmikz, + VREDUCEPHZrri, + VREDUCEPHZrrib, + VREDUCEPHZrribk, + VREDUCEPHZrribkz, + VREDUCEPHZrrik, + VREDUCEPHZrrikz, + VREDUCEPSZ128rmbi, + VREDUCEPSZ128rmbik, + VREDUCEPSZ128rmbikz, + VREDUCEPSZ128rmi, + VREDUCEPSZ128rmik, + VREDUCEPSZ128rmikz, + VREDUCEPSZ128rri, + VREDUCEPSZ128rrik, + VREDUCEPSZ128rrikz, + VREDUCEPSZ256rmbi, + VREDUCEPSZ256rmbik, + VREDUCEPSZ256rmbikz, + VREDUCEPSZ256rmi, + VREDUCEPSZ256rmik, + VREDUCEPSZ256rmikz, + VREDUCEPSZ256rri, + VREDUCEPSZ256rrik, + VREDUCEPSZ256rrikz, + VREDUCEPSZrmbi, + VREDUCEPSZrmbik, + VREDUCEPSZrmbikz, + VREDUCEPSZrmi, + VREDUCEPSZrmik, + VREDUCEPSZrmikz, + VREDUCEPSZrri, + VREDUCEPSZrrib, + VREDUCEPSZrribk, + VREDUCEPSZrribkz, + VREDUCEPSZrrik, + VREDUCEPSZrrikz, + VREDUCESDZrmi, + VREDUCESDZrmik, + VREDUCESDZrmikz, + VREDUCESDZrri, + VREDUCESDZrrib, + VREDUCESDZrribk, + VREDUCESDZrribkz, + VREDUCESDZrrik, + VREDUCESDZrrikz, + VREDUCESHZrmi, + VREDUCESHZrmik, + VREDUCESHZrmikz, + VREDUCESHZrri, + VREDUCESHZrrib, + VREDUCESHZrribk, + VREDUCESHZrribkz, + VREDUCESHZrrik, + VREDUCESHZrrikz, + VREDUCESSZrmi, + VREDUCESSZrmik, + VREDUCESSZrmikz, + VREDUCESSZrri, + VREDUCESSZrrib, + VREDUCESSZrribk, + VREDUCESSZrribkz, + VREDUCESSZrrik, + VREDUCESSZrrikz, + VRNDSCALEBF16Z128rmbi, + VRNDSCALEBF16Z128rmbik, + VRNDSCALEBF16Z128rmbikz, + VRNDSCALEBF16Z128rmi, + VRNDSCALEBF16Z128rmik, + VRNDSCALEBF16Z128rmikz, + VRNDSCALEBF16Z128rri, + VRNDSCALEBF16Z128rrik, + VRNDSCALEBF16Z128rrikz, + VRNDSCALEBF16Z256rmbi, + VRNDSCALEBF16Z256rmbik, + VRNDSCALEBF16Z256rmbikz, + VRNDSCALEBF16Z256rmi, + VRNDSCALEBF16Z256rmik, + VRNDSCALEBF16Z256rmikz, + VRNDSCALEBF16Z256rri, + VRNDSCALEBF16Z256rrik, + VRNDSCALEBF16Z256rrikz, + VRNDSCALEBF16Zrmbi, + VRNDSCALEBF16Zrmbik, + VRNDSCALEBF16Zrmbikz, + VRNDSCALEBF16Zrmi, + VRNDSCALEBF16Zrmik, + VRNDSCALEBF16Zrmikz, + VRNDSCALEBF16Zrri, + VRNDSCALEBF16Zrrik, + VRNDSCALEBF16Zrrikz, + VRNDSCALEPDZ128rmbi, + VRNDSCALEPDZ128rmbik, + VRNDSCALEPDZ128rmbikz, + VRNDSCALEPDZ128rmi, + VRNDSCALEPDZ128rmik, + VRNDSCALEPDZ128rmikz, + VRNDSCALEPDZ128rri, + VRNDSCALEPDZ128rrik, + VRNDSCALEPDZ128rrikz, + VRNDSCALEPDZ256rmbi, + VRNDSCALEPDZ256rmbik, + VRNDSCALEPDZ256rmbikz, + VRNDSCALEPDZ256rmi, + VRNDSCALEPDZ256rmik, + VRNDSCALEPDZ256rmikz, + VRNDSCALEPDZ256rri, + VRNDSCALEPDZ256rrik, + VRNDSCALEPDZ256rrikz, + VRNDSCALEPDZrmbi, + VRNDSCALEPDZrmbik, + VRNDSCALEPDZrmbikz, + VRNDSCALEPDZrmi, + VRNDSCALEPDZrmik, + VRNDSCALEPDZrmikz, + VRNDSCALEPDZrri, + VRNDSCALEPDZrrib, + VRNDSCALEPDZrribk, + VRNDSCALEPDZrribkz, + VRNDSCALEPDZrrik, + VRNDSCALEPDZrrikz, + VRNDSCALEPHZ128rmbi, + VRNDSCALEPHZ128rmbik, + VRNDSCALEPHZ128rmbikz, + VRNDSCALEPHZ128rmi, + VRNDSCALEPHZ128rmik, + VRNDSCALEPHZ128rmikz, + VRNDSCALEPHZ128rri, + VRNDSCALEPHZ128rrik, + VRNDSCALEPHZ128rrikz, + VRNDSCALEPHZ256rmbi, + VRNDSCALEPHZ256rmbik, + VRNDSCALEPHZ256rmbikz, + VRNDSCALEPHZ256rmi, + VRNDSCALEPHZ256rmik, + VRNDSCALEPHZ256rmikz, + VRNDSCALEPHZ256rri, + VRNDSCALEPHZ256rrik, + VRNDSCALEPHZ256rrikz, + VRNDSCALEPHZrmbi, + VRNDSCALEPHZrmbik, + VRNDSCALEPHZrmbikz, + VRNDSCALEPHZrmi, + VRNDSCALEPHZrmik, + VRNDSCALEPHZrmikz, + VRNDSCALEPHZrri, + VRNDSCALEPHZrrib, + VRNDSCALEPHZrribk, + VRNDSCALEPHZrribkz, + VRNDSCALEPHZrrik, + VRNDSCALEPHZrrikz, + VRNDSCALEPSZ128rmbi, + VRNDSCALEPSZ128rmbik, + VRNDSCALEPSZ128rmbikz, + VRNDSCALEPSZ128rmi, + VRNDSCALEPSZ128rmik, + VRNDSCALEPSZ128rmikz, + VRNDSCALEPSZ128rri, + VRNDSCALEPSZ128rrik, + VRNDSCALEPSZ128rrikz, + VRNDSCALEPSZ256rmbi, + VRNDSCALEPSZ256rmbik, + VRNDSCALEPSZ256rmbikz, + VRNDSCALEPSZ256rmi, + VRNDSCALEPSZ256rmik, + VRNDSCALEPSZ256rmikz, + VRNDSCALEPSZ256rri, + VRNDSCALEPSZ256rrik, + VRNDSCALEPSZ256rrikz, + VRNDSCALEPSZrmbi, + VRNDSCALEPSZrmbik, + VRNDSCALEPSZrmbikz, + VRNDSCALEPSZrmi, + VRNDSCALEPSZrmik, + VRNDSCALEPSZrmikz, + VRNDSCALEPSZrri, + VRNDSCALEPSZrrib, + VRNDSCALEPSZrribk, + VRNDSCALEPSZrribkz, + VRNDSCALEPSZrrik, + VRNDSCALEPSZrrikz, + VRNDSCALESDZrmi, + VRNDSCALESDZrmi_Int, + VRNDSCALESDZrmik_Int, + VRNDSCALESDZrmikz_Int, + VRNDSCALESDZrri, + VRNDSCALESDZrri_Int, + VRNDSCALESDZrrib_Int, + VRNDSCALESDZrribk_Int, + VRNDSCALESDZrribkz_Int, + VRNDSCALESDZrrik_Int, + VRNDSCALESDZrrikz_Int, + VRNDSCALESHZrmi, + VRNDSCALESHZrmi_Int, + VRNDSCALESHZrmik_Int, + VRNDSCALESHZrmikz_Int, + VRNDSCALESHZrri, + VRNDSCALESHZrri_Int, + VRNDSCALESHZrrib_Int, + VRNDSCALESHZrribk_Int, + VRNDSCALESHZrribkz_Int, + VRNDSCALESHZrrik_Int, + VRNDSCALESHZrrikz_Int, + VRNDSCALESSZrmi, + VRNDSCALESSZrmi_Int, + VRNDSCALESSZrmik_Int, + VRNDSCALESSZrmikz_Int, + VRNDSCALESSZrri, + VRNDSCALESSZrri_Int, + VRNDSCALESSZrrib_Int, + VRNDSCALESSZrribk_Int, + VRNDSCALESSZrribkz_Int, + VRNDSCALESSZrrik_Int, + VRNDSCALESSZrrikz_Int, + VROUNDPDYmi, + VROUNDPDYri, + VROUNDPDmi, + VROUNDPDri, + VROUNDPSYmi, + VROUNDPSYri, + VROUNDPSmi, + VROUNDPSri, + VROUNDSDmi, + VROUNDSDmi_Int, + VROUNDSDri, + VROUNDSDri_Int, + VROUNDSSmi, + VROUNDSSmi_Int, + VROUNDSSri, + VROUNDSSri_Int, + VRSQRT14PDZ128m, + VRSQRT14PDZ128mb, + VRSQRT14PDZ128mbk, + VRSQRT14PDZ128mbkz, + VRSQRT14PDZ128mk, + VRSQRT14PDZ128mkz, + VRSQRT14PDZ128r, + VRSQRT14PDZ128rk, + VRSQRT14PDZ128rkz, + VRSQRT14PDZ256m, + VRSQRT14PDZ256mb, + VRSQRT14PDZ256mbk, + VRSQRT14PDZ256mbkz, + VRSQRT14PDZ256mk, + VRSQRT14PDZ256mkz, + VRSQRT14PDZ256r, + VRSQRT14PDZ256rk, + VRSQRT14PDZ256rkz, + VRSQRT14PDZm, + VRSQRT14PDZmb, + VRSQRT14PDZmbk, + VRSQRT14PDZmbkz, + VRSQRT14PDZmk, + VRSQRT14PDZmkz, + VRSQRT14PDZr, + VRSQRT14PDZrk, + VRSQRT14PDZrkz, + VRSQRT14PSZ128m, + VRSQRT14PSZ128mb, + VRSQRT14PSZ128mbk, + VRSQRT14PSZ128mbkz, + VRSQRT14PSZ128mk, + VRSQRT14PSZ128mkz, + VRSQRT14PSZ128r, + VRSQRT14PSZ128rk, + VRSQRT14PSZ128rkz, + VRSQRT14PSZ256m, + VRSQRT14PSZ256mb, + VRSQRT14PSZ256mbk, + VRSQRT14PSZ256mbkz, + VRSQRT14PSZ256mk, + VRSQRT14PSZ256mkz, + VRSQRT14PSZ256r, + VRSQRT14PSZ256rk, + VRSQRT14PSZ256rkz, + VRSQRT14PSZm, + VRSQRT14PSZmb, + VRSQRT14PSZmbk, + VRSQRT14PSZmbkz, + VRSQRT14PSZmk, + VRSQRT14PSZmkz, + VRSQRT14PSZr, + VRSQRT14PSZrk, + VRSQRT14PSZrkz, + VRSQRT14SDZrm, + VRSQRT14SDZrmk, + VRSQRT14SDZrmkz, + VRSQRT14SDZrr, + VRSQRT14SDZrrk, + VRSQRT14SDZrrkz, + VRSQRT14SSZrm, + VRSQRT14SSZrmk, + VRSQRT14SSZrmkz, + VRSQRT14SSZrr, + VRSQRT14SSZrrk, + VRSQRT14SSZrrkz, + VRSQRT28PDZm, + VRSQRT28PDZmb, + VRSQRT28PDZmbk, + VRSQRT28PDZmbkz, + VRSQRT28PDZmk, + VRSQRT28PDZmkz, + VRSQRT28PDZr, + VRSQRT28PDZrb, + VRSQRT28PDZrbk, + VRSQRT28PDZrbkz, + VRSQRT28PDZrk, + VRSQRT28PDZrkz, + VRSQRT28PSZm, + VRSQRT28PSZmb, + VRSQRT28PSZmbk, + VRSQRT28PSZmbkz, + VRSQRT28PSZmk, + VRSQRT28PSZmkz, + VRSQRT28PSZr, + VRSQRT28PSZrb, + VRSQRT28PSZrbk, + VRSQRT28PSZrbkz, + VRSQRT28PSZrk, + VRSQRT28PSZrkz, + VRSQRT28SDZm, + VRSQRT28SDZmk, + VRSQRT28SDZmkz, + VRSQRT28SDZr, + VRSQRT28SDZrb, + VRSQRT28SDZrbk, + VRSQRT28SDZrbkz, + VRSQRT28SDZrk, + VRSQRT28SDZrkz, + VRSQRT28SSZm, + VRSQRT28SSZmk, + VRSQRT28SSZmkz, + VRSQRT28SSZr, + VRSQRT28SSZrb, + VRSQRT28SSZrbk, + VRSQRT28SSZrbkz, + VRSQRT28SSZrk, + VRSQRT28SSZrkz, + VRSQRTBF16Z128m, + VRSQRTBF16Z128mb, + VRSQRTBF16Z128mbk, + VRSQRTBF16Z128mbkz, + VRSQRTBF16Z128mk, + VRSQRTBF16Z128mkz, + VRSQRTBF16Z128r, + VRSQRTBF16Z128rk, + VRSQRTBF16Z128rkz, + VRSQRTBF16Z256m, + VRSQRTBF16Z256mb, + VRSQRTBF16Z256mbk, + VRSQRTBF16Z256mbkz, + VRSQRTBF16Z256mk, + VRSQRTBF16Z256mkz, + VRSQRTBF16Z256r, + VRSQRTBF16Z256rk, + VRSQRTBF16Z256rkz, + VRSQRTBF16Zm, + VRSQRTBF16Zmb, + VRSQRTBF16Zmbk, + VRSQRTBF16Zmbkz, + VRSQRTBF16Zmk, + VRSQRTBF16Zmkz, + VRSQRTBF16Zr, + VRSQRTBF16Zrk, + VRSQRTBF16Zrkz, + VRSQRTPHZ128m, + VRSQRTPHZ128mb, + VRSQRTPHZ128mbk, + VRSQRTPHZ128mbkz, + VRSQRTPHZ128mk, + VRSQRTPHZ128mkz, + VRSQRTPHZ128r, + VRSQRTPHZ128rk, + VRSQRTPHZ128rkz, + VRSQRTPHZ256m, + VRSQRTPHZ256mb, + VRSQRTPHZ256mbk, + VRSQRTPHZ256mbkz, + VRSQRTPHZ256mk, + VRSQRTPHZ256mkz, + VRSQRTPHZ256r, + VRSQRTPHZ256rk, + VRSQRTPHZ256rkz, + VRSQRTPHZm, + VRSQRTPHZmb, + VRSQRTPHZmbk, + VRSQRTPHZmbkz, + VRSQRTPHZmk, + VRSQRTPHZmkz, + VRSQRTPHZr, + VRSQRTPHZrk, + VRSQRTPHZrkz, + VRSQRTPSYm, + VRSQRTPSYr, + VRSQRTPSm, + VRSQRTPSr, + VRSQRTSHZrm, + VRSQRTSHZrmk, + VRSQRTSHZrmkz, + VRSQRTSHZrr, + VRSQRTSHZrrk, + VRSQRTSHZrrkz, + VRSQRTSSm, + VRSQRTSSm_Int, + VRSQRTSSr, + VRSQRTSSr_Int, + VSCALEFBF16Z128rm, + VSCALEFBF16Z128rmb, + VSCALEFBF16Z128rmbk, + VSCALEFBF16Z128rmbkz, + VSCALEFBF16Z128rmk, + VSCALEFBF16Z128rmkz, + VSCALEFBF16Z128rr, + VSCALEFBF16Z128rrk, + VSCALEFBF16Z128rrkz, + VSCALEFBF16Z256rm, + VSCALEFBF16Z256rmb, + VSCALEFBF16Z256rmbk, + VSCALEFBF16Z256rmbkz, + VSCALEFBF16Z256rmk, + VSCALEFBF16Z256rmkz, + VSCALEFBF16Z256rr, + VSCALEFBF16Z256rrk, + VSCALEFBF16Z256rrkz, + VSCALEFBF16Zrm, + VSCALEFBF16Zrmb, + VSCALEFBF16Zrmbk, + VSCALEFBF16Zrmbkz, + VSCALEFBF16Zrmk, + VSCALEFBF16Zrmkz, + VSCALEFBF16Zrr, + VSCALEFBF16Zrrk, + VSCALEFBF16Zrrkz, + VSCALEFPDZ128rm, + VSCALEFPDZ128rmb, + VSCALEFPDZ128rmbk, + VSCALEFPDZ128rmbkz, + VSCALEFPDZ128rmk, + VSCALEFPDZ128rmkz, + VSCALEFPDZ128rr, + VSCALEFPDZ128rrk, + VSCALEFPDZ128rrkz, + VSCALEFPDZ256rm, + VSCALEFPDZ256rmb, + VSCALEFPDZ256rmbk, + VSCALEFPDZ256rmbkz, + VSCALEFPDZ256rmk, + VSCALEFPDZ256rmkz, + VSCALEFPDZ256rr, + VSCALEFPDZ256rrk, + VSCALEFPDZ256rrkz, + VSCALEFPDZrm, + VSCALEFPDZrmb, + VSCALEFPDZrmbk, + VSCALEFPDZrmbkz, + VSCALEFPDZrmk, + VSCALEFPDZrmkz, + VSCALEFPDZrr, + VSCALEFPDZrrb, + VSCALEFPDZrrbk, + VSCALEFPDZrrbkz, + VSCALEFPDZrrk, + VSCALEFPDZrrkz, + VSCALEFPHZ128rm, + VSCALEFPHZ128rmb, + VSCALEFPHZ128rmbk, + VSCALEFPHZ128rmbkz, + VSCALEFPHZ128rmk, + VSCALEFPHZ128rmkz, + VSCALEFPHZ128rr, + VSCALEFPHZ128rrk, + VSCALEFPHZ128rrkz, + VSCALEFPHZ256rm, + VSCALEFPHZ256rmb, + VSCALEFPHZ256rmbk, + VSCALEFPHZ256rmbkz, + VSCALEFPHZ256rmk, + VSCALEFPHZ256rmkz, + VSCALEFPHZ256rr, + VSCALEFPHZ256rrk, + VSCALEFPHZ256rrkz, + VSCALEFPHZrm, + VSCALEFPHZrmb, + VSCALEFPHZrmbk, + VSCALEFPHZrmbkz, + VSCALEFPHZrmk, + VSCALEFPHZrmkz, + VSCALEFPHZrr, + VSCALEFPHZrrb, + VSCALEFPHZrrbk, + VSCALEFPHZrrbkz, + VSCALEFPHZrrk, + VSCALEFPHZrrkz, + VSCALEFPSZ128rm, + VSCALEFPSZ128rmb, + VSCALEFPSZ128rmbk, + VSCALEFPSZ128rmbkz, + VSCALEFPSZ128rmk, + VSCALEFPSZ128rmkz, + VSCALEFPSZ128rr, + VSCALEFPSZ128rrk, + VSCALEFPSZ128rrkz, + VSCALEFPSZ256rm, + VSCALEFPSZ256rmb, + VSCALEFPSZ256rmbk, + VSCALEFPSZ256rmbkz, + VSCALEFPSZ256rmk, + VSCALEFPSZ256rmkz, + VSCALEFPSZ256rr, + VSCALEFPSZ256rrk, + VSCALEFPSZ256rrkz, + VSCALEFPSZrm, + VSCALEFPSZrmb, + VSCALEFPSZrmbk, + VSCALEFPSZrmbkz, + VSCALEFPSZrmk, + VSCALEFPSZrmkz, + VSCALEFPSZrr, + VSCALEFPSZrrb, + VSCALEFPSZrrbk, + VSCALEFPSZrrbkz, + VSCALEFPSZrrk, + VSCALEFPSZrrkz, + VSCALEFSDZrm, + VSCALEFSDZrmk, + VSCALEFSDZrmkz, + VSCALEFSDZrr, + VSCALEFSDZrrb_Int, + VSCALEFSDZrrbk_Int, + VSCALEFSDZrrbkz_Int, + VSCALEFSDZrrk, + VSCALEFSDZrrkz, + VSCALEFSHZrm, + VSCALEFSHZrmk, + VSCALEFSHZrmkz, + VSCALEFSHZrr, + VSCALEFSHZrrb_Int, + VSCALEFSHZrrbk_Int, + VSCALEFSHZrrbkz_Int, + VSCALEFSHZrrk, + VSCALEFSHZrrkz, + VSCALEFSSZrm, + VSCALEFSSZrmk, + VSCALEFSSZrmkz, + VSCALEFSSZrr, + VSCALEFSSZrrb_Int, + VSCALEFSSZrrbk_Int, + VSCALEFSSZrrbkz_Int, + VSCALEFSSZrrk, + VSCALEFSSZrrkz, + VSCATTERDPDZ128mr, + VSCATTERDPDZ256mr, + VSCATTERDPDZmr, + VSCATTERDPSZ128mr, + VSCATTERDPSZ256mr, + VSCATTERDPSZmr, + VSCATTERPF0DPDm, + VSCATTERPF0DPSm, + VSCATTERPF0QPDm, + VSCATTERPF0QPSm, + VSCATTERPF1DPDm, + VSCATTERPF1DPSm, + VSCATTERPF1QPDm, + VSCATTERPF1QPSm, + VSCATTERQPDZ128mr, + VSCATTERQPDZ256mr, + VSCATTERQPDZmr, + VSCATTERQPSZ128mr, + VSCATTERQPSZ256mr, + VSCATTERQPSZmr, + VSHA512MSG1rr, + VSHA512MSG2rr, + VSHA512RNDS2rr, + VSHUFF32X4Z256rmbi, + VSHUFF32X4Z256rmbik, + VSHUFF32X4Z256rmbikz, + VSHUFF32X4Z256rmi, + VSHUFF32X4Z256rmik, + VSHUFF32X4Z256rmikz, + VSHUFF32X4Z256rri, + VSHUFF32X4Z256rrik, + VSHUFF32X4Z256rrikz, + VSHUFF32X4Zrmbi, + VSHUFF32X4Zrmbik, + VSHUFF32X4Zrmbikz, + VSHUFF32X4Zrmi, + VSHUFF32X4Zrmik, + VSHUFF32X4Zrmikz, + VSHUFF32X4Zrri, + VSHUFF32X4Zrrik, + VSHUFF32X4Zrrikz, + VSHUFF64X2Z256rmbi, + VSHUFF64X2Z256rmbik, + VSHUFF64X2Z256rmbikz, + VSHUFF64X2Z256rmi, + VSHUFF64X2Z256rmik, + VSHUFF64X2Z256rmikz, + VSHUFF64X2Z256rri, + VSHUFF64X2Z256rrik, + VSHUFF64X2Z256rrikz, + VSHUFF64X2Zrmbi, + VSHUFF64X2Zrmbik, + VSHUFF64X2Zrmbikz, + VSHUFF64X2Zrmi, + VSHUFF64X2Zrmik, + VSHUFF64X2Zrmikz, + VSHUFF64X2Zrri, + VSHUFF64X2Zrrik, + VSHUFF64X2Zrrikz, + VSHUFI32X4Z256rmbi, + VSHUFI32X4Z256rmbik, + VSHUFI32X4Z256rmbikz, + VSHUFI32X4Z256rmi, + VSHUFI32X4Z256rmik, + VSHUFI32X4Z256rmikz, + VSHUFI32X4Z256rri, + VSHUFI32X4Z256rrik, + VSHUFI32X4Z256rrikz, + VSHUFI32X4Zrmbi, + VSHUFI32X4Zrmbik, + VSHUFI32X4Zrmbikz, + VSHUFI32X4Zrmi, + VSHUFI32X4Zrmik, + VSHUFI32X4Zrmikz, + VSHUFI32X4Zrri, + VSHUFI32X4Zrrik, + VSHUFI32X4Zrrikz, + VSHUFI64X2Z256rmbi, + VSHUFI64X2Z256rmbik, + VSHUFI64X2Z256rmbikz, + VSHUFI64X2Z256rmi, + VSHUFI64X2Z256rmik, + VSHUFI64X2Z256rmikz, + VSHUFI64X2Z256rri, + VSHUFI64X2Z256rrik, + VSHUFI64X2Z256rrikz, + VSHUFI64X2Zrmbi, + VSHUFI64X2Zrmbik, + VSHUFI64X2Zrmbikz, + VSHUFI64X2Zrmi, + VSHUFI64X2Zrmik, + VSHUFI64X2Zrmikz, + VSHUFI64X2Zrri, + VSHUFI64X2Zrrik, + VSHUFI64X2Zrrikz, + VSHUFPDYrmi, + VSHUFPDYrri, + VSHUFPDZ128rmbi, + VSHUFPDZ128rmbik, + VSHUFPDZ128rmbikz, + VSHUFPDZ128rmi, + VSHUFPDZ128rmik, + VSHUFPDZ128rmikz, + VSHUFPDZ128rri, + VSHUFPDZ128rrik, + VSHUFPDZ128rrikz, + VSHUFPDZ256rmbi, + VSHUFPDZ256rmbik, + VSHUFPDZ256rmbikz, + VSHUFPDZ256rmi, + VSHUFPDZ256rmik, + VSHUFPDZ256rmikz, + VSHUFPDZ256rri, + VSHUFPDZ256rrik, + VSHUFPDZ256rrikz, + VSHUFPDZrmbi, + VSHUFPDZrmbik, + VSHUFPDZrmbikz, + VSHUFPDZrmi, + VSHUFPDZrmik, + VSHUFPDZrmikz, + VSHUFPDZrri, + VSHUFPDZrrik, + VSHUFPDZrrikz, + VSHUFPDrmi, + VSHUFPDrri, + VSHUFPSYrmi, + VSHUFPSYrri, + VSHUFPSZ128rmbi, + VSHUFPSZ128rmbik, + VSHUFPSZ128rmbikz, + VSHUFPSZ128rmi, + VSHUFPSZ128rmik, + VSHUFPSZ128rmikz, + VSHUFPSZ128rri, + VSHUFPSZ128rrik, + VSHUFPSZ128rrikz, + VSHUFPSZ256rmbi, + VSHUFPSZ256rmbik, + VSHUFPSZ256rmbikz, + VSHUFPSZ256rmi, + VSHUFPSZ256rmik, + VSHUFPSZ256rmikz, + VSHUFPSZ256rri, + VSHUFPSZ256rrik, + VSHUFPSZ256rrikz, + VSHUFPSZrmbi, + VSHUFPSZrmbik, + VSHUFPSZrmbikz, + VSHUFPSZrmi, + VSHUFPSZrmik, + VSHUFPSZrmikz, + VSHUFPSZrri, + VSHUFPSZrrik, + VSHUFPSZrrikz, + VSHUFPSrmi, + VSHUFPSrri, + VSM3MSG1rm, + VSM3MSG1rr, + VSM3MSG2rm, + VSM3MSG2rr, + VSM3RNDS2rmi, + VSM3RNDS2rri, + VSM4KEY4Yrm, + VSM4KEY4Yrr, + VSM4KEY4Z128rm, + VSM4KEY4Z128rr, + VSM4KEY4Z256rm, + VSM4KEY4Z256rr, + VSM4KEY4Zrm, + VSM4KEY4Zrr, + VSM4KEY4rm, + VSM4KEY4rr, + VSM4RNDS4Yrm, + VSM4RNDS4Yrr, + VSM4RNDS4Z128rm, + VSM4RNDS4Z128rr, + VSM4RNDS4Z256rm, + VSM4RNDS4Z256rr, + VSM4RNDS4Zrm, + VSM4RNDS4Zrr, + VSM4RNDS4rm, + VSM4RNDS4rr, + VSQRTBF16Z128m, + VSQRTBF16Z128mb, + VSQRTBF16Z128mbk, + VSQRTBF16Z128mbkz, + VSQRTBF16Z128mk, + VSQRTBF16Z128mkz, + VSQRTBF16Z128r, + VSQRTBF16Z128rk, + VSQRTBF16Z128rkz, + VSQRTBF16Z256m, + VSQRTBF16Z256mb, + VSQRTBF16Z256mbk, + VSQRTBF16Z256mbkz, + VSQRTBF16Z256mk, + VSQRTBF16Z256mkz, + VSQRTBF16Z256r, + VSQRTBF16Z256rk, + VSQRTBF16Z256rkz, + VSQRTBF16Zm, + VSQRTBF16Zmb, + VSQRTBF16Zmbk, + VSQRTBF16Zmbkz, + VSQRTBF16Zmk, + VSQRTBF16Zmkz, + VSQRTBF16Zr, + VSQRTBF16Zrk, + VSQRTBF16Zrkz, + VSQRTPDYm, + VSQRTPDYr, + VSQRTPDZ128m, + VSQRTPDZ128mb, + VSQRTPDZ128mbk, + VSQRTPDZ128mbkz, + VSQRTPDZ128mk, + VSQRTPDZ128mkz, + VSQRTPDZ128r, + VSQRTPDZ128rk, + VSQRTPDZ128rkz, + VSQRTPDZ256m, + VSQRTPDZ256mb, + VSQRTPDZ256mbk, + VSQRTPDZ256mbkz, + VSQRTPDZ256mk, + VSQRTPDZ256mkz, + VSQRTPDZ256r, + VSQRTPDZ256rk, + VSQRTPDZ256rkz, + VSQRTPDZm, + VSQRTPDZmb, + VSQRTPDZmbk, + VSQRTPDZmbkz, + VSQRTPDZmk, + VSQRTPDZmkz, + VSQRTPDZr, + VSQRTPDZrb, + VSQRTPDZrbk, + VSQRTPDZrbkz, + VSQRTPDZrk, + VSQRTPDZrkz, + VSQRTPDm, + VSQRTPDr, + VSQRTPHZ128m, + VSQRTPHZ128mb, + VSQRTPHZ128mbk, + VSQRTPHZ128mbkz, + VSQRTPHZ128mk, + VSQRTPHZ128mkz, + VSQRTPHZ128r, + VSQRTPHZ128rk, + VSQRTPHZ128rkz, + VSQRTPHZ256m, + VSQRTPHZ256mb, + VSQRTPHZ256mbk, + VSQRTPHZ256mbkz, + VSQRTPHZ256mk, + VSQRTPHZ256mkz, + VSQRTPHZ256r, + VSQRTPHZ256rk, + VSQRTPHZ256rkz, + VSQRTPHZm, + VSQRTPHZmb, + VSQRTPHZmbk, + VSQRTPHZmbkz, + VSQRTPHZmk, + VSQRTPHZmkz, + VSQRTPHZr, + VSQRTPHZrb, + VSQRTPHZrbk, + VSQRTPHZrbkz, + VSQRTPHZrk, + VSQRTPHZrkz, + VSQRTPSYm, + VSQRTPSYr, + VSQRTPSZ128m, + VSQRTPSZ128mb, + VSQRTPSZ128mbk, + VSQRTPSZ128mbkz, + VSQRTPSZ128mk, + VSQRTPSZ128mkz, + VSQRTPSZ128r, + VSQRTPSZ128rk, + VSQRTPSZ128rkz, + VSQRTPSZ256m, + VSQRTPSZ256mb, + VSQRTPSZ256mbk, + VSQRTPSZ256mbkz, + VSQRTPSZ256mk, + VSQRTPSZ256mkz, + VSQRTPSZ256r, + VSQRTPSZ256rk, + VSQRTPSZ256rkz, + VSQRTPSZm, + VSQRTPSZmb, + VSQRTPSZmbk, + VSQRTPSZmbkz, + VSQRTPSZmk, + VSQRTPSZmkz, + VSQRTPSZr, + VSQRTPSZrb, + VSQRTPSZrbk, + VSQRTPSZrbkz, + VSQRTPSZrk, + VSQRTPSZrkz, + VSQRTPSm, + VSQRTPSr, + VSQRTSDZm, + VSQRTSDZm_Int, + VSQRTSDZmk_Int, + VSQRTSDZmkz_Int, + VSQRTSDZr, + VSQRTSDZr_Int, + VSQRTSDZrb_Int, + VSQRTSDZrbk_Int, + VSQRTSDZrbkz_Int, + VSQRTSDZrk_Int, + VSQRTSDZrkz_Int, + VSQRTSDm, + VSQRTSDm_Int, + VSQRTSDr, + VSQRTSDr_Int, + VSQRTSHZm, + VSQRTSHZm_Int, + VSQRTSHZmk_Int, + VSQRTSHZmkz_Int, + VSQRTSHZr, + VSQRTSHZr_Int, + VSQRTSHZrb_Int, + VSQRTSHZrbk_Int, + VSQRTSHZrbkz_Int, + VSQRTSHZrk_Int, + VSQRTSHZrkz_Int, + VSQRTSSZm, + VSQRTSSZm_Int, + VSQRTSSZmk_Int, + VSQRTSSZmkz_Int, + VSQRTSSZr, + VSQRTSSZr_Int, + VSQRTSSZrb_Int, + VSQRTSSZrbk_Int, + VSQRTSSZrbkz_Int, + VSQRTSSZrk_Int, + VSQRTSSZrkz_Int, + VSQRTSSm, + VSQRTSSm_Int, + VSQRTSSr, + VSQRTSSr_Int, + VSTMXCSR, + VSUBBF16Z128rm, + VSUBBF16Z128rmb, + VSUBBF16Z128rmbk, + VSUBBF16Z128rmbkz, + VSUBBF16Z128rmk, + VSUBBF16Z128rmkz, + VSUBBF16Z128rr, + VSUBBF16Z128rrk, + VSUBBF16Z128rrkz, + VSUBBF16Z256rm, + VSUBBF16Z256rmb, + VSUBBF16Z256rmbk, + VSUBBF16Z256rmbkz, + VSUBBF16Z256rmk, + VSUBBF16Z256rmkz, + VSUBBF16Z256rr, + VSUBBF16Z256rrk, + VSUBBF16Z256rrkz, + VSUBBF16Zrm, + VSUBBF16Zrmb, + VSUBBF16Zrmbk, + VSUBBF16Zrmbkz, + VSUBBF16Zrmk, + VSUBBF16Zrmkz, + VSUBBF16Zrr, + VSUBBF16Zrrk, + VSUBBF16Zrrkz, + VSUBPDYrm, + VSUBPDYrr, + VSUBPDZ128rm, + VSUBPDZ128rmb, + VSUBPDZ128rmbk, + VSUBPDZ128rmbkz, + VSUBPDZ128rmk, + VSUBPDZ128rmkz, + VSUBPDZ128rr, + VSUBPDZ128rrk, + VSUBPDZ128rrkz, + VSUBPDZ256rm, + VSUBPDZ256rmb, + VSUBPDZ256rmbk, + VSUBPDZ256rmbkz, + VSUBPDZ256rmk, + VSUBPDZ256rmkz, + VSUBPDZ256rr, + VSUBPDZ256rrk, + VSUBPDZ256rrkz, + VSUBPDZrm, + VSUBPDZrmb, + VSUBPDZrmbk, + VSUBPDZrmbkz, + VSUBPDZrmk, + VSUBPDZrmkz, + VSUBPDZrr, + VSUBPDZrrb, + VSUBPDZrrbk, + VSUBPDZrrbkz, + VSUBPDZrrk, + VSUBPDZrrkz, + VSUBPDrm, + VSUBPDrr, + VSUBPHZ128rm, + VSUBPHZ128rmb, + VSUBPHZ128rmbk, + VSUBPHZ128rmbkz, + VSUBPHZ128rmk, + VSUBPHZ128rmkz, + VSUBPHZ128rr, + VSUBPHZ128rrk, + VSUBPHZ128rrkz, + VSUBPHZ256rm, + VSUBPHZ256rmb, + VSUBPHZ256rmbk, + VSUBPHZ256rmbkz, + VSUBPHZ256rmk, + VSUBPHZ256rmkz, + VSUBPHZ256rr, + VSUBPHZ256rrk, + VSUBPHZ256rrkz, + VSUBPHZrm, + VSUBPHZrmb, + VSUBPHZrmbk, + VSUBPHZrmbkz, + VSUBPHZrmk, + VSUBPHZrmkz, + VSUBPHZrr, + VSUBPHZrrb, + VSUBPHZrrbk, + VSUBPHZrrbkz, + VSUBPHZrrk, + VSUBPHZrrkz, + VSUBPSYrm, + VSUBPSYrr, + VSUBPSZ128rm, + VSUBPSZ128rmb, + VSUBPSZ128rmbk, + VSUBPSZ128rmbkz, + VSUBPSZ128rmk, + VSUBPSZ128rmkz, + VSUBPSZ128rr, + VSUBPSZ128rrk, + VSUBPSZ128rrkz, + VSUBPSZ256rm, + VSUBPSZ256rmb, + VSUBPSZ256rmbk, + VSUBPSZ256rmbkz, + VSUBPSZ256rmk, + VSUBPSZ256rmkz, + VSUBPSZ256rr, + VSUBPSZ256rrk, + VSUBPSZ256rrkz, + VSUBPSZrm, + VSUBPSZrmb, + VSUBPSZrmbk, + VSUBPSZrmbkz, + VSUBPSZrmk, + VSUBPSZrmkz, + VSUBPSZrr, + VSUBPSZrrb, + VSUBPSZrrbk, + VSUBPSZrrbkz, + VSUBPSZrrk, + VSUBPSZrrkz, + VSUBPSrm, + VSUBPSrr, + VSUBSDZrm, + VSUBSDZrm_Int, + VSUBSDZrmk_Int, + VSUBSDZrmkz_Int, + VSUBSDZrr, + VSUBSDZrr_Int, + VSUBSDZrrb_Int, + VSUBSDZrrbk_Int, + VSUBSDZrrbkz_Int, + VSUBSDZrrk_Int, + VSUBSDZrrkz_Int, + VSUBSDrm, + VSUBSDrm_Int, + VSUBSDrr, + VSUBSDrr_Int, + VSUBSHZrm, + VSUBSHZrm_Int, + VSUBSHZrmk_Int, + VSUBSHZrmkz_Int, + VSUBSHZrr, + VSUBSHZrr_Int, + VSUBSHZrrb_Int, + VSUBSHZrrbk_Int, + VSUBSHZrrbkz_Int, + VSUBSHZrrk_Int, + VSUBSHZrrkz_Int, + VSUBSSZrm, + VSUBSSZrm_Int, + VSUBSSZrmk_Int, + VSUBSSZrmkz_Int, + VSUBSSZrr, + VSUBSSZrr_Int, + VSUBSSZrrb_Int, + VSUBSSZrrbk_Int, + VSUBSSZrrbkz_Int, + VSUBSSZrrk_Int, + VSUBSSZrrkz_Int, + VSUBSSrm, + VSUBSSrm_Int, + VSUBSSrr, + VSUBSSrr_Int, + VTESTPDYrm, + VTESTPDYrr, + VTESTPDrm, + VTESTPDrr, + VTESTPSYrm, + VTESTPSYrr, + VTESTPSrm, + VTESTPSrr, + VUCOMISDZrm, + VUCOMISDZrm_Int, + VUCOMISDZrr, + VUCOMISDZrr_Int, + VUCOMISDZrrb, + VUCOMISDrm, + VUCOMISDrm_Int, + VUCOMISDrr, + VUCOMISDrr_Int, + VUCOMISHZrm, + VUCOMISHZrm_Int, + VUCOMISHZrr, + VUCOMISHZrr_Int, + VUCOMISHZrrb, + VUCOMISSZrm, + VUCOMISSZrm_Int, + VUCOMISSZrr, + VUCOMISSZrr_Int, + VUCOMISSZrrb, + VUCOMISSrm, + VUCOMISSrm_Int, + VUCOMISSrr, + VUCOMISSrr_Int, + VUCOMXSDZrm, + VUCOMXSDZrm_Int, + VUCOMXSDZrr, + VUCOMXSDZrr_Int, + VUCOMXSDZrrb_Int, + VUCOMXSHZrm, + VUCOMXSHZrm_Int, + VUCOMXSHZrr, + VUCOMXSHZrr_Int, + VUCOMXSHZrrb_Int, + VUCOMXSSZrm, + VUCOMXSSZrm_Int, + VUCOMXSSZrr, + VUCOMXSSZrr_Int, + VUCOMXSSZrrb_Int, + VUNPCKHPDYrm, + VUNPCKHPDYrr, + VUNPCKHPDZ128rm, + VUNPCKHPDZ128rmb, + VUNPCKHPDZ128rmbk, + VUNPCKHPDZ128rmbkz, + VUNPCKHPDZ128rmk, + VUNPCKHPDZ128rmkz, + VUNPCKHPDZ128rr, + VUNPCKHPDZ128rrk, + VUNPCKHPDZ128rrkz, + VUNPCKHPDZ256rm, + VUNPCKHPDZ256rmb, + VUNPCKHPDZ256rmbk, + VUNPCKHPDZ256rmbkz, + VUNPCKHPDZ256rmk, + VUNPCKHPDZ256rmkz, + VUNPCKHPDZ256rr, + VUNPCKHPDZ256rrk, + VUNPCKHPDZ256rrkz, + VUNPCKHPDZrm, + VUNPCKHPDZrmb, + VUNPCKHPDZrmbk, + VUNPCKHPDZrmbkz, + VUNPCKHPDZrmk, + VUNPCKHPDZrmkz, + VUNPCKHPDZrr, + VUNPCKHPDZrrk, + VUNPCKHPDZrrkz, + VUNPCKHPDrm, + VUNPCKHPDrr, + VUNPCKHPSYrm, + VUNPCKHPSYrr, + VUNPCKHPSZ128rm, + VUNPCKHPSZ128rmb, + VUNPCKHPSZ128rmbk, + VUNPCKHPSZ128rmbkz, + VUNPCKHPSZ128rmk, + VUNPCKHPSZ128rmkz, + VUNPCKHPSZ128rr, + VUNPCKHPSZ128rrk, + VUNPCKHPSZ128rrkz, + VUNPCKHPSZ256rm, + VUNPCKHPSZ256rmb, + VUNPCKHPSZ256rmbk, + VUNPCKHPSZ256rmbkz, + VUNPCKHPSZ256rmk, + VUNPCKHPSZ256rmkz, + VUNPCKHPSZ256rr, + VUNPCKHPSZ256rrk, + VUNPCKHPSZ256rrkz, + VUNPCKHPSZrm, + VUNPCKHPSZrmb, + VUNPCKHPSZrmbk, + VUNPCKHPSZrmbkz, + VUNPCKHPSZrmk, + VUNPCKHPSZrmkz, + VUNPCKHPSZrr, + VUNPCKHPSZrrk, + VUNPCKHPSZrrkz, + VUNPCKHPSrm, + VUNPCKHPSrr, + VUNPCKLPDYrm, + VUNPCKLPDYrr, + VUNPCKLPDZ128rm, + VUNPCKLPDZ128rmb, + VUNPCKLPDZ128rmbk, + VUNPCKLPDZ128rmbkz, + VUNPCKLPDZ128rmk, + VUNPCKLPDZ128rmkz, + VUNPCKLPDZ128rr, + VUNPCKLPDZ128rrk, + VUNPCKLPDZ128rrkz, + VUNPCKLPDZ256rm, + VUNPCKLPDZ256rmb, + VUNPCKLPDZ256rmbk, + VUNPCKLPDZ256rmbkz, + VUNPCKLPDZ256rmk, + VUNPCKLPDZ256rmkz, + VUNPCKLPDZ256rr, + VUNPCKLPDZ256rrk, + VUNPCKLPDZ256rrkz, + VUNPCKLPDZrm, + VUNPCKLPDZrmb, + VUNPCKLPDZrmbk, + VUNPCKLPDZrmbkz, + VUNPCKLPDZrmk, + VUNPCKLPDZrmkz, + VUNPCKLPDZrr, + VUNPCKLPDZrrk, + VUNPCKLPDZrrkz, + VUNPCKLPDrm, + VUNPCKLPDrr, + VUNPCKLPSYrm, + VUNPCKLPSYrr, + VUNPCKLPSZ128rm, + VUNPCKLPSZ128rmb, + VUNPCKLPSZ128rmbk, + VUNPCKLPSZ128rmbkz, + VUNPCKLPSZ128rmk, + VUNPCKLPSZ128rmkz, + VUNPCKLPSZ128rr, + VUNPCKLPSZ128rrk, + VUNPCKLPSZ128rrkz, + VUNPCKLPSZ256rm, + VUNPCKLPSZ256rmb, + VUNPCKLPSZ256rmbk, + VUNPCKLPSZ256rmbkz, + VUNPCKLPSZ256rmk, + VUNPCKLPSZ256rmkz, + VUNPCKLPSZ256rr, + VUNPCKLPSZ256rrk, + VUNPCKLPSZ256rrkz, + VUNPCKLPSZrm, + VUNPCKLPSZrmb, + VUNPCKLPSZrmbk, + VUNPCKLPSZrmbkz, + VUNPCKLPSZrmk, + VUNPCKLPSZrmkz, + VUNPCKLPSZrr, + VUNPCKLPSZrrk, + VUNPCKLPSZrrkz, + VUNPCKLPSrm, + VUNPCKLPSrr, + VXORPDYrm, + VXORPDYrr, + VXORPDZ128rm, + VXORPDZ128rmb, + VXORPDZ128rmbk, + VXORPDZ128rmbkz, + VXORPDZ128rmk, + VXORPDZ128rmkz, + VXORPDZ128rr, + VXORPDZ128rrk, + VXORPDZ128rrkz, + VXORPDZ256rm, + VXORPDZ256rmb, + VXORPDZ256rmbk, + VXORPDZ256rmbkz, + VXORPDZ256rmk, + VXORPDZ256rmkz, + VXORPDZ256rr, + VXORPDZ256rrk, + VXORPDZ256rrkz, + VXORPDZrm, + VXORPDZrmb, + VXORPDZrmbk, + VXORPDZrmbkz, + VXORPDZrmk, + VXORPDZrmkz, + VXORPDZrr, + VXORPDZrrk, + VXORPDZrrkz, + VXORPDrm, + VXORPDrr, + VXORPSYrm, + VXORPSYrr, + VXORPSZ128rm, + VXORPSZ128rmb, + VXORPSZ128rmbk, + VXORPSZ128rmbkz, + VXORPSZ128rmk, + VXORPSZ128rmkz, + VXORPSZ128rr, + VXORPSZ128rrk, + VXORPSZ128rrkz, + VXORPSZ256rm, + VXORPSZ256rmb, + VXORPSZ256rmbk, + VXORPSZ256rmbkz, + VXORPSZ256rmk, + VXORPSZ256rmkz, + VXORPSZ256rr, + VXORPSZ256rrk, + VXORPSZ256rrkz, + VXORPSZrm, + VXORPSZrmb, + VXORPSZrmbk, + VXORPSZrmbkz, + VXORPSZrmk, + VXORPSZrmkz, + VXORPSZrr, + VXORPSZrrk, + VXORPSZrrkz, + VXORPSrm, + VXORPSrr, + VZEROALL, + VZEROUPPER, + WAIT, + WBINVD, + WBNOINVD, + WRFSBASE, + WRFSBASE64, + WRGSBASE, + WRGSBASE64, + WRMSR, + WRMSRLIST, + WRMSRNS, + WRMSRNSir, + WRMSRNSir_EVEX, + WRPKRUr, + WRSSD, + WRSSD_EVEX, + WRSSQ, + WRSSQ_EVEX, + WRUSSD, + WRUSSD_EVEX, + WRUSSQ, + WRUSSQ_EVEX, + XABORT, + XACQUIRE_PREFIX, + XADD16rm, + XADD16rr, + XADD32rm, + XADD32rr, + XADD64rm, + XADD64rr, + XADD8rm, + XADD8rr, + XAM_F, + XAM_Fp32, + XAM_Fp64, + XAM_Fp80, + XBEGIN, + XBEGIN_2, + XBEGIN_4, + XCHG16ar, + XCHG16rm, + XCHG16rr, + XCHG32ar, + XCHG32rm, + XCHG32rr, + XCHG64ar, + XCHG64rm, + XCHG64rr, + XCHG8rm, + XCHG8rr, + XCH_F, + XCRYPTCBC, + XCRYPTCFB, + XCRYPTCTR, + XCRYPTECB, + XCRYPTOFB, + XEND, + XGETBV, + XLAT, + XOR16i16, + XOR16mi, + XOR16mi8, + XOR16mi8_EVEX, + XOR16mi8_ND, + XOR16mi8_NF, + XOR16mi8_NF_ND, + XOR16mi_EVEX, + XOR16mi_ND, + XOR16mi_NF, + XOR16mi_NF_ND, + XOR16mr, + XOR16mr_EVEX, + XOR16mr_ND, + XOR16mr_NF, + XOR16mr_NF_ND, + XOR16ri, + XOR16ri8, + XOR16ri8_EVEX, + XOR16ri8_ND, + XOR16ri8_NF, + XOR16ri8_NF_ND, + XOR16ri_EVEX, + XOR16ri_ND, + XOR16ri_NF, + XOR16ri_NF_ND, + XOR16rm, + XOR16rm_EVEX, + XOR16rm_ND, + XOR16rm_NF, + XOR16rm_NF_ND, + XOR16rr, + XOR16rr_EVEX, + XOR16rr_EVEX_REV, + XOR16rr_ND, + XOR16rr_ND_REV, + XOR16rr_NF, + XOR16rr_NF_ND, + XOR16rr_NF_ND_REV, + XOR16rr_NF_REV, + XOR16rr_REV, + XOR32i32, + XOR32mi, + XOR32mi8, + XOR32mi8_EVEX, + XOR32mi8_ND, + XOR32mi8_NF, + XOR32mi8_NF_ND, + XOR32mi_EVEX, + XOR32mi_ND, + XOR32mi_NF, + XOR32mi_NF_ND, + XOR32mr, + XOR32mr_EVEX, + XOR32mr_ND, + XOR32mr_NF, + XOR32mr_NF_ND, + XOR32ri, + XOR32ri8, + XOR32ri8_EVEX, + XOR32ri8_ND, + XOR32ri8_NF, + XOR32ri8_NF_ND, + XOR32ri_EVEX, + XOR32ri_ND, + XOR32ri_NF, + XOR32ri_NF_ND, + XOR32rm, + XOR32rm_EVEX, + XOR32rm_ND, + XOR32rm_NF, + XOR32rm_NF_ND, + XOR32rr, + XOR32rr_EVEX, + XOR32rr_EVEX_REV, + XOR32rr_ND, + XOR32rr_ND_REV, + XOR32rr_NF, + XOR32rr_NF_ND, + XOR32rr_NF_ND_REV, + XOR32rr_NF_REV, + XOR32rr_REV, + XOR64i32, + XOR64mi32, + XOR64mi32_EVEX, + XOR64mi32_ND, + XOR64mi32_NF, + XOR64mi32_NF_ND, + XOR64mi8, + XOR64mi8_EVEX, + XOR64mi8_ND, + XOR64mi8_NF, + XOR64mi8_NF_ND, + XOR64mr, + XOR64mr_EVEX, + XOR64mr_ND, + XOR64mr_NF, + XOR64mr_NF_ND, + XOR64ri32, + XOR64ri32_EVEX, + XOR64ri32_ND, + XOR64ri32_NF, + XOR64ri32_NF_ND, + XOR64ri8, + XOR64ri8_EVEX, + XOR64ri8_ND, + XOR64ri8_NF, + XOR64ri8_NF_ND, + XOR64rm, + XOR64rm_EVEX, + XOR64rm_ND, + XOR64rm_NF, + XOR64rm_NF_ND, + XOR64rr, + XOR64rr_EVEX, + XOR64rr_EVEX_REV, + XOR64rr_ND, + XOR64rr_ND_REV, + XOR64rr_NF, + XOR64rr_NF_ND, + XOR64rr_NF_ND_REV, + XOR64rr_NF_REV, + XOR64rr_REV, + XOR8i8, + XOR8mi, + XOR8mi8, + XOR8mi_EVEX, + XOR8mi_ND, + XOR8mi_NF, + XOR8mi_NF_ND, + XOR8mr, + XOR8mr_EVEX, + XOR8mr_ND, + XOR8mr_NF, + XOR8mr_NF_ND, + XOR8ri, + XOR8ri8, + XOR8ri_EVEX, + XOR8ri_ND, + XOR8ri_NF, + XOR8ri_NF_ND, + XOR8rm, + XOR8rm_EVEX, + XOR8rm_ND, + XOR8rm_NF, + XOR8rm_NF_ND, + XOR8rr, + XOR8rr_EVEX, + XOR8rr_EVEX_REV, + XOR8rr_ND, + XOR8rr_ND_REV, + XOR8rr_NF, + XOR8rr_NF_ND, + XOR8rr_NF_ND_REV, + XOR8rr_NF_REV, + XOR8rr_NOREX, + XOR8rr_REV, + XORPDrm, + XORPDrr, + XORPSrm, + XORPSrr, + XRELEASE_PREFIX, + XRESLDTRK, + XRSTOR, + XRSTOR64, + XRSTORS, + XRSTORS64, + XSAVE, + XSAVE64, + XSAVEC, + XSAVEC64, + XSAVEOPT, + XSAVEOPT64, + XSAVES, + XSAVES64, + XSETBV, + XSHA1, + XSHA256, + XSTORE, + XSUSLDTRK, + XTEST, + INSTRUCTION_LIST_END, + UNKNOWN(u64), +} + +impl From for Opcode { + fn from(value: u64) -> Self { + match value { + 0 => Opcode::PHI, + 1 => Opcode::INLINEASM, + 2 => Opcode::INLINEASM_BR, + 3 => Opcode::CFI_INSTRUCTION, + 4 => Opcode::EH_LABEL, + 5 => Opcode::GC_LABEL, + 6 => Opcode::ANNOTATION_LABEL, + 7 => Opcode::KILL, + 8 => Opcode::EXTRACT_SUBREG, + 9 => Opcode::INSERT_SUBREG, + 10 => Opcode::IMPLICIT_DEF, + 11 => Opcode::INIT_UNDEF, + 12 => Opcode::SUBREG_TO_REG, + 13 => Opcode::COPY_TO_REGCLASS, + 14 => Opcode::DBG_VALUE, + 15 => Opcode::DBG_VALUE_LIST, + 16 => Opcode::DBG_INSTR_REF, + 17 => Opcode::DBG_PHI, + 18 => Opcode::DBG_LABEL, + 19 => Opcode::REG_SEQUENCE, + 20 => Opcode::COPY, + 21 => Opcode::COPY_LANEMASK, + 22 => Opcode::BUNDLE, + 23 => Opcode::LIFETIME_START, + 24 => Opcode::LIFETIME_END, + 25 => Opcode::PSEUDO_PROBE, + 26 => Opcode::ARITH_FENCE, + 27 => Opcode::STACKMAP, + 28 => Opcode::FENTRY_CALL, + 29 => Opcode::PATCHPOINT, + 30 => Opcode::LOAD_STACK_GUARD, + 31 => Opcode::PREALLOCATED_SETUP, + 32 => Opcode::PREALLOCATED_ARG, + 33 => Opcode::STATEPOINT, + 34 => Opcode::LOCAL_ESCAPE, + 35 => Opcode::FAULTING_OP, + 36 => Opcode::PATCHABLE_OP, + 37 => Opcode::PATCHABLE_FUNCTION_ENTER, + 38 => Opcode::PATCHABLE_RET, + 39 => Opcode::PATCHABLE_FUNCTION_EXIT, + 40 => Opcode::PATCHABLE_TAIL_CALL, + 41 => Opcode::PATCHABLE_EVENT_CALL, + 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL, + 43 => Opcode::ICALL_BRANCH_FUNNEL, + 44 => Opcode::FAKE_USE, + 45 => Opcode::MEMBARRIER, + 46 => Opcode::JUMP_TABLE_DEBUG_INFO, + 47 => Opcode::RELOC_NONE, + 48 => Opcode::CONVERGENCECTRL_ENTRY, + 49 => Opcode::CONVERGENCECTRL_ANCHOR, + 50 => Opcode::CONVERGENCECTRL_LOOP, + 51 => Opcode::CONVERGENCECTRL_GLUE, + 52 => Opcode::G_ASSERT_SEXT, + 53 => Opcode::G_ASSERT_ZEXT, + 54 => Opcode::G_ASSERT_ALIGN, + 55 => Opcode::G_ADD, + 56 => Opcode::G_SUB, + 57 => Opcode::G_MUL, + 58 => Opcode::G_SDIV, + 59 => Opcode::G_UDIV, + 60 => Opcode::G_SREM, + 61 => Opcode::G_UREM, + 62 => Opcode::G_SDIVREM, + 63 => Opcode::G_UDIVREM, + 64 => Opcode::G_AND, + 65 => Opcode::G_OR, + 66 => Opcode::G_XOR, + 67 => Opcode::G_ABDS, + 68 => Opcode::G_ABDU, + 69 => Opcode::G_UAVGFLOOR, + 70 => Opcode::G_UAVGCEIL, + 71 => Opcode::G_SAVGFLOOR, + 72 => Opcode::G_SAVGCEIL, + 73 => Opcode::G_IMPLICIT_DEF, + 74 => Opcode::G_PHI, + 75 => Opcode::G_FRAME_INDEX, + 76 => Opcode::G_GLOBAL_VALUE, + 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE, + 78 => Opcode::G_CONSTANT_POOL, + 79 => Opcode::G_EXTRACT, + 80 => Opcode::G_UNMERGE_VALUES, + 81 => Opcode::G_INSERT, + 82 => Opcode::G_MERGE_VALUES, + 83 => Opcode::G_BUILD_VECTOR, + 84 => Opcode::G_BUILD_VECTOR_TRUNC, + 85 => Opcode::G_CONCAT_VECTORS, + 86 => Opcode::G_PTRTOINT, + 87 => Opcode::G_INTTOPTR, + 88 => Opcode::G_BITCAST, + 89 => Opcode::G_FREEZE, + 90 => Opcode::G_CONSTANT_FOLD_BARRIER, + 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND, + 92 => Opcode::G_INTRINSIC_TRUNC, + 93 => Opcode::G_INTRINSIC_ROUND, + 94 => Opcode::G_INTRINSIC_LRINT, + 95 => Opcode::G_INTRINSIC_LLRINT, + 96 => Opcode::G_INTRINSIC_ROUNDEVEN, + 97 => Opcode::G_READCYCLECOUNTER, + 98 => Opcode::G_READSTEADYCOUNTER, + 99 => Opcode::G_LOAD, + 100 => Opcode::G_SEXTLOAD, + 101 => Opcode::G_ZEXTLOAD, + 102 => Opcode::G_INDEXED_LOAD, + 103 => Opcode::G_INDEXED_SEXTLOAD, + 104 => Opcode::G_INDEXED_ZEXTLOAD, + 105 => Opcode::G_STORE, + 106 => Opcode::G_INDEXED_STORE, + 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS, + 108 => Opcode::G_ATOMIC_CMPXCHG, + 109 => Opcode::G_ATOMICRMW_XCHG, + 110 => Opcode::G_ATOMICRMW_ADD, + 111 => Opcode::G_ATOMICRMW_SUB, + 112 => Opcode::G_ATOMICRMW_AND, + 113 => Opcode::G_ATOMICRMW_NAND, + 114 => Opcode::G_ATOMICRMW_OR, + 115 => Opcode::G_ATOMICRMW_XOR, + 116 => Opcode::G_ATOMICRMW_MAX, + 117 => Opcode::G_ATOMICRMW_MIN, + 118 => Opcode::G_ATOMICRMW_UMAX, + 119 => Opcode::G_ATOMICRMW_UMIN, + 120 => Opcode::G_ATOMICRMW_FADD, + 121 => Opcode::G_ATOMICRMW_FSUB, + 122 => Opcode::G_ATOMICRMW_FMAX, + 123 => Opcode::G_ATOMICRMW_FMIN, + 124 => Opcode::G_ATOMICRMW_FMAXIMUM, + 125 => Opcode::G_ATOMICRMW_FMINIMUM, + 126 => Opcode::G_ATOMICRMW_UINC_WRAP, + 127 => Opcode::G_ATOMICRMW_UDEC_WRAP, + 128 => Opcode::G_ATOMICRMW_USUB_COND, + 129 => Opcode::G_ATOMICRMW_USUB_SAT, + 130 => Opcode::G_FENCE, + 131 => Opcode::G_PREFETCH, + 132 => Opcode::G_BRCOND, + 133 => Opcode::G_BRINDIRECT, + 134 => Opcode::G_INVOKE_REGION_START, + 135 => Opcode::G_INTRINSIC, + 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS, + 137 => Opcode::G_INTRINSIC_CONVERGENT, + 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS, + 139 => Opcode::G_ANYEXT, + 140 => Opcode::G_TRUNC, + 141 => Opcode::G_TRUNC_SSAT_S, + 142 => Opcode::G_TRUNC_SSAT_U, + 143 => Opcode::G_TRUNC_USAT_U, + 144 => Opcode::G_CONSTANT, + 145 => Opcode::G_FCONSTANT, + 146 => Opcode::G_VASTART, + 147 => Opcode::G_VAARG, + 148 => Opcode::G_SEXT, + 149 => Opcode::G_SEXT_INREG, + 150 => Opcode::G_ZEXT, + 151 => Opcode::G_SHL, + 152 => Opcode::G_LSHR, + 153 => Opcode::G_ASHR, + 154 => Opcode::G_FSHL, + 155 => Opcode::G_FSHR, + 156 => Opcode::G_ROTR, + 157 => Opcode::G_ROTL, + 158 => Opcode::G_ICMP, + 159 => Opcode::G_FCMP, + 160 => Opcode::G_SCMP, + 161 => Opcode::G_UCMP, + 162 => Opcode::G_SELECT, + 163 => Opcode::G_UADDO, + 164 => Opcode::G_UADDE, + 165 => Opcode::G_USUBO, + 166 => Opcode::G_USUBE, + 167 => Opcode::G_SADDO, + 168 => Opcode::G_SADDE, + 169 => Opcode::G_SSUBO, + 170 => Opcode::G_SSUBE, + 171 => Opcode::G_UMULO, + 172 => Opcode::G_SMULO, + 173 => Opcode::G_UMULH, + 174 => Opcode::G_SMULH, + 175 => Opcode::G_UADDSAT, + 176 => Opcode::G_SADDSAT, + 177 => Opcode::G_USUBSAT, + 178 => Opcode::G_SSUBSAT, + 179 => Opcode::G_USHLSAT, + 180 => Opcode::G_SSHLSAT, + 181 => Opcode::G_SMULFIX, + 182 => Opcode::G_UMULFIX, + 183 => Opcode::G_SMULFIXSAT, + 184 => Opcode::G_UMULFIXSAT, + 185 => Opcode::G_SDIVFIX, + 186 => Opcode::G_UDIVFIX, + 187 => Opcode::G_SDIVFIXSAT, + 188 => Opcode::G_UDIVFIXSAT, + 189 => Opcode::G_FADD, + 190 => Opcode::G_FSUB, + 191 => Opcode::G_FMUL, + 192 => Opcode::G_FMA, + 193 => Opcode::G_FMAD, + 194 => Opcode::G_FDIV, + 195 => Opcode::G_FREM, + 196 => Opcode::G_FMODF, + 197 => Opcode::G_FPOW, + 198 => Opcode::G_FPOWI, + 199 => Opcode::G_FEXP, + 200 => Opcode::G_FEXP2, + 201 => Opcode::G_FEXP10, + 202 => Opcode::G_FLOG, + 203 => Opcode::G_FLOG2, + 204 => Opcode::G_FLOG10, + 205 => Opcode::G_FLDEXP, + 206 => Opcode::G_FFREXP, + 207 => Opcode::G_FNEG, + 208 => Opcode::G_FPEXT, + 209 => Opcode::G_FPTRUNC, + 210 => Opcode::G_FPTOSI, + 211 => Opcode::G_FPTOUI, + 212 => Opcode::G_SITOFP, + 213 => Opcode::G_UITOFP, + 214 => Opcode::G_FPTOSI_SAT, + 215 => Opcode::G_FPTOUI_SAT, + 216 => Opcode::G_FABS, + 217 => Opcode::G_FCOPYSIGN, + 218 => Opcode::G_IS_FPCLASS, + 219 => Opcode::G_FCANONICALIZE, + 220 => Opcode::G_FMINNUM, + 221 => Opcode::G_FMAXNUM, + 222 => Opcode::G_FMINNUM_IEEE, + 223 => Opcode::G_FMAXNUM_IEEE, + 224 => Opcode::G_FMINIMUM, + 225 => Opcode::G_FMAXIMUM, + 226 => Opcode::G_FMINIMUMNUM, + 227 => Opcode::G_FMAXIMUMNUM, + 228 => Opcode::G_GET_FPENV, + 229 => Opcode::G_SET_FPENV, + 230 => Opcode::G_RESET_FPENV, + 231 => Opcode::G_GET_FPMODE, + 232 => Opcode::G_SET_FPMODE, + 233 => Opcode::G_RESET_FPMODE, + 234 => Opcode::G_GET_ROUNDING, + 235 => Opcode::G_SET_ROUNDING, + 236 => Opcode::G_PTR_ADD, + 237 => Opcode::G_PTRMASK, + 238 => Opcode::G_SMIN, + 239 => Opcode::G_SMAX, + 240 => Opcode::G_UMIN, + 241 => Opcode::G_UMAX, + 242 => Opcode::G_ABS, + 243 => Opcode::G_LROUND, + 244 => Opcode::G_LLROUND, + 245 => Opcode::G_BR, + 246 => Opcode::G_BRJT, + 247 => Opcode::G_VSCALE, + 248 => Opcode::G_INSERT_SUBVECTOR, + 249 => Opcode::G_EXTRACT_SUBVECTOR, + 250 => Opcode::G_INSERT_VECTOR_ELT, + 251 => Opcode::G_EXTRACT_VECTOR_ELT, + 252 => Opcode::G_SHUFFLE_VECTOR, + 253 => Opcode::G_SPLAT_VECTOR, + 254 => Opcode::G_STEP_VECTOR, + 255 => Opcode::G_VECTOR_COMPRESS, + 256 => Opcode::G_CTTZ, + 257 => Opcode::G_CTTZ_ZERO_UNDEF, + 258 => Opcode::G_CTLZ, + 259 => Opcode::G_CTLZ_ZERO_UNDEF, + 260 => Opcode::G_CTPOP, + 261 => Opcode::G_BSWAP, + 262 => Opcode::G_BITREVERSE, + 263 => Opcode::G_FCEIL, + 264 => Opcode::G_FCOS, + 265 => Opcode::G_FSIN, + 266 => Opcode::G_FSINCOS, + 267 => Opcode::G_FTAN, + 268 => Opcode::G_FACOS, + 269 => Opcode::G_FASIN, + 270 => Opcode::G_FATAN, + 271 => Opcode::G_FATAN2, + 272 => Opcode::G_FCOSH, + 273 => Opcode::G_FSINH, + 274 => Opcode::G_FTANH, + 275 => Opcode::G_FSQRT, + 276 => Opcode::G_FFLOOR, + 277 => Opcode::G_FRINT, + 278 => Opcode::G_FNEARBYINT, + 279 => Opcode::G_ADDRSPACE_CAST, + 280 => Opcode::G_BLOCK_ADDR, + 281 => Opcode::G_JUMP_TABLE, + 282 => Opcode::G_DYN_STACKALLOC, + 283 => Opcode::G_STACKSAVE, + 284 => Opcode::G_STACKRESTORE, + 285 => Opcode::G_STRICT_FADD, + 286 => Opcode::G_STRICT_FSUB, + 287 => Opcode::G_STRICT_FMUL, + 288 => Opcode::G_STRICT_FDIV, + 289 => Opcode::G_STRICT_FREM, + 290 => Opcode::G_STRICT_FMA, + 291 => Opcode::G_STRICT_FSQRT, + 292 => Opcode::G_STRICT_FLDEXP, + 293 => Opcode::G_READ_REGISTER, + 294 => Opcode::G_WRITE_REGISTER, + 295 => Opcode::G_MEMCPY, + 296 => Opcode::G_MEMCPY_INLINE, + 297 => Opcode::G_MEMMOVE, + 298 => Opcode::G_MEMSET, + 299 => Opcode::G_BZERO, + 300 => Opcode::G_TRAP, + 301 => Opcode::G_DEBUGTRAP, + 302 => Opcode::G_UBSANTRAP, + 303 => Opcode::G_VECREDUCE_SEQ_FADD, + 304 => Opcode::G_VECREDUCE_SEQ_FMUL, + 305 => Opcode::G_VECREDUCE_FADD, + 306 => Opcode::G_VECREDUCE_FMUL, + 307 => Opcode::G_VECREDUCE_FMAX, + 308 => Opcode::G_VECREDUCE_FMIN, + 309 => Opcode::G_VECREDUCE_FMAXIMUM, + 310 => Opcode::G_VECREDUCE_FMINIMUM, + 311 => Opcode::G_VECREDUCE_ADD, + 312 => Opcode::G_VECREDUCE_MUL, + 313 => Opcode::G_VECREDUCE_AND, + 314 => Opcode::G_VECREDUCE_OR, + 315 => Opcode::G_VECREDUCE_XOR, + 316 => Opcode::G_VECREDUCE_SMAX, + 317 => Opcode::G_VECREDUCE_SMIN, + 318 => Opcode::G_VECREDUCE_UMAX, + 319 => Opcode::G_VECREDUCE_UMIN, + 320 => Opcode::G_SBFX, + 321 => Opcode::G_UBFX, + 322 => Opcode::ADD16ri_DB, + 323 => Opcode::ADD16rr_DB, + 324 => Opcode::ADD32ri_DB, + 325 => Opcode::ADD32rr_DB, + 326 => Opcode::ADD64ri32_DB, + 327 => Opcode::ADD64rr_DB, + 328 => Opcode::ADD8ri_DB, + 329 => Opcode::ADD8rr_DB, + 330 => Opcode::AVX1_SETALLONES, + 331 => Opcode::AVX2_SETALLONES, + 332 => Opcode::AVX512_128_SET0, + 333 => Opcode::AVX512_128_SETALLONES, + 334 => Opcode::AVX512_256_SET0, + 335 => Opcode::AVX512_256_SETALLONES, + 336 => Opcode::AVX512_512_SET0, + 337 => Opcode::AVX512_512_SETALLONES, + 338 => Opcode::AVX512_512_SEXT_MASK_32, + 339 => Opcode::AVX512_512_SEXT_MASK_64, + 340 => Opcode::AVX512_FsFLD0F128, + 341 => Opcode::AVX512_FsFLD0SD, + 342 => Opcode::AVX512_FsFLD0SH, + 343 => Opcode::AVX512_FsFLD0SS, + 344 => Opcode::AVX_SET0, + 345 => Opcode::CALL64m_RVMARKER, + 346 => Opcode::CALL64pcrel32_RVMARKER, + 347 => Opcode::CALL64r_ImpCall, + 348 => Opcode::CALL64r_RVMARKER, + 349 => Opcode::FsFLD0F128, + 350 => Opcode::FsFLD0SD, + 351 => Opcode::FsFLD0SH, + 352 => Opcode::FsFLD0SS, + 353 => Opcode::G_FILD, + 354 => Opcode::G_FIST, + 355 => Opcode::G_FLDCW16, + 356 => Opcode::G_FNSTCW16, + 357 => Opcode::INDIRECT_THUNK_CALL32, + 358 => Opcode::INDIRECT_THUNK_CALL64, + 359 => Opcode::INDIRECT_THUNK_TCRETURN32, + 360 => Opcode::INDIRECT_THUNK_TCRETURN64, + 361 => Opcode::KSET0B, + 362 => Opcode::KSET0D, + 363 => Opcode::KSET0Q, + 364 => Opcode::KSET0W, + 365 => Opcode::KSET1B, + 366 => Opcode::KSET1D, + 367 => Opcode::KSET1Q, + 368 => Opcode::KSET1W, + 369 => Opcode::LCMPXCHG16B_NO_RBX, + 370 => Opcode::LCMPXCHG16B_SAVE_RBX, + 371 => Opcode::MMX_SET0, + 372 => Opcode::MORESTACK_RET, + 373 => Opcode::MORESTACK_RET_RESTORE_R10, + 374 => Opcode::MOV32ImmSExti8, + 375 => Opcode::MOV32r0, + 376 => Opcode::MOV32r1, + 377 => Opcode::MOV32r_1, + 378 => Opcode::MOV32ri64, + 379 => Opcode::MOV64ImmSExti8, + 380 => Opcode::MOVSHPmr, + 381 => Opcode::MOVSHPrm, + 382 => Opcode::MWAITX, + 383 => Opcode::MWAITX_SAVE_RBX, + 384 => Opcode::PLDTILECFGV, + 385 => Opcode::PLEA32r, + 386 => Opcode::PLEA64r, + 387 => Opcode::PTDPBF16PSV, + 388 => Opcode::PTDPBSSDV, + 389 => Opcode::PTDPBSUDV, + 390 => Opcode::PTDPBUSDV, + 391 => Opcode::PTDPBUUDV, + 392 => Opcode::PTDPFP16PSV, + 393 => Opcode::PTILELOADDRST1V, + 394 => Opcode::PTILELOADDRSV, + 395 => Opcode::PTILELOADDT1V, + 396 => Opcode::PTILELOADDV, + 397 => Opcode::PTILESTOREDV, + 398 => Opcode::PTILEZEROV, + 399 => Opcode::RDFLAGS32, + 400 => Opcode::RDFLAGS64, + 401 => Opcode::SEH_BeginEpilogue, + 402 => Opcode::SEH_EndEpilogue, + 403 => Opcode::SEH_EndPrologue, + 404 => Opcode::SEH_PushFrame, + 405 => Opcode::SEH_PushReg, + 406 => Opcode::SEH_SaveReg, + 407 => Opcode::SEH_SaveXMM, + 408 => Opcode::SEH_SetFrame, + 409 => Opcode::SEH_StackAlign, + 410 => Opcode::SEH_StackAlloc, + 411 => Opcode::SEH_UnwindV2Start, + 412 => Opcode::SEH_UnwindVersion, + 413 => Opcode::SETB_C32r, + 414 => Opcode::SETB_C64r, + 415 => Opcode::SHLDROT32ri, + 416 => Opcode::SHLDROT64ri, + 417 => Opcode::SHRDROT32ri, + 418 => Opcode::SHRDROT64ri, + 419 => Opcode::VMOVAPSZ128mr_NOVLX, + 420 => Opcode::VMOVAPSZ128rm_NOVLX, + 421 => Opcode::VMOVAPSZ256mr_NOVLX, + 422 => Opcode::VMOVAPSZ256rm_NOVLX, + 423 => Opcode::VMOVUPSZ128mr_NOVLX, + 424 => Opcode::VMOVUPSZ128rm_NOVLX, + 425 => Opcode::VMOVUPSZ256mr_NOVLX, + 426 => Opcode::VMOVUPSZ256rm_NOVLX, + 427 => Opcode::V_SET0, + 428 => Opcode::V_SETALLONES, + 429 => Opcode::WRFLAGS32, + 430 => Opcode::WRFLAGS64, + 431 => Opcode::XABORT_DEF, + 432 => Opcode::XOR32_FP, + 433 => Opcode::XOR64_FP, + 434 => Opcode::AAA, + 435 => Opcode::AAD8i8, + 436 => Opcode::AADD32mr, + 437 => Opcode::AADD32mr_EVEX, + 438 => Opcode::AADD64mr, + 439 => Opcode::AADD64mr_EVEX, + 440 => Opcode::AAM8i8, + 441 => Opcode::AAND32mr, + 442 => Opcode::AAND32mr_EVEX, + 443 => Opcode::AAND64mr, + 444 => Opcode::AAND64mr_EVEX, + 445 => Opcode::AAS, + 446 => Opcode::ABS_F, + 447 => Opcode::ABS_Fp32, + 448 => Opcode::ABS_Fp64, + 449 => Opcode::ABS_Fp80, + 450 => Opcode::ADC16i16, + 451 => Opcode::ADC16mi, + 452 => Opcode::ADC16mi8, + 453 => Opcode::ADC16mi8_EVEX, + 454 => Opcode::ADC16mi8_ND, + 455 => Opcode::ADC16mi_EVEX, + 456 => Opcode::ADC16mi_ND, + 457 => Opcode::ADC16mr, + 458 => Opcode::ADC16mr_EVEX, + 459 => Opcode::ADC16mr_ND, + 460 => Opcode::ADC16ri, + 461 => Opcode::ADC16ri8, + 462 => Opcode::ADC16ri8_EVEX, + 463 => Opcode::ADC16ri8_ND, + 464 => Opcode::ADC16ri_EVEX, + 465 => Opcode::ADC16ri_ND, + 466 => Opcode::ADC16rm, + 467 => Opcode::ADC16rm_EVEX, + 468 => Opcode::ADC16rm_ND, + 469 => Opcode::ADC16rr, + 470 => Opcode::ADC16rr_EVEX, + 471 => Opcode::ADC16rr_EVEX_REV, + 472 => Opcode::ADC16rr_ND, + 473 => Opcode::ADC16rr_ND_REV, + 474 => Opcode::ADC16rr_REV, + 475 => Opcode::ADC32i32, + 476 => Opcode::ADC32mi, + 477 => Opcode::ADC32mi8, + 478 => Opcode::ADC32mi8_EVEX, + 479 => Opcode::ADC32mi8_ND, + 480 => Opcode::ADC32mi_EVEX, + 481 => Opcode::ADC32mi_ND, + 482 => Opcode::ADC32mr, + 483 => Opcode::ADC32mr_EVEX, + 484 => Opcode::ADC32mr_ND, + 485 => Opcode::ADC32ri, + 486 => Opcode::ADC32ri8, + 487 => Opcode::ADC32ri8_EVEX, + 488 => Opcode::ADC32ri8_ND, + 489 => Opcode::ADC32ri_EVEX, + 490 => Opcode::ADC32ri_ND, + 491 => Opcode::ADC32rm, + 492 => Opcode::ADC32rm_EVEX, + 493 => Opcode::ADC32rm_ND, + 494 => Opcode::ADC32rr, + 495 => Opcode::ADC32rr_EVEX, + 496 => Opcode::ADC32rr_EVEX_REV, + 497 => Opcode::ADC32rr_ND, + 498 => Opcode::ADC32rr_ND_REV, + 499 => Opcode::ADC32rr_REV, + 500 => Opcode::ADC64i32, + 501 => Opcode::ADC64mi32, + 502 => Opcode::ADC64mi32_EVEX, + 503 => Opcode::ADC64mi32_ND, + 504 => Opcode::ADC64mi8, + 505 => Opcode::ADC64mi8_EVEX, + 506 => Opcode::ADC64mi8_ND, + 507 => Opcode::ADC64mr, + 508 => Opcode::ADC64mr_EVEX, + 509 => Opcode::ADC64mr_ND, + 510 => Opcode::ADC64ri32, + 511 => Opcode::ADC64ri32_EVEX, + 512 => Opcode::ADC64ri32_ND, + 513 => Opcode::ADC64ri8, + 514 => Opcode::ADC64ri8_EVEX, + 515 => Opcode::ADC64ri8_ND, + 516 => Opcode::ADC64rm, + 517 => Opcode::ADC64rm_EVEX, + 518 => Opcode::ADC64rm_ND, + 519 => Opcode::ADC64rr, + 520 => Opcode::ADC64rr_EVEX, + 521 => Opcode::ADC64rr_EVEX_REV, + 522 => Opcode::ADC64rr_ND, + 523 => Opcode::ADC64rr_ND_REV, + 524 => Opcode::ADC64rr_REV, + 525 => Opcode::ADC8i8, + 526 => Opcode::ADC8mi, + 527 => Opcode::ADC8mi8, + 528 => Opcode::ADC8mi_EVEX, + 529 => Opcode::ADC8mi_ND, + 530 => Opcode::ADC8mr, + 531 => Opcode::ADC8mr_EVEX, + 532 => Opcode::ADC8mr_ND, + 533 => Opcode::ADC8ri, + 534 => Opcode::ADC8ri8, + 535 => Opcode::ADC8ri_EVEX, + 536 => Opcode::ADC8ri_ND, + 537 => Opcode::ADC8rm, + 538 => Opcode::ADC8rm_EVEX, + 539 => Opcode::ADC8rm_ND, + 540 => Opcode::ADC8rr, + 541 => Opcode::ADC8rr_EVEX, + 542 => Opcode::ADC8rr_EVEX_REV, + 543 => Opcode::ADC8rr_ND, + 544 => Opcode::ADC8rr_ND_REV, + 545 => Opcode::ADC8rr_REV, + 546 => Opcode::ADCX32rm, + 547 => Opcode::ADCX32rm_EVEX, + 548 => Opcode::ADCX32rm_ND, + 549 => Opcode::ADCX32rr, + 550 => Opcode::ADCX32rr_EVEX, + 551 => Opcode::ADCX32rr_ND, + 552 => Opcode::ADCX64rm, + 553 => Opcode::ADCX64rm_EVEX, + 554 => Opcode::ADCX64rm_ND, + 555 => Opcode::ADCX64rr, + 556 => Opcode::ADCX64rr_EVEX, + 557 => Opcode::ADCX64rr_ND, + 558 => Opcode::ADD16i16, + 559 => Opcode::ADD16mi, + 560 => Opcode::ADD16mi8, + 561 => Opcode::ADD16mi8_EVEX, + 562 => Opcode::ADD16mi8_ND, + 563 => Opcode::ADD16mi8_NF, + 564 => Opcode::ADD16mi8_NF_ND, + 565 => Opcode::ADD16mi_EVEX, + 566 => Opcode::ADD16mi_ND, + 567 => Opcode::ADD16mi_NF, + 568 => Opcode::ADD16mi_NF_ND, + 569 => Opcode::ADD16mr, + 570 => Opcode::ADD16mr_EVEX, + 571 => Opcode::ADD16mr_ND, + 572 => Opcode::ADD16mr_NF, + 573 => Opcode::ADD16mr_NF_ND, + 574 => Opcode::ADD16ri, + 575 => Opcode::ADD16ri8, + 576 => Opcode::ADD16ri8_EVEX, + 577 => Opcode::ADD16ri8_ND, + 578 => Opcode::ADD16ri8_NF, + 579 => Opcode::ADD16ri8_NF_ND, + 580 => Opcode::ADD16ri_EVEX, + 581 => Opcode::ADD16ri_ND, + 582 => Opcode::ADD16ri_NF, + 583 => Opcode::ADD16ri_NF_ND, + 584 => Opcode::ADD16rm, + 585 => Opcode::ADD16rm_EVEX, + 586 => Opcode::ADD16rm_ND, + 587 => Opcode::ADD16rm_NF, + 588 => Opcode::ADD16rm_NF_ND, + 589 => Opcode::ADD16rr, + 590 => Opcode::ADD16rr_EVEX, + 591 => Opcode::ADD16rr_EVEX_REV, + 592 => Opcode::ADD16rr_ND, + 593 => Opcode::ADD16rr_ND_REV, + 594 => Opcode::ADD16rr_NF, + 595 => Opcode::ADD16rr_NF_ND, + 596 => Opcode::ADD16rr_NF_ND_REV, + 597 => Opcode::ADD16rr_NF_REV, + 598 => Opcode::ADD16rr_REV, + 599 => Opcode::ADD32i32, + 600 => Opcode::ADD32mi, + 601 => Opcode::ADD32mi8, + 602 => Opcode::ADD32mi8_EVEX, + 603 => Opcode::ADD32mi8_ND, + 604 => Opcode::ADD32mi8_NF, + 605 => Opcode::ADD32mi8_NF_ND, + 606 => Opcode::ADD32mi_EVEX, + 607 => Opcode::ADD32mi_ND, + 608 => Opcode::ADD32mi_NF, + 609 => Opcode::ADD32mi_NF_ND, + 610 => Opcode::ADD32mr, + 611 => Opcode::ADD32mr_EVEX, + 612 => Opcode::ADD32mr_ND, + 613 => Opcode::ADD32mr_NF, + 614 => Opcode::ADD32mr_NF_ND, + 615 => Opcode::ADD32ri, + 616 => Opcode::ADD32ri8, + 617 => Opcode::ADD32ri8_EVEX, + 618 => Opcode::ADD32ri8_ND, + 619 => Opcode::ADD32ri8_NF, + 620 => Opcode::ADD32ri8_NF_ND, + 621 => Opcode::ADD32ri_EVEX, + 622 => Opcode::ADD32ri_ND, + 623 => Opcode::ADD32ri_NF, + 624 => Opcode::ADD32ri_NF_ND, + 625 => Opcode::ADD32rm, + 626 => Opcode::ADD32rm_EVEX, + 627 => Opcode::ADD32rm_ND, + 628 => Opcode::ADD32rm_NF, + 629 => Opcode::ADD32rm_NF_ND, + 630 => Opcode::ADD32rr, + 631 => Opcode::ADD32rr_EVEX, + 632 => Opcode::ADD32rr_EVEX_REV, + 633 => Opcode::ADD32rr_ND, + 634 => Opcode::ADD32rr_ND_REV, + 635 => Opcode::ADD32rr_NF, + 636 => Opcode::ADD32rr_NF_ND, + 637 => Opcode::ADD32rr_NF_ND_REV, + 638 => Opcode::ADD32rr_NF_REV, + 639 => Opcode::ADD32rr_REV, + 640 => Opcode::ADD64i32, + 641 => Opcode::ADD64mi32, + 642 => Opcode::ADD64mi32_EVEX, + 643 => Opcode::ADD64mi32_ND, + 644 => Opcode::ADD64mi32_NF, + 645 => Opcode::ADD64mi32_NF_ND, + 646 => Opcode::ADD64mi8, + 647 => Opcode::ADD64mi8_EVEX, + 648 => Opcode::ADD64mi8_ND, + 649 => Opcode::ADD64mi8_NF, + 650 => Opcode::ADD64mi8_NF_ND, + 651 => Opcode::ADD64mr, + 652 => Opcode::ADD64mr_EVEX, + 653 => Opcode::ADD64mr_ND, + 654 => Opcode::ADD64mr_NF, + 655 => Opcode::ADD64mr_NF_ND, + 656 => Opcode::ADD64ri32, + 657 => Opcode::ADD64ri32_EVEX, + 658 => Opcode::ADD64ri32_ND, + 659 => Opcode::ADD64ri32_NF, + 660 => Opcode::ADD64ri32_NF_ND, + 661 => Opcode::ADD64ri8, + 662 => Opcode::ADD64ri8_EVEX, + 663 => Opcode::ADD64ri8_ND, + 664 => Opcode::ADD64ri8_NF, + 665 => Opcode::ADD64ri8_NF_ND, + 666 => Opcode::ADD64rm, + 667 => Opcode::ADD64rm_EVEX, + 668 => Opcode::ADD64rm_ND, + 669 => Opcode::ADD64rm_NF, + 670 => Opcode::ADD64rm_NF_ND, + 671 => Opcode::ADD64rr, + 672 => Opcode::ADD64rr_EVEX, + 673 => Opcode::ADD64rr_EVEX_REV, + 674 => Opcode::ADD64rr_ND, + 675 => Opcode::ADD64rr_ND_REV, + 676 => Opcode::ADD64rr_NF, + 677 => Opcode::ADD64rr_NF_ND, + 678 => Opcode::ADD64rr_NF_ND_REV, + 679 => Opcode::ADD64rr_NF_REV, + 680 => Opcode::ADD64rr_REV, + 681 => Opcode::ADD8i8, + 682 => Opcode::ADD8mi, + 683 => Opcode::ADD8mi8, + 684 => Opcode::ADD8mi_EVEX, + 685 => Opcode::ADD8mi_ND, + 686 => Opcode::ADD8mi_NF, + 687 => Opcode::ADD8mi_NF_ND, + 688 => Opcode::ADD8mr, + 689 => Opcode::ADD8mr_EVEX, + 690 => Opcode::ADD8mr_ND, + 691 => Opcode::ADD8mr_NF, + 692 => Opcode::ADD8mr_NF_ND, + 693 => Opcode::ADD8ri, + 694 => Opcode::ADD8ri8, + 695 => Opcode::ADD8ri_EVEX, + 696 => Opcode::ADD8ri_ND, + 697 => Opcode::ADD8ri_NF, + 698 => Opcode::ADD8ri_NF_ND, + 699 => Opcode::ADD8rm, + 700 => Opcode::ADD8rm_EVEX, + 701 => Opcode::ADD8rm_ND, + 702 => Opcode::ADD8rm_NF, + 703 => Opcode::ADD8rm_NF_ND, + 704 => Opcode::ADD8rr, + 705 => Opcode::ADD8rr_EVEX, + 706 => Opcode::ADD8rr_EVEX_REV, + 707 => Opcode::ADD8rr_ND, + 708 => Opcode::ADD8rr_ND_REV, + 709 => Opcode::ADD8rr_NF, + 710 => Opcode::ADD8rr_NF_ND, + 711 => Opcode::ADD8rr_NF_ND_REV, + 712 => Opcode::ADD8rr_NF_REV, + 713 => Opcode::ADD8rr_REV, + 714 => Opcode::ADDPDrm, + 715 => Opcode::ADDPDrr, + 716 => Opcode::ADDPSrm, + 717 => Opcode::ADDPSrr, + 718 => Opcode::ADDR16_PREFIX, + 719 => Opcode::ADDR32_PREFIX, + 720 => Opcode::ADDSDrm, + 721 => Opcode::ADDSDrm_Int, + 722 => Opcode::ADDSDrr, + 723 => Opcode::ADDSDrr_Int, + 724 => Opcode::ADDSSrm, + 725 => Opcode::ADDSSrm_Int, + 726 => Opcode::ADDSSrr, + 727 => Opcode::ADDSSrr_Int, + 728 => Opcode::ADDSUBPDrm, + 729 => Opcode::ADDSUBPDrr, + 730 => Opcode::ADDSUBPSrm, + 731 => Opcode::ADDSUBPSrr, + 732 => Opcode::ADD_F32m, + 733 => Opcode::ADD_F64m, + 734 => Opcode::ADD_FI16m, + 735 => Opcode::ADD_FI32m, + 736 => Opcode::ADD_FPrST0, + 737 => Opcode::ADD_FST0r, + 738 => Opcode::ADD_Fp32, + 739 => Opcode::ADD_Fp32m, + 740 => Opcode::ADD_Fp64, + 741 => Opcode::ADD_Fp64m, + 742 => Opcode::ADD_Fp64m32, + 743 => Opcode::ADD_Fp80, + 744 => Opcode::ADD_Fp80m32, + 745 => Opcode::ADD_Fp80m64, + 746 => Opcode::ADD_FpI16m32, + 747 => Opcode::ADD_FpI16m64, + 748 => Opcode::ADD_FpI16m80, + 749 => Opcode::ADD_FpI32m32, + 750 => Opcode::ADD_FpI32m64, + 751 => Opcode::ADD_FpI32m80, + 752 => Opcode::ADD_FrST0, + 753 => Opcode::ADJCALLSTACKDOWN32, + 754 => Opcode::ADJCALLSTACKDOWN64, + 755 => Opcode::ADJCALLSTACKUP32, + 756 => Opcode::ADJCALLSTACKUP64, + 757 => Opcode::ADOX32rm, + 758 => Opcode::ADOX32rm_EVEX, + 759 => Opcode::ADOX32rm_ND, + 760 => Opcode::ADOX32rr, + 761 => Opcode::ADOX32rr_EVEX, + 762 => Opcode::ADOX32rr_ND, + 763 => Opcode::ADOX64rm, + 764 => Opcode::ADOX64rm_EVEX, + 765 => Opcode::ADOX64rm_ND, + 766 => Opcode::ADOX64rr, + 767 => Opcode::ADOX64rr_EVEX, + 768 => Opcode::ADOX64rr_ND, + 769 => Opcode::AESDEC128KL, + 770 => Opcode::AESDEC256KL, + 771 => Opcode::AESDECLASTrm, + 772 => Opcode::AESDECLASTrr, + 773 => Opcode::AESDECWIDE128KL, + 774 => Opcode::AESDECWIDE256KL, + 775 => Opcode::AESDECrm, + 776 => Opcode::AESDECrr, + 777 => Opcode::AESENC128KL, + 778 => Opcode::AESENC256KL, + 779 => Opcode::AESENCLASTrm, + 780 => Opcode::AESENCLASTrr, + 781 => Opcode::AESENCWIDE128KL, + 782 => Opcode::AESENCWIDE256KL, + 783 => Opcode::AESENCrm, + 784 => Opcode::AESENCrr, + 785 => Opcode::AESIMCrm, + 786 => Opcode::AESIMCrr, + 787 => Opcode::AESKEYGENASSISTrmi, + 788 => Opcode::AESKEYGENASSISTrri, + 789 => Opcode::AND16i16, + 790 => Opcode::AND16mi, + 791 => Opcode::AND16mi8, + 792 => Opcode::AND16mi8_EVEX, + 793 => Opcode::AND16mi8_ND, + 794 => Opcode::AND16mi8_NF, + 795 => Opcode::AND16mi8_NF_ND, + 796 => Opcode::AND16mi_EVEX, + 797 => Opcode::AND16mi_ND, + 798 => Opcode::AND16mi_NF, + 799 => Opcode::AND16mi_NF_ND, + 800 => Opcode::AND16mr, + 801 => Opcode::AND16mr_EVEX, + 802 => Opcode::AND16mr_ND, + 803 => Opcode::AND16mr_NF, + 804 => Opcode::AND16mr_NF_ND, + 805 => Opcode::AND16ri, + 806 => Opcode::AND16ri8, + 807 => Opcode::AND16ri8_EVEX, + 808 => Opcode::AND16ri8_ND, + 809 => Opcode::AND16ri8_NF, + 810 => Opcode::AND16ri8_NF_ND, + 811 => Opcode::AND16ri_EVEX, + 812 => Opcode::AND16ri_ND, + 813 => Opcode::AND16ri_NF, + 814 => Opcode::AND16ri_NF_ND, + 815 => Opcode::AND16rm, + 816 => Opcode::AND16rm_EVEX, + 817 => Opcode::AND16rm_ND, + 818 => Opcode::AND16rm_NF, + 819 => Opcode::AND16rm_NF_ND, + 820 => Opcode::AND16rr, + 821 => Opcode::AND16rr_EVEX, + 822 => Opcode::AND16rr_EVEX_REV, + 823 => Opcode::AND16rr_ND, + 824 => Opcode::AND16rr_ND_REV, + 825 => Opcode::AND16rr_NF, + 826 => Opcode::AND16rr_NF_ND, + 827 => Opcode::AND16rr_NF_ND_REV, + 828 => Opcode::AND16rr_NF_REV, + 829 => Opcode::AND16rr_REV, + 830 => Opcode::AND32i32, + 831 => Opcode::AND32mi, + 832 => Opcode::AND32mi8, + 833 => Opcode::AND32mi8_EVEX, + 834 => Opcode::AND32mi8_ND, + 835 => Opcode::AND32mi8_NF, + 836 => Opcode::AND32mi8_NF_ND, + 837 => Opcode::AND32mi_EVEX, + 838 => Opcode::AND32mi_ND, + 839 => Opcode::AND32mi_NF, + 840 => Opcode::AND32mi_NF_ND, + 841 => Opcode::AND32mr, + 842 => Opcode::AND32mr_EVEX, + 843 => Opcode::AND32mr_ND, + 844 => Opcode::AND32mr_NF, + 845 => Opcode::AND32mr_NF_ND, + 846 => Opcode::AND32ri, + 847 => Opcode::AND32ri8, + 848 => Opcode::AND32ri8_EVEX, + 849 => Opcode::AND32ri8_ND, + 850 => Opcode::AND32ri8_NF, + 851 => Opcode::AND32ri8_NF_ND, + 852 => Opcode::AND32ri_EVEX, + 853 => Opcode::AND32ri_ND, + 854 => Opcode::AND32ri_NF, + 855 => Opcode::AND32ri_NF_ND, + 856 => Opcode::AND32rm, + 857 => Opcode::AND32rm_EVEX, + 858 => Opcode::AND32rm_ND, + 859 => Opcode::AND32rm_NF, + 860 => Opcode::AND32rm_NF_ND, + 861 => Opcode::AND32rr, + 862 => Opcode::AND32rr_EVEX, + 863 => Opcode::AND32rr_EVEX_REV, + 864 => Opcode::AND32rr_ND, + 865 => Opcode::AND32rr_ND_REV, + 866 => Opcode::AND32rr_NF, + 867 => Opcode::AND32rr_NF_ND, + 868 => Opcode::AND32rr_NF_ND_REV, + 869 => Opcode::AND32rr_NF_REV, + 870 => Opcode::AND32rr_REV, + 871 => Opcode::AND64i32, + 872 => Opcode::AND64mi32, + 873 => Opcode::AND64mi32_EVEX, + 874 => Opcode::AND64mi32_ND, + 875 => Opcode::AND64mi32_NF, + 876 => Opcode::AND64mi32_NF_ND, + 877 => Opcode::AND64mi8, + 878 => Opcode::AND64mi8_EVEX, + 879 => Opcode::AND64mi8_ND, + 880 => Opcode::AND64mi8_NF, + 881 => Opcode::AND64mi8_NF_ND, + 882 => Opcode::AND64mr, + 883 => Opcode::AND64mr_EVEX, + 884 => Opcode::AND64mr_ND, + 885 => Opcode::AND64mr_NF, + 886 => Opcode::AND64mr_NF_ND, + 887 => Opcode::AND64ri32, + 888 => Opcode::AND64ri32_EVEX, + 889 => Opcode::AND64ri32_ND, + 890 => Opcode::AND64ri32_NF, + 891 => Opcode::AND64ri32_NF_ND, + 892 => Opcode::AND64ri8, + 893 => Opcode::AND64ri8_EVEX, + 894 => Opcode::AND64ri8_ND, + 895 => Opcode::AND64ri8_NF, + 896 => Opcode::AND64ri8_NF_ND, + 897 => Opcode::AND64rm, + 898 => Opcode::AND64rm_EVEX, + 899 => Opcode::AND64rm_ND, + 900 => Opcode::AND64rm_NF, + 901 => Opcode::AND64rm_NF_ND, + 902 => Opcode::AND64rr, + 903 => Opcode::AND64rr_EVEX, + 904 => Opcode::AND64rr_EVEX_REV, + 905 => Opcode::AND64rr_ND, + 906 => Opcode::AND64rr_ND_REV, + 907 => Opcode::AND64rr_NF, + 908 => Opcode::AND64rr_NF_ND, + 909 => Opcode::AND64rr_NF_ND_REV, + 910 => Opcode::AND64rr_NF_REV, + 911 => Opcode::AND64rr_REV, + 912 => Opcode::AND8i8, + 913 => Opcode::AND8mi, + 914 => Opcode::AND8mi8, + 915 => Opcode::AND8mi_EVEX, + 916 => Opcode::AND8mi_ND, + 917 => Opcode::AND8mi_NF, + 918 => Opcode::AND8mi_NF_ND, + 919 => Opcode::AND8mr, + 920 => Opcode::AND8mr_EVEX, + 921 => Opcode::AND8mr_ND, + 922 => Opcode::AND8mr_NF, + 923 => Opcode::AND8mr_NF_ND, + 924 => Opcode::AND8ri, + 925 => Opcode::AND8ri8, + 926 => Opcode::AND8ri_EVEX, + 927 => Opcode::AND8ri_ND, + 928 => Opcode::AND8ri_NF, + 929 => Opcode::AND8ri_NF_ND, + 930 => Opcode::AND8rm, + 931 => Opcode::AND8rm_EVEX, + 932 => Opcode::AND8rm_ND, + 933 => Opcode::AND8rm_NF, + 934 => Opcode::AND8rm_NF_ND, + 935 => Opcode::AND8rr, + 936 => Opcode::AND8rr_EVEX, + 937 => Opcode::AND8rr_EVEX_REV, + 938 => Opcode::AND8rr_ND, + 939 => Opcode::AND8rr_ND_REV, + 940 => Opcode::AND8rr_NF, + 941 => Opcode::AND8rr_NF_ND, + 942 => Opcode::AND8rr_NF_ND_REV, + 943 => Opcode::AND8rr_NF_REV, + 944 => Opcode::AND8rr_REV, + 945 => Opcode::ANDN32rm, + 946 => Opcode::ANDN32rm_EVEX, + 947 => Opcode::ANDN32rm_NF, + 948 => Opcode::ANDN32rr, + 949 => Opcode::ANDN32rr_EVEX, + 950 => Opcode::ANDN32rr_NF, + 951 => Opcode::ANDN64rm, + 952 => Opcode::ANDN64rm_EVEX, + 953 => Opcode::ANDN64rm_NF, + 954 => Opcode::ANDN64rr, + 955 => Opcode::ANDN64rr_EVEX, + 956 => Opcode::ANDN64rr_NF, + 957 => Opcode::ANDNPDrm, + 958 => Opcode::ANDNPDrr, + 959 => Opcode::ANDNPSrm, + 960 => Opcode::ANDNPSrr, + 961 => Opcode::ANDPDrm, + 962 => Opcode::ANDPDrr, + 963 => Opcode::ANDPSrm, + 964 => Opcode::ANDPSrr, + 965 => Opcode::AOR32mr, + 966 => Opcode::AOR32mr_EVEX, + 967 => Opcode::AOR64mr, + 968 => Opcode::AOR64mr_EVEX, + 969 => Opcode::ARPL16mr, + 970 => Opcode::ARPL16rr, + 971 => Opcode::ASAN_CHECK_MEMACCESS, + 972 => Opcode::AXOR32mr, + 973 => Opcode::AXOR32mr_EVEX, + 974 => Opcode::AXOR64mr, + 975 => Opcode::AXOR64mr_EVEX, + 976 => Opcode::BEXTR32rm, + 977 => Opcode::BEXTR32rm_EVEX, + 978 => Opcode::BEXTR32rm_NF, + 979 => Opcode::BEXTR32rr, + 980 => Opcode::BEXTR32rr_EVEX, + 981 => Opcode::BEXTR32rr_NF, + 982 => Opcode::BEXTR64rm, + 983 => Opcode::BEXTR64rm_EVEX, + 984 => Opcode::BEXTR64rm_NF, + 985 => Opcode::BEXTR64rr, + 986 => Opcode::BEXTR64rr_EVEX, + 987 => Opcode::BEXTR64rr_NF, + 988 => Opcode::BEXTRI32mi, + 989 => Opcode::BEXTRI32ri, + 990 => Opcode::BEXTRI64mi, + 991 => Opcode::BEXTRI64ri, + 992 => Opcode::BLCFILL32rm, + 993 => Opcode::BLCFILL32rr, + 994 => Opcode::BLCFILL64rm, + 995 => Opcode::BLCFILL64rr, + 996 => Opcode::BLCI32rm, + 997 => Opcode::BLCI32rr, + 998 => Opcode::BLCI64rm, + 999 => Opcode::BLCI64rr, + 1000 => Opcode::BLCIC32rm, + 1001 => Opcode::BLCIC32rr, + 1002 => Opcode::BLCIC64rm, + 1003 => Opcode::BLCIC64rr, + 1004 => Opcode::BLCMSK32rm, + 1005 => Opcode::BLCMSK32rr, + 1006 => Opcode::BLCMSK64rm, + 1007 => Opcode::BLCMSK64rr, + 1008 => Opcode::BLCS32rm, + 1009 => Opcode::BLCS32rr, + 1010 => Opcode::BLCS64rm, + 1011 => Opcode::BLCS64rr, + 1012 => Opcode::BLENDPDrmi, + 1013 => Opcode::BLENDPDrri, + 1014 => Opcode::BLENDPSrmi, + 1015 => Opcode::BLENDPSrri, + 1016 => Opcode::BLENDVPDrm0, + 1017 => Opcode::BLENDVPDrr0, + 1018 => Opcode::BLENDVPSrm0, + 1019 => Opcode::BLENDVPSrr0, + 1020 => Opcode::BLSFILL32rm, + 1021 => Opcode::BLSFILL32rr, + 1022 => Opcode::BLSFILL64rm, + 1023 => Opcode::BLSFILL64rr, + 1024 => Opcode::BLSI32rm, + 1025 => Opcode::BLSI32rm_EVEX, + 1026 => Opcode::BLSI32rm_NF, + 1027 => Opcode::BLSI32rr, + 1028 => Opcode::BLSI32rr_EVEX, + 1029 => Opcode::BLSI32rr_NF, + 1030 => Opcode::BLSI64rm, + 1031 => Opcode::BLSI64rm_EVEX, + 1032 => Opcode::BLSI64rm_NF, + 1033 => Opcode::BLSI64rr, + 1034 => Opcode::BLSI64rr_EVEX, + 1035 => Opcode::BLSI64rr_NF, + 1036 => Opcode::BLSIC32rm, + 1037 => Opcode::BLSIC32rr, + 1038 => Opcode::BLSIC64rm, + 1039 => Opcode::BLSIC64rr, + 1040 => Opcode::BLSMSK32rm, + 1041 => Opcode::BLSMSK32rm_EVEX, + 1042 => Opcode::BLSMSK32rm_NF, + 1043 => Opcode::BLSMSK32rr, + 1044 => Opcode::BLSMSK32rr_EVEX, + 1045 => Opcode::BLSMSK32rr_NF, + 1046 => Opcode::BLSMSK64rm, + 1047 => Opcode::BLSMSK64rm_EVEX, + 1048 => Opcode::BLSMSK64rm_NF, + 1049 => Opcode::BLSMSK64rr, + 1050 => Opcode::BLSMSK64rr_EVEX, + 1051 => Opcode::BLSMSK64rr_NF, + 1052 => Opcode::BLSR32rm, + 1053 => Opcode::BLSR32rm_EVEX, + 1054 => Opcode::BLSR32rm_NF, + 1055 => Opcode::BLSR32rr, + 1056 => Opcode::BLSR32rr_EVEX, + 1057 => Opcode::BLSR32rr_NF, + 1058 => Opcode::BLSR64rm, + 1059 => Opcode::BLSR64rm_EVEX, + 1060 => Opcode::BLSR64rm_NF, + 1061 => Opcode::BLSR64rr, + 1062 => Opcode::BLSR64rr_EVEX, + 1063 => Opcode::BLSR64rr_NF, + 1064 => Opcode::BOUNDS16rm, + 1065 => Opcode::BOUNDS32rm, + 1066 => Opcode::BSF16rm, + 1067 => Opcode::BSF16rr, + 1068 => Opcode::BSF32rm, + 1069 => Opcode::BSF32rr, + 1070 => Opcode::BSF64rm, + 1071 => Opcode::BSF64rr, + 1072 => Opcode::BSR16rm, + 1073 => Opcode::BSR16rr, + 1074 => Opcode::BSR32rm, + 1075 => Opcode::BSR32rr, + 1076 => Opcode::BSR64rm, + 1077 => Opcode::BSR64rr, + 1078 => Opcode::BSWAP16r_BAD, + 1079 => Opcode::BSWAP32r, + 1080 => Opcode::BSWAP64r, + 1081 => Opcode::BT16mi8, + 1082 => Opcode::BT16mr, + 1083 => Opcode::BT16ri8, + 1084 => Opcode::BT16rr, + 1085 => Opcode::BT32mi8, + 1086 => Opcode::BT32mr, + 1087 => Opcode::BT32ri8, + 1088 => Opcode::BT32rr, + 1089 => Opcode::BT64mi8, + 1090 => Opcode::BT64mr, + 1091 => Opcode::BT64ri8, + 1092 => Opcode::BT64rr, + 1093 => Opcode::BTC16mi8, + 1094 => Opcode::BTC16mr, + 1095 => Opcode::BTC16ri8, + 1096 => Opcode::BTC16rr, + 1097 => Opcode::BTC32mi8, + 1098 => Opcode::BTC32mr, + 1099 => Opcode::BTC32ri8, + 1100 => Opcode::BTC32rr, + 1101 => Opcode::BTC64mi8, + 1102 => Opcode::BTC64mr, + 1103 => Opcode::BTC64ri8, + 1104 => Opcode::BTC64rr, + 1105 => Opcode::BTR16mi8, + 1106 => Opcode::BTR16mr, + 1107 => Opcode::BTR16ri8, + 1108 => Opcode::BTR16rr, + 1109 => Opcode::BTR32mi8, + 1110 => Opcode::BTR32mr, + 1111 => Opcode::BTR32ri8, + 1112 => Opcode::BTR32rr, + 1113 => Opcode::BTR64mi8, + 1114 => Opcode::BTR64mr, + 1115 => Opcode::BTR64ri8, + 1116 => Opcode::BTR64rr, + 1117 => Opcode::BTS16mi8, + 1118 => Opcode::BTS16mr, + 1119 => Opcode::BTS16ri8, + 1120 => Opcode::BTS16rr, + 1121 => Opcode::BTS32mi8, + 1122 => Opcode::BTS32mr, + 1123 => Opcode::BTS32ri8, + 1124 => Opcode::BTS32rr, + 1125 => Opcode::BTS64mi8, + 1126 => Opcode::BTS64mr, + 1127 => Opcode::BTS64ri8, + 1128 => Opcode::BTS64rr, + 1129 => Opcode::BZHI32rm, + 1130 => Opcode::BZHI32rm_EVEX, + 1131 => Opcode::BZHI32rm_NF, + 1132 => Opcode::BZHI32rr, + 1133 => Opcode::BZHI32rr_EVEX, + 1134 => Opcode::BZHI32rr_NF, + 1135 => Opcode::BZHI64rm, + 1136 => Opcode::BZHI64rm_EVEX, + 1137 => Opcode::BZHI64rm_NF, + 1138 => Opcode::BZHI64rr, + 1139 => Opcode::BZHI64rr_EVEX, + 1140 => Opcode::BZHI64rr_NF, + 1141 => Opcode::CALL16m, + 1142 => Opcode::CALL16m_NT, + 1143 => Opcode::CALL16r, + 1144 => Opcode::CALL16r_NT, + 1145 => Opcode::CALL32m, + 1146 => Opcode::CALL32m_NT, + 1147 => Opcode::CALL32r, + 1148 => Opcode::CALL32r_NT, + 1149 => Opcode::CALL64m, + 1150 => Opcode::CALL64m_NT, + 1151 => Opcode::CALL64pcrel32, + 1152 => Opcode::CALL64r, + 1153 => Opcode::CALL64r_NT, + 1154 => Opcode::CALLpcrel16, + 1155 => Opcode::CALLpcrel32, + 1156 => Opcode::CATCHRET, + 1157 => Opcode::CBW, + 1158 => Opcode::CCMP16mi, + 1159 => Opcode::CCMP16mi8, + 1160 => Opcode::CCMP16mr, + 1161 => Opcode::CCMP16ri, + 1162 => Opcode::CCMP16ri8, + 1163 => Opcode::CCMP16rm, + 1164 => Opcode::CCMP16rr, + 1165 => Opcode::CCMP16rr_REV, + 1166 => Opcode::CCMP32mi, + 1167 => Opcode::CCMP32mi8, + 1168 => Opcode::CCMP32mr, + 1169 => Opcode::CCMP32ri, + 1170 => Opcode::CCMP32ri8, + 1171 => Opcode::CCMP32rm, + 1172 => Opcode::CCMP32rr, + 1173 => Opcode::CCMP32rr_REV, + 1174 => Opcode::CCMP64mi32, + 1175 => Opcode::CCMP64mi8, + 1176 => Opcode::CCMP64mr, + 1177 => Opcode::CCMP64ri32, + 1178 => Opcode::CCMP64ri8, + 1179 => Opcode::CCMP64rm, + 1180 => Opcode::CCMP64rr, + 1181 => Opcode::CCMP64rr_REV, + 1182 => Opcode::CCMP8mi, + 1183 => Opcode::CCMP8mr, + 1184 => Opcode::CCMP8ri, + 1185 => Opcode::CCMP8rm, + 1186 => Opcode::CCMP8rr, + 1187 => Opcode::CCMP8rr_REV, + 1188 => Opcode::CDQ, + 1189 => Opcode::CDQE, + 1190 => Opcode::CFCMOV16mr, + 1191 => Opcode::CFCMOV16rm, + 1192 => Opcode::CFCMOV16rm_ND, + 1193 => Opcode::CFCMOV16rr, + 1194 => Opcode::CFCMOV16rr_ND, + 1195 => Opcode::CFCMOV16rr_REV, + 1196 => Opcode::CFCMOV32mr, + 1197 => Opcode::CFCMOV32rm, + 1198 => Opcode::CFCMOV32rm_ND, + 1199 => Opcode::CFCMOV32rr, + 1200 => Opcode::CFCMOV32rr_ND, + 1201 => Opcode::CFCMOV32rr_REV, + 1202 => Opcode::CFCMOV64mr, + 1203 => Opcode::CFCMOV64rm, + 1204 => Opcode::CFCMOV64rm_ND, + 1205 => Opcode::CFCMOV64rr, + 1206 => Opcode::CFCMOV64rr_ND, + 1207 => Opcode::CFCMOV64rr_REV, + 1208 => Opcode::CHS_F, + 1209 => Opcode::CHS_Fp32, + 1210 => Opcode::CHS_Fp64, + 1211 => Opcode::CHS_Fp80, + 1212 => Opcode::CLAC, + 1213 => Opcode::CLC, + 1214 => Opcode::CLD, + 1215 => Opcode::CLDEMOTE, + 1216 => Opcode::CLEANUPRET, + 1217 => Opcode::CLFLUSH, + 1218 => Opcode::CLFLUSHOPT, + 1219 => Opcode::CLGI, + 1220 => Opcode::CLI, + 1221 => Opcode::CLRSSBSY, + 1222 => Opcode::CLTS, + 1223 => Opcode::CLUI, + 1224 => Opcode::CLWB, + 1225 => Opcode::CLZERO32r, + 1226 => Opcode::CLZERO64r, + 1227 => Opcode::CMC, + 1228 => Opcode::CMOV16rm, + 1229 => Opcode::CMOV16rm_ND, + 1230 => Opcode::CMOV16rr, + 1231 => Opcode::CMOV16rr_ND, + 1232 => Opcode::CMOV32rm, + 1233 => Opcode::CMOV32rm_ND, + 1234 => Opcode::CMOV32rr, + 1235 => Opcode::CMOV32rr_ND, + 1236 => Opcode::CMOV64rm, + 1237 => Opcode::CMOV64rm_ND, + 1238 => Opcode::CMOV64rr, + 1239 => Opcode::CMOV64rr_ND, + 1240 => Opcode::CMOVBE_F, + 1241 => Opcode::CMOVBE_Fp32, + 1242 => Opcode::CMOVBE_Fp64, + 1243 => Opcode::CMOVBE_Fp80, + 1244 => Opcode::CMOVB_F, + 1245 => Opcode::CMOVB_Fp32, + 1246 => Opcode::CMOVB_Fp64, + 1247 => Opcode::CMOVB_Fp80, + 1248 => Opcode::CMOVE_F, + 1249 => Opcode::CMOVE_Fp32, + 1250 => Opcode::CMOVE_Fp64, + 1251 => Opcode::CMOVE_Fp80, + 1252 => Opcode::CMOVNBE_F, + 1253 => Opcode::CMOVNBE_Fp32, + 1254 => Opcode::CMOVNBE_Fp64, + 1255 => Opcode::CMOVNBE_Fp80, + 1256 => Opcode::CMOVNB_F, + 1257 => Opcode::CMOVNB_Fp32, + 1258 => Opcode::CMOVNB_Fp64, + 1259 => Opcode::CMOVNB_Fp80, + 1260 => Opcode::CMOVNE_F, + 1261 => Opcode::CMOVNE_Fp32, + 1262 => Opcode::CMOVNE_Fp64, + 1263 => Opcode::CMOVNE_Fp80, + 1264 => Opcode::CMOVNP_F, + 1265 => Opcode::CMOVNP_Fp32, + 1266 => Opcode::CMOVNP_Fp64, + 1267 => Opcode::CMOVNP_Fp80, + 1268 => Opcode::CMOVP_F, + 1269 => Opcode::CMOVP_Fp32, + 1270 => Opcode::CMOVP_Fp64, + 1271 => Opcode::CMOVP_Fp80, + 1272 => Opcode::CMOV_FR16, + 1273 => Opcode::CMOV_FR16X, + 1274 => Opcode::CMOV_FR32, + 1275 => Opcode::CMOV_FR32X, + 1276 => Opcode::CMOV_FR64, + 1277 => Opcode::CMOV_FR64X, + 1278 => Opcode::CMOV_GR16, + 1279 => Opcode::CMOV_GR32, + 1280 => Opcode::CMOV_GR8, + 1281 => Opcode::CMOV_RFP32, + 1282 => Opcode::CMOV_RFP64, + 1283 => Opcode::CMOV_RFP80, + 1284 => Opcode::CMOV_VK1, + 1285 => Opcode::CMOV_VK16, + 1286 => Opcode::CMOV_VK2, + 1287 => Opcode::CMOV_VK32, + 1288 => Opcode::CMOV_VK4, + 1289 => Opcode::CMOV_VK64, + 1290 => Opcode::CMOV_VK8, + 1291 => Opcode::CMOV_VR128, + 1292 => Opcode::CMOV_VR128X, + 1293 => Opcode::CMOV_VR256, + 1294 => Opcode::CMOV_VR256X, + 1295 => Opcode::CMOV_VR512, + 1296 => Opcode::CMOV_VR64, + 1297 => Opcode::CMP16i16, + 1298 => Opcode::CMP16mi, + 1299 => Opcode::CMP16mi8, + 1300 => Opcode::CMP16mr, + 1301 => Opcode::CMP16ri, + 1302 => Opcode::CMP16ri8, + 1303 => Opcode::CMP16rm, + 1304 => Opcode::CMP16rr, + 1305 => Opcode::CMP16rr_REV, + 1306 => Opcode::CMP32i32, + 1307 => Opcode::CMP32mi, + 1308 => Opcode::CMP32mi8, + 1309 => Opcode::CMP32mr, + 1310 => Opcode::CMP32ri, + 1311 => Opcode::CMP32ri8, + 1312 => Opcode::CMP32rm, + 1313 => Opcode::CMP32rr, + 1314 => Opcode::CMP32rr_REV, + 1315 => Opcode::CMP64i32, + 1316 => Opcode::CMP64mi32, + 1317 => Opcode::CMP64mi8, + 1318 => Opcode::CMP64mr, + 1319 => Opcode::CMP64ri32, + 1320 => Opcode::CMP64ri8, + 1321 => Opcode::CMP64rm, + 1322 => Opcode::CMP64rr, + 1323 => Opcode::CMP64rr_REV, + 1324 => Opcode::CMP8i8, + 1325 => Opcode::CMP8mi, + 1326 => Opcode::CMP8mi8, + 1327 => Opcode::CMP8mr, + 1328 => Opcode::CMP8ri, + 1329 => Opcode::CMP8ri8, + 1330 => Opcode::CMP8rm, + 1331 => Opcode::CMP8rr, + 1332 => Opcode::CMP8rr_REV, + 1333 => Opcode::CMPCCXADDmr32, + 1334 => Opcode::CMPCCXADDmr32_EVEX, + 1335 => Opcode::CMPCCXADDmr64, + 1336 => Opcode::CMPCCXADDmr64_EVEX, + 1337 => Opcode::CMPPDrmi, + 1338 => Opcode::CMPPDrri, + 1339 => Opcode::CMPPSrmi, + 1340 => Opcode::CMPPSrri, + 1341 => Opcode::CMPSB, + 1342 => Opcode::CMPSDrmi, + 1343 => Opcode::CMPSDrmi_Int, + 1344 => Opcode::CMPSDrri, + 1345 => Opcode::CMPSDrri_Int, + 1346 => Opcode::CMPSL, + 1347 => Opcode::CMPSQ, + 1348 => Opcode::CMPSSrmi, + 1349 => Opcode::CMPSSrmi_Int, + 1350 => Opcode::CMPSSrri, + 1351 => Opcode::CMPSSrri_Int, + 1352 => Opcode::CMPSW, + 1353 => Opcode::CMPXCHG16B, + 1354 => Opcode::CMPXCHG16rm, + 1355 => Opcode::CMPXCHG16rr, + 1356 => Opcode::CMPXCHG32rm, + 1357 => Opcode::CMPXCHG32rr, + 1358 => Opcode::CMPXCHG64rm, + 1359 => Opcode::CMPXCHG64rr, + 1360 => Opcode::CMPXCHG8B, + 1361 => Opcode::CMPXCHG8rm, + 1362 => Opcode::CMPXCHG8rr, + 1363 => Opcode::COMISDrm, + 1364 => Opcode::COMISDrm_Int, + 1365 => Opcode::COMISDrr, + 1366 => Opcode::COMISDrr_Int, + 1367 => Opcode::COMISSrm, + 1368 => Opcode::COMISSrm_Int, + 1369 => Opcode::COMISSrr, + 1370 => Opcode::COMISSrr_Int, + 1371 => Opcode::COMP_FST0r, + 1372 => Opcode::COM_FIPr, + 1373 => Opcode::COM_FIr, + 1374 => Opcode::COM_FST0r, + 1375 => Opcode::COM_FpIr32, + 1376 => Opcode::COM_FpIr64, + 1377 => Opcode::COM_FpIr80, + 1378 => Opcode::COM_Fpr32, + 1379 => Opcode::COM_Fpr64, + 1380 => Opcode::COM_Fpr80, + 1381 => Opcode::CPUID, + 1382 => Opcode::CQO, + 1383 => Opcode::CRC32r32m16, + 1384 => Opcode::CRC32r32m16_EVEX, + 1385 => Opcode::CRC32r32m32, + 1386 => Opcode::CRC32r32m32_EVEX, + 1387 => Opcode::CRC32r32m8, + 1388 => Opcode::CRC32r32m8_EVEX, + 1389 => Opcode::CRC32r32r16, + 1390 => Opcode::CRC32r32r16_EVEX, + 1391 => Opcode::CRC32r32r32, + 1392 => Opcode::CRC32r32r32_EVEX, + 1393 => Opcode::CRC32r32r8, + 1394 => Opcode::CRC32r32r8_EVEX, + 1395 => Opcode::CRC32r64m64, + 1396 => Opcode::CRC32r64m64_EVEX, + 1397 => Opcode::CRC32r64m8, + 1398 => Opcode::CRC32r64m8_EVEX, + 1399 => Opcode::CRC32r64r64, + 1400 => Opcode::CRC32r64r64_EVEX, + 1401 => Opcode::CRC32r64r8, + 1402 => Opcode::CRC32r64r8_EVEX, + 1403 => Opcode::CS_PREFIX, + 1404 => Opcode::CTEST16mi, + 1405 => Opcode::CTEST16mr, + 1406 => Opcode::CTEST16ri, + 1407 => Opcode::CTEST16rr, + 1408 => Opcode::CTEST32mi, + 1409 => Opcode::CTEST32mr, + 1410 => Opcode::CTEST32ri, + 1411 => Opcode::CTEST32rr, + 1412 => Opcode::CTEST64mi32, + 1413 => Opcode::CTEST64mr, + 1414 => Opcode::CTEST64ri32, + 1415 => Opcode::CTEST64rr, + 1416 => Opcode::CTEST8mi, + 1417 => Opcode::CTEST8mr, + 1418 => Opcode::CTEST8ri, + 1419 => Opcode::CTEST8rr, + 1420 => Opcode::CVTDQ2PDrm, + 1421 => Opcode::CVTDQ2PDrr, + 1422 => Opcode::CVTDQ2PSrm, + 1423 => Opcode::CVTDQ2PSrr, + 1424 => Opcode::CVTPD2DQrm, + 1425 => Opcode::CVTPD2DQrr, + 1426 => Opcode::CVTPD2PSrm, + 1427 => Opcode::CVTPD2PSrr, + 1428 => Opcode::CVTPS2DQrm, + 1429 => Opcode::CVTPS2DQrr, + 1430 => Opcode::CVTPS2PDrm, + 1431 => Opcode::CVTPS2PDrr, + 1432 => Opcode::CVTSD2SI64rm, + 1433 => Opcode::CVTSD2SI64rm_Int, + 1434 => Opcode::CVTSD2SI64rr, + 1435 => Opcode::CVTSD2SI64rr_Int, + 1436 => Opcode::CVTSD2SIrm, + 1437 => Opcode::CVTSD2SIrm_Int, + 1438 => Opcode::CVTSD2SIrr, + 1439 => Opcode::CVTSD2SIrr_Int, + 1440 => Opcode::CVTSD2SSrm, + 1441 => Opcode::CVTSD2SSrm_Int, + 1442 => Opcode::CVTSD2SSrr, + 1443 => Opcode::CVTSD2SSrr_Int, + 1444 => Opcode::CVTSI2SDrm, + 1445 => Opcode::CVTSI2SDrm_Int, + 1446 => Opcode::CVTSI2SDrr, + 1447 => Opcode::CVTSI2SDrr_Int, + 1448 => Opcode::CVTSI2SSrm, + 1449 => Opcode::CVTSI2SSrm_Int, + 1450 => Opcode::CVTSI2SSrr, + 1451 => Opcode::CVTSI2SSrr_Int, + 1452 => Opcode::CVTSI642SDrm, + 1453 => Opcode::CVTSI642SDrm_Int, + 1454 => Opcode::CVTSI642SDrr, + 1455 => Opcode::CVTSI642SDrr_Int, + 1456 => Opcode::CVTSI642SSrm, + 1457 => Opcode::CVTSI642SSrm_Int, + 1458 => Opcode::CVTSI642SSrr, + 1459 => Opcode::CVTSI642SSrr_Int, + 1460 => Opcode::CVTSS2SDrm, + 1461 => Opcode::CVTSS2SDrm_Int, + 1462 => Opcode::CVTSS2SDrr, + 1463 => Opcode::CVTSS2SDrr_Int, + 1464 => Opcode::CVTSS2SI64rm, + 1465 => Opcode::CVTSS2SI64rm_Int, + 1466 => Opcode::CVTSS2SI64rr, + 1467 => Opcode::CVTSS2SI64rr_Int, + 1468 => Opcode::CVTSS2SIrm, + 1469 => Opcode::CVTSS2SIrm_Int, + 1470 => Opcode::CVTSS2SIrr, + 1471 => Opcode::CVTSS2SIrr_Int, + 1472 => Opcode::CVTTPD2DQrm, + 1473 => Opcode::CVTTPD2DQrr, + 1474 => Opcode::CVTTPS2DQrm, + 1475 => Opcode::CVTTPS2DQrr, + 1476 => Opcode::CVTTSD2SI64rm, + 1477 => Opcode::CVTTSD2SI64rm_Int, + 1478 => Opcode::CVTTSD2SI64rr, + 1479 => Opcode::CVTTSD2SI64rr_Int, + 1480 => Opcode::CVTTSD2SIrm, + 1481 => Opcode::CVTTSD2SIrm_Int, + 1482 => Opcode::CVTTSD2SIrr, + 1483 => Opcode::CVTTSD2SIrr_Int, + 1484 => Opcode::CVTTSS2SI64rm, + 1485 => Opcode::CVTTSS2SI64rm_Int, + 1486 => Opcode::CVTTSS2SI64rr, + 1487 => Opcode::CVTTSS2SI64rr_Int, + 1488 => Opcode::CVTTSS2SIrm, + 1489 => Opcode::CVTTSS2SIrm_Int, + 1490 => Opcode::CVTTSS2SIrr, + 1491 => Opcode::CVTTSS2SIrr_Int, + 1492 => Opcode::CWD, + 1493 => Opcode::CWDE, + 1494 => Opcode::DAA, + 1495 => Opcode::DAS, + 1496 => Opcode::DATA16_PREFIX, + 1497 => Opcode::DEC16m, + 1498 => Opcode::DEC16m_EVEX, + 1499 => Opcode::DEC16m_ND, + 1500 => Opcode::DEC16m_NF, + 1501 => Opcode::DEC16m_NF_ND, + 1502 => Opcode::DEC16r, + 1503 => Opcode::DEC16r_EVEX, + 1504 => Opcode::DEC16r_ND, + 1505 => Opcode::DEC16r_NF, + 1506 => Opcode::DEC16r_NF_ND, + 1507 => Opcode::DEC16r_alt, + 1508 => Opcode::DEC32m, + 1509 => Opcode::DEC32m_EVEX, + 1510 => Opcode::DEC32m_ND, + 1511 => Opcode::DEC32m_NF, + 1512 => Opcode::DEC32m_NF_ND, + 1513 => Opcode::DEC32r, + 1514 => Opcode::DEC32r_EVEX, + 1515 => Opcode::DEC32r_ND, + 1516 => Opcode::DEC32r_NF, + 1517 => Opcode::DEC32r_NF_ND, + 1518 => Opcode::DEC32r_alt, + 1519 => Opcode::DEC64m, + 1520 => Opcode::DEC64m_EVEX, + 1521 => Opcode::DEC64m_ND, + 1522 => Opcode::DEC64m_NF, + 1523 => Opcode::DEC64m_NF_ND, + 1524 => Opcode::DEC64r, + 1525 => Opcode::DEC64r_EVEX, + 1526 => Opcode::DEC64r_ND, + 1527 => Opcode::DEC64r_NF, + 1528 => Opcode::DEC64r_NF_ND, + 1529 => Opcode::DEC8m, + 1530 => Opcode::DEC8m_EVEX, + 1531 => Opcode::DEC8m_ND, + 1532 => Opcode::DEC8m_NF, + 1533 => Opcode::DEC8m_NF_ND, + 1534 => Opcode::DEC8r, + 1535 => Opcode::DEC8r_EVEX, + 1536 => Opcode::DEC8r_ND, + 1537 => Opcode::DEC8r_NF, + 1538 => Opcode::DEC8r_NF_ND, + 1539 => Opcode::DIV16m, + 1540 => Opcode::DIV16m_EVEX, + 1541 => Opcode::DIV16m_NF, + 1542 => Opcode::DIV16r, + 1543 => Opcode::DIV16r_EVEX, + 1544 => Opcode::DIV16r_NF, + 1545 => Opcode::DIV32m, + 1546 => Opcode::DIV32m_EVEX, + 1547 => Opcode::DIV32m_NF, + 1548 => Opcode::DIV32r, + 1549 => Opcode::DIV32r_EVEX, + 1550 => Opcode::DIV32r_NF, + 1551 => Opcode::DIV64m, + 1552 => Opcode::DIV64m_EVEX, + 1553 => Opcode::DIV64m_NF, + 1554 => Opcode::DIV64r, + 1555 => Opcode::DIV64r_EVEX, + 1556 => Opcode::DIV64r_NF, + 1557 => Opcode::DIV8m, + 1558 => Opcode::DIV8m_EVEX, + 1559 => Opcode::DIV8m_NF, + 1560 => Opcode::DIV8r, + 1561 => Opcode::DIV8r_EVEX, + 1562 => Opcode::DIV8r_NF, + 1563 => Opcode::DIVPDrm, + 1564 => Opcode::DIVPDrr, + 1565 => Opcode::DIVPSrm, + 1566 => Opcode::DIVPSrr, + 1567 => Opcode::DIVR_F32m, + 1568 => Opcode::DIVR_F64m, + 1569 => Opcode::DIVR_FI16m, + 1570 => Opcode::DIVR_FI32m, + 1571 => Opcode::DIVR_FPrST0, + 1572 => Opcode::DIVR_FST0r, + 1573 => Opcode::DIVR_Fp32m, + 1574 => Opcode::DIVR_Fp64m, + 1575 => Opcode::DIVR_Fp64m32, + 1576 => Opcode::DIVR_Fp80m32, + 1577 => Opcode::DIVR_Fp80m64, + 1578 => Opcode::DIVR_FpI16m32, + 1579 => Opcode::DIVR_FpI16m64, + 1580 => Opcode::DIVR_FpI16m80, + 1581 => Opcode::DIVR_FpI32m32, + 1582 => Opcode::DIVR_FpI32m64, + 1583 => Opcode::DIVR_FpI32m80, + 1584 => Opcode::DIVR_FrST0, + 1585 => Opcode::DIVSDrm, + 1586 => Opcode::DIVSDrm_Int, + 1587 => Opcode::DIVSDrr, + 1588 => Opcode::DIVSDrr_Int, + 1589 => Opcode::DIVSSrm, + 1590 => Opcode::DIVSSrm_Int, + 1591 => Opcode::DIVSSrr, + 1592 => Opcode::DIVSSrr_Int, + 1593 => Opcode::DIV_F32m, + 1594 => Opcode::DIV_F64m, + 1595 => Opcode::DIV_FI16m, + 1596 => Opcode::DIV_FI32m, + 1597 => Opcode::DIV_FPrST0, + 1598 => Opcode::DIV_FST0r, + 1599 => Opcode::DIV_Fp32, + 1600 => Opcode::DIV_Fp32m, + 1601 => Opcode::DIV_Fp64, + 1602 => Opcode::DIV_Fp64m, + 1603 => Opcode::DIV_Fp64m32, + 1604 => Opcode::DIV_Fp80, + 1605 => Opcode::DIV_Fp80m32, + 1606 => Opcode::DIV_Fp80m64, + 1607 => Opcode::DIV_FpI16m32, + 1608 => Opcode::DIV_FpI16m64, + 1609 => Opcode::DIV_FpI16m80, + 1610 => Opcode::DIV_FpI32m32, + 1611 => Opcode::DIV_FpI32m64, + 1612 => Opcode::DIV_FpI32m80, + 1613 => Opcode::DIV_FrST0, + 1614 => Opcode::DPPDrmi, + 1615 => Opcode::DPPDrri, + 1616 => Opcode::DPPSrmi, + 1617 => Opcode::DPPSrri, + 1618 => Opcode::DS_PREFIX, + 1619 => Opcode::DYN_ALLOCA_32, + 1620 => Opcode::DYN_ALLOCA_64, + 1621 => Opcode::EH_RETURN, + 1622 => Opcode::EH_RETURN64, + 1623 => Opcode::EH_SjLj_LongJmp32, + 1624 => Opcode::EH_SjLj_LongJmp64, + 1625 => Opcode::EH_SjLj_SetJmp32, + 1626 => Opcode::EH_SjLj_SetJmp64, + 1627 => Opcode::EH_SjLj_Setup, + 1628 => Opcode::ENCLS, + 1629 => Opcode::ENCLU, + 1630 => Opcode::ENCLV, + 1631 => Opcode::ENCODEKEY128, + 1632 => Opcode::ENCODEKEY256, + 1633 => Opcode::ENDBR32, + 1634 => Opcode::ENDBR64, + 1635 => Opcode::ENQCMD16, + 1636 => Opcode::ENQCMD32, + 1637 => Opcode::ENQCMD32_EVEX, + 1638 => Opcode::ENQCMD64, + 1639 => Opcode::ENQCMD64_EVEX, + 1640 => Opcode::ENQCMDS16, + 1641 => Opcode::ENQCMDS32, + 1642 => Opcode::ENQCMDS32_EVEX, + 1643 => Opcode::ENQCMDS64, + 1644 => Opcode::ENQCMDS64_EVEX, + 1645 => Opcode::ENTER, + 1646 => Opcode::ERETS, + 1647 => Opcode::ERETU, + 1648 => Opcode::ES_PREFIX, + 1649 => Opcode::EXTRACTPSmri, + 1650 => Opcode::EXTRACTPSrri, + 1651 => Opcode::EXTRQ, + 1652 => Opcode::EXTRQI, + 1653 => Opcode::F2XM1, + 1654 => Opcode::FARCALL16i, + 1655 => Opcode::FARCALL16m, + 1656 => Opcode::FARCALL32i, + 1657 => Opcode::FARCALL32m, + 1658 => Opcode::FARCALL64m, + 1659 => Opcode::FARJMP16i, + 1660 => Opcode::FARJMP16m, + 1661 => Opcode::FARJMP32i, + 1662 => Opcode::FARJMP32m, + 1663 => Opcode::FARJMP64m, + 1664 => Opcode::FBLDm, + 1665 => Opcode::FBSTPm, + 1666 => Opcode::FCOM32m, + 1667 => Opcode::FCOM64m, + 1668 => Opcode::FCOMP32m, + 1669 => Opcode::FCOMP64m, + 1670 => Opcode::FCOMPP, + 1671 => Opcode::FCOS, + 1672 => Opcode::FDECSTP, + 1673 => Opcode::FEMMS, + 1674 => Opcode::FFREE, + 1675 => Opcode::FFREEP, + 1676 => Opcode::FICOM16m, + 1677 => Opcode::FICOM32m, + 1678 => Opcode::FICOMP16m, + 1679 => Opcode::FICOMP32m, + 1680 => Opcode::FINCSTP, + 1681 => Opcode::FLDCW16m, + 1682 => Opcode::FLDENVm, + 1683 => Opcode::FLDL2E, + 1684 => Opcode::FLDL2T, + 1685 => Opcode::FLDLG2, + 1686 => Opcode::FLDLN2, + 1687 => Opcode::FLDPI, + 1688 => Opcode::FNCLEX, + 1689 => Opcode::FNINIT, + 1690 => Opcode::FNOP, + 1691 => Opcode::FNSTCW16m, + 1692 => Opcode::FNSTSW16r, + 1693 => Opcode::FNSTSWm, + 1694 => Opcode::FP32_TO_INT16_IN_MEM, + 1695 => Opcode::FP32_TO_INT32_IN_MEM, + 1696 => Opcode::FP32_TO_INT64_IN_MEM, + 1697 => Opcode::FP64_TO_INT16_IN_MEM, + 1698 => Opcode::FP64_TO_INT32_IN_MEM, + 1699 => Opcode::FP64_TO_INT64_IN_MEM, + 1700 => Opcode::FP80_ADDm32, + 1701 => Opcode::FP80_ADDr, + 1702 => Opcode::FP80_TO_INT16_IN_MEM, + 1703 => Opcode::FP80_TO_INT32_IN_MEM, + 1704 => Opcode::FP80_TO_INT64_IN_MEM, + 1705 => Opcode::FPATAN, + 1706 => Opcode::FPREM, + 1707 => Opcode::FPREM1, + 1708 => Opcode::FPTAN, + 1709 => Opcode::FRNDINT, + 1710 => Opcode::FRSTORm, + 1711 => Opcode::FSAVEm, + 1712 => Opcode::FSCALE_, + 1713 => Opcode::FSIN, + 1714 => Opcode::FSINCOS, + 1715 => Opcode::FSTENVm, + 1716 => Opcode::FS_PREFIX, + 1717 => Opcode::FXRSTOR, + 1718 => Opcode::FXRSTOR64, + 1719 => Opcode::FXSAVE, + 1720 => Opcode::FXSAVE64, + 1721 => Opcode::FXTRACT, + 1722 => Opcode::FYL2X, + 1723 => Opcode::FYL2XP1, + 1724 => Opcode::GETSEC, + 1725 => Opcode::GF2P8AFFINEINVQBrmi, + 1726 => Opcode::GF2P8AFFINEINVQBrri, + 1727 => Opcode::GF2P8AFFINEQBrmi, + 1728 => Opcode::GF2P8AFFINEQBrri, + 1729 => Opcode::GF2P8MULBrm, + 1730 => Opcode::GF2P8MULBrr, + 1731 => Opcode::GS_PREFIX, + 1732 => Opcode::HADDPDrm, + 1733 => Opcode::HADDPDrr, + 1734 => Opcode::HADDPSrm, + 1735 => Opcode::HADDPSrr, + 1736 => Opcode::HLT, + 1737 => Opcode::HRESET, + 1738 => Opcode::HSUBPDrm, + 1739 => Opcode::HSUBPDrr, + 1740 => Opcode::HSUBPSrm, + 1741 => Opcode::HSUBPSrr, + 1742 => Opcode::IDIV16m, + 1743 => Opcode::IDIV16m_EVEX, + 1744 => Opcode::IDIV16m_NF, + 1745 => Opcode::IDIV16r, + 1746 => Opcode::IDIV16r_EVEX, + 1747 => Opcode::IDIV16r_NF, + 1748 => Opcode::IDIV32m, + 1749 => Opcode::IDIV32m_EVEX, + 1750 => Opcode::IDIV32m_NF, + 1751 => Opcode::IDIV32r, + 1752 => Opcode::IDIV32r_EVEX, + 1753 => Opcode::IDIV32r_NF, + 1754 => Opcode::IDIV64m, + 1755 => Opcode::IDIV64m_EVEX, + 1756 => Opcode::IDIV64m_NF, + 1757 => Opcode::IDIV64r, + 1758 => Opcode::IDIV64r_EVEX, + 1759 => Opcode::IDIV64r_NF, + 1760 => Opcode::IDIV8m, + 1761 => Opcode::IDIV8m_EVEX, + 1762 => Opcode::IDIV8m_NF, + 1763 => Opcode::IDIV8r, + 1764 => Opcode::IDIV8r_EVEX, + 1765 => Opcode::IDIV8r_NF, + 1766 => Opcode::ILD_F16m, + 1767 => Opcode::ILD_F32m, + 1768 => Opcode::ILD_F64m, + 1769 => Opcode::ILD_Fp16m32, + 1770 => Opcode::ILD_Fp16m64, + 1771 => Opcode::ILD_Fp16m80, + 1772 => Opcode::ILD_Fp32m32, + 1773 => Opcode::ILD_Fp32m64, + 1774 => Opcode::ILD_Fp32m80, + 1775 => Opcode::ILD_Fp64m32, + 1776 => Opcode::ILD_Fp64m64, + 1777 => Opcode::ILD_Fp64m80, + 1778 => Opcode::IMUL16m, + 1779 => Opcode::IMUL16m_EVEX, + 1780 => Opcode::IMUL16m_NF, + 1781 => Opcode::IMUL16r, + 1782 => Opcode::IMUL16r_EVEX, + 1783 => Opcode::IMUL16r_NF, + 1784 => Opcode::IMUL16rm, + 1785 => Opcode::IMUL16rm_EVEX, + 1786 => Opcode::IMUL16rm_ND, + 1787 => Opcode::IMUL16rm_NF, + 1788 => Opcode::IMUL16rm_NF_ND, + 1789 => Opcode::IMUL16rmi, + 1790 => Opcode::IMUL16rmi8, + 1791 => Opcode::IMUL16rmi8_EVEX, + 1792 => Opcode::IMUL16rmi8_NF, + 1793 => Opcode::IMUL16rmi_EVEX, + 1794 => Opcode::IMUL16rmi_NF, + 1795 => Opcode::IMUL16rr, + 1796 => Opcode::IMUL16rr_EVEX, + 1797 => Opcode::IMUL16rr_ND, + 1798 => Opcode::IMUL16rr_NF, + 1799 => Opcode::IMUL16rr_NF_ND, + 1800 => Opcode::IMUL16rri, + 1801 => Opcode::IMUL16rri8, + 1802 => Opcode::IMUL16rri8_EVEX, + 1803 => Opcode::IMUL16rri8_NF, + 1804 => Opcode::IMUL16rri_EVEX, + 1805 => Opcode::IMUL16rri_NF, + 1806 => Opcode::IMUL32m, + 1807 => Opcode::IMUL32m_EVEX, + 1808 => Opcode::IMUL32m_NF, + 1809 => Opcode::IMUL32r, + 1810 => Opcode::IMUL32r_EVEX, + 1811 => Opcode::IMUL32r_NF, + 1812 => Opcode::IMUL32rm, + 1813 => Opcode::IMUL32rm_EVEX, + 1814 => Opcode::IMUL32rm_ND, + 1815 => Opcode::IMUL32rm_NF, + 1816 => Opcode::IMUL32rm_NF_ND, + 1817 => Opcode::IMUL32rmi, + 1818 => Opcode::IMUL32rmi8, + 1819 => Opcode::IMUL32rmi8_EVEX, + 1820 => Opcode::IMUL32rmi8_NF, + 1821 => Opcode::IMUL32rmi_EVEX, + 1822 => Opcode::IMUL32rmi_NF, + 1823 => Opcode::IMUL32rr, + 1824 => Opcode::IMUL32rr_EVEX, + 1825 => Opcode::IMUL32rr_ND, + 1826 => Opcode::IMUL32rr_NF, + 1827 => Opcode::IMUL32rr_NF_ND, + 1828 => Opcode::IMUL32rri, + 1829 => Opcode::IMUL32rri8, + 1830 => Opcode::IMUL32rri8_EVEX, + 1831 => Opcode::IMUL32rri8_NF, + 1832 => Opcode::IMUL32rri_EVEX, + 1833 => Opcode::IMUL32rri_NF, + 1834 => Opcode::IMUL64m, + 1835 => Opcode::IMUL64m_EVEX, + 1836 => Opcode::IMUL64m_NF, + 1837 => Opcode::IMUL64r, + 1838 => Opcode::IMUL64r_EVEX, + 1839 => Opcode::IMUL64r_NF, + 1840 => Opcode::IMUL64rm, + 1841 => Opcode::IMUL64rm_EVEX, + 1842 => Opcode::IMUL64rm_ND, + 1843 => Opcode::IMUL64rm_NF, + 1844 => Opcode::IMUL64rm_NF_ND, + 1845 => Opcode::IMUL64rmi32, + 1846 => Opcode::IMUL64rmi32_EVEX, + 1847 => Opcode::IMUL64rmi32_NF, + 1848 => Opcode::IMUL64rmi8, + 1849 => Opcode::IMUL64rmi8_EVEX, + 1850 => Opcode::IMUL64rmi8_NF, + 1851 => Opcode::IMUL64rr, + 1852 => Opcode::IMUL64rr_EVEX, + 1853 => Opcode::IMUL64rr_ND, + 1854 => Opcode::IMUL64rr_NF, + 1855 => Opcode::IMUL64rr_NF_ND, + 1856 => Opcode::IMUL64rri32, + 1857 => Opcode::IMUL64rri32_EVEX, + 1858 => Opcode::IMUL64rri32_NF, + 1859 => Opcode::IMUL64rri8, + 1860 => Opcode::IMUL64rri8_EVEX, + 1861 => Opcode::IMUL64rri8_NF, + 1862 => Opcode::IMUL8m, + 1863 => Opcode::IMUL8m_EVEX, + 1864 => Opcode::IMUL8m_NF, + 1865 => Opcode::IMUL8r, + 1866 => Opcode::IMUL8r_EVEX, + 1867 => Opcode::IMUL8r_NF, + 1868 => Opcode::IMULZU16rmi, + 1869 => Opcode::IMULZU16rmi8, + 1870 => Opcode::IMULZU16rri, + 1871 => Opcode::IMULZU16rri8, + 1872 => Opcode::IMULZU32rmi, + 1873 => Opcode::IMULZU32rmi8, + 1874 => Opcode::IMULZU32rri, + 1875 => Opcode::IMULZU32rri8, + 1876 => Opcode::IMULZU64rmi32, + 1877 => Opcode::IMULZU64rmi8, + 1878 => Opcode::IMULZU64rri32, + 1879 => Opcode::IMULZU64rri8, + 1880 => Opcode::IN16ri, + 1881 => Opcode::IN16rr, + 1882 => Opcode::IN32ri, + 1883 => Opcode::IN32rr, + 1884 => Opcode::IN8ri, + 1885 => Opcode::IN8rr, + 1886 => Opcode::INC16m, + 1887 => Opcode::INC16m_EVEX, + 1888 => Opcode::INC16m_ND, + 1889 => Opcode::INC16m_NF, + 1890 => Opcode::INC16m_NF_ND, + 1891 => Opcode::INC16r, + 1892 => Opcode::INC16r_EVEX, + 1893 => Opcode::INC16r_ND, + 1894 => Opcode::INC16r_NF, + 1895 => Opcode::INC16r_NF_ND, + 1896 => Opcode::INC16r_alt, + 1897 => Opcode::INC32m, + 1898 => Opcode::INC32m_EVEX, + 1899 => Opcode::INC32m_ND, + 1900 => Opcode::INC32m_NF, + 1901 => Opcode::INC32m_NF_ND, + 1902 => Opcode::INC32r, + 1903 => Opcode::INC32r_EVEX, + 1904 => Opcode::INC32r_ND, + 1905 => Opcode::INC32r_NF, + 1906 => Opcode::INC32r_NF_ND, + 1907 => Opcode::INC32r_alt, + 1908 => Opcode::INC64m, + 1909 => Opcode::INC64m_EVEX, + 1910 => Opcode::INC64m_ND, + 1911 => Opcode::INC64m_NF, + 1912 => Opcode::INC64m_NF_ND, + 1913 => Opcode::INC64r, + 1914 => Opcode::INC64r_EVEX, + 1915 => Opcode::INC64r_ND, + 1916 => Opcode::INC64r_NF, + 1917 => Opcode::INC64r_NF_ND, + 1918 => Opcode::INC8m, + 1919 => Opcode::INC8m_EVEX, + 1920 => Opcode::INC8m_ND, + 1921 => Opcode::INC8m_NF, + 1922 => Opcode::INC8m_NF_ND, + 1923 => Opcode::INC8r, + 1924 => Opcode::INC8r_EVEX, + 1925 => Opcode::INC8r_ND, + 1926 => Opcode::INC8r_NF, + 1927 => Opcode::INC8r_NF_ND, + 1928 => Opcode::INCSSPD, + 1929 => Opcode::INCSSPQ, + 1930 => Opcode::INSB, + 1931 => Opcode::INSERTPSrmi, + 1932 => Opcode::INSERTPSrri, + 1933 => Opcode::INSERTQ, + 1934 => Opcode::INSERTQI, + 1935 => Opcode::INSL, + 1936 => Opcode::INSW, + 1937 => Opcode::INT, + 1938 => Opcode::INT3, + 1939 => Opcode::INTO, + 1940 => Opcode::INVD, + 1941 => Opcode::INVEPT32, + 1942 => Opcode::INVEPT64, + 1943 => Opcode::INVEPT64_EVEX, + 1944 => Opcode::INVLPG, + 1945 => Opcode::INVLPGA32, + 1946 => Opcode::INVLPGA64, + 1947 => Opcode::INVLPGB32, + 1948 => Opcode::INVLPGB64, + 1949 => Opcode::INVPCID32, + 1950 => Opcode::INVPCID64, + 1951 => Opcode::INVPCID64_EVEX, + 1952 => Opcode::INVVPID32, + 1953 => Opcode::INVVPID64, + 1954 => Opcode::INVVPID64_EVEX, + 1955 => Opcode::IRET, + 1956 => Opcode::IRET16, + 1957 => Opcode::IRET32, + 1958 => Opcode::IRET64, + 1959 => Opcode::ISTT_FP16m, + 1960 => Opcode::ISTT_FP32m, + 1961 => Opcode::ISTT_FP64m, + 1962 => Opcode::ISTT_Fp16m32, + 1963 => Opcode::ISTT_Fp16m64, + 1964 => Opcode::ISTT_Fp16m80, + 1965 => Opcode::ISTT_Fp32m32, + 1966 => Opcode::ISTT_Fp32m64, + 1967 => Opcode::ISTT_Fp32m80, + 1968 => Opcode::ISTT_Fp64m32, + 1969 => Opcode::ISTT_Fp64m64, + 1970 => Opcode::ISTT_Fp64m80, + 1971 => Opcode::IST_F16m, + 1972 => Opcode::IST_F32m, + 1973 => Opcode::IST_FP16m, + 1974 => Opcode::IST_FP32m, + 1975 => Opcode::IST_FP64m, + 1976 => Opcode::IST_Fp16m32, + 1977 => Opcode::IST_Fp16m64, + 1978 => Opcode::IST_Fp16m80, + 1979 => Opcode::IST_Fp32m32, + 1980 => Opcode::IST_Fp32m64, + 1981 => Opcode::IST_Fp32m80, + 1982 => Opcode::IST_Fp64m32, + 1983 => Opcode::IST_Fp64m64, + 1984 => Opcode::IST_Fp64m80, + 1985 => Opcode::Int_eh_sjlj_setup_dispatch, + 1986 => Opcode::JCC_1, + 1987 => Opcode::JCC_2, + 1988 => Opcode::JCC_4, + 1989 => Opcode::JCXZ, + 1990 => Opcode::JECXZ, + 1991 => Opcode::JMP16m, + 1992 => Opcode::JMP16m_NT, + 1993 => Opcode::JMP16r, + 1994 => Opcode::JMP16r_NT, + 1995 => Opcode::JMP32m, + 1996 => Opcode::JMP32m_NT, + 1997 => Opcode::JMP32r, + 1998 => Opcode::JMP32r_NT, + 1999 => Opcode::JMP64m, + 2000 => Opcode::JMP64m_NT, + 2001 => Opcode::JMP64m_REX, + 2002 => Opcode::JMP64r, + 2003 => Opcode::JMP64r_NT, + 2004 => Opcode::JMP64r_REX, + 2005 => Opcode::JMPABS64i, + 2006 => Opcode::JMP_1, + 2007 => Opcode::JMP_2, + 2008 => Opcode::JMP_4, + 2009 => Opcode::JRCXZ, + 2010 => Opcode::KADDBkk, + 2011 => Opcode::KADDDkk, + 2012 => Opcode::KADDQkk, + 2013 => Opcode::KADDWkk, + 2014 => Opcode::KANDBkk, + 2015 => Opcode::KANDDkk, + 2016 => Opcode::KANDNBkk, + 2017 => Opcode::KANDNDkk, + 2018 => Opcode::KANDNQkk, + 2019 => Opcode::KANDNWkk, + 2020 => Opcode::KANDQkk, + 2021 => Opcode::KANDWkk, + 2022 => Opcode::KCFI_CHECK, + 2023 => Opcode::KMOVBkk, + 2024 => Opcode::KMOVBkk_EVEX, + 2025 => Opcode::KMOVBkm, + 2026 => Opcode::KMOVBkm_EVEX, + 2027 => Opcode::KMOVBkr, + 2028 => Opcode::KMOVBkr_EVEX, + 2029 => Opcode::KMOVBmk, + 2030 => Opcode::KMOVBmk_EVEX, + 2031 => Opcode::KMOVBrk, + 2032 => Opcode::KMOVBrk_EVEX, + 2033 => Opcode::KMOVDkk, + 2034 => Opcode::KMOVDkk_EVEX, + 2035 => Opcode::KMOVDkm, + 2036 => Opcode::KMOVDkm_EVEX, + 2037 => Opcode::KMOVDkr, + 2038 => Opcode::KMOVDkr_EVEX, + 2039 => Opcode::KMOVDmk, + 2040 => Opcode::KMOVDmk_EVEX, + 2041 => Opcode::KMOVDrk, + 2042 => Opcode::KMOVDrk_EVEX, + 2043 => Opcode::KMOVQkk, + 2044 => Opcode::KMOVQkk_EVEX, + 2045 => Opcode::KMOVQkm, + 2046 => Opcode::KMOVQkm_EVEX, + 2047 => Opcode::KMOVQkr, + 2048 => Opcode::KMOVQkr_EVEX, + 2049 => Opcode::KMOVQmk, + 2050 => Opcode::KMOVQmk_EVEX, + 2051 => Opcode::KMOVQrk, + 2052 => Opcode::KMOVQrk_EVEX, + 2053 => Opcode::KMOVWkk, + 2054 => Opcode::KMOVWkk_EVEX, + 2055 => Opcode::KMOVWkm, + 2056 => Opcode::KMOVWkm_EVEX, + 2057 => Opcode::KMOVWkr, + 2058 => Opcode::KMOVWkr_EVEX, + 2059 => Opcode::KMOVWmk, + 2060 => Opcode::KMOVWmk_EVEX, + 2061 => Opcode::KMOVWrk, + 2062 => Opcode::KMOVWrk_EVEX, + 2063 => Opcode::KNOTBkk, + 2064 => Opcode::KNOTDkk, + 2065 => Opcode::KNOTQkk, + 2066 => Opcode::KNOTWkk, + 2067 => Opcode::KORBkk, + 2068 => Opcode::KORDkk, + 2069 => Opcode::KORQkk, + 2070 => Opcode::KORTESTBkk, + 2071 => Opcode::KORTESTDkk, + 2072 => Opcode::KORTESTQkk, + 2073 => Opcode::KORTESTWkk, + 2074 => Opcode::KORWkk, + 2075 => Opcode::KSHIFTLBki, + 2076 => Opcode::KSHIFTLDki, + 2077 => Opcode::KSHIFTLQki, + 2078 => Opcode::KSHIFTLWki, + 2079 => Opcode::KSHIFTRBki, + 2080 => Opcode::KSHIFTRDki, + 2081 => Opcode::KSHIFTRQki, + 2082 => Opcode::KSHIFTRWki, + 2083 => Opcode::KTESTBkk, + 2084 => Opcode::KTESTDkk, + 2085 => Opcode::KTESTQkk, + 2086 => Opcode::KTESTWkk, + 2087 => Opcode::KUNPCKBWkk, + 2088 => Opcode::KUNPCKDQkk, + 2089 => Opcode::KUNPCKWDkk, + 2090 => Opcode::KXNORBkk, + 2091 => Opcode::KXNORDkk, + 2092 => Opcode::KXNORQkk, + 2093 => Opcode::KXNORWkk, + 2094 => Opcode::KXORBkk, + 2095 => Opcode::KXORDkk, + 2096 => Opcode::KXORQkk, + 2097 => Opcode::KXORWkk, + 2098 => Opcode::LAHF, + 2099 => Opcode::LAR16rm, + 2100 => Opcode::LAR16rr, + 2101 => Opcode::LAR32rm, + 2102 => Opcode::LAR32rr, + 2103 => Opcode::LAR64rm, + 2104 => Opcode::LAR64rr, + 2105 => Opcode::LCMPXCHG16, + 2106 => Opcode::LCMPXCHG16B, + 2107 => Opcode::LCMPXCHG32, + 2108 => Opcode::LCMPXCHG64, + 2109 => Opcode::LCMPXCHG8, + 2110 => Opcode::LCMPXCHG8B, + 2111 => Opcode::LDDQUrm, + 2112 => Opcode::LDMXCSR, + 2113 => Opcode::LDS16rm, + 2114 => Opcode::LDS32rm, + 2115 => Opcode::LDTILECFG, + 2116 => Opcode::LDTILECFG_EVEX, + 2117 => Opcode::LD_F0, + 2118 => Opcode::LD_F1, + 2119 => Opcode::LD_F32m, + 2120 => Opcode::LD_F64m, + 2121 => Opcode::LD_F80m, + 2122 => Opcode::LD_Fp032, + 2123 => Opcode::LD_Fp064, + 2124 => Opcode::LD_Fp080, + 2125 => Opcode::LD_Fp132, + 2126 => Opcode::LD_Fp164, + 2127 => Opcode::LD_Fp180, + 2128 => Opcode::LD_Fp32m, + 2129 => Opcode::LD_Fp32m64, + 2130 => Opcode::LD_Fp32m80, + 2131 => Opcode::LD_Fp64m, + 2132 => Opcode::LD_Fp64m80, + 2133 => Opcode::LD_Fp80m, + 2134 => Opcode::LD_Frr, + 2135 => Opcode::LEA16r, + 2136 => Opcode::LEA32r, + 2137 => Opcode::LEA64_16r, + 2138 => Opcode::LEA64_32r, + 2139 => Opcode::LEA64_8r, + 2140 => Opcode::LEA64r, + 2141 => Opcode::LEAVE, + 2142 => Opcode::LEAVE64, + 2143 => Opcode::LES16rm, + 2144 => Opcode::LES32rm, + 2145 => Opcode::LFENCE, + 2146 => Opcode::LFS16rm, + 2147 => Opcode::LFS32rm, + 2148 => Opcode::LFS64rm, + 2149 => Opcode::LGDT16m, + 2150 => Opcode::LGDT32m, + 2151 => Opcode::LGDT64m, + 2152 => Opcode::LGS16rm, + 2153 => Opcode::LGS32rm, + 2154 => Opcode::LGS64rm, + 2155 => Opcode::LIDT16m, + 2156 => Opcode::LIDT32m, + 2157 => Opcode::LIDT64m, + 2158 => Opcode::LKGS16m, + 2159 => Opcode::LKGS16r, + 2160 => Opcode::LLDT16m, + 2161 => Opcode::LLDT16r, + 2162 => Opcode::LLWPCB, + 2163 => Opcode::LLWPCB64, + 2164 => Opcode::LMSW16m, + 2165 => Opcode::LMSW16r, + 2166 => Opcode::LOADIWKEY, + 2167 => Opcode::LOCK_ADD16mi, + 2168 => Opcode::LOCK_ADD16mi8, + 2169 => Opcode::LOCK_ADD16mr, + 2170 => Opcode::LOCK_ADD32mi, + 2171 => Opcode::LOCK_ADD32mi8, + 2172 => Opcode::LOCK_ADD32mr, + 2173 => Opcode::LOCK_ADD64mi32, + 2174 => Opcode::LOCK_ADD64mi8, + 2175 => Opcode::LOCK_ADD64mr, + 2176 => Opcode::LOCK_ADD8mi, + 2177 => Opcode::LOCK_ADD8mr, + 2178 => Opcode::LOCK_AND16mi, + 2179 => Opcode::LOCK_AND16mi8, + 2180 => Opcode::LOCK_AND16mr, + 2181 => Opcode::LOCK_AND32mi, + 2182 => Opcode::LOCK_AND32mi8, + 2183 => Opcode::LOCK_AND32mr, + 2184 => Opcode::LOCK_AND64mi32, + 2185 => Opcode::LOCK_AND64mi8, + 2186 => Opcode::LOCK_AND64mr, + 2187 => Opcode::LOCK_AND8mi, + 2188 => Opcode::LOCK_AND8mr, + 2189 => Opcode::LOCK_BTC16m, + 2190 => Opcode::LOCK_BTC32m, + 2191 => Opcode::LOCK_BTC64m, + 2192 => Opcode::LOCK_BTC_RM16rm, + 2193 => Opcode::LOCK_BTC_RM32rm, + 2194 => Opcode::LOCK_BTC_RM64rm, + 2195 => Opcode::LOCK_BTR16m, + 2196 => Opcode::LOCK_BTR32m, + 2197 => Opcode::LOCK_BTR64m, + 2198 => Opcode::LOCK_BTR_RM16rm, + 2199 => Opcode::LOCK_BTR_RM32rm, + 2200 => Opcode::LOCK_BTR_RM64rm, + 2201 => Opcode::LOCK_BTS16m, + 2202 => Opcode::LOCK_BTS32m, + 2203 => Opcode::LOCK_BTS64m, + 2204 => Opcode::LOCK_BTS_RM16rm, + 2205 => Opcode::LOCK_BTS_RM32rm, + 2206 => Opcode::LOCK_BTS_RM64rm, + 2207 => Opcode::LOCK_DEC16m, + 2208 => Opcode::LOCK_DEC32m, + 2209 => Opcode::LOCK_DEC64m, + 2210 => Opcode::LOCK_DEC8m, + 2211 => Opcode::LOCK_INC16m, + 2212 => Opcode::LOCK_INC32m, + 2213 => Opcode::LOCK_INC64m, + 2214 => Opcode::LOCK_INC8m, + 2215 => Opcode::LOCK_OR16mi, + 2216 => Opcode::LOCK_OR16mi8, + 2217 => Opcode::LOCK_OR16mr, + 2218 => Opcode::LOCK_OR32mi, + 2219 => Opcode::LOCK_OR32mi8, + 2220 => Opcode::LOCK_OR32mr, + 2221 => Opcode::LOCK_OR64mi32, + 2222 => Opcode::LOCK_OR64mi8, + 2223 => Opcode::LOCK_OR64mr, + 2224 => Opcode::LOCK_OR8mi, + 2225 => Opcode::LOCK_OR8mr, + 2226 => Opcode::LOCK_PREFIX, + 2227 => Opcode::LOCK_SUB16mi, + 2228 => Opcode::LOCK_SUB16mi8, + 2229 => Opcode::LOCK_SUB16mr, + 2230 => Opcode::LOCK_SUB32mi, + 2231 => Opcode::LOCK_SUB32mi8, + 2232 => Opcode::LOCK_SUB32mr, + 2233 => Opcode::LOCK_SUB64mi32, + 2234 => Opcode::LOCK_SUB64mi8, + 2235 => Opcode::LOCK_SUB64mr, + 2236 => Opcode::LOCK_SUB8mi, + 2237 => Opcode::LOCK_SUB8mr, + 2238 => Opcode::LOCK_XOR16mi, + 2239 => Opcode::LOCK_XOR16mi8, + 2240 => Opcode::LOCK_XOR16mr, + 2241 => Opcode::LOCK_XOR32mi, + 2242 => Opcode::LOCK_XOR32mi8, + 2243 => Opcode::LOCK_XOR32mr, + 2244 => Opcode::LOCK_XOR64mi32, + 2245 => Opcode::LOCK_XOR64mi8, + 2246 => Opcode::LOCK_XOR64mr, + 2247 => Opcode::LOCK_XOR8mi, + 2248 => Opcode::LOCK_XOR8mr, + 2249 => Opcode::LODSB, + 2250 => Opcode::LODSL, + 2251 => Opcode::LODSQ, + 2252 => Opcode::LODSW, + 2253 => Opcode::LOOP, + 2254 => Opcode::LOOPE, + 2255 => Opcode::LOOPNE, + 2256 => Opcode::LRET16, + 2257 => Opcode::LRET32, + 2258 => Opcode::LRET64, + 2259 => Opcode::LRETI16, + 2260 => Opcode::LRETI32, + 2261 => Opcode::LRETI64, + 2262 => Opcode::LSL16rm, + 2263 => Opcode::LSL16rr, + 2264 => Opcode::LSL32rm, + 2265 => Opcode::LSL32rr, + 2266 => Opcode::LSL64rm, + 2267 => Opcode::LSL64rr, + 2268 => Opcode::LSS16rm, + 2269 => Opcode::LSS32rm, + 2270 => Opcode::LSS64rm, + 2271 => Opcode::LTRm, + 2272 => Opcode::LTRr, + 2273 => Opcode::LWPINS32rmi, + 2274 => Opcode::LWPINS32rri, + 2275 => Opcode::LWPINS64rmi, + 2276 => Opcode::LWPINS64rri, + 2277 => Opcode::LWPVAL32rmi, + 2278 => Opcode::LWPVAL32rri, + 2279 => Opcode::LWPVAL64rmi, + 2280 => Opcode::LWPVAL64rri, + 2281 => Opcode::LXADD16, + 2282 => Opcode::LXADD32, + 2283 => Opcode::LXADD64, + 2284 => Opcode::LXADD8, + 2285 => Opcode::LZCNT16rm, + 2286 => Opcode::LZCNT16rm_EVEX, + 2287 => Opcode::LZCNT16rm_NF, + 2288 => Opcode::LZCNT16rr, + 2289 => Opcode::LZCNT16rr_EVEX, + 2290 => Opcode::LZCNT16rr_NF, + 2291 => Opcode::LZCNT32rm, + 2292 => Opcode::LZCNT32rm_EVEX, + 2293 => Opcode::LZCNT32rm_NF, + 2294 => Opcode::LZCNT32rr, + 2295 => Opcode::LZCNT32rr_EVEX, + 2296 => Opcode::LZCNT32rr_NF, + 2297 => Opcode::LZCNT64rm, + 2298 => Opcode::LZCNT64rm_EVEX, + 2299 => Opcode::LZCNT64rm_NF, + 2300 => Opcode::LZCNT64rr, + 2301 => Opcode::LZCNT64rr_EVEX, + 2302 => Opcode::LZCNT64rr_NF, + 2303 => Opcode::MASKMOVDQU, + 2304 => Opcode::MASKMOVDQU64, + 2305 => Opcode::MASKPAIR16LOAD, + 2306 => Opcode::MASKPAIR16STORE, + 2307 => Opcode::MAXCPDrm, + 2308 => Opcode::MAXCPDrr, + 2309 => Opcode::MAXCPSrm, + 2310 => Opcode::MAXCPSrr, + 2311 => Opcode::MAXCSDrm, + 2312 => Opcode::MAXCSDrr, + 2313 => Opcode::MAXCSSrm, + 2314 => Opcode::MAXCSSrr, + 2315 => Opcode::MAXPDrm, + 2316 => Opcode::MAXPDrr, + 2317 => Opcode::MAXPSrm, + 2318 => Opcode::MAXPSrr, + 2319 => Opcode::MAXSDrm, + 2320 => Opcode::MAXSDrm_Int, + 2321 => Opcode::MAXSDrr, + 2322 => Opcode::MAXSDrr_Int, + 2323 => Opcode::MAXSSrm, + 2324 => Opcode::MAXSSrm_Int, + 2325 => Opcode::MAXSSrr, + 2326 => Opcode::MAXSSrr_Int, + 2327 => Opcode::MFENCE, + 2328 => Opcode::MINCPDrm, + 2329 => Opcode::MINCPDrr, + 2330 => Opcode::MINCPSrm, + 2331 => Opcode::MINCPSrr, + 2332 => Opcode::MINCSDrm, + 2333 => Opcode::MINCSDrr, + 2334 => Opcode::MINCSSrm, + 2335 => Opcode::MINCSSrr, + 2336 => Opcode::MINPDrm, + 2337 => Opcode::MINPDrr, + 2338 => Opcode::MINPSrm, + 2339 => Opcode::MINPSrr, + 2340 => Opcode::MINSDrm, + 2341 => Opcode::MINSDrm_Int, + 2342 => Opcode::MINSDrr, + 2343 => Opcode::MINSDrr_Int, + 2344 => Opcode::MINSSrm, + 2345 => Opcode::MINSSrm_Int, + 2346 => Opcode::MINSSrr, + 2347 => Opcode::MINSSrr_Int, + 2348 => Opcode::MMX_CVTPD2PIrm, + 2349 => Opcode::MMX_CVTPD2PIrr, + 2350 => Opcode::MMX_CVTPI2PDrm, + 2351 => Opcode::MMX_CVTPI2PDrr, + 2352 => Opcode::MMX_CVTPI2PSrm, + 2353 => Opcode::MMX_CVTPI2PSrr, + 2354 => Opcode::MMX_CVTPS2PIrm, + 2355 => Opcode::MMX_CVTPS2PIrr, + 2356 => Opcode::MMX_CVTTPD2PIrm, + 2357 => Opcode::MMX_CVTTPD2PIrr, + 2358 => Opcode::MMX_CVTTPS2PIrm, + 2359 => Opcode::MMX_CVTTPS2PIrr, + 2360 => Opcode::MMX_EMMS, + 2361 => Opcode::MMX_MASKMOVQ, + 2362 => Opcode::MMX_MASKMOVQ64, + 2363 => Opcode::MMX_MOVD64from64mr, + 2364 => Opcode::MMX_MOVD64from64rr, + 2365 => Opcode::MMX_MOVD64grr, + 2366 => Opcode::MMX_MOVD64mr, + 2367 => Opcode::MMX_MOVD64rm, + 2368 => Opcode::MMX_MOVD64rr, + 2369 => Opcode::MMX_MOVD64to64rm, + 2370 => Opcode::MMX_MOVD64to64rr, + 2371 => Opcode::MMX_MOVDQ2Qrr, + 2372 => Opcode::MMX_MOVFR642Qrr, + 2373 => Opcode::MMX_MOVNTQmr, + 2374 => Opcode::MMX_MOVQ2DQrr, + 2375 => Opcode::MMX_MOVQ2FR64rr, + 2376 => Opcode::MMX_MOVQ64mr, + 2377 => Opcode::MMX_MOVQ64rm, + 2378 => Opcode::MMX_MOVQ64rr, + 2379 => Opcode::MMX_MOVQ64rr_REV, + 2380 => Opcode::MMX_PABSBrm, + 2381 => Opcode::MMX_PABSBrr, + 2382 => Opcode::MMX_PABSDrm, + 2383 => Opcode::MMX_PABSDrr, + 2384 => Opcode::MMX_PABSWrm, + 2385 => Opcode::MMX_PABSWrr, + 2386 => Opcode::MMX_PACKSSDWrm, + 2387 => Opcode::MMX_PACKSSDWrr, + 2388 => Opcode::MMX_PACKSSWBrm, + 2389 => Opcode::MMX_PACKSSWBrr, + 2390 => Opcode::MMX_PACKUSWBrm, + 2391 => Opcode::MMX_PACKUSWBrr, + 2392 => Opcode::MMX_PADDBrm, + 2393 => Opcode::MMX_PADDBrr, + 2394 => Opcode::MMX_PADDDrm, + 2395 => Opcode::MMX_PADDDrr, + 2396 => Opcode::MMX_PADDQrm, + 2397 => Opcode::MMX_PADDQrr, + 2398 => Opcode::MMX_PADDSBrm, + 2399 => Opcode::MMX_PADDSBrr, + 2400 => Opcode::MMX_PADDSWrm, + 2401 => Opcode::MMX_PADDSWrr, + 2402 => Opcode::MMX_PADDUSBrm, + 2403 => Opcode::MMX_PADDUSBrr, + 2404 => Opcode::MMX_PADDUSWrm, + 2405 => Opcode::MMX_PADDUSWrr, + 2406 => Opcode::MMX_PADDWrm, + 2407 => Opcode::MMX_PADDWrr, + 2408 => Opcode::MMX_PALIGNRrmi, + 2409 => Opcode::MMX_PALIGNRrri, + 2410 => Opcode::MMX_PANDNrm, + 2411 => Opcode::MMX_PANDNrr, + 2412 => Opcode::MMX_PANDrm, + 2413 => Opcode::MMX_PANDrr, + 2414 => Opcode::MMX_PAVGBrm, + 2415 => Opcode::MMX_PAVGBrr, + 2416 => Opcode::MMX_PAVGWrm, + 2417 => Opcode::MMX_PAVGWrr, + 2418 => Opcode::MMX_PCMPEQBrm, + 2419 => Opcode::MMX_PCMPEQBrr, + 2420 => Opcode::MMX_PCMPEQDrm, + 2421 => Opcode::MMX_PCMPEQDrr, + 2422 => Opcode::MMX_PCMPEQWrm, + 2423 => Opcode::MMX_PCMPEQWrr, + 2424 => Opcode::MMX_PCMPGTBrm, + 2425 => Opcode::MMX_PCMPGTBrr, + 2426 => Opcode::MMX_PCMPGTDrm, + 2427 => Opcode::MMX_PCMPGTDrr, + 2428 => Opcode::MMX_PCMPGTWrm, + 2429 => Opcode::MMX_PCMPGTWrr, + 2430 => Opcode::MMX_PEXTRWrri, + 2431 => Opcode::MMX_PHADDDrm, + 2432 => Opcode::MMX_PHADDDrr, + 2433 => Opcode::MMX_PHADDSWrm, + 2434 => Opcode::MMX_PHADDSWrr, + 2435 => Opcode::MMX_PHADDWrm, + 2436 => Opcode::MMX_PHADDWrr, + 2437 => Opcode::MMX_PHSUBDrm, + 2438 => Opcode::MMX_PHSUBDrr, + 2439 => Opcode::MMX_PHSUBSWrm, + 2440 => Opcode::MMX_PHSUBSWrr, + 2441 => Opcode::MMX_PHSUBWrm, + 2442 => Opcode::MMX_PHSUBWrr, + 2443 => Opcode::MMX_PINSRWrmi, + 2444 => Opcode::MMX_PINSRWrri, + 2445 => Opcode::MMX_PMADDUBSWrm, + 2446 => Opcode::MMX_PMADDUBSWrr, + 2447 => Opcode::MMX_PMADDWDrm, + 2448 => Opcode::MMX_PMADDWDrr, + 2449 => Opcode::MMX_PMAXSWrm, + 2450 => Opcode::MMX_PMAXSWrr, + 2451 => Opcode::MMX_PMAXUBrm, + 2452 => Opcode::MMX_PMAXUBrr, + 2453 => Opcode::MMX_PMINSWrm, + 2454 => Opcode::MMX_PMINSWrr, + 2455 => Opcode::MMX_PMINUBrm, + 2456 => Opcode::MMX_PMINUBrr, + 2457 => Opcode::MMX_PMOVMSKBrr, + 2458 => Opcode::MMX_PMULHRSWrm, + 2459 => Opcode::MMX_PMULHRSWrr, + 2460 => Opcode::MMX_PMULHUWrm, + 2461 => Opcode::MMX_PMULHUWrr, + 2462 => Opcode::MMX_PMULHWrm, + 2463 => Opcode::MMX_PMULHWrr, + 2464 => Opcode::MMX_PMULLWrm, + 2465 => Opcode::MMX_PMULLWrr, + 2466 => Opcode::MMX_PMULUDQrm, + 2467 => Opcode::MMX_PMULUDQrr, + 2468 => Opcode::MMX_PORrm, + 2469 => Opcode::MMX_PORrr, + 2470 => Opcode::MMX_PSADBWrm, + 2471 => Opcode::MMX_PSADBWrr, + 2472 => Opcode::MMX_PSHUFBrm, + 2473 => Opcode::MMX_PSHUFBrr, + 2474 => Opcode::MMX_PSHUFWmi, + 2475 => Opcode::MMX_PSHUFWri, + 2476 => Opcode::MMX_PSIGNBrm, + 2477 => Opcode::MMX_PSIGNBrr, + 2478 => Opcode::MMX_PSIGNDrm, + 2479 => Opcode::MMX_PSIGNDrr, + 2480 => Opcode::MMX_PSIGNWrm, + 2481 => Opcode::MMX_PSIGNWrr, + 2482 => Opcode::MMX_PSLLDri, + 2483 => Opcode::MMX_PSLLDrm, + 2484 => Opcode::MMX_PSLLDrr, + 2485 => Opcode::MMX_PSLLQri, + 2486 => Opcode::MMX_PSLLQrm, + 2487 => Opcode::MMX_PSLLQrr, + 2488 => Opcode::MMX_PSLLWri, + 2489 => Opcode::MMX_PSLLWrm, + 2490 => Opcode::MMX_PSLLWrr, + 2491 => Opcode::MMX_PSRADri, + 2492 => Opcode::MMX_PSRADrm, + 2493 => Opcode::MMX_PSRADrr, + 2494 => Opcode::MMX_PSRAWri, + 2495 => Opcode::MMX_PSRAWrm, + 2496 => Opcode::MMX_PSRAWrr, + 2497 => Opcode::MMX_PSRLDri, + 2498 => Opcode::MMX_PSRLDrm, + 2499 => Opcode::MMX_PSRLDrr, + 2500 => Opcode::MMX_PSRLQri, + 2501 => Opcode::MMX_PSRLQrm, + 2502 => Opcode::MMX_PSRLQrr, + 2503 => Opcode::MMX_PSRLWri, + 2504 => Opcode::MMX_PSRLWrm, + 2505 => Opcode::MMX_PSRLWrr, + 2506 => Opcode::MMX_PSUBBrm, + 2507 => Opcode::MMX_PSUBBrr, + 2508 => Opcode::MMX_PSUBDrm, + 2509 => Opcode::MMX_PSUBDrr, + 2510 => Opcode::MMX_PSUBQrm, + 2511 => Opcode::MMX_PSUBQrr, + 2512 => Opcode::MMX_PSUBSBrm, + 2513 => Opcode::MMX_PSUBSBrr, + 2514 => Opcode::MMX_PSUBSWrm, + 2515 => Opcode::MMX_PSUBSWrr, + 2516 => Opcode::MMX_PSUBUSBrm, + 2517 => Opcode::MMX_PSUBUSBrr, + 2518 => Opcode::MMX_PSUBUSWrm, + 2519 => Opcode::MMX_PSUBUSWrr, + 2520 => Opcode::MMX_PSUBWrm, + 2521 => Opcode::MMX_PSUBWrr, + 2522 => Opcode::MMX_PUNPCKHBWrm, + 2523 => Opcode::MMX_PUNPCKHBWrr, + 2524 => Opcode::MMX_PUNPCKHDQrm, + 2525 => Opcode::MMX_PUNPCKHDQrr, + 2526 => Opcode::MMX_PUNPCKHWDrm, + 2527 => Opcode::MMX_PUNPCKHWDrr, + 2528 => Opcode::MMX_PUNPCKLBWrm, + 2529 => Opcode::MMX_PUNPCKLBWrr, + 2530 => Opcode::MMX_PUNPCKLDQrm, + 2531 => Opcode::MMX_PUNPCKLDQrr, + 2532 => Opcode::MMX_PUNPCKLWDrm, + 2533 => Opcode::MMX_PUNPCKLWDrr, + 2534 => Opcode::MMX_PXORrm, + 2535 => Opcode::MMX_PXORrr, + 2536 => Opcode::MONITOR32rrr, + 2537 => Opcode::MONITOR64rrr, + 2538 => Opcode::MONITORX32rrr, + 2539 => Opcode::MONITORX64rrr, + 2540 => Opcode::MONTMUL, + 2541 => Opcode::MOV16ao16, + 2542 => Opcode::MOV16ao32, + 2543 => Opcode::MOV16ao64, + 2544 => Opcode::MOV16mi, + 2545 => Opcode::MOV16mr, + 2546 => Opcode::MOV16ms, + 2547 => Opcode::MOV16o16a, + 2548 => Opcode::MOV16o32a, + 2549 => Opcode::MOV16o64a, + 2550 => Opcode::MOV16ri, + 2551 => Opcode::MOV16ri_alt, + 2552 => Opcode::MOV16rm, + 2553 => Opcode::MOV16rr, + 2554 => Opcode::MOV16rr_REV, + 2555 => Opcode::MOV16rs, + 2556 => Opcode::MOV16sm, + 2557 => Opcode::MOV16sr, + 2558 => Opcode::MOV32ao16, + 2559 => Opcode::MOV32ao32, + 2560 => Opcode::MOV32ao64, + 2561 => Opcode::MOV32cr, + 2562 => Opcode::MOV32dr, + 2563 => Opcode::MOV32mi, + 2564 => Opcode::MOV32mr, + 2565 => Opcode::MOV32o16a, + 2566 => Opcode::MOV32o32a, + 2567 => Opcode::MOV32o64a, + 2568 => Opcode::MOV32rc, + 2569 => Opcode::MOV32rd, + 2570 => Opcode::MOV32ri, + 2571 => Opcode::MOV32ri_alt, + 2572 => Opcode::MOV32rm, + 2573 => Opcode::MOV32rr, + 2574 => Opcode::MOV32rr_REV, + 2575 => Opcode::MOV32rs, + 2576 => Opcode::MOV32sr, + 2577 => Opcode::MOV64ao32, + 2578 => Opcode::MOV64ao64, + 2579 => Opcode::MOV64cr, + 2580 => Opcode::MOV64dr, + 2581 => Opcode::MOV64mi32, + 2582 => Opcode::MOV64mr, + 2583 => Opcode::MOV64o32a, + 2584 => Opcode::MOV64o64a, + 2585 => Opcode::MOV64rc, + 2586 => Opcode::MOV64rd, + 2587 => Opcode::MOV64ri, + 2588 => Opcode::MOV64ri32, + 2589 => Opcode::MOV64rm, + 2590 => Opcode::MOV64rr, + 2591 => Opcode::MOV64rr_REV, + 2592 => Opcode::MOV64rs, + 2593 => Opcode::MOV64sr, + 2594 => Opcode::MOV64toPQIrm, + 2595 => Opcode::MOV64toPQIrr, + 2596 => Opcode::MOV64toSDrr, + 2597 => Opcode::MOV8ao16, + 2598 => Opcode::MOV8ao32, + 2599 => Opcode::MOV8ao64, + 2600 => Opcode::MOV8mi, + 2601 => Opcode::MOV8mr, + 2602 => Opcode::MOV8mr_NOREX, + 2603 => Opcode::MOV8o16a, + 2604 => Opcode::MOV8o32a, + 2605 => Opcode::MOV8o64a, + 2606 => Opcode::MOV8ri, + 2607 => Opcode::MOV8ri_alt, + 2608 => Opcode::MOV8rm, + 2609 => Opcode::MOV8rm_NOREX, + 2610 => Opcode::MOV8rr, + 2611 => Opcode::MOV8rr_NOREX, + 2612 => Opcode::MOV8rr_REV, + 2613 => Opcode::MOVAPDmr, + 2614 => Opcode::MOVAPDrm, + 2615 => Opcode::MOVAPDrr, + 2616 => Opcode::MOVAPDrr_REV, + 2617 => Opcode::MOVAPSmr, + 2618 => Opcode::MOVAPSrm, + 2619 => Opcode::MOVAPSrr, + 2620 => Opcode::MOVAPSrr_REV, + 2621 => Opcode::MOVBE16mr, + 2622 => Opcode::MOVBE16mr_EVEX, + 2623 => Opcode::MOVBE16rm, + 2624 => Opcode::MOVBE16rm_EVEX, + 2625 => Opcode::MOVBE16rr, + 2626 => Opcode::MOVBE16rr_REV, + 2627 => Opcode::MOVBE32mr, + 2628 => Opcode::MOVBE32mr_EVEX, + 2629 => Opcode::MOVBE32rm, + 2630 => Opcode::MOVBE32rm_EVEX, + 2631 => Opcode::MOVBE32rr, + 2632 => Opcode::MOVBE32rr_REV, + 2633 => Opcode::MOVBE64mr, + 2634 => Opcode::MOVBE64mr_EVEX, + 2635 => Opcode::MOVBE64rm, + 2636 => Opcode::MOVBE64rm_EVEX, + 2637 => Opcode::MOVBE64rr, + 2638 => Opcode::MOVBE64rr_REV, + 2639 => Opcode::MOVDDUPrm, + 2640 => Opcode::MOVDDUPrr, + 2641 => Opcode::MOVDI2PDIrm, + 2642 => Opcode::MOVDI2PDIrr, + 2643 => Opcode::MOVDI2SSrr, + 2644 => Opcode::MOVDIR64B16, + 2645 => Opcode::MOVDIR64B32, + 2646 => Opcode::MOVDIR64B32_EVEX, + 2647 => Opcode::MOVDIR64B64, + 2648 => Opcode::MOVDIR64B64_EVEX, + 2649 => Opcode::MOVDIRI32, + 2650 => Opcode::MOVDIRI32_EVEX, + 2651 => Opcode::MOVDIRI64, + 2652 => Opcode::MOVDIRI64_EVEX, + 2653 => Opcode::MOVDQAmr, + 2654 => Opcode::MOVDQArm, + 2655 => Opcode::MOVDQArr, + 2656 => Opcode::MOVDQArr_REV, + 2657 => Opcode::MOVDQUmr, + 2658 => Opcode::MOVDQUrm, + 2659 => Opcode::MOVDQUrr, + 2660 => Opcode::MOVDQUrr_REV, + 2661 => Opcode::MOVHLPSrr, + 2662 => Opcode::MOVHPDmr, + 2663 => Opcode::MOVHPDrm, + 2664 => Opcode::MOVHPSmr, + 2665 => Opcode::MOVHPSrm, + 2666 => Opcode::MOVLHPSrr, + 2667 => Opcode::MOVLPDmr, + 2668 => Opcode::MOVLPDrm, + 2669 => Opcode::MOVLPSmr, + 2670 => Opcode::MOVLPSrm, + 2671 => Opcode::MOVMSKPDrr, + 2672 => Opcode::MOVMSKPSrr, + 2673 => Opcode::MOVNTDQArm, + 2674 => Opcode::MOVNTDQmr, + 2675 => Opcode::MOVNTI_64mr, + 2676 => Opcode::MOVNTImr, + 2677 => Opcode::MOVNTPDmr, + 2678 => Opcode::MOVNTPSmr, + 2679 => Opcode::MOVNTSD, + 2680 => Opcode::MOVNTSS, + 2681 => Opcode::MOVPC32r, + 2682 => Opcode::MOVPDI2DImr, + 2683 => Opcode::MOVPDI2DIrr, + 2684 => Opcode::MOVPQI2QImr, + 2685 => Opcode::MOVPQI2QIrr, + 2686 => Opcode::MOVPQIto64mr, + 2687 => Opcode::MOVPQIto64rr, + 2688 => Opcode::MOVQI2PQIrm, + 2689 => Opcode::MOVRS16rm, + 2690 => Opcode::MOVRS16rm_EVEX, + 2691 => Opcode::MOVRS32rm, + 2692 => Opcode::MOVRS32rm_EVEX, + 2693 => Opcode::MOVRS64rm, + 2694 => Opcode::MOVRS64rm_EVEX, + 2695 => Opcode::MOVRS8rm, + 2696 => Opcode::MOVRS8rm_EVEX, + 2697 => Opcode::MOVSB, + 2698 => Opcode::MOVSDmr, + 2699 => Opcode::MOVSDrm, + 2700 => Opcode::MOVSDrm_alt, + 2701 => Opcode::MOVSDrr, + 2702 => Opcode::MOVSDrr_REV, + 2703 => Opcode::MOVSDto64rr, + 2704 => Opcode::MOVSHDUPrm, + 2705 => Opcode::MOVSHDUPrr, + 2706 => Opcode::MOVSL, + 2707 => Opcode::MOVSLDUPrm, + 2708 => Opcode::MOVSLDUPrr, + 2709 => Opcode::MOVSQ, + 2710 => Opcode::MOVSS2DIrr, + 2711 => Opcode::MOVSSmr, + 2712 => Opcode::MOVSSrm, + 2713 => Opcode::MOVSSrm_alt, + 2714 => Opcode::MOVSSrr, + 2715 => Opcode::MOVSSrr_REV, + 2716 => Opcode::MOVSW, + 2717 => Opcode::MOVSX16rm16, + 2718 => Opcode::MOVSX16rm32, + 2719 => Opcode::MOVSX16rm8, + 2720 => Opcode::MOVSX16rr16, + 2721 => Opcode::MOVSX16rr32, + 2722 => Opcode::MOVSX16rr8, + 2723 => Opcode::MOVSX32rm16, + 2724 => Opcode::MOVSX32rm32, + 2725 => Opcode::MOVSX32rm8, + 2726 => Opcode::MOVSX32rm8_NOREX, + 2727 => Opcode::MOVSX32rr16, + 2728 => Opcode::MOVSX32rr32, + 2729 => Opcode::MOVSX32rr8, + 2730 => Opcode::MOVSX32rr8_NOREX, + 2731 => Opcode::MOVSX64rm16, + 2732 => Opcode::MOVSX64rm32, + 2733 => Opcode::MOVSX64rm8, + 2734 => Opcode::MOVSX64rr16, + 2735 => Opcode::MOVSX64rr32, + 2736 => Opcode::MOVSX64rr8, + 2737 => Opcode::MOVUPDmr, + 2738 => Opcode::MOVUPDrm, + 2739 => Opcode::MOVUPDrr, + 2740 => Opcode::MOVUPDrr_REV, + 2741 => Opcode::MOVUPSmr, + 2742 => Opcode::MOVUPSrm, + 2743 => Opcode::MOVUPSrr, + 2744 => Opcode::MOVUPSrr_REV, + 2745 => Opcode::MOVZPQILo2PQIrr, + 2746 => Opcode::MOVZX16rm16, + 2747 => Opcode::MOVZX16rm8, + 2748 => Opcode::MOVZX16rr16, + 2749 => Opcode::MOVZX16rr8, + 2750 => Opcode::MOVZX32rm16, + 2751 => Opcode::MOVZX32rm8, + 2752 => Opcode::MOVZX32rm8_NOREX, + 2753 => Opcode::MOVZX32rr16, + 2754 => Opcode::MOVZX32rr8, + 2755 => Opcode::MOVZX32rr8_NOREX, + 2756 => Opcode::MOVZX64rm16, + 2757 => Opcode::MOVZX64rm8, + 2758 => Opcode::MOVZX64rr16, + 2759 => Opcode::MOVZX64rr8, + 2760 => Opcode::MPSADBWrmi, + 2761 => Opcode::MPSADBWrri, + 2762 => Opcode::MUL16m, + 2763 => Opcode::MUL16m_EVEX, + 2764 => Opcode::MUL16m_NF, + 2765 => Opcode::MUL16r, + 2766 => Opcode::MUL16r_EVEX, + 2767 => Opcode::MUL16r_NF, + 2768 => Opcode::MUL32m, + 2769 => Opcode::MUL32m_EVEX, + 2770 => Opcode::MUL32m_NF, + 2771 => Opcode::MUL32r, + 2772 => Opcode::MUL32r_EVEX, + 2773 => Opcode::MUL32r_NF, + 2774 => Opcode::MUL64m, + 2775 => Opcode::MUL64m_EVEX, + 2776 => Opcode::MUL64m_NF, + 2777 => Opcode::MUL64r, + 2778 => Opcode::MUL64r_EVEX, + 2779 => Opcode::MUL64r_NF, + 2780 => Opcode::MUL8m, + 2781 => Opcode::MUL8m_EVEX, + 2782 => Opcode::MUL8m_NF, + 2783 => Opcode::MUL8r, + 2784 => Opcode::MUL8r_EVEX, + 2785 => Opcode::MUL8r_NF, + 2786 => Opcode::MULPDrm, + 2787 => Opcode::MULPDrr, + 2788 => Opcode::MULPSrm, + 2789 => Opcode::MULPSrr, + 2790 => Opcode::MULSDrm, + 2791 => Opcode::MULSDrm_Int, + 2792 => Opcode::MULSDrr, + 2793 => Opcode::MULSDrr_Int, + 2794 => Opcode::MULSSrm, + 2795 => Opcode::MULSSrm_Int, + 2796 => Opcode::MULSSrr, + 2797 => Opcode::MULSSrr_Int, + 2798 => Opcode::MULX32Hrm, + 2799 => Opcode::MULX32Hrr, + 2800 => Opcode::MULX32rm, + 2801 => Opcode::MULX32rm_EVEX, + 2802 => Opcode::MULX32rr, + 2803 => Opcode::MULX32rr_EVEX, + 2804 => Opcode::MULX64Hrm, + 2805 => Opcode::MULX64Hrr, + 2806 => Opcode::MULX64rm, + 2807 => Opcode::MULX64rm_EVEX, + 2808 => Opcode::MULX64rr, + 2809 => Opcode::MULX64rr_EVEX, + 2810 => Opcode::MUL_F32m, + 2811 => Opcode::MUL_F64m, + 2812 => Opcode::MUL_FI16m, + 2813 => Opcode::MUL_FI32m, + 2814 => Opcode::MUL_FPrST0, + 2815 => Opcode::MUL_FST0r, + 2816 => Opcode::MUL_Fp32, + 2817 => Opcode::MUL_Fp32m, + 2818 => Opcode::MUL_Fp64, + 2819 => Opcode::MUL_Fp64m, + 2820 => Opcode::MUL_Fp64m32, + 2821 => Opcode::MUL_Fp80, + 2822 => Opcode::MUL_Fp80m32, + 2823 => Opcode::MUL_Fp80m64, + 2824 => Opcode::MUL_FpI16m32, + 2825 => Opcode::MUL_FpI16m64, + 2826 => Opcode::MUL_FpI16m80, + 2827 => Opcode::MUL_FpI32m32, + 2828 => Opcode::MUL_FpI32m64, + 2829 => Opcode::MUL_FpI32m80, + 2830 => Opcode::MUL_FrST0, + 2831 => Opcode::MWAITXrrr, + 2832 => Opcode::MWAITrr, + 2833 => Opcode::NEG16m, + 2834 => Opcode::NEG16m_EVEX, + 2835 => Opcode::NEG16m_ND, + 2836 => Opcode::NEG16m_NF, + 2837 => Opcode::NEG16m_NF_ND, + 2838 => Opcode::NEG16r, + 2839 => Opcode::NEG16r_EVEX, + 2840 => Opcode::NEG16r_ND, + 2841 => Opcode::NEG16r_NF, + 2842 => Opcode::NEG16r_NF_ND, + 2843 => Opcode::NEG32m, + 2844 => Opcode::NEG32m_EVEX, + 2845 => Opcode::NEG32m_ND, + 2846 => Opcode::NEG32m_NF, + 2847 => Opcode::NEG32m_NF_ND, + 2848 => Opcode::NEG32r, + 2849 => Opcode::NEG32r_EVEX, + 2850 => Opcode::NEG32r_ND, + 2851 => Opcode::NEG32r_NF, + 2852 => Opcode::NEG32r_NF_ND, + 2853 => Opcode::NEG64m, + 2854 => Opcode::NEG64m_EVEX, + 2855 => Opcode::NEG64m_ND, + 2856 => Opcode::NEG64m_NF, + 2857 => Opcode::NEG64m_NF_ND, + 2858 => Opcode::NEG64r, + 2859 => Opcode::NEG64r_EVEX, + 2860 => Opcode::NEG64r_ND, + 2861 => Opcode::NEG64r_NF, + 2862 => Opcode::NEG64r_NF_ND, + 2863 => Opcode::NEG8m, + 2864 => Opcode::NEG8m_EVEX, + 2865 => Opcode::NEG8m_ND, + 2866 => Opcode::NEG8m_NF, + 2867 => Opcode::NEG8m_NF_ND, + 2868 => Opcode::NEG8r, + 2869 => Opcode::NEG8r_EVEX, + 2870 => Opcode::NEG8r_ND, + 2871 => Opcode::NEG8r_NF, + 2872 => Opcode::NEG8r_NF_ND, + 2873 => Opcode::NOOP, + 2874 => Opcode::NOOPL, + 2875 => Opcode::NOOPLr, + 2876 => Opcode::NOOPQ, + 2877 => Opcode::NOOPQr, + 2878 => Opcode::NOOPW, + 2879 => Opcode::NOOPWr, + 2880 => Opcode::NOT16m, + 2881 => Opcode::NOT16m_EVEX, + 2882 => Opcode::NOT16m_ND, + 2883 => Opcode::NOT16r, + 2884 => Opcode::NOT16r_EVEX, + 2885 => Opcode::NOT16r_ND, + 2886 => Opcode::NOT32m, + 2887 => Opcode::NOT32m_EVEX, + 2888 => Opcode::NOT32m_ND, + 2889 => Opcode::NOT32r, + 2890 => Opcode::NOT32r_EVEX, + 2891 => Opcode::NOT32r_ND, + 2892 => Opcode::NOT64m, + 2893 => Opcode::NOT64m_EVEX, + 2894 => Opcode::NOT64m_ND, + 2895 => Opcode::NOT64r, + 2896 => Opcode::NOT64r_EVEX, + 2897 => Opcode::NOT64r_ND, + 2898 => Opcode::NOT8m, + 2899 => Opcode::NOT8m_EVEX, + 2900 => Opcode::NOT8m_ND, + 2901 => Opcode::NOT8r, + 2902 => Opcode::NOT8r_EVEX, + 2903 => Opcode::NOT8r_ND, + 2904 => Opcode::OR16i16, + 2905 => Opcode::OR16mi, + 2906 => Opcode::OR16mi8, + 2907 => Opcode::OR16mi8_EVEX, + 2908 => Opcode::OR16mi8_ND, + 2909 => Opcode::OR16mi8_NF, + 2910 => Opcode::OR16mi8_NF_ND, + 2911 => Opcode::OR16mi_EVEX, + 2912 => Opcode::OR16mi_ND, + 2913 => Opcode::OR16mi_NF, + 2914 => Opcode::OR16mi_NF_ND, + 2915 => Opcode::OR16mr, + 2916 => Opcode::OR16mr_EVEX, + 2917 => Opcode::OR16mr_ND, + 2918 => Opcode::OR16mr_NF, + 2919 => Opcode::OR16mr_NF_ND, + 2920 => Opcode::OR16ri, + 2921 => Opcode::OR16ri8, + 2922 => Opcode::OR16ri8_EVEX, + 2923 => Opcode::OR16ri8_ND, + 2924 => Opcode::OR16ri8_NF, + 2925 => Opcode::OR16ri8_NF_ND, + 2926 => Opcode::OR16ri_EVEX, + 2927 => Opcode::OR16ri_ND, + 2928 => Opcode::OR16ri_NF, + 2929 => Opcode::OR16ri_NF_ND, + 2930 => Opcode::OR16rm, + 2931 => Opcode::OR16rm_EVEX, + 2932 => Opcode::OR16rm_ND, + 2933 => Opcode::OR16rm_NF, + 2934 => Opcode::OR16rm_NF_ND, + 2935 => Opcode::OR16rr, + 2936 => Opcode::OR16rr_EVEX, + 2937 => Opcode::OR16rr_EVEX_REV, + 2938 => Opcode::OR16rr_ND, + 2939 => Opcode::OR16rr_ND_REV, + 2940 => Opcode::OR16rr_NF, + 2941 => Opcode::OR16rr_NF_ND, + 2942 => Opcode::OR16rr_NF_ND_REV, + 2943 => Opcode::OR16rr_NF_REV, + 2944 => Opcode::OR16rr_REV, + 2945 => Opcode::OR32i32, + 2946 => Opcode::OR32mi, + 2947 => Opcode::OR32mi8, + 2948 => Opcode::OR32mi8Locked, + 2949 => Opcode::OR32mi8_EVEX, + 2950 => Opcode::OR32mi8_ND, + 2951 => Opcode::OR32mi8_NF, + 2952 => Opcode::OR32mi8_NF_ND, + 2953 => Opcode::OR32mi_EVEX, + 2954 => Opcode::OR32mi_ND, + 2955 => Opcode::OR32mi_NF, + 2956 => Opcode::OR32mi_NF_ND, + 2957 => Opcode::OR32mr, + 2958 => Opcode::OR32mr_EVEX, + 2959 => Opcode::OR32mr_ND, + 2960 => Opcode::OR32mr_NF, + 2961 => Opcode::OR32mr_NF_ND, + 2962 => Opcode::OR32ri, + 2963 => Opcode::OR32ri8, + 2964 => Opcode::OR32ri8_EVEX, + 2965 => Opcode::OR32ri8_ND, + 2966 => Opcode::OR32ri8_NF, + 2967 => Opcode::OR32ri8_NF_ND, + 2968 => Opcode::OR32ri_EVEX, + 2969 => Opcode::OR32ri_ND, + 2970 => Opcode::OR32ri_NF, + 2971 => Opcode::OR32ri_NF_ND, + 2972 => Opcode::OR32rm, + 2973 => Opcode::OR32rm_EVEX, + 2974 => Opcode::OR32rm_ND, + 2975 => Opcode::OR32rm_NF, + 2976 => Opcode::OR32rm_NF_ND, + 2977 => Opcode::OR32rr, + 2978 => Opcode::OR32rr_EVEX, + 2979 => Opcode::OR32rr_EVEX_REV, + 2980 => Opcode::OR32rr_ND, + 2981 => Opcode::OR32rr_ND_REV, + 2982 => Opcode::OR32rr_NF, + 2983 => Opcode::OR32rr_NF_ND, + 2984 => Opcode::OR32rr_NF_ND_REV, + 2985 => Opcode::OR32rr_NF_REV, + 2986 => Opcode::OR32rr_REV, + 2987 => Opcode::OR64i32, + 2988 => Opcode::OR64mi32, + 2989 => Opcode::OR64mi32_EVEX, + 2990 => Opcode::OR64mi32_ND, + 2991 => Opcode::OR64mi32_NF, + 2992 => Opcode::OR64mi32_NF_ND, + 2993 => Opcode::OR64mi8, + 2994 => Opcode::OR64mi8_EVEX, + 2995 => Opcode::OR64mi8_ND, + 2996 => Opcode::OR64mi8_NF, + 2997 => Opcode::OR64mi8_NF_ND, + 2998 => Opcode::OR64mr, + 2999 => Opcode::OR64mr_EVEX, + 3000 => Opcode::OR64mr_ND, + 3001 => Opcode::OR64mr_NF, + 3002 => Opcode::OR64mr_NF_ND, + 3003 => Opcode::OR64ri32, + 3004 => Opcode::OR64ri32_EVEX, + 3005 => Opcode::OR64ri32_ND, + 3006 => Opcode::OR64ri32_NF, + 3007 => Opcode::OR64ri32_NF_ND, + 3008 => Opcode::OR64ri8, + 3009 => Opcode::OR64ri8_EVEX, + 3010 => Opcode::OR64ri8_ND, + 3011 => Opcode::OR64ri8_NF, + 3012 => Opcode::OR64ri8_NF_ND, + 3013 => Opcode::OR64rm, + 3014 => Opcode::OR64rm_EVEX, + 3015 => Opcode::OR64rm_ND, + 3016 => Opcode::OR64rm_NF, + 3017 => Opcode::OR64rm_NF_ND, + 3018 => Opcode::OR64rr, + 3019 => Opcode::OR64rr_EVEX, + 3020 => Opcode::OR64rr_EVEX_REV, + 3021 => Opcode::OR64rr_ND, + 3022 => Opcode::OR64rr_ND_REV, + 3023 => Opcode::OR64rr_NF, + 3024 => Opcode::OR64rr_NF_ND, + 3025 => Opcode::OR64rr_NF_ND_REV, + 3026 => Opcode::OR64rr_NF_REV, + 3027 => Opcode::OR64rr_REV, + 3028 => Opcode::OR8i8, + 3029 => Opcode::OR8mi, + 3030 => Opcode::OR8mi8, + 3031 => Opcode::OR8mi_EVEX, + 3032 => Opcode::OR8mi_ND, + 3033 => Opcode::OR8mi_NF, + 3034 => Opcode::OR8mi_NF_ND, + 3035 => Opcode::OR8mr, + 3036 => Opcode::OR8mr_EVEX, + 3037 => Opcode::OR8mr_ND, + 3038 => Opcode::OR8mr_NF, + 3039 => Opcode::OR8mr_NF_ND, + 3040 => Opcode::OR8ri, + 3041 => Opcode::OR8ri8, + 3042 => Opcode::OR8ri_EVEX, + 3043 => Opcode::OR8ri_ND, + 3044 => Opcode::OR8ri_NF, + 3045 => Opcode::OR8ri_NF_ND, + 3046 => Opcode::OR8rm, + 3047 => Opcode::OR8rm_EVEX, + 3048 => Opcode::OR8rm_ND, + 3049 => Opcode::OR8rm_NF, + 3050 => Opcode::OR8rm_NF_ND, + 3051 => Opcode::OR8rr, + 3052 => Opcode::OR8rr_EVEX, + 3053 => Opcode::OR8rr_EVEX_REV, + 3054 => Opcode::OR8rr_ND, + 3055 => Opcode::OR8rr_ND_REV, + 3056 => Opcode::OR8rr_NF, + 3057 => Opcode::OR8rr_NF_ND, + 3058 => Opcode::OR8rr_NF_ND_REV, + 3059 => Opcode::OR8rr_NF_REV, + 3060 => Opcode::OR8rr_REV, + 3061 => Opcode::ORPDrm, + 3062 => Opcode::ORPDrr, + 3063 => Opcode::ORPSrm, + 3064 => Opcode::ORPSrr, + 3065 => Opcode::OUT16ir, + 3066 => Opcode::OUT16rr, + 3067 => Opcode::OUT32ir, + 3068 => Opcode::OUT32rr, + 3069 => Opcode::OUT8ir, + 3070 => Opcode::OUT8rr, + 3071 => Opcode::OUTSB, + 3072 => Opcode::OUTSL, + 3073 => Opcode::OUTSW, + 3074 => Opcode::PABSBrm, + 3075 => Opcode::PABSBrr, + 3076 => Opcode::PABSDrm, + 3077 => Opcode::PABSDrr, + 3078 => Opcode::PABSWrm, + 3079 => Opcode::PABSWrr, + 3080 => Opcode::PACKSSDWrm, + 3081 => Opcode::PACKSSDWrr, + 3082 => Opcode::PACKSSWBrm, + 3083 => Opcode::PACKSSWBrr, + 3084 => Opcode::PACKUSDWrm, + 3085 => Opcode::PACKUSDWrr, + 3086 => Opcode::PACKUSWBrm, + 3087 => Opcode::PACKUSWBrr, + 3088 => Opcode::PADDBrm, + 3089 => Opcode::PADDBrr, + 3090 => Opcode::PADDDrm, + 3091 => Opcode::PADDDrr, + 3092 => Opcode::PADDQrm, + 3093 => Opcode::PADDQrr, + 3094 => Opcode::PADDSBrm, + 3095 => Opcode::PADDSBrr, + 3096 => Opcode::PADDSWrm, + 3097 => Opcode::PADDSWrr, + 3098 => Opcode::PADDUSBrm, + 3099 => Opcode::PADDUSBrr, + 3100 => Opcode::PADDUSWrm, + 3101 => Opcode::PADDUSWrr, + 3102 => Opcode::PADDWrm, + 3103 => Opcode::PADDWrr, + 3104 => Opcode::PALIGNRrmi, + 3105 => Opcode::PALIGNRrri, + 3106 => Opcode::PANDNrm, + 3107 => Opcode::PANDNrr, + 3108 => Opcode::PANDrm, + 3109 => Opcode::PANDrr, + 3110 => Opcode::PAUSE, + 3111 => Opcode::PAVGBrm, + 3112 => Opcode::PAVGBrr, + 3113 => Opcode::PAVGUSBrm, + 3114 => Opcode::PAVGUSBrr, + 3115 => Opcode::PAVGWrm, + 3116 => Opcode::PAVGWrr, + 3117 => Opcode::PBLENDVBrm0, + 3118 => Opcode::PBLENDVBrr0, + 3119 => Opcode::PBLENDWrmi, + 3120 => Opcode::PBLENDWrri, + 3121 => Opcode::PBNDKB, + 3122 => Opcode::PCLMULQDQrmi, + 3123 => Opcode::PCLMULQDQrri, + 3124 => Opcode::PCMPEQBrm, + 3125 => Opcode::PCMPEQBrr, + 3126 => Opcode::PCMPEQDrm, + 3127 => Opcode::PCMPEQDrr, + 3128 => Opcode::PCMPEQQrm, + 3129 => Opcode::PCMPEQQrr, + 3130 => Opcode::PCMPEQWrm, + 3131 => Opcode::PCMPEQWrr, + 3132 => Opcode::PCMPESTRIrmi, + 3133 => Opcode::PCMPESTRIrri, + 3134 => Opcode::PCMPESTRMrmi, + 3135 => Opcode::PCMPESTRMrri, + 3136 => Opcode::PCMPGTBrm, + 3137 => Opcode::PCMPGTBrr, + 3138 => Opcode::PCMPGTDrm, + 3139 => Opcode::PCMPGTDrr, + 3140 => Opcode::PCMPGTQrm, + 3141 => Opcode::PCMPGTQrr, + 3142 => Opcode::PCMPGTWrm, + 3143 => Opcode::PCMPGTWrr, + 3144 => Opcode::PCMPISTRIrmi, + 3145 => Opcode::PCMPISTRIrri, + 3146 => Opcode::PCMPISTRMrmi, + 3147 => Opcode::PCMPISTRMrri, + 3148 => Opcode::PCONFIG, + 3149 => Opcode::PDEP32rm, + 3150 => Opcode::PDEP32rm_EVEX, + 3151 => Opcode::PDEP32rr, + 3152 => Opcode::PDEP32rr_EVEX, + 3153 => Opcode::PDEP64rm, + 3154 => Opcode::PDEP64rm_EVEX, + 3155 => Opcode::PDEP64rr, + 3156 => Opcode::PDEP64rr_EVEX, + 3157 => Opcode::PEXT32rm, + 3158 => Opcode::PEXT32rm_EVEX, + 3159 => Opcode::PEXT32rr, + 3160 => Opcode::PEXT32rr_EVEX, + 3161 => Opcode::PEXT64rm, + 3162 => Opcode::PEXT64rm_EVEX, + 3163 => Opcode::PEXT64rr, + 3164 => Opcode::PEXT64rr_EVEX, + 3165 => Opcode::PEXTRBmri, + 3166 => Opcode::PEXTRBrri, + 3167 => Opcode::PEXTRDmri, + 3168 => Opcode::PEXTRDrri, + 3169 => Opcode::PEXTRQmri, + 3170 => Opcode::PEXTRQrri, + 3171 => Opcode::PEXTRWmri, + 3172 => Opcode::PEXTRWrri, + 3173 => Opcode::PEXTRWrri_REV, + 3174 => Opcode::PF2IDrm, + 3175 => Opcode::PF2IDrr, + 3176 => Opcode::PF2IWrm, + 3177 => Opcode::PF2IWrr, + 3178 => Opcode::PFACCrm, + 3179 => Opcode::PFACCrr, + 3180 => Opcode::PFADDrm, + 3181 => Opcode::PFADDrr, + 3182 => Opcode::PFCMPEQrm, + 3183 => Opcode::PFCMPEQrr, + 3184 => Opcode::PFCMPGErm, + 3185 => Opcode::PFCMPGErr, + 3186 => Opcode::PFCMPGTrm, + 3187 => Opcode::PFCMPGTrr, + 3188 => Opcode::PFMAXrm, + 3189 => Opcode::PFMAXrr, + 3190 => Opcode::PFMINrm, + 3191 => Opcode::PFMINrr, + 3192 => Opcode::PFMULrm, + 3193 => Opcode::PFMULrr, + 3194 => Opcode::PFNACCrm, + 3195 => Opcode::PFNACCrr, + 3196 => Opcode::PFPNACCrm, + 3197 => Opcode::PFPNACCrr, + 3198 => Opcode::PFRCPIT1rm, + 3199 => Opcode::PFRCPIT1rr, + 3200 => Opcode::PFRCPIT2rm, + 3201 => Opcode::PFRCPIT2rr, + 3202 => Opcode::PFRCPrm, + 3203 => Opcode::PFRCPrr, + 3204 => Opcode::PFRSQIT1rm, + 3205 => Opcode::PFRSQIT1rr, + 3206 => Opcode::PFRSQRTrm, + 3207 => Opcode::PFRSQRTrr, + 3208 => Opcode::PFSUBRrm, + 3209 => Opcode::PFSUBRrr, + 3210 => Opcode::PFSUBrm, + 3211 => Opcode::PFSUBrr, + 3212 => Opcode::PHADDDrm, + 3213 => Opcode::PHADDDrr, + 3214 => Opcode::PHADDSWrm, + 3215 => Opcode::PHADDSWrr, + 3216 => Opcode::PHADDWrm, + 3217 => Opcode::PHADDWrr, + 3218 => Opcode::PHMINPOSUWrm, + 3219 => Opcode::PHMINPOSUWrr, + 3220 => Opcode::PHSUBDrm, + 3221 => Opcode::PHSUBDrr, + 3222 => Opcode::PHSUBSWrm, + 3223 => Opcode::PHSUBSWrr, + 3224 => Opcode::PHSUBWrm, + 3225 => Opcode::PHSUBWrr, + 3226 => Opcode::PI2FDrm, + 3227 => Opcode::PI2FDrr, + 3228 => Opcode::PI2FWrm, + 3229 => Opcode::PI2FWrr, + 3230 => Opcode::PINSRBrmi, + 3231 => Opcode::PINSRBrri, + 3232 => Opcode::PINSRDrmi, + 3233 => Opcode::PINSRDrri, + 3234 => Opcode::PINSRQrmi, + 3235 => Opcode::PINSRQrri, + 3236 => Opcode::PINSRWrmi, + 3237 => Opcode::PINSRWrri, + 3238 => Opcode::PMADDUBSWrm, + 3239 => Opcode::PMADDUBSWrr, + 3240 => Opcode::PMADDWDrm, + 3241 => Opcode::PMADDWDrr, + 3242 => Opcode::PMAXSBrm, + 3243 => Opcode::PMAXSBrr, + 3244 => Opcode::PMAXSDrm, + 3245 => Opcode::PMAXSDrr, + 3246 => Opcode::PMAXSWrm, + 3247 => Opcode::PMAXSWrr, + 3248 => Opcode::PMAXUBrm, + 3249 => Opcode::PMAXUBrr, + 3250 => Opcode::PMAXUDrm, + 3251 => Opcode::PMAXUDrr, + 3252 => Opcode::PMAXUWrm, + 3253 => Opcode::PMAXUWrr, + 3254 => Opcode::PMINSBrm, + 3255 => Opcode::PMINSBrr, + 3256 => Opcode::PMINSDrm, + 3257 => Opcode::PMINSDrr, + 3258 => Opcode::PMINSWrm, + 3259 => Opcode::PMINSWrr, + 3260 => Opcode::PMINUBrm, + 3261 => Opcode::PMINUBrr, + 3262 => Opcode::PMINUDrm, + 3263 => Opcode::PMINUDrr, + 3264 => Opcode::PMINUWrm, + 3265 => Opcode::PMINUWrr, + 3266 => Opcode::PMOVMSKBrr, + 3267 => Opcode::PMOVSXBDrm, + 3268 => Opcode::PMOVSXBDrr, + 3269 => Opcode::PMOVSXBQrm, + 3270 => Opcode::PMOVSXBQrr, + 3271 => Opcode::PMOVSXBWrm, + 3272 => Opcode::PMOVSXBWrr, + 3273 => Opcode::PMOVSXDQrm, + 3274 => Opcode::PMOVSXDQrr, + 3275 => Opcode::PMOVSXWDrm, + 3276 => Opcode::PMOVSXWDrr, + 3277 => Opcode::PMOVSXWQrm, + 3278 => Opcode::PMOVSXWQrr, + 3279 => Opcode::PMOVZXBDrm, + 3280 => Opcode::PMOVZXBDrr, + 3281 => Opcode::PMOVZXBQrm, + 3282 => Opcode::PMOVZXBQrr, + 3283 => Opcode::PMOVZXBWrm, + 3284 => Opcode::PMOVZXBWrr, + 3285 => Opcode::PMOVZXDQrm, + 3286 => Opcode::PMOVZXDQrr, + 3287 => Opcode::PMOVZXWDrm, + 3288 => Opcode::PMOVZXWDrr, + 3289 => Opcode::PMOVZXWQrm, + 3290 => Opcode::PMOVZXWQrr, + 3291 => Opcode::PMULDQrm, + 3292 => Opcode::PMULDQrr, + 3293 => Opcode::PMULHRSWrm, + 3294 => Opcode::PMULHRSWrr, + 3295 => Opcode::PMULHRWrm, + 3296 => Opcode::PMULHRWrr, + 3297 => Opcode::PMULHUWrm, + 3298 => Opcode::PMULHUWrr, + 3299 => Opcode::PMULHWrm, + 3300 => Opcode::PMULHWrr, + 3301 => Opcode::PMULLDrm, + 3302 => Opcode::PMULLDrr, + 3303 => Opcode::PMULLWrm, + 3304 => Opcode::PMULLWrr, + 3305 => Opcode::PMULUDQrm, + 3306 => Opcode::PMULUDQrr, + 3307 => Opcode::POP16r, + 3308 => Opcode::POP16rmm, + 3309 => Opcode::POP16rmr, + 3310 => Opcode::POP2, + 3311 => Opcode::POP2P, + 3312 => Opcode::POP32r, + 3313 => Opcode::POP32rmm, + 3314 => Opcode::POP32rmr, + 3315 => Opcode::POP64r, + 3316 => Opcode::POP64rmm, + 3317 => Opcode::POP64rmr, + 3318 => Opcode::POPA16, + 3319 => Opcode::POPA32, + 3320 => Opcode::POPCNT16rm, + 3321 => Opcode::POPCNT16rm_EVEX, + 3322 => Opcode::POPCNT16rm_NF, + 3323 => Opcode::POPCNT16rr, + 3324 => Opcode::POPCNT16rr_EVEX, + 3325 => Opcode::POPCNT16rr_NF, + 3326 => Opcode::POPCNT32rm, + 3327 => Opcode::POPCNT32rm_EVEX, + 3328 => Opcode::POPCNT32rm_NF, + 3329 => Opcode::POPCNT32rr, + 3330 => Opcode::POPCNT32rr_EVEX, + 3331 => Opcode::POPCNT32rr_NF, + 3332 => Opcode::POPCNT64rm, + 3333 => Opcode::POPCNT64rm_EVEX, + 3334 => Opcode::POPCNT64rm_NF, + 3335 => Opcode::POPCNT64rr, + 3336 => Opcode::POPCNT64rr_EVEX, + 3337 => Opcode::POPCNT64rr_NF, + 3338 => Opcode::POPDS16, + 3339 => Opcode::POPDS32, + 3340 => Opcode::POPES16, + 3341 => Opcode::POPES32, + 3342 => Opcode::POPF16, + 3343 => Opcode::POPF32, + 3344 => Opcode::POPF64, + 3345 => Opcode::POPFS16, + 3346 => Opcode::POPFS32, + 3347 => Opcode::POPFS64, + 3348 => Opcode::POPGS16, + 3349 => Opcode::POPGS32, + 3350 => Opcode::POPGS64, + 3351 => Opcode::POPP64r, + 3352 => Opcode::POPSS16, + 3353 => Opcode::POPSS32, + 3354 => Opcode::PORrm, + 3355 => Opcode::PORrr, + 3356 => Opcode::PREFETCH, + 3357 => Opcode::PREFETCHIT0, + 3358 => Opcode::PREFETCHIT1, + 3359 => Opcode::PREFETCHNTA, + 3360 => Opcode::PREFETCHRST2, + 3361 => Opcode::PREFETCHT0, + 3362 => Opcode::PREFETCHT1, + 3363 => Opcode::PREFETCHT2, + 3364 => Opcode::PREFETCHW, + 3365 => Opcode::PREFETCHWT1, + 3366 => Opcode::PROBED_ALLOCA_32, + 3367 => Opcode::PROBED_ALLOCA_64, + 3368 => Opcode::PSADBWrm, + 3369 => Opcode::PSADBWrr, + 3370 => Opcode::PSHUFBrm, + 3371 => Opcode::PSHUFBrr, + 3372 => Opcode::PSHUFDmi, + 3373 => Opcode::PSHUFDri, + 3374 => Opcode::PSHUFHWmi, + 3375 => Opcode::PSHUFHWri, + 3376 => Opcode::PSHUFLWmi, + 3377 => Opcode::PSHUFLWri, + 3378 => Opcode::PSIGNBrm, + 3379 => Opcode::PSIGNBrr, + 3380 => Opcode::PSIGNDrm, + 3381 => Opcode::PSIGNDrr, + 3382 => Opcode::PSIGNWrm, + 3383 => Opcode::PSIGNWrr, + 3384 => Opcode::PSLLDQri, + 3385 => Opcode::PSLLDri, + 3386 => Opcode::PSLLDrm, + 3387 => Opcode::PSLLDrr, + 3388 => Opcode::PSLLQri, + 3389 => Opcode::PSLLQrm, + 3390 => Opcode::PSLLQrr, + 3391 => Opcode::PSLLWri, + 3392 => Opcode::PSLLWrm, + 3393 => Opcode::PSLLWrr, + 3394 => Opcode::PSMASH, + 3395 => Opcode::PSRADri, + 3396 => Opcode::PSRADrm, + 3397 => Opcode::PSRADrr, + 3398 => Opcode::PSRAWri, + 3399 => Opcode::PSRAWrm, + 3400 => Opcode::PSRAWrr, + 3401 => Opcode::PSRLDQri, + 3402 => Opcode::PSRLDri, + 3403 => Opcode::PSRLDrm, + 3404 => Opcode::PSRLDrr, + 3405 => Opcode::PSRLQri, + 3406 => Opcode::PSRLQrm, + 3407 => Opcode::PSRLQrr, + 3408 => Opcode::PSRLWri, + 3409 => Opcode::PSRLWrm, + 3410 => Opcode::PSRLWrr, + 3411 => Opcode::PSUBBrm, + 3412 => Opcode::PSUBBrr, + 3413 => Opcode::PSUBDrm, + 3414 => Opcode::PSUBDrr, + 3415 => Opcode::PSUBQrm, + 3416 => Opcode::PSUBQrr, + 3417 => Opcode::PSUBSBrm, + 3418 => Opcode::PSUBSBrr, + 3419 => Opcode::PSUBSWrm, + 3420 => Opcode::PSUBSWrr, + 3421 => Opcode::PSUBUSBrm, + 3422 => Opcode::PSUBUSBrr, + 3423 => Opcode::PSUBUSWrm, + 3424 => Opcode::PSUBUSWrr, + 3425 => Opcode::PSUBWrm, + 3426 => Opcode::PSUBWrr, + 3427 => Opcode::PSWAPDrm, + 3428 => Opcode::PSWAPDrr, + 3429 => Opcode::PTCMMIMFP16PS, + 3430 => Opcode::PTCMMIMFP16PSV, + 3431 => Opcode::PTCMMRLFP16PS, + 3432 => Opcode::PTCMMRLFP16PSV, + 3433 => Opcode::PTCVTROWD2PSrre, + 3434 => Opcode::PTCVTROWD2PSrreV, + 3435 => Opcode::PTCVTROWD2PSrri, + 3436 => Opcode::PTCVTROWD2PSrriV, + 3437 => Opcode::PTCVTROWPS2BF16Hrre, + 3438 => Opcode::PTCVTROWPS2BF16HrreV, + 3439 => Opcode::PTCVTROWPS2BF16Hrri, + 3440 => Opcode::PTCVTROWPS2BF16HrriV, + 3441 => Opcode::PTCVTROWPS2BF16Lrre, + 3442 => Opcode::PTCVTROWPS2BF16LrreV, + 3443 => Opcode::PTCVTROWPS2BF16Lrri, + 3444 => Opcode::PTCVTROWPS2BF16LrriV, + 3445 => Opcode::PTCVTROWPS2PHHrre, + 3446 => Opcode::PTCVTROWPS2PHHrreV, + 3447 => Opcode::PTCVTROWPS2PHHrri, + 3448 => Opcode::PTCVTROWPS2PHHrriV, + 3449 => Opcode::PTCVTROWPS2PHLrre, + 3450 => Opcode::PTCVTROWPS2PHLrreV, + 3451 => Opcode::PTCVTROWPS2PHLrri, + 3452 => Opcode::PTCVTROWPS2PHLrriV, + 3453 => Opcode::PTDPBF16PS, + 3454 => Opcode::PTDPBF8PS, + 3455 => Opcode::PTDPBF8PSV, + 3456 => Opcode::PTDPBHF8PS, + 3457 => Opcode::PTDPBHF8PSV, + 3458 => Opcode::PTDPBSSD, + 3459 => Opcode::PTDPBSUD, + 3460 => Opcode::PTDPBUSD, + 3461 => Opcode::PTDPBUUD, + 3462 => Opcode::PTDPFP16PS, + 3463 => Opcode::PTDPHBF8PS, + 3464 => Opcode::PTDPHBF8PSV, + 3465 => Opcode::PTDPHF8PS, + 3466 => Opcode::PTDPHF8PSV, + 3467 => Opcode::PTESTrm, + 3468 => Opcode::PTESTrr, + 3469 => Opcode::PTILELOADD, + 3470 => Opcode::PTILELOADDRS, + 3471 => Opcode::PTILELOADDRST1, + 3472 => Opcode::PTILELOADDT1, + 3473 => Opcode::PTILEMOVROWrre, + 3474 => Opcode::PTILEMOVROWrreV, + 3475 => Opcode::PTILEMOVROWrri, + 3476 => Opcode::PTILEMOVROWrriV, + 3477 => Opcode::PTILESTORED, + 3478 => Opcode::PTILEZERO, + 3479 => Opcode::PTMMULTF32PS, + 3480 => Opcode::PTMMULTF32PSV, + 3481 => Opcode::PTWRITE64m, + 3482 => Opcode::PTWRITE64r, + 3483 => Opcode::PTWRITEm, + 3484 => Opcode::PTWRITEr, + 3485 => Opcode::PUNPCKHBWrm, + 3486 => Opcode::PUNPCKHBWrr, + 3487 => Opcode::PUNPCKHDQrm, + 3488 => Opcode::PUNPCKHDQrr, + 3489 => Opcode::PUNPCKHQDQrm, + 3490 => Opcode::PUNPCKHQDQrr, + 3491 => Opcode::PUNPCKHWDrm, + 3492 => Opcode::PUNPCKHWDrr, + 3493 => Opcode::PUNPCKLBWrm, + 3494 => Opcode::PUNPCKLBWrr, + 3495 => Opcode::PUNPCKLDQrm, + 3496 => Opcode::PUNPCKLDQrr, + 3497 => Opcode::PUNPCKLQDQrm, + 3498 => Opcode::PUNPCKLQDQrr, + 3499 => Opcode::PUNPCKLWDrm, + 3500 => Opcode::PUNPCKLWDrr, + 3501 => Opcode::PUSH16i, + 3502 => Opcode::PUSH16i8, + 3503 => Opcode::PUSH16r, + 3504 => Opcode::PUSH16rmm, + 3505 => Opcode::PUSH16rmr, + 3506 => Opcode::PUSH2, + 3507 => Opcode::PUSH2P, + 3508 => Opcode::PUSH32i, + 3509 => Opcode::PUSH32i8, + 3510 => Opcode::PUSH32r, + 3511 => Opcode::PUSH32rmm, + 3512 => Opcode::PUSH32rmr, + 3513 => Opcode::PUSH64i32, + 3514 => Opcode::PUSH64i8, + 3515 => Opcode::PUSH64r, + 3516 => Opcode::PUSH64rmm, + 3517 => Opcode::PUSH64rmr, + 3518 => Opcode::PUSHA16, + 3519 => Opcode::PUSHA32, + 3520 => Opcode::PUSHCS16, + 3521 => Opcode::PUSHCS32, + 3522 => Opcode::PUSHDS16, + 3523 => Opcode::PUSHDS32, + 3524 => Opcode::PUSHES16, + 3525 => Opcode::PUSHES32, + 3526 => Opcode::PUSHF16, + 3527 => Opcode::PUSHF32, + 3528 => Opcode::PUSHF64, + 3529 => Opcode::PUSHFS16, + 3530 => Opcode::PUSHFS32, + 3531 => Opcode::PUSHFS64, + 3532 => Opcode::PUSHGS16, + 3533 => Opcode::PUSHGS32, + 3534 => Opcode::PUSHGS64, + 3535 => Opcode::PUSHP64r, + 3536 => Opcode::PUSHSS16, + 3537 => Opcode::PUSHSS32, + 3538 => Opcode::PVALIDATE32, + 3539 => Opcode::PVALIDATE64, + 3540 => Opcode::PXORrm, + 3541 => Opcode::PXORrr, + 3542 => Opcode::RCL16m1, + 3543 => Opcode::RCL16m1_EVEX, + 3544 => Opcode::RCL16m1_ND, + 3545 => Opcode::RCL16mCL, + 3546 => Opcode::RCL16mCL_EVEX, + 3547 => Opcode::RCL16mCL_ND, + 3548 => Opcode::RCL16mi, + 3549 => Opcode::RCL16mi_EVEX, + 3550 => Opcode::RCL16mi_ND, + 3551 => Opcode::RCL16r1, + 3552 => Opcode::RCL16r1_EVEX, + 3553 => Opcode::RCL16r1_ND, + 3554 => Opcode::RCL16rCL, + 3555 => Opcode::RCL16rCL_EVEX, + 3556 => Opcode::RCL16rCL_ND, + 3557 => Opcode::RCL16ri, + 3558 => Opcode::RCL16ri_EVEX, + 3559 => Opcode::RCL16ri_ND, + 3560 => Opcode::RCL32m1, + 3561 => Opcode::RCL32m1_EVEX, + 3562 => Opcode::RCL32m1_ND, + 3563 => Opcode::RCL32mCL, + 3564 => Opcode::RCL32mCL_EVEX, + 3565 => Opcode::RCL32mCL_ND, + 3566 => Opcode::RCL32mi, + 3567 => Opcode::RCL32mi_EVEX, + 3568 => Opcode::RCL32mi_ND, + 3569 => Opcode::RCL32r1, + 3570 => Opcode::RCL32r1_EVEX, + 3571 => Opcode::RCL32r1_ND, + 3572 => Opcode::RCL32rCL, + 3573 => Opcode::RCL32rCL_EVEX, + 3574 => Opcode::RCL32rCL_ND, + 3575 => Opcode::RCL32ri, + 3576 => Opcode::RCL32ri_EVEX, + 3577 => Opcode::RCL32ri_ND, + 3578 => Opcode::RCL64m1, + 3579 => Opcode::RCL64m1_EVEX, + 3580 => Opcode::RCL64m1_ND, + 3581 => Opcode::RCL64mCL, + 3582 => Opcode::RCL64mCL_EVEX, + 3583 => Opcode::RCL64mCL_ND, + 3584 => Opcode::RCL64mi, + 3585 => Opcode::RCL64mi_EVEX, + 3586 => Opcode::RCL64mi_ND, + 3587 => Opcode::RCL64r1, + 3588 => Opcode::RCL64r1_EVEX, + 3589 => Opcode::RCL64r1_ND, + 3590 => Opcode::RCL64rCL, + 3591 => Opcode::RCL64rCL_EVEX, + 3592 => Opcode::RCL64rCL_ND, + 3593 => Opcode::RCL64ri, + 3594 => Opcode::RCL64ri_EVEX, + 3595 => Opcode::RCL64ri_ND, + 3596 => Opcode::RCL8m1, + 3597 => Opcode::RCL8m1_EVEX, + 3598 => Opcode::RCL8m1_ND, + 3599 => Opcode::RCL8mCL, + 3600 => Opcode::RCL8mCL_EVEX, + 3601 => Opcode::RCL8mCL_ND, + 3602 => Opcode::RCL8mi, + 3603 => Opcode::RCL8mi_EVEX, + 3604 => Opcode::RCL8mi_ND, + 3605 => Opcode::RCL8r1, + 3606 => Opcode::RCL8r1_EVEX, + 3607 => Opcode::RCL8r1_ND, + 3608 => Opcode::RCL8rCL, + 3609 => Opcode::RCL8rCL_EVEX, + 3610 => Opcode::RCL8rCL_ND, + 3611 => Opcode::RCL8ri, + 3612 => Opcode::RCL8ri_EVEX, + 3613 => Opcode::RCL8ri_ND, + 3614 => Opcode::RCPPSm, + 3615 => Opcode::RCPPSr, + 3616 => Opcode::RCPSSm, + 3617 => Opcode::RCPSSm_Int, + 3618 => Opcode::RCPSSr, + 3619 => Opcode::RCPSSr_Int, + 3620 => Opcode::RCR16m1, + 3621 => Opcode::RCR16m1_EVEX, + 3622 => Opcode::RCR16m1_ND, + 3623 => Opcode::RCR16mCL, + 3624 => Opcode::RCR16mCL_EVEX, + 3625 => Opcode::RCR16mCL_ND, + 3626 => Opcode::RCR16mi, + 3627 => Opcode::RCR16mi_EVEX, + 3628 => Opcode::RCR16mi_ND, + 3629 => Opcode::RCR16r1, + 3630 => Opcode::RCR16r1_EVEX, + 3631 => Opcode::RCR16r1_ND, + 3632 => Opcode::RCR16rCL, + 3633 => Opcode::RCR16rCL_EVEX, + 3634 => Opcode::RCR16rCL_ND, + 3635 => Opcode::RCR16ri, + 3636 => Opcode::RCR16ri_EVEX, + 3637 => Opcode::RCR16ri_ND, + 3638 => Opcode::RCR32m1, + 3639 => Opcode::RCR32m1_EVEX, + 3640 => Opcode::RCR32m1_ND, + 3641 => Opcode::RCR32mCL, + 3642 => Opcode::RCR32mCL_EVEX, + 3643 => Opcode::RCR32mCL_ND, + 3644 => Opcode::RCR32mi, + 3645 => Opcode::RCR32mi_EVEX, + 3646 => Opcode::RCR32mi_ND, + 3647 => Opcode::RCR32r1, + 3648 => Opcode::RCR32r1_EVEX, + 3649 => Opcode::RCR32r1_ND, + 3650 => Opcode::RCR32rCL, + 3651 => Opcode::RCR32rCL_EVEX, + 3652 => Opcode::RCR32rCL_ND, + 3653 => Opcode::RCR32ri, + 3654 => Opcode::RCR32ri_EVEX, + 3655 => Opcode::RCR32ri_ND, + 3656 => Opcode::RCR64m1, + 3657 => Opcode::RCR64m1_EVEX, + 3658 => Opcode::RCR64m1_ND, + 3659 => Opcode::RCR64mCL, + 3660 => Opcode::RCR64mCL_EVEX, + 3661 => Opcode::RCR64mCL_ND, + 3662 => Opcode::RCR64mi, + 3663 => Opcode::RCR64mi_EVEX, + 3664 => Opcode::RCR64mi_ND, + 3665 => Opcode::RCR64r1, + 3666 => Opcode::RCR64r1_EVEX, + 3667 => Opcode::RCR64r1_ND, + 3668 => Opcode::RCR64rCL, + 3669 => Opcode::RCR64rCL_EVEX, + 3670 => Opcode::RCR64rCL_ND, + 3671 => Opcode::RCR64ri, + 3672 => Opcode::RCR64ri_EVEX, + 3673 => Opcode::RCR64ri_ND, + 3674 => Opcode::RCR8m1, + 3675 => Opcode::RCR8m1_EVEX, + 3676 => Opcode::RCR8m1_ND, + 3677 => Opcode::RCR8mCL, + 3678 => Opcode::RCR8mCL_EVEX, + 3679 => Opcode::RCR8mCL_ND, + 3680 => Opcode::RCR8mi, + 3681 => Opcode::RCR8mi_EVEX, + 3682 => Opcode::RCR8mi_ND, + 3683 => Opcode::RCR8r1, + 3684 => Opcode::RCR8r1_EVEX, + 3685 => Opcode::RCR8r1_ND, + 3686 => Opcode::RCR8rCL, + 3687 => Opcode::RCR8rCL_EVEX, + 3688 => Opcode::RCR8rCL_ND, + 3689 => Opcode::RCR8ri, + 3690 => Opcode::RCR8ri_EVEX, + 3691 => Opcode::RCR8ri_ND, + 3692 => Opcode::RDFSBASE, + 3693 => Opcode::RDFSBASE64, + 3694 => Opcode::RDGSBASE, + 3695 => Opcode::RDGSBASE64, + 3696 => Opcode::RDMSR, + 3697 => Opcode::RDMSRLIST, + 3698 => Opcode::RDMSRri, + 3699 => Opcode::RDMSRri_EVEX, + 3700 => Opcode::RDPID32, + 3701 => Opcode::RDPID64, + 3702 => Opcode::RDPKRUr, + 3703 => Opcode::RDPMC, + 3704 => Opcode::RDPRU, + 3705 => Opcode::RDRAND16r, + 3706 => Opcode::RDRAND32r, + 3707 => Opcode::RDRAND64r, + 3708 => Opcode::RDSEED16r, + 3709 => Opcode::RDSEED32r, + 3710 => Opcode::RDSEED64r, + 3711 => Opcode::RDSSPD, + 3712 => Opcode::RDSSPQ, + 3713 => Opcode::RDTSC, + 3714 => Opcode::RDTSCP, + 3715 => Opcode::REPNE_PREFIX, + 3716 => Opcode::REP_MOVSB_32, + 3717 => Opcode::REP_MOVSB_64, + 3718 => Opcode::REP_MOVSD_32, + 3719 => Opcode::REP_MOVSD_64, + 3720 => Opcode::REP_MOVSQ_32, + 3721 => Opcode::REP_MOVSQ_64, + 3722 => Opcode::REP_MOVSW_32, + 3723 => Opcode::REP_MOVSW_64, + 3724 => Opcode::REP_PREFIX, + 3725 => Opcode::REP_STOSB_32, + 3726 => Opcode::REP_STOSB_64, + 3727 => Opcode::REP_STOSD_32, + 3728 => Opcode::REP_STOSD_64, + 3729 => Opcode::REP_STOSQ_32, + 3730 => Opcode::REP_STOSQ_64, + 3731 => Opcode::REP_STOSW_32, + 3732 => Opcode::REP_STOSW_64, + 3733 => Opcode::RET, + 3734 => Opcode::RET16, + 3735 => Opcode::RET32, + 3736 => Opcode::RET64, + 3737 => Opcode::RETI16, + 3738 => Opcode::RETI32, + 3739 => Opcode::RETI64, + 3740 => Opcode::REX64_PREFIX, + 3741 => Opcode::RMPADJUST, + 3742 => Opcode::RMPQUERY, + 3743 => Opcode::RMPUPDATE, + 3744 => Opcode::ROL16m1, + 3745 => Opcode::ROL16m1_EVEX, + 3746 => Opcode::ROL16m1_ND, + 3747 => Opcode::ROL16m1_NF, + 3748 => Opcode::ROL16m1_NF_ND, + 3749 => Opcode::ROL16mCL, + 3750 => Opcode::ROL16mCL_EVEX, + 3751 => Opcode::ROL16mCL_ND, + 3752 => Opcode::ROL16mCL_NF, + 3753 => Opcode::ROL16mCL_NF_ND, + 3754 => Opcode::ROL16mi, + 3755 => Opcode::ROL16mi_EVEX, + 3756 => Opcode::ROL16mi_ND, + 3757 => Opcode::ROL16mi_NF, + 3758 => Opcode::ROL16mi_NF_ND, + 3759 => Opcode::ROL16r1, + 3760 => Opcode::ROL16r1_EVEX, + 3761 => Opcode::ROL16r1_ND, + 3762 => Opcode::ROL16r1_NF, + 3763 => Opcode::ROL16r1_NF_ND, + 3764 => Opcode::ROL16rCL, + 3765 => Opcode::ROL16rCL_EVEX, + 3766 => Opcode::ROL16rCL_ND, + 3767 => Opcode::ROL16rCL_NF, + 3768 => Opcode::ROL16rCL_NF_ND, + 3769 => Opcode::ROL16ri, + 3770 => Opcode::ROL16ri_EVEX, + 3771 => Opcode::ROL16ri_ND, + 3772 => Opcode::ROL16ri_NF, + 3773 => Opcode::ROL16ri_NF_ND, + 3774 => Opcode::ROL32m1, + 3775 => Opcode::ROL32m1_EVEX, + 3776 => Opcode::ROL32m1_ND, + 3777 => Opcode::ROL32m1_NF, + 3778 => Opcode::ROL32m1_NF_ND, + 3779 => Opcode::ROL32mCL, + 3780 => Opcode::ROL32mCL_EVEX, + 3781 => Opcode::ROL32mCL_ND, + 3782 => Opcode::ROL32mCL_NF, + 3783 => Opcode::ROL32mCL_NF_ND, + 3784 => Opcode::ROL32mi, + 3785 => Opcode::ROL32mi_EVEX, + 3786 => Opcode::ROL32mi_ND, + 3787 => Opcode::ROL32mi_NF, + 3788 => Opcode::ROL32mi_NF_ND, + 3789 => Opcode::ROL32r1, + 3790 => Opcode::ROL32r1_EVEX, + 3791 => Opcode::ROL32r1_ND, + 3792 => Opcode::ROL32r1_NF, + 3793 => Opcode::ROL32r1_NF_ND, + 3794 => Opcode::ROL32rCL, + 3795 => Opcode::ROL32rCL_EVEX, + 3796 => Opcode::ROL32rCL_ND, + 3797 => Opcode::ROL32rCL_NF, + 3798 => Opcode::ROL32rCL_NF_ND, + 3799 => Opcode::ROL32ri, + 3800 => Opcode::ROL32ri_EVEX, + 3801 => Opcode::ROL32ri_ND, + 3802 => Opcode::ROL32ri_NF, + 3803 => Opcode::ROL32ri_NF_ND, + 3804 => Opcode::ROL64m1, + 3805 => Opcode::ROL64m1_EVEX, + 3806 => Opcode::ROL64m1_ND, + 3807 => Opcode::ROL64m1_NF, + 3808 => Opcode::ROL64m1_NF_ND, + 3809 => Opcode::ROL64mCL, + 3810 => Opcode::ROL64mCL_EVEX, + 3811 => Opcode::ROL64mCL_ND, + 3812 => Opcode::ROL64mCL_NF, + 3813 => Opcode::ROL64mCL_NF_ND, + 3814 => Opcode::ROL64mi, + 3815 => Opcode::ROL64mi_EVEX, + 3816 => Opcode::ROL64mi_ND, + 3817 => Opcode::ROL64mi_NF, + 3818 => Opcode::ROL64mi_NF_ND, + 3819 => Opcode::ROL64r1, + 3820 => Opcode::ROL64r1_EVEX, + 3821 => Opcode::ROL64r1_ND, + 3822 => Opcode::ROL64r1_NF, + 3823 => Opcode::ROL64r1_NF_ND, + 3824 => Opcode::ROL64rCL, + 3825 => Opcode::ROL64rCL_EVEX, + 3826 => Opcode::ROL64rCL_ND, + 3827 => Opcode::ROL64rCL_NF, + 3828 => Opcode::ROL64rCL_NF_ND, + 3829 => Opcode::ROL64ri, + 3830 => Opcode::ROL64ri_EVEX, + 3831 => Opcode::ROL64ri_ND, + 3832 => Opcode::ROL64ri_NF, + 3833 => Opcode::ROL64ri_NF_ND, + 3834 => Opcode::ROL8m1, + 3835 => Opcode::ROL8m1_EVEX, + 3836 => Opcode::ROL8m1_ND, + 3837 => Opcode::ROL8m1_NF, + 3838 => Opcode::ROL8m1_NF_ND, + 3839 => Opcode::ROL8mCL, + 3840 => Opcode::ROL8mCL_EVEX, + 3841 => Opcode::ROL8mCL_ND, + 3842 => Opcode::ROL8mCL_NF, + 3843 => Opcode::ROL8mCL_NF_ND, + 3844 => Opcode::ROL8mi, + 3845 => Opcode::ROL8mi_EVEX, + 3846 => Opcode::ROL8mi_ND, + 3847 => Opcode::ROL8mi_NF, + 3848 => Opcode::ROL8mi_NF_ND, + 3849 => Opcode::ROL8r1, + 3850 => Opcode::ROL8r1_EVEX, + 3851 => Opcode::ROL8r1_ND, + 3852 => Opcode::ROL8r1_NF, + 3853 => Opcode::ROL8r1_NF_ND, + 3854 => Opcode::ROL8rCL, + 3855 => Opcode::ROL8rCL_EVEX, + 3856 => Opcode::ROL8rCL_ND, + 3857 => Opcode::ROL8rCL_NF, + 3858 => Opcode::ROL8rCL_NF_ND, + 3859 => Opcode::ROL8ri, + 3860 => Opcode::ROL8ri_EVEX, + 3861 => Opcode::ROL8ri_ND, + 3862 => Opcode::ROL8ri_NF, + 3863 => Opcode::ROL8ri_NF_ND, + 3864 => Opcode::ROR16m1, + 3865 => Opcode::ROR16m1_EVEX, + 3866 => Opcode::ROR16m1_ND, + 3867 => Opcode::ROR16m1_NF, + 3868 => Opcode::ROR16m1_NF_ND, + 3869 => Opcode::ROR16mCL, + 3870 => Opcode::ROR16mCL_EVEX, + 3871 => Opcode::ROR16mCL_ND, + 3872 => Opcode::ROR16mCL_NF, + 3873 => Opcode::ROR16mCL_NF_ND, + 3874 => Opcode::ROR16mi, + 3875 => Opcode::ROR16mi_EVEX, + 3876 => Opcode::ROR16mi_ND, + 3877 => Opcode::ROR16mi_NF, + 3878 => Opcode::ROR16mi_NF_ND, + 3879 => Opcode::ROR16r1, + 3880 => Opcode::ROR16r1_EVEX, + 3881 => Opcode::ROR16r1_ND, + 3882 => Opcode::ROR16r1_NF, + 3883 => Opcode::ROR16r1_NF_ND, + 3884 => Opcode::ROR16rCL, + 3885 => Opcode::ROR16rCL_EVEX, + 3886 => Opcode::ROR16rCL_ND, + 3887 => Opcode::ROR16rCL_NF, + 3888 => Opcode::ROR16rCL_NF_ND, + 3889 => Opcode::ROR16ri, + 3890 => Opcode::ROR16ri_EVEX, + 3891 => Opcode::ROR16ri_ND, + 3892 => Opcode::ROR16ri_NF, + 3893 => Opcode::ROR16ri_NF_ND, + 3894 => Opcode::ROR32m1, + 3895 => Opcode::ROR32m1_EVEX, + 3896 => Opcode::ROR32m1_ND, + 3897 => Opcode::ROR32m1_NF, + 3898 => Opcode::ROR32m1_NF_ND, + 3899 => Opcode::ROR32mCL, + 3900 => Opcode::ROR32mCL_EVEX, + 3901 => Opcode::ROR32mCL_ND, + 3902 => Opcode::ROR32mCL_NF, + 3903 => Opcode::ROR32mCL_NF_ND, + 3904 => Opcode::ROR32mi, + 3905 => Opcode::ROR32mi_EVEX, + 3906 => Opcode::ROR32mi_ND, + 3907 => Opcode::ROR32mi_NF, + 3908 => Opcode::ROR32mi_NF_ND, + 3909 => Opcode::ROR32r1, + 3910 => Opcode::ROR32r1_EVEX, + 3911 => Opcode::ROR32r1_ND, + 3912 => Opcode::ROR32r1_NF, + 3913 => Opcode::ROR32r1_NF_ND, + 3914 => Opcode::ROR32rCL, + 3915 => Opcode::ROR32rCL_EVEX, + 3916 => Opcode::ROR32rCL_ND, + 3917 => Opcode::ROR32rCL_NF, + 3918 => Opcode::ROR32rCL_NF_ND, + 3919 => Opcode::ROR32ri, + 3920 => Opcode::ROR32ri_EVEX, + 3921 => Opcode::ROR32ri_ND, + 3922 => Opcode::ROR32ri_NF, + 3923 => Opcode::ROR32ri_NF_ND, + 3924 => Opcode::ROR64m1, + 3925 => Opcode::ROR64m1_EVEX, + 3926 => Opcode::ROR64m1_ND, + 3927 => Opcode::ROR64m1_NF, + 3928 => Opcode::ROR64m1_NF_ND, + 3929 => Opcode::ROR64mCL, + 3930 => Opcode::ROR64mCL_EVEX, + 3931 => Opcode::ROR64mCL_ND, + 3932 => Opcode::ROR64mCL_NF, + 3933 => Opcode::ROR64mCL_NF_ND, + 3934 => Opcode::ROR64mi, + 3935 => Opcode::ROR64mi_EVEX, + 3936 => Opcode::ROR64mi_ND, + 3937 => Opcode::ROR64mi_NF, + 3938 => Opcode::ROR64mi_NF_ND, + 3939 => Opcode::ROR64r1, + 3940 => Opcode::ROR64r1_EVEX, + 3941 => Opcode::ROR64r1_ND, + 3942 => Opcode::ROR64r1_NF, + 3943 => Opcode::ROR64r1_NF_ND, + 3944 => Opcode::ROR64rCL, + 3945 => Opcode::ROR64rCL_EVEX, + 3946 => Opcode::ROR64rCL_ND, + 3947 => Opcode::ROR64rCL_NF, + 3948 => Opcode::ROR64rCL_NF_ND, + 3949 => Opcode::ROR64ri, + 3950 => Opcode::ROR64ri_EVEX, + 3951 => Opcode::ROR64ri_ND, + 3952 => Opcode::ROR64ri_NF, + 3953 => Opcode::ROR64ri_NF_ND, + 3954 => Opcode::ROR8m1, + 3955 => Opcode::ROR8m1_EVEX, + 3956 => Opcode::ROR8m1_ND, + 3957 => Opcode::ROR8m1_NF, + 3958 => Opcode::ROR8m1_NF_ND, + 3959 => Opcode::ROR8mCL, + 3960 => Opcode::ROR8mCL_EVEX, + 3961 => Opcode::ROR8mCL_ND, + 3962 => Opcode::ROR8mCL_NF, + 3963 => Opcode::ROR8mCL_NF_ND, + 3964 => Opcode::ROR8mi, + 3965 => Opcode::ROR8mi_EVEX, + 3966 => Opcode::ROR8mi_ND, + 3967 => Opcode::ROR8mi_NF, + 3968 => Opcode::ROR8mi_NF_ND, + 3969 => Opcode::ROR8r1, + 3970 => Opcode::ROR8r1_EVEX, + 3971 => Opcode::ROR8r1_ND, + 3972 => Opcode::ROR8r1_NF, + 3973 => Opcode::ROR8r1_NF_ND, + 3974 => Opcode::ROR8rCL, + 3975 => Opcode::ROR8rCL_EVEX, + 3976 => Opcode::ROR8rCL_ND, + 3977 => Opcode::ROR8rCL_NF, + 3978 => Opcode::ROR8rCL_NF_ND, + 3979 => Opcode::ROR8ri, + 3980 => Opcode::ROR8ri_EVEX, + 3981 => Opcode::ROR8ri_ND, + 3982 => Opcode::ROR8ri_NF, + 3983 => Opcode::ROR8ri_NF_ND, + 3984 => Opcode::RORX32mi, + 3985 => Opcode::RORX32mi_EVEX, + 3986 => Opcode::RORX32ri, + 3987 => Opcode::RORX32ri_EVEX, + 3988 => Opcode::RORX64mi, + 3989 => Opcode::RORX64mi_EVEX, + 3990 => Opcode::RORX64ri, + 3991 => Opcode::RORX64ri_EVEX, + 3992 => Opcode::ROUNDPDmi, + 3993 => Opcode::ROUNDPDri, + 3994 => Opcode::ROUNDPSmi, + 3995 => Opcode::ROUNDPSri, + 3996 => Opcode::ROUNDSDmi, + 3997 => Opcode::ROUNDSDmi_Int, + 3998 => Opcode::ROUNDSDri, + 3999 => Opcode::ROUNDSDri_Int, + 4000 => Opcode::ROUNDSSmi, + 4001 => Opcode::ROUNDSSmi_Int, + 4002 => Opcode::ROUNDSSri, + 4003 => Opcode::ROUNDSSri_Int, + 4004 => Opcode::RSM, + 4005 => Opcode::RSQRTPSm, + 4006 => Opcode::RSQRTPSr, + 4007 => Opcode::RSQRTSSm, + 4008 => Opcode::RSQRTSSm_Int, + 4009 => Opcode::RSQRTSSr, + 4010 => Opcode::RSQRTSSr_Int, + 4011 => Opcode::RSTORSSP, + 4012 => Opcode::SAHF, + 4013 => Opcode::SALC, + 4014 => Opcode::SAR16m1, + 4015 => Opcode::SAR16m1_EVEX, + 4016 => Opcode::SAR16m1_ND, + 4017 => Opcode::SAR16m1_NF, + 4018 => Opcode::SAR16m1_NF_ND, + 4019 => Opcode::SAR16mCL, + 4020 => Opcode::SAR16mCL_EVEX, + 4021 => Opcode::SAR16mCL_ND, + 4022 => Opcode::SAR16mCL_NF, + 4023 => Opcode::SAR16mCL_NF_ND, + 4024 => Opcode::SAR16mi, + 4025 => Opcode::SAR16mi_EVEX, + 4026 => Opcode::SAR16mi_ND, + 4027 => Opcode::SAR16mi_NF, + 4028 => Opcode::SAR16mi_NF_ND, + 4029 => Opcode::SAR16r1, + 4030 => Opcode::SAR16r1_EVEX, + 4031 => Opcode::SAR16r1_ND, + 4032 => Opcode::SAR16r1_NF, + 4033 => Opcode::SAR16r1_NF_ND, + 4034 => Opcode::SAR16rCL, + 4035 => Opcode::SAR16rCL_EVEX, + 4036 => Opcode::SAR16rCL_ND, + 4037 => Opcode::SAR16rCL_NF, + 4038 => Opcode::SAR16rCL_NF_ND, + 4039 => Opcode::SAR16ri, + 4040 => Opcode::SAR16ri_EVEX, + 4041 => Opcode::SAR16ri_ND, + 4042 => Opcode::SAR16ri_NF, + 4043 => Opcode::SAR16ri_NF_ND, + 4044 => Opcode::SAR32m1, + 4045 => Opcode::SAR32m1_EVEX, + 4046 => Opcode::SAR32m1_ND, + 4047 => Opcode::SAR32m1_NF, + 4048 => Opcode::SAR32m1_NF_ND, + 4049 => Opcode::SAR32mCL, + 4050 => Opcode::SAR32mCL_EVEX, + 4051 => Opcode::SAR32mCL_ND, + 4052 => Opcode::SAR32mCL_NF, + 4053 => Opcode::SAR32mCL_NF_ND, + 4054 => Opcode::SAR32mi, + 4055 => Opcode::SAR32mi_EVEX, + 4056 => Opcode::SAR32mi_ND, + 4057 => Opcode::SAR32mi_NF, + 4058 => Opcode::SAR32mi_NF_ND, + 4059 => Opcode::SAR32r1, + 4060 => Opcode::SAR32r1_EVEX, + 4061 => Opcode::SAR32r1_ND, + 4062 => Opcode::SAR32r1_NF, + 4063 => Opcode::SAR32r1_NF_ND, + 4064 => Opcode::SAR32rCL, + 4065 => Opcode::SAR32rCL_EVEX, + 4066 => Opcode::SAR32rCL_ND, + 4067 => Opcode::SAR32rCL_NF, + 4068 => Opcode::SAR32rCL_NF_ND, + 4069 => Opcode::SAR32ri, + 4070 => Opcode::SAR32ri_EVEX, + 4071 => Opcode::SAR32ri_ND, + 4072 => Opcode::SAR32ri_NF, + 4073 => Opcode::SAR32ri_NF_ND, + 4074 => Opcode::SAR64m1, + 4075 => Opcode::SAR64m1_EVEX, + 4076 => Opcode::SAR64m1_ND, + 4077 => Opcode::SAR64m1_NF, + 4078 => Opcode::SAR64m1_NF_ND, + 4079 => Opcode::SAR64mCL, + 4080 => Opcode::SAR64mCL_EVEX, + 4081 => Opcode::SAR64mCL_ND, + 4082 => Opcode::SAR64mCL_NF, + 4083 => Opcode::SAR64mCL_NF_ND, + 4084 => Opcode::SAR64mi, + 4085 => Opcode::SAR64mi_EVEX, + 4086 => Opcode::SAR64mi_ND, + 4087 => Opcode::SAR64mi_NF, + 4088 => Opcode::SAR64mi_NF_ND, + 4089 => Opcode::SAR64r1, + 4090 => Opcode::SAR64r1_EVEX, + 4091 => Opcode::SAR64r1_ND, + 4092 => Opcode::SAR64r1_NF, + 4093 => Opcode::SAR64r1_NF_ND, + 4094 => Opcode::SAR64rCL, + 4095 => Opcode::SAR64rCL_EVEX, + 4096 => Opcode::SAR64rCL_ND, + 4097 => Opcode::SAR64rCL_NF, + 4098 => Opcode::SAR64rCL_NF_ND, + 4099 => Opcode::SAR64ri, + 4100 => Opcode::SAR64ri_EVEX, + 4101 => Opcode::SAR64ri_ND, + 4102 => Opcode::SAR64ri_NF, + 4103 => Opcode::SAR64ri_NF_ND, + 4104 => Opcode::SAR8m1, + 4105 => Opcode::SAR8m1_EVEX, + 4106 => Opcode::SAR8m1_ND, + 4107 => Opcode::SAR8m1_NF, + 4108 => Opcode::SAR8m1_NF_ND, + 4109 => Opcode::SAR8mCL, + 4110 => Opcode::SAR8mCL_EVEX, + 4111 => Opcode::SAR8mCL_ND, + 4112 => Opcode::SAR8mCL_NF, + 4113 => Opcode::SAR8mCL_NF_ND, + 4114 => Opcode::SAR8mi, + 4115 => Opcode::SAR8mi_EVEX, + 4116 => Opcode::SAR8mi_ND, + 4117 => Opcode::SAR8mi_NF, + 4118 => Opcode::SAR8mi_NF_ND, + 4119 => Opcode::SAR8r1, + 4120 => Opcode::SAR8r1_EVEX, + 4121 => Opcode::SAR8r1_ND, + 4122 => Opcode::SAR8r1_NF, + 4123 => Opcode::SAR8r1_NF_ND, + 4124 => Opcode::SAR8rCL, + 4125 => Opcode::SAR8rCL_EVEX, + 4126 => Opcode::SAR8rCL_ND, + 4127 => Opcode::SAR8rCL_NF, + 4128 => Opcode::SAR8rCL_NF_ND, + 4129 => Opcode::SAR8ri, + 4130 => Opcode::SAR8ri_EVEX, + 4131 => Opcode::SAR8ri_ND, + 4132 => Opcode::SAR8ri_NF, + 4133 => Opcode::SAR8ri_NF_ND, + 4134 => Opcode::SARX32rm, + 4135 => Opcode::SARX32rm_EVEX, + 4136 => Opcode::SARX32rr, + 4137 => Opcode::SARX32rr_EVEX, + 4138 => Opcode::SARX64rm, + 4139 => Opcode::SARX64rm_EVEX, + 4140 => Opcode::SARX64rr, + 4141 => Opcode::SARX64rr_EVEX, + 4142 => Opcode::SAVEPREVSSP, + 4143 => Opcode::SBB16i16, + 4144 => Opcode::SBB16mi, + 4145 => Opcode::SBB16mi8, + 4146 => Opcode::SBB16mi8_EVEX, + 4147 => Opcode::SBB16mi8_ND, + 4148 => Opcode::SBB16mi_EVEX, + 4149 => Opcode::SBB16mi_ND, + 4150 => Opcode::SBB16mr, + 4151 => Opcode::SBB16mr_EVEX, + 4152 => Opcode::SBB16mr_ND, + 4153 => Opcode::SBB16ri, + 4154 => Opcode::SBB16ri8, + 4155 => Opcode::SBB16ri8_EVEX, + 4156 => Opcode::SBB16ri8_ND, + 4157 => Opcode::SBB16ri_EVEX, + 4158 => Opcode::SBB16ri_ND, + 4159 => Opcode::SBB16rm, + 4160 => Opcode::SBB16rm_EVEX, + 4161 => Opcode::SBB16rm_ND, + 4162 => Opcode::SBB16rr, + 4163 => Opcode::SBB16rr_EVEX, + 4164 => Opcode::SBB16rr_EVEX_REV, + 4165 => Opcode::SBB16rr_ND, + 4166 => Opcode::SBB16rr_ND_REV, + 4167 => Opcode::SBB16rr_REV, + 4168 => Opcode::SBB32i32, + 4169 => Opcode::SBB32mi, + 4170 => Opcode::SBB32mi8, + 4171 => Opcode::SBB32mi8_EVEX, + 4172 => Opcode::SBB32mi8_ND, + 4173 => Opcode::SBB32mi_EVEX, + 4174 => Opcode::SBB32mi_ND, + 4175 => Opcode::SBB32mr, + 4176 => Opcode::SBB32mr_EVEX, + 4177 => Opcode::SBB32mr_ND, + 4178 => Opcode::SBB32ri, + 4179 => Opcode::SBB32ri8, + 4180 => Opcode::SBB32ri8_EVEX, + 4181 => Opcode::SBB32ri8_ND, + 4182 => Opcode::SBB32ri_EVEX, + 4183 => Opcode::SBB32ri_ND, + 4184 => Opcode::SBB32rm, + 4185 => Opcode::SBB32rm_EVEX, + 4186 => Opcode::SBB32rm_ND, + 4187 => Opcode::SBB32rr, + 4188 => Opcode::SBB32rr_EVEX, + 4189 => Opcode::SBB32rr_EVEX_REV, + 4190 => Opcode::SBB32rr_ND, + 4191 => Opcode::SBB32rr_ND_REV, + 4192 => Opcode::SBB32rr_REV, + 4193 => Opcode::SBB64i32, + 4194 => Opcode::SBB64mi32, + 4195 => Opcode::SBB64mi32_EVEX, + 4196 => Opcode::SBB64mi32_ND, + 4197 => Opcode::SBB64mi8, + 4198 => Opcode::SBB64mi8_EVEX, + 4199 => Opcode::SBB64mi8_ND, + 4200 => Opcode::SBB64mr, + 4201 => Opcode::SBB64mr_EVEX, + 4202 => Opcode::SBB64mr_ND, + 4203 => Opcode::SBB64ri32, + 4204 => Opcode::SBB64ri32_EVEX, + 4205 => Opcode::SBB64ri32_ND, + 4206 => Opcode::SBB64ri8, + 4207 => Opcode::SBB64ri8_EVEX, + 4208 => Opcode::SBB64ri8_ND, + 4209 => Opcode::SBB64rm, + 4210 => Opcode::SBB64rm_EVEX, + 4211 => Opcode::SBB64rm_ND, + 4212 => Opcode::SBB64rr, + 4213 => Opcode::SBB64rr_EVEX, + 4214 => Opcode::SBB64rr_EVEX_REV, + 4215 => Opcode::SBB64rr_ND, + 4216 => Opcode::SBB64rr_ND_REV, + 4217 => Opcode::SBB64rr_REV, + 4218 => Opcode::SBB8i8, + 4219 => Opcode::SBB8mi, + 4220 => Opcode::SBB8mi8, + 4221 => Opcode::SBB8mi_EVEX, + 4222 => Opcode::SBB8mi_ND, + 4223 => Opcode::SBB8mr, + 4224 => Opcode::SBB8mr_EVEX, + 4225 => Opcode::SBB8mr_ND, + 4226 => Opcode::SBB8ri, + 4227 => Opcode::SBB8ri8, + 4228 => Opcode::SBB8ri_EVEX, + 4229 => Opcode::SBB8ri_ND, + 4230 => Opcode::SBB8rm, + 4231 => Opcode::SBB8rm_EVEX, + 4232 => Opcode::SBB8rm_ND, + 4233 => Opcode::SBB8rr, + 4234 => Opcode::SBB8rr_EVEX, + 4235 => Opcode::SBB8rr_EVEX_REV, + 4236 => Opcode::SBB8rr_ND, + 4237 => Opcode::SBB8rr_ND_REV, + 4238 => Opcode::SBB8rr_REV, + 4239 => Opcode::SCASB, + 4240 => Opcode::SCASL, + 4241 => Opcode::SCASQ, + 4242 => Opcode::SCASW, + 4243 => Opcode::SEAMCALL, + 4244 => Opcode::SEAMOPS, + 4245 => Opcode::SEAMRET, + 4246 => Opcode::SEG_ALLOCA_32, + 4247 => Opcode::SEG_ALLOCA_64, + 4248 => Opcode::SENDUIPI, + 4249 => Opcode::SERIALIZE, + 4250 => Opcode::SETCCm, + 4251 => Opcode::SETCCm_EVEX, + 4252 => Opcode::SETCCr, + 4253 => Opcode::SETCCr_EVEX, + 4254 => Opcode::SETSSBSY, + 4255 => Opcode::SETZUCCm, + 4256 => Opcode::SETZUCCr, + 4257 => Opcode::SFENCE, + 4258 => Opcode::SGDT16m, + 4259 => Opcode::SGDT32m, + 4260 => Opcode::SGDT64m, + 4261 => Opcode::SHA1MSG1rm, + 4262 => Opcode::SHA1MSG1rr, + 4263 => Opcode::SHA1MSG2rm, + 4264 => Opcode::SHA1MSG2rr, + 4265 => Opcode::SHA1NEXTErm, + 4266 => Opcode::SHA1NEXTErr, + 4267 => Opcode::SHA1RNDS4rmi, + 4268 => Opcode::SHA1RNDS4rri, + 4269 => Opcode::SHA256MSG1rm, + 4270 => Opcode::SHA256MSG1rr, + 4271 => Opcode::SHA256MSG2rm, + 4272 => Opcode::SHA256MSG2rr, + 4273 => Opcode::SHA256RNDS2rm, + 4274 => Opcode::SHA256RNDS2rr, + 4275 => Opcode::SHL16m1, + 4276 => Opcode::SHL16m1_EVEX, + 4277 => Opcode::SHL16m1_ND, + 4278 => Opcode::SHL16m1_NF, + 4279 => Opcode::SHL16m1_NF_ND, + 4280 => Opcode::SHL16mCL, + 4281 => Opcode::SHL16mCL_EVEX, + 4282 => Opcode::SHL16mCL_ND, + 4283 => Opcode::SHL16mCL_NF, + 4284 => Opcode::SHL16mCL_NF_ND, + 4285 => Opcode::SHL16mi, + 4286 => Opcode::SHL16mi_EVEX, + 4287 => Opcode::SHL16mi_ND, + 4288 => Opcode::SHL16mi_NF, + 4289 => Opcode::SHL16mi_NF_ND, + 4290 => Opcode::SHL16r1, + 4291 => Opcode::SHL16r1_EVEX, + 4292 => Opcode::SHL16r1_ND, + 4293 => Opcode::SHL16r1_NF, + 4294 => Opcode::SHL16r1_NF_ND, + 4295 => Opcode::SHL16rCL, + 4296 => Opcode::SHL16rCL_EVEX, + 4297 => Opcode::SHL16rCL_ND, + 4298 => Opcode::SHL16rCL_NF, + 4299 => Opcode::SHL16rCL_NF_ND, + 4300 => Opcode::SHL16ri, + 4301 => Opcode::SHL16ri_EVEX, + 4302 => Opcode::SHL16ri_ND, + 4303 => Opcode::SHL16ri_NF, + 4304 => Opcode::SHL16ri_NF_ND, + 4305 => Opcode::SHL32m1, + 4306 => Opcode::SHL32m1_EVEX, + 4307 => Opcode::SHL32m1_ND, + 4308 => Opcode::SHL32m1_NF, + 4309 => Opcode::SHL32m1_NF_ND, + 4310 => Opcode::SHL32mCL, + 4311 => Opcode::SHL32mCL_EVEX, + 4312 => Opcode::SHL32mCL_ND, + 4313 => Opcode::SHL32mCL_NF, + 4314 => Opcode::SHL32mCL_NF_ND, + 4315 => Opcode::SHL32mi, + 4316 => Opcode::SHL32mi_EVEX, + 4317 => Opcode::SHL32mi_ND, + 4318 => Opcode::SHL32mi_NF, + 4319 => Opcode::SHL32mi_NF_ND, + 4320 => Opcode::SHL32r1, + 4321 => Opcode::SHL32r1_EVEX, + 4322 => Opcode::SHL32r1_ND, + 4323 => Opcode::SHL32r1_NF, + 4324 => Opcode::SHL32r1_NF_ND, + 4325 => Opcode::SHL32rCL, + 4326 => Opcode::SHL32rCL_EVEX, + 4327 => Opcode::SHL32rCL_ND, + 4328 => Opcode::SHL32rCL_NF, + 4329 => Opcode::SHL32rCL_NF_ND, + 4330 => Opcode::SHL32ri, + 4331 => Opcode::SHL32ri_EVEX, + 4332 => Opcode::SHL32ri_ND, + 4333 => Opcode::SHL32ri_NF, + 4334 => Opcode::SHL32ri_NF_ND, + 4335 => Opcode::SHL64m1, + 4336 => Opcode::SHL64m1_EVEX, + 4337 => Opcode::SHL64m1_ND, + 4338 => Opcode::SHL64m1_NF, + 4339 => Opcode::SHL64m1_NF_ND, + 4340 => Opcode::SHL64mCL, + 4341 => Opcode::SHL64mCL_EVEX, + 4342 => Opcode::SHL64mCL_ND, + 4343 => Opcode::SHL64mCL_NF, + 4344 => Opcode::SHL64mCL_NF_ND, + 4345 => Opcode::SHL64mi, + 4346 => Opcode::SHL64mi_EVEX, + 4347 => Opcode::SHL64mi_ND, + 4348 => Opcode::SHL64mi_NF, + 4349 => Opcode::SHL64mi_NF_ND, + 4350 => Opcode::SHL64r1, + 4351 => Opcode::SHL64r1_EVEX, + 4352 => Opcode::SHL64r1_ND, + 4353 => Opcode::SHL64r1_NF, + 4354 => Opcode::SHL64r1_NF_ND, + 4355 => Opcode::SHL64rCL, + 4356 => Opcode::SHL64rCL_EVEX, + 4357 => Opcode::SHL64rCL_ND, + 4358 => Opcode::SHL64rCL_NF, + 4359 => Opcode::SHL64rCL_NF_ND, + 4360 => Opcode::SHL64ri, + 4361 => Opcode::SHL64ri_EVEX, + 4362 => Opcode::SHL64ri_ND, + 4363 => Opcode::SHL64ri_NF, + 4364 => Opcode::SHL64ri_NF_ND, + 4365 => Opcode::SHL8m1, + 4366 => Opcode::SHL8m1_EVEX, + 4367 => Opcode::SHL8m1_ND, + 4368 => Opcode::SHL8m1_NF, + 4369 => Opcode::SHL8m1_NF_ND, + 4370 => Opcode::SHL8mCL, + 4371 => Opcode::SHL8mCL_EVEX, + 4372 => Opcode::SHL8mCL_ND, + 4373 => Opcode::SHL8mCL_NF, + 4374 => Opcode::SHL8mCL_NF_ND, + 4375 => Opcode::SHL8mi, + 4376 => Opcode::SHL8mi_EVEX, + 4377 => Opcode::SHL8mi_ND, + 4378 => Opcode::SHL8mi_NF, + 4379 => Opcode::SHL8mi_NF_ND, + 4380 => Opcode::SHL8r1, + 4381 => Opcode::SHL8r1_EVEX, + 4382 => Opcode::SHL8r1_ND, + 4383 => Opcode::SHL8r1_NF, + 4384 => Opcode::SHL8r1_NF_ND, + 4385 => Opcode::SHL8rCL, + 4386 => Opcode::SHL8rCL_EVEX, + 4387 => Opcode::SHL8rCL_ND, + 4388 => Opcode::SHL8rCL_NF, + 4389 => Opcode::SHL8rCL_NF_ND, + 4390 => Opcode::SHL8ri, + 4391 => Opcode::SHL8ri_EVEX, + 4392 => Opcode::SHL8ri_ND, + 4393 => Opcode::SHL8ri_NF, + 4394 => Opcode::SHL8ri_NF_ND, + 4395 => Opcode::SHLD16mrCL, + 4396 => Opcode::SHLD16mrCL_EVEX, + 4397 => Opcode::SHLD16mrCL_ND, + 4398 => Opcode::SHLD16mrCL_NF, + 4399 => Opcode::SHLD16mrCL_NF_ND, + 4400 => Opcode::SHLD16mri8, + 4401 => Opcode::SHLD16mri8_EVEX, + 4402 => Opcode::SHLD16mri8_ND, + 4403 => Opcode::SHLD16mri8_NF, + 4404 => Opcode::SHLD16mri8_NF_ND, + 4405 => Opcode::SHLD16rrCL, + 4406 => Opcode::SHLD16rrCL_EVEX, + 4407 => Opcode::SHLD16rrCL_ND, + 4408 => Opcode::SHLD16rrCL_NF, + 4409 => Opcode::SHLD16rrCL_NF_ND, + 4410 => Opcode::SHLD16rri8, + 4411 => Opcode::SHLD16rri8_EVEX, + 4412 => Opcode::SHLD16rri8_ND, + 4413 => Opcode::SHLD16rri8_NF, + 4414 => Opcode::SHLD16rri8_NF_ND, + 4415 => Opcode::SHLD32mrCL, + 4416 => Opcode::SHLD32mrCL_EVEX, + 4417 => Opcode::SHLD32mrCL_ND, + 4418 => Opcode::SHLD32mrCL_NF, + 4419 => Opcode::SHLD32mrCL_NF_ND, + 4420 => Opcode::SHLD32mri8, + 4421 => Opcode::SHLD32mri8_EVEX, + 4422 => Opcode::SHLD32mri8_ND, + 4423 => Opcode::SHLD32mri8_NF, + 4424 => Opcode::SHLD32mri8_NF_ND, + 4425 => Opcode::SHLD32rrCL, + 4426 => Opcode::SHLD32rrCL_EVEX, + 4427 => Opcode::SHLD32rrCL_ND, + 4428 => Opcode::SHLD32rrCL_NF, + 4429 => Opcode::SHLD32rrCL_NF_ND, + 4430 => Opcode::SHLD32rri8, + 4431 => Opcode::SHLD32rri8_EVEX, + 4432 => Opcode::SHLD32rri8_ND, + 4433 => Opcode::SHLD32rri8_NF, + 4434 => Opcode::SHLD32rri8_NF_ND, + 4435 => Opcode::SHLD64mrCL, + 4436 => Opcode::SHLD64mrCL_EVEX, + 4437 => Opcode::SHLD64mrCL_ND, + 4438 => Opcode::SHLD64mrCL_NF, + 4439 => Opcode::SHLD64mrCL_NF_ND, + 4440 => Opcode::SHLD64mri8, + 4441 => Opcode::SHLD64mri8_EVEX, + 4442 => Opcode::SHLD64mri8_ND, + 4443 => Opcode::SHLD64mri8_NF, + 4444 => Opcode::SHLD64mri8_NF_ND, + 4445 => Opcode::SHLD64rrCL, + 4446 => Opcode::SHLD64rrCL_EVEX, + 4447 => Opcode::SHLD64rrCL_ND, + 4448 => Opcode::SHLD64rrCL_NF, + 4449 => Opcode::SHLD64rrCL_NF_ND, + 4450 => Opcode::SHLD64rri8, + 4451 => Opcode::SHLD64rri8_EVEX, + 4452 => Opcode::SHLD64rri8_ND, + 4453 => Opcode::SHLD64rri8_NF, + 4454 => Opcode::SHLD64rri8_NF_ND, + 4455 => Opcode::SHLX32rm, + 4456 => Opcode::SHLX32rm_EVEX, + 4457 => Opcode::SHLX32rr, + 4458 => Opcode::SHLX32rr_EVEX, + 4459 => Opcode::SHLX64rm, + 4460 => Opcode::SHLX64rm_EVEX, + 4461 => Opcode::SHLX64rr, + 4462 => Opcode::SHLX64rr_EVEX, + 4463 => Opcode::SHR16m1, + 4464 => Opcode::SHR16m1_EVEX, + 4465 => Opcode::SHR16m1_ND, + 4466 => Opcode::SHR16m1_NF, + 4467 => Opcode::SHR16m1_NF_ND, + 4468 => Opcode::SHR16mCL, + 4469 => Opcode::SHR16mCL_EVEX, + 4470 => Opcode::SHR16mCL_ND, + 4471 => Opcode::SHR16mCL_NF, + 4472 => Opcode::SHR16mCL_NF_ND, + 4473 => Opcode::SHR16mi, + 4474 => Opcode::SHR16mi_EVEX, + 4475 => Opcode::SHR16mi_ND, + 4476 => Opcode::SHR16mi_NF, + 4477 => Opcode::SHR16mi_NF_ND, + 4478 => Opcode::SHR16r1, + 4479 => Opcode::SHR16r1_EVEX, + 4480 => Opcode::SHR16r1_ND, + 4481 => Opcode::SHR16r1_NF, + 4482 => Opcode::SHR16r1_NF_ND, + 4483 => Opcode::SHR16rCL, + 4484 => Opcode::SHR16rCL_EVEX, + 4485 => Opcode::SHR16rCL_ND, + 4486 => Opcode::SHR16rCL_NF, + 4487 => Opcode::SHR16rCL_NF_ND, + 4488 => Opcode::SHR16ri, + 4489 => Opcode::SHR16ri_EVEX, + 4490 => Opcode::SHR16ri_ND, + 4491 => Opcode::SHR16ri_NF, + 4492 => Opcode::SHR16ri_NF_ND, + 4493 => Opcode::SHR32m1, + 4494 => Opcode::SHR32m1_EVEX, + 4495 => Opcode::SHR32m1_ND, + 4496 => Opcode::SHR32m1_NF, + 4497 => Opcode::SHR32m1_NF_ND, + 4498 => Opcode::SHR32mCL, + 4499 => Opcode::SHR32mCL_EVEX, + 4500 => Opcode::SHR32mCL_ND, + 4501 => Opcode::SHR32mCL_NF, + 4502 => Opcode::SHR32mCL_NF_ND, + 4503 => Opcode::SHR32mi, + 4504 => Opcode::SHR32mi_EVEX, + 4505 => Opcode::SHR32mi_ND, + 4506 => Opcode::SHR32mi_NF, + 4507 => Opcode::SHR32mi_NF_ND, + 4508 => Opcode::SHR32r1, + 4509 => Opcode::SHR32r1_EVEX, + 4510 => Opcode::SHR32r1_ND, + 4511 => Opcode::SHR32r1_NF, + 4512 => Opcode::SHR32r1_NF_ND, + 4513 => Opcode::SHR32rCL, + 4514 => Opcode::SHR32rCL_EVEX, + 4515 => Opcode::SHR32rCL_ND, + 4516 => Opcode::SHR32rCL_NF, + 4517 => Opcode::SHR32rCL_NF_ND, + 4518 => Opcode::SHR32ri, + 4519 => Opcode::SHR32ri_EVEX, + 4520 => Opcode::SHR32ri_ND, + 4521 => Opcode::SHR32ri_NF, + 4522 => Opcode::SHR32ri_NF_ND, + 4523 => Opcode::SHR64m1, + 4524 => Opcode::SHR64m1_EVEX, + 4525 => Opcode::SHR64m1_ND, + 4526 => Opcode::SHR64m1_NF, + 4527 => Opcode::SHR64m1_NF_ND, + 4528 => Opcode::SHR64mCL, + 4529 => Opcode::SHR64mCL_EVEX, + 4530 => Opcode::SHR64mCL_ND, + 4531 => Opcode::SHR64mCL_NF, + 4532 => Opcode::SHR64mCL_NF_ND, + 4533 => Opcode::SHR64mi, + 4534 => Opcode::SHR64mi_EVEX, + 4535 => Opcode::SHR64mi_ND, + 4536 => Opcode::SHR64mi_NF, + 4537 => Opcode::SHR64mi_NF_ND, + 4538 => Opcode::SHR64r1, + 4539 => Opcode::SHR64r1_EVEX, + 4540 => Opcode::SHR64r1_ND, + 4541 => Opcode::SHR64r1_NF, + 4542 => Opcode::SHR64r1_NF_ND, + 4543 => Opcode::SHR64rCL, + 4544 => Opcode::SHR64rCL_EVEX, + 4545 => Opcode::SHR64rCL_ND, + 4546 => Opcode::SHR64rCL_NF, + 4547 => Opcode::SHR64rCL_NF_ND, + 4548 => Opcode::SHR64ri, + 4549 => Opcode::SHR64ri_EVEX, + 4550 => Opcode::SHR64ri_ND, + 4551 => Opcode::SHR64ri_NF, + 4552 => Opcode::SHR64ri_NF_ND, + 4553 => Opcode::SHR8m1, + 4554 => Opcode::SHR8m1_EVEX, + 4555 => Opcode::SHR8m1_ND, + 4556 => Opcode::SHR8m1_NF, + 4557 => Opcode::SHR8m1_NF_ND, + 4558 => Opcode::SHR8mCL, + 4559 => Opcode::SHR8mCL_EVEX, + 4560 => Opcode::SHR8mCL_ND, + 4561 => Opcode::SHR8mCL_NF, + 4562 => Opcode::SHR8mCL_NF_ND, + 4563 => Opcode::SHR8mi, + 4564 => Opcode::SHR8mi_EVEX, + 4565 => Opcode::SHR8mi_ND, + 4566 => Opcode::SHR8mi_NF, + 4567 => Opcode::SHR8mi_NF_ND, + 4568 => Opcode::SHR8r1, + 4569 => Opcode::SHR8r1_EVEX, + 4570 => Opcode::SHR8r1_ND, + 4571 => Opcode::SHR8r1_NF, + 4572 => Opcode::SHR8r1_NF_ND, + 4573 => Opcode::SHR8rCL, + 4574 => Opcode::SHR8rCL_EVEX, + 4575 => Opcode::SHR8rCL_ND, + 4576 => Opcode::SHR8rCL_NF, + 4577 => Opcode::SHR8rCL_NF_ND, + 4578 => Opcode::SHR8ri, + 4579 => Opcode::SHR8ri_EVEX, + 4580 => Opcode::SHR8ri_ND, + 4581 => Opcode::SHR8ri_NF, + 4582 => Opcode::SHR8ri_NF_ND, + 4583 => Opcode::SHRD16mrCL, + 4584 => Opcode::SHRD16mrCL_EVEX, + 4585 => Opcode::SHRD16mrCL_ND, + 4586 => Opcode::SHRD16mrCL_NF, + 4587 => Opcode::SHRD16mrCL_NF_ND, + 4588 => Opcode::SHRD16mri8, + 4589 => Opcode::SHRD16mri8_EVEX, + 4590 => Opcode::SHRD16mri8_ND, + 4591 => Opcode::SHRD16mri8_NF, + 4592 => Opcode::SHRD16mri8_NF_ND, + 4593 => Opcode::SHRD16rrCL, + 4594 => Opcode::SHRD16rrCL_EVEX, + 4595 => Opcode::SHRD16rrCL_ND, + 4596 => Opcode::SHRD16rrCL_NF, + 4597 => Opcode::SHRD16rrCL_NF_ND, + 4598 => Opcode::SHRD16rri8, + 4599 => Opcode::SHRD16rri8_EVEX, + 4600 => Opcode::SHRD16rri8_ND, + 4601 => Opcode::SHRD16rri8_NF, + 4602 => Opcode::SHRD16rri8_NF_ND, + 4603 => Opcode::SHRD32mrCL, + 4604 => Opcode::SHRD32mrCL_EVEX, + 4605 => Opcode::SHRD32mrCL_ND, + 4606 => Opcode::SHRD32mrCL_NF, + 4607 => Opcode::SHRD32mrCL_NF_ND, + 4608 => Opcode::SHRD32mri8, + 4609 => Opcode::SHRD32mri8_EVEX, + 4610 => Opcode::SHRD32mri8_ND, + 4611 => Opcode::SHRD32mri8_NF, + 4612 => Opcode::SHRD32mri8_NF_ND, + 4613 => Opcode::SHRD32rrCL, + 4614 => Opcode::SHRD32rrCL_EVEX, + 4615 => Opcode::SHRD32rrCL_ND, + 4616 => Opcode::SHRD32rrCL_NF, + 4617 => Opcode::SHRD32rrCL_NF_ND, + 4618 => Opcode::SHRD32rri8, + 4619 => Opcode::SHRD32rri8_EVEX, + 4620 => Opcode::SHRD32rri8_ND, + 4621 => Opcode::SHRD32rri8_NF, + 4622 => Opcode::SHRD32rri8_NF_ND, + 4623 => Opcode::SHRD64mrCL, + 4624 => Opcode::SHRD64mrCL_EVEX, + 4625 => Opcode::SHRD64mrCL_ND, + 4626 => Opcode::SHRD64mrCL_NF, + 4627 => Opcode::SHRD64mrCL_NF_ND, + 4628 => Opcode::SHRD64mri8, + 4629 => Opcode::SHRD64mri8_EVEX, + 4630 => Opcode::SHRD64mri8_ND, + 4631 => Opcode::SHRD64mri8_NF, + 4632 => Opcode::SHRD64mri8_NF_ND, + 4633 => Opcode::SHRD64rrCL, + 4634 => Opcode::SHRD64rrCL_EVEX, + 4635 => Opcode::SHRD64rrCL_ND, + 4636 => Opcode::SHRD64rrCL_NF, + 4637 => Opcode::SHRD64rrCL_NF_ND, + 4638 => Opcode::SHRD64rri8, + 4639 => Opcode::SHRD64rri8_EVEX, + 4640 => Opcode::SHRD64rri8_ND, + 4641 => Opcode::SHRD64rri8_NF, + 4642 => Opcode::SHRD64rri8_NF_ND, + 4643 => Opcode::SHRX32rm, + 4644 => Opcode::SHRX32rm_EVEX, + 4645 => Opcode::SHRX32rr, + 4646 => Opcode::SHRX32rr_EVEX, + 4647 => Opcode::SHRX64rm, + 4648 => Opcode::SHRX64rm_EVEX, + 4649 => Opcode::SHRX64rr, + 4650 => Opcode::SHRX64rr_EVEX, + 4651 => Opcode::SHUFPDrmi, + 4652 => Opcode::SHUFPDrri, + 4653 => Opcode::SHUFPSrmi, + 4654 => Opcode::SHUFPSrri, + 4655 => Opcode::SIDT16m, + 4656 => Opcode::SIDT32m, + 4657 => Opcode::SIDT64m, + 4658 => Opcode::SKINIT, + 4659 => Opcode::SLDT16m, + 4660 => Opcode::SLDT16r, + 4661 => Opcode::SLDT32r, + 4662 => Opcode::SLDT64r, + 4663 => Opcode::SLWPCB, + 4664 => Opcode::SLWPCB64, + 4665 => Opcode::SMSW16m, + 4666 => Opcode::SMSW16r, + 4667 => Opcode::SMSW32r, + 4668 => Opcode::SMSW64r, + 4669 => Opcode::SQRTPDm, + 4670 => Opcode::SQRTPDr, + 4671 => Opcode::SQRTPSm, + 4672 => Opcode::SQRTPSr, + 4673 => Opcode::SQRTSDm, + 4674 => Opcode::SQRTSDm_Int, + 4675 => Opcode::SQRTSDr, + 4676 => Opcode::SQRTSDr_Int, + 4677 => Opcode::SQRTSSm, + 4678 => Opcode::SQRTSSm_Int, + 4679 => Opcode::SQRTSSr, + 4680 => Opcode::SQRTSSr_Int, + 4681 => Opcode::SQRT_F, + 4682 => Opcode::SQRT_Fp32, + 4683 => Opcode::SQRT_Fp64, + 4684 => Opcode::SQRT_Fp80, + 4685 => Opcode::SS_PREFIX, + 4686 => Opcode::STAC, + 4687 => Opcode::STACKALLOC_W_PROBING, + 4688 => Opcode::STC, + 4689 => Opcode::STD, + 4690 => Opcode::STGI, + 4691 => Opcode::STI, + 4692 => Opcode::STMXCSR, + 4693 => Opcode::STOSB, + 4694 => Opcode::STOSL, + 4695 => Opcode::STOSQ, + 4696 => Opcode::STOSW, + 4697 => Opcode::STR16r, + 4698 => Opcode::STR32r, + 4699 => Opcode::STR64r, + 4700 => Opcode::STRm, + 4701 => Opcode::STTILECFG, + 4702 => Opcode::STTILECFG_EVEX, + 4703 => Opcode::STUI, + 4704 => Opcode::ST_F32m, + 4705 => Opcode::ST_F64m, + 4706 => Opcode::ST_FP32m, + 4707 => Opcode::ST_FP64m, + 4708 => Opcode::ST_FP80m, + 4709 => Opcode::ST_FPrr, + 4710 => Opcode::ST_Fp32m, + 4711 => Opcode::ST_Fp64m, + 4712 => Opcode::ST_Fp64m32, + 4713 => Opcode::ST_Fp80m32, + 4714 => Opcode::ST_Fp80m64, + 4715 => Opcode::ST_FpP32m, + 4716 => Opcode::ST_FpP64m, + 4717 => Opcode::ST_FpP64m32, + 4718 => Opcode::ST_FpP80m, + 4719 => Opcode::ST_FpP80m32, + 4720 => Opcode::ST_FpP80m64, + 4721 => Opcode::ST_Frr, + 4722 => Opcode::SUB16i16, + 4723 => Opcode::SUB16mi, + 4724 => Opcode::SUB16mi8, + 4725 => Opcode::SUB16mi8_EVEX, + 4726 => Opcode::SUB16mi8_ND, + 4727 => Opcode::SUB16mi8_NF, + 4728 => Opcode::SUB16mi8_NF_ND, + 4729 => Opcode::SUB16mi_EVEX, + 4730 => Opcode::SUB16mi_ND, + 4731 => Opcode::SUB16mi_NF, + 4732 => Opcode::SUB16mi_NF_ND, + 4733 => Opcode::SUB16mr, + 4734 => Opcode::SUB16mr_EVEX, + 4735 => Opcode::SUB16mr_ND, + 4736 => Opcode::SUB16mr_NF, + 4737 => Opcode::SUB16mr_NF_ND, + 4738 => Opcode::SUB16ri, + 4739 => Opcode::SUB16ri8, + 4740 => Opcode::SUB16ri8_EVEX, + 4741 => Opcode::SUB16ri8_ND, + 4742 => Opcode::SUB16ri8_NF, + 4743 => Opcode::SUB16ri8_NF_ND, + 4744 => Opcode::SUB16ri_EVEX, + 4745 => Opcode::SUB16ri_ND, + 4746 => Opcode::SUB16ri_NF, + 4747 => Opcode::SUB16ri_NF_ND, + 4748 => Opcode::SUB16rm, + 4749 => Opcode::SUB16rm_EVEX, + 4750 => Opcode::SUB16rm_ND, + 4751 => Opcode::SUB16rm_NF, + 4752 => Opcode::SUB16rm_NF_ND, + 4753 => Opcode::SUB16rr, + 4754 => Opcode::SUB16rr_EVEX, + 4755 => Opcode::SUB16rr_EVEX_REV, + 4756 => Opcode::SUB16rr_ND, + 4757 => Opcode::SUB16rr_ND_REV, + 4758 => Opcode::SUB16rr_NF, + 4759 => Opcode::SUB16rr_NF_ND, + 4760 => Opcode::SUB16rr_NF_ND_REV, + 4761 => Opcode::SUB16rr_NF_REV, + 4762 => Opcode::SUB16rr_REV, + 4763 => Opcode::SUB32i32, + 4764 => Opcode::SUB32mi, + 4765 => Opcode::SUB32mi8, + 4766 => Opcode::SUB32mi8_EVEX, + 4767 => Opcode::SUB32mi8_ND, + 4768 => Opcode::SUB32mi8_NF, + 4769 => Opcode::SUB32mi8_NF_ND, + 4770 => Opcode::SUB32mi_EVEX, + 4771 => Opcode::SUB32mi_ND, + 4772 => Opcode::SUB32mi_NF, + 4773 => Opcode::SUB32mi_NF_ND, + 4774 => Opcode::SUB32mr, + 4775 => Opcode::SUB32mr_EVEX, + 4776 => Opcode::SUB32mr_ND, + 4777 => Opcode::SUB32mr_NF, + 4778 => Opcode::SUB32mr_NF_ND, + 4779 => Opcode::SUB32ri, + 4780 => Opcode::SUB32ri8, + 4781 => Opcode::SUB32ri8_EVEX, + 4782 => Opcode::SUB32ri8_ND, + 4783 => Opcode::SUB32ri8_NF, + 4784 => Opcode::SUB32ri8_NF_ND, + 4785 => Opcode::SUB32ri_EVEX, + 4786 => Opcode::SUB32ri_ND, + 4787 => Opcode::SUB32ri_NF, + 4788 => Opcode::SUB32ri_NF_ND, + 4789 => Opcode::SUB32rm, + 4790 => Opcode::SUB32rm_EVEX, + 4791 => Opcode::SUB32rm_ND, + 4792 => Opcode::SUB32rm_NF, + 4793 => Opcode::SUB32rm_NF_ND, + 4794 => Opcode::SUB32rr, + 4795 => Opcode::SUB32rr_EVEX, + 4796 => Opcode::SUB32rr_EVEX_REV, + 4797 => Opcode::SUB32rr_ND, + 4798 => Opcode::SUB32rr_ND_REV, + 4799 => Opcode::SUB32rr_NF, + 4800 => Opcode::SUB32rr_NF_ND, + 4801 => Opcode::SUB32rr_NF_ND_REV, + 4802 => Opcode::SUB32rr_NF_REV, + 4803 => Opcode::SUB32rr_REV, + 4804 => Opcode::SUB64i32, + 4805 => Opcode::SUB64mi32, + 4806 => Opcode::SUB64mi32_EVEX, + 4807 => Opcode::SUB64mi32_ND, + 4808 => Opcode::SUB64mi32_NF, + 4809 => Opcode::SUB64mi32_NF_ND, + 4810 => Opcode::SUB64mi8, + 4811 => Opcode::SUB64mi8_EVEX, + 4812 => Opcode::SUB64mi8_ND, + 4813 => Opcode::SUB64mi8_NF, + 4814 => Opcode::SUB64mi8_NF_ND, + 4815 => Opcode::SUB64mr, + 4816 => Opcode::SUB64mr_EVEX, + 4817 => Opcode::SUB64mr_ND, + 4818 => Opcode::SUB64mr_NF, + 4819 => Opcode::SUB64mr_NF_ND, + 4820 => Opcode::SUB64ri32, + 4821 => Opcode::SUB64ri32_EVEX, + 4822 => Opcode::SUB64ri32_ND, + 4823 => Opcode::SUB64ri32_NF, + 4824 => Opcode::SUB64ri32_NF_ND, + 4825 => Opcode::SUB64ri8, + 4826 => Opcode::SUB64ri8_EVEX, + 4827 => Opcode::SUB64ri8_ND, + 4828 => Opcode::SUB64ri8_NF, + 4829 => Opcode::SUB64ri8_NF_ND, + 4830 => Opcode::SUB64rm, + 4831 => Opcode::SUB64rm_EVEX, + 4832 => Opcode::SUB64rm_ND, + 4833 => Opcode::SUB64rm_NF, + 4834 => Opcode::SUB64rm_NF_ND, + 4835 => Opcode::SUB64rr, + 4836 => Opcode::SUB64rr_EVEX, + 4837 => Opcode::SUB64rr_EVEX_REV, + 4838 => Opcode::SUB64rr_ND, + 4839 => Opcode::SUB64rr_ND_REV, + 4840 => Opcode::SUB64rr_NF, + 4841 => Opcode::SUB64rr_NF_ND, + 4842 => Opcode::SUB64rr_NF_ND_REV, + 4843 => Opcode::SUB64rr_NF_REV, + 4844 => Opcode::SUB64rr_REV, + 4845 => Opcode::SUB8i8, + 4846 => Opcode::SUB8mi, + 4847 => Opcode::SUB8mi8, + 4848 => Opcode::SUB8mi_EVEX, + 4849 => Opcode::SUB8mi_ND, + 4850 => Opcode::SUB8mi_NF, + 4851 => Opcode::SUB8mi_NF_ND, + 4852 => Opcode::SUB8mr, + 4853 => Opcode::SUB8mr_EVEX, + 4854 => Opcode::SUB8mr_ND, + 4855 => Opcode::SUB8mr_NF, + 4856 => Opcode::SUB8mr_NF_ND, + 4857 => Opcode::SUB8ri, + 4858 => Opcode::SUB8ri8, + 4859 => Opcode::SUB8ri_EVEX, + 4860 => Opcode::SUB8ri_ND, + 4861 => Opcode::SUB8ri_NF, + 4862 => Opcode::SUB8ri_NF_ND, + 4863 => Opcode::SUB8rm, + 4864 => Opcode::SUB8rm_EVEX, + 4865 => Opcode::SUB8rm_ND, + 4866 => Opcode::SUB8rm_NF, + 4867 => Opcode::SUB8rm_NF_ND, + 4868 => Opcode::SUB8rr, + 4869 => Opcode::SUB8rr_EVEX, + 4870 => Opcode::SUB8rr_EVEX_REV, + 4871 => Opcode::SUB8rr_ND, + 4872 => Opcode::SUB8rr_ND_REV, + 4873 => Opcode::SUB8rr_NF, + 4874 => Opcode::SUB8rr_NF_ND, + 4875 => Opcode::SUB8rr_NF_ND_REV, + 4876 => Opcode::SUB8rr_NF_REV, + 4877 => Opcode::SUB8rr_REV, + 4878 => Opcode::SUBPDrm, + 4879 => Opcode::SUBPDrr, + 4880 => Opcode::SUBPSrm, + 4881 => Opcode::SUBPSrr, + 4882 => Opcode::SUBR_F32m, + 4883 => Opcode::SUBR_F64m, + 4884 => Opcode::SUBR_FI16m, + 4885 => Opcode::SUBR_FI32m, + 4886 => Opcode::SUBR_FPrST0, + 4887 => Opcode::SUBR_FST0r, + 4888 => Opcode::SUBR_Fp32m, + 4889 => Opcode::SUBR_Fp64m, + 4890 => Opcode::SUBR_Fp64m32, + 4891 => Opcode::SUBR_Fp80m32, + 4892 => Opcode::SUBR_Fp80m64, + 4893 => Opcode::SUBR_FpI16m32, + 4894 => Opcode::SUBR_FpI16m64, + 4895 => Opcode::SUBR_FpI16m80, + 4896 => Opcode::SUBR_FpI32m32, + 4897 => Opcode::SUBR_FpI32m64, + 4898 => Opcode::SUBR_FpI32m80, + 4899 => Opcode::SUBR_FrST0, + 4900 => Opcode::SUBSDrm, + 4901 => Opcode::SUBSDrm_Int, + 4902 => Opcode::SUBSDrr, + 4903 => Opcode::SUBSDrr_Int, + 4904 => Opcode::SUBSSrm, + 4905 => Opcode::SUBSSrm_Int, + 4906 => Opcode::SUBSSrr, + 4907 => Opcode::SUBSSrr_Int, + 4908 => Opcode::SUB_F32m, + 4909 => Opcode::SUB_F64m, + 4910 => Opcode::SUB_FI16m, + 4911 => Opcode::SUB_FI32m, + 4912 => Opcode::SUB_FPrST0, + 4913 => Opcode::SUB_FST0r, + 4914 => Opcode::SUB_Fp32, + 4915 => Opcode::SUB_Fp32m, + 4916 => Opcode::SUB_Fp64, + 4917 => Opcode::SUB_Fp64m, + 4918 => Opcode::SUB_Fp64m32, + 4919 => Opcode::SUB_Fp80, + 4920 => Opcode::SUB_Fp80m32, + 4921 => Opcode::SUB_Fp80m64, + 4922 => Opcode::SUB_FpI16m32, + 4923 => Opcode::SUB_FpI16m64, + 4924 => Opcode::SUB_FpI16m80, + 4925 => Opcode::SUB_FpI32m32, + 4926 => Opcode::SUB_FpI32m64, + 4927 => Opcode::SUB_FpI32m80, + 4928 => Opcode::SUB_FrST0, + 4929 => Opcode::SWAPGS, + 4930 => Opcode::SYSCALL, + 4931 => Opcode::SYSENTER, + 4932 => Opcode::SYSEXIT, + 4933 => Opcode::SYSEXIT64, + 4934 => Opcode::SYSRET, + 4935 => Opcode::SYSRET64, + 4936 => Opcode::T1MSKC32rm, + 4937 => Opcode::T1MSKC32rr, + 4938 => Opcode::T1MSKC64rm, + 4939 => Opcode::T1MSKC64rr, + 4940 => Opcode::TAILJMPd, + 4941 => Opcode::TAILJMPd64, + 4942 => Opcode::TAILJMPd64_CC, + 4943 => Opcode::TAILJMPd_CC, + 4944 => Opcode::TAILJMPm, + 4945 => Opcode::TAILJMPm64, + 4946 => Opcode::TAILJMPm64_REX, + 4947 => Opcode::TAILJMPr, + 4948 => Opcode::TAILJMPr64, + 4949 => Opcode::TAILJMPr64_REX, + 4950 => Opcode::TCMMIMFP16PS, + 4951 => Opcode::TCMMRLFP16PS, + 4952 => Opcode::TCRETURN_HIPE32ri, + 4953 => Opcode::TCRETURN_WIN64ri, + 4954 => Opcode::TCRETURN_WINmi64, + 4955 => Opcode::TCRETURNdi, + 4956 => Opcode::TCRETURNdi64, + 4957 => Opcode::TCRETURNdi64cc, + 4958 => Opcode::TCRETURNdicc, + 4959 => Opcode::TCRETURNmi, + 4960 => Opcode::TCRETURNmi64, + 4961 => Opcode::TCRETURNri, + 4962 => Opcode::TCRETURNri64, + 4963 => Opcode::TCRETURNri64_ImpCall, + 4964 => Opcode::TCVTROWD2PSrte, + 4965 => Opcode::TCVTROWD2PSrti, + 4966 => Opcode::TCVTROWPS2BF16Hrte, + 4967 => Opcode::TCVTROWPS2BF16Hrti, + 4968 => Opcode::TCVTROWPS2BF16Lrte, + 4969 => Opcode::TCVTROWPS2BF16Lrti, + 4970 => Opcode::TCVTROWPS2PHHrte, + 4971 => Opcode::TCVTROWPS2PHHrti, + 4972 => Opcode::TCVTROWPS2PHLrte, + 4973 => Opcode::TCVTROWPS2PHLrti, + 4974 => Opcode::TDCALL, + 4975 => Opcode::TDPBF16PS, + 4976 => Opcode::TDPBF8PS, + 4977 => Opcode::TDPBHF8PS, + 4978 => Opcode::TDPBSSD, + 4979 => Opcode::TDPBSUD, + 4980 => Opcode::TDPBUSD, + 4981 => Opcode::TDPBUUD, + 4982 => Opcode::TDPFP16PS, + 4983 => Opcode::TDPHBF8PS, + 4984 => Opcode::TDPHF8PS, + 4985 => Opcode::TEST16i16, + 4986 => Opcode::TEST16mi, + 4987 => Opcode::TEST16mr, + 4988 => Opcode::TEST16ri, + 4989 => Opcode::TEST16rr, + 4990 => Opcode::TEST32i32, + 4991 => Opcode::TEST32mi, + 4992 => Opcode::TEST32mr, + 4993 => Opcode::TEST32ri, + 4994 => Opcode::TEST32rr, + 4995 => Opcode::TEST64i32, + 4996 => Opcode::TEST64mi32, + 4997 => Opcode::TEST64mr, + 4998 => Opcode::TEST64ri32, + 4999 => Opcode::TEST64rr, + 5000 => Opcode::TEST8i8, + 5001 => Opcode::TEST8mi, + 5002 => Opcode::TEST8mr, + 5003 => Opcode::TEST8ri, + 5004 => Opcode::TEST8rr, + 5005 => Opcode::TESTUI, + 5006 => Opcode::TILELOADD, + 5007 => Opcode::TILELOADDRS, + 5008 => Opcode::TILELOADDRST1, + 5009 => Opcode::TILELOADDRST1_EVEX, + 5010 => Opcode::TILELOADDRS_EVEX, + 5011 => Opcode::TILELOADDT1, + 5012 => Opcode::TILELOADDT1_EVEX, + 5013 => Opcode::TILELOADD_EVEX, + 5014 => Opcode::TILEMOVROWrte, + 5015 => Opcode::TILEMOVROWrti, + 5016 => Opcode::TILERELEASE, + 5017 => Opcode::TILESTORED, + 5018 => Opcode::TILESTORED_EVEX, + 5019 => Opcode::TILEZERO, + 5020 => Opcode::TLBSYNC, + 5021 => Opcode::TLSCall_32, + 5022 => Opcode::TLSCall_64, + 5023 => Opcode::TLS_addr32, + 5024 => Opcode::TLS_addr64, + 5025 => Opcode::TLS_addrX32, + 5026 => Opcode::TLS_base_addr32, + 5027 => Opcode::TLS_base_addr64, + 5028 => Opcode::TLS_base_addrX32, + 5029 => Opcode::TLS_desc32, + 5030 => Opcode::TLS_desc64, + 5031 => Opcode::TMMULTF32PS, + 5032 => Opcode::TPAUSE, + 5033 => Opcode::TRAP, + 5034 => Opcode::TST_F, + 5035 => Opcode::TST_Fp32, + 5036 => Opcode::TST_Fp64, + 5037 => Opcode::TST_Fp80, + 5038 => Opcode::TZCNT16rm, + 5039 => Opcode::TZCNT16rm_EVEX, + 5040 => Opcode::TZCNT16rm_NF, + 5041 => Opcode::TZCNT16rr, + 5042 => Opcode::TZCNT16rr_EVEX, + 5043 => Opcode::TZCNT16rr_NF, + 5044 => Opcode::TZCNT32rm, + 5045 => Opcode::TZCNT32rm_EVEX, + 5046 => Opcode::TZCNT32rm_NF, + 5047 => Opcode::TZCNT32rr, + 5048 => Opcode::TZCNT32rr_EVEX, + 5049 => Opcode::TZCNT32rr_NF, + 5050 => Opcode::TZCNT64rm, + 5051 => Opcode::TZCNT64rm_EVEX, + 5052 => Opcode::TZCNT64rm_NF, + 5053 => Opcode::TZCNT64rr, + 5054 => Opcode::TZCNT64rr_EVEX, + 5055 => Opcode::TZCNT64rr_NF, + 5056 => Opcode::TZMSK32rm, + 5057 => Opcode::TZMSK32rr, + 5058 => Opcode::TZMSK64rm, + 5059 => Opcode::TZMSK64rr, + 5060 => Opcode::UBSAN_UD1, + 5061 => Opcode::UCOMISDrm, + 5062 => Opcode::UCOMISDrm_Int, + 5063 => Opcode::UCOMISDrr, + 5064 => Opcode::UCOMISDrr_Int, + 5065 => Opcode::UCOMISSrm, + 5066 => Opcode::UCOMISSrm_Int, + 5067 => Opcode::UCOMISSrr, + 5068 => Opcode::UCOMISSrr_Int, + 5069 => Opcode::UCOM_FIPr, + 5070 => Opcode::UCOM_FIr, + 5071 => Opcode::UCOM_FPPr, + 5072 => Opcode::UCOM_FPr, + 5073 => Opcode::UCOM_FpIr32, + 5074 => Opcode::UCOM_FpIr64, + 5075 => Opcode::UCOM_FpIr80, + 5076 => Opcode::UCOM_Fpr32, + 5077 => Opcode::UCOM_Fpr64, + 5078 => Opcode::UCOM_Fpr80, + 5079 => Opcode::UCOM_Fr, + 5080 => Opcode::UD1Lm, + 5081 => Opcode::UD1Lr, + 5082 => Opcode::UD1Qm, + 5083 => Opcode::UD1Qr, + 5084 => Opcode::UD1Wm, + 5085 => Opcode::UD1Wr, + 5086 => Opcode::UIRET, + 5087 => Opcode::UMONITOR16, + 5088 => Opcode::UMONITOR32, + 5089 => Opcode::UMONITOR64, + 5090 => Opcode::UMWAIT, + 5091 => Opcode::UNPCKHPDrm, + 5092 => Opcode::UNPCKHPDrr, + 5093 => Opcode::UNPCKHPSrm, + 5094 => Opcode::UNPCKHPSrr, + 5095 => Opcode::UNPCKLPDrm, + 5096 => Opcode::UNPCKLPDrr, + 5097 => Opcode::UNPCKLPSrm, + 5098 => Opcode::UNPCKLPSrr, + 5099 => Opcode::URDMSRri, + 5100 => Opcode::URDMSRri_EVEX, + 5101 => Opcode::URDMSRrr, + 5102 => Opcode::URDMSRrr_EVEX, + 5103 => Opcode::UWRMSRir, + 5104 => Opcode::UWRMSRir_EVEX, + 5105 => Opcode::UWRMSRrr, + 5106 => Opcode::UWRMSRrr_EVEX, + 5107 => Opcode::V4FMADDPSrm, + 5108 => Opcode::V4FMADDPSrmk, + 5109 => Opcode::V4FMADDPSrmkz, + 5110 => Opcode::V4FMADDSSrm, + 5111 => Opcode::V4FMADDSSrmk, + 5112 => Opcode::V4FMADDSSrmkz, + 5113 => Opcode::V4FNMADDPSrm, + 5114 => Opcode::V4FNMADDPSrmk, + 5115 => Opcode::V4FNMADDPSrmkz, + 5116 => Opcode::V4FNMADDSSrm, + 5117 => Opcode::V4FNMADDSSrmk, + 5118 => Opcode::V4FNMADDSSrmkz, + 5119 => Opcode::VAARG_64, + 5120 => Opcode::VAARG_X32, + 5121 => Opcode::VADDBF16Z128rm, + 5122 => Opcode::VADDBF16Z128rmb, + 5123 => Opcode::VADDBF16Z128rmbk, + 5124 => Opcode::VADDBF16Z128rmbkz, + 5125 => Opcode::VADDBF16Z128rmk, + 5126 => Opcode::VADDBF16Z128rmkz, + 5127 => Opcode::VADDBF16Z128rr, + 5128 => Opcode::VADDBF16Z128rrk, + 5129 => Opcode::VADDBF16Z128rrkz, + 5130 => Opcode::VADDBF16Z256rm, + 5131 => Opcode::VADDBF16Z256rmb, + 5132 => Opcode::VADDBF16Z256rmbk, + 5133 => Opcode::VADDBF16Z256rmbkz, + 5134 => Opcode::VADDBF16Z256rmk, + 5135 => Opcode::VADDBF16Z256rmkz, + 5136 => Opcode::VADDBF16Z256rr, + 5137 => Opcode::VADDBF16Z256rrk, + 5138 => Opcode::VADDBF16Z256rrkz, + 5139 => Opcode::VADDBF16Zrm, + 5140 => Opcode::VADDBF16Zrmb, + 5141 => Opcode::VADDBF16Zrmbk, + 5142 => Opcode::VADDBF16Zrmbkz, + 5143 => Opcode::VADDBF16Zrmk, + 5144 => Opcode::VADDBF16Zrmkz, + 5145 => Opcode::VADDBF16Zrr, + 5146 => Opcode::VADDBF16Zrrk, + 5147 => Opcode::VADDBF16Zrrkz, + 5148 => Opcode::VADDPDYrm, + 5149 => Opcode::VADDPDYrr, + 5150 => Opcode::VADDPDZ128rm, + 5151 => Opcode::VADDPDZ128rmb, + 5152 => Opcode::VADDPDZ128rmbk, + 5153 => Opcode::VADDPDZ128rmbkz, + 5154 => Opcode::VADDPDZ128rmk, + 5155 => Opcode::VADDPDZ128rmkz, + 5156 => Opcode::VADDPDZ128rr, + 5157 => Opcode::VADDPDZ128rrk, + 5158 => Opcode::VADDPDZ128rrkz, + 5159 => Opcode::VADDPDZ256rm, + 5160 => Opcode::VADDPDZ256rmb, + 5161 => Opcode::VADDPDZ256rmbk, + 5162 => Opcode::VADDPDZ256rmbkz, + 5163 => Opcode::VADDPDZ256rmk, + 5164 => Opcode::VADDPDZ256rmkz, + 5165 => Opcode::VADDPDZ256rr, + 5166 => Opcode::VADDPDZ256rrk, + 5167 => Opcode::VADDPDZ256rrkz, + 5168 => Opcode::VADDPDZrm, + 5169 => Opcode::VADDPDZrmb, + 5170 => Opcode::VADDPDZrmbk, + 5171 => Opcode::VADDPDZrmbkz, + 5172 => Opcode::VADDPDZrmk, + 5173 => Opcode::VADDPDZrmkz, + 5174 => Opcode::VADDPDZrr, + 5175 => Opcode::VADDPDZrrb, + 5176 => Opcode::VADDPDZrrbk, + 5177 => Opcode::VADDPDZrrbkz, + 5178 => Opcode::VADDPDZrrk, + 5179 => Opcode::VADDPDZrrkz, + 5180 => Opcode::VADDPDrm, + 5181 => Opcode::VADDPDrr, + 5182 => Opcode::VADDPHZ128rm, + 5183 => Opcode::VADDPHZ128rmb, + 5184 => Opcode::VADDPHZ128rmbk, + 5185 => Opcode::VADDPHZ128rmbkz, + 5186 => Opcode::VADDPHZ128rmk, + 5187 => Opcode::VADDPHZ128rmkz, + 5188 => Opcode::VADDPHZ128rr, + 5189 => Opcode::VADDPHZ128rrk, + 5190 => Opcode::VADDPHZ128rrkz, + 5191 => Opcode::VADDPHZ256rm, + 5192 => Opcode::VADDPHZ256rmb, + 5193 => Opcode::VADDPHZ256rmbk, + 5194 => Opcode::VADDPHZ256rmbkz, + 5195 => Opcode::VADDPHZ256rmk, + 5196 => Opcode::VADDPHZ256rmkz, + 5197 => Opcode::VADDPHZ256rr, + 5198 => Opcode::VADDPHZ256rrk, + 5199 => Opcode::VADDPHZ256rrkz, + 5200 => Opcode::VADDPHZrm, + 5201 => Opcode::VADDPHZrmb, + 5202 => Opcode::VADDPHZrmbk, + 5203 => Opcode::VADDPHZrmbkz, + 5204 => Opcode::VADDPHZrmk, + 5205 => Opcode::VADDPHZrmkz, + 5206 => Opcode::VADDPHZrr, + 5207 => Opcode::VADDPHZrrb, + 5208 => Opcode::VADDPHZrrbk, + 5209 => Opcode::VADDPHZrrbkz, + 5210 => Opcode::VADDPHZrrk, + 5211 => Opcode::VADDPHZrrkz, + 5212 => Opcode::VADDPSYrm, + 5213 => Opcode::VADDPSYrr, + 5214 => Opcode::VADDPSZ128rm, + 5215 => Opcode::VADDPSZ128rmb, + 5216 => Opcode::VADDPSZ128rmbk, + 5217 => Opcode::VADDPSZ128rmbkz, + 5218 => Opcode::VADDPSZ128rmk, + 5219 => Opcode::VADDPSZ128rmkz, + 5220 => Opcode::VADDPSZ128rr, + 5221 => Opcode::VADDPSZ128rrk, + 5222 => Opcode::VADDPSZ128rrkz, + 5223 => Opcode::VADDPSZ256rm, + 5224 => Opcode::VADDPSZ256rmb, + 5225 => Opcode::VADDPSZ256rmbk, + 5226 => Opcode::VADDPSZ256rmbkz, + 5227 => Opcode::VADDPSZ256rmk, + 5228 => Opcode::VADDPSZ256rmkz, + 5229 => Opcode::VADDPSZ256rr, + 5230 => Opcode::VADDPSZ256rrk, + 5231 => Opcode::VADDPSZ256rrkz, + 5232 => Opcode::VADDPSZrm, + 5233 => Opcode::VADDPSZrmb, + 5234 => Opcode::VADDPSZrmbk, + 5235 => Opcode::VADDPSZrmbkz, + 5236 => Opcode::VADDPSZrmk, + 5237 => Opcode::VADDPSZrmkz, + 5238 => Opcode::VADDPSZrr, + 5239 => Opcode::VADDPSZrrb, + 5240 => Opcode::VADDPSZrrbk, + 5241 => Opcode::VADDPSZrrbkz, + 5242 => Opcode::VADDPSZrrk, + 5243 => Opcode::VADDPSZrrkz, + 5244 => Opcode::VADDPSrm, + 5245 => Opcode::VADDPSrr, + 5246 => Opcode::VADDSDZrm, + 5247 => Opcode::VADDSDZrm_Int, + 5248 => Opcode::VADDSDZrmk_Int, + 5249 => Opcode::VADDSDZrmkz_Int, + 5250 => Opcode::VADDSDZrr, + 5251 => Opcode::VADDSDZrr_Int, + 5252 => Opcode::VADDSDZrrb_Int, + 5253 => Opcode::VADDSDZrrbk_Int, + 5254 => Opcode::VADDSDZrrbkz_Int, + 5255 => Opcode::VADDSDZrrk_Int, + 5256 => Opcode::VADDSDZrrkz_Int, + 5257 => Opcode::VADDSDrm, + 5258 => Opcode::VADDSDrm_Int, + 5259 => Opcode::VADDSDrr, + 5260 => Opcode::VADDSDrr_Int, + 5261 => Opcode::VADDSHZrm, + 5262 => Opcode::VADDSHZrm_Int, + 5263 => Opcode::VADDSHZrmk_Int, + 5264 => Opcode::VADDSHZrmkz_Int, + 5265 => Opcode::VADDSHZrr, + 5266 => Opcode::VADDSHZrr_Int, + 5267 => Opcode::VADDSHZrrb_Int, + 5268 => Opcode::VADDSHZrrbk_Int, + 5269 => Opcode::VADDSHZrrbkz_Int, + 5270 => Opcode::VADDSHZrrk_Int, + 5271 => Opcode::VADDSHZrrkz_Int, + 5272 => Opcode::VADDSSZrm, + 5273 => Opcode::VADDSSZrm_Int, + 5274 => Opcode::VADDSSZrmk_Int, + 5275 => Opcode::VADDSSZrmkz_Int, + 5276 => Opcode::VADDSSZrr, + 5277 => Opcode::VADDSSZrr_Int, + 5278 => Opcode::VADDSSZrrb_Int, + 5279 => Opcode::VADDSSZrrbk_Int, + 5280 => Opcode::VADDSSZrrbkz_Int, + 5281 => Opcode::VADDSSZrrk_Int, + 5282 => Opcode::VADDSSZrrkz_Int, + 5283 => Opcode::VADDSSrm, + 5284 => Opcode::VADDSSrm_Int, + 5285 => Opcode::VADDSSrr, + 5286 => Opcode::VADDSSrr_Int, + 5287 => Opcode::VADDSUBPDYrm, + 5288 => Opcode::VADDSUBPDYrr, + 5289 => Opcode::VADDSUBPDrm, + 5290 => Opcode::VADDSUBPDrr, + 5291 => Opcode::VADDSUBPSYrm, + 5292 => Opcode::VADDSUBPSYrr, + 5293 => Opcode::VADDSUBPSrm, + 5294 => Opcode::VADDSUBPSrr, + 5295 => Opcode::VAESDECLASTYrm, + 5296 => Opcode::VAESDECLASTYrr, + 5297 => Opcode::VAESDECLASTZ128rm, + 5298 => Opcode::VAESDECLASTZ128rr, + 5299 => Opcode::VAESDECLASTZ256rm, + 5300 => Opcode::VAESDECLASTZ256rr, + 5301 => Opcode::VAESDECLASTZrm, + 5302 => Opcode::VAESDECLASTZrr, + 5303 => Opcode::VAESDECLASTrm, + 5304 => Opcode::VAESDECLASTrr, + 5305 => Opcode::VAESDECYrm, + 5306 => Opcode::VAESDECYrr, + 5307 => Opcode::VAESDECZ128rm, + 5308 => Opcode::VAESDECZ128rr, + 5309 => Opcode::VAESDECZ256rm, + 5310 => Opcode::VAESDECZ256rr, + 5311 => Opcode::VAESDECZrm, + 5312 => Opcode::VAESDECZrr, + 5313 => Opcode::VAESDECrm, + 5314 => Opcode::VAESDECrr, + 5315 => Opcode::VAESENCLASTYrm, + 5316 => Opcode::VAESENCLASTYrr, + 5317 => Opcode::VAESENCLASTZ128rm, + 5318 => Opcode::VAESENCLASTZ128rr, + 5319 => Opcode::VAESENCLASTZ256rm, + 5320 => Opcode::VAESENCLASTZ256rr, + 5321 => Opcode::VAESENCLASTZrm, + 5322 => Opcode::VAESENCLASTZrr, + 5323 => Opcode::VAESENCLASTrm, + 5324 => Opcode::VAESENCLASTrr, + 5325 => Opcode::VAESENCYrm, + 5326 => Opcode::VAESENCYrr, + 5327 => Opcode::VAESENCZ128rm, + 5328 => Opcode::VAESENCZ128rr, + 5329 => Opcode::VAESENCZ256rm, + 5330 => Opcode::VAESENCZ256rr, + 5331 => Opcode::VAESENCZrm, + 5332 => Opcode::VAESENCZrr, + 5333 => Opcode::VAESENCrm, + 5334 => Opcode::VAESENCrr, + 5335 => Opcode::VAESIMCrm, + 5336 => Opcode::VAESIMCrr, + 5337 => Opcode::VAESKEYGENASSISTrmi, + 5338 => Opcode::VAESKEYGENASSISTrri, + 5339 => Opcode::VALIGNDZ128rmbi, + 5340 => Opcode::VALIGNDZ128rmbik, + 5341 => Opcode::VALIGNDZ128rmbikz, + 5342 => Opcode::VALIGNDZ128rmi, + 5343 => Opcode::VALIGNDZ128rmik, + 5344 => Opcode::VALIGNDZ128rmikz, + 5345 => Opcode::VALIGNDZ128rri, + 5346 => Opcode::VALIGNDZ128rrik, + 5347 => Opcode::VALIGNDZ128rrikz, + 5348 => Opcode::VALIGNDZ256rmbi, + 5349 => Opcode::VALIGNDZ256rmbik, + 5350 => Opcode::VALIGNDZ256rmbikz, + 5351 => Opcode::VALIGNDZ256rmi, + 5352 => Opcode::VALIGNDZ256rmik, + 5353 => Opcode::VALIGNDZ256rmikz, + 5354 => Opcode::VALIGNDZ256rri, + 5355 => Opcode::VALIGNDZ256rrik, + 5356 => Opcode::VALIGNDZ256rrikz, + 5357 => Opcode::VALIGNDZrmbi, + 5358 => Opcode::VALIGNDZrmbik, + 5359 => Opcode::VALIGNDZrmbikz, + 5360 => Opcode::VALIGNDZrmi, + 5361 => Opcode::VALIGNDZrmik, + 5362 => Opcode::VALIGNDZrmikz, + 5363 => Opcode::VALIGNDZrri, + 5364 => Opcode::VALIGNDZrrik, + 5365 => Opcode::VALIGNDZrrikz, + 5366 => Opcode::VALIGNQZ128rmbi, + 5367 => Opcode::VALIGNQZ128rmbik, + 5368 => Opcode::VALIGNQZ128rmbikz, + 5369 => Opcode::VALIGNQZ128rmi, + 5370 => Opcode::VALIGNQZ128rmik, + 5371 => Opcode::VALIGNQZ128rmikz, + 5372 => Opcode::VALIGNQZ128rri, + 5373 => Opcode::VALIGNQZ128rrik, + 5374 => Opcode::VALIGNQZ128rrikz, + 5375 => Opcode::VALIGNQZ256rmbi, + 5376 => Opcode::VALIGNQZ256rmbik, + 5377 => Opcode::VALIGNQZ256rmbikz, + 5378 => Opcode::VALIGNQZ256rmi, + 5379 => Opcode::VALIGNQZ256rmik, + 5380 => Opcode::VALIGNQZ256rmikz, + 5381 => Opcode::VALIGNQZ256rri, + 5382 => Opcode::VALIGNQZ256rrik, + 5383 => Opcode::VALIGNQZ256rrikz, + 5384 => Opcode::VALIGNQZrmbi, + 5385 => Opcode::VALIGNQZrmbik, + 5386 => Opcode::VALIGNQZrmbikz, + 5387 => Opcode::VALIGNQZrmi, + 5388 => Opcode::VALIGNQZrmik, + 5389 => Opcode::VALIGNQZrmikz, + 5390 => Opcode::VALIGNQZrri, + 5391 => Opcode::VALIGNQZrrik, + 5392 => Opcode::VALIGNQZrrikz, + 5393 => Opcode::VANDNPDYrm, + 5394 => Opcode::VANDNPDYrr, + 5395 => Opcode::VANDNPDZ128rm, + 5396 => Opcode::VANDNPDZ128rmb, + 5397 => Opcode::VANDNPDZ128rmbk, + 5398 => Opcode::VANDNPDZ128rmbkz, + 5399 => Opcode::VANDNPDZ128rmk, + 5400 => Opcode::VANDNPDZ128rmkz, + 5401 => Opcode::VANDNPDZ128rr, + 5402 => Opcode::VANDNPDZ128rrk, + 5403 => Opcode::VANDNPDZ128rrkz, + 5404 => Opcode::VANDNPDZ256rm, + 5405 => Opcode::VANDNPDZ256rmb, + 5406 => Opcode::VANDNPDZ256rmbk, + 5407 => Opcode::VANDNPDZ256rmbkz, + 5408 => Opcode::VANDNPDZ256rmk, + 5409 => Opcode::VANDNPDZ256rmkz, + 5410 => Opcode::VANDNPDZ256rr, + 5411 => Opcode::VANDNPDZ256rrk, + 5412 => Opcode::VANDNPDZ256rrkz, + 5413 => Opcode::VANDNPDZrm, + 5414 => Opcode::VANDNPDZrmb, + 5415 => Opcode::VANDNPDZrmbk, + 5416 => Opcode::VANDNPDZrmbkz, + 5417 => Opcode::VANDNPDZrmk, + 5418 => Opcode::VANDNPDZrmkz, + 5419 => Opcode::VANDNPDZrr, + 5420 => Opcode::VANDNPDZrrk, + 5421 => Opcode::VANDNPDZrrkz, + 5422 => Opcode::VANDNPDrm, + 5423 => Opcode::VANDNPDrr, + 5424 => Opcode::VANDNPSYrm, + 5425 => Opcode::VANDNPSYrr, + 5426 => Opcode::VANDNPSZ128rm, + 5427 => Opcode::VANDNPSZ128rmb, + 5428 => Opcode::VANDNPSZ128rmbk, + 5429 => Opcode::VANDNPSZ128rmbkz, + 5430 => Opcode::VANDNPSZ128rmk, + 5431 => Opcode::VANDNPSZ128rmkz, + 5432 => Opcode::VANDNPSZ128rr, + 5433 => Opcode::VANDNPSZ128rrk, + 5434 => Opcode::VANDNPSZ128rrkz, + 5435 => Opcode::VANDNPSZ256rm, + 5436 => Opcode::VANDNPSZ256rmb, + 5437 => Opcode::VANDNPSZ256rmbk, + 5438 => Opcode::VANDNPSZ256rmbkz, + 5439 => Opcode::VANDNPSZ256rmk, + 5440 => Opcode::VANDNPSZ256rmkz, + 5441 => Opcode::VANDNPSZ256rr, + 5442 => Opcode::VANDNPSZ256rrk, + 5443 => Opcode::VANDNPSZ256rrkz, + 5444 => Opcode::VANDNPSZrm, + 5445 => Opcode::VANDNPSZrmb, + 5446 => Opcode::VANDNPSZrmbk, + 5447 => Opcode::VANDNPSZrmbkz, + 5448 => Opcode::VANDNPSZrmk, + 5449 => Opcode::VANDNPSZrmkz, + 5450 => Opcode::VANDNPSZrr, + 5451 => Opcode::VANDNPSZrrk, + 5452 => Opcode::VANDNPSZrrkz, + 5453 => Opcode::VANDNPSrm, + 5454 => Opcode::VANDNPSrr, + 5455 => Opcode::VANDPDYrm, + 5456 => Opcode::VANDPDYrr, + 5457 => Opcode::VANDPDZ128rm, + 5458 => Opcode::VANDPDZ128rmb, + 5459 => Opcode::VANDPDZ128rmbk, + 5460 => Opcode::VANDPDZ128rmbkz, + 5461 => Opcode::VANDPDZ128rmk, + 5462 => Opcode::VANDPDZ128rmkz, + 5463 => Opcode::VANDPDZ128rr, + 5464 => Opcode::VANDPDZ128rrk, + 5465 => Opcode::VANDPDZ128rrkz, + 5466 => Opcode::VANDPDZ256rm, + 5467 => Opcode::VANDPDZ256rmb, + 5468 => Opcode::VANDPDZ256rmbk, + 5469 => Opcode::VANDPDZ256rmbkz, + 5470 => Opcode::VANDPDZ256rmk, + 5471 => Opcode::VANDPDZ256rmkz, + 5472 => Opcode::VANDPDZ256rr, + 5473 => Opcode::VANDPDZ256rrk, + 5474 => Opcode::VANDPDZ256rrkz, + 5475 => Opcode::VANDPDZrm, + 5476 => Opcode::VANDPDZrmb, + 5477 => Opcode::VANDPDZrmbk, + 5478 => Opcode::VANDPDZrmbkz, + 5479 => Opcode::VANDPDZrmk, + 5480 => Opcode::VANDPDZrmkz, + 5481 => Opcode::VANDPDZrr, + 5482 => Opcode::VANDPDZrrk, + 5483 => Opcode::VANDPDZrrkz, + 5484 => Opcode::VANDPDrm, + 5485 => Opcode::VANDPDrr, + 5486 => Opcode::VANDPSYrm, + 5487 => Opcode::VANDPSYrr, + 5488 => Opcode::VANDPSZ128rm, + 5489 => Opcode::VANDPSZ128rmb, + 5490 => Opcode::VANDPSZ128rmbk, + 5491 => Opcode::VANDPSZ128rmbkz, + 5492 => Opcode::VANDPSZ128rmk, + 5493 => Opcode::VANDPSZ128rmkz, + 5494 => Opcode::VANDPSZ128rr, + 5495 => Opcode::VANDPSZ128rrk, + 5496 => Opcode::VANDPSZ128rrkz, + 5497 => Opcode::VANDPSZ256rm, + 5498 => Opcode::VANDPSZ256rmb, + 5499 => Opcode::VANDPSZ256rmbk, + 5500 => Opcode::VANDPSZ256rmbkz, + 5501 => Opcode::VANDPSZ256rmk, + 5502 => Opcode::VANDPSZ256rmkz, + 5503 => Opcode::VANDPSZ256rr, + 5504 => Opcode::VANDPSZ256rrk, + 5505 => Opcode::VANDPSZ256rrkz, + 5506 => Opcode::VANDPSZrm, + 5507 => Opcode::VANDPSZrmb, + 5508 => Opcode::VANDPSZrmbk, + 5509 => Opcode::VANDPSZrmbkz, + 5510 => Opcode::VANDPSZrmk, + 5511 => Opcode::VANDPSZrmkz, + 5512 => Opcode::VANDPSZrr, + 5513 => Opcode::VANDPSZrrk, + 5514 => Opcode::VANDPSZrrkz, + 5515 => Opcode::VANDPSrm, + 5516 => Opcode::VANDPSrr, + 5517 => Opcode::VASTART_SAVE_XMM_REGS, + 5518 => Opcode::VBCSTNEBF162PSYrm, + 5519 => Opcode::VBCSTNEBF162PSrm, + 5520 => Opcode::VBCSTNESH2PSYrm, + 5521 => Opcode::VBCSTNESH2PSrm, + 5522 => Opcode::VBLENDMPDZ128rm, + 5523 => Opcode::VBLENDMPDZ128rmb, + 5524 => Opcode::VBLENDMPDZ128rmbk, + 5525 => Opcode::VBLENDMPDZ128rmbkz, + 5526 => Opcode::VBLENDMPDZ128rmk, + 5527 => Opcode::VBLENDMPDZ128rmkz, + 5528 => Opcode::VBLENDMPDZ128rr, + 5529 => Opcode::VBLENDMPDZ128rrk, + 5530 => Opcode::VBLENDMPDZ128rrkz, + 5531 => Opcode::VBLENDMPDZ256rm, + 5532 => Opcode::VBLENDMPDZ256rmb, + 5533 => Opcode::VBLENDMPDZ256rmbk, + 5534 => Opcode::VBLENDMPDZ256rmbkz, + 5535 => Opcode::VBLENDMPDZ256rmk, + 5536 => Opcode::VBLENDMPDZ256rmkz, + 5537 => Opcode::VBLENDMPDZ256rr, + 5538 => Opcode::VBLENDMPDZ256rrk, + 5539 => Opcode::VBLENDMPDZ256rrkz, + 5540 => Opcode::VBLENDMPDZrm, + 5541 => Opcode::VBLENDMPDZrmb, + 5542 => Opcode::VBLENDMPDZrmbk, + 5543 => Opcode::VBLENDMPDZrmbkz, + 5544 => Opcode::VBLENDMPDZrmk, + 5545 => Opcode::VBLENDMPDZrmkz, + 5546 => Opcode::VBLENDMPDZrr, + 5547 => Opcode::VBLENDMPDZrrk, + 5548 => Opcode::VBLENDMPDZrrkz, + 5549 => Opcode::VBLENDMPSZ128rm, + 5550 => Opcode::VBLENDMPSZ128rmb, + 5551 => Opcode::VBLENDMPSZ128rmbk, + 5552 => Opcode::VBLENDMPSZ128rmbkz, + 5553 => Opcode::VBLENDMPSZ128rmk, + 5554 => Opcode::VBLENDMPSZ128rmkz, + 5555 => Opcode::VBLENDMPSZ128rr, + 5556 => Opcode::VBLENDMPSZ128rrk, + 5557 => Opcode::VBLENDMPSZ128rrkz, + 5558 => Opcode::VBLENDMPSZ256rm, + 5559 => Opcode::VBLENDMPSZ256rmb, + 5560 => Opcode::VBLENDMPSZ256rmbk, + 5561 => Opcode::VBLENDMPSZ256rmbkz, + 5562 => Opcode::VBLENDMPSZ256rmk, + 5563 => Opcode::VBLENDMPSZ256rmkz, + 5564 => Opcode::VBLENDMPSZ256rr, + 5565 => Opcode::VBLENDMPSZ256rrk, + 5566 => Opcode::VBLENDMPSZ256rrkz, + 5567 => Opcode::VBLENDMPSZrm, + 5568 => Opcode::VBLENDMPSZrmb, + 5569 => Opcode::VBLENDMPSZrmbk, + 5570 => Opcode::VBLENDMPSZrmbkz, + 5571 => Opcode::VBLENDMPSZrmk, + 5572 => Opcode::VBLENDMPSZrmkz, + 5573 => Opcode::VBLENDMPSZrr, + 5574 => Opcode::VBLENDMPSZrrk, + 5575 => Opcode::VBLENDMPSZrrkz, + 5576 => Opcode::VBLENDPDYrmi, + 5577 => Opcode::VBLENDPDYrri, + 5578 => Opcode::VBLENDPDrmi, + 5579 => Opcode::VBLENDPDrri, + 5580 => Opcode::VBLENDPSYrmi, + 5581 => Opcode::VBLENDPSYrri, + 5582 => Opcode::VBLENDPSrmi, + 5583 => Opcode::VBLENDPSrri, + 5584 => Opcode::VBLENDVPDYrmr, + 5585 => Opcode::VBLENDVPDYrrr, + 5586 => Opcode::VBLENDVPDrmr, + 5587 => Opcode::VBLENDVPDrrr, + 5588 => Opcode::VBLENDVPSYrmr, + 5589 => Opcode::VBLENDVPSYrrr, + 5590 => Opcode::VBLENDVPSrmr, + 5591 => Opcode::VBLENDVPSrrr, + 5592 => Opcode::VBROADCASTF128rm, + 5593 => Opcode::VBROADCASTF32X2Z256rm, + 5594 => Opcode::VBROADCASTF32X2Z256rmk, + 5595 => Opcode::VBROADCASTF32X2Z256rmkz, + 5596 => Opcode::VBROADCASTF32X2Z256rr, + 5597 => Opcode::VBROADCASTF32X2Z256rrk, + 5598 => Opcode::VBROADCASTF32X2Z256rrkz, + 5599 => Opcode::VBROADCASTF32X2Zrm, + 5600 => Opcode::VBROADCASTF32X2Zrmk, + 5601 => Opcode::VBROADCASTF32X2Zrmkz, + 5602 => Opcode::VBROADCASTF32X2Zrr, + 5603 => Opcode::VBROADCASTF32X2Zrrk, + 5604 => Opcode::VBROADCASTF32X2Zrrkz, + 5605 => Opcode::VBROADCASTF32X4Z256rm, + 5606 => Opcode::VBROADCASTF32X4Z256rmk, + 5607 => Opcode::VBROADCASTF32X4Z256rmkz, + 5608 => Opcode::VBROADCASTF32X4Zrm, + 5609 => Opcode::VBROADCASTF32X4Zrmk, + 5610 => Opcode::VBROADCASTF32X4Zrmkz, + 5611 => Opcode::VBROADCASTF32X8Zrm, + 5612 => Opcode::VBROADCASTF32X8Zrmk, + 5613 => Opcode::VBROADCASTF32X8Zrmkz, + 5614 => Opcode::VBROADCASTF64X2Z256rm, + 5615 => Opcode::VBROADCASTF64X2Z256rmk, + 5616 => Opcode::VBROADCASTF64X2Z256rmkz, + 5617 => Opcode::VBROADCASTF64X2Zrm, + 5618 => Opcode::VBROADCASTF64X2Zrmk, + 5619 => Opcode::VBROADCASTF64X2Zrmkz, + 5620 => Opcode::VBROADCASTF64X4Zrm, + 5621 => Opcode::VBROADCASTF64X4Zrmk, + 5622 => Opcode::VBROADCASTF64X4Zrmkz, + 5623 => Opcode::VBROADCASTI128rm, + 5624 => Opcode::VBROADCASTI32X2Z128rm, + 5625 => Opcode::VBROADCASTI32X2Z128rmk, + 5626 => Opcode::VBROADCASTI32X2Z128rmkz, + 5627 => Opcode::VBROADCASTI32X2Z128rr, + 5628 => Opcode::VBROADCASTI32X2Z128rrk, + 5629 => Opcode::VBROADCASTI32X2Z128rrkz, + 5630 => Opcode::VBROADCASTI32X2Z256rm, + 5631 => Opcode::VBROADCASTI32X2Z256rmk, + 5632 => Opcode::VBROADCASTI32X2Z256rmkz, + 5633 => Opcode::VBROADCASTI32X2Z256rr, + 5634 => Opcode::VBROADCASTI32X2Z256rrk, + 5635 => Opcode::VBROADCASTI32X2Z256rrkz, + 5636 => Opcode::VBROADCASTI32X2Zrm, + 5637 => Opcode::VBROADCASTI32X2Zrmk, + 5638 => Opcode::VBROADCASTI32X2Zrmkz, + 5639 => Opcode::VBROADCASTI32X2Zrr, + 5640 => Opcode::VBROADCASTI32X2Zrrk, + 5641 => Opcode::VBROADCASTI32X2Zrrkz, + 5642 => Opcode::VBROADCASTI32X4Z256rm, + 5643 => Opcode::VBROADCASTI32X4Z256rmk, + 5644 => Opcode::VBROADCASTI32X4Z256rmkz, + 5645 => Opcode::VBROADCASTI32X4Zrm, + 5646 => Opcode::VBROADCASTI32X4Zrmk, + 5647 => Opcode::VBROADCASTI32X4Zrmkz, + 5648 => Opcode::VBROADCASTI32X8Zrm, + 5649 => Opcode::VBROADCASTI32X8Zrmk, + 5650 => Opcode::VBROADCASTI32X8Zrmkz, + 5651 => Opcode::VBROADCASTI64X2Z256rm, + 5652 => Opcode::VBROADCASTI64X2Z256rmk, + 5653 => Opcode::VBROADCASTI64X2Z256rmkz, + 5654 => Opcode::VBROADCASTI64X2Zrm, + 5655 => Opcode::VBROADCASTI64X2Zrmk, + 5656 => Opcode::VBROADCASTI64X2Zrmkz, + 5657 => Opcode::VBROADCASTI64X4Zrm, + 5658 => Opcode::VBROADCASTI64X4Zrmk, + 5659 => Opcode::VBROADCASTI64X4Zrmkz, + 5660 => Opcode::VBROADCASTSDYrm, + 5661 => Opcode::VBROADCASTSDYrr, + 5662 => Opcode::VBROADCASTSDZ256rm, + 5663 => Opcode::VBROADCASTSDZ256rmk, + 5664 => Opcode::VBROADCASTSDZ256rmkz, + 5665 => Opcode::VBROADCASTSDZ256rr, + 5666 => Opcode::VBROADCASTSDZ256rrk, + 5667 => Opcode::VBROADCASTSDZ256rrkz, + 5668 => Opcode::VBROADCASTSDZrm, + 5669 => Opcode::VBROADCASTSDZrmk, + 5670 => Opcode::VBROADCASTSDZrmkz, + 5671 => Opcode::VBROADCASTSDZrr, + 5672 => Opcode::VBROADCASTSDZrrk, + 5673 => Opcode::VBROADCASTSDZrrkz, + 5674 => Opcode::VBROADCASTSSYrm, + 5675 => Opcode::VBROADCASTSSYrr, + 5676 => Opcode::VBROADCASTSSZ128rm, + 5677 => Opcode::VBROADCASTSSZ128rmk, + 5678 => Opcode::VBROADCASTSSZ128rmkz, + 5679 => Opcode::VBROADCASTSSZ128rr, + 5680 => Opcode::VBROADCASTSSZ128rrk, + 5681 => Opcode::VBROADCASTSSZ128rrkz, + 5682 => Opcode::VBROADCASTSSZ256rm, + 5683 => Opcode::VBROADCASTSSZ256rmk, + 5684 => Opcode::VBROADCASTSSZ256rmkz, + 5685 => Opcode::VBROADCASTSSZ256rr, + 5686 => Opcode::VBROADCASTSSZ256rrk, + 5687 => Opcode::VBROADCASTSSZ256rrkz, + 5688 => Opcode::VBROADCASTSSZrm, + 5689 => Opcode::VBROADCASTSSZrmk, + 5690 => Opcode::VBROADCASTSSZrmkz, + 5691 => Opcode::VBROADCASTSSZrr, + 5692 => Opcode::VBROADCASTSSZrrk, + 5693 => Opcode::VBROADCASTSSZrrkz, + 5694 => Opcode::VBROADCASTSSrm, + 5695 => Opcode::VBROADCASTSSrr, + 5696 => Opcode::VCMPBF16Z128rmbi, + 5697 => Opcode::VCMPBF16Z128rmbik, + 5698 => Opcode::VCMPBF16Z128rmi, + 5699 => Opcode::VCMPBF16Z128rmik, + 5700 => Opcode::VCMPBF16Z128rri, + 5701 => Opcode::VCMPBF16Z128rrik, + 5702 => Opcode::VCMPBF16Z256rmbi, + 5703 => Opcode::VCMPBF16Z256rmbik, + 5704 => Opcode::VCMPBF16Z256rmi, + 5705 => Opcode::VCMPBF16Z256rmik, + 5706 => Opcode::VCMPBF16Z256rri, + 5707 => Opcode::VCMPBF16Z256rrik, + 5708 => Opcode::VCMPBF16Zrmbi, + 5709 => Opcode::VCMPBF16Zrmbik, + 5710 => Opcode::VCMPBF16Zrmi, + 5711 => Opcode::VCMPBF16Zrmik, + 5712 => Opcode::VCMPBF16Zrri, + 5713 => Opcode::VCMPBF16Zrrik, + 5714 => Opcode::VCMPPDYrmi, + 5715 => Opcode::VCMPPDYrri, + 5716 => Opcode::VCMPPDZ128rmbi, + 5717 => Opcode::VCMPPDZ128rmbik, + 5718 => Opcode::VCMPPDZ128rmi, + 5719 => Opcode::VCMPPDZ128rmik, + 5720 => Opcode::VCMPPDZ128rri, + 5721 => Opcode::VCMPPDZ128rrik, + 5722 => Opcode::VCMPPDZ256rmbi, + 5723 => Opcode::VCMPPDZ256rmbik, + 5724 => Opcode::VCMPPDZ256rmi, + 5725 => Opcode::VCMPPDZ256rmik, + 5726 => Opcode::VCMPPDZ256rri, + 5727 => Opcode::VCMPPDZ256rrik, + 5728 => Opcode::VCMPPDZrmbi, + 5729 => Opcode::VCMPPDZrmbik, + 5730 => Opcode::VCMPPDZrmi, + 5731 => Opcode::VCMPPDZrmik, + 5732 => Opcode::VCMPPDZrri, + 5733 => Opcode::VCMPPDZrrib, + 5734 => Opcode::VCMPPDZrribk, + 5735 => Opcode::VCMPPDZrrik, + 5736 => Opcode::VCMPPDrmi, + 5737 => Opcode::VCMPPDrri, + 5738 => Opcode::VCMPPHZ128rmbi, + 5739 => Opcode::VCMPPHZ128rmbik, + 5740 => Opcode::VCMPPHZ128rmi, + 5741 => Opcode::VCMPPHZ128rmik, + 5742 => Opcode::VCMPPHZ128rri, + 5743 => Opcode::VCMPPHZ128rrik, + 5744 => Opcode::VCMPPHZ256rmbi, + 5745 => Opcode::VCMPPHZ256rmbik, + 5746 => Opcode::VCMPPHZ256rmi, + 5747 => Opcode::VCMPPHZ256rmik, + 5748 => Opcode::VCMPPHZ256rri, + 5749 => Opcode::VCMPPHZ256rrik, + 5750 => Opcode::VCMPPHZrmbi, + 5751 => Opcode::VCMPPHZrmbik, + 5752 => Opcode::VCMPPHZrmi, + 5753 => Opcode::VCMPPHZrmik, + 5754 => Opcode::VCMPPHZrri, + 5755 => Opcode::VCMPPHZrrib, + 5756 => Opcode::VCMPPHZrribk, + 5757 => Opcode::VCMPPHZrrik, + 5758 => Opcode::VCMPPSYrmi, + 5759 => Opcode::VCMPPSYrri, + 5760 => Opcode::VCMPPSZ128rmbi, + 5761 => Opcode::VCMPPSZ128rmbik, + 5762 => Opcode::VCMPPSZ128rmi, + 5763 => Opcode::VCMPPSZ128rmik, + 5764 => Opcode::VCMPPSZ128rri, + 5765 => Opcode::VCMPPSZ128rrik, + 5766 => Opcode::VCMPPSZ256rmbi, + 5767 => Opcode::VCMPPSZ256rmbik, + 5768 => Opcode::VCMPPSZ256rmi, + 5769 => Opcode::VCMPPSZ256rmik, + 5770 => Opcode::VCMPPSZ256rri, + 5771 => Opcode::VCMPPSZ256rrik, + 5772 => Opcode::VCMPPSZrmbi, + 5773 => Opcode::VCMPPSZrmbik, + 5774 => Opcode::VCMPPSZrmi, + 5775 => Opcode::VCMPPSZrmik, + 5776 => Opcode::VCMPPSZrri, + 5777 => Opcode::VCMPPSZrrib, + 5778 => Opcode::VCMPPSZrribk, + 5779 => Opcode::VCMPPSZrrik, + 5780 => Opcode::VCMPPSrmi, + 5781 => Opcode::VCMPPSrri, + 5782 => Opcode::VCMPSDZrmi, + 5783 => Opcode::VCMPSDZrmi_Int, + 5784 => Opcode::VCMPSDZrmik_Int, + 5785 => Opcode::VCMPSDZrri, + 5786 => Opcode::VCMPSDZrri_Int, + 5787 => Opcode::VCMPSDZrrib_Int, + 5788 => Opcode::VCMPSDZrribk_Int, + 5789 => Opcode::VCMPSDZrrik_Int, + 5790 => Opcode::VCMPSDrmi, + 5791 => Opcode::VCMPSDrmi_Int, + 5792 => Opcode::VCMPSDrri, + 5793 => Opcode::VCMPSDrri_Int, + 5794 => Opcode::VCMPSHZrmi, + 5795 => Opcode::VCMPSHZrmi_Int, + 5796 => Opcode::VCMPSHZrmik_Int, + 5797 => Opcode::VCMPSHZrri, + 5798 => Opcode::VCMPSHZrri_Int, + 5799 => Opcode::VCMPSHZrrib_Int, + 5800 => Opcode::VCMPSHZrribk_Int, + 5801 => Opcode::VCMPSHZrrik_Int, + 5802 => Opcode::VCMPSSZrmi, + 5803 => Opcode::VCMPSSZrmi_Int, + 5804 => Opcode::VCMPSSZrmik_Int, + 5805 => Opcode::VCMPSSZrri, + 5806 => Opcode::VCMPSSZrri_Int, + 5807 => Opcode::VCMPSSZrrib_Int, + 5808 => Opcode::VCMPSSZrribk_Int, + 5809 => Opcode::VCMPSSZrrik_Int, + 5810 => Opcode::VCMPSSrmi, + 5811 => Opcode::VCMPSSrmi_Int, + 5812 => Opcode::VCMPSSrri, + 5813 => Opcode::VCMPSSrri_Int, + 5814 => Opcode::VCOMISBF16Zrm, + 5815 => Opcode::VCOMISBF16Zrm_Int, + 5816 => Opcode::VCOMISBF16Zrr, + 5817 => Opcode::VCOMISBF16Zrr_Int, + 5818 => Opcode::VCOMISDZrm, + 5819 => Opcode::VCOMISDZrm_Int, + 5820 => Opcode::VCOMISDZrr, + 5821 => Opcode::VCOMISDZrr_Int, + 5822 => Opcode::VCOMISDZrrb, + 5823 => Opcode::VCOMISDrm, + 5824 => Opcode::VCOMISDrm_Int, + 5825 => Opcode::VCOMISDrr, + 5826 => Opcode::VCOMISDrr_Int, + 5827 => Opcode::VCOMISHZrm, + 5828 => Opcode::VCOMISHZrm_Int, + 5829 => Opcode::VCOMISHZrr, + 5830 => Opcode::VCOMISHZrr_Int, + 5831 => Opcode::VCOMISHZrrb, + 5832 => Opcode::VCOMISSZrm, + 5833 => Opcode::VCOMISSZrm_Int, + 5834 => Opcode::VCOMISSZrr, + 5835 => Opcode::VCOMISSZrr_Int, + 5836 => Opcode::VCOMISSZrrb, + 5837 => Opcode::VCOMISSrm, + 5838 => Opcode::VCOMISSrm_Int, + 5839 => Opcode::VCOMISSrr, + 5840 => Opcode::VCOMISSrr_Int, + 5841 => Opcode::VCOMPRESSPDZ128mr, + 5842 => Opcode::VCOMPRESSPDZ128mrk, + 5843 => Opcode::VCOMPRESSPDZ128rr, + 5844 => Opcode::VCOMPRESSPDZ128rrk, + 5845 => Opcode::VCOMPRESSPDZ128rrkz, + 5846 => Opcode::VCOMPRESSPDZ256mr, + 5847 => Opcode::VCOMPRESSPDZ256mrk, + 5848 => Opcode::VCOMPRESSPDZ256rr, + 5849 => Opcode::VCOMPRESSPDZ256rrk, + 5850 => Opcode::VCOMPRESSPDZ256rrkz, + 5851 => Opcode::VCOMPRESSPDZmr, + 5852 => Opcode::VCOMPRESSPDZmrk, + 5853 => Opcode::VCOMPRESSPDZrr, + 5854 => Opcode::VCOMPRESSPDZrrk, + 5855 => Opcode::VCOMPRESSPDZrrkz, + 5856 => Opcode::VCOMPRESSPSZ128mr, + 5857 => Opcode::VCOMPRESSPSZ128mrk, + 5858 => Opcode::VCOMPRESSPSZ128rr, + 5859 => Opcode::VCOMPRESSPSZ128rrk, + 5860 => Opcode::VCOMPRESSPSZ128rrkz, + 5861 => Opcode::VCOMPRESSPSZ256mr, + 5862 => Opcode::VCOMPRESSPSZ256mrk, + 5863 => Opcode::VCOMPRESSPSZ256rr, + 5864 => Opcode::VCOMPRESSPSZ256rrk, + 5865 => Opcode::VCOMPRESSPSZ256rrkz, + 5866 => Opcode::VCOMPRESSPSZmr, + 5867 => Opcode::VCOMPRESSPSZmrk, + 5868 => Opcode::VCOMPRESSPSZrr, + 5869 => Opcode::VCOMPRESSPSZrrk, + 5870 => Opcode::VCOMPRESSPSZrrkz, + 5871 => Opcode::VCOMXSDZrm_Int, + 5872 => Opcode::VCOMXSDZrr_Int, + 5873 => Opcode::VCOMXSDZrrb_Int, + 5874 => Opcode::VCOMXSHZrm_Int, + 5875 => Opcode::VCOMXSHZrr_Int, + 5876 => Opcode::VCOMXSHZrrb_Int, + 5877 => Opcode::VCOMXSSZrm_Int, + 5878 => Opcode::VCOMXSSZrr_Int, + 5879 => Opcode::VCOMXSSZrrb_Int, + 5880 => Opcode::VCVT2PH2BF8SZ128rm, + 5881 => Opcode::VCVT2PH2BF8SZ128rmb, + 5882 => Opcode::VCVT2PH2BF8SZ128rmbk, + 5883 => Opcode::VCVT2PH2BF8SZ128rmbkz, + 5884 => Opcode::VCVT2PH2BF8SZ128rmk, + 5885 => Opcode::VCVT2PH2BF8SZ128rmkz, + 5886 => Opcode::VCVT2PH2BF8SZ128rr, + 5887 => Opcode::VCVT2PH2BF8SZ128rrk, + 5888 => Opcode::VCVT2PH2BF8SZ128rrkz, + 5889 => Opcode::VCVT2PH2BF8SZ256rm, + 5890 => Opcode::VCVT2PH2BF8SZ256rmb, + 5891 => Opcode::VCVT2PH2BF8SZ256rmbk, + 5892 => Opcode::VCVT2PH2BF8SZ256rmbkz, + 5893 => Opcode::VCVT2PH2BF8SZ256rmk, + 5894 => Opcode::VCVT2PH2BF8SZ256rmkz, + 5895 => Opcode::VCVT2PH2BF8SZ256rr, + 5896 => Opcode::VCVT2PH2BF8SZ256rrk, + 5897 => Opcode::VCVT2PH2BF8SZ256rrkz, + 5898 => Opcode::VCVT2PH2BF8SZrm, + 5899 => Opcode::VCVT2PH2BF8SZrmb, + 5900 => Opcode::VCVT2PH2BF8SZrmbk, + 5901 => Opcode::VCVT2PH2BF8SZrmbkz, + 5902 => Opcode::VCVT2PH2BF8SZrmk, + 5903 => Opcode::VCVT2PH2BF8SZrmkz, + 5904 => Opcode::VCVT2PH2BF8SZrr, + 5905 => Opcode::VCVT2PH2BF8SZrrk, + 5906 => Opcode::VCVT2PH2BF8SZrrkz, + 5907 => Opcode::VCVT2PH2BF8Z128rm, + 5908 => Opcode::VCVT2PH2BF8Z128rmb, + 5909 => Opcode::VCVT2PH2BF8Z128rmbk, + 5910 => Opcode::VCVT2PH2BF8Z128rmbkz, + 5911 => Opcode::VCVT2PH2BF8Z128rmk, + 5912 => Opcode::VCVT2PH2BF8Z128rmkz, + 5913 => Opcode::VCVT2PH2BF8Z128rr, + 5914 => Opcode::VCVT2PH2BF8Z128rrk, + 5915 => Opcode::VCVT2PH2BF8Z128rrkz, + 5916 => Opcode::VCVT2PH2BF8Z256rm, + 5917 => Opcode::VCVT2PH2BF8Z256rmb, + 5918 => Opcode::VCVT2PH2BF8Z256rmbk, + 5919 => Opcode::VCVT2PH2BF8Z256rmbkz, + 5920 => Opcode::VCVT2PH2BF8Z256rmk, + 5921 => Opcode::VCVT2PH2BF8Z256rmkz, + 5922 => Opcode::VCVT2PH2BF8Z256rr, + 5923 => Opcode::VCVT2PH2BF8Z256rrk, + 5924 => Opcode::VCVT2PH2BF8Z256rrkz, + 5925 => Opcode::VCVT2PH2BF8Zrm, + 5926 => Opcode::VCVT2PH2BF8Zrmb, + 5927 => Opcode::VCVT2PH2BF8Zrmbk, + 5928 => Opcode::VCVT2PH2BF8Zrmbkz, + 5929 => Opcode::VCVT2PH2BF8Zrmk, + 5930 => Opcode::VCVT2PH2BF8Zrmkz, + 5931 => Opcode::VCVT2PH2BF8Zrr, + 5932 => Opcode::VCVT2PH2BF8Zrrk, + 5933 => Opcode::VCVT2PH2BF8Zrrkz, + 5934 => Opcode::VCVT2PH2HF8SZ128rm, + 5935 => Opcode::VCVT2PH2HF8SZ128rmb, + 5936 => Opcode::VCVT2PH2HF8SZ128rmbk, + 5937 => Opcode::VCVT2PH2HF8SZ128rmbkz, + 5938 => Opcode::VCVT2PH2HF8SZ128rmk, + 5939 => Opcode::VCVT2PH2HF8SZ128rmkz, + 5940 => Opcode::VCVT2PH2HF8SZ128rr, + 5941 => Opcode::VCVT2PH2HF8SZ128rrk, + 5942 => Opcode::VCVT2PH2HF8SZ128rrkz, + 5943 => Opcode::VCVT2PH2HF8SZ256rm, + 5944 => Opcode::VCVT2PH2HF8SZ256rmb, + 5945 => Opcode::VCVT2PH2HF8SZ256rmbk, + 5946 => Opcode::VCVT2PH2HF8SZ256rmbkz, + 5947 => Opcode::VCVT2PH2HF8SZ256rmk, + 5948 => Opcode::VCVT2PH2HF8SZ256rmkz, + 5949 => Opcode::VCVT2PH2HF8SZ256rr, + 5950 => Opcode::VCVT2PH2HF8SZ256rrk, + 5951 => Opcode::VCVT2PH2HF8SZ256rrkz, + 5952 => Opcode::VCVT2PH2HF8SZrm, + 5953 => Opcode::VCVT2PH2HF8SZrmb, + 5954 => Opcode::VCVT2PH2HF8SZrmbk, + 5955 => Opcode::VCVT2PH2HF8SZrmbkz, + 5956 => Opcode::VCVT2PH2HF8SZrmk, + 5957 => Opcode::VCVT2PH2HF8SZrmkz, + 5958 => Opcode::VCVT2PH2HF8SZrr, + 5959 => Opcode::VCVT2PH2HF8SZrrk, + 5960 => Opcode::VCVT2PH2HF8SZrrkz, + 5961 => Opcode::VCVT2PH2HF8Z128rm, + 5962 => Opcode::VCVT2PH2HF8Z128rmb, + 5963 => Opcode::VCVT2PH2HF8Z128rmbk, + 5964 => Opcode::VCVT2PH2HF8Z128rmbkz, + 5965 => Opcode::VCVT2PH2HF8Z128rmk, + 5966 => Opcode::VCVT2PH2HF8Z128rmkz, + 5967 => Opcode::VCVT2PH2HF8Z128rr, + 5968 => Opcode::VCVT2PH2HF8Z128rrk, + 5969 => Opcode::VCVT2PH2HF8Z128rrkz, + 5970 => Opcode::VCVT2PH2HF8Z256rm, + 5971 => Opcode::VCVT2PH2HF8Z256rmb, + 5972 => Opcode::VCVT2PH2HF8Z256rmbk, + 5973 => Opcode::VCVT2PH2HF8Z256rmbkz, + 5974 => Opcode::VCVT2PH2HF8Z256rmk, + 5975 => Opcode::VCVT2PH2HF8Z256rmkz, + 5976 => Opcode::VCVT2PH2HF8Z256rr, + 5977 => Opcode::VCVT2PH2HF8Z256rrk, + 5978 => Opcode::VCVT2PH2HF8Z256rrkz, + 5979 => Opcode::VCVT2PH2HF8Zrm, + 5980 => Opcode::VCVT2PH2HF8Zrmb, + 5981 => Opcode::VCVT2PH2HF8Zrmbk, + 5982 => Opcode::VCVT2PH2HF8Zrmbkz, + 5983 => Opcode::VCVT2PH2HF8Zrmk, + 5984 => Opcode::VCVT2PH2HF8Zrmkz, + 5985 => Opcode::VCVT2PH2HF8Zrr, + 5986 => Opcode::VCVT2PH2HF8Zrrk, + 5987 => Opcode::VCVT2PH2HF8Zrrkz, + 5988 => Opcode::VCVT2PS2PHXZ128rm, + 5989 => Opcode::VCVT2PS2PHXZ128rmb, + 5990 => Opcode::VCVT2PS2PHXZ128rmbk, + 5991 => Opcode::VCVT2PS2PHXZ128rmbkz, + 5992 => Opcode::VCVT2PS2PHXZ128rmk, + 5993 => Opcode::VCVT2PS2PHXZ128rmkz, + 5994 => Opcode::VCVT2PS2PHXZ128rr, + 5995 => Opcode::VCVT2PS2PHXZ128rrk, + 5996 => Opcode::VCVT2PS2PHXZ128rrkz, + 5997 => Opcode::VCVT2PS2PHXZ256rm, + 5998 => Opcode::VCVT2PS2PHXZ256rmb, + 5999 => Opcode::VCVT2PS2PHXZ256rmbk, + 6000 => Opcode::VCVT2PS2PHXZ256rmbkz, + 6001 => Opcode::VCVT2PS2PHXZ256rmk, + 6002 => Opcode::VCVT2PS2PHXZ256rmkz, + 6003 => Opcode::VCVT2PS2PHXZ256rr, + 6004 => Opcode::VCVT2PS2PHXZ256rrk, + 6005 => Opcode::VCVT2PS2PHXZ256rrkz, + 6006 => Opcode::VCVT2PS2PHXZrm, + 6007 => Opcode::VCVT2PS2PHXZrmb, + 6008 => Opcode::VCVT2PS2PHXZrmbk, + 6009 => Opcode::VCVT2PS2PHXZrmbkz, + 6010 => Opcode::VCVT2PS2PHXZrmk, + 6011 => Opcode::VCVT2PS2PHXZrmkz, + 6012 => Opcode::VCVT2PS2PHXZrr, + 6013 => Opcode::VCVT2PS2PHXZrrb, + 6014 => Opcode::VCVT2PS2PHXZrrbk, + 6015 => Opcode::VCVT2PS2PHXZrrbkz, + 6016 => Opcode::VCVT2PS2PHXZrrk, + 6017 => Opcode::VCVT2PS2PHXZrrkz, + 6018 => Opcode::VCVTBF162IBSZ128rm, + 6019 => Opcode::VCVTBF162IBSZ128rmb, + 6020 => Opcode::VCVTBF162IBSZ128rmbk, + 6021 => Opcode::VCVTBF162IBSZ128rmbkz, + 6022 => Opcode::VCVTBF162IBSZ128rmk, + 6023 => Opcode::VCVTBF162IBSZ128rmkz, + 6024 => Opcode::VCVTBF162IBSZ128rr, + 6025 => Opcode::VCVTBF162IBSZ128rrk, + 6026 => Opcode::VCVTBF162IBSZ128rrkz, + 6027 => Opcode::VCVTBF162IBSZ256rm, + 6028 => Opcode::VCVTBF162IBSZ256rmb, + 6029 => Opcode::VCVTBF162IBSZ256rmbk, + 6030 => Opcode::VCVTBF162IBSZ256rmbkz, + 6031 => Opcode::VCVTBF162IBSZ256rmk, + 6032 => Opcode::VCVTBF162IBSZ256rmkz, + 6033 => Opcode::VCVTBF162IBSZ256rr, + 6034 => Opcode::VCVTBF162IBSZ256rrk, + 6035 => Opcode::VCVTBF162IBSZ256rrkz, + 6036 => Opcode::VCVTBF162IBSZrm, + 6037 => Opcode::VCVTBF162IBSZrmb, + 6038 => Opcode::VCVTBF162IBSZrmbk, + 6039 => Opcode::VCVTBF162IBSZrmbkz, + 6040 => Opcode::VCVTBF162IBSZrmk, + 6041 => Opcode::VCVTBF162IBSZrmkz, + 6042 => Opcode::VCVTBF162IBSZrr, + 6043 => Opcode::VCVTBF162IBSZrrk, + 6044 => Opcode::VCVTBF162IBSZrrkz, + 6045 => Opcode::VCVTBF162IUBSZ128rm, + 6046 => Opcode::VCVTBF162IUBSZ128rmb, + 6047 => Opcode::VCVTBF162IUBSZ128rmbk, + 6048 => Opcode::VCVTBF162IUBSZ128rmbkz, + 6049 => Opcode::VCVTBF162IUBSZ128rmk, + 6050 => Opcode::VCVTBF162IUBSZ128rmkz, + 6051 => Opcode::VCVTBF162IUBSZ128rr, + 6052 => Opcode::VCVTBF162IUBSZ128rrk, + 6053 => Opcode::VCVTBF162IUBSZ128rrkz, + 6054 => Opcode::VCVTBF162IUBSZ256rm, + 6055 => Opcode::VCVTBF162IUBSZ256rmb, + 6056 => Opcode::VCVTBF162IUBSZ256rmbk, + 6057 => Opcode::VCVTBF162IUBSZ256rmbkz, + 6058 => Opcode::VCVTBF162IUBSZ256rmk, + 6059 => Opcode::VCVTBF162IUBSZ256rmkz, + 6060 => Opcode::VCVTBF162IUBSZ256rr, + 6061 => Opcode::VCVTBF162IUBSZ256rrk, + 6062 => Opcode::VCVTBF162IUBSZ256rrkz, + 6063 => Opcode::VCVTBF162IUBSZrm, + 6064 => Opcode::VCVTBF162IUBSZrmb, + 6065 => Opcode::VCVTBF162IUBSZrmbk, + 6066 => Opcode::VCVTBF162IUBSZrmbkz, + 6067 => Opcode::VCVTBF162IUBSZrmk, + 6068 => Opcode::VCVTBF162IUBSZrmkz, + 6069 => Opcode::VCVTBF162IUBSZrr, + 6070 => Opcode::VCVTBF162IUBSZrrk, + 6071 => Opcode::VCVTBF162IUBSZrrkz, + 6072 => Opcode::VCVTBIASPH2BF8SZ128rm, + 6073 => Opcode::VCVTBIASPH2BF8SZ128rmb, + 6074 => Opcode::VCVTBIASPH2BF8SZ128rmbk, + 6075 => Opcode::VCVTBIASPH2BF8SZ128rmbkz, + 6076 => Opcode::VCVTBIASPH2BF8SZ128rmk, + 6077 => Opcode::VCVTBIASPH2BF8SZ128rmkz, + 6078 => Opcode::VCVTBIASPH2BF8SZ128rr, + 6079 => Opcode::VCVTBIASPH2BF8SZ128rrk, + 6080 => Opcode::VCVTBIASPH2BF8SZ128rrkz, + 6081 => Opcode::VCVTBIASPH2BF8SZ256rm, + 6082 => Opcode::VCVTBIASPH2BF8SZ256rmb, + 6083 => Opcode::VCVTBIASPH2BF8SZ256rmbk, + 6084 => Opcode::VCVTBIASPH2BF8SZ256rmbkz, + 6085 => Opcode::VCVTBIASPH2BF8SZ256rmk, + 6086 => Opcode::VCVTBIASPH2BF8SZ256rmkz, + 6087 => Opcode::VCVTBIASPH2BF8SZ256rr, + 6088 => Opcode::VCVTBIASPH2BF8SZ256rrk, + 6089 => Opcode::VCVTBIASPH2BF8SZ256rrkz, + 6090 => Opcode::VCVTBIASPH2BF8SZrm, + 6091 => Opcode::VCVTBIASPH2BF8SZrmb, + 6092 => Opcode::VCVTBIASPH2BF8SZrmbk, + 6093 => Opcode::VCVTBIASPH2BF8SZrmbkz, + 6094 => Opcode::VCVTBIASPH2BF8SZrmk, + 6095 => Opcode::VCVTBIASPH2BF8SZrmkz, + 6096 => Opcode::VCVTBIASPH2BF8SZrr, + 6097 => Opcode::VCVTBIASPH2BF8SZrrk, + 6098 => Opcode::VCVTBIASPH2BF8SZrrkz, + 6099 => Opcode::VCVTBIASPH2BF8Z128rm, + 6100 => Opcode::VCVTBIASPH2BF8Z128rmb, + 6101 => Opcode::VCVTBIASPH2BF8Z128rmbk, + 6102 => Opcode::VCVTBIASPH2BF8Z128rmbkz, + 6103 => Opcode::VCVTBIASPH2BF8Z128rmk, + 6104 => Opcode::VCVTBIASPH2BF8Z128rmkz, + 6105 => Opcode::VCVTBIASPH2BF8Z128rr, + 6106 => Opcode::VCVTBIASPH2BF8Z128rrk, + 6107 => Opcode::VCVTBIASPH2BF8Z128rrkz, + 6108 => Opcode::VCVTBIASPH2BF8Z256rm, + 6109 => Opcode::VCVTBIASPH2BF8Z256rmb, + 6110 => Opcode::VCVTBIASPH2BF8Z256rmbk, + 6111 => Opcode::VCVTBIASPH2BF8Z256rmbkz, + 6112 => Opcode::VCVTBIASPH2BF8Z256rmk, + 6113 => Opcode::VCVTBIASPH2BF8Z256rmkz, + 6114 => Opcode::VCVTBIASPH2BF8Z256rr, + 6115 => Opcode::VCVTBIASPH2BF8Z256rrk, + 6116 => Opcode::VCVTBIASPH2BF8Z256rrkz, + 6117 => Opcode::VCVTBIASPH2BF8Zrm, + 6118 => Opcode::VCVTBIASPH2BF8Zrmb, + 6119 => Opcode::VCVTBIASPH2BF8Zrmbk, + 6120 => Opcode::VCVTBIASPH2BF8Zrmbkz, + 6121 => Opcode::VCVTBIASPH2BF8Zrmk, + 6122 => Opcode::VCVTBIASPH2BF8Zrmkz, + 6123 => Opcode::VCVTBIASPH2BF8Zrr, + 6124 => Opcode::VCVTBIASPH2BF8Zrrk, + 6125 => Opcode::VCVTBIASPH2BF8Zrrkz, + 6126 => Opcode::VCVTBIASPH2HF8SZ128rm, + 6127 => Opcode::VCVTBIASPH2HF8SZ128rmb, + 6128 => Opcode::VCVTBIASPH2HF8SZ128rmbk, + 6129 => Opcode::VCVTBIASPH2HF8SZ128rmbkz, + 6130 => Opcode::VCVTBIASPH2HF8SZ128rmk, + 6131 => Opcode::VCVTBIASPH2HF8SZ128rmkz, + 6132 => Opcode::VCVTBIASPH2HF8SZ128rr, + 6133 => Opcode::VCVTBIASPH2HF8SZ128rrk, + 6134 => Opcode::VCVTBIASPH2HF8SZ128rrkz, + 6135 => Opcode::VCVTBIASPH2HF8SZ256rm, + 6136 => Opcode::VCVTBIASPH2HF8SZ256rmb, + 6137 => Opcode::VCVTBIASPH2HF8SZ256rmbk, + 6138 => Opcode::VCVTBIASPH2HF8SZ256rmbkz, + 6139 => Opcode::VCVTBIASPH2HF8SZ256rmk, + 6140 => Opcode::VCVTBIASPH2HF8SZ256rmkz, + 6141 => Opcode::VCVTBIASPH2HF8SZ256rr, + 6142 => Opcode::VCVTBIASPH2HF8SZ256rrk, + 6143 => Opcode::VCVTBIASPH2HF8SZ256rrkz, + 6144 => Opcode::VCVTBIASPH2HF8SZrm, + 6145 => Opcode::VCVTBIASPH2HF8SZrmb, + 6146 => Opcode::VCVTBIASPH2HF8SZrmbk, + 6147 => Opcode::VCVTBIASPH2HF8SZrmbkz, + 6148 => Opcode::VCVTBIASPH2HF8SZrmk, + 6149 => Opcode::VCVTBIASPH2HF8SZrmkz, + 6150 => Opcode::VCVTBIASPH2HF8SZrr, + 6151 => Opcode::VCVTBIASPH2HF8SZrrk, + 6152 => Opcode::VCVTBIASPH2HF8SZrrkz, + 6153 => Opcode::VCVTBIASPH2HF8Z128rm, + 6154 => Opcode::VCVTBIASPH2HF8Z128rmb, + 6155 => Opcode::VCVTBIASPH2HF8Z128rmbk, + 6156 => Opcode::VCVTBIASPH2HF8Z128rmbkz, + 6157 => Opcode::VCVTBIASPH2HF8Z128rmk, + 6158 => Opcode::VCVTBIASPH2HF8Z128rmkz, + 6159 => Opcode::VCVTBIASPH2HF8Z128rr, + 6160 => Opcode::VCVTBIASPH2HF8Z128rrk, + 6161 => Opcode::VCVTBIASPH2HF8Z128rrkz, + 6162 => Opcode::VCVTBIASPH2HF8Z256rm, + 6163 => Opcode::VCVTBIASPH2HF8Z256rmb, + 6164 => Opcode::VCVTBIASPH2HF8Z256rmbk, + 6165 => Opcode::VCVTBIASPH2HF8Z256rmbkz, + 6166 => Opcode::VCVTBIASPH2HF8Z256rmk, + 6167 => Opcode::VCVTBIASPH2HF8Z256rmkz, + 6168 => Opcode::VCVTBIASPH2HF8Z256rr, + 6169 => Opcode::VCVTBIASPH2HF8Z256rrk, + 6170 => Opcode::VCVTBIASPH2HF8Z256rrkz, + 6171 => Opcode::VCVTBIASPH2HF8Zrm, + 6172 => Opcode::VCVTBIASPH2HF8Zrmb, + 6173 => Opcode::VCVTBIASPH2HF8Zrmbk, + 6174 => Opcode::VCVTBIASPH2HF8Zrmbkz, + 6175 => Opcode::VCVTBIASPH2HF8Zrmk, + 6176 => Opcode::VCVTBIASPH2HF8Zrmkz, + 6177 => Opcode::VCVTBIASPH2HF8Zrr, + 6178 => Opcode::VCVTBIASPH2HF8Zrrk, + 6179 => Opcode::VCVTBIASPH2HF8Zrrkz, + 6180 => Opcode::VCVTDQ2PDYrm, + 6181 => Opcode::VCVTDQ2PDYrr, + 6182 => Opcode::VCVTDQ2PDZ128rm, + 6183 => Opcode::VCVTDQ2PDZ128rmb, + 6184 => Opcode::VCVTDQ2PDZ128rmbk, + 6185 => Opcode::VCVTDQ2PDZ128rmbkz, + 6186 => Opcode::VCVTDQ2PDZ128rmk, + 6187 => Opcode::VCVTDQ2PDZ128rmkz, + 6188 => Opcode::VCVTDQ2PDZ128rr, + 6189 => Opcode::VCVTDQ2PDZ128rrk, + 6190 => Opcode::VCVTDQ2PDZ128rrkz, + 6191 => Opcode::VCVTDQ2PDZ256rm, + 6192 => Opcode::VCVTDQ2PDZ256rmb, + 6193 => Opcode::VCVTDQ2PDZ256rmbk, + 6194 => Opcode::VCVTDQ2PDZ256rmbkz, + 6195 => Opcode::VCVTDQ2PDZ256rmk, + 6196 => Opcode::VCVTDQ2PDZ256rmkz, + 6197 => Opcode::VCVTDQ2PDZ256rr, + 6198 => Opcode::VCVTDQ2PDZ256rrk, + 6199 => Opcode::VCVTDQ2PDZ256rrkz, + 6200 => Opcode::VCVTDQ2PDZrm, + 6201 => Opcode::VCVTDQ2PDZrmb, + 6202 => Opcode::VCVTDQ2PDZrmbk, + 6203 => Opcode::VCVTDQ2PDZrmbkz, + 6204 => Opcode::VCVTDQ2PDZrmk, + 6205 => Opcode::VCVTDQ2PDZrmkz, + 6206 => Opcode::VCVTDQ2PDZrr, + 6207 => Opcode::VCVTDQ2PDZrrk, + 6208 => Opcode::VCVTDQ2PDZrrkz, + 6209 => Opcode::VCVTDQ2PDrm, + 6210 => Opcode::VCVTDQ2PDrr, + 6211 => Opcode::VCVTDQ2PHZ128rm, + 6212 => Opcode::VCVTDQ2PHZ128rmb, + 6213 => Opcode::VCVTDQ2PHZ128rmbk, + 6214 => Opcode::VCVTDQ2PHZ128rmbkz, + 6215 => Opcode::VCVTDQ2PHZ128rmk, + 6216 => Opcode::VCVTDQ2PHZ128rmkz, + 6217 => Opcode::VCVTDQ2PHZ128rr, + 6218 => Opcode::VCVTDQ2PHZ128rrk, + 6219 => Opcode::VCVTDQ2PHZ128rrkz, + 6220 => Opcode::VCVTDQ2PHZ256rm, + 6221 => Opcode::VCVTDQ2PHZ256rmb, + 6222 => Opcode::VCVTDQ2PHZ256rmbk, + 6223 => Opcode::VCVTDQ2PHZ256rmbkz, + 6224 => Opcode::VCVTDQ2PHZ256rmk, + 6225 => Opcode::VCVTDQ2PHZ256rmkz, + 6226 => Opcode::VCVTDQ2PHZ256rr, + 6227 => Opcode::VCVTDQ2PHZ256rrk, + 6228 => Opcode::VCVTDQ2PHZ256rrkz, + 6229 => Opcode::VCVTDQ2PHZrm, + 6230 => Opcode::VCVTDQ2PHZrmb, + 6231 => Opcode::VCVTDQ2PHZrmbk, + 6232 => Opcode::VCVTDQ2PHZrmbkz, + 6233 => Opcode::VCVTDQ2PHZrmk, + 6234 => Opcode::VCVTDQ2PHZrmkz, + 6235 => Opcode::VCVTDQ2PHZrr, + 6236 => Opcode::VCVTDQ2PHZrrb, + 6237 => Opcode::VCVTDQ2PHZrrbk, + 6238 => Opcode::VCVTDQ2PHZrrbkz, + 6239 => Opcode::VCVTDQ2PHZrrk, + 6240 => Opcode::VCVTDQ2PHZrrkz, + 6241 => Opcode::VCVTDQ2PSYrm, + 6242 => Opcode::VCVTDQ2PSYrr, + 6243 => Opcode::VCVTDQ2PSZ128rm, + 6244 => Opcode::VCVTDQ2PSZ128rmb, + 6245 => Opcode::VCVTDQ2PSZ128rmbk, + 6246 => Opcode::VCVTDQ2PSZ128rmbkz, + 6247 => Opcode::VCVTDQ2PSZ128rmk, + 6248 => Opcode::VCVTDQ2PSZ128rmkz, + 6249 => Opcode::VCVTDQ2PSZ128rr, + 6250 => Opcode::VCVTDQ2PSZ128rrk, + 6251 => Opcode::VCVTDQ2PSZ128rrkz, + 6252 => Opcode::VCVTDQ2PSZ256rm, + 6253 => Opcode::VCVTDQ2PSZ256rmb, + 6254 => Opcode::VCVTDQ2PSZ256rmbk, + 6255 => Opcode::VCVTDQ2PSZ256rmbkz, + 6256 => Opcode::VCVTDQ2PSZ256rmk, + 6257 => Opcode::VCVTDQ2PSZ256rmkz, + 6258 => Opcode::VCVTDQ2PSZ256rr, + 6259 => Opcode::VCVTDQ2PSZ256rrk, + 6260 => Opcode::VCVTDQ2PSZ256rrkz, + 6261 => Opcode::VCVTDQ2PSZrm, + 6262 => Opcode::VCVTDQ2PSZrmb, + 6263 => Opcode::VCVTDQ2PSZrmbk, + 6264 => Opcode::VCVTDQ2PSZrmbkz, + 6265 => Opcode::VCVTDQ2PSZrmk, + 6266 => Opcode::VCVTDQ2PSZrmkz, + 6267 => Opcode::VCVTDQ2PSZrr, + 6268 => Opcode::VCVTDQ2PSZrrb, + 6269 => Opcode::VCVTDQ2PSZrrbk, + 6270 => Opcode::VCVTDQ2PSZrrbkz, + 6271 => Opcode::VCVTDQ2PSZrrk, + 6272 => Opcode::VCVTDQ2PSZrrkz, + 6273 => Opcode::VCVTDQ2PSrm, + 6274 => Opcode::VCVTDQ2PSrr, + 6275 => Opcode::VCVTHF82PHZ128rm, + 6276 => Opcode::VCVTHF82PHZ128rmk, + 6277 => Opcode::VCVTHF82PHZ128rmkz, + 6278 => Opcode::VCVTHF82PHZ128rr, + 6279 => Opcode::VCVTHF82PHZ128rrk, + 6280 => Opcode::VCVTHF82PHZ128rrkz, + 6281 => Opcode::VCVTHF82PHZ256rm, + 6282 => Opcode::VCVTHF82PHZ256rmk, + 6283 => Opcode::VCVTHF82PHZ256rmkz, + 6284 => Opcode::VCVTHF82PHZ256rr, + 6285 => Opcode::VCVTHF82PHZ256rrk, + 6286 => Opcode::VCVTHF82PHZ256rrkz, + 6287 => Opcode::VCVTHF82PHZrm, + 6288 => Opcode::VCVTHF82PHZrmk, + 6289 => Opcode::VCVTHF82PHZrmkz, + 6290 => Opcode::VCVTHF82PHZrr, + 6291 => Opcode::VCVTHF82PHZrrk, + 6292 => Opcode::VCVTHF82PHZrrkz, + 6293 => Opcode::VCVTNE2PS2BF16Z128rm, + 6294 => Opcode::VCVTNE2PS2BF16Z128rmb, + 6295 => Opcode::VCVTNE2PS2BF16Z128rmbk, + 6296 => Opcode::VCVTNE2PS2BF16Z128rmbkz, + 6297 => Opcode::VCVTNE2PS2BF16Z128rmk, + 6298 => Opcode::VCVTNE2PS2BF16Z128rmkz, + 6299 => Opcode::VCVTNE2PS2BF16Z128rr, + 6300 => Opcode::VCVTNE2PS2BF16Z128rrk, + 6301 => Opcode::VCVTNE2PS2BF16Z128rrkz, + 6302 => Opcode::VCVTNE2PS2BF16Z256rm, + 6303 => Opcode::VCVTNE2PS2BF16Z256rmb, + 6304 => Opcode::VCVTNE2PS2BF16Z256rmbk, + 6305 => Opcode::VCVTNE2PS2BF16Z256rmbkz, + 6306 => Opcode::VCVTNE2PS2BF16Z256rmk, + 6307 => Opcode::VCVTNE2PS2BF16Z256rmkz, + 6308 => Opcode::VCVTNE2PS2BF16Z256rr, + 6309 => Opcode::VCVTNE2PS2BF16Z256rrk, + 6310 => Opcode::VCVTNE2PS2BF16Z256rrkz, + 6311 => Opcode::VCVTNE2PS2BF16Zrm, + 6312 => Opcode::VCVTNE2PS2BF16Zrmb, + 6313 => Opcode::VCVTNE2PS2BF16Zrmbk, + 6314 => Opcode::VCVTNE2PS2BF16Zrmbkz, + 6315 => Opcode::VCVTNE2PS2BF16Zrmk, + 6316 => Opcode::VCVTNE2PS2BF16Zrmkz, + 6317 => Opcode::VCVTNE2PS2BF16Zrr, + 6318 => Opcode::VCVTNE2PS2BF16Zrrk, + 6319 => Opcode::VCVTNE2PS2BF16Zrrkz, + 6320 => Opcode::VCVTNEEBF162PSYrm, + 6321 => Opcode::VCVTNEEBF162PSrm, + 6322 => Opcode::VCVTNEEPH2PSYrm, + 6323 => Opcode::VCVTNEEPH2PSrm, + 6324 => Opcode::VCVTNEOBF162PSYrm, + 6325 => Opcode::VCVTNEOBF162PSrm, + 6326 => Opcode::VCVTNEOPH2PSYrm, + 6327 => Opcode::VCVTNEOPH2PSrm, + 6328 => Opcode::VCVTNEPS2BF16Yrm, + 6329 => Opcode::VCVTNEPS2BF16Yrr, + 6330 => Opcode::VCVTNEPS2BF16Z128rm, + 6331 => Opcode::VCVTNEPS2BF16Z128rmb, + 6332 => Opcode::VCVTNEPS2BF16Z128rmbk, + 6333 => Opcode::VCVTNEPS2BF16Z128rmbkz, + 6334 => Opcode::VCVTNEPS2BF16Z128rmk, + 6335 => Opcode::VCVTNEPS2BF16Z128rmkz, + 6336 => Opcode::VCVTNEPS2BF16Z128rr, + 6337 => Opcode::VCVTNEPS2BF16Z128rrk, + 6338 => Opcode::VCVTNEPS2BF16Z128rrkz, + 6339 => Opcode::VCVTNEPS2BF16Z256rm, + 6340 => Opcode::VCVTNEPS2BF16Z256rmb, + 6341 => Opcode::VCVTNEPS2BF16Z256rmbk, + 6342 => Opcode::VCVTNEPS2BF16Z256rmbkz, + 6343 => Opcode::VCVTNEPS2BF16Z256rmk, + 6344 => Opcode::VCVTNEPS2BF16Z256rmkz, + 6345 => Opcode::VCVTNEPS2BF16Z256rr, + 6346 => Opcode::VCVTNEPS2BF16Z256rrk, + 6347 => Opcode::VCVTNEPS2BF16Z256rrkz, + 6348 => Opcode::VCVTNEPS2BF16Zrm, + 6349 => Opcode::VCVTNEPS2BF16Zrmb, + 6350 => Opcode::VCVTNEPS2BF16Zrmbk, + 6351 => Opcode::VCVTNEPS2BF16Zrmbkz, + 6352 => Opcode::VCVTNEPS2BF16Zrmk, + 6353 => Opcode::VCVTNEPS2BF16Zrmkz, + 6354 => Opcode::VCVTNEPS2BF16Zrr, + 6355 => Opcode::VCVTNEPS2BF16Zrrk, + 6356 => Opcode::VCVTNEPS2BF16Zrrkz, + 6357 => Opcode::VCVTNEPS2BF16rm, + 6358 => Opcode::VCVTNEPS2BF16rr, + 6359 => Opcode::VCVTPD2DQYrm, + 6360 => Opcode::VCVTPD2DQYrr, + 6361 => Opcode::VCVTPD2DQZ128rm, + 6362 => Opcode::VCVTPD2DQZ128rmb, + 6363 => Opcode::VCVTPD2DQZ128rmbk, + 6364 => Opcode::VCVTPD2DQZ128rmbkz, + 6365 => Opcode::VCVTPD2DQZ128rmk, + 6366 => Opcode::VCVTPD2DQZ128rmkz, + 6367 => Opcode::VCVTPD2DQZ128rr, + 6368 => Opcode::VCVTPD2DQZ128rrk, + 6369 => Opcode::VCVTPD2DQZ128rrkz, + 6370 => Opcode::VCVTPD2DQZ256rm, + 6371 => Opcode::VCVTPD2DQZ256rmb, + 6372 => Opcode::VCVTPD2DQZ256rmbk, + 6373 => Opcode::VCVTPD2DQZ256rmbkz, + 6374 => Opcode::VCVTPD2DQZ256rmk, + 6375 => Opcode::VCVTPD2DQZ256rmkz, + 6376 => Opcode::VCVTPD2DQZ256rr, + 6377 => Opcode::VCVTPD2DQZ256rrk, + 6378 => Opcode::VCVTPD2DQZ256rrkz, + 6379 => Opcode::VCVTPD2DQZrm, + 6380 => Opcode::VCVTPD2DQZrmb, + 6381 => Opcode::VCVTPD2DQZrmbk, + 6382 => Opcode::VCVTPD2DQZrmbkz, + 6383 => Opcode::VCVTPD2DQZrmk, + 6384 => Opcode::VCVTPD2DQZrmkz, + 6385 => Opcode::VCVTPD2DQZrr, + 6386 => Opcode::VCVTPD2DQZrrb, + 6387 => Opcode::VCVTPD2DQZrrbk, + 6388 => Opcode::VCVTPD2DQZrrbkz, + 6389 => Opcode::VCVTPD2DQZrrk, + 6390 => Opcode::VCVTPD2DQZrrkz, + 6391 => Opcode::VCVTPD2DQrm, + 6392 => Opcode::VCVTPD2DQrr, + 6393 => Opcode::VCVTPD2PHZ128rm, + 6394 => Opcode::VCVTPD2PHZ128rmb, + 6395 => Opcode::VCVTPD2PHZ128rmbk, + 6396 => Opcode::VCVTPD2PHZ128rmbkz, + 6397 => Opcode::VCVTPD2PHZ128rmk, + 6398 => Opcode::VCVTPD2PHZ128rmkz, + 6399 => Opcode::VCVTPD2PHZ128rr, + 6400 => Opcode::VCVTPD2PHZ128rrk, + 6401 => Opcode::VCVTPD2PHZ128rrkz, + 6402 => Opcode::VCVTPD2PHZ256rm, + 6403 => Opcode::VCVTPD2PHZ256rmb, + 6404 => Opcode::VCVTPD2PHZ256rmbk, + 6405 => Opcode::VCVTPD2PHZ256rmbkz, + 6406 => Opcode::VCVTPD2PHZ256rmk, + 6407 => Opcode::VCVTPD2PHZ256rmkz, + 6408 => Opcode::VCVTPD2PHZ256rr, + 6409 => Opcode::VCVTPD2PHZ256rrk, + 6410 => Opcode::VCVTPD2PHZ256rrkz, + 6411 => Opcode::VCVTPD2PHZrm, + 6412 => Opcode::VCVTPD2PHZrmb, + 6413 => Opcode::VCVTPD2PHZrmbk, + 6414 => Opcode::VCVTPD2PHZrmbkz, + 6415 => Opcode::VCVTPD2PHZrmk, + 6416 => Opcode::VCVTPD2PHZrmkz, + 6417 => Opcode::VCVTPD2PHZrr, + 6418 => Opcode::VCVTPD2PHZrrb, + 6419 => Opcode::VCVTPD2PHZrrbk, + 6420 => Opcode::VCVTPD2PHZrrbkz, + 6421 => Opcode::VCVTPD2PHZrrk, + 6422 => Opcode::VCVTPD2PHZrrkz, + 6423 => Opcode::VCVTPD2PSYrm, + 6424 => Opcode::VCVTPD2PSYrr, + 6425 => Opcode::VCVTPD2PSZ128rm, + 6426 => Opcode::VCVTPD2PSZ128rmb, + 6427 => Opcode::VCVTPD2PSZ128rmbk, + 6428 => Opcode::VCVTPD2PSZ128rmbkz, + 6429 => Opcode::VCVTPD2PSZ128rmk, + 6430 => Opcode::VCVTPD2PSZ128rmkz, + 6431 => Opcode::VCVTPD2PSZ128rr, + 6432 => Opcode::VCVTPD2PSZ128rrk, + 6433 => Opcode::VCVTPD2PSZ128rrkz, + 6434 => Opcode::VCVTPD2PSZ256rm, + 6435 => Opcode::VCVTPD2PSZ256rmb, + 6436 => Opcode::VCVTPD2PSZ256rmbk, + 6437 => Opcode::VCVTPD2PSZ256rmbkz, + 6438 => Opcode::VCVTPD2PSZ256rmk, + 6439 => Opcode::VCVTPD2PSZ256rmkz, + 6440 => Opcode::VCVTPD2PSZ256rr, + 6441 => Opcode::VCVTPD2PSZ256rrk, + 6442 => Opcode::VCVTPD2PSZ256rrkz, + 6443 => Opcode::VCVTPD2PSZrm, + 6444 => Opcode::VCVTPD2PSZrmb, + 6445 => Opcode::VCVTPD2PSZrmbk, + 6446 => Opcode::VCVTPD2PSZrmbkz, + 6447 => Opcode::VCVTPD2PSZrmk, + 6448 => Opcode::VCVTPD2PSZrmkz, + 6449 => Opcode::VCVTPD2PSZrr, + 6450 => Opcode::VCVTPD2PSZrrb, + 6451 => Opcode::VCVTPD2PSZrrbk, + 6452 => Opcode::VCVTPD2PSZrrbkz, + 6453 => Opcode::VCVTPD2PSZrrk, + 6454 => Opcode::VCVTPD2PSZrrkz, + 6455 => Opcode::VCVTPD2PSrm, + 6456 => Opcode::VCVTPD2PSrr, + 6457 => Opcode::VCVTPD2QQZ128rm, + 6458 => Opcode::VCVTPD2QQZ128rmb, + 6459 => Opcode::VCVTPD2QQZ128rmbk, + 6460 => Opcode::VCVTPD2QQZ128rmbkz, + 6461 => Opcode::VCVTPD2QQZ128rmk, + 6462 => Opcode::VCVTPD2QQZ128rmkz, + 6463 => Opcode::VCVTPD2QQZ128rr, + 6464 => Opcode::VCVTPD2QQZ128rrk, + 6465 => Opcode::VCVTPD2QQZ128rrkz, + 6466 => Opcode::VCVTPD2QQZ256rm, + 6467 => Opcode::VCVTPD2QQZ256rmb, + 6468 => Opcode::VCVTPD2QQZ256rmbk, + 6469 => Opcode::VCVTPD2QQZ256rmbkz, + 6470 => Opcode::VCVTPD2QQZ256rmk, + 6471 => Opcode::VCVTPD2QQZ256rmkz, + 6472 => Opcode::VCVTPD2QQZ256rr, + 6473 => Opcode::VCVTPD2QQZ256rrk, + 6474 => Opcode::VCVTPD2QQZ256rrkz, + 6475 => Opcode::VCVTPD2QQZrm, + 6476 => Opcode::VCVTPD2QQZrmb, + 6477 => Opcode::VCVTPD2QQZrmbk, + 6478 => Opcode::VCVTPD2QQZrmbkz, + 6479 => Opcode::VCVTPD2QQZrmk, + 6480 => Opcode::VCVTPD2QQZrmkz, + 6481 => Opcode::VCVTPD2QQZrr, + 6482 => Opcode::VCVTPD2QQZrrb, + 6483 => Opcode::VCVTPD2QQZrrbk, + 6484 => Opcode::VCVTPD2QQZrrbkz, + 6485 => Opcode::VCVTPD2QQZrrk, + 6486 => Opcode::VCVTPD2QQZrrkz, + 6487 => Opcode::VCVTPD2UDQZ128rm, + 6488 => Opcode::VCVTPD2UDQZ128rmb, + 6489 => Opcode::VCVTPD2UDQZ128rmbk, + 6490 => Opcode::VCVTPD2UDQZ128rmbkz, + 6491 => Opcode::VCVTPD2UDQZ128rmk, + 6492 => Opcode::VCVTPD2UDQZ128rmkz, + 6493 => Opcode::VCVTPD2UDQZ128rr, + 6494 => Opcode::VCVTPD2UDQZ128rrk, + 6495 => Opcode::VCVTPD2UDQZ128rrkz, + 6496 => Opcode::VCVTPD2UDQZ256rm, + 6497 => Opcode::VCVTPD2UDQZ256rmb, + 6498 => Opcode::VCVTPD2UDQZ256rmbk, + 6499 => Opcode::VCVTPD2UDQZ256rmbkz, + 6500 => Opcode::VCVTPD2UDQZ256rmk, + 6501 => Opcode::VCVTPD2UDQZ256rmkz, + 6502 => Opcode::VCVTPD2UDQZ256rr, + 6503 => Opcode::VCVTPD2UDQZ256rrk, + 6504 => Opcode::VCVTPD2UDQZ256rrkz, + 6505 => Opcode::VCVTPD2UDQZrm, + 6506 => Opcode::VCVTPD2UDQZrmb, + 6507 => Opcode::VCVTPD2UDQZrmbk, + 6508 => Opcode::VCVTPD2UDQZrmbkz, + 6509 => Opcode::VCVTPD2UDQZrmk, + 6510 => Opcode::VCVTPD2UDQZrmkz, + 6511 => Opcode::VCVTPD2UDQZrr, + 6512 => Opcode::VCVTPD2UDQZrrb, + 6513 => Opcode::VCVTPD2UDQZrrbk, + 6514 => Opcode::VCVTPD2UDQZrrbkz, + 6515 => Opcode::VCVTPD2UDQZrrk, + 6516 => Opcode::VCVTPD2UDQZrrkz, + 6517 => Opcode::VCVTPD2UQQZ128rm, + 6518 => Opcode::VCVTPD2UQQZ128rmb, + 6519 => Opcode::VCVTPD2UQQZ128rmbk, + 6520 => Opcode::VCVTPD2UQQZ128rmbkz, + 6521 => Opcode::VCVTPD2UQQZ128rmk, + 6522 => Opcode::VCVTPD2UQQZ128rmkz, + 6523 => Opcode::VCVTPD2UQQZ128rr, + 6524 => Opcode::VCVTPD2UQQZ128rrk, + 6525 => Opcode::VCVTPD2UQQZ128rrkz, + 6526 => Opcode::VCVTPD2UQQZ256rm, + 6527 => Opcode::VCVTPD2UQQZ256rmb, + 6528 => Opcode::VCVTPD2UQQZ256rmbk, + 6529 => Opcode::VCVTPD2UQQZ256rmbkz, + 6530 => Opcode::VCVTPD2UQQZ256rmk, + 6531 => Opcode::VCVTPD2UQQZ256rmkz, + 6532 => Opcode::VCVTPD2UQQZ256rr, + 6533 => Opcode::VCVTPD2UQQZ256rrk, + 6534 => Opcode::VCVTPD2UQQZ256rrkz, + 6535 => Opcode::VCVTPD2UQQZrm, + 6536 => Opcode::VCVTPD2UQQZrmb, + 6537 => Opcode::VCVTPD2UQQZrmbk, + 6538 => Opcode::VCVTPD2UQQZrmbkz, + 6539 => Opcode::VCVTPD2UQQZrmk, + 6540 => Opcode::VCVTPD2UQQZrmkz, + 6541 => Opcode::VCVTPD2UQQZrr, + 6542 => Opcode::VCVTPD2UQQZrrb, + 6543 => Opcode::VCVTPD2UQQZrrbk, + 6544 => Opcode::VCVTPD2UQQZrrbkz, + 6545 => Opcode::VCVTPD2UQQZrrk, + 6546 => Opcode::VCVTPD2UQQZrrkz, + 6547 => Opcode::VCVTPH2BF8SZ128rm, + 6548 => Opcode::VCVTPH2BF8SZ128rmb, + 6549 => Opcode::VCVTPH2BF8SZ128rmbk, + 6550 => Opcode::VCVTPH2BF8SZ128rmbkz, + 6551 => Opcode::VCVTPH2BF8SZ128rmk, + 6552 => Opcode::VCVTPH2BF8SZ128rmkz, + 6553 => Opcode::VCVTPH2BF8SZ128rr, + 6554 => Opcode::VCVTPH2BF8SZ128rrk, + 6555 => Opcode::VCVTPH2BF8SZ128rrkz, + 6556 => Opcode::VCVTPH2BF8SZ256rm, + 6557 => Opcode::VCVTPH2BF8SZ256rmb, + 6558 => Opcode::VCVTPH2BF8SZ256rmbk, + 6559 => Opcode::VCVTPH2BF8SZ256rmbkz, + 6560 => Opcode::VCVTPH2BF8SZ256rmk, + 6561 => Opcode::VCVTPH2BF8SZ256rmkz, + 6562 => Opcode::VCVTPH2BF8SZ256rr, + 6563 => Opcode::VCVTPH2BF8SZ256rrk, + 6564 => Opcode::VCVTPH2BF8SZ256rrkz, + 6565 => Opcode::VCVTPH2BF8SZrm, + 6566 => Opcode::VCVTPH2BF8SZrmb, + 6567 => Opcode::VCVTPH2BF8SZrmbk, + 6568 => Opcode::VCVTPH2BF8SZrmbkz, + 6569 => Opcode::VCVTPH2BF8SZrmk, + 6570 => Opcode::VCVTPH2BF8SZrmkz, + 6571 => Opcode::VCVTPH2BF8SZrr, + 6572 => Opcode::VCVTPH2BF8SZrrk, + 6573 => Opcode::VCVTPH2BF8SZrrkz, + 6574 => Opcode::VCVTPH2BF8Z128rm, + 6575 => Opcode::VCVTPH2BF8Z128rmb, + 6576 => Opcode::VCVTPH2BF8Z128rmbk, + 6577 => Opcode::VCVTPH2BF8Z128rmbkz, + 6578 => Opcode::VCVTPH2BF8Z128rmk, + 6579 => Opcode::VCVTPH2BF8Z128rmkz, + 6580 => Opcode::VCVTPH2BF8Z128rr, + 6581 => Opcode::VCVTPH2BF8Z128rrk, + 6582 => Opcode::VCVTPH2BF8Z128rrkz, + 6583 => Opcode::VCVTPH2BF8Z256rm, + 6584 => Opcode::VCVTPH2BF8Z256rmb, + 6585 => Opcode::VCVTPH2BF8Z256rmbk, + 6586 => Opcode::VCVTPH2BF8Z256rmbkz, + 6587 => Opcode::VCVTPH2BF8Z256rmk, + 6588 => Opcode::VCVTPH2BF8Z256rmkz, + 6589 => Opcode::VCVTPH2BF8Z256rr, + 6590 => Opcode::VCVTPH2BF8Z256rrk, + 6591 => Opcode::VCVTPH2BF8Z256rrkz, + 6592 => Opcode::VCVTPH2BF8Zrm, + 6593 => Opcode::VCVTPH2BF8Zrmb, + 6594 => Opcode::VCVTPH2BF8Zrmbk, + 6595 => Opcode::VCVTPH2BF8Zrmbkz, + 6596 => Opcode::VCVTPH2BF8Zrmk, + 6597 => Opcode::VCVTPH2BF8Zrmkz, + 6598 => Opcode::VCVTPH2BF8Zrr, + 6599 => Opcode::VCVTPH2BF8Zrrk, + 6600 => Opcode::VCVTPH2BF8Zrrkz, + 6601 => Opcode::VCVTPH2DQZ128rm, + 6602 => Opcode::VCVTPH2DQZ128rmb, + 6603 => Opcode::VCVTPH2DQZ128rmbk, + 6604 => Opcode::VCVTPH2DQZ128rmbkz, + 6605 => Opcode::VCVTPH2DQZ128rmk, + 6606 => Opcode::VCVTPH2DQZ128rmkz, + 6607 => Opcode::VCVTPH2DQZ128rr, + 6608 => Opcode::VCVTPH2DQZ128rrk, + 6609 => Opcode::VCVTPH2DQZ128rrkz, + 6610 => Opcode::VCVTPH2DQZ256rm, + 6611 => Opcode::VCVTPH2DQZ256rmb, + 6612 => Opcode::VCVTPH2DQZ256rmbk, + 6613 => Opcode::VCVTPH2DQZ256rmbkz, + 6614 => Opcode::VCVTPH2DQZ256rmk, + 6615 => Opcode::VCVTPH2DQZ256rmkz, + 6616 => Opcode::VCVTPH2DQZ256rr, + 6617 => Opcode::VCVTPH2DQZ256rrk, + 6618 => Opcode::VCVTPH2DQZ256rrkz, + 6619 => Opcode::VCVTPH2DQZrm, + 6620 => Opcode::VCVTPH2DQZrmb, + 6621 => Opcode::VCVTPH2DQZrmbk, + 6622 => Opcode::VCVTPH2DQZrmbkz, + 6623 => Opcode::VCVTPH2DQZrmk, + 6624 => Opcode::VCVTPH2DQZrmkz, + 6625 => Opcode::VCVTPH2DQZrr, + 6626 => Opcode::VCVTPH2DQZrrb, + 6627 => Opcode::VCVTPH2DQZrrbk, + 6628 => Opcode::VCVTPH2DQZrrbkz, + 6629 => Opcode::VCVTPH2DQZrrk, + 6630 => Opcode::VCVTPH2DQZrrkz, + 6631 => Opcode::VCVTPH2HF8SZ128rm, + 6632 => Opcode::VCVTPH2HF8SZ128rmb, + 6633 => Opcode::VCVTPH2HF8SZ128rmbk, + 6634 => Opcode::VCVTPH2HF8SZ128rmbkz, + 6635 => Opcode::VCVTPH2HF8SZ128rmk, + 6636 => Opcode::VCVTPH2HF8SZ128rmkz, + 6637 => Opcode::VCVTPH2HF8SZ128rr, + 6638 => Opcode::VCVTPH2HF8SZ128rrk, + 6639 => Opcode::VCVTPH2HF8SZ128rrkz, + 6640 => Opcode::VCVTPH2HF8SZ256rm, + 6641 => Opcode::VCVTPH2HF8SZ256rmb, + 6642 => Opcode::VCVTPH2HF8SZ256rmbk, + 6643 => Opcode::VCVTPH2HF8SZ256rmbkz, + 6644 => Opcode::VCVTPH2HF8SZ256rmk, + 6645 => Opcode::VCVTPH2HF8SZ256rmkz, + 6646 => Opcode::VCVTPH2HF8SZ256rr, + 6647 => Opcode::VCVTPH2HF8SZ256rrk, + 6648 => Opcode::VCVTPH2HF8SZ256rrkz, + 6649 => Opcode::VCVTPH2HF8SZrm, + 6650 => Opcode::VCVTPH2HF8SZrmb, + 6651 => Opcode::VCVTPH2HF8SZrmbk, + 6652 => Opcode::VCVTPH2HF8SZrmbkz, + 6653 => Opcode::VCVTPH2HF8SZrmk, + 6654 => Opcode::VCVTPH2HF8SZrmkz, + 6655 => Opcode::VCVTPH2HF8SZrr, + 6656 => Opcode::VCVTPH2HF8SZrrk, + 6657 => Opcode::VCVTPH2HF8SZrrkz, + 6658 => Opcode::VCVTPH2HF8Z128rm, + 6659 => Opcode::VCVTPH2HF8Z128rmb, + 6660 => Opcode::VCVTPH2HF8Z128rmbk, + 6661 => Opcode::VCVTPH2HF8Z128rmbkz, + 6662 => Opcode::VCVTPH2HF8Z128rmk, + 6663 => Opcode::VCVTPH2HF8Z128rmkz, + 6664 => Opcode::VCVTPH2HF8Z128rr, + 6665 => Opcode::VCVTPH2HF8Z128rrk, + 6666 => Opcode::VCVTPH2HF8Z128rrkz, + 6667 => Opcode::VCVTPH2HF8Z256rm, + 6668 => Opcode::VCVTPH2HF8Z256rmb, + 6669 => Opcode::VCVTPH2HF8Z256rmbk, + 6670 => Opcode::VCVTPH2HF8Z256rmbkz, + 6671 => Opcode::VCVTPH2HF8Z256rmk, + 6672 => Opcode::VCVTPH2HF8Z256rmkz, + 6673 => Opcode::VCVTPH2HF8Z256rr, + 6674 => Opcode::VCVTPH2HF8Z256rrk, + 6675 => Opcode::VCVTPH2HF8Z256rrkz, + 6676 => Opcode::VCVTPH2HF8Zrm, + 6677 => Opcode::VCVTPH2HF8Zrmb, + 6678 => Opcode::VCVTPH2HF8Zrmbk, + 6679 => Opcode::VCVTPH2HF8Zrmbkz, + 6680 => Opcode::VCVTPH2HF8Zrmk, + 6681 => Opcode::VCVTPH2HF8Zrmkz, + 6682 => Opcode::VCVTPH2HF8Zrr, + 6683 => Opcode::VCVTPH2HF8Zrrk, + 6684 => Opcode::VCVTPH2HF8Zrrkz, + 6685 => Opcode::VCVTPH2IBSZ128rm, + 6686 => Opcode::VCVTPH2IBSZ128rmb, + 6687 => Opcode::VCVTPH2IBSZ128rmbk, + 6688 => Opcode::VCVTPH2IBSZ128rmbkz, + 6689 => Opcode::VCVTPH2IBSZ128rmk, + 6690 => Opcode::VCVTPH2IBSZ128rmkz, + 6691 => Opcode::VCVTPH2IBSZ128rr, + 6692 => Opcode::VCVTPH2IBSZ128rrk, + 6693 => Opcode::VCVTPH2IBSZ128rrkz, + 6694 => Opcode::VCVTPH2IBSZ256rm, + 6695 => Opcode::VCVTPH2IBSZ256rmb, + 6696 => Opcode::VCVTPH2IBSZ256rmbk, + 6697 => Opcode::VCVTPH2IBSZ256rmbkz, + 6698 => Opcode::VCVTPH2IBSZ256rmk, + 6699 => Opcode::VCVTPH2IBSZ256rmkz, + 6700 => Opcode::VCVTPH2IBSZ256rr, + 6701 => Opcode::VCVTPH2IBSZ256rrk, + 6702 => Opcode::VCVTPH2IBSZ256rrkz, + 6703 => Opcode::VCVTPH2IBSZrm, + 6704 => Opcode::VCVTPH2IBSZrmb, + 6705 => Opcode::VCVTPH2IBSZrmbk, + 6706 => Opcode::VCVTPH2IBSZrmbkz, + 6707 => Opcode::VCVTPH2IBSZrmk, + 6708 => Opcode::VCVTPH2IBSZrmkz, + 6709 => Opcode::VCVTPH2IBSZrr, + 6710 => Opcode::VCVTPH2IBSZrrb, + 6711 => Opcode::VCVTPH2IBSZrrbk, + 6712 => Opcode::VCVTPH2IBSZrrbkz, + 6713 => Opcode::VCVTPH2IBSZrrk, + 6714 => Opcode::VCVTPH2IBSZrrkz, + 6715 => Opcode::VCVTPH2IUBSZ128rm, + 6716 => Opcode::VCVTPH2IUBSZ128rmb, + 6717 => Opcode::VCVTPH2IUBSZ128rmbk, + 6718 => Opcode::VCVTPH2IUBSZ128rmbkz, + 6719 => Opcode::VCVTPH2IUBSZ128rmk, + 6720 => Opcode::VCVTPH2IUBSZ128rmkz, + 6721 => Opcode::VCVTPH2IUBSZ128rr, + 6722 => Opcode::VCVTPH2IUBSZ128rrk, + 6723 => Opcode::VCVTPH2IUBSZ128rrkz, + 6724 => Opcode::VCVTPH2IUBSZ256rm, + 6725 => Opcode::VCVTPH2IUBSZ256rmb, + 6726 => Opcode::VCVTPH2IUBSZ256rmbk, + 6727 => Opcode::VCVTPH2IUBSZ256rmbkz, + 6728 => Opcode::VCVTPH2IUBSZ256rmk, + 6729 => Opcode::VCVTPH2IUBSZ256rmkz, + 6730 => Opcode::VCVTPH2IUBSZ256rr, + 6731 => Opcode::VCVTPH2IUBSZ256rrk, + 6732 => Opcode::VCVTPH2IUBSZ256rrkz, + 6733 => Opcode::VCVTPH2IUBSZrm, + 6734 => Opcode::VCVTPH2IUBSZrmb, + 6735 => Opcode::VCVTPH2IUBSZrmbk, + 6736 => Opcode::VCVTPH2IUBSZrmbkz, + 6737 => Opcode::VCVTPH2IUBSZrmk, + 6738 => Opcode::VCVTPH2IUBSZrmkz, + 6739 => Opcode::VCVTPH2IUBSZrr, + 6740 => Opcode::VCVTPH2IUBSZrrb, + 6741 => Opcode::VCVTPH2IUBSZrrbk, + 6742 => Opcode::VCVTPH2IUBSZrrbkz, + 6743 => Opcode::VCVTPH2IUBSZrrk, + 6744 => Opcode::VCVTPH2IUBSZrrkz, + 6745 => Opcode::VCVTPH2PDZ128rm, + 6746 => Opcode::VCVTPH2PDZ128rmb, + 6747 => Opcode::VCVTPH2PDZ128rmbk, + 6748 => Opcode::VCVTPH2PDZ128rmbkz, + 6749 => Opcode::VCVTPH2PDZ128rmk, + 6750 => Opcode::VCVTPH2PDZ128rmkz, + 6751 => Opcode::VCVTPH2PDZ128rr, + 6752 => Opcode::VCVTPH2PDZ128rrk, + 6753 => Opcode::VCVTPH2PDZ128rrkz, + 6754 => Opcode::VCVTPH2PDZ256rm, + 6755 => Opcode::VCVTPH2PDZ256rmb, + 6756 => Opcode::VCVTPH2PDZ256rmbk, + 6757 => Opcode::VCVTPH2PDZ256rmbkz, + 6758 => Opcode::VCVTPH2PDZ256rmk, + 6759 => Opcode::VCVTPH2PDZ256rmkz, + 6760 => Opcode::VCVTPH2PDZ256rr, + 6761 => Opcode::VCVTPH2PDZ256rrk, + 6762 => Opcode::VCVTPH2PDZ256rrkz, + 6763 => Opcode::VCVTPH2PDZrm, + 6764 => Opcode::VCVTPH2PDZrmb, + 6765 => Opcode::VCVTPH2PDZrmbk, + 6766 => Opcode::VCVTPH2PDZrmbkz, + 6767 => Opcode::VCVTPH2PDZrmk, + 6768 => Opcode::VCVTPH2PDZrmkz, + 6769 => Opcode::VCVTPH2PDZrr, + 6770 => Opcode::VCVTPH2PDZrrb, + 6771 => Opcode::VCVTPH2PDZrrbk, + 6772 => Opcode::VCVTPH2PDZrrbkz, + 6773 => Opcode::VCVTPH2PDZrrk, + 6774 => Opcode::VCVTPH2PDZrrkz, + 6775 => Opcode::VCVTPH2PSXZ128rm, + 6776 => Opcode::VCVTPH2PSXZ128rmb, + 6777 => Opcode::VCVTPH2PSXZ128rmbk, + 6778 => Opcode::VCVTPH2PSXZ128rmbkz, + 6779 => Opcode::VCVTPH2PSXZ128rmk, + 6780 => Opcode::VCVTPH2PSXZ128rmkz, + 6781 => Opcode::VCVTPH2PSXZ128rr, + 6782 => Opcode::VCVTPH2PSXZ128rrk, + 6783 => Opcode::VCVTPH2PSXZ128rrkz, + 6784 => Opcode::VCVTPH2PSXZ256rm, + 6785 => Opcode::VCVTPH2PSXZ256rmb, + 6786 => Opcode::VCVTPH2PSXZ256rmbk, + 6787 => Opcode::VCVTPH2PSXZ256rmbkz, + 6788 => Opcode::VCVTPH2PSXZ256rmk, + 6789 => Opcode::VCVTPH2PSXZ256rmkz, + 6790 => Opcode::VCVTPH2PSXZ256rr, + 6791 => Opcode::VCVTPH2PSXZ256rrk, + 6792 => Opcode::VCVTPH2PSXZ256rrkz, + 6793 => Opcode::VCVTPH2PSXZrm, + 6794 => Opcode::VCVTPH2PSXZrmb, + 6795 => Opcode::VCVTPH2PSXZrmbk, + 6796 => Opcode::VCVTPH2PSXZrmbkz, + 6797 => Opcode::VCVTPH2PSXZrmk, + 6798 => Opcode::VCVTPH2PSXZrmkz, + 6799 => Opcode::VCVTPH2PSXZrr, + 6800 => Opcode::VCVTPH2PSXZrrb, + 6801 => Opcode::VCVTPH2PSXZrrbk, + 6802 => Opcode::VCVTPH2PSXZrrbkz, + 6803 => Opcode::VCVTPH2PSXZrrk, + 6804 => Opcode::VCVTPH2PSXZrrkz, + 6805 => Opcode::VCVTPH2PSYrm, + 6806 => Opcode::VCVTPH2PSYrr, + 6807 => Opcode::VCVTPH2PSZ128rm, + 6808 => Opcode::VCVTPH2PSZ128rmk, + 6809 => Opcode::VCVTPH2PSZ128rmkz, + 6810 => Opcode::VCVTPH2PSZ128rr, + 6811 => Opcode::VCVTPH2PSZ128rrk, + 6812 => Opcode::VCVTPH2PSZ128rrkz, + 6813 => Opcode::VCVTPH2PSZ256rm, + 6814 => Opcode::VCVTPH2PSZ256rmk, + 6815 => Opcode::VCVTPH2PSZ256rmkz, + 6816 => Opcode::VCVTPH2PSZ256rr, + 6817 => Opcode::VCVTPH2PSZ256rrk, + 6818 => Opcode::VCVTPH2PSZ256rrkz, + 6819 => Opcode::VCVTPH2PSZrm, + 6820 => Opcode::VCVTPH2PSZrmk, + 6821 => Opcode::VCVTPH2PSZrmkz, + 6822 => Opcode::VCVTPH2PSZrr, + 6823 => Opcode::VCVTPH2PSZrrb, + 6824 => Opcode::VCVTPH2PSZrrbk, + 6825 => Opcode::VCVTPH2PSZrrbkz, + 6826 => Opcode::VCVTPH2PSZrrk, + 6827 => Opcode::VCVTPH2PSZrrkz, + 6828 => Opcode::VCVTPH2PSrm, + 6829 => Opcode::VCVTPH2PSrr, + 6830 => Opcode::VCVTPH2QQZ128rm, + 6831 => Opcode::VCVTPH2QQZ128rmb, + 6832 => Opcode::VCVTPH2QQZ128rmbk, + 6833 => Opcode::VCVTPH2QQZ128rmbkz, + 6834 => Opcode::VCVTPH2QQZ128rmk, + 6835 => Opcode::VCVTPH2QQZ128rmkz, + 6836 => Opcode::VCVTPH2QQZ128rr, + 6837 => Opcode::VCVTPH2QQZ128rrk, + 6838 => Opcode::VCVTPH2QQZ128rrkz, + 6839 => Opcode::VCVTPH2QQZ256rm, + 6840 => Opcode::VCVTPH2QQZ256rmb, + 6841 => Opcode::VCVTPH2QQZ256rmbk, + 6842 => Opcode::VCVTPH2QQZ256rmbkz, + 6843 => Opcode::VCVTPH2QQZ256rmk, + 6844 => Opcode::VCVTPH2QQZ256rmkz, + 6845 => Opcode::VCVTPH2QQZ256rr, + 6846 => Opcode::VCVTPH2QQZ256rrk, + 6847 => Opcode::VCVTPH2QQZ256rrkz, + 6848 => Opcode::VCVTPH2QQZrm, + 6849 => Opcode::VCVTPH2QQZrmb, + 6850 => Opcode::VCVTPH2QQZrmbk, + 6851 => Opcode::VCVTPH2QQZrmbkz, + 6852 => Opcode::VCVTPH2QQZrmk, + 6853 => Opcode::VCVTPH2QQZrmkz, + 6854 => Opcode::VCVTPH2QQZrr, + 6855 => Opcode::VCVTPH2QQZrrb, + 6856 => Opcode::VCVTPH2QQZrrbk, + 6857 => Opcode::VCVTPH2QQZrrbkz, + 6858 => Opcode::VCVTPH2QQZrrk, + 6859 => Opcode::VCVTPH2QQZrrkz, + 6860 => Opcode::VCVTPH2UDQZ128rm, + 6861 => Opcode::VCVTPH2UDQZ128rmb, + 6862 => Opcode::VCVTPH2UDQZ128rmbk, + 6863 => Opcode::VCVTPH2UDQZ128rmbkz, + 6864 => Opcode::VCVTPH2UDQZ128rmk, + 6865 => Opcode::VCVTPH2UDQZ128rmkz, + 6866 => Opcode::VCVTPH2UDQZ128rr, + 6867 => Opcode::VCVTPH2UDQZ128rrk, + 6868 => Opcode::VCVTPH2UDQZ128rrkz, + 6869 => Opcode::VCVTPH2UDQZ256rm, + 6870 => Opcode::VCVTPH2UDQZ256rmb, + 6871 => Opcode::VCVTPH2UDQZ256rmbk, + 6872 => Opcode::VCVTPH2UDQZ256rmbkz, + 6873 => Opcode::VCVTPH2UDQZ256rmk, + 6874 => Opcode::VCVTPH2UDQZ256rmkz, + 6875 => Opcode::VCVTPH2UDQZ256rr, + 6876 => Opcode::VCVTPH2UDQZ256rrk, + 6877 => Opcode::VCVTPH2UDQZ256rrkz, + 6878 => Opcode::VCVTPH2UDQZrm, + 6879 => Opcode::VCVTPH2UDQZrmb, + 6880 => Opcode::VCVTPH2UDQZrmbk, + 6881 => Opcode::VCVTPH2UDQZrmbkz, + 6882 => Opcode::VCVTPH2UDQZrmk, + 6883 => Opcode::VCVTPH2UDQZrmkz, + 6884 => Opcode::VCVTPH2UDQZrr, + 6885 => Opcode::VCVTPH2UDQZrrb, + 6886 => Opcode::VCVTPH2UDQZrrbk, + 6887 => Opcode::VCVTPH2UDQZrrbkz, + 6888 => Opcode::VCVTPH2UDQZrrk, + 6889 => Opcode::VCVTPH2UDQZrrkz, + 6890 => Opcode::VCVTPH2UQQZ128rm, + 6891 => Opcode::VCVTPH2UQQZ128rmb, + 6892 => Opcode::VCVTPH2UQQZ128rmbk, + 6893 => Opcode::VCVTPH2UQQZ128rmbkz, + 6894 => Opcode::VCVTPH2UQQZ128rmk, + 6895 => Opcode::VCVTPH2UQQZ128rmkz, + 6896 => Opcode::VCVTPH2UQQZ128rr, + 6897 => Opcode::VCVTPH2UQQZ128rrk, + 6898 => Opcode::VCVTPH2UQQZ128rrkz, + 6899 => Opcode::VCVTPH2UQQZ256rm, + 6900 => Opcode::VCVTPH2UQQZ256rmb, + 6901 => Opcode::VCVTPH2UQQZ256rmbk, + 6902 => Opcode::VCVTPH2UQQZ256rmbkz, + 6903 => Opcode::VCVTPH2UQQZ256rmk, + 6904 => Opcode::VCVTPH2UQQZ256rmkz, + 6905 => Opcode::VCVTPH2UQQZ256rr, + 6906 => Opcode::VCVTPH2UQQZ256rrk, + 6907 => Opcode::VCVTPH2UQQZ256rrkz, + 6908 => Opcode::VCVTPH2UQQZrm, + 6909 => Opcode::VCVTPH2UQQZrmb, + 6910 => Opcode::VCVTPH2UQQZrmbk, + 6911 => Opcode::VCVTPH2UQQZrmbkz, + 6912 => Opcode::VCVTPH2UQQZrmk, + 6913 => Opcode::VCVTPH2UQQZrmkz, + 6914 => Opcode::VCVTPH2UQQZrr, + 6915 => Opcode::VCVTPH2UQQZrrb, + 6916 => Opcode::VCVTPH2UQQZrrbk, + 6917 => Opcode::VCVTPH2UQQZrrbkz, + 6918 => Opcode::VCVTPH2UQQZrrk, + 6919 => Opcode::VCVTPH2UQQZrrkz, + 6920 => Opcode::VCVTPH2UWZ128rm, + 6921 => Opcode::VCVTPH2UWZ128rmb, + 6922 => Opcode::VCVTPH2UWZ128rmbk, + 6923 => Opcode::VCVTPH2UWZ128rmbkz, + 6924 => Opcode::VCVTPH2UWZ128rmk, + 6925 => Opcode::VCVTPH2UWZ128rmkz, + 6926 => Opcode::VCVTPH2UWZ128rr, + 6927 => Opcode::VCVTPH2UWZ128rrk, + 6928 => Opcode::VCVTPH2UWZ128rrkz, + 6929 => Opcode::VCVTPH2UWZ256rm, + 6930 => Opcode::VCVTPH2UWZ256rmb, + 6931 => Opcode::VCVTPH2UWZ256rmbk, + 6932 => Opcode::VCVTPH2UWZ256rmbkz, + 6933 => Opcode::VCVTPH2UWZ256rmk, + 6934 => Opcode::VCVTPH2UWZ256rmkz, + 6935 => Opcode::VCVTPH2UWZ256rr, + 6936 => Opcode::VCVTPH2UWZ256rrk, + 6937 => Opcode::VCVTPH2UWZ256rrkz, + 6938 => Opcode::VCVTPH2UWZrm, + 6939 => Opcode::VCVTPH2UWZrmb, + 6940 => Opcode::VCVTPH2UWZrmbk, + 6941 => Opcode::VCVTPH2UWZrmbkz, + 6942 => Opcode::VCVTPH2UWZrmk, + 6943 => Opcode::VCVTPH2UWZrmkz, + 6944 => Opcode::VCVTPH2UWZrr, + 6945 => Opcode::VCVTPH2UWZrrb, + 6946 => Opcode::VCVTPH2UWZrrbk, + 6947 => Opcode::VCVTPH2UWZrrbkz, + 6948 => Opcode::VCVTPH2UWZrrk, + 6949 => Opcode::VCVTPH2UWZrrkz, + 6950 => Opcode::VCVTPH2WZ128rm, + 6951 => Opcode::VCVTPH2WZ128rmb, + 6952 => Opcode::VCVTPH2WZ128rmbk, + 6953 => Opcode::VCVTPH2WZ128rmbkz, + 6954 => Opcode::VCVTPH2WZ128rmk, + 6955 => Opcode::VCVTPH2WZ128rmkz, + 6956 => Opcode::VCVTPH2WZ128rr, + 6957 => Opcode::VCVTPH2WZ128rrk, + 6958 => Opcode::VCVTPH2WZ128rrkz, + 6959 => Opcode::VCVTPH2WZ256rm, + 6960 => Opcode::VCVTPH2WZ256rmb, + 6961 => Opcode::VCVTPH2WZ256rmbk, + 6962 => Opcode::VCVTPH2WZ256rmbkz, + 6963 => Opcode::VCVTPH2WZ256rmk, + 6964 => Opcode::VCVTPH2WZ256rmkz, + 6965 => Opcode::VCVTPH2WZ256rr, + 6966 => Opcode::VCVTPH2WZ256rrk, + 6967 => Opcode::VCVTPH2WZ256rrkz, + 6968 => Opcode::VCVTPH2WZrm, + 6969 => Opcode::VCVTPH2WZrmb, + 6970 => Opcode::VCVTPH2WZrmbk, + 6971 => Opcode::VCVTPH2WZrmbkz, + 6972 => Opcode::VCVTPH2WZrmk, + 6973 => Opcode::VCVTPH2WZrmkz, + 6974 => Opcode::VCVTPH2WZrr, + 6975 => Opcode::VCVTPH2WZrrb, + 6976 => Opcode::VCVTPH2WZrrbk, + 6977 => Opcode::VCVTPH2WZrrbkz, + 6978 => Opcode::VCVTPH2WZrrk, + 6979 => Opcode::VCVTPH2WZrrkz, + 6980 => Opcode::VCVTPS2DQYrm, + 6981 => Opcode::VCVTPS2DQYrr, + 6982 => Opcode::VCVTPS2DQZ128rm, + 6983 => Opcode::VCVTPS2DQZ128rmb, + 6984 => Opcode::VCVTPS2DQZ128rmbk, + 6985 => Opcode::VCVTPS2DQZ128rmbkz, + 6986 => Opcode::VCVTPS2DQZ128rmk, + 6987 => Opcode::VCVTPS2DQZ128rmkz, + 6988 => Opcode::VCVTPS2DQZ128rr, + 6989 => Opcode::VCVTPS2DQZ128rrk, + 6990 => Opcode::VCVTPS2DQZ128rrkz, + 6991 => Opcode::VCVTPS2DQZ256rm, + 6992 => Opcode::VCVTPS2DQZ256rmb, + 6993 => Opcode::VCVTPS2DQZ256rmbk, + 6994 => Opcode::VCVTPS2DQZ256rmbkz, + 6995 => Opcode::VCVTPS2DQZ256rmk, + 6996 => Opcode::VCVTPS2DQZ256rmkz, + 6997 => Opcode::VCVTPS2DQZ256rr, + 6998 => Opcode::VCVTPS2DQZ256rrk, + 6999 => Opcode::VCVTPS2DQZ256rrkz, + 7000 => Opcode::VCVTPS2DQZrm, + 7001 => Opcode::VCVTPS2DQZrmb, + 7002 => Opcode::VCVTPS2DQZrmbk, + 7003 => Opcode::VCVTPS2DQZrmbkz, + 7004 => Opcode::VCVTPS2DQZrmk, + 7005 => Opcode::VCVTPS2DQZrmkz, + 7006 => Opcode::VCVTPS2DQZrr, + 7007 => Opcode::VCVTPS2DQZrrb, + 7008 => Opcode::VCVTPS2DQZrrbk, + 7009 => Opcode::VCVTPS2DQZrrbkz, + 7010 => Opcode::VCVTPS2DQZrrk, + 7011 => Opcode::VCVTPS2DQZrrkz, + 7012 => Opcode::VCVTPS2DQrm, + 7013 => Opcode::VCVTPS2DQrr, + 7014 => Opcode::VCVTPS2IBSZ128rm, + 7015 => Opcode::VCVTPS2IBSZ128rmb, + 7016 => Opcode::VCVTPS2IBSZ128rmbk, + 7017 => Opcode::VCVTPS2IBSZ128rmbkz, + 7018 => Opcode::VCVTPS2IBSZ128rmk, + 7019 => Opcode::VCVTPS2IBSZ128rmkz, + 7020 => Opcode::VCVTPS2IBSZ128rr, + 7021 => Opcode::VCVTPS2IBSZ128rrk, + 7022 => Opcode::VCVTPS2IBSZ128rrkz, + 7023 => Opcode::VCVTPS2IBSZ256rm, + 7024 => Opcode::VCVTPS2IBSZ256rmb, + 7025 => Opcode::VCVTPS2IBSZ256rmbk, + 7026 => Opcode::VCVTPS2IBSZ256rmbkz, + 7027 => Opcode::VCVTPS2IBSZ256rmk, + 7028 => Opcode::VCVTPS2IBSZ256rmkz, + 7029 => Opcode::VCVTPS2IBSZ256rr, + 7030 => Opcode::VCVTPS2IBSZ256rrk, + 7031 => Opcode::VCVTPS2IBSZ256rrkz, + 7032 => Opcode::VCVTPS2IBSZrm, + 7033 => Opcode::VCVTPS2IBSZrmb, + 7034 => Opcode::VCVTPS2IBSZrmbk, + 7035 => Opcode::VCVTPS2IBSZrmbkz, + 7036 => Opcode::VCVTPS2IBSZrmk, + 7037 => Opcode::VCVTPS2IBSZrmkz, + 7038 => Opcode::VCVTPS2IBSZrr, + 7039 => Opcode::VCVTPS2IBSZrrb, + 7040 => Opcode::VCVTPS2IBSZrrbk, + 7041 => Opcode::VCVTPS2IBSZrrbkz, + 7042 => Opcode::VCVTPS2IBSZrrk, + 7043 => Opcode::VCVTPS2IBSZrrkz, + 7044 => Opcode::VCVTPS2IUBSZ128rm, + 7045 => Opcode::VCVTPS2IUBSZ128rmb, + 7046 => Opcode::VCVTPS2IUBSZ128rmbk, + 7047 => Opcode::VCVTPS2IUBSZ128rmbkz, + 7048 => Opcode::VCVTPS2IUBSZ128rmk, + 7049 => Opcode::VCVTPS2IUBSZ128rmkz, + 7050 => Opcode::VCVTPS2IUBSZ128rr, + 7051 => Opcode::VCVTPS2IUBSZ128rrk, + 7052 => Opcode::VCVTPS2IUBSZ128rrkz, + 7053 => Opcode::VCVTPS2IUBSZ256rm, + 7054 => Opcode::VCVTPS2IUBSZ256rmb, + 7055 => Opcode::VCVTPS2IUBSZ256rmbk, + 7056 => Opcode::VCVTPS2IUBSZ256rmbkz, + 7057 => Opcode::VCVTPS2IUBSZ256rmk, + 7058 => Opcode::VCVTPS2IUBSZ256rmkz, + 7059 => Opcode::VCVTPS2IUBSZ256rr, + 7060 => Opcode::VCVTPS2IUBSZ256rrk, + 7061 => Opcode::VCVTPS2IUBSZ256rrkz, + 7062 => Opcode::VCVTPS2IUBSZrm, + 7063 => Opcode::VCVTPS2IUBSZrmb, + 7064 => Opcode::VCVTPS2IUBSZrmbk, + 7065 => Opcode::VCVTPS2IUBSZrmbkz, + 7066 => Opcode::VCVTPS2IUBSZrmk, + 7067 => Opcode::VCVTPS2IUBSZrmkz, + 7068 => Opcode::VCVTPS2IUBSZrr, + 7069 => Opcode::VCVTPS2IUBSZrrb, + 7070 => Opcode::VCVTPS2IUBSZrrbk, + 7071 => Opcode::VCVTPS2IUBSZrrbkz, + 7072 => Opcode::VCVTPS2IUBSZrrk, + 7073 => Opcode::VCVTPS2IUBSZrrkz, + 7074 => Opcode::VCVTPS2PDYrm, + 7075 => Opcode::VCVTPS2PDYrr, + 7076 => Opcode::VCVTPS2PDZ128rm, + 7077 => Opcode::VCVTPS2PDZ128rmb, + 7078 => Opcode::VCVTPS2PDZ128rmbk, + 7079 => Opcode::VCVTPS2PDZ128rmbkz, + 7080 => Opcode::VCVTPS2PDZ128rmk, + 7081 => Opcode::VCVTPS2PDZ128rmkz, + 7082 => Opcode::VCVTPS2PDZ128rr, + 7083 => Opcode::VCVTPS2PDZ128rrk, + 7084 => Opcode::VCVTPS2PDZ128rrkz, + 7085 => Opcode::VCVTPS2PDZ256rm, + 7086 => Opcode::VCVTPS2PDZ256rmb, + 7087 => Opcode::VCVTPS2PDZ256rmbk, + 7088 => Opcode::VCVTPS2PDZ256rmbkz, + 7089 => Opcode::VCVTPS2PDZ256rmk, + 7090 => Opcode::VCVTPS2PDZ256rmkz, + 7091 => Opcode::VCVTPS2PDZ256rr, + 7092 => Opcode::VCVTPS2PDZ256rrk, + 7093 => Opcode::VCVTPS2PDZ256rrkz, + 7094 => Opcode::VCVTPS2PDZrm, + 7095 => Opcode::VCVTPS2PDZrmb, + 7096 => Opcode::VCVTPS2PDZrmbk, + 7097 => Opcode::VCVTPS2PDZrmbkz, + 7098 => Opcode::VCVTPS2PDZrmk, + 7099 => Opcode::VCVTPS2PDZrmkz, + 7100 => Opcode::VCVTPS2PDZrr, + 7101 => Opcode::VCVTPS2PDZrrb, + 7102 => Opcode::VCVTPS2PDZrrbk, + 7103 => Opcode::VCVTPS2PDZrrbkz, + 7104 => Opcode::VCVTPS2PDZrrk, + 7105 => Opcode::VCVTPS2PDZrrkz, + 7106 => Opcode::VCVTPS2PDrm, + 7107 => Opcode::VCVTPS2PDrr, + 7108 => Opcode::VCVTPS2PHXZ128rm, + 7109 => Opcode::VCVTPS2PHXZ128rmb, + 7110 => Opcode::VCVTPS2PHXZ128rmbk, + 7111 => Opcode::VCVTPS2PHXZ128rmbkz, + 7112 => Opcode::VCVTPS2PHXZ128rmk, + 7113 => Opcode::VCVTPS2PHXZ128rmkz, + 7114 => Opcode::VCVTPS2PHXZ128rr, + 7115 => Opcode::VCVTPS2PHXZ128rrk, + 7116 => Opcode::VCVTPS2PHXZ128rrkz, + 7117 => Opcode::VCVTPS2PHXZ256rm, + 7118 => Opcode::VCVTPS2PHXZ256rmb, + 7119 => Opcode::VCVTPS2PHXZ256rmbk, + 7120 => Opcode::VCVTPS2PHXZ256rmbkz, + 7121 => Opcode::VCVTPS2PHXZ256rmk, + 7122 => Opcode::VCVTPS2PHXZ256rmkz, + 7123 => Opcode::VCVTPS2PHXZ256rr, + 7124 => Opcode::VCVTPS2PHXZ256rrk, + 7125 => Opcode::VCVTPS2PHXZ256rrkz, + 7126 => Opcode::VCVTPS2PHXZrm, + 7127 => Opcode::VCVTPS2PHXZrmb, + 7128 => Opcode::VCVTPS2PHXZrmbk, + 7129 => Opcode::VCVTPS2PHXZrmbkz, + 7130 => Opcode::VCVTPS2PHXZrmk, + 7131 => Opcode::VCVTPS2PHXZrmkz, + 7132 => Opcode::VCVTPS2PHXZrr, + 7133 => Opcode::VCVTPS2PHXZrrb, + 7134 => Opcode::VCVTPS2PHXZrrbk, + 7135 => Opcode::VCVTPS2PHXZrrbkz, + 7136 => Opcode::VCVTPS2PHXZrrk, + 7137 => Opcode::VCVTPS2PHXZrrkz, + 7138 => Opcode::VCVTPS2PHYmr, + 7139 => Opcode::VCVTPS2PHYrr, + 7140 => Opcode::VCVTPS2PHZ128mr, + 7141 => Opcode::VCVTPS2PHZ128mrk, + 7142 => Opcode::VCVTPS2PHZ128rr, + 7143 => Opcode::VCVTPS2PHZ128rrk, + 7144 => Opcode::VCVTPS2PHZ128rrkz, + 7145 => Opcode::VCVTPS2PHZ256mr, + 7146 => Opcode::VCVTPS2PHZ256mrk, + 7147 => Opcode::VCVTPS2PHZ256rr, + 7148 => Opcode::VCVTPS2PHZ256rrk, + 7149 => Opcode::VCVTPS2PHZ256rrkz, + 7150 => Opcode::VCVTPS2PHZmr, + 7151 => Opcode::VCVTPS2PHZmrk, + 7152 => Opcode::VCVTPS2PHZrr, + 7153 => Opcode::VCVTPS2PHZrrb, + 7154 => Opcode::VCVTPS2PHZrrbk, + 7155 => Opcode::VCVTPS2PHZrrbkz, + 7156 => Opcode::VCVTPS2PHZrrk, + 7157 => Opcode::VCVTPS2PHZrrkz, + 7158 => Opcode::VCVTPS2PHmr, + 7159 => Opcode::VCVTPS2PHrr, + 7160 => Opcode::VCVTPS2QQZ128rm, + 7161 => Opcode::VCVTPS2QQZ128rmb, + 7162 => Opcode::VCVTPS2QQZ128rmbk, + 7163 => Opcode::VCVTPS2QQZ128rmbkz, + 7164 => Opcode::VCVTPS2QQZ128rmk, + 7165 => Opcode::VCVTPS2QQZ128rmkz, + 7166 => Opcode::VCVTPS2QQZ128rr, + 7167 => Opcode::VCVTPS2QQZ128rrk, + 7168 => Opcode::VCVTPS2QQZ128rrkz, + 7169 => Opcode::VCVTPS2QQZ256rm, + 7170 => Opcode::VCVTPS2QQZ256rmb, + 7171 => Opcode::VCVTPS2QQZ256rmbk, + 7172 => Opcode::VCVTPS2QQZ256rmbkz, + 7173 => Opcode::VCVTPS2QQZ256rmk, + 7174 => Opcode::VCVTPS2QQZ256rmkz, + 7175 => Opcode::VCVTPS2QQZ256rr, + 7176 => Opcode::VCVTPS2QQZ256rrk, + 7177 => Opcode::VCVTPS2QQZ256rrkz, + 7178 => Opcode::VCVTPS2QQZrm, + 7179 => Opcode::VCVTPS2QQZrmb, + 7180 => Opcode::VCVTPS2QQZrmbk, + 7181 => Opcode::VCVTPS2QQZrmbkz, + 7182 => Opcode::VCVTPS2QQZrmk, + 7183 => Opcode::VCVTPS2QQZrmkz, + 7184 => Opcode::VCVTPS2QQZrr, + 7185 => Opcode::VCVTPS2QQZrrb, + 7186 => Opcode::VCVTPS2QQZrrbk, + 7187 => Opcode::VCVTPS2QQZrrbkz, + 7188 => Opcode::VCVTPS2QQZrrk, + 7189 => Opcode::VCVTPS2QQZrrkz, + 7190 => Opcode::VCVTPS2UDQZ128rm, + 7191 => Opcode::VCVTPS2UDQZ128rmb, + 7192 => Opcode::VCVTPS2UDQZ128rmbk, + 7193 => Opcode::VCVTPS2UDQZ128rmbkz, + 7194 => Opcode::VCVTPS2UDQZ128rmk, + 7195 => Opcode::VCVTPS2UDQZ128rmkz, + 7196 => Opcode::VCVTPS2UDQZ128rr, + 7197 => Opcode::VCVTPS2UDQZ128rrk, + 7198 => Opcode::VCVTPS2UDQZ128rrkz, + 7199 => Opcode::VCVTPS2UDQZ256rm, + 7200 => Opcode::VCVTPS2UDQZ256rmb, + 7201 => Opcode::VCVTPS2UDQZ256rmbk, + 7202 => Opcode::VCVTPS2UDQZ256rmbkz, + 7203 => Opcode::VCVTPS2UDQZ256rmk, + 7204 => Opcode::VCVTPS2UDQZ256rmkz, + 7205 => Opcode::VCVTPS2UDQZ256rr, + 7206 => Opcode::VCVTPS2UDQZ256rrk, + 7207 => Opcode::VCVTPS2UDQZ256rrkz, + 7208 => Opcode::VCVTPS2UDQZrm, + 7209 => Opcode::VCVTPS2UDQZrmb, + 7210 => Opcode::VCVTPS2UDQZrmbk, + 7211 => Opcode::VCVTPS2UDQZrmbkz, + 7212 => Opcode::VCVTPS2UDQZrmk, + 7213 => Opcode::VCVTPS2UDQZrmkz, + 7214 => Opcode::VCVTPS2UDQZrr, + 7215 => Opcode::VCVTPS2UDQZrrb, + 7216 => Opcode::VCVTPS2UDQZrrbk, + 7217 => Opcode::VCVTPS2UDQZrrbkz, + 7218 => Opcode::VCVTPS2UDQZrrk, + 7219 => Opcode::VCVTPS2UDQZrrkz, + 7220 => Opcode::VCVTPS2UQQZ128rm, + 7221 => Opcode::VCVTPS2UQQZ128rmb, + 7222 => Opcode::VCVTPS2UQQZ128rmbk, + 7223 => Opcode::VCVTPS2UQQZ128rmbkz, + 7224 => Opcode::VCVTPS2UQQZ128rmk, + 7225 => Opcode::VCVTPS2UQQZ128rmkz, + 7226 => Opcode::VCVTPS2UQQZ128rr, + 7227 => Opcode::VCVTPS2UQQZ128rrk, + 7228 => Opcode::VCVTPS2UQQZ128rrkz, + 7229 => Opcode::VCVTPS2UQQZ256rm, + 7230 => Opcode::VCVTPS2UQQZ256rmb, + 7231 => Opcode::VCVTPS2UQQZ256rmbk, + 7232 => Opcode::VCVTPS2UQQZ256rmbkz, + 7233 => Opcode::VCVTPS2UQQZ256rmk, + 7234 => Opcode::VCVTPS2UQQZ256rmkz, + 7235 => Opcode::VCVTPS2UQQZ256rr, + 7236 => Opcode::VCVTPS2UQQZ256rrk, + 7237 => Opcode::VCVTPS2UQQZ256rrkz, + 7238 => Opcode::VCVTPS2UQQZrm, + 7239 => Opcode::VCVTPS2UQQZrmb, + 7240 => Opcode::VCVTPS2UQQZrmbk, + 7241 => Opcode::VCVTPS2UQQZrmbkz, + 7242 => Opcode::VCVTPS2UQQZrmk, + 7243 => Opcode::VCVTPS2UQQZrmkz, + 7244 => Opcode::VCVTPS2UQQZrr, + 7245 => Opcode::VCVTPS2UQQZrrb, + 7246 => Opcode::VCVTPS2UQQZrrbk, + 7247 => Opcode::VCVTPS2UQQZrrbkz, + 7248 => Opcode::VCVTPS2UQQZrrk, + 7249 => Opcode::VCVTPS2UQQZrrkz, + 7250 => Opcode::VCVTQQ2PDZ128rm, + 7251 => Opcode::VCVTQQ2PDZ128rmb, + 7252 => Opcode::VCVTQQ2PDZ128rmbk, + 7253 => Opcode::VCVTQQ2PDZ128rmbkz, + 7254 => Opcode::VCVTQQ2PDZ128rmk, + 7255 => Opcode::VCVTQQ2PDZ128rmkz, + 7256 => Opcode::VCVTQQ2PDZ128rr, + 7257 => Opcode::VCVTQQ2PDZ128rrk, + 7258 => Opcode::VCVTQQ2PDZ128rrkz, + 7259 => Opcode::VCVTQQ2PDZ256rm, + 7260 => Opcode::VCVTQQ2PDZ256rmb, + 7261 => Opcode::VCVTQQ2PDZ256rmbk, + 7262 => Opcode::VCVTQQ2PDZ256rmbkz, + 7263 => Opcode::VCVTQQ2PDZ256rmk, + 7264 => Opcode::VCVTQQ2PDZ256rmkz, + 7265 => Opcode::VCVTQQ2PDZ256rr, + 7266 => Opcode::VCVTQQ2PDZ256rrk, + 7267 => Opcode::VCVTQQ2PDZ256rrkz, + 7268 => Opcode::VCVTQQ2PDZrm, + 7269 => Opcode::VCVTQQ2PDZrmb, + 7270 => Opcode::VCVTQQ2PDZrmbk, + 7271 => Opcode::VCVTQQ2PDZrmbkz, + 7272 => Opcode::VCVTQQ2PDZrmk, + 7273 => Opcode::VCVTQQ2PDZrmkz, + 7274 => Opcode::VCVTQQ2PDZrr, + 7275 => Opcode::VCVTQQ2PDZrrb, + 7276 => Opcode::VCVTQQ2PDZrrbk, + 7277 => Opcode::VCVTQQ2PDZrrbkz, + 7278 => Opcode::VCVTQQ2PDZrrk, + 7279 => Opcode::VCVTQQ2PDZrrkz, + 7280 => Opcode::VCVTQQ2PHZ128rm, + 7281 => Opcode::VCVTQQ2PHZ128rmb, + 7282 => Opcode::VCVTQQ2PHZ128rmbk, + 7283 => Opcode::VCVTQQ2PHZ128rmbkz, + 7284 => Opcode::VCVTQQ2PHZ128rmk, + 7285 => Opcode::VCVTQQ2PHZ128rmkz, + 7286 => Opcode::VCVTQQ2PHZ128rr, + 7287 => Opcode::VCVTQQ2PHZ128rrk, + 7288 => Opcode::VCVTQQ2PHZ128rrkz, + 7289 => Opcode::VCVTQQ2PHZ256rm, + 7290 => Opcode::VCVTQQ2PHZ256rmb, + 7291 => Opcode::VCVTQQ2PHZ256rmbk, + 7292 => Opcode::VCVTQQ2PHZ256rmbkz, + 7293 => Opcode::VCVTQQ2PHZ256rmk, + 7294 => Opcode::VCVTQQ2PHZ256rmkz, + 7295 => Opcode::VCVTQQ2PHZ256rr, + 7296 => Opcode::VCVTQQ2PHZ256rrk, + 7297 => Opcode::VCVTQQ2PHZ256rrkz, + 7298 => Opcode::VCVTQQ2PHZrm, + 7299 => Opcode::VCVTQQ2PHZrmb, + 7300 => Opcode::VCVTQQ2PHZrmbk, + 7301 => Opcode::VCVTQQ2PHZrmbkz, + 7302 => Opcode::VCVTQQ2PHZrmk, + 7303 => Opcode::VCVTQQ2PHZrmkz, + 7304 => Opcode::VCVTQQ2PHZrr, + 7305 => Opcode::VCVTQQ2PHZrrb, + 7306 => Opcode::VCVTQQ2PHZrrbk, + 7307 => Opcode::VCVTQQ2PHZrrbkz, + 7308 => Opcode::VCVTQQ2PHZrrk, + 7309 => Opcode::VCVTQQ2PHZrrkz, + 7310 => Opcode::VCVTQQ2PSZ128rm, + 7311 => Opcode::VCVTQQ2PSZ128rmb, + 7312 => Opcode::VCVTQQ2PSZ128rmbk, + 7313 => Opcode::VCVTQQ2PSZ128rmbkz, + 7314 => Opcode::VCVTQQ2PSZ128rmk, + 7315 => Opcode::VCVTQQ2PSZ128rmkz, + 7316 => Opcode::VCVTQQ2PSZ128rr, + 7317 => Opcode::VCVTQQ2PSZ128rrk, + 7318 => Opcode::VCVTQQ2PSZ128rrkz, + 7319 => Opcode::VCVTQQ2PSZ256rm, + 7320 => Opcode::VCVTQQ2PSZ256rmb, + 7321 => Opcode::VCVTQQ2PSZ256rmbk, + 7322 => Opcode::VCVTQQ2PSZ256rmbkz, + 7323 => Opcode::VCVTQQ2PSZ256rmk, + 7324 => Opcode::VCVTQQ2PSZ256rmkz, + 7325 => Opcode::VCVTQQ2PSZ256rr, + 7326 => Opcode::VCVTQQ2PSZ256rrk, + 7327 => Opcode::VCVTQQ2PSZ256rrkz, + 7328 => Opcode::VCVTQQ2PSZrm, + 7329 => Opcode::VCVTQQ2PSZrmb, + 7330 => Opcode::VCVTQQ2PSZrmbk, + 7331 => Opcode::VCVTQQ2PSZrmbkz, + 7332 => Opcode::VCVTQQ2PSZrmk, + 7333 => Opcode::VCVTQQ2PSZrmkz, + 7334 => Opcode::VCVTQQ2PSZrr, + 7335 => Opcode::VCVTQQ2PSZrrb, + 7336 => Opcode::VCVTQQ2PSZrrbk, + 7337 => Opcode::VCVTQQ2PSZrrbkz, + 7338 => Opcode::VCVTQQ2PSZrrk, + 7339 => Opcode::VCVTQQ2PSZrrkz, + 7340 => Opcode::VCVTSD2SHZrm, + 7341 => Opcode::VCVTSD2SHZrm_Int, + 7342 => Opcode::VCVTSD2SHZrmk_Int, + 7343 => Opcode::VCVTSD2SHZrmkz_Int, + 7344 => Opcode::VCVTSD2SHZrr, + 7345 => Opcode::VCVTSD2SHZrr_Int, + 7346 => Opcode::VCVTSD2SHZrrb_Int, + 7347 => Opcode::VCVTSD2SHZrrbk_Int, + 7348 => Opcode::VCVTSD2SHZrrbkz_Int, + 7349 => Opcode::VCVTSD2SHZrrk_Int, + 7350 => Opcode::VCVTSD2SHZrrkz_Int, + 7351 => Opcode::VCVTSD2SI64Zrm, + 7352 => Opcode::VCVTSD2SI64Zrm_Int, + 7353 => Opcode::VCVTSD2SI64Zrr, + 7354 => Opcode::VCVTSD2SI64Zrr_Int, + 7355 => Opcode::VCVTSD2SI64Zrrb_Int, + 7356 => Opcode::VCVTSD2SI64rm, + 7357 => Opcode::VCVTSD2SI64rm_Int, + 7358 => Opcode::VCVTSD2SI64rr, + 7359 => Opcode::VCVTSD2SI64rr_Int, + 7360 => Opcode::VCVTSD2SIZrm, + 7361 => Opcode::VCVTSD2SIZrm_Int, + 7362 => Opcode::VCVTSD2SIZrr, + 7363 => Opcode::VCVTSD2SIZrr_Int, + 7364 => Opcode::VCVTSD2SIZrrb_Int, + 7365 => Opcode::VCVTSD2SIrm, + 7366 => Opcode::VCVTSD2SIrm_Int, + 7367 => Opcode::VCVTSD2SIrr, + 7368 => Opcode::VCVTSD2SIrr_Int, + 7369 => Opcode::VCVTSD2SSZrm, + 7370 => Opcode::VCVTSD2SSZrm_Int, + 7371 => Opcode::VCVTSD2SSZrmk_Int, + 7372 => Opcode::VCVTSD2SSZrmkz_Int, + 7373 => Opcode::VCVTSD2SSZrr, + 7374 => Opcode::VCVTSD2SSZrr_Int, + 7375 => Opcode::VCVTSD2SSZrrb_Int, + 7376 => Opcode::VCVTSD2SSZrrbk_Int, + 7377 => Opcode::VCVTSD2SSZrrbkz_Int, + 7378 => Opcode::VCVTSD2SSZrrk_Int, + 7379 => Opcode::VCVTSD2SSZrrkz_Int, + 7380 => Opcode::VCVTSD2SSrm, + 7381 => Opcode::VCVTSD2SSrm_Int, + 7382 => Opcode::VCVTSD2SSrr, + 7383 => Opcode::VCVTSD2SSrr_Int, + 7384 => Opcode::VCVTSD2USI64Zrm_Int, + 7385 => Opcode::VCVTSD2USI64Zrr_Int, + 7386 => Opcode::VCVTSD2USI64Zrrb_Int, + 7387 => Opcode::VCVTSD2USIZrm_Int, + 7388 => Opcode::VCVTSD2USIZrr_Int, + 7389 => Opcode::VCVTSD2USIZrrb_Int, + 7390 => Opcode::VCVTSH2SDZrm, + 7391 => Opcode::VCVTSH2SDZrm_Int, + 7392 => Opcode::VCVTSH2SDZrmk_Int, + 7393 => Opcode::VCVTSH2SDZrmkz_Int, + 7394 => Opcode::VCVTSH2SDZrr, + 7395 => Opcode::VCVTSH2SDZrr_Int, + 7396 => Opcode::VCVTSH2SDZrrb_Int, + 7397 => Opcode::VCVTSH2SDZrrbk_Int, + 7398 => Opcode::VCVTSH2SDZrrbkz_Int, + 7399 => Opcode::VCVTSH2SDZrrk_Int, + 7400 => Opcode::VCVTSH2SDZrrkz_Int, + 7401 => Opcode::VCVTSH2SI64Zrm_Int, + 7402 => Opcode::VCVTSH2SI64Zrr_Int, + 7403 => Opcode::VCVTSH2SI64Zrrb_Int, + 7404 => Opcode::VCVTSH2SIZrm_Int, + 7405 => Opcode::VCVTSH2SIZrr_Int, + 7406 => Opcode::VCVTSH2SIZrrb_Int, + 7407 => Opcode::VCVTSH2SSZrm, + 7408 => Opcode::VCVTSH2SSZrm_Int, + 7409 => Opcode::VCVTSH2SSZrmk_Int, + 7410 => Opcode::VCVTSH2SSZrmkz_Int, + 7411 => Opcode::VCVTSH2SSZrr, + 7412 => Opcode::VCVTSH2SSZrr_Int, + 7413 => Opcode::VCVTSH2SSZrrb_Int, + 7414 => Opcode::VCVTSH2SSZrrbk_Int, + 7415 => Opcode::VCVTSH2SSZrrbkz_Int, + 7416 => Opcode::VCVTSH2SSZrrk_Int, + 7417 => Opcode::VCVTSH2SSZrrkz_Int, + 7418 => Opcode::VCVTSH2USI64Zrm_Int, + 7419 => Opcode::VCVTSH2USI64Zrr_Int, + 7420 => Opcode::VCVTSH2USI64Zrrb_Int, + 7421 => Opcode::VCVTSH2USIZrm_Int, + 7422 => Opcode::VCVTSH2USIZrr_Int, + 7423 => Opcode::VCVTSH2USIZrrb_Int, + 7424 => Opcode::VCVTSI2SDZrm, + 7425 => Opcode::VCVTSI2SDZrm_Int, + 7426 => Opcode::VCVTSI2SDZrr, + 7427 => Opcode::VCVTSI2SDZrr_Int, + 7428 => Opcode::VCVTSI2SDrm, + 7429 => Opcode::VCVTSI2SDrm_Int, + 7430 => Opcode::VCVTSI2SDrr, + 7431 => Opcode::VCVTSI2SDrr_Int, + 7432 => Opcode::VCVTSI2SHZrm, + 7433 => Opcode::VCVTSI2SHZrm_Int, + 7434 => Opcode::VCVTSI2SHZrr, + 7435 => Opcode::VCVTSI2SHZrr_Int, + 7436 => Opcode::VCVTSI2SHZrrb_Int, + 7437 => Opcode::VCVTSI2SSZrm, + 7438 => Opcode::VCVTSI2SSZrm_Int, + 7439 => Opcode::VCVTSI2SSZrr, + 7440 => Opcode::VCVTSI2SSZrr_Int, + 7441 => Opcode::VCVTSI2SSZrrb_Int, + 7442 => Opcode::VCVTSI2SSrm, + 7443 => Opcode::VCVTSI2SSrm_Int, + 7444 => Opcode::VCVTSI2SSrr, + 7445 => Opcode::VCVTSI2SSrr_Int, + 7446 => Opcode::VCVTSI642SDZrm, + 7447 => Opcode::VCVTSI642SDZrm_Int, + 7448 => Opcode::VCVTSI642SDZrr, + 7449 => Opcode::VCVTSI642SDZrr_Int, + 7450 => Opcode::VCVTSI642SDZrrb_Int, + 7451 => Opcode::VCVTSI642SDrm, + 7452 => Opcode::VCVTSI642SDrm_Int, + 7453 => Opcode::VCVTSI642SDrr, + 7454 => Opcode::VCVTSI642SDrr_Int, + 7455 => Opcode::VCVTSI642SHZrm, + 7456 => Opcode::VCVTSI642SHZrm_Int, + 7457 => Opcode::VCVTSI642SHZrr, + 7458 => Opcode::VCVTSI642SHZrr_Int, + 7459 => Opcode::VCVTSI642SHZrrb_Int, + 7460 => Opcode::VCVTSI642SSZrm, + 7461 => Opcode::VCVTSI642SSZrm_Int, + 7462 => Opcode::VCVTSI642SSZrr, + 7463 => Opcode::VCVTSI642SSZrr_Int, + 7464 => Opcode::VCVTSI642SSZrrb_Int, + 7465 => Opcode::VCVTSI642SSrm, + 7466 => Opcode::VCVTSI642SSrm_Int, + 7467 => Opcode::VCVTSI642SSrr, + 7468 => Opcode::VCVTSI642SSrr_Int, + 7469 => Opcode::VCVTSS2SDZrm, + 7470 => Opcode::VCVTSS2SDZrm_Int, + 7471 => Opcode::VCVTSS2SDZrmk_Int, + 7472 => Opcode::VCVTSS2SDZrmkz_Int, + 7473 => Opcode::VCVTSS2SDZrr, + 7474 => Opcode::VCVTSS2SDZrr_Int, + 7475 => Opcode::VCVTSS2SDZrrb_Int, + 7476 => Opcode::VCVTSS2SDZrrbk_Int, + 7477 => Opcode::VCVTSS2SDZrrbkz_Int, + 7478 => Opcode::VCVTSS2SDZrrk_Int, + 7479 => Opcode::VCVTSS2SDZrrkz_Int, + 7480 => Opcode::VCVTSS2SDrm, + 7481 => Opcode::VCVTSS2SDrm_Int, + 7482 => Opcode::VCVTSS2SDrr, + 7483 => Opcode::VCVTSS2SDrr_Int, + 7484 => Opcode::VCVTSS2SHZrm, + 7485 => Opcode::VCVTSS2SHZrm_Int, + 7486 => Opcode::VCVTSS2SHZrmk_Int, + 7487 => Opcode::VCVTSS2SHZrmkz_Int, + 7488 => Opcode::VCVTSS2SHZrr, + 7489 => Opcode::VCVTSS2SHZrr_Int, + 7490 => Opcode::VCVTSS2SHZrrb_Int, + 7491 => Opcode::VCVTSS2SHZrrbk_Int, + 7492 => Opcode::VCVTSS2SHZrrbkz_Int, + 7493 => Opcode::VCVTSS2SHZrrk_Int, + 7494 => Opcode::VCVTSS2SHZrrkz_Int, + 7495 => Opcode::VCVTSS2SI64Zrm, + 7496 => Opcode::VCVTSS2SI64Zrm_Int, + 7497 => Opcode::VCVTSS2SI64Zrr, + 7498 => Opcode::VCVTSS2SI64Zrr_Int, + 7499 => Opcode::VCVTSS2SI64Zrrb_Int, + 7500 => Opcode::VCVTSS2SI64rm, + 7501 => Opcode::VCVTSS2SI64rm_Int, + 7502 => Opcode::VCVTSS2SI64rr, + 7503 => Opcode::VCVTSS2SI64rr_Int, + 7504 => Opcode::VCVTSS2SIZrm, + 7505 => Opcode::VCVTSS2SIZrm_Int, + 7506 => Opcode::VCVTSS2SIZrr, + 7507 => Opcode::VCVTSS2SIZrr_Int, + 7508 => Opcode::VCVTSS2SIZrrb_Int, + 7509 => Opcode::VCVTSS2SIrm, + 7510 => Opcode::VCVTSS2SIrm_Int, + 7511 => Opcode::VCVTSS2SIrr, + 7512 => Opcode::VCVTSS2SIrr_Int, + 7513 => Opcode::VCVTSS2USI64Zrm_Int, + 7514 => Opcode::VCVTSS2USI64Zrr_Int, + 7515 => Opcode::VCVTSS2USI64Zrrb_Int, + 7516 => Opcode::VCVTSS2USIZrm_Int, + 7517 => Opcode::VCVTSS2USIZrr_Int, + 7518 => Opcode::VCVTSS2USIZrrb_Int, + 7519 => Opcode::VCVTTBF162IBSZ128rm, + 7520 => Opcode::VCVTTBF162IBSZ128rmb, + 7521 => Opcode::VCVTTBF162IBSZ128rmbk, + 7522 => Opcode::VCVTTBF162IBSZ128rmbkz, + 7523 => Opcode::VCVTTBF162IBSZ128rmk, + 7524 => Opcode::VCVTTBF162IBSZ128rmkz, + 7525 => Opcode::VCVTTBF162IBSZ128rr, + 7526 => Opcode::VCVTTBF162IBSZ128rrk, + 7527 => Opcode::VCVTTBF162IBSZ128rrkz, + 7528 => Opcode::VCVTTBF162IBSZ256rm, + 7529 => Opcode::VCVTTBF162IBSZ256rmb, + 7530 => Opcode::VCVTTBF162IBSZ256rmbk, + 7531 => Opcode::VCVTTBF162IBSZ256rmbkz, + 7532 => Opcode::VCVTTBF162IBSZ256rmk, + 7533 => Opcode::VCVTTBF162IBSZ256rmkz, + 7534 => Opcode::VCVTTBF162IBSZ256rr, + 7535 => Opcode::VCVTTBF162IBSZ256rrk, + 7536 => Opcode::VCVTTBF162IBSZ256rrkz, + 7537 => Opcode::VCVTTBF162IBSZrm, + 7538 => Opcode::VCVTTBF162IBSZrmb, + 7539 => Opcode::VCVTTBF162IBSZrmbk, + 7540 => Opcode::VCVTTBF162IBSZrmbkz, + 7541 => Opcode::VCVTTBF162IBSZrmk, + 7542 => Opcode::VCVTTBF162IBSZrmkz, + 7543 => Opcode::VCVTTBF162IBSZrr, + 7544 => Opcode::VCVTTBF162IBSZrrk, + 7545 => Opcode::VCVTTBF162IBSZrrkz, + 7546 => Opcode::VCVTTBF162IUBSZ128rm, + 7547 => Opcode::VCVTTBF162IUBSZ128rmb, + 7548 => Opcode::VCVTTBF162IUBSZ128rmbk, + 7549 => Opcode::VCVTTBF162IUBSZ128rmbkz, + 7550 => Opcode::VCVTTBF162IUBSZ128rmk, + 7551 => Opcode::VCVTTBF162IUBSZ128rmkz, + 7552 => Opcode::VCVTTBF162IUBSZ128rr, + 7553 => Opcode::VCVTTBF162IUBSZ128rrk, + 7554 => Opcode::VCVTTBF162IUBSZ128rrkz, + 7555 => Opcode::VCVTTBF162IUBSZ256rm, + 7556 => Opcode::VCVTTBF162IUBSZ256rmb, + 7557 => Opcode::VCVTTBF162IUBSZ256rmbk, + 7558 => Opcode::VCVTTBF162IUBSZ256rmbkz, + 7559 => Opcode::VCVTTBF162IUBSZ256rmk, + 7560 => Opcode::VCVTTBF162IUBSZ256rmkz, + 7561 => Opcode::VCVTTBF162IUBSZ256rr, + 7562 => Opcode::VCVTTBF162IUBSZ256rrk, + 7563 => Opcode::VCVTTBF162IUBSZ256rrkz, + 7564 => Opcode::VCVTTBF162IUBSZrm, + 7565 => Opcode::VCVTTBF162IUBSZrmb, + 7566 => Opcode::VCVTTBF162IUBSZrmbk, + 7567 => Opcode::VCVTTBF162IUBSZrmbkz, + 7568 => Opcode::VCVTTBF162IUBSZrmk, + 7569 => Opcode::VCVTTBF162IUBSZrmkz, + 7570 => Opcode::VCVTTBF162IUBSZrr, + 7571 => Opcode::VCVTTBF162IUBSZrrk, + 7572 => Opcode::VCVTTBF162IUBSZrrkz, + 7573 => Opcode::VCVTTPD2DQSZ128rm, + 7574 => Opcode::VCVTTPD2DQSZ128rmb, + 7575 => Opcode::VCVTTPD2DQSZ128rmbk, + 7576 => Opcode::VCVTTPD2DQSZ128rmbkz, + 7577 => Opcode::VCVTTPD2DQSZ128rmk, + 7578 => Opcode::VCVTTPD2DQSZ128rmkz, + 7579 => Opcode::VCVTTPD2DQSZ128rr, + 7580 => Opcode::VCVTTPD2DQSZ128rrk, + 7581 => Opcode::VCVTTPD2DQSZ128rrkz, + 7582 => Opcode::VCVTTPD2DQSZ256rm, + 7583 => Opcode::VCVTTPD2DQSZ256rmb, + 7584 => Opcode::VCVTTPD2DQSZ256rmbk, + 7585 => Opcode::VCVTTPD2DQSZ256rmbkz, + 7586 => Opcode::VCVTTPD2DQSZ256rmk, + 7587 => Opcode::VCVTTPD2DQSZ256rmkz, + 7588 => Opcode::VCVTTPD2DQSZ256rr, + 7589 => Opcode::VCVTTPD2DQSZ256rrb, + 7590 => Opcode::VCVTTPD2DQSZ256rrbk, + 7591 => Opcode::VCVTTPD2DQSZ256rrbkz, + 7592 => Opcode::VCVTTPD2DQSZ256rrk, + 7593 => Opcode::VCVTTPD2DQSZ256rrkz, + 7594 => Opcode::VCVTTPD2DQSZrm, + 7595 => Opcode::VCVTTPD2DQSZrmb, + 7596 => Opcode::VCVTTPD2DQSZrmbk, + 7597 => Opcode::VCVTTPD2DQSZrmbkz, + 7598 => Opcode::VCVTTPD2DQSZrmk, + 7599 => Opcode::VCVTTPD2DQSZrmkz, + 7600 => Opcode::VCVTTPD2DQSZrr, + 7601 => Opcode::VCVTTPD2DQSZrrb, + 7602 => Opcode::VCVTTPD2DQSZrrbk, + 7603 => Opcode::VCVTTPD2DQSZrrbkz, + 7604 => Opcode::VCVTTPD2DQSZrrk, + 7605 => Opcode::VCVTTPD2DQSZrrkz, + 7606 => Opcode::VCVTTPD2DQYrm, + 7607 => Opcode::VCVTTPD2DQYrr, + 7608 => Opcode::VCVTTPD2DQZ128rm, + 7609 => Opcode::VCVTTPD2DQZ128rmb, + 7610 => Opcode::VCVTTPD2DQZ128rmbk, + 7611 => Opcode::VCVTTPD2DQZ128rmbkz, + 7612 => Opcode::VCVTTPD2DQZ128rmk, + 7613 => Opcode::VCVTTPD2DQZ128rmkz, + 7614 => Opcode::VCVTTPD2DQZ128rr, + 7615 => Opcode::VCVTTPD2DQZ128rrk, + 7616 => Opcode::VCVTTPD2DQZ128rrkz, + 7617 => Opcode::VCVTTPD2DQZ256rm, + 7618 => Opcode::VCVTTPD2DQZ256rmb, + 7619 => Opcode::VCVTTPD2DQZ256rmbk, + 7620 => Opcode::VCVTTPD2DQZ256rmbkz, + 7621 => Opcode::VCVTTPD2DQZ256rmk, + 7622 => Opcode::VCVTTPD2DQZ256rmkz, + 7623 => Opcode::VCVTTPD2DQZ256rr, + 7624 => Opcode::VCVTTPD2DQZ256rrk, + 7625 => Opcode::VCVTTPD2DQZ256rrkz, + 7626 => Opcode::VCVTTPD2DQZrm, + 7627 => Opcode::VCVTTPD2DQZrmb, + 7628 => Opcode::VCVTTPD2DQZrmbk, + 7629 => Opcode::VCVTTPD2DQZrmbkz, + 7630 => Opcode::VCVTTPD2DQZrmk, + 7631 => Opcode::VCVTTPD2DQZrmkz, + 7632 => Opcode::VCVTTPD2DQZrr, + 7633 => Opcode::VCVTTPD2DQZrrb, + 7634 => Opcode::VCVTTPD2DQZrrbk, + 7635 => Opcode::VCVTTPD2DQZrrbkz, + 7636 => Opcode::VCVTTPD2DQZrrk, + 7637 => Opcode::VCVTTPD2DQZrrkz, + 7638 => Opcode::VCVTTPD2DQrm, + 7639 => Opcode::VCVTTPD2DQrr, + 7640 => Opcode::VCVTTPD2QQSZ128rm, + 7641 => Opcode::VCVTTPD2QQSZ128rmb, + 7642 => Opcode::VCVTTPD2QQSZ128rmbk, + 7643 => Opcode::VCVTTPD2QQSZ128rmbkz, + 7644 => Opcode::VCVTTPD2QQSZ128rmk, + 7645 => Opcode::VCVTTPD2QQSZ128rmkz, + 7646 => Opcode::VCVTTPD2QQSZ128rr, + 7647 => Opcode::VCVTTPD2QQSZ128rrk, + 7648 => Opcode::VCVTTPD2QQSZ128rrkz, + 7649 => Opcode::VCVTTPD2QQSZ256rm, + 7650 => Opcode::VCVTTPD2QQSZ256rmb, + 7651 => Opcode::VCVTTPD2QQSZ256rmbk, + 7652 => Opcode::VCVTTPD2QQSZ256rmbkz, + 7653 => Opcode::VCVTTPD2QQSZ256rmk, + 7654 => Opcode::VCVTTPD2QQSZ256rmkz, + 7655 => Opcode::VCVTTPD2QQSZ256rr, + 7656 => Opcode::VCVTTPD2QQSZ256rrb, + 7657 => Opcode::VCVTTPD2QQSZ256rrbk, + 7658 => Opcode::VCVTTPD2QQSZ256rrbkz, + 7659 => Opcode::VCVTTPD2QQSZ256rrk, + 7660 => Opcode::VCVTTPD2QQSZ256rrkz, + 7661 => Opcode::VCVTTPD2QQSZrm, + 7662 => Opcode::VCVTTPD2QQSZrmb, + 7663 => Opcode::VCVTTPD2QQSZrmbk, + 7664 => Opcode::VCVTTPD2QQSZrmbkz, + 7665 => Opcode::VCVTTPD2QQSZrmk, + 7666 => Opcode::VCVTTPD2QQSZrmkz, + 7667 => Opcode::VCVTTPD2QQSZrr, + 7668 => Opcode::VCVTTPD2QQSZrrb, + 7669 => Opcode::VCVTTPD2QQSZrrbk, + 7670 => Opcode::VCVTTPD2QQSZrrbkz, + 7671 => Opcode::VCVTTPD2QQSZrrk, + 7672 => Opcode::VCVTTPD2QQSZrrkz, + 7673 => Opcode::VCVTTPD2QQZ128rm, + 7674 => Opcode::VCVTTPD2QQZ128rmb, + 7675 => Opcode::VCVTTPD2QQZ128rmbk, + 7676 => Opcode::VCVTTPD2QQZ128rmbkz, + 7677 => Opcode::VCVTTPD2QQZ128rmk, + 7678 => Opcode::VCVTTPD2QQZ128rmkz, + 7679 => Opcode::VCVTTPD2QQZ128rr, + 7680 => Opcode::VCVTTPD2QQZ128rrk, + 7681 => Opcode::VCVTTPD2QQZ128rrkz, + 7682 => Opcode::VCVTTPD2QQZ256rm, + 7683 => Opcode::VCVTTPD2QQZ256rmb, + 7684 => Opcode::VCVTTPD2QQZ256rmbk, + 7685 => Opcode::VCVTTPD2QQZ256rmbkz, + 7686 => Opcode::VCVTTPD2QQZ256rmk, + 7687 => Opcode::VCVTTPD2QQZ256rmkz, + 7688 => Opcode::VCVTTPD2QQZ256rr, + 7689 => Opcode::VCVTTPD2QQZ256rrk, + 7690 => Opcode::VCVTTPD2QQZ256rrkz, + 7691 => Opcode::VCVTTPD2QQZrm, + 7692 => Opcode::VCVTTPD2QQZrmb, + 7693 => Opcode::VCVTTPD2QQZrmbk, + 7694 => Opcode::VCVTTPD2QQZrmbkz, + 7695 => Opcode::VCVTTPD2QQZrmk, + 7696 => Opcode::VCVTTPD2QQZrmkz, + 7697 => Opcode::VCVTTPD2QQZrr, + 7698 => Opcode::VCVTTPD2QQZrrb, + 7699 => Opcode::VCVTTPD2QQZrrbk, + 7700 => Opcode::VCVTTPD2QQZrrbkz, + 7701 => Opcode::VCVTTPD2QQZrrk, + 7702 => Opcode::VCVTTPD2QQZrrkz, + 7703 => Opcode::VCVTTPD2UDQSZ128rm, + 7704 => Opcode::VCVTTPD2UDQSZ128rmb, + 7705 => Opcode::VCVTTPD2UDQSZ128rmbk, + 7706 => Opcode::VCVTTPD2UDQSZ128rmbkz, + 7707 => Opcode::VCVTTPD2UDQSZ128rmk, + 7708 => Opcode::VCVTTPD2UDQSZ128rmkz, + 7709 => Opcode::VCVTTPD2UDQSZ128rr, + 7710 => Opcode::VCVTTPD2UDQSZ128rrk, + 7711 => Opcode::VCVTTPD2UDQSZ128rrkz, + 7712 => Opcode::VCVTTPD2UDQSZ256rm, + 7713 => Opcode::VCVTTPD2UDQSZ256rmb, + 7714 => Opcode::VCVTTPD2UDQSZ256rmbk, + 7715 => Opcode::VCVTTPD2UDQSZ256rmbkz, + 7716 => Opcode::VCVTTPD2UDQSZ256rmk, + 7717 => Opcode::VCVTTPD2UDQSZ256rmkz, + 7718 => Opcode::VCVTTPD2UDQSZ256rr, + 7719 => Opcode::VCVTTPD2UDQSZ256rrb, + 7720 => Opcode::VCVTTPD2UDQSZ256rrbk, + 7721 => Opcode::VCVTTPD2UDQSZ256rrbkz, + 7722 => Opcode::VCVTTPD2UDQSZ256rrk, + 7723 => Opcode::VCVTTPD2UDQSZ256rrkz, + 7724 => Opcode::VCVTTPD2UDQSZrm, + 7725 => Opcode::VCVTTPD2UDQSZrmb, + 7726 => Opcode::VCVTTPD2UDQSZrmbk, + 7727 => Opcode::VCVTTPD2UDQSZrmbkz, + 7728 => Opcode::VCVTTPD2UDQSZrmk, + 7729 => Opcode::VCVTTPD2UDQSZrmkz, + 7730 => Opcode::VCVTTPD2UDQSZrr, + 7731 => Opcode::VCVTTPD2UDQSZrrb, + 7732 => Opcode::VCVTTPD2UDQSZrrbk, + 7733 => Opcode::VCVTTPD2UDQSZrrbkz, + 7734 => Opcode::VCVTTPD2UDQSZrrk, + 7735 => Opcode::VCVTTPD2UDQSZrrkz, + 7736 => Opcode::VCVTTPD2UDQZ128rm, + 7737 => Opcode::VCVTTPD2UDQZ128rmb, + 7738 => Opcode::VCVTTPD2UDQZ128rmbk, + 7739 => Opcode::VCVTTPD2UDQZ128rmbkz, + 7740 => Opcode::VCVTTPD2UDQZ128rmk, + 7741 => Opcode::VCVTTPD2UDQZ128rmkz, + 7742 => Opcode::VCVTTPD2UDQZ128rr, + 7743 => Opcode::VCVTTPD2UDQZ128rrk, + 7744 => Opcode::VCVTTPD2UDQZ128rrkz, + 7745 => Opcode::VCVTTPD2UDQZ256rm, + 7746 => Opcode::VCVTTPD2UDQZ256rmb, + 7747 => Opcode::VCVTTPD2UDQZ256rmbk, + 7748 => Opcode::VCVTTPD2UDQZ256rmbkz, + 7749 => Opcode::VCVTTPD2UDQZ256rmk, + 7750 => Opcode::VCVTTPD2UDQZ256rmkz, + 7751 => Opcode::VCVTTPD2UDQZ256rr, + 7752 => Opcode::VCVTTPD2UDQZ256rrk, + 7753 => Opcode::VCVTTPD2UDQZ256rrkz, + 7754 => Opcode::VCVTTPD2UDQZrm, + 7755 => Opcode::VCVTTPD2UDQZrmb, + 7756 => Opcode::VCVTTPD2UDQZrmbk, + 7757 => Opcode::VCVTTPD2UDQZrmbkz, + 7758 => Opcode::VCVTTPD2UDQZrmk, + 7759 => Opcode::VCVTTPD2UDQZrmkz, + 7760 => Opcode::VCVTTPD2UDQZrr, + 7761 => Opcode::VCVTTPD2UDQZrrb, + 7762 => Opcode::VCVTTPD2UDQZrrbk, + 7763 => Opcode::VCVTTPD2UDQZrrbkz, + 7764 => Opcode::VCVTTPD2UDQZrrk, + 7765 => Opcode::VCVTTPD2UDQZrrkz, + 7766 => Opcode::VCVTTPD2UQQSZ128rm, + 7767 => Opcode::VCVTTPD2UQQSZ128rmb, + 7768 => Opcode::VCVTTPD2UQQSZ128rmbk, + 7769 => Opcode::VCVTTPD2UQQSZ128rmbkz, + 7770 => Opcode::VCVTTPD2UQQSZ128rmk, + 7771 => Opcode::VCVTTPD2UQQSZ128rmkz, + 7772 => Opcode::VCVTTPD2UQQSZ128rr, + 7773 => Opcode::VCVTTPD2UQQSZ128rrk, + 7774 => Opcode::VCVTTPD2UQQSZ128rrkz, + 7775 => Opcode::VCVTTPD2UQQSZ256rm, + 7776 => Opcode::VCVTTPD2UQQSZ256rmb, + 7777 => Opcode::VCVTTPD2UQQSZ256rmbk, + 7778 => Opcode::VCVTTPD2UQQSZ256rmbkz, + 7779 => Opcode::VCVTTPD2UQQSZ256rmk, + 7780 => Opcode::VCVTTPD2UQQSZ256rmkz, + 7781 => Opcode::VCVTTPD2UQQSZ256rr, + 7782 => Opcode::VCVTTPD2UQQSZ256rrb, + 7783 => Opcode::VCVTTPD2UQQSZ256rrbk, + 7784 => Opcode::VCVTTPD2UQQSZ256rrbkz, + 7785 => Opcode::VCVTTPD2UQQSZ256rrk, + 7786 => Opcode::VCVTTPD2UQQSZ256rrkz, + 7787 => Opcode::VCVTTPD2UQQSZrm, + 7788 => Opcode::VCVTTPD2UQQSZrmb, + 7789 => Opcode::VCVTTPD2UQQSZrmbk, + 7790 => Opcode::VCVTTPD2UQQSZrmbkz, + 7791 => Opcode::VCVTTPD2UQQSZrmk, + 7792 => Opcode::VCVTTPD2UQQSZrmkz, + 7793 => Opcode::VCVTTPD2UQQSZrr, + 7794 => Opcode::VCVTTPD2UQQSZrrb, + 7795 => Opcode::VCVTTPD2UQQSZrrbk, + 7796 => Opcode::VCVTTPD2UQQSZrrbkz, + 7797 => Opcode::VCVTTPD2UQQSZrrk, + 7798 => Opcode::VCVTTPD2UQQSZrrkz, + 7799 => Opcode::VCVTTPD2UQQZ128rm, + 7800 => Opcode::VCVTTPD2UQQZ128rmb, + 7801 => Opcode::VCVTTPD2UQQZ128rmbk, + 7802 => Opcode::VCVTTPD2UQQZ128rmbkz, + 7803 => Opcode::VCVTTPD2UQQZ128rmk, + 7804 => Opcode::VCVTTPD2UQQZ128rmkz, + 7805 => Opcode::VCVTTPD2UQQZ128rr, + 7806 => Opcode::VCVTTPD2UQQZ128rrk, + 7807 => Opcode::VCVTTPD2UQQZ128rrkz, + 7808 => Opcode::VCVTTPD2UQQZ256rm, + 7809 => Opcode::VCVTTPD2UQQZ256rmb, + 7810 => Opcode::VCVTTPD2UQQZ256rmbk, + 7811 => Opcode::VCVTTPD2UQQZ256rmbkz, + 7812 => Opcode::VCVTTPD2UQQZ256rmk, + 7813 => Opcode::VCVTTPD2UQQZ256rmkz, + 7814 => Opcode::VCVTTPD2UQQZ256rr, + 7815 => Opcode::VCVTTPD2UQQZ256rrk, + 7816 => Opcode::VCVTTPD2UQQZ256rrkz, + 7817 => Opcode::VCVTTPD2UQQZrm, + 7818 => Opcode::VCVTTPD2UQQZrmb, + 7819 => Opcode::VCVTTPD2UQQZrmbk, + 7820 => Opcode::VCVTTPD2UQQZrmbkz, + 7821 => Opcode::VCVTTPD2UQQZrmk, + 7822 => Opcode::VCVTTPD2UQQZrmkz, + 7823 => Opcode::VCVTTPD2UQQZrr, + 7824 => Opcode::VCVTTPD2UQQZrrb, + 7825 => Opcode::VCVTTPD2UQQZrrbk, + 7826 => Opcode::VCVTTPD2UQQZrrbkz, + 7827 => Opcode::VCVTTPD2UQQZrrk, + 7828 => Opcode::VCVTTPD2UQQZrrkz, + 7829 => Opcode::VCVTTPH2DQZ128rm, + 7830 => Opcode::VCVTTPH2DQZ128rmb, + 7831 => Opcode::VCVTTPH2DQZ128rmbk, + 7832 => Opcode::VCVTTPH2DQZ128rmbkz, + 7833 => Opcode::VCVTTPH2DQZ128rmk, + 7834 => Opcode::VCVTTPH2DQZ128rmkz, + 7835 => Opcode::VCVTTPH2DQZ128rr, + 7836 => Opcode::VCVTTPH2DQZ128rrk, + 7837 => Opcode::VCVTTPH2DQZ128rrkz, + 7838 => Opcode::VCVTTPH2DQZ256rm, + 7839 => Opcode::VCVTTPH2DQZ256rmb, + 7840 => Opcode::VCVTTPH2DQZ256rmbk, + 7841 => Opcode::VCVTTPH2DQZ256rmbkz, + 7842 => Opcode::VCVTTPH2DQZ256rmk, + 7843 => Opcode::VCVTTPH2DQZ256rmkz, + 7844 => Opcode::VCVTTPH2DQZ256rr, + 7845 => Opcode::VCVTTPH2DQZ256rrk, + 7846 => Opcode::VCVTTPH2DQZ256rrkz, + 7847 => Opcode::VCVTTPH2DQZrm, + 7848 => Opcode::VCVTTPH2DQZrmb, + 7849 => Opcode::VCVTTPH2DQZrmbk, + 7850 => Opcode::VCVTTPH2DQZrmbkz, + 7851 => Opcode::VCVTTPH2DQZrmk, + 7852 => Opcode::VCVTTPH2DQZrmkz, + 7853 => Opcode::VCVTTPH2DQZrr, + 7854 => Opcode::VCVTTPH2DQZrrb, + 7855 => Opcode::VCVTTPH2DQZrrbk, + 7856 => Opcode::VCVTTPH2DQZrrbkz, + 7857 => Opcode::VCVTTPH2DQZrrk, + 7858 => Opcode::VCVTTPH2DQZrrkz, + 7859 => Opcode::VCVTTPH2IBSZ128rm, + 7860 => Opcode::VCVTTPH2IBSZ128rmb, + 7861 => Opcode::VCVTTPH2IBSZ128rmbk, + 7862 => Opcode::VCVTTPH2IBSZ128rmbkz, + 7863 => Opcode::VCVTTPH2IBSZ128rmk, + 7864 => Opcode::VCVTTPH2IBSZ128rmkz, + 7865 => Opcode::VCVTTPH2IBSZ128rr, + 7866 => Opcode::VCVTTPH2IBSZ128rrk, + 7867 => Opcode::VCVTTPH2IBSZ128rrkz, + 7868 => Opcode::VCVTTPH2IBSZ256rm, + 7869 => Opcode::VCVTTPH2IBSZ256rmb, + 7870 => Opcode::VCVTTPH2IBSZ256rmbk, + 7871 => Opcode::VCVTTPH2IBSZ256rmbkz, + 7872 => Opcode::VCVTTPH2IBSZ256rmk, + 7873 => Opcode::VCVTTPH2IBSZ256rmkz, + 7874 => Opcode::VCVTTPH2IBSZ256rr, + 7875 => Opcode::VCVTTPH2IBSZ256rrk, + 7876 => Opcode::VCVTTPH2IBSZ256rrkz, + 7877 => Opcode::VCVTTPH2IBSZrm, + 7878 => Opcode::VCVTTPH2IBSZrmb, + 7879 => Opcode::VCVTTPH2IBSZrmbk, + 7880 => Opcode::VCVTTPH2IBSZrmbkz, + 7881 => Opcode::VCVTTPH2IBSZrmk, + 7882 => Opcode::VCVTTPH2IBSZrmkz, + 7883 => Opcode::VCVTTPH2IBSZrr, + 7884 => Opcode::VCVTTPH2IBSZrrb, + 7885 => Opcode::VCVTTPH2IBSZrrbk, + 7886 => Opcode::VCVTTPH2IBSZrrbkz, + 7887 => Opcode::VCVTTPH2IBSZrrk, + 7888 => Opcode::VCVTTPH2IBSZrrkz, + 7889 => Opcode::VCVTTPH2IUBSZ128rm, + 7890 => Opcode::VCVTTPH2IUBSZ128rmb, + 7891 => Opcode::VCVTTPH2IUBSZ128rmbk, + 7892 => Opcode::VCVTTPH2IUBSZ128rmbkz, + 7893 => Opcode::VCVTTPH2IUBSZ128rmk, + 7894 => Opcode::VCVTTPH2IUBSZ128rmkz, + 7895 => Opcode::VCVTTPH2IUBSZ128rr, + 7896 => Opcode::VCVTTPH2IUBSZ128rrk, + 7897 => Opcode::VCVTTPH2IUBSZ128rrkz, + 7898 => Opcode::VCVTTPH2IUBSZ256rm, + 7899 => Opcode::VCVTTPH2IUBSZ256rmb, + 7900 => Opcode::VCVTTPH2IUBSZ256rmbk, + 7901 => Opcode::VCVTTPH2IUBSZ256rmbkz, + 7902 => Opcode::VCVTTPH2IUBSZ256rmk, + 7903 => Opcode::VCVTTPH2IUBSZ256rmkz, + 7904 => Opcode::VCVTTPH2IUBSZ256rr, + 7905 => Opcode::VCVTTPH2IUBSZ256rrk, + 7906 => Opcode::VCVTTPH2IUBSZ256rrkz, + 7907 => Opcode::VCVTTPH2IUBSZrm, + 7908 => Opcode::VCVTTPH2IUBSZrmb, + 7909 => Opcode::VCVTTPH2IUBSZrmbk, + 7910 => Opcode::VCVTTPH2IUBSZrmbkz, + 7911 => Opcode::VCVTTPH2IUBSZrmk, + 7912 => Opcode::VCVTTPH2IUBSZrmkz, + 7913 => Opcode::VCVTTPH2IUBSZrr, + 7914 => Opcode::VCVTTPH2IUBSZrrb, + 7915 => Opcode::VCVTTPH2IUBSZrrbk, + 7916 => Opcode::VCVTTPH2IUBSZrrbkz, + 7917 => Opcode::VCVTTPH2IUBSZrrk, + 7918 => Opcode::VCVTTPH2IUBSZrrkz, + 7919 => Opcode::VCVTTPH2QQZ128rm, + 7920 => Opcode::VCVTTPH2QQZ128rmb, + 7921 => Opcode::VCVTTPH2QQZ128rmbk, + 7922 => Opcode::VCVTTPH2QQZ128rmbkz, + 7923 => Opcode::VCVTTPH2QQZ128rmk, + 7924 => Opcode::VCVTTPH2QQZ128rmkz, + 7925 => Opcode::VCVTTPH2QQZ128rr, + 7926 => Opcode::VCVTTPH2QQZ128rrk, + 7927 => Opcode::VCVTTPH2QQZ128rrkz, + 7928 => Opcode::VCVTTPH2QQZ256rm, + 7929 => Opcode::VCVTTPH2QQZ256rmb, + 7930 => Opcode::VCVTTPH2QQZ256rmbk, + 7931 => Opcode::VCVTTPH2QQZ256rmbkz, + 7932 => Opcode::VCVTTPH2QQZ256rmk, + 7933 => Opcode::VCVTTPH2QQZ256rmkz, + 7934 => Opcode::VCVTTPH2QQZ256rr, + 7935 => Opcode::VCVTTPH2QQZ256rrk, + 7936 => Opcode::VCVTTPH2QQZ256rrkz, + 7937 => Opcode::VCVTTPH2QQZrm, + 7938 => Opcode::VCVTTPH2QQZrmb, + 7939 => Opcode::VCVTTPH2QQZrmbk, + 7940 => Opcode::VCVTTPH2QQZrmbkz, + 7941 => Opcode::VCVTTPH2QQZrmk, + 7942 => Opcode::VCVTTPH2QQZrmkz, + 7943 => Opcode::VCVTTPH2QQZrr, + 7944 => Opcode::VCVTTPH2QQZrrb, + 7945 => Opcode::VCVTTPH2QQZrrbk, + 7946 => Opcode::VCVTTPH2QQZrrbkz, + 7947 => Opcode::VCVTTPH2QQZrrk, + 7948 => Opcode::VCVTTPH2QQZrrkz, + 7949 => Opcode::VCVTTPH2UDQZ128rm, + 7950 => Opcode::VCVTTPH2UDQZ128rmb, + 7951 => Opcode::VCVTTPH2UDQZ128rmbk, + 7952 => Opcode::VCVTTPH2UDQZ128rmbkz, + 7953 => Opcode::VCVTTPH2UDQZ128rmk, + 7954 => Opcode::VCVTTPH2UDQZ128rmkz, + 7955 => Opcode::VCVTTPH2UDQZ128rr, + 7956 => Opcode::VCVTTPH2UDQZ128rrk, + 7957 => Opcode::VCVTTPH2UDQZ128rrkz, + 7958 => Opcode::VCVTTPH2UDQZ256rm, + 7959 => Opcode::VCVTTPH2UDQZ256rmb, + 7960 => Opcode::VCVTTPH2UDQZ256rmbk, + 7961 => Opcode::VCVTTPH2UDQZ256rmbkz, + 7962 => Opcode::VCVTTPH2UDQZ256rmk, + 7963 => Opcode::VCVTTPH2UDQZ256rmkz, + 7964 => Opcode::VCVTTPH2UDQZ256rr, + 7965 => Opcode::VCVTTPH2UDQZ256rrk, + 7966 => Opcode::VCVTTPH2UDQZ256rrkz, + 7967 => Opcode::VCVTTPH2UDQZrm, + 7968 => Opcode::VCVTTPH2UDQZrmb, + 7969 => Opcode::VCVTTPH2UDQZrmbk, + 7970 => Opcode::VCVTTPH2UDQZrmbkz, + 7971 => Opcode::VCVTTPH2UDQZrmk, + 7972 => Opcode::VCVTTPH2UDQZrmkz, + 7973 => Opcode::VCVTTPH2UDQZrr, + 7974 => Opcode::VCVTTPH2UDQZrrb, + 7975 => Opcode::VCVTTPH2UDQZrrbk, + 7976 => Opcode::VCVTTPH2UDQZrrbkz, + 7977 => Opcode::VCVTTPH2UDQZrrk, + 7978 => Opcode::VCVTTPH2UDQZrrkz, + 7979 => Opcode::VCVTTPH2UQQZ128rm, + 7980 => Opcode::VCVTTPH2UQQZ128rmb, + 7981 => Opcode::VCVTTPH2UQQZ128rmbk, + 7982 => Opcode::VCVTTPH2UQQZ128rmbkz, + 7983 => Opcode::VCVTTPH2UQQZ128rmk, + 7984 => Opcode::VCVTTPH2UQQZ128rmkz, + 7985 => Opcode::VCVTTPH2UQQZ128rr, + 7986 => Opcode::VCVTTPH2UQQZ128rrk, + 7987 => Opcode::VCVTTPH2UQQZ128rrkz, + 7988 => Opcode::VCVTTPH2UQQZ256rm, + 7989 => Opcode::VCVTTPH2UQQZ256rmb, + 7990 => Opcode::VCVTTPH2UQQZ256rmbk, + 7991 => Opcode::VCVTTPH2UQQZ256rmbkz, + 7992 => Opcode::VCVTTPH2UQQZ256rmk, + 7993 => Opcode::VCVTTPH2UQQZ256rmkz, + 7994 => Opcode::VCVTTPH2UQQZ256rr, + 7995 => Opcode::VCVTTPH2UQQZ256rrk, + 7996 => Opcode::VCVTTPH2UQQZ256rrkz, + 7997 => Opcode::VCVTTPH2UQQZrm, + 7998 => Opcode::VCVTTPH2UQQZrmb, + 7999 => Opcode::VCVTTPH2UQQZrmbk, + 8000 => Opcode::VCVTTPH2UQQZrmbkz, + 8001 => Opcode::VCVTTPH2UQQZrmk, + 8002 => Opcode::VCVTTPH2UQQZrmkz, + 8003 => Opcode::VCVTTPH2UQQZrr, + 8004 => Opcode::VCVTTPH2UQQZrrb, + 8005 => Opcode::VCVTTPH2UQQZrrbk, + 8006 => Opcode::VCVTTPH2UQQZrrbkz, + 8007 => Opcode::VCVTTPH2UQQZrrk, + 8008 => Opcode::VCVTTPH2UQQZrrkz, + 8009 => Opcode::VCVTTPH2UWZ128rm, + 8010 => Opcode::VCVTTPH2UWZ128rmb, + 8011 => Opcode::VCVTTPH2UWZ128rmbk, + 8012 => Opcode::VCVTTPH2UWZ128rmbkz, + 8013 => Opcode::VCVTTPH2UWZ128rmk, + 8014 => Opcode::VCVTTPH2UWZ128rmkz, + 8015 => Opcode::VCVTTPH2UWZ128rr, + 8016 => Opcode::VCVTTPH2UWZ128rrk, + 8017 => Opcode::VCVTTPH2UWZ128rrkz, + 8018 => Opcode::VCVTTPH2UWZ256rm, + 8019 => Opcode::VCVTTPH2UWZ256rmb, + 8020 => Opcode::VCVTTPH2UWZ256rmbk, + 8021 => Opcode::VCVTTPH2UWZ256rmbkz, + 8022 => Opcode::VCVTTPH2UWZ256rmk, + 8023 => Opcode::VCVTTPH2UWZ256rmkz, + 8024 => Opcode::VCVTTPH2UWZ256rr, + 8025 => Opcode::VCVTTPH2UWZ256rrk, + 8026 => Opcode::VCVTTPH2UWZ256rrkz, + 8027 => Opcode::VCVTTPH2UWZrm, + 8028 => Opcode::VCVTTPH2UWZrmb, + 8029 => Opcode::VCVTTPH2UWZrmbk, + 8030 => Opcode::VCVTTPH2UWZrmbkz, + 8031 => Opcode::VCVTTPH2UWZrmk, + 8032 => Opcode::VCVTTPH2UWZrmkz, + 8033 => Opcode::VCVTTPH2UWZrr, + 8034 => Opcode::VCVTTPH2UWZrrb, + 8035 => Opcode::VCVTTPH2UWZrrbk, + 8036 => Opcode::VCVTTPH2UWZrrbkz, + 8037 => Opcode::VCVTTPH2UWZrrk, + 8038 => Opcode::VCVTTPH2UWZrrkz, + 8039 => Opcode::VCVTTPH2WZ128rm, + 8040 => Opcode::VCVTTPH2WZ128rmb, + 8041 => Opcode::VCVTTPH2WZ128rmbk, + 8042 => Opcode::VCVTTPH2WZ128rmbkz, + 8043 => Opcode::VCVTTPH2WZ128rmk, + 8044 => Opcode::VCVTTPH2WZ128rmkz, + 8045 => Opcode::VCVTTPH2WZ128rr, + 8046 => Opcode::VCVTTPH2WZ128rrk, + 8047 => Opcode::VCVTTPH2WZ128rrkz, + 8048 => Opcode::VCVTTPH2WZ256rm, + 8049 => Opcode::VCVTTPH2WZ256rmb, + 8050 => Opcode::VCVTTPH2WZ256rmbk, + 8051 => Opcode::VCVTTPH2WZ256rmbkz, + 8052 => Opcode::VCVTTPH2WZ256rmk, + 8053 => Opcode::VCVTTPH2WZ256rmkz, + 8054 => Opcode::VCVTTPH2WZ256rr, + 8055 => Opcode::VCVTTPH2WZ256rrk, + 8056 => Opcode::VCVTTPH2WZ256rrkz, + 8057 => Opcode::VCVTTPH2WZrm, + 8058 => Opcode::VCVTTPH2WZrmb, + 8059 => Opcode::VCVTTPH2WZrmbk, + 8060 => Opcode::VCVTTPH2WZrmbkz, + 8061 => Opcode::VCVTTPH2WZrmk, + 8062 => Opcode::VCVTTPH2WZrmkz, + 8063 => Opcode::VCVTTPH2WZrr, + 8064 => Opcode::VCVTTPH2WZrrb, + 8065 => Opcode::VCVTTPH2WZrrbk, + 8066 => Opcode::VCVTTPH2WZrrbkz, + 8067 => Opcode::VCVTTPH2WZrrk, + 8068 => Opcode::VCVTTPH2WZrrkz, + 8069 => Opcode::VCVTTPS2DQSZ128rm, + 8070 => Opcode::VCVTTPS2DQSZ128rmb, + 8071 => Opcode::VCVTTPS2DQSZ128rmbk, + 8072 => Opcode::VCVTTPS2DQSZ128rmbkz, + 8073 => Opcode::VCVTTPS2DQSZ128rmk, + 8074 => Opcode::VCVTTPS2DQSZ128rmkz, + 8075 => Opcode::VCVTTPS2DQSZ128rr, + 8076 => Opcode::VCVTTPS2DQSZ128rrk, + 8077 => Opcode::VCVTTPS2DQSZ128rrkz, + 8078 => Opcode::VCVTTPS2DQSZ256rm, + 8079 => Opcode::VCVTTPS2DQSZ256rmb, + 8080 => Opcode::VCVTTPS2DQSZ256rmbk, + 8081 => Opcode::VCVTTPS2DQSZ256rmbkz, + 8082 => Opcode::VCVTTPS2DQSZ256rmk, + 8083 => Opcode::VCVTTPS2DQSZ256rmkz, + 8084 => Opcode::VCVTTPS2DQSZ256rr, + 8085 => Opcode::VCVTTPS2DQSZ256rrk, + 8086 => Opcode::VCVTTPS2DQSZ256rrkz, + 8087 => Opcode::VCVTTPS2DQSZrm, + 8088 => Opcode::VCVTTPS2DQSZrmb, + 8089 => Opcode::VCVTTPS2DQSZrmbk, + 8090 => Opcode::VCVTTPS2DQSZrmbkz, + 8091 => Opcode::VCVTTPS2DQSZrmk, + 8092 => Opcode::VCVTTPS2DQSZrmkz, + 8093 => Opcode::VCVTTPS2DQSZrr, + 8094 => Opcode::VCVTTPS2DQSZrrb, + 8095 => Opcode::VCVTTPS2DQSZrrbk, + 8096 => Opcode::VCVTTPS2DQSZrrbkz, + 8097 => Opcode::VCVTTPS2DQSZrrk, + 8098 => Opcode::VCVTTPS2DQSZrrkz, + 8099 => Opcode::VCVTTPS2DQYrm, + 8100 => Opcode::VCVTTPS2DQYrr, + 8101 => Opcode::VCVTTPS2DQZ128rm, + 8102 => Opcode::VCVTTPS2DQZ128rmb, + 8103 => Opcode::VCVTTPS2DQZ128rmbk, + 8104 => Opcode::VCVTTPS2DQZ128rmbkz, + 8105 => Opcode::VCVTTPS2DQZ128rmk, + 8106 => Opcode::VCVTTPS2DQZ128rmkz, + 8107 => Opcode::VCVTTPS2DQZ128rr, + 8108 => Opcode::VCVTTPS2DQZ128rrk, + 8109 => Opcode::VCVTTPS2DQZ128rrkz, + 8110 => Opcode::VCVTTPS2DQZ256rm, + 8111 => Opcode::VCVTTPS2DQZ256rmb, + 8112 => Opcode::VCVTTPS2DQZ256rmbk, + 8113 => Opcode::VCVTTPS2DQZ256rmbkz, + 8114 => Opcode::VCVTTPS2DQZ256rmk, + 8115 => Opcode::VCVTTPS2DQZ256rmkz, + 8116 => Opcode::VCVTTPS2DQZ256rr, + 8117 => Opcode::VCVTTPS2DQZ256rrk, + 8118 => Opcode::VCVTTPS2DQZ256rrkz, + 8119 => Opcode::VCVTTPS2DQZrm, + 8120 => Opcode::VCVTTPS2DQZrmb, + 8121 => Opcode::VCVTTPS2DQZrmbk, + 8122 => Opcode::VCVTTPS2DQZrmbkz, + 8123 => Opcode::VCVTTPS2DQZrmk, + 8124 => Opcode::VCVTTPS2DQZrmkz, + 8125 => Opcode::VCVTTPS2DQZrr, + 8126 => Opcode::VCVTTPS2DQZrrb, + 8127 => Opcode::VCVTTPS2DQZrrbk, + 8128 => Opcode::VCVTTPS2DQZrrbkz, + 8129 => Opcode::VCVTTPS2DQZrrk, + 8130 => Opcode::VCVTTPS2DQZrrkz, + 8131 => Opcode::VCVTTPS2DQrm, + 8132 => Opcode::VCVTTPS2DQrr, + 8133 => Opcode::VCVTTPS2IBSZ128rm, + 8134 => Opcode::VCVTTPS2IBSZ128rmb, + 8135 => Opcode::VCVTTPS2IBSZ128rmbk, + 8136 => Opcode::VCVTTPS2IBSZ128rmbkz, + 8137 => Opcode::VCVTTPS2IBSZ128rmk, + 8138 => Opcode::VCVTTPS2IBSZ128rmkz, + 8139 => Opcode::VCVTTPS2IBSZ128rr, + 8140 => Opcode::VCVTTPS2IBSZ128rrk, + 8141 => Opcode::VCVTTPS2IBSZ128rrkz, + 8142 => Opcode::VCVTTPS2IBSZ256rm, + 8143 => Opcode::VCVTTPS2IBSZ256rmb, + 8144 => Opcode::VCVTTPS2IBSZ256rmbk, + 8145 => Opcode::VCVTTPS2IBSZ256rmbkz, + 8146 => Opcode::VCVTTPS2IBSZ256rmk, + 8147 => Opcode::VCVTTPS2IBSZ256rmkz, + 8148 => Opcode::VCVTTPS2IBSZ256rr, + 8149 => Opcode::VCVTTPS2IBSZ256rrk, + 8150 => Opcode::VCVTTPS2IBSZ256rrkz, + 8151 => Opcode::VCVTTPS2IBSZrm, + 8152 => Opcode::VCVTTPS2IBSZrmb, + 8153 => Opcode::VCVTTPS2IBSZrmbk, + 8154 => Opcode::VCVTTPS2IBSZrmbkz, + 8155 => Opcode::VCVTTPS2IBSZrmk, + 8156 => Opcode::VCVTTPS2IBSZrmkz, + 8157 => Opcode::VCVTTPS2IBSZrr, + 8158 => Opcode::VCVTTPS2IBSZrrb, + 8159 => Opcode::VCVTTPS2IBSZrrbk, + 8160 => Opcode::VCVTTPS2IBSZrrbkz, + 8161 => Opcode::VCVTTPS2IBSZrrk, + 8162 => Opcode::VCVTTPS2IBSZrrkz, + 8163 => Opcode::VCVTTPS2IUBSZ128rm, + 8164 => Opcode::VCVTTPS2IUBSZ128rmb, + 8165 => Opcode::VCVTTPS2IUBSZ128rmbk, + 8166 => Opcode::VCVTTPS2IUBSZ128rmbkz, + 8167 => Opcode::VCVTTPS2IUBSZ128rmk, + 8168 => Opcode::VCVTTPS2IUBSZ128rmkz, + 8169 => Opcode::VCVTTPS2IUBSZ128rr, + 8170 => Opcode::VCVTTPS2IUBSZ128rrk, + 8171 => Opcode::VCVTTPS2IUBSZ128rrkz, + 8172 => Opcode::VCVTTPS2IUBSZ256rm, + 8173 => Opcode::VCVTTPS2IUBSZ256rmb, + 8174 => Opcode::VCVTTPS2IUBSZ256rmbk, + 8175 => Opcode::VCVTTPS2IUBSZ256rmbkz, + 8176 => Opcode::VCVTTPS2IUBSZ256rmk, + 8177 => Opcode::VCVTTPS2IUBSZ256rmkz, + 8178 => Opcode::VCVTTPS2IUBSZ256rr, + 8179 => Opcode::VCVTTPS2IUBSZ256rrk, + 8180 => Opcode::VCVTTPS2IUBSZ256rrkz, + 8181 => Opcode::VCVTTPS2IUBSZrm, + 8182 => Opcode::VCVTTPS2IUBSZrmb, + 8183 => Opcode::VCVTTPS2IUBSZrmbk, + 8184 => Opcode::VCVTTPS2IUBSZrmbkz, + 8185 => Opcode::VCVTTPS2IUBSZrmk, + 8186 => Opcode::VCVTTPS2IUBSZrmkz, + 8187 => Opcode::VCVTTPS2IUBSZrr, + 8188 => Opcode::VCVTTPS2IUBSZrrb, + 8189 => Opcode::VCVTTPS2IUBSZrrbk, + 8190 => Opcode::VCVTTPS2IUBSZrrbkz, + 8191 => Opcode::VCVTTPS2IUBSZrrk, + 8192 => Opcode::VCVTTPS2IUBSZrrkz, + 8193 => Opcode::VCVTTPS2QQSZ128rm, + 8194 => Opcode::VCVTTPS2QQSZ128rmb, + 8195 => Opcode::VCVTTPS2QQSZ128rmbk, + 8196 => Opcode::VCVTTPS2QQSZ128rmbkz, + 8197 => Opcode::VCVTTPS2QQSZ128rmk, + 8198 => Opcode::VCVTTPS2QQSZ128rmkz, + 8199 => Opcode::VCVTTPS2QQSZ128rr, + 8200 => Opcode::VCVTTPS2QQSZ128rrk, + 8201 => Opcode::VCVTTPS2QQSZ128rrkz, + 8202 => Opcode::VCVTTPS2QQSZ256rm, + 8203 => Opcode::VCVTTPS2QQSZ256rmb, + 8204 => Opcode::VCVTTPS2QQSZ256rmbk, + 8205 => Opcode::VCVTTPS2QQSZ256rmbkz, + 8206 => Opcode::VCVTTPS2QQSZ256rmk, + 8207 => Opcode::VCVTTPS2QQSZ256rmkz, + 8208 => Opcode::VCVTTPS2QQSZ256rr, + 8209 => Opcode::VCVTTPS2QQSZ256rrb, + 8210 => Opcode::VCVTTPS2QQSZ256rrbk, + 8211 => Opcode::VCVTTPS2QQSZ256rrbkz, + 8212 => Opcode::VCVTTPS2QQSZ256rrk, + 8213 => Opcode::VCVTTPS2QQSZ256rrkz, + 8214 => Opcode::VCVTTPS2QQSZrm, + 8215 => Opcode::VCVTTPS2QQSZrmb, + 8216 => Opcode::VCVTTPS2QQSZrmbk, + 8217 => Opcode::VCVTTPS2QQSZrmbkz, + 8218 => Opcode::VCVTTPS2QQSZrmk, + 8219 => Opcode::VCVTTPS2QQSZrmkz, + 8220 => Opcode::VCVTTPS2QQSZrr, + 8221 => Opcode::VCVTTPS2QQSZrrb, + 8222 => Opcode::VCVTTPS2QQSZrrbk, + 8223 => Opcode::VCVTTPS2QQSZrrbkz, + 8224 => Opcode::VCVTTPS2QQSZrrk, + 8225 => Opcode::VCVTTPS2QQSZrrkz, + 8226 => Opcode::VCVTTPS2QQZ128rm, + 8227 => Opcode::VCVTTPS2QQZ128rmb, + 8228 => Opcode::VCVTTPS2QQZ128rmbk, + 8229 => Opcode::VCVTTPS2QQZ128rmbkz, + 8230 => Opcode::VCVTTPS2QQZ128rmk, + 8231 => Opcode::VCVTTPS2QQZ128rmkz, + 8232 => Opcode::VCVTTPS2QQZ128rr, + 8233 => Opcode::VCVTTPS2QQZ128rrk, + 8234 => Opcode::VCVTTPS2QQZ128rrkz, + 8235 => Opcode::VCVTTPS2QQZ256rm, + 8236 => Opcode::VCVTTPS2QQZ256rmb, + 8237 => Opcode::VCVTTPS2QQZ256rmbk, + 8238 => Opcode::VCVTTPS2QQZ256rmbkz, + 8239 => Opcode::VCVTTPS2QQZ256rmk, + 8240 => Opcode::VCVTTPS2QQZ256rmkz, + 8241 => Opcode::VCVTTPS2QQZ256rr, + 8242 => Opcode::VCVTTPS2QQZ256rrk, + 8243 => Opcode::VCVTTPS2QQZ256rrkz, + 8244 => Opcode::VCVTTPS2QQZrm, + 8245 => Opcode::VCVTTPS2QQZrmb, + 8246 => Opcode::VCVTTPS2QQZrmbk, + 8247 => Opcode::VCVTTPS2QQZrmbkz, + 8248 => Opcode::VCVTTPS2QQZrmk, + 8249 => Opcode::VCVTTPS2QQZrmkz, + 8250 => Opcode::VCVTTPS2QQZrr, + 8251 => Opcode::VCVTTPS2QQZrrb, + 8252 => Opcode::VCVTTPS2QQZrrbk, + 8253 => Opcode::VCVTTPS2QQZrrbkz, + 8254 => Opcode::VCVTTPS2QQZrrk, + 8255 => Opcode::VCVTTPS2QQZrrkz, + 8256 => Opcode::VCVTTPS2UDQSZ128rm, + 8257 => Opcode::VCVTTPS2UDQSZ128rmb, + 8258 => Opcode::VCVTTPS2UDQSZ128rmbk, + 8259 => Opcode::VCVTTPS2UDQSZ128rmbkz, + 8260 => Opcode::VCVTTPS2UDQSZ128rmk, + 8261 => Opcode::VCVTTPS2UDQSZ128rmkz, + 8262 => Opcode::VCVTTPS2UDQSZ128rr, + 8263 => Opcode::VCVTTPS2UDQSZ128rrk, + 8264 => Opcode::VCVTTPS2UDQSZ128rrkz, + 8265 => Opcode::VCVTTPS2UDQSZ256rm, + 8266 => Opcode::VCVTTPS2UDQSZ256rmb, + 8267 => Opcode::VCVTTPS2UDQSZ256rmbk, + 8268 => Opcode::VCVTTPS2UDQSZ256rmbkz, + 8269 => Opcode::VCVTTPS2UDQSZ256rmk, + 8270 => Opcode::VCVTTPS2UDQSZ256rmkz, + 8271 => Opcode::VCVTTPS2UDQSZ256rr, + 8272 => Opcode::VCVTTPS2UDQSZ256rrk, + 8273 => Opcode::VCVTTPS2UDQSZ256rrkz, + 8274 => Opcode::VCVTTPS2UDQSZrm, + 8275 => Opcode::VCVTTPS2UDQSZrmb, + 8276 => Opcode::VCVTTPS2UDQSZrmbk, + 8277 => Opcode::VCVTTPS2UDQSZrmbkz, + 8278 => Opcode::VCVTTPS2UDQSZrmk, + 8279 => Opcode::VCVTTPS2UDQSZrmkz, + 8280 => Opcode::VCVTTPS2UDQSZrr, + 8281 => Opcode::VCVTTPS2UDQSZrrb, + 8282 => Opcode::VCVTTPS2UDQSZrrbk, + 8283 => Opcode::VCVTTPS2UDQSZrrbkz, + 8284 => Opcode::VCVTTPS2UDQSZrrk, + 8285 => Opcode::VCVTTPS2UDQSZrrkz, + 8286 => Opcode::VCVTTPS2UDQZ128rm, + 8287 => Opcode::VCVTTPS2UDQZ128rmb, + 8288 => Opcode::VCVTTPS2UDQZ128rmbk, + 8289 => Opcode::VCVTTPS2UDQZ128rmbkz, + 8290 => Opcode::VCVTTPS2UDQZ128rmk, + 8291 => Opcode::VCVTTPS2UDQZ128rmkz, + 8292 => Opcode::VCVTTPS2UDQZ128rr, + 8293 => Opcode::VCVTTPS2UDQZ128rrk, + 8294 => Opcode::VCVTTPS2UDQZ128rrkz, + 8295 => Opcode::VCVTTPS2UDQZ256rm, + 8296 => Opcode::VCVTTPS2UDQZ256rmb, + 8297 => Opcode::VCVTTPS2UDQZ256rmbk, + 8298 => Opcode::VCVTTPS2UDQZ256rmbkz, + 8299 => Opcode::VCVTTPS2UDQZ256rmk, + 8300 => Opcode::VCVTTPS2UDQZ256rmkz, + 8301 => Opcode::VCVTTPS2UDQZ256rr, + 8302 => Opcode::VCVTTPS2UDQZ256rrk, + 8303 => Opcode::VCVTTPS2UDQZ256rrkz, + 8304 => Opcode::VCVTTPS2UDQZrm, + 8305 => Opcode::VCVTTPS2UDQZrmb, + 8306 => Opcode::VCVTTPS2UDQZrmbk, + 8307 => Opcode::VCVTTPS2UDQZrmbkz, + 8308 => Opcode::VCVTTPS2UDQZrmk, + 8309 => Opcode::VCVTTPS2UDQZrmkz, + 8310 => Opcode::VCVTTPS2UDQZrr, + 8311 => Opcode::VCVTTPS2UDQZrrb, + 8312 => Opcode::VCVTTPS2UDQZrrbk, + 8313 => Opcode::VCVTTPS2UDQZrrbkz, + 8314 => Opcode::VCVTTPS2UDQZrrk, + 8315 => Opcode::VCVTTPS2UDQZrrkz, + 8316 => Opcode::VCVTTPS2UQQSZ128rm, + 8317 => Opcode::VCVTTPS2UQQSZ128rmb, + 8318 => Opcode::VCVTTPS2UQQSZ128rmbk, + 8319 => Opcode::VCVTTPS2UQQSZ128rmbkz, + 8320 => Opcode::VCVTTPS2UQQSZ128rmk, + 8321 => Opcode::VCVTTPS2UQQSZ128rmkz, + 8322 => Opcode::VCVTTPS2UQQSZ128rr, + 8323 => Opcode::VCVTTPS2UQQSZ128rrk, + 8324 => Opcode::VCVTTPS2UQQSZ128rrkz, + 8325 => Opcode::VCVTTPS2UQQSZ256rm, + 8326 => Opcode::VCVTTPS2UQQSZ256rmb, + 8327 => Opcode::VCVTTPS2UQQSZ256rmbk, + 8328 => Opcode::VCVTTPS2UQQSZ256rmbkz, + 8329 => Opcode::VCVTTPS2UQQSZ256rmk, + 8330 => Opcode::VCVTTPS2UQQSZ256rmkz, + 8331 => Opcode::VCVTTPS2UQQSZ256rr, + 8332 => Opcode::VCVTTPS2UQQSZ256rrb, + 8333 => Opcode::VCVTTPS2UQQSZ256rrbk, + 8334 => Opcode::VCVTTPS2UQQSZ256rrbkz, + 8335 => Opcode::VCVTTPS2UQQSZ256rrk, + 8336 => Opcode::VCVTTPS2UQQSZ256rrkz, + 8337 => Opcode::VCVTTPS2UQQSZrm, + 8338 => Opcode::VCVTTPS2UQQSZrmb, + 8339 => Opcode::VCVTTPS2UQQSZrmbk, + 8340 => Opcode::VCVTTPS2UQQSZrmbkz, + 8341 => Opcode::VCVTTPS2UQQSZrmk, + 8342 => Opcode::VCVTTPS2UQQSZrmkz, + 8343 => Opcode::VCVTTPS2UQQSZrr, + 8344 => Opcode::VCVTTPS2UQQSZrrb, + 8345 => Opcode::VCVTTPS2UQQSZrrbk, + 8346 => Opcode::VCVTTPS2UQQSZrrbkz, + 8347 => Opcode::VCVTTPS2UQQSZrrk, + 8348 => Opcode::VCVTTPS2UQQSZrrkz, + 8349 => Opcode::VCVTTPS2UQQZ128rm, + 8350 => Opcode::VCVTTPS2UQQZ128rmb, + 8351 => Opcode::VCVTTPS2UQQZ128rmbk, + 8352 => Opcode::VCVTTPS2UQQZ128rmbkz, + 8353 => Opcode::VCVTTPS2UQQZ128rmk, + 8354 => Opcode::VCVTTPS2UQQZ128rmkz, + 8355 => Opcode::VCVTTPS2UQQZ128rr, + 8356 => Opcode::VCVTTPS2UQQZ128rrk, + 8357 => Opcode::VCVTTPS2UQQZ128rrkz, + 8358 => Opcode::VCVTTPS2UQQZ256rm, + 8359 => Opcode::VCVTTPS2UQQZ256rmb, + 8360 => Opcode::VCVTTPS2UQQZ256rmbk, + 8361 => Opcode::VCVTTPS2UQQZ256rmbkz, + 8362 => Opcode::VCVTTPS2UQQZ256rmk, + 8363 => Opcode::VCVTTPS2UQQZ256rmkz, + 8364 => Opcode::VCVTTPS2UQQZ256rr, + 8365 => Opcode::VCVTTPS2UQQZ256rrk, + 8366 => Opcode::VCVTTPS2UQQZ256rrkz, + 8367 => Opcode::VCVTTPS2UQQZrm, + 8368 => Opcode::VCVTTPS2UQQZrmb, + 8369 => Opcode::VCVTTPS2UQQZrmbk, + 8370 => Opcode::VCVTTPS2UQQZrmbkz, + 8371 => Opcode::VCVTTPS2UQQZrmk, + 8372 => Opcode::VCVTTPS2UQQZrmkz, + 8373 => Opcode::VCVTTPS2UQQZrr, + 8374 => Opcode::VCVTTPS2UQQZrrb, + 8375 => Opcode::VCVTTPS2UQQZrrbk, + 8376 => Opcode::VCVTTPS2UQQZrrbkz, + 8377 => Opcode::VCVTTPS2UQQZrrk, + 8378 => Opcode::VCVTTPS2UQQZrrkz, + 8379 => Opcode::VCVTTSD2SI64Srm, + 8380 => Opcode::VCVTTSD2SI64Srm_Int, + 8381 => Opcode::VCVTTSD2SI64Srr, + 8382 => Opcode::VCVTTSD2SI64Srr_Int, + 8383 => Opcode::VCVTTSD2SI64Srrb_Int, + 8384 => Opcode::VCVTTSD2SI64Zrm, + 8385 => Opcode::VCVTTSD2SI64Zrm_Int, + 8386 => Opcode::VCVTTSD2SI64Zrr, + 8387 => Opcode::VCVTTSD2SI64Zrr_Int, + 8388 => Opcode::VCVTTSD2SI64Zrrb_Int, + 8389 => Opcode::VCVTTSD2SI64rm, + 8390 => Opcode::VCVTTSD2SI64rm_Int, + 8391 => Opcode::VCVTTSD2SI64rr, + 8392 => Opcode::VCVTTSD2SI64rr_Int, + 8393 => Opcode::VCVTTSD2SISrm, + 8394 => Opcode::VCVTTSD2SISrm_Int, + 8395 => Opcode::VCVTTSD2SISrr, + 8396 => Opcode::VCVTTSD2SISrr_Int, + 8397 => Opcode::VCVTTSD2SISrrb_Int, + 8398 => Opcode::VCVTTSD2SIZrm, + 8399 => Opcode::VCVTTSD2SIZrm_Int, + 8400 => Opcode::VCVTTSD2SIZrr, + 8401 => Opcode::VCVTTSD2SIZrr_Int, + 8402 => Opcode::VCVTTSD2SIZrrb_Int, + 8403 => Opcode::VCVTTSD2SIrm, + 8404 => Opcode::VCVTTSD2SIrm_Int, + 8405 => Opcode::VCVTTSD2SIrr, + 8406 => Opcode::VCVTTSD2SIrr_Int, + 8407 => Opcode::VCVTTSD2USI64Srm, + 8408 => Opcode::VCVTTSD2USI64Srm_Int, + 8409 => Opcode::VCVTTSD2USI64Srr, + 8410 => Opcode::VCVTTSD2USI64Srr_Int, + 8411 => Opcode::VCVTTSD2USI64Srrb_Int, + 8412 => Opcode::VCVTTSD2USI64Zrm, + 8413 => Opcode::VCVTTSD2USI64Zrm_Int, + 8414 => Opcode::VCVTTSD2USI64Zrr, + 8415 => Opcode::VCVTTSD2USI64Zrr_Int, + 8416 => Opcode::VCVTTSD2USI64Zrrb_Int, + 8417 => Opcode::VCVTTSD2USISrm, + 8418 => Opcode::VCVTTSD2USISrm_Int, + 8419 => Opcode::VCVTTSD2USISrr, + 8420 => Opcode::VCVTTSD2USISrr_Int, + 8421 => Opcode::VCVTTSD2USISrrb_Int, + 8422 => Opcode::VCVTTSD2USIZrm, + 8423 => Opcode::VCVTTSD2USIZrm_Int, + 8424 => Opcode::VCVTTSD2USIZrr, + 8425 => Opcode::VCVTTSD2USIZrr_Int, + 8426 => Opcode::VCVTTSD2USIZrrb_Int, + 8427 => Opcode::VCVTTSH2SI64Zrm, + 8428 => Opcode::VCVTTSH2SI64Zrm_Int, + 8429 => Opcode::VCVTTSH2SI64Zrr, + 8430 => Opcode::VCVTTSH2SI64Zrr_Int, + 8431 => Opcode::VCVTTSH2SI64Zrrb_Int, + 8432 => Opcode::VCVTTSH2SIZrm, + 8433 => Opcode::VCVTTSH2SIZrm_Int, + 8434 => Opcode::VCVTTSH2SIZrr, + 8435 => Opcode::VCVTTSH2SIZrr_Int, + 8436 => Opcode::VCVTTSH2SIZrrb_Int, + 8437 => Opcode::VCVTTSH2USI64Zrm, + 8438 => Opcode::VCVTTSH2USI64Zrm_Int, + 8439 => Opcode::VCVTTSH2USI64Zrr, + 8440 => Opcode::VCVTTSH2USI64Zrr_Int, + 8441 => Opcode::VCVTTSH2USI64Zrrb_Int, + 8442 => Opcode::VCVTTSH2USIZrm, + 8443 => Opcode::VCVTTSH2USIZrm_Int, + 8444 => Opcode::VCVTTSH2USIZrr, + 8445 => Opcode::VCVTTSH2USIZrr_Int, + 8446 => Opcode::VCVTTSH2USIZrrb_Int, + 8447 => Opcode::VCVTTSS2SI64Srm, + 8448 => Opcode::VCVTTSS2SI64Srm_Int, + 8449 => Opcode::VCVTTSS2SI64Srr, + 8450 => Opcode::VCVTTSS2SI64Srr_Int, + 8451 => Opcode::VCVTTSS2SI64Srrb_Int, + 8452 => Opcode::VCVTTSS2SI64Zrm, + 8453 => Opcode::VCVTTSS2SI64Zrm_Int, + 8454 => Opcode::VCVTTSS2SI64Zrr, + 8455 => Opcode::VCVTTSS2SI64Zrr_Int, + 8456 => Opcode::VCVTTSS2SI64Zrrb_Int, + 8457 => Opcode::VCVTTSS2SI64rm, + 8458 => Opcode::VCVTTSS2SI64rm_Int, + 8459 => Opcode::VCVTTSS2SI64rr, + 8460 => Opcode::VCVTTSS2SI64rr_Int, + 8461 => Opcode::VCVTTSS2SISrm, + 8462 => Opcode::VCVTTSS2SISrm_Int, + 8463 => Opcode::VCVTTSS2SISrr, + 8464 => Opcode::VCVTTSS2SISrr_Int, + 8465 => Opcode::VCVTTSS2SISrrb_Int, + 8466 => Opcode::VCVTTSS2SIZrm, + 8467 => Opcode::VCVTTSS2SIZrm_Int, + 8468 => Opcode::VCVTTSS2SIZrr, + 8469 => Opcode::VCVTTSS2SIZrr_Int, + 8470 => Opcode::VCVTTSS2SIZrrb_Int, + 8471 => Opcode::VCVTTSS2SIrm, + 8472 => Opcode::VCVTTSS2SIrm_Int, + 8473 => Opcode::VCVTTSS2SIrr, + 8474 => Opcode::VCVTTSS2SIrr_Int, + 8475 => Opcode::VCVTTSS2USI64Srm, + 8476 => Opcode::VCVTTSS2USI64Srm_Int, + 8477 => Opcode::VCVTTSS2USI64Srr, + 8478 => Opcode::VCVTTSS2USI64Srr_Int, + 8479 => Opcode::VCVTTSS2USI64Srrb_Int, + 8480 => Opcode::VCVTTSS2USI64Zrm, + 8481 => Opcode::VCVTTSS2USI64Zrm_Int, + 8482 => Opcode::VCVTTSS2USI64Zrr, + 8483 => Opcode::VCVTTSS2USI64Zrr_Int, + 8484 => Opcode::VCVTTSS2USI64Zrrb_Int, + 8485 => Opcode::VCVTTSS2USISrm, + 8486 => Opcode::VCVTTSS2USISrm_Int, + 8487 => Opcode::VCVTTSS2USISrr, + 8488 => Opcode::VCVTTSS2USISrr_Int, + 8489 => Opcode::VCVTTSS2USISrrb_Int, + 8490 => Opcode::VCVTTSS2USIZrm, + 8491 => Opcode::VCVTTSS2USIZrm_Int, + 8492 => Opcode::VCVTTSS2USIZrr, + 8493 => Opcode::VCVTTSS2USIZrr_Int, + 8494 => Opcode::VCVTTSS2USIZrrb_Int, + 8495 => Opcode::VCVTUDQ2PDZ128rm, + 8496 => Opcode::VCVTUDQ2PDZ128rmb, + 8497 => Opcode::VCVTUDQ2PDZ128rmbk, + 8498 => Opcode::VCVTUDQ2PDZ128rmbkz, + 8499 => Opcode::VCVTUDQ2PDZ128rmk, + 8500 => Opcode::VCVTUDQ2PDZ128rmkz, + 8501 => Opcode::VCVTUDQ2PDZ128rr, + 8502 => Opcode::VCVTUDQ2PDZ128rrk, + 8503 => Opcode::VCVTUDQ2PDZ128rrkz, + 8504 => Opcode::VCVTUDQ2PDZ256rm, + 8505 => Opcode::VCVTUDQ2PDZ256rmb, + 8506 => Opcode::VCVTUDQ2PDZ256rmbk, + 8507 => Opcode::VCVTUDQ2PDZ256rmbkz, + 8508 => Opcode::VCVTUDQ2PDZ256rmk, + 8509 => Opcode::VCVTUDQ2PDZ256rmkz, + 8510 => Opcode::VCVTUDQ2PDZ256rr, + 8511 => Opcode::VCVTUDQ2PDZ256rrk, + 8512 => Opcode::VCVTUDQ2PDZ256rrkz, + 8513 => Opcode::VCVTUDQ2PDZrm, + 8514 => Opcode::VCVTUDQ2PDZrmb, + 8515 => Opcode::VCVTUDQ2PDZrmbk, + 8516 => Opcode::VCVTUDQ2PDZrmbkz, + 8517 => Opcode::VCVTUDQ2PDZrmk, + 8518 => Opcode::VCVTUDQ2PDZrmkz, + 8519 => Opcode::VCVTUDQ2PDZrr, + 8520 => Opcode::VCVTUDQ2PDZrrk, + 8521 => Opcode::VCVTUDQ2PDZrrkz, + 8522 => Opcode::VCVTUDQ2PHZ128rm, + 8523 => Opcode::VCVTUDQ2PHZ128rmb, + 8524 => Opcode::VCVTUDQ2PHZ128rmbk, + 8525 => Opcode::VCVTUDQ2PHZ128rmbkz, + 8526 => Opcode::VCVTUDQ2PHZ128rmk, + 8527 => Opcode::VCVTUDQ2PHZ128rmkz, + 8528 => Opcode::VCVTUDQ2PHZ128rr, + 8529 => Opcode::VCVTUDQ2PHZ128rrk, + 8530 => Opcode::VCVTUDQ2PHZ128rrkz, + 8531 => Opcode::VCVTUDQ2PHZ256rm, + 8532 => Opcode::VCVTUDQ2PHZ256rmb, + 8533 => Opcode::VCVTUDQ2PHZ256rmbk, + 8534 => Opcode::VCVTUDQ2PHZ256rmbkz, + 8535 => Opcode::VCVTUDQ2PHZ256rmk, + 8536 => Opcode::VCVTUDQ2PHZ256rmkz, + 8537 => Opcode::VCVTUDQ2PHZ256rr, + 8538 => Opcode::VCVTUDQ2PHZ256rrk, + 8539 => Opcode::VCVTUDQ2PHZ256rrkz, + 8540 => Opcode::VCVTUDQ2PHZrm, + 8541 => Opcode::VCVTUDQ2PHZrmb, + 8542 => Opcode::VCVTUDQ2PHZrmbk, + 8543 => Opcode::VCVTUDQ2PHZrmbkz, + 8544 => Opcode::VCVTUDQ2PHZrmk, + 8545 => Opcode::VCVTUDQ2PHZrmkz, + 8546 => Opcode::VCVTUDQ2PHZrr, + 8547 => Opcode::VCVTUDQ2PHZrrb, + 8548 => Opcode::VCVTUDQ2PHZrrbk, + 8549 => Opcode::VCVTUDQ2PHZrrbkz, + 8550 => Opcode::VCVTUDQ2PHZrrk, + 8551 => Opcode::VCVTUDQ2PHZrrkz, + 8552 => Opcode::VCVTUDQ2PSZ128rm, + 8553 => Opcode::VCVTUDQ2PSZ128rmb, + 8554 => Opcode::VCVTUDQ2PSZ128rmbk, + 8555 => Opcode::VCVTUDQ2PSZ128rmbkz, + 8556 => Opcode::VCVTUDQ2PSZ128rmk, + 8557 => Opcode::VCVTUDQ2PSZ128rmkz, + 8558 => Opcode::VCVTUDQ2PSZ128rr, + 8559 => Opcode::VCVTUDQ2PSZ128rrk, + 8560 => Opcode::VCVTUDQ2PSZ128rrkz, + 8561 => Opcode::VCVTUDQ2PSZ256rm, + 8562 => Opcode::VCVTUDQ2PSZ256rmb, + 8563 => Opcode::VCVTUDQ2PSZ256rmbk, + 8564 => Opcode::VCVTUDQ2PSZ256rmbkz, + 8565 => Opcode::VCVTUDQ2PSZ256rmk, + 8566 => Opcode::VCVTUDQ2PSZ256rmkz, + 8567 => Opcode::VCVTUDQ2PSZ256rr, + 8568 => Opcode::VCVTUDQ2PSZ256rrk, + 8569 => Opcode::VCVTUDQ2PSZ256rrkz, + 8570 => Opcode::VCVTUDQ2PSZrm, + 8571 => Opcode::VCVTUDQ2PSZrmb, + 8572 => Opcode::VCVTUDQ2PSZrmbk, + 8573 => Opcode::VCVTUDQ2PSZrmbkz, + 8574 => Opcode::VCVTUDQ2PSZrmk, + 8575 => Opcode::VCVTUDQ2PSZrmkz, + 8576 => Opcode::VCVTUDQ2PSZrr, + 8577 => Opcode::VCVTUDQ2PSZrrb, + 8578 => Opcode::VCVTUDQ2PSZrrbk, + 8579 => Opcode::VCVTUDQ2PSZrrbkz, + 8580 => Opcode::VCVTUDQ2PSZrrk, + 8581 => Opcode::VCVTUDQ2PSZrrkz, + 8582 => Opcode::VCVTUQQ2PDZ128rm, + 8583 => Opcode::VCVTUQQ2PDZ128rmb, + 8584 => Opcode::VCVTUQQ2PDZ128rmbk, + 8585 => Opcode::VCVTUQQ2PDZ128rmbkz, + 8586 => Opcode::VCVTUQQ2PDZ128rmk, + 8587 => Opcode::VCVTUQQ2PDZ128rmkz, + 8588 => Opcode::VCVTUQQ2PDZ128rr, + 8589 => Opcode::VCVTUQQ2PDZ128rrk, + 8590 => Opcode::VCVTUQQ2PDZ128rrkz, + 8591 => Opcode::VCVTUQQ2PDZ256rm, + 8592 => Opcode::VCVTUQQ2PDZ256rmb, + 8593 => Opcode::VCVTUQQ2PDZ256rmbk, + 8594 => Opcode::VCVTUQQ2PDZ256rmbkz, + 8595 => Opcode::VCVTUQQ2PDZ256rmk, + 8596 => Opcode::VCVTUQQ2PDZ256rmkz, + 8597 => Opcode::VCVTUQQ2PDZ256rr, + 8598 => Opcode::VCVTUQQ2PDZ256rrk, + 8599 => Opcode::VCVTUQQ2PDZ256rrkz, + 8600 => Opcode::VCVTUQQ2PDZrm, + 8601 => Opcode::VCVTUQQ2PDZrmb, + 8602 => Opcode::VCVTUQQ2PDZrmbk, + 8603 => Opcode::VCVTUQQ2PDZrmbkz, + 8604 => Opcode::VCVTUQQ2PDZrmk, + 8605 => Opcode::VCVTUQQ2PDZrmkz, + 8606 => Opcode::VCVTUQQ2PDZrr, + 8607 => Opcode::VCVTUQQ2PDZrrb, + 8608 => Opcode::VCVTUQQ2PDZrrbk, + 8609 => Opcode::VCVTUQQ2PDZrrbkz, + 8610 => Opcode::VCVTUQQ2PDZrrk, + 8611 => Opcode::VCVTUQQ2PDZrrkz, + 8612 => Opcode::VCVTUQQ2PHZ128rm, + 8613 => Opcode::VCVTUQQ2PHZ128rmb, + 8614 => Opcode::VCVTUQQ2PHZ128rmbk, + 8615 => Opcode::VCVTUQQ2PHZ128rmbkz, + 8616 => Opcode::VCVTUQQ2PHZ128rmk, + 8617 => Opcode::VCVTUQQ2PHZ128rmkz, + 8618 => Opcode::VCVTUQQ2PHZ128rr, + 8619 => Opcode::VCVTUQQ2PHZ128rrk, + 8620 => Opcode::VCVTUQQ2PHZ128rrkz, + 8621 => Opcode::VCVTUQQ2PHZ256rm, + 8622 => Opcode::VCVTUQQ2PHZ256rmb, + 8623 => Opcode::VCVTUQQ2PHZ256rmbk, + 8624 => Opcode::VCVTUQQ2PHZ256rmbkz, + 8625 => Opcode::VCVTUQQ2PHZ256rmk, + 8626 => Opcode::VCVTUQQ2PHZ256rmkz, + 8627 => Opcode::VCVTUQQ2PHZ256rr, + 8628 => Opcode::VCVTUQQ2PHZ256rrk, + 8629 => Opcode::VCVTUQQ2PHZ256rrkz, + 8630 => Opcode::VCVTUQQ2PHZrm, + 8631 => Opcode::VCVTUQQ2PHZrmb, + 8632 => Opcode::VCVTUQQ2PHZrmbk, + 8633 => Opcode::VCVTUQQ2PHZrmbkz, + 8634 => Opcode::VCVTUQQ2PHZrmk, + 8635 => Opcode::VCVTUQQ2PHZrmkz, + 8636 => Opcode::VCVTUQQ2PHZrr, + 8637 => Opcode::VCVTUQQ2PHZrrb, + 8638 => Opcode::VCVTUQQ2PHZrrbk, + 8639 => Opcode::VCVTUQQ2PHZrrbkz, + 8640 => Opcode::VCVTUQQ2PHZrrk, + 8641 => Opcode::VCVTUQQ2PHZrrkz, + 8642 => Opcode::VCVTUQQ2PSZ128rm, + 8643 => Opcode::VCVTUQQ2PSZ128rmb, + 8644 => Opcode::VCVTUQQ2PSZ128rmbk, + 8645 => Opcode::VCVTUQQ2PSZ128rmbkz, + 8646 => Opcode::VCVTUQQ2PSZ128rmk, + 8647 => Opcode::VCVTUQQ2PSZ128rmkz, + 8648 => Opcode::VCVTUQQ2PSZ128rr, + 8649 => Opcode::VCVTUQQ2PSZ128rrk, + 8650 => Opcode::VCVTUQQ2PSZ128rrkz, + 8651 => Opcode::VCVTUQQ2PSZ256rm, + 8652 => Opcode::VCVTUQQ2PSZ256rmb, + 8653 => Opcode::VCVTUQQ2PSZ256rmbk, + 8654 => Opcode::VCVTUQQ2PSZ256rmbkz, + 8655 => Opcode::VCVTUQQ2PSZ256rmk, + 8656 => Opcode::VCVTUQQ2PSZ256rmkz, + 8657 => Opcode::VCVTUQQ2PSZ256rr, + 8658 => Opcode::VCVTUQQ2PSZ256rrk, + 8659 => Opcode::VCVTUQQ2PSZ256rrkz, + 8660 => Opcode::VCVTUQQ2PSZrm, + 8661 => Opcode::VCVTUQQ2PSZrmb, + 8662 => Opcode::VCVTUQQ2PSZrmbk, + 8663 => Opcode::VCVTUQQ2PSZrmbkz, + 8664 => Opcode::VCVTUQQ2PSZrmk, + 8665 => Opcode::VCVTUQQ2PSZrmkz, + 8666 => Opcode::VCVTUQQ2PSZrr, + 8667 => Opcode::VCVTUQQ2PSZrrb, + 8668 => Opcode::VCVTUQQ2PSZrrbk, + 8669 => Opcode::VCVTUQQ2PSZrrbkz, + 8670 => Opcode::VCVTUQQ2PSZrrk, + 8671 => Opcode::VCVTUQQ2PSZrrkz, + 8672 => Opcode::VCVTUSI2SDZrm, + 8673 => Opcode::VCVTUSI2SDZrm_Int, + 8674 => Opcode::VCVTUSI2SDZrr, + 8675 => Opcode::VCVTUSI2SDZrr_Int, + 8676 => Opcode::VCVTUSI2SHZrm, + 8677 => Opcode::VCVTUSI2SHZrm_Int, + 8678 => Opcode::VCVTUSI2SHZrr, + 8679 => Opcode::VCVTUSI2SHZrr_Int, + 8680 => Opcode::VCVTUSI2SHZrrb_Int, + 8681 => Opcode::VCVTUSI2SSZrm, + 8682 => Opcode::VCVTUSI2SSZrm_Int, + 8683 => Opcode::VCVTUSI2SSZrr, + 8684 => Opcode::VCVTUSI2SSZrr_Int, + 8685 => Opcode::VCVTUSI2SSZrrb_Int, + 8686 => Opcode::VCVTUSI642SDZrm, + 8687 => Opcode::VCVTUSI642SDZrm_Int, + 8688 => Opcode::VCVTUSI642SDZrr, + 8689 => Opcode::VCVTUSI642SDZrr_Int, + 8690 => Opcode::VCVTUSI642SDZrrb_Int, + 8691 => Opcode::VCVTUSI642SHZrm, + 8692 => Opcode::VCVTUSI642SHZrm_Int, + 8693 => Opcode::VCVTUSI642SHZrr, + 8694 => Opcode::VCVTUSI642SHZrr_Int, + 8695 => Opcode::VCVTUSI642SHZrrb_Int, + 8696 => Opcode::VCVTUSI642SSZrm, + 8697 => Opcode::VCVTUSI642SSZrm_Int, + 8698 => Opcode::VCVTUSI642SSZrr, + 8699 => Opcode::VCVTUSI642SSZrr_Int, + 8700 => Opcode::VCVTUSI642SSZrrb_Int, + 8701 => Opcode::VCVTUW2PHZ128rm, + 8702 => Opcode::VCVTUW2PHZ128rmb, + 8703 => Opcode::VCVTUW2PHZ128rmbk, + 8704 => Opcode::VCVTUW2PHZ128rmbkz, + 8705 => Opcode::VCVTUW2PHZ128rmk, + 8706 => Opcode::VCVTUW2PHZ128rmkz, + 8707 => Opcode::VCVTUW2PHZ128rr, + 8708 => Opcode::VCVTUW2PHZ128rrk, + 8709 => Opcode::VCVTUW2PHZ128rrkz, + 8710 => Opcode::VCVTUW2PHZ256rm, + 8711 => Opcode::VCVTUW2PHZ256rmb, + 8712 => Opcode::VCVTUW2PHZ256rmbk, + 8713 => Opcode::VCVTUW2PHZ256rmbkz, + 8714 => Opcode::VCVTUW2PHZ256rmk, + 8715 => Opcode::VCVTUW2PHZ256rmkz, + 8716 => Opcode::VCVTUW2PHZ256rr, + 8717 => Opcode::VCVTUW2PHZ256rrk, + 8718 => Opcode::VCVTUW2PHZ256rrkz, + 8719 => Opcode::VCVTUW2PHZrm, + 8720 => Opcode::VCVTUW2PHZrmb, + 8721 => Opcode::VCVTUW2PHZrmbk, + 8722 => Opcode::VCVTUW2PHZrmbkz, + 8723 => Opcode::VCVTUW2PHZrmk, + 8724 => Opcode::VCVTUW2PHZrmkz, + 8725 => Opcode::VCVTUW2PHZrr, + 8726 => Opcode::VCVTUW2PHZrrb, + 8727 => Opcode::VCVTUW2PHZrrbk, + 8728 => Opcode::VCVTUW2PHZrrbkz, + 8729 => Opcode::VCVTUW2PHZrrk, + 8730 => Opcode::VCVTUW2PHZrrkz, + 8731 => Opcode::VCVTW2PHZ128rm, + 8732 => Opcode::VCVTW2PHZ128rmb, + 8733 => Opcode::VCVTW2PHZ128rmbk, + 8734 => Opcode::VCVTW2PHZ128rmbkz, + 8735 => Opcode::VCVTW2PHZ128rmk, + 8736 => Opcode::VCVTW2PHZ128rmkz, + 8737 => Opcode::VCVTW2PHZ128rr, + 8738 => Opcode::VCVTW2PHZ128rrk, + 8739 => Opcode::VCVTW2PHZ128rrkz, + 8740 => Opcode::VCVTW2PHZ256rm, + 8741 => Opcode::VCVTW2PHZ256rmb, + 8742 => Opcode::VCVTW2PHZ256rmbk, + 8743 => Opcode::VCVTW2PHZ256rmbkz, + 8744 => Opcode::VCVTW2PHZ256rmk, + 8745 => Opcode::VCVTW2PHZ256rmkz, + 8746 => Opcode::VCVTW2PHZ256rr, + 8747 => Opcode::VCVTW2PHZ256rrk, + 8748 => Opcode::VCVTW2PHZ256rrkz, + 8749 => Opcode::VCVTW2PHZrm, + 8750 => Opcode::VCVTW2PHZrmb, + 8751 => Opcode::VCVTW2PHZrmbk, + 8752 => Opcode::VCVTW2PHZrmbkz, + 8753 => Opcode::VCVTW2PHZrmk, + 8754 => Opcode::VCVTW2PHZrmkz, + 8755 => Opcode::VCVTW2PHZrr, + 8756 => Opcode::VCVTW2PHZrrb, + 8757 => Opcode::VCVTW2PHZrrbk, + 8758 => Opcode::VCVTW2PHZrrbkz, + 8759 => Opcode::VCVTW2PHZrrk, + 8760 => Opcode::VCVTW2PHZrrkz, + 8761 => Opcode::VDBPSADBWZ128rmi, + 8762 => Opcode::VDBPSADBWZ128rmik, + 8763 => Opcode::VDBPSADBWZ128rmikz, + 8764 => Opcode::VDBPSADBWZ128rri, + 8765 => Opcode::VDBPSADBWZ128rrik, + 8766 => Opcode::VDBPSADBWZ128rrikz, + 8767 => Opcode::VDBPSADBWZ256rmi, + 8768 => Opcode::VDBPSADBWZ256rmik, + 8769 => Opcode::VDBPSADBWZ256rmikz, + 8770 => Opcode::VDBPSADBWZ256rri, + 8771 => Opcode::VDBPSADBWZ256rrik, + 8772 => Opcode::VDBPSADBWZ256rrikz, + 8773 => Opcode::VDBPSADBWZrmi, + 8774 => Opcode::VDBPSADBWZrmik, + 8775 => Opcode::VDBPSADBWZrmikz, + 8776 => Opcode::VDBPSADBWZrri, + 8777 => Opcode::VDBPSADBWZrrik, + 8778 => Opcode::VDBPSADBWZrrikz, + 8779 => Opcode::VDIVBF16Z128rm, + 8780 => Opcode::VDIVBF16Z128rmb, + 8781 => Opcode::VDIVBF16Z128rmbk, + 8782 => Opcode::VDIVBF16Z128rmbkz, + 8783 => Opcode::VDIVBF16Z128rmk, + 8784 => Opcode::VDIVBF16Z128rmkz, + 8785 => Opcode::VDIVBF16Z128rr, + 8786 => Opcode::VDIVBF16Z128rrk, + 8787 => Opcode::VDIVBF16Z128rrkz, + 8788 => Opcode::VDIVBF16Z256rm, + 8789 => Opcode::VDIVBF16Z256rmb, + 8790 => Opcode::VDIVBF16Z256rmbk, + 8791 => Opcode::VDIVBF16Z256rmbkz, + 8792 => Opcode::VDIVBF16Z256rmk, + 8793 => Opcode::VDIVBF16Z256rmkz, + 8794 => Opcode::VDIVBF16Z256rr, + 8795 => Opcode::VDIVBF16Z256rrk, + 8796 => Opcode::VDIVBF16Z256rrkz, + 8797 => Opcode::VDIVBF16Zrm, + 8798 => Opcode::VDIVBF16Zrmb, + 8799 => Opcode::VDIVBF16Zrmbk, + 8800 => Opcode::VDIVBF16Zrmbkz, + 8801 => Opcode::VDIVBF16Zrmk, + 8802 => Opcode::VDIVBF16Zrmkz, + 8803 => Opcode::VDIVBF16Zrr, + 8804 => Opcode::VDIVBF16Zrrk, + 8805 => Opcode::VDIVBF16Zrrkz, + 8806 => Opcode::VDIVPDYrm, + 8807 => Opcode::VDIVPDYrr, + 8808 => Opcode::VDIVPDZ128rm, + 8809 => Opcode::VDIVPDZ128rmb, + 8810 => Opcode::VDIVPDZ128rmbk, + 8811 => Opcode::VDIVPDZ128rmbkz, + 8812 => Opcode::VDIVPDZ128rmk, + 8813 => Opcode::VDIVPDZ128rmkz, + 8814 => Opcode::VDIVPDZ128rr, + 8815 => Opcode::VDIVPDZ128rrk, + 8816 => Opcode::VDIVPDZ128rrkz, + 8817 => Opcode::VDIVPDZ256rm, + 8818 => Opcode::VDIVPDZ256rmb, + 8819 => Opcode::VDIVPDZ256rmbk, + 8820 => Opcode::VDIVPDZ256rmbkz, + 8821 => Opcode::VDIVPDZ256rmk, + 8822 => Opcode::VDIVPDZ256rmkz, + 8823 => Opcode::VDIVPDZ256rr, + 8824 => Opcode::VDIVPDZ256rrk, + 8825 => Opcode::VDIVPDZ256rrkz, + 8826 => Opcode::VDIVPDZrm, + 8827 => Opcode::VDIVPDZrmb, + 8828 => Opcode::VDIVPDZrmbk, + 8829 => Opcode::VDIVPDZrmbkz, + 8830 => Opcode::VDIVPDZrmk, + 8831 => Opcode::VDIVPDZrmkz, + 8832 => Opcode::VDIVPDZrr, + 8833 => Opcode::VDIVPDZrrb, + 8834 => Opcode::VDIVPDZrrbk, + 8835 => Opcode::VDIVPDZrrbkz, + 8836 => Opcode::VDIVPDZrrk, + 8837 => Opcode::VDIVPDZrrkz, + 8838 => Opcode::VDIVPDrm, + 8839 => Opcode::VDIVPDrr, + 8840 => Opcode::VDIVPHZ128rm, + 8841 => Opcode::VDIVPHZ128rmb, + 8842 => Opcode::VDIVPHZ128rmbk, + 8843 => Opcode::VDIVPHZ128rmbkz, + 8844 => Opcode::VDIVPHZ128rmk, + 8845 => Opcode::VDIVPHZ128rmkz, + 8846 => Opcode::VDIVPHZ128rr, + 8847 => Opcode::VDIVPHZ128rrk, + 8848 => Opcode::VDIVPHZ128rrkz, + 8849 => Opcode::VDIVPHZ256rm, + 8850 => Opcode::VDIVPHZ256rmb, + 8851 => Opcode::VDIVPHZ256rmbk, + 8852 => Opcode::VDIVPHZ256rmbkz, + 8853 => Opcode::VDIVPHZ256rmk, + 8854 => Opcode::VDIVPHZ256rmkz, + 8855 => Opcode::VDIVPHZ256rr, + 8856 => Opcode::VDIVPHZ256rrk, + 8857 => Opcode::VDIVPHZ256rrkz, + 8858 => Opcode::VDIVPHZrm, + 8859 => Opcode::VDIVPHZrmb, + 8860 => Opcode::VDIVPHZrmbk, + 8861 => Opcode::VDIVPHZrmbkz, + 8862 => Opcode::VDIVPHZrmk, + 8863 => Opcode::VDIVPHZrmkz, + 8864 => Opcode::VDIVPHZrr, + 8865 => Opcode::VDIVPHZrrb, + 8866 => Opcode::VDIVPHZrrbk, + 8867 => Opcode::VDIVPHZrrbkz, + 8868 => Opcode::VDIVPHZrrk, + 8869 => Opcode::VDIVPHZrrkz, + 8870 => Opcode::VDIVPSYrm, + 8871 => Opcode::VDIVPSYrr, + 8872 => Opcode::VDIVPSZ128rm, + 8873 => Opcode::VDIVPSZ128rmb, + 8874 => Opcode::VDIVPSZ128rmbk, + 8875 => Opcode::VDIVPSZ128rmbkz, + 8876 => Opcode::VDIVPSZ128rmk, + 8877 => Opcode::VDIVPSZ128rmkz, + 8878 => Opcode::VDIVPSZ128rr, + 8879 => Opcode::VDIVPSZ128rrk, + 8880 => Opcode::VDIVPSZ128rrkz, + 8881 => Opcode::VDIVPSZ256rm, + 8882 => Opcode::VDIVPSZ256rmb, + 8883 => Opcode::VDIVPSZ256rmbk, + 8884 => Opcode::VDIVPSZ256rmbkz, + 8885 => Opcode::VDIVPSZ256rmk, + 8886 => Opcode::VDIVPSZ256rmkz, + 8887 => Opcode::VDIVPSZ256rr, + 8888 => Opcode::VDIVPSZ256rrk, + 8889 => Opcode::VDIVPSZ256rrkz, + 8890 => Opcode::VDIVPSZrm, + 8891 => Opcode::VDIVPSZrmb, + 8892 => Opcode::VDIVPSZrmbk, + 8893 => Opcode::VDIVPSZrmbkz, + 8894 => Opcode::VDIVPSZrmk, + 8895 => Opcode::VDIVPSZrmkz, + 8896 => Opcode::VDIVPSZrr, + 8897 => Opcode::VDIVPSZrrb, + 8898 => Opcode::VDIVPSZrrbk, + 8899 => Opcode::VDIVPSZrrbkz, + 8900 => Opcode::VDIVPSZrrk, + 8901 => Opcode::VDIVPSZrrkz, + 8902 => Opcode::VDIVPSrm, + 8903 => Opcode::VDIVPSrr, + 8904 => Opcode::VDIVSDZrm, + 8905 => Opcode::VDIVSDZrm_Int, + 8906 => Opcode::VDIVSDZrmk_Int, + 8907 => Opcode::VDIVSDZrmkz_Int, + 8908 => Opcode::VDIVSDZrr, + 8909 => Opcode::VDIVSDZrr_Int, + 8910 => Opcode::VDIVSDZrrb_Int, + 8911 => Opcode::VDIVSDZrrbk_Int, + 8912 => Opcode::VDIVSDZrrbkz_Int, + 8913 => Opcode::VDIVSDZrrk_Int, + 8914 => Opcode::VDIVSDZrrkz_Int, + 8915 => Opcode::VDIVSDrm, + 8916 => Opcode::VDIVSDrm_Int, + 8917 => Opcode::VDIVSDrr, + 8918 => Opcode::VDIVSDrr_Int, + 8919 => Opcode::VDIVSHZrm, + 8920 => Opcode::VDIVSHZrm_Int, + 8921 => Opcode::VDIVSHZrmk_Int, + 8922 => Opcode::VDIVSHZrmkz_Int, + 8923 => Opcode::VDIVSHZrr, + 8924 => Opcode::VDIVSHZrr_Int, + 8925 => Opcode::VDIVSHZrrb_Int, + 8926 => Opcode::VDIVSHZrrbk_Int, + 8927 => Opcode::VDIVSHZrrbkz_Int, + 8928 => Opcode::VDIVSHZrrk_Int, + 8929 => Opcode::VDIVSHZrrkz_Int, + 8930 => Opcode::VDIVSSZrm, + 8931 => Opcode::VDIVSSZrm_Int, + 8932 => Opcode::VDIVSSZrmk_Int, + 8933 => Opcode::VDIVSSZrmkz_Int, + 8934 => Opcode::VDIVSSZrr, + 8935 => Opcode::VDIVSSZrr_Int, + 8936 => Opcode::VDIVSSZrrb_Int, + 8937 => Opcode::VDIVSSZrrbk_Int, + 8938 => Opcode::VDIVSSZrrbkz_Int, + 8939 => Opcode::VDIVSSZrrk_Int, + 8940 => Opcode::VDIVSSZrrkz_Int, + 8941 => Opcode::VDIVSSrm, + 8942 => Opcode::VDIVSSrm_Int, + 8943 => Opcode::VDIVSSrr, + 8944 => Opcode::VDIVSSrr_Int, + 8945 => Opcode::VDPBF16PSZ128m, + 8946 => Opcode::VDPBF16PSZ128mb, + 8947 => Opcode::VDPBF16PSZ128mbk, + 8948 => Opcode::VDPBF16PSZ128mbkz, + 8949 => Opcode::VDPBF16PSZ128mk, + 8950 => Opcode::VDPBF16PSZ128mkz, + 8951 => Opcode::VDPBF16PSZ128r, + 8952 => Opcode::VDPBF16PSZ128rk, + 8953 => Opcode::VDPBF16PSZ128rkz, + 8954 => Opcode::VDPBF16PSZ256m, + 8955 => Opcode::VDPBF16PSZ256mb, + 8956 => Opcode::VDPBF16PSZ256mbk, + 8957 => Opcode::VDPBF16PSZ256mbkz, + 8958 => Opcode::VDPBF16PSZ256mk, + 8959 => Opcode::VDPBF16PSZ256mkz, + 8960 => Opcode::VDPBF16PSZ256r, + 8961 => Opcode::VDPBF16PSZ256rk, + 8962 => Opcode::VDPBF16PSZ256rkz, + 8963 => Opcode::VDPBF16PSZm, + 8964 => Opcode::VDPBF16PSZmb, + 8965 => Opcode::VDPBF16PSZmbk, + 8966 => Opcode::VDPBF16PSZmbkz, + 8967 => Opcode::VDPBF16PSZmk, + 8968 => Opcode::VDPBF16PSZmkz, + 8969 => Opcode::VDPBF16PSZr, + 8970 => Opcode::VDPBF16PSZrk, + 8971 => Opcode::VDPBF16PSZrkz, + 8972 => Opcode::VDPPDrmi, + 8973 => Opcode::VDPPDrri, + 8974 => Opcode::VDPPHPSZ128m, + 8975 => Opcode::VDPPHPSZ128mb, + 8976 => Opcode::VDPPHPSZ128mbk, + 8977 => Opcode::VDPPHPSZ128mbkz, + 8978 => Opcode::VDPPHPSZ128mk, + 8979 => Opcode::VDPPHPSZ128mkz, + 8980 => Opcode::VDPPHPSZ128r, + 8981 => Opcode::VDPPHPSZ128rk, + 8982 => Opcode::VDPPHPSZ128rkz, + 8983 => Opcode::VDPPHPSZ256m, + 8984 => Opcode::VDPPHPSZ256mb, + 8985 => Opcode::VDPPHPSZ256mbk, + 8986 => Opcode::VDPPHPSZ256mbkz, + 8987 => Opcode::VDPPHPSZ256mk, + 8988 => Opcode::VDPPHPSZ256mkz, + 8989 => Opcode::VDPPHPSZ256r, + 8990 => Opcode::VDPPHPSZ256rk, + 8991 => Opcode::VDPPHPSZ256rkz, + 8992 => Opcode::VDPPHPSZm, + 8993 => Opcode::VDPPHPSZmb, + 8994 => Opcode::VDPPHPSZmbk, + 8995 => Opcode::VDPPHPSZmbkz, + 8996 => Opcode::VDPPHPSZmk, + 8997 => Opcode::VDPPHPSZmkz, + 8998 => Opcode::VDPPHPSZr, + 8999 => Opcode::VDPPHPSZrk, + 9000 => Opcode::VDPPHPSZrkz, + 9001 => Opcode::VDPPSYrmi, + 9002 => Opcode::VDPPSYrri, + 9003 => Opcode::VDPPSrmi, + 9004 => Opcode::VDPPSrri, + 9005 => Opcode::VERRm, + 9006 => Opcode::VERRr, + 9007 => Opcode::VERWm, + 9008 => Opcode::VERWr, + 9009 => Opcode::VEXP2PDZm, + 9010 => Opcode::VEXP2PDZmb, + 9011 => Opcode::VEXP2PDZmbk, + 9012 => Opcode::VEXP2PDZmbkz, + 9013 => Opcode::VEXP2PDZmk, + 9014 => Opcode::VEXP2PDZmkz, + 9015 => Opcode::VEXP2PDZr, + 9016 => Opcode::VEXP2PDZrb, + 9017 => Opcode::VEXP2PDZrbk, + 9018 => Opcode::VEXP2PDZrbkz, + 9019 => Opcode::VEXP2PDZrk, + 9020 => Opcode::VEXP2PDZrkz, + 9021 => Opcode::VEXP2PSZm, + 9022 => Opcode::VEXP2PSZmb, + 9023 => Opcode::VEXP2PSZmbk, + 9024 => Opcode::VEXP2PSZmbkz, + 9025 => Opcode::VEXP2PSZmk, + 9026 => Opcode::VEXP2PSZmkz, + 9027 => Opcode::VEXP2PSZr, + 9028 => Opcode::VEXP2PSZrb, + 9029 => Opcode::VEXP2PSZrbk, + 9030 => Opcode::VEXP2PSZrbkz, + 9031 => Opcode::VEXP2PSZrk, + 9032 => Opcode::VEXP2PSZrkz, + 9033 => Opcode::VEXPANDPDZ128rm, + 9034 => Opcode::VEXPANDPDZ128rmk, + 9035 => Opcode::VEXPANDPDZ128rmkz, + 9036 => Opcode::VEXPANDPDZ128rr, + 9037 => Opcode::VEXPANDPDZ128rrk, + 9038 => Opcode::VEXPANDPDZ128rrkz, + 9039 => Opcode::VEXPANDPDZ256rm, + 9040 => Opcode::VEXPANDPDZ256rmk, + 9041 => Opcode::VEXPANDPDZ256rmkz, + 9042 => Opcode::VEXPANDPDZ256rr, + 9043 => Opcode::VEXPANDPDZ256rrk, + 9044 => Opcode::VEXPANDPDZ256rrkz, + 9045 => Opcode::VEXPANDPDZrm, + 9046 => Opcode::VEXPANDPDZrmk, + 9047 => Opcode::VEXPANDPDZrmkz, + 9048 => Opcode::VEXPANDPDZrr, + 9049 => Opcode::VEXPANDPDZrrk, + 9050 => Opcode::VEXPANDPDZrrkz, + 9051 => Opcode::VEXPANDPSZ128rm, + 9052 => Opcode::VEXPANDPSZ128rmk, + 9053 => Opcode::VEXPANDPSZ128rmkz, + 9054 => Opcode::VEXPANDPSZ128rr, + 9055 => Opcode::VEXPANDPSZ128rrk, + 9056 => Opcode::VEXPANDPSZ128rrkz, + 9057 => Opcode::VEXPANDPSZ256rm, + 9058 => Opcode::VEXPANDPSZ256rmk, + 9059 => Opcode::VEXPANDPSZ256rmkz, + 9060 => Opcode::VEXPANDPSZ256rr, + 9061 => Opcode::VEXPANDPSZ256rrk, + 9062 => Opcode::VEXPANDPSZ256rrkz, + 9063 => Opcode::VEXPANDPSZrm, + 9064 => Opcode::VEXPANDPSZrmk, + 9065 => Opcode::VEXPANDPSZrmkz, + 9066 => Opcode::VEXPANDPSZrr, + 9067 => Opcode::VEXPANDPSZrrk, + 9068 => Opcode::VEXPANDPSZrrkz, + 9069 => Opcode::VEXTRACTF128mri, + 9070 => Opcode::VEXTRACTF128rri, + 9071 => Opcode::VEXTRACTF32X4Z256mri, + 9072 => Opcode::VEXTRACTF32X4Z256mrik, + 9073 => Opcode::VEXTRACTF32X4Z256rri, + 9074 => Opcode::VEXTRACTF32X4Z256rrik, + 9075 => Opcode::VEXTRACTF32X4Z256rrikz, + 9076 => Opcode::VEXTRACTF32X4Zmri, + 9077 => Opcode::VEXTRACTF32X4Zmrik, + 9078 => Opcode::VEXTRACTF32X4Zrri, + 9079 => Opcode::VEXTRACTF32X4Zrrik, + 9080 => Opcode::VEXTRACTF32X4Zrrikz, + 9081 => Opcode::VEXTRACTF32X8Zmri, + 9082 => Opcode::VEXTRACTF32X8Zmrik, + 9083 => Opcode::VEXTRACTF32X8Zrri, + 9084 => Opcode::VEXTRACTF32X8Zrrik, + 9085 => Opcode::VEXTRACTF32X8Zrrikz, + 9086 => Opcode::VEXTRACTF64X2Z256mri, + 9087 => Opcode::VEXTRACTF64X2Z256mrik, + 9088 => Opcode::VEXTRACTF64X2Z256rri, + 9089 => Opcode::VEXTRACTF64X2Z256rrik, + 9090 => Opcode::VEXTRACTF64X2Z256rrikz, + 9091 => Opcode::VEXTRACTF64X2Zmri, + 9092 => Opcode::VEXTRACTF64X2Zmrik, + 9093 => Opcode::VEXTRACTF64X2Zrri, + 9094 => Opcode::VEXTRACTF64X2Zrrik, + 9095 => Opcode::VEXTRACTF64X2Zrrikz, + 9096 => Opcode::VEXTRACTF64X4Zmri, + 9097 => Opcode::VEXTRACTF64X4Zmrik, + 9098 => Opcode::VEXTRACTF64X4Zrri, + 9099 => Opcode::VEXTRACTF64X4Zrrik, + 9100 => Opcode::VEXTRACTF64X4Zrrikz, + 9101 => Opcode::VEXTRACTI128mri, + 9102 => Opcode::VEXTRACTI128rri, + 9103 => Opcode::VEXTRACTI32X4Z256mri, + 9104 => Opcode::VEXTRACTI32X4Z256mrik, + 9105 => Opcode::VEXTRACTI32X4Z256rri, + 9106 => Opcode::VEXTRACTI32X4Z256rrik, + 9107 => Opcode::VEXTRACTI32X4Z256rrikz, + 9108 => Opcode::VEXTRACTI32X4Zmri, + 9109 => Opcode::VEXTRACTI32X4Zmrik, + 9110 => Opcode::VEXTRACTI32X4Zrri, + 9111 => Opcode::VEXTRACTI32X4Zrrik, + 9112 => Opcode::VEXTRACTI32X4Zrrikz, + 9113 => Opcode::VEXTRACTI32X8Zmri, + 9114 => Opcode::VEXTRACTI32X8Zmrik, + 9115 => Opcode::VEXTRACTI32X8Zrri, + 9116 => Opcode::VEXTRACTI32X8Zrrik, + 9117 => Opcode::VEXTRACTI32X8Zrrikz, + 9118 => Opcode::VEXTRACTI64X2Z256mri, + 9119 => Opcode::VEXTRACTI64X2Z256mrik, + 9120 => Opcode::VEXTRACTI64X2Z256rri, + 9121 => Opcode::VEXTRACTI64X2Z256rrik, + 9122 => Opcode::VEXTRACTI64X2Z256rrikz, + 9123 => Opcode::VEXTRACTI64X2Zmri, + 9124 => Opcode::VEXTRACTI64X2Zmrik, + 9125 => Opcode::VEXTRACTI64X2Zrri, + 9126 => Opcode::VEXTRACTI64X2Zrrik, + 9127 => Opcode::VEXTRACTI64X2Zrrikz, + 9128 => Opcode::VEXTRACTI64X4Zmri, + 9129 => Opcode::VEXTRACTI64X4Zmrik, + 9130 => Opcode::VEXTRACTI64X4Zrri, + 9131 => Opcode::VEXTRACTI64X4Zrrik, + 9132 => Opcode::VEXTRACTI64X4Zrrikz, + 9133 => Opcode::VEXTRACTPSZmri, + 9134 => Opcode::VEXTRACTPSZrri, + 9135 => Opcode::VEXTRACTPSmri, + 9136 => Opcode::VEXTRACTPSrri, + 9137 => Opcode::VFCMADDCPHZ128m, + 9138 => Opcode::VFCMADDCPHZ128mb, + 9139 => Opcode::VFCMADDCPHZ128mbk, + 9140 => Opcode::VFCMADDCPHZ128mbkz, + 9141 => Opcode::VFCMADDCPHZ128mk, + 9142 => Opcode::VFCMADDCPHZ128mkz, + 9143 => Opcode::VFCMADDCPHZ128r, + 9144 => Opcode::VFCMADDCPHZ128rk, + 9145 => Opcode::VFCMADDCPHZ128rkz, + 9146 => Opcode::VFCMADDCPHZ256m, + 9147 => Opcode::VFCMADDCPHZ256mb, + 9148 => Opcode::VFCMADDCPHZ256mbk, + 9149 => Opcode::VFCMADDCPHZ256mbkz, + 9150 => Opcode::VFCMADDCPHZ256mk, + 9151 => Opcode::VFCMADDCPHZ256mkz, + 9152 => Opcode::VFCMADDCPHZ256r, + 9153 => Opcode::VFCMADDCPHZ256rk, + 9154 => Opcode::VFCMADDCPHZ256rkz, + 9155 => Opcode::VFCMADDCPHZm, + 9156 => Opcode::VFCMADDCPHZmb, + 9157 => Opcode::VFCMADDCPHZmbk, + 9158 => Opcode::VFCMADDCPHZmbkz, + 9159 => Opcode::VFCMADDCPHZmk, + 9160 => Opcode::VFCMADDCPHZmkz, + 9161 => Opcode::VFCMADDCPHZr, + 9162 => Opcode::VFCMADDCPHZrb, + 9163 => Opcode::VFCMADDCPHZrbk, + 9164 => Opcode::VFCMADDCPHZrbkz, + 9165 => Opcode::VFCMADDCPHZrk, + 9166 => Opcode::VFCMADDCPHZrkz, + 9167 => Opcode::VFCMADDCSHZm, + 9168 => Opcode::VFCMADDCSHZmk, + 9169 => Opcode::VFCMADDCSHZmkz, + 9170 => Opcode::VFCMADDCSHZr, + 9171 => Opcode::VFCMADDCSHZrb, + 9172 => Opcode::VFCMADDCSHZrbk, + 9173 => Opcode::VFCMADDCSHZrbkz, + 9174 => Opcode::VFCMADDCSHZrk, + 9175 => Opcode::VFCMADDCSHZrkz, + 9176 => Opcode::VFCMULCPHZ128rm, + 9177 => Opcode::VFCMULCPHZ128rmb, + 9178 => Opcode::VFCMULCPHZ128rmbk, + 9179 => Opcode::VFCMULCPHZ128rmbkz, + 9180 => Opcode::VFCMULCPHZ128rmk, + 9181 => Opcode::VFCMULCPHZ128rmkz, + 9182 => Opcode::VFCMULCPHZ128rr, + 9183 => Opcode::VFCMULCPHZ128rrk, + 9184 => Opcode::VFCMULCPHZ128rrkz, + 9185 => Opcode::VFCMULCPHZ256rm, + 9186 => Opcode::VFCMULCPHZ256rmb, + 9187 => Opcode::VFCMULCPHZ256rmbk, + 9188 => Opcode::VFCMULCPHZ256rmbkz, + 9189 => Opcode::VFCMULCPHZ256rmk, + 9190 => Opcode::VFCMULCPHZ256rmkz, + 9191 => Opcode::VFCMULCPHZ256rr, + 9192 => Opcode::VFCMULCPHZ256rrk, + 9193 => Opcode::VFCMULCPHZ256rrkz, + 9194 => Opcode::VFCMULCPHZrm, + 9195 => Opcode::VFCMULCPHZrmb, + 9196 => Opcode::VFCMULCPHZrmbk, + 9197 => Opcode::VFCMULCPHZrmbkz, + 9198 => Opcode::VFCMULCPHZrmk, + 9199 => Opcode::VFCMULCPHZrmkz, + 9200 => Opcode::VFCMULCPHZrr, + 9201 => Opcode::VFCMULCPHZrrb, + 9202 => Opcode::VFCMULCPHZrrbk, + 9203 => Opcode::VFCMULCPHZrrbkz, + 9204 => Opcode::VFCMULCPHZrrk, + 9205 => Opcode::VFCMULCPHZrrkz, + 9206 => Opcode::VFCMULCSHZrm, + 9207 => Opcode::VFCMULCSHZrmk, + 9208 => Opcode::VFCMULCSHZrmkz, + 9209 => Opcode::VFCMULCSHZrr, + 9210 => Opcode::VFCMULCSHZrrb, + 9211 => Opcode::VFCMULCSHZrrbk, + 9212 => Opcode::VFCMULCSHZrrbkz, + 9213 => Opcode::VFCMULCSHZrrk, + 9214 => Opcode::VFCMULCSHZrrkz, + 9215 => Opcode::VFIXUPIMMPDZ128rmbi, + 9216 => Opcode::VFIXUPIMMPDZ128rmbik, + 9217 => Opcode::VFIXUPIMMPDZ128rmbikz, + 9218 => Opcode::VFIXUPIMMPDZ128rmi, + 9219 => Opcode::VFIXUPIMMPDZ128rmik, + 9220 => Opcode::VFIXUPIMMPDZ128rmikz, + 9221 => Opcode::VFIXUPIMMPDZ128rri, + 9222 => Opcode::VFIXUPIMMPDZ128rrik, + 9223 => Opcode::VFIXUPIMMPDZ128rrikz, + 9224 => Opcode::VFIXUPIMMPDZ256rmbi, + 9225 => Opcode::VFIXUPIMMPDZ256rmbik, + 9226 => Opcode::VFIXUPIMMPDZ256rmbikz, + 9227 => Opcode::VFIXUPIMMPDZ256rmi, + 9228 => Opcode::VFIXUPIMMPDZ256rmik, + 9229 => Opcode::VFIXUPIMMPDZ256rmikz, + 9230 => Opcode::VFIXUPIMMPDZ256rri, + 9231 => Opcode::VFIXUPIMMPDZ256rrik, + 9232 => Opcode::VFIXUPIMMPDZ256rrikz, + 9233 => Opcode::VFIXUPIMMPDZrmbi, + 9234 => Opcode::VFIXUPIMMPDZrmbik, + 9235 => Opcode::VFIXUPIMMPDZrmbikz, + 9236 => Opcode::VFIXUPIMMPDZrmi, + 9237 => Opcode::VFIXUPIMMPDZrmik, + 9238 => Opcode::VFIXUPIMMPDZrmikz, + 9239 => Opcode::VFIXUPIMMPDZrri, + 9240 => Opcode::VFIXUPIMMPDZrrib, + 9241 => Opcode::VFIXUPIMMPDZrribk, + 9242 => Opcode::VFIXUPIMMPDZrribkz, + 9243 => Opcode::VFIXUPIMMPDZrrik, + 9244 => Opcode::VFIXUPIMMPDZrrikz, + 9245 => Opcode::VFIXUPIMMPSZ128rmbi, + 9246 => Opcode::VFIXUPIMMPSZ128rmbik, + 9247 => Opcode::VFIXUPIMMPSZ128rmbikz, + 9248 => Opcode::VFIXUPIMMPSZ128rmi, + 9249 => Opcode::VFIXUPIMMPSZ128rmik, + 9250 => Opcode::VFIXUPIMMPSZ128rmikz, + 9251 => Opcode::VFIXUPIMMPSZ128rri, + 9252 => Opcode::VFIXUPIMMPSZ128rrik, + 9253 => Opcode::VFIXUPIMMPSZ128rrikz, + 9254 => Opcode::VFIXUPIMMPSZ256rmbi, + 9255 => Opcode::VFIXUPIMMPSZ256rmbik, + 9256 => Opcode::VFIXUPIMMPSZ256rmbikz, + 9257 => Opcode::VFIXUPIMMPSZ256rmi, + 9258 => Opcode::VFIXUPIMMPSZ256rmik, + 9259 => Opcode::VFIXUPIMMPSZ256rmikz, + 9260 => Opcode::VFIXUPIMMPSZ256rri, + 9261 => Opcode::VFIXUPIMMPSZ256rrik, + 9262 => Opcode::VFIXUPIMMPSZ256rrikz, + 9263 => Opcode::VFIXUPIMMPSZrmbi, + 9264 => Opcode::VFIXUPIMMPSZrmbik, + 9265 => Opcode::VFIXUPIMMPSZrmbikz, + 9266 => Opcode::VFIXUPIMMPSZrmi, + 9267 => Opcode::VFIXUPIMMPSZrmik, + 9268 => Opcode::VFIXUPIMMPSZrmikz, + 9269 => Opcode::VFIXUPIMMPSZrri, + 9270 => Opcode::VFIXUPIMMPSZrrib, + 9271 => Opcode::VFIXUPIMMPSZrribk, + 9272 => Opcode::VFIXUPIMMPSZrribkz, + 9273 => Opcode::VFIXUPIMMPSZrrik, + 9274 => Opcode::VFIXUPIMMPSZrrikz, + 9275 => Opcode::VFIXUPIMMSDZrmi, + 9276 => Opcode::VFIXUPIMMSDZrmik, + 9277 => Opcode::VFIXUPIMMSDZrmikz, + 9278 => Opcode::VFIXUPIMMSDZrri, + 9279 => Opcode::VFIXUPIMMSDZrrib, + 9280 => Opcode::VFIXUPIMMSDZrribk, + 9281 => Opcode::VFIXUPIMMSDZrribkz, + 9282 => Opcode::VFIXUPIMMSDZrrik, + 9283 => Opcode::VFIXUPIMMSDZrrikz, + 9284 => Opcode::VFIXUPIMMSSZrmi, + 9285 => Opcode::VFIXUPIMMSSZrmik, + 9286 => Opcode::VFIXUPIMMSSZrmikz, + 9287 => Opcode::VFIXUPIMMSSZrri, + 9288 => Opcode::VFIXUPIMMSSZrrib, + 9289 => Opcode::VFIXUPIMMSSZrribk, + 9290 => Opcode::VFIXUPIMMSSZrribkz, + 9291 => Opcode::VFIXUPIMMSSZrrik, + 9292 => Opcode::VFIXUPIMMSSZrrikz, + 9293 => Opcode::VFMADD132BF16Z128m, + 9294 => Opcode::VFMADD132BF16Z128mb, + 9295 => Opcode::VFMADD132BF16Z128mbk, + 9296 => Opcode::VFMADD132BF16Z128mbkz, + 9297 => Opcode::VFMADD132BF16Z128mk, + 9298 => Opcode::VFMADD132BF16Z128mkz, + 9299 => Opcode::VFMADD132BF16Z128r, + 9300 => Opcode::VFMADD132BF16Z128rk, + 9301 => Opcode::VFMADD132BF16Z128rkz, + 9302 => Opcode::VFMADD132BF16Z256m, + 9303 => Opcode::VFMADD132BF16Z256mb, + 9304 => Opcode::VFMADD132BF16Z256mbk, + 9305 => Opcode::VFMADD132BF16Z256mbkz, + 9306 => Opcode::VFMADD132BF16Z256mk, + 9307 => Opcode::VFMADD132BF16Z256mkz, + 9308 => Opcode::VFMADD132BF16Z256r, + 9309 => Opcode::VFMADD132BF16Z256rk, + 9310 => Opcode::VFMADD132BF16Z256rkz, + 9311 => Opcode::VFMADD132BF16Zm, + 9312 => Opcode::VFMADD132BF16Zmb, + 9313 => Opcode::VFMADD132BF16Zmbk, + 9314 => Opcode::VFMADD132BF16Zmbkz, + 9315 => Opcode::VFMADD132BF16Zmk, + 9316 => Opcode::VFMADD132BF16Zmkz, + 9317 => Opcode::VFMADD132BF16Zr, + 9318 => Opcode::VFMADD132BF16Zrk, + 9319 => Opcode::VFMADD132BF16Zrkz, + 9320 => Opcode::VFMADD132PDYm, + 9321 => Opcode::VFMADD132PDYr, + 9322 => Opcode::VFMADD132PDZ128m, + 9323 => Opcode::VFMADD132PDZ128mb, + 9324 => Opcode::VFMADD132PDZ128mbk, + 9325 => Opcode::VFMADD132PDZ128mbkz, + 9326 => Opcode::VFMADD132PDZ128mk, + 9327 => Opcode::VFMADD132PDZ128mkz, + 9328 => Opcode::VFMADD132PDZ128r, + 9329 => Opcode::VFMADD132PDZ128rk, + 9330 => Opcode::VFMADD132PDZ128rkz, + 9331 => Opcode::VFMADD132PDZ256m, + 9332 => Opcode::VFMADD132PDZ256mb, + 9333 => Opcode::VFMADD132PDZ256mbk, + 9334 => Opcode::VFMADD132PDZ256mbkz, + 9335 => Opcode::VFMADD132PDZ256mk, + 9336 => Opcode::VFMADD132PDZ256mkz, + 9337 => Opcode::VFMADD132PDZ256r, + 9338 => Opcode::VFMADD132PDZ256rk, + 9339 => Opcode::VFMADD132PDZ256rkz, + 9340 => Opcode::VFMADD132PDZm, + 9341 => Opcode::VFMADD132PDZmb, + 9342 => Opcode::VFMADD132PDZmbk, + 9343 => Opcode::VFMADD132PDZmbkz, + 9344 => Opcode::VFMADD132PDZmk, + 9345 => Opcode::VFMADD132PDZmkz, + 9346 => Opcode::VFMADD132PDZr, + 9347 => Opcode::VFMADD132PDZrb, + 9348 => Opcode::VFMADD132PDZrbk, + 9349 => Opcode::VFMADD132PDZrbkz, + 9350 => Opcode::VFMADD132PDZrk, + 9351 => Opcode::VFMADD132PDZrkz, + 9352 => Opcode::VFMADD132PDm, + 9353 => Opcode::VFMADD132PDr, + 9354 => Opcode::VFMADD132PHZ128m, + 9355 => Opcode::VFMADD132PHZ128mb, + 9356 => Opcode::VFMADD132PHZ128mbk, + 9357 => Opcode::VFMADD132PHZ128mbkz, + 9358 => Opcode::VFMADD132PHZ128mk, + 9359 => Opcode::VFMADD132PHZ128mkz, + 9360 => Opcode::VFMADD132PHZ128r, + 9361 => Opcode::VFMADD132PHZ128rk, + 9362 => Opcode::VFMADD132PHZ128rkz, + 9363 => Opcode::VFMADD132PHZ256m, + 9364 => Opcode::VFMADD132PHZ256mb, + 9365 => Opcode::VFMADD132PHZ256mbk, + 9366 => Opcode::VFMADD132PHZ256mbkz, + 9367 => Opcode::VFMADD132PHZ256mk, + 9368 => Opcode::VFMADD132PHZ256mkz, + 9369 => Opcode::VFMADD132PHZ256r, + 9370 => Opcode::VFMADD132PHZ256rk, + 9371 => Opcode::VFMADD132PHZ256rkz, + 9372 => Opcode::VFMADD132PHZm, + 9373 => Opcode::VFMADD132PHZmb, + 9374 => Opcode::VFMADD132PHZmbk, + 9375 => Opcode::VFMADD132PHZmbkz, + 9376 => Opcode::VFMADD132PHZmk, + 9377 => Opcode::VFMADD132PHZmkz, + 9378 => Opcode::VFMADD132PHZr, + 9379 => Opcode::VFMADD132PHZrb, + 9380 => Opcode::VFMADD132PHZrbk, + 9381 => Opcode::VFMADD132PHZrbkz, + 9382 => Opcode::VFMADD132PHZrk, + 9383 => Opcode::VFMADD132PHZrkz, + 9384 => Opcode::VFMADD132PSYm, + 9385 => Opcode::VFMADD132PSYr, + 9386 => Opcode::VFMADD132PSZ128m, + 9387 => Opcode::VFMADD132PSZ128mb, + 9388 => Opcode::VFMADD132PSZ128mbk, + 9389 => Opcode::VFMADD132PSZ128mbkz, + 9390 => Opcode::VFMADD132PSZ128mk, + 9391 => Opcode::VFMADD132PSZ128mkz, + 9392 => Opcode::VFMADD132PSZ128r, + 9393 => Opcode::VFMADD132PSZ128rk, + 9394 => Opcode::VFMADD132PSZ128rkz, + 9395 => Opcode::VFMADD132PSZ256m, + 9396 => Opcode::VFMADD132PSZ256mb, + 9397 => Opcode::VFMADD132PSZ256mbk, + 9398 => Opcode::VFMADD132PSZ256mbkz, + 9399 => Opcode::VFMADD132PSZ256mk, + 9400 => Opcode::VFMADD132PSZ256mkz, + 9401 => Opcode::VFMADD132PSZ256r, + 9402 => Opcode::VFMADD132PSZ256rk, + 9403 => Opcode::VFMADD132PSZ256rkz, + 9404 => Opcode::VFMADD132PSZm, + 9405 => Opcode::VFMADD132PSZmb, + 9406 => Opcode::VFMADD132PSZmbk, + 9407 => Opcode::VFMADD132PSZmbkz, + 9408 => Opcode::VFMADD132PSZmk, + 9409 => Opcode::VFMADD132PSZmkz, + 9410 => Opcode::VFMADD132PSZr, + 9411 => Opcode::VFMADD132PSZrb, + 9412 => Opcode::VFMADD132PSZrbk, + 9413 => Opcode::VFMADD132PSZrbkz, + 9414 => Opcode::VFMADD132PSZrk, + 9415 => Opcode::VFMADD132PSZrkz, + 9416 => Opcode::VFMADD132PSm, + 9417 => Opcode::VFMADD132PSr, + 9418 => Opcode::VFMADD132SDZm, + 9419 => Opcode::VFMADD132SDZm_Int, + 9420 => Opcode::VFMADD132SDZmk_Int, + 9421 => Opcode::VFMADD132SDZmkz_Int, + 9422 => Opcode::VFMADD132SDZr, + 9423 => Opcode::VFMADD132SDZr_Int, + 9424 => Opcode::VFMADD132SDZrb, + 9425 => Opcode::VFMADD132SDZrb_Int, + 9426 => Opcode::VFMADD132SDZrbk_Int, + 9427 => Opcode::VFMADD132SDZrbkz_Int, + 9428 => Opcode::VFMADD132SDZrk_Int, + 9429 => Opcode::VFMADD132SDZrkz_Int, + 9430 => Opcode::VFMADD132SDm, + 9431 => Opcode::VFMADD132SDm_Int, + 9432 => Opcode::VFMADD132SDr, + 9433 => Opcode::VFMADD132SDr_Int, + 9434 => Opcode::VFMADD132SHZm, + 9435 => Opcode::VFMADD132SHZm_Int, + 9436 => Opcode::VFMADD132SHZmk_Int, + 9437 => Opcode::VFMADD132SHZmkz_Int, + 9438 => Opcode::VFMADD132SHZr, + 9439 => Opcode::VFMADD132SHZr_Int, + 9440 => Opcode::VFMADD132SHZrb, + 9441 => Opcode::VFMADD132SHZrb_Int, + 9442 => Opcode::VFMADD132SHZrbk_Int, + 9443 => Opcode::VFMADD132SHZrbkz_Int, + 9444 => Opcode::VFMADD132SHZrk_Int, + 9445 => Opcode::VFMADD132SHZrkz_Int, + 9446 => Opcode::VFMADD132SSZm, + 9447 => Opcode::VFMADD132SSZm_Int, + 9448 => Opcode::VFMADD132SSZmk_Int, + 9449 => Opcode::VFMADD132SSZmkz_Int, + 9450 => Opcode::VFMADD132SSZr, + 9451 => Opcode::VFMADD132SSZr_Int, + 9452 => Opcode::VFMADD132SSZrb, + 9453 => Opcode::VFMADD132SSZrb_Int, + 9454 => Opcode::VFMADD132SSZrbk_Int, + 9455 => Opcode::VFMADD132SSZrbkz_Int, + 9456 => Opcode::VFMADD132SSZrk_Int, + 9457 => Opcode::VFMADD132SSZrkz_Int, + 9458 => Opcode::VFMADD132SSm, + 9459 => Opcode::VFMADD132SSm_Int, + 9460 => Opcode::VFMADD132SSr, + 9461 => Opcode::VFMADD132SSr_Int, + 9462 => Opcode::VFMADD213BF16Z128m, + 9463 => Opcode::VFMADD213BF16Z128mb, + 9464 => Opcode::VFMADD213BF16Z128mbk, + 9465 => Opcode::VFMADD213BF16Z128mbkz, + 9466 => Opcode::VFMADD213BF16Z128mk, + 9467 => Opcode::VFMADD213BF16Z128mkz, + 9468 => Opcode::VFMADD213BF16Z128r, + 9469 => Opcode::VFMADD213BF16Z128rk, + 9470 => Opcode::VFMADD213BF16Z128rkz, + 9471 => Opcode::VFMADD213BF16Z256m, + 9472 => Opcode::VFMADD213BF16Z256mb, + 9473 => Opcode::VFMADD213BF16Z256mbk, + 9474 => Opcode::VFMADD213BF16Z256mbkz, + 9475 => Opcode::VFMADD213BF16Z256mk, + 9476 => Opcode::VFMADD213BF16Z256mkz, + 9477 => Opcode::VFMADD213BF16Z256r, + 9478 => Opcode::VFMADD213BF16Z256rk, + 9479 => Opcode::VFMADD213BF16Z256rkz, + 9480 => Opcode::VFMADD213BF16Zm, + 9481 => Opcode::VFMADD213BF16Zmb, + 9482 => Opcode::VFMADD213BF16Zmbk, + 9483 => Opcode::VFMADD213BF16Zmbkz, + 9484 => Opcode::VFMADD213BF16Zmk, + 9485 => Opcode::VFMADD213BF16Zmkz, + 9486 => Opcode::VFMADD213BF16Zr, + 9487 => Opcode::VFMADD213BF16Zrk, + 9488 => Opcode::VFMADD213BF16Zrkz, + 9489 => Opcode::VFMADD213PDYm, + 9490 => Opcode::VFMADD213PDYr, + 9491 => Opcode::VFMADD213PDZ128m, + 9492 => Opcode::VFMADD213PDZ128mb, + 9493 => Opcode::VFMADD213PDZ128mbk, + 9494 => Opcode::VFMADD213PDZ128mbkz, + 9495 => Opcode::VFMADD213PDZ128mk, + 9496 => Opcode::VFMADD213PDZ128mkz, + 9497 => Opcode::VFMADD213PDZ128r, + 9498 => Opcode::VFMADD213PDZ128rk, + 9499 => Opcode::VFMADD213PDZ128rkz, + 9500 => Opcode::VFMADD213PDZ256m, + 9501 => Opcode::VFMADD213PDZ256mb, + 9502 => Opcode::VFMADD213PDZ256mbk, + 9503 => Opcode::VFMADD213PDZ256mbkz, + 9504 => Opcode::VFMADD213PDZ256mk, + 9505 => Opcode::VFMADD213PDZ256mkz, + 9506 => Opcode::VFMADD213PDZ256r, + 9507 => Opcode::VFMADD213PDZ256rk, + 9508 => Opcode::VFMADD213PDZ256rkz, + 9509 => Opcode::VFMADD213PDZm, + 9510 => Opcode::VFMADD213PDZmb, + 9511 => Opcode::VFMADD213PDZmbk, + 9512 => Opcode::VFMADD213PDZmbkz, + 9513 => Opcode::VFMADD213PDZmk, + 9514 => Opcode::VFMADD213PDZmkz, + 9515 => Opcode::VFMADD213PDZr, + 9516 => Opcode::VFMADD213PDZrb, + 9517 => Opcode::VFMADD213PDZrbk, + 9518 => Opcode::VFMADD213PDZrbkz, + 9519 => Opcode::VFMADD213PDZrk, + 9520 => Opcode::VFMADD213PDZrkz, + 9521 => Opcode::VFMADD213PDm, + 9522 => Opcode::VFMADD213PDr, + 9523 => Opcode::VFMADD213PHZ128m, + 9524 => Opcode::VFMADD213PHZ128mb, + 9525 => Opcode::VFMADD213PHZ128mbk, + 9526 => Opcode::VFMADD213PHZ128mbkz, + 9527 => Opcode::VFMADD213PHZ128mk, + 9528 => Opcode::VFMADD213PHZ128mkz, + 9529 => Opcode::VFMADD213PHZ128r, + 9530 => Opcode::VFMADD213PHZ128rk, + 9531 => Opcode::VFMADD213PHZ128rkz, + 9532 => Opcode::VFMADD213PHZ256m, + 9533 => Opcode::VFMADD213PHZ256mb, + 9534 => Opcode::VFMADD213PHZ256mbk, + 9535 => Opcode::VFMADD213PHZ256mbkz, + 9536 => Opcode::VFMADD213PHZ256mk, + 9537 => Opcode::VFMADD213PHZ256mkz, + 9538 => Opcode::VFMADD213PHZ256r, + 9539 => Opcode::VFMADD213PHZ256rk, + 9540 => Opcode::VFMADD213PHZ256rkz, + 9541 => Opcode::VFMADD213PHZm, + 9542 => Opcode::VFMADD213PHZmb, + 9543 => Opcode::VFMADD213PHZmbk, + 9544 => Opcode::VFMADD213PHZmbkz, + 9545 => Opcode::VFMADD213PHZmk, + 9546 => Opcode::VFMADD213PHZmkz, + 9547 => Opcode::VFMADD213PHZr, + 9548 => Opcode::VFMADD213PHZrb, + 9549 => Opcode::VFMADD213PHZrbk, + 9550 => Opcode::VFMADD213PHZrbkz, + 9551 => Opcode::VFMADD213PHZrk, + 9552 => Opcode::VFMADD213PHZrkz, + 9553 => Opcode::VFMADD213PSYm, + 9554 => Opcode::VFMADD213PSYr, + 9555 => Opcode::VFMADD213PSZ128m, + 9556 => Opcode::VFMADD213PSZ128mb, + 9557 => Opcode::VFMADD213PSZ128mbk, + 9558 => Opcode::VFMADD213PSZ128mbkz, + 9559 => Opcode::VFMADD213PSZ128mk, + 9560 => Opcode::VFMADD213PSZ128mkz, + 9561 => Opcode::VFMADD213PSZ128r, + 9562 => Opcode::VFMADD213PSZ128rk, + 9563 => Opcode::VFMADD213PSZ128rkz, + 9564 => Opcode::VFMADD213PSZ256m, + 9565 => Opcode::VFMADD213PSZ256mb, + 9566 => Opcode::VFMADD213PSZ256mbk, + 9567 => Opcode::VFMADD213PSZ256mbkz, + 9568 => Opcode::VFMADD213PSZ256mk, + 9569 => Opcode::VFMADD213PSZ256mkz, + 9570 => Opcode::VFMADD213PSZ256r, + 9571 => Opcode::VFMADD213PSZ256rk, + 9572 => Opcode::VFMADD213PSZ256rkz, + 9573 => Opcode::VFMADD213PSZm, + 9574 => Opcode::VFMADD213PSZmb, + 9575 => Opcode::VFMADD213PSZmbk, + 9576 => Opcode::VFMADD213PSZmbkz, + 9577 => Opcode::VFMADD213PSZmk, + 9578 => Opcode::VFMADD213PSZmkz, + 9579 => Opcode::VFMADD213PSZr, + 9580 => Opcode::VFMADD213PSZrb, + 9581 => Opcode::VFMADD213PSZrbk, + 9582 => Opcode::VFMADD213PSZrbkz, + 9583 => Opcode::VFMADD213PSZrk, + 9584 => Opcode::VFMADD213PSZrkz, + 9585 => Opcode::VFMADD213PSm, + 9586 => Opcode::VFMADD213PSr, + 9587 => Opcode::VFMADD213SDZm, + 9588 => Opcode::VFMADD213SDZm_Int, + 9589 => Opcode::VFMADD213SDZmk_Int, + 9590 => Opcode::VFMADD213SDZmkz_Int, + 9591 => Opcode::VFMADD213SDZr, + 9592 => Opcode::VFMADD213SDZr_Int, + 9593 => Opcode::VFMADD213SDZrb, + 9594 => Opcode::VFMADD213SDZrb_Int, + 9595 => Opcode::VFMADD213SDZrbk_Int, + 9596 => Opcode::VFMADD213SDZrbkz_Int, + 9597 => Opcode::VFMADD213SDZrk_Int, + 9598 => Opcode::VFMADD213SDZrkz_Int, + 9599 => Opcode::VFMADD213SDm, + 9600 => Opcode::VFMADD213SDm_Int, + 9601 => Opcode::VFMADD213SDr, + 9602 => Opcode::VFMADD213SDr_Int, + 9603 => Opcode::VFMADD213SHZm, + 9604 => Opcode::VFMADD213SHZm_Int, + 9605 => Opcode::VFMADD213SHZmk_Int, + 9606 => Opcode::VFMADD213SHZmkz_Int, + 9607 => Opcode::VFMADD213SHZr, + 9608 => Opcode::VFMADD213SHZr_Int, + 9609 => Opcode::VFMADD213SHZrb, + 9610 => Opcode::VFMADD213SHZrb_Int, + 9611 => Opcode::VFMADD213SHZrbk_Int, + 9612 => Opcode::VFMADD213SHZrbkz_Int, + 9613 => Opcode::VFMADD213SHZrk_Int, + 9614 => Opcode::VFMADD213SHZrkz_Int, + 9615 => Opcode::VFMADD213SSZm, + 9616 => Opcode::VFMADD213SSZm_Int, + 9617 => Opcode::VFMADD213SSZmk_Int, + 9618 => Opcode::VFMADD213SSZmkz_Int, + 9619 => Opcode::VFMADD213SSZr, + 9620 => Opcode::VFMADD213SSZr_Int, + 9621 => Opcode::VFMADD213SSZrb, + 9622 => Opcode::VFMADD213SSZrb_Int, + 9623 => Opcode::VFMADD213SSZrbk_Int, + 9624 => Opcode::VFMADD213SSZrbkz_Int, + 9625 => Opcode::VFMADD213SSZrk_Int, + 9626 => Opcode::VFMADD213SSZrkz_Int, + 9627 => Opcode::VFMADD213SSm, + 9628 => Opcode::VFMADD213SSm_Int, + 9629 => Opcode::VFMADD213SSr, + 9630 => Opcode::VFMADD213SSr_Int, + 9631 => Opcode::VFMADD231BF16Z128m, + 9632 => Opcode::VFMADD231BF16Z128mb, + 9633 => Opcode::VFMADD231BF16Z128mbk, + 9634 => Opcode::VFMADD231BF16Z128mbkz, + 9635 => Opcode::VFMADD231BF16Z128mk, + 9636 => Opcode::VFMADD231BF16Z128mkz, + 9637 => Opcode::VFMADD231BF16Z128r, + 9638 => Opcode::VFMADD231BF16Z128rk, + 9639 => Opcode::VFMADD231BF16Z128rkz, + 9640 => Opcode::VFMADD231BF16Z256m, + 9641 => Opcode::VFMADD231BF16Z256mb, + 9642 => Opcode::VFMADD231BF16Z256mbk, + 9643 => Opcode::VFMADD231BF16Z256mbkz, + 9644 => Opcode::VFMADD231BF16Z256mk, + 9645 => Opcode::VFMADD231BF16Z256mkz, + 9646 => Opcode::VFMADD231BF16Z256r, + 9647 => Opcode::VFMADD231BF16Z256rk, + 9648 => Opcode::VFMADD231BF16Z256rkz, + 9649 => Opcode::VFMADD231BF16Zm, + 9650 => Opcode::VFMADD231BF16Zmb, + 9651 => Opcode::VFMADD231BF16Zmbk, + 9652 => Opcode::VFMADD231BF16Zmbkz, + 9653 => Opcode::VFMADD231BF16Zmk, + 9654 => Opcode::VFMADD231BF16Zmkz, + 9655 => Opcode::VFMADD231BF16Zr, + 9656 => Opcode::VFMADD231BF16Zrk, + 9657 => Opcode::VFMADD231BF16Zrkz, + 9658 => Opcode::VFMADD231PDYm, + 9659 => Opcode::VFMADD231PDYr, + 9660 => Opcode::VFMADD231PDZ128m, + 9661 => Opcode::VFMADD231PDZ128mb, + 9662 => Opcode::VFMADD231PDZ128mbk, + 9663 => Opcode::VFMADD231PDZ128mbkz, + 9664 => Opcode::VFMADD231PDZ128mk, + 9665 => Opcode::VFMADD231PDZ128mkz, + 9666 => Opcode::VFMADD231PDZ128r, + 9667 => Opcode::VFMADD231PDZ128rk, + 9668 => Opcode::VFMADD231PDZ128rkz, + 9669 => Opcode::VFMADD231PDZ256m, + 9670 => Opcode::VFMADD231PDZ256mb, + 9671 => Opcode::VFMADD231PDZ256mbk, + 9672 => Opcode::VFMADD231PDZ256mbkz, + 9673 => Opcode::VFMADD231PDZ256mk, + 9674 => Opcode::VFMADD231PDZ256mkz, + 9675 => Opcode::VFMADD231PDZ256r, + 9676 => Opcode::VFMADD231PDZ256rk, + 9677 => Opcode::VFMADD231PDZ256rkz, + 9678 => Opcode::VFMADD231PDZm, + 9679 => Opcode::VFMADD231PDZmb, + 9680 => Opcode::VFMADD231PDZmbk, + 9681 => Opcode::VFMADD231PDZmbkz, + 9682 => Opcode::VFMADD231PDZmk, + 9683 => Opcode::VFMADD231PDZmkz, + 9684 => Opcode::VFMADD231PDZr, + 9685 => Opcode::VFMADD231PDZrb, + 9686 => Opcode::VFMADD231PDZrbk, + 9687 => Opcode::VFMADD231PDZrbkz, + 9688 => Opcode::VFMADD231PDZrk, + 9689 => Opcode::VFMADD231PDZrkz, + 9690 => Opcode::VFMADD231PDm, + 9691 => Opcode::VFMADD231PDr, + 9692 => Opcode::VFMADD231PHZ128m, + 9693 => Opcode::VFMADD231PHZ128mb, + 9694 => Opcode::VFMADD231PHZ128mbk, + 9695 => Opcode::VFMADD231PHZ128mbkz, + 9696 => Opcode::VFMADD231PHZ128mk, + 9697 => Opcode::VFMADD231PHZ128mkz, + 9698 => Opcode::VFMADD231PHZ128r, + 9699 => Opcode::VFMADD231PHZ128rk, + 9700 => Opcode::VFMADD231PHZ128rkz, + 9701 => Opcode::VFMADD231PHZ256m, + 9702 => Opcode::VFMADD231PHZ256mb, + 9703 => Opcode::VFMADD231PHZ256mbk, + 9704 => Opcode::VFMADD231PHZ256mbkz, + 9705 => Opcode::VFMADD231PHZ256mk, + 9706 => Opcode::VFMADD231PHZ256mkz, + 9707 => Opcode::VFMADD231PHZ256r, + 9708 => Opcode::VFMADD231PHZ256rk, + 9709 => Opcode::VFMADD231PHZ256rkz, + 9710 => Opcode::VFMADD231PHZm, + 9711 => Opcode::VFMADD231PHZmb, + 9712 => Opcode::VFMADD231PHZmbk, + 9713 => Opcode::VFMADD231PHZmbkz, + 9714 => Opcode::VFMADD231PHZmk, + 9715 => Opcode::VFMADD231PHZmkz, + 9716 => Opcode::VFMADD231PHZr, + 9717 => Opcode::VFMADD231PHZrb, + 9718 => Opcode::VFMADD231PHZrbk, + 9719 => Opcode::VFMADD231PHZrbkz, + 9720 => Opcode::VFMADD231PHZrk, + 9721 => Opcode::VFMADD231PHZrkz, + 9722 => Opcode::VFMADD231PSYm, + 9723 => Opcode::VFMADD231PSYr, + 9724 => Opcode::VFMADD231PSZ128m, + 9725 => Opcode::VFMADD231PSZ128mb, + 9726 => Opcode::VFMADD231PSZ128mbk, + 9727 => Opcode::VFMADD231PSZ128mbkz, + 9728 => Opcode::VFMADD231PSZ128mk, + 9729 => Opcode::VFMADD231PSZ128mkz, + 9730 => Opcode::VFMADD231PSZ128r, + 9731 => Opcode::VFMADD231PSZ128rk, + 9732 => Opcode::VFMADD231PSZ128rkz, + 9733 => Opcode::VFMADD231PSZ256m, + 9734 => Opcode::VFMADD231PSZ256mb, + 9735 => Opcode::VFMADD231PSZ256mbk, + 9736 => Opcode::VFMADD231PSZ256mbkz, + 9737 => Opcode::VFMADD231PSZ256mk, + 9738 => Opcode::VFMADD231PSZ256mkz, + 9739 => Opcode::VFMADD231PSZ256r, + 9740 => Opcode::VFMADD231PSZ256rk, + 9741 => Opcode::VFMADD231PSZ256rkz, + 9742 => Opcode::VFMADD231PSZm, + 9743 => Opcode::VFMADD231PSZmb, + 9744 => Opcode::VFMADD231PSZmbk, + 9745 => Opcode::VFMADD231PSZmbkz, + 9746 => Opcode::VFMADD231PSZmk, + 9747 => Opcode::VFMADD231PSZmkz, + 9748 => Opcode::VFMADD231PSZr, + 9749 => Opcode::VFMADD231PSZrb, + 9750 => Opcode::VFMADD231PSZrbk, + 9751 => Opcode::VFMADD231PSZrbkz, + 9752 => Opcode::VFMADD231PSZrk, + 9753 => Opcode::VFMADD231PSZrkz, + 9754 => Opcode::VFMADD231PSm, + 9755 => Opcode::VFMADD231PSr, + 9756 => Opcode::VFMADD231SDZm, + 9757 => Opcode::VFMADD231SDZm_Int, + 9758 => Opcode::VFMADD231SDZmk_Int, + 9759 => Opcode::VFMADD231SDZmkz_Int, + 9760 => Opcode::VFMADD231SDZr, + 9761 => Opcode::VFMADD231SDZr_Int, + 9762 => Opcode::VFMADD231SDZrb, + 9763 => Opcode::VFMADD231SDZrb_Int, + 9764 => Opcode::VFMADD231SDZrbk_Int, + 9765 => Opcode::VFMADD231SDZrbkz_Int, + 9766 => Opcode::VFMADD231SDZrk_Int, + 9767 => Opcode::VFMADD231SDZrkz_Int, + 9768 => Opcode::VFMADD231SDm, + 9769 => Opcode::VFMADD231SDm_Int, + 9770 => Opcode::VFMADD231SDr, + 9771 => Opcode::VFMADD231SDr_Int, + 9772 => Opcode::VFMADD231SHZm, + 9773 => Opcode::VFMADD231SHZm_Int, + 9774 => Opcode::VFMADD231SHZmk_Int, + 9775 => Opcode::VFMADD231SHZmkz_Int, + 9776 => Opcode::VFMADD231SHZr, + 9777 => Opcode::VFMADD231SHZr_Int, + 9778 => Opcode::VFMADD231SHZrb, + 9779 => Opcode::VFMADD231SHZrb_Int, + 9780 => Opcode::VFMADD231SHZrbk_Int, + 9781 => Opcode::VFMADD231SHZrbkz_Int, + 9782 => Opcode::VFMADD231SHZrk_Int, + 9783 => Opcode::VFMADD231SHZrkz_Int, + 9784 => Opcode::VFMADD231SSZm, + 9785 => Opcode::VFMADD231SSZm_Int, + 9786 => Opcode::VFMADD231SSZmk_Int, + 9787 => Opcode::VFMADD231SSZmkz_Int, + 9788 => Opcode::VFMADD231SSZr, + 9789 => Opcode::VFMADD231SSZr_Int, + 9790 => Opcode::VFMADD231SSZrb, + 9791 => Opcode::VFMADD231SSZrb_Int, + 9792 => Opcode::VFMADD231SSZrbk_Int, + 9793 => Opcode::VFMADD231SSZrbkz_Int, + 9794 => Opcode::VFMADD231SSZrk_Int, + 9795 => Opcode::VFMADD231SSZrkz_Int, + 9796 => Opcode::VFMADD231SSm, + 9797 => Opcode::VFMADD231SSm_Int, + 9798 => Opcode::VFMADD231SSr, + 9799 => Opcode::VFMADD231SSr_Int, + 9800 => Opcode::VFMADDCPHZ128m, + 9801 => Opcode::VFMADDCPHZ128mb, + 9802 => Opcode::VFMADDCPHZ128mbk, + 9803 => Opcode::VFMADDCPHZ128mbkz, + 9804 => Opcode::VFMADDCPHZ128mk, + 9805 => Opcode::VFMADDCPHZ128mkz, + 9806 => Opcode::VFMADDCPHZ128r, + 9807 => Opcode::VFMADDCPHZ128rk, + 9808 => Opcode::VFMADDCPHZ128rkz, + 9809 => Opcode::VFMADDCPHZ256m, + 9810 => Opcode::VFMADDCPHZ256mb, + 9811 => Opcode::VFMADDCPHZ256mbk, + 9812 => Opcode::VFMADDCPHZ256mbkz, + 9813 => Opcode::VFMADDCPHZ256mk, + 9814 => Opcode::VFMADDCPHZ256mkz, + 9815 => Opcode::VFMADDCPHZ256r, + 9816 => Opcode::VFMADDCPHZ256rk, + 9817 => Opcode::VFMADDCPHZ256rkz, + 9818 => Opcode::VFMADDCPHZm, + 9819 => Opcode::VFMADDCPHZmb, + 9820 => Opcode::VFMADDCPHZmbk, + 9821 => Opcode::VFMADDCPHZmbkz, + 9822 => Opcode::VFMADDCPHZmk, + 9823 => Opcode::VFMADDCPHZmkz, + 9824 => Opcode::VFMADDCPHZr, + 9825 => Opcode::VFMADDCPHZrb, + 9826 => Opcode::VFMADDCPHZrbk, + 9827 => Opcode::VFMADDCPHZrbkz, + 9828 => Opcode::VFMADDCPHZrk, + 9829 => Opcode::VFMADDCPHZrkz, + 9830 => Opcode::VFMADDCSHZm, + 9831 => Opcode::VFMADDCSHZmk, + 9832 => Opcode::VFMADDCSHZmkz, + 9833 => Opcode::VFMADDCSHZr, + 9834 => Opcode::VFMADDCSHZrb, + 9835 => Opcode::VFMADDCSHZrbk, + 9836 => Opcode::VFMADDCSHZrbkz, + 9837 => Opcode::VFMADDCSHZrk, + 9838 => Opcode::VFMADDCSHZrkz, + 9839 => Opcode::VFMADDPD4Ymr, + 9840 => Opcode::VFMADDPD4Yrm, + 9841 => Opcode::VFMADDPD4Yrr, + 9842 => Opcode::VFMADDPD4Yrr_REV, + 9843 => Opcode::VFMADDPD4mr, + 9844 => Opcode::VFMADDPD4rm, + 9845 => Opcode::VFMADDPD4rr, + 9846 => Opcode::VFMADDPD4rr_REV, + 9847 => Opcode::VFMADDPS4Ymr, + 9848 => Opcode::VFMADDPS4Yrm, + 9849 => Opcode::VFMADDPS4Yrr, + 9850 => Opcode::VFMADDPS4Yrr_REV, + 9851 => Opcode::VFMADDPS4mr, + 9852 => Opcode::VFMADDPS4rm, + 9853 => Opcode::VFMADDPS4rr, + 9854 => Opcode::VFMADDPS4rr_REV, + 9855 => Opcode::VFMADDSD4mr, + 9856 => Opcode::VFMADDSD4mr_Int, + 9857 => Opcode::VFMADDSD4rm, + 9858 => Opcode::VFMADDSD4rm_Int, + 9859 => Opcode::VFMADDSD4rr, + 9860 => Opcode::VFMADDSD4rr_Int, + 9861 => Opcode::VFMADDSD4rr_Int_REV, + 9862 => Opcode::VFMADDSD4rr_REV, + 9863 => Opcode::VFMADDSS4mr, + 9864 => Opcode::VFMADDSS4mr_Int, + 9865 => Opcode::VFMADDSS4rm, + 9866 => Opcode::VFMADDSS4rm_Int, + 9867 => Opcode::VFMADDSS4rr, + 9868 => Opcode::VFMADDSS4rr_Int, + 9869 => Opcode::VFMADDSS4rr_Int_REV, + 9870 => Opcode::VFMADDSS4rr_REV, + 9871 => Opcode::VFMADDSUB132PDYm, + 9872 => Opcode::VFMADDSUB132PDYr, + 9873 => Opcode::VFMADDSUB132PDZ128m, + 9874 => Opcode::VFMADDSUB132PDZ128mb, + 9875 => Opcode::VFMADDSUB132PDZ128mbk, + 9876 => Opcode::VFMADDSUB132PDZ128mbkz, + 9877 => Opcode::VFMADDSUB132PDZ128mk, + 9878 => Opcode::VFMADDSUB132PDZ128mkz, + 9879 => Opcode::VFMADDSUB132PDZ128r, + 9880 => Opcode::VFMADDSUB132PDZ128rk, + 9881 => Opcode::VFMADDSUB132PDZ128rkz, + 9882 => Opcode::VFMADDSUB132PDZ256m, + 9883 => Opcode::VFMADDSUB132PDZ256mb, + 9884 => Opcode::VFMADDSUB132PDZ256mbk, + 9885 => Opcode::VFMADDSUB132PDZ256mbkz, + 9886 => Opcode::VFMADDSUB132PDZ256mk, + 9887 => Opcode::VFMADDSUB132PDZ256mkz, + 9888 => Opcode::VFMADDSUB132PDZ256r, + 9889 => Opcode::VFMADDSUB132PDZ256rk, + 9890 => Opcode::VFMADDSUB132PDZ256rkz, + 9891 => Opcode::VFMADDSUB132PDZm, + 9892 => Opcode::VFMADDSUB132PDZmb, + 9893 => Opcode::VFMADDSUB132PDZmbk, + 9894 => Opcode::VFMADDSUB132PDZmbkz, + 9895 => Opcode::VFMADDSUB132PDZmk, + 9896 => Opcode::VFMADDSUB132PDZmkz, + 9897 => Opcode::VFMADDSUB132PDZr, + 9898 => Opcode::VFMADDSUB132PDZrb, + 9899 => Opcode::VFMADDSUB132PDZrbk, + 9900 => Opcode::VFMADDSUB132PDZrbkz, + 9901 => Opcode::VFMADDSUB132PDZrk, + 9902 => Opcode::VFMADDSUB132PDZrkz, + 9903 => Opcode::VFMADDSUB132PDm, + 9904 => Opcode::VFMADDSUB132PDr, + 9905 => Opcode::VFMADDSUB132PHZ128m, + 9906 => Opcode::VFMADDSUB132PHZ128mb, + 9907 => Opcode::VFMADDSUB132PHZ128mbk, + 9908 => Opcode::VFMADDSUB132PHZ128mbkz, + 9909 => Opcode::VFMADDSUB132PHZ128mk, + 9910 => Opcode::VFMADDSUB132PHZ128mkz, + 9911 => Opcode::VFMADDSUB132PHZ128r, + 9912 => Opcode::VFMADDSUB132PHZ128rk, + 9913 => Opcode::VFMADDSUB132PHZ128rkz, + 9914 => Opcode::VFMADDSUB132PHZ256m, + 9915 => Opcode::VFMADDSUB132PHZ256mb, + 9916 => Opcode::VFMADDSUB132PHZ256mbk, + 9917 => Opcode::VFMADDSUB132PHZ256mbkz, + 9918 => Opcode::VFMADDSUB132PHZ256mk, + 9919 => Opcode::VFMADDSUB132PHZ256mkz, + 9920 => Opcode::VFMADDSUB132PHZ256r, + 9921 => Opcode::VFMADDSUB132PHZ256rk, + 9922 => Opcode::VFMADDSUB132PHZ256rkz, + 9923 => Opcode::VFMADDSUB132PHZm, + 9924 => Opcode::VFMADDSUB132PHZmb, + 9925 => Opcode::VFMADDSUB132PHZmbk, + 9926 => Opcode::VFMADDSUB132PHZmbkz, + 9927 => Opcode::VFMADDSUB132PHZmk, + 9928 => Opcode::VFMADDSUB132PHZmkz, + 9929 => Opcode::VFMADDSUB132PHZr, + 9930 => Opcode::VFMADDSUB132PHZrb, + 9931 => Opcode::VFMADDSUB132PHZrbk, + 9932 => Opcode::VFMADDSUB132PHZrbkz, + 9933 => Opcode::VFMADDSUB132PHZrk, + 9934 => Opcode::VFMADDSUB132PHZrkz, + 9935 => Opcode::VFMADDSUB132PSYm, + 9936 => Opcode::VFMADDSUB132PSYr, + 9937 => Opcode::VFMADDSUB132PSZ128m, + 9938 => Opcode::VFMADDSUB132PSZ128mb, + 9939 => Opcode::VFMADDSUB132PSZ128mbk, + 9940 => Opcode::VFMADDSUB132PSZ128mbkz, + 9941 => Opcode::VFMADDSUB132PSZ128mk, + 9942 => Opcode::VFMADDSUB132PSZ128mkz, + 9943 => Opcode::VFMADDSUB132PSZ128r, + 9944 => Opcode::VFMADDSUB132PSZ128rk, + 9945 => Opcode::VFMADDSUB132PSZ128rkz, + 9946 => Opcode::VFMADDSUB132PSZ256m, + 9947 => Opcode::VFMADDSUB132PSZ256mb, + 9948 => Opcode::VFMADDSUB132PSZ256mbk, + 9949 => Opcode::VFMADDSUB132PSZ256mbkz, + 9950 => Opcode::VFMADDSUB132PSZ256mk, + 9951 => Opcode::VFMADDSUB132PSZ256mkz, + 9952 => Opcode::VFMADDSUB132PSZ256r, + 9953 => Opcode::VFMADDSUB132PSZ256rk, + 9954 => Opcode::VFMADDSUB132PSZ256rkz, + 9955 => Opcode::VFMADDSUB132PSZm, + 9956 => Opcode::VFMADDSUB132PSZmb, + 9957 => Opcode::VFMADDSUB132PSZmbk, + 9958 => Opcode::VFMADDSUB132PSZmbkz, + 9959 => Opcode::VFMADDSUB132PSZmk, + 9960 => Opcode::VFMADDSUB132PSZmkz, + 9961 => Opcode::VFMADDSUB132PSZr, + 9962 => Opcode::VFMADDSUB132PSZrb, + 9963 => Opcode::VFMADDSUB132PSZrbk, + 9964 => Opcode::VFMADDSUB132PSZrbkz, + 9965 => Opcode::VFMADDSUB132PSZrk, + 9966 => Opcode::VFMADDSUB132PSZrkz, + 9967 => Opcode::VFMADDSUB132PSm, + 9968 => Opcode::VFMADDSUB132PSr, + 9969 => Opcode::VFMADDSUB213PDYm, + 9970 => Opcode::VFMADDSUB213PDYr, + 9971 => Opcode::VFMADDSUB213PDZ128m, + 9972 => Opcode::VFMADDSUB213PDZ128mb, + 9973 => Opcode::VFMADDSUB213PDZ128mbk, + 9974 => Opcode::VFMADDSUB213PDZ128mbkz, + 9975 => Opcode::VFMADDSUB213PDZ128mk, + 9976 => Opcode::VFMADDSUB213PDZ128mkz, + 9977 => Opcode::VFMADDSUB213PDZ128r, + 9978 => Opcode::VFMADDSUB213PDZ128rk, + 9979 => Opcode::VFMADDSUB213PDZ128rkz, + 9980 => Opcode::VFMADDSUB213PDZ256m, + 9981 => Opcode::VFMADDSUB213PDZ256mb, + 9982 => Opcode::VFMADDSUB213PDZ256mbk, + 9983 => Opcode::VFMADDSUB213PDZ256mbkz, + 9984 => Opcode::VFMADDSUB213PDZ256mk, + 9985 => Opcode::VFMADDSUB213PDZ256mkz, + 9986 => Opcode::VFMADDSUB213PDZ256r, + 9987 => Opcode::VFMADDSUB213PDZ256rk, + 9988 => Opcode::VFMADDSUB213PDZ256rkz, + 9989 => Opcode::VFMADDSUB213PDZm, + 9990 => Opcode::VFMADDSUB213PDZmb, + 9991 => Opcode::VFMADDSUB213PDZmbk, + 9992 => Opcode::VFMADDSUB213PDZmbkz, + 9993 => Opcode::VFMADDSUB213PDZmk, + 9994 => Opcode::VFMADDSUB213PDZmkz, + 9995 => Opcode::VFMADDSUB213PDZr, + 9996 => Opcode::VFMADDSUB213PDZrb, + 9997 => Opcode::VFMADDSUB213PDZrbk, + 9998 => Opcode::VFMADDSUB213PDZrbkz, + 9999 => Opcode::VFMADDSUB213PDZrk, + 10000 => Opcode::VFMADDSUB213PDZrkz, + 10001 => Opcode::VFMADDSUB213PDm, + 10002 => Opcode::VFMADDSUB213PDr, + 10003 => Opcode::VFMADDSUB213PHZ128m, + 10004 => Opcode::VFMADDSUB213PHZ128mb, + 10005 => Opcode::VFMADDSUB213PHZ128mbk, + 10006 => Opcode::VFMADDSUB213PHZ128mbkz, + 10007 => Opcode::VFMADDSUB213PHZ128mk, + 10008 => Opcode::VFMADDSUB213PHZ128mkz, + 10009 => Opcode::VFMADDSUB213PHZ128r, + 10010 => Opcode::VFMADDSUB213PHZ128rk, + 10011 => Opcode::VFMADDSUB213PHZ128rkz, + 10012 => Opcode::VFMADDSUB213PHZ256m, + 10013 => Opcode::VFMADDSUB213PHZ256mb, + 10014 => Opcode::VFMADDSUB213PHZ256mbk, + 10015 => Opcode::VFMADDSUB213PHZ256mbkz, + 10016 => Opcode::VFMADDSUB213PHZ256mk, + 10017 => Opcode::VFMADDSUB213PHZ256mkz, + 10018 => Opcode::VFMADDSUB213PHZ256r, + 10019 => Opcode::VFMADDSUB213PHZ256rk, + 10020 => Opcode::VFMADDSUB213PHZ256rkz, + 10021 => Opcode::VFMADDSUB213PHZm, + 10022 => Opcode::VFMADDSUB213PHZmb, + 10023 => Opcode::VFMADDSUB213PHZmbk, + 10024 => Opcode::VFMADDSUB213PHZmbkz, + 10025 => Opcode::VFMADDSUB213PHZmk, + 10026 => Opcode::VFMADDSUB213PHZmkz, + 10027 => Opcode::VFMADDSUB213PHZr, + 10028 => Opcode::VFMADDSUB213PHZrb, + 10029 => Opcode::VFMADDSUB213PHZrbk, + 10030 => Opcode::VFMADDSUB213PHZrbkz, + 10031 => Opcode::VFMADDSUB213PHZrk, + 10032 => Opcode::VFMADDSUB213PHZrkz, + 10033 => Opcode::VFMADDSUB213PSYm, + 10034 => Opcode::VFMADDSUB213PSYr, + 10035 => Opcode::VFMADDSUB213PSZ128m, + 10036 => Opcode::VFMADDSUB213PSZ128mb, + 10037 => Opcode::VFMADDSUB213PSZ128mbk, + 10038 => Opcode::VFMADDSUB213PSZ128mbkz, + 10039 => Opcode::VFMADDSUB213PSZ128mk, + 10040 => Opcode::VFMADDSUB213PSZ128mkz, + 10041 => Opcode::VFMADDSUB213PSZ128r, + 10042 => Opcode::VFMADDSUB213PSZ128rk, + 10043 => Opcode::VFMADDSUB213PSZ128rkz, + 10044 => Opcode::VFMADDSUB213PSZ256m, + 10045 => Opcode::VFMADDSUB213PSZ256mb, + 10046 => Opcode::VFMADDSUB213PSZ256mbk, + 10047 => Opcode::VFMADDSUB213PSZ256mbkz, + 10048 => Opcode::VFMADDSUB213PSZ256mk, + 10049 => Opcode::VFMADDSUB213PSZ256mkz, + 10050 => Opcode::VFMADDSUB213PSZ256r, + 10051 => Opcode::VFMADDSUB213PSZ256rk, + 10052 => Opcode::VFMADDSUB213PSZ256rkz, + 10053 => Opcode::VFMADDSUB213PSZm, + 10054 => Opcode::VFMADDSUB213PSZmb, + 10055 => Opcode::VFMADDSUB213PSZmbk, + 10056 => Opcode::VFMADDSUB213PSZmbkz, + 10057 => Opcode::VFMADDSUB213PSZmk, + 10058 => Opcode::VFMADDSUB213PSZmkz, + 10059 => Opcode::VFMADDSUB213PSZr, + 10060 => Opcode::VFMADDSUB213PSZrb, + 10061 => Opcode::VFMADDSUB213PSZrbk, + 10062 => Opcode::VFMADDSUB213PSZrbkz, + 10063 => Opcode::VFMADDSUB213PSZrk, + 10064 => Opcode::VFMADDSUB213PSZrkz, + 10065 => Opcode::VFMADDSUB213PSm, + 10066 => Opcode::VFMADDSUB213PSr, + 10067 => Opcode::VFMADDSUB231PDYm, + 10068 => Opcode::VFMADDSUB231PDYr, + 10069 => Opcode::VFMADDSUB231PDZ128m, + 10070 => Opcode::VFMADDSUB231PDZ128mb, + 10071 => Opcode::VFMADDSUB231PDZ128mbk, + 10072 => Opcode::VFMADDSUB231PDZ128mbkz, + 10073 => Opcode::VFMADDSUB231PDZ128mk, + 10074 => Opcode::VFMADDSUB231PDZ128mkz, + 10075 => Opcode::VFMADDSUB231PDZ128r, + 10076 => Opcode::VFMADDSUB231PDZ128rk, + 10077 => Opcode::VFMADDSUB231PDZ128rkz, + 10078 => Opcode::VFMADDSUB231PDZ256m, + 10079 => Opcode::VFMADDSUB231PDZ256mb, + 10080 => Opcode::VFMADDSUB231PDZ256mbk, + 10081 => Opcode::VFMADDSUB231PDZ256mbkz, + 10082 => Opcode::VFMADDSUB231PDZ256mk, + 10083 => Opcode::VFMADDSUB231PDZ256mkz, + 10084 => Opcode::VFMADDSUB231PDZ256r, + 10085 => Opcode::VFMADDSUB231PDZ256rk, + 10086 => Opcode::VFMADDSUB231PDZ256rkz, + 10087 => Opcode::VFMADDSUB231PDZm, + 10088 => Opcode::VFMADDSUB231PDZmb, + 10089 => Opcode::VFMADDSUB231PDZmbk, + 10090 => Opcode::VFMADDSUB231PDZmbkz, + 10091 => Opcode::VFMADDSUB231PDZmk, + 10092 => Opcode::VFMADDSUB231PDZmkz, + 10093 => Opcode::VFMADDSUB231PDZr, + 10094 => Opcode::VFMADDSUB231PDZrb, + 10095 => Opcode::VFMADDSUB231PDZrbk, + 10096 => Opcode::VFMADDSUB231PDZrbkz, + 10097 => Opcode::VFMADDSUB231PDZrk, + 10098 => Opcode::VFMADDSUB231PDZrkz, + 10099 => Opcode::VFMADDSUB231PDm, + 10100 => Opcode::VFMADDSUB231PDr, + 10101 => Opcode::VFMADDSUB231PHZ128m, + 10102 => Opcode::VFMADDSUB231PHZ128mb, + 10103 => Opcode::VFMADDSUB231PHZ128mbk, + 10104 => Opcode::VFMADDSUB231PHZ128mbkz, + 10105 => Opcode::VFMADDSUB231PHZ128mk, + 10106 => Opcode::VFMADDSUB231PHZ128mkz, + 10107 => Opcode::VFMADDSUB231PHZ128r, + 10108 => Opcode::VFMADDSUB231PHZ128rk, + 10109 => Opcode::VFMADDSUB231PHZ128rkz, + 10110 => Opcode::VFMADDSUB231PHZ256m, + 10111 => Opcode::VFMADDSUB231PHZ256mb, + 10112 => Opcode::VFMADDSUB231PHZ256mbk, + 10113 => Opcode::VFMADDSUB231PHZ256mbkz, + 10114 => Opcode::VFMADDSUB231PHZ256mk, + 10115 => Opcode::VFMADDSUB231PHZ256mkz, + 10116 => Opcode::VFMADDSUB231PHZ256r, + 10117 => Opcode::VFMADDSUB231PHZ256rk, + 10118 => Opcode::VFMADDSUB231PHZ256rkz, + 10119 => Opcode::VFMADDSUB231PHZm, + 10120 => Opcode::VFMADDSUB231PHZmb, + 10121 => Opcode::VFMADDSUB231PHZmbk, + 10122 => Opcode::VFMADDSUB231PHZmbkz, + 10123 => Opcode::VFMADDSUB231PHZmk, + 10124 => Opcode::VFMADDSUB231PHZmkz, + 10125 => Opcode::VFMADDSUB231PHZr, + 10126 => Opcode::VFMADDSUB231PHZrb, + 10127 => Opcode::VFMADDSUB231PHZrbk, + 10128 => Opcode::VFMADDSUB231PHZrbkz, + 10129 => Opcode::VFMADDSUB231PHZrk, + 10130 => Opcode::VFMADDSUB231PHZrkz, + 10131 => Opcode::VFMADDSUB231PSYm, + 10132 => Opcode::VFMADDSUB231PSYr, + 10133 => Opcode::VFMADDSUB231PSZ128m, + 10134 => Opcode::VFMADDSUB231PSZ128mb, + 10135 => Opcode::VFMADDSUB231PSZ128mbk, + 10136 => Opcode::VFMADDSUB231PSZ128mbkz, + 10137 => Opcode::VFMADDSUB231PSZ128mk, + 10138 => Opcode::VFMADDSUB231PSZ128mkz, + 10139 => Opcode::VFMADDSUB231PSZ128r, + 10140 => Opcode::VFMADDSUB231PSZ128rk, + 10141 => Opcode::VFMADDSUB231PSZ128rkz, + 10142 => Opcode::VFMADDSUB231PSZ256m, + 10143 => Opcode::VFMADDSUB231PSZ256mb, + 10144 => Opcode::VFMADDSUB231PSZ256mbk, + 10145 => Opcode::VFMADDSUB231PSZ256mbkz, + 10146 => Opcode::VFMADDSUB231PSZ256mk, + 10147 => Opcode::VFMADDSUB231PSZ256mkz, + 10148 => Opcode::VFMADDSUB231PSZ256r, + 10149 => Opcode::VFMADDSUB231PSZ256rk, + 10150 => Opcode::VFMADDSUB231PSZ256rkz, + 10151 => Opcode::VFMADDSUB231PSZm, + 10152 => Opcode::VFMADDSUB231PSZmb, + 10153 => Opcode::VFMADDSUB231PSZmbk, + 10154 => Opcode::VFMADDSUB231PSZmbkz, + 10155 => Opcode::VFMADDSUB231PSZmk, + 10156 => Opcode::VFMADDSUB231PSZmkz, + 10157 => Opcode::VFMADDSUB231PSZr, + 10158 => Opcode::VFMADDSUB231PSZrb, + 10159 => Opcode::VFMADDSUB231PSZrbk, + 10160 => Opcode::VFMADDSUB231PSZrbkz, + 10161 => Opcode::VFMADDSUB231PSZrk, + 10162 => Opcode::VFMADDSUB231PSZrkz, + 10163 => Opcode::VFMADDSUB231PSm, + 10164 => Opcode::VFMADDSUB231PSr, + 10165 => Opcode::VFMADDSUBPD4Ymr, + 10166 => Opcode::VFMADDSUBPD4Yrm, + 10167 => Opcode::VFMADDSUBPD4Yrr, + 10168 => Opcode::VFMADDSUBPD4Yrr_REV, + 10169 => Opcode::VFMADDSUBPD4mr, + 10170 => Opcode::VFMADDSUBPD4rm, + 10171 => Opcode::VFMADDSUBPD4rr, + 10172 => Opcode::VFMADDSUBPD4rr_REV, + 10173 => Opcode::VFMADDSUBPS4Ymr, + 10174 => Opcode::VFMADDSUBPS4Yrm, + 10175 => Opcode::VFMADDSUBPS4Yrr, + 10176 => Opcode::VFMADDSUBPS4Yrr_REV, + 10177 => Opcode::VFMADDSUBPS4mr, + 10178 => Opcode::VFMADDSUBPS4rm, + 10179 => Opcode::VFMADDSUBPS4rr, + 10180 => Opcode::VFMADDSUBPS4rr_REV, + 10181 => Opcode::VFMSUB132BF16Z128m, + 10182 => Opcode::VFMSUB132BF16Z128mb, + 10183 => Opcode::VFMSUB132BF16Z128mbk, + 10184 => Opcode::VFMSUB132BF16Z128mbkz, + 10185 => Opcode::VFMSUB132BF16Z128mk, + 10186 => Opcode::VFMSUB132BF16Z128mkz, + 10187 => Opcode::VFMSUB132BF16Z128r, + 10188 => Opcode::VFMSUB132BF16Z128rk, + 10189 => Opcode::VFMSUB132BF16Z128rkz, + 10190 => Opcode::VFMSUB132BF16Z256m, + 10191 => Opcode::VFMSUB132BF16Z256mb, + 10192 => Opcode::VFMSUB132BF16Z256mbk, + 10193 => Opcode::VFMSUB132BF16Z256mbkz, + 10194 => Opcode::VFMSUB132BF16Z256mk, + 10195 => Opcode::VFMSUB132BF16Z256mkz, + 10196 => Opcode::VFMSUB132BF16Z256r, + 10197 => Opcode::VFMSUB132BF16Z256rk, + 10198 => Opcode::VFMSUB132BF16Z256rkz, + 10199 => Opcode::VFMSUB132BF16Zm, + 10200 => Opcode::VFMSUB132BF16Zmb, + 10201 => Opcode::VFMSUB132BF16Zmbk, + 10202 => Opcode::VFMSUB132BF16Zmbkz, + 10203 => Opcode::VFMSUB132BF16Zmk, + 10204 => Opcode::VFMSUB132BF16Zmkz, + 10205 => Opcode::VFMSUB132BF16Zr, + 10206 => Opcode::VFMSUB132BF16Zrk, + 10207 => Opcode::VFMSUB132BF16Zrkz, + 10208 => Opcode::VFMSUB132PDYm, + 10209 => Opcode::VFMSUB132PDYr, + 10210 => Opcode::VFMSUB132PDZ128m, + 10211 => Opcode::VFMSUB132PDZ128mb, + 10212 => Opcode::VFMSUB132PDZ128mbk, + 10213 => Opcode::VFMSUB132PDZ128mbkz, + 10214 => Opcode::VFMSUB132PDZ128mk, + 10215 => Opcode::VFMSUB132PDZ128mkz, + 10216 => Opcode::VFMSUB132PDZ128r, + 10217 => Opcode::VFMSUB132PDZ128rk, + 10218 => Opcode::VFMSUB132PDZ128rkz, + 10219 => Opcode::VFMSUB132PDZ256m, + 10220 => Opcode::VFMSUB132PDZ256mb, + 10221 => Opcode::VFMSUB132PDZ256mbk, + 10222 => Opcode::VFMSUB132PDZ256mbkz, + 10223 => Opcode::VFMSUB132PDZ256mk, + 10224 => Opcode::VFMSUB132PDZ256mkz, + 10225 => Opcode::VFMSUB132PDZ256r, + 10226 => Opcode::VFMSUB132PDZ256rk, + 10227 => Opcode::VFMSUB132PDZ256rkz, + 10228 => Opcode::VFMSUB132PDZm, + 10229 => Opcode::VFMSUB132PDZmb, + 10230 => Opcode::VFMSUB132PDZmbk, + 10231 => Opcode::VFMSUB132PDZmbkz, + 10232 => Opcode::VFMSUB132PDZmk, + 10233 => Opcode::VFMSUB132PDZmkz, + 10234 => Opcode::VFMSUB132PDZr, + 10235 => Opcode::VFMSUB132PDZrb, + 10236 => Opcode::VFMSUB132PDZrbk, + 10237 => Opcode::VFMSUB132PDZrbkz, + 10238 => Opcode::VFMSUB132PDZrk, + 10239 => Opcode::VFMSUB132PDZrkz, + 10240 => Opcode::VFMSUB132PDm, + 10241 => Opcode::VFMSUB132PDr, + 10242 => Opcode::VFMSUB132PHZ128m, + 10243 => Opcode::VFMSUB132PHZ128mb, + 10244 => Opcode::VFMSUB132PHZ128mbk, + 10245 => Opcode::VFMSUB132PHZ128mbkz, + 10246 => Opcode::VFMSUB132PHZ128mk, + 10247 => Opcode::VFMSUB132PHZ128mkz, + 10248 => Opcode::VFMSUB132PHZ128r, + 10249 => Opcode::VFMSUB132PHZ128rk, + 10250 => Opcode::VFMSUB132PHZ128rkz, + 10251 => Opcode::VFMSUB132PHZ256m, + 10252 => Opcode::VFMSUB132PHZ256mb, + 10253 => Opcode::VFMSUB132PHZ256mbk, + 10254 => Opcode::VFMSUB132PHZ256mbkz, + 10255 => Opcode::VFMSUB132PHZ256mk, + 10256 => Opcode::VFMSUB132PHZ256mkz, + 10257 => Opcode::VFMSUB132PHZ256r, + 10258 => Opcode::VFMSUB132PHZ256rk, + 10259 => Opcode::VFMSUB132PHZ256rkz, + 10260 => Opcode::VFMSUB132PHZm, + 10261 => Opcode::VFMSUB132PHZmb, + 10262 => Opcode::VFMSUB132PHZmbk, + 10263 => Opcode::VFMSUB132PHZmbkz, + 10264 => Opcode::VFMSUB132PHZmk, + 10265 => Opcode::VFMSUB132PHZmkz, + 10266 => Opcode::VFMSUB132PHZr, + 10267 => Opcode::VFMSUB132PHZrb, + 10268 => Opcode::VFMSUB132PHZrbk, + 10269 => Opcode::VFMSUB132PHZrbkz, + 10270 => Opcode::VFMSUB132PHZrk, + 10271 => Opcode::VFMSUB132PHZrkz, + 10272 => Opcode::VFMSUB132PSYm, + 10273 => Opcode::VFMSUB132PSYr, + 10274 => Opcode::VFMSUB132PSZ128m, + 10275 => Opcode::VFMSUB132PSZ128mb, + 10276 => Opcode::VFMSUB132PSZ128mbk, + 10277 => Opcode::VFMSUB132PSZ128mbkz, + 10278 => Opcode::VFMSUB132PSZ128mk, + 10279 => Opcode::VFMSUB132PSZ128mkz, + 10280 => Opcode::VFMSUB132PSZ128r, + 10281 => Opcode::VFMSUB132PSZ128rk, + 10282 => Opcode::VFMSUB132PSZ128rkz, + 10283 => Opcode::VFMSUB132PSZ256m, + 10284 => Opcode::VFMSUB132PSZ256mb, + 10285 => Opcode::VFMSUB132PSZ256mbk, + 10286 => Opcode::VFMSUB132PSZ256mbkz, + 10287 => Opcode::VFMSUB132PSZ256mk, + 10288 => Opcode::VFMSUB132PSZ256mkz, + 10289 => Opcode::VFMSUB132PSZ256r, + 10290 => Opcode::VFMSUB132PSZ256rk, + 10291 => Opcode::VFMSUB132PSZ256rkz, + 10292 => Opcode::VFMSUB132PSZm, + 10293 => Opcode::VFMSUB132PSZmb, + 10294 => Opcode::VFMSUB132PSZmbk, + 10295 => Opcode::VFMSUB132PSZmbkz, + 10296 => Opcode::VFMSUB132PSZmk, + 10297 => Opcode::VFMSUB132PSZmkz, + 10298 => Opcode::VFMSUB132PSZr, + 10299 => Opcode::VFMSUB132PSZrb, + 10300 => Opcode::VFMSUB132PSZrbk, + 10301 => Opcode::VFMSUB132PSZrbkz, + 10302 => Opcode::VFMSUB132PSZrk, + 10303 => Opcode::VFMSUB132PSZrkz, + 10304 => Opcode::VFMSUB132PSm, + 10305 => Opcode::VFMSUB132PSr, + 10306 => Opcode::VFMSUB132SDZm, + 10307 => Opcode::VFMSUB132SDZm_Int, + 10308 => Opcode::VFMSUB132SDZmk_Int, + 10309 => Opcode::VFMSUB132SDZmkz_Int, + 10310 => Opcode::VFMSUB132SDZr, + 10311 => Opcode::VFMSUB132SDZr_Int, + 10312 => Opcode::VFMSUB132SDZrb, + 10313 => Opcode::VFMSUB132SDZrb_Int, + 10314 => Opcode::VFMSUB132SDZrbk_Int, + 10315 => Opcode::VFMSUB132SDZrbkz_Int, + 10316 => Opcode::VFMSUB132SDZrk_Int, + 10317 => Opcode::VFMSUB132SDZrkz_Int, + 10318 => Opcode::VFMSUB132SDm, + 10319 => Opcode::VFMSUB132SDm_Int, + 10320 => Opcode::VFMSUB132SDr, + 10321 => Opcode::VFMSUB132SDr_Int, + 10322 => Opcode::VFMSUB132SHZm, + 10323 => Opcode::VFMSUB132SHZm_Int, + 10324 => Opcode::VFMSUB132SHZmk_Int, + 10325 => Opcode::VFMSUB132SHZmkz_Int, + 10326 => Opcode::VFMSUB132SHZr, + 10327 => Opcode::VFMSUB132SHZr_Int, + 10328 => Opcode::VFMSUB132SHZrb, + 10329 => Opcode::VFMSUB132SHZrb_Int, + 10330 => Opcode::VFMSUB132SHZrbk_Int, + 10331 => Opcode::VFMSUB132SHZrbkz_Int, + 10332 => Opcode::VFMSUB132SHZrk_Int, + 10333 => Opcode::VFMSUB132SHZrkz_Int, + 10334 => Opcode::VFMSUB132SSZm, + 10335 => Opcode::VFMSUB132SSZm_Int, + 10336 => Opcode::VFMSUB132SSZmk_Int, + 10337 => Opcode::VFMSUB132SSZmkz_Int, + 10338 => Opcode::VFMSUB132SSZr, + 10339 => Opcode::VFMSUB132SSZr_Int, + 10340 => Opcode::VFMSUB132SSZrb, + 10341 => Opcode::VFMSUB132SSZrb_Int, + 10342 => Opcode::VFMSUB132SSZrbk_Int, + 10343 => Opcode::VFMSUB132SSZrbkz_Int, + 10344 => Opcode::VFMSUB132SSZrk_Int, + 10345 => Opcode::VFMSUB132SSZrkz_Int, + 10346 => Opcode::VFMSUB132SSm, + 10347 => Opcode::VFMSUB132SSm_Int, + 10348 => Opcode::VFMSUB132SSr, + 10349 => Opcode::VFMSUB132SSr_Int, + 10350 => Opcode::VFMSUB213BF16Z128m, + 10351 => Opcode::VFMSUB213BF16Z128mb, + 10352 => Opcode::VFMSUB213BF16Z128mbk, + 10353 => Opcode::VFMSUB213BF16Z128mbkz, + 10354 => Opcode::VFMSUB213BF16Z128mk, + 10355 => Opcode::VFMSUB213BF16Z128mkz, + 10356 => Opcode::VFMSUB213BF16Z128r, + 10357 => Opcode::VFMSUB213BF16Z128rk, + 10358 => Opcode::VFMSUB213BF16Z128rkz, + 10359 => Opcode::VFMSUB213BF16Z256m, + 10360 => Opcode::VFMSUB213BF16Z256mb, + 10361 => Opcode::VFMSUB213BF16Z256mbk, + 10362 => Opcode::VFMSUB213BF16Z256mbkz, + 10363 => Opcode::VFMSUB213BF16Z256mk, + 10364 => Opcode::VFMSUB213BF16Z256mkz, + 10365 => Opcode::VFMSUB213BF16Z256r, + 10366 => Opcode::VFMSUB213BF16Z256rk, + 10367 => Opcode::VFMSUB213BF16Z256rkz, + 10368 => Opcode::VFMSUB213BF16Zm, + 10369 => Opcode::VFMSUB213BF16Zmb, + 10370 => Opcode::VFMSUB213BF16Zmbk, + 10371 => Opcode::VFMSUB213BF16Zmbkz, + 10372 => Opcode::VFMSUB213BF16Zmk, + 10373 => Opcode::VFMSUB213BF16Zmkz, + 10374 => Opcode::VFMSUB213BF16Zr, + 10375 => Opcode::VFMSUB213BF16Zrk, + 10376 => Opcode::VFMSUB213BF16Zrkz, + 10377 => Opcode::VFMSUB213PDYm, + 10378 => Opcode::VFMSUB213PDYr, + 10379 => Opcode::VFMSUB213PDZ128m, + 10380 => Opcode::VFMSUB213PDZ128mb, + 10381 => Opcode::VFMSUB213PDZ128mbk, + 10382 => Opcode::VFMSUB213PDZ128mbkz, + 10383 => Opcode::VFMSUB213PDZ128mk, + 10384 => Opcode::VFMSUB213PDZ128mkz, + 10385 => Opcode::VFMSUB213PDZ128r, + 10386 => Opcode::VFMSUB213PDZ128rk, + 10387 => Opcode::VFMSUB213PDZ128rkz, + 10388 => Opcode::VFMSUB213PDZ256m, + 10389 => Opcode::VFMSUB213PDZ256mb, + 10390 => Opcode::VFMSUB213PDZ256mbk, + 10391 => Opcode::VFMSUB213PDZ256mbkz, + 10392 => Opcode::VFMSUB213PDZ256mk, + 10393 => Opcode::VFMSUB213PDZ256mkz, + 10394 => Opcode::VFMSUB213PDZ256r, + 10395 => Opcode::VFMSUB213PDZ256rk, + 10396 => Opcode::VFMSUB213PDZ256rkz, + 10397 => Opcode::VFMSUB213PDZm, + 10398 => Opcode::VFMSUB213PDZmb, + 10399 => Opcode::VFMSUB213PDZmbk, + 10400 => Opcode::VFMSUB213PDZmbkz, + 10401 => Opcode::VFMSUB213PDZmk, + 10402 => Opcode::VFMSUB213PDZmkz, + 10403 => Opcode::VFMSUB213PDZr, + 10404 => Opcode::VFMSUB213PDZrb, + 10405 => Opcode::VFMSUB213PDZrbk, + 10406 => Opcode::VFMSUB213PDZrbkz, + 10407 => Opcode::VFMSUB213PDZrk, + 10408 => Opcode::VFMSUB213PDZrkz, + 10409 => Opcode::VFMSUB213PDm, + 10410 => Opcode::VFMSUB213PDr, + 10411 => Opcode::VFMSUB213PHZ128m, + 10412 => Opcode::VFMSUB213PHZ128mb, + 10413 => Opcode::VFMSUB213PHZ128mbk, + 10414 => Opcode::VFMSUB213PHZ128mbkz, + 10415 => Opcode::VFMSUB213PHZ128mk, + 10416 => Opcode::VFMSUB213PHZ128mkz, + 10417 => Opcode::VFMSUB213PHZ128r, + 10418 => Opcode::VFMSUB213PHZ128rk, + 10419 => Opcode::VFMSUB213PHZ128rkz, + 10420 => Opcode::VFMSUB213PHZ256m, + 10421 => Opcode::VFMSUB213PHZ256mb, + 10422 => Opcode::VFMSUB213PHZ256mbk, + 10423 => Opcode::VFMSUB213PHZ256mbkz, + 10424 => Opcode::VFMSUB213PHZ256mk, + 10425 => Opcode::VFMSUB213PHZ256mkz, + 10426 => Opcode::VFMSUB213PHZ256r, + 10427 => Opcode::VFMSUB213PHZ256rk, + 10428 => Opcode::VFMSUB213PHZ256rkz, + 10429 => Opcode::VFMSUB213PHZm, + 10430 => Opcode::VFMSUB213PHZmb, + 10431 => Opcode::VFMSUB213PHZmbk, + 10432 => Opcode::VFMSUB213PHZmbkz, + 10433 => Opcode::VFMSUB213PHZmk, + 10434 => Opcode::VFMSUB213PHZmkz, + 10435 => Opcode::VFMSUB213PHZr, + 10436 => Opcode::VFMSUB213PHZrb, + 10437 => Opcode::VFMSUB213PHZrbk, + 10438 => Opcode::VFMSUB213PHZrbkz, + 10439 => Opcode::VFMSUB213PHZrk, + 10440 => Opcode::VFMSUB213PHZrkz, + 10441 => Opcode::VFMSUB213PSYm, + 10442 => Opcode::VFMSUB213PSYr, + 10443 => Opcode::VFMSUB213PSZ128m, + 10444 => Opcode::VFMSUB213PSZ128mb, + 10445 => Opcode::VFMSUB213PSZ128mbk, + 10446 => Opcode::VFMSUB213PSZ128mbkz, + 10447 => Opcode::VFMSUB213PSZ128mk, + 10448 => Opcode::VFMSUB213PSZ128mkz, + 10449 => Opcode::VFMSUB213PSZ128r, + 10450 => Opcode::VFMSUB213PSZ128rk, + 10451 => Opcode::VFMSUB213PSZ128rkz, + 10452 => Opcode::VFMSUB213PSZ256m, + 10453 => Opcode::VFMSUB213PSZ256mb, + 10454 => Opcode::VFMSUB213PSZ256mbk, + 10455 => Opcode::VFMSUB213PSZ256mbkz, + 10456 => Opcode::VFMSUB213PSZ256mk, + 10457 => Opcode::VFMSUB213PSZ256mkz, + 10458 => Opcode::VFMSUB213PSZ256r, + 10459 => Opcode::VFMSUB213PSZ256rk, + 10460 => Opcode::VFMSUB213PSZ256rkz, + 10461 => Opcode::VFMSUB213PSZm, + 10462 => Opcode::VFMSUB213PSZmb, + 10463 => Opcode::VFMSUB213PSZmbk, + 10464 => Opcode::VFMSUB213PSZmbkz, + 10465 => Opcode::VFMSUB213PSZmk, + 10466 => Opcode::VFMSUB213PSZmkz, + 10467 => Opcode::VFMSUB213PSZr, + 10468 => Opcode::VFMSUB213PSZrb, + 10469 => Opcode::VFMSUB213PSZrbk, + 10470 => Opcode::VFMSUB213PSZrbkz, + 10471 => Opcode::VFMSUB213PSZrk, + 10472 => Opcode::VFMSUB213PSZrkz, + 10473 => Opcode::VFMSUB213PSm, + 10474 => Opcode::VFMSUB213PSr, + 10475 => Opcode::VFMSUB213SDZm, + 10476 => Opcode::VFMSUB213SDZm_Int, + 10477 => Opcode::VFMSUB213SDZmk_Int, + 10478 => Opcode::VFMSUB213SDZmkz_Int, + 10479 => Opcode::VFMSUB213SDZr, + 10480 => Opcode::VFMSUB213SDZr_Int, + 10481 => Opcode::VFMSUB213SDZrb, + 10482 => Opcode::VFMSUB213SDZrb_Int, + 10483 => Opcode::VFMSUB213SDZrbk_Int, + 10484 => Opcode::VFMSUB213SDZrbkz_Int, + 10485 => Opcode::VFMSUB213SDZrk_Int, + 10486 => Opcode::VFMSUB213SDZrkz_Int, + 10487 => Opcode::VFMSUB213SDm, + 10488 => Opcode::VFMSUB213SDm_Int, + 10489 => Opcode::VFMSUB213SDr, + 10490 => Opcode::VFMSUB213SDr_Int, + 10491 => Opcode::VFMSUB213SHZm, + 10492 => Opcode::VFMSUB213SHZm_Int, + 10493 => Opcode::VFMSUB213SHZmk_Int, + 10494 => Opcode::VFMSUB213SHZmkz_Int, + 10495 => Opcode::VFMSUB213SHZr, + 10496 => Opcode::VFMSUB213SHZr_Int, + 10497 => Opcode::VFMSUB213SHZrb, + 10498 => Opcode::VFMSUB213SHZrb_Int, + 10499 => Opcode::VFMSUB213SHZrbk_Int, + 10500 => Opcode::VFMSUB213SHZrbkz_Int, + 10501 => Opcode::VFMSUB213SHZrk_Int, + 10502 => Opcode::VFMSUB213SHZrkz_Int, + 10503 => Opcode::VFMSUB213SSZm, + 10504 => Opcode::VFMSUB213SSZm_Int, + 10505 => Opcode::VFMSUB213SSZmk_Int, + 10506 => Opcode::VFMSUB213SSZmkz_Int, + 10507 => Opcode::VFMSUB213SSZr, + 10508 => Opcode::VFMSUB213SSZr_Int, + 10509 => Opcode::VFMSUB213SSZrb, + 10510 => Opcode::VFMSUB213SSZrb_Int, + 10511 => Opcode::VFMSUB213SSZrbk_Int, + 10512 => Opcode::VFMSUB213SSZrbkz_Int, + 10513 => Opcode::VFMSUB213SSZrk_Int, + 10514 => Opcode::VFMSUB213SSZrkz_Int, + 10515 => Opcode::VFMSUB213SSm, + 10516 => Opcode::VFMSUB213SSm_Int, + 10517 => Opcode::VFMSUB213SSr, + 10518 => Opcode::VFMSUB213SSr_Int, + 10519 => Opcode::VFMSUB231BF16Z128m, + 10520 => Opcode::VFMSUB231BF16Z128mb, + 10521 => Opcode::VFMSUB231BF16Z128mbk, + 10522 => Opcode::VFMSUB231BF16Z128mbkz, + 10523 => Opcode::VFMSUB231BF16Z128mk, + 10524 => Opcode::VFMSUB231BF16Z128mkz, + 10525 => Opcode::VFMSUB231BF16Z128r, + 10526 => Opcode::VFMSUB231BF16Z128rk, + 10527 => Opcode::VFMSUB231BF16Z128rkz, + 10528 => Opcode::VFMSUB231BF16Z256m, + 10529 => Opcode::VFMSUB231BF16Z256mb, + 10530 => Opcode::VFMSUB231BF16Z256mbk, + 10531 => Opcode::VFMSUB231BF16Z256mbkz, + 10532 => Opcode::VFMSUB231BF16Z256mk, + 10533 => Opcode::VFMSUB231BF16Z256mkz, + 10534 => Opcode::VFMSUB231BF16Z256r, + 10535 => Opcode::VFMSUB231BF16Z256rk, + 10536 => Opcode::VFMSUB231BF16Z256rkz, + 10537 => Opcode::VFMSUB231BF16Zm, + 10538 => Opcode::VFMSUB231BF16Zmb, + 10539 => Opcode::VFMSUB231BF16Zmbk, + 10540 => Opcode::VFMSUB231BF16Zmbkz, + 10541 => Opcode::VFMSUB231BF16Zmk, + 10542 => Opcode::VFMSUB231BF16Zmkz, + 10543 => Opcode::VFMSUB231BF16Zr, + 10544 => Opcode::VFMSUB231BF16Zrk, + 10545 => Opcode::VFMSUB231BF16Zrkz, + 10546 => Opcode::VFMSUB231PDYm, + 10547 => Opcode::VFMSUB231PDYr, + 10548 => Opcode::VFMSUB231PDZ128m, + 10549 => Opcode::VFMSUB231PDZ128mb, + 10550 => Opcode::VFMSUB231PDZ128mbk, + 10551 => Opcode::VFMSUB231PDZ128mbkz, + 10552 => Opcode::VFMSUB231PDZ128mk, + 10553 => Opcode::VFMSUB231PDZ128mkz, + 10554 => Opcode::VFMSUB231PDZ128r, + 10555 => Opcode::VFMSUB231PDZ128rk, + 10556 => Opcode::VFMSUB231PDZ128rkz, + 10557 => Opcode::VFMSUB231PDZ256m, + 10558 => Opcode::VFMSUB231PDZ256mb, + 10559 => Opcode::VFMSUB231PDZ256mbk, + 10560 => Opcode::VFMSUB231PDZ256mbkz, + 10561 => Opcode::VFMSUB231PDZ256mk, + 10562 => Opcode::VFMSUB231PDZ256mkz, + 10563 => Opcode::VFMSUB231PDZ256r, + 10564 => Opcode::VFMSUB231PDZ256rk, + 10565 => Opcode::VFMSUB231PDZ256rkz, + 10566 => Opcode::VFMSUB231PDZm, + 10567 => Opcode::VFMSUB231PDZmb, + 10568 => Opcode::VFMSUB231PDZmbk, + 10569 => Opcode::VFMSUB231PDZmbkz, + 10570 => Opcode::VFMSUB231PDZmk, + 10571 => Opcode::VFMSUB231PDZmkz, + 10572 => Opcode::VFMSUB231PDZr, + 10573 => Opcode::VFMSUB231PDZrb, + 10574 => Opcode::VFMSUB231PDZrbk, + 10575 => Opcode::VFMSUB231PDZrbkz, + 10576 => Opcode::VFMSUB231PDZrk, + 10577 => Opcode::VFMSUB231PDZrkz, + 10578 => Opcode::VFMSUB231PDm, + 10579 => Opcode::VFMSUB231PDr, + 10580 => Opcode::VFMSUB231PHZ128m, + 10581 => Opcode::VFMSUB231PHZ128mb, + 10582 => Opcode::VFMSUB231PHZ128mbk, + 10583 => Opcode::VFMSUB231PHZ128mbkz, + 10584 => Opcode::VFMSUB231PHZ128mk, + 10585 => Opcode::VFMSUB231PHZ128mkz, + 10586 => Opcode::VFMSUB231PHZ128r, + 10587 => Opcode::VFMSUB231PHZ128rk, + 10588 => Opcode::VFMSUB231PHZ128rkz, + 10589 => Opcode::VFMSUB231PHZ256m, + 10590 => Opcode::VFMSUB231PHZ256mb, + 10591 => Opcode::VFMSUB231PHZ256mbk, + 10592 => Opcode::VFMSUB231PHZ256mbkz, + 10593 => Opcode::VFMSUB231PHZ256mk, + 10594 => Opcode::VFMSUB231PHZ256mkz, + 10595 => Opcode::VFMSUB231PHZ256r, + 10596 => Opcode::VFMSUB231PHZ256rk, + 10597 => Opcode::VFMSUB231PHZ256rkz, + 10598 => Opcode::VFMSUB231PHZm, + 10599 => Opcode::VFMSUB231PHZmb, + 10600 => Opcode::VFMSUB231PHZmbk, + 10601 => Opcode::VFMSUB231PHZmbkz, + 10602 => Opcode::VFMSUB231PHZmk, + 10603 => Opcode::VFMSUB231PHZmkz, + 10604 => Opcode::VFMSUB231PHZr, + 10605 => Opcode::VFMSUB231PHZrb, + 10606 => Opcode::VFMSUB231PHZrbk, + 10607 => Opcode::VFMSUB231PHZrbkz, + 10608 => Opcode::VFMSUB231PHZrk, + 10609 => Opcode::VFMSUB231PHZrkz, + 10610 => Opcode::VFMSUB231PSYm, + 10611 => Opcode::VFMSUB231PSYr, + 10612 => Opcode::VFMSUB231PSZ128m, + 10613 => Opcode::VFMSUB231PSZ128mb, + 10614 => Opcode::VFMSUB231PSZ128mbk, + 10615 => Opcode::VFMSUB231PSZ128mbkz, + 10616 => Opcode::VFMSUB231PSZ128mk, + 10617 => Opcode::VFMSUB231PSZ128mkz, + 10618 => Opcode::VFMSUB231PSZ128r, + 10619 => Opcode::VFMSUB231PSZ128rk, + 10620 => Opcode::VFMSUB231PSZ128rkz, + 10621 => Opcode::VFMSUB231PSZ256m, + 10622 => Opcode::VFMSUB231PSZ256mb, + 10623 => Opcode::VFMSUB231PSZ256mbk, + 10624 => Opcode::VFMSUB231PSZ256mbkz, + 10625 => Opcode::VFMSUB231PSZ256mk, + 10626 => Opcode::VFMSUB231PSZ256mkz, + 10627 => Opcode::VFMSUB231PSZ256r, + 10628 => Opcode::VFMSUB231PSZ256rk, + 10629 => Opcode::VFMSUB231PSZ256rkz, + 10630 => Opcode::VFMSUB231PSZm, + 10631 => Opcode::VFMSUB231PSZmb, + 10632 => Opcode::VFMSUB231PSZmbk, + 10633 => Opcode::VFMSUB231PSZmbkz, + 10634 => Opcode::VFMSUB231PSZmk, + 10635 => Opcode::VFMSUB231PSZmkz, + 10636 => Opcode::VFMSUB231PSZr, + 10637 => Opcode::VFMSUB231PSZrb, + 10638 => Opcode::VFMSUB231PSZrbk, + 10639 => Opcode::VFMSUB231PSZrbkz, + 10640 => Opcode::VFMSUB231PSZrk, + 10641 => Opcode::VFMSUB231PSZrkz, + 10642 => Opcode::VFMSUB231PSm, + 10643 => Opcode::VFMSUB231PSr, + 10644 => Opcode::VFMSUB231SDZm, + 10645 => Opcode::VFMSUB231SDZm_Int, + 10646 => Opcode::VFMSUB231SDZmk_Int, + 10647 => Opcode::VFMSUB231SDZmkz_Int, + 10648 => Opcode::VFMSUB231SDZr, + 10649 => Opcode::VFMSUB231SDZr_Int, + 10650 => Opcode::VFMSUB231SDZrb, + 10651 => Opcode::VFMSUB231SDZrb_Int, + 10652 => Opcode::VFMSUB231SDZrbk_Int, + 10653 => Opcode::VFMSUB231SDZrbkz_Int, + 10654 => Opcode::VFMSUB231SDZrk_Int, + 10655 => Opcode::VFMSUB231SDZrkz_Int, + 10656 => Opcode::VFMSUB231SDm, + 10657 => Opcode::VFMSUB231SDm_Int, + 10658 => Opcode::VFMSUB231SDr, + 10659 => Opcode::VFMSUB231SDr_Int, + 10660 => Opcode::VFMSUB231SHZm, + 10661 => Opcode::VFMSUB231SHZm_Int, + 10662 => Opcode::VFMSUB231SHZmk_Int, + 10663 => Opcode::VFMSUB231SHZmkz_Int, + 10664 => Opcode::VFMSUB231SHZr, + 10665 => Opcode::VFMSUB231SHZr_Int, + 10666 => Opcode::VFMSUB231SHZrb, + 10667 => Opcode::VFMSUB231SHZrb_Int, + 10668 => Opcode::VFMSUB231SHZrbk_Int, + 10669 => Opcode::VFMSUB231SHZrbkz_Int, + 10670 => Opcode::VFMSUB231SHZrk_Int, + 10671 => Opcode::VFMSUB231SHZrkz_Int, + 10672 => Opcode::VFMSUB231SSZm, + 10673 => Opcode::VFMSUB231SSZm_Int, + 10674 => Opcode::VFMSUB231SSZmk_Int, + 10675 => Opcode::VFMSUB231SSZmkz_Int, + 10676 => Opcode::VFMSUB231SSZr, + 10677 => Opcode::VFMSUB231SSZr_Int, + 10678 => Opcode::VFMSUB231SSZrb, + 10679 => Opcode::VFMSUB231SSZrb_Int, + 10680 => Opcode::VFMSUB231SSZrbk_Int, + 10681 => Opcode::VFMSUB231SSZrbkz_Int, + 10682 => Opcode::VFMSUB231SSZrk_Int, + 10683 => Opcode::VFMSUB231SSZrkz_Int, + 10684 => Opcode::VFMSUB231SSm, + 10685 => Opcode::VFMSUB231SSm_Int, + 10686 => Opcode::VFMSUB231SSr, + 10687 => Opcode::VFMSUB231SSr_Int, + 10688 => Opcode::VFMSUBADD132PDYm, + 10689 => Opcode::VFMSUBADD132PDYr, + 10690 => Opcode::VFMSUBADD132PDZ128m, + 10691 => Opcode::VFMSUBADD132PDZ128mb, + 10692 => Opcode::VFMSUBADD132PDZ128mbk, + 10693 => Opcode::VFMSUBADD132PDZ128mbkz, + 10694 => Opcode::VFMSUBADD132PDZ128mk, + 10695 => Opcode::VFMSUBADD132PDZ128mkz, + 10696 => Opcode::VFMSUBADD132PDZ128r, + 10697 => Opcode::VFMSUBADD132PDZ128rk, + 10698 => Opcode::VFMSUBADD132PDZ128rkz, + 10699 => Opcode::VFMSUBADD132PDZ256m, + 10700 => Opcode::VFMSUBADD132PDZ256mb, + 10701 => Opcode::VFMSUBADD132PDZ256mbk, + 10702 => Opcode::VFMSUBADD132PDZ256mbkz, + 10703 => Opcode::VFMSUBADD132PDZ256mk, + 10704 => Opcode::VFMSUBADD132PDZ256mkz, + 10705 => Opcode::VFMSUBADD132PDZ256r, + 10706 => Opcode::VFMSUBADD132PDZ256rk, + 10707 => Opcode::VFMSUBADD132PDZ256rkz, + 10708 => Opcode::VFMSUBADD132PDZm, + 10709 => Opcode::VFMSUBADD132PDZmb, + 10710 => Opcode::VFMSUBADD132PDZmbk, + 10711 => Opcode::VFMSUBADD132PDZmbkz, + 10712 => Opcode::VFMSUBADD132PDZmk, + 10713 => Opcode::VFMSUBADD132PDZmkz, + 10714 => Opcode::VFMSUBADD132PDZr, + 10715 => Opcode::VFMSUBADD132PDZrb, + 10716 => Opcode::VFMSUBADD132PDZrbk, + 10717 => Opcode::VFMSUBADD132PDZrbkz, + 10718 => Opcode::VFMSUBADD132PDZrk, + 10719 => Opcode::VFMSUBADD132PDZrkz, + 10720 => Opcode::VFMSUBADD132PDm, + 10721 => Opcode::VFMSUBADD132PDr, + 10722 => Opcode::VFMSUBADD132PHZ128m, + 10723 => Opcode::VFMSUBADD132PHZ128mb, + 10724 => Opcode::VFMSUBADD132PHZ128mbk, + 10725 => Opcode::VFMSUBADD132PHZ128mbkz, + 10726 => Opcode::VFMSUBADD132PHZ128mk, + 10727 => Opcode::VFMSUBADD132PHZ128mkz, + 10728 => Opcode::VFMSUBADD132PHZ128r, + 10729 => Opcode::VFMSUBADD132PHZ128rk, + 10730 => Opcode::VFMSUBADD132PHZ128rkz, + 10731 => Opcode::VFMSUBADD132PHZ256m, + 10732 => Opcode::VFMSUBADD132PHZ256mb, + 10733 => Opcode::VFMSUBADD132PHZ256mbk, + 10734 => Opcode::VFMSUBADD132PHZ256mbkz, + 10735 => Opcode::VFMSUBADD132PHZ256mk, + 10736 => Opcode::VFMSUBADD132PHZ256mkz, + 10737 => Opcode::VFMSUBADD132PHZ256r, + 10738 => Opcode::VFMSUBADD132PHZ256rk, + 10739 => Opcode::VFMSUBADD132PHZ256rkz, + 10740 => Opcode::VFMSUBADD132PHZm, + 10741 => Opcode::VFMSUBADD132PHZmb, + 10742 => Opcode::VFMSUBADD132PHZmbk, + 10743 => Opcode::VFMSUBADD132PHZmbkz, + 10744 => Opcode::VFMSUBADD132PHZmk, + 10745 => Opcode::VFMSUBADD132PHZmkz, + 10746 => Opcode::VFMSUBADD132PHZr, + 10747 => Opcode::VFMSUBADD132PHZrb, + 10748 => Opcode::VFMSUBADD132PHZrbk, + 10749 => Opcode::VFMSUBADD132PHZrbkz, + 10750 => Opcode::VFMSUBADD132PHZrk, + 10751 => Opcode::VFMSUBADD132PHZrkz, + 10752 => Opcode::VFMSUBADD132PSYm, + 10753 => Opcode::VFMSUBADD132PSYr, + 10754 => Opcode::VFMSUBADD132PSZ128m, + 10755 => Opcode::VFMSUBADD132PSZ128mb, + 10756 => Opcode::VFMSUBADD132PSZ128mbk, + 10757 => Opcode::VFMSUBADD132PSZ128mbkz, + 10758 => Opcode::VFMSUBADD132PSZ128mk, + 10759 => Opcode::VFMSUBADD132PSZ128mkz, + 10760 => Opcode::VFMSUBADD132PSZ128r, + 10761 => Opcode::VFMSUBADD132PSZ128rk, + 10762 => Opcode::VFMSUBADD132PSZ128rkz, + 10763 => Opcode::VFMSUBADD132PSZ256m, + 10764 => Opcode::VFMSUBADD132PSZ256mb, + 10765 => Opcode::VFMSUBADD132PSZ256mbk, + 10766 => Opcode::VFMSUBADD132PSZ256mbkz, + 10767 => Opcode::VFMSUBADD132PSZ256mk, + 10768 => Opcode::VFMSUBADD132PSZ256mkz, + 10769 => Opcode::VFMSUBADD132PSZ256r, + 10770 => Opcode::VFMSUBADD132PSZ256rk, + 10771 => Opcode::VFMSUBADD132PSZ256rkz, + 10772 => Opcode::VFMSUBADD132PSZm, + 10773 => Opcode::VFMSUBADD132PSZmb, + 10774 => Opcode::VFMSUBADD132PSZmbk, + 10775 => Opcode::VFMSUBADD132PSZmbkz, + 10776 => Opcode::VFMSUBADD132PSZmk, + 10777 => Opcode::VFMSUBADD132PSZmkz, + 10778 => Opcode::VFMSUBADD132PSZr, + 10779 => Opcode::VFMSUBADD132PSZrb, + 10780 => Opcode::VFMSUBADD132PSZrbk, + 10781 => Opcode::VFMSUBADD132PSZrbkz, + 10782 => Opcode::VFMSUBADD132PSZrk, + 10783 => Opcode::VFMSUBADD132PSZrkz, + 10784 => Opcode::VFMSUBADD132PSm, + 10785 => Opcode::VFMSUBADD132PSr, + 10786 => Opcode::VFMSUBADD213PDYm, + 10787 => Opcode::VFMSUBADD213PDYr, + 10788 => Opcode::VFMSUBADD213PDZ128m, + 10789 => Opcode::VFMSUBADD213PDZ128mb, + 10790 => Opcode::VFMSUBADD213PDZ128mbk, + 10791 => Opcode::VFMSUBADD213PDZ128mbkz, + 10792 => Opcode::VFMSUBADD213PDZ128mk, + 10793 => Opcode::VFMSUBADD213PDZ128mkz, + 10794 => Opcode::VFMSUBADD213PDZ128r, + 10795 => Opcode::VFMSUBADD213PDZ128rk, + 10796 => Opcode::VFMSUBADD213PDZ128rkz, + 10797 => Opcode::VFMSUBADD213PDZ256m, + 10798 => Opcode::VFMSUBADD213PDZ256mb, + 10799 => Opcode::VFMSUBADD213PDZ256mbk, + 10800 => Opcode::VFMSUBADD213PDZ256mbkz, + 10801 => Opcode::VFMSUBADD213PDZ256mk, + 10802 => Opcode::VFMSUBADD213PDZ256mkz, + 10803 => Opcode::VFMSUBADD213PDZ256r, + 10804 => Opcode::VFMSUBADD213PDZ256rk, + 10805 => Opcode::VFMSUBADD213PDZ256rkz, + 10806 => Opcode::VFMSUBADD213PDZm, + 10807 => Opcode::VFMSUBADD213PDZmb, + 10808 => Opcode::VFMSUBADD213PDZmbk, + 10809 => Opcode::VFMSUBADD213PDZmbkz, + 10810 => Opcode::VFMSUBADD213PDZmk, + 10811 => Opcode::VFMSUBADD213PDZmkz, + 10812 => Opcode::VFMSUBADD213PDZr, + 10813 => Opcode::VFMSUBADD213PDZrb, + 10814 => Opcode::VFMSUBADD213PDZrbk, + 10815 => Opcode::VFMSUBADD213PDZrbkz, + 10816 => Opcode::VFMSUBADD213PDZrk, + 10817 => Opcode::VFMSUBADD213PDZrkz, + 10818 => Opcode::VFMSUBADD213PDm, + 10819 => Opcode::VFMSUBADD213PDr, + 10820 => Opcode::VFMSUBADD213PHZ128m, + 10821 => Opcode::VFMSUBADD213PHZ128mb, + 10822 => Opcode::VFMSUBADD213PHZ128mbk, + 10823 => Opcode::VFMSUBADD213PHZ128mbkz, + 10824 => Opcode::VFMSUBADD213PHZ128mk, + 10825 => Opcode::VFMSUBADD213PHZ128mkz, + 10826 => Opcode::VFMSUBADD213PHZ128r, + 10827 => Opcode::VFMSUBADD213PHZ128rk, + 10828 => Opcode::VFMSUBADD213PHZ128rkz, + 10829 => Opcode::VFMSUBADD213PHZ256m, + 10830 => Opcode::VFMSUBADD213PHZ256mb, + 10831 => Opcode::VFMSUBADD213PHZ256mbk, + 10832 => Opcode::VFMSUBADD213PHZ256mbkz, + 10833 => Opcode::VFMSUBADD213PHZ256mk, + 10834 => Opcode::VFMSUBADD213PHZ256mkz, + 10835 => Opcode::VFMSUBADD213PHZ256r, + 10836 => Opcode::VFMSUBADD213PHZ256rk, + 10837 => Opcode::VFMSUBADD213PHZ256rkz, + 10838 => Opcode::VFMSUBADD213PHZm, + 10839 => Opcode::VFMSUBADD213PHZmb, + 10840 => Opcode::VFMSUBADD213PHZmbk, + 10841 => Opcode::VFMSUBADD213PHZmbkz, + 10842 => Opcode::VFMSUBADD213PHZmk, + 10843 => Opcode::VFMSUBADD213PHZmkz, + 10844 => Opcode::VFMSUBADD213PHZr, + 10845 => Opcode::VFMSUBADD213PHZrb, + 10846 => Opcode::VFMSUBADD213PHZrbk, + 10847 => Opcode::VFMSUBADD213PHZrbkz, + 10848 => Opcode::VFMSUBADD213PHZrk, + 10849 => Opcode::VFMSUBADD213PHZrkz, + 10850 => Opcode::VFMSUBADD213PSYm, + 10851 => Opcode::VFMSUBADD213PSYr, + 10852 => Opcode::VFMSUBADD213PSZ128m, + 10853 => Opcode::VFMSUBADD213PSZ128mb, + 10854 => Opcode::VFMSUBADD213PSZ128mbk, + 10855 => Opcode::VFMSUBADD213PSZ128mbkz, + 10856 => Opcode::VFMSUBADD213PSZ128mk, + 10857 => Opcode::VFMSUBADD213PSZ128mkz, + 10858 => Opcode::VFMSUBADD213PSZ128r, + 10859 => Opcode::VFMSUBADD213PSZ128rk, + 10860 => Opcode::VFMSUBADD213PSZ128rkz, + 10861 => Opcode::VFMSUBADD213PSZ256m, + 10862 => Opcode::VFMSUBADD213PSZ256mb, + 10863 => Opcode::VFMSUBADD213PSZ256mbk, + 10864 => Opcode::VFMSUBADD213PSZ256mbkz, + 10865 => Opcode::VFMSUBADD213PSZ256mk, + 10866 => Opcode::VFMSUBADD213PSZ256mkz, + 10867 => Opcode::VFMSUBADD213PSZ256r, + 10868 => Opcode::VFMSUBADD213PSZ256rk, + 10869 => Opcode::VFMSUBADD213PSZ256rkz, + 10870 => Opcode::VFMSUBADD213PSZm, + 10871 => Opcode::VFMSUBADD213PSZmb, + 10872 => Opcode::VFMSUBADD213PSZmbk, + 10873 => Opcode::VFMSUBADD213PSZmbkz, + 10874 => Opcode::VFMSUBADD213PSZmk, + 10875 => Opcode::VFMSUBADD213PSZmkz, + 10876 => Opcode::VFMSUBADD213PSZr, + 10877 => Opcode::VFMSUBADD213PSZrb, + 10878 => Opcode::VFMSUBADD213PSZrbk, + 10879 => Opcode::VFMSUBADD213PSZrbkz, + 10880 => Opcode::VFMSUBADD213PSZrk, + 10881 => Opcode::VFMSUBADD213PSZrkz, + 10882 => Opcode::VFMSUBADD213PSm, + 10883 => Opcode::VFMSUBADD213PSr, + 10884 => Opcode::VFMSUBADD231PDYm, + 10885 => Opcode::VFMSUBADD231PDYr, + 10886 => Opcode::VFMSUBADD231PDZ128m, + 10887 => Opcode::VFMSUBADD231PDZ128mb, + 10888 => Opcode::VFMSUBADD231PDZ128mbk, + 10889 => Opcode::VFMSUBADD231PDZ128mbkz, + 10890 => Opcode::VFMSUBADD231PDZ128mk, + 10891 => Opcode::VFMSUBADD231PDZ128mkz, + 10892 => Opcode::VFMSUBADD231PDZ128r, + 10893 => Opcode::VFMSUBADD231PDZ128rk, + 10894 => Opcode::VFMSUBADD231PDZ128rkz, + 10895 => Opcode::VFMSUBADD231PDZ256m, + 10896 => Opcode::VFMSUBADD231PDZ256mb, + 10897 => Opcode::VFMSUBADD231PDZ256mbk, + 10898 => Opcode::VFMSUBADD231PDZ256mbkz, + 10899 => Opcode::VFMSUBADD231PDZ256mk, + 10900 => Opcode::VFMSUBADD231PDZ256mkz, + 10901 => Opcode::VFMSUBADD231PDZ256r, + 10902 => Opcode::VFMSUBADD231PDZ256rk, + 10903 => Opcode::VFMSUBADD231PDZ256rkz, + 10904 => Opcode::VFMSUBADD231PDZm, + 10905 => Opcode::VFMSUBADD231PDZmb, + 10906 => Opcode::VFMSUBADD231PDZmbk, + 10907 => Opcode::VFMSUBADD231PDZmbkz, + 10908 => Opcode::VFMSUBADD231PDZmk, + 10909 => Opcode::VFMSUBADD231PDZmkz, + 10910 => Opcode::VFMSUBADD231PDZr, + 10911 => Opcode::VFMSUBADD231PDZrb, + 10912 => Opcode::VFMSUBADD231PDZrbk, + 10913 => Opcode::VFMSUBADD231PDZrbkz, + 10914 => Opcode::VFMSUBADD231PDZrk, + 10915 => Opcode::VFMSUBADD231PDZrkz, + 10916 => Opcode::VFMSUBADD231PDm, + 10917 => Opcode::VFMSUBADD231PDr, + 10918 => Opcode::VFMSUBADD231PHZ128m, + 10919 => Opcode::VFMSUBADD231PHZ128mb, + 10920 => Opcode::VFMSUBADD231PHZ128mbk, + 10921 => Opcode::VFMSUBADD231PHZ128mbkz, + 10922 => Opcode::VFMSUBADD231PHZ128mk, + 10923 => Opcode::VFMSUBADD231PHZ128mkz, + 10924 => Opcode::VFMSUBADD231PHZ128r, + 10925 => Opcode::VFMSUBADD231PHZ128rk, + 10926 => Opcode::VFMSUBADD231PHZ128rkz, + 10927 => Opcode::VFMSUBADD231PHZ256m, + 10928 => Opcode::VFMSUBADD231PHZ256mb, + 10929 => Opcode::VFMSUBADD231PHZ256mbk, + 10930 => Opcode::VFMSUBADD231PHZ256mbkz, + 10931 => Opcode::VFMSUBADD231PHZ256mk, + 10932 => Opcode::VFMSUBADD231PHZ256mkz, + 10933 => Opcode::VFMSUBADD231PHZ256r, + 10934 => Opcode::VFMSUBADD231PHZ256rk, + 10935 => Opcode::VFMSUBADD231PHZ256rkz, + 10936 => Opcode::VFMSUBADD231PHZm, + 10937 => Opcode::VFMSUBADD231PHZmb, + 10938 => Opcode::VFMSUBADD231PHZmbk, + 10939 => Opcode::VFMSUBADD231PHZmbkz, + 10940 => Opcode::VFMSUBADD231PHZmk, + 10941 => Opcode::VFMSUBADD231PHZmkz, + 10942 => Opcode::VFMSUBADD231PHZr, + 10943 => Opcode::VFMSUBADD231PHZrb, + 10944 => Opcode::VFMSUBADD231PHZrbk, + 10945 => Opcode::VFMSUBADD231PHZrbkz, + 10946 => Opcode::VFMSUBADD231PHZrk, + 10947 => Opcode::VFMSUBADD231PHZrkz, + 10948 => Opcode::VFMSUBADD231PSYm, + 10949 => Opcode::VFMSUBADD231PSYr, + 10950 => Opcode::VFMSUBADD231PSZ128m, + 10951 => Opcode::VFMSUBADD231PSZ128mb, + 10952 => Opcode::VFMSUBADD231PSZ128mbk, + 10953 => Opcode::VFMSUBADD231PSZ128mbkz, + 10954 => Opcode::VFMSUBADD231PSZ128mk, + 10955 => Opcode::VFMSUBADD231PSZ128mkz, + 10956 => Opcode::VFMSUBADD231PSZ128r, + 10957 => Opcode::VFMSUBADD231PSZ128rk, + 10958 => Opcode::VFMSUBADD231PSZ128rkz, + 10959 => Opcode::VFMSUBADD231PSZ256m, + 10960 => Opcode::VFMSUBADD231PSZ256mb, + 10961 => Opcode::VFMSUBADD231PSZ256mbk, + 10962 => Opcode::VFMSUBADD231PSZ256mbkz, + 10963 => Opcode::VFMSUBADD231PSZ256mk, + 10964 => Opcode::VFMSUBADD231PSZ256mkz, + 10965 => Opcode::VFMSUBADD231PSZ256r, + 10966 => Opcode::VFMSUBADD231PSZ256rk, + 10967 => Opcode::VFMSUBADD231PSZ256rkz, + 10968 => Opcode::VFMSUBADD231PSZm, + 10969 => Opcode::VFMSUBADD231PSZmb, + 10970 => Opcode::VFMSUBADD231PSZmbk, + 10971 => Opcode::VFMSUBADD231PSZmbkz, + 10972 => Opcode::VFMSUBADD231PSZmk, + 10973 => Opcode::VFMSUBADD231PSZmkz, + 10974 => Opcode::VFMSUBADD231PSZr, + 10975 => Opcode::VFMSUBADD231PSZrb, + 10976 => Opcode::VFMSUBADD231PSZrbk, + 10977 => Opcode::VFMSUBADD231PSZrbkz, + 10978 => Opcode::VFMSUBADD231PSZrk, + 10979 => Opcode::VFMSUBADD231PSZrkz, + 10980 => Opcode::VFMSUBADD231PSm, + 10981 => Opcode::VFMSUBADD231PSr, + 10982 => Opcode::VFMSUBADDPD4Ymr, + 10983 => Opcode::VFMSUBADDPD4Yrm, + 10984 => Opcode::VFMSUBADDPD4Yrr, + 10985 => Opcode::VFMSUBADDPD4Yrr_REV, + 10986 => Opcode::VFMSUBADDPD4mr, + 10987 => Opcode::VFMSUBADDPD4rm, + 10988 => Opcode::VFMSUBADDPD4rr, + 10989 => Opcode::VFMSUBADDPD4rr_REV, + 10990 => Opcode::VFMSUBADDPS4Ymr, + 10991 => Opcode::VFMSUBADDPS4Yrm, + 10992 => Opcode::VFMSUBADDPS4Yrr, + 10993 => Opcode::VFMSUBADDPS4Yrr_REV, + 10994 => Opcode::VFMSUBADDPS4mr, + 10995 => Opcode::VFMSUBADDPS4rm, + 10996 => Opcode::VFMSUBADDPS4rr, + 10997 => Opcode::VFMSUBADDPS4rr_REV, + 10998 => Opcode::VFMSUBPD4Ymr, + 10999 => Opcode::VFMSUBPD4Yrm, + 11000 => Opcode::VFMSUBPD4Yrr, + 11001 => Opcode::VFMSUBPD4Yrr_REV, + 11002 => Opcode::VFMSUBPD4mr, + 11003 => Opcode::VFMSUBPD4rm, + 11004 => Opcode::VFMSUBPD4rr, + 11005 => Opcode::VFMSUBPD4rr_REV, + 11006 => Opcode::VFMSUBPS4Ymr, + 11007 => Opcode::VFMSUBPS4Yrm, + 11008 => Opcode::VFMSUBPS4Yrr, + 11009 => Opcode::VFMSUBPS4Yrr_REV, + 11010 => Opcode::VFMSUBPS4mr, + 11011 => Opcode::VFMSUBPS4rm, + 11012 => Opcode::VFMSUBPS4rr, + 11013 => Opcode::VFMSUBPS4rr_REV, + 11014 => Opcode::VFMSUBSD4mr, + 11015 => Opcode::VFMSUBSD4mr_Int, + 11016 => Opcode::VFMSUBSD4rm, + 11017 => Opcode::VFMSUBSD4rm_Int, + 11018 => Opcode::VFMSUBSD4rr, + 11019 => Opcode::VFMSUBSD4rr_Int, + 11020 => Opcode::VFMSUBSD4rr_Int_REV, + 11021 => Opcode::VFMSUBSD4rr_REV, + 11022 => Opcode::VFMSUBSS4mr, + 11023 => Opcode::VFMSUBSS4mr_Int, + 11024 => Opcode::VFMSUBSS4rm, + 11025 => Opcode::VFMSUBSS4rm_Int, + 11026 => Opcode::VFMSUBSS4rr, + 11027 => Opcode::VFMSUBSS4rr_Int, + 11028 => Opcode::VFMSUBSS4rr_Int_REV, + 11029 => Opcode::VFMSUBSS4rr_REV, + 11030 => Opcode::VFMULCPHZ128rm, + 11031 => Opcode::VFMULCPHZ128rmb, + 11032 => Opcode::VFMULCPHZ128rmbk, + 11033 => Opcode::VFMULCPHZ128rmbkz, + 11034 => Opcode::VFMULCPHZ128rmk, + 11035 => Opcode::VFMULCPHZ128rmkz, + 11036 => Opcode::VFMULCPHZ128rr, + 11037 => Opcode::VFMULCPHZ128rrk, + 11038 => Opcode::VFMULCPHZ128rrkz, + 11039 => Opcode::VFMULCPHZ256rm, + 11040 => Opcode::VFMULCPHZ256rmb, + 11041 => Opcode::VFMULCPHZ256rmbk, + 11042 => Opcode::VFMULCPHZ256rmbkz, + 11043 => Opcode::VFMULCPHZ256rmk, + 11044 => Opcode::VFMULCPHZ256rmkz, + 11045 => Opcode::VFMULCPHZ256rr, + 11046 => Opcode::VFMULCPHZ256rrk, + 11047 => Opcode::VFMULCPHZ256rrkz, + 11048 => Opcode::VFMULCPHZrm, + 11049 => Opcode::VFMULCPHZrmb, + 11050 => Opcode::VFMULCPHZrmbk, + 11051 => Opcode::VFMULCPHZrmbkz, + 11052 => Opcode::VFMULCPHZrmk, + 11053 => Opcode::VFMULCPHZrmkz, + 11054 => Opcode::VFMULCPHZrr, + 11055 => Opcode::VFMULCPHZrrb, + 11056 => Opcode::VFMULCPHZrrbk, + 11057 => Opcode::VFMULCPHZrrbkz, + 11058 => Opcode::VFMULCPHZrrk, + 11059 => Opcode::VFMULCPHZrrkz, + 11060 => Opcode::VFMULCSHZrm, + 11061 => Opcode::VFMULCSHZrmk, + 11062 => Opcode::VFMULCSHZrmkz, + 11063 => Opcode::VFMULCSHZrr, + 11064 => Opcode::VFMULCSHZrrb, + 11065 => Opcode::VFMULCSHZrrbk, + 11066 => Opcode::VFMULCSHZrrbkz, + 11067 => Opcode::VFMULCSHZrrk, + 11068 => Opcode::VFMULCSHZrrkz, + 11069 => Opcode::VFNMADD132BF16Z128m, + 11070 => Opcode::VFNMADD132BF16Z128mb, + 11071 => Opcode::VFNMADD132BF16Z128mbk, + 11072 => Opcode::VFNMADD132BF16Z128mbkz, + 11073 => Opcode::VFNMADD132BF16Z128mk, + 11074 => Opcode::VFNMADD132BF16Z128mkz, + 11075 => Opcode::VFNMADD132BF16Z128r, + 11076 => Opcode::VFNMADD132BF16Z128rk, + 11077 => Opcode::VFNMADD132BF16Z128rkz, + 11078 => Opcode::VFNMADD132BF16Z256m, + 11079 => Opcode::VFNMADD132BF16Z256mb, + 11080 => Opcode::VFNMADD132BF16Z256mbk, + 11081 => Opcode::VFNMADD132BF16Z256mbkz, + 11082 => Opcode::VFNMADD132BF16Z256mk, + 11083 => Opcode::VFNMADD132BF16Z256mkz, + 11084 => Opcode::VFNMADD132BF16Z256r, + 11085 => Opcode::VFNMADD132BF16Z256rk, + 11086 => Opcode::VFNMADD132BF16Z256rkz, + 11087 => Opcode::VFNMADD132BF16Zm, + 11088 => Opcode::VFNMADD132BF16Zmb, + 11089 => Opcode::VFNMADD132BF16Zmbk, + 11090 => Opcode::VFNMADD132BF16Zmbkz, + 11091 => Opcode::VFNMADD132BF16Zmk, + 11092 => Opcode::VFNMADD132BF16Zmkz, + 11093 => Opcode::VFNMADD132BF16Zr, + 11094 => Opcode::VFNMADD132BF16Zrk, + 11095 => Opcode::VFNMADD132BF16Zrkz, + 11096 => Opcode::VFNMADD132PDYm, + 11097 => Opcode::VFNMADD132PDYr, + 11098 => Opcode::VFNMADD132PDZ128m, + 11099 => Opcode::VFNMADD132PDZ128mb, + 11100 => Opcode::VFNMADD132PDZ128mbk, + 11101 => Opcode::VFNMADD132PDZ128mbkz, + 11102 => Opcode::VFNMADD132PDZ128mk, + 11103 => Opcode::VFNMADD132PDZ128mkz, + 11104 => Opcode::VFNMADD132PDZ128r, + 11105 => Opcode::VFNMADD132PDZ128rk, + 11106 => Opcode::VFNMADD132PDZ128rkz, + 11107 => Opcode::VFNMADD132PDZ256m, + 11108 => Opcode::VFNMADD132PDZ256mb, + 11109 => Opcode::VFNMADD132PDZ256mbk, + 11110 => Opcode::VFNMADD132PDZ256mbkz, + 11111 => Opcode::VFNMADD132PDZ256mk, + 11112 => Opcode::VFNMADD132PDZ256mkz, + 11113 => Opcode::VFNMADD132PDZ256r, + 11114 => Opcode::VFNMADD132PDZ256rk, + 11115 => Opcode::VFNMADD132PDZ256rkz, + 11116 => Opcode::VFNMADD132PDZm, + 11117 => Opcode::VFNMADD132PDZmb, + 11118 => Opcode::VFNMADD132PDZmbk, + 11119 => Opcode::VFNMADD132PDZmbkz, + 11120 => Opcode::VFNMADD132PDZmk, + 11121 => Opcode::VFNMADD132PDZmkz, + 11122 => Opcode::VFNMADD132PDZr, + 11123 => Opcode::VFNMADD132PDZrb, + 11124 => Opcode::VFNMADD132PDZrbk, + 11125 => Opcode::VFNMADD132PDZrbkz, + 11126 => Opcode::VFNMADD132PDZrk, + 11127 => Opcode::VFNMADD132PDZrkz, + 11128 => Opcode::VFNMADD132PDm, + 11129 => Opcode::VFNMADD132PDr, + 11130 => Opcode::VFNMADD132PHZ128m, + 11131 => Opcode::VFNMADD132PHZ128mb, + 11132 => Opcode::VFNMADD132PHZ128mbk, + 11133 => Opcode::VFNMADD132PHZ128mbkz, + 11134 => Opcode::VFNMADD132PHZ128mk, + 11135 => Opcode::VFNMADD132PHZ128mkz, + 11136 => Opcode::VFNMADD132PHZ128r, + 11137 => Opcode::VFNMADD132PHZ128rk, + 11138 => Opcode::VFNMADD132PHZ128rkz, + 11139 => Opcode::VFNMADD132PHZ256m, + 11140 => Opcode::VFNMADD132PHZ256mb, + 11141 => Opcode::VFNMADD132PHZ256mbk, + 11142 => Opcode::VFNMADD132PHZ256mbkz, + 11143 => Opcode::VFNMADD132PHZ256mk, + 11144 => Opcode::VFNMADD132PHZ256mkz, + 11145 => Opcode::VFNMADD132PHZ256r, + 11146 => Opcode::VFNMADD132PHZ256rk, + 11147 => Opcode::VFNMADD132PHZ256rkz, + 11148 => Opcode::VFNMADD132PHZm, + 11149 => Opcode::VFNMADD132PHZmb, + 11150 => Opcode::VFNMADD132PHZmbk, + 11151 => Opcode::VFNMADD132PHZmbkz, + 11152 => Opcode::VFNMADD132PHZmk, + 11153 => Opcode::VFNMADD132PHZmkz, + 11154 => Opcode::VFNMADD132PHZr, + 11155 => Opcode::VFNMADD132PHZrb, + 11156 => Opcode::VFNMADD132PHZrbk, + 11157 => Opcode::VFNMADD132PHZrbkz, + 11158 => Opcode::VFNMADD132PHZrk, + 11159 => Opcode::VFNMADD132PHZrkz, + 11160 => Opcode::VFNMADD132PSYm, + 11161 => Opcode::VFNMADD132PSYr, + 11162 => Opcode::VFNMADD132PSZ128m, + 11163 => Opcode::VFNMADD132PSZ128mb, + 11164 => Opcode::VFNMADD132PSZ128mbk, + 11165 => Opcode::VFNMADD132PSZ128mbkz, + 11166 => Opcode::VFNMADD132PSZ128mk, + 11167 => Opcode::VFNMADD132PSZ128mkz, + 11168 => Opcode::VFNMADD132PSZ128r, + 11169 => Opcode::VFNMADD132PSZ128rk, + 11170 => Opcode::VFNMADD132PSZ128rkz, + 11171 => Opcode::VFNMADD132PSZ256m, + 11172 => Opcode::VFNMADD132PSZ256mb, + 11173 => Opcode::VFNMADD132PSZ256mbk, + 11174 => Opcode::VFNMADD132PSZ256mbkz, + 11175 => Opcode::VFNMADD132PSZ256mk, + 11176 => Opcode::VFNMADD132PSZ256mkz, + 11177 => Opcode::VFNMADD132PSZ256r, + 11178 => Opcode::VFNMADD132PSZ256rk, + 11179 => Opcode::VFNMADD132PSZ256rkz, + 11180 => Opcode::VFNMADD132PSZm, + 11181 => Opcode::VFNMADD132PSZmb, + 11182 => Opcode::VFNMADD132PSZmbk, + 11183 => Opcode::VFNMADD132PSZmbkz, + 11184 => Opcode::VFNMADD132PSZmk, + 11185 => Opcode::VFNMADD132PSZmkz, + 11186 => Opcode::VFNMADD132PSZr, + 11187 => Opcode::VFNMADD132PSZrb, + 11188 => Opcode::VFNMADD132PSZrbk, + 11189 => Opcode::VFNMADD132PSZrbkz, + 11190 => Opcode::VFNMADD132PSZrk, + 11191 => Opcode::VFNMADD132PSZrkz, + 11192 => Opcode::VFNMADD132PSm, + 11193 => Opcode::VFNMADD132PSr, + 11194 => Opcode::VFNMADD132SDZm, + 11195 => Opcode::VFNMADD132SDZm_Int, + 11196 => Opcode::VFNMADD132SDZmk_Int, + 11197 => Opcode::VFNMADD132SDZmkz_Int, + 11198 => Opcode::VFNMADD132SDZr, + 11199 => Opcode::VFNMADD132SDZr_Int, + 11200 => Opcode::VFNMADD132SDZrb, + 11201 => Opcode::VFNMADD132SDZrb_Int, + 11202 => Opcode::VFNMADD132SDZrbk_Int, + 11203 => Opcode::VFNMADD132SDZrbkz_Int, + 11204 => Opcode::VFNMADD132SDZrk_Int, + 11205 => Opcode::VFNMADD132SDZrkz_Int, + 11206 => Opcode::VFNMADD132SDm, + 11207 => Opcode::VFNMADD132SDm_Int, + 11208 => Opcode::VFNMADD132SDr, + 11209 => Opcode::VFNMADD132SDr_Int, + 11210 => Opcode::VFNMADD132SHZm, + 11211 => Opcode::VFNMADD132SHZm_Int, + 11212 => Opcode::VFNMADD132SHZmk_Int, + 11213 => Opcode::VFNMADD132SHZmkz_Int, + 11214 => Opcode::VFNMADD132SHZr, + 11215 => Opcode::VFNMADD132SHZr_Int, + 11216 => Opcode::VFNMADD132SHZrb, + 11217 => Opcode::VFNMADD132SHZrb_Int, + 11218 => Opcode::VFNMADD132SHZrbk_Int, + 11219 => Opcode::VFNMADD132SHZrbkz_Int, + 11220 => Opcode::VFNMADD132SHZrk_Int, + 11221 => Opcode::VFNMADD132SHZrkz_Int, + 11222 => Opcode::VFNMADD132SSZm, + 11223 => Opcode::VFNMADD132SSZm_Int, + 11224 => Opcode::VFNMADD132SSZmk_Int, + 11225 => Opcode::VFNMADD132SSZmkz_Int, + 11226 => Opcode::VFNMADD132SSZr, + 11227 => Opcode::VFNMADD132SSZr_Int, + 11228 => Opcode::VFNMADD132SSZrb, + 11229 => Opcode::VFNMADD132SSZrb_Int, + 11230 => Opcode::VFNMADD132SSZrbk_Int, + 11231 => Opcode::VFNMADD132SSZrbkz_Int, + 11232 => Opcode::VFNMADD132SSZrk_Int, + 11233 => Opcode::VFNMADD132SSZrkz_Int, + 11234 => Opcode::VFNMADD132SSm, + 11235 => Opcode::VFNMADD132SSm_Int, + 11236 => Opcode::VFNMADD132SSr, + 11237 => Opcode::VFNMADD132SSr_Int, + 11238 => Opcode::VFNMADD213BF16Z128m, + 11239 => Opcode::VFNMADD213BF16Z128mb, + 11240 => Opcode::VFNMADD213BF16Z128mbk, + 11241 => Opcode::VFNMADD213BF16Z128mbkz, + 11242 => Opcode::VFNMADD213BF16Z128mk, + 11243 => Opcode::VFNMADD213BF16Z128mkz, + 11244 => Opcode::VFNMADD213BF16Z128r, + 11245 => Opcode::VFNMADD213BF16Z128rk, + 11246 => Opcode::VFNMADD213BF16Z128rkz, + 11247 => Opcode::VFNMADD213BF16Z256m, + 11248 => Opcode::VFNMADD213BF16Z256mb, + 11249 => Opcode::VFNMADD213BF16Z256mbk, + 11250 => Opcode::VFNMADD213BF16Z256mbkz, + 11251 => Opcode::VFNMADD213BF16Z256mk, + 11252 => Opcode::VFNMADD213BF16Z256mkz, + 11253 => Opcode::VFNMADD213BF16Z256r, + 11254 => Opcode::VFNMADD213BF16Z256rk, + 11255 => Opcode::VFNMADD213BF16Z256rkz, + 11256 => Opcode::VFNMADD213BF16Zm, + 11257 => Opcode::VFNMADD213BF16Zmb, + 11258 => Opcode::VFNMADD213BF16Zmbk, + 11259 => Opcode::VFNMADD213BF16Zmbkz, + 11260 => Opcode::VFNMADD213BF16Zmk, + 11261 => Opcode::VFNMADD213BF16Zmkz, + 11262 => Opcode::VFNMADD213BF16Zr, + 11263 => Opcode::VFNMADD213BF16Zrk, + 11264 => Opcode::VFNMADD213BF16Zrkz, + 11265 => Opcode::VFNMADD213PDYm, + 11266 => Opcode::VFNMADD213PDYr, + 11267 => Opcode::VFNMADD213PDZ128m, + 11268 => Opcode::VFNMADD213PDZ128mb, + 11269 => Opcode::VFNMADD213PDZ128mbk, + 11270 => Opcode::VFNMADD213PDZ128mbkz, + 11271 => Opcode::VFNMADD213PDZ128mk, + 11272 => Opcode::VFNMADD213PDZ128mkz, + 11273 => Opcode::VFNMADD213PDZ128r, + 11274 => Opcode::VFNMADD213PDZ128rk, + 11275 => Opcode::VFNMADD213PDZ128rkz, + 11276 => Opcode::VFNMADD213PDZ256m, + 11277 => Opcode::VFNMADD213PDZ256mb, + 11278 => Opcode::VFNMADD213PDZ256mbk, + 11279 => Opcode::VFNMADD213PDZ256mbkz, + 11280 => Opcode::VFNMADD213PDZ256mk, + 11281 => Opcode::VFNMADD213PDZ256mkz, + 11282 => Opcode::VFNMADD213PDZ256r, + 11283 => Opcode::VFNMADD213PDZ256rk, + 11284 => Opcode::VFNMADD213PDZ256rkz, + 11285 => Opcode::VFNMADD213PDZm, + 11286 => Opcode::VFNMADD213PDZmb, + 11287 => Opcode::VFNMADD213PDZmbk, + 11288 => Opcode::VFNMADD213PDZmbkz, + 11289 => Opcode::VFNMADD213PDZmk, + 11290 => Opcode::VFNMADD213PDZmkz, + 11291 => Opcode::VFNMADD213PDZr, + 11292 => Opcode::VFNMADD213PDZrb, + 11293 => Opcode::VFNMADD213PDZrbk, + 11294 => Opcode::VFNMADD213PDZrbkz, + 11295 => Opcode::VFNMADD213PDZrk, + 11296 => Opcode::VFNMADD213PDZrkz, + 11297 => Opcode::VFNMADD213PDm, + 11298 => Opcode::VFNMADD213PDr, + 11299 => Opcode::VFNMADD213PHZ128m, + 11300 => Opcode::VFNMADD213PHZ128mb, + 11301 => Opcode::VFNMADD213PHZ128mbk, + 11302 => Opcode::VFNMADD213PHZ128mbkz, + 11303 => Opcode::VFNMADD213PHZ128mk, + 11304 => Opcode::VFNMADD213PHZ128mkz, + 11305 => Opcode::VFNMADD213PHZ128r, + 11306 => Opcode::VFNMADD213PHZ128rk, + 11307 => Opcode::VFNMADD213PHZ128rkz, + 11308 => Opcode::VFNMADD213PHZ256m, + 11309 => Opcode::VFNMADD213PHZ256mb, + 11310 => Opcode::VFNMADD213PHZ256mbk, + 11311 => Opcode::VFNMADD213PHZ256mbkz, + 11312 => Opcode::VFNMADD213PHZ256mk, + 11313 => Opcode::VFNMADD213PHZ256mkz, + 11314 => Opcode::VFNMADD213PHZ256r, + 11315 => Opcode::VFNMADD213PHZ256rk, + 11316 => Opcode::VFNMADD213PHZ256rkz, + 11317 => Opcode::VFNMADD213PHZm, + 11318 => Opcode::VFNMADD213PHZmb, + 11319 => Opcode::VFNMADD213PHZmbk, + 11320 => Opcode::VFNMADD213PHZmbkz, + 11321 => Opcode::VFNMADD213PHZmk, + 11322 => Opcode::VFNMADD213PHZmkz, + 11323 => Opcode::VFNMADD213PHZr, + 11324 => Opcode::VFNMADD213PHZrb, + 11325 => Opcode::VFNMADD213PHZrbk, + 11326 => Opcode::VFNMADD213PHZrbkz, + 11327 => Opcode::VFNMADD213PHZrk, + 11328 => Opcode::VFNMADD213PHZrkz, + 11329 => Opcode::VFNMADD213PSYm, + 11330 => Opcode::VFNMADD213PSYr, + 11331 => Opcode::VFNMADD213PSZ128m, + 11332 => Opcode::VFNMADD213PSZ128mb, + 11333 => Opcode::VFNMADD213PSZ128mbk, + 11334 => Opcode::VFNMADD213PSZ128mbkz, + 11335 => Opcode::VFNMADD213PSZ128mk, + 11336 => Opcode::VFNMADD213PSZ128mkz, + 11337 => Opcode::VFNMADD213PSZ128r, + 11338 => Opcode::VFNMADD213PSZ128rk, + 11339 => Opcode::VFNMADD213PSZ128rkz, + 11340 => Opcode::VFNMADD213PSZ256m, + 11341 => Opcode::VFNMADD213PSZ256mb, + 11342 => Opcode::VFNMADD213PSZ256mbk, + 11343 => Opcode::VFNMADD213PSZ256mbkz, + 11344 => Opcode::VFNMADD213PSZ256mk, + 11345 => Opcode::VFNMADD213PSZ256mkz, + 11346 => Opcode::VFNMADD213PSZ256r, + 11347 => Opcode::VFNMADD213PSZ256rk, + 11348 => Opcode::VFNMADD213PSZ256rkz, + 11349 => Opcode::VFNMADD213PSZm, + 11350 => Opcode::VFNMADD213PSZmb, + 11351 => Opcode::VFNMADD213PSZmbk, + 11352 => Opcode::VFNMADD213PSZmbkz, + 11353 => Opcode::VFNMADD213PSZmk, + 11354 => Opcode::VFNMADD213PSZmkz, + 11355 => Opcode::VFNMADD213PSZr, + 11356 => Opcode::VFNMADD213PSZrb, + 11357 => Opcode::VFNMADD213PSZrbk, + 11358 => Opcode::VFNMADD213PSZrbkz, + 11359 => Opcode::VFNMADD213PSZrk, + 11360 => Opcode::VFNMADD213PSZrkz, + 11361 => Opcode::VFNMADD213PSm, + 11362 => Opcode::VFNMADD213PSr, + 11363 => Opcode::VFNMADD213SDZm, + 11364 => Opcode::VFNMADD213SDZm_Int, + 11365 => Opcode::VFNMADD213SDZmk_Int, + 11366 => Opcode::VFNMADD213SDZmkz_Int, + 11367 => Opcode::VFNMADD213SDZr, + 11368 => Opcode::VFNMADD213SDZr_Int, + 11369 => Opcode::VFNMADD213SDZrb, + 11370 => Opcode::VFNMADD213SDZrb_Int, + 11371 => Opcode::VFNMADD213SDZrbk_Int, + 11372 => Opcode::VFNMADD213SDZrbkz_Int, + 11373 => Opcode::VFNMADD213SDZrk_Int, + 11374 => Opcode::VFNMADD213SDZrkz_Int, + 11375 => Opcode::VFNMADD213SDm, + 11376 => Opcode::VFNMADD213SDm_Int, + 11377 => Opcode::VFNMADD213SDr, + 11378 => Opcode::VFNMADD213SDr_Int, + 11379 => Opcode::VFNMADD213SHZm, + 11380 => Opcode::VFNMADD213SHZm_Int, + 11381 => Opcode::VFNMADD213SHZmk_Int, + 11382 => Opcode::VFNMADD213SHZmkz_Int, + 11383 => Opcode::VFNMADD213SHZr, + 11384 => Opcode::VFNMADD213SHZr_Int, + 11385 => Opcode::VFNMADD213SHZrb, + 11386 => Opcode::VFNMADD213SHZrb_Int, + 11387 => Opcode::VFNMADD213SHZrbk_Int, + 11388 => Opcode::VFNMADD213SHZrbkz_Int, + 11389 => Opcode::VFNMADD213SHZrk_Int, + 11390 => Opcode::VFNMADD213SHZrkz_Int, + 11391 => Opcode::VFNMADD213SSZm, + 11392 => Opcode::VFNMADD213SSZm_Int, + 11393 => Opcode::VFNMADD213SSZmk_Int, + 11394 => Opcode::VFNMADD213SSZmkz_Int, + 11395 => Opcode::VFNMADD213SSZr, + 11396 => Opcode::VFNMADD213SSZr_Int, + 11397 => Opcode::VFNMADD213SSZrb, + 11398 => Opcode::VFNMADD213SSZrb_Int, + 11399 => Opcode::VFNMADD213SSZrbk_Int, + 11400 => Opcode::VFNMADD213SSZrbkz_Int, + 11401 => Opcode::VFNMADD213SSZrk_Int, + 11402 => Opcode::VFNMADD213SSZrkz_Int, + 11403 => Opcode::VFNMADD213SSm, + 11404 => Opcode::VFNMADD213SSm_Int, + 11405 => Opcode::VFNMADD213SSr, + 11406 => Opcode::VFNMADD213SSr_Int, + 11407 => Opcode::VFNMADD231BF16Z128m, + 11408 => Opcode::VFNMADD231BF16Z128mb, + 11409 => Opcode::VFNMADD231BF16Z128mbk, + 11410 => Opcode::VFNMADD231BF16Z128mbkz, + 11411 => Opcode::VFNMADD231BF16Z128mk, + 11412 => Opcode::VFNMADD231BF16Z128mkz, + 11413 => Opcode::VFNMADD231BF16Z128r, + 11414 => Opcode::VFNMADD231BF16Z128rk, + 11415 => Opcode::VFNMADD231BF16Z128rkz, + 11416 => Opcode::VFNMADD231BF16Z256m, + 11417 => Opcode::VFNMADD231BF16Z256mb, + 11418 => Opcode::VFNMADD231BF16Z256mbk, + 11419 => Opcode::VFNMADD231BF16Z256mbkz, + 11420 => Opcode::VFNMADD231BF16Z256mk, + 11421 => Opcode::VFNMADD231BF16Z256mkz, + 11422 => Opcode::VFNMADD231BF16Z256r, + 11423 => Opcode::VFNMADD231BF16Z256rk, + 11424 => Opcode::VFNMADD231BF16Z256rkz, + 11425 => Opcode::VFNMADD231BF16Zm, + 11426 => Opcode::VFNMADD231BF16Zmb, + 11427 => Opcode::VFNMADD231BF16Zmbk, + 11428 => Opcode::VFNMADD231BF16Zmbkz, + 11429 => Opcode::VFNMADD231BF16Zmk, + 11430 => Opcode::VFNMADD231BF16Zmkz, + 11431 => Opcode::VFNMADD231BF16Zr, + 11432 => Opcode::VFNMADD231BF16Zrk, + 11433 => Opcode::VFNMADD231BF16Zrkz, + 11434 => Opcode::VFNMADD231PDYm, + 11435 => Opcode::VFNMADD231PDYr, + 11436 => Opcode::VFNMADD231PDZ128m, + 11437 => Opcode::VFNMADD231PDZ128mb, + 11438 => Opcode::VFNMADD231PDZ128mbk, + 11439 => Opcode::VFNMADD231PDZ128mbkz, + 11440 => Opcode::VFNMADD231PDZ128mk, + 11441 => Opcode::VFNMADD231PDZ128mkz, + 11442 => Opcode::VFNMADD231PDZ128r, + 11443 => Opcode::VFNMADD231PDZ128rk, + 11444 => Opcode::VFNMADD231PDZ128rkz, + 11445 => Opcode::VFNMADD231PDZ256m, + 11446 => Opcode::VFNMADD231PDZ256mb, + 11447 => Opcode::VFNMADD231PDZ256mbk, + 11448 => Opcode::VFNMADD231PDZ256mbkz, + 11449 => Opcode::VFNMADD231PDZ256mk, + 11450 => Opcode::VFNMADD231PDZ256mkz, + 11451 => Opcode::VFNMADD231PDZ256r, + 11452 => Opcode::VFNMADD231PDZ256rk, + 11453 => Opcode::VFNMADD231PDZ256rkz, + 11454 => Opcode::VFNMADD231PDZm, + 11455 => Opcode::VFNMADD231PDZmb, + 11456 => Opcode::VFNMADD231PDZmbk, + 11457 => Opcode::VFNMADD231PDZmbkz, + 11458 => Opcode::VFNMADD231PDZmk, + 11459 => Opcode::VFNMADD231PDZmkz, + 11460 => Opcode::VFNMADD231PDZr, + 11461 => Opcode::VFNMADD231PDZrb, + 11462 => Opcode::VFNMADD231PDZrbk, + 11463 => Opcode::VFNMADD231PDZrbkz, + 11464 => Opcode::VFNMADD231PDZrk, + 11465 => Opcode::VFNMADD231PDZrkz, + 11466 => Opcode::VFNMADD231PDm, + 11467 => Opcode::VFNMADD231PDr, + 11468 => Opcode::VFNMADD231PHZ128m, + 11469 => Opcode::VFNMADD231PHZ128mb, + 11470 => Opcode::VFNMADD231PHZ128mbk, + 11471 => Opcode::VFNMADD231PHZ128mbkz, + 11472 => Opcode::VFNMADD231PHZ128mk, + 11473 => Opcode::VFNMADD231PHZ128mkz, + 11474 => Opcode::VFNMADD231PHZ128r, + 11475 => Opcode::VFNMADD231PHZ128rk, + 11476 => Opcode::VFNMADD231PHZ128rkz, + 11477 => Opcode::VFNMADD231PHZ256m, + 11478 => Opcode::VFNMADD231PHZ256mb, + 11479 => Opcode::VFNMADD231PHZ256mbk, + 11480 => Opcode::VFNMADD231PHZ256mbkz, + 11481 => Opcode::VFNMADD231PHZ256mk, + 11482 => Opcode::VFNMADD231PHZ256mkz, + 11483 => Opcode::VFNMADD231PHZ256r, + 11484 => Opcode::VFNMADD231PHZ256rk, + 11485 => Opcode::VFNMADD231PHZ256rkz, + 11486 => Opcode::VFNMADD231PHZm, + 11487 => Opcode::VFNMADD231PHZmb, + 11488 => Opcode::VFNMADD231PHZmbk, + 11489 => Opcode::VFNMADD231PHZmbkz, + 11490 => Opcode::VFNMADD231PHZmk, + 11491 => Opcode::VFNMADD231PHZmkz, + 11492 => Opcode::VFNMADD231PHZr, + 11493 => Opcode::VFNMADD231PHZrb, + 11494 => Opcode::VFNMADD231PHZrbk, + 11495 => Opcode::VFNMADD231PHZrbkz, + 11496 => Opcode::VFNMADD231PHZrk, + 11497 => Opcode::VFNMADD231PHZrkz, + 11498 => Opcode::VFNMADD231PSYm, + 11499 => Opcode::VFNMADD231PSYr, + 11500 => Opcode::VFNMADD231PSZ128m, + 11501 => Opcode::VFNMADD231PSZ128mb, + 11502 => Opcode::VFNMADD231PSZ128mbk, + 11503 => Opcode::VFNMADD231PSZ128mbkz, + 11504 => Opcode::VFNMADD231PSZ128mk, + 11505 => Opcode::VFNMADD231PSZ128mkz, + 11506 => Opcode::VFNMADD231PSZ128r, + 11507 => Opcode::VFNMADD231PSZ128rk, + 11508 => Opcode::VFNMADD231PSZ128rkz, + 11509 => Opcode::VFNMADD231PSZ256m, + 11510 => Opcode::VFNMADD231PSZ256mb, + 11511 => Opcode::VFNMADD231PSZ256mbk, + 11512 => Opcode::VFNMADD231PSZ256mbkz, + 11513 => Opcode::VFNMADD231PSZ256mk, + 11514 => Opcode::VFNMADD231PSZ256mkz, + 11515 => Opcode::VFNMADD231PSZ256r, + 11516 => Opcode::VFNMADD231PSZ256rk, + 11517 => Opcode::VFNMADD231PSZ256rkz, + 11518 => Opcode::VFNMADD231PSZm, + 11519 => Opcode::VFNMADD231PSZmb, + 11520 => Opcode::VFNMADD231PSZmbk, + 11521 => Opcode::VFNMADD231PSZmbkz, + 11522 => Opcode::VFNMADD231PSZmk, + 11523 => Opcode::VFNMADD231PSZmkz, + 11524 => Opcode::VFNMADD231PSZr, + 11525 => Opcode::VFNMADD231PSZrb, + 11526 => Opcode::VFNMADD231PSZrbk, + 11527 => Opcode::VFNMADD231PSZrbkz, + 11528 => Opcode::VFNMADD231PSZrk, + 11529 => Opcode::VFNMADD231PSZrkz, + 11530 => Opcode::VFNMADD231PSm, + 11531 => Opcode::VFNMADD231PSr, + 11532 => Opcode::VFNMADD231SDZm, + 11533 => Opcode::VFNMADD231SDZm_Int, + 11534 => Opcode::VFNMADD231SDZmk_Int, + 11535 => Opcode::VFNMADD231SDZmkz_Int, + 11536 => Opcode::VFNMADD231SDZr, + 11537 => Opcode::VFNMADD231SDZr_Int, + 11538 => Opcode::VFNMADD231SDZrb, + 11539 => Opcode::VFNMADD231SDZrb_Int, + 11540 => Opcode::VFNMADD231SDZrbk_Int, + 11541 => Opcode::VFNMADD231SDZrbkz_Int, + 11542 => Opcode::VFNMADD231SDZrk_Int, + 11543 => Opcode::VFNMADD231SDZrkz_Int, + 11544 => Opcode::VFNMADD231SDm, + 11545 => Opcode::VFNMADD231SDm_Int, + 11546 => Opcode::VFNMADD231SDr, + 11547 => Opcode::VFNMADD231SDr_Int, + 11548 => Opcode::VFNMADD231SHZm, + 11549 => Opcode::VFNMADD231SHZm_Int, + 11550 => Opcode::VFNMADD231SHZmk_Int, + 11551 => Opcode::VFNMADD231SHZmkz_Int, + 11552 => Opcode::VFNMADD231SHZr, + 11553 => Opcode::VFNMADD231SHZr_Int, + 11554 => Opcode::VFNMADD231SHZrb, + 11555 => Opcode::VFNMADD231SHZrb_Int, + 11556 => Opcode::VFNMADD231SHZrbk_Int, + 11557 => Opcode::VFNMADD231SHZrbkz_Int, + 11558 => Opcode::VFNMADD231SHZrk_Int, + 11559 => Opcode::VFNMADD231SHZrkz_Int, + 11560 => Opcode::VFNMADD231SSZm, + 11561 => Opcode::VFNMADD231SSZm_Int, + 11562 => Opcode::VFNMADD231SSZmk_Int, + 11563 => Opcode::VFNMADD231SSZmkz_Int, + 11564 => Opcode::VFNMADD231SSZr, + 11565 => Opcode::VFNMADD231SSZr_Int, + 11566 => Opcode::VFNMADD231SSZrb, + 11567 => Opcode::VFNMADD231SSZrb_Int, + 11568 => Opcode::VFNMADD231SSZrbk_Int, + 11569 => Opcode::VFNMADD231SSZrbkz_Int, + 11570 => Opcode::VFNMADD231SSZrk_Int, + 11571 => Opcode::VFNMADD231SSZrkz_Int, + 11572 => Opcode::VFNMADD231SSm, + 11573 => Opcode::VFNMADD231SSm_Int, + 11574 => Opcode::VFNMADD231SSr, + 11575 => Opcode::VFNMADD231SSr_Int, + 11576 => Opcode::VFNMADDPD4Ymr, + 11577 => Opcode::VFNMADDPD4Yrm, + 11578 => Opcode::VFNMADDPD4Yrr, + 11579 => Opcode::VFNMADDPD4Yrr_REV, + 11580 => Opcode::VFNMADDPD4mr, + 11581 => Opcode::VFNMADDPD4rm, + 11582 => Opcode::VFNMADDPD4rr, + 11583 => Opcode::VFNMADDPD4rr_REV, + 11584 => Opcode::VFNMADDPS4Ymr, + 11585 => Opcode::VFNMADDPS4Yrm, + 11586 => Opcode::VFNMADDPS4Yrr, + 11587 => Opcode::VFNMADDPS4Yrr_REV, + 11588 => Opcode::VFNMADDPS4mr, + 11589 => Opcode::VFNMADDPS4rm, + 11590 => Opcode::VFNMADDPS4rr, + 11591 => Opcode::VFNMADDPS4rr_REV, + 11592 => Opcode::VFNMADDSD4mr, + 11593 => Opcode::VFNMADDSD4mr_Int, + 11594 => Opcode::VFNMADDSD4rm, + 11595 => Opcode::VFNMADDSD4rm_Int, + 11596 => Opcode::VFNMADDSD4rr, + 11597 => Opcode::VFNMADDSD4rr_Int, + 11598 => Opcode::VFNMADDSD4rr_Int_REV, + 11599 => Opcode::VFNMADDSD4rr_REV, + 11600 => Opcode::VFNMADDSS4mr, + 11601 => Opcode::VFNMADDSS4mr_Int, + 11602 => Opcode::VFNMADDSS4rm, + 11603 => Opcode::VFNMADDSS4rm_Int, + 11604 => Opcode::VFNMADDSS4rr, + 11605 => Opcode::VFNMADDSS4rr_Int, + 11606 => Opcode::VFNMADDSS4rr_Int_REV, + 11607 => Opcode::VFNMADDSS4rr_REV, + 11608 => Opcode::VFNMSUB132BF16Z128m, + 11609 => Opcode::VFNMSUB132BF16Z128mb, + 11610 => Opcode::VFNMSUB132BF16Z128mbk, + 11611 => Opcode::VFNMSUB132BF16Z128mbkz, + 11612 => Opcode::VFNMSUB132BF16Z128mk, + 11613 => Opcode::VFNMSUB132BF16Z128mkz, + 11614 => Opcode::VFNMSUB132BF16Z128r, + 11615 => Opcode::VFNMSUB132BF16Z128rk, + 11616 => Opcode::VFNMSUB132BF16Z128rkz, + 11617 => Opcode::VFNMSUB132BF16Z256m, + 11618 => Opcode::VFNMSUB132BF16Z256mb, + 11619 => Opcode::VFNMSUB132BF16Z256mbk, + 11620 => Opcode::VFNMSUB132BF16Z256mbkz, + 11621 => Opcode::VFNMSUB132BF16Z256mk, + 11622 => Opcode::VFNMSUB132BF16Z256mkz, + 11623 => Opcode::VFNMSUB132BF16Z256r, + 11624 => Opcode::VFNMSUB132BF16Z256rk, + 11625 => Opcode::VFNMSUB132BF16Z256rkz, + 11626 => Opcode::VFNMSUB132BF16Zm, + 11627 => Opcode::VFNMSUB132BF16Zmb, + 11628 => Opcode::VFNMSUB132BF16Zmbk, + 11629 => Opcode::VFNMSUB132BF16Zmbkz, + 11630 => Opcode::VFNMSUB132BF16Zmk, + 11631 => Opcode::VFNMSUB132BF16Zmkz, + 11632 => Opcode::VFNMSUB132BF16Zr, + 11633 => Opcode::VFNMSUB132BF16Zrk, + 11634 => Opcode::VFNMSUB132BF16Zrkz, + 11635 => Opcode::VFNMSUB132PDYm, + 11636 => Opcode::VFNMSUB132PDYr, + 11637 => Opcode::VFNMSUB132PDZ128m, + 11638 => Opcode::VFNMSUB132PDZ128mb, + 11639 => Opcode::VFNMSUB132PDZ128mbk, + 11640 => Opcode::VFNMSUB132PDZ128mbkz, + 11641 => Opcode::VFNMSUB132PDZ128mk, + 11642 => Opcode::VFNMSUB132PDZ128mkz, + 11643 => Opcode::VFNMSUB132PDZ128r, + 11644 => Opcode::VFNMSUB132PDZ128rk, + 11645 => Opcode::VFNMSUB132PDZ128rkz, + 11646 => Opcode::VFNMSUB132PDZ256m, + 11647 => Opcode::VFNMSUB132PDZ256mb, + 11648 => Opcode::VFNMSUB132PDZ256mbk, + 11649 => Opcode::VFNMSUB132PDZ256mbkz, + 11650 => Opcode::VFNMSUB132PDZ256mk, + 11651 => Opcode::VFNMSUB132PDZ256mkz, + 11652 => Opcode::VFNMSUB132PDZ256r, + 11653 => Opcode::VFNMSUB132PDZ256rk, + 11654 => Opcode::VFNMSUB132PDZ256rkz, + 11655 => Opcode::VFNMSUB132PDZm, + 11656 => Opcode::VFNMSUB132PDZmb, + 11657 => Opcode::VFNMSUB132PDZmbk, + 11658 => Opcode::VFNMSUB132PDZmbkz, + 11659 => Opcode::VFNMSUB132PDZmk, + 11660 => Opcode::VFNMSUB132PDZmkz, + 11661 => Opcode::VFNMSUB132PDZr, + 11662 => Opcode::VFNMSUB132PDZrb, + 11663 => Opcode::VFNMSUB132PDZrbk, + 11664 => Opcode::VFNMSUB132PDZrbkz, + 11665 => Opcode::VFNMSUB132PDZrk, + 11666 => Opcode::VFNMSUB132PDZrkz, + 11667 => Opcode::VFNMSUB132PDm, + 11668 => Opcode::VFNMSUB132PDr, + 11669 => Opcode::VFNMSUB132PHZ128m, + 11670 => Opcode::VFNMSUB132PHZ128mb, + 11671 => Opcode::VFNMSUB132PHZ128mbk, + 11672 => Opcode::VFNMSUB132PHZ128mbkz, + 11673 => Opcode::VFNMSUB132PHZ128mk, + 11674 => Opcode::VFNMSUB132PHZ128mkz, + 11675 => Opcode::VFNMSUB132PHZ128r, + 11676 => Opcode::VFNMSUB132PHZ128rk, + 11677 => Opcode::VFNMSUB132PHZ128rkz, + 11678 => Opcode::VFNMSUB132PHZ256m, + 11679 => Opcode::VFNMSUB132PHZ256mb, + 11680 => Opcode::VFNMSUB132PHZ256mbk, + 11681 => Opcode::VFNMSUB132PHZ256mbkz, + 11682 => Opcode::VFNMSUB132PHZ256mk, + 11683 => Opcode::VFNMSUB132PHZ256mkz, + 11684 => Opcode::VFNMSUB132PHZ256r, + 11685 => Opcode::VFNMSUB132PHZ256rk, + 11686 => Opcode::VFNMSUB132PHZ256rkz, + 11687 => Opcode::VFNMSUB132PHZm, + 11688 => Opcode::VFNMSUB132PHZmb, + 11689 => Opcode::VFNMSUB132PHZmbk, + 11690 => Opcode::VFNMSUB132PHZmbkz, + 11691 => Opcode::VFNMSUB132PHZmk, + 11692 => Opcode::VFNMSUB132PHZmkz, + 11693 => Opcode::VFNMSUB132PHZr, + 11694 => Opcode::VFNMSUB132PHZrb, + 11695 => Opcode::VFNMSUB132PHZrbk, + 11696 => Opcode::VFNMSUB132PHZrbkz, + 11697 => Opcode::VFNMSUB132PHZrk, + 11698 => Opcode::VFNMSUB132PHZrkz, + 11699 => Opcode::VFNMSUB132PSYm, + 11700 => Opcode::VFNMSUB132PSYr, + 11701 => Opcode::VFNMSUB132PSZ128m, + 11702 => Opcode::VFNMSUB132PSZ128mb, + 11703 => Opcode::VFNMSUB132PSZ128mbk, + 11704 => Opcode::VFNMSUB132PSZ128mbkz, + 11705 => Opcode::VFNMSUB132PSZ128mk, + 11706 => Opcode::VFNMSUB132PSZ128mkz, + 11707 => Opcode::VFNMSUB132PSZ128r, + 11708 => Opcode::VFNMSUB132PSZ128rk, + 11709 => Opcode::VFNMSUB132PSZ128rkz, + 11710 => Opcode::VFNMSUB132PSZ256m, + 11711 => Opcode::VFNMSUB132PSZ256mb, + 11712 => Opcode::VFNMSUB132PSZ256mbk, + 11713 => Opcode::VFNMSUB132PSZ256mbkz, + 11714 => Opcode::VFNMSUB132PSZ256mk, + 11715 => Opcode::VFNMSUB132PSZ256mkz, + 11716 => Opcode::VFNMSUB132PSZ256r, + 11717 => Opcode::VFNMSUB132PSZ256rk, + 11718 => Opcode::VFNMSUB132PSZ256rkz, + 11719 => Opcode::VFNMSUB132PSZm, + 11720 => Opcode::VFNMSUB132PSZmb, + 11721 => Opcode::VFNMSUB132PSZmbk, + 11722 => Opcode::VFNMSUB132PSZmbkz, + 11723 => Opcode::VFNMSUB132PSZmk, + 11724 => Opcode::VFNMSUB132PSZmkz, + 11725 => Opcode::VFNMSUB132PSZr, + 11726 => Opcode::VFNMSUB132PSZrb, + 11727 => Opcode::VFNMSUB132PSZrbk, + 11728 => Opcode::VFNMSUB132PSZrbkz, + 11729 => Opcode::VFNMSUB132PSZrk, + 11730 => Opcode::VFNMSUB132PSZrkz, + 11731 => Opcode::VFNMSUB132PSm, + 11732 => Opcode::VFNMSUB132PSr, + 11733 => Opcode::VFNMSUB132SDZm, + 11734 => Opcode::VFNMSUB132SDZm_Int, + 11735 => Opcode::VFNMSUB132SDZmk_Int, + 11736 => Opcode::VFNMSUB132SDZmkz_Int, + 11737 => Opcode::VFNMSUB132SDZr, + 11738 => Opcode::VFNMSUB132SDZr_Int, + 11739 => Opcode::VFNMSUB132SDZrb, + 11740 => Opcode::VFNMSUB132SDZrb_Int, + 11741 => Opcode::VFNMSUB132SDZrbk_Int, + 11742 => Opcode::VFNMSUB132SDZrbkz_Int, + 11743 => Opcode::VFNMSUB132SDZrk_Int, + 11744 => Opcode::VFNMSUB132SDZrkz_Int, + 11745 => Opcode::VFNMSUB132SDm, + 11746 => Opcode::VFNMSUB132SDm_Int, + 11747 => Opcode::VFNMSUB132SDr, + 11748 => Opcode::VFNMSUB132SDr_Int, + 11749 => Opcode::VFNMSUB132SHZm, + 11750 => Opcode::VFNMSUB132SHZm_Int, + 11751 => Opcode::VFNMSUB132SHZmk_Int, + 11752 => Opcode::VFNMSUB132SHZmkz_Int, + 11753 => Opcode::VFNMSUB132SHZr, + 11754 => Opcode::VFNMSUB132SHZr_Int, + 11755 => Opcode::VFNMSUB132SHZrb, + 11756 => Opcode::VFNMSUB132SHZrb_Int, + 11757 => Opcode::VFNMSUB132SHZrbk_Int, + 11758 => Opcode::VFNMSUB132SHZrbkz_Int, + 11759 => Opcode::VFNMSUB132SHZrk_Int, + 11760 => Opcode::VFNMSUB132SHZrkz_Int, + 11761 => Opcode::VFNMSUB132SSZm, + 11762 => Opcode::VFNMSUB132SSZm_Int, + 11763 => Opcode::VFNMSUB132SSZmk_Int, + 11764 => Opcode::VFNMSUB132SSZmkz_Int, + 11765 => Opcode::VFNMSUB132SSZr, + 11766 => Opcode::VFNMSUB132SSZr_Int, + 11767 => Opcode::VFNMSUB132SSZrb, + 11768 => Opcode::VFNMSUB132SSZrb_Int, + 11769 => Opcode::VFNMSUB132SSZrbk_Int, + 11770 => Opcode::VFNMSUB132SSZrbkz_Int, + 11771 => Opcode::VFNMSUB132SSZrk_Int, + 11772 => Opcode::VFNMSUB132SSZrkz_Int, + 11773 => Opcode::VFNMSUB132SSm, + 11774 => Opcode::VFNMSUB132SSm_Int, + 11775 => Opcode::VFNMSUB132SSr, + 11776 => Opcode::VFNMSUB132SSr_Int, + 11777 => Opcode::VFNMSUB213BF16Z128m, + 11778 => Opcode::VFNMSUB213BF16Z128mb, + 11779 => Opcode::VFNMSUB213BF16Z128mbk, + 11780 => Opcode::VFNMSUB213BF16Z128mbkz, + 11781 => Opcode::VFNMSUB213BF16Z128mk, + 11782 => Opcode::VFNMSUB213BF16Z128mkz, + 11783 => Opcode::VFNMSUB213BF16Z128r, + 11784 => Opcode::VFNMSUB213BF16Z128rk, + 11785 => Opcode::VFNMSUB213BF16Z128rkz, + 11786 => Opcode::VFNMSUB213BF16Z256m, + 11787 => Opcode::VFNMSUB213BF16Z256mb, + 11788 => Opcode::VFNMSUB213BF16Z256mbk, + 11789 => Opcode::VFNMSUB213BF16Z256mbkz, + 11790 => Opcode::VFNMSUB213BF16Z256mk, + 11791 => Opcode::VFNMSUB213BF16Z256mkz, + 11792 => Opcode::VFNMSUB213BF16Z256r, + 11793 => Opcode::VFNMSUB213BF16Z256rk, + 11794 => Opcode::VFNMSUB213BF16Z256rkz, + 11795 => Opcode::VFNMSUB213BF16Zm, + 11796 => Opcode::VFNMSUB213BF16Zmb, + 11797 => Opcode::VFNMSUB213BF16Zmbk, + 11798 => Opcode::VFNMSUB213BF16Zmbkz, + 11799 => Opcode::VFNMSUB213BF16Zmk, + 11800 => Opcode::VFNMSUB213BF16Zmkz, + 11801 => Opcode::VFNMSUB213BF16Zr, + 11802 => Opcode::VFNMSUB213BF16Zrk, + 11803 => Opcode::VFNMSUB213BF16Zrkz, + 11804 => Opcode::VFNMSUB213PDYm, + 11805 => Opcode::VFNMSUB213PDYr, + 11806 => Opcode::VFNMSUB213PDZ128m, + 11807 => Opcode::VFNMSUB213PDZ128mb, + 11808 => Opcode::VFNMSUB213PDZ128mbk, + 11809 => Opcode::VFNMSUB213PDZ128mbkz, + 11810 => Opcode::VFNMSUB213PDZ128mk, + 11811 => Opcode::VFNMSUB213PDZ128mkz, + 11812 => Opcode::VFNMSUB213PDZ128r, + 11813 => Opcode::VFNMSUB213PDZ128rk, + 11814 => Opcode::VFNMSUB213PDZ128rkz, + 11815 => Opcode::VFNMSUB213PDZ256m, + 11816 => Opcode::VFNMSUB213PDZ256mb, + 11817 => Opcode::VFNMSUB213PDZ256mbk, + 11818 => Opcode::VFNMSUB213PDZ256mbkz, + 11819 => Opcode::VFNMSUB213PDZ256mk, + 11820 => Opcode::VFNMSUB213PDZ256mkz, + 11821 => Opcode::VFNMSUB213PDZ256r, + 11822 => Opcode::VFNMSUB213PDZ256rk, + 11823 => Opcode::VFNMSUB213PDZ256rkz, + 11824 => Opcode::VFNMSUB213PDZm, + 11825 => Opcode::VFNMSUB213PDZmb, + 11826 => Opcode::VFNMSUB213PDZmbk, + 11827 => Opcode::VFNMSUB213PDZmbkz, + 11828 => Opcode::VFNMSUB213PDZmk, + 11829 => Opcode::VFNMSUB213PDZmkz, + 11830 => Opcode::VFNMSUB213PDZr, + 11831 => Opcode::VFNMSUB213PDZrb, + 11832 => Opcode::VFNMSUB213PDZrbk, + 11833 => Opcode::VFNMSUB213PDZrbkz, + 11834 => Opcode::VFNMSUB213PDZrk, + 11835 => Opcode::VFNMSUB213PDZrkz, + 11836 => Opcode::VFNMSUB213PDm, + 11837 => Opcode::VFNMSUB213PDr, + 11838 => Opcode::VFNMSUB213PHZ128m, + 11839 => Opcode::VFNMSUB213PHZ128mb, + 11840 => Opcode::VFNMSUB213PHZ128mbk, + 11841 => Opcode::VFNMSUB213PHZ128mbkz, + 11842 => Opcode::VFNMSUB213PHZ128mk, + 11843 => Opcode::VFNMSUB213PHZ128mkz, + 11844 => Opcode::VFNMSUB213PHZ128r, + 11845 => Opcode::VFNMSUB213PHZ128rk, + 11846 => Opcode::VFNMSUB213PHZ128rkz, + 11847 => Opcode::VFNMSUB213PHZ256m, + 11848 => Opcode::VFNMSUB213PHZ256mb, + 11849 => Opcode::VFNMSUB213PHZ256mbk, + 11850 => Opcode::VFNMSUB213PHZ256mbkz, + 11851 => Opcode::VFNMSUB213PHZ256mk, + 11852 => Opcode::VFNMSUB213PHZ256mkz, + 11853 => Opcode::VFNMSUB213PHZ256r, + 11854 => Opcode::VFNMSUB213PHZ256rk, + 11855 => Opcode::VFNMSUB213PHZ256rkz, + 11856 => Opcode::VFNMSUB213PHZm, + 11857 => Opcode::VFNMSUB213PHZmb, + 11858 => Opcode::VFNMSUB213PHZmbk, + 11859 => Opcode::VFNMSUB213PHZmbkz, + 11860 => Opcode::VFNMSUB213PHZmk, + 11861 => Opcode::VFNMSUB213PHZmkz, + 11862 => Opcode::VFNMSUB213PHZr, + 11863 => Opcode::VFNMSUB213PHZrb, + 11864 => Opcode::VFNMSUB213PHZrbk, + 11865 => Opcode::VFNMSUB213PHZrbkz, + 11866 => Opcode::VFNMSUB213PHZrk, + 11867 => Opcode::VFNMSUB213PHZrkz, + 11868 => Opcode::VFNMSUB213PSYm, + 11869 => Opcode::VFNMSUB213PSYr, + 11870 => Opcode::VFNMSUB213PSZ128m, + 11871 => Opcode::VFNMSUB213PSZ128mb, + 11872 => Opcode::VFNMSUB213PSZ128mbk, + 11873 => Opcode::VFNMSUB213PSZ128mbkz, + 11874 => Opcode::VFNMSUB213PSZ128mk, + 11875 => Opcode::VFNMSUB213PSZ128mkz, + 11876 => Opcode::VFNMSUB213PSZ128r, + 11877 => Opcode::VFNMSUB213PSZ128rk, + 11878 => Opcode::VFNMSUB213PSZ128rkz, + 11879 => Opcode::VFNMSUB213PSZ256m, + 11880 => Opcode::VFNMSUB213PSZ256mb, + 11881 => Opcode::VFNMSUB213PSZ256mbk, + 11882 => Opcode::VFNMSUB213PSZ256mbkz, + 11883 => Opcode::VFNMSUB213PSZ256mk, + 11884 => Opcode::VFNMSUB213PSZ256mkz, + 11885 => Opcode::VFNMSUB213PSZ256r, + 11886 => Opcode::VFNMSUB213PSZ256rk, + 11887 => Opcode::VFNMSUB213PSZ256rkz, + 11888 => Opcode::VFNMSUB213PSZm, + 11889 => Opcode::VFNMSUB213PSZmb, + 11890 => Opcode::VFNMSUB213PSZmbk, + 11891 => Opcode::VFNMSUB213PSZmbkz, + 11892 => Opcode::VFNMSUB213PSZmk, + 11893 => Opcode::VFNMSUB213PSZmkz, + 11894 => Opcode::VFNMSUB213PSZr, + 11895 => Opcode::VFNMSUB213PSZrb, + 11896 => Opcode::VFNMSUB213PSZrbk, + 11897 => Opcode::VFNMSUB213PSZrbkz, + 11898 => Opcode::VFNMSUB213PSZrk, + 11899 => Opcode::VFNMSUB213PSZrkz, + 11900 => Opcode::VFNMSUB213PSm, + 11901 => Opcode::VFNMSUB213PSr, + 11902 => Opcode::VFNMSUB213SDZm, + 11903 => Opcode::VFNMSUB213SDZm_Int, + 11904 => Opcode::VFNMSUB213SDZmk_Int, + 11905 => Opcode::VFNMSUB213SDZmkz_Int, + 11906 => Opcode::VFNMSUB213SDZr, + 11907 => Opcode::VFNMSUB213SDZr_Int, + 11908 => Opcode::VFNMSUB213SDZrb, + 11909 => Opcode::VFNMSUB213SDZrb_Int, + 11910 => Opcode::VFNMSUB213SDZrbk_Int, + 11911 => Opcode::VFNMSUB213SDZrbkz_Int, + 11912 => Opcode::VFNMSUB213SDZrk_Int, + 11913 => Opcode::VFNMSUB213SDZrkz_Int, + 11914 => Opcode::VFNMSUB213SDm, + 11915 => Opcode::VFNMSUB213SDm_Int, + 11916 => Opcode::VFNMSUB213SDr, + 11917 => Opcode::VFNMSUB213SDr_Int, + 11918 => Opcode::VFNMSUB213SHZm, + 11919 => Opcode::VFNMSUB213SHZm_Int, + 11920 => Opcode::VFNMSUB213SHZmk_Int, + 11921 => Opcode::VFNMSUB213SHZmkz_Int, + 11922 => Opcode::VFNMSUB213SHZr, + 11923 => Opcode::VFNMSUB213SHZr_Int, + 11924 => Opcode::VFNMSUB213SHZrb, + 11925 => Opcode::VFNMSUB213SHZrb_Int, + 11926 => Opcode::VFNMSUB213SHZrbk_Int, + 11927 => Opcode::VFNMSUB213SHZrbkz_Int, + 11928 => Opcode::VFNMSUB213SHZrk_Int, + 11929 => Opcode::VFNMSUB213SHZrkz_Int, + 11930 => Opcode::VFNMSUB213SSZm, + 11931 => Opcode::VFNMSUB213SSZm_Int, + 11932 => Opcode::VFNMSUB213SSZmk_Int, + 11933 => Opcode::VFNMSUB213SSZmkz_Int, + 11934 => Opcode::VFNMSUB213SSZr, + 11935 => Opcode::VFNMSUB213SSZr_Int, + 11936 => Opcode::VFNMSUB213SSZrb, + 11937 => Opcode::VFNMSUB213SSZrb_Int, + 11938 => Opcode::VFNMSUB213SSZrbk_Int, + 11939 => Opcode::VFNMSUB213SSZrbkz_Int, + 11940 => Opcode::VFNMSUB213SSZrk_Int, + 11941 => Opcode::VFNMSUB213SSZrkz_Int, + 11942 => Opcode::VFNMSUB213SSm, + 11943 => Opcode::VFNMSUB213SSm_Int, + 11944 => Opcode::VFNMSUB213SSr, + 11945 => Opcode::VFNMSUB213SSr_Int, + 11946 => Opcode::VFNMSUB231BF16Z128m, + 11947 => Opcode::VFNMSUB231BF16Z128mb, + 11948 => Opcode::VFNMSUB231BF16Z128mbk, + 11949 => Opcode::VFNMSUB231BF16Z128mbkz, + 11950 => Opcode::VFNMSUB231BF16Z128mk, + 11951 => Opcode::VFNMSUB231BF16Z128mkz, + 11952 => Opcode::VFNMSUB231BF16Z128r, + 11953 => Opcode::VFNMSUB231BF16Z128rk, + 11954 => Opcode::VFNMSUB231BF16Z128rkz, + 11955 => Opcode::VFNMSUB231BF16Z256m, + 11956 => Opcode::VFNMSUB231BF16Z256mb, + 11957 => Opcode::VFNMSUB231BF16Z256mbk, + 11958 => Opcode::VFNMSUB231BF16Z256mbkz, + 11959 => Opcode::VFNMSUB231BF16Z256mk, + 11960 => Opcode::VFNMSUB231BF16Z256mkz, + 11961 => Opcode::VFNMSUB231BF16Z256r, + 11962 => Opcode::VFNMSUB231BF16Z256rk, + 11963 => Opcode::VFNMSUB231BF16Z256rkz, + 11964 => Opcode::VFNMSUB231BF16Zm, + 11965 => Opcode::VFNMSUB231BF16Zmb, + 11966 => Opcode::VFNMSUB231BF16Zmbk, + 11967 => Opcode::VFNMSUB231BF16Zmbkz, + 11968 => Opcode::VFNMSUB231BF16Zmk, + 11969 => Opcode::VFNMSUB231BF16Zmkz, + 11970 => Opcode::VFNMSUB231BF16Zr, + 11971 => Opcode::VFNMSUB231BF16Zrk, + 11972 => Opcode::VFNMSUB231BF16Zrkz, + 11973 => Opcode::VFNMSUB231PDYm, + 11974 => Opcode::VFNMSUB231PDYr, + 11975 => Opcode::VFNMSUB231PDZ128m, + 11976 => Opcode::VFNMSUB231PDZ128mb, + 11977 => Opcode::VFNMSUB231PDZ128mbk, + 11978 => Opcode::VFNMSUB231PDZ128mbkz, + 11979 => Opcode::VFNMSUB231PDZ128mk, + 11980 => Opcode::VFNMSUB231PDZ128mkz, + 11981 => Opcode::VFNMSUB231PDZ128r, + 11982 => Opcode::VFNMSUB231PDZ128rk, + 11983 => Opcode::VFNMSUB231PDZ128rkz, + 11984 => Opcode::VFNMSUB231PDZ256m, + 11985 => Opcode::VFNMSUB231PDZ256mb, + 11986 => Opcode::VFNMSUB231PDZ256mbk, + 11987 => Opcode::VFNMSUB231PDZ256mbkz, + 11988 => Opcode::VFNMSUB231PDZ256mk, + 11989 => Opcode::VFNMSUB231PDZ256mkz, + 11990 => Opcode::VFNMSUB231PDZ256r, + 11991 => Opcode::VFNMSUB231PDZ256rk, + 11992 => Opcode::VFNMSUB231PDZ256rkz, + 11993 => Opcode::VFNMSUB231PDZm, + 11994 => Opcode::VFNMSUB231PDZmb, + 11995 => Opcode::VFNMSUB231PDZmbk, + 11996 => Opcode::VFNMSUB231PDZmbkz, + 11997 => Opcode::VFNMSUB231PDZmk, + 11998 => Opcode::VFNMSUB231PDZmkz, + 11999 => Opcode::VFNMSUB231PDZr, + 12000 => Opcode::VFNMSUB231PDZrb, + 12001 => Opcode::VFNMSUB231PDZrbk, + 12002 => Opcode::VFNMSUB231PDZrbkz, + 12003 => Opcode::VFNMSUB231PDZrk, + 12004 => Opcode::VFNMSUB231PDZrkz, + 12005 => Opcode::VFNMSUB231PDm, + 12006 => Opcode::VFNMSUB231PDr, + 12007 => Opcode::VFNMSUB231PHZ128m, + 12008 => Opcode::VFNMSUB231PHZ128mb, + 12009 => Opcode::VFNMSUB231PHZ128mbk, + 12010 => Opcode::VFNMSUB231PHZ128mbkz, + 12011 => Opcode::VFNMSUB231PHZ128mk, + 12012 => Opcode::VFNMSUB231PHZ128mkz, + 12013 => Opcode::VFNMSUB231PHZ128r, + 12014 => Opcode::VFNMSUB231PHZ128rk, + 12015 => Opcode::VFNMSUB231PHZ128rkz, + 12016 => Opcode::VFNMSUB231PHZ256m, + 12017 => Opcode::VFNMSUB231PHZ256mb, + 12018 => Opcode::VFNMSUB231PHZ256mbk, + 12019 => Opcode::VFNMSUB231PHZ256mbkz, + 12020 => Opcode::VFNMSUB231PHZ256mk, + 12021 => Opcode::VFNMSUB231PHZ256mkz, + 12022 => Opcode::VFNMSUB231PHZ256r, + 12023 => Opcode::VFNMSUB231PHZ256rk, + 12024 => Opcode::VFNMSUB231PHZ256rkz, + 12025 => Opcode::VFNMSUB231PHZm, + 12026 => Opcode::VFNMSUB231PHZmb, + 12027 => Opcode::VFNMSUB231PHZmbk, + 12028 => Opcode::VFNMSUB231PHZmbkz, + 12029 => Opcode::VFNMSUB231PHZmk, + 12030 => Opcode::VFNMSUB231PHZmkz, + 12031 => Opcode::VFNMSUB231PHZr, + 12032 => Opcode::VFNMSUB231PHZrb, + 12033 => Opcode::VFNMSUB231PHZrbk, + 12034 => Opcode::VFNMSUB231PHZrbkz, + 12035 => Opcode::VFNMSUB231PHZrk, + 12036 => Opcode::VFNMSUB231PHZrkz, + 12037 => Opcode::VFNMSUB231PSYm, + 12038 => Opcode::VFNMSUB231PSYr, + 12039 => Opcode::VFNMSUB231PSZ128m, + 12040 => Opcode::VFNMSUB231PSZ128mb, + 12041 => Opcode::VFNMSUB231PSZ128mbk, + 12042 => Opcode::VFNMSUB231PSZ128mbkz, + 12043 => Opcode::VFNMSUB231PSZ128mk, + 12044 => Opcode::VFNMSUB231PSZ128mkz, + 12045 => Opcode::VFNMSUB231PSZ128r, + 12046 => Opcode::VFNMSUB231PSZ128rk, + 12047 => Opcode::VFNMSUB231PSZ128rkz, + 12048 => Opcode::VFNMSUB231PSZ256m, + 12049 => Opcode::VFNMSUB231PSZ256mb, + 12050 => Opcode::VFNMSUB231PSZ256mbk, + 12051 => Opcode::VFNMSUB231PSZ256mbkz, + 12052 => Opcode::VFNMSUB231PSZ256mk, + 12053 => Opcode::VFNMSUB231PSZ256mkz, + 12054 => Opcode::VFNMSUB231PSZ256r, + 12055 => Opcode::VFNMSUB231PSZ256rk, + 12056 => Opcode::VFNMSUB231PSZ256rkz, + 12057 => Opcode::VFNMSUB231PSZm, + 12058 => Opcode::VFNMSUB231PSZmb, + 12059 => Opcode::VFNMSUB231PSZmbk, + 12060 => Opcode::VFNMSUB231PSZmbkz, + 12061 => Opcode::VFNMSUB231PSZmk, + 12062 => Opcode::VFNMSUB231PSZmkz, + 12063 => Opcode::VFNMSUB231PSZr, + 12064 => Opcode::VFNMSUB231PSZrb, + 12065 => Opcode::VFNMSUB231PSZrbk, + 12066 => Opcode::VFNMSUB231PSZrbkz, + 12067 => Opcode::VFNMSUB231PSZrk, + 12068 => Opcode::VFNMSUB231PSZrkz, + 12069 => Opcode::VFNMSUB231PSm, + 12070 => Opcode::VFNMSUB231PSr, + 12071 => Opcode::VFNMSUB231SDZm, + 12072 => Opcode::VFNMSUB231SDZm_Int, + 12073 => Opcode::VFNMSUB231SDZmk_Int, + 12074 => Opcode::VFNMSUB231SDZmkz_Int, + 12075 => Opcode::VFNMSUB231SDZr, + 12076 => Opcode::VFNMSUB231SDZr_Int, + 12077 => Opcode::VFNMSUB231SDZrb, + 12078 => Opcode::VFNMSUB231SDZrb_Int, + 12079 => Opcode::VFNMSUB231SDZrbk_Int, + 12080 => Opcode::VFNMSUB231SDZrbkz_Int, + 12081 => Opcode::VFNMSUB231SDZrk_Int, + 12082 => Opcode::VFNMSUB231SDZrkz_Int, + 12083 => Opcode::VFNMSUB231SDm, + 12084 => Opcode::VFNMSUB231SDm_Int, + 12085 => Opcode::VFNMSUB231SDr, + 12086 => Opcode::VFNMSUB231SDr_Int, + 12087 => Opcode::VFNMSUB231SHZm, + 12088 => Opcode::VFNMSUB231SHZm_Int, + 12089 => Opcode::VFNMSUB231SHZmk_Int, + 12090 => Opcode::VFNMSUB231SHZmkz_Int, + 12091 => Opcode::VFNMSUB231SHZr, + 12092 => Opcode::VFNMSUB231SHZr_Int, + 12093 => Opcode::VFNMSUB231SHZrb, + 12094 => Opcode::VFNMSUB231SHZrb_Int, + 12095 => Opcode::VFNMSUB231SHZrbk_Int, + 12096 => Opcode::VFNMSUB231SHZrbkz_Int, + 12097 => Opcode::VFNMSUB231SHZrk_Int, + 12098 => Opcode::VFNMSUB231SHZrkz_Int, + 12099 => Opcode::VFNMSUB231SSZm, + 12100 => Opcode::VFNMSUB231SSZm_Int, + 12101 => Opcode::VFNMSUB231SSZmk_Int, + 12102 => Opcode::VFNMSUB231SSZmkz_Int, + 12103 => Opcode::VFNMSUB231SSZr, + 12104 => Opcode::VFNMSUB231SSZr_Int, + 12105 => Opcode::VFNMSUB231SSZrb, + 12106 => Opcode::VFNMSUB231SSZrb_Int, + 12107 => Opcode::VFNMSUB231SSZrbk_Int, + 12108 => Opcode::VFNMSUB231SSZrbkz_Int, + 12109 => Opcode::VFNMSUB231SSZrk_Int, + 12110 => Opcode::VFNMSUB231SSZrkz_Int, + 12111 => Opcode::VFNMSUB231SSm, + 12112 => Opcode::VFNMSUB231SSm_Int, + 12113 => Opcode::VFNMSUB231SSr, + 12114 => Opcode::VFNMSUB231SSr_Int, + 12115 => Opcode::VFNMSUBPD4Ymr, + 12116 => Opcode::VFNMSUBPD4Yrm, + 12117 => Opcode::VFNMSUBPD4Yrr, + 12118 => Opcode::VFNMSUBPD4Yrr_REV, + 12119 => Opcode::VFNMSUBPD4mr, + 12120 => Opcode::VFNMSUBPD4rm, + 12121 => Opcode::VFNMSUBPD4rr, + 12122 => Opcode::VFNMSUBPD4rr_REV, + 12123 => Opcode::VFNMSUBPS4Ymr, + 12124 => Opcode::VFNMSUBPS4Yrm, + 12125 => Opcode::VFNMSUBPS4Yrr, + 12126 => Opcode::VFNMSUBPS4Yrr_REV, + 12127 => Opcode::VFNMSUBPS4mr, + 12128 => Opcode::VFNMSUBPS4rm, + 12129 => Opcode::VFNMSUBPS4rr, + 12130 => Opcode::VFNMSUBPS4rr_REV, + 12131 => Opcode::VFNMSUBSD4mr, + 12132 => Opcode::VFNMSUBSD4mr_Int, + 12133 => Opcode::VFNMSUBSD4rm, + 12134 => Opcode::VFNMSUBSD4rm_Int, + 12135 => Opcode::VFNMSUBSD4rr, + 12136 => Opcode::VFNMSUBSD4rr_Int, + 12137 => Opcode::VFNMSUBSD4rr_Int_REV, + 12138 => Opcode::VFNMSUBSD4rr_REV, + 12139 => Opcode::VFNMSUBSS4mr, + 12140 => Opcode::VFNMSUBSS4mr_Int, + 12141 => Opcode::VFNMSUBSS4rm, + 12142 => Opcode::VFNMSUBSS4rm_Int, + 12143 => Opcode::VFNMSUBSS4rr, + 12144 => Opcode::VFNMSUBSS4rr_Int, + 12145 => Opcode::VFNMSUBSS4rr_Int_REV, + 12146 => Opcode::VFNMSUBSS4rr_REV, + 12147 => Opcode::VFPCLASSBF16Z128mbi, + 12148 => Opcode::VFPCLASSBF16Z128mbik, + 12149 => Opcode::VFPCLASSBF16Z128mi, + 12150 => Opcode::VFPCLASSBF16Z128mik, + 12151 => Opcode::VFPCLASSBF16Z128ri, + 12152 => Opcode::VFPCLASSBF16Z128rik, + 12153 => Opcode::VFPCLASSBF16Z256mbi, + 12154 => Opcode::VFPCLASSBF16Z256mbik, + 12155 => Opcode::VFPCLASSBF16Z256mi, + 12156 => Opcode::VFPCLASSBF16Z256mik, + 12157 => Opcode::VFPCLASSBF16Z256ri, + 12158 => Opcode::VFPCLASSBF16Z256rik, + 12159 => Opcode::VFPCLASSBF16Zmbi, + 12160 => Opcode::VFPCLASSBF16Zmbik, + 12161 => Opcode::VFPCLASSBF16Zmi, + 12162 => Opcode::VFPCLASSBF16Zmik, + 12163 => Opcode::VFPCLASSBF16Zri, + 12164 => Opcode::VFPCLASSBF16Zrik, + 12165 => Opcode::VFPCLASSPDZ128mbi, + 12166 => Opcode::VFPCLASSPDZ128mbik, + 12167 => Opcode::VFPCLASSPDZ128mi, + 12168 => Opcode::VFPCLASSPDZ128mik, + 12169 => Opcode::VFPCLASSPDZ128ri, + 12170 => Opcode::VFPCLASSPDZ128rik, + 12171 => Opcode::VFPCLASSPDZ256mbi, + 12172 => Opcode::VFPCLASSPDZ256mbik, + 12173 => Opcode::VFPCLASSPDZ256mi, + 12174 => Opcode::VFPCLASSPDZ256mik, + 12175 => Opcode::VFPCLASSPDZ256ri, + 12176 => Opcode::VFPCLASSPDZ256rik, + 12177 => Opcode::VFPCLASSPDZmbi, + 12178 => Opcode::VFPCLASSPDZmbik, + 12179 => Opcode::VFPCLASSPDZmi, + 12180 => Opcode::VFPCLASSPDZmik, + 12181 => Opcode::VFPCLASSPDZri, + 12182 => Opcode::VFPCLASSPDZrik, + 12183 => Opcode::VFPCLASSPHZ128mbi, + 12184 => Opcode::VFPCLASSPHZ128mbik, + 12185 => Opcode::VFPCLASSPHZ128mi, + 12186 => Opcode::VFPCLASSPHZ128mik, + 12187 => Opcode::VFPCLASSPHZ128ri, + 12188 => Opcode::VFPCLASSPHZ128rik, + 12189 => Opcode::VFPCLASSPHZ256mbi, + 12190 => Opcode::VFPCLASSPHZ256mbik, + 12191 => Opcode::VFPCLASSPHZ256mi, + 12192 => Opcode::VFPCLASSPHZ256mik, + 12193 => Opcode::VFPCLASSPHZ256ri, + 12194 => Opcode::VFPCLASSPHZ256rik, + 12195 => Opcode::VFPCLASSPHZmbi, + 12196 => Opcode::VFPCLASSPHZmbik, + 12197 => Opcode::VFPCLASSPHZmi, + 12198 => Opcode::VFPCLASSPHZmik, + 12199 => Opcode::VFPCLASSPHZri, + 12200 => Opcode::VFPCLASSPHZrik, + 12201 => Opcode::VFPCLASSPSZ128mbi, + 12202 => Opcode::VFPCLASSPSZ128mbik, + 12203 => Opcode::VFPCLASSPSZ128mi, + 12204 => Opcode::VFPCLASSPSZ128mik, + 12205 => Opcode::VFPCLASSPSZ128ri, + 12206 => Opcode::VFPCLASSPSZ128rik, + 12207 => Opcode::VFPCLASSPSZ256mbi, + 12208 => Opcode::VFPCLASSPSZ256mbik, + 12209 => Opcode::VFPCLASSPSZ256mi, + 12210 => Opcode::VFPCLASSPSZ256mik, + 12211 => Opcode::VFPCLASSPSZ256ri, + 12212 => Opcode::VFPCLASSPSZ256rik, + 12213 => Opcode::VFPCLASSPSZmbi, + 12214 => Opcode::VFPCLASSPSZmbik, + 12215 => Opcode::VFPCLASSPSZmi, + 12216 => Opcode::VFPCLASSPSZmik, + 12217 => Opcode::VFPCLASSPSZri, + 12218 => Opcode::VFPCLASSPSZrik, + 12219 => Opcode::VFPCLASSSDZmi, + 12220 => Opcode::VFPCLASSSDZmik, + 12221 => Opcode::VFPCLASSSDZri, + 12222 => Opcode::VFPCLASSSDZrik, + 12223 => Opcode::VFPCLASSSHZmi, + 12224 => Opcode::VFPCLASSSHZmik, + 12225 => Opcode::VFPCLASSSHZri, + 12226 => Opcode::VFPCLASSSHZrik, + 12227 => Opcode::VFPCLASSSSZmi, + 12228 => Opcode::VFPCLASSSSZmik, + 12229 => Opcode::VFPCLASSSSZri, + 12230 => Opcode::VFPCLASSSSZrik, + 12231 => Opcode::VFRCZPDYrm, + 12232 => Opcode::VFRCZPDYrr, + 12233 => Opcode::VFRCZPDrm, + 12234 => Opcode::VFRCZPDrr, + 12235 => Opcode::VFRCZPSYrm, + 12236 => Opcode::VFRCZPSYrr, + 12237 => Opcode::VFRCZPSrm, + 12238 => Opcode::VFRCZPSrr, + 12239 => Opcode::VFRCZSDrm, + 12240 => Opcode::VFRCZSDrr, + 12241 => Opcode::VFRCZSSrm, + 12242 => Opcode::VFRCZSSrr, + 12243 => Opcode::VGATHERDPDYrm, + 12244 => Opcode::VGATHERDPDZ128rm, + 12245 => Opcode::VGATHERDPDZ256rm, + 12246 => Opcode::VGATHERDPDZrm, + 12247 => Opcode::VGATHERDPDrm, + 12248 => Opcode::VGATHERDPSYrm, + 12249 => Opcode::VGATHERDPSZ128rm, + 12250 => Opcode::VGATHERDPSZ256rm, + 12251 => Opcode::VGATHERDPSZrm, + 12252 => Opcode::VGATHERDPSrm, + 12253 => Opcode::VGATHERPF0DPDm, + 12254 => Opcode::VGATHERPF0DPSm, + 12255 => Opcode::VGATHERPF0QPDm, + 12256 => Opcode::VGATHERPF0QPSm, + 12257 => Opcode::VGATHERPF1DPDm, + 12258 => Opcode::VGATHERPF1DPSm, + 12259 => Opcode::VGATHERPF1QPDm, + 12260 => Opcode::VGATHERPF1QPSm, + 12261 => Opcode::VGATHERQPDYrm, + 12262 => Opcode::VGATHERQPDZ128rm, + 12263 => Opcode::VGATHERQPDZ256rm, + 12264 => Opcode::VGATHERQPDZrm, + 12265 => Opcode::VGATHERQPDrm, + 12266 => Opcode::VGATHERQPSYrm, + 12267 => Opcode::VGATHERQPSZ128rm, + 12268 => Opcode::VGATHERQPSZ256rm, + 12269 => Opcode::VGATHERQPSZrm, + 12270 => Opcode::VGATHERQPSrm, + 12271 => Opcode::VGETEXPBF16Z128m, + 12272 => Opcode::VGETEXPBF16Z128mb, + 12273 => Opcode::VGETEXPBF16Z128mbk, + 12274 => Opcode::VGETEXPBF16Z128mbkz, + 12275 => Opcode::VGETEXPBF16Z128mk, + 12276 => Opcode::VGETEXPBF16Z128mkz, + 12277 => Opcode::VGETEXPBF16Z128r, + 12278 => Opcode::VGETEXPBF16Z128rk, + 12279 => Opcode::VGETEXPBF16Z128rkz, + 12280 => Opcode::VGETEXPBF16Z256m, + 12281 => Opcode::VGETEXPBF16Z256mb, + 12282 => Opcode::VGETEXPBF16Z256mbk, + 12283 => Opcode::VGETEXPBF16Z256mbkz, + 12284 => Opcode::VGETEXPBF16Z256mk, + 12285 => Opcode::VGETEXPBF16Z256mkz, + 12286 => Opcode::VGETEXPBF16Z256r, + 12287 => Opcode::VGETEXPBF16Z256rk, + 12288 => Opcode::VGETEXPBF16Z256rkz, + 12289 => Opcode::VGETEXPBF16Zm, + 12290 => Opcode::VGETEXPBF16Zmb, + 12291 => Opcode::VGETEXPBF16Zmbk, + 12292 => Opcode::VGETEXPBF16Zmbkz, + 12293 => Opcode::VGETEXPBF16Zmk, + 12294 => Opcode::VGETEXPBF16Zmkz, + 12295 => Opcode::VGETEXPBF16Zr, + 12296 => Opcode::VGETEXPBF16Zrk, + 12297 => Opcode::VGETEXPBF16Zrkz, + 12298 => Opcode::VGETEXPPDZ128m, + 12299 => Opcode::VGETEXPPDZ128mb, + 12300 => Opcode::VGETEXPPDZ128mbk, + 12301 => Opcode::VGETEXPPDZ128mbkz, + 12302 => Opcode::VGETEXPPDZ128mk, + 12303 => Opcode::VGETEXPPDZ128mkz, + 12304 => Opcode::VGETEXPPDZ128r, + 12305 => Opcode::VGETEXPPDZ128rk, + 12306 => Opcode::VGETEXPPDZ128rkz, + 12307 => Opcode::VGETEXPPDZ256m, + 12308 => Opcode::VGETEXPPDZ256mb, + 12309 => Opcode::VGETEXPPDZ256mbk, + 12310 => Opcode::VGETEXPPDZ256mbkz, + 12311 => Opcode::VGETEXPPDZ256mk, + 12312 => Opcode::VGETEXPPDZ256mkz, + 12313 => Opcode::VGETEXPPDZ256r, + 12314 => Opcode::VGETEXPPDZ256rk, + 12315 => Opcode::VGETEXPPDZ256rkz, + 12316 => Opcode::VGETEXPPDZm, + 12317 => Opcode::VGETEXPPDZmb, + 12318 => Opcode::VGETEXPPDZmbk, + 12319 => Opcode::VGETEXPPDZmbkz, + 12320 => Opcode::VGETEXPPDZmk, + 12321 => Opcode::VGETEXPPDZmkz, + 12322 => Opcode::VGETEXPPDZr, + 12323 => Opcode::VGETEXPPDZrb, + 12324 => Opcode::VGETEXPPDZrbk, + 12325 => Opcode::VGETEXPPDZrbkz, + 12326 => Opcode::VGETEXPPDZrk, + 12327 => Opcode::VGETEXPPDZrkz, + 12328 => Opcode::VGETEXPPHZ128m, + 12329 => Opcode::VGETEXPPHZ128mb, + 12330 => Opcode::VGETEXPPHZ128mbk, + 12331 => Opcode::VGETEXPPHZ128mbkz, + 12332 => Opcode::VGETEXPPHZ128mk, + 12333 => Opcode::VGETEXPPHZ128mkz, + 12334 => Opcode::VGETEXPPHZ128r, + 12335 => Opcode::VGETEXPPHZ128rk, + 12336 => Opcode::VGETEXPPHZ128rkz, + 12337 => Opcode::VGETEXPPHZ256m, + 12338 => Opcode::VGETEXPPHZ256mb, + 12339 => Opcode::VGETEXPPHZ256mbk, + 12340 => Opcode::VGETEXPPHZ256mbkz, + 12341 => Opcode::VGETEXPPHZ256mk, + 12342 => Opcode::VGETEXPPHZ256mkz, + 12343 => Opcode::VGETEXPPHZ256r, + 12344 => Opcode::VGETEXPPHZ256rk, + 12345 => Opcode::VGETEXPPHZ256rkz, + 12346 => Opcode::VGETEXPPHZm, + 12347 => Opcode::VGETEXPPHZmb, + 12348 => Opcode::VGETEXPPHZmbk, + 12349 => Opcode::VGETEXPPHZmbkz, + 12350 => Opcode::VGETEXPPHZmk, + 12351 => Opcode::VGETEXPPHZmkz, + 12352 => Opcode::VGETEXPPHZr, + 12353 => Opcode::VGETEXPPHZrb, + 12354 => Opcode::VGETEXPPHZrbk, + 12355 => Opcode::VGETEXPPHZrbkz, + 12356 => Opcode::VGETEXPPHZrk, + 12357 => Opcode::VGETEXPPHZrkz, + 12358 => Opcode::VGETEXPPSZ128m, + 12359 => Opcode::VGETEXPPSZ128mb, + 12360 => Opcode::VGETEXPPSZ128mbk, + 12361 => Opcode::VGETEXPPSZ128mbkz, + 12362 => Opcode::VGETEXPPSZ128mk, + 12363 => Opcode::VGETEXPPSZ128mkz, + 12364 => Opcode::VGETEXPPSZ128r, + 12365 => Opcode::VGETEXPPSZ128rk, + 12366 => Opcode::VGETEXPPSZ128rkz, + 12367 => Opcode::VGETEXPPSZ256m, + 12368 => Opcode::VGETEXPPSZ256mb, + 12369 => Opcode::VGETEXPPSZ256mbk, + 12370 => Opcode::VGETEXPPSZ256mbkz, + 12371 => Opcode::VGETEXPPSZ256mk, + 12372 => Opcode::VGETEXPPSZ256mkz, + 12373 => Opcode::VGETEXPPSZ256r, + 12374 => Opcode::VGETEXPPSZ256rk, + 12375 => Opcode::VGETEXPPSZ256rkz, + 12376 => Opcode::VGETEXPPSZm, + 12377 => Opcode::VGETEXPPSZmb, + 12378 => Opcode::VGETEXPPSZmbk, + 12379 => Opcode::VGETEXPPSZmbkz, + 12380 => Opcode::VGETEXPPSZmk, + 12381 => Opcode::VGETEXPPSZmkz, + 12382 => Opcode::VGETEXPPSZr, + 12383 => Opcode::VGETEXPPSZrb, + 12384 => Opcode::VGETEXPPSZrbk, + 12385 => Opcode::VGETEXPPSZrbkz, + 12386 => Opcode::VGETEXPPSZrk, + 12387 => Opcode::VGETEXPPSZrkz, + 12388 => Opcode::VGETEXPSDZm, + 12389 => Opcode::VGETEXPSDZmk, + 12390 => Opcode::VGETEXPSDZmkz, + 12391 => Opcode::VGETEXPSDZr, + 12392 => Opcode::VGETEXPSDZrb, + 12393 => Opcode::VGETEXPSDZrbk, + 12394 => Opcode::VGETEXPSDZrbkz, + 12395 => Opcode::VGETEXPSDZrk, + 12396 => Opcode::VGETEXPSDZrkz, + 12397 => Opcode::VGETEXPSHZm, + 12398 => Opcode::VGETEXPSHZmk, + 12399 => Opcode::VGETEXPSHZmkz, + 12400 => Opcode::VGETEXPSHZr, + 12401 => Opcode::VGETEXPSHZrb, + 12402 => Opcode::VGETEXPSHZrbk, + 12403 => Opcode::VGETEXPSHZrbkz, + 12404 => Opcode::VGETEXPSHZrk, + 12405 => Opcode::VGETEXPSHZrkz, + 12406 => Opcode::VGETEXPSSZm, + 12407 => Opcode::VGETEXPSSZmk, + 12408 => Opcode::VGETEXPSSZmkz, + 12409 => Opcode::VGETEXPSSZr, + 12410 => Opcode::VGETEXPSSZrb, + 12411 => Opcode::VGETEXPSSZrbk, + 12412 => Opcode::VGETEXPSSZrbkz, + 12413 => Opcode::VGETEXPSSZrk, + 12414 => Opcode::VGETEXPSSZrkz, + 12415 => Opcode::VGETMANTBF16Z128rmbi, + 12416 => Opcode::VGETMANTBF16Z128rmbik, + 12417 => Opcode::VGETMANTBF16Z128rmbikz, + 12418 => Opcode::VGETMANTBF16Z128rmi, + 12419 => Opcode::VGETMANTBF16Z128rmik, + 12420 => Opcode::VGETMANTBF16Z128rmikz, + 12421 => Opcode::VGETMANTBF16Z128rri, + 12422 => Opcode::VGETMANTBF16Z128rrik, + 12423 => Opcode::VGETMANTBF16Z128rrikz, + 12424 => Opcode::VGETMANTBF16Z256rmbi, + 12425 => Opcode::VGETMANTBF16Z256rmbik, + 12426 => Opcode::VGETMANTBF16Z256rmbikz, + 12427 => Opcode::VGETMANTBF16Z256rmi, + 12428 => Opcode::VGETMANTBF16Z256rmik, + 12429 => Opcode::VGETMANTBF16Z256rmikz, + 12430 => Opcode::VGETMANTBF16Z256rri, + 12431 => Opcode::VGETMANTBF16Z256rrik, + 12432 => Opcode::VGETMANTBF16Z256rrikz, + 12433 => Opcode::VGETMANTBF16Zrmbi, + 12434 => Opcode::VGETMANTBF16Zrmbik, + 12435 => Opcode::VGETMANTBF16Zrmbikz, + 12436 => Opcode::VGETMANTBF16Zrmi, + 12437 => Opcode::VGETMANTBF16Zrmik, + 12438 => Opcode::VGETMANTBF16Zrmikz, + 12439 => Opcode::VGETMANTBF16Zrri, + 12440 => Opcode::VGETMANTBF16Zrrik, + 12441 => Opcode::VGETMANTBF16Zrrikz, + 12442 => Opcode::VGETMANTPDZ128rmbi, + 12443 => Opcode::VGETMANTPDZ128rmbik, + 12444 => Opcode::VGETMANTPDZ128rmbikz, + 12445 => Opcode::VGETMANTPDZ128rmi, + 12446 => Opcode::VGETMANTPDZ128rmik, + 12447 => Opcode::VGETMANTPDZ128rmikz, + 12448 => Opcode::VGETMANTPDZ128rri, + 12449 => Opcode::VGETMANTPDZ128rrik, + 12450 => Opcode::VGETMANTPDZ128rrikz, + 12451 => Opcode::VGETMANTPDZ256rmbi, + 12452 => Opcode::VGETMANTPDZ256rmbik, + 12453 => Opcode::VGETMANTPDZ256rmbikz, + 12454 => Opcode::VGETMANTPDZ256rmi, + 12455 => Opcode::VGETMANTPDZ256rmik, + 12456 => Opcode::VGETMANTPDZ256rmikz, + 12457 => Opcode::VGETMANTPDZ256rri, + 12458 => Opcode::VGETMANTPDZ256rrik, + 12459 => Opcode::VGETMANTPDZ256rrikz, + 12460 => Opcode::VGETMANTPDZrmbi, + 12461 => Opcode::VGETMANTPDZrmbik, + 12462 => Opcode::VGETMANTPDZrmbikz, + 12463 => Opcode::VGETMANTPDZrmi, + 12464 => Opcode::VGETMANTPDZrmik, + 12465 => Opcode::VGETMANTPDZrmikz, + 12466 => Opcode::VGETMANTPDZrri, + 12467 => Opcode::VGETMANTPDZrrib, + 12468 => Opcode::VGETMANTPDZrribk, + 12469 => Opcode::VGETMANTPDZrribkz, + 12470 => Opcode::VGETMANTPDZrrik, + 12471 => Opcode::VGETMANTPDZrrikz, + 12472 => Opcode::VGETMANTPHZ128rmbi, + 12473 => Opcode::VGETMANTPHZ128rmbik, + 12474 => Opcode::VGETMANTPHZ128rmbikz, + 12475 => Opcode::VGETMANTPHZ128rmi, + 12476 => Opcode::VGETMANTPHZ128rmik, + 12477 => Opcode::VGETMANTPHZ128rmikz, + 12478 => Opcode::VGETMANTPHZ128rri, + 12479 => Opcode::VGETMANTPHZ128rrik, + 12480 => Opcode::VGETMANTPHZ128rrikz, + 12481 => Opcode::VGETMANTPHZ256rmbi, + 12482 => Opcode::VGETMANTPHZ256rmbik, + 12483 => Opcode::VGETMANTPHZ256rmbikz, + 12484 => Opcode::VGETMANTPHZ256rmi, + 12485 => Opcode::VGETMANTPHZ256rmik, + 12486 => Opcode::VGETMANTPHZ256rmikz, + 12487 => Opcode::VGETMANTPHZ256rri, + 12488 => Opcode::VGETMANTPHZ256rrik, + 12489 => Opcode::VGETMANTPHZ256rrikz, + 12490 => Opcode::VGETMANTPHZrmbi, + 12491 => Opcode::VGETMANTPHZrmbik, + 12492 => Opcode::VGETMANTPHZrmbikz, + 12493 => Opcode::VGETMANTPHZrmi, + 12494 => Opcode::VGETMANTPHZrmik, + 12495 => Opcode::VGETMANTPHZrmikz, + 12496 => Opcode::VGETMANTPHZrri, + 12497 => Opcode::VGETMANTPHZrrib, + 12498 => Opcode::VGETMANTPHZrribk, + 12499 => Opcode::VGETMANTPHZrribkz, + 12500 => Opcode::VGETMANTPHZrrik, + 12501 => Opcode::VGETMANTPHZrrikz, + 12502 => Opcode::VGETMANTPSZ128rmbi, + 12503 => Opcode::VGETMANTPSZ128rmbik, + 12504 => Opcode::VGETMANTPSZ128rmbikz, + 12505 => Opcode::VGETMANTPSZ128rmi, + 12506 => Opcode::VGETMANTPSZ128rmik, + 12507 => Opcode::VGETMANTPSZ128rmikz, + 12508 => Opcode::VGETMANTPSZ128rri, + 12509 => Opcode::VGETMANTPSZ128rrik, + 12510 => Opcode::VGETMANTPSZ128rrikz, + 12511 => Opcode::VGETMANTPSZ256rmbi, + 12512 => Opcode::VGETMANTPSZ256rmbik, + 12513 => Opcode::VGETMANTPSZ256rmbikz, + 12514 => Opcode::VGETMANTPSZ256rmi, + 12515 => Opcode::VGETMANTPSZ256rmik, + 12516 => Opcode::VGETMANTPSZ256rmikz, + 12517 => Opcode::VGETMANTPSZ256rri, + 12518 => Opcode::VGETMANTPSZ256rrik, + 12519 => Opcode::VGETMANTPSZ256rrikz, + 12520 => Opcode::VGETMANTPSZrmbi, + 12521 => Opcode::VGETMANTPSZrmbik, + 12522 => Opcode::VGETMANTPSZrmbikz, + 12523 => Opcode::VGETMANTPSZrmi, + 12524 => Opcode::VGETMANTPSZrmik, + 12525 => Opcode::VGETMANTPSZrmikz, + 12526 => Opcode::VGETMANTPSZrri, + 12527 => Opcode::VGETMANTPSZrrib, + 12528 => Opcode::VGETMANTPSZrribk, + 12529 => Opcode::VGETMANTPSZrribkz, + 12530 => Opcode::VGETMANTPSZrrik, + 12531 => Opcode::VGETMANTPSZrrikz, + 12532 => Opcode::VGETMANTSDZrmi, + 12533 => Opcode::VGETMANTSDZrmik, + 12534 => Opcode::VGETMANTSDZrmikz, + 12535 => Opcode::VGETMANTSDZrri, + 12536 => Opcode::VGETMANTSDZrrib, + 12537 => Opcode::VGETMANTSDZrribk, + 12538 => Opcode::VGETMANTSDZrribkz, + 12539 => Opcode::VGETMANTSDZrrik, + 12540 => Opcode::VGETMANTSDZrrikz, + 12541 => Opcode::VGETMANTSHZrmi, + 12542 => Opcode::VGETMANTSHZrmik, + 12543 => Opcode::VGETMANTSHZrmikz, + 12544 => Opcode::VGETMANTSHZrri, + 12545 => Opcode::VGETMANTSHZrrib, + 12546 => Opcode::VGETMANTSHZrribk, + 12547 => Opcode::VGETMANTSHZrribkz, + 12548 => Opcode::VGETMANTSHZrrik, + 12549 => Opcode::VGETMANTSHZrrikz, + 12550 => Opcode::VGETMANTSSZrmi, + 12551 => Opcode::VGETMANTSSZrmik, + 12552 => Opcode::VGETMANTSSZrmikz, + 12553 => Opcode::VGETMANTSSZrri, + 12554 => Opcode::VGETMANTSSZrrib, + 12555 => Opcode::VGETMANTSSZrribk, + 12556 => Opcode::VGETMANTSSZrribkz, + 12557 => Opcode::VGETMANTSSZrrik, + 12558 => Opcode::VGETMANTSSZrrikz, + 12559 => Opcode::VGF2P8AFFINEINVQBYrmi, + 12560 => Opcode::VGF2P8AFFINEINVQBYrri, + 12561 => Opcode::VGF2P8AFFINEINVQBZ128rmbi, + 12562 => Opcode::VGF2P8AFFINEINVQBZ128rmbik, + 12563 => Opcode::VGF2P8AFFINEINVQBZ128rmbikz, + 12564 => Opcode::VGF2P8AFFINEINVQBZ128rmi, + 12565 => Opcode::VGF2P8AFFINEINVQBZ128rmik, + 12566 => Opcode::VGF2P8AFFINEINVQBZ128rmikz, + 12567 => Opcode::VGF2P8AFFINEINVQBZ128rri, + 12568 => Opcode::VGF2P8AFFINEINVQBZ128rrik, + 12569 => Opcode::VGF2P8AFFINEINVQBZ128rrikz, + 12570 => Opcode::VGF2P8AFFINEINVQBZ256rmbi, + 12571 => Opcode::VGF2P8AFFINEINVQBZ256rmbik, + 12572 => Opcode::VGF2P8AFFINEINVQBZ256rmbikz, + 12573 => Opcode::VGF2P8AFFINEINVQBZ256rmi, + 12574 => Opcode::VGF2P8AFFINEINVQBZ256rmik, + 12575 => Opcode::VGF2P8AFFINEINVQBZ256rmikz, + 12576 => Opcode::VGF2P8AFFINEINVQBZ256rri, + 12577 => Opcode::VGF2P8AFFINEINVQBZ256rrik, + 12578 => Opcode::VGF2P8AFFINEINVQBZ256rrikz, + 12579 => Opcode::VGF2P8AFFINEINVQBZrmbi, + 12580 => Opcode::VGF2P8AFFINEINVQBZrmbik, + 12581 => Opcode::VGF2P8AFFINEINVQBZrmbikz, + 12582 => Opcode::VGF2P8AFFINEINVQBZrmi, + 12583 => Opcode::VGF2P8AFFINEINVQBZrmik, + 12584 => Opcode::VGF2P8AFFINEINVQBZrmikz, + 12585 => Opcode::VGF2P8AFFINEINVQBZrri, + 12586 => Opcode::VGF2P8AFFINEINVQBZrrik, + 12587 => Opcode::VGF2P8AFFINEINVQBZrrikz, + 12588 => Opcode::VGF2P8AFFINEINVQBrmi, + 12589 => Opcode::VGF2P8AFFINEINVQBrri, + 12590 => Opcode::VGF2P8AFFINEQBYrmi, + 12591 => Opcode::VGF2P8AFFINEQBYrri, + 12592 => Opcode::VGF2P8AFFINEQBZ128rmbi, + 12593 => Opcode::VGF2P8AFFINEQBZ128rmbik, + 12594 => Opcode::VGF2P8AFFINEQBZ128rmbikz, + 12595 => Opcode::VGF2P8AFFINEQBZ128rmi, + 12596 => Opcode::VGF2P8AFFINEQBZ128rmik, + 12597 => Opcode::VGF2P8AFFINEQBZ128rmikz, + 12598 => Opcode::VGF2P8AFFINEQBZ128rri, + 12599 => Opcode::VGF2P8AFFINEQBZ128rrik, + 12600 => Opcode::VGF2P8AFFINEQBZ128rrikz, + 12601 => Opcode::VGF2P8AFFINEQBZ256rmbi, + 12602 => Opcode::VGF2P8AFFINEQBZ256rmbik, + 12603 => Opcode::VGF2P8AFFINEQBZ256rmbikz, + 12604 => Opcode::VGF2P8AFFINEQBZ256rmi, + 12605 => Opcode::VGF2P8AFFINEQBZ256rmik, + 12606 => Opcode::VGF2P8AFFINEQBZ256rmikz, + 12607 => Opcode::VGF2P8AFFINEQBZ256rri, + 12608 => Opcode::VGF2P8AFFINEQBZ256rrik, + 12609 => Opcode::VGF2P8AFFINEQBZ256rrikz, + 12610 => Opcode::VGF2P8AFFINEQBZrmbi, + 12611 => Opcode::VGF2P8AFFINEQBZrmbik, + 12612 => Opcode::VGF2P8AFFINEQBZrmbikz, + 12613 => Opcode::VGF2P8AFFINEQBZrmi, + 12614 => Opcode::VGF2P8AFFINEQBZrmik, + 12615 => Opcode::VGF2P8AFFINEQBZrmikz, + 12616 => Opcode::VGF2P8AFFINEQBZrri, + 12617 => Opcode::VGF2P8AFFINEQBZrrik, + 12618 => Opcode::VGF2P8AFFINEQBZrrikz, + 12619 => Opcode::VGF2P8AFFINEQBrmi, + 12620 => Opcode::VGF2P8AFFINEQBrri, + 12621 => Opcode::VGF2P8MULBYrm, + 12622 => Opcode::VGF2P8MULBYrr, + 12623 => Opcode::VGF2P8MULBZ128rm, + 12624 => Opcode::VGF2P8MULBZ128rmk, + 12625 => Opcode::VGF2P8MULBZ128rmkz, + 12626 => Opcode::VGF2P8MULBZ128rr, + 12627 => Opcode::VGF2P8MULBZ128rrk, + 12628 => Opcode::VGF2P8MULBZ128rrkz, + 12629 => Opcode::VGF2P8MULBZ256rm, + 12630 => Opcode::VGF2P8MULBZ256rmk, + 12631 => Opcode::VGF2P8MULBZ256rmkz, + 12632 => Opcode::VGF2P8MULBZ256rr, + 12633 => Opcode::VGF2P8MULBZ256rrk, + 12634 => Opcode::VGF2P8MULBZ256rrkz, + 12635 => Opcode::VGF2P8MULBZrm, + 12636 => Opcode::VGF2P8MULBZrmk, + 12637 => Opcode::VGF2P8MULBZrmkz, + 12638 => Opcode::VGF2P8MULBZrr, + 12639 => Opcode::VGF2P8MULBZrrk, + 12640 => Opcode::VGF2P8MULBZrrkz, + 12641 => Opcode::VGF2P8MULBrm, + 12642 => Opcode::VGF2P8MULBrr, + 12643 => Opcode::VHADDPDYrm, + 12644 => Opcode::VHADDPDYrr, + 12645 => Opcode::VHADDPDrm, + 12646 => Opcode::VHADDPDrr, + 12647 => Opcode::VHADDPSYrm, + 12648 => Opcode::VHADDPSYrr, + 12649 => Opcode::VHADDPSrm, + 12650 => Opcode::VHADDPSrr, + 12651 => Opcode::VHSUBPDYrm, + 12652 => Opcode::VHSUBPDYrr, + 12653 => Opcode::VHSUBPDrm, + 12654 => Opcode::VHSUBPDrr, + 12655 => Opcode::VHSUBPSYrm, + 12656 => Opcode::VHSUBPSYrr, + 12657 => Opcode::VHSUBPSrm, + 12658 => Opcode::VHSUBPSrr, + 12659 => Opcode::VINSERTF128rmi, + 12660 => Opcode::VINSERTF128rri, + 12661 => Opcode::VINSERTF32X4Z256rmi, + 12662 => Opcode::VINSERTF32X4Z256rmik, + 12663 => Opcode::VINSERTF32X4Z256rmikz, + 12664 => Opcode::VINSERTF32X4Z256rri, + 12665 => Opcode::VINSERTF32X4Z256rrik, + 12666 => Opcode::VINSERTF32X4Z256rrikz, + 12667 => Opcode::VINSERTF32X4Zrmi, + 12668 => Opcode::VINSERTF32X4Zrmik, + 12669 => Opcode::VINSERTF32X4Zrmikz, + 12670 => Opcode::VINSERTF32X4Zrri, + 12671 => Opcode::VINSERTF32X4Zrrik, + 12672 => Opcode::VINSERTF32X4Zrrikz, + 12673 => Opcode::VINSERTF32X8Zrmi, + 12674 => Opcode::VINSERTF32X8Zrmik, + 12675 => Opcode::VINSERTF32X8Zrmikz, + 12676 => Opcode::VINSERTF32X8Zrri, + 12677 => Opcode::VINSERTF32X8Zrrik, + 12678 => Opcode::VINSERTF32X8Zrrikz, + 12679 => Opcode::VINSERTF64X2Z256rmi, + 12680 => Opcode::VINSERTF64X2Z256rmik, + 12681 => Opcode::VINSERTF64X2Z256rmikz, + 12682 => Opcode::VINSERTF64X2Z256rri, + 12683 => Opcode::VINSERTF64X2Z256rrik, + 12684 => Opcode::VINSERTF64X2Z256rrikz, + 12685 => Opcode::VINSERTF64X2Zrmi, + 12686 => Opcode::VINSERTF64X2Zrmik, + 12687 => Opcode::VINSERTF64X2Zrmikz, + 12688 => Opcode::VINSERTF64X2Zrri, + 12689 => Opcode::VINSERTF64X2Zrrik, + 12690 => Opcode::VINSERTF64X2Zrrikz, + 12691 => Opcode::VINSERTF64X4Zrmi, + 12692 => Opcode::VINSERTF64X4Zrmik, + 12693 => Opcode::VINSERTF64X4Zrmikz, + 12694 => Opcode::VINSERTF64X4Zrri, + 12695 => Opcode::VINSERTF64X4Zrrik, + 12696 => Opcode::VINSERTF64X4Zrrikz, + 12697 => Opcode::VINSERTI128rmi, + 12698 => Opcode::VINSERTI128rri, + 12699 => Opcode::VINSERTI32X4Z256rmi, + 12700 => Opcode::VINSERTI32X4Z256rmik, + 12701 => Opcode::VINSERTI32X4Z256rmikz, + 12702 => Opcode::VINSERTI32X4Z256rri, + 12703 => Opcode::VINSERTI32X4Z256rrik, + 12704 => Opcode::VINSERTI32X4Z256rrikz, + 12705 => Opcode::VINSERTI32X4Zrmi, + 12706 => Opcode::VINSERTI32X4Zrmik, + 12707 => Opcode::VINSERTI32X4Zrmikz, + 12708 => Opcode::VINSERTI32X4Zrri, + 12709 => Opcode::VINSERTI32X4Zrrik, + 12710 => Opcode::VINSERTI32X4Zrrikz, + 12711 => Opcode::VINSERTI32X8Zrmi, + 12712 => Opcode::VINSERTI32X8Zrmik, + 12713 => Opcode::VINSERTI32X8Zrmikz, + 12714 => Opcode::VINSERTI32X8Zrri, + 12715 => Opcode::VINSERTI32X8Zrrik, + 12716 => Opcode::VINSERTI32X8Zrrikz, + 12717 => Opcode::VINSERTI64X2Z256rmi, + 12718 => Opcode::VINSERTI64X2Z256rmik, + 12719 => Opcode::VINSERTI64X2Z256rmikz, + 12720 => Opcode::VINSERTI64X2Z256rri, + 12721 => Opcode::VINSERTI64X2Z256rrik, + 12722 => Opcode::VINSERTI64X2Z256rrikz, + 12723 => Opcode::VINSERTI64X2Zrmi, + 12724 => Opcode::VINSERTI64X2Zrmik, + 12725 => Opcode::VINSERTI64X2Zrmikz, + 12726 => Opcode::VINSERTI64X2Zrri, + 12727 => Opcode::VINSERTI64X2Zrrik, + 12728 => Opcode::VINSERTI64X2Zrrikz, + 12729 => Opcode::VINSERTI64X4Zrmi, + 12730 => Opcode::VINSERTI64X4Zrmik, + 12731 => Opcode::VINSERTI64X4Zrmikz, + 12732 => Opcode::VINSERTI64X4Zrri, + 12733 => Opcode::VINSERTI64X4Zrrik, + 12734 => Opcode::VINSERTI64X4Zrrikz, + 12735 => Opcode::VINSERTPSZrmi, + 12736 => Opcode::VINSERTPSZrri, + 12737 => Opcode::VINSERTPSrmi, + 12738 => Opcode::VINSERTPSrri, + 12739 => Opcode::VLDDQUYrm, + 12740 => Opcode::VLDDQUrm, + 12741 => Opcode::VLDMXCSR, + 12742 => Opcode::VMASKMOVDQU, + 12743 => Opcode::VMASKMOVDQU64, + 12744 => Opcode::VMASKMOVPDYmr, + 12745 => Opcode::VMASKMOVPDYrm, + 12746 => Opcode::VMASKMOVPDmr, + 12747 => Opcode::VMASKMOVPDrm, + 12748 => Opcode::VMASKMOVPSYmr, + 12749 => Opcode::VMASKMOVPSYrm, + 12750 => Opcode::VMASKMOVPSmr, + 12751 => Opcode::VMASKMOVPSrm, + 12752 => Opcode::VMAXBF16Z128rm, + 12753 => Opcode::VMAXBF16Z128rmb, + 12754 => Opcode::VMAXBF16Z128rmbk, + 12755 => Opcode::VMAXBF16Z128rmbkz, + 12756 => Opcode::VMAXBF16Z128rmk, + 12757 => Opcode::VMAXBF16Z128rmkz, + 12758 => Opcode::VMAXBF16Z128rr, + 12759 => Opcode::VMAXBF16Z128rrk, + 12760 => Opcode::VMAXBF16Z128rrkz, + 12761 => Opcode::VMAXBF16Z256rm, + 12762 => Opcode::VMAXBF16Z256rmb, + 12763 => Opcode::VMAXBF16Z256rmbk, + 12764 => Opcode::VMAXBF16Z256rmbkz, + 12765 => Opcode::VMAXBF16Z256rmk, + 12766 => Opcode::VMAXBF16Z256rmkz, + 12767 => Opcode::VMAXBF16Z256rr, + 12768 => Opcode::VMAXBF16Z256rrk, + 12769 => Opcode::VMAXBF16Z256rrkz, + 12770 => Opcode::VMAXBF16Zrm, + 12771 => Opcode::VMAXBF16Zrmb, + 12772 => Opcode::VMAXBF16Zrmbk, + 12773 => Opcode::VMAXBF16Zrmbkz, + 12774 => Opcode::VMAXBF16Zrmk, + 12775 => Opcode::VMAXBF16Zrmkz, + 12776 => Opcode::VMAXBF16Zrr, + 12777 => Opcode::VMAXBF16Zrrk, + 12778 => Opcode::VMAXBF16Zrrkz, + 12779 => Opcode::VMAXCPDYrm, + 12780 => Opcode::VMAXCPDYrr, + 12781 => Opcode::VMAXCPDZ128rm, + 12782 => Opcode::VMAXCPDZ128rmb, + 12783 => Opcode::VMAXCPDZ128rmbk, + 12784 => Opcode::VMAXCPDZ128rmbkz, + 12785 => Opcode::VMAXCPDZ128rmk, + 12786 => Opcode::VMAXCPDZ128rmkz, + 12787 => Opcode::VMAXCPDZ128rr, + 12788 => Opcode::VMAXCPDZ128rrk, + 12789 => Opcode::VMAXCPDZ128rrkz, + 12790 => Opcode::VMAXCPDZ256rm, + 12791 => Opcode::VMAXCPDZ256rmb, + 12792 => Opcode::VMAXCPDZ256rmbk, + 12793 => Opcode::VMAXCPDZ256rmbkz, + 12794 => Opcode::VMAXCPDZ256rmk, + 12795 => Opcode::VMAXCPDZ256rmkz, + 12796 => Opcode::VMAXCPDZ256rr, + 12797 => Opcode::VMAXCPDZ256rrk, + 12798 => Opcode::VMAXCPDZ256rrkz, + 12799 => Opcode::VMAXCPDZrm, + 12800 => Opcode::VMAXCPDZrmb, + 12801 => Opcode::VMAXCPDZrmbk, + 12802 => Opcode::VMAXCPDZrmbkz, + 12803 => Opcode::VMAXCPDZrmk, + 12804 => Opcode::VMAXCPDZrmkz, + 12805 => Opcode::VMAXCPDZrr, + 12806 => Opcode::VMAXCPDZrrk, + 12807 => Opcode::VMAXCPDZrrkz, + 12808 => Opcode::VMAXCPDrm, + 12809 => Opcode::VMAXCPDrr, + 12810 => Opcode::VMAXCPHZ128rm, + 12811 => Opcode::VMAXCPHZ128rmb, + 12812 => Opcode::VMAXCPHZ128rmbk, + 12813 => Opcode::VMAXCPHZ128rmbkz, + 12814 => Opcode::VMAXCPHZ128rmk, + 12815 => Opcode::VMAXCPHZ128rmkz, + 12816 => Opcode::VMAXCPHZ128rr, + 12817 => Opcode::VMAXCPHZ128rrk, + 12818 => Opcode::VMAXCPHZ128rrkz, + 12819 => Opcode::VMAXCPHZ256rm, + 12820 => Opcode::VMAXCPHZ256rmb, + 12821 => Opcode::VMAXCPHZ256rmbk, + 12822 => Opcode::VMAXCPHZ256rmbkz, + 12823 => Opcode::VMAXCPHZ256rmk, + 12824 => Opcode::VMAXCPHZ256rmkz, + 12825 => Opcode::VMAXCPHZ256rr, + 12826 => Opcode::VMAXCPHZ256rrk, + 12827 => Opcode::VMAXCPHZ256rrkz, + 12828 => Opcode::VMAXCPHZrm, + 12829 => Opcode::VMAXCPHZrmb, + 12830 => Opcode::VMAXCPHZrmbk, + 12831 => Opcode::VMAXCPHZrmbkz, + 12832 => Opcode::VMAXCPHZrmk, + 12833 => Opcode::VMAXCPHZrmkz, + 12834 => Opcode::VMAXCPHZrr, + 12835 => Opcode::VMAXCPHZrrk, + 12836 => Opcode::VMAXCPHZrrkz, + 12837 => Opcode::VMAXCPSYrm, + 12838 => Opcode::VMAXCPSYrr, + 12839 => Opcode::VMAXCPSZ128rm, + 12840 => Opcode::VMAXCPSZ128rmb, + 12841 => Opcode::VMAXCPSZ128rmbk, + 12842 => Opcode::VMAXCPSZ128rmbkz, + 12843 => Opcode::VMAXCPSZ128rmk, + 12844 => Opcode::VMAXCPSZ128rmkz, + 12845 => Opcode::VMAXCPSZ128rr, + 12846 => Opcode::VMAXCPSZ128rrk, + 12847 => Opcode::VMAXCPSZ128rrkz, + 12848 => Opcode::VMAXCPSZ256rm, + 12849 => Opcode::VMAXCPSZ256rmb, + 12850 => Opcode::VMAXCPSZ256rmbk, + 12851 => Opcode::VMAXCPSZ256rmbkz, + 12852 => Opcode::VMAXCPSZ256rmk, + 12853 => Opcode::VMAXCPSZ256rmkz, + 12854 => Opcode::VMAXCPSZ256rr, + 12855 => Opcode::VMAXCPSZ256rrk, + 12856 => Opcode::VMAXCPSZ256rrkz, + 12857 => Opcode::VMAXCPSZrm, + 12858 => Opcode::VMAXCPSZrmb, + 12859 => Opcode::VMAXCPSZrmbk, + 12860 => Opcode::VMAXCPSZrmbkz, + 12861 => Opcode::VMAXCPSZrmk, + 12862 => Opcode::VMAXCPSZrmkz, + 12863 => Opcode::VMAXCPSZrr, + 12864 => Opcode::VMAXCPSZrrk, + 12865 => Opcode::VMAXCPSZrrkz, + 12866 => Opcode::VMAXCPSrm, + 12867 => Opcode::VMAXCPSrr, + 12868 => Opcode::VMAXCSDZrm, + 12869 => Opcode::VMAXCSDZrr, + 12870 => Opcode::VMAXCSDrm, + 12871 => Opcode::VMAXCSDrr, + 12872 => Opcode::VMAXCSHZrm, + 12873 => Opcode::VMAXCSHZrr, + 12874 => Opcode::VMAXCSSZrm, + 12875 => Opcode::VMAXCSSZrr, + 12876 => Opcode::VMAXCSSrm, + 12877 => Opcode::VMAXCSSrr, + 12878 => Opcode::VMAXPDYrm, + 12879 => Opcode::VMAXPDYrr, + 12880 => Opcode::VMAXPDZ128rm, + 12881 => Opcode::VMAXPDZ128rmb, + 12882 => Opcode::VMAXPDZ128rmbk, + 12883 => Opcode::VMAXPDZ128rmbkz, + 12884 => Opcode::VMAXPDZ128rmk, + 12885 => Opcode::VMAXPDZ128rmkz, + 12886 => Opcode::VMAXPDZ128rr, + 12887 => Opcode::VMAXPDZ128rrk, + 12888 => Opcode::VMAXPDZ128rrkz, + 12889 => Opcode::VMAXPDZ256rm, + 12890 => Opcode::VMAXPDZ256rmb, + 12891 => Opcode::VMAXPDZ256rmbk, + 12892 => Opcode::VMAXPDZ256rmbkz, + 12893 => Opcode::VMAXPDZ256rmk, + 12894 => Opcode::VMAXPDZ256rmkz, + 12895 => Opcode::VMAXPDZ256rr, + 12896 => Opcode::VMAXPDZ256rrk, + 12897 => Opcode::VMAXPDZ256rrkz, + 12898 => Opcode::VMAXPDZrm, + 12899 => Opcode::VMAXPDZrmb, + 12900 => Opcode::VMAXPDZrmbk, + 12901 => Opcode::VMAXPDZrmbkz, + 12902 => Opcode::VMAXPDZrmk, + 12903 => Opcode::VMAXPDZrmkz, + 12904 => Opcode::VMAXPDZrr, + 12905 => Opcode::VMAXPDZrrb, + 12906 => Opcode::VMAXPDZrrbk, + 12907 => Opcode::VMAXPDZrrbkz, + 12908 => Opcode::VMAXPDZrrk, + 12909 => Opcode::VMAXPDZrrkz, + 12910 => Opcode::VMAXPDrm, + 12911 => Opcode::VMAXPDrr, + 12912 => Opcode::VMAXPHZ128rm, + 12913 => Opcode::VMAXPHZ128rmb, + 12914 => Opcode::VMAXPHZ128rmbk, + 12915 => Opcode::VMAXPHZ128rmbkz, + 12916 => Opcode::VMAXPHZ128rmk, + 12917 => Opcode::VMAXPHZ128rmkz, + 12918 => Opcode::VMAXPHZ128rr, + 12919 => Opcode::VMAXPHZ128rrk, + 12920 => Opcode::VMAXPHZ128rrkz, + 12921 => Opcode::VMAXPHZ256rm, + 12922 => Opcode::VMAXPHZ256rmb, + 12923 => Opcode::VMAXPHZ256rmbk, + 12924 => Opcode::VMAXPHZ256rmbkz, + 12925 => Opcode::VMAXPHZ256rmk, + 12926 => Opcode::VMAXPHZ256rmkz, + 12927 => Opcode::VMAXPHZ256rr, + 12928 => Opcode::VMAXPHZ256rrk, + 12929 => Opcode::VMAXPHZ256rrkz, + 12930 => Opcode::VMAXPHZrm, + 12931 => Opcode::VMAXPHZrmb, + 12932 => Opcode::VMAXPHZrmbk, + 12933 => Opcode::VMAXPHZrmbkz, + 12934 => Opcode::VMAXPHZrmk, + 12935 => Opcode::VMAXPHZrmkz, + 12936 => Opcode::VMAXPHZrr, + 12937 => Opcode::VMAXPHZrrb, + 12938 => Opcode::VMAXPHZrrbk, + 12939 => Opcode::VMAXPHZrrbkz, + 12940 => Opcode::VMAXPHZrrk, + 12941 => Opcode::VMAXPHZrrkz, + 12942 => Opcode::VMAXPSYrm, + 12943 => Opcode::VMAXPSYrr, + 12944 => Opcode::VMAXPSZ128rm, + 12945 => Opcode::VMAXPSZ128rmb, + 12946 => Opcode::VMAXPSZ128rmbk, + 12947 => Opcode::VMAXPSZ128rmbkz, + 12948 => Opcode::VMAXPSZ128rmk, + 12949 => Opcode::VMAXPSZ128rmkz, + 12950 => Opcode::VMAXPSZ128rr, + 12951 => Opcode::VMAXPSZ128rrk, + 12952 => Opcode::VMAXPSZ128rrkz, + 12953 => Opcode::VMAXPSZ256rm, + 12954 => Opcode::VMAXPSZ256rmb, + 12955 => Opcode::VMAXPSZ256rmbk, + 12956 => Opcode::VMAXPSZ256rmbkz, + 12957 => Opcode::VMAXPSZ256rmk, + 12958 => Opcode::VMAXPSZ256rmkz, + 12959 => Opcode::VMAXPSZ256rr, + 12960 => Opcode::VMAXPSZ256rrk, + 12961 => Opcode::VMAXPSZ256rrkz, + 12962 => Opcode::VMAXPSZrm, + 12963 => Opcode::VMAXPSZrmb, + 12964 => Opcode::VMAXPSZrmbk, + 12965 => Opcode::VMAXPSZrmbkz, + 12966 => Opcode::VMAXPSZrmk, + 12967 => Opcode::VMAXPSZrmkz, + 12968 => Opcode::VMAXPSZrr, + 12969 => Opcode::VMAXPSZrrb, + 12970 => Opcode::VMAXPSZrrbk, + 12971 => Opcode::VMAXPSZrrbkz, + 12972 => Opcode::VMAXPSZrrk, + 12973 => Opcode::VMAXPSZrrkz, + 12974 => Opcode::VMAXPSrm, + 12975 => Opcode::VMAXPSrr, + 12976 => Opcode::VMAXSDZrm, + 12977 => Opcode::VMAXSDZrm_Int, + 12978 => Opcode::VMAXSDZrmk_Int, + 12979 => Opcode::VMAXSDZrmkz_Int, + 12980 => Opcode::VMAXSDZrr, + 12981 => Opcode::VMAXSDZrr_Int, + 12982 => Opcode::VMAXSDZrrb_Int, + 12983 => Opcode::VMAXSDZrrbk_Int, + 12984 => Opcode::VMAXSDZrrbkz_Int, + 12985 => Opcode::VMAXSDZrrk_Int, + 12986 => Opcode::VMAXSDZrrkz_Int, + 12987 => Opcode::VMAXSDrm, + 12988 => Opcode::VMAXSDrm_Int, + 12989 => Opcode::VMAXSDrr, + 12990 => Opcode::VMAXSDrr_Int, + 12991 => Opcode::VMAXSHZrm, + 12992 => Opcode::VMAXSHZrm_Int, + 12993 => Opcode::VMAXSHZrmk_Int, + 12994 => Opcode::VMAXSHZrmkz_Int, + 12995 => Opcode::VMAXSHZrr, + 12996 => Opcode::VMAXSHZrr_Int, + 12997 => Opcode::VMAXSHZrrb_Int, + 12998 => Opcode::VMAXSHZrrbk_Int, + 12999 => Opcode::VMAXSHZrrbkz_Int, + 13000 => Opcode::VMAXSHZrrk_Int, + 13001 => Opcode::VMAXSHZrrkz_Int, + 13002 => Opcode::VMAXSSZrm, + 13003 => Opcode::VMAXSSZrm_Int, + 13004 => Opcode::VMAXSSZrmk_Int, + 13005 => Opcode::VMAXSSZrmkz_Int, + 13006 => Opcode::VMAXSSZrr, + 13007 => Opcode::VMAXSSZrr_Int, + 13008 => Opcode::VMAXSSZrrb_Int, + 13009 => Opcode::VMAXSSZrrbk_Int, + 13010 => Opcode::VMAXSSZrrbkz_Int, + 13011 => Opcode::VMAXSSZrrk_Int, + 13012 => Opcode::VMAXSSZrrkz_Int, + 13013 => Opcode::VMAXSSrm, + 13014 => Opcode::VMAXSSrm_Int, + 13015 => Opcode::VMAXSSrr, + 13016 => Opcode::VMAXSSrr_Int, + 13017 => Opcode::VMCALL, + 13018 => Opcode::VMCLEARm, + 13019 => Opcode::VMFUNC, + 13020 => Opcode::VMINBF16Z128rm, + 13021 => Opcode::VMINBF16Z128rmb, + 13022 => Opcode::VMINBF16Z128rmbk, + 13023 => Opcode::VMINBF16Z128rmbkz, + 13024 => Opcode::VMINBF16Z128rmk, + 13025 => Opcode::VMINBF16Z128rmkz, + 13026 => Opcode::VMINBF16Z128rr, + 13027 => Opcode::VMINBF16Z128rrk, + 13028 => Opcode::VMINBF16Z128rrkz, + 13029 => Opcode::VMINBF16Z256rm, + 13030 => Opcode::VMINBF16Z256rmb, + 13031 => Opcode::VMINBF16Z256rmbk, + 13032 => Opcode::VMINBF16Z256rmbkz, + 13033 => Opcode::VMINBF16Z256rmk, + 13034 => Opcode::VMINBF16Z256rmkz, + 13035 => Opcode::VMINBF16Z256rr, + 13036 => Opcode::VMINBF16Z256rrk, + 13037 => Opcode::VMINBF16Z256rrkz, + 13038 => Opcode::VMINBF16Zrm, + 13039 => Opcode::VMINBF16Zrmb, + 13040 => Opcode::VMINBF16Zrmbk, + 13041 => Opcode::VMINBF16Zrmbkz, + 13042 => Opcode::VMINBF16Zrmk, + 13043 => Opcode::VMINBF16Zrmkz, + 13044 => Opcode::VMINBF16Zrr, + 13045 => Opcode::VMINBF16Zrrk, + 13046 => Opcode::VMINBF16Zrrkz, + 13047 => Opcode::VMINCPDYrm, + 13048 => Opcode::VMINCPDYrr, + 13049 => Opcode::VMINCPDZ128rm, + 13050 => Opcode::VMINCPDZ128rmb, + 13051 => Opcode::VMINCPDZ128rmbk, + 13052 => Opcode::VMINCPDZ128rmbkz, + 13053 => Opcode::VMINCPDZ128rmk, + 13054 => Opcode::VMINCPDZ128rmkz, + 13055 => Opcode::VMINCPDZ128rr, + 13056 => Opcode::VMINCPDZ128rrk, + 13057 => Opcode::VMINCPDZ128rrkz, + 13058 => Opcode::VMINCPDZ256rm, + 13059 => Opcode::VMINCPDZ256rmb, + 13060 => Opcode::VMINCPDZ256rmbk, + 13061 => Opcode::VMINCPDZ256rmbkz, + 13062 => Opcode::VMINCPDZ256rmk, + 13063 => Opcode::VMINCPDZ256rmkz, + 13064 => Opcode::VMINCPDZ256rr, + 13065 => Opcode::VMINCPDZ256rrk, + 13066 => Opcode::VMINCPDZ256rrkz, + 13067 => Opcode::VMINCPDZrm, + 13068 => Opcode::VMINCPDZrmb, + 13069 => Opcode::VMINCPDZrmbk, + 13070 => Opcode::VMINCPDZrmbkz, + 13071 => Opcode::VMINCPDZrmk, + 13072 => Opcode::VMINCPDZrmkz, + 13073 => Opcode::VMINCPDZrr, + 13074 => Opcode::VMINCPDZrrk, + 13075 => Opcode::VMINCPDZrrkz, + 13076 => Opcode::VMINCPDrm, + 13077 => Opcode::VMINCPDrr, + 13078 => Opcode::VMINCPHZ128rm, + 13079 => Opcode::VMINCPHZ128rmb, + 13080 => Opcode::VMINCPHZ128rmbk, + 13081 => Opcode::VMINCPHZ128rmbkz, + 13082 => Opcode::VMINCPHZ128rmk, + 13083 => Opcode::VMINCPHZ128rmkz, + 13084 => Opcode::VMINCPHZ128rr, + 13085 => Opcode::VMINCPHZ128rrk, + 13086 => Opcode::VMINCPHZ128rrkz, + 13087 => Opcode::VMINCPHZ256rm, + 13088 => Opcode::VMINCPHZ256rmb, + 13089 => Opcode::VMINCPHZ256rmbk, + 13090 => Opcode::VMINCPHZ256rmbkz, + 13091 => Opcode::VMINCPHZ256rmk, + 13092 => Opcode::VMINCPHZ256rmkz, + 13093 => Opcode::VMINCPHZ256rr, + 13094 => Opcode::VMINCPHZ256rrk, + 13095 => Opcode::VMINCPHZ256rrkz, + 13096 => Opcode::VMINCPHZrm, + 13097 => Opcode::VMINCPHZrmb, + 13098 => Opcode::VMINCPHZrmbk, + 13099 => Opcode::VMINCPHZrmbkz, + 13100 => Opcode::VMINCPHZrmk, + 13101 => Opcode::VMINCPHZrmkz, + 13102 => Opcode::VMINCPHZrr, + 13103 => Opcode::VMINCPHZrrk, + 13104 => Opcode::VMINCPHZrrkz, + 13105 => Opcode::VMINCPSYrm, + 13106 => Opcode::VMINCPSYrr, + 13107 => Opcode::VMINCPSZ128rm, + 13108 => Opcode::VMINCPSZ128rmb, + 13109 => Opcode::VMINCPSZ128rmbk, + 13110 => Opcode::VMINCPSZ128rmbkz, + 13111 => Opcode::VMINCPSZ128rmk, + 13112 => Opcode::VMINCPSZ128rmkz, + 13113 => Opcode::VMINCPSZ128rr, + 13114 => Opcode::VMINCPSZ128rrk, + 13115 => Opcode::VMINCPSZ128rrkz, + 13116 => Opcode::VMINCPSZ256rm, + 13117 => Opcode::VMINCPSZ256rmb, + 13118 => Opcode::VMINCPSZ256rmbk, + 13119 => Opcode::VMINCPSZ256rmbkz, + 13120 => Opcode::VMINCPSZ256rmk, + 13121 => Opcode::VMINCPSZ256rmkz, + 13122 => Opcode::VMINCPSZ256rr, + 13123 => Opcode::VMINCPSZ256rrk, + 13124 => Opcode::VMINCPSZ256rrkz, + 13125 => Opcode::VMINCPSZrm, + 13126 => Opcode::VMINCPSZrmb, + 13127 => Opcode::VMINCPSZrmbk, + 13128 => Opcode::VMINCPSZrmbkz, + 13129 => Opcode::VMINCPSZrmk, + 13130 => Opcode::VMINCPSZrmkz, + 13131 => Opcode::VMINCPSZrr, + 13132 => Opcode::VMINCPSZrrk, + 13133 => Opcode::VMINCPSZrrkz, + 13134 => Opcode::VMINCPSrm, + 13135 => Opcode::VMINCPSrr, + 13136 => Opcode::VMINCSDZrm, + 13137 => Opcode::VMINCSDZrr, + 13138 => Opcode::VMINCSDrm, + 13139 => Opcode::VMINCSDrr, + 13140 => Opcode::VMINCSHZrm, + 13141 => Opcode::VMINCSHZrr, + 13142 => Opcode::VMINCSSZrm, + 13143 => Opcode::VMINCSSZrr, + 13144 => Opcode::VMINCSSrm, + 13145 => Opcode::VMINCSSrr, + 13146 => Opcode::VMINMAXBF16Z128rmbi, + 13147 => Opcode::VMINMAXBF16Z128rmbik, + 13148 => Opcode::VMINMAXBF16Z128rmbikz, + 13149 => Opcode::VMINMAXBF16Z128rmi, + 13150 => Opcode::VMINMAXBF16Z128rmik, + 13151 => Opcode::VMINMAXBF16Z128rmikz, + 13152 => Opcode::VMINMAXBF16Z128rri, + 13153 => Opcode::VMINMAXBF16Z128rrik, + 13154 => Opcode::VMINMAXBF16Z128rrikz, + 13155 => Opcode::VMINMAXBF16Z256rmbi, + 13156 => Opcode::VMINMAXBF16Z256rmbik, + 13157 => Opcode::VMINMAXBF16Z256rmbikz, + 13158 => Opcode::VMINMAXBF16Z256rmi, + 13159 => Opcode::VMINMAXBF16Z256rmik, + 13160 => Opcode::VMINMAXBF16Z256rmikz, + 13161 => Opcode::VMINMAXBF16Z256rri, + 13162 => Opcode::VMINMAXBF16Z256rrik, + 13163 => Opcode::VMINMAXBF16Z256rrikz, + 13164 => Opcode::VMINMAXBF16Zrmbi, + 13165 => Opcode::VMINMAXBF16Zrmbik, + 13166 => Opcode::VMINMAXBF16Zrmbikz, + 13167 => Opcode::VMINMAXBF16Zrmi, + 13168 => Opcode::VMINMAXBF16Zrmik, + 13169 => Opcode::VMINMAXBF16Zrmikz, + 13170 => Opcode::VMINMAXBF16Zrri, + 13171 => Opcode::VMINMAXBF16Zrrik, + 13172 => Opcode::VMINMAXBF16Zrrikz, + 13173 => Opcode::VMINMAXPDZ128rmbi, + 13174 => Opcode::VMINMAXPDZ128rmbik, + 13175 => Opcode::VMINMAXPDZ128rmbikz, + 13176 => Opcode::VMINMAXPDZ128rmi, + 13177 => Opcode::VMINMAXPDZ128rmik, + 13178 => Opcode::VMINMAXPDZ128rmikz, + 13179 => Opcode::VMINMAXPDZ128rri, + 13180 => Opcode::VMINMAXPDZ128rrik, + 13181 => Opcode::VMINMAXPDZ128rrikz, + 13182 => Opcode::VMINMAXPDZ256rmbi, + 13183 => Opcode::VMINMAXPDZ256rmbik, + 13184 => Opcode::VMINMAXPDZ256rmbikz, + 13185 => Opcode::VMINMAXPDZ256rmi, + 13186 => Opcode::VMINMAXPDZ256rmik, + 13187 => Opcode::VMINMAXPDZ256rmikz, + 13188 => Opcode::VMINMAXPDZ256rri, + 13189 => Opcode::VMINMAXPDZ256rrik, + 13190 => Opcode::VMINMAXPDZ256rrikz, + 13191 => Opcode::VMINMAXPDZrmbi, + 13192 => Opcode::VMINMAXPDZrmbik, + 13193 => Opcode::VMINMAXPDZrmbikz, + 13194 => Opcode::VMINMAXPDZrmi, + 13195 => Opcode::VMINMAXPDZrmik, + 13196 => Opcode::VMINMAXPDZrmikz, + 13197 => Opcode::VMINMAXPDZrri, + 13198 => Opcode::VMINMAXPDZrrib, + 13199 => Opcode::VMINMAXPDZrribk, + 13200 => Opcode::VMINMAXPDZrribkz, + 13201 => Opcode::VMINMAXPDZrrik, + 13202 => Opcode::VMINMAXPDZrrikz, + 13203 => Opcode::VMINMAXPHZ128rmbi, + 13204 => Opcode::VMINMAXPHZ128rmbik, + 13205 => Opcode::VMINMAXPHZ128rmbikz, + 13206 => Opcode::VMINMAXPHZ128rmi, + 13207 => Opcode::VMINMAXPHZ128rmik, + 13208 => Opcode::VMINMAXPHZ128rmikz, + 13209 => Opcode::VMINMAXPHZ128rri, + 13210 => Opcode::VMINMAXPHZ128rrik, + 13211 => Opcode::VMINMAXPHZ128rrikz, + 13212 => Opcode::VMINMAXPHZ256rmbi, + 13213 => Opcode::VMINMAXPHZ256rmbik, + 13214 => Opcode::VMINMAXPHZ256rmbikz, + 13215 => Opcode::VMINMAXPHZ256rmi, + 13216 => Opcode::VMINMAXPHZ256rmik, + 13217 => Opcode::VMINMAXPHZ256rmikz, + 13218 => Opcode::VMINMAXPHZ256rri, + 13219 => Opcode::VMINMAXPHZ256rrik, + 13220 => Opcode::VMINMAXPHZ256rrikz, + 13221 => Opcode::VMINMAXPHZrmbi, + 13222 => Opcode::VMINMAXPHZrmbik, + 13223 => Opcode::VMINMAXPHZrmbikz, + 13224 => Opcode::VMINMAXPHZrmi, + 13225 => Opcode::VMINMAXPHZrmik, + 13226 => Opcode::VMINMAXPHZrmikz, + 13227 => Opcode::VMINMAXPHZrri, + 13228 => Opcode::VMINMAXPHZrrib, + 13229 => Opcode::VMINMAXPHZrribk, + 13230 => Opcode::VMINMAXPHZrribkz, + 13231 => Opcode::VMINMAXPHZrrik, + 13232 => Opcode::VMINMAXPHZrrikz, + 13233 => Opcode::VMINMAXPSZ128rmbi, + 13234 => Opcode::VMINMAXPSZ128rmbik, + 13235 => Opcode::VMINMAXPSZ128rmbikz, + 13236 => Opcode::VMINMAXPSZ128rmi, + 13237 => Opcode::VMINMAXPSZ128rmik, + 13238 => Opcode::VMINMAXPSZ128rmikz, + 13239 => Opcode::VMINMAXPSZ128rri, + 13240 => Opcode::VMINMAXPSZ128rrik, + 13241 => Opcode::VMINMAXPSZ128rrikz, + 13242 => Opcode::VMINMAXPSZ256rmbi, + 13243 => Opcode::VMINMAXPSZ256rmbik, + 13244 => Opcode::VMINMAXPSZ256rmbikz, + 13245 => Opcode::VMINMAXPSZ256rmi, + 13246 => Opcode::VMINMAXPSZ256rmik, + 13247 => Opcode::VMINMAXPSZ256rmikz, + 13248 => Opcode::VMINMAXPSZ256rri, + 13249 => Opcode::VMINMAXPSZ256rrik, + 13250 => Opcode::VMINMAXPSZ256rrikz, + 13251 => Opcode::VMINMAXPSZrmbi, + 13252 => Opcode::VMINMAXPSZrmbik, + 13253 => Opcode::VMINMAXPSZrmbikz, + 13254 => Opcode::VMINMAXPSZrmi, + 13255 => Opcode::VMINMAXPSZrmik, + 13256 => Opcode::VMINMAXPSZrmikz, + 13257 => Opcode::VMINMAXPSZrri, + 13258 => Opcode::VMINMAXPSZrrib, + 13259 => Opcode::VMINMAXPSZrribk, + 13260 => Opcode::VMINMAXPSZrribkz, + 13261 => Opcode::VMINMAXPSZrrik, + 13262 => Opcode::VMINMAXPSZrrikz, + 13263 => Opcode::VMINMAXSDrmi, + 13264 => Opcode::VMINMAXSDrmi_Int, + 13265 => Opcode::VMINMAXSDrmik_Int, + 13266 => Opcode::VMINMAXSDrmikz_Int, + 13267 => Opcode::VMINMAXSDrri, + 13268 => Opcode::VMINMAXSDrri_Int, + 13269 => Opcode::VMINMAXSDrrib_Int, + 13270 => Opcode::VMINMAXSDrribk_Int, + 13271 => Opcode::VMINMAXSDrribkz_Int, + 13272 => Opcode::VMINMAXSDrrik_Int, + 13273 => Opcode::VMINMAXSDrrikz_Int, + 13274 => Opcode::VMINMAXSHrmi, + 13275 => Opcode::VMINMAXSHrmi_Int, + 13276 => Opcode::VMINMAXSHrmik_Int, + 13277 => Opcode::VMINMAXSHrmikz_Int, + 13278 => Opcode::VMINMAXSHrri, + 13279 => Opcode::VMINMAXSHrri_Int, + 13280 => Opcode::VMINMAXSHrrib_Int, + 13281 => Opcode::VMINMAXSHrribk_Int, + 13282 => Opcode::VMINMAXSHrribkz_Int, + 13283 => Opcode::VMINMAXSHrrik_Int, + 13284 => Opcode::VMINMAXSHrrikz_Int, + 13285 => Opcode::VMINMAXSSrmi, + 13286 => Opcode::VMINMAXSSrmi_Int, + 13287 => Opcode::VMINMAXSSrmik_Int, + 13288 => Opcode::VMINMAXSSrmikz_Int, + 13289 => Opcode::VMINMAXSSrri, + 13290 => Opcode::VMINMAXSSrri_Int, + 13291 => Opcode::VMINMAXSSrrib_Int, + 13292 => Opcode::VMINMAXSSrribk_Int, + 13293 => Opcode::VMINMAXSSrribkz_Int, + 13294 => Opcode::VMINMAXSSrrik_Int, + 13295 => Opcode::VMINMAXSSrrikz_Int, + 13296 => Opcode::VMINPDYrm, + 13297 => Opcode::VMINPDYrr, + 13298 => Opcode::VMINPDZ128rm, + 13299 => Opcode::VMINPDZ128rmb, + 13300 => Opcode::VMINPDZ128rmbk, + 13301 => Opcode::VMINPDZ128rmbkz, + 13302 => Opcode::VMINPDZ128rmk, + 13303 => Opcode::VMINPDZ128rmkz, + 13304 => Opcode::VMINPDZ128rr, + 13305 => Opcode::VMINPDZ128rrk, + 13306 => Opcode::VMINPDZ128rrkz, + 13307 => Opcode::VMINPDZ256rm, + 13308 => Opcode::VMINPDZ256rmb, + 13309 => Opcode::VMINPDZ256rmbk, + 13310 => Opcode::VMINPDZ256rmbkz, + 13311 => Opcode::VMINPDZ256rmk, + 13312 => Opcode::VMINPDZ256rmkz, + 13313 => Opcode::VMINPDZ256rr, + 13314 => Opcode::VMINPDZ256rrk, + 13315 => Opcode::VMINPDZ256rrkz, + 13316 => Opcode::VMINPDZrm, + 13317 => Opcode::VMINPDZrmb, + 13318 => Opcode::VMINPDZrmbk, + 13319 => Opcode::VMINPDZrmbkz, + 13320 => Opcode::VMINPDZrmk, + 13321 => Opcode::VMINPDZrmkz, + 13322 => Opcode::VMINPDZrr, + 13323 => Opcode::VMINPDZrrb, + 13324 => Opcode::VMINPDZrrbk, + 13325 => Opcode::VMINPDZrrbkz, + 13326 => Opcode::VMINPDZrrk, + 13327 => Opcode::VMINPDZrrkz, + 13328 => Opcode::VMINPDrm, + 13329 => Opcode::VMINPDrr, + 13330 => Opcode::VMINPHZ128rm, + 13331 => Opcode::VMINPHZ128rmb, + 13332 => Opcode::VMINPHZ128rmbk, + 13333 => Opcode::VMINPHZ128rmbkz, + 13334 => Opcode::VMINPHZ128rmk, + 13335 => Opcode::VMINPHZ128rmkz, + 13336 => Opcode::VMINPHZ128rr, + 13337 => Opcode::VMINPHZ128rrk, + 13338 => Opcode::VMINPHZ128rrkz, + 13339 => Opcode::VMINPHZ256rm, + 13340 => Opcode::VMINPHZ256rmb, + 13341 => Opcode::VMINPHZ256rmbk, + 13342 => Opcode::VMINPHZ256rmbkz, + 13343 => Opcode::VMINPHZ256rmk, + 13344 => Opcode::VMINPHZ256rmkz, + 13345 => Opcode::VMINPHZ256rr, + 13346 => Opcode::VMINPHZ256rrk, + 13347 => Opcode::VMINPHZ256rrkz, + 13348 => Opcode::VMINPHZrm, + 13349 => Opcode::VMINPHZrmb, + 13350 => Opcode::VMINPHZrmbk, + 13351 => Opcode::VMINPHZrmbkz, + 13352 => Opcode::VMINPHZrmk, + 13353 => Opcode::VMINPHZrmkz, + 13354 => Opcode::VMINPHZrr, + 13355 => Opcode::VMINPHZrrb, + 13356 => Opcode::VMINPHZrrbk, + 13357 => Opcode::VMINPHZrrbkz, + 13358 => Opcode::VMINPHZrrk, + 13359 => Opcode::VMINPHZrrkz, + 13360 => Opcode::VMINPSYrm, + 13361 => Opcode::VMINPSYrr, + 13362 => Opcode::VMINPSZ128rm, + 13363 => Opcode::VMINPSZ128rmb, + 13364 => Opcode::VMINPSZ128rmbk, + 13365 => Opcode::VMINPSZ128rmbkz, + 13366 => Opcode::VMINPSZ128rmk, + 13367 => Opcode::VMINPSZ128rmkz, + 13368 => Opcode::VMINPSZ128rr, + 13369 => Opcode::VMINPSZ128rrk, + 13370 => Opcode::VMINPSZ128rrkz, + 13371 => Opcode::VMINPSZ256rm, + 13372 => Opcode::VMINPSZ256rmb, + 13373 => Opcode::VMINPSZ256rmbk, + 13374 => Opcode::VMINPSZ256rmbkz, + 13375 => Opcode::VMINPSZ256rmk, + 13376 => Opcode::VMINPSZ256rmkz, + 13377 => Opcode::VMINPSZ256rr, + 13378 => Opcode::VMINPSZ256rrk, + 13379 => Opcode::VMINPSZ256rrkz, + 13380 => Opcode::VMINPSZrm, + 13381 => Opcode::VMINPSZrmb, + 13382 => Opcode::VMINPSZrmbk, + 13383 => Opcode::VMINPSZrmbkz, + 13384 => Opcode::VMINPSZrmk, + 13385 => Opcode::VMINPSZrmkz, + 13386 => Opcode::VMINPSZrr, + 13387 => Opcode::VMINPSZrrb, + 13388 => Opcode::VMINPSZrrbk, + 13389 => Opcode::VMINPSZrrbkz, + 13390 => Opcode::VMINPSZrrk, + 13391 => Opcode::VMINPSZrrkz, + 13392 => Opcode::VMINPSrm, + 13393 => Opcode::VMINPSrr, + 13394 => Opcode::VMINSDZrm, + 13395 => Opcode::VMINSDZrm_Int, + 13396 => Opcode::VMINSDZrmk_Int, + 13397 => Opcode::VMINSDZrmkz_Int, + 13398 => Opcode::VMINSDZrr, + 13399 => Opcode::VMINSDZrr_Int, + 13400 => Opcode::VMINSDZrrb_Int, + 13401 => Opcode::VMINSDZrrbk_Int, + 13402 => Opcode::VMINSDZrrbkz_Int, + 13403 => Opcode::VMINSDZrrk_Int, + 13404 => Opcode::VMINSDZrrkz_Int, + 13405 => Opcode::VMINSDrm, + 13406 => Opcode::VMINSDrm_Int, + 13407 => Opcode::VMINSDrr, + 13408 => Opcode::VMINSDrr_Int, + 13409 => Opcode::VMINSHZrm, + 13410 => Opcode::VMINSHZrm_Int, + 13411 => Opcode::VMINSHZrmk_Int, + 13412 => Opcode::VMINSHZrmkz_Int, + 13413 => Opcode::VMINSHZrr, + 13414 => Opcode::VMINSHZrr_Int, + 13415 => Opcode::VMINSHZrrb_Int, + 13416 => Opcode::VMINSHZrrbk_Int, + 13417 => Opcode::VMINSHZrrbkz_Int, + 13418 => Opcode::VMINSHZrrk_Int, + 13419 => Opcode::VMINSHZrrkz_Int, + 13420 => Opcode::VMINSSZrm, + 13421 => Opcode::VMINSSZrm_Int, + 13422 => Opcode::VMINSSZrmk_Int, + 13423 => Opcode::VMINSSZrmkz_Int, + 13424 => Opcode::VMINSSZrr, + 13425 => Opcode::VMINSSZrr_Int, + 13426 => Opcode::VMINSSZrrb_Int, + 13427 => Opcode::VMINSSZrrbk_Int, + 13428 => Opcode::VMINSSZrrbkz_Int, + 13429 => Opcode::VMINSSZrrk_Int, + 13430 => Opcode::VMINSSZrrkz_Int, + 13431 => Opcode::VMINSSrm, + 13432 => Opcode::VMINSSrm_Int, + 13433 => Opcode::VMINSSrr, + 13434 => Opcode::VMINSSrr_Int, + 13435 => Opcode::VMLAUNCH, + 13436 => Opcode::VMLOAD32, + 13437 => Opcode::VMLOAD64, + 13438 => Opcode::VMMCALL, + 13439 => Opcode::VMOV64toPQIZrm, + 13440 => Opcode::VMOV64toPQIZrr, + 13441 => Opcode::VMOV64toPQIrm, + 13442 => Opcode::VMOV64toPQIrr, + 13443 => Opcode::VMOV64toSDZrr, + 13444 => Opcode::VMOV64toSDrr, + 13445 => Opcode::VMOVAPDYmr, + 13446 => Opcode::VMOVAPDYrm, + 13447 => Opcode::VMOVAPDYrr, + 13448 => Opcode::VMOVAPDYrr_REV, + 13449 => Opcode::VMOVAPDZ128mr, + 13450 => Opcode::VMOVAPDZ128mrk, + 13451 => Opcode::VMOVAPDZ128rm, + 13452 => Opcode::VMOVAPDZ128rmk, + 13453 => Opcode::VMOVAPDZ128rmkz, + 13454 => Opcode::VMOVAPDZ128rr, + 13455 => Opcode::VMOVAPDZ128rr_REV, + 13456 => Opcode::VMOVAPDZ128rrk, + 13457 => Opcode::VMOVAPDZ128rrk_REV, + 13458 => Opcode::VMOVAPDZ128rrkz, + 13459 => Opcode::VMOVAPDZ128rrkz_REV, + 13460 => Opcode::VMOVAPDZ256mr, + 13461 => Opcode::VMOVAPDZ256mrk, + 13462 => Opcode::VMOVAPDZ256rm, + 13463 => Opcode::VMOVAPDZ256rmk, + 13464 => Opcode::VMOVAPDZ256rmkz, + 13465 => Opcode::VMOVAPDZ256rr, + 13466 => Opcode::VMOVAPDZ256rr_REV, + 13467 => Opcode::VMOVAPDZ256rrk, + 13468 => Opcode::VMOVAPDZ256rrk_REV, + 13469 => Opcode::VMOVAPDZ256rrkz, + 13470 => Opcode::VMOVAPDZ256rrkz_REV, + 13471 => Opcode::VMOVAPDZmr, + 13472 => Opcode::VMOVAPDZmrk, + 13473 => Opcode::VMOVAPDZrm, + 13474 => Opcode::VMOVAPDZrmk, + 13475 => Opcode::VMOVAPDZrmkz, + 13476 => Opcode::VMOVAPDZrr, + 13477 => Opcode::VMOVAPDZrr_REV, + 13478 => Opcode::VMOVAPDZrrk, + 13479 => Opcode::VMOVAPDZrrk_REV, + 13480 => Opcode::VMOVAPDZrrkz, + 13481 => Opcode::VMOVAPDZrrkz_REV, + 13482 => Opcode::VMOVAPDmr, + 13483 => Opcode::VMOVAPDrm, + 13484 => Opcode::VMOVAPDrr, + 13485 => Opcode::VMOVAPDrr_REV, + 13486 => Opcode::VMOVAPSYmr, + 13487 => Opcode::VMOVAPSYrm, + 13488 => Opcode::VMOVAPSYrr, + 13489 => Opcode::VMOVAPSYrr_REV, + 13490 => Opcode::VMOVAPSZ128mr, + 13491 => Opcode::VMOVAPSZ128mrk, + 13492 => Opcode::VMOVAPSZ128rm, + 13493 => Opcode::VMOVAPSZ128rmk, + 13494 => Opcode::VMOVAPSZ128rmkz, + 13495 => Opcode::VMOVAPSZ128rr, + 13496 => Opcode::VMOVAPSZ128rr_REV, + 13497 => Opcode::VMOVAPSZ128rrk, + 13498 => Opcode::VMOVAPSZ128rrk_REV, + 13499 => Opcode::VMOVAPSZ128rrkz, + 13500 => Opcode::VMOVAPSZ128rrkz_REV, + 13501 => Opcode::VMOVAPSZ256mr, + 13502 => Opcode::VMOVAPSZ256mrk, + 13503 => Opcode::VMOVAPSZ256rm, + 13504 => Opcode::VMOVAPSZ256rmk, + 13505 => Opcode::VMOVAPSZ256rmkz, + 13506 => Opcode::VMOVAPSZ256rr, + 13507 => Opcode::VMOVAPSZ256rr_REV, + 13508 => Opcode::VMOVAPSZ256rrk, + 13509 => Opcode::VMOVAPSZ256rrk_REV, + 13510 => Opcode::VMOVAPSZ256rrkz, + 13511 => Opcode::VMOVAPSZ256rrkz_REV, + 13512 => Opcode::VMOVAPSZmr, + 13513 => Opcode::VMOVAPSZmrk, + 13514 => Opcode::VMOVAPSZrm, + 13515 => Opcode::VMOVAPSZrmk, + 13516 => Opcode::VMOVAPSZrmkz, + 13517 => Opcode::VMOVAPSZrr, + 13518 => Opcode::VMOVAPSZrr_REV, + 13519 => Opcode::VMOVAPSZrrk, + 13520 => Opcode::VMOVAPSZrrk_REV, + 13521 => Opcode::VMOVAPSZrrkz, + 13522 => Opcode::VMOVAPSZrrkz_REV, + 13523 => Opcode::VMOVAPSmr, + 13524 => Opcode::VMOVAPSrm, + 13525 => Opcode::VMOVAPSrr, + 13526 => Opcode::VMOVAPSrr_REV, + 13527 => Opcode::VMOVDDUPYrm, + 13528 => Opcode::VMOVDDUPYrr, + 13529 => Opcode::VMOVDDUPZ128rm, + 13530 => Opcode::VMOVDDUPZ128rmk, + 13531 => Opcode::VMOVDDUPZ128rmkz, + 13532 => Opcode::VMOVDDUPZ128rr, + 13533 => Opcode::VMOVDDUPZ128rrk, + 13534 => Opcode::VMOVDDUPZ128rrkz, + 13535 => Opcode::VMOVDDUPZ256rm, + 13536 => Opcode::VMOVDDUPZ256rmk, + 13537 => Opcode::VMOVDDUPZ256rmkz, + 13538 => Opcode::VMOVDDUPZ256rr, + 13539 => Opcode::VMOVDDUPZ256rrk, + 13540 => Opcode::VMOVDDUPZ256rrkz, + 13541 => Opcode::VMOVDDUPZrm, + 13542 => Opcode::VMOVDDUPZrmk, + 13543 => Opcode::VMOVDDUPZrmkz, + 13544 => Opcode::VMOVDDUPZrr, + 13545 => Opcode::VMOVDDUPZrrk, + 13546 => Opcode::VMOVDDUPZrrkz, + 13547 => Opcode::VMOVDDUPrm, + 13548 => Opcode::VMOVDDUPrr, + 13549 => Opcode::VMOVDI2PDIZrm, + 13550 => Opcode::VMOVDI2PDIZrr, + 13551 => Opcode::VMOVDI2PDIrm, + 13552 => Opcode::VMOVDI2PDIrr, + 13553 => Opcode::VMOVDI2SSZrr, + 13554 => Opcode::VMOVDI2SSrr, + 13555 => Opcode::VMOVDQA32Z128mr, + 13556 => Opcode::VMOVDQA32Z128mrk, + 13557 => Opcode::VMOVDQA32Z128rm, + 13558 => Opcode::VMOVDQA32Z128rmk, + 13559 => Opcode::VMOVDQA32Z128rmkz, + 13560 => Opcode::VMOVDQA32Z128rr, + 13561 => Opcode::VMOVDQA32Z128rr_REV, + 13562 => Opcode::VMOVDQA32Z128rrk, + 13563 => Opcode::VMOVDQA32Z128rrk_REV, + 13564 => Opcode::VMOVDQA32Z128rrkz, + 13565 => Opcode::VMOVDQA32Z128rrkz_REV, + 13566 => Opcode::VMOVDQA32Z256mr, + 13567 => Opcode::VMOVDQA32Z256mrk, + 13568 => Opcode::VMOVDQA32Z256rm, + 13569 => Opcode::VMOVDQA32Z256rmk, + 13570 => Opcode::VMOVDQA32Z256rmkz, + 13571 => Opcode::VMOVDQA32Z256rr, + 13572 => Opcode::VMOVDQA32Z256rr_REV, + 13573 => Opcode::VMOVDQA32Z256rrk, + 13574 => Opcode::VMOVDQA32Z256rrk_REV, + 13575 => Opcode::VMOVDQA32Z256rrkz, + 13576 => Opcode::VMOVDQA32Z256rrkz_REV, + 13577 => Opcode::VMOVDQA32Zmr, + 13578 => Opcode::VMOVDQA32Zmrk, + 13579 => Opcode::VMOVDQA32Zrm, + 13580 => Opcode::VMOVDQA32Zrmk, + 13581 => Opcode::VMOVDQA32Zrmkz, + 13582 => Opcode::VMOVDQA32Zrr, + 13583 => Opcode::VMOVDQA32Zrr_REV, + 13584 => Opcode::VMOVDQA32Zrrk, + 13585 => Opcode::VMOVDQA32Zrrk_REV, + 13586 => Opcode::VMOVDQA32Zrrkz, + 13587 => Opcode::VMOVDQA32Zrrkz_REV, + 13588 => Opcode::VMOVDQA64Z128mr, + 13589 => Opcode::VMOVDQA64Z128mrk, + 13590 => Opcode::VMOVDQA64Z128rm, + 13591 => Opcode::VMOVDQA64Z128rmk, + 13592 => Opcode::VMOVDQA64Z128rmkz, + 13593 => Opcode::VMOVDQA64Z128rr, + 13594 => Opcode::VMOVDQA64Z128rr_REV, + 13595 => Opcode::VMOVDQA64Z128rrk, + 13596 => Opcode::VMOVDQA64Z128rrk_REV, + 13597 => Opcode::VMOVDQA64Z128rrkz, + 13598 => Opcode::VMOVDQA64Z128rrkz_REV, + 13599 => Opcode::VMOVDQA64Z256mr, + 13600 => Opcode::VMOVDQA64Z256mrk, + 13601 => Opcode::VMOVDQA64Z256rm, + 13602 => Opcode::VMOVDQA64Z256rmk, + 13603 => Opcode::VMOVDQA64Z256rmkz, + 13604 => Opcode::VMOVDQA64Z256rr, + 13605 => Opcode::VMOVDQA64Z256rr_REV, + 13606 => Opcode::VMOVDQA64Z256rrk, + 13607 => Opcode::VMOVDQA64Z256rrk_REV, + 13608 => Opcode::VMOVDQA64Z256rrkz, + 13609 => Opcode::VMOVDQA64Z256rrkz_REV, + 13610 => Opcode::VMOVDQA64Zmr, + 13611 => Opcode::VMOVDQA64Zmrk, + 13612 => Opcode::VMOVDQA64Zrm, + 13613 => Opcode::VMOVDQA64Zrmk, + 13614 => Opcode::VMOVDQA64Zrmkz, + 13615 => Opcode::VMOVDQA64Zrr, + 13616 => Opcode::VMOVDQA64Zrr_REV, + 13617 => Opcode::VMOVDQA64Zrrk, + 13618 => Opcode::VMOVDQA64Zrrk_REV, + 13619 => Opcode::VMOVDQA64Zrrkz, + 13620 => Opcode::VMOVDQA64Zrrkz_REV, + 13621 => Opcode::VMOVDQAYmr, + 13622 => Opcode::VMOVDQAYrm, + 13623 => Opcode::VMOVDQAYrr, + 13624 => Opcode::VMOVDQAYrr_REV, + 13625 => Opcode::VMOVDQAmr, + 13626 => Opcode::VMOVDQArm, + 13627 => Opcode::VMOVDQArr, + 13628 => Opcode::VMOVDQArr_REV, + 13629 => Opcode::VMOVDQU16Z128mr, + 13630 => Opcode::VMOVDQU16Z128mrk, + 13631 => Opcode::VMOVDQU16Z128rm, + 13632 => Opcode::VMOVDQU16Z128rmk, + 13633 => Opcode::VMOVDQU16Z128rmkz, + 13634 => Opcode::VMOVDQU16Z128rr, + 13635 => Opcode::VMOVDQU16Z128rr_REV, + 13636 => Opcode::VMOVDQU16Z128rrk, + 13637 => Opcode::VMOVDQU16Z128rrk_REV, + 13638 => Opcode::VMOVDQU16Z128rrkz, + 13639 => Opcode::VMOVDQU16Z128rrkz_REV, + 13640 => Opcode::VMOVDQU16Z256mr, + 13641 => Opcode::VMOVDQU16Z256mrk, + 13642 => Opcode::VMOVDQU16Z256rm, + 13643 => Opcode::VMOVDQU16Z256rmk, + 13644 => Opcode::VMOVDQU16Z256rmkz, + 13645 => Opcode::VMOVDQU16Z256rr, + 13646 => Opcode::VMOVDQU16Z256rr_REV, + 13647 => Opcode::VMOVDQU16Z256rrk, + 13648 => Opcode::VMOVDQU16Z256rrk_REV, + 13649 => Opcode::VMOVDQU16Z256rrkz, + 13650 => Opcode::VMOVDQU16Z256rrkz_REV, + 13651 => Opcode::VMOVDQU16Zmr, + 13652 => Opcode::VMOVDQU16Zmrk, + 13653 => Opcode::VMOVDQU16Zrm, + 13654 => Opcode::VMOVDQU16Zrmk, + 13655 => Opcode::VMOVDQU16Zrmkz, + 13656 => Opcode::VMOVDQU16Zrr, + 13657 => Opcode::VMOVDQU16Zrr_REV, + 13658 => Opcode::VMOVDQU16Zrrk, + 13659 => Opcode::VMOVDQU16Zrrk_REV, + 13660 => Opcode::VMOVDQU16Zrrkz, + 13661 => Opcode::VMOVDQU16Zrrkz_REV, + 13662 => Opcode::VMOVDQU32Z128mr, + 13663 => Opcode::VMOVDQU32Z128mrk, + 13664 => Opcode::VMOVDQU32Z128rm, + 13665 => Opcode::VMOVDQU32Z128rmk, + 13666 => Opcode::VMOVDQU32Z128rmkz, + 13667 => Opcode::VMOVDQU32Z128rr, + 13668 => Opcode::VMOVDQU32Z128rr_REV, + 13669 => Opcode::VMOVDQU32Z128rrk, + 13670 => Opcode::VMOVDQU32Z128rrk_REV, + 13671 => Opcode::VMOVDQU32Z128rrkz, + 13672 => Opcode::VMOVDQU32Z128rrkz_REV, + 13673 => Opcode::VMOVDQU32Z256mr, + 13674 => Opcode::VMOVDQU32Z256mrk, + 13675 => Opcode::VMOVDQU32Z256rm, + 13676 => Opcode::VMOVDQU32Z256rmk, + 13677 => Opcode::VMOVDQU32Z256rmkz, + 13678 => Opcode::VMOVDQU32Z256rr, + 13679 => Opcode::VMOVDQU32Z256rr_REV, + 13680 => Opcode::VMOVDQU32Z256rrk, + 13681 => Opcode::VMOVDQU32Z256rrk_REV, + 13682 => Opcode::VMOVDQU32Z256rrkz, + 13683 => Opcode::VMOVDQU32Z256rrkz_REV, + 13684 => Opcode::VMOVDQU32Zmr, + 13685 => Opcode::VMOVDQU32Zmrk, + 13686 => Opcode::VMOVDQU32Zrm, + 13687 => Opcode::VMOVDQU32Zrmk, + 13688 => Opcode::VMOVDQU32Zrmkz, + 13689 => Opcode::VMOVDQU32Zrr, + 13690 => Opcode::VMOVDQU32Zrr_REV, + 13691 => Opcode::VMOVDQU32Zrrk, + 13692 => Opcode::VMOVDQU32Zrrk_REV, + 13693 => Opcode::VMOVDQU32Zrrkz, + 13694 => Opcode::VMOVDQU32Zrrkz_REV, + 13695 => Opcode::VMOVDQU64Z128mr, + 13696 => Opcode::VMOVDQU64Z128mrk, + 13697 => Opcode::VMOVDQU64Z128rm, + 13698 => Opcode::VMOVDQU64Z128rmk, + 13699 => Opcode::VMOVDQU64Z128rmkz, + 13700 => Opcode::VMOVDQU64Z128rr, + 13701 => Opcode::VMOVDQU64Z128rr_REV, + 13702 => Opcode::VMOVDQU64Z128rrk, + 13703 => Opcode::VMOVDQU64Z128rrk_REV, + 13704 => Opcode::VMOVDQU64Z128rrkz, + 13705 => Opcode::VMOVDQU64Z128rrkz_REV, + 13706 => Opcode::VMOVDQU64Z256mr, + 13707 => Opcode::VMOVDQU64Z256mrk, + 13708 => Opcode::VMOVDQU64Z256rm, + 13709 => Opcode::VMOVDQU64Z256rmk, + 13710 => Opcode::VMOVDQU64Z256rmkz, + 13711 => Opcode::VMOVDQU64Z256rr, + 13712 => Opcode::VMOVDQU64Z256rr_REV, + 13713 => Opcode::VMOVDQU64Z256rrk, + 13714 => Opcode::VMOVDQU64Z256rrk_REV, + 13715 => Opcode::VMOVDQU64Z256rrkz, + 13716 => Opcode::VMOVDQU64Z256rrkz_REV, + 13717 => Opcode::VMOVDQU64Zmr, + 13718 => Opcode::VMOVDQU64Zmrk, + 13719 => Opcode::VMOVDQU64Zrm, + 13720 => Opcode::VMOVDQU64Zrmk, + 13721 => Opcode::VMOVDQU64Zrmkz, + 13722 => Opcode::VMOVDQU64Zrr, + 13723 => Opcode::VMOVDQU64Zrr_REV, + 13724 => Opcode::VMOVDQU64Zrrk, + 13725 => Opcode::VMOVDQU64Zrrk_REV, + 13726 => Opcode::VMOVDQU64Zrrkz, + 13727 => Opcode::VMOVDQU64Zrrkz_REV, + 13728 => Opcode::VMOVDQU8Z128mr, + 13729 => Opcode::VMOVDQU8Z128mrk, + 13730 => Opcode::VMOVDQU8Z128rm, + 13731 => Opcode::VMOVDQU8Z128rmk, + 13732 => Opcode::VMOVDQU8Z128rmkz, + 13733 => Opcode::VMOVDQU8Z128rr, + 13734 => Opcode::VMOVDQU8Z128rr_REV, + 13735 => Opcode::VMOVDQU8Z128rrk, + 13736 => Opcode::VMOVDQU8Z128rrk_REV, + 13737 => Opcode::VMOVDQU8Z128rrkz, + 13738 => Opcode::VMOVDQU8Z128rrkz_REV, + 13739 => Opcode::VMOVDQU8Z256mr, + 13740 => Opcode::VMOVDQU8Z256mrk, + 13741 => Opcode::VMOVDQU8Z256rm, + 13742 => Opcode::VMOVDQU8Z256rmk, + 13743 => Opcode::VMOVDQU8Z256rmkz, + 13744 => Opcode::VMOVDQU8Z256rr, + 13745 => Opcode::VMOVDQU8Z256rr_REV, + 13746 => Opcode::VMOVDQU8Z256rrk, + 13747 => Opcode::VMOVDQU8Z256rrk_REV, + 13748 => Opcode::VMOVDQU8Z256rrkz, + 13749 => Opcode::VMOVDQU8Z256rrkz_REV, + 13750 => Opcode::VMOVDQU8Zmr, + 13751 => Opcode::VMOVDQU8Zmrk, + 13752 => Opcode::VMOVDQU8Zrm, + 13753 => Opcode::VMOVDQU8Zrmk, + 13754 => Opcode::VMOVDQU8Zrmkz, + 13755 => Opcode::VMOVDQU8Zrr, + 13756 => Opcode::VMOVDQU8Zrr_REV, + 13757 => Opcode::VMOVDQU8Zrrk, + 13758 => Opcode::VMOVDQU8Zrrk_REV, + 13759 => Opcode::VMOVDQU8Zrrkz, + 13760 => Opcode::VMOVDQU8Zrrkz_REV, + 13761 => Opcode::VMOVDQUYmr, + 13762 => Opcode::VMOVDQUYrm, + 13763 => Opcode::VMOVDQUYrr, + 13764 => Opcode::VMOVDQUYrr_REV, + 13765 => Opcode::VMOVDQUmr, + 13766 => Opcode::VMOVDQUrm, + 13767 => Opcode::VMOVDQUrr, + 13768 => Opcode::VMOVDQUrr_REV, + 13769 => Opcode::VMOVHLPSZrr, + 13770 => Opcode::VMOVHLPSrr, + 13771 => Opcode::VMOVHPDZ128mr, + 13772 => Opcode::VMOVHPDZ128rm, + 13773 => Opcode::VMOVHPDmr, + 13774 => Opcode::VMOVHPDrm, + 13775 => Opcode::VMOVHPSZ128mr, + 13776 => Opcode::VMOVHPSZ128rm, + 13777 => Opcode::VMOVHPSmr, + 13778 => Opcode::VMOVHPSrm, + 13779 => Opcode::VMOVLHPSZrr, + 13780 => Opcode::VMOVLHPSrr, + 13781 => Opcode::VMOVLPDZ128mr, + 13782 => Opcode::VMOVLPDZ128rm, + 13783 => Opcode::VMOVLPDmr, + 13784 => Opcode::VMOVLPDrm, + 13785 => Opcode::VMOVLPSZ128mr, + 13786 => Opcode::VMOVLPSZ128rm, + 13787 => Opcode::VMOVLPSmr, + 13788 => Opcode::VMOVLPSrm, + 13789 => Opcode::VMOVMSKPDYrr, + 13790 => Opcode::VMOVMSKPDrr, + 13791 => Opcode::VMOVMSKPSYrr, + 13792 => Opcode::VMOVMSKPSrr, + 13793 => Opcode::VMOVNTDQAYrm, + 13794 => Opcode::VMOVNTDQAZ128rm, + 13795 => Opcode::VMOVNTDQAZ256rm, + 13796 => Opcode::VMOVNTDQAZrm, + 13797 => Opcode::VMOVNTDQArm, + 13798 => Opcode::VMOVNTDQYmr, + 13799 => Opcode::VMOVNTDQZ128mr, + 13800 => Opcode::VMOVNTDQZ256mr, + 13801 => Opcode::VMOVNTDQZmr, + 13802 => Opcode::VMOVNTDQmr, + 13803 => Opcode::VMOVNTPDYmr, + 13804 => Opcode::VMOVNTPDZ128mr, + 13805 => Opcode::VMOVNTPDZ256mr, + 13806 => Opcode::VMOVNTPDZmr, + 13807 => Opcode::VMOVNTPDmr, + 13808 => Opcode::VMOVNTPSYmr, + 13809 => Opcode::VMOVNTPSZ128mr, + 13810 => Opcode::VMOVNTPSZ256mr, + 13811 => Opcode::VMOVNTPSZmr, + 13812 => Opcode::VMOVNTPSmr, + 13813 => Opcode::VMOVPDI2DIZmr, + 13814 => Opcode::VMOVPDI2DIZrr, + 13815 => Opcode::VMOVPDI2DImr, + 13816 => Opcode::VMOVPDI2DIrr, + 13817 => Opcode::VMOVPQI2QIZmr, + 13818 => Opcode::VMOVPQI2QIZrr, + 13819 => Opcode::VMOVPQI2QImr, + 13820 => Opcode::VMOVPQI2QIrr, + 13821 => Opcode::VMOVPQIto64Zmr, + 13822 => Opcode::VMOVPQIto64Zrr, + 13823 => Opcode::VMOVPQIto64mr, + 13824 => Opcode::VMOVPQIto64rr, + 13825 => Opcode::VMOVQI2PQIZrm, + 13826 => Opcode::VMOVQI2PQIrm, + 13827 => Opcode::VMOVRSBZ128m, + 13828 => Opcode::VMOVRSBZ128mk, + 13829 => Opcode::VMOVRSBZ128mkz, + 13830 => Opcode::VMOVRSBZ256m, + 13831 => Opcode::VMOVRSBZ256mk, + 13832 => Opcode::VMOVRSBZ256mkz, + 13833 => Opcode::VMOVRSBZm, + 13834 => Opcode::VMOVRSBZmk, + 13835 => Opcode::VMOVRSBZmkz, + 13836 => Opcode::VMOVRSDZ128m, + 13837 => Opcode::VMOVRSDZ128mk, + 13838 => Opcode::VMOVRSDZ128mkz, + 13839 => Opcode::VMOVRSDZ256m, + 13840 => Opcode::VMOVRSDZ256mk, + 13841 => Opcode::VMOVRSDZ256mkz, + 13842 => Opcode::VMOVRSDZm, + 13843 => Opcode::VMOVRSDZmk, + 13844 => Opcode::VMOVRSDZmkz, + 13845 => Opcode::VMOVRSQZ128m, + 13846 => Opcode::VMOVRSQZ128mk, + 13847 => Opcode::VMOVRSQZ128mkz, + 13848 => Opcode::VMOVRSQZ256m, + 13849 => Opcode::VMOVRSQZ256mk, + 13850 => Opcode::VMOVRSQZ256mkz, + 13851 => Opcode::VMOVRSQZm, + 13852 => Opcode::VMOVRSQZmk, + 13853 => Opcode::VMOVRSQZmkz, + 13854 => Opcode::VMOVRSWZ128m, + 13855 => Opcode::VMOVRSWZ128mk, + 13856 => Opcode::VMOVRSWZ128mkz, + 13857 => Opcode::VMOVRSWZ256m, + 13858 => Opcode::VMOVRSWZ256mk, + 13859 => Opcode::VMOVRSWZ256mkz, + 13860 => Opcode::VMOVRSWZm, + 13861 => Opcode::VMOVRSWZmk, + 13862 => Opcode::VMOVRSWZmkz, + 13863 => Opcode::VMOVSDZmr, + 13864 => Opcode::VMOVSDZmrk, + 13865 => Opcode::VMOVSDZrm, + 13866 => Opcode::VMOVSDZrm_alt, + 13867 => Opcode::VMOVSDZrmk, + 13868 => Opcode::VMOVSDZrmkz, + 13869 => Opcode::VMOVSDZrr, + 13870 => Opcode::VMOVSDZrr_REV, + 13871 => Opcode::VMOVSDZrrk, + 13872 => Opcode::VMOVSDZrrk_REV, + 13873 => Opcode::VMOVSDZrrkz, + 13874 => Opcode::VMOVSDZrrkz_REV, + 13875 => Opcode::VMOVSDmr, + 13876 => Opcode::VMOVSDrm, + 13877 => Opcode::VMOVSDrm_alt, + 13878 => Opcode::VMOVSDrr, + 13879 => Opcode::VMOVSDrr_REV, + 13880 => Opcode::VMOVSDto64Zrr, + 13881 => Opcode::VMOVSDto64rr, + 13882 => Opcode::VMOVSH2Wrr, + 13883 => Opcode::VMOVSHDUPYrm, + 13884 => Opcode::VMOVSHDUPYrr, + 13885 => Opcode::VMOVSHDUPZ128rm, + 13886 => Opcode::VMOVSHDUPZ128rmk, + 13887 => Opcode::VMOVSHDUPZ128rmkz, + 13888 => Opcode::VMOVSHDUPZ128rr, + 13889 => Opcode::VMOVSHDUPZ128rrk, + 13890 => Opcode::VMOVSHDUPZ128rrkz, + 13891 => Opcode::VMOVSHDUPZ256rm, + 13892 => Opcode::VMOVSHDUPZ256rmk, + 13893 => Opcode::VMOVSHDUPZ256rmkz, + 13894 => Opcode::VMOVSHDUPZ256rr, + 13895 => Opcode::VMOVSHDUPZ256rrk, + 13896 => Opcode::VMOVSHDUPZ256rrkz, + 13897 => Opcode::VMOVSHDUPZrm, + 13898 => Opcode::VMOVSHDUPZrmk, + 13899 => Opcode::VMOVSHDUPZrmkz, + 13900 => Opcode::VMOVSHDUPZrr, + 13901 => Opcode::VMOVSHDUPZrrk, + 13902 => Opcode::VMOVSHDUPZrrkz, + 13903 => Opcode::VMOVSHDUPrm, + 13904 => Opcode::VMOVSHDUPrr, + 13905 => Opcode::VMOVSHZmr, + 13906 => Opcode::VMOVSHZmrk, + 13907 => Opcode::VMOVSHZrm, + 13908 => Opcode::VMOVSHZrm_alt, + 13909 => Opcode::VMOVSHZrmk, + 13910 => Opcode::VMOVSHZrmkz, + 13911 => Opcode::VMOVSHZrr, + 13912 => Opcode::VMOVSHZrr_REV, + 13913 => Opcode::VMOVSHZrrk, + 13914 => Opcode::VMOVSHZrrk_REV, + 13915 => Opcode::VMOVSHZrrkz, + 13916 => Opcode::VMOVSHZrrkz_REV, + 13917 => Opcode::VMOVSHtoW64rr, + 13918 => Opcode::VMOVSLDUPYrm, + 13919 => Opcode::VMOVSLDUPYrr, + 13920 => Opcode::VMOVSLDUPZ128rm, + 13921 => Opcode::VMOVSLDUPZ128rmk, + 13922 => Opcode::VMOVSLDUPZ128rmkz, + 13923 => Opcode::VMOVSLDUPZ128rr, + 13924 => Opcode::VMOVSLDUPZ128rrk, + 13925 => Opcode::VMOVSLDUPZ128rrkz, + 13926 => Opcode::VMOVSLDUPZ256rm, + 13927 => Opcode::VMOVSLDUPZ256rmk, + 13928 => Opcode::VMOVSLDUPZ256rmkz, + 13929 => Opcode::VMOVSLDUPZ256rr, + 13930 => Opcode::VMOVSLDUPZ256rrk, + 13931 => Opcode::VMOVSLDUPZ256rrkz, + 13932 => Opcode::VMOVSLDUPZrm, + 13933 => Opcode::VMOVSLDUPZrmk, + 13934 => Opcode::VMOVSLDUPZrmkz, + 13935 => Opcode::VMOVSLDUPZrr, + 13936 => Opcode::VMOVSLDUPZrrk, + 13937 => Opcode::VMOVSLDUPZrrkz, + 13938 => Opcode::VMOVSLDUPrm, + 13939 => Opcode::VMOVSLDUPrr, + 13940 => Opcode::VMOVSS2DIZrr, + 13941 => Opcode::VMOVSS2DIrr, + 13942 => Opcode::VMOVSSZmr, + 13943 => Opcode::VMOVSSZmrk, + 13944 => Opcode::VMOVSSZrm, + 13945 => Opcode::VMOVSSZrm_alt, + 13946 => Opcode::VMOVSSZrmk, + 13947 => Opcode::VMOVSSZrmkz, + 13948 => Opcode::VMOVSSZrr, + 13949 => Opcode::VMOVSSZrr_REV, + 13950 => Opcode::VMOVSSZrrk, + 13951 => Opcode::VMOVSSZrrk_REV, + 13952 => Opcode::VMOVSSZrrkz, + 13953 => Opcode::VMOVSSZrrkz_REV, + 13954 => Opcode::VMOVSSmr, + 13955 => Opcode::VMOVSSrm, + 13956 => Opcode::VMOVSSrm_alt, + 13957 => Opcode::VMOVSSrr, + 13958 => Opcode::VMOVSSrr_REV, + 13959 => Opcode::VMOVUPDYmr, + 13960 => Opcode::VMOVUPDYrm, + 13961 => Opcode::VMOVUPDYrr, + 13962 => Opcode::VMOVUPDYrr_REV, + 13963 => Opcode::VMOVUPDZ128mr, + 13964 => Opcode::VMOVUPDZ128mrk, + 13965 => Opcode::VMOVUPDZ128rm, + 13966 => Opcode::VMOVUPDZ128rmk, + 13967 => Opcode::VMOVUPDZ128rmkz, + 13968 => Opcode::VMOVUPDZ128rr, + 13969 => Opcode::VMOVUPDZ128rr_REV, + 13970 => Opcode::VMOVUPDZ128rrk, + 13971 => Opcode::VMOVUPDZ128rrk_REV, + 13972 => Opcode::VMOVUPDZ128rrkz, + 13973 => Opcode::VMOVUPDZ128rrkz_REV, + 13974 => Opcode::VMOVUPDZ256mr, + 13975 => Opcode::VMOVUPDZ256mrk, + 13976 => Opcode::VMOVUPDZ256rm, + 13977 => Opcode::VMOVUPDZ256rmk, + 13978 => Opcode::VMOVUPDZ256rmkz, + 13979 => Opcode::VMOVUPDZ256rr, + 13980 => Opcode::VMOVUPDZ256rr_REV, + 13981 => Opcode::VMOVUPDZ256rrk, + 13982 => Opcode::VMOVUPDZ256rrk_REV, + 13983 => Opcode::VMOVUPDZ256rrkz, + 13984 => Opcode::VMOVUPDZ256rrkz_REV, + 13985 => Opcode::VMOVUPDZmr, + 13986 => Opcode::VMOVUPDZmrk, + 13987 => Opcode::VMOVUPDZrm, + 13988 => Opcode::VMOVUPDZrmk, + 13989 => Opcode::VMOVUPDZrmkz, + 13990 => Opcode::VMOVUPDZrr, + 13991 => Opcode::VMOVUPDZrr_REV, + 13992 => Opcode::VMOVUPDZrrk, + 13993 => Opcode::VMOVUPDZrrk_REV, + 13994 => Opcode::VMOVUPDZrrkz, + 13995 => Opcode::VMOVUPDZrrkz_REV, + 13996 => Opcode::VMOVUPDmr, + 13997 => Opcode::VMOVUPDrm, + 13998 => Opcode::VMOVUPDrr, + 13999 => Opcode::VMOVUPDrr_REV, + 14000 => Opcode::VMOVUPSYmr, + 14001 => Opcode::VMOVUPSYrm, + 14002 => Opcode::VMOVUPSYrr, + 14003 => Opcode::VMOVUPSYrr_REV, + 14004 => Opcode::VMOVUPSZ128mr, + 14005 => Opcode::VMOVUPSZ128mrk, + 14006 => Opcode::VMOVUPSZ128rm, + 14007 => Opcode::VMOVUPSZ128rmk, + 14008 => Opcode::VMOVUPSZ128rmkz, + 14009 => Opcode::VMOVUPSZ128rr, + 14010 => Opcode::VMOVUPSZ128rr_REV, + 14011 => Opcode::VMOVUPSZ128rrk, + 14012 => Opcode::VMOVUPSZ128rrk_REV, + 14013 => Opcode::VMOVUPSZ128rrkz, + 14014 => Opcode::VMOVUPSZ128rrkz_REV, + 14015 => Opcode::VMOVUPSZ256mr, + 14016 => Opcode::VMOVUPSZ256mrk, + 14017 => Opcode::VMOVUPSZ256rm, + 14018 => Opcode::VMOVUPSZ256rmk, + 14019 => Opcode::VMOVUPSZ256rmkz, + 14020 => Opcode::VMOVUPSZ256rr, + 14021 => Opcode::VMOVUPSZ256rr_REV, + 14022 => Opcode::VMOVUPSZ256rrk, + 14023 => Opcode::VMOVUPSZ256rrk_REV, + 14024 => Opcode::VMOVUPSZ256rrkz, + 14025 => Opcode::VMOVUPSZ256rrkz_REV, + 14026 => Opcode::VMOVUPSZmr, + 14027 => Opcode::VMOVUPSZmrk, + 14028 => Opcode::VMOVUPSZrm, + 14029 => Opcode::VMOVUPSZrmk, + 14030 => Opcode::VMOVUPSZrmkz, + 14031 => Opcode::VMOVUPSZrr, + 14032 => Opcode::VMOVUPSZrr_REV, + 14033 => Opcode::VMOVUPSZrrk, + 14034 => Opcode::VMOVUPSZrrk_REV, + 14035 => Opcode::VMOVUPSZrrkz, + 14036 => Opcode::VMOVUPSZrrkz_REV, + 14037 => Opcode::VMOVUPSmr, + 14038 => Opcode::VMOVUPSrm, + 14039 => Opcode::VMOVUPSrr, + 14040 => Opcode::VMOVUPSrr_REV, + 14041 => Opcode::VMOVW2SHrr, + 14042 => Opcode::VMOVW64toSHrr, + 14043 => Opcode::VMOVWmr, + 14044 => Opcode::VMOVWrm, + 14045 => Opcode::VMOVZPDILo2PDIZmr, + 14046 => Opcode::VMOVZPDILo2PDIZrm, + 14047 => Opcode::VMOVZPDILo2PDIZrr, + 14048 => Opcode::VMOVZPDILo2PDIZrr2, + 14049 => Opcode::VMOVZPQILo2PQIZrr, + 14050 => Opcode::VMOVZPQILo2PQIrr, + 14051 => Opcode::VMOVZPWILo2PWIZmr, + 14052 => Opcode::VMOVZPWILo2PWIZrm, + 14053 => Opcode::VMOVZPWILo2PWIZrr, + 14054 => Opcode::VMOVZPWILo2PWIZrr2, + 14055 => Opcode::VMPSADBWYrmi, + 14056 => Opcode::VMPSADBWYrri, + 14057 => Opcode::VMPSADBWZ128rmi, + 14058 => Opcode::VMPSADBWZ128rmik, + 14059 => Opcode::VMPSADBWZ128rmikz, + 14060 => Opcode::VMPSADBWZ128rri, + 14061 => Opcode::VMPSADBWZ128rrik, + 14062 => Opcode::VMPSADBWZ128rrikz, + 14063 => Opcode::VMPSADBWZ256rmi, + 14064 => Opcode::VMPSADBWZ256rmik, + 14065 => Opcode::VMPSADBWZ256rmikz, + 14066 => Opcode::VMPSADBWZ256rri, + 14067 => Opcode::VMPSADBWZ256rrik, + 14068 => Opcode::VMPSADBWZ256rrikz, + 14069 => Opcode::VMPSADBWZrmi, + 14070 => Opcode::VMPSADBWZrmik, + 14071 => Opcode::VMPSADBWZrmikz, + 14072 => Opcode::VMPSADBWZrri, + 14073 => Opcode::VMPSADBWZrrik, + 14074 => Opcode::VMPSADBWZrrikz, + 14075 => Opcode::VMPSADBWrmi, + 14076 => Opcode::VMPSADBWrri, + 14077 => Opcode::VMPTRLDm, + 14078 => Opcode::VMPTRSTm, + 14079 => Opcode::VMREAD32mr, + 14080 => Opcode::VMREAD32rr, + 14081 => Opcode::VMREAD64mr, + 14082 => Opcode::VMREAD64rr, + 14083 => Opcode::VMRESUME, + 14084 => Opcode::VMRUN32, + 14085 => Opcode::VMRUN64, + 14086 => Opcode::VMSAVE32, + 14087 => Opcode::VMSAVE64, + 14088 => Opcode::VMULBF16Z128rm, + 14089 => Opcode::VMULBF16Z128rmb, + 14090 => Opcode::VMULBF16Z128rmbk, + 14091 => Opcode::VMULBF16Z128rmbkz, + 14092 => Opcode::VMULBF16Z128rmk, + 14093 => Opcode::VMULBF16Z128rmkz, + 14094 => Opcode::VMULBF16Z128rr, + 14095 => Opcode::VMULBF16Z128rrk, + 14096 => Opcode::VMULBF16Z128rrkz, + 14097 => Opcode::VMULBF16Z256rm, + 14098 => Opcode::VMULBF16Z256rmb, + 14099 => Opcode::VMULBF16Z256rmbk, + 14100 => Opcode::VMULBF16Z256rmbkz, + 14101 => Opcode::VMULBF16Z256rmk, + 14102 => Opcode::VMULBF16Z256rmkz, + 14103 => Opcode::VMULBF16Z256rr, + 14104 => Opcode::VMULBF16Z256rrk, + 14105 => Opcode::VMULBF16Z256rrkz, + 14106 => Opcode::VMULBF16Zrm, + 14107 => Opcode::VMULBF16Zrmb, + 14108 => Opcode::VMULBF16Zrmbk, + 14109 => Opcode::VMULBF16Zrmbkz, + 14110 => Opcode::VMULBF16Zrmk, + 14111 => Opcode::VMULBF16Zrmkz, + 14112 => Opcode::VMULBF16Zrr, + 14113 => Opcode::VMULBF16Zrrk, + 14114 => Opcode::VMULBF16Zrrkz, + 14115 => Opcode::VMULPDYrm, + 14116 => Opcode::VMULPDYrr, + 14117 => Opcode::VMULPDZ128rm, + 14118 => Opcode::VMULPDZ128rmb, + 14119 => Opcode::VMULPDZ128rmbk, + 14120 => Opcode::VMULPDZ128rmbkz, + 14121 => Opcode::VMULPDZ128rmk, + 14122 => Opcode::VMULPDZ128rmkz, + 14123 => Opcode::VMULPDZ128rr, + 14124 => Opcode::VMULPDZ128rrk, + 14125 => Opcode::VMULPDZ128rrkz, + 14126 => Opcode::VMULPDZ256rm, + 14127 => Opcode::VMULPDZ256rmb, + 14128 => Opcode::VMULPDZ256rmbk, + 14129 => Opcode::VMULPDZ256rmbkz, + 14130 => Opcode::VMULPDZ256rmk, + 14131 => Opcode::VMULPDZ256rmkz, + 14132 => Opcode::VMULPDZ256rr, + 14133 => Opcode::VMULPDZ256rrk, + 14134 => Opcode::VMULPDZ256rrkz, + 14135 => Opcode::VMULPDZrm, + 14136 => Opcode::VMULPDZrmb, + 14137 => Opcode::VMULPDZrmbk, + 14138 => Opcode::VMULPDZrmbkz, + 14139 => Opcode::VMULPDZrmk, + 14140 => Opcode::VMULPDZrmkz, + 14141 => Opcode::VMULPDZrr, + 14142 => Opcode::VMULPDZrrb, + 14143 => Opcode::VMULPDZrrbk, + 14144 => Opcode::VMULPDZrrbkz, + 14145 => Opcode::VMULPDZrrk, + 14146 => Opcode::VMULPDZrrkz, + 14147 => Opcode::VMULPDrm, + 14148 => Opcode::VMULPDrr, + 14149 => Opcode::VMULPHZ128rm, + 14150 => Opcode::VMULPHZ128rmb, + 14151 => Opcode::VMULPHZ128rmbk, + 14152 => Opcode::VMULPHZ128rmbkz, + 14153 => Opcode::VMULPHZ128rmk, + 14154 => Opcode::VMULPHZ128rmkz, + 14155 => Opcode::VMULPHZ128rr, + 14156 => Opcode::VMULPHZ128rrk, + 14157 => Opcode::VMULPHZ128rrkz, + 14158 => Opcode::VMULPHZ256rm, + 14159 => Opcode::VMULPHZ256rmb, + 14160 => Opcode::VMULPHZ256rmbk, + 14161 => Opcode::VMULPHZ256rmbkz, + 14162 => Opcode::VMULPHZ256rmk, + 14163 => Opcode::VMULPHZ256rmkz, + 14164 => Opcode::VMULPHZ256rr, + 14165 => Opcode::VMULPHZ256rrk, + 14166 => Opcode::VMULPHZ256rrkz, + 14167 => Opcode::VMULPHZrm, + 14168 => Opcode::VMULPHZrmb, + 14169 => Opcode::VMULPHZrmbk, + 14170 => Opcode::VMULPHZrmbkz, + 14171 => Opcode::VMULPHZrmk, + 14172 => Opcode::VMULPHZrmkz, + 14173 => Opcode::VMULPHZrr, + 14174 => Opcode::VMULPHZrrb, + 14175 => Opcode::VMULPHZrrbk, + 14176 => Opcode::VMULPHZrrbkz, + 14177 => Opcode::VMULPHZrrk, + 14178 => Opcode::VMULPHZrrkz, + 14179 => Opcode::VMULPSYrm, + 14180 => Opcode::VMULPSYrr, + 14181 => Opcode::VMULPSZ128rm, + 14182 => Opcode::VMULPSZ128rmb, + 14183 => Opcode::VMULPSZ128rmbk, + 14184 => Opcode::VMULPSZ128rmbkz, + 14185 => Opcode::VMULPSZ128rmk, + 14186 => Opcode::VMULPSZ128rmkz, + 14187 => Opcode::VMULPSZ128rr, + 14188 => Opcode::VMULPSZ128rrk, + 14189 => Opcode::VMULPSZ128rrkz, + 14190 => Opcode::VMULPSZ256rm, + 14191 => Opcode::VMULPSZ256rmb, + 14192 => Opcode::VMULPSZ256rmbk, + 14193 => Opcode::VMULPSZ256rmbkz, + 14194 => Opcode::VMULPSZ256rmk, + 14195 => Opcode::VMULPSZ256rmkz, + 14196 => Opcode::VMULPSZ256rr, + 14197 => Opcode::VMULPSZ256rrk, + 14198 => Opcode::VMULPSZ256rrkz, + 14199 => Opcode::VMULPSZrm, + 14200 => Opcode::VMULPSZrmb, + 14201 => Opcode::VMULPSZrmbk, + 14202 => Opcode::VMULPSZrmbkz, + 14203 => Opcode::VMULPSZrmk, + 14204 => Opcode::VMULPSZrmkz, + 14205 => Opcode::VMULPSZrr, + 14206 => Opcode::VMULPSZrrb, + 14207 => Opcode::VMULPSZrrbk, + 14208 => Opcode::VMULPSZrrbkz, + 14209 => Opcode::VMULPSZrrk, + 14210 => Opcode::VMULPSZrrkz, + 14211 => Opcode::VMULPSrm, + 14212 => Opcode::VMULPSrr, + 14213 => Opcode::VMULSDZrm, + 14214 => Opcode::VMULSDZrm_Int, + 14215 => Opcode::VMULSDZrmk_Int, + 14216 => Opcode::VMULSDZrmkz_Int, + 14217 => Opcode::VMULSDZrr, + 14218 => Opcode::VMULSDZrr_Int, + 14219 => Opcode::VMULSDZrrb_Int, + 14220 => Opcode::VMULSDZrrbk_Int, + 14221 => Opcode::VMULSDZrrbkz_Int, + 14222 => Opcode::VMULSDZrrk_Int, + 14223 => Opcode::VMULSDZrrkz_Int, + 14224 => Opcode::VMULSDrm, + 14225 => Opcode::VMULSDrm_Int, + 14226 => Opcode::VMULSDrr, + 14227 => Opcode::VMULSDrr_Int, + 14228 => Opcode::VMULSHZrm, + 14229 => Opcode::VMULSHZrm_Int, + 14230 => Opcode::VMULSHZrmk_Int, + 14231 => Opcode::VMULSHZrmkz_Int, + 14232 => Opcode::VMULSHZrr, + 14233 => Opcode::VMULSHZrr_Int, + 14234 => Opcode::VMULSHZrrb_Int, + 14235 => Opcode::VMULSHZrrbk_Int, + 14236 => Opcode::VMULSHZrrbkz_Int, + 14237 => Opcode::VMULSHZrrk_Int, + 14238 => Opcode::VMULSHZrrkz_Int, + 14239 => Opcode::VMULSSZrm, + 14240 => Opcode::VMULSSZrm_Int, + 14241 => Opcode::VMULSSZrmk_Int, + 14242 => Opcode::VMULSSZrmkz_Int, + 14243 => Opcode::VMULSSZrr, + 14244 => Opcode::VMULSSZrr_Int, + 14245 => Opcode::VMULSSZrrb_Int, + 14246 => Opcode::VMULSSZrrbk_Int, + 14247 => Opcode::VMULSSZrrbkz_Int, + 14248 => Opcode::VMULSSZrrk_Int, + 14249 => Opcode::VMULSSZrrkz_Int, + 14250 => Opcode::VMULSSrm, + 14251 => Opcode::VMULSSrm_Int, + 14252 => Opcode::VMULSSrr, + 14253 => Opcode::VMULSSrr_Int, + 14254 => Opcode::VMWRITE32rm, + 14255 => Opcode::VMWRITE32rr, + 14256 => Opcode::VMWRITE64rm, + 14257 => Opcode::VMWRITE64rr, + 14258 => Opcode::VMXOFF, + 14259 => Opcode::VMXON, + 14260 => Opcode::VORPDYrm, + 14261 => Opcode::VORPDYrr, + 14262 => Opcode::VORPDZ128rm, + 14263 => Opcode::VORPDZ128rmb, + 14264 => Opcode::VORPDZ128rmbk, + 14265 => Opcode::VORPDZ128rmbkz, + 14266 => Opcode::VORPDZ128rmk, + 14267 => Opcode::VORPDZ128rmkz, + 14268 => Opcode::VORPDZ128rr, + 14269 => Opcode::VORPDZ128rrk, + 14270 => Opcode::VORPDZ128rrkz, + 14271 => Opcode::VORPDZ256rm, + 14272 => Opcode::VORPDZ256rmb, + 14273 => Opcode::VORPDZ256rmbk, + 14274 => Opcode::VORPDZ256rmbkz, + 14275 => Opcode::VORPDZ256rmk, + 14276 => Opcode::VORPDZ256rmkz, + 14277 => Opcode::VORPDZ256rr, + 14278 => Opcode::VORPDZ256rrk, + 14279 => Opcode::VORPDZ256rrkz, + 14280 => Opcode::VORPDZrm, + 14281 => Opcode::VORPDZrmb, + 14282 => Opcode::VORPDZrmbk, + 14283 => Opcode::VORPDZrmbkz, + 14284 => Opcode::VORPDZrmk, + 14285 => Opcode::VORPDZrmkz, + 14286 => Opcode::VORPDZrr, + 14287 => Opcode::VORPDZrrk, + 14288 => Opcode::VORPDZrrkz, + 14289 => Opcode::VORPDrm, + 14290 => Opcode::VORPDrr, + 14291 => Opcode::VORPSYrm, + 14292 => Opcode::VORPSYrr, + 14293 => Opcode::VORPSZ128rm, + 14294 => Opcode::VORPSZ128rmb, + 14295 => Opcode::VORPSZ128rmbk, + 14296 => Opcode::VORPSZ128rmbkz, + 14297 => Opcode::VORPSZ128rmk, + 14298 => Opcode::VORPSZ128rmkz, + 14299 => Opcode::VORPSZ128rr, + 14300 => Opcode::VORPSZ128rrk, + 14301 => Opcode::VORPSZ128rrkz, + 14302 => Opcode::VORPSZ256rm, + 14303 => Opcode::VORPSZ256rmb, + 14304 => Opcode::VORPSZ256rmbk, + 14305 => Opcode::VORPSZ256rmbkz, + 14306 => Opcode::VORPSZ256rmk, + 14307 => Opcode::VORPSZ256rmkz, + 14308 => Opcode::VORPSZ256rr, + 14309 => Opcode::VORPSZ256rrk, + 14310 => Opcode::VORPSZ256rrkz, + 14311 => Opcode::VORPSZrm, + 14312 => Opcode::VORPSZrmb, + 14313 => Opcode::VORPSZrmbk, + 14314 => Opcode::VORPSZrmbkz, + 14315 => Opcode::VORPSZrmk, + 14316 => Opcode::VORPSZrmkz, + 14317 => Opcode::VORPSZrr, + 14318 => Opcode::VORPSZrrk, + 14319 => Opcode::VORPSZrrkz, + 14320 => Opcode::VORPSrm, + 14321 => Opcode::VORPSrr, + 14322 => Opcode::VP2INTERSECTDZ128rm, + 14323 => Opcode::VP2INTERSECTDZ128rmb, + 14324 => Opcode::VP2INTERSECTDZ128rr, + 14325 => Opcode::VP2INTERSECTDZ256rm, + 14326 => Opcode::VP2INTERSECTDZ256rmb, + 14327 => Opcode::VP2INTERSECTDZ256rr, + 14328 => Opcode::VP2INTERSECTDZrm, + 14329 => Opcode::VP2INTERSECTDZrmb, + 14330 => Opcode::VP2INTERSECTDZrr, + 14331 => Opcode::VP2INTERSECTQZ128rm, + 14332 => Opcode::VP2INTERSECTQZ128rmb, + 14333 => Opcode::VP2INTERSECTQZ128rr, + 14334 => Opcode::VP2INTERSECTQZ256rm, + 14335 => Opcode::VP2INTERSECTQZ256rmb, + 14336 => Opcode::VP2INTERSECTQZ256rr, + 14337 => Opcode::VP2INTERSECTQZrm, + 14338 => Opcode::VP2INTERSECTQZrmb, + 14339 => Opcode::VP2INTERSECTQZrr, + 14340 => Opcode::VP4DPWSSDSrm, + 14341 => Opcode::VP4DPWSSDSrmk, + 14342 => Opcode::VP4DPWSSDSrmkz, + 14343 => Opcode::VP4DPWSSDrm, + 14344 => Opcode::VP4DPWSSDrmk, + 14345 => Opcode::VP4DPWSSDrmkz, + 14346 => Opcode::VPABSBYrm, + 14347 => Opcode::VPABSBYrr, + 14348 => Opcode::VPABSBZ128rm, + 14349 => Opcode::VPABSBZ128rmk, + 14350 => Opcode::VPABSBZ128rmkz, + 14351 => Opcode::VPABSBZ128rr, + 14352 => Opcode::VPABSBZ128rrk, + 14353 => Opcode::VPABSBZ128rrkz, + 14354 => Opcode::VPABSBZ256rm, + 14355 => Opcode::VPABSBZ256rmk, + 14356 => Opcode::VPABSBZ256rmkz, + 14357 => Opcode::VPABSBZ256rr, + 14358 => Opcode::VPABSBZ256rrk, + 14359 => Opcode::VPABSBZ256rrkz, + 14360 => Opcode::VPABSBZrm, + 14361 => Opcode::VPABSBZrmk, + 14362 => Opcode::VPABSBZrmkz, + 14363 => Opcode::VPABSBZrr, + 14364 => Opcode::VPABSBZrrk, + 14365 => Opcode::VPABSBZrrkz, + 14366 => Opcode::VPABSBrm, + 14367 => Opcode::VPABSBrr, + 14368 => Opcode::VPABSDYrm, + 14369 => Opcode::VPABSDYrr, + 14370 => Opcode::VPABSDZ128rm, + 14371 => Opcode::VPABSDZ128rmb, + 14372 => Opcode::VPABSDZ128rmbk, + 14373 => Opcode::VPABSDZ128rmbkz, + 14374 => Opcode::VPABSDZ128rmk, + 14375 => Opcode::VPABSDZ128rmkz, + 14376 => Opcode::VPABSDZ128rr, + 14377 => Opcode::VPABSDZ128rrk, + 14378 => Opcode::VPABSDZ128rrkz, + 14379 => Opcode::VPABSDZ256rm, + 14380 => Opcode::VPABSDZ256rmb, + 14381 => Opcode::VPABSDZ256rmbk, + 14382 => Opcode::VPABSDZ256rmbkz, + 14383 => Opcode::VPABSDZ256rmk, + 14384 => Opcode::VPABSDZ256rmkz, + 14385 => Opcode::VPABSDZ256rr, + 14386 => Opcode::VPABSDZ256rrk, + 14387 => Opcode::VPABSDZ256rrkz, + 14388 => Opcode::VPABSDZrm, + 14389 => Opcode::VPABSDZrmb, + 14390 => Opcode::VPABSDZrmbk, + 14391 => Opcode::VPABSDZrmbkz, + 14392 => Opcode::VPABSDZrmk, + 14393 => Opcode::VPABSDZrmkz, + 14394 => Opcode::VPABSDZrr, + 14395 => Opcode::VPABSDZrrk, + 14396 => Opcode::VPABSDZrrkz, + 14397 => Opcode::VPABSDrm, + 14398 => Opcode::VPABSDrr, + 14399 => Opcode::VPABSQZ128rm, + 14400 => Opcode::VPABSQZ128rmb, + 14401 => Opcode::VPABSQZ128rmbk, + 14402 => Opcode::VPABSQZ128rmbkz, + 14403 => Opcode::VPABSQZ128rmk, + 14404 => Opcode::VPABSQZ128rmkz, + 14405 => Opcode::VPABSQZ128rr, + 14406 => Opcode::VPABSQZ128rrk, + 14407 => Opcode::VPABSQZ128rrkz, + 14408 => Opcode::VPABSQZ256rm, + 14409 => Opcode::VPABSQZ256rmb, + 14410 => Opcode::VPABSQZ256rmbk, + 14411 => Opcode::VPABSQZ256rmbkz, + 14412 => Opcode::VPABSQZ256rmk, + 14413 => Opcode::VPABSQZ256rmkz, + 14414 => Opcode::VPABSQZ256rr, + 14415 => Opcode::VPABSQZ256rrk, + 14416 => Opcode::VPABSQZ256rrkz, + 14417 => Opcode::VPABSQZrm, + 14418 => Opcode::VPABSQZrmb, + 14419 => Opcode::VPABSQZrmbk, + 14420 => Opcode::VPABSQZrmbkz, + 14421 => Opcode::VPABSQZrmk, + 14422 => Opcode::VPABSQZrmkz, + 14423 => Opcode::VPABSQZrr, + 14424 => Opcode::VPABSQZrrk, + 14425 => Opcode::VPABSQZrrkz, + 14426 => Opcode::VPABSWYrm, + 14427 => Opcode::VPABSWYrr, + 14428 => Opcode::VPABSWZ128rm, + 14429 => Opcode::VPABSWZ128rmk, + 14430 => Opcode::VPABSWZ128rmkz, + 14431 => Opcode::VPABSWZ128rr, + 14432 => Opcode::VPABSWZ128rrk, + 14433 => Opcode::VPABSWZ128rrkz, + 14434 => Opcode::VPABSWZ256rm, + 14435 => Opcode::VPABSWZ256rmk, + 14436 => Opcode::VPABSWZ256rmkz, + 14437 => Opcode::VPABSWZ256rr, + 14438 => Opcode::VPABSWZ256rrk, + 14439 => Opcode::VPABSWZ256rrkz, + 14440 => Opcode::VPABSWZrm, + 14441 => Opcode::VPABSWZrmk, + 14442 => Opcode::VPABSWZrmkz, + 14443 => Opcode::VPABSWZrr, + 14444 => Opcode::VPABSWZrrk, + 14445 => Opcode::VPABSWZrrkz, + 14446 => Opcode::VPABSWrm, + 14447 => Opcode::VPABSWrr, + 14448 => Opcode::VPACKSSDWYrm, + 14449 => Opcode::VPACKSSDWYrr, + 14450 => Opcode::VPACKSSDWZ128rm, + 14451 => Opcode::VPACKSSDWZ128rmb, + 14452 => Opcode::VPACKSSDWZ128rmbk, + 14453 => Opcode::VPACKSSDWZ128rmbkz, + 14454 => Opcode::VPACKSSDWZ128rmk, + 14455 => Opcode::VPACKSSDWZ128rmkz, + 14456 => Opcode::VPACKSSDWZ128rr, + 14457 => Opcode::VPACKSSDWZ128rrk, + 14458 => Opcode::VPACKSSDWZ128rrkz, + 14459 => Opcode::VPACKSSDWZ256rm, + 14460 => Opcode::VPACKSSDWZ256rmb, + 14461 => Opcode::VPACKSSDWZ256rmbk, + 14462 => Opcode::VPACKSSDWZ256rmbkz, + 14463 => Opcode::VPACKSSDWZ256rmk, + 14464 => Opcode::VPACKSSDWZ256rmkz, + 14465 => Opcode::VPACKSSDWZ256rr, + 14466 => Opcode::VPACKSSDWZ256rrk, + 14467 => Opcode::VPACKSSDWZ256rrkz, + 14468 => Opcode::VPACKSSDWZrm, + 14469 => Opcode::VPACKSSDWZrmb, + 14470 => Opcode::VPACKSSDWZrmbk, + 14471 => Opcode::VPACKSSDWZrmbkz, + 14472 => Opcode::VPACKSSDWZrmk, + 14473 => Opcode::VPACKSSDWZrmkz, + 14474 => Opcode::VPACKSSDWZrr, + 14475 => Opcode::VPACKSSDWZrrk, + 14476 => Opcode::VPACKSSDWZrrkz, + 14477 => Opcode::VPACKSSDWrm, + 14478 => Opcode::VPACKSSDWrr, + 14479 => Opcode::VPACKSSWBYrm, + 14480 => Opcode::VPACKSSWBYrr, + 14481 => Opcode::VPACKSSWBZ128rm, + 14482 => Opcode::VPACKSSWBZ128rmk, + 14483 => Opcode::VPACKSSWBZ128rmkz, + 14484 => Opcode::VPACKSSWBZ128rr, + 14485 => Opcode::VPACKSSWBZ128rrk, + 14486 => Opcode::VPACKSSWBZ128rrkz, + 14487 => Opcode::VPACKSSWBZ256rm, + 14488 => Opcode::VPACKSSWBZ256rmk, + 14489 => Opcode::VPACKSSWBZ256rmkz, + 14490 => Opcode::VPACKSSWBZ256rr, + 14491 => Opcode::VPACKSSWBZ256rrk, + 14492 => Opcode::VPACKSSWBZ256rrkz, + 14493 => Opcode::VPACKSSWBZrm, + 14494 => Opcode::VPACKSSWBZrmk, + 14495 => Opcode::VPACKSSWBZrmkz, + 14496 => Opcode::VPACKSSWBZrr, + 14497 => Opcode::VPACKSSWBZrrk, + 14498 => Opcode::VPACKSSWBZrrkz, + 14499 => Opcode::VPACKSSWBrm, + 14500 => Opcode::VPACKSSWBrr, + 14501 => Opcode::VPACKUSDWYrm, + 14502 => Opcode::VPACKUSDWYrr, + 14503 => Opcode::VPACKUSDWZ128rm, + 14504 => Opcode::VPACKUSDWZ128rmb, + 14505 => Opcode::VPACKUSDWZ128rmbk, + 14506 => Opcode::VPACKUSDWZ128rmbkz, + 14507 => Opcode::VPACKUSDWZ128rmk, + 14508 => Opcode::VPACKUSDWZ128rmkz, + 14509 => Opcode::VPACKUSDWZ128rr, + 14510 => Opcode::VPACKUSDWZ128rrk, + 14511 => Opcode::VPACKUSDWZ128rrkz, + 14512 => Opcode::VPACKUSDWZ256rm, + 14513 => Opcode::VPACKUSDWZ256rmb, + 14514 => Opcode::VPACKUSDWZ256rmbk, + 14515 => Opcode::VPACKUSDWZ256rmbkz, + 14516 => Opcode::VPACKUSDWZ256rmk, + 14517 => Opcode::VPACKUSDWZ256rmkz, + 14518 => Opcode::VPACKUSDWZ256rr, + 14519 => Opcode::VPACKUSDWZ256rrk, + 14520 => Opcode::VPACKUSDWZ256rrkz, + 14521 => Opcode::VPACKUSDWZrm, + 14522 => Opcode::VPACKUSDWZrmb, + 14523 => Opcode::VPACKUSDWZrmbk, + 14524 => Opcode::VPACKUSDWZrmbkz, + 14525 => Opcode::VPACKUSDWZrmk, + 14526 => Opcode::VPACKUSDWZrmkz, + 14527 => Opcode::VPACKUSDWZrr, + 14528 => Opcode::VPACKUSDWZrrk, + 14529 => Opcode::VPACKUSDWZrrkz, + 14530 => Opcode::VPACKUSDWrm, + 14531 => Opcode::VPACKUSDWrr, + 14532 => Opcode::VPACKUSWBYrm, + 14533 => Opcode::VPACKUSWBYrr, + 14534 => Opcode::VPACKUSWBZ128rm, + 14535 => Opcode::VPACKUSWBZ128rmk, + 14536 => Opcode::VPACKUSWBZ128rmkz, + 14537 => Opcode::VPACKUSWBZ128rr, + 14538 => Opcode::VPACKUSWBZ128rrk, + 14539 => Opcode::VPACKUSWBZ128rrkz, + 14540 => Opcode::VPACKUSWBZ256rm, + 14541 => Opcode::VPACKUSWBZ256rmk, + 14542 => Opcode::VPACKUSWBZ256rmkz, + 14543 => Opcode::VPACKUSWBZ256rr, + 14544 => Opcode::VPACKUSWBZ256rrk, + 14545 => Opcode::VPACKUSWBZ256rrkz, + 14546 => Opcode::VPACKUSWBZrm, + 14547 => Opcode::VPACKUSWBZrmk, + 14548 => Opcode::VPACKUSWBZrmkz, + 14549 => Opcode::VPACKUSWBZrr, + 14550 => Opcode::VPACKUSWBZrrk, + 14551 => Opcode::VPACKUSWBZrrkz, + 14552 => Opcode::VPACKUSWBrm, + 14553 => Opcode::VPACKUSWBrr, + 14554 => Opcode::VPADDBYrm, + 14555 => Opcode::VPADDBYrr, + 14556 => Opcode::VPADDBZ128rm, + 14557 => Opcode::VPADDBZ128rmk, + 14558 => Opcode::VPADDBZ128rmkz, + 14559 => Opcode::VPADDBZ128rr, + 14560 => Opcode::VPADDBZ128rrk, + 14561 => Opcode::VPADDBZ128rrkz, + 14562 => Opcode::VPADDBZ256rm, + 14563 => Opcode::VPADDBZ256rmk, + 14564 => Opcode::VPADDBZ256rmkz, + 14565 => Opcode::VPADDBZ256rr, + 14566 => Opcode::VPADDBZ256rrk, + 14567 => Opcode::VPADDBZ256rrkz, + 14568 => Opcode::VPADDBZrm, + 14569 => Opcode::VPADDBZrmk, + 14570 => Opcode::VPADDBZrmkz, + 14571 => Opcode::VPADDBZrr, + 14572 => Opcode::VPADDBZrrk, + 14573 => Opcode::VPADDBZrrkz, + 14574 => Opcode::VPADDBrm, + 14575 => Opcode::VPADDBrr, + 14576 => Opcode::VPADDDYrm, + 14577 => Opcode::VPADDDYrr, + 14578 => Opcode::VPADDDZ128rm, + 14579 => Opcode::VPADDDZ128rmb, + 14580 => Opcode::VPADDDZ128rmbk, + 14581 => Opcode::VPADDDZ128rmbkz, + 14582 => Opcode::VPADDDZ128rmk, + 14583 => Opcode::VPADDDZ128rmkz, + 14584 => Opcode::VPADDDZ128rr, + 14585 => Opcode::VPADDDZ128rrk, + 14586 => Opcode::VPADDDZ128rrkz, + 14587 => Opcode::VPADDDZ256rm, + 14588 => Opcode::VPADDDZ256rmb, + 14589 => Opcode::VPADDDZ256rmbk, + 14590 => Opcode::VPADDDZ256rmbkz, + 14591 => Opcode::VPADDDZ256rmk, + 14592 => Opcode::VPADDDZ256rmkz, + 14593 => Opcode::VPADDDZ256rr, + 14594 => Opcode::VPADDDZ256rrk, + 14595 => Opcode::VPADDDZ256rrkz, + 14596 => Opcode::VPADDDZrm, + 14597 => Opcode::VPADDDZrmb, + 14598 => Opcode::VPADDDZrmbk, + 14599 => Opcode::VPADDDZrmbkz, + 14600 => Opcode::VPADDDZrmk, + 14601 => Opcode::VPADDDZrmkz, + 14602 => Opcode::VPADDDZrr, + 14603 => Opcode::VPADDDZrrk, + 14604 => Opcode::VPADDDZrrkz, + 14605 => Opcode::VPADDDrm, + 14606 => Opcode::VPADDDrr, + 14607 => Opcode::VPADDQYrm, + 14608 => Opcode::VPADDQYrr, + 14609 => Opcode::VPADDQZ128rm, + 14610 => Opcode::VPADDQZ128rmb, + 14611 => Opcode::VPADDQZ128rmbk, + 14612 => Opcode::VPADDQZ128rmbkz, + 14613 => Opcode::VPADDQZ128rmk, + 14614 => Opcode::VPADDQZ128rmkz, + 14615 => Opcode::VPADDQZ128rr, + 14616 => Opcode::VPADDQZ128rrk, + 14617 => Opcode::VPADDQZ128rrkz, + 14618 => Opcode::VPADDQZ256rm, + 14619 => Opcode::VPADDQZ256rmb, + 14620 => Opcode::VPADDQZ256rmbk, + 14621 => Opcode::VPADDQZ256rmbkz, + 14622 => Opcode::VPADDQZ256rmk, + 14623 => Opcode::VPADDQZ256rmkz, + 14624 => Opcode::VPADDQZ256rr, + 14625 => Opcode::VPADDQZ256rrk, + 14626 => Opcode::VPADDQZ256rrkz, + 14627 => Opcode::VPADDQZrm, + 14628 => Opcode::VPADDQZrmb, + 14629 => Opcode::VPADDQZrmbk, + 14630 => Opcode::VPADDQZrmbkz, + 14631 => Opcode::VPADDQZrmk, + 14632 => Opcode::VPADDQZrmkz, + 14633 => Opcode::VPADDQZrr, + 14634 => Opcode::VPADDQZrrk, + 14635 => Opcode::VPADDQZrrkz, + 14636 => Opcode::VPADDQrm, + 14637 => Opcode::VPADDQrr, + 14638 => Opcode::VPADDSBYrm, + 14639 => Opcode::VPADDSBYrr, + 14640 => Opcode::VPADDSBZ128rm, + 14641 => Opcode::VPADDSBZ128rmk, + 14642 => Opcode::VPADDSBZ128rmkz, + 14643 => Opcode::VPADDSBZ128rr, + 14644 => Opcode::VPADDSBZ128rrk, + 14645 => Opcode::VPADDSBZ128rrkz, + 14646 => Opcode::VPADDSBZ256rm, + 14647 => Opcode::VPADDSBZ256rmk, + 14648 => Opcode::VPADDSBZ256rmkz, + 14649 => Opcode::VPADDSBZ256rr, + 14650 => Opcode::VPADDSBZ256rrk, + 14651 => Opcode::VPADDSBZ256rrkz, + 14652 => Opcode::VPADDSBZrm, + 14653 => Opcode::VPADDSBZrmk, + 14654 => Opcode::VPADDSBZrmkz, + 14655 => Opcode::VPADDSBZrr, + 14656 => Opcode::VPADDSBZrrk, + 14657 => Opcode::VPADDSBZrrkz, + 14658 => Opcode::VPADDSBrm, + 14659 => Opcode::VPADDSBrr, + 14660 => Opcode::VPADDSWYrm, + 14661 => Opcode::VPADDSWYrr, + 14662 => Opcode::VPADDSWZ128rm, + 14663 => Opcode::VPADDSWZ128rmk, + 14664 => Opcode::VPADDSWZ128rmkz, + 14665 => Opcode::VPADDSWZ128rr, + 14666 => Opcode::VPADDSWZ128rrk, + 14667 => Opcode::VPADDSWZ128rrkz, + 14668 => Opcode::VPADDSWZ256rm, + 14669 => Opcode::VPADDSWZ256rmk, + 14670 => Opcode::VPADDSWZ256rmkz, + 14671 => Opcode::VPADDSWZ256rr, + 14672 => Opcode::VPADDSWZ256rrk, + 14673 => Opcode::VPADDSWZ256rrkz, + 14674 => Opcode::VPADDSWZrm, + 14675 => Opcode::VPADDSWZrmk, + 14676 => Opcode::VPADDSWZrmkz, + 14677 => Opcode::VPADDSWZrr, + 14678 => Opcode::VPADDSWZrrk, + 14679 => Opcode::VPADDSWZrrkz, + 14680 => Opcode::VPADDSWrm, + 14681 => Opcode::VPADDSWrr, + 14682 => Opcode::VPADDUSBYrm, + 14683 => Opcode::VPADDUSBYrr, + 14684 => Opcode::VPADDUSBZ128rm, + 14685 => Opcode::VPADDUSBZ128rmk, + 14686 => Opcode::VPADDUSBZ128rmkz, + 14687 => Opcode::VPADDUSBZ128rr, + 14688 => Opcode::VPADDUSBZ128rrk, + 14689 => Opcode::VPADDUSBZ128rrkz, + 14690 => Opcode::VPADDUSBZ256rm, + 14691 => Opcode::VPADDUSBZ256rmk, + 14692 => Opcode::VPADDUSBZ256rmkz, + 14693 => Opcode::VPADDUSBZ256rr, + 14694 => Opcode::VPADDUSBZ256rrk, + 14695 => Opcode::VPADDUSBZ256rrkz, + 14696 => Opcode::VPADDUSBZrm, + 14697 => Opcode::VPADDUSBZrmk, + 14698 => Opcode::VPADDUSBZrmkz, + 14699 => Opcode::VPADDUSBZrr, + 14700 => Opcode::VPADDUSBZrrk, + 14701 => Opcode::VPADDUSBZrrkz, + 14702 => Opcode::VPADDUSBrm, + 14703 => Opcode::VPADDUSBrr, + 14704 => Opcode::VPADDUSWYrm, + 14705 => Opcode::VPADDUSWYrr, + 14706 => Opcode::VPADDUSWZ128rm, + 14707 => Opcode::VPADDUSWZ128rmk, + 14708 => Opcode::VPADDUSWZ128rmkz, + 14709 => Opcode::VPADDUSWZ128rr, + 14710 => Opcode::VPADDUSWZ128rrk, + 14711 => Opcode::VPADDUSWZ128rrkz, + 14712 => Opcode::VPADDUSWZ256rm, + 14713 => Opcode::VPADDUSWZ256rmk, + 14714 => Opcode::VPADDUSWZ256rmkz, + 14715 => Opcode::VPADDUSWZ256rr, + 14716 => Opcode::VPADDUSWZ256rrk, + 14717 => Opcode::VPADDUSWZ256rrkz, + 14718 => Opcode::VPADDUSWZrm, + 14719 => Opcode::VPADDUSWZrmk, + 14720 => Opcode::VPADDUSWZrmkz, + 14721 => Opcode::VPADDUSWZrr, + 14722 => Opcode::VPADDUSWZrrk, + 14723 => Opcode::VPADDUSWZrrkz, + 14724 => Opcode::VPADDUSWrm, + 14725 => Opcode::VPADDUSWrr, + 14726 => Opcode::VPADDWYrm, + 14727 => Opcode::VPADDWYrr, + 14728 => Opcode::VPADDWZ128rm, + 14729 => Opcode::VPADDWZ128rmk, + 14730 => Opcode::VPADDWZ128rmkz, + 14731 => Opcode::VPADDWZ128rr, + 14732 => Opcode::VPADDWZ128rrk, + 14733 => Opcode::VPADDWZ128rrkz, + 14734 => Opcode::VPADDWZ256rm, + 14735 => Opcode::VPADDWZ256rmk, + 14736 => Opcode::VPADDWZ256rmkz, + 14737 => Opcode::VPADDWZ256rr, + 14738 => Opcode::VPADDWZ256rrk, + 14739 => Opcode::VPADDWZ256rrkz, + 14740 => Opcode::VPADDWZrm, + 14741 => Opcode::VPADDWZrmk, + 14742 => Opcode::VPADDWZrmkz, + 14743 => Opcode::VPADDWZrr, + 14744 => Opcode::VPADDWZrrk, + 14745 => Opcode::VPADDWZrrkz, + 14746 => Opcode::VPADDWrm, + 14747 => Opcode::VPADDWrr, + 14748 => Opcode::VPALIGNRYrmi, + 14749 => Opcode::VPALIGNRYrri, + 14750 => Opcode::VPALIGNRZ128rmi, + 14751 => Opcode::VPALIGNRZ128rmik, + 14752 => Opcode::VPALIGNRZ128rmikz, + 14753 => Opcode::VPALIGNRZ128rri, + 14754 => Opcode::VPALIGNRZ128rrik, + 14755 => Opcode::VPALIGNRZ128rrikz, + 14756 => Opcode::VPALIGNRZ256rmi, + 14757 => Opcode::VPALIGNRZ256rmik, + 14758 => Opcode::VPALIGNRZ256rmikz, + 14759 => Opcode::VPALIGNRZ256rri, + 14760 => Opcode::VPALIGNRZ256rrik, + 14761 => Opcode::VPALIGNRZ256rrikz, + 14762 => Opcode::VPALIGNRZrmi, + 14763 => Opcode::VPALIGNRZrmik, + 14764 => Opcode::VPALIGNRZrmikz, + 14765 => Opcode::VPALIGNRZrri, + 14766 => Opcode::VPALIGNRZrrik, + 14767 => Opcode::VPALIGNRZrrikz, + 14768 => Opcode::VPALIGNRrmi, + 14769 => Opcode::VPALIGNRrri, + 14770 => Opcode::VPANDDZ128rm, + 14771 => Opcode::VPANDDZ128rmb, + 14772 => Opcode::VPANDDZ128rmbk, + 14773 => Opcode::VPANDDZ128rmbkz, + 14774 => Opcode::VPANDDZ128rmk, + 14775 => Opcode::VPANDDZ128rmkz, + 14776 => Opcode::VPANDDZ128rr, + 14777 => Opcode::VPANDDZ128rrk, + 14778 => Opcode::VPANDDZ128rrkz, + 14779 => Opcode::VPANDDZ256rm, + 14780 => Opcode::VPANDDZ256rmb, + 14781 => Opcode::VPANDDZ256rmbk, + 14782 => Opcode::VPANDDZ256rmbkz, + 14783 => Opcode::VPANDDZ256rmk, + 14784 => Opcode::VPANDDZ256rmkz, + 14785 => Opcode::VPANDDZ256rr, + 14786 => Opcode::VPANDDZ256rrk, + 14787 => Opcode::VPANDDZ256rrkz, + 14788 => Opcode::VPANDDZrm, + 14789 => Opcode::VPANDDZrmb, + 14790 => Opcode::VPANDDZrmbk, + 14791 => Opcode::VPANDDZrmbkz, + 14792 => Opcode::VPANDDZrmk, + 14793 => Opcode::VPANDDZrmkz, + 14794 => Opcode::VPANDDZrr, + 14795 => Opcode::VPANDDZrrk, + 14796 => Opcode::VPANDDZrrkz, + 14797 => Opcode::VPANDNDZ128rm, + 14798 => Opcode::VPANDNDZ128rmb, + 14799 => Opcode::VPANDNDZ128rmbk, + 14800 => Opcode::VPANDNDZ128rmbkz, + 14801 => Opcode::VPANDNDZ128rmk, + 14802 => Opcode::VPANDNDZ128rmkz, + 14803 => Opcode::VPANDNDZ128rr, + 14804 => Opcode::VPANDNDZ128rrk, + 14805 => Opcode::VPANDNDZ128rrkz, + 14806 => Opcode::VPANDNDZ256rm, + 14807 => Opcode::VPANDNDZ256rmb, + 14808 => Opcode::VPANDNDZ256rmbk, + 14809 => Opcode::VPANDNDZ256rmbkz, + 14810 => Opcode::VPANDNDZ256rmk, + 14811 => Opcode::VPANDNDZ256rmkz, + 14812 => Opcode::VPANDNDZ256rr, + 14813 => Opcode::VPANDNDZ256rrk, + 14814 => Opcode::VPANDNDZ256rrkz, + 14815 => Opcode::VPANDNDZrm, + 14816 => Opcode::VPANDNDZrmb, + 14817 => Opcode::VPANDNDZrmbk, + 14818 => Opcode::VPANDNDZrmbkz, + 14819 => Opcode::VPANDNDZrmk, + 14820 => Opcode::VPANDNDZrmkz, + 14821 => Opcode::VPANDNDZrr, + 14822 => Opcode::VPANDNDZrrk, + 14823 => Opcode::VPANDNDZrrkz, + 14824 => Opcode::VPANDNQZ128rm, + 14825 => Opcode::VPANDNQZ128rmb, + 14826 => Opcode::VPANDNQZ128rmbk, + 14827 => Opcode::VPANDNQZ128rmbkz, + 14828 => Opcode::VPANDNQZ128rmk, + 14829 => Opcode::VPANDNQZ128rmkz, + 14830 => Opcode::VPANDNQZ128rr, + 14831 => Opcode::VPANDNQZ128rrk, + 14832 => Opcode::VPANDNQZ128rrkz, + 14833 => Opcode::VPANDNQZ256rm, + 14834 => Opcode::VPANDNQZ256rmb, + 14835 => Opcode::VPANDNQZ256rmbk, + 14836 => Opcode::VPANDNQZ256rmbkz, + 14837 => Opcode::VPANDNQZ256rmk, + 14838 => Opcode::VPANDNQZ256rmkz, + 14839 => Opcode::VPANDNQZ256rr, + 14840 => Opcode::VPANDNQZ256rrk, + 14841 => Opcode::VPANDNQZ256rrkz, + 14842 => Opcode::VPANDNQZrm, + 14843 => Opcode::VPANDNQZrmb, + 14844 => Opcode::VPANDNQZrmbk, + 14845 => Opcode::VPANDNQZrmbkz, + 14846 => Opcode::VPANDNQZrmk, + 14847 => Opcode::VPANDNQZrmkz, + 14848 => Opcode::VPANDNQZrr, + 14849 => Opcode::VPANDNQZrrk, + 14850 => Opcode::VPANDNQZrrkz, + 14851 => Opcode::VPANDNYrm, + 14852 => Opcode::VPANDNYrr, + 14853 => Opcode::VPANDNrm, + 14854 => Opcode::VPANDNrr, + 14855 => Opcode::VPANDQZ128rm, + 14856 => Opcode::VPANDQZ128rmb, + 14857 => Opcode::VPANDQZ128rmbk, + 14858 => Opcode::VPANDQZ128rmbkz, + 14859 => Opcode::VPANDQZ128rmk, + 14860 => Opcode::VPANDQZ128rmkz, + 14861 => Opcode::VPANDQZ128rr, + 14862 => Opcode::VPANDQZ128rrk, + 14863 => Opcode::VPANDQZ128rrkz, + 14864 => Opcode::VPANDQZ256rm, + 14865 => Opcode::VPANDQZ256rmb, + 14866 => Opcode::VPANDQZ256rmbk, + 14867 => Opcode::VPANDQZ256rmbkz, + 14868 => Opcode::VPANDQZ256rmk, + 14869 => Opcode::VPANDQZ256rmkz, + 14870 => Opcode::VPANDQZ256rr, + 14871 => Opcode::VPANDQZ256rrk, + 14872 => Opcode::VPANDQZ256rrkz, + 14873 => Opcode::VPANDQZrm, + 14874 => Opcode::VPANDQZrmb, + 14875 => Opcode::VPANDQZrmbk, + 14876 => Opcode::VPANDQZrmbkz, + 14877 => Opcode::VPANDQZrmk, + 14878 => Opcode::VPANDQZrmkz, + 14879 => Opcode::VPANDQZrr, + 14880 => Opcode::VPANDQZrrk, + 14881 => Opcode::VPANDQZrrkz, + 14882 => Opcode::VPANDYrm, + 14883 => Opcode::VPANDYrr, + 14884 => Opcode::VPANDrm, + 14885 => Opcode::VPANDrr, + 14886 => Opcode::VPAVGBYrm, + 14887 => Opcode::VPAVGBYrr, + 14888 => Opcode::VPAVGBZ128rm, + 14889 => Opcode::VPAVGBZ128rmk, + 14890 => Opcode::VPAVGBZ128rmkz, + 14891 => Opcode::VPAVGBZ128rr, + 14892 => Opcode::VPAVGBZ128rrk, + 14893 => Opcode::VPAVGBZ128rrkz, + 14894 => Opcode::VPAVGBZ256rm, + 14895 => Opcode::VPAVGBZ256rmk, + 14896 => Opcode::VPAVGBZ256rmkz, + 14897 => Opcode::VPAVGBZ256rr, + 14898 => Opcode::VPAVGBZ256rrk, + 14899 => Opcode::VPAVGBZ256rrkz, + 14900 => Opcode::VPAVGBZrm, + 14901 => Opcode::VPAVGBZrmk, + 14902 => Opcode::VPAVGBZrmkz, + 14903 => Opcode::VPAVGBZrr, + 14904 => Opcode::VPAVGBZrrk, + 14905 => Opcode::VPAVGBZrrkz, + 14906 => Opcode::VPAVGBrm, + 14907 => Opcode::VPAVGBrr, + 14908 => Opcode::VPAVGWYrm, + 14909 => Opcode::VPAVGWYrr, + 14910 => Opcode::VPAVGWZ128rm, + 14911 => Opcode::VPAVGWZ128rmk, + 14912 => Opcode::VPAVGWZ128rmkz, + 14913 => Opcode::VPAVGWZ128rr, + 14914 => Opcode::VPAVGWZ128rrk, + 14915 => Opcode::VPAVGWZ128rrkz, + 14916 => Opcode::VPAVGWZ256rm, + 14917 => Opcode::VPAVGWZ256rmk, + 14918 => Opcode::VPAVGWZ256rmkz, + 14919 => Opcode::VPAVGWZ256rr, + 14920 => Opcode::VPAVGWZ256rrk, + 14921 => Opcode::VPAVGWZ256rrkz, + 14922 => Opcode::VPAVGWZrm, + 14923 => Opcode::VPAVGWZrmk, + 14924 => Opcode::VPAVGWZrmkz, + 14925 => Opcode::VPAVGWZrr, + 14926 => Opcode::VPAVGWZrrk, + 14927 => Opcode::VPAVGWZrrkz, + 14928 => Opcode::VPAVGWrm, + 14929 => Opcode::VPAVGWrr, + 14930 => Opcode::VPBLENDDYrmi, + 14931 => Opcode::VPBLENDDYrri, + 14932 => Opcode::VPBLENDDrmi, + 14933 => Opcode::VPBLENDDrri, + 14934 => Opcode::VPBLENDMBZ128rm, + 14935 => Opcode::VPBLENDMBZ128rmk, + 14936 => Opcode::VPBLENDMBZ128rmkz, + 14937 => Opcode::VPBLENDMBZ128rr, + 14938 => Opcode::VPBLENDMBZ128rrk, + 14939 => Opcode::VPBLENDMBZ128rrkz, + 14940 => Opcode::VPBLENDMBZ256rm, + 14941 => Opcode::VPBLENDMBZ256rmk, + 14942 => Opcode::VPBLENDMBZ256rmkz, + 14943 => Opcode::VPBLENDMBZ256rr, + 14944 => Opcode::VPBLENDMBZ256rrk, + 14945 => Opcode::VPBLENDMBZ256rrkz, + 14946 => Opcode::VPBLENDMBZrm, + 14947 => Opcode::VPBLENDMBZrmk, + 14948 => Opcode::VPBLENDMBZrmkz, + 14949 => Opcode::VPBLENDMBZrr, + 14950 => Opcode::VPBLENDMBZrrk, + 14951 => Opcode::VPBLENDMBZrrkz, + 14952 => Opcode::VPBLENDMDZ128rm, + 14953 => Opcode::VPBLENDMDZ128rmb, + 14954 => Opcode::VPBLENDMDZ128rmbk, + 14955 => Opcode::VPBLENDMDZ128rmbkz, + 14956 => Opcode::VPBLENDMDZ128rmk, + 14957 => Opcode::VPBLENDMDZ128rmkz, + 14958 => Opcode::VPBLENDMDZ128rr, + 14959 => Opcode::VPBLENDMDZ128rrk, + 14960 => Opcode::VPBLENDMDZ128rrkz, + 14961 => Opcode::VPBLENDMDZ256rm, + 14962 => Opcode::VPBLENDMDZ256rmb, + 14963 => Opcode::VPBLENDMDZ256rmbk, + 14964 => Opcode::VPBLENDMDZ256rmbkz, + 14965 => Opcode::VPBLENDMDZ256rmk, + 14966 => Opcode::VPBLENDMDZ256rmkz, + 14967 => Opcode::VPBLENDMDZ256rr, + 14968 => Opcode::VPBLENDMDZ256rrk, + 14969 => Opcode::VPBLENDMDZ256rrkz, + 14970 => Opcode::VPBLENDMDZrm, + 14971 => Opcode::VPBLENDMDZrmb, + 14972 => Opcode::VPBLENDMDZrmbk, + 14973 => Opcode::VPBLENDMDZrmbkz, + 14974 => Opcode::VPBLENDMDZrmk, + 14975 => Opcode::VPBLENDMDZrmkz, + 14976 => Opcode::VPBLENDMDZrr, + 14977 => Opcode::VPBLENDMDZrrk, + 14978 => Opcode::VPBLENDMDZrrkz, + 14979 => Opcode::VPBLENDMQZ128rm, + 14980 => Opcode::VPBLENDMQZ128rmb, + 14981 => Opcode::VPBLENDMQZ128rmbk, + 14982 => Opcode::VPBLENDMQZ128rmbkz, + 14983 => Opcode::VPBLENDMQZ128rmk, + 14984 => Opcode::VPBLENDMQZ128rmkz, + 14985 => Opcode::VPBLENDMQZ128rr, + 14986 => Opcode::VPBLENDMQZ128rrk, + 14987 => Opcode::VPBLENDMQZ128rrkz, + 14988 => Opcode::VPBLENDMQZ256rm, + 14989 => Opcode::VPBLENDMQZ256rmb, + 14990 => Opcode::VPBLENDMQZ256rmbk, + 14991 => Opcode::VPBLENDMQZ256rmbkz, + 14992 => Opcode::VPBLENDMQZ256rmk, + 14993 => Opcode::VPBLENDMQZ256rmkz, + 14994 => Opcode::VPBLENDMQZ256rr, + 14995 => Opcode::VPBLENDMQZ256rrk, + 14996 => Opcode::VPBLENDMQZ256rrkz, + 14997 => Opcode::VPBLENDMQZrm, + 14998 => Opcode::VPBLENDMQZrmb, + 14999 => Opcode::VPBLENDMQZrmbk, + 15000 => Opcode::VPBLENDMQZrmbkz, + 15001 => Opcode::VPBLENDMQZrmk, + 15002 => Opcode::VPBLENDMQZrmkz, + 15003 => Opcode::VPBLENDMQZrr, + 15004 => Opcode::VPBLENDMQZrrk, + 15005 => Opcode::VPBLENDMQZrrkz, + 15006 => Opcode::VPBLENDMWZ128rm, + 15007 => Opcode::VPBLENDMWZ128rmk, + 15008 => Opcode::VPBLENDMWZ128rmkz, + 15009 => Opcode::VPBLENDMWZ128rr, + 15010 => Opcode::VPBLENDMWZ128rrk, + 15011 => Opcode::VPBLENDMWZ128rrkz, + 15012 => Opcode::VPBLENDMWZ256rm, + 15013 => Opcode::VPBLENDMWZ256rmk, + 15014 => Opcode::VPBLENDMWZ256rmkz, + 15015 => Opcode::VPBLENDMWZ256rr, + 15016 => Opcode::VPBLENDMWZ256rrk, + 15017 => Opcode::VPBLENDMWZ256rrkz, + 15018 => Opcode::VPBLENDMWZrm, + 15019 => Opcode::VPBLENDMWZrmk, + 15020 => Opcode::VPBLENDMWZrmkz, + 15021 => Opcode::VPBLENDMWZrr, + 15022 => Opcode::VPBLENDMWZrrk, + 15023 => Opcode::VPBLENDMWZrrkz, + 15024 => Opcode::VPBLENDVBYrmr, + 15025 => Opcode::VPBLENDVBYrrr, + 15026 => Opcode::VPBLENDVBrmr, + 15027 => Opcode::VPBLENDVBrrr, + 15028 => Opcode::VPBLENDWYrmi, + 15029 => Opcode::VPBLENDWYrri, + 15030 => Opcode::VPBLENDWrmi, + 15031 => Opcode::VPBLENDWrri, + 15032 => Opcode::VPBROADCASTBYrm, + 15033 => Opcode::VPBROADCASTBYrr, + 15034 => Opcode::VPBROADCASTBZ128rm, + 15035 => Opcode::VPBROADCASTBZ128rmk, + 15036 => Opcode::VPBROADCASTBZ128rmkz, + 15037 => Opcode::VPBROADCASTBZ128rr, + 15038 => Opcode::VPBROADCASTBZ128rrk, + 15039 => Opcode::VPBROADCASTBZ128rrkz, + 15040 => Opcode::VPBROADCASTBZ256rm, + 15041 => Opcode::VPBROADCASTBZ256rmk, + 15042 => Opcode::VPBROADCASTBZ256rmkz, + 15043 => Opcode::VPBROADCASTBZ256rr, + 15044 => Opcode::VPBROADCASTBZ256rrk, + 15045 => Opcode::VPBROADCASTBZ256rrkz, + 15046 => Opcode::VPBROADCASTBZrm, + 15047 => Opcode::VPBROADCASTBZrmk, + 15048 => Opcode::VPBROADCASTBZrmkz, + 15049 => Opcode::VPBROADCASTBZrr, + 15050 => Opcode::VPBROADCASTBZrrk, + 15051 => Opcode::VPBROADCASTBZrrkz, + 15052 => Opcode::VPBROADCASTBrZ128rr, + 15053 => Opcode::VPBROADCASTBrZ128rrk, + 15054 => Opcode::VPBROADCASTBrZ128rrkz, + 15055 => Opcode::VPBROADCASTBrZ256rr, + 15056 => Opcode::VPBROADCASTBrZ256rrk, + 15057 => Opcode::VPBROADCASTBrZ256rrkz, + 15058 => Opcode::VPBROADCASTBrZrr, + 15059 => Opcode::VPBROADCASTBrZrrk, + 15060 => Opcode::VPBROADCASTBrZrrkz, + 15061 => Opcode::VPBROADCASTBrm, + 15062 => Opcode::VPBROADCASTBrr, + 15063 => Opcode::VPBROADCASTDYrm, + 15064 => Opcode::VPBROADCASTDYrr, + 15065 => Opcode::VPBROADCASTDZ128rm, + 15066 => Opcode::VPBROADCASTDZ128rmk, + 15067 => Opcode::VPBROADCASTDZ128rmkz, + 15068 => Opcode::VPBROADCASTDZ128rr, + 15069 => Opcode::VPBROADCASTDZ128rrk, + 15070 => Opcode::VPBROADCASTDZ128rrkz, + 15071 => Opcode::VPBROADCASTDZ256rm, + 15072 => Opcode::VPBROADCASTDZ256rmk, + 15073 => Opcode::VPBROADCASTDZ256rmkz, + 15074 => Opcode::VPBROADCASTDZ256rr, + 15075 => Opcode::VPBROADCASTDZ256rrk, + 15076 => Opcode::VPBROADCASTDZ256rrkz, + 15077 => Opcode::VPBROADCASTDZrm, + 15078 => Opcode::VPBROADCASTDZrmk, + 15079 => Opcode::VPBROADCASTDZrmkz, + 15080 => Opcode::VPBROADCASTDZrr, + 15081 => Opcode::VPBROADCASTDZrrk, + 15082 => Opcode::VPBROADCASTDZrrkz, + 15083 => Opcode::VPBROADCASTDrZ128rr, + 15084 => Opcode::VPBROADCASTDrZ128rrk, + 15085 => Opcode::VPBROADCASTDrZ128rrkz, + 15086 => Opcode::VPBROADCASTDrZ256rr, + 15087 => Opcode::VPBROADCASTDrZ256rrk, + 15088 => Opcode::VPBROADCASTDrZ256rrkz, + 15089 => Opcode::VPBROADCASTDrZrr, + 15090 => Opcode::VPBROADCASTDrZrrk, + 15091 => Opcode::VPBROADCASTDrZrrkz, + 15092 => Opcode::VPBROADCASTDrm, + 15093 => Opcode::VPBROADCASTDrr, + 15094 => Opcode::VPBROADCASTMB2QZ128rr, + 15095 => Opcode::VPBROADCASTMB2QZ256rr, + 15096 => Opcode::VPBROADCASTMB2QZrr, + 15097 => Opcode::VPBROADCASTMW2DZ128rr, + 15098 => Opcode::VPBROADCASTMW2DZ256rr, + 15099 => Opcode::VPBROADCASTMW2DZrr, + 15100 => Opcode::VPBROADCASTQYrm, + 15101 => Opcode::VPBROADCASTQYrr, + 15102 => Opcode::VPBROADCASTQZ128rm, + 15103 => Opcode::VPBROADCASTQZ128rmk, + 15104 => Opcode::VPBROADCASTQZ128rmkz, + 15105 => Opcode::VPBROADCASTQZ128rr, + 15106 => Opcode::VPBROADCASTQZ128rrk, + 15107 => Opcode::VPBROADCASTQZ128rrkz, + 15108 => Opcode::VPBROADCASTQZ256rm, + 15109 => Opcode::VPBROADCASTQZ256rmk, + 15110 => Opcode::VPBROADCASTQZ256rmkz, + 15111 => Opcode::VPBROADCASTQZ256rr, + 15112 => Opcode::VPBROADCASTQZ256rrk, + 15113 => Opcode::VPBROADCASTQZ256rrkz, + 15114 => Opcode::VPBROADCASTQZrm, + 15115 => Opcode::VPBROADCASTQZrmk, + 15116 => Opcode::VPBROADCASTQZrmkz, + 15117 => Opcode::VPBROADCASTQZrr, + 15118 => Opcode::VPBROADCASTQZrrk, + 15119 => Opcode::VPBROADCASTQZrrkz, + 15120 => Opcode::VPBROADCASTQrZ128rr, + 15121 => Opcode::VPBROADCASTQrZ128rrk, + 15122 => Opcode::VPBROADCASTQrZ128rrkz, + 15123 => Opcode::VPBROADCASTQrZ256rr, + 15124 => Opcode::VPBROADCASTQrZ256rrk, + 15125 => Opcode::VPBROADCASTQrZ256rrkz, + 15126 => Opcode::VPBROADCASTQrZrr, + 15127 => Opcode::VPBROADCASTQrZrrk, + 15128 => Opcode::VPBROADCASTQrZrrkz, + 15129 => Opcode::VPBROADCASTQrm, + 15130 => Opcode::VPBROADCASTQrr, + 15131 => Opcode::VPBROADCASTWYrm, + 15132 => Opcode::VPBROADCASTWYrr, + 15133 => Opcode::VPBROADCASTWZ128rm, + 15134 => Opcode::VPBROADCASTWZ128rmk, + 15135 => Opcode::VPBROADCASTWZ128rmkz, + 15136 => Opcode::VPBROADCASTWZ128rr, + 15137 => Opcode::VPBROADCASTWZ128rrk, + 15138 => Opcode::VPBROADCASTWZ128rrkz, + 15139 => Opcode::VPBROADCASTWZ256rm, + 15140 => Opcode::VPBROADCASTWZ256rmk, + 15141 => Opcode::VPBROADCASTWZ256rmkz, + 15142 => Opcode::VPBROADCASTWZ256rr, + 15143 => Opcode::VPBROADCASTWZ256rrk, + 15144 => Opcode::VPBROADCASTWZ256rrkz, + 15145 => Opcode::VPBROADCASTWZrm, + 15146 => Opcode::VPBROADCASTWZrmk, + 15147 => Opcode::VPBROADCASTWZrmkz, + 15148 => Opcode::VPBROADCASTWZrr, + 15149 => Opcode::VPBROADCASTWZrrk, + 15150 => Opcode::VPBROADCASTWZrrkz, + 15151 => Opcode::VPBROADCASTWrZ128rr, + 15152 => Opcode::VPBROADCASTWrZ128rrk, + 15153 => Opcode::VPBROADCASTWrZ128rrkz, + 15154 => Opcode::VPBROADCASTWrZ256rr, + 15155 => Opcode::VPBROADCASTWrZ256rrk, + 15156 => Opcode::VPBROADCASTWrZ256rrkz, + 15157 => Opcode::VPBROADCASTWrZrr, + 15158 => Opcode::VPBROADCASTWrZrrk, + 15159 => Opcode::VPBROADCASTWrZrrkz, + 15160 => Opcode::VPBROADCASTWrm, + 15161 => Opcode::VPBROADCASTWrr, + 15162 => Opcode::VPCLMULQDQYrmi, + 15163 => Opcode::VPCLMULQDQYrri, + 15164 => Opcode::VPCLMULQDQZ128rmi, + 15165 => Opcode::VPCLMULQDQZ128rri, + 15166 => Opcode::VPCLMULQDQZ256rmi, + 15167 => Opcode::VPCLMULQDQZ256rri, + 15168 => Opcode::VPCLMULQDQZrmi, + 15169 => Opcode::VPCLMULQDQZrri, + 15170 => Opcode::VPCLMULQDQrmi, + 15171 => Opcode::VPCLMULQDQrri, + 15172 => Opcode::VPCMOVYrmr, + 15173 => Opcode::VPCMOVYrrm, + 15174 => Opcode::VPCMOVYrrr, + 15175 => Opcode::VPCMOVYrrr_REV, + 15176 => Opcode::VPCMOVrmr, + 15177 => Opcode::VPCMOVrrm, + 15178 => Opcode::VPCMOVrrr, + 15179 => Opcode::VPCMOVrrr_REV, + 15180 => Opcode::VPCMPBZ128rmi, + 15181 => Opcode::VPCMPBZ128rmik, + 15182 => Opcode::VPCMPBZ128rri, + 15183 => Opcode::VPCMPBZ128rrik, + 15184 => Opcode::VPCMPBZ256rmi, + 15185 => Opcode::VPCMPBZ256rmik, + 15186 => Opcode::VPCMPBZ256rri, + 15187 => Opcode::VPCMPBZ256rrik, + 15188 => Opcode::VPCMPBZrmi, + 15189 => Opcode::VPCMPBZrmik, + 15190 => Opcode::VPCMPBZrri, + 15191 => Opcode::VPCMPBZrrik, + 15192 => Opcode::VPCMPDZ128rmbi, + 15193 => Opcode::VPCMPDZ128rmbik, + 15194 => Opcode::VPCMPDZ128rmi, + 15195 => Opcode::VPCMPDZ128rmik, + 15196 => Opcode::VPCMPDZ128rri, + 15197 => Opcode::VPCMPDZ128rrik, + 15198 => Opcode::VPCMPDZ256rmbi, + 15199 => Opcode::VPCMPDZ256rmbik, + 15200 => Opcode::VPCMPDZ256rmi, + 15201 => Opcode::VPCMPDZ256rmik, + 15202 => Opcode::VPCMPDZ256rri, + 15203 => Opcode::VPCMPDZ256rrik, + 15204 => Opcode::VPCMPDZrmbi, + 15205 => Opcode::VPCMPDZrmbik, + 15206 => Opcode::VPCMPDZrmi, + 15207 => Opcode::VPCMPDZrmik, + 15208 => Opcode::VPCMPDZrri, + 15209 => Opcode::VPCMPDZrrik, + 15210 => Opcode::VPCMPEQBYrm, + 15211 => Opcode::VPCMPEQBYrr, + 15212 => Opcode::VPCMPEQBZ128rm, + 15213 => Opcode::VPCMPEQBZ128rmk, + 15214 => Opcode::VPCMPEQBZ128rr, + 15215 => Opcode::VPCMPEQBZ128rrk, + 15216 => Opcode::VPCMPEQBZ256rm, + 15217 => Opcode::VPCMPEQBZ256rmk, + 15218 => Opcode::VPCMPEQBZ256rr, + 15219 => Opcode::VPCMPEQBZ256rrk, + 15220 => Opcode::VPCMPEQBZrm, + 15221 => Opcode::VPCMPEQBZrmk, + 15222 => Opcode::VPCMPEQBZrr, + 15223 => Opcode::VPCMPEQBZrrk, + 15224 => Opcode::VPCMPEQBrm, + 15225 => Opcode::VPCMPEQBrr, + 15226 => Opcode::VPCMPEQDYrm, + 15227 => Opcode::VPCMPEQDYrr, + 15228 => Opcode::VPCMPEQDZ128rm, + 15229 => Opcode::VPCMPEQDZ128rmb, + 15230 => Opcode::VPCMPEQDZ128rmbk, + 15231 => Opcode::VPCMPEQDZ128rmk, + 15232 => Opcode::VPCMPEQDZ128rr, + 15233 => Opcode::VPCMPEQDZ128rrk, + 15234 => Opcode::VPCMPEQDZ256rm, + 15235 => Opcode::VPCMPEQDZ256rmb, + 15236 => Opcode::VPCMPEQDZ256rmbk, + 15237 => Opcode::VPCMPEQDZ256rmk, + 15238 => Opcode::VPCMPEQDZ256rr, + 15239 => Opcode::VPCMPEQDZ256rrk, + 15240 => Opcode::VPCMPEQDZrm, + 15241 => Opcode::VPCMPEQDZrmb, + 15242 => Opcode::VPCMPEQDZrmbk, + 15243 => Opcode::VPCMPEQDZrmk, + 15244 => Opcode::VPCMPEQDZrr, + 15245 => Opcode::VPCMPEQDZrrk, + 15246 => Opcode::VPCMPEQDrm, + 15247 => Opcode::VPCMPEQDrr, + 15248 => Opcode::VPCMPEQQYrm, + 15249 => Opcode::VPCMPEQQYrr, + 15250 => Opcode::VPCMPEQQZ128rm, + 15251 => Opcode::VPCMPEQQZ128rmb, + 15252 => Opcode::VPCMPEQQZ128rmbk, + 15253 => Opcode::VPCMPEQQZ128rmk, + 15254 => Opcode::VPCMPEQQZ128rr, + 15255 => Opcode::VPCMPEQQZ128rrk, + 15256 => Opcode::VPCMPEQQZ256rm, + 15257 => Opcode::VPCMPEQQZ256rmb, + 15258 => Opcode::VPCMPEQQZ256rmbk, + 15259 => Opcode::VPCMPEQQZ256rmk, + 15260 => Opcode::VPCMPEQQZ256rr, + 15261 => Opcode::VPCMPEQQZ256rrk, + 15262 => Opcode::VPCMPEQQZrm, + 15263 => Opcode::VPCMPEQQZrmb, + 15264 => Opcode::VPCMPEQQZrmbk, + 15265 => Opcode::VPCMPEQQZrmk, + 15266 => Opcode::VPCMPEQQZrr, + 15267 => Opcode::VPCMPEQQZrrk, + 15268 => Opcode::VPCMPEQQrm, + 15269 => Opcode::VPCMPEQQrr, + 15270 => Opcode::VPCMPEQWYrm, + 15271 => Opcode::VPCMPEQWYrr, + 15272 => Opcode::VPCMPEQWZ128rm, + 15273 => Opcode::VPCMPEQWZ128rmk, + 15274 => Opcode::VPCMPEQWZ128rr, + 15275 => Opcode::VPCMPEQWZ128rrk, + 15276 => Opcode::VPCMPEQWZ256rm, + 15277 => Opcode::VPCMPEQWZ256rmk, + 15278 => Opcode::VPCMPEQWZ256rr, + 15279 => Opcode::VPCMPEQWZ256rrk, + 15280 => Opcode::VPCMPEQWZrm, + 15281 => Opcode::VPCMPEQWZrmk, + 15282 => Opcode::VPCMPEQWZrr, + 15283 => Opcode::VPCMPEQWZrrk, + 15284 => Opcode::VPCMPEQWrm, + 15285 => Opcode::VPCMPEQWrr, + 15286 => Opcode::VPCMPESTRIrmi, + 15287 => Opcode::VPCMPESTRIrri, + 15288 => Opcode::VPCMPESTRMrmi, + 15289 => Opcode::VPCMPESTRMrri, + 15290 => Opcode::VPCMPGTBYrm, + 15291 => Opcode::VPCMPGTBYrr, + 15292 => Opcode::VPCMPGTBZ128rm, + 15293 => Opcode::VPCMPGTBZ128rmk, + 15294 => Opcode::VPCMPGTBZ128rr, + 15295 => Opcode::VPCMPGTBZ128rrk, + 15296 => Opcode::VPCMPGTBZ256rm, + 15297 => Opcode::VPCMPGTBZ256rmk, + 15298 => Opcode::VPCMPGTBZ256rr, + 15299 => Opcode::VPCMPGTBZ256rrk, + 15300 => Opcode::VPCMPGTBZrm, + 15301 => Opcode::VPCMPGTBZrmk, + 15302 => Opcode::VPCMPGTBZrr, + 15303 => Opcode::VPCMPGTBZrrk, + 15304 => Opcode::VPCMPGTBrm, + 15305 => Opcode::VPCMPGTBrr, + 15306 => Opcode::VPCMPGTDYrm, + 15307 => Opcode::VPCMPGTDYrr, + 15308 => Opcode::VPCMPGTDZ128rm, + 15309 => Opcode::VPCMPGTDZ128rmb, + 15310 => Opcode::VPCMPGTDZ128rmbk, + 15311 => Opcode::VPCMPGTDZ128rmk, + 15312 => Opcode::VPCMPGTDZ128rr, + 15313 => Opcode::VPCMPGTDZ128rrk, + 15314 => Opcode::VPCMPGTDZ256rm, + 15315 => Opcode::VPCMPGTDZ256rmb, + 15316 => Opcode::VPCMPGTDZ256rmbk, + 15317 => Opcode::VPCMPGTDZ256rmk, + 15318 => Opcode::VPCMPGTDZ256rr, + 15319 => Opcode::VPCMPGTDZ256rrk, + 15320 => Opcode::VPCMPGTDZrm, + 15321 => Opcode::VPCMPGTDZrmb, + 15322 => Opcode::VPCMPGTDZrmbk, + 15323 => Opcode::VPCMPGTDZrmk, + 15324 => Opcode::VPCMPGTDZrr, + 15325 => Opcode::VPCMPGTDZrrk, + 15326 => Opcode::VPCMPGTDrm, + 15327 => Opcode::VPCMPGTDrr, + 15328 => Opcode::VPCMPGTQYrm, + 15329 => Opcode::VPCMPGTQYrr, + 15330 => Opcode::VPCMPGTQZ128rm, + 15331 => Opcode::VPCMPGTQZ128rmb, + 15332 => Opcode::VPCMPGTQZ128rmbk, + 15333 => Opcode::VPCMPGTQZ128rmk, + 15334 => Opcode::VPCMPGTQZ128rr, + 15335 => Opcode::VPCMPGTQZ128rrk, + 15336 => Opcode::VPCMPGTQZ256rm, + 15337 => Opcode::VPCMPGTQZ256rmb, + 15338 => Opcode::VPCMPGTQZ256rmbk, + 15339 => Opcode::VPCMPGTQZ256rmk, + 15340 => Opcode::VPCMPGTQZ256rr, + 15341 => Opcode::VPCMPGTQZ256rrk, + 15342 => Opcode::VPCMPGTQZrm, + 15343 => Opcode::VPCMPGTQZrmb, + 15344 => Opcode::VPCMPGTQZrmbk, + 15345 => Opcode::VPCMPGTQZrmk, + 15346 => Opcode::VPCMPGTQZrr, + 15347 => Opcode::VPCMPGTQZrrk, + 15348 => Opcode::VPCMPGTQrm, + 15349 => Opcode::VPCMPGTQrr, + 15350 => Opcode::VPCMPGTWYrm, + 15351 => Opcode::VPCMPGTWYrr, + 15352 => Opcode::VPCMPGTWZ128rm, + 15353 => Opcode::VPCMPGTWZ128rmk, + 15354 => Opcode::VPCMPGTWZ128rr, + 15355 => Opcode::VPCMPGTWZ128rrk, + 15356 => Opcode::VPCMPGTWZ256rm, + 15357 => Opcode::VPCMPGTWZ256rmk, + 15358 => Opcode::VPCMPGTWZ256rr, + 15359 => Opcode::VPCMPGTWZ256rrk, + 15360 => Opcode::VPCMPGTWZrm, + 15361 => Opcode::VPCMPGTWZrmk, + 15362 => Opcode::VPCMPGTWZrr, + 15363 => Opcode::VPCMPGTWZrrk, + 15364 => Opcode::VPCMPGTWrm, + 15365 => Opcode::VPCMPGTWrr, + 15366 => Opcode::VPCMPISTRIrmi, + 15367 => Opcode::VPCMPISTRIrri, + 15368 => Opcode::VPCMPISTRMrmi, + 15369 => Opcode::VPCMPISTRMrri, + 15370 => Opcode::VPCMPQZ128rmbi, + 15371 => Opcode::VPCMPQZ128rmbik, + 15372 => Opcode::VPCMPQZ128rmi, + 15373 => Opcode::VPCMPQZ128rmik, + 15374 => Opcode::VPCMPQZ128rri, + 15375 => Opcode::VPCMPQZ128rrik, + 15376 => Opcode::VPCMPQZ256rmbi, + 15377 => Opcode::VPCMPQZ256rmbik, + 15378 => Opcode::VPCMPQZ256rmi, + 15379 => Opcode::VPCMPQZ256rmik, + 15380 => Opcode::VPCMPQZ256rri, + 15381 => Opcode::VPCMPQZ256rrik, + 15382 => Opcode::VPCMPQZrmbi, + 15383 => Opcode::VPCMPQZrmbik, + 15384 => Opcode::VPCMPQZrmi, + 15385 => Opcode::VPCMPQZrmik, + 15386 => Opcode::VPCMPQZrri, + 15387 => Opcode::VPCMPQZrrik, + 15388 => Opcode::VPCMPUBZ128rmi, + 15389 => Opcode::VPCMPUBZ128rmik, + 15390 => Opcode::VPCMPUBZ128rri, + 15391 => Opcode::VPCMPUBZ128rrik, + 15392 => Opcode::VPCMPUBZ256rmi, + 15393 => Opcode::VPCMPUBZ256rmik, + 15394 => Opcode::VPCMPUBZ256rri, + 15395 => Opcode::VPCMPUBZ256rrik, + 15396 => Opcode::VPCMPUBZrmi, + 15397 => Opcode::VPCMPUBZrmik, + 15398 => Opcode::VPCMPUBZrri, + 15399 => Opcode::VPCMPUBZrrik, + 15400 => Opcode::VPCMPUDZ128rmbi, + 15401 => Opcode::VPCMPUDZ128rmbik, + 15402 => Opcode::VPCMPUDZ128rmi, + 15403 => Opcode::VPCMPUDZ128rmik, + 15404 => Opcode::VPCMPUDZ128rri, + 15405 => Opcode::VPCMPUDZ128rrik, + 15406 => Opcode::VPCMPUDZ256rmbi, + 15407 => Opcode::VPCMPUDZ256rmbik, + 15408 => Opcode::VPCMPUDZ256rmi, + 15409 => Opcode::VPCMPUDZ256rmik, + 15410 => Opcode::VPCMPUDZ256rri, + 15411 => Opcode::VPCMPUDZ256rrik, + 15412 => Opcode::VPCMPUDZrmbi, + 15413 => Opcode::VPCMPUDZrmbik, + 15414 => Opcode::VPCMPUDZrmi, + 15415 => Opcode::VPCMPUDZrmik, + 15416 => Opcode::VPCMPUDZrri, + 15417 => Opcode::VPCMPUDZrrik, + 15418 => Opcode::VPCMPUQZ128rmbi, + 15419 => Opcode::VPCMPUQZ128rmbik, + 15420 => Opcode::VPCMPUQZ128rmi, + 15421 => Opcode::VPCMPUQZ128rmik, + 15422 => Opcode::VPCMPUQZ128rri, + 15423 => Opcode::VPCMPUQZ128rrik, + 15424 => Opcode::VPCMPUQZ256rmbi, + 15425 => Opcode::VPCMPUQZ256rmbik, + 15426 => Opcode::VPCMPUQZ256rmi, + 15427 => Opcode::VPCMPUQZ256rmik, + 15428 => Opcode::VPCMPUQZ256rri, + 15429 => Opcode::VPCMPUQZ256rrik, + 15430 => Opcode::VPCMPUQZrmbi, + 15431 => Opcode::VPCMPUQZrmbik, + 15432 => Opcode::VPCMPUQZrmi, + 15433 => Opcode::VPCMPUQZrmik, + 15434 => Opcode::VPCMPUQZrri, + 15435 => Opcode::VPCMPUQZrrik, + 15436 => Opcode::VPCMPUWZ128rmi, + 15437 => Opcode::VPCMPUWZ128rmik, + 15438 => Opcode::VPCMPUWZ128rri, + 15439 => Opcode::VPCMPUWZ128rrik, + 15440 => Opcode::VPCMPUWZ256rmi, + 15441 => Opcode::VPCMPUWZ256rmik, + 15442 => Opcode::VPCMPUWZ256rri, + 15443 => Opcode::VPCMPUWZ256rrik, + 15444 => Opcode::VPCMPUWZrmi, + 15445 => Opcode::VPCMPUWZrmik, + 15446 => Opcode::VPCMPUWZrri, + 15447 => Opcode::VPCMPUWZrrik, + 15448 => Opcode::VPCMPWZ128rmi, + 15449 => Opcode::VPCMPWZ128rmik, + 15450 => Opcode::VPCMPWZ128rri, + 15451 => Opcode::VPCMPWZ128rrik, + 15452 => Opcode::VPCMPWZ256rmi, + 15453 => Opcode::VPCMPWZ256rmik, + 15454 => Opcode::VPCMPWZ256rri, + 15455 => Opcode::VPCMPWZ256rrik, + 15456 => Opcode::VPCMPWZrmi, + 15457 => Opcode::VPCMPWZrmik, + 15458 => Opcode::VPCMPWZrri, + 15459 => Opcode::VPCMPWZrrik, + 15460 => Opcode::VPCOMBmi, + 15461 => Opcode::VPCOMBri, + 15462 => Opcode::VPCOMDmi, + 15463 => Opcode::VPCOMDri, + 15464 => Opcode::VPCOMPRESSBZ128mr, + 15465 => Opcode::VPCOMPRESSBZ128mrk, + 15466 => Opcode::VPCOMPRESSBZ128rr, + 15467 => Opcode::VPCOMPRESSBZ128rrk, + 15468 => Opcode::VPCOMPRESSBZ128rrkz, + 15469 => Opcode::VPCOMPRESSBZ256mr, + 15470 => Opcode::VPCOMPRESSBZ256mrk, + 15471 => Opcode::VPCOMPRESSBZ256rr, + 15472 => Opcode::VPCOMPRESSBZ256rrk, + 15473 => Opcode::VPCOMPRESSBZ256rrkz, + 15474 => Opcode::VPCOMPRESSBZmr, + 15475 => Opcode::VPCOMPRESSBZmrk, + 15476 => Opcode::VPCOMPRESSBZrr, + 15477 => Opcode::VPCOMPRESSBZrrk, + 15478 => Opcode::VPCOMPRESSBZrrkz, + 15479 => Opcode::VPCOMPRESSDZ128mr, + 15480 => Opcode::VPCOMPRESSDZ128mrk, + 15481 => Opcode::VPCOMPRESSDZ128rr, + 15482 => Opcode::VPCOMPRESSDZ128rrk, + 15483 => Opcode::VPCOMPRESSDZ128rrkz, + 15484 => Opcode::VPCOMPRESSDZ256mr, + 15485 => Opcode::VPCOMPRESSDZ256mrk, + 15486 => Opcode::VPCOMPRESSDZ256rr, + 15487 => Opcode::VPCOMPRESSDZ256rrk, + 15488 => Opcode::VPCOMPRESSDZ256rrkz, + 15489 => Opcode::VPCOMPRESSDZmr, + 15490 => Opcode::VPCOMPRESSDZmrk, + 15491 => Opcode::VPCOMPRESSDZrr, + 15492 => Opcode::VPCOMPRESSDZrrk, + 15493 => Opcode::VPCOMPRESSDZrrkz, + 15494 => Opcode::VPCOMPRESSQZ128mr, + 15495 => Opcode::VPCOMPRESSQZ128mrk, + 15496 => Opcode::VPCOMPRESSQZ128rr, + 15497 => Opcode::VPCOMPRESSQZ128rrk, + 15498 => Opcode::VPCOMPRESSQZ128rrkz, + 15499 => Opcode::VPCOMPRESSQZ256mr, + 15500 => Opcode::VPCOMPRESSQZ256mrk, + 15501 => Opcode::VPCOMPRESSQZ256rr, + 15502 => Opcode::VPCOMPRESSQZ256rrk, + 15503 => Opcode::VPCOMPRESSQZ256rrkz, + 15504 => Opcode::VPCOMPRESSQZmr, + 15505 => Opcode::VPCOMPRESSQZmrk, + 15506 => Opcode::VPCOMPRESSQZrr, + 15507 => Opcode::VPCOMPRESSQZrrk, + 15508 => Opcode::VPCOMPRESSQZrrkz, + 15509 => Opcode::VPCOMPRESSWZ128mr, + 15510 => Opcode::VPCOMPRESSWZ128mrk, + 15511 => Opcode::VPCOMPRESSWZ128rr, + 15512 => Opcode::VPCOMPRESSWZ128rrk, + 15513 => Opcode::VPCOMPRESSWZ128rrkz, + 15514 => Opcode::VPCOMPRESSWZ256mr, + 15515 => Opcode::VPCOMPRESSWZ256mrk, + 15516 => Opcode::VPCOMPRESSWZ256rr, + 15517 => Opcode::VPCOMPRESSWZ256rrk, + 15518 => Opcode::VPCOMPRESSWZ256rrkz, + 15519 => Opcode::VPCOMPRESSWZmr, + 15520 => Opcode::VPCOMPRESSWZmrk, + 15521 => Opcode::VPCOMPRESSWZrr, + 15522 => Opcode::VPCOMPRESSWZrrk, + 15523 => Opcode::VPCOMPRESSWZrrkz, + 15524 => Opcode::VPCOMQmi, + 15525 => Opcode::VPCOMQri, + 15526 => Opcode::VPCOMUBmi, + 15527 => Opcode::VPCOMUBri, + 15528 => Opcode::VPCOMUDmi, + 15529 => Opcode::VPCOMUDri, + 15530 => Opcode::VPCOMUQmi, + 15531 => Opcode::VPCOMUQri, + 15532 => Opcode::VPCOMUWmi, + 15533 => Opcode::VPCOMUWri, + 15534 => Opcode::VPCOMWmi, + 15535 => Opcode::VPCOMWri, + 15536 => Opcode::VPCONFLICTDZ128rm, + 15537 => Opcode::VPCONFLICTDZ128rmb, + 15538 => Opcode::VPCONFLICTDZ128rmbk, + 15539 => Opcode::VPCONFLICTDZ128rmbkz, + 15540 => Opcode::VPCONFLICTDZ128rmk, + 15541 => Opcode::VPCONFLICTDZ128rmkz, + 15542 => Opcode::VPCONFLICTDZ128rr, + 15543 => Opcode::VPCONFLICTDZ128rrk, + 15544 => Opcode::VPCONFLICTDZ128rrkz, + 15545 => Opcode::VPCONFLICTDZ256rm, + 15546 => Opcode::VPCONFLICTDZ256rmb, + 15547 => Opcode::VPCONFLICTDZ256rmbk, + 15548 => Opcode::VPCONFLICTDZ256rmbkz, + 15549 => Opcode::VPCONFLICTDZ256rmk, + 15550 => Opcode::VPCONFLICTDZ256rmkz, + 15551 => Opcode::VPCONFLICTDZ256rr, + 15552 => Opcode::VPCONFLICTDZ256rrk, + 15553 => Opcode::VPCONFLICTDZ256rrkz, + 15554 => Opcode::VPCONFLICTDZrm, + 15555 => Opcode::VPCONFLICTDZrmb, + 15556 => Opcode::VPCONFLICTDZrmbk, + 15557 => Opcode::VPCONFLICTDZrmbkz, + 15558 => Opcode::VPCONFLICTDZrmk, + 15559 => Opcode::VPCONFLICTDZrmkz, + 15560 => Opcode::VPCONFLICTDZrr, + 15561 => Opcode::VPCONFLICTDZrrk, + 15562 => Opcode::VPCONFLICTDZrrkz, + 15563 => Opcode::VPCONFLICTQZ128rm, + 15564 => Opcode::VPCONFLICTQZ128rmb, + 15565 => Opcode::VPCONFLICTQZ128rmbk, + 15566 => Opcode::VPCONFLICTQZ128rmbkz, + 15567 => Opcode::VPCONFLICTQZ128rmk, + 15568 => Opcode::VPCONFLICTQZ128rmkz, + 15569 => Opcode::VPCONFLICTQZ128rr, + 15570 => Opcode::VPCONFLICTQZ128rrk, + 15571 => Opcode::VPCONFLICTQZ128rrkz, + 15572 => Opcode::VPCONFLICTQZ256rm, + 15573 => Opcode::VPCONFLICTQZ256rmb, + 15574 => Opcode::VPCONFLICTQZ256rmbk, + 15575 => Opcode::VPCONFLICTQZ256rmbkz, + 15576 => Opcode::VPCONFLICTQZ256rmk, + 15577 => Opcode::VPCONFLICTQZ256rmkz, + 15578 => Opcode::VPCONFLICTQZ256rr, + 15579 => Opcode::VPCONFLICTQZ256rrk, + 15580 => Opcode::VPCONFLICTQZ256rrkz, + 15581 => Opcode::VPCONFLICTQZrm, + 15582 => Opcode::VPCONFLICTQZrmb, + 15583 => Opcode::VPCONFLICTQZrmbk, + 15584 => Opcode::VPCONFLICTQZrmbkz, + 15585 => Opcode::VPCONFLICTQZrmk, + 15586 => Opcode::VPCONFLICTQZrmkz, + 15587 => Opcode::VPCONFLICTQZrr, + 15588 => Opcode::VPCONFLICTQZrrk, + 15589 => Opcode::VPCONFLICTQZrrkz, + 15590 => Opcode::VPDPBSSDSYrm, + 15591 => Opcode::VPDPBSSDSYrr, + 15592 => Opcode::VPDPBSSDSZ128rm, + 15593 => Opcode::VPDPBSSDSZ128rmb, + 15594 => Opcode::VPDPBSSDSZ128rmbk, + 15595 => Opcode::VPDPBSSDSZ128rmbkz, + 15596 => Opcode::VPDPBSSDSZ128rmk, + 15597 => Opcode::VPDPBSSDSZ128rmkz, + 15598 => Opcode::VPDPBSSDSZ128rr, + 15599 => Opcode::VPDPBSSDSZ128rrk, + 15600 => Opcode::VPDPBSSDSZ128rrkz, + 15601 => Opcode::VPDPBSSDSZ256rm, + 15602 => Opcode::VPDPBSSDSZ256rmb, + 15603 => Opcode::VPDPBSSDSZ256rmbk, + 15604 => Opcode::VPDPBSSDSZ256rmbkz, + 15605 => Opcode::VPDPBSSDSZ256rmk, + 15606 => Opcode::VPDPBSSDSZ256rmkz, + 15607 => Opcode::VPDPBSSDSZ256rr, + 15608 => Opcode::VPDPBSSDSZ256rrk, + 15609 => Opcode::VPDPBSSDSZ256rrkz, + 15610 => Opcode::VPDPBSSDSZrm, + 15611 => Opcode::VPDPBSSDSZrmb, + 15612 => Opcode::VPDPBSSDSZrmbk, + 15613 => Opcode::VPDPBSSDSZrmbkz, + 15614 => Opcode::VPDPBSSDSZrmk, + 15615 => Opcode::VPDPBSSDSZrmkz, + 15616 => Opcode::VPDPBSSDSZrr, + 15617 => Opcode::VPDPBSSDSZrrk, + 15618 => Opcode::VPDPBSSDSZrrkz, + 15619 => Opcode::VPDPBSSDSrm, + 15620 => Opcode::VPDPBSSDSrr, + 15621 => Opcode::VPDPBSSDYrm, + 15622 => Opcode::VPDPBSSDYrr, + 15623 => Opcode::VPDPBSSDZ128rm, + 15624 => Opcode::VPDPBSSDZ128rmb, + 15625 => Opcode::VPDPBSSDZ128rmbk, + 15626 => Opcode::VPDPBSSDZ128rmbkz, + 15627 => Opcode::VPDPBSSDZ128rmk, + 15628 => Opcode::VPDPBSSDZ128rmkz, + 15629 => Opcode::VPDPBSSDZ128rr, + 15630 => Opcode::VPDPBSSDZ128rrk, + 15631 => Opcode::VPDPBSSDZ128rrkz, + 15632 => Opcode::VPDPBSSDZ256rm, + 15633 => Opcode::VPDPBSSDZ256rmb, + 15634 => Opcode::VPDPBSSDZ256rmbk, + 15635 => Opcode::VPDPBSSDZ256rmbkz, + 15636 => Opcode::VPDPBSSDZ256rmk, + 15637 => Opcode::VPDPBSSDZ256rmkz, + 15638 => Opcode::VPDPBSSDZ256rr, + 15639 => Opcode::VPDPBSSDZ256rrk, + 15640 => Opcode::VPDPBSSDZ256rrkz, + 15641 => Opcode::VPDPBSSDZrm, + 15642 => Opcode::VPDPBSSDZrmb, + 15643 => Opcode::VPDPBSSDZrmbk, + 15644 => Opcode::VPDPBSSDZrmbkz, + 15645 => Opcode::VPDPBSSDZrmk, + 15646 => Opcode::VPDPBSSDZrmkz, + 15647 => Opcode::VPDPBSSDZrr, + 15648 => Opcode::VPDPBSSDZrrk, + 15649 => Opcode::VPDPBSSDZrrkz, + 15650 => Opcode::VPDPBSSDrm, + 15651 => Opcode::VPDPBSSDrr, + 15652 => Opcode::VPDPBSUDSYrm, + 15653 => Opcode::VPDPBSUDSYrr, + 15654 => Opcode::VPDPBSUDSZ128rm, + 15655 => Opcode::VPDPBSUDSZ128rmb, + 15656 => Opcode::VPDPBSUDSZ128rmbk, + 15657 => Opcode::VPDPBSUDSZ128rmbkz, + 15658 => Opcode::VPDPBSUDSZ128rmk, + 15659 => Opcode::VPDPBSUDSZ128rmkz, + 15660 => Opcode::VPDPBSUDSZ128rr, + 15661 => Opcode::VPDPBSUDSZ128rrk, + 15662 => Opcode::VPDPBSUDSZ128rrkz, + 15663 => Opcode::VPDPBSUDSZ256rm, + 15664 => Opcode::VPDPBSUDSZ256rmb, + 15665 => Opcode::VPDPBSUDSZ256rmbk, + 15666 => Opcode::VPDPBSUDSZ256rmbkz, + 15667 => Opcode::VPDPBSUDSZ256rmk, + 15668 => Opcode::VPDPBSUDSZ256rmkz, + 15669 => Opcode::VPDPBSUDSZ256rr, + 15670 => Opcode::VPDPBSUDSZ256rrk, + 15671 => Opcode::VPDPBSUDSZ256rrkz, + 15672 => Opcode::VPDPBSUDSZrm, + 15673 => Opcode::VPDPBSUDSZrmb, + 15674 => Opcode::VPDPBSUDSZrmbk, + 15675 => Opcode::VPDPBSUDSZrmbkz, + 15676 => Opcode::VPDPBSUDSZrmk, + 15677 => Opcode::VPDPBSUDSZrmkz, + 15678 => Opcode::VPDPBSUDSZrr, + 15679 => Opcode::VPDPBSUDSZrrk, + 15680 => Opcode::VPDPBSUDSZrrkz, + 15681 => Opcode::VPDPBSUDSrm, + 15682 => Opcode::VPDPBSUDSrr, + 15683 => Opcode::VPDPBSUDYrm, + 15684 => Opcode::VPDPBSUDYrr, + 15685 => Opcode::VPDPBSUDZ128rm, + 15686 => Opcode::VPDPBSUDZ128rmb, + 15687 => Opcode::VPDPBSUDZ128rmbk, + 15688 => Opcode::VPDPBSUDZ128rmbkz, + 15689 => Opcode::VPDPBSUDZ128rmk, + 15690 => Opcode::VPDPBSUDZ128rmkz, + 15691 => Opcode::VPDPBSUDZ128rr, + 15692 => Opcode::VPDPBSUDZ128rrk, + 15693 => Opcode::VPDPBSUDZ128rrkz, + 15694 => Opcode::VPDPBSUDZ256rm, + 15695 => Opcode::VPDPBSUDZ256rmb, + 15696 => Opcode::VPDPBSUDZ256rmbk, + 15697 => Opcode::VPDPBSUDZ256rmbkz, + 15698 => Opcode::VPDPBSUDZ256rmk, + 15699 => Opcode::VPDPBSUDZ256rmkz, + 15700 => Opcode::VPDPBSUDZ256rr, + 15701 => Opcode::VPDPBSUDZ256rrk, + 15702 => Opcode::VPDPBSUDZ256rrkz, + 15703 => Opcode::VPDPBSUDZrm, + 15704 => Opcode::VPDPBSUDZrmb, + 15705 => Opcode::VPDPBSUDZrmbk, + 15706 => Opcode::VPDPBSUDZrmbkz, + 15707 => Opcode::VPDPBSUDZrmk, + 15708 => Opcode::VPDPBSUDZrmkz, + 15709 => Opcode::VPDPBSUDZrr, + 15710 => Opcode::VPDPBSUDZrrk, + 15711 => Opcode::VPDPBSUDZrrkz, + 15712 => Opcode::VPDPBSUDrm, + 15713 => Opcode::VPDPBSUDrr, + 15714 => Opcode::VPDPBUSDSYrm, + 15715 => Opcode::VPDPBUSDSYrr, + 15716 => Opcode::VPDPBUSDSZ128rm, + 15717 => Opcode::VPDPBUSDSZ128rmb, + 15718 => Opcode::VPDPBUSDSZ128rmbk, + 15719 => Opcode::VPDPBUSDSZ128rmbkz, + 15720 => Opcode::VPDPBUSDSZ128rmk, + 15721 => Opcode::VPDPBUSDSZ128rmkz, + 15722 => Opcode::VPDPBUSDSZ128rr, + 15723 => Opcode::VPDPBUSDSZ128rrk, + 15724 => Opcode::VPDPBUSDSZ128rrkz, + 15725 => Opcode::VPDPBUSDSZ256rm, + 15726 => Opcode::VPDPBUSDSZ256rmb, + 15727 => Opcode::VPDPBUSDSZ256rmbk, + 15728 => Opcode::VPDPBUSDSZ256rmbkz, + 15729 => Opcode::VPDPBUSDSZ256rmk, + 15730 => Opcode::VPDPBUSDSZ256rmkz, + 15731 => Opcode::VPDPBUSDSZ256rr, + 15732 => Opcode::VPDPBUSDSZ256rrk, + 15733 => Opcode::VPDPBUSDSZ256rrkz, + 15734 => Opcode::VPDPBUSDSZrm, + 15735 => Opcode::VPDPBUSDSZrmb, + 15736 => Opcode::VPDPBUSDSZrmbk, + 15737 => Opcode::VPDPBUSDSZrmbkz, + 15738 => Opcode::VPDPBUSDSZrmk, + 15739 => Opcode::VPDPBUSDSZrmkz, + 15740 => Opcode::VPDPBUSDSZrr, + 15741 => Opcode::VPDPBUSDSZrrk, + 15742 => Opcode::VPDPBUSDSZrrkz, + 15743 => Opcode::VPDPBUSDSrm, + 15744 => Opcode::VPDPBUSDSrr, + 15745 => Opcode::VPDPBUSDYrm, + 15746 => Opcode::VPDPBUSDYrr, + 15747 => Opcode::VPDPBUSDZ128rm, + 15748 => Opcode::VPDPBUSDZ128rmb, + 15749 => Opcode::VPDPBUSDZ128rmbk, + 15750 => Opcode::VPDPBUSDZ128rmbkz, + 15751 => Opcode::VPDPBUSDZ128rmk, + 15752 => Opcode::VPDPBUSDZ128rmkz, + 15753 => Opcode::VPDPBUSDZ128rr, + 15754 => Opcode::VPDPBUSDZ128rrk, + 15755 => Opcode::VPDPBUSDZ128rrkz, + 15756 => Opcode::VPDPBUSDZ256rm, + 15757 => Opcode::VPDPBUSDZ256rmb, + 15758 => Opcode::VPDPBUSDZ256rmbk, + 15759 => Opcode::VPDPBUSDZ256rmbkz, + 15760 => Opcode::VPDPBUSDZ256rmk, + 15761 => Opcode::VPDPBUSDZ256rmkz, + 15762 => Opcode::VPDPBUSDZ256rr, + 15763 => Opcode::VPDPBUSDZ256rrk, + 15764 => Opcode::VPDPBUSDZ256rrkz, + 15765 => Opcode::VPDPBUSDZrm, + 15766 => Opcode::VPDPBUSDZrmb, + 15767 => Opcode::VPDPBUSDZrmbk, + 15768 => Opcode::VPDPBUSDZrmbkz, + 15769 => Opcode::VPDPBUSDZrmk, + 15770 => Opcode::VPDPBUSDZrmkz, + 15771 => Opcode::VPDPBUSDZrr, + 15772 => Opcode::VPDPBUSDZrrk, + 15773 => Opcode::VPDPBUSDZrrkz, + 15774 => Opcode::VPDPBUSDrm, + 15775 => Opcode::VPDPBUSDrr, + 15776 => Opcode::VPDPBUUDSYrm, + 15777 => Opcode::VPDPBUUDSYrr, + 15778 => Opcode::VPDPBUUDSZ128rm, + 15779 => Opcode::VPDPBUUDSZ128rmb, + 15780 => Opcode::VPDPBUUDSZ128rmbk, + 15781 => Opcode::VPDPBUUDSZ128rmbkz, + 15782 => Opcode::VPDPBUUDSZ128rmk, + 15783 => Opcode::VPDPBUUDSZ128rmkz, + 15784 => Opcode::VPDPBUUDSZ128rr, + 15785 => Opcode::VPDPBUUDSZ128rrk, + 15786 => Opcode::VPDPBUUDSZ128rrkz, + 15787 => Opcode::VPDPBUUDSZ256rm, + 15788 => Opcode::VPDPBUUDSZ256rmb, + 15789 => Opcode::VPDPBUUDSZ256rmbk, + 15790 => Opcode::VPDPBUUDSZ256rmbkz, + 15791 => Opcode::VPDPBUUDSZ256rmk, + 15792 => Opcode::VPDPBUUDSZ256rmkz, + 15793 => Opcode::VPDPBUUDSZ256rr, + 15794 => Opcode::VPDPBUUDSZ256rrk, + 15795 => Opcode::VPDPBUUDSZ256rrkz, + 15796 => Opcode::VPDPBUUDSZrm, + 15797 => Opcode::VPDPBUUDSZrmb, + 15798 => Opcode::VPDPBUUDSZrmbk, + 15799 => Opcode::VPDPBUUDSZrmbkz, + 15800 => Opcode::VPDPBUUDSZrmk, + 15801 => Opcode::VPDPBUUDSZrmkz, + 15802 => Opcode::VPDPBUUDSZrr, + 15803 => Opcode::VPDPBUUDSZrrk, + 15804 => Opcode::VPDPBUUDSZrrkz, + 15805 => Opcode::VPDPBUUDSrm, + 15806 => Opcode::VPDPBUUDSrr, + 15807 => Opcode::VPDPBUUDYrm, + 15808 => Opcode::VPDPBUUDYrr, + 15809 => Opcode::VPDPBUUDZ128rm, + 15810 => Opcode::VPDPBUUDZ128rmb, + 15811 => Opcode::VPDPBUUDZ128rmbk, + 15812 => Opcode::VPDPBUUDZ128rmbkz, + 15813 => Opcode::VPDPBUUDZ128rmk, + 15814 => Opcode::VPDPBUUDZ128rmkz, + 15815 => Opcode::VPDPBUUDZ128rr, + 15816 => Opcode::VPDPBUUDZ128rrk, + 15817 => Opcode::VPDPBUUDZ128rrkz, + 15818 => Opcode::VPDPBUUDZ256rm, + 15819 => Opcode::VPDPBUUDZ256rmb, + 15820 => Opcode::VPDPBUUDZ256rmbk, + 15821 => Opcode::VPDPBUUDZ256rmbkz, + 15822 => Opcode::VPDPBUUDZ256rmk, + 15823 => Opcode::VPDPBUUDZ256rmkz, + 15824 => Opcode::VPDPBUUDZ256rr, + 15825 => Opcode::VPDPBUUDZ256rrk, + 15826 => Opcode::VPDPBUUDZ256rrkz, + 15827 => Opcode::VPDPBUUDZrm, + 15828 => Opcode::VPDPBUUDZrmb, + 15829 => Opcode::VPDPBUUDZrmbk, + 15830 => Opcode::VPDPBUUDZrmbkz, + 15831 => Opcode::VPDPBUUDZrmk, + 15832 => Opcode::VPDPBUUDZrmkz, + 15833 => Opcode::VPDPBUUDZrr, + 15834 => Opcode::VPDPBUUDZrrk, + 15835 => Opcode::VPDPBUUDZrrkz, + 15836 => Opcode::VPDPBUUDrm, + 15837 => Opcode::VPDPBUUDrr, + 15838 => Opcode::VPDPWSSDSYrm, + 15839 => Opcode::VPDPWSSDSYrr, + 15840 => Opcode::VPDPWSSDSZ128rm, + 15841 => Opcode::VPDPWSSDSZ128rmb, + 15842 => Opcode::VPDPWSSDSZ128rmbk, + 15843 => Opcode::VPDPWSSDSZ128rmbkz, + 15844 => Opcode::VPDPWSSDSZ128rmk, + 15845 => Opcode::VPDPWSSDSZ128rmkz, + 15846 => Opcode::VPDPWSSDSZ128rr, + 15847 => Opcode::VPDPWSSDSZ128rrk, + 15848 => Opcode::VPDPWSSDSZ128rrkz, + 15849 => Opcode::VPDPWSSDSZ256rm, + 15850 => Opcode::VPDPWSSDSZ256rmb, + 15851 => Opcode::VPDPWSSDSZ256rmbk, + 15852 => Opcode::VPDPWSSDSZ256rmbkz, + 15853 => Opcode::VPDPWSSDSZ256rmk, + 15854 => Opcode::VPDPWSSDSZ256rmkz, + 15855 => Opcode::VPDPWSSDSZ256rr, + 15856 => Opcode::VPDPWSSDSZ256rrk, + 15857 => Opcode::VPDPWSSDSZ256rrkz, + 15858 => Opcode::VPDPWSSDSZrm, + 15859 => Opcode::VPDPWSSDSZrmb, + 15860 => Opcode::VPDPWSSDSZrmbk, + 15861 => Opcode::VPDPWSSDSZrmbkz, + 15862 => Opcode::VPDPWSSDSZrmk, + 15863 => Opcode::VPDPWSSDSZrmkz, + 15864 => Opcode::VPDPWSSDSZrr, + 15865 => Opcode::VPDPWSSDSZrrk, + 15866 => Opcode::VPDPWSSDSZrrkz, + 15867 => Opcode::VPDPWSSDSrm, + 15868 => Opcode::VPDPWSSDSrr, + 15869 => Opcode::VPDPWSSDYrm, + 15870 => Opcode::VPDPWSSDYrr, + 15871 => Opcode::VPDPWSSDZ128rm, + 15872 => Opcode::VPDPWSSDZ128rmb, + 15873 => Opcode::VPDPWSSDZ128rmbk, + 15874 => Opcode::VPDPWSSDZ128rmbkz, + 15875 => Opcode::VPDPWSSDZ128rmk, + 15876 => Opcode::VPDPWSSDZ128rmkz, + 15877 => Opcode::VPDPWSSDZ128rr, + 15878 => Opcode::VPDPWSSDZ128rrk, + 15879 => Opcode::VPDPWSSDZ128rrkz, + 15880 => Opcode::VPDPWSSDZ256rm, + 15881 => Opcode::VPDPWSSDZ256rmb, + 15882 => Opcode::VPDPWSSDZ256rmbk, + 15883 => Opcode::VPDPWSSDZ256rmbkz, + 15884 => Opcode::VPDPWSSDZ256rmk, + 15885 => Opcode::VPDPWSSDZ256rmkz, + 15886 => Opcode::VPDPWSSDZ256rr, + 15887 => Opcode::VPDPWSSDZ256rrk, + 15888 => Opcode::VPDPWSSDZ256rrkz, + 15889 => Opcode::VPDPWSSDZrm, + 15890 => Opcode::VPDPWSSDZrmb, + 15891 => Opcode::VPDPWSSDZrmbk, + 15892 => Opcode::VPDPWSSDZrmbkz, + 15893 => Opcode::VPDPWSSDZrmk, + 15894 => Opcode::VPDPWSSDZrmkz, + 15895 => Opcode::VPDPWSSDZrr, + 15896 => Opcode::VPDPWSSDZrrk, + 15897 => Opcode::VPDPWSSDZrrkz, + 15898 => Opcode::VPDPWSSDrm, + 15899 => Opcode::VPDPWSSDrr, + 15900 => Opcode::VPDPWSUDSYrm, + 15901 => Opcode::VPDPWSUDSYrr, + 15902 => Opcode::VPDPWSUDSZ128rm, + 15903 => Opcode::VPDPWSUDSZ128rmb, + 15904 => Opcode::VPDPWSUDSZ128rmbk, + 15905 => Opcode::VPDPWSUDSZ128rmbkz, + 15906 => Opcode::VPDPWSUDSZ128rmk, + 15907 => Opcode::VPDPWSUDSZ128rmkz, + 15908 => Opcode::VPDPWSUDSZ128rr, + 15909 => Opcode::VPDPWSUDSZ128rrk, + 15910 => Opcode::VPDPWSUDSZ128rrkz, + 15911 => Opcode::VPDPWSUDSZ256rm, + 15912 => Opcode::VPDPWSUDSZ256rmb, + 15913 => Opcode::VPDPWSUDSZ256rmbk, + 15914 => Opcode::VPDPWSUDSZ256rmbkz, + 15915 => Opcode::VPDPWSUDSZ256rmk, + 15916 => Opcode::VPDPWSUDSZ256rmkz, + 15917 => Opcode::VPDPWSUDSZ256rr, + 15918 => Opcode::VPDPWSUDSZ256rrk, + 15919 => Opcode::VPDPWSUDSZ256rrkz, + 15920 => Opcode::VPDPWSUDSZrm, + 15921 => Opcode::VPDPWSUDSZrmb, + 15922 => Opcode::VPDPWSUDSZrmbk, + 15923 => Opcode::VPDPWSUDSZrmbkz, + 15924 => Opcode::VPDPWSUDSZrmk, + 15925 => Opcode::VPDPWSUDSZrmkz, + 15926 => Opcode::VPDPWSUDSZrr, + 15927 => Opcode::VPDPWSUDSZrrk, + 15928 => Opcode::VPDPWSUDSZrrkz, + 15929 => Opcode::VPDPWSUDSrm, + 15930 => Opcode::VPDPWSUDSrr, + 15931 => Opcode::VPDPWSUDYrm, + 15932 => Opcode::VPDPWSUDYrr, + 15933 => Opcode::VPDPWSUDZ128rm, + 15934 => Opcode::VPDPWSUDZ128rmb, + 15935 => Opcode::VPDPWSUDZ128rmbk, + 15936 => Opcode::VPDPWSUDZ128rmbkz, + 15937 => Opcode::VPDPWSUDZ128rmk, + 15938 => Opcode::VPDPWSUDZ128rmkz, + 15939 => Opcode::VPDPWSUDZ128rr, + 15940 => Opcode::VPDPWSUDZ128rrk, + 15941 => Opcode::VPDPWSUDZ128rrkz, + 15942 => Opcode::VPDPWSUDZ256rm, + 15943 => Opcode::VPDPWSUDZ256rmb, + 15944 => Opcode::VPDPWSUDZ256rmbk, + 15945 => Opcode::VPDPWSUDZ256rmbkz, + 15946 => Opcode::VPDPWSUDZ256rmk, + 15947 => Opcode::VPDPWSUDZ256rmkz, + 15948 => Opcode::VPDPWSUDZ256rr, + 15949 => Opcode::VPDPWSUDZ256rrk, + 15950 => Opcode::VPDPWSUDZ256rrkz, + 15951 => Opcode::VPDPWSUDZrm, + 15952 => Opcode::VPDPWSUDZrmb, + 15953 => Opcode::VPDPWSUDZrmbk, + 15954 => Opcode::VPDPWSUDZrmbkz, + 15955 => Opcode::VPDPWSUDZrmk, + 15956 => Opcode::VPDPWSUDZrmkz, + 15957 => Opcode::VPDPWSUDZrr, + 15958 => Opcode::VPDPWSUDZrrk, + 15959 => Opcode::VPDPWSUDZrrkz, + 15960 => Opcode::VPDPWSUDrm, + 15961 => Opcode::VPDPWSUDrr, + 15962 => Opcode::VPDPWUSDSYrm, + 15963 => Opcode::VPDPWUSDSYrr, + 15964 => Opcode::VPDPWUSDSZ128rm, + 15965 => Opcode::VPDPWUSDSZ128rmb, + 15966 => Opcode::VPDPWUSDSZ128rmbk, + 15967 => Opcode::VPDPWUSDSZ128rmbkz, + 15968 => Opcode::VPDPWUSDSZ128rmk, + 15969 => Opcode::VPDPWUSDSZ128rmkz, + 15970 => Opcode::VPDPWUSDSZ128rr, + 15971 => Opcode::VPDPWUSDSZ128rrk, + 15972 => Opcode::VPDPWUSDSZ128rrkz, + 15973 => Opcode::VPDPWUSDSZ256rm, + 15974 => Opcode::VPDPWUSDSZ256rmb, + 15975 => Opcode::VPDPWUSDSZ256rmbk, + 15976 => Opcode::VPDPWUSDSZ256rmbkz, + 15977 => Opcode::VPDPWUSDSZ256rmk, + 15978 => Opcode::VPDPWUSDSZ256rmkz, + 15979 => Opcode::VPDPWUSDSZ256rr, + 15980 => Opcode::VPDPWUSDSZ256rrk, + 15981 => Opcode::VPDPWUSDSZ256rrkz, + 15982 => Opcode::VPDPWUSDSZrm, + 15983 => Opcode::VPDPWUSDSZrmb, + 15984 => Opcode::VPDPWUSDSZrmbk, + 15985 => Opcode::VPDPWUSDSZrmbkz, + 15986 => Opcode::VPDPWUSDSZrmk, + 15987 => Opcode::VPDPWUSDSZrmkz, + 15988 => Opcode::VPDPWUSDSZrr, + 15989 => Opcode::VPDPWUSDSZrrk, + 15990 => Opcode::VPDPWUSDSZrrkz, + 15991 => Opcode::VPDPWUSDSrm, + 15992 => Opcode::VPDPWUSDSrr, + 15993 => Opcode::VPDPWUSDYrm, + 15994 => Opcode::VPDPWUSDYrr, + 15995 => Opcode::VPDPWUSDZ128rm, + 15996 => Opcode::VPDPWUSDZ128rmb, + 15997 => Opcode::VPDPWUSDZ128rmbk, + 15998 => Opcode::VPDPWUSDZ128rmbkz, + 15999 => Opcode::VPDPWUSDZ128rmk, + 16000 => Opcode::VPDPWUSDZ128rmkz, + 16001 => Opcode::VPDPWUSDZ128rr, + 16002 => Opcode::VPDPWUSDZ128rrk, + 16003 => Opcode::VPDPWUSDZ128rrkz, + 16004 => Opcode::VPDPWUSDZ256rm, + 16005 => Opcode::VPDPWUSDZ256rmb, + 16006 => Opcode::VPDPWUSDZ256rmbk, + 16007 => Opcode::VPDPWUSDZ256rmbkz, + 16008 => Opcode::VPDPWUSDZ256rmk, + 16009 => Opcode::VPDPWUSDZ256rmkz, + 16010 => Opcode::VPDPWUSDZ256rr, + 16011 => Opcode::VPDPWUSDZ256rrk, + 16012 => Opcode::VPDPWUSDZ256rrkz, + 16013 => Opcode::VPDPWUSDZrm, + 16014 => Opcode::VPDPWUSDZrmb, + 16015 => Opcode::VPDPWUSDZrmbk, + 16016 => Opcode::VPDPWUSDZrmbkz, + 16017 => Opcode::VPDPWUSDZrmk, + 16018 => Opcode::VPDPWUSDZrmkz, + 16019 => Opcode::VPDPWUSDZrr, + 16020 => Opcode::VPDPWUSDZrrk, + 16021 => Opcode::VPDPWUSDZrrkz, + 16022 => Opcode::VPDPWUSDrm, + 16023 => Opcode::VPDPWUSDrr, + 16024 => Opcode::VPDPWUUDSYrm, + 16025 => Opcode::VPDPWUUDSYrr, + 16026 => Opcode::VPDPWUUDSZ128rm, + 16027 => Opcode::VPDPWUUDSZ128rmb, + 16028 => Opcode::VPDPWUUDSZ128rmbk, + 16029 => Opcode::VPDPWUUDSZ128rmbkz, + 16030 => Opcode::VPDPWUUDSZ128rmk, + 16031 => Opcode::VPDPWUUDSZ128rmkz, + 16032 => Opcode::VPDPWUUDSZ128rr, + 16033 => Opcode::VPDPWUUDSZ128rrk, + 16034 => Opcode::VPDPWUUDSZ128rrkz, + 16035 => Opcode::VPDPWUUDSZ256rm, + 16036 => Opcode::VPDPWUUDSZ256rmb, + 16037 => Opcode::VPDPWUUDSZ256rmbk, + 16038 => Opcode::VPDPWUUDSZ256rmbkz, + 16039 => Opcode::VPDPWUUDSZ256rmk, + 16040 => Opcode::VPDPWUUDSZ256rmkz, + 16041 => Opcode::VPDPWUUDSZ256rr, + 16042 => Opcode::VPDPWUUDSZ256rrk, + 16043 => Opcode::VPDPWUUDSZ256rrkz, + 16044 => Opcode::VPDPWUUDSZrm, + 16045 => Opcode::VPDPWUUDSZrmb, + 16046 => Opcode::VPDPWUUDSZrmbk, + 16047 => Opcode::VPDPWUUDSZrmbkz, + 16048 => Opcode::VPDPWUUDSZrmk, + 16049 => Opcode::VPDPWUUDSZrmkz, + 16050 => Opcode::VPDPWUUDSZrr, + 16051 => Opcode::VPDPWUUDSZrrk, + 16052 => Opcode::VPDPWUUDSZrrkz, + 16053 => Opcode::VPDPWUUDSrm, + 16054 => Opcode::VPDPWUUDSrr, + 16055 => Opcode::VPDPWUUDYrm, + 16056 => Opcode::VPDPWUUDYrr, + 16057 => Opcode::VPDPWUUDZ128rm, + 16058 => Opcode::VPDPWUUDZ128rmb, + 16059 => Opcode::VPDPWUUDZ128rmbk, + 16060 => Opcode::VPDPWUUDZ128rmbkz, + 16061 => Opcode::VPDPWUUDZ128rmk, + 16062 => Opcode::VPDPWUUDZ128rmkz, + 16063 => Opcode::VPDPWUUDZ128rr, + 16064 => Opcode::VPDPWUUDZ128rrk, + 16065 => Opcode::VPDPWUUDZ128rrkz, + 16066 => Opcode::VPDPWUUDZ256rm, + 16067 => Opcode::VPDPWUUDZ256rmb, + 16068 => Opcode::VPDPWUUDZ256rmbk, + 16069 => Opcode::VPDPWUUDZ256rmbkz, + 16070 => Opcode::VPDPWUUDZ256rmk, + 16071 => Opcode::VPDPWUUDZ256rmkz, + 16072 => Opcode::VPDPWUUDZ256rr, + 16073 => Opcode::VPDPWUUDZ256rrk, + 16074 => Opcode::VPDPWUUDZ256rrkz, + 16075 => Opcode::VPDPWUUDZrm, + 16076 => Opcode::VPDPWUUDZrmb, + 16077 => Opcode::VPDPWUUDZrmbk, + 16078 => Opcode::VPDPWUUDZrmbkz, + 16079 => Opcode::VPDPWUUDZrmk, + 16080 => Opcode::VPDPWUUDZrmkz, + 16081 => Opcode::VPDPWUUDZrr, + 16082 => Opcode::VPDPWUUDZrrk, + 16083 => Opcode::VPDPWUUDZrrkz, + 16084 => Opcode::VPDPWUUDrm, + 16085 => Opcode::VPDPWUUDrr, + 16086 => Opcode::VPERM2F128rmi, + 16087 => Opcode::VPERM2F128rri, + 16088 => Opcode::VPERM2I128rmi, + 16089 => Opcode::VPERM2I128rri, + 16090 => Opcode::VPERMBZ128rm, + 16091 => Opcode::VPERMBZ128rmk, + 16092 => Opcode::VPERMBZ128rmkz, + 16093 => Opcode::VPERMBZ128rr, + 16094 => Opcode::VPERMBZ128rrk, + 16095 => Opcode::VPERMBZ128rrkz, + 16096 => Opcode::VPERMBZ256rm, + 16097 => Opcode::VPERMBZ256rmk, + 16098 => Opcode::VPERMBZ256rmkz, + 16099 => Opcode::VPERMBZ256rr, + 16100 => Opcode::VPERMBZ256rrk, + 16101 => Opcode::VPERMBZ256rrkz, + 16102 => Opcode::VPERMBZrm, + 16103 => Opcode::VPERMBZrmk, + 16104 => Opcode::VPERMBZrmkz, + 16105 => Opcode::VPERMBZrr, + 16106 => Opcode::VPERMBZrrk, + 16107 => Opcode::VPERMBZrrkz, + 16108 => Opcode::VPERMDYrm, + 16109 => Opcode::VPERMDYrr, + 16110 => Opcode::VPERMDZ256rm, + 16111 => Opcode::VPERMDZ256rmb, + 16112 => Opcode::VPERMDZ256rmbk, + 16113 => Opcode::VPERMDZ256rmbkz, + 16114 => Opcode::VPERMDZ256rmk, + 16115 => Opcode::VPERMDZ256rmkz, + 16116 => Opcode::VPERMDZ256rr, + 16117 => Opcode::VPERMDZ256rrk, + 16118 => Opcode::VPERMDZ256rrkz, + 16119 => Opcode::VPERMDZrm, + 16120 => Opcode::VPERMDZrmb, + 16121 => Opcode::VPERMDZrmbk, + 16122 => Opcode::VPERMDZrmbkz, + 16123 => Opcode::VPERMDZrmk, + 16124 => Opcode::VPERMDZrmkz, + 16125 => Opcode::VPERMDZrr, + 16126 => Opcode::VPERMDZrrk, + 16127 => Opcode::VPERMDZrrkz, + 16128 => Opcode::VPERMI2BZ128rm, + 16129 => Opcode::VPERMI2BZ128rmk, + 16130 => Opcode::VPERMI2BZ128rmkz, + 16131 => Opcode::VPERMI2BZ128rr, + 16132 => Opcode::VPERMI2BZ128rrk, + 16133 => Opcode::VPERMI2BZ128rrkz, + 16134 => Opcode::VPERMI2BZ256rm, + 16135 => Opcode::VPERMI2BZ256rmk, + 16136 => Opcode::VPERMI2BZ256rmkz, + 16137 => Opcode::VPERMI2BZ256rr, + 16138 => Opcode::VPERMI2BZ256rrk, + 16139 => Opcode::VPERMI2BZ256rrkz, + 16140 => Opcode::VPERMI2BZrm, + 16141 => Opcode::VPERMI2BZrmk, + 16142 => Opcode::VPERMI2BZrmkz, + 16143 => Opcode::VPERMI2BZrr, + 16144 => Opcode::VPERMI2BZrrk, + 16145 => Opcode::VPERMI2BZrrkz, + 16146 => Opcode::VPERMI2DZ128rm, + 16147 => Opcode::VPERMI2DZ128rmb, + 16148 => Opcode::VPERMI2DZ128rmbk, + 16149 => Opcode::VPERMI2DZ128rmbkz, + 16150 => Opcode::VPERMI2DZ128rmk, + 16151 => Opcode::VPERMI2DZ128rmkz, + 16152 => Opcode::VPERMI2DZ128rr, + 16153 => Opcode::VPERMI2DZ128rrk, + 16154 => Opcode::VPERMI2DZ128rrkz, + 16155 => Opcode::VPERMI2DZ256rm, + 16156 => Opcode::VPERMI2DZ256rmb, + 16157 => Opcode::VPERMI2DZ256rmbk, + 16158 => Opcode::VPERMI2DZ256rmbkz, + 16159 => Opcode::VPERMI2DZ256rmk, + 16160 => Opcode::VPERMI2DZ256rmkz, + 16161 => Opcode::VPERMI2DZ256rr, + 16162 => Opcode::VPERMI2DZ256rrk, + 16163 => Opcode::VPERMI2DZ256rrkz, + 16164 => Opcode::VPERMI2DZrm, + 16165 => Opcode::VPERMI2DZrmb, + 16166 => Opcode::VPERMI2DZrmbk, + 16167 => Opcode::VPERMI2DZrmbkz, + 16168 => Opcode::VPERMI2DZrmk, + 16169 => Opcode::VPERMI2DZrmkz, + 16170 => Opcode::VPERMI2DZrr, + 16171 => Opcode::VPERMI2DZrrk, + 16172 => Opcode::VPERMI2DZrrkz, + 16173 => Opcode::VPERMI2PDZ128rm, + 16174 => Opcode::VPERMI2PDZ128rmb, + 16175 => Opcode::VPERMI2PDZ128rmbk, + 16176 => Opcode::VPERMI2PDZ128rmbkz, + 16177 => Opcode::VPERMI2PDZ128rmk, + 16178 => Opcode::VPERMI2PDZ128rmkz, + 16179 => Opcode::VPERMI2PDZ128rr, + 16180 => Opcode::VPERMI2PDZ128rrk, + 16181 => Opcode::VPERMI2PDZ128rrkz, + 16182 => Opcode::VPERMI2PDZ256rm, + 16183 => Opcode::VPERMI2PDZ256rmb, + 16184 => Opcode::VPERMI2PDZ256rmbk, + 16185 => Opcode::VPERMI2PDZ256rmbkz, + 16186 => Opcode::VPERMI2PDZ256rmk, + 16187 => Opcode::VPERMI2PDZ256rmkz, + 16188 => Opcode::VPERMI2PDZ256rr, + 16189 => Opcode::VPERMI2PDZ256rrk, + 16190 => Opcode::VPERMI2PDZ256rrkz, + 16191 => Opcode::VPERMI2PDZrm, + 16192 => Opcode::VPERMI2PDZrmb, + 16193 => Opcode::VPERMI2PDZrmbk, + 16194 => Opcode::VPERMI2PDZrmbkz, + 16195 => Opcode::VPERMI2PDZrmk, + 16196 => Opcode::VPERMI2PDZrmkz, + 16197 => Opcode::VPERMI2PDZrr, + 16198 => Opcode::VPERMI2PDZrrk, + 16199 => Opcode::VPERMI2PDZrrkz, + 16200 => Opcode::VPERMI2PSZ128rm, + 16201 => Opcode::VPERMI2PSZ128rmb, + 16202 => Opcode::VPERMI2PSZ128rmbk, + 16203 => Opcode::VPERMI2PSZ128rmbkz, + 16204 => Opcode::VPERMI2PSZ128rmk, + 16205 => Opcode::VPERMI2PSZ128rmkz, + 16206 => Opcode::VPERMI2PSZ128rr, + 16207 => Opcode::VPERMI2PSZ128rrk, + 16208 => Opcode::VPERMI2PSZ128rrkz, + 16209 => Opcode::VPERMI2PSZ256rm, + 16210 => Opcode::VPERMI2PSZ256rmb, + 16211 => Opcode::VPERMI2PSZ256rmbk, + 16212 => Opcode::VPERMI2PSZ256rmbkz, + 16213 => Opcode::VPERMI2PSZ256rmk, + 16214 => Opcode::VPERMI2PSZ256rmkz, + 16215 => Opcode::VPERMI2PSZ256rr, + 16216 => Opcode::VPERMI2PSZ256rrk, + 16217 => Opcode::VPERMI2PSZ256rrkz, + 16218 => Opcode::VPERMI2PSZrm, + 16219 => Opcode::VPERMI2PSZrmb, + 16220 => Opcode::VPERMI2PSZrmbk, + 16221 => Opcode::VPERMI2PSZrmbkz, + 16222 => Opcode::VPERMI2PSZrmk, + 16223 => Opcode::VPERMI2PSZrmkz, + 16224 => Opcode::VPERMI2PSZrr, + 16225 => Opcode::VPERMI2PSZrrk, + 16226 => Opcode::VPERMI2PSZrrkz, + 16227 => Opcode::VPERMI2QZ128rm, + 16228 => Opcode::VPERMI2QZ128rmb, + 16229 => Opcode::VPERMI2QZ128rmbk, + 16230 => Opcode::VPERMI2QZ128rmbkz, + 16231 => Opcode::VPERMI2QZ128rmk, + 16232 => Opcode::VPERMI2QZ128rmkz, + 16233 => Opcode::VPERMI2QZ128rr, + 16234 => Opcode::VPERMI2QZ128rrk, + 16235 => Opcode::VPERMI2QZ128rrkz, + 16236 => Opcode::VPERMI2QZ256rm, + 16237 => Opcode::VPERMI2QZ256rmb, + 16238 => Opcode::VPERMI2QZ256rmbk, + 16239 => Opcode::VPERMI2QZ256rmbkz, + 16240 => Opcode::VPERMI2QZ256rmk, + 16241 => Opcode::VPERMI2QZ256rmkz, + 16242 => Opcode::VPERMI2QZ256rr, + 16243 => Opcode::VPERMI2QZ256rrk, + 16244 => Opcode::VPERMI2QZ256rrkz, + 16245 => Opcode::VPERMI2QZrm, + 16246 => Opcode::VPERMI2QZrmb, + 16247 => Opcode::VPERMI2QZrmbk, + 16248 => Opcode::VPERMI2QZrmbkz, + 16249 => Opcode::VPERMI2QZrmk, + 16250 => Opcode::VPERMI2QZrmkz, + 16251 => Opcode::VPERMI2QZrr, + 16252 => Opcode::VPERMI2QZrrk, + 16253 => Opcode::VPERMI2QZrrkz, + 16254 => Opcode::VPERMI2WZ128rm, + 16255 => Opcode::VPERMI2WZ128rmk, + 16256 => Opcode::VPERMI2WZ128rmkz, + 16257 => Opcode::VPERMI2WZ128rr, + 16258 => Opcode::VPERMI2WZ128rrk, + 16259 => Opcode::VPERMI2WZ128rrkz, + 16260 => Opcode::VPERMI2WZ256rm, + 16261 => Opcode::VPERMI2WZ256rmk, + 16262 => Opcode::VPERMI2WZ256rmkz, + 16263 => Opcode::VPERMI2WZ256rr, + 16264 => Opcode::VPERMI2WZ256rrk, + 16265 => Opcode::VPERMI2WZ256rrkz, + 16266 => Opcode::VPERMI2WZrm, + 16267 => Opcode::VPERMI2WZrmk, + 16268 => Opcode::VPERMI2WZrmkz, + 16269 => Opcode::VPERMI2WZrr, + 16270 => Opcode::VPERMI2WZrrk, + 16271 => Opcode::VPERMI2WZrrkz, + 16272 => Opcode::VPERMIL2PDYmr, + 16273 => Opcode::VPERMIL2PDYrm, + 16274 => Opcode::VPERMIL2PDYrr, + 16275 => Opcode::VPERMIL2PDYrr_REV, + 16276 => Opcode::VPERMIL2PDmr, + 16277 => Opcode::VPERMIL2PDrm, + 16278 => Opcode::VPERMIL2PDrr, + 16279 => Opcode::VPERMIL2PDrr_REV, + 16280 => Opcode::VPERMIL2PSYmr, + 16281 => Opcode::VPERMIL2PSYrm, + 16282 => Opcode::VPERMIL2PSYrr, + 16283 => Opcode::VPERMIL2PSYrr_REV, + 16284 => Opcode::VPERMIL2PSmr, + 16285 => Opcode::VPERMIL2PSrm, + 16286 => Opcode::VPERMIL2PSrr, + 16287 => Opcode::VPERMIL2PSrr_REV, + 16288 => Opcode::VPERMILPDYmi, + 16289 => Opcode::VPERMILPDYri, + 16290 => Opcode::VPERMILPDYrm, + 16291 => Opcode::VPERMILPDYrr, + 16292 => Opcode::VPERMILPDZ128mbi, + 16293 => Opcode::VPERMILPDZ128mbik, + 16294 => Opcode::VPERMILPDZ128mbikz, + 16295 => Opcode::VPERMILPDZ128mi, + 16296 => Opcode::VPERMILPDZ128mik, + 16297 => Opcode::VPERMILPDZ128mikz, + 16298 => Opcode::VPERMILPDZ128ri, + 16299 => Opcode::VPERMILPDZ128rik, + 16300 => Opcode::VPERMILPDZ128rikz, + 16301 => Opcode::VPERMILPDZ128rm, + 16302 => Opcode::VPERMILPDZ128rmb, + 16303 => Opcode::VPERMILPDZ128rmbk, + 16304 => Opcode::VPERMILPDZ128rmbkz, + 16305 => Opcode::VPERMILPDZ128rmk, + 16306 => Opcode::VPERMILPDZ128rmkz, + 16307 => Opcode::VPERMILPDZ128rr, + 16308 => Opcode::VPERMILPDZ128rrk, + 16309 => Opcode::VPERMILPDZ128rrkz, + 16310 => Opcode::VPERMILPDZ256mbi, + 16311 => Opcode::VPERMILPDZ256mbik, + 16312 => Opcode::VPERMILPDZ256mbikz, + 16313 => Opcode::VPERMILPDZ256mi, + 16314 => Opcode::VPERMILPDZ256mik, + 16315 => Opcode::VPERMILPDZ256mikz, + 16316 => Opcode::VPERMILPDZ256ri, + 16317 => Opcode::VPERMILPDZ256rik, + 16318 => Opcode::VPERMILPDZ256rikz, + 16319 => Opcode::VPERMILPDZ256rm, + 16320 => Opcode::VPERMILPDZ256rmb, + 16321 => Opcode::VPERMILPDZ256rmbk, + 16322 => Opcode::VPERMILPDZ256rmbkz, + 16323 => Opcode::VPERMILPDZ256rmk, + 16324 => Opcode::VPERMILPDZ256rmkz, + 16325 => Opcode::VPERMILPDZ256rr, + 16326 => Opcode::VPERMILPDZ256rrk, + 16327 => Opcode::VPERMILPDZ256rrkz, + 16328 => Opcode::VPERMILPDZmbi, + 16329 => Opcode::VPERMILPDZmbik, + 16330 => Opcode::VPERMILPDZmbikz, + 16331 => Opcode::VPERMILPDZmi, + 16332 => Opcode::VPERMILPDZmik, + 16333 => Opcode::VPERMILPDZmikz, + 16334 => Opcode::VPERMILPDZri, + 16335 => Opcode::VPERMILPDZrik, + 16336 => Opcode::VPERMILPDZrikz, + 16337 => Opcode::VPERMILPDZrm, + 16338 => Opcode::VPERMILPDZrmb, + 16339 => Opcode::VPERMILPDZrmbk, + 16340 => Opcode::VPERMILPDZrmbkz, + 16341 => Opcode::VPERMILPDZrmk, + 16342 => Opcode::VPERMILPDZrmkz, + 16343 => Opcode::VPERMILPDZrr, + 16344 => Opcode::VPERMILPDZrrk, + 16345 => Opcode::VPERMILPDZrrkz, + 16346 => Opcode::VPERMILPDmi, + 16347 => Opcode::VPERMILPDri, + 16348 => Opcode::VPERMILPDrm, + 16349 => Opcode::VPERMILPDrr, + 16350 => Opcode::VPERMILPSYmi, + 16351 => Opcode::VPERMILPSYri, + 16352 => Opcode::VPERMILPSYrm, + 16353 => Opcode::VPERMILPSYrr, + 16354 => Opcode::VPERMILPSZ128mbi, + 16355 => Opcode::VPERMILPSZ128mbik, + 16356 => Opcode::VPERMILPSZ128mbikz, + 16357 => Opcode::VPERMILPSZ128mi, + 16358 => Opcode::VPERMILPSZ128mik, + 16359 => Opcode::VPERMILPSZ128mikz, + 16360 => Opcode::VPERMILPSZ128ri, + 16361 => Opcode::VPERMILPSZ128rik, + 16362 => Opcode::VPERMILPSZ128rikz, + 16363 => Opcode::VPERMILPSZ128rm, + 16364 => Opcode::VPERMILPSZ128rmb, + 16365 => Opcode::VPERMILPSZ128rmbk, + 16366 => Opcode::VPERMILPSZ128rmbkz, + 16367 => Opcode::VPERMILPSZ128rmk, + 16368 => Opcode::VPERMILPSZ128rmkz, + 16369 => Opcode::VPERMILPSZ128rr, + 16370 => Opcode::VPERMILPSZ128rrk, + 16371 => Opcode::VPERMILPSZ128rrkz, + 16372 => Opcode::VPERMILPSZ256mbi, + 16373 => Opcode::VPERMILPSZ256mbik, + 16374 => Opcode::VPERMILPSZ256mbikz, + 16375 => Opcode::VPERMILPSZ256mi, + 16376 => Opcode::VPERMILPSZ256mik, + 16377 => Opcode::VPERMILPSZ256mikz, + 16378 => Opcode::VPERMILPSZ256ri, + 16379 => Opcode::VPERMILPSZ256rik, + 16380 => Opcode::VPERMILPSZ256rikz, + 16381 => Opcode::VPERMILPSZ256rm, + 16382 => Opcode::VPERMILPSZ256rmb, + 16383 => Opcode::VPERMILPSZ256rmbk, + 16384 => Opcode::VPERMILPSZ256rmbkz, + 16385 => Opcode::VPERMILPSZ256rmk, + 16386 => Opcode::VPERMILPSZ256rmkz, + 16387 => Opcode::VPERMILPSZ256rr, + 16388 => Opcode::VPERMILPSZ256rrk, + 16389 => Opcode::VPERMILPSZ256rrkz, + 16390 => Opcode::VPERMILPSZmbi, + 16391 => Opcode::VPERMILPSZmbik, + 16392 => Opcode::VPERMILPSZmbikz, + 16393 => Opcode::VPERMILPSZmi, + 16394 => Opcode::VPERMILPSZmik, + 16395 => Opcode::VPERMILPSZmikz, + 16396 => Opcode::VPERMILPSZri, + 16397 => Opcode::VPERMILPSZrik, + 16398 => Opcode::VPERMILPSZrikz, + 16399 => Opcode::VPERMILPSZrm, + 16400 => Opcode::VPERMILPSZrmb, + 16401 => Opcode::VPERMILPSZrmbk, + 16402 => Opcode::VPERMILPSZrmbkz, + 16403 => Opcode::VPERMILPSZrmk, + 16404 => Opcode::VPERMILPSZrmkz, + 16405 => Opcode::VPERMILPSZrr, + 16406 => Opcode::VPERMILPSZrrk, + 16407 => Opcode::VPERMILPSZrrkz, + 16408 => Opcode::VPERMILPSmi, + 16409 => Opcode::VPERMILPSri, + 16410 => Opcode::VPERMILPSrm, + 16411 => Opcode::VPERMILPSrr, + 16412 => Opcode::VPERMPDYmi, + 16413 => Opcode::VPERMPDYri, + 16414 => Opcode::VPERMPDZ256mbi, + 16415 => Opcode::VPERMPDZ256mbik, + 16416 => Opcode::VPERMPDZ256mbikz, + 16417 => Opcode::VPERMPDZ256mi, + 16418 => Opcode::VPERMPDZ256mik, + 16419 => Opcode::VPERMPDZ256mikz, + 16420 => Opcode::VPERMPDZ256ri, + 16421 => Opcode::VPERMPDZ256rik, + 16422 => Opcode::VPERMPDZ256rikz, + 16423 => Opcode::VPERMPDZ256rm, + 16424 => Opcode::VPERMPDZ256rmb, + 16425 => Opcode::VPERMPDZ256rmbk, + 16426 => Opcode::VPERMPDZ256rmbkz, + 16427 => Opcode::VPERMPDZ256rmk, + 16428 => Opcode::VPERMPDZ256rmkz, + 16429 => Opcode::VPERMPDZ256rr, + 16430 => Opcode::VPERMPDZ256rrk, + 16431 => Opcode::VPERMPDZ256rrkz, + 16432 => Opcode::VPERMPDZmbi, + 16433 => Opcode::VPERMPDZmbik, + 16434 => Opcode::VPERMPDZmbikz, + 16435 => Opcode::VPERMPDZmi, + 16436 => Opcode::VPERMPDZmik, + 16437 => Opcode::VPERMPDZmikz, + 16438 => Opcode::VPERMPDZri, + 16439 => Opcode::VPERMPDZrik, + 16440 => Opcode::VPERMPDZrikz, + 16441 => Opcode::VPERMPDZrm, + 16442 => Opcode::VPERMPDZrmb, + 16443 => Opcode::VPERMPDZrmbk, + 16444 => Opcode::VPERMPDZrmbkz, + 16445 => Opcode::VPERMPDZrmk, + 16446 => Opcode::VPERMPDZrmkz, + 16447 => Opcode::VPERMPDZrr, + 16448 => Opcode::VPERMPDZrrk, + 16449 => Opcode::VPERMPDZrrkz, + 16450 => Opcode::VPERMPSYrm, + 16451 => Opcode::VPERMPSYrr, + 16452 => Opcode::VPERMPSZ256rm, + 16453 => Opcode::VPERMPSZ256rmb, + 16454 => Opcode::VPERMPSZ256rmbk, + 16455 => Opcode::VPERMPSZ256rmbkz, + 16456 => Opcode::VPERMPSZ256rmk, + 16457 => Opcode::VPERMPSZ256rmkz, + 16458 => Opcode::VPERMPSZ256rr, + 16459 => Opcode::VPERMPSZ256rrk, + 16460 => Opcode::VPERMPSZ256rrkz, + 16461 => Opcode::VPERMPSZrm, + 16462 => Opcode::VPERMPSZrmb, + 16463 => Opcode::VPERMPSZrmbk, + 16464 => Opcode::VPERMPSZrmbkz, + 16465 => Opcode::VPERMPSZrmk, + 16466 => Opcode::VPERMPSZrmkz, + 16467 => Opcode::VPERMPSZrr, + 16468 => Opcode::VPERMPSZrrk, + 16469 => Opcode::VPERMPSZrrkz, + 16470 => Opcode::VPERMQYmi, + 16471 => Opcode::VPERMQYri, + 16472 => Opcode::VPERMQZ256mbi, + 16473 => Opcode::VPERMQZ256mbik, + 16474 => Opcode::VPERMQZ256mbikz, + 16475 => Opcode::VPERMQZ256mi, + 16476 => Opcode::VPERMQZ256mik, + 16477 => Opcode::VPERMQZ256mikz, + 16478 => Opcode::VPERMQZ256ri, + 16479 => Opcode::VPERMQZ256rik, + 16480 => Opcode::VPERMQZ256rikz, + 16481 => Opcode::VPERMQZ256rm, + 16482 => Opcode::VPERMQZ256rmb, + 16483 => Opcode::VPERMQZ256rmbk, + 16484 => Opcode::VPERMQZ256rmbkz, + 16485 => Opcode::VPERMQZ256rmk, + 16486 => Opcode::VPERMQZ256rmkz, + 16487 => Opcode::VPERMQZ256rr, + 16488 => Opcode::VPERMQZ256rrk, + 16489 => Opcode::VPERMQZ256rrkz, + 16490 => Opcode::VPERMQZmbi, + 16491 => Opcode::VPERMQZmbik, + 16492 => Opcode::VPERMQZmbikz, + 16493 => Opcode::VPERMQZmi, + 16494 => Opcode::VPERMQZmik, + 16495 => Opcode::VPERMQZmikz, + 16496 => Opcode::VPERMQZri, + 16497 => Opcode::VPERMQZrik, + 16498 => Opcode::VPERMQZrikz, + 16499 => Opcode::VPERMQZrm, + 16500 => Opcode::VPERMQZrmb, + 16501 => Opcode::VPERMQZrmbk, + 16502 => Opcode::VPERMQZrmbkz, + 16503 => Opcode::VPERMQZrmk, + 16504 => Opcode::VPERMQZrmkz, + 16505 => Opcode::VPERMQZrr, + 16506 => Opcode::VPERMQZrrk, + 16507 => Opcode::VPERMQZrrkz, + 16508 => Opcode::VPERMT2BZ128rm, + 16509 => Opcode::VPERMT2BZ128rmk, + 16510 => Opcode::VPERMT2BZ128rmkz, + 16511 => Opcode::VPERMT2BZ128rr, + 16512 => Opcode::VPERMT2BZ128rrk, + 16513 => Opcode::VPERMT2BZ128rrkz, + 16514 => Opcode::VPERMT2BZ256rm, + 16515 => Opcode::VPERMT2BZ256rmk, + 16516 => Opcode::VPERMT2BZ256rmkz, + 16517 => Opcode::VPERMT2BZ256rr, + 16518 => Opcode::VPERMT2BZ256rrk, + 16519 => Opcode::VPERMT2BZ256rrkz, + 16520 => Opcode::VPERMT2BZrm, + 16521 => Opcode::VPERMT2BZrmk, + 16522 => Opcode::VPERMT2BZrmkz, + 16523 => Opcode::VPERMT2BZrr, + 16524 => Opcode::VPERMT2BZrrk, + 16525 => Opcode::VPERMT2BZrrkz, + 16526 => Opcode::VPERMT2DZ128rm, + 16527 => Opcode::VPERMT2DZ128rmb, + 16528 => Opcode::VPERMT2DZ128rmbk, + 16529 => Opcode::VPERMT2DZ128rmbkz, + 16530 => Opcode::VPERMT2DZ128rmk, + 16531 => Opcode::VPERMT2DZ128rmkz, + 16532 => Opcode::VPERMT2DZ128rr, + 16533 => Opcode::VPERMT2DZ128rrk, + 16534 => Opcode::VPERMT2DZ128rrkz, + 16535 => Opcode::VPERMT2DZ256rm, + 16536 => Opcode::VPERMT2DZ256rmb, + 16537 => Opcode::VPERMT2DZ256rmbk, + 16538 => Opcode::VPERMT2DZ256rmbkz, + 16539 => Opcode::VPERMT2DZ256rmk, + 16540 => Opcode::VPERMT2DZ256rmkz, + 16541 => Opcode::VPERMT2DZ256rr, + 16542 => Opcode::VPERMT2DZ256rrk, + 16543 => Opcode::VPERMT2DZ256rrkz, + 16544 => Opcode::VPERMT2DZrm, + 16545 => Opcode::VPERMT2DZrmb, + 16546 => Opcode::VPERMT2DZrmbk, + 16547 => Opcode::VPERMT2DZrmbkz, + 16548 => Opcode::VPERMT2DZrmk, + 16549 => Opcode::VPERMT2DZrmkz, + 16550 => Opcode::VPERMT2DZrr, + 16551 => Opcode::VPERMT2DZrrk, + 16552 => Opcode::VPERMT2DZrrkz, + 16553 => Opcode::VPERMT2PDZ128rm, + 16554 => Opcode::VPERMT2PDZ128rmb, + 16555 => Opcode::VPERMT2PDZ128rmbk, + 16556 => Opcode::VPERMT2PDZ128rmbkz, + 16557 => Opcode::VPERMT2PDZ128rmk, + 16558 => Opcode::VPERMT2PDZ128rmkz, + 16559 => Opcode::VPERMT2PDZ128rr, + 16560 => Opcode::VPERMT2PDZ128rrk, + 16561 => Opcode::VPERMT2PDZ128rrkz, + 16562 => Opcode::VPERMT2PDZ256rm, + 16563 => Opcode::VPERMT2PDZ256rmb, + 16564 => Opcode::VPERMT2PDZ256rmbk, + 16565 => Opcode::VPERMT2PDZ256rmbkz, + 16566 => Opcode::VPERMT2PDZ256rmk, + 16567 => Opcode::VPERMT2PDZ256rmkz, + 16568 => Opcode::VPERMT2PDZ256rr, + 16569 => Opcode::VPERMT2PDZ256rrk, + 16570 => Opcode::VPERMT2PDZ256rrkz, + 16571 => Opcode::VPERMT2PDZrm, + 16572 => Opcode::VPERMT2PDZrmb, + 16573 => Opcode::VPERMT2PDZrmbk, + 16574 => Opcode::VPERMT2PDZrmbkz, + 16575 => Opcode::VPERMT2PDZrmk, + 16576 => Opcode::VPERMT2PDZrmkz, + 16577 => Opcode::VPERMT2PDZrr, + 16578 => Opcode::VPERMT2PDZrrk, + 16579 => Opcode::VPERMT2PDZrrkz, + 16580 => Opcode::VPERMT2PSZ128rm, + 16581 => Opcode::VPERMT2PSZ128rmb, + 16582 => Opcode::VPERMT2PSZ128rmbk, + 16583 => Opcode::VPERMT2PSZ128rmbkz, + 16584 => Opcode::VPERMT2PSZ128rmk, + 16585 => Opcode::VPERMT2PSZ128rmkz, + 16586 => Opcode::VPERMT2PSZ128rr, + 16587 => Opcode::VPERMT2PSZ128rrk, + 16588 => Opcode::VPERMT2PSZ128rrkz, + 16589 => Opcode::VPERMT2PSZ256rm, + 16590 => Opcode::VPERMT2PSZ256rmb, + 16591 => Opcode::VPERMT2PSZ256rmbk, + 16592 => Opcode::VPERMT2PSZ256rmbkz, + 16593 => Opcode::VPERMT2PSZ256rmk, + 16594 => Opcode::VPERMT2PSZ256rmkz, + 16595 => Opcode::VPERMT2PSZ256rr, + 16596 => Opcode::VPERMT2PSZ256rrk, + 16597 => Opcode::VPERMT2PSZ256rrkz, + 16598 => Opcode::VPERMT2PSZrm, + 16599 => Opcode::VPERMT2PSZrmb, + 16600 => Opcode::VPERMT2PSZrmbk, + 16601 => Opcode::VPERMT2PSZrmbkz, + 16602 => Opcode::VPERMT2PSZrmk, + 16603 => Opcode::VPERMT2PSZrmkz, + 16604 => Opcode::VPERMT2PSZrr, + 16605 => Opcode::VPERMT2PSZrrk, + 16606 => Opcode::VPERMT2PSZrrkz, + 16607 => Opcode::VPERMT2QZ128rm, + 16608 => Opcode::VPERMT2QZ128rmb, + 16609 => Opcode::VPERMT2QZ128rmbk, + 16610 => Opcode::VPERMT2QZ128rmbkz, + 16611 => Opcode::VPERMT2QZ128rmk, + 16612 => Opcode::VPERMT2QZ128rmkz, + 16613 => Opcode::VPERMT2QZ128rr, + 16614 => Opcode::VPERMT2QZ128rrk, + 16615 => Opcode::VPERMT2QZ128rrkz, + 16616 => Opcode::VPERMT2QZ256rm, + 16617 => Opcode::VPERMT2QZ256rmb, + 16618 => Opcode::VPERMT2QZ256rmbk, + 16619 => Opcode::VPERMT2QZ256rmbkz, + 16620 => Opcode::VPERMT2QZ256rmk, + 16621 => Opcode::VPERMT2QZ256rmkz, + 16622 => Opcode::VPERMT2QZ256rr, + 16623 => Opcode::VPERMT2QZ256rrk, + 16624 => Opcode::VPERMT2QZ256rrkz, + 16625 => Opcode::VPERMT2QZrm, + 16626 => Opcode::VPERMT2QZrmb, + 16627 => Opcode::VPERMT2QZrmbk, + 16628 => Opcode::VPERMT2QZrmbkz, + 16629 => Opcode::VPERMT2QZrmk, + 16630 => Opcode::VPERMT2QZrmkz, + 16631 => Opcode::VPERMT2QZrr, + 16632 => Opcode::VPERMT2QZrrk, + 16633 => Opcode::VPERMT2QZrrkz, + 16634 => Opcode::VPERMT2WZ128rm, + 16635 => Opcode::VPERMT2WZ128rmk, + 16636 => Opcode::VPERMT2WZ128rmkz, + 16637 => Opcode::VPERMT2WZ128rr, + 16638 => Opcode::VPERMT2WZ128rrk, + 16639 => Opcode::VPERMT2WZ128rrkz, + 16640 => Opcode::VPERMT2WZ256rm, + 16641 => Opcode::VPERMT2WZ256rmk, + 16642 => Opcode::VPERMT2WZ256rmkz, + 16643 => Opcode::VPERMT2WZ256rr, + 16644 => Opcode::VPERMT2WZ256rrk, + 16645 => Opcode::VPERMT2WZ256rrkz, + 16646 => Opcode::VPERMT2WZrm, + 16647 => Opcode::VPERMT2WZrmk, + 16648 => Opcode::VPERMT2WZrmkz, + 16649 => Opcode::VPERMT2WZrr, + 16650 => Opcode::VPERMT2WZrrk, + 16651 => Opcode::VPERMT2WZrrkz, + 16652 => Opcode::VPERMWZ128rm, + 16653 => Opcode::VPERMWZ128rmk, + 16654 => Opcode::VPERMWZ128rmkz, + 16655 => Opcode::VPERMWZ128rr, + 16656 => Opcode::VPERMWZ128rrk, + 16657 => Opcode::VPERMWZ128rrkz, + 16658 => Opcode::VPERMWZ256rm, + 16659 => Opcode::VPERMWZ256rmk, + 16660 => Opcode::VPERMWZ256rmkz, + 16661 => Opcode::VPERMWZ256rr, + 16662 => Opcode::VPERMWZ256rrk, + 16663 => Opcode::VPERMWZ256rrkz, + 16664 => Opcode::VPERMWZrm, + 16665 => Opcode::VPERMWZrmk, + 16666 => Opcode::VPERMWZrmkz, + 16667 => Opcode::VPERMWZrr, + 16668 => Opcode::VPERMWZrrk, + 16669 => Opcode::VPERMWZrrkz, + 16670 => Opcode::VPEXPANDBZ128rm, + 16671 => Opcode::VPEXPANDBZ128rmk, + 16672 => Opcode::VPEXPANDBZ128rmkz, + 16673 => Opcode::VPEXPANDBZ128rr, + 16674 => Opcode::VPEXPANDBZ128rrk, + 16675 => Opcode::VPEXPANDBZ128rrkz, + 16676 => Opcode::VPEXPANDBZ256rm, + 16677 => Opcode::VPEXPANDBZ256rmk, + 16678 => Opcode::VPEXPANDBZ256rmkz, + 16679 => Opcode::VPEXPANDBZ256rr, + 16680 => Opcode::VPEXPANDBZ256rrk, + 16681 => Opcode::VPEXPANDBZ256rrkz, + 16682 => Opcode::VPEXPANDBZrm, + 16683 => Opcode::VPEXPANDBZrmk, + 16684 => Opcode::VPEXPANDBZrmkz, + 16685 => Opcode::VPEXPANDBZrr, + 16686 => Opcode::VPEXPANDBZrrk, + 16687 => Opcode::VPEXPANDBZrrkz, + 16688 => Opcode::VPEXPANDDZ128rm, + 16689 => Opcode::VPEXPANDDZ128rmk, + 16690 => Opcode::VPEXPANDDZ128rmkz, + 16691 => Opcode::VPEXPANDDZ128rr, + 16692 => Opcode::VPEXPANDDZ128rrk, + 16693 => Opcode::VPEXPANDDZ128rrkz, + 16694 => Opcode::VPEXPANDDZ256rm, + 16695 => Opcode::VPEXPANDDZ256rmk, + 16696 => Opcode::VPEXPANDDZ256rmkz, + 16697 => Opcode::VPEXPANDDZ256rr, + 16698 => Opcode::VPEXPANDDZ256rrk, + 16699 => Opcode::VPEXPANDDZ256rrkz, + 16700 => Opcode::VPEXPANDDZrm, + 16701 => Opcode::VPEXPANDDZrmk, + 16702 => Opcode::VPEXPANDDZrmkz, + 16703 => Opcode::VPEXPANDDZrr, + 16704 => Opcode::VPEXPANDDZrrk, + 16705 => Opcode::VPEXPANDDZrrkz, + 16706 => Opcode::VPEXPANDQZ128rm, + 16707 => Opcode::VPEXPANDQZ128rmk, + 16708 => Opcode::VPEXPANDQZ128rmkz, + 16709 => Opcode::VPEXPANDQZ128rr, + 16710 => Opcode::VPEXPANDQZ128rrk, + 16711 => Opcode::VPEXPANDQZ128rrkz, + 16712 => Opcode::VPEXPANDQZ256rm, + 16713 => Opcode::VPEXPANDQZ256rmk, + 16714 => Opcode::VPEXPANDQZ256rmkz, + 16715 => Opcode::VPEXPANDQZ256rr, + 16716 => Opcode::VPEXPANDQZ256rrk, + 16717 => Opcode::VPEXPANDQZ256rrkz, + 16718 => Opcode::VPEXPANDQZrm, + 16719 => Opcode::VPEXPANDQZrmk, + 16720 => Opcode::VPEXPANDQZrmkz, + 16721 => Opcode::VPEXPANDQZrr, + 16722 => Opcode::VPEXPANDQZrrk, + 16723 => Opcode::VPEXPANDQZrrkz, + 16724 => Opcode::VPEXPANDWZ128rm, + 16725 => Opcode::VPEXPANDWZ128rmk, + 16726 => Opcode::VPEXPANDWZ128rmkz, + 16727 => Opcode::VPEXPANDWZ128rr, + 16728 => Opcode::VPEXPANDWZ128rrk, + 16729 => Opcode::VPEXPANDWZ128rrkz, + 16730 => Opcode::VPEXPANDWZ256rm, + 16731 => Opcode::VPEXPANDWZ256rmk, + 16732 => Opcode::VPEXPANDWZ256rmkz, + 16733 => Opcode::VPEXPANDWZ256rr, + 16734 => Opcode::VPEXPANDWZ256rrk, + 16735 => Opcode::VPEXPANDWZ256rrkz, + 16736 => Opcode::VPEXPANDWZrm, + 16737 => Opcode::VPEXPANDWZrmk, + 16738 => Opcode::VPEXPANDWZrmkz, + 16739 => Opcode::VPEXPANDWZrr, + 16740 => Opcode::VPEXPANDWZrrk, + 16741 => Opcode::VPEXPANDWZrrkz, + 16742 => Opcode::VPEXTRBZmri, + 16743 => Opcode::VPEXTRBZrri, + 16744 => Opcode::VPEXTRBmri, + 16745 => Opcode::VPEXTRBrri, + 16746 => Opcode::VPEXTRDZmri, + 16747 => Opcode::VPEXTRDZrri, + 16748 => Opcode::VPEXTRDmri, + 16749 => Opcode::VPEXTRDrri, + 16750 => Opcode::VPEXTRQZmri, + 16751 => Opcode::VPEXTRQZrri, + 16752 => Opcode::VPEXTRQmri, + 16753 => Opcode::VPEXTRQrri, + 16754 => Opcode::VPEXTRWZmri, + 16755 => Opcode::VPEXTRWZrri, + 16756 => Opcode::VPEXTRWZrri_REV, + 16757 => Opcode::VPEXTRWmri, + 16758 => Opcode::VPEXTRWrri, + 16759 => Opcode::VPEXTRWrri_REV, + 16760 => Opcode::VPGATHERDDYrm, + 16761 => Opcode::VPGATHERDDZ128rm, + 16762 => Opcode::VPGATHERDDZ256rm, + 16763 => Opcode::VPGATHERDDZrm, + 16764 => Opcode::VPGATHERDDrm, + 16765 => Opcode::VPGATHERDQYrm, + 16766 => Opcode::VPGATHERDQZ128rm, + 16767 => Opcode::VPGATHERDQZ256rm, + 16768 => Opcode::VPGATHERDQZrm, + 16769 => Opcode::VPGATHERDQrm, + 16770 => Opcode::VPGATHERQDYrm, + 16771 => Opcode::VPGATHERQDZ128rm, + 16772 => Opcode::VPGATHERQDZ256rm, + 16773 => Opcode::VPGATHERQDZrm, + 16774 => Opcode::VPGATHERQDrm, + 16775 => Opcode::VPGATHERQQYrm, + 16776 => Opcode::VPGATHERQQZ128rm, + 16777 => Opcode::VPGATHERQQZ256rm, + 16778 => Opcode::VPGATHERQQZrm, + 16779 => Opcode::VPGATHERQQrm, + 16780 => Opcode::VPHADDBDrm, + 16781 => Opcode::VPHADDBDrr, + 16782 => Opcode::VPHADDBQrm, + 16783 => Opcode::VPHADDBQrr, + 16784 => Opcode::VPHADDBWrm, + 16785 => Opcode::VPHADDBWrr, + 16786 => Opcode::VPHADDDQrm, + 16787 => Opcode::VPHADDDQrr, + 16788 => Opcode::VPHADDDYrm, + 16789 => Opcode::VPHADDDYrr, + 16790 => Opcode::VPHADDDrm, + 16791 => Opcode::VPHADDDrr, + 16792 => Opcode::VPHADDSWYrm, + 16793 => Opcode::VPHADDSWYrr, + 16794 => Opcode::VPHADDSWrm, + 16795 => Opcode::VPHADDSWrr, + 16796 => Opcode::VPHADDUBDrm, + 16797 => Opcode::VPHADDUBDrr, + 16798 => Opcode::VPHADDUBQrm, + 16799 => Opcode::VPHADDUBQrr, + 16800 => Opcode::VPHADDUBWrm, + 16801 => Opcode::VPHADDUBWrr, + 16802 => Opcode::VPHADDUDQrm, + 16803 => Opcode::VPHADDUDQrr, + 16804 => Opcode::VPHADDUWDrm, + 16805 => Opcode::VPHADDUWDrr, + 16806 => Opcode::VPHADDUWQrm, + 16807 => Opcode::VPHADDUWQrr, + 16808 => Opcode::VPHADDWDrm, + 16809 => Opcode::VPHADDWDrr, + 16810 => Opcode::VPHADDWQrm, + 16811 => Opcode::VPHADDWQrr, + 16812 => Opcode::VPHADDWYrm, + 16813 => Opcode::VPHADDWYrr, + 16814 => Opcode::VPHADDWrm, + 16815 => Opcode::VPHADDWrr, + 16816 => Opcode::VPHMINPOSUWrm, + 16817 => Opcode::VPHMINPOSUWrr, + 16818 => Opcode::VPHSUBBWrm, + 16819 => Opcode::VPHSUBBWrr, + 16820 => Opcode::VPHSUBDQrm, + 16821 => Opcode::VPHSUBDQrr, + 16822 => Opcode::VPHSUBDYrm, + 16823 => Opcode::VPHSUBDYrr, + 16824 => Opcode::VPHSUBDrm, + 16825 => Opcode::VPHSUBDrr, + 16826 => Opcode::VPHSUBSWYrm, + 16827 => Opcode::VPHSUBSWYrr, + 16828 => Opcode::VPHSUBSWrm, + 16829 => Opcode::VPHSUBSWrr, + 16830 => Opcode::VPHSUBWDrm, + 16831 => Opcode::VPHSUBWDrr, + 16832 => Opcode::VPHSUBWYrm, + 16833 => Opcode::VPHSUBWYrr, + 16834 => Opcode::VPHSUBWrm, + 16835 => Opcode::VPHSUBWrr, + 16836 => Opcode::VPINSRBZrmi, + 16837 => Opcode::VPINSRBZrri, + 16838 => Opcode::VPINSRBrmi, + 16839 => Opcode::VPINSRBrri, + 16840 => Opcode::VPINSRDZrmi, + 16841 => Opcode::VPINSRDZrri, + 16842 => Opcode::VPINSRDrmi, + 16843 => Opcode::VPINSRDrri, + 16844 => Opcode::VPINSRQZrmi, + 16845 => Opcode::VPINSRQZrri, + 16846 => Opcode::VPINSRQrmi, + 16847 => Opcode::VPINSRQrri, + 16848 => Opcode::VPINSRWZrmi, + 16849 => Opcode::VPINSRWZrri, + 16850 => Opcode::VPINSRWrmi, + 16851 => Opcode::VPINSRWrri, + 16852 => Opcode::VPLZCNTDZ128rm, + 16853 => Opcode::VPLZCNTDZ128rmb, + 16854 => Opcode::VPLZCNTDZ128rmbk, + 16855 => Opcode::VPLZCNTDZ128rmbkz, + 16856 => Opcode::VPLZCNTDZ128rmk, + 16857 => Opcode::VPLZCNTDZ128rmkz, + 16858 => Opcode::VPLZCNTDZ128rr, + 16859 => Opcode::VPLZCNTDZ128rrk, + 16860 => Opcode::VPLZCNTDZ128rrkz, + 16861 => Opcode::VPLZCNTDZ256rm, + 16862 => Opcode::VPLZCNTDZ256rmb, + 16863 => Opcode::VPLZCNTDZ256rmbk, + 16864 => Opcode::VPLZCNTDZ256rmbkz, + 16865 => Opcode::VPLZCNTDZ256rmk, + 16866 => Opcode::VPLZCNTDZ256rmkz, + 16867 => Opcode::VPLZCNTDZ256rr, + 16868 => Opcode::VPLZCNTDZ256rrk, + 16869 => Opcode::VPLZCNTDZ256rrkz, + 16870 => Opcode::VPLZCNTDZrm, + 16871 => Opcode::VPLZCNTDZrmb, + 16872 => Opcode::VPLZCNTDZrmbk, + 16873 => Opcode::VPLZCNTDZrmbkz, + 16874 => Opcode::VPLZCNTDZrmk, + 16875 => Opcode::VPLZCNTDZrmkz, + 16876 => Opcode::VPLZCNTDZrr, + 16877 => Opcode::VPLZCNTDZrrk, + 16878 => Opcode::VPLZCNTDZrrkz, + 16879 => Opcode::VPLZCNTQZ128rm, + 16880 => Opcode::VPLZCNTQZ128rmb, + 16881 => Opcode::VPLZCNTQZ128rmbk, + 16882 => Opcode::VPLZCNTQZ128rmbkz, + 16883 => Opcode::VPLZCNTQZ128rmk, + 16884 => Opcode::VPLZCNTQZ128rmkz, + 16885 => Opcode::VPLZCNTQZ128rr, + 16886 => Opcode::VPLZCNTQZ128rrk, + 16887 => Opcode::VPLZCNTQZ128rrkz, + 16888 => Opcode::VPLZCNTQZ256rm, + 16889 => Opcode::VPLZCNTQZ256rmb, + 16890 => Opcode::VPLZCNTQZ256rmbk, + 16891 => Opcode::VPLZCNTQZ256rmbkz, + 16892 => Opcode::VPLZCNTQZ256rmk, + 16893 => Opcode::VPLZCNTQZ256rmkz, + 16894 => Opcode::VPLZCNTQZ256rr, + 16895 => Opcode::VPLZCNTQZ256rrk, + 16896 => Opcode::VPLZCNTQZ256rrkz, + 16897 => Opcode::VPLZCNTQZrm, + 16898 => Opcode::VPLZCNTQZrmb, + 16899 => Opcode::VPLZCNTQZrmbk, + 16900 => Opcode::VPLZCNTQZrmbkz, + 16901 => Opcode::VPLZCNTQZrmk, + 16902 => Opcode::VPLZCNTQZrmkz, + 16903 => Opcode::VPLZCNTQZrr, + 16904 => Opcode::VPLZCNTQZrrk, + 16905 => Opcode::VPLZCNTQZrrkz, + 16906 => Opcode::VPMACSDDrm, + 16907 => Opcode::VPMACSDDrr, + 16908 => Opcode::VPMACSDQHrm, + 16909 => Opcode::VPMACSDQHrr, + 16910 => Opcode::VPMACSDQLrm, + 16911 => Opcode::VPMACSDQLrr, + 16912 => Opcode::VPMACSSDDrm, + 16913 => Opcode::VPMACSSDDrr, + 16914 => Opcode::VPMACSSDQHrm, + 16915 => Opcode::VPMACSSDQHrr, + 16916 => Opcode::VPMACSSDQLrm, + 16917 => Opcode::VPMACSSDQLrr, + 16918 => Opcode::VPMACSSWDrm, + 16919 => Opcode::VPMACSSWDrr, + 16920 => Opcode::VPMACSSWWrm, + 16921 => Opcode::VPMACSSWWrr, + 16922 => Opcode::VPMACSWDrm, + 16923 => Opcode::VPMACSWDrr, + 16924 => Opcode::VPMACSWWrm, + 16925 => Opcode::VPMACSWWrr, + 16926 => Opcode::VPMADCSSWDrm, + 16927 => Opcode::VPMADCSSWDrr, + 16928 => Opcode::VPMADCSWDrm, + 16929 => Opcode::VPMADCSWDrr, + 16930 => Opcode::VPMADD52HUQYrm, + 16931 => Opcode::VPMADD52HUQYrr, + 16932 => Opcode::VPMADD52HUQZ128m, + 16933 => Opcode::VPMADD52HUQZ128mb, + 16934 => Opcode::VPMADD52HUQZ128mbk, + 16935 => Opcode::VPMADD52HUQZ128mbkz, + 16936 => Opcode::VPMADD52HUQZ128mk, + 16937 => Opcode::VPMADD52HUQZ128mkz, + 16938 => Opcode::VPMADD52HUQZ128r, + 16939 => Opcode::VPMADD52HUQZ128rk, + 16940 => Opcode::VPMADD52HUQZ128rkz, + 16941 => Opcode::VPMADD52HUQZ256m, + 16942 => Opcode::VPMADD52HUQZ256mb, + 16943 => Opcode::VPMADD52HUQZ256mbk, + 16944 => Opcode::VPMADD52HUQZ256mbkz, + 16945 => Opcode::VPMADD52HUQZ256mk, + 16946 => Opcode::VPMADD52HUQZ256mkz, + 16947 => Opcode::VPMADD52HUQZ256r, + 16948 => Opcode::VPMADD52HUQZ256rk, + 16949 => Opcode::VPMADD52HUQZ256rkz, + 16950 => Opcode::VPMADD52HUQZm, + 16951 => Opcode::VPMADD52HUQZmb, + 16952 => Opcode::VPMADD52HUQZmbk, + 16953 => Opcode::VPMADD52HUQZmbkz, + 16954 => Opcode::VPMADD52HUQZmk, + 16955 => Opcode::VPMADD52HUQZmkz, + 16956 => Opcode::VPMADD52HUQZr, + 16957 => Opcode::VPMADD52HUQZrk, + 16958 => Opcode::VPMADD52HUQZrkz, + 16959 => Opcode::VPMADD52HUQrm, + 16960 => Opcode::VPMADD52HUQrr, + 16961 => Opcode::VPMADD52LUQYrm, + 16962 => Opcode::VPMADD52LUQYrr, + 16963 => Opcode::VPMADD52LUQZ128m, + 16964 => Opcode::VPMADD52LUQZ128mb, + 16965 => Opcode::VPMADD52LUQZ128mbk, + 16966 => Opcode::VPMADD52LUQZ128mbkz, + 16967 => Opcode::VPMADD52LUQZ128mk, + 16968 => Opcode::VPMADD52LUQZ128mkz, + 16969 => Opcode::VPMADD52LUQZ128r, + 16970 => Opcode::VPMADD52LUQZ128rk, + 16971 => Opcode::VPMADD52LUQZ128rkz, + 16972 => Opcode::VPMADD52LUQZ256m, + 16973 => Opcode::VPMADD52LUQZ256mb, + 16974 => Opcode::VPMADD52LUQZ256mbk, + 16975 => Opcode::VPMADD52LUQZ256mbkz, + 16976 => Opcode::VPMADD52LUQZ256mk, + 16977 => Opcode::VPMADD52LUQZ256mkz, + 16978 => Opcode::VPMADD52LUQZ256r, + 16979 => Opcode::VPMADD52LUQZ256rk, + 16980 => Opcode::VPMADD52LUQZ256rkz, + 16981 => Opcode::VPMADD52LUQZm, + 16982 => Opcode::VPMADD52LUQZmb, + 16983 => Opcode::VPMADD52LUQZmbk, + 16984 => Opcode::VPMADD52LUQZmbkz, + 16985 => Opcode::VPMADD52LUQZmk, + 16986 => Opcode::VPMADD52LUQZmkz, + 16987 => Opcode::VPMADD52LUQZr, + 16988 => Opcode::VPMADD52LUQZrk, + 16989 => Opcode::VPMADD52LUQZrkz, + 16990 => Opcode::VPMADD52LUQrm, + 16991 => Opcode::VPMADD52LUQrr, + 16992 => Opcode::VPMADDUBSWYrm, + 16993 => Opcode::VPMADDUBSWYrr, + 16994 => Opcode::VPMADDUBSWZ128rm, + 16995 => Opcode::VPMADDUBSWZ128rmk, + 16996 => Opcode::VPMADDUBSWZ128rmkz, + 16997 => Opcode::VPMADDUBSWZ128rr, + 16998 => Opcode::VPMADDUBSWZ128rrk, + 16999 => Opcode::VPMADDUBSWZ128rrkz, + 17000 => Opcode::VPMADDUBSWZ256rm, + 17001 => Opcode::VPMADDUBSWZ256rmk, + 17002 => Opcode::VPMADDUBSWZ256rmkz, + 17003 => Opcode::VPMADDUBSWZ256rr, + 17004 => Opcode::VPMADDUBSWZ256rrk, + 17005 => Opcode::VPMADDUBSWZ256rrkz, + 17006 => Opcode::VPMADDUBSWZrm, + 17007 => Opcode::VPMADDUBSWZrmk, + 17008 => Opcode::VPMADDUBSWZrmkz, + 17009 => Opcode::VPMADDUBSWZrr, + 17010 => Opcode::VPMADDUBSWZrrk, + 17011 => Opcode::VPMADDUBSWZrrkz, + 17012 => Opcode::VPMADDUBSWrm, + 17013 => Opcode::VPMADDUBSWrr, + 17014 => Opcode::VPMADDWDYrm, + 17015 => Opcode::VPMADDWDYrr, + 17016 => Opcode::VPMADDWDZ128rm, + 17017 => Opcode::VPMADDWDZ128rmk, + 17018 => Opcode::VPMADDWDZ128rmkz, + 17019 => Opcode::VPMADDWDZ128rr, + 17020 => Opcode::VPMADDWDZ128rrk, + 17021 => Opcode::VPMADDWDZ128rrkz, + 17022 => Opcode::VPMADDWDZ256rm, + 17023 => Opcode::VPMADDWDZ256rmk, + 17024 => Opcode::VPMADDWDZ256rmkz, + 17025 => Opcode::VPMADDWDZ256rr, + 17026 => Opcode::VPMADDWDZ256rrk, + 17027 => Opcode::VPMADDWDZ256rrkz, + 17028 => Opcode::VPMADDWDZrm, + 17029 => Opcode::VPMADDWDZrmk, + 17030 => Opcode::VPMADDWDZrmkz, + 17031 => Opcode::VPMADDWDZrr, + 17032 => Opcode::VPMADDWDZrrk, + 17033 => Opcode::VPMADDWDZrrkz, + 17034 => Opcode::VPMADDWDrm, + 17035 => Opcode::VPMADDWDrr, + 17036 => Opcode::VPMASKMOVDYmr, + 17037 => Opcode::VPMASKMOVDYrm, + 17038 => Opcode::VPMASKMOVDmr, + 17039 => Opcode::VPMASKMOVDrm, + 17040 => Opcode::VPMASKMOVQYmr, + 17041 => Opcode::VPMASKMOVQYrm, + 17042 => Opcode::VPMASKMOVQmr, + 17043 => Opcode::VPMASKMOVQrm, + 17044 => Opcode::VPMAXSBYrm, + 17045 => Opcode::VPMAXSBYrr, + 17046 => Opcode::VPMAXSBZ128rm, + 17047 => Opcode::VPMAXSBZ128rmk, + 17048 => Opcode::VPMAXSBZ128rmkz, + 17049 => Opcode::VPMAXSBZ128rr, + 17050 => Opcode::VPMAXSBZ128rrk, + 17051 => Opcode::VPMAXSBZ128rrkz, + 17052 => Opcode::VPMAXSBZ256rm, + 17053 => Opcode::VPMAXSBZ256rmk, + 17054 => Opcode::VPMAXSBZ256rmkz, + 17055 => Opcode::VPMAXSBZ256rr, + 17056 => Opcode::VPMAXSBZ256rrk, + 17057 => Opcode::VPMAXSBZ256rrkz, + 17058 => Opcode::VPMAXSBZrm, + 17059 => Opcode::VPMAXSBZrmk, + 17060 => Opcode::VPMAXSBZrmkz, + 17061 => Opcode::VPMAXSBZrr, + 17062 => Opcode::VPMAXSBZrrk, + 17063 => Opcode::VPMAXSBZrrkz, + 17064 => Opcode::VPMAXSBrm, + 17065 => Opcode::VPMAXSBrr, + 17066 => Opcode::VPMAXSDYrm, + 17067 => Opcode::VPMAXSDYrr, + 17068 => Opcode::VPMAXSDZ128rm, + 17069 => Opcode::VPMAXSDZ128rmb, + 17070 => Opcode::VPMAXSDZ128rmbk, + 17071 => Opcode::VPMAXSDZ128rmbkz, + 17072 => Opcode::VPMAXSDZ128rmk, + 17073 => Opcode::VPMAXSDZ128rmkz, + 17074 => Opcode::VPMAXSDZ128rr, + 17075 => Opcode::VPMAXSDZ128rrk, + 17076 => Opcode::VPMAXSDZ128rrkz, + 17077 => Opcode::VPMAXSDZ256rm, + 17078 => Opcode::VPMAXSDZ256rmb, + 17079 => Opcode::VPMAXSDZ256rmbk, + 17080 => Opcode::VPMAXSDZ256rmbkz, + 17081 => Opcode::VPMAXSDZ256rmk, + 17082 => Opcode::VPMAXSDZ256rmkz, + 17083 => Opcode::VPMAXSDZ256rr, + 17084 => Opcode::VPMAXSDZ256rrk, + 17085 => Opcode::VPMAXSDZ256rrkz, + 17086 => Opcode::VPMAXSDZrm, + 17087 => Opcode::VPMAXSDZrmb, + 17088 => Opcode::VPMAXSDZrmbk, + 17089 => Opcode::VPMAXSDZrmbkz, + 17090 => Opcode::VPMAXSDZrmk, + 17091 => Opcode::VPMAXSDZrmkz, + 17092 => Opcode::VPMAXSDZrr, + 17093 => Opcode::VPMAXSDZrrk, + 17094 => Opcode::VPMAXSDZrrkz, + 17095 => Opcode::VPMAXSDrm, + 17096 => Opcode::VPMAXSDrr, + 17097 => Opcode::VPMAXSQZ128rm, + 17098 => Opcode::VPMAXSQZ128rmb, + 17099 => Opcode::VPMAXSQZ128rmbk, + 17100 => Opcode::VPMAXSQZ128rmbkz, + 17101 => Opcode::VPMAXSQZ128rmk, + 17102 => Opcode::VPMAXSQZ128rmkz, + 17103 => Opcode::VPMAXSQZ128rr, + 17104 => Opcode::VPMAXSQZ128rrk, + 17105 => Opcode::VPMAXSQZ128rrkz, + 17106 => Opcode::VPMAXSQZ256rm, + 17107 => Opcode::VPMAXSQZ256rmb, + 17108 => Opcode::VPMAXSQZ256rmbk, + 17109 => Opcode::VPMAXSQZ256rmbkz, + 17110 => Opcode::VPMAXSQZ256rmk, + 17111 => Opcode::VPMAXSQZ256rmkz, + 17112 => Opcode::VPMAXSQZ256rr, + 17113 => Opcode::VPMAXSQZ256rrk, + 17114 => Opcode::VPMAXSQZ256rrkz, + 17115 => Opcode::VPMAXSQZrm, + 17116 => Opcode::VPMAXSQZrmb, + 17117 => Opcode::VPMAXSQZrmbk, + 17118 => Opcode::VPMAXSQZrmbkz, + 17119 => Opcode::VPMAXSQZrmk, + 17120 => Opcode::VPMAXSQZrmkz, + 17121 => Opcode::VPMAXSQZrr, + 17122 => Opcode::VPMAXSQZrrk, + 17123 => Opcode::VPMAXSQZrrkz, + 17124 => Opcode::VPMAXSWYrm, + 17125 => Opcode::VPMAXSWYrr, + 17126 => Opcode::VPMAXSWZ128rm, + 17127 => Opcode::VPMAXSWZ128rmk, + 17128 => Opcode::VPMAXSWZ128rmkz, + 17129 => Opcode::VPMAXSWZ128rr, + 17130 => Opcode::VPMAXSWZ128rrk, + 17131 => Opcode::VPMAXSWZ128rrkz, + 17132 => Opcode::VPMAXSWZ256rm, + 17133 => Opcode::VPMAXSWZ256rmk, + 17134 => Opcode::VPMAXSWZ256rmkz, + 17135 => Opcode::VPMAXSWZ256rr, + 17136 => Opcode::VPMAXSWZ256rrk, + 17137 => Opcode::VPMAXSWZ256rrkz, + 17138 => Opcode::VPMAXSWZrm, + 17139 => Opcode::VPMAXSWZrmk, + 17140 => Opcode::VPMAXSWZrmkz, + 17141 => Opcode::VPMAXSWZrr, + 17142 => Opcode::VPMAXSWZrrk, + 17143 => Opcode::VPMAXSWZrrkz, + 17144 => Opcode::VPMAXSWrm, + 17145 => Opcode::VPMAXSWrr, + 17146 => Opcode::VPMAXUBYrm, + 17147 => Opcode::VPMAXUBYrr, + 17148 => Opcode::VPMAXUBZ128rm, + 17149 => Opcode::VPMAXUBZ128rmk, + 17150 => Opcode::VPMAXUBZ128rmkz, + 17151 => Opcode::VPMAXUBZ128rr, + 17152 => Opcode::VPMAXUBZ128rrk, + 17153 => Opcode::VPMAXUBZ128rrkz, + 17154 => Opcode::VPMAXUBZ256rm, + 17155 => Opcode::VPMAXUBZ256rmk, + 17156 => Opcode::VPMAXUBZ256rmkz, + 17157 => Opcode::VPMAXUBZ256rr, + 17158 => Opcode::VPMAXUBZ256rrk, + 17159 => Opcode::VPMAXUBZ256rrkz, + 17160 => Opcode::VPMAXUBZrm, + 17161 => Opcode::VPMAXUBZrmk, + 17162 => Opcode::VPMAXUBZrmkz, + 17163 => Opcode::VPMAXUBZrr, + 17164 => Opcode::VPMAXUBZrrk, + 17165 => Opcode::VPMAXUBZrrkz, + 17166 => Opcode::VPMAXUBrm, + 17167 => Opcode::VPMAXUBrr, + 17168 => Opcode::VPMAXUDYrm, + 17169 => Opcode::VPMAXUDYrr, + 17170 => Opcode::VPMAXUDZ128rm, + 17171 => Opcode::VPMAXUDZ128rmb, + 17172 => Opcode::VPMAXUDZ128rmbk, + 17173 => Opcode::VPMAXUDZ128rmbkz, + 17174 => Opcode::VPMAXUDZ128rmk, + 17175 => Opcode::VPMAXUDZ128rmkz, + 17176 => Opcode::VPMAXUDZ128rr, + 17177 => Opcode::VPMAXUDZ128rrk, + 17178 => Opcode::VPMAXUDZ128rrkz, + 17179 => Opcode::VPMAXUDZ256rm, + 17180 => Opcode::VPMAXUDZ256rmb, + 17181 => Opcode::VPMAXUDZ256rmbk, + 17182 => Opcode::VPMAXUDZ256rmbkz, + 17183 => Opcode::VPMAXUDZ256rmk, + 17184 => Opcode::VPMAXUDZ256rmkz, + 17185 => Opcode::VPMAXUDZ256rr, + 17186 => Opcode::VPMAXUDZ256rrk, + 17187 => Opcode::VPMAXUDZ256rrkz, + 17188 => Opcode::VPMAXUDZrm, + 17189 => Opcode::VPMAXUDZrmb, + 17190 => Opcode::VPMAXUDZrmbk, + 17191 => Opcode::VPMAXUDZrmbkz, + 17192 => Opcode::VPMAXUDZrmk, + 17193 => Opcode::VPMAXUDZrmkz, + 17194 => Opcode::VPMAXUDZrr, + 17195 => Opcode::VPMAXUDZrrk, + 17196 => Opcode::VPMAXUDZrrkz, + 17197 => Opcode::VPMAXUDrm, + 17198 => Opcode::VPMAXUDrr, + 17199 => Opcode::VPMAXUQZ128rm, + 17200 => Opcode::VPMAXUQZ128rmb, + 17201 => Opcode::VPMAXUQZ128rmbk, + 17202 => Opcode::VPMAXUQZ128rmbkz, + 17203 => Opcode::VPMAXUQZ128rmk, + 17204 => Opcode::VPMAXUQZ128rmkz, + 17205 => Opcode::VPMAXUQZ128rr, + 17206 => Opcode::VPMAXUQZ128rrk, + 17207 => Opcode::VPMAXUQZ128rrkz, + 17208 => Opcode::VPMAXUQZ256rm, + 17209 => Opcode::VPMAXUQZ256rmb, + 17210 => Opcode::VPMAXUQZ256rmbk, + 17211 => Opcode::VPMAXUQZ256rmbkz, + 17212 => Opcode::VPMAXUQZ256rmk, + 17213 => Opcode::VPMAXUQZ256rmkz, + 17214 => Opcode::VPMAXUQZ256rr, + 17215 => Opcode::VPMAXUQZ256rrk, + 17216 => Opcode::VPMAXUQZ256rrkz, + 17217 => Opcode::VPMAXUQZrm, + 17218 => Opcode::VPMAXUQZrmb, + 17219 => Opcode::VPMAXUQZrmbk, + 17220 => Opcode::VPMAXUQZrmbkz, + 17221 => Opcode::VPMAXUQZrmk, + 17222 => Opcode::VPMAXUQZrmkz, + 17223 => Opcode::VPMAXUQZrr, + 17224 => Opcode::VPMAXUQZrrk, + 17225 => Opcode::VPMAXUQZrrkz, + 17226 => Opcode::VPMAXUWYrm, + 17227 => Opcode::VPMAXUWYrr, + 17228 => Opcode::VPMAXUWZ128rm, + 17229 => Opcode::VPMAXUWZ128rmk, + 17230 => Opcode::VPMAXUWZ128rmkz, + 17231 => Opcode::VPMAXUWZ128rr, + 17232 => Opcode::VPMAXUWZ128rrk, + 17233 => Opcode::VPMAXUWZ128rrkz, + 17234 => Opcode::VPMAXUWZ256rm, + 17235 => Opcode::VPMAXUWZ256rmk, + 17236 => Opcode::VPMAXUWZ256rmkz, + 17237 => Opcode::VPMAXUWZ256rr, + 17238 => Opcode::VPMAXUWZ256rrk, + 17239 => Opcode::VPMAXUWZ256rrkz, + 17240 => Opcode::VPMAXUWZrm, + 17241 => Opcode::VPMAXUWZrmk, + 17242 => Opcode::VPMAXUWZrmkz, + 17243 => Opcode::VPMAXUWZrr, + 17244 => Opcode::VPMAXUWZrrk, + 17245 => Opcode::VPMAXUWZrrkz, + 17246 => Opcode::VPMAXUWrm, + 17247 => Opcode::VPMAXUWrr, + 17248 => Opcode::VPMINSBYrm, + 17249 => Opcode::VPMINSBYrr, + 17250 => Opcode::VPMINSBZ128rm, + 17251 => Opcode::VPMINSBZ128rmk, + 17252 => Opcode::VPMINSBZ128rmkz, + 17253 => Opcode::VPMINSBZ128rr, + 17254 => Opcode::VPMINSBZ128rrk, + 17255 => Opcode::VPMINSBZ128rrkz, + 17256 => Opcode::VPMINSBZ256rm, + 17257 => Opcode::VPMINSBZ256rmk, + 17258 => Opcode::VPMINSBZ256rmkz, + 17259 => Opcode::VPMINSBZ256rr, + 17260 => Opcode::VPMINSBZ256rrk, + 17261 => Opcode::VPMINSBZ256rrkz, + 17262 => Opcode::VPMINSBZrm, + 17263 => Opcode::VPMINSBZrmk, + 17264 => Opcode::VPMINSBZrmkz, + 17265 => Opcode::VPMINSBZrr, + 17266 => Opcode::VPMINSBZrrk, + 17267 => Opcode::VPMINSBZrrkz, + 17268 => Opcode::VPMINSBrm, + 17269 => Opcode::VPMINSBrr, + 17270 => Opcode::VPMINSDYrm, + 17271 => Opcode::VPMINSDYrr, + 17272 => Opcode::VPMINSDZ128rm, + 17273 => Opcode::VPMINSDZ128rmb, + 17274 => Opcode::VPMINSDZ128rmbk, + 17275 => Opcode::VPMINSDZ128rmbkz, + 17276 => Opcode::VPMINSDZ128rmk, + 17277 => Opcode::VPMINSDZ128rmkz, + 17278 => Opcode::VPMINSDZ128rr, + 17279 => Opcode::VPMINSDZ128rrk, + 17280 => Opcode::VPMINSDZ128rrkz, + 17281 => Opcode::VPMINSDZ256rm, + 17282 => Opcode::VPMINSDZ256rmb, + 17283 => Opcode::VPMINSDZ256rmbk, + 17284 => Opcode::VPMINSDZ256rmbkz, + 17285 => Opcode::VPMINSDZ256rmk, + 17286 => Opcode::VPMINSDZ256rmkz, + 17287 => Opcode::VPMINSDZ256rr, + 17288 => Opcode::VPMINSDZ256rrk, + 17289 => Opcode::VPMINSDZ256rrkz, + 17290 => Opcode::VPMINSDZrm, + 17291 => Opcode::VPMINSDZrmb, + 17292 => Opcode::VPMINSDZrmbk, + 17293 => Opcode::VPMINSDZrmbkz, + 17294 => Opcode::VPMINSDZrmk, + 17295 => Opcode::VPMINSDZrmkz, + 17296 => Opcode::VPMINSDZrr, + 17297 => Opcode::VPMINSDZrrk, + 17298 => Opcode::VPMINSDZrrkz, + 17299 => Opcode::VPMINSDrm, + 17300 => Opcode::VPMINSDrr, + 17301 => Opcode::VPMINSQZ128rm, + 17302 => Opcode::VPMINSQZ128rmb, + 17303 => Opcode::VPMINSQZ128rmbk, + 17304 => Opcode::VPMINSQZ128rmbkz, + 17305 => Opcode::VPMINSQZ128rmk, + 17306 => Opcode::VPMINSQZ128rmkz, + 17307 => Opcode::VPMINSQZ128rr, + 17308 => Opcode::VPMINSQZ128rrk, + 17309 => Opcode::VPMINSQZ128rrkz, + 17310 => Opcode::VPMINSQZ256rm, + 17311 => Opcode::VPMINSQZ256rmb, + 17312 => Opcode::VPMINSQZ256rmbk, + 17313 => Opcode::VPMINSQZ256rmbkz, + 17314 => Opcode::VPMINSQZ256rmk, + 17315 => Opcode::VPMINSQZ256rmkz, + 17316 => Opcode::VPMINSQZ256rr, + 17317 => Opcode::VPMINSQZ256rrk, + 17318 => Opcode::VPMINSQZ256rrkz, + 17319 => Opcode::VPMINSQZrm, + 17320 => Opcode::VPMINSQZrmb, + 17321 => Opcode::VPMINSQZrmbk, + 17322 => Opcode::VPMINSQZrmbkz, + 17323 => Opcode::VPMINSQZrmk, + 17324 => Opcode::VPMINSQZrmkz, + 17325 => Opcode::VPMINSQZrr, + 17326 => Opcode::VPMINSQZrrk, + 17327 => Opcode::VPMINSQZrrkz, + 17328 => Opcode::VPMINSWYrm, + 17329 => Opcode::VPMINSWYrr, + 17330 => Opcode::VPMINSWZ128rm, + 17331 => Opcode::VPMINSWZ128rmk, + 17332 => Opcode::VPMINSWZ128rmkz, + 17333 => Opcode::VPMINSWZ128rr, + 17334 => Opcode::VPMINSWZ128rrk, + 17335 => Opcode::VPMINSWZ128rrkz, + 17336 => Opcode::VPMINSWZ256rm, + 17337 => Opcode::VPMINSWZ256rmk, + 17338 => Opcode::VPMINSWZ256rmkz, + 17339 => Opcode::VPMINSWZ256rr, + 17340 => Opcode::VPMINSWZ256rrk, + 17341 => Opcode::VPMINSWZ256rrkz, + 17342 => Opcode::VPMINSWZrm, + 17343 => Opcode::VPMINSWZrmk, + 17344 => Opcode::VPMINSWZrmkz, + 17345 => Opcode::VPMINSWZrr, + 17346 => Opcode::VPMINSWZrrk, + 17347 => Opcode::VPMINSWZrrkz, + 17348 => Opcode::VPMINSWrm, + 17349 => Opcode::VPMINSWrr, + 17350 => Opcode::VPMINUBYrm, + 17351 => Opcode::VPMINUBYrr, + 17352 => Opcode::VPMINUBZ128rm, + 17353 => Opcode::VPMINUBZ128rmk, + 17354 => Opcode::VPMINUBZ128rmkz, + 17355 => Opcode::VPMINUBZ128rr, + 17356 => Opcode::VPMINUBZ128rrk, + 17357 => Opcode::VPMINUBZ128rrkz, + 17358 => Opcode::VPMINUBZ256rm, + 17359 => Opcode::VPMINUBZ256rmk, + 17360 => Opcode::VPMINUBZ256rmkz, + 17361 => Opcode::VPMINUBZ256rr, + 17362 => Opcode::VPMINUBZ256rrk, + 17363 => Opcode::VPMINUBZ256rrkz, + 17364 => Opcode::VPMINUBZrm, + 17365 => Opcode::VPMINUBZrmk, + 17366 => Opcode::VPMINUBZrmkz, + 17367 => Opcode::VPMINUBZrr, + 17368 => Opcode::VPMINUBZrrk, + 17369 => Opcode::VPMINUBZrrkz, + 17370 => Opcode::VPMINUBrm, + 17371 => Opcode::VPMINUBrr, + 17372 => Opcode::VPMINUDYrm, + 17373 => Opcode::VPMINUDYrr, + 17374 => Opcode::VPMINUDZ128rm, + 17375 => Opcode::VPMINUDZ128rmb, + 17376 => Opcode::VPMINUDZ128rmbk, + 17377 => Opcode::VPMINUDZ128rmbkz, + 17378 => Opcode::VPMINUDZ128rmk, + 17379 => Opcode::VPMINUDZ128rmkz, + 17380 => Opcode::VPMINUDZ128rr, + 17381 => Opcode::VPMINUDZ128rrk, + 17382 => Opcode::VPMINUDZ128rrkz, + 17383 => Opcode::VPMINUDZ256rm, + 17384 => Opcode::VPMINUDZ256rmb, + 17385 => Opcode::VPMINUDZ256rmbk, + 17386 => Opcode::VPMINUDZ256rmbkz, + 17387 => Opcode::VPMINUDZ256rmk, + 17388 => Opcode::VPMINUDZ256rmkz, + 17389 => Opcode::VPMINUDZ256rr, + 17390 => Opcode::VPMINUDZ256rrk, + 17391 => Opcode::VPMINUDZ256rrkz, + 17392 => Opcode::VPMINUDZrm, + 17393 => Opcode::VPMINUDZrmb, + 17394 => Opcode::VPMINUDZrmbk, + 17395 => Opcode::VPMINUDZrmbkz, + 17396 => Opcode::VPMINUDZrmk, + 17397 => Opcode::VPMINUDZrmkz, + 17398 => Opcode::VPMINUDZrr, + 17399 => Opcode::VPMINUDZrrk, + 17400 => Opcode::VPMINUDZrrkz, + 17401 => Opcode::VPMINUDrm, + 17402 => Opcode::VPMINUDrr, + 17403 => Opcode::VPMINUQZ128rm, + 17404 => Opcode::VPMINUQZ128rmb, + 17405 => Opcode::VPMINUQZ128rmbk, + 17406 => Opcode::VPMINUQZ128rmbkz, + 17407 => Opcode::VPMINUQZ128rmk, + 17408 => Opcode::VPMINUQZ128rmkz, + 17409 => Opcode::VPMINUQZ128rr, + 17410 => Opcode::VPMINUQZ128rrk, + 17411 => Opcode::VPMINUQZ128rrkz, + 17412 => Opcode::VPMINUQZ256rm, + 17413 => Opcode::VPMINUQZ256rmb, + 17414 => Opcode::VPMINUQZ256rmbk, + 17415 => Opcode::VPMINUQZ256rmbkz, + 17416 => Opcode::VPMINUQZ256rmk, + 17417 => Opcode::VPMINUQZ256rmkz, + 17418 => Opcode::VPMINUQZ256rr, + 17419 => Opcode::VPMINUQZ256rrk, + 17420 => Opcode::VPMINUQZ256rrkz, + 17421 => Opcode::VPMINUQZrm, + 17422 => Opcode::VPMINUQZrmb, + 17423 => Opcode::VPMINUQZrmbk, + 17424 => Opcode::VPMINUQZrmbkz, + 17425 => Opcode::VPMINUQZrmk, + 17426 => Opcode::VPMINUQZrmkz, + 17427 => Opcode::VPMINUQZrr, + 17428 => Opcode::VPMINUQZrrk, + 17429 => Opcode::VPMINUQZrrkz, + 17430 => Opcode::VPMINUWYrm, + 17431 => Opcode::VPMINUWYrr, + 17432 => Opcode::VPMINUWZ128rm, + 17433 => Opcode::VPMINUWZ128rmk, + 17434 => Opcode::VPMINUWZ128rmkz, + 17435 => Opcode::VPMINUWZ128rr, + 17436 => Opcode::VPMINUWZ128rrk, + 17437 => Opcode::VPMINUWZ128rrkz, + 17438 => Opcode::VPMINUWZ256rm, + 17439 => Opcode::VPMINUWZ256rmk, + 17440 => Opcode::VPMINUWZ256rmkz, + 17441 => Opcode::VPMINUWZ256rr, + 17442 => Opcode::VPMINUWZ256rrk, + 17443 => Opcode::VPMINUWZ256rrkz, + 17444 => Opcode::VPMINUWZrm, + 17445 => Opcode::VPMINUWZrmk, + 17446 => Opcode::VPMINUWZrmkz, + 17447 => Opcode::VPMINUWZrr, + 17448 => Opcode::VPMINUWZrrk, + 17449 => Opcode::VPMINUWZrrkz, + 17450 => Opcode::VPMINUWrm, + 17451 => Opcode::VPMINUWrr, + 17452 => Opcode::VPMOVB2MZ128kr, + 17453 => Opcode::VPMOVB2MZ256kr, + 17454 => Opcode::VPMOVB2MZkr, + 17455 => Opcode::VPMOVD2MZ128kr, + 17456 => Opcode::VPMOVD2MZ256kr, + 17457 => Opcode::VPMOVD2MZkr, + 17458 => Opcode::VPMOVDBZ128mr, + 17459 => Opcode::VPMOVDBZ128mrk, + 17460 => Opcode::VPMOVDBZ128rr, + 17461 => Opcode::VPMOVDBZ128rrk, + 17462 => Opcode::VPMOVDBZ128rrkz, + 17463 => Opcode::VPMOVDBZ256mr, + 17464 => Opcode::VPMOVDBZ256mrk, + 17465 => Opcode::VPMOVDBZ256rr, + 17466 => Opcode::VPMOVDBZ256rrk, + 17467 => Opcode::VPMOVDBZ256rrkz, + 17468 => Opcode::VPMOVDBZmr, + 17469 => Opcode::VPMOVDBZmrk, + 17470 => Opcode::VPMOVDBZrr, + 17471 => Opcode::VPMOVDBZrrk, + 17472 => Opcode::VPMOVDBZrrkz, + 17473 => Opcode::VPMOVDWZ128mr, + 17474 => Opcode::VPMOVDWZ128mrk, + 17475 => Opcode::VPMOVDWZ128rr, + 17476 => Opcode::VPMOVDWZ128rrk, + 17477 => Opcode::VPMOVDWZ128rrkz, + 17478 => Opcode::VPMOVDWZ256mr, + 17479 => Opcode::VPMOVDWZ256mrk, + 17480 => Opcode::VPMOVDWZ256rr, + 17481 => Opcode::VPMOVDWZ256rrk, + 17482 => Opcode::VPMOVDWZ256rrkz, + 17483 => Opcode::VPMOVDWZmr, + 17484 => Opcode::VPMOVDWZmrk, + 17485 => Opcode::VPMOVDWZrr, + 17486 => Opcode::VPMOVDWZrrk, + 17487 => Opcode::VPMOVDWZrrkz, + 17488 => Opcode::VPMOVM2BZ128rk, + 17489 => Opcode::VPMOVM2BZ256rk, + 17490 => Opcode::VPMOVM2BZrk, + 17491 => Opcode::VPMOVM2DZ128rk, + 17492 => Opcode::VPMOVM2DZ256rk, + 17493 => Opcode::VPMOVM2DZrk, + 17494 => Opcode::VPMOVM2QZ128rk, + 17495 => Opcode::VPMOVM2QZ256rk, + 17496 => Opcode::VPMOVM2QZrk, + 17497 => Opcode::VPMOVM2WZ128rk, + 17498 => Opcode::VPMOVM2WZ256rk, + 17499 => Opcode::VPMOVM2WZrk, + 17500 => Opcode::VPMOVMSKBYrr, + 17501 => Opcode::VPMOVMSKBrr, + 17502 => Opcode::VPMOVQ2MZ128kr, + 17503 => Opcode::VPMOVQ2MZ256kr, + 17504 => Opcode::VPMOVQ2MZkr, + 17505 => Opcode::VPMOVQBZ128mr, + 17506 => Opcode::VPMOVQBZ128mrk, + 17507 => Opcode::VPMOVQBZ128rr, + 17508 => Opcode::VPMOVQBZ128rrk, + 17509 => Opcode::VPMOVQBZ128rrkz, + 17510 => Opcode::VPMOVQBZ256mr, + 17511 => Opcode::VPMOVQBZ256mrk, + 17512 => Opcode::VPMOVQBZ256rr, + 17513 => Opcode::VPMOVQBZ256rrk, + 17514 => Opcode::VPMOVQBZ256rrkz, + 17515 => Opcode::VPMOVQBZmr, + 17516 => Opcode::VPMOVQBZmrk, + 17517 => Opcode::VPMOVQBZrr, + 17518 => Opcode::VPMOVQBZrrk, + 17519 => Opcode::VPMOVQBZrrkz, + 17520 => Opcode::VPMOVQDZ128mr, + 17521 => Opcode::VPMOVQDZ128mrk, + 17522 => Opcode::VPMOVQDZ128rr, + 17523 => Opcode::VPMOVQDZ128rrk, + 17524 => Opcode::VPMOVQDZ128rrkz, + 17525 => Opcode::VPMOVQDZ256mr, + 17526 => Opcode::VPMOVQDZ256mrk, + 17527 => Opcode::VPMOVQDZ256rr, + 17528 => Opcode::VPMOVQDZ256rrk, + 17529 => Opcode::VPMOVQDZ256rrkz, + 17530 => Opcode::VPMOVQDZmr, + 17531 => Opcode::VPMOVQDZmrk, + 17532 => Opcode::VPMOVQDZrr, + 17533 => Opcode::VPMOVQDZrrk, + 17534 => Opcode::VPMOVQDZrrkz, + 17535 => Opcode::VPMOVQWZ128mr, + 17536 => Opcode::VPMOVQWZ128mrk, + 17537 => Opcode::VPMOVQWZ128rr, + 17538 => Opcode::VPMOVQWZ128rrk, + 17539 => Opcode::VPMOVQWZ128rrkz, + 17540 => Opcode::VPMOVQWZ256mr, + 17541 => Opcode::VPMOVQWZ256mrk, + 17542 => Opcode::VPMOVQWZ256rr, + 17543 => Opcode::VPMOVQWZ256rrk, + 17544 => Opcode::VPMOVQWZ256rrkz, + 17545 => Opcode::VPMOVQWZmr, + 17546 => Opcode::VPMOVQWZmrk, + 17547 => Opcode::VPMOVQWZrr, + 17548 => Opcode::VPMOVQWZrrk, + 17549 => Opcode::VPMOVQWZrrkz, + 17550 => Opcode::VPMOVSDBZ128mr, + 17551 => Opcode::VPMOVSDBZ128mrk, + 17552 => Opcode::VPMOVSDBZ128rr, + 17553 => Opcode::VPMOVSDBZ128rrk, + 17554 => Opcode::VPMOVSDBZ128rrkz, + 17555 => Opcode::VPMOVSDBZ256mr, + 17556 => Opcode::VPMOVSDBZ256mrk, + 17557 => Opcode::VPMOVSDBZ256rr, + 17558 => Opcode::VPMOVSDBZ256rrk, + 17559 => Opcode::VPMOVSDBZ256rrkz, + 17560 => Opcode::VPMOVSDBZmr, + 17561 => Opcode::VPMOVSDBZmrk, + 17562 => Opcode::VPMOVSDBZrr, + 17563 => Opcode::VPMOVSDBZrrk, + 17564 => Opcode::VPMOVSDBZrrkz, + 17565 => Opcode::VPMOVSDWZ128mr, + 17566 => Opcode::VPMOVSDWZ128mrk, + 17567 => Opcode::VPMOVSDWZ128rr, + 17568 => Opcode::VPMOVSDWZ128rrk, + 17569 => Opcode::VPMOVSDWZ128rrkz, + 17570 => Opcode::VPMOVSDWZ256mr, + 17571 => Opcode::VPMOVSDWZ256mrk, + 17572 => Opcode::VPMOVSDWZ256rr, + 17573 => Opcode::VPMOVSDWZ256rrk, + 17574 => Opcode::VPMOVSDWZ256rrkz, + 17575 => Opcode::VPMOVSDWZmr, + 17576 => Opcode::VPMOVSDWZmrk, + 17577 => Opcode::VPMOVSDWZrr, + 17578 => Opcode::VPMOVSDWZrrk, + 17579 => Opcode::VPMOVSDWZrrkz, + 17580 => Opcode::VPMOVSQBZ128mr, + 17581 => Opcode::VPMOVSQBZ128mrk, + 17582 => Opcode::VPMOVSQBZ128rr, + 17583 => Opcode::VPMOVSQBZ128rrk, + 17584 => Opcode::VPMOVSQBZ128rrkz, + 17585 => Opcode::VPMOVSQBZ256mr, + 17586 => Opcode::VPMOVSQBZ256mrk, + 17587 => Opcode::VPMOVSQBZ256rr, + 17588 => Opcode::VPMOVSQBZ256rrk, + 17589 => Opcode::VPMOVSQBZ256rrkz, + 17590 => Opcode::VPMOVSQBZmr, + 17591 => Opcode::VPMOVSQBZmrk, + 17592 => Opcode::VPMOVSQBZrr, + 17593 => Opcode::VPMOVSQBZrrk, + 17594 => Opcode::VPMOVSQBZrrkz, + 17595 => Opcode::VPMOVSQDZ128mr, + 17596 => Opcode::VPMOVSQDZ128mrk, + 17597 => Opcode::VPMOVSQDZ128rr, + 17598 => Opcode::VPMOVSQDZ128rrk, + 17599 => Opcode::VPMOVSQDZ128rrkz, + 17600 => Opcode::VPMOVSQDZ256mr, + 17601 => Opcode::VPMOVSQDZ256mrk, + 17602 => Opcode::VPMOVSQDZ256rr, + 17603 => Opcode::VPMOVSQDZ256rrk, + 17604 => Opcode::VPMOVSQDZ256rrkz, + 17605 => Opcode::VPMOVSQDZmr, + 17606 => Opcode::VPMOVSQDZmrk, + 17607 => Opcode::VPMOVSQDZrr, + 17608 => Opcode::VPMOVSQDZrrk, + 17609 => Opcode::VPMOVSQDZrrkz, + 17610 => Opcode::VPMOVSQWZ128mr, + 17611 => Opcode::VPMOVSQWZ128mrk, + 17612 => Opcode::VPMOVSQWZ128rr, + 17613 => Opcode::VPMOVSQWZ128rrk, + 17614 => Opcode::VPMOVSQWZ128rrkz, + 17615 => Opcode::VPMOVSQWZ256mr, + 17616 => Opcode::VPMOVSQWZ256mrk, + 17617 => Opcode::VPMOVSQWZ256rr, + 17618 => Opcode::VPMOVSQWZ256rrk, + 17619 => Opcode::VPMOVSQWZ256rrkz, + 17620 => Opcode::VPMOVSQWZmr, + 17621 => Opcode::VPMOVSQWZmrk, + 17622 => Opcode::VPMOVSQWZrr, + 17623 => Opcode::VPMOVSQWZrrk, + 17624 => Opcode::VPMOVSQWZrrkz, + 17625 => Opcode::VPMOVSWBZ128mr, + 17626 => Opcode::VPMOVSWBZ128mrk, + 17627 => Opcode::VPMOVSWBZ128rr, + 17628 => Opcode::VPMOVSWBZ128rrk, + 17629 => Opcode::VPMOVSWBZ128rrkz, + 17630 => Opcode::VPMOVSWBZ256mr, + 17631 => Opcode::VPMOVSWBZ256mrk, + 17632 => Opcode::VPMOVSWBZ256rr, + 17633 => Opcode::VPMOVSWBZ256rrk, + 17634 => Opcode::VPMOVSWBZ256rrkz, + 17635 => Opcode::VPMOVSWBZmr, + 17636 => Opcode::VPMOVSWBZmrk, + 17637 => Opcode::VPMOVSWBZrr, + 17638 => Opcode::VPMOVSWBZrrk, + 17639 => Opcode::VPMOVSWBZrrkz, + 17640 => Opcode::VPMOVSXBDYrm, + 17641 => Opcode::VPMOVSXBDYrr, + 17642 => Opcode::VPMOVSXBDZ128rm, + 17643 => Opcode::VPMOVSXBDZ128rmk, + 17644 => Opcode::VPMOVSXBDZ128rmkz, + 17645 => Opcode::VPMOVSXBDZ128rr, + 17646 => Opcode::VPMOVSXBDZ128rrk, + 17647 => Opcode::VPMOVSXBDZ128rrkz, + 17648 => Opcode::VPMOVSXBDZ256rm, + 17649 => Opcode::VPMOVSXBDZ256rmk, + 17650 => Opcode::VPMOVSXBDZ256rmkz, + 17651 => Opcode::VPMOVSXBDZ256rr, + 17652 => Opcode::VPMOVSXBDZ256rrk, + 17653 => Opcode::VPMOVSXBDZ256rrkz, + 17654 => Opcode::VPMOVSXBDZrm, + 17655 => Opcode::VPMOVSXBDZrmk, + 17656 => Opcode::VPMOVSXBDZrmkz, + 17657 => Opcode::VPMOVSXBDZrr, + 17658 => Opcode::VPMOVSXBDZrrk, + 17659 => Opcode::VPMOVSXBDZrrkz, + 17660 => Opcode::VPMOVSXBDrm, + 17661 => Opcode::VPMOVSXBDrr, + 17662 => Opcode::VPMOVSXBQYrm, + 17663 => Opcode::VPMOVSXBQYrr, + 17664 => Opcode::VPMOVSXBQZ128rm, + 17665 => Opcode::VPMOVSXBQZ128rmk, + 17666 => Opcode::VPMOVSXBQZ128rmkz, + 17667 => Opcode::VPMOVSXBQZ128rr, + 17668 => Opcode::VPMOVSXBQZ128rrk, + 17669 => Opcode::VPMOVSXBQZ128rrkz, + 17670 => Opcode::VPMOVSXBQZ256rm, + 17671 => Opcode::VPMOVSXBQZ256rmk, + 17672 => Opcode::VPMOVSXBQZ256rmkz, + 17673 => Opcode::VPMOVSXBQZ256rr, + 17674 => Opcode::VPMOVSXBQZ256rrk, + 17675 => Opcode::VPMOVSXBQZ256rrkz, + 17676 => Opcode::VPMOVSXBQZrm, + 17677 => Opcode::VPMOVSXBQZrmk, + 17678 => Opcode::VPMOVSXBQZrmkz, + 17679 => Opcode::VPMOVSXBQZrr, + 17680 => Opcode::VPMOVSXBQZrrk, + 17681 => Opcode::VPMOVSXBQZrrkz, + 17682 => Opcode::VPMOVSXBQrm, + 17683 => Opcode::VPMOVSXBQrr, + 17684 => Opcode::VPMOVSXBWYrm, + 17685 => Opcode::VPMOVSXBWYrr, + 17686 => Opcode::VPMOVSXBWZ128rm, + 17687 => Opcode::VPMOVSXBWZ128rmk, + 17688 => Opcode::VPMOVSXBWZ128rmkz, + 17689 => Opcode::VPMOVSXBWZ128rr, + 17690 => Opcode::VPMOVSXBWZ128rrk, + 17691 => Opcode::VPMOVSXBWZ128rrkz, + 17692 => Opcode::VPMOVSXBWZ256rm, + 17693 => Opcode::VPMOVSXBWZ256rmk, + 17694 => Opcode::VPMOVSXBWZ256rmkz, + 17695 => Opcode::VPMOVSXBWZ256rr, + 17696 => Opcode::VPMOVSXBWZ256rrk, + 17697 => Opcode::VPMOVSXBWZ256rrkz, + 17698 => Opcode::VPMOVSXBWZrm, + 17699 => Opcode::VPMOVSXBWZrmk, + 17700 => Opcode::VPMOVSXBWZrmkz, + 17701 => Opcode::VPMOVSXBWZrr, + 17702 => Opcode::VPMOVSXBWZrrk, + 17703 => Opcode::VPMOVSXBWZrrkz, + 17704 => Opcode::VPMOVSXBWrm, + 17705 => Opcode::VPMOVSXBWrr, + 17706 => Opcode::VPMOVSXDQYrm, + 17707 => Opcode::VPMOVSXDQYrr, + 17708 => Opcode::VPMOVSXDQZ128rm, + 17709 => Opcode::VPMOVSXDQZ128rmk, + 17710 => Opcode::VPMOVSXDQZ128rmkz, + 17711 => Opcode::VPMOVSXDQZ128rr, + 17712 => Opcode::VPMOVSXDQZ128rrk, + 17713 => Opcode::VPMOVSXDQZ128rrkz, + 17714 => Opcode::VPMOVSXDQZ256rm, + 17715 => Opcode::VPMOVSXDQZ256rmk, + 17716 => Opcode::VPMOVSXDQZ256rmkz, + 17717 => Opcode::VPMOVSXDQZ256rr, + 17718 => Opcode::VPMOVSXDQZ256rrk, + 17719 => Opcode::VPMOVSXDQZ256rrkz, + 17720 => Opcode::VPMOVSXDQZrm, + 17721 => Opcode::VPMOVSXDQZrmk, + 17722 => Opcode::VPMOVSXDQZrmkz, + 17723 => Opcode::VPMOVSXDQZrr, + 17724 => Opcode::VPMOVSXDQZrrk, + 17725 => Opcode::VPMOVSXDQZrrkz, + 17726 => Opcode::VPMOVSXDQrm, + 17727 => Opcode::VPMOVSXDQrr, + 17728 => Opcode::VPMOVSXWDYrm, + 17729 => Opcode::VPMOVSXWDYrr, + 17730 => Opcode::VPMOVSXWDZ128rm, + 17731 => Opcode::VPMOVSXWDZ128rmk, + 17732 => Opcode::VPMOVSXWDZ128rmkz, + 17733 => Opcode::VPMOVSXWDZ128rr, + 17734 => Opcode::VPMOVSXWDZ128rrk, + 17735 => Opcode::VPMOVSXWDZ128rrkz, + 17736 => Opcode::VPMOVSXWDZ256rm, + 17737 => Opcode::VPMOVSXWDZ256rmk, + 17738 => Opcode::VPMOVSXWDZ256rmkz, + 17739 => Opcode::VPMOVSXWDZ256rr, + 17740 => Opcode::VPMOVSXWDZ256rrk, + 17741 => Opcode::VPMOVSXWDZ256rrkz, + 17742 => Opcode::VPMOVSXWDZrm, + 17743 => Opcode::VPMOVSXWDZrmk, + 17744 => Opcode::VPMOVSXWDZrmkz, + 17745 => Opcode::VPMOVSXWDZrr, + 17746 => Opcode::VPMOVSXWDZrrk, + 17747 => Opcode::VPMOVSXWDZrrkz, + 17748 => Opcode::VPMOVSXWDrm, + 17749 => Opcode::VPMOVSXWDrr, + 17750 => Opcode::VPMOVSXWQYrm, + 17751 => Opcode::VPMOVSXWQYrr, + 17752 => Opcode::VPMOVSXWQZ128rm, + 17753 => Opcode::VPMOVSXWQZ128rmk, + 17754 => Opcode::VPMOVSXWQZ128rmkz, + 17755 => Opcode::VPMOVSXWQZ128rr, + 17756 => Opcode::VPMOVSXWQZ128rrk, + 17757 => Opcode::VPMOVSXWQZ128rrkz, + 17758 => Opcode::VPMOVSXWQZ256rm, + 17759 => Opcode::VPMOVSXWQZ256rmk, + 17760 => Opcode::VPMOVSXWQZ256rmkz, + 17761 => Opcode::VPMOVSXWQZ256rr, + 17762 => Opcode::VPMOVSXWQZ256rrk, + 17763 => Opcode::VPMOVSXWQZ256rrkz, + 17764 => Opcode::VPMOVSXWQZrm, + 17765 => Opcode::VPMOVSXWQZrmk, + 17766 => Opcode::VPMOVSXWQZrmkz, + 17767 => Opcode::VPMOVSXWQZrr, + 17768 => Opcode::VPMOVSXWQZrrk, + 17769 => Opcode::VPMOVSXWQZrrkz, + 17770 => Opcode::VPMOVSXWQrm, + 17771 => Opcode::VPMOVSXWQrr, + 17772 => Opcode::VPMOVUSDBZ128mr, + 17773 => Opcode::VPMOVUSDBZ128mrk, + 17774 => Opcode::VPMOVUSDBZ128rr, + 17775 => Opcode::VPMOVUSDBZ128rrk, + 17776 => Opcode::VPMOVUSDBZ128rrkz, + 17777 => Opcode::VPMOVUSDBZ256mr, + 17778 => Opcode::VPMOVUSDBZ256mrk, + 17779 => Opcode::VPMOVUSDBZ256rr, + 17780 => Opcode::VPMOVUSDBZ256rrk, + 17781 => Opcode::VPMOVUSDBZ256rrkz, + 17782 => Opcode::VPMOVUSDBZmr, + 17783 => Opcode::VPMOVUSDBZmrk, + 17784 => Opcode::VPMOVUSDBZrr, + 17785 => Opcode::VPMOVUSDBZrrk, + 17786 => Opcode::VPMOVUSDBZrrkz, + 17787 => Opcode::VPMOVUSDWZ128mr, + 17788 => Opcode::VPMOVUSDWZ128mrk, + 17789 => Opcode::VPMOVUSDWZ128rr, + 17790 => Opcode::VPMOVUSDWZ128rrk, + 17791 => Opcode::VPMOVUSDWZ128rrkz, + 17792 => Opcode::VPMOVUSDWZ256mr, + 17793 => Opcode::VPMOVUSDWZ256mrk, + 17794 => Opcode::VPMOVUSDWZ256rr, + 17795 => Opcode::VPMOVUSDWZ256rrk, + 17796 => Opcode::VPMOVUSDWZ256rrkz, + 17797 => Opcode::VPMOVUSDWZmr, + 17798 => Opcode::VPMOVUSDWZmrk, + 17799 => Opcode::VPMOVUSDWZrr, + 17800 => Opcode::VPMOVUSDWZrrk, + 17801 => Opcode::VPMOVUSDWZrrkz, + 17802 => Opcode::VPMOVUSQBZ128mr, + 17803 => Opcode::VPMOVUSQBZ128mrk, + 17804 => Opcode::VPMOVUSQBZ128rr, + 17805 => Opcode::VPMOVUSQBZ128rrk, + 17806 => Opcode::VPMOVUSQBZ128rrkz, + 17807 => Opcode::VPMOVUSQBZ256mr, + 17808 => Opcode::VPMOVUSQBZ256mrk, + 17809 => Opcode::VPMOVUSQBZ256rr, + 17810 => Opcode::VPMOVUSQBZ256rrk, + 17811 => Opcode::VPMOVUSQBZ256rrkz, + 17812 => Opcode::VPMOVUSQBZmr, + 17813 => Opcode::VPMOVUSQBZmrk, + 17814 => Opcode::VPMOVUSQBZrr, + 17815 => Opcode::VPMOVUSQBZrrk, + 17816 => Opcode::VPMOVUSQBZrrkz, + 17817 => Opcode::VPMOVUSQDZ128mr, + 17818 => Opcode::VPMOVUSQDZ128mrk, + 17819 => Opcode::VPMOVUSQDZ128rr, + 17820 => Opcode::VPMOVUSQDZ128rrk, + 17821 => Opcode::VPMOVUSQDZ128rrkz, + 17822 => Opcode::VPMOVUSQDZ256mr, + 17823 => Opcode::VPMOVUSQDZ256mrk, + 17824 => Opcode::VPMOVUSQDZ256rr, + 17825 => Opcode::VPMOVUSQDZ256rrk, + 17826 => Opcode::VPMOVUSQDZ256rrkz, + 17827 => Opcode::VPMOVUSQDZmr, + 17828 => Opcode::VPMOVUSQDZmrk, + 17829 => Opcode::VPMOVUSQDZrr, + 17830 => Opcode::VPMOVUSQDZrrk, + 17831 => Opcode::VPMOVUSQDZrrkz, + 17832 => Opcode::VPMOVUSQWZ128mr, + 17833 => Opcode::VPMOVUSQWZ128mrk, + 17834 => Opcode::VPMOVUSQWZ128rr, + 17835 => Opcode::VPMOVUSQWZ128rrk, + 17836 => Opcode::VPMOVUSQWZ128rrkz, + 17837 => Opcode::VPMOVUSQWZ256mr, + 17838 => Opcode::VPMOVUSQWZ256mrk, + 17839 => Opcode::VPMOVUSQWZ256rr, + 17840 => Opcode::VPMOVUSQWZ256rrk, + 17841 => Opcode::VPMOVUSQWZ256rrkz, + 17842 => Opcode::VPMOVUSQWZmr, + 17843 => Opcode::VPMOVUSQWZmrk, + 17844 => Opcode::VPMOVUSQWZrr, + 17845 => Opcode::VPMOVUSQWZrrk, + 17846 => Opcode::VPMOVUSQWZrrkz, + 17847 => Opcode::VPMOVUSWBZ128mr, + 17848 => Opcode::VPMOVUSWBZ128mrk, + 17849 => Opcode::VPMOVUSWBZ128rr, + 17850 => Opcode::VPMOVUSWBZ128rrk, + 17851 => Opcode::VPMOVUSWBZ128rrkz, + 17852 => Opcode::VPMOVUSWBZ256mr, + 17853 => Opcode::VPMOVUSWBZ256mrk, + 17854 => Opcode::VPMOVUSWBZ256rr, + 17855 => Opcode::VPMOVUSWBZ256rrk, + 17856 => Opcode::VPMOVUSWBZ256rrkz, + 17857 => Opcode::VPMOVUSWBZmr, + 17858 => Opcode::VPMOVUSWBZmrk, + 17859 => Opcode::VPMOVUSWBZrr, + 17860 => Opcode::VPMOVUSWBZrrk, + 17861 => Opcode::VPMOVUSWBZrrkz, + 17862 => Opcode::VPMOVW2MZ128kr, + 17863 => Opcode::VPMOVW2MZ256kr, + 17864 => Opcode::VPMOVW2MZkr, + 17865 => Opcode::VPMOVWBZ128mr, + 17866 => Opcode::VPMOVWBZ128mrk, + 17867 => Opcode::VPMOVWBZ128rr, + 17868 => Opcode::VPMOVWBZ128rrk, + 17869 => Opcode::VPMOVWBZ128rrkz, + 17870 => Opcode::VPMOVWBZ256mr, + 17871 => Opcode::VPMOVWBZ256mrk, + 17872 => Opcode::VPMOVWBZ256rr, + 17873 => Opcode::VPMOVWBZ256rrk, + 17874 => Opcode::VPMOVWBZ256rrkz, + 17875 => Opcode::VPMOVWBZmr, + 17876 => Opcode::VPMOVWBZmrk, + 17877 => Opcode::VPMOVWBZrr, + 17878 => Opcode::VPMOVWBZrrk, + 17879 => Opcode::VPMOVWBZrrkz, + 17880 => Opcode::VPMOVZXBDYrm, + 17881 => Opcode::VPMOVZXBDYrr, + 17882 => Opcode::VPMOVZXBDZ128rm, + 17883 => Opcode::VPMOVZXBDZ128rmk, + 17884 => Opcode::VPMOVZXBDZ128rmkz, + 17885 => Opcode::VPMOVZXBDZ128rr, + 17886 => Opcode::VPMOVZXBDZ128rrk, + 17887 => Opcode::VPMOVZXBDZ128rrkz, + 17888 => Opcode::VPMOVZXBDZ256rm, + 17889 => Opcode::VPMOVZXBDZ256rmk, + 17890 => Opcode::VPMOVZXBDZ256rmkz, + 17891 => Opcode::VPMOVZXBDZ256rr, + 17892 => Opcode::VPMOVZXBDZ256rrk, + 17893 => Opcode::VPMOVZXBDZ256rrkz, + 17894 => Opcode::VPMOVZXBDZrm, + 17895 => Opcode::VPMOVZXBDZrmk, + 17896 => Opcode::VPMOVZXBDZrmkz, + 17897 => Opcode::VPMOVZXBDZrr, + 17898 => Opcode::VPMOVZXBDZrrk, + 17899 => Opcode::VPMOVZXBDZrrkz, + 17900 => Opcode::VPMOVZXBDrm, + 17901 => Opcode::VPMOVZXBDrr, + 17902 => Opcode::VPMOVZXBQYrm, + 17903 => Opcode::VPMOVZXBQYrr, + 17904 => Opcode::VPMOVZXBQZ128rm, + 17905 => Opcode::VPMOVZXBQZ128rmk, + 17906 => Opcode::VPMOVZXBQZ128rmkz, + 17907 => Opcode::VPMOVZXBQZ128rr, + 17908 => Opcode::VPMOVZXBQZ128rrk, + 17909 => Opcode::VPMOVZXBQZ128rrkz, + 17910 => Opcode::VPMOVZXBQZ256rm, + 17911 => Opcode::VPMOVZXBQZ256rmk, + 17912 => Opcode::VPMOVZXBQZ256rmkz, + 17913 => Opcode::VPMOVZXBQZ256rr, + 17914 => Opcode::VPMOVZXBQZ256rrk, + 17915 => Opcode::VPMOVZXBQZ256rrkz, + 17916 => Opcode::VPMOVZXBQZrm, + 17917 => Opcode::VPMOVZXBQZrmk, + 17918 => Opcode::VPMOVZXBQZrmkz, + 17919 => Opcode::VPMOVZXBQZrr, + 17920 => Opcode::VPMOVZXBQZrrk, + 17921 => Opcode::VPMOVZXBQZrrkz, + 17922 => Opcode::VPMOVZXBQrm, + 17923 => Opcode::VPMOVZXBQrr, + 17924 => Opcode::VPMOVZXBWYrm, + 17925 => Opcode::VPMOVZXBWYrr, + 17926 => Opcode::VPMOVZXBWZ128rm, + 17927 => Opcode::VPMOVZXBWZ128rmk, + 17928 => Opcode::VPMOVZXBWZ128rmkz, + 17929 => Opcode::VPMOVZXBWZ128rr, + 17930 => Opcode::VPMOVZXBWZ128rrk, + 17931 => Opcode::VPMOVZXBWZ128rrkz, + 17932 => Opcode::VPMOVZXBWZ256rm, + 17933 => Opcode::VPMOVZXBWZ256rmk, + 17934 => Opcode::VPMOVZXBWZ256rmkz, + 17935 => Opcode::VPMOVZXBWZ256rr, + 17936 => Opcode::VPMOVZXBWZ256rrk, + 17937 => Opcode::VPMOVZXBWZ256rrkz, + 17938 => Opcode::VPMOVZXBWZrm, + 17939 => Opcode::VPMOVZXBWZrmk, + 17940 => Opcode::VPMOVZXBWZrmkz, + 17941 => Opcode::VPMOVZXBWZrr, + 17942 => Opcode::VPMOVZXBWZrrk, + 17943 => Opcode::VPMOVZXBWZrrkz, + 17944 => Opcode::VPMOVZXBWrm, + 17945 => Opcode::VPMOVZXBWrr, + 17946 => Opcode::VPMOVZXDQYrm, + 17947 => Opcode::VPMOVZXDQYrr, + 17948 => Opcode::VPMOVZXDQZ128rm, + 17949 => Opcode::VPMOVZXDQZ128rmk, + 17950 => Opcode::VPMOVZXDQZ128rmkz, + 17951 => Opcode::VPMOVZXDQZ128rr, + 17952 => Opcode::VPMOVZXDQZ128rrk, + 17953 => Opcode::VPMOVZXDQZ128rrkz, + 17954 => Opcode::VPMOVZXDQZ256rm, + 17955 => Opcode::VPMOVZXDQZ256rmk, + 17956 => Opcode::VPMOVZXDQZ256rmkz, + 17957 => Opcode::VPMOVZXDQZ256rr, + 17958 => Opcode::VPMOVZXDQZ256rrk, + 17959 => Opcode::VPMOVZXDQZ256rrkz, + 17960 => Opcode::VPMOVZXDQZrm, + 17961 => Opcode::VPMOVZXDQZrmk, + 17962 => Opcode::VPMOVZXDQZrmkz, + 17963 => Opcode::VPMOVZXDQZrr, + 17964 => Opcode::VPMOVZXDQZrrk, + 17965 => Opcode::VPMOVZXDQZrrkz, + 17966 => Opcode::VPMOVZXDQrm, + 17967 => Opcode::VPMOVZXDQrr, + 17968 => Opcode::VPMOVZXWDYrm, + 17969 => Opcode::VPMOVZXWDYrr, + 17970 => Opcode::VPMOVZXWDZ128rm, + 17971 => Opcode::VPMOVZXWDZ128rmk, + 17972 => Opcode::VPMOVZXWDZ128rmkz, + 17973 => Opcode::VPMOVZXWDZ128rr, + 17974 => Opcode::VPMOVZXWDZ128rrk, + 17975 => Opcode::VPMOVZXWDZ128rrkz, + 17976 => Opcode::VPMOVZXWDZ256rm, + 17977 => Opcode::VPMOVZXWDZ256rmk, + 17978 => Opcode::VPMOVZXWDZ256rmkz, + 17979 => Opcode::VPMOVZXWDZ256rr, + 17980 => Opcode::VPMOVZXWDZ256rrk, + 17981 => Opcode::VPMOVZXWDZ256rrkz, + 17982 => Opcode::VPMOVZXWDZrm, + 17983 => Opcode::VPMOVZXWDZrmk, + 17984 => Opcode::VPMOVZXWDZrmkz, + 17985 => Opcode::VPMOVZXWDZrr, + 17986 => Opcode::VPMOVZXWDZrrk, + 17987 => Opcode::VPMOVZXWDZrrkz, + 17988 => Opcode::VPMOVZXWDrm, + 17989 => Opcode::VPMOVZXWDrr, + 17990 => Opcode::VPMOVZXWQYrm, + 17991 => Opcode::VPMOVZXWQYrr, + 17992 => Opcode::VPMOVZXWQZ128rm, + 17993 => Opcode::VPMOVZXWQZ128rmk, + 17994 => Opcode::VPMOVZXWQZ128rmkz, + 17995 => Opcode::VPMOVZXWQZ128rr, + 17996 => Opcode::VPMOVZXWQZ128rrk, + 17997 => Opcode::VPMOVZXWQZ128rrkz, + 17998 => Opcode::VPMOVZXWQZ256rm, + 17999 => Opcode::VPMOVZXWQZ256rmk, + 18000 => Opcode::VPMOVZXWQZ256rmkz, + 18001 => Opcode::VPMOVZXWQZ256rr, + 18002 => Opcode::VPMOVZXWQZ256rrk, + 18003 => Opcode::VPMOVZXWQZ256rrkz, + 18004 => Opcode::VPMOVZXWQZrm, + 18005 => Opcode::VPMOVZXWQZrmk, + 18006 => Opcode::VPMOVZXWQZrmkz, + 18007 => Opcode::VPMOVZXWQZrr, + 18008 => Opcode::VPMOVZXWQZrrk, + 18009 => Opcode::VPMOVZXWQZrrkz, + 18010 => Opcode::VPMOVZXWQrm, + 18011 => Opcode::VPMOVZXWQrr, + 18012 => Opcode::VPMULDQYrm, + 18013 => Opcode::VPMULDQYrr, + 18014 => Opcode::VPMULDQZ128rm, + 18015 => Opcode::VPMULDQZ128rmb, + 18016 => Opcode::VPMULDQZ128rmbk, + 18017 => Opcode::VPMULDQZ128rmbkz, + 18018 => Opcode::VPMULDQZ128rmk, + 18019 => Opcode::VPMULDQZ128rmkz, + 18020 => Opcode::VPMULDQZ128rr, + 18021 => Opcode::VPMULDQZ128rrk, + 18022 => Opcode::VPMULDQZ128rrkz, + 18023 => Opcode::VPMULDQZ256rm, + 18024 => Opcode::VPMULDQZ256rmb, + 18025 => Opcode::VPMULDQZ256rmbk, + 18026 => Opcode::VPMULDQZ256rmbkz, + 18027 => Opcode::VPMULDQZ256rmk, + 18028 => Opcode::VPMULDQZ256rmkz, + 18029 => Opcode::VPMULDQZ256rr, + 18030 => Opcode::VPMULDQZ256rrk, + 18031 => Opcode::VPMULDQZ256rrkz, + 18032 => Opcode::VPMULDQZrm, + 18033 => Opcode::VPMULDQZrmb, + 18034 => Opcode::VPMULDQZrmbk, + 18035 => Opcode::VPMULDQZrmbkz, + 18036 => Opcode::VPMULDQZrmk, + 18037 => Opcode::VPMULDQZrmkz, + 18038 => Opcode::VPMULDQZrr, + 18039 => Opcode::VPMULDQZrrk, + 18040 => Opcode::VPMULDQZrrkz, + 18041 => Opcode::VPMULDQrm, + 18042 => Opcode::VPMULDQrr, + 18043 => Opcode::VPMULHRSWYrm, + 18044 => Opcode::VPMULHRSWYrr, + 18045 => Opcode::VPMULHRSWZ128rm, + 18046 => Opcode::VPMULHRSWZ128rmk, + 18047 => Opcode::VPMULHRSWZ128rmkz, + 18048 => Opcode::VPMULHRSWZ128rr, + 18049 => Opcode::VPMULHRSWZ128rrk, + 18050 => Opcode::VPMULHRSWZ128rrkz, + 18051 => Opcode::VPMULHRSWZ256rm, + 18052 => Opcode::VPMULHRSWZ256rmk, + 18053 => Opcode::VPMULHRSWZ256rmkz, + 18054 => Opcode::VPMULHRSWZ256rr, + 18055 => Opcode::VPMULHRSWZ256rrk, + 18056 => Opcode::VPMULHRSWZ256rrkz, + 18057 => Opcode::VPMULHRSWZrm, + 18058 => Opcode::VPMULHRSWZrmk, + 18059 => Opcode::VPMULHRSWZrmkz, + 18060 => Opcode::VPMULHRSWZrr, + 18061 => Opcode::VPMULHRSWZrrk, + 18062 => Opcode::VPMULHRSWZrrkz, + 18063 => Opcode::VPMULHRSWrm, + 18064 => Opcode::VPMULHRSWrr, + 18065 => Opcode::VPMULHUWYrm, + 18066 => Opcode::VPMULHUWYrr, + 18067 => Opcode::VPMULHUWZ128rm, + 18068 => Opcode::VPMULHUWZ128rmk, + 18069 => Opcode::VPMULHUWZ128rmkz, + 18070 => Opcode::VPMULHUWZ128rr, + 18071 => Opcode::VPMULHUWZ128rrk, + 18072 => Opcode::VPMULHUWZ128rrkz, + 18073 => Opcode::VPMULHUWZ256rm, + 18074 => Opcode::VPMULHUWZ256rmk, + 18075 => Opcode::VPMULHUWZ256rmkz, + 18076 => Opcode::VPMULHUWZ256rr, + 18077 => Opcode::VPMULHUWZ256rrk, + 18078 => Opcode::VPMULHUWZ256rrkz, + 18079 => Opcode::VPMULHUWZrm, + 18080 => Opcode::VPMULHUWZrmk, + 18081 => Opcode::VPMULHUWZrmkz, + 18082 => Opcode::VPMULHUWZrr, + 18083 => Opcode::VPMULHUWZrrk, + 18084 => Opcode::VPMULHUWZrrkz, + 18085 => Opcode::VPMULHUWrm, + 18086 => Opcode::VPMULHUWrr, + 18087 => Opcode::VPMULHWYrm, + 18088 => Opcode::VPMULHWYrr, + 18089 => Opcode::VPMULHWZ128rm, + 18090 => Opcode::VPMULHWZ128rmk, + 18091 => Opcode::VPMULHWZ128rmkz, + 18092 => Opcode::VPMULHWZ128rr, + 18093 => Opcode::VPMULHWZ128rrk, + 18094 => Opcode::VPMULHWZ128rrkz, + 18095 => Opcode::VPMULHWZ256rm, + 18096 => Opcode::VPMULHWZ256rmk, + 18097 => Opcode::VPMULHWZ256rmkz, + 18098 => Opcode::VPMULHWZ256rr, + 18099 => Opcode::VPMULHWZ256rrk, + 18100 => Opcode::VPMULHWZ256rrkz, + 18101 => Opcode::VPMULHWZrm, + 18102 => Opcode::VPMULHWZrmk, + 18103 => Opcode::VPMULHWZrmkz, + 18104 => Opcode::VPMULHWZrr, + 18105 => Opcode::VPMULHWZrrk, + 18106 => Opcode::VPMULHWZrrkz, + 18107 => Opcode::VPMULHWrm, + 18108 => Opcode::VPMULHWrr, + 18109 => Opcode::VPMULLDYrm, + 18110 => Opcode::VPMULLDYrr, + 18111 => Opcode::VPMULLDZ128rm, + 18112 => Opcode::VPMULLDZ128rmb, + 18113 => Opcode::VPMULLDZ128rmbk, + 18114 => Opcode::VPMULLDZ128rmbkz, + 18115 => Opcode::VPMULLDZ128rmk, + 18116 => Opcode::VPMULLDZ128rmkz, + 18117 => Opcode::VPMULLDZ128rr, + 18118 => Opcode::VPMULLDZ128rrk, + 18119 => Opcode::VPMULLDZ128rrkz, + 18120 => Opcode::VPMULLDZ256rm, + 18121 => Opcode::VPMULLDZ256rmb, + 18122 => Opcode::VPMULLDZ256rmbk, + 18123 => Opcode::VPMULLDZ256rmbkz, + 18124 => Opcode::VPMULLDZ256rmk, + 18125 => Opcode::VPMULLDZ256rmkz, + 18126 => Opcode::VPMULLDZ256rr, + 18127 => Opcode::VPMULLDZ256rrk, + 18128 => Opcode::VPMULLDZ256rrkz, + 18129 => Opcode::VPMULLDZrm, + 18130 => Opcode::VPMULLDZrmb, + 18131 => Opcode::VPMULLDZrmbk, + 18132 => Opcode::VPMULLDZrmbkz, + 18133 => Opcode::VPMULLDZrmk, + 18134 => Opcode::VPMULLDZrmkz, + 18135 => Opcode::VPMULLDZrr, + 18136 => Opcode::VPMULLDZrrk, + 18137 => Opcode::VPMULLDZrrkz, + 18138 => Opcode::VPMULLDrm, + 18139 => Opcode::VPMULLDrr, + 18140 => Opcode::VPMULLQZ128rm, + 18141 => Opcode::VPMULLQZ128rmb, + 18142 => Opcode::VPMULLQZ128rmbk, + 18143 => Opcode::VPMULLQZ128rmbkz, + 18144 => Opcode::VPMULLQZ128rmk, + 18145 => Opcode::VPMULLQZ128rmkz, + 18146 => Opcode::VPMULLQZ128rr, + 18147 => Opcode::VPMULLQZ128rrk, + 18148 => Opcode::VPMULLQZ128rrkz, + 18149 => Opcode::VPMULLQZ256rm, + 18150 => Opcode::VPMULLQZ256rmb, + 18151 => Opcode::VPMULLQZ256rmbk, + 18152 => Opcode::VPMULLQZ256rmbkz, + 18153 => Opcode::VPMULLQZ256rmk, + 18154 => Opcode::VPMULLQZ256rmkz, + 18155 => Opcode::VPMULLQZ256rr, + 18156 => Opcode::VPMULLQZ256rrk, + 18157 => Opcode::VPMULLQZ256rrkz, + 18158 => Opcode::VPMULLQZrm, + 18159 => Opcode::VPMULLQZrmb, + 18160 => Opcode::VPMULLQZrmbk, + 18161 => Opcode::VPMULLQZrmbkz, + 18162 => Opcode::VPMULLQZrmk, + 18163 => Opcode::VPMULLQZrmkz, + 18164 => Opcode::VPMULLQZrr, + 18165 => Opcode::VPMULLQZrrk, + 18166 => Opcode::VPMULLQZrrkz, + 18167 => Opcode::VPMULLWYrm, + 18168 => Opcode::VPMULLWYrr, + 18169 => Opcode::VPMULLWZ128rm, + 18170 => Opcode::VPMULLWZ128rmk, + 18171 => Opcode::VPMULLWZ128rmkz, + 18172 => Opcode::VPMULLWZ128rr, + 18173 => Opcode::VPMULLWZ128rrk, + 18174 => Opcode::VPMULLWZ128rrkz, + 18175 => Opcode::VPMULLWZ256rm, + 18176 => Opcode::VPMULLWZ256rmk, + 18177 => Opcode::VPMULLWZ256rmkz, + 18178 => Opcode::VPMULLWZ256rr, + 18179 => Opcode::VPMULLWZ256rrk, + 18180 => Opcode::VPMULLWZ256rrkz, + 18181 => Opcode::VPMULLWZrm, + 18182 => Opcode::VPMULLWZrmk, + 18183 => Opcode::VPMULLWZrmkz, + 18184 => Opcode::VPMULLWZrr, + 18185 => Opcode::VPMULLWZrrk, + 18186 => Opcode::VPMULLWZrrkz, + 18187 => Opcode::VPMULLWrm, + 18188 => Opcode::VPMULLWrr, + 18189 => Opcode::VPMULTISHIFTQBZ128rm, + 18190 => Opcode::VPMULTISHIFTQBZ128rmb, + 18191 => Opcode::VPMULTISHIFTQBZ128rmbk, + 18192 => Opcode::VPMULTISHIFTQBZ128rmbkz, + 18193 => Opcode::VPMULTISHIFTQBZ128rmk, + 18194 => Opcode::VPMULTISHIFTQBZ128rmkz, + 18195 => Opcode::VPMULTISHIFTQBZ128rr, + 18196 => Opcode::VPMULTISHIFTQBZ128rrk, + 18197 => Opcode::VPMULTISHIFTQBZ128rrkz, + 18198 => Opcode::VPMULTISHIFTQBZ256rm, + 18199 => Opcode::VPMULTISHIFTQBZ256rmb, + 18200 => Opcode::VPMULTISHIFTQBZ256rmbk, + 18201 => Opcode::VPMULTISHIFTQBZ256rmbkz, + 18202 => Opcode::VPMULTISHIFTQBZ256rmk, + 18203 => Opcode::VPMULTISHIFTQBZ256rmkz, + 18204 => Opcode::VPMULTISHIFTQBZ256rr, + 18205 => Opcode::VPMULTISHIFTQBZ256rrk, + 18206 => Opcode::VPMULTISHIFTQBZ256rrkz, + 18207 => Opcode::VPMULTISHIFTQBZrm, + 18208 => Opcode::VPMULTISHIFTQBZrmb, + 18209 => Opcode::VPMULTISHIFTQBZrmbk, + 18210 => Opcode::VPMULTISHIFTQBZrmbkz, + 18211 => Opcode::VPMULTISHIFTQBZrmk, + 18212 => Opcode::VPMULTISHIFTQBZrmkz, + 18213 => Opcode::VPMULTISHIFTQBZrr, + 18214 => Opcode::VPMULTISHIFTQBZrrk, + 18215 => Opcode::VPMULTISHIFTQBZrrkz, + 18216 => Opcode::VPMULUDQYrm, + 18217 => Opcode::VPMULUDQYrr, + 18218 => Opcode::VPMULUDQZ128rm, + 18219 => Opcode::VPMULUDQZ128rmb, + 18220 => Opcode::VPMULUDQZ128rmbk, + 18221 => Opcode::VPMULUDQZ128rmbkz, + 18222 => Opcode::VPMULUDQZ128rmk, + 18223 => Opcode::VPMULUDQZ128rmkz, + 18224 => Opcode::VPMULUDQZ128rr, + 18225 => Opcode::VPMULUDQZ128rrk, + 18226 => Opcode::VPMULUDQZ128rrkz, + 18227 => Opcode::VPMULUDQZ256rm, + 18228 => Opcode::VPMULUDQZ256rmb, + 18229 => Opcode::VPMULUDQZ256rmbk, + 18230 => Opcode::VPMULUDQZ256rmbkz, + 18231 => Opcode::VPMULUDQZ256rmk, + 18232 => Opcode::VPMULUDQZ256rmkz, + 18233 => Opcode::VPMULUDQZ256rr, + 18234 => Opcode::VPMULUDQZ256rrk, + 18235 => Opcode::VPMULUDQZ256rrkz, + 18236 => Opcode::VPMULUDQZrm, + 18237 => Opcode::VPMULUDQZrmb, + 18238 => Opcode::VPMULUDQZrmbk, + 18239 => Opcode::VPMULUDQZrmbkz, + 18240 => Opcode::VPMULUDQZrmk, + 18241 => Opcode::VPMULUDQZrmkz, + 18242 => Opcode::VPMULUDQZrr, + 18243 => Opcode::VPMULUDQZrrk, + 18244 => Opcode::VPMULUDQZrrkz, + 18245 => Opcode::VPMULUDQrm, + 18246 => Opcode::VPMULUDQrr, + 18247 => Opcode::VPOPCNTBZ128rm, + 18248 => Opcode::VPOPCNTBZ128rmk, + 18249 => Opcode::VPOPCNTBZ128rmkz, + 18250 => Opcode::VPOPCNTBZ128rr, + 18251 => Opcode::VPOPCNTBZ128rrk, + 18252 => Opcode::VPOPCNTBZ128rrkz, + 18253 => Opcode::VPOPCNTBZ256rm, + 18254 => Opcode::VPOPCNTBZ256rmk, + 18255 => Opcode::VPOPCNTBZ256rmkz, + 18256 => Opcode::VPOPCNTBZ256rr, + 18257 => Opcode::VPOPCNTBZ256rrk, + 18258 => Opcode::VPOPCNTBZ256rrkz, + 18259 => Opcode::VPOPCNTBZrm, + 18260 => Opcode::VPOPCNTBZrmk, + 18261 => Opcode::VPOPCNTBZrmkz, + 18262 => Opcode::VPOPCNTBZrr, + 18263 => Opcode::VPOPCNTBZrrk, + 18264 => Opcode::VPOPCNTBZrrkz, + 18265 => Opcode::VPOPCNTDZ128rm, + 18266 => Opcode::VPOPCNTDZ128rmb, + 18267 => Opcode::VPOPCNTDZ128rmbk, + 18268 => Opcode::VPOPCNTDZ128rmbkz, + 18269 => Opcode::VPOPCNTDZ128rmk, + 18270 => Opcode::VPOPCNTDZ128rmkz, + 18271 => Opcode::VPOPCNTDZ128rr, + 18272 => Opcode::VPOPCNTDZ128rrk, + 18273 => Opcode::VPOPCNTDZ128rrkz, + 18274 => Opcode::VPOPCNTDZ256rm, + 18275 => Opcode::VPOPCNTDZ256rmb, + 18276 => Opcode::VPOPCNTDZ256rmbk, + 18277 => Opcode::VPOPCNTDZ256rmbkz, + 18278 => Opcode::VPOPCNTDZ256rmk, + 18279 => Opcode::VPOPCNTDZ256rmkz, + 18280 => Opcode::VPOPCNTDZ256rr, + 18281 => Opcode::VPOPCNTDZ256rrk, + 18282 => Opcode::VPOPCNTDZ256rrkz, + 18283 => Opcode::VPOPCNTDZrm, + 18284 => Opcode::VPOPCNTDZrmb, + 18285 => Opcode::VPOPCNTDZrmbk, + 18286 => Opcode::VPOPCNTDZrmbkz, + 18287 => Opcode::VPOPCNTDZrmk, + 18288 => Opcode::VPOPCNTDZrmkz, + 18289 => Opcode::VPOPCNTDZrr, + 18290 => Opcode::VPOPCNTDZrrk, + 18291 => Opcode::VPOPCNTDZrrkz, + 18292 => Opcode::VPOPCNTQZ128rm, + 18293 => Opcode::VPOPCNTQZ128rmb, + 18294 => Opcode::VPOPCNTQZ128rmbk, + 18295 => Opcode::VPOPCNTQZ128rmbkz, + 18296 => Opcode::VPOPCNTQZ128rmk, + 18297 => Opcode::VPOPCNTQZ128rmkz, + 18298 => Opcode::VPOPCNTQZ128rr, + 18299 => Opcode::VPOPCNTQZ128rrk, + 18300 => Opcode::VPOPCNTQZ128rrkz, + 18301 => Opcode::VPOPCNTQZ256rm, + 18302 => Opcode::VPOPCNTQZ256rmb, + 18303 => Opcode::VPOPCNTQZ256rmbk, + 18304 => Opcode::VPOPCNTQZ256rmbkz, + 18305 => Opcode::VPOPCNTQZ256rmk, + 18306 => Opcode::VPOPCNTQZ256rmkz, + 18307 => Opcode::VPOPCNTQZ256rr, + 18308 => Opcode::VPOPCNTQZ256rrk, + 18309 => Opcode::VPOPCNTQZ256rrkz, + 18310 => Opcode::VPOPCNTQZrm, + 18311 => Opcode::VPOPCNTQZrmb, + 18312 => Opcode::VPOPCNTQZrmbk, + 18313 => Opcode::VPOPCNTQZrmbkz, + 18314 => Opcode::VPOPCNTQZrmk, + 18315 => Opcode::VPOPCNTQZrmkz, + 18316 => Opcode::VPOPCNTQZrr, + 18317 => Opcode::VPOPCNTQZrrk, + 18318 => Opcode::VPOPCNTQZrrkz, + 18319 => Opcode::VPOPCNTWZ128rm, + 18320 => Opcode::VPOPCNTWZ128rmk, + 18321 => Opcode::VPOPCNTWZ128rmkz, + 18322 => Opcode::VPOPCNTWZ128rr, + 18323 => Opcode::VPOPCNTWZ128rrk, + 18324 => Opcode::VPOPCNTWZ128rrkz, + 18325 => Opcode::VPOPCNTWZ256rm, + 18326 => Opcode::VPOPCNTWZ256rmk, + 18327 => Opcode::VPOPCNTWZ256rmkz, + 18328 => Opcode::VPOPCNTWZ256rr, + 18329 => Opcode::VPOPCNTWZ256rrk, + 18330 => Opcode::VPOPCNTWZ256rrkz, + 18331 => Opcode::VPOPCNTWZrm, + 18332 => Opcode::VPOPCNTWZrmk, + 18333 => Opcode::VPOPCNTWZrmkz, + 18334 => Opcode::VPOPCNTWZrr, + 18335 => Opcode::VPOPCNTWZrrk, + 18336 => Opcode::VPOPCNTWZrrkz, + 18337 => Opcode::VPORDZ128rm, + 18338 => Opcode::VPORDZ128rmb, + 18339 => Opcode::VPORDZ128rmbk, + 18340 => Opcode::VPORDZ128rmbkz, + 18341 => Opcode::VPORDZ128rmk, + 18342 => Opcode::VPORDZ128rmkz, + 18343 => Opcode::VPORDZ128rr, + 18344 => Opcode::VPORDZ128rrk, + 18345 => Opcode::VPORDZ128rrkz, + 18346 => Opcode::VPORDZ256rm, + 18347 => Opcode::VPORDZ256rmb, + 18348 => Opcode::VPORDZ256rmbk, + 18349 => Opcode::VPORDZ256rmbkz, + 18350 => Opcode::VPORDZ256rmk, + 18351 => Opcode::VPORDZ256rmkz, + 18352 => Opcode::VPORDZ256rr, + 18353 => Opcode::VPORDZ256rrk, + 18354 => Opcode::VPORDZ256rrkz, + 18355 => Opcode::VPORDZrm, + 18356 => Opcode::VPORDZrmb, + 18357 => Opcode::VPORDZrmbk, + 18358 => Opcode::VPORDZrmbkz, + 18359 => Opcode::VPORDZrmk, + 18360 => Opcode::VPORDZrmkz, + 18361 => Opcode::VPORDZrr, + 18362 => Opcode::VPORDZrrk, + 18363 => Opcode::VPORDZrrkz, + 18364 => Opcode::VPORQZ128rm, + 18365 => Opcode::VPORQZ128rmb, + 18366 => Opcode::VPORQZ128rmbk, + 18367 => Opcode::VPORQZ128rmbkz, + 18368 => Opcode::VPORQZ128rmk, + 18369 => Opcode::VPORQZ128rmkz, + 18370 => Opcode::VPORQZ128rr, + 18371 => Opcode::VPORQZ128rrk, + 18372 => Opcode::VPORQZ128rrkz, + 18373 => Opcode::VPORQZ256rm, + 18374 => Opcode::VPORQZ256rmb, + 18375 => Opcode::VPORQZ256rmbk, + 18376 => Opcode::VPORQZ256rmbkz, + 18377 => Opcode::VPORQZ256rmk, + 18378 => Opcode::VPORQZ256rmkz, + 18379 => Opcode::VPORQZ256rr, + 18380 => Opcode::VPORQZ256rrk, + 18381 => Opcode::VPORQZ256rrkz, + 18382 => Opcode::VPORQZrm, + 18383 => Opcode::VPORQZrmb, + 18384 => Opcode::VPORQZrmbk, + 18385 => Opcode::VPORQZrmbkz, + 18386 => Opcode::VPORQZrmk, + 18387 => Opcode::VPORQZrmkz, + 18388 => Opcode::VPORQZrr, + 18389 => Opcode::VPORQZrrk, + 18390 => Opcode::VPORQZrrkz, + 18391 => Opcode::VPORYrm, + 18392 => Opcode::VPORYrr, + 18393 => Opcode::VPORrm, + 18394 => Opcode::VPORrr, + 18395 => Opcode::VPPERMrmr, + 18396 => Opcode::VPPERMrrm, + 18397 => Opcode::VPPERMrrr, + 18398 => Opcode::VPPERMrrr_REV, + 18399 => Opcode::VPROLDZ128mbi, + 18400 => Opcode::VPROLDZ128mbik, + 18401 => Opcode::VPROLDZ128mbikz, + 18402 => Opcode::VPROLDZ128mi, + 18403 => Opcode::VPROLDZ128mik, + 18404 => Opcode::VPROLDZ128mikz, + 18405 => Opcode::VPROLDZ128ri, + 18406 => Opcode::VPROLDZ128rik, + 18407 => Opcode::VPROLDZ128rikz, + 18408 => Opcode::VPROLDZ256mbi, + 18409 => Opcode::VPROLDZ256mbik, + 18410 => Opcode::VPROLDZ256mbikz, + 18411 => Opcode::VPROLDZ256mi, + 18412 => Opcode::VPROLDZ256mik, + 18413 => Opcode::VPROLDZ256mikz, + 18414 => Opcode::VPROLDZ256ri, + 18415 => Opcode::VPROLDZ256rik, + 18416 => Opcode::VPROLDZ256rikz, + 18417 => Opcode::VPROLDZmbi, + 18418 => Opcode::VPROLDZmbik, + 18419 => Opcode::VPROLDZmbikz, + 18420 => Opcode::VPROLDZmi, + 18421 => Opcode::VPROLDZmik, + 18422 => Opcode::VPROLDZmikz, + 18423 => Opcode::VPROLDZri, + 18424 => Opcode::VPROLDZrik, + 18425 => Opcode::VPROLDZrikz, + 18426 => Opcode::VPROLQZ128mbi, + 18427 => Opcode::VPROLQZ128mbik, + 18428 => Opcode::VPROLQZ128mbikz, + 18429 => Opcode::VPROLQZ128mi, + 18430 => Opcode::VPROLQZ128mik, + 18431 => Opcode::VPROLQZ128mikz, + 18432 => Opcode::VPROLQZ128ri, + 18433 => Opcode::VPROLQZ128rik, + 18434 => Opcode::VPROLQZ128rikz, + 18435 => Opcode::VPROLQZ256mbi, + 18436 => Opcode::VPROLQZ256mbik, + 18437 => Opcode::VPROLQZ256mbikz, + 18438 => Opcode::VPROLQZ256mi, + 18439 => Opcode::VPROLQZ256mik, + 18440 => Opcode::VPROLQZ256mikz, + 18441 => Opcode::VPROLQZ256ri, + 18442 => Opcode::VPROLQZ256rik, + 18443 => Opcode::VPROLQZ256rikz, + 18444 => Opcode::VPROLQZmbi, + 18445 => Opcode::VPROLQZmbik, + 18446 => Opcode::VPROLQZmbikz, + 18447 => Opcode::VPROLQZmi, + 18448 => Opcode::VPROLQZmik, + 18449 => Opcode::VPROLQZmikz, + 18450 => Opcode::VPROLQZri, + 18451 => Opcode::VPROLQZrik, + 18452 => Opcode::VPROLQZrikz, + 18453 => Opcode::VPROLVDZ128rm, + 18454 => Opcode::VPROLVDZ128rmb, + 18455 => Opcode::VPROLVDZ128rmbk, + 18456 => Opcode::VPROLVDZ128rmbkz, + 18457 => Opcode::VPROLVDZ128rmk, + 18458 => Opcode::VPROLVDZ128rmkz, + 18459 => Opcode::VPROLVDZ128rr, + 18460 => Opcode::VPROLVDZ128rrk, + 18461 => Opcode::VPROLVDZ128rrkz, + 18462 => Opcode::VPROLVDZ256rm, + 18463 => Opcode::VPROLVDZ256rmb, + 18464 => Opcode::VPROLVDZ256rmbk, + 18465 => Opcode::VPROLVDZ256rmbkz, + 18466 => Opcode::VPROLVDZ256rmk, + 18467 => Opcode::VPROLVDZ256rmkz, + 18468 => Opcode::VPROLVDZ256rr, + 18469 => Opcode::VPROLVDZ256rrk, + 18470 => Opcode::VPROLVDZ256rrkz, + 18471 => Opcode::VPROLVDZrm, + 18472 => Opcode::VPROLVDZrmb, + 18473 => Opcode::VPROLVDZrmbk, + 18474 => Opcode::VPROLVDZrmbkz, + 18475 => Opcode::VPROLVDZrmk, + 18476 => Opcode::VPROLVDZrmkz, + 18477 => Opcode::VPROLVDZrr, + 18478 => Opcode::VPROLVDZrrk, + 18479 => Opcode::VPROLVDZrrkz, + 18480 => Opcode::VPROLVQZ128rm, + 18481 => Opcode::VPROLVQZ128rmb, + 18482 => Opcode::VPROLVQZ128rmbk, + 18483 => Opcode::VPROLVQZ128rmbkz, + 18484 => Opcode::VPROLVQZ128rmk, + 18485 => Opcode::VPROLVQZ128rmkz, + 18486 => Opcode::VPROLVQZ128rr, + 18487 => Opcode::VPROLVQZ128rrk, + 18488 => Opcode::VPROLVQZ128rrkz, + 18489 => Opcode::VPROLVQZ256rm, + 18490 => Opcode::VPROLVQZ256rmb, + 18491 => Opcode::VPROLVQZ256rmbk, + 18492 => Opcode::VPROLVQZ256rmbkz, + 18493 => Opcode::VPROLVQZ256rmk, + 18494 => Opcode::VPROLVQZ256rmkz, + 18495 => Opcode::VPROLVQZ256rr, + 18496 => Opcode::VPROLVQZ256rrk, + 18497 => Opcode::VPROLVQZ256rrkz, + 18498 => Opcode::VPROLVQZrm, + 18499 => Opcode::VPROLVQZrmb, + 18500 => Opcode::VPROLVQZrmbk, + 18501 => Opcode::VPROLVQZrmbkz, + 18502 => Opcode::VPROLVQZrmk, + 18503 => Opcode::VPROLVQZrmkz, + 18504 => Opcode::VPROLVQZrr, + 18505 => Opcode::VPROLVQZrrk, + 18506 => Opcode::VPROLVQZrrkz, + 18507 => Opcode::VPRORDZ128mbi, + 18508 => Opcode::VPRORDZ128mbik, + 18509 => Opcode::VPRORDZ128mbikz, + 18510 => Opcode::VPRORDZ128mi, + 18511 => Opcode::VPRORDZ128mik, + 18512 => Opcode::VPRORDZ128mikz, + 18513 => Opcode::VPRORDZ128ri, + 18514 => Opcode::VPRORDZ128rik, + 18515 => Opcode::VPRORDZ128rikz, + 18516 => Opcode::VPRORDZ256mbi, + 18517 => Opcode::VPRORDZ256mbik, + 18518 => Opcode::VPRORDZ256mbikz, + 18519 => Opcode::VPRORDZ256mi, + 18520 => Opcode::VPRORDZ256mik, + 18521 => Opcode::VPRORDZ256mikz, + 18522 => Opcode::VPRORDZ256ri, + 18523 => Opcode::VPRORDZ256rik, + 18524 => Opcode::VPRORDZ256rikz, + 18525 => Opcode::VPRORDZmbi, + 18526 => Opcode::VPRORDZmbik, + 18527 => Opcode::VPRORDZmbikz, + 18528 => Opcode::VPRORDZmi, + 18529 => Opcode::VPRORDZmik, + 18530 => Opcode::VPRORDZmikz, + 18531 => Opcode::VPRORDZri, + 18532 => Opcode::VPRORDZrik, + 18533 => Opcode::VPRORDZrikz, + 18534 => Opcode::VPRORQZ128mbi, + 18535 => Opcode::VPRORQZ128mbik, + 18536 => Opcode::VPRORQZ128mbikz, + 18537 => Opcode::VPRORQZ128mi, + 18538 => Opcode::VPRORQZ128mik, + 18539 => Opcode::VPRORQZ128mikz, + 18540 => Opcode::VPRORQZ128ri, + 18541 => Opcode::VPRORQZ128rik, + 18542 => Opcode::VPRORQZ128rikz, + 18543 => Opcode::VPRORQZ256mbi, + 18544 => Opcode::VPRORQZ256mbik, + 18545 => Opcode::VPRORQZ256mbikz, + 18546 => Opcode::VPRORQZ256mi, + 18547 => Opcode::VPRORQZ256mik, + 18548 => Opcode::VPRORQZ256mikz, + 18549 => Opcode::VPRORQZ256ri, + 18550 => Opcode::VPRORQZ256rik, + 18551 => Opcode::VPRORQZ256rikz, + 18552 => Opcode::VPRORQZmbi, + 18553 => Opcode::VPRORQZmbik, + 18554 => Opcode::VPRORQZmbikz, + 18555 => Opcode::VPRORQZmi, + 18556 => Opcode::VPRORQZmik, + 18557 => Opcode::VPRORQZmikz, + 18558 => Opcode::VPRORQZri, + 18559 => Opcode::VPRORQZrik, + 18560 => Opcode::VPRORQZrikz, + 18561 => Opcode::VPRORVDZ128rm, + 18562 => Opcode::VPRORVDZ128rmb, + 18563 => Opcode::VPRORVDZ128rmbk, + 18564 => Opcode::VPRORVDZ128rmbkz, + 18565 => Opcode::VPRORVDZ128rmk, + 18566 => Opcode::VPRORVDZ128rmkz, + 18567 => Opcode::VPRORVDZ128rr, + 18568 => Opcode::VPRORVDZ128rrk, + 18569 => Opcode::VPRORVDZ128rrkz, + 18570 => Opcode::VPRORVDZ256rm, + 18571 => Opcode::VPRORVDZ256rmb, + 18572 => Opcode::VPRORVDZ256rmbk, + 18573 => Opcode::VPRORVDZ256rmbkz, + 18574 => Opcode::VPRORVDZ256rmk, + 18575 => Opcode::VPRORVDZ256rmkz, + 18576 => Opcode::VPRORVDZ256rr, + 18577 => Opcode::VPRORVDZ256rrk, + 18578 => Opcode::VPRORVDZ256rrkz, + 18579 => Opcode::VPRORVDZrm, + 18580 => Opcode::VPRORVDZrmb, + 18581 => Opcode::VPRORVDZrmbk, + 18582 => Opcode::VPRORVDZrmbkz, + 18583 => Opcode::VPRORVDZrmk, + 18584 => Opcode::VPRORVDZrmkz, + 18585 => Opcode::VPRORVDZrr, + 18586 => Opcode::VPRORVDZrrk, + 18587 => Opcode::VPRORVDZrrkz, + 18588 => Opcode::VPRORVQZ128rm, + 18589 => Opcode::VPRORVQZ128rmb, + 18590 => Opcode::VPRORVQZ128rmbk, + 18591 => Opcode::VPRORVQZ128rmbkz, + 18592 => Opcode::VPRORVQZ128rmk, + 18593 => Opcode::VPRORVQZ128rmkz, + 18594 => Opcode::VPRORVQZ128rr, + 18595 => Opcode::VPRORVQZ128rrk, + 18596 => Opcode::VPRORVQZ128rrkz, + 18597 => Opcode::VPRORVQZ256rm, + 18598 => Opcode::VPRORVQZ256rmb, + 18599 => Opcode::VPRORVQZ256rmbk, + 18600 => Opcode::VPRORVQZ256rmbkz, + 18601 => Opcode::VPRORVQZ256rmk, + 18602 => Opcode::VPRORVQZ256rmkz, + 18603 => Opcode::VPRORVQZ256rr, + 18604 => Opcode::VPRORVQZ256rrk, + 18605 => Opcode::VPRORVQZ256rrkz, + 18606 => Opcode::VPRORVQZrm, + 18607 => Opcode::VPRORVQZrmb, + 18608 => Opcode::VPRORVQZrmbk, + 18609 => Opcode::VPRORVQZrmbkz, + 18610 => Opcode::VPRORVQZrmk, + 18611 => Opcode::VPRORVQZrmkz, + 18612 => Opcode::VPRORVQZrr, + 18613 => Opcode::VPRORVQZrrk, + 18614 => Opcode::VPRORVQZrrkz, + 18615 => Opcode::VPROTBmi, + 18616 => Opcode::VPROTBmr, + 18617 => Opcode::VPROTBri, + 18618 => Opcode::VPROTBrm, + 18619 => Opcode::VPROTBrr, + 18620 => Opcode::VPROTBrr_REV, + 18621 => Opcode::VPROTDmi, + 18622 => Opcode::VPROTDmr, + 18623 => Opcode::VPROTDri, + 18624 => Opcode::VPROTDrm, + 18625 => Opcode::VPROTDrr, + 18626 => Opcode::VPROTDrr_REV, + 18627 => Opcode::VPROTQmi, + 18628 => Opcode::VPROTQmr, + 18629 => Opcode::VPROTQri, + 18630 => Opcode::VPROTQrm, + 18631 => Opcode::VPROTQrr, + 18632 => Opcode::VPROTQrr_REV, + 18633 => Opcode::VPROTWmi, + 18634 => Opcode::VPROTWmr, + 18635 => Opcode::VPROTWri, + 18636 => Opcode::VPROTWrm, + 18637 => Opcode::VPROTWrr, + 18638 => Opcode::VPROTWrr_REV, + 18639 => Opcode::VPSADBWYrm, + 18640 => Opcode::VPSADBWYrr, + 18641 => Opcode::VPSADBWZ128rm, + 18642 => Opcode::VPSADBWZ128rr, + 18643 => Opcode::VPSADBWZ256rm, + 18644 => Opcode::VPSADBWZ256rr, + 18645 => Opcode::VPSADBWZrm, + 18646 => Opcode::VPSADBWZrr, + 18647 => Opcode::VPSADBWrm, + 18648 => Opcode::VPSADBWrr, + 18649 => Opcode::VPSCATTERDDZ128mr, + 18650 => Opcode::VPSCATTERDDZ256mr, + 18651 => Opcode::VPSCATTERDDZmr, + 18652 => Opcode::VPSCATTERDQZ128mr, + 18653 => Opcode::VPSCATTERDQZ256mr, + 18654 => Opcode::VPSCATTERDQZmr, + 18655 => Opcode::VPSCATTERQDZ128mr, + 18656 => Opcode::VPSCATTERQDZ256mr, + 18657 => Opcode::VPSCATTERQDZmr, + 18658 => Opcode::VPSCATTERQQZ128mr, + 18659 => Opcode::VPSCATTERQQZ256mr, + 18660 => Opcode::VPSCATTERQQZmr, + 18661 => Opcode::VPSHABmr, + 18662 => Opcode::VPSHABrm, + 18663 => Opcode::VPSHABrr, + 18664 => Opcode::VPSHABrr_REV, + 18665 => Opcode::VPSHADmr, + 18666 => Opcode::VPSHADrm, + 18667 => Opcode::VPSHADrr, + 18668 => Opcode::VPSHADrr_REV, + 18669 => Opcode::VPSHAQmr, + 18670 => Opcode::VPSHAQrm, + 18671 => Opcode::VPSHAQrr, + 18672 => Opcode::VPSHAQrr_REV, + 18673 => Opcode::VPSHAWmr, + 18674 => Opcode::VPSHAWrm, + 18675 => Opcode::VPSHAWrr, + 18676 => Opcode::VPSHAWrr_REV, + 18677 => Opcode::VPSHLBmr, + 18678 => Opcode::VPSHLBrm, + 18679 => Opcode::VPSHLBrr, + 18680 => Opcode::VPSHLBrr_REV, + 18681 => Opcode::VPSHLDDZ128rmbi, + 18682 => Opcode::VPSHLDDZ128rmbik, + 18683 => Opcode::VPSHLDDZ128rmbikz, + 18684 => Opcode::VPSHLDDZ128rmi, + 18685 => Opcode::VPSHLDDZ128rmik, + 18686 => Opcode::VPSHLDDZ128rmikz, + 18687 => Opcode::VPSHLDDZ128rri, + 18688 => Opcode::VPSHLDDZ128rrik, + 18689 => Opcode::VPSHLDDZ128rrikz, + 18690 => Opcode::VPSHLDDZ256rmbi, + 18691 => Opcode::VPSHLDDZ256rmbik, + 18692 => Opcode::VPSHLDDZ256rmbikz, + 18693 => Opcode::VPSHLDDZ256rmi, + 18694 => Opcode::VPSHLDDZ256rmik, + 18695 => Opcode::VPSHLDDZ256rmikz, + 18696 => Opcode::VPSHLDDZ256rri, + 18697 => Opcode::VPSHLDDZ256rrik, + 18698 => Opcode::VPSHLDDZ256rrikz, + 18699 => Opcode::VPSHLDDZrmbi, + 18700 => Opcode::VPSHLDDZrmbik, + 18701 => Opcode::VPSHLDDZrmbikz, + 18702 => Opcode::VPSHLDDZrmi, + 18703 => Opcode::VPSHLDDZrmik, + 18704 => Opcode::VPSHLDDZrmikz, + 18705 => Opcode::VPSHLDDZrri, + 18706 => Opcode::VPSHLDDZrrik, + 18707 => Opcode::VPSHLDDZrrikz, + 18708 => Opcode::VPSHLDQZ128rmbi, + 18709 => Opcode::VPSHLDQZ128rmbik, + 18710 => Opcode::VPSHLDQZ128rmbikz, + 18711 => Opcode::VPSHLDQZ128rmi, + 18712 => Opcode::VPSHLDQZ128rmik, + 18713 => Opcode::VPSHLDQZ128rmikz, + 18714 => Opcode::VPSHLDQZ128rri, + 18715 => Opcode::VPSHLDQZ128rrik, + 18716 => Opcode::VPSHLDQZ128rrikz, + 18717 => Opcode::VPSHLDQZ256rmbi, + 18718 => Opcode::VPSHLDQZ256rmbik, + 18719 => Opcode::VPSHLDQZ256rmbikz, + 18720 => Opcode::VPSHLDQZ256rmi, + 18721 => Opcode::VPSHLDQZ256rmik, + 18722 => Opcode::VPSHLDQZ256rmikz, + 18723 => Opcode::VPSHLDQZ256rri, + 18724 => Opcode::VPSHLDQZ256rrik, + 18725 => Opcode::VPSHLDQZ256rrikz, + 18726 => Opcode::VPSHLDQZrmbi, + 18727 => Opcode::VPSHLDQZrmbik, + 18728 => Opcode::VPSHLDQZrmbikz, + 18729 => Opcode::VPSHLDQZrmi, + 18730 => Opcode::VPSHLDQZrmik, + 18731 => Opcode::VPSHLDQZrmikz, + 18732 => Opcode::VPSHLDQZrri, + 18733 => Opcode::VPSHLDQZrrik, + 18734 => Opcode::VPSHLDQZrrikz, + 18735 => Opcode::VPSHLDVDZ128m, + 18736 => Opcode::VPSHLDVDZ128mb, + 18737 => Opcode::VPSHLDVDZ128mbk, + 18738 => Opcode::VPSHLDVDZ128mbkz, + 18739 => Opcode::VPSHLDVDZ128mk, + 18740 => Opcode::VPSHLDVDZ128mkz, + 18741 => Opcode::VPSHLDVDZ128r, + 18742 => Opcode::VPSHLDVDZ128rk, + 18743 => Opcode::VPSHLDVDZ128rkz, + 18744 => Opcode::VPSHLDVDZ256m, + 18745 => Opcode::VPSHLDVDZ256mb, + 18746 => Opcode::VPSHLDVDZ256mbk, + 18747 => Opcode::VPSHLDVDZ256mbkz, + 18748 => Opcode::VPSHLDVDZ256mk, + 18749 => Opcode::VPSHLDVDZ256mkz, + 18750 => Opcode::VPSHLDVDZ256r, + 18751 => Opcode::VPSHLDVDZ256rk, + 18752 => Opcode::VPSHLDVDZ256rkz, + 18753 => Opcode::VPSHLDVDZm, + 18754 => Opcode::VPSHLDVDZmb, + 18755 => Opcode::VPSHLDVDZmbk, + 18756 => Opcode::VPSHLDVDZmbkz, + 18757 => Opcode::VPSHLDVDZmk, + 18758 => Opcode::VPSHLDVDZmkz, + 18759 => Opcode::VPSHLDVDZr, + 18760 => Opcode::VPSHLDVDZrk, + 18761 => Opcode::VPSHLDVDZrkz, + 18762 => Opcode::VPSHLDVQZ128m, + 18763 => Opcode::VPSHLDVQZ128mb, + 18764 => Opcode::VPSHLDVQZ128mbk, + 18765 => Opcode::VPSHLDVQZ128mbkz, + 18766 => Opcode::VPSHLDVQZ128mk, + 18767 => Opcode::VPSHLDVQZ128mkz, + 18768 => Opcode::VPSHLDVQZ128r, + 18769 => Opcode::VPSHLDVQZ128rk, + 18770 => Opcode::VPSHLDVQZ128rkz, + 18771 => Opcode::VPSHLDVQZ256m, + 18772 => Opcode::VPSHLDVQZ256mb, + 18773 => Opcode::VPSHLDVQZ256mbk, + 18774 => Opcode::VPSHLDVQZ256mbkz, + 18775 => Opcode::VPSHLDVQZ256mk, + 18776 => Opcode::VPSHLDVQZ256mkz, + 18777 => Opcode::VPSHLDVQZ256r, + 18778 => Opcode::VPSHLDVQZ256rk, + 18779 => Opcode::VPSHLDVQZ256rkz, + 18780 => Opcode::VPSHLDVQZm, + 18781 => Opcode::VPSHLDVQZmb, + 18782 => Opcode::VPSHLDVQZmbk, + 18783 => Opcode::VPSHLDVQZmbkz, + 18784 => Opcode::VPSHLDVQZmk, + 18785 => Opcode::VPSHLDVQZmkz, + 18786 => Opcode::VPSHLDVQZr, + 18787 => Opcode::VPSHLDVQZrk, + 18788 => Opcode::VPSHLDVQZrkz, + 18789 => Opcode::VPSHLDVWZ128m, + 18790 => Opcode::VPSHLDVWZ128mk, + 18791 => Opcode::VPSHLDVWZ128mkz, + 18792 => Opcode::VPSHLDVWZ128r, + 18793 => Opcode::VPSHLDVWZ128rk, + 18794 => Opcode::VPSHLDVWZ128rkz, + 18795 => Opcode::VPSHLDVWZ256m, + 18796 => Opcode::VPSHLDVWZ256mk, + 18797 => Opcode::VPSHLDVWZ256mkz, + 18798 => Opcode::VPSHLDVWZ256r, + 18799 => Opcode::VPSHLDVWZ256rk, + 18800 => Opcode::VPSHLDVWZ256rkz, + 18801 => Opcode::VPSHLDVWZm, + 18802 => Opcode::VPSHLDVWZmk, + 18803 => Opcode::VPSHLDVWZmkz, + 18804 => Opcode::VPSHLDVWZr, + 18805 => Opcode::VPSHLDVWZrk, + 18806 => Opcode::VPSHLDVWZrkz, + 18807 => Opcode::VPSHLDWZ128rmi, + 18808 => Opcode::VPSHLDWZ128rmik, + 18809 => Opcode::VPSHLDWZ128rmikz, + 18810 => Opcode::VPSHLDWZ128rri, + 18811 => Opcode::VPSHLDWZ128rrik, + 18812 => Opcode::VPSHLDWZ128rrikz, + 18813 => Opcode::VPSHLDWZ256rmi, + 18814 => Opcode::VPSHLDWZ256rmik, + 18815 => Opcode::VPSHLDWZ256rmikz, + 18816 => Opcode::VPSHLDWZ256rri, + 18817 => Opcode::VPSHLDWZ256rrik, + 18818 => Opcode::VPSHLDWZ256rrikz, + 18819 => Opcode::VPSHLDWZrmi, + 18820 => Opcode::VPSHLDWZrmik, + 18821 => Opcode::VPSHLDWZrmikz, + 18822 => Opcode::VPSHLDWZrri, + 18823 => Opcode::VPSHLDWZrrik, + 18824 => Opcode::VPSHLDWZrrikz, + 18825 => Opcode::VPSHLDmr, + 18826 => Opcode::VPSHLDrm, + 18827 => Opcode::VPSHLDrr, + 18828 => Opcode::VPSHLDrr_REV, + 18829 => Opcode::VPSHLQmr, + 18830 => Opcode::VPSHLQrm, + 18831 => Opcode::VPSHLQrr, + 18832 => Opcode::VPSHLQrr_REV, + 18833 => Opcode::VPSHLWmr, + 18834 => Opcode::VPSHLWrm, + 18835 => Opcode::VPSHLWrr, + 18836 => Opcode::VPSHLWrr_REV, + 18837 => Opcode::VPSHRDDZ128rmbi, + 18838 => Opcode::VPSHRDDZ128rmbik, + 18839 => Opcode::VPSHRDDZ128rmbikz, + 18840 => Opcode::VPSHRDDZ128rmi, + 18841 => Opcode::VPSHRDDZ128rmik, + 18842 => Opcode::VPSHRDDZ128rmikz, + 18843 => Opcode::VPSHRDDZ128rri, + 18844 => Opcode::VPSHRDDZ128rrik, + 18845 => Opcode::VPSHRDDZ128rrikz, + 18846 => Opcode::VPSHRDDZ256rmbi, + 18847 => Opcode::VPSHRDDZ256rmbik, + 18848 => Opcode::VPSHRDDZ256rmbikz, + 18849 => Opcode::VPSHRDDZ256rmi, + 18850 => Opcode::VPSHRDDZ256rmik, + 18851 => Opcode::VPSHRDDZ256rmikz, + 18852 => Opcode::VPSHRDDZ256rri, + 18853 => Opcode::VPSHRDDZ256rrik, + 18854 => Opcode::VPSHRDDZ256rrikz, + 18855 => Opcode::VPSHRDDZrmbi, + 18856 => Opcode::VPSHRDDZrmbik, + 18857 => Opcode::VPSHRDDZrmbikz, + 18858 => Opcode::VPSHRDDZrmi, + 18859 => Opcode::VPSHRDDZrmik, + 18860 => Opcode::VPSHRDDZrmikz, + 18861 => Opcode::VPSHRDDZrri, + 18862 => Opcode::VPSHRDDZrrik, + 18863 => Opcode::VPSHRDDZrrikz, + 18864 => Opcode::VPSHRDQZ128rmbi, + 18865 => Opcode::VPSHRDQZ128rmbik, + 18866 => Opcode::VPSHRDQZ128rmbikz, + 18867 => Opcode::VPSHRDQZ128rmi, + 18868 => Opcode::VPSHRDQZ128rmik, + 18869 => Opcode::VPSHRDQZ128rmikz, + 18870 => Opcode::VPSHRDQZ128rri, + 18871 => Opcode::VPSHRDQZ128rrik, + 18872 => Opcode::VPSHRDQZ128rrikz, + 18873 => Opcode::VPSHRDQZ256rmbi, + 18874 => Opcode::VPSHRDQZ256rmbik, + 18875 => Opcode::VPSHRDQZ256rmbikz, + 18876 => Opcode::VPSHRDQZ256rmi, + 18877 => Opcode::VPSHRDQZ256rmik, + 18878 => Opcode::VPSHRDQZ256rmikz, + 18879 => Opcode::VPSHRDQZ256rri, + 18880 => Opcode::VPSHRDQZ256rrik, + 18881 => Opcode::VPSHRDQZ256rrikz, + 18882 => Opcode::VPSHRDQZrmbi, + 18883 => Opcode::VPSHRDQZrmbik, + 18884 => Opcode::VPSHRDQZrmbikz, + 18885 => Opcode::VPSHRDQZrmi, + 18886 => Opcode::VPSHRDQZrmik, + 18887 => Opcode::VPSHRDQZrmikz, + 18888 => Opcode::VPSHRDQZrri, + 18889 => Opcode::VPSHRDQZrrik, + 18890 => Opcode::VPSHRDQZrrikz, + 18891 => Opcode::VPSHRDVDZ128m, + 18892 => Opcode::VPSHRDVDZ128mb, + 18893 => Opcode::VPSHRDVDZ128mbk, + 18894 => Opcode::VPSHRDVDZ128mbkz, + 18895 => Opcode::VPSHRDVDZ128mk, + 18896 => Opcode::VPSHRDVDZ128mkz, + 18897 => Opcode::VPSHRDVDZ128r, + 18898 => Opcode::VPSHRDVDZ128rk, + 18899 => Opcode::VPSHRDVDZ128rkz, + 18900 => Opcode::VPSHRDVDZ256m, + 18901 => Opcode::VPSHRDVDZ256mb, + 18902 => Opcode::VPSHRDVDZ256mbk, + 18903 => Opcode::VPSHRDVDZ256mbkz, + 18904 => Opcode::VPSHRDVDZ256mk, + 18905 => Opcode::VPSHRDVDZ256mkz, + 18906 => Opcode::VPSHRDVDZ256r, + 18907 => Opcode::VPSHRDVDZ256rk, + 18908 => Opcode::VPSHRDVDZ256rkz, + 18909 => Opcode::VPSHRDVDZm, + 18910 => Opcode::VPSHRDVDZmb, + 18911 => Opcode::VPSHRDVDZmbk, + 18912 => Opcode::VPSHRDVDZmbkz, + 18913 => Opcode::VPSHRDVDZmk, + 18914 => Opcode::VPSHRDVDZmkz, + 18915 => Opcode::VPSHRDVDZr, + 18916 => Opcode::VPSHRDVDZrk, + 18917 => Opcode::VPSHRDVDZrkz, + 18918 => Opcode::VPSHRDVQZ128m, + 18919 => Opcode::VPSHRDVQZ128mb, + 18920 => Opcode::VPSHRDVQZ128mbk, + 18921 => Opcode::VPSHRDVQZ128mbkz, + 18922 => Opcode::VPSHRDVQZ128mk, + 18923 => Opcode::VPSHRDVQZ128mkz, + 18924 => Opcode::VPSHRDVQZ128r, + 18925 => Opcode::VPSHRDVQZ128rk, + 18926 => Opcode::VPSHRDVQZ128rkz, + 18927 => Opcode::VPSHRDVQZ256m, + 18928 => Opcode::VPSHRDVQZ256mb, + 18929 => Opcode::VPSHRDVQZ256mbk, + 18930 => Opcode::VPSHRDVQZ256mbkz, + 18931 => Opcode::VPSHRDVQZ256mk, + 18932 => Opcode::VPSHRDVQZ256mkz, + 18933 => Opcode::VPSHRDVQZ256r, + 18934 => Opcode::VPSHRDVQZ256rk, + 18935 => Opcode::VPSHRDVQZ256rkz, + 18936 => Opcode::VPSHRDVQZm, + 18937 => Opcode::VPSHRDVQZmb, + 18938 => Opcode::VPSHRDVQZmbk, + 18939 => Opcode::VPSHRDVQZmbkz, + 18940 => Opcode::VPSHRDVQZmk, + 18941 => Opcode::VPSHRDVQZmkz, + 18942 => Opcode::VPSHRDVQZr, + 18943 => Opcode::VPSHRDVQZrk, + 18944 => Opcode::VPSHRDVQZrkz, + 18945 => Opcode::VPSHRDVWZ128m, + 18946 => Opcode::VPSHRDVWZ128mk, + 18947 => Opcode::VPSHRDVWZ128mkz, + 18948 => Opcode::VPSHRDVWZ128r, + 18949 => Opcode::VPSHRDVWZ128rk, + 18950 => Opcode::VPSHRDVWZ128rkz, + 18951 => Opcode::VPSHRDVWZ256m, + 18952 => Opcode::VPSHRDVWZ256mk, + 18953 => Opcode::VPSHRDVWZ256mkz, + 18954 => Opcode::VPSHRDVWZ256r, + 18955 => Opcode::VPSHRDVWZ256rk, + 18956 => Opcode::VPSHRDVWZ256rkz, + 18957 => Opcode::VPSHRDVWZm, + 18958 => Opcode::VPSHRDVWZmk, + 18959 => Opcode::VPSHRDVWZmkz, + 18960 => Opcode::VPSHRDVWZr, + 18961 => Opcode::VPSHRDVWZrk, + 18962 => Opcode::VPSHRDVWZrkz, + 18963 => Opcode::VPSHRDWZ128rmi, + 18964 => Opcode::VPSHRDWZ128rmik, + 18965 => Opcode::VPSHRDWZ128rmikz, + 18966 => Opcode::VPSHRDWZ128rri, + 18967 => Opcode::VPSHRDWZ128rrik, + 18968 => Opcode::VPSHRDWZ128rrikz, + 18969 => Opcode::VPSHRDWZ256rmi, + 18970 => Opcode::VPSHRDWZ256rmik, + 18971 => Opcode::VPSHRDWZ256rmikz, + 18972 => Opcode::VPSHRDWZ256rri, + 18973 => Opcode::VPSHRDWZ256rrik, + 18974 => Opcode::VPSHRDWZ256rrikz, + 18975 => Opcode::VPSHRDWZrmi, + 18976 => Opcode::VPSHRDWZrmik, + 18977 => Opcode::VPSHRDWZrmikz, + 18978 => Opcode::VPSHRDWZrri, + 18979 => Opcode::VPSHRDWZrrik, + 18980 => Opcode::VPSHRDWZrrikz, + 18981 => Opcode::VPSHUFBITQMBZ128rm, + 18982 => Opcode::VPSHUFBITQMBZ128rmk, + 18983 => Opcode::VPSHUFBITQMBZ128rr, + 18984 => Opcode::VPSHUFBITQMBZ128rrk, + 18985 => Opcode::VPSHUFBITQMBZ256rm, + 18986 => Opcode::VPSHUFBITQMBZ256rmk, + 18987 => Opcode::VPSHUFBITQMBZ256rr, + 18988 => Opcode::VPSHUFBITQMBZ256rrk, + 18989 => Opcode::VPSHUFBITQMBZrm, + 18990 => Opcode::VPSHUFBITQMBZrmk, + 18991 => Opcode::VPSHUFBITQMBZrr, + 18992 => Opcode::VPSHUFBITQMBZrrk, + 18993 => Opcode::VPSHUFBYrm, + 18994 => Opcode::VPSHUFBYrr, + 18995 => Opcode::VPSHUFBZ128rm, + 18996 => Opcode::VPSHUFBZ128rmk, + 18997 => Opcode::VPSHUFBZ128rmkz, + 18998 => Opcode::VPSHUFBZ128rr, + 18999 => Opcode::VPSHUFBZ128rrk, + 19000 => Opcode::VPSHUFBZ128rrkz, + 19001 => Opcode::VPSHUFBZ256rm, + 19002 => Opcode::VPSHUFBZ256rmk, + 19003 => Opcode::VPSHUFBZ256rmkz, + 19004 => Opcode::VPSHUFBZ256rr, + 19005 => Opcode::VPSHUFBZ256rrk, + 19006 => Opcode::VPSHUFBZ256rrkz, + 19007 => Opcode::VPSHUFBZrm, + 19008 => Opcode::VPSHUFBZrmk, + 19009 => Opcode::VPSHUFBZrmkz, + 19010 => Opcode::VPSHUFBZrr, + 19011 => Opcode::VPSHUFBZrrk, + 19012 => Opcode::VPSHUFBZrrkz, + 19013 => Opcode::VPSHUFBrm, + 19014 => Opcode::VPSHUFBrr, + 19015 => Opcode::VPSHUFDYmi, + 19016 => Opcode::VPSHUFDYri, + 19017 => Opcode::VPSHUFDZ128mbi, + 19018 => Opcode::VPSHUFDZ128mbik, + 19019 => Opcode::VPSHUFDZ128mbikz, + 19020 => Opcode::VPSHUFDZ128mi, + 19021 => Opcode::VPSHUFDZ128mik, + 19022 => Opcode::VPSHUFDZ128mikz, + 19023 => Opcode::VPSHUFDZ128ri, + 19024 => Opcode::VPSHUFDZ128rik, + 19025 => Opcode::VPSHUFDZ128rikz, + 19026 => Opcode::VPSHUFDZ256mbi, + 19027 => Opcode::VPSHUFDZ256mbik, + 19028 => Opcode::VPSHUFDZ256mbikz, + 19029 => Opcode::VPSHUFDZ256mi, + 19030 => Opcode::VPSHUFDZ256mik, + 19031 => Opcode::VPSHUFDZ256mikz, + 19032 => Opcode::VPSHUFDZ256ri, + 19033 => Opcode::VPSHUFDZ256rik, + 19034 => Opcode::VPSHUFDZ256rikz, + 19035 => Opcode::VPSHUFDZmbi, + 19036 => Opcode::VPSHUFDZmbik, + 19037 => Opcode::VPSHUFDZmbikz, + 19038 => Opcode::VPSHUFDZmi, + 19039 => Opcode::VPSHUFDZmik, + 19040 => Opcode::VPSHUFDZmikz, + 19041 => Opcode::VPSHUFDZri, + 19042 => Opcode::VPSHUFDZrik, + 19043 => Opcode::VPSHUFDZrikz, + 19044 => Opcode::VPSHUFDmi, + 19045 => Opcode::VPSHUFDri, + 19046 => Opcode::VPSHUFHWYmi, + 19047 => Opcode::VPSHUFHWYri, + 19048 => Opcode::VPSHUFHWZ128mi, + 19049 => Opcode::VPSHUFHWZ128mik, + 19050 => Opcode::VPSHUFHWZ128mikz, + 19051 => Opcode::VPSHUFHWZ128ri, + 19052 => Opcode::VPSHUFHWZ128rik, + 19053 => Opcode::VPSHUFHWZ128rikz, + 19054 => Opcode::VPSHUFHWZ256mi, + 19055 => Opcode::VPSHUFHWZ256mik, + 19056 => Opcode::VPSHUFHWZ256mikz, + 19057 => Opcode::VPSHUFHWZ256ri, + 19058 => Opcode::VPSHUFHWZ256rik, + 19059 => Opcode::VPSHUFHWZ256rikz, + 19060 => Opcode::VPSHUFHWZmi, + 19061 => Opcode::VPSHUFHWZmik, + 19062 => Opcode::VPSHUFHWZmikz, + 19063 => Opcode::VPSHUFHWZri, + 19064 => Opcode::VPSHUFHWZrik, + 19065 => Opcode::VPSHUFHWZrikz, + 19066 => Opcode::VPSHUFHWmi, + 19067 => Opcode::VPSHUFHWri, + 19068 => Opcode::VPSHUFLWYmi, + 19069 => Opcode::VPSHUFLWYri, + 19070 => Opcode::VPSHUFLWZ128mi, + 19071 => Opcode::VPSHUFLWZ128mik, + 19072 => Opcode::VPSHUFLWZ128mikz, + 19073 => Opcode::VPSHUFLWZ128ri, + 19074 => Opcode::VPSHUFLWZ128rik, + 19075 => Opcode::VPSHUFLWZ128rikz, + 19076 => Opcode::VPSHUFLWZ256mi, + 19077 => Opcode::VPSHUFLWZ256mik, + 19078 => Opcode::VPSHUFLWZ256mikz, + 19079 => Opcode::VPSHUFLWZ256ri, + 19080 => Opcode::VPSHUFLWZ256rik, + 19081 => Opcode::VPSHUFLWZ256rikz, + 19082 => Opcode::VPSHUFLWZmi, + 19083 => Opcode::VPSHUFLWZmik, + 19084 => Opcode::VPSHUFLWZmikz, + 19085 => Opcode::VPSHUFLWZri, + 19086 => Opcode::VPSHUFLWZrik, + 19087 => Opcode::VPSHUFLWZrikz, + 19088 => Opcode::VPSHUFLWmi, + 19089 => Opcode::VPSHUFLWri, + 19090 => Opcode::VPSIGNBYrm, + 19091 => Opcode::VPSIGNBYrr, + 19092 => Opcode::VPSIGNBrm, + 19093 => Opcode::VPSIGNBrr, + 19094 => Opcode::VPSIGNDYrm, + 19095 => Opcode::VPSIGNDYrr, + 19096 => Opcode::VPSIGNDrm, + 19097 => Opcode::VPSIGNDrr, + 19098 => Opcode::VPSIGNWYrm, + 19099 => Opcode::VPSIGNWYrr, + 19100 => Opcode::VPSIGNWrm, + 19101 => Opcode::VPSIGNWrr, + 19102 => Opcode::VPSLLDQYri, + 19103 => Opcode::VPSLLDQZ128mi, + 19104 => Opcode::VPSLLDQZ128ri, + 19105 => Opcode::VPSLLDQZ256mi, + 19106 => Opcode::VPSLLDQZ256ri, + 19107 => Opcode::VPSLLDQZmi, + 19108 => Opcode::VPSLLDQZri, + 19109 => Opcode::VPSLLDQri, + 19110 => Opcode::VPSLLDYri, + 19111 => Opcode::VPSLLDYrm, + 19112 => Opcode::VPSLLDYrr, + 19113 => Opcode::VPSLLDZ128mbi, + 19114 => Opcode::VPSLLDZ128mbik, + 19115 => Opcode::VPSLLDZ128mbikz, + 19116 => Opcode::VPSLLDZ128mi, + 19117 => Opcode::VPSLLDZ128mik, + 19118 => Opcode::VPSLLDZ128mikz, + 19119 => Opcode::VPSLLDZ128ri, + 19120 => Opcode::VPSLLDZ128rik, + 19121 => Opcode::VPSLLDZ128rikz, + 19122 => Opcode::VPSLLDZ128rm, + 19123 => Opcode::VPSLLDZ128rmk, + 19124 => Opcode::VPSLLDZ128rmkz, + 19125 => Opcode::VPSLLDZ128rr, + 19126 => Opcode::VPSLLDZ128rrk, + 19127 => Opcode::VPSLLDZ128rrkz, + 19128 => Opcode::VPSLLDZ256mbi, + 19129 => Opcode::VPSLLDZ256mbik, + 19130 => Opcode::VPSLLDZ256mbikz, + 19131 => Opcode::VPSLLDZ256mi, + 19132 => Opcode::VPSLLDZ256mik, + 19133 => Opcode::VPSLLDZ256mikz, + 19134 => Opcode::VPSLLDZ256ri, + 19135 => Opcode::VPSLLDZ256rik, + 19136 => Opcode::VPSLLDZ256rikz, + 19137 => Opcode::VPSLLDZ256rm, + 19138 => Opcode::VPSLLDZ256rmk, + 19139 => Opcode::VPSLLDZ256rmkz, + 19140 => Opcode::VPSLLDZ256rr, + 19141 => Opcode::VPSLLDZ256rrk, + 19142 => Opcode::VPSLLDZ256rrkz, + 19143 => Opcode::VPSLLDZmbi, + 19144 => Opcode::VPSLLDZmbik, + 19145 => Opcode::VPSLLDZmbikz, + 19146 => Opcode::VPSLLDZmi, + 19147 => Opcode::VPSLLDZmik, + 19148 => Opcode::VPSLLDZmikz, + 19149 => Opcode::VPSLLDZri, + 19150 => Opcode::VPSLLDZrik, + 19151 => Opcode::VPSLLDZrikz, + 19152 => Opcode::VPSLLDZrm, + 19153 => Opcode::VPSLLDZrmk, + 19154 => Opcode::VPSLLDZrmkz, + 19155 => Opcode::VPSLLDZrr, + 19156 => Opcode::VPSLLDZrrk, + 19157 => Opcode::VPSLLDZrrkz, + 19158 => Opcode::VPSLLDri, + 19159 => Opcode::VPSLLDrm, + 19160 => Opcode::VPSLLDrr, + 19161 => Opcode::VPSLLQYri, + 19162 => Opcode::VPSLLQYrm, + 19163 => Opcode::VPSLLQYrr, + 19164 => Opcode::VPSLLQZ128mbi, + 19165 => Opcode::VPSLLQZ128mbik, + 19166 => Opcode::VPSLLQZ128mbikz, + 19167 => Opcode::VPSLLQZ128mi, + 19168 => Opcode::VPSLLQZ128mik, + 19169 => Opcode::VPSLLQZ128mikz, + 19170 => Opcode::VPSLLQZ128ri, + 19171 => Opcode::VPSLLQZ128rik, + 19172 => Opcode::VPSLLQZ128rikz, + 19173 => Opcode::VPSLLQZ128rm, + 19174 => Opcode::VPSLLQZ128rmk, + 19175 => Opcode::VPSLLQZ128rmkz, + 19176 => Opcode::VPSLLQZ128rr, + 19177 => Opcode::VPSLLQZ128rrk, + 19178 => Opcode::VPSLLQZ128rrkz, + 19179 => Opcode::VPSLLQZ256mbi, + 19180 => Opcode::VPSLLQZ256mbik, + 19181 => Opcode::VPSLLQZ256mbikz, + 19182 => Opcode::VPSLLQZ256mi, + 19183 => Opcode::VPSLLQZ256mik, + 19184 => Opcode::VPSLLQZ256mikz, + 19185 => Opcode::VPSLLQZ256ri, + 19186 => Opcode::VPSLLQZ256rik, + 19187 => Opcode::VPSLLQZ256rikz, + 19188 => Opcode::VPSLLQZ256rm, + 19189 => Opcode::VPSLLQZ256rmk, + 19190 => Opcode::VPSLLQZ256rmkz, + 19191 => Opcode::VPSLLQZ256rr, + 19192 => Opcode::VPSLLQZ256rrk, + 19193 => Opcode::VPSLLQZ256rrkz, + 19194 => Opcode::VPSLLQZmbi, + 19195 => Opcode::VPSLLQZmbik, + 19196 => Opcode::VPSLLQZmbikz, + 19197 => Opcode::VPSLLQZmi, + 19198 => Opcode::VPSLLQZmik, + 19199 => Opcode::VPSLLQZmikz, + 19200 => Opcode::VPSLLQZri, + 19201 => Opcode::VPSLLQZrik, + 19202 => Opcode::VPSLLQZrikz, + 19203 => Opcode::VPSLLQZrm, + 19204 => Opcode::VPSLLQZrmk, + 19205 => Opcode::VPSLLQZrmkz, + 19206 => Opcode::VPSLLQZrr, + 19207 => Opcode::VPSLLQZrrk, + 19208 => Opcode::VPSLLQZrrkz, + 19209 => Opcode::VPSLLQri, + 19210 => Opcode::VPSLLQrm, + 19211 => Opcode::VPSLLQrr, + 19212 => Opcode::VPSLLVDYrm, + 19213 => Opcode::VPSLLVDYrr, + 19214 => Opcode::VPSLLVDZ128rm, + 19215 => Opcode::VPSLLVDZ128rmb, + 19216 => Opcode::VPSLLVDZ128rmbk, + 19217 => Opcode::VPSLLVDZ128rmbkz, + 19218 => Opcode::VPSLLVDZ128rmk, + 19219 => Opcode::VPSLLVDZ128rmkz, + 19220 => Opcode::VPSLLVDZ128rr, + 19221 => Opcode::VPSLLVDZ128rrk, + 19222 => Opcode::VPSLLVDZ128rrkz, + 19223 => Opcode::VPSLLVDZ256rm, + 19224 => Opcode::VPSLLVDZ256rmb, + 19225 => Opcode::VPSLLVDZ256rmbk, + 19226 => Opcode::VPSLLVDZ256rmbkz, + 19227 => Opcode::VPSLLVDZ256rmk, + 19228 => Opcode::VPSLLVDZ256rmkz, + 19229 => Opcode::VPSLLVDZ256rr, + 19230 => Opcode::VPSLLVDZ256rrk, + 19231 => Opcode::VPSLLVDZ256rrkz, + 19232 => Opcode::VPSLLVDZrm, + 19233 => Opcode::VPSLLVDZrmb, + 19234 => Opcode::VPSLLVDZrmbk, + 19235 => Opcode::VPSLLVDZrmbkz, + 19236 => Opcode::VPSLLVDZrmk, + 19237 => Opcode::VPSLLVDZrmkz, + 19238 => Opcode::VPSLLVDZrr, + 19239 => Opcode::VPSLLVDZrrk, + 19240 => Opcode::VPSLLVDZrrkz, + 19241 => Opcode::VPSLLVDrm, + 19242 => Opcode::VPSLLVDrr, + 19243 => Opcode::VPSLLVQYrm, + 19244 => Opcode::VPSLLVQYrr, + 19245 => Opcode::VPSLLVQZ128rm, + 19246 => Opcode::VPSLLVQZ128rmb, + 19247 => Opcode::VPSLLVQZ128rmbk, + 19248 => Opcode::VPSLLVQZ128rmbkz, + 19249 => Opcode::VPSLLVQZ128rmk, + 19250 => Opcode::VPSLLVQZ128rmkz, + 19251 => Opcode::VPSLLVQZ128rr, + 19252 => Opcode::VPSLLVQZ128rrk, + 19253 => Opcode::VPSLLVQZ128rrkz, + 19254 => Opcode::VPSLLVQZ256rm, + 19255 => Opcode::VPSLLVQZ256rmb, + 19256 => Opcode::VPSLLVQZ256rmbk, + 19257 => Opcode::VPSLLVQZ256rmbkz, + 19258 => Opcode::VPSLLVQZ256rmk, + 19259 => Opcode::VPSLLVQZ256rmkz, + 19260 => Opcode::VPSLLVQZ256rr, + 19261 => Opcode::VPSLLVQZ256rrk, + 19262 => Opcode::VPSLLVQZ256rrkz, + 19263 => Opcode::VPSLLVQZrm, + 19264 => Opcode::VPSLLVQZrmb, + 19265 => Opcode::VPSLLVQZrmbk, + 19266 => Opcode::VPSLLVQZrmbkz, + 19267 => Opcode::VPSLLVQZrmk, + 19268 => Opcode::VPSLLVQZrmkz, + 19269 => Opcode::VPSLLVQZrr, + 19270 => Opcode::VPSLLVQZrrk, + 19271 => Opcode::VPSLLVQZrrkz, + 19272 => Opcode::VPSLLVQrm, + 19273 => Opcode::VPSLLVQrr, + 19274 => Opcode::VPSLLVWZ128rm, + 19275 => Opcode::VPSLLVWZ128rmk, + 19276 => Opcode::VPSLLVWZ128rmkz, + 19277 => Opcode::VPSLLVWZ128rr, + 19278 => Opcode::VPSLLVWZ128rrk, + 19279 => Opcode::VPSLLVWZ128rrkz, + 19280 => Opcode::VPSLLVWZ256rm, + 19281 => Opcode::VPSLLVWZ256rmk, + 19282 => Opcode::VPSLLVWZ256rmkz, + 19283 => Opcode::VPSLLVWZ256rr, + 19284 => Opcode::VPSLLVWZ256rrk, + 19285 => Opcode::VPSLLVWZ256rrkz, + 19286 => Opcode::VPSLLVWZrm, + 19287 => Opcode::VPSLLVWZrmk, + 19288 => Opcode::VPSLLVWZrmkz, + 19289 => Opcode::VPSLLVWZrr, + 19290 => Opcode::VPSLLVWZrrk, + 19291 => Opcode::VPSLLVWZrrkz, + 19292 => Opcode::VPSLLWYri, + 19293 => Opcode::VPSLLWYrm, + 19294 => Opcode::VPSLLWYrr, + 19295 => Opcode::VPSLLWZ128mi, + 19296 => Opcode::VPSLLWZ128mik, + 19297 => Opcode::VPSLLWZ128mikz, + 19298 => Opcode::VPSLLWZ128ri, + 19299 => Opcode::VPSLLWZ128rik, + 19300 => Opcode::VPSLLWZ128rikz, + 19301 => Opcode::VPSLLWZ128rm, + 19302 => Opcode::VPSLLWZ128rmk, + 19303 => Opcode::VPSLLWZ128rmkz, + 19304 => Opcode::VPSLLWZ128rr, + 19305 => Opcode::VPSLLWZ128rrk, + 19306 => Opcode::VPSLLWZ128rrkz, + 19307 => Opcode::VPSLLWZ256mi, + 19308 => Opcode::VPSLLWZ256mik, + 19309 => Opcode::VPSLLWZ256mikz, + 19310 => Opcode::VPSLLWZ256ri, + 19311 => Opcode::VPSLLWZ256rik, + 19312 => Opcode::VPSLLWZ256rikz, + 19313 => Opcode::VPSLLWZ256rm, + 19314 => Opcode::VPSLLWZ256rmk, + 19315 => Opcode::VPSLLWZ256rmkz, + 19316 => Opcode::VPSLLWZ256rr, + 19317 => Opcode::VPSLLWZ256rrk, + 19318 => Opcode::VPSLLWZ256rrkz, + 19319 => Opcode::VPSLLWZmi, + 19320 => Opcode::VPSLLWZmik, + 19321 => Opcode::VPSLLWZmikz, + 19322 => Opcode::VPSLLWZri, + 19323 => Opcode::VPSLLWZrik, + 19324 => Opcode::VPSLLWZrikz, + 19325 => Opcode::VPSLLWZrm, + 19326 => Opcode::VPSLLWZrmk, + 19327 => Opcode::VPSLLWZrmkz, + 19328 => Opcode::VPSLLWZrr, + 19329 => Opcode::VPSLLWZrrk, + 19330 => Opcode::VPSLLWZrrkz, + 19331 => Opcode::VPSLLWri, + 19332 => Opcode::VPSLLWrm, + 19333 => Opcode::VPSLLWrr, + 19334 => Opcode::VPSRADYri, + 19335 => Opcode::VPSRADYrm, + 19336 => Opcode::VPSRADYrr, + 19337 => Opcode::VPSRADZ128mbi, + 19338 => Opcode::VPSRADZ128mbik, + 19339 => Opcode::VPSRADZ128mbikz, + 19340 => Opcode::VPSRADZ128mi, + 19341 => Opcode::VPSRADZ128mik, + 19342 => Opcode::VPSRADZ128mikz, + 19343 => Opcode::VPSRADZ128ri, + 19344 => Opcode::VPSRADZ128rik, + 19345 => Opcode::VPSRADZ128rikz, + 19346 => Opcode::VPSRADZ128rm, + 19347 => Opcode::VPSRADZ128rmk, + 19348 => Opcode::VPSRADZ128rmkz, + 19349 => Opcode::VPSRADZ128rr, + 19350 => Opcode::VPSRADZ128rrk, + 19351 => Opcode::VPSRADZ128rrkz, + 19352 => Opcode::VPSRADZ256mbi, + 19353 => Opcode::VPSRADZ256mbik, + 19354 => Opcode::VPSRADZ256mbikz, + 19355 => Opcode::VPSRADZ256mi, + 19356 => Opcode::VPSRADZ256mik, + 19357 => Opcode::VPSRADZ256mikz, + 19358 => Opcode::VPSRADZ256ri, + 19359 => Opcode::VPSRADZ256rik, + 19360 => Opcode::VPSRADZ256rikz, + 19361 => Opcode::VPSRADZ256rm, + 19362 => Opcode::VPSRADZ256rmk, + 19363 => Opcode::VPSRADZ256rmkz, + 19364 => Opcode::VPSRADZ256rr, + 19365 => Opcode::VPSRADZ256rrk, + 19366 => Opcode::VPSRADZ256rrkz, + 19367 => Opcode::VPSRADZmbi, + 19368 => Opcode::VPSRADZmbik, + 19369 => Opcode::VPSRADZmbikz, + 19370 => Opcode::VPSRADZmi, + 19371 => Opcode::VPSRADZmik, + 19372 => Opcode::VPSRADZmikz, + 19373 => Opcode::VPSRADZri, + 19374 => Opcode::VPSRADZrik, + 19375 => Opcode::VPSRADZrikz, + 19376 => Opcode::VPSRADZrm, + 19377 => Opcode::VPSRADZrmk, + 19378 => Opcode::VPSRADZrmkz, + 19379 => Opcode::VPSRADZrr, + 19380 => Opcode::VPSRADZrrk, + 19381 => Opcode::VPSRADZrrkz, + 19382 => Opcode::VPSRADri, + 19383 => Opcode::VPSRADrm, + 19384 => Opcode::VPSRADrr, + 19385 => Opcode::VPSRAQZ128mbi, + 19386 => Opcode::VPSRAQZ128mbik, + 19387 => Opcode::VPSRAQZ128mbikz, + 19388 => Opcode::VPSRAQZ128mi, + 19389 => Opcode::VPSRAQZ128mik, + 19390 => Opcode::VPSRAQZ128mikz, + 19391 => Opcode::VPSRAQZ128ri, + 19392 => Opcode::VPSRAQZ128rik, + 19393 => Opcode::VPSRAQZ128rikz, + 19394 => Opcode::VPSRAQZ128rm, + 19395 => Opcode::VPSRAQZ128rmk, + 19396 => Opcode::VPSRAQZ128rmkz, + 19397 => Opcode::VPSRAQZ128rr, + 19398 => Opcode::VPSRAQZ128rrk, + 19399 => Opcode::VPSRAQZ128rrkz, + 19400 => Opcode::VPSRAQZ256mbi, + 19401 => Opcode::VPSRAQZ256mbik, + 19402 => Opcode::VPSRAQZ256mbikz, + 19403 => Opcode::VPSRAQZ256mi, + 19404 => Opcode::VPSRAQZ256mik, + 19405 => Opcode::VPSRAQZ256mikz, + 19406 => Opcode::VPSRAQZ256ri, + 19407 => Opcode::VPSRAQZ256rik, + 19408 => Opcode::VPSRAQZ256rikz, + 19409 => Opcode::VPSRAQZ256rm, + 19410 => Opcode::VPSRAQZ256rmk, + 19411 => Opcode::VPSRAQZ256rmkz, + 19412 => Opcode::VPSRAQZ256rr, + 19413 => Opcode::VPSRAQZ256rrk, + 19414 => Opcode::VPSRAQZ256rrkz, + 19415 => Opcode::VPSRAQZmbi, + 19416 => Opcode::VPSRAQZmbik, + 19417 => Opcode::VPSRAQZmbikz, + 19418 => Opcode::VPSRAQZmi, + 19419 => Opcode::VPSRAQZmik, + 19420 => Opcode::VPSRAQZmikz, + 19421 => Opcode::VPSRAQZri, + 19422 => Opcode::VPSRAQZrik, + 19423 => Opcode::VPSRAQZrikz, + 19424 => Opcode::VPSRAQZrm, + 19425 => Opcode::VPSRAQZrmk, + 19426 => Opcode::VPSRAQZrmkz, + 19427 => Opcode::VPSRAQZrr, + 19428 => Opcode::VPSRAQZrrk, + 19429 => Opcode::VPSRAQZrrkz, + 19430 => Opcode::VPSRAVDYrm, + 19431 => Opcode::VPSRAVDYrr, + 19432 => Opcode::VPSRAVDZ128rm, + 19433 => Opcode::VPSRAVDZ128rmb, + 19434 => Opcode::VPSRAVDZ128rmbk, + 19435 => Opcode::VPSRAVDZ128rmbkz, + 19436 => Opcode::VPSRAVDZ128rmk, + 19437 => Opcode::VPSRAVDZ128rmkz, + 19438 => Opcode::VPSRAVDZ128rr, + 19439 => Opcode::VPSRAVDZ128rrk, + 19440 => Opcode::VPSRAVDZ128rrkz, + 19441 => Opcode::VPSRAVDZ256rm, + 19442 => Opcode::VPSRAVDZ256rmb, + 19443 => Opcode::VPSRAVDZ256rmbk, + 19444 => Opcode::VPSRAVDZ256rmbkz, + 19445 => Opcode::VPSRAVDZ256rmk, + 19446 => Opcode::VPSRAVDZ256rmkz, + 19447 => Opcode::VPSRAVDZ256rr, + 19448 => Opcode::VPSRAVDZ256rrk, + 19449 => Opcode::VPSRAVDZ256rrkz, + 19450 => Opcode::VPSRAVDZrm, + 19451 => Opcode::VPSRAVDZrmb, + 19452 => Opcode::VPSRAVDZrmbk, + 19453 => Opcode::VPSRAVDZrmbkz, + 19454 => Opcode::VPSRAVDZrmk, + 19455 => Opcode::VPSRAVDZrmkz, + 19456 => Opcode::VPSRAVDZrr, + 19457 => Opcode::VPSRAVDZrrk, + 19458 => Opcode::VPSRAVDZrrkz, + 19459 => Opcode::VPSRAVDrm, + 19460 => Opcode::VPSRAVDrr, + 19461 => Opcode::VPSRAVQZ128rm, + 19462 => Opcode::VPSRAVQZ128rmb, + 19463 => Opcode::VPSRAVQZ128rmbk, + 19464 => Opcode::VPSRAVQZ128rmbkz, + 19465 => Opcode::VPSRAVQZ128rmk, + 19466 => Opcode::VPSRAVQZ128rmkz, + 19467 => Opcode::VPSRAVQZ128rr, + 19468 => Opcode::VPSRAVQZ128rrk, + 19469 => Opcode::VPSRAVQZ128rrkz, + 19470 => Opcode::VPSRAVQZ256rm, + 19471 => Opcode::VPSRAVQZ256rmb, + 19472 => Opcode::VPSRAVQZ256rmbk, + 19473 => Opcode::VPSRAVQZ256rmbkz, + 19474 => Opcode::VPSRAVQZ256rmk, + 19475 => Opcode::VPSRAVQZ256rmkz, + 19476 => Opcode::VPSRAVQZ256rr, + 19477 => Opcode::VPSRAVQZ256rrk, + 19478 => Opcode::VPSRAVQZ256rrkz, + 19479 => Opcode::VPSRAVQZrm, + 19480 => Opcode::VPSRAVQZrmb, + 19481 => Opcode::VPSRAVQZrmbk, + 19482 => Opcode::VPSRAVQZrmbkz, + 19483 => Opcode::VPSRAVQZrmk, + 19484 => Opcode::VPSRAVQZrmkz, + 19485 => Opcode::VPSRAVQZrr, + 19486 => Opcode::VPSRAVQZrrk, + 19487 => Opcode::VPSRAVQZrrkz, + 19488 => Opcode::VPSRAVWZ128rm, + 19489 => Opcode::VPSRAVWZ128rmk, + 19490 => Opcode::VPSRAVWZ128rmkz, + 19491 => Opcode::VPSRAVWZ128rr, + 19492 => Opcode::VPSRAVWZ128rrk, + 19493 => Opcode::VPSRAVWZ128rrkz, + 19494 => Opcode::VPSRAVWZ256rm, + 19495 => Opcode::VPSRAVWZ256rmk, + 19496 => Opcode::VPSRAVWZ256rmkz, + 19497 => Opcode::VPSRAVWZ256rr, + 19498 => Opcode::VPSRAVWZ256rrk, + 19499 => Opcode::VPSRAVWZ256rrkz, + 19500 => Opcode::VPSRAVWZrm, + 19501 => Opcode::VPSRAVWZrmk, + 19502 => Opcode::VPSRAVWZrmkz, + 19503 => Opcode::VPSRAVWZrr, + 19504 => Opcode::VPSRAVWZrrk, + 19505 => Opcode::VPSRAVWZrrkz, + 19506 => Opcode::VPSRAWYri, + 19507 => Opcode::VPSRAWYrm, + 19508 => Opcode::VPSRAWYrr, + 19509 => Opcode::VPSRAWZ128mi, + 19510 => Opcode::VPSRAWZ128mik, + 19511 => Opcode::VPSRAWZ128mikz, + 19512 => Opcode::VPSRAWZ128ri, + 19513 => Opcode::VPSRAWZ128rik, + 19514 => Opcode::VPSRAWZ128rikz, + 19515 => Opcode::VPSRAWZ128rm, + 19516 => Opcode::VPSRAWZ128rmk, + 19517 => Opcode::VPSRAWZ128rmkz, + 19518 => Opcode::VPSRAWZ128rr, + 19519 => Opcode::VPSRAWZ128rrk, + 19520 => Opcode::VPSRAWZ128rrkz, + 19521 => Opcode::VPSRAWZ256mi, + 19522 => Opcode::VPSRAWZ256mik, + 19523 => Opcode::VPSRAWZ256mikz, + 19524 => Opcode::VPSRAWZ256ri, + 19525 => Opcode::VPSRAWZ256rik, + 19526 => Opcode::VPSRAWZ256rikz, + 19527 => Opcode::VPSRAWZ256rm, + 19528 => Opcode::VPSRAWZ256rmk, + 19529 => Opcode::VPSRAWZ256rmkz, + 19530 => Opcode::VPSRAWZ256rr, + 19531 => Opcode::VPSRAWZ256rrk, + 19532 => Opcode::VPSRAWZ256rrkz, + 19533 => Opcode::VPSRAWZmi, + 19534 => Opcode::VPSRAWZmik, + 19535 => Opcode::VPSRAWZmikz, + 19536 => Opcode::VPSRAWZri, + 19537 => Opcode::VPSRAWZrik, + 19538 => Opcode::VPSRAWZrikz, + 19539 => Opcode::VPSRAWZrm, + 19540 => Opcode::VPSRAWZrmk, + 19541 => Opcode::VPSRAWZrmkz, + 19542 => Opcode::VPSRAWZrr, + 19543 => Opcode::VPSRAWZrrk, + 19544 => Opcode::VPSRAWZrrkz, + 19545 => Opcode::VPSRAWri, + 19546 => Opcode::VPSRAWrm, + 19547 => Opcode::VPSRAWrr, + 19548 => Opcode::VPSRLDQYri, + 19549 => Opcode::VPSRLDQZ128mi, + 19550 => Opcode::VPSRLDQZ128ri, + 19551 => Opcode::VPSRLDQZ256mi, + 19552 => Opcode::VPSRLDQZ256ri, + 19553 => Opcode::VPSRLDQZmi, + 19554 => Opcode::VPSRLDQZri, + 19555 => Opcode::VPSRLDQri, + 19556 => Opcode::VPSRLDYri, + 19557 => Opcode::VPSRLDYrm, + 19558 => Opcode::VPSRLDYrr, + 19559 => Opcode::VPSRLDZ128mbi, + 19560 => Opcode::VPSRLDZ128mbik, + 19561 => Opcode::VPSRLDZ128mbikz, + 19562 => Opcode::VPSRLDZ128mi, + 19563 => Opcode::VPSRLDZ128mik, + 19564 => Opcode::VPSRLDZ128mikz, + 19565 => Opcode::VPSRLDZ128ri, + 19566 => Opcode::VPSRLDZ128rik, + 19567 => Opcode::VPSRLDZ128rikz, + 19568 => Opcode::VPSRLDZ128rm, + 19569 => Opcode::VPSRLDZ128rmk, + 19570 => Opcode::VPSRLDZ128rmkz, + 19571 => Opcode::VPSRLDZ128rr, + 19572 => Opcode::VPSRLDZ128rrk, + 19573 => Opcode::VPSRLDZ128rrkz, + 19574 => Opcode::VPSRLDZ256mbi, + 19575 => Opcode::VPSRLDZ256mbik, + 19576 => Opcode::VPSRLDZ256mbikz, + 19577 => Opcode::VPSRLDZ256mi, + 19578 => Opcode::VPSRLDZ256mik, + 19579 => Opcode::VPSRLDZ256mikz, + 19580 => Opcode::VPSRLDZ256ri, + 19581 => Opcode::VPSRLDZ256rik, + 19582 => Opcode::VPSRLDZ256rikz, + 19583 => Opcode::VPSRLDZ256rm, + 19584 => Opcode::VPSRLDZ256rmk, + 19585 => Opcode::VPSRLDZ256rmkz, + 19586 => Opcode::VPSRLDZ256rr, + 19587 => Opcode::VPSRLDZ256rrk, + 19588 => Opcode::VPSRLDZ256rrkz, + 19589 => Opcode::VPSRLDZmbi, + 19590 => Opcode::VPSRLDZmbik, + 19591 => Opcode::VPSRLDZmbikz, + 19592 => Opcode::VPSRLDZmi, + 19593 => Opcode::VPSRLDZmik, + 19594 => Opcode::VPSRLDZmikz, + 19595 => Opcode::VPSRLDZri, + 19596 => Opcode::VPSRLDZrik, + 19597 => Opcode::VPSRLDZrikz, + 19598 => Opcode::VPSRLDZrm, + 19599 => Opcode::VPSRLDZrmk, + 19600 => Opcode::VPSRLDZrmkz, + 19601 => Opcode::VPSRLDZrr, + 19602 => Opcode::VPSRLDZrrk, + 19603 => Opcode::VPSRLDZrrkz, + 19604 => Opcode::VPSRLDri, + 19605 => Opcode::VPSRLDrm, + 19606 => Opcode::VPSRLDrr, + 19607 => Opcode::VPSRLQYri, + 19608 => Opcode::VPSRLQYrm, + 19609 => Opcode::VPSRLQYrr, + 19610 => Opcode::VPSRLQZ128mbi, + 19611 => Opcode::VPSRLQZ128mbik, + 19612 => Opcode::VPSRLQZ128mbikz, + 19613 => Opcode::VPSRLQZ128mi, + 19614 => Opcode::VPSRLQZ128mik, + 19615 => Opcode::VPSRLQZ128mikz, + 19616 => Opcode::VPSRLQZ128ri, + 19617 => Opcode::VPSRLQZ128rik, + 19618 => Opcode::VPSRLQZ128rikz, + 19619 => Opcode::VPSRLQZ128rm, + 19620 => Opcode::VPSRLQZ128rmk, + 19621 => Opcode::VPSRLQZ128rmkz, + 19622 => Opcode::VPSRLQZ128rr, + 19623 => Opcode::VPSRLQZ128rrk, + 19624 => Opcode::VPSRLQZ128rrkz, + 19625 => Opcode::VPSRLQZ256mbi, + 19626 => Opcode::VPSRLQZ256mbik, + 19627 => Opcode::VPSRLQZ256mbikz, + 19628 => Opcode::VPSRLQZ256mi, + 19629 => Opcode::VPSRLQZ256mik, + 19630 => Opcode::VPSRLQZ256mikz, + 19631 => Opcode::VPSRLQZ256ri, + 19632 => Opcode::VPSRLQZ256rik, + 19633 => Opcode::VPSRLQZ256rikz, + 19634 => Opcode::VPSRLQZ256rm, + 19635 => Opcode::VPSRLQZ256rmk, + 19636 => Opcode::VPSRLQZ256rmkz, + 19637 => Opcode::VPSRLQZ256rr, + 19638 => Opcode::VPSRLQZ256rrk, + 19639 => Opcode::VPSRLQZ256rrkz, + 19640 => Opcode::VPSRLQZmbi, + 19641 => Opcode::VPSRLQZmbik, + 19642 => Opcode::VPSRLQZmbikz, + 19643 => Opcode::VPSRLQZmi, + 19644 => Opcode::VPSRLQZmik, + 19645 => Opcode::VPSRLQZmikz, + 19646 => Opcode::VPSRLQZri, + 19647 => Opcode::VPSRLQZrik, + 19648 => Opcode::VPSRLQZrikz, + 19649 => Opcode::VPSRLQZrm, + 19650 => Opcode::VPSRLQZrmk, + 19651 => Opcode::VPSRLQZrmkz, + 19652 => Opcode::VPSRLQZrr, + 19653 => Opcode::VPSRLQZrrk, + 19654 => Opcode::VPSRLQZrrkz, + 19655 => Opcode::VPSRLQri, + 19656 => Opcode::VPSRLQrm, + 19657 => Opcode::VPSRLQrr, + 19658 => Opcode::VPSRLVDYrm, + 19659 => Opcode::VPSRLVDYrr, + 19660 => Opcode::VPSRLVDZ128rm, + 19661 => Opcode::VPSRLVDZ128rmb, + 19662 => Opcode::VPSRLVDZ128rmbk, + 19663 => Opcode::VPSRLVDZ128rmbkz, + 19664 => Opcode::VPSRLVDZ128rmk, + 19665 => Opcode::VPSRLVDZ128rmkz, + 19666 => Opcode::VPSRLVDZ128rr, + 19667 => Opcode::VPSRLVDZ128rrk, + 19668 => Opcode::VPSRLVDZ128rrkz, + 19669 => Opcode::VPSRLVDZ256rm, + 19670 => Opcode::VPSRLVDZ256rmb, + 19671 => Opcode::VPSRLVDZ256rmbk, + 19672 => Opcode::VPSRLVDZ256rmbkz, + 19673 => Opcode::VPSRLVDZ256rmk, + 19674 => Opcode::VPSRLVDZ256rmkz, + 19675 => Opcode::VPSRLVDZ256rr, + 19676 => Opcode::VPSRLVDZ256rrk, + 19677 => Opcode::VPSRLVDZ256rrkz, + 19678 => Opcode::VPSRLVDZrm, + 19679 => Opcode::VPSRLVDZrmb, + 19680 => Opcode::VPSRLVDZrmbk, + 19681 => Opcode::VPSRLVDZrmbkz, + 19682 => Opcode::VPSRLVDZrmk, + 19683 => Opcode::VPSRLVDZrmkz, + 19684 => Opcode::VPSRLVDZrr, + 19685 => Opcode::VPSRLVDZrrk, + 19686 => Opcode::VPSRLVDZrrkz, + 19687 => Opcode::VPSRLVDrm, + 19688 => Opcode::VPSRLVDrr, + 19689 => Opcode::VPSRLVQYrm, + 19690 => Opcode::VPSRLVQYrr, + 19691 => Opcode::VPSRLVQZ128rm, + 19692 => Opcode::VPSRLVQZ128rmb, + 19693 => Opcode::VPSRLVQZ128rmbk, + 19694 => Opcode::VPSRLVQZ128rmbkz, + 19695 => Opcode::VPSRLVQZ128rmk, + 19696 => Opcode::VPSRLVQZ128rmkz, + 19697 => Opcode::VPSRLVQZ128rr, + 19698 => Opcode::VPSRLVQZ128rrk, + 19699 => Opcode::VPSRLVQZ128rrkz, + 19700 => Opcode::VPSRLVQZ256rm, + 19701 => Opcode::VPSRLVQZ256rmb, + 19702 => Opcode::VPSRLVQZ256rmbk, + 19703 => Opcode::VPSRLVQZ256rmbkz, + 19704 => Opcode::VPSRLVQZ256rmk, + 19705 => Opcode::VPSRLVQZ256rmkz, + 19706 => Opcode::VPSRLVQZ256rr, + 19707 => Opcode::VPSRLVQZ256rrk, + 19708 => Opcode::VPSRLVQZ256rrkz, + 19709 => Opcode::VPSRLVQZrm, + 19710 => Opcode::VPSRLVQZrmb, + 19711 => Opcode::VPSRLVQZrmbk, + 19712 => Opcode::VPSRLVQZrmbkz, + 19713 => Opcode::VPSRLVQZrmk, + 19714 => Opcode::VPSRLVQZrmkz, + 19715 => Opcode::VPSRLVQZrr, + 19716 => Opcode::VPSRLVQZrrk, + 19717 => Opcode::VPSRLVQZrrkz, + 19718 => Opcode::VPSRLVQrm, + 19719 => Opcode::VPSRLVQrr, + 19720 => Opcode::VPSRLVWZ128rm, + 19721 => Opcode::VPSRLVWZ128rmk, + 19722 => Opcode::VPSRLVWZ128rmkz, + 19723 => Opcode::VPSRLVWZ128rr, + 19724 => Opcode::VPSRLVWZ128rrk, + 19725 => Opcode::VPSRLVWZ128rrkz, + 19726 => Opcode::VPSRLVWZ256rm, + 19727 => Opcode::VPSRLVWZ256rmk, + 19728 => Opcode::VPSRLVWZ256rmkz, + 19729 => Opcode::VPSRLVWZ256rr, + 19730 => Opcode::VPSRLVWZ256rrk, + 19731 => Opcode::VPSRLVWZ256rrkz, + 19732 => Opcode::VPSRLVWZrm, + 19733 => Opcode::VPSRLVWZrmk, + 19734 => Opcode::VPSRLVWZrmkz, + 19735 => Opcode::VPSRLVWZrr, + 19736 => Opcode::VPSRLVWZrrk, + 19737 => Opcode::VPSRLVWZrrkz, + 19738 => Opcode::VPSRLWYri, + 19739 => Opcode::VPSRLWYrm, + 19740 => Opcode::VPSRLWYrr, + 19741 => Opcode::VPSRLWZ128mi, + 19742 => Opcode::VPSRLWZ128mik, + 19743 => Opcode::VPSRLWZ128mikz, + 19744 => Opcode::VPSRLWZ128ri, + 19745 => Opcode::VPSRLWZ128rik, + 19746 => Opcode::VPSRLWZ128rikz, + 19747 => Opcode::VPSRLWZ128rm, + 19748 => Opcode::VPSRLWZ128rmk, + 19749 => Opcode::VPSRLWZ128rmkz, + 19750 => Opcode::VPSRLWZ128rr, + 19751 => Opcode::VPSRLWZ128rrk, + 19752 => Opcode::VPSRLWZ128rrkz, + 19753 => Opcode::VPSRLWZ256mi, + 19754 => Opcode::VPSRLWZ256mik, + 19755 => Opcode::VPSRLWZ256mikz, + 19756 => Opcode::VPSRLWZ256ri, + 19757 => Opcode::VPSRLWZ256rik, + 19758 => Opcode::VPSRLWZ256rikz, + 19759 => Opcode::VPSRLWZ256rm, + 19760 => Opcode::VPSRLWZ256rmk, + 19761 => Opcode::VPSRLWZ256rmkz, + 19762 => Opcode::VPSRLWZ256rr, + 19763 => Opcode::VPSRLWZ256rrk, + 19764 => Opcode::VPSRLWZ256rrkz, + 19765 => Opcode::VPSRLWZmi, + 19766 => Opcode::VPSRLWZmik, + 19767 => Opcode::VPSRLWZmikz, + 19768 => Opcode::VPSRLWZri, + 19769 => Opcode::VPSRLWZrik, + 19770 => Opcode::VPSRLWZrikz, + 19771 => Opcode::VPSRLWZrm, + 19772 => Opcode::VPSRLWZrmk, + 19773 => Opcode::VPSRLWZrmkz, + 19774 => Opcode::VPSRLWZrr, + 19775 => Opcode::VPSRLWZrrk, + 19776 => Opcode::VPSRLWZrrkz, + 19777 => Opcode::VPSRLWri, + 19778 => Opcode::VPSRLWrm, + 19779 => Opcode::VPSRLWrr, + 19780 => Opcode::VPSUBBYrm, + 19781 => Opcode::VPSUBBYrr, + 19782 => Opcode::VPSUBBZ128rm, + 19783 => Opcode::VPSUBBZ128rmk, + 19784 => Opcode::VPSUBBZ128rmkz, + 19785 => Opcode::VPSUBBZ128rr, + 19786 => Opcode::VPSUBBZ128rrk, + 19787 => Opcode::VPSUBBZ128rrkz, + 19788 => Opcode::VPSUBBZ256rm, + 19789 => Opcode::VPSUBBZ256rmk, + 19790 => Opcode::VPSUBBZ256rmkz, + 19791 => Opcode::VPSUBBZ256rr, + 19792 => Opcode::VPSUBBZ256rrk, + 19793 => Opcode::VPSUBBZ256rrkz, + 19794 => Opcode::VPSUBBZrm, + 19795 => Opcode::VPSUBBZrmk, + 19796 => Opcode::VPSUBBZrmkz, + 19797 => Opcode::VPSUBBZrr, + 19798 => Opcode::VPSUBBZrrk, + 19799 => Opcode::VPSUBBZrrkz, + 19800 => Opcode::VPSUBBrm, + 19801 => Opcode::VPSUBBrr, + 19802 => Opcode::VPSUBDYrm, + 19803 => Opcode::VPSUBDYrr, + 19804 => Opcode::VPSUBDZ128rm, + 19805 => Opcode::VPSUBDZ128rmb, + 19806 => Opcode::VPSUBDZ128rmbk, + 19807 => Opcode::VPSUBDZ128rmbkz, + 19808 => Opcode::VPSUBDZ128rmk, + 19809 => Opcode::VPSUBDZ128rmkz, + 19810 => Opcode::VPSUBDZ128rr, + 19811 => Opcode::VPSUBDZ128rrk, + 19812 => Opcode::VPSUBDZ128rrkz, + 19813 => Opcode::VPSUBDZ256rm, + 19814 => Opcode::VPSUBDZ256rmb, + 19815 => Opcode::VPSUBDZ256rmbk, + 19816 => Opcode::VPSUBDZ256rmbkz, + 19817 => Opcode::VPSUBDZ256rmk, + 19818 => Opcode::VPSUBDZ256rmkz, + 19819 => Opcode::VPSUBDZ256rr, + 19820 => Opcode::VPSUBDZ256rrk, + 19821 => Opcode::VPSUBDZ256rrkz, + 19822 => Opcode::VPSUBDZrm, + 19823 => Opcode::VPSUBDZrmb, + 19824 => Opcode::VPSUBDZrmbk, + 19825 => Opcode::VPSUBDZrmbkz, + 19826 => Opcode::VPSUBDZrmk, + 19827 => Opcode::VPSUBDZrmkz, + 19828 => Opcode::VPSUBDZrr, + 19829 => Opcode::VPSUBDZrrk, + 19830 => Opcode::VPSUBDZrrkz, + 19831 => Opcode::VPSUBDrm, + 19832 => Opcode::VPSUBDrr, + 19833 => Opcode::VPSUBQYrm, + 19834 => Opcode::VPSUBQYrr, + 19835 => Opcode::VPSUBQZ128rm, + 19836 => Opcode::VPSUBQZ128rmb, + 19837 => Opcode::VPSUBQZ128rmbk, + 19838 => Opcode::VPSUBQZ128rmbkz, + 19839 => Opcode::VPSUBQZ128rmk, + 19840 => Opcode::VPSUBQZ128rmkz, + 19841 => Opcode::VPSUBQZ128rr, + 19842 => Opcode::VPSUBQZ128rrk, + 19843 => Opcode::VPSUBQZ128rrkz, + 19844 => Opcode::VPSUBQZ256rm, + 19845 => Opcode::VPSUBQZ256rmb, + 19846 => Opcode::VPSUBQZ256rmbk, + 19847 => Opcode::VPSUBQZ256rmbkz, + 19848 => Opcode::VPSUBQZ256rmk, + 19849 => Opcode::VPSUBQZ256rmkz, + 19850 => Opcode::VPSUBQZ256rr, + 19851 => Opcode::VPSUBQZ256rrk, + 19852 => Opcode::VPSUBQZ256rrkz, + 19853 => Opcode::VPSUBQZrm, + 19854 => Opcode::VPSUBQZrmb, + 19855 => Opcode::VPSUBQZrmbk, + 19856 => Opcode::VPSUBQZrmbkz, + 19857 => Opcode::VPSUBQZrmk, + 19858 => Opcode::VPSUBQZrmkz, + 19859 => Opcode::VPSUBQZrr, + 19860 => Opcode::VPSUBQZrrk, + 19861 => Opcode::VPSUBQZrrkz, + 19862 => Opcode::VPSUBQrm, + 19863 => Opcode::VPSUBQrr, + 19864 => Opcode::VPSUBSBYrm, + 19865 => Opcode::VPSUBSBYrr, + 19866 => Opcode::VPSUBSBZ128rm, + 19867 => Opcode::VPSUBSBZ128rmk, + 19868 => Opcode::VPSUBSBZ128rmkz, + 19869 => Opcode::VPSUBSBZ128rr, + 19870 => Opcode::VPSUBSBZ128rrk, + 19871 => Opcode::VPSUBSBZ128rrkz, + 19872 => Opcode::VPSUBSBZ256rm, + 19873 => Opcode::VPSUBSBZ256rmk, + 19874 => Opcode::VPSUBSBZ256rmkz, + 19875 => Opcode::VPSUBSBZ256rr, + 19876 => Opcode::VPSUBSBZ256rrk, + 19877 => Opcode::VPSUBSBZ256rrkz, + 19878 => Opcode::VPSUBSBZrm, + 19879 => Opcode::VPSUBSBZrmk, + 19880 => Opcode::VPSUBSBZrmkz, + 19881 => Opcode::VPSUBSBZrr, + 19882 => Opcode::VPSUBSBZrrk, + 19883 => Opcode::VPSUBSBZrrkz, + 19884 => Opcode::VPSUBSBrm, + 19885 => Opcode::VPSUBSBrr, + 19886 => Opcode::VPSUBSWYrm, + 19887 => Opcode::VPSUBSWYrr, + 19888 => Opcode::VPSUBSWZ128rm, + 19889 => Opcode::VPSUBSWZ128rmk, + 19890 => Opcode::VPSUBSWZ128rmkz, + 19891 => Opcode::VPSUBSWZ128rr, + 19892 => Opcode::VPSUBSWZ128rrk, + 19893 => Opcode::VPSUBSWZ128rrkz, + 19894 => Opcode::VPSUBSWZ256rm, + 19895 => Opcode::VPSUBSWZ256rmk, + 19896 => Opcode::VPSUBSWZ256rmkz, + 19897 => Opcode::VPSUBSWZ256rr, + 19898 => Opcode::VPSUBSWZ256rrk, + 19899 => Opcode::VPSUBSWZ256rrkz, + 19900 => Opcode::VPSUBSWZrm, + 19901 => Opcode::VPSUBSWZrmk, + 19902 => Opcode::VPSUBSWZrmkz, + 19903 => Opcode::VPSUBSWZrr, + 19904 => Opcode::VPSUBSWZrrk, + 19905 => Opcode::VPSUBSWZrrkz, + 19906 => Opcode::VPSUBSWrm, + 19907 => Opcode::VPSUBSWrr, + 19908 => Opcode::VPSUBUSBYrm, + 19909 => Opcode::VPSUBUSBYrr, + 19910 => Opcode::VPSUBUSBZ128rm, + 19911 => Opcode::VPSUBUSBZ128rmk, + 19912 => Opcode::VPSUBUSBZ128rmkz, + 19913 => Opcode::VPSUBUSBZ128rr, + 19914 => Opcode::VPSUBUSBZ128rrk, + 19915 => Opcode::VPSUBUSBZ128rrkz, + 19916 => Opcode::VPSUBUSBZ256rm, + 19917 => Opcode::VPSUBUSBZ256rmk, + 19918 => Opcode::VPSUBUSBZ256rmkz, + 19919 => Opcode::VPSUBUSBZ256rr, + 19920 => Opcode::VPSUBUSBZ256rrk, + 19921 => Opcode::VPSUBUSBZ256rrkz, + 19922 => Opcode::VPSUBUSBZrm, + 19923 => Opcode::VPSUBUSBZrmk, + 19924 => Opcode::VPSUBUSBZrmkz, + 19925 => Opcode::VPSUBUSBZrr, + 19926 => Opcode::VPSUBUSBZrrk, + 19927 => Opcode::VPSUBUSBZrrkz, + 19928 => Opcode::VPSUBUSBrm, + 19929 => Opcode::VPSUBUSBrr, + 19930 => Opcode::VPSUBUSWYrm, + 19931 => Opcode::VPSUBUSWYrr, + 19932 => Opcode::VPSUBUSWZ128rm, + 19933 => Opcode::VPSUBUSWZ128rmk, + 19934 => Opcode::VPSUBUSWZ128rmkz, + 19935 => Opcode::VPSUBUSWZ128rr, + 19936 => Opcode::VPSUBUSWZ128rrk, + 19937 => Opcode::VPSUBUSWZ128rrkz, + 19938 => Opcode::VPSUBUSWZ256rm, + 19939 => Opcode::VPSUBUSWZ256rmk, + 19940 => Opcode::VPSUBUSWZ256rmkz, + 19941 => Opcode::VPSUBUSWZ256rr, + 19942 => Opcode::VPSUBUSWZ256rrk, + 19943 => Opcode::VPSUBUSWZ256rrkz, + 19944 => Opcode::VPSUBUSWZrm, + 19945 => Opcode::VPSUBUSWZrmk, + 19946 => Opcode::VPSUBUSWZrmkz, + 19947 => Opcode::VPSUBUSWZrr, + 19948 => Opcode::VPSUBUSWZrrk, + 19949 => Opcode::VPSUBUSWZrrkz, + 19950 => Opcode::VPSUBUSWrm, + 19951 => Opcode::VPSUBUSWrr, + 19952 => Opcode::VPSUBWYrm, + 19953 => Opcode::VPSUBWYrr, + 19954 => Opcode::VPSUBWZ128rm, + 19955 => Opcode::VPSUBWZ128rmk, + 19956 => Opcode::VPSUBWZ128rmkz, + 19957 => Opcode::VPSUBWZ128rr, + 19958 => Opcode::VPSUBWZ128rrk, + 19959 => Opcode::VPSUBWZ128rrkz, + 19960 => Opcode::VPSUBWZ256rm, + 19961 => Opcode::VPSUBWZ256rmk, + 19962 => Opcode::VPSUBWZ256rmkz, + 19963 => Opcode::VPSUBWZ256rr, + 19964 => Opcode::VPSUBWZ256rrk, + 19965 => Opcode::VPSUBWZ256rrkz, + 19966 => Opcode::VPSUBWZrm, + 19967 => Opcode::VPSUBWZrmk, + 19968 => Opcode::VPSUBWZrmkz, + 19969 => Opcode::VPSUBWZrr, + 19970 => Opcode::VPSUBWZrrk, + 19971 => Opcode::VPSUBWZrrkz, + 19972 => Opcode::VPSUBWrm, + 19973 => Opcode::VPSUBWrr, + 19974 => Opcode::VPTERNLOGDZ128rmbi, + 19975 => Opcode::VPTERNLOGDZ128rmbik, + 19976 => Opcode::VPTERNLOGDZ128rmbikz, + 19977 => Opcode::VPTERNLOGDZ128rmi, + 19978 => Opcode::VPTERNLOGDZ128rmik, + 19979 => Opcode::VPTERNLOGDZ128rmikz, + 19980 => Opcode::VPTERNLOGDZ128rri, + 19981 => Opcode::VPTERNLOGDZ128rrik, + 19982 => Opcode::VPTERNLOGDZ128rrikz, + 19983 => Opcode::VPTERNLOGDZ256rmbi, + 19984 => Opcode::VPTERNLOGDZ256rmbik, + 19985 => Opcode::VPTERNLOGDZ256rmbikz, + 19986 => Opcode::VPTERNLOGDZ256rmi, + 19987 => Opcode::VPTERNLOGDZ256rmik, + 19988 => Opcode::VPTERNLOGDZ256rmikz, + 19989 => Opcode::VPTERNLOGDZ256rri, + 19990 => Opcode::VPTERNLOGDZ256rrik, + 19991 => Opcode::VPTERNLOGDZ256rrikz, + 19992 => Opcode::VPTERNLOGDZrmbi, + 19993 => Opcode::VPTERNLOGDZrmbik, + 19994 => Opcode::VPTERNLOGDZrmbikz, + 19995 => Opcode::VPTERNLOGDZrmi, + 19996 => Opcode::VPTERNLOGDZrmik, + 19997 => Opcode::VPTERNLOGDZrmikz, + 19998 => Opcode::VPTERNLOGDZrri, + 19999 => Opcode::VPTERNLOGDZrrik, + 20000 => Opcode::VPTERNLOGDZrrikz, + 20001 => Opcode::VPTERNLOGQZ128rmbi, + 20002 => Opcode::VPTERNLOGQZ128rmbik, + 20003 => Opcode::VPTERNLOGQZ128rmbikz, + 20004 => Opcode::VPTERNLOGQZ128rmi, + 20005 => Opcode::VPTERNLOGQZ128rmik, + 20006 => Opcode::VPTERNLOGQZ128rmikz, + 20007 => Opcode::VPTERNLOGQZ128rri, + 20008 => Opcode::VPTERNLOGQZ128rrik, + 20009 => Opcode::VPTERNLOGQZ128rrikz, + 20010 => Opcode::VPTERNLOGQZ256rmbi, + 20011 => Opcode::VPTERNLOGQZ256rmbik, + 20012 => Opcode::VPTERNLOGQZ256rmbikz, + 20013 => Opcode::VPTERNLOGQZ256rmi, + 20014 => Opcode::VPTERNLOGQZ256rmik, + 20015 => Opcode::VPTERNLOGQZ256rmikz, + 20016 => Opcode::VPTERNLOGQZ256rri, + 20017 => Opcode::VPTERNLOGQZ256rrik, + 20018 => Opcode::VPTERNLOGQZ256rrikz, + 20019 => Opcode::VPTERNLOGQZrmbi, + 20020 => Opcode::VPTERNLOGQZrmbik, + 20021 => Opcode::VPTERNLOGQZrmbikz, + 20022 => Opcode::VPTERNLOGQZrmi, + 20023 => Opcode::VPTERNLOGQZrmik, + 20024 => Opcode::VPTERNLOGQZrmikz, + 20025 => Opcode::VPTERNLOGQZrri, + 20026 => Opcode::VPTERNLOGQZrrik, + 20027 => Opcode::VPTERNLOGQZrrikz, + 20028 => Opcode::VPTESTMBZ128rm, + 20029 => Opcode::VPTESTMBZ128rmk, + 20030 => Opcode::VPTESTMBZ128rr, + 20031 => Opcode::VPTESTMBZ128rrk, + 20032 => Opcode::VPTESTMBZ256rm, + 20033 => Opcode::VPTESTMBZ256rmk, + 20034 => Opcode::VPTESTMBZ256rr, + 20035 => Opcode::VPTESTMBZ256rrk, + 20036 => Opcode::VPTESTMBZrm, + 20037 => Opcode::VPTESTMBZrmk, + 20038 => Opcode::VPTESTMBZrr, + 20039 => Opcode::VPTESTMBZrrk, + 20040 => Opcode::VPTESTMDZ128rm, + 20041 => Opcode::VPTESTMDZ128rmb, + 20042 => Opcode::VPTESTMDZ128rmbk, + 20043 => Opcode::VPTESTMDZ128rmk, + 20044 => Opcode::VPTESTMDZ128rr, + 20045 => Opcode::VPTESTMDZ128rrk, + 20046 => Opcode::VPTESTMDZ256rm, + 20047 => Opcode::VPTESTMDZ256rmb, + 20048 => Opcode::VPTESTMDZ256rmbk, + 20049 => Opcode::VPTESTMDZ256rmk, + 20050 => Opcode::VPTESTMDZ256rr, + 20051 => Opcode::VPTESTMDZ256rrk, + 20052 => Opcode::VPTESTMDZrm, + 20053 => Opcode::VPTESTMDZrmb, + 20054 => Opcode::VPTESTMDZrmbk, + 20055 => Opcode::VPTESTMDZrmk, + 20056 => Opcode::VPTESTMDZrr, + 20057 => Opcode::VPTESTMDZrrk, + 20058 => Opcode::VPTESTMQZ128rm, + 20059 => Opcode::VPTESTMQZ128rmb, + 20060 => Opcode::VPTESTMQZ128rmbk, + 20061 => Opcode::VPTESTMQZ128rmk, + 20062 => Opcode::VPTESTMQZ128rr, + 20063 => Opcode::VPTESTMQZ128rrk, + 20064 => Opcode::VPTESTMQZ256rm, + 20065 => Opcode::VPTESTMQZ256rmb, + 20066 => Opcode::VPTESTMQZ256rmbk, + 20067 => Opcode::VPTESTMQZ256rmk, + 20068 => Opcode::VPTESTMQZ256rr, + 20069 => Opcode::VPTESTMQZ256rrk, + 20070 => Opcode::VPTESTMQZrm, + 20071 => Opcode::VPTESTMQZrmb, + 20072 => Opcode::VPTESTMQZrmbk, + 20073 => Opcode::VPTESTMQZrmk, + 20074 => Opcode::VPTESTMQZrr, + 20075 => Opcode::VPTESTMQZrrk, + 20076 => Opcode::VPTESTMWZ128rm, + 20077 => Opcode::VPTESTMWZ128rmk, + 20078 => Opcode::VPTESTMWZ128rr, + 20079 => Opcode::VPTESTMWZ128rrk, + 20080 => Opcode::VPTESTMWZ256rm, + 20081 => Opcode::VPTESTMWZ256rmk, + 20082 => Opcode::VPTESTMWZ256rr, + 20083 => Opcode::VPTESTMWZ256rrk, + 20084 => Opcode::VPTESTMWZrm, + 20085 => Opcode::VPTESTMWZrmk, + 20086 => Opcode::VPTESTMWZrr, + 20087 => Opcode::VPTESTMWZrrk, + 20088 => Opcode::VPTESTNMBZ128rm, + 20089 => Opcode::VPTESTNMBZ128rmk, + 20090 => Opcode::VPTESTNMBZ128rr, + 20091 => Opcode::VPTESTNMBZ128rrk, + 20092 => Opcode::VPTESTNMBZ256rm, + 20093 => Opcode::VPTESTNMBZ256rmk, + 20094 => Opcode::VPTESTNMBZ256rr, + 20095 => Opcode::VPTESTNMBZ256rrk, + 20096 => Opcode::VPTESTNMBZrm, + 20097 => Opcode::VPTESTNMBZrmk, + 20098 => Opcode::VPTESTNMBZrr, + 20099 => Opcode::VPTESTNMBZrrk, + 20100 => Opcode::VPTESTNMDZ128rm, + 20101 => Opcode::VPTESTNMDZ128rmb, + 20102 => Opcode::VPTESTNMDZ128rmbk, + 20103 => Opcode::VPTESTNMDZ128rmk, + 20104 => Opcode::VPTESTNMDZ128rr, + 20105 => Opcode::VPTESTNMDZ128rrk, + 20106 => Opcode::VPTESTNMDZ256rm, + 20107 => Opcode::VPTESTNMDZ256rmb, + 20108 => Opcode::VPTESTNMDZ256rmbk, + 20109 => Opcode::VPTESTNMDZ256rmk, + 20110 => Opcode::VPTESTNMDZ256rr, + 20111 => Opcode::VPTESTNMDZ256rrk, + 20112 => Opcode::VPTESTNMDZrm, + 20113 => Opcode::VPTESTNMDZrmb, + 20114 => Opcode::VPTESTNMDZrmbk, + 20115 => Opcode::VPTESTNMDZrmk, + 20116 => Opcode::VPTESTNMDZrr, + 20117 => Opcode::VPTESTNMDZrrk, + 20118 => Opcode::VPTESTNMQZ128rm, + 20119 => Opcode::VPTESTNMQZ128rmb, + 20120 => Opcode::VPTESTNMQZ128rmbk, + 20121 => Opcode::VPTESTNMQZ128rmk, + 20122 => Opcode::VPTESTNMQZ128rr, + 20123 => Opcode::VPTESTNMQZ128rrk, + 20124 => Opcode::VPTESTNMQZ256rm, + 20125 => Opcode::VPTESTNMQZ256rmb, + 20126 => Opcode::VPTESTNMQZ256rmbk, + 20127 => Opcode::VPTESTNMQZ256rmk, + 20128 => Opcode::VPTESTNMQZ256rr, + 20129 => Opcode::VPTESTNMQZ256rrk, + 20130 => Opcode::VPTESTNMQZrm, + 20131 => Opcode::VPTESTNMQZrmb, + 20132 => Opcode::VPTESTNMQZrmbk, + 20133 => Opcode::VPTESTNMQZrmk, + 20134 => Opcode::VPTESTNMQZrr, + 20135 => Opcode::VPTESTNMQZrrk, + 20136 => Opcode::VPTESTNMWZ128rm, + 20137 => Opcode::VPTESTNMWZ128rmk, + 20138 => Opcode::VPTESTNMWZ128rr, + 20139 => Opcode::VPTESTNMWZ128rrk, + 20140 => Opcode::VPTESTNMWZ256rm, + 20141 => Opcode::VPTESTNMWZ256rmk, + 20142 => Opcode::VPTESTNMWZ256rr, + 20143 => Opcode::VPTESTNMWZ256rrk, + 20144 => Opcode::VPTESTNMWZrm, + 20145 => Opcode::VPTESTNMWZrmk, + 20146 => Opcode::VPTESTNMWZrr, + 20147 => Opcode::VPTESTNMWZrrk, + 20148 => Opcode::VPTESTYrm, + 20149 => Opcode::VPTESTYrr, + 20150 => Opcode::VPTESTrm, + 20151 => Opcode::VPTESTrr, + 20152 => Opcode::VPUNPCKHBWYrm, + 20153 => Opcode::VPUNPCKHBWYrr, + 20154 => Opcode::VPUNPCKHBWZ128rm, + 20155 => Opcode::VPUNPCKHBWZ128rmk, + 20156 => Opcode::VPUNPCKHBWZ128rmkz, + 20157 => Opcode::VPUNPCKHBWZ128rr, + 20158 => Opcode::VPUNPCKHBWZ128rrk, + 20159 => Opcode::VPUNPCKHBWZ128rrkz, + 20160 => Opcode::VPUNPCKHBWZ256rm, + 20161 => Opcode::VPUNPCKHBWZ256rmk, + 20162 => Opcode::VPUNPCKHBWZ256rmkz, + 20163 => Opcode::VPUNPCKHBWZ256rr, + 20164 => Opcode::VPUNPCKHBWZ256rrk, + 20165 => Opcode::VPUNPCKHBWZ256rrkz, + 20166 => Opcode::VPUNPCKHBWZrm, + 20167 => Opcode::VPUNPCKHBWZrmk, + 20168 => Opcode::VPUNPCKHBWZrmkz, + 20169 => Opcode::VPUNPCKHBWZrr, + 20170 => Opcode::VPUNPCKHBWZrrk, + 20171 => Opcode::VPUNPCKHBWZrrkz, + 20172 => Opcode::VPUNPCKHBWrm, + 20173 => Opcode::VPUNPCKHBWrr, + 20174 => Opcode::VPUNPCKHDQYrm, + 20175 => Opcode::VPUNPCKHDQYrr, + 20176 => Opcode::VPUNPCKHDQZ128rm, + 20177 => Opcode::VPUNPCKHDQZ128rmb, + 20178 => Opcode::VPUNPCKHDQZ128rmbk, + 20179 => Opcode::VPUNPCKHDQZ128rmbkz, + 20180 => Opcode::VPUNPCKHDQZ128rmk, + 20181 => Opcode::VPUNPCKHDQZ128rmkz, + 20182 => Opcode::VPUNPCKHDQZ128rr, + 20183 => Opcode::VPUNPCKHDQZ128rrk, + 20184 => Opcode::VPUNPCKHDQZ128rrkz, + 20185 => Opcode::VPUNPCKHDQZ256rm, + 20186 => Opcode::VPUNPCKHDQZ256rmb, + 20187 => Opcode::VPUNPCKHDQZ256rmbk, + 20188 => Opcode::VPUNPCKHDQZ256rmbkz, + 20189 => Opcode::VPUNPCKHDQZ256rmk, + 20190 => Opcode::VPUNPCKHDQZ256rmkz, + 20191 => Opcode::VPUNPCKHDQZ256rr, + 20192 => Opcode::VPUNPCKHDQZ256rrk, + 20193 => Opcode::VPUNPCKHDQZ256rrkz, + 20194 => Opcode::VPUNPCKHDQZrm, + 20195 => Opcode::VPUNPCKHDQZrmb, + 20196 => Opcode::VPUNPCKHDQZrmbk, + 20197 => Opcode::VPUNPCKHDQZrmbkz, + 20198 => Opcode::VPUNPCKHDQZrmk, + 20199 => Opcode::VPUNPCKHDQZrmkz, + 20200 => Opcode::VPUNPCKHDQZrr, + 20201 => Opcode::VPUNPCKHDQZrrk, + 20202 => Opcode::VPUNPCKHDQZrrkz, + 20203 => Opcode::VPUNPCKHDQrm, + 20204 => Opcode::VPUNPCKHDQrr, + 20205 => Opcode::VPUNPCKHQDQYrm, + 20206 => Opcode::VPUNPCKHQDQYrr, + 20207 => Opcode::VPUNPCKHQDQZ128rm, + 20208 => Opcode::VPUNPCKHQDQZ128rmb, + 20209 => Opcode::VPUNPCKHQDQZ128rmbk, + 20210 => Opcode::VPUNPCKHQDQZ128rmbkz, + 20211 => Opcode::VPUNPCKHQDQZ128rmk, + 20212 => Opcode::VPUNPCKHQDQZ128rmkz, + 20213 => Opcode::VPUNPCKHQDQZ128rr, + 20214 => Opcode::VPUNPCKHQDQZ128rrk, + 20215 => Opcode::VPUNPCKHQDQZ128rrkz, + 20216 => Opcode::VPUNPCKHQDQZ256rm, + 20217 => Opcode::VPUNPCKHQDQZ256rmb, + 20218 => Opcode::VPUNPCKHQDQZ256rmbk, + 20219 => Opcode::VPUNPCKHQDQZ256rmbkz, + 20220 => Opcode::VPUNPCKHQDQZ256rmk, + 20221 => Opcode::VPUNPCKHQDQZ256rmkz, + 20222 => Opcode::VPUNPCKHQDQZ256rr, + 20223 => Opcode::VPUNPCKHQDQZ256rrk, + 20224 => Opcode::VPUNPCKHQDQZ256rrkz, + 20225 => Opcode::VPUNPCKHQDQZrm, + 20226 => Opcode::VPUNPCKHQDQZrmb, + 20227 => Opcode::VPUNPCKHQDQZrmbk, + 20228 => Opcode::VPUNPCKHQDQZrmbkz, + 20229 => Opcode::VPUNPCKHQDQZrmk, + 20230 => Opcode::VPUNPCKHQDQZrmkz, + 20231 => Opcode::VPUNPCKHQDQZrr, + 20232 => Opcode::VPUNPCKHQDQZrrk, + 20233 => Opcode::VPUNPCKHQDQZrrkz, + 20234 => Opcode::VPUNPCKHQDQrm, + 20235 => Opcode::VPUNPCKHQDQrr, + 20236 => Opcode::VPUNPCKHWDYrm, + 20237 => Opcode::VPUNPCKHWDYrr, + 20238 => Opcode::VPUNPCKHWDZ128rm, + 20239 => Opcode::VPUNPCKHWDZ128rmk, + 20240 => Opcode::VPUNPCKHWDZ128rmkz, + 20241 => Opcode::VPUNPCKHWDZ128rr, + 20242 => Opcode::VPUNPCKHWDZ128rrk, + 20243 => Opcode::VPUNPCKHWDZ128rrkz, + 20244 => Opcode::VPUNPCKHWDZ256rm, + 20245 => Opcode::VPUNPCKHWDZ256rmk, + 20246 => Opcode::VPUNPCKHWDZ256rmkz, + 20247 => Opcode::VPUNPCKHWDZ256rr, + 20248 => Opcode::VPUNPCKHWDZ256rrk, + 20249 => Opcode::VPUNPCKHWDZ256rrkz, + 20250 => Opcode::VPUNPCKHWDZrm, + 20251 => Opcode::VPUNPCKHWDZrmk, + 20252 => Opcode::VPUNPCKHWDZrmkz, + 20253 => Opcode::VPUNPCKHWDZrr, + 20254 => Opcode::VPUNPCKHWDZrrk, + 20255 => Opcode::VPUNPCKHWDZrrkz, + 20256 => Opcode::VPUNPCKHWDrm, + 20257 => Opcode::VPUNPCKHWDrr, + 20258 => Opcode::VPUNPCKLBWYrm, + 20259 => Opcode::VPUNPCKLBWYrr, + 20260 => Opcode::VPUNPCKLBWZ128rm, + 20261 => Opcode::VPUNPCKLBWZ128rmk, + 20262 => Opcode::VPUNPCKLBWZ128rmkz, + 20263 => Opcode::VPUNPCKLBWZ128rr, + 20264 => Opcode::VPUNPCKLBWZ128rrk, + 20265 => Opcode::VPUNPCKLBWZ128rrkz, + 20266 => Opcode::VPUNPCKLBWZ256rm, + 20267 => Opcode::VPUNPCKLBWZ256rmk, + 20268 => Opcode::VPUNPCKLBWZ256rmkz, + 20269 => Opcode::VPUNPCKLBWZ256rr, + 20270 => Opcode::VPUNPCKLBWZ256rrk, + 20271 => Opcode::VPUNPCKLBWZ256rrkz, + 20272 => Opcode::VPUNPCKLBWZrm, + 20273 => Opcode::VPUNPCKLBWZrmk, + 20274 => Opcode::VPUNPCKLBWZrmkz, + 20275 => Opcode::VPUNPCKLBWZrr, + 20276 => Opcode::VPUNPCKLBWZrrk, + 20277 => Opcode::VPUNPCKLBWZrrkz, + 20278 => Opcode::VPUNPCKLBWrm, + 20279 => Opcode::VPUNPCKLBWrr, + 20280 => Opcode::VPUNPCKLDQYrm, + 20281 => Opcode::VPUNPCKLDQYrr, + 20282 => Opcode::VPUNPCKLDQZ128rm, + 20283 => Opcode::VPUNPCKLDQZ128rmb, + 20284 => Opcode::VPUNPCKLDQZ128rmbk, + 20285 => Opcode::VPUNPCKLDQZ128rmbkz, + 20286 => Opcode::VPUNPCKLDQZ128rmk, + 20287 => Opcode::VPUNPCKLDQZ128rmkz, + 20288 => Opcode::VPUNPCKLDQZ128rr, + 20289 => Opcode::VPUNPCKLDQZ128rrk, + 20290 => Opcode::VPUNPCKLDQZ128rrkz, + 20291 => Opcode::VPUNPCKLDQZ256rm, + 20292 => Opcode::VPUNPCKLDQZ256rmb, + 20293 => Opcode::VPUNPCKLDQZ256rmbk, + 20294 => Opcode::VPUNPCKLDQZ256rmbkz, + 20295 => Opcode::VPUNPCKLDQZ256rmk, + 20296 => Opcode::VPUNPCKLDQZ256rmkz, + 20297 => Opcode::VPUNPCKLDQZ256rr, + 20298 => Opcode::VPUNPCKLDQZ256rrk, + 20299 => Opcode::VPUNPCKLDQZ256rrkz, + 20300 => Opcode::VPUNPCKLDQZrm, + 20301 => Opcode::VPUNPCKLDQZrmb, + 20302 => Opcode::VPUNPCKLDQZrmbk, + 20303 => Opcode::VPUNPCKLDQZrmbkz, + 20304 => Opcode::VPUNPCKLDQZrmk, + 20305 => Opcode::VPUNPCKLDQZrmkz, + 20306 => Opcode::VPUNPCKLDQZrr, + 20307 => Opcode::VPUNPCKLDQZrrk, + 20308 => Opcode::VPUNPCKLDQZrrkz, + 20309 => Opcode::VPUNPCKLDQrm, + 20310 => Opcode::VPUNPCKLDQrr, + 20311 => Opcode::VPUNPCKLQDQYrm, + 20312 => Opcode::VPUNPCKLQDQYrr, + 20313 => Opcode::VPUNPCKLQDQZ128rm, + 20314 => Opcode::VPUNPCKLQDQZ128rmb, + 20315 => Opcode::VPUNPCKLQDQZ128rmbk, + 20316 => Opcode::VPUNPCKLQDQZ128rmbkz, + 20317 => Opcode::VPUNPCKLQDQZ128rmk, + 20318 => Opcode::VPUNPCKLQDQZ128rmkz, + 20319 => Opcode::VPUNPCKLQDQZ128rr, + 20320 => Opcode::VPUNPCKLQDQZ128rrk, + 20321 => Opcode::VPUNPCKLQDQZ128rrkz, + 20322 => Opcode::VPUNPCKLQDQZ256rm, + 20323 => Opcode::VPUNPCKLQDQZ256rmb, + 20324 => Opcode::VPUNPCKLQDQZ256rmbk, + 20325 => Opcode::VPUNPCKLQDQZ256rmbkz, + 20326 => Opcode::VPUNPCKLQDQZ256rmk, + 20327 => Opcode::VPUNPCKLQDQZ256rmkz, + 20328 => Opcode::VPUNPCKLQDQZ256rr, + 20329 => Opcode::VPUNPCKLQDQZ256rrk, + 20330 => Opcode::VPUNPCKLQDQZ256rrkz, + 20331 => Opcode::VPUNPCKLQDQZrm, + 20332 => Opcode::VPUNPCKLQDQZrmb, + 20333 => Opcode::VPUNPCKLQDQZrmbk, + 20334 => Opcode::VPUNPCKLQDQZrmbkz, + 20335 => Opcode::VPUNPCKLQDQZrmk, + 20336 => Opcode::VPUNPCKLQDQZrmkz, + 20337 => Opcode::VPUNPCKLQDQZrr, + 20338 => Opcode::VPUNPCKLQDQZrrk, + 20339 => Opcode::VPUNPCKLQDQZrrkz, + 20340 => Opcode::VPUNPCKLQDQrm, + 20341 => Opcode::VPUNPCKLQDQrr, + 20342 => Opcode::VPUNPCKLWDYrm, + 20343 => Opcode::VPUNPCKLWDYrr, + 20344 => Opcode::VPUNPCKLWDZ128rm, + 20345 => Opcode::VPUNPCKLWDZ128rmk, + 20346 => Opcode::VPUNPCKLWDZ128rmkz, + 20347 => Opcode::VPUNPCKLWDZ128rr, + 20348 => Opcode::VPUNPCKLWDZ128rrk, + 20349 => Opcode::VPUNPCKLWDZ128rrkz, + 20350 => Opcode::VPUNPCKLWDZ256rm, + 20351 => Opcode::VPUNPCKLWDZ256rmk, + 20352 => Opcode::VPUNPCKLWDZ256rmkz, + 20353 => Opcode::VPUNPCKLWDZ256rr, + 20354 => Opcode::VPUNPCKLWDZ256rrk, + 20355 => Opcode::VPUNPCKLWDZ256rrkz, + 20356 => Opcode::VPUNPCKLWDZrm, + 20357 => Opcode::VPUNPCKLWDZrmk, + 20358 => Opcode::VPUNPCKLWDZrmkz, + 20359 => Opcode::VPUNPCKLWDZrr, + 20360 => Opcode::VPUNPCKLWDZrrk, + 20361 => Opcode::VPUNPCKLWDZrrkz, + 20362 => Opcode::VPUNPCKLWDrm, + 20363 => Opcode::VPUNPCKLWDrr, + 20364 => Opcode::VPXORDZ128rm, + 20365 => Opcode::VPXORDZ128rmb, + 20366 => Opcode::VPXORDZ128rmbk, + 20367 => Opcode::VPXORDZ128rmbkz, + 20368 => Opcode::VPXORDZ128rmk, + 20369 => Opcode::VPXORDZ128rmkz, + 20370 => Opcode::VPXORDZ128rr, + 20371 => Opcode::VPXORDZ128rrk, + 20372 => Opcode::VPXORDZ128rrkz, + 20373 => Opcode::VPXORDZ256rm, + 20374 => Opcode::VPXORDZ256rmb, + 20375 => Opcode::VPXORDZ256rmbk, + 20376 => Opcode::VPXORDZ256rmbkz, + 20377 => Opcode::VPXORDZ256rmk, + 20378 => Opcode::VPXORDZ256rmkz, + 20379 => Opcode::VPXORDZ256rr, + 20380 => Opcode::VPXORDZ256rrk, + 20381 => Opcode::VPXORDZ256rrkz, + 20382 => Opcode::VPXORDZrm, + 20383 => Opcode::VPXORDZrmb, + 20384 => Opcode::VPXORDZrmbk, + 20385 => Opcode::VPXORDZrmbkz, + 20386 => Opcode::VPXORDZrmk, + 20387 => Opcode::VPXORDZrmkz, + 20388 => Opcode::VPXORDZrr, + 20389 => Opcode::VPXORDZrrk, + 20390 => Opcode::VPXORDZrrkz, + 20391 => Opcode::VPXORQZ128rm, + 20392 => Opcode::VPXORQZ128rmb, + 20393 => Opcode::VPXORQZ128rmbk, + 20394 => Opcode::VPXORQZ128rmbkz, + 20395 => Opcode::VPXORQZ128rmk, + 20396 => Opcode::VPXORQZ128rmkz, + 20397 => Opcode::VPXORQZ128rr, + 20398 => Opcode::VPXORQZ128rrk, + 20399 => Opcode::VPXORQZ128rrkz, + 20400 => Opcode::VPXORQZ256rm, + 20401 => Opcode::VPXORQZ256rmb, + 20402 => Opcode::VPXORQZ256rmbk, + 20403 => Opcode::VPXORQZ256rmbkz, + 20404 => Opcode::VPXORQZ256rmk, + 20405 => Opcode::VPXORQZ256rmkz, + 20406 => Opcode::VPXORQZ256rr, + 20407 => Opcode::VPXORQZ256rrk, + 20408 => Opcode::VPXORQZ256rrkz, + 20409 => Opcode::VPXORQZrm, + 20410 => Opcode::VPXORQZrmb, + 20411 => Opcode::VPXORQZrmbk, + 20412 => Opcode::VPXORQZrmbkz, + 20413 => Opcode::VPXORQZrmk, + 20414 => Opcode::VPXORQZrmkz, + 20415 => Opcode::VPXORQZrr, + 20416 => Opcode::VPXORQZrrk, + 20417 => Opcode::VPXORQZrrkz, + 20418 => Opcode::VPXORYrm, + 20419 => Opcode::VPXORYrr, + 20420 => Opcode::VPXORrm, + 20421 => Opcode::VPXORrr, + 20422 => Opcode::VRANGEPDZ128rmbi, + 20423 => Opcode::VRANGEPDZ128rmbik, + 20424 => Opcode::VRANGEPDZ128rmbikz, + 20425 => Opcode::VRANGEPDZ128rmi, + 20426 => Opcode::VRANGEPDZ128rmik, + 20427 => Opcode::VRANGEPDZ128rmikz, + 20428 => Opcode::VRANGEPDZ128rri, + 20429 => Opcode::VRANGEPDZ128rrik, + 20430 => Opcode::VRANGEPDZ128rrikz, + 20431 => Opcode::VRANGEPDZ256rmbi, + 20432 => Opcode::VRANGEPDZ256rmbik, + 20433 => Opcode::VRANGEPDZ256rmbikz, + 20434 => Opcode::VRANGEPDZ256rmi, + 20435 => Opcode::VRANGEPDZ256rmik, + 20436 => Opcode::VRANGEPDZ256rmikz, + 20437 => Opcode::VRANGEPDZ256rri, + 20438 => Opcode::VRANGEPDZ256rrik, + 20439 => Opcode::VRANGEPDZ256rrikz, + 20440 => Opcode::VRANGEPDZrmbi, + 20441 => Opcode::VRANGEPDZrmbik, + 20442 => Opcode::VRANGEPDZrmbikz, + 20443 => Opcode::VRANGEPDZrmi, + 20444 => Opcode::VRANGEPDZrmik, + 20445 => Opcode::VRANGEPDZrmikz, + 20446 => Opcode::VRANGEPDZrri, + 20447 => Opcode::VRANGEPDZrrib, + 20448 => Opcode::VRANGEPDZrribk, + 20449 => Opcode::VRANGEPDZrribkz, + 20450 => Opcode::VRANGEPDZrrik, + 20451 => Opcode::VRANGEPDZrrikz, + 20452 => Opcode::VRANGEPSZ128rmbi, + 20453 => Opcode::VRANGEPSZ128rmbik, + 20454 => Opcode::VRANGEPSZ128rmbikz, + 20455 => Opcode::VRANGEPSZ128rmi, + 20456 => Opcode::VRANGEPSZ128rmik, + 20457 => Opcode::VRANGEPSZ128rmikz, + 20458 => Opcode::VRANGEPSZ128rri, + 20459 => Opcode::VRANGEPSZ128rrik, + 20460 => Opcode::VRANGEPSZ128rrikz, + 20461 => Opcode::VRANGEPSZ256rmbi, + 20462 => Opcode::VRANGEPSZ256rmbik, + 20463 => Opcode::VRANGEPSZ256rmbikz, + 20464 => Opcode::VRANGEPSZ256rmi, + 20465 => Opcode::VRANGEPSZ256rmik, + 20466 => Opcode::VRANGEPSZ256rmikz, + 20467 => Opcode::VRANGEPSZ256rri, + 20468 => Opcode::VRANGEPSZ256rrik, + 20469 => Opcode::VRANGEPSZ256rrikz, + 20470 => Opcode::VRANGEPSZrmbi, + 20471 => Opcode::VRANGEPSZrmbik, + 20472 => Opcode::VRANGEPSZrmbikz, + 20473 => Opcode::VRANGEPSZrmi, + 20474 => Opcode::VRANGEPSZrmik, + 20475 => Opcode::VRANGEPSZrmikz, + 20476 => Opcode::VRANGEPSZrri, + 20477 => Opcode::VRANGEPSZrrib, + 20478 => Opcode::VRANGEPSZrribk, + 20479 => Opcode::VRANGEPSZrribkz, + 20480 => Opcode::VRANGEPSZrrik, + 20481 => Opcode::VRANGEPSZrrikz, + 20482 => Opcode::VRANGESDZrmi, + 20483 => Opcode::VRANGESDZrmik, + 20484 => Opcode::VRANGESDZrmikz, + 20485 => Opcode::VRANGESDZrri, + 20486 => Opcode::VRANGESDZrrib, + 20487 => Opcode::VRANGESDZrribk, + 20488 => Opcode::VRANGESDZrribkz, + 20489 => Opcode::VRANGESDZrrik, + 20490 => Opcode::VRANGESDZrrikz, + 20491 => Opcode::VRANGESSZrmi, + 20492 => Opcode::VRANGESSZrmik, + 20493 => Opcode::VRANGESSZrmikz, + 20494 => Opcode::VRANGESSZrri, + 20495 => Opcode::VRANGESSZrrib, + 20496 => Opcode::VRANGESSZrribk, + 20497 => Opcode::VRANGESSZrribkz, + 20498 => Opcode::VRANGESSZrrik, + 20499 => Opcode::VRANGESSZrrikz, + 20500 => Opcode::VRCP14PDZ128m, + 20501 => Opcode::VRCP14PDZ128mb, + 20502 => Opcode::VRCP14PDZ128mbk, + 20503 => Opcode::VRCP14PDZ128mbkz, + 20504 => Opcode::VRCP14PDZ128mk, + 20505 => Opcode::VRCP14PDZ128mkz, + 20506 => Opcode::VRCP14PDZ128r, + 20507 => Opcode::VRCP14PDZ128rk, + 20508 => Opcode::VRCP14PDZ128rkz, + 20509 => Opcode::VRCP14PDZ256m, + 20510 => Opcode::VRCP14PDZ256mb, + 20511 => Opcode::VRCP14PDZ256mbk, + 20512 => Opcode::VRCP14PDZ256mbkz, + 20513 => Opcode::VRCP14PDZ256mk, + 20514 => Opcode::VRCP14PDZ256mkz, + 20515 => Opcode::VRCP14PDZ256r, + 20516 => Opcode::VRCP14PDZ256rk, + 20517 => Opcode::VRCP14PDZ256rkz, + 20518 => Opcode::VRCP14PDZm, + 20519 => Opcode::VRCP14PDZmb, + 20520 => Opcode::VRCP14PDZmbk, + 20521 => Opcode::VRCP14PDZmbkz, + 20522 => Opcode::VRCP14PDZmk, + 20523 => Opcode::VRCP14PDZmkz, + 20524 => Opcode::VRCP14PDZr, + 20525 => Opcode::VRCP14PDZrk, + 20526 => Opcode::VRCP14PDZrkz, + 20527 => Opcode::VRCP14PSZ128m, + 20528 => Opcode::VRCP14PSZ128mb, + 20529 => Opcode::VRCP14PSZ128mbk, + 20530 => Opcode::VRCP14PSZ128mbkz, + 20531 => Opcode::VRCP14PSZ128mk, + 20532 => Opcode::VRCP14PSZ128mkz, + 20533 => Opcode::VRCP14PSZ128r, + 20534 => Opcode::VRCP14PSZ128rk, + 20535 => Opcode::VRCP14PSZ128rkz, + 20536 => Opcode::VRCP14PSZ256m, + 20537 => Opcode::VRCP14PSZ256mb, + 20538 => Opcode::VRCP14PSZ256mbk, + 20539 => Opcode::VRCP14PSZ256mbkz, + 20540 => Opcode::VRCP14PSZ256mk, + 20541 => Opcode::VRCP14PSZ256mkz, + 20542 => Opcode::VRCP14PSZ256r, + 20543 => Opcode::VRCP14PSZ256rk, + 20544 => Opcode::VRCP14PSZ256rkz, + 20545 => Opcode::VRCP14PSZm, + 20546 => Opcode::VRCP14PSZmb, + 20547 => Opcode::VRCP14PSZmbk, + 20548 => Opcode::VRCP14PSZmbkz, + 20549 => Opcode::VRCP14PSZmk, + 20550 => Opcode::VRCP14PSZmkz, + 20551 => Opcode::VRCP14PSZr, + 20552 => Opcode::VRCP14PSZrk, + 20553 => Opcode::VRCP14PSZrkz, + 20554 => Opcode::VRCP14SDZrm, + 20555 => Opcode::VRCP14SDZrmk, + 20556 => Opcode::VRCP14SDZrmkz, + 20557 => Opcode::VRCP14SDZrr, + 20558 => Opcode::VRCP14SDZrrk, + 20559 => Opcode::VRCP14SDZrrkz, + 20560 => Opcode::VRCP14SSZrm, + 20561 => Opcode::VRCP14SSZrmk, + 20562 => Opcode::VRCP14SSZrmkz, + 20563 => Opcode::VRCP14SSZrr, + 20564 => Opcode::VRCP14SSZrrk, + 20565 => Opcode::VRCP14SSZrrkz, + 20566 => Opcode::VRCP28PDZm, + 20567 => Opcode::VRCP28PDZmb, + 20568 => Opcode::VRCP28PDZmbk, + 20569 => Opcode::VRCP28PDZmbkz, + 20570 => Opcode::VRCP28PDZmk, + 20571 => Opcode::VRCP28PDZmkz, + 20572 => Opcode::VRCP28PDZr, + 20573 => Opcode::VRCP28PDZrb, + 20574 => Opcode::VRCP28PDZrbk, + 20575 => Opcode::VRCP28PDZrbkz, + 20576 => Opcode::VRCP28PDZrk, + 20577 => Opcode::VRCP28PDZrkz, + 20578 => Opcode::VRCP28PSZm, + 20579 => Opcode::VRCP28PSZmb, + 20580 => Opcode::VRCP28PSZmbk, + 20581 => Opcode::VRCP28PSZmbkz, + 20582 => Opcode::VRCP28PSZmk, + 20583 => Opcode::VRCP28PSZmkz, + 20584 => Opcode::VRCP28PSZr, + 20585 => Opcode::VRCP28PSZrb, + 20586 => Opcode::VRCP28PSZrbk, + 20587 => Opcode::VRCP28PSZrbkz, + 20588 => Opcode::VRCP28PSZrk, + 20589 => Opcode::VRCP28PSZrkz, + 20590 => Opcode::VRCP28SDZm, + 20591 => Opcode::VRCP28SDZmk, + 20592 => Opcode::VRCP28SDZmkz, + 20593 => Opcode::VRCP28SDZr, + 20594 => Opcode::VRCP28SDZrb, + 20595 => Opcode::VRCP28SDZrbk, + 20596 => Opcode::VRCP28SDZrbkz, + 20597 => Opcode::VRCP28SDZrk, + 20598 => Opcode::VRCP28SDZrkz, + 20599 => Opcode::VRCP28SSZm, + 20600 => Opcode::VRCP28SSZmk, + 20601 => Opcode::VRCP28SSZmkz, + 20602 => Opcode::VRCP28SSZr, + 20603 => Opcode::VRCP28SSZrb, + 20604 => Opcode::VRCP28SSZrbk, + 20605 => Opcode::VRCP28SSZrbkz, + 20606 => Opcode::VRCP28SSZrk, + 20607 => Opcode::VRCP28SSZrkz, + 20608 => Opcode::VRCPBF16Z128m, + 20609 => Opcode::VRCPBF16Z128mb, + 20610 => Opcode::VRCPBF16Z128mbk, + 20611 => Opcode::VRCPBF16Z128mbkz, + 20612 => Opcode::VRCPBF16Z128mk, + 20613 => Opcode::VRCPBF16Z128mkz, + 20614 => Opcode::VRCPBF16Z128r, + 20615 => Opcode::VRCPBF16Z128rk, + 20616 => Opcode::VRCPBF16Z128rkz, + 20617 => Opcode::VRCPBF16Z256m, + 20618 => Opcode::VRCPBF16Z256mb, + 20619 => Opcode::VRCPBF16Z256mbk, + 20620 => Opcode::VRCPBF16Z256mbkz, + 20621 => Opcode::VRCPBF16Z256mk, + 20622 => Opcode::VRCPBF16Z256mkz, + 20623 => Opcode::VRCPBF16Z256r, + 20624 => Opcode::VRCPBF16Z256rk, + 20625 => Opcode::VRCPBF16Z256rkz, + 20626 => Opcode::VRCPBF16Zm, + 20627 => Opcode::VRCPBF16Zmb, + 20628 => Opcode::VRCPBF16Zmbk, + 20629 => Opcode::VRCPBF16Zmbkz, + 20630 => Opcode::VRCPBF16Zmk, + 20631 => Opcode::VRCPBF16Zmkz, + 20632 => Opcode::VRCPBF16Zr, + 20633 => Opcode::VRCPBF16Zrk, + 20634 => Opcode::VRCPBF16Zrkz, + 20635 => Opcode::VRCPPHZ128m, + 20636 => Opcode::VRCPPHZ128mb, + 20637 => Opcode::VRCPPHZ128mbk, + 20638 => Opcode::VRCPPHZ128mbkz, + 20639 => Opcode::VRCPPHZ128mk, + 20640 => Opcode::VRCPPHZ128mkz, + 20641 => Opcode::VRCPPHZ128r, + 20642 => Opcode::VRCPPHZ128rk, + 20643 => Opcode::VRCPPHZ128rkz, + 20644 => Opcode::VRCPPHZ256m, + 20645 => Opcode::VRCPPHZ256mb, + 20646 => Opcode::VRCPPHZ256mbk, + 20647 => Opcode::VRCPPHZ256mbkz, + 20648 => Opcode::VRCPPHZ256mk, + 20649 => Opcode::VRCPPHZ256mkz, + 20650 => Opcode::VRCPPHZ256r, + 20651 => Opcode::VRCPPHZ256rk, + 20652 => Opcode::VRCPPHZ256rkz, + 20653 => Opcode::VRCPPHZm, + 20654 => Opcode::VRCPPHZmb, + 20655 => Opcode::VRCPPHZmbk, + 20656 => Opcode::VRCPPHZmbkz, + 20657 => Opcode::VRCPPHZmk, + 20658 => Opcode::VRCPPHZmkz, + 20659 => Opcode::VRCPPHZr, + 20660 => Opcode::VRCPPHZrk, + 20661 => Opcode::VRCPPHZrkz, + 20662 => Opcode::VRCPPSYm, + 20663 => Opcode::VRCPPSYr, + 20664 => Opcode::VRCPPSm, + 20665 => Opcode::VRCPPSr, + 20666 => Opcode::VRCPSHZrm, + 20667 => Opcode::VRCPSHZrmk, + 20668 => Opcode::VRCPSHZrmkz, + 20669 => Opcode::VRCPSHZrr, + 20670 => Opcode::VRCPSHZrrk, + 20671 => Opcode::VRCPSHZrrkz, + 20672 => Opcode::VRCPSSm, + 20673 => Opcode::VRCPSSm_Int, + 20674 => Opcode::VRCPSSr, + 20675 => Opcode::VRCPSSr_Int, + 20676 => Opcode::VREDUCEBF16Z128rmbi, + 20677 => Opcode::VREDUCEBF16Z128rmbik, + 20678 => Opcode::VREDUCEBF16Z128rmbikz, + 20679 => Opcode::VREDUCEBF16Z128rmi, + 20680 => Opcode::VREDUCEBF16Z128rmik, + 20681 => Opcode::VREDUCEBF16Z128rmikz, + 20682 => Opcode::VREDUCEBF16Z128rri, + 20683 => Opcode::VREDUCEBF16Z128rrik, + 20684 => Opcode::VREDUCEBF16Z128rrikz, + 20685 => Opcode::VREDUCEBF16Z256rmbi, + 20686 => Opcode::VREDUCEBF16Z256rmbik, + 20687 => Opcode::VREDUCEBF16Z256rmbikz, + 20688 => Opcode::VREDUCEBF16Z256rmi, + 20689 => Opcode::VREDUCEBF16Z256rmik, + 20690 => Opcode::VREDUCEBF16Z256rmikz, + 20691 => Opcode::VREDUCEBF16Z256rri, + 20692 => Opcode::VREDUCEBF16Z256rrik, + 20693 => Opcode::VREDUCEBF16Z256rrikz, + 20694 => Opcode::VREDUCEBF16Zrmbi, + 20695 => Opcode::VREDUCEBF16Zrmbik, + 20696 => Opcode::VREDUCEBF16Zrmbikz, + 20697 => Opcode::VREDUCEBF16Zrmi, + 20698 => Opcode::VREDUCEBF16Zrmik, + 20699 => Opcode::VREDUCEBF16Zrmikz, + 20700 => Opcode::VREDUCEBF16Zrri, + 20701 => Opcode::VREDUCEBF16Zrrik, + 20702 => Opcode::VREDUCEBF16Zrrikz, + 20703 => Opcode::VREDUCEPDZ128rmbi, + 20704 => Opcode::VREDUCEPDZ128rmbik, + 20705 => Opcode::VREDUCEPDZ128rmbikz, + 20706 => Opcode::VREDUCEPDZ128rmi, + 20707 => Opcode::VREDUCEPDZ128rmik, + 20708 => Opcode::VREDUCEPDZ128rmikz, + 20709 => Opcode::VREDUCEPDZ128rri, + 20710 => Opcode::VREDUCEPDZ128rrik, + 20711 => Opcode::VREDUCEPDZ128rrikz, + 20712 => Opcode::VREDUCEPDZ256rmbi, + 20713 => Opcode::VREDUCEPDZ256rmbik, + 20714 => Opcode::VREDUCEPDZ256rmbikz, + 20715 => Opcode::VREDUCEPDZ256rmi, + 20716 => Opcode::VREDUCEPDZ256rmik, + 20717 => Opcode::VREDUCEPDZ256rmikz, + 20718 => Opcode::VREDUCEPDZ256rri, + 20719 => Opcode::VREDUCEPDZ256rrik, + 20720 => Opcode::VREDUCEPDZ256rrikz, + 20721 => Opcode::VREDUCEPDZrmbi, + 20722 => Opcode::VREDUCEPDZrmbik, + 20723 => Opcode::VREDUCEPDZrmbikz, + 20724 => Opcode::VREDUCEPDZrmi, + 20725 => Opcode::VREDUCEPDZrmik, + 20726 => Opcode::VREDUCEPDZrmikz, + 20727 => Opcode::VREDUCEPDZrri, + 20728 => Opcode::VREDUCEPDZrrib, + 20729 => Opcode::VREDUCEPDZrribk, + 20730 => Opcode::VREDUCEPDZrribkz, + 20731 => Opcode::VREDUCEPDZrrik, + 20732 => Opcode::VREDUCEPDZrrikz, + 20733 => Opcode::VREDUCEPHZ128rmbi, + 20734 => Opcode::VREDUCEPHZ128rmbik, + 20735 => Opcode::VREDUCEPHZ128rmbikz, + 20736 => Opcode::VREDUCEPHZ128rmi, + 20737 => Opcode::VREDUCEPHZ128rmik, + 20738 => Opcode::VREDUCEPHZ128rmikz, + 20739 => Opcode::VREDUCEPHZ128rri, + 20740 => Opcode::VREDUCEPHZ128rrik, + 20741 => Opcode::VREDUCEPHZ128rrikz, + 20742 => Opcode::VREDUCEPHZ256rmbi, + 20743 => Opcode::VREDUCEPHZ256rmbik, + 20744 => Opcode::VREDUCEPHZ256rmbikz, + 20745 => Opcode::VREDUCEPHZ256rmi, + 20746 => Opcode::VREDUCEPHZ256rmik, + 20747 => Opcode::VREDUCEPHZ256rmikz, + 20748 => Opcode::VREDUCEPHZ256rri, + 20749 => Opcode::VREDUCEPHZ256rrik, + 20750 => Opcode::VREDUCEPHZ256rrikz, + 20751 => Opcode::VREDUCEPHZrmbi, + 20752 => Opcode::VREDUCEPHZrmbik, + 20753 => Opcode::VREDUCEPHZrmbikz, + 20754 => Opcode::VREDUCEPHZrmi, + 20755 => Opcode::VREDUCEPHZrmik, + 20756 => Opcode::VREDUCEPHZrmikz, + 20757 => Opcode::VREDUCEPHZrri, + 20758 => Opcode::VREDUCEPHZrrib, + 20759 => Opcode::VREDUCEPHZrribk, + 20760 => Opcode::VREDUCEPHZrribkz, + 20761 => Opcode::VREDUCEPHZrrik, + 20762 => Opcode::VREDUCEPHZrrikz, + 20763 => Opcode::VREDUCEPSZ128rmbi, + 20764 => Opcode::VREDUCEPSZ128rmbik, + 20765 => Opcode::VREDUCEPSZ128rmbikz, + 20766 => Opcode::VREDUCEPSZ128rmi, + 20767 => Opcode::VREDUCEPSZ128rmik, + 20768 => Opcode::VREDUCEPSZ128rmikz, + 20769 => Opcode::VREDUCEPSZ128rri, + 20770 => Opcode::VREDUCEPSZ128rrik, + 20771 => Opcode::VREDUCEPSZ128rrikz, + 20772 => Opcode::VREDUCEPSZ256rmbi, + 20773 => Opcode::VREDUCEPSZ256rmbik, + 20774 => Opcode::VREDUCEPSZ256rmbikz, + 20775 => Opcode::VREDUCEPSZ256rmi, + 20776 => Opcode::VREDUCEPSZ256rmik, + 20777 => Opcode::VREDUCEPSZ256rmikz, + 20778 => Opcode::VREDUCEPSZ256rri, + 20779 => Opcode::VREDUCEPSZ256rrik, + 20780 => Opcode::VREDUCEPSZ256rrikz, + 20781 => Opcode::VREDUCEPSZrmbi, + 20782 => Opcode::VREDUCEPSZrmbik, + 20783 => Opcode::VREDUCEPSZrmbikz, + 20784 => Opcode::VREDUCEPSZrmi, + 20785 => Opcode::VREDUCEPSZrmik, + 20786 => Opcode::VREDUCEPSZrmikz, + 20787 => Opcode::VREDUCEPSZrri, + 20788 => Opcode::VREDUCEPSZrrib, + 20789 => Opcode::VREDUCEPSZrribk, + 20790 => Opcode::VREDUCEPSZrribkz, + 20791 => Opcode::VREDUCEPSZrrik, + 20792 => Opcode::VREDUCEPSZrrikz, + 20793 => Opcode::VREDUCESDZrmi, + 20794 => Opcode::VREDUCESDZrmik, + 20795 => Opcode::VREDUCESDZrmikz, + 20796 => Opcode::VREDUCESDZrri, + 20797 => Opcode::VREDUCESDZrrib, + 20798 => Opcode::VREDUCESDZrribk, + 20799 => Opcode::VREDUCESDZrribkz, + 20800 => Opcode::VREDUCESDZrrik, + 20801 => Opcode::VREDUCESDZrrikz, + 20802 => Opcode::VREDUCESHZrmi, + 20803 => Opcode::VREDUCESHZrmik, + 20804 => Opcode::VREDUCESHZrmikz, + 20805 => Opcode::VREDUCESHZrri, + 20806 => Opcode::VREDUCESHZrrib, + 20807 => Opcode::VREDUCESHZrribk, + 20808 => Opcode::VREDUCESHZrribkz, + 20809 => Opcode::VREDUCESHZrrik, + 20810 => Opcode::VREDUCESHZrrikz, + 20811 => Opcode::VREDUCESSZrmi, + 20812 => Opcode::VREDUCESSZrmik, + 20813 => Opcode::VREDUCESSZrmikz, + 20814 => Opcode::VREDUCESSZrri, + 20815 => Opcode::VREDUCESSZrrib, + 20816 => Opcode::VREDUCESSZrribk, + 20817 => Opcode::VREDUCESSZrribkz, + 20818 => Opcode::VREDUCESSZrrik, + 20819 => Opcode::VREDUCESSZrrikz, + 20820 => Opcode::VRNDSCALEBF16Z128rmbi, + 20821 => Opcode::VRNDSCALEBF16Z128rmbik, + 20822 => Opcode::VRNDSCALEBF16Z128rmbikz, + 20823 => Opcode::VRNDSCALEBF16Z128rmi, + 20824 => Opcode::VRNDSCALEBF16Z128rmik, + 20825 => Opcode::VRNDSCALEBF16Z128rmikz, + 20826 => Opcode::VRNDSCALEBF16Z128rri, + 20827 => Opcode::VRNDSCALEBF16Z128rrik, + 20828 => Opcode::VRNDSCALEBF16Z128rrikz, + 20829 => Opcode::VRNDSCALEBF16Z256rmbi, + 20830 => Opcode::VRNDSCALEBF16Z256rmbik, + 20831 => Opcode::VRNDSCALEBF16Z256rmbikz, + 20832 => Opcode::VRNDSCALEBF16Z256rmi, + 20833 => Opcode::VRNDSCALEBF16Z256rmik, + 20834 => Opcode::VRNDSCALEBF16Z256rmikz, + 20835 => Opcode::VRNDSCALEBF16Z256rri, + 20836 => Opcode::VRNDSCALEBF16Z256rrik, + 20837 => Opcode::VRNDSCALEBF16Z256rrikz, + 20838 => Opcode::VRNDSCALEBF16Zrmbi, + 20839 => Opcode::VRNDSCALEBF16Zrmbik, + 20840 => Opcode::VRNDSCALEBF16Zrmbikz, + 20841 => Opcode::VRNDSCALEBF16Zrmi, + 20842 => Opcode::VRNDSCALEBF16Zrmik, + 20843 => Opcode::VRNDSCALEBF16Zrmikz, + 20844 => Opcode::VRNDSCALEBF16Zrri, + 20845 => Opcode::VRNDSCALEBF16Zrrik, + 20846 => Opcode::VRNDSCALEBF16Zrrikz, + 20847 => Opcode::VRNDSCALEPDZ128rmbi, + 20848 => Opcode::VRNDSCALEPDZ128rmbik, + 20849 => Opcode::VRNDSCALEPDZ128rmbikz, + 20850 => Opcode::VRNDSCALEPDZ128rmi, + 20851 => Opcode::VRNDSCALEPDZ128rmik, + 20852 => Opcode::VRNDSCALEPDZ128rmikz, + 20853 => Opcode::VRNDSCALEPDZ128rri, + 20854 => Opcode::VRNDSCALEPDZ128rrik, + 20855 => Opcode::VRNDSCALEPDZ128rrikz, + 20856 => Opcode::VRNDSCALEPDZ256rmbi, + 20857 => Opcode::VRNDSCALEPDZ256rmbik, + 20858 => Opcode::VRNDSCALEPDZ256rmbikz, + 20859 => Opcode::VRNDSCALEPDZ256rmi, + 20860 => Opcode::VRNDSCALEPDZ256rmik, + 20861 => Opcode::VRNDSCALEPDZ256rmikz, + 20862 => Opcode::VRNDSCALEPDZ256rri, + 20863 => Opcode::VRNDSCALEPDZ256rrik, + 20864 => Opcode::VRNDSCALEPDZ256rrikz, + 20865 => Opcode::VRNDSCALEPDZrmbi, + 20866 => Opcode::VRNDSCALEPDZrmbik, + 20867 => Opcode::VRNDSCALEPDZrmbikz, + 20868 => Opcode::VRNDSCALEPDZrmi, + 20869 => Opcode::VRNDSCALEPDZrmik, + 20870 => Opcode::VRNDSCALEPDZrmikz, + 20871 => Opcode::VRNDSCALEPDZrri, + 20872 => Opcode::VRNDSCALEPDZrrib, + 20873 => Opcode::VRNDSCALEPDZrribk, + 20874 => Opcode::VRNDSCALEPDZrribkz, + 20875 => Opcode::VRNDSCALEPDZrrik, + 20876 => Opcode::VRNDSCALEPDZrrikz, + 20877 => Opcode::VRNDSCALEPHZ128rmbi, + 20878 => Opcode::VRNDSCALEPHZ128rmbik, + 20879 => Opcode::VRNDSCALEPHZ128rmbikz, + 20880 => Opcode::VRNDSCALEPHZ128rmi, + 20881 => Opcode::VRNDSCALEPHZ128rmik, + 20882 => Opcode::VRNDSCALEPHZ128rmikz, + 20883 => Opcode::VRNDSCALEPHZ128rri, + 20884 => Opcode::VRNDSCALEPHZ128rrik, + 20885 => Opcode::VRNDSCALEPHZ128rrikz, + 20886 => Opcode::VRNDSCALEPHZ256rmbi, + 20887 => Opcode::VRNDSCALEPHZ256rmbik, + 20888 => Opcode::VRNDSCALEPHZ256rmbikz, + 20889 => Opcode::VRNDSCALEPHZ256rmi, + 20890 => Opcode::VRNDSCALEPHZ256rmik, + 20891 => Opcode::VRNDSCALEPHZ256rmikz, + 20892 => Opcode::VRNDSCALEPHZ256rri, + 20893 => Opcode::VRNDSCALEPHZ256rrik, + 20894 => Opcode::VRNDSCALEPHZ256rrikz, + 20895 => Opcode::VRNDSCALEPHZrmbi, + 20896 => Opcode::VRNDSCALEPHZrmbik, + 20897 => Opcode::VRNDSCALEPHZrmbikz, + 20898 => Opcode::VRNDSCALEPHZrmi, + 20899 => Opcode::VRNDSCALEPHZrmik, + 20900 => Opcode::VRNDSCALEPHZrmikz, + 20901 => Opcode::VRNDSCALEPHZrri, + 20902 => Opcode::VRNDSCALEPHZrrib, + 20903 => Opcode::VRNDSCALEPHZrribk, + 20904 => Opcode::VRNDSCALEPHZrribkz, + 20905 => Opcode::VRNDSCALEPHZrrik, + 20906 => Opcode::VRNDSCALEPHZrrikz, + 20907 => Opcode::VRNDSCALEPSZ128rmbi, + 20908 => Opcode::VRNDSCALEPSZ128rmbik, + 20909 => Opcode::VRNDSCALEPSZ128rmbikz, + 20910 => Opcode::VRNDSCALEPSZ128rmi, + 20911 => Opcode::VRNDSCALEPSZ128rmik, + 20912 => Opcode::VRNDSCALEPSZ128rmikz, + 20913 => Opcode::VRNDSCALEPSZ128rri, + 20914 => Opcode::VRNDSCALEPSZ128rrik, + 20915 => Opcode::VRNDSCALEPSZ128rrikz, + 20916 => Opcode::VRNDSCALEPSZ256rmbi, + 20917 => Opcode::VRNDSCALEPSZ256rmbik, + 20918 => Opcode::VRNDSCALEPSZ256rmbikz, + 20919 => Opcode::VRNDSCALEPSZ256rmi, + 20920 => Opcode::VRNDSCALEPSZ256rmik, + 20921 => Opcode::VRNDSCALEPSZ256rmikz, + 20922 => Opcode::VRNDSCALEPSZ256rri, + 20923 => Opcode::VRNDSCALEPSZ256rrik, + 20924 => Opcode::VRNDSCALEPSZ256rrikz, + 20925 => Opcode::VRNDSCALEPSZrmbi, + 20926 => Opcode::VRNDSCALEPSZrmbik, + 20927 => Opcode::VRNDSCALEPSZrmbikz, + 20928 => Opcode::VRNDSCALEPSZrmi, + 20929 => Opcode::VRNDSCALEPSZrmik, + 20930 => Opcode::VRNDSCALEPSZrmikz, + 20931 => Opcode::VRNDSCALEPSZrri, + 20932 => Opcode::VRNDSCALEPSZrrib, + 20933 => Opcode::VRNDSCALEPSZrribk, + 20934 => Opcode::VRNDSCALEPSZrribkz, + 20935 => Opcode::VRNDSCALEPSZrrik, + 20936 => Opcode::VRNDSCALEPSZrrikz, + 20937 => Opcode::VRNDSCALESDZrmi, + 20938 => Opcode::VRNDSCALESDZrmi_Int, + 20939 => Opcode::VRNDSCALESDZrmik_Int, + 20940 => Opcode::VRNDSCALESDZrmikz_Int, + 20941 => Opcode::VRNDSCALESDZrri, + 20942 => Opcode::VRNDSCALESDZrri_Int, + 20943 => Opcode::VRNDSCALESDZrrib_Int, + 20944 => Opcode::VRNDSCALESDZrribk_Int, + 20945 => Opcode::VRNDSCALESDZrribkz_Int, + 20946 => Opcode::VRNDSCALESDZrrik_Int, + 20947 => Opcode::VRNDSCALESDZrrikz_Int, + 20948 => Opcode::VRNDSCALESHZrmi, + 20949 => Opcode::VRNDSCALESHZrmi_Int, + 20950 => Opcode::VRNDSCALESHZrmik_Int, + 20951 => Opcode::VRNDSCALESHZrmikz_Int, + 20952 => Opcode::VRNDSCALESHZrri, + 20953 => Opcode::VRNDSCALESHZrri_Int, + 20954 => Opcode::VRNDSCALESHZrrib_Int, + 20955 => Opcode::VRNDSCALESHZrribk_Int, + 20956 => Opcode::VRNDSCALESHZrribkz_Int, + 20957 => Opcode::VRNDSCALESHZrrik_Int, + 20958 => Opcode::VRNDSCALESHZrrikz_Int, + 20959 => Opcode::VRNDSCALESSZrmi, + 20960 => Opcode::VRNDSCALESSZrmi_Int, + 20961 => Opcode::VRNDSCALESSZrmik_Int, + 20962 => Opcode::VRNDSCALESSZrmikz_Int, + 20963 => Opcode::VRNDSCALESSZrri, + 20964 => Opcode::VRNDSCALESSZrri_Int, + 20965 => Opcode::VRNDSCALESSZrrib_Int, + 20966 => Opcode::VRNDSCALESSZrribk_Int, + 20967 => Opcode::VRNDSCALESSZrribkz_Int, + 20968 => Opcode::VRNDSCALESSZrrik_Int, + 20969 => Opcode::VRNDSCALESSZrrikz_Int, + 20970 => Opcode::VROUNDPDYmi, + 20971 => Opcode::VROUNDPDYri, + 20972 => Opcode::VROUNDPDmi, + 20973 => Opcode::VROUNDPDri, + 20974 => Opcode::VROUNDPSYmi, + 20975 => Opcode::VROUNDPSYri, + 20976 => Opcode::VROUNDPSmi, + 20977 => Opcode::VROUNDPSri, + 20978 => Opcode::VROUNDSDmi, + 20979 => Opcode::VROUNDSDmi_Int, + 20980 => Opcode::VROUNDSDri, + 20981 => Opcode::VROUNDSDri_Int, + 20982 => Opcode::VROUNDSSmi, + 20983 => Opcode::VROUNDSSmi_Int, + 20984 => Opcode::VROUNDSSri, + 20985 => Opcode::VROUNDSSri_Int, + 20986 => Opcode::VRSQRT14PDZ128m, + 20987 => Opcode::VRSQRT14PDZ128mb, + 20988 => Opcode::VRSQRT14PDZ128mbk, + 20989 => Opcode::VRSQRT14PDZ128mbkz, + 20990 => Opcode::VRSQRT14PDZ128mk, + 20991 => Opcode::VRSQRT14PDZ128mkz, + 20992 => Opcode::VRSQRT14PDZ128r, + 20993 => Opcode::VRSQRT14PDZ128rk, + 20994 => Opcode::VRSQRT14PDZ128rkz, + 20995 => Opcode::VRSQRT14PDZ256m, + 20996 => Opcode::VRSQRT14PDZ256mb, + 20997 => Opcode::VRSQRT14PDZ256mbk, + 20998 => Opcode::VRSQRT14PDZ256mbkz, + 20999 => Opcode::VRSQRT14PDZ256mk, + 21000 => Opcode::VRSQRT14PDZ256mkz, + 21001 => Opcode::VRSQRT14PDZ256r, + 21002 => Opcode::VRSQRT14PDZ256rk, + 21003 => Opcode::VRSQRT14PDZ256rkz, + 21004 => Opcode::VRSQRT14PDZm, + 21005 => Opcode::VRSQRT14PDZmb, + 21006 => Opcode::VRSQRT14PDZmbk, + 21007 => Opcode::VRSQRT14PDZmbkz, + 21008 => Opcode::VRSQRT14PDZmk, + 21009 => Opcode::VRSQRT14PDZmkz, + 21010 => Opcode::VRSQRT14PDZr, + 21011 => Opcode::VRSQRT14PDZrk, + 21012 => Opcode::VRSQRT14PDZrkz, + 21013 => Opcode::VRSQRT14PSZ128m, + 21014 => Opcode::VRSQRT14PSZ128mb, + 21015 => Opcode::VRSQRT14PSZ128mbk, + 21016 => Opcode::VRSQRT14PSZ128mbkz, + 21017 => Opcode::VRSQRT14PSZ128mk, + 21018 => Opcode::VRSQRT14PSZ128mkz, + 21019 => Opcode::VRSQRT14PSZ128r, + 21020 => Opcode::VRSQRT14PSZ128rk, + 21021 => Opcode::VRSQRT14PSZ128rkz, + 21022 => Opcode::VRSQRT14PSZ256m, + 21023 => Opcode::VRSQRT14PSZ256mb, + 21024 => Opcode::VRSQRT14PSZ256mbk, + 21025 => Opcode::VRSQRT14PSZ256mbkz, + 21026 => Opcode::VRSQRT14PSZ256mk, + 21027 => Opcode::VRSQRT14PSZ256mkz, + 21028 => Opcode::VRSQRT14PSZ256r, + 21029 => Opcode::VRSQRT14PSZ256rk, + 21030 => Opcode::VRSQRT14PSZ256rkz, + 21031 => Opcode::VRSQRT14PSZm, + 21032 => Opcode::VRSQRT14PSZmb, + 21033 => Opcode::VRSQRT14PSZmbk, + 21034 => Opcode::VRSQRT14PSZmbkz, + 21035 => Opcode::VRSQRT14PSZmk, + 21036 => Opcode::VRSQRT14PSZmkz, + 21037 => Opcode::VRSQRT14PSZr, + 21038 => Opcode::VRSQRT14PSZrk, + 21039 => Opcode::VRSQRT14PSZrkz, + 21040 => Opcode::VRSQRT14SDZrm, + 21041 => Opcode::VRSQRT14SDZrmk, + 21042 => Opcode::VRSQRT14SDZrmkz, + 21043 => Opcode::VRSQRT14SDZrr, + 21044 => Opcode::VRSQRT14SDZrrk, + 21045 => Opcode::VRSQRT14SDZrrkz, + 21046 => Opcode::VRSQRT14SSZrm, + 21047 => Opcode::VRSQRT14SSZrmk, + 21048 => Opcode::VRSQRT14SSZrmkz, + 21049 => Opcode::VRSQRT14SSZrr, + 21050 => Opcode::VRSQRT14SSZrrk, + 21051 => Opcode::VRSQRT14SSZrrkz, + 21052 => Opcode::VRSQRT28PDZm, + 21053 => Opcode::VRSQRT28PDZmb, + 21054 => Opcode::VRSQRT28PDZmbk, + 21055 => Opcode::VRSQRT28PDZmbkz, + 21056 => Opcode::VRSQRT28PDZmk, + 21057 => Opcode::VRSQRT28PDZmkz, + 21058 => Opcode::VRSQRT28PDZr, + 21059 => Opcode::VRSQRT28PDZrb, + 21060 => Opcode::VRSQRT28PDZrbk, + 21061 => Opcode::VRSQRT28PDZrbkz, + 21062 => Opcode::VRSQRT28PDZrk, + 21063 => Opcode::VRSQRT28PDZrkz, + 21064 => Opcode::VRSQRT28PSZm, + 21065 => Opcode::VRSQRT28PSZmb, + 21066 => Opcode::VRSQRT28PSZmbk, + 21067 => Opcode::VRSQRT28PSZmbkz, + 21068 => Opcode::VRSQRT28PSZmk, + 21069 => Opcode::VRSQRT28PSZmkz, + 21070 => Opcode::VRSQRT28PSZr, + 21071 => Opcode::VRSQRT28PSZrb, + 21072 => Opcode::VRSQRT28PSZrbk, + 21073 => Opcode::VRSQRT28PSZrbkz, + 21074 => Opcode::VRSQRT28PSZrk, + 21075 => Opcode::VRSQRT28PSZrkz, + 21076 => Opcode::VRSQRT28SDZm, + 21077 => Opcode::VRSQRT28SDZmk, + 21078 => Opcode::VRSQRT28SDZmkz, + 21079 => Opcode::VRSQRT28SDZr, + 21080 => Opcode::VRSQRT28SDZrb, + 21081 => Opcode::VRSQRT28SDZrbk, + 21082 => Opcode::VRSQRT28SDZrbkz, + 21083 => Opcode::VRSQRT28SDZrk, + 21084 => Opcode::VRSQRT28SDZrkz, + 21085 => Opcode::VRSQRT28SSZm, + 21086 => Opcode::VRSQRT28SSZmk, + 21087 => Opcode::VRSQRT28SSZmkz, + 21088 => Opcode::VRSQRT28SSZr, + 21089 => Opcode::VRSQRT28SSZrb, + 21090 => Opcode::VRSQRT28SSZrbk, + 21091 => Opcode::VRSQRT28SSZrbkz, + 21092 => Opcode::VRSQRT28SSZrk, + 21093 => Opcode::VRSQRT28SSZrkz, + 21094 => Opcode::VRSQRTBF16Z128m, + 21095 => Opcode::VRSQRTBF16Z128mb, + 21096 => Opcode::VRSQRTBF16Z128mbk, + 21097 => Opcode::VRSQRTBF16Z128mbkz, + 21098 => Opcode::VRSQRTBF16Z128mk, + 21099 => Opcode::VRSQRTBF16Z128mkz, + 21100 => Opcode::VRSQRTBF16Z128r, + 21101 => Opcode::VRSQRTBF16Z128rk, + 21102 => Opcode::VRSQRTBF16Z128rkz, + 21103 => Opcode::VRSQRTBF16Z256m, + 21104 => Opcode::VRSQRTBF16Z256mb, + 21105 => Opcode::VRSQRTBF16Z256mbk, + 21106 => Opcode::VRSQRTBF16Z256mbkz, + 21107 => Opcode::VRSQRTBF16Z256mk, + 21108 => Opcode::VRSQRTBF16Z256mkz, + 21109 => Opcode::VRSQRTBF16Z256r, + 21110 => Opcode::VRSQRTBF16Z256rk, + 21111 => Opcode::VRSQRTBF16Z256rkz, + 21112 => Opcode::VRSQRTBF16Zm, + 21113 => Opcode::VRSQRTBF16Zmb, + 21114 => Opcode::VRSQRTBF16Zmbk, + 21115 => Opcode::VRSQRTBF16Zmbkz, + 21116 => Opcode::VRSQRTBF16Zmk, + 21117 => Opcode::VRSQRTBF16Zmkz, + 21118 => Opcode::VRSQRTBF16Zr, + 21119 => Opcode::VRSQRTBF16Zrk, + 21120 => Opcode::VRSQRTBF16Zrkz, + 21121 => Opcode::VRSQRTPHZ128m, + 21122 => Opcode::VRSQRTPHZ128mb, + 21123 => Opcode::VRSQRTPHZ128mbk, + 21124 => Opcode::VRSQRTPHZ128mbkz, + 21125 => Opcode::VRSQRTPHZ128mk, + 21126 => Opcode::VRSQRTPHZ128mkz, + 21127 => Opcode::VRSQRTPHZ128r, + 21128 => Opcode::VRSQRTPHZ128rk, + 21129 => Opcode::VRSQRTPHZ128rkz, + 21130 => Opcode::VRSQRTPHZ256m, + 21131 => Opcode::VRSQRTPHZ256mb, + 21132 => Opcode::VRSQRTPHZ256mbk, + 21133 => Opcode::VRSQRTPHZ256mbkz, + 21134 => Opcode::VRSQRTPHZ256mk, + 21135 => Opcode::VRSQRTPHZ256mkz, + 21136 => Opcode::VRSQRTPHZ256r, + 21137 => Opcode::VRSQRTPHZ256rk, + 21138 => Opcode::VRSQRTPHZ256rkz, + 21139 => Opcode::VRSQRTPHZm, + 21140 => Opcode::VRSQRTPHZmb, + 21141 => Opcode::VRSQRTPHZmbk, + 21142 => Opcode::VRSQRTPHZmbkz, + 21143 => Opcode::VRSQRTPHZmk, + 21144 => Opcode::VRSQRTPHZmkz, + 21145 => Opcode::VRSQRTPHZr, + 21146 => Opcode::VRSQRTPHZrk, + 21147 => Opcode::VRSQRTPHZrkz, + 21148 => Opcode::VRSQRTPSYm, + 21149 => Opcode::VRSQRTPSYr, + 21150 => Opcode::VRSQRTPSm, + 21151 => Opcode::VRSQRTPSr, + 21152 => Opcode::VRSQRTSHZrm, + 21153 => Opcode::VRSQRTSHZrmk, + 21154 => Opcode::VRSQRTSHZrmkz, + 21155 => Opcode::VRSQRTSHZrr, + 21156 => Opcode::VRSQRTSHZrrk, + 21157 => Opcode::VRSQRTSHZrrkz, + 21158 => Opcode::VRSQRTSSm, + 21159 => Opcode::VRSQRTSSm_Int, + 21160 => Opcode::VRSQRTSSr, + 21161 => Opcode::VRSQRTSSr_Int, + 21162 => Opcode::VSCALEFBF16Z128rm, + 21163 => Opcode::VSCALEFBF16Z128rmb, + 21164 => Opcode::VSCALEFBF16Z128rmbk, + 21165 => Opcode::VSCALEFBF16Z128rmbkz, + 21166 => Opcode::VSCALEFBF16Z128rmk, + 21167 => Opcode::VSCALEFBF16Z128rmkz, + 21168 => Opcode::VSCALEFBF16Z128rr, + 21169 => Opcode::VSCALEFBF16Z128rrk, + 21170 => Opcode::VSCALEFBF16Z128rrkz, + 21171 => Opcode::VSCALEFBF16Z256rm, + 21172 => Opcode::VSCALEFBF16Z256rmb, + 21173 => Opcode::VSCALEFBF16Z256rmbk, + 21174 => Opcode::VSCALEFBF16Z256rmbkz, + 21175 => Opcode::VSCALEFBF16Z256rmk, + 21176 => Opcode::VSCALEFBF16Z256rmkz, + 21177 => Opcode::VSCALEFBF16Z256rr, + 21178 => Opcode::VSCALEFBF16Z256rrk, + 21179 => Opcode::VSCALEFBF16Z256rrkz, + 21180 => Opcode::VSCALEFBF16Zrm, + 21181 => Opcode::VSCALEFBF16Zrmb, + 21182 => Opcode::VSCALEFBF16Zrmbk, + 21183 => Opcode::VSCALEFBF16Zrmbkz, + 21184 => Opcode::VSCALEFBF16Zrmk, + 21185 => Opcode::VSCALEFBF16Zrmkz, + 21186 => Opcode::VSCALEFBF16Zrr, + 21187 => Opcode::VSCALEFBF16Zrrk, + 21188 => Opcode::VSCALEFBF16Zrrkz, + 21189 => Opcode::VSCALEFPDZ128rm, + 21190 => Opcode::VSCALEFPDZ128rmb, + 21191 => Opcode::VSCALEFPDZ128rmbk, + 21192 => Opcode::VSCALEFPDZ128rmbkz, + 21193 => Opcode::VSCALEFPDZ128rmk, + 21194 => Opcode::VSCALEFPDZ128rmkz, + 21195 => Opcode::VSCALEFPDZ128rr, + 21196 => Opcode::VSCALEFPDZ128rrk, + 21197 => Opcode::VSCALEFPDZ128rrkz, + 21198 => Opcode::VSCALEFPDZ256rm, + 21199 => Opcode::VSCALEFPDZ256rmb, + 21200 => Opcode::VSCALEFPDZ256rmbk, + 21201 => Opcode::VSCALEFPDZ256rmbkz, + 21202 => Opcode::VSCALEFPDZ256rmk, + 21203 => Opcode::VSCALEFPDZ256rmkz, + 21204 => Opcode::VSCALEFPDZ256rr, + 21205 => Opcode::VSCALEFPDZ256rrk, + 21206 => Opcode::VSCALEFPDZ256rrkz, + 21207 => Opcode::VSCALEFPDZrm, + 21208 => Opcode::VSCALEFPDZrmb, + 21209 => Opcode::VSCALEFPDZrmbk, + 21210 => Opcode::VSCALEFPDZrmbkz, + 21211 => Opcode::VSCALEFPDZrmk, + 21212 => Opcode::VSCALEFPDZrmkz, + 21213 => Opcode::VSCALEFPDZrr, + 21214 => Opcode::VSCALEFPDZrrb, + 21215 => Opcode::VSCALEFPDZrrbk, + 21216 => Opcode::VSCALEFPDZrrbkz, + 21217 => Opcode::VSCALEFPDZrrk, + 21218 => Opcode::VSCALEFPDZrrkz, + 21219 => Opcode::VSCALEFPHZ128rm, + 21220 => Opcode::VSCALEFPHZ128rmb, + 21221 => Opcode::VSCALEFPHZ128rmbk, + 21222 => Opcode::VSCALEFPHZ128rmbkz, + 21223 => Opcode::VSCALEFPHZ128rmk, + 21224 => Opcode::VSCALEFPHZ128rmkz, + 21225 => Opcode::VSCALEFPHZ128rr, + 21226 => Opcode::VSCALEFPHZ128rrk, + 21227 => Opcode::VSCALEFPHZ128rrkz, + 21228 => Opcode::VSCALEFPHZ256rm, + 21229 => Opcode::VSCALEFPHZ256rmb, + 21230 => Opcode::VSCALEFPHZ256rmbk, + 21231 => Opcode::VSCALEFPHZ256rmbkz, + 21232 => Opcode::VSCALEFPHZ256rmk, + 21233 => Opcode::VSCALEFPHZ256rmkz, + 21234 => Opcode::VSCALEFPHZ256rr, + 21235 => Opcode::VSCALEFPHZ256rrk, + 21236 => Opcode::VSCALEFPHZ256rrkz, + 21237 => Opcode::VSCALEFPHZrm, + 21238 => Opcode::VSCALEFPHZrmb, + 21239 => Opcode::VSCALEFPHZrmbk, + 21240 => Opcode::VSCALEFPHZrmbkz, + 21241 => Opcode::VSCALEFPHZrmk, + 21242 => Opcode::VSCALEFPHZrmkz, + 21243 => Opcode::VSCALEFPHZrr, + 21244 => Opcode::VSCALEFPHZrrb, + 21245 => Opcode::VSCALEFPHZrrbk, + 21246 => Opcode::VSCALEFPHZrrbkz, + 21247 => Opcode::VSCALEFPHZrrk, + 21248 => Opcode::VSCALEFPHZrrkz, + 21249 => Opcode::VSCALEFPSZ128rm, + 21250 => Opcode::VSCALEFPSZ128rmb, + 21251 => Opcode::VSCALEFPSZ128rmbk, + 21252 => Opcode::VSCALEFPSZ128rmbkz, + 21253 => Opcode::VSCALEFPSZ128rmk, + 21254 => Opcode::VSCALEFPSZ128rmkz, + 21255 => Opcode::VSCALEFPSZ128rr, + 21256 => Opcode::VSCALEFPSZ128rrk, + 21257 => Opcode::VSCALEFPSZ128rrkz, + 21258 => Opcode::VSCALEFPSZ256rm, + 21259 => Opcode::VSCALEFPSZ256rmb, + 21260 => Opcode::VSCALEFPSZ256rmbk, + 21261 => Opcode::VSCALEFPSZ256rmbkz, + 21262 => Opcode::VSCALEFPSZ256rmk, + 21263 => Opcode::VSCALEFPSZ256rmkz, + 21264 => Opcode::VSCALEFPSZ256rr, + 21265 => Opcode::VSCALEFPSZ256rrk, + 21266 => Opcode::VSCALEFPSZ256rrkz, + 21267 => Opcode::VSCALEFPSZrm, + 21268 => Opcode::VSCALEFPSZrmb, + 21269 => Opcode::VSCALEFPSZrmbk, + 21270 => Opcode::VSCALEFPSZrmbkz, + 21271 => Opcode::VSCALEFPSZrmk, + 21272 => Opcode::VSCALEFPSZrmkz, + 21273 => Opcode::VSCALEFPSZrr, + 21274 => Opcode::VSCALEFPSZrrb, + 21275 => Opcode::VSCALEFPSZrrbk, + 21276 => Opcode::VSCALEFPSZrrbkz, + 21277 => Opcode::VSCALEFPSZrrk, + 21278 => Opcode::VSCALEFPSZrrkz, + 21279 => Opcode::VSCALEFSDZrm, + 21280 => Opcode::VSCALEFSDZrmk, + 21281 => Opcode::VSCALEFSDZrmkz, + 21282 => Opcode::VSCALEFSDZrr, + 21283 => Opcode::VSCALEFSDZrrb_Int, + 21284 => Opcode::VSCALEFSDZrrbk_Int, + 21285 => Opcode::VSCALEFSDZrrbkz_Int, + 21286 => Opcode::VSCALEFSDZrrk, + 21287 => Opcode::VSCALEFSDZrrkz, + 21288 => Opcode::VSCALEFSHZrm, + 21289 => Opcode::VSCALEFSHZrmk, + 21290 => Opcode::VSCALEFSHZrmkz, + 21291 => Opcode::VSCALEFSHZrr, + 21292 => Opcode::VSCALEFSHZrrb_Int, + 21293 => Opcode::VSCALEFSHZrrbk_Int, + 21294 => Opcode::VSCALEFSHZrrbkz_Int, + 21295 => Opcode::VSCALEFSHZrrk, + 21296 => Opcode::VSCALEFSHZrrkz, + 21297 => Opcode::VSCALEFSSZrm, + 21298 => Opcode::VSCALEFSSZrmk, + 21299 => Opcode::VSCALEFSSZrmkz, + 21300 => Opcode::VSCALEFSSZrr, + 21301 => Opcode::VSCALEFSSZrrb_Int, + 21302 => Opcode::VSCALEFSSZrrbk_Int, + 21303 => Opcode::VSCALEFSSZrrbkz_Int, + 21304 => Opcode::VSCALEFSSZrrk, + 21305 => Opcode::VSCALEFSSZrrkz, + 21306 => Opcode::VSCATTERDPDZ128mr, + 21307 => Opcode::VSCATTERDPDZ256mr, + 21308 => Opcode::VSCATTERDPDZmr, + 21309 => Opcode::VSCATTERDPSZ128mr, + 21310 => Opcode::VSCATTERDPSZ256mr, + 21311 => Opcode::VSCATTERDPSZmr, + 21312 => Opcode::VSCATTERPF0DPDm, + 21313 => Opcode::VSCATTERPF0DPSm, + 21314 => Opcode::VSCATTERPF0QPDm, + 21315 => Opcode::VSCATTERPF0QPSm, + 21316 => Opcode::VSCATTERPF1DPDm, + 21317 => Opcode::VSCATTERPF1DPSm, + 21318 => Opcode::VSCATTERPF1QPDm, + 21319 => Opcode::VSCATTERPF1QPSm, + 21320 => Opcode::VSCATTERQPDZ128mr, + 21321 => Opcode::VSCATTERQPDZ256mr, + 21322 => Opcode::VSCATTERQPDZmr, + 21323 => Opcode::VSCATTERQPSZ128mr, + 21324 => Opcode::VSCATTERQPSZ256mr, + 21325 => Opcode::VSCATTERQPSZmr, + 21326 => Opcode::VSHA512MSG1rr, + 21327 => Opcode::VSHA512MSG2rr, + 21328 => Opcode::VSHA512RNDS2rr, + 21329 => Opcode::VSHUFF32X4Z256rmbi, + 21330 => Opcode::VSHUFF32X4Z256rmbik, + 21331 => Opcode::VSHUFF32X4Z256rmbikz, + 21332 => Opcode::VSHUFF32X4Z256rmi, + 21333 => Opcode::VSHUFF32X4Z256rmik, + 21334 => Opcode::VSHUFF32X4Z256rmikz, + 21335 => Opcode::VSHUFF32X4Z256rri, + 21336 => Opcode::VSHUFF32X4Z256rrik, + 21337 => Opcode::VSHUFF32X4Z256rrikz, + 21338 => Opcode::VSHUFF32X4Zrmbi, + 21339 => Opcode::VSHUFF32X4Zrmbik, + 21340 => Opcode::VSHUFF32X4Zrmbikz, + 21341 => Opcode::VSHUFF32X4Zrmi, + 21342 => Opcode::VSHUFF32X4Zrmik, + 21343 => Opcode::VSHUFF32X4Zrmikz, + 21344 => Opcode::VSHUFF32X4Zrri, + 21345 => Opcode::VSHUFF32X4Zrrik, + 21346 => Opcode::VSHUFF32X4Zrrikz, + 21347 => Opcode::VSHUFF64X2Z256rmbi, + 21348 => Opcode::VSHUFF64X2Z256rmbik, + 21349 => Opcode::VSHUFF64X2Z256rmbikz, + 21350 => Opcode::VSHUFF64X2Z256rmi, + 21351 => Opcode::VSHUFF64X2Z256rmik, + 21352 => Opcode::VSHUFF64X2Z256rmikz, + 21353 => Opcode::VSHUFF64X2Z256rri, + 21354 => Opcode::VSHUFF64X2Z256rrik, + 21355 => Opcode::VSHUFF64X2Z256rrikz, + 21356 => Opcode::VSHUFF64X2Zrmbi, + 21357 => Opcode::VSHUFF64X2Zrmbik, + 21358 => Opcode::VSHUFF64X2Zrmbikz, + 21359 => Opcode::VSHUFF64X2Zrmi, + 21360 => Opcode::VSHUFF64X2Zrmik, + 21361 => Opcode::VSHUFF64X2Zrmikz, + 21362 => Opcode::VSHUFF64X2Zrri, + 21363 => Opcode::VSHUFF64X2Zrrik, + 21364 => Opcode::VSHUFF64X2Zrrikz, + 21365 => Opcode::VSHUFI32X4Z256rmbi, + 21366 => Opcode::VSHUFI32X4Z256rmbik, + 21367 => Opcode::VSHUFI32X4Z256rmbikz, + 21368 => Opcode::VSHUFI32X4Z256rmi, + 21369 => Opcode::VSHUFI32X4Z256rmik, + 21370 => Opcode::VSHUFI32X4Z256rmikz, + 21371 => Opcode::VSHUFI32X4Z256rri, + 21372 => Opcode::VSHUFI32X4Z256rrik, + 21373 => Opcode::VSHUFI32X4Z256rrikz, + 21374 => Opcode::VSHUFI32X4Zrmbi, + 21375 => Opcode::VSHUFI32X4Zrmbik, + 21376 => Opcode::VSHUFI32X4Zrmbikz, + 21377 => Opcode::VSHUFI32X4Zrmi, + 21378 => Opcode::VSHUFI32X4Zrmik, + 21379 => Opcode::VSHUFI32X4Zrmikz, + 21380 => Opcode::VSHUFI32X4Zrri, + 21381 => Opcode::VSHUFI32X4Zrrik, + 21382 => Opcode::VSHUFI32X4Zrrikz, + 21383 => Opcode::VSHUFI64X2Z256rmbi, + 21384 => Opcode::VSHUFI64X2Z256rmbik, + 21385 => Opcode::VSHUFI64X2Z256rmbikz, + 21386 => Opcode::VSHUFI64X2Z256rmi, + 21387 => Opcode::VSHUFI64X2Z256rmik, + 21388 => Opcode::VSHUFI64X2Z256rmikz, + 21389 => Opcode::VSHUFI64X2Z256rri, + 21390 => Opcode::VSHUFI64X2Z256rrik, + 21391 => Opcode::VSHUFI64X2Z256rrikz, + 21392 => Opcode::VSHUFI64X2Zrmbi, + 21393 => Opcode::VSHUFI64X2Zrmbik, + 21394 => Opcode::VSHUFI64X2Zrmbikz, + 21395 => Opcode::VSHUFI64X2Zrmi, + 21396 => Opcode::VSHUFI64X2Zrmik, + 21397 => Opcode::VSHUFI64X2Zrmikz, + 21398 => Opcode::VSHUFI64X2Zrri, + 21399 => Opcode::VSHUFI64X2Zrrik, + 21400 => Opcode::VSHUFI64X2Zrrikz, + 21401 => Opcode::VSHUFPDYrmi, + 21402 => Opcode::VSHUFPDYrri, + 21403 => Opcode::VSHUFPDZ128rmbi, + 21404 => Opcode::VSHUFPDZ128rmbik, + 21405 => Opcode::VSHUFPDZ128rmbikz, + 21406 => Opcode::VSHUFPDZ128rmi, + 21407 => Opcode::VSHUFPDZ128rmik, + 21408 => Opcode::VSHUFPDZ128rmikz, + 21409 => Opcode::VSHUFPDZ128rri, + 21410 => Opcode::VSHUFPDZ128rrik, + 21411 => Opcode::VSHUFPDZ128rrikz, + 21412 => Opcode::VSHUFPDZ256rmbi, + 21413 => Opcode::VSHUFPDZ256rmbik, + 21414 => Opcode::VSHUFPDZ256rmbikz, + 21415 => Opcode::VSHUFPDZ256rmi, + 21416 => Opcode::VSHUFPDZ256rmik, + 21417 => Opcode::VSHUFPDZ256rmikz, + 21418 => Opcode::VSHUFPDZ256rri, + 21419 => Opcode::VSHUFPDZ256rrik, + 21420 => Opcode::VSHUFPDZ256rrikz, + 21421 => Opcode::VSHUFPDZrmbi, + 21422 => Opcode::VSHUFPDZrmbik, + 21423 => Opcode::VSHUFPDZrmbikz, + 21424 => Opcode::VSHUFPDZrmi, + 21425 => Opcode::VSHUFPDZrmik, + 21426 => Opcode::VSHUFPDZrmikz, + 21427 => Opcode::VSHUFPDZrri, + 21428 => Opcode::VSHUFPDZrrik, + 21429 => Opcode::VSHUFPDZrrikz, + 21430 => Opcode::VSHUFPDrmi, + 21431 => Opcode::VSHUFPDrri, + 21432 => Opcode::VSHUFPSYrmi, + 21433 => Opcode::VSHUFPSYrri, + 21434 => Opcode::VSHUFPSZ128rmbi, + 21435 => Opcode::VSHUFPSZ128rmbik, + 21436 => Opcode::VSHUFPSZ128rmbikz, + 21437 => Opcode::VSHUFPSZ128rmi, + 21438 => Opcode::VSHUFPSZ128rmik, + 21439 => Opcode::VSHUFPSZ128rmikz, + 21440 => Opcode::VSHUFPSZ128rri, + 21441 => Opcode::VSHUFPSZ128rrik, + 21442 => Opcode::VSHUFPSZ128rrikz, + 21443 => Opcode::VSHUFPSZ256rmbi, + 21444 => Opcode::VSHUFPSZ256rmbik, + 21445 => Opcode::VSHUFPSZ256rmbikz, + 21446 => Opcode::VSHUFPSZ256rmi, + 21447 => Opcode::VSHUFPSZ256rmik, + 21448 => Opcode::VSHUFPSZ256rmikz, + 21449 => Opcode::VSHUFPSZ256rri, + 21450 => Opcode::VSHUFPSZ256rrik, + 21451 => Opcode::VSHUFPSZ256rrikz, + 21452 => Opcode::VSHUFPSZrmbi, + 21453 => Opcode::VSHUFPSZrmbik, + 21454 => Opcode::VSHUFPSZrmbikz, + 21455 => Opcode::VSHUFPSZrmi, + 21456 => Opcode::VSHUFPSZrmik, + 21457 => Opcode::VSHUFPSZrmikz, + 21458 => Opcode::VSHUFPSZrri, + 21459 => Opcode::VSHUFPSZrrik, + 21460 => Opcode::VSHUFPSZrrikz, + 21461 => Opcode::VSHUFPSrmi, + 21462 => Opcode::VSHUFPSrri, + 21463 => Opcode::VSM3MSG1rm, + 21464 => Opcode::VSM3MSG1rr, + 21465 => Opcode::VSM3MSG2rm, + 21466 => Opcode::VSM3MSG2rr, + 21467 => Opcode::VSM3RNDS2rmi, + 21468 => Opcode::VSM3RNDS2rri, + 21469 => Opcode::VSM4KEY4Yrm, + 21470 => Opcode::VSM4KEY4Yrr, + 21471 => Opcode::VSM4KEY4Z128rm, + 21472 => Opcode::VSM4KEY4Z128rr, + 21473 => Opcode::VSM4KEY4Z256rm, + 21474 => Opcode::VSM4KEY4Z256rr, + 21475 => Opcode::VSM4KEY4Zrm, + 21476 => Opcode::VSM4KEY4Zrr, + 21477 => Opcode::VSM4KEY4rm, + 21478 => Opcode::VSM4KEY4rr, + 21479 => Opcode::VSM4RNDS4Yrm, + 21480 => Opcode::VSM4RNDS4Yrr, + 21481 => Opcode::VSM4RNDS4Z128rm, + 21482 => Opcode::VSM4RNDS4Z128rr, + 21483 => Opcode::VSM4RNDS4Z256rm, + 21484 => Opcode::VSM4RNDS4Z256rr, + 21485 => Opcode::VSM4RNDS4Zrm, + 21486 => Opcode::VSM4RNDS4Zrr, + 21487 => Opcode::VSM4RNDS4rm, + 21488 => Opcode::VSM4RNDS4rr, + 21489 => Opcode::VSQRTBF16Z128m, + 21490 => Opcode::VSQRTBF16Z128mb, + 21491 => Opcode::VSQRTBF16Z128mbk, + 21492 => Opcode::VSQRTBF16Z128mbkz, + 21493 => Opcode::VSQRTBF16Z128mk, + 21494 => Opcode::VSQRTBF16Z128mkz, + 21495 => Opcode::VSQRTBF16Z128r, + 21496 => Opcode::VSQRTBF16Z128rk, + 21497 => Opcode::VSQRTBF16Z128rkz, + 21498 => Opcode::VSQRTBF16Z256m, + 21499 => Opcode::VSQRTBF16Z256mb, + 21500 => Opcode::VSQRTBF16Z256mbk, + 21501 => Opcode::VSQRTBF16Z256mbkz, + 21502 => Opcode::VSQRTBF16Z256mk, + 21503 => Opcode::VSQRTBF16Z256mkz, + 21504 => Opcode::VSQRTBF16Z256r, + 21505 => Opcode::VSQRTBF16Z256rk, + 21506 => Opcode::VSQRTBF16Z256rkz, + 21507 => Opcode::VSQRTBF16Zm, + 21508 => Opcode::VSQRTBF16Zmb, + 21509 => Opcode::VSQRTBF16Zmbk, + 21510 => Opcode::VSQRTBF16Zmbkz, + 21511 => Opcode::VSQRTBF16Zmk, + 21512 => Opcode::VSQRTBF16Zmkz, + 21513 => Opcode::VSQRTBF16Zr, + 21514 => Opcode::VSQRTBF16Zrk, + 21515 => Opcode::VSQRTBF16Zrkz, + 21516 => Opcode::VSQRTPDYm, + 21517 => Opcode::VSQRTPDYr, + 21518 => Opcode::VSQRTPDZ128m, + 21519 => Opcode::VSQRTPDZ128mb, + 21520 => Opcode::VSQRTPDZ128mbk, + 21521 => Opcode::VSQRTPDZ128mbkz, + 21522 => Opcode::VSQRTPDZ128mk, + 21523 => Opcode::VSQRTPDZ128mkz, + 21524 => Opcode::VSQRTPDZ128r, + 21525 => Opcode::VSQRTPDZ128rk, + 21526 => Opcode::VSQRTPDZ128rkz, + 21527 => Opcode::VSQRTPDZ256m, + 21528 => Opcode::VSQRTPDZ256mb, + 21529 => Opcode::VSQRTPDZ256mbk, + 21530 => Opcode::VSQRTPDZ256mbkz, + 21531 => Opcode::VSQRTPDZ256mk, + 21532 => Opcode::VSQRTPDZ256mkz, + 21533 => Opcode::VSQRTPDZ256r, + 21534 => Opcode::VSQRTPDZ256rk, + 21535 => Opcode::VSQRTPDZ256rkz, + 21536 => Opcode::VSQRTPDZm, + 21537 => Opcode::VSQRTPDZmb, + 21538 => Opcode::VSQRTPDZmbk, + 21539 => Opcode::VSQRTPDZmbkz, + 21540 => Opcode::VSQRTPDZmk, + 21541 => Opcode::VSQRTPDZmkz, + 21542 => Opcode::VSQRTPDZr, + 21543 => Opcode::VSQRTPDZrb, + 21544 => Opcode::VSQRTPDZrbk, + 21545 => Opcode::VSQRTPDZrbkz, + 21546 => Opcode::VSQRTPDZrk, + 21547 => Opcode::VSQRTPDZrkz, + 21548 => Opcode::VSQRTPDm, + 21549 => Opcode::VSQRTPDr, + 21550 => Opcode::VSQRTPHZ128m, + 21551 => Opcode::VSQRTPHZ128mb, + 21552 => Opcode::VSQRTPHZ128mbk, + 21553 => Opcode::VSQRTPHZ128mbkz, + 21554 => Opcode::VSQRTPHZ128mk, + 21555 => Opcode::VSQRTPHZ128mkz, + 21556 => Opcode::VSQRTPHZ128r, + 21557 => Opcode::VSQRTPHZ128rk, + 21558 => Opcode::VSQRTPHZ128rkz, + 21559 => Opcode::VSQRTPHZ256m, + 21560 => Opcode::VSQRTPHZ256mb, + 21561 => Opcode::VSQRTPHZ256mbk, + 21562 => Opcode::VSQRTPHZ256mbkz, + 21563 => Opcode::VSQRTPHZ256mk, + 21564 => Opcode::VSQRTPHZ256mkz, + 21565 => Opcode::VSQRTPHZ256r, + 21566 => Opcode::VSQRTPHZ256rk, + 21567 => Opcode::VSQRTPHZ256rkz, + 21568 => Opcode::VSQRTPHZm, + 21569 => Opcode::VSQRTPHZmb, + 21570 => Opcode::VSQRTPHZmbk, + 21571 => Opcode::VSQRTPHZmbkz, + 21572 => Opcode::VSQRTPHZmk, + 21573 => Opcode::VSQRTPHZmkz, + 21574 => Opcode::VSQRTPHZr, + 21575 => Opcode::VSQRTPHZrb, + 21576 => Opcode::VSQRTPHZrbk, + 21577 => Opcode::VSQRTPHZrbkz, + 21578 => Opcode::VSQRTPHZrk, + 21579 => Opcode::VSQRTPHZrkz, + 21580 => Opcode::VSQRTPSYm, + 21581 => Opcode::VSQRTPSYr, + 21582 => Opcode::VSQRTPSZ128m, + 21583 => Opcode::VSQRTPSZ128mb, + 21584 => Opcode::VSQRTPSZ128mbk, + 21585 => Opcode::VSQRTPSZ128mbkz, + 21586 => Opcode::VSQRTPSZ128mk, + 21587 => Opcode::VSQRTPSZ128mkz, + 21588 => Opcode::VSQRTPSZ128r, + 21589 => Opcode::VSQRTPSZ128rk, + 21590 => Opcode::VSQRTPSZ128rkz, + 21591 => Opcode::VSQRTPSZ256m, + 21592 => Opcode::VSQRTPSZ256mb, + 21593 => Opcode::VSQRTPSZ256mbk, + 21594 => Opcode::VSQRTPSZ256mbkz, + 21595 => Opcode::VSQRTPSZ256mk, + 21596 => Opcode::VSQRTPSZ256mkz, + 21597 => Opcode::VSQRTPSZ256r, + 21598 => Opcode::VSQRTPSZ256rk, + 21599 => Opcode::VSQRTPSZ256rkz, + 21600 => Opcode::VSQRTPSZm, + 21601 => Opcode::VSQRTPSZmb, + 21602 => Opcode::VSQRTPSZmbk, + 21603 => Opcode::VSQRTPSZmbkz, + 21604 => Opcode::VSQRTPSZmk, + 21605 => Opcode::VSQRTPSZmkz, + 21606 => Opcode::VSQRTPSZr, + 21607 => Opcode::VSQRTPSZrb, + 21608 => Opcode::VSQRTPSZrbk, + 21609 => Opcode::VSQRTPSZrbkz, + 21610 => Opcode::VSQRTPSZrk, + 21611 => Opcode::VSQRTPSZrkz, + 21612 => Opcode::VSQRTPSm, + 21613 => Opcode::VSQRTPSr, + 21614 => Opcode::VSQRTSDZm, + 21615 => Opcode::VSQRTSDZm_Int, + 21616 => Opcode::VSQRTSDZmk_Int, + 21617 => Opcode::VSQRTSDZmkz_Int, + 21618 => Opcode::VSQRTSDZr, + 21619 => Opcode::VSQRTSDZr_Int, + 21620 => Opcode::VSQRTSDZrb_Int, + 21621 => Opcode::VSQRTSDZrbk_Int, + 21622 => Opcode::VSQRTSDZrbkz_Int, + 21623 => Opcode::VSQRTSDZrk_Int, + 21624 => Opcode::VSQRTSDZrkz_Int, + 21625 => Opcode::VSQRTSDm, + 21626 => Opcode::VSQRTSDm_Int, + 21627 => Opcode::VSQRTSDr, + 21628 => Opcode::VSQRTSDr_Int, + 21629 => Opcode::VSQRTSHZm, + 21630 => Opcode::VSQRTSHZm_Int, + 21631 => Opcode::VSQRTSHZmk_Int, + 21632 => Opcode::VSQRTSHZmkz_Int, + 21633 => Opcode::VSQRTSHZr, + 21634 => Opcode::VSQRTSHZr_Int, + 21635 => Opcode::VSQRTSHZrb_Int, + 21636 => Opcode::VSQRTSHZrbk_Int, + 21637 => Opcode::VSQRTSHZrbkz_Int, + 21638 => Opcode::VSQRTSHZrk_Int, + 21639 => Opcode::VSQRTSHZrkz_Int, + 21640 => Opcode::VSQRTSSZm, + 21641 => Opcode::VSQRTSSZm_Int, + 21642 => Opcode::VSQRTSSZmk_Int, + 21643 => Opcode::VSQRTSSZmkz_Int, + 21644 => Opcode::VSQRTSSZr, + 21645 => Opcode::VSQRTSSZr_Int, + 21646 => Opcode::VSQRTSSZrb_Int, + 21647 => Opcode::VSQRTSSZrbk_Int, + 21648 => Opcode::VSQRTSSZrbkz_Int, + 21649 => Opcode::VSQRTSSZrk_Int, + 21650 => Opcode::VSQRTSSZrkz_Int, + 21651 => Opcode::VSQRTSSm, + 21652 => Opcode::VSQRTSSm_Int, + 21653 => Opcode::VSQRTSSr, + 21654 => Opcode::VSQRTSSr_Int, + 21655 => Opcode::VSTMXCSR, + 21656 => Opcode::VSUBBF16Z128rm, + 21657 => Opcode::VSUBBF16Z128rmb, + 21658 => Opcode::VSUBBF16Z128rmbk, + 21659 => Opcode::VSUBBF16Z128rmbkz, + 21660 => Opcode::VSUBBF16Z128rmk, + 21661 => Opcode::VSUBBF16Z128rmkz, + 21662 => Opcode::VSUBBF16Z128rr, + 21663 => Opcode::VSUBBF16Z128rrk, + 21664 => Opcode::VSUBBF16Z128rrkz, + 21665 => Opcode::VSUBBF16Z256rm, + 21666 => Opcode::VSUBBF16Z256rmb, + 21667 => Opcode::VSUBBF16Z256rmbk, + 21668 => Opcode::VSUBBF16Z256rmbkz, + 21669 => Opcode::VSUBBF16Z256rmk, + 21670 => Opcode::VSUBBF16Z256rmkz, + 21671 => Opcode::VSUBBF16Z256rr, + 21672 => Opcode::VSUBBF16Z256rrk, + 21673 => Opcode::VSUBBF16Z256rrkz, + 21674 => Opcode::VSUBBF16Zrm, + 21675 => Opcode::VSUBBF16Zrmb, + 21676 => Opcode::VSUBBF16Zrmbk, + 21677 => Opcode::VSUBBF16Zrmbkz, + 21678 => Opcode::VSUBBF16Zrmk, + 21679 => Opcode::VSUBBF16Zrmkz, + 21680 => Opcode::VSUBBF16Zrr, + 21681 => Opcode::VSUBBF16Zrrk, + 21682 => Opcode::VSUBBF16Zrrkz, + 21683 => Opcode::VSUBPDYrm, + 21684 => Opcode::VSUBPDYrr, + 21685 => Opcode::VSUBPDZ128rm, + 21686 => Opcode::VSUBPDZ128rmb, + 21687 => Opcode::VSUBPDZ128rmbk, + 21688 => Opcode::VSUBPDZ128rmbkz, + 21689 => Opcode::VSUBPDZ128rmk, + 21690 => Opcode::VSUBPDZ128rmkz, + 21691 => Opcode::VSUBPDZ128rr, + 21692 => Opcode::VSUBPDZ128rrk, + 21693 => Opcode::VSUBPDZ128rrkz, + 21694 => Opcode::VSUBPDZ256rm, + 21695 => Opcode::VSUBPDZ256rmb, + 21696 => Opcode::VSUBPDZ256rmbk, + 21697 => Opcode::VSUBPDZ256rmbkz, + 21698 => Opcode::VSUBPDZ256rmk, + 21699 => Opcode::VSUBPDZ256rmkz, + 21700 => Opcode::VSUBPDZ256rr, + 21701 => Opcode::VSUBPDZ256rrk, + 21702 => Opcode::VSUBPDZ256rrkz, + 21703 => Opcode::VSUBPDZrm, + 21704 => Opcode::VSUBPDZrmb, + 21705 => Opcode::VSUBPDZrmbk, + 21706 => Opcode::VSUBPDZrmbkz, + 21707 => Opcode::VSUBPDZrmk, + 21708 => Opcode::VSUBPDZrmkz, + 21709 => Opcode::VSUBPDZrr, + 21710 => Opcode::VSUBPDZrrb, + 21711 => Opcode::VSUBPDZrrbk, + 21712 => Opcode::VSUBPDZrrbkz, + 21713 => Opcode::VSUBPDZrrk, + 21714 => Opcode::VSUBPDZrrkz, + 21715 => Opcode::VSUBPDrm, + 21716 => Opcode::VSUBPDrr, + 21717 => Opcode::VSUBPHZ128rm, + 21718 => Opcode::VSUBPHZ128rmb, + 21719 => Opcode::VSUBPHZ128rmbk, + 21720 => Opcode::VSUBPHZ128rmbkz, + 21721 => Opcode::VSUBPHZ128rmk, + 21722 => Opcode::VSUBPHZ128rmkz, + 21723 => Opcode::VSUBPHZ128rr, + 21724 => Opcode::VSUBPHZ128rrk, + 21725 => Opcode::VSUBPHZ128rrkz, + 21726 => Opcode::VSUBPHZ256rm, + 21727 => Opcode::VSUBPHZ256rmb, + 21728 => Opcode::VSUBPHZ256rmbk, + 21729 => Opcode::VSUBPHZ256rmbkz, + 21730 => Opcode::VSUBPHZ256rmk, + 21731 => Opcode::VSUBPHZ256rmkz, + 21732 => Opcode::VSUBPHZ256rr, + 21733 => Opcode::VSUBPHZ256rrk, + 21734 => Opcode::VSUBPHZ256rrkz, + 21735 => Opcode::VSUBPHZrm, + 21736 => Opcode::VSUBPHZrmb, + 21737 => Opcode::VSUBPHZrmbk, + 21738 => Opcode::VSUBPHZrmbkz, + 21739 => Opcode::VSUBPHZrmk, + 21740 => Opcode::VSUBPHZrmkz, + 21741 => Opcode::VSUBPHZrr, + 21742 => Opcode::VSUBPHZrrb, + 21743 => Opcode::VSUBPHZrrbk, + 21744 => Opcode::VSUBPHZrrbkz, + 21745 => Opcode::VSUBPHZrrk, + 21746 => Opcode::VSUBPHZrrkz, + 21747 => Opcode::VSUBPSYrm, + 21748 => Opcode::VSUBPSYrr, + 21749 => Opcode::VSUBPSZ128rm, + 21750 => Opcode::VSUBPSZ128rmb, + 21751 => Opcode::VSUBPSZ128rmbk, + 21752 => Opcode::VSUBPSZ128rmbkz, + 21753 => Opcode::VSUBPSZ128rmk, + 21754 => Opcode::VSUBPSZ128rmkz, + 21755 => Opcode::VSUBPSZ128rr, + 21756 => Opcode::VSUBPSZ128rrk, + 21757 => Opcode::VSUBPSZ128rrkz, + 21758 => Opcode::VSUBPSZ256rm, + 21759 => Opcode::VSUBPSZ256rmb, + 21760 => Opcode::VSUBPSZ256rmbk, + 21761 => Opcode::VSUBPSZ256rmbkz, + 21762 => Opcode::VSUBPSZ256rmk, + 21763 => Opcode::VSUBPSZ256rmkz, + 21764 => Opcode::VSUBPSZ256rr, + 21765 => Opcode::VSUBPSZ256rrk, + 21766 => Opcode::VSUBPSZ256rrkz, + 21767 => Opcode::VSUBPSZrm, + 21768 => Opcode::VSUBPSZrmb, + 21769 => Opcode::VSUBPSZrmbk, + 21770 => Opcode::VSUBPSZrmbkz, + 21771 => Opcode::VSUBPSZrmk, + 21772 => Opcode::VSUBPSZrmkz, + 21773 => Opcode::VSUBPSZrr, + 21774 => Opcode::VSUBPSZrrb, + 21775 => Opcode::VSUBPSZrrbk, + 21776 => Opcode::VSUBPSZrrbkz, + 21777 => Opcode::VSUBPSZrrk, + 21778 => Opcode::VSUBPSZrrkz, + 21779 => Opcode::VSUBPSrm, + 21780 => Opcode::VSUBPSrr, + 21781 => Opcode::VSUBSDZrm, + 21782 => Opcode::VSUBSDZrm_Int, + 21783 => Opcode::VSUBSDZrmk_Int, + 21784 => Opcode::VSUBSDZrmkz_Int, + 21785 => Opcode::VSUBSDZrr, + 21786 => Opcode::VSUBSDZrr_Int, + 21787 => Opcode::VSUBSDZrrb_Int, + 21788 => Opcode::VSUBSDZrrbk_Int, + 21789 => Opcode::VSUBSDZrrbkz_Int, + 21790 => Opcode::VSUBSDZrrk_Int, + 21791 => Opcode::VSUBSDZrrkz_Int, + 21792 => Opcode::VSUBSDrm, + 21793 => Opcode::VSUBSDrm_Int, + 21794 => Opcode::VSUBSDrr, + 21795 => Opcode::VSUBSDrr_Int, + 21796 => Opcode::VSUBSHZrm, + 21797 => Opcode::VSUBSHZrm_Int, + 21798 => Opcode::VSUBSHZrmk_Int, + 21799 => Opcode::VSUBSHZrmkz_Int, + 21800 => Opcode::VSUBSHZrr, + 21801 => Opcode::VSUBSHZrr_Int, + 21802 => Opcode::VSUBSHZrrb_Int, + 21803 => Opcode::VSUBSHZrrbk_Int, + 21804 => Opcode::VSUBSHZrrbkz_Int, + 21805 => Opcode::VSUBSHZrrk_Int, + 21806 => Opcode::VSUBSHZrrkz_Int, + 21807 => Opcode::VSUBSSZrm, + 21808 => Opcode::VSUBSSZrm_Int, + 21809 => Opcode::VSUBSSZrmk_Int, + 21810 => Opcode::VSUBSSZrmkz_Int, + 21811 => Opcode::VSUBSSZrr, + 21812 => Opcode::VSUBSSZrr_Int, + 21813 => Opcode::VSUBSSZrrb_Int, + 21814 => Opcode::VSUBSSZrrbk_Int, + 21815 => Opcode::VSUBSSZrrbkz_Int, + 21816 => Opcode::VSUBSSZrrk_Int, + 21817 => Opcode::VSUBSSZrrkz_Int, + 21818 => Opcode::VSUBSSrm, + 21819 => Opcode::VSUBSSrm_Int, + 21820 => Opcode::VSUBSSrr, + 21821 => Opcode::VSUBSSrr_Int, + 21822 => Opcode::VTESTPDYrm, + 21823 => Opcode::VTESTPDYrr, + 21824 => Opcode::VTESTPDrm, + 21825 => Opcode::VTESTPDrr, + 21826 => Opcode::VTESTPSYrm, + 21827 => Opcode::VTESTPSYrr, + 21828 => Opcode::VTESTPSrm, + 21829 => Opcode::VTESTPSrr, + 21830 => Opcode::VUCOMISDZrm, + 21831 => Opcode::VUCOMISDZrm_Int, + 21832 => Opcode::VUCOMISDZrr, + 21833 => Opcode::VUCOMISDZrr_Int, + 21834 => Opcode::VUCOMISDZrrb, + 21835 => Opcode::VUCOMISDrm, + 21836 => Opcode::VUCOMISDrm_Int, + 21837 => Opcode::VUCOMISDrr, + 21838 => Opcode::VUCOMISDrr_Int, + 21839 => Opcode::VUCOMISHZrm, + 21840 => Opcode::VUCOMISHZrm_Int, + 21841 => Opcode::VUCOMISHZrr, + 21842 => Opcode::VUCOMISHZrr_Int, + 21843 => Opcode::VUCOMISHZrrb, + 21844 => Opcode::VUCOMISSZrm, + 21845 => Opcode::VUCOMISSZrm_Int, + 21846 => Opcode::VUCOMISSZrr, + 21847 => Opcode::VUCOMISSZrr_Int, + 21848 => Opcode::VUCOMISSZrrb, + 21849 => Opcode::VUCOMISSrm, + 21850 => Opcode::VUCOMISSrm_Int, + 21851 => Opcode::VUCOMISSrr, + 21852 => Opcode::VUCOMISSrr_Int, + 21853 => Opcode::VUCOMXSDZrm, + 21854 => Opcode::VUCOMXSDZrm_Int, + 21855 => Opcode::VUCOMXSDZrr, + 21856 => Opcode::VUCOMXSDZrr_Int, + 21857 => Opcode::VUCOMXSDZrrb_Int, + 21858 => Opcode::VUCOMXSHZrm, + 21859 => Opcode::VUCOMXSHZrm_Int, + 21860 => Opcode::VUCOMXSHZrr, + 21861 => Opcode::VUCOMXSHZrr_Int, + 21862 => Opcode::VUCOMXSHZrrb_Int, + 21863 => Opcode::VUCOMXSSZrm, + 21864 => Opcode::VUCOMXSSZrm_Int, + 21865 => Opcode::VUCOMXSSZrr, + 21866 => Opcode::VUCOMXSSZrr_Int, + 21867 => Opcode::VUCOMXSSZrrb_Int, + 21868 => Opcode::VUNPCKHPDYrm, + 21869 => Opcode::VUNPCKHPDYrr, + 21870 => Opcode::VUNPCKHPDZ128rm, + 21871 => Opcode::VUNPCKHPDZ128rmb, + 21872 => Opcode::VUNPCKHPDZ128rmbk, + 21873 => Opcode::VUNPCKHPDZ128rmbkz, + 21874 => Opcode::VUNPCKHPDZ128rmk, + 21875 => Opcode::VUNPCKHPDZ128rmkz, + 21876 => Opcode::VUNPCKHPDZ128rr, + 21877 => Opcode::VUNPCKHPDZ128rrk, + 21878 => Opcode::VUNPCKHPDZ128rrkz, + 21879 => Opcode::VUNPCKHPDZ256rm, + 21880 => Opcode::VUNPCKHPDZ256rmb, + 21881 => Opcode::VUNPCKHPDZ256rmbk, + 21882 => Opcode::VUNPCKHPDZ256rmbkz, + 21883 => Opcode::VUNPCKHPDZ256rmk, + 21884 => Opcode::VUNPCKHPDZ256rmkz, + 21885 => Opcode::VUNPCKHPDZ256rr, + 21886 => Opcode::VUNPCKHPDZ256rrk, + 21887 => Opcode::VUNPCKHPDZ256rrkz, + 21888 => Opcode::VUNPCKHPDZrm, + 21889 => Opcode::VUNPCKHPDZrmb, + 21890 => Opcode::VUNPCKHPDZrmbk, + 21891 => Opcode::VUNPCKHPDZrmbkz, + 21892 => Opcode::VUNPCKHPDZrmk, + 21893 => Opcode::VUNPCKHPDZrmkz, + 21894 => Opcode::VUNPCKHPDZrr, + 21895 => Opcode::VUNPCKHPDZrrk, + 21896 => Opcode::VUNPCKHPDZrrkz, + 21897 => Opcode::VUNPCKHPDrm, + 21898 => Opcode::VUNPCKHPDrr, + 21899 => Opcode::VUNPCKHPSYrm, + 21900 => Opcode::VUNPCKHPSYrr, + 21901 => Opcode::VUNPCKHPSZ128rm, + 21902 => Opcode::VUNPCKHPSZ128rmb, + 21903 => Opcode::VUNPCKHPSZ128rmbk, + 21904 => Opcode::VUNPCKHPSZ128rmbkz, + 21905 => Opcode::VUNPCKHPSZ128rmk, + 21906 => Opcode::VUNPCKHPSZ128rmkz, + 21907 => Opcode::VUNPCKHPSZ128rr, + 21908 => Opcode::VUNPCKHPSZ128rrk, + 21909 => Opcode::VUNPCKHPSZ128rrkz, + 21910 => Opcode::VUNPCKHPSZ256rm, + 21911 => Opcode::VUNPCKHPSZ256rmb, + 21912 => Opcode::VUNPCKHPSZ256rmbk, + 21913 => Opcode::VUNPCKHPSZ256rmbkz, + 21914 => Opcode::VUNPCKHPSZ256rmk, + 21915 => Opcode::VUNPCKHPSZ256rmkz, + 21916 => Opcode::VUNPCKHPSZ256rr, + 21917 => Opcode::VUNPCKHPSZ256rrk, + 21918 => Opcode::VUNPCKHPSZ256rrkz, + 21919 => Opcode::VUNPCKHPSZrm, + 21920 => Opcode::VUNPCKHPSZrmb, + 21921 => Opcode::VUNPCKHPSZrmbk, + 21922 => Opcode::VUNPCKHPSZrmbkz, + 21923 => Opcode::VUNPCKHPSZrmk, + 21924 => Opcode::VUNPCKHPSZrmkz, + 21925 => Opcode::VUNPCKHPSZrr, + 21926 => Opcode::VUNPCKHPSZrrk, + 21927 => Opcode::VUNPCKHPSZrrkz, + 21928 => Opcode::VUNPCKHPSrm, + 21929 => Opcode::VUNPCKHPSrr, + 21930 => Opcode::VUNPCKLPDYrm, + 21931 => Opcode::VUNPCKLPDYrr, + 21932 => Opcode::VUNPCKLPDZ128rm, + 21933 => Opcode::VUNPCKLPDZ128rmb, + 21934 => Opcode::VUNPCKLPDZ128rmbk, + 21935 => Opcode::VUNPCKLPDZ128rmbkz, + 21936 => Opcode::VUNPCKLPDZ128rmk, + 21937 => Opcode::VUNPCKLPDZ128rmkz, + 21938 => Opcode::VUNPCKLPDZ128rr, + 21939 => Opcode::VUNPCKLPDZ128rrk, + 21940 => Opcode::VUNPCKLPDZ128rrkz, + 21941 => Opcode::VUNPCKLPDZ256rm, + 21942 => Opcode::VUNPCKLPDZ256rmb, + 21943 => Opcode::VUNPCKLPDZ256rmbk, + 21944 => Opcode::VUNPCKLPDZ256rmbkz, + 21945 => Opcode::VUNPCKLPDZ256rmk, + 21946 => Opcode::VUNPCKLPDZ256rmkz, + 21947 => Opcode::VUNPCKLPDZ256rr, + 21948 => Opcode::VUNPCKLPDZ256rrk, + 21949 => Opcode::VUNPCKLPDZ256rrkz, + 21950 => Opcode::VUNPCKLPDZrm, + 21951 => Opcode::VUNPCKLPDZrmb, + 21952 => Opcode::VUNPCKLPDZrmbk, + 21953 => Opcode::VUNPCKLPDZrmbkz, + 21954 => Opcode::VUNPCKLPDZrmk, + 21955 => Opcode::VUNPCKLPDZrmkz, + 21956 => Opcode::VUNPCKLPDZrr, + 21957 => Opcode::VUNPCKLPDZrrk, + 21958 => Opcode::VUNPCKLPDZrrkz, + 21959 => Opcode::VUNPCKLPDrm, + 21960 => Opcode::VUNPCKLPDrr, + 21961 => Opcode::VUNPCKLPSYrm, + 21962 => Opcode::VUNPCKLPSYrr, + 21963 => Opcode::VUNPCKLPSZ128rm, + 21964 => Opcode::VUNPCKLPSZ128rmb, + 21965 => Opcode::VUNPCKLPSZ128rmbk, + 21966 => Opcode::VUNPCKLPSZ128rmbkz, + 21967 => Opcode::VUNPCKLPSZ128rmk, + 21968 => Opcode::VUNPCKLPSZ128rmkz, + 21969 => Opcode::VUNPCKLPSZ128rr, + 21970 => Opcode::VUNPCKLPSZ128rrk, + 21971 => Opcode::VUNPCKLPSZ128rrkz, + 21972 => Opcode::VUNPCKLPSZ256rm, + 21973 => Opcode::VUNPCKLPSZ256rmb, + 21974 => Opcode::VUNPCKLPSZ256rmbk, + 21975 => Opcode::VUNPCKLPSZ256rmbkz, + 21976 => Opcode::VUNPCKLPSZ256rmk, + 21977 => Opcode::VUNPCKLPSZ256rmkz, + 21978 => Opcode::VUNPCKLPSZ256rr, + 21979 => Opcode::VUNPCKLPSZ256rrk, + 21980 => Opcode::VUNPCKLPSZ256rrkz, + 21981 => Opcode::VUNPCKLPSZrm, + 21982 => Opcode::VUNPCKLPSZrmb, + 21983 => Opcode::VUNPCKLPSZrmbk, + 21984 => Opcode::VUNPCKLPSZrmbkz, + 21985 => Opcode::VUNPCKLPSZrmk, + 21986 => Opcode::VUNPCKLPSZrmkz, + 21987 => Opcode::VUNPCKLPSZrr, + 21988 => Opcode::VUNPCKLPSZrrk, + 21989 => Opcode::VUNPCKLPSZrrkz, + 21990 => Opcode::VUNPCKLPSrm, + 21991 => Opcode::VUNPCKLPSrr, + 21992 => Opcode::VXORPDYrm, + 21993 => Opcode::VXORPDYrr, + 21994 => Opcode::VXORPDZ128rm, + 21995 => Opcode::VXORPDZ128rmb, + 21996 => Opcode::VXORPDZ128rmbk, + 21997 => Opcode::VXORPDZ128rmbkz, + 21998 => Opcode::VXORPDZ128rmk, + 21999 => Opcode::VXORPDZ128rmkz, + 22000 => Opcode::VXORPDZ128rr, + 22001 => Opcode::VXORPDZ128rrk, + 22002 => Opcode::VXORPDZ128rrkz, + 22003 => Opcode::VXORPDZ256rm, + 22004 => Opcode::VXORPDZ256rmb, + 22005 => Opcode::VXORPDZ256rmbk, + 22006 => Opcode::VXORPDZ256rmbkz, + 22007 => Opcode::VXORPDZ256rmk, + 22008 => Opcode::VXORPDZ256rmkz, + 22009 => Opcode::VXORPDZ256rr, + 22010 => Opcode::VXORPDZ256rrk, + 22011 => Opcode::VXORPDZ256rrkz, + 22012 => Opcode::VXORPDZrm, + 22013 => Opcode::VXORPDZrmb, + 22014 => Opcode::VXORPDZrmbk, + 22015 => Opcode::VXORPDZrmbkz, + 22016 => Opcode::VXORPDZrmk, + 22017 => Opcode::VXORPDZrmkz, + 22018 => Opcode::VXORPDZrr, + 22019 => Opcode::VXORPDZrrk, + 22020 => Opcode::VXORPDZrrkz, + 22021 => Opcode::VXORPDrm, + 22022 => Opcode::VXORPDrr, + 22023 => Opcode::VXORPSYrm, + 22024 => Opcode::VXORPSYrr, + 22025 => Opcode::VXORPSZ128rm, + 22026 => Opcode::VXORPSZ128rmb, + 22027 => Opcode::VXORPSZ128rmbk, + 22028 => Opcode::VXORPSZ128rmbkz, + 22029 => Opcode::VXORPSZ128rmk, + 22030 => Opcode::VXORPSZ128rmkz, + 22031 => Opcode::VXORPSZ128rr, + 22032 => Opcode::VXORPSZ128rrk, + 22033 => Opcode::VXORPSZ128rrkz, + 22034 => Opcode::VXORPSZ256rm, + 22035 => Opcode::VXORPSZ256rmb, + 22036 => Opcode::VXORPSZ256rmbk, + 22037 => Opcode::VXORPSZ256rmbkz, + 22038 => Opcode::VXORPSZ256rmk, + 22039 => Opcode::VXORPSZ256rmkz, + 22040 => Opcode::VXORPSZ256rr, + 22041 => Opcode::VXORPSZ256rrk, + 22042 => Opcode::VXORPSZ256rrkz, + 22043 => Opcode::VXORPSZrm, + 22044 => Opcode::VXORPSZrmb, + 22045 => Opcode::VXORPSZrmbk, + 22046 => Opcode::VXORPSZrmbkz, + 22047 => Opcode::VXORPSZrmk, + 22048 => Opcode::VXORPSZrmkz, + 22049 => Opcode::VXORPSZrr, + 22050 => Opcode::VXORPSZrrk, + 22051 => Opcode::VXORPSZrrkz, + 22052 => Opcode::VXORPSrm, + 22053 => Opcode::VXORPSrr, + 22054 => Opcode::VZEROALL, + 22055 => Opcode::VZEROUPPER, + 22056 => Opcode::WAIT, + 22057 => Opcode::WBINVD, + 22058 => Opcode::WBNOINVD, + 22059 => Opcode::WRFSBASE, + 22060 => Opcode::WRFSBASE64, + 22061 => Opcode::WRGSBASE, + 22062 => Opcode::WRGSBASE64, + 22063 => Opcode::WRMSR, + 22064 => Opcode::WRMSRLIST, + 22065 => Opcode::WRMSRNS, + 22066 => Opcode::WRMSRNSir, + 22067 => Opcode::WRMSRNSir_EVEX, + 22068 => Opcode::WRPKRUr, + 22069 => Opcode::WRSSD, + 22070 => Opcode::WRSSD_EVEX, + 22071 => Opcode::WRSSQ, + 22072 => Opcode::WRSSQ_EVEX, + 22073 => Opcode::WRUSSD, + 22074 => Opcode::WRUSSD_EVEX, + 22075 => Opcode::WRUSSQ, + 22076 => Opcode::WRUSSQ_EVEX, + 22077 => Opcode::XABORT, + 22078 => Opcode::XACQUIRE_PREFIX, + 22079 => Opcode::XADD16rm, + 22080 => Opcode::XADD16rr, + 22081 => Opcode::XADD32rm, + 22082 => Opcode::XADD32rr, + 22083 => Opcode::XADD64rm, + 22084 => Opcode::XADD64rr, + 22085 => Opcode::XADD8rm, + 22086 => Opcode::XADD8rr, + 22087 => Opcode::XAM_F, + 22088 => Opcode::XAM_Fp32, + 22089 => Opcode::XAM_Fp64, + 22090 => Opcode::XAM_Fp80, + 22091 => Opcode::XBEGIN, + 22092 => Opcode::XBEGIN_2, + 22093 => Opcode::XBEGIN_4, + 22094 => Opcode::XCHG16ar, + 22095 => Opcode::XCHG16rm, + 22096 => Opcode::XCHG16rr, + 22097 => Opcode::XCHG32ar, + 22098 => Opcode::XCHG32rm, + 22099 => Opcode::XCHG32rr, + 22100 => Opcode::XCHG64ar, + 22101 => Opcode::XCHG64rm, + 22102 => Opcode::XCHG64rr, + 22103 => Opcode::XCHG8rm, + 22104 => Opcode::XCHG8rr, + 22105 => Opcode::XCH_F, + 22106 => Opcode::XCRYPTCBC, + 22107 => Opcode::XCRYPTCFB, + 22108 => Opcode::XCRYPTCTR, + 22109 => Opcode::XCRYPTECB, + 22110 => Opcode::XCRYPTOFB, + 22111 => Opcode::XEND, + 22112 => Opcode::XGETBV, + 22113 => Opcode::XLAT, + 22114 => Opcode::XOR16i16, + 22115 => Opcode::XOR16mi, + 22116 => Opcode::XOR16mi8, + 22117 => Opcode::XOR16mi8_EVEX, + 22118 => Opcode::XOR16mi8_ND, + 22119 => Opcode::XOR16mi8_NF, + 22120 => Opcode::XOR16mi8_NF_ND, + 22121 => Opcode::XOR16mi_EVEX, + 22122 => Opcode::XOR16mi_ND, + 22123 => Opcode::XOR16mi_NF, + 22124 => Opcode::XOR16mi_NF_ND, + 22125 => Opcode::XOR16mr, + 22126 => Opcode::XOR16mr_EVEX, + 22127 => Opcode::XOR16mr_ND, + 22128 => Opcode::XOR16mr_NF, + 22129 => Opcode::XOR16mr_NF_ND, + 22130 => Opcode::XOR16ri, + 22131 => Opcode::XOR16ri8, + 22132 => Opcode::XOR16ri8_EVEX, + 22133 => Opcode::XOR16ri8_ND, + 22134 => Opcode::XOR16ri8_NF, + 22135 => Opcode::XOR16ri8_NF_ND, + 22136 => Opcode::XOR16ri_EVEX, + 22137 => Opcode::XOR16ri_ND, + 22138 => Opcode::XOR16ri_NF, + 22139 => Opcode::XOR16ri_NF_ND, + 22140 => Opcode::XOR16rm, + 22141 => Opcode::XOR16rm_EVEX, + 22142 => Opcode::XOR16rm_ND, + 22143 => Opcode::XOR16rm_NF, + 22144 => Opcode::XOR16rm_NF_ND, + 22145 => Opcode::XOR16rr, + 22146 => Opcode::XOR16rr_EVEX, + 22147 => Opcode::XOR16rr_EVEX_REV, + 22148 => Opcode::XOR16rr_ND, + 22149 => Opcode::XOR16rr_ND_REV, + 22150 => Opcode::XOR16rr_NF, + 22151 => Opcode::XOR16rr_NF_ND, + 22152 => Opcode::XOR16rr_NF_ND_REV, + 22153 => Opcode::XOR16rr_NF_REV, + 22154 => Opcode::XOR16rr_REV, + 22155 => Opcode::XOR32i32, + 22156 => Opcode::XOR32mi, + 22157 => Opcode::XOR32mi8, + 22158 => Opcode::XOR32mi8_EVEX, + 22159 => Opcode::XOR32mi8_ND, + 22160 => Opcode::XOR32mi8_NF, + 22161 => Opcode::XOR32mi8_NF_ND, + 22162 => Opcode::XOR32mi_EVEX, + 22163 => Opcode::XOR32mi_ND, + 22164 => Opcode::XOR32mi_NF, + 22165 => Opcode::XOR32mi_NF_ND, + 22166 => Opcode::XOR32mr, + 22167 => Opcode::XOR32mr_EVEX, + 22168 => Opcode::XOR32mr_ND, + 22169 => Opcode::XOR32mr_NF, + 22170 => Opcode::XOR32mr_NF_ND, + 22171 => Opcode::XOR32ri, + 22172 => Opcode::XOR32ri8, + 22173 => Opcode::XOR32ri8_EVEX, + 22174 => Opcode::XOR32ri8_ND, + 22175 => Opcode::XOR32ri8_NF, + 22176 => Opcode::XOR32ri8_NF_ND, + 22177 => Opcode::XOR32ri_EVEX, + 22178 => Opcode::XOR32ri_ND, + 22179 => Opcode::XOR32ri_NF, + 22180 => Opcode::XOR32ri_NF_ND, + 22181 => Opcode::XOR32rm, + 22182 => Opcode::XOR32rm_EVEX, + 22183 => Opcode::XOR32rm_ND, + 22184 => Opcode::XOR32rm_NF, + 22185 => Opcode::XOR32rm_NF_ND, + 22186 => Opcode::XOR32rr, + 22187 => Opcode::XOR32rr_EVEX, + 22188 => Opcode::XOR32rr_EVEX_REV, + 22189 => Opcode::XOR32rr_ND, + 22190 => Opcode::XOR32rr_ND_REV, + 22191 => Opcode::XOR32rr_NF, + 22192 => Opcode::XOR32rr_NF_ND, + 22193 => Opcode::XOR32rr_NF_ND_REV, + 22194 => Opcode::XOR32rr_NF_REV, + 22195 => Opcode::XOR32rr_REV, + 22196 => Opcode::XOR64i32, + 22197 => Opcode::XOR64mi32, + 22198 => Opcode::XOR64mi32_EVEX, + 22199 => Opcode::XOR64mi32_ND, + 22200 => Opcode::XOR64mi32_NF, + 22201 => Opcode::XOR64mi32_NF_ND, + 22202 => Opcode::XOR64mi8, + 22203 => Opcode::XOR64mi8_EVEX, + 22204 => Opcode::XOR64mi8_ND, + 22205 => Opcode::XOR64mi8_NF, + 22206 => Opcode::XOR64mi8_NF_ND, + 22207 => Opcode::XOR64mr, + 22208 => Opcode::XOR64mr_EVEX, + 22209 => Opcode::XOR64mr_ND, + 22210 => Opcode::XOR64mr_NF, + 22211 => Opcode::XOR64mr_NF_ND, + 22212 => Opcode::XOR64ri32, + 22213 => Opcode::XOR64ri32_EVEX, + 22214 => Opcode::XOR64ri32_ND, + 22215 => Opcode::XOR64ri32_NF, + 22216 => Opcode::XOR64ri32_NF_ND, + 22217 => Opcode::XOR64ri8, + 22218 => Opcode::XOR64ri8_EVEX, + 22219 => Opcode::XOR64ri8_ND, + 22220 => Opcode::XOR64ri8_NF, + 22221 => Opcode::XOR64ri8_NF_ND, + 22222 => Opcode::XOR64rm, + 22223 => Opcode::XOR64rm_EVEX, + 22224 => Opcode::XOR64rm_ND, + 22225 => Opcode::XOR64rm_NF, + 22226 => Opcode::XOR64rm_NF_ND, + 22227 => Opcode::XOR64rr, + 22228 => Opcode::XOR64rr_EVEX, + 22229 => Opcode::XOR64rr_EVEX_REV, + 22230 => Opcode::XOR64rr_ND, + 22231 => Opcode::XOR64rr_ND_REV, + 22232 => Opcode::XOR64rr_NF, + 22233 => Opcode::XOR64rr_NF_ND, + 22234 => Opcode::XOR64rr_NF_ND_REV, + 22235 => Opcode::XOR64rr_NF_REV, + 22236 => Opcode::XOR64rr_REV, + 22237 => Opcode::XOR8i8, + 22238 => Opcode::XOR8mi, + 22239 => Opcode::XOR8mi8, + 22240 => Opcode::XOR8mi_EVEX, + 22241 => Opcode::XOR8mi_ND, + 22242 => Opcode::XOR8mi_NF, + 22243 => Opcode::XOR8mi_NF_ND, + 22244 => Opcode::XOR8mr, + 22245 => Opcode::XOR8mr_EVEX, + 22246 => Opcode::XOR8mr_ND, + 22247 => Opcode::XOR8mr_NF, + 22248 => Opcode::XOR8mr_NF_ND, + 22249 => Opcode::XOR8ri, + 22250 => Opcode::XOR8ri8, + 22251 => Opcode::XOR8ri_EVEX, + 22252 => Opcode::XOR8ri_ND, + 22253 => Opcode::XOR8ri_NF, + 22254 => Opcode::XOR8ri_NF_ND, + 22255 => Opcode::XOR8rm, + 22256 => Opcode::XOR8rm_EVEX, + 22257 => Opcode::XOR8rm_ND, + 22258 => Opcode::XOR8rm_NF, + 22259 => Opcode::XOR8rm_NF_ND, + 22260 => Opcode::XOR8rr, + 22261 => Opcode::XOR8rr_EVEX, + 22262 => Opcode::XOR8rr_EVEX_REV, + 22263 => Opcode::XOR8rr_ND, + 22264 => Opcode::XOR8rr_ND_REV, + 22265 => Opcode::XOR8rr_NF, + 22266 => Opcode::XOR8rr_NF_ND, + 22267 => Opcode::XOR8rr_NF_ND_REV, + 22268 => Opcode::XOR8rr_NF_REV, + 22269 => Opcode::XOR8rr_NOREX, + 22270 => Opcode::XOR8rr_REV, + 22271 => Opcode::XORPDrm, + 22272 => Opcode::XORPDrr, + 22273 => Opcode::XORPSrm, + 22274 => Opcode::XORPSrr, + 22275 => Opcode::XRELEASE_PREFIX, + 22276 => Opcode::XRESLDTRK, + 22277 => Opcode::XRSTOR, + 22278 => Opcode::XRSTOR64, + 22279 => Opcode::XRSTORS, + 22280 => Opcode::XRSTORS64, + 22281 => Opcode::XSAVE, + 22282 => Opcode::XSAVE64, + 22283 => Opcode::XSAVEC, + 22284 => Opcode::XSAVEC64, + 22285 => Opcode::XSAVEOPT, + 22286 => Opcode::XSAVEOPT64, + 22287 => Opcode::XSAVES, + 22288 => Opcode::XSAVES64, + 22289 => Opcode::XSETBV, + 22290 => Opcode::XSHA1, + 22291 => Opcode::XSHA256, + 22292 => Opcode::XSTORE, + 22293 => Opcode::XSUSLDTRK, + 22294 => Opcode::XTEST, + 22295 => Opcode::INSTRUCTION_LIST_END, + _ => Opcode::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands.rs new file mode 100644 index 0000000..066d805 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +pub mod immediate; +pub mod memory; +pub mod pc_relative; +pub mod register; + +#[doc(inline)] +pub use register::Register; + +#[doc(inline)] +pub use pc_relative::PCRelative; + +#[doc(inline)] +pub use immediate::Immediate; + +#[doc(inline)] +pub use memory::Memory; + +/// Trait shared by **all** [`Operands`] +pub trait Operand { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand; + + /// Pretty representation of the operand + fn to_string(&self) -> String { + self.as_generic().to_string().to_string() + } +} + +/// This enum represents the different kind of operands associated with [`super::Instruction`] +pub enum Operands { + /// A register operand (e.g. `RIP`) + Reg(Register), + + /// A RIP/EIP-relative operand + PCRelative(PCRelative), + + /// An immediate value + Imm(Immediate), + + /// A memory operand + Mem(Memory), + + /// Operand that is not correctly supported + Unknown(Unknown), +} + +impl FromFFI for Operands { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let op_ref = ptr.as_ref().unwrap(); + if ffi::asm_x86_operands_Memory::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Mem(Memory::from_ffi(raw)); + } else if ffi::asm_x86_operands_Register::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Reg(Register::from_ffi(raw)); + } else if ffi::asm_x86_operands_Immediate::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::Imm(Immediate::from_ffi(raw)); + } else if ffi::asm_x86_operands_PCRelative::classof(op_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Operands::PCRelative(PCRelative::from_ffi(raw)); + } + Operands::Unknown(Unknown::from_ffi(ptr)) + } + } +} + +impl Operand for Operands { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + match &self { + Operands::Reg(op) => op.as_generic(), + + Operands::Imm(op) => op.as_generic(), + + Operands::Mem(op) => op.as_generic(), + + Operands::PCRelative(op) => op.as_generic(), + + Operands::Unknown(op) => op.as_generic(), + } + } +} + +pub struct Unknown { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Unknown { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Unknown { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + self.ptr.as_ref().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/immediate.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/immediate.rs new file mode 100644 index 0000000..58eaf63 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/immediate.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents an immediate operand. +/// +/// For instance: +/// +/// ```text +/// mov edi, 1; +/// | +/// +---> Immediate(1) +/// ``` +pub struct Immediate { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Immediate { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Immediate { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immediate { + /// The constant value wrapped by this operand + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/memory.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/memory.rs new file mode 100644 index 0000000..2f810a9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/memory.rs @@ -0,0 +1,75 @@ +use lief_ffi as ffi; + +use crate::{assembly::x86::registers::Reg, common::FromFFI}; + +use super::Operand; + +/// This structure represents a memory operand. +/// +/// For instance: +/// +/// ```text +/// movq xmm3, qword ptr [rip + 823864]; +/// +/// | +/// | +/// Memory +/// | +/// +-----------+-----------+ +/// | | | +/// Base: rip Scale: 1 Displacement: 823864 +/// +/// ``` +pub struct Memory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Memory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Memory { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Memory { + /// The base register. + /// + /// For `lea rdx, [rip + 244634]` it would return [`Reg::RIP`] + pub fn base(&self) -> Reg { + Reg::from(self.ptr.base()) + } + + /// The scaled register. + /// + /// For `mov rdi, qword ptr [r13 + 8*r14]` it would return [`Reg::R14`] + pub fn scaled_register(&self) -> Reg { + Reg::from(self.ptr.scaled_register()) + } + + /// The segment register associated with the memory operation. + /// + /// For `mov eax, dword ptr gs:[0]` is would return [`Reg::GS`] + pub fn segment_register(&self) -> Reg { + Reg::from(self.ptr.segment_register()) + } + + /// The scale value associated with the [`Memory::scaled_register`] + /// + /// For `mov rdi, qword ptr [r13 + 8*r14]` it would return `8` + pub fn scale(&self) -> u64 { + self.ptr.scale() + } + + /// The displacement value + /// + /// For `call qword ptr [rip + 248779]` it would return `248779` + pub fn displacement(&self) -> i64 { + self.ptr.displacement() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/pc_relative.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/pc_relative.rs new file mode 100644 index 0000000..0848525 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/pc_relative.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a RIP/EIP-relative operand. +/// +/// For instance: +/// +/// ```text +/// jmp 67633; +/// | +/// +----------> PCRelative(67633) +/// ``` +pub struct PCRelative { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PCRelative { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for PCRelative { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PCRelative { + /// The effective value that is relative to the current `rip/eip` register + pub fn value(&self) -> i64 { + self.ptr.value() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/register.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/register.rs new file mode 100644 index 0000000..a97ff59 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/operands/register.rs @@ -0,0 +1,41 @@ +use lief_ffi as ffi; + +use crate::assembly::x86::registers::Reg; +use crate::common::FromFFI; + +use super::Operand; + +/// This structure represents a register operand. +/// +/// For instance: +/// +/// ```text +/// mov r15d, edi +/// | | +/// | +---------> Register(EDI) +/// | +/// +---------------> Register(R15D) +/// ``` +pub struct Register { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Register { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Operand for Register { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::asm_x86_Operand { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Register { + /// The effective register wrapped by this operand + pub fn value(&self) -> Reg { + Reg::from(self.ptr.value()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/assembly/x86/registers.rs b/vendor/lief/api/rust/crates/lief/src/assembly/x86/registers.rs new file mode 100644 index 0000000..6a48f37 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/assembly/x86/registers.rs @@ -0,0 +1,791 @@ +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Reg { + NoRegister, + AH, + AL, + AX, + BH, + BL, + BP, + BPH, + BPL, + BX, + CH, + CL, + CS, + CX, + DF, + DH, + DI, + DIH, + DIL, + DL, + DS, + DX, + EAX, + EBP, + EBX, + ECX, + EDI, + EDX, + EFLAGS, + EIP, + EIZ, + ES, + ESI, + ESP, + FPCW, + FPSW, + FS, + FS_BASE, + GS, + GS_BASE, + HAX, + HBP, + HBX, + HCX, + HDI, + HDX, + HIP, + HSI, + HSP, + IP, + MXCSR, + RAX, + RBP, + RBX, + RCX, + RDI, + RDX, + RFLAGS, + RIP, + RIZ, + RSI, + RSP, + SI, + SIH, + SIL, + SP, + SPH, + SPL, + SS, + SSP, + _EFLAGS, + CR0, + CR1, + CR2, + CR3, + CR4, + CR5, + CR6, + CR7, + CR8, + CR9, + CR10, + CR11, + CR12, + CR13, + CR14, + CR15, + DR0, + DR1, + DR2, + DR3, + DR4, + DR5, + DR6, + DR7, + DR8, + DR9, + DR10, + DR11, + DR12, + DR13, + DR14, + DR15, + FP0, + FP1, + FP2, + FP3, + FP4, + FP5, + FP6, + FP7, + MM0, + MM1, + MM2, + MM3, + MM4, + MM5, + MM6, + MM7, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + ST0, + ST1, + ST2, + ST3, + ST4, + ST5, + ST6, + ST7, + XMM0, + XMM1, + XMM2, + XMM3, + XMM4, + XMM5, + XMM6, + XMM7, + XMM8, + XMM9, + XMM10, + XMM11, + XMM12, + XMM13, + XMM14, + XMM15, + R8B, + R9B, + R10B, + R11B, + R12B, + R13B, + R14B, + R15B, + R8BH, + R9BH, + R10BH, + R11BH, + R12BH, + R13BH, + R14BH, + R15BH, + R8D, + R9D, + R10D, + R11D, + R12D, + R13D, + R14D, + R15D, + R8W, + R9W, + R10W, + R11W, + R12W, + R13W, + R14W, + R15W, + R8WH, + R9WH, + R10WH, + R11WH, + R12WH, + R13WH, + R14WH, + R15WH, + YMM0, + YMM1, + YMM2, + YMM3, + YMM4, + YMM5, + YMM6, + YMM7, + YMM8, + YMM9, + YMM10, + YMM11, + YMM12, + YMM13, + YMM14, + YMM15, + K0, + K1, + K2, + K3, + K4, + K5, + K6, + K7, + XMM16, + XMM17, + XMM18, + XMM19, + XMM20, + XMM21, + XMM22, + XMM23, + XMM24, + XMM25, + XMM26, + XMM27, + XMM28, + XMM29, + XMM30, + XMM31, + YMM16, + YMM17, + YMM18, + YMM19, + YMM20, + YMM21, + YMM22, + YMM23, + YMM24, + YMM25, + YMM26, + YMM27, + YMM28, + YMM29, + YMM30, + YMM31, + ZMM0, + ZMM1, + ZMM2, + ZMM3, + ZMM4, + ZMM5, + ZMM6, + ZMM7, + ZMM8, + ZMM9, + ZMM10, + ZMM11, + ZMM12, + ZMM13, + ZMM14, + ZMM15, + ZMM16, + ZMM17, + ZMM18, + ZMM19, + ZMM20, + ZMM21, + ZMM22, + ZMM23, + ZMM24, + ZMM25, + ZMM26, + ZMM27, + ZMM28, + ZMM29, + ZMM30, + ZMM31, + K0_K1, + K2_K3, + K4_K5, + K6_K7, + TMMCFG, + TMM0, + TMM1, + TMM2, + TMM3, + TMM4, + TMM5, + TMM6, + TMM7, + R16, + R17, + R18, + R19, + R20, + R21, + R22, + R23, + R24, + R25, + R26, + R27, + R28, + R29, + R30, + R31, + R16B, + R17B, + R18B, + R19B, + R20B, + R21B, + R22B, + R23B, + R24B, + R25B, + R26B, + R27B, + R28B, + R29B, + R30B, + R31B, + R16BH, + R17BH, + R18BH, + R19BH, + R20BH, + R21BH, + R22BH, + R23BH, + R24BH, + R25BH, + R26BH, + R27BH, + R28BH, + R29BH, + R30BH, + R31BH, + R16D, + R17D, + R18D, + R19D, + R20D, + R21D, + R22D, + R23D, + R24D, + R25D, + R26D, + R27D, + R28D, + R29D, + R30D, + R31D, + R16W, + R17W, + R18W, + R19W, + R20W, + R21W, + R22W, + R23W, + R24W, + R25W, + R26W, + R27W, + R28W, + R29W, + R30W, + R31W, + R16WH, + R17WH, + R18WH, + R19WH, + R20WH, + R21WH, + R22WH, + R23WH, + R24WH, + R25WH, + R26WH, + R27WH, + R28WH, + R29WH, + R30WH, + R31WH, + NUM_TARGET_REGS, + UNKNOWN(u64), +} + +impl From for Reg { + fn from(value: u64) -> Self { + match value { + 0 => Reg::NoRegister, + 1 => Reg::AH, + 2 => Reg::AL, + 3 => Reg::AX, + 4 => Reg::BH, + 5 => Reg::BL, + 6 => Reg::BP, + 7 => Reg::BPH, + 8 => Reg::BPL, + 9 => Reg::BX, + 10 => Reg::CH, + 11 => Reg::CL, + 12 => Reg::CS, + 13 => Reg::CX, + 14 => Reg::DF, + 15 => Reg::DH, + 16 => Reg::DI, + 17 => Reg::DIH, + 18 => Reg::DIL, + 19 => Reg::DL, + 20 => Reg::DS, + 21 => Reg::DX, + 22 => Reg::EAX, + 23 => Reg::EBP, + 24 => Reg::EBX, + 25 => Reg::ECX, + 26 => Reg::EDI, + 27 => Reg::EDX, + 28 => Reg::EFLAGS, + 29 => Reg::EIP, + 30 => Reg::EIZ, + 31 => Reg::ES, + 32 => Reg::ESI, + 33 => Reg::ESP, + 34 => Reg::FPCW, + 35 => Reg::FPSW, + 36 => Reg::FS, + 37 => Reg::FS_BASE, + 38 => Reg::GS, + 39 => Reg::GS_BASE, + 40 => Reg::HAX, + 41 => Reg::HBP, + 42 => Reg::HBX, + 43 => Reg::HCX, + 44 => Reg::HDI, + 45 => Reg::HDX, + 46 => Reg::HIP, + 47 => Reg::HSI, + 48 => Reg::HSP, + 49 => Reg::IP, + 50 => Reg::MXCSR, + 51 => Reg::RAX, + 52 => Reg::RBP, + 53 => Reg::RBX, + 54 => Reg::RCX, + 55 => Reg::RDI, + 56 => Reg::RDX, + 57 => Reg::RFLAGS, + 58 => Reg::RIP, + 59 => Reg::RIZ, + 60 => Reg::RSI, + 61 => Reg::RSP, + 62 => Reg::SI, + 63 => Reg::SIH, + 64 => Reg::SIL, + 65 => Reg::SP, + 66 => Reg::SPH, + 67 => Reg::SPL, + 68 => Reg::SS, + 69 => Reg::SSP, + 70 => Reg::_EFLAGS, + 71 => Reg::CR0, + 72 => Reg::CR1, + 73 => Reg::CR2, + 74 => Reg::CR3, + 75 => Reg::CR4, + 76 => Reg::CR5, + 77 => Reg::CR6, + 78 => Reg::CR7, + 79 => Reg::CR8, + 80 => Reg::CR9, + 81 => Reg::CR10, + 82 => Reg::CR11, + 83 => Reg::CR12, + 84 => Reg::CR13, + 85 => Reg::CR14, + 86 => Reg::CR15, + 87 => Reg::DR0, + 88 => Reg::DR1, + 89 => Reg::DR2, + 90 => Reg::DR3, + 91 => Reg::DR4, + 92 => Reg::DR5, + 93 => Reg::DR6, + 94 => Reg::DR7, + 95 => Reg::DR8, + 96 => Reg::DR9, + 97 => Reg::DR10, + 98 => Reg::DR11, + 99 => Reg::DR12, + 100 => Reg::DR13, + 101 => Reg::DR14, + 102 => Reg::DR15, + 103 => Reg::FP0, + 104 => Reg::FP1, + 105 => Reg::FP2, + 106 => Reg::FP3, + 107 => Reg::FP4, + 108 => Reg::FP5, + 109 => Reg::FP6, + 110 => Reg::FP7, + 111 => Reg::MM0, + 112 => Reg::MM1, + 113 => Reg::MM2, + 114 => Reg::MM3, + 115 => Reg::MM4, + 116 => Reg::MM5, + 117 => Reg::MM6, + 118 => Reg::MM7, + 119 => Reg::R8, + 120 => Reg::R9, + 121 => Reg::R10, + 122 => Reg::R11, + 123 => Reg::R12, + 124 => Reg::R13, + 125 => Reg::R14, + 126 => Reg::R15, + 127 => Reg::ST0, + 128 => Reg::ST1, + 129 => Reg::ST2, + 130 => Reg::ST3, + 131 => Reg::ST4, + 132 => Reg::ST5, + 133 => Reg::ST6, + 134 => Reg::ST7, + 135 => Reg::XMM0, + 136 => Reg::XMM1, + 137 => Reg::XMM2, + 138 => Reg::XMM3, + 139 => Reg::XMM4, + 140 => Reg::XMM5, + 141 => Reg::XMM6, + 142 => Reg::XMM7, + 143 => Reg::XMM8, + 144 => Reg::XMM9, + 145 => Reg::XMM10, + 146 => Reg::XMM11, + 147 => Reg::XMM12, + 148 => Reg::XMM13, + 149 => Reg::XMM14, + 150 => Reg::XMM15, + 151 => Reg::R8B, + 152 => Reg::R9B, + 153 => Reg::R10B, + 154 => Reg::R11B, + 155 => Reg::R12B, + 156 => Reg::R13B, + 157 => Reg::R14B, + 158 => Reg::R15B, + 159 => Reg::R8BH, + 160 => Reg::R9BH, + 161 => Reg::R10BH, + 162 => Reg::R11BH, + 163 => Reg::R12BH, + 164 => Reg::R13BH, + 165 => Reg::R14BH, + 166 => Reg::R15BH, + 167 => Reg::R8D, + 168 => Reg::R9D, + 169 => Reg::R10D, + 170 => Reg::R11D, + 171 => Reg::R12D, + 172 => Reg::R13D, + 173 => Reg::R14D, + 174 => Reg::R15D, + 175 => Reg::R8W, + 176 => Reg::R9W, + 177 => Reg::R10W, + 178 => Reg::R11W, + 179 => Reg::R12W, + 180 => Reg::R13W, + 181 => Reg::R14W, + 182 => Reg::R15W, + 183 => Reg::R8WH, + 184 => Reg::R9WH, + 185 => Reg::R10WH, + 186 => Reg::R11WH, + 187 => Reg::R12WH, + 188 => Reg::R13WH, + 189 => Reg::R14WH, + 190 => Reg::R15WH, + 191 => Reg::YMM0, + 192 => Reg::YMM1, + 193 => Reg::YMM2, + 194 => Reg::YMM3, + 195 => Reg::YMM4, + 196 => Reg::YMM5, + 197 => Reg::YMM6, + 198 => Reg::YMM7, + 199 => Reg::YMM8, + 200 => Reg::YMM9, + 201 => Reg::YMM10, + 202 => Reg::YMM11, + 203 => Reg::YMM12, + 204 => Reg::YMM13, + 205 => Reg::YMM14, + 206 => Reg::YMM15, + 207 => Reg::K0, + 208 => Reg::K1, + 209 => Reg::K2, + 210 => Reg::K3, + 211 => Reg::K4, + 212 => Reg::K5, + 213 => Reg::K6, + 214 => Reg::K7, + 215 => Reg::XMM16, + 216 => Reg::XMM17, + 217 => Reg::XMM18, + 218 => Reg::XMM19, + 219 => Reg::XMM20, + 220 => Reg::XMM21, + 221 => Reg::XMM22, + 222 => Reg::XMM23, + 223 => Reg::XMM24, + 224 => Reg::XMM25, + 225 => Reg::XMM26, + 226 => Reg::XMM27, + 227 => Reg::XMM28, + 228 => Reg::XMM29, + 229 => Reg::XMM30, + 230 => Reg::XMM31, + 231 => Reg::YMM16, + 232 => Reg::YMM17, + 233 => Reg::YMM18, + 234 => Reg::YMM19, + 235 => Reg::YMM20, + 236 => Reg::YMM21, + 237 => Reg::YMM22, + 238 => Reg::YMM23, + 239 => Reg::YMM24, + 240 => Reg::YMM25, + 241 => Reg::YMM26, + 242 => Reg::YMM27, + 243 => Reg::YMM28, + 244 => Reg::YMM29, + 245 => Reg::YMM30, + 246 => Reg::YMM31, + 247 => Reg::ZMM0, + 248 => Reg::ZMM1, + 249 => Reg::ZMM2, + 250 => Reg::ZMM3, + 251 => Reg::ZMM4, + 252 => Reg::ZMM5, + 253 => Reg::ZMM6, + 254 => Reg::ZMM7, + 255 => Reg::ZMM8, + 256 => Reg::ZMM9, + 257 => Reg::ZMM10, + 258 => Reg::ZMM11, + 259 => Reg::ZMM12, + 260 => Reg::ZMM13, + 261 => Reg::ZMM14, + 262 => Reg::ZMM15, + 263 => Reg::ZMM16, + 264 => Reg::ZMM17, + 265 => Reg::ZMM18, + 266 => Reg::ZMM19, + 267 => Reg::ZMM20, + 268 => Reg::ZMM21, + 269 => Reg::ZMM22, + 270 => Reg::ZMM23, + 271 => Reg::ZMM24, + 272 => Reg::ZMM25, + 273 => Reg::ZMM26, + 274 => Reg::ZMM27, + 275 => Reg::ZMM28, + 276 => Reg::ZMM29, + 277 => Reg::ZMM30, + 278 => Reg::ZMM31, + 279 => Reg::K0_K1, + 280 => Reg::K2_K3, + 281 => Reg::K4_K5, + 282 => Reg::K6_K7, + 283 => Reg::TMMCFG, + 284 => Reg::TMM0, + 285 => Reg::TMM1, + 286 => Reg::TMM2, + 287 => Reg::TMM3, + 288 => Reg::TMM4, + 289 => Reg::TMM5, + 290 => Reg::TMM6, + 291 => Reg::TMM7, + 292 => Reg::R16, + 293 => Reg::R17, + 294 => Reg::R18, + 295 => Reg::R19, + 296 => Reg::R20, + 297 => Reg::R21, + 298 => Reg::R22, + 299 => Reg::R23, + 300 => Reg::R24, + 301 => Reg::R25, + 302 => Reg::R26, + 303 => Reg::R27, + 304 => Reg::R28, + 305 => Reg::R29, + 306 => Reg::R30, + 307 => Reg::R31, + 308 => Reg::R16B, + 309 => Reg::R17B, + 310 => Reg::R18B, + 311 => Reg::R19B, + 312 => Reg::R20B, + 313 => Reg::R21B, + 314 => Reg::R22B, + 315 => Reg::R23B, + 316 => Reg::R24B, + 317 => Reg::R25B, + 318 => Reg::R26B, + 319 => Reg::R27B, + 320 => Reg::R28B, + 321 => Reg::R29B, + 322 => Reg::R30B, + 323 => Reg::R31B, + 324 => Reg::R16BH, + 325 => Reg::R17BH, + 326 => Reg::R18BH, + 327 => Reg::R19BH, + 328 => Reg::R20BH, + 329 => Reg::R21BH, + 330 => Reg::R22BH, + 331 => Reg::R23BH, + 332 => Reg::R24BH, + 333 => Reg::R25BH, + 334 => Reg::R26BH, + 335 => Reg::R27BH, + 336 => Reg::R28BH, + 337 => Reg::R29BH, + 338 => Reg::R30BH, + 339 => Reg::R31BH, + 340 => Reg::R16D, + 341 => Reg::R17D, + 342 => Reg::R18D, + 343 => Reg::R19D, + 344 => Reg::R20D, + 345 => Reg::R21D, + 346 => Reg::R22D, + 347 => Reg::R23D, + 348 => Reg::R24D, + 349 => Reg::R25D, + 350 => Reg::R26D, + 351 => Reg::R27D, + 352 => Reg::R28D, + 353 => Reg::R29D, + 354 => Reg::R30D, + 355 => Reg::R31D, + 356 => Reg::R16W, + 357 => Reg::R17W, + 358 => Reg::R18W, + 359 => Reg::R19W, + 360 => Reg::R20W, + 361 => Reg::R21W, + 362 => Reg::R22W, + 363 => Reg::R23W, + 364 => Reg::R24W, + 365 => Reg::R25W, + 366 => Reg::R26W, + 367 => Reg::R27W, + 368 => Reg::R28W, + 369 => Reg::R29W, + 370 => Reg::R30W, + 371 => Reg::R31W, + 372 => Reg::R16WH, + 373 => Reg::R17WH, + 374 => Reg::R18WH, + 375 => Reg::R19WH, + 376 => Reg::R20WH, + 377 => Reg::R21WH, + 378 => Reg::R22WH, + 379 => Reg::R23WH, + 380 => Reg::R24WH, + 381 => Reg::R25WH, + 382 => Reg::R26WH, + 383 => Reg::R27WH, + 384 => Reg::R28WH, + 385 => Reg::R29WH, + 386 => Reg::R30WH, + 387 => Reg::R31WH, + 388 => Reg::NUM_TARGET_REGS, + _ => Reg::UNKNOWN(value), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/binary.rs b/vendor/lief/api/rust/crates/lief/src/binary.rs new file mode 100644 index 0000000..0d11ab8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/binary.rs @@ -0,0 +1,109 @@ +use lief_ffi as ffi; + +use super::coff; +use super::elf; +use super::macho; +use super::pe; +use crate::common::FromFFI; +use std::io::{Read, Seek}; +use std::path::Path; + +#[derive(Debug)] +/// Enum that wraps all the executable formats supported by LIEF +pub enum Binary { + /// An ELF binary + ELF(elf::Binary), + + /// A PE binary + PE(pe::Binary), + + /// A Mach-O (FAT) binary + MachO(macho::FatBinary), + + /// A COFF binary object + COFF(coff::Binary), +} + +impl Binary { + /// Parse from a file path + /// + /// ``` + /// if let Some(Binary::ELF(elf)) = Binary::parse("/bin/ls") { + /// // ... + /// } + /// ``` + pub fn parse>(path: P) -> Option { + let path_str = path.as_ref().to_str().unwrap(); + cxx::let_cxx_string!(__cxx_s = path_str); + if ffi::ELF_Utils::is_elf(&__cxx_s) { + if let Some(elf) = elf::Binary::parse(path) { + return Some(Binary::ELF(elf)); + } + return None; + } + cxx::let_cxx_string!(__cxx_s = path_str); + if ffi::PE_Utils::is_pe(&__cxx_s) { + if let Some(pe) = pe::Binary::parse(path) { + return Some(Binary::PE(pe)); + } + return None; + } + cxx::let_cxx_string!(__cxx_s = path_str); + if ffi::MachO_Utils::is_macho(&__cxx_s) { + if let Some(fat) = macho::FatBinary::parse(path) { + return Some(Binary::MachO(fat)); + } + return None; + } + + cxx::let_cxx_string!(__cxx_s = path_str); + if ffi::COFF_Utils::is_coff(&__cxx_s) { + if let Some(coff) = coff::Binary::parse(path) { + return Some(Binary::COFF(coff)); + } + return None; + } + None + } + /// Parse from an input that implements `Read + Seek` traits + /// + /// ``` + /// let mut file = std::fs::File::open("C:/test.ext").expect("Can't open the file"); + /// if let Some(Binary::PE(pe)) = Binary::from(&mut file) { + /// // ... + /// } + /// ``` + pub fn from(reader: &mut R) -> Option { + let mut buffer = std::vec::Vec::new(); + if reader.read_to_end(&mut buffer).is_err() { + return None; + } + + let mut ffi_stream = + unsafe { ffi::RustStream::from_rust(buffer.as_mut_ptr(), buffer.len()) }; + buffer.clear(); + + if ffi_stream.is_elf() { + return Some(Binary::ELF(elf::Binary::from_ffi( + ffi_stream.pin_mut().as_elf(), + ))); + } + if ffi_stream.is_macho() { + return Some(Binary::MachO(macho::FatBinary::from_ffi( + ffi_stream.pin_mut().as_macho(), + ))); + } + if ffi_stream.is_pe() { + return Some(Binary::PE(pe::Binary::from_ffi( + ffi_stream.pin_mut().as_pe(), + ))); + } + + if ffi_stream.is_coff() { + return Some(Binary::COFF(coff::Binary::from_ffi( + ffi_stream.pin_mut().as_coff(), + ))); + } + None + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/coff.rs b/vendor/lief/api/rust/crates/lief/src/coff.rs new file mode 100644 index 0000000..6a8112d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff.rs @@ -0,0 +1,48 @@ +//! Module for the COFF file format support in LIEF. +//! +//! The [`Binary`] structure exposes the main API to inspect a COFF file. It can be instantiated, +//! using either: [`crate::coff::parse`], [`crate::coff::Binary::parse`] or [`crate::Binary::parse`] +//! +//! ``` +//! let coff = lief::coff::parse("demo.obj").unwrap(); +//! for section in coff.sections() { +//! println!("section: {}", section.name()); +//! } +//! ``` + +use std::path::Path; + +pub mod binary; +pub mod header; +pub mod relocation; +pub mod section; +pub mod string; +pub mod symbol; + +#[doc(inline)] +pub use symbol::Symbol; + +#[doc(inline)] +pub use string::String; + +#[doc(inline)] +pub use binary::Binary; + +#[doc(inline)] +pub use section::Section; + +#[doc(inline)] +pub use relocation::Relocation; + +#[doc(inline)] +pub use header::{BigObjHeader, Header, RegularHeader}; + +/// Parse a COFF file from the given file path +pub fn parse>(path: P) -> Option { + Binary::parse(path) +} + +pub fn is_coff>(path: P) -> bool { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + lief_ffi::COFF_Utils::is_coff(&__cxx_s) +} diff --git a/vendor/lief/api/rust/crates/lief/src/coff/binary.rs b/vendor/lief/api/rust/crates/lief/src/coff/binary.rs new file mode 100644 index 0000000..a2bc12b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/binary.rs @@ -0,0 +1,201 @@ +use super::{Header, Relocation, Section, String, Symbol}; +use crate::assembly::Instructions; +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::{declare_iterator, declare_lazy_iterator}; +use lief_ffi as ffi; +use std::path::Path; + +pub struct Binary { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Binary { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Binary { + /// Parse from a file path given as a string + pub fn parse>(path: P) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::COFF_Binary::parse(&__cxx_s); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// The COFF header + pub fn header(&self) -> Header<'_> { + Header::from_ffi(self.ptr.header()) + } + + /// Iterator over the different sections located in this COFF binary + pub fn sections(&self) -> Sections<'_> { + Sections::new(self.ptr.sections()) + } + + /// Find the section matching the given name. + /// + /// Section names that do not fit in the 8 bytes allocated by the COFF format are stored + /// in the COFF string table while the section itself only holds a `/` placeholder. + /// This function transparently resolves both forms, so a long name can be looked up with + /// its **regular** value: + /// + /// ``` + /// let section = binary.section_by_name(".debug_rnglists").unwrap(); + /// assert_eq!(section.name(), "/18"); + /// assert_eq!(section.coff_string().unwrap().str(), ".debug_rnglists"); + /// ``` + pub fn section_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.section_by_name(&__cxx_s)) + } + + /// Iterator over **all** the relocations used by this COFF binary + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// Iterator over the COFF's symbols + pub fn symbols(&self) -> Symbols<'_> { + Symbols::new(self.ptr.symbols()) + } + + /// Iterator over the functions implemented in this COFF + pub fn functions(&self) -> Functions<'_> { + Functions::new(self.ptr.functions()) + } + + /// Iterator over the COFF's strings + pub fn string_table(&self) -> Strings<'_> { + Strings::new(self.ptr.string_table()) + } + + /// Try to find the COFF string at the given offset in the COFF string table. + /// + ///
+ /// This offset must include the first 4 bytes holding the size of the table. Hence, + /// the first string starts a the offset 4. + ///
+ pub fn find_string(&self, offset: u32) -> Option> { + into_optional(self.ptr.find_string(offset)) + } + + /// Try to find the function (symbol) with the given name + pub fn find_function(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.find_function(&__cxx_s)) + } + + /// Try to find the function (symbol) with the given **demangled** name + pub fn find_demangled_function(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.find_demangled_function(&__cxx_s)) + } + + /// Disassemble code provided by the given slice at the specified `address` parameter. + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + pub fn disassemble_slice(&self, slice: &[u8], address: u64) -> InstructionsIt<'_> { + unsafe { + InstructionsIt::new(self.ptr.disassemble_buffer( + slice.as_ptr(), + slice.len().try_into().unwrap(), + address, + )) + } + } + + /// Disassemble code for the given function name + /// + /// ``` + /// let insts = binary.disassemble_function("int __cdecl bar(int, int)"); + /// for inst in insts { + /// println!("{}", inst.to_string()); + /// } + /// ``` + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + pub fn disassemble_function(&self, name: &str) -> InstructionsIt<'_> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + InstructionsIt::new(self.ptr.disassemble_function(&__cxx_s)) + } + + /// Disassemble code for the given symbol + /// + /// ``` + /// let symbol = binary.find_demangled_function("int __cdecl bar(int, int)").unwrap(); + /// let insts = binary.disassemble_symbol(&symbol); + /// for inst in insts { + /// println!("{}", inst.to_string()); + /// } + /// ``` + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + pub fn disassemble_symbol(&self, symbol: &Symbol) -> InstructionsIt<'_> { + InstructionsIt::new(self.ptr.disassemble_symbol(symbol.ptr.as_ref().unwrap())) + } +} + +impl std::fmt::Display for Binary { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl std::fmt::Debug for Binary { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("COFF Binary").finish() + } +} + +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::COFF_Relocation, + ffi::COFF_Binary, + ffi::COFF_Binary_it_relocations +); + +declare_iterator!( + Sections, + Section<'a>, + ffi::COFF_Section, + ffi::COFF_Binary, + ffi::COFF_Binary_it_sections +); + +declare_iterator!( + Symbols, + Symbol<'a>, + ffi::COFF_Symbol, + ffi::COFF_Binary, + ffi::COFF_Binary_it_symbols +); + +declare_iterator!( + Strings, + String<'a>, + ffi::COFF_String, + ffi::COFF_Binary, + ffi::COFF_Binary_it_strings +); + +declare_iterator!( + Functions, + Symbol<'a>, + ffi::COFF_Symbol, + ffi::COFF_Binary, + ffi::COFF_Binary_it_functions +); + +declare_lazy_iterator!( + InstructionsIt, + Instructions, + ffi::asm_Instruction, + ffi::COFF_Binary, + ffi::COFF_Binary_it_instructions +); diff --git a/vendor/lief/api/rust/crates/lief/src/coff/header.rs b/vendor/lief/api/rust/crates/lief/src/coff/header.rs new file mode 100644 index 0000000..407cdd4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/header.rs @@ -0,0 +1,225 @@ +//! COFF section module + +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pe; +use crate::to_slice; + +/// This enum represents the different types of COFF header. +pub enum Header<'a> { + /// Regular (default) header + Regular(RegularHeader<'a>), + + /// Header for COFF files that contain more than 65536 sections (compiled with `/bigobj`) + BigObj(BigObjHeader<'a>), +} + +impl FromFFI for Header<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::COFF_RegularHeader::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Header::Regular(RegularHeader::from_ffi(raw)) + } else if ffi::COFF_BigObjHeader::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Header::BigObj(BigObjHeader::from_ffi(raw)) + } else { + panic!("unsupported header"); + } + } + } +} + +/// Trait shared by the different COFF headers +pub trait GenericHeader { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::COFF_Header; + + /// The machine type targeted by this COFF + fn machine(&self) -> pe::headers::MachineType { + pe::headers::MachineType::from(self.as_generic().machine()) + } + + /// The number of sections + fn nb_sections(&self) -> u32 { + self.as_generic().nb_sections() + } + + /// Offset of the symbols table + fn pointerto_symbol_table(&self) -> u32 { + self.as_generic().pointerto_symbol_table() + } + + /// Number of symbols (including auxiliary symbols) + fn nb_symbols(&self) -> u32 { + self.as_generic().nb_symbols() + } + + /// Timestamp when the COFF has been generated + fn timedatestamp(&self) -> u32 { + self.as_generic().timedatestamp() + } +} + +impl GenericHeader for Header<'_> { + fn as_generic(&self) -> &ffi::COFF_Header { + match &self { + Header::Regular(h) => h.as_generic(), + Header::BigObj(h) => h.as_generic(), + } + } +} + +impl std::fmt::Debug for &dyn GenericHeader { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("GenericHeader") + .field("machine", &self.machine()) + .field("nb_sections", &self.nb_sections()) + .field("pointerto_symbol_table", &self.pointerto_symbol_table()) + .field("nb_symbols", &self.nb_symbols()) + .field("timedatestamp", &self.timedatestamp()) + .finish() + } +} + +impl std::fmt::Display for &dyn GenericHeader { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +/// Regular (default) header +pub struct RegularHeader<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Binary>, +} + +impl FromFFI for RegularHeader<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RegularHeader<'_> { + /// The size of the optional header that follows this header (should be 0) + pub fn sizeof_optionalheader(&self) -> u16 { + self.ptr.sizeof_optionalheader() + } + + /// Characteristics + pub fn characteristics(&self) -> u16 { + self.ptr.characteristics() + } +} + +impl GenericHeader for RegularHeader<'_> { + fn as_generic(&self) -> &ffi::COFF_Header { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for RegularHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn GenericHeader; + f.debug_struct("RegularHeader") + .field("base", &base) + .field("sizeof_optionalheader", &self.sizeof_optionalheader()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +impl std::fmt::Display for RegularHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +/// Header for COFF files that contain more than 65536 sections (compiled with `/bigobj`) +pub struct BigObjHeader<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Binary>, +} + +impl FromFFI for BigObjHeader<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl BigObjHeader<'_> { + /// The version of this header which must be >= 2 + pub fn version(&self) -> u16 { + self.ptr.version() + } + + /// Originally named `ClassID`, this uuid should match: `{D1BAA1C7-BAEE-4ba9-AF20-FAF66AA4DCB8}` + pub fn uuid(&self) -> &[u8] { + to_slice!(self.ptr.uuid()); + } + + /// Size of data that follows the header + pub fn sizeof_data(&self) -> u32 { + self.ptr.sizeof_data() + } + + /// 1 means that it contains metadata + pub fn flags(&self) -> u32 { + self.ptr.flags() + } + + /// Size of CLR metadata + pub fn metadata_size(&self) -> u32 { + self.ptr.metadata_size() + } + + /// Offset of CLR metadata + pub fn metadata_offset(&self) -> u32 { + self.ptr.metadata_offset() + } +} + +impl std::fmt::Debug for BigObjHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn GenericHeader; + f.debug_struct("BigObjHeader") + .field("base", &base) + .field("version", &self.version()) + .field("uuid", &self.uuid()) + .field("sizeof_data", &self.sizeof_data()) + .field("flags", &self.flags()) + .field("metadata_size", &self.metadata_size()) + .field("metadata_offset", &self.metadata_offset()) + .finish() + } +} + +impl GenericHeader for BigObjHeader<'_> { + fn as_generic(&self) -> &ffi::COFF_Header { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for BigObjHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/coff/relocation.rs b/vendor/lief/api/rust/crates/lief/src/coff/relocation.rs new file mode 100644 index 0000000..077f6da --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/relocation.rs @@ -0,0 +1,324 @@ +//! COFF relocation module + +use super::{Section, Symbol}; +use crate::common::{FromFFI, into_optional}; +use crate::generic; +use std::marker::PhantomData; + +use lief_ffi as ffi; + +/// This class represents a COFF relocation +pub struct Relocation<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Binary>, +} + +impl FromFFI for Relocation<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Relocation { + ptr, + _owner: PhantomData, + } + } +} + +impl generic::Relocation for Relocation<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Relocation<'_> { + /// Symbol index associated with this relocation + pub fn symbol_idx(&self) -> u32 { + self.ptr.symbol_idx() + } + + /// Symbol associated with the relocation (if any) + pub fn symbol(&self) -> Option> { + into_optional(self.ptr.symbol()) + } + + /// Type of the relocation + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + + /// Section in which the relocation takes place + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } +} + +impl std::fmt::Debug for Relocation<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Relocation; + f.debug_struct("Relocation") + .field("base", &base) + .field("symbol_idx", &self.symbol_idx()) + .field("type", &self.get_type()) + .finish() + } +} + +impl std::fmt::Display for Relocation<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Type { + I386_ABSOLUTE, + I386_DIR16, + I386_REL16, + I386_DIR32, + I386_DIR32NB, + I386_SEG12, + I386_SECTION, + I386_SECREL, + I386_TOKEN, + I386_SECREL7, + I386_REL32, + AMD64_ABSOLUTE, + AMD64_ADDR64, + AMD64_ADDR32, + AMD64_ADDR32NB, + AMD64_REL32, + AMD64_REL32_1, + AMD64_REL32_2, + AMD64_REL32_3, + AMD64_REL32_4, + AMD64_REL32_5, + AMD64_SECTION, + AMD64_SECREL, + AMD64_SECREL7, + AMD64_TOKEN, + AMD64_SREL32, + AMD64_PAIR, + AMD64_SSPAN32, + ARM_ABSOLUTE, + ARM_ADDR32, + ARM_ADDR32NB, + ARM_BRANCH24, + ARM_BRANCH11, + ARM_TOKEN, + ARM_BLX24, + ARM_BLX11, + ARM_REL32, + ARM_SECTION, + ARM_SECREL, + ARM_MOV32A, + ARM_MOV32T, + ARM_BRANCH20T, + ARM_BRANCH24T, + ARM_BLX23T, + ARM_PAIR, + ARM64_ABSOLUTE, + ARM64_ADDR32, + ARM64_ADDR32NB, + ARM64_BRANCH26, + ARM64_PAGEBASE_REL21, + ARM64_REL21, + ARM64_PAGEOFFSET_12A, + ARM64_PAGEOFFSET_12L, + ARM64_SECREL, + ARM64_SECREL_LOW12A, + ARM64_SECREL_HIGH12A, + ARM64_SECREL_LOW12L, + ARM64_TOKEN, + ARM64_SECTION, + ARM64_ADDR64, + ARM64_BRANCH19, + ARM64_BRANCH14, + ARM64_REL32, + MIPS_ABSOLUTE, + MIPS_REFHALF, + MIPS_REFWORD, + MIPS_JMPADDR, + MIPS_REFHI, + MIPS_REFLO, + MIPS_GPREL, + MIPS_LITERAL, + MIPS_SECTION, + MIPS_SECREL, + MIPS_SECRELLO, + MIPS_SECRELHI, + MIPS_JMPADDR16, + MIPS_REFWORDNB, + MIPS_PAIR, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x00020000 => Type::I386_ABSOLUTE, + 0x00020001 => Type::I386_DIR16, + 0x00020002 => Type::I386_REL16, + 0x00020006 => Type::I386_DIR32, + 0x00020007 => Type::I386_DIR32NB, + 0x00020009 => Type::I386_SEG12, + 0x0002000a => Type::I386_SECTION, + 0x0002000b => Type::I386_SECREL, + 0x0002000c => Type::I386_TOKEN, + 0x0002000d => Type::I386_SECREL7, + 0x00020014 => Type::I386_REL32, + 0x00040000 => Type::AMD64_ABSOLUTE, + 0x00040001 => Type::AMD64_ADDR64, + 0x00040002 => Type::AMD64_ADDR32, + 0x00040003 => Type::AMD64_ADDR32NB, + 0x00040004 => Type::AMD64_REL32, + 0x00040005 => Type::AMD64_REL32_1, + 0x00040006 => Type::AMD64_REL32_2, + 0x00040007 => Type::AMD64_REL32_3, + 0x00040008 => Type::AMD64_REL32_4, + 0x00040009 => Type::AMD64_REL32_5, + 0x0004000a => Type::AMD64_SECTION, + 0x0004000b => Type::AMD64_SECREL, + 0x0004000c => Type::AMD64_SECREL7, + 0x0004000d => Type::AMD64_TOKEN, + 0x0004000e => Type::AMD64_SREL32, + 0x0004000f => Type::AMD64_PAIR, + 0x00040010 => Type::AMD64_SSPAN32, + 0x00080000 => Type::ARM_ABSOLUTE, + 0x00080001 => Type::ARM_ADDR32, + 0x00080002 => Type::ARM_ADDR32NB, + 0x00080003 => Type::ARM_BRANCH24, + 0x00080004 => Type::ARM_BRANCH11, + 0x00080005 => Type::ARM_TOKEN, + 0x00080008 => Type::ARM_BLX24, + 0x00080009 => Type::ARM_BLX11, + 0x0008000a => Type::ARM_REL32, + 0x0008000e => Type::ARM_SECTION, + 0x0008000f => Type::ARM_SECREL, + 0x00080010 => Type::ARM_MOV32A, + 0x00080011 => Type::ARM_MOV32T, + 0x00080012 => Type::ARM_BRANCH20T, + 0x00080014 => Type::ARM_BRANCH24T, + 0x00080015 => Type::ARM_BLX23T, + 0x00080016 => Type::ARM_PAIR, + 0x00100000 => Type::ARM64_ABSOLUTE, + 0x00100001 => Type::ARM64_ADDR32, + 0x00100002 => Type::ARM64_ADDR32NB, + 0x00100003 => Type::ARM64_BRANCH26, + 0x00100004 => Type::ARM64_PAGEBASE_REL21, + 0x00100005 => Type::ARM64_REL21, + 0x00100006 => Type::ARM64_PAGEOFFSET_12A, + 0x00100007 => Type::ARM64_PAGEOFFSET_12L, + 0x00100008 => Type::ARM64_SECREL, + 0x00100009 => Type::ARM64_SECREL_LOW12A, + 0x0010000a => Type::ARM64_SECREL_HIGH12A, + 0x0010000b => Type::ARM64_SECREL_LOW12L, + 0x0010000c => Type::ARM64_TOKEN, + 0x0010000d => Type::ARM64_SECTION, + 0x0010000e => Type::ARM64_ADDR64, + 0x0010000f => Type::ARM64_BRANCH19, + 0x00100010 => Type::ARM64_BRANCH14, + 0x00100011 => Type::ARM64_REL32, + 0x00200000 => Type::MIPS_ABSOLUTE, + 0x00200001 => Type::MIPS_REFHALF, + 0x00200002 => Type::MIPS_REFWORD, + 0x00200003 => Type::MIPS_JMPADDR, + 0x00200004 => Type::MIPS_REFHI, + 0x00200005 => Type::MIPS_REFLO, + 0x00200006 => Type::MIPS_GPREL, + 0x00200007 => Type::MIPS_LITERAL, + 0x0020000a => Type::MIPS_SECTION, + 0x0020000b => Type::MIPS_SECREL, + 0x0020000c => Type::MIPS_SECRELLO, + 0x0020000d => Type::MIPS_SECRELHI, + 0x00200010 => Type::MIPS_JMPADDR16, + 0x00200022 => Type::MIPS_REFWORDNB, + 0x00200025 => Type::MIPS_PAIR, + _ => Type::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Type) -> u32 { + match value { + Type::I386_ABSOLUTE => 0x00020000, + Type::I386_DIR16 => 0x00020001, + Type::I386_REL16 => 0x00020002, + Type::I386_DIR32 => 0x00020006, + Type::I386_DIR32NB => 0x00020007, + Type::I386_SEG12 => 0x00020009, + Type::I386_SECTION => 0x0002000a, + Type::I386_SECREL => 0x0002000b, + Type::I386_TOKEN => 0x0002000c, + Type::I386_SECREL7 => 0x0002000d, + Type::I386_REL32 => 0x00020014, + Type::AMD64_ABSOLUTE => 0x00040000, + Type::AMD64_ADDR64 => 0x00040001, + Type::AMD64_ADDR32 => 0x00040002, + Type::AMD64_ADDR32NB => 0x00040003, + Type::AMD64_REL32 => 0x00040004, + Type::AMD64_REL32_1 => 0x00040005, + Type::AMD64_REL32_2 => 0x00040006, + Type::AMD64_REL32_3 => 0x00040007, + Type::AMD64_REL32_4 => 0x00040008, + Type::AMD64_REL32_5 => 0x00040009, + Type::AMD64_SECTION => 0x0004000a, + Type::AMD64_SECREL => 0x0004000b, + Type::AMD64_SECREL7 => 0x0004000c, + Type::AMD64_TOKEN => 0x0004000d, + Type::AMD64_SREL32 => 0x0004000e, + Type::AMD64_PAIR => 0x0004000f, + Type::AMD64_SSPAN32 => 0x00040010, + Type::ARM_ABSOLUTE => 0x00080000, + Type::ARM_ADDR32 => 0x00080001, + Type::ARM_ADDR32NB => 0x00080002, + Type::ARM_BRANCH24 => 0x00080003, + Type::ARM_BRANCH11 => 0x00080004, + Type::ARM_TOKEN => 0x00080005, + Type::ARM_BLX24 => 0x00080008, + Type::ARM_BLX11 => 0x00080009, + Type::ARM_REL32 => 0x0008000a, + Type::ARM_SECTION => 0x0008000e, + Type::ARM_SECREL => 0x0008000f, + Type::ARM_MOV32A => 0x00080010, + Type::ARM_MOV32T => 0x00080011, + Type::ARM_BRANCH20T => 0x00080012, + Type::ARM_BRANCH24T => 0x00080014, + Type::ARM_BLX23T => 0x00080015, + Type::ARM_PAIR => 0x00080016, + Type::ARM64_ABSOLUTE => 0x00100000, + Type::ARM64_ADDR32 => 0x00100001, + Type::ARM64_ADDR32NB => 0x00100002, + Type::ARM64_BRANCH26 => 0x00100003, + Type::ARM64_PAGEBASE_REL21 => 0x00100004, + Type::ARM64_REL21 => 0x00100005, + Type::ARM64_PAGEOFFSET_12A => 0x00100006, + Type::ARM64_PAGEOFFSET_12L => 0x00100007, + Type::ARM64_SECREL => 0x00100008, + Type::ARM64_SECREL_LOW12A => 0x00100009, + Type::ARM64_SECREL_HIGH12A => 0x0010000a, + Type::ARM64_SECREL_LOW12L => 0x0010000b, + Type::ARM64_TOKEN => 0x0010000c, + Type::ARM64_SECTION => 0x0010000d, + Type::ARM64_ADDR64 => 0x0010000e, + Type::ARM64_BRANCH19 => 0x0010000f, + Type::ARM64_BRANCH14 => 0x00100010, + Type::ARM64_REL32 => 0x00100011, + Type::MIPS_ABSOLUTE => 0x00200000, + Type::MIPS_REFHALF => 0x00200001, + Type::MIPS_REFWORD => 0x00200002, + Type::MIPS_JMPADDR => 0x00200003, + Type::MIPS_REFHI => 0x00200004, + Type::MIPS_REFLO => 0x00200005, + Type::MIPS_GPREL => 0x00200006, + Type::MIPS_LITERAL => 0x00200007, + Type::MIPS_SECTION => 0x0020000a, + Type::MIPS_SECREL => 0x0020000b, + Type::MIPS_SECRELLO => 0x0020000c, + Type::MIPS_SECRELHI => 0x0020000d, + Type::MIPS_JMPADDR16 => 0x00200010, + Type::MIPS_REFWORDNB => 0x00200022, + Type::MIPS_PAIR => 0x00200025, + Type::UNKNOWN(value) => value, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/coff/section.rs b/vendor/lief/api/rust/crates/lief/src/coff/section.rs new file mode 100644 index 0000000..8fca938 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/section.rs @@ -0,0 +1,209 @@ +//! COFF section module + +use super::Relocation; +use super::Symbol; +use crate::coff; +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::declare_iterator; +use crate::generic; +use crate::pe; +use std::marker::PhantomData; +use std::pin::Pin; + +use lief_ffi as ffi; + +pub struct Section<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Binary>, +} + +impl FromFFI for Section<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Section<'_> { + /// Return the size of the data in the section. + pub fn sizeof_raw_data(&self) -> u32 { + self.ptr.sizeof_raw_data() + } + + /// Return the size of the data when mapped in memory (should be 0) + pub fn virtual_size(&self) -> u32 { + self.ptr.virtual_size() + } + + /// Offset to the section's content + pub fn pointerto_raw_data(&self) -> u32 { + self.ptr.pointerto_raw_data() + } + + /// Offset to the relocation table + pub fn pointerto_relocation(&self) -> u32 { + self.ptr.pointerto_relocation() + } + + /// The file pointer to the beginning of line-number entries for the section. + /// + /// This is set to zero if there are no COFF line numbers. + /// This value should be zero for an image because COFF debugging information + /// is deprecated and modern debug information relies on the PDB files. + pub fn pointerto_line_numbers(&self) -> u32 { + self.ptr.pointerto_line_numbers() + } + + /// Number of relocations. + /// + ///
+ /// If the number of relocations is greater than 0xFFFF (maximum value for 16-bits integer), + /// then the number of relocations is stored in the virtual address attribute. + ///
+ pub fn numberof_relocations(&self) -> u16 { + self.ptr.numberof_relocations() + } + + /// Number of line number entries (if any). + pub fn numberof_line_numbers(&self) -> u16 { + self.ptr.numberof_line_numbers() + } + + /// Characteristics of the section: it provides information about + /// the permissions of the section when mapped. It can also provide + /// information about the *purpose* of the section (contain code, BSS-like, ...) + pub fn characteristics(&self) -> pe::section::Characteristics { + pe::section::Characteristics::from(self.ptr.characteristics()) + } + + /// True if the section can be discarded as needed. + /// + /// This is typically the case for debug-related sections + pub fn is_discardable(&self) -> bool { + self.ptr.is_discardable() + } + + /// Whether there is a large number of relocations whose number need to be stored in the + /// virtual address attribute + pub fn has_extended_relocations(&self) -> bool { + self.ptr.has_extended_relocations() + } + + /// Iterator over the relocations associated with this section + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// Iterator over the symbols associated with this section + pub fn symbols(&self) -> Symbols<'_> { + Symbols::new(self.ptr.symbols()) + } + + /// Return comdat information (only if the section has the + /// [`crate::pe::section::Characteristics::LNK_COMDAT`] characteristic) + pub fn comdat_info(&self) -> Option> { + into_optional(self.ptr.comdat_info()) + } + + /// Return the COFF string associated with the section's name (or a None) + /// + /// This coff string is usually present for long section names whose length + /// does not fit in the 8 bytes allocated by the COFF format. + pub fn coff_string(&self) -> Option> { + into_optional(self.ptr.coff_string()) + } +} + +impl generic::Section for Section<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSection + as *mut ffi::AbstractSection) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Section<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Section; + f.debug_struct("Section") + .field("base", &base) + .field("sizeof_raw_data", &self.sizeof_raw_data()) + .field("virtual_size", &self.virtual_size()) + .field("pointerto_raw_data", &self.pointerto_raw_data()) + .field("pointerto_relocation", &self.pointerto_relocation()) + .field("pointerto_line_numbers", &self.pointerto_line_numbers()) + .field("numberof_relocations", &self.numberof_relocations()) + .field("numberof_line_numbers", &self.numberof_line_numbers()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +impl std::fmt::Display for Section<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +/// This structure wraps comdat information which is composed of the symbol +/// associated with the comdat section and its selection flag +pub struct ComdatInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Binary>, +} + +impl ComdatInfo<'_> { + pub fn symbol(&self) -> Option> { + into_optional(self.ptr.symbol()) + } + + pub fn kind(&self) -> coff::symbol::ComdatSelection { + coff::symbol::ComdatSelection::from(self.ptr.kind()) + } +} + +impl FromFFI for ComdatInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for ComdatInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("ComdatInfo") + .field("symbol", &self.symbol()) + .field("kind", &self.kind()) + .finish() + } +} + +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::COFF_Relocation, + ffi::COFF_Section, + ffi::COFF_Section_it_relocations +); + +declare_iterator!( + Symbols, + Symbol<'a>, + ffi::COFF_Symbol, + ffi::COFF_Section, + ffi::COFF_Section_it_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/coff/string.rs b/vendor/lief/api/rust/crates/lief/src/coff/string.rs new file mode 100644 index 0000000..53b706c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/string.rs @@ -0,0 +1,37 @@ +use crate::common::FromFFI; +use std::marker::PhantomData; + +use lief_ffi as ffi; + +pub struct String<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl<'a> FromFFI for String<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// This class represents a string located in the COFF string table. +/// +/// Some of these strings can be used for section names that are greater than 8 +/// bytes. See: [`crate::pe::Section::coff_string`] +/// +/// Reference: +impl String<'_> { + /// The actual string + pub fn str(&self) -> std::string::String { + self.ptr.str().to_string() + } + + /// The offset of this string the in the COFF string table. + /// This offset includes the first 4-bytes that holds the table size + pub fn offset(&self) -> u32 { + self.ptr.offset() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/coff/symbol.rs b/vendor/lief/api/rust/crates/lief/src/coff/symbol.rs new file mode 100644 index 0000000..3ef4179 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/coff/symbol.rs @@ -0,0 +1,825 @@ +use lief_ffi as ffi; + +use std::marker::PhantomData; +use std::pin::Pin; + +use crate::common::{FromFFI, into_optional}; +use crate::to_slice; +use crate::{declare_iterator, generic}; + +use super::Section; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum StorageClass { + INVALID, + END_OF_FUNCTION, + NONE, + AUTOMATIC, + EXTERNAL, + STATIC, + REGISTER, + EXTERNAL_DEF, + LABEL, + UNDEFINED_LABEL, + MEMBER_OF_STRUCT, + ARGUMENT, + STRUCT_TAG, + MEMBER_OF_UNION, + UNION_TAG, + TYPE_DEFINITION, + UNDEFINED_STATIC, + ENUM_TAG, + MEMBER_OF_ENUM, + REGISTER_PARAM, + BIT_FIELD, + BLOCK, + FUNCTION, + END_OF_STRUCT, + FILE, + SECTION, + WEAK_EXTERNAL, + CLR_TOKEN, + UNKNOWN(u32), +} + +impl From for StorageClass { + fn from(value: u32) -> Self { + match value { + 0x000000ff => StorageClass::INVALID, + 0xffffffff => StorageClass::END_OF_FUNCTION, + 0x00000000 => StorageClass::NONE, + 0x00000001 => StorageClass::AUTOMATIC, + 0x00000002 => StorageClass::EXTERNAL, + 0x00000003 => StorageClass::STATIC, + 0x00000004 => StorageClass::REGISTER, + 0x00000005 => StorageClass::EXTERNAL_DEF, + 0x00000006 => StorageClass::LABEL, + 0x00000007 => StorageClass::UNDEFINED_LABEL, + 0x00000008 => StorageClass::MEMBER_OF_STRUCT, + 0x00000009 => StorageClass::ARGUMENT, + 0x0000000a => StorageClass::STRUCT_TAG, + 0x0000000b => StorageClass::MEMBER_OF_UNION, + 0x0000000c => StorageClass::UNION_TAG, + 0x0000000d => StorageClass::TYPE_DEFINITION, + 0x0000000e => StorageClass::UNDEFINED_STATIC, + 0x0000000f => StorageClass::ENUM_TAG, + 0x00000010 => StorageClass::MEMBER_OF_ENUM, + 0x00000011 => StorageClass::REGISTER_PARAM, + 0x00000012 => StorageClass::BIT_FIELD, + 0x00000064 => StorageClass::BLOCK, + 0x00000065 => StorageClass::FUNCTION, + 0x00000066 => StorageClass::END_OF_STRUCT, + 0x00000067 => StorageClass::FILE, + 0x00000068 => StorageClass::SECTION, + 0x00000069 => StorageClass::WEAK_EXTERNAL, + 0x0000006b => StorageClass::CLR_TOKEN, + _ => StorageClass::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: StorageClass) -> u32 { + match value { + StorageClass::INVALID => 0x000000ff, + StorageClass::END_OF_FUNCTION => 0xffffffff, + StorageClass::NONE => 0x00000000, + StorageClass::AUTOMATIC => 0x00000001, + StorageClass::EXTERNAL => 0x00000002, + StorageClass::STATIC => 0x00000003, + StorageClass::REGISTER => 0x00000004, + StorageClass::EXTERNAL_DEF => 0x00000005, + StorageClass::LABEL => 0x00000006, + StorageClass::UNDEFINED_LABEL => 0x00000007, + StorageClass::MEMBER_OF_STRUCT => 0x00000008, + StorageClass::ARGUMENT => 0x00000009, + StorageClass::STRUCT_TAG => 0x0000000a, + StorageClass::MEMBER_OF_UNION => 0x0000000b, + StorageClass::UNION_TAG => 0x0000000c, + StorageClass::TYPE_DEFINITION => 0x0000000d, + StorageClass::UNDEFINED_STATIC => 0x0000000e, + StorageClass::ENUM_TAG => 0x0000000f, + StorageClass::MEMBER_OF_ENUM => 0x00000010, + StorageClass::REGISTER_PARAM => 0x00000011, + StorageClass::BIT_FIELD => 0x00000012, + StorageClass::BLOCK => 0x00000064, + StorageClass::FUNCTION => 0x00000065, + StorageClass::END_OF_STRUCT => 0x00000066, + StorageClass::FILE => 0x00000067, + StorageClass::SECTION => 0x00000068, + StorageClass::WEAK_EXTERNAL => 0x00000069, + StorageClass::CLR_TOKEN => 0x0000006b, + StorageClass::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum BaseType { + TY_NULL, + TY_VOID, + TY_CHAR, + TY_SHORT, + TY_INT, + TY_LONG, + TY_FLOAT, + TY_DOUBLE, + TY_STRUCT, + TY_UNION, + TY_ENUM, + TY_MOE, + TY_BYTE, + TY_WORD, + TY_UINT, + TY_DWORD, + UNKNOWN(u32), +} + +impl From for BaseType { + fn from(value: u32) -> Self { + match value { + 0x00000000 => BaseType::TY_NULL, + 0x00000001 => BaseType::TY_VOID, + 0x00000002 => BaseType::TY_CHAR, + 0x00000003 => BaseType::TY_SHORT, + 0x00000004 => BaseType::TY_INT, + 0x00000005 => BaseType::TY_LONG, + 0x00000006 => BaseType::TY_FLOAT, + 0x00000007 => BaseType::TY_DOUBLE, + 0x00000008 => BaseType::TY_STRUCT, + 0x00000009 => BaseType::TY_UNION, + 0x0000000a => BaseType::TY_ENUM, + 0x0000000b => BaseType::TY_MOE, + 0x0000000c => BaseType::TY_BYTE, + 0x0000000d => BaseType::TY_WORD, + 0x0000000e => BaseType::TY_UINT, + 0x0000000f => BaseType::TY_DWORD, + _ => BaseType::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: BaseType) -> u32 { + match value { + BaseType::TY_NULL => 0x00000000, + BaseType::TY_VOID => 0x00000001, + BaseType::TY_CHAR => 0x00000002, + BaseType::TY_SHORT => 0x00000003, + BaseType::TY_INT => 0x00000004, + BaseType::TY_LONG => 0x00000005, + BaseType::TY_FLOAT => 0x00000006, + BaseType::TY_DOUBLE => 0x00000007, + BaseType::TY_STRUCT => 0x00000008, + BaseType::TY_UNION => 0x00000009, + BaseType::TY_ENUM => 0x0000000a, + BaseType::TY_MOE => 0x0000000b, + BaseType::TY_BYTE => 0x0000000c, + BaseType::TY_WORD => 0x0000000d, + BaseType::TY_UINT => 0x0000000e, + BaseType::TY_DWORD => 0x0000000f, + BaseType::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum ComplexType { + TY_NULL, + TY_POINTER, + TY_FUNCTION, + TY_ARRAY, + UNKNOWN(u32), +} + +impl From for ComplexType { + fn from(value: u32) -> Self { + match value { + 0x00000000 => ComplexType::TY_NULL, + 0x00000001 => ComplexType::TY_POINTER, + 0x00000002 => ComplexType::TY_FUNCTION, + 0x00000003 => ComplexType::TY_ARRAY, + _ => ComplexType::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: ComplexType) -> u32 { + match value { + ComplexType::TY_NULL => 0x00000000, + ComplexType::TY_POINTER => 0x00000001, + ComplexType::TY_FUNCTION => 0x00000002, + ComplexType::TY_ARRAY => 0x00000003, + ComplexType::UNKNOWN(value) => value, + } + } +} + +/// Structure that represents a COFF symbol. +/// +/// **Warning:** The [`crate::generic::Symbol::value`] should be interpreted in perspective of +/// the [`Symbol::storage_class`]. +/// +/// Reference: +pub struct Symbol<'a> { + pub(crate) ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Symbol<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for Symbol<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("Symbol") + .field("base", &base) + .field("storage_class", &self.storage_class()) + .field("base_type", &self.base_type()) + .field("complex_type", &self.complex_type()) + .field("section_idx", &self.section_idx()) + .finish() + } +} + +impl std::fmt::Display for Symbol<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl Symbol<'_> { + /// Auxiliary symbols associated with this symbol. + pub fn auxiliary_symbols(&self) -> ItAuxiliarySymbols<'_> { + ItAuxiliarySymbols::new(self.ptr.auxiliary_symbols()) + } + + /// Storage class of the symbol which indicates what kind of definition a + /// symbol represents. + pub fn storage_class(&self) -> StorageClass { + StorageClass::from(self.ptr.storage_class()) + } + + /// The simple (base) data type + pub fn base_type(&self) -> BaseType { + BaseType::from(self.ptr.base_type()) + } + + /// The complex type (if any) + pub fn complex_type(&self) -> ComplexType { + ComplexType::from(self.ptr.complex_type()) + } + + /// The signed integer that identifies the section, using a one-based index + /// into the section table. Some values have special meaning: + /// + /// * 0: The symbol record is not yet assigned a section. A value of zero + /// indicates that a reference to an external symbol is defined elsewhere. + /// A value of non-zero is a common symbol with a size that is specified + /// by the value. + /// * -1: The symbol has an absolute (non-relocatable) value and is not an + /// address. + /// * -2: The symbol provides general type or debugging information but does + /// not correspond to a section. Microsoft tools use this setting along + /// with `.file` records + pub fn section_idx(&self) -> i16 { + self.ptr.section_idx() + } + + /// Section associated with this symbol (if any) + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } + + pub fn is_external(&self) -> bool { + self.ptr.is_external() + } + + pub fn is_weak_external(&self) -> bool { + self.ptr.is_weak_external() + } + + pub fn is_undefined(&self) -> bool { + self.ptr.is_undefined() + } + + pub fn is_function_line_info(&self) -> bool { + self.ptr.is_function_line_info() + } + + pub fn is_absolute(&self) -> bool { + self.ptr.is_absolute() + } + + pub fn is_file_record(&self) -> bool { + self.ptr.is_file_record() + } + + pub fn is_function(&self) -> bool { + self.ptr.is_function() + } + + /// Demangled representation of the symbol or an empty string if it can't be demangled + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } +} + +impl generic::Symbol for Symbol<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +/// Class that represents an auxiliary symbol. +/// +/// An auxiliary symbol has the same size as a regular [`Symbol`] (18 bytes) but its content +/// depends on the parent symbol. +#[derive(Debug)] +pub enum AuxiliarySymbols<'a> { + /// Auxiliary Format 1 from the PE-COFF documentation + FunctionDefinition(AuxiliaryFunctionDefinition<'a>), + /// Auxiliary Format 2: .bf and .ef Symbols from the PE-COFF documentation + BfAndEf(AuxiliaryBfAndEf<'a>), + /// Auxiliary Format 3: Weak Externals from the PE-COFF documentation + WeakExternal(AuxiliaryWeakExternal<'a>), + /// Auxiliary Format 4: Files from the PE-COFF documentation + File(AuxiliaryFile<'a>), + /// Auxiliary Format 5: Section Definitions from the PE-COFF documentation + SectionDefinition(AuxiliarySectionDefinition<'a>), + CLRToken(AuxiliaryCLRToken<'a>), + Unknown(AuxiliarySymbol<'a>), +} + +impl FromFFI for AuxiliarySymbols<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let aux_ref = ffi_entry.as_ref().unwrap(); + if ffi::COFF_AuxiliaryFile::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::File(AuxiliaryFile::from_ffi(raw)) + } else if ffi::COFF_AuxiliarybfAndefSymbol::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::BfAndEf(AuxiliaryBfAndEf::from_ffi(raw)) + } else if ffi::COFF_AuxiliaryCLRToken::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::CLRToken(AuxiliaryCLRToken::from_ffi(raw)) + } else if ffi::COFF_AuxiliaryFunctionDefinition::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::FunctionDefinition(AuxiliaryFunctionDefinition::from_ffi(raw)) + } else if ffi::COFF_AuxiliaryWeakExternal::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::WeakExternal(AuxiliaryWeakExternal::from_ffi(raw)) + } else if ffi::COFF_AuxiliarySectionDefinition::classof(aux_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + AuxiliarySymbols::SectionDefinition(AuxiliarySectionDefinition::from_ffi(raw)) + } else { + AuxiliarySymbols::Unknown(AuxiliarySymbol::from_ffi(ffi_entry)) + } + } + } +} + +/// This auxiliary symbol represents a filename (auxiliary format 4) +/// +/// The [`crate::generic::Symbol::name`] itself should start with `.file`, and this auxiliary record +/// gives the name of a source-code file. +/// +/// Reference: +pub struct AuxiliaryFile<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl std::fmt::Debug for AuxiliaryFile<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliaryFile") + .field("filename", &self.filename()) + .finish() + } +} + +impl FromFFI for AuxiliaryFile<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AuxiliaryFile<'_> { + /// The associated filename + pub fn filename(&self) -> String { + self.ptr.filename().to_string() + } +} + +pub struct AuxiliaryBfAndEf<'a> { + #[allow(dead_code)] + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl std::fmt::Debug for AuxiliaryBfAndEf<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliaryBfAndEf").finish() + } +} + +impl FromFFI for AuxiliaryBfAndEf<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +pub struct AuxiliaryCLRToken<'a> { + #[allow(dead_code)] + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl AuxiliaryCLRToken<'_> { + /// `IMAGE_AUX_SYMBOL_TYPE` which should be `IMAGE_AUX_SYMBOL_TYPE_TOKEN_DEF` (1) + pub fn aux_type(&self) -> u8 { + self.ptr.aux_type() + } + + /// Reserved value (should be 0) + pub fn reserved(&self) -> u8 { + self.ptr.reserved() + } + + /// Index in the symbol table + pub fn symbol_idx(&self) -> u32 { + self.ptr.symbol_idx() + } + + /// Symbol referenced by [`AuxiliaryCLRToken::symbol_idx`] (if resolved) + pub fn symbol(&self) -> Option> { + into_optional(self.ptr.symbol()) + } + + /// Reserved (padding) values. Should be 0 + pub fn rgb_reserved(&self) -> &[u8] { + to_slice!(self.ptr.rgb_reserved()); + } +} + +impl std::fmt::Debug for AuxiliaryCLRToken<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliaryCLRToken") + .field("aux_type", &self.aux_type()) + .field("reserved", &self.reserved()) + .field("symbol_idx", &self.symbol_idx()) + .finish() + } +} + +impl FromFFI for AuxiliaryCLRToken<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// This auxiliary symbols marks the beginning of a function definition. +/// +/// Reference: +pub struct AuxiliaryFunctionDefinition<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl FromFFI for AuxiliaryFunctionDefinition<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AuxiliaryFunctionDefinition<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliaryFunctionDefinition") + .field("tag_index", &self.tag_index()) + .field("total_size", &self.total_size()) + .field("ptr_to_line_number", &self.ptr_to_line_number()) + .field("ptr_to_next_func", &self.ptr_to_next_func()) + .field("padding", &self.padding()) + .finish() + } +} + +impl AuxiliaryFunctionDefinition<'_> { + /// The symbol-table index of the corresponding `.bf` (begin function) + /// symbol record. + pub fn tag_index(&self) -> u32 { + self.ptr.tag_index() + } + + /// The size of the executable code for the function itself. + /// + /// If the function is in its own section, the `SizeOfRawData` in the section + /// header is greater or equal to this field, depending on alignment considerations. + pub fn total_size(&self) -> u32 { + self.ptr.total_size() + } + + /// The file offset of the first COFF line-number entry for the function, + /// or zero if none exists (deprecated) + pub fn ptr_to_line_number(&self) -> u32 { + self.ptr.ptr_to_line_number() + } + + /// The symbol-table index of the record for the next function. If the function + /// is the last in the symbol table, this field is set to zero. + pub fn ptr_to_next_func(&self) -> u32 { + self.ptr.ptr_to_next_func() + } + + /// Padding value (should be 0) + pub fn padding(&self) -> u16 { + self.ptr.padding() + } +} + +/// This auxiliary symbol exposes information about the associated section. +/// +/// It **duplicates** some information that are provided in the section header +pub struct AuxiliarySectionDefinition<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl FromFFI for AuxiliarySectionDefinition<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AuxiliarySectionDefinition<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliarySectionDefinition") + .field("length", &self.length()) + .field("nb_relocs", &self.nb_relocs()) + .field("nb_line_numbers", &self.nb_line_numbers()) + .field("checksum", &self.checksum()) + .field("section_idx", &self.section_idx()) + .field("selection", &self.selection()) + .finish() + } +} + +impl AuxiliarySectionDefinition<'_> { + /// The size of section data. The same as `SizeOfRawData` in the section header. + pub fn length(&self) -> u32 { + self.ptr.length() + } + + /// The number of relocation entries for the section. + pub fn nb_relocs(&self) -> u16 { + self.ptr.nb_relocs() + } + + /// The number of line-number entries for the section. + pub fn nb_line_numbers(&self) -> u16 { + self.ptr.nb_line_numbers() + } + + /// The checksum for communal data. It is applicable if the `IMAGE_SCN_LNK_COMDAT` flag is set + /// in the section header. + pub fn checksum(&self) -> u32 { + self.ptr.checksum() + } + + /// One-based index into the section table for the associated section. + /// This is used when the COMDAT selection setting is 5. + pub fn section_idx(&self) -> u32 { + self.ptr.section_idx() + } + + /// The COMDAT selection number. This is applicable if the section is a + /// COMDAT section. + pub fn selection(&self) -> ComdatSelection { + ComdatSelection::from(self.ptr.selection()) + } + + /// Reserved value (should be 0) + pub fn reserved(&self) -> u8 { + self.ptr.reserved() + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum ComdatSelection { + NONE, + NODUPLICATES, + ANY, + SAME_SIZE, + EXACT_MATCH, + ASSOCIATIVE, + LARGEST, + UNKNOWN(u8), +} + +impl From for ComdatSelection { + fn from(value: u8) -> Self { + match value { + 0x00000000 => ComdatSelection::NONE, + 0x00000001 => ComdatSelection::NODUPLICATES, + 0x00000002 => ComdatSelection::ANY, + 0x00000003 => ComdatSelection::SAME_SIZE, + 0x00000004 => ComdatSelection::EXACT_MATCH, + 0x00000005 => ComdatSelection::ASSOCIATIVE, + 0x00000006 => ComdatSelection::LARGEST, + _ => ComdatSelection::UNKNOWN(value), + } + } +} +impl From for u8 { + fn from(value: ComdatSelection) -> u8 { + match value { + ComdatSelection::NONE => 0x00000000, + ComdatSelection::NODUPLICATES => 0x00000001, + ComdatSelection::ANY => 0x00000002, + ComdatSelection::SAME_SIZE => 0x00000003, + ComdatSelection::EXACT_MATCH => 0x00000004, + ComdatSelection::ASSOCIATIVE => 0x00000005, + ComdatSelection::LARGEST => 0x00000006, + ComdatSelection::UNKNOWN(value) => value, + } + } +} + +/// "Weak externals" are a mechanism for object files that allows flexibility at +/// link time. A module can contain an unresolved external symbol (`sym1`), but +/// it can also include an auxiliary record that indicates that if `sym1` is not +/// present at link time, another external symbol (`sym2`) is used to resolve +/// references instead. +/// +/// If a definition of `sym1` is linked, then an external reference to the +/// symbol is resolved normally. If a definition of `sym1` is not linked, then all +/// references to the weak external for `sym1` refer to `sym2` instead. The external +/// symbol, `sym2`, must always be linked; typically, it is defined in the module +/// that contains the weak reference to `sym1`. +/// +/// Reference: +pub struct AuxiliaryWeakExternal<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Characteristics { + SEARCH_NOLIBRARY, + SEARCH_LIBRARY, + SEARCH_ALIAS, + ANTI_DEPENDENCY, + UNKNOWN(u32), +} + +impl From for Characteristics { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Characteristics::SEARCH_NOLIBRARY, + 0x00000002 => Characteristics::SEARCH_LIBRARY, + 0x00000003 => Characteristics::SEARCH_ALIAS, + 0x00000004 => Characteristics::ANTI_DEPENDENCY, + _ => Characteristics::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Characteristics) -> u32 { + match value { + Characteristics::SEARCH_NOLIBRARY => 0x00000001, + Characteristics::SEARCH_LIBRARY => 0x00000002, + Characteristics::SEARCH_ALIAS => 0x00000003, + Characteristics::ANTI_DEPENDENCY => 0x00000004, + Characteristics::UNKNOWN(value) => value, + } + } +} + +impl FromFFI for AuxiliaryWeakExternal<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AuxiliaryWeakExternal<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliaryWeakExternal") + .field("sym_idx", &self.sym_idx()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +impl AuxiliaryWeakExternal<'_> { + /// The symbol-table index of `sym2`, the symbol to be linked if `sym1` is not + /// found. + pub fn sym_idx(&self) -> u32 { + self.ptr.sym_idx() + } + + pub fn characteristics(&self) -> Characteristics { + Characteristics::from(self.ptr.characteristics()) + } + + pub fn padding(&self) -> &[u8] { + to_slice!(self.ptr.padding()); + } +} + +pub struct AuxiliarySymbol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::COFF_Symbol>, +} + +impl FromFFI for AuxiliarySymbol<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AuxiliarySymbol<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AuxiliarySymbol").finish() + } +} + +impl AuxiliarySymbol<'_> { + /// Return the raw representation of this symbol + pub fn payload(&self) -> &[u8] { + to_slice!(self.ptr.payload()); + } +} + +declare_iterator!( + ItAuxiliarySymbols, + AuxiliarySymbols<'a>, + ffi::COFF_AuxiliarySymbol, + ffi::COFF_Symbol, + ffi::COFF_Symbol_it_auxiliary_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/common.rs b/vendor/lief/api/rust/crates/lief/src/common.rs new file mode 100644 index 0000000..5695278 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/common.rs @@ -0,0 +1,325 @@ +use cxx::memory::UniquePtrTarget; +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::Range; + +#[doc(hidden)] +pub trait FromFFI { + fn from_ffi(ptr: cxx::UniquePtr) -> Self; +} + +#[doc(hidden)] +pub trait AsFFI { + fn as_ffi(&self) -> &U; + + #[allow(dead_code)] + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut U>; +} + +#[doc(hidden)] +pub fn into_optional, U: UniquePtrTarget>(raw_ffi: cxx::UniquePtr) -> Option { + if raw_ffi.is_null() { + None + } else { + Some(T::from_ffi(raw_ffi)) + } +} + +#[doc(hidden)] +pub fn into_ranges(raw_ffi: cxx::UniquePtr>) -> Vec { + let cxx_vec = raw_ffi.as_ref().unwrap(); + if cxx_vec.is_empty() { + return Vec::new(); + } + + let mut rust_range: Vec = Vec::with_capacity(cxx_vec.len()); + + for ffi_range in cxx_vec { + rust_range.push(Range::from_ffi(ffi_range)); + } + + rust_range +} + +pub struct Iterator<'a, Parent: UniquePtrTarget, It: UniquePtrTarget> { + #[doc(hidden)] + pub it: cxx::UniquePtr, + _owner: PhantomData<&'a Parent>, +} + +impl<'a, Parent: UniquePtrTarget, It: UniquePtrTarget> Iterator<'a, Parent, It> { + #[doc(hidden)] + pub fn new(it: cxx::UniquePtr) -> Self { + Self { + it, + _owner: PhantomData, + } + } +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_iterator_conv { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty, $conv: expr) => { + pub type $name<'a> = $crate::common::Iterator<'a, $parent, $ffi_iterator>; + impl<'a> Iterator for $name<'a> { + type Item = $from; + fn next(&mut self) -> Option { + let next = self.it.as_mut().unwrap().next(); + if next.is_null() { + None + } else { + Some($conv(next)) + } + } + } + impl<'a> ExactSizeIterator for $name<'a> { + fn len(&self) -> usize { + self.it.as_ref().unwrap().size().try_into().unwrap() + } + } + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_iterator { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty) => { + $crate::declare_iterator_conv!($name, $from, $ffi, $parent, $ffi_iterator, |n| { + Self::Item::from_ffi(n) + }); + }; +} + +pub struct ForwardIterator<'a, Parent: UniquePtrTarget, It: UniquePtrTarget> { + #[doc(hidden)] + pub it: cxx::UniquePtr, + _owner: PhantomData<&'a Parent>, +} + +impl<'a, Parent: UniquePtrTarget, It: UniquePtrTarget> ForwardIterator<'a, Parent, It> { + #[doc(hidden)] + pub fn new(it: cxx::UniquePtr) -> Self { + Self { + it, + _owner: PhantomData, + } + } +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_fwd_iterator_conv { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty, $conv: expr) => { + pub type $name<'a> = $crate::common::ForwardIterator<'a, $parent, $ffi_iterator>; + impl<'a> Iterator for $name<'a> { + type Item = $from; + fn next(&mut self) -> Option { + let next = self.it.as_mut().unwrap().next(); + if next.is_null() { + None + } else { + Some($conv(next)) + } + } + + fn size_hint(&self) -> (usize, Option) { + let hint = self.it.as_ref().unwrap().size().try_into().unwrap(); + (hint, Some(hint)) + } + } + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_fwd_iterator { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty) => { + $crate::declare_fwd_iterator_conv!($name, $from, $ffi, $parent, $ffi_iterator, |n| { + Self::Item::from_ffi(n) + }); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_lazy_iterator_conv { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty, $conv: expr) => { + pub type $name<'a> = $crate::common::ForwardIterator<'a, $parent, $ffi_iterator>; + impl<'a> Iterator for $name<'a> { + type Item = $from; + fn next(&mut self) -> Option { + let next = self.it.as_mut().unwrap().next(); + if next.is_null() { + None + } else { + Some($conv(next)) + } + } + } + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_lazy_iterator { + ($name:ident, $from:ty, $ffi:ty, $parent:ty, $ffi_iterator:ty) => { + $crate::declare_lazy_iterator_conv!($name, $from, $ffi, $parent, $ffi_iterator, |n| { + Self::Item::from_ffi(n) + }); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_slice { + ($e:expr) => { + let content_ptr = $e; + unsafe { + if content_ptr.size > 0 { + return std::slice::from_raw_parts_mut(content_ptr.ptr, content_ptr.size as usize); + } + return &[]; + } + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! __to_result { + ($func: expr, $self: expr, $conv: expr $(, $args:tt)*) => { + let mut err: u32 = 0; + + let value = $func($self, $($args,)* std::pin::Pin::new(&mut err)); + if err > 0 { + return Err($crate::Error::from(err)); + } + return Ok($conv(value)); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_result { + ($func: expr, $self: expr $(, $args:tt)*) => { + $crate::__to_result!($func, &$self.ptr, |x| x $(, $args)*) + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_conv_result { + ($func: expr, $self: expr, $conv: expr $(, $args:tt)*) => { + $crate::__to_result!($func, $self, $conv $(, $args)*) + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! __to_opt { + ($func: expr, $self: expr, $conv: expr $(, $args:tt)*) => { + let mut _is_set: u32 = 0; + + let value = $func(&$self, $($args,)* std::pin::Pin::new(&mut _is_set)); + if _is_set == 0 { + return None; + } + return Some($conv(value.into())); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_opt { + ($func: expr, $self: expr $(, $args:tt)*) => { + $crate::__to_opt!($func, $self.ptr, |x| x $(, $args)*) + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_conv_opt { + ($func: expr, $self: expr, $conv: expr $(, $args:tt)*) => { + $crate::__to_opt!($func, $self.ptr, $conv $(, $args)*) + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_opt_trait { + ($func: expr, $self: expr $(, $args:tt)*) => { + $crate::__to_opt!($func, $self, |x| x $(, $args)*) + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_opt_trait_conv { + ($func: expr, $self: expr, $conv: expr $(, $args:tt)*) => { + $crate::__to_opt!($func, $self, $conv $(, $args)*) + }; +} + +pub struct StandaloneForwardIterator { + #[doc(hidden)] + pub it: cxx::UniquePtr, +} + +impl StandaloneForwardIterator { + #[doc(hidden)] + pub fn new(it: cxx::UniquePtr) -> Self { + Self { it } + } +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_standalone_fwd_iterator { + ($name:ident, $from:ty, $ffi:ty, $ffi_iterator:ty) => { + $crate::declare_standalone_fwd_iterator_conv!($name, $from, $ffi, $ffi_iterator, |n| { + Self::Item::from_ffi(n) + }); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! declare_standalone_fwd_iterator_conv { + ($name:ident, $from:ty, $ffi:ty, $ffi_iterator:ty, $conv: expr) => { + pub type $name = $crate::common::StandaloneForwardIterator<$ffi_iterator>; + impl Iterator for $name { + type Item = $from; + fn next(&mut self) -> Option { + let next = self.it.as_mut().unwrap().next(); + if next.is_null() { + None + } else { + Some($conv(next)) + } + } + } + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! __to_ok_result { + ($func: expr $(, $args:expr)*) => { + let mut err: u32 = 0; + + $func($($args,)* std::pin::Pin::new(&mut err)); + if err > 0 { + return Err($crate::Error::from(err)); + } + return Ok(()); + }; +} + +#[doc(hidden)] +#[macro_export] +macro_rules! to_ok_result { + ($func: expr $(, $args:expr)*) => { + $crate::__to_ok_result!($func $(, $args)*) + }; +} diff --git a/vendor/lief/api/rust/crates/lief/src/debug_info.rs b/vendor/lief/api/rust/crates/lief/src/debug_info.rs new file mode 100644 index 0000000..aaf1226 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/debug_info.rs @@ -0,0 +1,38 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf; +use crate::pdb; + +/// This enum wraps either a PDB or a DWARF debug info +pub enum DebugInfo<'a> { + Pdb(pdb::DebugInfo<'a>), + Dwarf(dwarf::DebugInfo<'a>), +} + +impl FromFFI for DebugInfo<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + unsafe { + let info_ref = info.as_ref().unwrap(); + + if ffi::PDB_DebugInfo::classof(info_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(info) + }; + return DebugInfo::Pdb(pdb::DebugInfo::from_ffi(raw)); + } + + if !ffi::DWARF_DebugInfo::classof(info_ref) { + panic!("Expecting a DWARF debug info"); + } + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(info) + }; + DebugInfo::Dwarf(dwarf::DebugInfo::from_ffi(raw)) + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/debug_location.rs b/vendor/lief/api/rust/crates/lief/src/debug_location.rs new file mode 100644 index 0000000..0ad1e12 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/debug_location.rs @@ -0,0 +1,22 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +/// This structure represents a location in the different debug formats (DWARF/PDB) +pub struct DebugLocation { + /// Line number + pub line: u64, + + /// Filename or filepath + pub file: String, +} + +impl FromFFI for DebugLocation { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + DebugLocation { + line: ptr.line(), + file: ptr.file().to_string(), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/decl_opt.rs b/vendor/lief/api/rust/crates/lief/src/decl_opt.rs new file mode 100644 index 0000000..888c8e6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/decl_opt.rs @@ -0,0 +1,73 @@ +use lief_ffi as ffi; + +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +/// Configuration options for generated code from debug info. +/// +/// This structure configures how the debug information (DWARF/PDB) translated +/// into an AST is generated. +pub struct DeclOpt { + pub indentation: u32, + + /// Prefer C++ syntax over C syntax. + /// + /// If true, the output will use C++ features (e.g. `bool` keyword) + pub is_cpp: bool, + + /// Enable extended comments and annotations. + /// + /// If true, the generated code will include comments containing low-level + /// details such as memory addresses, offsets, type sizes, and original + /// source locations. + pub show_extended_annotations: bool, + + /// Include full type definitions. + /// + /// If true, the output will contain the full definition of types (structs, + /// enums, unions). + pub include_types: bool, + + /// Emit a function body listing its local / stack variables + pub include_locals: bool, + + /// Resolve type aliases (sugar). + /// + /// If true, typedef and type aliases are replaced by their underlying + /// canonical types (e.g., `uint32_t` might become `unsigned int`). + pub desugar: bool, + + /// Show the relative offset of each field/attribute in structures. + /// + /// If true, every member of a structure is prefixed with its byte offset (e.g. `/* 0x04 */`). + pub show_field_offsets: bool, +} + +impl Default for DeclOpt { + fn default() -> DeclOpt { + DeclOpt { + indentation: 2, + is_cpp: false, + show_extended_annotations: true, + include_types: false, + include_locals: false, + desugar: true, + show_field_offsets: false, + } + } +} + +impl DeclOpt { + #[doc(hidden)] + pub fn to_ffi(&self) -> cxx::UniquePtr { + let mut ptr = ffi::LIEF_DeclOpt::create(); + ptr.pin_mut().set_indentation(self.indentation); + ptr.pin_mut().set_is_cpp(self.is_cpp); + ptr.pin_mut() + .set_show_extended_annotations(self.show_extended_annotations); + ptr.pin_mut().set_include_types(self.include_types); + ptr.pin_mut().set_include_locals(self.include_locals); + ptr.pin_mut().set_desugar(self.desugar); + ptr.pin_mut() + .set_show_field_offsets(self.show_field_offsets); + ptr + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc.rs b/vendor/lief/api/rust/crates/lief/src/dsc.rs new file mode 100644 index 0000000..14b55ec --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc.rs @@ -0,0 +1,106 @@ +//! Module for Dyld shared cache support +//! +//! ### Getting Started +//! +//! ```rust +//! let dyld_cache = lief::dsc::from_path("macos-15.0.1/"); +//! for dylib in dyld_cache.libraries() { +//! println!("0x{:016x}: {}", dylib.address(), dylib.path()); +//! let macho: lief::macho::Binary = dylib.get().expect("Can't get Mach-O representation"); +//! } +//! ``` +//! +//! ### Performance Considerations +//! +//!
+//! If you aim at extracting several libraries from a dyld shared cache, it is +//! highly recommended to enable caching. Otherwise, performances can be +//! impacted. +//!
+//! +//! See: [`crate::dsc::enable_cache`] and [`crate::dsc::enable_cache_from_dir`] +use crate::common::into_optional; +use lief_ffi as ffi; +use std::ffi::{CString, c_char}; +use std::path::Path; + +pub mod dyld_shared_cache; +pub mod dylib; +pub mod mapping_info; +pub mod subcache; +pub mod uuid; + +mod caching; + +#[doc(inline)] +pub use dyld_shared_cache::DyldSharedCache; + +#[doc(inline)] +pub use dylib::Dylib; + +#[doc(inline)] +pub use subcache::SubCache; + +#[doc(inline)] +pub use mapping_info::MappingInfo; + +#[doc(inline)] +pub use uuid::UUID; + +#[doc(inline)] +pub use caching::enable_cache; + +#[doc(inline)] +pub use caching::enable_cache_from_dir; + +/// Load a shared cache from a single file or from a directory specified +/// by the `path` parameter. +/// +/// In the case where multiple architectures are +/// available in the `path` directory, the `arch` parameter can be used to +/// define which architecture should be preferred. +/// +/// **Example:** +/// +/// ```rust +/// // From a directory (split caches) +/// let cache = lief::dsc::load("vision-pro-2.0/", ""); +/// +/// // From a single cache file +/// let cache = lief::dsc::load("ios-14.2/dyld_shared_cache_arm64", ""); +/// +/// // From a directory with multiple architectures +/// let cache = LIEF::dsc::load("macos-12.6/", /*arch=*/"x86_64h"); +/// ``` +pub fn load_from_path>(path: P, arch: &str) -> Option { + cxx::let_cxx_string!(__cxx_path = path.as_ref().to_str().unwrap()); + cxx::let_cxx_string!(__cxx_arch = arch); + into_optional(ffi::dsc_DyldSharedCache::from_path( + &__cxx_path, + &__cxx_arch, + )) +} + +pub fn load_from_files>(files: &[P]) -> Option { + let mut c_strings = Vec::new(); + let mut c_ptrs = Vec::new(); + for file in files.iter() { + let c_str = CString::new(file.as_ref().to_str().unwrap()).unwrap(); + c_strings.push(c_str); + let c_ptr = c_strings.last().unwrap().as_ptr() as *const c_char; + c_ptrs.push(c_ptr); + } + let files_ptr: *const *const c_char = c_ptrs.as_ptr(); + unsafe { + into_optional(ffi::dsc_DyldSharedCache::from_files( + files_ptr as *const c_char, + c_ptrs.len(), + )) + } +} + +/// Check if the given file is a dyld shared cache +pub fn is_shared_cache>(path: P) -> bool { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + ffi::dsc_Utils::is_shared_cache(&__cxx_s) +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/caching.rs b/vendor/lief/api/rust/crates/lief/src/dsc/caching.rs new file mode 100644 index 0000000..ac034a5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/caching.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; +use std::path::Path; + +/// Enable globally cache/memoization. One can also leverage this function +/// by setting the environment variable `DYLDSC_ENABLE_CACHE` to `1` +/// +/// By default, LIEF will use the directory specified by the environment +/// variable `DYLDSC_CACHE_DIR` as its cache-root directory: +/// +/// ```bash +/// DYLDSC_ENABLE_CACHE=1 DYLDSC_CACHE_DIR=/tmp/my_dir ./my-program +/// ``` +/// +/// Otherwise, if `DYLDSC_CACHE_DIR` is not set, LIEF will use the following +/// directory (in this priority): +/// +/// 1. System or user cache directory +/// - macOS: `DARWIN_USER_TEMP_DIR` / `DARWIN_USER_CACHE_DIR` + `/dyld_shared_cache` +/// - Linux: `${XDG_CACHE_HOME}/dyld_shared_cache` +/// - Windows: `%LOCALAPPDATA%\dyld_shared_cache` +/// 2. Home directory +/// - macOS/Linux: `$HOME/.dyld_shared_cache` +/// - Windows: `%USERPROFILE%\.dyld_shared_cache` +/// +/// See [`crate::dsc::DyldSharedCache::enable_caching`] for a finer granularity +pub fn enable_cache() -> bool { + ffi::dsc_enable_cache() +} + +/// Same behavior as [`enable_cache`] but with a user-provided cache directory +pub fn enable_cache_from_dir>(target_dir: P) -> bool { + cxx::let_cxx_string!(__cxx_s = target_dir.as_ref().to_str().unwrap()); + ffi::dsc_enable_cache_from_dir(&__cxx_s) +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/dyld_shared_cache.rs b/vendor/lief/api/rust/crates/lief/src/dsc/dyld_shared_cache.rs new file mode 100644 index 0000000..8420c8c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/dyld_shared_cache.rs @@ -0,0 +1,385 @@ +use lief_ffi as ffi; + +use super::{Dylib, MappingInfo, SubCache}; +use crate::Error; +use crate::common::{FromFFI, into_optional}; +use crate::{declare_iterator, declare_lazy_iterator, to_result}; +use std::path::Path; + +use crate::assembly; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// This enum wraps the dyld's git tags for which the structure of +/// dyld shared cache evolved +pub enum Version { + /// dyld-95.3 (2007-10-30) + DYLD_95_3, + /// dyld-195.5 (2011-07-13) + DYLD_195_5, + /// dyld-239.3 (2013-10-29) + DYLD_239_3, + /// dyld-360.14 (2015-09-04) + DYLD_360_14, + /// dyld-421.1 (2016-09-22) + DYLD_421_1, + /// dyld-832.7.1 (2020-11-19) + DYLD_832_7_1, + /// dyld-940 (2021-02-09) + DYLD_940, + /// dyld-1042.1 (2022-10-19) + DYLD_1042_1, + /// dyld-1231.3 (2024-09-24) + DYLD_1231_3, + /// dyld-1284.13 (2025-04-25) + DYLD_1284_13, + /// This value is used for versions of dyld not publicly released or not yet + /// supported by LIEF + UNRELEASED, + UNKNOWN(u32), +} + +impl From for Version { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Version::DYLD_95_3, + 0x00000002 => Version::DYLD_195_5, + 0x00000003 => Version::DYLD_239_3, + 0x00000004 => Version::DYLD_360_14, + 0x00000005 => Version::DYLD_421_1, + 0x00000006 => Version::DYLD_832_7_1, + 0x00000007 => Version::DYLD_940, + 0x00000008 => Version::DYLD_1042_1, + 0x00000009 => Version::DYLD_1231_3, + 0x0000000A => Version::DYLD_1284_13, + 0x0000000B => Version::UNRELEASED, + _ => Version::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Version) -> u32 { + match value { + Version::DYLD_95_3 => 0x00000001, + Version::DYLD_195_5 => 0x00000002, + Version::DYLD_239_3 => 0x00000003, + Version::DYLD_360_14 => 0x00000004, + Version::DYLD_421_1 => 0x00000005, + Version::DYLD_832_7_1 => 0x00000006, + Version::DYLD_940 => 0x00000007, + Version::DYLD_1042_1 => 0x00000008, + Version::DYLD_1231_3 => 0x00000009, + Version::DYLD_1284_13 => 0x0000000A, + Version::UNRELEASED => 0x0000000B, + Version::UNKNOWN(_) => 0, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// Platforms supported by the dyld shared cache +pub enum Platform { + MACOS, + IOS, + TVOS, + WATCHOS, + BRIDGEOS, + IOSMAC, + IOS_SIMULATOR, + TVOS_SIMULATOR, + WATCHOS_SIMULATOR, + DRIVERKIT, + VISIONOS, + VISIONOS_SIMULATOR, + FIRMWARE, + SEPOS, + ANY, + UNKNOWN(u32), +} + +impl From for Platform { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Platform::MACOS, + 0x00000002 => Platform::IOS, + 0x00000003 => Platform::TVOS, + 0x00000004 => Platform::WATCHOS, + 0x00000005 => Platform::BRIDGEOS, + 0x00000006 => Platform::IOSMAC, + 0x00000007 => Platform::IOS_SIMULATOR, + 0x00000008 => Platform::TVOS_SIMULATOR, + 0x00000009 => Platform::WATCHOS_SIMULATOR, + 0x0000000a => Platform::DRIVERKIT, + 0x0000000b => Platform::VISIONOS, + 0x0000000c => Platform::VISIONOS_SIMULATOR, + 0x0000000d => Platform::FIRMWARE, + 0x0000000e => Platform::SEPOS, + 0xffffffff => Platform::ANY, + _ => Platform::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Platform) -> u32 { + match value { + Platform::MACOS => 0x00000001, + Platform::IOS => 0x00000002, + Platform::TVOS => 0x00000003, + Platform::WATCHOS => 0x00000004, + Platform::BRIDGEOS => 0x00000005, + Platform::IOSMAC => 0x00000006, + Platform::IOS_SIMULATOR => 0x00000007, + Platform::TVOS_SIMULATOR => 0x00000008, + Platform::WATCHOS_SIMULATOR => 0x00000009, + Platform::DRIVERKIT => 0x0000000a, + Platform::VISIONOS => 0x0000000b, + Platform::VISIONOS_SIMULATOR => 0x0000000c, + Platform::FIRMWARE => 0x0000000d, + Platform::SEPOS => 0x0000000e, + Platform::ANY => 0xffffffff, + Platform::UNKNOWN(_) => 0, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// Architecture supported by the dyld shared cache +pub enum Arch { + I386, + X86_64, + X86_64H, + ARMV5, + ARMV6, + ARMV7, + ARM64, + ARM64E, + UNKNOWN(u32), +} + +impl From for Arch { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Arch::I386, + 0x00000002 => Arch::X86_64, + 0x00000003 => Arch::X86_64H, + 0x00000004 => Arch::ARMV5, + 0x00000005 => Arch::ARMV6, + 0x00000006 => Arch::ARMV7, + 0x00000007 => Arch::ARM64, + 0x00000008 => Arch::ARM64E, + _ => Arch::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Arch) -> u32 { + match value { + Arch::I386 => 0x00000001, + Arch::X86_64 => 0x00000002, + Arch::X86_64H => 0x00000003, + Arch::ARMV5 => 0x00000004, + Arch::ARMV6 => 0x00000005, + Arch::ARMV7 => 0x00000006, + Arch::ARM64 => 0x00000007, + Arch::ARM64E => 0x00000008, + Arch::UNKNOWN(_) => 0, + } + } +} + +/// This struct interfaces a dyld shared cache file. +pub struct DyldSharedCache { + ptr: cxx::UniquePtr, +} + +impl FromFFI for DyldSharedCache { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { ptr: info } + } +} + +impl DyldSharedCache { + /// Filename of the dyld shared file associated with this object. + /// + /// For instance: `dyld_shared_cache_arm64e, dyld_shared_cache_arm64e.62.dyldlinkedit` + pub fn filename(&self) -> String { + self.ptr.filename().to_string() + } + + /// Full path to the original dyld shared cache file associated with object + /// (e.g. `/home/lief/downloads/visionos/dyld_shared_cache_arm64e.42`) + pub fn filepath(&self) -> String { + self.ptr.filepath().to_string() + } + + /// Based address of this cache + pub fn load_address(&self) -> u64 { + self.ptr.load_address() + } + + /// Version of dyld used by this cache + pub fn version(&self) -> Version { + Version::from(self.ptr.version()) + } + + /// Name of the architecture targeted by this cache (`x86_64h`) + pub fn arch_name(&self) -> String { + self.ptr.arch_name().to_string() + } + + /// Platform targeted by this cache (e.g. vision-os) + pub fn platform(&self) -> Platform { + Platform::from(self.ptr.platform()) + } + + /// Architecture targeted by this cache + pub fn arch(&self) -> Arch { + Arch::from(self.ptr.arch()) + } + + /// Find the [`Dylib`] that encompasses the given virtual address. + pub fn find_lib_from_va(&self, va: u64) -> Option> { + into_optional(self.ptr.find_lib_from_va(va)) + } + + /// Find the [`Dylib`] whose [`Dylib::path`] matches the provided path. + pub fn find_lib_from_path>(&self, path: P) -> Option> { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + into_optional(self.ptr.find_lib_from_path(&__cxx_s)) + } + + /// Find the [`Dylib`] whose filename of [`Dylib::path`] matches the provided name. + /// + /// If multiple libraries have the same name (but with a different path), + /// the **first one** matching the provided name is returned. + pub fn find_lib_from_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.find_lib_from_name(&__cxx_s)) + } + + /// True if the subcaches are associated with this cache + pub fn has_subcaches(&self) -> bool { + self.ptr.has_subcaches() + } + + /// Return an iterator over the different [`Dylib`] libraries embedded + /// in this dyld shared cache + pub fn libraries(&self) -> Dylibs<'_> { + Dylibs::new(self.ptr.libraries()) + } + + /// Return an iterator over the different [`MappingInfo`] associated + /// with this dyld shared cache + pub fn mapping_info(&self) -> MappingInfoIt<'_> { + MappingInfoIt::new(self.ptr.mapping_info()) + } + + /// Return an interator over the subcaches associated with this (main) dyld shared + /// cache. + pub fn subcaches(&self) -> SubCacheIt<'_> { + SubCacheIt::new(self.ptr.subcaches()) + } + + /// Disassemble instructions at the provided virtual address. + /// + /// This function returns an iterator over [`assembly::Instructions`]. + pub fn disassemble(&self, address: u64) -> Instructions<'_> { + Instructions::new(self.ptr.disassemble(address)) + } + + /// Return the content at the specified virtual address + pub fn get_content_from_va(&self, address: u64, size: u64) -> Vec { + Vec::from(self.ptr.get_content_from_va(address, size).as_slice()) + } + + /// Find the sub-DyldSharedCache that wraps the given virtual address + pub fn cache_for_address(&self, address: u64) -> Option { + into_optional(self.ptr.cache_for_address(address)) + } + + /// Return the principal dyld shared cache in the case of multiple subcaches + pub fn main_cache(&self) -> Option { + into_optional(self.ptr.main_cache()) + } + + /// Try to find the [`DyldSharedCache`] associated with the filename given + /// in the first parameter. + pub fn find_subcache(&self, filename: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = filename); + into_optional(self.ptr.find_subcache(&__cxx_s)) + } + + /// Convert the given virtual address into an offset. + ///
+ /// If the shared cache contains multiple subcaches, + /// this function needs to be called on the targeted subcache. + ///
+ /// + /// See: [`DyldSharedCache::cache_for_address`] + pub fn va_to_offset(&self, address: u64) -> Result { + to_result!(ffi::dsc_DyldSharedCache::va_to_offset, &self, address); + } + + /// When enabled, this function allows to record and to keep in *cache*, + /// dyld shared cache information that are costly to access. + /// + /// For instance, GOT symbols, rebases information, stub symbols, ... + /// + /// It is **highly** recommended to enable this function when processing + /// a dyld shared cache several times or when extracting a large number of + /// [`Dylib`] with enhanced extraction options (e.g. [`crate::dsc::dylib::ExtractOpt::fix_memory`]) + /// + /// One can enable caching by calling this function: + /// + /// ```rust + /// let dyld_cache = lief::dsc::load_from_path("macos-15.0.1/", ""); + /// dyld_cache.enable_caching("/home/user/.cache/lief-dsc"); + /// ``` + /// + /// One can also enable this cache optimization **globally** using the + /// function: [`crate::dsc::enable_cache`] or by setting the environment variable + /// `DYLDSC_ENABLE_CACHE` to 1. + pub fn enable_caching>(&self, target_cache_dir: P) { + cxx::let_cxx_string!(__cxx_s = target_cache_dir.as_ref().to_str().unwrap()); + self.ptr.enable_caching(&__cxx_s) + } + + /// Flush internal information into the on-disk cache (see: enable_caching) + pub fn flush_cache(&self) { + self.ptr.flush_cache() + } +} + +declare_iterator!( + Dylibs, + Dylib<'a>, + ffi::dsc_Dylib, + ffi::dsc_DyldSharedCache, + ffi::dsc_DyldSharedCache_it_libraries +); + +declare_iterator!( + MappingInfoIt, + MappingInfo<'a>, + ffi::dsc_MappingInfo, + ffi::dsc_DyldSharedCache, + ffi::dsc_DyldSharedCache_it_mapping_info +); + +declare_iterator!( + SubCacheIt, + SubCache<'a>, + ffi::dsc_SubCache, + ffi::dsc_DyldSharedCache, + ffi::dsc_DyldSharedCache_it_subcaches +); + +declare_lazy_iterator!( + Instructions, + assembly::Instructions, + ffi::asm_Instruction, + ffi::dsc_DyldSharedCache, + ffi::dsc_DyldSharedCache_it_instructions +); diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/dylib.rs b/vendor/lief/api/rust/crates/lief/src/dsc/dylib.rs new file mode 100644 index 0000000..d6b74d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/dylib.rs @@ -0,0 +1,164 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::macho::Binary; +use std::marker::PhantomData; + +/// This structure represents a library embedded in a dyld shared cache. +/// It mirrors the original `dyld_cache_image_info` structure. +pub struct Dylib<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Dylib<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Dylib<'_> { + /// Original path of the library (e.g. `/usr/lib/libcryptex.dylib`) + pub fn path(&self) -> String { + self.ptr.path().to_string() + } + + /// In-memory address of the library + pub fn address(&self) -> u64 { + self.ptr.address() + } + + /// Modification time of the library matching `stat.st_mtime`, or 0 + pub fn modtime(&self) -> u64 { + self.ptr.modtime() + } + + /// File serial number matching `stat.st_ino` or 0 + /// + /// Note that for shared cache targeting iOS, this value can hold a hash of + /// the path (if modtime is set to 0) + pub fn inode(&self) -> u64 { + self.ptr.inode() + } + + /// Padding alignment value (should be 0) + pub fn padding(&self) -> u64 { + self.ptr.padding() + } + + /// Get a [`Binary`] representation for this Dylib. + /// + /// One can use this function to write back the Mach-O binary on the disk: + /// + /// ```rust + /// dylib.get().expect("Can't extract").write("liblockdown.dylib"); + /// ``` + pub fn get(&self) -> Option { + self.get_with_opt(&ExtractOpt::default()) + } + /// Get a [`Binary`] representation for this Dylib with the provided [`ExtractOpt`] options. + pub fn get_with_opt(&self, opt: &ExtractOpt) -> Option { + into_optional(self.ptr.get_macho(&opt.to_ffi())) + } +} + +/// This structure is used to tweak the extraction process while calling +/// [`Dylib::get_with_opt`]. These options allow to deoptimize the dylib and get an +/// accurate representation of the origin Mach-O binary. +pub struct ExtractOpt { + /// Whether the segment's offsets should be packed to avoid + /// an in-memory size while writing back the binary. + /// + ///
This option does not have an impact on the performances
+ pub pack: bool, + + /// Fix call instructions that target addresses outside the current dylib + /// virtual space. + /// + ///
+ /// Enabling this option can have a significant impact on the performance. + /// Make sure to enable the internal cache mechanism. + ///
+ /// + /// [`crate::dsc::enable_cache`] or [`crate::dsc::DyldSharedCache::enable_caching`] + pub fix_branches: bool, + + /// Fix memory accesses performed outside the dylib's virtual space + /// + ///
+ /// Enabling this option can have a significant impact on the performance. + /// Make sure to enable the internal cache mechanism. + ///
+ /// + /// [`crate::dsc::enable_cache`] or [`crate::dsc::DyldSharedCache::enable_caching`] + pub fix_memory: bool, + + /// Recover and fix relocations + /// + ///
+ /// Enabling this option can have a significant impact on the performance. + /// Make sure to enable the internal cache mechanism. + ///
+ /// + /// [`crate::dsc::enable_cache`] or [`crate::dsc::DyldSharedCache::enable_caching`] + pub fix_relocations: bool, + + /// Fix Objective-C information + /// + ///
+ /// Enabling this option can have a significant impact on the performance. + /// Make sure to enable the internal cache mechanism. + ///
+ /// + /// [`crate::dsc::enable_cache`] or [`crate::dsc::DyldSharedCache::enable_caching`] + pub fix_objc: bool, + + /// Whether the `LC_DYLD_CHAINED_FIXUPS` command should be (re)created. + /// + /// If this value is not set, LIEF will add the command only if it's + /// meaningful regarding the other options + pub create_dyld_chained_fixup_cmd: Option, +} + +impl Default for ExtractOpt { + fn default() -> ExtractOpt { + ExtractOpt { + pack: true, + fix_branches: false, + fix_memory: true, + fix_relocations: true, + fix_objc: true, + create_dyld_chained_fixup_cmd: None, + } + } +} + +impl ExtractOpt { + #[doc(hidden)] + fn to_ffi(&self) -> ffi::dsc_Dylib_extract_opt { + ffi::dsc_Dylib_extract_opt { + pack: self.pack, + fix_branches: self.fix_branches, + fix_memory: self.fix_memory, + fix_relocations: self.fix_relocations, + fix_objc: self.fix_objc, + create_dyld_chained_fixup_cmd: self.create_dyld_chained_fixup_cmd.unwrap_or(false), + create_dyld_chained_fixup_cmd_set: self.create_dyld_chained_fixup_cmd.is_some(), + } + } +} + +impl std::fmt::Debug for Dylib<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Dylib") + .field("path", &self.path()) + .field("address", &self.address()) + .field("modtime", &self.modtime()) + .field("inode", &self.inode()) + .field("padding", &self.padding()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/mapping_info.rs b/vendor/lief/api/rust/crates/lief/src/dsc/mapping_info.rs new file mode 100644 index 0000000..4fa0351 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/mapping_info.rs @@ -0,0 +1,67 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// This structure represents a `dyld_cache_mapping_info` entry. +/// +/// It provides information about the relationshiop between on-disk shared cache +/// and in-memory shared cache. +pub struct MappingInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for MappingInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl MappingInfo<'_> { + /// The in-memory address where this dyld shared cache region is mapped + pub fn address(&self) -> u64 { + self.ptr.address() + } + + /// Size of the region being mapped + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// End virtual address of the region + pub fn end_address(&self) -> u64 { + self.ptr.end_address() + } + + /// On-disk file offset + pub fn file_offset(&self) -> u64 { + self.ptr.file_offset() + } + + /// Max memory protection + pub fn max_prot(&self) -> u32 { + self.ptr.max_prot() + } + + /// Initial memory protection + pub fn init_prot(&self) -> u32 { + self.ptr.init_prot() + } +} + +impl std::fmt::Debug for MappingInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MappingInfo") + .field("address", &self.address()) + .field("end_address", &self.end_address()) + .field("size", &self.size()) + .field("file_offset", &self.file_offset()) + .field("max_prot", &self.max_prot()) + .field("init_prot", &self.init_prot()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/subcache.rs b/vendor/lief/api/rust/crates/lief/src/dsc/subcache.rs new file mode 100644 index 0000000..869267d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/subcache.rs @@ -0,0 +1,62 @@ +use lief_ffi as ffi; + +use super::DyldSharedCache; +use crate::common::{FromFFI, into_optional}; +use crate::dsc::UUID; +use std::marker::PhantomData; + +/// This class represents a subcache in the case of large/split dyld shared +/// cache. +/// +/// It mirror (and abstracts) the original `dyld_subcache_entry` / `dyld_subcache_entry_v1` +pub struct SubCache<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for SubCache<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl SubCache<'_> { + /// The uuid of the subcache file + pub fn uuid(&self) -> UUID { + let vec = Vec::from(self.ptr.uuid().as_slice()); + assert!(vec.len() == 16); + let mut uuid: UUID = [0; 16]; + for i in 0..16 { + uuid[i] = vec[i] as u8; + } + uuid + } + + /// The offset of this subcache from the main cache base address + pub fn vm_offset(&self) -> u64 { + self.ptr.vm_offset() + } + + /// The file name suffix of the subCache file (e.g. `.25.data`, `.03.development`) + pub fn suffix(&self) -> String { + self.ptr.suffix().to_string() + } + + /// The associated DyldSharedCache object for this subcache + pub fn cache(&self) -> Option { + into_optional(self.ptr.cache()) + } +} + +impl std::fmt::Debug for SubCache<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SubCache") + .field("uuid", &self.uuid()) + .field("vm_offset", &self.vm_offset()) + .field("suffix", &self.suffix()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dsc/uuid.rs b/vendor/lief/api/rust/crates/lief/src/dsc/uuid.rs new file mode 100644 index 0000000..a62fa2f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dsc/uuid.rs @@ -0,0 +1,2 @@ +/// UUID used in different places of the shared cache +pub type UUID = [u8; 16]; diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf.rs b/vendor/lief/api/rust/crates/lief/src/dwarf.rs new file mode 100644 index 0000000..a4c2836 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf.rs @@ -0,0 +1,72 @@ +//! Module for processing DWARF debug info +//! +//! This module exposes an API similar to the [`crate::pdb`] module to process DWARF +//! debug info (embedded or not). +//! +//! One can instantiate a [`crate::dwarf::DebugInfo`] using either [`crate::generic::Binary::debug_info`] or +//! [`crate::dwarf::load`] for external DWARF files. +//! +//! ``` +//! fn from_binary(elf: &lief::elf::Binary) { +//! if let Some(lief::DebugInfo::Dwarf(dwarf)) = elf.debug_info() { +//! for complilation_unit in dwarf.compilation_units() { +//! println!("{}", complilation_unit.name()); +//! } +//! } +//! } +//! +//! fn from_external(dwarf_file: &str) { +//! let debug_info = lief::dwarf::load(dwarf_file).unwrap(); +//! for complilation_unit in debug_info.compilation_units() { +//! println!("{}", complilation_unit.name()); +//! } +//! } +//! ``` + +use lief_ffi as ffi; +use std::path::Path; + +pub mod compilation_unit; +pub mod debug_info; +pub mod editor; +pub mod function; +pub mod lexical_block; +pub mod parameters; +pub mod scope; +pub mod types; +pub mod variable; + +use crate::common::into_optional; + +#[doc(inline)] +pub use debug_info::DebugInfo; + +#[doc(inline)] +pub use compilation_unit::CompilationUnit; + +#[doc(inline)] +pub use function::Function; + +#[doc(inline)] +pub use variable::Variable; + +#[doc(inline)] +pub use scope::Scope; + +#[doc(inline)] +pub use types::Type; + +#[doc(inline)] +pub use editor::Editor; + +#[doc(inline)] +pub use parameters::{Parameter, Parameters}; + +#[doc(inline)] +pub use lexical_block::LexicalBlock; + +/// Load a DWARF from its file path +pub fn load>(path: P) -> Option> { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + into_optional(ffi::DWARF_DebugInfo::from_file(&__cxx_s)) +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/compilation_unit.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/compilation_unit.rs new file mode 100644 index 0000000..9a0d860 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/compilation_unit.rs @@ -0,0 +1,283 @@ +//! This module wraps DWARF compilation unit + +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use crate::DeclOpt; +use crate::Range; +use crate::common::{FromFFI, into_optional, into_ranges}; +use crate::declare_fwd_iterator; + +use super::{Function, Variable}; +use crate::dwarf::function::Functions; +use crate::dwarf::types::Types; +use crate::dwarf::variable::CompilationUnitVariables; + +/// A DWARF compilation unit +pub struct CompilationUnit<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Langs { + C, + CPP, + RUST, + DART, + MODULA, + FORTRAN, + SWIFT, + D, + JAVA, + COBOL, + UNKNOWN(u32), +} + +impl From for Langs { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Langs::C, + 0x00000002 => Langs::CPP, + 0x00000003 => Langs::RUST, + 0x00000004 => Langs::DART, + 0x00000005 => Langs::MODULA, + 0x00000006 => Langs::FORTRAN, + 0x00000007 => Langs::SWIFT, + 0x00000008 => Langs::D, + 0x00000009 => Langs::JAVA, + 0x0000000A => Langs::COBOL, + _ => Langs::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Langs) -> u32 { + match value { + Langs::C => 0x00000001, + Langs::CPP => 0x00000002, + Langs::RUST => 0x00000003, + Langs::DART => 0x00000004, + Langs::MODULA => 0x00000005, + Langs::FORTRAN => 0x00000006, + Langs::SWIFT => 0x00000007, + Langs::D => 0x00000008, + Langs::JAVA => 0x00000009, + Langs::COBOL => 0x0000000A, + Langs::UNKNOWN(_) => 0, + } + } +} + +/// Languages supported by the DWARF (v5) format. +/// See: +/// +/// Some languages (like C++11, C++17, ..) have a version (11, 17, ...) which +/// is stored in a dedicated attribute: #version +#[derive(Debug)] +pub struct Language { + /// The language itself + pub lang: Langs, + + /// Version of the language (e.g. 17 for C++17) + pub version: u32, +} + +impl Language { + fn from_ffi(ffi_lang: ffi::DWARF_CompilationUnit_Language) -> Self { + Self { + lang: Langs::from(ffi_lang.lang), + version: ffi_lang.version, + } + } +} + +impl FromFFI for CompilationUnit<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CompilationUnit<'_> { + /// Name of the file associated with this compilation unit (e.g. `test.cpp`) + /// Return an **empty** string if the name is not found or can't be resolved + /// + /// This value matches the `DW_AT_name` attribute + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Information about the program (or library) that generated this compilation + /// unit. For instance, it can output: `Debian clang version 17.0.6`. + /// + /// It returns an **empty** string if the producer is not present or can't be + /// resolved + /// + /// This value matches the `DW_AT_producer` attribute + pub fn producer(&self) -> String { + self.ptr.producer().to_string() + } + + /// Return the path to the directory in which the compilation took place for + /// compiling this compilation unit (e.g. `/workdir/build`) + /// + /// It returns an **empty** string if the entry is not present or can't be + /// resolved + /// + /// This value matches the `DW_AT_comp_dir` attributeducer` attribute + pub fn compilation_dir(&self) -> String { + self.ptr.compilation_dir().to_string() + } + + /// Original Language of this compilation unit. + /// + /// This value matches the `DW_AT_language` attribute + pub fn language(&self) -> Language { + Language::from_ffi(self.ptr.language()) + } + + /// Return the lowest virtual address owned by this compilation unit. + pub fn low_address(&self) -> u64 { + self.ptr.low_address() + } + + /// Return the highest virtual address owned by this compilation unit. + pub fn high_address(&self) -> u64 { + self.ptr.high_address() + } + + /// Return the size of the compilation unit according to its range of address. + /// + /// If the compilation is fragmented (i.e. there are some address ranges + /// between the lowest address and the highest that are not owned by the CU), + /// then it returns the sum of **all** the address ranges owned by this CU. + /// + /// If the compilation unit is **not** fragmented, then is basically returns + /// `high_address - low_address`. + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Return a list of address ranges owned by this compilation unit. + /// + /// If the compilation unit owns a contiguous range, it should return + /// **a single** range. + pub fn ranges(&self) -> Vec { + into_ranges(self.ptr.ranges()) + } + + /// Return an iterator over the functions [`Function`] implemented in this compilation + /// unit. + /// + /// Note that this iterator only iterates over the functions that have a + /// **concrete** implementation in the compilation unit. + /// + /// For instance with this code: + /// + /// ```cpp + /// inline const char* get_secret_env() { + /// return getenv("MY_SECRET_ENV"); + /// } + /// + /// int main() { + /// printf("%s", get_secret_env()); + /// return 0; + /// } + /// ``` + /// + /// The iterator will only return **one function** for `main` since + /// `get_secret_env` is inlined and thus, its implementation is located in + /// `main`. + pub fn functions(&self) -> Functions<'_> { + Functions::new(self.ptr.functions()) + } + + /// Return an iterator over the functions **imported** in this compilation + /// unit **but not** implemented. + /// + /// For instance with this code: + /// + /// ```cpp + /// #include + /// int main() { + /// printf("Hello\n"); + /// return 0; + /// } + /// ``` + /// + /// `printf` is imported from the standard libc so the function is returned by + /// the iterator. On the other hand, `main()` is implemented in this + /// compilation unit so it is not returned by [`CompilationUnit::imported_functions`] but + /// [`CompilationUnit::functions`]. + pub fn imported_functions(&self) -> Functions<'_> { + Functions::new(self.ptr.imported_functions()) + } + + /// Return an iterator over the variables defined in the **global** scope + /// of this compilation unit: + /// + /// ```cpp + /// static int A = 1; // Returned by the iterator + /// static const char* B = "Hello"; // Returned by the iterator + /// + /// int get() { + /// static int C = 2; // Returned by the iterator + /// return C; + /// } + /// ``` + pub fn variables(&self) -> CompilationUnitVariables<'_> { + CompilationUnitVariables::new(self.ptr.variables()) + } + + pub fn types(&self) -> Types<'_> { + Types::new(self.ptr.types()) + } + + /// Try to find the function whose name is given in parameter. + /// + /// The provided name can be demangled. + pub fn function_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.function_by_name(&__cxx_s)) + } + + /// Try to find the function at the given address + pub fn function_by_addr(&self, address: u64) -> Option> { + into_optional(self.ptr.function_by_address(address)) + } + + /// Try to find the variable whose name is given in parameter. + pub fn variable_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.variable_by_name(&__cxx_s)) + } + + /// Try to find the variable at the given address + pub fn variable_by_addr(&self, address: u64) -> Option> { + into_optional(self.ptr.variable_by_address(address)) + } + + /// Generate a C/C++ definition for the functions defined in this + /// compilation unit. + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same as [`CompilationUnit::to_decl`] but with the given configuration + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + CompilationUnits, + CompilationUnit<'a>, + ffi::DWARF_CompilationUnit, + ffi::DWARF_DebugInfo, + ffi::DWARF_DebugInfo_it_compilation_units +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/debug_info.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/debug_info.rs new file mode 100644 index 0000000..fca05c0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/debug_info.rs @@ -0,0 +1,80 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::function::Function; +use crate::dwarf::types::Type; +use crate::dwarf::variable::Variable; +use crate::generic; +use std::marker::PhantomData; + +use super::compilation_unit::CompilationUnits; + +/// This class represents a DWARF debug information. It can embed different +/// compilation units which can be accessed through [`DebugInfo::compilation_units`]. +/// +/// This class can be instantiated from [`crate::generic::Binary::debug_info`] or using the +/// function [`crate::dwarf::load`] +pub struct DebugInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for DebugInfo<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl DebugInfo<'_> { + /// Iterator on the [`crate::dwarf::CompilationUnit`] embedded in this dwarf + pub fn compilation_units(&self) -> CompilationUnits<'_> { + CompilationUnits::new(self.ptr.compilation_units()) + } + + /// Try to find the function with the given name (mangled or not) + /// + /// ``` + /// if let Some(func) = info.function_by_name("_ZNSt6localeD1Ev") { + /// // Found + /// } + /// if let Some(func) = info.function_by_name("std::locale::~locale()") { + /// // Found + /// } + /// ``` + pub fn function_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.function_by_name(&__cxx_s)) + } + + /// Try to find the function at the given **virtual** address + pub fn function_by_addr(&self, addr: u64) -> Option> { + into_optional(self.ptr.function_by_addr(addr)) + } + + /// Try to find the variable with the given name. This name can be mangled or + /// not. + pub fn variable_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.variable_by_name(&__cxx_s)) + } + + /// Try to find the (static) variable at the given **virtual** address + pub fn variable_by_addr(&self, addr: u64) -> Option> { + into_optional(self.ptr.variable_by_addr(addr)) + } + + /// Try to find the (static) variable at the given **virtual** address + pub fn type_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.type_by_name(&__cxx_s)) + } +} + +impl generic::DebugInfo for DebugInfo<'_> { + fn as_generic(&self) -> &ffi::AbstracDebugInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor.rs new file mode 100644 index 0000000..c773e65 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor.rs @@ -0,0 +1,124 @@ +use lief_ffi as ffi; + +use crate::{common::FromFFI, common::into_optional, generic}; +use std::marker::PhantomData; +use std::option::Option; +use std::path::Path; + +pub mod compilation_unit; +pub mod function; +pub mod types; +pub mod variable; + +#[doc(inline)] +pub use compilation_unit::CompilationUnit; + +#[doc(inline)] +pub use types::Type; + +#[doc(inline)] +pub use variable::Variable; + +#[doc(inline)] +pub use function::Function; + +/// This structure exposes the main API to create DWARF information +pub struct Editor<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Editor<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Format { + ELF, + MACHO, + PE, + UNKNOWN(u32), +} + +impl From for Format { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Format::ELF, + 0x00000001 => Format::MACHO, + 0x00000002 => Format::PE, + _ => Format::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Format) -> u32 { + match value { + Format::ELF => 0x00000000, + Format::MACHO => 0x00000001, + Format::PE => 0x00000002, + Format::UNKNOWN(_) => 0, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Arch { + X64, + X86, + AARCH64, + ARM, + UNKNOWN(u32), +} + +impl From for Arch { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Arch::X64, + 0x00000002 => Arch::X86, + 0x00000003 => Arch::AARCH64, + 0x00000004 => Arch::ARM, + _ => Arch::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Arch) -> u32 { + match value { + Arch::X64 => 0x00000001, + Arch::X86 => 0x00000002, + Arch::AARCH64 => 0x00000003, + Arch::ARM => 0x00000004, + Arch::UNKNOWN(_) => 0, + } + } +} + +impl<'a> Editor<'a> { + /// Instantiate an editor for the given binary object + pub fn from_binary(bin: &'a mut dyn generic::Binary) -> Option> { + into_optional(ffi::DWARF_Editor::from_binary(bin.as_pin_mut_generic())) + } + + /// Instantiate an editor for the given format and arch + pub fn create(fmt: Format, arch: Arch) -> Option> { + into_optional(ffi::DWARF_Editor::create(fmt.into(), arch.into())) + } + + /// Create a new compilation unit + pub fn create_compile_unit(&mut self) -> Option> { + into_optional(self.ptr.pin_mut().create_compilation_unit()) + } + + /// Write the DWARF file to the specified output + pub fn write>(&mut self, output: P) { + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr.pin_mut().write(&__cxx_s) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/compilation_unit.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/compilation_unit.rs new file mode 100644 index 0000000..2c70b8a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/compilation_unit.rs @@ -0,0 +1,136 @@ +use lief_ffi as ffi; + +use crate::{common::FromFFI, common::into_optional}; +use std::marker::PhantomData; +use std::option::Option; + +use super::Type; +use super::function::Function; +use super::types::Function as FunctionType; +use super::types::base; +use super::types::struct_ty; +use super::types::{Array, Base, EditorType, Enum, Pointer, Struct, Typedef}; +use super::variable::Variable; + +/// This structure represents an **editable** DWARF compilation unit +pub struct CompilationUnit<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for CompilationUnit<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CompilationUnit<'_> { + /// Set the `DW_AT_producer` producer attribute. + /// + /// This attribute aims to inform about the program that generated this + /// compilation unit (e.g. `LIEF Extended`) + pub fn set_producer(&mut self, value: &str) { + cxx::let_cxx_string!(__cxx_s = value); + self.ptr.pin_mut().set_producer(&__cxx_s) + } + + /// Create a new function owned by this compilation unit + pub fn create_function(&mut self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.pin_mut().create_function(&__cxx_s)) + } + + /// Create a new **global** variable owned by this compilation unit + pub fn create_variable(&mut self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.pin_mut().create_variable(&__cxx_s)) + } + + /// Create a `DW_TAG_unspecified_type` type with the given name + pub fn create_generic_type(&mut self, name: &str) -> Type { + cxx::let_cxx_string!(__cxx_s = name); + Type::from_ffi(self.ptr.pin_mut().create_generic_type(&__cxx_s)) + } + + /// Create an enum type (`DW_TAG_enumeration_type`) + pub fn create_enum(&mut self, name: &str) -> Enum { + cxx::let_cxx_string!(__cxx_s = name); + Enum::from_ffi(self.ptr.pin_mut().create_enum(&__cxx_s)) + } + + /// Create a typdef with the name provided in the first parameter which aliases + /// the type provided in the second parameter + pub fn create_typedef(&mut self, name: &str, ty: &dyn EditorType) -> Typedef { + cxx::let_cxx_string!(__cxx_s = name); + Typedef::from_ffi(self.ptr.pin_mut().create_typedef(&__cxx_s, ty.get_base())) + } + + /// Create a structure type (`DW_TAG_structure_type`) + pub fn create_structure(&mut self, name: &str) -> Struct { + cxx::let_cxx_string!(__cxx_s = name); + Struct::from_ffi( + self.ptr + .pin_mut() + .create_structure(&__cxx_s, struct_ty::Kind::STRUCT.into()), + ) + } + + /// Create a structure type (`DW_TAG_class_type`) + pub fn create_class(&mut self, name: &str) -> Struct { + cxx::let_cxx_string!(__cxx_s = name); + Struct::from_ffi( + self.ptr + .pin_mut() + .create_structure(&__cxx_s, struct_ty::Kind::CLASS.into()), + ) + } + + /// Create a union type (`DW_TAG_union_type`) + pub fn create_union(&mut self, name: &str) -> Struct { + cxx::let_cxx_string!(__cxx_s = name); + Struct::from_ffi( + self.ptr + .pin_mut() + .create_structure(&__cxx_s, struct_ty::Kind::UNION.into()), + ) + } + + /// Create a primitive type with the given name and size. + pub fn create_base_type(&mut self, name: &str, size: u64, encoding: base::Encoding) -> Base { + cxx::let_cxx_string!(__cxx_s = name); + Base::from_ffi( + self.ptr + .pin_mut() + .create_base_type(&__cxx_s, size, encoding.into()), + ) + } + + /// Create a function type with the given name. + pub fn create_function_type(&mut self, name: &str) -> FunctionType { + cxx::let_cxx_string!(__cxx_s = name); + FunctionType::from_ffi(self.ptr.pin_mut().create_function_type(&__cxx_s)) + } + + /// Create a pointer on the provided type + pub fn create_pointer_type(&mut self, ty: &dyn EditorType) -> Pointer { + Pointer::from_ffi(self.ptr.pin_mut().create_pointer_type(ty.get_base())) + } + + /// Create a `void` type + pub fn create_void_type(&mut self) -> Type { + Type::from_ffi(self.ptr.pin_mut().create_void_type()) + } + + /// Create an array type with the given name, type and size. + pub fn create_array_type(&mut self, name: &str, ty: &dyn EditorType, count: u64) -> Array { + cxx::let_cxx_string!(__cxx_s = name); + Array::from_ffi( + self.ptr + .pin_mut() + .create_array_type(&__cxx_s, ty.get_base(), count), + ) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/function.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/function.rs new file mode 100644 index 0000000..3ce710c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/function.rs @@ -0,0 +1,185 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; + +use crate::dwarf::editor::Variable; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents an **editable** DWARF function (`DW_TAG_subprogram`) +pub struct Function { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Function { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +/// This structure defines an implementation range +pub struct Range { + start: u64, + end: u64, +} + +/// This structure represents a parameter of the current function (`DW_TAG_formal_parameter`) +pub struct Parameter { + ptr: cxx::UniquePtr, +} + +impl Parameter { + /// Assign this parameter to a specific named register. + pub fn assign_register_by_name(&mut self, name: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().assign_register_by_name(&__cxx_s); + self + } + + /// Assign this parameter to the given DWARF register id (e.g. `DW_OP_reg0`). + pub fn assign_register_by_id(&mut self, id: u64) -> &mut Self { + self.ptr.pin_mut().assign_register_by_id(id); + self + } +} + +impl FromFFI for Parameter { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +/// This structure mirrors the `DW_TAG_lexical_block` DWARF tag +pub struct LexicalBlock { + ptr: cxx::UniquePtr, +} + +impl FromFFI for LexicalBlock { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl LexicalBlock { + /// Create a `DW_AT_name` entry to associate a name to this entry + pub fn add_name(&mut self, name: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().add_name(&__cxx_s); + self + } + + /// Create a `DW_AT_description` entry with the description + /// provided in parameter. + pub fn add_description(&mut self, description: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = description); + self.ptr.pin_mut().add_description(&__cxx_s); + self + } + + /// Create a sub-block with the given low/high addresses. + pub fn add_block(&mut self, start: u64, end: u64) -> Option { + into_optional(self.ptr.pin_mut().add_block(start, end)) + } + + /// Create a sub-block with the given range of addresses. + pub fn add_block_from_range(&mut self, ranges: &[Range]) -> Option { + let mut ffi_ranges = cxx::CxxVector::new(); + for range in ranges { + let ffi_range = ffi::DWARF_editor_Function_Range { + start: range.start, + end: range.end, + }; + ffi_ranges.as_mut().unwrap().push(ffi_range); + } + into_optional(self.ptr.pin_mut().add_block_from_range(&ffi_ranges)) + } +} + +/// This class mirrors the `DW_TAG_label` DWARF tag +#[allow(dead_code)] +pub struct Label { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Label { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Function { + /// Set the address of this function by defining `DW_AT_entry_pc` + pub fn set_address(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().set_address(addr); + self + } + + /// Set the upper and lower bound addresses for this function. This assumes + /// that the function is contiguous between `low` and `high`. + /// + /// Underneath, the function defines `DW_AT_low_pc` and `DW_AT_high_pc` + pub fn set_low_high(&mut self, low: u64, high: u64) -> &mut Self { + self.ptr.pin_mut().set_low_high(low, high); + self + } + + /// Set the ranges of addresses owned by the implementation of this function + /// by setting the `DW_AT_ranges` attribute. + /// + /// This setter should be used for non-contiguous functions. + pub fn set_ranges(&mut self, ranges: &[Range]) -> &mut Self { + let mut ffi_ranges = cxx::CxxVector::new(); + for range in ranges { + let ffi_range = ffi::DWARF_editor_Function_Range { + start: range.start, + end: range.end, + }; + ffi_ranges.as_mut().unwrap().push(ffi_range); + } + self.ptr.pin_mut().set_ranges(&ffi_ranges); + self + } + + /// Set the function as external by defining `DW_AT_external` to true. + /// This means that the function is **imported** by the current compilation unit. + pub fn set_external(&mut self) -> &mut Self { + self.ptr.pin_mut().set_external(); + self + } + + /// Set the return type of this function + pub fn set_return_type(&mut self, ty: &dyn EditorType) -> &mut Self { + self.ptr.pin_mut().set_return_type(ty.get_base()); + self + } + + /// Add a parameter to the current function + pub fn add_parameter(&mut self, name: &str, ty: &dyn EditorType) -> Parameter { + cxx::let_cxx_string!(__cxx_s = name); + Parameter::from_ffi(self.ptr.pin_mut().add_parameter(&__cxx_s, ty.get_base())) + } + + /// Create a stack-based variable owned by the current function + pub fn create_stack_variable(&mut self, name: &str) -> Variable { + cxx::let_cxx_string!(__cxx_s = name); + Variable::from_ffi(self.ptr.pin_mut().create_stack_variable(&__cxx_s)) + } + + /// Add a lexical block with the given range + pub fn add_lexical_block(&mut self, start: u64, end: u64) -> LexicalBlock { + LexicalBlock::from_ffi(self.ptr.pin_mut().add_lexical_block(start, end)) + } + + /// Add a label at the given address + pub fn add_label(&mut self, addr: u64, name: &str) -> Label { + cxx::let_cxx_string!(__cxx_name = name); + Label::from_ffi(self.ptr.pin_mut().add_label(addr, &__cxx_name)) + } + + /// Create a `DW_AT_description` entry with the description + /// provided in parameter. + pub fn add_description(&mut self, description: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = description); + self.ptr.pin_mut().add_description(&__cxx_s); + self + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types.rs new file mode 100644 index 0000000..e656c62 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types.rs @@ -0,0 +1,161 @@ +use lief_ffi as ffi; + +pub mod array; +pub mod base; +pub mod enum_ty; +pub mod function; +pub mod pointer; +pub mod struct_ty; +pub mod typedef; + +use crate::common::FromFFI; + +#[doc(inline)] +pub use pointer::Pointer; + +#[doc(inline)] +pub use array::Array; + +#[doc(inline)] +pub use base::Base; + +#[doc(inline)] +pub use enum_ty::Enum; + +#[doc(inline)] +pub use function::Function; + +#[doc(inline)] +pub use struct_ty::Struct; + +#[doc(inline)] +pub use typedef::Typedef; + +/// The different types supported by the editor interface +pub enum Type { + /// Mirror `DW_TAG_pointer_type` + Pointer(Pointer), + + /// Mirror `DW_TAG_array_type` + Array(Array), + + /// Mirror `DW_TAG_base_type` + Base(Base), + + /// Mirror `DW_TAG_enumeration_type` + Enum(Enum), + + /// Mirror `DW_TAG_subroutine_type` + Function(Function), + + /// Mirror `DW_TAG_class_type, DW_TAG_structure_type, DW_TAG_union_type` + Struct(Struct), + + /// Mirror `DW_TAG_typedef` + Typedef(Typedef), + + Generic(Generic), +} + +impl FromFFI for Type { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let type_ref = ffi_entry.as_ref().unwrap(); + + if ffi::DWARF_editor_PointerType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Pointer(Pointer::from_ffi(raw)) + } else if ffi::DWARF_editor_ArrayType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Array(Array::from_ffi(raw)) + } else if ffi::DWARF_editor_BaseType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Base(Base::from_ffi(raw)) + } else if ffi::DWARF_editor_EnumType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Enum(Enum::from_ffi(raw)) + } else if ffi::DWARF_editor_FunctionType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Function(Function::from_ffi(raw)) + } else if ffi::DWARF_editor_StructType::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Struct(Struct::from_ffi(raw)) + } else if ffi::DWARF_editor_TypeDef::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Typedef(Typedef::from_ffi(raw)) + } else { + Type::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +/// Generic trait shared by all DWARF editor types +pub trait EditorType { + #[doc(hidden)] + fn get_base(&self) -> &ffi::DWARF_editor_Type; + + fn pointer_to(&self) -> Pointer { + Pointer::from_ffi(self.get_base().pointer_to()) + } +} + +/// This structure represents a generic type (like `DW_TAG_unspecified_type`) +pub struct Generic { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Generic { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Generic { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap() + } +} + +impl EditorType for Type { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + match &self { + Type::Pointer(s) => s.get_base(), + Type::Array(s) => s.get_base(), + Type::Base(s) => s.get_base(), + Type::Enum(s) => s.get_base(), + Type::Function(s) => s.get_base(), + Type::Struct(s) => s.get_base(), + Type::Typedef(s) => s.get_base(), + Type::Generic(s) => s.get_base(), + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/array.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/array.rs new file mode 100644 index 0000000..16dde71 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/array.rs @@ -0,0 +1,21 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents an array type (`DW_TAG_array_type`). +pub struct Array { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Array { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Array { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/base.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/base.rs new file mode 100644 index 0000000..58beeb1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/base.rs @@ -0,0 +1,67 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents a primitive type like `int, char`. +pub struct Base { + ptr: cxx::UniquePtr, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Encoding { + NONE, + ADDRESS, + SIGNED, + SIGNED_CHAR, + UNSIGNED, + UNSIGNED_CHAR, + BOOLEAN, + FLOAT, + UNKNOWN(u32), +} + +impl From for Encoding { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Encoding::NONE, + 0x00000001 => Encoding::ADDRESS, + 0x00000002 => Encoding::SIGNED, + 0x00000003 => Encoding::SIGNED_CHAR, + 0x00000004 => Encoding::UNSIGNED, + 0x00000005 => Encoding::UNSIGNED_CHAR, + 0x00000006 => Encoding::BOOLEAN, + 0x00000007 => Encoding::FLOAT, + _ => Encoding::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Encoding) -> Self { + match value { + Encoding::NONE => 0, + Encoding::ADDRESS => 1, + Encoding::SIGNED => 2, + Encoding::SIGNED_CHAR => 3, + Encoding::UNSIGNED => 4, + Encoding::UNSIGNED_CHAR => 5, + Encoding::BOOLEAN => 6, + Encoding::FLOAT => 7, + Encoding::UNKNOWN(value) => value, + } + } +} + +impl FromFFI for Base { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Base { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/enum_ty.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/enum_ty.rs new file mode 100644 index 0000000..a2d16aa --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/enum_ty.rs @@ -0,0 +1,53 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents an editable enum type (`DW_TAG_enumeration_type`) +pub struct Enum { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Enum { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl Enum { + /// Define the number of bytes required to hold an instance of the + /// enumeration (`DW_AT_byte_size`). + pub fn set_size(&mut self, size: u64) { + self.ptr.pin_mut().set_size(size); + } + + /// Add an enum value by specifying its name and its integer value + pub fn add_value(&mut self, name: &str, value: i64) -> Value { + cxx::let_cxx_string!(__cxx_name = name); + Value::from_ffi(self.ptr.pin_mut().add_value(&__cxx_name, value)) + } + + /// Set the underlying type that is used to encode this enum + pub fn set_underlying_type(&mut self, ty: &dyn EditorType) -> &mut Self { + self.ptr.pin_mut().set_underlying_type(ty.get_base()); + self + } +} + +impl EditorType for Enum { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This structure represents an enum value. +#[allow(dead_code)] +pub struct Value { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Value { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/function.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/function.rs new file mode 100644 index 0000000..62450e8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/function.rs @@ -0,0 +1,46 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents a function type (`DW_TAG_subroutine_type`) +pub struct Function { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Function { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Function { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Function { + /// Set the return type of this function + pub fn set_return_type(&mut self, ty: &dyn EditorType) -> &mut Self { + self.ptr.pin_mut().set_return_type(ty.get_base()); + self + } + + /// Add a parameter + pub fn add_parameter(&mut self, ty: &dyn EditorType) -> Parameter { + Parameter::from_ffi(self.ptr.pin_mut().add_parameter(ty.get_base())) + } +} + +/// This structure represents a function's parameter +#[allow(dead_code)] +pub struct Parameter { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Parameter { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/pointer.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/pointer.rs new file mode 100644 index 0000000..8aa4be3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/pointer.rs @@ -0,0 +1,21 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents a `DW_TAG_pointer_type` DWARF type. +pub struct Pointer { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Pointer { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Pointer { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/struct_ty.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/struct_ty.rs new file mode 100644 index 0000000..f91df4f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/struct_ty.rs @@ -0,0 +1,125 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents a struct-like type which can be: +/// +/// - `DW_TAG_class_type` +/// - `DW_TAG_structure_type` +/// - `DW_TAG_union_type` +pub struct Struct { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Struct { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Kind { + CLASS, + STRUCT, + UNION, + UNKNOWN(u32), +} + +impl From for Kind { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Kind::CLASS, + 0x00000001 => Kind::STRUCT, + 0x00000002 => Kind::UNION, + _ => Kind::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Kind) -> Self { + match value { + Kind::CLASS => 0, + Kind::STRUCT => 1, + Kind::UNION => 2, + Kind::UNKNOWN(value) => value, + } + } +} + +impl Struct { + /// Define the overall size which is equivalent to the `sizeof` of the current + /// type. + /// + /// This function defines the `DW_AT_byte_size` attribute + pub fn set_size(&mut self, size: u64) { + self.ptr.pin_mut().set_size(size); + } + + /// Add a member to the current struct-like + pub fn add_member(&mut self, name: &str, ty: &mut dyn EditorType) -> Member { + cxx::let_cxx_string!(__cxx_name = name); + Member::from_ffi(self.ptr.pin_mut().add_member(&__cxx_name, ty.get_base())) + } + + /// Add a member to the current struct-like at the specified offset + pub fn add_member_at_offset( + &mut self, + name: &str, + ty: &mut dyn EditorType, + offset: u64, + ) -> Member { + cxx::let_cxx_string!(__cxx_name = name); + Member::from_ffi(self.ptr.pin_mut().add_member_with_offset( + &__cxx_name, + ty.get_base(), + offset, + )) + } + + /// Add a bitfield to the current struct-like + pub fn add_bitfield(&mut self, name: &str, ty: &mut dyn EditorType, bitsize: u64) -> Member { + cxx::let_cxx_string!(__cxx_name = name); + Member::from_ffi( + self.ptr + .pin_mut() + .add_bitfield(&__cxx_name, ty.get_base(), bitsize), + ) + } + + /// Add a bitfield to the current struct-like at the specified offset + pub fn add_bitfield_at_offset( + &mut self, + name: &str, + ty: &mut dyn EditorType, + bitsize: u64, + bitoffset: u64, + ) -> Member { + cxx::let_cxx_string!(__cxx_name = name); + Member::from_ffi(self.ptr.pin_mut().add_bitfield_with_offset( + &__cxx_name, + ty.get_base(), + bitsize, + bitoffset, + )) + } +} + +impl EditorType for Struct { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +#[allow(dead_code)] +pub struct Member { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Member { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/typedef.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/typedef.rs new file mode 100644 index 0000000..015a337 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/types/typedef.rs @@ -0,0 +1,21 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::editor::types::EditorType; + +/// This structure represents a typedef (`DW_TAG_typedef`). +pub struct Typedef { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Typedef { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { ptr: cmd } + } +} + +impl EditorType for Typedef { + fn get_base(&self) -> &ffi::DWARF_editor_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/editor/variable.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/variable.rs new file mode 100644 index 0000000..44a52bd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/editor/variable.rs @@ -0,0 +1,56 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; + +use crate::dwarf::editor::Type; +use crate::dwarf::editor::types::EditorType; + +pub struct Variable { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Variable { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Variable { + /// Set the global address of this variable. Setting this address is only + /// revelant in the case of a static global variable. For stack variable, you + /// should use [`Variable::set_stack_offset`]. + /// + /// This function set the `DW_AT_location` attribute + pub fn set_addr(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().set_addr(addr); + self + } + + /// Set the stack offset of this variable. + /// + /// This function set the `DW_AT_location` attribute + pub fn set_stack_offset(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().set_stack_offset(addr); + self + } + + /// Mark this variable as **imported** + pub fn set_external(&mut self) -> &mut Self { + self.ptr.pin_mut().set_external(); + self + } + + /// Set the type of the current variable + pub fn set_type(&mut self, ty: &Type) -> &mut Self { + self.ptr.pin_mut().set_type(ty.get_base()); + self + } + + /// Create a `DW_AT_description` entry with the description + /// provided in parameter. + pub fn add_description(&mut self, description: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = description); + self.ptr.pin_mut().add_description(&__cxx_s); + self + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/function.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/function.rs new file mode 100644 index 0000000..a24d917 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/function.rs @@ -0,0 +1,179 @@ +use lief_ffi as ffi; + +use super::lexical_block::LexicalBlock; +use super::variable::Variables; +use super::{Parameters, Scope, Type}; +use crate::Error; +use crate::Range; +use crate::assembly; +use crate::common::{FromFFI, into_optional, into_ranges}; +use crate::to_result; +use crate::{DebugLocation, DeclOpt}; +use crate::{declare_fwd_iterator, declare_lazy_iterator}; +use std::marker::PhantomData; + +/// This structure represents a DWARF function which can be associated with either: +/// `DW_TAG_subprogram` or `DW_TAG_inlined_subroutine`. +pub struct Function<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Function<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Function<'_> { + /// The name of the function (`DW_AT_name`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// The name of the function which is used for linking (`DW_AT_linkage_name`). + /// + /// This name differs from [`Function::name`] as it is usually mangled. The function + /// return an empty string if the linkage name is not available. + pub fn linkage_name(&self) -> String { + self.ptr.linkage_name().to_string() + } + + /// Return the address of the function (`DW_AT_entry_pc` or `DW_AT_low_pc`). + pub fn address(&self) -> Result { + to_result!(ffi::DWARF_Function::address, self); + } + + /// Return an iterator of variables (`DW_TAG_variable`) defined within the + /// scope of this function. This includes regular stack-based variables as + /// well as static ones. + pub fn variables(&self) -> Variables<'_> { + Variables::new(self.ptr.variables()) + } + + /// Whether this function is created by the compiler and not + /// present in the original source code + pub fn is_artificial(&self) -> bool { + self.ptr.is_artificial() + } + + /// Whether the function is defined **outside** the compilation unit (`DW_AT_external`) + pub fn is_external(&self) -> bool { + self.ptr.is_external() + } + + /// Return the size taken by this function in the binary + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Ranges of virtual addresses owned by this function + pub fn ranges(&self) -> Vec { + into_ranges(self.ptr.ranges()) + } + + /// Original source code location + pub fn debug_location(&self) -> DebugLocation { + DebugLocation::from_ffi(self.ptr.debug_location()) + } + + /// Return the [`Type`] associated with the **return type** of this function. + pub fn return_type(&self) -> Option> { + into_optional(self.ptr.get_type()) + } + + /// Return an iterator over the [`Parameters`] of this function + pub fn parameters(&self) -> ParametersIt<'_> { + ParametersIt::new(self.ptr.parameters()) + } + + /// List of exceptions (types) that can be thrown by the function. + /// + /// For instance, given this Swift code: + /// + /// ```swift + /// func summarize(_ ratings: [Int]) throws(StatisticsError) { + /// // ... + /// } + /// ``` + /// + /// [`Function::thrown_types`] returns one element associated with the [`Type`]: + /// `StatisticsError`. + pub fn thrown_types(&self) -> ThrownTypes<'_> { + ThrownTypes::new(self.ptr.thrown_types()) + } + + /// The scope in which this function is defined + pub fn scope(&self) -> Option> { + into_optional(self.ptr.scope()) + } + + /// Disassemble the current function by returning an iterator over + /// the [`assembly::Instructions`] + pub fn instructions(&self) -> Instructions<'_> { + Instructions::new(self.ptr.instructions()) + } + + /// Description (`DW_AT_description`) of this function or an empty string + pub fn description(&self) -> String { + self.ptr.description().to_string() + } + + /// Iterator over the [`crate::dwarf::LexicalBlock`] owned by this function + pub fn lexical_blocks(&self) -> LexicalBlocks<'_> { + LexicalBlocks::new(self.ptr.lexical_blocks()) + } + + /// Generates a C/C++ definition for this function + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Generates a C/C++ definition for this function with the given configuration + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Functions, + Function<'a>, + ffi::DWARF_Function, + ffi::DWARF_CompilationUnit, + ffi::DWARF_CompilationUnit_it_functions +); + +declare_fwd_iterator!( + ParametersIt, + Parameters<'a>, + ffi::DWARF_Parameter, + ffi::DWARF_Function, + ffi::DWARF_Function_it_parameters +); + +declare_fwd_iterator!( + ThrownTypes, + Type<'a>, + ffi::DWARF_Type, + ffi::DWARF_Function, + ffi::DWARF_Function_it_thrown_types +); + +declare_lazy_iterator!( + Instructions, + assembly::Instructions, + ffi::asm_Instruction, + ffi::DWARF_Function, + ffi::DWARF_Function_it_instructions +); + +declare_fwd_iterator!( + LexicalBlocks, + LexicalBlock<'a>, + ffi::DWARF_LexicalBlock, + ffi::DWARF_Function, + ffi::DWARF_Function_it_lexical_blocks +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/lexical_block.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/lexical_block.rs new file mode 100644 index 0000000..ab53953 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/lexical_block.rs @@ -0,0 +1,74 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_ranges}; +use crate::{Range, declare_fwd_iterator, to_opt}; +use std::marker::PhantomData; + +/// This structure represents a DWARF lexical block (`DW_TAG_lexical_block`) +pub struct LexicalBlock<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for LexicalBlock<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl LexicalBlock<'_> { + /// Return the *name* associated with this lexical block or an empty string + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Return the description associated with this lexical block or an empty string + pub fn description(&self) -> String { + self.ptr.description().to_string() + } + + /// Return an iterator over the sub-LexicalBlock owned by this block. + pub fn sub_blocks(&self) -> LexicalBlocks<'_> { + LexicalBlocks::new(self.ptr.sub_blocks()) + } + + /// Return the start address of this block + pub fn addr(&self) -> Option { + to_opt!(&lief_ffi::DWARF_LexicalBlock::addr, &self); + } + + /// Return the lowest virtual address owned by this block. + pub fn low_pc(&self) -> Option { + to_opt!(&lief_ffi::DWARF_LexicalBlock::low_pc, &self); + } + + /// Return the highest virtual address owned by this block. + pub fn high_pc(&self) -> Option { + to_opt!(&lief_ffi::DWARF_LexicalBlock::high_pc, &self); + } + + /// Return the size of this block as the difference of the highest address and the lowest + /// address. + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Return a list of address ranges owned by this block. + /// + /// If the lexical block owns a contiguous range, it should return + /// **a single** range. + pub fn ranges(&self) -> Vec { + into_ranges(self.ptr.ranges()) + } +} + +declare_fwd_iterator!( + LexicalBlocks, + LexicalBlock<'a>, + ffi::DWARF_LexicalBlock, + ffi::DWARF_LexicalBlock, + ffi::DWARF_LexicalBlock_it_sub_blocks +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/parameters.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/parameters.rs new file mode 100644 index 0000000..fe40b14 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/parameters.rs @@ -0,0 +1,184 @@ +use lief_ffi as ffi; + +use super::Type; +use crate::common::FromFFI; + +use crate::common::into_optional; +use std::marker::PhantomData; + +pub trait Parameter { + #[doc(hidden)] + fn get_base(&self) -> &ffi::DWARF_Parameter; + + /// The name of the parameter + fn name(&self) -> String { + self.get_base().name().to_string() + } + + /// Return the type of the parameter + fn get_type(&self) -> Option> { + into_optional(self.get_base().get_type()) + } + + /// Location of this parameter. For instance it can be a specific register + /// that is not following the calling convention. + fn location(&self) -> Option> { + into_optional(self.get_base().location()) + } +} + +pub enum Parameters<'a> { + Formal(Formal<'a>), + TemplateValue(TemplateValue<'a>), + TemplateType(TemplateType<'a>), +} + +impl FromFFI for Parameters<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let param_ref = ffi_entry.as_ref().unwrap(); + + if ffi::DWARF_parameters_Formal::classof(param_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Parameters::Formal(Formal::from_ffi(raw)) + } else if ffi::DWARF_parameters_TemplateValue::classof(param_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Parameters::TemplateValue(TemplateValue::from_ffi(raw)) + } else if ffi::DWARF_parameters_TemplateType::classof(param_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Parameters::TemplateType(TemplateType::from_ffi(raw)) + } else { + panic!("Unknown Parameter"); + } + } + } +} + +impl Parameter for Parameters<'_> { + fn get_base(&self) -> &ffi::DWARF_Parameter { + match &self { + Parameters::Formal(p) => p.get_base(), + Parameters::TemplateValue(p) => p.get_base(), + Parameters::TemplateType(p) => p.get_base(), + } + } +} + +pub struct Formal<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Formal<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Parameter for Formal<'_> { + fn get_base(&self) -> &ffi::DWARF_Parameter { + self.ptr.as_ref().unwrap().as_ref() + } +} + +pub struct TemplateValue<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for TemplateValue<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Parameter for TemplateValue<'_> { + fn get_base(&self) -> &ffi::DWARF_Parameter { + self.ptr.as_ref().unwrap().as_ref() + } +} + +pub struct TemplateType<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for TemplateType<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Parameter for TemplateType<'_> { + fn get_base(&self) -> &ffi::DWARF_Parameter { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Enum that represents the different type of locations for a parameters +pub enum Location<'a> { + /// Register location (e.g. `r8, x13`) + Register(RegisterLocation<'a>), +} + +impl FromFFI for Location<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let loc_ref = ffi_entry.as_ref().unwrap(); + + if ffi::DWARF_Parameter_RegisterLocation::classof(loc_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Location::Register(RegisterLocation::from_ffi(raw)) + } else { + panic!("Unknown Parameter"); + } + } + } +} + +/// Location as a register +pub struct RegisterLocation<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for RegisterLocation<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RegisterLocation<'_> { + /// DWARF id of the register (e.g. `DW_OP_reg0`) + pub fn id(&self) -> u64 { + self.ptr.id() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/scope.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/scope.rs new file mode 100644 index 0000000..b066538 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/scope.rs @@ -0,0 +1,84 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::common::into_optional; +use std::marker::PhantomData; + +/// This class materializes a scope in which Function, Variable, Type, ... +/// can be defined. +pub struct Scope<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Type { + UNION, + CLASS, + STRUCT, + NAMESPACE, + FUNCTION, + COMPILATION_UNIT, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Type::UNION, + 0x00000002 => Type::CLASS, + 0x00000003 => Type::STRUCT, + 0x00000004 => Type::NAMESPACE, + 0x00000005 => Type::FUNCTION, + 0x00000006 => Type::COMPILATION_UNIT, + _ => Type::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Type) -> u32 { + match value { + Type::UNION => 0x00000001, + Type::CLASS => 0x00000002, + Type::STRUCT => 0x00000003, + Type::NAMESPACE => 0x00000004, + Type::FUNCTION => 0x00000005, + Type::COMPILATION_UNIT => 0x00000006, + Type::UNKNOWN(_) => 0, + } + } +} + +impl FromFFI for Scope<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Scope<'_> { + /// Name of the scope. For instance namespace's name or function's name. + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Parent scope (if any) + pub fn parent(&self) -> Option> { + into_optional(self.ptr.parent()) + } + + /// The current scope type + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + + /// Represent the whole chain of all (parent) scopes using the provided + /// separator. E.g. `ns1::ns2::Class1::Struct2::Type` + pub fn chained(&self, sep: &str) -> String { + cxx::let_cxx_string!(__cxx_s = sep); + self.ptr.chained(&__cxx_s).to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types.rs new file mode 100644 index 0000000..ea199aa --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types.rs @@ -0,0 +1,548 @@ +use lief_ffi as ffi; + +use crate::{Error, common::FromFFI}; + +use crate::DeclOpt; +use crate::common::into_optional; +use crate::debug_location::DebugLocation; +use crate::declare_fwd_iterator; +use crate::dwarf::Scope; +use crate::to_conv_result; +use std::marker::PhantomData; + +pub mod array; +pub mod atomic; +pub mod base; +pub mod classlike; +pub mod coarray; +pub mod const_ty; +pub mod dynamic; +pub mod enum_type; +pub mod file; +pub mod immutable; +pub mod interface; +pub mod pointer; +pub mod pointer_to_member; +pub mod reference; +pub mod restrict; +pub mod rvalue_ref; +pub mod set_type; +pub mod shared; +pub mod string; +pub mod subroutine; +pub mod template_alias; +pub mod thrown; +pub mod typedef; +pub mod volatile; + +#[doc(inline)] +pub use classlike::Structure; + +#[doc(inline)] +pub use classlike::Class; + +#[doc(inline)] +pub use classlike::Union; + +#[doc(inline)] +pub use classlike::Packed; + +#[doc(inline)] +pub use classlike::ClassLike; + +#[doc(inline)] +pub use pointer::Pointer; + +#[doc(inline)] +pub use const_ty::Const; + +#[doc(inline)] +pub use base::Base; + +#[doc(inline)] +pub use array::Array; + +#[doc(inline)] +pub use typedef::Typedef; + +#[doc(inline)] +pub use atomic::Atomic; + +#[doc(inline)] +pub use coarray::Coarray; + +#[doc(inline)] +pub use dynamic::Dynamic; + +#[doc(inline)] +pub use file::File; + +#[doc(inline)] +pub use immutable::Immutable; + +#[doc(inline)] +pub use enum_type::Enum; + +#[doc(inline)] +pub use interface::Interface; + +#[doc(inline)] +pub use pointer_to_member::PointerToMember; + +#[doc(inline)] +pub use rvalue_ref::RValueReference; + +#[doc(inline)] +pub use reference::Reference; + +#[doc(inline)] +pub use restrict::Restrict; + +#[doc(inline)] +pub use set_type::SetTy; + +#[doc(inline)] +pub use shared::Shared; + +#[doc(inline)] +pub use string::StringTy; + +#[doc(inline)] +pub use subroutine::Subroutine; + +#[doc(inline)] +pub use template_alias::TemplateAlias; + +#[doc(inline)] +pub use thrown::Thrown; + +#[doc(inline)] +pub use volatile::Volatile; + +/// This enum represents a DWARF Type which includes: +/// +/// - `DW_TAG_array_type` +/// - `DW_TAG_atomic_type` +/// - `DW_TAG_base_type` +/// - `DW_TAG_class_type` +/// - `DW_TAG_coarray_type` +/// - `DW_TAG_const_type` +/// - `DW_TAG_dynamic_type` +/// - `DW_TAG_enumeration_type` +/// - `DW_TAG_file_type` +/// - `DW_TAG_immutable_type` +/// - `DW_TAG_interface_type` +/// - `DW_TAG_packed_type` +/// - `DW_TAG_pointer_type` +/// - `DW_TAG_ptr_to_member_type` +/// - `DW_TAG_reference_type` +/// - `DW_TAG_restrict_type` +/// - `DW_TAG_rvalue_reference_type` +/// - `DW_TAG_set_type` +/// - `DW_TAG_shared_type` +/// - `DW_TAG_string_type` +/// - `DW_TAG_structure_type` +/// - `DW_TAG_subroutine_type` +/// - `DW_TAG_template_alias` +/// - `DW_TAG_thrown_type` +/// - `DW_TAG_typedef` +/// - `DW_TAG_union_type` +/// - `DW_TAG_unspecified_type` +/// - `DW_TAG_volatile_type`d_type` +pub enum Type<'a> { + /// Interface over `DW_TAG_structure_type` + Structure(Structure<'a>), + + /// Interface over `DW_TAG_class_type` + Class(Class<'a>), + + /// Interface over `DW_TAG_union_type` + Union(Union<'a>), + + /// Interface over `DW_TAG_packed_type` + Packed(Packed<'a>), + + /// Interface over `DW_TAG_pointer_type` + Pointer(Pointer<'a>), + + /// Interface over `DW_TAG_const_type` + Const(Const<'a>), + + /// Interface over `DW_TAG_base_type` + Base(Base<'a>), + + /// Interface over `DW_TAG_array_type` + Array(Array<'a>), + + /// Interface over `DW_TAG_typedef` + Typedef(Typedef<'a>), + + /// Interface over `DW_TAG_atomic_type` + Atomic(Atomic<'a>), + + /// Interface over `DW_TAG_coarray_type` + Coarray(Coarray<'a>), + + /// Interface over `DW_TAG_dynamic_type` + Dynamic(Dynamic<'a>), + + /// Interface over `DW_TAG_enumeration_type` + Enum(Enum<'a>), + + /// Interface over `DW_TAG_file_type` + File(File<'a>), + + /// Interface over `DW_TAG_immutable_type` + Immutable(Immutable<'a>), + + /// Interface over `DW_TAG_interface_type` + Interface(Interface<'a>), + + /// Interface over `DW_TAG_ptr_to_member_type` + PointerToMember(PointerToMember<'a>), + + /// Interface over `DW_TAG_rvalue_reference_type` + RValueReference(RValueReference<'a>), + + /// Interface over `DW_TAG_reference_type` + Reference(Reference<'a>), + + /// Interface over `DW_TADW_TAG_restrict_type` + Restrict(Restrict<'a>), + + /// Interface over `DW_TAG_set_type` + SetTy(SetTy<'a>), + + /// Interface over `DW_TAG_shared_type` + Shared(Shared<'a>), + + /// Interface over `DW_TAG_string_type` + StringTy(StringTy<'a>), + + /// Interface over `DW_TAG_subroutine_type` + Subroutine(Subroutine<'a>), + + /// Interface over `DW_TAG_template_alias` + TemplateAlias(TemplateAlias<'a>), + + /// Interface over `DW_TAG_thrown_type` + Thrown(Thrown<'a>), + + /// Interface over `DW_TAG_volatile_type` + Volatile(Volatile<'a>), + + /// Generic type (fallback value) + Generic(Generic<'a>), +} + +impl FromFFI for Type<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let type_ref = ffi_entry.as_ref().unwrap(); + + if ffi::DWARF_types_Structure::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Structure(Structure::from_ffi(raw)) + } else if ffi::DWARF_types_Class::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Class(Class::from_ffi(raw)) + } else if ffi::DWARF_types_Union::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Union(Union::from_ffi(raw)) + } else if ffi::DWARF_types_Packed::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Packed(Packed::from_ffi(raw)) + } else if ffi::DWARF_types_Pointer::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Pointer(Pointer::from_ffi(raw)) + } else if ffi::DWARF_types_Const::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Const(Const::from_ffi(raw)) + } else if ffi::DWARF_types_Base::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Base(Base::from_ffi(raw)) + } else if ffi::DWARF_types_Array::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Array(Array::from_ffi(raw)) + } else if ffi::DWARF_types_Typedef::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Typedef(Typedef::from_ffi(raw)) + } else if ffi::DWARF_types_Atomic::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Atomic(Atomic::from_ffi(raw)) + } else if ffi::DWARF_types_Coarray::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Coarray(Coarray::from_ffi(raw)) + } else if ffi::DWARF_types_Dynamic::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Dynamic(Dynamic::from_ffi(raw)) + } else if ffi::DWARF_types_Enum::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Enum(Enum::from_ffi(raw)) + } else if ffi::DWARF_types_File::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::File(File::from_ffi(raw)) + } else if ffi::DWARF_types_Immutable::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Immutable(Immutable::from_ffi(raw)) + } else if ffi::DWARF_types_Interface::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Interface(Interface::from_ffi(raw)) + } else if ffi::DWARF_types_PointerToMember::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::PointerToMember(PointerToMember::from_ffi(raw)) + } else if ffi::DWARF_types_RValueReference::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::RValueReference(RValueReference::from_ffi(raw)) + } else if ffi::DWARF_types_Reference::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Reference(Reference::from_ffi(raw)) + } else if ffi::DWARF_types_Restrict::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Restrict(Restrict::from_ffi(raw)) + } else if ffi::DWARF_types_SetTy::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::SetTy(SetTy::from_ffi(raw)) + } else if ffi::DWARF_types_Shared::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Shared(Shared::from_ffi(raw)) + } else if ffi::DWARF_types_StringTy::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::StringTy(StringTy::from_ffi(raw)) + } else if ffi::DWARF_types_Subroutine::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Subroutine(Subroutine::from_ffi(raw)) + } else if ffi::DWARF_types_TemplateAlias::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::TemplateAlias(TemplateAlias::from_ffi(raw)) + } else if ffi::DWARF_types_Thrown::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Thrown(Thrown::from_ffi(raw)) + } else if ffi::DWARF_types_Volatile::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Volatile(Volatile::from_ffi(raw)) + } else { + Type::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +/// Generic structure for types that do not required a dedicated interface +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Generic<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +/// Generic trait shared by all DWARF types +pub trait DwarfType { + #[doc(hidden)] + fn get_base(&self) -> &ffi::DWARF_Type; + + /// Return the type's name using either `DW_AT_name` or `DW_AT_picture_string` (if any) + fn name(&self) -> Result { + to_conv_result!( + ffi::DWARF_Type::name, + self.get_base(), + |e: cxx::UniquePtr| { e.to_string() } + ); + } + + /// Return the size of the type or an error if it can't be computed. + /// + /// This size should match the equivalent of `sizeof(Type)`. + fn size(&self) -> Result { + to_conv_result!(ffi::DWARF_Type::size, self.get_base(), |e| e); + } + + /// Return the debug location where this type is defined. + fn location(&self) -> DebugLocation { + DebugLocation::from_ffi(self.get_base().location()) + } + + /// Whether this type is a `DW_TAG_unspecified_type`. + fn is_unspecified(&self) -> bool { + self.get_base().is_unspecified() + } + + /// The scope in which this function is defined + fn scope(&self) -> Option> { + into_optional(self.get_base().scope()) + } + + /// Generates a C/C++ definition for this type + fn to_decl(&self) -> String { + self.get_base().to_decl().to_string() + } + + /// Generates a C/C++ definition for this type with the given configuration + fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.get_base().to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +impl DwarfType for Generic<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap() + } +} + +impl DwarfType for Type<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + match &self { + Type::Structure(s) => s.get_base(), + Type::Class(s) => s.get_base(), + Type::Union(s) => s.get_base(), + Type::Packed(s) => s.get_base(), + Type::Pointer(s) => s.get_base(), + Type::Const(s) => s.get_base(), + Type::Base(s) => s.get_base(), + Type::Array(s) => s.get_base(), + Type::Typedef(s) => s.get_base(), + Type::Atomic(s) => s.get_base(), + Type::Coarray(s) => s.get_base(), + Type::Dynamic(s) => s.get_base(), + Type::Enum(s) => s.get_base(), + Type::File(s) => s.get_base(), + Type::Immutable(s) => s.get_base(), + Type::Interface(s) => s.get_base(), + Type::PointerToMember(s) => s.get_base(), + Type::RValueReference(s) => s.get_base(), + Type::Reference(s) => s.get_base(), + Type::Restrict(s) => s.get_base(), + Type::SetTy(s) => s.get_base(), + Type::Shared(s) => s.get_base(), + Type::StringTy(s) => s.get_base(), + Type::Subroutine(s) => s.get_base(), + Type::TemplateAlias(s) => s.get_base(), + Type::Thrown(s) => s.get_base(), + Type::Volatile(s) => s.get_base(), + Type::Generic(s) => s.get_base(), + } + } +} + +declare_fwd_iterator!( + Types, + Type<'a>, + ffi::DWARF_Type, + ffi::DWARF_CompilationUnit, + ffi::DWARF_CompilationUnit_it_types +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/array.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/array.rs new file mode 100644 index 0000000..6da5136 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/array.rs @@ -0,0 +1,77 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +use crate::dwarf::Type; + +/// This class represents a `DW_TAG_array_type` +pub struct Array<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Array<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Array<'_> { + /// The underlying type of this array + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } + + /// Return information about the size of this array. + /// + /// This size info is usually embedded in a `DW_TAG_subrange_type` DIE which + /// is represented by the [`SizeInfo`] structure. + pub fn size_info(&self) -> SizeInfo<'_> { + SizeInfo::from_ffi(self.ptr.size_info()) + } +} + +impl DwarfType for Array<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Structure that wraps information about the dimension of this array +pub struct SizeInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for SizeInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl SizeInfo<'_> { + /// Name of the index (usually not relevant like `__ARRAY_SIZE_TYPE__`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Size of the array. For instance in `uint8_t[3]`, it returns 3 + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Type of the **index** for this array. + /// + /// For instance in `uint8_t[3]` the index type could be set to a `size_t`. + pub fn get_type(&self) -> Option> { + into_optional(self.ptr.get_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/atomic.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/atomic.rs new file mode 100644 index 0000000..43a9fd8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/atomic.rs @@ -0,0 +1,33 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_atomic_type` +pub struct Atomic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Atomic<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Atomic<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Atomic<'_> { + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/base.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/base.rs new file mode 100644 index 0000000..f7d05b0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/base.rs @@ -0,0 +1,94 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This class wraps the `DW_TAG_base_type` type which can be used -- for +/// instance -- to represent integers or primitive types. +pub struct Base<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Encoding { + NONE, + + /// Mirror `DW_ATE_signed` + SIGNED, + + /// Mirror `DW_ATE_signed_char` + SIGNED_CHAR, + + /// Mirror `DW_ATE_unsigned` + UNSIGNED, + + /// Mirror `DW_ATE_unsigned_char` + UNSIGNED_CHAR, + + /// Mirror `DW_ATE_float` + FLOAT, + + /// Mirror `DW_ATE_boolean` + BOOLEAN, + + /// Mirror `DW_ATE_address` + ADDRESS, + + UNKNOWN(u32), +} + +impl From for Encoding { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Encoding::NONE, + 0x00000001 => Encoding::SIGNED, + 0x00000002 => Encoding::SIGNED_CHAR, + 0x00000003 => Encoding::UNSIGNED, + 0x00000004 => Encoding::UNSIGNED_CHAR, + 0x00000005 => Encoding::FLOAT, + 0x00000006 => Encoding::BOOLEAN, + 0x00000007 => Encoding::ADDRESS, + _ => Encoding::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Encoding) -> u32 { + match value { + Encoding::NONE => 0x00000000, + Encoding::SIGNED => 0x00000001, + Encoding::SIGNED_CHAR => 0x00000002, + Encoding::UNSIGNED => 0x00000003, + Encoding::UNSIGNED_CHAR => 0x00000004, + Encoding::FLOAT => 0x00000005, + Encoding::BOOLEAN => 0x00000006, + Encoding::ADDRESS => 0x00000007, + Encoding::UNKNOWN(_) => 0, + } + } +} + +impl FromFFI for Base<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Base<'_> { + /// Describe how the base type is encoded and should be interpreted + pub fn encoding(&self) -> Encoding { + Encoding::from(self.ptr.encoding()) + } +} + +impl DwarfType for Base<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/classlike.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/classlike.rs new file mode 100644 index 0000000..ff86ccc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/classlike.rs @@ -0,0 +1,211 @@ +use lief_ffi as ffi; + +use super::Type; +use crate::Error; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use crate::dwarf::Function; +use crate::dwarf::types::DwarfType; +use crate::to_result; +use std::marker::PhantomData; + +/// Trait shared by [`Structure`], [`Class`], [`Union`] or [`Packed`] +pub trait ClassLike { + #[doc(hidden)] + fn get_classlike(&self) -> &ffi::DWARF_types_ClassLike; + + /// Return this list of all the attributes defined in this class-like type + fn members(&self) -> Members<'_> { + Members::new(self.get_classlike().members()) + } + + /// Iterator over the functions defined by the class-like. + fn functions(&self) -> Functions<'_> { + Functions::new(self.get_classlike().functions()) + } +} + +pub struct Member<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Member<'_> { + /// Name of the member + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Offset of the current member in the struct/union/class + pub fn offset(&self) -> Result { + to_result!(ffi::DWARF_types_ClassLike_Member::offset, self); + } + + /// Offset of the current member in **bits** the struct/union/class + /// + /// This function differs from [`Member::offset`] for aggregates using bit-field + /// declaration: + /// + /// ```cpp + /// struct S { + /// int flag : 4; + /// int opt : 1 + /// }; + /// ``` + /// + /// Usually, `offset() * 8 == bit_offset()` + pub fn bit_offset(&self) -> Result { + to_result!(ffi::DWARF_types_ClassLike_Member::bit_offset, self); + } + + /// If the current member is a bit-field, this function returns its size in bits + pub fn bit_size(&self) -> Result { + to_result!(ffi::DWARF_types_ClassLike_Member::bit_size, self); + } + + /// Type of the current member + pub fn get_type(&self) -> Option> { + into_optional(self.ptr.get_type()) + } + + pub fn is_external(&self) -> bool { + self.ptr.is_external() + } + + pub fn is_declaration(&self) -> bool { + self.ptr.is_declaration() + } +} + +impl FromFFI for Member<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +/// This structure represents a `DW_TAG_structure_type` DWARF type +pub struct Structure<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Structure<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Structure<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl ClassLike for Structure<'_> { + fn get_classlike(&self) -> &ffi::DWARF_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This structure represents a `DW_TAG_union_type` DWARF type +pub struct Union<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Union<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Union<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl ClassLike for Union<'_> { + fn get_classlike(&self) -> &ffi::DWARF_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This structure represents a DWARF `packed` type (`DW_TAG_packed_type`) +pub struct Packed<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Packed<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Packed<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl ClassLike for Packed<'_> { + fn get_classlike(&self) -> &ffi::DWARF_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This structure represents a `DW_TAG_class_type` DWARF type +pub struct Class<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Class<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Class<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl ClassLike for Class<'_> { + fn get_classlike(&self) -> &ffi::DWARF_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_fwd_iterator!( + Members, + Member<'a>, + ffi::DWARF_types_ClassLike_Member, + ffi::DWARF_types_ClassLike, + ffi::DWARF_types_ClassLike_it_members +); + +declare_fwd_iterator!( + Functions, + Function<'a>, + ffi::DWARF_Function, + ffi::DWARF_types_ClassLike, + ffi::DWARF_types_ClassLike_it_functions +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/coarray.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/coarray.rs new file mode 100644 index 0000000..8f5e166 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/coarray.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_coarray_type` +pub struct Coarray<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Coarray<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Coarray<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/const_ty.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/const_ty.rs new file mode 100644 index 0000000..9a06189 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/const_ty.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This class represents a `DW_TAG_const_type` +pub struct Const<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Const<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Const<'_> { + /// The underlying type being const-ed by this type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} + +impl DwarfType for Const<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/dynamic.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/dynamic.rs new file mode 100644 index 0000000..3909db0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/dynamic.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_dynamic_type` +pub struct Dynamic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Dynamic<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Dynamic<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/enum_type.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/enum_type.rs new file mode 100644 index 0000000..85261d2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/enum_type.rs @@ -0,0 +1,81 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::types::{DwarfType, Type}; +use std::marker::PhantomData; + +use crate::{declare_fwd_iterator, to_opt}; + +/// This structure represents a `DW_TAG_enumeration_type` +pub struct Enum<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Enum<'_> { + /// Entries associated with this enum + pub fn entries(&self) -> Entries<'_> { + Entries::new(self.ptr.entries()) + } + + /// The underlying type that is used to encode this enum + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } + + /// Try to find the enum entry matching the given value + pub fn entry_by_value(&self, value: i64) -> Option> { + into_optional(self.ptr.find_entry(value)) + } +} + +impl FromFFI for Enum<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Enum<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This struct represents an enum entry which is essentially composed of a name and its value +/// (integer). +pub struct Entry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Entry<'_> { + /// Enum entry's name + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Enum entry's value + pub fn value(&self) -> Option { + to_opt!(&lief_ffi::DWARF_types_Enum_Entry::value, self); + } +} + +impl FromFFI for Entry<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +declare_fwd_iterator!( + Entries, + Entry<'a>, + ffi::DWARF_types_Enum_Entry, + ffi::DWARF_types_Enum, + ffi::DWARF_types_Enum_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/file.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/file.rs new file mode 100644 index 0000000..cc8faee --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/file.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_file_type` +pub struct File<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for File<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for File<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/immutable.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/immutable.rs new file mode 100644 index 0000000..e77a0ca --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/immutable.rs @@ -0,0 +1,33 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_immutable_type` +pub struct Immutable<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Immutable<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Immutable<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Immutable<'_> { + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/interface.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/interface.rs new file mode 100644 index 0000000..1dc3057 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/interface.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_interface_type` +pub struct Interface<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Interface<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Interface<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer.rs new file mode 100644 index 0000000..ea86819 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_pointer_type` DWARF type. +pub struct Pointer<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Pointer<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Pointer<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Pointer<'_> { + /// The type pointed by this pointer + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer_to_member.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer_to_member.rs new file mode 100644 index 0000000..d1ccc2c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/pointer_to_member.rs @@ -0,0 +1,39 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_interface_type` +pub struct PointerToMember<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for PointerToMember<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for PointerToMember<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PointerToMember<'_> { + /// The type of the member referenced by this pointer + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } + + /// The type that embeds this member + pub fn containing_type(&self) -> Option> { + into_optional(self.ptr.containing_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/reference.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/reference.rs new file mode 100644 index 0000000..0ab8f4f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/reference.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_reference_type` +pub struct Reference<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Reference<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Reference<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Reference<'_> { + /// The underlying type referenced by this ref-type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/restrict.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/restrict.rs new file mode 100644 index 0000000..ec0a358 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/restrict.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_restrict_type` +pub struct Restrict<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Restrict<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Restrict<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Restrict<'_> { + /// The underlying type referenced by this restrict-type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/rvalue_ref.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/rvalue_ref.rs new file mode 100644 index 0000000..0fd2d24 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/rvalue_ref.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_rvalue_reference_type` +pub struct RValueReference<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for RValueReference<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for RValueReference<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl RValueReference<'_> { + /// The type of the member referenced by this pointer + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/set_type.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/set_type.rs new file mode 100644 index 0000000..f771e37 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/set_type.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_set_type` +pub struct SetTy<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for SetTy<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for SetTy<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl SetTy<'_> { + /// The underlying type referenced by this set-type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/shared.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/shared.rs new file mode 100644 index 0000000..ef6380f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/shared.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_shared_type` +pub struct Shared<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Shared<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Shared<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Shared<'_> { + /// The underlying type referenced by this shared-type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/string.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/string.rs new file mode 100644 index 0000000..3125c6b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/string.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_string_type` +pub struct StringTy<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for StringTy<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for StringTy<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/subroutine.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/subroutine.rs new file mode 100644 index 0000000..94272b6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/subroutine.rs @@ -0,0 +1,49 @@ +use lief_ffi as ffi; + +use super::Type; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use crate::dwarf::Parameters; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_subroutine_type` +pub struct Subroutine<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Subroutine<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Subroutine<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Subroutine<'_> { + /// Return the [`Type`] associated with the **return type** of this function. + pub fn return_type(&self) -> Option> { + into_optional(self.ptr.return_type()) + } + + /// [`Parameters`] of this subroutine + pub fn parameters(&self) -> ParametersIt<'_> { + ParametersIt::new(self.ptr.parameters()) + } +} + +declare_fwd_iterator!( + ParametersIt, + Parameters<'a>, + ffi::DWARF_Parameter, + ffi::DWARF_types_Subroutine, + ffi::DWARF_types_Subroutine_it_parameters +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/template_alias.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/template_alias.rs new file mode 100644 index 0000000..04ab69c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/template_alias.rs @@ -0,0 +1,49 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use crate::dwarf::Parameters; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_template_alias` +pub struct TemplateAlias<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for TemplateAlias<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for TemplateAlias<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl TemplateAlias<'_> { + /// The underlying type aliased by this type. + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } + + /// [`Parameters`] associated with the underlying template + pub fn parameters(&self) -> ParametersIt<'_> { + ParametersIt::new(self.ptr.parameters()) + } +} + +declare_fwd_iterator!( + ParametersIt, + Parameters<'a>, + ffi::DWARF_Parameter, + ffi::DWARF_types_TemplateAlias, + ffi::DWARF_types_TemplateAlias_it_parameters +); diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/thrown.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/thrown.rs new file mode 100644 index 0000000..70e5f90 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/thrown.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_thrown_type` +pub struct Thrown<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Thrown<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Thrown<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Thrown<'_> { + /// The underlying type being thrown + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/typedef.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/typedef.rs new file mode 100644 index 0000000..0088399 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/typedef.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_typedef` DWARF type. +pub struct Typedef<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Typedef<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl DwarfType for Typedef<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Typedef<'_> { + /// The type aliased by this typedef + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/types/volatile.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/types/volatile.rs new file mode 100644 index 0000000..f6bfaa3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/types/volatile.rs @@ -0,0 +1,34 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::dwarf::Type; +use crate::dwarf::types::DwarfType; +use std::marker::PhantomData; + +/// This structure represents a `DW_TAG_volatile_type` +pub struct Volatile<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Volatile<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DwarfType for Volatile<'_> { + fn get_base(&self) -> &ffi::DWARF_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Volatile<'_> { + /// This underlying type + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/dwarf/variable.rs b/vendor/lief/api/rust/crates/lief/src/dwarf/variable.rs new file mode 100644 index 0000000..392123b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/dwarf/variable.rs @@ -0,0 +1,119 @@ +use lief_ffi as ffi; + +use super::Type; +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::dwarf::Scope; +use crate::{DebugLocation, DeclOpt}; +use crate::{Error, declare_fwd_iterator, to_result}; +use std::marker::PhantomData; + +/// This class represents a DWARF variable which can be owned by a +/// [`crate::dwarf::Function`] or a [`crate::dwarf::CompilationUnit`] +pub struct Variable<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Variable<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Variable<'_> { + /// Name of the variable (usually demangled) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// The name of the variable which is used for linking (`DW_AT_linkage_name`). + /// + /// This name differs from [`Variable::name`] as it is usually mangled. + pub fn linkage_name(&self) -> Option { + let name = self.ptr.name().to_string(); + if !name.is_empty() { + return Some(name); + } + None + } + + /// Address of the variable. + /// + /// If the variable is **static**, it returns the **virtual address** + /// where it is defined. + /// If the variable is stack-based, it returns the **relative offset** from + /// the frame based register. + /// + /// If the address can't be resolved, it returns an [`Error`]. + pub fn address(&self) -> Result { + to_result!(ffi::DWARF_Variable::address, self); + } + + /// Return the size of the variable (or an [`Error`] if it can't be + /// resolved). + /// + /// This size is defined by its type. + pub fn size(&self) -> Result { + to_result!(ffi::DWARF_Variable::size, self); + } + + /// Whether it's a `constexpr` variable + pub fn is_constexpr(&self) -> bool { + self.ptr.is_constexpr() + } + + /// Whether this variable is allocated on the stack + pub fn is_stack_based(&self) -> bool { + self.ptr.is_stack_based() + } + + /// The original source location where the variable is defined. + pub fn debug_location(&self) -> DebugLocation { + DebugLocation::from_ffi(self.ptr.debug_location()) + } + + /// Return the type of this variable + pub fn get_type(&self) -> Option> { + into_optional(self.ptr.get_type()) + } + + /// The scope in which this variable is defined + pub fn scope(&self) -> Option> { + into_optional(self.ptr.scope()) + } + + /// Description (`DW_AT_description`) of the variable or an empty string + pub fn description(&self) -> String { + self.ptr.description().to_string() + } + + /// Generates a C/C++ definition for this variable + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Generates a C/C++ definition for this variable with the given configuration + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Variables, + Variable<'a>, + ffi::DWARF_Variable, + ffi::DWARF_Function, + ffi::DWARF_Function_it_variables +); + +declare_fwd_iterator!( + CompilationUnitVariables, + Variable<'a>, + ffi::DWARF_Variable, + ffi::DWARF_CompilationUnit, + ffi::DWARF_CompilationUnit_it_variables +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf.rs b/vendor/lief/api/rust/crates/lief/src/elf.rs new file mode 100644 index 0000000..c0971bc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf.rs @@ -0,0 +1,181 @@ +//! Module for the ELF file format support in LIEF. +//! +//! The [`Binary`] structure exposes the main API to inspect an ELF file. It can be instantiated, +//! using either: [`crate::elf::parse`], [`crate::elf::Binary::parse`] or [`crate::Binary::parse`] +//! +//! ``` +//! let elf = lief::elf::parse("/bin/ls").unwrap(); +//! for section in elf.sections() { +//! println!("section: {}", section.name()); +//! } +//! ``` + +use crate::common::AsFFI; +use lief_ffi as ffi; +use std::path::Path; + +pub mod binary; +pub mod builder; +pub mod dynamic; +pub mod hash; +pub mod header; +pub mod note; +pub mod parser_config; +pub mod relocation; +pub mod section; +pub mod segment; +pub mod symbol; +pub mod symbol_versioning; + +#[doc(inline)] +pub use binary::Binary; + +#[doc(inline)] +pub use header::Header; + +#[doc(inline)] +pub use section::Section; + +#[doc(inline)] +pub use segment::Segment; + +#[doc(inline)] +pub use symbol::Symbol; + +#[doc(inline)] +pub use hash::Sysv as SysvHash; + +#[doc(inline)] +pub use hash::Gnu as GnuHash; + +#[doc(inline)] +pub use note::Notes; + +#[doc(inline)] +pub use dynamic::Entries as DynamicEntries; + +#[doc(inline)] +pub use relocation::Relocation; + +#[doc(inline)] +pub use symbol_versioning::{ + SymbolVersion, SymbolVersionAux, SymbolVersionAuxRequirement, SymbolVersionDefinition, + SymbolVersionRequirement, +}; + +#[doc(inline)] +pub use parser_config::Config as ParserConfig; + +/// Strategy used for relocating the PHDR table +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum PhdrReloc { + /// Let LIEF choose the best strategy + AUTO, + /// Shift content after the PHDR table (PIE binaries only) + PIE_SHIFT, + /// Relocate the PHDR after the first BSS-like segment + BSS_END, + /// Relocate at the end of the binary + BINARY_END, + /// Relocate between two LOAD segments + SEGMENT_GAP, + UNKNOWN(u32), +} + +impl From for PhdrReloc { + fn from(value: u32) -> Self { + match value { + 0 => PhdrReloc::AUTO, + 1 => PhdrReloc::PIE_SHIFT, + 2 => PhdrReloc::BSS_END, + 3 => PhdrReloc::BINARY_END, + 4 => PhdrReloc::SEGMENT_GAP, + _ => PhdrReloc::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: PhdrReloc) -> u32 { + match value { + PhdrReloc::AUTO => 0, + PhdrReloc::PIE_SHIFT => 1, + PhdrReloc::BSS_END => 2, + PhdrReloc::BINARY_END => 3, + PhdrReloc::SEGMENT_GAP => 4, + PhdrReloc::UNKNOWN(v) => v, + } + } +} + +/// Strategy for inserting a new section +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum SecInsertPos { + /// Let LIEF choose the best strategy + AUTO, + /// Insert after the last segment offset, before debug info + POST_SEGMENT, + /// Insert after the last section offset, at binary end + POST_SECTION, + UNKNOWN(u32), +} + +impl From for SecInsertPos { + fn from(value: u32) -> Self { + match value { + 0 => SecInsertPos::AUTO, + 1 => SecInsertPos::POST_SEGMENT, + 2 => SecInsertPos::POST_SECTION, + _ => SecInsertPos::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: SecInsertPos) -> u32 { + match value { + SecInsertPos::AUTO => 0, + SecInsertPos::POST_SEGMENT => 1, + SecInsertPos::POST_SECTION => 2, + SecInsertPos::UNKNOWN(v) => v, + } + } +} + +/// Parse an ELF file from the given filepath +pub fn parse>(path: P) -> Option { + Binary::parse(path) +} + +/// Parse an ELF file from the given filepath and configuration +pub fn parse_with_config>(path: P, config: &ParserConfig) -> Option { + Binary::parse_with_config(path, config) +} + +/// Parse an ELF binary from a memory dump located at `path` that was mapped at +/// the virtual address `addr` +pub fn parse_from_dump>(path: P, addr: u64) -> Option { + Binary::parse_from_dump(path, addr) +} + +/// Same as [`parse_from_dump`] but with a provided configuration +pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &ParserConfig, +) -> Option { + Binary::parse_from_dump_with_config(path, addr, config) +} + +/// Check that the layout of the given binary is correct +pub fn check_layout(binary: &Binary) -> Result<(), String> { + cxx::let_cxx_string!(error = ""); + unsafe { + if ffi::ELF_Utils::check_layout(binary.as_ffi(), error.as_mut().get_unchecked_mut()) { + return Ok(()); + } + } + Err(error.to_string()) +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/binary.rs b/vendor/lief/api/rust/crates/lief/src/elf/binary.rs new file mode 100644 index 0000000..475532b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/binary.rs @@ -0,0 +1,925 @@ +use std::mem::size_of; +use std::path::Path; +use std::pin::Pin; + +use num_traits::{Num, cast}; + +use lief_ffi as ffi; + +use super::builder::Config; +use super::dynamic::{self, DynamicEntries, Library}; +use super::hash::{Gnu, Sysv}; +use super::header::Header; +use super::note::ItNotes; +use super::parser_config::Config as ParserConfig; +use super::relocation::{ + DynamicRelocations, ObjectRelocations, PltGotRelocations, Relocation, Relocations, +}; +use super::section::{Section, Sections}; +use super::segment::{self, Segments}; +use super::symbol::{DynamicSymbols, ExportedSymbols, ImportedSymbols, SymtabSymbols}; +use super::symbol_versioning::{SymbolVersion, SymbolVersionDefinition, SymbolVersionRequirement}; +use super::{Segment, Symbol}; +use crate::Error; +use crate::elf::dynamic::DynamicEntry; + +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::generic; +use crate::{declare_iterator, to_conv_result, to_result, to_slice}; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum ElfClass { + Elf32, + Elf64, + Unknown, +} + +impl ElfClass { + const ELF_CLASS32: u32 = 1; + const ELF_CLASS64: u32 = 2; + + pub fn from_value(value: u32) -> Self { + match value { + Self::ELF_CLASS32 => ElfClass::Elf32, + Self::ELF_CLASS64 => ElfClass::Elf64, + _ => ElfClass::Unknown, + } + } +} + +/// Strategy used for relocating the PHDR table +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum PhdrReloc { + /// Let LIEF choose the best strategy + AUTO, + /// Shift content after the PHDR table (PIE binaries only) + PIE_SHIFT, + /// Relocate the PHDR after the first BSS-like segment + BSS_END, + /// Relocate at the end of the binary + BINARY_END, + /// Relocate between two LOAD segments + SEGMENT_GAP, + UNKNOWN(u32), +} + +impl From for PhdrReloc { + fn from(value: u32) -> Self { + match value { + 0 => PhdrReloc::AUTO, + 1 => PhdrReloc::PIE_SHIFT, + 2 => PhdrReloc::BSS_END, + 3 => PhdrReloc::BINARY_END, + 4 => PhdrReloc::SEGMENT_GAP, + _ => PhdrReloc::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: PhdrReloc) -> u32 { + match value { + PhdrReloc::AUTO => 0, + PhdrReloc::PIE_SHIFT => 1, + PhdrReloc::BSS_END => 2, + PhdrReloc::BINARY_END => 3, + PhdrReloc::SEGMENT_GAP => 4, + PhdrReloc::UNKNOWN(v) => v, + } + } +} + +/// Strategy for inserting a new section +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum SecInsertPos { + /// Let LIEF choose the best strategy + AUTO, + /// Insert after the last segment offset, before debug info + POST_SEGMENT, + /// Insert after the last section offset, at binary end + POST_SECTION, + UNKNOWN(u32), +} + +impl From for SecInsertPos { + fn from(value: u32) -> Self { + match value { + 0 => SecInsertPos::AUTO, + 1 => SecInsertPos::POST_SEGMENT, + 2 => SecInsertPos::POST_SECTION, + _ => SecInsertPos::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: SecInsertPos) -> u32 { + match value { + SecInsertPos::AUTO => 0, + SecInsertPos::POST_SEGMENT => 1, + SecInsertPos::POST_SECTION => 2, + SecInsertPos::UNKNOWN(v) => v, + } + } +} + +/// This is the main interface to read and write ELF binary attributes. +/// +/// Note that this structure implements the [`generic::Binary`] trait from which other generic +/// functions are exposed +pub struct Binary { + ptr: cxx::UniquePtr, +} + +impl std::fmt::Debug for Binary { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Binary") + .field("header", &self.header()) + .finish() + } +} + +impl FromFFI for Binary { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Binary { + /// Create a [`Binary`] from the given file path + pub fn parse>(path: P) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let bin = ffi::ELF_Binary::parse(&__cxx_s); + if bin.is_null() { + return None; + } + Some(Binary::from_ffi(bin)) + } + + /// Parse from a string file path and with a provided configuration + pub fn parse_with_config>(path: P, config: &ParserConfig) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::ELF_Binary::parse_with_config(&__cxx_s, &ffi_config); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Parse an ELF binary from a memory dump located at `path` that was mapped + /// at the virtual address `addr` + pub fn parse_from_dump>(path: P, addr: u64) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::ELF_Binary::parse_from_dump(&__cxx_s, addr); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Same as [`Binary::parse_from_dump`] but with a provided configuration + pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &ParserConfig, + ) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::ELF_Binary::parse_from_dump_with_config(&__cxx_s, addr, &ffi_config); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Return the main ELF header + pub fn header(&self) -> Header<'_> { + Header::from_ffi(self.ptr.header()) + } + + /// Return the size taken by the binary when loaded (virtual size) + pub fn virtual_size(&self) -> u64 { + self.ptr.virtual_size() + } + + /// Return the path to the ELF interpreter that is used to process the ELF information + /// once loaded by the kernel + pub fn interpreter(&self) -> String { + self.ptr.interpreter().to_string() + } + + /// Return sysv-hash information (if present) + pub fn sysv_hash(&self) -> Option> { + into_optional(self.ptr.sysv_hash()) + } + + /// Return GNU Hash info (if present) + pub fn gnu_hash(&self) -> Option> { + into_optional(self.ptr.gnu_hash()) + } + + /// Return an iterator over the [`crate::elf::Section`] of the binary + pub fn sections(&self) -> Sections<'_> { + Sections::new(self.ptr.sections()) + } + + /// Return an iterator over the [`crate::elf::Segment`] of the binary + pub fn segments(&self) -> Segments<'_> { + Segments::new(self.ptr.segments()) + } + + /// Return an iterator over the [`crate::elf::DynamicEntries`] of the binary + pub fn dynamic_entries(&self) -> DynamicEntries<'_> { + DynamicEntries::new(self.ptr.dynamic_entries()) + } + + /// Remove **all** dynamic entries with the given tag + pub fn remove_dynamic_entries_by_tag(&mut self, tag: dynamic::Tag) { + self.ptr + .as_mut() + .unwrap() + .remove_dynamic_entries_by_tag(tag.into()) + } + + /// Add the given dynamic entry and return the new entry + pub fn add_dynamic_entry(&mut self, entry: &dyn dynamic::DynamicEntry) -> dynamic::Entries<'_> { + dynamic::Entries::from_ffi( + self.ptr + .as_mut() + .unwrap() + .add_dynamic_entry(entry.as_base()), + ) + } + + /// Return an iterator over the dynamic [`crate::elf::Symbol`] of the binary + pub fn dynamic_symbols(&self) -> DynamicSymbols<'_> { + DynamicSymbols::new(self.ptr.dynamic_symbols()) + } + + /// Return an iterator over the **exported** [`crate::elf::Symbol`] of the binary + pub fn exported_symbols(&self) -> ExportedSymbols<'_> { + ExportedSymbols::new(self.ptr.exported_symbols()) + } + + /// Return an iterator over the **imported** [`crate::elf::Symbol`] of the binary + pub fn imported_symbols(&self) -> ImportedSymbols<'_> { + ImportedSymbols::new(self.ptr.imported_symbols()) + } + + /// Return an iterator over the symtab-debug [`crate::elf::Symbol`] of the binary + pub fn symtab_symbols(&self) -> SymtabSymbols<'_> { + SymtabSymbols::new(self.ptr.symtab_symbols()) + } + + /// Return an iterator over the [`crate::elf::SymbolVersion`] of the binary + pub fn symbols_version(&self) -> SymbolsVersion<'_> { + SymbolsVersion::new(self.ptr.symbols_version()) + } + + /// Return an iterator over the [`crate::elf::SymbolVersionRequirement`] of the binary + pub fn symbols_version_requirement(&self) -> SymbolsVersionRequirement<'_> { + SymbolsVersionRequirement::new(self.ptr.symbols_version_requirement()) + } + + /// Return an iterator over the [`crate::elf::SymbolVersionDefinition`] of the binary + pub fn symbols_version_definition(&self) -> SymbolsVersionDefinition<'_> { + SymbolsVersionDefinition::new(self.ptr.symbols_version_definition()) + } + + /// Return an iterator over the [`crate::elf::Notes`] of the binary + pub fn notes(&self) -> ItNotes<'_> { + ItNotes::new(self.ptr.notes()) + } + + /// Return an iterator over the `.plt.got` [`crate::elf::Relocation`] of the binary + pub fn pltgot_relocations(&self) -> PltGotRelocations<'_> { + PltGotRelocations::new(self.ptr.pltgot_relocations()) + } + + /// Return an iterator over the regular [`crate::elf::Relocation`] of the binary + pub fn dynamic_relocations(&self) -> DynamicRelocations<'_> { + DynamicRelocations::new(self.ptr.dynamic_relocations()) + } + + /// Return an iterator over the object-file (`.o`) [`crate::elf::Relocation`] + pub fn object_relocations(&self) -> ObjectRelocations<'_> { + ObjectRelocations::new(self.ptr.object_relocations()) + } + + /// Return an iterator over **all** [`crate::elf::Relocation`] of the binary + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// Try to find the ELF section with the given name + pub fn section_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.section_by_name(&__cxx_s)) + } + + /// Try to find the ELF relocation that takes place at the given address + pub fn relocation_by_addr(&self, address: u64) -> Option> { + into_optional(self.ptr.relocation_by_addr(address)) + } + + /// Try to find the `.plt.got` relocation for the given symbol name + pub fn relocation_for_symbol(&self, sym_name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = sym_name); + into_optional(self.ptr.relocation_for_symbol(&__cxx_s)) + } + + /// Try to find the symbol with the given name in the dynamic `.dynsym` table + pub fn dynamic_symbol_by_name(&self, sym_name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = sym_name); + into_optional(self.ptr.get_dynamic_symbol(&__cxx_s)) + } + + /// Try to find the symbol with the given name in the debug `.symtab` table + pub fn symtab_symbol_by_name(&self, sym_name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = sym_name); + into_optional(self.ptr.get_symtab_symbol(&__cxx_s)) + } + + /// Try to find the library (`DT_NEEDED`) with the given name + pub fn get_library(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.get_library(&__cxx_s)) + } + + /// Try to find the section that encompasses the given offset. `skip_nobits` can be used + /// to include (or not) the `SHT_NOTBIT` sections + pub fn section_from_offset(&self, offset: u64, skip_nobits: bool) -> Option> { + into_optional(self.ptr.section_from_offset(offset, skip_nobits)) + } + + /// Try to find the section that encompasses the given virtual address. `skip_nobits` can be used + /// to include (or not) the `SHT_NOTBIT` sections + pub fn section_from_virtual_address( + &self, + address: u64, + skip_nobits: bool, + ) -> Option> { + into_optional(self.ptr.section_from_virtual_address(address, skip_nobits)) + } + + /// Try to find the segment that encompasses the given virtual address + pub fn segment_from_virtual_address(&self, address: u64) -> Option> { + into_optional(self.ptr.segment_from_virtual_address(address)) + } + + /// Try to find the segment that encompasses the given offset + pub fn segment_from_offset(&self, offset: u64) -> Option> { + into_optional(self.ptr.segment_from_offset(offset)) + } + + /// Get a slice of the content at the given address. + pub fn content_from_virtual_address(&self, address: u64, size: u64) -> &[u8] { + to_slice!(self.ptr.get_content_from_virtual_address(address, size)); + } + + /// Convert the given virtual address into an offset + pub fn virtual_address_to_offset(&self, address: u64) -> Result { + to_result!(ffi::ELF_Binary::virtual_address_to_offset, &self, address); + } + + /// Return the array defined by the given tag (e.g. + /// [`dynamic::Tag::INIT_ARRAY`]) with relocations applied (if any) + pub fn get_relocated_dynamic_array(&self, tag: dynamic::Tag) -> Vec { + Vec::from( + self.ptr + .get_relocated_dynamic_array(u64::from(tag)) + .as_slice(), + ) + } + + /// True if the current binary is targeting Android + pub fn is_targeting_android(&self) -> bool { + self.ptr.is_targeting_android() + } + + /// Get the integer value at the given virtual address + pub fn get_int_from_virtual_address(&self, addr: u64) -> Result + where + T: Num + cast::FromPrimitive + cast::ToPrimitive, + { + // Can't be in the generic trait because of: + // > for a trait to be "object safe" it needs to allow building a vtable to allow the call + // > to be resolvable dynamically; for more information visit + // > https://doc.rust-lang.org/reference/items/traits.html#object-safety + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u8, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u8(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u16, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u16(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u32, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u32(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u64, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u64(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + Err(Error::NotSupported) + } + + /// Write back the current ELF binary into the file specified in parameter + pub fn write>(&mut self, output: P) { + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr.as_mut().unwrap().write(&__cxx_s); + } + + /// Write back the current ELF binary into the file specified in parameter with the + /// configuration provided in the second parameter. + pub fn write_with_config>(&mut self, output: P, config: Config) { + cxx::let_cxx_string!(__cxx_out = output.as_ref().to_str().unwrap()); + let cfg = config.to_ffi(); + self.ptr + .as_mut() + .unwrap() + .write_with_config(&__cxx_out, &cfg); + } + + /// Rebuild the current ELF binary and return the raw bytes. + /// + /// This is similar to [`Binary::write`] but instead of writing the result + /// into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes(&mut self) -> Vec { + Vec::from(self.ptr.as_mut().unwrap().write_to_bytes().as_slice()) + } + + /// Rebuild the current ELF binary with the configuration provided in the + /// parameter and return the raw bytes. + /// + /// This is similar to [`Binary::write_with_config`] but instead of writing + /// the result into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes_with_config(&mut self, config: Config) -> Vec { + let cfg = config.to_ffi(); + Vec::from( + self.ptr + .as_mut() + .unwrap() + .write_to_bytes_with_config(&cfg) + .as_slice(), + ) + } + + /// Add a library as dependency + pub fn add_library<'a>(&'a mut self, library: &str) -> Library<'a> { + cxx::let_cxx_string!(__cxx_s = library); + Library::from_ffi(self.ptr.as_mut().unwrap().add_library(&__cxx_s)) + } + + /// Iterator over the functions found in this binary + pub fn functions(&self) -> generic::Functions<'_> { + generic::Functions::new(self.ptr.functions()) + } + + /// Try to find the dynamic entry associated with the given tag + pub fn dynamic_entry_by_tag(&self, tag: dynamic::Tag) -> Option> { + into_optional(self.ptr.dynamic_entry_by_tag(tag.into())) + } + + /// Look for the segment with the given type. If there are multiple segment + /// with the same type, it returns the first one. + pub fn segment_by_type(&self, seg_type: segment::Type) -> Option> { + into_optional(self.ptr.segment_by_type(seg_type.into())) + } + + /// Remove the given dynamic entry + pub fn remove_dynamic_entry(&mut self, entry: impl dynamic::DynamicEntry) { + self.ptr.pin_mut().remove_dynamic_entry(entry.as_base()); + } + + /// Remove the dynamic entries matching the given predicate. + /// + /// The function returns the number of entries that have been deleted. + pub fn remove_dynamic_entry_if

(&mut self, predicate: P) -> usize + where + P: Fn(&dynamic::Entries) -> bool, + { + let entries = self + .dynamic_entries() + .filter(predicate) + .map(|e| e.as_base().raw_ptr()) + .collect::>(); + + let cnt = entries.len(); + + for ffi_entry in entries { + unsafe { + self.ptr.pin_mut().remove_dynamic_entry_from_ptr(ffi_entry); + } + } + cnt + } + + /// Remove the `DT_NEEDED` dependency with the given name + pub fn remove_library(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().remove_library(&__cxx_s); + } + + /// Add the provided segment to the binary. This function returns the + /// newly added segment which could define additional attributes like the virtual address. + pub fn add_segment(&mut self, segment: &Segment) -> Option> { + into_optional( + self.ptr + .pin_mut() + .add_segment(segment.ptr.as_ref().unwrap()), + ) + } + + /// Change the path to the interpreter + pub fn set_interpreter>(&mut self, interpreter: P) { + cxx::let_cxx_string!(__cxx_s = interpreter.as_ref().to_str().unwrap()); + self.ptr.pin_mut().set_interpreter(&__cxx_s); + } + + /// Try to find the SymbolVersionRequirement associated with the given library + /// name (e.g. `libc.so.6`) + pub fn find_version_requirement(&self, libname: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = libname.to_string()); + into_optional(self.ptr.find_version_requirement(&__cxx_s)) + } + + /// Deletes all required symbol versions linked to the specified library name. + /// The function returns true if the operation succeed, false otherwise. + /// + ///

+ /// To maintain consistency, this function also removes versions + /// associated with dynamic symbols that are linked to the specified + /// library name. + ///
+ pub fn remove_version_requirement(&mut self, libname: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = libname.to_string()); + self.ptr.pin_mut().remove_version_requirement(&__cxx_s) + } + + /// Remove the given segment. If `clear` is set, the original content of the + /// segment will be filled with zeros before removal. + pub fn remove_segment(&mut self, segment: Segment, clear: bool) { + self.ptr + .pin_mut() + .remove_segment(segment.ptr.as_ref().unwrap(), clear) + } + + /// Remove all segments associated with the given type. + /// + /// If `clear` is set, the original content of the segments will be filled + /// with zeros before removal. + pub fn remove_segments_by_type(&mut self, ty: segment::Type, clear: bool) { + self.ptr.pin_mut().remove_segments_by_type(ty.into(), clear) + } + + /// Return an iterator over all symbols (combined dynamic + symtab) + pub fn symbols(&self) -> AllSymbols<'_> { + AllSymbols::new(self.ptr.symbols()) + } + + /// Return all printable strings from the binary with a minimum length + pub fn strings(&self, min_size: u64) -> Vec { + self.ptr + .strings(min_size) + .iter() + .map(|s| s.to_string()) + .collect() + } + + /// Return the last offset used in binary according to sections table + pub fn last_offset_section(&self) -> u64 { + self.ptr.last_offset_section() + } + + /// Return the last offset used in binary according to segments table + pub fn last_offset_segment(&self) -> u64 { + self.ptr.last_offset_segment() + } + + /// Return the next virtual address available + pub fn next_virtual_address(&self) -> u64 { + self.ptr.next_virtual_address() + } + + /// Return the offset of the end of the binary on disk + pub fn eof_offset(&self) -> u64 { + self.ptr.eof_offset() + } + + /// Return the destructor functions (from `.fini_array`, `.dtors`, etc.) + pub fn dtor_functions(&self) -> generic::Functions<'_> { + generic::Functions::new(self.ptr.dtor_functions()) + } + + /// Return the overlay data + pub fn overlay(&self) -> &[u8] { + to_slice!(self.ptr.get_overlay()); + } + + /// Set the overlay data + pub fn set_overlay(&mut self, data: &[u8]) { + unsafe { + self.ptr + .pin_mut() + .set_overlay(data.as_ptr(), data.len() as u64); + } + } + + /// Check if the binary has a dynamic entry with the given tag + pub fn has_dynamic_entry_tag(&self, tag: dynamic::Tag) -> bool { + self.ptr.has_dynamic_entry_tag(tag.into()) + } + + /// Check if the binary has a segment with the given type + pub fn has_segment_type(&self, ty: segment::Type) -> bool { + self.ptr.has_segment_type(ty.into()) + } + + /// Check if the binary has a note with the given type + pub fn has_note_type(&self, ty: super::note::Type) -> bool { + self.ptr.has_note_type(ty.into()) + } + + /// Check if the binary has a section with the given type + pub fn has_section_type(&self, ty: super::section::Type) -> bool { + self.ptr.has_section_type(ty.into()) + } + + /// Try to find a note by its type + pub fn note_by_type(&self, ty: super::note::Type) -> Option> { + into_optional(self.ptr.get_note_by_type(ty.into())) + } + + /// Try to find a section by its type + pub fn section_by_type(&self, ty: super::section::Type) -> Option> { + into_optional(self.ptr.get_section_by_type(ty.into())) + } + + /// Check if the binary has a section with the given name + pub fn has_section(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_section(&__cxx_s) + } + + /// Check if the binary has a section that spans the given offset + pub fn has_section_with_offset(&self, offset: u64) -> bool { + self.ptr.has_section_with_offset(offset) + } + + /// Check if the binary has a section that spans the given virtual address + pub fn has_section_with_va(&self, va: u64) -> bool { + self.ptr.has_section_with_va(va) + } + + /// Check if the binary has a library dependency with the given name + pub fn has_library(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_library(&__cxx_s) + } + + /// Check if the binary has a dynamic symbol with the given name + pub fn has_dynamic_symbol(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_dynamic_symbol(&__cxx_s) + } + + /// Check if the binary has a symtab symbol with the given name + pub fn has_symtab_symbol(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_symtab_symbol(&__cxx_s) + } + + /// Return the index of the given name in the dynamic symbol table + pub fn dynsym_idx(&self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + let idx = self.ptr.dynsym_idx(&__cxx_s); + if idx < 0 { + return None; + } + Some(idx as u64) + } + + /// Return the index of the given name in the symtab symbol table, or -1 + pub fn symtab_idx(&self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + let idx = self.ptr.symtab_idx(&__cxx_s); + if idx < 0 { + return None; + } + Some(idx as u64) + } + + /// Patch the GOT/PLT entry for the given symbol name + pub fn patch_pltgot(&mut self, symbol_name: &str, address: u64) { + cxx::let_cxx_string!(__cxx_s = symbol_name.to_string()); + self.ptr.pin_mut().patch_pltgot_by_name(&__cxx_s, address); + } + + /// Add a section to the binary. If `loaded` is true, the section will be + /// added in a way that it is loaded in memory. `pos` controls where the + /// section is inserted. + pub fn add_section( + &mut self, + section: &Section, + loaded: bool, + pos: SecInsertPos, + ) -> Option> { + into_optional( + self.ptr + .pin_mut() + .add_section(section.as_ffi(), loaded, pos.into()), + ) + } + + /// Add a note to the binary + pub fn add_note(&mut self, note: &super::note::Notes) -> super::note::Notes<'_> { + super::note::Notes::from_ffi(self.ptr.pin_mut().add_note(note.as_ffi())) + } + + /// Add a dynamic relocation + pub fn add_dynamic_relocation(&mut self, reloc: &Relocation) -> Relocation<'_> { + Relocation::from_ffi(self.ptr.pin_mut().add_dynamic_relocation(reloc.as_ffi())) + } + + /// Add a `.plt.got` relocation + pub fn add_pltgot_relocation(&mut self, reloc: &Relocation) -> Relocation<'_> { + Relocation::from_ffi(self.ptr.pin_mut().add_pltgot_relocation(reloc.as_ffi())) + } + + /// Add a symbol to the `.symtab` table + pub fn add_symtab_symbol(&mut self, symbol: &Symbol) -> Symbol<'_> { + Symbol::from_ffi(self.ptr.pin_mut().add_symtab_symbol(symbol.as_ffi())) + } + + /// Add a symbol to the dynamic symbol table (`.dynsym`) + pub fn add_dynamic_symbol(&mut self, symbol: &Symbol) -> Symbol<'_> { + Symbol::from_ffi(self.ptr.pin_mut().add_dynamic_symbol(symbol.as_ffi())) + } + + /// Add an exported function with the given address and name + pub fn add_exported_function(&mut self, address: u64, name: &str) -> Symbol<'_> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Symbol::from_ffi(self.ptr.pin_mut().add_exported_function(address, &__cxx_s)) + } + + /// Export the symbol with the given name, optionally setting its value (can be 0) + pub fn export_symbol_by_name(&mut self, symbol_name: &str, value: u64) -> Symbol<'_> { + cxx::let_cxx_string!(__cxx_s = symbol_name.to_string()); + Symbol::from_ffi(self.ptr.pin_mut().export_symbol_by_name(&__cxx_s, value)) + } + + /// Export an existing symbol + pub fn export_symbol(&mut self, symbol: &Symbol) -> Symbol<'_> { + Symbol::from_ffi(self.ptr.pin_mut().export_symbol_obj(symbol.as_ffi())) + } + + /// Remove the symtab symbol with the given name + pub fn remove_symtab_symbol(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().remove_symtab_symbol_by_name(&__cxx_s); + } + + /// Remove the dynamic symbol with the given name + pub fn remove_dynamic_symbol(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().remove_dynamic_symbol_by_name(&__cxx_s); + } + + /// Remove the given section. If `clear` is set, the section content will be + /// filled with zeros before removal. + pub fn remove_section(&mut self, section: &Section, clear: bool) { + self.ptr.pin_mut().remove_section(section.as_ffi(), clear); + } + + /// Remove the given note + pub fn remove_note(&mut self, note: &super::note::Notes) { + self.ptr.pin_mut().remove_note(note.as_ffi()); + } + + /// Extend the given segment by `size` bytes + pub fn extend_segment(&mut self, segment: &Segment, size: u64) -> Option> { + into_optional( + self.ptr + .pin_mut() + .extend_segment(segment.ptr.as_ref().unwrap(), size), + ) + } + + /// Extend the given section by `size` bytes + pub fn extend_section(&mut self, section: &Section, size: u64) -> Option> { + into_optional(self.ptr.pin_mut().extend_section(section.as_ffi(), size)) + } + + /// Strip all debug symbols from the binary + pub fn strip(&mut self) { + self.ptr.pin_mut().strip(); + } + + /// Get the index of a section by its name. Returns `None` if not found. + pub fn section_idx_by_name(&self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + let idx = self.ptr.get_section_idx_by_name(&__cxx_s); + if idx < 0 { None } else { Some(idx as usize) } + } + + /// Get the index of the given section. Returns `None` if not found. + pub fn section_idx(&self, section: &Section) -> Option { + let idx = self.ptr.get_section_idx_by_section(section.as_ffi()); + if idx < 0 { None } else { Some(idx as usize) } + } + + /// Relocate the PHDR table using the given strategy. + /// Returns the new offset of the PHDR table. + pub fn relocate_phdr_table(&mut self, reloc_type: PhdrReloc) -> u64 { + self.ptr.pin_mut().relocate_phdr_table(reloc_type.into()) + } +} + +impl AsFFI for Binary { + fn as_ffi(&self) -> &ffi::ELF_Binary { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::ELF_Binary> { + self.ptr.pin_mut() + } +} + +impl generic::Binary for Binary { + fn as_generic(&self) -> &ffi::AbstractBinary { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractBinary> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractBinary + as *mut ffi::AbstractBinary) + .as_mut() + .unwrap() + }) + } + } +} + +declare_iterator!( + SymbolsVersion, + SymbolVersion<'a>, + ffi::ELF_SymbolVersion, + ffi::ELF_Binary, + ffi::ELF_Binary_it_symbols_version +); +declare_iterator!( + SymbolsVersionRequirement, + SymbolVersionRequirement<'a>, + ffi::ELF_SymbolVersionRequirement, + ffi::ELF_Binary, + ffi::ELF_Binary_it_symbols_version_requirement +); +declare_iterator!( + SymbolsVersionDefinition, + SymbolVersionDefinition<'a>, + ffi::ELF_SymbolVersionDefinition, + ffi::ELF_Binary, + ffi::ELF_Binary_it_symbols_version_definition +); +declare_iterator!( + AllSymbols, + Symbol<'a>, + ffi::ELF_Symbol, + ffi::ELF_Binary, + ffi::ELF_Binary_it_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/builder.rs b/vendor/lief/api/rust/crates/lief/src/elf/builder.rs new file mode 100644 index 0000000..8bdfea6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/builder.rs @@ -0,0 +1,130 @@ +use lief_ffi as ffi; + +/// Structure used to configure the [`crate::elf::Binary::write_with_config`] operation +#[derive(Debug)] +pub struct Config { + /// Rebuild `DT_HASH` + pub dt_hash: bool, + + /// Rebuild `DT_STRTAB` + pub dyn_str: bool, + + /// Rebuild `PT_DYNAMIC` segment + pub dynamic_section: bool, + + /// Rebuild `DT_FINI_ARRAY` + pub fini_array: bool, + + /// Rebuild `DT_GNU_HASH` + pub gnu_hash: bool, + + /// Rebuild `DT_INIT_ARRAY` + pub init_array: bool, + + /// Rebuild `PT_INTERPRETER` + pub interpreter: bool, + + /// Rebuild `DT_JMPREL` + pub jmprel: bool, + + /// Rebuild notes sections + pub notes: bool, + + /// Rebuild `DT_PREINIT_ARRAY` + pub preinit_array: bool, + + /// Rebuild `DT_RELR` + pub relr: bool, + + /// Rebuild `DT_ANDROID_REL[A]` + pub android_rela: bool, + + /// Rebuild `DT_REL[A]` + pub rela: bool, + + /// Rebuild `.symtab` + pub static_symtab: bool, + + /// Rebuild `DT_VERDEF` + pub sym_verdef: bool, + + /// Rebuild `DT_VERNEED` + pub sym_verneed: bool, + + /// Rebuild `DT_VERSYM` + pub sym_versym: bool, + + /// Rebuild `DT_SYMTAB` + pub symtab: bool, + + /// Rebuild the Coredump notes + pub coredump_notes: bool, + + /// Force to relocating all the ELF structures that are supported by LIEF (mostly for testing) + pub force_relocate: bool, + + /// Remove entries in `.gnu.version_r` if they are not associated with at least one version + pub keep_empty_version_requirement: bool, + + /// Skip relocating the `PT_DYNAMIC` segment (only relevant if [`Config::keep_empty_version_requirement`] is set) + pub skip_dynamic: bool, +} + +impl Default for Config { + fn default() -> Config { + Config { + dt_hash: true, + dyn_str: true, + dynamic_section: true, + fini_array: true, + gnu_hash: true, + init_array: true, + interpreter: true, + jmprel: true, + notes: false, + preinit_array: true, + relr: true, + android_rela: true, + rela: true, + static_symtab: true, + sym_verdef: true, + sym_verneed: true, + sym_versym: true, + symtab: true, + coredump_notes: true, + force_relocate: false, + keep_empty_version_requirement: false, + skip_dynamic: false, + } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> ffi::ELF_Binary_write_config_t { + ffi::ELF_Binary_write_config_t { + dt_hash: self.dt_hash, + dyn_str: self.dyn_str, + dynamic_section: self.dynamic_section, + fini_array: self.fini_array, + gnu_hash: self.gnu_hash, + init_array: self.init_array, + interpreter: self.interpreter, + jmprel: self.jmprel, + notes: self.notes, + preinit_array: self.preinit_array, + relr: self.relr, + android_rela: self.android_rela, + rela: self.rela, + static_symtab: self.static_symtab, + sym_verdef: self.sym_verdef, + sym_verneed: self.sym_verneed, + sym_versym: self.sym_versym, + symtab: self.symtab, + coredump_notes: self.coredump_notes, + force_relocate: self.force_relocate, + keep_empty_version_requirement: self.keep_empty_version_requirement, + skip_dynamic: self.skip_dynamic, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/dynamic.rs b/vendor/lief/api/rust/crates/lief/src/elf/dynamic.rs new file mode 100644 index 0000000..ce97cfd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/dynamic.rs @@ -0,0 +1,1316 @@ +use std::marker::PhantomData; + +use bitflags::bitflags; +use lief_ffi as ffi; +use std::pin::Pin; + +use crate::common::FromFFI; +use crate::declare_iterator; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Tag { + DT_NULL_, + NEEDED, + PLTRELSZ, + PLTGOT, + HASH, + STRTAB, + SYMTAB, + RELA, + RELASZ, + RELAENT, + STRSZ, + SYMENT, + INIT, + FINI, + SONAME, + RPATH, + SYMBOLIC, + REL, + RELSZ, + RELENT, + PLTREL, + DEBUG_TAG, + TEXTREL, + JMPREL, + BIND_NOW, + INIT_ARRAY, + FINI_ARRAY, + INIT_ARRAYSZ, + FINI_ARRAYSZ, + RUNPATH, + FLAGS, + PREINIT_ARRAY, + PREINIT_ARRAYSZ, + SYMTAB_SHNDX, + RELRSZ, + RELR, + RELRENT, + GNU_HASH, + TLSDESC_PLT, + TLSDESC_GOT, + RELACOUNT, + RELCOUNT, + FLAGS_1, + VERSYM, + VERDEF, + VERDEFNUM, + VERNEED, + VERNEEDNUM, + AUXILIARY, + FILTER, + ANDROID_REL_OFFSET, + ANDROID_REL_SIZE, + ANDROID_REL, + ANDROID_RELSZ, + ANDROID_RELA, + ANDROID_RELASZ, + ANDROID_RELR, + ANDROID_RELRSZ, + ANDROID_RELRENT, + ANDROID_RELRCOUNT, + MIPS_RLD_VERSION, + MIPS_TIME_STAMP, + MIPS_ICHECKSUM, + MIPS_IVERSION, + MIPS_FLAGS, + MIPS_BASE_ADDRESS, + MIPS_MSYM, + MIPS_CONFLICT, + MIPS_LIBLIST, + MIPS_LOCAL_GOTNO, + MIPS_CONFLICTNO, + MIPS_LIBLISTNO, + MIPS_SYMTABNO, + MIPS_UNREFEXTNO, + MIPS_GOTSYM, + MIPS_HIPAGENO, + MIPS_RLD_MAP, + MIPS_DELTA_CLASS, + MIPS_DELTA_CLASS_NO, + MIPS_DELTA_INSTANCE, + MIPS_DELTA_INSTANCE_NO, + MIPS_DELTA_RELOC, + MIPS_DELTA_RELOC_NO, + MIPS_DELTA_SYM, + MIPS_DELTA_SYM_NO, + MIPS_DELTA_CLASSSYM, + MIPS_DELTA_CLASSSYM_NO, + MIPS_CXX_FLAGS, + MIPS_PIXIE_INIT, + MIPS_SYMBOL_LIB, + MIPS_LOCALPAGE_GOTIDX, + MIPS_LOCAL_GOTIDX, + MIPS_HIDDEN_GOTIDX, + MIPS_PROTECTED_GOTIDX, + MIPS_OPTIONS, + MIPS_INTERFACE, + MIPS_DYNSTR_ALIGN, + MIPS_INTERFACE_SIZE, + MIPS_RLD_TEXT_RESOLVE_ADDR, + MIPS_PERF_SUFFIX, + MIPS_COMPACT_SIZE, + MIPS_GP_VALUE, + MIPS_AUX_DYNAMIC, + MIPS_PLTGOT, + MIPS_RWPLT, + MIPS_RLD_MAP_REL, + MIPS_XHASH, + AARCH64_BTI_PLT, + AARCH64_PAC_PLT, + AARCH64_VARIANT_PCS, + AARCH64_MEMTAG_MODE, + AARCH64_MEMTAG_HEAP, + AARCH64_MEMTAG_STACK, + AARCH64_MEMTAG_GLOBALS, + AARCH64_MEMTAG_GLOBALSSZ, + HEXAGON_SYMSZ, + HEXAGON_VER, + HEXAGON_PLT, + PPC_GOT, + PPC_OPT, + PPC64_GLINK, + PPC64_OPT, + RISCV_VARIANT_CC, + X86_64_PLT, + X86_64_PLTSZ, + X86_64_PLTENT, + IA_64_PLT_RESERVE, + IA_64_VMS_SUBTYPE, + IA_64_VMS_IMGIOCNT, + IA_64_VMS_LNKFLAGS, + IA_64_VMS_VIR_MEM_BLK_SIZ, + IA_64_VMS_IDENT, + IA_64_VMS_NEEDED_IDENT, + IA_64_VMS_IMG_RELA_CNT, + IA_64_VMS_SEG_RELA_CNT, + IA_64_VMS_FIXUP_RELA_CNT, + IA_64_VMS_FIXUP_NEEDED, + IA_64_VMS_SYMVEC_CNT, + IA_64_VMS_XLATED, + IA_64_VMS_STACKSIZE, + IA_64_VMS_UNWINDSZ, + IA_64_VMS_UNWIND_CODSEG, + IA_64_VMS_UNWIND_INFOSEG, + IA_64_VMS_LINKTIME, + IA_64_VMS_SEG_NO, + IA_64_VMS_SYMVEC_OFFSET, + IA_64_VMS_SYMVEC_SEG, + IA_64_VMS_UNWIND_OFFSET, + IA_64_VMS_UNWIND_SEG, + IA_64_VMS_STRTAB_OFFSET, + IA_64_VMS_SYSVER_OFFSET, + IA_64_VMS_IMG_RELA_OFF, + IA_64_VMS_SEG_RELA_OFF, + IA_64_VMS_FIXUP_RELA_OFF, + IA_64_VMS_PLTGOT_OFFSET, + IA_64_VMS_PLTGOT_SEG, + IA_64_VMS_FPMODE, + UNKNOWN(u64), +} + +impl From for Tag { + fn from(value: u64) -> Self { + match value { + 0x00000000 => Tag::DT_NULL_, + 0x00000001 => Tag::NEEDED, + 0x00000002 => Tag::PLTRELSZ, + 0x00000003 => Tag::PLTGOT, + 0x00000004 => Tag::HASH, + 0x00000005 => Tag::STRTAB, + 0x00000006 => Tag::SYMTAB, + 0x00000007 => Tag::RELA, + 0x00000008 => Tag::RELASZ, + 0x00000009 => Tag::RELAENT, + 0x0000000a => Tag::STRSZ, + 0x0000000b => Tag::SYMENT, + 0x0000000c => Tag::INIT, + 0x0000000d => Tag::FINI, + 0x0000000e => Tag::SONAME, + 0x0000000f => Tag::RPATH, + 0x00000010 => Tag::SYMBOLIC, + 0x00000011 => Tag::REL, + 0x00000012 => Tag::RELSZ, + 0x00000013 => Tag::RELENT, + 0x00000014 => Tag::PLTREL, + 0x00000015 => Tag::DEBUG_TAG, + 0x00000016 => Tag::TEXTREL, + 0x00000017 => Tag::JMPREL, + 0x00000018 => Tag::BIND_NOW, + 0x00000019 => Tag::INIT_ARRAY, + 0x0000001a => Tag::FINI_ARRAY, + 0x0000001b => Tag::INIT_ARRAYSZ, + 0x0000001c => Tag::FINI_ARRAYSZ, + 0x0000001d => Tag::RUNPATH, + 0x0000001e => Tag::FLAGS, + 0x00000020 => Tag::PREINIT_ARRAY, + 0x00000021 => Tag::PREINIT_ARRAYSZ, + 0x00000022 => Tag::SYMTAB_SHNDX, + 0x00000023 => Tag::RELRSZ, + 0x00000024 => Tag::RELR, + 0x00000025 => Tag::RELRENT, + 0x6ffffef5 => Tag::GNU_HASH, + 0x6ffffef6 => Tag::TLSDESC_PLT, + 0x6ffffef7 => Tag::TLSDESC_GOT, + 0x6ffffff9 => Tag::RELACOUNT, + 0x6ffffffa => Tag::RELCOUNT, + 0x6ffffffb => Tag::FLAGS_1, + 0x6ffffff0 => Tag::VERSYM, + 0x6ffffffc => Tag::VERDEF, + 0x6ffffffd => Tag::VERDEFNUM, + 0x6ffffffe => Tag::VERNEED, + 0x6fffffff => Tag::VERNEEDNUM, + 0x7ffffffd => Tag::AUXILIARY, + 0x7fffffff => Tag::FILTER, + 0x6000000d => Tag::ANDROID_REL_OFFSET, + 0x6000000e => Tag::ANDROID_REL_SIZE, + 0x6000000f => Tag::ANDROID_REL, + 0x60000010 => Tag::ANDROID_RELSZ, + 0x60000011 => Tag::ANDROID_RELA, + 0x60000012 => Tag::ANDROID_RELASZ, + 0x6fffe000 => Tag::ANDROID_RELR, + 0x6fffe001 => Tag::ANDROID_RELRSZ, + 0x6fffe003 => Tag::ANDROID_RELRENT, + 0x6fffe005 => Tag::ANDROID_RELRCOUNT, + 0x170000001 => Tag::MIPS_RLD_VERSION, + 0x170000002 => Tag::MIPS_TIME_STAMP, + 0x170000003 => Tag::MIPS_ICHECKSUM, + 0x170000004 => Tag::MIPS_IVERSION, + 0x170000005 => Tag::MIPS_FLAGS, + 0x170000006 => Tag::MIPS_BASE_ADDRESS, + 0x170000007 => Tag::MIPS_MSYM, + 0x170000008 => Tag::MIPS_CONFLICT, + 0x170000009 => Tag::MIPS_LIBLIST, + 0x17000000a => Tag::MIPS_LOCAL_GOTNO, + 0x17000000b => Tag::MIPS_CONFLICTNO, + 0x170000010 => Tag::MIPS_LIBLISTNO, + 0x170000011 => Tag::MIPS_SYMTABNO, + 0x170000012 => Tag::MIPS_UNREFEXTNO, + 0x170000013 => Tag::MIPS_GOTSYM, + 0x170000014 => Tag::MIPS_HIPAGENO, + 0x170000016 => Tag::MIPS_RLD_MAP, + 0x170000017 => Tag::MIPS_DELTA_CLASS, + 0x170000018 => Tag::MIPS_DELTA_CLASS_NO, + 0x170000019 => Tag::MIPS_DELTA_INSTANCE, + 0x17000001a => Tag::MIPS_DELTA_INSTANCE_NO, + 0x17000001b => Tag::MIPS_DELTA_RELOC, + 0x17000001c => Tag::MIPS_DELTA_RELOC_NO, + 0x17000001d => Tag::MIPS_DELTA_SYM, + 0x17000001e => Tag::MIPS_DELTA_SYM_NO, + 0x170000020 => Tag::MIPS_DELTA_CLASSSYM, + 0x170000021 => Tag::MIPS_DELTA_CLASSSYM_NO, + 0x170000022 => Tag::MIPS_CXX_FLAGS, + 0x170000023 => Tag::MIPS_PIXIE_INIT, + 0x170000024 => Tag::MIPS_SYMBOL_LIB, + 0x170000025 => Tag::MIPS_LOCALPAGE_GOTIDX, + 0x170000026 => Tag::MIPS_LOCAL_GOTIDX, + 0x170000027 => Tag::MIPS_HIDDEN_GOTIDX, + 0x170000028 => Tag::MIPS_PROTECTED_GOTIDX, + 0x170000029 => Tag::MIPS_OPTIONS, + 0x17000002a => Tag::MIPS_INTERFACE, + 0x17000002b => Tag::MIPS_DYNSTR_ALIGN, + 0x17000002c => Tag::MIPS_INTERFACE_SIZE, + 0x17000002d => Tag::MIPS_RLD_TEXT_RESOLVE_ADDR, + 0x17000002e => Tag::MIPS_PERF_SUFFIX, + 0x17000002f => Tag::MIPS_COMPACT_SIZE, + 0x170000030 => Tag::MIPS_GP_VALUE, + 0x170000031 => Tag::MIPS_AUX_DYNAMIC, + 0x170000032 => Tag::MIPS_PLTGOT, + 0x170000034 => Tag::MIPS_RWPLT, + 0x170000035 => Tag::MIPS_RLD_MAP_REL, + 0x170000036 => Tag::MIPS_XHASH, + 0x270000001 => Tag::AARCH64_BTI_PLT, + 0x270000003 => Tag::AARCH64_PAC_PLT, + 0x270000005 => Tag::AARCH64_VARIANT_PCS, + 0x270000009 => Tag::AARCH64_MEMTAG_MODE, + 0x27000000b => Tag::AARCH64_MEMTAG_HEAP, + 0x27000000c => Tag::AARCH64_MEMTAG_STACK, + 0x27000000d => Tag::AARCH64_MEMTAG_GLOBALS, + 0x27000000f => Tag::AARCH64_MEMTAG_GLOBALSSZ, + 0x370000000 => Tag::HEXAGON_SYMSZ, + 0x370000001 => Tag::HEXAGON_VER, + 0x370000002 => Tag::HEXAGON_PLT, + 0x470000000 => Tag::PPC_GOT, + 0x470000001 => Tag::PPC_OPT, + 0x570000000 => Tag::PPC64_GLINK, + 0x570000003 => Tag::PPC64_OPT, + 0x670000003 => Tag::RISCV_VARIANT_CC, + 0x770000000 => Tag::X86_64_PLT, + 0x770000001 => Tag::X86_64_PLTSZ, + 0x770000003 => Tag::X86_64_PLTENT, + 0x870000000 => Tag::IA_64_PLT_RESERVE, + 0x860000000 => Tag::IA_64_VMS_SUBTYPE, + 0x860000002 => Tag::IA_64_VMS_IMGIOCNT, + 0x860000008 => Tag::IA_64_VMS_LNKFLAGS, + 0x86000000a => Tag::IA_64_VMS_VIR_MEM_BLK_SIZ, + 0x86000000c => Tag::IA_64_VMS_IDENT, + 0x860000010 => Tag::IA_64_VMS_NEEDED_IDENT, + 0x860000012 => Tag::IA_64_VMS_IMG_RELA_CNT, + 0x860000014 => Tag::IA_64_VMS_SEG_RELA_CNT, + 0x860000016 => Tag::IA_64_VMS_FIXUP_RELA_CNT, + 0x860000018 => Tag::IA_64_VMS_FIXUP_NEEDED, + 0x86000001a => Tag::IA_64_VMS_SYMVEC_CNT, + 0x86000001e => Tag::IA_64_VMS_XLATED, + 0x860000020 => Tag::IA_64_VMS_STACKSIZE, + 0x860000022 => Tag::IA_64_VMS_UNWINDSZ, + 0x860000024 => Tag::IA_64_VMS_UNWIND_CODSEG, + 0x860000026 => Tag::IA_64_VMS_UNWIND_INFOSEG, + 0x860000028 => Tag::IA_64_VMS_LINKTIME, + 0x86000002a => Tag::IA_64_VMS_SEG_NO, + 0x86000002c => Tag::IA_64_VMS_SYMVEC_OFFSET, + 0x86000002e => Tag::IA_64_VMS_SYMVEC_SEG, + 0x860000030 => Tag::IA_64_VMS_UNWIND_OFFSET, + 0x860000032 => Tag::IA_64_VMS_UNWIND_SEG, + 0x860000034 => Tag::IA_64_VMS_STRTAB_OFFSET, + 0x860000036 => Tag::IA_64_VMS_SYSVER_OFFSET, + 0x860000038 => Tag::IA_64_VMS_IMG_RELA_OFF, + 0x86000003a => Tag::IA_64_VMS_SEG_RELA_OFF, + 0x86000003c => Tag::IA_64_VMS_FIXUP_RELA_OFF, + 0x86000003e => Tag::IA_64_VMS_PLTGOT_OFFSET, + 0x860000040 => Tag::IA_64_VMS_PLTGOT_SEG, + 0x860000042 => Tag::IA_64_VMS_FPMODE, + _ => Tag::UNKNOWN(value), + } + } +} + +impl From for u64 { + fn from(value: Tag) -> u64 { + match value { + Tag::DT_NULL_ => 0x00000000, + Tag::NEEDED => 0x00000001, + Tag::PLTRELSZ => 0x00000002, + Tag::PLTGOT => 0x00000003, + Tag::HASH => 0x00000004, + Tag::STRTAB => 0x00000005, + Tag::SYMTAB => 0x00000006, + Tag::RELA => 0x00000007, + Tag::RELASZ => 0x00000008, + Tag::RELAENT => 0x00000009, + Tag::STRSZ => 0x0000000a, + Tag::SYMENT => 0x0000000b, + Tag::INIT => 0x0000000c, + Tag::FINI => 0x0000000d, + Tag::SONAME => 0x0000000e, + Tag::RPATH => 0x0000000f, + Tag::SYMBOLIC => 0x00000010, + Tag::REL => 0x00000011, + Tag::RELSZ => 0x00000012, + Tag::RELENT => 0x00000013, + Tag::PLTREL => 0x00000014, + Tag::DEBUG_TAG => 0x00000015, + Tag::TEXTREL => 0x00000016, + Tag::JMPREL => 0x00000017, + Tag::BIND_NOW => 0x00000018, + Tag::INIT_ARRAY => 0x00000019, + Tag::FINI_ARRAY => 0x0000001a, + Tag::INIT_ARRAYSZ => 0x0000001b, + Tag::FINI_ARRAYSZ => 0x0000001c, + Tag::RUNPATH => 0x0000001d, + Tag::FLAGS => 0x0000001e, + Tag::PREINIT_ARRAY => 0x00000020, + Tag::PREINIT_ARRAYSZ => 0x00000021, + Tag::SYMTAB_SHNDX => 0x00000022, + Tag::RELRSZ => 0x00000023, + Tag::RELR => 0x00000024, + Tag::RELRENT => 0x00000025, + Tag::GNU_HASH => 0x6ffffef5, + Tag::TLSDESC_PLT => 0x6ffffef6, + Tag::TLSDESC_GOT => 0x6ffffef7, + Tag::RELACOUNT => 0x6ffffff9, + Tag::RELCOUNT => 0x6ffffffa, + Tag::FLAGS_1 => 0x6ffffffb, + Tag::VERSYM => 0x6ffffff0, + Tag::VERDEF => 0x6ffffffc, + Tag::VERDEFNUM => 0x6ffffffd, + Tag::VERNEED => 0x6ffffffe, + Tag::VERNEEDNUM => 0x6fffffff, + Tag::AUXILIARY => 0x7ffffffd, + Tag::FILTER => 0x7fffffff, + Tag::ANDROID_REL_OFFSET => 0x6000000d, + Tag::ANDROID_REL_SIZE => 0x6000000e, + Tag::ANDROID_REL => 0x6000000f, + Tag::ANDROID_RELSZ => 0x60000010, + Tag::ANDROID_RELA => 0x60000011, + Tag::ANDROID_RELASZ => 0x60000012, + Tag::ANDROID_RELR => 0x6fffe000, + Tag::ANDROID_RELRSZ => 0x6fffe001, + Tag::ANDROID_RELRENT => 0x6fffe003, + Tag::ANDROID_RELRCOUNT => 0x6fffe005, + Tag::MIPS_RLD_VERSION => 0x170000001, + Tag::MIPS_TIME_STAMP => 0x170000002, + Tag::MIPS_ICHECKSUM => 0x170000003, + Tag::MIPS_IVERSION => 0x170000004, + Tag::MIPS_FLAGS => 0x170000005, + Tag::MIPS_BASE_ADDRESS => 0x170000006, + Tag::MIPS_MSYM => 0x170000007, + Tag::MIPS_CONFLICT => 0x170000008, + Tag::MIPS_LIBLIST => 0x170000009, + Tag::MIPS_LOCAL_GOTNO => 0x17000000a, + Tag::MIPS_CONFLICTNO => 0x17000000b, + Tag::MIPS_LIBLISTNO => 0x170000010, + Tag::MIPS_SYMTABNO => 0x170000011, + Tag::MIPS_UNREFEXTNO => 0x170000012, + Tag::MIPS_GOTSYM => 0x170000013, + Tag::MIPS_HIPAGENO => 0x170000014, + Tag::MIPS_RLD_MAP => 0x170000016, + Tag::MIPS_DELTA_CLASS => 0x170000017, + Tag::MIPS_DELTA_CLASS_NO => 0x170000018, + Tag::MIPS_DELTA_INSTANCE => 0x170000019, + Tag::MIPS_DELTA_INSTANCE_NO => 0x17000001a, + Tag::MIPS_DELTA_RELOC => 0x17000001b, + Tag::MIPS_DELTA_RELOC_NO => 0x17000001c, + Tag::MIPS_DELTA_SYM => 0x17000001d, + Tag::MIPS_DELTA_SYM_NO => 0x17000001e, + Tag::MIPS_DELTA_CLASSSYM => 0x170000020, + Tag::MIPS_DELTA_CLASSSYM_NO => 0x170000021, + Tag::MIPS_CXX_FLAGS => 0x170000022, + Tag::MIPS_PIXIE_INIT => 0x170000023, + Tag::MIPS_SYMBOL_LIB => 0x170000024, + Tag::MIPS_LOCALPAGE_GOTIDX => 0x170000025, + Tag::MIPS_LOCAL_GOTIDX => 0x170000026, + Tag::MIPS_HIDDEN_GOTIDX => 0x170000027, + Tag::MIPS_PROTECTED_GOTIDX => 0x170000028, + Tag::MIPS_OPTIONS => 0x170000029, + Tag::MIPS_INTERFACE => 0x17000002a, + Tag::MIPS_DYNSTR_ALIGN => 0x17000002b, + Tag::MIPS_INTERFACE_SIZE => 0x17000002c, + Tag::MIPS_RLD_TEXT_RESOLVE_ADDR => 0x17000002d, + Tag::MIPS_PERF_SUFFIX => 0x17000002e, + Tag::MIPS_COMPACT_SIZE => 0x17000002f, + Tag::MIPS_GP_VALUE => 0x170000030, + Tag::MIPS_AUX_DYNAMIC => 0x170000031, + Tag::MIPS_PLTGOT => 0x170000032, + Tag::MIPS_RWPLT => 0x170000034, + Tag::MIPS_RLD_MAP_REL => 0x170000035, + Tag::MIPS_XHASH => 0x170000036, + Tag::AARCH64_BTI_PLT => 0x270000001, + Tag::AARCH64_PAC_PLT => 0x270000003, + Tag::AARCH64_VARIANT_PCS => 0x270000005, + Tag::AARCH64_MEMTAG_MODE => 0x270000009, + Tag::AARCH64_MEMTAG_HEAP => 0x27000000b, + Tag::AARCH64_MEMTAG_STACK => 0x27000000c, + Tag::AARCH64_MEMTAG_GLOBALS => 0x27000000d, + Tag::AARCH64_MEMTAG_GLOBALSSZ => 0x27000000f, + Tag::HEXAGON_SYMSZ => 0x370000000, + Tag::HEXAGON_VER => 0x370000001, + Tag::HEXAGON_PLT => 0x370000002, + Tag::PPC_GOT => 0x470000000, + Tag::PPC_OPT => 0x470000001, + Tag::PPC64_GLINK => 0x570000000, + Tag::PPC64_OPT => 0x570000003, + Tag::RISCV_VARIANT_CC => 0x670000003, + Tag::X86_64_PLT => 0x770000000, + Tag::X86_64_PLTSZ => 0x770000001, + Tag::X86_64_PLTENT => 0x770000003, + Tag::IA_64_PLT_RESERVE => 0x870000000, + Tag::IA_64_VMS_SUBTYPE => 0x860000000, + Tag::IA_64_VMS_IMGIOCNT => 0x860000002, + Tag::IA_64_VMS_LNKFLAGS => 0x860000008, + Tag::IA_64_VMS_VIR_MEM_BLK_SIZ => 0x86000000a, + Tag::IA_64_VMS_IDENT => 0x86000000c, + Tag::IA_64_VMS_NEEDED_IDENT => 0x860000010, + Tag::IA_64_VMS_IMG_RELA_CNT => 0x860000012, + Tag::IA_64_VMS_SEG_RELA_CNT => 0x860000014, + Tag::IA_64_VMS_FIXUP_RELA_CNT => 0x860000016, + Tag::IA_64_VMS_FIXUP_NEEDED => 0x860000018, + Tag::IA_64_VMS_SYMVEC_CNT => 0x86000001a, + Tag::IA_64_VMS_XLATED => 0x86000001e, + Tag::IA_64_VMS_STACKSIZE => 0x860000020, + Tag::IA_64_VMS_UNWINDSZ => 0x860000022, + Tag::IA_64_VMS_UNWIND_CODSEG => 0x860000024, + Tag::IA_64_VMS_UNWIND_INFOSEG => 0x860000026, + Tag::IA_64_VMS_LINKTIME => 0x860000028, + Tag::IA_64_VMS_SEG_NO => 0x86000002a, + Tag::IA_64_VMS_SYMVEC_OFFSET => 0x86000002c, + Tag::IA_64_VMS_SYMVEC_SEG => 0x86000002e, + Tag::IA_64_VMS_UNWIND_OFFSET => 0x860000030, + Tag::IA_64_VMS_UNWIND_SEG => 0x860000032, + Tag::IA_64_VMS_STRTAB_OFFSET => 0x860000034, + Tag::IA_64_VMS_SYSVER_OFFSET => 0x860000036, + Tag::IA_64_VMS_IMG_RELA_OFF => 0x860000038, + Tag::IA_64_VMS_SEG_RELA_OFF => 0x86000003a, + Tag::IA_64_VMS_FIXUP_RELA_OFF => 0x86000003c, + Tag::IA_64_VMS_PLTGOT_OFFSET => 0x86000003e, + Tag::IA_64_VMS_PLTGOT_SEG => 0x860000040, + Tag::IA_64_VMS_FPMODE => 0x860000042, + Tag::UNKNOWN(value) => value, + } + } +} + +#[derive(Debug)] +/// Enum that represents the different variants of a dynamic entry +pub enum Entries<'a> { + /// Entry for `DT_NEEDED` + Library(Library<'a>), + + /// Entry for `DT_INIT_ARRAY, DT_FINI_ARRAY`, ... + Array(Array<'a>), + + /// Entry for `DT_RPATH` + Rpath(Rpath<'a>), + + /// Entry for `DT_RUNPATH` + RunPath(RunPath<'a>), + + /// Entry for `DT_SONAME` + SharedObject(SharedObject<'a>), + + /// Entry for `DT_AUXILIARY` + Auxiliary(Auxiliary<'a>), + + /// Entry for `DT_FILTER` + Filter(Filter<'a>), + + /// Entry for `DT_FLAGS` and `DT_FLAGS_1` + Flags(Flags<'a>), + + /// Generic value + Generic(Generic<'a>), +} + +impl Entries<'_> { + /// Create a new dynamic entry with the given Tag + pub fn with_tag(tag: Tag) -> Entries<'static> { + Entries::from_ffi(lief_ffi::ELF_DynamicEntry::create(tag.into())) + } +} + +/// Trait shared by all the [`Entries`] +pub trait DynamicEntry { + #[doc(hidden)] + fn as_base(&self) -> &ffi::ELF_DynamicEntry; + + #[doc(hidden)] + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry>; + + /// Dynamic TAG associated with the entry + fn tag(&self) -> Tag { + Tag::from(self.as_base().tag()) + } + + /// Raw value which should be interpreted according to the [`DynamicEntry::tag`] + fn value(&self) -> u64 { + self.as_base().value() + } + + fn set_value(&mut self, value: u64) { + self.as_mut_base().set_value(value); + } +} + +impl std::fmt::Display for &dyn DynamicEntry { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_base().to_string()) + } +} + +impl DynamicEntry for Entries<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + match &self { + Entries::Library(entry) => entry.as_base(), + + Entries::Array(entry) => entry.as_base(), + + Entries::Rpath(entry) => entry.as_base(), + + Entries::RunPath(entry) => entry.as_base(), + + Entries::SharedObject(entry) => entry.as_base(), + + Entries::Auxiliary(entry) => entry.as_base(), + + Entries::Filter(entry) => entry.as_base(), + + Entries::Flags(entry) => entry.as_base(), + + Entries::Generic(entry) => entry.as_base(), + } + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + match self { + Entries::Library(entry) => entry.as_mut_base(), + + Entries::Array(entry) => entry.as_mut_base(), + + Entries::Rpath(entry) => entry.as_mut_base(), + + Entries::RunPath(entry) => entry.as_mut_base(), + + Entries::SharedObject(entry) => entry.as_mut_base(), + + Entries::Auxiliary(entry) => entry.as_mut_base(), + + Entries::Filter(entry) => entry.as_mut_base(), + + Entries::Flags(entry) => entry.as_mut_base(), + + Entries::Generic(entry) => entry.as_mut_base(), + } + } +} + +impl FromFFI for Entries<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::ELF_DynamicEntryLibrary::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Library(Library::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryArray::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Array(Array::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryRpath::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Rpath(Rpath::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryRunPath::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::RunPath(RunPath::from_ffi(raw)) + } else if ffi::ELF_DynamicSharedObject::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::SharedObject(SharedObject::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryAuxiliary::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Auxiliary(Auxiliary::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryFilter::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Filter(Filter::from_ffi(raw)) + } else if ffi::ELF_DynamicEntryFlags::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Flags(Flags::from_ffi(raw)) + } else { + Entries::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +/// Generic structure for the dynamic entries whose [`DynamicEntry::value`] can be interpreted +/// as is. +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl FromFFI for Generic<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Generic<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Generic").finish() + } +} + +/// Structure that represents a dynamic entry associated with a library name (e.g. `DT_NEEDED`) +pub struct Library<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Library<'_> { + /// Name of the library (e.g. `libc.so.6`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Set a new library name + pub fn set_name(&mut self, new_name: &str) { + cxx::let_cxx_string!(__cxx_s = new_name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } +} + +impl FromFFI for Library<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Library<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Library<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Library").finish() + } +} + +/// Structure that represents a dynamic entry associated with an array (e.g. `DT_INIT_ARRAY`) +pub struct Array<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Array<'_> { + pub fn array(&self) -> Vec { + Vec::from(self.ptr.array().as_slice()) + } +} + +impl FromFFI for Array<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Array<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Array<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Array").finish() + } +} + +/// Structure that represents a dynamic entry associated with the rpath info +pub struct Rpath<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Rpath<'_> { + /// Create a new Rpath entry with the given path(s) + /// + /// For instance: + /// + /// ``` + /// Rpath::new("$ORIGIN/../:/lib64") + /// ``` + pub fn new(value: &str) -> Rpath<'static> { + cxx::let_cxx_string!(__cxx_s = value.to_string()); + Rpath::from_ffi(lief_ffi::ELF_DynamicEntryRpath::create(&__cxx_s)) + } + + /// Create a new Rpath entry from a slice of paths + /// + /// For instance: + /// + /// ``` + /// Rpath::with_paths(&vec!["$ORIGIN/../", "/lib64"]) + /// ``` + pub fn with_paths(values: &[&str]) -> Rpath<'static> { + Rpath::new(&values.join(":")) + } + + /// The actual rpath as a string + pub fn rpath(&self) -> String { + self.ptr.rpath().to_string() + } + + /// Change the rpath value + pub fn set_rpath(&mut self, value: &str) { + cxx::let_cxx_string!(__cxx_s = value.to_string()); + self.ptr.pin_mut().set_rpath(&__cxx_s); + } + + /// Change the rpath value with the given slice + pub fn set_rpath_with_value(&mut self, values: &[&str]) { + cxx::let_cxx_string!(__cxx_s = values.join(":")); + self.ptr.pin_mut().set_rpath(&__cxx_s); + } + + /// The specified paths as a list of string + pub fn paths(&self) -> Vec { + let mut result = Vec::new(); + for entry in self.ptr.paths().into_iter() { + result.push(entry.to_string()); + } + result + } + + /// Insert a `path` at the given `position` + pub fn insert(&mut self, pos: u32, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().insert(pos, &__cxx_s); + } + + /// Append the given path + pub fn append(&mut self, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().append(&__cxx_s); + } + + /// The given path + pub fn remove(&mut self, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().remove(&__cxx_s); + } +} + +impl FromFFI for Rpath<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Rpath<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Rpath<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Rpath").finish() + } +} + +/// Structure that represents a dynamic entry associated with the runpath info +pub struct RunPath<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl RunPath<'_> { + /// Create a new RunPath entry with the given path(s) + /// + /// For instance: + /// + /// ``` + /// RunPath::new("$ORIGIN/../:/lib64") + /// ``` + pub fn new(value: &str) -> RunPath<'static> { + cxx::let_cxx_string!(__cxx_s = value.to_string()); + RunPath::from_ffi(lief_ffi::ELF_DynamicEntryRunPath::create(&__cxx_s)) + } + + /// Create a new RunPath entry from a slice of paths + /// + /// For instance: + /// + /// ``` + /// RunPath::with_paths(&vec!["$ORIGIN/../", "/lib64"]) + /// ``` + pub fn with_paths(values: &[&str]) -> RunPath<'static> { + RunPath::new(&values.join(":")) + } + + pub fn runpath(&self) -> String { + self.ptr.runpath().to_string() + } + + /// The specified paths as a list of string + pub fn paths(&self) -> Vec { + let mut result = Vec::new(); + for entry in self.ptr.paths().into_iter() { + result.push(entry.to_string()); + } + result + } + + /// Change the runpath value + pub fn set_runpath(&mut self, value: &str) { + cxx::let_cxx_string!(__cxx_s = value.to_string()); + self.ptr.pin_mut().set_runpath(&__cxx_s); + } + + /// Change the runpath value with the given slice + pub fn set_runpath_with_value(&mut self, values: &[&str]) { + cxx::let_cxx_string!(__cxx_s = values.join(":")); + self.ptr.pin_mut().set_runpath(&__cxx_s); + } + + /// Insert a `path` at the given `position` + pub fn insert(&mut self, pos: u32, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().insert(pos, &__cxx_s); + } + + /// Append the given path + pub fn append(&mut self, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().append(&__cxx_s); + } + + /// The given path + pub fn remove(&mut self, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().remove(&__cxx_s); + } +} + +impl FromFFI for RunPath<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for RunPath<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for RunPath<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RunPath").finish() + } +} + +/// Structure that represents a dynamic entry associated with the name of a library (`DT_SONAME`) +pub struct SharedObject<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl SharedObject<'_> { + pub fn new(name: &str) -> SharedObject<'static> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + SharedObject::from_ffi(lief_ffi::ELF_DynamicSharedObject::create(&__cxx_s)) + } + + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } +} + +impl FromFFI for SharedObject<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for SharedObject<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for SharedObject<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SharedObject").finish() + } +} + +/// Structure that represents a dynamic entry associated with the name of a library (`DT_AUXILIARY`) +pub struct Auxiliary<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Auxiliary<'_> { + pub fn new(name: &str) -> Auxiliary<'static> { + cxx::let_cxx_string!(__cxx_s = name); + Auxiliary::from_ffi(lief_ffi::ELF_DynamicEntryAuxiliary::create(&__cxx_s)) + } + + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } +} + +impl FromFFI for Auxiliary<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Auxiliary<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Auxiliary<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Auxiliary").finish() + } +} + +/// Structure that represents a dynamic entry associated with the name of a library (`DT_FILTER`) +pub struct Filter<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Filter<'_> { + pub fn new(name: &str) -> Filter<'static> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Filter::from_ffi(lief_ffi::ELF_DynamicEntryFilter::create(&__cxx_s)) + } + + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } +} + +impl FromFFI for Filter<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Filter<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Filter<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Filter").finish() + } +} + +/// Structure that represents a dynamic flag entry: `DT_FLAGS` or `DT_FLAGS_1` +pub struct Flags<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Flags<'_> { + pub fn flags(&self) -> DtFlags { + DtFlags::from(self.ptr.flags()) + } + + pub fn add_flag(&mut self, flag: DtFlags) { + self.ptr.pin_mut().add_flag(flag.into()) + } + + pub fn remove_flag(&mut self, flag: DtFlags) { + self.ptr.pin_mut().remove_flag(flag.into()) + } + + pub fn create_dt_flag(value: u64) -> Self { + Self::from_ffi(ffi::ELF_DynamicEntryFlags::create_dt_flag(value)) + } + + pub fn create_dt_flag_1(value: u64) -> Self { + Self::from_ffi(ffi::ELF_DynamicEntryFlags::create_dt_flag_1(value)) + } +} + +impl FromFFI for Flags<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DynamicEntry for Flags<'_> { + fn as_base(&self) -> &ffi::ELF_DynamicEntry { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::ELF_DynamicEntry> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::ELF_DynamicEntry + as *mut ffi::ELF_DynamicEntry) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Flags<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Flags").finish() + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct DtFlags: u64 { + const ORIGIN = 0x1; + const SYMBOLIC = 0x2; + const TEXTREL = 0x4; + const BIND_NOW = 0x8; + const STATIC_TLS = 0x10; + const NOW = 0x100000001; + const GLOBAL = 0x100000002; + const GROUP = 0x100000004; + const NODELETE = 0x100000008; + const LOADFLTR = 0x100000010; + const INITFIRST = 0x100000020; + const NOOPEN = 0x100000040; + const HANDLE_ORIGIN = 0x100000080; + const DIRECT = 0x100000100; + const TRANS = 0x100000200; + const INTERPOSE = 0x100000400; + const NODEFLIB = 0x100000800; + const NODUMP = 0x100001000; + const CONFALT = 0x100002000; + const ENDFILTEE = 0x100004000; + const DISPRELDNE = 0x100008000; + const DISPRELPND = 0x100010000; + const NODIRECT = 0x100020000; + const IGNMULDEF = 0x100040000; + const NOKSYMS = 0x100080000; + const NOHDR = 0x100100000; + const EDITED = 0x100200000; + const NORELOC = 0x100400000; + const SYMINTPOSE = 0x100800000; + const GLOBAUDIT = 0x101000000; + const SINGLETON = 0x102000000; + const PIE = 0x108000000; + const KMOD = 0x110000000; + const WEAKFILTER = 0x120000000; + const NOCOMMON = 0x140000000; + } +} + +impl From for DtFlags { + fn from(value: u64) -> Self { + DtFlags::from_bits_truncate(value) + } +} +impl From for u64 { + fn from(value: DtFlags) -> Self { + value.bits() + } +} +impl std::fmt::Display for DtFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +declare_iterator!( + DynamicEntries, + Entries<'a>, + ffi::ELF_DynamicEntry, + ffi::ELF_Binary, + ffi::ELF_Binary_it_dynamic_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/hash.rs b/vendor/lief/api/rust/crates/lief/src/elf/hash.rs new file mode 100644 index 0000000..38c0f6f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/hash.rs @@ -0,0 +1,118 @@ +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; + +/// This structure wraps the sysv-hash info +pub struct Sysv<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Sysv<'_> { + /// Number of bucket used for this hash table + pub fn nbucket(&self) -> u32 { + self.ptr.nbucket() + } + + /// Number of chains used for this hash table + pub fn nchain(&self) -> u32 { + self.ptr.nchain() + } + + /// Bucket's values + pub fn buckets(&self) -> Vec { + Vec::from(self.ptr.buckets().as_slice()) + } + + /// Chain's values + pub fn chains(&self) -> Vec { + Vec::from(self.ptr.chains().as_slice()) + } +} + +impl fmt::Debug for Sysv<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Sysv") + .field("nbucket", &self.nbucket()) + .field("nchain", &self.nchain()) + .field("buckets", &self.buckets()) + .field("chains", &self.chains()) + .finish() + } +} + +impl FromFFI for Sysv<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure that wraps the GNU-hash implementation +pub struct Gnu<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Gnu<'_> { + /// Number of buckets used in this hash table + pub fn nb_buckets(&self) -> u32 { + self.ptr.nb_buckets() + } + + /// Index of the first symbol in the dynamic symbols table which accessible with the hash table + pub fn symbol_index(&self) -> u32 { + self.ptr.symbol_index() + } + + /// Shift count used in the bloom filter + pub fn shift2(&self) -> u32 { + self.ptr.shift2() + } + + /// Number of bloom filters used. It must be a power of 2. + pub fn maskwords(&self) -> u32 { + self.ptr.maskwords() + } + + /// Bloom filters + pub fn bloom_filters(&self) -> Vec { + Vec::from(self.ptr.bloom_filters().as_slice()) + } + + /// Hash bucket values + pub fn buckets(&self) -> Vec { + Vec::from(self.ptr.buckets().as_slice()) + } + + /// Hash values + pub fn hash_values(&self) -> Vec { + Vec::from(self.ptr.hash_values().as_slice()) + } +} + +impl fmt::Debug for Gnu<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("GnuHash") + .field("nb_buckets", &self.nb_buckets()) + .field("symbol_index", &self.symbol_index()) + .field("shift2", &self.shift2()) + .field("maskwords", &self.maskwords()) + .field("bloom_filters", &self.bloom_filters()) + .field("buckets", &self.buckets()) + .field("hash_values", &self.hash_values()) + .finish() + } +} + +impl FromFFI for Gnu<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/header.rs b/vendor/lief/api/rust/crates/lief/src/elf/header.rs new file mode 100644 index 0000000..e18992e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/header.rs @@ -0,0 +1,932 @@ +use lief_ffi as ffi; + +use std::{fmt, marker::PhantomData}; + +use crate::common::FromFFI; + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// The type of the underlying ELF file. This enum matches +/// the semantic of `ET_NONE`, `ET_REL`, ... +pub enum FileType { + /// Can't be determined + NONE, + + /// Relocatable file (or object file) + REL, + + /// non-pie executable + EXEC, + + /// Shared library **or** a pie-executable + DYN, + + /// Core dump file + CORE, + UNKNOWN(u32), +} + +impl From for FileType { + fn from(value: u32) -> Self { + match value { + 0x00000000 => FileType::NONE, + 0x00000001 => FileType::REL, + 0x00000002 => FileType::EXEC, + 0x00000003 => FileType::DYN, + 0x00000004 => FileType::CORE, + _ => FileType::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Match the result of `Elfxx_Ehdr.e_version` +pub enum Version { + /// Invalid ELF version + NONE, + + /// Current version (default) + CURRENT, + UNKNOWN(u32), +} + +impl From for Version { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Version::NONE, + 0x00000001 => Version::CURRENT, + _ => Version::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Match the result of `Elfxx_Ehdr.e_ident[EI_CLASS]` +pub enum Class { + /// Invalid class + NONE, + + /// 32-bit objects + ELF32, + + /// 64-bits objects + ELF64, + UNKNOWN(u32), +} + +impl From for Class { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Class::NONE, + 0x00000001 => Class::ELF32, + 0x00000002 => Class::ELF64, + _ => Class::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Match the result `Elfxx_Ehdr.e_ident[EI_OSABI]` +pub enum OsAbi { + /// UNIX System V ABI + SYSTEMV, + /// HP-UX operating system + HPUX, + /// NetBSD + NETBSD, + /// GNU/Linux + GNU, + /// Historical alias for ELFOSABI_GNU. + LINUX, + /// GNU/Hurd + HURD, + /// Solaris + SOLARIS, + /// AIX + AIX, + /// IRIX + IRIX, + /// FreeBSD + FREEBSD, + /// TRU64 UNIX + TRU64, + /// Novell Modesto + MODESTO, + /// OpenBSD + OPENBSD, + /// OpenVMS + OPENVMS, + /// Hewlett-Packard Non-Stop Kernel + NSK, + /// AROS + AROS, + /// FenixOS + FENIXOS, + /// Nuxi CloudABI + CLOUDABI, + /// Bare-metal TMS320C6000 + C6000_ELFABI, + /// AMD HSA runtime + AMDGPU_HSA, + /// Linux TMS320C6000 + C6000_LINUX, + /// ARM + ARM, + /// Standalone (embedded) applicatio + STANDALONE, + UNKNOWN(u32), +} + +impl From for OsAbi { + fn from(value: u32) -> Self { + match value { + 0x00000000 => OsAbi::SYSTEMV, + 0x00000001 => OsAbi::HPUX, + 0x00000002 => OsAbi::NETBSD, + 0x00000003 => OsAbi::LINUX, + 0x00000004 => OsAbi::HURD, + 0x00000006 => OsAbi::SOLARIS, + 0x00000007 => OsAbi::AIX, + 0x00000008 => OsAbi::IRIX, + 0x00000009 => OsAbi::FREEBSD, + 0x0000000a => OsAbi::TRU64, + 0x0000000b => OsAbi::MODESTO, + 0x0000000c => OsAbi::OPENBSD, + 0x0000000d => OsAbi::OPENVMS, + 0x0000000e => OsAbi::NSK, + 0x0000000f => OsAbi::AROS, + 0x00000010 => OsAbi::FENIXOS, + 0x00000011 => OsAbi::CLOUDABI, + /* 0x00000040 => OsAbi::C6000_ELFABI, */ + 0x00000040 => OsAbi::AMDGPU_HSA, + 0x00000041 => OsAbi::C6000_LINUX, + 0x00000061 => OsAbi::ARM, + 0x000000ff => OsAbi::STANDALONE, + _ => OsAbi::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: OsAbi) -> u32 { + match value { + OsAbi::SYSTEMV => 0x00000000, + OsAbi::HPUX => 0x00000001, + OsAbi::NETBSD => 0x00000002, + OsAbi::GNU => 0x00000003, + OsAbi::LINUX => 0x00000003, + OsAbi::HURD => 0x00000004, + OsAbi::SOLARIS => 0x00000006, + OsAbi::AIX => 0x00000007, + OsAbi::IRIX => 0x00000008, + OsAbi::FREEBSD => 0x00000009, + OsAbi::TRU64 => 0x0000000a, + OsAbi::MODESTO => 0x0000000b, + OsAbi::OPENBSD => 0x0000000c, + OsAbi::OPENVMS => 0x0000000d, + OsAbi::NSK => 0x0000000e, + OsAbi::AROS => 0x0000000f, + OsAbi::FENIXOS => 0x00000010, + OsAbi::CLOUDABI => 0x00000011, + OsAbi::C6000_ELFABI => 0x00000040, + OsAbi::AMDGPU_HSA => 0x00000040, + OsAbi::C6000_LINUX => 0x00000041, + OsAbi::ARM => 0x00000061, + OsAbi::STANDALONE => 0x000000ff, + OsAbi::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Match the result `Elfxx_Ehdr.e_ident[EI_DATA]` +pub enum ElfData { + /// Invalid data encoding + NONE, + /// 2's complement, little endian + LSB, + /// 2's complement, big endian + MSB, + UNKNOWN(u32), +} + +impl From for ElfData { + fn from(value: u32) -> Self { + match value { + 0x00000000 => ElfData::NONE, + 0x00000001 => ElfData::LSB, + 0x00000002 => ElfData::MSB, + _ => ElfData::UNKNOWN(value), + } + } +} + +/// Class which represents the ELF's header. This class mirrors the raw +/// ELF `Elfxx_Ehdr` structure +pub struct Header<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl FromFFI for Header<'_> { + fn from_ffi(hdr: cxx::UniquePtr) -> Self { + Self { + ptr: hdr, + _owner: PhantomData, + } + } +} + +impl Header<'_> { + /// Executable entrypoint + pub fn entrypoint(&self) -> u64 { + self.ptr.entrypoint() + } + + /// Define the object file type. (e.g. executable, library...) + pub fn file_type(&self) -> FileType { + FileType::from(self.ptr.file_type()) + } + + /// Version of the object file format + pub fn object_file_version(&self) -> Version { + Version::from(self.ptr.object_file_version()) + } + + /// Return the object's class. `ELF64` or `ELF32` + pub fn identity_class(&self) -> Class { + Class::from(self.ptr.identity_class()) + } + + /// Specify the data encoding + pub fn identity_data(&self) -> ElfData { + ElfData::from(self.ptr.identity_data()) + } + + /// Whether this header uses the MIPS n64 ELF encoding. + pub fn is_mips_n64(&self) -> bool { + self.ptr.is_mips_n64() + } + + /// See: [`Header::object_file_version`] + pub fn identity_version(&self) -> Version { + Version::from(self.ptr.identity_version()) + } + + /// Identifies the version of the ABI for which the object is prepared + pub fn identity_os_abi(&self) -> OsAbi { + OsAbi::from(self.ptr.identity_os_abi()) + } + + /// Target architecture + pub fn machine_type(&self) -> Arch { + Arch::from(self.ptr.machine_type()) + } + + /// Offset of the programs table (also known as segments table) + pub fn program_headers_offset(&self) -> u64 { + self.ptr.program_headers_offset() + } + + /// Offset of the sections table + pub fn section_headers_offset(&self) -> u64 { + self.ptr.section_headers_offset() + } + + /// Processor-specific flags + pub fn processor_flag(&self) -> u32 { + self.ptr.processor_flag() + } + + /// Size of the current header (i.e. `sizeof(Elfxx_Ehdr)`) + /// This size should be 64 for an `ELF64` binary and 52 for an `ELF32`. + pub fn header_size(&self) -> u32 { + self.ptr.header_size() + } + + /// Return the size of a program header (i.e. `sizeof(Elfxx_Phdr)`) + /// This size should be 56 for an `ELF64` binary and 32 for an `ELF32`. + pub fn program_header_size(&self) -> u32 { + self.ptr.program_header_size() + } + + /// Return the number of segments + pub fn numberof_segments(&self) -> u32 { + self.ptr.numberof_segments() + } + + /// Return the size of a section header (i.e. `sizeof(Elfxx_Shdr)`) + /// This size should be 64 for an ``ELF64`` binary and 40 for an ``ELF32``. + pub fn section_header_size(&self) -> u32 { + self.ptr.section_header_size() + } + + /// Return the number of sections + /// + ///
+ /// This value could differ from the real number of sections + /// present in the binary. It must be taken as an indication + ///
+ pub fn numberof_sections(&self) -> u32 { + self.ptr.numberof_sections() + } + + /// Return the section's index which contains sections' names + pub fn section_name_table_idx(&self) -> u32 { + self.ptr.section_name_table_idx() + } + + pub fn set_osabi(&mut self, osabi: OsAbi) { + self.ptr.pin_mut().set_osabi(osabi.into()); + } +} + +impl fmt::Debug for Header<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Header") + .field("entrypoint", &self.entrypoint()) + .field("object_file_version", &self.object_file_version()) + .field("identity_class", &self.identity_class()) + .field("identity_os_abi", &self.identity_os_abi()) + .field("identity_data", &self.identity_data()) + .field("is_mips_n64", &self.is_mips_n64()) + .field("identity_version", &self.identity_version()) + .field("file_type", &self.file_type()) + .field("machine_type", &self.machine_type()) + .field("program_headers_offset", &self.program_headers_offset()) + .field("section_headers_offset", &self.section_headers_offset()) + .field("processor_flag", &self.processor_flag()) + .field("header_size", &self.header_size()) + .field("program_header_size", &self.program_header_size()) + .field("numberof_segments", &self.numberof_segments()) + .field("section_header_size", &self.section_header_size()) + .field("numberof_sections", &self.numberof_sections()) + .field("section_name_table_idx", &self.section_name_table_idx()) + .finish() + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Arch { + NONE, + M32, + SPARC, + I386, + M68K, + M88K, + IAMCU, + I860, + MIPS, + S370, + MIPS_RS3_LE, + PARISC, + VPP500, + SPARC32PLUS, + I60, + PPC, + PPC64, + S390, + SPU, + V800, + FR20, + RH32, + RCE, + ARM, + ALPHA, + SH, + SPARCV9, + TRICORE, + ARC, + H8_300, + H8_300H, + H8S, + H8_500, + IA_64, + MIPS_X, + COLDFIRE, + M68HC12, + MMA, + PCP, + NCPU, + NDR1, + STARCORE, + ME16, + ST100, + TINYJ, + X86_64, + PDSP, + PDP10, + PDP11, + FX66, + ST9PLUS, + ST7, + M68HC16, + M68HC11, + M68HC08, + M68HC05, + SVX, + ST19, + VAX, + CRIS, + JAVELIN, + FIREPATH, + ZSP, + MMIX, + HUANY, + PRISM, + AVR, + FR30, + D10V, + D30V, + V850, + M32R, + MN10300, + MN10200, + PJ, + OPENRISC, + ARC_COMPACT, + XTENSA, + VIDEOCORE, + TMM_GPP, + NS32K, + TPC, + SNP1K, + ST200, + IP2K, + MAX, + CR, + F2MC16, + MSP430, + BLACKFIN, + SE_C33, + SEP, + ARCA, + UNICORE, + EXCESS, + DXP, + ALTERA_NIOS2, + CRX, + XGATE, + C166, + M16C, + DSPIC30F, + CE, + M32C, + TSK3000, + RS08, + SHARC, + ECOG2, + SCORE7, + DSP24, + VIDEOCORE3, + LATTICEMICO32, + SE_C17, + TI_C6000, + TI_C2000, + TI_C5500, + MMDSP_PLUS, + CYPRESS_M8C, + R32C, + TRIMEDIA, + HEXAGON, + M8051, + STXP7X, + NDS32, + ECOG1, + //ECOG1X, + MAXQ30, + XIMO16, + MANIK, + CRAYNV2, + RX, + METAG, + MCST_ELBRUS, + ECOG16, + CR16, + ETPU, + SLE9X, + L10M, + K10M, + AARCH64, + AVR32, + STM8, + TILE64, + TILEPRO, + CUDA, + TILEGX, + CLOUDSHIELD, + COREA_1ST, + COREA_2ND, + ARC_COMPACT2, + OPEN8, + RL78, + VIDEOCORE5, + M78KOR, + M56800EX, + BA1, + BA2, + XCORE, + MCHP_PIC, + INTEL205, + INTEL206, + INTEL207, + INTEL208, + INTEL209, + KM32, + KMX32, + KMX16, + KMX8, + KVARC, + CDP, + COGE, + COOL, + NORC, + CSR_KALIMBA, + AMDGPU, + RISCV, + BPF, + CSKY, + LOONGARCH, + ALPHA_ALT, + UNKNOWN(u32), +} + +impl From for Arch { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Arch::NONE, + 0x00000001 => Arch::M32, + 0x00000002 => Arch::SPARC, + 0x00000003 => Arch::I386, + 0x00000004 => Arch::M68K, + 0x00000005 => Arch::M88K, + 0x00000006 => Arch::IAMCU, + 0x00000007 => Arch::I860, + 0x00000008 => Arch::MIPS, + 0x00000009 => Arch::S370, + 0x0000000a => Arch::MIPS_RS3_LE, + 0x0000000f => Arch::PARISC, + 0x00000011 => Arch::VPP500, + 0x00000012 => Arch::SPARC32PLUS, + 0x00000013 => Arch::I60, + 0x00000014 => Arch::PPC, + 0x00000015 => Arch::PPC64, + 0x00000016 => Arch::S390, + 0x00000017 => Arch::SPU, + 0x00000024 => Arch::V800, + 0x00000025 => Arch::FR20, + 0x00000026 => Arch::RH32, + 0x00000027 => Arch::RCE, + 0x00000028 => Arch::ARM, + 0x00000029 => Arch::ALPHA, + 0x0000002a => Arch::SH, + 0x0000002b => Arch::SPARCV9, + 0x0000002c => Arch::TRICORE, + 0x0000002d => Arch::ARC, + 0x0000002e => Arch::H8_300, + 0x0000002f => Arch::H8_300H, + 0x00000030 => Arch::H8S, + 0x00000031 => Arch::H8_500, + 0x00000032 => Arch::IA_64, + 0x00000033 => Arch::MIPS_X, + 0x00000034 => Arch::COLDFIRE, + 0x00000035 => Arch::M68HC12, + 0x00000036 => Arch::MMA, + 0x00000037 => Arch::PCP, + 0x00000038 => Arch::NCPU, + 0x00000039 => Arch::NDR1, + 0x0000003a => Arch::STARCORE, + 0x0000003b => Arch::ME16, + 0x0000003c => Arch::ST100, + 0x0000003d => Arch::TINYJ, + 0x0000003e => Arch::X86_64, + 0x0000003f => Arch::PDSP, + 0x00000040 => Arch::PDP10, + 0x00000041 => Arch::PDP11, + 0x00000042 => Arch::FX66, + 0x00000043 => Arch::ST9PLUS, + 0x00000044 => Arch::ST7, + 0x00000045 => Arch::M68HC16, + 0x00000046 => Arch::M68HC11, + 0x00000047 => Arch::M68HC08, + 0x00000048 => Arch::M68HC05, + 0x00000049 => Arch::SVX, + 0x0000004a => Arch::ST19, + 0x0000004b => Arch::VAX, + 0x0000004c => Arch::CRIS, + 0x0000004d => Arch::JAVELIN, + 0x0000004e => Arch::FIREPATH, + 0x0000004f => Arch::ZSP, + 0x00000050 => Arch::MMIX, + 0x00000051 => Arch::HUANY, + 0x00000052 => Arch::PRISM, + 0x00000053 => Arch::AVR, + 0x00000054 => Arch::FR30, + 0x00000055 => Arch::D10V, + 0x00000056 => Arch::D30V, + 0x00000057 => Arch::V850, + 0x00000058 => Arch::M32R, + 0x00000059 => Arch::MN10300, + 0x0000005a => Arch::MN10200, + 0x0000005b => Arch::PJ, + 0x0000005c => Arch::OPENRISC, + 0x0000005d => Arch::ARC_COMPACT, + 0x0000005e => Arch::XTENSA, + 0x0000005f => Arch::VIDEOCORE, + 0x00000060 => Arch::TMM_GPP, + 0x00000061 => Arch::NS32K, + 0x00000062 => Arch::TPC, + 0x00000063 => Arch::SNP1K, + 0x00000064 => Arch::ST200, + 0x00000065 => Arch::IP2K, + 0x00000066 => Arch::MAX, + 0x00000067 => Arch::CR, + 0x00000068 => Arch::F2MC16, + 0x00000069 => Arch::MSP430, + 0x0000006a => Arch::BLACKFIN, + 0x0000006b => Arch::SE_C33, + 0x0000006c => Arch::SEP, + 0x0000006d => Arch::ARCA, + 0x0000006e => Arch::UNICORE, + 0x0000006f => Arch::EXCESS, + 0x00000070 => Arch::DXP, + 0x00000071 => Arch::ALTERA_NIOS2, + 0x00000072 => Arch::CRX, + 0x00000073 => Arch::XGATE, + 0x00000074 => Arch::C166, + 0x00000075 => Arch::M16C, + 0x00000076 => Arch::DSPIC30F, + 0x00000077 => Arch::CE, + 0x00000078 => Arch::M32C, + 0x00000083 => Arch::TSK3000, + 0x00000084 => Arch::RS08, + 0x00000085 => Arch::SHARC, + 0x00000086 => Arch::ECOG2, + 0x00000087 => Arch::SCORE7, + 0x00000088 => Arch::DSP24, + 0x00000089 => Arch::VIDEOCORE3, + 0x0000008a => Arch::LATTICEMICO32, + 0x0000008b => Arch::SE_C17, + 0x0000008c => Arch::TI_C6000, + 0x0000008d => Arch::TI_C2000, + 0x0000008e => Arch::TI_C5500, + 0x000000a0 => Arch::MMDSP_PLUS, + 0x000000a1 => Arch::CYPRESS_M8C, + 0x000000a2 => Arch::R32C, + 0x000000a3 => Arch::TRIMEDIA, + 0x000000a4 => Arch::HEXAGON, + 0x000000a5 => Arch::M8051, + 0x000000a6 => Arch::STXP7X, + 0x000000a7 => Arch::NDS32, + 0x000000a8 => Arch::ECOG1, + /*0x000000a8 => Arch::ECOG1X,*/ + 0x000000a9 => Arch::MAXQ30, + 0x000000aa => Arch::XIMO16, + 0x000000ab => Arch::MANIK, + 0x000000ac => Arch::CRAYNV2, + 0x000000ad => Arch::RX, + 0x000000ae => Arch::METAG, + 0x000000af => Arch::MCST_ELBRUS, + 0x000000b0 => Arch::ECOG16, + 0x000000b1 => Arch::CR16, + 0x000000b2 => Arch::ETPU, + 0x000000b3 => Arch::SLE9X, + 0x000000b4 => Arch::L10M, + 0x000000b5 => Arch::K10M, + 0x000000b7 => Arch::AARCH64, + 0x000000b9 => Arch::AVR32, + 0x000000ba => Arch::STM8, + 0x000000bb => Arch::TILE64, + 0x000000bc => Arch::TILEPRO, + 0x000000be => Arch::CUDA, + 0x000000bf => Arch::TILEGX, + 0x000000c0 => Arch::CLOUDSHIELD, + 0x000000c1 => Arch::COREA_1ST, + 0x000000c2 => Arch::COREA_2ND, + 0x000000c3 => Arch::ARC_COMPACT2, + 0x000000c4 => Arch::OPEN8, + 0x000000c5 => Arch::RL78, + 0x000000c6 => Arch::VIDEOCORE5, + 0x000000c7 => Arch::M78KOR, + 0x000000c8 => Arch::M56800EX, + 0x000000c9 => Arch::BA1, + 0x000000ca => Arch::BA2, + 0x000000cb => Arch::XCORE, + 0x000000cc => Arch::MCHP_PIC, + 0x000000cd => Arch::INTEL205, + 0x000000ce => Arch::INTEL206, + 0x000000cf => Arch::INTEL207, + 0x000000d0 => Arch::INTEL208, + 0x000000d1 => Arch::INTEL209, + 0x000000d2 => Arch::KM32, + 0x000000d3 => Arch::KMX32, + 0x000000d4 => Arch::KMX16, + 0x000000d5 => Arch::KMX8, + 0x000000d6 => Arch::KVARC, + 0x000000d7 => Arch::CDP, + 0x000000d8 => Arch::COGE, + 0x000000d9 => Arch::COOL, + 0x000000da => Arch::NORC, + 0x000000db => Arch::CSR_KALIMBA, + 0x000000e0 => Arch::AMDGPU, + 0x000000f3 => Arch::RISCV, + 0x000000f7 => Arch::BPF, + 0x000000fc => Arch::CSKY, + 0x00000102 => Arch::LOONGARCH, + 0x00009026 => Arch::ALPHA_ALT, + _ => Arch::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Arch) -> u32 { + match value { + Arch::NONE => 0x00000000, + Arch::M32 => 0x00000001, + Arch::SPARC => 0x00000002, + Arch::I386 => 0x00000003, + Arch::M68K => 0x00000004, + Arch::M88K => 0x00000005, + Arch::IAMCU => 0x00000006, + Arch::I860 => 0x00000007, + Arch::MIPS => 0x00000008, + Arch::S370 => 0x00000009, + Arch::MIPS_RS3_LE => 0x0000000a, + Arch::PARISC => 0x0000000f, + Arch::VPP500 => 0x00000011, + Arch::SPARC32PLUS => 0x00000012, + Arch::I60 => 0x00000013, + Arch::PPC => 0x00000014, + Arch::PPC64 => 0x00000015, + Arch::S390 => 0x00000016, + Arch::SPU => 0x00000017, + Arch::V800 => 0x00000024, + Arch::FR20 => 0x00000025, + Arch::RH32 => 0x00000026, + Arch::RCE => 0x00000027, + Arch::ARM => 0x00000028, + Arch::ALPHA => 0x00000029, + Arch::SH => 0x0000002a, + Arch::SPARCV9 => 0x0000002b, + Arch::TRICORE => 0x0000002c, + Arch::ARC => 0x0000002d, + Arch::H8_300 => 0x0000002e, + Arch::H8_300H => 0x0000002f, + Arch::H8S => 0x00000030, + Arch::H8_500 => 0x00000031, + Arch::IA_64 => 0x00000032, + Arch::MIPS_X => 0x00000033, + Arch::COLDFIRE => 0x00000034, + Arch::M68HC12 => 0x00000035, + Arch::MMA => 0x00000036, + Arch::PCP => 0x00000037, + Arch::NCPU => 0x00000038, + Arch::NDR1 => 0x00000039, + Arch::STARCORE => 0x0000003a, + Arch::ME16 => 0x0000003b, + Arch::ST100 => 0x0000003c, + Arch::TINYJ => 0x0000003d, + Arch::X86_64 => 0x0000003e, + Arch::PDSP => 0x0000003f, + Arch::PDP10 => 0x00000040, + Arch::PDP11 => 0x00000041, + Arch::FX66 => 0x00000042, + Arch::ST9PLUS => 0x00000043, + Arch::ST7 => 0x00000044, + Arch::M68HC16 => 0x00000045, + Arch::M68HC11 => 0x00000046, + Arch::M68HC08 => 0x00000047, + Arch::M68HC05 => 0x00000048, + Arch::SVX => 0x00000049, + Arch::ST19 => 0x0000004a, + Arch::VAX => 0x0000004b, + Arch::CRIS => 0x0000004c, + Arch::JAVELIN => 0x0000004d, + Arch::FIREPATH => 0x0000004e, + Arch::ZSP => 0x0000004f, + Arch::MMIX => 0x00000050, + Arch::HUANY => 0x00000051, + Arch::PRISM => 0x00000052, + Arch::AVR => 0x00000053, + Arch::FR30 => 0x00000054, + Arch::D10V => 0x00000055, + Arch::D30V => 0x00000056, + Arch::V850 => 0x00000057, + Arch::M32R => 0x00000058, + Arch::MN10300 => 0x00000059, + Arch::MN10200 => 0x0000005a, + Arch::PJ => 0x0000005b, + Arch::OPENRISC => 0x0000005c, + Arch::ARC_COMPACT => 0x0000005d, + Arch::XTENSA => 0x0000005e, + Arch::VIDEOCORE => 0x0000005f, + Arch::TMM_GPP => 0x00000060, + Arch::NS32K => 0x00000061, + Arch::TPC => 0x00000062, + Arch::SNP1K => 0x00000063, + Arch::ST200 => 0x00000064, + Arch::IP2K => 0x00000065, + Arch::MAX => 0x00000066, + Arch::CR => 0x00000067, + Arch::F2MC16 => 0x00000068, + Arch::MSP430 => 0x00000069, + Arch::BLACKFIN => 0x0000006a, + Arch::SE_C33 => 0x0000006b, + Arch::SEP => 0x0000006c, + Arch::ARCA => 0x0000006d, + Arch::UNICORE => 0x0000006e, + Arch::EXCESS => 0x0000006f, + Arch::DXP => 0x00000070, + Arch::ALTERA_NIOS2 => 0x00000071, + Arch::CRX => 0x00000072, + Arch::XGATE => 0x00000073, + Arch::C166 => 0x00000074, + Arch::M16C => 0x00000075, + Arch::DSPIC30F => 0x00000076, + Arch::CE => 0x00000077, + Arch::M32C => 0x00000078, + Arch::TSK3000 => 0x00000083, + Arch::RS08 => 0x00000084, + Arch::SHARC => 0x00000085, + Arch::ECOG2 => 0x00000086, + Arch::SCORE7 => 0x00000087, + Arch::DSP24 => 0x00000088, + Arch::VIDEOCORE3 => 0x00000089, + Arch::LATTICEMICO32 => 0x0000008a, + Arch::SE_C17 => 0x0000008b, + Arch::TI_C6000 => 0x0000008c, + Arch::TI_C2000 => 0x0000008d, + Arch::TI_C5500 => 0x0000008e, + Arch::MMDSP_PLUS => 0x000000a0, + Arch::CYPRESS_M8C => 0x000000a1, + Arch::R32C => 0x000000a2, + Arch::TRIMEDIA => 0x000000a3, + Arch::HEXAGON => 0x000000a4, + Arch::M8051 => 0x000000a5, + Arch::STXP7X => 0x000000a6, + Arch::NDS32 => 0x000000a7, + Arch::ECOG1 => 0x000000a8, + /*Arch::ECOG1X => 0x000000a8,*/ + Arch::MAXQ30 => 0x000000a9, + Arch::XIMO16 => 0x000000aa, + Arch::MANIK => 0x000000ab, + Arch::CRAYNV2 => 0x000000ac, + Arch::RX => 0x000000ad, + Arch::METAG => 0x000000ae, + Arch::MCST_ELBRUS => 0x000000af, + Arch::ECOG16 => 0x000000b0, + Arch::CR16 => 0x000000b1, + Arch::ETPU => 0x000000b2, + Arch::SLE9X => 0x000000b3, + Arch::L10M => 0x000000b4, + Arch::K10M => 0x000000b5, + Arch::AARCH64 => 0x000000b7, + Arch::AVR32 => 0x000000b9, + Arch::STM8 => 0x000000ba, + Arch::TILE64 => 0x000000bb, + Arch::TILEPRO => 0x000000bc, + Arch::CUDA => 0x000000be, + Arch::TILEGX => 0x000000bf, + Arch::CLOUDSHIELD => 0x000000c0, + Arch::COREA_1ST => 0x000000c1, + Arch::COREA_2ND => 0x000000c2, + Arch::ARC_COMPACT2 => 0x000000c3, + Arch::OPEN8 => 0x000000c4, + Arch::RL78 => 0x000000c5, + Arch::VIDEOCORE5 => 0x000000c6, + Arch::M78KOR => 0x000000c7, + Arch::M56800EX => 0x000000c8, + Arch::BA1 => 0x000000c9, + Arch::BA2 => 0x000000ca, + Arch::XCORE => 0x000000cb, + Arch::MCHP_PIC => 0x000000cc, + Arch::INTEL205 => 0x000000cd, + Arch::INTEL206 => 0x000000ce, + Arch::INTEL207 => 0x000000cf, + Arch::INTEL208 => 0x000000d0, + Arch::INTEL209 => 0x000000d1, + Arch::KM32 => 0x000000d2, + Arch::KMX32 => 0x000000d3, + Arch::KMX16 => 0x000000d4, + Arch::KMX8 => 0x000000d5, + Arch::KVARC => 0x000000d6, + Arch::CDP => 0x000000d7, + Arch::COGE => 0x000000d8, + Arch::COOL => 0x000000d9, + Arch::NORC => 0x000000da, + Arch::CSR_KALIMBA => 0x000000db, + Arch::AMDGPU => 0x000000e0, + Arch::RISCV => 0x000000f3, + Arch::BPF => 0x000000f7, + Arch::CSKY => 0x000000fc, + Arch::LOONGARCH => 0x00000102, + Arch::ALPHA_ALT => 0x00009026, + Arch::UNKNOWN(value) => value, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/android_ident.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/android_ident.rs new file mode 100644 index 0000000..802f058 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/android_ident.rs @@ -0,0 +1,55 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use super::NoteBase; +use crate::common::FromFFI; + +/// Note representing the `.note.android.ident` section +pub struct AndroidIdent<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl AndroidIdent<'_> { + /// Target SDK version (or 0 if it can't be resolved) + pub fn sdk_version(&self) -> u32 { + self.ptr.sdk_version() + } + + /// NDK version used (or an empty string if it can't be parsed) + pub fn ndk_version(&self) -> String { + self.ptr.ndk_version().to_string() + } + + /// NDK build number (or an empty string if it can't be parsed) + pub fn ndk_build_number(&self) -> String { + self.ptr.ndk_build_number().to_string() + } +} + +impl NoteBase for AndroidIdent<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for AndroidIdent<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AndroidIdent<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("AndroidIdent") + .field("base", &base) + .field("sdk_version", &self.sdk_version()) + .field("ndk_version", &self.ndk_version()) + .field("ndk_build_number", &self.ndk_build_number()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/auxv.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/auxv.rs new file mode 100644 index 0000000..7c3d449 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/auxv.rs @@ -0,0 +1,121 @@ +use lief_ffi as ffi; +use std::collections::HashMap; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::elf::note::NoteBase; + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Auxiliary vector types +pub enum Type { + END, + IGNORE_TY, + EXECFD, + PHDR, + PHENT, + PHNUM, + PAGESZ, + BASE, + FLAGS, + ENTRY, + NOTELF, + UID, + EUID, + GID, + EGID, + TGT_PLATFORM, + HWCAP, + CLKTCK, + FPUCW, + DCACHEBSIZE, + ICACHEBSIZE, + UCACHEBSIZE, + IGNOREPPC, + SECURE, + BASE_PLATFORM, + RANDOM, + HWCAP2, + EXECFN, + SYSINFO, + SYSINFO_EHDR, + UNKNOWN(u64), +} + +impl From for Type { + fn from(value: u64) -> Self { + match value { + 0 => Type::END, + 1 => Type::IGNORE_TY, + 2 => Type::EXECFD, + 3 => Type::PHDR, + 4 => Type::PHENT, + 5 => Type::PHNUM, + 6 => Type::PAGESZ, + 7 => Type::BASE, + 8 => Type::FLAGS, + 9 => Type::ENTRY, + 10 => Type::NOTELF, + 11 => Type::UID, + 12 => Type::EUID, + 13 => Type::GID, + 14 => Type::EGID, + 15 => Type::TGT_PLATFORM, + 16 => Type::HWCAP, + 17 => Type::CLKTCK, + 18 => Type::FPUCW, + 19 => Type::DCACHEBSIZE, + 20 => Type::ICACHEBSIZE, + 21 => Type::UCACHEBSIZE, + 22 => Type::IGNOREPPC, + 23 => Type::SECURE, + 24 => Type::BASE_PLATFORM, + 25 => Type::RANDOM, + 26 => Type::HWCAP2, + 31 => Type::EXECFN, + 32 => Type::SYSINFO, + 33 => Type::SYSINFO_EHDR, + _ => Type::UNKNOWN(value), + } + } +} + +/// Note representing core auxiliary vector (`NT_AUXV`) +pub struct Auxv<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl Auxv<'_> { + /// Return the auxiliary values as a map of (Type, value) + pub fn values(&self) -> HashMap { + self.ptr + .values() + .as_slice() + .chunks_exact(2) + .map(|c| (Type::from(c[0]), c[1])) + .collect() + } +} + +impl NoteBase for Auxv<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for Auxv<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for Auxv<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("CoreAuxv").field("base", &base).finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/file.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/file.rs new file mode 100644 index 0000000..d9d1252 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/file.rs @@ -0,0 +1,105 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::declare_fwd_iterator; +use crate::elf::note::NoteBase; + +/// An entry in the core file mapping +pub struct Entry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_CoreFile>, +} + +impl Entry<'_> { + /// Start address of the mapping + pub fn start(&self) -> u64 { + self.ptr.start() + } + + /// End address of the mapping + pub fn end(&self) -> u64 { + self.ptr.end() + } + + /// Offset in the file + pub fn file_ofs(&self) -> u64 { + self.ptr.file_ofs() + } + + /// File path + pub fn path(&self) -> String { + self.ptr.path().to_string() + } +} + +impl std::fmt::Debug for Entry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Entry") + .field("start", &format_args!("0x{:x}", self.start())) + .field("end", &format_args!("0x{:x}", self.end())) + .field("file_ofs", &format_args!("0x{:x}", self.file_ofs())) + .field("path", &self.path()) + .finish() + } +} + +impl<'a> FromFFI for Entry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Note representing core mapped files (`NT_FILE`) +pub struct File<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl File<'_> { + /// Number of file entries + pub fn count(&self) -> u64 { + self.ptr.count() + } + + /// Return the list of file entries as an iterator + pub fn files(&self) -> Entries<'_> { + Entries::new(self.ptr.files()) + } +} + +impl NoteBase for File<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for File<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for File<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("CoreFile") + .field("base", &base) + .field("count", &self.count()) + .finish() + } +} + +declare_fwd_iterator!( + Entries, + Entry<'a>, + ffi::ELF_CoreFile_entry, + ffi::ELF_CoreFile, + ffi::ELF_CoreFile_it_files +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/mod.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/mod.rs new file mode 100644 index 0000000..fcbe432 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/mod.rs @@ -0,0 +1,16 @@ +pub mod auxv; +pub mod file; +pub mod prpsinfo; +pub mod prstatus; +pub mod siginfo; + +#[doc(inline)] +pub use auxv::Auxv; +#[doc(inline)] +pub use file::File; +#[doc(inline)] +pub use prpsinfo::PrPsInfo; +#[doc(inline)] +pub use prstatus::PrStatus; +#[doc(inline)] +pub use siginfo::SigInfo; diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/prpsinfo.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/prpsinfo.rs new file mode 100644 index 0000000..995162f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/prpsinfo.rs @@ -0,0 +1,70 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::elf::note::NoteBase; + +/// Process info from a core dump +#[derive(Debug)] +pub struct Info { + /// Numeric process state + pub state: u32, + /// Printable character representing state + pub sname: String, + /// Whether the process is a zombie + pub zombie: bool, + /// Nice value + pub nice: u32, + /// Process flag + pub flag: u64, + /// Process user ID + pub uid: u32, + /// Process group ID + pub gid: u32, + /// Process ID + pub pid: u32, + /// Process parent ID + pub ppid: u32, + /// Process group + pub pgrp: u32, + /// Process session id + pub sid: u32, + /// Filename of the executable + pub filename: String, + /// Initial part of the arguments + pub args: String, +} + +/// Note representing core process info (`NT_PRPSINFO`) +pub struct PrPsInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl PrPsInfo<'_> { + pub fn info(&self) -> Option { + todo!(); + } +} + +impl NoteBase for PrPsInfo<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for PrPsInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for PrPsInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("CorePrPsInfo").field("base", &base).finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/prstatus.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/prstatus.rs new file mode 100644 index 0000000..6090971 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/prstatus.rs @@ -0,0 +1,376 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; +use std::time::Duration; + +use crate::common::FromFFI; +use crate::elf::header::Arch; +use crate::elf::note::NoteBase; +use crate::{Error, to_result}; + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Register for the x86 architecture +pub enum RegX86 { + EBX, + ECX, + EDX, + ESI, + EDI, + EBP, + EAX, + DS, + ES, + FS, + GS, + ORIG_EAX, + EIP, + CS, + EFLAGS, + ESP, + SS, + UNKNOWN(u32), +} + +impl From for RegX86 { + fn from(value: u32) -> Self { + match value { + 0 => RegX86::EBX, + 1 => RegX86::ECX, + 2 => RegX86::EDX, + 3 => RegX86::ESI, + 4 => RegX86::EDI, + 5 => RegX86::EBP, + 6 => RegX86::EAX, + 7 => RegX86::DS, + 8 => RegX86::ES, + 9 => RegX86::FS, + 10 => RegX86::GS, + 11 => RegX86::ORIG_EAX, + 12 => RegX86::EIP, + 13 => RegX86::CS, + 14 => RegX86::EFLAGS, + 15 => RegX86::ESP, + 16 => RegX86::SS, + _ => RegX86::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Register for the x86-64 architecture +pub enum RegX86_64 { + R15, + R14, + R13, + R12, + RBP, + RBX, + R11, + R10, + R9, + R8, + RAX, + RCX, + RDX, + RSI, + RDI, + ORIG_RAX, + RIP, + CS, + EFLAGS, + RSP, + SS, + FS_BASE, + GS_BASE, + DS, + ES, + UNKNOWN(u32), +} + +impl From for RegX86_64 { + fn from(value: u32) -> Self { + match value { + 0 => RegX86_64::R15, + 1 => RegX86_64::R14, + 2 => RegX86_64::R13, + 3 => RegX86_64::R12, + 4 => RegX86_64::RBP, + 5 => RegX86_64::RBX, + 6 => RegX86_64::R11, + 7 => RegX86_64::R10, + 8 => RegX86_64::R9, + 9 => RegX86_64::R8, + 10 => RegX86_64::RAX, + 11 => RegX86_64::RCX, + 12 => RegX86_64::RDX, + 13 => RegX86_64::RSI, + 14 => RegX86_64::RDI, + 15 => RegX86_64::ORIG_RAX, + 16 => RegX86_64::RIP, + 17 => RegX86_64::CS, + 18 => RegX86_64::EFLAGS, + 19 => RegX86_64::RSP, + 20 => RegX86_64::SS, + 21 => RegX86_64::FS_BASE, + 22 => RegX86_64::GS_BASE, + 23 => RegX86_64::DS, + 24 => RegX86_64::ES, + _ => RegX86_64::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Register for the ARM architecture +pub enum RegARM { + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + CPSR, + UNKNOWN(u32), +} + +impl From for RegARM { + fn from(value: u32) -> Self { + match value { + 0 => RegARM::R0, + 1 => RegARM::R1, + 2 => RegARM::R2, + 3 => RegARM::R3, + 4 => RegARM::R4, + 5 => RegARM::R5, + 6 => RegARM::R6, + 7 => RegARM::R7, + 8 => RegARM::R8, + 9 => RegARM::R9, + 10 => RegARM::R10, + 11 => RegARM::R11, + 12 => RegARM::R12, + 13 => RegARM::R13, + 14 => RegARM::R14, + 15 => RegARM::R15, + 16 => RegARM::CPSR, + _ => RegARM::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Register for the AArch64 architecture +pub enum RegAArch64 { + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + X29, + X30, + X31, + PC, + PSTATE, + UNKNOWN(u32), +} + +impl From for RegAArch64 { + fn from(value: u32) -> Self { + match value { + 0 => RegAArch64::X0, + 1 => RegAArch64::X1, + 2 => RegAArch64::X2, + 3 => RegAArch64::X3, + 4 => RegAArch64::X4, + 5 => RegAArch64::X5, + 6 => RegAArch64::X6, + 7 => RegAArch64::X7, + 8 => RegAArch64::X8, + 9 => RegAArch64::X9, + 10 => RegAArch64::X10, + 11 => RegAArch64::X11, + 12 => RegAArch64::X12, + 13 => RegAArch64::X13, + 14 => RegAArch64::X14, + 15 => RegAArch64::X15, + 16 => RegAArch64::X16, + 17 => RegAArch64::X17, + 18 => RegAArch64::X18, + 19 => RegAArch64::X19, + 20 => RegAArch64::X20, + 21 => RegAArch64::X21, + 22 => RegAArch64::X22, + 23 => RegAArch64::X23, + 24 => RegAArch64::X24, + 25 => RegAArch64::X25, + 26 => RegAArch64::X26, + 27 => RegAArch64::X27, + 28 => RegAArch64::X28, + 29 => RegAArch64::X29, + 30 => RegAArch64::X30, + 31 => RegAArch64::X31, + 32 => RegAArch64::PC, + 33 => RegAArch64::PSTATE, + _ => RegAArch64::UNKNOWN(value), + } + } +} + +/// Status information from a core dump +/// +/// This structure mirrors the kernel's `prstatus` data embedded in +/// `NT_PRSTATUS` core-dump notes and exposes signal state, process +/// identifiers, and CPU-time accounting. +#[derive(Debug)] +pub struct Status { + /// Current signal number being delivered + pub cursig: u16, + /// Set of pending signals (bitmask) + pub sigpend: u64, + /// Set of held (blocked) signals (bitmask) + pub sighold: u64, + /// Process ID + pub pid: i32, + /// Parent process ID + pub ppid: i32, + /// Process group ID + pub pgrp: i32, + /// Session ID + pub sid: i32, + /// Signal number that caused the core dump + pub signo: i32, + /// Signal code providing additional detail + pub sigcode: i32, + /// Error number associated with the signal + pub sigerr: i32, + + /// Reserved field for alignment + pub reserved: u16, + + /// User CPU time consumed by the process + pub utime: Duration, + /// System CPU time consumed by the process + pub stime: Duration, + /// User CPU time consumed by waited-for children + pub cutime: Duration, + /// System CPU time consumed by waited-for children + pub cstime: Duration, +} + +/// Note representing core process status (`NT_PRSTATUS`) +pub struct PrStatus<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl PrStatus<'_> { + /// The architecture + pub fn architecture(&self) -> Arch { + Arch::from(self.ptr.architecture()) + } + + /// Status information + pub fn status(&self) -> Status { + let s = self.ptr.status(); + Status { + cursig: s.cursig, + sigpend: s.sigpend, + sighold: s.sighold, + pid: s.pid, + ppid: s.ppid, + pgrp: s.pgrp, + sid: s.sid, + signo: s.signo, + sigcode: s.code, + sigerr: s.err, + reserved: s.reserved, + utime: Duration::new(s.utime_sec, s.utime_usec as u32), + stime: Duration::new(s.stime_sec, s.stime_usec as u32), + cutime: Duration::new(s.cutime_sec, s.cutime_usec as u32), + cstime: Duration::new(s.cstime_sec, s.cstime_usec as u32), + } + } + + /// The program counter + pub fn pc(&self) -> Result { + to_result!(ffi::ELF_CorePrStatus::pc, &self); + } + + //// The stack pointer value + pub fn sp(&self) -> Result { + to_result!(ffi::ELF_CorePrStatus::sp, &self); + } + + /// The return value register + pub fn return_value(&self) -> Result { + to_result!(ffi::ELF_CorePrStatus::return_value, &self); + } + + /// Get all register values + pub fn register_values(&self) -> Vec { + Vec::from(self.ptr.register_values().as_slice()) + } +} + +impl NoteBase for PrStatus<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for PrStatus<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for PrStatus<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("CorePrStatus") + .field("base", &base) + //.field("architecture", &self.architecture()) + //.field("status", &self.status()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/core/siginfo.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/core/siginfo.rs new file mode 100644 index 0000000..c0c123a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/core/siginfo.rs @@ -0,0 +1,56 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::elf::note::NoteBase; +use crate::{Error, to_result}; + +/// Note representing core signal information (`NT_SIGINFO`) +pub struct SigInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl SigInfo<'_> { + /// Signal number + pub fn signo(&self) -> Result { + to_result!(ffi::ELF_CoreSigInfo::signo, &self); + } + + /// Signal code + pub fn sigcode(&self) -> Result { + to_result!(ffi::ELF_CoreSigInfo::sigcode, &self); + } + + /// Signal error number + pub fn sigerrno(&self) -> Result { + to_result!(ffi::ELF_CoreSigInfo::sigerrno, &self); + } +} + +impl NoteBase for SigInfo<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for SigInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for SigInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("CoreSigInfo") + .field("base", &base) + //.field("signo", &self.signo()) + //.field("sigcode", &self.sigcode()) + //.field("sigerrno", &self.sigerrno()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/gnu_property.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/gnu_property.rs new file mode 100644 index 0000000..6d1f488 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/gnu_property.rs @@ -0,0 +1,57 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use super::NoteBase; +use super::properties::{Properties, PropertyType}; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; + +/// Note representing a GNU Property (`NT_GNU_PROPERTY_TYPE_0`) +pub struct NoteGnuProperty<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl NoteGnuProperty<'_> { + /// Return the properties as an iterator + pub fn properties(&self) -> PropertiesIt<'_> { + PropertiesIt::new(self.ptr.properties()) + } + + /// Find a property by its type + pub fn find(&self, prop_type: PropertyType) -> Option> { + into_optional(self.ptr.find(prop_type.into())) + } +} + +impl NoteBase for NoteGnuProperty<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for NoteGnuProperty<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for NoteGnuProperty<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("NoteGnuProperty") + .field("base", &base) + .finish() + } +} + +declare_fwd_iterator!( + PropertiesIt, + Properties<'a>, + ffi::ELF_NoteGnuProperty_Property, + ffi::ELF_NoteGnuProperty, + ffi::ELF_NoteGnuProperty_it_properties +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/mod.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/mod.rs new file mode 100644 index 0000000..98f91b5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/mod.rs @@ -0,0 +1,411 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::declare_iterator; +use crate::to_slice; + +pub mod android_ident; +pub mod core; +pub mod gnu_property; +pub mod note_abi; +pub mod properties; +pub mod qnx_stack; + +#[doc(inline)] +pub use android_ident::AndroidIdent; +#[doc(inline)] +pub use core::Auxv as CoreAuxv; +#[doc(inline)] +pub use core::File as CoreFile; +#[doc(inline)] +pub use core::PrPsInfo as CorePrPsInfo; +#[doc(inline)] +pub use core::PrStatus as CorePrStatus; +#[doc(inline)] +pub use core::SigInfo as CoreSigInfo; +#[doc(inline)] +pub use gnu_property::NoteGnuProperty; +#[doc(inline)] +pub use note_abi::NoteAbi; +#[doc(inline)] +pub use properties::Properties; +#[doc(inline)] +pub use qnx_stack::QNXStack; + +#[derive(Debug)] +/// The different notes recognized and supported by LIEF +pub enum Notes<'a> { + /// Android identification note + AndroidIdent(AndroidIdent<'a>), + /// ABI note (e.g. `NT_GNU_ABI_TAG`) + NoteAbi(NoteAbi<'a>), + /// GNU Property note (`NT_GNU_PROPERTY_TYPE_0`) + NoteGnuProperty(NoteGnuProperty<'a>), + /// QNX stack note + QNXStack(QNXStack<'a>), + /// Core auxiliary vector + CoreAuxv(CoreAuxv<'a>), + /// Core mapped files + CoreFile(CoreFile<'a>), + /// Core process info + CorePrPsInfo(CorePrPsInfo<'a>), + /// Core process status (registers) + CorePrStatus(CorePrStatus<'a>), + /// Core signal info + CoreSigInfo(CoreSigInfo<'a>), + /// Generic note + Generic(Generic<'a>), +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// LIEF representation of the ELF `NT_` values. +pub enum Type { + GNU_ABI_TAG, + GNU_HWCAP, + GNU_BUILD_ID, + GNU_GOLD_VERSION, + GNU_PROPERTY_TYPE_0, + GNU_BUILD_ATTRIBUTE_OPEN, + GNU_BUILD_ATTRIBUTE_FUNC, + CRASHPAD, + CORE_PRSTATUS, + CORE_FPREGSET, + CORE_PRPSINFO, + CORE_TASKSTRUCT, + CORE_AUXV, + CORE_PSTATUS, + CORE_FPREGS, + CORE_PSINFO, + CORE_LWPSTATUS, + CORE_LWPSINFO, + CORE_WIN32PSTATUS, + CORE_FILE, + CORE_PRXFPREG, + CORE_SIGINFO, + CORE_ARM_VFP, + CORE_ARM_TLS, + CORE_ARM_HW_BREAK, + CORE_ARM_HW_WATCH, + CORE_ARM_SYSTEM_CALL, + CORE_ARM_SVE, + CORE_ARM_PAC_MASK, + CORE_ARM_PACA_KEYS, + CORE_ARM_PACG_KEYS, + CORE_TAGGED_ADDR_CTRL, + CORE_PAC_ENABLED_KEYS, + CORE_X86_TLS, + CORE_X86_IOPERM, + CORE_X86_XSTATE, + CORE_X86_CET, + ANDROID_IDENT, + ANDROID_MEMTAG, + ANDROID_KUSER, + GO_BUILDID, + STAPSDT, + QNX_STACK, + UNKNOWN(u32), +} + +impl Type { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000001 => Type::GNU_ABI_TAG, + 0x00000002 => Type::GNU_HWCAP, + 0x00000003 => Type::GNU_BUILD_ID, + 0x00000004 => Type::GNU_GOLD_VERSION, + 0x00000005 => Type::GNU_PROPERTY_TYPE_0, + 0x00000006 => Type::GNU_BUILD_ATTRIBUTE_OPEN, + 0x00000007 => Type::GNU_BUILD_ATTRIBUTE_FUNC, + 0x00000008 => Type::CRASHPAD, + 0x00000009 => Type::CORE_PRSTATUS, + 0x0000000a => Type::CORE_FPREGSET, + 0x0000000b => Type::CORE_PRPSINFO, + 0x0000000c => Type::CORE_TASKSTRUCT, + 0x0000000d => Type::CORE_AUXV, + 0x0000000e => Type::CORE_PSTATUS, + 0x0000000f => Type::CORE_FPREGS, + 0x00000010 => Type::CORE_PSINFO, + 0x00000011 => Type::CORE_LWPSTATUS, + 0x00000012 => Type::CORE_LWPSINFO, + 0x00000013 => Type::CORE_WIN32PSTATUS, + 0x00000014 => Type::CORE_FILE, + 0x00000015 => Type::CORE_PRXFPREG, + 0x00000016 => Type::CORE_SIGINFO, + 0x00000017 => Type::CORE_ARM_VFP, + 0x00000018 => Type::CORE_ARM_TLS, + 0x00000019 => Type::CORE_ARM_HW_BREAK, + 0x0000001a => Type::CORE_ARM_HW_WATCH, + 0x0000001b => Type::CORE_ARM_SYSTEM_CALL, + 0x0000001c => Type::CORE_ARM_SVE, + 0x0000001d => Type::CORE_ARM_PAC_MASK, + 0x0000001e => Type::CORE_ARM_PACA_KEYS, + 0x0000001f => Type::CORE_ARM_PACG_KEYS, + 0x00000020 => Type::CORE_TAGGED_ADDR_CTRL, + 0x00000021 => Type::CORE_PAC_ENABLED_KEYS, + 0x00000022 => Type::CORE_X86_TLS, + 0x00000023 => Type::CORE_X86_IOPERM, + 0x00000024 => Type::CORE_X86_XSTATE, + 0x00000025 => Type::CORE_X86_CET, + 0x00000026 => Type::ANDROID_IDENT, + 0x00000027 => Type::ANDROID_MEMTAG, + 0x00000028 => Type::ANDROID_KUSER, + 0x00000029 => Type::GO_BUILDID, + 0x0000002a => Type::STAPSDT, + 0x0000002b => Type::QNX_STACK, + _ => Type::UNKNOWN(value), + } + } +} + +impl From for Type { + fn from(value: u32) -> Self { + Type::from_value(value) + } +} + +impl From for u32 { + fn from(value: Type) -> u32 { + match value { + Type::GNU_ABI_TAG => 0x00000001, + Type::GNU_HWCAP => 0x00000002, + Type::GNU_BUILD_ID => 0x00000003, + Type::GNU_GOLD_VERSION => 0x00000004, + Type::GNU_PROPERTY_TYPE_0 => 0x00000005, + Type::GNU_BUILD_ATTRIBUTE_OPEN => 0x00000006, + Type::GNU_BUILD_ATTRIBUTE_FUNC => 0x00000007, + Type::CRASHPAD => 0x00000008, + Type::CORE_PRSTATUS => 0x00000009, + Type::CORE_FPREGSET => 0x0000000a, + Type::CORE_PRPSINFO => 0x0000000b, + Type::CORE_TASKSTRUCT => 0x0000000c, + Type::CORE_AUXV => 0x0000000d, + Type::CORE_PSTATUS => 0x0000000e, + Type::CORE_FPREGS => 0x0000000f, + Type::CORE_PSINFO => 0x00000010, + Type::CORE_LWPSTATUS => 0x00000011, + Type::CORE_LWPSINFO => 0x00000012, + Type::CORE_WIN32PSTATUS => 0x00000013, + Type::CORE_FILE => 0x00000014, + Type::CORE_PRXFPREG => 0x00000015, + Type::CORE_SIGINFO => 0x00000016, + Type::CORE_ARM_VFP => 0x00000017, + Type::CORE_ARM_TLS => 0x00000018, + Type::CORE_ARM_HW_BREAK => 0x00000019, + Type::CORE_ARM_HW_WATCH => 0x0000001a, + Type::CORE_ARM_SYSTEM_CALL => 0x0000001b, + Type::CORE_ARM_SVE => 0x0000001c, + Type::CORE_ARM_PAC_MASK => 0x0000001d, + Type::CORE_ARM_PACA_KEYS => 0x0000001e, + Type::CORE_ARM_PACG_KEYS => 0x0000001f, + Type::CORE_TAGGED_ADDR_CTRL => 0x00000020, + Type::CORE_PAC_ENABLED_KEYS => 0x00000021, + Type::CORE_X86_TLS => 0x00000022, + Type::CORE_X86_IOPERM => 0x00000023, + Type::CORE_X86_XSTATE => 0x00000024, + Type::CORE_X86_CET => 0x00000025, + Type::ANDROID_IDENT => 0x00000026, + Type::ANDROID_MEMTAG => 0x00000027, + Type::ANDROID_KUSER => 0x00000028, + Type::GO_BUILDID => 0x00000029, + Type::STAPSDT => 0x0000002a, + Type::QNX_STACK => 0x0000002b, + Type::UNKNOWN(value) => value, + } + } +} + +/// Trait shared by all [`Notes`] +pub trait NoteBase { + #[doc(hidden)] + fn get_base(&self) -> &ffi::ELF_Note; + + /// Return the *name* of the note (also known as 'owner') + fn name(&self) -> String { + self.get_base().name().to_string() + } + + /// Return the type of the note. This type does not match the `NT_` type + /// value. For accessing the original `NT_` value, check [`NoteBase::original_type`] + fn get_type(&self) -> Type { + Type::from_value(self.get_base().get_type()) + } + + /// The original `NT_xxx` integer value. The meaning of this value likely + /// depends on the owner of the note. + fn original_type(&self) -> u32 { + self.get_base().original_type() + } + + /// Size of the **raw** note which includes padding + fn size(&self) -> u64 { + self.get_base().size() + } + + /// Return the description associated with the note + fn description(&self) -> &[u8] { + to_slice!(self.get_base().description()); + } +} + +impl NoteBase for Generic<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap() + } +} + +impl NoteBase for Notes<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + match &self { + Notes::AndroidIdent(n) => n.get_base(), + Notes::NoteAbi(n) => n.get_base(), + Notes::NoteGnuProperty(n) => n.get_base(), + Notes::QNXStack(n) => n.get_base(), + Notes::CoreAuxv(n) => n.get_base(), + Notes::CoreFile(n) => n.get_base(), + Notes::CorePrPsInfo(n) => n.get_base(), + Notes::CorePrStatus(n) => n.get_base(), + Notes::CoreSigInfo(n) => n.get_base(), + Notes::Generic(n) => n.get_base(), + } + } +} + +impl crate::common::AsFFI for Notes<'_> { + fn as_ffi(&self) -> &ffi::ELF_Note { + self.get_base() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::ELF_Note> { + match self { + Notes::Generic(g) => g.ptr.pin_mut(), + _ => { + // For non-generic notes, we still need pin_mut access to the base + // This follows the same unsafe pattern used by dynamic entries + unsafe { + std::pin::Pin::new_unchecked({ + (self.get_base() as *const ffi::ELF_Note as *mut ffi::ELF_Note) + .as_mut() + .unwrap() + }) + } + } + } + } +} + +impl FromFFI for Notes<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let note_ref = ffi_entry.as_ref().unwrap(); + + if ffi::ELF_AndroidIdent::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::AndroidIdent(AndroidIdent::from_ffi(raw)) + } else if ffi::ELF_NoteAbi::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::NoteAbi(NoteAbi::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::NoteGnuProperty(NoteGnuProperty::from_ffi(raw)) + } else if ffi::ELF_QNXStack::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::QNXStack(QNXStack::from_ffi(raw)) + } else if ffi::ELF_CoreAuxv::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::CoreAuxv(CoreAuxv::from_ffi(raw)) + } else if ffi::ELF_CoreFile::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::CoreFile(CoreFile::from_ffi(raw)) + } else if ffi::ELF_CorePrPsInfo::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::CorePrPsInfo(CorePrPsInfo::from_ffi(raw)) + } else if ffi::ELF_CorePrStatus::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::CorePrStatus(CorePrStatus::from_ffi(raw)) + } else if ffi::ELF_CoreSigInfo::classof(note_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Notes::CoreSigInfo(CoreSigInfo::from_ffi(raw)) + } else { + Notes::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +/// Generic note +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl std::fmt::Debug for &dyn NoteBase { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("NoteBase") + .field("name", &self.name()) + .field("type", &self.get_type()) + .field("size", &self.size()) + .finish() + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("GenericNote").field("base", &base).finish() + } +} + +impl FromFFI for Generic<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +declare_iterator!( + ItNotes, + Notes<'a>, + ffi::ELF_Note, + ffi::ELF_Binary, + ffi::ELF_Binary_it_notes +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/note_abi.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/note_abi.rs new file mode 100644 index 0000000..59f9d1d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/note_abi.rs @@ -0,0 +1,78 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use super::NoteBase; +use crate::common::FromFFI; + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// ABI type for the note +pub enum Abi { + LINUX, + GNU, + SOLARIS2, + FREEBSD, + NETBSD, + SYLLABLE, + NACL, + UNKNOWN(u32), +} + +impl From for Abi { + fn from(value: u32) -> Self { + match value { + 0 => Abi::LINUX, + 1 => Abi::GNU, + 2 => Abi::SOLARIS2, + 3 => Abi::FREEBSD, + 4 => Abi::NETBSD, + 5 => Abi::SYLLABLE, + 6 => Abi::NACL, + _ => Abi::UNKNOWN(value), + } + } +} + +/// Note representing an ABI tag (e.g. `NT_GNU_ABI_TAG`) +pub struct NoteAbi<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl NoteAbi<'_> { + /// Return the ABI + pub fn abi(&self) -> Abi { + Abi::from(self.ptr.abi()) + } + + /// Return the version as `[major, minor, patch]` + pub fn version(&self) -> Vec { + Vec::from(self.ptr.version().as_slice()) + } +} + +impl NoteBase for NoteAbi<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for NoteAbi<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for NoteAbi<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("NoteAbi") + .field("base", &base) + .field("abi", &self.abi()) + .field("version", &self.version()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/properties.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/properties.rs new file mode 100644 index 0000000..3e5a9ff --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/properties.rs @@ -0,0 +1,678 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::common::FromFFI; + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Type of the GNU property +pub enum PropertyType { + UNKNOWN, + GENERIC, + AARCH64_FEATURES, + AARCH64_PAUTH, + STACK_SIZE, + NO_COPY_ON_PROTECTED, + X86_ISA, + X86_FEATURE, + NEEDED, +} + +impl From for PropertyType { + fn from(value: u32) -> Self { + match value { + 0 => PropertyType::UNKNOWN, + 1 => PropertyType::GENERIC, + 2 => PropertyType::AARCH64_FEATURES, + 3 => PropertyType::AARCH64_PAUTH, + 4 => PropertyType::STACK_SIZE, + 5 => PropertyType::NO_COPY_ON_PROTECTED, + 6 => PropertyType::X86_ISA, + 7 => PropertyType::X86_FEATURE, + 8 => PropertyType::NEEDED, + _ => PropertyType::UNKNOWN, + } + } +} + +impl From for u32 { + fn from(value: PropertyType) -> u32 { + match value { + PropertyType::UNKNOWN => 0, + PropertyType::GENERIC => 1, + PropertyType::AARCH64_FEATURES => 2, + PropertyType::AARCH64_PAUTH => 3, + PropertyType::STACK_SIZE => 4, + PropertyType::NO_COPY_ON_PROTECTED => 5, + PropertyType::X86_ISA => 6, + PropertyType::X86_FEATURE => 7, + PropertyType::NEEDED => 8, + } + } +} + +/// Trait shared by all GNU property types +pub trait NoteProperty { + #[doc(hidden)] + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property; + + /// Return the type of the property + fn property_type(&self) -> PropertyType { + PropertyType::from(self.get_base().get_type()) + } +} + +#[derive(Debug)] +/// Enum of the different GNU property subtypes +pub enum Properties<'a> { + AArch64Feature(AArch64Feature<'a>), + AArch64PAuth(AArch64PAuth<'a>), + X86Features(X86Features<'a>), + X86ISA(X86ISA<'a>), + StackSize(StackSize<'a>), + NoCopyOnProtected(NoCopyOnProtected<'a>), + Needed(Needed<'a>), + Generic(GenericProperty<'a>), +} + +impl NoteProperty for Properties<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + match &self { + Properties::AArch64Feature(p) => p.get_base(), + Properties::AArch64PAuth(p) => p.get_base(), + Properties::X86Features(p) => p.get_base(), + Properties::X86ISA(p) => p.get_base(), + Properties::StackSize(p) => p.get_base(), + Properties::NoCopyOnProtected(p) => p.get_base(), + Properties::Needed(p) => p.get_base(), + Properties::Generic(p) => p.get_base(), + } + } +} + +impl FromFFI for Properties<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let prop_ref = ffi_entry.as_ref().unwrap(); + + if ffi::ELF_NoteGnuProperty_AArch64Feature::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::AArch64Feature(AArch64Feature::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_AArch64PAuth::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::AArch64PAuth(AArch64PAuth::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_X86Features::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::X86Features(X86Features::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_X86ISA::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::X86ISA(X86ISA::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_StackSize::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::StackSize(StackSize::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_NoteNoCopyOnProtected::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::NoCopyOnProtected(NoCopyOnProtected::from_ffi(raw)) + } else if ffi::ELF_NoteGnuProperty_Needed::classof(prop_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Properties::Needed(Needed::from_ffi(raw)) + } else { + assert!(ffi::ELF_NoteGnuProperty_Generic::classof(prop_ref)); + Properties::Generic(GenericProperty { + ptr: std::mem::transmute::< + cxx::UniquePtr, + cxx::UniquePtr, + >(ffi_entry), + _owner: PhantomData, + }) + } + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum AArch64FeatureFlag { + UNKNOWN, + BTI, + PAC, + GCS, +} + +impl From for AArch64FeatureFlag { + fn from(value: u64) -> Self { + match value { + 0 => AArch64FeatureFlag::UNKNOWN, + 1 => AArch64FeatureFlag::BTI, + 2 => AArch64FeatureFlag::PAC, + 3 => AArch64FeatureFlag::GCS, + _ => AArch64FeatureFlag::UNKNOWN, + } + } +} + +/// AArch64 feature property (`GNU_PROPERTY_AARCH64_FEATURE_1_AND`) +pub struct AArch64Feature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl AArch64Feature<'_> { + /// Return the list of features + pub fn features(&self) -> Vec { + Vec::from(self.ptr.features().as_slice()) + .into_iter() + .map(AArch64FeatureFlag::from) + .collect() + } +} + +impl NoteProperty for AArch64Feature<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for AArch64Feature<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AArch64Feature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AArch64Feature") + .field("type", &self.property_type()) + .field("features", &self.features()) + .finish() + } +} + +/// AArch64 pointer authentication property +pub struct AArch64PAuth<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl AArch64PAuth<'_> { + /// Platform identifier + pub fn platform(&self) -> u64 { + self.ptr.platform() + } + + /// Version + pub fn version(&self) -> u64 { + self.ptr.version() + } +} + +impl NoteProperty for AArch64PAuth<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for AArch64PAuth<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for AArch64PAuth<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AArch64PAuth") + .field("type", &self.property_type()) + .field("platform", &self.platform()) + .field("version", &self.version()) + .finish() + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum X86FeatureFlag { + NONE, + USED, + NEEDED, + UNKNOWN(u64), +} + +impl From for X86FeatureFlag { + fn from(value: u64) -> Self { + match value { + 0 => X86FeatureFlag::NONE, + 1 => X86FeatureFlag::USED, + 2 => X86FeatureFlag::NEEDED, + _ => X86FeatureFlag::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum X86Feature { + UNKNOWN, + IBT, + SHSTK, + LAM_U48, + LAM_U57, + X86, + X87, + MMX, + XMM, + YMM, + ZMM, + FXSR, + XSAVE, + XSAVEOPT, + XSAVEC, + TMM, + MASK, +} + +impl From for X86Feature { + fn from(value: u64) -> Self { + match value { + 0 => X86Feature::UNKNOWN, + 1 => X86Feature::IBT, + 2 => X86Feature::SHSTK, + 3 => X86Feature::LAM_U48, + 4 => X86Feature::LAM_U57, + 5 => X86Feature::X86, + 6 => X86Feature::X87, + 7 => X86Feature::MMX, + 8 => X86Feature::XMM, + 9 => X86Feature::YMM, + 10 => X86Feature::ZMM, + 11 => X86Feature::FXSR, + 12 => X86Feature::XSAVE, + 13 => X86Feature::XSAVEOPT, + 14 => X86Feature::XSAVEC, + 15 => X86Feature::TMM, + 16 => X86Feature::MASK, + _ => X86Feature::UNKNOWN, + } + } +} + +/// X86 feature property (`GNU_PROPERTY_X86_FEATURE_*`) +pub struct X86Features<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl X86Features<'_> { + /// Return pairs of (flag, feature) + pub fn features(&self) -> Vec<(X86FeatureFlag, X86Feature)> { + self.ptr + .features() + .as_slice() + .chunks_exact(2) + .map(|c| (X86FeatureFlag::from(c[0]), X86Feature::from(c[1]))) + .collect() + } +} + +impl NoteProperty for X86Features<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for X86Features<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for X86Features<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("X86Features") + .field("type", &self.property_type()) + .field("features", &self.features()) + .finish() + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum X86ISAFlag { + NONE, + USED, + NEEDED, + UNKNOWN(u64), +} + +impl From for X86ISAFlag { + fn from(value: u64) -> Self { + match value { + 0 => X86ISAFlag::NONE, + 1 => X86ISAFlag::USED, + 2 => X86ISAFlag::NEEDED, + _ => X86ISAFlag::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum X86ISAValue { + UNKNOWN, + BASELINE, + V2, + V3, + V4, + CMOV, + FMA, + I486, + I586, + I686, + SSE, + SSE2, + SSE3, + SSSE3, + SSE4_1, + SSE4_2, + AVX, + AVX2, + AVX512F, + AVX512CD, + AVX512ER, + AVX512PF, + AVX512VL, + AVX512DQ, + AVX512BW, + AVX512_4FMAPS, + AVX512_4VNNIW, + AVX512_BITALG, + AVX512_IFMA, + AVX512_VBMI, + AVX512_VBMI2, + AVX512_VNNI, + AVX512_BF16, +} + +impl From for X86ISAValue { + fn from(value: u64) -> Self { + match value { + 0 => X86ISAValue::UNKNOWN, + 1 => X86ISAValue::BASELINE, + 2 => X86ISAValue::V2, + 3 => X86ISAValue::V3, + 4 => X86ISAValue::V4, + 5 => X86ISAValue::CMOV, + 6 => X86ISAValue::FMA, + 7 => X86ISAValue::I486, + 8 => X86ISAValue::I586, + 9 => X86ISAValue::I686, + 10 => X86ISAValue::SSE, + 11 => X86ISAValue::SSE2, + 12 => X86ISAValue::SSE3, + 13 => X86ISAValue::SSSE3, + 14 => X86ISAValue::SSE4_1, + 15 => X86ISAValue::SSE4_2, + 16 => X86ISAValue::AVX, + 17 => X86ISAValue::AVX2, + 18 => X86ISAValue::AVX512F, + 19 => X86ISAValue::AVX512CD, + 20 => X86ISAValue::AVX512ER, + 21 => X86ISAValue::AVX512PF, + 22 => X86ISAValue::AVX512VL, + 23 => X86ISAValue::AVX512DQ, + 24 => X86ISAValue::AVX512BW, + 25 => X86ISAValue::AVX512_4FMAPS, + 26 => X86ISAValue::AVX512_4VNNIW, + 27 => X86ISAValue::AVX512_BITALG, + 28 => X86ISAValue::AVX512_IFMA, + 29 => X86ISAValue::AVX512_VBMI, + 30 => X86ISAValue::AVX512_VBMI2, + 31 => X86ISAValue::AVX512_VNNI, + 32 => X86ISAValue::AVX512_BF16, + _ => X86ISAValue::UNKNOWN, + } + } +} + +/// X86 ISA property (`GNU_PROPERTY_X86_ISA_1_*`) +pub struct X86ISA<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl X86ISA<'_> { + /// Return pairs of (flag, isa) + pub fn values(&self) -> Vec<(X86ISAFlag, X86ISAValue)> { + self.ptr + .values() + .as_slice() + .chunks_exact(2) + .map(|c| (X86ISAFlag::from(c[0]), X86ISAValue::from(c[1]))) + .collect() + } +} + +impl NoteProperty for X86ISA<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for X86ISA<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for X86ISA<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("X86ISA") + .field("type", &self.property_type()) + .field("values", &self.values()) + .finish() + } +} + +/// Stack size property (`GNU_PROPERTY_STACK_SIZE`) +pub struct StackSize<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl StackSize<'_> { + /// The stack size + pub fn stack_size(&self) -> u64 { + self.ptr.stack_size() + } +} + +impl NoteProperty for StackSize<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for StackSize<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for StackSize<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("StackSize") + .field("type", &self.property_type()) + .field("stack_size", &self.stack_size()) + .finish() + } +} + +/// No copy on protected property (`GNU_PROPERTY_NO_COPY_ON_PROTECTED`) +pub struct NoCopyOnProtected<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl NoteProperty for NoCopyOnProtected<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for NoCopyOnProtected<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for NoCopyOnProtected<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("NoCopyOnProtected") + .field("type", &self.property_type()) + .finish() + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +/// Flags for the `GNU_PROPERTY_1_NEEDED` property +pub enum NeedFlag { + UNKNOWN, + /// The object needs indirect external access + INDIRECT_EXTERN_ACCESS, +} + +impl From for NeedFlag { + fn from(value: u64) -> Self { + match value { + 0 => NeedFlag::UNKNOWN, + 1 => NeedFlag::INDIRECT_EXTERN_ACCESS, + _ => NeedFlag::UNKNOWN, + } + } +} + +/// Needed property (`GNU_PROPERTY_1_NEEDED`) +/// +/// This property conveys information about additional features that the +/// object file needs at runtime (e.g. indirect external access). +pub struct Needed<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl Needed<'_> { + /// Return the list of needed features + pub fn needs(&self) -> Vec { + Vec::from(self.ptr.needs().as_slice()) + .into_iter() + .map(NeedFlag::from) + .collect() + } +} + +impl NoteProperty for Needed<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for Needed<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for Needed<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Needed") + .field("type", &self.property_type()) + .field("needs", &self.needs()) + .finish() + } +} + +/// Generic property (unrecognized by LIEF) +pub struct GenericProperty<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_NoteGnuProperty>, +} + +impl GenericProperty<'_> { + /// The raw type value + pub fn raw_type(&self) -> u32 { + self.ptr.raw_type() + } +} + +impl NoteProperty for GenericProperty<'_> { + fn get_base(&self) -> &ffi::ELF_NoteGnuProperty_Property { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for GenericProperty<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for GenericProperty<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("GenericProperty") + .field("type", &self.property_type()) + .field("raw_type", &self.raw_type()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/note/qnx_stack.rs b/vendor/lief/api/rust/crates/lief/src/elf/note/qnx_stack.rs new file mode 100644 index 0000000..65514c0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/note/qnx_stack.rs @@ -0,0 +1,55 @@ +use lief_ffi as ffi; +use std::marker::PhantomData; + +use super::NoteBase; +use crate::common::FromFFI; + +/// Note representing the QNX stack information +pub struct QNXStack<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl QNXStack<'_> { + /// The stack size + pub fn stack_size(&self) -> u32 { + self.ptr.stack_size() + } + + /// The stack allocated size + pub fn stack_allocated(&self) -> u32 { + self.ptr.stack_allocated() + } + + /// Whether the stack is executable + pub fn is_executable(&self) -> bool { + self.ptr.is_executable() + } +} + +impl NoteBase for QNXStack<'_> { + fn get_base(&self) -> &ffi::ELF_Note { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl FromFFI for QNXStack<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for QNXStack<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn NoteBase; + f.debug_struct("QNXStack") + .field("base", &base) + .field("stack_size", &self.stack_size()) + .field("stack_allocated", &self.stack_allocated()) + .field("is_executable", &self.is_executable()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/parser_config.rs b/vendor/lief/api/rust/crates/lief/src/elf/parser_config.rs new file mode 100644 index 0000000..044c1c0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/parser_config.rs @@ -0,0 +1,108 @@ +use lief_ffi as ffi; + +/// This structure is used to tweak the ELF parser: [`crate::elf::Binary::parse_with_config`] +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct Config { + /// Whether relocations (including plt-like relocations) should be parsed. + pub parse_relocations: bool, + + /// Whether dynamic symbols (those from `.dynsym`) should be parsed + pub parse_dyn_symbols: bool, + + /// Whether debug symbols (those from `.symtab`) should be parsed + pub parse_symtab_symbols: bool, + + /// Whether versioning symbols should be parsed + pub parse_symbol_versions: bool, + + /// Whether ELF notes information should be parsed + pub parse_notes: bool, + + /// Whether the overlay data should be parsed + pub parse_overlay: bool, + + /// The method used to count the number of dynamic symbols + pub count_mtd: DynSymCount, + + /// Memory page size if the binary uses a non-standard value. + /// + /// For instance, SPARCV9 binary can use page size from 0x2000 to 0x100000. + pub page_size: u64, +} + +impl Default for Config { + fn default() -> Config { + Config { + parse_relocations: true, + parse_dyn_symbols: true, + parse_symtab_symbols: true, + parse_symbol_versions: true, + parse_notes: true, + parse_overlay: true, + count_mtd: DynSymCount::AUTO, + page_size: 0, + } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> cxx::UniquePtr { + let mut ptr = ffi::ELF_ParserConfig::create(); + ptr.pin_mut().set_parse_relocations(self.parse_relocations); + ptr.pin_mut().set_parse_dyn_symbols(self.parse_dyn_symbols); + ptr.pin_mut() + .set_parse_symtab_symbols(self.parse_symtab_symbols); + ptr.pin_mut() + .set_parse_symbol_versions(self.parse_symbol_versions); + ptr.pin_mut().set_parse_notes(self.parse_notes); + ptr.pin_mut().set_parse_overlay(self.parse_overlay); + ptr.pin_mut().set_count_mtd(self.count_mtd.into()); + ptr.pin_mut().set_page_size(self.page_size); + ptr + } +} + +/// Enum that describes the different methods that can be used by the parser to identify +/// the number of dynamic symbols +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum DynSymCount { + /// Automatic detection + AUTO, + + /// Count based on sections (not very reliable + SECTION, + + /// Count based on hash table (reliable) + HASH, + + /// Count based on PLT/GOT relocations (very reliable but not accurate) + RELOCATIONS, + + UNKNOWN(u32), +} + +impl From for DynSymCount { + fn from(value: u32) -> Self { + match value { + 0 => DynSymCount::AUTO, + 1 => DynSymCount::SECTION, + 2 => DynSymCount::HASH, + 3 => DynSymCount::RELOCATIONS, + _ => DynSymCount::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: DynSymCount) -> u32 { + match value { + DynSymCount::AUTO => 0, + DynSymCount::SECTION => 1, + DynSymCount::HASH => 2, + DynSymCount::RELOCATIONS => 3, + DynSymCount::UNKNOWN(value) => value, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/elf/relocation.rs b/vendor/lief/api/rust/crates/lief/src/elf/relocation.rs new file mode 100644 index 0000000..0b734d5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/relocation.rs @@ -0,0 +1,3632 @@ +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::Error; +use crate::elf::Section; +use crate::generic; + +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::{declare_iterator, to_result}; + +use super::Symbol; + +/// Structure which represents an ELF relocation +pub struct Relocation<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// The different types of the relocation +pub enum Type { + X86_64_NONE, + X86_64_64, + X86_64_PC32, + X86_64_GOT32, + X86_64_PLT32, + X86_64_COPY, + X86_64_GLOB_DAT, + X86_64_JUMP_SLOT, + X86_64_RELATIVE, + X86_64_GOTPCREL, + X86_64_32, + X86_64_32S, + X86_64_16, + X86_64_PC16, + X86_64_8, + X86_64_PC8, + X86_64_DTPMOD64, + X86_64_DTPOFF64, + X86_64_TPOFF64, + X86_64_TLSGD, + X86_64_TLSLD, + X86_64_DTPOFF32, + X86_64_GOTTPOFF, + X86_64_TPOFF32, + X86_64_PC64, + X86_64_GOTOFF64, + X86_64_GOTPC32, + X86_64_GOT64, + X86_64_GOTPCREL64, + X86_64_GOTPC64, + X86_64_GOTPLT64, + X86_64_PLTOFF64, + X86_64_SIZE32, + X86_64_SIZE64, + X86_64_GOTPC32_TLSDESC, + X86_64_TLSDESC_CALL, + X86_64_TLSDESC, + X86_64_IRELATIVE, + X86_64_RELATIVE64, + X86_64_PC32_BND, + X86_64_PLT32_BND, + X86_64_GOTPCRELX, + X86_64_REX_GOTPCRELX, + AARCH64_NONE, + AARCH64_ABS64, + AARCH64_ABS32, + AARCH64_ABS16, + AARCH64_PREL64, + AARCH64_PREL32, + AARCH64_PREL16, + AARCH64_MOVW_UABS_G0, + AARCH64_MOVW_UABS_G0_NC, + AARCH64_MOVW_UABS_G1, + AARCH64_MOVW_UABS_G1_NC, + AARCH64_MOVW_UABS_G2, + AARCH64_MOVW_UABS_G2_NC, + AARCH64_MOVW_UABS_G3, + AARCH64_MOVW_SABS_G0, + AARCH64_MOVW_SABS_G1, + AARCH64_MOVW_SABS_G2, + AARCH64_LD_PREL_LO19, + AARCH64_ADR_PREL_LO21, + AARCH64_ADR_PREL_PG_HI21, + AARCH64_ADR_PREL_PG_HI21_NC, + AARCH64_ADD_ABS_LO12_NC, + AARCH64_LDST8_ABS_LO12_NC, + AARCH64_TSTBR14, + AARCH64_CONDBR19, + AARCH64_JUMP26, + AARCH64_CALL26, + AARCH64_LDST16_ABS_LO12_NC, + AARCH64_LDST32_ABS_LO12_NC, + AARCH64_LDST64_ABS_LO12_NC, + AARCH64_MOVW_PREL_G0, + AARCH64_MOVW_PREL_G0_NC, + AARCH64_MOVW_PREL_G1, + AARCH64_MOVW_PREL_G1_NC, + AARCH64_MOVW_PREL_G2, + AARCH64_MOVW_PREL_G2_NC, + AARCH64_MOVW_PREL_G3, + AARCH64_LDST128_ABS_LO12_NC, + AARCH64_MOVW_GOTOFF_G0, + AARCH64_MOVW_GOTOFF_G0_NC, + AARCH64_MOVW_GOTOFF_G1, + AARCH64_MOVW_GOTOFF_G1_NC, + AARCH64_MOVW_GOTOFF_G2, + AARCH64_MOVW_GOTOFF_G2_NC, + AARCH64_MOVW_GOTOFF_G3, + AARCH64_GOTREL64, + AARCH64_GOTREL32, + AARCH64_GOT_LD_PREL19, + AARCH64_LD64_GOTOFF_LO15, + AARCH64_ADR_GOT_PAGE, + AARCH64_LD64_GOT_LO12_NC, + AARCH64_LD64_GOTPAGE_LO15, + AARCH64_TLSGD_ADR_PREL21, + AARCH64_TLSGD_ADR_PAGE21, + AARCH64_TLSGD_ADD_LO12_NC, + AARCH64_TLSGD_MOVW_G1, + AARCH64_TLSGD_MOVW_G0_NC, + AARCH64_TLSLD_ADR_PREL21, + AARCH64_TLSLD_ADR_PAGE21, + AARCH64_TLSLD_ADD_LO12_NC, + AARCH64_TLSLD_MOVW_G1, + AARCH64_TLSLD_MOVW_G0_NC, + AARCH64_TLSLD_LD_PREL19, + AARCH64_TLSLD_MOVW_DTPREL_G2, + AARCH64_TLSLD_MOVW_DTPREL_G1, + AARCH64_TLSLD_MOVW_DTPREL_G1_NC, + AARCH64_TLSLD_MOVW_DTPREL_G0, + AARCH64_TLSLD_MOVW_DTPREL_G0_NC, + AARCH64_TLSLD_ADD_DTPREL_HI12, + AARCH64_TLSLD_ADD_DTPREL_LO12, + AARCH64_TLSLD_ADD_DTPREL_LO12_NC, + AARCH64_TLSLD_LDST8_DTPREL_LO12, + AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, + AARCH64_TLSLD_LDST16_DTPREL_LO12, + AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, + AARCH64_TLSLD_LDST32_DTPREL_LO12, + AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, + AARCH64_TLSLD_LDST64_DTPREL_LO12, + AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, + AARCH64_TLSIE_MOVW_GOTTPREL_G1, + AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, + AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, + AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, + AARCH64_TLSIE_LD_GOTTPREL_PREL19, + AARCH64_TLSLE_MOVW_TPREL_G2, + AARCH64_TLSLE_MOVW_TPREL_G1, + AARCH64_TLSLE_MOVW_TPREL_G1_NC, + AARCH64_TLSLE_MOVW_TPREL_G0, + AARCH64_TLSLE_MOVW_TPREL_G0_NC, + AARCH64_TLSLE_ADD_TPREL_HI12, + AARCH64_TLSLE_ADD_TPREL_LO12, + AARCH64_TLSLE_ADD_TPREL_LO12_NC, + AARCH64_TLSLE_LDST8_TPREL_LO12, + AARCH64_TLSLE_LDST8_TPREL_LO12_NC, + AARCH64_TLSLE_LDST16_TPREL_LO12, + AARCH64_TLSLE_LDST16_TPREL_LO12_NC, + AARCH64_TLSLE_LDST32_TPREL_LO12, + AARCH64_TLSLE_LDST32_TPREL_LO12_NC, + AARCH64_TLSLE_LDST64_TPREL_LO12, + AARCH64_TLSLE_LDST64_TPREL_LO12_NC, + AARCH64_TLSDESC_LD_PREL19, + AARCH64_TLSDESC_ADR_PREL21, + AARCH64_TLSDESC_ADR_PAGE21, + AARCH64_TLSDESC_LD64_LO12_NC, + AARCH64_TLSDESC_ADD_LO12_NC, + AARCH64_TLSDESC_OFF_G1, + AARCH64_TLSDESC_OFF_G0_NC, + AARCH64_TLSDESC_LDR, + AARCH64_TLSDESC_ADD, + AARCH64_TLSDESC_CALL, + AARCH64_TLSLE_LDST128_TPREL_LO12, + AARCH64_TLSLE_LDST128_TPREL_LO12_NC, + AARCH64_TLSLD_LDST128_DTPREL_LO12, + AARCH64_TLSLD_LDST128_DTPREL_LO12_NC, + AARCH64_COPY, + AARCH64_GLOB_DAT, + AARCH64_JUMP_SLOT, + AARCH64_RELATIVE, + AARCH64_TLS_DTPREL64, + AARCH64_TLS_DTPMOD64, + AARCH64_TLS_TPREL64, + AARCH64_TLSDESC, + AARCH64_IRELATIVE, + ARM_NONE, + ARM_PC24, + ARM_ABS32, + ARM_REL32, + ARM_LDR_PC_G0, + ARM_ABS16, + ARM_ABS12, + ARM_THM_ABS5, + ARM_ABS8, + ARM_SBREL32, + ARM_THM_CALL, + ARM_THM_PC8, + ARM_BREL_ADJ, + ARM_TLS_DESC, + ARM_THM_SWI8, + ARM_XPC25, + ARM_THM_XPC22, + ARM_TLS_DTPMOD32, + ARM_TLS_DTPOFF32, + ARM_TLS_TPOFF32, + ARM_COPY, + ARM_GLOB_DAT, + ARM_JUMP_SLOT, + ARM_RELATIVE, + ARM_GOTOFF32, + ARM_BASE_PREL, + ARM_GOT_BREL, + ARM_PLT32, + ARM_CALL, + ARM_JUMP24, + ARM_THM_JUMP24, + ARM_BASE_ABS, + ARM_ALU_PCREL_7_0, + ARM_ALU_PCREL_15_8, + ARM_ALU_PCREL_23_15, + ARM_LDR_SBREL_11_0_NC, + ARM_ALU_SBREL_19_12_NC, + ARM_ALU_SBREL_27_20_CK, + ARM_TARGET1, + ARM_SBREL31, + ARM_V4BX, + ARM_TARGET2, + ARM_PREL31, + ARM_MOVW_ABS_NC, + ARM_MOVT_ABS, + ARM_MOVW_PREL_NC, + ARM_MOVT_PREL, + ARM_THM_MOVW_ABS_NC, + ARM_THM_MOVT_ABS, + ARM_THM_MOVW_PREL_NC, + ARM_THM_MOVT_PREL, + ARM_THM_JUMP19, + ARM_THM_JUMP6, + ARM_THM_ALU_PREL_11_0, + ARM_THM_PC12, + ARM_ABS32_NOI, + ARM_REL32_NOI, + ARM_ALU_PC_G0_NC, + ARM_ALU_PC_G0, + ARM_ALU_PC_G1_NC, + ARM_ALU_PC_G1, + ARM_ALU_PC_G2, + ARM_LDR_PC_G1, + ARM_LDR_PC_G2, + ARM_LDRS_PC_G0, + ARM_LDRS_PC_G1, + ARM_LDRS_PC_G2, + ARM_LDC_PC_G0, + ARM_LDC_PC_G1, + ARM_LDC_PC_G2, + ARM_ALU_SB_G0_NC, + ARM_ALU_SB_G0, + ARM_ALU_SB_G1_NC, + ARM_ALU_SB_G1, + ARM_ALU_SB_G2, + ARM_LDR_SB_G0, + ARM_LDR_SB_G1, + ARM_LDR_SB_G2, + ARM_LDRS_SB_G0, + ARM_LDRS_SB_G1, + ARM_LDRS_SB_G2, + ARM_LDC_SB_G0, + ARM_LDC_SB_G1, + ARM_LDC_SB_G2, + ARM_MOVW_BREL_NC, + ARM_MOVT_BREL, + ARM_MOVW_BREL, + ARM_THM_MOVW_BREL_NC, + ARM_THM_MOVT_BREL, + ARM_THM_MOVW_BREL, + ARM_TLS_GOTDESC, + ARM_TLS_CALL, + ARM_TLS_DESCSEQ, + ARM_THM_TLS_CALL, + ARM_PLT32_ABS, + ARM_GOT_ABS, + ARM_GOT_PREL, + ARM_GOT_BREL12, + ARM_GOTOFF12, + ARM_GOTRELAX, + ARM_GNU_VTENTRY, + ARM_GNU_VTINHERIT, + ARM_THM_JUMP11, + ARM_THM_JUMP8, + ARM_TLS_GD32, + ARM_TLS_LDM32, + ARM_TLS_LDO32, + ARM_TLS_IE32, + ARM_TLS_LE32, + ARM_TLS_LDO12, + ARM_TLS_LE12, + ARM_TLS_IE12GP, + ARM_PRIVATE_0, + ARM_PRIVATE_1, + ARM_PRIVATE_2, + ARM_PRIVATE_3, + ARM_PRIVATE_4, + ARM_PRIVATE_5, + ARM_PRIVATE_6, + ARM_PRIVATE_7, + ARM_PRIVATE_8, + ARM_PRIVATE_9, + ARM_PRIVATE_10, + ARM_PRIVATE_11, + ARM_PRIVATE_12, + ARM_PRIVATE_13, + ARM_PRIVATE_14, + ARM_PRIVATE_15, + ARM_ME_TOO, + ARM_THM_TLS_DESCSEQ16, + ARM_THM_TLS_DESCSEQ32, + ARM_IRELATIVE, + ARM_RXPC25, + ARM_RSBREL32, + ARM_THM_RPC22, + ARM_RREL32, + ARM_RPC24, + ARM_RBASE, + HEX_NONE, + HEX_B22_PCREL, + HEX_B15_PCREL, + HEX_B7_PCREL, + HEX_LO16, + HEX_HI16, + HEX_32, + HEX_16, + HEX_8, + HEX_GPREL16_0, + HEX_GPREL16_1, + HEX_GPREL16_2, + HEX_GPREL16_3, + HEX_HL16, + HEX_B13_PCREL, + HEX_B9_PCREL, + HEX_B32_PCREL_X, + HEX_32_6_X, + HEX_B22_PCREL_X, + HEX_B15_PCREL_X, + HEX_B13_PCREL_X, + HEX_B9_PCREL_X, + HEX_B7_PCREL_X, + HEX_16_X, + HEX_12_X, + HEX_11_X, + HEX_10_X, + HEX_9_X, + HEX_8_X, + HEX_7_X, + HEX_6_X, + HEX_32_PCREL, + HEX_COPY, + HEX_GLOB_DAT, + HEX_JMP_SLOT, + HEX_RELATIVE, + HEX_PLT_B22_PCREL, + HEX_GOTREL_LO16, + HEX_GOTREL_HI16, + HEX_GOTREL_32, + HEX_GOT_LO16, + HEX_GOT_HI16, + HEX_GOT_32, + HEX_GOT_16, + HEX_DTPMOD_32, + HEX_DTPREL_LO16, + HEX_DTPREL_HI16, + HEX_DTPREL_32, + HEX_DTPREL_16, + HEX_GD_PLT_B22_PCREL, + HEX_GD_GOT_LO16, + HEX_GD_GOT_HI16, + HEX_GD_GOT_32, + HEX_GD_GOT_16, + HEX_IE_LO16, + HEX_IE_HI16, + HEX_IE_32, + HEX_IE_GOT_LO16, + HEX_IE_GOT_HI16, + HEX_IE_GOT_32, + HEX_IE_GOT_16, + HEX_TPREL_LO16, + HEX_TPREL_HI16, + HEX_TPREL_32, + HEX_TPREL_16, + HEX_6_PCREL_X, + HEX_GOTREL_32_6_X, + HEX_GOTREL_16_X, + HEX_GOTREL_11_X, + HEX_GOT_32_6_X, + HEX_GOT_16_X, + HEX_GOT_11_X, + HEX_DTPREL_32_6_X, + HEX_DTPREL_16_X, + HEX_DTPREL_11_X, + HEX_GD_GOT_32_6_X, + HEX_GD_GOT_16_X, + HEX_GD_GOT_11_X, + HEX_IE_32_6_X, + HEX_IE_16_X, + HEX_IE_GOT_32_6_X, + HEX_IE_GOT_16_X, + HEX_IE_GOT_11_X, + HEX_TPREL_32_6_X, + HEX_TPREL_16_X, + HEX_TPREL_11_X, + HEX_LD_PLT_B22_PCREL, + HEX_LD_GOT_LO16, + HEX_LD_GOT_HI16, + HEX_LD_GOT_32, + HEX_LD_GOT_16, + HEX_LD_GOT_32_6_X, + HEX_LD_GOT_16_X, + HEX_LD_GOT_11_X, + X86_NONE, + X86_32, + X86_PC32, + X86_GOT32, + X86_PLT32, + X86_COPY, + X86_GLOB_DAT, + X86_JUMP_SLOT, + X86_RELATIVE, + X86_GOTOFF, + X86_GOTPC, + X86_32PLT, + X86_TLS_TPOFF, + X86_TLS_IE, + X86_TLS_GOTIE, + X86_TLS_LE, + X86_TLS_GD, + X86_TLS_LDM, + X86_16, + X86_PC16, + X86_8, + X86_PC8, + X86_TLS_GD_32, + X86_TLS_GD_PUSH, + X86_TLS_GD_CALL, + X86_TLS_GD_POP, + X86_TLS_LDM_32, + X86_TLS_LDM_PUSH, + X86_TLS_LDM_CALL, + X86_TLS_LDM_POP, + X86_TLS_LDO_32, + X86_TLS_IE_32, + X86_TLS_LE_32, + X86_TLS_DTPMOD32, + X86_TLS_DTPOFF32, + X86_TLS_TPOFF32, + X86_TLS_GOTDESC, + X86_TLS_DESC_CALL, + X86_TLS_DESC, + X86_IRELATIVE, + LARCH_NONE, + LARCH_32, + LARCH_64, + LARCH_RELATIVE, + LARCH_COPY, + LARCH_JUMP_SLOT, + LARCH_TLS_DTPMOD32, + LARCH_TLS_DTPMOD64, + LARCH_TLS_DTPREL32, + LARCH_TLS_DTPREL64, + LARCH_TLS_TPREL32, + LARCH_TLS_TPREL64, + LARCH_IRELATIVE, + LARCH_MARK_LA, + LARCH_MARK_PCREL, + LARCH_SOP_PUSH_PCREL, + LARCH_SOP_PUSH_ABSOLUTE, + LARCH_SOP_PUSH_DUP, + LARCH_SOP_PUSH_GPREL, + LARCH_SOP_PUSH_TLS_TPREL, + LARCH_SOP_PUSH_TLS_GOT, + LARCH_SOP_PUSH_TLS_GD, + LARCH_SOP_PUSH_PLT_PCREL, + LARCH_SOP_ASSERT, + LARCH_SOP_NOT, + LARCH_SOP_SUB, + LARCH_SOP_SL, + LARCH_SOP_SR, + LARCH_SOP_ADD, + LARCH_SOP_AND, + LARCH_SOP_IF_ELSE, + LARCH_SOP_POP_32_S_10_5, + LARCH_SOP_POP_32_U_10_12, + LARCH_SOP_POP_32_S_10_12, + LARCH_SOP_POP_32_S_10_16, + LARCH_SOP_POP_32_S_10_16_S2, + LARCH_SOP_POP_32_S_5_20, + LARCH_SOP_POP_32_S_0_5_10_16_S2, + LARCH_SOP_POP_32_S_0_10_10_16_S2, + LARCH_SOP_POP_32_U, + LARCH_ADD8, + LARCH_ADD16, + LARCH_ADD24, + LARCH_ADD32, + LARCH_ADD64, + LARCH_SUB8, + LARCH_SUB16, + LARCH_SUB24, + LARCH_SUB32, + LARCH_SUB64, + LARCH_GNU_VTINHERIT, + LARCH_GNU_VTENTRY, + LARCH_B16, + LARCH_B21, + LARCH_B26, + LARCH_ABS_HI20, + LARCH_ABS_LO12, + LARCH_ABS64_LO20, + LARCH_ABS64_HI12, + LARCH_PCALA_HI20, + LARCH_PCALA_LO12, + LARCH_PCALA64_LO20, + LARCH_PCALA64_HI12, + LARCH_GOT_PC_HI20, + LARCH_GOT_PC_LO12, + LARCH_GOT64_PC_LO20, + LARCH_GOT64_PC_HI12, + LARCH_GOT_HI20, + LARCH_GOT_LO12, + LARCH_GOT64_LO20, + LARCH_GOT64_HI12, + LARCH_TLS_LE_HI20, + LARCH_TLS_LE_LO12, + LARCH_TLS_LE64_LO20, + LARCH_TLS_LE64_HI12, + LARCH_TLS_IE_PC_HI20, + LARCH_TLS_IE_PC_LO12, + LARCH_TLS_IE64_PC_LO20, + LARCH_TLS_IE64_PC_HI12, + LARCH_TLS_IE_HI20, + LARCH_TLS_IE_LO12, + LARCH_TLS_IE64_LO20, + LARCH_TLS_IE64_HI12, + LARCH_TLS_LD_PC_HI20, + LARCH_TLS_LD_HI20, + LARCH_TLS_GD_PC_HI20, + LARCH_TLS_GD_HI20, + LARCH_32_PCREL, + LARCH_RELAX, + LARCH_ALIGN, + LARCH_PCREL20_S2, + LARCH_ADD6, + LARCH_SUB6, + LARCH_ADD_ULEB128, + LARCH_SUB_ULEB128, + LARCH_64_PCREL, + LARCH_CALL36, + LARCH_TLS_DESC32, + LARCH_TLS_DESC64, + LARCH_TLS_DESC_PC_HI20, + LARCH_TLS_DESC_PC_LO12, + LARCH_TLS_DESC64_PC_LO20, + LARCH_TLS_DESC64_PC_HI12, + LARCH_TLS_DESC_HI20, + LARCH_TLS_DESC_LO12, + LARCH_TLS_DESC64_LO20, + LARCH_TLS_DESC64_HI12, + LARCH_TLS_DESC_LD, + LARCH_TLS_DESC_CALL, + LARCH_TLS_LE_HI20_R, + LARCH_TLS_LE_ADD_R, + LARCH_TLS_LE_LO12_R, + LARCH_TLS_LD_PCREL20_S2, + LARCH_TLS_GD_PCREL20_S2, + LARCH_TLS_DESC_PCREL20_S2, + MIPS_NONE, + MIPS_16, + MIPS_32, + MIPS_REL32, + MIPS_26, + MIPS_HI16, + MIPS_LO16, + MIPS_GPREL16, + MIPS_LITERAL, + MIPS_GOT16, + MIPS_PC16, + MIPS_CALL16, + MIPS_GPREL32, + MIPS_UNUSED1, + MIPS_UNUSED2, + MIPS_UNUSED3, + MIPS_SHIFT5, + MIPS_SHIFT6, + MIPS_64, + MIPS_GOT_DISP, + MIPS_GOT_PAGE, + MIPS_GOT_OFST, + MIPS_GOT_HI16, + MIPS_GOT_LO16, + MIPS_SUB, + MIPS_INSERT_A, + MIPS_INSERT_B, + MIPS_DELETE, + MIPS_HIGHER, + MIPS_HIGHEST, + MIPS_CALL_HI16, + MIPS_CALL_LO16, + MIPS_SCN_DISP, + MIPS_REL16, + MIPS_ADD_IMMEDIATE, + MIPS_PJUMP, + MIPS_RELGOT, + MIPS_JALR, + MIPS_TLS_DTPMOD32, + MIPS_TLS_DTPREL32, + MIPS_TLS_DTPMOD64, + MIPS_TLS_DTPREL64, + MIPS_TLS_GD, + MIPS_TLS_LDM, + MIPS_TLS_DTPREL_HI16, + MIPS_TLS_DTPREL_LO16, + MIPS_TLS_GOTTPREL, + MIPS_TLS_TPREL32, + MIPS_TLS_TPREL64, + MIPS_TLS_TPREL_HI16, + MIPS_TLS_TPREL_LO16, + MIPS_GLOB_DAT, + MIPS_PC21_S2, + MIPS_PC26_S2, + MIPS_PC18_S3, + MIPS_PC19_S2, + MIPS_PCHI16, + MIPS_PCLO16, + MIPS16_26, + MIPS16_GPREL, + MIPS16_GOT16, + MIPS16_CALL16, + MIPS16_HI16, + MIPS16_LO16, + MIPS16_TLS_GD, + MIPS16_TLS_LDM, + MIPS16_TLS_DTPREL_HI16, + MIPS16_TLS_DTPREL_LO16, + MIPS16_TLS_GOTTPREL, + MIPS16_TLS_TPREL_HI16, + MIPS16_TLS_TPREL_LO16, + MIPS_COPY, + MIPS_JUMP_SLOT, + MICROMIPS_26_S1, + MICROMIPS_HI16, + MICROMIPS_LO16, + MICROMIPS_GPREL16, + MICROMIPS_LITERAL, + MICROMIPS_GOT16, + MICROMIPS_PC7_S1, + MICROMIPS_PC10_S1, + MICROMIPS_PC16_S1, + MICROMIPS_CALL16, + MICROMIPS_GOT_DISP, + MICROMIPS_GOT_PAGE, + MICROMIPS_GOT_OFST, + MICROMIPS_GOT_HI16, + MICROMIPS_GOT_LO16, + MICROMIPS_SUB, + MICROMIPS_HIGHER, + MICROMIPS_HIGHEST, + MICROMIPS_CALL_HI16, + MICROMIPS_CALL_LO16, + MICROMIPS_SCN_DISP, + MICROMIPS_JALR, + MICROMIPS_HI0_LO16, + MICROMIPS_TLS_GD, + MICROMIPS_TLS_LDM, + MICROMIPS_TLS_DTPREL_HI16, + MICROMIPS_TLS_DTPREL_LO16, + MICROMIPS_TLS_GOTTPREL, + MICROMIPS_TLS_TPREL_HI16, + MICROMIPS_TLS_TPREL_LO16, + MICROMIPS_GPREL7_S2, + MICROMIPS_PC23_S2, + MICROMIPS_PC21_S2, + MICROMIPS_PC26_S2, + MICROMIPS_PC18_S3, + MICROMIPS_PC19_S2, + MIPS_NUM, + MIPS_PC32, + MIPS_EH, + PPC_NONE, + PPC_ADDR32, + PPC_ADDR24, + PPC_ADDR16, + PPC_ADDR16_LO, + PPC_ADDR16_HI, + PPC_ADDR16_HA, + PPC_ADDR14, + PPC_ADDR14_BRTAKEN, + PPC_ADDR14_BRNTAKEN, + PPC_REL24, + PPC_REL14, + PPC_REL14_BRTAKEN, + PPC_REL14_BRNTAKEN, + PPC_GOT16, + PPC_GOT16_LO, + PPC_GOT16_HI, + PPC_GOT16_HA, + PPC_PLTREL24, + PPC_JMP_SLOT, + PPC_RELATIVE, + PPC_LOCAL24PC, + PPC_REL32, + PPC_TLS, + PPC_DTPMOD32, + PPC_TPREL16, + PPC_TPREL16_LO, + PPC_TPREL16_HI, + PPC_TPREL16_HA, + PPC_TPREL32, + PPC_DTPREL16, + PPC_DTPREL16_LO, + PPC_DTPREL16_HI, + PPC_DTPREL16_HA, + PPC_DTPREL32, + PPC_GOT_TLSGD16, + PPC_GOT_TLSGD16_LO, + PPC_GOT_TLSGD16_HI, + PPC_GOT_TLSGD16_HA, + PPC_GOT_TLSLD16, + PPC_GOT_TLSLD16_LO, + PPC_GOT_TLSLD16_HI, + PPC_GOT_TLSLD16_HA, + PPC_GOT_TPREL16, + PPC_GOT_TPREL16_LO, + PPC_GOT_TPREL16_HI, + PPC_GOT_TPREL16_HA, + PPC_GOT_DTPREL16, + PPC_GOT_DTPREL16_LO, + PPC_GOT_DTPREL16_HI, + PPC_GOT_DTPREL16_HA, + PPC_TLSGD, + PPC_TLSLD, + PPC_REL16, + PPC_REL16_LO, + PPC_REL16_HI, + PPC_REL16_HA, + PPC64_NONE, + PPC64_ADDR32, + PPC64_ADDR24, + PPC64_ADDR16, + PPC64_ADDR16_LO, + PPC64_ADDR16_HI, + PPC64_ADDR16_HA, + PPC64_ADDR14, + PPC64_ADDR14_BRTAKEN, + PPC64_ADDR14_BRNTAKEN, + PPC64_REL24, + PPC64_REL14, + PPC64_REL14_BRTAKEN, + PPC64_REL14_BRNTAKEN, + PPC64_GOT16, + PPC64_GOT16_LO, + PPC64_GOT16_HI, + PPC64_GOT16_HA, + PPC64_JMP_SLOT, + PPC64_RELATIVE, + PPC64_REL32, + PPC64_ADDR64, + PPC64_ADDR16_HIGHER, + PPC64_ADDR16_HIGHERA, + PPC64_ADDR16_HIGHEST, + PPC64_ADDR16_HIGHESTA, + PPC64_REL64, + PPC64_TOC16, + PPC64_TOC16_LO, + PPC64_TOC16_HI, + PPC64_TOC16_HA, + PPC64_TOC, + PPC64_ADDR16_DS, + PPC64_ADDR16_LO_DS, + PPC64_GOT16_DS, + PPC64_GOT16_LO_DS, + PPC64_TOC16_DS, + PPC64_TOC16_LO_DS, + PPC64_TLS, + PPC64_DTPMOD64, + PPC64_TPREL16, + PPC64_TPREL16_LO, + PPC64_TPREL16_HI, + PPC64_TPREL16_HA, + PPC64_TPREL64, + PPC64_DTPREL16, + PPC64_DTPREL16_LO, + PPC64_DTPREL16_HI, + PPC64_DTPREL16_HA, + PPC64_DTPREL64, + PPC64_GOT_TLSGD16, + PPC64_GOT_TLSGD16_LO, + PPC64_GOT_TLSGD16_HI, + PPC64_GOT_TLSGD16_HA, + PPC64_GOT_TLSLD16, + PPC64_GOT_TLSLD16_LO, + PPC64_GOT_TLSLD16_HI, + PPC64_GOT_TLSLD16_HA, + PPC64_GOT_TPREL16_DS, + PPC64_GOT_TPREL16_LO_DS, + PPC64_GOT_TPREL16_HI, + PPC64_GOT_TPREL16_HA, + PPC64_GOT_DTPREL16_DS, + PPC64_GOT_DTPREL16_LO_DS, + PPC64_GOT_DTPREL16_HI, + PPC64_GOT_DTPREL16_HA, + PPC64_TPREL16_DS, + PPC64_TPREL16_LO_DS, + PPC64_TPREL16_HIGHER, + PPC64_TPREL16_HIGHERA, + PPC64_TPREL16_HIGHEST, + PPC64_TPREL16_HIGHESTA, + PPC64_DTPREL16_DS, + PPC64_DTPREL16_LO_DS, + PPC64_DTPREL16_HIGHER, + PPC64_DTPREL16_HIGHERA, + PPC64_DTPREL16_HIGHEST, + PPC64_DTPREL16_HIGHESTA, + PPC64_TLSGD, + PPC64_TLSLD, + PPC64_REL16, + PPC64_REL16_LO, + PPC64_REL16_HI, + PPC64_REL16_HA, + SPARC_NONE, + SPARC_8, + SPARC_16, + SPARC_32, + SPARC_DISP8, + SPARC_DISP16, + SPARC_DISP32, + SPARC_WDISP30, + SPARC_WDISP22, + SPARC_HI22, + SPARC_22, + SPARC_13, + SPARC_LO10, + SPARC_GOT10, + SPARC_GOT13, + SPARC_GOT22, + SPARC_PC10, + SPARC_PC22, + SPARC_WPLT30, + SPARC_COPY, + SPARC_GLOB_DAT, + SPARC_JMP_SLOT, + SPARC_RELATIVE, + SPARC_UA32, + SPARC_PLT32, + SPARC_HIPLT22, + SPARC_LOPLT10, + SPARC_PCPLT32, + SPARC_PCPLT22, + SPARC_PCPLT10, + SPARC_10, + SPARC_11, + SPARC_64, + SPARC_OLO10, + SPARC_HH22, + SPARC_HM10, + SPARC_LM22, + SPARC_PC_HH22, + SPARC_PC_HM10, + SPARC_PC_LM22, + SPARC_WDISP16, + SPARC_WDISP19, + SPARC_7, + SPARC_5, + SPARC_6, + SPARC_DISP64, + SPARC_PLT64, + SPARC_HIX22, + SPARC_LOX10, + SPARC_H44, + SPARC_M44, + SPARC_L44, + SPARC_REGISTER, + SPARC_UA64, + SPARC_UA16, + SPARC_TLS_GD_HI22, + SPARC_TLS_GD_LO10, + SPARC_TLS_GD_ADD, + SPARC_TLS_GD_CALL, + SPARC_TLS_LDM_HI22, + SPARC_TLS_LDM_LO10, + SPARC_TLS_LDM_ADD, + SPARC_TLS_LDM_CALL, + SPARC_TLS_LDO_HIX22, + SPARC_TLS_LDO_LOX10, + SPARC_TLS_LDO_ADD, + SPARC_TLS_IE_HI22, + SPARC_TLS_IE_LO10, + SPARC_TLS_IE_LD, + SPARC_TLS_IE_LDX, + SPARC_TLS_IE_ADD, + SPARC_TLS_LE_HIX22, + SPARC_TLS_LE_LOX10, + SPARC_TLS_DTPMOD32, + SPARC_TLS_DTPMOD64, + SPARC_TLS_DTPOFF32, + SPARC_TLS_DTPOFF64, + SPARC_TLS_TPOFF32, + SPARC_TLS_TPOFF64, + SPARC_GOTDATA_HIX22, + SPARC_GOTDATA_LOX10, + SPARC_GOTDATA_OP_HIX22, + SPARC_GOTDATA_OP_LOX10, + SPARC_GOTDATA_OP, + SYSZ_NONE, + SYSZ_8, + SYSZ_12, + SYSZ_16, + SYSZ_32, + SYSZ_PC32, + SYSZ_GOT12, + SYSZ_GOT32, + SYSZ_PLT32, + SYSZ_COPY, + SYSZ_GLOB_DAT, + SYSZ_JMP_SLOT, + SYSZ_RELATIVE, + SYSZ_GOTOFF, + SYSZ_GOTPC, + SYSZ_GOT16, + SYSZ_PC16, + SYSZ_PC16DBL, + SYSZ_PLT16DBL, + SYSZ_PC32DBL, + SYSZ_PLT32DBL, + SYSZ_GOTPCDBL, + SYSZ_64, + SYSZ_PC64, + SYSZ_GOT64, + SYSZ_PLT64, + SYSZ_GOTENT, + SYSZ_GOTOFF16, + SYSZ_GOTOFF64, + SYSZ_GOTPLT12, + SYSZ_GOTPLT16, + SYSZ_GOTPLT32, + SYSZ_GOTPLT64, + SYSZ_GOTPLTENT, + SYSZ_PLTOFF16, + SYSZ_PLTOFF32, + SYSZ_PLTOFF64, + SYSZ_TLS_LOAD, + SYSZ_TLS_GDCALL, + SYSZ_TLS_LDCALL, + SYSZ_TLS_GD32, + SYSZ_TLS_GD64, + SYSZ_TLS_GOTIE12, + SYSZ_TLS_GOTIE32, + SYSZ_TLS_GOTIE64, + SYSZ_TLS_LDM32, + SYSZ_TLS_LDM64, + SYSZ_TLS_IE32, + SYSZ_TLS_IE64, + SYSZ_TLS_IEENT, + SYSZ_TLS_LE32, + SYSZ_TLS_LE64, + SYSZ_TLS_LDO32, + SYSZ_TLS_LDO64, + SYSZ_TLS_DTPMOD, + SYSZ_TLS_DTPOFF, + SYSZ_TLS_TPOFF, + SYSZ_20, + SYSZ_GOT20, + SYSZ_GOTPLT20, + SYSZ_TLS_GOTIE20, + SYSZ_IRELATIVE, + SYSZ_PC12DBL, + SYSZ_PLT12DBL, + SYSZ_PC24DBL, + SYSZ_PLT24DBL, + RISCV_NONE, + RISCV_32, + RISCV_64, + RISCV_RELATIVE, + RISCV_COPY, + RISCV_JUMP_SLOT, + RISCV_TLS_DTPMOD32, + RISCV_TLS_DTPMOD64, + RISCV_TLS_DTPREL32, + RISCV_TLS_DTPREL64, + RISCV_TLS_TPREL32, + RISCV_TLS_TPREL64, + RISCV_TLSDESC, + RISCV_BRANCH, + RISCV_JAL, + RISCV_CALL, + RISCV_CALL_PLT, + RISCV_GOT_HI20, + RISCV_TLS_GOT_HI20, + RISCV_TLS_GD_HI20, + RISCV_PCREL_HI20, + RISCV_PCREL_LO12_I, + RISCV_PCREL_LO12_S, + RISCV_HI20, + RISCV_LO12_I, + RISCV_LO12_S, + RISCV_TPREL_HI20, + RISCV_TPREL_LO12_I, + RISCV_TPREL_LO12_S, + RISCV_TPREL_ADD, + RISCV_ADD8, + RISCV_ADD16, + RISCV_ADD32, + RISCV_ADD64, + RISCV_SUB8, + RISCV_SUB16, + RISCV_SUB32, + RISCV_SUB64, + RISCV_GOT32_PCREL, + RISCV_ALIGN, + RISCV_RVC_BRANCH, + RISCV_RVC_JUMP, + RISCV_RVC_LUI, + RISCV_RELAX, + RISCV_SUB6, + RISCV_SET6, + RISCV_SET8, + RISCV_SET16, + RISCV_SET32, + RISCV_32_PCREL, + RISCV_IRELATIVE, + RISCV_PLT32, + RISCV_SET_ULEB128, + RISCV_SUB_ULEB128, + RISCV_TLSDESC_HI20, + RISCV_TLSDESC_LOAD_LO12, + RISCV_TLSDESC_ADD_LO12, + RISCV_TLSDESC_CALL, + BPF_NONE, + BPF_64_64, + BPF_64_ABS64, + BPF_64_ABS32, + BPF_64_NODYLD32, + BPF_64_32, + SH_NONE, + SH_DIR32, + SH_REL32, + SH_DIR8WPN, + SH_IND12W, + SH_DIR8WPL, + SH_DIR8WPZ, + SH_DIR8BP, + SH_DIR8W, + SH_DIR8L, + SH_LOOP_START, + SH_LOOP_END, + SH_GNU_VTINHERIT, + SH_GNU_VTENTRY, + SH_SWITCH8, + SH_SWITCH16, + SH_SWITCH32, + SH_USES, + SH_COUNT, + SH_ALIGN, + SH_CODE, + SH_DATA, + SH_LABEL, + SH_DIR16, + SH_DIR8, + SH_DIR8UL, + SH_DIR8UW, + SH_DIR8U, + SH_DIR8SW, + SH_DIR8S, + SH_DIR4UL, + SH_DIR4UW, + SH_DIR4U, + SH_PSHA, + SH_PSHL, + SH_DIR5U, + SH_DIR6U, + SH_DIR6S, + SH_DIR10S, + SH_DIR10SW, + SH_DIR10SL, + SH_DIR10SQ, + SH_DIR16S, + SH_TLS_GD_32, + SH_TLS_LD_32, + SH_TLS_LDO_32, + SH_TLS_IE_32, + SH_TLS_LE_32, + SH_TLS_DTPMOD32, + SH_TLS_DTPOFF32, + SH_TLS_TPOFF32, + SH_GOT32, + SH_PLT32, + SH_COPY, + SH_GLOB_DAT, + SH_JMP_SLOT, + SH_RELATIVE, + SH_GOTOFF, + SH_GOTPC, + SH_GOTPLT32, + SH_GOT_LOW16, + SH_GOT_MEDLOW16, + SH_GOT_MEDHI16, + SH_GOT_HI16, + SH_GOTPLT_LOW16, + SH_GOTPLT_MEDLOW16, + SH_GOTPLT_MEDHI16, + SH_GOTPLT_HI16, + SH_PLT_LOW16, + SH_PLT_MEDLOW16, + SH_PLT_MEDHI16, + SH_PLT_HI16, + SH_GOTOFF_LOW16, + SH_GOTOFF_MEDLOW16, + SH_GOTOFF_MEDHI16, + SH_GOTOFF_HI16, + SH_GOTPC_LOW16, + SH_GOTPC_MEDLOW16, + SH_GOTPC_MEDHI16, + SH_GOTPC_HI16, + SH_GOT10BY4, + SH_GOTPLT10BY4, + SH_GOT10BY8, + SH_GOTPLT10BY8, + SH_COPY64, + SH_GLOB_DAT64, + SH_JMP_SLOT64, + SH_RELATIVE64, + SH_GOT20, + SH_GOTOFF20, + SH_GOTFUNCDESC, + SH_GOTFUNCDESC20, + SH_GOTOFFFUNCDESC, + SH_GOTOFFFUNCDESC20, + SH_FUNCDESC, + SH_FUNCDESC_VALUE, + SH_SHMEDIA_CODE, + SH_PT_16, + SH_IMMS16, + SH_IMMU16, + SH_IMM_LOW16, + SH_IMM_LOW16_PCREL, + SH_IMM_MEDLOW16, + SH_IMM_MEDLOW16_PCREL, + SH_IMM_MEDHI16, + SH_IMM_MEDHI16_PCREL, + SH_IMM_HI16, + SH_IMM_HI16_PCREL, + SH_64, + SH_64_PCREL, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x08000000 => Type::X86_64_NONE, + 0x08000001 => Type::X86_64_64, + 0x08000002 => Type::X86_64_PC32, + 0x08000003 => Type::X86_64_GOT32, + 0x08000004 => Type::X86_64_PLT32, + 0x08000005 => Type::X86_64_COPY, + 0x08000006 => Type::X86_64_GLOB_DAT, + 0x08000007 => Type::X86_64_JUMP_SLOT, + 0x08000008 => Type::X86_64_RELATIVE, + 0x08000009 => Type::X86_64_GOTPCREL, + 0x0800000a => Type::X86_64_32, + 0x0800000b => Type::X86_64_32S, + 0x0800000c => Type::X86_64_16, + 0x0800000d => Type::X86_64_PC16, + 0x0800000e => Type::X86_64_8, + 0x0800000f => Type::X86_64_PC8, + 0x08000010 => Type::X86_64_DTPMOD64, + 0x08000011 => Type::X86_64_DTPOFF64, + 0x08000012 => Type::X86_64_TPOFF64, + 0x08000013 => Type::X86_64_TLSGD, + 0x08000014 => Type::X86_64_TLSLD, + 0x08000015 => Type::X86_64_DTPOFF32, + 0x08000016 => Type::X86_64_GOTTPOFF, + 0x08000017 => Type::X86_64_TPOFF32, + 0x08000018 => Type::X86_64_PC64, + 0x08000019 => Type::X86_64_GOTOFF64, + 0x0800001a => Type::X86_64_GOTPC32, + 0x0800001b => Type::X86_64_GOT64, + 0x0800001c => Type::X86_64_GOTPCREL64, + 0x0800001d => Type::X86_64_GOTPC64, + 0x0800001e => Type::X86_64_GOTPLT64, + 0x0800001f => Type::X86_64_PLTOFF64, + 0x08000020 => Type::X86_64_SIZE32, + 0x08000021 => Type::X86_64_SIZE64, + 0x08000022 => Type::X86_64_GOTPC32_TLSDESC, + 0x08000023 => Type::X86_64_TLSDESC_CALL, + 0x08000024 => Type::X86_64_TLSDESC, + 0x08000025 => Type::X86_64_IRELATIVE, + 0x08000026 => Type::X86_64_RELATIVE64, + 0x08000027 => Type::X86_64_PC32_BND, + 0x08000028 => Type::X86_64_PLT32_BND, + 0x08000029 => Type::X86_64_GOTPCRELX, + 0x0800002a => Type::X86_64_REX_GOTPCRELX, + 0x10000000 => Type::AARCH64_NONE, + 0x10000101 => Type::AARCH64_ABS64, + 0x10000102 => Type::AARCH64_ABS32, + 0x10000103 => Type::AARCH64_ABS16, + 0x10000104 => Type::AARCH64_PREL64, + 0x10000105 => Type::AARCH64_PREL32, + 0x10000106 => Type::AARCH64_PREL16, + 0x10000107 => Type::AARCH64_MOVW_UABS_G0, + 0x10000108 => Type::AARCH64_MOVW_UABS_G0_NC, + 0x10000109 => Type::AARCH64_MOVW_UABS_G1, + 0x1000010a => Type::AARCH64_MOVW_UABS_G1_NC, + 0x1000010b => Type::AARCH64_MOVW_UABS_G2, + 0x1000010c => Type::AARCH64_MOVW_UABS_G2_NC, + 0x1000010d => Type::AARCH64_MOVW_UABS_G3, + 0x1000010e => Type::AARCH64_MOVW_SABS_G0, + 0x1000010f => Type::AARCH64_MOVW_SABS_G1, + 0x10000110 => Type::AARCH64_MOVW_SABS_G2, + 0x10000111 => Type::AARCH64_LD_PREL_LO19, + 0x10000112 => Type::AARCH64_ADR_PREL_LO21, + 0x10000113 => Type::AARCH64_ADR_PREL_PG_HI21, + 0x10000114 => Type::AARCH64_ADR_PREL_PG_HI21_NC, + 0x10000115 => Type::AARCH64_ADD_ABS_LO12_NC, + 0x10000116 => Type::AARCH64_LDST8_ABS_LO12_NC, + 0x10000117 => Type::AARCH64_TSTBR14, + 0x10000118 => Type::AARCH64_CONDBR19, + 0x1000011a => Type::AARCH64_JUMP26, + 0x1000011b => Type::AARCH64_CALL26, + 0x1000011c => Type::AARCH64_LDST16_ABS_LO12_NC, + 0x1000011d => Type::AARCH64_LDST32_ABS_LO12_NC, + 0x1000011e => Type::AARCH64_LDST64_ABS_LO12_NC, + 0x1000011f => Type::AARCH64_MOVW_PREL_G0, + 0x10000120 => Type::AARCH64_MOVW_PREL_G0_NC, + 0x10000121 => Type::AARCH64_MOVW_PREL_G1, + 0x10000122 => Type::AARCH64_MOVW_PREL_G1_NC, + 0x10000123 => Type::AARCH64_MOVW_PREL_G2, + 0x10000124 => Type::AARCH64_MOVW_PREL_G2_NC, + 0x10000125 => Type::AARCH64_MOVW_PREL_G3, + 0x1000012b => Type::AARCH64_LDST128_ABS_LO12_NC, + 0x1000012c => Type::AARCH64_MOVW_GOTOFF_G0, + 0x1000012d => Type::AARCH64_MOVW_GOTOFF_G0_NC, + 0x1000012e => Type::AARCH64_MOVW_GOTOFF_G1, + 0x1000012f => Type::AARCH64_MOVW_GOTOFF_G1_NC, + 0x10000130 => Type::AARCH64_MOVW_GOTOFF_G2, + 0x10000131 => Type::AARCH64_MOVW_GOTOFF_G2_NC, + 0x10000132 => Type::AARCH64_MOVW_GOTOFF_G3, + 0x10000133 => Type::AARCH64_GOTREL64, + 0x10000134 => Type::AARCH64_GOTREL32, + 0x10000135 => Type::AARCH64_GOT_LD_PREL19, + 0x10000136 => Type::AARCH64_LD64_GOTOFF_LO15, + 0x10000137 => Type::AARCH64_ADR_GOT_PAGE, + 0x10000138 => Type::AARCH64_LD64_GOT_LO12_NC, + 0x10000139 => Type::AARCH64_LD64_GOTPAGE_LO15, + 0x10000200 => Type::AARCH64_TLSGD_ADR_PREL21, + 0x10000201 => Type::AARCH64_TLSGD_ADR_PAGE21, + 0x10000202 => Type::AARCH64_TLSGD_ADD_LO12_NC, + 0x10000203 => Type::AARCH64_TLSGD_MOVW_G1, + 0x10000204 => Type::AARCH64_TLSGD_MOVW_G0_NC, + 0x10000205 => Type::AARCH64_TLSLD_ADR_PREL21, + 0x10000206 => Type::AARCH64_TLSLD_ADR_PAGE21, + 0x10000207 => Type::AARCH64_TLSLD_ADD_LO12_NC, + 0x10000208 => Type::AARCH64_TLSLD_MOVW_G1, + 0x10000209 => Type::AARCH64_TLSLD_MOVW_G0_NC, + 0x1000020a => Type::AARCH64_TLSLD_LD_PREL19, + 0x1000020b => Type::AARCH64_TLSLD_MOVW_DTPREL_G2, + 0x1000020c => Type::AARCH64_TLSLD_MOVW_DTPREL_G1, + 0x1000020d => Type::AARCH64_TLSLD_MOVW_DTPREL_G1_NC, + 0x1000020e => Type::AARCH64_TLSLD_MOVW_DTPREL_G0, + 0x1000020f => Type::AARCH64_TLSLD_MOVW_DTPREL_G0_NC, + 0x10000210 => Type::AARCH64_TLSLD_ADD_DTPREL_HI12, + 0x10000211 => Type::AARCH64_TLSLD_ADD_DTPREL_LO12, + 0x10000212 => Type::AARCH64_TLSLD_ADD_DTPREL_LO12_NC, + 0x10000213 => Type::AARCH64_TLSLD_LDST8_DTPREL_LO12, + 0x10000214 => Type::AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, + 0x10000215 => Type::AARCH64_TLSLD_LDST16_DTPREL_LO12, + 0x10000216 => Type::AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, + 0x10000217 => Type::AARCH64_TLSLD_LDST32_DTPREL_LO12, + 0x10000218 => Type::AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, + 0x10000219 => Type::AARCH64_TLSLD_LDST64_DTPREL_LO12, + 0x1000021a => Type::AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, + 0x1000021b => Type::AARCH64_TLSIE_MOVW_GOTTPREL_G1, + 0x1000021c => Type::AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, + 0x1000021d => Type::AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, + 0x1000021e => Type::AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, + 0x1000021f => Type::AARCH64_TLSIE_LD_GOTTPREL_PREL19, + 0x10000220 => Type::AARCH64_TLSLE_MOVW_TPREL_G2, + 0x10000221 => Type::AARCH64_TLSLE_MOVW_TPREL_G1, + 0x10000222 => Type::AARCH64_TLSLE_MOVW_TPREL_G1_NC, + 0x10000223 => Type::AARCH64_TLSLE_MOVW_TPREL_G0, + 0x10000224 => Type::AARCH64_TLSLE_MOVW_TPREL_G0_NC, + 0x10000225 => Type::AARCH64_TLSLE_ADD_TPREL_HI12, + 0x10000226 => Type::AARCH64_TLSLE_ADD_TPREL_LO12, + 0x10000227 => Type::AARCH64_TLSLE_ADD_TPREL_LO12_NC, + 0x10000228 => Type::AARCH64_TLSLE_LDST8_TPREL_LO12, + 0x10000229 => Type::AARCH64_TLSLE_LDST8_TPREL_LO12_NC, + 0x1000022a => Type::AARCH64_TLSLE_LDST16_TPREL_LO12, + 0x1000022b => Type::AARCH64_TLSLE_LDST16_TPREL_LO12_NC, + 0x1000022c => Type::AARCH64_TLSLE_LDST32_TPREL_LO12, + 0x1000022d => Type::AARCH64_TLSLE_LDST32_TPREL_LO12_NC, + 0x1000022e => Type::AARCH64_TLSLE_LDST64_TPREL_LO12, + 0x1000022f => Type::AARCH64_TLSLE_LDST64_TPREL_LO12_NC, + 0x10000230 => Type::AARCH64_TLSDESC_LD_PREL19, + 0x10000231 => Type::AARCH64_TLSDESC_ADR_PREL21, + 0x10000232 => Type::AARCH64_TLSDESC_ADR_PAGE21, + 0x10000233 => Type::AARCH64_TLSDESC_LD64_LO12_NC, + 0x10000234 => Type::AARCH64_TLSDESC_ADD_LO12_NC, + 0x10000235 => Type::AARCH64_TLSDESC_OFF_G1, + 0x10000236 => Type::AARCH64_TLSDESC_OFF_G0_NC, + 0x10000237 => Type::AARCH64_TLSDESC_LDR, + 0x10000238 => Type::AARCH64_TLSDESC_ADD, + 0x10000239 => Type::AARCH64_TLSDESC_CALL, + 0x1000023a => Type::AARCH64_TLSLE_LDST128_TPREL_LO12, + 0x1000023b => Type::AARCH64_TLSLE_LDST128_TPREL_LO12_NC, + 0x1000023c => Type::AARCH64_TLSLD_LDST128_DTPREL_LO12, + 0x1000023d => Type::AARCH64_TLSLD_LDST128_DTPREL_LO12_NC, + 0x10000400 => Type::AARCH64_COPY, + 0x10000401 => Type::AARCH64_GLOB_DAT, + 0x10000402 => Type::AARCH64_JUMP_SLOT, + 0x10000403 => Type::AARCH64_RELATIVE, + 0x10000404 => Type::AARCH64_TLS_DTPREL64, + 0x10000405 => Type::AARCH64_TLS_DTPMOD64, + 0x10000406 => Type::AARCH64_TLS_TPREL64, + 0x10000407 => Type::AARCH64_TLSDESC, + 0x10000408 => Type::AARCH64_IRELATIVE, + 0x18000000 => Type::ARM_NONE, + 0x18000001 => Type::ARM_PC24, + 0x18000002 => Type::ARM_ABS32, + 0x18000003 => Type::ARM_REL32, + 0x18000004 => Type::ARM_LDR_PC_G0, + 0x18000005 => Type::ARM_ABS16, + 0x18000006 => Type::ARM_ABS12, + 0x18000007 => Type::ARM_THM_ABS5, + 0x18000008 => Type::ARM_ABS8, + 0x18000009 => Type::ARM_SBREL32, + 0x1800000a => Type::ARM_THM_CALL, + 0x1800000b => Type::ARM_THM_PC8, + 0x1800000c => Type::ARM_BREL_ADJ, + 0x1800000d => Type::ARM_TLS_DESC, + 0x1800000e => Type::ARM_THM_SWI8, + 0x1800000f => Type::ARM_XPC25, + 0x18000010 => Type::ARM_THM_XPC22, + 0x18000011 => Type::ARM_TLS_DTPMOD32, + 0x18000012 => Type::ARM_TLS_DTPOFF32, + 0x18000013 => Type::ARM_TLS_TPOFF32, + 0x18000014 => Type::ARM_COPY, + 0x18000015 => Type::ARM_GLOB_DAT, + 0x18000016 => Type::ARM_JUMP_SLOT, + 0x18000017 => Type::ARM_RELATIVE, + 0x18000018 => Type::ARM_GOTOFF32, + 0x18000019 => Type::ARM_BASE_PREL, + 0x1800001a => Type::ARM_GOT_BREL, + 0x1800001b => Type::ARM_PLT32, + 0x1800001c => Type::ARM_CALL, + 0x1800001d => Type::ARM_JUMP24, + 0x1800001e => Type::ARM_THM_JUMP24, + 0x1800001f => Type::ARM_BASE_ABS, + 0x18000020 => Type::ARM_ALU_PCREL_7_0, + 0x18000021 => Type::ARM_ALU_PCREL_15_8, + 0x18000022 => Type::ARM_ALU_PCREL_23_15, + 0x18000023 => Type::ARM_LDR_SBREL_11_0_NC, + 0x18000024 => Type::ARM_ALU_SBREL_19_12_NC, + 0x18000025 => Type::ARM_ALU_SBREL_27_20_CK, + 0x18000026 => Type::ARM_TARGET1, + 0x18000027 => Type::ARM_SBREL31, + 0x18000028 => Type::ARM_V4BX, + 0x18000029 => Type::ARM_TARGET2, + 0x1800002a => Type::ARM_PREL31, + 0x1800002b => Type::ARM_MOVW_ABS_NC, + 0x1800002c => Type::ARM_MOVT_ABS, + 0x1800002d => Type::ARM_MOVW_PREL_NC, + 0x1800002e => Type::ARM_MOVT_PREL, + 0x1800002f => Type::ARM_THM_MOVW_ABS_NC, + 0x18000030 => Type::ARM_THM_MOVT_ABS, + 0x18000031 => Type::ARM_THM_MOVW_PREL_NC, + 0x18000032 => Type::ARM_THM_MOVT_PREL, + 0x18000033 => Type::ARM_THM_JUMP19, + 0x18000034 => Type::ARM_THM_JUMP6, + 0x18000035 => Type::ARM_THM_ALU_PREL_11_0, + 0x18000036 => Type::ARM_THM_PC12, + 0x18000037 => Type::ARM_ABS32_NOI, + 0x18000038 => Type::ARM_REL32_NOI, + 0x18000039 => Type::ARM_ALU_PC_G0_NC, + 0x1800003a => Type::ARM_ALU_PC_G0, + 0x1800003b => Type::ARM_ALU_PC_G1_NC, + 0x1800003c => Type::ARM_ALU_PC_G1, + 0x1800003d => Type::ARM_ALU_PC_G2, + 0x1800003e => Type::ARM_LDR_PC_G1, + 0x1800003f => Type::ARM_LDR_PC_G2, + 0x18000040 => Type::ARM_LDRS_PC_G0, + 0x18000041 => Type::ARM_LDRS_PC_G1, + 0x18000042 => Type::ARM_LDRS_PC_G2, + 0x18000043 => Type::ARM_LDC_PC_G0, + 0x18000044 => Type::ARM_LDC_PC_G1, + 0x18000045 => Type::ARM_LDC_PC_G2, + 0x18000046 => Type::ARM_ALU_SB_G0_NC, + 0x18000047 => Type::ARM_ALU_SB_G0, + 0x18000048 => Type::ARM_ALU_SB_G1_NC, + 0x18000049 => Type::ARM_ALU_SB_G1, + 0x1800004a => Type::ARM_ALU_SB_G2, + 0x1800004b => Type::ARM_LDR_SB_G0, + 0x1800004c => Type::ARM_LDR_SB_G1, + 0x1800004d => Type::ARM_LDR_SB_G2, + 0x1800004e => Type::ARM_LDRS_SB_G0, + 0x1800004f => Type::ARM_LDRS_SB_G1, + 0x18000050 => Type::ARM_LDRS_SB_G2, + 0x18000051 => Type::ARM_LDC_SB_G0, + 0x18000052 => Type::ARM_LDC_SB_G1, + 0x18000053 => Type::ARM_LDC_SB_G2, + 0x18000054 => Type::ARM_MOVW_BREL_NC, + 0x18000055 => Type::ARM_MOVT_BREL, + 0x18000056 => Type::ARM_MOVW_BREL, + 0x18000057 => Type::ARM_THM_MOVW_BREL_NC, + 0x18000058 => Type::ARM_THM_MOVT_BREL, + 0x18000059 => Type::ARM_THM_MOVW_BREL, + 0x1800005a => Type::ARM_TLS_GOTDESC, + 0x1800005b => Type::ARM_TLS_CALL, + 0x1800005c => Type::ARM_TLS_DESCSEQ, + 0x1800005d => Type::ARM_THM_TLS_CALL, + 0x1800005e => Type::ARM_PLT32_ABS, + 0x1800005f => Type::ARM_GOT_ABS, + 0x18000060 => Type::ARM_GOT_PREL, + 0x18000061 => Type::ARM_GOT_BREL12, + 0x18000062 => Type::ARM_GOTOFF12, + 0x18000063 => Type::ARM_GOTRELAX, + 0x18000064 => Type::ARM_GNU_VTENTRY, + 0x18000065 => Type::ARM_GNU_VTINHERIT, + 0x18000066 => Type::ARM_THM_JUMP11, + 0x18000067 => Type::ARM_THM_JUMP8, + 0x18000068 => Type::ARM_TLS_GD32, + 0x18000069 => Type::ARM_TLS_LDM32, + 0x1800006a => Type::ARM_TLS_LDO32, + 0x1800006b => Type::ARM_TLS_IE32, + 0x1800006c => Type::ARM_TLS_LE32, + 0x1800006d => Type::ARM_TLS_LDO12, + 0x1800006e => Type::ARM_TLS_LE12, + 0x1800006f => Type::ARM_TLS_IE12GP, + 0x18000070 => Type::ARM_PRIVATE_0, + 0x18000071 => Type::ARM_PRIVATE_1, + 0x18000072 => Type::ARM_PRIVATE_2, + 0x18000073 => Type::ARM_PRIVATE_3, + 0x18000074 => Type::ARM_PRIVATE_4, + 0x18000075 => Type::ARM_PRIVATE_5, + 0x18000076 => Type::ARM_PRIVATE_6, + 0x18000077 => Type::ARM_PRIVATE_7, + 0x18000078 => Type::ARM_PRIVATE_8, + 0x18000079 => Type::ARM_PRIVATE_9, + 0x1800007a => Type::ARM_PRIVATE_10, + 0x1800007b => Type::ARM_PRIVATE_11, + 0x1800007c => Type::ARM_PRIVATE_12, + 0x1800007d => Type::ARM_PRIVATE_13, + 0x1800007e => Type::ARM_PRIVATE_14, + 0x1800007f => Type::ARM_PRIVATE_15, + 0x18000080 => Type::ARM_ME_TOO, + 0x18000081 => Type::ARM_THM_TLS_DESCSEQ16, + 0x18000082 => Type::ARM_THM_TLS_DESCSEQ32, + 0x180000a0 => Type::ARM_IRELATIVE, + 0x180000f9 => Type::ARM_RXPC25, + 0x180000fa => Type::ARM_RSBREL32, + 0x180000fb => Type::ARM_THM_RPC22, + 0x180000fc => Type::ARM_RREL32, + 0x180000fd => Type::ARM_RPC24, + 0x180000fe => Type::ARM_RBASE, + 0x20000000 => Type::HEX_NONE, + 0x20000001 => Type::HEX_B22_PCREL, + 0x20000002 => Type::HEX_B15_PCREL, + 0x20000003 => Type::HEX_B7_PCREL, + 0x20000004 => Type::HEX_LO16, + 0x20000005 => Type::HEX_HI16, + 0x20000006 => Type::HEX_32, + 0x20000007 => Type::HEX_16, + 0x20000008 => Type::HEX_8, + 0x20000009 => Type::HEX_GPREL16_0, + 0x2000000a => Type::HEX_GPREL16_1, + 0x2000000b => Type::HEX_GPREL16_2, + 0x2000000c => Type::HEX_GPREL16_3, + 0x2000000d => Type::HEX_HL16, + 0x2000000e => Type::HEX_B13_PCREL, + 0x2000000f => Type::HEX_B9_PCREL, + 0x20000010 => Type::HEX_B32_PCREL_X, + 0x20000011 => Type::HEX_32_6_X, + 0x20000012 => Type::HEX_B22_PCREL_X, + 0x20000013 => Type::HEX_B15_PCREL_X, + 0x20000014 => Type::HEX_B13_PCREL_X, + 0x20000015 => Type::HEX_B9_PCREL_X, + 0x20000016 => Type::HEX_B7_PCREL_X, + 0x20000017 => Type::HEX_16_X, + 0x20000018 => Type::HEX_12_X, + 0x20000019 => Type::HEX_11_X, + 0x2000001a => Type::HEX_10_X, + 0x2000001b => Type::HEX_9_X, + 0x2000001c => Type::HEX_8_X, + 0x2000001d => Type::HEX_7_X, + 0x2000001e => Type::HEX_6_X, + 0x2000001f => Type::HEX_32_PCREL, + 0x20000020 => Type::HEX_COPY, + 0x20000021 => Type::HEX_GLOB_DAT, + 0x20000022 => Type::HEX_JMP_SLOT, + 0x20000023 => Type::HEX_RELATIVE, + 0x20000024 => Type::HEX_PLT_B22_PCREL, + 0x20000025 => Type::HEX_GOTREL_LO16, + 0x20000026 => Type::HEX_GOTREL_HI16, + 0x20000027 => Type::HEX_GOTREL_32, + 0x20000028 => Type::HEX_GOT_LO16, + 0x20000029 => Type::HEX_GOT_HI16, + 0x2000002a => Type::HEX_GOT_32, + 0x2000002b => Type::HEX_GOT_16, + 0x2000002c => Type::HEX_DTPMOD_32, + 0x2000002d => Type::HEX_DTPREL_LO16, + 0x2000002e => Type::HEX_DTPREL_HI16, + 0x2000002f => Type::HEX_DTPREL_32, + 0x20000030 => Type::HEX_DTPREL_16, + 0x20000031 => Type::HEX_GD_PLT_B22_PCREL, + 0x20000032 => Type::HEX_GD_GOT_LO16, + 0x20000033 => Type::HEX_GD_GOT_HI16, + 0x20000034 => Type::HEX_GD_GOT_32, + 0x20000035 => Type::HEX_GD_GOT_16, + 0x20000036 => Type::HEX_IE_LO16, + 0x20000037 => Type::HEX_IE_HI16, + 0x20000038 => Type::HEX_IE_32, + 0x20000039 => Type::HEX_IE_GOT_LO16, + 0x2000003a => Type::HEX_IE_GOT_HI16, + 0x2000003b => Type::HEX_IE_GOT_32, + 0x2000003c => Type::HEX_IE_GOT_16, + 0x2000003d => Type::HEX_TPREL_LO16, + 0x2000003e => Type::HEX_TPREL_HI16, + 0x2000003f => Type::HEX_TPREL_32, + 0x20000040 => Type::HEX_TPREL_16, + 0x20000041 => Type::HEX_6_PCREL_X, + 0x20000042 => Type::HEX_GOTREL_32_6_X, + 0x20000043 => Type::HEX_GOTREL_16_X, + 0x20000044 => Type::HEX_GOTREL_11_X, + 0x20000045 => Type::HEX_GOT_32_6_X, + 0x20000046 => Type::HEX_GOT_16_X, + 0x20000047 => Type::HEX_GOT_11_X, + 0x20000048 => Type::HEX_DTPREL_32_6_X, + 0x20000049 => Type::HEX_DTPREL_16_X, + 0x2000004a => Type::HEX_DTPREL_11_X, + 0x2000004b => Type::HEX_GD_GOT_32_6_X, + 0x2000004c => Type::HEX_GD_GOT_16_X, + 0x2000004d => Type::HEX_GD_GOT_11_X, + 0x2000004e => Type::HEX_IE_32_6_X, + 0x2000004f => Type::HEX_IE_16_X, + 0x20000050 => Type::HEX_IE_GOT_32_6_X, + 0x20000051 => Type::HEX_IE_GOT_16_X, + 0x20000052 => Type::HEX_IE_GOT_11_X, + 0x20000053 => Type::HEX_TPREL_32_6_X, + 0x20000054 => Type::HEX_TPREL_16_X, + 0x20000055 => Type::HEX_TPREL_11_X, + 0x20000056 => Type::HEX_LD_PLT_B22_PCREL, + 0x20000057 => Type::HEX_LD_GOT_LO16, + 0x20000058 => Type::HEX_LD_GOT_HI16, + 0x20000059 => Type::HEX_LD_GOT_32, + 0x2000005a => Type::HEX_LD_GOT_16, + 0x2000005b => Type::HEX_LD_GOT_32_6_X, + 0x2000005c => Type::HEX_LD_GOT_16_X, + 0x2000005d => Type::HEX_LD_GOT_11_X, + 0x28000000 => Type::X86_NONE, + 0x28000001 => Type::X86_32, + 0x28000002 => Type::X86_PC32, + 0x28000003 => Type::X86_GOT32, + 0x28000004 => Type::X86_PLT32, + 0x28000005 => Type::X86_COPY, + 0x28000006 => Type::X86_GLOB_DAT, + 0x28000007 => Type::X86_JUMP_SLOT, + 0x28000008 => Type::X86_RELATIVE, + 0x28000009 => Type::X86_GOTOFF, + 0x2800000a => Type::X86_GOTPC, + 0x2800000b => Type::X86_32PLT, + 0x2800000e => Type::X86_TLS_TPOFF, + 0x2800000f => Type::X86_TLS_IE, + 0x28000010 => Type::X86_TLS_GOTIE, + 0x28000011 => Type::X86_TLS_LE, + 0x28000012 => Type::X86_TLS_GD, + 0x28000013 => Type::X86_TLS_LDM, + 0x28000014 => Type::X86_16, + 0x28000015 => Type::X86_PC16, + 0x28000016 => Type::X86_8, + 0x28000017 => Type::X86_PC8, + 0x28000018 => Type::X86_TLS_GD_32, + 0x28000019 => Type::X86_TLS_GD_PUSH, + 0x2800001a => Type::X86_TLS_GD_CALL, + 0x2800001b => Type::X86_TLS_GD_POP, + 0x2800001c => Type::X86_TLS_LDM_32, + 0x2800001d => Type::X86_TLS_LDM_PUSH, + 0x2800001e => Type::X86_TLS_LDM_CALL, + 0x2800001f => Type::X86_TLS_LDM_POP, + 0x28000020 => Type::X86_TLS_LDO_32, + 0x28000021 => Type::X86_TLS_IE_32, + 0x28000022 => Type::X86_TLS_LE_32, + 0x28000023 => Type::X86_TLS_DTPMOD32, + 0x28000024 => Type::X86_TLS_DTPOFF32, + 0x28000025 => Type::X86_TLS_TPOFF32, + 0x28000027 => Type::X86_TLS_GOTDESC, + 0x28000028 => Type::X86_TLS_DESC_CALL, + 0x28000029 => Type::X86_TLS_DESC, + 0x2800002a => Type::X86_IRELATIVE, + 0x30000000 => Type::LARCH_NONE, + 0x30000001 => Type::LARCH_32, + 0x30000002 => Type::LARCH_64, + 0x30000003 => Type::LARCH_RELATIVE, + 0x30000004 => Type::LARCH_COPY, + 0x30000005 => Type::LARCH_JUMP_SLOT, + 0x30000006 => Type::LARCH_TLS_DTPMOD32, + 0x30000007 => Type::LARCH_TLS_DTPMOD64, + 0x30000008 => Type::LARCH_TLS_DTPREL32, + 0x30000009 => Type::LARCH_TLS_DTPREL64, + 0x3000000a => Type::LARCH_TLS_TPREL32, + 0x3000000b => Type::LARCH_TLS_TPREL64, + 0x3000000c => Type::LARCH_IRELATIVE, + 0x30000014 => Type::LARCH_MARK_LA, + 0x30000015 => Type::LARCH_MARK_PCREL, + 0x30000016 => Type::LARCH_SOP_PUSH_PCREL, + 0x30000017 => Type::LARCH_SOP_PUSH_ABSOLUTE, + 0x30000018 => Type::LARCH_SOP_PUSH_DUP, + 0x30000019 => Type::LARCH_SOP_PUSH_GPREL, + 0x3000001a => Type::LARCH_SOP_PUSH_TLS_TPREL, + 0x3000001b => Type::LARCH_SOP_PUSH_TLS_GOT, + 0x3000001c => Type::LARCH_SOP_PUSH_TLS_GD, + 0x3000001d => Type::LARCH_SOP_PUSH_PLT_PCREL, + 0x3000001e => Type::LARCH_SOP_ASSERT, + 0x3000001f => Type::LARCH_SOP_NOT, + 0x30000020 => Type::LARCH_SOP_SUB, + 0x30000021 => Type::LARCH_SOP_SL, + 0x30000022 => Type::LARCH_SOP_SR, + 0x30000023 => Type::LARCH_SOP_ADD, + 0x30000024 => Type::LARCH_SOP_AND, + 0x30000025 => Type::LARCH_SOP_IF_ELSE, + 0x30000026 => Type::LARCH_SOP_POP_32_S_10_5, + 0x30000027 => Type::LARCH_SOP_POP_32_U_10_12, + 0x30000028 => Type::LARCH_SOP_POP_32_S_10_12, + 0x30000029 => Type::LARCH_SOP_POP_32_S_10_16, + 0x3000002a => Type::LARCH_SOP_POP_32_S_10_16_S2, + 0x3000002b => Type::LARCH_SOP_POP_32_S_5_20, + 0x3000002c => Type::LARCH_SOP_POP_32_S_0_5_10_16_S2, + 0x3000002d => Type::LARCH_SOP_POP_32_S_0_10_10_16_S2, + 0x3000002e => Type::LARCH_SOP_POP_32_U, + 0x3000002f => Type::LARCH_ADD8, + 0x30000030 => Type::LARCH_ADD16, + 0x30000031 => Type::LARCH_ADD24, + 0x30000032 => Type::LARCH_ADD32, + 0x30000033 => Type::LARCH_ADD64, + 0x30000034 => Type::LARCH_SUB8, + 0x30000035 => Type::LARCH_SUB16, + 0x30000036 => Type::LARCH_SUB24, + 0x30000037 => Type::LARCH_SUB32, + 0x30000038 => Type::LARCH_SUB64, + 0x30000039 => Type::LARCH_GNU_VTINHERIT, + 0x3000003a => Type::LARCH_GNU_VTENTRY, + 0x30000040 => Type::LARCH_B16, + 0x30000041 => Type::LARCH_B21, + 0x30000042 => Type::LARCH_B26, + 0x30000043 => Type::LARCH_ABS_HI20, + 0x30000044 => Type::LARCH_ABS_LO12, + 0x30000045 => Type::LARCH_ABS64_LO20, + 0x30000046 => Type::LARCH_ABS64_HI12, + 0x30000047 => Type::LARCH_PCALA_HI20, + 0x30000048 => Type::LARCH_PCALA_LO12, + 0x30000049 => Type::LARCH_PCALA64_LO20, + 0x3000004a => Type::LARCH_PCALA64_HI12, + 0x3000004b => Type::LARCH_GOT_PC_HI20, + 0x3000004c => Type::LARCH_GOT_PC_LO12, + 0x3000004d => Type::LARCH_GOT64_PC_LO20, + 0x3000004e => Type::LARCH_GOT64_PC_HI12, + 0x3000004f => Type::LARCH_GOT_HI20, + 0x30000050 => Type::LARCH_GOT_LO12, + 0x30000051 => Type::LARCH_GOT64_LO20, + 0x30000052 => Type::LARCH_GOT64_HI12, + 0x30000053 => Type::LARCH_TLS_LE_HI20, + 0x30000054 => Type::LARCH_TLS_LE_LO12, + 0x30000055 => Type::LARCH_TLS_LE64_LO20, + 0x30000056 => Type::LARCH_TLS_LE64_HI12, + 0x30000057 => Type::LARCH_TLS_IE_PC_HI20, + 0x30000058 => Type::LARCH_TLS_IE_PC_LO12, + 0x30000059 => Type::LARCH_TLS_IE64_PC_LO20, + 0x3000005a => Type::LARCH_TLS_IE64_PC_HI12, + 0x3000005b => Type::LARCH_TLS_IE_HI20, + 0x3000005c => Type::LARCH_TLS_IE_LO12, + 0x3000005d => Type::LARCH_TLS_IE64_LO20, + 0x3000005e => Type::LARCH_TLS_IE64_HI12, + 0x3000005f => Type::LARCH_TLS_LD_PC_HI20, + 0x30000060 => Type::LARCH_TLS_LD_HI20, + 0x30000061 => Type::LARCH_TLS_GD_PC_HI20, + 0x30000062 => Type::LARCH_TLS_GD_HI20, + 0x30000063 => Type::LARCH_32_PCREL, + 0x30000064 => Type::LARCH_RELAX, + 0x30000066 => Type::LARCH_ALIGN, + 0x30000067 => Type::LARCH_PCREL20_S2, + 0x30000069 => Type::LARCH_ADD6, + 0x3000006a => Type::LARCH_SUB6, + 0x3000006b => Type::LARCH_ADD_ULEB128, + 0x3000006c => Type::LARCH_SUB_ULEB128, + 0x3000006d => Type::LARCH_64_PCREL, + 0x3000006e => Type::LARCH_CALL36, + 0x3000000d => Type::LARCH_TLS_DESC32, + 0x3000000e => Type::LARCH_TLS_DESC64, + 0x3000006f => Type::LARCH_TLS_DESC_PC_HI20, + 0x30000070 => Type::LARCH_TLS_DESC_PC_LO12, + 0x30000071 => Type::LARCH_TLS_DESC64_PC_LO20, + 0x30000072 => Type::LARCH_TLS_DESC64_PC_HI12, + 0x30000073 => Type::LARCH_TLS_DESC_HI20, + 0x30000074 => Type::LARCH_TLS_DESC_LO12, + 0x30000075 => Type::LARCH_TLS_DESC64_LO20, + 0x30000076 => Type::LARCH_TLS_DESC64_HI12, + 0x30000077 => Type::LARCH_TLS_DESC_LD, + 0x30000078 => Type::LARCH_TLS_DESC_CALL, + 0x30000079 => Type::LARCH_TLS_LE_HI20_R, + 0x3000007a => Type::LARCH_TLS_LE_ADD_R, + 0x3000007b => Type::LARCH_TLS_LE_LO12_R, + 0x3000007c => Type::LARCH_TLS_LD_PCREL20_S2, + 0x3000007d => Type::LARCH_TLS_GD_PCREL20_S2, + 0x3000007e => Type::LARCH_TLS_DESC_PCREL20_S2, + 0x38000000 => Type::MIPS_NONE, + 0x38000001 => Type::MIPS_16, + 0x38000002 => Type::MIPS_32, + 0x38000003 => Type::MIPS_REL32, + 0x38000004 => Type::MIPS_26, + 0x38000005 => Type::MIPS_HI16, + 0x38000006 => Type::MIPS_LO16, + 0x38000007 => Type::MIPS_GPREL16, + 0x38000008 => Type::MIPS_LITERAL, + 0x38000009 => Type::MIPS_GOT16, + 0x3800000a => Type::MIPS_PC16, + 0x3800000b => Type::MIPS_CALL16, + 0x3800000c => Type::MIPS_GPREL32, + 0x3800000d => Type::MIPS_UNUSED1, + 0x3800000e => Type::MIPS_UNUSED2, + 0x3800000f => Type::MIPS_UNUSED3, + 0x38000010 => Type::MIPS_SHIFT5, + 0x38000011 => Type::MIPS_SHIFT6, + 0x38000012 => Type::MIPS_64, + 0x38000013 => Type::MIPS_GOT_DISP, + 0x38000014 => Type::MIPS_GOT_PAGE, + 0x38000015 => Type::MIPS_GOT_OFST, + 0x38000016 => Type::MIPS_GOT_HI16, + 0x38000017 => Type::MIPS_GOT_LO16, + 0x38000018 => Type::MIPS_SUB, + 0x38000019 => Type::MIPS_INSERT_A, + 0x3800001a => Type::MIPS_INSERT_B, + 0x3800001b => Type::MIPS_DELETE, + 0x3800001c => Type::MIPS_HIGHER, + 0x3800001d => Type::MIPS_HIGHEST, + 0x3800001e => Type::MIPS_CALL_HI16, + 0x3800001f => Type::MIPS_CALL_LO16, + 0x38000020 => Type::MIPS_SCN_DISP, + 0x38000021 => Type::MIPS_REL16, + 0x38000022 => Type::MIPS_ADD_IMMEDIATE, + 0x38000023 => Type::MIPS_PJUMP, + 0x38000024 => Type::MIPS_RELGOT, + 0x38000025 => Type::MIPS_JALR, + 0x38000026 => Type::MIPS_TLS_DTPMOD32, + 0x38000027 => Type::MIPS_TLS_DTPREL32, + 0x38000028 => Type::MIPS_TLS_DTPMOD64, + 0x38000029 => Type::MIPS_TLS_DTPREL64, + 0x3800002a => Type::MIPS_TLS_GD, + 0x3800002b => Type::MIPS_TLS_LDM, + 0x3800002c => Type::MIPS_TLS_DTPREL_HI16, + 0x3800002d => Type::MIPS_TLS_DTPREL_LO16, + 0x3800002e => Type::MIPS_TLS_GOTTPREL, + 0x3800002f => Type::MIPS_TLS_TPREL32, + 0x38000030 => Type::MIPS_TLS_TPREL64, + 0x38000031 => Type::MIPS_TLS_TPREL_HI16, + 0x38000032 => Type::MIPS_TLS_TPREL_LO16, + 0x38000033 => Type::MIPS_GLOB_DAT, + 0x3800003c => Type::MIPS_PC21_S2, + 0x3800003d => Type::MIPS_PC26_S2, + 0x3800003e => Type::MIPS_PC18_S3, + 0x3800003f => Type::MIPS_PC19_S2, + 0x38000040 => Type::MIPS_PCHI16, + 0x38000041 => Type::MIPS_PCLO16, + 0x38000064 => Type::MIPS16_26, + 0x38000065 => Type::MIPS16_GPREL, + 0x38000066 => Type::MIPS16_GOT16, + 0x38000067 => Type::MIPS16_CALL16, + 0x38000068 => Type::MIPS16_HI16, + 0x38000069 => Type::MIPS16_LO16, + 0x3800006a => Type::MIPS16_TLS_GD, + 0x3800006b => Type::MIPS16_TLS_LDM, + 0x3800006c => Type::MIPS16_TLS_DTPREL_HI16, + 0x3800006d => Type::MIPS16_TLS_DTPREL_LO16, + 0x3800006e => Type::MIPS16_TLS_GOTTPREL, + 0x3800006f => Type::MIPS16_TLS_TPREL_HI16, + 0x38000070 => Type::MIPS16_TLS_TPREL_LO16, + 0x3800007e => Type::MIPS_COPY, + 0x3800007f => Type::MIPS_JUMP_SLOT, + 0x38000085 => Type::MICROMIPS_26_S1, + 0x38000086 => Type::MICROMIPS_HI16, + 0x38000087 => Type::MICROMIPS_LO16, + 0x38000088 => Type::MICROMIPS_GPREL16, + 0x38000089 => Type::MICROMIPS_LITERAL, + 0x3800008a => Type::MICROMIPS_GOT16, + 0x3800008b => Type::MICROMIPS_PC7_S1, + 0x3800008c => Type::MICROMIPS_PC10_S1, + 0x3800008d => Type::MICROMIPS_PC16_S1, + 0x3800008e => Type::MICROMIPS_CALL16, + 0x38000091 => Type::MICROMIPS_GOT_DISP, + 0x38000092 => Type::MICROMIPS_GOT_PAGE, + 0x38000093 => Type::MICROMIPS_GOT_OFST, + 0x38000094 => Type::MICROMIPS_GOT_HI16, + 0x38000095 => Type::MICROMIPS_GOT_LO16, + 0x38000096 => Type::MICROMIPS_SUB, + 0x38000097 => Type::MICROMIPS_HIGHER, + 0x38000098 => Type::MICROMIPS_HIGHEST, + 0x38000099 => Type::MICROMIPS_CALL_HI16, + 0x3800009a => Type::MICROMIPS_CALL_LO16, + 0x3800009b => Type::MICROMIPS_SCN_DISP, + 0x3800009c => Type::MICROMIPS_JALR, + 0x3800009d => Type::MICROMIPS_HI0_LO16, + 0x380000a2 => Type::MICROMIPS_TLS_GD, + 0x380000a3 => Type::MICROMIPS_TLS_LDM, + 0x380000a4 => Type::MICROMIPS_TLS_DTPREL_HI16, + 0x380000a5 => Type::MICROMIPS_TLS_DTPREL_LO16, + 0x380000a6 => Type::MICROMIPS_TLS_GOTTPREL, + 0x380000a9 => Type::MICROMIPS_TLS_TPREL_HI16, + 0x380000aa => Type::MICROMIPS_TLS_TPREL_LO16, + 0x380000ac => Type::MICROMIPS_GPREL7_S2, + 0x380000ad => Type::MICROMIPS_PC23_S2, + 0x380000ae => Type::MICROMIPS_PC21_S2, + 0x380000af => Type::MICROMIPS_PC26_S2, + 0x380000b0 => Type::MICROMIPS_PC18_S3, + 0x380000b1 => Type::MICROMIPS_PC19_S2, + 0x380000da => Type::MIPS_NUM, + 0x380000f8 => Type::MIPS_PC32, + 0x380000f9 => Type::MIPS_EH, + 0x40000000 => Type::PPC_NONE, + 0x40000001 => Type::PPC_ADDR32, + 0x40000002 => Type::PPC_ADDR24, + 0x40000003 => Type::PPC_ADDR16, + 0x40000004 => Type::PPC_ADDR16_LO, + 0x40000005 => Type::PPC_ADDR16_HI, + 0x40000006 => Type::PPC_ADDR16_HA, + 0x40000007 => Type::PPC_ADDR14, + 0x40000008 => Type::PPC_ADDR14_BRTAKEN, + 0x40000009 => Type::PPC_ADDR14_BRNTAKEN, + 0x4000000a => Type::PPC_REL24, + 0x4000000b => Type::PPC_REL14, + 0x4000000c => Type::PPC_REL14_BRTAKEN, + 0x4000000d => Type::PPC_REL14_BRNTAKEN, + 0x4000000e => Type::PPC_GOT16, + 0x4000000f => Type::PPC_GOT16_LO, + 0x40000010 => Type::PPC_GOT16_HI, + 0x40000011 => Type::PPC_GOT16_HA, + 0x40000012 => Type::PPC_PLTREL24, + 0x40000015 => Type::PPC_JMP_SLOT, + 0x40000016 => Type::PPC_RELATIVE, + 0x40000017 => Type::PPC_LOCAL24PC, + 0x4000001a => Type::PPC_REL32, + 0x40000043 => Type::PPC_TLS, + 0x40000044 => Type::PPC_DTPMOD32, + 0x40000045 => Type::PPC_TPREL16, + 0x40000046 => Type::PPC_TPREL16_LO, + 0x40000047 => Type::PPC_TPREL16_HI, + 0x40000048 => Type::PPC_TPREL16_HA, + 0x40000049 => Type::PPC_TPREL32, + 0x4000004a => Type::PPC_DTPREL16, + 0x4000004b => Type::PPC_DTPREL16_LO, + 0x4000004c => Type::PPC_DTPREL16_HI, + 0x4000004d => Type::PPC_DTPREL16_HA, + 0x4000004e => Type::PPC_DTPREL32, + 0x4000004f => Type::PPC_GOT_TLSGD16, + 0x40000050 => Type::PPC_GOT_TLSGD16_LO, + 0x40000051 => Type::PPC_GOT_TLSGD16_HI, + 0x40000052 => Type::PPC_GOT_TLSGD16_HA, + 0x40000053 => Type::PPC_GOT_TLSLD16, + 0x40000054 => Type::PPC_GOT_TLSLD16_LO, + 0x40000055 => Type::PPC_GOT_TLSLD16_HI, + 0x40000056 => Type::PPC_GOT_TLSLD16_HA, + 0x40000057 => Type::PPC_GOT_TPREL16, + 0x40000058 => Type::PPC_GOT_TPREL16_LO, + 0x40000059 => Type::PPC_GOT_TPREL16_HI, + 0x4000005a => Type::PPC_GOT_TPREL16_HA, + 0x4000005b => Type::PPC_GOT_DTPREL16, + 0x4000005c => Type::PPC_GOT_DTPREL16_LO, + 0x4000005d => Type::PPC_GOT_DTPREL16_HI, + 0x4000005e => Type::PPC_GOT_DTPREL16_HA, + 0x4000005f => Type::PPC_TLSGD, + 0x40000060 => Type::PPC_TLSLD, + 0x400000f9 => Type::PPC_REL16, + 0x400000fa => Type::PPC_REL16_LO, + 0x400000fb => Type::PPC_REL16_HI, + 0x400000fc => Type::PPC_REL16_HA, + 0x48000000 => Type::PPC64_NONE, + 0x48000001 => Type::PPC64_ADDR32, + 0x48000002 => Type::PPC64_ADDR24, + 0x48000003 => Type::PPC64_ADDR16, + 0x48000004 => Type::PPC64_ADDR16_LO, + 0x48000005 => Type::PPC64_ADDR16_HI, + 0x48000006 => Type::PPC64_ADDR16_HA, + 0x48000007 => Type::PPC64_ADDR14, + 0x48000008 => Type::PPC64_ADDR14_BRTAKEN, + 0x48000009 => Type::PPC64_ADDR14_BRNTAKEN, + 0x4800000a => Type::PPC64_REL24, + 0x4800000b => Type::PPC64_REL14, + 0x4800000c => Type::PPC64_REL14_BRTAKEN, + 0x4800000d => Type::PPC64_REL14_BRNTAKEN, + 0x4800000e => Type::PPC64_GOT16, + 0x4800000f => Type::PPC64_GOT16_LO, + 0x48000010 => Type::PPC64_GOT16_HI, + 0x48000011 => Type::PPC64_GOT16_HA, + 0x48000015 => Type::PPC64_JMP_SLOT, + 0x48000016 => Type::PPC64_RELATIVE, + 0x4800001a => Type::PPC64_REL32, + 0x48000026 => Type::PPC64_ADDR64, + 0x48000027 => Type::PPC64_ADDR16_HIGHER, + 0x48000028 => Type::PPC64_ADDR16_HIGHERA, + 0x48000029 => Type::PPC64_ADDR16_HIGHEST, + 0x4800002a => Type::PPC64_ADDR16_HIGHESTA, + 0x4800002c => Type::PPC64_REL64, + 0x4800002f => Type::PPC64_TOC16, + 0x48000030 => Type::PPC64_TOC16_LO, + 0x48000031 => Type::PPC64_TOC16_HI, + 0x48000032 => Type::PPC64_TOC16_HA, + 0x48000033 => Type::PPC64_TOC, + 0x48000038 => Type::PPC64_ADDR16_DS, + 0x48000039 => Type::PPC64_ADDR16_LO_DS, + 0x4800003a => Type::PPC64_GOT16_DS, + 0x4800003b => Type::PPC64_GOT16_LO_DS, + 0x4800003f => Type::PPC64_TOC16_DS, + 0x48000040 => Type::PPC64_TOC16_LO_DS, + 0x48000043 => Type::PPC64_TLS, + 0x48000044 => Type::PPC64_DTPMOD64, + 0x48000045 => Type::PPC64_TPREL16, + 0x48000046 => Type::PPC64_TPREL16_LO, + 0x48000047 => Type::PPC64_TPREL16_HI, + 0x48000048 => Type::PPC64_TPREL16_HA, + 0x48000049 => Type::PPC64_TPREL64, + 0x4800004a => Type::PPC64_DTPREL16, + 0x4800004b => Type::PPC64_DTPREL16_LO, + 0x4800004c => Type::PPC64_DTPREL16_HI, + 0x4800004d => Type::PPC64_DTPREL16_HA, + 0x4800004e => Type::PPC64_DTPREL64, + 0x4800004f => Type::PPC64_GOT_TLSGD16, + 0x48000050 => Type::PPC64_GOT_TLSGD16_LO, + 0x48000051 => Type::PPC64_GOT_TLSGD16_HI, + 0x48000052 => Type::PPC64_GOT_TLSGD16_HA, + 0x48000053 => Type::PPC64_GOT_TLSLD16, + 0x48000054 => Type::PPC64_GOT_TLSLD16_LO, + 0x48000055 => Type::PPC64_GOT_TLSLD16_HI, + 0x48000056 => Type::PPC64_GOT_TLSLD16_HA, + 0x48000057 => Type::PPC64_GOT_TPREL16_DS, + 0x48000058 => Type::PPC64_GOT_TPREL16_LO_DS, + 0x48000059 => Type::PPC64_GOT_TPREL16_HI, + 0x4800005a => Type::PPC64_GOT_TPREL16_HA, + 0x4800005b => Type::PPC64_GOT_DTPREL16_DS, + 0x4800005c => Type::PPC64_GOT_DTPREL16_LO_DS, + 0x4800005d => Type::PPC64_GOT_DTPREL16_HI, + 0x4800005e => Type::PPC64_GOT_DTPREL16_HA, + 0x4800005f => Type::PPC64_TPREL16_DS, + 0x48000060 => Type::PPC64_TPREL16_LO_DS, + 0x48000061 => Type::PPC64_TPREL16_HIGHER, + 0x48000062 => Type::PPC64_TPREL16_HIGHERA, + 0x48000063 => Type::PPC64_TPREL16_HIGHEST, + 0x48000064 => Type::PPC64_TPREL16_HIGHESTA, + 0x48000065 => Type::PPC64_DTPREL16_DS, + 0x48000066 => Type::PPC64_DTPREL16_LO_DS, + 0x48000067 => Type::PPC64_DTPREL16_HIGHER, + 0x48000068 => Type::PPC64_DTPREL16_HIGHERA, + 0x48000069 => Type::PPC64_DTPREL16_HIGHEST, + 0x4800006a => Type::PPC64_DTPREL16_HIGHESTA, + 0x4800006b => Type::PPC64_TLSGD, + 0x4800006c => Type::PPC64_TLSLD, + 0x480000f9 => Type::PPC64_REL16, + 0x480000fa => Type::PPC64_REL16_LO, + 0x480000fb => Type::PPC64_REL16_HI, + 0x480000fc => Type::PPC64_REL16_HA, + 0x50000000 => Type::SPARC_NONE, + 0x50000001 => Type::SPARC_8, + 0x50000002 => Type::SPARC_16, + 0x50000003 => Type::SPARC_32, + 0x50000004 => Type::SPARC_DISP8, + 0x50000005 => Type::SPARC_DISP16, + 0x50000006 => Type::SPARC_DISP32, + 0x50000007 => Type::SPARC_WDISP30, + 0x50000008 => Type::SPARC_WDISP22, + 0x50000009 => Type::SPARC_HI22, + 0x5000000a => Type::SPARC_22, + 0x5000000b => Type::SPARC_13, + 0x5000000c => Type::SPARC_LO10, + 0x5000000d => Type::SPARC_GOT10, + 0x5000000e => Type::SPARC_GOT13, + 0x5000000f => Type::SPARC_GOT22, + 0x50000010 => Type::SPARC_PC10, + 0x50000011 => Type::SPARC_PC22, + 0x50000012 => Type::SPARC_WPLT30, + 0x50000013 => Type::SPARC_COPY, + 0x50000014 => Type::SPARC_GLOB_DAT, + 0x50000015 => Type::SPARC_JMP_SLOT, + 0x50000016 => Type::SPARC_RELATIVE, + 0x50000017 => Type::SPARC_UA32, + 0x50000018 => Type::SPARC_PLT32, + 0x50000019 => Type::SPARC_HIPLT22, + 0x5000001a => Type::SPARC_LOPLT10, + 0x5000001b => Type::SPARC_PCPLT32, + 0x5000001c => Type::SPARC_PCPLT22, + 0x5000001d => Type::SPARC_PCPLT10, + 0x5000001e => Type::SPARC_10, + 0x5000001f => Type::SPARC_11, + 0x50000020 => Type::SPARC_64, + 0x50000021 => Type::SPARC_OLO10, + 0x50000022 => Type::SPARC_HH22, + 0x50000023 => Type::SPARC_HM10, + 0x50000024 => Type::SPARC_LM22, + 0x50000025 => Type::SPARC_PC_HH22, + 0x50000026 => Type::SPARC_PC_HM10, + 0x50000027 => Type::SPARC_PC_LM22, + 0x50000028 => Type::SPARC_WDISP16, + 0x50000029 => Type::SPARC_WDISP19, + 0x5000002b => Type::SPARC_7, + 0x5000002c => Type::SPARC_5, + 0x5000002d => Type::SPARC_6, + 0x5000002e => Type::SPARC_DISP64, + 0x5000002f => Type::SPARC_PLT64, + 0x50000030 => Type::SPARC_HIX22, + 0x50000031 => Type::SPARC_LOX10, + 0x50000032 => Type::SPARC_H44, + 0x50000033 => Type::SPARC_M44, + 0x50000034 => Type::SPARC_L44, + 0x50000035 => Type::SPARC_REGISTER, + 0x50000036 => Type::SPARC_UA64, + 0x50000037 => Type::SPARC_UA16, + 0x50000038 => Type::SPARC_TLS_GD_HI22, + 0x50000039 => Type::SPARC_TLS_GD_LO10, + 0x5000003a => Type::SPARC_TLS_GD_ADD, + 0x5000003b => Type::SPARC_TLS_GD_CALL, + 0x5000003c => Type::SPARC_TLS_LDM_HI22, + 0x5000003d => Type::SPARC_TLS_LDM_LO10, + 0x5000003e => Type::SPARC_TLS_LDM_ADD, + 0x5000003f => Type::SPARC_TLS_LDM_CALL, + 0x50000040 => Type::SPARC_TLS_LDO_HIX22, + 0x50000041 => Type::SPARC_TLS_LDO_LOX10, + 0x50000042 => Type::SPARC_TLS_LDO_ADD, + 0x50000043 => Type::SPARC_TLS_IE_HI22, + 0x50000044 => Type::SPARC_TLS_IE_LO10, + 0x50000045 => Type::SPARC_TLS_IE_LD, + 0x50000046 => Type::SPARC_TLS_IE_LDX, + 0x50000047 => Type::SPARC_TLS_IE_ADD, + 0x50000048 => Type::SPARC_TLS_LE_HIX22, + 0x50000049 => Type::SPARC_TLS_LE_LOX10, + 0x5000004a => Type::SPARC_TLS_DTPMOD32, + 0x5000004b => Type::SPARC_TLS_DTPMOD64, + 0x5000004c => Type::SPARC_TLS_DTPOFF32, + 0x5000004d => Type::SPARC_TLS_DTPOFF64, + 0x5000004e => Type::SPARC_TLS_TPOFF32, + 0x5000004f => Type::SPARC_TLS_TPOFF64, + 0x50000050 => Type::SPARC_GOTDATA_HIX22, + 0x50000051 => Type::SPARC_GOTDATA_LOX10, + 0x50000052 => Type::SPARC_GOTDATA_OP_HIX22, + 0x50000053 => Type::SPARC_GOTDATA_OP_LOX10, + 0x50000054 => Type::SPARC_GOTDATA_OP, + 0x58000000 => Type::SYSZ_NONE, + 0x58000001 => Type::SYSZ_8, + 0x58000002 => Type::SYSZ_12, + 0x58000003 => Type::SYSZ_16, + 0x58000004 => Type::SYSZ_32, + 0x58000005 => Type::SYSZ_PC32, + 0x58000006 => Type::SYSZ_GOT12, + 0x58000007 => Type::SYSZ_GOT32, + 0x58000008 => Type::SYSZ_PLT32, + 0x58000009 => Type::SYSZ_COPY, + 0x5800000a => Type::SYSZ_GLOB_DAT, + 0x5800000b => Type::SYSZ_JMP_SLOT, + 0x5800000c => Type::SYSZ_RELATIVE, + 0x5800000d => Type::SYSZ_GOTOFF, + 0x5800000e => Type::SYSZ_GOTPC, + 0x5800000f => Type::SYSZ_GOT16, + 0x58000010 => Type::SYSZ_PC16, + 0x58000011 => Type::SYSZ_PC16DBL, + 0x58000012 => Type::SYSZ_PLT16DBL, + 0x58000013 => Type::SYSZ_PC32DBL, + 0x58000014 => Type::SYSZ_PLT32DBL, + 0x58000015 => Type::SYSZ_GOTPCDBL, + 0x58000016 => Type::SYSZ_64, + 0x58000017 => Type::SYSZ_PC64, + 0x58000018 => Type::SYSZ_GOT64, + 0x58000019 => Type::SYSZ_PLT64, + 0x5800001a => Type::SYSZ_GOTENT, + 0x5800001b => Type::SYSZ_GOTOFF16, + 0x5800001c => Type::SYSZ_GOTOFF64, + 0x5800001d => Type::SYSZ_GOTPLT12, + 0x5800001e => Type::SYSZ_GOTPLT16, + 0x5800001f => Type::SYSZ_GOTPLT32, + 0x58000020 => Type::SYSZ_GOTPLT64, + 0x58000021 => Type::SYSZ_GOTPLTENT, + 0x58000022 => Type::SYSZ_PLTOFF16, + 0x58000023 => Type::SYSZ_PLTOFF32, + 0x58000024 => Type::SYSZ_PLTOFF64, + 0x58000025 => Type::SYSZ_TLS_LOAD, + 0x58000026 => Type::SYSZ_TLS_GDCALL, + 0x58000027 => Type::SYSZ_TLS_LDCALL, + 0x58000028 => Type::SYSZ_TLS_GD32, + 0x58000029 => Type::SYSZ_TLS_GD64, + 0x5800002a => Type::SYSZ_TLS_GOTIE12, + 0x5800002b => Type::SYSZ_TLS_GOTIE32, + 0x5800002c => Type::SYSZ_TLS_GOTIE64, + 0x5800002d => Type::SYSZ_TLS_LDM32, + 0x5800002e => Type::SYSZ_TLS_LDM64, + 0x5800002f => Type::SYSZ_TLS_IE32, + 0x58000030 => Type::SYSZ_TLS_IE64, + 0x58000031 => Type::SYSZ_TLS_IEENT, + 0x58000032 => Type::SYSZ_TLS_LE32, + 0x58000033 => Type::SYSZ_TLS_LE64, + 0x58000034 => Type::SYSZ_TLS_LDO32, + 0x58000035 => Type::SYSZ_TLS_LDO64, + 0x58000036 => Type::SYSZ_TLS_DTPMOD, + 0x58000037 => Type::SYSZ_TLS_DTPOFF, + 0x58000038 => Type::SYSZ_TLS_TPOFF, + 0x58000039 => Type::SYSZ_20, + 0x5800003a => Type::SYSZ_GOT20, + 0x5800003b => Type::SYSZ_GOTPLT20, + 0x5800003c => Type::SYSZ_TLS_GOTIE20, + 0x5800003d => Type::SYSZ_IRELATIVE, + 0x5800003e => Type::SYSZ_PC12DBL, + 0x5800003f => Type::SYSZ_PLT12DBL, + 0x58000040 => Type::SYSZ_PC24DBL, + 0x58000041 => Type::SYSZ_PLT24DBL, + 0x60000000 => Type::RISCV_NONE, + 0x60000001 => Type::RISCV_32, + 0x60000002 => Type::RISCV_64, + 0x60000003 => Type::RISCV_RELATIVE, + 0x60000004 => Type::RISCV_COPY, + 0x60000005 => Type::RISCV_JUMP_SLOT, + 0x60000006 => Type::RISCV_TLS_DTPMOD32, + 0x60000007 => Type::RISCV_TLS_DTPMOD64, + 0x60000008 => Type::RISCV_TLS_DTPREL32, + 0x60000009 => Type::RISCV_TLS_DTPREL64, + 0x6000000a => Type::RISCV_TLS_TPREL32, + 0x6000000b => Type::RISCV_TLS_TPREL64, + 0x6000000c => Type::RISCV_TLSDESC, + 0x60000010 => Type::RISCV_BRANCH, + 0x60000011 => Type::RISCV_JAL, + 0x60000012 => Type::RISCV_CALL, + 0x60000013 => Type::RISCV_CALL_PLT, + 0x60000014 => Type::RISCV_GOT_HI20, + 0x60000015 => Type::RISCV_TLS_GOT_HI20, + 0x60000016 => Type::RISCV_TLS_GD_HI20, + 0x60000017 => Type::RISCV_PCREL_HI20, + 0x60000018 => Type::RISCV_PCREL_LO12_I, + 0x60000019 => Type::RISCV_PCREL_LO12_S, + 0x6000001a => Type::RISCV_HI20, + 0x6000001b => Type::RISCV_LO12_I, + 0x6000001c => Type::RISCV_LO12_S, + 0x6000001d => Type::RISCV_TPREL_HI20, + 0x6000001e => Type::RISCV_TPREL_LO12_I, + 0x6000001f => Type::RISCV_TPREL_LO12_S, + 0x60000020 => Type::RISCV_TPREL_ADD, + 0x60000021 => Type::RISCV_ADD8, + 0x60000022 => Type::RISCV_ADD16, + 0x60000023 => Type::RISCV_ADD32, + 0x60000024 => Type::RISCV_ADD64, + 0x60000025 => Type::RISCV_SUB8, + 0x60000026 => Type::RISCV_SUB16, + 0x60000027 => Type::RISCV_SUB32, + 0x60000028 => Type::RISCV_SUB64, + 0x60000029 => Type::RISCV_GOT32_PCREL, + 0x6000002b => Type::RISCV_ALIGN, + 0x6000002c => Type::RISCV_RVC_BRANCH, + 0x6000002d => Type::RISCV_RVC_JUMP, + 0x6000002e => Type::RISCV_RVC_LUI, + 0x60000033 => Type::RISCV_RELAX, + 0x60000034 => Type::RISCV_SUB6, + 0x60000035 => Type::RISCV_SET6, + 0x60000036 => Type::RISCV_SET8, + 0x60000037 => Type::RISCV_SET16, + 0x60000038 => Type::RISCV_SET32, + 0x60000039 => Type::RISCV_32_PCREL, + 0x6000003a => Type::RISCV_IRELATIVE, + 0x6000003b => Type::RISCV_PLT32, + 0x6000003c => Type::RISCV_SET_ULEB128, + 0x6000003d => Type::RISCV_SUB_ULEB128, + 0x6000003e => Type::RISCV_TLSDESC_HI20, + 0x6000003f => Type::RISCV_TLSDESC_LOAD_LO12, + 0x60000040 => Type::RISCV_TLSDESC_ADD_LO12, + 0x60000041 => Type::RISCV_TLSDESC_CALL, + 0x68000000 => Type::BPF_NONE, + 0x68000001 => Type::BPF_64_64, + 0x68000002 => Type::BPF_64_ABS64, + 0x68000003 => Type::BPF_64_ABS32, + 0x68000004 => Type::BPF_64_NODYLD32, + 0x6800000a => Type::BPF_64_32, + 0x70000000 => Type::SH_NONE, + 0x70000001 => Type::SH_DIR32, + 0x70000002 => Type::SH_REL32, + 0x70000003 => Type::SH_DIR8WPN, + 0x70000004 => Type::SH_IND12W, + 0x70000005 => Type::SH_DIR8WPL, + 0x70000006 => Type::SH_DIR8WPZ, + 0x70000007 => Type::SH_DIR8BP, + 0x70000008 => Type::SH_DIR8W, + 0x70000009 => Type::SH_DIR8L, + 0x7000000a => Type::SH_LOOP_START, + 0x7000000b => Type::SH_LOOP_END, + 0x70000016 => Type::SH_GNU_VTINHERIT, + 0x70000017 => Type::SH_GNU_VTENTRY, + 0x70000018 => Type::SH_SWITCH8, + 0x70000019 => Type::SH_SWITCH16, + 0x7000001a => Type::SH_SWITCH32, + 0x7000001b => Type::SH_USES, + 0x7000001c => Type::SH_COUNT, + 0x7000001d => Type::SH_ALIGN, + 0x7000001e => Type::SH_CODE, + 0x7000001f => Type::SH_DATA, + 0x70000020 => Type::SH_LABEL, + 0x70000021 => Type::SH_DIR16, + 0x70000022 => Type::SH_DIR8, + 0x70000023 => Type::SH_DIR8UL, + 0x70000024 => Type::SH_DIR8UW, + 0x70000025 => Type::SH_DIR8U, + 0x70000026 => Type::SH_DIR8SW, + 0x70000027 => Type::SH_DIR8S, + 0x70000028 => Type::SH_DIR4UL, + 0x70000029 => Type::SH_DIR4UW, + 0x7000002a => Type::SH_DIR4U, + 0x7000002b => Type::SH_PSHA, + 0x7000002c => Type::SH_PSHL, + 0x7000002d => Type::SH_DIR5U, + 0x7000002e => Type::SH_DIR6U, + 0x7000002f => Type::SH_DIR6S, + 0x70000030 => Type::SH_DIR10S, + 0x70000031 => Type::SH_DIR10SW, + 0x70000032 => Type::SH_DIR10SL, + 0x70000033 => Type::SH_DIR10SQ, + 0x70000035 => Type::SH_DIR16S, + 0x70000090 => Type::SH_TLS_GD_32, + 0x70000091 => Type::SH_TLS_LD_32, + 0x70000092 => Type::SH_TLS_LDO_32, + 0x70000093 => Type::SH_TLS_IE_32, + 0x70000094 => Type::SH_TLS_LE_32, + 0x70000095 => Type::SH_TLS_DTPMOD32, + 0x70000096 => Type::SH_TLS_DTPOFF32, + 0x70000097 => Type::SH_TLS_TPOFF32, + 0x700000a0 => Type::SH_GOT32, + 0x700000a1 => Type::SH_PLT32, + 0x700000a2 => Type::SH_COPY, + 0x700000a3 => Type::SH_GLOB_DAT, + 0x700000a4 => Type::SH_JMP_SLOT, + 0x700000a5 => Type::SH_RELATIVE, + 0x700000a6 => Type::SH_GOTOFF, + 0x700000a7 => Type::SH_GOTPC, + 0x700000a8 => Type::SH_GOTPLT32, + 0x700000a9 => Type::SH_GOT_LOW16, + 0x700000aa => Type::SH_GOT_MEDLOW16, + 0x700000ab => Type::SH_GOT_MEDHI16, + 0x700000ac => Type::SH_GOT_HI16, + 0x700000ad => Type::SH_GOTPLT_LOW16, + 0x700000ae => Type::SH_GOTPLT_MEDLOW16, + 0x700000af => Type::SH_GOTPLT_MEDHI16, + 0x700000b0 => Type::SH_GOTPLT_HI16, + 0x700000b1 => Type::SH_PLT_LOW16, + 0x700000b2 => Type::SH_PLT_MEDLOW16, + 0x700000b3 => Type::SH_PLT_MEDHI16, + 0x700000b4 => Type::SH_PLT_HI16, + 0x700000b5 => Type::SH_GOTOFF_LOW16, + 0x700000b6 => Type::SH_GOTOFF_MEDLOW16, + 0x700000b7 => Type::SH_GOTOFF_MEDHI16, + 0x700000b8 => Type::SH_GOTOFF_HI16, + 0x700000b9 => Type::SH_GOTPC_LOW16, + 0x700000ba => Type::SH_GOTPC_MEDLOW16, + 0x700000bb => Type::SH_GOTPC_MEDHI16, + 0x700000bc => Type::SH_GOTPC_HI16, + 0x700000bd => Type::SH_GOT10BY4, + 0x700000be => Type::SH_GOTPLT10BY4, + 0x700000bf => Type::SH_GOT10BY8, + 0x700000c0 => Type::SH_GOTPLT10BY8, + 0x700000c1 => Type::SH_COPY64, + 0x700000c2 => Type::SH_GLOB_DAT64, + 0x700000c3 => Type::SH_JMP_SLOT64, + 0x700000c4 => Type::SH_RELATIVE64, + 0x700000c9 => Type::SH_GOT20, + 0x700000ca => Type::SH_GOTOFF20, + 0x700000cb => Type::SH_GOTFUNCDESC, + 0x700000cc => Type::SH_GOTFUNCDESC20, + 0x700000cd => Type::SH_GOTOFFFUNCDESC, + 0x700000ce => Type::SH_GOTOFFFUNCDESC20, + 0x700000cf => Type::SH_FUNCDESC, + 0x700000d0 => Type::SH_FUNCDESC_VALUE, + 0x700000f2 => Type::SH_SHMEDIA_CODE, + 0x700000f3 => Type::SH_PT_16, + 0x700000f4 => Type::SH_IMMS16, + 0x700000f5 => Type::SH_IMMU16, + 0x700000f6 => Type::SH_IMM_LOW16, + 0x700000f7 => Type::SH_IMM_LOW16_PCREL, + 0x700000f8 => Type::SH_IMM_MEDLOW16, + 0x700000f9 => Type::SH_IMM_MEDLOW16_PCREL, + 0x700000fa => Type::SH_IMM_MEDHI16, + 0x700000fb => Type::SH_IMM_MEDHI16_PCREL, + 0x700000fc => Type::SH_IMM_HI16, + 0x700000fd => Type::SH_IMM_HI16_PCREL, + 0x700000fe => Type::SH_64, + 0x700000ff => Type::SH_64_PCREL, + _ => Type::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Type) -> u32 { + match value { + Type::X86_64_NONE => 0x08000000, + Type::X86_64_64 => 0x08000001, + Type::X86_64_PC32 => 0x08000002, + Type::X86_64_GOT32 => 0x08000003, + Type::X86_64_PLT32 => 0x08000004, + Type::X86_64_COPY => 0x08000005, + Type::X86_64_GLOB_DAT => 0x08000006, + Type::X86_64_JUMP_SLOT => 0x08000007, + Type::X86_64_RELATIVE => 0x08000008, + Type::X86_64_GOTPCREL => 0x08000009, + Type::X86_64_32 => 0x0800000a, + Type::X86_64_32S => 0x0800000b, + Type::X86_64_16 => 0x0800000c, + Type::X86_64_PC16 => 0x0800000d, + Type::X86_64_8 => 0x0800000e, + Type::X86_64_PC8 => 0x0800000f, + Type::X86_64_DTPMOD64 => 0x08000010, + Type::X86_64_DTPOFF64 => 0x08000011, + Type::X86_64_TPOFF64 => 0x08000012, + Type::X86_64_TLSGD => 0x08000013, + Type::X86_64_TLSLD => 0x08000014, + Type::X86_64_DTPOFF32 => 0x08000015, + Type::X86_64_GOTTPOFF => 0x08000016, + Type::X86_64_TPOFF32 => 0x08000017, + Type::X86_64_PC64 => 0x08000018, + Type::X86_64_GOTOFF64 => 0x08000019, + Type::X86_64_GOTPC32 => 0x0800001a, + Type::X86_64_GOT64 => 0x0800001b, + Type::X86_64_GOTPCREL64 => 0x0800001c, + Type::X86_64_GOTPC64 => 0x0800001d, + Type::X86_64_GOTPLT64 => 0x0800001e, + Type::X86_64_PLTOFF64 => 0x0800001f, + Type::X86_64_SIZE32 => 0x08000020, + Type::X86_64_SIZE64 => 0x08000021, + Type::X86_64_GOTPC32_TLSDESC => 0x08000022, + Type::X86_64_TLSDESC_CALL => 0x08000023, + Type::X86_64_TLSDESC => 0x08000024, + Type::X86_64_IRELATIVE => 0x08000025, + Type::X86_64_RELATIVE64 => 0x08000026, + Type::X86_64_PC32_BND => 0x08000027, + Type::X86_64_PLT32_BND => 0x08000028, + Type::X86_64_GOTPCRELX => 0x08000029, + Type::X86_64_REX_GOTPCRELX => 0x0800002a, + Type::AARCH64_NONE => 0x10000000, + Type::AARCH64_ABS64 => 0x10000101, + Type::AARCH64_ABS32 => 0x10000102, + Type::AARCH64_ABS16 => 0x10000103, + Type::AARCH64_PREL64 => 0x10000104, + Type::AARCH64_PREL32 => 0x10000105, + Type::AARCH64_PREL16 => 0x10000106, + Type::AARCH64_MOVW_UABS_G0 => 0x10000107, + Type::AARCH64_MOVW_UABS_G0_NC => 0x10000108, + Type::AARCH64_MOVW_UABS_G1 => 0x10000109, + Type::AARCH64_MOVW_UABS_G1_NC => 0x1000010a, + Type::AARCH64_MOVW_UABS_G2 => 0x1000010b, + Type::AARCH64_MOVW_UABS_G2_NC => 0x1000010c, + Type::AARCH64_MOVW_UABS_G3 => 0x1000010d, + Type::AARCH64_MOVW_SABS_G0 => 0x1000010e, + Type::AARCH64_MOVW_SABS_G1 => 0x1000010f, + Type::AARCH64_MOVW_SABS_G2 => 0x10000110, + Type::AARCH64_LD_PREL_LO19 => 0x10000111, + Type::AARCH64_ADR_PREL_LO21 => 0x10000112, + Type::AARCH64_ADR_PREL_PG_HI21 => 0x10000113, + Type::AARCH64_ADR_PREL_PG_HI21_NC => 0x10000114, + Type::AARCH64_ADD_ABS_LO12_NC => 0x10000115, + Type::AARCH64_LDST8_ABS_LO12_NC => 0x10000116, + Type::AARCH64_TSTBR14 => 0x10000117, + Type::AARCH64_CONDBR19 => 0x10000118, + Type::AARCH64_JUMP26 => 0x1000011a, + Type::AARCH64_CALL26 => 0x1000011b, + Type::AARCH64_LDST16_ABS_LO12_NC => 0x1000011c, + Type::AARCH64_LDST32_ABS_LO12_NC => 0x1000011d, + Type::AARCH64_LDST64_ABS_LO12_NC => 0x1000011e, + Type::AARCH64_MOVW_PREL_G0 => 0x1000011f, + Type::AARCH64_MOVW_PREL_G0_NC => 0x10000120, + Type::AARCH64_MOVW_PREL_G1 => 0x10000121, + Type::AARCH64_MOVW_PREL_G1_NC => 0x10000122, + Type::AARCH64_MOVW_PREL_G2 => 0x10000123, + Type::AARCH64_MOVW_PREL_G2_NC => 0x10000124, + Type::AARCH64_MOVW_PREL_G3 => 0x10000125, + Type::AARCH64_LDST128_ABS_LO12_NC => 0x1000012b, + Type::AARCH64_MOVW_GOTOFF_G0 => 0x1000012c, + Type::AARCH64_MOVW_GOTOFF_G0_NC => 0x1000012d, + Type::AARCH64_MOVW_GOTOFF_G1 => 0x1000012e, + Type::AARCH64_MOVW_GOTOFF_G1_NC => 0x1000012f, + Type::AARCH64_MOVW_GOTOFF_G2 => 0x10000130, + Type::AARCH64_MOVW_GOTOFF_G2_NC => 0x10000131, + Type::AARCH64_MOVW_GOTOFF_G3 => 0x10000132, + Type::AARCH64_GOTREL64 => 0x10000133, + Type::AARCH64_GOTREL32 => 0x10000134, + Type::AARCH64_GOT_LD_PREL19 => 0x10000135, + Type::AARCH64_LD64_GOTOFF_LO15 => 0x10000136, + Type::AARCH64_ADR_GOT_PAGE => 0x10000137, + Type::AARCH64_LD64_GOT_LO12_NC => 0x10000138, + Type::AARCH64_LD64_GOTPAGE_LO15 => 0x10000139, + Type::AARCH64_TLSGD_ADR_PREL21 => 0x10000200, + Type::AARCH64_TLSGD_ADR_PAGE21 => 0x10000201, + Type::AARCH64_TLSGD_ADD_LO12_NC => 0x10000202, + Type::AARCH64_TLSGD_MOVW_G1 => 0x10000203, + Type::AARCH64_TLSGD_MOVW_G0_NC => 0x10000204, + Type::AARCH64_TLSLD_ADR_PREL21 => 0x10000205, + Type::AARCH64_TLSLD_ADR_PAGE21 => 0x10000206, + Type::AARCH64_TLSLD_ADD_LO12_NC => 0x10000207, + Type::AARCH64_TLSLD_MOVW_G1 => 0x10000208, + Type::AARCH64_TLSLD_MOVW_G0_NC => 0x10000209, + Type::AARCH64_TLSLD_LD_PREL19 => 0x1000020a, + Type::AARCH64_TLSLD_MOVW_DTPREL_G2 => 0x1000020b, + Type::AARCH64_TLSLD_MOVW_DTPREL_G1 => 0x1000020c, + Type::AARCH64_TLSLD_MOVW_DTPREL_G1_NC => 0x1000020d, + Type::AARCH64_TLSLD_MOVW_DTPREL_G0 => 0x1000020e, + Type::AARCH64_TLSLD_MOVW_DTPREL_G0_NC => 0x1000020f, + Type::AARCH64_TLSLD_ADD_DTPREL_HI12 => 0x10000210, + Type::AARCH64_TLSLD_ADD_DTPREL_LO12 => 0x10000211, + Type::AARCH64_TLSLD_ADD_DTPREL_LO12_NC => 0x10000212, + Type::AARCH64_TLSLD_LDST8_DTPREL_LO12 => 0x10000213, + Type::AARCH64_TLSLD_LDST8_DTPREL_LO12_NC => 0x10000214, + Type::AARCH64_TLSLD_LDST16_DTPREL_LO12 => 0x10000215, + Type::AARCH64_TLSLD_LDST16_DTPREL_LO12_NC => 0x10000216, + Type::AARCH64_TLSLD_LDST32_DTPREL_LO12 => 0x10000217, + Type::AARCH64_TLSLD_LDST32_DTPREL_LO12_NC => 0x10000218, + Type::AARCH64_TLSLD_LDST64_DTPREL_LO12 => 0x10000219, + Type::AARCH64_TLSLD_LDST64_DTPREL_LO12_NC => 0x1000021a, + Type::AARCH64_TLSIE_MOVW_GOTTPREL_G1 => 0x1000021b, + Type::AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC => 0x1000021c, + Type::AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 => 0x1000021d, + Type::AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC => 0x1000021e, + Type::AARCH64_TLSIE_LD_GOTTPREL_PREL19 => 0x1000021f, + Type::AARCH64_TLSLE_MOVW_TPREL_G2 => 0x10000220, + Type::AARCH64_TLSLE_MOVW_TPREL_G1 => 0x10000221, + Type::AARCH64_TLSLE_MOVW_TPREL_G1_NC => 0x10000222, + Type::AARCH64_TLSLE_MOVW_TPREL_G0 => 0x10000223, + Type::AARCH64_TLSLE_MOVW_TPREL_G0_NC => 0x10000224, + Type::AARCH64_TLSLE_ADD_TPREL_HI12 => 0x10000225, + Type::AARCH64_TLSLE_ADD_TPREL_LO12 => 0x10000226, + Type::AARCH64_TLSLE_ADD_TPREL_LO12_NC => 0x10000227, + Type::AARCH64_TLSLE_LDST8_TPREL_LO12 => 0x10000228, + Type::AARCH64_TLSLE_LDST8_TPREL_LO12_NC => 0x10000229, + Type::AARCH64_TLSLE_LDST16_TPREL_LO12 => 0x1000022a, + Type::AARCH64_TLSLE_LDST16_TPREL_LO12_NC => 0x1000022b, + Type::AARCH64_TLSLE_LDST32_TPREL_LO12 => 0x1000022c, + Type::AARCH64_TLSLE_LDST32_TPREL_LO12_NC => 0x1000022d, + Type::AARCH64_TLSLE_LDST64_TPREL_LO12 => 0x1000022e, + Type::AARCH64_TLSLE_LDST64_TPREL_LO12_NC => 0x1000022f, + Type::AARCH64_TLSDESC_LD_PREL19 => 0x10000230, + Type::AARCH64_TLSDESC_ADR_PREL21 => 0x10000231, + Type::AARCH64_TLSDESC_ADR_PAGE21 => 0x10000232, + Type::AARCH64_TLSDESC_LD64_LO12_NC => 0x10000233, + Type::AARCH64_TLSDESC_ADD_LO12_NC => 0x10000234, + Type::AARCH64_TLSDESC_OFF_G1 => 0x10000235, + Type::AARCH64_TLSDESC_OFF_G0_NC => 0x10000236, + Type::AARCH64_TLSDESC_LDR => 0x10000237, + Type::AARCH64_TLSDESC_ADD => 0x10000238, + Type::AARCH64_TLSDESC_CALL => 0x10000239, + Type::AARCH64_TLSLE_LDST128_TPREL_LO12 => 0x1000023a, + Type::AARCH64_TLSLE_LDST128_TPREL_LO12_NC => 0x1000023b, + Type::AARCH64_TLSLD_LDST128_DTPREL_LO12 => 0x1000023c, + Type::AARCH64_TLSLD_LDST128_DTPREL_LO12_NC => 0x1000023d, + Type::AARCH64_COPY => 0x10000400, + Type::AARCH64_GLOB_DAT => 0x10000401, + Type::AARCH64_JUMP_SLOT => 0x10000402, + Type::AARCH64_RELATIVE => 0x10000403, + Type::AARCH64_TLS_DTPREL64 => 0x10000404, + Type::AARCH64_TLS_DTPMOD64 => 0x10000405, + Type::AARCH64_TLS_TPREL64 => 0x10000406, + Type::AARCH64_TLSDESC => 0x10000407, + Type::AARCH64_IRELATIVE => 0x10000408, + Type::ARM_NONE => 0x18000000, + Type::ARM_PC24 => 0x18000001, + Type::ARM_ABS32 => 0x18000002, + Type::ARM_REL32 => 0x18000003, + Type::ARM_LDR_PC_G0 => 0x18000004, + Type::ARM_ABS16 => 0x18000005, + Type::ARM_ABS12 => 0x18000006, + Type::ARM_THM_ABS5 => 0x18000007, + Type::ARM_ABS8 => 0x18000008, + Type::ARM_SBREL32 => 0x18000009, + Type::ARM_THM_CALL => 0x1800000a, + Type::ARM_THM_PC8 => 0x1800000b, + Type::ARM_BREL_ADJ => 0x1800000c, + Type::ARM_TLS_DESC => 0x1800000d, + Type::ARM_THM_SWI8 => 0x1800000e, + Type::ARM_XPC25 => 0x1800000f, + Type::ARM_THM_XPC22 => 0x18000010, + Type::ARM_TLS_DTPMOD32 => 0x18000011, + Type::ARM_TLS_DTPOFF32 => 0x18000012, + Type::ARM_TLS_TPOFF32 => 0x18000013, + Type::ARM_COPY => 0x18000014, + Type::ARM_GLOB_DAT => 0x18000015, + Type::ARM_JUMP_SLOT => 0x18000016, + Type::ARM_RELATIVE => 0x18000017, + Type::ARM_GOTOFF32 => 0x18000018, + Type::ARM_BASE_PREL => 0x18000019, + Type::ARM_GOT_BREL => 0x1800001a, + Type::ARM_PLT32 => 0x1800001b, + Type::ARM_CALL => 0x1800001c, + Type::ARM_JUMP24 => 0x1800001d, + Type::ARM_THM_JUMP24 => 0x1800001e, + Type::ARM_BASE_ABS => 0x1800001f, + Type::ARM_ALU_PCREL_7_0 => 0x18000020, + Type::ARM_ALU_PCREL_15_8 => 0x18000021, + Type::ARM_ALU_PCREL_23_15 => 0x18000022, + Type::ARM_LDR_SBREL_11_0_NC => 0x18000023, + Type::ARM_ALU_SBREL_19_12_NC => 0x18000024, + Type::ARM_ALU_SBREL_27_20_CK => 0x18000025, + Type::ARM_TARGET1 => 0x18000026, + Type::ARM_SBREL31 => 0x18000027, + Type::ARM_V4BX => 0x18000028, + Type::ARM_TARGET2 => 0x18000029, + Type::ARM_PREL31 => 0x1800002a, + Type::ARM_MOVW_ABS_NC => 0x1800002b, + Type::ARM_MOVT_ABS => 0x1800002c, + Type::ARM_MOVW_PREL_NC => 0x1800002d, + Type::ARM_MOVT_PREL => 0x1800002e, + Type::ARM_THM_MOVW_ABS_NC => 0x1800002f, + Type::ARM_THM_MOVT_ABS => 0x18000030, + Type::ARM_THM_MOVW_PREL_NC => 0x18000031, + Type::ARM_THM_MOVT_PREL => 0x18000032, + Type::ARM_THM_JUMP19 => 0x18000033, + Type::ARM_THM_JUMP6 => 0x18000034, + Type::ARM_THM_ALU_PREL_11_0 => 0x18000035, + Type::ARM_THM_PC12 => 0x18000036, + Type::ARM_ABS32_NOI => 0x18000037, + Type::ARM_REL32_NOI => 0x18000038, + Type::ARM_ALU_PC_G0_NC => 0x18000039, + Type::ARM_ALU_PC_G0 => 0x1800003a, + Type::ARM_ALU_PC_G1_NC => 0x1800003b, + Type::ARM_ALU_PC_G1 => 0x1800003c, + Type::ARM_ALU_PC_G2 => 0x1800003d, + Type::ARM_LDR_PC_G1 => 0x1800003e, + Type::ARM_LDR_PC_G2 => 0x1800003f, + Type::ARM_LDRS_PC_G0 => 0x18000040, + Type::ARM_LDRS_PC_G1 => 0x18000041, + Type::ARM_LDRS_PC_G2 => 0x18000042, + Type::ARM_LDC_PC_G0 => 0x18000043, + Type::ARM_LDC_PC_G1 => 0x18000044, + Type::ARM_LDC_PC_G2 => 0x18000045, + Type::ARM_ALU_SB_G0_NC => 0x18000046, + Type::ARM_ALU_SB_G0 => 0x18000047, + Type::ARM_ALU_SB_G1_NC => 0x18000048, + Type::ARM_ALU_SB_G1 => 0x18000049, + Type::ARM_ALU_SB_G2 => 0x1800004a, + Type::ARM_LDR_SB_G0 => 0x1800004b, + Type::ARM_LDR_SB_G1 => 0x1800004c, + Type::ARM_LDR_SB_G2 => 0x1800004d, + Type::ARM_LDRS_SB_G0 => 0x1800004e, + Type::ARM_LDRS_SB_G1 => 0x1800004f, + Type::ARM_LDRS_SB_G2 => 0x18000050, + Type::ARM_LDC_SB_G0 => 0x18000051, + Type::ARM_LDC_SB_G1 => 0x18000052, + Type::ARM_LDC_SB_G2 => 0x18000053, + Type::ARM_MOVW_BREL_NC => 0x18000054, + Type::ARM_MOVT_BREL => 0x18000055, + Type::ARM_MOVW_BREL => 0x18000056, + Type::ARM_THM_MOVW_BREL_NC => 0x18000057, + Type::ARM_THM_MOVT_BREL => 0x18000058, + Type::ARM_THM_MOVW_BREL => 0x18000059, + Type::ARM_TLS_GOTDESC => 0x1800005a, + Type::ARM_TLS_CALL => 0x1800005b, + Type::ARM_TLS_DESCSEQ => 0x1800005c, + Type::ARM_THM_TLS_CALL => 0x1800005d, + Type::ARM_PLT32_ABS => 0x1800005e, + Type::ARM_GOT_ABS => 0x1800005f, + Type::ARM_GOT_PREL => 0x18000060, + Type::ARM_GOT_BREL12 => 0x18000061, + Type::ARM_GOTOFF12 => 0x18000062, + Type::ARM_GOTRELAX => 0x18000063, + Type::ARM_GNU_VTENTRY => 0x18000064, + Type::ARM_GNU_VTINHERIT => 0x18000065, + Type::ARM_THM_JUMP11 => 0x18000066, + Type::ARM_THM_JUMP8 => 0x18000067, + Type::ARM_TLS_GD32 => 0x18000068, + Type::ARM_TLS_LDM32 => 0x18000069, + Type::ARM_TLS_LDO32 => 0x1800006a, + Type::ARM_TLS_IE32 => 0x1800006b, + Type::ARM_TLS_LE32 => 0x1800006c, + Type::ARM_TLS_LDO12 => 0x1800006d, + Type::ARM_TLS_LE12 => 0x1800006e, + Type::ARM_TLS_IE12GP => 0x1800006f, + Type::ARM_PRIVATE_0 => 0x18000070, + Type::ARM_PRIVATE_1 => 0x18000071, + Type::ARM_PRIVATE_2 => 0x18000072, + Type::ARM_PRIVATE_3 => 0x18000073, + Type::ARM_PRIVATE_4 => 0x18000074, + Type::ARM_PRIVATE_5 => 0x18000075, + Type::ARM_PRIVATE_6 => 0x18000076, + Type::ARM_PRIVATE_7 => 0x18000077, + Type::ARM_PRIVATE_8 => 0x18000078, + Type::ARM_PRIVATE_9 => 0x18000079, + Type::ARM_PRIVATE_10 => 0x1800007a, + Type::ARM_PRIVATE_11 => 0x1800007b, + Type::ARM_PRIVATE_12 => 0x1800007c, + Type::ARM_PRIVATE_13 => 0x1800007d, + Type::ARM_PRIVATE_14 => 0x1800007e, + Type::ARM_PRIVATE_15 => 0x1800007f, + Type::ARM_ME_TOO => 0x18000080, + Type::ARM_THM_TLS_DESCSEQ16 => 0x18000081, + Type::ARM_THM_TLS_DESCSEQ32 => 0x18000082, + Type::ARM_IRELATIVE => 0x180000a0, + Type::ARM_RXPC25 => 0x180000f9, + Type::ARM_RSBREL32 => 0x180000fa, + Type::ARM_THM_RPC22 => 0x180000fb, + Type::ARM_RREL32 => 0x180000fc, + Type::ARM_RPC24 => 0x180000fd, + Type::ARM_RBASE => 0x180000fe, + Type::HEX_NONE => 0x20000000, + Type::HEX_B22_PCREL => 0x20000001, + Type::HEX_B15_PCREL => 0x20000002, + Type::HEX_B7_PCREL => 0x20000003, + Type::HEX_LO16 => 0x20000004, + Type::HEX_HI16 => 0x20000005, + Type::HEX_32 => 0x20000006, + Type::HEX_16 => 0x20000007, + Type::HEX_8 => 0x20000008, + Type::HEX_GPREL16_0 => 0x20000009, + Type::HEX_GPREL16_1 => 0x2000000a, + Type::HEX_GPREL16_2 => 0x2000000b, + Type::HEX_GPREL16_3 => 0x2000000c, + Type::HEX_HL16 => 0x2000000d, + Type::HEX_B13_PCREL => 0x2000000e, + Type::HEX_B9_PCREL => 0x2000000f, + Type::HEX_B32_PCREL_X => 0x20000010, + Type::HEX_32_6_X => 0x20000011, + Type::HEX_B22_PCREL_X => 0x20000012, + Type::HEX_B15_PCREL_X => 0x20000013, + Type::HEX_B13_PCREL_X => 0x20000014, + Type::HEX_B9_PCREL_X => 0x20000015, + Type::HEX_B7_PCREL_X => 0x20000016, + Type::HEX_16_X => 0x20000017, + Type::HEX_12_X => 0x20000018, + Type::HEX_11_X => 0x20000019, + Type::HEX_10_X => 0x2000001a, + Type::HEX_9_X => 0x2000001b, + Type::HEX_8_X => 0x2000001c, + Type::HEX_7_X => 0x2000001d, + Type::HEX_6_X => 0x2000001e, + Type::HEX_32_PCREL => 0x2000001f, + Type::HEX_COPY => 0x20000020, + Type::HEX_GLOB_DAT => 0x20000021, + Type::HEX_JMP_SLOT => 0x20000022, + Type::HEX_RELATIVE => 0x20000023, + Type::HEX_PLT_B22_PCREL => 0x20000024, + Type::HEX_GOTREL_LO16 => 0x20000025, + Type::HEX_GOTREL_HI16 => 0x20000026, + Type::HEX_GOTREL_32 => 0x20000027, + Type::HEX_GOT_LO16 => 0x20000028, + Type::HEX_GOT_HI16 => 0x20000029, + Type::HEX_GOT_32 => 0x2000002a, + Type::HEX_GOT_16 => 0x2000002b, + Type::HEX_DTPMOD_32 => 0x2000002c, + Type::HEX_DTPREL_LO16 => 0x2000002d, + Type::HEX_DTPREL_HI16 => 0x2000002e, + Type::HEX_DTPREL_32 => 0x2000002f, + Type::HEX_DTPREL_16 => 0x20000030, + Type::HEX_GD_PLT_B22_PCREL => 0x20000031, + Type::HEX_GD_GOT_LO16 => 0x20000032, + Type::HEX_GD_GOT_HI16 => 0x20000033, + Type::HEX_GD_GOT_32 => 0x20000034, + Type::HEX_GD_GOT_16 => 0x20000035, + Type::HEX_IE_LO16 => 0x20000036, + Type::HEX_IE_HI16 => 0x20000037, + Type::HEX_IE_32 => 0x20000038, + Type::HEX_IE_GOT_LO16 => 0x20000039, + Type::HEX_IE_GOT_HI16 => 0x2000003a, + Type::HEX_IE_GOT_32 => 0x2000003b, + Type::HEX_IE_GOT_16 => 0x2000003c, + Type::HEX_TPREL_LO16 => 0x2000003d, + Type::HEX_TPREL_HI16 => 0x2000003e, + Type::HEX_TPREL_32 => 0x2000003f, + Type::HEX_TPREL_16 => 0x20000040, + Type::HEX_6_PCREL_X => 0x20000041, + Type::HEX_GOTREL_32_6_X => 0x20000042, + Type::HEX_GOTREL_16_X => 0x20000043, + Type::HEX_GOTREL_11_X => 0x20000044, + Type::HEX_GOT_32_6_X => 0x20000045, + Type::HEX_GOT_16_X => 0x20000046, + Type::HEX_GOT_11_X => 0x20000047, + Type::HEX_DTPREL_32_6_X => 0x20000048, + Type::HEX_DTPREL_16_X => 0x20000049, + Type::HEX_DTPREL_11_X => 0x2000004a, + Type::HEX_GD_GOT_32_6_X => 0x2000004b, + Type::HEX_GD_GOT_16_X => 0x2000004c, + Type::HEX_GD_GOT_11_X => 0x2000004d, + Type::HEX_IE_32_6_X => 0x2000004e, + Type::HEX_IE_16_X => 0x2000004f, + Type::HEX_IE_GOT_32_6_X => 0x20000050, + Type::HEX_IE_GOT_16_X => 0x20000051, + Type::HEX_IE_GOT_11_X => 0x20000052, + Type::HEX_TPREL_32_6_X => 0x20000053, + Type::HEX_TPREL_16_X => 0x20000054, + Type::HEX_TPREL_11_X => 0x20000055, + Type::HEX_LD_PLT_B22_PCREL => 0x20000056, + Type::HEX_LD_GOT_LO16 => 0x20000057, + Type::HEX_LD_GOT_HI16 => 0x20000058, + Type::HEX_LD_GOT_32 => 0x20000059, + Type::HEX_LD_GOT_16 => 0x2000005a, + Type::HEX_LD_GOT_32_6_X => 0x2000005b, + Type::HEX_LD_GOT_16_X => 0x2000005c, + Type::HEX_LD_GOT_11_X => 0x2000005d, + Type::X86_NONE => 0x28000000, + Type::X86_32 => 0x28000001, + Type::X86_PC32 => 0x28000002, + Type::X86_GOT32 => 0x28000003, + Type::X86_PLT32 => 0x28000004, + Type::X86_COPY => 0x28000005, + Type::X86_GLOB_DAT => 0x28000006, + Type::X86_JUMP_SLOT => 0x28000007, + Type::X86_RELATIVE => 0x28000008, + Type::X86_GOTOFF => 0x28000009, + Type::X86_GOTPC => 0x2800000a, + Type::X86_32PLT => 0x2800000b, + Type::X86_TLS_TPOFF => 0x2800000e, + Type::X86_TLS_IE => 0x2800000f, + Type::X86_TLS_GOTIE => 0x28000010, + Type::X86_TLS_LE => 0x28000011, + Type::X86_TLS_GD => 0x28000012, + Type::X86_TLS_LDM => 0x28000013, + Type::X86_16 => 0x28000014, + Type::X86_PC16 => 0x28000015, + Type::X86_8 => 0x28000016, + Type::X86_PC8 => 0x28000017, + Type::X86_TLS_GD_32 => 0x28000018, + Type::X86_TLS_GD_PUSH => 0x28000019, + Type::X86_TLS_GD_CALL => 0x2800001a, + Type::X86_TLS_GD_POP => 0x2800001b, + Type::X86_TLS_LDM_32 => 0x2800001c, + Type::X86_TLS_LDM_PUSH => 0x2800001d, + Type::X86_TLS_LDM_CALL => 0x2800001e, + Type::X86_TLS_LDM_POP => 0x2800001f, + Type::X86_TLS_LDO_32 => 0x28000020, + Type::X86_TLS_IE_32 => 0x28000021, + Type::X86_TLS_LE_32 => 0x28000022, + Type::X86_TLS_DTPMOD32 => 0x28000023, + Type::X86_TLS_DTPOFF32 => 0x28000024, + Type::X86_TLS_TPOFF32 => 0x28000025, + Type::X86_TLS_GOTDESC => 0x28000027, + Type::X86_TLS_DESC_CALL => 0x28000028, + Type::X86_TLS_DESC => 0x28000029, + Type::X86_IRELATIVE => 0x2800002a, + Type::LARCH_NONE => 0x30000000, + Type::LARCH_32 => 0x30000001, + Type::LARCH_64 => 0x30000002, + Type::LARCH_RELATIVE => 0x30000003, + Type::LARCH_COPY => 0x30000004, + Type::LARCH_JUMP_SLOT => 0x30000005, + Type::LARCH_TLS_DTPMOD32 => 0x30000006, + Type::LARCH_TLS_DTPMOD64 => 0x30000007, + Type::LARCH_TLS_DTPREL32 => 0x30000008, + Type::LARCH_TLS_DTPREL64 => 0x30000009, + Type::LARCH_TLS_TPREL32 => 0x3000000a, + Type::LARCH_TLS_TPREL64 => 0x3000000b, + Type::LARCH_IRELATIVE => 0x3000000c, + Type::LARCH_MARK_LA => 0x30000014, + Type::LARCH_MARK_PCREL => 0x30000015, + Type::LARCH_SOP_PUSH_PCREL => 0x30000016, + Type::LARCH_SOP_PUSH_ABSOLUTE => 0x30000017, + Type::LARCH_SOP_PUSH_DUP => 0x30000018, + Type::LARCH_SOP_PUSH_GPREL => 0x30000019, + Type::LARCH_SOP_PUSH_TLS_TPREL => 0x3000001a, + Type::LARCH_SOP_PUSH_TLS_GOT => 0x3000001b, + Type::LARCH_SOP_PUSH_TLS_GD => 0x3000001c, + Type::LARCH_SOP_PUSH_PLT_PCREL => 0x3000001d, + Type::LARCH_SOP_ASSERT => 0x3000001e, + Type::LARCH_SOP_NOT => 0x3000001f, + Type::LARCH_SOP_SUB => 0x30000020, + Type::LARCH_SOP_SL => 0x30000021, + Type::LARCH_SOP_SR => 0x30000022, + Type::LARCH_SOP_ADD => 0x30000023, + Type::LARCH_SOP_AND => 0x30000024, + Type::LARCH_SOP_IF_ELSE => 0x30000025, + Type::LARCH_SOP_POP_32_S_10_5 => 0x30000026, + Type::LARCH_SOP_POP_32_U_10_12 => 0x30000027, + Type::LARCH_SOP_POP_32_S_10_12 => 0x30000028, + Type::LARCH_SOP_POP_32_S_10_16 => 0x30000029, + Type::LARCH_SOP_POP_32_S_10_16_S2 => 0x3000002a, + Type::LARCH_SOP_POP_32_S_5_20 => 0x3000002b, + Type::LARCH_SOP_POP_32_S_0_5_10_16_S2 => 0x3000002c, + Type::LARCH_SOP_POP_32_S_0_10_10_16_S2 => 0x3000002d, + Type::LARCH_SOP_POP_32_U => 0x3000002e, + Type::LARCH_ADD8 => 0x3000002f, + Type::LARCH_ADD16 => 0x30000030, + Type::LARCH_ADD24 => 0x30000031, + Type::LARCH_ADD32 => 0x30000032, + Type::LARCH_ADD64 => 0x30000033, + Type::LARCH_SUB8 => 0x30000034, + Type::LARCH_SUB16 => 0x30000035, + Type::LARCH_SUB24 => 0x30000036, + Type::LARCH_SUB32 => 0x30000037, + Type::LARCH_SUB64 => 0x30000038, + Type::LARCH_GNU_VTINHERIT => 0x30000039, + Type::LARCH_GNU_VTENTRY => 0x3000003a, + Type::LARCH_B16 => 0x30000040, + Type::LARCH_B21 => 0x30000041, + Type::LARCH_B26 => 0x30000042, + Type::LARCH_ABS_HI20 => 0x30000043, + Type::LARCH_ABS_LO12 => 0x30000044, + Type::LARCH_ABS64_LO20 => 0x30000045, + Type::LARCH_ABS64_HI12 => 0x30000046, + Type::LARCH_PCALA_HI20 => 0x30000047, + Type::LARCH_PCALA_LO12 => 0x30000048, + Type::LARCH_PCALA64_LO20 => 0x30000049, + Type::LARCH_PCALA64_HI12 => 0x3000004a, + Type::LARCH_GOT_PC_HI20 => 0x3000004b, + Type::LARCH_GOT_PC_LO12 => 0x3000004c, + Type::LARCH_GOT64_PC_LO20 => 0x3000004d, + Type::LARCH_GOT64_PC_HI12 => 0x3000004e, + Type::LARCH_GOT_HI20 => 0x3000004f, + Type::LARCH_GOT_LO12 => 0x30000050, + Type::LARCH_GOT64_LO20 => 0x30000051, + Type::LARCH_GOT64_HI12 => 0x30000052, + Type::LARCH_TLS_LE_HI20 => 0x30000053, + Type::LARCH_TLS_LE_LO12 => 0x30000054, + Type::LARCH_TLS_LE64_LO20 => 0x30000055, + Type::LARCH_TLS_LE64_HI12 => 0x30000056, + Type::LARCH_TLS_IE_PC_HI20 => 0x30000057, + Type::LARCH_TLS_IE_PC_LO12 => 0x30000058, + Type::LARCH_TLS_IE64_PC_LO20 => 0x30000059, + Type::LARCH_TLS_IE64_PC_HI12 => 0x3000005a, + Type::LARCH_TLS_IE_HI20 => 0x3000005b, + Type::LARCH_TLS_IE_LO12 => 0x3000005c, + Type::LARCH_TLS_IE64_LO20 => 0x3000005d, + Type::LARCH_TLS_IE64_HI12 => 0x3000005e, + Type::LARCH_TLS_LD_PC_HI20 => 0x3000005f, + Type::LARCH_TLS_LD_HI20 => 0x30000060, + Type::LARCH_TLS_GD_PC_HI20 => 0x30000061, + Type::LARCH_TLS_GD_HI20 => 0x30000062, + Type::LARCH_32_PCREL => 0x30000063, + Type::LARCH_RELAX => 0x30000064, + Type::LARCH_ALIGN => 0x30000066, + Type::LARCH_PCREL20_S2 => 0x30000067, + Type::LARCH_ADD6 => 0x30000069, + Type::LARCH_SUB6 => 0x3000006a, + Type::LARCH_ADD_ULEB128 => 0x3000006b, + Type::LARCH_SUB_ULEB128 => 0x3000006c, + Type::LARCH_64_PCREL => 0x3000006d, + Type::LARCH_CALL36 => 0x3000006e, + Type::LARCH_TLS_DESC32 => 0x3000000d, + Type::LARCH_TLS_DESC64 => 0x3000000e, + Type::LARCH_TLS_DESC_PC_HI20 => 0x3000006f, + Type::LARCH_TLS_DESC_PC_LO12 => 0x30000070, + Type::LARCH_TLS_DESC64_PC_LO20 => 0x30000071, + Type::LARCH_TLS_DESC64_PC_HI12 => 0x30000072, + Type::LARCH_TLS_DESC_HI20 => 0x30000073, + Type::LARCH_TLS_DESC_LO12 => 0x30000074, + Type::LARCH_TLS_DESC64_LO20 => 0x30000075, + Type::LARCH_TLS_DESC64_HI12 => 0x30000076, + Type::LARCH_TLS_DESC_LD => 0x30000077, + Type::LARCH_TLS_DESC_CALL => 0x30000078, + Type::LARCH_TLS_LE_HI20_R => 0x30000079, + Type::LARCH_TLS_LE_ADD_R => 0x3000007a, + Type::LARCH_TLS_LE_LO12_R => 0x3000007b, + Type::LARCH_TLS_LD_PCREL20_S2 => 0x3000007c, + Type::LARCH_TLS_GD_PCREL20_S2 => 0x3000007d, + Type::LARCH_TLS_DESC_PCREL20_S2 => 0x3000007e, + Type::MIPS_NONE => 0x38000000, + Type::MIPS_16 => 0x38000001, + Type::MIPS_32 => 0x38000002, + Type::MIPS_REL32 => 0x38000003, + Type::MIPS_26 => 0x38000004, + Type::MIPS_HI16 => 0x38000005, + Type::MIPS_LO16 => 0x38000006, + Type::MIPS_GPREL16 => 0x38000007, + Type::MIPS_LITERAL => 0x38000008, + Type::MIPS_GOT16 => 0x38000009, + Type::MIPS_PC16 => 0x3800000a, + Type::MIPS_CALL16 => 0x3800000b, + Type::MIPS_GPREL32 => 0x3800000c, + Type::MIPS_UNUSED1 => 0x3800000d, + Type::MIPS_UNUSED2 => 0x3800000e, + Type::MIPS_UNUSED3 => 0x3800000f, + Type::MIPS_SHIFT5 => 0x38000010, + Type::MIPS_SHIFT6 => 0x38000011, + Type::MIPS_64 => 0x38000012, + Type::MIPS_GOT_DISP => 0x38000013, + Type::MIPS_GOT_PAGE => 0x38000014, + Type::MIPS_GOT_OFST => 0x38000015, + Type::MIPS_GOT_HI16 => 0x38000016, + Type::MIPS_GOT_LO16 => 0x38000017, + Type::MIPS_SUB => 0x38000018, + Type::MIPS_INSERT_A => 0x38000019, + Type::MIPS_INSERT_B => 0x3800001a, + Type::MIPS_DELETE => 0x3800001b, + Type::MIPS_HIGHER => 0x3800001c, + Type::MIPS_HIGHEST => 0x3800001d, + Type::MIPS_CALL_HI16 => 0x3800001e, + Type::MIPS_CALL_LO16 => 0x3800001f, + Type::MIPS_SCN_DISP => 0x38000020, + Type::MIPS_REL16 => 0x38000021, + Type::MIPS_ADD_IMMEDIATE => 0x38000022, + Type::MIPS_PJUMP => 0x38000023, + Type::MIPS_RELGOT => 0x38000024, + Type::MIPS_JALR => 0x38000025, + Type::MIPS_TLS_DTPMOD32 => 0x38000026, + Type::MIPS_TLS_DTPREL32 => 0x38000027, + Type::MIPS_TLS_DTPMOD64 => 0x38000028, + Type::MIPS_TLS_DTPREL64 => 0x38000029, + Type::MIPS_TLS_GD => 0x3800002a, + Type::MIPS_TLS_LDM => 0x3800002b, + Type::MIPS_TLS_DTPREL_HI16 => 0x3800002c, + Type::MIPS_TLS_DTPREL_LO16 => 0x3800002d, + Type::MIPS_TLS_GOTTPREL => 0x3800002e, + Type::MIPS_TLS_TPREL32 => 0x3800002f, + Type::MIPS_TLS_TPREL64 => 0x38000030, + Type::MIPS_TLS_TPREL_HI16 => 0x38000031, + Type::MIPS_TLS_TPREL_LO16 => 0x38000032, + Type::MIPS_GLOB_DAT => 0x38000033, + Type::MIPS_PC21_S2 => 0x3800003c, + Type::MIPS_PC26_S2 => 0x3800003d, + Type::MIPS_PC18_S3 => 0x3800003e, + Type::MIPS_PC19_S2 => 0x3800003f, + Type::MIPS_PCHI16 => 0x38000040, + Type::MIPS_PCLO16 => 0x38000041, + Type::MIPS16_26 => 0x38000064, + Type::MIPS16_GPREL => 0x38000065, + Type::MIPS16_GOT16 => 0x38000066, + Type::MIPS16_CALL16 => 0x38000067, + Type::MIPS16_HI16 => 0x38000068, + Type::MIPS16_LO16 => 0x38000069, + Type::MIPS16_TLS_GD => 0x3800006a, + Type::MIPS16_TLS_LDM => 0x3800006b, + Type::MIPS16_TLS_DTPREL_HI16 => 0x3800006c, + Type::MIPS16_TLS_DTPREL_LO16 => 0x3800006d, + Type::MIPS16_TLS_GOTTPREL => 0x3800006e, + Type::MIPS16_TLS_TPREL_HI16 => 0x3800006f, + Type::MIPS16_TLS_TPREL_LO16 => 0x38000070, + Type::MIPS_COPY => 0x3800007e, + Type::MIPS_JUMP_SLOT => 0x3800007f, + Type::MICROMIPS_26_S1 => 0x38000085, + Type::MICROMIPS_HI16 => 0x38000086, + Type::MICROMIPS_LO16 => 0x38000087, + Type::MICROMIPS_GPREL16 => 0x38000088, + Type::MICROMIPS_LITERAL => 0x38000089, + Type::MICROMIPS_GOT16 => 0x3800008a, + Type::MICROMIPS_PC7_S1 => 0x3800008b, + Type::MICROMIPS_PC10_S1 => 0x3800008c, + Type::MICROMIPS_PC16_S1 => 0x3800008d, + Type::MICROMIPS_CALL16 => 0x3800008e, + Type::MICROMIPS_GOT_DISP => 0x38000091, + Type::MICROMIPS_GOT_PAGE => 0x38000092, + Type::MICROMIPS_GOT_OFST => 0x38000093, + Type::MICROMIPS_GOT_HI16 => 0x38000094, + Type::MICROMIPS_GOT_LO16 => 0x38000095, + Type::MICROMIPS_SUB => 0x38000096, + Type::MICROMIPS_HIGHER => 0x38000097, + Type::MICROMIPS_HIGHEST => 0x38000098, + Type::MICROMIPS_CALL_HI16 => 0x38000099, + Type::MICROMIPS_CALL_LO16 => 0x3800009a, + Type::MICROMIPS_SCN_DISP => 0x3800009b, + Type::MICROMIPS_JALR => 0x3800009c, + Type::MICROMIPS_HI0_LO16 => 0x3800009d, + Type::MICROMIPS_TLS_GD => 0x380000a2, + Type::MICROMIPS_TLS_LDM => 0x380000a3, + Type::MICROMIPS_TLS_DTPREL_HI16 => 0x380000a4, + Type::MICROMIPS_TLS_DTPREL_LO16 => 0x380000a5, + Type::MICROMIPS_TLS_GOTTPREL => 0x380000a6, + Type::MICROMIPS_TLS_TPREL_HI16 => 0x380000a9, + Type::MICROMIPS_TLS_TPREL_LO16 => 0x380000aa, + Type::MICROMIPS_GPREL7_S2 => 0x380000ac, + Type::MICROMIPS_PC23_S2 => 0x380000ad, + Type::MICROMIPS_PC21_S2 => 0x380000ae, + Type::MICROMIPS_PC26_S2 => 0x380000af, + Type::MICROMIPS_PC18_S3 => 0x380000b0, + Type::MICROMIPS_PC19_S2 => 0x380000b1, + Type::MIPS_NUM => 0x380000da, + Type::MIPS_PC32 => 0x380000f8, + Type::MIPS_EH => 0x380000f9, + Type::PPC_NONE => 0x40000000, + Type::PPC_ADDR32 => 0x40000001, + Type::PPC_ADDR24 => 0x40000002, + Type::PPC_ADDR16 => 0x40000003, + Type::PPC_ADDR16_LO => 0x40000004, + Type::PPC_ADDR16_HI => 0x40000005, + Type::PPC_ADDR16_HA => 0x40000006, + Type::PPC_ADDR14 => 0x40000007, + Type::PPC_ADDR14_BRTAKEN => 0x40000008, + Type::PPC_ADDR14_BRNTAKEN => 0x40000009, + Type::PPC_REL24 => 0x4000000a, + Type::PPC_REL14 => 0x4000000b, + Type::PPC_REL14_BRTAKEN => 0x4000000c, + Type::PPC_REL14_BRNTAKEN => 0x4000000d, + Type::PPC_GOT16 => 0x4000000e, + Type::PPC_GOT16_LO => 0x4000000f, + Type::PPC_GOT16_HI => 0x40000010, + Type::PPC_GOT16_HA => 0x40000011, + Type::PPC_PLTREL24 => 0x40000012, + Type::PPC_JMP_SLOT => 0x40000015, + Type::PPC_RELATIVE => 0x40000016, + Type::PPC_LOCAL24PC => 0x40000017, + Type::PPC_REL32 => 0x4000001a, + Type::PPC_TLS => 0x40000043, + Type::PPC_DTPMOD32 => 0x40000044, + Type::PPC_TPREL16 => 0x40000045, + Type::PPC_TPREL16_LO => 0x40000046, + Type::PPC_TPREL16_HI => 0x40000047, + Type::PPC_TPREL16_HA => 0x40000048, + Type::PPC_TPREL32 => 0x40000049, + Type::PPC_DTPREL16 => 0x4000004a, + Type::PPC_DTPREL16_LO => 0x4000004b, + Type::PPC_DTPREL16_HI => 0x4000004c, + Type::PPC_DTPREL16_HA => 0x4000004d, + Type::PPC_DTPREL32 => 0x4000004e, + Type::PPC_GOT_TLSGD16 => 0x4000004f, + Type::PPC_GOT_TLSGD16_LO => 0x40000050, + Type::PPC_GOT_TLSGD16_HI => 0x40000051, + Type::PPC_GOT_TLSGD16_HA => 0x40000052, + Type::PPC_GOT_TLSLD16 => 0x40000053, + Type::PPC_GOT_TLSLD16_LO => 0x40000054, + Type::PPC_GOT_TLSLD16_HI => 0x40000055, + Type::PPC_GOT_TLSLD16_HA => 0x40000056, + Type::PPC_GOT_TPREL16 => 0x40000057, + Type::PPC_GOT_TPREL16_LO => 0x40000058, + Type::PPC_GOT_TPREL16_HI => 0x40000059, + Type::PPC_GOT_TPREL16_HA => 0x4000005a, + Type::PPC_GOT_DTPREL16 => 0x4000005b, + Type::PPC_GOT_DTPREL16_LO => 0x4000005c, + Type::PPC_GOT_DTPREL16_HI => 0x4000005d, + Type::PPC_GOT_DTPREL16_HA => 0x4000005e, + Type::PPC_TLSGD => 0x4000005f, + Type::PPC_TLSLD => 0x40000060, + Type::PPC_REL16 => 0x400000f9, + Type::PPC_REL16_LO => 0x400000fa, + Type::PPC_REL16_HI => 0x400000fb, + Type::PPC_REL16_HA => 0x400000fc, + Type::PPC64_NONE => 0x48000000, + Type::PPC64_ADDR32 => 0x48000001, + Type::PPC64_ADDR24 => 0x48000002, + Type::PPC64_ADDR16 => 0x48000003, + Type::PPC64_ADDR16_LO => 0x48000004, + Type::PPC64_ADDR16_HI => 0x48000005, + Type::PPC64_ADDR16_HA => 0x48000006, + Type::PPC64_ADDR14 => 0x48000007, + Type::PPC64_ADDR14_BRTAKEN => 0x48000008, + Type::PPC64_ADDR14_BRNTAKEN => 0x48000009, + Type::PPC64_REL24 => 0x4800000a, + Type::PPC64_REL14 => 0x4800000b, + Type::PPC64_REL14_BRTAKEN => 0x4800000c, + Type::PPC64_REL14_BRNTAKEN => 0x4800000d, + Type::PPC64_GOT16 => 0x4800000e, + Type::PPC64_GOT16_LO => 0x4800000f, + Type::PPC64_GOT16_HI => 0x48000010, + Type::PPC64_GOT16_HA => 0x48000011, + Type::PPC64_JMP_SLOT => 0x48000015, + Type::PPC64_RELATIVE => 0x48000016, + Type::PPC64_REL32 => 0x4800001a, + Type::PPC64_ADDR64 => 0x48000026, + Type::PPC64_ADDR16_HIGHER => 0x48000027, + Type::PPC64_ADDR16_HIGHERA => 0x48000028, + Type::PPC64_ADDR16_HIGHEST => 0x48000029, + Type::PPC64_ADDR16_HIGHESTA => 0x4800002a, + Type::PPC64_REL64 => 0x4800002c, + Type::PPC64_TOC16 => 0x4800002f, + Type::PPC64_TOC16_LO => 0x48000030, + Type::PPC64_TOC16_HI => 0x48000031, + Type::PPC64_TOC16_HA => 0x48000032, + Type::PPC64_TOC => 0x48000033, + Type::PPC64_ADDR16_DS => 0x48000038, + Type::PPC64_ADDR16_LO_DS => 0x48000039, + Type::PPC64_GOT16_DS => 0x4800003a, + Type::PPC64_GOT16_LO_DS => 0x4800003b, + Type::PPC64_TOC16_DS => 0x4800003f, + Type::PPC64_TOC16_LO_DS => 0x48000040, + Type::PPC64_TLS => 0x48000043, + Type::PPC64_DTPMOD64 => 0x48000044, + Type::PPC64_TPREL16 => 0x48000045, + Type::PPC64_TPREL16_LO => 0x48000046, + Type::PPC64_TPREL16_HI => 0x48000047, + Type::PPC64_TPREL16_HA => 0x48000048, + Type::PPC64_TPREL64 => 0x48000049, + Type::PPC64_DTPREL16 => 0x4800004a, + Type::PPC64_DTPREL16_LO => 0x4800004b, + Type::PPC64_DTPREL16_HI => 0x4800004c, + Type::PPC64_DTPREL16_HA => 0x4800004d, + Type::PPC64_DTPREL64 => 0x4800004e, + Type::PPC64_GOT_TLSGD16 => 0x4800004f, + Type::PPC64_GOT_TLSGD16_LO => 0x48000050, + Type::PPC64_GOT_TLSGD16_HI => 0x48000051, + Type::PPC64_GOT_TLSGD16_HA => 0x48000052, + Type::PPC64_GOT_TLSLD16 => 0x48000053, + Type::PPC64_GOT_TLSLD16_LO => 0x48000054, + Type::PPC64_GOT_TLSLD16_HI => 0x48000055, + Type::PPC64_GOT_TLSLD16_HA => 0x48000056, + Type::PPC64_GOT_TPREL16_DS => 0x48000057, + Type::PPC64_GOT_TPREL16_LO_DS => 0x48000058, + Type::PPC64_GOT_TPREL16_HI => 0x48000059, + Type::PPC64_GOT_TPREL16_HA => 0x4800005a, + Type::PPC64_GOT_DTPREL16_DS => 0x4800005b, + Type::PPC64_GOT_DTPREL16_LO_DS => 0x4800005c, + Type::PPC64_GOT_DTPREL16_HI => 0x4800005d, + Type::PPC64_GOT_DTPREL16_HA => 0x4800005e, + Type::PPC64_TPREL16_DS => 0x4800005f, + Type::PPC64_TPREL16_LO_DS => 0x48000060, + Type::PPC64_TPREL16_HIGHER => 0x48000061, + Type::PPC64_TPREL16_HIGHERA => 0x48000062, + Type::PPC64_TPREL16_HIGHEST => 0x48000063, + Type::PPC64_TPREL16_HIGHESTA => 0x48000064, + Type::PPC64_DTPREL16_DS => 0x48000065, + Type::PPC64_DTPREL16_LO_DS => 0x48000066, + Type::PPC64_DTPREL16_HIGHER => 0x48000067, + Type::PPC64_DTPREL16_HIGHERA => 0x48000068, + Type::PPC64_DTPREL16_HIGHEST => 0x48000069, + Type::PPC64_DTPREL16_HIGHESTA => 0x4800006a, + Type::PPC64_TLSGD => 0x4800006b, + Type::PPC64_TLSLD => 0x4800006c, + Type::PPC64_REL16 => 0x480000f9, + Type::PPC64_REL16_LO => 0x480000fa, + Type::PPC64_REL16_HI => 0x480000fb, + Type::PPC64_REL16_HA => 0x480000fc, + Type::SPARC_NONE => 0x50000000, + Type::SPARC_8 => 0x50000001, + Type::SPARC_16 => 0x50000002, + Type::SPARC_32 => 0x50000003, + Type::SPARC_DISP8 => 0x50000004, + Type::SPARC_DISP16 => 0x50000005, + Type::SPARC_DISP32 => 0x50000006, + Type::SPARC_WDISP30 => 0x50000007, + Type::SPARC_WDISP22 => 0x50000008, + Type::SPARC_HI22 => 0x50000009, + Type::SPARC_22 => 0x5000000a, + Type::SPARC_13 => 0x5000000b, + Type::SPARC_LO10 => 0x5000000c, + Type::SPARC_GOT10 => 0x5000000d, + Type::SPARC_GOT13 => 0x5000000e, + Type::SPARC_GOT22 => 0x5000000f, + Type::SPARC_PC10 => 0x50000010, + Type::SPARC_PC22 => 0x50000011, + Type::SPARC_WPLT30 => 0x50000012, + Type::SPARC_COPY => 0x50000013, + Type::SPARC_GLOB_DAT => 0x50000014, + Type::SPARC_JMP_SLOT => 0x50000015, + Type::SPARC_RELATIVE => 0x50000016, + Type::SPARC_UA32 => 0x50000017, + Type::SPARC_PLT32 => 0x50000018, + Type::SPARC_HIPLT22 => 0x50000019, + Type::SPARC_LOPLT10 => 0x5000001a, + Type::SPARC_PCPLT32 => 0x5000001b, + Type::SPARC_PCPLT22 => 0x5000001c, + Type::SPARC_PCPLT10 => 0x5000001d, + Type::SPARC_10 => 0x5000001e, + Type::SPARC_11 => 0x5000001f, + Type::SPARC_64 => 0x50000020, + Type::SPARC_OLO10 => 0x50000021, + Type::SPARC_HH22 => 0x50000022, + Type::SPARC_HM10 => 0x50000023, + Type::SPARC_LM22 => 0x50000024, + Type::SPARC_PC_HH22 => 0x50000025, + Type::SPARC_PC_HM10 => 0x50000026, + Type::SPARC_PC_LM22 => 0x50000027, + Type::SPARC_WDISP16 => 0x50000028, + Type::SPARC_WDISP19 => 0x50000029, + Type::SPARC_7 => 0x5000002b, + Type::SPARC_5 => 0x5000002c, + Type::SPARC_6 => 0x5000002d, + Type::SPARC_DISP64 => 0x5000002e, + Type::SPARC_PLT64 => 0x5000002f, + Type::SPARC_HIX22 => 0x50000030, + Type::SPARC_LOX10 => 0x50000031, + Type::SPARC_H44 => 0x50000032, + Type::SPARC_M44 => 0x50000033, + Type::SPARC_L44 => 0x50000034, + Type::SPARC_REGISTER => 0x50000035, + Type::SPARC_UA64 => 0x50000036, + Type::SPARC_UA16 => 0x50000037, + Type::SPARC_TLS_GD_HI22 => 0x50000038, + Type::SPARC_TLS_GD_LO10 => 0x50000039, + Type::SPARC_TLS_GD_ADD => 0x5000003a, + Type::SPARC_TLS_GD_CALL => 0x5000003b, + Type::SPARC_TLS_LDM_HI22 => 0x5000003c, + Type::SPARC_TLS_LDM_LO10 => 0x5000003d, + Type::SPARC_TLS_LDM_ADD => 0x5000003e, + Type::SPARC_TLS_LDM_CALL => 0x5000003f, + Type::SPARC_TLS_LDO_HIX22 => 0x50000040, + Type::SPARC_TLS_LDO_LOX10 => 0x50000041, + Type::SPARC_TLS_LDO_ADD => 0x50000042, + Type::SPARC_TLS_IE_HI22 => 0x50000043, + Type::SPARC_TLS_IE_LO10 => 0x50000044, + Type::SPARC_TLS_IE_LD => 0x50000045, + Type::SPARC_TLS_IE_LDX => 0x50000046, + Type::SPARC_TLS_IE_ADD => 0x50000047, + Type::SPARC_TLS_LE_HIX22 => 0x50000048, + Type::SPARC_TLS_LE_LOX10 => 0x50000049, + Type::SPARC_TLS_DTPMOD32 => 0x5000004a, + Type::SPARC_TLS_DTPMOD64 => 0x5000004b, + Type::SPARC_TLS_DTPOFF32 => 0x5000004c, + Type::SPARC_TLS_DTPOFF64 => 0x5000004d, + Type::SPARC_TLS_TPOFF32 => 0x5000004e, + Type::SPARC_TLS_TPOFF64 => 0x5000004f, + Type::SPARC_GOTDATA_HIX22 => 0x50000050, + Type::SPARC_GOTDATA_LOX10 => 0x50000051, + Type::SPARC_GOTDATA_OP_HIX22 => 0x50000052, + Type::SPARC_GOTDATA_OP_LOX10 => 0x50000053, + Type::SPARC_GOTDATA_OP => 0x50000054, + Type::SYSZ_NONE => 0x58000000, + Type::SYSZ_8 => 0x58000001, + Type::SYSZ_12 => 0x58000002, + Type::SYSZ_16 => 0x58000003, + Type::SYSZ_32 => 0x58000004, + Type::SYSZ_PC32 => 0x58000005, + Type::SYSZ_GOT12 => 0x58000006, + Type::SYSZ_GOT32 => 0x58000007, + Type::SYSZ_PLT32 => 0x58000008, + Type::SYSZ_COPY => 0x58000009, + Type::SYSZ_GLOB_DAT => 0x5800000a, + Type::SYSZ_JMP_SLOT => 0x5800000b, + Type::SYSZ_RELATIVE => 0x5800000c, + Type::SYSZ_GOTOFF => 0x5800000d, + Type::SYSZ_GOTPC => 0x5800000e, + Type::SYSZ_GOT16 => 0x5800000f, + Type::SYSZ_PC16 => 0x58000010, + Type::SYSZ_PC16DBL => 0x58000011, + Type::SYSZ_PLT16DBL => 0x58000012, + Type::SYSZ_PC32DBL => 0x58000013, + Type::SYSZ_PLT32DBL => 0x58000014, + Type::SYSZ_GOTPCDBL => 0x58000015, + Type::SYSZ_64 => 0x58000016, + Type::SYSZ_PC64 => 0x58000017, + Type::SYSZ_GOT64 => 0x58000018, + Type::SYSZ_PLT64 => 0x58000019, + Type::SYSZ_GOTENT => 0x5800001a, + Type::SYSZ_GOTOFF16 => 0x5800001b, + Type::SYSZ_GOTOFF64 => 0x5800001c, + Type::SYSZ_GOTPLT12 => 0x5800001d, + Type::SYSZ_GOTPLT16 => 0x5800001e, + Type::SYSZ_GOTPLT32 => 0x5800001f, + Type::SYSZ_GOTPLT64 => 0x58000020, + Type::SYSZ_GOTPLTENT => 0x58000021, + Type::SYSZ_PLTOFF16 => 0x58000022, + Type::SYSZ_PLTOFF32 => 0x58000023, + Type::SYSZ_PLTOFF64 => 0x58000024, + Type::SYSZ_TLS_LOAD => 0x58000025, + Type::SYSZ_TLS_GDCALL => 0x58000026, + Type::SYSZ_TLS_LDCALL => 0x58000027, + Type::SYSZ_TLS_GD32 => 0x58000028, + Type::SYSZ_TLS_GD64 => 0x58000029, + Type::SYSZ_TLS_GOTIE12 => 0x5800002a, + Type::SYSZ_TLS_GOTIE32 => 0x5800002b, + Type::SYSZ_TLS_GOTIE64 => 0x5800002c, + Type::SYSZ_TLS_LDM32 => 0x5800002d, + Type::SYSZ_TLS_LDM64 => 0x5800002e, + Type::SYSZ_TLS_IE32 => 0x5800002f, + Type::SYSZ_TLS_IE64 => 0x58000030, + Type::SYSZ_TLS_IEENT => 0x58000031, + Type::SYSZ_TLS_LE32 => 0x58000032, + Type::SYSZ_TLS_LE64 => 0x58000033, + Type::SYSZ_TLS_LDO32 => 0x58000034, + Type::SYSZ_TLS_LDO64 => 0x58000035, + Type::SYSZ_TLS_DTPMOD => 0x58000036, + Type::SYSZ_TLS_DTPOFF => 0x58000037, + Type::SYSZ_TLS_TPOFF => 0x58000038, + Type::SYSZ_20 => 0x58000039, + Type::SYSZ_GOT20 => 0x5800003a, + Type::SYSZ_GOTPLT20 => 0x5800003b, + Type::SYSZ_TLS_GOTIE20 => 0x5800003c, + Type::SYSZ_IRELATIVE => 0x5800003d, + Type::SYSZ_PC12DBL => 0x5800003e, + Type::SYSZ_PLT12DBL => 0x5800003f, + Type::SYSZ_PC24DBL => 0x58000040, + Type::SYSZ_PLT24DBL => 0x58000041, + Type::RISCV_NONE => 0x60000000, + Type::RISCV_32 => 0x60000001, + Type::RISCV_64 => 0x60000002, + Type::RISCV_RELATIVE => 0x60000003, + Type::RISCV_COPY => 0x60000004, + Type::RISCV_JUMP_SLOT => 0x60000005, + Type::RISCV_TLS_DTPMOD32 => 0x60000006, + Type::RISCV_TLS_DTPMOD64 => 0x60000007, + Type::RISCV_TLS_DTPREL32 => 0x60000008, + Type::RISCV_TLS_DTPREL64 => 0x60000009, + Type::RISCV_TLS_TPREL32 => 0x6000000a, + Type::RISCV_TLS_TPREL64 => 0x6000000b, + Type::RISCV_TLSDESC => 0x6000000c, + Type::RISCV_BRANCH => 0x60000010, + Type::RISCV_JAL => 0x60000011, + Type::RISCV_CALL => 0x60000012, + Type::RISCV_CALL_PLT => 0x60000013, + Type::RISCV_GOT_HI20 => 0x60000014, + Type::RISCV_TLS_GOT_HI20 => 0x60000015, + Type::RISCV_TLS_GD_HI20 => 0x60000016, + Type::RISCV_PCREL_HI20 => 0x60000017, + Type::RISCV_PCREL_LO12_I => 0x60000018, + Type::RISCV_PCREL_LO12_S => 0x60000019, + Type::RISCV_HI20 => 0x6000001a, + Type::RISCV_LO12_I => 0x6000001b, + Type::RISCV_LO12_S => 0x6000001c, + Type::RISCV_TPREL_HI20 => 0x6000001d, + Type::RISCV_TPREL_LO12_I => 0x6000001e, + Type::RISCV_TPREL_LO12_S => 0x6000001f, + Type::RISCV_TPREL_ADD => 0x60000020, + Type::RISCV_ADD8 => 0x60000021, + Type::RISCV_ADD16 => 0x60000022, + Type::RISCV_ADD32 => 0x60000023, + Type::RISCV_ADD64 => 0x60000024, + Type::RISCV_SUB8 => 0x60000025, + Type::RISCV_SUB16 => 0x60000026, + Type::RISCV_SUB32 => 0x60000027, + Type::RISCV_SUB64 => 0x60000028, + Type::RISCV_GOT32_PCREL => 0x60000029, + Type::RISCV_ALIGN => 0x6000002b, + Type::RISCV_RVC_BRANCH => 0x6000002c, + Type::RISCV_RVC_JUMP => 0x6000002d, + Type::RISCV_RVC_LUI => 0x6000002e, + Type::RISCV_RELAX => 0x60000033, + Type::RISCV_SUB6 => 0x60000034, + Type::RISCV_SET6 => 0x60000035, + Type::RISCV_SET8 => 0x60000036, + Type::RISCV_SET16 => 0x60000037, + Type::RISCV_SET32 => 0x60000038, + Type::RISCV_32_PCREL => 0x60000039, + Type::RISCV_IRELATIVE => 0x6000003a, + Type::RISCV_PLT32 => 0x6000003b, + Type::RISCV_SET_ULEB128 => 0x6000003c, + Type::RISCV_SUB_ULEB128 => 0x6000003d, + Type::RISCV_TLSDESC_HI20 => 0x6000003e, + Type::RISCV_TLSDESC_LOAD_LO12 => 0x6000003f, + Type::RISCV_TLSDESC_ADD_LO12 => 0x60000040, + Type::RISCV_TLSDESC_CALL => 0x60000041, + Type::BPF_NONE => 0x68000000, + Type::BPF_64_64 => 0x68000001, + Type::BPF_64_ABS64 => 0x68000002, + Type::BPF_64_ABS32 => 0x68000003, + Type::BPF_64_NODYLD32 => 0x68000004, + Type::BPF_64_32 => 0x6800000a, + Type::SH_NONE => 0x70000000, + Type::SH_DIR32 => 0x70000001, + Type::SH_REL32 => 0x70000002, + Type::SH_DIR8WPN => 0x70000003, + Type::SH_IND12W => 0x70000004, + Type::SH_DIR8WPL => 0x70000005, + Type::SH_DIR8WPZ => 0x70000006, + Type::SH_DIR8BP => 0x70000007, + Type::SH_DIR8W => 0x70000008, + Type::SH_DIR8L => 0x70000009, + Type::SH_LOOP_START => 0x7000000a, + Type::SH_LOOP_END => 0x7000000b, + Type::SH_GNU_VTINHERIT => 0x70000016, + Type::SH_GNU_VTENTRY => 0x70000017, + Type::SH_SWITCH8 => 0x70000018, + Type::SH_SWITCH16 => 0x70000019, + Type::SH_SWITCH32 => 0x7000001a, + Type::SH_USES => 0x7000001b, + Type::SH_COUNT => 0x7000001c, + Type::SH_ALIGN => 0x7000001d, + Type::SH_CODE => 0x7000001e, + Type::SH_DATA => 0x7000001f, + Type::SH_LABEL => 0x70000020, + Type::SH_DIR16 => 0x70000021, + Type::SH_DIR8 => 0x70000022, + Type::SH_DIR8UL => 0x70000023, + Type::SH_DIR8UW => 0x70000024, + Type::SH_DIR8U => 0x70000025, + Type::SH_DIR8SW => 0x70000026, + Type::SH_DIR8S => 0x70000027, + Type::SH_DIR4UL => 0x70000028, + Type::SH_DIR4UW => 0x70000029, + Type::SH_DIR4U => 0x7000002a, + Type::SH_PSHA => 0x7000002b, + Type::SH_PSHL => 0x7000002c, + Type::SH_DIR5U => 0x7000002d, + Type::SH_DIR6U => 0x7000002e, + Type::SH_DIR6S => 0x7000002f, + Type::SH_DIR10S => 0x70000030, + Type::SH_DIR10SW => 0x70000031, + Type::SH_DIR10SL => 0x70000032, + Type::SH_DIR10SQ => 0x70000033, + Type::SH_DIR16S => 0x70000035, + Type::SH_TLS_GD_32 => 0x70000090, + Type::SH_TLS_LD_32 => 0x70000091, + Type::SH_TLS_LDO_32 => 0x70000092, + Type::SH_TLS_IE_32 => 0x70000093, + Type::SH_TLS_LE_32 => 0x70000094, + Type::SH_TLS_DTPMOD32 => 0x70000095, + Type::SH_TLS_DTPOFF32 => 0x70000096, + Type::SH_TLS_TPOFF32 => 0x70000097, + Type::SH_GOT32 => 0x700000a0, + Type::SH_PLT32 => 0x700000a1, + Type::SH_COPY => 0x700000a2, + Type::SH_GLOB_DAT => 0x700000a3, + Type::SH_JMP_SLOT => 0x700000a4, + Type::SH_RELATIVE => 0x700000a5, + Type::SH_GOTOFF => 0x700000a6, + Type::SH_GOTPC => 0x700000a7, + Type::SH_GOTPLT32 => 0x700000a8, + Type::SH_GOT_LOW16 => 0x700000a9, + Type::SH_GOT_MEDLOW16 => 0x700000aa, + Type::SH_GOT_MEDHI16 => 0x700000ab, + Type::SH_GOT_HI16 => 0x700000ac, + Type::SH_GOTPLT_LOW16 => 0x700000ad, + Type::SH_GOTPLT_MEDLOW16 => 0x700000ae, + Type::SH_GOTPLT_MEDHI16 => 0x700000af, + Type::SH_GOTPLT_HI16 => 0x700000b0, + Type::SH_PLT_LOW16 => 0x700000b1, + Type::SH_PLT_MEDLOW16 => 0x700000b2, + Type::SH_PLT_MEDHI16 => 0x700000b3, + Type::SH_PLT_HI16 => 0x700000b4, + Type::SH_GOTOFF_LOW16 => 0x700000b5, + Type::SH_GOTOFF_MEDLOW16 => 0x700000b6, + Type::SH_GOTOFF_MEDHI16 => 0x700000b7, + Type::SH_GOTOFF_HI16 => 0x700000b8, + Type::SH_GOTPC_LOW16 => 0x700000b9, + Type::SH_GOTPC_MEDLOW16 => 0x700000ba, + Type::SH_GOTPC_MEDHI16 => 0x700000bb, + Type::SH_GOTPC_HI16 => 0x700000bc, + Type::SH_GOT10BY4 => 0x700000bd, + Type::SH_GOTPLT10BY4 => 0x700000be, + Type::SH_GOT10BY8 => 0x700000bf, + Type::SH_GOTPLT10BY8 => 0x700000c0, + Type::SH_COPY64 => 0x700000c1, + Type::SH_GLOB_DAT64 => 0x700000c2, + Type::SH_JMP_SLOT64 => 0x700000c3, + Type::SH_RELATIVE64 => 0x700000c4, + Type::SH_GOT20 => 0x700000c9, + Type::SH_GOTOFF20 => 0x700000ca, + Type::SH_GOTFUNCDESC => 0x700000cb, + Type::SH_GOTFUNCDESC20 => 0x700000cc, + Type::SH_GOTOFFFUNCDESC => 0x700000cd, + Type::SH_GOTOFFFUNCDESC20 => 0x700000ce, + Type::SH_FUNCDESC => 0x700000cf, + Type::SH_FUNCDESC_VALUE => 0x700000d0, + Type::SH_SHMEDIA_CODE => 0x700000f2, + Type::SH_PT_16 => 0x700000f3, + Type::SH_IMMS16 => 0x700000f4, + Type::SH_IMMU16 => 0x700000f5, + Type::SH_IMM_LOW16 => 0x700000f6, + Type::SH_IMM_LOW16_PCREL => 0x700000f7, + Type::SH_IMM_MEDLOW16 => 0x700000f8, + Type::SH_IMM_MEDLOW16_PCREL => 0x700000f9, + Type::SH_IMM_MEDHI16 => 0x700000fa, + Type::SH_IMM_MEDHI16_PCREL => 0x700000fb, + Type::SH_IMM_HI16 => 0x700000fc, + Type::SH_IMM_HI16_PCREL => 0x700000fd, + Type::SH_64 => 0x700000fe, + Type::SH_64_PCREL => 0x700000ff, + Type::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// The *purpose* of a relocation defines how this relocation is used by the +/// loader. +pub enum Purpose { + NONE, + /// The relocation is associated with the PLT/GOT resolution + PLTGOT, + /// The relocation is used for regulard data/code relocation + DYNAMIC, + /// The relocation is used in an object file + OBJECT, + UNKNOWN(u32), +} + +impl Purpose { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000000 => Purpose::NONE, + 0x00000001 => Purpose::PLTGOT, + 0x00000002 => Purpose::DYNAMIC, + 0x00000003 => Purpose::OBJECT, + _ => Purpose::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Encoding { + /// The relocation is using the regular Elf_Rel structure + REL, + /// The relocation is using the regular Elf_Rela structure + RELA, + /// The relocation is using the relative relocation format + RELR, + /// The relocation is using the packed Android-SLEB128 format + ANDROID_SLEB, + UNKNOWN(u32), +} + +impl Encoding { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000001 => Encoding::REL, + 0x00000002 => Encoding::RELA, + 0x00000003 => Encoding::RELR, + 0x00000004 => Encoding::ANDROID_SLEB, + _ => Encoding::UNKNOWN(value), + } + } +} + +impl Relocation<'_> { + /// Additional value that can be involved in the relocation processing + pub fn addend(&self) -> i64 { + self.ptr.addend() + } + + /// Type of the relocation + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + + /// Check if the relocation uses the explicit [`Relocation::addend`] field + /// (this is usually the case for 64 bits binaries) + pub fn is_rela(&self) -> bool { + self.ptr.is_rela() + } + + /// Check if the relocation uses the implicit addend + /// (i.e. not present in the ELF structure) + pub fn is_rel(&self) -> bool { + self.ptr.is_rel() + } + + /// Relocation info which contains, for instance, the symbol index + pub fn info(&self) -> u32 { + self.ptr.info() + } + + /// Target architecture for this relocation + pub fn architecture(&self) -> u32 { + self.ptr.architecture() + } + + /// The purpose of the relocation + pub fn purpose(&self) -> Purpose { + Purpose::from_value(self.ptr.purpose()) + } + + /// The encoding of the relocation + pub fn encoding(&self) -> Encoding { + Encoding::from_value(self.ptr.encoding()) + } + + /// Symbol associated with the relocation (if any) + pub fn symbol(&self) -> Option> { + into_optional(self.ptr.symbol()) + } + + /// The section in which the relocation is applied (if any) + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } + + /// The associated symbol table (if any) + pub fn symbol_table(&self) -> Option> { + into_optional(self.ptr.symbol_table()) + } + + /// Try to resolve the value of the relocation with the provided base address. + /// + /// The returned value could be used such as: `*address = resolve_with_base_address(...)` + /// + /// See: [`Relocation::resolve`] + pub fn resolve_with_base_address(&self, base_address: u64) -> Result { + to_result!(ffi::ELF_Relocation::resolve, &self, base_address); + } + + /// Try to resolve the value of the relocation. + /// The returned value could be used such as: `*address = resolve(...)` + /// + /// See: [`Relocation::resolve_with_base_address`] + pub fn resolve(&self) -> Result { + self.resolve_with_base_address(0) + } +} + +impl std::fmt::Debug for Relocation<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Relocation; + f.debug_struct("Relocation") + .field("base", &base) + .field("addend", &self.addend()) + .field("type", &self.get_type()) + .field("info", &self.info()) + .field("architecture", &self.architecture()) + .field("purpose", &self.purpose()) + .field("encoding", &self.encoding()) + .field("symbol", &self.symbol()) + .field("section", &self.section()) + .field("symbol_table", &self.symbol_table()) + .finish() + } +} + +impl FromFFI for Relocation<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Relocation { + ptr, + _owner: PhantomData, + } + } +} + +impl crate::common::AsFFI for Relocation<'_> { + fn as_ffi(&self) -> &ffi::ELF_Relocation { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::ELF_Relocation> { + self.ptr.pin_mut() + } +} + +impl generic::Relocation for Relocation<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::ELF_Relocation, + ffi::ELF_Binary, + ffi::ELF_Binary_it_relocations +); +declare_iterator!( + PltGotRelocations, + Relocation<'a>, + ffi::ELF_Relocation, + ffi::ELF_Binary, + ffi::ELF_Binary_it_pltgot_relocations +); +declare_iterator!( + DynamicRelocations, + Relocation<'a>, + ffi::ELF_Relocation, + ffi::ELF_Binary, + ffi::ELF_Binary_it_dynamic_relocations +); +declare_iterator!( + ObjectRelocations, + Relocation<'a>, + ffi::ELF_Relocation, + ffi::ELF_Binary, + ffi::ELF_Binary_it_object_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/section.rs b/vendor/lief/api/rust/crates/lief/src/elf/section.rs new file mode 100644 index 0000000..3e14d11 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/section.rs @@ -0,0 +1,386 @@ +use bitflags::bitflags; +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; +use std::pin::Pin; + +use crate::common::FromFFI; +use crate::declare_iterator; +use crate::generic; +use crate::to_slice; + +/// Structure which represents an ELF Section +pub struct Section<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Section<'_> { + /// Create a new section + pub fn new() -> Section<'static> { + Section::from_ffi(ffi::ELF_Section::create()) + } + + /// Create a new section with the given name + pub fn new_with_name(name: &str) -> Section<'static> { + cxx::let_cxx_string!(__cxx_name = name); + Section::from_ffi(ffi::ELF_Section::create_with_name(&__cxx_name)) + } + + /// Create a new section with the given name and content + pub fn new_with_content(name: &str, content: &[u8]) -> Section<'static> { + cxx::let_cxx_string!(__cxx_name = name); + unsafe { + Section::from_ffi(ffi::ELF_Section::create_with_content( + &__cxx_name, + content.as_ptr(), + content.len(), + )) + } + } + + /// Type of the section + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + + /// Sections flags + pub fn flags(&self) -> Flags { + Flags::from_value(self.ptr.flags()) + } + + /// Section alignment + pub fn alignment(&self) -> u64 { + self.ptr.alignment() + } + + /// Section information. + /// This meaning of this value depends on the section's type + pub fn information(&self) -> u64 { + self.ptr.information() + } + + /// This function returns the size of an element in the case of a section that contains + /// an array. + /// + /// For instance, the `.dynamic` section contains an array of DynamicEntry. As the + /// size of the raw C structure of this entry is 0x10 (`sizeof(Elf64_Dyn)`) + /// in an ELF64, the `entry_size` is set to this value. + pub fn entry_size(&self) -> u64 { + self.ptr.entry_size() + } + + /// Index to another section + pub fn link(&self) -> u64 { + self.ptr.link() + } + + /// Offset in the file where the content of this section is located + pub fn file_offset(&self) -> u64 { + self.ptr.file_offset() + } + + /// Original size of the section (regardless modifications) + pub fn original_size(&self) -> u64 { + self.ptr.original_size() + } + + /// Content of the section as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Type { + /// No associated section (inactive entry) + SHT_NULL, + /// Program-defined contents. + PROGBITS, + /// Symbol table + SYMTAB, + /// String table + STRTAB, + /// Relocation entries; explicit addends. + RELA, + /// Symbol hash table. + HASH, + /// Information for dynamic linking. + DYNAMIC, + /// Information about the file. + NOTE, + /// Data occupies no space in the file. + NOBITS, + /// Relocation entries; no explicit addends. + REL, + /// Reserved + SHLIB, + /// Symbol table. + DYNSYM, + /// Pointers to initialization functions. + INIT_ARRAY, + /// Pointers to termination functions. + FINI_ARRAY, + /// Pointers to pre-init functions. + PREINIT_ARRAY, + /// Section group. + GROUP, + /// Indices for SHN_XINDEX entries. + SYMTAB_SHNDX, + /// Relocation entries; only offsets. + RELR, + /// Packed relocations (Android specific). + ANDROID_REL, + /// Packed relocations (Android specific). + ANDROID_RELA, + /// This section is used to mark symbols as address-significant. + LLVM_ADDRSIG, + /// New relr relocations (Android specific). + ANDROID_RELR, + /// Object attributes. + GNU_ATTRIBUTES, + /// GNU-style hash table. + GNU_HASH, + /// GNU version definitions. + GNU_VERDEF, + /// GNU version references. + GNU_VERNEED, + /// GNU symbol versions table. + GNU_VERSYM, + /// Exception Index table + ARM_EXIDX, + /// BPABI DLL dynamic linking pre-emption map + ARM_PREEMPTMAP, + /// Object file compatibility attributes + ARM_ATTRIBUTES, + ARM_DEBUGOVERLAY, + ARM_OVERLAYSECTION, + /// Link editor is to sort the entries in this section based on their sizes + HEX_ORDERED, + /// Unwind information + X86_64_UNWIND, + /// Register usage information + MIPS_REGINFO, + /// General options + MIPS_OPTIONS, + /// ABI information + MIPS_ABIFLAGS, + /// RISC-V Attribute + RISCV_ATTRIBUTES, + /// AArch64 build attributes + AARCH64_ATTRIBUTES, + /// AArch64 PAuth relocations + AARCH64_AUTH_RELR, + /// AArch64 memory tagging globals (static) + AARCH64_MEMTAG_GLOBALS_STATIC, + /// AArch64 memory tagging globals (dynamic) + AARCH64_MEMTAG_GLOBALS_DYNAMIC, + UNKNOWN(u64), +} + +impl From for Type { + fn from(value: u64) -> Self { + match value { + 0x00000000 => Type::SHT_NULL, + 0x00000001 => Type::PROGBITS, + 0x00000002 => Type::SYMTAB, + 0x00000003 => Type::STRTAB, + 0x00000004 => Type::RELA, + 0x00000005 => Type::HASH, + 0x00000006 => Type::DYNAMIC, + 0x00000007 => Type::NOTE, + 0x00000008 => Type::NOBITS, + 0x00000009 => Type::REL, + 0x0000000a => Type::SHLIB, + 0x0000000b => Type::DYNSYM, + 0x0000000e => Type::INIT_ARRAY, + 0x0000000f => Type::FINI_ARRAY, + 0x00000010 => Type::PREINIT_ARRAY, + 0x00000011 => Type::GROUP, + 0x00000012 => Type::SYMTAB_SHNDX, + 0x00000013 => Type::RELR, + 0x60000001 => Type::ANDROID_REL, + 0x60000002 => Type::ANDROID_RELA, + 0x6fff4c03 => Type::LLVM_ADDRSIG, + 0x6fffff00 => Type::ANDROID_RELR, + 0x6ffffff5 => Type::GNU_ATTRIBUTES, + 0x6ffffff6 => Type::GNU_HASH, + 0x6ffffffd => Type::GNU_VERDEF, + 0x6ffffffe => Type::GNU_VERNEED, + 0x6fffffff => Type::GNU_VERSYM, + 0x170000001 => Type::ARM_EXIDX, + 0x170000002 => Type::ARM_PREEMPTMAP, + 0x170000003 => Type::ARM_ATTRIBUTES, + 0x170000004 => Type::ARM_DEBUGOVERLAY, + 0x170000005 => Type::ARM_OVERLAYSECTION, + 0x270000000 => Type::HEX_ORDERED, + 0x270000001 => Type::X86_64_UNWIND, + 0x370000006 => Type::MIPS_REGINFO, + 0x37000000d => Type::MIPS_OPTIONS, + 0x37000002a => Type::MIPS_ABIFLAGS, + 0x470000003 => Type::RISCV_ATTRIBUTES, + 0x570000003 => Type::AARCH64_ATTRIBUTES, + 0x570000004 => Type::AARCH64_AUTH_RELR, + 0x570000007 => Type::AARCH64_MEMTAG_GLOBALS_STATIC, + 0x570000008 => Type::AARCH64_MEMTAG_GLOBALS_DYNAMIC, + _ => Type::UNKNOWN(value), + } + } +} +impl From for u64 { + fn from(value: Type) -> u64 { + match value { + Type::SHT_NULL => 0x00000000, + Type::PROGBITS => 0x00000001, + Type::SYMTAB => 0x00000002, + Type::STRTAB => 0x00000003, + Type::RELA => 0x00000004, + Type::HASH => 0x00000005, + Type::DYNAMIC => 0x00000006, + Type::NOTE => 0x00000007, + Type::NOBITS => 0x00000008, + Type::REL => 0x00000009, + Type::SHLIB => 0x0000000a, + Type::DYNSYM => 0x0000000b, + Type::INIT_ARRAY => 0x0000000e, + Type::FINI_ARRAY => 0x0000000f, + Type::PREINIT_ARRAY => 0x00000010, + Type::GROUP => 0x00000011, + Type::SYMTAB_SHNDX => 0x00000012, + Type::RELR => 0x00000013, + Type::ANDROID_REL => 0x60000001, + Type::ANDROID_RELA => 0x60000002, + Type::LLVM_ADDRSIG => 0x6fff4c03, + Type::ANDROID_RELR => 0x6fffff00, + Type::GNU_ATTRIBUTES => 0x6ffffff5, + Type::GNU_HASH => 0x6ffffff6, + Type::GNU_VERDEF => 0x6ffffffd, + Type::GNU_VERNEED => 0x6ffffffe, + Type::GNU_VERSYM => 0x6fffffff, + Type::ARM_EXIDX => 0x170000001, + Type::ARM_PREEMPTMAP => 0x170000002, + Type::ARM_ATTRIBUTES => 0x170000003, + Type::ARM_DEBUGOVERLAY => 0x170000004, + Type::ARM_OVERLAYSECTION => 0x170000005, + Type::HEX_ORDERED => 0x270000000, + Type::X86_64_UNWIND => 0x270000001, + Type::MIPS_REGINFO => 0x370000006, + Type::MIPS_OPTIONS => 0x37000000d, + Type::MIPS_ABIFLAGS => 0x37000002a, + Type::RISCV_ATTRIBUTES => 0x470000003, + Type::AARCH64_ATTRIBUTES => 0x570000003, + Type::AARCH64_AUTH_RELR => 0x570000004, + Type::AARCH64_MEMTAG_GLOBALS_STATIC => 0x570000007, + Type::AARCH64_MEMTAG_GLOBALS_DYNAMIC => 0x570000008, + Type::UNKNOWN(value) => value, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u64 { + const NONE = 0x0; + const WRITE = 0x1; + const ALLOC = 0x2; + const EXECINSTR = 0x4; + const MERGE = 0x10; + const STRINGS = 0x20; + const INFO_LINK = 0x40; + const LINK_ORDER = 0x80; + const OS_NONCONFORMING = 0x100; + const GROUP = 0x200; + const TLS = 0x400; + const COMPRESSED = 0x800; + const GNU_RETAIN = 0x200000; + const EXCLUDE = 0x80000000; + const XCORE_SHF_DP_SECTION = 0x110000000; + const XCORE_SHF_CP_SECTION = 0x120000000; + const X86_64_LARGE = 0x210000000; + const HEX_GPREL = 0x310000000; + const MIPS_NODUPES = 0x401000000; + const MIPS_NAMES = 0x402000000; + const MIPS_LOCAL = 0x404000000; + const MIPS_NOSTRIP = 0x408000000; + const MIPS_GPREL = 0x410000000; + const MIPS_MERGE = 0x420000000; + const MIPS_ADDR = 0x440000000; + const MIPS_STRING = 0x480000000; + const ARM_PURECODE = 0x520000000; + const AARCH64_PURECODE = 0x620000000; + } +} + +impl Flags { + pub fn from_value(value: u64) -> Self { + Flags::from_bits_truncate(value) + } +} + +impl fmt::Debug for Section<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn generic::Section; + f.debug_struct("Section") + .field("base", &base) + .field("type", &self.get_type()) + .field("flags", &self.flags()) + .field("alignment", &self.alignment()) + .field("information", &self.information()) + .field("entry_size", &self.entry_size()) + .field("link", &self.link()) + .field("file_offset", &self.file_offset()) + .field("original_size", &self.original_size()) + .finish() + } +} + +impl fmt::Display for Section<'_> { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl FromFFI for Section<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl crate::common::AsFFI for Section<'_> { + fn as_ffi(&self) -> &ffi::ELF_Section { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> Pin<&mut ffi::ELF_Section> { + self.ptr.pin_mut() + } +} + +impl generic::Section for Section<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSection + as *mut ffi::AbstractSection) + .as_mut() + .unwrap() + }) + } + } +} + +declare_iterator!( + Sections, + Section<'a>, + ffi::ELF_Section, + ffi::ELF_Binary, + ffi::ELF_Binary_it_sections +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/segment.rs b/vendor/lief/api/rust/crates/lief/src/elf/segment.rs new file mode 100644 index 0000000..45b0ab0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/segment.rs @@ -0,0 +1,334 @@ +use bitflags::bitflags; +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::{declare_iterator, to_slice}; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Type { + /// Unused segment + PT_NULL, + /// Loadable segment + LOAD, + /// Dynamic linking information. + DYNAMIC, + /// Interpreter pathname. + INTERP, + /// Auxiliary information. + NOTE, + /// Reserved + SHLIB, + /// The program header table itself. + PHDR, + /// The thread-local storage template. + TLS, + GNU_EH_FRAME, + /// Indicates stack executability + GNU_STACK, + /// GNU property + GNU_PROPERTY, + /// Read-only after relocation. + GNU_RELRO, + PAX_FLAGS, + /// Platform architecture compatibility info + ARM_ARCHEXT, + ARM_EXIDX, + ARM_UNWIND, + AARCH64_MEMTAG_MTE, + /// Register usage information + MIPS_REGINFO, + /// Runtime procedure table. + MIPS_RTPROC, + /// Options segment. + MIPS_OPTIONS, + /// Abiflags segment. + MIPS_ABIFLAGS, + RISCV_ATTRIBUTES, + IA_64_EXT, + IA_64_UNWIND, + HP_TLS, + HP_CORE_NONE, + HP_CORE_VERSION, + HP_CORE_KERNEL, + HP_CORE_COMM, + HP_CORE_PROC, + HP_CORE_LOADABLE, + HP_CORE_STACK, + HP_CORE_SHM, + HP_CORE_MMF, + HP_PARALLEL, + HP_FASTBIND, + HP_OPT_ANNOT, + HP_HSL_ANNOT, + HP_STACK, + HP_CORE_UTSNAME, + UNKNOWN(u64), +} + +impl From for Type { + fn from(value: u64) -> Self { + match value { + 0x00000000 => Type::PT_NULL, + 0x00000001 => Type::LOAD, + 0x00000002 => Type::DYNAMIC, + 0x00000003 => Type::INTERP, + 0x00000004 => Type::NOTE, + 0x00000005 => Type::SHLIB, + 0x00000006 => Type::PHDR, + 0x00000007 => Type::TLS, + 0x6474e550 => Type::GNU_EH_FRAME, + 0x6474e551 => Type::GNU_STACK, + 0x6474e553 => Type::GNU_PROPERTY, + 0x6474e552 => Type::GNU_RELRO, + 0x65041580 => Type::PAX_FLAGS, + 0x270000000 => Type::ARM_ARCHEXT, + 0x270000001 => Type::ARM_EXIDX, + 0x470000002 => Type::AARCH64_MEMTAG_MTE, + 0x670000000 => Type::MIPS_REGINFO, + 0x670000001 => Type::MIPS_RTPROC, + 0x670000002 => Type::MIPS_OPTIONS, + 0x670000003 => Type::MIPS_ABIFLAGS, + 0x870000003 => Type::RISCV_ATTRIBUTES, + 0xa70000000 => Type::IA_64_EXT, + 0xa70000001 => Type::IA_64_UNWIND, + 0x20000060000000 => Type::HP_TLS, + 0x20000060000001 => Type::HP_CORE_NONE, + 0x20000060000002 => Type::HP_CORE_VERSION, + 0x20000060000003 => Type::HP_CORE_KERNEL, + 0x20000060000004 => Type::HP_CORE_COMM, + 0x20000060000005 => Type::HP_CORE_PROC, + 0x20000060000006 => Type::HP_CORE_LOADABLE, + 0x20000060000007 => Type::HP_CORE_STACK, + 0x20000060000008 => Type::HP_CORE_SHM, + 0x20000060000009 => Type::HP_CORE_MMF, + 0x20000060000010 => Type::HP_PARALLEL, + 0x20000060000011 => Type::HP_FASTBIND, + 0x20000060000012 => Type::HP_OPT_ANNOT, + 0x20000060000013 => Type::HP_HSL_ANNOT, + 0x20000060000014 => Type::HP_STACK, + 0x20000060000015 => Type::HP_CORE_UTSNAME, + _ => Type::UNKNOWN(value), + } + } +} +impl From for u64 { + fn from(value: Type) -> u64 { + match value { + Type::PT_NULL => 0x00000000, + Type::LOAD => 0x00000001, + Type::DYNAMIC => 0x00000002, + Type::INTERP => 0x00000003, + Type::NOTE => 0x00000004, + Type::SHLIB => 0x00000005, + Type::PHDR => 0x00000006, + Type::TLS => 0x00000007, + Type::GNU_EH_FRAME => 0x6474e550, + Type::GNU_STACK => 0x6474e551, + Type::GNU_PROPERTY => 0x6474e553, + Type::GNU_RELRO => 0x6474e552, + Type::PAX_FLAGS => 0x65041580, + Type::ARM_ARCHEXT => 0x270000000, + Type::ARM_EXIDX => 0x270000001, + Type::ARM_UNWIND => 0x270000001, + Type::AARCH64_MEMTAG_MTE => 0x470000002, + Type::MIPS_REGINFO => 0x670000000, + Type::MIPS_RTPROC => 0x670000001, + Type::MIPS_OPTIONS => 0x670000002, + Type::MIPS_ABIFLAGS => 0x670000003, + Type::RISCV_ATTRIBUTES => 0x870000003, + Type::IA_64_EXT => 0xa70000000, + Type::IA_64_UNWIND => 0xa70000001, + Type::HP_TLS => 0x20000060000000, + Type::HP_CORE_NONE => 0x20000060000001, + Type::HP_CORE_VERSION => 0x20000060000002, + Type::HP_CORE_KERNEL => 0x20000060000003, + Type::HP_CORE_COMM => 0x20000060000004, + Type::HP_CORE_PROC => 0x20000060000005, + Type::HP_CORE_LOADABLE => 0x20000060000006, + Type::HP_CORE_STACK => 0x20000060000007, + Type::HP_CORE_SHM => 0x20000060000008, + Type::HP_CORE_MMF => 0x20000060000009, + Type::HP_PARALLEL => 0x20000060000010, + Type::HP_FASTBIND => 0x20000060000011, + Type::HP_OPT_ANNOT => 0x20000060000012, + Type::HP_HSL_ANNOT => 0x20000060000013, + Type::HP_STACK => 0x20000060000014, + Type::HP_CORE_UTSNAME => 0x20000060000015, + Type::UNKNOWN(value) => value, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u32 { + const NONE = 0x0; + const X = 0x1; + const W = 0x2; + const R = 0x4; + } +} + +impl Flags { + pub fn from_value(value: u32) -> Self { + Flags::from_bits_truncate(value) + } + + pub fn to_value(&self) -> u32 { + self.bits() + } +} + +/// Structure which represents an ELF segment +pub struct Segment<'a> { + pub(super) ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl fmt::Debug for Segment<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Segment") + .field("p_type", &self.p_type()) + .field("flags", &self.flags()) + .field("file_offset", &self.file_offset()) + .field("virtual_address", &self.virtual_address()) + .field("physical_address", &self.physical_address()) + .field("physical_size", &self.physical_size()) + .field("virtual_size", &self.virtual_size()) + .field("alignment", &self.alignment()) + .finish() + } +} + +impl FromFFI for Segment<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Segment { + ptr, + _owner: PhantomData, + } + } +} + +impl Segment<'_> { + /// Create a new segment + pub fn new() -> Segment<'static> { + Segment::from_ffi(lief_ffi::ELF_Segment::create()) + } + + /// Content of the segment as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// The segment's type (LOAD, DYNAMIC, ...) + pub fn p_type(&self) -> Type { + Type::from(self.ptr.stype()) + } + + /// The flag permissions associated with this segment + pub fn flags(&self) -> u32 { + self.ptr.flags() + } + + /// The file offset of the data associated with this segment + pub fn file_offset(&self) -> u64 { + self.ptr.file_offset() + } + + /// The virtual address of the segment. + pub fn virtual_address(&self) -> u64 { + self.ptr.virtual_address() + } + /// The physical address of the segment. + /// This value is not really relevant on systems like Linux or Android. + /// On the other hand, Qualcomm trustlets might use this value. + /// + /// Usually this value matches [`Segment::virtual_address`] + pub fn physical_address(&self) -> u64 { + self.ptr.physical_address() + } + + /// The **file** size of the data associated with this segment + pub fn physical_size(&self) -> u64 { + self.ptr.physical_size() + } + + /// The in-memory size of this segment. + /// Usually, if the `.bss` segment is wrapped by this segment + /// then, virtual_size is larger than physical_size + pub fn virtual_size(&self) -> u64 { + self.ptr.virtual_size() + } + + /// The offset alignment of the segment + pub fn alignment(&self) -> u64 { + self.ptr.alignment() + } + + pub fn set_type(&mut self, ty: Type) { + self.ptr.pin_mut().set_type(ty.into()); + } + + pub fn set_flags(&mut self, flags: Flags) { + self.ptr.pin_mut().set_flags(flags.to_value()) + } + + pub fn set_file_offset(&mut self, offset: u64) { + self.ptr.pin_mut().set_file_offset(offset); + } + + pub fn set_virtual_address(&mut self, va: u64) { + self.ptr.pin_mut().set_virtual_address(va); + } + + pub fn set_physical_address(&mut self, addr: u64) { + self.ptr.pin_mut().set_physical_address(addr); + } + + pub fn set_virtual_size(&mut self, vsize: u64) { + self.ptr.pin_mut().set_virtual_size(vsize); + } + + pub fn set_alignment(&mut self, alignment: u64) { + self.ptr.pin_mut().set_alignment(alignment); + } + + pub fn set_content(&mut self, content: &[u8]) { + unsafe { + self.ptr + .pin_mut() + .set_content(content.as_ptr(), content.len().try_into().unwrap()); + } + } + + /// Clear the content of this segment + pub fn clear(&mut self) { + self.ptr.pin_mut().clear() + } + + /// Fill the content of this segment with the value provided in parameter + pub fn fill(&mut self, value: u8) { + // Note(romain): This is on purpose to fix issues with AArch64 architecture + #[allow(clippy::useless_conversion)] + { + self.ptr.pin_mut().fill((value as i8).try_into().unwrap()) + } + } +} + +impl fmt::Display for Segment<'_> { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_iterator!( + Segments, + Segment<'a>, + ffi::ELF_Segment, + ffi::ELF_Binary, + ffi::ELF_Binary_it_segments +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/symbol.rs b/vendor/lief/api/rust/crates/lief/src/elf/symbol.rs new file mode 100644 index 0000000..69dcfcb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/symbol.rs @@ -0,0 +1,245 @@ +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; +use std::pin::Pin; + +use super::SymbolVersion; +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::elf::Section; +use crate::generic; + +/// Structure which represents an ELF symbol +pub struct Symbol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Binding { + /// Local symbol + LOCAL, + /// Global symbol + GLOBAL, + /// Weak symbol + WEAK, + /// Unique symbol + GNU_UNIQUE, + UNKNOWN(u32), +} + +impl Binding { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000000 => Binding::LOCAL, + 0x00000001 => Binding::GLOBAL, + 0x00000002 => Binding::WEAK, + 0x0000000a => Binding::GNU_UNIQUE, + _ => Binding::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Type of the symbol. This enum matches the `STT_xxx` values of the ELF +/// specs +pub enum Type { + /// Symbol's type is not specified + NOTYPE, + /// Symbol is a data object (variable, array, etc.) + OBJECT, + /// Symbol is executable code (function, etc.) + FUNC, + /// Symbol refers to a section + SECTION, + /// Local, absolute symbol that refers to a file + FILE, + /// An uninitialized common block + COMMON, + /// Thread local data object + TLS, + /// GNU indirect function + GNU_IFUNC, + UNKNOWN(u32), +} + +impl Type { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000000 => Type::NOTYPE, + 0x00000001 => Type::OBJECT, + 0x00000002 => Type::FUNC, + 0x00000003 => Type::SECTION, + 0x00000004 => Type::FILE, + 0x00000005 => Type::COMMON, + 0x00000006 => Type::TLS, + 0x0000000a => Type::GNU_IFUNC, + _ => Type::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Visibility of the symbol. This enum matches the `STV_xxx` values of the +/// official ELF specs +pub enum Visibility { + /// Visibility is specified by binding type + DEFAULT, + /// Defined by processor supplements + INTERNAL, + /// Not visible to other components + HIDDEN, + /// Visible in other components but not preemptable + PROTECTED, + UNKNOWN(u32), +} + +impl Visibility { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000000 => Visibility::DEFAULT, + 0x00000001 => Visibility::INTERNAL, + 0x00000002 => Visibility::HIDDEN, + 0x00000003 => Visibility::PROTECTED, + _ => Visibility::UNKNOWN(value), + } + } +} + +impl Symbol<'_> { + /// The symbol's type provides a general classification for the associated entity + pub fn get_type(&self) -> Type { + Type::from_value(self.ptr.get_type()) + } + + /// The symbol's binding determines the linkage visibility and behavior + pub fn binding(&self) -> Binding { + Binding::from_value(self.ptr.binding()) + } + + /// This member specifies the symbol's type and binding attributes. + pub fn information(&self) -> u8 { + self.ptr.information() + } + + /// Alias for [`Symbol::visibility`] + pub fn other(&self) -> u8 { + self.ptr.other() + } + + /// ELF Section index associated with the symbol + pub fn section_idx(&self) -> u16 { + self.ptr.section_idx() + } + + /// Symbol visibility + pub fn visibility(&self) -> Visibility { + Visibility::from_value(self.ptr.visibility()) + } + + /// Section associated with the symbol (if any) + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } + + /// Return the SymbolVersion associated with this symbol (if any) + pub fn symbol_version(&self) -> Option> { + into_optional(self.ptr.symbol_version()) + } + + /// Try to demangle the symbol or return an empty string if it is not possible + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } +} + +impl fmt::Debug for Symbol<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("Symbol") + .field("base", &base) + .field("type", &self.get_type()) + .field("binding", &self.binding()) + .field("information", &self.information()) + .field("other", &self.other()) + .field("section_idx", &self.section_idx()) + .field("visibility", &self.visibility()) + .field("section", &self.section()) + .field("symbol_version", &self.symbol_version()) + .finish() + } +} + +impl FromFFI for Symbol<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl crate::common::AsFFI for Symbol<'_> { + fn as_ffi(&self) -> &ffi::ELF_Symbol { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> Pin<&mut ffi::ELF_Symbol> { + self.ptr.pin_mut() + } +} + +impl generic::Symbol for Symbol<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +impl fmt::Display for Symbol<'_> { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_iterator!( + DynamicSymbols, + Symbol<'a>, + ffi::ELF_Symbol, + ffi::ELF_Binary, + ffi::ELF_Binary_it_dynamic_symbols +); +declare_iterator!( + ExportedSymbols, + Symbol<'a>, + ffi::ELF_Symbol, + ffi::ELF_Binary, + ffi::ELF_Binary_it_exported_symbols +); +declare_iterator!( + ImportedSymbols, + Symbol<'a>, + ffi::ELF_Symbol, + ffi::ELF_Binary, + ffi::ELF_Binary_it_imported_symbols +); +declare_iterator!( + SymtabSymbols, + Symbol<'a>, + ffi::ELF_Symbol, + ffi::ELF_Binary, + ffi::ELF_Binary_it_symtab_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/elf/symbol_versioning.rs b/vendor/lief/api/rust/crates/lief/src/elf/symbol_versioning.rs new file mode 100644 index 0000000..ebfe007 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/elf/symbol_versioning.rs @@ -0,0 +1,293 @@ +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; + +/// Structure which represents an entry defined in the `DT_VERSYM` +/// dynamic entry +pub struct SymbolVersion<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::ELF_Binary>, +} + +impl SymbolVersion<'_> { + /// Value associated with the symbol + /// + /// If the given [`SymbolVersion`] doesn't have [`SymbolVersion::symbol_version_auxiliary`]: + /// + /// * `0` means **Local** + /// * `1` means **Global** + pub fn value(&self) -> u16 { + self.ptr.value() + } + + /// SymbolVersionAux associated with the current Version if any. + pub fn symbol_version_auxiliary(&self) -> Option> { + into_optional(self.ptr.symbol_version_auxiliary()) + } + + /// Drop the versioning requirement and replace the value (local/global) + pub fn drop_version(&mut self, value: u16) { + self.ptr.pin_mut().drop_version(value) + } + + /// Redefine this version as local by dropping its auxiliary version + /// + /// See: [`SymbolVersion::as_global`], [`SymbolVersion::drop_version`] + pub fn as_local(&mut self) { + self.ptr.pin_mut().as_local() + } + + /// Redefine this version as global by dropping its auxiliary version + /// + /// See: [`SymbolVersion::as_local`], [`SymbolVersion::drop_version`] + pub fn as_global(&mut self) { + self.ptr.pin_mut().as_global() + } +} + +impl fmt::Debug for SymbolVersion<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("SymbolVersion") + .field("value", &self.value()) + .field("symbol_version_auxiliary", &self.symbol_version_auxiliary()) + .finish() + } +} + +impl FromFFI for SymbolVersion<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +pub struct SymbolVersionAux<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl SymbolVersionAux<'_> { + pub fn name(&self) -> String { + self.ptr.name().to_string() + } +} + +impl fmt::Debug for SymbolVersionAux<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("SymbolVersionAux") + .field("name", &self.name()) + .finish() + } +} + +impl FromFFI for SymbolVersionAux<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +pub struct SymbolVersionAuxRequirement<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl SymbolVersionAuxRequirement<'_> { + /// Hash value of the dependency name (use ELF hashing function) + pub fn hash(&self) -> u32 { + self.ptr.hash() + } + /// Bitmask of flags + pub fn flags(&self) -> u16 { + self.ptr.flags() + } + + /// It returns the unique version index for the file which is used in the + /// version symbol table. If the highest bit (bit 15) is set this + /// is a hidden symbol which cannot be referenced from outside the + /// object. + pub fn other(&self) -> u16 { + self.ptr.other() + } + + /// Symbol's aux name (e.g. `GLIBC_2.2.5`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } +} + +impl fmt::Debug for SymbolVersionAuxRequirement<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("SymbolVersionAuxRequirement") + .field("hash", &self.hash()) + .field("flags", &self.flags()) + .field("other", &self.other()) + .finish() + } +} + +impl FromFFI for SymbolVersionAuxRequirement<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure which represents an entry defined in `DT_VERDEF` or `.gnu.version_d` +pub struct SymbolVersionDefinition<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl SymbolVersionDefinition<'_> { + /// Version revision + /// + /// This field should always have the value `1`. It will be changed + /// if the versioning implementation has to be changed in an incompatible way. + pub fn version(&self) -> u16 { + self.ptr.version() + } + + /// Version information + pub fn flags(&self) -> u16 { + self.ptr.flags() + } + + /// Version index + /// Numeric value used as an index in the [`SymbolVersion`] table + pub fn ndx(&self) -> u16 { + self.ptr.ndx() + } + + /// Hash value of the symbol's name (using ELF hash function) + pub fn hash(&self) -> u32 { + self.ptr.hash() + } + + /// Iterator over the [`SymbolVersionAux`] associated with this entry + pub fn auxiliary_symbols(&self) -> DefAuxiliarySymbols<'_> { + DefAuxiliarySymbols::new(self.ptr.sym_aux()) + } +} + +impl fmt::Debug for SymbolVersionDefinition<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("SymbolVersionDefinition") + .field("version", &self.version()) + .field("flags", &self.flags()) + .field("ndx", &self.ndx()) + .field("hash", &self.hash()) + .finish() + } +} + +impl FromFFI for SymbolVersionDefinition<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure which represents an entry in the `DT_VERNEED` or `.gnu.version_r` table +pub struct SymbolVersionRequirement<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl SymbolVersionRequirement<'_> { + /// Version revision + /// + /// This field should always have the value `1`. It will be changed + /// if the versioning implementation has to be changed in an incompatible way. + pub fn version(&self) -> u16 { + self.ptr.version() + } + + /// Number of auxiliary entries + pub fn cnt(&self) -> u32 { + self.ptr.cnt() + } + + /// Return the library name associated with this requirement (e.g. `libc.so.6`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Auxiliary entries as an iterator over [`SymbolVersionAuxRequirement`] + pub fn auxiliary_symbols(&self) -> AuxiliarySymbols<'_> { + AuxiliarySymbols::new(self.ptr.auxiliary_symbols()) + } + + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } + + pub fn set_version(&mut self, version: u16) { + self.ptr.pin_mut().set_version(version); + } + + /// Try to find the [`SymbolVersionAuxRequirement`] with the given name (e.g. `GLIBC_2.27`) + pub fn find_aux(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional(self.ptr.find_aux(&__cxx_s)) + } + + /// Try to remove the auxiliary requirement symbol with the given name. + /// The function returns true if the operation succeed, false otherwise. + /// + /// **warning**: + /// + /// This function invalidates all the references of + /// [`SymbolVersionAuxRequirement`]. Therefore, the user is reponsible + /// to ensure that the auxiliary requirement is no longer used in the + /// ELF binary (e.g. in [`SymbolVersion`]) + pub fn remove_aux_requirement_by_name(&mut self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().remove_aux_requirement_by_name(&__cxx_s) + } +} + +impl fmt::Debug for SymbolVersionRequirement<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("SymbolVersionRequirement") + .field("verison", &self.version()) + .field("cnt", &self.cnt()) + .field("name", &self.name()) + .finish() + } +} + +impl FromFFI for SymbolVersionRequirement<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + AuxiliarySymbols, + SymbolVersionAuxRequirement<'a>, + ffi::ELF_SymbolVersionAuxRequirement, + ffi::ELF_SymbolVersionRequirement, + ffi::ELF_SymbolVersionRequirement_it_auxiliary_symbols +); +declare_iterator!( + DefAuxiliarySymbols, + SymbolVersionAux<'a>, + ffi::ELF_SymbolVersionAux, + ffi::ELF_SymbolVersionDefinition, + ffi::ELF_SymbolVersionDefinition_it_auxiliary_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/error.rs b/vendor/lief/api/rust/crates/lief/src/error.rs new file mode 100644 index 0000000..6535144 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/error.rs @@ -0,0 +1,52 @@ +use std::fmt; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum Error { + ReadError, + NotFound, + NotImplemented, + NotSupported, + Corrupted, + ConversionError, + ReadOutOfBound, + ASN1BadTag, + FileError, + FileFormatError, + ParsingError, + BuildError, + DataTooLarge, + RequireExtendedVersion, + Inconsistent, + RuntimeError, + Unknown(u32), +} + +impl From for Error { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Error::ReadError, + 0x00000002 => Error::NotFound, + 0x00000003 => Error::NotImplemented, + 0x00000004 => Error::NotSupported, + 0x00000005 => Error::Corrupted, + 0x00000006 => Error::ConversionError, + 0x00000007 => Error::ReadOutOfBound, + 0x00000008 => Error::ASN1BadTag, + 0x00000009 => Error::FileError, + 0x0000000a => Error::FileFormatError, + 0x0000000b => Error::ParsingError, + 0x0000000c => Error::BuildError, + 0x0000000d => Error::DataTooLarge, + 0x0000000e => Error::RequireExtendedVersion, + 0x0000000f => Error::Inconsistent, + 0x00000010 => Error::RuntimeError, + _ => Error::Unknown(value), + } + } +} + +impl fmt::Display for Error { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "LIEF Error Occurred!") + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/generic.rs b/vendor/lief/api/rust/crates/lief/src/generic.rs new file mode 100644 index 0000000..77c8e86 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/generic.rs @@ -0,0 +1,498 @@ +use crate::assembly::{AssemblerConfig, Instructions}; +use crate::common::{FromFFI, into_optional}; +use crate::{declare_fwd_iterator, declare_lazy_iterator, to_slice}; +use bitflags::bitflags; +use lief_ffi as ffi; + +use std::pin::Pin; + +/// Trait shared by all the symbols in executable formats +pub trait Symbol { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::AbstractSymbol; + + #[doc(hidden)] + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol>; + + /// Symbol's name + fn name(&self) -> String { + self.as_generic().name().to_string() + } + /// Symbol's value whose interpretation depends on the symbol's kind. + /// Usually this is the address of the symbol though. + fn value(&self) -> u64 { + self.as_generic().value() + } + /// Size of the symbol (can be 0) + fn size(&self) -> u64 { + self.as_generic().size() + } + + fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.as_pin_mut_generic().set_name(&__cxx_s); + } + + fn set_value(&mut self, value: u64) { + self.as_pin_mut_generic().set_value(value); + } + + fn set_size(&mut self, size: u64) { + self.as_pin_mut_generic().set_size(size); + } +} + +impl std::fmt::Debug for &dyn Symbol { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Symbol") + .field("name", &self.name()) + .field("value", &self.value()) + .field("size", &self.size()) + .finish() + } +} + +/// Trait shared by all the sections in executable formats +pub trait Section { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::AbstractSection; + + #[doc(hidden)] + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection>; + + /// Name of the section + fn name(&self) -> String { + self.as_generic().name().to_string() + } + + /// Size of the section **in the file** + fn size(&self) -> u64 { + self.as_generic().size() + } + + /// Offset of the section **in the file** + fn offset(&self) -> u64 { + self.as_generic().offset() + } + + /// Address of the section **in memory** + fn virtual_address(&self) -> u64 { + self.as_generic().virtual_address() + } + + /// Content of the section + fn content(&self) -> &[u8] { + to_slice!(self.as_generic().content()); + } + + /// Change the section's name + fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.as_generic_mut().set_name(&__cxx_s); + } + + /// Change section content + fn set_content(&mut self, data: &[u8]) { + unsafe { + self.as_generic_mut().set_content(data.as_ptr(), data.len()); + } + } + + /// Change section size + fn set_size(&mut self, size: u64) { + self.as_generic_mut().set_size(size); + } +} + +impl std::fmt::Debug for &dyn Section { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Section") + .field("name", &self.name()) + .field("size", &self.size()) + .field("offset", &self.offset()) + .field("virtual_address", &self.virtual_address()) + .finish() + } +} + +pub trait Relocation { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::AbstractRelocation; + + /// Address where the relocation should take place + fn address(&self) -> u64 { + self.as_generic().address() + } + + /// Size of the relocation + fn size(&self) -> u64 { + self.as_generic().size() + } +} + +impl std::fmt::Debug for &dyn Relocation { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Relocation") + .field("address", &self.address()) + .field("size", &self.size()) + .finish() + } +} + +/// Generic interface representing a binary executable. +/// +/// This trait provides a unified interface across multiple binary formats +/// such as ELF, PE, Mach-O, and others. It enables users to access binary +/// components like headers, sections, symbols, relocations, +/// and functions in a format-agnostic way. +pub trait Binary { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::AbstractBinary; + + #[doc(hidden)] + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractBinary>; + + /// Binary's entrypoint + fn entrypoint(&self) -> u64 { + self.as_generic().entrypoint() + } + + /// Default base address where the binary should be mapped + fn imagebase(&self) -> u64 { + self.as_generic().imagebase() + } + + /// Size of the binary when mapped in memory + fn virtual_size(&self) -> u64 { + self.as_generic().virtual_size() + } + + /// Whether the current binary is **an executable** and **position independent** + fn is_pie(&self) -> bool { + self.as_generic().is_pie() + } + + /// Whether the binary defines a non-executable stack + fn has_nx(&self) -> bool { + self.as_generic().has_nx() + } + + /// Original file size of the binary + fn original_size(&self) -> u64 { + self.as_generic().original_size() + } + + /// Return the debug info if present. It can be either a + /// [`crate::pdb::DebugInfo`] or [`crate::dwarf::DebugInfo`]. + /// + /// For ELF and Mach-O binaries, it returns the given DebugInfo object **only** + /// if the binary embeds the DWARF debug info in the binary itself. + /// + /// For PE file, this function tries to find the **external** PDB using + /// the [`crate::pe::debug::CodeViewPDB::filename`] output (if present). One can also + /// use [`crate::pdb::load`] or [`crate::pdb::DebugInfo::from`] to get PDB debug + /// info. + /// + ///
+ /// This function requires LIEF's extended version otherwise it always return `None` + ///
+ fn debug_info(&self) -> Option> { + into_optional(self.as_generic().debug_info()) + } + + /// Disassemble code starting at the given virtual address and with the given + /// size. + /// + /// ``` + /// let insts = binary.disassemble(0xacde, 100); + /// for inst in insts { + /// println!("{}", inst.to_string()); + /// } + /// ``` + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + fn disassemble(&self, address: u64, size: u64) -> InstructionsIt<'_> { + InstructionsIt::new(self.as_generic().disassemble(address, size)) + } + + /// Disassemble code for the given symbol name + /// + /// ``` + /// let insts = binary.disassemble_symbol("__libc_start_main"); + /// for inst in insts { + /// println!("{}", inst.to_string()); + /// } + /// ``` + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + fn disassemble_symbol(&self, name: &str) -> InstructionsIt<'_> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + InstructionsIt::new(self.as_generic().disassemble_function(&__cxx_s)) + } + + /// Disassemble code at the given virtual address + /// + /// ``` + /// let insts = binary.disassemble_address(0xacde); + /// for inst in insts { + /// println!("{}", inst.to_string()); + /// } + /// ``` + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + fn disassemble_address(&self, address: u64) -> InstructionsIt<'_> { + InstructionsIt::new(self.as_generic().disassemble_address(address)) + } + + /// Disassemble code provided by the given slice at the specified `address` parameter. + /// + /// See also [`crate::assembly::Instruction`] and [`crate::assembly::Instructions`] + fn disassemble_slice(&self, slice: &[u8], address: u64) -> InstructionsIt<'_> { + unsafe { + InstructionsIt::new(self.as_generic().disassemble_buffer( + slice.as_ptr(), + slice.len().try_into().unwrap(), + address, + )) + } + } + + /// Assemble **and patch** the provided assembly code at the specified address. + /// + /// The generated assembly is returned by the function + /// + /// ``` + /// let mut bin = get_binary(); + /// + /// let Vec bytes = bin.assemble(0x12000440, r#" + /// xor rax, rbx; + /// mov rcx, rax; + /// "#); + /// ``` + fn assemble(&mut self, address: u64, asm: &str) -> Vec { + cxx::let_cxx_string!(__cxx_s = asm); + Vec::from( + self.as_pin_mut_generic() + .assemble(address, &__cxx_s) + .as_slice(), + ) + } + + /// Same as [`Binary::assemble`] but this function takes an extra [`AssemblerConfig`] that + /// is used to configure the assembly engine: dialect, symbols definitions. + fn assemble_with_config( + &mut self, + address: u64, + asm: &str, + config: &AssemblerConfig, + ) -> Vec { + let ffi_config = config.into_ffi(); + cxx::let_cxx_string!(__cxx_s = asm); + Vec::from( + self.as_pin_mut_generic() + .assemble_with_config(address, &__cxx_s, ffi_config.as_ref()) + .as_slice(), + ) + } + + /// Default memory page size according to the architecture and the format of the + /// current binary + fn page_size(&self) -> u64 { + self.as_generic().page_size() + } + + /// Patch the content at virtual address address with patch_value. + fn patch_address(&mut self, address: u64, patch_value: &[u8]) { + unsafe { + self.as_pin_mut_generic().patch_address_bytes( + address, + patch_value.as_ptr(), + patch_value.len().try_into().unwrap(), + ); + } + } + + /// Patch the address with the given value. + /// You must specify a valid size, MAX: `size_of::()` + fn patch_address_with_value(&mut self, address: u64, patch_value: u64, size: usize) { + self.as_pin_mut_generic().patch_address_value( + address, + patch_value, + size.try_into().unwrap(), + ); + } + + /// Convert the given offset into a virtual address. + /// + /// If the `slide` parameter is provided (non-zero), it will be used as the base address + /// instead of the binary's imagebase. + fn offset_to_virtual_address(&self, offset: u64, slide: u64) -> Result { + let mut err: u32 = 0; + let va = self + .as_generic() + .offset_to_virtual_address(offset, slide, Pin::new(&mut err)); + if err > 0 { + return Err(crate::Error::from(err)); + } + Ok(va) + } + + /// Load and associate an external debug file (e.g., DWARF or PDB) with this binary. + /// + /// This method attempts to load the debug information from the file located at the given path, + /// and binds it to the current binary instance. If successful, it returns the + /// loaded [`crate::DebugInfo`] object. + /// + ///
+ /// It is the caller's responsibility to ensure that the debug file is + /// compatible with the binary. Incorrect associations may lead to + /// inconsistent or invalid results. + ///
+ /// + ///
+ /// This function does not verify that the debug file matches the binary's unique + /// identifier (e.g., build ID, GUID). + ///
+ fn load_debug_info(&mut self, path: &std::path::Path) -> Option> { + cxx::let_cxx_string!(__cxx_s = path.to_str().unwrap()); + into_optional(self.as_pin_mut_generic().load_debug_info(&__cxx_s)) + } +} + +/// This class provides a generic interface for accessing debug information +/// from different formats such as DWARF and PDB. +/// +/// Users can use this interface to access high-level debug features like +/// resolving function addresses. +/// +/// See: [`crate::pdb::DebugInfo`], [`crate::dwarf::DebugInfo`] +pub trait DebugInfo { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::AbstracDebugInfo; + + /// Attempt to resolve the address of the function specified by `name`. + fn find_function_address(&self, name: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = name); + let mut is_set: u32 = 0; + let value = lief_ffi::AbstracDebugInfo::find_function_address( + self.as_generic(), + &__cxx_s, + std::pin::Pin::new(&mut is_set), + ); + if is_set == 0 { None } else { Some(value) } + } +} + +bitflags! { + /// Flags used to characterize the semantics of the function + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct FunctionFlags: u32 { + const NONE = 0x0; + /// The function acts as constructor. + /// + /// Usually this flag is associated with functions + /// that are located in the `.init_array`, `__mod_init_func` or `.tls` sections + const CONSTRUCTOR = 0x1; + + /// The function acts as a destructor. + /// + /// Usually this flag is associated with functions + /// that are located in the `.fini_array` or `__mod_term_func` sections + const DESTRUCTOR = 0x2; + + /// The function is associated with Debug information + const DEBUG_INFO = 0x4; + + /// The function is exported by the binary and the [`Function::address`] + /// returns its virtual address in the binary + const EXPORTED = 0x8; + + /// The function is **imported** by the binary and the [`Function::address`] + /// should return 0 + const IMPORTED = 0x10; + } +} + +impl From for FunctionFlags { + fn from(value: u32) -> Self { + FunctionFlags::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: FunctionFlags) -> Self { + value.bits() + } +} + +impl std::fmt::Display for FunctionFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +/// Structure that represents a binary's function +pub struct Function { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Function { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Symbol for Function { + fn as_generic(&self) -> &lief_ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +impl Function { + /// Flags characterizing the semantics of the function + pub fn flags(&self) -> FunctionFlags { + FunctionFlags::from(self.ptr.flags()) + } + + /// Address of the function (if not imported) + pub fn address(&self) -> u64 { + self.ptr.address() + } +} + +impl std::fmt::Debug for Function { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Function") + .field("name", &self.name()) + .field("address", &self.address()) + .field("flags", &self.flags()) + .finish() + } +} + +declare_fwd_iterator!( + Functions, + Function, + ffi::AbstractFunction, + ffi::AbstractBinary, + ffi::AbstractBinary_it_functions +); + +declare_lazy_iterator!( + InstructionsIt, + Instructions, + ffi::asm_Instruction, + ffi::AbstractBinary, + ffi::AbstractBinary_it_instructions +); diff --git a/vendor/lief/api/rust/crates/lief/src/lib.rs b/vendor/lief/api/rust/crates/lief/src/lib.rs new file mode 100644 index 0000000..53024cb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/lib.rs @@ -0,0 +1,211 @@ +//! # LIEF +//! +//! ![LIEF Design](https://raw.githubusercontent.com/lief-project/LIEF/main/.github/images/architecture.png) +//! +//! This package provides Rust bindings for [LIEF](https://lief.re). It exposes most of the +//! LIEF API to **read** these formats: +//! - ELF +//! - PE +//! - Mach-O +//! +//! The bindings require at least Rust version **1.85.0** with the 2024 edition and support: +//! - Windows x86-64 (support `/MT` and `/MD` linking) +//! - Windows arm64 (support `/MT` and `/MD` linking) +//! - Linux x86-64 (+gnu/musl): Ubuntu 21.10+, Debian 12+, Fedora 35+, CentOS/RHEL 9+ +//! - Linux i686 (+gnu/musl): Ubuntu 19.10+, Debian 10+ +//! - Linux aarch64 (+gnu/musl): Ubuntu 21.10+, Debian 12+ +//! - Android: API 30+ +//! - macOS (`x86-64` and `aarch64` with at least OSX Big Sur: 11.0) +//! - iOS (`aarch64`): 12+ +//! +//! ## Getting Started +//! +//! ```toml +//! [package] +//! name = "my-awesome-project" +//! version = "0.0.1" +//! edition = "2024" +//! +//! [dependencies] +//! # For nightly +//! lief = { git = "https://github.com/lief-project/LIEF", branch = "main" } +//! # For releases +//! lief = 2.0.0 +//! ``` +//! +//! ```rust +//! fn main() { +//! let path = std::env::args().last().unwrap(); +//! let mut file = std::fs::File::open(path).expect("Can't open the file"); +//! match lief::Binary::from(&mut file) { +//! Some(lief::Binary::ELF(elf)) => { +//! // Process ELF file +//! }, +//! Some(lief::Binary::PE(pe)) => { +//! // Process PE file +//! }, +//! Some(lief::Binary::MachO(macho)) => { +//! // Process Mach-O file (including FatMachO) +//! }, +//! Some(lief::Binary::COFF(coff)) => { +//! // Process coff file +//! }, +//! None => { +//! // Parsing error +//! } +//! } +//! return; +//! } +//! ``` +//! +//! Note that the [`generic`] module implements the different traits shared by different structure +//! of executable formats (symbols, relocations, ...) +//! +//! ## Additional Information +//! +//! For more details about the install procedure and the configuration, please check: +//! + +#![doc(html_no_source)] + +pub mod elf; + +/// Executable formats generic traits (LIEF's abstract layer) +pub mod generic; + +pub mod macho; + +pub mod pe; + +pub mod coff; + +pub mod pdb; + +pub mod dwarf; + +pub mod objc; + +pub mod dsc; + +pub mod debug_info; + +pub mod assembly; +mod range; + +/// Module for LIEF's error +pub mod error; + +pub mod logging; + +pub mod runtime; + +mod binary; +mod common; + +mod debug_location; + +mod decl_opt; + +#[doc(inline)] +pub use binary::Binary; + +#[doc(inline)] +pub use generic::{Function, Relocation}; + +#[doc(inline)] +pub use error::Error; + +#[doc(inline)] +pub use debug_info::DebugInfo; + +#[doc(inline)] +pub use range::Range; + +#[doc(inline)] +pub use debug_location::DebugLocation; + +#[doc(inline)] +pub use decl_opt::DeclOpt; + +pub struct Version { + pub major: u64, + pub minor: u64, + pub patch: u64, + pub id: u64, +} + +impl std::fmt::Display for Version { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!( + f, + "{}.{}.{}.{}", + self.major, self.minor, self.patch, self.id + ) + } +} + +/// Whether it is an extended version of LIEF +pub fn is_extended() -> bool { + lief_ffi::is_extended() +} + +/// Return details about the extended version +pub fn extended_version_info() -> String { + lief_ffi::extended_version_info().to_string() +} + +/// Return the extended version +pub fn extended_version() -> Version { + let ffi_version = lief_ffi::extended_version(); + Version { + major: ffi_version.major, + minor: ffi_version.minor, + patch: ffi_version.patch, + id: ffi_version.id, + } +} + +/// Return the current version +pub fn version() -> Version { + let ffi_version = lief_ffi::version(); + Version { + major: ffi_version.major, + minor: ffi_version.minor, + patch: ffi_version.patch, + id: ffi_version.id, + } +} + +/// Try to demangle the given input. +/// +/// This function requires the extended version of LIEF +pub fn demangle(mangled: &str) -> Result { + cxx::let_cxx_string!(__cxx_mangled = mangled); + let mut err: u32 = 0; + let value = lief_ffi::demangle(&__cxx_mangled, std::pin::Pin::new(&mut err)); + if err > 0 { + return Err(Error::from(err)); + } + Ok(value.to_string()) +} + +/// Hexdump the provided buffer. +/// +/// For instance: +/// +/// ```text +/// +---------------------------------------------------------------------+ +/// | 88 56 05 00 00 00 00 00 00 00 00 00 22 58 05 00 | .V.........."X.. | +/// | 10 71 02 00 78 55 05 00 00 00 00 00 00 00 00 00 | .q..xU.......... | +/// | 68 5c 05 00 00 70 02 00 00 00 00 00 00 00 00 00 | h\...p.......... | +/// | 00 00 00 00 00 00 00 00 00 00 00 00 | ............ | +/// +---------------------------------------------------------------------+ +/// ``` +pub fn dump(buffer: &[u8]) -> String { + unsafe { lief_ffi::dump(buffer.as_ptr(), buffer.len()).to_string() } +} + +/// Same as [`dump`] but with a limit on the number of bytes to dump +pub fn dump_with_limit(buffer: &[u8], limit: u64) -> String { + unsafe { lief_ffi::dump_with_limit(buffer.as_ptr(), buffer.len(), limit).to_string() } +} diff --git a/vendor/lief/api/rust/crates/lief/src/logging.rs b/vendor/lief/api/rust/crates/lief/src/logging.rs new file mode 100644 index 0000000..a20bb55 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/logging.rs @@ -0,0 +1,183 @@ +//! LIEF's logging API +//! +//! This module contains function to tweak or use LIEF's logging mechanisms +//! +//! +//! ``` +//! use lief::logging; +//! +//! logging::set_level(logging::Level::Debug); +//! logging::log(logging::Level::Debug, "Hi!"); +//! ``` + +use lief_ffi as ffi; + +use std::convert::{From, Into}; +use std::path::Path; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// The different levels of log +pub enum Level { + Off, + Trace, + Debug, + Info, + Warn, + Err, + Critical, + Unknown(u32), +} + +impl From for Level { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Level::Off, + 0x00000001 => Level::Trace, + 0x00000002 => Level::Debug, + 0x00000003 => Level::Info, + 0x00000004 => Level::Warn, + 0x00000005 => Level::Err, + 0x00000006 => Level::Critical, + _ => Level::Unknown(value), + } + } +} + +impl From for u32 { + fn from(value: Level) -> Self { + match value { + Level::Off => 0x00000000, + Level::Trace => 0x00000001, + Level::Debug => 0x00000002, + Level::Info => 0x00000003, + Level::Warn => 0x00000004, + Level::Err => 0x00000005, + Level::Critical => 0x00000006, + Level::Unknown(_) => 0x00000003, // Info + } + } +} + +/// Reset the current logger +pub fn reset() { + ffi::LIEF_Logging::reset() +} + +/// Prevent any log message from being printed +pub fn disable() { + ffi::LIEF_Logging::disable() +} + +/// Enable the logger +pub fn enable() { + ffi::LIEF_Logging::enable() +} + +/// Change the logging level +/// +/// ``` +/// set_level(Level::Info) +/// ``` +pub fn set_level(level: Level) { + ffi::LIEF_Logging::set_level(level.into()) +} +/// Switch to a file-based logger (instead of stderr-based) +/// +/// ``` +/// let mut tmp = env::temp_dir(); +/// tmp.push("lief_log.log"); +/// logging::set_path(dir.as_path()); +/// ``` +pub fn set_path>(path: P) { + cxx::let_cxx_string!(p = path.as_ref().to_str().expect("Can't convert into string")); + ffi::LIEF_Logging::set_path(&p); +} + +/// Log a message with the logger +pub fn log(level: Level, message: &str) { + cxx::let_cxx_string!(msg = message); + ffi::LIEF_Logging::log(level.into(), &msg); +} + +/// Return the current logging level +pub fn get_level() -> Level { + Level::from(ffi::LIEF_Logging::get_level()) +} + +/// RAII-like scoped log level. +/// +/// +/// ``` +/// use lief::logging; +/// +/// logging::set_level(logging::Level::Info); +/// +/// { +/// let _scoped = logging::Scoped::new(logging::Level::Debug); +/// // Log level is now Debug +/// } +/// // Log level is restored to Info +/// ``` +pub struct Scoped { + inner: cxx::UniquePtr, +} + +impl Scoped { + /// Create a new scoped log level. The current log level is saved and + /// replaced with the provided `level`. When this value is dropped, the + /// original level is restored. + pub fn new(level: Level) -> Self { + Self { + inner: ffi::LIEF_Logging_Scoped::create(level.into()), + } + } + + /// Change the log level within this scope + pub fn set_level(&self, level: Level) { + self.inner.set_level(level.into()) + } + + /// Reset the log level to the value it had before this scope was created + pub fn reset(&mut self) { + self.inner.pin_mut().reset() + } +} + +#[doc(hidden)] +#[macro_export] +macro_rules! __lief_log { + ($level: expr) => { + lief::logging::log($level, "") + }; + ($level: expr, $($arg:tt)*) => {{ + lief::logging::log($level, &format!($($arg)*)); + }}; +} + +#[macro_export] +macro_rules! log_dbg { + ($($args:tt)*) => { + $crate::__lief_log!(lief::logging::Level::Debug, $($args)*) + }; +} + +#[macro_export] +macro_rules! log_info { + ($($args:tt)*) => { + $crate::__lief_log!(lief::logging::Level::Info, $($args)*) + }; +} + +#[macro_export] +macro_rules! log_warn { + ($($args:tt)*) => { + $crate::__lief_log!(lief::logging::Level::Warn, $($args)*) + }; +} + +#[macro_export] +macro_rules! log_err { + ($($args:tt)*) => { + $crate::__lief_log!(lief::logging::Level::Err, $($args)*) + }; +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho.rs b/vendor/lief/api/rust/crates/lief/src/macho.rs new file mode 100644 index 0000000..fbf953f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho.rs @@ -0,0 +1,187 @@ +//! Module for the Mach-O file format support in LIEF. +//! +//! To get started, one can use [`crate::macho::parse`], [`crate::macho::FatBinary::parse`] or +//! [`crate::Binary::parse`] to instantiate a [`crate::macho::FatBinary`]. +//! +//! Even though the targeted Mach-O binary is not FAT, LIEF **always** return a [`crate::macho::FatBinary`] +//! which can wrap a single [`Binary`]. +//! +//! ``` +//! let fat = lief::macho::parse("non-fat.macho").unwrap(); +//! assert!(fat.iter().len() == 1); +//! +//! let fat = lief::macho::parse("real-fat.macho").unwrap(); +//! assert!(fat.iter().len() > 1); +//! ``` +//! +//! The [`Binary`] structure exposes the main interface to inspect or modify Mach-O binaries: +//! +//! ``` +//! fn inspect_macho(macho: &lief::macho::Binary) { +//! for cmd in macho.commands() { +//! println!("{:?}", cmd); +//! } +//! } +//! ``` +//! +pub mod binary; +pub mod binding_info; +pub mod builder; +pub mod commands; +pub mod export_info; +pub mod fat_binary; +pub mod header; +pub mod parser_config; +pub mod relocation; +pub mod section; +pub mod stub; +pub mod symbol; +pub mod thread_local_variables; + +use lief_ffi as ffi; +use std::path::Path; + +#[doc(inline)] +pub use binary::Binary; +#[doc(inline)] +pub use binding_info::BindingInfo; +#[doc(inline)] +pub use commands::Commands; +#[doc(inline)] +pub use export_info::ExportInfo; +#[doc(inline)] +pub use fat_binary::FatBinary; +#[doc(inline)] +pub use header::Header; +#[doc(inline)] +pub use relocation::Relocation; +#[doc(inline)] +pub use section::Generic; +#[doc(inline)] +pub use section::MachOSection; +#[doc(inline)] +pub use section::Section; +#[doc(inline)] +pub use stub::Stub; +#[doc(inline)] +pub use symbol::Symbol; +#[doc(inline)] +pub use thread_local_variables::ThreadLocalVariables; + +use crate::common::AsFFI; + +#[doc(inline)] +pub use parser_config::Config as ParserConfig; + +/// Parse a Mach-O file from the given file path +pub fn parse>(path: P) -> Option { + FatBinary::parse(path) +} + +/// Parse a Mach-O file from the given file path with the provided parser +/// configuration +pub fn parse_with_config>(path: P, config: &ParserConfig) -> Option { + FatBinary::parse_with_config(path, config) +} + +/// Parse a Mach-O binary from a memory dump located at `path` that was mapped +/// at the virtual address `addr` +pub fn parse_from_dump>(path: P, addr: u64) -> Option { + FatBinary::parse_from_dump(path, addr) +} + +/// Same as [`parse_from_dump`] but with a provided configuration +pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &ParserConfig, +) -> Option { + FatBinary::parse_from_dump_with_config(path, addr, config) +} + +/// Check that the layout of the given binary is correct from the loader +/// perspective +pub fn check_layout(binary: &Binary) -> Result<(), String> { + cxx::let_cxx_string!(error = ""); + unsafe { + if ffi::MachO_Utils::check_layout(binary.as_ffi(), error.as_mut().get_unchecked_mut()) { + return Ok(()); + } + } + Err(error.to_string()) +} + +/// Check that the layout of the given FAT binary is correct from the loader +/// perspective +pub fn check_fat_layout(fat: &FatBinary) -> Result<(), String> { + cxx::let_cxx_string!(error = ""); + unsafe { + if ffi::MachO_Utils::check_layout_fat(fat.as_ffi(), error.as_mut().get_unchecked_mut()) { + return Ok(()); + } + } + Err(error.to_string()) +} + +/// Check if the given file is a FAT Mach-O +pub fn is_fat>(path: P) -> bool { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap().to_string()); + ffi::MachO_Utils::is_fat(&__cxx_s) +} + +/// Check if the given file is a 64-bit Mach-O +pub fn is_64>(path: P) -> bool { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap().to_string()); + ffi::MachO_Utils::is_64(&__cxx_s) +} + +/// Mach-O magic values +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum MachOType { + /// 32-bit big-endian magic + MAGIC, + /// 32-bit little-endian magic + CIGAM, + /// 64-bit big-endian magic + MAGIC_64, + /// 64-bit little-endian magic + CIGAM_64, + /// Big-endian fat magic + MAGIC_FAT, + /// Little-endian fat magic + CIGAM_FAT, + /// Neural model magic + NEURAL_MODEL, + UNKNOWN(u32), +} + +impl From for MachOType { + fn from(value: u32) -> Self { + match value { + 0xFEEDFACE => MachOType::MAGIC, + 0xCEFAEDFE => MachOType::CIGAM, + 0xFEEDFACF => MachOType::MAGIC_64, + 0xCFFAEDFE => MachOType::CIGAM_64, + 0xCAFEBABE => MachOType::MAGIC_FAT, + 0xBEBAFECA => MachOType::CIGAM_FAT, + 0xBEEFFACE => MachOType::NEURAL_MODEL, + _ => MachOType::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: MachOType) -> u32 { + match value { + MachOType::MAGIC => 0xFEEDFACE, + MachOType::CIGAM => 0xCEFAEDFE, + MachOType::MAGIC_64 => 0xFEEDFACF, + MachOType::CIGAM_64 => 0xCFFAEDFE, + MachOType::MAGIC_FAT => 0xCAFEBABE, + MachOType::CIGAM_FAT => 0xBEBAFECA, + MachOType::NEURAL_MODEL => 0xBEEFFACE, + MachOType::UNKNOWN(v) => v, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/binary.rs b/vendor/lief/api/rust/crates/lief/src/macho/binary.rs new file mode 100644 index 0000000..550489b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/binary.rs @@ -0,0 +1,706 @@ +use num_traits::{Num, cast}; +use std::mem::size_of; +use std::path::Path; +use std::pin::Pin; + +use super::binding_info::BindingInfo; +use super::builder::Config; +use super::commands::atom_info::AtomInfo; +use super::commands::build_version::{BuildVersion, Platform}; +use super::commands::code_signature::CodeSignature; +use super::commands::code_signature_dir::CodeSignatureDir; +use super::commands::data_in_code::DataInCode; +use super::commands::dyld_chained_fixups::DyldChainedFixups; +use super::commands::dyld_environment::DyldEnvironment; +use super::commands::dyld_export_trie::DyldExportsTrie; +use super::commands::dyldinfo::DyldInfo; +use super::commands::dylib::Libraries; +use super::commands::dylinker::Dylinker; +use super::commands::dynamic_symbol_command::DynamicSymbolCommand; +use super::commands::encryption_info::EncryptionInfo; +use super::commands::function_variant_fixups::FunctionVariantFixups; +use super::commands::function_variants::FunctionVariants; +use super::commands::functionstarts::FunctionStarts; +use super::commands::lazy_load_dylib_info::LazyLoadDylibInfo; +use super::commands::linker_opt_hint::LinkerOptHint; +use super::commands::main_cmd::Main; +use super::commands::note::Note; +use super::commands::routine::Routine; +use super::commands::rpath::RPath; +use super::commands::rpath::RPaths; +use super::commands::segment::{Segment, Segments}; +use super::commands::segment_split_info::SegmentSplitInfo; +use super::commands::source_version::SourceVersion; +use super::commands::sub_client::SubClients; +use super::commands::sub_framework::SubFramework; +use super::commands::symbol_command::SymbolCommand; +use super::commands::thread_command::ThreadCommand; +use super::commands::two_level_hints::TwoLevelHints; +use super::commands::uuid::UUID; +use super::commands::version_min::VersionMin; +use super::commands::{Command, Commands, CommandsIter, Dylib, LoadCommandTypes}; +use super::export_info::ExportInfo; +use super::header::Header; +use super::relocation::Relocations; +use super::section::{Section, Sections}; +use super::stub::Stub; +use super::symbol::{ExportedSymbols, Symbol, Symbols}; +use crate::Error; +use lief_ffi as ffi; + +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::objc::Metadata; +use crate::{declare_fwd_iterator, declare_iterator, generic, to_conv_result, to_result, to_slice}; + +/// This is the main interface to read and write Mach-O binary attributes. +/// +/// Note that this structure implements the [`generic::Binary`] trait from which other generic +/// functions are exposed +pub struct Binary { + ptr: cxx::UniquePtr, +} + +impl std::fmt::Debug for Binary { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Binary").finish() + } +} + +impl FromFFI for Binary { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Binary { ptr } + } +} + +impl Binary { + /// Return the main Mach-O header + pub fn header(&self) -> Header<'_> { + Header::from_ffi(self.ptr.header()) + } + + /// Return an iterator over the different [`crate::macho::Commands`] used by the + /// Mach-O binary + pub fn commands(&self) -> CommandsIter<'_> { + CommandsIter::new(self.ptr.commands()) + } + + /// Return an iterator over the different [`crate::macho::Section`] of the binary + pub fn sections(&self) -> Sections<'_> { + Sections::new(self.ptr.sections()) + } + + /// Return an iterator over the different [`crate::macho::commands::Segment`] (`LC_SEGMENT/LC_SIGNATURE`) + /// of the binary. + pub fn segments(&self) -> Segments<'_> { + Segments::new(self.ptr.segments()) + } + + /// Return an iterator over the [`crate::macho::commands::Dylib`] used by this binary + pub fn libraries(&self) -> Libraries<'_> { + Libraries::new(self.ptr.libraries()) + } + + /// Return an iterator over the different [`crate::macho::Relocation`] of this binary + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// Return an iterator over the different [`crate::macho::commands::RPath`] of this binary + pub fn rpaths(&self) -> RPaths<'_> { + RPaths::new(self.ptr.rpaths()) + } + + /// Return an iterator over the different [`crate::macho::Symbol`] of this binary + pub fn symbols(&self) -> Symbols<'_> { + Symbols::new(self.ptr.symbols()) + } + + /// Return an iterator over the **exported** [`crate::macho::Symbol`] of this binary + pub fn exported_symbols(&self) -> ExportedSymbols<'_> { + ExportedSymbols::new(self.ptr.exported_symbols()) + } + + /// Return the `LC_DYLD_INFO/LC_DYLD_INFO_ONLY` command if present + pub fn dyld_info(&self) -> Option> { + into_optional(self.ptr.dyld_info()) + } + + /// Return the `LC_UUID` command if present + pub fn uuid(&self) -> Option> { + into_optional(self.ptr.uuid()) + } + + /// Return the `LC_MAIN` command if present + pub fn main_command(&self) -> Option> { + into_optional(self.ptr.main_command()) + } + + /// Return the `LC_LOAD_DYLINKER/LC_ID_DYLINKER` command if present + pub fn dylinker(&self) -> Option> { + into_optional(self.ptr.dylinker()) + } + + /// Return the `LC_FUNCTION_STARTS` command if present + pub fn function_starts(&self) -> Option> { + into_optional(self.ptr.function_starts()) + } + + /// Return the `LC_SOURCE_VERSION` command if present + pub fn source_version(&self) -> Option> { + into_optional(self.ptr.source_version()) + } + + /// Return the `LC_THREAD/LC_UNIXTHREAD` command if present + pub fn thread_command(&self) -> Option> { + into_optional(self.ptr.thread_command()) + } + + /// Return the `LC_RPATH` command if present + pub fn rpath(&self) -> Option> { + into_optional(self.ptr.rpath()) + } + + /// Return the `LC_ROUTINE/LC_ROUTINE64` command if present + pub fn routine(&self) -> Option> { + into_optional(self.ptr.routine_command()) + } + + /// Return the `LC_SYMTAB` command if present + pub fn symbol_command(&self) -> Option> { + into_optional(self.ptr.symbol_command()) + } + + /// Return the `LC_DYSYMTAB` command if present + pub fn dynamic_symbol(&self) -> Option> { + into_optional(self.ptr.dynamic_symbol_command()) + } + + /// Return the `LC_CODE_SIGNATURE` command if present + pub fn code_signature(&self) -> Option> { + into_optional(self.ptr.code_signature()) + } + + /// Return the `LC_DYLIB_CODE_SIGN_DRS` command if present + pub fn code_signature_dir(&self) -> Option> { + into_optional(self.ptr.code_signature_dir()) + } + + /// Return the `LC_DATA_IN_CODE` command if present + pub fn data_in_code(&self) -> Option> { + into_optional(self.ptr.data_in_code()) + } + + /// Return the `LC_SEGMENT_SPLIT_INFO` command if present + pub fn segment_split_info(&self) -> Option> { + into_optional(self.ptr.segment_split_info()) + } + + /// Return the `LC_ENCRYPTION_INFO/LC_ENCRYPTION_INFO_64` command if present + pub fn encryption_info(&self) -> Option> { + into_optional(self.ptr.encryption_info()) + } + + /// Return the `LC_SUB_FRAMEWORK` command if present + pub fn sub_framework(&self) -> Option> { + into_optional(self.ptr.sub_framework()) + } + + /// Return the `LC_SUBCLIENT` command if present + pub fn subclients(&self) -> SubClients<'_> { + SubClients::new(self.ptr.subclients()) + } + + /// Return the `LC_DYLD_ENVIRONMENT` command if present + pub fn dyld_environment(&self) -> Option> { + into_optional(self.ptr.dyld_environment()) + } + + /// Return the `LC_BUILD_VERSION` command if present + pub fn build_version(&self) -> Option> { + into_optional(self.ptr.build_version()) + } + + /// Return the `LC_DYLD_CHAINED_FIXUPS` command if present + pub fn dyld_chained_fixups(&self) -> Option> { + into_optional(self.ptr.dyld_chained_fixups()) + } + + /// Return the `LC_DYLD_EXPORTS_TRIE` command if present + pub fn dyld_exports_trie(&self) -> Option> { + into_optional(self.ptr.dyld_exports_trie()) + } + + /// Return the `LC_TWOLEVEL_HINTS` command if present + pub fn two_level_hints(&self) -> Option> { + into_optional(self.ptr.two_level_hints()) + } + + /// Return the `LC_LINKER_OPTIMIZATION_HINT` command if present + pub fn linker_opt_hint(&self) -> Option> { + into_optional(self.ptr.linker_opt_hint()) + } + + /// Return the `LC_ATOM_INFO` command if present + pub fn atom_info(&self) -> Option> { + into_optional(self.ptr.atom_info()) + } + + /// Return the `LC_FUNCTION_VARIANTS` command if present + pub fn function_variants(&self) -> Option> { + into_optional(self.ptr.function_variants()) + } + + /// Return the `LC_FUNCTION_VARIANT_FIXUPS` command if present + pub fn function_variant_fixups(&self) -> Option> { + into_optional(self.ptr.function_variant_fixups()) + } + + /// Return an iterator over the binary's `LC_LAZY_LOAD_DYLIB_INFO` commands + pub fn lazy_load_dylib_infos(&self) -> LazyLoadDylibInfos<'_> { + LazyLoadDylibInfos::new(self.ptr.lazy_load_dylib_infos()) + } + + /// Return the `LC_VERSION_MIN_MACOSX/VERSION_MIN_IPHONEOS` command if present + pub fn version_min(&self) -> Option> { + into_optional(self.ptr.version_min()) + } + + /// Check if the binary is supporting ARM64 pointer authentication (arm64e) + pub fn support_arm64_ptr_auth(&self) -> bool { + self.ptr.support_arm64_ptr_auth() + } + + /// Return an iterator over the bindings located in [`DyldInfo`] or [`DyldChainedFixups`] + pub fn bindings(&self) -> BindingsInfo<'_> { + BindingsInfo::new(self.ptr.bindings()) + } + + /// Return an iterator over the symbol stubs. + /// + /// These stubs are involved when calling an **imported** function and are + /// similar to the ELF's plt/got mechanism. + /// + /// There are located in sections like: `__stubs,__auth_stubs,__symbol_stub,__picsymbolstub4` + pub fn symbol_stubs(&self) -> Stubs<'_> { + Stubs::new(self.ptr.symbol_stubs()) + } + + /// Return Objective-C metadata if present + pub fn objc_metadata(&self) -> Option> { + into_optional(self.ptr.objc_metadata()) + } + + /// Return the platform for which this Mach-O has been compiled + pub fn platform(&self) -> Platform { + Platform::from(self.ptr.platform()) + } + + /// True if this binary targets iOS + pub fn is_ios(&self) -> bool { + self.ptr.is_ios() + } + + /// True if this binary targets macOS + pub fn is_macos(&self) -> bool { + self.ptr.is_macos() + } + + /// Try to find the library with the given library name. + /// + /// This function tries to match the fullpath of the DylibCommand or the + /// library name suffix. + pub fn find_library(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional(self.ptr.find_library(&__cxx_s)) + } + + /// Get the integer value at the given virtual address + pub fn get_int_from_virtual_address(&self, addr: u64) -> Result + where + T: Num + cast::FromPrimitive + cast::ToPrimitive, + { + // Can't be in the generic trait because of: + // > for a trait to be "object safe" it needs to allow building a vtable to allow the call + // > to be resolvable dynamically; for more information visit + // > https://doc.rust-lang.org/reference/items/traits.html#object-safety + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u8, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u8(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u16, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u16(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u32, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u32(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u64, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u64(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + Err(Error::NotSupported) + } + + /// Write back the current MachO binary into the file specified in parameter + pub fn write>(&mut self, output: P) { + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr.as_mut().unwrap().write(&__cxx_s); + } + + /// Write back the current MachO binary into the file specified in parameter with the + /// configuration provided in the second parameter. + pub fn write_with_config>(&mut self, output: P, config: Config) { + cxx::let_cxx_string!(__cxx_out = output.as_ref().to_str().unwrap()); + let cfg = config.to_ffi(); + self.ptr + .as_mut() + .unwrap() + .write_with_config(&__cxx_out, &cfg); + } + + /// Rebuild the current MachO binary and return the raw bytes. + /// + /// This is similar to [`Binary::write`] but instead of writing the result + /// into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes(&mut self) -> Vec { + Vec::from(self.ptr.as_mut().unwrap().write_to_bytes().as_slice()) + } + + /// Rebuild the current MachO binary with the configuration provided in the + /// parameter and return the raw bytes. + /// + /// This is similar to [`Binary::write_with_config`] but instead of writing + /// the result into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes_with_config(&mut self, config: Config) -> Vec { + let cfg = config.to_ffi(); + Vec::from( + self.ptr + .as_mut() + .unwrap() + .write_to_bytes_with_config(&cfg) + .as_slice(), + ) + } + + /// Insert a new command + pub fn add_command(&mut self, command: impl Command) -> Option> { + into_optional(self.ptr.as_mut().unwrap().add_command(command.get_base())) + } + + /// Insert a new shared library through a `LC_LOAD_DYLIB` command + pub fn add_library<'a>(&'a mut self, libname: &str) -> Dylib<'a> { + cxx::let_cxx_string!(__cxx_s = libname); + Dylib::from_ffi(self.ptr.as_mut().unwrap().add_library(&__cxx_s)) + } + + /// Remove all commands that have the given type + pub fn remove_commands_by_type(&mut self, ty: LoadCommandTypes) -> bool { + self.ptr + .as_mut() + .unwrap() + .remove_commands_by_type(ty.into()) + } + + pub fn functions(&self) -> generic::Functions<'_> { + generic::Functions::new(self.ptr.functions()) + } + + /// Return an iterator over the `LC_NOTE` commands + pub fn notes(&self) -> Notes<'_> { + Notes::new(self.ptr.notes()) + } + + /// Name associated with the `LC_FILESET_ENTRY` for this MachO. + /// For instance: `com.apple.kec.corecrypto` + pub fn fileset_name(&self) -> String { + self.ptr.fileset_name().to_string() + } + + /// Original address associated with the `LC_FILESET_ENTRY` for this MachO. + pub fn fileset_addr(&self) -> u64 { + self.ptr.fileset_addr() + } + + /// Return an iterator over the [`Binary`] associated with the `LC_FILESET_ENTRY` commands + pub fn filesets(&self) -> FilesetBinaries<'_> { + FilesetBinaries::new(self.ptr.filesets()) + } + + /// Convert the given virtual address into an offset + pub fn virtual_address_to_offset(&self, address: u64) -> Result { + to_result!(ffi::MachO_Binary::virtual_address_to_offset, &self, address); + } + /// Return the [`Segment`] associated with the given offset + pub fn segment_from_offset(&self, offset: u64) -> Option> { + into_optional(self.ptr.segment_from_offset(offset)) + } + + /// Return the [`Segment`] associated with the given virtual address + pub fn segment_from_virtual_address(&self, va: u64) -> Option> { + into_optional(self.ptr.segment_from_virtual_address(va)) + } + + /// Return the [`Section`] associated with the given virtual address + pub fn section_from_virtual_address(&self, va: u64) -> Option> { + into_optional(self.ptr.section_from_virtual_address(va)) + } + + /// Return the [`Segment`] matching the given name + pub fn get_segment(&self, name: String) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.get_segment(&__cxx_s)) + } + + /// Return the [`Section`] embedded in the given segment's name + pub fn get_section(&self, segment_name: String, section_name: String) -> Option> { + cxx::let_cxx_string!(seg = segment_name); + cxx::let_cxx_string!(sec = section_name); + into_optional(self.ptr.get_section(&seg, &sec)) + } + + /// Return the offset of this binary in the FAT binary + pub fn fat_offset(&self) -> u64 { + self.ptr.fat_offset() + } + + /// Return the overlay data (if any) + pub fn overlay(&self) -> &[u8] { + to_slice!(self.ptr.overlay()); + } + + /// Return the TLV initial content range + pub fn tlv_initial_content_range(&self) -> crate::Range { + crate::Range::from_ffi(&self.ptr.tlv_initial_content_range()) + } + + /// Check if the given address is valid for this binary + pub fn is_valid_addr(&self, address: u64) -> bool { + self.ptr.is_valid_addr(address) + } + + /// Check if the binary contains a symbol with the given name + pub fn has_symbol(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_symbol(&__cxx_s) + } + + /// Return the symbol with the given name (if any) + pub fn get_symbol(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional(self.ptr.get_symbol(&__cxx_s)) + } + + /// Check if the binary contains a section with the given name + pub fn has_section(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_section(&__cxx_s) + } + + /// Return the [`Section`] associated with the given offset + pub fn section_from_offset(&self, offset: u64) -> Option> { + into_optional(self.ptr.section_from_offset(offset)) + } + + /// Check if the binary contains a segment with the given name + pub fn has_segment(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_segment(&__cxx_s) + } + + /// Check if the binary has a command with the given type + pub fn has_command_type(&self, ty: LoadCommandTypes) -> bool { + self.ptr.has_command_type(ty.into()) + } + + /// Get a command with the given type + pub fn get_command_type(&self, ty: LoadCommandTypes) -> Option> { + into_optional(self.ptr.get_command_type(ty.into())) + } + + /// Remove the command at the given index + pub fn remove_command(&mut self, index: u32) -> bool { + self.ptr.as_mut().unwrap().remove_command(index) + } + + /// Remove a section by name + pub fn remove_section(&mut self, name: &str, clear: bool) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.as_mut().unwrap().remove_section(&__cxx_s, clear); + } + + /// Remove a section by segment name and section name + pub fn remove_section_from_segment(&mut self, segname: &str, secname: &str, clear: bool) { + cxx::let_cxx_string!(seg = segname); + cxx::let_cxx_string!(sec = secname); + self.ptr + .as_mut() + .unwrap() + .remove_section_seg(&seg, &sec, clear); + } + + /// Remove the `LC_CODE_SIGNATURE` command + pub fn remove_signature(&mut self) -> bool { + self.ptr.as_mut().unwrap().remove_signature() + } + + /// Remove a symbol by name + pub fn remove_symbol(&mut self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.as_mut().unwrap().remove_symbol(&__cxx_s) + } + + /// Check if the given symbol can be safely removed + pub fn can_remove(&self, sym: &Symbol<'_>) -> bool { + self.ptr.can_remove(sym.as_ffi()) + } + + /// Check if the symbol with the given name can be safely removed + pub fn can_remove_symbol(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.can_remove_symbol(&__cxx_s) + } + + /// Unexport the symbol with the given name + pub fn unexport_name(&mut self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.as_mut().unwrap().unexport_name(&__cxx_s) + } + + /// Unexport the given symbol + pub fn unexport_symbol(&mut self, sym: &super::Symbol<'_>) -> bool { + self.ptr.as_mut().unwrap().unexport_symbol(sym.as_ffi()) + } + + /// Add a new exported function + pub fn add_exported_function(&mut self, address: u64, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional( + self.ptr + .as_mut() + .unwrap() + .add_exported_function(address, &__cxx_s), + ) + } + + /// Add a new local symbol + pub fn add_local_symbol(&mut self, address: u64, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional( + self.ptr + .as_mut() + .unwrap() + .add_local_symbol(address, &__cxx_s), + ) + } + + /// Shift the content of the binary + pub fn shift(&mut self, value: u64) -> Result<(), Error> { + to_conv_result!(ffi::MachO_Binary::shift, self.ptr.pin_mut(), |_| (), value); + } + + /// Shift the __LINKEDIT segment + pub fn shift_linkedit(&mut self, width: u64) -> Result<(), Error> { + to_conv_result!( + ffi::MachO_Binary::shift_linkedit, + self.ptr.pin_mut(), + |_| (), + width + ); + } +} + +impl AsFFI for Binary { + fn as_ffi(&self) -> &ffi::MachO_Binary { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::MachO_Binary> { + self.ptr.pin_mut() + } +} + +impl generic::Binary for Binary { + fn as_generic(&self) -> &ffi::AbstractBinary { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractBinary> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractBinary + as *mut ffi::AbstractBinary) + .as_mut() + .unwrap() + }) + } + } +} + +declare_fwd_iterator!( + BindingsInfo, + BindingInfo<'a>, + ffi::MachO_BindingInfo, + ffi::MachO_Binary, + ffi::MachO_Binary_it_bindings_info +); + +declare_iterator!( + Stubs, + Stub<'a>, + ffi::MachO_Stub, + ffi::MachO_Binary, + ffi::MachO_Binary_it_stubs +); + +declare_iterator!( + Notes, + Note<'a>, + ffi::MachO_NoteCommand, + ffi::MachO_Binary, + ffi::MachO_Binary_it_notes +); + +declare_iterator!( + FilesetBinaries, + Binary, + ffi::MachO_Binary, + ffi::MachO_Binary, + ffi::MachO_Binary_it_fileset_binaries +); + +declare_iterator!( + LazyLoadDylibInfos, + LazyLoadDylibInfo<'a>, + ffi::MachO_LazyLoadDylibInfo, + ffi::MachO_Binary, + ffi::MachO_Binary_it_lazy_load_dylib_info +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/binding_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/binding_info.rs new file mode 100644 index 0000000..9eb607a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/binding_info.rs @@ -0,0 +1,341 @@ +use lief_ffi as ffi; + +use super::commands::Segment; +use super::commands::dylib::Dylib; +use super::symbol::Symbol; +use std::{fmt, marker::PhantomData}; + +use crate::common::{FromFFI, into_optional}; + +#[derive(Debug)] +/// This enum exposes all the different types of binding operations that +/// we can find in a Mach-O binary. [`BindingInfo::Dyld`] exposes the bindings info +/// wrapped in the `LC_DYLD_INFO` command while [`BindingInfo::Chained`] exposes the new +/// chained bindings implemented in the `DYLD_CHAINED_FIXUPS` command. +pub enum BindingInfo<'a> { + /// Bindings defined in `LC_DYLD_INFO` command + Dyld(Dyld<'a>), + /// Bindings defined in `DYLD_CHAINED_FIXUPS` command + Chained(Chained<'a>), + /// Bindings infered from the indirect symbol table + Indirect(Indirect<'a>), + /// Fallback item + Generic(Generic<'a>), +} + +/// Generic trait shared by all [`BindingInfo`] items +pub trait AsGeneric { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::MachO_BindingInfo; + + /// Library associated with the binding (if any) + fn library(&self) -> Option> { + into_optional(self.as_generic().library()) + } + + /// Symbol associated with the binding (if any) + fn symbol(&self) -> Option> { + into_optional(self.as_generic().symbol()) + } + + /// Segment associated with the binding (if any) + fn segment(&self) -> Option> { + into_optional(self.as_generic().segment()) + } + + /// Address of the binding + fn address(&self) -> u64 { + self.as_generic().address() + } + + /// Value added to the segment's virtual address when bound + fn addend(&self) -> i64 { + self.as_generic().addend() + } + + fn library_ordinal(&self) -> i32 { + self.as_generic().library_ordinal() + } +} + +impl AsGeneric for BindingInfo<'_> { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::MachO_BindingInfo { + match &self { + BindingInfo::Dyld(info) => info.as_generic(), + BindingInfo::Chained(info) => info.as_generic(), + BindingInfo::Indirect(info) => info.as_generic(), + BindingInfo::Generic(info) => info.as_generic(), + } + } +} + +impl std::fmt::Debug for &dyn AsGeneric { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("AsGeneric") + .field("address", &self.address()) + .field("addend", &self.addend()) + .field("library_ordinal", &self.library_ordinal()) + .finish() + } +} + +impl<'a> FromFFI for BindingInfo<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::MachO_ChainedBindingInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + BindingInfo::Chained(Chained::from_ffi(raw)) + } else if ffi::MachO_DyldBindingInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + BindingInfo::Dyld(Dyld::from_ffi(raw)) + } else if ffi::MachO_IndirectBindingInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + BindingInfo::Indirect(Indirect::from_ffi(raw)) + } else { + BindingInfo::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn AsGeneric; + f.debug_struct("Generic").field("base", &base).finish() + } +} + +impl<'a> FromFFI for Generic<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsGeneric for Generic<'_> { + fn as_generic(&self) -> &ffi::MachO_BindingInfo { + self.ptr.as_ref().unwrap() + } +} + +/// This structure represents a binding operation coming from binding bytecode +/// of `LC_DYLD_INFO` +pub struct Dyld<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum BINDING_CLASS { + WEAK, + LAZY, + STANDARD, + THREADED, + UNKNOWN(u64), +} + +impl BINDING_CLASS { + pub fn from_value(value: u64) -> Self { + match value { + 0x00000001 => BINDING_CLASS::WEAK, + 0x00000002 => BINDING_CLASS::LAZY, + 0x00000003 => BINDING_CLASS::STANDARD, + 0x00000064 => BINDING_CLASS::THREADED, + _ => BINDING_CLASS::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum BIND_TYPES { + POINTER, + TEXT_ABSOLUTE32, + TEXT_PCREL32, + UNKNOWN(u64), +} + +impl BIND_TYPES { + pub fn from_value(value: u64) -> Self { + match value { + 0x00000001 => BIND_TYPES::POINTER, + 0x00000002 => BIND_TYPES::TEXT_ABSOLUTE32, + 0x00000003 => BIND_TYPES::TEXT_PCREL32, + _ => BIND_TYPES::UNKNOWN(value), + } + } +} + +impl Dyld<'_> { + /// Class of the binding (weak, lazy, ...) + pub fn binding_class(&self) -> BINDING_CLASS { + BINDING_CLASS::from_value(self.ptr.binding_class()) + } + + /// Type of the binding. Most of the times it should be [`BIND_TYPES::POINTER`] + pub fn binding_type(&self) -> BIND_TYPES { + BIND_TYPES::from_value(self.ptr.binding_type()) + } + + pub fn is_non_weak_definition(&self) -> bool { + self.ptr.is_non_weak_definition() + } + + pub fn original_offset(&self) -> u64 { + self.ptr.original_offset() + } +} + +impl fmt::Debug for Dyld<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn AsGeneric; + f.debug_struct("Dyld") + .field("base", &base) + .field("binding_class", &self.binding_class()) + .field("binding_type", &self.binding_type()) + .field("is_non_weak_definition", &self.is_non_weak_definition()) + .field("original_offset", &self.original_offset()) + .finish() + } +} + +impl FromFFI for Dyld<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsGeneric for Dyld<'_> { + fn as_generic(&self) -> &ffi::MachO_BindingInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} +/// This structure represents a binding operation coming from chained binding command: +/// `LC_DYLD_CHAINED_FIXUPS` +pub struct Chained<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum CHAINED_FORMAT { + IMPORT, + IMPORT_ADDEND, + IMPORT_ADDEND64, + UNKNOWN(u32), +} + +impl CHAINED_FORMAT { + pub fn from_value(value: u32) -> Self { + match value { + 0x00000001 => CHAINED_FORMAT::IMPORT, + 0x00000002 => CHAINED_FORMAT::IMPORT_ADDEND, + 0x00000003 => CHAINED_FORMAT::IMPORT_ADDEND64, + _ => CHAINED_FORMAT::UNKNOWN(value), + } + } +} + +impl Chained<'_> { + /// Format of the imports + pub fn format(&self) -> CHAINED_FORMAT { + CHAINED_FORMAT::from_value(self.ptr.format()) + } + + /// Format of the pointer + pub fn ptr_format(&self) -> u32 { + self.ptr.ptr_format() + } + + /// Original offset in the chain of this binding + pub fn offset(&self) -> u32 { + self.ptr.offset() + } + + /// Sign-extended addend for this chained binding + pub fn sign_extended_addend(&self) -> u64 { + self.ptr.sign_extended_addend() + } +} + +impl fmt::Debug for Chained<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn AsGeneric; + f.debug_struct("Chained") + .field("base", &base) + .field("format", &self.format()) + .field("ptr_format", &self.ptr_format()) + .field("offset", &self.offset()) + .finish() + } +} + +impl FromFFI for Chained<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsGeneric for Chained<'_> { + fn as_generic(&self) -> &ffi::MachO_BindingInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This structure represents a binding operation coming from the indirect symbol table +pub struct Indirect<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl fmt::Debug for Indirect<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn AsGeneric; + f.debug_struct("Indirect").field("base", &base).finish() + } +} + +impl FromFFI for Indirect<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsGeneric for Indirect<'_> { + fn as_generic(&self) -> &ffi::MachO_BindingInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/builder.rs b/vendor/lief/api/rust/crates/lief/src/macho/builder.rs new file mode 100644 index 0000000..67baab8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/builder.rs @@ -0,0 +1,23 @@ +use lief_ffi as ffi; + +/// Structure used to configure the [`crate::macho::Binary::write_with_config`] operation +#[derive(Debug)] +pub struct Config { + /// Rebuild the `__LINKEDIT` segment + pub linkedit: bool, +} + +impl Default for Config { + fn default() -> Config { + Config { linkedit: true } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> ffi::MachO_Binary_write_config_t { + ffi::MachO_Binary_write_config_t { + linkedit: self.linkedit, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands.rs new file mode 100644 index 0000000..704d771 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands.rs @@ -0,0 +1,786 @@ +use std::marker::PhantomData; + +use lief_ffi as ffi; +pub mod atom_info; +pub mod build_version; +pub mod code_signature; +pub mod code_signature_dir; +pub mod data_in_code; +pub mod dyld_chained_fixups; +pub mod dyld_environment; +pub mod dyld_export_trie; +pub mod dyldinfo; +pub mod dylib; +pub mod dylinker; +pub mod dynamic_symbol_command; +pub mod encryption_info; +pub mod fileset; +pub mod function_variant_fixups; +pub mod function_variants; +pub mod functionstarts; +pub mod lazy_load_dylib_info; +pub mod linker_opt_hint; +pub mod main_cmd; +pub mod note; +pub mod routine; +pub mod rpath; +pub mod segment; +pub mod segment_split_info; +pub mod source_version; +pub mod sub_client; +pub mod sub_framework; +pub mod symbol_command; +pub mod thread_command; +pub mod two_level_hints; +pub mod unknown; +pub mod uuid; +pub mod version_min; + +#[doc(inline)] +pub use atom_info::AtomInfo; +#[doc(inline)] +pub use build_version::BuildVersion; +#[doc(inline)] +pub use code_signature::CodeSignature; +#[doc(inline)] +pub use code_signature_dir::CodeSignatureDir; +#[doc(inline)] +pub use data_in_code::DataInCode; +#[doc(inline)] +pub use dyld_chained_fixups::DyldChainedFixups; +#[doc(inline)] +pub use dyld_environment::DyldEnvironment; +#[doc(inline)] +pub use dyld_export_trie::DyldExportsTrie; +#[doc(inline)] +pub use dyldinfo::DyldInfo; +#[doc(inline)] +pub use dylib::{Dylib, Libraries}; +#[doc(inline)] +pub use dylinker::Dylinker; +#[doc(inline)] +pub use dynamic_symbol_command::DynamicSymbolCommand; +#[doc(inline)] +pub use encryption_info::EncryptionInfo; +#[doc(inline)] +pub use fileset::Fileset; +#[doc(inline)] +pub use function_variant_fixups::FunctionVariantFixups; +#[doc(inline)] +pub use function_variants::FunctionVariants; +#[doc(inline)] +pub use functionstarts::FunctionStarts; +#[doc(inline)] +pub use lazy_load_dylib_info::LazyLoadDylibInfo; +#[doc(inline)] +pub use linker_opt_hint::LinkerOptHint; +#[doc(inline)] +pub use main_cmd::Main; +#[doc(inline)] +pub use note::Note; +#[doc(inline)] +pub use routine::Routine; +#[doc(inline)] +pub use rpath::RPath; +#[doc(inline)] +pub use segment::Segment; +#[doc(inline)] +pub use segment_split_info::SegmentSplitInfo; +#[doc(inline)] +pub use source_version::SourceVersion; +#[doc(inline)] +pub use sub_client::SubClient; +#[doc(inline)] +pub use sub_framework::SubFramework; +#[doc(inline)] +pub use symbol_command::SymbolCommand; +#[doc(inline)] +pub use thread_command::ThreadCommand; +#[doc(inline)] +pub use two_level_hints::TwoLevelHints; +#[doc(inline)] +pub use unknown::Unknown; +#[doc(inline)] +pub use uuid::UUID; +#[doc(inline)] +pub use version_min::VersionMin; + +use crate::common::FromFFI; +use crate::{declare_iterator, to_slice}; + +#[derive(Debug, Copy, Clone)] +pub enum LoadCommandTypes { + BuildVersion, + CodeSignature, + DataInCode, + DyldChainedFixups, + DyldEnvironment, + DyldExportsTrie, + DyldInfo, + DyldInfoOnly, + DylibCodeSignDrs, + Dysymtab, + EncryptionInfo, + EncryptionInfo64, + FilesetEntry, + FunctionStarts, + Fvmfile, + Ident, + Idfvmlib, + IdDylib, + IdDylinker, + LazyLoadDylib, + LinkerOptimizationHint, + LinkerOption, + LoadFvmLib, + LoadDylib, + LoadDylinker, + LoadUpwardDylib, + LoadWeakDylib, + Main, + Note, + PrebindCksum, + PreboundDylib, + Prepage, + ReExportDylib, + Routines, + Routines64, + Rpath, + Segment, + Segment64, + SegmentSplitInfo, + SourceVersion, + SubClient, + SubFramework, + SubLibrary, + SubUmbrella, + Symseg, + Symtab, + Thread, + TwoLevelHints, + Unixthread, + Uuid, + VersionMinIphoneOS, + VersionMinMacOSX, + VersionMinTvOS, + VersionMinWatchOS, + AtomInfo, + FunctionVariants, + FunctionVariantsFixups, + TargetTriple, + LazyLoadDylibInfo, + + LiefUnknown, + Unknown(u64), +} +impl LoadCommandTypes { + const LC_BUILD_VERSION: u64 = 0x00000032; + const LC_CODE_SIGNATURE: u64 = 0x0000001D; + const LC_DATA_IN_CODE: u64 = 0x00000029; + const LC_DYLD_CHAINED_FIXUPS: u64 = 0x80000034; + const LC_DYLD_ENVIRONMENT: u64 = 0x00000027; + const LC_DYLD_EXPORTS_TRIE: u64 = 0x80000033; + const LC_DYLD_INFO: u64 = 0x00000022; + const LC_DYLD_INFO_ONLY: u64 = 0x80000022; + const LC_DYLIB_CODE_SIGN_DRS: u64 = 0x0000002B; + const LC_DYSYMTAB: u64 = 0x0000000B; + const LC_ENCRYPTION_INFO: u64 = 0x00000021; + const LC_ENCRYPTION_INFO_64: u64 = 0x0000002C; + const LC_FILESET_ENTRY: u64 = 0x80000035; + const LC_FUNCTION_STARTS: u64 = 0x00000026; + const LC_FVMFILE: u64 = 0x00000009; + const LC_IDENT: u64 = 0x00000008; + const LC_IDFVMLIB: u64 = 0x00000007; + const LC_ID_DYLIB: u64 = 0x0000000D; + const LC_ID_DYLINKER: u64 = 0x0000000F; + const LC_LAZY_LOAD_DYLIB: u64 = 0x00000020; + const LC_LINKER_OPTIMIZATION_HINT: u64 = 0x0000002E; + const LC_LINKER_OPTION: u64 = 0x0000002D; + const LC_LOADFVMLIB: u64 = 0x00000006; + const LC_LOAD_DYLIB: u64 = 0x0000000C; + const LC_LOAD_DYLINKER: u64 = 0x0000000E; + const LC_LOAD_UPWARD_DYLIB: u64 = 0x80000023; + const LC_LOAD_WEAK_DYLIB: u64 = 0x80000018; + const LC_MAIN: u64 = 0x80000028; + const LC_NOTE: u64 = 0x00000031; + const LC_PREBIND_CKSUM: u64 = 0x00000017; + const LC_PREBOUND_DYLIB: u64 = 0x00000010; + const LC_PREPAGE: u64 = 0x0000000A; + const LC_REEXPORT_DYLIB: u64 = 0x8000001F; + const LC_ROUTINES: u64 = 0x00000011; + const LC_ROUTINES_64: u64 = 0x0000001A; + const LC_RPATH: u64 = 0x8000001C; + const LC_SEGMENT: u64 = 0x00000001; + const LC_SEGMENT_64: u64 = 0x00000019; + const LC_SEGMENT_SPLIT_INFO: u64 = 0x0000001E; + const LC_SOURCE_VERSION: u64 = 0x0000002A; + const LC_SUB_CLIENT: u64 = 0x00000014; + const LC_SUB_FRAMEWORK: u64 = 0x00000012; + const LC_SUB_LIBRARY: u64 = 0x00000015; + const LC_SUB_UMBRELLA: u64 = 0x00000013; + const LC_SYMSEG: u64 = 0x00000003; + const LC_SYMTAB: u64 = 0x00000002; + const LC_THREAD: u64 = 0x00000004; + const LC_TWOLEVEL_HINTS: u64 = 0x00000016; + const LC_UNIXTHREAD: u64 = 0x00000005; + const LC_UUID: u64 = 0x0000001B; + const LC_VERSION_MIN_IPHONEOS: u64 = 0x00000025; + const LC_VERSION_MIN_MACOSX: u64 = 0x00000024; + const LC_VERSION_MIN_TVOS: u64 = 0x0000002F; + const LC_VERSION_MIN_WATCHOS: u64 = 0x00000030; + const LC_ATOM_INFO: u64 = 0x00000036; + const LC_FUNCTION_VARIANTS: u64 = 0x00000037; + const LC_FUNCTION_VARIANT_FIXUPS: u64 = 0x00000038; + const LC_TARGET_TRIPLE: u64 = 0x00000039; + const LC_LAZY_LOAD_DYLIB_INFO: u64 = 0x0000003A; + + const LIEF_UNKNOWN: u64 = 0xffee0001; +} + +impl From for LoadCommandTypes { + fn from(value: u64) -> Self { + match value { + LoadCommandTypes::LC_BUILD_VERSION => LoadCommandTypes::BuildVersion, + LoadCommandTypes::LC_CODE_SIGNATURE => LoadCommandTypes::CodeSignature, + LoadCommandTypes::LC_DATA_IN_CODE => LoadCommandTypes::DataInCode, + LoadCommandTypes::LC_DYLD_CHAINED_FIXUPS => LoadCommandTypes::DyldChainedFixups, + LoadCommandTypes::LC_DYLD_ENVIRONMENT => LoadCommandTypes::DyldEnvironment, + LoadCommandTypes::LC_DYLD_EXPORTS_TRIE => LoadCommandTypes::DyldExportsTrie, + LoadCommandTypes::LC_DYLD_INFO => LoadCommandTypes::DyldInfo, + LoadCommandTypes::LC_DYLD_INFO_ONLY => LoadCommandTypes::DyldInfoOnly, + LoadCommandTypes::LC_DYLIB_CODE_SIGN_DRS => LoadCommandTypes::DylibCodeSignDrs, + LoadCommandTypes::LC_DYSYMTAB => LoadCommandTypes::Dysymtab, + LoadCommandTypes::LC_ENCRYPTION_INFO => LoadCommandTypes::EncryptionInfo, + LoadCommandTypes::LC_ENCRYPTION_INFO_64 => LoadCommandTypes::EncryptionInfo64, + LoadCommandTypes::LC_FILESET_ENTRY => LoadCommandTypes::FilesetEntry, + LoadCommandTypes::LC_FUNCTION_STARTS => LoadCommandTypes::FunctionStarts, + LoadCommandTypes::LC_FVMFILE => LoadCommandTypes::Fvmfile, + LoadCommandTypes::LC_IDENT => LoadCommandTypes::Ident, + LoadCommandTypes::LC_IDFVMLIB => LoadCommandTypes::Idfvmlib, + LoadCommandTypes::LC_ID_DYLIB => LoadCommandTypes::IdDylib, + LoadCommandTypes::LC_ID_DYLINKER => LoadCommandTypes::IdDylinker, + LoadCommandTypes::LC_LAZY_LOAD_DYLIB => LoadCommandTypes::LazyLoadDylib, + LoadCommandTypes::LC_LINKER_OPTIMIZATION_HINT => { + LoadCommandTypes::LinkerOptimizationHint + } + LoadCommandTypes::LC_LINKER_OPTION => LoadCommandTypes::LinkerOption, + LoadCommandTypes::LC_LOADFVMLIB => LoadCommandTypes::LoadFvmLib, + LoadCommandTypes::LC_LOAD_DYLIB => LoadCommandTypes::LoadDylib, + LoadCommandTypes::LC_LOAD_DYLINKER => LoadCommandTypes::LoadDylinker, + LoadCommandTypes::LC_LOAD_UPWARD_DYLIB => LoadCommandTypes::LoadUpwardDylib, + LoadCommandTypes::LC_LOAD_WEAK_DYLIB => LoadCommandTypes::LoadWeakDylib, + LoadCommandTypes::LC_MAIN => LoadCommandTypes::Main, + LoadCommandTypes::LC_NOTE => LoadCommandTypes::Note, + LoadCommandTypes::LC_PREBIND_CKSUM => LoadCommandTypes::PrebindCksum, + LoadCommandTypes::LC_PREBOUND_DYLIB => LoadCommandTypes::PreboundDylib, + LoadCommandTypes::LC_PREPAGE => LoadCommandTypes::Prepage, + LoadCommandTypes::LC_REEXPORT_DYLIB => LoadCommandTypes::ReExportDylib, + LoadCommandTypes::LC_ROUTINES => LoadCommandTypes::Routines, + LoadCommandTypes::LC_ROUTINES_64 => LoadCommandTypes::Routines64, + LoadCommandTypes::LC_RPATH => LoadCommandTypes::Rpath, + LoadCommandTypes::LC_SEGMENT => LoadCommandTypes::Segment, + LoadCommandTypes::LC_SEGMENT_64 => LoadCommandTypes::Segment64, + LoadCommandTypes::LC_SEGMENT_SPLIT_INFO => LoadCommandTypes::SegmentSplitInfo, + LoadCommandTypes::LC_SOURCE_VERSION => LoadCommandTypes::SourceVersion, + LoadCommandTypes::LC_SUB_CLIENT => LoadCommandTypes::SubClient, + LoadCommandTypes::LC_SUB_FRAMEWORK => LoadCommandTypes::SubFramework, + LoadCommandTypes::LC_SUB_LIBRARY => LoadCommandTypes::SubLibrary, + LoadCommandTypes::LC_SUB_UMBRELLA => LoadCommandTypes::SubUmbrella, + LoadCommandTypes::LC_SYMSEG => LoadCommandTypes::Symseg, + LoadCommandTypes::LC_SYMTAB => LoadCommandTypes::Symtab, + LoadCommandTypes::LC_THREAD => LoadCommandTypes::Thread, + LoadCommandTypes::LC_TWOLEVEL_HINTS => LoadCommandTypes::TwoLevelHints, + LoadCommandTypes::LC_UNIXTHREAD => LoadCommandTypes::Unixthread, + LoadCommandTypes::LC_UUID => LoadCommandTypes::Uuid, + LoadCommandTypes::LC_VERSION_MIN_IPHONEOS => LoadCommandTypes::VersionMinIphoneOS, + LoadCommandTypes::LC_VERSION_MIN_MACOSX => LoadCommandTypes::VersionMinMacOSX, + LoadCommandTypes::LC_VERSION_MIN_TVOS => LoadCommandTypes::VersionMinTvOS, + LoadCommandTypes::LC_VERSION_MIN_WATCHOS => LoadCommandTypes::VersionMinWatchOS, + LoadCommandTypes::LC_ATOM_INFO => LoadCommandTypes::AtomInfo, + LoadCommandTypes::LC_FUNCTION_VARIANTS => LoadCommandTypes::FunctionVariants, + LoadCommandTypes::LC_FUNCTION_VARIANT_FIXUPS => { + LoadCommandTypes::FunctionVariantsFixups + } + LoadCommandTypes::LC_TARGET_TRIPLE => LoadCommandTypes::TargetTriple, + LoadCommandTypes::LC_LAZY_LOAD_DYLIB_INFO => LoadCommandTypes::LazyLoadDylibInfo, + LoadCommandTypes::LIEF_UNKNOWN => LoadCommandTypes::LiefUnknown, + _ => LoadCommandTypes::Unknown(value), + } + } +} + +impl From for u64 { + fn from(value: LoadCommandTypes) -> Self { + match value { + LoadCommandTypes::BuildVersion => LoadCommandTypes::LC_BUILD_VERSION, + LoadCommandTypes::CodeSignature => LoadCommandTypes::LC_CODE_SIGNATURE, + LoadCommandTypes::DataInCode => LoadCommandTypes::LC_DATA_IN_CODE, + LoadCommandTypes::DyldChainedFixups => LoadCommandTypes::LC_DYLD_CHAINED_FIXUPS, + LoadCommandTypes::DyldEnvironment => LoadCommandTypes::LC_DYLD_ENVIRONMENT, + LoadCommandTypes::DyldExportsTrie => LoadCommandTypes::LC_DYLD_EXPORTS_TRIE, + LoadCommandTypes::DyldInfo => LoadCommandTypes::LC_DYLD_INFO, + LoadCommandTypes::DyldInfoOnly => LoadCommandTypes::LC_DYLD_INFO_ONLY, + LoadCommandTypes::DylibCodeSignDrs => LoadCommandTypes::LC_DYLIB_CODE_SIGN_DRS, + LoadCommandTypes::Dysymtab => LoadCommandTypes::LC_DYSYMTAB, + LoadCommandTypes::EncryptionInfo => LoadCommandTypes::LC_ENCRYPTION_INFO, + LoadCommandTypes::EncryptionInfo64 => LoadCommandTypes::LC_ENCRYPTION_INFO_64, + LoadCommandTypes::FilesetEntry => LoadCommandTypes::LC_FILESET_ENTRY, + LoadCommandTypes::FunctionStarts => LoadCommandTypes::LC_FUNCTION_STARTS, + LoadCommandTypes::Fvmfile => LoadCommandTypes::LC_FVMFILE, + LoadCommandTypes::Ident => LoadCommandTypes::LC_IDENT, + LoadCommandTypes::Idfvmlib => LoadCommandTypes::LC_IDFVMLIB, + LoadCommandTypes::IdDylib => LoadCommandTypes::LC_ID_DYLIB, + LoadCommandTypes::IdDylinker => LoadCommandTypes::LC_ID_DYLINKER, + LoadCommandTypes::LazyLoadDylib => LoadCommandTypes::LC_LAZY_LOAD_DYLIB, + LoadCommandTypes::LinkerOptimizationHint => { + LoadCommandTypes::LC_LINKER_OPTIMIZATION_HINT + } + LoadCommandTypes::LinkerOption => LoadCommandTypes::LC_LINKER_OPTION, + LoadCommandTypes::LoadFvmLib => LoadCommandTypes::LC_LOADFVMLIB, + LoadCommandTypes::LoadDylib => LoadCommandTypes::LC_LOAD_DYLIB, + LoadCommandTypes::LoadDylinker => LoadCommandTypes::LC_LOAD_DYLINKER, + LoadCommandTypes::LoadUpwardDylib => LoadCommandTypes::LC_LOAD_UPWARD_DYLIB, + LoadCommandTypes::LoadWeakDylib => LoadCommandTypes::LC_LOAD_WEAK_DYLIB, + LoadCommandTypes::Main => LoadCommandTypes::LC_MAIN, + LoadCommandTypes::Note => LoadCommandTypes::LC_NOTE, + LoadCommandTypes::PrebindCksum => LoadCommandTypes::LC_PREBIND_CKSUM, + LoadCommandTypes::PreboundDylib => LoadCommandTypes::LC_PREBOUND_DYLIB, + LoadCommandTypes::Prepage => LoadCommandTypes::LC_PREPAGE, + LoadCommandTypes::ReExportDylib => LoadCommandTypes::LC_REEXPORT_DYLIB, + LoadCommandTypes::Routines => LoadCommandTypes::LC_ROUTINES, + LoadCommandTypes::Routines64 => LoadCommandTypes::LC_ROUTINES_64, + LoadCommandTypes::Rpath => LoadCommandTypes::LC_RPATH, + LoadCommandTypes::Segment => LoadCommandTypes::LC_SEGMENT, + LoadCommandTypes::Segment64 => LoadCommandTypes::LC_SEGMENT_64, + LoadCommandTypes::SegmentSplitInfo => LoadCommandTypes::LC_SEGMENT_SPLIT_INFO, + LoadCommandTypes::SourceVersion => LoadCommandTypes::LC_SOURCE_VERSION, + LoadCommandTypes::SubClient => LoadCommandTypes::LC_SUB_CLIENT, + LoadCommandTypes::SubFramework => LoadCommandTypes::LC_SUB_FRAMEWORK, + LoadCommandTypes::SubLibrary => LoadCommandTypes::LC_SUB_LIBRARY, + LoadCommandTypes::SubUmbrella => LoadCommandTypes::LC_SUB_UMBRELLA, + LoadCommandTypes::Symseg => LoadCommandTypes::LC_SYMSEG, + LoadCommandTypes::Symtab => LoadCommandTypes::LC_SYMTAB, + LoadCommandTypes::Thread => LoadCommandTypes::LC_THREAD, + LoadCommandTypes::TwoLevelHints => LoadCommandTypes::LC_TWOLEVEL_HINTS, + LoadCommandTypes::Unixthread => LoadCommandTypes::LC_UNIXTHREAD, + LoadCommandTypes::Uuid => LoadCommandTypes::LC_UUID, + LoadCommandTypes::VersionMinIphoneOS => LoadCommandTypes::LC_VERSION_MIN_IPHONEOS, + LoadCommandTypes::VersionMinMacOSX => LoadCommandTypes::LC_VERSION_MIN_MACOSX, + LoadCommandTypes::VersionMinTvOS => LoadCommandTypes::LC_VERSION_MIN_TVOS, + LoadCommandTypes::VersionMinWatchOS => LoadCommandTypes::LC_VERSION_MIN_WATCHOS, + LoadCommandTypes::AtomInfo => LoadCommandTypes::LC_ATOM_INFO, + LoadCommandTypes::FunctionVariants => LoadCommandTypes::LC_FUNCTION_VARIANTS, + LoadCommandTypes::FunctionVariantsFixups => { + LoadCommandTypes::LC_FUNCTION_VARIANT_FIXUPS + } + LoadCommandTypes::TargetTriple => LoadCommandTypes::LC_TARGET_TRIPLE, + LoadCommandTypes::LazyLoadDylibInfo => LoadCommandTypes::LC_LAZY_LOAD_DYLIB_INFO, + LoadCommandTypes::LiefUnknown => LoadCommandTypes::LIEF_UNKNOWN, + LoadCommandTypes::Unknown(value) => value, + } + } +} + +#[derive(Debug)] +/// Enum that wraps all the different Mach-O load commands (`LC_xxx`). +/// Note that all these commands implements the trait: [`Command`] +pub enum Commands<'a> { + Generic(Generic<'a>), + BuildVersion(BuildVersion<'a>), + CodeSignature(CodeSignature<'a>), + CodeSignatureDir(CodeSignatureDir<'a>), + DataInCode(DataInCode<'a>), + DyldChainedFixups(DyldChainedFixups<'a>), + DyldEnvironment(DyldEnvironment<'a>), + DyldExportsTrie(DyldExportsTrie<'a>), + DyldInfo(DyldInfo<'a>), + Dylib(Dylib<'a>), + Dylinker(Dylinker<'a>), + DynamicSymbolCommand(DynamicSymbolCommand<'a>), + EncryptionInfo(EncryptionInfo<'a>), + Fileset(Fileset<'a>), + FunctionStarts(FunctionStarts<'a>), + LinkerOptHint(LinkerOptHint<'a>), + Main(Main<'a>), + RPath(RPath<'a>), + Routine(Routine<'a>), + Segment(Segment<'a>), + SegmentSplitInfo(SegmentSplitInfo<'a>), + SourceVersion(SourceVersion<'a>), + SubFramework(SubFramework<'a>), + SubClient(SubClient<'a>), + SymbolCommand(SymbolCommand<'a>), + ThreadCommand(ThreadCommand<'a>), + TwoLevelHints(TwoLevelHints<'a>), + UUID(UUID<'a>), + VersionMin(VersionMin<'a>), + AtomInfo(AtomInfo<'a>), + Note(Note<'a>), + FunctionVariants(FunctionVariants<'a>), + FunctionVariantFixups(FunctionVariantFixups<'a>), + LazyLoadDylibInfo(LazyLoadDylibInfo<'a>), + Unknown(Unknown<'a>), +} + +impl FromFFI for Commands<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::MachO_Dylib::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Dylib(Dylib::from_ffi(raw)) + } else if ffi::MachO_Main::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Main(Main::from_ffi(raw)) + } else if ffi::MachO_SegmentCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Segment(Segment::from_ffi(raw)) + } else if ffi::MachO_DyldInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DyldInfo(DyldInfo::from_ffi(raw)) + } else if ffi::MachO_UUIDCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::UUID(UUID::from_ffi(raw)) + } else if ffi::MachO_Dylinker::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Dylinker(Dylinker::from_ffi(raw)) + } else if ffi::MachO_Fileset::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Fileset(Fileset::from_ffi(raw)) + } else if ffi::MachO_FunctionStarts::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::FunctionStarts(FunctionStarts::from_ffi(raw)) + } else if ffi::MachO_SourceVersion::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::SourceVersion(SourceVersion::from_ffi(raw)) + } else if ffi::MachO_ThreadCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::ThreadCommand(ThreadCommand::from_ffi(raw)) + } else if ffi::MachO_RPathCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::RPath(RPath::from_ffi(raw)) + } else if ffi::MachO_Routine::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Routine(Routine::from_ffi(raw)) + } else if ffi::MachO_SymbolCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::SymbolCommand(SymbolCommand::from_ffi(raw)) + } else if ffi::MachO_DynamicSymbolCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DynamicSymbolCommand(DynamicSymbolCommand::from_ffi(raw)) + } else if ffi::MachO_CodeSignature::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::CodeSignature(CodeSignature::from_ffi(raw)) + } else if ffi::MachO_CodeSignatureDir::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::CodeSignatureDir(CodeSignatureDir::from_ffi(raw)) + } else if ffi::MachO_DataInCode::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DataInCode(DataInCode::from_ffi(raw)) + } else if ffi::MachO_SegmentSplitInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::SegmentSplitInfo(SegmentSplitInfo::from_ffi(raw)) + } else if ffi::MachO_EncryptionInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::EncryptionInfo(EncryptionInfo::from_ffi(raw)) + } else if ffi::MachO_SubFramework::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::SubFramework(SubFramework::from_ffi(raw)) + } else if ffi::MachO_SubClient::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::SubClient(SubClient::from_ffi(raw)) + } else if ffi::MachO_DyldEnvironment::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DyldEnvironment(DyldEnvironment::from_ffi(raw)) + } else if ffi::MachO_BuildVersion::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::BuildVersion(BuildVersion::from_ffi(raw)) + } else if ffi::MachO_DyldChainedFixups::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DyldChainedFixups(DyldChainedFixups::from_ffi(raw)) + } else if ffi::MachO_DyldExportsTrie::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::DyldExportsTrie(DyldExportsTrie::from_ffi(raw)) + } else if ffi::MachO_TwoLevelHints::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::TwoLevelHints(TwoLevelHints::from_ffi(raw)) + } else if ffi::MachO_LinkerOptHint::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::LinkerOptHint(LinkerOptHint::from_ffi(raw)) + } else if ffi::MachO_VersionMin::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::VersionMin(VersionMin::from_ffi(raw)) + } else if ffi::MachO_UnknownCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Unknown(Unknown::from_ffi(raw)) + } else if ffi::MachO_AtomInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::AtomInfo(AtomInfo::from_ffi(raw)) + } else if ffi::MachO_NoteCommand::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::Note(Note::from_ffi(raw)) + } else if ffi::MachO_FunctionVariants::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::FunctionVariants(FunctionVariants::from_ffi(raw)) + } else if ffi::MachO_FunctionVariantFixups::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::FunctionVariantFixups(FunctionVariantFixups::from_ffi(raw)) + } else if ffi::MachO_LazyLoadDylibInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Commands::LazyLoadDylibInfo(LazyLoadDylibInfo::from_ffi(raw)) + } else { + Commands::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Generic").finish() + } +} + +impl FromFFI for Generic<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +/// Trait shared by **all** the load command: [`Commands`] +pub trait Command { + #[doc(hidden)] + fn get_base(&self) -> &ffi::MachO_Command; + + /// Size of the command (should be greater than ``sizeof(load_command)``) + fn size(&self) -> u32 { + self.get_base().size() + } + + /// Offset of the command within the *Load Command Table* + fn offset(&self) -> u64 { + self.get_base().command_offset() + } + + /// The command's type + fn command_type(&self) -> LoadCommandTypes { + LoadCommandTypes::from(self.get_base().cmd_type()) + } + + /// The raw command as a slice of bytes + fn data(&self) -> &[u8] { + to_slice!(self.get_base().data()); + } +} + +impl Command for Commands<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + match &self { + Commands::Generic(cmd) => cmd.get_base(), + Commands::BuildVersion(cmd) => cmd.get_base(), + Commands::CodeSignature(cmd) => cmd.get_base(), + Commands::CodeSignatureDir(cmd) => cmd.get_base(), + Commands::DataInCode(cmd) => cmd.get_base(), + Commands::DyldChainedFixups(cmd) => cmd.get_base(), + Commands::DyldEnvironment(cmd) => cmd.get_base(), + Commands::DyldExportsTrie(cmd) => cmd.get_base(), + Commands::DyldInfo(cmd) => cmd.get_base(), + Commands::Dylib(cmd) => cmd.get_base(), + Commands::Dylinker(cmd) => cmd.get_base(), + Commands::DynamicSymbolCommand(cmd) => cmd.get_base(), + Commands::EncryptionInfo(cmd) => cmd.get_base(), + Commands::FunctionStarts(cmd) => cmd.get_base(), + Commands::LinkerOptHint(cmd) => cmd.get_base(), + Commands::Main(cmd) => cmd.get_base(), + Commands::Routine(cmd) => cmd.get_base(), + Commands::RPath(cmd) => cmd.get_base(), + Commands::Segment(cmd) => cmd.get_base(), + Commands::SegmentSplitInfo(cmd) => cmd.get_base(), + Commands::SourceVersion(cmd) => cmd.get_base(), + Commands::SubFramework(cmd) => cmd.get_base(), + Commands::SubClient(cmd) => cmd.get_base(), + Commands::SymbolCommand(cmd) => cmd.get_base(), + Commands::ThreadCommand(cmd) => cmd.get_base(), + Commands::TwoLevelHints(cmd) => cmd.get_base(), + Commands::UUID(cmd) => cmd.get_base(), + Commands::VersionMin(cmd) => cmd.get_base(), + Commands::AtomInfo(cmd) => cmd.get_base(), + Commands::Note(cmd) => cmd.get_base(), + Commands::FunctionVariants(cmd) => cmd.get_base(), + Commands::FunctionVariantFixups(cmd) => cmd.get_base(), + Commands::LazyLoadDylibInfo(cmd) => cmd.get_base(), + Commands::Fileset(cmd) => cmd.get_base(), + Commands::Unknown(cmd) => cmd.get_base(), + } + } +} + +impl Command for Generic<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap() + } +} + +impl std::fmt::Debug for &dyn Command { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Command") + .field("offset", &self.offset()) + .field("size", &self.size()) + .field("type", &self.command_type()) + .field("data_len", &self.data().len()) + .finish() + } +} + +declare_iterator!( + CommandsIter, + Commands<'a>, + ffi::MachO_Command, + ffi::MachO_Binary, + ffi::MachO_Binary_it_commands +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/atom_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/atom_info.rs new file mode 100644 index 0000000..85c124f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/atom_info.rs @@ -0,0 +1,54 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure which represents the `LC_ATOM_INFO` command +pub struct AtomInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl AtomInfo<'_> { + /// Offset in the `__LINKEDIT` segment where the payload is located + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the payload + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for AtomInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("AtomInfo") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for AtomInfo<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for AtomInfo<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/build_version.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/build_version.rs new file mode 100644 index 0000000..71b02bb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/build_version.rs @@ -0,0 +1,235 @@ +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use super::Command; +use crate::common::FromFFI; +use crate::declare_iterator; + +/// Tool used during the build +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Tool { + CLANG, + SWIFT, + LD, + LLD, + METAL, + AIRLLD, + AIRNT, + AIRNT_PLUGIN, + AIRPACK, + GPUARCHIVER, + METAL_FRAMEWORK, + UNKNOWN(u32), +} + +impl From for Tool { + fn from(value: u32) -> Self { + match value { + 1 => Tool::CLANG, + 2 => Tool::SWIFT, + 3 => Tool::LD, + 4 => Tool::LLD, + 1024 => Tool::METAL, + 1025 => Tool::AIRLLD, + 1026 => Tool::AIRNT, + 1027 => Tool::AIRNT_PLUGIN, + 1028 => Tool::AIRPACK, + 1031 => Tool::GPUARCHIVER, + 1032 => Tool::METAL_FRAMEWORK, + _ => Tool::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Tool) -> u32 { + match value { + Tool::CLANG => 1, + Tool::SWIFT => 2, + Tool::LD => 3, + Tool::LLD => 4, + Tool::METAL => 1024, + Tool::AIRLLD => 1025, + Tool::AIRNT => 1026, + Tool::AIRNT_PLUGIN => 1027, + Tool::AIRPACK => 1028, + Tool::GPUARCHIVER => 1031, + Tool::METAL_FRAMEWORK => 1032, + Tool::UNKNOWN(v) => v, + } + } +} + +/// Represents a tool version used during the build +pub struct BuildToolVersion<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_BuildVersion>, +} + +impl BuildToolVersion<'_> { + /// The tool used + pub fn tool(&self) -> Tool { + Tool::from(self.ptr.tool()) + } + + /// Version associated with the tool + pub fn version(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.version().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } +} + +impl std::fmt::Debug for BuildToolVersion<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("BuildToolVersion") + .field("tool", &self.tool()) + .field("version", &self.version()) + .finish() + } +} + +impl<'a> FromFFI for BuildToolVersion<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure that represents the `LC_BUILD_VERSION` command +pub struct BuildVersion<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Platform { + MACOS, + IOS, + TVOS, + WATCHOS, + BRIDGEOS, + MAC_CATALYST, + IOS_SIMULATOR, + TVOS_SIMULATOR, + WATCHOS_SIMULATOR, + DRIVERKIT, + VISIONOS, + VISIONOS_SIMULATOR, + FIRMWARE, + SEPOS, + MACOS_EXCLAVE_CORE, + MACOS_EXCLAVE_KIT, + IOS_EXCLAVE_CORE, + IOS_EXCLAVE_KIT, + TVOS_EXCLAVE_CORE, + TVOS_EXCLAVE_KIT, + WATCHOS_EXCLAVE_CORE, + WATCHOS_EXCLAVE_KIT, + VISIONOS_EXCLAVE_CORE, + VISIONOS_EXCLAVE_KIT, + ANY, + UNKNOWN(u32), +} + +impl From for Platform { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Platform::MACOS, + 0x00000002 => Platform::IOS, + 0x00000003 => Platform::TVOS, + 0x00000004 => Platform::WATCHOS, + 0x00000005 => Platform::BRIDGEOS, + 0x00000006 => Platform::MAC_CATALYST, + 0x00000007 => Platform::IOS_SIMULATOR, + 0x00000008 => Platform::TVOS_SIMULATOR, + 0x00000009 => Platform::WATCHOS_SIMULATOR, + 0x0000000A => Platform::DRIVERKIT, + 0x0000000B => Platform::VISIONOS, + 0x0000000C => Platform::VISIONOS_SIMULATOR, + 0x0000000D => Platform::FIRMWARE, + 0x0000000E => Platform::SEPOS, + 0x0000000F => Platform::MACOS_EXCLAVE_CORE, + 0x00000010 => Platform::MACOS_EXCLAVE_KIT, + 0x00000011 => Platform::IOS_EXCLAVE_CORE, + 0x00000012 => Platform::IOS_EXCLAVE_KIT, + 0x00000013 => Platform::TVOS_EXCLAVE_CORE, + 0x00000014 => Platform::TVOS_EXCLAVE_KIT, + 0x00000015 => Platform::WATCHOS_EXCLAVE_CORE, + 0x00000016 => Platform::WATCHOS_EXCLAVE_KIT, + 0x00000017 => Platform::VISIONOS_EXCLAVE_CORE, + 0x00000018 => Platform::VISIONOS_EXCLAVE_KIT, + 0xFFFFFFFF => Platform::ANY, + _ => Platform::UNKNOWN(value), + } + } +} + +impl BuildVersion<'_> { + pub fn sdk(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.sdk().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } + + pub fn minos(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.sdk().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } + + pub fn platform(&self) -> Platform { + Platform::from(self.ptr.platform()) + } + + /// Return an iterator over the [`BuildToolVersion`] entries + pub fn tools(&self) -> BuildTools<'_> { + BuildTools::new(self.ptr.tools()) + } +} + +impl std::fmt::Debug for BuildVersion<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("BuildVersion") + .field("base", &base) + .field("sdk", &self.sdk()) + .field("minos", &self.minos()) + .field("platform", &self.platform()) + .finish() + } +} + +impl FromFFI for BuildVersion<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for BuildVersion<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + BuildTools, + BuildToolVersion<'a>, + ffi::MachO_BuildToolVersion, + ffi::MachO_BuildVersion, + ffi::MachO_BuildVersion_it_tools +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature.rs new file mode 100644 index 0000000..5cf64d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature.rs @@ -0,0 +1,55 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::to_slice; +use std::marker::PhantomData; + +/// Structure that represents the `LC_CODE_SIGNATURE` command +pub struct CodeSignature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl CodeSignature<'_> { + /// Offset in the binary where the signature starts + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the raw signature + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Content of the signature as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for CodeSignature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("CodeSignature") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for CodeSignature<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for CodeSignature<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature_dir.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature_dir.rs new file mode 100644 index 0000000..8b94897 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/code_signature_dir.rs @@ -0,0 +1,55 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::to_slice; +use std::marker::PhantomData; + +/// Structure that represents the `LC_DYLIB_CODE_SIGN_DRS` command +pub struct CodeSignatureDir<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl CodeSignatureDir<'_> { + /// Offset in the binary where the signature starts + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the raw signature + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Content of the signature as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for CodeSignatureDir<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("CodeSignatureDir") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for CodeSignatureDir<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for CodeSignatureDir<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/data_in_code.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/data_in_code.rs new file mode 100644 index 0000000..efa193b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/data_in_code.rs @@ -0,0 +1,135 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::to_slice; +use crate::{common::FromFFI, declare_iterator}; +use std::marker::PhantomData; + +/// Structure that represents the `LC_DATA_IN_CODE` command +/// +/// This command is used to list slices of code sections that contain data. The *slices* +/// information are stored as an array of [`DataCodeEntry`] +pub struct DataInCode<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl DataInCode<'_> { + /// Start of the array of the [`DataCodeEntry`] entries + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the (raw) array (`size = sizeof(DataCodeEntry) * nb_elements`) + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw content as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Iterator over the [`DataCodeEntry`] + pub fn entries(&self) -> Entries<'_> { + Entries::new(self.ptr.entries()) + } +} + +impl std::fmt::Debug for DataInCode<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DataInCode") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for DataInCode<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for DataInCode<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +pub struct DataCodeEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_DataInCode>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum EntryType { + DATA, + JUMP_TABLE_8, + JUMP_TABLE_16, + JUMP_TABLE_32, + ABS_JUMP_TABLE_32, + UNKNOWN(u32), +} + +impl From for EntryType { + fn from(value: u32) -> Self { + match value { + 0x00000001 => EntryType::DATA, + 0x00000002 => EntryType::JUMP_TABLE_8, + 0x00000003 => EntryType::JUMP_TABLE_16, + 0x00000004 => EntryType::JUMP_TABLE_32, + 0x00000005 => EntryType::ABS_JUMP_TABLE_32, + _ => EntryType::UNKNOWN(value), + } + } +} + +impl DataCodeEntry<'_> { + /// Offset of the data + pub fn offset(&self) -> u32 { + self.ptr.offset() + } + /// Length of the data + pub fn length(&self) -> u32 { + self.ptr.length() + } + + /// Type of the data + pub fn get_type(&self) -> EntryType { + EntryType::from(self.ptr.get_type()) + } +} + +impl std::fmt::Debug for DataCodeEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DataCodeEntry") + .field("offset", &self.offset()) + .field("length", &self.length()) + .field("type", &self.get_type()) + .finish() + } +} + +impl FromFFI for DataCodeEntry<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + Entries, + DataCodeEntry<'a>, + ffi::MachO_DataCodeEntry, + ffi::MachO_DataInCode, + ffi::MachO_DataInCode_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_chained_fixups.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_chained_fixups.rs new file mode 100644 index 0000000..6dd3157 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_chained_fixups.rs @@ -0,0 +1,122 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::macho::binding_info::{CHAINED_FORMAT, Chained}; +use crate::to_slice; +use crate::{common::FromFFI, declare_iterator}; +use std::marker::PhantomData; + +/// Structure that represents the `LC_DYLD_CHAINED_FIXUPS` command +/// +/// This command aims at providing rebase and binding information like +/// the DyldInfo's bytecode. Compared to the DyldInfo bytecode, these chained +/// fixups are taking less space. +pub struct DyldChainedFixups<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl std::fmt::Debug for DyldChainedFixups<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DyldChainedFixups") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .field("fixups_version", &self.fixups_version()) + .field("starts_offset", &self.starts_offset()) + .field("imports_offset", &self.imports_offset()) + .field("symbols_offset", &self.symbols_offset()) + .field("imports_count", &self.imports_count()) + .field("symbols_format", &self.symbols_format()) + .field("imports_format", &self.imports_format()) + .finish() + } +} + +impl DyldChainedFixups<'_> { + /// Offset of the `LC_DYLD_CHAINED_FIXUPS` chained payload. + /// This offset should point in the `__LINKEDIT` segment + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the `LC_DYLD_CHAINED_FIXUPS` payload. + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Chained fixups version. The loader (dyld v852.2) checks + /// that this value is set to 0 + pub fn fixups_version(&self) -> u32 { + self.ptr.fixups_version() + } + + /// offset of `dyld_chained_starts_in_image` in chain_data + pub fn starts_offset(&self) -> u32 { + self.ptr.starts_offset() + } + + /// Offset of imports table in chain data + pub fn imports_offset(&self) -> u32 { + self.ptr.imports_offset() + } + + /// Offset of symbol strings in chain data + pub fn symbols_offset(&self) -> u32 { + self.ptr.symbols_offset() + } + + /// Number of imported symbol names + pub fn imports_count(&self) -> u32 { + self.ptr.imports_count() + } + + /// The compression algorithm (if any) used to store the symbols + /// 0 means uncompressed while 1 means zlib compressed. + /// + /// As far of the version v852.2 of dyld loader, it only supports + /// **uncompressed** format + pub fn symbols_format(&self) -> u32 { + self.ptr.symbols_format() + } + + /// The format of the imports + pub fn imports_format(&self) -> CHAINED_FORMAT { + CHAINED_FORMAT::from_value(self.ptr.imports_format()) + } + + /// Iterator over the bindings [`crate::macho::BindingInfo::Chained`] + /// associated with this command + pub fn bindings(&self) -> Bindings<'_> { + Bindings::new(self.ptr.bindings()) + } + + /// Return the raw content of the command + pub fn payload(&self) -> &[u8] { + to_slice!(self.ptr.payload()); + } +} + +impl FromFFI for DyldChainedFixups<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for DyldChainedFixups<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + Bindings, + Chained<'a>, + ffi::MachO_ChainedBindingInfo, + ffi::MachO_DyldChainedFixups, + ffi::MachO_DyldChainedFixups_it_bindings +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_environment.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_environment.rs new file mode 100644 index 0000000..30a935d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_environment.rs @@ -0,0 +1,44 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// Structure that represents a `LC_DYLD_ENVIRONMENT` command which is +/// used by the Mach-O linker/loader to initialize an environment variable +pub struct DyldEnvironment<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl DyldEnvironment<'_> { + /// The actual environment variable + pub fn value(&self) -> String { + self.ptr.value().to_string() + } +} + +impl std::fmt::Debug for DyldEnvironment<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DyldEnvironment") + .field("base", &base) + .field("value", &self.value()) + .finish() + } +} + +impl FromFFI for DyldEnvironment<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for DyldEnvironment<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_export_trie.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_export_trie.rs new file mode 100644 index 0000000..010ac27 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyld_export_trie.rs @@ -0,0 +1,73 @@ +use super::Command; +use crate::common::FromFFI; +use crate::macho::export_info::ExportInfo; +use crate::to_slice; +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::declare_iterator; + +/// Structure that represents the `LC_DYLD_EXPORTS_TRIE` command +/// +/// In recent Mach-O binaries, this command replace the DyldInfo export trie buffer +pub struct DyldExportsTrie<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl DyldExportsTrie<'_> { + /// Offset of the `LC_DYLD_EXPORTS_TRIE`. This offset should point in the + /// `__LINKEDIT` segment + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the `LC_DYLD_EXPORTS_TRIE` payload. + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Iterator over the [`crate::macho::ExportInfo`] associated with this command + pub fn exports(&self) -> ExportInfos<'_> { + ExportInfos::new(self.ptr.exports()) + } +} + +impl std::fmt::Debug for DyldExportsTrie<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DyldExportsTrie") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for DyldExportsTrie<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for DyldExportsTrie<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + ExportInfos, + ExportInfo<'a>, + ffi::MachO_ExportInfo, + ffi::MachO_DyldExportsTrie, + ffi::MachO_DyldExportsTrie_it_exports +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dyldinfo.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyldinfo.rs new file mode 100644 index 0000000..5575066 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dyldinfo.rs @@ -0,0 +1,98 @@ +use super::Command; +use crate::common::FromFFI; +use crate::macho::binding_info::Dyld; +use crate::macho::{BindingInfo, ExportInfo}; +use std::marker::PhantomData; + +use crate::{declare_iterator, declare_iterator_conv, to_slice}; + +use lief_ffi as ffi; + +/// Structure that represents the `LC_DYLD_INFO` and `LC_DYLD_INFO_ONLY` commands +pub struct DyldInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl std::fmt::Debug for DyldInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DyldInfo") + .field("base", &base) + .field("rebase_opcodes", &self.rebase_opcodes().is_empty()) + .field("bind_opcodes", &self.bind_opcodes().is_empty()) + .field("weak_bind_opcodes", &self.weak_bind_opcodes().is_empty()) + .field("lazy_bind_opcodes", &self.lazy_bind_opcodes().is_empty()) + .field("export_trie", &self.export_trie().is_empty()) + .finish() + } +} + +impl FromFFI for DyldInfo<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl<'a> DyldInfo<'a> { + /// Return Rebase's opcodes as a slice of bytes + pub fn rebase_opcodes(&self) -> &[u8] { + to_slice!(self.ptr.rebase_opcodes()); + } + + /// Return **regular** binding's opcodes as a slice of bytes + pub fn bind_opcodes(&self) -> &[u8] { + to_slice!(self.ptr.bind_opcodes()); + } + + /// Return **weak** binding's opcodes as a slice of bytes + pub fn weak_bind_opcodes(&self) -> &[u8] { + to_slice!(self.ptr.weak_bind_opcodes()); + } + + /// Return **lazy** binding's opcodes as a slice of bytes + pub fn lazy_bind_opcodes(&self) -> &[u8] { + to_slice!(self.ptr.lazy_bind_opcodes()); + } + + /// Return the raw export trie as a slice of bytes + pub fn export_trie(&self) -> &[u8] { + to_slice!(self.ptr.export_trie()); + } + + /// Return an iterator over the [`crate::macho::BindingInfo::Dyld`] associated with this + /// command + pub fn bindings(&self) -> BindingInfos<'_> { + BindingInfos::new(self.ptr.bindings()) + } + + /// Return an iterator over the [`crate::macho::ExportInfo`] associated with this command + pub fn exports(&self) -> ExportInfos<'_> { + ExportInfos::new(self.ptr.exports()) + } +} + +impl Command for DyldInfo<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator_conv!( + BindingInfos, + BindingInfo<'a>, + ffi::MachO_BindingInfo, + ffi::MachO_DyldInfo, + ffi::MachO_DyldInfo_it_bindings, + |n| BindingInfo::Dyld(Dyld::from_ffi(n)) +); +declare_iterator!( + ExportInfos, + ExportInfo<'a>, + ffi::MachO_ExportInfo, + ffi::MachO_DyldInfo, + ffi::MachO_DyldInfo_it_exports +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dylib.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dylib.rs new file mode 100644 index 0000000..66a0cf7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dylib.rs @@ -0,0 +1,162 @@ +use super::Command; +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_iterator; +use std::marker::PhantomData; + +/// Structure which represents a library dependency +pub struct Dylib<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Dylib<'_> { + /// Library name + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } + + /// Create a new ID_DYLIB command + pub fn id_dylib(name: &str, timestamp: u32, current_version: u32, compat_version: u32) -> Self { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Self::from_ffi(ffi::MachO_Dylib::id_dylib( + &__cxx_s, + timestamp, + current_version, + compat_version, + )) + } + + /// Create a new LOAD_DYLIB command + pub fn load_dylib( + name: &str, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> Self { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Self::from_ffi(ffi::MachO_Dylib::load_dylib( + &__cxx_s, + timestamp, + current_version, + compat_version, + )) + } + + /// Create a new REEXPORT_DYLIB command + pub fn reexport_dylib( + name: &str, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> Self { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Self::from_ffi(ffi::MachO_Dylib::reexport_dylib( + &__cxx_s, + timestamp, + current_version, + compat_version, + )) + } + + /// Create a new WEAK_DYLIB command + pub fn weak_dylib( + name: &str, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> Self { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Self::from_ffi(ffi::MachO_Dylib::weak_dylib( + &__cxx_s, + timestamp, + current_version, + compat_version, + )) + } + + /// Create a new LAZY_LOAD_DYLIB command + pub fn lazy_load_dylib( + name: &str, + timestamp: u32, + current_version: u32, + compat_version: u32, + ) -> Self { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Self::from_ffi(ffi::MachO_Dylib::lazy_load_dylib( + &__cxx_s, + timestamp, + current_version, + compat_version, + )) + } + + /// Original string offset of the name + pub fn name_offset(&self) -> u32 { + self.ptr.name_offset() + } + + /// Date and Time when the shared library was built + pub fn timestamp(&self) -> u32 { + self.ptr.timestamp() + } + + /// Current version of the shared library + pub fn current_version(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.current_version().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } + /// Compatibility version of the shared library + pub fn compatibility_version(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.compatibility_version().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } +} + +impl std::fmt::Debug for Dylib<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Dylib") + .field("base", &base) + .field("name", &self.name()) + .field("timestamp", &self.timestamp()) + .field("current_version", &self.current_version()) + .field("compatibility_version", &self.compatibility_version()) + .finish() + } +} + +impl FromFFI for Dylib<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Dylib<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + Libraries, + Dylib<'a>, + ffi::MachO_Dylib, + ffi::MachO_Binary, + ffi::MachO_Binary_it_libraries +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dylinker.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dylinker.rs new file mode 100644 index 0000000..27fadb0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dylinker.rs @@ -0,0 +1,43 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure that represents the Mach-O linker, also named loader. +/// Most of the time, [`Dylinker::name`] should return `/usr/lib/dyld` +pub struct Dylinker<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl std::fmt::Debug for Dylinker<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Dylinker") + .field("base", &base) + .field("name", &self.name()) + .finish() + } +} + +impl Dylinker<'_> { + /// Path to the linker (or loader) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } +} + +impl FromFFI for Dylinker<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Dylinker<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/dynamic_symbol_command.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/dynamic_symbol_command.rs new file mode 100644 index 0000000..b5f59e6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/dynamic_symbol_command.rs @@ -0,0 +1,206 @@ +use super::Command; +use crate::common::FromFFI; +use crate::macho::Symbol; +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::declare_iterator; + +/// Structure that represents the `LC_DYSYMTAB` command. +/// +/// This command completes the `LC_SYMTAB` to provide +/// a better granularity over the symbols layout. +pub struct DynamicSymbolCommand<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl DynamicSymbolCommand<'_> { + /// Index of the first symbol in the group of local symbols. + pub fn idx_local_symbol(&self) -> u32 { + self.ptr.idx_local_symbol() + } + + /// Number of symbols in the group of local symbols. + pub fn nb_local_symbols(&self) -> u32 { + self.ptr.nb_local_symbols() + } + + /// Index of the first symbol in the group of defined external symbols. + pub fn idx_external_define_symbol(&self) -> u32 { + self.ptr.idx_external_define_symbol() + } + + /// Number of symbols in the group of defined external symbols. + pub fn nb_external_define_symbols(&self) -> u32 { + self.ptr.nb_external_define_symbols() + } + + /// Index of the first symbol in the group of undefined external symbols. + pub fn idx_undefined_symbol(&self) -> u32 { + self.ptr.idx_undefined_symbol() + } + + /// Number of symbols in the group of undefined external symbols. + pub fn nb_undefined_symbols(&self) -> u32 { + self.ptr.nb_undefined_symbols() + } + + /// Byte offset from the start of the file to the table of contents data + /// + /// Table of content is used by legacy Mach-O loader and this field should be + /// set to 0 + pub fn toc_offset(&self) -> u32 { + self.ptr.toc_offset() + } + + /// Number of entries in the table of contents. + /// + /// Should be set to 0 on recent Mach-O + pub fn nb_toc(&self) -> u32 { + self.ptr.nb_toc() + } + + /// Byte offset from the start of the file to the module table data. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn module_table_offset(&self) -> u32 { + self.ptr.module_table_offset() + } + + /// Number of entries in the module table. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn nb_module_table(&self) -> u32 { + self.ptr.nb_module_table() + } + + /// Byte offset from the start of the file to the external reference table data. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn external_reference_symbol_offset(&self) -> u32 { + self.ptr.external_reference_symbol_offset() + } + + /// Number of entries in the external reference table + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn nb_external_reference_symbols(&self) -> u32 { + self.ptr.nb_external_reference_symbols() + } + + /// Byte offset from the start of the file to the indirect symbol table data. + /// + /// Indirect symbol table is used by the loader to speed-up symbol resolution during + /// the *lazy binding* process + /// + /// References: + /// * dyld-519.2.1/src/ImageLoaderMachOCompressed.cpp + /// * dyld-519.2.1/src/ImageLoaderMachOClassic.cpp + pub fn indirect_symbol_offset(&self) -> u32 { + self.ptr.indirect_symbol_offset() + } + + /// Number of entries in the indirect symbol table. + pub fn nb_indirect_symbols(&self) -> u32 { + self.ptr.nb_indirect_symbols() + } + + /// Byte offset from the start of the file to the external relocation table data. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn external_relocation_offset(&self) -> u32 { + self.ptr.external_relocation_offset() + } + + /// Number of entries in the external relocation table. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn nb_external_relocations(&self) -> u32 { + self.ptr.nb_external_relocations() + } + + /// Byte offset from the start of the file to the local relocation table data. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn local_relocation_offset(&self) -> u32 { + self.ptr.local_relocation_offset() + } + + /// Number of entries in the local relocation table. + /// + /// This field seems unused by recent Mach-O loader and should be set to 0 + pub fn nb_local_relocations(&self) -> u32 { + self.ptr.nb_local_relocations() + } + + /// Iterator over the indirect symbols indexed by this command + pub fn indirect_symbols(&self) -> IndirectSymbols<'_> { + IndirectSymbols::new(self.ptr.indirect_symbols()) + } +} + +impl std::fmt::Debug for DynamicSymbolCommand<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("DynamicSymbolCommand") + .field("base", &base) + .field("idx_local_symbol", &self.idx_local_symbol()) + .field("nb_local_symbols", &self.nb_local_symbols()) + .field( + "idx_external_define_symbol", + &self.idx_external_define_symbol(), + ) + .field( + "nb_external_define_symbols", + &self.nb_external_define_symbols(), + ) + .field("idx_undefined_symbol", &self.idx_undefined_symbol()) + .field("nb_undefined_symbols", &self.nb_undefined_symbols()) + .field("toc_offset", &self.toc_offset()) + .field("nb_toc", &self.nb_toc()) + .field("module_table_offset", &self.module_table_offset()) + .field("nb_module_table", &self.nb_module_table()) + .field( + "external_reference_symbol_offset", + &self.external_reference_symbol_offset(), + ) + .field( + "nb_external_reference_symbols", + &self.nb_external_reference_symbols(), + ) + .field("indirect_symbol_offset", &self.indirect_symbol_offset()) + .field("nb_indirect_symbols", &self.nb_indirect_symbols()) + .field( + "external_relocation_offset", + &self.external_relocation_offset(), + ) + .field("nb_external_relocations", &self.nb_external_relocations()) + .field("local_relocation_offset", &self.local_relocation_offset()) + .field("nb_local_relocations", &self.nb_local_relocations()) + .finish() + } +} + +impl FromFFI for DynamicSymbolCommand<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for DynamicSymbolCommand<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + IndirectSymbols, + Symbol<'a>, + ffi::MachO_Symbol, + ffi::MachO_DynamicSymbolCommand, + ffi::MachO_DynamicSymbolCommand_it_indirect_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/encryption_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/encryption_info.rs new file mode 100644 index 0000000..f862773 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/encryption_info.rs @@ -0,0 +1,57 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure that represents the LC_ENCRYPTION_INFO / LC_ENCRYPTION_INFO_64 commands +/// +/// The encryption info is usually present in Mach-O executables that +/// target iOS to encrypt some sections of the binary +pub struct EncryptionInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl EncryptionInfo<'_> { + /// The beginning of the encrypted area + pub fn crypt_offset(&self) -> u32 { + self.ptr.crypt_offset() + } + + /// The size of the encrypted area + pub fn crypt_size(&self) -> u32 { + self.ptr.crypt_size() + } + + /// The encryption system. 0 means no encrypted + pub fn crypt_id(&self) -> u32 { + self.ptr.crypt_id() + } +} + +impl std::fmt::Debug for EncryptionInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("EncryptionInfo") + .field("base", &base) + .field("crypt_id", &self.crypt_id()) + .field("crypt_offset", &self.crypt_offset()) + .field("crypt_size", &self.crypt_size()) + .finish() + } +} + +impl FromFFI for EncryptionInfo<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for EncryptionInfo<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/fileset.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/fileset.rs new file mode 100644 index 0000000..d058b4d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/fileset.rs @@ -0,0 +1,50 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::marker::PhantomData; + +pub struct Fileset<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Fileset<'_> { + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn virtual_address(&self) -> u64 { + self.ptr.virtual_address() + } + + pub fn file_offset(&self) -> u64 { + self.ptr.file_offset() + } +} + +impl std::fmt::Debug for Fileset<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Note") + .field("base", &base) + .field("name", &self.name()) + .field("virtual_address", &self.virtual_address()) + .field("file_offset", &self.file_offset()) + .finish() + } +} + +impl<'a> FromFFI for Fileset<'a> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Fileset<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variant_fixups.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variant_fixups.rs new file mode 100644 index 0000000..02ff637 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variant_fixups.rs @@ -0,0 +1,155 @@ +use super::Command; +use super::Segment; +use crate::common::{FromFFI, into_optional}; +use crate::{declare_iterator, to_slice}; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure which represents the `LC_FUNCTION_VARIANT_FIXUPS` command. +/// +/// This command contains the relocations that must be applied to the GOT-like +/// slots associated with a [`crate::macho::commands::FunctionVariants`] table. +/// At runtime, `dyld` resolves each slot to the best implementation and +/// (re-)signs it according to the pointer-authentication information. +pub struct FunctionVariantFixups<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl FunctionVariantFixups<'_> { + /// Offset in the `__LINKEDIT` segment where the payload is located + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the payload + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Iterator over the different [`Fixup`] entries + pub fn fixups(&self) -> Fixups<'_> { + Fixups::new(self.ptr.fixups()) + } +} + +impl std::fmt::Debug for FunctionVariantFixups<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("FunctionVariantFixups") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for FunctionVariantFixups<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for FunctionVariantFixups<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// A single relocation associated with a function-variant. It mirrors the +/// `FunctionVariantFixups::InternalFixup` structure used by `dyld` and +/// describes a slot that must be fixed up to point to the variant referenced by +/// [`Fixup::variant_index`]. +pub struct Fixup<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_FunctionVariantFixups>, +} + +impl FromFFI for Fixup<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Fixup<'_> { + /// Offset of the slot to fix up, relative to the segment designated by + /// [`Fixup::seg_index`] + pub fn seg_offset(&self) -> u32 { + self.ptr.seg_offset() + } + + /// Index of the segment that owns the slot to fix up + pub fn seg_index(&self) -> u32 { + self.ptr.seg_index() + } + + /// Index of the FunctionVariants runtime table used to resolve the slot + pub fn variant_index(&self) -> u32 { + self.ptr.variant_index() + } + + /// Whether the slot is signed with pointer authentication (arm64e) + pub fn pac_auth(&self) -> bool { + self.ptr.pac_auth() + } + + /// Whether the pointer-authentication signature mixes the storage address + /// (address diversity) + pub fn pac_address(&self) -> bool { + self.ptr.pac_address() + } + + /// Pointer-authentication key used to sign the slot + pub fn pac_key(&self) -> u8 { + self.ptr.pac_key() + } + + /// Pointer-authentication diversity (discriminator) of the slot + pub fn pac_diversity(&self) -> u16 { + self.ptr.pac_diversity() + } + + /// [`Segment`] referenced by [`Fixup::seg_index`] if it could be resolved + pub fn segment(&self) -> Option> { + into_optional(self.ptr.segment()) + } +} + +impl std::fmt::Debug for Fixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Fixup") + .field("seg_offset", &self.seg_offset()) + .field("seg_index", &self.seg_index()) + .field("variant_index", &self.variant_index()) + .field("pac_auth", &self.pac_auth()) + .field("pac_address", &self.pac_address()) + .field("pac_key", &self.pac_key()) + .field("pac_diversity", &self.pac_diversity()) + .finish() + } +} + +impl std::fmt::Display for Fixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_iterator!( + Fixups, + Fixup<'a>, + ffi::MachO_FunctionVariantFixups_Fixup, + ffi::MachO_FunctionVariantFixups, + ffi::MachO_FunctionVariantFixups_it_fixups +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variants.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variants.rs new file mode 100644 index 0000000..64ceddf --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/function_variants.rs @@ -0,0 +1,490 @@ +use super::Command; +use crate::common::FromFFI; +use crate::{declare_iterator, to_slice}; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Class representing the `LC_FUNCTION_VARIANTS` load command. +/// +/// Introduced publicly in `dyld-1284.13` (April 2025), this command supports +/// **function multiversioning**, the ability to associate multiple implementations +/// of the same function, each optimized for a specific platform, architecture, +/// or runtime context. +/// +/// At runtime, the system dispatches the most appropriate variant based on +/// hardware capabilities or execution environment. +/// +/// For example: +/// +/// ```cpp +/// FUNCTION_VARIANT_TABLE(my_function, +/// { (void*)my_function$Rosetta, "rosetta" }, // Rosetta translation +/// { (void*)my_function$Haswell, "haswell" }, // Haswell-optimized +/// { (void*)my_function$Base, "default" } // Default fallback +/// ); +/// ``` +pub struct FunctionVariants<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl FunctionVariants<'_> { + /// Offset in the `__LINKEDIT` segment where the payload is located + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the payload + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Iterator over the different [`RuntimeTable`] entries located in the content + /// of this `__LINKEDIT` command + pub fn runtime_table(&self) -> RuntimeTables<'_> { + RuntimeTables::new(self.ptr.runtime_table()) + } +} + +impl std::fmt::Debug for FunctionVariants<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("FunctionVariants") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for FunctionVariants<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for FunctionVariants<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Represents a runtime table of function variants sharing a common namespace +/// (referred to internally as `FunctionVariantsRuntimeTable` in `dyld`). +/// +/// Each table holds multiple [`RuntimeTableEntry`] instances that map to +/// function implementations optimized for a given [`Kind`]. +pub struct RuntimeTable<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_FunctionVariants>, +} + +impl FromFFI for RuntimeTable<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl RuntimeTable<'_> { + /// Kind of this runtime table + pub fn kind(&self) -> Kind { + Kind::from(self.ptr.kind()) + } + + /// Original offset in the payload + pub fn offset(&self) -> u32 { + self.ptr.offset() + } + + /// Iterator over the different [`RuntimeTableEntry`] entries + pub fn entries(&self) -> RuntimeTableEntries<'_> { + RuntimeTableEntries::new(self.ptr.entries()) + } +} + +impl std::fmt::Debug for RuntimeTable<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RuntimeTable") + .field("kind", &self.kind()) + .field("offset", &self.offset()) + .finish() + } +} + +impl std::fmt::Display for RuntimeTable<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// Enumeration describing the namespace or category of a function variant. +/// +/// Each [`RuntimeTable`] is associated with one [`Kind`], +/// which indicates the domain or context under which its variant entries +/// should be considered valid or applicable. +/// +/// These categories map to the runtime dispatch logic used by `dyld` +/// when selecting the optimal function variant. +pub enum Kind { + /// Variants that apply on a per-process basis + PER_PROCESS, + + /// Variants that are selected based on system-wide capabilities or configurations. + SYSTEM_WIDE, + + /// Variants optimized for the ARM64 architecture. + ARM64, + + /// Variants optimized for the x86-64 architecture. + X86_64, + + /// Fallback/default kind when the category is not recognized. + UNKNOWN(u32), +} + +impl From for Kind { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Kind::PER_PROCESS, + 0x00000002 => Kind::SYSTEM_WIDE, + 0x00000003 => Kind::ARM64, + 0x00000004 => Kind::X86_64, + _ => Kind::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Kind) -> u32 { + match value { + Kind::PER_PROCESS => 0x00000001, + Kind::SYSTEM_WIDE => 0x00000002, + Kind::ARM64 => 0x00000003, + Kind::X86_64 => 0x00000004, + Kind::UNKNOWN(value) => value, + } + } +} + +/// This class exposes information about a given implementation. +pub struct RuntimeTableEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_FunctionVariants_RuntimeTable>, +} + +impl FromFFI for RuntimeTableEntry<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl RuntimeTableEntry<'_> { + /// The relative address of the implementation or an index if [`RuntimeTableEntry::another_table`] is set. + pub fn implementation(&self) -> u32 { + self.ptr.implementation() + } + + /// Indicates whether [`RuntimeTableEntry::implementation`] refers to an entry in another runtime table, + /// rather than a direct function implementation address. + pub fn another_table(&self) -> bool { + self.ptr.another_table() + } + + /// The `flagBitNums` value as a slice of bytes + pub fn flag_bit_nums(&self) -> &[u8] { + to_slice!(self.ptr.flag_bit_nums()); + } + + /// Return the **interpreted** [`RuntimeTableEntry::flag_bit_nums`] + pub fn flags(&self) -> Vec { + let vec = Vec::from(self.ptr.flags().as_slice()); + vec.iter().map(|e| Flag::from(*e)).collect() + } +} + +impl std::fmt::Debug for RuntimeTableEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RuntimeTableEntry") + .field("implementation", &self.implementation()) + .field("another_table", &self.another_table()) + .field("flag_bit_nums", &self.flag_bit_nums()) + .field("flags", &self.flags()) + .finish() + } +} + +impl std::fmt::Display for RuntimeTableEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// Flags describing the target platform, environment, or architecture +/// for a given function implementation. +/// +/// These are encoded as a `uint32_t`, where high bits determine the namespace +/// ([`Kind`]), and the lower bits encode the specific capability. +pub enum Flag { + ARM64_DEFAULT, + ARM64_FLAGM, + ARM64_FLAGM2, + ARM64_FHM, + ARM64_DOTPROD, + ARM64_SHA3, + ARM64_RDM, + ARM64_LSE, + ARM64_SHA256, + ARM64_SHA512, + ARM64_SHA1, + ARM64_AES, + ARM64_PMULL, + ARM64_SPECRES, + ARM64_SB, + ARM64_FRINTTS, + ARM64_LRCPC, + ARM64_LRCPC2, + ARM64_FCMA, + ARM64_JSCVT, + ARM64_PAUTH, + ARM64_PAUTH2, + ARM64_FPAC, + ARM64_DPB, + ARM64_DPB2, + ARM64_BF16, + ARM64_I8MM, + ARM64_WFXT, + ARM64_RPRES, + ARM64_ECV, + ARM64_AFP, + ARM64_LSE2, + ARM64_CSV2, + ARM64_CVS3, + ARM64_DIT, + ARM64_FP16, + ARM64_SSBS, + ARM64_BTI, + ARM64_SME, + ARM64_SME2, + ARM64_SMEF64F64, + ARM64_SMEI16I64, + ARM64_SMEF32F32, + ARM64_SMEBI32I32, + ARM64_SMEB16F32, + ARM64_SMEF16F32, + ARM64_SMEI8I32, + ARM64_SMEI16I32, + ARM64_ADVSIMD, + ARM64_ADVSIMDHPFP, + ARM64_CRC32, + X86_64_DEFAULT, + X86_64_SSE41, + X86_64_FMA, + X86_64_AVX, + X86_64_AVX2, + X86_64_AVX512F, + X86_64_AVX512BW, + X86_64_BMI1, + X86_64_ROSETTA, + X86_64_HASWELL, + X86_64_IVYBRIDGE, + X86_64_NEHALEM, + SYSTEM_WIDE_DEFAULT, + SYSTEM_WIDE_INTERNAL_INSTALL, + SYSTEM_WIDE_CUSTOMER_INSTALL, + SYSTEM_WIDE_LOCKDOWN, + PER_PROCESS_DEFAULT, + PER_PROCESS_TRANSLATED, + PER_PROCESS_MTE_ENABLED, + PER_PROCESS_NO_OVERREAD, + UNKNOWN(u32), +} + +impl From for Flag { + fn from(value: u32) -> Self { + match value { + 0x00300000 => Flag::ARM64_DEFAULT, + 0x00300001 => Flag::ARM64_FLAGM, + 0x00300002 => Flag::ARM64_FLAGM2, + 0x00300003 => Flag::ARM64_FHM, + 0x00300004 => Flag::ARM64_DOTPROD, + 0x00300005 => Flag::ARM64_SHA3, + 0x00300006 => Flag::ARM64_RDM, + 0x00300007 => Flag::ARM64_LSE, + 0x00300008 => Flag::ARM64_SHA256, + 0x00300009 => Flag::ARM64_SHA512, + 0x0030000a => Flag::ARM64_SHA1, + 0x0030000b => Flag::ARM64_AES, + 0x0030000c => Flag::ARM64_PMULL, + 0x0030000d => Flag::ARM64_SPECRES, + 0x0030000e => Flag::ARM64_SB, + 0x0030000f => Flag::ARM64_FRINTTS, + 0x00300010 => Flag::ARM64_LRCPC, + 0x00300011 => Flag::ARM64_LRCPC2, + 0x00300012 => Flag::ARM64_FCMA, + 0x00300013 => Flag::ARM64_JSCVT, + 0x00300014 => Flag::ARM64_PAUTH, + 0x00300015 => Flag::ARM64_PAUTH2, + 0x00300016 => Flag::ARM64_FPAC, + 0x00300017 => Flag::ARM64_DPB, + 0x00300018 => Flag::ARM64_DPB2, + 0x00300019 => Flag::ARM64_BF16, + 0x0030001a => Flag::ARM64_I8MM, + 0x0030001b => Flag::ARM64_WFXT, + 0x0030001c => Flag::ARM64_RPRES, + 0x0030001d => Flag::ARM64_ECV, + 0x0030001e => Flag::ARM64_AFP, + 0x0030001f => Flag::ARM64_LSE2, + 0x00300020 => Flag::ARM64_CSV2, + 0x00300021 => Flag::ARM64_CVS3, + 0x00300022 => Flag::ARM64_DIT, + 0x00300023 => Flag::ARM64_FP16, + 0x00300024 => Flag::ARM64_SSBS, + 0x00300025 => Flag::ARM64_BTI, + 0x0030002c => Flag::ARM64_SME, + 0x0030002d => Flag::ARM64_SME2, + 0x0030002e => Flag::ARM64_SMEF64F64, + 0x0030002f => Flag::ARM64_SMEI16I64, + 0x00300030 => Flag::ARM64_SMEF32F32, + 0x00300031 => Flag::ARM64_SMEBI32I32, + 0x00300032 => Flag::ARM64_SMEB16F32, + 0x00300033 => Flag::ARM64_SMEF16F32, + 0x00300034 => Flag::ARM64_SMEI8I32, + 0x00300035 => Flag::ARM64_SMEI16I32, + 0x00300036 => Flag::ARM64_ADVSIMD, + 0x00300037 => Flag::ARM64_ADVSIMDHPFP, + 0x00300038 => Flag::ARM64_CRC32, + 0x00400000 => Flag::X86_64_DEFAULT, + 0x00400001 => Flag::X86_64_SSE41, + 0x00400002 => Flag::X86_64_FMA, + 0x00400003 => Flag::X86_64_AVX, + 0x00400004 => Flag::X86_64_AVX2, + 0x00400005 => Flag::X86_64_AVX512F, + 0x00400006 => Flag::X86_64_AVX512BW, + 0x00400007 => Flag::X86_64_BMI1, + 0x00400008 => Flag::X86_64_ROSETTA, + 0x00400009 => Flag::X86_64_HASWELL, + 0x0040000a => Flag::X86_64_IVYBRIDGE, + 0x0040000b => Flag::X86_64_NEHALEM, + 0x00200000 => Flag::SYSTEM_WIDE_DEFAULT, + 0x00200001 => Flag::SYSTEM_WIDE_INTERNAL_INSTALL, + 0x00200002 => Flag::SYSTEM_WIDE_CUSTOMER_INSTALL, + 0x00200003 => Flag::SYSTEM_WIDE_LOCKDOWN, + 0x00100000 => Flag::PER_PROCESS_DEFAULT, + 0x00100001 => Flag::PER_PROCESS_TRANSLATED, + 0x00100002 => Flag::PER_PROCESS_MTE_ENABLED, + 0x00100003 => Flag::PER_PROCESS_NO_OVERREAD, + _ => Flag::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Flag) -> u32 { + match value { + Flag::ARM64_DEFAULT => 0x00300000, + Flag::ARM64_FLAGM => 0x00300001, + Flag::ARM64_FLAGM2 => 0x00300002, + Flag::ARM64_FHM => 0x00300003, + Flag::ARM64_DOTPROD => 0x00300004, + Flag::ARM64_SHA3 => 0x00300005, + Flag::ARM64_RDM => 0x00300006, + Flag::ARM64_LSE => 0x00300007, + Flag::ARM64_SHA256 => 0x00300008, + Flag::ARM64_SHA512 => 0x00300009, + Flag::ARM64_SHA1 => 0x0030000a, + Flag::ARM64_AES => 0x0030000b, + Flag::ARM64_PMULL => 0x0030000c, + Flag::ARM64_SPECRES => 0x0030000d, + Flag::ARM64_SB => 0x0030000e, + Flag::ARM64_FRINTTS => 0x0030000f, + Flag::ARM64_LRCPC => 0x00300010, + Flag::ARM64_LRCPC2 => 0x00300011, + Flag::ARM64_FCMA => 0x00300012, + Flag::ARM64_JSCVT => 0x00300013, + Flag::ARM64_PAUTH => 0x00300014, + Flag::ARM64_PAUTH2 => 0x00300015, + Flag::ARM64_FPAC => 0x00300016, + Flag::ARM64_DPB => 0x00300017, + Flag::ARM64_DPB2 => 0x00300018, + Flag::ARM64_BF16 => 0x00300019, + Flag::ARM64_I8MM => 0x0030001a, + Flag::ARM64_WFXT => 0x0030001b, + Flag::ARM64_RPRES => 0x0030001c, + Flag::ARM64_ECV => 0x0030001d, + Flag::ARM64_AFP => 0x0030001e, + Flag::ARM64_LSE2 => 0x0030001f, + Flag::ARM64_CSV2 => 0x00300020, + Flag::ARM64_CVS3 => 0x00300021, + Flag::ARM64_DIT => 0x00300022, + Flag::ARM64_FP16 => 0x00300023, + Flag::ARM64_SSBS => 0x00300024, + Flag::ARM64_BTI => 0x00300025, + Flag::ARM64_SME => 0x0030002c, + Flag::ARM64_SME2 => 0x0030002d, + Flag::ARM64_SMEF64F64 => 0x0030002e, + Flag::ARM64_SMEI16I64 => 0x0030002f, + Flag::ARM64_SMEF32F32 => 0x00300030, + Flag::ARM64_SMEBI32I32 => 0x00300031, + Flag::ARM64_SMEB16F32 => 0x00300032, + Flag::ARM64_SMEF16F32 => 0x00300033, + Flag::ARM64_SMEI8I32 => 0x00300034, + Flag::ARM64_SMEI16I32 => 0x00300035, + Flag::ARM64_ADVSIMD => 0x00300036, + Flag::ARM64_ADVSIMDHPFP => 0x00300037, + Flag::ARM64_CRC32 => 0x00300038, + Flag::X86_64_DEFAULT => 0x00400000, + Flag::X86_64_SSE41 => 0x00400001, + Flag::X86_64_FMA => 0x00400002, + Flag::X86_64_AVX => 0x00400003, + Flag::X86_64_AVX2 => 0x00400004, + Flag::X86_64_AVX512F => 0x00400005, + Flag::X86_64_AVX512BW => 0x00400006, + Flag::X86_64_BMI1 => 0x00400007, + Flag::X86_64_ROSETTA => 0x00400008, + Flag::X86_64_HASWELL => 0x00400009, + Flag::X86_64_IVYBRIDGE => 0x0040000a, + Flag::X86_64_NEHALEM => 0x0040000b, + Flag::SYSTEM_WIDE_DEFAULT => 0x00200000, + Flag::SYSTEM_WIDE_INTERNAL_INSTALL => 0x00200001, + Flag::SYSTEM_WIDE_CUSTOMER_INSTALL => 0x00200002, + Flag::SYSTEM_WIDE_LOCKDOWN => 0x00200003, + Flag::PER_PROCESS_DEFAULT => 0x00100000, + Flag::PER_PROCESS_TRANSLATED => 0x00100001, + Flag::PER_PROCESS_MTE_ENABLED => 0x00100002, + Flag::PER_PROCESS_NO_OVERREAD => 0x00100003, + Flag::UNKNOWN(value) => value, + } + } +} + +declare_iterator!( + RuntimeTables, + RuntimeTable<'a>, + ffi::MachO_FunctionVariants_RuntimeTable, + ffi::MachO_FunctionVariants, + ffi::MachO_FunctionVariants_it_runtime_table +); + +declare_iterator!( + RuntimeTableEntries, + RuntimeTableEntry<'a>, + ffi::MachO_FunctionVariants_RuntimeTableEntry, + ffi::MachO_FunctionVariants_RuntimeTable, + ffi::MachO_FunctionVariants_RuntimeTable_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/functionstarts.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/functionstarts.rs new file mode 100644 index 0000000..285e20f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/functionstarts.rs @@ -0,0 +1,72 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure which represents the `LC_FUNCTION_STARTS` command +/// +/// This command is an array of ULEB128 encoded values +pub struct FunctionStarts<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl FunctionStarts<'_> { + /// Offset in the ``__LINKEDIT`` segment where *start functions* are located + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the functions list in the binary + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Addresses of every function entry point in the executable. + /// + /// This allows functions to exist for which there are no entries in the symbol table. + /// + ///
+ /// The address is relative to the __TEXT segment + ///
+ pub fn functions(&self) -> Vec { + Vec::from(self.ptr.functions().as_slice()) + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Add a function address to the list of function starts + pub fn add_function(&mut self, address: u64) { + self.ptr.pin_mut().add_function(address); + } +} + +impl std::fmt::Debug for FunctionStarts<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("FunctionStarts") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for FunctionStarts<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for FunctionStarts<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/lazy_load_dylib_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/lazy_load_dylib_info.rs new file mode 100644 index 0000000..734fb63 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/lazy_load_dylib_info.rs @@ -0,0 +1,215 @@ +use super::Command; +use crate::common::FromFFI; +use crate::{declare_iterator, to_slice}; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Class representing the `LC_LAZY_LOAD_DYLIB_INFO` load command. +/// +/// This command describes how to **lazily load a dylib**: instead of binding +/// the library and its symbols at launch time, `dyld` keeps the information +/// required to resolve the dylib on the first use of one of its symbols. +pub struct LazyLoadDylibInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl LazyLoadDylibInfo<'_> { + /// Offset in the `__LINKEDIT` segment where the payload is located + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the payload + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Raw payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Load path of the dylib to bind lazily + pub fn load_path(&self) -> String { + self.ptr.load_path().to_string() + } + + /// Image offset of the global flag that is set once the dylib has been loaded by dyld + pub fn flag_image_offset(&self) -> u32 { + self.ptr.flag_image_offset() + } + + /// Raw flags associated with this command (see [`LazyLoadDylibInfo::may_be_missing`]) + pub fn flags(&self) -> u16 { + self.ptr.flags() + } + + /// Whether the dylib is allowed to be missing at runtime (weak linked) + pub fn may_be_missing(&self) -> bool { + self.ptr.may_be_missing() + } + + /// Chained-fixups pointer format used by the binding chain + pub fn pointer_format(&self) -> u16 { + self.ptr.pointer_format() + } + + /// Image offset of the fixup chain start used to bind the dylib's symbols + pub fn chain_start_image_offset(&self) -> u32 { + self.ptr.chain_start_image_offset() + } + + /// List of the symbol names to bind lazily for this dylib + pub fn symbols(&self) -> Vec { + let mut result = Vec::new(); + for entry in self.ptr.symbols().into_iter() { + result.push(entry.to_string()); + } + result + } + + /// Iterator over the lazy-binding [`Fixup`] entries + pub fn fixups(&self) -> Fixups<'_> { + Fixups::new(self.ptr.fixups()) + } + + /// Change the load path of the dylib to bind lazily. The new path is + /// serialized into the payload when the binary is rebuilt. + pub fn set_load_path(&mut self, value: &str) { + cxx::let_cxx_string!(value = value); + self.ptr.pin_mut().set_load_path(&value); + } + + /// Set the image offset of the global "loaded" flag. + pub fn set_flag_image_offset(&mut self, value: u32) { + self.ptr.pin_mut().set_flag_image_offset(value); + } + + /// Set the raw flags associated with this command. + pub fn set_flags(&mut self, value: u16) { + self.ptr.pin_mut().set_flags(value); + } + + /// Set or clear the "may be missing" (weak linked) flag bit. + pub fn set_may_be_missing(&mut self, value: bool) { + self.ptr.pin_mut().set_may_be_missing(value); + } + + /// Set the chained-fixups pointer format used by the binding chain. + pub fn set_pointer_format(&mut self, value: u16) { + self.ptr.pin_mut().set_pointer_format(value); + } + + /// Set the image offset of the fixup chain start. + pub fn set_chain_start_image_offset(&mut self, value: u32) { + self.ptr.pin_mut().set_chain_start_image_offset(value); + } + + /// Append a symbol name to the list of symbols to bind lazily. + pub fn add_symbol(&mut self, value: &str) { + cxx::let_cxx_string!(value = value); + self.ptr.pin_mut().add_symbol(&value); + } + + /// Replace the list of symbol names to bind lazily. The new list is + /// serialized into the payload when the binary is rebuilt. + pub fn set_symbols(&mut self, symbols: &[&str]) { + self.ptr.pin_mut().clear_symbols(); + for symbol in symbols { + cxx::let_cxx_string!(symbol = *symbol); + self.ptr.pin_mut().add_symbol(&symbol); + } + } +} + +/// A single lazy-binding fixup decoded from a [`LazyLoadDylibInfo`] chain. +pub struct Fixup<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_LazyLoadDylibInfo>, +} + +impl Fixup<'_> { + /// Virtual address of the slot bound by this fixup + pub fn address(&self) -> u64 { + self.ptr.address() + } + + /// Index of the bound symbol in [`LazyLoadDylibInfo::symbols`] + pub fn ordinal(&self) -> u32 { + self.ptr.ordinal() + } + + /// Name of the bound symbol (resolved from [`Fixup::ordinal`]) + pub fn symbol(&self) -> String { + self.ptr.symbol().to_string() + } + + /// Whether the bound pointer is authenticated (`arm64e` PAC) + pub fn is_auth(&self) -> bool { + self.ptr.is_auth() + } +} + +impl FromFFI for Fixup<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for Fixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Fixup") + .field("address", &self.address()) + .field("ordinal", &self.ordinal()) + .field("symbol", &self.symbol()) + .field("is_auth", &self.is_auth()) + .finish() + } +} + +impl std::fmt::Display for Fixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl std::fmt::Debug for LazyLoadDylibInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("LazyLoadDylibInfo") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .field("load_path", &self.load_path()) + .field("flags", &self.flags()) + .field("pointer_format", &self.pointer_format()) + .finish() + } +} + +impl FromFFI for LazyLoadDylibInfo<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for LazyLoadDylibInfo<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + Fixups, + Fixup<'a>, + ffi::MachO_LazyLoadDylibInfo_Fixup, + ffi::MachO_LazyLoadDylibInfo, + ffi::MachO_LazyLoadDylibInfo_it_fixups +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/linker_opt_hint.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/linker_opt_hint.rs new file mode 100644 index 0000000..977b1f8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/linker_opt_hint.rs @@ -0,0 +1,55 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure which represents the `LC_LINKER_OPTIMIZATION_HINT` command +pub struct LinkerOptHint<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl LinkerOptHint<'_> { + /// Offset in the binary where the *hint* starts + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + + /// Size of the payload + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + + /// Payload as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for LinkerOptHint<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("LinkerOptHint") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl FromFFI for LinkerOptHint<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for LinkerOptHint<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/main_cmd.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/main_cmd.rs new file mode 100644 index 0000000..2619a8a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/main_cmd.rs @@ -0,0 +1,50 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure that represents the `LC_MAIN` command. This kind of command can be used to determine the +/// entrypoint of an executable. +pub struct Main<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Main<'_> { + /// Offset of the *main* function **relative** to the `__TEXT` + /// segment + pub fn entrypoint(&self) -> u64 { + self.ptr.entrypoint() + } + + /// The initial stack size + pub fn stack_size(&self) -> u64 { + self.ptr.stack_size() + } +} + +impl std::fmt::Debug for Main<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Main") + .field("base", &base) + .field("entrypoint", &self.entrypoint()) + .field("stack_size", &self.stack_size()) + .finish() + } +} + +impl<'a> FromFFI for Main<'a> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Main<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/note.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/note.rs new file mode 100644 index 0000000..d96ff5d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/note.rs @@ -0,0 +1,65 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Class that represents the `LC_NOTE` command. +/// +/// This command is used to include arbitrary notes or metadata within a binary. +pub struct Note<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Note<'_> { + /// Offset of the data associated with this note + pub fn note_offset(&self) -> u64 { + self.ptr.note_offset() + } + + /// Size of the data referenced by the note_offset + pub fn note_size(&self) -> u64 { + self.ptr.note_size() + } + + /// Owner of the note (e.g. `AIR_METALLIB`) + pub fn owner(&self) -> &[u8] { + to_slice!(self.ptr.owner()); + } + + pub fn set_note_offset(&mut self, offset: u64) { + self.ptr.pin_mut().set_note_offset(offset); + } + + pub fn set_note_size(&mut self, size: u64) { + self.ptr.pin_mut().set_note_size(size); + } +} + +impl std::fmt::Debug for Note<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Note") + .field("base", &base) + .field("note_offset", &self.note_offset()) + .field("note_size", &self.note_size()) + .field("owner", &self.owner()) + .finish() + } +} + +impl<'a> FromFFI for Note<'a> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Note<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/routine.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/routine.rs new file mode 100644 index 0000000..2b103db --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/routine.rs @@ -0,0 +1,86 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Class that represents the `LC_ROUTINE/LC_ROUTINE64` commands. +/// Accodring to the Mach-O `loader.h` documentation: +/// +/// > The routines command contains the address of the dynamic shared library +/// > initialization routine and an index into the module table for the module +/// > that defines the routine. Before any modules are used from the library the +/// > dynamic linker fully binds the module that defines the initialization routine +/// > and then calls it. This gets called before any module initialization +/// > routines (used for C++ static constructors) in the library. +pub struct Routine<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Routine<'_> { + /// address of initialization routine + pub fn init_address(&self) -> u64 { + self.ptr.init_address() + } + + /// Index into the module table that the init routine is defined in + pub fn init_module(&self) -> u64 { + self.ptr.init_module() + } + + pub fn reserved1(&self) -> u64 { + self.ptr.reserved1() + } + + pub fn reserved2(&self) -> u64 { + self.ptr.reserved2() + } + + pub fn reserved3(&self) -> u64 { + self.ptr.reserved3() + } + + pub fn reserved4(&self) -> u64 { + self.ptr.reserved4() + } + + pub fn reserved5(&self) -> u64 { + self.ptr.reserved5() + } + + pub fn reserved6(&self) -> u64 { + self.ptr.reserved6() + } +} + +impl std::fmt::Debug for Routine<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Routine") + .field("base", &base) + .field("init_address", &self.init_address()) + .field("init_module", &self.init_module()) + .field("reserved1", &self.reserved1()) + .field("reserved2", &self.reserved2()) + .field("reserved3", &self.reserved3()) + .field("reserved4", &self.reserved4()) + .field("reserved5", &self.reserved5()) + .field("reserved6", &self.reserved6()) + .finish() + } +} + +impl FromFFI for Routine<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Routine<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/rpath.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/rpath.rs new file mode 100644 index 0000000..53d206e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/rpath.rs @@ -0,0 +1,71 @@ +use super::Command; +use crate::common::FromFFI; +use crate::declare_iterator; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// Structure that represents the `LC_RPATH` command. +/// +/// This command is used to add path for searching libraries +/// associated with the `@rpath` prefix. +pub struct RPath<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl RPath<'_> { + /// Create a new Rpath command with the given path + pub fn new(value: &str) -> RPath<'static> { + cxx::let_cxx_string!(__cxx_s = value.to_string()); + RPath::from_ffi(lief_ffi::MachO_RPathCommand::create(&__cxx_s)) + } + + /// The rpath value as a string + pub fn path(&self) -> String { + self.ptr.path().to_string() + } + + /// Set the rpath value + pub fn set_path(&mut self, path: &str) { + cxx::let_cxx_string!(__cxx_s = path.to_string()); + self.ptr.pin_mut().set_path(&__cxx_s); + } + + /// Original string offset of the path + pub fn path_offset(&self) -> u32 { + self.ptr.path_offset() + } +} + +impl std::fmt::Debug for RPath<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("RPath") + .field("base", &base) + .field("path", &self.path()) + .finish() + } +} + +impl FromFFI for RPath<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for RPath<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + RPaths, + RPath<'a>, + ffi::MachO_RPathCommand, + ffi::MachO_Binary, + ffi::MachO_Binary_it_rpaths +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/segment.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/segment.rs new file mode 100644 index 0000000..f5ee40f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/segment.rs @@ -0,0 +1,204 @@ +use super::Command; +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::to_slice; +use lief_ffi as ffi; +use std::marker::PhantomData; + +use crate::macho::relocation::Relocation; +use crate::macho::section::Section; + +use bitflags::bitflags; + +bitflags! { + /// Segment flags + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u64 { + const HIGHVM = 0x1; + const FVMLIB = 0x2; + const NORELOC = 0x4; + const PROTECTED_VERSION_1 = 0x8; + const READ_ONLY = 0x10; + } +} + +impl From for Flags { + fn from(value: u64) -> Self { + Flags::from_bits_truncate(value) + } +} +impl From for u64 { + fn from(value: Flags) -> Self { + value.bits() + } +} +impl std::fmt::Display for Flags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +bitflags! { + /// VM protection flags + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct VmProtections: u32 { + const READ = 0x1; + const WRITE = 0x2; + const EXECUTE = 0x4; + } +} + +impl From for VmProtections { + fn from(value: u32) -> Self { + VmProtections::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: VmProtections) -> Self { + value.bits() + } +} +impl std::fmt::Display for VmProtections { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +/// Class which represents a `LC_SEGMENT/LC_SEGMENT_64` command +pub struct Segment<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Segment<'_> { + /// Name of the segment (e.g. `__TEXT`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Absolute virtual base address of the segment + pub fn virtual_address(&self) -> u64 { + self.ptr.virtual_address() + } + + /// Virtual size of the segment + pub fn virtual_size(&self) -> u64 { + self.ptr.virtual_size() + } + + /// Size of this segment in the binary file + pub fn file_size(&self) -> u64 { + self.ptr.file_size() + } + + /// Offset of the data of this segment in the file + pub fn file_offset(&self) -> u64 { + self.ptr.file_offset() + } + + /// The maximum of protections for this segment + pub fn max_protection(&self) -> u32 { + self.ptr.max_protection() + } + + /// The initial protections of this segment + pub fn init_protection(&self) -> u32 { + self.ptr.init_protection() + } + + /// The number of sections associated with this segment + pub fn numberof_sections(&self) -> u32 { + self.ptr.numberof_sections() + } + + /// Flags associated with this segment + pub fn flags(&self) -> u32 { + self.ptr.flags() + } + + /// The raw content of this segment as a slice of bytes + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Iterator over the [`crate::macho::Section`] owned by this segment + pub fn sections(&self) -> Sections<'_> { + Sections::new(self.ptr.sections()) + } + + /// Return an iterator over the [`crate::macho::Relocation`] linked to this segment + /// + /// For Mach-O executable or library this iterator should be empty as + /// the relocations are managed by the Dyld's rebase opcodes. + /// On the other hand, for object files (`.o`) this iterator should not be empty. + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// The original index of this segment or -1 if not defined + pub fn index(&self) -> Option { + let idx = self.ptr.index(); + if idx < 0 { None } else { Some(idx as u8) } + } + + /// Return the [`Section`] with the given name (if any) + pub fn get_section(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + into_optional(self.ptr.get_section(&__cxx_s)) + } +} + +impl std::fmt::Debug for Segment<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("Segment") + .field("base", &base) + .field("name", &self.name()) + .field("virtual_address", &self.virtual_address()) + .field("virtual_size", &self.virtual_size()) + .field("file_size", &self.file_size()) + .field("file_offset", &self.file_offset()) + .field("max_protection", &self.max_protection()) + .field("init_protection", &self.init_protection()) + .field("numberof_sections", &self.numberof_sections()) + .field("flags", &self.flags()) + .finish() + } +} + +impl FromFFI for Segment<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Segment<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + Segments, + Segment<'a>, + ffi::MachO_SegmentCommand, + ffi::MachO_Binary, + ffi::MachO_Binary_it_segments +); +declare_iterator!( + Sections, + Section<'a>, + ffi::MachO_Section, + ffi::MachO_SegmentCommand, + ffi::MachO_SegmentCommand_it_sections +); +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::MachO_Relocation, + ffi::MachO_SegmentCommand, + ffi::MachO_SegmentCommand_it_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/segment_split_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/segment_split_info.rs new file mode 100644 index 0000000..31a18b9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/segment_split_info.rs @@ -0,0 +1,50 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure that represents the `LC_SEGMENT_SPLIT_INFO` command +pub struct SegmentSplitInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl SegmentSplitInfo<'_> { + pub fn data_offset(&self) -> u32 { + self.ptr.data_offset() + } + pub fn data_size(&self) -> u32 { + self.ptr.data_size() + } + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for SegmentSplitInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("SegmentSplitInfo") + .field("base", &base) + .field("data_offset", &self.data_offset()) + .field("data_size", &self.data_size()) + .finish() + } +} + +impl<'a> FromFFI for SegmentSplitInfo<'a> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for SegmentSplitInfo<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/source_version.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/source_version.rs new file mode 100644 index 0000000..1d46790 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/source_version.rs @@ -0,0 +1,48 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Class that represents the MachO `LC_SOURCE_VERSION` +/// This command is used to provide the *version* of the sources used to +/// build the binary. +pub struct SourceVersion<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl SourceVersion<'_> { + pub fn version(&self) -> (u64, u64, u64, u64, u64) { + let vec = Vec::from(self.ptr.version().as_slice()); + if vec.len() != 5 { + return (0, 0, 0, 0, 0); + } + (vec[0], vec[1], vec[2], vec[3], vec[4]) + } +} + +impl std::fmt::Debug for SourceVersion<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("SourceVersion") + .field("base", &base) + .field("version", &self.version()) + .finish() + } +} + +impl<'a> FromFFI for SourceVersion<'a> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for SourceVersion<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_client.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_client.rs new file mode 100644 index 0000000..f9464a3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_client.rs @@ -0,0 +1,61 @@ +use super::Command; +use crate::common::FromFFI; +use crate::declare_iterator; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Class that represents the SubClient command. +/// Accodring to the Mach-O `loader.h` documentation: +/// +/// > For dynamically linked shared libraries that are subframework of an umbrella +/// > framework they can allow clients other than the umbrella framework or other +/// > subframeworks in the same umbrella framework. To do this the subframework +/// > is built with "-allowable_client client_name" and an LC_SUB_CLIENT load +/// > command is created for each -allowable_client flag. The client_name is +/// > usually a framework name. It can also be a name used for bundles clients +/// > where the bundle is built with "-client_name client_name". +pub struct SubClient<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl SubClient<'_> { + /// Name of the subclient + pub fn client(&self) -> String { + self.ptr.client().to_string() + } +} + +impl std::fmt::Debug for SubClient<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("SubClient") + .field("base", &base) + .field("client", &self.client()) + .finish() + } +} + +impl FromFFI for SubClient<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for SubClient<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_iterator!( + SubClients, + SubClient<'a>, + ffi::MachO_SubClient, + ffi::MachO_Binary, + ffi::MachO_Binary_it_sub_clients +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_framework.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_framework.rs new file mode 100644 index 0000000..8adeb51 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/sub_framework.rs @@ -0,0 +1,53 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Class that represents the SubFramework command. +/// Accodring to the Mach-O ``loader.h`` documentation: +/// +/// > A dynamically linked shared library may be a subframework of an umbrella +/// > framework. If so it will be linked with "-umbrella umbrella_name" where +/// > Where "umbrella_name" is the name of the umbrella framework. A subframework +/// > can only be linked against by its umbrella framework or other subframeworks +/// > that are part of the same umbrella framework. Otherwise the static link +/// > editor produces an error and states to link against the umbrella framework. +/// > The name of the umbrella framework for subframeworks is recorded in the +/// > following structure. +pub struct SubFramework<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl SubFramework<'_> { + /// Name of the umbrella framework + pub fn umbrella(&self) -> String { + self.ptr.umbrella().to_string() + } +} + +impl std::fmt::Debug for SubFramework<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("SubFramework") + .field("base", &base) + .field("umbrella", &self.umbrella()) + .finish() + } +} + +impl FromFFI for SubFramework<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for SubFramework<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/symbol_command.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/symbol_command.rs new file mode 100644 index 0000000..649ddf6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/symbol_command.rs @@ -0,0 +1,78 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure that represents the `LC_SYMTAB` command +pub struct SymbolCommand<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl SymbolCommand<'_> { + /// Offset from the start of the file to the n_list associated with the command + pub fn symbol_offset(&self) -> u32 { + self.ptr.symbol_offset() + } + + /// Number of symbols registered + pub fn numberof_symbols(&self) -> u32 { + self.ptr.numberof_symbols() + } + + /// Offset from the start of the file to the string table + pub fn strings_offset(&self) -> u32 { + self.ptr.strings_offset() + } + + /// Size of the size string table + pub fn strings_size(&self) -> u32 { + self.ptr.strings_size() + } + + pub fn original_str_size(&self) -> u32 { + self.ptr.original_str_size() + } + + pub fn original_nb_symbols(&self) -> u32 { + self.ptr.original_nb_symbols() + } + + pub fn symbol_table(&self) -> &[u8] { + to_slice!(self.ptr.symbol_table()); + } + + pub fn string_table(&self) -> &[u8] { + to_slice!(self.ptr.string_table()); + } +} + +impl std::fmt::Debug for SymbolCommand<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("SymbolCommand") + .field("base", &base) + .field("symbol_offset", &self.symbol_offset()) + .field("numberof_symbols", &self.numberof_symbols()) + .field("strings_offset", &self.strings_offset()) + .field("strings_size", &self.strings_size()) + .finish() + } +} + +impl FromFFI for SymbolCommand<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for SymbolCommand<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/thread_command.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/thread_command.rs new file mode 100644 index 0000000..1a2d1b1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/thread_command.rs @@ -0,0 +1,83 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; + +use crate::macho::header::CpuType; +use std::marker::PhantomData; + +/// Structure that represents the `LC_THREAD` / `LC_UNIXTHREAD` commands and that +/// can be used to get the binary entrypoint when the `LC_MAIN` is not present +/// +/// Generally speaking, this command aims at defining the original state +/// of the main thread which includes the registers' values +pub struct ThreadCommand<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl ThreadCommand<'_> { + /// Integer that defines a special *flavor* for the thread. + /// + /// The meaning of this value depends on the architecture. The list of + /// the values can be found in the XNU kernel files: + /// - xnu/osfmk/mach/arm/thread_status.h for the ARM/AArch64 architectures + /// - xnu/osfmk/mach/i386/thread_status.h for the x86/x86-64 architectures + pub fn flavor(&self) -> u32 { + self.ptr.flavor() + } + + /// The CPU architecture that is targeted by this Thread Command + pub fn architecture(&self) -> CpuType { + CpuType::from(self.ptr.architecture()) + } + + /// Size of the thread state data with 32-bits alignment. + /// + /// This value should match `state().len()` + pub fn count(&self) -> u32 { + self.ptr.count() + } + + /// Return the initial Program Counter regardless of the underlying architecture. + /// This value, when non null, can be used to determine the binary's entrypoint. + /// + /// Underneath, it works by looking for the PC register value in the [`ThreadCommand::state`] + /// data + pub fn pc(&self) -> u64 { + self.ptr.pc() + } + + /// The actual thread state as a vector of bytes. Depending on the architecture(), + /// these data can be cast into `x86_thread_state_t, x86_thread_state64_t, ...` + pub fn state(&self) -> &[u8] { + to_slice!(self.ptr.state()); + } +} + +impl std::fmt::Debug for ThreadCommand<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("ThreadCommand") + .field("base", &base) + .field("flavor", &self.flavor()) + .field("count", &self.count()) + .field("pc", &self.pc()) + .finish() + } +} + +impl FromFFI for ThreadCommand<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for ThreadCommand<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/two_level_hints.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/two_level_hints.rs new file mode 100644 index 0000000..d133823 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/two_level_hints.rs @@ -0,0 +1,52 @@ +use super::Command; +use crate::common::FromFFI; +use crate::to_slice; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure which represents the `LC_TWOLEVEL_HINTS` command +pub struct TwoLevelHints<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl TwoLevelHints<'_> { + /// Offset of the command. It should point in the `__LINKEDIT` segment + pub fn offset(&self) -> u32 { + self.ptr.offset() + } + pub fn original_nb_hints(&self) -> u32 { + self.ptr.original_nb_hints() + } + + /// Original payload of the command + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +impl std::fmt::Debug for TwoLevelHints<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("TwoLevelHints") + .field("base", &base) + .field("offset", &self.offset()) + .finish() + } +} + +impl FromFFI for TwoLevelHints<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for TwoLevelHints<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/unknown.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/unknown.rs new file mode 100644 index 0000000..1c396fc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/unknown.rs @@ -0,0 +1,43 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Generic structure when the command is not recognized by LIEF (e.g private `LC_xxx` command) +pub struct Unknown<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Unknown<'_> { + /// The original `LC_` int that is not supported by LIEF + pub fn original_command(&self) -> u64 { + self.ptr.original_command() + } +} + +impl std::fmt::Debug for Unknown<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("UnknownCommand") + .field("base", &base) + .field("original_command", &self.original_command()) + .finish() + } +} + +impl FromFFI for Unknown<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for Unknown<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/uuid.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/uuid.rs new file mode 100644 index 0000000..6ce8f8e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/uuid.rs @@ -0,0 +1,43 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure that represents the `LC_UUID` command +pub struct UUID<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl UUID<'_> { + /// The UUID as a 16-bytes array + pub fn uuid(&self) -> Vec { + Vec::from(self.ptr.uuid().as_slice()) + } +} + +impl std::fmt::Debug for UUID<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("UUID") + .field("base", &base) + .field("uuid", &self.uuid()) + .finish() + } +} + +impl FromFFI for UUID<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for UUID<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/commands/version_min.rs b/vendor/lief/api/rust/crates/lief/src/macho/commands/version_min.rs new file mode 100644 index 0000000..cfb54d9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/commands/version_min.rs @@ -0,0 +1,57 @@ +use super::Command; +use crate::common::FromFFI; +use lief_ffi as ffi; + +use std::marker::PhantomData; + +/// Structure that wraps the `LC_VERSION_MIN_MACOSX, LC_VERSION_MIN_IPHONEOS, ...` commands. +pub struct VersionMin<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl VersionMin<'_> { + /// Version as a tuplce + pub fn version(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.version().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } + + /// SDK version as a tuple + pub fn sdk(&self) -> (u64, u64, u64) { + let vec = Vec::from(self.ptr.sdk().as_slice()); + if vec.len() != 3 { + return (0, 0, 0); + } + (vec[0], vec[1], vec[2]) + } +} + +impl std::fmt::Debug for VersionMin<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn Command; + f.debug_struct("VersionMin") + .field("base", &base) + .field("version", &self.version()) + .field("sdk", &self.sdk()) + .finish() + } +} + +impl FromFFI for VersionMin<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Command for VersionMin<'_> { + fn get_base(&self) -> &ffi::MachO_Command { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/export_info.rs b/vendor/lief/api/rust/crates/lief/src/macho/export_info.rs new file mode 100644 index 0000000..dbc7224 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/export_info.rs @@ -0,0 +1,123 @@ +use lief_ffi as ffi; + +use bitflags::bitflags; +use std::{fmt, marker::PhantomData}; + +use crate::common::{FromFFI, into_optional}; + +use super::{Symbol, commands::Dylib}; + +/// This structure represents an export (info) in a Mach-O binary +pub struct ExportInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Kind { + REGULAR, + THREAD_LOCAL, + ABSOLUTE, + UNKNOWN(u64), +} + +impl From for Kind { + fn from(value: u64) -> Self { + match value { + 0x00000000 => Kind::REGULAR, + 0x00000001 => Kind::THREAD_LOCAL, + 0x00000002 => Kind::ABSOLUTE, + _ => Kind::UNKNOWN(value), + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u64 { + const WEAK_DEFINITION = 0x4; + const REEXPORT = 0x8; + const STUB_AND_RESOLVER = 0x10; + const STATIC_RESOLVER = 0x20; + } +} + +impl From for Flags { + fn from(value: u64) -> Self { + Flags::from_bits_truncate(value) + } +} +impl From for u64 { + fn from(value: Flags) -> Self { + value.bits() + } +} +impl std::fmt::Display for Flags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl fmt::Debug for ExportInfo<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("ExportInfo") + .field("node_offset", &self.node_offset()) + .field("flags", &self.flags()) + .field("address", &self.address()) + .field("other", &self.other()) + .field("kind", &self.kind()) + .finish() + } +} + +impl ExportInfo<'_> { + /// Original offset in the export Trie + pub fn node_offset(&self) -> u64 { + self.ptr.node_offset() + } + + pub fn flags(&self) -> Flags { + Flags::from(self.ptr.flags()) + } + + /// The address of the export + pub fn address(&self) -> u64 { + self.ptr.address() + } + + pub fn other(&self) -> u64 { + self.ptr.other() + } + + /// The export's kind (regular, thread local, absolute, ...) + pub fn kind(&self) -> Kind { + Kind::from(self.ptr.kind()) + } + + /// Symbol associated with this export + pub fn symbol(&self) -> Option> { + into_optional(self.ptr.symbol()) + } + + /// If the export is a re-export ([`Flags::REEXPORT`]) this function returns + /// the symbol being re-exported + pub fn alias(&self) -> Option> { + into_optional(self.ptr.alias()) + } + + /// If the export is a re-export ([`Flags::REEXPORT`]) this function returns + /// the library from which the symbol is re-exported + pub fn alias_library(&self) -> Option> { + into_optional(self.ptr.alias_library()) + } +} + +impl<'a> FromFFI for ExportInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/fat_binary.rs b/vendor/lief/api/rust/crates/lief/src/macho/fat_binary.rs new file mode 100644 index 0000000..663b3e5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/fat_binary.rs @@ -0,0 +1,136 @@ +use super::binary::Binary; +use lief_ffi as ffi; + +use crate::{ + common::{AsFFI, FromFFI, into_optional}, + macho::header::CpuType, +}; +use std::path::Path; + +/// This structure represents a FAT Mach-O +pub struct FatBinary { + pub nb_macho: u32, + ptr: cxx::UniquePtr, +} + +impl FromFFI for FatBinary { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + nb_macho: ptr.size(), + ptr, + } + } +} + +impl std::fmt::Debug for FatBinary { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("FatBinary") + .field("nb_macho", &self.nb_macho) + .finish() + } +} + +/// Iterator over the different [`crate::macho::Binary`] wrapped by this FAT Mach-O +pub struct FatBinaryIterator<'a> { + index: u32, + fat: &'a FatBinary, +} + +impl FatBinary { + /// Create a FatBinary from the given Mach-O path. + pub fn parse>(path: P) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::MachO_FatBinary::parse(&__cxx_s); + if ffi.is_null() { + return None; + } + Some(FatBinary::from_ffi(ffi)) + } + + /// Create a FatBinary from the given Mach-O path with the provided + /// parser configuration. + pub fn parse_with_config>( + path: P, + config: &super::parser_config::Config, + ) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::MachO_FatBinary::parse_with_config(&__cxx_s, &ffi_config); + if ffi.is_null() { + return None; + } + Some(FatBinary::from_ffi(ffi)) + } + + /// Parse a Mach-O binary from a memory dump located at `path` that was + /// mapped at the virtual address `addr` + pub fn parse_from_dump>(path: P, addr: u64) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::MachO_FatBinary::parse_from_dump(&__cxx_s, addr); + if ffi.is_null() { + return None; + } + Some(FatBinary::from_ffi(ffi)) + } + + /// Same as [`FatBinary::parse_from_dump`] but with a provided configuration + pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &super::parser_config::Config, + ) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::MachO_FatBinary::parse_from_dump_with_config(&__cxx_s, addr, &ffi_config); + if ffi.is_null() { + return None; + } + Some(FatBinary::from_ffi(ffi)) + } + + /// Gets the [`Binary`] that matches the given architecture + pub fn with_cpu(&self, cpu: CpuType) -> Option { + into_optional(self.ptr.binary_from_arch(cpu.into())) + } + + /// Iterator over the [`crate::macho::Binary`] + pub fn iter(&self) -> FatBinaryIterator<'_> { + FatBinaryIterator { + index: 0, + fat: self, + } + } + + /// Reconstruct the FAT binary object and write it to the given path + pub fn write>(&mut self, output: P) { + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr.as_mut().unwrap().write(&__cxx_s); + } +} + +impl AsFFI for FatBinary { + fn as_ffi(&self) -> &ffi::MachO_FatBinary { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::MachO_FatBinary> { + self.ptr.pin_mut() + } +} + +impl<'a> Iterator for FatBinaryIterator<'a> { + type Item = Binary; + fn next(&mut self) -> Option { + if self.index >= self.fat.nb_macho { + return None; + } + self.index += 1; + Some(Binary::from_ffi(self.fat.ptr.binary_at(self.index - 1))) + } +} + +impl<'a> ExactSizeIterator for FatBinaryIterator<'a> { + fn len(&self) -> usize { + self.fat.nb_macho.try_into().unwrap() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/header.rs b/vendor/lief/api/rust/crates/lief/src/macho/header.rs new file mode 100644 index 0000000..9857014 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/header.rs @@ -0,0 +1,276 @@ +use lief_ffi as ffi; + +use bitflags::bitflags; + +use crate::common::FromFFI; +use std::{fmt, marker::PhantomData}; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum FileType { + OBJECT, + EXECUTE, + FVMLIB, + CORE, + PRELOAD, + DYLIB, + DYLINKER, + BUNDLE, + DYLIB_STUB, + DSYM, + KEXT_BUNDLE, + FILESET, + GPU_EXECUTE, + GPU_DYLIB, + UNKNOWN(u32), +} + +impl From for FileType { + fn from(value: u32) -> Self { + match value { + 0x00000001 => FileType::OBJECT, + 0x00000002 => FileType::EXECUTE, + 0x00000003 => FileType::FVMLIB, + 0x00000004 => FileType::CORE, + 0x00000005 => FileType::PRELOAD, + 0x00000006 => FileType::DYLIB, + 0x00000007 => FileType::DYLINKER, + 0x00000008 => FileType::BUNDLE, + 0x00000009 => FileType::DYLIB_STUB, + 0x0000000a => FileType::DSYM, + 0x0000000b => FileType::KEXT_BUNDLE, + 0x0000000c => FileType::FILESET, + 0x0000000d => FileType::GPU_EXECUTE, + 0x0000000e => FileType::GPU_DYLIB, + _ => FileType::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: FileType) -> u32 { + match value { + FileType::OBJECT => 0x00000001, + FileType::EXECUTE => 0x00000002, + FileType::FVMLIB => 0x00000003, + FileType::CORE => 0x00000004, + FileType::PRELOAD => 0x00000005, + FileType::DYLIB => 0x00000006, + FileType::DYLINKER => 0x00000007, + FileType::BUNDLE => 0x00000008, + FileType::DYLIB_STUB => 0x00000009, + FileType::DSYM => 0x0000000a, + FileType::KEXT_BUNDLE => 0x0000000b, + FileType::FILESET => 0x0000000c, + FileType::GPU_EXECUTE => 0x0000000d, + FileType::GPU_DYLIB => 0x0000000e, + FileType::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum CpuType { + ANY, + X86, + X86_64, + MIPS, + MC98000, + HPPA, + ARM, + ARM64, + MC88000, + SPARC, + I860, + ALPHA, + POWERPC, + POWERPC64, + APPLE_GPU, + AMD_GPU, + INTEL_GPU, + AIR64, + UNKNOWN(i32), +} + +impl From for CpuType { + fn from(value: i32) -> Self { + match value { + -1 => CpuType::ANY, + 0x00000007 => CpuType::X86, + 0x01000007 => CpuType::X86_64, + 0x00000008 => CpuType::MIPS, + 0x0000000a => CpuType::MC98000, + 0x0000000b => CpuType::HPPA, + 0x0000000c => CpuType::ARM, + 0x0100000c => CpuType::ARM64, + 0x0000000d => CpuType::MC88000, + 0x0000000e => CpuType::SPARC, + 0x0000000f => CpuType::I860, + 0x00000010 => CpuType::ALPHA, + 0x00000012 => CpuType::POWERPC, + 0x01000012 => CpuType::POWERPC64, + 0x01000013 => CpuType::APPLE_GPU, + 0x01000014 => CpuType::AMD_GPU, + 0x01000015 => CpuType::INTEL_GPU, + 0x01000017 => CpuType::AIR64, + _ => CpuType::UNKNOWN(value), + } + } +} +impl From for i32 { + fn from(value: CpuType) -> i32 { + match value { + CpuType::ANY => -1, + CpuType::X86 => 0x00000007, + CpuType::X86_64 => 0x01000007, + CpuType::MIPS => 0x00000008, + CpuType::MC98000 => 0x0000000a, + CpuType::HPPA => 0x0000000b, + CpuType::ARM => 0x0000000c, + CpuType::ARM64 => 0x0100000c, + CpuType::MC88000 => 0x0000000d, + CpuType::SPARC => 0x0000000e, + CpuType::I860 => 0x0000000f, + CpuType::ALPHA => 0x00000010, + CpuType::POWERPC => 0x00000012, + CpuType::POWERPC64 => 0x01000012, + CpuType::APPLE_GPU => 0x01000013, + CpuType::AMD_GPU => 0x01000014, + CpuType::INTEL_GPU => 0x01000015, + CpuType::AIR64 => 0x01000017, + CpuType::UNKNOWN(_) => -1, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u32 { + const NOUNDEFS = 0x1; + const INCRLINK = 0x2; + const DYLDLINK = 0x4; + const BINDATLOAD = 0x8; + const PREBOUND = 0x10; + const SPLIT_SEGS = 0x20; + const LAZY_INIT = 0x40; + const TWOLEVEL = 0x80; + const FORCE_FLAT = 0x100; + const NOMULTIDEFS = 0x200; + const NOFIXPREBINDING = 0x400; + const PREBINDABLE = 0x800; + const ALLMODSBOUND = 0x1000; + const SUBSECTIONS_VIA_SYMBOLS = 0x2000; + const CANONICAL = 0x4000; + const WEAK_DEFINES = 0x8000; + const BINDS_TO_WEAK = 0x10000; + const ALLOW_STACK_EXECUTION = 0x20000; + const ROOT_SAFE = 0x40000; + const SETUID_SAFE = 0x80000; + const NO_REEXPORTED_DYLIBS = 0x100000; + const PIE = 0x200000; + const DEAD_STRIPPABLE_DYLIB = 0x400000; + const HAS_TLV_DESCRIPTORS = 0x800000; + const NO_HEAP_EXECUTION = 0x1000000; + const APP_EXTENSION_SAFE = 0x2000000; + const NLIST_OUTOFSYNC_WITH_DYLDINFO = 0x04000000; + const SIM_SUPPORT = 0x08000000; + const IMPLICIT_PAGEZERO = 0x10000000; + const DYLIB_IN_CACHE = 0x80000000; + } +} + +impl From for Flags { + fn from(value: u32) -> Self { + Flags::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: Flags) -> Self { + value.bits() + } +} + +/// Structure that represents the main Mach-O header (at the beginning of the file) +pub struct Header<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl FromFFI for Header<'_> { + fn from_ffi(hdr: cxx::UniquePtr) -> Self { + Self { + ptr: hdr, + _owner: PhantomData, + } + } +} + +impl Header<'_> { + /// The Mach-O magic bytes. These bytes determine whether it is + /// a 32 bits Mach-O, a 64 bits Mach-O files etc. + pub fn magic(&self) -> u32 { + self.ptr.magic() + } + + /// The CPU architecture targeted by this binary + pub fn cpu_type(&self) -> CpuType { + CpuType::from(self.ptr.cpu_type()) + } + + /// Return the CPU subtype supported by the Mach-O binary. + /// For ARM architectures, this value could represent the minimum version + /// for which the Mach-O binary has been compiled. + pub fn cpu_subtype(&self) -> u32 { + self.ptr.cpu_subtype() + } + + /// Return the type of the Mach-O file (executable, object, shared library, ...) + pub fn file_type(&self) -> FileType { + FileType::from(self.ptr.file_type()) + } + + /// Number of [`crate::macho::Commands`] present in the Mach-O binary + pub fn nb_cmds(&self) -> u32 { + self.ptr.nb_cmds() + } + + /// The raw size of **all** the load commands (`LC_xxx`) + pub fn sizeof_cmds(&self) -> u32 { + self.ptr.sizeof_cmds() + } + + /// Header flags + pub fn flags(&self) -> Flags { + Flags::from(self.ptr.flags()) + } + + /// According to the official specs, a reserved value + pub fn reserved(&self) -> u32 { + self.ptr.reserved() + } + + /// True if the binary is 32-bit + pub fn is_32bit(&self) -> bool { + self.ptr.is_32bit() + } + + /// True if the binary is 64-bit + pub fn is_64bit(&self) -> bool { + self.ptr.is_64bit() + } +} + +impl fmt::Debug for Header<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Header") + .field("magic", &self.magic()) + .field("cpu_type", &self.cpu_type()) + .field("cpu_subtype", &self.cpu_subtype()) + .field("file_type", &self.file_type()) + .field("nb_cmds", &self.nb_cmds()) + .field("sizeof_cmds", &self.sizeof_cmds()) + .field("flags", &self.flags()) + .field("reserved", &self.reserved()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/parser_config.rs b/vendor/lief/api/rust/crates/lief/src/macho/parser_config.rs new file mode 100644 index 0000000..4e05fb3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/parser_config.rs @@ -0,0 +1,76 @@ +use lief_ffi as ffi; + +/// This structure is used to tweak the MachO parser: +/// [`crate::macho::FatBinary::parse_with_config`] +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct Config { + /// Parse the Dyld export trie + pub parse_dyld_exports: bool, + + /// Parse the Dyld binding opcodes + pub parse_dyld_bindings: bool, + + /// Parse the Dyld rebase opcodes + pub parse_dyld_rebases: bool, + + /// Whether the overlay data should be parsed + pub parse_overlay: bool, + + /// When parsing Mach-O from memory, this option + /// can be used to *undo* relocations and symbols bindings. + /// + /// When activated, this option requires `parse_dyld_bindings` + /// and `parse_dyld_rebases` to be enabled. + pub fix_from_memory: bool, + + /// Whether the binary is coming/extracted from Dyld shared cache + pub from_dyld_shared_cache: bool, +} + +impl Default for Config { + fn default() -> Config { + Config { + parse_dyld_exports: true, + parse_dyld_bindings: true, + parse_dyld_rebases: true, + parse_overlay: true, + fix_from_memory: false, + from_dyld_shared_cache: false, + } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> cxx::UniquePtr { + let mut ptr = ffi::MachO_ParserConfig::create(); + ptr.pin_mut() + .set_parse_dyld_exports(self.parse_dyld_exports); + ptr.pin_mut() + .set_parse_dyld_bindings(self.parse_dyld_bindings); + ptr.pin_mut() + .set_parse_dyld_rebases(self.parse_dyld_rebases); + ptr.pin_mut().set_parse_overlay(self.parse_overlay); + ptr.pin_mut().set_fix_from_memory(self.fix_from_memory); + ptr.pin_mut() + .set_from_dyld_shared_cache(self.from_dyld_shared_cache); + ptr + } + + /// Configuration that parses all supported MachO structures (deep parse). + pub fn deep() -> Self { + Self::default() + } + + /// Configuration for a quick parse of the most important MachO structures. + pub fn quick() -> Self { + Self { + parse_dyld_exports: true, + parse_dyld_bindings: false, + parse_dyld_rebases: false, + parse_overlay: true, + fix_from_memory: false, + from_dyld_shared_cache: false, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/relocation.rs b/vendor/lief/api/rust/crates/lief/src/macho/relocation.rs new file mode 100644 index 0000000..453f469 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/relocation.rs @@ -0,0 +1,331 @@ +use std::marker::PhantomData; + +use super::commands::segment::Segment; +use super::section::Section; +use super::symbol::Symbol; +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; +use lief_ffi as ffi; + +#[derive(Debug)] +/// Enum that represents the different to encode/represent a relocation +/// in a Mach-O file +pub enum Relocation<'a> { + /// Relocation encoded in the rebase bytecode of `LC_DYLD_INFO` + Dyld(Dyld<'a>), + + /// Relocation encoded in chained fixup `LC_DYLD_CHAINED_FIXUPS` + Fixup(Fixup<'a>), + + /// Relocation of Mach-O object files (`.o`) wrapped by the sections + Object(Object<'a>), + + /// Fallback structure + Generic(Generic<'a>), +} + +impl<'a> FromFFI for Relocation<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::MachO_RelocationDyld::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Relocation::Dyld(Dyld::from_ffi(raw)) + } else if ffi::MachO_RelocationFixup::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Relocation::Fixup(Fixup::from_ffi(raw)) + } else if ffi::MachO_RelocationObject::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Relocation::Object(Object::from_ffi(raw)) + } else { + Relocation::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +/// Trait shared by **all** the relocations defined in [`Relocation`] +pub trait RelocationBase { + #[doc(hidden)] + fn get_base(&self) -> &ffi::MachO_Relocation; + + /// Indicates whether the item containing the address to be + /// relocated is part of a CPU instruction that uses PC-relative addressing. + /// + /// For addresses contained in PC-relative instructions, the CPU adds the address of + /// the instruction to the address contained in the instruction. + fn is_pc_relative(&self) -> bool { + self.get_base().is_pc_relative() + } + + /// CPU architecture targeted by this relocation + fn architecture(&self) -> u32 { + self.get_base().architecture() + } + + /// Origin of the relocation + fn origin(&self) -> Origin { + Origin::from(self.get_base().origin()) + } + + /// Symbol associated with the relocation (if any) + fn symbol(&self) -> Option> { + into_optional(self.get_base().symbol()) + } + + /// Section associated with the section (if any) + fn section(&self) -> Option> { + into_optional(self.get_base().section()) + } + + /// Segment command associated with the relocation (if any) + fn segment(&self) -> Option> { + into_optional(self.get_base().segment()) + } +} + +/// Origin of a Mach-O relocation +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Origin { + UNKNOWN, + DYLDINFO, + RELOC_TABLE, + CHAINED_FIXUPS, +} + +impl From for Origin { + fn from(value: u32) -> Self { + match value { + 0 => Origin::UNKNOWN, + 1 => Origin::DYLDINFO, + 2 => Origin::RELOC_TABLE, + 3 => Origin::CHAINED_FIXUPS, + _ => Origin::UNKNOWN, + } + } +} + +impl RelocationBase for Relocation<'_> { + fn get_base(&self) -> &ffi::MachO_Relocation { + match &self { + Relocation::Dyld(reloc) => reloc.get_base(), + + Relocation::Fixup(reloc) => reloc.get_base(), + + Relocation::Object(reloc) => reloc.get_base(), + + Relocation::Generic(reloc) => reloc.get_base(), + } + } +} + +impl generic::Relocation for Relocation<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + match &self { + Relocation::Dyld(reloc) => reloc.as_generic(), + + Relocation::Fixup(reloc) => reloc.as_generic(), + + Relocation::Object(reloc) => reloc.as_generic(), + + Relocation::Generic(reloc) => reloc.as_generic(), + } + } +} + +impl std::fmt::Debug for &dyn RelocationBase { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Section") + .field("is_pc_relative", &self.is_pc_relative()) + .field("symbol", &self.symbol()) + .field("section", &self.section()) + .field("segment", &self.segment()) + .finish() + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl RelocationBase for Generic<'_> { + fn get_base(&self) -> &ffi::MachO_Relocation { + self.ptr.as_ref().unwrap() + } +} + +impl generic::Relocation for Generic<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn RelocationBase; + f.debug_struct("Generic").field("base", &base).finish() + } +} + +impl FromFFI for Generic<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure that represents a bytecode rebase operation (from `LC_DYLD_INFO`) +pub struct Dyld<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Dyld<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RelocationBase for Dyld<'_> { + fn get_base(&self) -> &ffi::MachO_Relocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl generic::Relocation for Dyld<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl std::fmt::Debug for Dyld<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn RelocationBase; + f.debug_struct("Dyld").field("base", &base).finish() + } +} + +/// Structure that represents a fixup (i.e. relocation) from the `LC_DYLD_CHAINED_FIXUPS` +/// command +pub struct Fixup<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Fixup<'_> { + /// The value that should be set at the address pointed by [`crate::Relocation::address`] + /// if the imagebase chosen by the loader is [`crate::generic::Binary::imagebase`]. + /// Otherwise: [`Fixup::target`] - [`crate::generic::Binary::imagebase`] + new_imagebase. + pub fn target(&self) -> u64 { + self.ptr.target() + } + pub fn ptr_format(&self) -> u32 { + self.ptr.ptr_format() + } + + /// The address of this relocation is bound to its offset + pub fn offset(&self) -> u32 { + self.ptr.offset() + } + + /// Return the (unscaled) next offset in the chain + pub fn next(&self) -> u32 { + self.ptr.next() + } +} + +impl FromFFI for Fixup<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RelocationBase for Fixup<'_> { + fn get_base(&self) -> &ffi::MachO_Relocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl generic::Relocation for Fixup<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl std::fmt::Debug for Fixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn RelocationBase; + f.debug_struct("Fixup") + .field("base", &base) + .field("target", &self.target()) + .field("ptr_format", &self.ptr_format()) + .field("offset", &self.offset()) + .finish() + } +} + +/// This structure represents a relocation in a Mach-O object file (`.o`) +pub struct Object<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Object<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RelocationBase for Object<'_> { + fn get_base(&self) -> &ffi::MachO_Relocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl generic::Relocation for Object<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl std::fmt::Debug for Object<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn RelocationBase; + f.debug_struct("Object").field("base", &base).finish() + } +} + +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::MachO_Relocation, + ffi::MachO_Binary, + ffi::MachO_Binary_it_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/section.rs b/vendor/lief/api/rust/crates/lief/src/macho/section.rs new file mode 100644 index 0000000..b775b7f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/section.rs @@ -0,0 +1,354 @@ +use super::Relocation; +use super::commands::segment::Segment; +use super::thread_local_variables::ThreadLocalVariables; +use lief_ffi as ffi; +use std::fmt; +use std::marker::PhantomData; +use std::pin::Pin; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; + +use bitflags::bitflags; + +/// Enum that wraps all the Mach-O section types, dispatching to the +/// appropriate concrete type when extra semantics are available. +#[derive(Debug)] +pub enum Section<'a> { + /// A section without additional specialization. + Generic(Generic<'a>), + + /// A section whose type is [`Type::THREAD_LOCAL_VARIABLES`], providing access + /// to thread-local variable descriptors. + ThreadLocalVariables(ThreadLocalVariables<'a>), +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Type { + /// Regular section. + REGULAR, + /// Zero fill on demand section. + ZEROFILL, + /// Section with literal C strings. + CSTRING_LITERALS, + /// Section with 4 byte literals. + S_4BYTE_LITERALS, + /// Section with 8 byte literals. + S_8BYTE_LITERALS, + /// Section with pointers to literals. + LITERAL_POINTERS, + /// Section with non-lazy symbol pointers. + NON_LAZY_SYMBOL_POINTERS, + /// Section with lazy symbol pointers. + LAZY_SYMBOL_POINTERS, + /// Section with symbol stubs, byte size of stub in the Reserved2 field. + SYMBOL_STUBS, + /// Section with only function pointers for initialization. + MOD_INIT_FUNC_POINTERS, + /// Section with only function pointers for termination. + MOD_TERM_FUNC_POINTERS, + /// Section contains symbols that are to be coalesced. + COALESCED, + /// Zero fill on demand section (that can be larger than 4 gigabytes). + GB_ZEROFILL, + /// Section with only pairs of function pointers for interposing. + INTERPOSING, + /// Section with only 16 byte literals. + S_16BYTE_LITERALS, + /// Section contains DTrace Object Format. + DTRACE_DOF, + /// Section with lazy symbol pointers to lazy loaded dylibs. + LAZY_DYLIB_SYMBOL_POINTERS, + /// Thread local data section. + THREAD_LOCAL_REGULAR, + /// Thread local zerofill section. + THREAD_LOCAL_ZEROFILL, + /// Section with thread local variable structure data. + THREAD_LOCAL_VARIABLES, + /// Section with pointers to thread local structures. + THREAD_LOCAL_VARIABLE_POINTERS, + /// Section with thread local variable initialization pointers to functions. + THREAD_LOCAL_INIT_FUNCTION_POINTERS, + /// Section with 32-bit offsets to initializer functions + INIT_FUNC_OFFSETS, + UNKNOWN(u64), +} + +impl From for Type { + fn from(value: u64) -> Self { + match value { + 0x00000000 => Type::REGULAR, + 0x00000001 => Type::ZEROFILL, + 0x00000002 => Type::CSTRING_LITERALS, + 0x00000003 => Type::S_4BYTE_LITERALS, + 0x00000004 => Type::S_8BYTE_LITERALS, + 0x00000005 => Type::LITERAL_POINTERS, + 0x00000006 => Type::NON_LAZY_SYMBOL_POINTERS, + 0x00000007 => Type::LAZY_SYMBOL_POINTERS, + 0x00000008 => Type::SYMBOL_STUBS, + 0x00000009 => Type::MOD_INIT_FUNC_POINTERS, + 0x0000000a => Type::MOD_TERM_FUNC_POINTERS, + 0x0000000b => Type::COALESCED, + 0x0000000c => Type::GB_ZEROFILL, + 0x0000000d => Type::INTERPOSING, + 0x0000000e => Type::S_16BYTE_LITERALS, + 0x0000000f => Type::DTRACE_DOF, + 0x00000010 => Type::LAZY_DYLIB_SYMBOL_POINTERS, + 0x00000011 => Type::THREAD_LOCAL_REGULAR, + 0x00000012 => Type::THREAD_LOCAL_ZEROFILL, + 0x00000013 => Type::THREAD_LOCAL_VARIABLES, + 0x00000014 => Type::THREAD_LOCAL_VARIABLE_POINTERS, + 0x00000015 => Type::THREAD_LOCAL_INIT_FUNCTION_POINTERS, + 0x00000016 => Type::INIT_FUNC_OFFSETS, + _ => Type::UNKNOWN(value), + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Flags: u64 { + const PURE_INSTRUCTIONS = 0x80000000; + const NO_TOC = 0x40000000; + const STRIP_STATIC_SYMS = 0x20000000; + const NO_DEAD_STRIP = 0x10000000; + const LIVE_SUPPORT = 0x8000000; + const SELF_MODIFYING_CODE = 0x4000000; + const DEBUG_INFO = 0x2000000; + const SOME_INSTRUCTIONS = 0x400; + const EXT_RELOC = 0x200; + const LOC_RELOC = 0x100; + } +} + +impl From for Flags { + fn from(value: u64) -> Self { + Flags::from_bits_truncate(value) + } +} +impl From for u64 { + fn from(value: Flags) -> Self { + value.bits() + } +} +impl std::fmt::Display for Flags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +/// Trait shared by **all** Mach-O section types in the [`Section`] enum. +pub trait MachOSection { + #[doc(hidden)] + fn as_base(&self) -> &ffi::MachO_Section; + + #[doc(hidden)] + fn as_mut_base(&mut self) -> Pin<&mut ffi::MachO_Section>; + + /// Name of the segment that owns this section + fn segment_name(&self) -> String { + self.as_base().segment_name().to_string() + } + + /// Virtual base address of this section + fn address(&self) -> u64 { + self.as_base().address() + } + + /// Section alignment as a power of 2 + fn alignment(&self) -> u32 { + self.as_base().alignment() + } + + /// Offset of the relocation table. This value should be 0 + /// for executable and libraries as the relocations are managed by + /// [`crate::macho::Relocation::Dyld`] or [`crate::macho::Relocation::Fixup`] + /// + /// On the other hand, for object files (`.o`) this value should not be 0 (c.f. [`crate::macho::Relocation::Object`]) + fn relocation_offset(&self) -> u32 { + self.as_base().relocation_offset() + } + + /// Number of relocations associated with this section + fn numberof_relocations(&self) -> u32 { + self.as_base().numberof_relocations() + } + + fn raw_flags(&self) -> u32 { + self.as_base().raw_flags() + } + + /// Section's flags masked with `SECTION_FLAGS_MASK` + fn flags(&self) -> Flags { + Flags::from_bits_truncate(self.as_base().flags()) + } + + /// Type of the section. This value can help to determine the purpose of the section + fn section_type(&self) -> Type { + Type::from(self.as_base().section_type()) + } + + /// According to the official `loader.h` file, this value is reserved + /// for *offset* or *index* + fn reserved1(&self) -> u32 { + self.as_base().reserved1() + } + + /// According to the official `loader.h` file, this value is reserved + /// for *count* or *sizeof* + fn reserved2(&self) -> u32 { + self.as_base().reserved2() + } + + /// This value is only present for 64 bits Mach-O files. In that case, + /// the value is *reserved*. + fn reserved3(&self) -> u32 { + self.as_base().reserved3() + } + + /// Segment bound to this section + fn segment(&self) -> Option> { + into_optional(self.as_base().segment()) + } + + /// Iterator over the [`crate::macho::Relocation`] associated with this section + fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.as_base().relocations()) + } +} + +impl MachOSection for Generic<'_> { + fn as_base(&self) -> &ffi::MachO_Section { + self.ptr.as_ref().unwrap() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::MachO_Section> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap() as *const ffi::MachO_Section as *mut ffi::MachO_Section) + .as_mut() + .unwrap() + }) + } + } +} + +impl MachOSection for Section<'_> { + fn as_base(&self) -> &ffi::MachO_Section { + match self { + Section::Generic(s) => s.as_base(), + Section::ThreadLocalVariables(s) => s.as_base(), + } + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::MachO_Section> { + match self { + Section::Generic(s) => s.as_mut_base(), + Section::ThreadLocalVariables(s) => s.as_mut_base(), + } + } +} + +impl fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn generic::Section; + f.debug_struct("Generic") + .field("base", &base) + .field("segment_name", &MachOSection::segment_name(self)) + .field("address", &MachOSection::address(self)) + .field("alignment", &MachOSection::alignment(self)) + .field("relocation_offset", &MachOSection::relocation_offset(self)) + .field( + "numberof_relocations", + &MachOSection::numberof_relocations(self), + ) + .field("raw_flags", &MachOSection::raw_flags(self)) + .field("flags", &MachOSection::flags(self)) + .field("type", &MachOSection::section_type(self)) + .field("reserved1", &MachOSection::reserved1(self)) + .field("reserved2", &MachOSection::reserved2(self)) + .field("reserved3", &MachOSection::reserved3(self)) + .finish() + } +} + +impl<'a> FromFFI for Generic<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> FromFFI for Section<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let sec_ref = ffi_entry.as_ref().unwrap(); + if ffi::MachO_ThreadLocalVariables::classof(sec_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Section::ThreadLocalVariables(ThreadLocalVariables::from_ffi(raw)) + } else { + Section::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +impl generic::Section for Generic<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + self.as_base().as_ref() + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + unsafe { + Pin::new_unchecked({ + (self.as_generic() as *const ffi::AbstractSection as *mut ffi::AbstractSection) + .as_mut() + .unwrap() + }) + } + } +} + +impl generic::Section for Section<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + match self { + Section::Generic(s) => s.as_generic(), + Section::ThreadLocalVariables(s) => s.as_generic(), + } + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + match self { + Section::Generic(s) => s.as_generic_mut(), + Section::ThreadLocalVariables(s) => s.as_generic_mut(), + } + } +} + +declare_iterator!( + Sections, + Section<'a>, + ffi::MachO_Section, + ffi::MachO_Binary, + ffi::MachO_Binary_it_sections +); +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::MachO_Relocation, + ffi::MachO_Section, + ffi::MachO_Section_it_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/stub.rs b/vendor/lief/api/rust/crates/lief/src/macho/stub.rs new file mode 100644 index 0000000..b906448 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/stub.rs @@ -0,0 +1,71 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::{Error, to_result, to_slice}; + +use std::fmt; +use std::marker::PhantomData; + +/// This class represents a stub entry in sections like `__stubs,__auth_stubs`. +/// +/// It wraps assembly instructions which are used to access the *got* where the +/// address of the symbol is resolved. +/// +/// Example: +/// +/// ```text +/// 0000000236a3c1bc: ___memcpy_chk +/// adrp x17, #0x241513aa8 +/// add x17, x17, #0x241513aa8 +/// ldr x16, [x17] +/// braa x16, x17 +/// ``` +pub struct Stub<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl Stub<'_> { + /// The virtual address where the stub is located + pub fn address(&self) -> u64 { + self.ptr.address() + } + + /// The (raw) instructions of this entry as a slice of bytes + pub fn raw(&self) -> &[u8] { + to_slice!(self.ptr.raw()); + } + + /// + /// For instance, given this stub: + /// + /// ```text + /// 0x3eec: adrp x16, #4096 + /// 0x3ef0: ldr x16, [x16, #24] + /// 0x3ef4: br x16 + /// ``` + /// + /// The function returns: `0x4018`. + /// + ///
This function is only available with LIEF's extended version
+ pub fn target(&self) -> Result { + to_result!(ffi::MachO_Stub::target, self); + } +} + +impl fmt::Debug for Stub<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Stub") + .field("address", &self.address()) + .finish() + } +} + +impl FromFFI for Stub<'_> { + fn from_ffi(stub: cxx::UniquePtr) -> Self { + Self { + ptr: stub, + _owner: PhantomData, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/macho/symbol.rs b/vendor/lief/api/rust/crates/lief/src/macho/symbol.rs new file mode 100644 index 0000000..7b7ed60 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/symbol.rs @@ -0,0 +1,239 @@ +use std::marker::PhantomData; +use std::pin::Pin; + +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; +use lief_ffi as ffi; + +use super::commands::Dylib; +use super::{BindingInfo, ExportInfo}; + +/// Structure that represents a Symbol in a Mach-O file. +/// +/// A Mach-O symbol can come from: +/// 1. The symbols command (LC_SYMTAB / SymbolCommand) +/// 2. The Dyld Export trie +/// 3. The Dyld Symbol bindings +pub struct Symbol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Category { + NONE, + LOCAL, + EXTERNAL, + UNDEFINED, + INDIRECT_ABS, + INDIRECT_LOCAL, + INDIRECT_ABS_LOCAL, + UNKNOWN(u32), +} + +impl From for Category { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Category::NONE, + 0x00000001 => Category::LOCAL, + 0x00000002 => Category::EXTERNAL, + 0x00000003 => Category::UNDEFINED, + 0x00000004 => Category::INDIRECT_ABS, + 0x00000005 => Category::INDIRECT_LOCAL, + 0x00000006 => Category::INDIRECT_ABS_LOCAL, + _ => Category::UNKNOWN(value), + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Origin { + DYLD_EXPORT, + DYLD_BIND, + LC_SYMTAB, + UNKNOWN(u32), +} + +impl From for Origin { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Origin::DYLD_EXPORT, + 0x00000002 => Origin::DYLD_BIND, + 0x00000003 => Origin::LC_SYMTAB, + _ => Origin::UNKNOWN(value), + } + } +} + +/// Symbol type as defined by `nlist_xx.n_type & N_TYPE` +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Type { + /// The symbol is undefined + UNDEFINED, + /// The symbol is absolute + ABSOLUTE_SYM, + /// The symbol is defined in a specific section + SECTION, + /// The symbol is undefined and the image is using a prebound value + PREBOUND, + /// The symbol is defined to be the same as another symbol + INDIRECT, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x0 => Type::UNDEFINED, + 0x2 => Type::ABSOLUTE_SYM, + 0xe => Type::SECTION, + 0xc => Type::PREBOUND, + 0xa => Type::INDIRECT, + _ => Type::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Type) -> u32 { + match value { + Type::UNDEFINED => 0x0, + Type::ABSOLUTE_SYM => 0x2, + Type::SECTION => 0xe, + Type::PREBOUND => 0xc, + Type::INDIRECT => 0xa, + Type::UNKNOWN(v) => v, + } + } +} + +impl Symbol<'_> { + pub fn get_type(&self) -> u8 { + self.ptr.get_type() + } + + /// It returns the number of sections in which this symbol can be found. + /// If the symbol can't be found in any section, it returns 0 (`NO_SECT`) + pub fn numberof_sections(&self) -> u8 { + self.ptr.numberof_sections() + } + + /// Return information about the symbol + pub fn description(&self) -> u16 { + self.ptr.description() + } + + /// Return the origin of the symbol: from `LC_SYMTAB` from the Dyld information, ... + pub fn origin(&self) -> Origin { + Origin::from(self.ptr.origin()) + } + + /// Category of the symbol according to the `LC_DYSYMTAB` command + pub fn category(&self) -> Category { + Category::from(self.ptr.category()) + } + + /// Export info associated with this symbol (if any) + pub fn export_info(&self) -> Option> { + into_optional(self.ptr.export_info()) + } + + /// Binding info associated with this symbol (if any) + pub fn binding_info(&self) -> Option> { + into_optional(self.ptr.binding_info()) + } + + /// Return the library in which this symbol is defined (if any) + pub fn library(&self) -> Option> { + into_optional(self.ptr.library()) + } + + /// Whether this symbol is external + pub fn is_external(&self) -> bool { + self.ptr.is_external() + } + + /// Return the library ordinal for this symbol. A negative ordinal indicates + /// a special value (e.g., -1 for `SELF_LIBRARY`, -2 for `MAIN_EXECUTABLE`) + pub fn library_ordinal(&self) -> i32 { + self.ptr.library_ordinal() + } + + /// Try to demangle the symbol or return an empty string if it is not possible + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } +} + +impl std::fmt::Debug for Symbol<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("Symbol") + .field("base", &base) + .field("type", &self.get_type()) + .field("numberof_sections", &self.numberof_sections()) + .field("description", &self.description()) + .field("origin", &self.origin()) + .field("category", &self.category()) + .field("export_info", &self.export_info()) + .field("binding_info", &self.binding_info()) + .field("library", &self.library()) + .finish() + } +} + +impl<'a> FromFFI for Symbol<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsFFI for Symbol<'_> { + fn as_ffi(&self) -> &ffi::MachO_Symbol { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> Pin<&mut ffi::MachO_Symbol> { + self.ptr.pin_mut() + } +} + +impl generic::Symbol for Symbol<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +declare_iterator!( + Symbols, + Symbol<'a>, + ffi::MachO_Symbol, + ffi::MachO_Binary, + ffi::MachO_Binary_it_symbols +); + +declare_iterator!( + ExportedSymbols, + Symbol<'a>, + ffi::MachO_Symbol, + ffi::MachO_Binary, + ffi::MachO_Binary_it_exported_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/macho/thread_local_variables.rs b/vendor/lief/api/rust/crates/lief/src/macho/thread_local_variables.rs new file mode 100644 index 0000000..9f29f71 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/macho/thread_local_variables.rs @@ -0,0 +1,144 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; +use crate::macho::section::MachOSection; +use std::fmt; +use std::marker::PhantomData; +use std::pin::Pin; + +/// This class represents a MachO section whose type is +/// [`crate::macho::section::Type::THREAD_LOCAL_VARIABLES`]. +/// +/// It contains an array of thread-local variable descriptors ([`Thunk`]) used +/// by dyld to lazily initialize thread-local storage on first access. +pub struct ThreadLocalVariables<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_Binary>, +} + +impl ThreadLocalVariables<'_> { + /// Number of [`Thunk`] descriptors in this section + pub fn nb_thunks(&self) -> u64 { + self.ptr.nb_thunks().try_into().unwrap() + } + + /// Iterator over the [`Thunk`] descriptors stored in this section + pub fn thunks(&self) -> Thunks<'_> { + Thunks::new(self.ptr.thunks()) + } + + /// Return the [`Thunk`] at the given index, or `None` if out of range. + pub fn get(&self, idx: u64) -> Option> { + into_optional(self.ptr.get_thunk(idx)) + } + + /// Change the [`Thunk`] at the given index. + pub fn set(&mut self, idx: u64, thunk: &Thunk<'_>) { + self.ptr + .pin_mut() + .set_thunk(idx, thunk.func(), thunk.key(), thunk.offset()); + } +} + +impl fmt::Debug for ThreadLocalVariables<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("ThreadLocalVariables") + .field("nb_thunks", &self.nb_thunks()) + .finish() + } +} + +impl<'a> FromFFI for ThreadLocalVariables<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl generic::Section for ThreadLocalVariables<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + self.as_base().as_ref() + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + unsafe { + Pin::new_unchecked({ + (self.as_generic() as *const ffi::AbstractSection as *mut ffi::AbstractSection) + .as_mut() + .unwrap() + }) + } + } +} + +impl MachOSection for ThreadLocalVariables<'_> { + fn as_base(&self) -> &ffi::MachO_Section { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_mut_base(&mut self) -> Pin<&mut ffi::MachO_Section> { + unsafe { + Pin::new_unchecked({ + (self.as_base() as *const ffi::MachO_Section as *mut ffi::MachO_Section) + .as_mut() + .unwrap() + }) + } + } +} + +/// Descriptor for a single thread-local variable. +/// +/// The layout mirrors the `tlv_descriptor` structure from ``. +pub struct Thunk<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::MachO_ThreadLocalVariables>, +} + +impl Thunk<'_> { + /// Address of the initializer function (`tlv_thunk`) + pub fn func(&self) -> u64 { + self.ptr.func() + } + + /// `pthread_key_t` key used by the runtime + pub fn key(&self) -> u64 { + self.ptr.key() + } + + /// Offset of the variable in the TLS block + pub fn offset(&self) -> u64 { + self.ptr.offset() + } +} + +impl fmt::Debug for Thunk<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Thunk") + .field("func", &format_args!("{:#x}", self.func())) + .field("key", &format_args!("{:#x}", self.key())) + .field("offset", &format_args!("{:#x}", self.offset())) + .finish() + } +} + +impl<'a> FromFFI for Thunk<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + Thunks, + Thunk<'a>, + ffi::MachO_ThreadLocalVariables_Thunk, + ffi::MachO_ThreadLocalVariables, + ffi::MachO_ThreadLocalVariables_it_thunks +); diff --git a/vendor/lief/api/rust/crates/lief/src/objc.rs b/vendor/lief/api/rust/crates/lief/src/objc.rs new file mode 100644 index 0000000..3d78f22 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc.rs @@ -0,0 +1,48 @@ +//! Module for Objective-C metadata +//! +//! This module contains the support of Objective-C metadata embedded in Mach-O +//! [`crate::macho::Binary`]. +//! +//! One can access this metadata using the [`crate::macho::Binary::objc_metadata`] function +//! +//! ``` +//! fn inspect_objc(macho: &lief::macho::Binary) { +//! let metadata: lief::objc::Metadata = macho.objc_metadata().expect("Can't access metadata"); +//! for class in metadata.classes() { +//! println!("{}", class.to_decl()); +//! } +//! } +//! ``` + +pub mod category; +pub mod class; +pub mod decl_opt; +pub mod ivar; +pub mod metadata; +pub mod method; +pub mod property; +pub mod protocol; + +#[doc(inline)] +pub use metadata::Metadata; + +#[doc(inline)] +pub use class::Class; + +#[doc(inline)] +pub use category::Category; + +#[doc(inline)] +pub use method::Method; + +#[doc(inline)] +pub use property::Property; + +#[doc(inline)] +pub use protocol::Protocol; + +#[doc(inline)] +pub use ivar::IVar; + +#[doc(inline)] +pub use decl_opt::DeclOpt; diff --git a/vendor/lief/api/rust/crates/lief/src/objc/category.rs b/vendor/lief/api/rust/crates/lief/src/objc/category.rs new file mode 100644 index 0000000..227c88c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/category.rs @@ -0,0 +1,84 @@ +use lief_ffi as ffi; + +use super::{DeclOpt, Method, Property, Protocol}; +use crate::common::FromFFI; +use crate::declare_fwd_iterator; +use std::marker::PhantomData; + +/// This class represents an Objective-C category (e.g. +/// `@interface NSString (MyAdditions)`) +pub struct Category<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Category<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Category<'_> { + /// Name of the category + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// (demangled) name of the class extended by this category + pub fn class_name(&self) -> String { + self.ptr.class_name().to_string() + } + + /// Iterator over the different [`Method`] defined by this category + pub fn methods(&self) -> Methods<'_> { + Methods::new(self.ptr.methods()) + } + + /// Iterator over the different [`Protocol`] adopted by this category + pub fn protocols(&self) -> Protocols<'_> { + Protocols::new(self.ptr.protocols()) + } + + /// Iterator over the [`Property`] of this category + pub fn properties(&self) -> Properties<'_> { + Properties::new(self.ptr.properties()) + } + + /// Generate a header-like string for this specific category + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same behavior as [`Category::to_decl`] but with an additional + /// [`DeclOpt`] parameter to customize the output + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Methods, + Method<'a>, + ffi::ObjC_Method, + ffi::ObjC_Category, + ffi::ObjC_Category_it_methods +); + +declare_fwd_iterator!( + Protocols, + Protocol<'a>, + ffi::ObjC_Protocol, + ffi::ObjC_Category, + ffi::ObjC_Category_it_protocols +); + +declare_fwd_iterator!( + Properties, + Property<'a>, + ffi::ObjC_Property, + ffi::ObjC_Category, + ffi::ObjC_Category_it_properties +); diff --git a/vendor/lief/api/rust/crates/lief/src/objc/class.rs b/vendor/lief/api/rust/crates/lief/src/objc/class.rs new file mode 100644 index 0000000..45f1ec2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/class.rs @@ -0,0 +1,116 @@ +use lief_ffi as ffi; + +use super::{DeclOpt, IVar, Method, Property, Protocol}; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use std::marker::PhantomData; + +/// This class represents an Objective-C class (`@interface`) +pub struct Class<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Class<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Class<'_> { + /// Name of the class + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Demangled name of the class + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } + + /// Parent class in case of inheritance + pub fn super_class(&self) -> Option> { + into_optional(self.ptr.super_class()) + } + + /// (raw) name of the superclass (empty for root classes or when it could + /// not be resolved). + pub fn super_name(&self) -> String { + self.ptr.super_name().to_string() + } + + /// Demangled name of the superclass. + pub fn demangled_super_name(&self) -> String { + self.ptr.demangled_super_name().to_string() + } + + pub fn is_meta(&self) -> bool { + self.ptr.is_meta() + } + + /// Iterator over the different [`Method`] defined by this class + pub fn methods(&self) -> Methods<'_> { + Methods::new(self.ptr.methods()) + } + + /// Iterator over the different [`Protocol`] implemented by this class + pub fn protocols(&self) -> Protocols<'_> { + Protocols::new(self.ptr.protocols()) + } + + /// Iterator over the [`Property`] of this class + pub fn properties(&self) -> Properties<'_> { + Properties::new(self.ptr.properties()) + } + + /// Iterator over the different instance variables ([`IVar`]) defined in this class + pub fn ivars(&self) -> IVars<'_> { + IVars::new(self.ptr.ivars()) + } + + /// Generate a header-like string for this specific class + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same behavior as [`Class::to_decl`] but with an additional + /// [`DeclOpt`] parameter to customize the output + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Methods, + Method<'a>, + ffi::ObjC_Method, + ffi::ObjC_Class, + ffi::ObjC_Class_it_methods +); + +declare_fwd_iterator!( + Protocols, + Protocol<'a>, + ffi::ObjC_Protocol, + ffi::ObjC_Class, + ffi::ObjC_Class_it_protocols +); + +declare_fwd_iterator!( + Properties, + Property<'a>, + ffi::ObjC_Property, + ffi::ObjC_Class, + ffi::ObjC_Class_it_properties +); + +declare_fwd_iterator!( + IVars, + IVar<'a>, + ffi::ObjC_IVar, + ffi::ObjC_Class, + ffi::ObjC_Class_it_ivars +); diff --git a/vendor/lief/api/rust/crates/lief/src/objc/decl_opt.rs b/vendor/lief/api/rust/crates/lief/src/objc/decl_opt.rs new file mode 100644 index 0000000..2432639 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/decl_opt.rs @@ -0,0 +1,25 @@ +use lief_ffi as ffi; + +/// This structure wraps options to tweak the generated output of +/// functions like [`crate::objc::Metadata::to_decl_with_opt`] +pub struct DeclOpt { + /// Whether annotations like method's address should be printed + pub show_annotations: bool, +} + +impl Default for DeclOpt { + fn default() -> DeclOpt { + DeclOpt { + show_annotations: true, + } + } +} + +impl DeclOpt { + #[doc(hidden)] + pub fn to_ffi(&self) -> ffi::ObjC_DeclOpt { + ffi::ObjC_DeclOpt { + show_annotations: self.show_annotations, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/objc/ivar.rs b/vendor/lief/api/rust/crates/lief/src/objc/ivar.rs new file mode 100644 index 0000000..d449a4a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/ivar.rs @@ -0,0 +1,31 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// This structure represents an instance variable (ivar) +pub struct IVar<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for IVar<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl IVar<'_> { + /// Name of the instance variable + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Type of the instance var in its mangled representation (`[29i]`) + pub fn mangled_type(&self) -> String { + self.ptr.mangled_type().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/objc/metadata.rs b/vendor/lief/api/rust/crates/lief/src/objc/metadata.rs new file mode 100644 index 0000000..62f37b6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/metadata.rs @@ -0,0 +1,90 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use std::marker::PhantomData; + +use super::{Category, Class, DeclOpt, Protocol}; + +/// This structure is the main interface to inspect Objective-C metadata +/// +/// It can be accessed using the function [`crate::macho::Binary::objc_metadata`] +pub struct Metadata<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Metadata<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Metadata<'_> { + /// Return an iterator over the different Objective-C classes (`@interface`) + pub fn classes(&self) -> Classes<'_> { + Classes::new(self.ptr.classes()) + } + + /// Return an iterator over the Objective-C protocols declared in this binary (`@protocol`). + pub fn protocols(&self) -> Protocols<'_> { + Protocols::new(self.ptr.protocols()) + } + + /// Return an iterator over the Objective-C categories declared in this binary + /// (e.g. `@interface NSString (MyAdditions)`). + pub fn categories(&self) -> Categories<'_> { + Categories::new(self.ptr.categories()) + } + + /// Try to find the Objective-C class with the given **mangled** name + pub fn class_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.get_class(&__cxx_s)) + } + + /// Try to find the Objective-C protocol with the given **mangled** name + pub fn protocol_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.get_protocol(&__cxx_s)) + } + + /// Generate a header-like string of all the Objective-C metadata identified in the + /// binary. + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same behavior as [`Metadata::to_decl`] but with an additional + /// [`DeclOpt`] parameter to customize the output + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Classes, + Class<'a>, + ffi::ObjC_Class, + ffi::ObjC_Metadata, + ffi::ObjC_Metadata_it_classes +); + +declare_fwd_iterator!( + Protocols, + Protocol<'a>, + ffi::ObjC_Protocol, + ffi::ObjC_Metadata, + ffi::ObjC_Metadata_it_protocols +); + +declare_fwd_iterator!( + Categories, + Category<'a>, + ffi::ObjC_Category, + ffi::ObjC_Metadata, + ffi::ObjC_Metadata_it_categories +); diff --git a/vendor/lief/api/rust/crates/lief/src/objc/method.rs b/vendor/lief/api/rust/crates/lief/src/objc/method.rs new file mode 100644 index 0000000..3ddd4f9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/method.rs @@ -0,0 +1,41 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// This structure represents an Objective-C Method +pub struct Method<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Method<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Method<'_> { + /// Name of the method + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Prototype of the method in its mangled representation (e.g. `@16@0:8`) + pub fn mangled_type(&self) -> String { + self.ptr.mangled_type().to_string() + } + + /// Virtual address where this method is implemented in the binary + pub fn address(&self) -> u64 { + self.ptr.address() + } + + /// Whether it's an instance method + pub fn is_instance(&self) -> bool { + self.ptr.is_instance() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/objc/property.rs b/vendor/lief/api/rust/crates/lief/src/objc/property.rs new file mode 100644 index 0000000..153c2c3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/property.rs @@ -0,0 +1,31 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// This class represents a `@property` in Objective-C +pub struct Property<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Property<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Property<'_> { + /// Name of the property + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// (raw) property's attributes (e.g. `T@"NSString",C,D,N`) + pub fn attribute(&self) -> String { + self.ptr.attribute().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/objc/protocol.rs b/vendor/lief/api/rust/crates/lief/src/objc/protocol.rs new file mode 100644 index 0000000..d22a3ba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/objc/protocol.rs @@ -0,0 +1,93 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_fwd_iterator; +use std::marker::PhantomData; + +use super::{DeclOpt, Method, Property}; + +/// This class represents an Objective-C `@protocol` +pub struct Protocol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Protocol<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl Protocol<'_> { + /// Mangled name of the protocol + pub fn mangled_name(&self) -> String { + self.ptr.mangled_name().to_string() + } + + /// Iterator over the protocols adopted by this protocol (e.g. the + /// `` in `@protocol Foo `). + pub fn protocols(&self) -> Protocols<'_> { + Protocols::new(self.ptr.protocols()) + } + + /// Iterator over the methods that could be overridden + pub fn optional_methods(&self) -> OptionalMethods<'_> { + OptionalMethods::new(self.ptr.optional_methods()) + } + + /// Iterator over the methods of this protocol that must be implemented + pub fn required_methods(&self) -> RequiredMethods<'_> { + RequiredMethods::new(self.ptr.required_methods()) + } + + /// Iterator over the properties defined in this protocol + pub fn properties(&self) -> Properties<'_> { + Properties::new(self.ptr.properties()) + } + + /// Generate a header-like string for this specific class + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same behavior as [`Protocol::to_decl`] but with an additional + /// [`DeclOpt`] parameter to customize the output + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +declare_fwd_iterator!( + Protocols, + Protocol<'a>, + ffi::ObjC_Protocol, + ffi::ObjC_Protocol, + ffi::ObjC_Protocol_it_protocols +); + +declare_fwd_iterator!( + OptionalMethods, + Method<'a>, + ffi::ObjC_Method, + ffi::ObjC_Protocol, + ffi::ObjC_Protocol_it_opt_methods +); + +declare_fwd_iterator!( + RequiredMethods, + Method<'a>, + ffi::ObjC_Method, + ffi::ObjC_Protocol, + ffi::ObjC_Protocol_it_req_methods +); + +declare_fwd_iterator!( + Properties, + Property<'a>, + ffi::ObjC_Property, + ffi::ObjC_Protocol, + ffi::ObjC_Protocol_it_properties +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb.rs b/vendor/lief/api/rust/crates/lief/src/pdb.rs new file mode 100644 index 0000000..97ccece --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb.rs @@ -0,0 +1,59 @@ +//! Module for processing PDB file +//! +//! This module exposes an API similar to the [`crate::dwarf`] module to process PDB +//! files. +//! +//! One can instantiate a [`crate::pdb::DebugInfo`] using either [`crate::generic::Binary::debug_info`] or +//! [`crate::pdb::load`]. +//! +//! ``` +//! fn read_pdb(file: &str) { +//! let pdb = lief::pdb::load(file).unwrap(); +//! for symbol in pdb.public_symbols() { +//! println!("name: {}", symbol.name()); +//! } +//! } +//! ``` + +use std::path::Path; + +use lief_ffi as ffi; + +use crate::common::into_optional; + +pub mod build_metadata; +pub mod compilation_unit; +pub mod debug_info; +pub mod function; +pub mod public_symbol; +pub mod types; + +#[doc(inline)] +pub use debug_info::DebugInfo; + +#[doc(inline)] +pub use compilation_unit::CompilationUnit; + +#[doc(inline)] +pub use public_symbol::PublicSymbol; + +#[doc(inline)] +pub use function::Function; + +#[doc(inline)] +pub use types::Type; + +#[doc(inline)] +pub use build_metadata::BuildMetadata; + +/// Load a PDB from its filepath +pub fn load>(path: P) -> Option> { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + into_optional(ffi::PDB_DebugInfo::from_file(&__cxx_s)) +} + +/// Check if the given file is a `PDB` +pub fn is_pdb>(path: P) -> bool { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + ffi::PDB_Utils::is_pdb(&__cxx_s) +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/build_metadata.rs b/vendor/lief/api/rust/crates/lief/src/pdb/build_metadata.rs new file mode 100644 index 0000000..3222064 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/build_metadata.rs @@ -0,0 +1,452 @@ +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use crate::common::FromFFI; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Cpu { + INTEL_8080, + INTEL_8086, + INTEL_80286, + INTEL_80386, + INTEL_80486, + PENTIUM, + PENTIUMPRO, + PENTIUM3, + MIPS, + MIPS16, + MIPS32, + MIPS64, + MIPSI, + MIPSII, + MIPSIII, + MIPSIV, + MIPSV, + M68000, + M68010, + M68020, + M68030, + M68040, + ALPHA, + ALPHA_21164, + ALPHA_21164A, + ALPHA_21264, + ALPHA_21364, + PPC601, + PPC603, + PPC604, + PPC620, + PPCFP, + PPCBE, + SH3, + SH3E, + SH3DSP, + SH4, + SHMEDIA, + ARM3, + ARM4, + ARM4T, + ARM5, + ARM5T, + ARM6, + ARM_XMAC, + ARM_WMMX, + ARM7, + OMNI, + IA64, + IA64_2, + CEE, + AM33, + M32R, + TRICORE, + X64, + EBC, + THUMB, + ARMNT, + ARM64, + HYBRID_X86ARM64, + ARM64EC, + ARM64X, + D3D11_SHADER, + UNKNOWN(u16), +} + +impl From for Cpu { + fn from(value: u16) -> Self { + match value { + 0x00000000 => Cpu::INTEL_8080, + 0x00000001 => Cpu::INTEL_8086, + 0x00000002 => Cpu::INTEL_80286, + 0x00000003 => Cpu::INTEL_80386, + 0x00000004 => Cpu::INTEL_80486, + 0x00000005 => Cpu::PENTIUM, + 0x00000006 => Cpu::PENTIUMPRO, + 0x00000007 => Cpu::PENTIUM3, + 0x00000010 => Cpu::MIPS, + 0x00000011 => Cpu::MIPS16, + 0x00000012 => Cpu::MIPS32, + 0x00000013 => Cpu::MIPS64, + 0x00000014 => Cpu::MIPSI, + 0x00000015 => Cpu::MIPSII, + 0x00000016 => Cpu::MIPSIII, + 0x00000017 => Cpu::MIPSIV, + 0x00000018 => Cpu::MIPSV, + 0x00000020 => Cpu::M68000, + 0x00000021 => Cpu::M68010, + 0x00000022 => Cpu::M68020, + 0x00000023 => Cpu::M68030, + 0x00000024 => Cpu::M68040, + 0x00000030 => Cpu::ALPHA, + 0x00000031 => Cpu::ALPHA_21164, + 0x00000032 => Cpu::ALPHA_21164A, + 0x00000033 => Cpu::ALPHA_21264, + 0x00000034 => Cpu::ALPHA_21364, + 0x00000040 => Cpu::PPC601, + 0x00000041 => Cpu::PPC603, + 0x00000042 => Cpu::PPC604, + 0x00000043 => Cpu::PPC620, + 0x00000044 => Cpu::PPCFP, + 0x00000045 => Cpu::PPCBE, + 0x00000050 => Cpu::SH3, + 0x00000051 => Cpu::SH3E, + 0x00000052 => Cpu::SH3DSP, + 0x00000053 => Cpu::SH4, + 0x00000054 => Cpu::SHMEDIA, + 0x00000060 => Cpu::ARM3, + 0x00000061 => Cpu::ARM4, + 0x00000062 => Cpu::ARM4T, + 0x00000063 => Cpu::ARM5, + 0x00000064 => Cpu::ARM5T, + 0x00000065 => Cpu::ARM6, + 0x00000066 => Cpu::ARM_XMAC, + 0x00000067 => Cpu::ARM_WMMX, + 0x00000068 => Cpu::ARM7, + 0x00000070 => Cpu::OMNI, + 0x00000080 => Cpu::IA64, + 0x00000081 => Cpu::IA64_2, + 0x00000090 => Cpu::CEE, + 0x000000a0 => Cpu::AM33, + 0x000000b0 => Cpu::M32R, + 0x000000c0 => Cpu::TRICORE, + 0x000000d0 => Cpu::X64, + 0x000000e0 => Cpu::EBC, + 0x000000f0 => Cpu::THUMB, + 0x000000f4 => Cpu::ARMNT, + 0x000000f6 => Cpu::ARM64, + 0x000000f7 => Cpu::HYBRID_X86ARM64, + 0x000000f8 => Cpu::ARM64EC, + 0x000000f9 => Cpu::ARM64X, + 0x00000100 => Cpu::D3D11_SHADER, + _ => Cpu::UNKNOWN(value), + } + } +} + +impl From for u16 { + fn from(value: Cpu) -> u16 { + match value { + Cpu::INTEL_8080 => 0x00000000, + Cpu::INTEL_8086 => 0x00000001, + Cpu::INTEL_80286 => 0x00000002, + Cpu::INTEL_80386 => 0x00000003, + Cpu::INTEL_80486 => 0x00000004, + Cpu::PENTIUM => 0x00000005, + Cpu::PENTIUMPRO => 0x00000006, + Cpu::PENTIUM3 => 0x00000007, + Cpu::MIPS => 0x00000010, + Cpu::MIPS16 => 0x00000011, + Cpu::MIPS32 => 0x00000012, + Cpu::MIPS64 => 0x00000013, + Cpu::MIPSI => 0x00000014, + Cpu::MIPSII => 0x00000015, + Cpu::MIPSIII => 0x00000016, + Cpu::MIPSIV => 0x00000017, + Cpu::MIPSV => 0x00000018, + Cpu::M68000 => 0x00000020, + Cpu::M68010 => 0x00000021, + Cpu::M68020 => 0x00000022, + Cpu::M68030 => 0x00000023, + Cpu::M68040 => 0x00000024, + Cpu::ALPHA => 0x00000030, + Cpu::ALPHA_21164 => 0x00000031, + Cpu::ALPHA_21164A => 0x00000032, + Cpu::ALPHA_21264 => 0x00000033, + Cpu::ALPHA_21364 => 0x00000034, + Cpu::PPC601 => 0x00000040, + Cpu::PPC603 => 0x00000041, + Cpu::PPC604 => 0x00000042, + Cpu::PPC620 => 0x00000043, + Cpu::PPCFP => 0x00000044, + Cpu::PPCBE => 0x00000045, + Cpu::SH3 => 0x00000050, + Cpu::SH3E => 0x00000051, + Cpu::SH3DSP => 0x00000052, + Cpu::SH4 => 0x00000053, + Cpu::SHMEDIA => 0x00000054, + Cpu::ARM3 => 0x00000060, + Cpu::ARM4 => 0x00000061, + Cpu::ARM4T => 0x00000062, + Cpu::ARM5 => 0x00000063, + Cpu::ARM5T => 0x00000064, + Cpu::ARM6 => 0x00000065, + Cpu::ARM_XMAC => 0x00000066, + Cpu::ARM_WMMX => 0x00000067, + Cpu::ARM7 => 0x00000068, + Cpu::OMNI => 0x00000070, + Cpu::IA64 => 0x00000080, + Cpu::IA64_2 => 0x00000081, + Cpu::CEE => 0x00000090, + Cpu::AM33 => 0x000000a0, + Cpu::M32R => 0x000000b0, + Cpu::TRICORE => 0x000000c0, + Cpu::X64 => 0x000000d0, + Cpu::EBC => 0x000000e0, + Cpu::THUMB => 0x000000f0, + Cpu::ARMNT => 0x000000f4, + Cpu::ARM64 => 0x000000f6, + Cpu::HYBRID_X86ARM64 => 0x000000f7, + Cpu::ARM64EC => 0x000000f8, + Cpu::ARM64X => 0x000000f9, + Cpu::D3D11_SHADER => 0x00000100, + Cpu::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Lang { + C, + CPP, + FORTRAN, + MASM, + PASCAL_LANG, + BASIC, + COBOL, + LINK, + CVTRES, + CVTPGD, + CSHARP, + VB, + ILASM, + JAVA, + JSCRIPT, + MSIL, + HLSL, + OBJC, + OBJCPP, + SWIFT, + ALIASOBJ, + RUST, + GO, + UNKNOWN(u8), +} + +impl From for Lang { + fn from(value: u8) -> Self { + match value { + 0x00000000 => Lang::C, + 0x00000001 => Lang::CPP, + 0x00000002 => Lang::FORTRAN, + 0x00000003 => Lang::MASM, + 0x00000004 => Lang::PASCAL_LANG, + 0x00000005 => Lang::BASIC, + 0x00000006 => Lang::COBOL, + 0x00000007 => Lang::LINK, + 0x00000008 => Lang::CVTRES, + 0x00000009 => Lang::CVTPGD, + 0x0000000a => Lang::CSHARP, + 0x0000000b => Lang::VB, + 0x0000000c => Lang::ILASM, + 0x0000000d => Lang::JAVA, + 0x0000000e => Lang::JSCRIPT, + 0x0000000f => Lang::MSIL, + 0x00000010 => Lang::HLSL, + 0x00000011 => Lang::OBJC, + 0x00000012 => Lang::OBJCPP, + 0x00000013 => Lang::SWIFT, + 0x00000014 => Lang::ALIASOBJ, + 0x00000015 => Lang::RUST, + 0x00000016 => Lang::GO, + _ => Lang::UNKNOWN(value), + } + } +} +impl From for u8 { + fn from(value: Lang) -> u8 { + match value { + Lang::C => 0x00000000, + Lang::CPP => 0x00000001, + Lang::FORTRAN => 0x00000002, + Lang::MASM => 0x00000003, + Lang::PASCAL_LANG => 0x00000004, + Lang::BASIC => 0x00000005, + Lang::COBOL => 0x00000006, + Lang::LINK => 0x00000007, + Lang::CVTRES => 0x00000008, + Lang::CVTPGD => 0x00000009, + Lang::CSHARP => 0x0000000a, + Lang::VB => 0x0000000b, + Lang::ILASM => 0x0000000c, + Lang::JAVA => 0x0000000d, + Lang::JSCRIPT => 0x0000000e, + Lang::MSIL => 0x0000000f, + Lang::HLSL => 0x00000010, + Lang::OBJC => 0x00000011, + Lang::OBJCPP => 0x00000012, + Lang::SWIFT => 0x00000013, + Lang::ALIASOBJ => 0x00000014, + Lang::RUST => 0x00000015, + Lang::GO => 0x00000016, + Lang::UNKNOWN(value) => value, + } + } +} + +/// This class wraps build metadata represented by the codeview symbols: +/// `S_COMPILE3, S_COMPILE2, S_BUILDINFO` +pub struct BuildMetadata<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for BuildMetadata<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl BuildMetadata<'_> { + /// Version of the frontend (e.g. `19.36.32537`) + pub fn frontend_version(&self) -> Version { + Version::from_ffi(self.ptr.frontend_version()) + } + + /// Version of the backend (e.g. `14.36.32537`) + pub fn backend_version(&self) -> Version { + Version::from_ffi(self.ptr.backend_version()) + } + + /// Version of the *tool* as a string. For instance, `Microsoft (R) CVTRES`, + /// `Microsoft (R) LINK`. + pub fn version(&self) -> String { + self.ptr.version().to_string() + } + + /// Source language + pub fn language(&self) -> Lang { + Lang::from(self.ptr.language()) + } + + /// Target CPU + pub fn target_cpu(&self) -> Cpu { + Cpu::from(self.ptr.target_cpu()) + } + + /// Environment information represented by the `S_ENVBLOCK` symbol + pub fn env(&self) -> Vec { + self.ptr + .env() + .iter() + .map(|e| e.to_string()) + .collect::>() + } + + /// Build information represented by the `S_BUILDINFO` symbol + pub fn build_info(&self) -> Option { + BuildInfo::from_ffi(self.ptr.build_info()) + } +} + +impl std::fmt::Display for BuildMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl std::fmt::Debug for BuildMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("BuildMetadata") + .field("frontend_version", &self.frontend_version()) + .field("backend_version", &self.backend_version()) + .field("version", &self.version()) + .field("language", &self.language()) + .field("target_cpu", &self.target_cpu()) + .field("env", &self.env()) + .field("build_info", &self.build_info()) + .finish() + } +} + +/// This structure represents a version for the backend or the frontend. +#[derive(Debug)] +pub struct Version { + /// Major Version + pub major: u16, + + /// Minor Version + pub minor: u16, + + /// Build Version + pub build: u16, + + /// Quick Fix Engineeringa version + pub qfe: u16, +} + +impl Version { + #[doc(hidden)] + pub fn from_ffi(ffi: cxx::UniquePtr>) -> Self { + let vec = ffi.as_ref().unwrap(); + Self { + major: *vec.get(0).unwrap(), + minor: *vec.get(1).unwrap(), + build: *vec.get(2).unwrap(), + qfe: *vec.get(3).unwrap(), + } + } +} + +/// This structure represents information wrapped by the `S_BUILDINFO` +/// symbol +#[derive(Debug)] +pub struct BuildInfo { + /// Working directory where the *build tool* was invoked + pub cwd: String, + + /// Path to the build tool (e.g. `C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.36.32532\bin\HostX64\x64\CL.exe`) + pub build_tool: String, + + /// Source file consumed by the *build tool* + pub source_file: String, + + /// PDB path + pub pdb: String, + + /// Command line arguments used to invoke the *build tool* + pub command_line: String, +} + +impl BuildInfo { + #[doc(hidden)] + pub fn from_ffi(ffi: cxx::UniquePtr>) -> Option { + let vec = ffi.as_ref().unwrap(); + if vec.is_empty() { + return None; + } + + assert_eq!(vec.len(), 5); + Some(Self { + cwd: vec.get(0).unwrap().to_string(), + build_tool: vec.get(1).unwrap().to_string(), + source_file: vec.get(2).unwrap().to_string(), + pdb: vec.get(3).unwrap().to_string(), + command_line: vec.get(4).unwrap().to_string(), + }) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/compilation_unit.rs b/vendor/lief/api/rust/crates/lief/src/pdb/compilation_unit.rs new file mode 100644 index 0000000..59fc185 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/compilation_unit.rs @@ -0,0 +1,115 @@ +//! This module wraps a PDB compilation unit + +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use crate::DeclOpt; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; + +use super::build_metadata::BuildMetadata; +use super::function::Functions; + +/// This structure represents a CompilationUnit (or Module) in a PDB file +pub struct CompilationUnit<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for CompilationUnit<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CompilationUnit<'_> { + /// Name (or path) to the COFF object (`.obj`) associated with this + /// compilation unit (e.g. `e:\obj.amd64fre\minkernel\ntos\hvl\mp\objfre\amd64\hvlp.obj`) + pub fn module_name(&self) -> String { + self.ptr.module_name().to_string() + } + + /// Name of path to the original binary object (COFF, Archive) in which + /// the compilation unit was located before being linked. + /// e.g. `e:\obj.amd64fre\minkernel\ntos\hvl\mp\objfre\amd64\hvl.lib` + pub fn object_filename(&self) -> String { + self.ptr.object_filename().to_string() + } + + /// Return an iterator over the [`crate::pdb::Function`] defined in this compilation unit. + /// If the PDB does not contain or has an empty DBI stream, it returns + /// an empty iterator. + pub fn functions(&self) -> Functions<'_> { + Functions::new(self.ptr.functions()) + } + + /// Iterator over the sources files (as string) that compose this compilation unit. + /// These files include the **header** (`.h, .hpp`, ...). + pub fn sources(&self) -> Sources<'_> { + Sources::new(self.ptr.sources()) + } + + /// Return build metadata such as the version of the compiler or + /// the original source language of this compilation unit + pub fn build_metadata(&self) -> Option> { + into_optional(self.ptr.build_metadata()) + } + + /// Generate a C/C++ definition for the functions defined in this + /// compilation unit. + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same as [`CompilationUnit::to_decl`] but with the given configuration + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +impl std::fmt::Display for CompilationUnit<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_fwd_iterator!( + CompilationUnits, + CompilationUnit<'a>, + ffi::PDB_CompilationUnit, + ffi::PDB_DebugInfo, + ffi::PDB_DebugInfo_it_compilation_units +); + +pub struct Sources<'a> { + #[doc(hidden)] + pub it: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PDB_CompilationUnit>, +} + +impl Sources<'_> { + #[doc(hidden)] + pub fn new(it: cxx::UniquePtr) -> Self { + Self { + it, + _owner: PhantomData, + } + } +} + +impl Iterator for Sources<'_> { + type Item = String; + fn next(&mut self) -> Option { + let string = self.it.as_mut().unwrap().next().to_string(); + // c.f. comment in rust/LIEF/PDB/CompilationUnit.hpp + if string == "[LIEF_STOP]" { + None + } else { + Some(string) + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/debug_info.rs b/vendor/lief/api/rust/crates/lief/src/pdb/debug_info.rs new file mode 100644 index 0000000..ad0daac --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/debug_info.rs @@ -0,0 +1,99 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::generic; +use std::marker::PhantomData; +use std::path::Path; + +use super::PublicSymbol; +use super::compilation_unit::CompilationUnits; +use super::public_symbol::PublicSymbols; +use super::types::{Type, Types}; + +/// Main interface over a PDB. +/// +/// One can instantiate this structure with [`crate::pdb::load`], +/// [`DebugInfo::from`] or using [`crate::generic::Binary::debug_info`]. +pub struct DebugInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for DebugInfo<'_> { + fn from_ffi(info: cxx::UniquePtr) -> Self { + Self { + ptr: info, + _owner: PhantomData, + } + } +} + +impl DebugInfo<'_> { + /// Create a DebugInfo from a PDB file path + pub fn from>(path: P) -> Option> { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + into_optional(ffi::PDB_DebugInfo::from_file(&__cxx_s)) + } + + /// The number of times the PDB file has been written. + pub fn age(&self) -> u32 { + self.ptr.age() + } + + /// Unique identifier of the PDB file + pub fn guid(&self) -> String { + self.ptr.guid().to_string() + } + + /// Iterator over the CompilationUnit from the PDB's DBI stream. + /// [`crate::pdb::CompilationUnit`] are also named "Module" in the PDB's official documentation + pub fn compilation_units(&self) -> CompilationUnits<'_> { + CompilationUnits::new(self.ptr.compilation_units()) + } + + /// Return an iterator over the public symbol stream ([`PublicSymbol`]) + pub fn public_symbols(&self) -> PublicSymbols<'_> { + PublicSymbols::new(self.ptr.public_symbols()) + } + + /// Try to find the [`PublicSymbol`] from the given name (based on the public symbol stream) + /// + /// + /// ``` + /// if let Some(symbol) = info.public_symbol_by_name("MiSyncSystemPdes") { + /// // FOUND! + /// } + /// ``` + pub fn public_symbol_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.public_symbol_by_name(&__cxx_s)) + } + + /// Return an iterator over the different [`crate::pdb::Type`] registered for this PDB file + pub fn types(&self) -> Types<'_> { + Types::new(self.ptr.types()) + } + + /// Try to find the type with the given name + pub fn type_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.find_type(&__cxx_s)) + } + + /// Try to find the type at the given index + pub fn type_by_index(&self, index: u32) -> Option> { + into_optional(self.ptr.find_type_by_index(index)) + } +} + +impl generic::DebugInfo for DebugInfo<'_> { + fn as_generic(&self) -> &ffi::AbstracDebugInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Display for DebugInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/function.rs b/vendor/lief/api/rust/crates/lief/src/pdb/function.rs new file mode 100644 index 0000000..391f2b8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/function.rs @@ -0,0 +1,73 @@ +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use crate::DebugLocation; +use crate::DeclOpt; +use crate::common::FromFFI; +use crate::declare_fwd_iterator; + +pub struct Function<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Function<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Function<'_> { + /// The name of the function (this name is usually demangled) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// The **Relative** Virtual Address of the function + pub fn rva(&self) -> u32 { + self.ptr.RVA() + } + + /// The size of the function + pub fn code_size(&self) -> u32 { + self.ptr.code_size() + } + + /// The name of the section in which this function is defined + pub fn section_name(&self) -> String { + self.ptr.section_name().to_string() + } + + /// Original source code location + pub fn debug_location(&self) -> DebugLocation { + DebugLocation::from_ffi(self.ptr.debug_location()) + } + + /// Generate a C/C++ definition for this function + pub fn to_decl(&self) -> String { + self.ptr.to_decl().to_string() + } + + /// Same as [`Function::to_decl`] but with the given configuration + pub fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.ptr.to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +impl std::fmt::Display for Function<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_fwd_iterator!( + Functions, + Function<'a>, + ffi::PDB_Function, + ffi::PDB_CompilationUnit, + ffi::PDB_CompilationUnit_it_functions +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/public_symbol.rs b/vendor/lief/api/rust/crates/lief/src/pdb/public_symbol.rs new file mode 100644 index 0000000..9a49c01 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/public_symbol.rs @@ -0,0 +1,63 @@ +//! This module wraps a PDB public symbol (stream number `n+5`) + +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::declare_fwd_iterator; + +/// This class provides general information (RVA, name) about a symbol +/// from the PDB's public symbol stream (or Public symbol hash stream) +pub struct PublicSymbol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for PublicSymbol<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl PublicSymbol<'_> { + /// Name of the symbol + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Demangled representation of the symbol + pub fn demangled_name(&self) -> String { + self.ptr.name().to_string() + } + + /// Name of the section in which this symbol is defined (e.g. `.text`). + pub fn section_name(&self) -> Option { + let name = self.ptr.section_name().to_string(); + if !name.is_empty() { Some(name) } else { None } + } + + /// **Relative** Virtual Address of this symbol. + /// + /// This function returns 0 if the RVA can't be computed. + pub fn rva(&self) -> u32 { + self.ptr.RVA() + } +} + +impl std::fmt::Display for PublicSymbol<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_fwd_iterator!( + PublicSymbols, + PublicSymbol<'a>, + ffi::PDB_PublicSymbol, + ffi::PDB_DebugInfo, + ffi::PDB_DebugInfo_it_public_symbols +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types.rs new file mode 100644 index 0000000..093653d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types.rs @@ -0,0 +1,254 @@ +use lief_ffi as ffi; + +use crate::{common::FromFFI, to_opt_trait, to_opt_trait_conv}; + +use crate::{DeclOpt, declare_fwd_iterator}; +use std::marker::PhantomData; + +pub mod array; +pub mod attribute; +pub mod bitfield; +pub mod classlike; +pub mod enum_ty; +pub mod function; +pub mod method; +pub mod modifier; +pub mod pointer; +pub mod simple; +pub mod union; + +#[doc(inline)] +pub use simple::Simple; + +#[doc(inline)] +pub use array::Array; + +#[doc(inline)] +pub use bitfield::BitField; + +#[doc(inline)] +pub use classlike::{Class, Interface, Structure}; + +#[doc(inline)] +pub use enum_ty::Enum; + +#[doc(inline)] +pub use function::Function; + +#[doc(inline)] +pub use modifier::Modifier; + +#[doc(inline)] +pub use pointer::Pointer; + +#[doc(inline)] +pub use union::Union; + +#[doc(inline)] +pub use attribute::Attribute; + +#[doc(inline)] +pub use method::Method; + +pub enum Type<'a> { + /// Represent primitive types (int, float, ...) + Simple(Simple<'a>), + + /// Mirror `LF_ARRAY` + Array(Array<'a>), + + /// Mirror `LF_BITFIELD + BitField(BitField<'a>), + + /// Mirror `LF_CLASS + Class(Class<'a>), + + /// Mirror `LF_STRUCTURE + Structure(Structure<'a>), + + /// Mirror `LF_INTERFACE + Interface(Interface<'a>), + + /// Mirror `LF_ENUM + Enum(Enum<'a>), + + /// Mirror `LF_PROCEDURE + Function(Function<'a>), + + /// Mirror `LF_MODIFIER + Modifier(Modifier<'a>), + + /// Mirror `LF_POINTER + Pointer(Pointer<'a>), + + /// Mirror `LF_UNION + Union(Union<'a>), + + Generic(Generic<'a>), +} + +impl FromFFI for Type<'_> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let type_ref = ffi_entry.as_ref().unwrap(); + + if ffi::PDB_types_Simple::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Simple(Simple::from_ffi(raw)) + } else if ffi::PDB_types_Array::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Array(Array::from_ffi(raw)) + } else if ffi::PDB_types_BitField::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::BitField(BitField::from_ffi(raw)) + } else if ffi::PDB_types_Class::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Class(Class::from_ffi(raw)) + } else if ffi::PDB_types_Structure::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Structure(Structure::from_ffi(raw)) + } else if ffi::PDB_types_Interface::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Interface(Interface::from_ffi(raw)) + } else if ffi::PDB_types_Enum::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Enum(Enum::from_ffi(raw)) + } else if ffi::PDB_types_Function::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Function(Function::from_ffi(raw)) + } else if ffi::PDB_types_Modifier::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Modifier(Modifier::from_ffi(raw)) + } else if ffi::PDB_types_Pointer::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Pointer(Pointer::from_ffi(raw)) + } else if ffi::PDB_types_Union::classof(type_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Type::Union(Union::from_ffi(raw)) + } else { + Type::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Generic<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +pub trait PdbType { + #[doc(hidden)] + fn get_base(&self) -> &ffi::PDB_Type; + + /// Size of the type. This size should match the value of `sizeof(...)` + /// applied to this type. + fn size(&self) -> Option { + to_opt_trait!(&lief_ffi::PDB_Type::size, self.get_base()); + } + + /// Type's name (if present) + fn name(&self) -> Option { + to_opt_trait_conv!( + &lief_ffi::PDB_Type::name, + self.get_base(), + |e: cxx::UniquePtr| e.to_string() + ); + } + + /// Generates a C/C++ definition for this type + fn to_decl(&self) -> String { + self.get_base().to_decl().to_string() + } + + /// Generates a C/C++ definition for this type with the given configuration + fn to_decl_with_opt(&self, opt: &DeclOpt) -> String { + self.get_base().to_decl_with_opt(&opt.to_ffi()).to_string() + } +} + +impl PdbType for Type<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + match &self { + Type::Simple(ty) => ty.get_base(), + Type::Array(ty) => ty.get_base(), + Type::BitField(ty) => ty.get_base(), + Type::Class(ty) => ty.get_base(), + Type::Structure(ty) => ty.get_base(), + Type::Interface(ty) => ty.get_base(), + Type::Enum(ty) => ty.get_base(), + Type::Function(ty) => ty.get_base(), + Type::Modifier(ty) => ty.get_base(), + Type::Pointer(ty) => ty.get_base(), + Type::Union(ty) => ty.get_base(), + Type::Generic(ty) => ty.get_base(), + } + } +} + +impl PdbType for Generic<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap() + } +} + +declare_fwd_iterator!( + Types, + Type<'a>, + ffi::PDB_Type, + ffi::PDB_DebugInfo, + ffi::PDB_DebugInfo_it_types +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/array.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/array.rs new file mode 100644 index 0000000..a10f5a9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/array.rs @@ -0,0 +1,46 @@ +use lief_ffi as ffi; + +use crate::pdb::types::PdbType; +use crate::{ + common::{FromFFI, into_optional}, + pdb::Type, +}; +use std::marker::PhantomData; + +/// This structure wraps a `LF_ARRAY` PDB type +pub struct Array<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Array<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Array<'_> { + /// The number of element in this array + pub fn numberof_elements(&self) -> u64 { + self.ptr.numberof_elements() + } + + /// Type of the elements + pub fn element_type(&self) -> Option> { + into_optional(self.ptr.element_type()) + } + + /// Type of the index + pub fn index_type(&self) -> Option> { + into_optional(self.ptr.index_type()) + } +} + +impl PdbType for Array<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/attribute.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/attribute.rs new file mode 100644 index 0000000..735a058 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/attribute.rs @@ -0,0 +1,49 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +use crate::common::into_optional; +use crate::declare_fwd_iterator; +use crate::pdb::Type; + +/// This class represents an attribute (`LF_MEMBER`) in an aggregate (class, +/// struct, union, ...) +pub struct Attribute<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Attribute<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Attribute<'_> { + /// Name of the attribute + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Offset of this attribute in the aggregate + pub fn field_offset(&self) -> u64 { + self.ptr.field_offset() + } + + /// Type of this attribute + pub fn get_type(&self) -> Option> { + into_optional(self.ptr.get_type()) + } +} + +declare_fwd_iterator!( + Attributes, + Attribute<'a>, + ffi::PDB_types_Attribute, + ffi::PDB_types_ClassLike, + ffi::PDB_types_ClassLike_it_attributes +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/bitfield.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/bitfield.rs new file mode 100644 index 0000000..d394685 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/bitfield.rs @@ -0,0 +1,28 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::PdbType; +use std::marker::PhantomData; + +/// This structure wraps a `LF_BITFIELD` PDB type +pub struct BitField<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for BitField<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl BitField<'_> {} + +impl PdbType for BitField<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/classlike.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/classlike.rs new file mode 100644 index 0000000..728f43e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/classlike.rs @@ -0,0 +1,111 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::PdbType; +use crate::pdb::types::attribute::Attributes; +use crate::pdb::types::method::Methods; +use std::marker::PhantomData; + +/// Trait shared by [`Structure`], [`Class`], [`Union`] and [`Interface`] +pub trait ClassLike { + #[doc(hidden)] + fn get_classlike(&self) -> &ffi::PDB_types_ClassLike; + + /// Mangled type name + fn unique_name(&self) -> String { + self.get_classlike().unique_name().to_string() + } + + /// Iterator over the different [`crate::pdb::types::Attribute`] defined in this + /// class-like type + fn attributes(&self) -> Attributes<'_> { + Attributes::new(self.get_classlike().attributes()) + } + + /// Iterator over the different [`crate::pdb::types::Method`] implemented in this + /// class-like type + fn methods(&self) -> Methods<'_> { + Methods::new(self.get_classlike().methods()) + } +} + +/// This structure wraps a `LF_CLASS` PDB type +pub struct Class<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Class<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ClassLike for Class<'_> { + fn get_classlike(&self) -> &ffi::PDB_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PdbType for Class<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +/// This structure wraps a `LF_STRUCTURE` PDB type +pub struct Structure<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Structure<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ClassLike for Structure<'_> { + fn get_classlike(&self) -> &ffi::PDB_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PdbType for Structure<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +/// This structure wraps a `LF_INTERFACE` PDB type +pub struct Interface<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Interface<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ClassLike for Interface<'_> { + fn get_classlike(&self) -> &ffi::PDB_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PdbType for Interface<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/enum_ty.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/enum_ty.rs new file mode 100644 index 0000000..f80c53c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/enum_ty.rs @@ -0,0 +1,81 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::pdb::types::{PdbType, Type}; +use std::marker::PhantomData; + +use crate::declare_fwd_iterator; + +/// This structure wraps a `LF_ENUM` PDB type +pub struct Enum<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Enum<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Enum<'_> { + /// Entries associated with this enum + pub fn entries(&self) -> Entries<'_> { + Entries::new(self.ptr.entries()) + } + + /// The underlying type that is used to encode this enum + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } + + /// Try to find the enum entry matching the given value + pub fn entry_by_value(&self, value: i64) -> Option> { + into_optional(self.ptr.find_entry(value)) + } +} + +impl PdbType for Enum<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// This struct represents an enum entry which is essentially composed of a name and its value +/// (integer). +pub struct Entry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl Entry<'_> { + /// Enum entry's name + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Enum entry's value + pub fn value(&self) -> i64 { + self.ptr.value() + } +} + +impl FromFFI for Entry<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +declare_fwd_iterator!( + Entries, + Entry<'a>, + ffi::PDB_types_Enum_Entry, + ffi::PDB_types_Enum, + ffi::PDB_types_Enum_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/function.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/function.rs new file mode 100644 index 0000000..b588ecf --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/function.rs @@ -0,0 +1,48 @@ +use lief_ffi as ffi; + +use super::Type; +use crate::common::{FromFFI, into_optional}; +use crate::declare_fwd_iterator; +use crate::pdb::types::PdbType; +use std::marker::PhantomData; + +/// This structure wraps a `LF_PROCEDURE` PDB type +pub struct Function<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Function<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Function<'_> { + /// [`Type`] returned by the function + pub fn return_type(&self) -> Option> { + into_optional(self.ptr.return_type()) + } + + /// [`Type`] of the function's parameters + pub fn parameters(&self) -> ParametersIt<'_> { + ParametersIt::new(self.ptr.parameters()) + } +} + +impl PdbType for Function<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_fwd_iterator!( + ParametersIt, + Type<'a>, + ffi::PDB_Type, + ffi::PDB_types_Function, + ffi::PDB_types_Function_it_parameters +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/method.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/method.rs new file mode 100644 index 0000000..ea787b7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/method.rs @@ -0,0 +1,135 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +use crate::declare_fwd_iterator; + +/// This class represents a Method (`LF_ONEMETHOD`) that can be defined in +/// ClassLike PDB type +pub struct Method<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Method<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum MethodAccess { + /// No access specifier (or unknown) + NONE, + /// Private access + PRIVATE, + /// Protected access + PROTECTED, + /// Public access + PUBLIC, + + UNKNOWN(u8), +} + +impl From for MethodAccess { + fn from(value: u8) -> Self { + match value { + 0 => MethodAccess::NONE, + 1 => MethodAccess::PRIVATE, + 2 => MethodAccess::PROTECTED, + 3 => MethodAccess::PUBLIC, + _ => MethodAccess::UNKNOWN(value), + } + } +} + +impl From for u8 { + fn from(value: MethodAccess) -> u8 { + match value { + MethodAccess::NONE => 0, + MethodAccess::PRIVATE => 1, + MethodAccess::PROTECTED => 2, + MethodAccess::PUBLIC => 3, + MethodAccess::UNKNOWN(v) => v, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum MethodType { + /// Regular instance method + VANILLA, + /// Virtual method + VIRTUAL, + /// Static method + STATIC, + /// Friend method + FRIEND, + /// Virtual method that introduces a new vtable slot + INTRODUCING_VIRTUAL, + /// Pure virtual method (abstract) + PURE_VIRTUAL, + /// Pure virtual method that introduces a new vtable slot + PURE_INTRODUCING_VIRTUAL, + + UNKNOWN(u32), +} + +impl From for MethodType { + fn from(value: u32) -> Self { + match value { + 0x00 => MethodType::VANILLA, + 0x01 => MethodType::VIRTUAL, + 0x02 => MethodType::STATIC, + 0x03 => MethodType::FRIEND, + 0x04 => MethodType::INTRODUCING_VIRTUAL, + 0x05 => MethodType::PURE_VIRTUAL, + 0x06 => MethodType::PURE_INTRODUCING_VIRTUAL, + _ => MethodType::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: MethodType) -> u32 { + match value { + MethodType::VANILLA => 0x00, + MethodType::VIRTUAL => 0x01, + MethodType::STATIC => 0x02, + MethodType::FRIEND => 0x03, + MethodType::INTRODUCING_VIRTUAL => 0x04, + MethodType::PURE_VIRTUAL => 0x05, + MethodType::PURE_INTRODUCING_VIRTUAL => 0x06, + MethodType::UNKNOWN(v) => v, + } + } +} + +impl Method<'_> { + /// Name of the method + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + pub fn get_type(&self) -> MethodType { + MethodType::from(self.ptr.get_type()) + } + + pub fn access(&self) -> MethodAccess { + MethodAccess::from(self.ptr.access()) + } +} + +declare_fwd_iterator!( + Methods, + Method<'a>, + ffi::PDB_types_Method, + ffi::PDB_types_ClassLike, + ffi::PDB_types_ClassLike_it_methods +); diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/modifier.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/modifier.rs new file mode 100644 index 0000000..fe6ffb0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/modifier.rs @@ -0,0 +1,35 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::{PdbType, Type}; +use std::marker::PhantomData; + +use crate::common::into_optional; + +/// This structure wraps a `LF_MODIFIER` PDB type +pub struct Modifier<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Modifier<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Modifier<'_> { + /// Underlying type targeted by this modifier + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} + +impl PdbType for Modifier<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/pointer.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/pointer.rs new file mode 100644 index 0000000..0d74f6d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/pointer.rs @@ -0,0 +1,35 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::{PdbType, Type}; +use std::marker::PhantomData; + +use crate::common::into_optional; + +/// This structure represents a `LF_POINTER` PDB type +pub struct Pointer<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Pointer<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Pointer<'_> { + /// Underlying type targeted by this modifier + pub fn underlying_type(&self) -> Option> { + into_optional(self.ptr.underlying_type()) + } +} + +impl PdbType for Pointer<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/simple.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/simple.rs new file mode 100644 index 0000000..7aef0dc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/simple.rs @@ -0,0 +1,320 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::PdbType; +use std::marker::PhantomData; + +/// This class represents a primitive types (int, float, ...) which are +/// also named *simple* types in the PDB format. +pub struct Simple<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Simple<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum SimpleType { + /// Void type (return type or void*) + VOID, + + // --- Characters --- + /// Signed Character + SCHAR, + /// Unsigned Character + UCHAR, + /// "Real" Character (char) + RCHAR, + + // --- Unicode / Wide Characters --- + /// Wide Character (wchar_t) + WCHAR, + /// 16-bit Character (char16_t) + CHAR16, + /// 32-bit Character (char32_t) + CHAR32, + /// 8-bit Character (char8_t) + CHAR8, + + // --- Bytes --- + /// Signed Byte + SBYTE, + /// Unsigned Byte + UBYTE, + + // --- Short (16-bit) --- + /// Signed Short + SSHORT, + /// Unsigned Short + USHORT, + + /// Explicit Signed 16-bit Integer + SINT16, + /// Explicit Unsigned 16-bit Integer + UINT16, + + // --- Long (32-bit) --- + /// Signed Long + SLONG, + /// Unsigned Long + ULONG, + + /// Explicit Signed 32-bit Integer + SINT32, + /// Explicit Unsigned 32-bit Integer + UINT32, + + // --- Quad (64-bit) --- + /// Signed Quadword + SQUAD, + /// Unsigned Quadword + UQUAD, + + /// Explicit Signed 64-bit Integer + SINT64, + /// Explicit Unsigned 64-bit Integer + UINT64, + + // --- Octa (128-bit) --- + /// Signed Octaword + SOCTA, + /// Unsigned Octaword + UOCTA, + + /// Explicit Signed 128-bit Integer + SINT128, + /// Explicit Unsigned 128-bit Integer + UINT128, + + // --- Floating Point --- + /// 16-bit Floating point + FLOAT16, + /// 32-bit Floating point (float) + FLOAT32, + FLOAT32_PARTIAL_PRECISION, + + /// 48-bit Floating point + FLOAT48, + /// 64-bit Floating point (double) + FLOAT64, + /// 80-bit Floating point + FLOAT80, + /// 128-bit Floating point + FLOAT128, + + // --- Complex Numbers --- + COMPLEX16, + COMPLEX32, + COMPLEX32_PARTIAL_PRECISION, + COMPLEX48, + COMPLEX64, + COMPLEX80, + COMPLEX128, + + // --- Booleans --- + /// 8-bit Boolean + BOOL8, + /// 16-bit Boolean + BOOL16, + /// 32-bit Boolean + BOOL32, + /// 64-bit Boolean + BOOL64, + /// 128-bit Boolean + BOOL128, + + UNKNOWN(u32), +} + +impl From for SimpleType { + fn from(value: u32) -> Self { + match value { + 0x0003 => SimpleType::VOID, + 0x0010 => SimpleType::SCHAR, + 0x0020 => SimpleType::UCHAR, + 0x0070 => SimpleType::RCHAR, + 0x0071 => SimpleType::WCHAR, + 0x007a => SimpleType::CHAR16, + 0x007b => SimpleType::CHAR32, + 0x007c => SimpleType::CHAR8, + 0x0068 => SimpleType::SBYTE, + 0x0069 => SimpleType::UBYTE, + 0x0011 => SimpleType::SSHORT, + 0x0021 => SimpleType::USHORT, + 0x0072 => SimpleType::SINT16, + 0x0073 => SimpleType::UINT16, + 0x0012 => SimpleType::SLONG, + 0x0022 => SimpleType::ULONG, + 0x0074 => SimpleType::SINT32, + 0x0075 => SimpleType::UINT32, + 0x0013 => SimpleType::SQUAD, + 0x0023 => SimpleType::UQUAD, + 0x0076 => SimpleType::SINT64, + 0x0077 => SimpleType::UINT64, + 0x0014 => SimpleType::SOCTA, + 0x0024 => SimpleType::UOCTA, + 0x0078 => SimpleType::SINT128, + 0x0079 => SimpleType::UINT128, + 0x0046 => SimpleType::FLOAT16, + 0x0040 => SimpleType::FLOAT32, + 0x0045 => SimpleType::FLOAT32_PARTIAL_PRECISION, + 0x0044 => SimpleType::FLOAT48, + 0x0041 => SimpleType::FLOAT64, + 0x0042 => SimpleType::FLOAT80, + 0x0043 => SimpleType::FLOAT128, + 0x0056 => SimpleType::COMPLEX16, + 0x0050 => SimpleType::COMPLEX32, + 0x0055 => SimpleType::COMPLEX32_PARTIAL_PRECISION, + 0x0054 => SimpleType::COMPLEX48, + 0x0051 => SimpleType::COMPLEX64, + 0x0052 => SimpleType::COMPLEX80, + 0x0053 => SimpleType::COMPLEX128, + 0x0030 => SimpleType::BOOL8, + 0x0031 => SimpleType::BOOL16, + 0x0032 => SimpleType::BOOL32, + 0x0033 => SimpleType::BOOL64, + 0x0034 => SimpleType::BOOL128, + _ => SimpleType::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: SimpleType) -> u32 { + match value { + SimpleType::VOID => 0x0003, + SimpleType::SCHAR => 0x0010, + SimpleType::UCHAR => 0x0020, + SimpleType::RCHAR => 0x0070, + SimpleType::WCHAR => 0x0071, + SimpleType::CHAR16 => 0x007a, + SimpleType::CHAR32 => 0x007b, + SimpleType::CHAR8 => 0x007c, + SimpleType::SBYTE => 0x0068, + SimpleType::UBYTE => 0x0069, + SimpleType::SSHORT => 0x0011, + SimpleType::USHORT => 0x0021, + SimpleType::SINT16 => 0x0072, + SimpleType::UINT16 => 0x0073, + SimpleType::SLONG => 0x0012, + SimpleType::ULONG => 0x0022, + SimpleType::SINT32 => 0x0074, + SimpleType::UINT32 => 0x0075, + SimpleType::SQUAD => 0x0013, + SimpleType::UQUAD => 0x0023, + SimpleType::SINT64 => 0x0076, + SimpleType::UINT64 => 0x0077, + SimpleType::SOCTA => 0x0014, + SimpleType::UOCTA => 0x0024, + SimpleType::SINT128 => 0x0078, + SimpleType::UINT128 => 0x0079, + SimpleType::FLOAT16 => 0x0046, + SimpleType::FLOAT32 => 0x0040, + SimpleType::FLOAT32_PARTIAL_PRECISION => 0x0045, + SimpleType::FLOAT48 => 0x0044, + SimpleType::FLOAT64 => 0x0041, + SimpleType::FLOAT80 => 0x0042, + SimpleType::FLOAT128 => 0x0043, + SimpleType::COMPLEX16 => 0x0056, + SimpleType::COMPLEX32 => 0x0050, + SimpleType::COMPLEX32_PARTIAL_PRECISION => 0x0055, + SimpleType::COMPLEX48 => 0x0054, + SimpleType::COMPLEX64 => 0x0051, + SimpleType::COMPLEX80 => 0x0052, + SimpleType::COMPLEX128 => 0x0053, + SimpleType::BOOL8 => 0x0030, + SimpleType::BOOL16 => 0x0031, + SimpleType::BOOL32 => 0x0032, + SimpleType::BOOL64 => 0x0033, + SimpleType::BOOL128 => 0x0034, + SimpleType::UNKNOWN(v) => v, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum SimpleMode { + /// Not a pointer (direct access) + DIRECT, + /// Far pointer + FAR_POINTER, + /// Huge pointer + HUGE_POINTER, + /// 32-bit Near pointer + NEAR_POINTER32, + /// 32-bit Far pointer + FAR_POINTER32, + /// 64-bit Near pointer + NEAR_POINTER64, + /// 128-bit Near pointer + NEAR_POINTER128, + + UNKNOWN(u32), +} + +impl From for SimpleMode { + fn from(value: u32) -> Self { + match value { + 0x00000000 => SimpleMode::DIRECT, + 0x00000200 => SimpleMode::FAR_POINTER, + 0x00000300 => SimpleMode::HUGE_POINTER, + 0x00000400 => SimpleMode::NEAR_POINTER32, + 0x00000500 => SimpleMode::FAR_POINTER32, + 0x00000600 => SimpleMode::NEAR_POINTER64, + 0x00000700 => SimpleMode::NEAR_POINTER128, + _ => SimpleMode::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: SimpleMode) -> u32 { + match value { + SimpleMode::DIRECT => 0x00000000, + SimpleMode::FAR_POINTER => 0x00000200, + SimpleMode::HUGE_POINTER => 0x00000300, + SimpleMode::NEAR_POINTER32 => 0x00000400, + SimpleMode::FAR_POINTER32 => 0x00000500, + SimpleMode::NEAR_POINTER64 => 0x00000600, + SimpleMode::NEAR_POINTER128 => 0x00000700, + SimpleMode::UNKNOWN(v) => v, + } + } +} + +impl Simple<'_> { + /// Check if this simple type is a pointer. + pub fn is_pointer(&self) -> bool { + self.ptr.is_pointer() + } + + /// Check if the underlying type is signed + pub fn is_signed(&self) -> bool { + self.ptr.is_signed() + } + + /// Returns the underlying primitive type. + pub fn get_type(&self) -> SimpleType { + SimpleType::from(self.ptr.get_type()) + } + + /// Returns the mode (pointer type) of this Simple type. + pub fn modes(&self) -> SimpleMode { + SimpleMode::from(self.ptr.modes()) + } +} + +impl PdbType for Simple<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pdb/types/union.rs b/vendor/lief/api/rust/crates/lief/src/pdb/types/union.rs new file mode 100644 index 0000000..1f0f5f9 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pdb/types/union.rs @@ -0,0 +1,35 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::pdb::types::PdbType; +use crate::pdb::types::classlike::ClassLike; +use std::marker::PhantomData; + +/// This structure wraps a `LF_UNION` PDB type +pub struct Union<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl FromFFI for Union<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl Union<'_> {} + +impl PdbType for Union<'_> { + fn get_base(&self) -> &ffi::PDB_Type { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl ClassLike for Union<'_> { + fn get_classlike(&self) -> &ffi::PDB_types_ClassLike { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe.rs b/vendor/lief/api/rust/crates/lief/src/pe.rs new file mode 100644 index 0000000..e9c3bc2 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe.rs @@ -0,0 +1,321 @@ +//! Module for the PE file format support in LIEF. +//! +//! The [`Binary`] structure exposes the main API to inspect a PE file. It can be instantiated, +//! using either: [`crate::pe::parse`], [`crate::pe::Binary::parse`] or [`crate::Binary::parse`] +//! +//! ``` +//! let pe = lief::pe::parse("demo.exe").unwrap(); +//! for section in pe.sections() { +//! println!("section: {}", section.name()); +//! } +//! ``` + +use lief_ffi as ffi; +use std::path::Path; + +pub mod binary; +pub mod builder; +pub mod chpe_metadata_arm64; +pub mod chpe_metadata_x86; +pub mod code_integrity; +pub mod data_directory; +pub mod debug; +pub mod delay_import; +pub mod dynamic_fixups; +pub mod dynamic_relocation; +pub mod enclave_configuration; +pub mod exception; +pub mod exception_aarch64; +pub mod exception_x64; +pub mod export; +pub mod factory; +pub mod headers; +pub mod import; +pub mod load_configuration; +pub mod parser_config; +pub mod relocation; +pub mod resources; +pub mod rich_header; +pub mod section; +pub mod signature; +pub mod tls; +pub mod volatile_metadata; + +#[doc(inline)] +pub use binary::Binary; +#[doc(inline)] +pub use data_directory::DataDirectory; +#[doc(inline)] +pub use delay_import::DelayImport; +#[doc(inline)] +pub use dynamic_fixups::DynamicFixup; +#[doc(inline)] +pub use dynamic_relocation::DynamicRelocation; +#[doc(inline)] +pub use enclave_configuration::{EnclaveConfiguration, EnclaveImport}; +#[doc(inline)] +pub use exception::{ExceptionInfo, RuntimeExceptionFunction}; +#[doc(inline)] +pub use export::Export; +#[doc(inline)] +pub use factory::Factory; +#[doc(inline)] +pub use headers::{DosHeader, Header, OptionalHeader}; +#[doc(inline)] +pub use import::Import; +#[doc(inline)] +pub use load_configuration::{CHPEMetadata, LoadConfiguration}; +#[doc(inline)] +pub use parser_config::Config as ParserConfig; +#[doc(inline)] +pub use relocation::Relocation; +#[doc(inline)] +pub use resources::Accelerator as ResourceAccelerator; +#[doc(inline)] +pub use resources::Icon as ResourceIcon; +#[doc(inline)] +pub use resources::Manager as ResourcesManager; +#[doc(inline)] +pub use resources::Node as ResourceNode; +#[doc(inline)] +pub use resources::StringEntry as ResourceStringEntry; +#[doc(inline)] +pub use resources::Version as ResourceVersion; +#[doc(inline)] +pub use rich_header::{RichEntry, RichHeader}; +#[doc(inline)] +pub use section::Section; +#[doc(inline)] +pub use signature::Signature; +#[doc(inline)] +pub use tls::TLS; +#[doc(inline)] +pub use volatile_metadata::VolatileMetadata; + +use crate::common::{AsFFI, into_optional}; + +/// PE type: 32-bit or 64-bit +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum PE_TYPE { + /// 32-bit PE + PE32, + /// 64-bit PE + PE32_PLUS, + UNKNOWN(u32), +} + +impl From for PE_TYPE { + fn from(value: u32) -> Self { + match value { + 0x10b => PE_TYPE::PE32, + 0x20b => PE_TYPE::PE32_PLUS, + _ => PE_TYPE::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: PE_TYPE) -> u32 { + match value { + PE_TYPE::PE32 => 0x10b, + PE_TYPE::PE32_PLUS => 0x20b, + PE_TYPE::UNKNOWN(v) => v, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Algorithms { + SHA_512, + SHA_384, + SHA_256, + SHA_1, + MD5, + MD4, + MD2, + RSA, + EC, + MD5_RSA, + SHA1_DSA, + SHA1_RSA, + SHA_256_RSA, + SHA_384_RSA, + SHA_512_RSA, + SHA1_ECDSA, + SHA_256_ECDSA, + SHA_384_ECDSA, + SHA_512_ECDSA, + UNKNOWN(u32), +} + +impl From for Algorithms { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Algorithms::SHA_512, + 0x00000002 => Algorithms::SHA_384, + 0x00000003 => Algorithms::SHA_256, + 0x00000004 => Algorithms::SHA_1, + 0x00000005 => Algorithms::MD5, + 0x00000006 => Algorithms::MD4, + 0x00000007 => Algorithms::MD2, + 0x00000008 => Algorithms::RSA, + 0x00000009 => Algorithms::EC, + 0x0000000a => Algorithms::MD5_RSA, + 0x0000000b => Algorithms::SHA1_DSA, + 0x0000000c => Algorithms::SHA1_RSA, + 0x0000000d => Algorithms::SHA_256_RSA, + 0x0000000e => Algorithms::SHA_384_RSA, + 0x0000000f => Algorithms::SHA_512_RSA, + 0x00000010 => Algorithms::SHA1_ECDSA, + 0x00000011 => Algorithms::SHA_256_ECDSA, + 0x00000012 => Algorithms::SHA_384_ECDSA, + 0x00000013 => Algorithms::SHA_512_ECDSA, + _ => Algorithms::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Algorithms) -> u32 { + match value { + Algorithms::SHA_512 => 0x00000001, + Algorithms::SHA_384 => 0x00000002, + Algorithms::SHA_256 => 0x00000003, + Algorithms::SHA_1 => 0x00000004, + Algorithms::MD5 => 0x00000005, + Algorithms::MD4 => 0x00000006, + Algorithms::MD2 => 0x00000007, + Algorithms::RSA => 0x00000008, + Algorithms::EC => 0x00000009, + Algorithms::MD5_RSA => 0x0000000a, + Algorithms::SHA1_DSA => 0x0000000b, + Algorithms::SHA1_RSA => 0x0000000c, + Algorithms::SHA_256_RSA => 0x0000000d, + Algorithms::SHA_384_RSA => 0x0000000e, + Algorithms::SHA_512_RSA => 0x0000000f, + Algorithms::SHA1_ECDSA => 0x00000010, + Algorithms::SHA_256_ECDSA => 0x00000011, + Algorithms::SHA_384_ECDSA => 0x00000012, + Algorithms::SHA_512_ECDSA => 0x00000013, + Algorithms::UNKNOWN(_) => 0, + } + } +} + +/// Parse a PE file from the given file path +pub fn parse>(path: P) -> Option { + Binary::parse(path) +} + +/// Parse a PE file from the given file path and configuration +pub fn parse_with_config>(path: P, config: &ParserConfig) -> Option { + Binary::parse_with_config(path, config) +} + +/// Check that the layout of the given binary is correct from the Windows loader +/// perspective +pub fn check_layout(binary: &Binary) -> Result<(), String> { + cxx::let_cxx_string!(error = ""); + unsafe { + if ffi::PE_Utils::check_layout(binary.as_ffi(), error.as_mut().get_unchecked_mut()) { + return Ok(()); + } + } + Err(error.to_string()) +} + +/// Parse the PE binary at the given memory address +pub fn parse_from_memory(addr: u64) -> Option { + into_optional(ffi::PE_Binary::parse_from_memory(addr)) +} + +/// Parse the PE binary at the given memory address +pub fn parse_from_memory_with_config(addr: u64, config: &ParserConfig) -> Option { + let ffi_config = config.to_ffi(); + into_optional(ffi::PE_Binary::parse_from_memory_with_config( + addr, + &ffi_config, + )) +} + +/// Parse the PE binary from a memory dump located at `path` that was mapped at +/// the virtual address `addr` +pub fn parse_from_dump>(path: P, addr: u64) -> Option { + Binary::parse_from_dump(path, addr) +} + +/// Same as [`parse_from_dump`] but with a provided configuration +pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &ParserConfig, +) -> Option { + Binary::parse_from_dump_with_config(path, addr, config) +} + +/// Determine the PE type (PE32 or PE32+) of the given file +pub fn get_type>(path: P) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap_or("").to_string()); + let val = ffi::PE_Utils::get_type(&__cxx_s); + if val == 0 { + return None; + } + Some(PE_TYPE::from(val)) +} + +/// Compute the import hash of the given binary +pub fn get_imphash(binary: &Binary, mode: ImphashMode) -> String { + ffi::PE_Utils::get_imphash(binary.as_ffi(), mode.into()).to_string() +} + +/// Convert an OID string to a human-readable string +pub fn oid_to_string(oid: &str) -> String { + cxx::let_cxx_string!(__cxx_s = oid.to_string()); + ffi::PE_Utils::oid_to_string(&__cxx_s).to_string() +} + +/// Try to resolve import ordinals using the well-known ordinal lookup table +pub fn resolve_ordinals<'a>( + imp: &'a Import<'a>, + strict: bool, + use_std: bool, +) -> Option> { + crate::common::into_optional(ffi::PE_Utils::resolve_ordinals( + imp.as_ffi(), + strict, + use_std, + )) +} + +/// Mode used for computing the import hash +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum ImphashMode { + /// Default LIEF implementation + DEFAULT, + /// Use pefile algorithm (same as VirusTotal) + PEFILE, + UNKNOWN(u32), +} + +impl From for ImphashMode { + fn from(value: u32) -> Self { + match value { + 0x00000000 => ImphashMode::DEFAULT, + 0x00000001 => ImphashMode::PEFILE, + _ => ImphashMode::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: ImphashMode) -> u32 { + match value { + ImphashMode::DEFAULT => 0x00000000, + ImphashMode::PEFILE => 0x00000001, + ImphashMode::UNKNOWN(v) => v, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/binary.rs b/vendor/lief/api/rust/crates/lief/src/pe/binary.rs new file mode 100644 index 0000000..a63e4f5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/binary.rs @@ -0,0 +1,704 @@ +use lief_ffi as ffi; + +use num_traits::{Num, cast}; +use std::mem::size_of; +use std::path::Path; +use std::pin::Pin; + +use super::builder::Config; +use super::data_directory::{DataDirectories, DataDirectory}; +use super::debug::CodeViewPDB; +use super::debug::{self, DebugEntry, Entries}; +use super::delay_import::{DelayImport, DelayImports}; +use super::exception::RuntimeExceptionFunction; +use super::export::Export; +use super::import::{Import, Imports}; +use super::load_configuration::LoadConfiguration; +use super::parser_config::Config as ParserConfig; +use super::relocation::Relocations; +use super::resources::Node as ResourceNode; +use super::resources::{Manager as ResourcesManager, NodeBase}; +use super::rich_header::RichHeader; +use super::section::{Section, Sections}; +use super::signature::Signatures; +use super::tls::TLS; +use super::{data_directory, signature}; +use crate::coff; +use crate::coff::Symbol; + +use crate::Error; +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; +use crate::to_conv_result; +use crate::to_slice; + +use super::Algorithms; +use super::{DosHeader, Header, OptionalHeader}; + +/// This is the main interface to read and write PE binary attributes. +/// +/// Note that this structure implements the [`generic::Binary`] trait from which other generic +/// functions are exposed +/// +/// ``` +/// fn use_trait(pe: &Binary) { +/// let generic_binary = pe as &dyn generic::Binary; +/// println!("{}", generic_binary.entrypoint()); +/// } +/// +/// ``` +pub struct Binary { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Binary { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Binary { + /// Parse from a filepath given as a string + pub fn parse>(path: P) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::PE_Binary::parse(&__cxx_s); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Parse from a string file path and with a provided configuration + pub fn parse_with_config>(path: P, config: &ParserConfig) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::PE_Binary::parse_with_config(&__cxx_s, &ffi_config); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Parse a PE binary from a memory dump located at `path` that was mapped + /// at the virtual address `addr` + pub fn parse_from_dump>(path: P, addr: u64) -> Option { + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::PE_Binary::parse_from_dump(&__cxx_s, addr); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// Same as [`Binary::parse_from_dump`] but with a provided configuration + pub fn parse_from_dump_with_config>( + path: P, + addr: u64, + config: &ParserConfig, + ) -> Option { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = path.as_ref().to_str().unwrap()); + let ffi = ffi::PE_Binary::parse_from_dump_with_config(&__cxx_s, addr, &ffi_config); + if ffi.is_null() { + return None; + } + Some(Binary::from_ffi(ffi)) + } + + /// DosHeader which starts the PE files + pub fn dos_header(&self) -> DosHeader<'_> { + DosHeader::from_ffi(self.ptr.dos_header()) + } + + /// Header that follows the [`Binary::header`]. It is named + /// *optional* from the COFF specification but it is mandatory in a PE file. + pub fn optional_header(&self) -> OptionalHeader<'_> { + OptionalHeader::from_ffi(self.ptr.optional_header()) + } + + /// Re-compute the value of [`OptionalHeader::checksum`] + pub fn compute_checksum(&self) -> u32 { + self.ptr.compute_checksum() + } + + /// Next header after the [`Binary::dos_header`] + pub fn header(&self) -> Header<'_> { + Header::from_ffi(self.ptr.header()) + } + + /// Return TLS information if present + pub fn tls(&self) -> Option> { + into_optional(self.ptr.tls()) + } + + /// Return rich header information if present. + pub fn rich_header(&self) -> Option> { + into_optional(self.ptr.rich_header()) + } + + /// Return export information + pub fn export(&self) -> Option> { + into_optional(self.ptr.get_export()) + } + + /// Return the root of the PE's resource tree + pub fn resources(&self) -> Option> { + into_optional(self.ptr.resources()) + } + + /// Return a manager interface to read and manipulate the resources tree with a user friendly + /// interface. + pub fn resources_manager(&self) -> Option> { + into_optional(self.ptr.resources_manager()) + } + + /// Return the imports as an **iterator** over the [`Import`] structure + pub fn imports(&self) -> Imports<'_> { + Imports::new(self.ptr.imports()) + } + + /// Return the data directories as an iterator over the [`DataDirectory`] structure + pub fn data_directories(&self) -> DataDirectories<'_> { + DataDirectories::new(self.ptr.data_directories()) + } + + /// Return the sections as an iterator over the [`Section`] structure + pub fn sections(&self) -> Sections<'_> { + Sections::new(self.ptr.sections()) + } + + /// Return the relocations as an iterator over the [`super::Relocation`] structure + pub fn relocations(&self) -> Relocations<'_> { + Relocations::new(self.ptr.relocations()) + } + + /// Return the delayed imports as an iterator over the [`DelayImport`] structure + pub fn delay_imports(&self) -> DelayImports<'_> { + DelayImports::new(self.ptr.delay_imports()) + } + + /// Return an iterator over the [`signature::Signature`] if the current PE is authenticode-signed. + pub fn signatures(&self) -> Signatures<'_> { + Signatures::new(self.ptr.signatures()) + } + + /// Return an iterator over the [`debug::Entries`] of the binary. + pub fn debug(&self) -> DebugEntries<'_> { + DebugEntries::new(self.ptr.debug()) + } + + /// Compute the authentihash for the current PE with the given algorithms. + pub fn authentihash(&self, algo: Algorithms) -> Vec { + Vec::from(self.ptr.authentihash(algo.into()).as_slice()) + } + + /// Return load configuration info if present. + pub fn load_configuration(&self) -> Option> { + into_optional(self.ptr.load_configuration()) + } + + /// Return the raw data between the [`Binary::dos_header`] and the regular [`Binary::header`] + pub fn dos_stub(&self) -> &[u8] { + to_slice!(self.ptr.dos_stub()); + } + + /// Return the original overlay data of the file + pub fn overlay(&self) -> &[u8] { + to_slice!(self.ptr.overlay()); + } + + /// Return the offset computed by LIEF to identify overlay data + pub fn overlay_offset(&self) -> u64 { + self.ptr.overlay_offset() + } + + /// Convert a **relative** virtual address into an offset + pub fn rva_to_offset(&self, rva: u64) -> u64 { + self.ptr.rva_to_offset(rva) + } + + /// Convert an **absolute** virtual address into an offset. + pub fn va_to_offset(&self, va: u64) -> u64 { + self.ptr.va_to_offset(va) + } + + /// Convert the given offset into a relative virtual address (RVA). + pub fn offset_to_rva(&self, offset: u64) -> u64 { + self.ptr.offset_to_rva(offset) + } + + /// Return the size of the current binary when loaded in memory. + pub fn virtual_size(&self) -> u64 { + self.ptr.virtual_size() + } + + /// Compute the size of all the headers. + pub fn sizeof_headers(&self) -> u64 { + self.ptr.sizeof_headers() + } + + /// Find a section by its offset + pub fn section_from_offset(&self, offset: u64) -> Option> { + into_optional(self.ptr.section_from_offset(offset)) + } + + /// Find a section by its **relative** virtual address + pub fn section_from_rva(&self, rva: u64) -> Option> { + into_optional(self.ptr.section_from_rva(rva)) + } + + /// Find a section by its name + pub fn section_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.section_by_name(&__cxx_s)) + } + + /// Add a section to the binary and return the section added. + pub fn add_section(&mut self, section: Section) -> Option> { + into_optional(self.ptr.as_mut().unwrap().add_section(section.as_ffi())) + } + + /// Find the data directory with the given type + pub fn data_directory_by_type( + &self, + dir_type: data_directory::Type, + ) -> Option> { + into_optional(self.ptr.data_directory_by_type(dir_type.into())) + } + + /// Verify the binary against the embedded signature(s) (if any) + /// + /// First, it checks that the embedded signatures are correct (c.f. [`signature::Signature::check`]) + /// and then, it checks that the authentihash matches [`crate::pe::signature::content_info::ContentInfo::digest`] + pub fn verify_signature( + &self, + checks: signature::VerificationChecks, + ) -> signature::VerificationFlags { + signature::VerificationFlags::from(self.ptr.verify_signature(checks.into())) + } + + /// Verify the binary with the [`signature::Signature`] object provided in the first parameter. + /// It can be used to verify a detached signature: + /// + /// ``` + /// if let Some(sig) = Signature::from_file(path_str.unwrap()) { + /// pe.verify_signature(&sig, signature::VerificationChecks::DEFAULT); + /// } + /// ``` + pub fn verify_with_signature( + &self, + sig: &signature::Signature, + checks: signature::VerificationChecks, + ) -> signature::VerificationFlags { + signature::VerificationFlags::from( + self.ptr.verify_with_signature(sig.into(), checks.into()), + ) + } + + /// Find an import by its DLL name (case insensitive) + pub fn import_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.import_by_name(&__cxx_s)) + } + + /// Find a delayed import by its name + pub fn delay_import_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.delay_import_by_name(&__cxx_s)) + } + + /// Return the sized content from the virtual address + pub fn content_from_virtual_address(&self, address: u64, size: u64) -> &[u8] { + to_slice!(self.ptr.get_content_from_virtual_address(address, size)); + } + + pub fn functions(&self) -> generic::Functions<'_> { + generic::Functions::new(self.ptr.functions()) + } + + /// Return the data directory associated with the export table + pub fn export_dir(&self) -> Option> { + into_optional(self.ptr.export_dir()) + } + + /// Return the data directory associated with the import table + pub fn import_dir(&self) -> Option> { + into_optional(self.ptr.import_dir()) + } + + /// Return the data directory associated with the resources tree + pub fn rsrc_dir(&self) -> Option> { + into_optional(self.ptr.rsrc_dir()) + } + + /// Return the data directory associated with the exceptions + pub fn exceptions_dir(&self) -> Option> { + into_optional(self.ptr.exceptions_dir()) + } + + /// Return the data directory associated with the certificate table + /// (authenticode) + pub fn cert_dir(&self) -> Option> { + into_optional(self.ptr.cert_dir()) + } + + /// Return the data directory associated with the relocation table + pub fn relocation_dir(&self) -> Option> { + into_optional(self.ptr.relocation_dir()) + } + + /// Return the data directory associated with the debug table + pub fn debug_dir(&self) -> Option> { + into_optional(self.ptr.debug_dir()) + } + + /// Return the data directory associated with TLS + pub fn tls_dir(&self) -> Option> { + into_optional(self.ptr.tls_dir()) + } + + /// Return the data directory associated with the load config + pub fn load_config_dir(&self) -> Option> { + into_optional(self.ptr.load_config_dir()) + } + + /// Return the data directory associated with the IAT + pub fn iat_dir(&self) -> Option> { + into_optional(self.ptr.iat_dir()) + } + + /// Return the data directory associated with delayed imports + pub fn export_delay_dirdir(&self) -> Option> { + into_optional(self.ptr.delay_dir()) + } + + /// Get the integer value at the given virtual address + pub fn get_int_from_virtual_address(&self, addr: u64) -> Result + where + T: Num + cast::FromPrimitive + cast::ToPrimitive, + { + // Can't be in the generic trait because of: + // > for a trait to be "object safe" it needs to allow building a vtable to allow the call + // > to be resolvable dynamically; for more information visit + // > https://doc.rust-lang.org/reference/items/traits.html#object-safety + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u8, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u8(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u16, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u16(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u32, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u32(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + if size_of::() == size_of::() { + to_conv_result!( + ffi::AbstractBinary::get_u64, + self.ptr.as_ref().unwrap().as_ref(), + |value| { + T::from_u64(value).unwrap_or_else(|| panic!("Can't cast value: {value}")) + }, + addr + ); + } + + Err(Error::NotSupported) + } + + /// Add an imported library (i.e. `DLL`) to the binary + pub fn add_import<'a>(&'a mut self, name: &str) -> Import<'a> { + cxx::let_cxx_string!(__cxx_s = name); + Import::from_ffi(self.ptr.pin_mut().add_import(&__cxx_s)) + } + + /// Add an imported library (i.e. `DLL`) to the binary. + /// + /// The second parameter `pos` defines where to insert the import. + pub fn add_import_at_pos<'a>(&'a mut self, name: &str, pos: u32) -> Import<'a> { + cxx::let_cxx_string!(__cxx_s = name); + Import::from_ffi(self.ptr.pin_mut().add_import_pos(&__cxx_s, pos)) + } + + /// Remove the imported library with the given `name` + pub fn remove_import(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().remove_import(&__cxx_s); + } + + /// Remove all libraries in the binary + pub fn remove_all_imports(&mut self) { + self.ptr.pin_mut().remove_all_imports(); + } + + /// Remove the TLS from the binary + pub fn remove_tls(&mut self) { + self.ptr.pin_mut().remove_tls(); + } + + /// Set or change the TLS information + pub fn set_tls(&mut self, tls: &TLS) { + self.ptr.pin_mut().set_tls(tls.as_ffi()); + } + + /// Change or set the resources tree to given node + pub fn set_resources(&mut self, node: &dyn NodeBase) { + self.ptr.pin_mut().set_resources(node.get_base()); + } + + /// Add a new debug entry + pub fn add_debug_info<'a>(&'a mut self, entry: &dyn DebugEntry) -> Option> { + into_optional(self.ptr.pin_mut().add_debug_info(entry.get_base())) + } + + /// Remove a specific debug entry + pub fn remove_debug(&mut self, entry: &dyn DebugEntry) -> bool { + self.ptr.pin_mut().remove_debug(entry.get_base()) + } + + /// Remove all debug info + pub fn clear_debug(&mut self) -> bool { + self.ptr.pin_mut().clear_debug() + } + + /// Return the [`CodeViewPDB`] object if present + pub fn codeview_pdb(&self) -> Option> { + into_optional(self.ptr.codeview_pdb()) + } + + /// Write back the current PE binary into the file specified in parameter + pub fn write>(&mut self, output: P) { + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr.as_mut().unwrap().write(&__cxx_s); + } + + /// Write back the current PE binary into the file specified in parameter with the + /// configuration provided in the second parameter. + pub fn write_with_config>(&mut self, output: P, config: Config) { + let ffi_config = config.to_ffi(); + cxx::let_cxx_string!(__cxx_s = output.as_ref().to_str().unwrap()); + self.ptr + .as_mut() + .unwrap() + .write_with_config(&__cxx_s, ffi_config.as_ref().unwrap()); + } + + /// Rebuild the current PE binary and return the raw bytes. + /// + /// This is similar to [`Binary::write`] but instead of writing the result + /// into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes(&mut self) -> Vec { + Vec::from(self.ptr.as_mut().unwrap().write_to_bytes().as_slice()) + } + + /// Rebuild the current PE binary with the configuration provided in the + /// parameter and return the raw bytes. + /// + /// This is similar to [`Binary::write_with_config`] but instead of writing + /// the result into a file, it returns the reconstructed binary as a buffer. + pub fn write_to_bytes_with_config(&mut self, config: Config) -> Vec { + let ffi_config = config.to_ffi(); + Vec::from( + self.ptr + .as_mut() + .unwrap() + .write_to_bytes_with_config(ffi_config.as_ref().unwrap()) + .as_slice(), + ) + } + + /// Iterator over the strings located in the COFF string table + pub fn coff_string_table(&self) -> COFFStrings<'_> { + COFFStrings::new(self.ptr.coff_string_table()) + } + + /// Return an iterator over the binary (COFF) symbols (if any). + pub fn symbols(&self) -> Symbols<'_> { + Symbols::new(self.ptr.symbols()) + } + + /// Try to find the COFF string at the given offset in the COFF string table. + /// + ///
+ /// This offset must include the first 4 bytes holding the size of the table. + /// Hence, the first string starts a the offset 4. + ///
+ pub fn find_coff_string_at(&self, offset: u32) -> Option> { + into_optional(self.ptr.find_coff_string_at(offset)) + } + + /// Iterator over the exception (`_RUNTIME_FUNCTION`) functions + /// + /// This function requires that the option [`ParserConfig::parse_exceptions`] was turned on + /// (default is `false`) when parsing the binary. + pub fn exceptions(&self) -> Exceptions<'_> { + Exceptions::new(self.ptr.exceptions()) + } + + /// Try to find the exception info at the given RVA + /// + /// This function requires that the option [`ParserConfig::parse_exceptions`] was turned on + /// (default is `false`) when parsing the binary. + pub fn find_exception_at(&self, rva: u32) -> Option> { + into_optional(self.ptr.find_exception_at(rva)) + } + + /// True if this binary is compiled in ARM64EC mode (emulation compatible) + pub fn is_arm64ec(&self) -> bool { + self.ptr.is_arm64ec() + } + + /// True if this binary is compiled in ARM64X mode (contains both ARM64 and ARM64EC). + pub fn is_arm64x(&self) -> bool { + self.ptr.is_arm64x() + } + + /// If the current binary contains dynamic relocations + /// (e.g. LIEF::PE::DynamicFixupARM64X), this function returns the + /// **relocated** view of the current PE. + /// + /// This can be used to get the alternative PE binary, targeting a different + /// architectures. + /// + ///
+ /// This function is moving and taking the ownership of the nested + /// PE binary. This means that subsequent calls to this function will return None. + ///
+ /// + /// This function requires that the option [`ParserConfig::parse_arm64x_binary`] was turned on + /// (default is `false`) when parsing the binary. + pub fn nested_pe_binary(&self) -> Option { + into_optional(self.ptr.nested_pe_binary()) + } + + /// Set or change the export table + pub fn set_export(&mut self, export: &Export) { + self.ptr.pin_mut().set_export(export.as_ffi()); + } + + /// Whether the current binary is a reproducible build + pub fn is_reproducible_build(&self) -> bool { + self.ptr.is_reproducible_build() + } + + /// Check if the binary imports the given library name + pub fn has_import(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_import(&__cxx_s) + } + + /// Check if the binary has a delay import with the given name + pub fn has_delay_import(&self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.has_delay_import(&__cxx_s) + } + + /// Return the exception functions (from the exception directory) + pub fn exception_functions(&self) -> generic::Functions<'_> { + generic::Functions::new(self.ptr.exception_functions()) + } + + /// Remove the section with the given name + pub fn remove_section(&mut self, name: &str, clear: bool) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().remove_section(&__cxx_s, clear); + } + + /// Fill the content at the given virtual address with the specified value + pub fn fill_address(&mut self, address: u64, size: u64, value: u8) { + self.ptr.pin_mut().fill_address(address, size, value); + } + + /// Remove all relocations + pub fn remove_all_relocations(&mut self) { + self.ptr.pin_mut().remove_all_relocations(); + } +} + +impl AsFFI for Binary { + fn as_ffi(&self) -> &ffi::PE_Binary { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::PE_Binary> { + self.ptr.pin_mut() + } +} + +impl std::fmt::Debug for Binary { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Binary").finish() + } +} + +impl generic::Binary for Binary { + fn as_generic(&self) -> &ffi::AbstractBinary { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractBinary> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractBinary + as *mut ffi::AbstractBinary) + .as_mut() + .unwrap() + }) + } + } +} + +declare_iterator!( + DebugEntries, + debug::Entries<'a>, + ffi::PE_Debug, + ffi::PE_Binary, + ffi::PE_Binary_it_debug +); + +declare_iterator!( + COFFStrings, + coff::String<'a>, + ffi::PE_COFFString, + ffi::PE_Binary, + ffi::PE_Binary_it_strings_table +); + +declare_iterator!( + Symbols, + Symbol<'a>, + ffi::PE_Symbol, + ffi::PE_Binary, + ffi::PE_Binary_it_symbols +); + +declare_iterator!( + Exceptions, + RuntimeExceptionFunction<'a>, + ffi::PE_ExceptionInfo, + ffi::PE_Binary, + ffi::PE_Binary_it_exceptions +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/builder.rs b/vendor/lief/api/rust/crates/lief/src/pe/builder.rs new file mode 100644 index 0000000..4b76021 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/builder.rs @@ -0,0 +1,114 @@ +use lief_ffi as ffi; + +/// Structure used to configure the [`crate::pe::Binary::write_with_config`] operation +/// +/// The default value of these attributes is set to `false` if the +/// operation modifies the binary layout even though nothing changed. +/// For instance, building the import table **always** requires relocating the +/// table to another place. Thus, the default value is false and must +/// be explicitly set to true. +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct Config { + /// Whether the builder should reconstruct the imports table. This option should be turned on + /// if you modify imports. + /// + /// Please check LIEF website for more details + pub imports: bool, + + /// Whether the builder should reconstruct the export table This option should be turned on if + /// you modify exports. + /// + /// Please check LIEF website for more details + pub exports: bool, + + /// Whether the builder should regenerate the resources tree + pub resources: bool, + + /// Whether the builder should regenerate relocations + pub relocations: bool, + + /// Whether the builder should regenerate the load config + pub load_configuration: bool, + + /// Whether the builder should regenerate the TLS info + pub tls: bool, + + /// Whether the builder should write back any overlay data + pub overlay: bool, + + /// Whether the builder should regenerate debug entries + pub debug: bool, + + /// Whether the builder should write back dos stub (including the rich + /// header) + pub dos_stub: bool, + + /// If the resources tree needs to be relocated, this defines the name of + /// the new section that contains the relocated tree. + pub rsrc_section: String, + + /// Section that holds the relocated import table (IAT/ILT) + pub idata_section: String, + + /// Section that holds the relocated TLS info + pub tls_section: String, + + /// Section that holds the relocated relocations + pub reloc_section: String, + + /// Section that holds the export table + pub export_section: String, + + /// Section that holds the debug entries + pub debug_section: String, +} + +impl Default for Config { + fn default() -> Config { + Config { + imports: false, + exports: false, + resources: true, + relocations: true, + load_configuration: true, + tls: true, + overlay: true, + debug: true, + dos_stub: true, + rsrc_section: ".rsrc".to_string(), + idata_section: ".idata".to_string(), + tls_section: ".tls".to_string(), + reloc_section: ".reloc".to_string(), + export_section: ".edata".to_string(), + debug_section: ".debug".to_string(), + } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> cxx::UniquePtr { + let mut ptr = ffi::PE_Binary_write_config_t::create(); + ptr.pin_mut().set_import(self.imports); + ptr.pin_mut().set_exports(self.exports); + ptr.pin_mut().set_resources(self.resources); + ptr.pin_mut().set_relocations(self.relocations); + ptr.pin_mut().set_load_config(self.load_configuration); + ptr.pin_mut().set_tls(self.tls); + ptr.pin_mut().set_overlay(self.overlay); + ptr.pin_mut().set_dos_stub(self.dos_stub); + cxx::let_cxx_string!(rsrc = self.rsrc_section.as_str()); + ptr.pin_mut().set_rsrc_section(&rsrc); + cxx::let_cxx_string!(idata = self.idata_section.as_str()); + ptr.pin_mut().set_idata_section(&idata); + cxx::let_cxx_string!(tls = self.tls_section.as_str()); + ptr.pin_mut().set_tls_section(&tls); + cxx::let_cxx_string!(reloc = self.reloc_section.as_str()); + ptr.pin_mut().set_reloc_section(&reloc); + cxx::let_cxx_string!(export = self.export_section.as_str()); + ptr.pin_mut().set_export_section(&export); + cxx::let_cxx_string!(debug = self.debug_section.as_str()); + ptr.pin_mut().set_debug_section(&debug); + ptr + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_arm64.rs b/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_arm64.rs new file mode 100644 index 0000000..d855514 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_arm64.rs @@ -0,0 +1,357 @@ +use super::load_configuration::AsCHPEMetadata; +use crate::common::FromFFI; +use crate::declare_iterator; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// This class represents ARM64-specific metadata used in CHPE +/// (Compatible Hybrid PE) binaries, particularly for hybrid architectures like +/// ARM64EC and ARM64X. +/// +/// It provides access to metadata describing code ranges, redirections, entry points, and other +/// hybrid-specific information relevant for binary analysis +pub struct CHPEMetadata<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for CHPEMetadata<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CHPEMetadata<'_> { + /// RVA to the array that describes architecture-specific ranges + pub fn code_map(&self) -> u32 { + self.ptr.code_map() + } + + /// Number of entries in the code map + pub fn code_map_count(&self) -> u32 { + self.ptr.code_map_count() + } + + pub fn redirection_metadata(&self) -> u32 { + self.ptr.redirection_metadata() + } + + pub fn os_arm64x_dispatch_call_no_redirect(&self) -> u32 { + self.ptr.os_arm64x_dispatch_call_no_redirect() + } + + pub fn os_arm64x_dispatch_ret(&self) -> u32 { + self.ptr.os_arm64x_dispatch_ret() + } + + pub fn os_arm64x_dispatch_call(&self) -> u32 { + self.ptr.os_arm64x_dispatch_call() + } + + pub fn os_arm64x_dispatch_icall(&self) -> u32 { + self.ptr.os_arm64x_dispatch_icall() + } + + pub fn os_arm64x_dispatch_icall_cfg(&self) -> u32 { + self.ptr.os_arm64x_dispatch_icall_cfg() + } + + pub fn alternate_entry_point(&self) -> u32 { + self.ptr.alternate_entry_point() + } + + pub fn auxiliary_iat(&self) -> u32 { + self.ptr.auxiliary_iat() + } + + pub fn code_ranges_to_entry_points_count(&self) -> u32 { + self.ptr.code_ranges_to_entry_points_count() + } + + pub fn redirection_metadata_count(&self) -> u32 { + self.ptr.redirection_metadata_count() + } + + pub fn get_x64_information_function_pointer(&self) -> u32 { + self.ptr.get_x64_information_function_pointer() + } + + pub fn set_x64_information_function_pointer(&self) -> u32 { + self.ptr.set_x64_information_function_pointer() + } + + /// RVA to this architecture-specific exception table + pub fn extra_rfe_table(&self) -> u32 { + self.ptr.extra_rfe_table() + } + + /// Architecture-specific exception table size + pub fn extra_rfe_table_size(&self) -> u32 { + self.ptr.extra_rfe_table_size() + } + + pub fn auxiliary_iat_copy(&self) -> u32 { + self.ptr.auxiliary_iat_copy() + } + + pub fn auxiliary_delay_import(&self) -> u32 { + self.ptr.auxiliary_delay_import() + } + + pub fn auxiliary_delay_import_copy(&self) -> u32 { + self.ptr.auxiliary_delay_import_copy() + } + + pub fn bitfield_info(&self) -> u32 { + self.ptr.bitfield_info() + } + + pub fn code_ranges(&self) -> CodeRanges<'_> { + CodeRanges::new(self.ptr.code_ranges()) + } + + pub fn redirections(&self) -> Redirections<'_> { + Redirections::new(self.ptr.redirections()) + } + + pub fn code_range_entry_point(&self) -> CodeRangeEntrypoints<'_> { + CodeRangeEntrypoints::new(self.ptr.code_range_entry_point()) + } +} + +impl AsCHPEMetadata for CHPEMetadata<'_> { + fn as_generic(&self) -> &ffi::PE_CHPEMetadata { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for CHPEMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("CHPEMetadataARM64") + .field("code_map", &self.code_map()) + .field("code_map_count", &self.code_map_count()) + .field("redirection_metadata", &self.redirection_metadata()) + .field( + "os_arm64x_dispatch_call_no_redirect", + &self.os_arm64x_dispatch_call_no_redirect(), + ) + .field("os_arm64x_dispatch_ret", &self.os_arm64x_dispatch_ret()) + .field("os_arm64x_dispatch_call", &self.os_arm64x_dispatch_call()) + .field("os_arm64x_dispatch_icall", &self.os_arm64x_dispatch_icall()) + .field( + "os_arm64x_dispatch_icall_cfg", + &self.os_arm64x_dispatch_icall_cfg(), + ) + .field("alternate_entry_point", &self.alternate_entry_point()) + .field("auxiliary_iat", &self.auxiliary_iat()) + .field( + "code_ranges_to_entry_points_count", + &self.code_ranges_to_entry_points_count(), + ) + .field( + "redirection_metadata_count", + &self.redirection_metadata_count(), + ) + .field( + "get_x64_information_function_pointer", + &self.get_x64_information_function_pointer(), + ) + .field( + "set_x64_information_function_pointer", + &self.set_x64_information_function_pointer(), + ) + .field("extra_rfe_table", &self.extra_rfe_table()) + .field("extra_rfe_table_size", &self.extra_rfe_table_size()) + .field("auxiliary_iat_copy", &self.auxiliary_iat_copy()) + .field("auxiliary_delay_import", &self.auxiliary_delay_import()) + .field( + "auxiliary_delay_import_copy", + &self.auxiliary_delay_import_copy(), + ) + .field("bitfield_info", &self.bitfield_info()) + .finish() + } +} + +/// Structure that describes architecture-specific ranges +pub struct RangeEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for RangeEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum RangeType { + /// Pure ARM64 code + ARM64, + + /// ARM64EC hybrid code (compatible with x64) + ARM64EC, + + /// x64 code + AMD64, + UNKNOWN(u32), +} + +impl From for RangeType { + fn from(value: u32) -> Self { + match value { + 0x000000000 => RangeType::ARM64, + 0x000000001 => RangeType::ARM64EC, + 0x000000002 => RangeType::AMD64, + _ => RangeType::UNKNOWN(value), + } + } +} + +impl RangeEntry<'_> { + /// Raw data (include start RVA and type) + pub fn start_offset(&self) -> u32 { + self.ptr.start_offset() + } + + /// Range's length + pub fn length(&self) -> u32 { + self.ptr.length() + } + + /// Start of the range (RVA) + pub fn start(&self) -> u32 { + self.ptr.start() + } + + /// End of the range (RVA) + pub fn end(&self) -> u32 { + self.ptr.end() + } + + /// Architecture for this range + pub fn range_type(&self) -> RangeType { + RangeType::from(self.ptr.get_type()) + } +} + +impl std::fmt::Debug for RangeEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RangeEntry") + .field("start_offset", &self.start_offset()) + .field("length", &self.length()) + .field("start", &self.start()) + .field("end", &self.end()) + .field("range_type", &self.range_type()) + .finish() + } +} + +/// Structure that describes a redirection +pub struct RedirectionEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for RedirectionEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl RedirectionEntry<'_> { + pub fn src(&self) -> u32 { + self.ptr.src() + } + + pub fn dst(&self) -> u32 { + self.ptr.dst() + } +} + +impl std::fmt::Debug for RedirectionEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RedirectionEntry") + .field("src", &self.src()) + .field("dst", &self.dst()) + .finish() + } +} + +/// Mirror of `IMAGE_ARM64EC_CODE_RANGE_ENTRY_POINT`: +/// Represents a mapping between code range and its entry point. +pub struct CodeRangeEntrypoint<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for CodeRangeEntrypoint<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CodeRangeEntrypoint<'_> { + /// Start of the code range. + pub fn start_rva(&self) -> u32 { + self.ptr.start_rva() + } + + /// End of the code range (RVA). + pub fn end_rva(&self) -> u32 { + self.ptr.end_rva() + } + + /// RVA of the entry point for this range. + pub fn entrypoint(&self) -> u32 { + self.ptr.entrypoint() + } +} + +impl std::fmt::Debug for CodeRangeEntrypoint<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("CodeRangeEntrypoint") + .field("start_rva", &self.start_rva()) + .field("end_rva", &self.end_rva()) + .field("entrypoint", &self.entrypoint()) + .finish() + } +} + +declare_iterator!( + CodeRanges, + RangeEntry<'a>, + ffi::PE_CHPEMetadataARM64_range_entry_t, + ffi::PE_CHPEMetadataARM64, + ffi::PE_CHPEMetadataARM64_it_const_range_entries +); + +declare_iterator!( + Redirections, + RedirectionEntry<'a>, + ffi::PE_CHPEMetadataARM64_redirection_entry_t, + ffi::PE_CHPEMetadataARM64, + ffi::PE_CHPEMetadataARM64_it_const_redirection_entries +); + +declare_iterator!( + CodeRangeEntrypoints, + CodeRangeEntrypoint<'a>, + ffi::PE_CHPEMetadataARM64_code_range_entry_point_t, + ffi::PE_CHPEMetadataARM64, + ffi::PE_CHPEMetadataARM64_it_const_code_range_entry_point +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_x86.rs b/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_x86.rs new file mode 100644 index 0000000..abf307d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/chpe_metadata_x86.rs @@ -0,0 +1,125 @@ +use super::load_configuration::AsCHPEMetadata; +use crate::common::FromFFI; +use crate::to_opt; + +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// This structure represents hybrid metadata for x86. +pub struct CHPEMetadata<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for CHPEMetadata<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl CHPEMetadata<'_> { + pub fn chpe_code_address_range_offset(&self) -> u32 { + self.ptr.chpe_code_address_range_offset() + } + + pub fn chpe_code_address_range_count(&self) -> u32 { + self.ptr.chpe_code_address_range_count() + } + + pub fn wowa64_exception_handler_function_pointer(&self) -> u32 { + self.ptr.wowa64_exception_handler_function_pointer() + } + + pub fn wowa64_dispatch_call_function_pointer(&self) -> u32 { + self.ptr.wowa64_dispatch_call_function_pointer() + } + + pub fn wowa64_dispatch_indirect_call_function_pointer(&self) -> u32 { + self.ptr.wowa64_dispatch_indirect_call_function_pointer() + } + + pub fn wowa64_dispatch_indirect_call_cfg_function_pointer(&self) -> u32 { + self.ptr + .wowa64_dispatch_indirect_call_cfg_function_pointer() + } + + pub fn wowa64_dispatch_ret_function_pointer(&self) -> u32 { + self.ptr.wowa64_dispatch_ret_function_pointer() + } + + pub fn wowa64_dispatch_ret_leaf_function_pointer(&self) -> u32 { + self.ptr.wowa64_dispatch_ret_leaf_function_pointer() + } + + pub fn wowa64_dispatch_jump_function_pointer(&self) -> u32 { + self.ptr.wowa64_dispatch_jump_function_pointer() + } + + pub fn compiler_iat_pointer(&self) -> Option { + to_opt!(&lief_ffi::PE_CHPEMetadataX86::compiler_iat_pointer, &self); + } + + pub fn wowa64_rdtsc_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_CHPEMetadataX86::wowa64_rdtsc_function_pointer, + &self + ); + } +} + +impl AsCHPEMetadata for CHPEMetadata<'_> { + fn as_generic(&self) -> &ffi::PE_CHPEMetadata { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for CHPEMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("CHPEMetadataX86") + .field( + "chpe_code_address_range_offset", + &self.chpe_code_address_range_offset(), + ) + .field( + "chpe_code_address_range_count", + &self.chpe_code_address_range_count(), + ) + .field( + "wowa64_exception_handler_function_pointer", + &self.wowa64_exception_handler_function_pointer(), + ) + .field( + "wowa64_dispatch_call_function_pointer", + &self.wowa64_dispatch_call_function_pointer(), + ) + .field( + "wowa64_dispatch_indirect_call_function_pointer", + &self.wowa64_dispatch_indirect_call_function_pointer(), + ) + .field( + "wowa64_dispatch_indirect_call_cfg_function_pointer", + &self.wowa64_dispatch_indirect_call_cfg_function_pointer(), + ) + .field( + "wowa64_dispatch_ret_function_pointer", + &self.wowa64_dispatch_ret_function_pointer(), + ) + .field( + "wowa64_dispatch_ret_leaf_function_pointer", + &self.wowa64_dispatch_ret_leaf_function_pointer(), + ) + .field( + "wowa64_dispatch_jump_function_pointer", + &self.wowa64_dispatch_jump_function_pointer(), + ) + .field("compiler_iat_pointer", &self.compiler_iat_pointer()) + .field( + "wowa64_rdtsc_function_pointer", + &self.wowa64_rdtsc_function_pointer(), + ) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/code_integrity.rs b/vendor/lief/api/rust/crates/lief/src/pe/code_integrity.rs new file mode 100644 index 0000000..a609024 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/code_integrity.rs @@ -0,0 +1,49 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +pub struct CodeIntegrity<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl std::fmt::Debug for CodeIntegrity<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("CodeIntegrity") + .field("flags", &self.flags()) + .field("catalog", &self.catalog()) + .field("catalog_offset", &self.catalog_offset()) + .field("reserved", &self.reserved()) + .finish() + } +} + +impl CodeIntegrity<'_> { + /// Flags to indicate if CI information is available, etc. + pub fn flags(&self) -> u16 { + self.ptr.flags() + } + + /// 0xFFFF means not available + pub fn catalog(&self) -> u16 { + self.ptr.catalog() + } + pub fn catalog_offset(&self) -> u32 { + self.ptr.catalog_offset() + } + + /// Additional bitmask to be defined later + pub fn reserved(&self) -> u32 { + self.ptr.reserved() + } +} + +impl<'a> FromFFI for CodeIntegrity<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + CodeIntegrity { + ptr, + _owner: PhantomData, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/data_directory.rs b/vendor/lief/api/rust/crates/lief/src/pe/data_directory.rs new file mode 100644 index 0000000..b77461e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/data_directory.rs @@ -0,0 +1,140 @@ +//! PE Data Directory module + +use std::marker::PhantomData; + +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::declare_iterator; +use crate::pe::Section; +use crate::to_slice; + +use lief_ffi as ffi; + +pub struct DataDirectory<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone)] +pub enum Type { + EXPORT_TABLE, + IMPORT_TABLE, + RESOURCE_TABLE, + EXCEPTION_TABLE, + CERTIFICATE_TABLE, + BASE_RELOCATION_TABLE, + DEBUG_DIR, + ARCHITECTURE, + GLOBAL_PTR, + TLS_TABLE, + LOAD_CONFIG_TABLE, + BOUND_IMPORT, + IAT, + DELAY_IMPORT_DESCRIPTOR, + CLR_RUNTIME_HEADER, + RESERVED, + UNKNOWN(u32), +} + +/// Data directory's types +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Type::EXPORT_TABLE, + 0x00000001 => Type::IMPORT_TABLE, + 0x00000002 => Type::RESOURCE_TABLE, + 0x00000003 => Type::EXCEPTION_TABLE, + 0x00000004 => Type::CERTIFICATE_TABLE, + 0x00000005 => Type::BASE_RELOCATION_TABLE, + 0x00000006 => Type::DEBUG_DIR, + 0x00000007 => Type::ARCHITECTURE, + 0x00000008 => Type::GLOBAL_PTR, + 0x00000009 => Type::TLS_TABLE, + 0x0000000a => Type::LOAD_CONFIG_TABLE, + 0x0000000b => Type::BOUND_IMPORT, + 0x0000000c => Type::IAT, + 0x0000000d => Type::DELAY_IMPORT_DESCRIPTOR, + 0x0000000e => Type::CLR_RUNTIME_HEADER, + 0x0000000f => Type::RESERVED, + _ => Type::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(ty: Type) -> Self { + match ty { + Type::EXPORT_TABLE => 0x00000000, + Type::IMPORT_TABLE => 0x00000001, + Type::RESOURCE_TABLE => 0x00000002, + Type::EXCEPTION_TABLE => 0x00000003, + Type::CERTIFICATE_TABLE => 0x00000004, + Type::BASE_RELOCATION_TABLE => 0x00000005, + Type::DEBUG_DIR => 0x00000006, + Type::ARCHITECTURE => 0x00000007, + Type::GLOBAL_PTR => 0x00000008, + Type::TLS_TABLE => 0x00000009, + Type::LOAD_CONFIG_TABLE => 0x0000000a, + Type::BOUND_IMPORT => 0x0000000b, + Type::IAT => 0x0000000c, + Type::DELAY_IMPORT_DESCRIPTOR => 0x0000000d, + Type::CLR_RUNTIME_HEADER => 0x0000000e, + Type::RESERVED => 0x0000000f, + Type::UNKNOWN(_) => 0x0000000f, // RESERVED + } + } +} + +impl std::fmt::Debug for DataDirectory<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DataDirectory") + .field("type", &self.get_type()) + .field("rva", &self.rva()) + .field("size", &self.size()) + .field("section", &self.section()) + .finish() + } +} + +impl FromFFI for DataDirectory<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + DataDirectory { + ptr, + _owner: PhantomData, + } + } +} + +impl DataDirectory<'_> { + /// The **relative** virtual address where the data referenced by this data directory are + /// located. + pub fn rva(&self) -> u32 { + self.ptr.RVA() + } + /// The size of the data referenced by this data directory + pub fn size(&self) -> u32 { + self.ptr.size() + } + /// The type of the data directory which is defined by its index. + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + /// The (optional) section in which the data associated with the data directory + /// are located. + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } + + /// Content bytes wraped with this data directory + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } +} + +declare_iterator!( + DataDirectories, + DataDirectory<'a>, + ffi::PE_DataDirectory, + ffi::PE_Binary, + ffi::PE_Binary_it_data_directories +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/debug.rs b/vendor/lief/api/rust/crates/lief/src/pe/debug.rs new file mode 100644 index 0000000..18d0cba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/debug.rs @@ -0,0 +1,1022 @@ +//! Module that wraps the different debug information structure we can find in a PE binary. + +use bitflags::bitflags; +use std::marker::PhantomData; + +use crate::common::into_optional; +use crate::declare_iterator; +use crate::{common::FromFFI, to_slice}; +use lief_ffi as ffi; +use std::pin::Pin; + +use super::Section; + +#[derive(Debug)] +/// This enum exposes the different debug entries that can be +/// found in the debug DataDirectory. +pub enum Entries<'a> { + CodeView(CodeView<'a>), + /// Entry associated with the `IMAGE_DEBUG_TYPE_CODEVIEW` + CodeViewPDB(CodeViewPDB<'a>), + /// Entry associated with `IMAGE_DEBUG_TYPE_REPRO` + Repro(Repro<'a>), + /// Entry associated with `IMAGE_DEBUG_TYPE_POGO` + Pogo(Pogo<'a>), + PDBChecksum(PDBChecksum<'a>), + /// Entry associated with `IMAGE_DEBUG_TYPE_VC_FEATURE` + VCFeature(VCFeature<'a>), + /// Entry associated with `IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS` + ExDllCharacteristics(ExDllCharacteristics<'a>), + /// Entry associated with `IMAGE_DEBUG_TYPE_FPO` + FPO(FPO<'a>), + /// Generic entry for all the other `IMAGE_DEBUG_xxx` + Generic(Generic<'a>), +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone)] +pub enum Type { + COFF, + CODEVIEW, + FPO, + MISC, + EXCEPTION, + FIXUP, + OMAP_TO_SRC, + OMAP_FROM_SRC, + BORLAND, + RESERVED10, + CLSID, + VC_FEATURE, + POGO, + ILTCG, + MPX, + REPRO, + PDBCHECKSUM, + EX_DLLCHARACTERISTICS, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Type::COFF, + 0x00000002 => Type::CODEVIEW, + 0x00000003 => Type::FPO, + 0x00000004 => Type::MISC, + 0x00000005 => Type::EXCEPTION, + 0x00000006 => Type::FIXUP, + 0x00000007 => Type::OMAP_TO_SRC, + 0x00000008 => Type::OMAP_FROM_SRC, + 0x00000009 => Type::BORLAND, + 0x0000000a => Type::RESERVED10, + 0x0000000b => Type::CLSID, + 0x0000000c => Type::VC_FEATURE, + 0x0000000d => Type::POGO, + 0x0000000e => Type::ILTCG, + 0x0000000f => Type::MPX, + 0x00000010 => Type::REPRO, + 0x00000013 => Type::PDBCHECKSUM, + 0x00000014 => Type::EX_DLLCHARACTERISTICS, + _ => Type::UNKNOWN(value), + } + } +} + +pub trait DebugEntry { + #[doc(hidden)] + fn get_base(&self) -> &ffi::PE_Debug; + + #[doc(hidden)] + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug>; + + /// Reserved should be 0 + fn characteristics(&self) -> u32 { + self.get_base().characteristics() + } + + /// The time and date when the debug data was created. + fn timestamp(&self) -> u32 { + self.get_base().timestamp() + } + + /// The major version number of the debug data format. + fn major_version(&self) -> u16 { + self.get_base().major_version() + } + + /// The minor version number of the debug data format. + fn minor_version(&self) -> u16 { + self.get_base().minor_version() + } + + /// The format of the debugging information + fn get_type(&self) -> Type { + Type::from(self.get_base().get_type()) + } + + /// Size of the debug data + fn sizeof_data(&self) -> u32 { + self.get_base().sizeof_data() + } + + /// Address of the debug data relative to the image base + fn addressof_rawdata(&self) -> u32 { + self.get_base().addressof_rawdata() + } + + /// File offset of the debug data + fn pointerto_rawdata(&self) -> u32 { + self.get_base().pointerto_rawdata() + } + + /// The section where debug data is located + fn section(&self) -> Option> { + into_optional(self.get_base().section()) + } + + /// Debug data associated with this entry + fn payload(&self) -> &[u8] { + to_slice!(self.get_base().payload()); + } +} + +impl DebugEntry for Entries<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + match &self { + Entries::CodeView(entry) => entry.get_base(), + + Entries::CodeViewPDB(entry) => entry.get_base(), + + Entries::Repro(entry) => entry.get_base(), + + Entries::Pogo(entry) => entry.get_base(), + + Entries::PDBChecksum(entry) => entry.get_base(), + + Entries::VCFeature(entry) => entry.get_base(), + + Entries::ExDllCharacteristics(entry) => entry.get_base(), + + Entries::FPO(entry) => entry.get_base(), + + Entries::Generic(entry) => entry.get_base(), + } + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + match self { + Entries::CodeView(entry) => entry.get_base_mut(), + + Entries::CodeViewPDB(entry) => entry.get_base_mut(), + + Entries::Repro(entry) => entry.get_base_mut(), + + Entries::Pogo(entry) => entry.get_base_mut(), + + Entries::PDBChecksum(entry) => entry.get_base_mut(), + + Entries::VCFeature(entry) => entry.get_base_mut(), + + Entries::ExDllCharacteristics(entry) => entry.get_base_mut(), + + Entries::FPO(entry) => entry.get_base_mut(), + + Entries::Generic(entry) => entry.get_base_mut(), + } + } +} + +impl std::fmt::Debug for &dyn DebugEntry { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DebugEntry") + .field("characteristics", &self.characteristics()) + .field("timestamp", &self.timestamp()) + .field("major_version", &self.major_version()) + .field("minor_version", &self.minor_version()) + .field("type", &self.get_type()) + .field("sizeof_data", &self.sizeof_data()) + .field("addressof_rawdata", &self.addressof_rawdata()) + .field("pointerto_rawdata", &self.pointerto_rawdata()) + .finish() + } +} + +impl<'a> FromFFI for Entries<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let debug_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_Pogo::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Pogo(Pogo::from_ffi(raw)) + } else if ffi::PE_CodeViewPDB::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::CodeViewPDB(CodeViewPDB::from_ffi(raw)) + } else if ffi::PE_Repro::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::Repro(Repro::from_ffi(raw)) + } else if ffi::PE_CodeView::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::CodeView(CodeView::from_ffi(raw)) + } else if ffi::PE_PDBChecksum::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::PDBChecksum(PDBChecksum::from_ffi(raw)) + } else if ffi::PE_VCFeature::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::VCFeature(VCFeature::from_ffi(raw)) + } else if ffi::PE_ExDllCharacteristics::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::ExDllCharacteristics(ExDllCharacteristics::from_ffi(raw)) + } else if ffi::PE_FPO::classof(debug_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Entries::FPO(FPO::from_ffi(raw)) + } else { + Entries::Generic(Generic::from_ffi(ffi_entry)) + } + } + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for Generic<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DebugEntry for Generic<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("Generic").field("base", &base).finish() + } +} + +/// This structure represents a *Profile Guided Optimization* entry from the +/// debug directory (`IMAGE_DEBUG_TYPE_POGO`). +pub struct Pogo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +/// Signature type for [`Pogo`] debug entries +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum PogoSignature { + ZERO, + LCTG, + PGI, + PGO, + PGU, + SPGO, + UNKNOWN(u32), +} + +impl From for PogoSignature { + fn from(value: u32) -> Self { + match value { + 0x00000000 => PogoSignature::ZERO, + 0x4C544347 => PogoSignature::LCTG, + 0x50474900 => PogoSignature::PGI, + 0x50474F00 => PogoSignature::PGO, + 0x50475500 => PogoSignature::PGU, + 0x5350474f => PogoSignature::SPGO, + _ => PogoSignature::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: PogoSignature) -> u32 { + match value { + PogoSignature::ZERO => 0x00000000, + PogoSignature::LCTG => 0x4C544347, + PogoSignature::PGI => 0x50474900, + PogoSignature::PGO => 0x50474F00, + PogoSignature::PGU => 0x50475500, + PogoSignature::SPGO => 0x5350474f, + PogoSignature::UNKNOWN(v) => v, + } + } +} + +impl Pogo<'_> { + /// An iterator over the different POGO elements: [`PogoEntry`] + pub fn entries(&self) -> PogoEntries<'_> { + PogoEntries::new(self.ptr.entries()) + } + + /// The POGO signature + pub fn signature(&self) -> PogoSignature { + PogoSignature::from(self.ptr.pogo_signature()) + } +} + +impl<'a> FromFFI for Pogo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DebugEntry for Pogo<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Pogo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("Pogo").field("base", &base).finish() + } +} + +/// Structure which represents an entry in the [`Pogo`] debug structure +pub struct PogoEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Pogo>, +} + +impl<'a> FromFFI for PogoEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl PogoEntry<'_> { + pub fn start_rva(&self) -> u32 { + self.ptr.start_rva() + } + pub fn size(&self) -> u32 { + self.ptr.size() + } + pub fn name(&self) -> String { + self.ptr.name().to_string() + } +} + +impl std::fmt::Debug for PogoEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PogoEntry") + .field("name", &self.name()) + .field("size", &self.size()) + .field("start_rva", &self.start_rva()) + .finish() + } +} + +/// Structure that represents the (generic) Debug CodeView (`IMAGE_DEBUG_TYPE_CODEVIEW`). +pub struct CodeView<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +/// Signature type for [`CodeView`] debug entries +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum CodeViewSignature { + /// PDB 7.0 signature + PDB_70, + /// PDB 2.0 signature + PDB_20, + /// CodeView 5.0 signature + CV_50, + /// CodeView 4.1 signature + CV_41, + UNKNOWN(u32), +} + +impl From for CodeViewSignature { + fn from(value: u32) -> Self { + match value { + 0x53445352 => CodeViewSignature::PDB_70, + 0x3031424e => CodeViewSignature::PDB_20, + 0x3131424e => CodeViewSignature::CV_50, + 0x3930424e => CodeViewSignature::CV_41, + _ => CodeViewSignature::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: CodeViewSignature) -> u32 { + match value { + CodeViewSignature::PDB_70 => 0x53445352, + CodeViewSignature::PDB_20 => 0x3031424e, + CodeViewSignature::CV_50 => 0x3131424e, + CodeViewSignature::CV_41 => 0x3930424e, + CodeViewSignature::UNKNOWN(v) => v, + } + } +} + +impl CodeView<'_> { + /// The CodeView signature that defines the type of the CodeView entry + pub fn cv_signature(&self) -> CodeViewSignature { + CodeViewSignature::from(self.ptr.signature()) + } +} + +impl<'a> FromFFI for CodeView<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DebugEntry for CodeView<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for CodeView<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("CodeView") + .field("base", &base) + .field("cv_signature", &self.cv_signature()) + .finish() + } +} + +/// CodeView PDB specialization +pub struct CodeViewPDB<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for CodeViewPDB<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// CodeView PDB specialization +impl CodeViewPDB<'_> { + pub fn new() -> CodeViewPDB<'static> { + CodeViewPDB::from_ffi(ffi::PE_CodeViewPDB::create()) + } + + pub fn with_filename(filename: &str) -> CodeViewPDB<'static> { + cxx::let_cxx_string!(__cxx_s = filename); + CodeViewPDB::from_ffi(ffi::PE_CodeViewPDB::create_with_filename(&__cxx_s)) + } + + /// Age value to verify. The age does not necessarily correspond to any known + /// time value, it is used to determine if a .pdb file is out of sync with a corresponding + /// `.exe` file. + pub fn age(&self) -> u32 { + self.ptr.age() + } + + /// The path to the `.pdb` file + pub fn filename(&self) -> String { + self.ptr.filename().to_string() + } + + /// The GUID signature to verify against the .pdb file signature. + /// This attribute might be used to lookup remote PDB file on a symbol server. + pub fn guid(&self) -> String { + self.ptr.guid().to_string() + } + + /// The 32-bit signature to verify against the .pdb file signature. + pub fn signature(&self) -> [u8; 16] { + let vector: Vec = self.ptr.signature().iter().map(|&e| e as u8).collect(); + vector.try_into().expect("Wrong size") + } + + /// Change or set the PDB filename + pub fn set_filename(&mut self, filename: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = filename); + self.ptr.pin_mut().set_filename(&__cxx_s); + self + } + + pub fn set_age(&mut self, age: u32) -> &mut Self { + self.ptr.pin_mut().set_age(age); + self + } + + pub fn set_signature(&mut self, signature: &[u8; 16]) -> &mut Self { + unsafe { + self.ptr + .pin_mut() + .set_signature(signature.as_ptr(), signature.len()); + } + self + } +} + +impl DebugEntry for CodeViewPDB<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref().as_ref() as *const ffi::PE_Debug + as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for CodeViewPDB<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("CodeViewPDB") + .field("base", &base) + .field("age", &self.age()) + .field("filename", &self.filename()) + .finish() + } +} + +/// This structure represents a reproducible build entry from the debug directory +/// (`IMAGE_DEBUG_TYPE_REPRO`) +/// +/// This entry is usually generated with the undocumented `/Brepro` linker flag. +/// See: +pub struct Repro<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for Repro<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Repro<'_> { + /// The hash associated with the reproducible build + pub fn hash(&self) -> &[u8] { + to_slice!(self.ptr.hash()); + } +} + +impl DebugEntry for Repro<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Repro<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("Repro").field("base", &base).finish() + } +} + +declare_iterator!( + PogoEntries, + PogoEntry<'a>, + ffi::PE_PogoEntry, + ffi::PE_Pogo, + ffi::PE_Pogo_it_entries +); + +/// This structure represents the PDB Checksum debug entry which is essentially +/// an array of bytes representing the checksum of the PDB content. +pub struct PDBChecksum<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for PDBChecksum<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum ChecksumAlgorithm { + SHA256, + UNKNOWN(u32), +} + +impl From for ChecksumAlgorithm { + fn from(value: u32) -> Self { + match value { + 0x00000001 => ChecksumAlgorithm::SHA256, + _ => ChecksumAlgorithm::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: ChecksumAlgorithm) -> u32 { + match value { + ChecksumAlgorithm::SHA256 => 0x00000001, + ChecksumAlgorithm::UNKNOWN(value) => value, + } + } +} + +impl PDBChecksum<'_> { + /// Hash of the PDB content + pub fn hash(&self) -> &[u8] { + to_slice!(self.ptr.hash()); + } + + /// Algorithm used for hashing the PDB content + pub fn algorithm(&self) -> ChecksumAlgorithm { + ChecksumAlgorithm::from(self.ptr.algo()) + } +} + +impl std::fmt::Debug for PDBChecksum<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("PDBChecksum").field("base", &base).finish() + } +} + +impl DebugEntry for PDBChecksum<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +/// This structure represents the `IMAGE_DEBUG_TYPE_VC_FEATURE` debug entry +pub struct VCFeature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for VCFeature<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl VCFeature<'_> { + /// Count for `Pre-VC++ 11.00` + pub fn pre_vcpp(&self) -> u32 { + self.ptr.pre_vcpp() + } + + /// Count for `C/C++` + pub fn c_cpp(&self) -> u32 { + self.ptr.c_cpp() + } + + /// Count for `/GS` (number of guard stack) + pub fn gs(&self) -> u32 { + self.ptr.gs() + } + + /// Whether `/sdl` was enabled for this binary. + /// + /// `sdl` stands for Security Development Lifecycle and provides enhanced + /// security features like changing security-relevant warnings into errors or + /// enforcing guard stack. + pub fn sdl(&self) -> u32 { + self.ptr.sdl() + } + + /// Count for `/guardN` + pub fn guards(&self) -> u32 { + self.ptr.guards() + } +} + +impl DebugEntry for VCFeature<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for VCFeature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("VCFeature").field("base", &base).finish() + } +} + +/// This structure represents the `IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS` debug entry +pub struct ExDllCharacteristics<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for ExDllCharacteristics<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct ExtendedDLLCharacteristics: u32 { + const CET_COMPAT = 0x1; + const CET_COMPAT_STRICT_MODE = 0x2; + const CET_SET_CONTEXT_IP_VALIDATION_RELAXED_MODE = 0x4; + const CET_DYNAMIC_APIS_ALLOW_IN_PROC = 0x8; + const CET_RESERVED_1 = 0x10; + const CET_RESERVED_2 = 0x20; + const FORWARD_CFI_COMPAT = 0x40; + const HOTPATCH_COMPATIBLE = 0x80; + } +} + +impl From for ExtendedDLLCharacteristics { + fn from(value: u32) -> Self { + ExtendedDLLCharacteristics::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: ExtendedDLLCharacteristics) -> Self { + value.bits() + } +} + +impl std::fmt::Display for ExtendedDLLCharacteristics { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl ExDllCharacteristics<'_> { + pub fn characteristics(&self) -> ExtendedDLLCharacteristics { + ExtendedDLLCharacteristics::from(self.ptr.characteristics()) + } +} + +impl DebugEntry for ExDllCharacteristics<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for ExDllCharacteristics<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("ExDllCharacteristics") + .field("base", &base) + .finish() + } +} + +/// This structure represents the `IMAGE_DEBUG_TYPE_FPO` debug entry +pub struct FPO<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FPO<'_> { + pub fn entries(&self) -> FPOEntries<'_> { + FPOEntries::new(self.ptr.entries()) + } +} + +impl<'a> FromFFI for FPO<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl DebugEntry for FPO<'_> { + fn get_base(&self) -> &ffi::PE_Debug { + self.ptr.as_ref().unwrap().as_ref() + } + + fn get_base_mut(&mut self) -> Pin<&mut ffi::PE_Debug> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_Debug as *mut ffi::PE_Debug) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for FPO<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn DebugEntry; + f.debug_struct("FPO").field("base", &base).finish() + } +} + +/// This structure represents the stack frame layout for a x86 function when frame pointer +/// omission (FPO) optimization is used. +pub struct FPOEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_FPO>, +} + +impl FPOEntry<'_> { + /// The function RVA + pub fn rva(&self) -> u32 { + self.ptr.rva() + } + + /// The number of bytes in the function. + pub fn proc_size(&self) -> u32 { + self.ptr.proc_size() + } + + /// The number of local variables. + pub fn nb_locals(&self) -> u32 { + self.ptr.nb_locals() + } + + /// The size of the parameters + pub fn parameters_size(&self) -> u32 { + self.ptr.parameters_size() + } + + /// The number of bytes in the function prolog code. + pub fn prolog_size(&self) -> u16 { + self.ptr.prolog_size() + } + + /// Number of registers saved + pub fn nb_saved_regs(&self) -> u16 { + self.ptr.nb_saved_regs() + } + + /// Whether the function uses structured exception handling. + pub fn use_seh(&self) -> bool { + self.ptr.use_seh() + } + + /// Whether the EBP register has been allocated. + pub fn use_bp(&self) -> bool { + self.ptr.use_bp() + } + + /// Reserved for future use + pub fn reserved(&self) -> u16 { + self.ptr.reserved() + } + + /// Variable that indicates the frame type. + pub fn frame_type(&self) -> u32 { + self.ptr.get_type() + } +} + +impl<'a> FromFFI for FPOEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + FPOEntries, + FPOEntry<'a>, + ffi::PE_FPO_entry_t, + ffi::PE_FPO, + ffi::PE_FPO_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/delay_import.rs b/vendor/lief/api/rust/crates/lief/src/pe/delay_import.rs new file mode 100644 index 0000000..080cb8e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/delay_import.rs @@ -0,0 +1,194 @@ +//! PE Delayed import module +use crate::{common::FromFFI, declare_iterator, generic}; +use lief_ffi as ffi; +use std::marker::PhantomData; +use std::pin::Pin; + +pub struct DelayImport<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl DelayImport<'_> { + /// According to the official PE specifications, this value is reserved and should be set to 0 + pub fn attribute(&self) -> u32 { + self.ptr.attribute() + } + + /// Return the library's name (e.g. `kernel32.dll`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// The RVA of the module handle (in the ``.data`` section). + /// It is used for storage by the routine that is supplied to manage delay-loading. + pub fn handle(&self) -> u32 { + self.ptr.handle() + } + + /// RVA of the delay-load import address table. + pub fn iat(&self) -> u32 { + self.ptr.iat() + } + + /// RVA of the delay-load import names table. + /// + /// The content of this table has the layout as the Import lookup table + pub fn names_table(&self) -> u32 { + self.ptr.names_table() + } + + /// RVA of the **bound** delay-load import address table or 0 if the table does not exist. + pub fn biat(&self) -> u32 { + self.ptr.biat() + } + + /// RVA of the **unload** delay-load import address table or 0 + /// if the table does not exist. + /// + /// According to the PE specifications, this table is an + /// exact copy of the delay import address table that can be + /// used to to restore the original IAT the case of unloading. + pub fn uiat(&self) -> u32 { + self.ptr.uiat() + } + + /// The timestamp of the DLL to which this image has been bound. + pub fn timestamp(&self) -> u32 { + self.ptr.timestamp() + } + + /// Iterator over the DelayImport's entries ([`DelayImportEntry`]) + pub fn entries(&self) -> Entries<'_> { + Entries::new(self.ptr.entries()) + } +} + +impl std::fmt::Debug for DelayImport<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DelayImport") + .field("attribute", &self.attribute()) + .field("name", &self.name()) + .field("handle", &self.handle()) + .field("iat", &self.iat()) + .field("names_table", &self.names_table()) + .field("biat", &self.biat()) + .field("uiat", &self.uiat()) + .field("timestamp", &self.timestamp()) + .finish() + } +} + +impl<'a> FromFFI for DelayImport<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + DelayImport { + ptr, + _owner: PhantomData, + } + } +} + +/// Structure that represents an entry (i.e. an import) in the delay import table. +/// +/// It implements the [`generic::Symbol`] trait that exposes [`generic::Symbol::name`] and +/// [`generic::Symbol::value`]. +/// +/// The meaning of [`generic::Symbol::value`] for this PE object is the address (as an RVA) in the +/// IAT where the resolution should take place. +pub struct DelayImportEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DelayImport>, +} + +impl DelayImportEntry<'_> { + /// `True` if it is an import by ordinal + pub fn is_ordinal(&self) -> bool { + self.ptr.is_ordinal() + } + + /// The ordinal value + pub fn ordinal(&self) -> u16 { + self.ptr.ordinal() + } + + /// See: [`DelayImportEntry::data`] + pub fn hint_name_rva(&self) -> u64 { + self.ptr.hint_name_rva() + } + + /// Index into the export table that is used to speed-up the symbol resolution + pub fn hint(&self) -> u16 { + self.ptr.hint() + } + + /// Value of the current entry in the Import Address Table. + pub fn iat_value(&self) -> u64 { + self.ptr.iat_value() + } + + /// Raw value + pub fn data(&self) -> u64 { + self.ptr.data() + } + + /// Demangled representation of the symbol or an empty string if it can't + /// be demangled + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } +} + +impl generic::Symbol for DelayImportEntry<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for DelayImportEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("DelayImportEntry") + .field("base", &base) + .field("ordinal", &self.ordinal()) + .field("hint_name_rva", &self.hint_name_rva()) + .field("hint", &self.hint()) + .field("iat_value", &self.iat_value()) + .field("data", &self.data()) + .finish() + } +} + +impl<'a> FromFFI for DelayImportEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + DelayImports, + DelayImport<'a>, + ffi::PE_DelayImport, + ffi::PE_Binary, + ffi::PE_Binary_it_delay_imports +); +declare_iterator!( + Entries, + DelayImportEntry<'a>, + ffi::PE_DelayImportEntry, + ffi::PE_DelayImport, + ffi::PE_DelayImport_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/dynamic_fixups.rs b/vendor/lief/api/rust/crates/lief/src/pe/dynamic_fixups.rs new file mode 100644 index 0000000..f4bcb6f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/dynamic_fixups.rs @@ -0,0 +1,698 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::pe::Relocation; +use crate::{declare_fwd_iterator, declare_iterator, to_slice}; +use std::marker::PhantomData; + +/// This enum wraps the different fixups that can be associated with a +/// [`crate::pe::DynamicRelocation`] +#[derive(Debug)] +pub enum DynamicFixup<'a> { + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is not + /// a special value + Generic(Generic<'a>), + + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is set + /// to [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_ARM64X`] + Arm64X(Arm64X<'a>), + + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is set + /// to [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE`] + FunctionOverride(FunctionOverride<'a>), + + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is set + /// to [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER`] + ARM64Kernel(ARM64Kernel<'a>), + + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is set + /// to [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER`] + ControlTransfer(ControlTransfer<'a>), + + /// Entry when [`crate::pe::dynamic_relocation::AsDynamicRelocation::symbol`] is set + /// to a special value that is not supported by LIEF. + Unknown(Unknown<'a>), +} + +impl<'a> FromFFI for DynamicFixup<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_DynamicFixupARM64Kernel::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::ARM64Kernel(ARM64Kernel::from_ffi(raw)) + } else if ffi::PE_DynamicFixupARM64X::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::Arm64X(Arm64X::from_ffi(raw)) + } else if ffi::PE_DynamicFixupControlTransfer::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::ControlTransfer(ControlTransfer::from_ffi(raw)) + } else if ffi::PE_DynamicFixupGeneric::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::Generic(Generic::from_ffi(raw)) + } else if ffi::PE_DynamicFixupUnknown::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::Unknown(Unknown::from_ffi(raw)) + } else if ffi::PE_FunctionOverride::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicFixup::FunctionOverride(FunctionOverride::from_ffi(raw)) + } else { + panic!("unsupported version"); + } + } + } +} + +pub trait AsDynamicFixup { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_DynamicFixup; +} + +impl std::fmt::Display for DynamicFixup<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + match self { + DynamicFixup::Generic(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + + DynamicFixup::Arm64X(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + + DynamicFixup::FunctionOverride(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + + DynamicFixup::ARM64Kernel(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + + DynamicFixup::ControlTransfer(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + + DynamicFixup::Unknown(fixup) => { + write!(f, "{}", fixup.as_generic().to_string()) + } + } + } +} + +/// This structure represents a generic entry where fixups are regular +/// relocations: [`crate::pe::Relocation`] +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for Generic<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for Generic<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Generic").finish() + } +} + +impl std::fmt::Display for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl Generic<'_> { + /// Iterator over the (regular) relocations + pub fn relocations(&self) -> GenericRelocations<'_> { + GenericRelocations::new(self.ptr.relocations()) + } +} + +/// This structure represents the [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_ARM64X`] +/// special value +pub struct Arm64X<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for Arm64X<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for Arm64X<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for Arm64X<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Arm64X").finish() + } +} + +impl std::fmt::Display for Arm64X<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl Arm64X<'_> { + /// Iterator over the relocations + pub fn relocations(&self) -> Arm64XRelocEntries<'_> { + Arm64XRelocEntries::new(self.ptr.relocations()) + } +} + +/// Structure that describes a relocation entry for [`Arm64X`] +pub struct Arm64XRelocEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicFixupARM64X>, +} + +impl<'a> FromFFI for Arm64XRelocEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +pub const ARM64X_RELOC_ZERO_FILL: u32 = 0; + +pub const ARM64X_RELOC_VALUE: u32 = 1; + +pub const ARM64X_RELOC_DELTA: u32 = 2; + +impl Arm64XRelocEntry<'_> { + /// RVA where the fixup takes place + pub fn rva(&self) -> u32 { + self.ptr.rva() + } + + pub fn size(&self) -> u32 { + self.ptr.size() + } + + /// If the fixup is [`ARM64X_RELOC_DELTA`], return the associated delta. + pub fn value(&self) -> Option { + if self.kind() != ARM64X_RELOC_DELTA { + return None; + } + Some(self.ptr.value()) + } + + /// If the fixup is [`ARM64X_RELOC_VALUE`], return the associated bytes. + pub fn bytes(&self) -> Option<&[u8]> { + if self.kind() != ARM64X_RELOC_VALUE { + return None; + } + unsafe { + let raw = self.ptr.get_bytes(); + if raw.size > 0 { + return Some(std::slice::from_raw_parts_mut(raw.ptr, raw.size as usize)); + } + Some(&[]) + } + } + + /// Fixup's kind can be either: + /// + /// - [`ARM64X_RELOC_ZERO_FILL`] + /// - [`ARM64X_RELOC_VALUE`] + /// - [`ARM64X_RELOC_DELTA`] + pub fn kind(&self) -> u32 { + self.ptr.get_type() + } +} + +/// This structure represents the +/// [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE`] special value +pub struct FunctionOverride<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for FunctionOverride<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for FunctionOverride<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for FunctionOverride<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("FunctionOverride").finish() + } +} + +impl std::fmt::Display for FunctionOverride<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl FunctionOverride<'_> { + /// Iterator over the overriding info + pub fn func_overriding_info(&self) -> ItFuncOverrideInfo<'_> { + ItFuncOverrideInfo::new(self.ptr.func_overriding_info()) + } + + /// Find the `IMAGE_BDD_INFO` associated with the given info + pub fn bdd_info(&self) -> ItImageBddInfo<'_> { + ItImageBddInfo::new(self.ptr.bdd_info()) + } + + /// Find the `IMAGE_BDD_INFO` at the given offset + pub fn bdd_info_at(&self, offset: u32) -> Option> { + into_optional(self.ptr.bdd_info_at(offset)) + } + + /// Find the `IMAGE_BDD_INFO` associated with the given info + pub fn bdd_info_for(&self, info: &FunctionOverrideInfo) -> Option> { + into_optional(self.ptr.bdd_info_for(info.ptr.as_ref().unwrap())) + } +} + +/// Mirror `IMAGE_BDD_DYNAMIC_RELOCATION` +pub struct ImageBddDynamicRelocation<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_FunctionOverride>, +} + +impl<'a> FromFFI + for ImageBddDynamicRelocation<'a> +{ + fn from_ffi( + ptr: cxx::UniquePtr, + ) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl ImageBddDynamicRelocation<'_> { + pub fn left(&self) -> u16 { + self.ptr.left() + } + + pub fn right(&self) -> u16 { + self.ptr.right() + } + + pub fn value(&self) -> u32 { + self.ptr.value() + } +} + +/// Mirror `IMAGE_BDD_INFO` +pub struct ImageBddInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_FunctionOverride>, +} + +impl<'a> FromFFI for ImageBddInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl ImageBddInfo<'_> { + pub fn version(&self) -> u32 { + self.ptr.version() + } + + pub fn original_size(&self) -> u32 { + self.ptr.original_size() + } + + pub fn original_offset(&self) -> u32 { + self.ptr.original_offset() + } + + /// If [`ImageBddInfo::version`] is 1 + pub fn payload(&self) -> &[u8] { + to_slice!(self.ptr.payload()); + } + + /// If [`ImageBddInfo::version`] is not 1 + pub fn relocations(&self) -> ImageBddDynRelocations<'_> { + ImageBddDynRelocations::new(self.ptr.relocations()) + } +} + +pub struct FunctionOverrideInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_FunctionOverride>, +} + +impl<'a> FromFFI for FunctionOverrideInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl FunctionOverrideInfo<'_> { + /// RVA of the original function + pub fn original_rva(&self) -> u32 { + self.ptr.original_rva() + } + + /// Offset into the BDD region + pub fn bdd_offset(&self) -> u32 { + self.ptr.bdd_offset() + } + + /// Size in bytes taken by RVAs + pub fn rva_size(&self) -> u32 { + self.ptr.rva_size() + } + + /// Size in bytes taken by BaseRelocs + pub fn base_reloc_size(&self) -> u32 { + self.ptr.base_reloc_size() + } + + pub fn functions_rva(&self) -> Vec { + Vec::from(self.ptr.functions_rva().as_slice()) + } + + pub fn relocations(&self) -> FuncOverrideRelocations<'_> { + FuncOverrideRelocations::new(self.ptr.relocations()) + } +} + +/// This class wraps fixups associated with the (special) symbol value: +/// [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER`]. +pub struct ARM64Kernel<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for ARM64Kernel<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for ARM64Kernel<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for ARM64Kernel<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("ARM64Kernel").finish() + } +} + +impl std::fmt::Display for ARM64Kernel<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl ARM64Kernel<'_> { + /// Iterator over the different relocations + pub fn relocations(&self) -> ARM64KernelEntries<'_> { + ARM64KernelEntries::new(self.ptr.relocations()) + } +} + +/// Mirror `IMAGE_IMPORT_CONTROL_TRANSFER_ARM64_RELOCATION` +pub struct ARM64KernelEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicFixupARM64Kernel>, +} + +impl<'a> FromFFI for ARM64KernelEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl ARM64KernelEntry<'_> { + /// RVA to the call instruction + pub fn rva(&self) -> u32 { + self.ptr.rva() + } + + /// True if target instruction is a `blr`, false if it's a `br`. + pub fn indirect_call(&self) -> bool { + self.ptr.indirect_call() + } + + /// Register index used for the indirect call/jump. + /// For instance, if the instruction is `br x3`, this index is set to `3` + pub fn register_index(&self) -> u8 { + self.ptr.register_index() + } + + /// IAT index of the corresponding import. `0x7FFF` is a special value + /// indicating no index. + pub fn iat_index(&self) -> u16 { + self.ptr.iat_index() + } +} + +/// This class wraps fixups associated with the (special) symbol value: +/// [`crate::pe::dynamic_relocation::IMAGE_DYNAMIC_RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER`]. +pub struct ControlTransfer<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for ControlTransfer<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for ControlTransfer<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for ControlTransfer<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("ControlTransfer").finish() + } +} + +impl std::fmt::Display for ControlTransfer<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl ControlTransfer<'_> { + /// Iterator over the relocations + pub fn relocations(&self) -> ControlTransferEntries<'_> { + ControlTransferEntries::new(self.ptr.relocations()) + } +} + +/// Mirror `IMAGE_IMPORT_CONTROL_TRANSFER_DYNAMIC_RELOCATION` +pub struct ControlTransferEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicFixupControlTransfer>, +} + +impl<'a> FromFFI for ControlTransferEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl ControlTransferEntry<'_> { + /// RVA to the call instruction + pub fn rva(&self) -> u32 { + self.ptr.rva() + } + + /// True if target instruction is a `call`, false otherwise. + pub fn is_call(&self) -> bool { + self.ptr.is_call() + } + + /// IAT index of the corresponding import. `0x7FFF` is a special value + /// indicating no index. + pub fn iat_index(&self) -> u16 { + self.ptr.iat_index() + } +} + +/// This class represents an special dynamic relocation where the format of the +/// fixups is not supported by LIEF. +pub struct Unknown<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_DynamicRelocation>, +} + +impl<'a> FromFFI for Unknown<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicFixup for Unknown<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicFixup { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for Unknown<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Unknown").finish() + } +} + +impl std::fmt::Display for Unknown<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl Unknown<'_> { + pub fn payload(&self) -> &[u8] { + to_slice!(self.ptr.payload()); + } +} + +declare_iterator!( + ARM64KernelEntries, + ARM64KernelEntry<'a>, + ffi::PE_DynamicFixupARM64Kernel_entry, + ffi::PE_DynamicFixupARM64Kernel, + ffi::PE_DynamicFixupARM64Kernel_it_relocations +); + +declare_iterator!( + Arm64XRelocEntries, + Arm64XRelocEntry<'a>, + ffi::PE_DynamicFixupARM64X_entry, + ffi::PE_DynamicFixupARM64X, + ffi::PE_DynamicFixupARM64X_it_relocations +); + +declare_iterator!( + ControlTransferEntries, + ControlTransferEntry<'a>, + ffi::PE_DynamicFixupControlTransfer_entry, + ffi::PE_DynamicFixupControlTransfer, + ffi::PE_DynamicFixupControlTransfer_it_relocations +); + +declare_iterator!( + GenericRelocations, + Relocation<'a>, + ffi::PE_Relocation, + ffi::PE_DynamicFixupGeneric, + ffi::PE_DynamicFixupGeneric_it_relocations +); + +declare_fwd_iterator!( + ImageBddDynRelocations, + ImageBddDynamicRelocation<'a>, + ffi::PE_FunctionOverride_image_bdd_dynamic_relocation_t, + ffi::PE_FunctionOverride_image_bdd_info_t, + ffi::PE_FunctionOverride_image_bdd_info_t_it_relocations +); + +declare_iterator!( + FuncOverrideRelocations, + Relocation<'a>, + ffi::PE_Relocation, + ffi::PE_FunctionOverrideInfo, + ffi::PE_FunctionOverrideInfo_it_relocations +); + +declare_iterator!( + ItFuncOverrideInfo, + FunctionOverrideInfo<'a>, + ffi::PE_FunctionOverrideInfo, + ffi::PE_FunctionOverride, + ffi::PE_FunctionOverride_it_func_overriding_info +); + +declare_iterator!( + ItImageBddInfo, + ImageBddInfo<'a>, + ffi::PE_FunctionOverride_image_bdd_info_t, + ffi::PE_FunctionOverride, + ffi::PE_FunctionOverride_it_bdd_info +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/dynamic_relocation.rs b/vendor/lief/api/rust/crates/lief/src/pe/dynamic_relocation.rs new file mode 100644 index 0000000..8ca81a7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/dynamic_relocation.rs @@ -0,0 +1,188 @@ +//! Module related to dynamic relocations (DVRT) + +use lief_ffi as ffi; + +use super::dynamic_fixups::DynamicFixup; +use crate::common::{FromFFI, into_optional}; +use std::marker::PhantomData; + +pub const IMAGE_DYNAMIC_RELOCATION_GUARD_RF_PROLOGUE: u32 = 1u32; + +pub const IMAGE_DYNAMIC_RELOCATION_GUARD_RF_EPILOGUE: u32 = 2u32; + +pub const IMAGE_DYNAMIC_RELOCATION_GUARD_IMPORT_CONTROL_TRANSFER: u32 = 3u32; + +pub const IMAGE_DYNAMIC_RELOCATION_GUARD_INDIR_CONTROL_TRANSFER: u32 = 4u32; + +pub const IMAGE_DYNAMIC_RELOCATION_GUARD_SWITCHTABLE_BRANCH: u32 = 5u32; + +pub const IMAGE_DYNAMIC_RELOCATION_ARM64X: u32 = 6u32; + +pub const IMAGE_DYNAMIC_RELOCATION_FUNCTION_OVERRIDE: u32 = 7u32; + +pub const IMAGE_DYNAMIC_RELOCATION_ARM64_KERNEL_IMPORT_CALL_TRANSFER: u32 = 8u32; + +/// This enum wraps the different versions of dynamic relocations: +/// +/// - `IMAGE_DYNAMIC_RELOCATION32` +/// - `IMAGE_DYNAMIC_RELOCATION32_V2` +/// - `IMAGE_DYNAMIC_RELOCATION64` +/// - `IMAGE_DYNAMIC_RELOCATION64_V2` +#[derive(Debug)] +pub enum DynamicRelocation<'a> { + /// Either `IMAGE_DYNAMIC_RELOCATION32` or `IMAGE_DYNAMIC_RELOCATION64` + V1(DynamicRelocationV1<'a>), + + /// Either `IMAGE_DYNAMIC_RELOCATION32` or `IMAGE_DYNAMIC_RELOCATION64_V2` + V2(DynamicRelocationV2<'a>), +} + +impl std::fmt::Display for DynamicRelocation<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + match self { + DynamicRelocation::V1(v1) => { + write!(f, "{}", v1.as_generic().to_string()) + } + DynamicRelocation::V2(v2) => { + write!(f, "{}", v2.as_generic().to_string()) + } + } + } +} + +impl<'a> FromFFI for DynamicRelocation<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_DynamicRelocationV1::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicRelocation::V1(DynamicRelocationV1::from_ffi(raw)) + } else if ffi::PE_DynamicRelocationV2::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + DynamicRelocation::V2(DynamicRelocationV2::from_ffi(raw)) + } else { + panic!("unsupported version"); + } + } + } +} + +/// Trait shared by all dynamic relocations +pub trait AsDynamicRelocation { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_DynamicRelocation; + + /// Version of the structure + fn version(&self) -> u32 { + self.as_generic().version() + } + + /// Symbol address. Some values have a special meaning and define how fixups are encoded + fn symbol(&self) -> u64 { + self.as_generic().symbol() + } + + /// Return fixups information, where the interpretation may depend on the + /// [`AsDynamicRelocation::symbol`] + fn fixups(&self) -> Option> { + into_optional(self.as_generic().fixups()) + } +} + +/// This structure represents a dynamic relocation (`IMAGE_DYNAMIC_RELOCATION32` or +/// `IMAGE_DYNAMIC_RELOCATION64`) +pub struct DynamicRelocationV1<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for DynamicRelocationV1<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicRelocation for DynamicRelocationV1<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for DynamicRelocationV1<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DynamicRelocationV1") + .field("version", &self.version()) + .field("symbol", &self.symbol()) + .finish() + } +} + +impl std::fmt::Display for DynamicRelocationV1<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +/// This class represents a dynamic relocation (`IMAGE_DYNAMIC_RELOCATION64_V2` or +/// `IMAGE_DYNAMIC_RELOCATION32_V2`) +pub struct DynamicRelocationV2<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for DynamicRelocationV2<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl AsDynamicRelocation for DynamicRelocationV2<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl std::fmt::Debug for DynamicRelocationV2<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DynamicRelocationV1") + .field("version", &self.version()) + .field("symbol", &self.symbol()) + .finish() + } +} + +impl std::fmt::Display for DynamicRelocationV2<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl AsDynamicRelocation for DynamicRelocation<'_> { + fn as_generic(&self) -> &ffi::PE_DynamicRelocation { + match &self { + DynamicRelocation::V1(entry) => entry.as_generic(), + + DynamicRelocation::V2(entry) => entry.as_generic(), + } + } +} + +impl std::fmt::Display for &dyn AsDynamicRelocation { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/enclave_configuration.rs b/vendor/lief/api/rust/crates/lief/src/pe/enclave_configuration.rs new file mode 100644 index 0000000..65d964f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/enclave_configuration.rs @@ -0,0 +1,273 @@ +//! PE enclave configuration +use std::marker::PhantomData; + +use crate::{common::FromFFI, declare_iterator, to_slice}; +use lief_ffi as ffi; + +/// Defines an entry in the array of images that an enclave can import. +pub struct EnclaveConfiguration<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl EnclaveConfiguration<'_> { + /// The size of the `IMAGE_ENCLAVE_CONFIG64/IMAGE_ENCLAVE_CONFIG32` structure, in bytes. + pub fn size(&self) -> u32 { + self.ptr.size() + } + + /// The minimum size of the `IMAGE_ENCLAVE_CONFIG(32,64)` structure that the + /// image loader must be able to process in order for the enclave to be usable. + /// + /// This member allows an enclave to inform an earlier version of the image + /// loader that the image loader can safely load the enclave and ignore + /// optional members added to `IMAGE_ENCLAVE_CONFIG(32,64)` for later versions + /// of the enclave. If the size of `IMAGE_ENCLAVE_CONFIG(32,64)` that the image + /// loader can process is less than `MinimumRequiredConfigSize`, the enclave + /// cannot be run securely. + /// + /// If `MinimumRequiredConfigSize` is zero, the minimum size of the + /// `IMAGE_ENCLAVE_CONFIG(32,64)` structure that the image loader must be able + /// to process in order for the enclave to be usable is assumed to be the size + /// of the structure through and including the `MinimumRequiredConfigSize` member. + pub fn min_required_config_size(&self) -> u32 { + self.ptr.min_required_config_size() + } + + /// A flag that indicates whether the enclave permits debugging. + pub fn policy_flags(&self) -> u32 { + self.ptr.policy_flags() + } + + /// Whether this enclave can be debugged + pub fn is_debuggable(&self) -> bool { + self.ptr.is_debuggable() + } + + /// The RVA of the array of images that the enclave image may import, with identity information + /// for each image. + pub fn import_list_rva(&self) -> u32 { + self.ptr.import_list_rva() + } + + /// The size of each image in the array of images that the [`EnclaveConfiguration::import_list_rva`] + /// member points to. + pub fn import_entry_size(&self) -> u32 { + self.ptr.import_entry_size() + } + + /// The number of images in the array of images that the [`EnclaveConfiguration::import_list_rva`] + /// member points to. + pub fn nb_imports(&self) -> u32 { + self.ptr.nb_imports() + } + + /// Return an iterator over the enclave's imports + pub fn imports(&self) -> Imports<'_> { + Imports::new(self.ptr.imports()) + } + + /// The family identifier that the author of the enclave assigned to the enclave. + pub fn family_id(&self) -> &[u8] { + to_slice!(self.ptr.family_id()); + } + + /// The image identifier that the author of the enclave assigned to the enclave. + pub fn image_id(&self) -> &[u8] { + to_slice!(self.ptr.image_id()); + } + + /// The version number that the author of the enclave assigned to the enclave. + pub fn image_version(&self) -> u32 { + self.ptr.image_version() + } + + /// The security version number that the author of the enclave assigned to the enclave. + pub fn security_version(&self) -> u32 { + self.ptr.security_version() + } + + /// The expected virtual size of the private address range for the enclave, in bytes. + pub fn enclave_size(&self) -> u64 { + self.ptr.enclave_size() + } + + /// The maximum number of threads that can be created within the enclave. + pub fn nb_threads(&self) -> u32 { + self.ptr.nb_threads() + } + + /// A flag that indicates whether the image is suitable for use as the primary image in the + /// enclave. + pub fn enclave_flags(&self) -> u32 { + self.ptr.enclave_flags() + } +} + +impl std::fmt::Debug for EnclaveConfiguration<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("EnclaveConfiguration") + .field("size", &self.size()) + .field("min_required_config_size", &self.min_required_config_size()) + .field("policy_flags", &self.policy_flags()) + .field("is_debuggable", &self.is_debuggable()) + .field("import_list_rva", &self.import_list_rva()) + .field("import_entry_size", &self.import_entry_size()) + .field("nb_imports", &self.nb_imports()) + .field("family_id", &self.family_id()) + .field("image_version", &self.image_version()) + .field("security_version", &self.security_version()) + .field("enclave_size", &self.enclave_size()) + .field("nb_threads", &self.nb_threads()) + .field("enclave_flags", &self.enclave_flags()) + .finish() + } +} + +impl std::fmt::Display for EnclaveConfiguration<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl<'a> FromFFI for EnclaveConfiguration<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// This structure represents an entry in the array of images that an enclave can import. +pub struct EnclaveImport<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_EnclaveConfiguration>, +} + +impl EnclaveImport<'_> { + /// The type of identifier of the image that must match the value in the import record. + pub fn get_type(&self) -> Type { + Type::from(self.ptr.get_type()) + } + + /// The minimum enclave security version that each image must have for the + /// image to be imported successfully. The image is rejected unless its enclave + /// security version is equal to or greater than the minimum value in the + /// import record. Set the value in the import record to zero to turn off the + /// security version check. + pub fn min_security_version(&self) -> u32 { + self.ptr.min_security_version() + } + + /// The relative virtual address of a NULL-terminated string that contains the + /// same value found in the import directory for the image. + pub fn import_name_rva(&self) -> u32 { + self.ptr.import_name_rva() + } + + /// Resolved import name + pub fn import_name(&self) -> String { + self.ptr.import_name().to_string() + } + + /// Reserved. Should be 0 + pub fn reserved(&self) -> u32 { + self.ptr.reserved() + } + + /// The unique identifier of the primary module for the enclave, if the + /// [`EnclaveImport::get_type`] is [`Type::UNIQUE_ID`]. Otherwise, the author identifier of the + /// primary module for the enclave. + pub fn id(&self) -> &[u8] { + to_slice!(self.ptr.id()); + } + + /// The family identifier of the primary module for the enclave. + pub fn family_id(&self) -> &[u8] { + to_slice!(self.ptr.family_id()); + } + + /// The image identifier of the primary module for the enclave. + pub fn image_id(&self) -> &[u8] { + to_slice!(self.ptr.image_id()); + } +} + +impl std::fmt::Debug for EnclaveImport<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("EnclaveImport") + .field("type", &self.get_type()) + .field("min_security_version", &self.min_security_version()) + .field("import_name_rva", &self.import_name_rva()) + .field("import_name", &self.import_name()) + .field("reserved", &self.reserved()) + .field("id", &self.id()) + .field("family_id", &self.family_id()) + .field("image_id", &self.image_id()) + .finish() + } +} + +impl std::fmt::Display for EnclaveImport<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl<'a> FromFFI for EnclaveImport<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone)] +pub enum Type { + /// None of the identifiers of the image need to match the value in the + /// import record. + NONE, + + /// The value of the enclave unique identifier of the image must match the + /// value in the import record. Otherwise, loading of the image fails. + UNIQUE_ID, + + /// The value of the enclave author identifier of the image must match the + /// value in the import record. Otherwise, loading of the image fails. If + /// this flag is set and the import record indicates an author identifier + /// of all zeros, the imported image must be part of the Windows installation. + AUTHOR_ID, + + /// The value of the enclave family identifier of the image must match the + /// value in the import record. Otherwise, loading of the image fails. + FAMILY_ID, + + /// The value of the enclave image identifier of the image must match the + /// value in the import record. Otherwise, loading of the image fails. + IMAGE_ID, + UNKNOWN(u32), +} + +impl From for Type { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Type::NONE, + 0x00000001 => Type::UNIQUE_ID, + 0x00000002 => Type::AUTHOR_ID, + 0x00000003 => Type::FAMILY_ID, + 0x00000004 => Type::IMAGE_ID, + _ => Type::UNKNOWN(value), + } + } +} + +declare_iterator!( + Imports, + EnclaveImport<'a>, + ffi::PE_EnclaveImport, + ffi::PE_EnclaveConfiguration, + ffi::PE_EnclaveConfiguration_it_imports +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/exception.rs b/vendor/lief/api/rust/crates/lief/src/pe/exception.rs new file mode 100644 index 0000000..c881e65 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/exception.rs @@ -0,0 +1,65 @@ +//! Module for the PE exception support + +use super::exception_aarch64; +use super::exception_x64; +use lief_ffi as ffi; + +use crate::common::FromFFI; + +/// Enum that wraps the different kinds of runtime functions associated with exceptions +#[derive(Debug)] +pub enum RuntimeExceptionFunction<'a> { + /// A x86_64 exception entry + X86_64(exception_x64::RuntimeFunction<'a>), + + /// An ARM64 exception entry + AArch64(exception_aarch64::RuntimeFunction<'a>), +} + +impl<'a> FromFFI for RuntimeExceptionFunction<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_RuntimeFunctionX64::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + RuntimeExceptionFunction::X86_64(exception_x64::RuntimeFunction::from_ffi(raw)) + } else if ffi::PE_RuntimeFunctionAArch64::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + RuntimeExceptionFunction::AArch64(exception_aarch64::RuntimeFunction::from_ffi(raw)) + } else { + panic!("unsupported architecture"); + } + } + } +} + +/// Trait shared by all runtime functions +pub trait ExceptionInfo { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_ExceptionInfo; + + /// Function start address + fn rva_start(&self) -> u32 { + self.as_generic().rva_start() + } + + /// Offset in the binary where the raw exception information associated with + /// this entry is defined + fn offset(&self) -> u64 { + self.as_generic().offset() + } +} + +impl std::fmt::Display for &dyn ExceptionInfo { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/exception_aarch64.rs b/vendor/lief/api/rust/crates/lief/src/pe/exception_aarch64.rs new file mode 100644 index 0000000..0e64c8d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/exception_aarch64.rs @@ -0,0 +1,282 @@ +//! This module contains structures related to the ARM64 exception support in PE files + +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use super::ExceptionInfo; + +use crate::common::FromFFI; +use crate::{declare_iterator, to_slice}; + +/// This enum represents an entry in the exception table (`.pdata` section) for the AArch64 +/// architecture. +/// +/// Since the ARM64 unwinding info can be encoded in a *packed* and *unpacked* format, this enums +/// wraps two entries [`Packed`] and [`Unpacked`]. +/// +/// Reference: +#[derive(Debug)] +pub enum RuntimeFunction<'a> { + /// A packed exception entry that fits on 30 bits + Packed(Packed<'a>), + + /// An extended exception entry that has variable length data + Unpacked(Unpacked<'a>), +} + +impl<'a> FromFFI for RuntimeFunction<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_unwind_aarch64_UnpackedFunction::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + RuntimeFunction::Unpacked(Unpacked::from_ffi(raw)) + } else if ffi::PE_unwind_aarch64_PackedFunction::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + RuntimeFunction::Packed(Packed::from_ffi(raw)) + } else { + panic!("unsupported format: {}", obj_ref.as_ref().to_string()); + } + } + } +} + +impl ExceptionInfo for RuntimeFunction<'_> { + fn as_generic(&self) -> &ffi::PE_ExceptionInfo { + match &self { + RuntimeFunction::Packed(f) => f.as_generic(), + RuntimeFunction::Unpacked(f) => f.as_generic(), + } + } +} + +/// This structure represents a packed AArch64 exception entry. +/// +/// An excepted entry can be packed if the unwind data fit in 30 bits +/// +/// Reference: +pub struct Packed<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for Packed<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Packed<'_> { + /// Size of the allocated stack + pub fn frame_size(&self) -> u8 { + self.ptr.frame_size() + } + + /// Number of non-volatile INT registers (x19-x28) saved in the canonical stack location. + #[allow(non_snake_case)] + pub fn reg_I(&self) -> u8 { + self.ptr.reg_I() + } + + /// Number of non-volatile FP registers (d8-d15) saved in the canonical stack location + #[allow(non_snake_case)] + pub fn reg_F(&self) -> u8 { + self.ptr.reg_F() + } + + /// 1-bit flag indicating whether the function homes the integer parameter registers (x0-x7) by + /// storing them at the very start of the function. + /// (0 = doesn't home registers, 1 = homes registers). + #[allow(non_snake_case)] + pub fn H(&self) -> u8 { + self.ptr.H() + } + + /// Flag indicating whether the function includes extra instructions to set up a frame chain + /// and return link. + #[allow(non_snake_case)] + pub fn CR(&self) -> u8 { + self.ptr.CR() + } +} + +impl ExceptionInfo for Packed<'_> { + fn as_generic(&self) -> &ffi::PE_ExceptionInfo { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl std::fmt::Debug for Packed<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Packed") + .field("frame_size", &self.frame_size()) + .field("RI", &self.reg_I()) + .field("RF", &self.reg_F()) + .field("H", &self.H()) + .field("CR", &self.CR()) + .finish() + } +} + +/// This class represents an unpacked AArch64 exception entry +/// +/// Reference: +pub struct Unpacked<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl<'a> FromFFI for Unpacked<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Unpacked<'_> { + /// RVA where this unpacked data is located (usually pointing in `.xdata`) + pub fn xdata_rva(&self) -> u32 { + self.ptr.xdata_rva() + } + + /// Describes the version of the remaining `.xdata`. + /// + /// Currently (2025-01-04), only version 0 is defined, so values of 1-3 aren't + /// permitted. + pub fn version(&self) -> u32 { + self.ptr.version() + } + + /// 1-bit field that indicates the presence (1) or absence (0) of exception + /// data. + #[allow(non_snake_case)] + pub fn X(&self) -> u8 { + self.ptr.X() + } + + /// 1-bit field that indicates that information describing a single epilog is + /// packed into the header (1) rather than requiring more scope words later (0). + #[allow(non_snake_case)] + pub fn E(&self) -> u8 { + self.ptr.E() + } + + /// If [`Unpacked::E`] == 0, specifies the count of the total number of epilog scopes. + /// Otherwise, return 0 + pub fn epilog_count(&self) -> u16 { + self.ptr.epilog_count() + } + + /// **If E() == 1**, index of the first unwind code that describes the one and + /// only epilog. + pub fn epilog_offset(&self) -> u16 { + self.ptr.epilog_offset() + } + + /// Number of 32-bit words needed to contain all of the unwind codes + pub fn code_words(&self) -> u32 { + self.ptr.code_words() + } + + /// Exception handler RVA (if any) + pub fn exception_handler(&self) -> u32 { + self.ptr.exception_handler() + } + + /// Slices that contain the unwind codes. + pub fn unwind_code(&self) -> &[u8] { + to_slice!(self.ptr.unwind_code()); + } + + /// Iterator over the epilog scopes + pub fn epilog_scopes(&self) -> EpilogScopes<'_> { + EpilogScopes::new(self.ptr.epilog_scopes()) + } +} + +impl ExceptionInfo for Unpacked<'_> { + fn as_generic(&self) -> &ffi::PE_ExceptionInfo { + self.ptr.as_ref().unwrap().as_ref().as_ref() + } +} + +impl std::fmt::Debug for Unpacked<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Unpacked") + .field("xdata_rva", &self.xdata_rva()) + .field("version", &self.version()) + .field("X", &self.X()) + .field("E", &self.E()) + .field("epilog_count", &self.epilog_count()) + .field("epilog_offset", &self.epilog_offset()) + .field("code_words", &self.code_words()) + .field("exception_handler", &self.exception_handler()) + .finish() + } +} + +/// This structure describes an epilog scope. +pub struct EpilogScope<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_unwind_aarch64_UnpackedFunction>, +} + +impl<'a> FromFFI for EpilogScope<'a> { + fn from_ffi( + ptr: cxx::UniquePtr, + ) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl EpilogScope<'_> { + /// Offset of the epilog relatives to the start of the function + pub fn start_offset(&self) -> u32 { + self.ptr.start_offset() + } + + /// Byte index of the first unwind code that describes this epilog + pub fn start_index(&self) -> u16 { + self.ptr.start_index() + } + + /// Reserved for future expansion. Should be 0. + pub fn reserved(&self) -> u8 { + self.ptr.reserved() + } +} + +impl std::fmt::Debug for EpilogScope<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("EpilogScope") + .field("start_offset", &self.start_offset()) + .field("start_index", &self.start_index()) + .field("reserved", &self.reserved()) + .finish() + } +} + +declare_iterator!( + EpilogScopes, + EpilogScope<'a>, + ffi::PE_unwind_aarch64_UnpackedFunction_epilog_scope_t, + ffi::PE_unwind_aarch64_UnpackedFunction, + ffi::PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/exception_x64.rs b/vendor/lief/api/rust/crates/lief/src/pe/exception_x64.rs new file mode 100644 index 0000000..e33b6d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/exception_x64.rs @@ -0,0 +1,730 @@ +//! Module related to the x86_64 exception unwinding support + +use lief_ffi as ffi; + +use std::marker::PhantomData; + +use super::exception::ExceptionInfo; +use crate::common::{FromFFI, into_optional}; +use crate::{declare_fwd_iterator, to_opt, to_slice}; +use bitflags::bitflags; + +/// This structure represents an entry in the exception table (`.pdata` section) +/// for the x86-64 architecture. +/// +/// Reference: +pub struct RuntimeFunction<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FromFFI for RuntimeFunction<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for RuntimeFunction<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn ExceptionInfo; + f.debug_struct("RuntimeFunction(x86_64)") + .field("rva_start", &base.rva_start()) + .field("rva_end", &self.rva_end()) + .field("unwind_rva", &self.unwind_rva()) + .field("size", &self.size()) + .field("unwind_info", &self.unwind_info()) + .finish() + } +} + +impl ExceptionInfo for RuntimeFunction<'_> { + fn as_generic(&self) -> &ffi::PE_ExceptionInfo { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl RuntimeFunction<'_> { + /// Function end address + pub fn rva_end(&self) -> u32 { + self.ptr.rva_end() + } + + /// Unwind info address + pub fn unwind_rva(&self) -> u32 { + self.ptr.unwind_rva() + } + + /// Size of the function (in bytes) + pub fn size(&self) -> u32 { + self.ptr.size() + } + + /// Detailed unwind information + pub fn unwind_info(&self) -> Option> { + into_optional(self.ptr.unwind_info()) + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum UnwindOpcodes { + /// Push a nonvolatile integer register, decrementing RSP by 8. + /// The operation info is the number of the register. Because of the + /// constraints on epilogs, `PUSH_NONVOL` unwind codes must appear first + /// in the prolog and correspondingly, last in the unwind code array. + /// This relative ordering applies to all other unwind codes except + /// [`UnwindOpcodes::PUSH_MACHFRAME`]. + PUSH_NONVOL, + + /// Allocate a large-sized area on the stack. + /// There are two forms. If the operation info equals 0, + /// then the size of the allocation divided by 8 is recorded in the next slot, + /// allowing an allocation up to 512K - 8. If the operation info equals 1, + /// then the unscaled size of the allocation is recorded in the next two + /// slots in little-endian format, allowing allocations up to 4GB - 8. + ALLOC_LARGE, + + /// Allocate a small-sized area on the stack. The size of the allocation is + /// the operation info field * 8 + 8, allowing allocations from 8 to 128 bytes. + ALLOC_SMALL, + + /// Establish the frame pointer register by setting the register to some + /// offset of the current RSP. The offset is equal to the Frame Register + /// offset (scaled) field in the UNWIND_INFO * 16, allowing offsets from + /// 0 to 240. The use of an offset permits establishing a frame pointer that + /// points to the middle of the fixed stack allocation, helping code density + /// by allowing more accesses to use short instruction forms. The operation + /// info field is reserved and shouldn't be us + SET_FPREG, + + /// Save a nonvolatile integer register on the stack using a MOV instead of a + /// PUSH. This code is primarily used for shrink-wrapping, where a nonvolatile + /// register is saved to the stack in a position that was previously allocated. + /// The operation info is the number of the register. The scaled-by-8 stack + /// offset is recorded in the next unwind operation code slot, as described + /// in the note above + SAVE_NONVOL, + + /// Save a nonvolatile integer register on the stack with a long offset, + /// using a MOV instead of a PUSH. This code is primarily used for + /// shrink-wrapping, where a nonvolatile register is saved to the stack in a + /// position that was previously allocated. The operation info is the number + /// of the register. The unscaled stack offset is recorded in the next two + /// unwind operation code slots, as described in the note above. + SAVE_NONVOL_FAR, + + /// This entry is only revelant for version 2. It describes the function + /// epilog. + EPILOG, + + /// Reserved + /// Originally SAVE_XMM128_FAR in version 1, but deprecated and removed + SPARE, + + /// Save all 128 bits of a nonvolatile XMM register on the stack. + /// The operation info is the number of the register. The scaled-by-16 stack + /// offset is recorded in the next slot. + SAVE_XMM128, + + /// Save all 128 bits of a nonvolatile XMM register on the stack with a + /// long offset. The operation info is the number of the register. + /// The unscaled stack offset is recorded in the next two slots. + SAVE_XMM128_FAR, + + /// Push a machine frame. This unwind code is used to record the effect of a + /// hardware interrupt or exception. + PUSH_MACHFRAME, + + UNKNOWN(u32), +} + +impl From for UnwindOpcodes { + fn from(value: u32) -> Self { + match value { + 0x00000000 => UnwindOpcodes::PUSH_NONVOL, + 0x00000001 => UnwindOpcodes::ALLOC_LARGE, + 0x00000002 => UnwindOpcodes::ALLOC_SMALL, + 0x00000003 => UnwindOpcodes::SET_FPREG, + 0x00000004 => UnwindOpcodes::SAVE_NONVOL, + 0x00000005 => UnwindOpcodes::SAVE_NONVOL_FAR, + 0x00000006 => UnwindOpcodes::EPILOG, + 0x00000007 => UnwindOpcodes::SPARE, + 0x00000008 => UnwindOpcodes::SAVE_XMM128, + 0x00000009 => UnwindOpcodes::SAVE_XMM128_FAR, + 0x0000000a => UnwindOpcodes::PUSH_MACHFRAME, + _ => UnwindOpcodes::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: UnwindOpcodes) -> u32 { + match value { + UnwindOpcodes::PUSH_NONVOL => 0x00000000, + UnwindOpcodes::ALLOC_LARGE => 0x00000001, + UnwindOpcodes::ALLOC_SMALL => 0x00000002, + UnwindOpcodes::SET_FPREG => 0x00000003, + UnwindOpcodes::SAVE_NONVOL => 0x00000004, + UnwindOpcodes::SAVE_NONVOL_FAR => 0x00000005, + UnwindOpcodes::EPILOG => 0x00000006, + UnwindOpcodes::SPARE => 0x00000007, + UnwindOpcodes::SAVE_XMM128 => 0x00000008, + UnwindOpcodes::SAVE_XMM128_FAR => 0x00000009, + UnwindOpcodes::PUSH_MACHFRAME => 0x0000000a, + UnwindOpcodes::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum UnwindReg { + RAX, + RCX, + RDX, + RBX, + RSP, + RBP, + RSI, + RDI, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + UNKNOWN(u32), +} + +impl From for UnwindReg { + fn from(value: u32) -> Self { + match value { + 0x00000000 => UnwindReg::RAX, + 0x00000001 => UnwindReg::RCX, + 0x00000002 => UnwindReg::RDX, + 0x00000003 => UnwindReg::RBX, + 0x00000004 => UnwindReg::RSP, + 0x00000005 => UnwindReg::RBP, + 0x00000006 => UnwindReg::RSI, + 0x00000007 => UnwindReg::RDI, + 0x00000008 => UnwindReg::R8, + 0x00000009 => UnwindReg::R9, + 0x0000000a => UnwindReg::R10, + 0x0000000b => UnwindReg::R11, + 0x0000000c => UnwindReg::R12, + 0x0000000d => UnwindReg::R13, + 0x0000000e => UnwindReg::R14, + 0x0000000f => UnwindReg::R15, + _ => UnwindReg::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: UnwindReg) -> u32 { + match value { + UnwindReg::RAX => 0x00000000, + UnwindReg::RCX => 0x00000001, + UnwindReg::RDX => 0x00000002, + UnwindReg::RBX => 0x00000003, + UnwindReg::RSP => 0x00000004, + UnwindReg::RBP => 0x00000005, + UnwindReg::RSI => 0x00000006, + UnwindReg::RDI => 0x00000007, + UnwindReg::R8 => 0x00000008, + UnwindReg::R9 => 0x00000009, + UnwindReg::R10 => 0x0000000a, + UnwindReg::R11 => 0x0000000b, + UnwindReg::R12 => 0x0000000c, + UnwindReg::R13 => 0x0000000d, + UnwindReg::R14 => 0x0000000e, + UnwindReg::R15 => 0x0000000f, + UnwindReg::UNKNOWN(value) => value, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct UnwindFlags: u8 { + /// The function has an exception handler that should be called when looking + /// for functions that need to examine exceptions. + const EXCEPTION_HANDLER = 0x1; + + /// The function has a termination handler that should be called when + /// unwinding an exception. + const TERMINATE_HANDLER = 0x2; + + /// The chained info payload references a previous `RUNTIME_FUNCTION` + const CHAIN_INFO = 0x4; + } +} + +impl From for UnwindFlags { + fn from(value: u8) -> Self { + UnwindFlags::from_bits_truncate(value) + } +} + +impl From for u8 { + fn from(value: UnwindFlags) -> Self { + value.bits() + } +} + +impl std::fmt::Display for UnwindFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +/// This structure represents the `UNWIND_INFO` which records the effects +/// a function has on the stack pointer, and where the nonvolatile registers +/// are saved on the stack. +pub struct UnwindInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FromFFI for UnwindInfo<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl UnwindInfo<'_> { + /// Version number of the unwind data, currently 1 or 2. + pub fn version(&self) -> u8 { + self.ptr.version() + } + + /// See: [`UnwindFlags`] + pub fn flags(&self) -> UnwindFlags { + UnwindFlags::from(self.ptr.flags()) + } + + /// Length of the function prolog in bytes. + pub fn sizeof_prologue(&self) -> u8 { + self.ptr.sizeof_prologue() + } + + /// The number of slots in the unwind codes array. Some unwind codes, for + /// example, [`UnwindOpcodes::SAVE_NONVOL`], require more than one slot in the + /// array + pub fn count_opcodes(&self) -> u8 { + self.ptr.count_opcodes() + } + + /// If nonzero, then the function uses a frame pointer (FP), and this field + /// is the number of the nonvolatile register used as the frame pointer, + /// using the same encoding for the operation info field of [`UnwindOpcodes`] + /// nodes. + pub fn frame_reg(&self) -> u8 { + self.ptr.frame_reg() + } + + /// If the frame register field is nonzero, this field is the scaled offset + /// from RSP that is applied to the FP register when it's established + pub fn frame_reg_offset(&self) -> u8 { + self.ptr.frame_reg_offset() + } + + /// An array of items that explains the effect of the prolog on the + /// nonvolatile registers and RSP + pub fn raw_opcodes(&self) -> &[u8] { + to_slice!(self.ptr.raw_opcodes()); + } + + /// Iterator over the unwind code which outputs [`Opcodes`] + pub fn opcodes(&self) -> OpcodesIterator<'_> { + OpcodesIterator::new(self.ptr.opcodes()) + } + + /// An image-relative pointer to either the function's language-specific + /// exception or termination handler. This value is set if one of these + /// flags is set: [`UnwindFlags::EXCEPTION_HANDLER`], + /// [`UnwindFlags::TERMINATE_HANDLER`] + pub fn handler(&self) -> Option { + to_opt!(&ffi::PE_RuntimeFunctionX64_unwind_info_t::handler, &self); + } + + /// If [`UnwindFlags::CHAIN_INFO`] is set, this attributes references the + /// chained runtime function. + pub fn chained(&self) -> Option> { + into_optional(self.ptr.chained()) + } +} + +impl std::fmt::Debug for UnwindInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("UnwindInfo") + .field("version", &self.version()) + .field("flags", &self.flags()) + .field("sizeof_prologue", &self.sizeof_prologue()) + .field("count_opcodes", &self.count_opcodes()) + .field("frame_reg", &self.frame_reg()) + .field("frame_reg_offset", &self.frame_reg_offset()) + .field("handler", &self.handler()) + .finish() + } +} + +impl std::fmt::Display for UnwindInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +/// Trait shared by all [`Opcodes`] +pub trait Opcode { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code; + + /// Offset in the prolog + fn position(&self) -> u32 { + self.as_generic().position() + } + + /// The original opcode + fn opcode(&self) -> UnwindOpcodes { + UnwindOpcodes::from(self.as_generic().opcode()) + } +} + +impl std::fmt::Display for &dyn Opcode { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +/// The different `x86_64` unwind opcodes. +pub enum Opcodes<'a> { + /// Represents a stack-allocation operation + Alloc(Alloc<'a>), + + /// Push a nonvolatile integer register + PushNonVol(PushNonVol<'a>), + + /// Push a machine frame + PushMachFrame(PushMachFrame<'a>), + + /// Establish the frame pointer register + SetFPReg(SetFPReg<'a>), + + /// Save a nonvolatile integer register + SaveNonVolatile(SaveNonVolatile<'a>), + + SaveXMM128(SaveXMM128<'a>), + + /// Describes the function's epilog + Epilog(Epilog<'a>), + Spare(Spare<'a>), +} + +impl<'a> FromFFI for Opcodes<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let code_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_unwind_x64_Alloc::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::Alloc(Alloc::from_ffi(raw)) + } else if ffi::PE_unwind_x64_PushNonVol::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::PushNonVol(PushNonVol::from_ffi(raw)) + } else if ffi::PE_unwind_x64_PushMachFrame::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::PushMachFrame(PushMachFrame::from_ffi(raw)) + } else if ffi::PE_unwind_x64_SetFPReg::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::SetFPReg(SetFPReg::from_ffi(raw)) + } else if ffi::PE_unwind_x64_SaveNonVolatile::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::SaveNonVolatile(SaveNonVolatile::from_ffi(raw)) + } else if ffi::PE_unwind_x64_SaveXMM128::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::SaveXMM128(SaveXMM128::from_ffi(raw)) + } else if ffi::PE_unwind_x64_Epilog::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::Epilog(Epilog::from_ffi(raw)) + } else if ffi::PE_unwind_x64_Spare::classof(code_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Opcodes::Spare(Spare::from_ffi(raw)) + } else { + panic!("Unknown opcode"); + } + } + } +} + +/// This structure represents a stack-allocation operation +/// ([`UnwindOpcodes::ALLOC_SMALL`] or [`UnwindOpcodes::ALLOC_LARGE`]). +pub struct Alloc<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for Alloc<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for Alloc<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Alloc<'_> { + /// The size allocated + pub fn size(&self) -> u32 { + self.ptr.size() + } +} + +/// Push a nonvolatile integer register, decrementing RSP by 8 +pub struct PushNonVol<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for PushNonVol<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for PushNonVol<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PushNonVol<'_> { + /// The register pushed + pub fn reg(&self) -> UnwindReg { + UnwindReg::from(self.ptr.reg()) + } +} + +/// Push a machine frame +pub struct PushMachFrame<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for PushMachFrame<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for PushMachFrame<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl PushMachFrame<'_> { + /// The register pushed + pub fn value(&self) -> u8 { + self.ptr.value() + } +} + +/// Establish the frame pointer register by setting the register to some offset +/// of the current RSP +pub struct SetFPReg<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for SetFPReg<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for SetFPReg<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl SetFPReg<'_> { + /// The register pushed + pub fn reg(&self) -> UnwindReg { + UnwindReg::from(self.ptr.reg()) + } +} + +/// Save a nonvolatile integer register on the stack using a `MOV` instead of a +/// `PUSH`. +pub struct SaveNonVolatile<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for SaveNonVolatile<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for SaveNonVolatile<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl SaveNonVolatile<'_> { + pub fn reg(&self) -> UnwindReg { + UnwindReg::from(self.ptr.reg()) + } + + pub fn offset(&self) -> u32 { + self.ptr.offset() + } +} + +pub struct SaveXMM128<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for SaveXMM128<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for SaveXMM128<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl SaveXMM128<'_> { + pub fn num(&self) -> u8 { + self.ptr.num() + } + + pub fn offset(&self) -> u32 { + self.ptr.offset() + } +} + +/// Describes the function's epilog +pub struct Epilog<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for Epilog<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for Epilog<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Epilog<'_> { + pub fn flags(&self) -> u8 { + self.ptr.flags() + } + + pub fn size(&self) -> u32 { + self.ptr.size() + } +} + +pub struct Spare<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RuntimeFunctionX64_unwind_info_t>, +} + +impl FromFFI for Spare<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Opcode for Spare<'_> { + fn as_generic(&self) -> &ffi::PE_unwind_x64_Code { + self.ptr.as_ref().unwrap().as_ref() + } +} + +declare_fwd_iterator!( + OpcodesIterator, + Opcodes<'a>, + ffi::PE_unwind_x64_Code, + ffi::PE_RuntimeFunctionX64_unwind_info_t, + ffi::PE_RuntimeFunctionX64_unwind_info_t_it_opcodes +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/export.rs b/vendor/lief/api/rust/crates/lief/src/pe/export.rs new file mode 100644 index 0000000..1ef951c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/export.rs @@ -0,0 +1,315 @@ +//! PE export module + +use lief_ffi as ffi; + +use crate::common::into_optional; +use crate::common::{AsFFI, FromFFI}; +use crate::declare_iterator; +use crate::generic; +use std::pin::Pin; + +use std::marker::PhantomData; + +pub struct Export<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl Export<'_> { + /// Create a new Export object + pub fn new() -> Export<'static> { + Export::from_ffi(ffi::PE_Export::create()) + } + + /// According to the PE specifications this value is reserved and should be set to 0 + pub fn export_flags(&self) -> u32 { + self.ptr.export_flags() + } + + /// The time and date that the export data was created + pub fn timestamp(&self) -> u32 { + self.ptr.timestamp() + } + + /// The major version number (can be user-defined) + pub fn major_version(&self) -> u16 { + self.ptr.major_version() + } + + /// The minor version number (can be user-defined) + pub fn minor_version(&self) -> u16 { + self.ptr.minor_version() + } + + /// The starting number for the exports. Usually this value is set to 1 + pub fn ordinal_base(&self) -> u32 { + self.ptr.ordinal_base() + } + + /// The name of the library exported (e.g. `KERNEL32.dll`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Iterator over the different [`Entry`] exported by this table + pub fn entries(&self) -> ExportEntries<'_> { + ExportEntries::new(self.ptr.entries()) + } + + /// Address of the ASCII DLL's name (RVA) + pub fn name_rva(&self) -> u32 { + self.ptr.name_rva() + } + + /// RVA to the list of exported names + pub fn names_addr_table_rva(&self) -> u32 { + self.ptr.names_addr_table_rva() + } + + /// Number of exports by name + pub fn names_addr_table_cnt(&self) -> u32 { + self.ptr.names_addr_table_cnt() + } + + /// RVA of the export address table + pub fn export_addr_table_rva(&self) -> u32 { + self.ptr.export_addr_table_rva() + } + + /// Number of entries in the export address table + pub fn export_addr_table_cnt(&self) -> u32 { + self.ptr.export_addr_table_cnt() + } + + /// RVA to the list of exported ordinals + pub fn ord_addr_table_rva(&self) -> u32 { + self.ptr.ord_addr_table_rva() + } + + /// Change or set the export flags + pub fn set_export_flags(&mut self, flags: u32) -> &mut Self { + self.ptr.pin_mut().set_export_flags(flags); + self + } + + /// Change or set the timestamp + pub fn set_timestamp(&mut self, timestamp: u32) -> &mut Self { + self.ptr.pin_mut().set_export_flags(timestamp); + self + } + + /// Change or set the major version of the DLL + pub fn set_major_version(&mut self, version: u32) -> &mut Self { + self.ptr.pin_mut().set_major_version(version); + self + } + + /// Change or set the minor version of the DLL + pub fn set_minor_version(&mut self, version: u32) -> &mut Self { + self.ptr.pin_mut().set_minor_version(version); + self + } + + /// Change or set the name of the DLL + pub fn set_name(&mut self, name: &str) -> &mut Self { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().set_name(&__cxx_s); + self + } + + /// Find the export entry with the given name + pub fn entry_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.entry_by_name(&__cxx_s)) + } + + /// Find the export entry with the given ordinal number + pub fn entry_by_ordinal(&self, ordinal: u32) -> Option> { + into_optional(self.ptr.entry_by_ordinal(ordinal)) + } + + /// Find the export entry at the provided RVA + pub fn entry_at_rva(&self, rva: u32) -> Option> { + into_optional(self.ptr.entry_at_rva(rva)) + } + + /// Add the given export and return the newly created and added export + pub fn add_entry(&mut self, entry: &Entry) -> Entry<'_> { + Entry::from_ffi(self.ptr.pin_mut().add_entry(entry.ptr.as_ref().unwrap())) + } + + /// Add a new export entry given its name and its RVA + pub fn add_entry_by_name(&mut self, name: &str, rva: u32) -> Entry<'_> { + cxx::let_cxx_string!(__cxx_s = name); + Entry::from_ffi(self.ptr.pin_mut().add_entry_by_name(&__cxx_s, rva)) + } + + /// Remove the given export entry + pub fn remove_entry(&mut self, entry: Entry) -> bool { + self.ptr.pin_mut().remove_entry(entry.ptr) + } + + /// Remove the export entry with the given RVA + pub fn remove_entry_at(&mut self, rva: u32) -> bool { + self.ptr.pin_mut().remove_entry_at(rva) + } + + /// Remove the export entry with the given RVA + pub fn remove_entry_by_name(&mut self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().remove_entry_by_name(&__cxx_s) + } +} + +impl std::fmt::Debug for Export<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Export") + .field("export_flags", &self.export_flags()) + .field("timestamp", &self.timestamp()) + .field("major_version", &self.major_version()) + .field("minor_version", &self.minor_version()) + .field("ordinal_base", &self.ordinal_base()) + .field("name", &self.name()) + .finish() + } +} + +impl<'a> FromFFI for Export<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Export { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> AsFFI for Export<'a> { + fn as_ffi(&self) -> &ffi::PE_Export { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::PE_Export> { + self.ptr.pin_mut() + } +} + +/// Structure which represents an entry in the export table. +/// +/// It implements the [`generic::Symbol`] trait that exposes [`generic::Symbol::name`] and +/// [`generic::Symbol::value`]. +pub struct Entry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Export>, +} + +impl Entry<'_> { + /// Ordinal value associated with this exported entry. + /// + /// This value is computed as the index of this entry in the address table + /// plus the ordinal base ([`Export::ordinal_base`]) + pub fn ordinal(&self) -> u16 { + self.ptr.ordinal() + } + + /// Address of the current exported function in the DLL. + /// + /// If this entry is **external** to the DLL then it returns 0 + /// and the external address is returned by [`Entry::function_rva`] + pub fn address(&self) -> u32 { + self.ptr.address() + } + + pub fn function_rva(&self) -> u32 { + self.ptr.function_rva() + } + + pub fn is_extern(&self) -> bool { + self.ptr.is_extern() + } + + pub fn is_forwarded(&self) -> bool { + self.ptr.is_forwarded() + } + + /// Demangled representation of the symbol or an empty string if it can't + /// be demangled + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } + + pub fn forward_info(&self) -> Option { + if !self.ptr.is_forwarded() { + return None; + } + Some(ForwardInfo::with_values( + self.ptr.fwd_library().to_string(), + self.ptr.fwd_function().to_string(), + )) + } + + pub fn set_ordinal(&mut self, ordinal: u16) -> &mut Self { + self.ptr.pin_mut().set_ordinal(ordinal); + self + } + + pub fn set_address(&mut self, address: u32) -> &mut Self { + self.ptr.pin_mut().set_address(address); + self + } +} + +impl generic::Symbol for Entry<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for Entry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("ExportEntry") + .field("base", &base) + .field("ordinal", &self.ordinal()) + .field("address", &self.address()) + .finish() + } +} + +impl<'a> FromFFI for Entry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Entry { + ptr, + _owner: PhantomData, + } + } +} + +pub struct ForwardInfo { + pub library: String, + pub function: String, +} + +impl ForwardInfo { + pub fn with_values(library: String, function: String) -> Self { + Self { library, function } + } +} + +declare_iterator!( + ExportEntries, + Entry<'a>, + ffi::PE_ExportEntry, + ffi::PE_Export, + ffi::PE_Export_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/factory.rs b/vendor/lief/api/rust/crates/lief/src/pe/factory.rs new file mode 100644 index 0000000..eb94690 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/factory.rs @@ -0,0 +1,83 @@ +//! PE Factory module for creating PE binaries from scratch + +use lief_ffi as ffi; + +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::pe; + +/// Factory for creating PE binaries from scratch +/// +/// ``` +/// use lief::pe; +/// +/// if let Some(mut factory) = pe::Factory::create(pe::PE_TYPE::PE32_PLUS) { +/// let section = pe::Section::new_with_name(".text"); +/// factory.add_section(§ion); +/// factory.set_entrypoint(0x1000); +/// if let Some(binary) = factory.get() { +/// // use binary +/// } +/// } +/// ``` +pub struct Factory { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Factory { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Factory { + /// Create a new factory for the given PE type (PE32 or PE32+) + pub fn create(pe_type: pe::PE_TYPE) -> Option { + into_optional(ffi::PE_Factory::create(pe_type.into())) + } + + /// Add a section to the PE being built + pub fn add_section(&mut self, section: &pe::Section) { + self.ptr.pin_mut().add_section(section.as_ffi()); + } + + /// Set the target architecture + pub fn set_arch(&mut self, arch: pe::headers::MachineType) { + self.ptr.pin_mut().set_arch(arch.into()); + } + + /// Set the entry point address + pub fn set_entrypoint(&mut self, ep: u64) { + self.ptr.pin_mut().set_entrypoint(ep); + } + + /// Build and return the PE binary + pub fn get(&mut self) -> Option { + into_optional(self.ptr.pin_mut().get()) + } + + /// Whether the factory is creating a 32-bit PE + pub fn is_32bit(&self) -> bool { + self.ptr.is_32bit() + } + + /// Whether the factory is creating a 64-bit PE + pub fn is_64bit(&self) -> bool { + self.ptr.is_64bit() + } + + /// Return the section alignment + pub fn section_align(&self) -> u32 { + self.ptr.section_align() + } + + /// Return the file alignment + pub fn file_align(&self) -> u32 { + self.ptr.file_align() + } +} + +impl std::fmt::Debug for Factory { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Factory").finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/headers.rs b/vendor/lief/api/rust/crates/lief/src/pe/headers.rs new file mode 100644 index 0000000..026bed0 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/headers.rs @@ -0,0 +1,892 @@ +//! This module exposes the different headers that we can find in a PE binary. +//! It includes: +//! - [`DosHeader`] +//! - [`Header`] +//! - [`OptionalHeader`] + +use bitflags::bitflags; +use std::marker::PhantomData; + +use crate::common::FromFFI; +use lief_ffi as ffi; + +/// Structure which represents the DosHeader, the **first** structure presents at the beginning of +/// a PE file. +/// +/// Most of the attributes of this structures are no longer relevant +pub struct DosHeader<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FromFFI for DosHeader<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> DosHeader<'a> { + /// Magic bytes identifying a DOS/PE binary + pub fn magic(&self) -> u16 { + self.ptr.magic() + } + + pub fn used_bytes_in_last_page(&self) -> u16 { + self.ptr.used_bytes_in_last_page() + } + + pub fn file_size_in_pages(&self) -> u16 { + self.ptr.file_size_in_pages() + } + + pub fn numberof_relocation(&self) -> u16 { + self.ptr.numberof_relocation() + } + + pub fn header_size_in_paragraphs(&self) -> u16 { + self.ptr.header_size_in_paragraphs() + } + + pub fn minimum_extra_paragraphs(&self) -> u16 { + self.ptr.minimum_extra_paragraphs() + } + + pub fn maximum_extra_paragraphs(&self) -> u16 { + self.ptr.maximum_extra_paragraphs() + } + + pub fn initial_relative_ss(&self) -> u16 { + self.ptr.initial_relative_ss() + } + + pub fn initial_sp(&self) -> u16 { + self.ptr.initial_sp() + } + + pub fn checksum(&self) -> u16 { + self.ptr.checksum() + } + + pub fn initial_ip(&self) -> u16 { + self.ptr.initial_ip() + } + + pub fn initial_relative_cs(&self) -> u16 { + self.ptr.initial_relative_cs() + } + + pub fn addressof_relocation_table(&self) -> u16 { + self.ptr.addressof_relocation_table() + } + + pub fn overlay_number(&self) -> u16 { + self.ptr.overlay_number() + } + + pub fn reserved(&self) -> Vec { + Vec::from_iter(self.ptr.reserved().iter().map(|x| *x as u16)) + } + + pub fn oem_id(&self) -> u16 { + self.ptr.oem_id() + } + + pub fn oem_info(&self) -> u16 { + self.ptr.oem_info() + } + + pub fn reserved2(&self) -> Vec { + Vec::from_iter(self.ptr.reserved2().iter().map(|x| *x as u16)) + } + + /// Return the offset to the [`Header`] structure. + pub fn addressof_new_exeheader(&self) -> u32 { + self.ptr.addressof_new_exeheader() + } +} + +impl std::fmt::Debug for DosHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DosHeader") + .field("magic", &self.magic()) + .field("used_bytes_in_last_page", &self.used_bytes_in_last_page()) + .field("file_size_in_pages", &self.file_size_in_pages()) + .field("numberof_relocation", &self.numberof_relocation()) + .field( + "header_size_in_paragraphs", + &self.header_size_in_paragraphs(), + ) + .field("minimum_extra_paragraphs", &self.minimum_extra_paragraphs()) + .field("maximum_extra_paragraphs", &self.maximum_extra_paragraphs()) + .field("initial_relative_ss", &self.initial_relative_ss()) + .field("initial_sp", &self.initial_sp()) + .field("checksum", &self.checksum()) + .field("initial_ip", &self.initial_ip()) + .field("initial_relative_cs", &self.initial_relative_cs()) + .field( + "addressof_relocation_table", + &self.addressof_relocation_table(), + ) + .field("overlay_number", &self.overlay_number()) + .field("reserved", &self.reserved()) + .field("oem_info", &self.oem_info()) + .field("oem_id", &self.oem_id()) + .field("reserved2", &self.reserved2()) + .field("addressof_new_exeheader", &self.addressof_new_exeheader()) + .finish() + } +} + +/// Structure that represents the PE header (which follows the [`DosHeader`]) +pub struct Header<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FromFFI for Header<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum MachineType { + /// Alpha AXP, 32-bit address space + ALPHA, + /// Alpha AXP, 64-bit address space + ALPHA64, + /// Matsushita AM33 + AM33, + /// AMD x64 + AMD64, + /// ARM little endian + ARM, + /// ARMv7 Thumb mode only + ARMNT, + /// ARMv8 in 64-bits mode + ARM64, + /// EFI byte code + EBC, + /// Intel 386 or later + I386, + /// Intel Itanium processor family + IA64, + /// LoongArch 32-bit processor family + LOONGARCH32, + /// LoongArch 64-bit processor family + LOONGARCH64, + /// Mitsubishi M32R little endian + M32R, + /// MIPS16 + MIPS16, + /// MIPS with FPU + MIPSFPU, + /// MIPS16 with FPU + MIPSFPU16, + /// Power PC little endian + POWERPC, + /// Power PC with floating point + POWERPCFP, + /// Power PC big endian + POWERPCBE, + /// MIPS with little endian + R4000, + /// RISC-V 32-bit address space + RISCV32, + /// RISC-V 64-bit address space + RISCV64, + /// RISC-V 128-bit address space + RISCV128, + /// Hitachi SH3 + SH3, + /// Hitachi SH3 DSP + SH3DSP, + /// Hitachi SH4 + SH4, + /// Hitachi SH5 + SH5, + /// ARM or Thumb + THUMB, + /// MIPS little-endian WCE v2 + WCEMIPSV2, + ARM64EC, + ARM64X, + CHPE_X86, + UNKNOWN(u32), +} + +impl From for MachineType { + fn from(value: u32) -> Self { + match value { + 0x00000184 => MachineType::ALPHA, + 0x00000284 => MachineType::ALPHA64, + 0x000001d3 => MachineType::AM33, + 0x00008664 => MachineType::AMD64, + 0x000001c0 => MachineType::ARM, + 0x000001c4 => MachineType::ARMNT, + 0x0000aa64 => MachineType::ARM64, + 0x00000ebc => MachineType::EBC, + 0x0000014c => MachineType::I386, + 0x00000200 => MachineType::IA64, + 0x00006232 => MachineType::LOONGARCH32, + 0x00006264 => MachineType::LOONGARCH64, + 0x00009041 => MachineType::M32R, + 0x00000266 => MachineType::MIPS16, + 0x00000366 => MachineType::MIPSFPU, + 0x00000466 => MachineType::MIPSFPU16, + 0x000001f0 => MachineType::POWERPC, + 0x000001f1 => MachineType::POWERPCFP, + 0x000001f2 => MachineType::POWERPCBE, + 0x00000166 => MachineType::R4000, + 0x00005032 => MachineType::RISCV32, + 0x00005064 => MachineType::RISCV64, + 0x00005128 => MachineType::RISCV128, + 0x000001a2 => MachineType::SH3, + 0x000001a3 => MachineType::SH3DSP, + 0x000001a6 => MachineType::SH4, + 0x000001a8 => MachineType::SH5, + 0x000001c2 => MachineType::THUMB, + 0x00000169 => MachineType::WCEMIPSV2, + 0x0000a641 => MachineType::ARM64EC, + 0x0000a64e => MachineType::ARM64X, + 0x00003a64 => MachineType::CHPE_X86, + _ => MachineType::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: MachineType) -> u32 { + match value { + MachineType::ALPHA => 0x184, + MachineType::ALPHA64 => 0x284, + MachineType::AM33 => 0x000001d3, + MachineType::AMD64 => 0x00008664, + MachineType::ARM => 0x000001c0, + MachineType::ARMNT => 0x000001c4, + MachineType::ARM64 => 0x0000aa64, + MachineType::EBC => 0x00000ebc, + MachineType::I386 => 0x0000014c, + MachineType::IA64 => 0x00000200, + MachineType::LOONGARCH32 => 0x6232, + MachineType::LOONGARCH64 => 0x6264, + MachineType::M32R => 0x00009041, + MachineType::MIPS16 => 0x00000266, + MachineType::MIPSFPU => 0x00000366, + MachineType::MIPSFPU16 => 0x00000466, + MachineType::POWERPC => 0x000001f0, + MachineType::POWERPCFP => 0x000001f1, + MachineType::POWERPCBE => 0x000001f2, + MachineType::R4000 => 0x00000166, + MachineType::RISCV32 => 0x00005032, + MachineType::RISCV64 => 0x00005064, + MachineType::RISCV128 => 0x00005128, + MachineType::SH3 => 0x000001a2, + MachineType::SH3DSP => 0x000001a3, + MachineType::SH4 => 0x000001a6, + MachineType::SH5 => 0x000001a8, + MachineType::THUMB => 0x000001c2, + MachineType::WCEMIPSV2 => 0x00000169, + MachineType::ARM64EC => 0x0000a641, + MachineType::ARM64X => 0x0000a64e, + MachineType::CHPE_X86 => 0x00003a64, + MachineType::UNKNOWN(_) => 0, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Characteristics: u32 { + const NONE = 0x0; + + /// The file does not contain base relocations and must be loaded at its preferred base. + /// If this cannot be done, the loader will error. + const RELOCS_STRIPPED = 0x1; + + /// File is executable (i.e. no unresolved externel references). + const EXECUTABLE_IMAGE = 0x2; + + /// COFF line numbers have been stripped. This is deprecated and should be 0 + const LINE_NUMS_STRIPPED = 0x4; + + /// COFF symbol table entries for local symbols have been removed. + /// This is deprecated and should be 0. + const LOCAL_SYMS_STRIPPED = 0x8; + + /// Aggressively trim working set. This is deprecated and must be 0. + const AGGRESSIVE_WS_TRIM = 0x10; + + /// App can handle >2gb addresses + const LARGE_ADDRESS_AWARE = 0x20; + + /// Little endian: the LSB precedes the MSB in memory. This is deprecated and should be 0. + const BYTES_REVERSED_LO = 0x80; + + /// Machine is based on a 32bit word architecture. + const NEED_32BIT_MACHINE = 0x100; + + /// Debugging info has been removed. + const DEBUG_STRIPPED = 0x200; + + /// If the image is on removable media, fully load it and copy it to swap. + const REMOVABLE_RUN_FROM_SWAP = 0x400; + + /// If the image is on network media, fully load it and copy it to swap. + const NET_RUN_FROM_SWAP = 0x800; + + /// The image file is a system file, not a user program. + const SYSTEM = 0x1000; + + /// The image file is a DLL. + const DLL = 0x2000; + + /// This file should only be run on a uniprocessor machine. + const UP_SYSTEM_ONLY = 0x4000; + + /// Big endian: the MSB precedes the LSB in memory. This is deprecated + const BYTES_REVERSED_HI = 0x8000; + } +} + +impl std::fmt::Display for Characteristics { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl From for Characteristics { + fn from(value: u32) -> Self { + Characteristics::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: Characteristics) -> Self { + value.bits() + } +} + +impl Header<'_> { + /// PE signature (should be `PE\0\0`) + pub fn signature(&self) -> Vec { + Vec::from(self.ptr.signature().as_slice()) + .iter() + .map(|&v: &u64| v as u8) + .collect() + } + + /// The targeted machine architecture like ARM, x86, AMD64, ... + pub fn machine(&self) -> MachineType { + MachineType::from(self.ptr.machine()) + } + + /// The number of sections in the binary. + pub fn nb_sections(&self) -> u16 { + self.ptr.numberof_sections() + } + + /// The low 32 bits of the number of seconds since January 1, 1970. + /// It **indicates** when the file was created. + pub fn time_date_stamp(&self) -> u32 { + self.ptr.time_date_stamp() + } + + /// The offset of the **COFF** symbol table. + /// This value should be zero for an image because COFF debugging information is deprecated on + /// in PE binary + pub fn pointerto_symbol_table(&self) -> u32 { + self.ptr.pointerto_symbol_table() + } + + /// The number of entries in the symbol table. This data can be used to locate the string table + /// which immediately follows the symbol table. + /// + /// This value should be zero for an image because COFF debugging information is deprecated in + /// PE binary + pub fn numberof_symbols(&self) -> u32 { + self.ptr.numberof_symbols() + } + + /// Size of the OptionalHeader **AND** the data directories which follows this header. + /// + /// This value is equivalent to: + /// `sizeof(pe_optional_header) + NB_DATA_DIR * sizeof(data_directory)` + /// + /// This size **should** be either: + /// * 0xE0 (224) for a PE32 (32 bits) + /// * 0xF0 (240) for a PE32+ (64 bits) + pub fn sizeof_optional_header(&self) -> u16 { + self.ptr.sizeof_optional_header() + } + + /// Characteristics of the binary like whether it is a DLL or an executable + pub fn characteristics(&self) -> Characteristics { + Characteristics::from(self.ptr.characteristics()) + } + + pub fn set_machine(&mut self, machine: MachineType) { + self.ptr.pin_mut().set_machine(u32::from(machine)); + } + + pub fn set_numberof_sections(&mut self, value: u16) { + self.ptr.pin_mut().set_numberof_sections(value); + } + + pub fn set_time_date_stamp(&mut self, value: u32) { + self.ptr.pin_mut().set_time_date_stamp(value); + } + + pub fn set_pointerto_symbol_table(&mut self, value: u32) { + self.ptr.pin_mut().set_pointerto_symbol_table(value); + } + + pub fn set_numberof_symbols(&mut self, value: u32) { + self.ptr.pin_mut().set_numberof_symbols(value); + } + + pub fn set_sizeof_optional_header(&mut self, value: u16) { + self.ptr.pin_mut().set_sizeof_optional_header(value); + } + + pub fn set_characteristics(&mut self, characteristics: Characteristics) { + self.ptr + .pin_mut() + .set_characteristics(characteristics.bits()); + } + + pub fn add_characteristic(&mut self, characteristics: Characteristics) { + self.ptr + .pin_mut() + .add_characteristic(characteristics.bits()); + } + + pub fn remove_characteristic(&mut self, characteristics: Characteristics) { + self.ptr + .pin_mut() + .remove_characteristic(characteristics.bits()); + } +} + +impl std::fmt::Debug for Header<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Header") + .field("machine", &self.machine()) + .field("nb_sections", &self.nb_sections()) + .field("time_date_stamp", &self.time_date_stamp()) + .field("pointerto_symbol_table", &self.pointerto_symbol_table()) + .field("numberof_symbols", &self.numberof_symbols()) + .field("sizeof_optional_header", &self.sizeof_optional_header()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +/// Structure which represents the PE OptionalHeader (after [`Header`]). +/// +/// Note that the term *optional* comes from the COFF specifications but this header is +/// **mandatory** for a PE binary. +pub struct OptionalHeader<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl FromFFI for OptionalHeader<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct DllCharacteristics: u32 { + /// ASLR with 64 bit address space. + const HIGH_ENTROPY_VA = 0x20; + + /// DLL can be relocated at load time. + const DYNAMIC_BASE = 0x40; + + /// Code integrity checks are enforced. + const FORCE_INTEGRITY = 0x80; + + /// Image is NX compatible. + const NX_COMPAT = 0x100; + + /// Isolation aware, but do not isolate the image. + const NO_ISOLATION = 0x200; + + /// Does not use structured exception handling (SEH). + /// No SEH handler may be called in this image. + const NO_SEH = 0x400; + + /// Do not bind the image. + const NO_BIND = 0x800; + + /// Image should execute in an AppContainer. + const APPCONTAINER = 0x1000; + + /// A WDM driver. + const WDM_DRIVER = 0x2000; + + /// Image supports Control Flow Guard. + const GUARD_CF = 0x4000; + + /// Terminal Server aware. + const TERMINAL_SERVER_AWARE = 0x8000; + } +} + +impl From for DllCharacteristics { + fn from(value: u32) -> Self { + DllCharacteristics::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: DllCharacteristics) -> Self { + value.bits() + } +} +impl std::fmt::Display for DllCharacteristics { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Subsystem { + /// Device drivers and native Windows processes + NATIVE, + + /// The Windows GUI subsystem. + WINDOWS_GUI, + + /// The Windows character subsystem. + WINDOWS_CUI, + + /// The OS/2 character subsytem. + OS2_CUI, + + /// The POSIX character subsystem. + POSIX_CUI, + + /// Native Windows 9x driver. + NATIVE_WINDOWS, + + /// Windows CE. + WINDOWS_CE_GUI, + + /// An EFI application. + EFI_APPLICATION, + + /// An EFI driver with boot services. + EFI_BOOT_SERVICE_DRIVER, + + /// An EFI driver with run-time services. + EFI_RUNTIME_DRIVER, + + /// An EFI ROM image. + EFI_ROM, + + /// XBOX + XBOX, + + /// A BCD application. + WINDOWS_BOOT_APPLICATION, + + /// Security Metadata Containers + XBOX_CODE_CATALOG, + + /// An unknown subsystem. + UNKNOWN(u64), +} + +impl From for Subsystem { + fn from(value: u64) -> Self { + match value { + 0x00000001 => Subsystem::NATIVE, + 0x00000002 => Subsystem::WINDOWS_GUI, + 0x00000003 => Subsystem::WINDOWS_CUI, + 0x00000005 => Subsystem::OS2_CUI, + 0x00000007 => Subsystem::POSIX_CUI, + 0x00000008 => Subsystem::NATIVE_WINDOWS, + 0x00000009 => Subsystem::WINDOWS_CE_GUI, + 0x0000000a => Subsystem::EFI_APPLICATION, + 0x0000000b => Subsystem::EFI_BOOT_SERVICE_DRIVER, + 0x0000000c => Subsystem::EFI_RUNTIME_DRIVER, + 0x0000000d => Subsystem::EFI_ROM, + 0x0000000e => Subsystem::XBOX, + 0x00000010 => Subsystem::WINDOWS_BOOT_APPLICATION, + 0x00000011 => Subsystem::XBOX_CODE_CATALOG, + _ => Subsystem::UNKNOWN(value), + } + } +} +impl From for u64 { + fn from(value: Subsystem) -> u64 { + match value { + Subsystem::NATIVE => 0x00000001, + Subsystem::WINDOWS_GUI => 0x00000002, + Subsystem::WINDOWS_CUI => 0x00000003, + Subsystem::OS2_CUI => 0x00000005, + Subsystem::POSIX_CUI => 0x00000007, + Subsystem::NATIVE_WINDOWS => 0x00000008, + Subsystem::WINDOWS_CE_GUI => 0x00000009, + Subsystem::EFI_APPLICATION => 0x0000000a, + Subsystem::EFI_BOOT_SERVICE_DRIVER => 0x0000000b, + Subsystem::EFI_RUNTIME_DRIVER => 0x0000000c, + Subsystem::EFI_ROM => 0x0000000d, + Subsystem::XBOX => 0x0000000e, + Subsystem::WINDOWS_BOOT_APPLICATION => 0x00000010, + Subsystem::XBOX_CODE_CATALOG => 0x00000011, + Subsystem::UNKNOWN(_) => 0, + } + } +} + +impl OptionalHeader<'_> { + /// Magic number identifying PE32 (0x10b) or PE32+ (0x20b) + pub fn magic(&self) -> u32 { + self.ptr.magic() as u32 + } + + /// The linker major version + pub fn major_linker_version(&self) -> u8 { + self.ptr.major_linker_version() + } + + /// The linker minor version + pub fn minor_linker_version(&self) -> u8 { + self.ptr.minor_linker_version() + } + + /// The size of the code `.text` section or the sum of + /// all the sections that contain code (i.e. sections with `CNT_CODE` flag) + pub fn sizeof_code(&self) -> u32 { + self.ptr.sizeof_code() + } + + /// The size of the initialized data which are usually located in the `.data` section. + /// If the initialized data are split across multiple sections, it is the sum of the sections. + pub fn sizeof_initialized_data(&self) -> u32 { + self.ptr.sizeof_initialized_data() + } + + /// The size of the uninitialized data which are usually located in the `.bss` section. + /// If the uninitialized data are split across multiple sections, it is the sum of the sections. + pub fn sizeof_uninitialized_data(&self) -> u32 { + self.ptr.sizeof_uninitialized_data() + } + + /// The address of the entry point relative to the image base when the executable file is + /// loaded into memory. For program images, this is the starting address. For device + /// drivers, this is the address of the initialization function. + /// + /// An entry point is optional for DLLs. When no entry point is present, this field must be zero. + pub fn addressof_entrypoint(&self) -> u32 { + self.ptr.addressof_entrypoint() + } + + /// Address relative to the imagebase where the binary's code starts. + pub fn baseof_code(&self) -> u32 { + self.ptr.baseof_code() + } + + /// Address relative to the imagebase where the binary's data starts. + /// + ///
This value is not present for PE64 files
+ pub fn baseof_data(&self) -> u32 { + self.ptr.baseof_data() + } + + /// The preferred base address when mapping the binary in memory + pub fn imagebase(&self) -> u64 { + self.ptr.imagebase() + } + + /// The alignment (in bytes) of sections when they are loaded into memory. + /// + /// It must be greater than or equal to file_alignment and + /// the default is the page size for the architecture. + pub fn section_alignment(&self) -> u32 { + self.ptr.section_alignment() + } + + /// The section's file alignment. This value must be a power of 2 between 512 and 64K. + /// The default value is usually 512 + pub fn file_alignment(&self) -> u32 { + self.ptr.file_alignment() + } + + /// The **major** version number of the required operating system + pub fn major_operating_system_version(&self) -> u16 { + self.ptr.major_operating_system_version() + } + + /// The **minor** version number of the required operating system + pub fn minor_operating_system_version(&self) -> u16 { + self.ptr.minor_operating_system_version() + } + + /// The major version number of the image + pub fn major_image_version(&self) -> u16 { + self.ptr.major_image_version() + } + + /// The minor version number of the image + pub fn minor_image_version(&self) -> u16 { + self.ptr.minor_image_version() + } + + /// The major version number of the subsystem + pub fn major_subsystem_version(&self) -> u16 { + self.ptr.major_subsystem_version() + } + + /// The minor version number of the subsystem + pub fn minor_subsystem_version(&self) -> u16 { + self.ptr.minor_subsystem_version() + } + + /// According to the official PE specifications, this value + /// is reserved and **should** be 0. + pub fn win32_version_value(&self) -> u32 { + self.ptr.win32_version_value() + } + + /// The size (in bytes) of the image, including all headers, as the image is loaded in memory. + /// + /// It must be a multiple of section_alignment and should match [`crate::pe::Binary::virtual_size`] + pub fn sizeof_image(&self) -> u32 { + self.ptr.sizeof_image() + } + + /// Size of the DosHeader + PE Header + Section headers rounded up to a multiple of the file_alignment + pub fn sizeof_headers(&self) -> u32 { + self.ptr.sizeof_headers() + } + + /// The image file checksum. The algorithm for computing the checksum is incorporated into `IMAGHELP.DLL`. + /// + /// The following are checked for validation at load time all **drivers**, any **DLL loaded at boot** + /// time, and any **DLL** that is loaded into a **critical** Windows process. + pub fn checksum(&self) -> u32 { + self.ptr.checksum() + } + + /// Target subsystem like Driver, XBox, Windows GUI, ... + pub fn subsystem(&self) -> Subsystem { + Subsystem::from(self.ptr.subsystem()) + } + + /// Some characteristics of the underlying binary like the support of the PIE. + /// The prefix ``dll`` comes from the official PE specifications but these characteristics + /// are also used for **executables** + pub fn dll_characteristics(&self) -> DllCharacteristics { + DllCharacteristics::from(self.ptr.dll_characteristics()) + } + + /// Size of the stack to reserve when loading the PE binary + /// + /// Only [`OptionalHeader::sizeof_stack_commit`] is committed, the rest + /// available one page at a time until the reserve size is reached. + pub fn sizeof_stack_reserve(&self) -> u64 { + self.ptr.sizeof_stack_reserve() + } + + /// Size of the stack to commit + pub fn sizeof_stack_commit(&self) -> u64 { + self.ptr.sizeof_stack_commit() + } + + /// Size of the heap to reserve when loading the PE binary + pub fn sizeof_heap_reserve(&self) -> u64 { + self.ptr.sizeof_heap_reserve() + } + + /// Size of the stack to commit + pub fn sizeof_heap_commit(&self) -> u64 { + self.ptr.sizeof_heap_commit() + } + + /// According to the PE specifications, this value is *reserved* and **should** be 0. + pub fn loader_flags(&self) -> u32 { + self.ptr.loader_flags() + } + + /// The number of DataDirectory that follow this header. + pub fn numberof_rva_and_size(&self) -> u32 { + self.ptr.numberof_rva_and_size() + } + + pub fn set_addressof_entrypoint(&mut self, value: u32) { + self.ptr.pin_mut().set_addressof_entrypoint(value) + } + + pub fn set_imagebase(&mut self, value: u64) { + self.ptr.pin_mut().set_imagebase(value) + } + + /// Add a DLL characteristic + pub fn add_dll_characteristic(&mut self, c: DllCharacteristics) { + self.ptr.pin_mut().add_dll_characteristic(c.bits()); + } + + /// Remove a DLL characteristic + pub fn remove_dll_characteristic(&mut self, c: DllCharacteristics) { + self.ptr.pin_mut().remove_dll_characteristic(c.bits()); + } +} + +impl std::fmt::Debug for OptionalHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("OptionalHeader") + .field("major_linker_version", &self.major_linker_version()) + .field("minor_linker_version", &self.minor_linker_version()) + .field("sizeof_code", &self.sizeof_code()) + .field("sizeof_initialized_data", &self.sizeof_initialized_data()) + .field( + "sizeof_uninitialized_data", + &self.sizeof_uninitialized_data(), + ) + .field("addressof_entrypoint", &self.addressof_entrypoint()) + .field("baseof_code", &self.baseof_code()) + .field("baseof_data", &self.baseof_data()) + .field("imagebase", &self.imagebase()) + .field("section_alignment", &self.section_alignment()) + .field("file_alignment", &self.file_alignment()) + .field( + "major_operating_system_version", + &self.major_operating_system_version(), + ) + .field( + "minor_operating_system_version", + &self.minor_operating_system_version(), + ) + .field("major_image_version", &self.major_image_version()) + .field("minor_image_version", &self.minor_image_version()) + .field("major_subsystem_version", &self.major_subsystem_version()) + .field("minor_subsystem_version", &self.minor_subsystem_version()) + .field("win32_version_value", &self.win32_version_value()) + .field("sizeof_image", &self.sizeof_image()) + .field("sizeof_headers", &self.sizeof_headers()) + .field("checksum", &self.checksum()) + .field("subsystem", &self.subsystem()) + .field("dll_characteristics", &self.dll_characteristics()) + .field("sizeof_stack_reserve", &self.sizeof_stack_reserve()) + .field("sizeof_stack_commit", &self.sizeof_stack_commit()) + .field("sizeof_heap_reserve", &self.sizeof_heap_reserve()) + .field("sizeof_heap_commit", &self.sizeof_heap_commit()) + .field("loader_flags", &self.loader_flags()) + .field("numberof_rva_and_size", &self.numberof_rva_and_size()) + .finish() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/import.rs b/vendor/lief/api/rust/crates/lief/src/pe/import.rs new file mode 100644 index 0000000..aa03b06 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/import.rs @@ -0,0 +1,260 @@ +//! This module represents PE's Imports + +use std::marker::PhantomData; +use std::pin::Pin; + +use crate::common::into_optional; +use crate::declare_iterator; +use crate::pe::DataDirectory; +use crate::{common::FromFFI, generic}; +use lief_ffi as ffi; + +pub struct Import<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl std::fmt::Debug for Import<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Import") + .field("name", &self.name()) + .field("forwarder_chain", &self.forwarder_chain()) + .field("timedatestamp", &self.timedatestamp()) + .field("import_address_table_rva", &self.import_address_table_rva()) + .field("import_lookup_table_rva", &self.import_lookup_table_rva()) + .field("directory", &self.directory()) + .field("iat_directory", &self.iat_directory()) + .finish() + } +} + +impl<'a> FromFFI for Import<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Import { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> crate::common::AsFFI for Import<'a> { + fn as_ffi(&self) -> &ffi::PE_Import { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> Pin<&mut ffi::PE_Import> { + self.ptr.pin_mut() + } +} + +impl Import<'_> { + /// Iterator over the [`ImportEntry`] + pub fn entries(&self) -> ImportEntries<'_> { + ImportEntries::new(self.ptr.entries()) + } + + /// The index of the first forwarder reference + pub fn forwarder_chain(&self) -> u32 { + self.ptr.forwarder_chain() + } + + /// The stamp that is set to zero until the image is bound. + /// After the image is bound, this field is set to the time/data stamp of the DLL + pub fn timedatestamp(&self) -> u32 { + self.ptr.timedatestamp() + } + + /// The RVA of the import address table (`IAT`). The content of this table is + /// **identical** to the content of the Import Lookup Table (`ILT`) until the image is bound. + /// + ///
This address could change when re-building the binary
+ pub fn import_address_table_rva(&self) -> u32 { + self.ptr.import_address_table_rva() + } + + /// Return the relative virtual address of the import lookup table + /// + ///
This address could change when re-building the binary
+ pub fn import_lookup_table_rva(&self) -> u32 { + self.ptr.import_lookup_table_rva() + } + + /// Return the library's name (e.g. `kernel32.dll`) + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Return the [`DataDirectory`] associated with this import. + pub fn directory(&self) -> Option> { + into_optional(self.ptr.directory()) + } + + /// Return the [`DataDirectory`] associated with the IAT (import address table). + pub fn iat_directory(&self) -> Option> { + into_optional(self.ptr.iat_directory()) + } + + /// Try to find an [`ImportEntry`] by its name + pub fn entry_by_name(&self, name: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = name); + into_optional(self.ptr.entry_by_name(&__cxx_s)) + } + + /// The original name rva + pub fn name_rva(&self) -> u32 { + self.ptr.name_rva() + } + + /// Remove the import entry with the given name. + /// + /// Return true if the deletion succeed, false otherwise + pub fn remove_entry_by_name(&mut self, name: &str) -> bool { + cxx::let_cxx_string!(__cxx_s = name); + self.ptr.pin_mut().remove_entry_by_name(&__cxx_s) + } + + /// Remove the import entry with the given ordinal number + /// + /// Return true if the deletion succeed, false otherwise + pub fn remove_entry_by_ordinal(&mut self, ord: u32) -> bool { + self.ptr.pin_mut().remove_entry_by_ordinal(ord) + } + + /// Add a new entry with the given name + pub fn add_entry_by_name<'a>(&'a mut self, name: &str) -> ImportEntry<'a> { + cxx::let_cxx_string!(__cxx_s = name); + ImportEntry::from_ffi(self.ptr.pin_mut().add_entry_by_name(&__cxx_s)) + } + + /// Set the name of the import + pub fn set_name(&mut self, name: &str) { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + self.ptr.pin_mut().set_name(&__cxx_s); + } +} + +/// Structure that represents an entry (i.e. an import) in the regular import table. +/// +/// It implements the [`generic::Symbol`] trait that exposes [`generic::Symbol::name`] and +/// [`generic::Symbol::value`]. +pub struct ImportEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Import>, +} + +impl ImportEntry<'_> { + /// `True` if it is an import by ordinal + pub fn is_ordinal(&self) -> bool { + self.ptr.is_ordinal() + } + + /// The ordinal value + pub fn ordinal(&self) -> u16 { + self.ptr.ordinal() + } + pub fn hint_name_rva(&self) -> u64 { + self.ptr.hint_name_rva() + } + + /// Index into the export table that is used to speed-up the resolution + pub fn hint(&self) -> u16 { + self.ptr.hint() + } + + /// Value of the current entry in the Import Address Table. + /// It should match the lookup table value + pub fn iat_value(&self) -> u64 { + self.ptr.iat_value() + } + + /// Original value in the import lookup table. + /// + /// This value should match the [`ImportEntry::iat_value`]. + pub fn ilt_value(&self) -> u64 { + self.ptr.ilt_value() + } + + /// Set the value of the current entry in the Import Address Table. + pub fn set_iat_value(&mut self, value: u64) -> &mut Self { + self.ptr.pin_mut().set_iat_value(value); + self + } + + /// Set the original value in the Import Lookup Table. + pub fn set_ilt_value(&mut self, value: u64) -> &mut Self { + self.ptr.pin_mut().set_ilt_value(value); + self + } + + /// Raw value + pub fn data(&self) -> u64 { + self.ptr.data() + } + + /// **Original** address of the entry in the Import Address Table + pub fn iat_address(&self) -> u64 { + self.ptr.iat_address() + } + + /// Demangled representation of the symbol or an empty string if it can't + /// be demangled + pub fn demangled_name(&self) -> String { + self.ptr.demangled_name().to_string() + } +} + +impl<'a> FromFFI for ImportEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + ImportEntry { + ptr, + _owner: PhantomData, + } + } +} + +impl generic::Symbol for ImportEntry<'_> { + fn as_generic(&self) -> &ffi::AbstractSymbol { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_pin_mut_generic(&mut self) -> Pin<&mut ffi::AbstractSymbol> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSymbol + as *mut ffi::AbstractSymbol) + .as_mut() + .unwrap() + }) + } + } +} + +impl std::fmt::Debug for ImportEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Symbol; + f.debug_struct("ImportEntry") + .field("base", &base) + .field("ordinal", &self.ordinal()) + .field("hint_name_rva", &self.hint_name_rva()) + .field("hint", &self.hint()) + .field("iat_value", &self.iat_value()) + .field("data", &self.data()) + .field("iat_address", &self.iat_address()) + .finish() + } +} + +declare_iterator!( + ImportEntries, + ImportEntry<'a>, + ffi::PE_ImportEntry, + ffi::PE_Import, + ffi::PE_Import_it_entries +); +declare_iterator!( + Imports, + Import<'a>, + ffi::PE_Import, + ffi::PE_Binary, + ffi::PE_Binary_it_imports +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/load_configuration.rs b/vendor/lief/api/rust/crates/lief/src/pe/load_configuration.rs new file mode 100644 index 0000000..38571ab --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/load_configuration.rs @@ -0,0 +1,1048 @@ +use super::chpe_metadata_arm64; +use super::chpe_metadata_x86; +use super::dynamic_relocation::DynamicRelocation; +use super::enclave_configuration::EnclaveConfiguration; +use super::volatile_metadata::VolatileMetadata; +use crate::common::{FromFFI, into_optional}; +use crate::pe::code_integrity::CodeIntegrity; +use crate::{declare_iterator, to_conv_opt, to_opt}; +use bitflags::bitflags; +use lief_ffi as ffi; +use std::marker::PhantomData; + +/// This structure represents the load configuration data associated with the +/// `IMAGE_LOAD_CONFIG_DIRECTORY`. +/// +/// This structure is frequently updated by Microsoft to add new metadata. +/// +/// Reference: +pub struct LoadConfiguration<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl LoadConfiguration<'_> { + /// Characteristics of the structure which is defined by its size + pub fn characteristics(&self) -> u32 { + self.ptr.characteristics() + } + + /// Size of the current structure + pub fn size(&self) -> u32 { + self.ptr.size() + } + + /// The date and time stamp value + pub fn timedatestamp(&self) -> u32 { + self.ptr.timedatestamp() + } + + /// Major version + pub fn major_version(&self) -> u16 { + self.ptr.major_version() + } + + /// Minor version + pub fn minor_version(&self) -> u16 { + self.ptr.minor_version() + } + + /// The global flags that control system behavior. For more information, see `Gflags.exe`. + pub fn global_flags_clear(&self) -> u32 { + self.ptr.global_flags_clear() + } + + /// The global flags that control system behavior. For more information, see `Gflags.exe`. + pub fn global_flags_set(&self) -> u32 { + self.ptr.global_flags_set() + } + + /// The critical section default time-out value. + pub fn critical_section_default_timeout(&self) -> u32 { + self.ptr.critical_section_default_timeout() + } + + /// The size of the minimum block that must be freed before it is freed (de-committed), in bytes. + /// This value is advisory. + pub fn decommit_free_block_threshold(&self) -> u64 { + self.ptr.decommit_free_block_threshold() + } + + /// The size of the minimum total memory that must be freed in the process heap before it is + /// freed (de-committed), in bytes. This value is advisory. + pub fn decommit_total_free_threshold(&self) -> u64 { + self.ptr.decommit_total_free_threshold() + } + + /// The VA of a list of addresses where the `LOCK` prefix is used. These will be replaced by + /// `NOP` on single-processor systems. This member is available only for x86. + pub fn lock_prefix_table(&self) -> u64 { + self.ptr.lock_prefix_table() + } + + /// The maximum allocation size, in bytes. This member is obsolete and is used only for + /// debugging purposes. + pub fn maximum_allocation_size(&self) -> u64 { + self.ptr.maximum_allocation_size() + } + + /// The maximum block size that can be allocated from heap segments, in bytes. + pub fn virtual_memory_threshold(&self) -> u64 { + self.ptr.virtual_memory_threshold() + } + + /// The process affinity mask. For more information, see `GetProcessAffinityMask`. This member + /// is available only for `.exe` files. + pub fn process_affinity_mask(&self) -> u64 { + self.ptr.process_affinity_mask() + } + + /// The process heap flags. For more information, see `HeapCreate`. + pub fn process_heap_flags(&self) -> u32 { + self.ptr.process_heap_flags() + } + + /// The service pack version. + pub fn csd_version(&self) -> u16 { + self.ptr.csd_version() + } + + /// See: [`LoadConfiguration::dependent_load_flags`] + pub fn reserved1(&self) -> u16 { + self.ptr.reserved1() + } + + /// Alias for [`LoadConfiguration::reserved1`]. + /// + /// The default load flags used when the operating system resolves the + /// statically linked imports of a module. For more information, see + /// `LoadLibraryEx`. + pub fn dependent_load_flags(&self) -> u16 { + self.ptr.dependent_load_flags() + } + + /// Reserved for use by the system. + pub fn editlist(&self) -> u64 { + self.ptr.editlist() + } + + /// A pointer to a cookie that is used by Visual C++ or GS implementation. + pub fn security_cookie(&self) -> u64 { + self.ptr.security_cookie() + } + + /// The VA of the sorted table of RVAs of each valid, unique handler in the image. This member + /// is available only for x86. + pub fn se_handler_table(&self) -> Option { + to_opt!(&lief_ffi::PE_LoadConfiguration::se_handler_table, &self); + } + + /// The count of unique handlers in the table. This member is available only for x86. + pub fn se_handler_count(&self) -> Option { + to_opt!(&lief_ffi::PE_LoadConfiguration::se_handler_count, &self); + } + + /// Return the list of the function RVA in the SEH table (if any) + pub fn seh_functions(&self) -> Vec { + Vec::from(self.ptr.seh_functions().as_slice()) + } + + /// The VA where Control Flow Guard check-function pointer is stored. + pub fn guard_cf_check_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_cf_check_function_pointer, + &self + ); + } + + /// The VA where Control Flow Guard dispatch-function pointer is stored. + pub fn guard_cf_dispatch_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_cf_dispatch_function_pointer, + &self + ); + } + + /// The VA of the sorted table of RVAs of each Control Flow Guard function in the image. + pub fn guard_cf_function_table(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_cf_function_table, + &self + ); + } + + /// The count of unique RVAs in the [`LoadConfiguration::guard_cf_function_table`] table. + pub fn guard_cf_function_count(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_cf_function_count, + &self + ); + } + + /// Iterator over the Control Flow Guard functions referenced by + /// [`LoadConfiguration::guard_cf_function_table`] + pub fn guard_cf_functions(&self) -> GuardCFFunctions<'_> { + GuardCFFunctions::new(self.ptr.guard_cf_functions()) + } + + /// Control Flow Guard related flags. + pub fn guard_flags(&self) -> Option { + to_conv_opt!( + &lief_ffi::PE_LoadConfiguration::guard_flags, + &self, + |e: u32| ImageGuardFlags::from(e) + ); + } + + /// Code integrity information. + pub fn code_integrity(&self) -> Option> { + into_optional(self.ptr.code_integrity()) + } + + /// The VA where Control Flow Guard address taken IAT table is stored. + pub fn guard_address_taken_iat_entry_table(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_address_taken_iat_entry_table, + &self + ); + } + + /// The count of unique RVAs in the table pointed by + /// [`LoadConfiguration::guard_address_taken_iat_entry_table`]. + pub fn guard_address_taken_iat_entry_count(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_address_taken_iat_entry_count, + &self + ); + } + + /// Iterator over the functions referenced by + /// [`LoadConfiguration::guard_address_taken_iat_entry_table`] + pub fn guard_address_taken_iat_entries(&self) -> GuardAddressTakenIATEntries<'_> { + GuardAddressTakenIATEntries::new(self.ptr.guard_address_taken_iat_entries()) + } + + /// The VA where Control Flow Guard long jump target table is stored. + pub fn guard_long_jump_target_table(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_long_jump_target_table, + &self + ); + } + + /// The count of unique RVAs in the table pointed by + /// [`LoadConfiguration::guard_long_jump_target_table`]. + pub fn guard_long_jump_target_count(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_long_jump_target_count, + &self + ); + } + + /// Iterator over the functions referenced by + /// [`LoadConfiguration::guard_long_jump_target_table`] + pub fn guard_long_jump_targets(&self) -> GuardLongJumpTargets<'_> { + GuardLongJumpTargets::new(self.ptr.guard_long_jump_targets()) + } + + /// VA of pointing to a `IMAGE_DYNAMIC_RELOCATION_TABLE` + pub fn dynamic_value_reloc_table(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::dynamic_value_reloc_table, + &self + ); + } + + /// Alias for [`LoadConfiguration::chpe_metadata_pointer`] + pub fn hybrid_metadata_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::hybrid_metadata_pointer, + &self + ); + } + + /// VA to the extra Compiled Hybrid Portable Executable (CHPE) metadata. + pub fn chpe_metadata_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::chpe_metadata_pointer, + &self + ); + } + + /// Compiled Hybrid Portable Executable (CHPE) metadata (if any) + pub fn chpe_metadata(&self) -> Option> { + into_optional(self.ptr.chpe_metadata()) + } + + /// VA of the failure routine + pub fn guard_rf_failure_routine(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_rf_failure_routine, + &self + ); + } + + /// VA of the failure routine `fptr`. + pub fn guard_rf_failure_routine_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_rf_failure_routine_function_pointer, + &self + ); + } + + /// Offset of dynamic relocation table relative to the relocation table + pub fn dynamic_value_reloctable_offset(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::dynamic_value_reloctable_offset, + &self + ); + } + + /// The section index of the dynamic value relocation table + pub fn dynamic_value_reloctable_section(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::dynamic_value_reloctable_section, + &self + ); + } + + /// Return an iterator over the Dynamic relocations (DVRT) + pub fn dynamic_relocations(&self) -> DynamicRelocations<'_> { + DynamicRelocations::new(self.ptr.dynamic_relocations()) + } + + /// Must be zero + pub fn reserved2(&self) -> Option { + to_opt!(&lief_ffi::PE_LoadConfiguration::reserved2, &self); + } + + /// VA of the Function verifying the stack pointer + pub fn guard_rf_verify_stackpointer_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_rf_verify_stackpointer_function_pointer, + &self + ); + } + + pub fn hotpatch_table_offset(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::hotpatch_table_offset, + &self + ); + } + + pub fn reserved3(&self) -> Option { + to_opt!(&lief_ffi::PE_LoadConfiguration::reserved3, &self); + } + + pub fn enclave_config(&self) -> Option> { + into_optional(self.ptr.enclave_config()) + } + + pub fn enclave_configuration_ptr(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::enclave_configuration_ptr, + &self + ); + } + + pub fn volatile_metadata_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::volatile_metadata_pointer, + &self + ); + } + + pub fn volatile_metadata(&self) -> Option> { + into_optional(self.ptr.volatile_metadata()) + } + + pub fn guard_eh_continuation_table(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_eh_continuation_table, + &self + ); + } + + pub fn guard_eh_continuation_count(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_eh_continuation_count, + &self + ); + } + + /// Iterator over the Guard EH continuation functions referenced by + /// [`LoadConfiguration::guard_eh_continuation_table`] + pub fn guard_eh_continuation_functions(&self) -> GuardEhContinuationFunctions<'_> { + GuardEhContinuationFunctions::new(self.ptr.guard_eh_continuation_functions()) + } + + pub fn guard_xfg_check_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_xfg_check_function_pointer, + &self + ); + } + + pub fn guard_xfg_dispatch_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_xfg_dispatch_function_pointer, + &self + ); + } + + pub fn guard_xfg_table_dispatch_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_xfg_table_dispatch_function_pointer, + &self + ); + } + + pub fn cast_guard_os_determined_failure_mode(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::cast_guard_os_determined_failure_mode, + &self + ); + } + + pub fn guard_memcpy_function_pointer(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::guard_memcpy_function_pointer, + &self + ); + } + + pub fn uma_function_pointers(&self) -> Option { + to_opt!( + &lief_ffi::PE_LoadConfiguration::uma_function_pointers, + &self + ); + } + + /// Set the characteristics value + pub fn set_characteristics(&mut self, value: u32) { + self.ptr.pin_mut().set_characteristics(value); + } + + /// Set the size value + pub fn set_size(&mut self, value: u32) { + self.ptr.pin_mut().set_size(value); + } + + /// Set the timedatestamp value + pub fn set_timedatestamp(&mut self, value: u32) { + self.ptr.pin_mut().set_timedatestamp(value); + } + + /// Set the major version + pub fn set_major_version(&mut self, value: u16) { + self.ptr.pin_mut().set_major_version(value); + } + + /// Set the minor version + pub fn set_minor_version(&mut self, value: u16) { + self.ptr.pin_mut().set_minor_version(value); + } + + /// Set the global flags to clear + pub fn set_global_flags_clear(&mut self, value: u32) { + self.ptr.pin_mut().set_global_flags_clear(value); + } + + /// Set the global flags to set + pub fn set_global_flags_set(&mut self, value: u32) { + self.ptr.pin_mut().set_global_flags_set(value); + } + + /// Set the critical section default timeout + pub fn set_critical_section_default_timeout(&mut self, value: u32) { + self.ptr + .pin_mut() + .set_critical_section_default_timeout(value); + } + + /// Set the decommit free block threshold + pub fn set_decommit_free_block_threshold(&mut self, value: u64) { + self.ptr.pin_mut().set_decommit_free_block_threshold(value); + } + + /// Set the decommit total free threshold + pub fn set_decommit_total_free_threshold(&mut self, value: u64) { + self.ptr.pin_mut().set_decommit_total_free_threshold(value); + } + + /// Set the lock prefix table VA + pub fn set_lock_prefix_table(&mut self, value: u64) { + self.ptr.pin_mut().set_lock_prefix_table(value); + } + + /// Set the maximum allocation size + pub fn set_maximum_allocation_size(&mut self, value: u64) { + self.ptr.pin_mut().set_maximum_allocation_size(value); + } + + /// Set the virtual memory threshold + pub fn set_virtual_memory_threshold(&mut self, value: u64) { + self.ptr.pin_mut().set_virtual_memory_threshold(value); + } + + /// Set the process affinity mask + pub fn set_process_affinity_mask(&mut self, value: u64) { + self.ptr.pin_mut().set_process_affinity_mask(value); + } + + /// Set the process heap flags + pub fn set_process_heap_flags(&mut self, value: u32) { + self.ptr.pin_mut().set_process_heap_flags(value); + } + + /// Set the CSD version + pub fn set_csd_version(&mut self, value: u16) { + self.ptr.pin_mut().set_csd_version(value); + } + + /// Set reserved1 + pub fn set_reserved1(&mut self, value: u16) { + self.ptr.pin_mut().set_reserved1(value); + } + + /// Set the dependent load flags + pub fn set_dependent_load_flags(&mut self, value: u16) { + self.ptr.pin_mut().set_dependent_load_flags(value); + } + + /// Set the editlist VA + pub fn set_editlist(&mut self, value: u32) { + self.ptr.pin_mut().set_editlist(value); + } + + /// Set the security cookie VA + pub fn set_security_cookie(&mut self, value: u64) { + self.ptr.pin_mut().set_security_cookie(value); + } + + /// Set the SE handler table VA + pub fn set_se_handler_table(&mut self, value: u64) { + self.ptr.pin_mut().set_se_handler_table(value); + } + + /// Set the SE handler count + pub fn set_se_handler_count(&mut self, value: u64) { + self.ptr.pin_mut().set_se_handler_count(value); + } + + /// Set the guard CF check function pointer VA + pub fn set_guard_cf_check_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_cf_check_function_pointer(value); + } + + /// Set the guard CF dispatch function pointer VA + pub fn set_guard_cf_dispatch_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_cf_dispatch_function_pointer(value); + } + + /// Set the guard CF function table VA + pub fn set_guard_cf_function_table(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_cf_function_table(value); + } + + /// Set the guard CF function count + pub fn set_guard_cf_function_count(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_cf_function_count(value); + } + + /// Set the guard flags + pub fn set_guard_flags(&mut self, flags: ImageGuardFlags) { + self.ptr.pin_mut().set_guard_flags(flags.bits()); + } + + /// Set the guard address taken IAT entry table VA + pub fn set_guard_address_taken_iat_entry_table(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_address_taken_iat_entry_table(value); + } + + /// Set the guard address taken IAT entry count + pub fn set_guard_address_taken_iat_entry_count(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_address_taken_iat_entry_count(value); + } + + /// Set the guard long jump target table VA + pub fn set_guard_long_jump_target_table(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_long_jump_target_table(value); + } + + /// Set the guard long jump target count + pub fn set_guard_long_jump_target_count(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_long_jump_target_count(value); + } + + /// Set the dynamic value relocation table VA + pub fn set_dynamic_value_reloc_table(&mut self, value: u64) { + self.ptr.pin_mut().set_dynamic_value_reloc_table(value); + } + + /// Set the hybrid metadata pointer VA + pub fn set_hybrid_metadata_pointer(&mut self, value: u64) { + self.ptr.pin_mut().set_hybrid_metadata_pointer(value); + } + + /// Set the guard RF failure routine VA + pub fn set_guard_rf_failure_routine(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_rf_failure_routine(value); + } + + /// Set the guard RF failure routine function pointer VA + pub fn set_guard_rf_failure_routine_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_rf_failure_routine_function_pointer(value); + } + + /// Set the dynamic value relocation table offset + pub fn set_dynamic_value_reloctable_offset(&mut self, value: u32) { + self.ptr + .pin_mut() + .set_dynamic_value_reloctable_offset(value); + } + + /// Set the dynamic value relocation table section + pub fn set_dynamic_value_reloctable_section(&mut self, value: u16) { + self.ptr + .pin_mut() + .set_dynamic_value_reloctable_section(value); + } + + /// Set reserved2 + pub fn set_reserved2(&mut self, value: u16) { + self.ptr.pin_mut().set_reserved2(value); + } + + /// Set the guard RF verify stack pointer function pointer VA + pub fn set_guard_rf_verify_stackpointer_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_rf_verify_stackpointer_function_pointer(value); + } + + /// Set the hotpatch table offset + pub fn set_hotpatch_table_offset(&mut self, value: u32) { + self.ptr.pin_mut().set_hotpatch_table_offset(value); + } + + /// Set reserved3 + pub fn set_reserved3(&mut self, value: u32) { + self.ptr.pin_mut().set_reserved3(value); + } + + /// Set the enclave configuration pointer VA + pub fn set_enclave_configuration_ptr(&mut self, value: u64) { + self.ptr.pin_mut().set_enclave_configuration_ptr(value); + } + + /// Set the volatile metadata pointer VA + pub fn set_volatile_metadata_pointer(&mut self, value: u64) { + self.ptr.pin_mut().set_volatile_metadata_pointer(value); + } + + /// Set the guard EH continuation table VA + pub fn set_guard_eh_continuation_table(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_eh_continuation_table(value); + } + + /// Set the guard EH continuation count + pub fn set_guard_eh_continuation_count(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_eh_continuation_count(value); + } + + /// Set the guard XFG check function pointer VA + pub fn set_guard_xfg_check_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_xfg_check_function_pointer(value); + } + + /// Set the guard XFG dispatch function pointer VA + pub fn set_guard_xfg_dispatch_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_xfg_dispatch_function_pointer(value); + } + + /// Set the guard XFG table dispatch function pointer VA + pub fn set_guard_xfg_table_dispatch_function_pointer(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_guard_xfg_table_dispatch_function_pointer(value); + } + + /// Set the CastGuard OS determined failure mode VA + pub fn set_cast_guard_os_determined_failure_mode(&mut self, value: u64) { + self.ptr + .pin_mut() + .set_cast_guard_os_determined_failure_mode(value); + } + + /// Set the guard memcpy function pointer VA + pub fn set_guard_memcpy_function_pointer(&mut self, value: u64) { + self.ptr.pin_mut().set_guard_memcpy_function_pointer(value); + } + + /// Set the UMA function pointers VA + pub fn set_uma_function_pointers(&mut self, value: u64) { + self.ptr.pin_mut().set_uma_function_pointers(value); + } +} + +impl<'a> FromFFI for LoadConfiguration<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl std::fmt::Debug for LoadConfiguration<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("LoadConfiguration") + .field("size", &self.size()) + .field("timedatestamp", &self.timedatestamp()) + .field("major_version", &self.major_version()) + .field("minor_version", &self.minor_version()) + .field("global_flags_clear", &self.global_flags_clear()) + .field("global_flags_set", &self.global_flags_set()) + .field( + "critical_section_default_timeout", + &self.critical_section_default_timeout(), + ) + .field( + "decommit_free_block_threshold", + &self.decommit_free_block_threshold(), + ) + .field( + "decommit_total_free_threshold", + &self.decommit_total_free_threshold(), + ) + .field("lock_prefix_table", &self.lock_prefix_table()) + .field("maximum_allocation_size", &self.maximum_allocation_size()) + .field("virtual_memory_threshold", &self.virtual_memory_threshold()) + .field("process_affinity_mask", &self.process_affinity_mask()) + .field("process_heap_flags", &self.process_heap_flags()) + .field("csd_version", &self.csd_version()) + .field("reserved1", &self.reserved1()) + .field("dependent_load_flags", &self.dependent_load_flags()) + .field("editlist", &self.editlist()) + .field("security_cookie", &self.security_cookie()) + .field("se_handler_table", &self.se_handler_table()) + .field("se_handler_count", &self.se_handler_count()) + .field( + "guard_cf_check_function_pointer", + &self.guard_cf_check_function_pointer(), + ) + .field( + "guard_cf_dispatch_function_pointer", + &self.guard_cf_dispatch_function_pointer(), + ) + .field("guard_cf_function_table", &self.guard_cf_function_table()) + .field("guard_cf_function_count", &self.guard_cf_function_count()) + .field("guard_flags", &self.guard_flags()) + .field( + "guard_address_taken_iat_entry_table", + &self.guard_address_taken_iat_entry_table(), + ) + .field( + "guard_address_taken_iat_entry_count", + &self.guard_address_taken_iat_entry_count(), + ) + .field( + "guard_long_jump_target_table", + &self.guard_long_jump_target_table(), + ) + .field( + "guard_long_jump_target_count", + &self.guard_long_jump_target_count(), + ) + .field( + "dynamic_value_reloc_table", + &self.dynamic_value_reloc_table(), + ) + .field("hybrid_metadata_pointer", &self.hybrid_metadata_pointer()) + .field("chpe_metadata_pointer", &self.chpe_metadata_pointer()) + .field("guard_rf_failure_routine", &self.guard_rf_failure_routine()) + .field( + "guard_rf_failure_routine_function_pointer", + &self.guard_rf_failure_routine_function_pointer(), + ) + .field( + "dynamic_value_reloctable_offset", + &self.dynamic_value_reloctable_offset(), + ) + .field( + "dynamic_value_reloctable_section", + &self.dynamic_value_reloctable_section(), + ) + .field("reserved2", &self.reserved2()) + .field( + "guard_rf_verify_stackpointer_function_pointer", + &self.guard_rf_verify_stackpointer_function_pointer(), + ) + .field("hotpatch_table_offset", &self.hotpatch_table_offset()) + .field("reserved3", &self.reserved3()) + .field( + "enclave_configuration_ptr", + &self.enclave_configuration_ptr(), + ) + .field( + "volatile_metadata_pointer", + &self.volatile_metadata_pointer(), + ) + .field( + "guard_eh_continuation_table", + &self.guard_eh_continuation_table(), + ) + .field( + "guard_eh_continuation_count", + &self.guard_eh_continuation_count(), + ) + .field( + "guard_xfg_check_function_pointer", + &self.guard_xfg_check_function_pointer(), + ) + .field( + "guard_xfg_dispatch_function_pointer", + &self.guard_xfg_dispatch_function_pointer(), + ) + .field( + "guard_xfg_table_dispatch_function_pointer", + &self.guard_xfg_table_dispatch_function_pointer(), + ) + .field( + "cast_guard_os_determined_failure_mode", + &self.cast_guard_os_determined_failure_mode(), + ) + .field( + "guard_memcpy_function_pointer", + &self.guard_memcpy_function_pointer(), + ) + .field("uma_function_pointers", &self.uma_function_pointers()) + .finish() + } +} + +pub struct GuardFunction<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for GuardFunction<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl GuardFunction<'_> { + /// RVA of the function + pub fn rva(&self) -> u32 { + self.ptr.rva() + } + + /// Additional information whose meaning is not officially documented + pub fn extra(&self) -> u32 { + self.ptr.extra() + } +} + +impl std::fmt::Debug for GuardFunction<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("GuardFunction") + .field("rva", &self.rva()) + .field("extra", &self.extra()) + .finish() + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct ImageGuardFlags: u32 { + const NONE = 0x0; + + /// Module performs control flow integrity checks using system-supplied + /// support. + const CF_INSTRUMENTED = 0x100; + + /// Module performs control flow and write integrity checks. + const CFW_INSTRUMENTED = 0x200; + + /// Module contains valid control flow target metadata. + const CF_FUNCTION_TABLE_PRESENT = 0x400; + + /// Module does not make use of the /GS security cookie. + const SECURITY_COOKIE_UNUSED = 0x800; + + /// Module supports read only delay load IAT. + const PROTECT_DELAYLOAD_IAT = 0x1000; + + /// Delayload import table in its own .didat section (with nothing else in it) + /// that can be freely reprotected. + const DELAYLOAD_IAT_IN_ITS_OWN_SECTION = 0x2000; + + /// Module contains suppressed export information. This also infers that the + /// address taken IAT table is also present in the load config. + const CF_EXPORT_SUPPRESSION_INFO_PRESENT = 0x4000; + + /// Module enables suppression of exports. + const CF_ENABLE_EXPORT_SUPPRESSION = 0x8000; + + /// Module contains longjmp target information. + const CF_LONGJUMP_TABLE_PRESENT = 0x10000; + + /// Module contains return flow instrumentation and metadata + const RF_INSTRUMENTED = 0x20000; + + /// Module requests that the OS enable return flow protection + const RF_ENABLE = 0x40000; + + /// Module requests that the OS enable return flow protection in strict mode + const RF_STRICT = 0x80000; + + /// Module was built with retpoline support + const RETPOLINE_PRESENT = 0x100000; + + /// Module contains EH continuation target information. + const EH_CONTINUATION_TABLE_PRESENT = 0x200000; + + /// Module was built with xfg (deprecated) + const XFG_ENABLED = 0x00800000; + + /// Module has CastGuard instrumentation present + const CASTGUARD_PRESENT = 0x01000000; + + /// Module has Guarded Memcpy instrumentation present + const MEMCPY_PRESENT = 0x02000000; + } +} + +impl From for ImageGuardFlags { + fn from(value: u32) -> Self { + ImageGuardFlags::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: ImageGuardFlags) -> Self { + value.bits() + } +} +impl std::fmt::Display for ImageGuardFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +#[derive(Debug)] +pub enum CHPEMetadata<'a> { + ARM64(chpe_metadata_arm64::CHPEMetadata<'a>), + X86(chpe_metadata_x86::CHPEMetadata<'a>), +} + +impl<'a> FromFFI for CHPEMetadata<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let obj_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_CHPEMetadataARM64::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + CHPEMetadata::ARM64(chpe_metadata_arm64::CHPEMetadata::from_ffi(raw)) + } else if ffi::PE_CHPEMetadataX86::classof(obj_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + CHPEMetadata::X86(chpe_metadata_x86::CHPEMetadata::from_ffi(raw)) + } else { + panic!("unsupported architecture"); + } + } + } +} + +/// Trait shared by all architecture-specific CHPEMetadata +pub trait AsCHPEMetadata { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_CHPEMetadata; + + /// Version of the structure + fn version(&self) -> u32 { + self.as_generic().version() + } +} + +impl std::fmt::Display for &dyn AsCHPEMetadata { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.as_generic().to_string()) + } +} + +impl AsCHPEMetadata for CHPEMetadata<'_> { + fn as_generic(&self) -> &ffi::PE_CHPEMetadata { + match &self { + CHPEMetadata::ARM64(entry) => entry.as_generic(), + + CHPEMetadata::X86(entry) => entry.as_generic(), + } + } +} + +declare_iterator!( + GuardCFFunctions, + GuardFunction<'a>, + ffi::PE_LoadConfiguration_guard_function_t, + ffi::PE_LoadConfiguration, + ffi::PE_LoadConfiguration_it_guard_cf_functions +); + +declare_iterator!( + GuardAddressTakenIATEntries, + GuardFunction<'a>, + ffi::PE_LoadConfiguration_guard_function_t, + ffi::PE_LoadConfiguration, + ffi::PE_LoadConfiguration_it_guard_address_taken_iat_entries +); + +declare_iterator!( + GuardLongJumpTargets, + GuardFunction<'a>, + ffi::PE_LoadConfiguration_guard_function_t, + ffi::PE_LoadConfiguration, + ffi::PE_LoadConfiguration_it_guard_long_jump_targets +); + +declare_iterator!( + GuardEhContinuationFunctions, + GuardFunction<'a>, + ffi::PE_LoadConfiguration_guard_function_t, + ffi::PE_LoadConfiguration, + ffi::PE_LoadConfiguration_it_guard_eh_continuation +); + +declare_iterator!( + DynamicRelocations, + DynamicRelocation<'a>, + ffi::PE_DynamicRelocation, + ffi::PE_LoadConfiguration, + ffi::PE_LoadConfiguration_it_dynamic_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/parser_config.rs b/vendor/lief/api/rust/crates/lief/src/pe/parser_config.rs new file mode 100644 index 0000000..2f1f0eb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/parser_config.rs @@ -0,0 +1,87 @@ +use lief_ffi as ffi; + +/// This structure is used to configure the behavior of the PE Parser: [`crate::pe::Binary::parse_with_config`] +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct Config { + /// Whether to parse the PE Authenticode signature. + pub parse_signature: bool, + + /// Whether to parse the PE Export Directory. + pub parse_exports: bool, + + /// Whether to parse the PE Import Directory. + pub parse_imports: bool, + + /// Whether to parse the PE resources tree. + pub parse_rsrc: bool, + + /// Whether to parse PE relocations. + pub parse_reloc: bool, + + /// Whether to parse in-depth exception metadata. + /// + /// This option is disabled by default because it can introduce significant + /// parsing overhead. + pub parse_exceptions: bool, + + /// Whether to parse nested ARM64X binaries. + /// + /// This option is disabled by default because it can introduce significant + /// parsing overhead. + pub parse_arm64x_binary: bool, + + /// If set, this value holds the original image base from which the binary + /// should be rebased. This is used to *undo* relocations and IAT bindings + /// when parsing a PE loaded in memory. + pub rebase: Option, +} + +impl Default for Config { + fn default() -> Config { + Config { + parse_signature: true, + parse_exports: true, + parse_imports: true, + parse_rsrc: true, + parse_reloc: true, + parse_exceptions: false, + parse_arm64x_binary: false, + rebase: None, + } + } +} + +impl Config { + #[doc(hidden)] + pub fn to_ffi(&self) -> cxx::UniquePtr { + let mut ptr = ffi::PE_ParserConfig::create(); + ptr.pin_mut().set_parse_signature(self.parse_signature); + ptr.pin_mut().set_parse_exports(self.parse_exports); + ptr.pin_mut().set_parse_imports(self.parse_imports); + ptr.pin_mut().set_parse_rsrc(self.parse_rsrc); + ptr.pin_mut().set_parse_reloc(self.parse_reloc); + ptr.pin_mut().set_parse_exceptions(self.parse_exceptions); + ptr.pin_mut() + .set_parse_arm64x_binary(self.parse_arm64x_binary); + if let Some(rebase_val) = self.rebase { + ptr.pin_mut().set_rebase(rebase_val); + } else { + ptr.pin_mut().clear_rebase(); + } + ptr + } + + /// Configuration that enables all optional parsing features. + pub fn with_all_options() -> Self { + Self { + parse_signature: true, + parse_exports: true, + parse_imports: true, + parse_rsrc: true, + parse_reloc: true, + parse_exceptions: true, + parse_arm64x_binary: true, + rebase: None, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/relocation.rs b/vendor/lief/api/rust/crates/lief/src/pe/relocation.rs new file mode 100644 index 0000000..0fe605a --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/relocation.rs @@ -0,0 +1,188 @@ +//! This module includes the different structures related to the relocation process in a PE binary + +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::{declare_iterator, generic}; + +/// Class which represents the *Base Relocation Block* +/// We usually find this structure in the `.reloc` section +pub struct Relocation<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl Relocation<'_> { + /// The RVA for which the offset of the relocation entries is added + pub fn virtual_address(&self) -> u32 { + self.ptr.virtual_address() + } + + /// The total number of bytes in the base relocation block. + /// `block_size = sizeof(BaseRelocationBlock) + nb_of_relocs * sizeof(uint16_t = RelocationEntry)` + pub fn block_size(&self) -> u32 { + self.ptr.block_size() + } + /// Iterator over the Relocation [`Entry`] + pub fn entries(&self) -> RelocationEntries<'_> { + RelocationEntries::new(self.ptr.entries()) + } +} + +impl std::fmt::Debug for Relocation<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Relocation") + .field("virtual_address", &self.virtual_address()) + .field("block_size", &self.block_size()) + .finish() + } +} + +impl<'a> FromFFI for Relocation<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Relocation { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum BaseType { + ABS, + HIGH, + LOW, + HIGHLOW, + HIGHADJ, + MIPS_JMPADDR, + ARM_MOV32, + RISCV_HI20, + SECTION, + THUMB_MOV32, + RISCV_LOW12I, + RISCV_LOW12S, + LOONARCH_MARK_LA, + MIPS_JMPADDR16, + DIR64, + HIGH3ADJ, + UNKNOWN(u32), +} + +impl From for BaseType { + fn from(value: u32) -> Self { + match value { + 0x00000000 => BaseType::ABS, + 0x00000001 => BaseType::HIGH, + 0x00000002 => BaseType::LOW, + 0x00000003 => BaseType::HIGHLOW, + 0x00000004 => BaseType::HIGHADJ, + 0x00000105 => BaseType::MIPS_JMPADDR, + 0x00000205 => BaseType::ARM_MOV32, + 0x00000405 => BaseType::RISCV_HI20, + 0x00000006 => BaseType::SECTION, + 0x00000807 => BaseType::THUMB_MOV32, + 0x00001007 => BaseType::RISCV_LOW12I, + 0x00002008 => BaseType::RISCV_LOW12S, + 0x00004008 => BaseType::LOONARCH_MARK_LA, + 0x00000009 => BaseType::MIPS_JMPADDR16, + 0x0000000a => BaseType::DIR64, + 0x0000000b => BaseType::HIGH3ADJ, + _ => BaseType::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: BaseType) -> u32 { + match value { + BaseType::ABS => 0x00000000, + BaseType::HIGH => 0x00000001, + BaseType::LOW => 0x00000002, + BaseType::HIGHLOW => 0x00000003, + BaseType::HIGHADJ => 0x00000004, + BaseType::MIPS_JMPADDR => 0x00000105, + BaseType::ARM_MOV32 => 0x00000205, + BaseType::RISCV_HI20 => 0x00000405, + BaseType::SECTION => 0x00000006, + BaseType::THUMB_MOV32 => 0x00000807, + BaseType::RISCV_LOW12I => 0x00001007, + BaseType::RISCV_LOW12S => 0x00002008, + BaseType::LOONARCH_MARK_LA => 0x00004008, + BaseType::MIPS_JMPADDR16 => 0x00000009, + BaseType::DIR64 => 0x0000000a, + BaseType::HIGH3ADJ => 0x0000000b, + BaseType::UNKNOWN(value) => value, + } + } +} + +/// Class which represents an entry in the relocation table +/// +/// It implements the [`generic::Relocation`] trait which provides additional functions +pub struct Entry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Relocation>, +} + +impl generic::Relocation for Entry<'_> { + fn as_generic(&self) -> &ffi::AbstractRelocation { + self.ptr.as_ref().unwrap().as_ref() + } +} + +impl Entry<'_> { + /// Offset relative to [`Relocation::virtual_address`] where the relocation occurs. + pub fn position(&self) -> u64 { + self.ptr.position() + } + + /// Type of the relocation + pub fn get_type(&self) -> BaseType { + BaseType::from(self.ptr.get_type()) + } + + /// Raw data of the relocation: + /// - The **high** 4 bits store the relocation type + /// - The **low** 12 bits store the relocation offset + pub fn data(&self) -> u16 { + self.ptr.data() + } +} + +impl std::fmt::Debug for Entry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Relocation; + f.debug_struct("RelocationEntry") + .field("base", &base) + .field("type", &self.get_type()) + .field("data", &self.data()) + .field("position", &self.position()) + .finish() + } +} + +impl<'a> FromFFI for Entry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Entry { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + RelocationEntries, + Entry<'a>, + ffi::PE_RelocationEntry, + ffi::PE_Relocation, + ffi::PE_Relocation_it_entries +); +declare_iterator!( + Relocations, + Relocation<'a>, + ffi::PE_Relocation, + ffi::PE_Binary, + ffi::PE_Binary_it_relocations +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/resources.rs b/vendor/lief/api/rust/crates/lief/src/pe/resources.rs new file mode 100644 index 0000000..ff3e914 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/resources.rs @@ -0,0 +1,1057 @@ +//! This module contains the different structures involved in the PE's resource tree +//! +//! One can access this tree using either: [`crate::pe::Binary::resources`] or by parsing raw bytes +//! with [`Node::from_slice`]. The [`Manager`] provides a logical API over the resource tree +//! to access specifics parts of the tree. + +use lief_ffi as ffi; + +use std::pin::Pin; +use std::{fmt, marker::PhantomData}; + +use crate::common::into_optional; +use crate::to_slice; +use crate::{common::FromFFI, declare_iterator}; + +/// This enum represents a node in the resource tree which can be either: a **directory** node +/// or a data (leaf) node. +#[derive(Debug)] +pub enum Node<'a> { + /// A *data* node (i.e. a leaf) + Data(Data<'a>), + /// A directory node + Directory(Directory<'a>), +} + +impl Node<'_> { + /// Parse a resource tree from the provided slice. The original RVA must be provided + /// to resolve the content of the data nodes. + pub fn from_slice(content: &[u8], rva: u64) -> Option> { + unsafe { + let ptr = ffi::PE_ResourceNode::from_slice(content.as_ptr(), content.len(), rva); + if ptr.is_null() { + return None; + } + Some(Node::from_ffi(ptr)) + } + } +} + +/// Trait that is shared by both [`Node::Data`] and [`Node::Directory`]. +pub trait NodeBase { + #[doc(hidden)] + fn get_base(&self) -> &ffi::PE_ResourceNode; + + #[doc(hidden)] + fn base_as_pin_mut(&mut self) -> Pin<&mut ffi::PE_ResourceNode>; + + /// Integer that identifies the Type, Name, or Language ID of the entry + /// depending on its [`NodeBase::depth`] in the tree + fn id(&self) -> u32 { + self.get_base().id() + } + + /// Current depth of the Node in the resource tree + fn depth(&self) -> u32 { + self.get_base().depth() + } + + /// Iterator on node's children + fn children(&self) -> Children<'_> { + Children::new(self.get_base().childs()) + } + + /// Name of the node (if any) + fn name(&self) -> Option { + if !self.get_base().has_name() { + return None; + } + Some(self.get_base().name().to_string()) + } + + /// Add a new child node to the current and return the newly-added node + fn add_child(&mut self, node: &Node) -> Node<'_> { + Node::from_ffi(self.base_as_pin_mut().add_child(node.get_base())) + } + + /// Delete the child node with the given id + fn delete_child(&mut self, id: u32) { + self.base_as_pin_mut().delete_child(id); + } +} + +impl std::fmt::Debug for &dyn NodeBase { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("NodeBase").field("id", &self.id()).finish() + } +} + +impl std::fmt::Display for &dyn NodeBase { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.get_base().print()) + } +} + +impl<'a> FromFFI for Node<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::PE_ResourceDirectory::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Node::Directory(Directory::from_ffi(raw)) + } else { + assert!( + ffi::PE_ResourceData::classof(cmd_ref), + "Must be a ResourceData node" + ); + + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Node::Data(Data::from_ffi(raw)) + } + } + } +} + +pub struct Data<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a Node<'a>>, +} + +impl Data<'_> { + /// Create a new Data node with the provided payload + pub fn with_buffer(buffer: &[u8]) -> Data<'static> { + unsafe { + Data::from_ffi(ffi::PE_ResourceData::create_from_data( + buffer.as_ptr(), + buffer.len(), + )) + } + } + + /// Create a new Data node + pub fn new() -> Data<'static> { + Data::from_ffi(ffi::PE_ResourceData::create()) + } + + /// Return the code page that is used to decode code point + /// values within the resource data. Typically, the code page is the unicode code page. + pub fn code_page(&self) -> u32 { + self.ptr.code_page() + } + + /// Reserved value. Should be `0` + pub fn reserved(&self) -> u32 { + self.ptr.reserved() + } + + /// Offset of the content within the resource + /// + ///
this value may change when rebuilding resource table
+ pub fn offset(&self) -> u32 { + self.ptr.offset() + } + + /// Resource content + pub fn content(&self) -> &[u8] { + to_slice!(self.ptr.content()); + } + + /// Change or set the raw data associated with this node + pub fn set_content(&mut self, content: &[u8]) -> &mut Self { + unsafe { + self.ptr + .pin_mut() + .set_content(content.as_ptr(), content.len()); + } + self + } + + /// Change or set the code page + pub fn set_code_page(&mut self, code_page: u32) -> &mut Self { + self.ptr.pin_mut().set_code_page(code_page); + self + } + + /// Change or set the *reserved* field + pub fn set_reserved(&mut self, reserved: u32) -> &mut Self { + self.ptr.pin_mut().set_reserved(reserved); + self + } +} + +impl NodeBase for Data<'_> { + fn get_base(&self) -> &ffi::PE_ResourceNode { + self.ptr.as_ref().unwrap().as_ref() + } + + fn base_as_pin_mut(&mut self) -> Pin<&mut ffi::PE_ResourceNode> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_ResourceNode + as *mut ffi::PE_ResourceNode) + .as_mut() + .unwrap() + }) + } + } +} + +impl fmt::Debug for Data<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn NodeBase; + f.debug_struct("Data") + .field("base", &base) + .field("code_page", &self.code_page()) + .field("reserved", &self.reserved()) + .field("offset", &self.offset()) + .finish() + } +} + +impl<'a> FromFFI for Data<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +pub struct Directory<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a Node<'a>>, +} + +impl Directory<'_> { + /// Create a new Directory node with the given d + pub fn with_id(id: u32) -> Directory<'static> { + Directory::from_ffi(ffi::PE_ResourceDirectory::create_from_id(id)) + } + + /// Create a new Directory node + pub fn new() -> Directory<'static> { + Directory::from_ffi(ffi::PE_ResourceDirectory::create()) + } + + /// Resource characteristics. This field is reserved for future use. + /// It is currently set to zero. + pub fn characteristics(&self) -> u32 { + self.ptr.characteristics() + } + + /// The time that the resource data was created by the + /// resource compiler. + pub fn time_date_stamp(&self) -> u32 { + self.ptr.time_date_stamp() + } + + /// The major version number, set by the user. + pub fn major_version(&self) -> u32 { + self.ptr.major_version() + } + + /// The minor version number, set by the user. + pub fn minor_version(&self) -> u32 { + self.ptr.minor_version() + } + + /// The number of directory entries immediately + /// following the table that use strings to identify Type, + /// Name, or Language entries (depending on the level of the table). + pub fn numberof_name_entries(&self) -> u32 { + self.ptr.numberof_name_entries() + } + + /// The number of directory entries immediately + /// following the Name entries that use numeric IDs for + /// Type, Name, or Language entries. + pub fn numberof_id_entries(&self) -> u32 { + self.ptr.numberof_id_entries() + } +} + +impl NodeBase for Directory<'_> { + fn get_base(&self) -> &ffi::PE_ResourceNode { + self.ptr.as_ref().unwrap().as_ref() + } + + fn base_as_pin_mut(&mut self) -> Pin<&mut ffi::PE_ResourceNode> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::PE_ResourceNode + as *mut ffi::PE_ResourceNode) + .as_mut() + .unwrap() + }) + } + } +} + +impl NodeBase for Node<'_> { + fn get_base(&self) -> &ffi::PE_ResourceNode { + match &self { + Node::Data(n) => n.get_base(), + Node::Directory(n) => n.get_base(), + } + } + + fn base_as_pin_mut(&mut self) -> Pin<&mut ffi::PE_ResourceNode> { + match self { + Node::Data(n) => n.base_as_pin_mut(), + Node::Directory(n) => n.base_as_pin_mut(), + } + } +} + +impl fmt::Debug for Directory<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let base = self as &dyn NodeBase; + f.debug_struct("Directory") + .field("base", &base) + .field("characteristics", &self.characteristics()) + .field("time_date_stamp", &self.time_date_stamp()) + .field("major_version", &self.major_version()) + .field("minor_version", &self.minor_version()) + .field("numberof_name_entries", &self.numberof_name_entries()) + .field("numberof_id_entries", &self.numberof_id_entries()) + .finish() + } +} + +impl<'a> FromFFI for Directory<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// This manager abstracts the tree representation to provide a comprehensive API over +/// the information wrapped by the resources tree. +pub struct Manager<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a Node<'a>>, +} + +impl<'a> FromFFI for Manager<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Types { + CURSOR, + BITMAP, + ICON, + MENU, + DIALOG, + STRING, + FONTDIR, + FONT, + ACCELERATOR, + RCDATA, + MESSAGETABLE, + GROUP_CURSOR, + GROUP_ICON, + VERSION, + DLGINCLUDE, + PLUGPLAY, + VXD, + ANICURSOR, + ANIICON, + HTML, + MANIFEST, + UNKNOWN(u32), +} + +impl From for Types { + fn from(value: u32) -> Self { + match value { + 0x00000001 => Types::CURSOR, + 0x00000002 => Types::BITMAP, + 0x00000003 => Types::ICON, + 0x00000004 => Types::MENU, + 0x00000005 => Types::DIALOG, + 0x00000006 => Types::STRING, + 0x00000007 => Types::FONTDIR, + 0x00000008 => Types::FONT, + 0x00000009 => Types::ACCELERATOR, + 0x0000000a => Types::RCDATA, + 0x0000000b => Types::MESSAGETABLE, + 0x0000000c => Types::GROUP_CURSOR, + 0x0000000e => Types::GROUP_ICON, + 0x00000010 => Types::VERSION, + 0x00000011 => Types::DLGINCLUDE, + 0x00000013 => Types::PLUGPLAY, + 0x00000014 => Types::VXD, + 0x00000015 => Types::ANICURSOR, + 0x00000016 => Types::ANIICON, + 0x00000017 => Types::HTML, + 0x00000018 => Types::MANIFEST, + _ => Types::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Types) -> u32 { + match value { + Types::CURSOR => 0x00000001, + Types::BITMAP => 0x00000002, + Types::ICON => 0x00000003, + Types::MENU => 0x00000004, + Types::DIALOG => 0x00000005, + Types::STRING => 0x00000006, + Types::FONTDIR => 0x00000007, + Types::FONT => 0x00000008, + Types::ACCELERATOR => 0x00000009, + Types::RCDATA => 0x0000000a, + Types::MESSAGETABLE => 0x0000000b, + Types::GROUP_CURSOR => 0x0000000c, + Types::GROUP_ICON => 0x0000000e, + Types::VERSION => 0x00000010, + Types::DLGINCLUDE => 0x00000011, + Types::PLUGPLAY => 0x00000013, + Types::VXD => 0x00000014, + Types::ANICURSOR => 0x00000015, + Types::ANIICON => 0x00000016, + Types::HTML => 0x00000017, + Types::MANIFEST => 0x00000018, + Types::UNKNOWN(value) => value, + } + } +} + +impl Manager<'_> { + /// Return the manifest as a string. This manifest matches the node associated with + /// the type: [`Types::MANIFEST`]. + pub fn manifest(&self) -> String { + self.ptr.manifest().to_string() + } + + /// Change or set the manifest. If the manifest node path does not exist, + /// all required nodes are created. + pub fn set_manifest(&mut self, content: &str) { + cxx::let_cxx_string!(__cxx_s = content); + self.ptr.pin_mut().set_manifest(&__cxx_s); + } + + /// Try to find the node associated with the given [`Types`] + /// + /// This type corresponds to the [`Node::id`] at the **level 1** of the + /// resource tree. + pub fn find_by_type(&self, res_type: Types) -> Option> { + into_optional(self.ptr.find_node_type(res_type.into())) + } + + /// Return the list of [`Types`] exposed by the resource tree. + pub fn types(&self) -> Vec { + self.ptr + .get_types() + .iter() + .map(|v| Types::from(*v)) + .collect() + } + + /// Return the HTML resources as a list of strings + pub fn html(&self) -> Vec { + self.ptr.html().iter().map(|s| s.to_string()).collect() + } + + /// Return an iterator over the resource icons + pub fn icons(&self) -> Icons<'_> { + Icons::new(self.ptr.icons()) + } + + /// Return an iterator over the resource version entries + pub fn version(&self) -> Versions<'_> { + Versions::new(self.ptr.version()) + } + + /// Return an iterator over the resource accelerator entries + pub fn accelerator(&self) -> Accelerators<'_> { + Accelerators::new(self.ptr.accelerator()) + } + + /// Return an iterator over the string table entries + pub fn string_table(&self) -> StringTableEntries<'_> { + StringTableEntries::new(self.ptr.string_table()) + } + + /// Print the current resources a tree in a pretty representation. + /// + /// ```text + /// │ ├── Directory ID: 0016 (0x0010) type: VERSION + /// │ │ └── Directory ID: 0001 (0x0001) + /// │ │ └── Data ID: 1033 (0x0409) [...] + /// │ │ ├── Hex: c0:03:34:00:00:00:[...] + /// │ │ └── Str: ..4...V.S._.V.E.R.S. + /// │ └── Directory ID: 0024 (0x0018) type: MANIFEST + /// │ └── Directory ID: 0001 (0x0001) + /// │ └── Data ID: 1033 (0x0409) [...] + /// │ ├── Hex: 3c:3f:78:6d:6c:20:[...] + /// │ └── Str: String { + self.ptr.print_tree().to_string() + } + + /// Same as [`Manager::print_tree`] but with a maximal depth provided in the + /// first parameter. + pub fn print_tree_with_depth(&self, depth: u32) -> String { + self.ptr.print_tree_with_depth(depth).to_string() + } +} + +/// Represents a PE icon resource +pub struct Icon<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourcesManager>, +} + +impl Icon<'_> { + /// ID of the icon + pub fn id(&self) -> u32 { + self.ptr.id() + } + + /// Language of the icon + pub fn lang(&self) -> u32 { + self.ptr.lang() + } + + /// Sublanguage of the icon + pub fn sublang(&self) -> u32 { + self.ptr.sublang() + } + + /// Width in pixels + pub fn width(&self) -> u8 { + self.ptr.width() + } + + /// Height in pixels + pub fn height(&self) -> u8 { + self.ptr.height() + } + + /// Number of colors in the palette (0 if more than 256) + pub fn color_count(&self) -> u8 { + self.ptr.color_count() + } + + /// Reserved (should be 0) + pub fn reserved(&self) -> u8 { + self.ptr.reserved() + } + + /// Number of color planes + pub fn planes(&self) -> u16 { + self.ptr.planes() + } + + /// Bits per pixel + pub fn bit_count(&self) -> u16 { + self.ptr.bit_count() + } + + /// Size of the icon pixel data + pub fn size(&self) -> u32 { + self.ptr.size() + } + + /// Raw pixel data of the icon + pub fn pixels(&self) -> &[u8] { + to_slice!(self.ptr.pixels()); + } +} + +impl fmt::Debug for Icon<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Icon") + .field("id", &self.id()) + .field("width", &self.width()) + .field("height", &self.height()) + .field("color_count", &self.color_count()) + .field("bit_count", &self.bit_count()) + .finish() + } +} + +impl<'a> FromFFI for Icon<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents fixed file information from a version resource +#[derive(Debug, Clone)] +pub struct FixedFileInfo { + /// Contains the value `0xFEEF04BD`. This is used with the `szKey` member of + /// the `VS_VERSIONINFO` structure when searching a file for the + /// `VS_FIXEDFILEINFO` structure. + pub signature: u32, + + /// The binary version number of this structure. The high-order word of + /// this member contains the major version number, and the low-order word + /// contains the minor version number. + pub struct_version: u32, + + /// The most significant 32 bits of the file's binary version number. + /// This member is used with file_version_ls to form a 64-bit value used + /// for numeric comparisons. + pub file_version_ms: u32, + + /// The least significant 32 bits of the file's binary version number. + /// This member is used with file_version_ms to form a 64-bit value used for + /// numeric comparisons. + pub file_version_ls: u32, + + /// The most significant 32 bits of the binary version number of the product + /// with which this file was distributed. This member is used with + /// product_version_ls to form a 64-bit value used for numeric comparisons. + pub product_version_ms: u32, + + /// The least significant 32 bits of the binary version number of the product + /// with which this file was distributed. This member is used with + /// product_version_ms to form a 64-bit value used for numeric comparisons. + pub product_version_ls: u32, + + /// Contains a bitmask that specifies the valid bits in file_flags. + /// A bit is valid only if it was defined when the file was created. + pub file_flags_mask: u32, + + /// Contains a bitmask that specifies the Boolean attributes of the file. + /// This member can include one or more of the values specified in FILE_FLAGS + pub file_flags: u32, + + /// The operating system for which this file was designed. This member can + /// be one of the values specified in VERSION_OS. + pub file_os: u32, + + /// The general type of file. This member can be one of the values specified + /// in FILE_TYPE. All other values are reserved. + pub file_type: u32, + + /// The function of the file. The possible values depend on the value of + /// file_type. + pub file_subtype: u32, + + /// The most significant 32 bits of the file's 64-bit binary creation date + /// and time stamp. + pub file_date_ms: u32, + + /// The least significant 32 bits of the file's 64-bit binary creation date + /// and time stamp. + pub file_date_ls: u32, +} + +/// Represents a string table entry (key/value) from a StringFileInfo +#[derive(Debug, Clone)] +pub struct VersionStringTableEntry { + /// Key of the entry + pub key: String, + /// Value of the entry + pub value: String, +} + +impl FromFFI for VersionStringTableEntry { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + key: ptr.key().to_string(), + value: ptr.value().to_string(), + } + } +} + +/// Represents a string table within a StringFileInfo +pub struct VersionStringTable<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourceVersion>, +} + +impl VersionStringTable<'_> { + /// Type of the string table + pub fn get_type(&self) -> u16 { + self.ptr.get_type() + } + + /// Key identifying the string table (typically a language/codepage pair) + pub fn key(&self) -> String { + self.ptr.key().to_string() + } + + /// Return an iterator over the key/value entries + pub fn entries(&self) -> VersionStringTableEntries<'_> { + VersionStringTableEntries::new(self.ptr.entries()) + } +} + +impl fmt::Debug for VersionStringTable<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("VersionStringTable") + .field("key", &self.key()) + .finish() + } +} + +impl<'a> FromFFI for VersionStringTable<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a Var entry within VarFileInfo +pub struct ResourceVar<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourceVersion>, +} + +impl ResourceVar<'_> { + /// Type of the var entry + pub fn get_type(&self) -> u16 { + self.ptr.get_type() + } + + /// Key of the var entry + pub fn key(&self) -> String { + self.ptr.key().to_string() + } + + /// Values of the var entry (language/codepage pairs) + pub fn values(&self) -> Vec { + self.ptr.values().iter().map(|&v| v as u32).collect() + } +} + +impl fmt::Debug for ResourceVar<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("ResourceVar") + .field("key", &self.key()) + .field("values", &self.values()) + .finish() + } +} + +impl<'a> FromFFI for ResourceVar<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a StringFileInfo structure from a version resource +pub struct StringFileInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourceVersion>, +} + +impl StringFileInfo<'_> { + /// Type of the StringFileInfo + pub fn get_type(&self) -> u16 { + self.ptr.get_type() + } + + /// Key of the StringFileInfo + pub fn key(&self) -> String { + self.ptr.key().to_string() + } + + /// Return an iterator over the child string tables + pub fn children(&self) -> StringFileInfoChildren<'_> { + StringFileInfoChildren::new(self.ptr.children()) + } +} + +impl fmt::Debug for StringFileInfo<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("StringFileInfo") + .field("key", &self.key()) + .finish() + } +} + +impl<'a> FromFFI for StringFileInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a VarFileInfo structure from a version resource +pub struct VarFileInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourceVersion>, +} + +impl VarFileInfo<'_> { + /// Type of the VarFileInfo + pub fn get_type(&self) -> u16 { + self.ptr.get_type() + } + + /// Key of the VarFileInfo + pub fn key(&self) -> String { + self.ptr.key().to_string() + } + + /// Return an iterator over the Var entries + pub fn vars(&self) -> VarFileInfoVars<'_> { + VarFileInfoVars::new(self.ptr.vars()) + } +} + +impl fmt::Debug for VarFileInfo<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("VarFileInfo") + .field("key", &self.key()) + .finish() + } +} + +impl<'a> FromFFI for VarFileInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a PE version resource +pub struct Version<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourcesManager>, +} + +impl Version<'_> { + /// Type of the version resource + pub fn get_type(&self) -> u16 { + self.ptr.get_type() + } + + /// Key of the version resource + pub fn key(&self) -> String { + self.ptr.key().to_string() + } + + /// Return the fixed file information if present + pub fn file_info(&self) -> FixedFileInfo { + FixedFileInfo { + signature: self.ptr.file_info_signature(), + struct_version: self.ptr.file_info_struct_version(), + file_version_ms: self.ptr.file_info_file_version_ms(), + file_version_ls: self.ptr.file_info_file_version_ls(), + product_version_ms: self.ptr.file_info_product_version_ms(), + product_version_ls: self.ptr.file_info_product_version_ls(), + file_flags_mask: self.ptr.file_info_file_flags_mask(), + file_flags: self.ptr.file_info_file_flags(), + file_os: self.ptr.file_info_file_os(), + file_type: self.ptr.file_info_file_type(), + file_subtype: self.ptr.file_info_file_subtype(), + file_date_ms: self.ptr.file_info_file_date_ms(), + file_date_ls: self.ptr.file_info_file_date_ls(), + } + } + + /// Return the StringFileInfo if present + pub fn string_file_info(&self) -> Option> { + into_optional(self.ptr.string_file_info()) + } + + /// Return the VarFileInfo if present + pub fn var_file_info(&self) -> Option> { + into_optional(self.ptr.var_file_info()) + } +} + +impl fmt::Debug for Version<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Version").field("key", &self.key()).finish() + } +} + +impl<'a> FromFFI for Version<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a PE accelerator resource entry +pub struct Accelerator<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourcesManager>, +} + +impl Accelerator<'_> { + /// Flags for the accelerator + pub fn flags(&self) -> i16 { + self.ptr.flags() + } + + /// ANSI code of the accelerator key + pub fn ansi(&self) -> i16 { + self.ptr.ansi() + } + + /// ID of the accelerator + pub fn id(&self) -> u16 { + self.ptr.id() + } + + /// Padding value + pub fn padding(&self) -> i16 { + self.ptr.padding() + } + + /// Return the ANSI string representation of the accelerator key + pub fn ansi_str(&self) -> String { + self.ptr.ansi_str().to_string() + } +} + +impl fmt::Debug for Accelerator<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Accelerator") + .field("id", &self.id()) + .field("flags", &self.flags()) + .field("ansi", &self.ansi()) + .finish() + } +} + +impl<'a> FromFFI for Accelerator<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Represents a string table entry from the ResourcesManager +pub struct StringEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ResourcesManager>, +} + +impl StringEntry<'_> { + /// The string value + pub fn string(&self) -> String { + self.ptr.string().to_string() + } + + /// The ID associated with this string + pub fn id(&self) -> u32 { + self.ptr.id() + } +} + +impl fmt::Debug for StringEntry<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("StringEntry") + .field("id", &self.id()) + .field("string", &self.string()) + .finish() + } +} + +impl<'a> FromFFI for StringEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + Children, + Node<'a>, + ffi::PE_ResourceNode, + ffi::PE_Binary, + ffi::PE_ResourceNode_it_childs +); + +declare_iterator!( + Icons, + Icon<'a>, + ffi::PE_ResourceIcon, + ffi::PE_ResourcesManager, + ffi::PE_ResourcesManager_it_icons +); + +declare_iterator!( + Versions, + Version<'a>, + ffi::PE_ResourceVersion, + ffi::PE_ResourcesManager, + ffi::PE_ResourcesManager_it_version +); + +declare_iterator!( + Accelerators, + Accelerator<'a>, + ffi::PE_ResourceAccelerator, + ffi::PE_ResourcesManager, + ffi::PE_ResourcesManager_it_accelerator +); + +declare_iterator!( + StringTableEntries, + StringEntry<'a>, + ffi::PE_ResourcesManager_string_entry_t, + ffi::PE_ResourcesManager, + ffi::PE_ResourcesManager_it_string_table_entry +); + +declare_iterator!( + VersionStringTableEntries, + VersionStringTableEntry, + ffi::PE_ResourceStringTable_entry_t, + ffi::PE_ResourceStringTable, + ffi::PE_ResourceStringTable_it_entries +); + +declare_iterator!( + StringFileInfoChildren, + VersionStringTable<'a>, + ffi::PE_ResourceStringTable, + ffi::PE_ResourceStringFileInfo, + ffi::PE_ResourceStringFileInfo_it_children +); + +declare_iterator!( + VarFileInfoVars, + ResourceVar<'a>, + ffi::PE_ResourceVar, + ffi::PE_ResourceVarFileInfo, + ffi::PE_ResourceVarFileInfo_it_vars +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/rich_header.rs b/vendor/lief/api/rust/crates/lief/src/pe/rich_header.rs new file mode 100644 index 0000000..9da9926 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/rich_header.rs @@ -0,0 +1,105 @@ +//! PE Rich Header module +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::{common::FromFFI, declare_iterator}; + +/// Structure which represents the not-so-documented rich header +/// +/// This structure is usually located at the end of the [`crate::pe::Binary::dos_stub`] +/// and contains information about the build environment. +/// It is generated by the Microsoft linker `link.exe` and there are no options to disable +/// or remove this information. +pub struct RichHeader<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl std::fmt::Debug for RichHeader<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RichHeader") + .field("key", &self.key()) + .finish() + } +} + +impl<'a> FromFFI for RichHeader<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + RichHeader { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> RichHeader<'a> { + /// Key used to encode the header (xor operation) + pub fn key(&self) -> u32 { + self.ptr.key() + } + + /// Return the raw bytes of the Rich header (decoded, without xor-encoding) + pub fn raw(&self) -> Vec { + Vec::from(self.ptr.raw().as_slice()) + } + + /// Return the raw bytes of the Rich header XOR-ed with the given key + pub fn raw_with_key(&self, xor_key: u32) -> Vec { + Vec::from(self.ptr.raw_with_key(xor_key).as_slice()) + } + + /// Return an iterator over the [`RichEntry`] within the header + pub fn entries(&self) -> Entries<'_> { + Entries::new(self.ptr.entries()) + } +} + +pub struct RichEntry<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_RichHeader>, +} + +impl RichEntry<'_> { + /// Entry type + pub fn id(&self) -> u16 { + self.ptr.id() + } + + /// Build number of the tool (if any) + pub fn build_id(&self) -> u16 { + self.ptr.build_id() + } + + /// *Occurrence* count. + pub fn count(&self) -> u32 { + self.ptr.count() + } +} + +impl std::fmt::Debug for RichEntry<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RichEntry") + .field("id", &self.id()) + .field("build_id", &self.build_id()) + .field("count", &self.count()) + .finish() + } +} + +impl<'a> FromFFI for RichEntry<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + RichEntry { + ptr, + _owner: PhantomData, + } + } +} + +declare_iterator!( + Entries, + RichEntry<'a>, + ffi::PE_RichEntry, + ffi::PE_RichHeader, + ffi::PE_RichHeader_it_entries +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/section.rs b/vendor/lief/api/rust/crates/lief/src/pe/section.rs new file mode 100644 index 0000000..1ce6afe --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/section.rs @@ -0,0 +1,240 @@ +//! PE section module + +use std::marker::PhantomData; + +use crate::coff; +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::declare_iterator; +use crate::generic; +use crate::to_slice; +use bitflags::bitflags; +use lief_ffi as ffi; +use std::pin::Pin; + +/// This structure defines a regular PE section. +/// +/// Note that it implements the trait [`generic::Section`] which provides additional +/// functions. +pub struct Section<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Characteristics: u32 { + const TYPE_NO_PAD = 0x8; + const CNT_CODE = 0x20; + const CNT_INITIALIZED_DATA = 0x40; + const CNT_UNINITIALIZED_DATA = 0x80; + const LNK_OTHER = 0x100; + const LNK_INFO = 0x200; + const LNK_REMOVE = 0x800; + const LNK_COMDAT = 0x1000; + const GPREL = 0x8000; + const MEM_PURGEABLE = 0x10000; + const MEM_16BIT = 0x20000; + const MEM_LOCKED = 0x40000; + const MEM_PRELOAD = 0x80000; + const ALIGN_1BYTES = 0x100000; + const ALIGN_2BYTES = 0x200000; + const ALIGN_4BYTES = 0x300000; + const ALIGN_8BYTES = 0x400000; + const ALIGN_16BYTES = 0x500000; + const ALIGN_32BYTES = 0x600000; + const ALIGN_64BYTES = 0x700000; + const ALIGN_128BYTES = 0x800000; + const ALIGN_256BYTES = 0x900000; + const ALIGN_512BYTES = 0xa00000; + const ALIGN_1024BYTES = 0xb00000; + const ALIGN_2048BYTES = 0xc00000; + const ALIGN_4096BYTES = 0xd00000; + const ALIGN_8192BYTES = 0xe00000; + const LNK_NRELOC_OVFL = 0x1000000; + const MEM_DISCARDABLE = 0x2000000; + const MEM_NOT_CACHED = 0x4000000; + const MEM_NOT_PAGED = 0x8000000; + const MEM_SHARED = 0x10000000; + const MEM_EXECUTE = 0x20000000; + const MEM_READ = 0x40000000; + const MEM_WRITE = 0x80000000; + } +} + +impl From for Characteristics { + fn from(value: u32) -> Self { + Characteristics::from_bits_truncate(value) + } +} +impl From for u32 { + fn from(value: Characteristics) -> Self { + value.bits() + } +} +impl std::fmt::Display for Characteristics { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl Section<'_> { + /// Create a new Section + pub fn new() -> Section<'static> { + Section::from_ffi(lief_ffi::PE_Section::create()) + } + + /// Create a new Section with the given name + pub fn new_with_name(name: &str) -> Section<'static> { + cxx::let_cxx_string!(__cxx_s = name.to_string()); + Section::from_ffi(lief_ffi::PE_Section::create_with_name(&__cxx_s)) + } + + /// Create a new Section with the given name and content + pub fn new_with_content(name: &str, content: &[u8]) -> Section<'static> { + cxx::let_cxx_string!(__cxx_name = name); + unsafe { + Section::from_ffi(lief_ffi::PE_Section::create_with_content( + &__cxx_name, + content.as_ptr(), + content.len(), + )) + } + } + + /// Return the size of the data in the section. + pub fn sizeof_raw_data(&self) -> u32 { + self.ptr.sizeof_raw_data() + } + + /// Return the size of the data when mapped in memory + /// + /// If this value is greater than [`Section::sizeof_raw_data`], the section is zero-padded. + pub fn virtual_size(&self) -> u32 { + self.ptr.virtual_size() + } + + /// The offset of the section data in the PE file + pub fn pointerto_raw_data(&self) -> u32 { + self.ptr.pointerto_raw_data() + } + + /// The file pointer to the beginning of the COFF relocation entries for the section. + /// This is set to zero for executable images or if there are no relocations. + /// + /// For modern PE binaries, this value is usually set to 0 as the relocations are managed by + /// [`crate::pe::Relocation`]. + pub fn pointerto_relocation(&self) -> u32 { + self.ptr.pointerto_relocation() + } + + /// The file pointer to the beginning of line-number entries for the section. + /// This is set to zero if there are no COFF line numbers. This value should be zero for an + /// image because COFF debugging information is deprecated and modern debug information relies + /// on the PDB files. + pub fn pointerto_line_numbers(&self) -> u32 { + self.ptr.pointerto_line_numbers() + } + + /// No longer used in recent PE binaries produced by Visual Studio + pub fn numberof_relocations(&self) -> u16 { + self.ptr.numberof_relocations() + } + + /// No longer used in recent PE binaries produced by Visual Studio + pub fn numberof_line_numbers(&self) -> u16 { + self.ptr.numberof_line_numbers() + } + + /// Characteristics of the section: it provides information about + /// the permissions of the section when mapped. It can also provide + /// information about the *purpose* of the section (contain code, BSS-like, ...) + pub fn characteristics(&self) -> Characteristics { + Characteristics::from(self.ptr.characteristics()) + } + + /// Content of the section's padding area + pub fn padding(&self) -> &[u8] { + to_slice!(self.ptr.padding()); + } + + /// True if the section can be discarded as needed. + /// + /// This is typically the case for debug-related sections + pub fn is_discardable(&self) -> bool { + self.ptr.is_discardable() + } + + /// Return the COFF string associated with the section's name (or a None) + /// + /// This coff string is usually present for long section names whose length + /// does not fit in the 8 bytes allocated by the PE format. + pub fn coff_string(&self) -> Option> { + into_optional(self.ptr.coff_string()) + } + + /// Set the virtual size of the section + pub fn set_virtual_size(&mut self, virtual_size: u32) { + self.ptr.pin_mut().set_virtual_size(virtual_size); + } +} + +impl std::fmt::Debug for Section<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + let base = self as &dyn generic::Section; + f.debug_struct("Section") + .field("base", &base) + .field("sizeof_raw_data", &self.sizeof_raw_data()) + .field("virtual_size", &self.virtual_size()) + .field("pointerto_raw_data", &self.pointerto_raw_data()) + .field("pointerto_relocation", &self.pointerto_relocation()) + .field("pointerto_line_numbers", &self.pointerto_line_numbers()) + .field("numberof_relocations", &self.numberof_relocations()) + .field("numberof_line_numbers", &self.numberof_line_numbers()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +impl<'a> FromFFI for Section<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Section { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> AsFFI for Section<'a> { + fn as_ffi(&self) -> &ffi::PE_Section { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::PE_Section> { + self.ptr.pin_mut() + } +} + +impl generic::Section for Section<'_> { + fn as_generic(&self) -> &ffi::AbstractSection { + self.ptr.as_ref().unwrap().as_ref() + } + + fn as_generic_mut(&mut self) -> Pin<&mut ffi::AbstractSection> { + unsafe { + Pin::new_unchecked({ + (self.ptr.as_ref().unwrap().as_ref() as *const ffi::AbstractSection + as *mut ffi::AbstractSection) + .as_mut() + .unwrap() + }) + } + } +} + +declare_iterator!( + Sections, + Section<'a>, + ffi::PE_Section, + ffi::PE_Binary, + ffi::PE_Binary_it_sections +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature.rs new file mode 100644 index 0000000..5477da1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature.rs @@ -0,0 +1,262 @@ +//! This module wraps the PKCS #7 PE authenticode signature + +use bitflags::bitflags; +use lief_ffi as ffi; + +pub mod attributes; +pub mod content_info; +pub mod rsa_info; +pub mod signer_info; +pub mod x509; + +#[doc(inline)] +pub use content_info::ContentInfo; +#[doc(inline)] +pub use rsa_info::RsaInfo; +#[doc(inline)] +pub use signer_info::{AttributeType, SignerInfo, Signers}; +#[doc(inline)] +pub use x509::{Certificates, KeyUsage, VerificationFlags as CertVerificationFlags, X509}; + +use std::io::{Read, Seek}; + +use crate::common::FromFFI; +use crate::common::into_optional; +use crate::declare_iterator; +use crate::pe::Algorithms; +use crate::to_slice; + +use std::marker::PhantomData; + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct VerificationFlags: u32 { + const OK = 0; + const INVALID_SIGNER = 1 << 0; + const UNSUPPORTED_ALGORITHM = 1 << 1; + const INCONSISTENT_DIGEST_ALGORITHM = 1 << 2; + const CERT_NOT_FOUND = 1 << 3; + const CORRUPTED_CONTENT_INFO = 1 << 4; + const CORRUPTED_AUTH_DATA = 1 << 5; + const MISSING_PKCS9_MESSAGE_DIGEST = 1 << 6; + const BAD_DIGEST = 1 << 7; + const BAD_SIGNATURE = 1 << 8; + const NO_SIGNATURE = 1 << 9; + const CERT_EXPIRED = 1 << 10; + const CERT_FUTURE = 1 << 11; + } +} + +impl std::fmt::Display for VerificationFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl From for VerificationFlags { + fn from(value: u32) -> Self { + VerificationFlags::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: VerificationFlags) -> Self { + value.bits() + } +} + +impl VerificationFlags { + pub fn is_ok(self) -> bool { + self == VerificationFlags::OK + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + /// Flags to tweak the verification process of the signature + /// + /// See [`Signature::check`] and [`crate::pe::Binary::verify_signature`] + pub struct VerificationChecks: u32 { + /// Default behavior that tries to follow the Microsoft verification process as close as + /// possible + const DEFAULT = 1 << 0; + + /// Only check that [`crate::pe::Binary::authentihash`] matches + /// [`ContentInfo::digest`] regardless of the signature's validity + const HASH_ONLY = 1 << 1; + + /// Same semantic as + /// [WTD_LIFETIME_SIGNING_FLAG](https://docs.microsoft.com/en-us/windows/win32/api/wintrust/ns-wintrust-wintrust_data#WTD_LIFETIME_SIGNING_FLAG) + const LIFETIME_SIGNING = 1 << 2; + + /// Skip the verification of the certificates time validities so that even though a + /// certificate expired, it returns [`VerificationFlags::OK`] + const SKIP_CERT_TIME = 1 << 3; + } +} + +impl From for VerificationChecks { + fn from(value: u32) -> Self { + VerificationChecks::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: VerificationChecks) -> Self { + value.bits() + } +} + +pub struct Signature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl<'b, 'a: 'b> From<&'a Signature<'_>> for &'b ffi::PE_Signature { + fn from(value: &'a Signature<'_>) -> &'b ffi::PE_Signature { + value.ptr.as_ref().unwrap() + } +} + +impl std::fmt::Debug for Signature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Signature").finish() + } +} + +impl FromFFI for Signature<'_> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Signature { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> Signature<'a> { + /// Create a Signature from a PKCS#7 file path + pub fn from_file(path: &str) -> Option { + cxx::let_cxx_string!(__cxx_s = path); + let ffi = ffi::PE_Signature::parse(&__cxx_s); + if ffi.is_null() { + return None; + } + Some(Signature::from_ffi(ffi)) + } + + /// Create a Signature from a PKCS#7 *reader* implementing the `Read + Seek` traits + pub fn from(reader: &mut R) -> Option { + let mut buffer = std::vec::Vec::new(); + if reader.read_to_end(&mut buffer).is_err() { + return None; + } + let ffi_stream = unsafe { ffi::PE_Signature::from_raw(buffer.as_mut_ptr(), buffer.len()) }; + Some(Signature::from_ffi(ffi_stream)) + } + + /// Should be 1 + pub fn version(&self) -> u32 { + self.ptr.version() + } + + /// Algorithm used to *digest* the file. + /// + /// It should match [`SignerInfo::digest_algorithm`] + pub fn digest_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.digest_algorithm()) + } + + /// ContentInfo as described in the RFC2315 + pub fn content_info(&'a self) -> ContentInfo<'a> { + ContentInfo::from_ffi(self.ptr.content_info()) + } + + /// Return list of [`X509`] certificates associated with this signature + pub fn certificates(&'a self) -> Certificates<'a> { + Certificates::new(self.ptr.certificates()) + } + + /// Iterator over the signer [`SignerInfo`] defined in the PKCS #7 signature + pub fn signers(&'a self) -> Signers<'a> { + Signers::new(self.ptr.signers()) + } + + /// The original raw signature as a slice of bytes + pub fn raw_der(&self) -> &[u8] { + to_slice!(self.ptr.raw_der()); + } + + /// Find x509 certificate according to its serial number + pub fn crt_by_serial(&self, serial: &[u8]) -> Option> { + unsafe { into_optional(self.ptr.find_crt_by_serial(serial.as_ptr(), serial.len())) } + } + + /// Find [`X509`] certificate according to its subject + pub fn crt_by_subject(&self, subject: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = subject); + into_optional(self.ptr.find_crt_by_subject(&__cxx_s)) + } + + /// Find [`X509`] certificate according to its subject **AND** serial number + pub fn crt_by_subject_and_serial(&self, subject: &str, serial: &[u8]) -> Option> { + cxx::let_cxx_string!(__cxx_s = subject); + unsafe { + into_optional(self.ptr.find_crt_by_subject_and_serial( + &__cxx_s, + serial.as_ptr(), + serial.len(), + )) + } + } + + /// Find [`X509`] certificate according to its issuer + pub fn crt_by_issuer(&self, issuer: &str) -> Option> { + cxx::let_cxx_string!(__cxx_s = issuer); + into_optional(self.ptr.find_crt_by_issuer(&__cxx_s)) + } + + /// Find [`X509`] certificate according to its issuer **AND** serial number + pub fn find_crt_by_issuer_and_serial(&self, issuer: &str, serial: &[u8]) -> Option> { + cxx::let_cxx_string!(__cxx_s = issuer); + unsafe { + into_optional(self.ptr.find_crt_by_issuer_and_serial( + &__cxx_s, + serial.as_ptr(), + serial.len(), + )) + } + } + + /// Check if this signature is valid according to the Authenticode/PKCS #7 verification scheme + /// + /// By default, it performs the following verifications: + /// + /// 1. It must contain only **one** signer info + /// 2. [`Signature::digest_algorithm`] must match: + /// * [`ContentInfo::digest_algorithm`] + /// * [`SignerInfo::digest_algorithm`] + /// 3. The x509 certificate specified by [`SignerInfo::serial_number`] **and** [`SignerInfo::issuer`] + /// must exist within [`Signature::certificates`] + /// 4. Given the x509 certificate, compare [`SignerInfo::encrypted_digest`] against either: + /// * hash of authenticated attributes if present + /// * hash of ContentInfo + /// 5. If authenticated attributes are present, check that a `PKCS9_MESSAGE_DIGEST` attribute exists + /// and that its value matches hash of ContentInfo + /// 6. Check the validity of the PKCS #9 counter signature if present + /// 7. If the signature doesn't embed a signing-time in the counter signature, check the certificate + /// validity. + /// (See [`VerificationChecks::LIFETIME_SIGNING`] and [`VerificationChecks::SKIP_CERT_TIME`]) + /// + /// See: [`VerificationChecks`] to tweak the behavior + pub fn check(&self, checks: VerificationChecks) -> VerificationFlags { + VerificationFlags::from(self.ptr.check(checks.into())) + } +} + +declare_iterator!( + Signatures, + Signature<'a>, + ffi::PE_Signature, + ffi::PE_Binary, + ffi::PE_Binary_it_signatures +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature/attributes.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature/attributes.rs new file mode 100644 index 0000000..c6f065b --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature/attributes.rs @@ -0,0 +1,682 @@ +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_iterator; +use crate::pe::Algorithms; +use crate::pe::signature::ContentInfo; +use crate::pe::signature::X509; +use crate::to_slice; + +use super::{Signature, SignerInfo}; + +#[derive(Debug)] +/// This enum exposes the different attributes that can be wrapped in +/// a [`crate::pe::signature::SignerInfo`] +pub enum Attribute<'a> { + /// Attribute for the OID: `1.2.840.113549.1.9.3` + ContentType(ContentType<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.2.4.1` + MsSpcNestedSignature(MsSpcNestedSignature<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.2.1.11` + MsSpcStatementType(MsSpcStatementType<'a>), + /// Attribute for the OID: `1.2.840.113549.1.9.25.4` + PKCS9AtSequenceNumber(PKCS9AtSequenceNumber<'a>), + /// Attribute for the OID: `1.2.840.113549.1.9.6` + PKCS9CounterSignature(PKCS9CounterSignature<'a>), + /// Attribute for the OID: `1.2.840.113549.1.9.4` + PKCS9MessageDigest(PKCS9MessageDigest<'a>), + /// Attribute for the OID: `1.2.840.113549.1.9.5` + PKCS9SigningTime(PKCS9SigningTime<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.2.1.12` + SpcSpOpusInfo(SpcSpOpusInfo<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.10.3.28` + MsManifestBinaryID(MsManifestBinaryID<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.3.3.1` + MsCounterSign(MsCounterSign<'a>), + /// Attribute for the OID: `1.2.840.113549.1.9.16.2.47` + SigningCertificateV2(SigningCertificateV2<'a>), + /// Attribute for the OID: `1.3.6.1.4.1.311.2.6.1` + SpcRelaxedPeMarkerCheck(SpcRelaxedPeMarkerCheck<'a>), + /// Attribute for an OID not supported by LIEF + GenericType(GenericType<'a>), +} + +impl<'a> FromFFI for Attribute<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let cmd_ref = ffi_entry.as_ref().unwrap(); + + if ffi::PE_ContentType::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::ContentType(ContentType::from_ffi(raw)) + } else if ffi::PE_MsSpcNestedSignature::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::MsSpcNestedSignature(MsSpcNestedSignature::from_ffi(raw)) + } else if ffi::PE_MsSpcStatementType::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::MsSpcStatementType(MsSpcStatementType::from_ffi(raw)) + } else if ffi::PE_PKCS9AtSequenceNumber::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::PKCS9AtSequenceNumber(PKCS9AtSequenceNumber::from_ffi(raw)) + } else if ffi::PE_PKCS9CounterSignature::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::PKCS9CounterSignature(PKCS9CounterSignature::from_ffi(raw)) + } else if ffi::PE_PKCS9MessageDigest::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::PKCS9MessageDigest(PKCS9MessageDigest::from_ffi(raw)) + } else if ffi::PE_PKCS9SigningTime::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::PKCS9SigningTime(PKCS9SigningTime::from_ffi(raw)) + } else if ffi::PE_SpcSpOpusInfo::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::SpcSpOpusInfo(SpcSpOpusInfo::from_ffi(raw)) + } else if ffi::PE_MsManifestBinaryID::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::MsManifestBinaryID(MsManifestBinaryID::from_ffi(raw)) + } else if ffi::PE_MsCounterSign::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::MsCounterSign(MsCounterSign::from_ffi(raw)) + } else if ffi::PE_SpcRelaxedPeMarkerCheck::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::SpcRelaxedPeMarkerCheck(SpcRelaxedPeMarkerCheck::from_ffi(raw)) + } else if ffi::PE_SigningCertificateV2::classof(cmd_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::SigningCertificateV2(SigningCertificateV2::from_ffi(raw)) + } else { + assert!( + ffi::PE_GenericType::classof(cmd_ref), + "Must be a GenericType node" + ); + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Attribute::GenericType(GenericType::from_ffi(raw)) + } + } + } +} +/// Interface over the structure described by the OID ``1.2.840.113549.1.9.3`` (PKCS #9) +/// +/// The internal structure is described in the RFC #2985 +/// +/// ```text +/// ContentType ::= OBJECT IDENTIFIER +/// ``` +pub struct ContentType<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for ContentType<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("ContentType") + .field("oid", &self.oid()) + .finish() + } +} + +impl<'a> FromFFI for ContentType<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl ContentType<'_> { + /// OID as described in RFC #2985 + pub fn oid(&self) -> String { + self.ptr.oid().to_string() + } +} + +/// Interface over an attribute for which the internal structure is not supported by LIEF +pub struct GenericType<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for GenericType<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("GenericType") + .field("oid", &self.oid()) + .finish() + } +} + +impl<'a> FromFFI for GenericType<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl GenericType<'_> { + /// OID of the original attribute + pub fn oid(&self) -> String { + self.ptr.oid().to_string() + } + + /// Original DER blob of the attribute + pub fn raw_content(&self) -> &[u8] { + to_slice!(self.ptr.raw_content()); + } +} + +/// Interface over the structure described by the OID `1.3.6.1.4.1.311.2.4.1` +/// +/// The internal structure is not documented but we can infer the following structure: +/// +/// ```text +/// MsSpcNestedSignature ::= SET OF SignedData +/// ``` +/// +/// `SignedData` is the structure described in PKCS #7 RFC +pub struct MsSpcNestedSignature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for MsSpcNestedSignature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MsSpcNestedSignature").finish() + } +} + +impl<'a> FromFFI for MsSpcNestedSignature<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl MsSpcNestedSignature<'_> { + /// Underlying Signature object + pub fn signature(&self) -> Signature<'_> { + Signature::from_ffi(self.ptr.sig()) + } +} + +/// Interface over the structure described by the OID `1.3.6.1.4.1.311.2.1.11` +/// +/// The internal structure is described in the official document: +/// *Windows Authenticode Portable Executable Signature Format* +/// +/// ```text +/// SpcStatementType ::= SEQUENCE of OBJECT IDENTIFIER +/// ``` +pub struct MsSpcStatementType<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for MsSpcStatementType<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MsSpcStatementType") + .field("oid", &self.oid()) + .finish() + } +} + +impl<'a> FromFFI for MsSpcStatementType<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl MsSpcStatementType<'_> { + /// According to the documentation: + /// > The SpcStatementType MUST contain one Object Identifier with either + /// > the value `1.3.6.1.4.1.311.2.1.21 (SPC_INDIVIDUAL_SP_KEY_PURPOSE_OBJID)` or + /// > `1.3.6.1.4.1.311.2.1.22 (SPC_COMMERCIAL_SP_KEY_PURPOSE_OBJID)`. + pub fn oid(&self) -> String { + self.ptr.oid().to_string() + } +} + +/// Interface over the structure described by the OID `1.2.840.113549.1.9.25.4` (PKCS #9) +/// +/// The internal structure is described in the +/// RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 +/// +/// ```text +/// sequenceNumber ATTRIBUTE ::= { +/// WITH SYNTAX SequenceNumber +/// EQUALITY MATCHING RULE integerMatch +/// SINGLE VALUE TRUE +/// ID pkcs-9-at-sequenceNumber +/// } +/// +/// SequenceNumber ::= INTEGER (1..MAX) +/// ``` +pub struct PKCS9AtSequenceNumber<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for PKCS9AtSequenceNumber<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PKCS9AtSequenceNumber") + .field("number", &self.number()) + .finish() + } +} + +impl PKCS9AtSequenceNumber<'_> { + //! Number as described in the RFC + pub fn number(&self) -> u32 { + self.ptr.number() + } +} + +impl<'a> FromFFI for PKCS9AtSequenceNumber<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Interface over the structure described by the OID `1.2.840.113549.1.9.6` (PKCS #9) +/// +/// The internal structure is described in the +/// RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 +/// +/// ```text +/// counterSignature ATTRIBUTE ::= { +/// WITH SYNTAX SignerInfo +/// ID pkcs-9-at-counterSignature +/// } +/// ``` +pub struct PKCS9CounterSignature<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for PKCS9CounterSignature<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PKCS9CounterSignature").finish() + } +} + +impl<'a> FromFFI for PKCS9CounterSignature<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl PKCS9CounterSignature<'_> { + /// SignerInfo as described in the RFC #2985 + pub fn signer(&self) -> SignerInfo<'_> { + SignerInfo::from_ffi(self.ptr.signer()) + } +} + +/// Interface over the structure described by the OID `1.2.840.113549.1.9.4` (PKCS #9) +/// +/// The internal structure is described in the +/// RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 +/// +/// ```text +/// messageDigest ATTRIBUTE ::= { +/// WITH SYNTAX MessageDigest +/// EQUALITY MATCHING RULE octetStringMatch +/// SINGLE VALUE TRUE +/// ID pkcs-9-at-messageDigest +/// } +/// +/// MessageDigest ::= OCTET STRING +/// ``` +pub struct PKCS9MessageDigest<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for PKCS9MessageDigest<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PKCS9MessageDigest").finish() + } +} + +impl PKCS9MessageDigest<'_> { + /// Message digeset as a blob of bytes as described in the RFC + pub fn digest(&self) -> &[u8] { + to_slice!(self.ptr.digest()); + } +} + +impl<'a> FromFFI for PKCS9MessageDigest<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +/// Interface over the structure described by the OID `1.2.840.113549.1.9.5` (PKCS #9) +/// +/// The internal structure is described in the +/// RFC #2985: PKCS #9 - Selected Object Classes and Attribute Types Version 2.0 +/// +/// ```text +/// signingTime ATTRIBUTE ::= { +/// WITH SYNTAX SigningTime +/// EQUALITY MATCHING RULE signingTimeMatch +/// SINGLE VALUE TRUE +/// ID pkcs-9-at-signingTime +/// } +/// +/// SigningTime ::= Time -- imported from ISO/IEC 9594-8 +/// ``` +pub struct PKCS9SigningTime<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for PKCS9SigningTime<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PKCS9SigningTime") + .field("time", &self.time()) + .finish() + } +} + +impl<'a> FromFFI for PKCS9SigningTime<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl PKCS9SigningTime<'_> { + /// Time as a tuple: `(year, month, day, hour, min, sec)` + pub fn time(&self) -> (u64, u64, u64, u64, u64, u64) { + let vec = Vec::from(self.ptr.time().as_slice()); + if vec.len() != 6 { + return (0, 0, 0, 0, 0, 0); + } + (vec[0], vec[1], vec[2], vec[3], vec[4], vec[5]) + } +} + +/// Interface over the structure described by the OID `1.3.6.1.4.1.311.2.1.12` +/// +/// The internal structure is described in the official document: +/// *Windows Authenticode Portable Executable Signature Format* +/// +/// ```text +/// SpcSpOpusInfo ::= SEQUENCE { +/// programName [0] EXPLICIT SpcString OPTIONAL, +/// moreInfo [1] EXPLICIT SpcLink OPTIONAL +/// } +/// ``` +pub struct SpcSpOpusInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for SpcSpOpusInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SpcSpOpusInfo") + .field("program_name", &self.program_name()) + .field("more_info", &self.more_info()) + .finish() + } +} + +impl<'a> FromFFI for SpcSpOpusInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl SpcSpOpusInfo<'_> { + /// Program description provided by the publisher + pub fn program_name(&self) -> String { + self.ptr.program_name().to_string() + } + + /// Other information such as an url + pub fn more_info(&self) -> String { + self.ptr.more_info().to_string() + } +} + +pub struct SpcRelaxedPeMarkerCheck<'a> { + #[allow(dead_code)] + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for SpcRelaxedPeMarkerCheck<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SpcRelaxedPeMarkerCheck").finish() + } +} + +impl<'a> FromFFI for SpcRelaxedPeMarkerCheck<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl SpcRelaxedPeMarkerCheck<'_> {} + +/// ```text +/// SigningCertificateV2 ::= SEQUENCE { +/// certs SEQUENCE OF ESSCertIDv2, +/// policies SEQUENCE OF PolicyInformation OPTIONAL +/// } +/// +/// ESSCertIDv2 ::= SEQUENCE { +/// hashAlgorithm AlgorithmIdentifier DEFAULT {algorithm id-sha256}, +/// certHash OCTET STRING, +/// issuerSerial IssuerSerial OPTIONAL +/// } +/// +/// IssuerSerial ::= SEQUENCE { +/// issuer GeneralNames, +/// serialNumber CertificateSerialNumber +/// } +/// +/// PolicyInformation ::= SEQUENCE { +/// policyIdentifier OBJECT IDENTIFIER, +/// policyQualifiers SEQUENCE SIZE (1..MAX) OF PolicyQualifierInfo OPTIONAL +/// } +/// ``` +pub struct SigningCertificateV2<'a> { + #[allow(dead_code)] + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for SigningCertificateV2<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SigningCertificateV2").finish() + } +} + +impl<'a> FromFFI for SigningCertificateV2<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl SigningCertificateV2<'_> { + // TODO(romain): Add API +} + +/// This structure exposes the MS Counter Signature attribute +pub struct MsCounterSign<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for MsCounterSign<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MsCounterSign").finish() + } +} + +impl<'a> FromFFI for MsCounterSign<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> MsCounterSign<'a> { + pub fn version(&self) -> u32 { + self.ptr.version() + } + + pub fn digest_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.digest_algorithm()) + } + + /// ContentInfo as described in the RFC2315 + pub fn content_info(&'a self) -> ContentInfo<'a> { + ContentInfo::from_ffi(self.ptr.content_info()) + } + + /// Return list of [`crate::pe::signature::X509`] certificates associated with this signature + pub fn certificates(&'a self) -> MsCounterCertificates<'a> { + MsCounterCertificates::new(self.ptr.certificates()) + } + + /// Iterator over the signer [`SignerInfo`] defined in the PKCS #7 signature + pub fn signers(&'a self) -> MsCounterSigners<'a> { + MsCounterSigners::new(self.ptr.signers()) + } +} + +declare_iterator!( + MsCounterCertificates, + X509<'a>, + ffi::PE_x509, + ffi::PE_MsCounterSign, + ffi::PE_MsCounterSign_it_certificates +); + +declare_iterator!( + MsCounterSigners, + SignerInfo<'a>, + ffi::PE_SignerInfo, + ffi::PE_MsCounterSign, + ffi::PE_MsCounterSign_it_signers +); + +/// Interface over the structure described by the OID `1.3.6.1.4.1.311.10.3.28` (szOID_PLATFORM_MANIFEST_BINARY_ID) +/// +/// The internal structure is not documented but we can infer the following structure: +/// +/// ```text +/// szOID_PLATFORM_MANIFEST_BINARY_ID ::= SET OF BinaryID +/// ``` +/// +/// `BinaryID` being an alias of UTF8STRING +pub struct MsManifestBinaryID<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for MsManifestBinaryID<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MsManifestBinaryID") + .field("manifest_id", &self.manifest_id()) + .finish() + } +} + +impl<'a> FromFFI for MsManifestBinaryID<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl MsManifestBinaryID<'_> { + pub fn manifest_id(&self) -> String { + self.ptr.manifest_id().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature/content_info.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature/content_info.rs new file mode 100644 index 0000000..059ea52 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature/content_info.rs @@ -0,0 +1,219 @@ +use std::marker::PhantomData; + +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::pe::Algorithms; +use crate::to_slice; + +pub struct ContentInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Signature>, +} + +/// ContentInfo as described in the RFC2315 +impl ContentInfo<'_> { + /// Return the OID that describes the content wrapped by this object. + /// It should match `SPC_INDIRECT_DATA_OBJID` (`1.3.6.1.4.1.311.2.1.4`) + pub fn content_type(&self) -> String { + self.ptr.content_type().to_string() + } + + pub fn value(&self) -> Option> { + into_optional(self.ptr.value()) + } + + /// Return the digest (authentihash) if the underlying content type is `SPC_INDIRECT_DATA_OBJID` + /// Otherwise, return an empty vector + pub fn digest(&self) -> Vec { + Vec::from(self.ptr.digest().as_slice()) + } + + /// Return the digest used to hash the file + pub fn digest_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.digest_algorithm()) + } +} + +impl std::fmt::Debug for ContentInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("ContentInfo") + .field("content_type", &self.content_type()) + .finish() + } +} + +impl<'a> FromFFI for ContentInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + ContentInfo { + ptr, + _owner: PhantomData, + } + } +} + +#[derive(Debug)] +pub enum Content<'a> { + SpcIndirectData(SpcIndirectData<'a>), + PKCS9TSTInfo(PKCS9TSTInfo<'a>), + Generic(Generic<'a>), +} + +impl<'a> FromFFI for Content<'a> { + fn from_ffi(ffi_entry: cxx::UniquePtr) -> Self { + unsafe { + let content_ref = ffi_entry.as_ref().unwrap(); + if ffi::PE_SpcIndirectData::classof(content_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Content::SpcIndirectData(SpcIndirectData::from_ffi(raw)) + } else if ffi::PE_PKCS9TSTInfo::classof(content_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Content::PKCS9TSTInfo(PKCS9TSTInfo::from_ffi(raw)) + } else { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ffi_entry) + }; + Content::Generic(Generic::from_ffi(raw)) + } + } + } +} + +pub trait ContentTrait { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::PE_ContentInfo_Content; + + /// Return the OID that describes this content info. + /// In the case of the PE authenticode, it should return `SPC_INDIRECT_DATA_OBJID (1.3.6.1.4.1.311.2.1.4)` + fn content_type(&self) -> String { + self.as_generic().content_type().to_string() + } +} + +pub struct SpcIndirectData<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ContentInfo>, +} + +impl SpcIndirectData<'_> { + pub fn file(&self) -> String { + self.ptr.file().to_string() + } + + pub fn url(&self) -> String { + self.ptr.url().to_string() + } + + /// PE's authentihash + /// + /// See: [`crate::pe::Binary::authentihash`] + pub fn digest(&self) -> &[u8] { + to_slice!(self.ptr.digest()); + } + + /// Digest used to hash the file + pub fn digest_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.digest_algorithm()) + } +} + +impl std::fmt::Debug for SpcIndirectData<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SpcIndirectData") + .field("file", &self.file()) + .field("url", &self.url()) + .field("digest_algorithm", &self.digest_algorithm()) + .finish() + } +} + +impl FromFFI for SpcIndirectData<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ContentTrait for SpcIndirectData<'_> { + fn as_generic(&self) -> &ffi::PE_ContentInfo_Content { + self.ptr.as_ref().unwrap().as_ref() + } +} + +pub struct PKCS9TSTInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ContentInfo>, +} + +impl PKCS9TSTInfo<'_> { + // TODO(romain): Add API +} + +impl std::fmt::Debug for PKCS9TSTInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("PKCS9TSTInfo").finish() + } +} + +impl FromFFI for PKCS9TSTInfo<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ContentTrait for PKCS9TSTInfo<'_> { + fn as_generic(&self) -> &ffi::PE_ContentInfo_Content { + self.ptr.as_ref().unwrap().as_ref() + } +} + +pub struct Generic<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_ContentInfo>, +} + +impl Generic<'_> { + pub fn raw(&self) -> &[u8] { + to_slice!(self.ptr.raw()); + } + + pub fn oid(&self) -> String { + self.ptr.oid().to_string() + } +} + +impl std::fmt::Debug for Generic<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Generic").finish() + } +} + +impl FromFFI for Generic<'_> { + fn from_ffi(cmd: cxx::UniquePtr) -> Self { + Self { + ptr: cmd, + _owner: PhantomData, + } + } +} + +impl ContentTrait for Generic<'_> { + fn as_generic(&self) -> &ffi::PE_ContentInfo_Content { + self.ptr.as_ref().unwrap().as_ref() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature/rsa_info.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature/rsa_info.rs new file mode 100644 index 0000000..a8fc928 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature/rsa_info.rs @@ -0,0 +1,76 @@ +use lief_ffi as ffi; +use num_bigint::BigUint; + +use crate::common::FromFFI; +use std::marker::PhantomData; + +/// Structure that wraps an RSA key +pub struct RsaInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, +} + +impl std::fmt::Debug for RsaInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("RsaInfo") + .field("key_size", &self.key_size()) + .field("has_public_key", &self.has_public_key()) + .field("has_private_key", &self.has_private_key()) + .finish() + } +} + +impl<'a> FromFFI for RsaInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + RsaInfo { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> RsaInfo<'a> { + #[allow(non_snake_case)] + /// RSA public modulus + pub fn N(&self) -> BigUint { + BigUint::from_bytes_le(self.ptr.N().as_slice()) + } + + /// RSA public exponent + #[allow(non_snake_case)] + pub fn E(&self) -> BigUint { + BigUint::from_bytes_le(self.ptr.E().as_slice()) + } + + #[allow(non_snake_case)] + /// RSA private exponent + pub fn D(&self) -> BigUint { + BigUint::from_bytes_le(self.ptr.D().as_slice()) + } + + #[allow(non_snake_case)] + /// First prime factor + pub fn P(&self) -> BigUint { + BigUint::from_bytes_le(self.ptr.P().as_slice()) + } + #[allow(non_snake_case)] + /// Second prime factor + pub fn Q(&self) -> BigUint { + BigUint::from_bytes_le(self.ptr.Q().as_slice()) + } + + /// Size of the public modulus (in bits) + pub fn key_size(&self) -> u32 { + self.ptr.key_size() + } + + /// True if it embeds a public key + pub fn has_public_key(&self) -> bool { + self.ptr.has_public_key() + } + + /// True if it embeds a private key + pub fn has_private_key(&self) -> bool { + self.ptr.has_private_key() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature/signer_info.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature/signer_info.rs new file mode 100644 index 0000000..3b84389 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature/signer_info.rs @@ -0,0 +1,187 @@ +use std::marker::PhantomData; + +use super::X509; +use super::attributes::Attribute; +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::pe::Algorithms; +use crate::to_slice; +use lief_ffi as ffi; + +/// Concrete type of a signature attribute +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum AttributeType { + CONTENT_TYPE, + GENERIC_TYPE, + SIGNING_CERTIFICATE_V2, + SPC_SP_OPUS_INFO, + SPC_RELAXED_PE_MARKER_CHECK, + MS_COUNTER_SIGN, + MS_SPC_NESTED_SIGN, + MS_SPC_STATEMENT_TYPE, + MS_PLATFORM_MANIFEST_BINARY_ID, + PKCS9_AT_SEQUENCE_NUMBER, + PKCS9_COUNTER_SIGNATURE, + PKCS9_MESSAGE_DIGEST, + PKCS9_SIGNING_TIME, + UNKNOWN(u32), +} + +impl From for AttributeType { + fn from(value: u32) -> Self { + match value { + 0x00000001 => AttributeType::CONTENT_TYPE, + 0x00000002 => AttributeType::GENERIC_TYPE, + 0x00000003 => AttributeType::SIGNING_CERTIFICATE_V2, + 0x00000004 => AttributeType::SPC_SP_OPUS_INFO, + 0x00000005 => AttributeType::SPC_RELAXED_PE_MARKER_CHECK, + 0x00000006 => AttributeType::MS_COUNTER_SIGN, + 0x00000007 => AttributeType::MS_SPC_NESTED_SIGN, + 0x00000008 => AttributeType::MS_SPC_STATEMENT_TYPE, + 0x00000009 => AttributeType::MS_PLATFORM_MANIFEST_BINARY_ID, + 0x0000000a => AttributeType::PKCS9_AT_SEQUENCE_NUMBER, + 0x0000000b => AttributeType::PKCS9_COUNTER_SIGNATURE, + 0x0000000c => AttributeType::PKCS9_MESSAGE_DIGEST, + 0x0000000d => AttributeType::PKCS9_SIGNING_TIME, + _ => AttributeType::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: AttributeType) -> u32 { + match value { + AttributeType::CONTENT_TYPE => 0x00000001, + AttributeType::GENERIC_TYPE => 0x00000002, + AttributeType::SIGNING_CERTIFICATE_V2 => 0x00000003, + AttributeType::SPC_SP_OPUS_INFO => 0x00000004, + AttributeType::SPC_RELAXED_PE_MARKER_CHECK => 0x00000005, + AttributeType::MS_COUNTER_SIGN => 0x00000006, + AttributeType::MS_SPC_NESTED_SIGN => 0x00000007, + AttributeType::MS_SPC_STATEMENT_TYPE => 0x00000008, + AttributeType::MS_PLATFORM_MANIFEST_BINARY_ID => 0x00000009, + AttributeType::PKCS9_AT_SEQUENCE_NUMBER => 0x0000000a, + AttributeType::PKCS9_COUNTER_SIGNATURE => 0x0000000b, + AttributeType::PKCS9_MESSAGE_DIGEST => 0x0000000c, + AttributeType::PKCS9_SIGNING_TIME => 0x0000000d, + AttributeType::UNKNOWN(v) => v, + } + } +} + +/// SignerInfo as described in the [RFC 2315](https://tools.ietf.org/html/rfc2315#section-9.2) +pub struct SignerInfo<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ()>, // Can be own by Signature or PKCS9CounterSignature +} + +impl std::fmt::Debug for SignerInfo<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("SignerInfo") + .field("version", &self.version()) + .field("issuer", &self.issuer()) + .field("digest_algorithm", &self.digest_algorithm()) + .field("encryption_algorithm", &self.encryption_algorithm()) + .finish() + } +} + +impl<'a> FromFFI for SignerInfo<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + SignerInfo { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> SignerInfo<'a> { + /// Should be 1 + pub fn version(&self) -> u32 { + self.ptr.version() + } + + /// Return the [`X509::issuer`] used by this signer + pub fn issuer(&self) -> String { + self.ptr.issuer().to_string() + } + + /// Algorithm used to hash the file. + pub fn digest_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.digest_algorithm()) + } + + /// Return the (public-key) algorithm used to encrypt the signature + pub fn encryption_algorithm(&self) -> Algorithms { + Algorithms::from(self.ptr.encryption_algorithm()) + } + + /// Return the serial number associated with the x509 certificate + /// used by this signer. + pub fn serial_number(&self) -> &[u8] { + to_slice!(self.ptr.serial_number()); + } + + /// Return the signature created by the signing certificate's private key + pub fn encrypted_digest(&self) -> Vec { + Vec::from(self.ptr.encrypted_digest().as_slice()) + } + + /// [`X509`] certificate used by this signer. + pub fn cert(&self) -> Option> { + into_optional(self.ptr.cert()) + } + + /// Iterator over the **authenticated** [`Attribute`] + pub fn authenticated_attributes(&self) -> AuthenticatedAttributes<'_> { + AuthenticatedAttributes::new(self.ptr.authenticated_attributes()) + } + + /// Iterator over the **unauthenticated** [`Attribute`] + pub fn unauthenticated_attributes(&self) -> UnAuthenticatedAttributes<'_> { + UnAuthenticatedAttributes::new(self.ptr.unauthenticated_attributes()) + } + + /// Raw blob that is signed by the signer certificate + pub fn raw_auth_data(&self) -> &[u8] { + to_slice!(self.ptr.raw_auth_data()); + } + + /// Return the first authenticated or unauthenticated attribute matching the given type + pub fn get_attribute(&self, attr_type: AttributeType) -> Option> { + into_optional(self.ptr.get_attribute(attr_type.into())) + } + + /// Return the first authenticated attribute matching the given type + pub fn get_auth_attribute(&self, attr_type: AttributeType) -> Option> { + into_optional(self.ptr.get_auth_attribute(attr_type.into())) + } + + /// Return the first unauthenticated attribute matching the given type + pub fn get_unauth_attribute(&self, attr_type: AttributeType) -> Option> { + into_optional(self.ptr.get_unauth_attribute(attr_type.into())) + } +} + +declare_iterator!( + Signers, + SignerInfo<'a>, + ffi::PE_SignerInfo, + ffi::PE_Signature, + ffi::PE_Signature_it_signers +); +declare_iterator!( + AuthenticatedAttributes, + Attribute<'a>, + ffi::PE_Attribute, + ffi::PE_SignerInfo, + ffi::PE_SignerInfo_it_authenticated_attributes +); +declare_iterator!( + UnAuthenticatedAttributes, + Attribute<'a>, + ffi::PE_Attribute, + ffi::PE_SignerInfo, + ffi::PE_SignerInfo_it_unauthenticated_attributes +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/signature/x509.rs b/vendor/lief/api/rust/crates/lief/src/pe/signature/x509.rs new file mode 100644 index 0000000..8b618e1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/signature/x509.rs @@ -0,0 +1,307 @@ +use std::marker::PhantomData; + +use bitflags::bitflags; +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_iterator; +use crate::pe::Algorithms; + +use super::RsaInfo; + +/// Structure for a x509 certificate +pub struct X509<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_SignerInfo>, +} + +impl std::fmt::Debug for X509<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("x509") + .field("version", &self.version()) + .field("signature_algorithm", &self.signature_algorithm()) + .field("valid_from", &self.valid_from()) + .field("valid_to", &self.valid_to()) + .field("issuer", &self.issuer()) + .field("key_type", &self.key_type()) + .field("subject", &self.subject()) + .field("is_ca", &self.is_ca()) + .finish() + } +} + +impl<'a> FromFFI for X509<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + X509 { + ptr, + _owner: PhantomData, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +/// Public key scheme +pub enum KeyType { + /// Unknown scheme + NONE, + + /// RSA Scheme + RSA, + + /// Elliptic-curve scheme + ECKEY, + + /// Elliptic-curve Diffie-Hellman + ECKEY_DH, + + /// Elliptic-curve Digital Signature Algorithm + ECDSA, + + /// RSA scheme with an alternative implementation for signing and decrypting + RSA_ALT, + + /// RSA Probabilistic signature scheme + RSASSA_PSS, + UNKNOWN(u32), +} + +impl From for KeyType { + fn from(value: u32) -> Self { + match value { + 0x00000000 => KeyType::NONE, + 0x00000001 => KeyType::RSA, + 0x00000002 => KeyType::ECKEY, + 0x00000003 => KeyType::ECKEY_DH, + 0x00000004 => KeyType::ECDSA, + 0x00000005 => KeyType::RSA_ALT, + 0x00000006 => KeyType::RSASSA_PSS, + _ => KeyType::UNKNOWN(value), + } + } +} + +/// Key usage as defined in RFC #5280 - section-4.2.1.3 +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum KeyUsage { + /// The key is used for digital signature + DIGITAL_SIGNATURE, + /// The key is used for digital signature and to protect against falsely denying some action + NON_REPUDIATION, + /// The key is used for enciphering private or secret keys + KEY_ENCIPHERMENT, + /// The key is used for directly enciphering raw user data without an intermediate symmetric cipher + DATA_ENCIPHERMENT, + /// The key is used for key agreement (e.g. with Diffie-Hellman) + KEY_AGREEMENT, + /// The key is used for verifying signatures on public key certificates + KEY_CERT_SIGN, + /// The key is used for verifying signatures on certificate revocation lists + CRL_SIGN, + /// In association with KEY_AGREEMENT, the key is only used for enciphering data + ENCIPHER_ONLY, + /// In association with KEY_AGREEMENT, the key is only used for deciphering data + DECIPHER_ONLY, + UNKNOWN(u32), +} + +impl From for KeyUsage { + fn from(value: u32) -> Self { + match value { + 0x00000000 => KeyUsage::DIGITAL_SIGNATURE, + 0x00000001 => KeyUsage::NON_REPUDIATION, + 0x00000002 => KeyUsage::KEY_ENCIPHERMENT, + 0x00000003 => KeyUsage::DATA_ENCIPHERMENT, + 0x00000004 => KeyUsage::KEY_AGREEMENT, + 0x00000005 => KeyUsage::KEY_CERT_SIGN, + 0x00000006 => KeyUsage::CRL_SIGN, + 0x00000007 => KeyUsage::ENCIPHER_ONLY, + 0x00000008 => KeyUsage::DECIPHER_ONLY, + _ => KeyUsage::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: KeyUsage) -> u32 { + match value { + KeyUsage::DIGITAL_SIGNATURE => 0x00000000, + KeyUsage::NON_REPUDIATION => 0x00000001, + KeyUsage::KEY_ENCIPHERMENT => 0x00000002, + KeyUsage::DATA_ENCIPHERMENT => 0x00000003, + KeyUsage::KEY_AGREEMENT => 0x00000004, + KeyUsage::KEY_CERT_SIGN => 0x00000005, + KeyUsage::CRL_SIGN => 0x00000006, + KeyUsage::ENCIPHER_ONLY => 0x00000007, + KeyUsage::DECIPHER_ONLY => 0x00000008, + KeyUsage::UNKNOWN(v) => v, + } + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + /// Mirror of mbedtls X509 verification flags for certificate verification + pub struct VerificationFlags: u32 { + const OK = 0; + const BADCERT_EXPIRED = 1 << 0; + const BADCERT_REVOKED = 1 << 1; + const BADCERT_CN_MISMATCH = 1 << 2; + const BADCERT_NOT_TRUSTED = 1 << 3; + const BADCRL_NOT_TRUSTED = 1 << 4; + const BADCRL_EXPIRED = 1 << 5; + const BADCERT_MISSING = 1 << 6; + const BADCERT_SKIP_VERIFY = 1 << 7; + const BADCERT_OTHER = 1 << 8; + const BADCERT_FUTURE = 1 << 9; + const BADCRL_FUTURE = 1 << 10; + const BADCERT_KEY_USAGE = 1 << 11; + const BADCERT_EXT_KEY_USAGE = 1 << 12; + const BADCERT_NS_CERT_TYPE = 1 << 13; + const BADCERT_BAD_MD = 1 << 14; + const BADCERT_BAD_PK = 1 << 15; + const BADCERT_BAD_KEY = 1 << 16; + const BADCRL_BAD_MD = 1 << 17; + const BADCRL_BAD_PK = 1 << 18; + const BADCRL_BAD_KEY = 1 << 19; + } +} + +impl std::fmt::Display for VerificationFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl From for VerificationFlags { + fn from(value: u32) -> Self { + VerificationFlags::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: VerificationFlags) -> Self { + value.bits() + } +} + +impl VerificationFlags { + pub fn is_ok(self) -> bool { + self == VerificationFlags::OK + } +} + +impl X509<'_> { + /// X.509 version. (1=v1, 2=v2, 3=v3) + pub fn version(&self) -> u32 { + self.ptr.version() + } + + /// Unique id for certificate issued by a specific CA. + pub fn serial_number(&self) -> Vec { + Vec::from(self.ptr.serial_number().as_slice()) + } + + /// Signature algorithm (OID) + pub fn signature_algorithm(&self) -> String { + self.ptr.signature_algorithm().to_string() + } + + /// Start time of certificate validity + pub fn valid_from(&self) -> Vec { + Vec::from(self.ptr.valid_from().as_slice()) + } + + /// End time of certificate validity + pub fn valid_to(&self) -> Vec { + Vec::from(self.ptr.valid_to().as_slice()) + } + + /// Issuer information + pub fn issuer(&self) -> String { + self.ptr.issuer().to_string() + } + + /// Subject information + pub fn subject(&self) -> String { + self.ptr.subject().to_string() + } + + /// The raw x509 bytes (DER encoded) + pub fn raw(&self) -> Vec { + Vec::from(self.ptr.raw().as_slice()) + } + + /// Return the underlying public-key scheme + pub fn key_type(&self) -> KeyType { + KeyType::from(self.ptr.key_type()) + } + pub fn is_ca(&self) -> bool { + self.ptr.is_ca() + } + + /// The signature of the certificate + pub fn signature(&self) -> Vec { + Vec::from(self.ptr.signature().as_slice()) + } + + /// **If** the underlying public-key scheme is RSA, return the RSA information. + pub fn rsa_info(&self) -> Option> { + into_optional(self.ptr.rsa_info()) + } + + /// Try to decrypt the given signature and check if it matches the given hash according to + /// the hash algorithm provided + pub fn check_signature(&self, hash: &[u8], signature: &[u8], digest: Algorithms) -> bool { + unsafe { + self.ptr.check_signature( + hash.as_ptr(), + hash.len(), + signature.as_ptr(), + signature.len(), + digest.into(), + ) != 0 + } + } + + /// Verify that this certificate has been used **to trust** the given certificate + pub fn verify(&self, ca: &X509) -> VerificationFlags { + VerificationFlags::from(self.ptr.verify(ca.ptr.as_ref().unwrap())) + } + + /// Return the key usage extensions of this certificate + pub fn key_usage(&self) -> Vec { + self.ptr + .key_usage() + .into_iter() + .map(|e| KeyUsage::from(*e)) + .collect() + } + + /// Return the extended key usage OIDs of this certificate + pub fn ext_key_usage(&self) -> Vec { + self.ptr + .ext_key_usage() + .into_iter() + .map(|e| e.to_string()) + .collect() + } + + /// Return the certificate policies OIDs of this certificate + pub fn certificate_policies(&self) -> Vec { + self.ptr + .certificate_policies() + .into_iter() + .map(|e| e.to_string()) + .collect() + } +} + +declare_iterator!( + Certificates, + X509<'a>, + ffi::PE_x509, + ffi::PE_Signature, + ffi::PE_Signature_it_certificates +); diff --git a/vendor/lief/api/rust/crates/lief/src/pe/tls.rs b/vendor/lief/api/rust/crates/lief/src/pe/tls.rs new file mode 100644 index 0000000..df22469 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/tls.rs @@ -0,0 +1,164 @@ +//! This module represents the PE's Thread Local Storage (TLS) + +use lief_ffi as ffi; + +use crate::common::{AsFFI, FromFFI, into_optional}; +use crate::to_slice; +use std::marker::PhantomData; + +use crate::pe::DataDirectory; +use crate::pe::Section; + +pub struct TLS<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_Binary>, +} + +impl std::fmt::Debug for TLS<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("TLS") + .field("callbacks", &self.callbacks()) + .field("addressof_index", &self.addressof_index()) + .field("addressof_callbacks", &self.addressof_callbacks()) + .field("sizeof_zero_fill", &self.sizeof_zero_fill()) + .field("characteristics", &self.characteristics()) + .finish() + } +} + +impl TLS<'_> { + pub fn new() -> TLS<'static> { + TLS::from_ffi(lief_ffi::PE_TLS::create()) + } + /// List of callbacks associated with the current TLS + /// + /// These functions are called before any other functions. + pub fn callbacks(&self) -> Vec { + Vec::from(self.ptr.callbacks().as_slice()) + } + + /// The location to receive the TLS index assigned by the loader. + /// This location should be located in a writable section like `.data` + pub fn addressof_index(&self) -> u64 { + self.ptr.addressof_index() + } + + /// Pointer to an array of TLS callback functions. + /// + /// The array is null-terminated, so if there is no callback function this field points to 4 + /// bytes set to zero. + /// + /// See [`TLS::callbacks`] + pub fn addressof_callbacks(&self) -> u64 { + self.ptr.addressof_callbacks() + } + + /// Size in bytes of the zero to be *padded* after the data specified by [`TLS::data_template`] + pub fn sizeof_zero_fill(&self) -> u32 { + self.ptr.sizeof_zero_fill() + } + + /// The four bits `[23:20]` describe alignment info. + /// + /// Possible values are those defined as `IMAGE_SCN_ALIGN_*`, which are also used to describe + /// alignment of section in object files. + /// + /// The other 28 bits are reserved for future use. + pub fn characteristics(&self) -> u32 { + self.ptr.characteristics() + } + + /// The initial content used to initialize TLS data. + pub fn data_template(&self) -> &[u8] { + to_slice!(self.ptr.data_template()); + } + + /// Range of addresses where the [`TLS::data_template`] is located. + /// + /// The template is a block of data that is used to initialize TLS data. + /// The system copies all of this data each time a thread is created, so it + /// must not be corrupted. + /// + /// These addresses are not RVA. It is addresses for which there + /// should be a rebase relocation in the `.reloc` section. + pub fn addressof_raw_data(&self) -> (u64, u64) { + let vec = Vec::from(self.ptr.addressof_raw_data().as_slice()); + if vec.len() != 2 { + return (0, 0); + } + (vec[0], vec[1]) + } + + /// The section where the TLS structure is located + pub fn section(&self) -> Option> { + into_optional(self.ptr.section()) + } + + /// The data directory describing the TLS + pub fn directory(&self) -> Option> { + into_optional(self.ptr.data_directory()) + } + + /// Add an address to the list of callbacks + pub fn add_callback(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().add_callback(addr); + self + } + + pub fn set_callbacks(&mut self, callbacks: &[u64]) -> &mut Self { + unsafe { + self.ptr + .pin_mut() + .set_callbacks(callbacks.as_ptr(), callbacks.len()); + } + self + } + + pub fn set_addressof_index(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().set_addressof_index(addr); + self + } + + pub fn set_addressof_callback(&mut self, addr: u64) -> &mut Self { + self.ptr.pin_mut().set_addressof_callback(addr); + self + } + + pub fn set_sizeof_zero_fill(&mut self, size: u32) -> &mut Self { + self.ptr.pin_mut().set_sizeof_zero_fill(size); + self + } + + pub fn set_characteristics(&mut self, characteristics: u32) -> &mut Self { + self.ptr.pin_mut().set_characteristics(characteristics); + self + } + + pub fn set_data_template(&mut self, data: &[u8]) -> &mut Self { + unsafe { + self.ptr + .pin_mut() + .set_data_template(data.as_ptr(), data.len()); + } + self + } +} + +impl<'a> FromFFI for TLS<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + TLS { + ptr, + _owner: PhantomData, + } + } +} + +impl<'a> AsFFI for TLS<'a> { + fn as_ffi(&self) -> &ffi::PE_TLS { + self.ptr.as_ref().unwrap() + } + + fn as_mut_ffi(&mut self) -> std::pin::Pin<&mut ffi::PE_TLS> { + self.ptr.pin_mut() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/pe/volatile_metadata.rs b/vendor/lief/api/rust/crates/lief/src/pe/volatile_metadata.rs new file mode 100644 index 0000000..13af119 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/pe/volatile_metadata.rs @@ -0,0 +1,127 @@ +//! PE volatile memory metadata +use std::marker::PhantomData; + +use crate::{common::FromFFI, declare_iterator}; +use lief_ffi as ffi; + +/// This class represents volatile metadata which can be enabled at link time +/// with `/volatileMetadata`. +/// +/// This metadata aims to improve performances when running x64 code on ARM64. +pub struct VolatileMetadata<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_LoadConfiguration>, +} + +impl<'a> FromFFI for VolatileMetadata<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl VolatileMetadata<'_> { + pub fn size(&self) -> u32 { + self.ptr.size() + } + + pub fn min_version(&self) -> u16 { + self.ptr.min_version() + } + + pub fn max_version(&self) -> u16 { + self.ptr.max_version() + } + + pub fn access_table_rva(&self) -> u32 { + self.ptr.access_table_rva() + } + + pub fn access_table_size(&self) -> u32 { + self.ptr.access_table_size() + } + + pub fn info_range_rva(&self) -> u32 { + self.ptr.info_range_rva() + } + + pub fn info_ranges_size(&self) -> u32 { + self.ptr.info_ranges_size() + } + + pub fn info_ranges(&self) -> Ranges<'_> { + Ranges::new(self.ptr.info_ranges()) + } + + pub fn access_table(&self) -> Vec { + Vec::from(self.ptr.access_table().as_slice()) + } +} + +impl std::fmt::Debug for VolatileMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("VolatileMetadata") + .field("size", &self.size()) + .field("min_version", &self.min_version()) + .field("max_version", &self.max_version()) + .field("access_table_rva", &self.access_table_rva()) + .field("access_table_size", &self.access_table_size()) + .field("info_range_rva", &self.info_range_rva()) + .field("info_ranges_size", &self.info_ranges_size()) + .finish() + } +} + +impl std::fmt::Display for VolatileMetadata<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +pub struct Range<'a> { + ptr: cxx::UniquePtr, + _owner: PhantomData<&'a ffi::PE_VolatileMetadata>, +} + +impl<'a> FromFFI for Range<'a> { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { + ptr, + _owner: PhantomData, + } + } +} + +impl Range<'_> { + pub fn start(&self) -> u32 { + self.ptr.start() + } + + pub fn end(&self) -> u32 { + self.ptr.end() + } + + pub fn size(&self) -> u32 { + self.ptr.size() + } +} + +impl std::fmt::Debug for Range<'_> { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Range") + .field("start", &self.start()) + .field("end", &self.end()) + .field("size", &self.size()) + .finish() + } +} + +declare_iterator!( + Ranges, + Range<'a>, + ffi::PE_Range, + ffi::PE_VolatileMetadata, + ffi::PE_VolatileMetadata_it_ranges +); diff --git a/vendor/lief/api/rust/crates/lief/src/range.rs b/vendor/lief/api/rust/crates/lief/src/range.rs new file mode 100644 index 0000000..9140efc --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/range.rs @@ -0,0 +1,16 @@ +use lief_ffi as ffi; + +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub struct Range { + pub low: u64, + pub high: u64, +} + +impl Range { + pub fn from_ffi(raw: &ffi::Range) -> Self { + Self { + low: raw.low, + high: raw.high, + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime.rs b/vendor/lief/api/rust/crates/lief/src/runtime.rs new file mode 100644 index 0000000..cf0d7c4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime.rs @@ -0,0 +1,122 @@ +//! This module contains all LIEF's runtime API + +pub mod android; +pub mod assembler; +pub mod disassembler; +pub mod host; +pub mod linux; +pub mod memory; +pub mod memory_layout; +pub mod module; +pub mod osx; +pub mod process; +pub mod windows; + +#[doc(inline)] +pub use assembler::{assemble, assemble_with_config}; + +#[doc(inline)] +pub use disassembler::disassemble; + +#[doc(inline)] +pub use host::Host; + +#[doc(inline)] +pub use process::Process; + +#[doc(inline)] +pub use module::{Module, Modules, module_from_addr, module_from_name, module_from_path, modules}; + +#[doc(inline)] +pub use memory::Memory; + +#[doc(inline)] +pub use memory_layout::{Region, RegionsIt, memory_layout}; + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Arch { + NONE, + X86_64, + ARM64, + RISCV64, + UNKNOWN(u32), +} + +impl From for Arch { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Arch::NONE, + 0x00000001 => Arch::X86_64, + 0x00000002 => Arch::ARM64, + 0x00000003 => Arch::RISCV64, + _ => Arch::UNKNOWN(value), + } + } +} +impl From for u32 { + fn from(value: Arch) -> u32 { + match value { + Arch::NONE => 0x00000000, + Arch::X86_64 => 0x00000001, + Arch::ARM64 => 0x00000002, + Arch::RISCV64 => 0x00000003, + Arch::UNKNOWN(value) => value, + } + } +} + +#[allow(non_camel_case_types)] +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub enum Platform { + NONE, + LINUX, + WINDOWS, + ANDROID, + OSX, + IOS, + UNKNOWN(u32), +} + +impl From for Platform { + fn from(value: u32) -> Self { + match value { + 0x00000000 => Platform::NONE, + 0x00000001 => Platform::LINUX, + 0x00000002 => Platform::WINDOWS, + 0x00000003 => Platform::ANDROID, + 0x00000004 => Platform::OSX, + 0x00000005 => Platform::IOS, + _ => Platform::UNKNOWN(value), + } + } +} + +impl From for u32 { + fn from(value: Platform) -> u32 { + match value { + Platform::NONE => 0x00000000, + Platform::LINUX => 0x00000001, + Platform::WINDOWS => 0x00000002, + Platform::ANDROID => 0x00000003, + Platform::OSX => 0x00000004, + Platform::IOS => 0x00000005, + Platform::UNKNOWN(value) => value, + } + } +} + +/// Whether runtime features are enabled +pub fn enabled() -> bool { + lief_ffi::runtime_enabled() +} + +/// Platform for which the runtime is compiled +pub fn platform() -> Platform { + Platform::from(lief_ffi::runtime_platform()) +} + +/// Architecture for which the runtime is compiled +pub fn arch() -> Arch { + Arch::from(lief_ffi::runtime_arch()) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/android.rs b/vendor/lief/api/rust/crates/lief/src/runtime/android.rs new file mode 100644 index 0000000..1c1c8ef --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/android.rs @@ -0,0 +1,17 @@ +//! Android-specific API +pub mod host; +pub mod module; +pub mod process; +pub mod property; + +#[doc(inline)] +pub use module::{Module, dlopen}; + +#[doc(inline)] +pub use host::Host; + +#[doc(inline)] +pub use process::Process; + +#[doc(inline)] +pub use property::{Properties, Property}; diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/android/host.rs b/vendor/lief/api/rust/crates/lief/src/runtime/android/host.rs new file mode 100644 index 0000000..fb70f5d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/android/host.rs @@ -0,0 +1,17 @@ +use lief_ffi as ffi; + +/// This structure exposes Android-specific host information. +pub struct Host {} + +impl Host { + /// Return the Android SDK/API level of the device (e.g. `34` for Android + /// 14). + pub fn sdk_version() -> Option { + let version = ffi::runtime_android_Host::sdk_version(); + if version < 0 { + None + } else { + Some(version as u32) + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/android/module.rs b/vendor/lief/api/rust/crates/lief/src/runtime/android/module.rs new file mode 100644 index 0000000..b77aec6 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/android/module.rs @@ -0,0 +1,73 @@ +use std::ffi::c_void; + +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::elf::{Binary, ParserConfig}; +use crate::runtime; + +/// This structure represents an Android-specific module +pub struct Module { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Module { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Module { + /// Instantiate a [`Module`] from the given `dlopen` handle. + pub fn from_handle(handle: *const c_void) -> Option { + into_optional(ffi::runtime_android_Module::from_handle(handle as u64)) + } + + /// Return the `dlopen` handle for this library as an opaque pointer. + /// + /// Return a null pointer if the function fails or if the handler can't be + /// found. + pub fn handle(&self) -> *const c_void { + self.ptr.handle() as *const c_void + } + + /// Resolve the symbol with the given name for the current module + pub fn dlsym(&self, name: String) -> *const c_void { + cxx::let_cxx_string!(s = name); + self.ptr.dlsym(&s) as *const c_void + } + + /// Parse the ELF module from its path on the filesystem + pub fn parse_from_path(&self) -> Option { + into_optional(self.ptr.parse_from_path()) + } + + /// Parse the ELF module from its path on the filesystem and given the + /// parser configuration + pub fn parse_from_path_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_path_with_config(&config.to_ffi())) + } + + /// Parse the ELF module from memory + pub fn parse_from_memory(&self) -> Option { + into_optional(self.ptr.parse_from_memory()) + } + + /// Parse the ELF module from memory with the given configuration + pub fn parse_from_memory_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_memory_with_config(&config.to_ffi())) + } +} + +impl runtime::Module for Module { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Load the library with the given path or name +pub fn dlopen(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_android_dlopen(&s)) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/android/process.rs b/vendor/lief/api/rust/crates/lief/src/runtime/android/process.rs new file mode 100644 index 0000000..794f0cd --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/android/process.rs @@ -0,0 +1,31 @@ +use lief_ffi as ffi; + +use super::{Properties, Property}; +use crate::common::into_optional; + +/// This structure exposes Android-specific API for the current process. +pub struct Process {} + +impl Process { + /// Return the content of `/proc/cmdline` + pub fn cmdline() -> Option { + let cmdline = ffi::runtime_android_Process::cmdline().to_string(); + if cmdline.is_empty() { + None + } else { + Some(cmdline) + } + } + + /// Return the Android system property with the given `name` + /// (e.g. `ro.build.version.sdk`) or `None` if the property does not exist. + pub fn get_system_property(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_android_Process::get_system_property(&s)) + } + + /// Return an iterator over all the Android system properties. + pub fn properties() -> Properties { + Properties::new(ffi::runtime_android_Process::properties()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/android/property.rs b/vendor/lief/api/rust/crates/lief/src/runtime/android/property.rs new file mode 100644 index 0000000..c88b333 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/android/property.rs @@ -0,0 +1,58 @@ +use std::fmt; + +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_standalone_fwd_iterator; + +/// This structure represents an Android system property such as +/// `ro.boot.hardware`. +pub struct Property { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Property { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Property { + /// Name of the property (e.g. `ro.boot.hardware`). + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Value associated with the property. + pub fn value(&self) -> String { + self.ptr.value().to_string() + } + + /// Serial number of the property. + pub fn serial(&self) -> u32 { + self.ptr.serial() + } +} + +impl fmt::Debug for Property { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("Property") + .field("name", &self.name()) + .field("value", &self.value()) + .field("serial", &self.serial()) + .finish() + } +} + +impl fmt::Display for Property { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_standalone_fwd_iterator!( + Properties, + Property, + ffi::runtime_android_Property, + ffi::runtime_android_it_properties +); diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/assembler.rs b/vendor/lief/api/rust/crates/lief/src/runtime/assembler.rs new file mode 100644 index 0000000..e2461f5 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/assembler.rs @@ -0,0 +1,29 @@ +use lief_ffi as ffi; + +use crate::assembly::AssemblerConfig; + +/// Assemble the provided assembly code at the specified (absolute) virtual +/// address. +/// +/// The generated assembly bytes are returned by the function. +/// +/// ```rust,no_run +/// use lief::runtime; +/// +/// let code = runtime::assemble(0x7f0011223344, r#" +/// xor rax, rbx; +/// mov rcx, rax; +/// "#); +/// ``` +pub fn assemble(address: u64, asm: &str) -> Vec { + cxx::let_cxx_string!(__cxx_s = asm); + Vec::from(ffi::runtime_assemble(address, &__cxx_s).as_slice()) +} + +/// Same as [`assemble`] but this function takes an extra [`AssemblerConfig`] +/// that is used to configure the assembly engine: dialect, symbols definitions. +pub fn assemble_with_config(address: u64, asm: &str, config: &AssemblerConfig) -> Vec { + let ffi_config = config.into_ffi(); + cxx::let_cxx_string!(__cxx_s = asm); + Vec::from(ffi::runtime_assemble_with_config(address, &__cxx_s, ffi_config.as_ref()).as_slice()) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/disassembler.rs b/vendor/lief/api/rust/crates/lief/src/runtime/disassembler.rs new file mode 100644 index 0000000..4d1f4d4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/disassembler.rs @@ -0,0 +1,25 @@ +use lief_ffi as ffi; + +use crate::assembly; +use crate::common::FromFFI; +use crate::declare_standalone_fwd_iterator; + +/// Start disassembling instructions at the given **absolute** virtual address. +/// +/// ```rust,no_run +/// use lief::runtime; +/// +/// for inst in runtime::disassemble(0x7f0011223344) { +/// println!("{}", inst); +/// } +/// ``` +pub fn disassemble(addr: u64) -> InstructionsIt { + InstructionsIt::new(ffi::runtime_disassemble(addr)) +} + +declare_standalone_fwd_iterator!( + InstructionsIt, + assembly::Instructions, + ffi::asm_Instruction, + ffi::runtime_it_instructions +); diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/host.rs b/vendor/lief/api/rust/crates/lief/src/runtime/host.rs new file mode 100644 index 0000000..3277cba --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/host.rs @@ -0,0 +1,35 @@ +use lief_ffi as ffi; + +/// This structure represents the current host. +pub struct Host {} + +impl Host { + /// The machine hostname + pub fn name() -> String { + ffi::runtime_Host::name().to_string() + } + + /// The user home dir (e.g. `/home/romain` or `C:\Users\romain`) + pub fn home_dir() -> String { + ffi::runtime_Host::home_dir().to_string() + } + + /// Temporary directory. + /// + /// This function looks at the environment variables to determine the + /// suitable temp directory (e.g. `TEMP`, `TMPDIR`) + pub fn tmp_dir() -> String { + ffi::runtime_Host::tmp_dir().to_string() + } + + /// The directory to store user-specific configuration + pub fn config_dir() -> String { + ffi::runtime_Host::config_dir().to_string() + } + + /// The directory where software should store their cache files + /// (e.g. `$HOME/.cache`) + pub fn cache_dir() -> String { + ffi::runtime_Host::cache_dir().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/linux.rs b/vendor/lief/api/rust/crates/lief/src/runtime/linux.rs new file mode 100644 index 0000000..dbfa725 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/linux.rs @@ -0,0 +1,13 @@ +//! Linux-specific API +pub mod host; +pub mod module; +pub mod process; + +#[doc(inline)] +pub use module::{Module, dlopen}; + +#[doc(inline)] +pub use host::Host; + +#[doc(inline)] +pub use process::Process; diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/linux/host.rs b/vendor/lief/api/rust/crates/lief/src/runtime/linux/host.rs new file mode 100644 index 0000000..d7dce2e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/linux/host.rs @@ -0,0 +1,26 @@ +use lief_ffi as ffi; + +/// This structure exposes Linux-specific host information. +pub struct Host {} + +impl Host { + /// Operating system name (e.g. `Linux`) + pub fn sys_name() -> String { + ffi::runtime_linux_Host::sys_name().to_string() + } + + /// Operating system release (e.g. `2.6.28`) + pub fn sys_release() -> String { + ffi::runtime_linux_Host::sys_release().to_string() + } + + /// Operating system version + pub fn sys_version() -> String { + ffi::runtime_linux_Host::sys_version().to_string() + } + + /// Hardware type identifier (e.g. `x86_64`) + pub fn hardware() -> String { + ffi::runtime_linux_Host::hardware().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/linux/module.rs b/vendor/lief/api/rust/crates/lief/src/runtime/linux/module.rs new file mode 100644 index 0000000..c280615 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/linux/module.rs @@ -0,0 +1,73 @@ +use std::ffi::c_void; + +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::elf::{Binary, ParserConfig}; +use crate::runtime; + +/// This structure represents a Linux-specific module +pub struct Module { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Module { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Module { + /// Instantiate a [`Module`] from the given ``dlopen`` handle. + pub fn from_handle(handle: *const c_void) -> Option { + into_optional(ffi::runtime_linux_Module::from_handle(handle as u64)) + } + + /// Return the ``dlopen`` handle for this library as an opaque pointer. + /// + /// Return a null pointer if the function fails or if the handler can't be + /// found. + pub fn handle(&self) -> *const c_void { + self.ptr.handle() as *const c_void + } + + /// Resolve the symbol with the given name for the current module + pub fn dlsym(&self, name: String) -> *const c_void { + cxx::let_cxx_string!(s = name); + self.ptr.dlsym(&s) as *const c_void + } + + /// Parse the ELF module from its path on the filesystem + pub fn parse_from_path(&self) -> Option { + into_optional(self.ptr.parse_from_path()) + } + + /// Parse the ELF module from its path on the filesystem and given the + /// parser configuration + pub fn parse_from_path_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_path_with_config(&config.to_ffi())) + } + + /// Parse the ELF module from memory + pub fn parse_from_memory(&self) -> Option { + into_optional(self.ptr.parse_from_memory()) + } + + /// Parse the ELF module from memory with the given configuration + pub fn parse_from_memory_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_memory_with_config(&config.to_ffi())) + } +} + +impl runtime::Module for Module { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Load the library with the given path or name +pub fn dlopen(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_linux_dlopen(&s)) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/linux/process.rs b/vendor/lief/api/rust/crates/lief/src/runtime/linux/process.rs new file mode 100644 index 0000000..ec01bc4 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/linux/process.rs @@ -0,0 +1,27 @@ +use lief_ffi as ffi; + +/// This structure exposes Linux-specific API for the current process. +pub struct Process {} + +impl Process { + /// Return the content of `/proc/cmdline` + pub fn cmdline() -> Option { + let cmdline = ffi::runtime_linux_Process::cmdline().to_string(); + if cmdline.is_empty() { + None + } else { + Some(cmdline) + } + } + + /// Return the version of the GNU C Library (glibc) loaded in the current + /// process (e.g. `2.39`). + pub fn glibc_version() -> Option { + let version = ffi::runtime_linux_Process::glibc_version().to_string(); + if version.is_empty() { + None + } else { + Some(version) + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/memory.rs b/vendor/lief/api/rust/crates/lief/src/runtime/memory.rs new file mode 100644 index 0000000..a2e9175 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/memory.rs @@ -0,0 +1,235 @@ +use crate::to_ok_result; +use bitflags::bitflags; + +use lief_ffi as ffi; +use num_traits::{Num, cast}; + +use crate::{ + Error, + common::{FromFFI, into_optional}, +}; + +bitflags! { + /// Flags used when creating a memory map (mmap). + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct MmapFlags: u32 { + const NONE = 0; + /// Changes are private to this process (copy-on-write). + const PRIVATE = 1 << 0; + + /// The mapping is not backed by any file. + const ANONYMOUS = 1 << 1; + + /// Changes are shared. + const SHARED = 1 << 2; + + /// Interpret the address as a fixed requirement. + const FIXED = 1 << 3; + + /// Map for Just-In-Time code generation. + const JIT = 1 << 4; + } +} + +impl std::fmt::Display for MmapFlags { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl From for MmapFlags { + fn from(value: u32) -> Self { + MmapFlags::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: MmapFlags) -> Self { + value.bits() + } +} + +bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] + pub struct Perm: u32 { + const NONE = 0; + const READ = 1 << 0; + const WRITE = 1 << 1; + const EXEC = 1 << 2; + } +} + +impl std::fmt::Display for Perm { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + bitflags::parser::to_writer(self, f) + } +} + +impl From for Perm { + fn from(value: u32) -> Self { + Perm::from_bits_truncate(value) + } +} + +impl From for u32 { + fn from(value: Perm) -> Self { + value.bits() + } +} + +/// Represents a contiguous chunk of memory allocated or inspected by the runtime. +pub struct Chunk { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Chunk { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Chunk { + /// Returns the start address of the memory chunk. + pub fn addr(&self) -> u64 { + self.ptr.addr() + } + + /// Returns the size of the memory chunk in bytes. + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Returns the current permissions of the memory chunk. + pub fn permissions(&self) -> Perm { + Perm::from(self.ptr.permissions()) + } + + /// Returns the address of the start of the page containing this chunk. + pub fn page_start(&self) -> u64 { + self.ptr.page_start() + } + + /// Returns the address of the end of the page containing this chunk. + pub fn page_end(&self) -> u64 { + self.ptr.page_end() + } + + /// Changes the permissions of the memory chunk. + pub fn change_permissions(&mut self, perm: Perm) { + self.ptr.pin_mut().change_permissions(perm.into()); + } + + /// Sets the permissions to Execute only. + pub fn make_x(&mut self) { + self.ptr.pin_mut().make_x(); + } + + /// Sets the permissions to Read and Write. + pub fn make_rw(&mut self) { + self.ptr.pin_mut().make_rw(); + } + + /// Sets the permissions to Read and Execute. + pub fn make_rx(&mut self) { + self.ptr.pin_mut().make_rx(); + } + + /// Sets the permissions to Read, Write, and Execute. + pub fn make_rwx(&mut self) { + self.ptr.pin_mut().make_rwx(); + } + + /// Sets the permissions to Read Only. + pub fn make_ro(&mut self) { + self.ptr.pin_mut().make_ro(); + } + + /// Flushes the instruction cache for this memory chunk. + /// This should be used when modifying code in memory (e.g., hooking, JIT). + pub fn cache_flush(&mut self) { + self.ptr.pin_mut().cache_flush(); + } + + pub fn is_valid(&self) -> bool { + self.ptr.is_valid() + } + + /// Deallocates this mmaped memory chunk. + pub fn deallocate(&mut self) -> Result<(), Error> { + to_ok_result!(ffi::runtime_Memory_Chunk::deallocate, self.ptr.pin_mut()); + } +} + +impl std::fmt::Display for Chunk { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +pub struct Memory {} + +impl Memory { + /// Allocates a memory chunk through mmap-like function + pub fn mmap(size: u64, flags: MmapFlags, permission: Perm) -> Option { + into_optional(ffi::runtime_Memory::mmap( + size, + flags.into(), + permission.into(), + )) + } + + /// Allocate a memory chunk through mmap-like function and + /// place the allocation at or near the address given in the first parameter. + /// + /// This address is a **hint**: it is rounded up to the next page boundary + /// (next allocation granularity on Windows) and the system remains free to + /// return a chunk located somewhere else. + pub fn mmap_hint(hint: u64, size: u64, flags: MmapFlags, permission: Perm) -> Option { + into_optional(ffi::runtime_Memory::mmap_hint( + hint, + size, + flags.into(), + permission.into(), + )) + } + + /// Deallocates a mmaped memory chunk + pub fn munmap(chunk: &mut Chunk) -> Result<(), Error> { + to_ok_result!(ffi::runtime_Memory::munmap, chunk.ptr.pin_mut()); + } + + /// Sets the permission of the given memory chunk + pub fn mprotect(chunk: &mut Chunk, perm: Perm) -> Result<(), Error> { + to_ok_result!( + ffi::runtime_Memory::mprotect, + chunk.ptr.pin_mut(), + perm.into() + ); + } + + /// Reads a value of type `T` from a raw memory address. + /// + /// # Safety + /// This function is unsafe and the caller must ensure that the operation is valid + pub unsafe fn read(addr: u64) -> T + where + T: Num + cast::FromPrimitive + cast::ToPrimitive + Clone, + { + let ptr = addr as *const T; + unsafe { (*ptr).clone() } + } + + /// Writes a value of type `T` to a raw memory address. + /// + /// # Safety + /// This function is unsafe and the caller must ensure that the operation is valid + pub unsafe fn write(addr: u64, value: T) + where + T: Num + cast::FromPrimitive + cast::ToPrimitive, + { + let ptr = addr as *mut T; + unsafe { + *ptr = value; + } + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/memory_layout.rs b/vendor/lief/api/rust/crates/lief/src/runtime/memory_layout.rs new file mode 100644 index 0000000..18a33af --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/memory_layout.rs @@ -0,0 +1,75 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_standalone_fwd_iterator; + +/// A contiguous range of memory mapped in the current process. +pub struct Region { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Region { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Region { + /// Name associated with the region: name/path of the module mapped at this + /// address (e.g. `libc.so.6`) or the identifier of a region that is not + /// backed by a file (e.g. `[stack]`, `[heap]`). + /// + /// It can be empty for anonymous regions. + pub fn name(&self) -> String { + self.ptr.name().to_string() + } + + /// Address at which the region starts + pub fn addr(&self) -> u64 { + self.ptr.addr() + } + + /// Size of the region + pub fn size(&self) -> u64 { + self.ptr.size() + } + + /// Address at which the region ends + pub fn end_addr(&self) -> u64 { + self.ptr.end_addr() + } + + /// Whether the given address is within this region + pub fn contains(&self, addr: u64) -> bool { + self.ptr.contains(addr) + } +} + +impl std::fmt::Display for Region { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +impl std::fmt::Debug for Region { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + f.debug_struct("Region") + .field("name", &self.name()) + .field("addr", &self.addr()) + .field("size", &self.size()) + .field("end_addr", &self.end_addr()) + .finish() + } +} + +/// Return an iterator over the memory layout of the current process +pub fn memory_layout() -> RegionsIt { + RegionsIt::new(ffi::runtime_memory_layout()) +} + +declare_standalone_fwd_iterator!( + RegionsIt, + Region, + ffi::runtime_MemoryLayout_Region, + ffi::runtime_it_memory_layout +); diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/module.rs b/vendor/lief/api/rust/crates/lief/src/runtime/module.rs new file mode 100644 index 0000000..5b227b1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/module.rs @@ -0,0 +1,162 @@ +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::declare_standalone_fwd_iterator; +use std::path::Path; + +use super::android; +use super::linux; +use super::osx; +use super::windows; + +/// This trait is shared by all system-specific modules. +/// It provides a common interface for accessing module metadata. +pub trait Module { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module; + + /// Name of the module (e.g. `libc.so.6, kernel32.dll, libsystem_c.dylib`) + fn name(&self) -> String { + self.as_generic().name().to_string() + } + + /// Absolute path to the module file + fn path(&self) -> String { + self.as_generic().path().to_string() + } + + /// Base address where the module is loaded in memory + fn imagebase(&self) -> u64 { + self.as_generic().imagebase() + } + + /// Virtual size of the current module + fn size(&self) -> u64 { + self.as_generic().size() + } + + /// End address of the module + fn end(&self) -> u64 { + self.as_generic().end() + } + + /// Check if the current module contains the given address + fn contains(&self, addr: u64) -> bool { + self.as_generic().contains(addr) + } + + /// Return the content of the module as it is currently mapped in memory. + /// + /// The returned buffer spans [`Module::imagebase`] over [`Module::size`] + /// bytes. An empty buffer is returned if the imagebase or the size is null. + fn dump(&self) -> Vec { + let base = self.imagebase(); + let size = self.size() as usize; + if base == 0 || size == 0 { + return Vec::new(); + } + unsafe { std::slice::from_raw_parts(base as *const u8, size).to_vec() } + } + + /// Same as [`Module::dump`] but also write the content into the file + /// located at `path`. + fn dump_to_file>(&self, path: P) -> Vec { + let data = self.dump(); + let _ = std::fs::write(path, &data); + data + } +} + +/// Enum for the modules whose value depends on the current platform +pub enum Modules { + /// A Linux module + Linux(linux::Module), + + /// A Windows module + Windows(windows::Module), + + /// An Android module + Android(android::Module), + + /// An OSX module + Osx(osx::Module), +} + +impl FromFFI for Modules { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + unsafe { + let mod_ref = ptr.as_ref().unwrap(); + if ffi::runtime_linux_Module::classof(mod_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Modules::Linux(linux::Module::from_ffi(raw)); + } else if ffi::runtime_windows_Module::classof(mod_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Modules::Windows(windows::Module::from_ffi(raw)); + } else if ffi::runtime_android_Module::classof(mod_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Modules::Android(android::Module::from_ffi(raw)); + } else if ffi::runtime_osx_Module::classof(mod_ref) { + let raw = { + type From = cxx::UniquePtr; + type To = cxx::UniquePtr; + std::mem::transmute::(ptr) + }; + return Modules::Osx(osx::Module::from_ffi(raw)); + } + panic!("Unsupported module") + } + } +} + +impl Module for Modules { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module { + match &self { + Modules::Linux(module) => module.as_generic(), + Modules::Windows(module) => module.as_generic(), + Modules::Android(module) => module.as_generic(), + Modules::Osx(module) => module.as_generic(), + } + } +} + +/// Return an iterator over the different modules loaded in the current process. +pub fn modules() -> ModulesIt { + ModulesIt::new(ffi::runtime_modules()) +} + +/// Find the module with the given name +pub fn module_from_name(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_module_from_name(&s)) +} + +/// Find the module with the given name +pub fn module_from_path>(path: P) -> Option { + cxx::let_cxx_string!(s = path.as_ref().to_str().unwrap()); + into_optional(ffi::runtime_module_from_path(&s)) +} + +/// Find the module that encompasses the given virtual address (absolute) +pub fn module_from_addr(addr: u64) -> Option { + into_optional(ffi::runtime_module_from_addr(addr)) +} + +declare_standalone_fwd_iterator!( + ModulesIt, + Modules, + ffi::runtime_Module, + ffi::runtime_it_modules +); diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/osx.rs b/vendor/lief/api/rust/crates/lief/src/runtime/osx.rs new file mode 100644 index 0000000..e6fa4d1 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/osx.rs @@ -0,0 +1,18 @@ +pub mod host; +pub mod module; +pub mod process; + +#[doc(inline)] +pub use module::Module; + +#[doc(inline)] +pub use module::dlopen; + +#[doc(inline)] +pub use host::Host; + +#[doc(inline)] +pub use process::Process; + +#[doc(inline)] +pub use host::Version; diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/osx/host.rs b/vendor/lief/api/rust/crates/lief/src/runtime/osx/host.rs new file mode 100644 index 0000000..a15b0d3 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/osx/host.rs @@ -0,0 +1,98 @@ +use lief_ffi as ffi; +use std::fmt; + +/// Represents a macOS version number (major.minor.patch). +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct Version { + pub major: u32, + pub minor: u32, + pub patch: u32, +} + +impl Version { + pub fn new(major: u32, minor: u32, patch: u32) -> Self { + Self { + major, + minor, + patch, + } + } + + fn from_ffi(v: cxx::UniquePtr) -> Self { + Self { + major: v.get_major(), + minor: v.get_minor(), + patch: v.get_patch(), + } + } + + /// macOS Big Sur (11.0) + pub fn big_sur() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::big_sur()) + } + + /// macOS Monterey (12.0) + pub fn monterey() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::monterey()) + } + + /// macOS Ventura (13.0) + pub fn ventura() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::ventura()) + } + + /// macOS Sonoma (14.0) + pub fn sonoma() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::sonoma()) + } + + /// macOS Sequoia (15.0) + pub fn sequoia() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::sequoia()) + } + + /// macOS Tahoe (26.0) + pub fn tahoe() -> Self { + Self::from_ffi(ffi::runtime_osx_Host_version_t::tahoe()) + } +} + +impl PartialOrd for Version { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for Version { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + (self.major, self.minor, self.patch).cmp(&(other.major, other.minor, other.patch)) + } +} + +impl fmt::Display for Version { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}.{}.{}", self.major, self.minor, self.patch) + } +} + +/// This structure exposes OSX-specific host information. +pub struct Host {} + +impl Host { + /// The operating system version string + pub fn os_version_name() -> String { + ffi::runtime_osx_Host::os_version_name().to_string() + } + + /// The operating system version as a [`Version`] + pub fn os_version() -> Version { + Version::from_ffi(ffi::runtime_osx_Host_version_t::os_version()) + } + + /// Whether System Integrity Protection (SIP) is enabled on this host. + /// + /// This conservatively returns `true` when the status can't be determined. + pub fn is_sip_enabled() -> bool { + ffi::runtime_osx_Host::is_sip_enabled() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/osx/module.rs b/vendor/lief/api/rust/crates/lief/src/runtime/osx/module.rs new file mode 100644 index 0000000..e1cba5f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/osx/module.rs @@ -0,0 +1,62 @@ +use std::ffi::c_void; + +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::macho::Binary; +use crate::runtime; + +/// This structure represents an OSX-specific module +pub struct Module { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Module { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Module { + /// Instantiate a [`Module`] from the given `dlopen` handle. + pub fn from_handle(handle: *const c_void) -> Option { + into_optional(ffi::runtime_osx_Module::from_handle(handle as u64)) + } + + /// Return the `dlopen` handle for this library as an opaque pointer. + /// + /// Return a null pointer if the function fails or if the handler can't be + /// found. + pub fn handle(&self) -> *const c_void { + self.ptr.handle() as *const c_void + } + + /// Resolve the symbol with the given name for the current module + pub fn dlsym(&self, name: String) -> *const c_void { + cxx::let_cxx_string!(s = name); + self.ptr.dlsym(&s) as *const c_void + } + + /// Parse the Mach-O module from its path on the filesystem + pub fn parse_from_path(&self) -> Option { + into_optional(self.ptr.parse_from_path()) + } + + /// Parse the Mach-O module from memory + pub fn parse_from_memory(&self) -> Option { + into_optional(self.ptr.parse_from_memory()) + } +} + +impl runtime::Module for Module { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Load the library with the given path or name +pub fn dlopen(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_osx_dlopen(&s)) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/osx/process.rs b/vendor/lief/api/rust/crates/lief/src/runtime/osx/process.rs new file mode 100644 index 0000000..edb6c59 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/osx/process.rs @@ -0,0 +1,11 @@ +use lief_ffi as ffi; + +/// This structure exposes OSX-specific API for the current process. +pub struct Process {} + +impl Process { + /// Return the version of dyld for the current process + pub fn dyld_version() -> String { + ffi::runtime_osx_Process::dyld_version().to_string() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/process.rs b/vendor/lief/api/rust/crates/lief/src/runtime/process.rs new file mode 100644 index 0000000..4faf22c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/process.rs @@ -0,0 +1,51 @@ +use super::{Arch, Platform}; +use lief_ffi as ffi; + +/// This structure represents the current process and provides functions to query process-level +/// information. +pub struct Process {} + +impl Process { + /// Get the Process ID of the current process. + pub fn pid() -> i32 { + ffi::runtime_Process::pid() + } + + /// Get the Thread ID of the current thread. + pub fn tid() -> i32 { + ffi::runtime_Process::tid() + } + + /// Return the number of bytes in a memory page. + /// + /// For instance: + /// * `0x1000` (4096 bytes) for x86_64 + /// * `0x4000` (16384 bytes) for ARM64 + pub fn page_size() -> u32 { + ffi::runtime_Process::page_size() + } + + /// Target architecture of the current process + pub fn arch() -> Arch { + Arch::from(ffi::runtime_Process::arch()) + } + + /// Target platform of the current process + pub fn platform() -> Platform { + Platform::from(ffi::runtime_Process::platform()) + } + + /// Return the value of the environment variable `key` for the current + /// process, or `None` if it is not set (or not valid Unicode). + pub fn get_env(key: &str) -> Option { + std::env::var(key).ok() + } + + /// Return all the environment variables of the current process as a + /// `name -> value` map. + pub fn get_envs() -> std::collections::HashMap { + std::env::vars_os() + .filter_map(|(key, value)| Some((key.into_string().ok()?, value.into_string().ok()?))) + .collect() + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows.rs new file mode 100644 index 0000000..b58ec55 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows.rs @@ -0,0 +1,20 @@ +pub mod host; +pub mod ldr_data_table_entry; +pub mod module; +pub mod peb; +pub mod process; + +#[doc(inline)] +pub use host::{Host, Version}; + +#[doc(inline)] +pub use ldr_data_table_entry::{LdrDataTableEntries, LdrDataTableEntry}; + +#[doc(inline)] +pub use module::{Module, dlopen, find_module}; + +#[doc(inline)] +pub use peb::PEB; + +#[doc(inline)] +pub use process::Process; diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows/host.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows/host.rs new file mode 100644 index 0000000..99615eb --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows/host.rs @@ -0,0 +1,61 @@ +use lief_ffi as ffi; +use std::fmt; + +/// Represents a Windows version number +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct Version { + pub major: u32, + pub minor: u32, + pub build_number: u32, +} + +impl Version { + pub fn new(major: u32, minor: u32, build_number: u32) -> Self { + Self { + major, + minor, + build_number, + } + } + + fn from_ffi(v: cxx::UniquePtr) -> Self { + Self { + major: v.get_major(), + minor: v.get_minor(), + build_number: v.get_build_number(), + } + } +} + +impl PartialOrd for Version { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for Version { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + (self.major, self.minor, self.build_number).cmp(&( + other.major, + other.minor, + other.build_number, + )) + } +} + +impl fmt::Display for Version { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}.{}.{}", self.major, self.minor, self.build_number) + } +} + +/// This structure exposes Windows-specific host information. +pub struct Host {} + +impl Host { + /// Return the Windows version (e.g., `10.0.26200`) + pub fn version() -> Option { + Some(Version::from_ffi(ffi::runtime_windows_Host::version())) + .filter(|v| v.major > 0 || v.minor > 0 || v.build_number > 0) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows/ldr_data_table_entry.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows/ldr_data_table_entry.rs new file mode 100644 index 0000000..85e0586 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows/ldr_data_table_entry.rs @@ -0,0 +1,231 @@ +use lief_ffi as ffi; + +use crate::common::FromFFI; +use crate::declare_standalone_fwd_iterator; +use crate::to_opt; + +/// This structure exposes a user-friendly interface over a `LDR_DATA_TABLE_ENTRY`, +/// the structure used by the Windows loader to describe a module loaded in the +/// current process. +/// +/// These entries can be enumerated through [`super::PEB::entries`]. +pub struct LdrDataTableEntry { + ptr: cxx::UniquePtr, +} + +impl FromFFI for LdrDataTableEntry { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl LdrDataTableEntry { + /// Base address at which the module is mapped in memory (`DllBase`). + pub fn dll_base(&self) -> u64 { + self.ptr.dll_base() + } + + /// Address of the entry point of the module (`EntryPoint`). + pub fn entry_point(&self) -> u64 { + self.ptr.entry_point() + } + + /// Size (in bytes) of the module's image in memory (`SizeOfImage`). + pub fn size_of_image(&self) -> u32 { + self.ptr.size_of_image() + } + + /// Full path of the module (`FullDllName`), + /// e.g. `C:\Windows\System32\ntdll.dll`. + pub fn full_dll_name(&self) -> String { + self.ptr.full_dll_name().to_string() + } + + /// Base name of the module (`BaseDllName`), e.g. `ntdll.dll`. + pub fn base_dll_name(&self) -> String { + self.ptr.base_dll_name().to_string() + } + + /// Loader flags describing the state of the module (`Flags`). + pub fn flags(&self) -> u32 { + self.ptr.flags() + } + + /// Legacy load count of the module (`ObsoleteLoadCount`). Superseded by + /// [`LdrDataTableEntry::reference_count`] on Windows 8 and later. + pub fn obsolete_load_count(&self) -> u16 { + self.ptr.obsolete_load_count() + } + + /// TLS slot index assigned to the module, or `0` when it has no TLS + /// (`TlsIndex`). + pub fn tls_index(&self) -> u16 { + self.ptr.tls_index() + } + + /// `TimeDateStamp` of the module as cached by the loader. + pub fn time_date_stamp(&self) -> u32 { + self.ptr.time_date_stamp() + } + + /// Address of the activation context associated with the module's entry + /// point. + pub fn entry_point_activation_context(&self) -> u64 { + self.ptr.entry_point_activation_context() + } + + /// Address of the per-entry loader lock. + pub fn lock(&self) -> u64 { + self.ptr.lock() + } + + /// Address of the dependency-graph node of the module (`DdagNode`). + /// + /// Available on Windows 8 and later. + pub fn ddag_node(&self) -> Option { + to_opt!(&ffi::runtime_windows_LdrDataTableEntry::ddag_node, &self); + } + + /// Address of the loader context used while the module is being snapped + /// + /// Available on Windows 8 and later. + pub fn load_context(&self) -> Option { + to_opt!(&ffi::runtime_windows_LdrDataTableEntry::load_context, &self); + } + + /// Base address of the module that triggered the load of this one. + /// + /// Available on Windows 8 and later. + pub fn parent_dll_base(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::parent_dll_base, + &self + ); + } + + /// Address of the CHPE switch-back context. + /// + /// Available on Windows 8 and later. + pub fn switch_back_context(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::switch_back_context, + &self + ); + } + + /// Preferred base address recorded in the PE headers + /// + /// Available on Windows 8 and later. + pub fn original_base(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::original_base, + &self + ); + } + + /// Time at which the module was loaded. + /// + /// Available on Windows 8 and later. + pub fn load_time(&self) -> Option { + to_opt!(&ffi::runtime_windows_LdrDataTableEntry::load_time, &self); + } + + /// Hash of the module's base name used to index the loader tables + /// + /// Available on Windows 8 and later. + pub fn base_name_hash_value(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::base_name_hash_value, + &self + ); + } + + /// Reason why the module was loaded, as a `LDR_DLL_LOAD_REASON` value + /// + /// Available on Windows 8 and later. + pub fn load_reason(&self) -> Option { + to_opt!(&ffi::runtime_windows_LdrDataTableEntry::load_reason, &self); + } + + /// Path-search options implied when the module was resolved + /// + /// Available on Windows 8 and later. + pub fn implicit_path_options(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::implicit_path_options, + &self + ); + } + + /// Number of references currently held on the module. + /// + /// Available on Windows 8 and later. + pub fn reference_count(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::reference_count, + &self + ); + } + + /// Flags controlling how the statically-linked dependencies of the module + /// are loaded. + /// + /// Available on Windows 8 and later. + pub fn dependent_load_flags(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::dependent_load_flags, + &self + ); + } + + /// Signing level of the module's image, as a `SE_SIGNING_LEVEL` value + /// + /// Available on Windows 10 and later. + pub fn signing_level(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::signing_level, + &self + ); + } + + /// Image checksum cached by the loader + /// + /// Available on Windows 10 and later. + pub fn check_sum(&self) -> Option { + to_opt!(&ffi::runtime_windows_LdrDataTableEntry::check_sum, &self); + } + + /// Base address of the active hot-patch image, if any. + /// + /// Available on Windows 11 and later. + pub fn active_patch_image_base(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::active_patch_image_base, + &self + ); + } + + /// State of the hot-patch engine for this module, as a + /// `LDR_HOT_PATCH_STATE` value. + /// + /// Available on Windows 11 and later. + pub fn hot_patch_state(&self) -> Option { + to_opt!( + &ffi::runtime_windows_LdrDataTableEntry::hot_patch_state, + &self + ); + } +} + +impl std::fmt::Display for LdrDataTableEntry { + fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(f, "{}", self.ptr.to_string()) + } +} + +declare_standalone_fwd_iterator!( + LdrDataTableEntries, + LdrDataTableEntry, + ffi::runtime_windows_LdrDataTableEntry, + ffi::runtime_windows_it_ldr_data_table_entry +); diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows/module.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows/module.rs new file mode 100644 index 0000000..36e4072 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows/module.rs @@ -0,0 +1,93 @@ +use std::ffi::c_void; + +use lief_ffi as ffi; + +use crate::common::{FromFFI, into_optional}; +use crate::pe::{Binary, ParserConfig}; +use crate::runtime; + +/// This structure represents a Windows-specific module +pub struct Module { + ptr: cxx::UniquePtr, +} + +impl FromFFI for Module { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl Module { + /// Return the `HMODULE` handle as an opaque pointer. + /// + /// Return a nullptr if the function fails or if the handler can't be found + pub fn handle(&self) -> *const c_void { + self.ptr.handle() as *const c_void + } + + /// Resolve the symbol with the given name for the current module + pub fn dlsym(&self, name: String) -> *const c_void { + cxx::let_cxx_string!(s = name); + self.ptr.dlsym(&s) as *const c_void + } + + /// Parse the PE module from its path on the filesystem + pub fn parse_from_path(&self) -> Option { + into_optional(self.ptr.parse_from_path()) + } + + /// Parse the PE module from its path on the filesystem and given the parser + /// configuration + pub fn parse_from_path_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_path_with_config(&config.to_ffi())) + } + + /// Parse the PE module from memory + pub fn parse_from_memory(&self) -> Option { + into_optional(self.ptr.parse_from_memory()) + } + + /// Parse the PE module from memory with the given configuration + pub fn parse_from_memory_with_config(&self, config: &ParserConfig) -> Option { + into_optional(self.ptr.parse_from_memory_with_config(&config.to_ffi())) + } +} + +impl runtime::Module for Module { + #[doc(hidden)] + fn as_generic(&self) -> &ffi::runtime_Module { + self.ptr.as_ref().unwrap().as_ref() + } +} + +/// Load the module (DLL) with the given `name` into the current process and +/// wrap the resulting handle in a [`Module`]. +/// +/// ```rust,no_run +/// if let Some(kernel32) = lief::runtime::windows::dlopen("kernel32.dll") { +/// println!("{}", kernel32.path()); +/// } +/// ``` +/// +/// This function relies on the Windows API `LoadLibrary`. To get a handle on a +/// module that is *already* loaded, prefer [`find_module`]. +pub fn dlopen(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_windows_dlopen(&s)) +} + +/// Try to get the [`Module`] with the given name. +/// +/// ```rust,no_run +/// if let Some(ntdll) = lief::runtime::windows::find_module("ntdll.dll") { +/// println!("{}", ntdll.path()); +/// } +/// ``` +/// +/// This function relies on the Windows API `GetModuleHandle` which is more +/// efficient than the generic implementation +/// [`crate::runtime::module_from_name`]. +pub fn find_module(name: &str) -> Option { + cxx::let_cxx_string!(s = name); + into_optional(ffi::runtime_windows_find_module(&s)) +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows/peb.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows/peb.rs new file mode 100644 index 0000000..db8f9f7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows/peb.rs @@ -0,0 +1,67 @@ +use lief_ffi as ffi; + +use super::ldr_data_table_entry::LdrDataTableEntries; +use crate::common::FromFFI; + +/// This structure exposes a user-friendly interface over the Process +/// Environment Block (PEB) of the current process. +/// +/// It can be accessed through [`super::Process::peb`]. +pub struct PEB { + ptr: cxx::UniquePtr, +} + +impl FromFFI for PEB { + fn from_ffi(ptr: cxx::UniquePtr) -> Self { + Self { ptr } + } +} + +impl PEB { + /// Whether the current process is being debugged. + /// + /// This mirrors the `BeingDebugged` field of the PEB and is equivalent to + /// the result of the `IsDebuggerPresent()` API. + pub fn being_debugged(&self) -> bool { + self.ptr.being_debugged() + } + + /// Address of the loader data structure (`PEB_LDR_DATA`) which holds the + /// list of the modules loaded in the current process. + pub fn ldr(&self) -> u64 { + self.ptr.ldr() + } + + /// Address of the process parameters (`RTL_USER_PROCESS_PARAMETERS`) which + /// holds information such as the command line or the current directory. + pub fn process_parameters(&self) -> u64 { + self.ptr.process_parameters() + } + + /// Address of the per-process ATL thunk SList (single-linked list). + pub fn atl_thunk_slist_ptr(&self) -> u64 { + self.ptr.atl_thunk_slist_ptr() + } + + /// 32-bit value of the ATL thunk SList pointer. + pub fn atl_thunk_slist_ptr32(&self) -> u32 { + self.ptr.atl_thunk_slist_ptr32() + } + + /// Address of the routine called once the process completed its + /// initialization (`PostProcessInitRoutine`). + pub fn post_process_init_routine(&self) -> u64 { + self.ptr.post_process_init_routine() + } + + /// Session ID associated with the current process. + pub fn session_id(&self) -> u32 { + self.ptr.session_id() + } + + /// Return a forward iterator over the modules referenced by the loader + /// data (`Ldr`) of the PEB, in load order. + pub fn entries(&self) -> LdrDataTableEntries { + LdrDataTableEntries::new(self.ptr.entries()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/src/runtime/windows/process.rs b/vendor/lief/api/rust/crates/lief/src/runtime/windows/process.rs new file mode 100644 index 0000000..89a2897 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/src/runtime/windows/process.rs @@ -0,0 +1,15 @@ +use lief_ffi as ffi; + +use super::PEB; +use crate::common::into_optional; + +/// This structure exposes Windows-specific API for the current process. +pub struct Process {} + +impl Process { + /// Return an interface over the internal Process Environment Block (PEB) + /// of the current process. + pub fn peb() -> Option { + into_optional(ffi::runtime_windows_Process::peb()) + } +} diff --git a/vendor/lief/api/rust/crates/lief/tests/assembler_test.rs b/vendor/lief/api/rust/crates/lief/tests/assembler_test.rs new file mode 100644 index 0000000..e214311 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/assembler_test.rs @@ -0,0 +1,129 @@ +#![allow(warnings)] +mod utils; +use lief; +use lief::assembly::{Instruction, Instructions}; +use lief::dwarf::types::{Base, ClassLike, DwarfType}; +use lief::dwarf::{Parameter, Scope, Type}; +use lief::generic::{Binary, Section}; + +use std::path::{Path, PathBuf}; +use std::sync::Arc; +fn get_binary(name: &str) -> lief::Binary { + let path = utils::get_sample(Path::new(name)).unwrap(); + let path_str = path.to_str().unwrap(); + + let bin = lief::Binary::parse(path_str); + bin.unwrap() +} + +fn should_skip(inst: &lief::assembly::Instructions) -> bool { + if let lief::assembly::Instructions::X86(x86) = inst { + if let opcode = x86.opcode() { + return opcode == lief::assembly::x86::Opcode::JCC_1 + || opcode == lief::assembly::x86::Opcode::JCC_2 + || opcode == lief::assembly::x86::Opcode::JCC_4 + || opcode == lief::assembly::x86::Opcode::JMP_1 + || opcode == lief::assembly::x86::Opcode::JMP_2 + || opcode == lief::assembly::x86::Opcode::JMP_4 + || opcode == lief::assembly::x86::Opcode::CALL64pcrel32 + || opcode == lief::assembly::x86::Opcode::CALLpcrel32; + } + } + return false; +} + +fn assemble_inst( + name: &str, + bin: &mut dyn lief::generic::Binary, + inst: &lief::assembly::Instructions, +) { + println!("{}: {:02X?}", inst.to_string(), inst.raw()); + if should_skip(inst) { + return; + } + let raw = bin.assemble(inst.address(), &inst.to_string_no_address()); + let new_inst = bin + .disassemble_slice(raw.as_slice(), inst.address()) + .next() + .unwrap(); + assert_eq!(new_inst.to_string_no_address(), inst.to_string_no_address()); +} + +fn reassemble_from(name: &str, address: u64, count: usize) { + let mut bin = get_binary(name); + match bin { + lief::Binary::ELF(mut elf) => { + let insts = elf + .disassemble_address(address) + .take(count) + .collect::>(); + + for inst in insts { + assemble_inst(name, &mut elf, &inst); + } + } + + lief::Binary::PE(mut pe) => { + let insts = pe + .disassemble_address(address) + .take(count) + .collect::>(); + + for inst in insts { + assemble_inst(name, &mut pe, &inst); + } + } + + lief::Binary::MachO(fat) => { + for mut macho in fat.iter() { + let insts = macho + .disassemble_address(address) + .take(count) + .collect::>(); + + for inst in insts { + assemble_inst(name, &mut macho, &inst); + } + } + } + lief::Binary::COFF(_) => { + todo!(); + } + } +} +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + + reassemble_from("MachO/ios17/DebugHierarchyKit", 0x16650, 100); // ARM64E + //reassemble_from("MachO/macho-issue-1110.bin", 0x00000b10, 10); // PPC + reassemble_from("PE/ntoskrnl.exe", 0x140200000, 300); + reassemble_from("ELF/ELF32_x86_library_libshellx.so", 0x000010c0, 300); + //reassemble_from("ELF/libmonochrome-armv7.so", 0x0468b701, 300); // Thumb + //reassemble_from("ELF/i872_risv.elf", 0x80000000, 300); + + if let lief::Binary::PE(mut pe) = get_binary("PE/ntoskrnl.exe") { + let imagebase = pe.imagebase(); + + let mut config = lief::assembly::AssemblerConfig::default(); + + let entrypoint = pe.entrypoint(); + let resolver = Arc::new(move |symbol: &str| { + if symbol == "entrypoint" { + return Some(entrypoint); + } + None + }); + + config.symbol_resolver = Some(resolver); + pe.assemble_with_config( + pe.entrypoint() - imagebase, + r#" + call entrypoint + "#, + &config, + ); + } +} diff --git a/vendor/lief/api/rust/crates/lief/tests/coff_tests.rs b/vendor/lief/api/rust/crates/lief/tests/coff_tests.rs new file mode 100644 index 0000000..b5e5322 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/coff_tests.rs @@ -0,0 +1,106 @@ +#![allow(warnings)] +mod utils; +use lief::generic::{Section, Symbol}; +use lief::logging; +use std::env; +use std::fmt::format; + +fn explore_coff(bin_name: &str, coff: &lief::coff::Binary) { + match coff.header() { + lief::coff::Header::BigObj(big) => { + format!("{:?}{}", big, big); + } + lief::coff::Header::Regular(regular) => { + format!("{:?}{}", regular, regular); + } + } + + for section in coff.sections() { + format!("{section:?} {section}"); + format!("nb relocs: {}", section.relocations().len()); + assert!(coff.section_by_name(§ion.name()).is_some()); + for symbol in section.symbols() { + format!("{symbol:?} {symbol}"); + } + if let Some(comdat) = section.comdat_info() { + format!("{comdat:?}"); + } + } + + for symbol in coff.symbols() { + format!("{symbol:?} {symbol}"); + for aux in symbol.auxiliary_symbols() { + format!("{aux:?}"); + } + if let Some(section) = symbol.section() { + format!("{section:?} {section}"); + } + } + + for relocation in coff.relocations() { + format!("{relocation:?} {relocation}"); + if let Some(section) = relocation.section() { + format!("{}", section.name()); + } + if let Some(symbol) = relocation.symbol() { + format!("{}", symbol.name()); + } + } + + for function in coff.functions() { + format!("{function:?} {function}"); + } + + assert!(coff.find_string(0).is_none()); + assert!(coff.find_string(4).is_some()); + assert!(coff.section_by_name("").is_none()); +} + +fn test_with(bin_name: &str) { + let path = utils::get_coff_sample(bin_name).unwrap(); + let path_str = path.to_str(); + if let Some(coff) = lief::coff::Binary::parse(path_str.unwrap()) { + explore_coff(bin_name, &coff); + } +} + +#[test] +fn test_api() { + let mut dir = env::temp_dir(); + dir.push("lief_coff_test.log"); + logging::set_path(dir.as_path()); + + test_with("psetargv.obj"); + test_with("comdata_tls_msvc.obj"); + test_with("comdata_tls.obj"); + test_with("x64_debug_cl_bigobj_gl.obj"); + test_with("x64_debug_cl_bigobj.obj"); + test_with("x64_debug_cl.obj"); + test_with("arm64_debug_cl_bigobj.obj"); + test_with("arm64_debug_cl.obj"); +} + +#[test] +fn test_section_by_name() { + let path = utils::get_coff_sample("arm64_debug_cl.obj").unwrap(); + let coff = lief::coff::Binary::parse(path.to_str().unwrap()).unwrap(); + + assert!(coff.section_by_name("").is_none()); + + let section = coff.section_by_name(".drectve").unwrap(); + assert_eq!(section.name(), ".drectve"); + assert_eq!(section.sizeof_raw_data(), 0x91); + assert!(section.coff_string().is_none()); + + let path = utils::get_coff_sample("dwarf.obj").unwrap(); + let coff = lief::coff::Binary::parse(path.to_str().unwrap()).unwrap(); + + let section = coff.section_by_name(".debug_rnglists").unwrap(); + assert_eq!(section.name(), "/18"); + assert_eq!(section.coff_string().unwrap().str(), ".debug_rnglists"); + + let section = coff.section_by_name("/18").unwrap(); + assert_eq!(section.coff_string().unwrap().str(), ".debug_rnglists"); + + assert!(coff.section_by_name(".debug_line").is_none()); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/disassembler_test.rs b/vendor/lief/api/rust/crates/lief/tests/disassembler_test.rs new file mode 100644 index 0000000..7fd0874 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/disassembler_test.rs @@ -0,0 +1,225 @@ +#![allow(warnings)] +mod utils; +use lief; +use lief::assembly::x86; +use lief::assembly::x86::Operand; +use lief::assembly::{Instruction, Instructions}; +use lief::dwarf::types::{Base, ClassLike, DwarfType}; +use lief::dwarf::{Parameter, Scope, Type}; +use lief::generic::{Binary, Section}; + +use std::path::{Path, PathBuf}; + +fn process_instruction(inst: &lief::assembly::Instructions) { + //println!("{} {:#02x?}", inst.to_string(), inst.raw()); + println!("{}", inst.to_string()); + format!( + "{} {} {} {}", + inst.address(), + inst.size(), + inst.raw().len(), + inst.mnemonic() + ); + format!("{}", inst.to_string()); + format!( + "{:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?} {:?}", + inst.is_call(), + inst.is_syscall(), + inst.is_terminator(), + inst.is_branch(), + inst.is_memory_access(), + inst.is_move_reg(), + inst.is_add(), + inst.is_trap(), + inst.is_barrier(), + inst.is_return(), + inst.is_indirect_branch(), + inst.is_conditional_branch(), + inst.is_compare(), + inst.is_move_immediate(), + inst.is_bitcast(), + inst.memory_access(), + inst.branch_target().unwrap_or(0) + ); + match inst { + Instructions::AArch64(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::ARM(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::X86(variant) => { + //println!("{}", inst.to_string()); + format!("{:?}", variant.opcode()); + format!( + "{:?} {:?} {:?}", + variant.has_lock_prefix(), + variant.is_lockable(), + variant.is_atomic() + ); + if let Some(locked) = variant.lock() { + format!("{}", locked.to_string()); + } + if let Some(unlocked) = variant.unlock() { + format!("{}", unlocked.to_string()); + } + for op in variant.operands() { + format!("{}", op.to_string()); + match op { + x86::Operands::Reg(reg) => { + format!("{:?}", reg.value()); + } + + x86::Operands::Imm(imm) => { + format!("{}", imm.value()); + } + + x86::Operands::PCRelative(pcr) => { + format!("{}", pcr.value()); + } + + x86::Operands::Mem(mem) => { + format!( + "{:?}{:?}{:?}{}{}", + mem.base(), + mem.scaled_register(), + mem.segment_register(), + mem.scale(), + mem.displacement() + ); + } + x86::Operands::Unknown(_) => {} + } + } + } + Instructions::Mips(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::PowerPC(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::EBPF(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::RiscV(variant) => { + format!("{:?}", variant.opcode()); + } + Instructions::Generic(_) => {} + } +} + +fn get_binary(name: &str) -> lief::Binary { + let path = utils::get_sample(Path::new(name)).unwrap(); + let path_str = path.to_str().unwrap(); + + let bin = lief::Binary::parse(path_str); + bin.unwrap() +} + +fn disa_from_address(name: &str, address: u64) { + let bin = get_binary(name); + + match bin { + lief::Binary::ELF(elf) => { + for inst in elf.disassemble_address(address) { + process_instruction(&inst); + } + } + + lief::Binary::PE(pe) => { + for inst in pe.disassemble_address(address) { + process_instruction(&inst); + } + } + + lief::Binary::MachO(fat) => { + for macho in fat.iter() { + for inst in macho.disassemble_address(address) { + process_instruction(&inst); + } + } + } + lief::Binary::COFF(_) => { + todo!(); + } + } +} + +fn disa_from_symbol(name: &str, symbol: &str) { + let bin = get_binary(name); + + match bin { + lief::Binary::ELF(elf) => { + for inst in elf.disassemble_symbol(symbol) { + process_instruction(&inst); + } + } + + lief::Binary::PE(pe) => { + for inst in pe.disassemble_symbol(symbol) { + process_instruction(&inst); + } + } + + lief::Binary::MachO(fat) => { + for macho in fat.iter() { + for inst in macho.disassemble_symbol(symbol) { + process_instruction(&inst); + } + } + } + lief::Binary::COFF(_) => { + todo!(); + } + } +} + +#[test] +fn test_from_slice() { + if !lief::is_extended() { + return; + } + + if let lief::Binary::ELF(elf) = get_binary("ELF/hello.bpf.o") { + let section = elf.section_by_name("tp/syscalls/sys_enter_write").unwrap(); + for inst in elf.disassemble_slice(section.content(), 0x100) { + process_instruction(&inst); + } + } +} + +#[test] +fn test_upx() { + if !lief::is_extended() { + return; + } + + if let lief::Binary::PE(pe) = get_binary("PE/PE32_x86_binary_cmd-upx.exe") { + let section = pe.section_by_name("UPX1").unwrap(); + let delta = 0x4ad4ee70 - 0x4ad3c000; + for inst in pe.disassemble_slice(§ion.content()[delta..], 0x4ad4ee70) { + process_instruction(&inst); + } + } +} + +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + + disa_from_symbol("ELF/libmonochrome-armv7.so", "Java_J_N_MENF59pO"); + disa_from_address("MachO/MachO32_ARM_binary_data-in-code-LLVM.bin", 0); + disa_from_address("ELF/echo.mips_r3000.bin", 0x00403664); + disa_from_address("MachO/macho-issue-1110.bin", 0x00000b10); + disa_from_address("ELF/i872_risv.elf", 0x80000000); + disa_from_address("ELF/elf_reader.riscv32.elf", 0x0001e810); + disa_from_address("PE/PE32_x86_binary_cmd-upx.exe", 0x0001e810); + disa_from_address("PE/ntoskrnl.exe", 0x140200000); + disa_from_address("ELF/ELF32_x86_library_libshellx.so", 0x000010c0); + disa_from_address("ELF/ELF64_x86-64_binary_static-binary.bin", 0x00400cdd); + disa_from_address("MachO/FAT_MachO_x86_x86-64_library_libdyld.dylib", 0x1141); + disa_from_address("MachO/FAT_MachO_x86_x86-64_library_libdyld.dylib", 0x1108); + disa_from_address("MachO/ios17/DebugHierarchyKit", 0x16650); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/dwarf_editor_tests.rs b/vendor/lief/api/rust/crates/lief/tests/dwarf_editor_tests.rs new file mode 100644 index 0000000..53b326e --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/dwarf_editor_tests.rs @@ -0,0 +1,85 @@ +#![allow(warnings)] +mod utils; +use lief; +use lief::dwarf::editor::types::EditorType; + +use std::env; +use std::path::Path; + +fn test_with_str(_: &str, path_str: &str) { + if let Some(lief::Binary::PE(mut bin)) = lief::Binary::parse(path_str) { + let mut editor = lief::dwarf::Editor::from_binary(&mut bin).expect("Can't load editor"); + { + let mut unit = editor.create_compile_unit().unwrap(); + unit.set_producer("LIEF Rust test (CU#1)"); + + { + let mut func_1 = unit.create_function("func_1").unwrap(); + func_1.set_address(0x1000); + func_1.set_return_type(&unit.create_void_type().pointer_to()); + + func_1.add_parameter("A", &unit.create_generic_type("generic")); + { + let mut enum_ty = unit.create_enum("enum_ty"); + enum_ty.add_value("V", 0); + enum_ty.set_size(8); + func_1.add_parameter("B", &enum_ty); + } + { + let mut func_ty = unit.create_function_type("my_func_ty"); + func_ty.set_return_type(&unit.create_void_type().pointer_to()); + let typedef = unit.create_typedef("my_func_alia", &func_ty); + func_1.add_parameter("C", &typedef); + } + { + let mut struct_ty = unit.create_structure("struct_t"); + struct_ty.set_size(42); + struct_ty.add_member("field_0", &mut unit.create_void_type().pointer_to()); + struct_ty.add_member_at_offset( + "field_0", + &mut unit.create_void_type().pointer_to(), + 64, + ); + func_1.add_parameter("D", &struct_ty); + } + { + let element_ty = unit.create_base_type( + "int", + 4, + lief::dwarf::editor::types::base::Encoding::SIGNED, + ); + func_1.set_return_type(&unit.create_array_type("array_t", &element_ty, 8)); + } + let mut var = func_1.create_stack_variable("my_local_var"); + var.set_stack_offset(8); + var.set_type(&unit.create_void_type()); + let mut gvar = unit.create_variable("g_var").unwrap(); + gvar.set_addr(0x40000); + } + } + { + let mut unit = editor.create_compile_unit().unwrap(); + unit.set_producer("LIEF Rust test (CU#2)"); + } + + let mut tempfile = env::temp_dir(); + tempfile.push("out.debug"); + editor.write(tempfile.to_str().unwrap()); + } +} + +fn test_with(name: &str, suffix: &str) { + let path = utils::get_sample(Path::new(suffix)).unwrap(); + let path_str = path.to_str().unwrap(); + test_with_str(name, path_str); +} + +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + + println!("{}", lief::extended_version_info()); + test_with("user32.dll", "PE/user32.dll"); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/dwarf_tests.rs b/vendor/lief/api/rust/crates/lief/tests/dwarf_tests.rs new file mode 100644 index 0000000..0b4024f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/dwarf_tests.rs @@ -0,0 +1,550 @@ +#![allow(warnings)] +mod utils; +use lief; +use lief::assembly::Instruction; +use lief::dwarf::types::{Base, ClassLike, DwarfType}; +use lief::dwarf::{Parameter, Scope, Type}; +use lief::generic::Binary; + +use std::path::{Path, PathBuf}; + +fn explore_variable(name: &str, var: &lief::dwarf::Variable) { + println!( + "{} {}", + var.name(), + var.linkage_name().unwrap_or("".to_string()) + ); + println!("{} {}", var.address().unwrap_or(0), var.size().unwrap_or(0)); + println!("{}", var.is_constexpr()); + println!("{:?}", var.debug_location()); + if let Some(ty) = var.get_type() { + explore_type(name, &ty); + } + + if let Some(scope) = var.scope() { + explore_scope(&scope); + } +} + +fn explore_trait_classlike(classlike: &dyn ClassLike) { + for func in classlike.functions() { + println!("{}", func.name()); + } + for member in classlike.members() { + println!( + "{} {} {} {} {}", + member.name(), + member.offset().unwrap_or(0), + member.bit_offset().unwrap_or(0), + member.is_external(), + member.is_declaration() + ); + if let Some(ty) = member.get_type() { + match ty { + lief::dwarf::Type::Base(_) => { + println!("Base"); + } + lief::dwarf::Type::Pointer(_) => { + println!("Pointer"); + } + lief::dwarf::Type::Const(_) => { + println!("Const"); + } + lief::dwarf::Type::Array(_) => { + println!("Array"); + } + lief::dwarf::Type::Structure(_) => { + println!("Structure"); + } + lief::dwarf::Type::Class(_) => { + println!("Class"); + } + lief::dwarf::Type::Union(_) => { + println!("Union"); + } + lief::dwarf::Type::Packed(_) => { + println!("Packed"); + } + lief::dwarf::Type::Typedef(_) => { + println!("Typedef"); + } + lief::dwarf::Type::Atomic(_) => { + println!("Atomic"); + } + lief::dwarf::Type::Coarray(_) => { + println!("Coarray"); + } + lief::dwarf::Type::Dynamic(_) => { + println!("Dynamic"); + } + lief::dwarf::Type::Enum(_) => { + println!("Enum"); + } + lief::dwarf::Type::File(_) => { + println!("File"); + } + lief::dwarf::Type::Immutable(_) => { + println!("Immutable"); + } + lief::dwarf::Type::Interface(_) => { + println!("Interface"); + } + lief::dwarf::Type::PointerToMember(_) => { + println!("PointerToMember"); + } + lief::dwarf::Type::RValueReference(_) => { + println!("RValueReference"); + } + lief::dwarf::Type::Reference(_) => { + println!("Reference"); + } + lief::dwarf::Type::Restrict(_) => { + println!("Restrict"); + } + lief::dwarf::Type::SetTy(_) => { + println!("SetTy"); + } + lief::dwarf::Type::Shared(_) => { + println!("Shared"); + } + lief::dwarf::Type::StringTy(_) => { + println!("StringTy"); + } + lief::dwarf::Type::Subroutine(_) => { + println!("Subroutine"); + } + lief::dwarf::Type::TemplateAlias(_) => { + println!("TemplateAlias"); + } + lief::dwarf::Type::Thrown(_) => { + println!("Thrown"); + } + lief::dwarf::Type::Volatile(_) => { + println!("Volatile"); + } + lief::dwarf::Type::Generic(_) => { + println!("Generic"); + } + } + } + } +} + +fn explore_trait_type(type_: &dyn DwarfType) { + println!( + "{} {} {:?} {}", + type_.name().unwrap_or("".to_string()), + type_.size().unwrap_or(0), + type_.location(), + type_.is_unspecified(), + ); + if let Some(scope) = type_.scope() { + explore_scope(&scope); + } +} + +fn explore_scope(scope: &Scope) { + println!( + "{} {:?} {}", + scope.name(), + scope.get_type(), + scope.chained("::") + ); + if let Some(parent) = scope.parent() { + explore_scope(&parent); + } +} + +fn explore_type(name: &str, type_: &lief::dwarf::Type) { + match type_ { + lief::dwarf::Type::Base(t) => { + explore_trait_type(t); + println!("{:?}", t.encoding()); + } + + lief::dwarf::Type::Pointer(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + + lief::dwarf::Type::Const(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + + lief::dwarf::Type::Array(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + let size_info = t.size_info(); + println!("{}{}", size_info.name(), size_info.size()); + + if let Some(ty) = size_info.get_type() { + println!("{}", ty.name().unwrap_or("".to_string())); + } + } + + lief::dwarf::Type::Structure(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + + lief::dwarf::Type::Class(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + lief::dwarf::Type::Union(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + + lief::dwarf::Type::Packed(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + + lief::dwarf::Type::Typedef(t) => { + explore_trait_type(t); + println!("{}", t.name().unwrap_or("".to_string())); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Atomic(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Coarray(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::Dynamic(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::Enum(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::File(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::Immutable(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Interface(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::PointerToMember(t) => { + explore_trait_type(t); + + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + + if let Some(containing_type) = t.containing_type() { + explore_type(name, &containing_type); + } + } + lief::dwarf::Type::RValueReference(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Reference(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Restrict(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::SetTy(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Shared(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::StringTy(t) => { + explore_trait_type(t); + } + lief::dwarf::Type::Subroutine(t) => { + explore_trait_type(t); + for p in t.parameters() { + explore_parameters(name, &p); + } + } + lief::dwarf::Type::TemplateAlias(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + for p in t.parameters() { + explore_parameters(name, &p); + } + } + lief::dwarf::Type::Thrown(t) => { + explore_trait_type(t); + + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Volatile(t) => { + explore_trait_type(t); + + if let Some(underlying) = t.underlying_type() { + explore_type(name, &underlying); + } + } + lief::dwarf::Type::Generic(t) => { + explore_trait_type(t); + } + } +} + +fn explore_parameters(name: &str, param: &lief::dwarf::Parameters) { + println!("{}", param.name()); + if let Some(ty) = param.get_type() { + explore_type(name, &ty); + } +} + +fn explore_function(name: &str, func: &lief::dwarf::Function) { + if let Some(scope) = func.scope() { + explore_scope(&scope); + } + println!( + "{} {} {}", + func.name(), + func.linkage_name(), + func.address().unwrap_or(0) + ); + println!( + "{} {} {} {}", + func.is_artificial(), + func.is_external(), + func.size(), + func.ranges().len() + ); + println!("{:?}", func.debug_location()); + + for param in func.parameters() { + explore_parameters(name, ¶m); + } + + if let Some(ty) = func.return_type() { + explore_type(name, &ty); + } + + for var in func.variables() { + explore_variable(name, &var); + } + + for ty in func.thrown_types() { + explore_type(name, &ty); + } + + //println!("{} {}", name, func.name()); + for inst in func.instructions() { + format!("{}", inst.to_string()); + } +} + +fn explore_dwarf(name: &str, dwarf: &lief::dwarf::DebugInfo) { + let func = dwarf.function_by_name("__empty__function__"); + assert!(func.is_none()); + for cu in dwarf.compilation_units() { + println!("{} {} {}", cu.name(), cu.producer(), cu.compilation_dir()); + println!("{} {} {}", cu.low_address(), cu.high_address(), cu.size()); + println!("{:?}", cu.language()); + + println!("{:?}", cu.ranges()); + + for func in cu.functions() { + explore_function(name, &func); + } + + for func in cu.imported_functions() { + explore_function(name, &func); + } + + for var in cu.variables() { + explore_variable(name, &var); + } + + for ty in cu.types() { + explore_type(name, &ty); + } + + if name == "simple-gcc-c.bin" { + assert!(cu.function_by_name("main").is_some()); + assert!(cu.function_by_name("_main_").is_none()); + + assert!(cu.function_by_addr(0x401126).is_some()); + assert!(cu.function_by_addr(0x123456).is_none()); + } + + if name == "vars_1.elf" { + assert!(cu.variable_by_name("g_map").is_some()); + assert!(cu.variable_by_name("__g_map__").is_none()); + + assert!(cu.variable_by_addr(0x40e0).is_some()); + assert!(cu.variable_by_addr(0).is_none()); + } + } + if name == "libLIEF.so" { + assert!( + dwarf + .variable_by_name("_ZN3fmt3v1012format_facetISt6localeE2idE") + .is_some() + ); + assert!(dwarf.variable_by_name("foo").is_none()); + + assert!(dwarf.variable_by_addr(0x44f5f8).is_some()); + assert!(dwarf.variable_by_addr(0xdeadc0de).is_none()); + + assert!(dwarf.function_by_name("mbedtls_ct_memcmp").is_some()); + assert!(dwarf.variable_by_name("_mbedtls_ct_memcmp_").is_none()); + + assert!(dwarf.function_by_addr(0x2e6b40).is_some()); + assert!(dwarf.function_by_addr(0xdeadc0de).is_none()); + + assert!(dwarf.function_by_addr(0x2e6b40).is_some()); + assert!(dwarf.function_by_addr(0xdeadc0de).is_none()); + + assert!( + dwarf + .type_by_name( + "unique_ptr >" + ) + .is_some() + ); + assert!(dwarf.type_by_name("foo").is_none()); + } +} + +fn test_with_str(name: &str, path_str: &str) { + if let Some(lief::Binary::ELF(bin)) = lief::Binary::parse(path_str) { + let debug_info = bin.debug_info(); + assert!(debug_info.is_some()); + if let Some(lief::debug_info::DebugInfo::Dwarf(dwarf)) = debug_info { + explore_dwarf(name, &dwarf); + } else { + panic!("Expecting a Dwarf"); + } + } +} + +fn test_with_elf(name: &str) { + let path = utils::get_elf_sample(name).unwrap(); + let path_str = path.to_str().unwrap(); + test_with_str(name, path_str); +} + +fn test_with_fullpath(name: &str, suffix: &str) { + let path = utils::get_sample(Path::new(suffix)).unwrap(); + let path_str = path.to_str().unwrap(); + test_with_str(name, path_str); +} + +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + + println!("{}", lief::extended_version_info()); + + let elf = lief::elf::Binary::parse("/bin/ls").unwrap(); + if let Some(lief::DebugInfo::Dwarf(dwarf)) = elf.debug_info() {} + + test_with_elf("simple-gcc-c.bin"); + test_with_fullpath("vars_1.elf", "DWARF/vars_1.elf"); + test_with_fullpath("libLIEF.so", "private/DWARF/libLIEF.so"); + test_with_fullpath("lsd", "private/DWARF/lsd"); + test_with_fullpath("libLIEF.dylib", "private/DWARF/libLIEF.dylib"); + test_with_fullpath( + "liblinker.debug", + "private/DWARF/binaryninja/liblinker.debug", + ); + test_with_fullpath("dxp.debug", "private/DWARF/binaryninja/dxp.debug"); + test_with_fullpath("cobol_hello.o", "private/DWARF/cobol_hello.o"); + test_with_fullpath("D_test.bin", "private/DWARF/D_test.bin"); + test_with_fullpath("java_Pig.o", "private/DWARF/java_Pig.o"); + test_with_fullpath( + "DW_TAG_string_type.o", + "private/DWARF/types/DW_TAG_string_type.o", + ); + test_with_fullpath( + "DW_TAG_ptr_to_member_type.o", + "private/DWARF/types/DW_TAG_ptr_to_member_type.o", + ); + test_with_fullpath("DW_TAG_set_type.o", "private/DWARF/types/DW_TAG_set_type.o"); + test_with_fullpath( + "DW_TAG_restrict_type.o", + "private/DWARF/types/DW_TAG_restrict_type.o", + ); + test_with_fullpath( + "DW_TAG_rvalue_reference_type.o", + "private/DWARF/types/DW_TAG_rvalue_reference_type.o", + ); + test_with_fullpath( + "DW_TAG_reference_type.o", + "private/DWARF/types/DW_TAG_reference_type.o", + ); + test_with_fullpath( + "DW_TAG_packed_type.ps.o", + "private/DWARF/types/DW_TAG_packed_type.ps.o", + ); + test_with_fullpath( + "DW_TAG_subrange_type.o", + "private/DWARF/types/DW_TAG_subrange_type.o", + ); + test_with_fullpath( + "DW_TAG_immutable_type.o", + "private/DWARF/types/DW_TAG_immutable_type.o", + ); + test_with_fullpath( + "DW_TAG_thrown_type.o", + "private/DWARF/types/DW_TAG_thrown_type.o", + ); + test_with_fullpath( + "DW_TAG_subroutine_type.o", + "private/DWARF/types/DW_TAG_subroutine_type.o", + ); + test_with_fullpath( + "DW_TAG_enumeration_type.o", + "private/DWARF/types/DW_TAG_enumeration_type.o", + ); + test_with_fullpath( + "DW_TAG_atomic_type.o", + "private/DWARF/types/DW_TAG_atomic_type.o", + ); + test_with_fullpath( + "DW_TAG_template_alias.o", + "private/DWARF/types/DW_TAG_template_alias.o", + ); + test_with_fullpath( + "DW_TAG_volatile_type.o", + "private/DWARF/types/DW_TAG_volatile_type.o", + ); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/dyld_shared_cache_test.rs b/vendor/lief/api/rust/crates/lief/tests/dyld_shared_cache_test.rs new file mode 100644 index 0000000..c17c77d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/dyld_shared_cache_test.rs @@ -0,0 +1,95 @@ +#![allow(warnings)] +mod utils; +use std::env; +use std::path::PathBuf; +use std::str::FromStr; + +fn has_dyld_shared_cache_samples() -> bool { + let dsc_dir = utils::get_sample_path().join("dyld_shared_cache"); + if dsc_dir.is_dir() { + return true; + } + if let Some(dir) = env::var_os("LIEF_DSC_SAMPLES_DIR") { + return PathBuf::from_str(&dir.into_string().unwrap_or("".to_string())) + .unwrap() + .is_dir(); + } + return false; +} + +fn get_dsc_sample(suffix: &str) -> PathBuf { + let dir = utils::get_sample_path().join("dyld_shared_cache"); + if dir.is_dir() { + return dir.join(suffix); + } + let env_dir = env::var_os("LIEF_DSC_SAMPLES_DIR") + .unwrap() + .into_string() + .unwrap(); + PathBuf::from_str(&env_dir).unwrap().join(suffix) +} + +fn explore_dylib(cache: &lief::dsc::DyldSharedCache, dylib: &lief::dsc::Dylib) { + println!("{:?}", dylib); +} + +fn explore_mapping_info(cache: &lief::dsc::DyldSharedCache, info: &lief::dsc::MappingInfo) { + println!("{:?}", info); +} + +fn explore_subcache(cache: &lief::dsc::DyldSharedCache, sc: &lief::dsc::SubCache) { + println!("{:?}", sc); +} + +fn run_ios_181(cache: &lief::dsc::DyldSharedCache) { + println!("{}", cache.filename()); + println!("{}", cache.filepath()); + println!("{}", cache.load_address()); + println!("{:?}", cache.version()); + println!("{}", cache.arch_name()); + println!("{:?}", cache.platform()); + println!("{:?}", cache.arch()); + + assert!(cache.find_lib_from_va(0x20d0a4010).is_some()); + assert!(cache.find_lib_from_va(0).is_none()); + + assert!( + cache + .find_lib_from_path("/usr/lib/libobjc.A.dylib") + .is_some() + ); + assert!( + cache + .find_lib_from_path("/usr/lib/libobjc.X.dylib") + .is_none() + ); + + assert!(cache.find_lib_from_name("liblockdown.dylib").is_some()); + assert!(cache.find_lib_from_path("liblockdown.A.dylib").is_none()); + + assert!(cache.has_subcaches()); + + for dylib in cache.libraries() { + explore_dylib(cache, &dylib); + } + + for sc in cache.subcaches() { + explore_subcache(cache, &sc); + for info in sc.cache().expect("Missing cache").mapping_info() { + explore_mapping_info(cache, &info); + } + } +} + +#[test] +fn test_api() { + if !lief::is_extended() || !has_dyld_shared_cache_samples() { + return; + } + let cache = lief::dsc::load_from_path( + get_dsc_sample("ios-18.1/").to_str().unwrap(), + /*arch*/ "", + ); + assert!(cache.is_some()); + run_ios_181(&cache.unwrap()); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/elf_notes_tests.rs b/vendor/lief/api/rust/crates/lief/tests/elf_notes_tests.rs new file mode 100644 index 0000000..43cd272 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/elf_notes_tests.rs @@ -0,0 +1,631 @@ +#![allow(warnings)] +mod utils; + +use lief::Binary; +use lief::elf::Notes; +use lief::elf::note; +use lief::elf::note::NoteBase; + +fn parse_elf(name: &str) -> lief::elf::Binary { + let path = utils::get_elf_sample(name).unwrap(); + match Binary::parse(path.to_str().unwrap()) { + Some(Binary::ELF(elf)) => elf, + _ => panic!("Failed to parse ELF: {name}"), + } +} + +// ============================================================================ +// Core dump tests: ARM 32-bit +// ============================================================================ + +#[test] +fn test_core_arm() { + let core = parse_elf("ELF32_ARM_core_hello.core"); + let notes: Vec> = core.notes().collect(); + assert_eq!(notes.len(), 6); + + // All notes should have debug representations + for note in ¬es { + let dbg = format!("{note:?}"); + assert!(!dbg.is_empty()); + } + + // NT_PRPSINFO + let Notes::CorePrPsInfo(prpsinfo) = ¬es[0] else { + panic!("Expected CorePrPsInfo, got {:?}", notes[0]); + }; + assert_eq!(prpsinfo.get_type(), note::Type::CORE_PRPSINFO); + + // NOTE(romain): not yet correctly implemented + //let info = prpsinfo.info().expect("info should be present"); + //assert_eq!(info.filename.trim_end_matches('\0'), "hello-exe"); + //assert!(info.args.starts_with("./hello-exe ")); + //assert_eq!(info.uid, 2000); + //assert_eq!(info.gid, 2000); + //assert_eq!(info.pid, 8166); + //assert_eq!(info.ppid, 8163); + //assert_eq!(info.pgrp, 8166); + //assert_eq!(info.sid, 7997); + + // NT_PRSTATUS + let Notes::CorePrStatus(prstatus) = ¬es[1] else { + panic!("Expected CorePrStatus, got {:?}", notes[1]); + }; + assert_eq!(prstatus.get_type(), note::Type::CORE_PRSTATUS); + assert_eq!(prstatus.architecture(), lief::elf::header::Arch::ARM); + + let status = prstatus.status(); + assert_eq!(status.cursig, 7); + assert_eq!(status.sigpend, 0); + assert_eq!(status.sighold, 0); + assert_eq!(status.pid, 8166); + assert_eq!(status.ppid, 0); + assert_eq!(status.pgrp, 0); + assert_eq!(status.sid, 0); + + let regs = prstatus.register_values(); + assert_eq!(regs.len(), 17); + // R0 + assert_eq!(regs[0], 0xAAD75074); + // R1 + assert_eq!(regs[1], 0); + // R2 + assert_eq!(regs[2], 0xB); + // R3-R11 are 0 + for i in 3..=11 { + assert_eq!(regs[i], 0, "R{i} should be 0"); + } + // R12 + assert_eq!(regs[12], 0xA); + // R13 + assert_eq!(regs[13], 1); + // R14 + assert_eq!(regs[14], 0xF7728841); + // R15 + assert_eq!(regs[15], 0xAAD7507C); + // CPSR (index 16) + assert_eq!(regs[16], 0x60010010); + + // pc/sp helpers + assert_eq!(prstatus.pc(), Ok(0xAAD7507C)); + assert_eq!(prstatus.sp(), Ok(1)); + assert_eq!(prstatus.return_value(), Ok(0xAAD75074)); + + // NT_SIGINFO + let Notes::CoreSigInfo(siginfo) = ¬es[3] else { + panic!("Expected CoreSigInfo, got {:?}", notes[3]); + }; + assert_eq!(siginfo.get_type(), note::Type::CORE_SIGINFO); + assert_eq!(siginfo.signo(), Ok(7)); + assert_eq!(siginfo.sigcode(), Ok(0)); + assert_eq!(siginfo.sigerrno(), Ok(1)); + + // NT_AUXV + let Notes::CoreAuxv(auxv) = ¬es[4] else { + panic!("Expected CoreAuxv, got {:?}", notes[4]); + }; + assert_eq!(auxv.get_type(), note::Type::CORE_AUXV); + let values = auxv.values(); + assert_eq!(values.len(), 18); + assert_eq!(values[¬e::core::auxv::Type::PHDR], 0xAAD74034); + assert_eq!(values[¬e::core::auxv::Type::PHENT], 0x20); + assert_eq!(values[¬e::core::auxv::Type::PHNUM], 0x9); + assert_eq!(values[¬e::core::auxv::Type::PAGESZ], 4096); + assert_eq!(values[¬e::core::auxv::Type::BASE], 0xF7716000); + assert_eq!(values[¬e::core::auxv::Type::FLAGS], 0); + assert_eq!(values[¬e::core::auxv::Type::ENTRY], 0xAAD75074); + assert_eq!(values[¬e::core::auxv::Type::UID], 2000); + assert_eq!(values[¬e::core::auxv::Type::EUID], 2000); + assert_eq!(values[¬e::core::auxv::Type::GID], 2000); + assert_eq!(values[¬e::core::auxv::Type::EGID], 2000); + assert_eq!(values[¬e::core::auxv::Type::CLKTCK], 0x64); + assert_eq!(values[¬e::core::auxv::Type::SECURE], 0); + + // NT_FILE + let Notes::CoreFile(corefile) = ¬es[5] else { + panic!("Expected CoreFile, got {:?}", notes[5]); + }; + assert_eq!(corefile.get_type(), note::Type::CORE_FILE); + assert_eq!(corefile.count(), 21); + + let files: Vec<_> = corefile.files().collect(); + assert_eq!(files.len(), 21); + + assert_eq!(files[0].start(), 0xAAD74000); + assert_eq!(files[0].end(), 0xAAD78000); + assert_eq!(files[0].file_ofs(), 0); + assert_eq!(files[0].path(), "/data/local/tmp/hello-exe"); + + let last = &files[files.len() - 1]; + assert_eq!(last.start(), 0xF77A1000); + assert_eq!(last.end(), 0xF77A2000); + assert_eq!(last.file_ofs(), 0x8A000); + assert_eq!(last.path(), "/system/bin/linker"); + + // All file entries should have non-empty paths + for f in &files { + assert!(!f.path().is_empty()); + } +} + +// ============================================================================ +// Core dump tests: AArch64 64-bit +// ============================================================================ + +#[test] +fn test_core_aarch64() { + let core = parse_elf("ELF64_AArch64_core_hello.core"); + let notes: Vec> = core.notes().collect(); + assert_eq!(notes.len(), 6); + + // NT_PRPSINFO + let Notes::CorePrPsInfo(prpsinfo) = ¬es[0] else { + panic!("Expected CorePrPsInfo, got {:?}", notes[0]); + }; + assert_eq!(prpsinfo.get_type(), note::Type::CORE_PRPSINFO); + // NOTE(romain): not yet correctly implemented + //let info = prpsinfo.info().expect("info should be present"); + //assert_eq!(info.filename.trim_end_matches('\0'), "hello-exe"); + //assert!(info.args.starts_with("./hello-exe ")); + //assert_eq!(info.uid, 2000); + //assert_eq!(info.gid, 2000); + //assert_eq!(info.pid, 8104); + //assert_eq!(info.ppid, 8101); + //assert_eq!(info.pgrp, 8104); + //assert_eq!(info.sid, 7997); + + // NT_PRSTATUS + let Notes::CorePrStatus(prstatus) = ¬es[1] else { + panic!("Expected CorePrStatus, got {:?}", notes[1]); + }; + assert_eq!(prstatus.get_type(), note::Type::CORE_PRSTATUS); + assert_eq!(prstatus.architecture(), lief::elf::header::Arch::AARCH64); + + let status = prstatus.status(); + assert_eq!(status.cursig, 5); + assert_eq!(status.sigpend, 0); + assert_eq!(status.sighold, 0); + assert_eq!(status.pid, 8104); + assert_eq!(status.ppid, 0); + assert_eq!(status.pgrp, 0); + assert_eq!(status.sid, 0); + + let regs = prstatus.register_values(); + assert_eq!(regs.len(), 34); + // X0 + assert_eq!(regs[0], 0x5580B86F50); + // X1 + assert_eq!(regs[1], 0); + // X2 + assert_eq!(regs[2], 0x1); + // X3 + assert_eq!(regs[3], 0x7FB7E2E160); + // X4 + assert_eq!(regs[4], 0x7FB7E83030); + // X5 + assert_eq!(regs[5], 0x4); + // X6 + assert_eq!(regs[6], 0x6F6C2F617461642F); + // X7 + assert_eq!(regs[7], 0x2F706D742F6C6163); + // X30 + assert_eq!(regs[30], 0x7FB7EB6068); + // X31 + assert_eq!(regs[31], 0x7FFFFFF950); + // PC + assert_eq!(regs[32], 0x5580B86F50); + + assert_eq!(prstatus.pc(), Ok(0x5580B86F50)); + + // NT_SIGINFO + let Notes::CoreSigInfo(siginfo) = ¬es[3] else { + panic!("Expected CoreSigInfo, got {:?}", notes[3]); + }; + assert_eq!(siginfo.signo(), Ok(5)); + assert_eq!(siginfo.sigcode(), Ok(0)); + assert_eq!(siginfo.sigerrno(), Ok(1)); + + // NT_AUXV + let Notes::CoreAuxv(auxv) = ¬es[4] else { + panic!("Expected CoreAuxv, got {:?}", notes[4]); + }; + assert_eq!(auxv.get_type(), note::Type::CORE_AUXV); + let values = auxv.values(); + assert_eq!(values.len(), 18); + assert_eq!(values[¬e::core::auxv::Type::PHDR], 0x5580B86040); + assert_eq!(values[¬e::core::auxv::Type::PHENT], 0x38); + assert_eq!(values[¬e::core::auxv::Type::PHNUM], 0x9); + assert_eq!(values[¬e::core::auxv::Type::PAGESZ], 4096); + assert_eq!(values[¬e::core::auxv::Type::BASE], 0x7FB7E93000); + assert_eq!(values[¬e::core::auxv::Type::FLAGS], 0); + assert_eq!(values[¬e::core::auxv::Type::ENTRY], 0x5580B86F50); + assert_eq!(values[¬e::core::auxv::Type::UID], 2000); + assert_eq!(values[¬e::core::auxv::Type::EUID], 2000); + assert_eq!(values[¬e::core::auxv::Type::GID], 2000); + assert_eq!(values[¬e::core::auxv::Type::EGID], 2000); + assert_eq!(values[¬e::core::auxv::Type::HWCAP], 0xFF); + assert_eq!(values[¬e::core::auxv::Type::CLKTCK], 0x64); + assert_eq!(values[¬e::core::auxv::Type::SECURE], 0); + assert_eq!(values[¬e::core::auxv::Type::SYSINFO_EHDR], 0x7FB7E91000); + + // NT_FILE + let Notes::CoreFile(corefile) = ¬es[5] else { + panic!("Expected CoreFile, got {:?}", notes[5]); + }; + assert_eq!(corefile.count(), 22); + + let files: Vec<_> = corefile.files().collect(); + assert_eq!(files.len(), 22); + + assert_eq!(files[0].start(), 0x5580B86000); + assert_eq!(files[0].end(), 0x5580B88000); + assert_eq!(files[0].file_ofs(), 0); + assert_eq!(files[0].path(), "/data/local/tmp/hello-exe"); + + let last = &files[files.len() - 1]; + assert_eq!(last.start(), 0x7FB7F8C000); + assert_eq!(last.end(), 0x7FB7F8D000); + assert_eq!(last.file_ofs(), 0xF8000); + assert_eq!(last.path(), "/system/bin/linker64"); +} + +// ============================================================================ +// Android identification note +// ============================================================================ + +#[test] +fn test_android_note() { + let elf = parse_elf("ELF64_AArch64_piebinary_ndkr16.bin"); + + let mut found_android = false; + for note_entry in elf.notes() { + if let Notes::AndroidIdent(android) = note_entry { + found_android = true; + assert_eq!(android.get_type(), note::Type::ANDROID_IDENT); + assert_eq!(android.sdk_version(), 21); + assert!(android.ndk_version().starts_with("r16b")); + assert!(android.ndk_build_number().starts_with("4479499")); + } + } + assert!(found_android, "Should find an AndroidIdent note"); +} + +// ============================================================================ +// GNU notes (generic iteration with NoteBase) +// ============================================================================ + +#[test] +fn test_generic_notes() { + let elf = parse_elf("ELF64_x86-64_binary_etterlog.bin"); + + let mut found_build_id = false; + let mut found_abi_tag = false; + for note_entry in elf.notes() { + let dbg = format!("{note_entry:?}"); + assert!(!dbg.is_empty()); + + match ¬e_entry { + Notes::NoteAbi(abi) => { + found_abi_tag = true; + assert_eq!(abi.get_type(), note::Type::GNU_ABI_TAG); + assert_eq!(abi.name(), "GNU"); + let _abi_enum = abi.abi(); + let _version = abi.version(); + format!("{abi:?}"); + } + Notes::Generic(g) => { + if g.get_type() == note::Type::GNU_BUILD_ID { + found_build_id = true; + assert!(!g.description().is_empty()); + assert_eq!(g.name(), "GNU"); + } + } + _ => {} + } + } + assert!(found_build_id, "Should find GNU_BUILD_ID"); + assert!(found_abi_tag, "Should find GNU_ABI_TAG"); +} + +// ============================================================================ +// GNU Property notes with properties (from simple-gcc-c.bin) +// ============================================================================ + +#[test] +fn test_gnu_property_notes() { + let elf = parse_elf("simple-gcc-c.bin"); + + let mut found_gnu_property = false; + for note_entry in elf.notes() { + if let Notes::NoteGnuProperty(gnu_prop) = note_entry { + found_gnu_property = true; + assert_eq!(gnu_prop.get_type(), note::Type::GNU_PROPERTY_TYPE_0); + assert_eq!(gnu_prop.name(), "GNU"); + + let props: Vec<_> = gnu_prop.properties().collect(); + assert!(!props.is_empty(), "Should have at least one property"); + + for prop in &props { + use note::properties::NoteProperty; + let _ptype = prop.property_type(); + let dbg = format!("{prop:?}"); + assert!(!dbg.is_empty()); + } + } + } + assert!(found_gnu_property, "Should find NoteGnuProperty"); +} + +// ============================================================================ +// Issue 816: binary with many notes +// ============================================================================ + +#[test] +fn test_notes_issue_816() { + let elf = parse_elf("elf_notes_issue_816.bin"); + let notes: Vec> = elf.notes().collect(); + assert_eq!(notes.len(), 272); + + for note_entry in ¬es { + let dbg = format!("{note_entry:?}"); + assert!(!dbg.is_empty()); + } +} + +// ============================================================================ +// NoteBase trait coverage: size, description, original_type +// ============================================================================ + +#[test] +fn test_note_base_trait() { + let core = parse_elf("ELF32_ARM_core_hello.core"); + for note_entry in core.notes() { + // Every note must have a non-empty name + let name = match ¬e_entry { + Notes::CorePrPsInfo(n) => n.name(), + Notes::CorePrStatus(n) => n.name(), + Notes::CoreSigInfo(n) => n.name(), + Notes::CoreAuxv(n) => n.name(), + Notes::CoreFile(n) => n.name(), + Notes::Generic(n) => n.name(), + Notes::AndroidIdent(n) => n.name(), + Notes::NoteAbi(n) => n.name(), + Notes::NoteGnuProperty(n) => n.name(), + Notes::QNXStack(n) => n.name(), + }; + assert!(!name.is_empty(), "Note name should not be empty"); + + // description should return bytes + let desc = match ¬e_entry { + Notes::CorePrPsInfo(n) => n.description().to_vec(), + Notes::CorePrStatus(n) => n.description().to_vec(), + Notes::CoreSigInfo(n) => n.description().to_vec(), + Notes::CoreAuxv(n) => n.description().to_vec(), + Notes::CoreFile(n) => n.description().to_vec(), + Notes::Generic(n) => n.description().to_vec(), + Notes::AndroidIdent(n) => n.description().to_vec(), + Notes::NoteAbi(n) => n.description().to_vec(), + Notes::NoteGnuProperty(n) => n.description().to_vec(), + Notes::QNXStack(n) => n.description().to_vec(), + }; + assert!(!desc.is_empty(), "Note description should not be empty"); + + // original_type should be non-zero for core notes + let otype = match ¬e_entry { + Notes::CorePrPsInfo(n) => n.original_type(), + Notes::CorePrStatus(n) => n.original_type(), + Notes::CoreSigInfo(n) => n.original_type(), + Notes::CoreAuxv(n) => n.original_type(), + Notes::CoreFile(n) => n.original_type(), + Notes::Generic(n) => n.original_type(), + Notes::AndroidIdent(n) => n.original_type(), + Notes::NoteAbi(n) => n.original_type(), + Notes::NoteGnuProperty(n) => n.original_type(), + Notes::QNXStack(n) => n.original_type(), + }; + assert!(otype != 0, "Core note original_type should be non-zero"); + } +} + +// ============================================================================ +// GNU Property: X86 properties from multiple binaries +// ============================================================================ + +#[test] +fn test_gnu_property_x86_features() { + use note::properties::{NoteProperty, Properties, PropertyType}; + + // docker-init.elf has GNU properties with X86 features + let elf = parse_elf("docker-init.elf"); + + let mut found_x86_feature = false; + for note_entry in elf.notes() { + if let Notes::NoteGnuProperty(gnu_prop) = note_entry { + for prop in gnu_prop.properties() { + match prop { + Properties::X86Features(x86f) => { + found_x86_feature = true; + assert_eq!(x86f.property_type(), PropertyType::X86_FEATURE); + let feats = x86f.features(); + assert!(!feats.is_empty()); + format!("{x86f:?}"); + } + Properties::X86ISA(x86isa) => { + assert_eq!(x86isa.property_type(), PropertyType::X86_ISA); + let vals = x86isa.values(); + assert!(!vals.is_empty()); + format!("{x86isa:?}"); + } + _ => { + format!("{prop:?}"); + } + } + } + } + } + assert!(found_x86_feature, "Should find X86Features property"); +} + +// ============================================================================ +// AArch64 property notes from aarch64 binaries +// ============================================================================ + +#[test] +fn test_gnu_property_aarch64() { + use note::properties::{NoteProperty, Properties, PropertyType}; + + let elf = parse_elf("issue_975_aarch64.o"); + + for note_entry in elf.notes() { + if let Notes::NoteGnuProperty(gnu_prop) = note_entry { + for prop in gnu_prop.properties() { + match prop { + Properties::AArch64Feature(aarch64f) => { + assert_eq!(aarch64f.property_type(), PropertyType::AARCH64_FEATURES); + let features = aarch64f.features(); + assert!(!features.is_empty()); + format!("{aarch64f:?}"); + } + _ => { + format!("{prop:?}"); + } + } + } + } + } +} + +// ============================================================================ +// Iterate all note types from the Core issue 808 sample +// ============================================================================ + +#[test] +fn test_core_issue_808() { + let core = parse_elf("ELF_Core_issue_808.core"); + let notes: Vec> = core.notes().collect(); + assert!(!notes.is_empty()); + + for note_entry in ¬es { + let dbg = format!("{note_entry:?}"); + assert!(!dbg.is_empty()); + } +} + +// ============================================================================ +// Debug formatting for all property types +// ============================================================================ + +#[test] +fn test_property_debug_formatting() { + use note::properties::Properties; + + let elf = parse_elf("simple-gcc-c.bin"); + + for note_entry in elf.notes() { + if let Notes::NoteGnuProperty(gnu_prop) = note_entry { + for prop in gnu_prop.properties() { + // Exercise Debug on every property variant + match &prop { + Properties::AArch64Feature(p) => { + format!("{p:?}"); + } + Properties::AArch64PAuth(p) => { + format!("{p:?}"); + } + Properties::X86Features(p) => { + format!("{p:?}"); + } + Properties::X86ISA(p) => { + format!("{p:?}"); + } + Properties::StackSize(p) => { + format!("{p:?}"); + } + Properties::NoCopyOnProtected(p) => { + format!("{p:?}"); + } + Properties::Needed(p) => { + format!("{p:?}"); + } + Properties::Generic(p) => { + format!("{p:?}"); + } + } + } + } + } +} + +// ============================================================================ +// GNU Property: find() method +// ============================================================================ + +#[test] +fn test_gnu_property_find() { + use note::properties::{NoteProperty, PropertyType}; + + let elf = parse_elf("simple-gcc-c.bin"); + + for note_entry in elf.notes() { + if let Notes::NoteGnuProperty(gnu_prop) = note_entry { + let props: Vec<_> = gnu_prop.properties().collect(); + if props.is_empty() { + continue; + } + + // The find method should return a property when searching for + // a type we know exists + let first_type = props[0].property_type(); + let found = gnu_prop.find(first_type); + assert!( + found.is_some(), + "find() should return a property for known type" + ); + + // Searching for an unlikely type should return None + let not_found = gnu_prop.find(255.into()); + assert!( + not_found.is_none(), + "find() should return None for unknown type" + ); + } + } +} + +// ============================================================================ +// Comprehensive note iteration over various ELF binaries +// ============================================================================ + +#[test] +fn test_notes_comprehensive_iteration() { + let samples = [ + "ELF64_x86-64_binary_etterlog.bin", + "simple-gcc-c.bin", + "ELF64_AArch64_piebinary_ndkr16.bin", + "issue_975_aarch64.o", + "elf_notes_issue_816.bin", + "ELF32_ARM_core_hello.core", + "ELF64_AArch64_core_hello.core", + "ELF_Core_issue_808.core", + ]; + + for name in &samples { + let path = utils::get_elf_sample(name); + if path.is_none() { + continue; + } + let path = path.unwrap(); + let Some(Binary::ELF(elf)) = Binary::parse(path.to_str().unwrap()) else { + continue; + }; + + let mut count = 0; + for note_entry in elf.notes() { + count += 1; + // Exercise debug formatting on every note + let dbg = format!("{note_entry:?}"); + assert!(!dbg.is_empty()); + } + assert!(count > 0, "{name} should have at least one note"); + } +} diff --git a/vendor/lief/api/rust/crates/lief/tests/elf_tests.rs b/vendor/lief/api/rust/crates/lief/tests/elf_tests.rs new file mode 100644 index 0000000..20e1fe7 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/elf_tests.rs @@ -0,0 +1,311 @@ +#![allow(warnings)] +mod utils; +use lief::Binary; +use lief::elf::Notes; +use lief::elf::builder::Config; +use lief::elf::dynamic; +use lief::elf::dynamic::DynamicEntry; +use lief::elf::note::NoteBase; +use lief::elf::relocation; +use lief::elf::segment; +use lief::generic::Binary as GenericBinary; +use lief::generic::Section; +use lief::generic::Symbol; +use lief::logging; +use std::env; + +fn explore_elf(name: &str, elf: &lief::elf::Binary) { + format!("{elf:?}"); + format!("{} {} {}", elf.entrypoint(), elf.imagebase(), elf.is_pie()); + format!( + "{} {} {}", + elf.has_nx(), + elf.original_size(), + elf.virtual_size() + ); + format!("{}", elf.interpreter()); + + for func in elf.functions() { + format!("{func:?}"); + } + + if let Some(sysv) = elf.sysv_hash() { + format!("{sysv:?}"); + } + + if let Some(text) = elf.section_by_name(".text") { + format!("{text:?}"); + } + + if let Some(gnu) = elf.gnu_hash() { + format!("{gnu:?}"); + } + + for section in elf.sections() { + format!("Section: {section:?}: {section}"); + format!("Name: {}", section.name()); + format!("{}", section.content().len()); + format!("{size}", size = section.size()); + format!( + "{virtual_address}", + virtual_address = section.virtual_address() + ); + format!("{offset}", offset = section.offset()); + if section.name() == ".text" && section.size() > 0 { + assert!(!section.content().is_empty()) + } + } + + for segment in elf.segments() { + format!("{segment:?}: {segment}"); + if segment.p_type() == segment::Type::PHDR { + assert!(!segment.content().is_empty()) + } + } + + for sym in elf.exported_symbols() { + format!("{sym:?}"); + } + + for sym in elf.imported_symbols() { + format!("{sym:?}"); + } + + for sym in elf.symtab_symbols() { + format!("{sym:?}"); + } + + for version in elf.symbols_version() { + format!("{version:?}"); + } + + for note in elf.notes() { + format!("{note:?}"); + #[allow(irrefutable_let_patterns)] + if let Notes::Generic(generic) = note { + assert!(!generic.description().is_empty()); + assert!(!generic.original_type() != 0); + } + } + + for reloc in elf.pltgot_relocations() { + format!("{reloc:?}"); + } + + for reloc in elf.dynamic_relocations() { + if reloc.encoding() == relocation::Encoding::REL { + assert!(reloc.is_rel()); + } + + if reloc.encoding() == relocation::Encoding::RELA { + assert!(reloc.is_rela()); + } + format!("{reloc:?}"); + } + + for reloc in elf.object_relocations() { + format!("{reloc:?}"); + } + + for reloc in elf.relocations() { + format!("{reloc:?}"); + } + + for sym in elf.dynamic_symbols() { + format!("{sym:?}: {sym}"); + format!("{}: {} ({})", sym.name(), sym.value(), sym.size()); + format!("{}", sym.demangled_name()); + } + + for sym_ver in elf.symbols_version() { + format!("{sym_ver:?}"); + } + + for sym_def in elf.symbols_version_definition() { + format!("{sym_def:?}"); + for aux in sym_def.auxiliary_symbols() { + println!("{aux:?}"); + } + } + + for sym_req in elf.symbols_version_requirement() { + format!("{sym_req:?}"); + for aux in sym_req.auxiliary_symbols() { + println!("{aux:?}"); + } + } + + for entry in elf.dynamic_entries() { + format!("{entry:?}"); + + match entry { + dynamic::Entries::Generic(generic) => { + format!("{:?}: {}", generic.tag(), generic.value()); + } + dynamic::Entries::Library(lib) => { + format!("{:?}: {} {}", lib.tag(), lib.value(), lib.name()); + } + dynamic::Entries::Array(array) => { + format!("{:?}: {} {:?}", array.tag(), array.value(), array.array()); + } + dynamic::Entries::Rpath(rpath) => { + format!("{:?}: {}", rpath.tag(), rpath.rpath()); + } + dynamic::Entries::RunPath(runpath) => { + format!("{:?}: {}", runpath.tag(), runpath.runpath()); + } + dynamic::Entries::SharedObject(shared) => { + format!("{:?}: {}", shared.tag(), shared.name()); + } + dynamic::Entries::Auxiliary(aux) => { + format!("{:?}: {}", aux.tag(), aux.name()); + } + dynamic::Entries::Filter(filter) => { + format!("{:?}: {}", filter.tag(), filter.name()); + } + dynamic::Entries::Flags(flags) => { + format!("{:?}: {:?}", flags.tag(), flags.flags()); + } + } + } + + elf.get_relocated_dynamic_array(dynamic::Tag::INIT_ARRAY); + elf.get_relocated_dynamic_array(dynamic::Tag::FINI_ARRAY); + elf.get_relocated_dynamic_array(dynamic::Tag::PREINIT_ARRAY); + + if name == "ELF64_x86-64_library_libfreebl3.so" { + assert!(elf.relocation_by_addr(0x1234).is_none()); + assert!(elf.relocation_by_addr(0x003369c01df0).is_some()); + + assert!(elf.relocation_for_symbol("tooto").is_none()); + assert!(elf.relocation_for_symbol("_Jv_RegisterClasses").is_some()); + + assert!(elf.dynamic_symbol_by_name("_Jv_RegisterClasses").is_some()); + } + if name == "simple-gcc-c.bin" { + assert!(elf.symtab_symbol_by_name("test.c").is_some()); + assert!(elf.get_library("libc.so.6").is_some()); + assert!(elf.get_library("libtoto.so").is_none()); + assert!(elf.virtual_address_to_offset(0x100000000).is_err()); + assert!(elf.virtual_address_to_offset(0x401000).is_ok()); + + assert!(elf.segment_from_virtual_address(0x401000).is_some()); + assert!(elf.segment_from_virtual_address(0x100000000).is_none()); + + assert!(elf.segment_from_offset(0).is_some()); + assert!(elf.segment_from_offset(0x100000000).is_none()); + + assert!( + elf.section_from_offset(0x318, /*skip_nobits*/ true) + .is_some() + ); + assert!( + elf.section_from_offset(0x100000000, /*skip_nobits*/ true) + .is_none() + ); + + assert!( + elf.section_from_virtual_address(0x400318, /*skip_nobits*/ true) + .is_some() + ); + assert!( + elf.section_from_virtual_address(0x100000000, /*skip_nobits*/ true) + .is_none() + ); + assert!(!elf.content_from_virtual_address(0x400318, 0x10).is_empty()); + + assert!( + elf.get_int_from_virtual_address::(0x401126) + .expect("Read error") + != 0 + ); + assert!( + elf.get_int_from_virtual_address::(0x401126) + .expect("Read error") + != 0 + ); + assert!( + elf.get_int_from_virtual_address::(0x401126) + .expect("Read error") + != 0 + ); + assert!( + elf.get_int_from_virtual_address::(0x401126) + .expect("Read error") + != 0 + ); + } +} + +fn test_with(bin_name: &str) { + let path = utils::get_elf_sample(bin_name).unwrap(); + let path_str = path.to_str(); + if let Some(Binary::ELF(bin)) = Binary::parse(path_str.unwrap()) { + explore_elf(bin_name, &bin); + } + + // Test Read + Seek interface + let mut file = std::fs::File::open(path).expect("Can't open the file"); + let binary = Binary::from(&mut file); + assert!(matches!(binary, Some(Binary::ELF(_)))); +} + +#[test] +fn test_api() { + let mut dir = env::temp_dir(); + dir.push("lief_elf_test.log"); + logging::set_path(dir.as_path()); + + test_with("elf_reader.mips.elf"); + test_with("issue_975_aarch64.o"); + test_with("ELF_Core_issue_808.core"); + test_with("ELF64_x86-64_library_libfreebl3.so"); + test_with("ELF64_x86-64_binary_etterlog.bin"); + test_with("ELF64_x86-64_binary_systemd-resolve.bin"); + test_with("art_reader.loongarch"); + test_with("simple-gcc-c.bin"); + test_with("libdt_auxiliary_filter.so"); + test_with("libdt_auxiliary.so"); +} + +#[test] +fn test_mut_api() { + let path = utils::get_elf_sample("elf_reader.mips.elf").unwrap(); + let Binary::ELF(mut bin) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + bin.add_library("this_is_a_test.so"); + let tmpfile = tempfile::NamedTempFile::new().unwrap(); + bin.write(tmpfile.path()); + + let path = utils::get_elf_sample("ELF_Core_issue_808.core").unwrap(); + let Binary::ELF(mut bin) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + let tmpfile = tempfile::NamedTempFile::new().unwrap(); + bin.write_with_config(tmpfile.path(), Config::default()); +} + +#[test] +fn test_mips_n64() { + let path = utils::get_elf_sample("libtest_mips64el_n64.bin").unwrap(); + let Binary::ELF(bin) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + + assert!(bin.header().is_mips_n64()); + let reloc = bin + .dynamic_relocations() + .find(|reloc| reloc.get_type() == relocation::Type::MIPS_REL32) + .unwrap(); + assert_eq!( + reloc.resolve_with_base_address(0x1000_0000_0000).unwrap(), + 0x1000_0000_07b8 + ); + + let path = utils::get_elf_sample("elf_reader.mips.elf").unwrap(); + let Binary::ELF(bin) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + assert!(!bin.header().is_mips_n64()); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/logging_test.rs b/vendor/lief/api/rust/crates/lief/tests/logging_test.rs new file mode 100644 index 0000000..bec7f24 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/logging_test.rs @@ -0,0 +1,49 @@ +#![allow(warnings)] +use lief::logging; +use std::env; + +#[test] +fn test_api() { + logging::disable(); + logging::enable(); + logging::set_level(logging::Level::Debug); + + let mut dir = env::temp_dir(); + dir.push("lief_test.log"); + logging::set_path(dir.as_path()); + logging::log(logging::Level::Info, "hi!"); + logging::reset(); + lief::log_dbg!("dbg: {:?}", dir); + lief::log_info!("info: {:?}", dir); + lief::log_warn!("warn: {:?}", dir); + lief::log_err!("err: {dir:?}"); + + logging::set_level(logging::Level::Warn); + assert_eq!(logging::get_level(), logging::Level::Warn); + + logging::set_level(logging::Level::Debug); + assert_eq!(logging::get_level(), logging::Level::Debug); + + // Test Scoped + logging::set_level(logging::Level::Info); + assert_eq!(logging::get_level(), logging::Level::Info); + + { + let mut scoped = logging::Scoped::new(logging::Level::Debug); + assert_eq!(logging::get_level(), logging::Level::Debug); + + scoped.set_level(logging::Level::Trace); + assert_eq!(logging::get_level(), logging::Level::Trace); + + scoped.reset(); + assert_eq!(logging::get_level(), logging::Level::Info); + + // Set again so the drop restores INFO + scoped.set_level(logging::Level::Err); + } + + // After drop, original level (INFO) is restored + assert_eq!(logging::get_level(), logging::Level::Info); + + logging::reset(); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/macho_tests.rs b/vendor/lief/api/rust/crates/lief/tests/macho_tests.rs new file mode 100644 index 0000000..ae20b4f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/macho_tests.rs @@ -0,0 +1,554 @@ +#![allow(warnings)] +mod utils; +use lief::Binary; +use lief::generic::Binary as GenericBinary; +use lief::generic::Symbol; +use lief::logging; +use lief::macho::MachOSection; +use lief::macho::Relocation; +use lief::macho::binding_info::{self, AsGeneric}; +use lief::macho::builder::Config; +use lief::macho::commands::{Command, Commands}; +use lief::macho::header::CpuType; +use std::env; +use std::path::Path; + +fn print_binding(binding: &binding_info::BindingInfo) { + format!("{:?}", binding); + match binding { + binding_info::BindingInfo::Generic(generic) => { + format!("{:?}", generic.symbol()); + format!("{:?}", generic.library()); + format!("{:?}", generic.segment()); + } + + binding_info::BindingInfo::Dyld(dyld) => { + format!("{:?}", dyld.symbol()); + format!("{:?}", dyld.library()); + format!("{:?}", dyld.segment()); + } + + binding_info::BindingInfo::Chained(chained) => { + format!("{:?}", chained.symbol()); + format!("{:?}", chained.library()); + format!("{:?}", chained.segment()); + } + binding_info::BindingInfo::Indirect(indirect) => { + format!("{:?}", indirect.symbol()); + } + } +} + +fn explore_macho(_: &str, macho: &lief::macho::Binary) { + format!("{macho:?}"); + format!("{}", macho.entrypoint()); + format!("{:?}", macho.header()); + format!("{}{}", macho.header().is_32bit(), macho.header().is_64bit()); + println!( + "{:?}:{}:{}", + macho.platform(), + macho.is_ios(), + macho.is_macos() + ); + + for func in macho.functions() { + format!("{func:?}"); + } + + for note in macho.notes() { + format!("{note:?}"); + } + + for info in macho.lazy_load_dylib_infos() { + format!("{info:?}"); + format!("{}", info.load_path()); + for fixup in info.fixups() { + format!("{fixup:?} {fixup}"); + format!( + "{:#x} {} {} {}", + fixup.address(), + fixup.ordinal(), + fixup.symbol(), + fixup.is_auth() + ); + } + } + + for section in macho.sections() { + format!("{section:?}"); + format!("{:?}", section.segment()); + for relocation in section.relocations() { + format!("{relocation:?}"); + } + } + + for binding in macho.bindings() { + format!("{:?}", binding); + } + + for stub in macho.symbol_stubs() { + format!("{stub:?}"); + format!("{}", stub.raw().len()); + } + + for command in macho.commands() { + format!("{command:?}"); + match command { + Commands::Generic(generic) => { + println!("TYPE: {:?}", generic.command_type()); + } + Commands::DyldChainedFixups(cmd) => { + format!("{}", cmd.payload().len()); + for binding in cmd.bindings() { + format!("{:?}", binding); + } + } + Commands::DataInCode(cmd) => { + format!("{}", cmd.content().len()); + for entry in cmd.entries() { + format!("{:?}", entry); + } + } + Commands::SymbolCommand(cmd) => { + format!("{}", cmd.symbol_table().len()); + format!("{}", cmd.string_table().len()); + format!("{}", cmd.original_str_size()); + format!("{}", cmd.original_nb_symbols()); + } + Commands::FunctionStarts(cmd) => { + format!("{}", cmd.content().len()); + for entry in cmd.functions() { + format!("{:?}", entry); + } + } + Commands::DyldExportsTrie(cmd) => { + format!("{}", cmd.content().len()); + for export in cmd.exports() { + format!("{:?}", export); + format!("{:?}", export.symbol()); + format!("{:?}", export.alias()); + format!("{:?}", export.alias_library()); + } + } + Commands::ThreadCommand(cmd) => { + format!("{}", cmd.state().len()); + } + Commands::CodeSignature(cmd) => { + format!("{}", cmd.content().len()); + } + Commands::CodeSignatureDir(cmd) => { + format!("{}", cmd.content().len()); + } + Commands::LinkerOptHint(cmd) => { + format!("{}", cmd.content().len()); + } + Commands::TwoLevelHints(cmd) => { + format!("{}", cmd.original_nb_hints()); + format!("{}", cmd.content().len()); + } + Commands::SegmentSplitInfo(cmd) => { + format!("{}", cmd.content().len()); + } + Commands::DyldInfo(cmd) => { + format!("{}", cmd.rebase_opcodes().len()); + format!("{}", cmd.bind_opcodes().len()); + format!("{}", cmd.weak_bind_opcodes().len()); + format!("{}", cmd.lazy_bind_opcodes().len()); + format!("{}", cmd.export_trie().len()); + for binding in cmd.bindings() { + format!("{:?}", binding); + print_binding(&binding); + } + for export in cmd.exports() { + format!("{:?}", export); + } + } + + Commands::Note(note) => { + println!("Note {note:?}"); + } + + Commands::FunctionVariants(func) => { + println!("{func:?}"); + for runtime_table in func.runtime_table() { + println!("{runtime_table:?} {runtime_table}"); + for entry in runtime_table.entries() { + println!("{entry:?} {entry}") + } + } + } + + Commands::FunctionVariantFixups(func) => { + println!("{func:?}"); + for fixup in func.fixups() { + println!("{fixup:?} {fixup}"); + if let Some(segment) = fixup.segment() { + println!(" segment: {}", segment.name()); + } + } + } + + Commands::LazyLoadDylibInfo(info) => { + println!("{info:?}"); + println!("load_path={}", info.load_path()); + println!( + "flags={:#x} may_be_missing={}", + info.flags(), + info.may_be_missing() + ); + println!("pointer_format={:#x}", info.pointer_format()); + println!("flag_image_offset={:#x}", info.flag_image_offset()); + println!( + "chain_start_image_offset={:#x}", + info.chain_start_image_offset() + ); + println!( + "data_offset={:#x} data_size={:#x}", + info.data_offset(), + info.data_size() + ); + let _ = info.content(); + for sym in info.symbols() { + println!(" symbol: {sym}"); + } + } + + Commands::Fileset(fileset) => { + println!("{fileset:?}"); + } + + Commands::Unknown(ukn) => { + println!("Original: {:?}", ukn.original_command()); + } + _ => {} + } + } + + for bin in macho.filesets() { + format!("{} - {}", bin.fileset_name(), bin.fileset_addr()); + } + + for segment in macho.segments() { + format!("{segment:?}"); + for section in segment.sections() { + format!("{section:?}"); + } + + for relocation in segment.relocations() { + format!("{relocation:?}"); + } + + format!("len: {}", segment.content().len()); + } + + for lib in macho.libraries() { + format!("{lib:?}"); + } + + for reloc in macho.relocations() { + format!("{reloc:?}"); + + match reloc { + Relocation::Dyld(_) => {} + Relocation::Fixup(fixup) => { + format!("{}", fixup.next()); + } + Relocation::Object(_) => {} + Relocation::Generic(_) => {} + } + } + + for sym in macho.symbols() { + format!("{sym:?}"); + format!("{}", sym.demangled_name()); + } + + if let Some(info) = macho.dyld_info() { + format!("{info:?}"); + } + + if let Some(uuid) = macho.uuid() { + format!("{uuid:?}"); + } + + if let Some(main) = macho.main_command() { + format!("{main:?}"); + } + + if let Some(linker) = macho.dylinker() { + format!("{linker:?}"); + } + + if let Some(starts) = macho.function_starts() { + format!("{starts:?}"); + } + + if let Some(version) = macho.source_version() { + format!("{version:?}"); + } + + if let Some(cmd) = macho.thread_command() { + format!("{cmd:?}"); + } + + if let Some(rpath) = macho.rpath() { + format!("{rpath:?}"); + } + + if let Some(routine) = macho.routine() { + format!("{routine:?}"); + } + + if let Some(symbol_command) = macho.symbol_command() { + format!("{symbol_command:?}"); + } + + if let Some(dynamic_symbol) = macho.dynamic_symbol() { + format!("{dynamic_symbol:?}"); + for sym in dynamic_symbol.indirect_symbols() { + format!("{}", sym.name()); + } + } + + if let Some(code_signature) = macho.code_signature() { + format!("{code_signature:?}"); + } + + if let Some(code_signature_dir) = macho.code_signature_dir() { + format!("{code_signature_dir:?}"); + } + + if let Some(data_in_code) = macho.data_in_code() { + format!("{data_in_code:?}"); + } + + if let Some(segment_split_info) = macho.segment_split_info() { + format!("{segment_split_info:?}"); + } + + if let Some(encryption_info) = macho.encryption_info() { + format!("{encryption_info:?}"); + } + + if let Some(sub_framework) = macho.sub_framework() { + format!("{sub_framework:?}"); + } + + for sc in macho.subclients() { + format!("{sc:?}"); + } + + if let Some(dyld_environment) = macho.dyld_environment() { + format!("{dyld_environment:?}"); + } + + if let Some(build_version) = macho.build_version() { + format!("{build_version:?}"); + } + + if let Some(dyld_chained_fixups) = macho.dyld_chained_fixups() { + format!("{dyld_chained_fixups:?}"); + } + + if let Some(dyld_exports_trie) = macho.dyld_exports_trie() { + format!("{dyld_exports_trie:?}"); + } + + if let Some(two_level_hints) = macho.two_level_hints() { + format!("{two_level_hints:?}"); + } + + if let Some(linker_opt_hint) = macho.linker_opt_hint() { + format!("{linker_opt_hint:?}"); + } + + if let Some(version_min) = macho.version_min() { + format!("{version_min:?}"); + } +} + +fn test_with(bin_name: &str) { + let path = utils::get_macho_sample(bin_name).unwrap(); + let path_str = path.to_str(); + if let Some(Binary::MachO(fat)) = Binary::parse(path_str.unwrap()) { + for bin in fat.iter() { + explore_macho(bin_name, &bin); + } + fat.with_cpu(CpuType::ARM64); + fat.with_cpu(CpuType::HPPA); + } + + // Test Read + Seek interface + let mut file = std::fs::File::open(path).expect("Can't open the file"); + let binary = Binary::from(&mut file); + assert!(matches!(binary, Some(Binary::MachO(_)))); +} + +fn test_with_str(name: &str, path_str: &str) { + if let Some(lief::Binary::MachO(fat)) = lief::Binary::parse(path_str) { + for bin in fat.iter() { + explore_macho(name, &bin); + } + } +} + +fn test_with_fullpath(name: &str, suffix: &str) { + let path = utils::get_sample(Path::new(suffix)).unwrap(); + let path_str = path.to_str().unwrap(); + test_with_str(name, path_str); +} + +#[test] +fn test_api() { + let mut dir = env::temp_dir(); + dir.push("lief_macho_test.log"); + logging::set_path(dir.as_path()); + + test_with("alivcffmpeg_armv7.dylib"); + test_with( + "9edfb04c55289c6c682a25211a4b30b927a86fe50b014610d04d6055bd4ac23d_crypt_and_hash.macho", + ); + test_with("MachO64_x86-64_binary_safaridriver.bin"); + test_with("FAT_MachO_x86_x86-64_library_libdyld.dylib"); + test_with("ios1-expr.bin"); + test_with("json_api.cpp_1.o"); + test_with("python3_issue_476.bin"); + test_with("FAT_MachO_x86_x86-64_library_libc++abi.dylib"); + test_with("libadd_unknown_cmd.so"); + test_with("StocksAnalytics"); + test_with("liblog_srp.dylib"); + test_with("binary.metallib"); + test_with("variants_alt.dylib"); + test_with_fullpath("CoreFoundation", "private/MachO/CoreFoundation"); + test_with_fullpath("xpcproxy", "private/MachO/xpcproxy"); + test_with_fullpath( + "kernelcache.release.iPhone17.5", + "private/MachO/kernelcache.release.iPhone17.5", + ); + test_with_fullpath( + "lief-dwarf-plugin", + "MachO/lief-dwarf-plugin-darwin-arm64.dylib", + ); +} + +#[test] +fn test_thread_local_variables() { + use lief::generic::Section as GenericSection; + use lief::macho::section::Type; + use lief::macho::{MachOSection, Section, ThreadLocalVariables}; + + let path = utils::get_macho_sample("lief-dwarf-plugin-darwin-arm64.dylib").unwrap(); + let Binary::MachO(fat) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting a MachO"); + }; + let macho = fat.iter().next().unwrap(); + + let thread_vars = macho + .sections() + .find(|s| s.section_type() == Type::THREAD_LOCAL_VARIABLES); + assert!(thread_vars.is_some()); + + let section = thread_vars.unwrap(); + assert_eq!(section.name(), "__thread_vars"); + assert_eq!(section.segment_name(), "__DATA"); + assert_eq!(section.section_type(), Type::THREAD_LOCAL_VARIABLES); + format!("{section:?}"); + + let Section::ThreadLocalVariables(ref tlv) = section else { + panic!("Expected Section::ThreadLocalVariables variant"); + }; + + assert_eq!(tlv.nb_thunks(), 2); + + let thunks: Vec<_> = tlv.thunks().collect(); + assert_eq!(thunks.len(), 2); + assert_eq!(thunks[0].offset(), 0); + assert_eq!(thunks[1].offset(), 0x18); + format!("{:?}", thunks[0]); + format!("{:?}", thunks[1]); +} + +#[test] +fn test_mut_api() { + let path = utils::get_macho_sample("FAT_MachO_x86_x86-64_library_libc++abi.dylib").unwrap(); + let Binary::MachO(fat) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + for mut bin in fat.iter() { + bin.add_library("this_is_a_dylib.dylib"); + let tmpfile = tempfile::NamedTempFile::new().unwrap(); + bin.write(tmpfile.path()); + } + + let path = utils::get_macho_sample("json_api.cpp_1.o").unwrap(); + let Binary::MachO(fat) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting an ELF"); + }; + for mut bin in fat.iter() { + let tmpfile = tempfile::NamedTempFile::new().unwrap(); + bin.write_with_config(tmpfile.path(), Config::default()); + } +} + +#[test] +fn test_lazy_load_dylib_info_mut() { + let path = utils::get_sample(Path::new("private/MachO/xpcproxy")).unwrap(); + let Binary::MachO(fat) = Binary::parse(path.to_str().unwrap()).unwrap() else { + panic!("Expecting a MachO"); + }; + + let tmpfile = tempfile::NamedTempFile::new().unwrap(); + let mut cryptex_path_before = String::new(); + let mut cryptex_content_before: Vec = Vec::new(); + for mut bin in fat.iter() { + for (idx, info) in bin.lazy_load_dylib_infos().enumerate() { + if idx == 1 { + cryptex_path_before = info.load_path(); + cryptex_content_before = info.content().to_vec(); + } + } + + for (idx, mut info) in bin.lazy_load_dylib_infos().enumerate() { + if idx == 0 { + info.set_load_path("/usr/lib/rust_relocated.dylib"); + info.set_flags(0x2); + info.set_may_be_missing(true); // -> flags 0x3 + info.set_pointer_format(2); + info.set_flag_image_offset(0x4242); + info.set_chain_start_image_offset(0); // disables the chain walk + info.set_symbols(&["_rust_sym_a", "_rust_sym_b"]); + info.add_symbol("_rust_sym_c"); + } + } + bin.write(tmpfile.path()); + } + + let Binary::MachO(fat) = Binary::parse(tmpfile.path().to_str().unwrap()).unwrap() else { + panic!("Expecting a MachO"); + }; + for bin in fat.iter() { + let infos: Vec<_> = bin.lazy_load_dylib_infos().collect(); + assert_eq!(infos.len(), 2); + + let first = &infos[0]; + assert_eq!(first.load_path(), "/usr/lib/rust_relocated.dylib"); + assert_eq!(first.flags(), 0x3); + assert!(first.may_be_missing()); + assert_eq!(first.pointer_format(), 2); + assert_eq!(first.flag_image_offset(), 0x4242); + assert_eq!(first.chain_start_image_offset(), 0); + assert_eq!(first.fixups().count(), 0); + assert_eq!( + first.symbols(), + vec![ + "_rust_sym_a".to_string(), + "_rust_sym_b".to_string(), + "_rust_sym_c".to_string(), + ] + ); + + let second = &infos[1]; + assert_eq!(second.load_path(), cryptex_path_before); + assert_eq!(second.content(), cryptex_content_before.as_slice()); + } +} diff --git a/vendor/lief/api/rust/crates/lief/tests/objc_tests.rs b/vendor/lief/api/rust/crates/lief/tests/objc_tests.rs new file mode 100644 index 0000000..e82a0d8 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/objc_tests.rs @@ -0,0 +1,134 @@ +#![allow(warnings)] +mod utils; +use lief; +use std::path::Path; + +fn explore_method(meth: &lief::objc::Method) { + println!( + "{}{}{}{}{}", + meth.name(), + meth.mangled_type(), + meth.address(), + meth.address(), + meth.is_instance() + ); +} + +fn explore_proptocol(prot: &lief::objc::Protocol) { + println!("{}", prot.to_decl()); + println!("{}", prot.to_decl_with_opt(&lief::objc::DeclOpt::default())); + println!("{}", prot.mangled_name()); + + for meth in prot.optional_methods() { + explore_method(&meth); + } + + for meth in prot.required_methods() { + explore_method(&meth); + } + + for prop in prot.properties() { + explore_property(&prop); + } +} + +fn explore_property(prop: &lief::objc::Property) { + println!("{}{}", prop.name(), prop.attribute()); +} + +fn explore_ivar(ivar: &lief::objc::IVar) { + println!("{}{}", ivar.name(), ivar.mangled_type()); +} + +fn explore_class(class: &lief::objc::Class) { + println!("{}", class.to_decl()); + println!( + "{}", + class.to_decl_with_opt(&lief::objc::DeclOpt::default()) + ); + println!( + "{}{}{:?}", + class.name(), + class.demangled_name(), + class.is_meta() + ); + if let Some(parent) = class.super_class() { + explore_class(&parent); + } + + for meth in class.methods() { + explore_method(&meth); + } + + for prot in class.protocols() { + explore_proptocol(&prot); + } + + for prop in class.properties() { + explore_property(&prop); + } + + for ivar in class.ivars() { + explore_ivar(&ivar); + } +} + +fn explore_metadata(name: &str, metadata: &lief::objc::Metadata) { + for cls in metadata.classes() { + explore_class(&cls); + } + + for prot in metadata.protocols() { + explore_proptocol(&prot); + } + + println!("{}", metadata.to_decl()); + println!( + "{}", + metadata.to_decl_with_opt(&lief::objc::DeclOpt::default()) + ); + + if name == "Module_Framework" { + assert!(metadata.class_by_name("GADGestureRecognizer").is_some()); + assert!( + metadata + .class_by_name("GADGestureRecognizer_xxxx") + .is_none() + ); + + assert!(metadata.protocol_by_name("PINCaching").is_some()); + assert!(metadata.protocol_by_name("PINCaching_xxx").is_none()); + } +} + +fn test_with_str(name: &str, path_str: &str) { + if let Some(lief::Binary::MachO(fat)) = lief::Binary::parse(path_str) { + for bin in fat.iter() { + if let Some(metadata) = bin.objc_metadata() { + explore_metadata(name, &metadata); + } + } + } +} + +fn test_with_fullpath(name: &str, suffix: &str) { + let path = utils::get_sample(Path::new(suffix)).unwrap(); + let path_str = path.to_str().unwrap(); + test_with_str(name, path_str); +} + +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + + test_with_fullpath("DebugHierarchyKit", "MachO/ios17/DebugHierarchyKit"); + test_with_fullpath( + "NTKPrideWeaveFaceBundleCompanion", + "MachO/ios17/NTKPrideWeaveFaceBundleCompanion", + ); + test_with_fullpath("RNCryptor.bin", "MachO/RNCryptor.bin"); + test_with_fullpath("SingPass", "private/MachO/SingPass"); + test_with_fullpath("Module_Framework", "private/MachO/Module_Framework"); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/pdb_tests.rs b/vendor/lief/api/rust/crates/lief/tests/pdb_tests.rs new file mode 100644 index 0000000..ba1a453 --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/pdb_tests.rs @@ -0,0 +1,191 @@ +#![allow(warnings)] +mod utils; +use lief::pdb::types::classlike::ClassLike; +use lief::{self, pdb::types::PdbType}; + +use std::path::Path; + +fn explore_trait_type(ty: &dyn PdbType) { + println!( + "{} {}", + ty.name().unwrap_or("".to_string()), + ty.size().unwrap_or(0) + ); +} + +fn explore_trait_classlike(ty: &dyn ClassLike) { + println!("{}", ty.unique_name()); + for meth in ty.methods() { + println!("{}", meth.name()); + } + for attr in ty.attributes() { + println!("{} {}", attr.name(), attr.field_offset()); + if let Some(attr_ty) = attr.get_type() { + match attr_ty { + lief::pdb::Type::Simple(_) => { + println!("Simple"); + } + lief::pdb::Type::Array(_) => { + println!("Array"); + } + lief::pdb::Type::BitField(_) => { + println!("BitField"); + } + lief::pdb::Type::Class(_) => { + println!("Class"); + } + lief::pdb::Type::Structure(_) => { + println!("Structure"); + } + lief::pdb::Type::Interface(_) => { + println!("Interface"); + } + lief::pdb::Type::Enum(_) => { + println!("Enum"); + } + lief::pdb::Type::Function(_) => { + println!("Function"); + } + lief::pdb::Type::Modifier(_) => { + println!("Modifier"); + } + lief::pdb::Type::Pointer(_) => { + println!("Pointer"); + } + lief::pdb::Type::Union(_) => { + println!("Union"); + } + lief::pdb::Type::Generic(_) => { + println!("Generic"); + } + } + } + } +} + +fn explore_type(ty: &lief::pdb::Type) { + match ty { + lief::pdb::Type::Simple(t) => { + explore_trait_type(t); + } + lief::pdb::Type::Array(t) => { + explore_trait_type(t); + } + lief::pdb::Type::BitField(t) => { + explore_trait_type(t); + } + lief::pdb::Type::Class(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + lief::pdb::Type::Structure(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + lief::pdb::Type::Interface(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + lief::pdb::Type::Enum(t) => { + explore_trait_type(t); + } + lief::pdb::Type::Function(t) => { + explore_trait_type(t); + } + lief::pdb::Type::Modifier(t) => { + explore_trait_type(t); + if let Some(underlying) = t.underlying_type() { + explore_type(&underlying); + } + } + lief::pdb::Type::Pointer(t) => { + explore_trait_type(t); + + if let Some(underlying) = t.underlying_type() { + explore_type(&underlying); + } + } + lief::pdb::Type::Union(t) => { + explore_trait_type(t); + explore_trait_classlike(t); + } + lief::pdb::Type::Generic(t) => { + explore_trait_type(t); + } + } +} + +fn explore_pdb(name: &str, pdb: &lief::pdb::DebugInfo) { + println!("{} {}", pdb.age(), pdb.guid()); + assert!(!pdb.type_by_index(3).is_none()); + assert!(pdb.type_by_index(4000000000).is_none()); + + pdb.public_symbol_by_name("foo"); + pdb.public_symbol_by_name("MiSyncSystemPdes"); + + for ty in pdb.types() { + explore_type(&ty); + } + + for sym in pdb.public_symbols() { + println!( + "{}{}{}0x{:x}", + sym.name(), + sym.demangled_name(), + sym.section_name().unwrap_or("".to_string()), + sym.rva(), + ); + } + + for cu in pdb.compilation_units() { + println!("{}{}", cu.module_name(), cu.object_filename()); + for src in cu.sources() { + println!("{}", src); + } + for func in cu.functions() { + println!( + "{} {} {} {} {:?}", + func.name(), + func.rva(), + func.code_size(), + func.section_name(), + func.debug_location() + ); + } + + if let Some(metadata) = cu.build_metadata() { + println!("{:?}{}", metadata, metadata); + } + } +} + +fn test_with(name: &str) { + let path = utils::get_pdb_sample(name).unwrap(); + let path_str = path.to_str(); + if let Some(pdb) = lief::pdb::load(path_str.unwrap()) { + explore_pdb(name, &pdb); + } +} + +fn test_with_fullpath(name: &str, suffix: &str) { + let path = utils::get_sample(Path::new(suffix)).unwrap(); + let path_str = path.to_str().unwrap(); + if let Some(pdb) = lief::pdb::load(path_str) { + explore_pdb(name, &pdb); + } +} + +#[test] +fn test_api() { + if !lief::is_extended() { + return; + } + test_with("ntkrnlmp.pdb"); + test_with("libdispatch.pdb"); + test_with("libobjc2.pdb"); + + test_with_fullpath("LIEF.pdb", "private/PDB/LIEF.pdb"); + test_with_fullpath("ast_grep.pdb", "private/PDB/ast_grep.pdb"); + test_with_fullpath("libcrypto-3-x64.pdb", "private/PDB/libcrypto-3-x64.pdb"); + test_with_fullpath("libssl-3-x64.pdb", "private/PDB/libssl-3-x64.pdb"); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/pe_tests.rs b/vendor/lief/api/rust/crates/lief/tests/pe_tests.rs new file mode 100644 index 0000000..795306c --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/pe_tests.rs @@ -0,0 +1,517 @@ +#![allow(warnings)] +mod utils; +use lief::Binary; +use lief::generic::Binary as GenericBinary; +use lief::generic::Section as GenericSection; +use lief::generic::Symbol; +use lief::logging; +use lief::pe::ParserConfig; +use lief::pe::debug::Entries as DebugEntries; +use lief::pe::load_configuration::LoadConfiguration; +use lief::pe::resources::{Node, NodeBase}; +use lief::pe::signature::Signature; +use lief::pe::signature::attributes::Attribute; +use lief::pe::signature::content_info::Content; +use lief::pe::{Algorithms, data_directory, signature}; +use std::env; +use std::fmt::format; +use std::io::Cursor; + +fn get_leaf<'a>(node: &'a Node) -> Option<&'a Node<'a>> { + match node { + Node::Data(_) => { + return Some(node); + } + + Node::Directory(dir) => { + for child in dir.children() { + if let Some(Node::Data(data)) = get_leaf(&child) { + format!("{}", data.content().len()); + format!("{data:?}"); + } + } + } + } + None +} + +fn explore_sig_attribute(attr: &Attribute) { + match attr { + Attribute::ContentType(item) => { + format!("{item:?}"); + } + Attribute::GenericType(item) => { + format!("{item:?}"); + } + Attribute::MsSpcNestedSignature(item) => { + format!("{item:?}"); + explore_signature(&item.signature()); + } + Attribute::MsSpcStatementType(item) => { + format!("{item:?}"); + } + Attribute::PKCS9AtSequenceNumber(item) => { + format!("{item:?}"); + } + Attribute::PKCS9CounterSignature(item) => { + format!("{item:?}"); + let signer = item.signer(); + println!("{}", signer.raw_auth_data().len()); + for attr in signer.authenticated_attributes() { + explore_sig_attribute(&attr); + } + + for attr in signer.unauthenticated_attributes() { + explore_sig_attribute(&attr); + } + } + Attribute::PKCS9MessageDigest(item) => { + format!("{item:?}"); + format!("{}", item.digest().len()); + } + Attribute::PKCS9SigningTime(item) => { + format!("{item:?}"); + } + Attribute::SpcSpOpusInfo(item) => { + format!("{item:?}"); + } + Attribute::MsManifestBinaryID(item) => { + format!("{}", item.manifest_id()); + } + Attribute::MsCounterSign(item) => { + let content_info = item.content_info(); + format!("{content_info:?}"); + for crt in item.certificates() { + format!("{crt:?}"); + format!("{}", crt.serial_number().len()); + format!("{}", crt.raw().len()); + format!("{}", crt.signature().len()); + + if let Some(rsa_info) = crt.rsa_info() { + format!("{rsa_info:?}"); + format!("{}", rsa_info.N().bits()); + format!("{}", rsa_info.E().bits()); + format!("{}", rsa_info.D().bits()); + format!("{}", rsa_info.P().bits()); + format!("{}", rsa_info.Q().bits()); + } + } + for signer in item.signers() { + format!("{signer:?}"); + if let Some(crt) = signer.cert() { + format!("{crt:?}"); + } + format!("{}", signer.encrypted_digest().len()); + format!("{}", signer.serial_number().len()); + + for attr in signer.authenticated_attributes() { + explore_sig_attribute(&attr); + } + + for attr in signer.unauthenticated_attributes() { + explore_sig_attribute(&attr); + } + } + let info = item.content_info(); + if let Some(value) = info.value() { + format!("{:?}", value); + match value { + Content::SpcIndirectData(data) => { + format!("{:?}", data); + format!("{}", data.digest().len()); + } + Content::PKCS9TSTInfo(data) => { + println!("PKCS9TSTInfo"); + } + Content::Generic(generic) => { + println!("{}", generic.oid()); + format!("{}", generic.raw().len()); + } + } + } + } + Attribute::SigningCertificateV2(item) => { + println!("SigningCertificateV2"); + } + Attribute::SpcRelaxedPeMarkerCheck(item) => { + println!("SpcRelaxedPeMarkerCheck"); + } + } +} + +fn explore_signature(signature: &Signature) { + format!("{signature:?}"); + let content_info = signature.content_info(); + format!("{content_info:?}"); + for crt in signature.certificates() { + format!("{crt:?}"); + format!("{}", crt.serial_number().len()); + format!("{}", crt.raw().len()); + format!("{}", crt.signature().len()); + + if let Some(rsa_info) = crt.rsa_info() { + format!("{rsa_info:?}"); + format!("{}", rsa_info.N().bits()); + format!("{}", rsa_info.E().bits()); + format!("{}", rsa_info.D().bits()); + format!("{}", rsa_info.P().bits()); + format!("{}", rsa_info.Q().bits()); + } + } + for signer in signature.signers() { + format!("{signer:?}"); + if let Some(crt) = signer.cert() { + format!("{crt:?}"); + } + format!("{}", signer.encrypted_digest().len()); + format!("{}", signer.serial_number().len()); + + for attr in signer.authenticated_attributes() { + explore_sig_attribute(&attr); + } + + for attr in signer.unauthenticated_attributes() { + explore_sig_attribute(&attr); + } + } + + let info = signature.content_info(); + if let Some(value) = info.value() { + format!("{:?}", value); + match value { + Content::SpcIndirectData(data) => { + format!("{:?}", data); + format!("{}", data.digest().len()); + } + Content::PKCS9TSTInfo(data) => { + println!("PKCS9TSTInfo"); + } + Content::Generic(generic) => { + println!("{}", generic.oid()); + format!("{}", generic.raw().len()); + } + } + } +} + +fn explore_pe(bin_name: &str, pe: &lief::pe::Binary) { + format!("{pe:?}"); + + let dos_header = pe.dos_header(); + format!("{dos_header:?}"); + + let optional_header = pe.optional_header(); + format!("{optional_header:?}"); + format!( + "checksum: {}, computed: {}", + optional_header.checksum(), + pe.compute_checksum() + ); + + let header = pe.header(); + format!("{header:?}"); + + format!("{} {}", pe.virtual_size(), pe.sizeof_headers()); + + if let Some(dir) = pe.data_directory_by_type(data_directory::Type::RESOURCE_TABLE) { + if !dir.content().is_empty() { + let tree = lief::pe::ResourceNode::from_slice(dir.content(), dir.rva() as u64); + assert!(tree.is_some()); + } + } + + if let Some(tls) = pe.tls() { + format!("{tls:?}"); + format!("{}", tls.data_template().len()); + format!("{:?}", tls.addressof_raw_data()); + } + + if let Some(export) = pe.export() { + format!("{export:?}"); + for entry in export.entries() { + format!("{entry:?}"); + if lief::is_extended() { + format!("{}", entry.demangled_name()); + } + } + } + + if let Some(resources) = pe.resources() { + format!("{resources:?}"); + match resources { + Node::Data(_) => {} + + Node::Directory(dir) => { + for child in dir.children() { + format!("{}", dir.depth()); + format!("{child:?}"); + } + } + } + } + + if let Some(resources) = pe.resources() { + if let Some(leaf) = get_leaf(&resources) { + format!("{leaf:?}"); + } + } + + for coff_str in pe.coff_string_table() { + format!("{}:{}", coff_str.str(), coff_str.offset()); + } + + if let Some(config) = pe.load_configuration() { + format!("{config:?}"); + + if let Some(enclave_config) = config.enclave_config() { + format!("{enclave_config:?} {enclave_config}"); + for entry in enclave_config.imports() { + format!("{entry:?} {entry}"); + } + } + + if let Some(volatile) = config.volatile_metadata() { + format!("{volatile:?} {volatile}"); + for range in volatile.info_ranges() { + format!("{range:?}"); + } + } + } + + if let Some(header) = pe.rich_header() { + format!("{header:?}"); + for entry in header.entries() { + format!("{entry:?}"); + } + } + + let _ = pe.resources_manager(); + + for imp in pe.imports() { + format!("{imp:?}"); + for entry in imp.entries() { + format!("{entry:?}"); + if lief::is_extended() { + format!("{}", entry.demangled_name()); + } + } + } + + for dir in pe.data_directories() { + format!("{dir:?}"); + } + + for sym in pe.symbols() { + format!("{sym:?}"); + for aux in sym.auxiliary_symbols() { + format!("{aux:?}"); + } + } + + for section in pe.sections() { + format!("{section:?}"); + format!("{}", section.padding().len()); + if let Some(coff_str) = section.coff_string() { + format!("{}", coff_str.str()); + } + } + + for relocation in pe.relocations() { + format!("{relocation:?}"); + for entry in relocation.entries() { + format!("{entry:?}"); + } + } + + for delay_import in pe.delay_imports() { + format!("{delay_import:?}"); + for entry in delay_import.entries() { + format!("{entry:?}"); + if lief::is_extended() { + format!("{}", entry.demangled_name()); + } + } + } + + for signature in pe.signatures() { + explore_signature(&signature); + } + + for debug in pe.debug() { + format!("{debug:?}"); + match debug { + DebugEntries::Pogo(pogo) => { + for entry in pogo.entries() { + format!("{entry:?}"); + } + } + DebugEntries::Repro(repro) => { + assert!(!repro.hash().is_empty()); + } + _ => {} + } + } + + for func in pe.functions() { + format!("{func:?}"); + } + + for exception in pe.exceptions() { + format!("{exception:?}"); + } + + if let Some(nested) = pe.nested_pe_binary() { + explore_pe(bin_name, &nested); + } + + format!( + "overlay: {}, len: {}", + pe.overlay_offset(), + pe.overlay().len() + ); + + assert!(pe.entrypoint() > 0); + + assert!(!pe.dos_stub().is_empty()); + assert!(!pe.authentihash(Algorithms::SHA_256).is_empty()); + + if bin_name == "ntoskrnl.exe" { + assert_eq!(pe.rva_to_offset(0xA85000), 0x9f3000); + assert_eq!(pe.va_to_offset(0x140000000 + 0xA85000), 0x9f3000); + assert!(pe.section_from_offset(0x9f3000).is_some()); + assert!(pe.section_from_offset(0x10009f3000).is_none()); + + assert!(pe.section_from_rva(0xA85000).is_some()); + assert!(pe.section_from_rva(0x100A85000).is_none()); + + assert!( + !pe.content_from_virtual_address(0x140000000 + 0xA85000, 0x10) + .is_empty() + ); + assert!(!pe.content_from_virtual_address(0xA85000, 0x10).is_empty()); + assert!( + pe.content_from_virtual_address(0xaaaaaaaaaaaa, 0x10) + .is_empty() + ); + + assert!(pe.section_by_name(".data").is_some()); + assert!(pe.section_by_name(".xdata").is_none()); + + assert!( + pe.data_directory_by_type(data_directory::Type::IMPORT_TABLE) + .is_some() + ); + + assert!(pe.import_by_name("BOOTVID.dll").is_some()); + assert!(pe.import_by_name("foo.dll").is_none()); + } + + if bin_name == "PE32_x86-64_binary_avast-free-antivirus-setup-online.exe" { + assert_eq!( + pe.verify_signature(signature::VerificationChecks::DEFAULT), + signature::VerificationFlags::OK + ); + let signature = pe.signatures().last().expect("Error"); + let raw_sig = signature.raw_der(); + let mut cursor = Cursor::new(raw_sig); + + let detached = Signature::from(&mut cursor).expect("Error"); + assert_eq!( + pe.verify_with_signature(&detached, signature::VerificationChecks::DEFAULT), + signature::VerificationFlags::OK + ); + } + + if bin_name == "PE64_x86-64_binary_cmd.exe" { + assert!(pe.delay_import_by_name("foo.dll").is_none()); + assert!(pe.delay_import_by_name("SHELL32.dll").is_some()); + } +} + +fn test_with(bin_name: &str) { + let path = utils::get_pe_sample(bin_name).unwrap(); + let path_str = path.to_str(); + if let Some(pe) = + lief::pe::Binary::parse_with_config(path_str.unwrap(), &ParserConfig::with_all_options()) + { + explore_pe(bin_name, &pe); + } + + // Test Read + Seek interface + let mut file = std::fs::File::open(path).expect("Can't open the file"); + let binary = Binary::from(&mut file); + assert!(matches!(binary, Some(Binary::PE(_)))); +} + +fn test_signature(name: &str) { + let path = utils::get_pkcs7_sample(name).unwrap(); + let path_str = path.to_str(); + if let Some(sig) = Signature::from_file(path_str.unwrap()) { + explore_signature(&sig); + } +} + +#[test] +fn test_api() { + let mut dir = env::temp_dir(); + dir.push("lief_pe_test.log"); + logging::set_path(dir.as_path()); + + test_with("ntoskrnl.exe"); + test_with("steam.exe"); + test_with("test.debug.repro.exe"); + test_with("PE64_x86-64_library_libLIEF.dll"); + test_with("PE32_x86-64_binary_avast-free-antivirus-setup-online.exe"); + test_with("PE32_x86-64_binary_self-signed.exe"); + test_with("PE64_x86-64_binary_winhello64-mingw.exe"); + test_with("PE64_x86-64_binary_cmd.exe"); + test_with("steam.exe"); + test_with("SFAPE.dll"); + test_with("LIEF-win64.dll"); + test_with("win11_arm64x_Windows.Media.Protection.PlayReady.dll"); + + test_signature("cert0.p7b"); + test_signature("cert3.p7b"); + test_signature("cert11.p7b"); + test_signature("cert9.p7b"); + test_signature("cert10.p7b"); +} + +#[test] +fn test_offset_to_rva() { + let path = utils::get_pe_sample("pe_reader.exe").unwrap(); + let pe = match Binary::parse(path.to_str().unwrap()) { + Some(Binary::PE(pe)) => pe, + _ => panic!("Expected PE binary"), + }; + + let section_text = pe.section_by_name(".text").expect("Error"); + let offset = section_text.offset() + 0x100; + let rva = pe.offset_to_rva(offset); + let expected_rva = section_text.virtual_address() + 0x100; + + assert_eq!(rva, expected_rva); +} + +#[test] +fn test_offset_to_va() { + let path = utils::get_pe_sample("pe_reader.exe").unwrap(); + let pe = match Binary::parse(path.to_str().unwrap()) { + Some(Binary::PE(pe)) => pe, + _ => panic!("Expected PE binary"), + }; + + let section_text = pe.section_by_name(".text").expect("Error"); + let offset = section_text.offset() + 0x100; + let va = pe.offset_to_virtual_address(offset, 0).expect("Error"); + let expected_va = pe.optional_header().imagebase() + section_text.virtual_address() + 0x100; + + assert_eq!(va, expected_va); + + // Test with slide + let slide = 0x10000000; + let va_slide = pe.offset_to_virtual_address(offset, slide).expect("Error"); + let expected_va_slide = slide + section_text.virtual_address() + 0x100; + + assert_eq!(va_slide, expected_va_slide); +} diff --git a/vendor/lief/api/rust/crates/lief/tests/runtime_tests.rs b/vendor/lief/api/rust/crates/lief/tests/runtime_tests.rs new file mode 100644 index 0000000..063691d --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/runtime_tests.rs @@ -0,0 +1,349 @@ +#![allow(warnings)] +use lief; +use lief::runtime::memory::{MmapFlags, Perm}; +use lief::runtime::{Memory, Module, Process}; + +fn test_process() { + println!( + "{} {} {} {:?} {:?}", + Process::pid(), + Process::tid(), + Process::page_size(), + Process::arch(), + Process::platform() + ); +} + +fn test_modules() { + for m in lief::runtime::modules() { + println!( + "{} {} {:#x} {:#x} {:#x} {:?}", + m.name(), + m.path(), + m.imagebase(), + m.size(), + m.end(), + m.contains(0) + ); + assert!(lief::runtime::module_from_addr(m.imagebase()).is_some()); + assert!(lief::runtime::module_from_path(m.path()).is_some()); + assert!(lief::runtime::module_from_name(&m.name()).is_some()); + match &m { + lief::runtime::Modules::Linux(linux) => {} + + lief::runtime::Modules::Android(android) => {} + + lief::runtime::Modules::Windows(win) => {} + + lief::runtime::Modules::Osx(osx) => {} + } + } +} + +fn test_osx_host() { + use lief::runtime::osx::Host; + let version = Host::os_version_name(); + println!("os_version_name: {}", version); + assert!(!version.is_empty()); +} + +fn test_windows_host() { + use lief::runtime::windows::{Host, Version}; + let version = Host::version().expect("missing version"); + println!("windows version: {}", version); + + // Sanity checks on the Version type. + let v = Version::new(10, 0, 26200); + assert_eq!(v.major, 10); + assert_eq!(v.minor, 0); + assert_eq!(v.build_number, 26200); + assert_eq!(format!("{}", v), "10.0.26200"); + + assert!(Version::new(10, 0, 10240) < Version::new(10, 0, 26100)); + assert_eq!(Version::new(6, 1, 7600), Version::new(6, 1, 7600)); + + // Any supported Windows host should be at least Windows 7 (6.1.x). + assert!(version >= Version::new(6, 1, 0)); +} + +fn test_windows_process() { + use lief::runtime::windows::Process; + let peb = Process::peb().expect("missing PEB"); + + println!( + "being_debugged={} ldr={:#x} process_parameters={:#x} session_id={}", + peb.being_debugged(), + peb.ldr(), + peb.process_parameters(), + peb.session_id() + ); + + // The loader data and the process parameters are always populated by the + // Windows loader. + assert_ne!(peb.ldr(), 0); + assert_ne!(peb.process_parameters(), 0); + + let _ = peb.atl_thunk_slist_ptr(); + let _ = peb.atl_thunk_slist_ptr32(); + let _ = peb.post_process_init_routine(); + + // Iterate the loader's module list. + let entries: Vec<_> = peb.entries().collect(); + assert!(entries.len() > 1); + + let first = &entries[0]; + assert_ne!(first.dll_base(), 0); + assert!(first.size_of_image() > 0); + assert!(!first.base_dll_name().is_empty()); + assert!( + first + .full_dll_name() + .to_lowercase() + .ends_with(&first.base_dll_name().to_lowercase()) + ); + + // ntdll.dll is always loaded in a Windows process. + assert!( + entries + .iter() + .any(|e| e.base_dll_name().eq_ignore_ascii_case("ntdll.dll")) + ); +} + +fn test_linux_process() { + use lief::runtime::linux::Process; + let version = Process::glibc_version(); + println!("glibc_version: {:?}", version); + assert!(version.is_some()); + + let cmdline = Process::cmdline(); + println!("cmdline: {:?}", cmdline); + assert!(cmdline.is_some()); +} + +fn test_linux_module() { + let libc = lief::runtime::modules() + .find_map(|m| match m { + lief::runtime::Modules::Linux(linux) if linux.name().starts_with("libc") => Some(linux), + _ => None, + }) + .expect("expected libc to be loaded in the current process"); + + assert!(!libc.handle().is_null()); + assert!(!libc.dlsym("malloc".to_string()).is_null()); + assert!(libc.dlsym("__lief_does_not_exist__".to_string()).is_null()); + + let from_hdl = lief::runtime::linux::Module::from_handle(libc.handle()); + assert!(from_hdl.is_some()); + + let parsed = libc.parse_from_path().expect("parse_from_path failed"); + assert!(parsed.header().entrypoint() > 0); + + let config = lief::elf::ParserConfig::default(); + let parsed = libc + .parse_from_path_with_config(&config) + .expect("parse_from_path_with_config failed"); + assert!(parsed.header().entrypoint() > 0); + + let _ = libc.parse_from_memory(); + let _ = libc.parse_from_memory_with_config(&config); + + let data = libc.dump(); + assert_eq!(data.len() as u64, libc.size()); + assert_eq!(&data[..4], b"\x7fELF"); + + let out = std::env::temp_dir().join("lief_runtime_libc.dump"); + let written = libc.dump_to_file(&out); + assert_eq!(written.len() as u64, libc.size()); + assert_eq!(&written[..4], b"\x7fELF"); + assert_eq!(std::fs::read(&out).expect("dump file not written"), written); + let _ = std::fs::remove_file(&out); +} + +fn test_android() { + use lief::runtime::android::{Host, Process}; + + let sdk = Host::sdk_version(); + println!("android sdk_version: {:?}", sdk); + + let prop = Process::get_system_property("ro.build.version.sdk"); + println!("android ro.build.version.sdk: {:?}", prop); + + let cmdline = Process::cmdline(); + println!("android cmdline: {:?}", cmdline); + + let props: Vec<_> = Process::properties().collect(); + println!("android #properties: {}", props.len()); + for prop in &props { + assert!(!prop.name().is_empty()); + } + + if cfg!(target_os = "android") { + assert!(sdk.is_some_and(|v| v > 0)); + + let prop = prop.expect("missing ro.build.version.sdk"); + assert_eq!(prop.name(), "ro.build.version.sdk"); + assert!(!prop.value().is_empty()); + println!( + "property: {} = {} (serial: {})", + prop.name(), + prop.value(), + prop.serial() + ); + + assert!(cmdline.is_some()); + assert!(Process::get_system_property("lief.does.not.exist").is_none()); + + assert!(!props.is_empty()); + assert!(props.iter().any(|p| p.name() == "ro.build.version.sdk")); + } +} + +fn test_memory_layout() { + let regions: Vec<_> = lief::runtime::memory_layout().collect(); + + for region in ®ions { + println!( + "{:#x}-{:#x} ({:#x}) {}", + region.addr(), + region.end_addr(), + region.size(), + region.name() + ); + assert_eq!(region.end_addr(), region.addr() + region.size()); + } + + if lief::is_extended() { + assert!(!regions.is_empty()); + assert!(regions.iter().all(|r| !format!("{r}").is_empty())); + + // The regions backing this test binary must be part of the layout. + let self_addr = test_memory_layout as usize as u64; + assert!(regions.iter().any(|r| r.contains(self_addr))); + } +} + +fn test_memory() { + let mut chunk = Memory::mmap( + 0x4000, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ, + ) + .unwrap(); + println!( + "{:#x} {:#x} {:?} {:#x} {:#x}", + chunk.addr(), + chunk.size(), + chunk.permissions(), + chunk.page_start(), + chunk.page_end() + ); + + assert_eq!(chunk.permissions(), Perm::READ); + { + chunk.change_permissions(Perm::READ | Perm::WRITE); + assert_eq!(chunk.permissions(), Perm::READ | Perm::WRITE); + unsafe { + Memory::write::(chunk.addr(), 1); + assert_eq!(Memory::read::(chunk.addr()), 1); + } + chunk.change_permissions(Perm::READ); + assert_eq!(chunk.permissions(), Perm::READ); + } + + chunk.change_permissions(Perm::READ); + chunk.make_x(); + chunk.make_rw(); + chunk.make_rx(); + chunk.make_rwx(); + chunk.make_ro(); + + chunk.cache_flush(); + assert!(chunk.is_valid()); + + Memory::munmap(&mut chunk); + + let mut owned = Memory::mmap( + 0x1000, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ | Perm::WRITE, + ) + .unwrap(); + assert!(owned.is_valid()); + assert!(owned.deallocate().is_ok()); +} + +fn test_memory_hint() { + let page_size = Process::page_size() as u64; + + let mut reserved = Memory::mmap( + 2 * page_size, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ | Perm::WRITE, + ) + .unwrap(); + + // A misaligned hint is rounded up to the next page boundary + let mut chunk = Memory::mmap_hint( + reserved.addr() + page_size + 1, + page_size, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ, + ) + .unwrap(); + + assert_eq!(chunk.addr() % page_size, 0); + assert_eq!(chunk.size(), page_size); + Memory::munmap(&mut chunk); + + // A hint set to 0 is equivalent to the non-hinted version + let mut chunk = Memory::mmap_hint( + 0, + page_size, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ, + ) + .unwrap(); + assert!(chunk.is_valid()); + Memory::munmap(&mut chunk); + + // A hint that can't be page-aligned is rejected + assert!( + Memory::mmap_hint( + u64::MAX, + page_size, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ, + ) + .is_none() + ); + + Memory::munmap(&mut reserved); +} + +#[test] +fn test_runtime() { + if !lief::runtime::enabled() { + return; + } + test_process(); + test_modules(); + test_memory(); + test_memory_hint(); + test_memory_layout(); + test_android(); + + if cfg!(target_os = "macos") { + test_osx_host(); + } + + if cfg!(target_os = "windows") { + test_windows_host(); + test_windows_process(); + } + + if cfg!(target_os = "linux") { + test_linux_module(); + test_linux_process(); + } +} diff --git a/vendor/lief/api/rust/crates/lief/tests/utils.rs b/vendor/lief/api/rust/crates/lief/tests/utils.rs new file mode 100644 index 0000000..a43380f --- /dev/null +++ b/vendor/lief/api/rust/crates/lief/tests/utils.rs @@ -0,0 +1,60 @@ +#![allow(warnings)] +use std::env; +use std::path::{Path, PathBuf}; +use std::str::FromStr; + +pub fn get_sample_dir() -> Option { + match env::var_os("LIEF_SAMPLES_DIR") { + Some(val) => Some(val.into_string().unwrap_or("".to_string())), + None => { + panic!("Can't find 'LIEF_SAMPLES_DIR'"); + } + } +} + +pub fn get_sample_path() -> PathBuf { + let sample_dir = get_sample_dir().unwrap(); + PathBuf::from_str(sample_dir.as_str()).expect("Can't create a PathBuf") +} + +pub fn get_sample(path: &Path) -> Option { + let sample_dir = get_sample_dir()?; + let sample_dir_path = PathBuf::from_str(sample_dir.as_str()).ok()?; + Some(sample_dir_path.join(path)) +} + +#[allow(dead_code)] +pub fn get_elf_sample(name: &str) -> Option { + let suffix = Path::new("ELF").join(name); + get_sample(suffix.as_path()) +} + +#[allow(dead_code)] +pub fn get_pe_sample(name: &str) -> Option { + let suffix = Path::new("PE").join(name); + get_sample(suffix.as_path()) +} + +#[allow(dead_code)] +pub fn get_coff_sample(name: &str) -> Option { + let suffix = Path::new("COFF").join(name); + get_sample(suffix.as_path()) +} + +#[allow(dead_code)] +pub fn get_macho_sample(name: &str) -> Option { + let suffix = Path::new("MachO").join(name); + get_sample(suffix.as_path()) +} + +#[allow(dead_code)] +pub fn get_pkcs7_sample(name: &str) -> Option { + let suffix = Path::new("pkcs7").join(name); + get_sample(suffix.as_path()) +} + +#[allow(dead_code)] +pub fn get_pdb_sample(name: &str) -> Option { + let suffix = Path::new("PDB").join(name); + get_sample(suffix.as_path()) +} diff --git a/vendor/lief/api/rust/examples/Cargo.lock b/vendor/lief/api/rust/examples/Cargo.lock new file mode 100644 index 0000000..4fe1530 --- /dev/null +++ b/vendor/lief/api/rust/examples/Cargo.lock @@ -0,0 +1,2075 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "addr2line" +version = "0.25.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b5d307320b3181d6d7954e663bd7c774a838b8220fe0593c86d9fb09f498b4b" +dependencies = [ + "gimli", +] + +[[package]] +name = "adler2" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa" + +[[package]] +name = "anstyle" +version = "1.0.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" + +[[package]] +name = "atomic-waker" +version = "1.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1505bd5d3d116872e7271a6d4e16d81d0c8570876c8de68093a09ac269d8aac0" + +[[package]] +name = "autocfg" +version = "1.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53" + +[[package]] +name = "aws-lc-rs" +version = "1.18.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ce2b2dcc879c3bae0d371e77c99f2238400ef24ec001394befa67b6e543add9e" +dependencies = [ + "aws-lc-sys", + "zeroize", +] + +[[package]] +name = "aws-lc-sys" +version = "0.44.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f09fae7be8bb3174e05c6afdb34199e6dc0c7c04ba9fa237b1967adfbde27483" +dependencies = [ + "cc", + "cmake", + "dunce", + "fs_extra", + "pkg-config", +] + +[[package]] +name = "backtrace" +version = "0.3.76" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb531853791a215d7c62a30daf0dde835f381ab5de4589cfe7c649d2cbe92bd6" +dependencies = [ + "addr2line", + "cfg-if", + "libc", + "miniz_oxide", + "object", + "rustc-demangle", + "windows-link", +] + +[[package]] +name = "backtrace-ext" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "537beee3be4a18fb023b570f80e3ae28003db9167a751266b259926e25539d50" +dependencies = [ + "backtrace", +] + +[[package]] +name = "base64" +version = "0.22.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6" + +[[package]] +name = "bitflags" +version = "2.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b588b76d00fde79687d7646a9b5bdf3cc0f655e0bbd080335a95d7e96f3587da" + +[[package]] +name = "bumpalo" +version = "3.20.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72f5acc6cb2ba439de613abc23857ec3d78374d8ed5ac84e9d11336e87da8649" + +[[package]] +name = "bytes" +version = "1.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fc652a48c352aef3ea3aed32080501cf3ef6ed5da78602a020c991775b0aff04" + +[[package]] +name = "cc" +version = "1.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "509591b7bcd67f4ef775afad7662703b4935daaa6ec0e5605cfb1090b32a2b6d" +dependencies = [ + "find-msvc-tools", + "jobserver", + "libc", + "shlex", +] + +[[package]] +name = "cfg-if" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" + +[[package]] +name = "cfg_aliases" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f079e83a288787bcd14a6aea84cee5c87a67c5a3e660c30f557a3d24761b3527" + +[[package]] +name = "chacha20" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d524456ba66e72eb8b115ff89e01e497f8e6d11d78b70b1aa13c0fbd97540a81" +dependencies = [ + "cfg-if", + "cpufeatures", + "rand_core", +] + +[[package]] +name = "clap" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "473c7e07f409a8d772161724aa8db6a765a2532a70f9667eeb7b49d3d02fbdca" +dependencies = [ + "clap_builder", +] + +[[package]] +name = "clap_builder" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7b48fea5a88e9ae728a2dcbedbfc0e730f7d60da42e1cb049a83c9fb8b789889" +dependencies = [ + "anstyle", + "clap_lex", + "strsim", +] + +[[package]] +name = "clap_lex" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" + +[[package]] +name = "cmake" +version = "0.1.58" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c0f78a02292a74a88ac736019ab962ece0bc380e3f977bf72e376c5d78ff0678" +dependencies = [ + "cc", +] + +[[package]] +name = "codespan-reporting" +version = "0.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "af491d569909a7e4dee0ad7db7f5341fef5c614d5b8ec8cf765732aba3cff681" +dependencies = [ + "serde", + "termcolor", + "unicode-width 0.2.2", +] + +[[package]] +name = "combine" +version = "4.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ba5a308b75df32fe02788e748662718f03fde005016435c444eea572398219fd" +dependencies = [ + "bytes", + "memchr", +] + +[[package]] +name = "core-foundation" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2a6cd9ae233e7f62ba4e9353e81a88df7fc8a5987b8d445b4d90c879bd156f6" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "core-foundation-sys" +version = "0.8.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "773648b94d0e5d620f64f280777445740e61fe701025087ec8b57f45c791888b" + +[[package]] +name = "cpufeatures" +version = "0.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b2a41393f66f16b0823bb79094d54ac5fbd34ab292ddafb9a0456ac9f87d201" +dependencies = [ + "libc", +] + +[[package]] +name = "crc32fast" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511" +dependencies = [ + "cfg-if", +] + +[[package]] +name = "cxx" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6fe442a792c7c736eea18b32a7f8a3b63cf8aafabda6760042dc2fdeda456291" +dependencies = [ + "cc", + "cxx-build", + "cxxbridge-cmd", + "cxxbridge-flags", + "cxxbridge-macro", + "foldhash", + "link-cplusplus", +] + +[[package]] +name = "cxx-build" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3184a94384c663718698311a78a51ac00c484c10b4eeac06fb0a068c5f64fa2" +dependencies = [ + "cc", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "scratch", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-cmd" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0148d8fd1199329ddf1d157a5e134e51ceff37c6a7ddd38615c399d81cb05d8d" +dependencies = [ + "clap", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-flags" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "52850339faed2eaadd24e286dc1d8268cc6f8a7bd9524d713adc9099566b4c89" + +[[package]] +name = "cxxbridge-macro" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2c77c856545d886c9bd5215409ebb63b925e262135248b50c79e5a5f194ee47c" +dependencies = [ + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "deranged" +version = "0.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7cd812cc2bc1d69d4764bd80df88b4317eaef9e773c75226407d9bc0876b211c" +dependencies = [ + "powerfmt", +] + +[[package]] +name = "displaydoc" +version = "0.2.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6232dd377dcc64799954cbd3a9bb882e9cdc1308ccd87b1c098f1fb2eaf82a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "dunce" +version = "1.0.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92773504d58c093f6de2459af4af33faa518c13451eb8f2b5698ed3d36e7c813" + +[[package]] +name = "equivalent" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" + +[[package]] +name = "errno" +version = "0.3.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "find-msvc-tools" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d45db016d36b838f563236e9193d0ee6ce38f3f68b6c94e914b4929c96bbb890" + +[[package]] +name = "flate2" +version = "1.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c" +dependencies = [ + "miniz_oxide", + "zlib-rs", +] + +[[package]] +name = "foldhash" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77ce24cb58228fbb8aa041425bb1050850ac19177686ea6e0f41a70416f56fdb" + +[[package]] +name = "form_urlencoded" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cb4cb245038516f5f85277875cdaa4f7d2c9a0fa0468de06ed190163b1581fcf" +dependencies = [ + "percent-encoding", +] + +[[package]] +name = "fs_extra" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "42703706b716c37f96a77aea830392ad231f44c9e9a67872fa5548707e11b11c" + +[[package]] +name = "futures-channel" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1f9e3d69d39e4862ffed03ed071a76f9a13ba1d9109d355b0f0aa6b15e393c4" +dependencies = [ + "futures-core", + "futures-sink", +] + +[[package]] +name = "futures-core" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92d699e522242e69e3003b94ecc1f960f3a5e015aa7c5d7486e65ad01dd94f5e" + +[[package]] +name = "futures-io" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53c0fa8157de1303bfffdaa1cc2a673bfffb60102f76b0ef4441659124373fed" + +[[package]] +name = "futures-sink" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1944426bf7d03f1d14f708785e4b33efd750b36d48a157b836b3efc15ede8e1d" + +[[package]] +name = "futures-task" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cd417de3d1d015fc3bfd2b1ea46dfc7bab72ef86f1cc7cc9c78e728b34a6d1fd" + +[[package]] +name = "futures-util" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0d50a92467f8ba5dd6e3ee5d4bd04d73ab2e4e1c44474a0674821dfce14b79bc" +dependencies = [ + "futures-core", + "futures-io", + "futures-sink", + "futures-task", + "memchr", + "pin-project-lite", + "slab", +] + +[[package]] +name = "getrandom" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "wasi", + "wasm-bindgen", +] + +[[package]] +name = "getrandom" +version = "0.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "300e883d756b2e4ec94e02791f39b04b522276138852cfc41d9fb7e904106099" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "r-efi", + "rand_core", + "wasm-bindgen", +] + +[[package]] +name = "gimli" +version = "0.32.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e629b9b98ef3dd8afe6ca2bd0f89306cec16d43d907889945bc5d6687f2f13c7" + +[[package]] +name = "git-version" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1ad568aa3db0fcbc81f2f116137f263d7304f512a1209b35b85150d3ef88ad19" +dependencies = [ + "git-version-macro", +] + +[[package]] +name = "git-version-macro" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53010ccb100b96a67bc32c0175f0ed1426b31b655d562898e57325f81c023ac0" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "hashbrown" +version = "0.17.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" + +[[package]] +name = "http" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "918d3568bebf352712bc2ef3d46a8bcf1a75b373be6539de198e9105cbbf9ce0" +dependencies = [ + "bytes", + "itoa", +] + +[[package]] +name = "http-body" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ca2a8f2913ee65f60facd6a5905613afaa448497a0230cc41ce022d93290bc2c" +dependencies = [ + "bytes", + "http", +] + +[[package]] +name = "http-body-util" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "23169fe34a5fbcdd3f3862e78fb9b6fccd5f02a6dc6f732547005d45631ce71c" +dependencies = [ + "bytes", + "futures-core", + "http", + "http-body", + "pin-project-lite", +] + +[[package]] +name = "httparse" +version = "1.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6dbf3de79e51f3d586ab4cb9d5c3e2c14aa28ed23d180cf89b4df0454a69cc87" + +[[package]] +name = "hyper" +version = "1.11.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d22053281f852e11534f5198498373cbb59295120a20771d90f7ed1897490a72" +dependencies = [ + "atomic-waker", + "bytes", + "futures-channel", + "futures-core", + "http", + "http-body", + "httparse", + "itoa", + "pin-project-lite", + "smallvec", + "tokio", + "want", +] + +[[package]] +name = "hyper-rustls" +version = "0.27.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "33ca68d021ef39cf6463ab54c1d0f5daf03377b70561305bb89a8f83aab66e0f" +dependencies = [ + "http", + "hyper", + "hyper-util", + "rustls", + "tokio", + "tokio-rustls", + "tower-service", +] + +[[package]] +name = "hyper-util" +version = "0.1.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "96547c2556ec9d12fb1578c4eaf448b04993e7fb79cbaad930a656880a6bdfa0" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-util", + "http", + "http-body", + "hyper", + "ipnet", + "libc", + "percent-encoding", + "pin-project-lite", + "socket2", + "tokio", + "tower-service", + "tracing", +] + +[[package]] +name = "icu_collections" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4c6b649701667bbe825c3b7e6388cb521c23d88644678e83c0c4d0a621a34b43" +dependencies = [ + "displaydoc", + "potential_utf", + "yoke", + "zerofrom", + "zerovec", +] + +[[package]] +name = "icu_locale_core" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "edba7861004dd3714265b4db54a3c390e880ab658fec5f7db895fae2046b5bb6" +dependencies = [ + "displaydoc", + "litemap", + "tinystr", + "writeable", + "zerovec", +] + +[[package]] +name = "icu_normalizer" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f6c8828b67bf8908d82127b2054ea1b4427ff0230ee9141c54251934ab1b599" +dependencies = [ + "icu_collections", + "icu_normalizer_data", + "icu_properties", + "icu_provider", + "smallvec", + "zerovec", +] + +[[package]] +name = "icu_normalizer_data" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7aedcccd01fc5fe81e6b489c15b247b8b0690feb23304303a9e560f37efc560a" + +[[package]] +name = "icu_properties" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "020bfc02fe870ec3a66d93e677ccca0562506e5872c650f893269e08615d74ec" +dependencies = [ + "icu_collections", + "icu_locale_core", + "icu_properties_data", + "icu_provider", + "zerotrie", + "zerovec", +] + +[[package]] +name = "icu_properties_data" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "616c294cf8d725c6afcd8f55abc17c56464ef6211f9ed59cccffe534129c77af" + +[[package]] +name = "icu_provider" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "85962cf0ce02e1e0a629cc34e7ca3e373ce20dda4c4d7294bbd0bf1fdb59e614" +dependencies = [ + "displaydoc", + "icu_locale_core", + "writeable", + "yoke", + "zerofrom", + "zerotrie", + "zerovec", +] + +[[package]] +name = "idna" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b0875f23caa03898994f6ddc501886a45c7d3d62d04d2d90788d47be1b1e4de" +dependencies = [ + "idna_adapter", + "smallvec", + "utf8_iter", +] + +[[package]] +name = "idna_adapter" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3acae9609540aa318d1bc588455225fb2085b9ed0c4f6bd0d9d5bcd86f1a0344" +dependencies = [ + "icu_normalizer", + "icu_properties", +] + +[[package]] +name = "indexmap" +version = "2.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" +dependencies = [ + "equivalent", + "hashbrown", +] + +[[package]] +name = "ipnet" +version = "2.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6a756c3fac73139e83f14c2d742155dd2b78d3ee56597b419a0579b7bdd6dd78" + +[[package]] +name = "is_ci" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7655c9839580ee829dfacba1d1278c2b7883e50a277ff7541299489d6bdfdc45" + +[[package]] +name = "itoa" +version = "1.0.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" + +[[package]] +name = "jni" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5efd9a482cf3a427f00d6b35f14332adc7902ce91efb778580e180ff90fa3498" +dependencies = [ + "cfg-if", + "combine", + "jni-macros", + "jni-sys", + "log", + "simd_cesu8", + "thiserror", + "walkdir", + "windows-link", +] + +[[package]] +name = "jni-macros" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a00109accc170f0bdb141fed3e393c565b6f5e072365c3bd58f5b062591560a3" +dependencies = [ + "proc-macro2", + "quote", + "rustc_version", + "simd_cesu8", + "syn 2.0.119", +] + +[[package]] +name = "jni-sys" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6377a88cb3910bee9b0fa88d4f42e1d2da8e79915598f65fb0c7ee14c878af2" +dependencies = [ + "jni-sys-macros", +] + +[[package]] +name = "jni-sys-macros" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "38c0b942f458fe50cdac086d2f946512305e5631e720728f2a61aabcd47a6264" +dependencies = [ + "quote", + "syn 2.0.119", +] + +[[package]] +name = "jobserver" +version = "0.1.35" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1c00acbd29eabad4a2392fa0e921c874934dbbf4194312ad20f04a0ed67a3cb3" +dependencies = [ + "getrandom 0.4.3", + "libc", +] + +[[package]] +name = "js-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0e0c1080212aad755ea003d18543e8768dd432c48819efd73a7bf1e39b7a5a3a" +dependencies = [ + "cfg-if", + "futures-util", + "wasm-bindgen", +] + +[[package]] +name = "libc" +version = "0.2.189" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2" + +[[package]] +name = "lief" +version = "2.0.0" +dependencies = [ + "bitflags", + "cxx", + "lief-ffi", + "num-bigint", + "num-derive", + "num-traits", +] + +[[package]] +name = "lief-build" +version = "2.0.0" +dependencies = [ + "git-version", + "miette", + "reqwest", + "semver", + "zip", +] + +[[package]] +name = "lief-examples" +version = "0.0.0" +dependencies = [ + "lief", +] + +[[package]] +name = "lief-ffi" +version = "2.0.0" +dependencies = [ + "cxx", + "lief-build", + "miette", +] + +[[package]] +name = "link-cplusplus" +version = "1.0.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7f78c730aaa7d0b9336a299029ea49f9ee53b0ed06e9202e8cb7db9bae7b8c82" +dependencies = [ + "cc", +] + +[[package]] +name = "linux-raw-sys" +version = "0.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53" + +[[package]] +name = "litemap" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "47d9d19d1d6efa0109d2f65ff4c85cddd50bd572e5a00127ab10987290bcefae" + +[[package]] +name = "log" +version = "0.4.33" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ceec5bc11778974d1bcb055b18002eba7f4b3518b6a0081b3af5f21666da9ad" + +[[package]] +name = "lru-slab" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "112b39cec0b298b6c1999fee3e31427f74f676e4cb9879ed1a121b43661a4154" + +[[package]] +name = "memchr" +version = "2.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf8baf1c55e62ffcace7a9f06f4bd9cd3f0c4beb022d3b367256b91b87513d98" + +[[package]] +name = "miette" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f98efec8807c63c752b5bd61f862c165c115b0a35685bdcfd9238c7aeb592b7" +dependencies = [ + "backtrace", + "backtrace-ext", + "cfg-if", + "miette-derive", + "owo-colors", + "supports-color", + "supports-hyperlinks", + "supports-unicode", + "terminal_size", + "textwrap", + "unicode-width 0.1.14", +] + +[[package]] +name = "miette-derive" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db5b29714e950dbb20d5e6f74f9dcec4edbcc1067bb7f8ed198c097b8c1a818b" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "miniz_oxide" +version = "0.8.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316" +dependencies = [ + "adler2", + "simd-adler32", +] + +[[package]] +name = "mio" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "30d65c71f1ce40ab09135ce117d742b9f8a19ff91a41a8b57ed50bc2de59c427" +dependencies = [ + "libc", + "wasi", + "windows-sys 0.61.2", +] + +[[package]] +name = "num-bigint" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93e7820bc0a80a0238e650327316f929ba18d5be054b647490a3a6a339f3e7c0" +dependencies = [ + "num-integer", + "num-traits", +] + +[[package]] +name = "num-conv" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9" + +[[package]] +name = "num-derive" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e4e98dc3b890f6c23a0f9d3d491a2823d0dea0fa656302a13dd225fa924112a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "num-integer" +version = "0.1.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ce2d95d4b3734dc35aa2f45e1aa22cd416814592a4f9d9205e11affd5b8e10b" +dependencies = [ + "num-traits", +] + +[[package]] +name = "num-traits" +version = "0.2.19" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" +dependencies = [ + "autocfg", +] + +[[package]] +name = "object" +version = "0.37.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe" +dependencies = [ + "memchr", +] + +[[package]] +name = "once_cell" +version = "1.21.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" + +[[package]] +name = "openssl-probe" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7c87def4c32ab89d880effc9e097653c8da5d6ef28e6b539d313baaacfbafcbe" + +[[package]] +name = "owo-colors" +version = "4.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d211803b9b6b570f68772237e415a029d5a50c65d382910b879fb19d3271f94d" + +[[package]] +name = "percent-encoding" +version = "2.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220" + +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" + +[[package]] +name = "pkg-config" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f6b464fbc74e149a392436b17d523f769e057cb6877f6a5c4618bc6f11800548" + +[[package]] +name = "potential_utf" +version = "0.1.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d83eb9bc6d8e5cf568e7a1101d60ee05e81ed50ea106026f3d18deeb046d7661" +dependencies = [ + "zerovec", +] + +[[package]] +name = "powerfmt" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "439ee305def115ba05938db6eb1644ff94165c5ab5e9420d1c1bcedbba909391" + +[[package]] +name = "proc-macro2" +version = "1.0.107" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "985e7ec9bb745e6ce6535b544d84d6cd6f7ad8bd711c398938ae983b91a766d9" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "quinn" +version = "0.11.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c1a41e437b6bbd489372cd4971de128e85c855f56c57f283d20ff016cf7c0a8" +dependencies = [ + "bytes", + "cfg_aliases", + "pin-project-lite", + "quinn-proto", + "quinn-udp", + "rustc-hash", + "rustls", + "socket2", + "thiserror", + "tokio", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-proto" +version = "0.11.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "04759210543be93709136e28212294a659ef5001836ff4eab4d663e4529bba83" +dependencies = [ + "aws-lc-rs", + "bytes", + "getrandom 0.4.3", + "lru-slab", + "rand", + "rand_pcg", + "ring", + "rustc-hash", + "rustls", + "rustls-pki-types", + "slab", + "thiserror", + "tinyvec", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-udp" +version = "0.5.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "35a133f956daabe89a61a685c2649f13d82d5aa4bd5d12d1277e1072a21c0694" +dependencies = [ + "cfg_aliases", + "libc", + "once_cell", + "socket2", + "tracing", + "windows-sys 0.61.2", +] + +[[package]] +name = "quote" +version = "1.0.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fbf4db142a473a8d80c26bbf18454ed458bf8d26c8219c331daecfdbd079001" +dependencies = [ + "proc-macro2", +] + +[[package]] +name = "r-efi" +version = "6.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf" + +[[package]] +name = "rand" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c7f5fa3a058cd35567ef9bfa5e75732bee0f9e4c55fa90477bef2dfcdbc4be80" +dependencies = [ + "chacha20", + "getrandom 0.4.3", + "rand_core", +] + +[[package]] +name = "rand_core" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63b8176103e19a2643978565ca18b50549f6101881c443590420e4dc998a3c69" + +[[package]] +name = "rand_pcg" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "caa0f4137e1c0a72f4c651489402276c8e8e1cf081f3b0ba156d2cbeef09e86a" +dependencies = [ + "rand_core", +] + +[[package]] +name = "reqwest" +version = "0.13.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "219c5811de6525e5416c7d5d53bb656d3afdbc6c5af816e0802bcfa42dbdc1c3" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-core", + "futures-util", + "http", + "http-body", + "http-body-util", + "hyper", + "hyper-rustls", + "hyper-util", + "js-sys", + "log", + "percent-encoding", + "pin-project-lite", + "quinn", + "rustls", + "rustls-pki-types", + "rustls-platform-verifier", + "sync_wrapper", + "tokio", + "tokio-rustls", + "tower", + "tower-http", + "tower-service", + "url", + "wasm-bindgen", + "wasm-bindgen-futures", + "web-sys", +] + +[[package]] +name = "ring" +version = "0.17.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7" +dependencies = [ + "cc", + "cfg-if", + "getrandom 0.2.17", + "libc", + "untrusted", + "windows-sys 0.52.0", +] + +[[package]] +name = "rustc-demangle" +version = "0.1.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b74b56ffa8bb2830709a538c2cbcae9aa062db0d2a42563bfb09bdaae44020eb" + +[[package]] +name = "rustc-hash" +version = "2.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b1e7f9a428571be2dc5bc0505c13fb6bf936822b894ec87abf8a08a4e51742d" + +[[package]] +name = "rustc_version" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cfcb3a22ef46e85b45de6ee7e79d063319ebb6594faafcf1c225ea92ab6e9b92" +dependencies = [ + "semver", +] + +[[package]] +name = "rustix" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190" +dependencies = [ + "bitflags", + "errno", + "libc", + "linux-raw-sys", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls" +version = "0.23.43" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0283386ce02abc0151e1761d08802dfe86c173b0b494af5cbc086574e453da06" +dependencies = [ + "aws-lc-rs", + "once_cell", + "rustls-pki-types", + "rustls-webpki", + "subtle", + "zeroize", +] + +[[package]] +name = "rustls-native-certs" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dab5152771c58876a2146916e53e35057e1a4dfa2b9df0f0305b07f611fdea4d" +dependencies = [ + "openssl-probe", + "rustls-pki-types", + "schannel", + "security-framework", +] + +[[package]] +name = "rustls-pki-types" +version = "1.15.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2f4925028c7eb5d1fcdaf196971378ed9d2c1c4efc7dc5d011256f76c99c0a96" +dependencies = [ + "web-time", + "zeroize", +] + +[[package]] +name = "rustls-platform-verifier" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "26d1e2536ce4f35f4846aa13bff16bd0ff40157cdb14cc056c7b14ba41233ba0" +dependencies = [ + "core-foundation", + "core-foundation-sys", + "jni", + "log", + "once_cell", + "rustls", + "rustls-native-certs", + "rustls-platform-verifier-android", + "rustls-webpki", + "security-framework", + "security-framework-sys", + "webpki-root-certs", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls-platform-verifier-android" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f87165f0995f63a9fbeea62b64d10b4d9d8e78ec6d7d51fb2125fda7bb36788f" + +[[package]] +name = "rustls-webpki" +version = "0.103.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0527518605e68109d875e248ea259b6758801cf165e4b2c2733ae3b51f12535a" +dependencies = [ + "aws-lc-rs", + "ring", + "rustls-pki-types", + "untrusted", +] + +[[package]] +name = "rustversion" +version = "1.0.23" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf54715a573b99ac80df0bc206da022bcd442c974952c7b9720069370852e21f" + +[[package]] +name = "same-file" +version = "1.0.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "schannel" +version = "0.1.29" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "91c1b7e4904c873ef0710c1f407dde2e6287de2bebc1bbbf7d430bb7cbffd939" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "scratch" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d68f2ec51b097e4c1a75b681a8bec621909b5e91f15bb7b840c4f2f7b01148b2" + +[[package]] +name = "security-framework" +version = "3.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7f4bc775c73d9a02cde8bf7b2ec4c9d12743edf609006c7facc23998404cd1d" +dependencies = [ + "bitflags", + "core-foundation", + "core-foundation-sys", + "libc", + "security-framework-sys", +] + +[[package]] +name = "security-framework-sys" +version = "2.17.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2691df843ecc5d231c0b14ece2acc3efb62c0a398c7e1d875f3983ce020e3" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "semver" +version = "1.0.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd" + +[[package]] +name = "serde" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4148590afebada386688f18773da617792bf2ef03ffc1e4cbd2b1d45b023e0ba" +dependencies = [ + "serde_core", + "serde_derive", +] + +[[package]] +name = "serde_core" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67dca2c9c51e58a4791a4b1ed58308b39c64224d349a935ab5039aa360942a48" +dependencies = [ + "serde_derive", +] + +[[package]] +name = "serde_derive" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e7a5d71263a5a7d47b41f6b3f06ba276f10cc18b0931f1799f710578e2309348" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "shlex" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8fadd59c855ef2080decdef8ff161eb6661b86933c9d82e5ba29dc602a55aba" + +[[package]] +name = "simd-adler32" +version = "0.3.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3a219298ac11a56ea9a6d2120044824d6f01aeb034955e7af7bc16858527deea" + +[[package]] +name = "simd_cesu8" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11031e251abf8611c80f460e19dbdeb54a66db918e49c65a7065b46ac7aec520" +dependencies = [ + "rustc_version", + "simdutf8", +] + +[[package]] +name = "simdutf8" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3a9fe34e3e7a50316060351f37187a3f546bce95496156754b601a5fa71b76e" + +[[package]] +name = "slab" +version = "0.4.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5" + +[[package]] +name = "smallvec" +version = "1.15.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ed6a63f02c8539c91a8685a86f4099661ba3da017932f6ebbea6de3f0fa7c90" + +[[package]] +name = "socket2" +version = "0.6.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c3d1e2c7f27f8d4cb10542a02c49005dbd6e93095799d6f3be745fae9f8fedd4" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "stable_deref_trait" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596" + +[[package]] +name = "strsim" +version = "0.11.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" + +[[package]] +name = "subtle" +version = "2.6.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292" + +[[package]] +name = "supports-color" +version = "3.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c64fc7232dd8d2e4ac5ce4ef302b1d81e0b80d055b9d77c7c4f51f6aa4c867d6" +dependencies = [ + "is_ci", +] + +[[package]] +name = "supports-hyperlinks" +version = "3.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e396b6523b11ccb83120b115a0b7366de372751aa6edf19844dfb13a6af97e91" + +[[package]] +name = "supports-unicode" +version = "3.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7401a30af6cb5818bb64852270bb722533397edcfc7344954a38f420819ece2" + +[[package]] +name = "syn" +version = "2.0.119" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "872831b642d1a07999a962a351ed35b955ea2cfc8f3862091e2a240a84f17297" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "syn" +version = "3.0.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53e9bae58849f64dfa4f5d5ae372c8341f7305f82a3868709269343628b659a3" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "sync_wrapper" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0bf256ce5efdfa370213c1dabab5935a12e49f2c58d15e9eac2870d3b4f27263" +dependencies = [ + "futures-core", +] + +[[package]] +name = "synstructure" +version = "0.13.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "728a70f3dbaf5bab7f0c4b1ac8d7ae5ea60a4b5549c8a5914361c99147a709d2" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "termcolor" +version = "1.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "06794f8f6c5c898b3275aebefa6b8a1cb24cd2c6c79397ab15774837a0bc5755" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "terminal_size" +version = "0.4.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "230a1b821ccbd75b185820a1f1ff7b14d21da1e442e22c0863ea5f08771a8874" +dependencies = [ + "rustix", + "windows-sys 0.61.2", +] + +[[package]] +name = "textwrap" +version = "0.16.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c13547615a44dc9c452a8a534638acdf07120d4b6847c8178705da06306a3057" +dependencies = [ + "unicode-linebreak", + "unicode-width 0.2.2", +] + +[[package]] +name = "thiserror" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ec86235f5fcc2a73650310756d2ac5b138a5780bbbdfae3eeccec992c435ba4f" +dependencies = [ + "thiserror-impl", +] + +[[package]] +name = "thiserror-impl" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bc04cd3e1236dd4a98afca4569f2deb3f120e5422a4023be2cb683f8486292af" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "time" +version = "0.3.45" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f9e442fc33d7fdb45aa9bfeb312c095964abdf596f7567261062b2a7107aaabd" +dependencies = [ + "deranged", + "js-sys", + "num-conv", + "powerfmt", + "serde_core", + "time-core", +] + +[[package]] +name = "time-core" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b36ee98fd31ec7426d599183e8fe26932a8dc1fb76ddb6214d05493377d34ca" + +[[package]] +name = "tinystr" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1e27c91459209c2986af3dcf603a5a74a4368754ce37414f59acc971167f643" +dependencies = [ + "displaydoc", + "zerovec", +] + +[[package]] +name = "tinyvec" +version = "1.12.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb4ebadaa0af04fab11ae01eb5f9fdb5f9c5b875506e210e71c07873528baa7f" +dependencies = [ + "tinyvec_macros", +] + +[[package]] +name = "tinyvec_macros" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1f3ccbac311fea05f86f61904b462b55fb3df8837a366dfc601a0161d0532f20" + +[[package]] +name = "tokio" +version = "1.53.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "202caea871b69668250d242070849eb495be178ed697a3e98aebce5bc81a0bed" +dependencies = [ + "bytes", + "libc", + "mio", + "pin-project-lite", + "socket2", + "windows-sys 0.61.2", +] + +[[package]] +name = "tokio-rustls" +version = "0.26.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1729aa945f29d91ba541258c8df89027d5792d85a8841fb65e8bf0f4ede4ef61" +dependencies = [ + "rustls", + "tokio", +] + +[[package]] +name = "tower" +version = "0.5.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ebe5ef63511595f1344e2d5cfa636d973292adc0eec1f0ad45fae9f0851ab1d4" +dependencies = [ + "futures-core", + "futures-util", + "pin-project-lite", + "sync_wrapper", + "tokio", + "tower-layer", + "tower-service", +] + +[[package]] +name = "tower-http" +version = "0.6.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4cfcf7e2740e6fc6d4d688b4ef00650406bb94adf4731e43c096c3a19fe40840" +dependencies = [ + "bitflags", + "bytes", + "futures-util", + "http", + "http-body", + "pin-project-lite", + "tower", + "tower-layer", + "tower-service", + "url", +] + +[[package]] +name = "tower-layer" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "121c2a6cda46980bb0fcd1647ffaf6cd3fc79a013de288782836f6df9c48780e" + +[[package]] +name = "tower-service" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8df9b6e13f2d32c91b9bd719c00d1958837bc7dec474d94952798cc8e69eeec3" + +[[package]] +name = "tracing" +version = "0.1.44" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63e71662fa4b2a2c3a26f570f037eb95bb1f85397f3cd8076caed2f026a6d100" +dependencies = [ + "pin-project-lite", + "tracing-core", +] + +[[package]] +name = "tracing-core" +version = "0.1.36" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db97caf9d906fbde555dd62fa95ddba9eecfd14cb388e4f491a66d74cd5fb79a" +dependencies = [ + "once_cell", +] + +[[package]] +name = "try-lock" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e421abadd41a4225275504ea4d6566923418b7f05506fbc9c0fe86ba7396114b" + +[[package]] +name = "typed-path" +version = "0.12.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e28f89b80c87b8fb0cf04ab448d5dd0dd0ade2f8891bae878de66a75a28600e" + +[[package]] +name = "unicode-ident" +version = "1.0.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" + +[[package]] +name = "unicode-linebreak" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b09c83c3c29d37506a3e260c08c03743a6bb66a9cd432c6934ab501a190571f" + +[[package]] +name = "unicode-width" +version = "0.1.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af" + +[[package]] +name = "unicode-width" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b4ac048d71ede7ee76d585517add45da530660ef4390e49b098733c6e897f254" + +[[package]] +name = "untrusted" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1" + +[[package]] +name = "url" +version = "2.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff67a8a4397373c3ef660812acab3268222035010ab8680ec4215f38ba3d0eed" +dependencies = [ + "form_urlencoded", + "idna", + "percent-encoding", + "serde", +] + +[[package]] +name = "utf8_iter" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be" + +[[package]] +name = "walkdir" +version = "2.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "29790946404f91d9c5d06f9874efddea1dc06c5efe94541a7d6863108e3a5e4b" +dependencies = [ + "same-file", + "winapi-util", +] + +[[package]] +name = "want" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bfa7760aed19e106de2c7c0b581b509f2f25d3dacaf737cb82ac61bc6d760b0e" +dependencies = [ + "try-lock", +] + +[[package]] +name = "wasi" +version = "0.11.1+wasi-snapshot-preview1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" + +[[package]] +name = "wasm-bindgen" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b70935747edd64d89de3efa29d73789b806c15798f8e7dca4d8ac356b50ce70" +dependencies = [ + "cfg-if", + "once_cell", + "rustversion", + "wasm-bindgen-macro", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-futures" +version = "0.4.77" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b7777d5cc23d0e91404e53ce2d5e8ec7acae3026b16233dba62cd3246457950" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "wasm-bindgen-macro" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77775f8f3f7217702089053b94958f8f54061a3f663417df76e19cbdcca29bc1" +dependencies = [ + "quote", + "wasm-bindgen-macro-support", +] + +[[package]] +name = "wasm-bindgen-macro-support" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e11d33f857dc2fb11b8bc75aee111aa9cbeb12cd9f25efd3d4c2a3dd4e235284" +dependencies = [ + "bumpalo", + "proc-macro2", + "quote", + "syn 2.0.119", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-shared" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ef64dbcc55df09c7e5a46182d181c2cfa3e925f3da937ea764728b4bbb9dcbf" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "web-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c435338968042f4f59a557f690a253676d47ce13ceb55d70100e7facf6620a30" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "web-time" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5a6580f308b1fad9207618087a65c04e7a10bc77e02c8e84e9b00dd4b12fa0bb" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "webpki-root-certs" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b96554aa2acc8ccdb7e1c9a58a7a68dd5d13bccc69cd124cb09406db612a1c9b" +dependencies = [ + "rustls-pki-types", +] + +[[package]] +name = "winapi-util" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "windows-link" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" + +[[package]] +name = "windows-sys" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" +dependencies = [ + "windows-targets", +] + +[[package]] +name = "windows-sys" +version = "0.61.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc" +dependencies = [ + "windows-link", +] + +[[package]] +name = "windows-targets" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" +dependencies = [ + "windows_aarch64_gnullvm", + "windows_aarch64_msvc", + "windows_i686_gnu", + "windows_i686_gnullvm", + "windows_i686_msvc", + "windows_x86_64_gnu", + "windows_x86_64_gnullvm", + "windows_x86_64_msvc", +] + +[[package]] +name = "windows_aarch64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" + +[[package]] +name = "windows_aarch64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" + +[[package]] +name = "windows_i686_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" + +[[package]] +name = "windows_i686_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" + +[[package]] +name = "windows_i686_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66" + +[[package]] +name = "windows_x86_64_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78" + +[[package]] +name = "windows_x86_64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" + +[[package]] +name = "writeable" +version = "0.6.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ad82d2a33cdc9674dc7465672f271e096168fcdbe0f799d9e6db8c5892679dc" + +[[package]] +name = "yoke" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "709fe23a0424b6a435d82152b1bd3fdfb0833487d5fa90d05d42762a9891fef5" +dependencies = [ + "stable_deref_trait", + "yoke-derive", + "zerofrom", +] + +[[package]] +name = "yoke-derive" +version = "0.8.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "de844c262c8848816172cef550288e7dc6c7b7814b4ee56b3e1553f275f1858e" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zerofrom" +version = "0.1.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ec05a11813ea801ff6d75110ad09cd0824ddba17dfe17128ea0d5f68e6c5272" +dependencies = [ + "zerofrom-derive", +] + +[[package]] +name = "zerofrom-derive" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11532158c46691caf0f2593ea8358fed6bbf68a0315e80aae9bd41fbade684a1" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zeroize" +version = "1.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e13c156562582aa81c60cb29407084cdb54c4164760106ab78e6c5b0858cf64e" + +[[package]] +name = "zerotrie" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4ea269c3bd32f0a32c321907a2ae912ba6f4649bb0fc764a15627e99a7095a3f" +dependencies = [ + "displaydoc", + "yoke", + "zerofrom", +] + +[[package]] +name = "zerovec" +version = "0.11.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb0464e17806c1d976d5cba29399c7f08e516e279e2ba493f63123b5fca67dd8" +dependencies = [ + "yoke", + "zerofrom", + "zerovec-derive", +] + +[[package]] +name = "zerovec-derive" +version = "0.11.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f212a141d820099d57ffafb9569be9617a6f27d3dc881fbee8fb56642f917a9" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "zip" +version = "7.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c42e33efc22a0650c311c2ef19115ce232583abbe80850bc8b66509ebef02de0" +dependencies = [ + "crc32fast", + "flate2", + "indexmap", + "memchr", + "time", + "typed-path", + "zopfli", +] + +[[package]] +name = "zlib-rs" +version = "0.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "34b31d188d9d685a4f9c7b46d6e36631b07058d2cfe190267adce54dc230bf12" + +[[package]] +name = "zopfli" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f05cd8797d63865425ff89b5c4a48804f35ba0ce8d125800027ad6017d2b5249" +dependencies = [ + "bumpalo", + "crc32fast", + "log", + "simd-adler32", +] diff --git a/vendor/lief/api/rust/examples/Cargo.toml b/vendor/lief/api/rust/examples/Cargo.toml new file mode 100644 index 0000000..b3a5f94 --- /dev/null +++ b/vendor/lief/api/rust/examples/Cargo.toml @@ -0,0 +1,60 @@ +[package] +name = "lief-examples" +version = "0.0.0" +edition = "2024" + +rust-version = "1.85.0" + +[dependencies] +lief = { path = "../crates/lief" } + +[[bin]] +name = "reader" + +[[bin]] +name = "pe_check_authenticode" + +[[bin]] +name = "pe_rich_header" + +[[bin]] +name = "elf_deps" + +[[bin]] +name = "pe_deps" + +[[bin]] +name = "list_macho_encryption" + +[[bin]] +name = "dwarf_inspect" + +[[bin]] +name = "dwarf_editor" + +[[bin]] +name = "pdb_inspect" + +[[bin]] +name = "objc_inspect" + +[[bin]] +name = "disassembler" + +[[bin]] +name = "pe_exceptions" + +[[bin]] +name = "runtime_linux" + +[[bin]] +name = "runtime_windows" + +[[bin]] +name = "runtime_osx" + +[[bin]] +name = "runtime_android" + +[[bin]] +name = "test_run_examples" diff --git a/vendor/lief/api/rust/examples/src/bin/disassembler.rs b/vendor/lief/api/rust/examples/src/bin/disassembler.rs new file mode 100644 index 0000000..7cf3858 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/disassembler.rs @@ -0,0 +1,54 @@ +/// This example shows how to disassemble an ELF/PE/Mach-O binary using LIEF's extended API +use lief::assembly::Instruction; +use std::process::ExitCode; + +fn disassemble(target: &dyn lief::generic::Binary, address: u64) -> ExitCode { + for inst in target.disassemble_address(address) { + println!("{inst}"); + } + ExitCode::SUCCESS +} + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF"); + return ExitCode::FAILURE; + } + + let args = Vec::from_iter(std::env::args()); + if args.len() != 3 { + println!("Usage: {}
", args[0]); + // Disassemble the disassemble() itself + for inst in lief::runtime::disassemble((disassemble as usize).try_into().unwrap()) { + println!("{inst}"); + if inst.is_return() { + break; + } + } + return ExitCode::FAILURE; + } + + let path = &args[1]; + let addr_str = &args[2]; + + let addr = { + if addr_str.starts_with("0x") { + u64::from_str_radix(addr_str.trim_start_matches("0x"), 16).unwrap() + } else { + addr_str.parse::().unwrap() + } + }; + + let bin = lief::Binary::parse(path).expect("Can't parse the binary"); + match bin { + lief::Binary::ELF(elf) => disassemble(&elf, addr), + + lief::Binary::PE(pe) => disassemble(&pe, addr), + + lief::Binary::MachO(fat) => { + let fit = fat.iter().next().unwrap(); + disassemble(&fit, addr) + } + lief::Binary::COFF(_) => ExitCode::SUCCESS, + } +} diff --git a/vendor/lief/api/rust/examples/src/bin/dwarf_editor.rs b/vendor/lief/api/rust/examples/src/bin/dwarf_editor.rs new file mode 100644 index 0000000..50a2818 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/dwarf_editor.rs @@ -0,0 +1,32 @@ +use lief::dwarf::editor::types::EditorType; +/// This example shows how to create a DWARF file by using LIEF's API +use std::process::ExitCode; + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF") + } + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + + let mut bin = lief::pe::Binary::parse(&path).unwrap(); + let mut editor = lief::dwarf::Editor::from_binary(&mut bin).unwrap(); + + let mut unit = editor.create_compile_unit().unwrap(); + unit.set_producer("LIEF"); + + let mut func = unit.create_function("hello").unwrap(); + func.set_address(0x123); + func.set_return_type(&unit.create_structure("my_struct_t").pointer_to()); + + let mut var = func.create_stack_variable("local_var"); + var.set_stack_offset(8); + + editor.write("/tmp/out.debug"); + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/dwarf_inspect.rs b/vendor/lief/api/rust/examples/src/bin/dwarf_inspect.rs new file mode 100644 index 0000000..b85367f --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/dwarf_inspect.rs @@ -0,0 +1,59 @@ +use lief::dwarf::types::DwarfType; +/// This example shows how to inspect a DWARF debug info using LIEF's API +use std::process::{self, ExitCode}; + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF") + } + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + + let dbg = lief::dwarf::load(&path).unwrap_or_else(|| { + process::exit(1); + }); + + for cu in dbg.compilation_units() { + println!("Producer: {}", cu.producer()); + for func in cu.functions() { + println!( + "name={}, linkage={}, address={}", + func.name(), + func.linkage_name(), + func.address().unwrap_or(0) + ); + } + + for var in cu.variables() { + println!( + "name={}, address={}", + var.name(), + var.address().unwrap_or(0) + ); + } + + for ty in cu.types() { + println!( + "name={}, size={}", + ty.name().unwrap_or("".to_string()), + ty.size().unwrap_or(0) + ); + } + } + + dbg.function_by_name("_ZNSi4peekEv"); + dbg.function_by_name("std::basic_istream >::peek()"); + dbg.function_by_addr(0x137a70); + + dbg.variable_by_name("_ZNSt12out_of_rangeC1EPKc"); + dbg.variable_by_name("std::out_of_range::out_of_range(char const*)"); + dbg.variable_by_addr(0x137a70); + + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/dyld_shared_cache_reader.rs b/vendor/lief/api/rust/examples/src/bin/dyld_shared_cache_reader.rs new file mode 100644 index 0000000..03978e3 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/dyld_shared_cache_reader.rs @@ -0,0 +1,34 @@ +/// This example shows how to inspect a dyld shared cache with LIEF using the Rust API +use std::process::{self, ExitCode}; + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF") + } + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + + let cache = lief::dsc::load_from_path(&path.as_str(), "").unwrap_or_else(|| { + process::exit(1); + }); + + for dylib in cache.libraries() { + println!("0x{:016x} {}", dylib.address(), dylib.path()); + } + + for minfo in cache.mapping_info() { + println!( + "[0x{:016x}, 0x{:016x}]: 0x{:016x}", + minfo.address(), + minfo.end_address(), + minfo.file_offset() + ) + } + + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/elf_deps.rs b/vendor/lief/api/rust/examples/src/bin/elf_deps.rs new file mode 100644 index 0000000..fae54ff --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/elf_deps.rs @@ -0,0 +1,34 @@ +use lief::elf::dynamic; +/// This example lists all the dependencies of an ELF file as well as the required symbol +/// versions. This can be used to assess if an ELF executable can run on a given Linux distribution +use std::process::ExitCode; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(&path).expect("Can't open the file"); + if let Some(lief::Binary::ELF(elf)) = lief::Binary::from(&mut file) { + println!("Dependencies:"); + for entry in elf.dynamic_entries() { + if let dynamic::Entries::Library(lib) = entry { + println!(" - {}", lib.name()); + } + } + println!("Versions:"); + for version in elf.symbols_version_requirement() { + println!(" From {}", version.name()); + for aux in version.auxiliary_symbols() { + println!(" - {}", aux.name()); + } + } + + return ExitCode::SUCCESS; + } + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/list_macho_encryption.rs b/vendor/lief/api/rust/examples/src/bin/list_macho_encryption.rs new file mode 100644 index 0000000..7238bfa --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/list_macho_encryption.rs @@ -0,0 +1,29 @@ +use std::process::ExitCode; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(&path).expect("Can't open the file"); + if let Some(lief::Binary::MachO(fat)) = lief::Binary::from(&mut file) { + for macho in fat.iter() { + for cmd in macho.commands() { + if let lief::macho::Commands::EncryptionInfo(info) = cmd { + println!( + "Encrypted area: 0x{:08x} - 0x{:08x} (id: {})", + info.crypt_offset(), + info.crypt_offset() + info.crypt_size(), + info.crypt_id() + ) + } + } + } + return ExitCode::SUCCESS; + } + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/objc_inspect.rs b/vendor/lief/api/rust/examples/src/bin/objc_inspect.rs new file mode 100644 index 0000000..083e9b8 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/objc_inspect.rs @@ -0,0 +1,35 @@ +/// This example shows how to inspect a Objective-C info using LIEF's API +use std::process::{self, ExitCode}; + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF") + } + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + + let Some(lief::Binary::MachO(fat)) = lief::Binary::parse(&path) else { + process::exit(1); + }; + let Some(bin) = fat.iter().next() else { + process::exit(1); + }; + let Some(metadata) = bin.objc_metadata() else { + process::exit(1); + }; + + for class in metadata.classes() { + println!("name={}", class.name()); + for method in class.methods() { + println!(" method.name={}", method.name()); + } + } + println!("{}", metadata.to_decl()); + + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/pdb_inspect.rs b/vendor/lief/api/rust/examples/src/bin/pdb_inspect.rs new file mode 100644 index 0000000..b4406bd --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/pdb_inspect.rs @@ -0,0 +1,55 @@ +use lief::pdb::types::PdbType; +/// This example shows how to inspect a PDB file using LIEF's API +use std::process::{self, ExitCode}; + +fn main() -> ExitCode { + if !lief::is_extended() { + println!("This example requires the extended version of LIEF") + } + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let pdb = lief::pdb::load(&path).unwrap_or_else(|| { + process::exit(1); + }); + println!("age={}, guid={}", pdb.age(), pdb.guid()); + + for symbol in pdb.public_symbols() { + println!( + "name={}, section={}, RVA={}", + symbol.name(), + symbol.section_name().unwrap_or("".to_string()), + symbol.rva() + ); + } + + for ty in pdb.types() { + if let lief::pdb::Type::Class(clazz) = ty { + println!("Class[name]={}", clazz.name().unwrap()); + } + } + + for cu in pdb.compilation_units() { + println!("module={}", cu.module_name()); + for src in cu.sources() { + println!(" - {}", src); + } + + for func in cu.functions() { + println!( + "name={}, section={}, RVA={}, code_size={}", + func.name(), + func.section_name(), + func.rva(), + func.code_size() + ); + } + } + + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/pe_check_authenticode.rs b/vendor/lief/api/rust/examples/src/bin/pe_check_authenticode.rs new file mode 100644 index 0000000..cac105c --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/pe_check_authenticode.rs @@ -0,0 +1,25 @@ +//! A simple example of validating PE authenticode signature in Rust + +use lief::pe; +use std::process::ExitCode; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(path).expect("Can't open the file"); + if let Some(lief::Binary::PE(pe)) = lief::Binary::from(&mut file) { + let result = pe.verify_signature(pe::signature::VerificationChecks::DEFAULT); + if result.is_ok() { + println!("Valid signature!"); + } else { + println!("Signature not valid: {}", result); + } + return ExitCode::SUCCESS; + } + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/pe_deps.rs b/vendor/lief/api/rust/examples/src/bin/pe_deps.rs new file mode 100644 index 0000000..a29917f --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/pe_deps.rs @@ -0,0 +1,44 @@ +//! This example prints the `.dll` needed by a PE including whether it's using +//! ordinal-based imports. + +use std::process::ExitCode; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(&path).expect("Can't open the file"); + if let Some(lief::Binary::PE(pe)) = lief::Binary::from(&mut file) { + println!("Imports:"); + for imp in pe.imports() { + let by_ordinal = imp.entries().any(|e| e.is_ordinal()); + let nb_entries = imp.entries().len(); + println!( + " - {} [#imports: {}, by ordinal: {}]", + imp.name(), + nb_entries, + by_ordinal + ); + } + + println!("Delay Imports:"); + for imp in pe.delay_imports() { + let by_ordinal = imp.entries().any(|e| e.is_ordinal()); + let nb_entries = imp.entries().len(); + println!( + " - {} [#imports: {}, by ordinal: {}]", + imp.name(), + nb_entries, + by_ordinal + ); + } + + return ExitCode::SUCCESS; + } + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/pe_exceptions.rs b/vendor/lief/api/rust/examples/src/bin/pe_exceptions.rs new file mode 100644 index 0000000..83e193b --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/pe_exceptions.rs @@ -0,0 +1,37 @@ +//! This examples iterates over the PE exceptions entries and pretty print their content + +use std::process::ExitCode; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(&path).expect("Can't open the file"); + if let Some(lief::Binary::PE(pe)) = lief::Binary::from(&mut file) { + let entries = pe.exceptions(); + if entries.len() == 0 { + println!("No entry"); + return ExitCode::SUCCESS; + } + + for entry in entries { + match entry { + lief::pe::RuntimeExceptionFunction::X86_64(rfunc) => { + println!("x86-64 Entry: {}", &rfunc as &dyn lief::pe::ExceptionInfo); + } + + lief::pe::RuntimeExceptionFunction::AArch64(rfunc) => { + println!("AArch64 Entry: {}", &rfunc as &dyn lief::pe::ExceptionInfo); + } + } + } + + return ExitCode::SUCCESS; + } + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/pe_rich_header.rs b/vendor/lief/api/rust/examples/src/bin/pe_rich_header.rs new file mode 100644 index 0000000..f5fb13b --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/pe_rich_header.rs @@ -0,0 +1,33 @@ +/// Print the different entries of the PE's rich header +use std::process::{self, ExitCode}; + +fn main() -> ExitCode { + let mut args = std::env::args(); + if args.len() != 2 { + println!("Usage: {} ", args.next().unwrap()); + return ExitCode::FAILURE; + } + + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(&path).expect("Can't open the file"); + if let Some(lief::Binary::PE(pe)) = lief::Binary::from(&mut file) { + let rich_header = pe.rich_header().unwrap_or_else(|| { + println!("Rich header not found!"); + process::exit(0); + }); + + println!("Rich header key: 0x{:x}", rich_header.key()); + for entry in rich_header.entries() { + println!( + "id: 0x{:04x} build_id: 0x{:04x} count: #{}", + entry.id(), + entry.build_id(), + entry.count() + ); + } + + return ExitCode::SUCCESS; + } + println!("Can't process {}", path); + ExitCode::FAILURE +} diff --git a/vendor/lief/api/rust/examples/src/bin/reader.rs b/vendor/lief/api/rust/examples/src/bin/reader.rs new file mode 100644 index 0000000..eab6631 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/reader.rs @@ -0,0 +1,34 @@ +use lief::Binary; +use lief::generic; + +use lief::elf; + +fn explore_elf(elf: &elf::Binary) { + let foo = elf as &dyn generic::Binary; + println!("{}", foo.entrypoint()); + for section in elf.sections() { + println!("{:?}", section); + } + for segment in elf.segments() { + println!("{:?}", segment); + } + for note in elf.notes() { + println!("{:?}", note); + } + for symbol in elf.dynamic_symbols() { + println!("{:?}", symbol); + } +} + +fn main() { + let path = std::env::args().last().unwrap(); + let mut file = std::fs::File::open(path).expect("Can't open the file"); + match Binary::from(&mut file) { + Some(Binary::ELF(elf)) => { + explore_elf(&elf); + } + Some(Binary::PE(_)) => {} + _ => {} + } + return; +} diff --git a/vendor/lief/api/rust/examples/src/bin/runtime_android.rs b/vendor/lief/api/rust/examples/src/bin/runtime_android.rs new file mode 100644 index 0000000..af84b22 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/runtime_android.rs @@ -0,0 +1,239 @@ +use std::process::ExitCode; +use std::sync::Arc; + +use lief::assembly::AssemblerConfig; +use lief::generic::Symbol; +use lief::runtime; +use lief::runtime::memory::{MmapFlags, Perm}; +use lief::runtime::module::Module; + +fn host_info() { + println!("Host"); + // lief-doc: host-start + println!(" Hostname: {}", runtime::Host::name()); + println!(" Home: {}", runtime::Host::home_dir()); + println!(" Cache: {}", runtime::Host::cache_dir()); + println!(" Temp: {}", runtime::Host::tmp_dir()); + println!(" Config: {}", runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-android-start + if let Some(sdk) = runtime::android::Host::sdk_version() { + println!(" SDK: {}", sdk); + } + // lief-doc: host-android-end +} + +fn process_info() { + println!("Process"); + // lief-doc: process-start + println!(" PID: {}", runtime::Process::pid()); + println!(" TID: {}", runtime::Process::tid()); + println!(" Page size: {:#06x}", runtime::Process::page_size()); + println!(" Arch: {:?}", runtime::Process::arch()); + println!(" Platform: {:?}", runtime::Process::platform()); + // lief-doc: process-end + + // lief-doc: process-android-start + // Query a single system property by name + if let Some(prop) = runtime::android::Process::get_system_property("ro.build.version.sdk") { + println!( + " {}: {} (serial: {})", + prop.name(), + prop.value(), + prop.serial() + ); + } + + // Iterate over all properties + for prop in runtime::android::Process::properties() { + println!( + " {}: {} (serial: {})", + prop.name(), + prop.value(), + prop.serial() + ); + } + // lief-doc: process-android-end +} + +fn modules_info() { + println!("Module API"); + let mut libc: Option = None; + // lief-doc: modules-start + for module in runtime::modules() { + println!( + "{} ({:#010x} - {:#010x})", + module.name(), + module.imagebase(), + module.end() + ); + if let runtime::Modules::Android(android_mod) = module { + if android_mod.name().ends_with("libc.so") { + println!( + "libc.so found: {} ([{:#010x}, {:#010x}])", + android_mod.path(), + android_mod.imagebase(), + android_mod.end() + ); + libc = Some(android_mod); + } + } + } + // lief-doc: modules-end + + let libc = match libc { + Some(lib) => lib, + None => return, + }; + + // lief-doc: modules-android-start + println!("libc path: {}", libc.path()); + let cxa_finalize = libc.dlsym("__cxa_finalize".to_string()); + if !cxa_finalize.is_null() { + println!( + "{}!__cxa_finalize: {:#010x}", + libc.name(), + cxa_finalize as usize + ); + } + + let malloc = libc.dlsym("malloc".to_string()); + if !malloc.is_null() { + println!("{}!malloc: {:#010x}", libc.name(), malloc as usize); + } + + // Parse the ELF from its path on the disk + if let Some(elf_on_disk) = libc.parse_from_path() { + for sym in elf_on_disk.dynamic_symbols() { + if sym.name() == "__cxa_finalize" { + println!("__cxa_finalize: {:#010x}", sym.value()); + break; + } + } + } + + if let Some(liblog) = runtime::android::dlopen("liblog.so") { + println!( + "liblog loaded: {} (dlopen handle={:#010x})", + liblog.path(), + liblog.handle() as usize + ); + + let log_print = liblog.dlsym("__android_log_print".to_string()); + if !log_print.is_null() { + println!( + "{}!__android_log_print: {:#010x}", + liblog.name(), + log_print as usize + ); + } + } + // lief-doc: modules-android-end +} + +fn memory_example() { + println!("Memory"); + // lief-doc: memory-start + let mut chunk = match runtime::Memory::mmap( + runtime::Process::page_size() as u64, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ | Perm::WRITE | Perm::EXEC, + ) { + Some(c) => c, + None => return, + }; + + let mut config = AssemblerConfig::default(); + config.symbol_resolver = Some(Arc::new(|name: &str| -> Option { + let libc = match runtime::android::dlopen("libc.so") { + Some(lib) => lib, + None => { + eprintln!("Failed to dlopen libc.so"); + return None; + } + }; + + if name == "write" { + return Some(libc.dlsym("write".to_string()) as usize as u64); + } + None + })); + + let raw_inst = runtime::assemble_with_config( + chunk.addr(), + r#" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + ldr x8, =write + + mov x0, 1 // STDOUT_FILENO + adr x1, msg // buf = &msg + mov x2, 27 // len("LIEF Runtime Extended Demo\n") + blr x8 // write(STDOUT_FILENO, msg, 27) + + ldp x29, x30, [sp], 16 + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + "#, + &config, + ); + + // Disassemble the JITed stub from memory + for inst in runtime::disassemble(chunk.addr()).take(9) { + println!("{}", inst); + } + + // Dump the JITed stub as raw bytes + let hex_bytes: Vec = raw_inst.iter().map(|&b| format!("{:02x}", b)).collect(); + println!("{}", hex_bytes.join(":")); + + // Flush the instruction cache before executing the freshly written code + // (this is required on AArch64). + chunk.cache_flush(); + + // Change the permission to R-X and invoke the JITed function + chunk.make_rx(); + + let hello_jit: unsafe extern "C" fn() = unsafe { std::mem::transmute(chunk.addr() as usize) }; + unsafe { hello_jit() }; + + // Change the message: locate it in the generated bytes and rewrite it. + let needle = b"LIEF Runtime"; + if let Some(msg_off) = raw_inst.windows(needle.len()).position(|w| w == needle) { + let new_msg = b"Hello Rust runtime World!\n"; + chunk.make_rw(); + unsafe { + let dst = (chunk.addr() as usize + msg_off) as *mut u8; + std::ptr::copy_nonoverlapping(new_msg.as_ptr(), dst, new_msg.len()); + } + chunk.make_rx(); + chunk.cache_flush(); + unsafe { hello_jit() }; + } + + // Don't miss good practices! + let _ = chunk.deallocate(); + // lief-doc: memory-end +} + +fn main() -> ExitCode { + if !runtime::enabled() { + eprintln!("Error: LIEF's runtime is not enabled"); + return ExitCode::SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/runtime_linux.rs b/vendor/lief/api/rust/examples/src/bin/runtime_linux.rs new file mode 100644 index 0000000..af384d4 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/runtime_linux.rs @@ -0,0 +1,210 @@ +use std::process::ExitCode; + +use lief::generic::{Relocation, Symbol}; +use lief::runtime; +use lief::runtime::memory::{MmapFlags, Perm}; +use lief::runtime::module::Module; + +fn host_info() { + println!("Host"); + // lief-doc: host-start + println!(" Hostname: {}", runtime::Host::name()); + println!(" Home: {}", runtime::Host::home_dir()); + println!(" Cache: {}", runtime::Host::cache_dir()); + println!(" Temp: {}", runtime::Host::tmp_dir()); + println!(" Config: {}", runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-linux-start + println!(" sys_name: {}", runtime::linux::Host::sys_name()); + println!(" sys_release: {}", runtime::linux::Host::sys_release()); + println!(" sys_version: {}", runtime::linux::Host::sys_version()); + println!(" hardware: {}", runtime::linux::Host::hardware()); + // lief-doc: host-linux-end +} + +fn process_info() { + println!("Process"); + // lief-doc: process-start + println!(" PID: {}", runtime::Process::pid()); + println!(" TID: {}", runtime::Process::tid()); + println!(" Page size: {:#06x}", runtime::Process::page_size()); + println!(" Arch: {:?}", runtime::Process::arch()); + println!(" Platform: {:?}", runtime::Process::platform()); + // lief-doc: process-end + + // lief-doc: process-linux-start + if let Some(version) = runtime::linux::Process::glibc_version() { + println!(" glibc: {}", version); + } + // lief-doc: process-linux-end +} + +fn modules_info() { + println!("Module API"); + let mut libc: Option = None; + // lief-doc: modules-start + for module in runtime::modules() { + println!( + "{} ({:#010x} - {:#010x})", + module.name(), + module.imagebase(), + module.end() + ); + if let runtime::Modules::Linux(linux_mod) = module { + if linux_mod.name().starts_with("libc.so") { + println!( + "libc.so found: {} ([{:#010x}, {:#010x}])", + linux_mod.path(), + linux_mod.imagebase(), + linux_mod.end() + ); + libc = Some(linux_mod); + } + } + } + // lief-doc: modules-end + + let libc = match libc { + Some(lib) => lib, + None => return, + }; + + // lief-doc: modules-linux-start + println!("libc path: {}", libc.path()); + let cxa_finalize = libc.dlsym("__cxa_finalize".to_string()); + if !cxa_finalize.is_null() { + println!( + "{}!__cxa_finalize: {:#010x}", + libc.name(), + cxa_finalize as usize + ); + } + + let malloc = libc.dlsym("malloc".to_string()); + if !malloc.is_null() { + println!("{}!malloc: {:#010x}", libc.name(), malloc as usize); + } + + // Parse the ELF from its path on the disk + if let Some(elf_on_disk) = libc.parse_from_path() { + for sym in elf_on_disk.dynamic_symbols() { + if sym.name() == "__cxa_finalize" { + println!("__cxa_finalize: {:#010x}", sym.value()); + break; + } + } + } + + // Load 'librt.so' and wrap the dlopen handle in a Module. + if let Some(librt) = runtime::linux::dlopen("librt.so.1") { + println!( + "librt loaded: {} (dlopen handle={:#010x})", + librt.path(), + librt.handle() as usize + ); + + // Parse the ELF directly from memory. + if let Some(librt_mem) = librt.parse_from_memory() { + // Find the relocation for the imported symbol `__cxa_finalize` + // defined in libc. Reading the relocation address returns the + // resolved address, which should match what dlsym returned. + for reloc in librt_mem.relocations() { + let sym = match reloc.symbol() { + Some(s) => s, + None => continue, + }; + if sym.name() != "__cxa_finalize" { + continue; + } + let abs_reloc_addr = librt.imagebase() + reloc.address(); + // Assume a 64-bit architecture + let resolved: u64 = unsafe { runtime::Memory::read(abs_reloc_addr) }; + println!( + "{} -> {:#010x} -> {:#010x}", + librt.name(), + abs_reloc_addr, + resolved + ); + break; + } + } + } + // lief-doc: modules-linux-end +} + +fn memory_example() { + println!("Memory"); + // lief-doc: memory-start + let mut chunk = match runtime::Memory::mmap( + runtime::Process::page_size() as u64, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ | Perm::WRITE | Perm::EXEC, + ) { + Some(c) => c, + None => return, + }; + + let raw_inst = runtime::assemble( + chunk.addr(), + r#" + .global _start + + .text + _start: + push 1 + pop rax + mov edi, eax + lea rsi, [rip + msg] + mov rdx, 28 + syscall + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + "#, + ); + + // Dump the generated instruction bytes + println!( + "{} bytes assembled at {:#010x}", + raw_inst.len(), + chunk.addr() + ); + + // Change the permission to R-X and invoke the JITed function + chunk.make_rx(); + + let hello_jit: unsafe extern "C" fn() = unsafe { std::mem::transmute(chunk.addr() as usize) }; + unsafe { hello_jit() }; + + // Locate the message in the generated bytes and rewrite it. + let needle = b"LIEF Runtime"; + if let Some(msg_off) = raw_inst.windows(needle.len()).position(|w| w == needle) { + let new_msg = b"Hello Rust runtime World!\n\0"; + chunk.make_rw(); + unsafe { + let dst = (chunk.addr() as usize + msg_off) as *mut u8; + std::ptr::copy_nonoverlapping(new_msg.as_ptr(), dst, new_msg.len() - 1); + } + chunk.make_rx(); + unsafe { hello_jit() }; + } + + // Don't miss good practices! + let _ = chunk.deallocate(); + // lief-doc: memory-end +} + +fn main() -> ExitCode { + if !runtime::enabled() { + eprintln!("Error: LIEF's runtime is not enabled"); + return ExitCode::SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/runtime_osx.rs b/vendor/lief/api/rust/examples/src/bin/runtime_osx.rs new file mode 100644 index 0000000..7e1cff3 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/runtime_osx.rs @@ -0,0 +1,240 @@ +use std::process::ExitCode; +use std::sync::Arc; + +use lief::assembly::{AssemblerConfig, Instruction}; +use lief::generic::{Binary, Symbol}; +use lief::runtime; +use lief::runtime::memory::{MmapFlags, Perm}; +use lief::runtime::module::Module; + +fn host_info() { + println!("Host"); + // lief-doc: host-start + println!(" Hostname: {}", runtime::Host::name()); + println!(" Home: {}", runtime::Host::home_dir()); + println!(" Cache: {}", runtime::Host::cache_dir()); + println!(" Temp: {}", runtime::Host::tmp_dir()); + println!(" Config: {}", runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-osx-start + println!(" Version: {}", runtime::osx::Host::os_version_name()); + println!( + " SIP: {}", + if runtime::osx::Host::is_sip_enabled() { + "enabled" + } else { + "disabled" + } + ); + // lief-doc: host-osx-end +} + +fn process_info() { + println!("Process"); + // lief-doc: process-start + println!(" PID: {}", runtime::Process::pid()); + println!(" TID: {}", runtime::Process::tid()); + println!(" Page size: {:#06x}", runtime::Process::page_size()); + println!(" Arch: {:?}", runtime::Process::arch()); + println!(" Platform: {:?}", runtime::Process::platform()); + // lief-doc: process-end + + // lief-doc: process-osx-start + println!(" dyld: {}", runtime::osx::Process::dyld_version()); + // lief-doc: process-osx-end +} + +fn modules_info() { + println!("Module API"); + + // Module referencing libsystem_c.dylib in memory + let mut libsystem: Option = None; + + // lief-doc: modules-start + for module in runtime::modules() { + println!( + "{} ({:#010x} - {:#010x})", + module.name(), + module.imagebase(), + module.end() + ); + if let runtime::Modules::Osx(osx_mod) = module { + if osx_mod.name().ends_with("libsystem_c.dylib") { + println!( + "libsystem_c.dylib found: {} ([{:#010x}, {:#010x}])", + osx_mod.path(), + osx_mod.imagebase(), + osx_mod.end() + ); + libsystem = Some(osx_mod); + } + } + } + // lief-doc: modules-end + + let libsystem = match libsystem { + Some(m) => m, + None => return, + }; + + // lief-doc: modules-osx-start + println!("libsystem_c path: {}", libsystem.path()); + let arc4_init = libsystem.dlsym("arc4_init".to_string()); + if !arc4_init.is_null() { + println!( + "{}!arc4_init: {:#010x}", + libsystem.name(), + arc4_init as usize + ); + + // Disassemble arc4_init directly from its resolved memory address + for inst in runtime::disassemble(arc4_init as u64).take(4) { + println!(" {}", inst.to_string()); + } + } + + // libsystem.path() looks like a valid path but libsystem_c.dylib lives in + // the dyld-shared-cache. Therefore, it's pointless to try to parse the + // library from its filepath as the library does not exist on the disk. + let macho_on_disk = { + let _scoped = lief::logging::Scoped::new(lief::logging::Level::Off); + libsystem.parse_from_path() + }; + if macho_on_disk.is_none() { + println!( + "As expected, {} is not present in the filesystem", + libsystem.path() + ); + } + + // But we can parse it from memory: + if let Some(macho_memory) = libsystem.parse_from_memory() { + println!("in-memory imagebase: {:#010x}", macho_memory.imagebase()); + // List 'exported' symbols + for sym in macho_memory.exported_symbols() { + println!("{:10}: {:#010x}", sym.name(), sym.value()); + } + } + // lief-doc: modules-osx-end +} + +fn memory_example() { + println!("Memory"); + // lief-doc: memory-start + // The JIT below allocates and executes RWX memory. On macOS this is only + // permitted when System Integrity Protection (SIP) is disabled, so gate the + // example on it. + if runtime::osx::Host::is_sip_enabled() { + eprintln!("SIP is enabled: skipping the JIT memory example"); + return; + } + + // Note the `JIT` flag here that is used to switch the allocated chunk into + // R-X once the shellcode is committed. + let mut chunk = match runtime::Memory::mmap( + runtime::Process::page_size() as u64, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE | MmapFlags::JIT, + Perm::READ | Perm::WRITE, + ) { + Some(c) => c, + None => return, + }; + + // libSystem re-exports the libc symbols (write, ...) + let libsystem = match runtime::osx::dlopen("libSystem.B.dylib") { + Some(m) => m, + None => { + eprintln!("Failed to dlopen libSystem.B.dylib"); + let _ = chunk.deallocate(); + return; + } + }; + + let p_write = libsystem.dlsym("write".to_string()); + if p_write.is_null() { + eprintln!("Failed to resolve write"); + let _ = chunk.deallocate(); + return; + } + let p_write = p_write as u64; + + // The message printed by the shellcode. + const HELLO: &[u8] = b"Hello World\n"; + let msg_ptr = HELLO.as_ptr() as u64; + let msg_len = HELLO.len() as u64; + + let mut config = AssemblerConfig::default(); + config.symbol_resolver = Some(Arc::new(move |name: &str| -> Option { + match name { + "write" => Some(p_write), + "var_msg" => Some(msg_ptr), + "var_msg_len" => Some(msg_len), + _ => None, + } + })); + + // Shellcode dynamically compiled and whose referenced symbols are resolved + // at runtime by the provided config + let raw_inst = runtime::assemble_with_config( + chunk.addr(), + r#" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x8, =write // write(2) libc wrapper + ldr x1, =var_msg // buffer + ldr w2, =var_msg_len // length + + // write(STDOUT_FILENO, msg, len) + mov x0, 1 + blr x8 + + mov x0, xzr + ldp x29, x30, [sp], 16 + ret + "#, + &config, + ); + + println!( + "{} bytes assembled at {:#010x}", + raw_inst.len(), + chunk.addr() + ); + + // Flush the instruction cache + chunk.cache_flush(); + + // Change the permission to R-X and invoke the JITed function + chunk.make_rx(); + + let hello_jit: unsafe extern "C" fn() = unsafe { std::mem::transmute(chunk.addr() as usize) }; + + // This call prints the message "Hello World" on the console + unsafe { hello_jit() }; + + // Don't miss good practices! + let _ = chunk.deallocate(); + // lief-doc: memory-end +} + +fn main() -> ExitCode { + if !runtime::enabled() { + eprintln!("Error: LIEF's runtime is not enabled"); + return ExitCode::SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/runtime_windows.rs b/vendor/lief/api/rust/examples/src/bin/runtime_windows.rs new file mode 100644 index 0000000..a1674ef --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/runtime_windows.rs @@ -0,0 +1,322 @@ +use std::process::ExitCode; +use std::sync::Arc; + +use lief::assembly::{AssemblerConfig, Instruction}; +use lief::runtime; +use lief::runtime::memory::{MmapFlags, Perm}; +use lief::runtime::module::Module; + +fn host_info() { + println!("Host"); + // lief-doc: host-start + println!(" Hostname: {}", runtime::Host::name()); + println!(" Home: {}", runtime::Host::home_dir()); + println!(" Cache: {}", runtime::Host::cache_dir()); + println!(" Temp: {}", runtime::Host::tmp_dir()); + println!(" Config: {}", runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-windows-start + if let Some(version) = runtime::windows::Host::version() { + println!(" Version: {}", version); + } + // lief-doc: host-windows-end +} + +fn process_info() { + println!("Process"); + // lief-doc: process-start + println!(" PID: {}", runtime::Process::pid()); + println!(" TID: {}", runtime::Process::tid()); + println!(" Page size: {:#06x}", runtime::Process::page_size()); + println!(" Arch: {:?}", runtime::Process::arch()); + println!(" Platform: {:?}", runtime::Process::platform()); + if let Some(userdomain) = runtime::Process::get_env("USERDOMAIN") { + println!(" USERDOMAIN:{}", userdomain); + } + // lief-doc: process-end + + // lief-doc: process-windows-start + if let Some(peb) = runtime::windows::Process::peb() { + println!(" PEB.BeingDebugged: {}", peb.being_debugged()); + println!(" PEB.Ldr: {:#06x}", peb.ldr()); + println!( + " PEB.ProcessParameters: {:#06x}", + peb.process_parameters() + ); + println!( + " PEB.AtlThunkSListPtr: {:#06x}", + peb.atl_thunk_slist_ptr() + ); + println!( + " PEB.AtlThunkSListPtr32: {:#06x}", + peb.atl_thunk_slist_ptr32() + ); + println!( + " PEB.PostProcessInitRoutine: {:#06x}", + peb.post_process_init_routine() + ); + println!(" PEB.SessionId: {:#06x}", peb.session_id()); + } + // lief-doc: process-windows-end + + // lief-doc: peb-modules-start + if let Some(peb) = runtime::windows::Process::peb() { + let modules: Vec<_> = peb.entries().collect(); + for (i, entry) in modules.iter().take(3).enumerate() { + println!( + " module[{}]: {} (base={:#06x}, size={:#06x})", + i, + entry.base_dll_name(), + entry.dll_base(), + entry.size_of_image() + ); + } + println!(" -> {} modules in the load order list", modules.len()); + if let Some(last) = modules.last() { + println!(" last module: {}", last.base_dll_name()); + } + } + // lief-doc: peb-modules-end + + // lief-doc: peb-module-details-start + if let Some(peb) = runtime::windows::Process::peb() { + if let Some(first) = peb.entries().next() { + println!( + " {} extended LDR_DATA_TABLE_ENTRY fields:", + first.base_dll_name() + ); + // Always available across the supported Windows versions: + println!(" Flags: {:#06x}", first.flags()); + println!(" ObsoleteLoadCount: {}", first.obsolete_load_count()); + println!(" TlsIndex: {:#06x}", first.tls_index()); + println!(" TimeDateStamp: {:#06x}", first.time_date_stamp()); + // Version-gated fields are None when the host kernel predates them: + if let Some(v) = first.ddag_node() { + println!(" DdagNode: {:#06x}", v); // Windows 8+ + } + if let Some(v) = first.original_base() { + println!(" OriginalBase: {:#06x}", v); // Windows 8+ + } + if let Some(v) = first.load_reason() { + println!(" LoadReason: {}", v); // Windows 8+ + } + if let Some(v) = first.signing_level() { + println!(" SigningLevel: {}", v); // Windows 10+ + } + if let Some(v) = first.check_sum() { + println!(" CheckSum: {:#06x}", v); // Windows 10+ + } + if let Some(v) = first.hot_patch_state() { + println!(" HotPatchState: {}", v); // Windows 11+ + } + } + } + // lief-doc: peb-module-details-end +} + +fn modules_info() { + println!("Module API"); + let mut ntdll: Option = None; + // lief-doc: modules-start + for module in runtime::modules() { + println!( + "{} ({:#010x} - {:#010x})", + module.name(), + module.imagebase(), + module.end() + ); + if let runtime::Modules::Windows(win_mod) = module { + if win_mod.name().ends_with("ntdll.dll") { + println!( + "ntdll.dll found: {} ([{:#010x}, {:#010x}])", + win_mod.path(), + win_mod.imagebase(), + win_mod.end() + ); + ntdll = Some(win_mod); + } + } + } + // lief-doc: modules-end + + let ntdll = match ntdll { + Some(m) => m, + None => return, + }; + + // lief-doc: modules-windows-start + println!("ntdll path: {}", ntdll.path()); + let nt_query = ntdll.dlsym("NtQueryInformationProcess".to_string()); + if !nt_query.is_null() { + println!( + "{}!NtQueryInformationProcess: {:#010x}", + ntdll.name(), + nt_query as usize + ); + } + + // Parse the PE from its path on the disk + if let Some(pe_on_disk) = ntdll.parse_from_path() { + println!( + "on-disk imagebase: {:#010x}", + pe_on_disk.optional_header().imagebase() + ); + if let Some(export) = pe_on_disk.export() { + if let Some(entry) = export.entry_by_name("NtQueryInformationProcess") { + println!("NtQueryInformationProcess: {:#010x}", entry.address()); + } + } + } + + // Parse the PE directly from memory + if let Some(pe_memory) = ntdll.parse_from_memory() { + let imagebase = pe_memory.optional_header().imagebase(); + println!("in-memory imagebase: {:#010x}", imagebase); + if let Some(export) = pe_memory.export() { + if let Some(entry) = export.entry_by_name("RtlFreeHeap") { + let rva = entry.address() as u64; + println!("RtlFreeHeap: {:#010x}", rva); + + // Disassemble the first instructions of RtlFreeHeap from memory + for inst in runtime::disassemble(imagebase + rva).take(4) { + println!(" {}", inst.to_string()); + } + } + } + } + // lief-doc: modules-windows-end +} + +fn memory_example() { + println!("Memory"); + // lief-doc: memory-start + let mut chunk = match runtime::Memory::mmap( + runtime::Process::page_size() as u64, + MmapFlags::ANONYMOUS | MmapFlags::PRIVATE, + Perm::READ | Perm::WRITE | Perm::EXEC, + ) { + Some(c) => c, + None => return, + }; + + // Resolve kernel32 (loaded in every Windows process) + let kernel32 = match runtime::windows::dlopen("kernel32.dll") { + Some(m) => m, + None => { + eprintln!("Failed to dlopen kernel32.dll"); + let _ = chunk.deallocate(); + return; + } + }; + + let p_get_std_handle = kernel32.dlsym("GetStdHandle".to_string()); + let p_write_file = kernel32.dlsym("WriteFile".to_string()); + if p_get_std_handle.is_null() || p_write_file.is_null() { + eprintln!("Failed to resolve kernel32 symbols"); + let _ = chunk.deallocate(); + return; + } + let p_get_std_handle = p_get_std_handle as u64; + let p_write_file = p_write_file as u64; + + // The message printed by the shellcode. + const HELLO: &[u8] = b"Hello World\n"; + let msg_ptr = HELLO.as_ptr() as u64; + let msg_len = HELLO.len() as u64; + + let mut config = AssemblerConfig::default(); + config.symbol_resolver = Some(Arc::new(move |name: &str| -> Option { + match name { + "GetStdHandle" => Some(p_get_std_handle), + "WriteFile" => Some(p_write_file), + "var_msg" => Some(msg_ptr), + "var_msg_len" => Some(msg_len), + _ => None, + } + })); + + // Shellcode dynamically compiled and whose referenced symbols are resolved + // at runtime by the provided config + let raw_inst = runtime::assemble_with_config( + chunk.addr(), + r#" + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -64]! + mov x29, sp + stp x19, x20, [sp, 16] + stp x21, x22, [sp, 32] + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x19, =GetStdHandle + ldr x20, =WriteFile + ldr x21, =var_msg + ldr w22, =var_msg_len + + // Call GetStdHandle(STD_OUTPUT_HANDLE) + // STD_OUTPUT_HANDLE = -11 + // GetStdHandle is stored in x19 + mov w0, -11 + blr x19 + + // Call ---> bool WriteFile( + // HANDLE hConsoleOutput, // x0: from GetStdHandle (already set) + // const VOID *lpBuffer, // x1: pointer to string + // DWORD nNumberOfCharsToWrite, // w2: length of string + // LPDWORD lpNumberOfCharsWritten,// x3: pointer to written count + // LPVOID lpReserved // x4: NULL + // ); + mov x1, x21 + mov w2, w22 + add x3, sp, 48 + mov x4, xzr + blr x20 + + mov x0, xzr + ldp x21, x22, [sp, 32] + ldp x19, x20, [sp, 16] + ldp x29, x30, [sp], 64 + ret + "#, + &config, + ); + + println!( + "{} bytes assembled at {:#010x}", + raw_inst.len(), + chunk.addr() + ); + + // Flush the instruction cache + chunk.cache_flush(); + + // Change the permission to R-X and invoke the JITed function + chunk.make_rx(); + + let hello_jit: unsafe extern "C" fn() = unsafe { std::mem::transmute(chunk.addr() as usize) }; + + // This call prints the message "Hello World" on the console + unsafe { hello_jit() }; + + // Don't miss good practices! + let _ = chunk.deallocate(); + // lief-doc: memory-end +} + +fn main() -> ExitCode { + if !runtime::enabled() { + eprintln!("Error: LIEF's runtime is not enabled"); + return ExitCode::SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/examples/src/bin/test_run_examples.rs b/vendor/lief/api/rust/examples/src/bin/test_run_examples.rs new file mode 100644 index 0000000..c6c1885 --- /dev/null +++ b/vendor/lief/api/rust/examples/src/bin/test_run_examples.rs @@ -0,0 +1,78 @@ +use std::env; +use std::path::PathBuf; +use std::process::Command; +use std::process::ExitCode; + +fn get_sample(format: &str, name: &str, private: bool) -> PathBuf { + let mut sample_dir = + PathBuf::from(env::var_os("LIEF_SAMPLES_DIR").expect("LIEF_SAMPLES_DIR not set")); + if private { + sample_dir.push("private"); + } + sample_dir.push(format); + sample_dir.push(name); + sample_dir +} + +fn call_example_with(mut example_dir: PathBuf, example: &str, sample: PathBuf) { + example_dir.push(example); + example_dir.with_extension(std::env::consts::EXE_EXTENSION); + let status = Command::new(example_dir.to_str().unwrap()) + .arg(sample.to_str().unwrap()) + .status() + .expect("Command failed"); + println!("process finished with: {status}"); + assert!(status.success()); +} + +fn main() -> ExitCode { + let argv0 = std::env::args().next().expect("argv[0]"); + let program_path = PathBuf::from(argv0); + let example_dir = program_path.parent().expect("Parent path").to_path_buf(); + + call_example_with( + example_dir.clone(), + "pe_check_authenticode", + get_sample( + "PE", + "PE32_x86-64_binary_avast-free-antivirus-setup-online.exe", + false, + ), + ); + + call_example_with( + example_dir.clone(), + "pe_deps", + get_sample("PE", "PE64_x86-64_binary_WinApp.exe", false), + ); + + call_example_with( + example_dir.clone(), + "pe_rich_header", + get_sample("PE", "PE32_x86_binary_cmd.exe", false), + ); + + call_example_with( + example_dir.clone(), + "list_macho_encryption.rs", + get_sample("MachO", "pgo.enc", true), + ); + + call_example_with( + example_dir.clone(), + "elf_deps", + get_sample("ELF", "ELF64_x86-64_binary_etterlog.bin", false), + ); + + call_example_with( + example_dir.clone(), + "dwarf_editor", + get_sample( + "PE", + "PE32_x86-64_binary_avast-free-antivirus-setup-online.exe", + false, + ), + ); + + ExitCode::SUCCESS +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/ASM.hpp b/vendor/lief/api/rust/include/LIEF/rust/ASM.hpp new file mode 100644 index 0000000..a4bb28d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ASM.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/asm/Engine.hpp" +#include "LIEF/rust/asm/Instruction.hpp" + +#include "LIEF/rust/asm/aarch64/Instruction.hpp" +#include "LIEF/rust/asm/aarch64/operands.hpp" +#include "LIEF/rust/asm/aarch64/operands/Register.hpp" + +#include "LIEF/rust/asm/x86/Instruction.hpp" +#include "LIEF/rust/asm/x86/operands.hpp" +#include "LIEF/rust/asm/x86/operands/Register.hpp" + +#include "LIEF/rust/asm/arm/Instruction.hpp" +#include "LIEF/rust/asm/ebpf/Instruction.hpp" +#include "LIEF/rust/asm/mips/Instruction.hpp" +#include "LIEF/rust/asm/powerpc/Instruction.hpp" +#include "LIEF/rust/asm/riscv/Instruction.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract.hpp new file mode 100644 index 0000000..70f30ea --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract.hpp @@ -0,0 +1,21 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Abstract/Binary.hpp" +#include "LIEF/rust/Abstract/DebugInfo.hpp" +#include "LIEF/rust/Abstract/Function.hpp" +#include "LIEF/rust/Abstract/Relocation.hpp" +#include "LIEF/rust/Abstract/Section.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/Binary.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Binary.hpp new file mode 100644 index 0000000..646fc7b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Binary.hpp @@ -0,0 +1,167 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include +#include +#include +#include + +#include "LIEF/rust/error.hpp" + +class AbstractBinary : public Mirror { + public: + using lief_t = LIEF::Binary; + using Mirror::Mirror; + + class it_instructions + : public ForwardIterator { + public: + it_instructions(const AbstractBinary::lief_t& src, uint64_t addr, + size_t size) : + ForwardIterator(src.disassemble(addr, size)) {} + + it_instructions(const AbstractBinary::lief_t& src, uint64_t addr) : + ForwardIterator(src.disassemble(addr)) {} + + it_instructions(const AbstractBinary::lief_t& src, const std::string& func) : + ForwardIterator(src.disassemble(func)) {} + + it_instructions(const AbstractBinary::lief_t& src, const uint8_t* ptr, + size_t size, uint64_t address) : + ForwardIterator(src.disassemble(ptr, size, address)) {} + + auto next() { + return ForwardIterator::next(); + } + }; + + + class it_functions + : public ContainerIterator { + public: + it_functions(LIEF::Binary::functions_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + uint64_t entrypoint() const { + return get().entrypoint(); + } + uint64_t imagebase() const { + return get().imagebase(); + } + uint64_t virtual_size() const { + return get().virtual_size(); + } + uint64_t original_size() const { + return get().original_size(); + } + auto is_pie() const { + return get().is_pie(); + } + auto has_nx() const { + return get().has_nx(); + } + + uint8_t get_u8(uint64_t addr, uint32_t& err) const { + return details::make_error(get().get_int_from_virtual_address(addr), + err); + } + + uint16_t get_u16(uint64_t addr, uint32_t& err) const { + return details::make_error(get().get_int_from_virtual_address(addr), + err); + } + + uint32_t get_u32(uint64_t addr, uint32_t& err) const { + return details::make_error(get().get_int_from_virtual_address(addr), + err); + } + + uint64_t get_u64(uint64_t addr, uint32_t& err) const { + return details::make_error(get().get_int_from_virtual_address(addr), + err); + } + + uint64_t offset_to_virtual_address(uint64_t offset, uint64_t slide, + uint32_t& err) const { + return details::make_error(get().offset_to_virtual_address(offset, slide), + err); + } + + auto debug_info() const { + return details::try_unique( + get().debug_info() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto disassemble(uint64_t addr, uint64_t size) const { + return std::make_unique(get(), addr, size); + } + + auto disassemble_address(uint64_t addr) const { + return std::make_unique(get(), addr); + } + + auto disassemble_buffer(const uint8_t* ptr, uint64_t size, uint64_t addr) const { + return std::make_unique(get(), ptr, size, addr); + } + + auto disassemble_function(const std::string& function) const { + return std::make_unique(get(), function); + } + + auto assemble(uint64_t address, const std::string& Asm) { + return make_unique_vector(get().assemble(address, Asm)); + } + + auto assemble_with_config(uint64_t address, const std::string& Asm, + const AssemblerConfig_r& ffi_config) { + std::unique_ptr config = + from_rust(ffi_config); + assert(config != nullptr); + return make_unique_vector(get().assemble(address, Asm, *config)); + } + + auto load_debug_info(const std::string& file) { + return details::try_unique(get().load_debug_info(file)); + } + + uint64_t page_size() const { + return get().page_size(); + } + + void patch_address_bytes(uint64_t address, const uint8_t* patch_value, + uint64_t size) { + get().patch_address(address, + std::vector(patch_value, patch_value + size)); + } + + void patch_address_value(uint64_t address, uint64_t patch_value, uint64_t size) { + get().patch_address(address, patch_value, size); + } +}; + +using AbstractBinary_it_functions = AbstractBinary::it_functions; +using AbstractBinary_it_instructions = AbstractBinary::it_instructions; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/DebugInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/DebugInfo.hpp new file mode 100644 index 0000000..b0b411b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/DebugInfo.hpp @@ -0,0 +1,28 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include + +class AbstracDebugInfo : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::DebugInfo; + + uint64_t find_function_address(const std::string& name, uint32_t& is_set) const { + return details::make_optional(get().find_function_address(name), is_set); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/Function.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Function.hpp new file mode 100644 index 0000000..ad61be4 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Function.hpp @@ -0,0 +1,39 @@ + +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include + +class AbstractFunction : public AbstractSymbol { + public: + using lief_t = LIEF::Function; + AbstractFunction(const lief_t& obj) : + AbstractSymbol(obj) {} + + auto address() const { + return impl().address(); + } + auto flags() const { + return to_int(impl().flags()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/Relocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Relocation.hpp new file mode 100644 index 0000000..1c45031 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Relocation.hpp @@ -0,0 +1,29 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include + +class AbstractRelocation : public Mirror { + public: + using Mirror::Mirror; + + uint64_t size() const { + return get().size(); + } + uint64_t address() const { + return get().address(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/Section.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Section.hpp new file mode 100644 index 0000000..7a5f4f0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Section.hpp @@ -0,0 +1,54 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include + +#include + +class AbstractSection : public Mirror { + public: + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + uint64_t size() const { + return get().size(); + } + uint64_t offset() const { + return get().offset(); + } + uint64_t virtual_address() const { + return get().virtual_address(); + } + Span content() const { + return make_span(get().content()); + } + + auto set_name(const std::string& name) { + get().name(name); + } + + auto set_content(const uint8_t* buffer, size_t size) { + get().content({buffer, buffer + size}); + } + + auto set_size(uint64_t size) { + get().size(size); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Abstract/Symbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Symbol.hpp new file mode 100644 index 0000000..97db42a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Abstract/Symbol.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include + +#include + +class AbstractSymbol : public Mirror { + public: + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + auto size() const { + return get().size(); + } + auto value() const { + return get().value(); + } + + auto set_name(const std::string& name) { + get().name(name); + } + + auto set_value(uint64_t value) { + get().value(value); + } + + auto set_size(uint64_t sz) { + get().size(sz); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF.hpp new file mode 100644 index 0000000..cac6dda --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF.hpp @@ -0,0 +1,31 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/COFF/Binary.hpp" +#include "LIEF/rust/COFF/Header.hpp" +#include "LIEF/rust/COFF/Relocation.hpp" +#include "LIEF/rust/COFF/Section.hpp" +#include "LIEF/rust/COFF/String.hpp" +#include "LIEF/rust/COFF/Symbol.hpp" + +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFile.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp" + +#include "LIEF/rust/COFF/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbol.hpp new file mode 100644 index 0000000..2ab436a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbol.hpp @@ -0,0 +1,29 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" + +class COFF_AuxiliarySymbol : public Mirror { + public: + using lief_t = LIEF::COFF::AuxiliarySymbol; + using Mirror::Mirror; + + auto payload() const { + return make_span(get().payload()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp new file mode 100644 index 0000000..2774471 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp @@ -0,0 +1,56 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/COFF/Symbol.hpp" +#include "LIEF/rust/Span.hpp" + +class COFF_AuxiliaryCLRToken : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliaryCLRToken; + COFF_AuxiliaryCLRToken(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + auto aux_type() const { + return impl().aux_type(); + } + + auto reserved() const { + return impl().reserved(); + } + + auto symbol_idx() const { + return impl().symbol_idx(); + } + + auto symbol() const { + return details::try_unique(impl().symbol()); + } + + auto rgb_reserved() const { + return make_span(impl().rgb_reserved()); + } + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFile.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFile.hpp new file mode 100644 index 0000000..78f0990 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFile.hpp @@ -0,0 +1,39 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_AuxiliaryFile : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliaryFile; + COFF_AuxiliaryFile(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + auto filename() const { + return to_unique_string(impl().filename()); + } + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp new file mode 100644 index 0000000..a61e323 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" + +class COFF_AuxiliaryFunctionDefinition : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliaryFunctionDefinition; + COFF_AuxiliaryFunctionDefinition(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + auto tag_index() const { + return impl().tag_index(); + } + auto total_size() const { + return impl().total_size(); + } + auto ptr_to_line_number() const { + return impl().ptr_to_line_number(); + } + auto ptr_to_next_func() const { + return impl().ptr_to_next_func(); + } + auto padding() const { + return impl().padding(); + } + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp new file mode 100644 index 0000000..45363f3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp @@ -0,0 +1,57 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_AuxiliarySectionDefinition : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliarySectionDefinition; + COFF_AuxiliarySectionDefinition(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + auto length() const { + return impl().length(); + } + auto nb_relocs() const { + return impl().nb_relocs(); + } + auto nb_line_numbers() const { + return impl().nb_line_numbers(); + } + auto checksum() const { + return impl().checksum(); + } + auto section_idx() const { + return impl().section_idx(); + } + auto selection() const { + return to_int(impl().selection()); + } + auto reserved() const { + return impl().reserved(); + } + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp new file mode 100644 index 0000000..bf5da4e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_AuxiliaryWeakExternal : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliaryWeakExternal; + COFF_AuxiliaryWeakExternal(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + auto sym_idx() const { + return impl().sym_idx(); + } + auto characteristics() const { + return to_int(impl().characteristics()); + } + + auto padding() const { + return make_span(impl().padding()); + } + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp new file mode 100644 index 0000000..37882ec --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp @@ -0,0 +1,34 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" + +class COFF_AuxiliarybfAndefSymbol : public COFF_AuxiliarySymbol { + public: + using lief_t = LIEF::COFF::AuxiliarybfAndefSymbol; + COFF_AuxiliarybfAndefSymbol(const lief_t& obj) : + COFF_AuxiliarySymbol(obj) {} + + static auto classof(const COFF_AuxiliarySymbol& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/Binary.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/Binary.hpp new file mode 100644 index 0000000..bd56f75 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/Binary.hpp @@ -0,0 +1,191 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/COFF/Binary.hpp" +#include "LIEF/COFF/Parser.hpp" + +#include "LIEF/rust/COFF/Header.hpp" +#include "LIEF/rust/COFF/Relocation.hpp" +#include "LIEF/rust/COFF/Section.hpp" +#include "LIEF/rust/COFF/String.hpp" +#include "LIEF/rust/COFF/Symbol.hpp" + +#include "LIEF/rust/asm/Instruction.hpp" + +#include "LIEF/rust/Mirror.hpp" + +class COFF_Binary : Mirror { + public: + using lief_t = LIEF::COFF::Binary; + using Mirror::Mirror; + + class it_relocations + : public Iterator { + public: + it_relocations(const COFF_Binary::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols + : public Iterator { + public: + it_symbols(const COFF_Binary::lief_t& src) : + Iterator(src.symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_sections + : public Iterator { + public: + it_sections(const COFF_Binary::lief_t& src) : + Iterator(src.sections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_strings + : public Iterator { + public: + it_strings(const COFF_Binary::lief_t& src) : + Iterator(src.string_table()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_functions + : public Iterator { + public: + it_functions(const COFF_Binary::lief_t& src) : + Iterator(src.functions()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_instructions + : public ForwardIterator { + public: + it_instructions(const COFF_Binary::lief_t& src, const std::string& func) : + ForwardIterator(src.disassemble(func)) {} + + it_instructions(const COFF_Binary::lief_t& src, + const LIEF::COFF::Symbol& sym) : + ForwardIterator(src.disassemble(sym)) {} + + it_instructions(const COFF_Binary::lief_t& src, const uint8_t* ptr, + size_t size, uint64_t address) : + ForwardIterator(src.disassemble(ptr, size, address)) {} + + auto next() { + return ForwardIterator::next(); + } + }; + + static auto parse(const std::string& path) { + return details::try_unique(LIEF::COFF::Parser::parse(path)); + } + + auto header() const { + return std::make_unique(get().header()); + } + + auto sections() const { + return std::make_unique(get()); + } + + auto symbols() const { + return std::make_unique(get()); + } + + auto relocations() const { + return std::make_unique(get()); + } + + auto string_table() const { + return std::make_unique(get()); + } + + auto section_by_name(const std::string& name) const { + return details::try_unique( + get().get_section(name) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto find_string(uint32_t offset) const { + return details::try_unique(get().find_string(offset)); + } + + auto find_function(const std::string& name) const { + return details::try_unique(get().find_function(name)); + } + + auto find_demangled_function(const std::string& name) const { + return details::try_unique(get().find_demangled_function(name)); + } + + auto functions() const { + return std::make_unique(get()); + } + + auto disassemble_buffer(const uint8_t* ptr, uint64_t size, uint64_t addr) const { + return std::make_unique(get(), ptr, size, addr); + } + + auto disassemble_function(const std::string& function) const { + return std::make_unique(get(), function); + } + + auto disassemble_symbol(const COFF_Symbol& sym) const { + return std::make_unique( + get(), static_cast(sym.get()) + ); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +using COFF_Binary_it_relocations = COFF_Binary::it_relocations; +using COFF_Binary_it_symbols = COFF_Binary::it_symbols; +using COFF_Binary_it_sections = COFF_Binary::it_sections; +using COFF_Binary_it_strings = COFF_Binary::it_strings; +using COFF_Binary_it_functions = COFF_Binary::it_functions; +using COFF_Binary_it_instructions = COFF_Binary::it_instructions; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/Header.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/Header.hpp new file mode 100644 index 0000000..700270b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/Header.hpp @@ -0,0 +1,110 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/COFF/BigObjHeader.hpp" +#include "LIEF/COFF/Header.hpp" +#include "LIEF/COFF/RegularHeader.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_Header : public Mirror { + public: + using lief_t = LIEF::COFF::Header; + using Mirror::Mirror; + + auto machine() const { + return as_u32(get().machine()); + } + + auto nb_sections() const { + return get().nb_sections(); + } + auto pointerto_symbol_table() const { + return get().pointerto_symbol_table(); + } + auto nb_symbols() const { + return get().nb_symbols(); + } + auto timedatestamp() const { + return get().timedatestamp(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class COFF_RegularHeader : public COFF_Header { + public: + using lief_t = LIEF::COFF::RegularHeader; + + auto sizeof_optionalheader() const { + return impl().sizeof_optionalheader(); + } + + auto characteristics() const { + return impl().characteristics(); + } + + static auto classof(const COFF_Header& hdr) { + return lief_t::classof(&hdr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class COFF_BigObjHeader : public COFF_Header { + public: + using lief_t = LIEF::COFF::BigObjHeader; + + auto version() const { + return impl().version(); + } + + auto uuid() const { + return make_span(impl().uuid()); + } + + auto sizeof_data() const { + return impl().sizeof_data(); + } + + auto flags() const { + return impl().flags(); + } + + auto metadata_size() const { + return impl().metadata_size(); + } + + auto metadata_offset() const { + return impl().metadata_offset(); + } + + static auto classof(const COFF_Header& hdr) { + return lief_t::classof(&hdr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/Relocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/Relocation.hpp new file mode 100644 index 0000000..5368fa5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/Relocation.hpp @@ -0,0 +1,55 @@ + +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/Relocation.hpp" +#include "LIEF/rust/Abstract/Relocation.hpp" +#include "LIEF/rust/COFF/Symbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_Section; + +class COFF_Relocation : public AbstractRelocation { + public: + using lief_t = LIEF::COFF::Relocation; + COFF_Relocation(const lief_t& obj) : + AbstractRelocation(obj) {} + + auto symbol_idx() const { + return impl().symbol_idx(); + } + + auto symbol() const { + return details::try_unique(impl().symbol()); + } + + auto get_type() const { + return to_int(impl().type()); + } + + auto section() const { + return details::try_unique(impl().section()); + } + + auto to_string() const { + return to_unique_string(impl().to_string()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/Section.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/Section.hpp new file mode 100644 index 0000000..b5fe33d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/Section.hpp @@ -0,0 +1,128 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/COFF/Section.hpp" +#include "LIEF/rust/Abstract/Section.hpp" +#include "LIEF/rust/COFF/Relocation.hpp" +#include "LIEF/rust/COFF/String.hpp" + +#include "LIEF/rust/Iterator.hpp" + +class COFF_Section_ComdataInfo : Mirror { + public: + using Mirror::Mirror; + auto symbol() const { + return details::try_unique(get().symbol); + } + + auto kind() const { + return to_int(get().kind); + } +}; + +class COFF_Section : public AbstractSection { + public: + using lief_t = LIEF::COFF::Section; + + COFF_Section(const lief_t& sec) : + AbstractSection(sec) {} + + class it_relocations + : public Iterator { + public: + it_relocations(const COFF_Section::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols + : public Iterator { + public: + it_symbols(const COFF_Section::lief_t& src) : + Iterator(src.symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto sizeof_raw_data() const { + return impl().sizeof_raw_data(); + } + auto virtual_size() const { + return impl().virtual_size(); + } + auto pointerto_raw_data() const { + return impl().pointerto_raw_data(); + } + auto pointerto_relocation() const { + return impl().pointerto_relocation(); + } + auto pointerto_line_numbers() const { + return impl().pointerto_line_numbers(); + } + auto numberof_relocations() const { + return impl().numberof_relocations(); + } + auto numberof_line_numbers() const { + return impl().numberof_line_numbers(); + } + auto characteristics() const { + return impl().characteristics(); + } + + auto is_discardable() const { + return impl().is_discardable(); + } + + auto has_extended_relocations() const { + return impl().has_extended_relocations(); + } + + auto relocations() const { + return std::make_unique(impl()); + } + + auto symbols() const { + return std::make_unique(impl()); + } + + auto comdat_info() const { + return details::try_unique(impl().comdat_info()); + } + + auto coff_string() const { + return details::try_unique(impl().coff_string()); + } + + auto to_string() const { + return to_unique_string(impl().to_string()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using COFF_Section_it_relocations = COFF_Section::it_relocations; +using COFF_Section_it_symbols = COFF_Section::it_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/String.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/String.hpp new file mode 100644 index 0000000..2436ace --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/String.hpp @@ -0,0 +1,33 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/COFF/String.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_String : public Mirror { + public: + using lief_t = LIEF::COFF::String; + using Mirror::Mirror; + + auto str() const { + return to_unique_string(get().str()); + } + + auto offset() const { + return get().offset(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/Symbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/Symbol.hpp new file mode 100644 index 0000000..4a2c9a2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/Symbol.hpp @@ -0,0 +1,112 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/COFF/Symbol.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/COFF/AuxiliarySymbol.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class COFF_Section; + +class COFF_Symbol : public AbstractSymbol { + public: + using lief_t = LIEF::COFF::Symbol; + COFF_Symbol(const lief_t& obj) : + AbstractSymbol(obj) {} + + class it_auxiliary_symbols + : public Iterator { + public: + it_auxiliary_symbols(const COFF_Symbol::lief_t& src) : + Iterator(src.auxiliary_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto storage_class() const { + return as_u32(impl().storage_class()); + } + + auto base_type() const { + return as_u32(impl().base_type()); + } + + auto complex_type() const { + return as_u32(impl().complex_type()); + } + + auto section_idx() const { + return impl().section_idx(); + } + + auto section() const { + return details::try_unique(impl().section()); + } + + auto is_external() const { + return impl().is_external(); + } + + auto is_function() const { + return impl().is_function(); + } + + auto is_absolute() const { + return impl().is_absolute(); + } + + auto is_weak_external() const { + return impl().is_weak_external(); + } + + auto is_undefined() const { + return impl().is_undefined(); + } + + auto is_function_line_info() const { + return impl().is_function_line_info(); + } + + auto is_file_record() const { + return impl().is_file_record(); + } + + auto auxiliary_symbols() const { + return std::make_unique(impl()); + } + + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + auto to_string() const { + return to_unique_string(impl().to_string()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using COFF_Symbol_it_auxiliary_symbols = COFF_Symbol::it_auxiliary_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/COFF/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/COFF/utils.hpp new file mode 100644 index 0000000..bb29d33 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/COFF/utils.hpp @@ -0,0 +1,24 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/COFF/utils.hpp" +#include + +class COFF_Utils { + public: + static auto is_coff(const std::string& file) { + return LIEF::COFF::is_coff(file); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF.hpp new file mode 100644 index 0000000..111e7ce --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF.hpp @@ -0,0 +1,61 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/DWARF/CompilationUnit.hpp" +#include "LIEF/rust/DWARF/DebugInfo.hpp" +#include "LIEF/rust/DWARF/Function.hpp" +#include "LIEF/rust/DWARF/LexicalBlock.hpp" +#include "LIEF/rust/DWARF/Parameter.hpp" +#include "LIEF/rust/DWARF/Scope.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/DWARF/Variable.hpp" + +#include "LIEF/rust/DWARF/types/Array.hpp" +#include "LIEF/rust/DWARF/types/Atomic.hpp" +#include "LIEF/rust/DWARF/types/Base.hpp" +#include "LIEF/rust/DWARF/types/ClassLike.hpp" +#include "LIEF/rust/DWARF/types/Coarray.hpp" +#include "LIEF/rust/DWARF/types/Const.hpp" +#include "LIEF/rust/DWARF/types/Dynamic.hpp" +#include "LIEF/rust/DWARF/types/Enum.hpp" +#include "LIEF/rust/DWARF/types/File.hpp" +#include "LIEF/rust/DWARF/types/Immutable.hpp" +#include "LIEF/rust/DWARF/types/Interface.hpp" +#include "LIEF/rust/DWARF/types/Pointer.hpp" +#include "LIEF/rust/DWARF/types/PointerToMember.hpp" +#include "LIEF/rust/DWARF/types/RValueRef.hpp" +#include "LIEF/rust/DWARF/types/Reference.hpp" +#include "LIEF/rust/DWARF/types/Restrict.hpp" +#include "LIEF/rust/DWARF/types/SetTy.hpp" +#include "LIEF/rust/DWARF/types/Shared.hpp" +#include "LIEF/rust/DWARF/types/StringTy.hpp" +#include "LIEF/rust/DWARF/types/Subroutine.hpp" +#include "LIEF/rust/DWARF/types/TemplateAlias.hpp" +#include "LIEF/rust/DWARF/types/Thrown.hpp" +#include "LIEF/rust/DWARF/types/Typedef.hpp" +#include "LIEF/rust/DWARF/types/Volatile.hpp" + +#include "LIEF/rust/DWARF/Editor.hpp" +#include "LIEF/rust/DWARF/editor/ArrayType.hpp" +#include "LIEF/rust/DWARF/editor/BaseType.hpp" +#include "LIEF/rust/DWARF/editor/CompilationUnit.hpp" +#include "LIEF/rust/DWARF/editor/EnumType.hpp" +#include "LIEF/rust/DWARF/editor/Function.hpp" +#include "LIEF/rust/DWARF/editor/FunctionType.hpp" +#include "LIEF/rust/DWARF/editor/PointerType.hpp" +#include "LIEF/rust/DWARF/editor/StructType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" +#include "LIEF/rust/DWARF/editor/TypeDef.hpp" +#include "LIEF/rust/DWARF/editor/Variable.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/CompilationUnit.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/CompilationUnit.hpp new file mode 100644 index 0000000..31f663b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/CompilationUnit.hpp @@ -0,0 +1,158 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/CompilationUnit.hpp" + +#include "LIEF/rust/DWARF/Function.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/range.hpp" + +struct imported_t {}; +struct implemented_t {}; + +class DWARF_CompilationUnit : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::CompilationUnit; + + class it_functions + : public ForwardIterator { + public: + it_functions(const DWARF_CompilationUnit::lief_t& src, implemented_t) : + ForwardIterator(src.functions()) {} + + it_functions(const DWARF_CompilationUnit::lief_t& src, imported_t) : + ForwardIterator(src.imported_functions()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_types + : public ForwardIterator { + public: + it_types(const DWARF_CompilationUnit::lief_t& src) : + ForwardIterator(src.types()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_variables + : public ForwardIterator { + public: + it_variables(const DWARF_CompilationUnit::lief_t& src) : + ForwardIterator(src.variables()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class Language { + public: + uint32_t lang = 0; + uint32_t version = 0; + }; + + auto name() const { + return to_unique_string(get().name()); + } + auto producer() const { + return to_unique_string(get().producer()); + } + auto compilation_dir() const { + return to_unique_string(get().compilation_dir()); + } + + auto low_address() const { + return get().low_address(); + } + auto high_address() const { + return get().high_address(); + } + auto size() const { + return get().size(); + } + auto ranges() const { + return make_unique_vector(details::make_range(get().ranges())); + } + + Language language() const { + auto lang = get().language(); + return {/*lang=*/to_int(lang.lang), + /*version=*/lang.version}; + } + + auto function_by_name(const std::string& name) const { + return details::try_unique(get().find_function(name)); + } + + auto function_by_address(uint64_t addr) const { + return details::try_unique(get().find_function(addr)); + } + + auto variable_by_name(const std::string& name) const { + return details::try_unique(get().find_variable(name)); + } + + auto variable_by_address(uint64_t addr) const { + return details::try_unique( + get().find_variable(addr) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto functions() const { + return std::make_unique(get(), implemented_t{}); + } + + auto imported_functions() const { + return std::make_unique(get(), imported_t{}); + } + + auto types() const { + return std::make_unique(get()); + } + + auto variables() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; + +using DWARF_CompilationUnit_it_functions = DWARF_CompilationUnit::it_functions; +using DWARF_CompilationUnit_it_types = DWARF_CompilationUnit::it_types; +using DWARF_CompilationUnit_it_variables = DWARF_CompilationUnit::it_variables; +using DWARF_CompilationUnit_Language = DWARF_CompilationUnit::Language; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/DebugInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/DebugInfo.hpp new file mode 100644 index 0000000..70db0f1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/DebugInfo.hpp @@ -0,0 +1,86 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include + +#include "LIEF/rust/Iterator.hpp" + +class DWARF_DebugInfo : public AbstracDebugInfo { + public: + using lief_t = LIEF::dwarf::DebugInfo; + + class it_compilation_units + : public ForwardIterator { + public: + it_compilation_units(const DWARF_DebugInfo::lief_t& src) : + ForwardIterator(src.compilation_units()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + DWARF_DebugInfo(std::unique_ptr bin) : + AbstracDebugInfo(std::move(bin)) {} + + static auto from_file(const std::string& file) { + return details::try_unique( + LIEF::dwarf::DebugInfo::from_file(file) + ); + } + + auto compilation_units() const { + return std::make_unique(impl()); + } + + auto function_by_name(const std::string& name) const { + return details::try_unique(impl().find_function(name)); + } + + auto function_by_addr(uint64_t addr) const { + return details::try_unique(impl().find_function(addr)); + } + + auto variable_by_name(const std::string& name) const { + return details::try_unique(impl().find_variable(name)); + } + + auto variable_by_addr(uint64_t addr) const { + return details::try_unique(impl().find_variable(addr)); + } + + auto type_by_name(const std::string& name) const { + return details::try_unique(impl().find_type(name)); + } + + static auto classof(const AbstracDebugInfo& reloc) { + return lief_t::classof( + static_cast(&reloc.get()) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using DWARF_DebugInfo_it_compilation_units = DWARF_DebugInfo::it_compilation_units; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Editor.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Editor.hpp new file mode 100644 index 0000000..a07cb24 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Editor.hpp @@ -0,0 +1,44 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Abstract/Binary.hpp" +#include "LIEF/rust/DWARF/editor/CompilationUnit.hpp" +#include "LIEF/rust/Mirror.hpp" +#include + +class DWARF_Editor : public Mirror { + public: + using lief_t = LIEF::dwarf::Editor; + using Mirror::Mirror; + + auto create_compilation_unit() { + return details::try_unique( + get().create_compilation_unit() + ); + } + + auto write(const std::string& output) { + get().write(output); + } + + static auto from_binary(AbstractBinary& bin) { + return details::try_unique(lief_t::from_binary(bin.get())); + } + + static auto create(uint32_t fmt, uint32_t arch) { + return details::try_unique(lief_t::create((lief_t::FORMAT)fmt, + (lief_t::ARCH)arch)); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Function.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Function.hpp new file mode 100644 index 0000000..1589c3b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Function.hpp @@ -0,0 +1,185 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/Function.hpp" +#include "LIEF/rust/DWARF/LexicalBlock.hpp" +#include "LIEF/rust/DWARF/Parameter.hpp" +#include "LIEF/rust/DWARF/Scope.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/DWARF/Variable.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/debug_location.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/range.hpp" + +class DWARF_Function : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Function; + + class it_variables + : public ForwardIterator { + public: + it_variables(const DWARF_Function::lief_t& src) : + ForwardIterator(src.variables()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_parameters + : public ContainerIterator< + DWARF_Parameter, std::vector> + > { + public: + using container_t = std::vector>; + it_parameters(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + class it_thrown_types + : public ContainerIterator>> { + public: + using container_t = std::vector>; + it_thrown_types(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + class it_instructions + : public ForwardIterator { + public: + it_instructions(const DWARF_Function::lief_t& src) : + ForwardIterator(src.instructions()) {} + auto next() { + return ForwardIterator::next(); + } + }; + + class it_lexical_blocks + : public ForwardIterator { + public: + it_lexical_blocks(const DWARF_Function::lief_t& src) : + ForwardIterator(src.lexical_blocks()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto name() const { + return to_unique_string(get().name()); + } + auto linkage_name() const { + return to_unique_string(get().linkage_name()); + } + + auto variables() const { + return std::make_unique(get()); + } + + uint64_t address(uint32_t& err) const { + return details::make_error(get().address(), err); + } + + auto is_artificial() const { + return get().is_artificial(); + } + auto is_external() const { + return get().is_external(); + } + + auto size() const { + return get().size(); + } + auto ranges() const { + return make_unique_vector(details::make_range(get().ranges())); + } + auto debug_location() const { + return details::make_location(get().debug_location()); + } + + auto get_type() const { + return details::try_unique( + get().type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto parameters() const { + std::vector> params = + get().parameters(); + return std::make_unique(std::move(params)); + } + + auto thrown_types() const { + std::vector> types = get().thrown_types(); + return std::make_unique(std::move(types)); + } + + auto scope() const { + return details::try_unique( + get().scope() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto instructions() const { + return std::make_unique(get()); + } + + auto description() const { + return to_unique_string(get().description()); + } + + auto lexical_blocks() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; + +using DWARF_Function_it_variables = DWARF_Function::it_variables; +using DWARF_Function_it_parameters = DWARF_Function::it_parameters; +using DWARF_Function_it_thrown_types = DWARF_Function::it_thrown_types; +using DWARF_Function_it_instructions = DWARF_Function::it_instructions; +using DWARF_Function_it_lexical_blocks = DWARF_Function::it_lexical_blocks; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/LexicalBlock.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/LexicalBlock.hpp new file mode 100644 index 0000000..a261d96 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/LexicalBlock.hpp @@ -0,0 +1,75 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/LexicalBlock.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" +#include "LIEF/rust/range.hpp" + +class DWARF_LexicalBlock : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::LexicalBlock; + + class it_sub_blocks + : public ForwardIterator { + public: + it_sub_blocks(const DWARF_LexicalBlock::lief_t& src) : + ForwardIterator(src.sub_blocks()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto name() const { + return to_unique_string(get().name()); + } + + auto description() const { + return to_unique_string(get().description()); + } + + uint64_t addr(uint32_t& is_set) const { + return details::make_optional(get().addr(), is_set); + } + + uint64_t low_pc(uint32_t& is_set) const { + return details::make_optional(get().low_pc(), is_set); + } + + uint64_t high_pc(uint32_t& is_set) const { + return details::make_optional(get().high_pc(), is_set); + } + + auto size() const { + return get().size(); + } + + auto ranges() const { + return make_unique_vector(details::make_range(get().ranges())); + } + + auto sub_blocks() const { + return std::make_unique(get()); + } +}; + +using DWARF_LexicalBlock_it_sub_blocks = DWARF_LexicalBlock::it_sub_blocks; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Parameter.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Parameter.hpp new file mode 100644 index 0000000..2dc48aa --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Parameter.hpp @@ -0,0 +1,109 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/Parameter.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_Parameter_Location : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Parameter::Location; + + auto get_type() const { + return to_int(get().type); + } +}; + +class DWARF_Parameter_RegisterLocation + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Parameter::RegisterLoc; + + auto id() const { + return impl().id; + } + + static auto classof(const DWARF_Parameter_Location& loc) { + return lief_t::classof(&loc.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class DWARF_Parameter : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Parameter; + + auto name() const { + return to_unique_string(get().name()); + } + + auto get_type() const { + return details::try_unique(get().type()); + } + + auto location() const { + return details::try_unique(get().location()); + } +}; + +class DWARF_parameters_Formal : public DWARF_Parameter { + public: + using lief_t = LIEF::dwarf::parameters::Formal; + + static auto classof(const DWARF_Parameter& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class DWARF_parameters_TemplateValue : public DWARF_Parameter { + public: + using lief_t = LIEF::dwarf::parameters::TemplateValue; + + static auto classof(const DWARF_Parameter& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class DWARF_parameters_TemplateType : public DWARF_Parameter { + public: + using lief_t = LIEF::dwarf::parameters::TemplateType; + + static auto classof(const DWARF_Parameter& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Scope.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Scope.hpp new file mode 100644 index 0000000..a422661 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Scope.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/Scope.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_Scope : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Scope; + + auto name() const { + return to_unique_string(get().name()); + } + auto parent() const { + return details::try_unique(get().parent()); + } + auto get_type() const { + return as_u32(get().type()); + } + auto chained(const std::string& sep) const { + return to_unique_string(get().chained(sep)); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Type.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Type.hpp new file mode 100644 index 0000000..55d7ff2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Type.hpp @@ -0,0 +1,58 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/rust/DWARF/Scope.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/debug_location.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_Type : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Type; + + auto name(uint32_t& err) const { + return to_unique_string(details::make_error(get().name(), err)); + } + + uint64_t size(uint32_t& err) const { + return details::make_error(get().size(), err); + } + + auto location() const { + return details::make_location(get().location()); + } + + auto is_unspecified() const { + return get().is_unspecified(); + } + + auto scope() const { + return details::try_unique( + get().scope() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/Variable.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Variable.hpp new file mode 100644 index 0000000..be306ae --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/Variable.hpp @@ -0,0 +1,78 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/rust/DWARF/Scope.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/debug_location.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_Variable : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::Variable; + + auto name() const { + return to_unique_string(get().name()); + } + auto linkage_name() const { + return to_unique_string(get().linkage_name()); + } + + int64_t address(uint32_t& err) const { + return details::make_error(get().address(), err); + } + + uint64_t size(uint32_t& err) const { + return details::make_error(get().size(), err); + } + + auto debug_location() const { + return details::make_location(get().debug_location()); + } + + auto is_constexpr() const { + return get().is_constexpr(); + } + + auto is_stack_based() const { + return get().is_stack_based(); + } + + auto get_type() const { + return details::try_unique( + get().type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto scope() const { + return details::try_unique(get().scope()); + } + + auto description() const { + return to_unique_string(get().description()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/ArrayType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/ArrayType.hpp new file mode 100644 index 0000000..29adeae --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/ArrayType.hpp @@ -0,0 +1,32 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/ArrayType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + +class DWARF_editor_ArrayType : public DWARF_editor_Type { + public: + using DWARF_editor_Type::DWARF_editor_Type; + using lief_t = LIEF::dwarf::editor::ArrayType; + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/BaseType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/BaseType.hpp new file mode 100644 index 0000000..11bd820 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/BaseType.hpp @@ -0,0 +1,32 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/BaseType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + +class DWARF_editor_BaseType : public DWARF_editor_Type { + public: + using lief_t = LIEF::dwarf::editor::BaseType; + using DWARF_editor_Type::DWARF_editor_Type; + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/CompilationUnit.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/CompilationUnit.hpp new file mode 100644 index 0000000..09e8233 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/CompilationUnit.hpp @@ -0,0 +1,97 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Mirror.hpp" +#include + +#include "LIEF/rust/DWARF/editor/ArrayType.hpp" +#include "LIEF/rust/DWARF/editor/BaseType.hpp" +#include "LIEF/rust/DWARF/editor/EnumType.hpp" +#include "LIEF/rust/DWARF/editor/Function.hpp" +#include "LIEF/rust/DWARF/editor/FunctionType.hpp" +#include "LIEF/rust/DWARF/editor/PointerType.hpp" +#include "LIEF/rust/DWARF/editor/StructType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" +#include "LIEF/rust/DWARF/editor/TypeDef.hpp" +#include "LIEF/rust/DWARF/editor/Variable.hpp" + +class DWARF_editor_CompilationUnit + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::CompilationUnit; + + auto set_producer(const std::string& value) { + get().set_producer(value); + } + + auto create_function(const std::string& name) { + return details::try_unique(get().create_function(name)); + } + + auto create_variable(const std::string& name) { + return details::try_unique(get().create_variable(name)); + } + + auto create_generic_type(const std::string& name) { + return details::try_unique(get().create_generic_type(name)); + } + + auto create_enum(const std::string& name) { + return details::try_unique(get().create_enum(name)); + } + + auto create_typedef(const std::string& name, const DWARF_editor_Type& ty) { + return details::try_unique( + get().create_typedef(name, ty.get()) + ); + } + + auto create_structure(const std::string& name, uint32_t kind) { + return details::try_unique( + get().create_structure(name, (LIEF::dwarf::editor::StructType::TYPE)kind) + ); + } + + auto create_base_type(const std::string& name, uint64_t size, + uint32_t encoding) { + return details::try_unique(get().create_base_type( + name, size, (LIEF::dwarf::editor::BaseType::ENCODING)encoding + )); + } + + auto create_function_type(const std::string& name) { + return details::try_unique( + get().create_function_type(name) + ); + } + + auto create_pointer_type(const DWARF_editor_Type& ty) { + return details::try_unique( + get().create_pointer_type(ty.get()) + ); + } + + auto create_void_type() { + return details::try_unique(get().create_void_type()); + } + + auto create_array_type(const std::string& name, const DWARF_editor_Type& ty, + uint64_t count) { + return details::try_unique( + get().create_array(name, ty.get(), count) + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/EnumType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/EnumType.hpp new file mode 100644 index 0000000..e2f9268 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/EnumType.hpp @@ -0,0 +1,57 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/EnumType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + + +class DWARF_editor_EnumType_Value + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::EnumType::Value; +}; + +class DWARF_editor_EnumType : public DWARF_editor_Type { + public: + using DWARF_editor_Type::DWARF_editor_Type; + using lief_t = LIEF::dwarf::editor::EnumType; + + auto set_size(uint64_t size) { + impl().set_size(size); + } + + auto add_value(const std::string& name, int64_t value) { + return details::try_unique( + impl().add_value(name, value) + ); + } + + auto set_underlying_type(const DWARF_editor_Type& ty) { + impl().set_underlying_type(ty.get()); + } + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Function.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Function.hpp new file mode 100644 index 0000000..73d6c8e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Function.hpp @@ -0,0 +1,143 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Mirror.hpp" +#include +#include +#include + +#include "LIEF/rust/DWARF/editor/Type.hpp" +#include "LIEF/rust/DWARF/editor/Variable.hpp" + +class DWARF_editor_Function_Range { + public: + uint64_t start = 0; + uint64_t end = 0; +}; + +class DWARF_editor_Function_Parameter + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Function::Parameter; + + auto assign_register_by_name(const std::string& name) { + get().assign_register(name); + } + + auto assign_register_by_id(uint64_t id) { + get().assign_register(id); + } +}; + +class DWARF_editor_Function_LexicalBlock + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Function::LexicalBlock; + + auto add_block(uint64_t start, uint64_t end) { + return details::try_unique( + get().add_block(start, end) + ); + } + + auto add_block_from_range( + const std::vector& ranges + ) { + std::vector conv_ranges; + conv_ranges.reserve(ranges.size()); + std::transform(ranges.begin(), ranges.end(), std::back_inserter(conv_ranges), + [](const DWARF_editor_Function_Range& R) { + return LIEF::dwarf::editor::Function::range_t{R.start, R.end}; + }); + + return details::try_unique( + get().add_block(conv_ranges) + ); + } + + auto add_name(const std::string& name) { + get().add_name(name); + } + + auto add_description(const std::string& name) { + get().add_description(name); + } +}; + +class DWARF_editor_Function_Label + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Function::Label; +}; + +class DWARF_editor_Function : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Function; + + auto set_address(uint64_t addr) { + get().set_address(addr); + } + auto set_low_high(uint64_t low, uint64_t high) { + get().set_low_high(low, high); + } + auto set_ranges(const std::vector& ranges) { + std::vector conv_ranges; + conv_ranges.reserve(ranges.size()); + std::transform(ranges.begin(), ranges.end(), std::back_inserter(conv_ranges), + [](const DWARF_editor_Function_Range& R) { + return lief_t::range_t{R.start, R.end}; + }); + get().set_ranges(std::move(conv_ranges)); + } + auto set_external() { + get().set_external(); + } + + auto set_return_type(const DWARF_editor_Type& ty) { + get().set_return_type(ty.get()); + } + + auto add_parameter(const std::string& name, const DWARF_editor_Type& ty) { + return details::try_unique( + get().add_parameter(name, ty.get()) + ); + } + + auto create_stack_variable(const std::string& name) { + return details::try_unique( + get().create_stack_variable(name) + ); + } + + auto add_lexical_block(uint64_t start, uint64_t end) { + return details::try_unique( + get().add_lexical_block(start, end) + ); + } + + auto add_label(uint64_t addr, const std::string& label) { + return details::try_unique( + get().add_label(addr, label) + ); + } + + auto add_description(const std::string& desc) { + get().add_description(desc); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/FunctionType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/FunctionType.hpp new file mode 100644 index 0000000..28cdf72 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/FunctionType.hpp @@ -0,0 +1,53 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/FunctionType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + + +class DWARF_editor_FunctionType_Parameter + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::FunctionType::Parameter; +}; + +class DWARF_editor_FunctionType : public DWARF_editor_Type { + public: + using lief_t = LIEF::dwarf::editor::FunctionType; + using DWARF_editor_Type::DWARF_editor_Type; + + auto set_return_type(const DWARF_editor_Type& ty) { + impl().set_return_type(ty.get()); + } + + auto add_parameter(const DWARF_editor_Type& ty) { + return details::try_unique( + impl().add_parameter(ty.get()) + ); + } + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/PointerType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/PointerType.hpp new file mode 100644 index 0000000..f6b007a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/PointerType.hpp @@ -0,0 +1,36 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/PointerType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + +class DWARF_editor_PointerType : public DWARF_editor_Type { + public: + using DWARF_editor_Type::DWARF_editor_Type; + using lief_t = LIEF::dwarf::editor::PointerType; + + auto pointer_to() const { + return details::try_unique(get().pointer_to()); + } + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/StructType.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/StructType.hpp new file mode 100644 index 0000000..23fc613 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/StructType.hpp @@ -0,0 +1,75 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/StructType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + + +class DWARF_editor_StructType_Member + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::StructType::Member; +}; + +class DWARF_editor_StructType : public DWARF_editor_Type { + public: + using DWARF_editor_Type::DWARF_editor_Type; + using lief_t = LIEF::dwarf::editor::StructType; + + auto set_size(uint64_t size) { + impl().set_size(size); + } + + auto add_member(const std::string& name, const DWARF_editor_Type& ty) { + return details::try_unique( + impl().add_member(name, ty.get()) + ); + } + + auto add_member_with_offset(const std::string& name, const DWARF_editor_Type& ty, + uint64_t offset) { + return details::try_unique( + impl().add_member(name, ty.get(), offset) + ); + } + + auto add_bitfield(const std::string& name, const DWARF_editor_Type& ty, + uint64_t bitsize) { + return details::try_unique( + impl().add_bitfield(name, ty.get(), bitsize) + ); + } + + auto add_bitfield_with_offset(const std::string& name, + const DWARF_editor_Type& ty, uint64_t bitsize, + uint64_t offset) { + return details::try_unique( + impl().add_bitfield(name, ty.get(), bitsize, offset) + ); + } + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Type.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Type.hpp new file mode 100644 index 0000000..9463578 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Type.hpp @@ -0,0 +1,27 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/rust/Mirror.hpp" + +class DWARF_editor_PointerType; + +class DWARF_editor_Type : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Type; + + LIEF_API std::unique_ptr pointer_to() const; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/TypeDef.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/TypeDef.hpp new file mode 100644 index 0000000..55c2df2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/TypeDef.hpp @@ -0,0 +1,32 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/editor/TypeDef.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + +class DWARF_editor_TypeDef : public DWARF_editor_Type { + public: + using lief_t = LIEF::dwarf::editor::TypeDef; + using DWARF_editor_Type::DWARF_editor_Type; + + static auto classof(const DWARF_editor_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Variable.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Variable.hpp new file mode 100644 index 0000000..9acf3ba --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/editor/Variable.hpp @@ -0,0 +1,41 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/DWARF/editor/Type.hpp" +#include "LIEF/rust/Mirror.hpp" +#include + +class DWARF_editor_Variable : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::editor::Variable; + + auto set_external() { + get().set_external(); + } + auto set_addr(uint64_t addr) { + get().set_addr(addr); + } + auto set_stack_offset(uint64_t addr) { + get().set_stack_offset(addr); + } + auto set_type(const DWARF_editor_Type& ty) { + get().set_type(ty.get()); + } + + auto add_description(const std::string& desc) { + get().add_description(desc); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Array.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Array.hpp new file mode 100644 index 0000000..9ed23bb --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Array.hpp @@ -0,0 +1,63 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Array.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_types_array_size_info + : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::types::Array::size_info_t; + + auto name() const { + return to_unique_string(get().name); + } + + uint64_t size() const { + return get().size; + } + + auto get_type() const { + return details::try_unique( + get().type.get() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } +}; + +class DWARF_types_Array : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Array; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto size_info() const { + return std::make_unique(impl().size_info()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Atomic.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Atomic.hpp new file mode 100644 index 0000000..c8cbec9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Atomic.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Atomic.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Atomic : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Atomic; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Base.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Base.hpp new file mode 100644 index 0000000..c0b62df --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Base.hpp @@ -0,0 +1,36 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Base.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_types_Base : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Base; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto encoding() const { + return as_u32(impl().encoding()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/ClassLike.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/ClassLike.hpp new file mode 100644 index 0000000..f0e98c3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/ClassLike.hpp @@ -0,0 +1,157 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/ClassLike.hpp" +#include "LIEF/rust/DWARF/Function.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class DWARF_types_ClassLike_Member + : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::types::ClassLike::Member; + + auto name() const { + return to_unique_string(get().name()); + } + + uint64_t bit_offset(uint32_t& err) const { + return details::make_error(get().bit_offset(), err); + } + + uint64_t bit_size(uint32_t& err) const { + return details::make_error(get().bit_size(), err); + } + + uint64_t offset(uint32_t& err) const { + return details::make_error(get().offset(), err); + } + + auto is_declaration() const { + return get().is_declaration(); + } + + auto is_external() const { + return get().is_external(); + } + + auto get_type() const { + return details::try_unique( + get().type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } +}; + + +class DWARF_types_ClassLike : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::ClassLike; + + class it_members : public ContainerIterator< + DWARF_types_ClassLike_Member, + std::vector + > { + public: + using container_t = std::vector; + it_members(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + class it_functions + : public ForwardIterator { + public: + it_functions(const DWARF_types_ClassLike::lief_t& src) : + ForwardIterator(src.functions()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto find_member(uint64_t offset) const { + return details::try_unique( + impl().find_member(offset) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto members() const { + std::vector members = impl().members(); + return std::make_unique(std::move(members)); + } + + auto functions() const { + return std::make_unique(impl()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using DWARF_types_ClassLike_it_members = DWARF_types_ClassLike::it_members; +using DWARF_types_ClassLike_it_functions = DWARF_types_ClassLike::it_functions; + +class DWARF_types_Structure : public DWARF_types_ClassLike { + public: + using lief_t = LIEF::dwarf::types::Structure; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } +}; + +class DWARF_types_Class : public DWARF_types_ClassLike { + public: + using lief_t = LIEF::dwarf::types::Class; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } +}; + +class DWARF_types_Union : public DWARF_types_ClassLike { + public: + using lief_t = LIEF::dwarf::types::Union; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } +}; + +class DWARF_types_Packed : public DWARF_types_ClassLike { + public: + using lief_t = LIEF::dwarf::types::Packed; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Coarray.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Coarray.hpp new file mode 100644 index 0000000..894de36 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Coarray.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Coarray.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Coarray : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Coarray; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Const.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Const.hpp new file mode 100644 index 0000000..5383216 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Const.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Const.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Const : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Const; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Dynamic.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Dynamic.hpp new file mode 100644 index 0000000..4fd9e4d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Dynamic.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Dynamic.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Dynamic : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Dynamic; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Enum.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Enum.hpp new file mode 100644 index 0000000..2756a1a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Enum.hpp @@ -0,0 +1,83 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Enum.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" + +class DWARF_types_Enum_Entry : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::dwarf::types::Enum::Entry; + + auto name() const { + return to_unique_string(get().name()); + } + + int64_t value(uint32_t& is_set) const { + return details::make_optional(get().value(), is_set); + } +}; + +class DWARF_types_Enum : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Enum; + + class it_entries + : public ContainerIterator> { + public: + using container_t = std::vector; + it_entries(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto entries() const { + std::vector entries = impl().entries(); + return std::make_unique(std::move(entries)); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + std::unique_ptr find_entry(int64_t value) const { + if (auto entry = impl().find_entry(value)) { + return std::make_unique(*entry); + } + return nullptr; + } + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using DWARF_types_Enum_it_entries = DWARF_types_Enum::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/File.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/File.hpp new file mode 100644 index 0000000..0a86fa1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/File.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/File.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_File : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::File; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Immutable.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Immutable.hpp new file mode 100644 index 0000000..ba1f634 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Immutable.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Immutable.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Immutable : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Immutable; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Interface.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Interface.hpp new file mode 100644 index 0000000..a11d839 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Interface.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Interface.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Interface : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Interface; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Pointer.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Pointer.hpp new file mode 100644 index 0000000..ba8b2d3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Pointer.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Pointer.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Pointer : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Pointer; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/PointerToMember.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/PointerToMember.hpp new file mode 100644 index 0000000..26f653e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/PointerToMember.hpp @@ -0,0 +1,43 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/PointerToMember.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_PointerToMember : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::PointerToMember; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto containing_type() const { + return details::try_unique( + impl().containing_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/RValueRef.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/RValueRef.hpp new file mode 100644 index 0000000..40e5891 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/RValueRef.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/RValueRef.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_RValueReference : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::RValueReference; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Reference.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Reference.hpp new file mode 100644 index 0000000..3f6524d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Reference.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Reference.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Reference : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Reference; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Restrict.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Restrict.hpp new file mode 100644 index 0000000..0d201b9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Restrict.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Restrict.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Restrict : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Restrict; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/SetTy.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/SetTy.hpp new file mode 100644 index 0000000..ddaa6ea --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/SetTy.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/SetTy.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_SetTy : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::SetTy; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Shared.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Shared.hpp new file mode 100644 index 0000000..844dd4d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Shared.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Shared.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Shared : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Shared; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/StringTy.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/StringTy.hpp new file mode 100644 index 0000000..056248a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/StringTy.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/StringTy.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_StringTy : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::StringTy; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Subroutine.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Subroutine.hpp new file mode 100644 index 0000000..4e10630 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Subroutine.hpp @@ -0,0 +1,61 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Subroutine.hpp" +#include "LIEF/rust/DWARF/Parameter.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/Iterator.hpp" + +class DWARF_types_Subroutine : public DWARF_Type { + public: + class it_parameters + : public ContainerIterator< + DWARF_Parameter, std::vector> + > { + public: + using container_t = std::vector>; + it_parameters(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + using lief_t = LIEF::dwarf::types::Subroutine; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto return_type() const { + return details::try_unique( + impl().return_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto parameters() const { + return std::make_unique(impl().parameters()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using DWARF_types_Subroutine_it_parameters = DWARF_types_Subroutine::it_parameters; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/TemplateAlias.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/TemplateAlias.hpp new file mode 100644 index 0000000..29d848e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/TemplateAlias.hpp @@ -0,0 +1,62 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/TemplateAlias.hpp" +#include "LIEF/rust/DWARF/Parameter.hpp" +#include "LIEF/rust/DWARF/Type.hpp" +#include "LIEF/rust/Iterator.hpp" + +class DWARF_types_TemplateAlias : public DWARF_Type { + public: + class it_parameters + : public ContainerIterator< + DWARF_Parameter, std::vector> + > { + public: + using container_t = std::vector>; + it_parameters(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + using lief_t = LIEF::dwarf::types::TemplateAlias; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto parameters() const { + return std::make_unique(impl().parameters()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using DWARF_types_TemplateAlias_it_parameters = + DWARF_types_TemplateAlias::it_parameters; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Thrown.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Thrown.hpp new file mode 100644 index 0000000..78934cb --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Thrown.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Thrown.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Thrown : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Thrown; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Typedef.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Typedef.hpp new file mode 100644 index 0000000..5cf95b5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Typedef.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Typedef.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Typedef : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Typedef; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Volatile.hpp b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Volatile.hpp new file mode 100644 index 0000000..4e5425b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DWARF/types/Volatile.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DWARF/types/Volatile.hpp" +#include "LIEF/rust/DWARF/Type.hpp" + +class DWARF_types_Volatile : public DWARF_Type { + public: + using lief_t = LIEF::dwarf::types::Volatile; + + static auto classof(const DWARF_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DebugDeclOpt.hpp b/vendor/lief/api/rust/include/LIEF/rust/DebugDeclOpt.hpp new file mode 100644 index 0000000..4f0607c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DebugDeclOpt.hpp @@ -0,0 +1,59 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include + +class LIEF_DeclOpt { + public: + static auto create() { + return std::make_unique(); + } + + const LIEF::DeclOpt& conf() const { + return config_; + } + + void set_indentation(uint32_t value) { + config_.indentation(value); + } + + void set_is_cpp(bool value) { + config_.is_cpp(value); + } + + void set_show_extended_annotations(bool value) { + config_.show_extended_annotations(value); + } + + void set_include_types(bool value) { + config_.include_types(value); + } + + void set_include_locals(bool value) { + config_.include_locals(value); + } + + void set_desugar(bool value) { + config_.desugar(value); + } + + void set_show_field_offsets(bool value) { + config_.show_field_offsets(value); + } + + private: + LIEF::DeclOpt config_; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache.hpp new file mode 100644 index 0000000..800f7b1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache.hpp @@ -0,0 +1,21 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/DyldSharedCache/DyldSharedCache.hpp" +#include "LIEF/rust/DyldSharedCache/Dylib.hpp" +#include "LIEF/rust/DyldSharedCache/MappingInfo.hpp" +#include "LIEF/rust/DyldSharedCache/SubCache.hpp" +#include "LIEF/rust/DyldSharedCache/caching.hpp" +#include "LIEF/rust/DyldSharedCache/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/DyldSharedCache.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/DyldSharedCache.hpp new file mode 100644 index 0000000..068f118 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/DyldSharedCache.hpp @@ -0,0 +1,182 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DyldSharedCache/DyldSharedCache.hpp" +#include "LIEF/rust/DyldSharedCache/Dylib.hpp" +#include "LIEF/rust/DyldSharedCache/MappingInfo.hpp" +#include "LIEF/rust/DyldSharedCache/SubCache.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class dsc_DyldSharedCache : private Mirror { + public: + using lief_t = LIEF::dsc::DyldSharedCache; + using Mirror::Mirror; + + class it_libraries + : public RandomRangeIterator { + public: + it_libraries(const dsc_DyldSharedCache::lief_t& src) : + RandomRangeIterator(src.libraries()) {} + auto next() { + return RandomRangeIterator::next(); + } + auto size() const { + return RandomRangeIterator::size(); + } + }; + + class it_mapping_info + : public RandomRangeIterator { + public: + it_mapping_info(const dsc_DyldSharedCache::lief_t& src) : + RandomRangeIterator(src.mapping_info()) {} + auto next() { + return RandomRangeIterator::next(); + } + auto size() const { + return RandomRangeIterator::size(); + } + }; + + class it_subcaches + : public RandomRangeIterator { + public: + it_subcaches(const dsc_DyldSharedCache::lief_t& src) : + RandomRangeIterator(src.subcaches()) {} + auto next() { + return RandomRangeIterator::next(); + } + auto size() const { + return RandomRangeIterator::size(); + } + }; + + class it_instructions + : public ForwardIterator { + public: + it_instructions(const dsc_DyldSharedCache::lief_t& src, uint64_t addr) : + ForwardIterator(src.disassemble(addr)) {} + auto next() { + return ForwardIterator::next(); + } + }; + + static auto from_path(const std::string& file, const std::string& arch) { + return details::try_unique( + LIEF::dsc::DyldSharedCache::from_path(file, arch) + ); + } + + static auto from_files(const char* ptr, size_t size) { + const auto* files = (const char* const*)ptr; + std::vector files_vec; + files_vec.reserve(size); + for (size_t i = 0; i < size; ++i) { + files_vec.push_back(files[i]); + } + return details::try_unique( + LIEF::dsc::DyldSharedCache::from_files(files_vec) + ); + } + + auto libraries() const { + return std::make_unique(get()); + } + auto mapping_info() const { + return std::make_unique(get()); + } + auto subcaches() const { + return std::make_unique(get()); + } + + auto filename() const { + return to_unique_string(get().filename()); + } + auto version() const { + return as_u32(get().version()); + } + auto filepath() const { + return to_unique_string(get().filepath()); + } + auto load_address() const { + return get().load_address(); + } + + auto arch_name() const { + return to_unique_string(get().arch_name()); + } + auto platform() const { + return as_u32(get().platform()); + } + auto arch() const { + return as_u32(get().arch()); + } + auto has_subcaches() const { + return get().has_subcaches(); + } + + auto find_lib_from_va(uint64_t va) const { + return details::try_unique(get().find_lib_from_va(va)); + } + + auto find_lib_from_path(const std::string& path) const { + return details::try_unique(get().find_lib_from_path(path)); + } + + auto find_lib_from_name(const std::string& name) const { + return details::try_unique(get().find_lib_from_name(name)); + } + + auto enable_caching(const std::string& dir) const { + get().enable_caching(dir); + } + auto flush_cache() const { + get().flush_cache(); + } + + auto disassemble(uint64_t addr) const { + return std::make_unique(get(), addr); + } + + auto cache_for_address(uint64_t addr) const { + return details::try_unique(get().cache_for_address(addr)); + } + + auto main_cache() const { + return details::try_unique(get().main_cache()); + } + + auto find_subcache(const std::string& filename) const { + return details::try_unique(get().find_subcache(filename)); + } + + uint64_t va_to_offset(uint64_t va, uint32_t& err) const { + return details::make_error(get().va_to_offset(va), err); + } + + auto get_content_from_va(uint64_t va, uint64_t size) const { + return make_unique_vector(get().get_content_from_va(va, size)); + } +}; + +using dsc_DyldSharedCache_it_libraries = dsc_DyldSharedCache::it_libraries; +using dsc_DyldSharedCache_it_mapping_info = dsc_DyldSharedCache::it_mapping_info; +using dsc_DyldSharedCache_it_subcaches = dsc_DyldSharedCache::it_subcaches; +using dsc_DyldSharedCache_it_instructions = dsc_DyldSharedCache::it_instructions; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/Dylib.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/Dylib.hpp new file mode 100644 index 0000000..577cfe3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/Dylib.hpp @@ -0,0 +1,72 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DyldSharedCache/Dylib.hpp" +#include "LIEF/rust/MachO/Binary.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class dsc_Dylib_extract_opt { + public: + bool pack = true; + bool fix_branches = false; + bool fix_memory = false; + bool fix_relocations = false; + bool fix_objc = false; + + bool create_dyld_chained_fixup_cmd = false; + bool create_dyld_chained_fixup_cmd_set = false; +}; + +inline LIEF::dsc::Dylib::extract_opt_t + from_rust(const dsc_Dylib_extract_opt& opt) { + LIEF::dsc::Dylib::extract_opt_t out; + + out.pack = opt.pack; + out.fix_branches = opt.fix_branches; + out.fix_memory = opt.fix_memory; + out.fix_relocations = opt.fix_relocations; + out.fix_objc = opt.fix_objc; + if (opt.create_dyld_chained_fixup_cmd_set) { + out.create_dyld_chained_fixup_cmd = opt.create_dyld_chained_fixup_cmd; + } + return out; +} + +class dsc_Dylib : private Mirror { + public: + using lief_t = LIEF::dsc::Dylib; + using Mirror::Mirror; + + auto path() const { + return to_unique_string(get().path()); + } + auto address() const { + return get().address(); + } + auto modtime() const { + return get().modtime(); + } + auto inode() const { + return get().inode(); + } + auto padding() const { + return get().padding(); + } + + auto get_macho(const dsc_Dylib_extract_opt& opt) const { + return details::try_unique(get().get(from_rust(opt))); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/MappingInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/MappingInfo.hpp new file mode 100644 index 0000000..67ea663 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/MappingInfo.hpp @@ -0,0 +1,42 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DyldSharedCache/MappingInfo.hpp" +#include "LIEF/rust/Mirror.hpp" + +class dsc_MappingInfo : private Mirror { + public: + using lief_t = LIEF::dsc::MappingInfo; + using Mirror::Mirror; + + auto address() const { + return get().address(); + } + auto size() const { + return get().size(); + } + auto end_address() const { + return get().end_address(); + } + auto file_offset() const { + return get().file_offset(); + } + auto max_prot() const { + return get().max_prot(); + } + auto init_prot() const { + return get().init_prot(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/SubCache.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/SubCache.hpp new file mode 100644 index 0000000..1bbf071 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/SubCache.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/DyldSharedCache/SubCache.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class dsc_DyldSharedCache; + +class dsc_SubCache : private Mirror { + public: + using lief_t = LIEF::dsc::SubCache; + using Mirror::Mirror; + + auto vm_offset() const { + return get().vm_offset(); + } + auto suffix() const { + return to_unique_string(get().suffix()); + } + auto uuid() const { + return make_unique_vector(details::make_vector(get().uuid())); + } + LIEF_API std::unique_ptr cache() const; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/caching.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/caching.hpp new file mode 100644 index 0000000..9421091 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/caching.hpp @@ -0,0 +1,10 @@ +#pragma once +#include "LIEF/DyldSharedCache/caching.hpp" + +inline bool dsc_enable_cache() { + return LIEF::dsc::enable_cache(); +} + +inline bool dsc_enable_cache_from_dir(const std::string& dir) { + return LIEF::dsc::enable_cache(dir); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/utils.hpp new file mode 100644 index 0000000..549b3de --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/DyldSharedCache/utils.hpp @@ -0,0 +1,25 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/DyldSharedCache/utils.hpp" +#include + +class dsc_Utils { + public: + static auto is_shared_cache(const std::string& file) { + return LIEF::dsc::is_shared_cache(file); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF.hpp new file mode 100644 index 0000000..7997ea6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/ELF/Binary.hpp" +#include "LIEF/rust/ELF/CoreAuxv.hpp" +#include "LIEF/rust/ELF/CoreFile.hpp" +#include "LIEF/rust/ELF/CorePrPsInfo.hpp" +#include "LIEF/rust/ELF/CorePrStatus.hpp" +#include "LIEF/rust/ELF/CoreSigInfo.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" +#include "LIEF/rust/ELF/DynamicEntryArray.hpp" +#include "LIEF/rust/ELF/DynamicEntryAuxiliary.hpp" +#include "LIEF/rust/ELF/DynamicEntryFilter.hpp" +#include "LIEF/rust/ELF/DynamicEntryFlags.hpp" +#include "LIEF/rust/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/rust/ELF/DynamicEntryRpath.hpp" +#include "LIEF/rust/ELF/DynamicEntryRunPath.hpp" +#include "LIEF/rust/ELF/DynamicSharedObject.hpp" +#include "LIEF/rust/ELF/NoteAbi.hpp" +#include "LIEF/rust/ELF/NoteAndroidIdent.hpp" +#include "LIEF/rust/ELF/NoteGnuProperty.hpp" +#include "LIEF/rust/ELF/NoteQNXStack.hpp" +#include "LIEF/rust/ELF/Section.hpp" +#include "LIEF/rust/ELF/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Binary.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Binary.hpp new file mode 100644 index 0000000..d472c9d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Binary.hpp @@ -0,0 +1,846 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include + +#include "LIEF/rust/Abstract/Binary.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" +#include "LIEF/rust/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/rust/ELF/GnuHash.hpp" +#include "LIEF/rust/ELF/Header.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/ELF/Relocation.hpp" +#include "LIEF/rust/ELF/Section.hpp" +#include "LIEF/rust/ELF/Segment.hpp" +#include "LIEF/rust/ELF/Symbol.hpp" +#include "LIEF/rust/ELF/SymbolVersion.hpp" +#include "LIEF/rust/ELF/SymbolVersionDefinition.hpp" +#include "LIEF/rust/ELF/SymbolVersionRequirement.hpp" +#include "LIEF/rust/ELF/Sysvhash.hpp" +#include "LIEF/rust/Iterator.hpp" + +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_Binary_write_config_t { + public: + bool dt_hash = true; + bool dyn_str = true; + bool dynamic_section = true; + bool fini_array = true; + bool gnu_hash = true; + bool init_array = true; + bool interpreter = true; + bool jmprel = true; + bool notes = true; + bool preinit_array = true; + bool relr = true; + bool android_rela = true; + bool rela = true; + bool static_symtab = true; + bool sym_verdef = true; + bool sym_verneed = true; + bool sym_versym = true; + bool symtab = true; + bool coredump_notes = true; + bool force_relocate = false; + bool keep_empty_version_requirement = false; + bool skip_dynamic = false; +}; + +class ELF_ParserConfig { + public: + static auto create() { + return std::make_unique(); + } + + const LIEF::ELF::ParserConfig& conf() const { + return config_; + } + + auto set_parse_relocations(bool value) { + config_.parse_relocations = value; + } + + auto set_parse_dyn_symbols(bool value) { + config_.parse_dyn_symbols = value; + } + + auto set_parse_symtab_symbols(bool value) { + config_.parse_symtab_symbols = value; + } + + auto set_parse_symbol_versions(bool value) { + config_.parse_symbol_versions = value; + } + + auto set_parse_notes(bool value) { + config_.parse_notes = value; + } + + auto set_parse_overlay(bool value) { + config_.parse_overlay = value; + } + + auto set_count_mtd(uint32_t value) { + config_.count_mtd = (LIEF::ELF::ParserConfig::DYNSYM_COUNT)value; + } + + auto set_page_size(uint64_t value) { + config_.page_size = value; + } + + private: + LIEF::ELF::ParserConfig config_; +}; + + +class ELF_Binary : public AbstractBinary { + public: + using lief_t = LIEF::ELF::Binary; + ELF_Binary(std::unique_ptr bin) : + AbstractBinary(std::move(bin)) {} + + static auto parse(const std::string& path) { + return details::try_unique(LIEF::ELF::Parser::parse(path)); + } + + static auto parse_with_config(const std::string& path, + const ELF_ParserConfig& config) { + return details::try_unique( + LIEF::ELF::Parser::parse(path, config.conf()) + ); + } + + static auto parse_from_dump(const std::string& path, uint64_t addr) { + return details::try_unique( + LIEF::ELF::Parser::parse_from_dump(path, addr) + ); + } + + static auto parse_from_dump_with_config(const std::string& path, uint64_t addr, + const ELF_ParserConfig& config) { + return details::try_unique( + LIEF::ELF::Parser::parse_from_dump(path, addr, config.conf()) + ); + } + + class it_sections + : public Iterator { + public: + it_sections(const ELF_Binary::lief_t& src) : + Iterator(src.sections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_segments + : public Iterator { + public: + it_segments(const ELF_Binary::lief_t& src) : + Iterator(src.segments()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_dynamic_entries + : public Iterator { + public: + it_dynamic_entries(const ELF_Binary::lief_t& src) : + Iterator(src.dynamic_entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_dynamic_symbols + : public Iterator { + public: + it_dynamic_symbols(const ELF_Binary::lief_t& src) : + Iterator(src.dynamic_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_exported_symbols + : public Iterator { + public: + it_exported_symbols(const ELF_Binary::lief_t& src) : + Iterator(src.exported_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_imported_symbols + : public Iterator { + public: + it_imported_symbols(const ELF_Binary::lief_t& src) : + Iterator(src.imported_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_notes : public Iterator { + public: + it_notes(const ELF_Binary::lief_t& src) : + Iterator(src.notes()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symtab_symbols + : public Iterator { + public: + it_symtab_symbols(const ELF_Binary::lief_t& src) : + Iterator(src.symtab_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_relocations + : public Iterator { + public: + it_relocations(const ELF_Binary::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_pltgot_relocations + : public Iterator { + public: + it_pltgot_relocations(const ELF_Binary::lief_t& src) : + Iterator(src.pltgot_relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_dynamic_relocations + : public Iterator { + public: + it_dynamic_relocations(const ELF_Binary::lief_t& src) : + Iterator(src.dynamic_relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_object_relocations + : public Iterator { + public: + it_object_relocations(const ELF_Binary::lief_t& src) : + Iterator(src.object_relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols_version + : public Iterator { + public: + it_symbols_version(const ELF_Binary::lief_t& src) : + Iterator(src.symbols_version()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols_version_requirement + : public Iterator { + public: + it_symbols_version_requirement(const ELF_Binary::lief_t& src) : + Iterator(src.symbols_version_requirement()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols_version_definition + : public Iterator { + public: + it_symbols_version_definition(const ELF_Binary::lief_t& src) : + Iterator(src.symbols_version_definition()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols + : public Iterator { + public: + it_symbols(const ELF_Binary::lief_t& src) : + Iterator(src.symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto header() const { + return std::make_unique(impl().header()); + } + + auto gnu_hash() const { + return details::try_unique( + impl().gnu_hash() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto sysv_hash() const { + return details::try_unique( + impl().sysv_hash() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto sections() const { + return std::make_unique(impl()); + } + + auto segments() const { + return std::make_unique(impl()); + } + + auto dynamic_entries() const { + return std::make_unique(impl()); + } + + auto remove_dynamic_entries_by_tag(uint64_t tag) { + impl().remove(LIEF::ELF::DynamicEntry::TAG(tag)); + } + + auto remove_dynamic_entry(const ELF_DynamicEntry& entry) { + impl().remove(entry.get()); + } + + auto remove_dynamic_entry_from_ptr(const LIEF::ELF::DynamicEntry* ptr) { + assert(ptr != nullptr); + impl().remove(*ptr); + } + + auto add_dynamic_entry(const ELF_DynamicEntry& entry) { + return std::make_unique(impl().add(entry.get())); + } + + auto dynamic_symbols() const { + return std::make_unique(impl()); + } + + auto exported_symbols() const { + return std::make_unique(impl()); + } + + auto imported_symbols() const { + return std::make_unique(impl()); + } + + auto symtab_symbols() const { + return std::make_unique(impl()); + } + + auto notes() const { + return std::make_unique(impl()); + } + + auto relocations() const { + return std::make_unique(impl()); + } + + auto pltgot_relocations() const { + return std::make_unique(impl()); + } + + auto dynamic_relocations() const { + return std::make_unique(impl()); + } + + auto object_relocations() const { + return std::make_unique(impl()); + } + + auto symbols_version() const { + return std::make_unique(impl()); + } + + auto symbols_version_requirement() const { + return std::make_unique(impl()); + } + + auto symbols_version_definition() const { + return std::make_unique(impl()); + } + + auto section_by_name(const std::string& name) const { + return details::try_unique(impl().get_section(name)); + } + + auto relocation_by_addr(uint64_t addr) const { + return details::try_unique(impl().get_relocation(addr)); + } + + auto relocation_for_symbol(const std::string& name) const { + return details::try_unique(impl().get_relocation(name)); + } + + auto get_dynamic_symbol(const std::string& name) const { + return details::try_unique(impl().get_dynamic_symbol(name)); + } + + auto get_symtab_symbol(const std::string& name) const { + return details::try_unique(impl().get_symtab_symbol(name)); + } + + auto get_library(const std::string& name) const { + return details::try_unique(impl().get_library(name)); + } + + auto section_from_offset(uint64_t offset, bool skip_nobits) const { + return details::try_unique( + impl().section_from_offset(offset, skip_nobits) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto section_from_virtual_address(uint64_t address, bool skip_nobits) const { + return details::try_unique( + impl().section_from_virtual_address(address, skip_nobits) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto segment_from_virtual_address(uint64_t address) const { + return details::try_unique( + impl().segment_from_virtual_address(address) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto segment_from_offset(uint64_t offset) const { + return details::try_unique( + impl().segment_from_offset(offset) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + Span get_content_from_virtual_address(uint64_t virtual_address, + uint64_t size) const { + return make_span(impl().get_content_from_virtual_address(virtual_address, + size)); + } + + uint64_t virtual_address_to_offset(uint64_t virtual_address, + uint32_t& error) const { + return details::make_error( + impl().virtual_address_to_offset(virtual_address), error + ); + } + + auto interpreter() const { + return to_unique_string(impl().interpreter()); + } + + auto set_interpreter(const std::string& name) { + impl().interpreter(name); + } + + auto get_relocated_dynamic_array(uint64_t tag) const { + return make_unique_vector( + impl().get_relocated_dynamic_array(LIEF::ELF::DynamicEntry::TAG(tag)) + ); + } + + auto is_targeting_android() const { + return impl().is_targeting_android(); + } + + auto add_library(const std::string& library) { + return std::make_unique(impl().add_library(library)); + } + + auto functions() const { + return std::make_unique(impl().functions()); + } + + auto dynamic_entry_by_tag(uint64_t tag) const { + return details::try_unique( + impl().get((LIEF::ELF::DynamicEntry::TAG)tag) + ); + } + + auto segment_by_type(uint64_t ty) const { + return details::try_unique( + impl().get((LIEF::ELF::Segment::TYPE)ty) + ); + } + + auto remove_library(const std::string& name) { + impl().remove_library(name); + } + + auto add_segment(const ELF_Segment& segment) { + return details::try_unique(impl().add(segment.get())); + } + + auto find_version_requirement(const std::string& libname) const { + return details::try_unique( + impl().find_version_requirement(libname) + ); + } + + auto remove_version_requirement(const std::string& libname) { + return impl().remove_version_requirement(libname); + } + + auto remove_segment(const ELF_Segment& segment, bool clear) { + impl().remove(segment.get(), clear); + } + + auto remove_segments_by_type(uint64_t ty, bool clear) { + impl().remove(LIEF::ELF::Segment::TYPE(ty), clear); + } + + auto symbols() const { + return std::make_unique(impl()); + } + + auto strings(uint64_t min_size) const { + return make_unique_vector(impl().strings(min_size)); + } + + auto last_offset_section() const { + return impl().last_offset_section(); + } + auto last_offset_segment() const { + return impl().last_offset_segment(); + } + auto next_virtual_address() const { + return impl().next_virtual_address(); + } + auto eof_offset() const { + return impl().eof_offset(); + } + + auto dtor_functions() const { + return std::make_unique(impl().dtor_functions()); + } + + Span get_overlay() const { + return make_span(impl().overlay()); + } + + auto set_overlay(const uint8_t* data, uint64_t size) { + impl().overlay(std::vector(data, data + size)); + } + + auto has_dynamic_entry_tag(uint64_t tag) const { + return impl().has(LIEF::ELF::DynamicEntry::TAG(tag)); + } + + auto has_segment_type(uint64_t ty) const { + return impl().has(LIEF::ELF::Segment::TYPE(ty)); + } + + auto has_note_type(uint32_t ty) const { + return impl().has(LIEF::ELF::Note::TYPE(ty)); + } + + auto has_section_type(uint64_t ty) const { + return impl().has(LIEF::ELF::Section::TYPE(ty)); + } + + auto get_note_by_type(uint32_t ty) const { + return details::try_unique(impl().get(LIEF::ELF::Note::TYPE(ty))); + } + + auto get_section_by_type(uint64_t ty) const { + return details::try_unique( + impl().get(LIEF::ELF::Section::TYPE(ty)) + ); + } + + auto has_section(const std::string& name) const { + return impl().has_section(name); + } + + auto has_section_with_offset(uint64_t offset) const { + return impl().has_section_with_offset(offset); + } + + auto has_section_with_va(uint64_t va) const { + return impl().has_section_with_va(va); + } + + auto has_library(const std::string& name) const { + return impl().has_library(name); + } + + auto has_dynamic_symbol(const std::string& name) const { + return impl().has_dynamic_symbol(name); + } + + auto has_symtab_symbol(const std::string& name) const { + return impl().has_symtab_symbol(name); + } + + int64_t dynsym_idx(const std::string& name) const { + return impl().dynsym_idx(name); + } + + int64_t symtab_idx(const std::string& name) const { + return impl().symtab_idx(name); + } + + auto patch_pltgot_by_name(const std::string& symbol_name, uint64_t address) { + impl().patch_pltgot(symbol_name, address); + } + + auto add_section(const ELF_Section& section, bool loaded, uint32_t pos) { + return details::try_unique( + impl().add(as(§ion), loaded, + LIEF::ELF::Binary::SEC_INSERT_POS(pos)) + ); + } + + auto add_note(const ELF_Note& note) { + return std::make_unique(impl().add(note.get())); + } + + auto add_dynamic_relocation(const ELF_Relocation& reloc) { + return std::make_unique( + impl().add_dynamic_relocation(as(&reloc)) + ); + } + + auto add_pltgot_relocation(const ELF_Relocation& reloc) { + return std::make_unique( + impl().add_pltgot_relocation(as(&reloc)) + ); + } + + auto add_symtab_symbol(const ELF_Symbol& symbol) { + return std::make_unique( + impl().add_symtab_symbol(as(&symbol)) + ); + } + + auto add_dynamic_symbol(const ELF_Symbol& symbol) { + return std::make_unique( + impl().add_dynamic_symbol(as(&symbol)) + ); + } + + auto add_exported_function(uint64_t address, const std::string& name) { + return std::make_unique(impl().add_exported_function(address, + name)); + } + + auto export_symbol_by_name(const std::string& symbol_name, uint64_t value) { + return std::make_unique(impl().export_symbol(symbol_name, value)); + } + + auto export_symbol_obj(const ELF_Symbol& symbol) { + return std::make_unique( + impl().export_symbol(as(&symbol)) + ); + } + + auto remove_symtab_symbol_by_name(const std::string& name) { + impl().remove_symtab_symbol(name); + } + + auto remove_dynamic_symbol_by_name(const std::string& name) { + impl().remove_dynamic_symbol(name); + } + + auto remove_section(const ELF_Section& section, bool clear) { + impl().remove(as(§ion), clear); + } + + auto remove_note(const ELF_Note& note) { + impl().remove(note.get()); + } + + auto extend_segment(const ELF_Segment& segment, uint64_t size) { + return details::try_unique(impl().extend(segment.get(), size)); + } + + auto extend_section(const ELF_Section& section, uint64_t size) { + return details::try_unique( + impl().extend(as(§ion), size) + ); + } + + auto strip() { + impl().strip(); + } + + + int64_t get_section_idx_by_name(const std::string& name) const { + if (auto res = impl().get_section_idx(name)) { + return static_cast(*res); + } + return -1; + } + + int64_t get_section_idx_by_section(const ELF_Section& section) const { + if (auto res = impl().get_section_idx(as(§ion))) { + return *res; + } + return -1; + } + + uint64_t relocate_phdr_table(uint32_t type) { + return impl().relocate_phdr_table(LIEF::ELF::Binary::PHDR_RELOC(type)); + } + + auto write(const std::string& output) { + impl().write(output); + } + void write_with_config(const std::string& output, + const ELF_Binary_write_config_t& config) { + impl().write(output, to_builder_config(config)); + } + + auto write_to_bytes() { + std::ostringstream os; + impl().write(os); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + auto write_to_bytes_with_config(const ELF_Binary_write_config_t& config) { + std::ostringstream os; + impl().write(os, to_builder_config(config)); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + private: + static LIEF::ELF::Builder::config_t + to_builder_config(const ELF_Binary_write_config_t& config) { + LIEF::ELF::Builder::config_t out; + out.dt_hash = config.dt_hash; + out.dyn_str = config.dyn_str; + out.dynamic_section = config.dynamic_section; + out.fini_array = config.fini_array; + out.gnu_hash = config.gnu_hash; + out.init_array = config.init_array; + out.interpreter = config.interpreter; + out.jmprel = config.jmprel; + out.notes = config.notes; + out.preinit_array = config.preinit_array; + out.relr = config.relr; + out.android_rela = config.android_rela; + out.rela = config.rela; + out.static_symtab = config.static_symtab; + out.sym_verdef = config.sym_verdef; + out.sym_verneed = config.sym_verneed; + out.sym_versym = config.sym_versym; + out.symtab = config.symtab; + out.coredump_notes = config.coredump_notes; + out.force_relocate = config.force_relocate; + out.skip_dynamic = config.skip_dynamic; + out.keep_empty_version_requirement = config.keep_empty_version_requirement; + return out; + } + + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using ELF_Binary_it_sections = ELF_Binary::it_sections; +using ELF_Binary_it_segments = ELF_Binary::it_segments; +using ELF_Binary_it_dynamic_entries = ELF_Binary::it_dynamic_entries; +using ELF_Binary_it_dynamic_symbols = ELF_Binary::it_dynamic_symbols; +using ELF_Binary_it_exported_symbols = ELF_Binary::it_exported_symbols; +using ELF_Binary_it_imported_symbols = ELF_Binary::it_imported_symbols; +using ELF_Binary_it_notes = ELF_Binary::it_notes; +using ELF_Binary_it_symtab_symbols = ELF_Binary::it_symtab_symbols; +using ELF_Binary_it_relocations = ELF_Binary::it_relocations; +using ELF_Binary_it_pltgot_relocations = ELF_Binary::it_pltgot_relocations; +using ELF_Binary_it_dynamic_relocations = ELF_Binary::it_dynamic_relocations; +using ELF_Binary_it_object_relocations = ELF_Binary::it_object_relocations; +using ELF_Binary_it_symbols_version = ELF_Binary::it_symbols_version; +using ELF_Binary_it_symbols_version_requirement = + ELF_Binary::it_symbols_version_requirement; +using ELF_Binary_it_symbols_version_definition = + ELF_Binary::it_symbols_version_definition; +using ELF_Binary_it_symbols = ELF_Binary::it_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreAuxv.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreAuxv.hpp new file mode 100644 index 0000000..9e63d2d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreAuxv.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/core/CoreAuxv.hpp" +#include "LIEF/rust/ELF/Note.hpp" + +class ELF_CoreAuxv : public ELF_Note { + public: + using lief_t = LIEF::ELF::CoreAuxv; + ELF_CoreAuxv(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto values() const { + auto vals = impl().values(); + auto result = make_unique_vector(); + result->reserve(vals.size() * 2); + + for (const auto& [k, v] : vals) { + result->push_back((uint64_t)k); + result->push_back(v); + } + return result; + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreFile.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreFile.hpp new file mode 100644 index 0000000..b40dc81 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreFile.hpp @@ -0,0 +1,77 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/core/CoreFile.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/Iterator.hpp" + +class ELF_CoreFile_entry : public Mirror { + public: + using lief_t = LIEF::ELF::CoreFile::entry_t; + using Mirror::Mirror; + + auto start() const { + return get().start; + } + auto end() const { + return get().end; + } + auto file_ofs() const { + return get().file_ofs; + } + auto path() const { + return to_unique_string(get().path); + } +}; + +class ELF_CoreFile : public ELF_Note { + public: + using lief_t = LIEF::ELF::CoreFile; + class it_files : public ContainerIterator { + public: + it_files(const lief_t& src) : + ContainerIterator(src.files()) {} + + auto next() { + return ContainerIterator::next(); + } + + auto size() const { + return ContainerIterator::size(); + } + }; + + ELF_CoreFile(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto count() const { + return impl().count(); + } + + auto files() const { + return std::make_unique(impl()); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using ELF_CoreFile_it_files = ELF_CoreFile::it_files; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrPsInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrPsInfo.hpp new file mode 100644 index 0000000..77a4fd6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrPsInfo.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/core/CorePrPsInfo.hpp" +#include "LIEF/rust/ELF/Note.hpp" + +class ELF_CorePrPsInfo : public ELF_Note { + public: + using lief_t = LIEF::ELF::CorePrPsInfo; + ELF_CorePrPsInfo(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + + // TODO(romain): CorePrPsInfo::info + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrStatus.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrStatus.hpp new file mode 100644 index 0000000..55166ee --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/CorePrStatus.hpp @@ -0,0 +1,117 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/core/CorePrStatus.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/error.hpp" + +class ELF_CorePrStatus_Status { + public: + // siginfo_t + int32_t signo = 0; + int32_t code = 0; + int32_t err = 0; + + uint16_t cursig = 0; + uint16_t reserved = 0; + + uint64_t sigpend = 0; + uint64_t sighold = 0; + + int32_t pid = 0; + int32_t ppid = 0; + int32_t pgrp = 0; + int32_t sid = 0; + + uint64_t utime_sec = 0; + uint64_t utime_usec = 0; + + uint64_t stime_sec = 0; + uint64_t stime_usec = 0; + + uint64_t cutime_sec = 0; + uint64_t cutime_usec = 0; + + uint64_t cstime_sec = 0; + uint64_t cstime_usec = 0; +}; + +class ELF_CorePrStatus : public ELF_Note { + public: + using lief_t = LIEF::ELF::CorePrStatus; + ELF_CorePrStatus(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto architecture() const { + return (uint32_t)impl().architecture(); + } + + ELF_CorePrStatus_Status status() const { + const lief_t::pr_status_t& S = impl().status(); + return { + .signo = S.info.signo, + .code = S.info.code, + .err = S.info.err, + + .cursig = S.cursig, + .reserved = S.reserved, + + .sigpend = S.sigpend, + .sighold = S.sighold, + + .pid = S.pid, + .ppid = S.ppid, + .pgrp = S.pgrp, + .sid = S.sid, + + .utime_sec = S.utime.sec, + .utime_usec = S.utime.usec, + + .stime_sec = S.stime.sec, + .stime_usec = S.stime.usec, + + .cutime_sec = S.cutime.sec, + .cutime_usec = S.cutime.usec, + + .cstime_sec = S.cstime.sec, + .cstime_usec = S.cstime.usec, + }; + } + + uint64_t pc(uint32_t& err) const { + return details::make_error(impl().pc(), err); + } + + uint64_t sp(uint32_t& err) const { + return details::make_error(impl().sp(), err); + } + + uint64_t return_value(uint32_t& err) const { + return details::make_error(impl().return_value(), err); + } + + auto register_values() const { + return make_unique_vector(impl().register_values()); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreSigInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreSigInfo.hpp new file mode 100644 index 0000000..2164794 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/CoreSigInfo.hpp @@ -0,0 +1,48 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/core/CoreSigInfo.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/error.hpp" + +#include + +class ELF_CoreSigInfo : public ELF_Note { + public: + using lief_t = LIEF::ELF::CoreSigInfo; + ELF_CoreSigInfo(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + int32_t signo(uint32_t& err) const { + return details::make_error(impl().signo(), err); + } + + int32_t sigcode(uint32_t& err) const { + return details::make_error(impl().sigcode(), err); + } + + int32_t sigerrno(uint32_t& err) const { + return details::make_error(impl().sigerrno(), err); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntry.hpp new file mode 100644 index 0000000..759ac2d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntry.hpp @@ -0,0 +1,56 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntry.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +using LIEF_ELF_DynamicEntry = LIEF::ELF::DynamicEntry; + +class ELF_DynamicEntry : public Mirror { + friend class ELF_DynamicEntryRpath; + friend class ELF_DynamicEntryArray; + friend class ELF_DynamicEntryFlags; + friend class ELF_DynamicEntryLibrary; + friend class ELF_DynamicEntryRunPath; + friend class ELF_DynamicSharedObject; + + public: + using lief_t = LIEF::ELF::DynamicEntry; + using Mirror::Mirror; + + static auto create(uint64_t tag) { + return std::make_unique(lief_t::create((lief_t::TAG)tag)); + } + + auto tag() const { + return as_u64(get().tag()); + } + auto value() const { + return get().value(); + } + + auto set_value(uint64_t value) { + get().value(value); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } + + const auto* raw_ptr() const { + return &get(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryArray.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryArray.hpp new file mode 100644 index 0000000..3aee7d8 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryArray.hpp @@ -0,0 +1,35 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryArray.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryArray : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryArray; + + auto array() const { + return make_unique_vector(impl().array()); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryAuxiliary.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryAuxiliary.hpp new file mode 100644 index 0000000..a452cab --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryAuxiliary.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryAuxiliary.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryAuxiliary : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryAuxiliary; + ELF_DynamicEntryAuxiliary(std::unique_ptr impl) : + ELF_DynamicEntry(std::move(impl)) {} + + static auto create(const std::string& name) { + return std::make_unique( + std::make_unique(name) + ); + } + + auto name() const { + return to_unique_string(impl().name()); + } + + auto set_name(const std::string& name) { + impl().name(name); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFilter.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFilter.hpp new file mode 100644 index 0000000..9e9385d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFilter.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryFilter.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryFilter : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryFilter; + ELF_DynamicEntryFilter(std::unique_ptr impl) : + ELF_DynamicEntry(std::move(impl)) {} + + static auto create(const std::string& name) { + return std::make_unique( + std::make_unique(name) + ); + } + + auto name() const { + return to_unique_string(impl().name()); + } + + auto set_name(const std::string& name) { + impl().name(name); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFlags.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFlags.hpp new file mode 100644 index 0000000..f7199b1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryFlags.hpp @@ -0,0 +1,58 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryFlags.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryFlags : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryFlags; + ELF_DynamicEntryFlags(const lief_t& impl) : + ELF_DynamicEntry(impl.clone()) {} + + auto flags() const { + return impl().raw_flags(); + } + + auto add_flag(uint64_t f) { + impl().add(lief_t::FLAG(f)); + } + + auto remove_flag(uint64_t f) { + impl().remove(lief_t::FLAG(f)); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + static auto create_dt_flag(uint64_t value) { + return std::make_unique(lief_t::create_dt_flag(value)); + } + + static auto create_dt_flag_1(uint64_t value) { + return std::make_unique( + lief_t::create_dt_flag_1(value) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryLibrary.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryLibrary.hpp new file mode 100644 index 0000000..e5049bf --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryLibrary.hpp @@ -0,0 +1,44 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryLibrary.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryLibrary : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryLibrary; + ELF_DynamicEntryLibrary(const lief_t& impl) : + ELF_DynamicEntry(static_cast(impl)) {} + + auto name() const { + return to_unique_string(impl().name()); + } + + auto set_name(const std::string& name) { + impl().name(name); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRpath.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRpath.hpp new file mode 100644 index 0000000..666e276 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRpath.hpp @@ -0,0 +1,64 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryRpath.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicEntryRpath : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryRpath; + + ELF_DynamicEntryRpath(std::unique_ptr impl) : + ELF_DynamicEntry(std::move(impl)) {} + + static auto create(const std::string& name) { + return std::make_unique(std::make_unique(name)); + } + + auto rpath() const { + return to_unique_string(impl().rpath()); + } + auto paths() const { + return make_unique_vector(impl().paths()); + } + + auto insert(uint32_t pos, const std::string& name) { + impl().insert(pos, name); + } + + auto append(const std::string& name) { + impl().append(name); + } + + auto remove(const std::string& path) { + impl().remove(path); + } + + auto set_rpath(const std::string& path) { + impl().rpath(path); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRunPath.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRunPath.hpp new file mode 100644 index 0000000..12f24f0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicEntryRunPath.hpp @@ -0,0 +1,69 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicEntryRunPath.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +#include +#include + +class ELF_DynamicEntryRunPath : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicEntryRunPath; + + ELF_DynamicEntryRunPath(std::unique_ptr impl) : + ELF_DynamicEntry(std::move(impl)) {} + + static auto create(const std::string& name) { + return std::make_unique( + std::make_unique(name) + ); + } + + auto runpath() const { + return to_unique_string(impl().runpath()); + } + auto paths() const { + return make_unique_vector(impl().paths()); + } + + auto insert(uint32_t pos, const std::string& name) { + impl().insert(pos, name); + } + + auto append(const std::string& name) { + impl().append(name); + } + + auto remove(const std::string& path) { + impl().remove(path); + } + + auto set_runpath(const std::string& path) { + impl().runpath(path); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicSharedObject.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicSharedObject.hpp new file mode 100644 index 0000000..c492037 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/DynamicSharedObject.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/DynamicSharedObject.hpp" +#include "LIEF/rust/ELF/DynamicEntry.hpp" + +class ELF_DynamicSharedObject : public ELF_DynamicEntry { + public: + using lief_t = LIEF::ELF::DynamicSharedObject; + ELF_DynamicSharedObject(std::unique_ptr impl) : + ELF_DynamicEntry(std::move(impl)) {} + + static auto create(const std::string& name) { + return std::make_unique( + std::make_unique(name) + ); + } + + auto name() const { + return to_unique_string(impl().name()); + } + + auto set_name(const std::string& name) { + impl().name(name); + } + + static auto classof(const ELF_DynamicEntry& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/GnuHash.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/GnuHash.hpp new file mode 100644 index 0000000..65df7e2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/GnuHash.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/GnuHash.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_GnuHash : private Mirror { + public: + using lief_t = LIEF::ELF::GnuHash; + using Mirror::Mirror; + + uint32_t nb_buckets() const { + return get().nb_buckets(); + } + uint32_t symbol_index() const { + return get().symbol_index(); + } + uint32_t shift2() const { + return get().shift2(); + } + uint32_t maskwords() const { + return get().maskwords(); + } + + auto bloom_filters() const { + return make_unique_vector(get().bloom_filters()); + } + auto buckets() const { + return make_unique_vector(get().buckets()); + } + auto hash_values() const { + return make_unique_vector(get().hash_values()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Header.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Header.hpp new file mode 100644 index 0000000..006b23c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Header.hpp @@ -0,0 +1,85 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include + +class ELF_Header : public Mirror { + public: + using Mirror::Mirror; + + uint64_t entrypoint() const { + return get().entrypoint(); + } + auto file_type() const { + return as_u32(get().file_type()); + } + auto machine_type() const { + return as_u32(get().machine_type()); + } + auto object_file_version() const { + return as_u32(get().object_file_version()); + } + auto identity_class() const { + return as_u32(get().identity_class()); + } + auto identity_os_abi() const { + return as_u32(get().identity_os_abi()); + } + auto identity_version() const { + return as_u32(get().identity_version()); + } + auto identity_data() const { + return as_u32(get().identity_data()); + } + bool is_mips_n64() const { + return get().is_mips_n64(); + } + uint32_t identity_abi_version() const { + return get().identity_abi_version(); + } + uint64_t program_headers_offset() const { + return get().program_headers_offset(); + } + uint64_t section_headers_offset() const { + return get().section_headers_offset(); + } + uint32_t processor_flag() const { + return get().processor_flag(); + } + uint32_t header_size() const { + return get().header_size(); + } + uint32_t program_header_size() const { + return get().program_header_size(); + } + uint32_t numberof_segments() const { + return get().numberof_segments(); + } + uint32_t section_header_size() const { + return get().section_header_size(); + } + uint32_t numberof_sections() const { + return get().numberof_sections(); + } + uint32_t section_name_table_idx() const { + return get().section_name_table_idx(); + } + + auto set_osabi(uint32_t value) { + get().identity_os_abi((LIEF::ELF::Header::OS_ABI)value); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Note.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Note.hpp new file mode 100644 index 0000000..848e342 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Note.hpp @@ -0,0 +1,44 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/Note.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_Note : public Mirror { + public: + using lief_t = LIEF::ELF::Note; + using Mirror::Mirror; + + friend class ELF_Binary; + + auto name() const { + return to_unique_string(get().name()); + } + auto get_type() const { + return as_u32(get().type()); + } + uint32_t original_type() const { + return get().original_type(); + } + uint64_t size() const { + return get().size(); + } + + Span description() const { + return make_span(get().description()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAbi.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAbi.hpp new file mode 100644 index 0000000..1371400 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAbi.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/NoteAbi.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_NoteAbi : public ELF_Note { + public: + using lief_t = LIEF::ELF::NoteAbi; + ELF_NoteAbi(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto abi() const { + return as_u32(impl().abi().value_or(lief_t::ABI::LINUX)); + } + + auto version() const { + if (auto res = impl().version()) { + return to_vector(*res); + } + return make_unique_vector(); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAndroidIdent.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAndroidIdent.hpp new file mode 100644 index 0000000..38792b5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteAndroidIdent.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/AndroidIdent.hpp" +#include "LIEF/rust/ELF/Note.hpp" + +class ELF_AndroidIdent : public ELF_Note { + public: + using lief_t = LIEF::ELF::AndroidIdent; + ELF_AndroidIdent(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto sdk_version() const { + return impl().sdk_version(); + } + + auto ndk_version() const { + return to_unique_string(impl().ndk_version()); + } + + auto ndk_build_number() const { + return to_unique_string(impl().ndk_build_number()); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteGnuProperty.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteGnuProperty.hpp new file mode 100644 index 0000000..16e3da8 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteGnuProperty.hpp @@ -0,0 +1,232 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/NoteGnuProperty.hpp" +#include "LIEF/rust/ELF/Note.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/ELF/NoteDetails/properties/AArch64Feature.hpp" +#include "LIEF/ELF/NoteDetails/properties/AArch64PAuth.hpp" +#include "LIEF/ELF/NoteDetails/properties/Generic.hpp" +#include "LIEF/ELF/NoteDetails/properties/Needed.hpp" +#include "LIEF/ELF/NoteDetails/properties/NoteNoCopyOnProtected.hpp" +#include "LIEF/ELF/NoteDetails/properties/StackSize.hpp" +#include "LIEF/ELF/NoteDetails/properties/X86Feature.hpp" +#include "LIEF/ELF/NoteDetails/properties/X86ISA.hpp" + +class ELF_NoteGnuProperty_Property + : public Mirror { + public: + using lief_t = LIEF::ELF::NoteGnuProperty::Property; + using Mirror::Mirror; + + auto get_type() const { + return as_u32(get().type()); + } +}; + +class ELF_NoteGnuProperty_AArch64Feature : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::AArch64Feature; + ELF_NoteGnuProperty_AArch64Feature(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + auto features() const { + return to_vector(as(this).features()); + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_AArch64PAuth : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::AArch64PAuth; + ELF_NoteGnuProperty_AArch64PAuth(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + auto platform() const { + return as(this).platform(); + } + + auto version() const { + return as(this).version(); + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_Generic : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::Generic; + ELF_NoteGnuProperty_Generic(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + auto raw_type() const { + return as(this).type(); + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_Needed : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::Needed; + ELF_NoteGnuProperty_Needed(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + auto needs() const { + return to_vector(as(this).needs()); + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_NoteNoCopyOnProtected + : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::NoteNoCopyOnProtected; + ELF_NoteGnuProperty_NoteNoCopyOnProtected(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_StackSize : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::StackSize; + ELF_NoteGnuProperty_StackSize(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + auto stack_size() const { + return as(this).stack_size(); + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_X86Features : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::X86Features; + ELF_NoteGnuProperty_X86Features(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + // Returns pairs of (flag, feature) as a flat vector: [flag0, feat0, flag1, + // feat1, ...] + auto features() const { + auto result = make_unique_vector(); + for (const auto& [f, feat] : as(this).features()) { + result->push_back((uint64_t)f); + result->push_back((uint64_t)feat); + } + return result; + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty_X86ISA : public ELF_NoteGnuProperty_Property { + public: + using lief_t = LIEF::ELF::X86ISA; + ELF_NoteGnuProperty_X86ISA(const lief_t& impl) : + ELF_NoteGnuProperty_Property( + static_cast(impl) + ) {} + + // Returns pairs of (flag, isa) as a flat vector: [flag0, isa0, flag1, isa1, ...] + auto values() const { + auto result = make_unique_vector(); + for (const auto& [f, isa] : as(this).values()) { + result->push_back((uint64_t)f); + result->push_back((uint64_t)isa); + } + return result; + } + + static auto classof(const ELF_NoteGnuProperty_Property& prop) { + return lief_t::classof(&prop.get()); + } +}; + +class ELF_NoteGnuProperty : public ELF_Note { + public: + using lief_t = LIEF::ELF::NoteGnuProperty; + + class it_properties : public ContainerIterator { + public: + it_properties(const lief_t& src) : + ContainerIterator(src.properties()) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + ELF_NoteGnuProperty(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto properties() const { + return std::make_unique(impl()); + } + + auto find(uint32_t type) const { + return details::try_unique( + impl().find((lief_t::Property::TYPE)type) + ); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using ELF_NoteGnuProperty_it_properties = ELF_NoteGnuProperty::it_properties; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteQNXStack.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteQNXStack.hpp new file mode 100644 index 0000000..5a7f276 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/NoteQNXStack.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/NoteDetails/QNXStack.hpp" +#include "LIEF/rust/ELF/Note.hpp" + +class ELF_QNXStack : public ELF_Note { + public: + using lief_t = LIEF::ELF::QNXStack; + ELF_QNXStack(const lief_t& impl) : + ELF_Note(static_cast(impl)) {} + + auto stack_size() const { + return impl().stack_size(); + } + + auto stack_allocated() const { + return impl().stack_allocated(); + } + + auto is_executable() const { + return impl().is_executable(); + } + + static auto classof(const ELF_Note& note) { + return lief_t::classof(¬e.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Relocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Relocation.hpp new file mode 100644 index 0000000..4f41645 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Relocation.hpp @@ -0,0 +1,74 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/Relocation.hpp" +#include "LIEF/rust/Abstract/Relocation.hpp" +#include "LIEF/rust/ELF/Section.hpp" +#include "LIEF/rust/ELF/Symbol.hpp" +#include "LIEF/rust/error.hpp" + +class ELF_Relocation : public AbstractRelocation { + public: + using lief_t = LIEF::ELF::Relocation; + ELF_Relocation(const lief_t& reloc) : + AbstractRelocation(reloc) {} + + int64_t addend() const { + return impl().addend(); + } + uint32_t get_type() const { + return to_int(impl().type()); + } + auto is_rela() const { + return impl().is_rela(); + } + auto is_rel() const { + return impl().is_rel(); + } + + uint32_t info() const { + return impl().info(); + } + uint32_t architecture() const { + return to_int(impl().architecture()); + } + uint32_t purpose() const { + return to_int(impl().purpose()); + } + uint32_t encoding() const { + return to_int(impl().encoding()); + } + + auto symbol() const { + return details::try_unique(impl().symbol()); + } + + auto section() const { + return details::try_unique(impl().section()); + } + + auto symbol_table() const { + return details::try_unique(impl().symbol_table()); + } + + uint64_t resolve(uint64_t base_address, uint32_t& err) const { + return details::make_error(impl().resolve(base_address), err); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Section.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Section.hpp new file mode 100644 index 0000000..325dfdc --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Section.hpp @@ -0,0 +1,81 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/ELF/Section.hpp" +#include "LIEF/rust/Abstract/Section.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_Section : public AbstractSection { + public: + using lief_t = LIEF::ELF::Section; + ELF_Section(const lief_t& section) : + AbstractSection(section) {} + ELF_Section(std::unique_ptr impl) : + AbstractSection(std::move(impl)) {} + + static auto create() { + return std::make_unique(std::make_unique()); + } + + static auto create_with_name(const std::string& name) { + return std::make_unique(std::make_unique(name)); + } + + static auto create_with_content(const std::string& name, const uint8_t* buffer, + size_t size) { + auto section = std::make_unique(name); + section->content(std::vector{buffer, buffer + size}); + return std::make_unique(std::move(section)); + } + + uint64_t get_type() const { + return to_int(impl().type()); + } + uint64_t flags() const { + return impl().flags(); + } + uint64_t alignment() const { + return impl().alignment(); + } + uint64_t information() const { + return impl().information(); + } + uint64_t entry_size() const { + return impl().entry_size(); + } + uint64_t link() const { + return impl().link(); + } + uint64_t file_offset() const { + return impl().file_offset(); + } + uint64_t original_size() const { + return impl().original_size(); + } + Span content() const { + return make_span(impl().content()); + } + + auto to_string() const { + return to_unique_string(details::to_string(impl())); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Segment.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Segment.hpp new file mode 100644 index 0000000..0106b4f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Segment.hpp @@ -0,0 +1,101 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/Segment.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_Segment : public Mirror { + public: + using lief_t = LIEF::ELF::Segment; + using Mirror::Mirror; + + static auto create() { + return std::make_unique(std::make_unique()); + } + + auto stype() const { + return as_u64(get().type()); + } + auto flags() const { + return as_u32(get().flags()); + } + auto file_offset() const { + return get().file_offset(); + } + auto virtual_address() const { + return get().virtual_address(); + } + auto physical_address() const { + return get().physical_address(); + } + auto physical_size() const { + return get().physical_size(); + } + auto virtual_size() const { + return get().virtual_size(); + } + auto alignment() const { + return get().alignment(); + } + + auto set_flags(uint32_t value) { + get().flags(value); + } + + auto set_type(uint64_t ty) { + get().type((lief_t::TYPE)ty); + } + + auto set_file_offset(uint64_t value) { + get().file_offset(value); + } + + auto set_virtual_address(uint64_t value) { + get().virtual_address(value); + } + + auto set_physical_address(uint64_t value) { + get().physical_address(value); + } + + auto set_virtual_size(uint64_t value) { + get().virtual_size(value); + } + + auto set_alignment(uint64_t value) { + get().alignment(value); + } + + auto set_content(const uint8_t* ptr, uint64_t size) { + get().content({ptr, ptr + size}); + } + + Span content() const { + return make_span(get().content()); + } + + auto fill(int8_t c) { + get().fill(c); + } + auto clear() { + get().clear(); + } + + auto to_string() const { + return to_unique_string(details::to_string(get())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Symbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Symbol.hpp new file mode 100644 index 0000000..aaa4fea --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Symbol.hpp @@ -0,0 +1,66 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/Symbol.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/ELF/Section.hpp" +#include "LIEF/rust/ELF/SymbolVersion.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_Symbol : public AbstractSymbol { + public: + using lief_t = LIEF::ELF::Symbol; + ELF_Symbol(const lief_t& obj) : + AbstractSymbol(obj) {} + uint32_t get_type() const { + return to_int(impl().type()); + } + + uint32_t binding() const { + return to_int(impl().binding()); + } + uint8_t information() const { + return impl().information(); + } + uint8_t other() const { + return impl().other(); + } + uint16_t section_idx() const { + return impl().section_idx(); + } + uint32_t visibility() const { + return to_int(impl().visibility()); + } + + auto section() const { + return details::try_unique(impl().section()); + } + auto symbol_version() const { + return details::try_unique(impl().symbol_version()); + } + + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + auto to_string() const { + return to_unique_string(details::to_string(impl())); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersion.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersion.hpp new file mode 100644 index 0000000..9d9c60c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersion.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/SymbolVersion.hpp" +#include "LIEF/rust/ELF/SymbolVersionAux.hpp" +#include "LIEF/rust/Mirror.hpp" + +class ELF_SymbolVersion : private Mirror { + public: + using lief_t = LIEF::ELF::SymbolVersion; + using Mirror::Mirror; + + auto value() const { + return get().value(); + } + + auto symbol_version_auxiliary() const { + return details::try_unique( + get().symbol_version_auxiliary() + ); + } + + auto drop_version(uint16_t value) { + get().drop_version(value); + } + + auto as_local() { + get().as_local(); + } + auto as_global() { + get().as_global(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAux.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAux.hpp new file mode 100644 index 0000000..5360288 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAux.hpp @@ -0,0 +1,27 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/SymbolVersionAux.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_SymbolVersionAux : public Mirror { + public: + using lief_t = LIEF::ELF::SymbolVersionAux; + using Mirror::Mirror; + auto name() const { + return to_unique_string(get().name()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAuxRequirement.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAuxRequirement.hpp new file mode 100644 index 0000000..e8b5233 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionAuxRequirement.hpp @@ -0,0 +1,43 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/SymbolVersionAuxRequirement.hpp" +#include "LIEF/rust/ELF/SymbolVersionAux.hpp" + +class ELF_SymbolVersionAuxRequirement : public ELF_SymbolVersionAux { + public: + using lief_t = LIEF::ELF::SymbolVersionAuxRequirement; + ELF_SymbolVersionAuxRequirement(const lief_t& sym) : + ELF_SymbolVersionAux(sym) {} + + uint32_t hash() const { + return impl().hash(); + } + uint16_t flags() const { + return impl().flags(); + } + uint16_t other() const { + return impl().other(); + } + + auto name() const { + return ELF_SymbolVersionAux::name(); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionDefinition.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionDefinition.hpp new file mode 100644 index 0000000..5441d68 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionDefinition.hpp @@ -0,0 +1,62 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ELF/SymbolVersionDefinition.hpp" +#include "LIEF/rust/ELF/SymbolVersionAux.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" + +class ELF_SymbolVersionDefinition + : private Mirror { + public: + using lief_t = LIEF::ELF::SymbolVersionDefinition; + using Mirror::Mirror; + + class it_auxiliary_symbols + : public Iterator { + public: + it_auxiliary_symbols(const ELF_SymbolVersionDefinition::lief_t& src) : + Iterator(src.symbols_aux()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + + uint16_t version() const { + return get().version(); + } + uint16_t flags() const { + return get().flags(); + } + uint16_t ndx() const { + return get().ndx(); + } + uint32_t hash() const { + return get().hash(); + } + + auto sym_aux() const { + return std::make_unique(get()); + } +}; + +using ELF_SymbolVersionDefinition_it_auxiliary_symbols = + ELF_SymbolVersionDefinition::it_auxiliary_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionRequirement.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionRequirement.hpp new file mode 100644 index 0000000..a0d1628 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/SymbolVersionRequirement.hpp @@ -0,0 +1,79 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/ELF/SymbolVersionRequirement.hpp" +#include "LIEF/rust/ELF/SymbolVersionAuxRequirement.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" +#include + +class ELF_SymbolVersionRequirement + : private Mirror { + public: + using lief_t = LIEF::ELF::SymbolVersionRequirement; + using Mirror::Mirror; + + class it_auxiliary_symbols + : public Iterator< + ELF_SymbolVersionAuxRequirement, + LIEF::ELF::SymbolVersionRequirement::it_const_aux_requirement + > { + public: + it_auxiliary_symbols(const ELF_SymbolVersionRequirement::lief_t& src) : + Iterator(src.auxiliary_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto version() const { + return get().version(); + } + uint32_t cnt() const { + return get().cnt(); + } + auto name() const { + return to_unique_string(get().name()); + } + + auto auxiliary_symbols() const { + return std::make_unique(get()); + } + + auto set_version(uint16_t version) { + get().version(version); + } + + auto set_name(const std::string& name) { + get().name(name); + } + + auto find_aux(const std::string& name) const { + return details::try_unique( + get().find_aux(name) + ); + } + + auto remove_aux_requirement_by_name(const std::string& name) { + return get().remove_aux_requirement(name); + } +}; + +using ELF_SymbolVersionRequirement_it_auxiliary_symbols = + ELF_SymbolVersionRequirement::it_auxiliary_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/Sysvhash.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/Sysvhash.hpp new file mode 100644 index 0000000..2911677 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/Sysvhash.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/ELF/SysvHash.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ELF_SysvHash : private Mirror { + public: + using lief_t = LIEF::ELF::SysvHash; + using Mirror::Mirror; + + uint32_t nbucket() const { + return get().nbucket(); + } + uint32_t nchain() const { + return get().nchain(); + } + auto buckets() const { + return make_unique_vector(get().buckets()); + } + auto chains() const { + return make_unique_vector(get().chains()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ELF/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/ELF/utils.hpp new file mode 100644 index 0000000..06e4cd9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ELF/utils.hpp @@ -0,0 +1,32 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/ELF/utils.hpp" +#include "LIEF/rust/ELF/Binary.hpp" +#include + +class ELF_Utils { + public: + static auto is_elf(const std::string& file) { + return LIEF::ELF::is_elf(file); + } + + static auto check_layout(const ELF_Binary& bin, std::string* error) { + return LIEF::ELF::check_layout( + static_cast(bin.get()), error + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Iterator.hpp b/vendor/lief/api/rust/include/LIEF/rust/Iterator.hpp new file mode 100644 index 0000000..69ccc85 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Iterator.hpp @@ -0,0 +1,179 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/iterators.hpp" +#include +#include +#include + +namespace details { +template +struct has_yield : std::false_type {}; + +template +struct has_yield().yield())>> + : std::true_type {}; + + +template +constexpr bool has_yield_v = has_yield::value; +} + +template +class Iterator { + public: + using lief_t = V; + std::unique_ptr next() { + if (it_ == it_.end()) { + return nullptr; + } + if constexpr (details::has_yield_v) { + auto owned = it_.yield(); + ++it_; + return owned ? std::make_unique(std::move(owned)) : nullptr; + } else { + return std::make_unique(*it_++); + } + } + + uint64_t size() const { + return it_.size(); + } + + protected: + Iterator(V it) : + it_(std::move(it)) {} + V it_; +}; + + +template +class ForwardIterator { + public: + using lief_t = V; + std::unique_ptr next() { + if (begin_ == end_) { + return nullptr; + } + if constexpr (details::has_yield_v) { + auto owned = begin_.yield(); + ++begin_; + return owned ? std::make_unique(std::move(owned)) : nullptr; + } else { + auto&& value = *begin_; + ++begin_; + return std::make_unique(std::move(value)); + } + } + + auto empty() const { + return begin_ == end_; + } + + uint64_t size() const { + return std::distance(begin_, end_); + } + + protected: + ForwardIterator(LIEF::iterator_range range) : + begin_(std::move(range.begin())), + end_(std::move(range.end())) {} + + ForwardIterator(V begin, V end) : + begin_(std::move(begin)), + end_(std::move(end)) {} + + V begin_; + V end_; +}; + +template +class RandomRangeIterator { + public: + using lief_t = V; + std::unique_ptr next() { + if (it_ == end_) { + return nullptr; + } + if constexpr (details::has_yield_v) { + auto owned = it_.yield(); + ++it_; + return owned ? std::make_unique(std::move(owned)) : nullptr; + } else { + return std::make_unique(*it_++); + } + } + + uint64_t size() const { + return std::distance(begin_, end_); + } + + auto empty() const { + return begin_ == end_; + } + + protected: + RandomRangeIterator(LIEF::iterator_range range) : + begin_(std::move(range.begin())), + end_(std::move(range.end())), + it_(begin_) {} + + RandomRangeIterator(V begin, V end) : + begin_(std::move(begin)), + end_(std::move(end)), + it_(begin_) {} + + V begin_; + V end_; + V it_; +}; + +template +class ContainerIterator { + public: + ContainerIterator(const ContainerIterator&) = delete; + ContainerIterator& operator=(const ContainerIterator&) = delete; + + ContainerIterator(ContainerIterator&&) = delete; + ContainerIterator& operator=(ContainerIterator&&) = delete; + + ~ContainerIterator() = default; + + std::unique_ptr next() { + if (begin_ == end_) { + return nullptr; + } + return std::make_unique(std::move(*begin_++)); + } + + uint64_t size() const { + return std::distance(begin_, end_); + } + + auto empty() const { + return begin_ == end_; + } + + protected: + template + ContainerIterator(CT&& C) : + container_(std::forward(C)), + begin_(std::begin(container_)), + end_(std::end(container_)) {} + + ContainerT container_; + typename ContainerT::iterator begin_; + typename ContainerT::iterator end_; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/LIEF.hpp b/vendor/lief/api/rust/include/LIEF/rust/LIEF.hpp new file mode 100644 index 0000000..c6162dd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/LIEF.hpp @@ -0,0 +1,34 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/ASM.hpp" +#include "LIEF/rust/Abstract.hpp" +#include "LIEF/rust/COFF.hpp" +#include "LIEF/rust/DWARF.hpp" +#include "LIEF/rust/DyldSharedCache.hpp" +#include "LIEF/rust/ELF.hpp" +#include "LIEF/rust/MachO.hpp" +#include "LIEF/rust/ObjC.hpp" +#include "LIEF/rust/PDB.hpp" +#include "LIEF/rust/PE.hpp" +#include "LIEF/rust/logging.hpp" +#include "LIEF/rust/runtime.hpp" + +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/debug_location.hpp" +#include "LIEF/rust/range.hpp" +#include "LIEF/rust/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO.hpp new file mode 100644 index 0000000..210c2a1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO.hpp @@ -0,0 +1,61 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/MachO/AtomInfo.hpp" +#include "LIEF/rust/MachO/Binary.hpp" +#include "LIEF/rust/MachO/BindingInfo.hpp" +#include "LIEF/rust/MachO/BuildToolVersion.hpp" +#include "LIEF/rust/MachO/BuildVersion.hpp" +#include "LIEF/rust/MachO/ChainedBindingInfo.hpp" +#include "LIEF/rust/MachO/DataCodeEntry.hpp" +#include "LIEF/rust/MachO/DataInCode.hpp" +#include "LIEF/rust/MachO/DyldBindingInfo.hpp" +#include "LIEF/rust/MachO/DyldInfo.hpp" +#include "LIEF/rust/MachO/Dylib.hpp" +#include "LIEF/rust/MachO/EncryptionInfo.hpp" +#include "LIEF/rust/MachO/ExportInfo.hpp" +#include "LIEF/rust/MachO/FatBinary.hpp" +#include "LIEF/rust/MachO/Fileset.hpp" +#include "LIEF/rust/MachO/FunctionStarts.hpp" +#include "LIEF/rust/MachO/FunctionVariantFixups.hpp" +#include "LIEF/rust/MachO/FunctionVariants.hpp" +#include "LIEF/rust/MachO/Header.hpp" +#include "LIEF/rust/MachO/IndirectBindingInfo.hpp" +#include "LIEF/rust/MachO/LazyLoadDylibInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/MachO/Main.hpp" +#include "LIEF/rust/MachO/NoteCommand.hpp" +#include "LIEF/rust/MachO/RPathCommand.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" +#include "LIEF/rust/MachO/RelocationDyld.hpp" +#include "LIEF/rust/MachO/RelocationFixup.hpp" +#include "LIEF/rust/MachO/RelocationObject.hpp" +#include "LIEF/rust/MachO/Routine.hpp" +#include "LIEF/rust/MachO/Section.hpp" +#include "LIEF/rust/MachO/SegmentCommand.hpp" +#include "LIEF/rust/MachO/SegmentSplitInfo.hpp" +#include "LIEF/rust/MachO/SourceVersion.hpp" +#include "LIEF/rust/MachO/Stub.hpp" +#include "LIEF/rust/MachO/SubClient.hpp" +#include "LIEF/rust/MachO/SubFramework.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" +#include "LIEF/rust/MachO/SymbolCommand.hpp" +#include "LIEF/rust/MachO/ThreadCommand.hpp" +#include "LIEF/rust/MachO/ThreadLocalVariables.hpp" +#include "LIEF/rust/MachO/TwoLevelHints.hpp" +#include "LIEF/rust/MachO/UUIDCommand.hpp" +#include "LIEF/rust/MachO/UnknownCommand.hpp" +#include "LIEF/rust/MachO/VersionMin.hpp" +#include "LIEF/rust/MachO/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/AtomInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/AtomInfo.hpp new file mode 100644 index 0000000..081dcf1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/AtomInfo.hpp @@ -0,0 +1,46 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/AtomInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_AtomInfo : public MachO_Command { + public: + using lief_t = LIEF::MachO::AtomInfo; + MachO_AtomInfo(const lief_t& base) : + MachO_Command(base) {} + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Binary.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Binary.hpp new file mode 100644 index 0000000..335eb91 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Binary.hpp @@ -0,0 +1,690 @@ +/* Copyright 2025 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include +#include +#include + +#include "LIEF/rust/MachO/AtomInfo.hpp" +#include "LIEF/rust/MachO/BuildVersion.hpp" +#include "LIEF/rust/MachO/CodeSignature.hpp" +#include "LIEF/rust/MachO/CodeSignatureDir.hpp" +#include "LIEF/rust/MachO/DataInCode.hpp" +#include "LIEF/rust/MachO/DyldChainedFixups.hpp" +#include "LIEF/rust/MachO/DyldEnvironment.hpp" +#include "LIEF/rust/MachO/DyldExportsTrie.hpp" +#include "LIEF/rust/MachO/DyldInfo.hpp" +#include "LIEF/rust/MachO/Dylib.hpp" +#include "LIEF/rust/MachO/Dylinker.hpp" +#include "LIEF/rust/MachO/DynamicSymbolCommand.hpp" +#include "LIEF/rust/MachO/EncryptionInfo.hpp" +#include "LIEF/rust/MachO/ExportInfo.hpp" +#include "LIEF/rust/MachO/FunctionStarts.hpp" +#include "LIEF/rust/MachO/FunctionVariantFixups.hpp" +#include "LIEF/rust/MachO/FunctionVariants.hpp" +#include "LIEF/rust/MachO/Header.hpp" +#include "LIEF/rust/MachO/LazyLoadDylibInfo.hpp" +#include "LIEF/rust/MachO/LinkerOptHint.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/MachO/Main.hpp" +#include "LIEF/rust/MachO/NoteCommand.hpp" +#include "LIEF/rust/MachO/RPathCommand.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" +#include "LIEF/rust/MachO/Routine.hpp" +#include "LIEF/rust/MachO/SegmentCommand.hpp" +#include "LIEF/rust/MachO/SegmentSplitInfo.hpp" +#include "LIEF/rust/MachO/SourceVersion.hpp" +#include "LIEF/rust/MachO/Stub.hpp" +#include "LIEF/rust/MachO/SubClient.hpp" +#include "LIEF/rust/MachO/SubFramework.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" +#include "LIEF/rust/MachO/SymbolCommand.hpp" +#include "LIEF/rust/MachO/ThreadCommand.hpp" +#include "LIEF/rust/MachO/TwoLevelHints.hpp" +#include "LIEF/rust/MachO/UUIDCommand.hpp" +#include "LIEF/rust/MachO/VersionMin.hpp" + +#include "LIEF/rust/Abstract/Binary.hpp" + +#include "LIEF/rust/ObjC/Metadata.hpp" + +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/range.hpp" + +class MachO_Binary_write_config_t { + public: + bool linkedit = true; +}; + +class MachO_Binary : public AbstractBinary { + public: + using lief_t = LIEF::MachO::Binary; + + class it_commands + : public Iterator { + public: + it_commands(const MachO_Binary::lief_t& src) : + Iterator(src.commands()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols + : public Iterator { + public: + it_symbols(const MachO_Binary::lief_t& src) : + Iterator(src.symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_exported_symbols + : public Iterator { + public: + it_exported_symbols(const MachO_Binary::lief_t& src) : + Iterator(src.exported_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_sections + : public Iterator { + public: + it_sections(const MachO_Binary::lief_t& src) : + Iterator(src.sections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_segments : public Iterator { + public: + it_segments(const MachO_Binary::lief_t& src) : + Iterator(src.segments()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_libraries + : public Iterator { + public: + it_libraries(const MachO_Binary::lief_t& src) : + Iterator(src.libraries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_lazy_load_dylib_info + : public Iterator { + public: + it_lazy_load_dylib_info(const MachO_Binary::lief_t& src) : + Iterator(src.lazy_load_dylib_infos()) {} + auto next() { // NOLINT + return Iterator::next(); + } + auto size() const { // NOLINT + return Iterator::size(); + } + }; + + class it_relocations + : public Iterator { + public: + it_relocations(const MachO_Binary::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + + class it_rpaths + : public Iterator { + public: + it_rpaths(const MachO_Binary::lief_t& src) : + Iterator(src.rpaths()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_sub_clients + : public Iterator { + public: + it_sub_clients(const MachO_Binary::lief_t& src) : + Iterator(src.subclients()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_bindings_info + : public ForwardIterator { + public: + it_bindings_info(const MachO_Binary::lief_t& src) : + ForwardIterator(src.bindings()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_stubs + : public RandomRangeIterator { + public: + it_stubs(const MachO_Binary::lief_t& src) : + RandomRangeIterator(src.symbol_stubs()) {} + auto next() { + return RandomRangeIterator::next(); + } + auto size() const { + return RandomRangeIterator::size(); + } + }; + + class it_notes + : public Iterator { + public: + it_notes(const MachO_Binary::lief_t& src) : + Iterator(src.notes()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_fileset_binaries + : public Iterator { + public: + it_fileset_binaries(const MachO_Binary::lief_t& src) : + Iterator(src.filesets()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_Binary(const lief_t& bin) : + AbstractBinary(bin) {} + MachO_Binary(std::unique_ptr ptr) : + AbstractBinary(std::move(ptr)) {} + + auto header() const { + return std::make_unique(impl().header()); + } + + auto commands() const { + return std::make_unique(impl()); + } + auto symbols() const { + return std::make_unique(impl()); + } + auto exported_symbols() const { + return std::make_unique(impl()); + } + auto sections() const { + return std::make_unique(impl()); + } + auto segments() const { + return std::make_unique(impl()); + } + auto libraries() const { + return std::make_unique(impl()); + } + auto lazy_load_dylib_infos() const { + return std::make_unique(impl()); + } + auto relocations() const { + return std::make_unique(impl()); + } + auto rpaths() const { + return std::make_unique(impl()); + } + auto bindings() const { + return std::make_unique(impl()); + } + auto symbol_stubs() const { + return std::make_unique(impl()); + } + auto notes() const { + return std::make_unique(impl()); + } + + auto dyld_info() const { + return details::try_unique(impl().dyld_info()); + } + + auto uuid() const { + return details::try_unique(impl().uuid()); + } + + auto main_command() const { + return details::try_unique(impl().main_command()); + } + + auto dylinker() const { + return details::try_unique(impl().dylinker()); + } + + auto function_starts() const { + return details::try_unique(impl().function_starts()); + } + + auto source_version() const { + return details::try_unique(impl().source_version()); + } + + auto thread_command() const { + return details::try_unique(impl().thread_command()); + } + + auto routine_command() const { + return details::try_unique(impl().routine_command()); + } + + auto rpath() const { + return details::try_unique(impl().rpath()); + } + + auto symbol_command() const { + return details::try_unique(impl().symbol_command()); + } + + auto dynamic_symbol_command() const { + return details::try_unique( + impl().dynamic_symbol_command() + ); + } + + auto code_signature() const { + return details::try_unique(impl().code_signature()); + } + + auto code_signature_dir() const { + return details::try_unique( + impl().code_signature_dir() + ); + } + + auto data_in_code() const { + return details::try_unique(impl().data_in_code()); + } + + auto segment_split_info() const { + return details::try_unique( + impl().segment_split_info() + ); + } + + auto encryption_info() const { + return details::try_unique(impl().encryption_info()); + } + + auto sub_framework() const { + return details::try_unique(impl().sub_framework()); + } + + auto subclients() const { + return std::make_unique(impl()); + } + + auto dyld_environment() const { + return details::try_unique(impl().dyld_environment()); + } + + auto build_version() const { + return details::try_unique(impl().build_version()); + } + + auto dyld_chained_fixups() const { + return details::try_unique( + impl().dyld_chained_fixups() + ); + } + + auto dyld_exports_trie() const { + return details::try_unique(impl().dyld_exports_trie()); + } + + auto two_level_hints() const { + return details::try_unique(impl().two_level_hints()); + } + + auto linker_opt_hint() const { + return details::try_unique(impl().linker_opt_hint()); + } + + auto atom_info() const { + return details::try_unique(impl().atom_info()); + } + + auto function_variants() const { + return details::try_unique(impl().function_variants()); + } + + auto function_variant_fixups() const { + return details::try_unique( + impl().function_variant_fixups() + ); + } + + auto version_min() const { + return details::try_unique(impl().version_min()); + } + + auto support_arm64_ptr_auth() const { + return impl().support_arm64_ptr_auth(); + } + + auto objc_metadata() const { + return details::try_unique(impl().objc_metadata()); + } + + auto platform() const { + return to_int(impl().platform()); + } + + auto functions() const { + return std::make_unique(impl().functions()); + } + + auto is_ios() const { + return impl().is_ios(); + } + auto is_macos() const { + return impl().is_macos(); + } + + auto find_library(const std::string& name) const { + return details::try_unique(impl().find_library(name)); + } + + auto write(const std::string& output) { + impl().write(output); + } + void write_with_config(const std::string& output, + const MachO_Binary_write_config_t& config) { + impl().write(output, {config.linkedit}); + } + + auto write_to_bytes() { + std::ostringstream os; + impl().write(os); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + auto write_to_bytes_with_config(const MachO_Binary_write_config_t& config) { + std::ostringstream os; + impl().write(os, {config.linkedit}); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + auto add_command(const MachO_Command& command) { + return details::try_unique(impl().add(command.get())); + } + + auto add_library(const std::string& name) { + return details::try_unique( + impl().add_library(name)->cast() + ); + } + + auto remove_commands_by_type(uint64_t type) { + return impl().remove((LIEF::MachO::LoadCommand::TYPE)type); + } + + static auto is_exported(const MachO_Symbol& symbol) { + return lief_t::is_exported( + static_cast(symbol.get()) + ); + } + + auto filesets() const { + return std::make_unique(impl()); + } + + auto has_filesets() const { + return impl().has_filesets(); + } + + auto fileset_name() const { + return to_unique_string(impl().fileset_name()); + } + + auto fileset_addr() const { + return impl().fileset_addr(); + } + + uint64_t virtual_address_to_offset(uint64_t virtual_address, + uint32_t& error) const { + return details::make_error( + impl().virtual_address_to_offset(virtual_address), error + ); + } + + auto segment_from_offset(uint64_t offset) const { + return details::try_unique( + impl().segment_from_offset(offset) + ); + } + + auto segment_from_virtual_address(uint64_t va) const { + return details::try_unique( + impl().segment_from_virtual_address(va) + ); + } + + auto section_from_virtual_address(uint64_t va) const { + return details::try_unique( + impl().section_from_virtual_address(va) + ); + } + + auto get_segment(const std::string& name) const { + return details::try_unique(impl().get_segment(name)); + } + + auto get_section(const std::string& segname, const std::string& secname) const { + return details::try_unique(impl().get_section(segname, + secname)); + } + + auto fat_offset() const { + return impl().fat_offset(); + } + + auto overlay() const { + return make_span(impl().overlay()); + } + + auto tlv_initial_content_range() const { + auto r = impl().tlv_initial_content_range(); + return Range{r.start, r.end}; + } + + auto is_valid_addr(uint64_t address) const { + return impl().is_valid_addr(address); + } + + auto has_symbol(const std::string& name) const { + return impl().has_symbol(name); + } + + auto get_symbol(const std::string& name) const { + return details::try_unique(impl().get_symbol(name)); + } + + auto has_section(const std::string& name) const { + return impl().has_section(name); + } + + auto section_from_offset(uint64_t offset) const { + return details::try_unique(impl().section_from_offset(offset)); + } + + auto has_segment(const std::string& name) const { + return impl().has_segment(name); + } + + auto has_command_type(uint64_t type) const { + return impl().has((LIEF::MachO::LoadCommand::TYPE)type); + } + + auto get_command_type(uint64_t type) const { + return details::try_unique( + impl().get((LIEF::MachO::LoadCommand::TYPE)type) + ); + } + + auto remove_command(uint32_t index) { + return impl().remove_command(index); + } + + auto remove_section(const std::string& name, bool clear) { + impl().remove_section(name, clear); + } + + void remove_section_seg(const std::string& segname, const std::string& secname, + bool clear) { + impl().remove_section(segname, secname, clear); + } + + auto remove_signature() { + return impl().remove_signature(); + } + + auto remove_symbol(const std::string& name) { + return impl().remove_symbol(name); + } + + auto can_remove(const MachO_Symbol& sym) const { + return impl().can_remove(as(&sym)); + } + + auto can_remove_symbol(const std::string& name) const { + return impl().can_remove_symbol(name); + } + + auto unexport_name(const std::string& name) { + return impl().unexport(name); + } + + auto unexport_symbol(const MachO_Symbol& sym) { + return impl().unexport(as(&sym)); + } + + auto extend(const MachO_Command& command, uint64_t size) { + return impl().extend(command.get(), size); + } + + auto extend_segment(const MachO_SegmentCommand& segment, uint64_t size) { + return impl().extend_segment(as(&segment), size); + } + + auto add_section_default(const MachO_Section& section) { + return details::try_unique( + impl().add_section(as(§ion)) + ); + } + + auto add_exported_function(uint64_t address, const std::string& name) { + return details::try_unique( + impl().add_exported_function(address, name) + ); + } + + auto add_local_symbol(uint64_t address, const std::string& name) { + return details::try_unique(impl().add_local_symbol(address, + name)); + } + + auto shift(uint64_t value, uint32_t& err) { + return details::make_ok_error(impl().shift(value), err); + } + + auto shift_linkedit(uint64_t width, uint32_t& err) { + return details::make_ok_error(impl().shift_linkedit(width), err); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using MachO_Binary_it_commands = MachO_Binary::it_commands; +using MachO_Binary_it_symbols = MachO_Binary::it_symbols; +using MachO_Binary_it_exported_symbols = MachO_Binary::it_exported_symbols; +using MachO_Binary_it_sections = MachO_Binary::it_sections; +using MachO_Binary_it_segments = MachO_Binary::it_segments; +using MachO_Binary_it_libraries = MachO_Binary::it_libraries; +using MachO_Binary_it_lazy_load_dylib_info = MachO_Binary::it_lazy_load_dylib_info; +using MachO_Binary_it_relocations = MachO_Binary::it_relocations; +using MachO_Binary_it_rpaths = MachO_Binary::it_rpaths; +using MachO_Binary_it_sub_clients = MachO_Binary::it_sub_clients; +using MachO_Binary_it_bindings_info = MachO_Binary::it_bindings_info; +using MachO_Binary_it_stubs = MachO_Binary::it_stubs; +using MachO_Binary_it_notes = MachO_Binary::it_notes; +using MachO_Binary_it_fileset_binaries = MachO_Binary::it_fileset_binaries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/BindingInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/BindingInfo.hpp new file mode 100644 index 0000000..f701ed9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/BindingInfo.hpp @@ -0,0 +1,49 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/BindingInfo.hpp" +#include "LIEF/rust/MachO/Dylib.hpp" +#include "LIEF/rust/MachO/SegmentCommand.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" + +class MachO_BindingInfo : public Mirror { + public: + using lief_t = LIEF::MachO::BindingInfo; + using Mirror::Mirror; + + uint64_t address() const { + return get().address(); + } + int64_t addend() const { + return get().addend(); + } + int32_t library_ordinal() const { + return get().library_ordinal(); + } + + auto library() const { + return details::try_unique(get().library()); + } + + auto symbol() const { + return details::try_unique(get().symbol()); + } + + auto segment() const { + return details::try_unique(get().segment()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildToolVersion.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildToolVersion.hpp new file mode 100644 index 0000000..6f22671 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildToolVersion.hpp @@ -0,0 +1,32 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/BuildToolVersion.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_BuildToolVersion : Mirror { + public: + using lief_t = LIEF::MachO::BuildToolVersion; + using Mirror::Mirror; + + auto tool() const { + return as_u32(get().tool()); + } + auto version() const { + return make_unique_vector(details::make_vector(get().version())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildVersion.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildVersion.hpp new file mode 100644 index 0000000..16e65d0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/BuildVersion.hpp @@ -0,0 +1,67 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/BuildVersion.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/MachO/BuildToolVersion.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_BuildVersion : public MachO_Command { + public: + using lief_t = LIEF::MachO::BuildVersion; + + class it_tools + : public ContainerIterator> { + public: + it_tools(const MachO_BuildVersion::lief_t& src) : + ContainerIterator(std::vector(src.tools())) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + MachO_BuildVersion(const lief_t& base) : + MachO_Command(base) {} + + auto sdk() const { + return make_unique_vector(details::make_vector(impl().sdk())); + } + auto minos() const { + return make_unique_vector(details::make_vector(impl().minos())); + } + auto platform() const { + return as_u32(impl().platform()); + } + auto tools() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_BuildVersion_it_tools = MachO_BuildVersion::it_tools; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/ChainedBindingInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/ChainedBindingInfo.hpp new file mode 100644 index 0000000..d43a7b9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/ChainedBindingInfo.hpp @@ -0,0 +1,49 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/ChainedBindingInfo.hpp" +#include "LIEF/rust/MachO/BindingInfo.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_ChainedBindingInfo : public MachO_BindingInfo { + public: + using MachO_BindingInfo::address; + using lief_t = LIEF::MachO::ChainedBindingInfo; + MachO_ChainedBindingInfo(const lief_t& base) : + MachO_BindingInfo(base) {} + + auto format() const { + return as_u32(impl().format()); + } + auto ptr_format() const { + return as_u32(impl().ptr_format()); + } + uint32_t offset() const { + return impl().offset(); + } + auto sign_extended_addend() const { + return impl().sign_extended_addend(); + } + + static auto classof(const MachO_BindingInfo& binding) { + return lief_t::classof(&binding.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignature.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignature.hpp new file mode 100644 index 0000000..ead1e4e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignature.hpp @@ -0,0 +1,46 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/CodeSignature.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_CodeSignature : public MachO_Command { + public: + using lief_t = LIEF::MachO::CodeSignature; + MachO_CodeSignature(const lief_t& base) : + MachO_Command(base) {} + + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignatureDir.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignatureDir.hpp new file mode 100644 index 0000000..2a260ae --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/CodeSignatureDir.hpp @@ -0,0 +1,46 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/CodeSignatureDir.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_CodeSignatureDir : public MachO_Command { + public: + using lief_t = LIEF::MachO::CodeSignatureDir; + MachO_CodeSignatureDir(const lief_t& base) : + MachO_Command(base) {} + + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DataCodeEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DataCodeEntry.hpp new file mode 100644 index 0000000..e5d3c72 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DataCodeEntry.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/DataCodeEntry.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_DataCodeEntry : private Mirror { + public: + using lief_t = LIEF::MachO::DataCodeEntry; + using Mirror::Mirror; + + uint32_t offset() const { + return get().offset(); + } + uint32_t length() const { + return get().length(); + } + auto get_type() const { + return as_u32(get().type()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DataInCode.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DataInCode.hpp new file mode 100644 index 0000000..dad54d2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DataInCode.hpp @@ -0,0 +1,66 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include + +#include "LIEF/MachO/DataInCode.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/MachO/DataCodeEntry.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_DataInCode : public MachO_Command { + public: + using lief_t = LIEF::MachO::DataInCode; + class it_entries : public Iterator { + public: + it_entries(const MachO_DataInCode::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + MachO_DataInCode(const lief_t& base) : + MachO_Command(base) {} + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + auto content() const { + return make_span(impl().content()); + } + + auto entries() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_DataInCode_it_entries = MachO_DataInCode::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldBindingInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldBindingInfo.hpp new file mode 100644 index 0000000..ede0b71 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldBindingInfo.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DyldBindingInfo.hpp" +#include "LIEF/rust/MachO/BindingInfo.hpp" + +class MachO_DyldBindingInfo : public MachO_BindingInfo { + public: + using lief_t = LIEF::MachO::DyldBindingInfo; + MachO_DyldBindingInfo(const lief_t& base) : + MachO_BindingInfo(base) {} + + auto binding_class() const { + return to_int(impl().binding_class()); + } + auto binding_type() const { + return to_int(impl().binding_type()); + } + auto is_non_weak_definition() const { + return impl().is_non_weak_definition(); + } + uint64_t original_offset() const { + return impl().original_offset(); + } + + static auto classof(const MachO_BindingInfo& binding) { + return lief_t::classof(&binding.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldChainedFixups.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldChainedFixups.hpp new file mode 100644 index 0000000..912e87d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldChainedFixups.hpp @@ -0,0 +1,89 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DyldChainedFixups.hpp" +#include "LIEF/rust/MachO/ChainedBindingInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_DyldChainedFixups : public MachO_Command { + public: + using lief_t = LIEF::MachO::DyldChainedFixups; + class it_bindings + : public Iterator { + public: + it_bindings(const MachO_DyldChainedFixups::lief_t& src) : + Iterator(src.bindings()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + MachO_DyldChainedFixups(const lief_t& base) : + MachO_Command(base) {} + + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + uint32_t fixups_version() const { + return impl().fixups_version(); + } + uint32_t starts_offset() const { + return impl().starts_offset(); + } + uint32_t imports_offset() const { + return impl().imports_offset(); + } + uint32_t symbols_offset() const { + return impl().symbols_offset(); + } + uint32_t imports_count() const { + return impl().imports_count(); + } + uint32_t symbols_format() const { + return impl().symbols_format(); + } + auto imports_format() const { + return as_u32(impl().imports_format()); + } + + auto bindings() const { + return std::make_unique(impl()); + } + + auto payload() const { + return make_span(impl().payload()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_DyldChainedFixups_it_bindings = MachO_DyldChainedFixups::it_bindings; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldEnvironment.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldEnvironment.hpp new file mode 100644 index 0000000..8ede25c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldEnvironment.hpp @@ -0,0 +1,39 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DyldEnvironment.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_DyldEnvironment : public MachO_Command { + public: + using lief_t = LIEF::MachO::DyldEnvironment; + MachO_DyldEnvironment(const lief_t& base) : + MachO_Command(base) {} + + auto value() const { + return to_unique_string(impl().value()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldExportsTrie.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldExportsTrie.hpp new file mode 100644 index 0000000..6132d1a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldExportsTrie.hpp @@ -0,0 +1,69 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DyldExportsTrie.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/MachO/ExportInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +#include "LIEF/rust/Span.hpp" +#include + +class MachO_DyldExportsTrie : public MachO_Command { + public: + using lief_t = LIEF::MachO::DyldExportsTrie; + class it_exports + : public Iterator { + public: + it_exports(const MachO_DyldExportsTrie::lief_t& src) : + Iterator(src.exports()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_DyldExportsTrie(const lief_t& base) : + MachO_Command(base) {} + + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + auto content() const { + return make_span(impl().content()); + } + + auto exports() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_DyldExportsTrie_it_exports = MachO_DyldExportsTrie::it_exports; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldInfo.hpp new file mode 100644 index 0000000..91ac86e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DyldInfo.hpp @@ -0,0 +1,93 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include + +#include "LIEF/rust/MachO/DyldBindingInfo.hpp" +#include "LIEF/rust/MachO/ExportInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +#include "LIEF/rust/Span.hpp" +#include + +class MachO_DyldInfo : public MachO_Command { + public: + using lief_t = LIEF::MachO::DyldInfo; + class it_bindings + : public Iterator { + public: + it_bindings(const MachO_DyldInfo::lief_t& src) : + Iterator(src.bindings()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_exports : public Iterator { + public: + it_exports(const MachO_DyldInfo::lief_t& src) : + Iterator(src.exports()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_DyldInfo(const lief_t& base) : + MachO_Command(base) {} + + auto bindings() const { + return std::make_unique(impl()); + } + auto exports() const { + return std::make_unique(impl()); + } + + auto rebase_opcodes() const { + return make_span(impl().rebase_opcodes()); + } + auto bind_opcodes() const { + return make_span(impl().bind_opcodes()); + } + auto weak_bind_opcodes() const { + return make_span(impl().weak_bind_opcodes()); + } + auto lazy_bind_opcodes() const { + return make_span(impl().lazy_bind_opcodes()); + } + auto export_trie() const { + return make_span(impl().export_trie()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_DyldInfo_it_bindings = MachO_DyldInfo::it_bindings; +using MachO_DyldInfo_it_exports = MachO_DyldInfo::it_exports; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylib.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylib.hpp new file mode 100644 index 0000000..cfec694 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylib.hpp @@ -0,0 +1,100 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DylibCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_Dylib : public MachO_Command { + public: + using lief_t = LIEF::MachO::DylibCommand; + MachO_Dylib(const lief_t& base) : + MachO_Command(base) {} + + auto name() const { + return to_unique_string(impl().name()); + } + uint32_t timestamp() const { + return impl().timestamp(); + } + + auto name_offset() const { + return impl().name_offset(); + } + + auto current_version() const { + return make_unique_vector( + details::make_vector(impl().current_version()) + ); + } + + auto compatibility_version() const { + return make_unique_vector( + details::make_vector(impl().compatibility_version()) + ); + } + + auto set_name(const std::string& name) { + impl().name(name); + } + + static auto id_dylib(const std::string& name, uint32_t timestamp, + uint32_t current_version, uint32_t compat_version) { + return std::make_unique( + lief_t::id_dylib(name, timestamp, current_version, compat_version) + ); + } + + static auto load_dylib(const std::string& name, uint32_t timestamp, + uint32_t current_version, uint32_t compat_version) { + return std::make_unique( + lief_t::load_dylib(name, timestamp, current_version, compat_version) + ); + } + + static auto reexport_dylib(const std::string& name, uint32_t timestamp, + uint32_t current_version, uint32_t compat_version) { + return std::make_unique( + lief_t::reexport_dylib(name, timestamp, current_version, compat_version) + ); + } + + static auto weak_dylib(const std::string& name, uint32_t timestamp, + uint32_t current_version, uint32_t compat_version) { + return std::make_unique( + lief_t::weak_dylib(name, timestamp, current_version, compat_version) + ); + } + + static auto lazy_load_dylib(const std::string& name, uint32_t timestamp, + uint32_t current_version, uint32_t compat_version) { + return std::make_unique( + lief_t::lazy_load_dylib(name, timestamp, current_version, compat_version) + ); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylinker.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylinker.hpp new file mode 100644 index 0000000..ae8d351 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Dylinker.hpp @@ -0,0 +1,39 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DylinkerCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_Dylinker : public MachO_Command { + public: + using lief_t = LIEF::MachO::DylinkerCommand; + MachO_Dylinker(const lief_t& base) : + MachO_Command(base) {} + + auto name() const { + return to_unique_string(impl().name()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/DynamicSymbolCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/DynamicSymbolCommand.hpp new file mode 100644 index 0000000..82ddbc1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/DynamicSymbolCommand.hpp @@ -0,0 +1,112 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/DynamicSymbolCommand.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" + +class MachO_DynamicSymbolCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::DynamicSymbolCommand; + MachO_DynamicSymbolCommand(const lief_t& base) : + MachO_Command(base) {} + + class it_indirect_symbols + : public Iterator { + public: + it_indirect_symbols(const MachO_DynamicSymbolCommand::lief_t& src) : + Iterator(src.indirect_symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t idx_local_symbol() const { + return impl().idx_local_symbol(); + } + uint32_t nb_local_symbols() const { + return impl().nb_local_symbols(); + } + uint32_t idx_external_define_symbol() const { + return impl().idx_external_define_symbol(); + } + uint32_t nb_external_define_symbols() const { + return impl().nb_external_define_symbols(); + } + uint32_t idx_undefined_symbol() const { + return impl().idx_undefined_symbol(); + } + uint32_t nb_undefined_symbols() const { + return impl().nb_undefined_symbols(); + } + uint32_t toc_offset() const { + return impl().toc_offset(); + } + uint32_t nb_toc() const { + return impl().nb_toc(); + } + uint32_t module_table_offset() const { + return impl().module_table_offset(); + } + uint32_t nb_module_table() const { + return impl().nb_module_table(); + } + uint32_t external_reference_symbol_offset() const { + return impl().external_reference_symbol_offset(); + } + uint32_t nb_external_reference_symbols() const { + return impl().nb_external_reference_symbols(); + } + uint32_t indirect_symbol_offset() const { + return impl().indirect_symbol_offset(); + } + uint32_t nb_indirect_symbols() const { + return impl().nb_indirect_symbols(); + } + uint32_t external_relocation_offset() const { + return impl().external_relocation_offset(); + } + uint32_t nb_external_relocations() const { + return impl().nb_external_relocations(); + } + uint32_t local_relocation_offset() const { + return impl().local_relocation_offset(); + } + uint32_t nb_local_relocations() const { + return impl().nb_local_relocations(); + } + + auto indirect_symbols() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_DynamicSymbolCommand_it_indirect_symbols = + MachO_DynamicSymbolCommand::it_indirect_symbols; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/EncryptionInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/EncryptionInfo.hpp new file mode 100644 index 0000000..b77dbcf --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/EncryptionInfo.hpp @@ -0,0 +1,45 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/EncryptionInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_EncryptionInfo : public MachO_Command { + using lief_t = LIEF::MachO::EncryptionInfo; + + public: + MachO_EncryptionInfo(const lief_t& base) : + MachO_Command(base) {} + uint32_t crypt_offset() const { + return impl().crypt_offset(); + } + uint32_t crypt_size() const { + return impl().crypt_size(); + } + uint32_t crypt_id() const { + return impl().crypt_id(); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/ExportInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/ExportInfo.hpp new file mode 100644 index 0000000..49ebeab --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/ExportInfo.hpp @@ -0,0 +1,56 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/ExportInfo.hpp" +#include "LIEF/rust/MachO/Dylib.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_ExportInfo : private Mirror { + public: + using lief_t = LIEF::MachO::ExportInfo; + using Mirror::Mirror; + + uint64_t node_offset() const { + return get().node_offset(); + } + uint64_t flags() const { + return get().flags(); + } + uint64_t address() const { + return get().address(); + } + uint64_t other() const { + return get().other(); + } + auto kind() const { + return as_u64(get().kind()); + } + + auto symbol() const { + return details::try_unique(get().symbol()); + } + + auto alias() const { + return details::try_unique(get().alias()); + } + + auto alias_library() const { + return details::try_unique(get().alias_library()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/FatBinary.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/FatBinary.hpp new file mode 100644 index 0000000..b584245 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/FatBinary.hpp @@ -0,0 +1,114 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO.hpp" +#include "LIEF/rust/MachO/Binary.hpp" +#include "LIEF/rust/Mirror.hpp" +#include +#include + +class MachO_ParserConfig { + public: + static auto create() { + return std::make_unique(); + } + + const LIEF::MachO::ParserConfig& conf() const { + return config_; + } + + auto set_parse_dyld_exports(bool value) { + config_.parse_dyld_exports = value; + } + + auto set_parse_dyld_bindings(bool value) { + config_.parse_dyld_bindings = value; + } + + auto set_parse_dyld_rebases(bool value) { + config_.parse_dyld_rebases = value; + } + + auto set_parse_overlay(bool value) { + config_.parse_overlay = value; + } + + auto set_fix_from_memory(bool value) { + config_.fix_from_memory = value; + } + + auto set_from_dyld_shared_cache(bool value) { + config_.from_dyld_shared_cache = value; + } + + private: + LIEF::MachO::ParserConfig config_ = LIEF::MachO::ParserConfig::deep(); +}; + +class MachO_FatBinary : public Mirror { + public: + using Mirror::Mirror; + static auto parse(const std::string& path) { + return details::try_unique(LIEF::MachO::Parser::parse(path)); + } + + static auto parse_with_config(const std::string& path, + const MachO_ParserConfig& config) { + return details::try_unique( + LIEF::MachO::Parser::parse(path, config.conf()) + ); + } + + static auto parse_from_dump(const std::string& path, uint64_t addr) { + return details::try_unique( + LIEF::MachO::Parser::parse_from_dump(path, addr) + ); + } + + static auto parse_from_dump_with_config(const std::string& path, uint64_t addr, + const MachO_ParserConfig& config) { + return details::try_unique( + LIEF::MachO::Parser::parse_from_dump(path, addr, config.conf()) + ); + } + + uint32_t size() const { + return get().size(); + } + + std::unique_ptr binary_at(uint32_t index) const { + if (auto* bin = get().at(index)) { + return std::make_unique(*bin); + } + return nullptr; + } + + std::unique_ptr binary_from_arch(int32_t cpu) const { + if (auto* bin = get().get((LIEF::MachO::Header::CPU_TYPE)cpu)) { + return std::make_unique(*bin); + } + return nullptr; + } + + auto write(const std::string& output) { + impl().write(output); + } + + private: + LIEF::MachO::FatBinary& impl() { + return const_cast(get()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Fileset.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Fileset.hpp new file mode 100644 index 0000000..166f377 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Fileset.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include + +#include "LIEF/MachO/FilesetCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_Fileset : public MachO_Command { + public: + using lief_t = LIEF::MachO::FilesetCommand; + MachO_Fileset(const lief_t& cmd) : + MachO_Command(cmd) {} + + auto name() const { + return to_unique_string(impl().name()); + } + uint64_t virtual_address() const { + return impl().virtual_address(); + } + uint64_t file_offset() const { + return impl().file_offset(); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionStarts.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionStarts.hpp new file mode 100644 index 0000000..d64607c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionStarts.hpp @@ -0,0 +1,57 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include + +#include "LIEF/MachO/FunctionStarts.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_FunctionStarts : public MachO_Command { + public: + using lief_t = LIEF::MachO::FunctionStarts; + MachO_FunctionStarts(const lief_t& base) : + MachO_Command(base) {} + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + auto functions() const { + return make_unique_vector(impl().functions()); + } + + auto content() const { + return make_span(impl().content()); + } + + auto add_function(uint64_t address) { + impl().add_function(address); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariantFixups.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariantFixups.hpp new file mode 100644 index 0000000..4e9cfdb --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariantFixups.hpp @@ -0,0 +1,108 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/FunctionVariantFixups.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/MachO/SegmentCommand.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_FunctionVariantFixups_Fixup + : public Mirror { + public: + using lief_t = LIEF::MachO::FunctionVariantFixups::Fixup; + using Mirror::Mirror; + + auto seg_offset() const { + return get().seg_offset(); + } + auto seg_index() const { + return get().seg_index(); + } + auto variant_index() const { + return get().variant_index(); + } + auto pac_auth() const { + return get().pac_auth(); + } + auto pac_address() const { + return get().pac_address(); + } + auto pac_key() const { + return get().pac_key(); + } + auto pac_diversity() const { + return get().pac_diversity(); + } + + auto segment() const { + return details::try_unique(get().segment()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class MachO_FunctionVariantFixups : public MachO_Command { + public: + using lief_t = LIEF::MachO::FunctionVariantFixups; + + class it_fixups + : public Iterator { + public: + it_fixups(const MachO_FunctionVariantFixups::lief_t& src) : + Iterator(src.fixups()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_FunctionVariantFixups(const lief_t& base) : + MachO_Command(base) {} + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + auto fixups() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_FunctionVariantFixups_it_fixups = + MachO_FunctionVariantFixups::it_fixups; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariants.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariants.hpp new file mode 100644 index 0000000..c19024a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/FunctionVariants.hpp @@ -0,0 +1,136 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/FunctionVariants.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_FunctionVariants_RuntimeTableEntry + : public Mirror { + public: + using lief_t = LIEF::MachO::FunctionVariants::RuntimeTableEntry; + using Mirror::Mirror; + + auto implementation() const { + return get().impl(); + } + auto another_table() const { + return get().another_table(); + } + auto flag_bit_nums() const { + return make_span(get().flag_bit_nums()); + } + auto flags() const { + auto out = make_unique_vector(); + const std::vector flags = get().flags(); + std::transform(flags.begin(), flags.end(), std::back_inserter(*out), + [](lief_t::FLAGS f) { return (uint32_t)f; }); + return out; + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class MachO_FunctionVariants_RuntimeTable + : public Mirror { + public: + using lief_t = LIEF::MachO::FunctionVariants::RuntimeTable; + using Mirror::Mirror; + + class it_entries : public Iterator { + public: + it_entries(const MachO_FunctionVariants_RuntimeTable::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto kind() const { + return as_u32(get().kind()); + } + auto offset() const { + return get().offset(); + } + auto entries() const { + return std::make_unique(get()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +using MachO_FunctionVariants_RuntimeTable_it_entries = + MachO_FunctionVariants_RuntimeTable::it_entries; + +class MachO_FunctionVariants : public MachO_Command { + public: + using lief_t = LIEF::MachO::FunctionVariants; + + class it_runtime_table : public Iterator { + public: + it_runtime_table(const MachO_FunctionVariants::lief_t& src) : + Iterator(src.runtime_table()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_FunctionVariants(const lief_t& base) : + MachO_Command(base) {} + + auto data_offset() const { + return impl().data_offset(); + } + auto data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + auto runtime_table() const { + return std::make_unique(impl()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_FunctionVariants_it_runtime_table = + MachO_FunctionVariants::it_runtime_table; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Header.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Header.hpp new file mode 100644 index 0000000..5857903 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Header.hpp @@ -0,0 +1,57 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Header.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_Header : private Mirror { + public: + using lief_t = LIEF::MachO::Header; + using Mirror::Mirror; + + auto magic() const { + return to_int(get().magic()); + } + int32_t cpu_type() const { + return to_int(get().cpu_type()); + } + auto cpu_subtype() const { + return get().cpu_subtype(); + } + auto file_type() const { + return to_int(get().file_type()); + } + auto nb_cmds() const { + return get().nb_cmds(); + } + auto sizeof_cmds() const { + return get().sizeof_cmds(); + } + auto flags() const { + return get().flags(); + } + auto reserved() const { + return get().reserved(); + } + + auto is_32bit() const { + return get().is_32bit(); + } + auto is_64bit() const { + return get().is_64bit(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/IndirectBindingInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/IndirectBindingInfo.hpp new file mode 100644 index 0000000..eb951e6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/IndirectBindingInfo.hpp @@ -0,0 +1,33 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/MachO/IndirectBindingInfo.hpp" +#include "LIEF/rust/MachO/BindingInfo.hpp" + +class MachO_IndirectBindingInfo : public MachO_BindingInfo { + public: + using lief_t = LIEF::MachO::IndirectBindingInfo; + MachO_IndirectBindingInfo(const lief_t& base) : + MachO_BindingInfo(base) {} + + static auto classof(const MachO_BindingInfo& binding) { + return lief_t::classof(&binding.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/LazyLoadDylibInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/LazyLoadDylibInfo.hpp new file mode 100644 index 0000000..f47379c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/LazyLoadDylibInfo.hpp @@ -0,0 +1,157 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/LazyLoadDylibInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_LazyLoadDylibInfo_Fixup + : public Mirror { + public: + using lief_t = LIEF::MachO::LazyLoadDylibInfo::Fixup; + using Mirror::Mirror; + + auto address() const { + return get().address(); + } + auto ordinal() const { + return get().ordinal(); + } + auto symbol() const { + return to_unique_string(get().symbol()); + } + auto is_auth() const { + return get().is_auth(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class MachO_LazyLoadDylibInfo : public MachO_Command { + public: + using lief_t = LIEF::MachO::LazyLoadDylibInfo; + + class it_fixups + : public Iterator { + public: + it_fixups(const MachO_LazyLoadDylibInfo::lief_t& src) : + Iterator(src.fixups()) {} + auto next() { // NOLINT + return Iterator::next(); + } + auto size() const { // NOLINT + return Iterator::size(); + } + }; + + MachO_LazyLoadDylibInfo(const lief_t& base) : + MachO_Command(base) {} + + auto data_offset() const { + return impl().data_offset(); + } + auto data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + auto load_path() const { + return to_unique_string(impl().load_path()); + } + + auto flag_image_offset() const { + return impl().flag_image_offset(); + } + + auto flags() const { + return impl().flags(); + } + + auto may_be_missing() const { + return impl().may_be_missing(); + } + + auto pointer_format() const { + return impl().pointer_format(); + } + + auto chain_start_image_offset() const { + return impl().chain_start_image_offset(); + } + + auto symbols() const { + return make_unique_vector(impl().symbols()); + } + + auto fixups() const { + return std::make_unique(impl()); + } + + void set_load_path(const std::string& value) { + impl().load_path(value); + } + + void set_flag_image_offset(uint32_t value) { + impl().flag_image_offset(value); + } + + void set_flags(uint16_t value) { + impl().flags(value); + } + + void set_may_be_missing(bool value) { + impl().may_be_missing(value); + } + + void set_pointer_format(uint16_t value) { + impl().pointer_format(value); + } + + void set_chain_start_image_offset(uint32_t value) { + impl().chain_start_image_offset(value); + } + + void add_symbol(const std::string& value) { + impl().add_symbol(value); + } + + void clear_symbols() { + impl().clear_symbols(); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using MachO_LazyLoadDylibInfo_it_fixups = MachO_LazyLoadDylibInfo::it_fixups; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/LinkerOptHint.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/LinkerOptHint.hpp new file mode 100644 index 0000000..7831ee2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/LinkerOptHint.hpp @@ -0,0 +1,46 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/LinkerOptHint.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_LinkerOptHint : public MachO_Command { + public: + using lief_t = LIEF::MachO::LinkerOptHint; + MachO_LinkerOptHint(const lief_t& base) : + MachO_Command(base) {} + + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/LoadCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/LoadCommand.hpp new file mode 100644 index 0000000..13b44f0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/LoadCommand.hpp @@ -0,0 +1,42 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/LoadCommand.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_Command : public Mirror { + public: + using lief_t = LIEF::MachO::LoadCommand; + using Mirror::Mirror; + + uint32_t size() const { + return get().size(); + } + uint64_t command_offset() const { + return get().command_offset(); + } + + + auto data() const { + return make_span(get().data()); + } + + auto cmd_type() const { + return to_int(get().command()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Main.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Main.hpp new file mode 100644 index 0000000..a388983 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Main.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/MainCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_Main : public MachO_Command { + public: + using lief_t = LIEF::MachO::MainCommand; + MachO_Main(const lief_t& base) : + MachO_Command(base) {} + uint64_t entrypoint() const { + return impl().entrypoint(); + } + uint64_t stack_size() const { + return impl().stack_size(); + } + + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/NoteCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/NoteCommand.hpp new file mode 100644 index 0000000..92d0437 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/NoteCommand.hpp @@ -0,0 +1,57 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/NoteCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_NoteCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::NoteCommand; + MachO_NoteCommand(const lief_t& base) : + MachO_Command(base) {} + + auto note_offset() const { + return impl().note_offset(); + } + auto note_size() const { + return impl().note_size(); + } + + Span owner() const { + return make_span(impl().owner()); + } + + auto set_note_offset(uint64_t value) { + impl().note_offset(value); + } + + auto set_note_size(uint64_t value) { + impl().note_size(value); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/RPathCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/RPathCommand.hpp new file mode 100644 index 0000000..7985f08 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/RPathCommand.hpp @@ -0,0 +1,56 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/RPathCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_RPathCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::RPathCommand; + MachO_RPathCommand(const lief_t& base) : + MachO_Command(base) {} + MachO_RPathCommand(std::unique_ptr impl) : + MachO_Command(std::move(impl)) {} + + static auto create(const std::string& path) { + return std::make_unique(std::make_unique(path)); + } + + auto path() const { + return to_unique_string(impl().path()); + } + auto path_offset() const { + return impl().path_offset(); + } + + auto set_path(const std::string& path) { + impl().path(path); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Relocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Relocation.hpp new file mode 100644 index 0000000..bdcfd9b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Relocation.hpp @@ -0,0 +1,57 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Relocation.hpp" +#include "LIEF/rust/Abstract/Relocation.hpp" +#include "LIEF/rust/MachO/Section.hpp" +#include "LIEF/rust/MachO/SegmentCommand.hpp" +#include "LIEF/rust/MachO/Symbol.hpp" + +#include + +class MachO_Relocation : public AbstractRelocation { + public: + using lief_t = LIEF::MachO::Relocation; + MachO_Relocation(const lief_t& reloc) : + AbstractRelocation(reloc) {} + + auto is_pc_relative() const { + return impl().is_pc_relative(); + } + auto architecture() const { + return as_u32(impl().architecture()); + } + auto origin() const { + return as_u32(impl().origin()); + } + + auto symbol() const { + return details::try_unique(impl().symbol()); + } + + auto section() const { + return details::try_unique(impl().section()); + } + + auto segment() const { + return details::try_unique(impl().segment()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationDyld.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationDyld.hpp new file mode 100644 index 0000000..8918329 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationDyld.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/RelocationDyld.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" + +class MachO_RelocationDyld : public MachO_Relocation { + public: + using lief_t = LIEF::MachO::RelocationDyld; + MachO_RelocationDyld(const lief_t& base) : + MachO_Relocation(base) {} + + static auto classof(const MachO_Relocation& reloc) { + return lief_t::classof( + *static_cast(&reloc.get()) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationFixup.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationFixup.hpp new file mode 100644 index 0000000..c292ebe --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationFixup.hpp @@ -0,0 +1,49 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/RelocationFixup.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" + +class MachO_RelocationFixup : public MachO_Relocation { + public: + using lief_t = LIEF::MachO::RelocationFixup; + MachO_RelocationFixup(const lief_t& base) : + MachO_Relocation(base) {} + + uint64_t target() const { + return impl().target(); + } + uint32_t ptr_format() const { + return as_u32(impl().ptr_format()); + } + uint32_t offset() const { + return impl().offset(); + } + uint32_t next() const { + return impl().next(); + } + + static auto classof(const MachO_Relocation& reloc) { + return lief_t::classof( + *static_cast(&reloc.get()) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationObject.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationObject.hpp new file mode 100644 index 0000000..74f2cc0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/RelocationObject.hpp @@ -0,0 +1,40 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/RelocationObject.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" + +class MachO_RelocationObject : public MachO_Relocation { + public: + using lief_t = LIEF::MachO::RelocationObject; + MachO_RelocationObject(const lief_t& base) : + MachO_Relocation(base) {} + + auto is_scattered() const { + return impl().is_scattered(); + } + + static auto classof(const MachO_Relocation& reloc) { + return lief_t::classof( + *static_cast(&reloc.get()) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Routine.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Routine.hpp new file mode 100644 index 0000000..2d0e1ad --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Routine.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Routine.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_Routine : public MachO_Command { + public: + using lief_t = LIEF::MachO::Routine; + MachO_Routine(const lief_t& base) : + MachO_Command(base) {} + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + auto init_address() const { + return impl().init_address(); + } + auto init_module() const { + return impl().init_module(); + } + + auto reserved1() const { + return impl().reserved1(); + } + auto reserved2() const { + return impl().reserved2(); + } + auto reserved3() const { + return impl().reserved3(); + } + auto reserved4() const { + return impl().reserved4(); + } + auto reserved5() const { + return impl().reserved5(); + } + auto reserved6() const { + return impl().reserved6(); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Section.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Section.hpp new file mode 100644 index 0000000..1429a7c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Section.hpp @@ -0,0 +1,100 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Section.hpp" +#include "LIEF/rust/Abstract/Section.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_SegmentCommand; +class MachO_Relocation; + +class MachO_Section : public AbstractSection { + public: + using lief_t = LIEF::MachO::Section; + MachO_Section(const lief_t& sec) : + AbstractSection(sec) {} + + class it_relocations + : public Iterator { + public: + it_relocations(const MachO_Section::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto segment_name() const { + return to_unique_string(impl().segment_name()); + } + auto address() const { + return impl().address(); + } + auto alignment() const { + return impl().alignment(); + } + auto relocation_offset() const { + return impl().relocation_offset(); + } + auto numberof_relocations() const { + return impl().numberof_relocations(); + } + auto flags() const { + return as_u64(impl().flags()); + } + auto section_type() const { + return as_u64(impl().type()); + } + auto reserved1() const { + return impl().reserved1(); + } + auto reserved2() const { + return impl().reserved2(); + } + auto reserved3() const { + return impl().reserved3(); + } + + auto raw_flags() const { + return impl().raw_flags(); + } + + auto segment() const { + return details::try_unique(impl().segment()); + } + auto relocations() const { + return std::make_unique(impl()); + } + + auto has_segment() const { + return impl().has_segment(); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using MachO_Section_it_relocations = MachO_Section::it_relocations; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentCommand.hpp new file mode 100644 index 0000000..02b8ee4 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentCommand.hpp @@ -0,0 +1,115 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/SegmentCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/MachO/Relocation.hpp" +#include "LIEF/rust/MachO/Section.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_SegmentCommand : public MachO_Command { + using lief_t = LIEF::MachO::SegmentCommand; + + public: + class it_relocations + : public Iterator { + public: + it_relocations(const MachO_SegmentCommand::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_sections + : public Iterator { + public: + it_sections(const MachO_SegmentCommand::lief_t& src) : + Iterator(src.sections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + MachO_SegmentCommand(const lief_t& base) : + MachO_Command(base) {} + + auto name() const { + return to_unique_string(impl().name()); + } + uint64_t virtual_address() const { + return impl().virtual_address(); + } + uint64_t virtual_size() const { + return impl().virtual_size(); + } + uint64_t file_size() const { + return impl().file_size(); + } + uint64_t file_offset() const { + return impl().file_offset(); + } + uint32_t max_protection() const { + return impl().max_protection(); + } + uint32_t init_protection() const { + return impl().init_protection(); + } + uint32_t numberof_sections() const { + return impl().numberof_sections(); + } + uint32_t flags() const { + return impl().flags(); + } + auto content() const { + return make_span(impl().content()); + } + + auto sections() const { + return std::make_unique(impl()); + } + auto relocations() const { + return std::make_unique(impl()); + } + + auto index() const { + return impl().index(); + } + + auto get_section(const std::string& name) const { + return details::try_unique(impl().get_section(name)); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using MachO_SegmentCommand_it_relocations = MachO_SegmentCommand::it_relocations; +using MachO_SegmentCommand_it_sections = MachO_SegmentCommand::it_sections; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentSplitInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentSplitInfo.hpp new file mode 100644 index 0000000..e8d7093 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SegmentSplitInfo.hpp @@ -0,0 +1,44 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/SegmentSplitInfo.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_SegmentSplitInfo : public MachO_Command { + public: + using lief_t = LIEF::MachO::SegmentSplitInfo; + MachO_SegmentSplitInfo(const lief_t& base) : + MachO_Command(base) {} + uint32_t data_offset() const { + return impl().data_offset(); + } + uint32_t data_size() const { + return impl().data_size(); + } + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SourceVersion.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SourceVersion.hpp new file mode 100644 index 0000000..f2dbc14 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SourceVersion.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/SourceVersion.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_SourceVersion : public MachO_Command { + public: + using lief_t = LIEF::MachO::SourceVersion; + MachO_SourceVersion(const lief_t& base) : + MachO_Command(base) {} + auto version() const { + return make_unique_vector(details::make_vector(impl().version())); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Stub.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Stub.hpp new file mode 100644 index 0000000..96608fa --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Stub.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Stub.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/error.hpp" + +class MachO_Stub : public Mirror { + public: + using lief_t = LIEF::MachO::Stub; + using Mirror::Mirror; + + auto address() const { + return get().address(); + } + Span raw() const { + return make_span(get().raw()); + } + + uint64_t target(uint32_t& err) const { + return details::make_error(get().target(), err); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SubClient.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SubClient.hpp new file mode 100644 index 0000000..6efb772 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SubClient.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/SubClient.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_SubClient : public MachO_Command { + public: + using lief_t = LIEF::MachO::SubClient; + MachO_SubClient(const lief_t& base) : + MachO_Command(base) {} + auto client() const { + return to_unique_string(impl().client()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SubFramework.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SubFramework.hpp new file mode 100644 index 0000000..94ac647 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SubFramework.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/SubFramework.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/helpers.hpp" + +class MachO_SubFramework : public MachO_Command { + public: + using lief_t = LIEF::MachO::SubFramework; + MachO_SubFramework(const lief_t& base) : + MachO_Command(base) {} + auto umbrella() const { + return to_unique_string(impl().umbrella()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/Symbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/Symbol.hpp new file mode 100644 index 0000000..2329ef1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/Symbol.hpp @@ -0,0 +1,71 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/Symbol.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/MachO/Dylib.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/visibility.h" + +class MachO_ExportInfo; +class MachO_BindingInfo; + +class MachO_Symbol : public AbstractSymbol { + using lief_t = LIEF::MachO::Symbol; + + public: + MachO_Symbol(const lief_t& sym) : + AbstractSymbol(sym) {} + + uint8_t get_type() const { + return impl().raw_type(); + } + uint8_t numberof_sections() const { + return impl().numberof_sections(); + } + uint16_t description() const { + return impl().description(); + } + auto origin() const { + return as_u32(impl().origin()); + } + auto category() const { + return as_u32(impl().category()); + } + auto is_external() const { + return impl().is_external(); + } + + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + LIEF_API std::unique_ptr export_info() const; + LIEF_API std::unique_ptr binding_info() const; + + auto library() const { + return details::try_unique(impl().library()); + } + + int32_t library_ordinal() const { + return impl().library_ordinal(); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/SymbolCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/SymbolCommand.hpp new file mode 100644 index 0000000..7d95794 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/SymbolCommand.hpp @@ -0,0 +1,61 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/SymbolCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_SymbolCommand : public MachO_Command { + using lief_t = LIEF::MachO::SymbolCommand; + + public: + MachO_SymbolCommand(const lief_t& base) : + MachO_Command(base) {} + uint32_t symbol_offset() const { + return impl().symbol_offset(); + } + uint32_t numberof_symbols() const { + return impl().numberof_symbols(); + } + uint32_t strings_offset() const { + return impl().strings_offset(); + } + uint32_t strings_size() const { + return impl().strings_size(); + } + uint32_t original_str_size() const { + return impl().original_str_size(); + } + uint32_t original_nb_symbols() const { + return impl().original_nb_symbols(); + } + + auto symbol_table() const { + return make_span(impl().symbol_table()); + } + auto string_table() const { + return make_span(impl().string_table()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadCommand.hpp new file mode 100644 index 0000000..9ef0121 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadCommand.hpp @@ -0,0 +1,51 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/ThreadCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_ThreadCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::ThreadCommand; + MachO_ThreadCommand(const lief_t& base) : + MachO_Command(base) {} + auto flavor() const { + return impl().flavor(); + } + auto count() const { + return impl().count(); + } + int32_t architecture() const { + return to_int(impl().architecture()); + } + auto pc() const { + return impl().pc(); + } + + auto state() const { + return make_span(impl().state()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadLocalVariables.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadLocalVariables.hpp new file mode 100644 index 0000000..5f0eed3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/ThreadLocalVariables.hpp @@ -0,0 +1,90 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/ThreadLocalVariables.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/MachO/Section.hpp" +#include "LIEF/rust/Mirror.hpp" + +class MachO_ThreadLocalVariables_Thunk + : public Mirror { + public: + using lief_t = LIEF::MachO::ThreadLocalVariables::Thunk; + using Mirror::Mirror; + + auto func() const { + return get().func; + } + auto key() const { + return get().key; + } + auto offset() const { + return get().offset; + } +}; + +class MachO_ThreadLocalVariables : public MachO_Section { + public: + using lief_t = LIEF::MachO::ThreadLocalVariables; + + class it_thunks + : public RandomRangeIterator { + public: + it_thunks(const MachO_ThreadLocalVariables::lief_t& src) : + RandomRangeIterator(src.thunks()) {} + auto next() { + return RandomRangeIterator::next(); + } + auto size() const { + return RandomRangeIterator::size(); + } + }; + + MachO_ThreadLocalVariables(const lief_t& base) : + MachO_Section(base) {} + + auto nb_thunks() const { + return impl().nb_thunks(); + } + + auto thunks() const { + return std::make_unique(impl()); + } + + auto get_thunk(uint64_t idx) const { + return details::try_unique(impl().get(idx)); + } + + auto set_thunk(uint64_t idx, uint64_t func, uint64_t key, uint64_t offset) { + impl().set(idx, lief_t::Thunk{func, key, offset}); + } + + static auto classof(const MachO_Section& sec) { + return lief_t::classof(&as(&sec)); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using MachO_ThreadLocalVariables_it_thunks = MachO_ThreadLocalVariables::it_thunks; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/TwoLevelHints.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/TwoLevelHints.hpp new file mode 100644 index 0000000..0904f7c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/TwoLevelHints.hpp @@ -0,0 +1,46 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/TwoLevelHints.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" +#include "LIEF/rust/Span.hpp" + +class MachO_TwoLevelHints : public MachO_Command { + public: + using lief_t = LIEF::MachO::TwoLevelHints; + MachO_TwoLevelHints(const lief_t& base) : + MachO_Command(base) {} + + uint32_t offset() const { + return impl().offset(); + } + uint32_t original_nb_hints() const { + return impl().original_nb_hints(); + } + + auto content() const { + return make_span(impl().content()); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/UUIDCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/UUIDCommand.hpp new file mode 100644 index 0000000..0c139f3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/UUIDCommand.hpp @@ -0,0 +1,39 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/UUIDCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_UUIDCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::UUIDCommand; + MachO_UUIDCommand(const lief_t& base) : + MachO_Command(base) {} + + auto uuid() const { + return make_unique_vector(details::make_vector(impl().uuid())); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/UnknownCommand.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/UnknownCommand.hpp new file mode 100644 index 0000000..1b14968 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/UnknownCommand.hpp @@ -0,0 +1,39 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/UnknownCommand.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_UnknownCommand : public MachO_Command { + public: + using lief_t = LIEF::MachO::UnknownCommand; + MachO_UnknownCommand(const lief_t& base) : + MachO_Command(base) {} + + auto original_command() const { + return impl().original_command(); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/VersionMin.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/VersionMin.hpp new file mode 100644 index 0000000..7f0cfd1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/VersionMin.hpp @@ -0,0 +1,43 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include "LIEF/MachO/VersionMin.hpp" +#include "LIEF/rust/MachO/LoadCommand.hpp" + +class MachO_VersionMin : public MachO_Command { + public: + using lief_t = LIEF::MachO::VersionMin; + MachO_VersionMin(const lief_t& base) : + MachO_Command(base) {} + + auto version() const { + return make_unique_vector(details::make_vector(impl().version())); + } + + auto sdk() const { + return make_unique_vector(details::make_vector(impl().sdk())); + } + + static auto classof(const MachO_Command& cmd) { + return lief_t::classof(&cmd.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/MachO/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/MachO/utils.hpp new file mode 100644 index 0000000..ae3fcde --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/MachO/utils.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/MachO/utils.hpp" +#include "LIEF/rust/MachO/Binary.hpp" +#include "LIEF/rust/MachO/FatBinary.hpp" +#include + +class MachO_Utils { + public: + static auto is_macho(const std::string& file) { + return LIEF::MachO::is_macho(file); + } + + static auto is_fat(const std::string& file) { + return LIEF::MachO::is_fat(file); + } + + static auto is_64(const std::string& file) { + return LIEF::MachO::is_64(file); + } + + static auto check_layout(const MachO_Binary& bin, std::string* error) { + return LIEF::MachO::check_layout( + static_cast(bin.get()), error + ); + } + + static auto check_layout_fat(const MachO_FatBinary& bin, std::string* error) { + return LIEF::MachO::check_layout( + static_cast(bin.get()), error + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Mirror.hpp b/vendor/lief/api/rust/include/LIEF/rust/Mirror.hpp new file mode 100644 index 0000000..12746a6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Mirror.hpp @@ -0,0 +1,107 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/canbe_unique.hpp" +#include "LIEF/errors.hpp" +#include +#include +#include +#include +#include + +template +class Mirror { + public: + Mirror(T& impl) : + impl_(impl) {} + Mirror(const T& impl) : + impl_(impl) {} + Mirror(T&& impl) : + Mirror(std::make_unique(std::move(impl))) {} + Mirror(std::unique_ptr impl) : + impl_(std::move(impl)) {} + + T& get() { + return *impl_; + } + const T& get() const { + return *impl_; + } + T& force_get() const { + return const_cast(*impl_); + } + + private: + LIEF::details::canbe_unique impl_; +}; + +template +const To& as(const From* thiz) { + return static_cast(thiz->get()); +} + +template +To& as(From* thiz) { + return static_cast(thiz->get()); +} + +namespace details { +template +inline std::string to_string(const T& value) { + std::ostringstream oss; + oss << value; + return oss.str(); +} + +template +inline std::unique_ptr try_unique(const V* value) { + return value ? std::make_unique(*value) : nullptr; +} + +template +inline std::unique_ptr try_unique(std::unique_ptr value) { + return value ? std::make_unique(std::move(value)) : nullptr; +} + +template +inline std::unique_ptr try_unique(std::unique_ptr value) { + return try_unique(std::unique_ptr(const_cast(value.release()))); +} + +template +inline std::unique_ptr try_unique(std::optional value) { + return value ? std::make_unique(std::move(*value)) : nullptr; +} + +template +inline std::unique_ptr from_result(const LIEF::result value) { + return value ? std::make_unique(std::move(*value)) : nullptr; +} + +// Note(romain): It looks like cxx can't generate a std::vector<> with any integer +// A C++ std::vector was found containing some type that cxx can't accommodate as a +// vector element (unsigned short) Not ideal but let's promote to uint64_t which is +// supported +template +inline auto make_vector(const std::array& array) { + return std::vector(std::begin(array), std::end(array)); +} + +template +inline auto make_vector(const std::pair& p) { + return std::vector{p.first, p.second}; +} + +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC.hpp new file mode 100644 index 0000000..b851d0c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC.hpp @@ -0,0 +1,22 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/ObjC/Class.hpp" +#include "LIEF/rust/ObjC/DeclOpt.hpp" +#include "LIEF/rust/ObjC/IVar.hpp" +#include "LIEF/rust/ObjC/Metadata.hpp" +#include "LIEF/rust/ObjC/Method.hpp" +#include "LIEF/rust/ObjC/Property.hpp" +#include "LIEF/rust/ObjC/Protocol.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Category.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Category.hpp new file mode 100644 index 0000000..dbd9886 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Category.hpp @@ -0,0 +1,99 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Category.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/ObjC/DeclOpt.hpp" +#include "LIEF/rust/ObjC/Method.hpp" +#include "LIEF/rust/ObjC/Property.hpp" +#include "LIEF/rust/ObjC/Protocol.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_Category : private Mirror { + public: + using lief_t = LIEF::objc::Category; + using Mirror::Mirror; + + class it_methods + : public ForwardIterator { + public: + it_methods(const ObjC_Category::lief_t& src) : + ForwardIterator(src.methods()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_protocols + : public ForwardIterator { + public: + it_protocols(const ObjC_Category::lief_t& src) : + ForwardIterator(src.protocols()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_properties + : public ForwardIterator { + public: + it_properties(const ObjC_Category::lief_t& src) : + ForwardIterator(src.properties()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto name() const { + return to_unique_string(get().name()); + } + auto class_name() const { + return to_unique_string(get().class_name()); + } + + auto methods() const { + return std::make_unique(get()); + } + auto protocols() const { + return std::make_unique(get()); + } + auto properties() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const ObjC_DeclOpt& opt) const { + return to_unique_string(get().to_decl(from_rust_declopt(opt))); + } +}; + +using ObjC_Category_it_methods = ObjC_Category::it_methods; +using ObjC_Category_it_protocols = ObjC_Category::it_protocols; +using ObjC_Category_it_properties = ObjC_Category::it_properties; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Class.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Class.hpp new file mode 100644 index 0000000..eb4f9a7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Class.hpp @@ -0,0 +1,131 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Class.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/ObjC/DeclOpt.hpp" +#include "LIEF/rust/ObjC/IVar.hpp" +#include "LIEF/rust/ObjC/Method.hpp" +#include "LIEF/rust/ObjC/Property.hpp" +#include "LIEF/rust/ObjC/Protocol.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_Class : private Mirror { + public: + using lief_t = LIEF::objc::Class; + using Mirror::Mirror; + + class it_methods + : public ForwardIterator { + public: + it_methods(const ObjC_Class::lief_t& src) : + ForwardIterator(src.methods()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_protocols + : public ForwardIterator { + public: + it_protocols(const ObjC_Class::lief_t& src) : + ForwardIterator(src.protocols()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_properties + : public ForwardIterator { + public: + it_properties(const ObjC_Class::lief_t& src) : + ForwardIterator(src.properties()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_ivars : public ForwardIterator { + public: + it_ivars(const ObjC_Class::lief_t& src) : + ForwardIterator(src.ivars()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto name() const { + return to_unique_string(get().name()); + } + auto demangled_name() const { + return to_unique_string(get().demangled_name()); + } + auto is_meta() const { + return get().is_meta(); + } + + auto super_class() const { + return details::try_unique(get().super_class()); + } + + auto super_name() const { + return to_unique_string(get().super_name()); + } + + auto demangled_super_name() const { + return to_unique_string(get().demangled_super_name()); + } + + auto methods() const { + return std::make_unique(get()); + } + auto protocols() const { + return std::make_unique(get()); + } + auto properties() const { + return std::make_unique(get()); + } + auto ivars() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const ObjC_DeclOpt& opt) const { + return to_unique_string(get().to_decl(from_rust_declopt(opt))); + } +}; + +using ObjC_Class_it_methods = ObjC_Class::it_methods; +using ObjC_Class_it_protocols = ObjC_Class::it_protocols; +using ObjC_Class_it_properties = ObjC_Class::it_properties; +using ObjC_Class_it_ivars = ObjC_Class::it_ivars; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/DeclOpt.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/DeclOpt.hpp new file mode 100644 index 0000000..e38f8cf --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/DeclOpt.hpp @@ -0,0 +1,29 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/DeclOpt.hpp" + +class ObjC_DeclOpt { + public: + bool show_annotations = true; +}; + +inline ObjC_DeclOpt make_declopt(const LIEF::objc::DeclOpt& opt) { + return ObjC_DeclOpt{/* .show_annotations = */ opt.show_annotations}; +} + +inline LIEF::objc::DeclOpt from_rust_declopt(const ObjC_DeclOpt& opt) { + return LIEF::objc::DeclOpt{/* .show_annotations = */ opt.show_annotations}; +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/IVar.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/IVar.hpp new file mode 100644 index 0000000..e110290 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/IVar.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/IVar.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_IVar : private Mirror { + public: + using lief_t = LIEF::objc::IVar; + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + auto mangled_type() const { + return to_unique_string(get().mangled_type()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Metadata.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Metadata.hpp new file mode 100644 index 0000000..dfdd162 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Metadata.hpp @@ -0,0 +1,102 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Metadata.hpp" +#include "LIEF/rust/Mirror.hpp" + +#include "LIEF/rust/ObjC/Category.hpp" +#include "LIEF/rust/ObjC/Class.hpp" +#include "LIEF/rust/ObjC/DeclOpt.hpp" +#include "LIEF/rust/ObjC/Protocol.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_Metadata : private Mirror { + public: + using lief_t = LIEF::objc::Metadata; + using Mirror::Mirror; + + class it_classes + : public ForwardIterator { + public: + it_classes(const ObjC_Metadata::lief_t& src) : + ForwardIterator(src.classes()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_protocols + : public ForwardIterator { + public: + it_protocols(const ObjC_Metadata::lief_t& src) : + ForwardIterator(src.protocols()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_categories + : public ForwardIterator { + public: + it_categories(const ObjC_Metadata::lief_t& src) : + ForwardIterator(src.categories()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto get_class(const std::string& name) const { + return details::try_unique(get().get_class(name)); + } + + auto get_protocol(const std::string& name) const { + return details::try_unique(get().get_protocol(name)); + } + + auto classes() const { + return std::make_unique(get()); + } + + auto protocols() const { + return std::make_unique(get()); + } + + auto categories() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const ObjC_DeclOpt& opt) const { + return to_unique_string(get().to_decl(from_rust_declopt(opt))); + } +}; + +using ObjC_Metadata_it_classes = ObjC_Metadata::it_classes; +using ObjC_Metadata_it_protocols = ObjC_Metadata::it_protocols; +using ObjC_Metadata_it_categories = ObjC_Metadata::it_categories; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Method.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Method.hpp new file mode 100644 index 0000000..c6c20ea --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Method.hpp @@ -0,0 +1,37 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Method.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_Method : private Mirror { + public: + using lief_t = LIEF::objc::Method; + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + auto mangled_type() const { + return to_unique_string(get().mangled_type()); + } + uint64_t address() const { + return get().address(); + } + auto is_instance() const { + return get().is_instance(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Property.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Property.hpp new file mode 100644 index 0000000..22efd50 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Property.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Property.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class ObjC_Property : private Mirror { + public: + using lief_t = LIEF::objc::Property; + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + auto attribute() const { + return to_unique_string(get().attribute()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/ObjC/Protocol.hpp b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Protocol.hpp new file mode 100644 index 0000000..9196cec --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/ObjC/Protocol.hpp @@ -0,0 +1,115 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/ObjC/Protocol.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/rust/ObjC/DeclOpt.hpp" +#include "LIEF/rust/ObjC/Method.hpp" +#include "LIEF/rust/ObjC/Property.hpp" + +class ObjC_Protocol : private Mirror { + public: + using lief_t = LIEF::objc::Protocol; + using Mirror::Mirror; + + class it_protocols + : public ForwardIterator { + public: + it_protocols(const ObjC_Protocol::lief_t& src) : + ForwardIterator(src.protocols()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_opt_methods + : public ForwardIterator { + public: + it_opt_methods(const ObjC_Protocol::lief_t& src) : + ForwardIterator(src.optional_methods()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_req_methods + : public ForwardIterator { + public: + it_req_methods(const ObjC_Protocol::lief_t& src) : + ForwardIterator(src.required_methods()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_properties + : public ForwardIterator { + public: + it_properties(const ObjC_Protocol::lief_t& src) : + ForwardIterator(src.properties()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto mangled_name() const { + return to_unique_string(get().mangled_name()); + } + + auto protocols() const { + return std::make_unique(get()); + } + + auto optional_methods() const { + return std::make_unique(get()); + } + + auto required_methods() const { + return std::make_unique(get()); + } + + auto properties() const { + return std::make_unique(get()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const ObjC_DeclOpt& opt) const { + return to_unique_string(get().to_decl(from_rust_declopt(opt))); + } +}; + +using ObjC_Protocol_it_protocols = ObjC_Protocol::it_protocols; +using ObjC_Protocol_it_opt_methods = ObjC_Protocol::it_opt_methods; +using ObjC_Protocol_it_req_methods = ObjC_Protocol::it_req_methods; +using ObjC_Protocol_it_properties = ObjC_Protocol::it_properties; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB.hpp new file mode 100644 index 0000000..85e45cd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB.hpp @@ -0,0 +1,33 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/PDB/BuildMetadata.hpp" +#include "LIEF/rust/PDB/CompilationUnit.hpp" +#include "LIEF/rust/PDB/DebugInfo.hpp" +#include "LIEF/rust/PDB/Function.hpp" +#include "LIEF/rust/PDB/PublicSymbol.hpp" +#include "LIEF/rust/PDB/Type.hpp" +#include "LIEF/rust/PDB/types/Array.hpp" +#include "LIEF/rust/PDB/types/Attribute.hpp" +#include "LIEF/rust/PDB/types/BitField.hpp" +#include "LIEF/rust/PDB/types/ClassLike.hpp" +#include "LIEF/rust/PDB/types/Enum.hpp" +#include "LIEF/rust/PDB/types/Function.hpp" +#include "LIEF/rust/PDB/types/Method.hpp" +#include "LIEF/rust/PDB/types/Modifier.hpp" +#include "LIEF/rust/PDB/types/Pointer.hpp" +#include "LIEF/rust/PDB/types/Simple.hpp" +#include "LIEF/rust/PDB/types/Union.hpp" +#include "LIEF/rust/PDB/utils.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/BuildMetadata.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/BuildMetadata.hpp new file mode 100644 index 0000000..ec5f2a8 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/BuildMetadata.hpp @@ -0,0 +1,77 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PDB/BuildMetadata.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +namespace details { +inline std::vector + to_vector(const LIEF::pdb::BuildMetadata::version_t& v) { + return {v.major, v.minor, v.build, v.qfe}; +} + + +inline std::vector + to_vector(LIEF::pdb::BuildMetadata::build_info_t v) { + return {std::move(v.cwd), std::move(v.build_tool), std::move(v.source_file), + std::move(v.pdb), std::move(v.command_line)}; +} +} + +class PDB_BuildMetadata : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::BuildMetadata; + + auto frontend_version() const { + return make_unique_vector( + details::to_vector(get().frontend_version()) + ); + } + + auto backend_version() const { + return make_unique_vector( + details::to_vector(get().backend_version()) + ); + } + + auto version() const { + return to_unique_string(get().version()); + } + + auto language() const { + return as_u8(get().language()); + } + auto target_cpu() const { + return as_u16(get().target_cpu()); + } + + auto env() const { + return make_unique_vector(get().env()); + } + + auto build_info() const { + if (auto opt = get().build_info()) { + return make_unique_vector(details::to_vector(std::move(*opt))); + } + return make_unique_vector(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/CompilationUnit.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/CompilationUnit.hpp new file mode 100644 index 0000000..c1178f9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/CompilationUnit.hpp @@ -0,0 +1,90 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PDB/CompilationUnit.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PDB/BuildMetadata.hpp" +#include "LIEF/rust/PDB/Function.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_CompilationUnit : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::CompilationUnit; + + class it_sources + : public ForwardIterator::const_iterator> { + public: + it_sources(const PDB_CompilationUnit::lief_t& src) : + ForwardIterator(src.sources()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_functions + : public ForwardIterator { + public: + it_functions(const PDB_CompilationUnit::lief_t& src) : + ForwardIterator(src.functions()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto module_name() const { + return to_unique_string(get().module_name()); + } + auto object_filename() const { + return to_unique_string(get().object_filename()); + } + + auto sources() const { + return std::make_unique(get()); + } + + auto functions() const { + return std::make_unique(get()); + } + + auto build_metadata() const { + return details::try_unique(get().build_metadata()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; + +using PDB_CompilationUnit_it_sources = PDB_CompilationUnit::it_sources; +using PDB_CompilationUnit_it_functions = PDB_CompilationUnit::it_functions; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/DebugInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/DebugInfo.hpp new file mode 100644 index 0000000..a9e2367 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/DebugInfo.hpp @@ -0,0 +1,127 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Abstract/DebugInfo.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PDB/CompilationUnit.hpp" +#include "LIEF/rust/PDB/PublicSymbol.hpp" +#include "LIEF/rust/PDB/Type.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/PDB/CompilationUnit.hpp" +#include "LIEF/PDB/DebugInfo.hpp" + +class PDB_DebugInfo : public AbstracDebugInfo { + public: + using lief_t = LIEF::pdb::DebugInfo; + + class it_compilation_units + : public ForwardIterator { + public: + it_compilation_units(const PDB_DebugInfo::lief_t& src) : + ForwardIterator(src.compilation_units()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_public_symbols + : public ForwardIterator { + public: + it_public_symbols(const PDB_DebugInfo::lief_t& src) : + ForwardIterator(src.public_symbols()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_types : public ForwardIterator { + public: + it_types(const PDB_DebugInfo::lief_t& src) : + ForwardIterator(src.types()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + PDB_DebugInfo(std::unique_ptr bin) : + AbstracDebugInfo(std::move(bin)) {} + + static auto from_file(const std::string& file) { + return details::try_unique( + LIEF::pdb::DebugInfo::from_file(file) + ); + } + + auto age() const { + return impl().age(); + } + auto guid() const { + return to_unique_string(impl().guid()); + } + + auto compilation_units() const { + return std::make_unique(impl()); + } + + auto public_symbols() const { + return std::make_unique(impl()); + } + + auto types() const { + return std::make_unique(impl()); + } + + auto public_symbol_by_name(const std::string& name) const { + return details::try_unique(impl().find_public_symbol(name)); + } + + auto find_type(const std::string& name) const { + return details::try_unique(impl().find_type(name)); + } + + auto find_type_by_index(uint32_t index) const { + return details::try_unique(impl().find_type(index)); + } + + auto to_string() const { + return to_unique_string(impl().to_string()); + } + + static auto classof(const AbstracDebugInfo& reloc) { + return lief_t::classof( + static_cast(&reloc.get()) + ); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PDB_DebugInfo_it_compilation_units = PDB_DebugInfo::it_compilation_units; +using PDB_DebugInfo_it_public_symbols = PDB_DebugInfo::it_public_symbols; +using PDB_DebugInfo_it_types = PDB_DebugInfo::it_types; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/Function.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/Function.hpp new file mode 100644 index 0000000..832db6c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/Function.hpp @@ -0,0 +1,55 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PDB/Function.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/debug_location.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_Function : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::Function; + + auto name() const { + return to_unique_string(get().name()); + } + auto RVA() const { + return get().RVA(); + } + auto code_size() const { + return get().code_size(); + } + auto section_name() const { + return to_unique_string(get().section_name()); + } + auto debug_location() const { + return details::make_location(get().debug_location()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/PublicSymbol.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/PublicSymbol.hpp new file mode 100644 index 0000000..ecf521b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/PublicSymbol.hpp @@ -0,0 +1,42 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PDB/PublicSymbol.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_PublicSymbol : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::PublicSymbol; + + auto name() const { + return to_unique_string(get().name()); + } + auto demangled_name() const { + return to_unique_string(get().demangled_name()); + } + auto section_name() const { + return to_unique_string(get().section_name()); + } + auto RVA() const { + return get().RVA(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/Type.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/Type.hpp new file mode 100644 index 0000000..69d6cad --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/Type.hpp @@ -0,0 +1,46 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/Type.hpp" +#include "LIEF/rust/DebugDeclOpt.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" + +class PDB_Type : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::Type; + + uint32_t kind() const { + return as_u32(get().kind()); + } + + auto name(uint32_t& is_set) const { + return to_unique_string(details::make_optional(get().name(), is_set)); + } + + uint64_t size(uint32_t& is_set) const { + return details::make_optional(get().size(), is_set); + } + + auto to_decl() const { + return to_unique_string(get().to_decl()); + } + + auto to_decl_with_opt(const LIEF_DeclOpt& opt) const { + return to_unique_string(get().to_decl(opt.conf())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Array.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Array.hpp new file mode 100644 index 0000000..c2980b4 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Array.hpp @@ -0,0 +1,43 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Array.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +class PDB_types_Array : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Array; + + uint64_t numberof_elements() const { + return impl().numberof_elements(); + } + + auto element_type() const { + return details::try_unique(impl().element_type()); + } + + auto index_type() const { + return details::try_unique(impl().index_type()); + } + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Attribute.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Attribute.hpp new file mode 100644 index 0000000..15b09da --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Attribute.hpp @@ -0,0 +1,35 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Attribute.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PDB/Type.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_types_Attribute : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::types::Attribute; + + auto name() const { + return to_unique_string(get().name()); + } + auto field_offset() const { + return get().field_offset(); + } + auto get_type() const { + return details::try_unique(get().type()); + } // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/BitField.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/BitField.hpp new file mode 100644 index 0000000..9b02507 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/BitField.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/BitField.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +class PDB_types_BitField : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::BitField; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/ClassLike.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/ClassLike.hpp new file mode 100644 index 0000000..64731ec --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/ClassLike.hpp @@ -0,0 +1,102 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/ClassLike.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PDB/Type.hpp" +#include "LIEF/rust/PDB/types/Attribute.hpp" +#include "LIEF/rust/PDB/types/Method.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_types_ClassLike : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::ClassLike; + + class it_attributes + : public ForwardIterator { + public: + it_attributes(const PDB_types_ClassLike::lief_t& src) : + ForwardIterator(src.attributes()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + class it_methods : public ForwardIterator { + public: + it_methods(const PDB_types_ClassLike::lief_t& src) : + ForwardIterator(src.methods()) {} + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + auto unique_name() const { + return to_unique_string(impl().unique_name()); + } + + auto attributes() const { + return std::make_unique(impl()); + } + + auto methods() const { + return std::make_unique(impl()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PDB_types_ClassLike_it_attributes = PDB_types_ClassLike::it_attributes; +using PDB_types_ClassLike_it_methods = PDB_types_ClassLike::it_methods; + + +class PDB_types_Class : public PDB_types_ClassLike { + public: + using lief_t = LIEF::pdb::types::Class; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } +}; + +class PDB_types_Structure : public PDB_types_ClassLike { + public: + using lief_t = LIEF::pdb::types::Structure; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } +}; + +class PDB_types_Interface : public PDB_types_ClassLike { + public: + using lief_t = LIEF::pdb::types::Interface; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Enum.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Enum.hpp new file mode 100644 index 0000000..d425ed0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Enum.hpp @@ -0,0 +1,87 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Enum.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_types_Enum_Entry : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::types::Enum::Entry; + + auto name() const { + return to_unique_string(get().name()); + } + + int64_t value() const { + return get().value(); + } +}; + +class PDB_types_Enum : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Enum; + + class it_entries + : public ContainerIterator> { + public: + using container_t = std::vector; + it_entries(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto entries() const { + std::vector entries = impl().entries(); + return std::make_unique(std::move(entries)); + } + + auto underlying_type() const { + return details::try_unique( + impl().underlying_type() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + std::unique_ptr find_entry(int64_t value) const { + if (auto entry = impl().find_entry(value)) { + return std::make_unique(*entry); + } + return nullptr; + } + + auto unique_name() const { + return to_unique_string(impl().unique_name()); + } + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PDB_types_Enum_it_entries = PDB_types_Enum::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Function.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Function.hpp new file mode 100644 index 0000000..5723fc0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Function.hpp @@ -0,0 +1,58 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Function.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +#include "LIEF/rust/Iterator.hpp" + +class PDB_types_Function : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Function; + + class it_parameters + : public ContainerIterator>> { + public: + using container_t = std::vector>; + it_parameters(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto return_type() const { + return details::try_unique(impl().return_type()); + } + + auto parameters() const { + return std::make_unique(impl().parameters()); + } + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PDB_types_Function_it_parameters = PDB_types_Function::it_parameters; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Method.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Method.hpp new file mode 100644 index 0000000..aaf63a9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Method.hpp @@ -0,0 +1,36 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Method.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PDB_types_Method : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::pdb::types::Method; + + auto name() const { + return to_unique_string(get().name()); + } + + auto get_type() const { + return as_u32(get().type()); + } + + auto access() const { + return to_int(get().access()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Modifier.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Modifier.hpp new file mode 100644 index 0000000..888fc36 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Modifier.hpp @@ -0,0 +1,35 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Modifier.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +class PDB_types_Modifier : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Modifier; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique(impl().underlying_type()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Pointer.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Pointer.hpp new file mode 100644 index 0000000..62b8196 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Pointer.hpp @@ -0,0 +1,35 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Pointer.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +class PDB_types_Pointer : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Pointer; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + auto underlying_type() const { + return details::try_unique(impl().underlying_type()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Simple.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Simple.hpp new file mode 100644 index 0000000..3640ca2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Simple.hpp @@ -0,0 +1,47 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Simple.hpp" +#include "LIEF/rust/PDB/Type.hpp" + +class PDB_types_Simple : public PDB_Type { + public: + using lief_t = LIEF::pdb::types::Simple; + + auto get_type() const { + return as_u32(impl().type()); + } + + auto modes() const { + return to_int(impl().modes()); + } + + auto is_pointer() const { + return impl().is_pointer(); + } + + auto is_signed() const { + return impl().is_signed(); + } + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Union.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Union.hpp new file mode 100644 index 0000000..ac9bcaf --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/types/Union.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PDB/types/Union.hpp" +#include "LIEF/rust/PDB/types/ClassLike.hpp" + +class PDB_types_Union : public PDB_types_ClassLike { + public: + using lief_t = LIEF::pdb::types::Union; + + static auto classof(const PDB_Type& type) { + return lief_t::classof(&type.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PDB/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/PDB/utils.hpp new file mode 100644 index 0000000..1468c67 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PDB/utils.hpp @@ -0,0 +1,25 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once +#include "LIEF/PDB/utils.hpp" +#include + +class PDB_Utils { + public: + static auto is_pdb(const std::string& file) { + return LIEF::pdb::is_pdb(file); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE.hpp new file mode 100644 index 0000000..48c608c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE.hpp @@ -0,0 +1,89 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/PE/Binary.hpp" +#include "LIEF/rust/PE/CodeIntegrity.hpp" +#include "LIEF/rust/PE/DataDirectories.hpp" +#include "LIEF/rust/PE/DelayImport.hpp" +#include "LIEF/rust/PE/DelayImportEntry.hpp" +#include "LIEF/rust/PE/DosHeader.hpp" +#include "LIEF/rust/PE/Export.hpp" +#include "LIEF/rust/PE/ExportEntry.hpp" +#include "LIEF/rust/PE/Header.hpp" +#include "LIEF/rust/PE/Import.hpp" +#include "LIEF/rust/PE/ImportEntry.hpp" +#include "LIEF/rust/PE/OptionalHeader.hpp" +#include "LIEF/rust/PE/Relocation.hpp" +#include "LIEF/rust/PE/RelocationEntry.hpp" +#include "LIEF/rust/PE/ResourceAccelerator.hpp" +#include "LIEF/rust/PE/ResourceData.hpp" +#include "LIEF/rust/PE/ResourceDirectory.hpp" +#include "LIEF/rust/PE/ResourceIcon.hpp" +#include "LIEF/rust/PE/ResourceNode.hpp" +#include "LIEF/rust/PE/ResourceVersion.hpp" +#include "LIEF/rust/PE/ResourcesManager.hpp" +#include "LIEF/rust/PE/RichEntry.hpp" +#include "LIEF/rust/PE/RichHeader.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include "LIEF/rust/PE/TLS.hpp" +#include "LIEF/rust/PE/utils.hpp" + +#include "LIEF/rust/PE/debug/CodeView.hpp" +#include "LIEF/rust/PE/debug/CodeViewPDB.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/PE/debug/ExDllCharacteristics.hpp" +#include "LIEF/rust/PE/debug/FPO.hpp" +#include "LIEF/rust/PE/debug/PDBChecksum.hpp" +#include "LIEF/rust/PE/debug/Pogo.hpp" +#include "LIEF/rust/PE/debug/PogoEntry.hpp" +#include "LIEF/rust/PE/debug/Repro.hpp" +#include "LIEF/rust/PE/debug/VCFeature.hpp" + +#include "LIEF/rust/PE/ExceptionInfo.hpp" +#include "LIEF/rust/PE/RuntimeFunctionAArch64.hpp" +#include "LIEF/rust/PE/RuntimeFunctionX64.hpp" +#include "LIEF/rust/PE/UnwindCodeX64.hpp" + +#include "LIEF/rust/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/PE/signature/GenericContent.hpp" +#include "LIEF/rust/PE/signature/PKCS9TSTInfo.hpp" +#include "LIEF/rust/PE/signature/RsaInfo.hpp" +#include "LIEF/rust/PE/signature/Signature.hpp" +#include "LIEF/rust/PE/signature/SignerInfo.hpp" +#include "LIEF/rust/PE/signature/SpcIndirectData.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/PE/signature/attributes/ContentType.hpp" +#include "LIEF/rust/PE/signature/attributes/GenericType.hpp" +#include "LIEF/rust/PE/signature/attributes/MsCounterSign.hpp" +#include "LIEF/rust/PE/signature/attributes/MsManifestBinaryID.hpp" +#include "LIEF/rust/PE/signature/attributes/MsSpcNestedSignature.hpp" +#include "LIEF/rust/PE/signature/attributes/MsSpcStatementType.hpp" +#include "LIEF/rust/PE/signature/attributes/PKCS9AtSequenceNumber.hpp" +#include "LIEF/rust/PE/signature/attributes/PKCS9CounterSignature.hpp" +#include "LIEF/rust/PE/signature/attributes/PKCS9MessageDigest.hpp" +#include "LIEF/rust/PE/signature/attributes/PKCS9SigningTime.hpp" +#include "LIEF/rust/PE/signature/attributes/SigningCertificateV2.hpp" +#include "LIEF/rust/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp" +#include "LIEF/rust/PE/signature/attributes/SpcSpOpusInfo.hpp" +#include "LIEF/rust/PE/signature/x509.hpp" + +#include "LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp" +#include "LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp" +#include "LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp" +#include "LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp" +#include "LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp" +#include "LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp" + +#include "LIEF/rust/PE/Factory.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Binary.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Binary.hpp new file mode 100644 index 0000000..e4ae5e6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Binary.hpp @@ -0,0 +1,717 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/Abstract/Binary.hpp" +#include "LIEF/rust/PE/DataDirectories.hpp" +#include "LIEF/rust/PE/DelayImport.hpp" +#include "LIEF/rust/PE/DosHeader.hpp" +#include "LIEF/rust/PE/ExceptionInfo.hpp" +#include "LIEF/rust/PE/Export.hpp" +#include "LIEF/rust/PE/Header.hpp" +#include "LIEF/rust/PE/Import.hpp" +#include "LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp" +#include "LIEF/rust/PE/OptionalHeader.hpp" +#include "LIEF/rust/PE/Relocation.hpp" +#include "LIEF/rust/PE/ResourceNode.hpp" +#include "LIEF/rust/PE/ResourcesManager.hpp" +#include "LIEF/rust/PE/RichHeader.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include "LIEF/rust/PE/TLS.hpp" +#include "LIEF/rust/PE/debug/CodeViewPDB.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/PE/signature/Signature.hpp" +#include "LIEF/rust/helpers.hpp" +#include +#include +#include +#include + +#include "LIEF/rust/COFF/Symbol.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_Binary_write_config_t { + public: + static auto create() { + return std::make_unique(); + } + auto set_import(bool value) { + config_.imports = value; + } + + auto set_exports(bool value) { + config_.exports = value; + } + + auto set_resources(bool value) { + config_.resources = value; + } + + auto set_relocations(bool value) { + config_.relocations = value; + } + + auto set_load_config(bool value) { + config_.load_configuration = value; + } + + auto set_tls(bool value) { + config_.tls = value; + } + + auto set_overlay(bool value) { + config_.overlay = value; + } + + auto set_debug(bool value) { + config_.debug = value; + } + + auto set_dos_stub(bool value) { + config_.dos_stub = value; + } + + auto set_rsrc_section(const std::string& sec) { + config_.rsrc_section = sec; + } + + auto set_idata_section(const std::string& sec) { + config_.idata_section = sec; + } + + auto set_tls_section(const std::string& sec) { + config_.tls_section = sec; + } + + auto set_reloc_section(const std::string& sec) { + config_.reloc_section = sec; + } + + auto set_export_section(const std::string& sec) { + config_.export_section = sec; + } + + auto set_debug_section(const std::string& sec) { + config_.debug_section = sec; + } + + const LIEF::PE::Builder::config_t& conf() const { + return config_; + } + + private: + LIEF::PE::Builder::config_t config_; +}; + +class PE_ParserConfig { + public: + static auto create() { + return std::make_unique(); + } + + const LIEF::PE::ParserConfig& conf() const { + return config_; + } + + auto set_parse_signature(bool value) { + config_.parse_signature = value; + } + + auto set_parse_exports(bool value) { + config_.parse_exports = value; + } + + auto set_parse_imports(bool value) { + config_.parse_imports = value; + } + + auto set_parse_rsrc(bool value) { + config_.parse_rsrc = value; + } + + auto set_parse_reloc(bool value) { + config_.parse_reloc = value; + } + + auto set_parse_exceptions(bool value) { + config_.parse_exceptions = value; + } + + auto set_parse_arm64x_binary(bool value) { + config_.parse_arm64x_binary = value; + } + + void set_rebase(uint64_t value) { + config_.rebase = value; + } + + void clear_rebase() { + config_.rebase.reset(); + } + + private: + LIEF::PE::ParserConfig config_; +}; + +class PE_Binary : public AbstractBinary { + public: + using lief_t = LIEF::PE::Binary; + + class it_debug + : public Iterator { + public: + it_debug(const PE_Binary::lief_t& src) : + Iterator(src.debug()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_signatures + : public Iterator { + public: + it_signatures(const PE_Binary::lief_t& src) : + Iterator(src.signatures()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_sections + : public Iterator { + public: + it_sections(const PE_Binary::lief_t& src) : + Iterator(src.sections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_relocations + : public Iterator { + public: + it_relocations(const PE_Binary::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_imports + : public Iterator { + public: + it_imports(const PE_Binary::lief_t& src) : + Iterator(src.imports()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_delay_imports + : public Iterator { + public: + it_delay_imports(const PE_Binary::lief_t& src) : + Iterator(src.delay_imports()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_data_directories + : public Iterator { + public: + it_data_directories(const PE_Binary::lief_t& src) : + Iterator(src.data_directories()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_strings_table + : public Iterator { + public: + it_strings_table(const PE_Binary::lief_t& src) : + Iterator(src.coff_string_table()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_symbols + : public Iterator { + public: + it_symbols(const PE_Binary::lief_t& src) : + Iterator(src.symbols()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_exceptions + : public Iterator { + public: + it_exceptions(const PE_Binary::lief_t& src) : + Iterator(src.exceptions()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + PE_Binary(std::unique_ptr bin) : + AbstractBinary(std::move(bin)) {} + + PE_Binary(std::unique_ptr bin) : + AbstractBinary(std::move(bin)) {} + + static auto parse_from_memory(uint64_t addr) { + return details::try_unique( + LIEF::PE::Parser::parse_from_memory(addr) + ); + } + + static auto parse_from_memory_with_config(uint64_t addr, + const PE_ParserConfig& config) { + return details::try_unique( + LIEF::PE::Parser::parse_from_memory(addr, config.conf()) + ); + } + + static auto parse_from_dump(const std::string& path, uint64_t addr) { + return details::try_unique(LIEF::PE::Parser::parse_from_dump(path, + addr)); + } + + static auto parse_from_dump_with_config(const std::string& path, uint64_t addr, + const PE_ParserConfig& config) { + return details::try_unique( + LIEF::PE::Parser::parse_from_dump(path, addr, config.conf()) + ); + } + + static auto parse(const std::string& path) { + return details::try_unique(LIEF::PE::Parser::parse(path)); + } + + static auto parse_with_config(const std::string& path, + const PE_ParserConfig& config) { + return details::try_unique(LIEF::PE::Parser::parse(path, + config.conf())); + } + + auto debug() const { + return std::make_unique(impl()); + } + + auto signatures() const { + return std::make_unique(impl()); + } + + auto sections() const { + return std::make_unique(impl()); + } + + auto relocations() const { + return std::make_unique(impl()); + } + + auto imports() const { + return std::make_unique(impl()); + } + + auto delay_imports() const { + return std::make_unique(impl()); + } + + auto data_directories() const { + return std::make_unique(impl()); + } + + auto tls() const { + return details::try_unique( + impl().tls() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto rich_header() const { + return details::try_unique( + impl().rich_header() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto get_export() const { + return details::try_unique( + impl().get_export() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto resources() const { + return details::try_unique( + impl().resources() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto load_configuration() const { + return details::try_unique( + impl().load_configuration() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto dos_header() const { + return std::make_unique(impl().dos_header()); + } + + auto header() const { + return std::make_unique(impl().header()); + } + + auto optional_header() const { + return std::make_unique(impl().optional_header()); + } + + uint32_t compute_checksum() const { + return impl().compute_checksum(); + } + + auto resources_manager() const { + return details::from_result( + impl().resources_manager() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto verify_signature(uint32_t flags) const { + using check_t = LIEF::PE::Signature::VERIFICATION_CHECKS; + return as_u32(impl().verify_signature(check_t(flags))); + } + + auto verify_with_signature(const PE_Signature& sig, uint32_t flags) const { + using check_t = LIEF::PE::Signature::VERIFICATION_CHECKS; + return as_u32(impl().verify_signature(sig.get(), check_t(flags))); + } + + auto authentihash(uint32_t algo) const { + return make_unique_vector( + impl().authentihash(LIEF::PE::ALGORITHMS(algo)) + ); + } + + auto overlay() const { + return make_span(impl().overlay()); + } + + auto overlay_offset() const { + return impl().overlay_offset(); + } + + auto dos_stub() const { + return make_span(impl().dos_stub()); + } + + auto rva_to_offset(uint64_t rva) const { + return impl().rva_to_offset(rva); + } + + auto va_to_offset(uint64_t rva) const { + return impl().va_to_offset(rva); + } + + uint64_t offset_to_rva(uint64_t offset) const { + return impl().offset_to_rva(offset); + } + + uint64_t virtual_size() const { + return impl().virtual_size(); + } + + uint64_t sizeof_headers() const { + return impl().sizeof_headers(); + } + + auto section_from_offset(uint64_t offset) const { + return details::try_unique( + impl().section_from_offset(offset) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto section_from_rva(uint64_t address) const { + return details::try_unique( + impl().section_from_offset(address) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto section_by_name(const std::string& name) const { + return details::try_unique( + impl().get_section(name) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto add_section(const PE_Section& section) { + return details::try_unique(impl().add_section(section.impl())); + } + + auto data_directory_by_type(uint32_t type) const { + return details::try_unique( + impl().data_directory(LIEF::PE::DataDirectory::TYPES(type)) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto import_by_name(const std::string& name) const { + return details::try_unique( + impl().get_import(name) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto delay_import_by_name(const std::string& name) const { + return details::try_unique( + impl().get_delay_import(name) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto export_dir() const { + return details::try_unique(impl().export_dir()); + } + + auto import_dir() const { + return details::try_unique(impl().import_dir()); + } + + auto rsrc_dir() const { + return details::try_unique(impl().rsrc_dir()); + } + + auto exceptions_dir() const { + return details::try_unique(impl().exceptions_dir()); + } + + auto cert_dir() const { + return details::try_unique(impl().cert_dir()); + } + + auto relocation_dir() const { + return details::try_unique(impl().relocation_dir()); + } + + auto debug_dir() const { + return details::try_unique(impl().debug_dir()); + } + + auto tls_dir() const { + return details::try_unique(impl().tls_dir()); + } + + auto load_config_dir() const { + return details::try_unique(impl().load_config_dir()); + } + + auto iat_dir() const { + return details::try_unique(impl().iat_dir()); + } + + auto delay_dir() const { + return details::try_unique(impl().delay_dir()); + } + + Span get_content_from_virtual_address(uint64_t virtual_address, + uint64_t size) const { + return make_span(impl().get_content_from_virtual_address(virtual_address, + size)); + } + + auto functions() const { + return std::make_unique(impl().functions()); + } + + auto add_import(const std::string& name) { + return std::make_unique(impl().add_import(name)); + } + + auto add_import_pos(const std::string& name, uint32_t pos) { + return std::make_unique(impl().add_import(name, pos)); + } + + auto remove_import(const std::string& name) { + impl().remove_import(name); + } + + auto remove_all_imports() { + impl().remove_all_imports(); + } + + auto remove_tls() { + impl().remove_tls(); + } + + auto set_tls(const PE_TLS& tls) { + impl().tls(tls.get()); + } + + auto set_resources(const PE_ResourceNode& node) { + impl().set_resources(node.get()); + } + + auto add_debug_info(const PE_Debug& entry) { + return details::try_unique(impl().add_debug_info(entry.get())); + } + + auto remove_debug(const PE_Debug& entry) { + return impl().remove_debug(entry.get()); + } + + auto clear_debug() { + return impl().clear_debug(); + } + + auto codeview_pdb() const { + return details::try_unique(impl().codeview_pdb()); + } + + auto coff_string_table() const { + return std::make_unique(impl()); + } + + auto find_coff_string_at(uint32_t offset) const { + return details::try_unique(impl().find_coff_string(offset)); + } + + auto symbols() const { + return std::make_unique(impl()); + } + + auto exceptions() const { + return std::make_unique(impl()); + } + + auto find_exception_at(uint32_t rva) const { + return details::try_unique(impl().find_exception_at(rva)); + } + + auto is_arm64x() const { + return impl().is_arm64x(); + } + + auto is_arm64ec() const { + return impl().is_arm64ec(); + } + + auto nested_pe_binary() const { + return details::try_unique( + const_cast(impl()).move_nested_pe_binary() + ); + } + + auto write(const std::string& output) { + impl().write(output); + } + + void write_with_config(const std::string& output, + const PE_Binary_write_config_t& config) { + impl().write(output, config.conf()); + } + + auto write_to_bytes() { + std::ostringstream os; + impl().write(os); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + auto write_to_bytes_with_config(const PE_Binary_write_config_t& config) { + std::ostringstream os; + impl().write(os, config.conf()); + std::string bytes = os.str(); + return make_unique_vector(bytes.begin(), bytes.end()); + } + + auto set_export(const PE_Export& exp) { + impl().set_export(exp.get()); + } + + auto is_reproducible_build() const { + return impl().is_reproducible_build(); + } + + auto has_import(const std::string& name) const { + return impl().has_import(name); + } + auto has_delay_import(const std::string& name) const { + return impl().has_delay_import(name); + } + + auto exception_functions() const { + return std::make_unique( + impl().exception_functions() + ); + } + + auto remove_section(const std::string& name, bool clear) { + impl().remove_section(name, clear); + } + + auto fill_address(uint64_t address, uint64_t size, uint8_t value) { + impl().fill_address(address, size, value); + } + + auto remove_all_relocations() { + impl().remove_all_relocations(); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; + +using PE_Binary_it_debug = PE_Binary::it_debug; +using PE_Binary_it_signatures = PE_Binary::it_signatures; +using PE_Binary_it_sections = PE_Binary::it_sections; +using PE_Binary_it_relocations = PE_Binary::it_relocations; +using PE_Binary_it_imports = PE_Binary::it_imports; +using PE_Binary_it_delay_imports = PE_Binary::it_delay_imports; +using PE_Binary_it_data_directories = PE_Binary::it_data_directories; +using PE_Binary_it_strings_table = PE_Binary::it_strings_table; +using PE_Binary_it_symbols = PE_Binary::it_symbols; +using PE_Binary_it_exceptions = PE_Binary::it_exceptions; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/CodeIntegrity.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/CodeIntegrity.hpp new file mode 100644 index 0000000..b9f3982 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/CodeIntegrity.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/CodeIntegrity.hpp" +#include "LIEF/rust/Mirror.hpp" + +class PE_CodeIntegrity : private Mirror { + public: + using lief_t = LIEF::PE::CodeIntegrity; + using Mirror::Mirror; + + auto flags() const { + return get().flags(); + } + auto catalog() const { + return get().catalog(); + } + auto catalog_offset() const { + return get().catalog_offset(); + } + auto reserved() const { + return get().reserved(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/DataDirectories.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/DataDirectories.hpp new file mode 100644 index 0000000..0bea8e3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/DataDirectories.hpp @@ -0,0 +1,43 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/DataDirectory.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_DataDirectory : private Mirror { + public: + using lief_t = LIEF::PE::DataDirectory; + using Mirror::Mirror; + + uint32_t RVA() const { + return get().RVA(); + } + uint32_t size() const { + return get().size(); + } + uint32_t get_type() const { + return to_int(get().type()); + } + + Span content() const { + return make_span(get().content()); + } + + auto section() const { + return details::try_unique(get().section()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImport.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImport.hpp new file mode 100644 index 0000000..bff4e2e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImport.hpp @@ -0,0 +1,73 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/DelayImport.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/DelayImportEntry.hpp" +#include "LIEF/rust/helpers.hpp" + +#include + +class PE_DelayImport : private Mirror { + public: + using lief_t = LIEF::PE::DelayImport; + using Mirror::Mirror; + + class it_entries : public Iterator { + public: + it_entries(const PE_DelayImport::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t attribute() const { + return get().attribute(); + } + auto name() const { + return to_unique_string(get().name()); + } + uint32_t handle() const { + return get().handle(); + } + uint32_t iat() const { + return get().iat(); + } + uint32_t names_table() const { + return get().names_table(); + } + uint32_t biat() const { + return get().biat(); + } + uint32_t uiat() const { + return get().uiat(); + } + uint32_t timestamp() const { + return get().timestamp(); + } + + auto entries() const { + return std::make_unique(get()); + } +}; + +using PE_DelayImport_it_entries = PE_DelayImport::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImportEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImportEntry.hpp new file mode 100644 index 0000000..897bdc0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/DelayImportEntry.hpp @@ -0,0 +1,54 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/DelayImportEntry.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_DelayImportEntry : public AbstractSymbol { + using lief_t = LIEF::PE::DelayImportEntry; + + public: + PE_DelayImportEntry(const lief_t& info) : + AbstractSymbol(const_cast(info)) {} + + auto is_ordinal() const { + return impl().is_ordinal(); + } + uint16_t ordinal() const { + return impl().ordinal(); + } + uint64_t hint_name_rva() const { + return impl().hint_name_rva(); + } + uint16_t hint() const { + return impl().hint(); + } + uint64_t iat_value() const { + return impl().iat_value(); + } + uint64_t data() const { + return impl().data(); + } + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/DosHeader.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/DosHeader.hpp new file mode 100644 index 0000000..f2af3d5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/DosHeader.hpp @@ -0,0 +1,86 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/DosHeader.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_DosHeader : private Mirror { + public: + using lief_t = LIEF::PE::DosHeader; + using Mirror::Mirror; + + uint16_t magic() const { + return get().magic(); + } + uint16_t used_bytes_in_last_page() const { + return get().used_bytes_in_last_page(); + } + uint16_t file_size_in_pages() const { + return get().file_size_in_pages(); + } + uint16_t numberof_relocation() const { + return get().numberof_relocation(); + } + uint16_t header_size_in_paragraphs() const { + return get().header_size_in_paragraphs(); + } + uint16_t minimum_extra_paragraphs() const { + return get().minimum_extra_paragraphs(); + } + uint16_t maximum_extra_paragraphs() const { + return get().maximum_extra_paragraphs(); + } + uint16_t initial_relative_ss() const { + return get().initial_relative_ss(); + } + uint16_t initial_sp() const { + return get().initial_sp(); + } + uint16_t checksum() const { + return get().checksum(); + } + uint16_t initial_ip() const { + return get().initial_ip(); + } + uint16_t initial_relative_cs() const { + return get().initial_relative_cs(); + } + uint16_t addressof_relocation_table() const { + return get().addressof_relocation_table(); + } + uint16_t overlay_number() const { + return get().overlay_number(); + } + auto reserved() const { + return make_unique_vector(details::make_vector(get().reserved())); + } + + uint16_t oem_id() const { + return get().oem_id(); + } + uint16_t oem_info() const { + return get().oem_info(); + } + + auto reserved2() const { + return make_unique_vector(details::make_vector(get().reserved2())); + } + uint32_t addressof_new_exeheader() const { + return get().addressof_new_exeheader(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ExceptionInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ExceptionInfo.hpp new file mode 100644 index 0000000..e402f87 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ExceptionInfo.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/ExceptionInfo.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ExceptionInfo : public Mirror { + public: + using lief_t = LIEF::PE::ExceptionInfo; + using Mirror::Mirror; + + auto rva_start() const { + return get().rva_start(); + } + + auto offset() const { + return get().offset(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Export.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Export.hpp new file mode 100644 index 0000000..5da67c2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Export.hpp @@ -0,0 +1,141 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/Export.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/ExportEntry.hpp" +#include "LIEF/rust/helpers.hpp" + +#include + +class PE_Export : public Mirror { + public: + using lief_t = LIEF::PE::Export; + using Mirror::Mirror; + + class it_entries + : public Iterator { + public: + it_entries(const PE_Export::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + static auto create() { + return std::make_unique(std::make_unique()); + } + + auto export_flags() const { + return get().export_flags(); + } + auto timestamp() const { + return get().timestamp(); + } + auto major_version() const { + return get().major_version(); + } + auto minor_version() const { + return get().minor_version(); + } + auto ordinal_base() const { + return get().ordinal_base(); + } + + auto name_rva() const { + return get().name_rva(); + } + auto export_addr_table_rva() const { + return get().export_addr_table_rva(); + } + auto export_addr_table_cnt() const { + return get().export_addr_table_cnt(); + } + auto names_addr_table_rva() const { + return get().names_addr_table_rva(); + } + auto names_addr_table_cnt() const { + return get().names_addr_table_cnt(); + } + auto ord_addr_table_rva() const { + return get().ord_addr_table_rva(); + } + + auto name() const { + return to_unique_string(get().name()); + } + + auto entries() const { + return std::make_unique(get()); + } + + auto set_export_flags(uint32_t flags) { + get().export_flags(flags); + } + auto set_timestamp(uint32_t ts) { + get().timestamp(ts); + } + auto set_major_version(uint32_t version) { + get().major_version(version); + } + auto set_minor_version(uint32_t version) { + get().minor_version(version); + } + auto set_name(const std::string& name) { + get().name(name); + } + + auto entry_by_name(const std::string& name) const { + return details::try_unique(get().find_entry(name)); + } + + auto entry_by_ordinal(uint32_t ord) const { + return details::try_unique(get().find_entry(ord)); + } + + auto entry_at_rva(uint32_t rva) const { + return details::try_unique(get().find_entry_at(rva)); + } + + auto add_entry(const PE_ExportEntry& entry) { + return std::make_unique( + get().add_entry(as(&entry)) + ); + } + + auto add_entry_by_name(const std::string& name, uint32_t rva) { + return std::make_unique(get().add_entry(name, rva)); + } + + auto remove_entry(std::unique_ptr entry) { + return get().remove_entry(static_cast((*entry).get())); + } + + auto remove_entry_at(uint32_t rva) { + return get().remove_entry(rva); + } + + auto remove_entry_by_name(const std::string& name) { + return get().remove_entry(name); + } +}; + +using PE_Export_it_entries = PE_Export::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ExportEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ExportEntry.hpp new file mode 100644 index 0000000..93bc0fd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ExportEntry.hpp @@ -0,0 +1,79 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/ExportEntry.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ExportEntry : public AbstractSymbol { + public: + using lief_t = LIEF::PE::ExportEntry; + PE_ExportEntry(const lief_t& info) : + AbstractSymbol(info) {} + PE_ExportEntry(std::unique_ptr impl) : + AbstractSymbol(std::move(impl)) {} + + static auto create() { + return std::make_unique(std::make_unique()); + } + + static auto create_with_name(const std::string& name, uint32_t addr) { + return std::make_unique(std::make_unique(name, addr)); + } + + auto ordinal() const { + return impl().ordinal(); + } + auto address() const { + return impl().address(); + } + auto is_extern() const { + return impl().is_extern(); + } + auto is_forwarded() const { + return impl().is_forwarded(); + } + auto function_rva() const { + return impl().function_rva(); + } + + auto fwd_library() const { + return to_unique_string(impl().forward_information().library); + } + auto fwd_function() const { + return to_unique_string(impl().forward_information().function); + } + + auto set_ordinal(uint16_t ordinal) { + impl().ordinal(ordinal); + } + auto set_address(uint32_t addr) { + impl().address(addr); + } + + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Factory.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Factory.hpp new file mode 100644 index 0000000..5273911 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Factory.hpp @@ -0,0 +1,65 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/Factory.hpp" +#include "LIEF/rust/PE/Binary.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include +#include + +class PE_Factory { + public: + static std::unique_ptr create(uint32_t pe_type) { + if (auto factory = LIEF::PE::Factory::create(LIEF::PE::PE_TYPE(pe_type))) { + return std::make_unique(std::move(factory)); + } + return nullptr; + } + + auto add_section(const PE_Section& section) { + factory_->add_section(section.impl()); + } + + auto set_arch(uint32_t arch) { + factory_->set_arch(LIEF::PE::Header::MACHINE_TYPES(arch)); + } + + auto set_entrypoint(uint64_t ep) { + factory_->set_entrypoint(ep); + } + + auto get() { + return details::try_unique(factory_->get()); + } + + auto is_32bit() const { + return factory_->is_32bit(); + } + auto is_64bit() const { + return factory_->is_64bit(); + } + auto section_align() const { + return factory_->section_align(); + } + auto file_align() const { + return factory_->file_align(); + } + + PE_Factory(std::unique_ptr f) : + factory_(std::move(f)) {} + + private: + std::unique_ptr factory_; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Header.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Header.hpp new file mode 100644 index 0000000..9c96582 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Header.hpp @@ -0,0 +1,88 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/Header.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_Header : private Mirror { + public: + using lief_t = LIEF::PE::Header; + using Mirror::Mirror; + + auto signature() const { + return make_unique_vector(details::make_vector(get().signature())); + } + + auto machine() const { + return as_u32(get().machine()); + } + auto numberof_sections() const { + return get().numberof_sections(); + } + auto time_date_stamp() const { + return get().time_date_stamp(); + } + auto pointerto_symbol_table() const { + return get().pointerto_symbol_table(); + } + auto numberof_symbols() const { + return get().numberof_symbols(); + } + auto sizeof_optional_header() const { + return get().sizeof_optional_header(); + } + auto characteristics() const { + return get().characteristics(); + } + + auto set_machine(uint32_t value) { + get().machine((lief_t::MACHINE_TYPES)value); + } + + auto set_numberof_sections(uint16_t value) { + get().numberof_sections(value); + } + + auto set_time_date_stamp(uint32_t value) { + get().time_date_stamp(value); + } + + auto set_pointerto_symbol_table(uint32_t value) { + get().pointerto_symbol_table(value); + } + + auto set_numberof_symbols(uint32_t value) { + get().numberof_symbols(value); + } + + auto set_sizeof_optional_header(uint16_t value) { + get().sizeof_optional_header(value); + } + + auto set_characteristics(uint32_t value) { + get().characteristics(value); + } + + auto add_characteristic(uint32_t value) { + get().add_characteristic((lief_t::CHARACTERISTICS)value); + } + + auto remove_characteristic(uint32_t value) { + get().remove_characteristic((lief_t::CHARACTERISTICS)value); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Import.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Import.hpp new file mode 100644 index 0000000..6649bf0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Import.hpp @@ -0,0 +1,108 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/Import.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/DataDirectories.hpp" +#include "LIEF/rust/PE/ImportEntry.hpp" +#include "LIEF/rust/helpers.hpp" + +#include + +class PE_Utils; + +class PE_Import : private Mirror { + friend class PE_Utils; + + public: + using lief_t = LIEF::PE::Import; + using Mirror::Mirror; + + class it_entries + : public Iterator { + public: + it_entries(const PE_Import::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t forwarder_chain() const { + return get().forwarder_chain(); + } + uint32_t timedatestamp() const { + return get().timedatestamp(); + } + uint32_t import_address_table_rva() const { + return get().import_address_table_rva(); + } + uint32_t import_lookup_table_rva() const { + return get().import_lookup_table_rva(); + } + auto name() const { + return to_unique_string(get().name()); + } + + auto name_rva() const { + return get().name_rva(); + } + + auto directory() const { + return details::try_unique( + get().directory() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto iat_directory() const { + return details::try_unique( + get().iat_directory() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto entries() const { + return std::make_unique(get()); + } + + auto entry_by_name(const std::string& name) const { + return details::try_unique( + get().get_entry(name) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto remove_entry_by_name(const std::string& name) { + return get().remove_entry(name); + } + + auto remove_entry_by_ordinal(uint32_t ord) { + return get().remove_entry(ord); + } + + /// Add a new import entry with the given name (i.e. an imported function) + auto add_entry_by_name(const std::string& name) { + return std::make_unique(get().add_entry(name)); + } + + auto set_name(const std::string& name) { + get().name(name); + } +}; + +using PE_Import_it_entries = PE_Import::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ImportEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ImportEntry.hpp new file mode 100644 index 0000000..ac36d43 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ImportEntry.hpp @@ -0,0 +1,70 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/ImportEntry.hpp" +#include "LIEF/rust/Abstract/Symbol.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ImportEntry : public AbstractSymbol { + public: + using lief_t = LIEF::PE::ImportEntry; + PE_ImportEntry(const lief_t& info) : + AbstractSymbol(info) {} + + auto is_ordinal() const { + return impl().is_ordinal(); + } + uint16_t ordinal() const { + return impl().ordinal(); + } + uint64_t hint_name_rva() const { + return impl().hint_name_rva(); + } + uint16_t hint() const { + return impl().hint(); + } + uint64_t iat_value() const { + return impl().iat_value(); + } + auto ilt_value() const { + return impl().ilt_value(); + } + uint64_t data() const { + return impl().data(); + } + uint64_t iat_address() const { + return impl().iat_address(); + } + + auto demangled_name() const { + return to_unique_string(impl().demangled_name()); + } + + auto set_iat_value(uint64_t value) { + impl().iat_value(value); + } + auto set_ilt_value(uint64_t value) { + impl().ilt_value(value); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp new file mode 100644 index 0000000..697fc62 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp @@ -0,0 +1,290 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/Metadata.hpp" +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/MetadataARM64.hpp" +#include "LIEF/PE/LoadConfigurations/CHPEMetadata/MetadataX86.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" + +class PE_CHPEMetadata : public Mirror { + public: + using lief_t = LIEF::PE::CHPEMetadata; + using Mirror::Mirror; + + auto version() const { + return get().version(); + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_CHPEMetadataARM64_range_entry_t + : public Mirror { + public: + using lief_t = LIEF::PE::CHPEMetadataARM64::range_entry_t; + using Mirror::Mirror; + + auto start_offset() const { + return get().start_offset; + } + auto length() const { + return get().length; + } + auto start() const { + return get().start(); + } + auto get_type() const { + return (uint32_t)to_int(get().type()); + } + auto end() const { + return get().end(); + } +}; + + +class PE_CHPEMetadataARM64_redirection_entry_t + : public Mirror { + public: + using lief_t = LIEF::PE::CHPEMetadataARM64::redirection_entry_t; + using Mirror::Mirror; + auto src() const { + return get().src; + } + auto dst() const { + return get().dst; + } +}; + +class PE_CHPEMetadataARM64_code_range_entry_point_t + : public Mirror { + public: + using lief_t = LIEF::PE::CHPEMetadataARM64::code_range_entry_point_t; + using Mirror::Mirror; + auto start_rva() const { + return get().start_rva; + } + auto end_rva() const { + return get().end_rva; + } + auto entrypoint() const { + return get().entrypoint; + } +}; + +class PE_CHPEMetadataARM64 : public PE_CHPEMetadata { + public: + using lief_t = LIEF::PE::CHPEMetadataARM64; + + class it_const_range_entries + : public Iterator { + public: + it_const_range_entries(const PE_CHPEMetadataARM64::lief_t& src) : + Iterator(src.code_ranges()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_const_redirection_entries + : public Iterator { + public: + it_const_redirection_entries(const PE_CHPEMetadataARM64::lief_t& src) : + Iterator(src.redirections()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_const_code_range_entry_point + : public Iterator< + PE_CHPEMetadataARM64_code_range_entry_point_t, + LIEF::PE::CHPEMetadataARM64::it_const_code_range_entry_point + > { + public: + it_const_code_range_entry_point(const PE_CHPEMetadataARM64::lief_t& src) : + Iterator(src.code_range_entry_point()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto code_map() const { + return impl().code_map(); + } + auto code_map_count() const { + return impl().code_map_count(); + } + auto code_ranges_to_entrypoints() const { + return impl().code_ranges_to_entrypoints(); + } + auto redirection_metadata() const { + return impl().redirection_metadata(); + } + auto os_arm64x_dispatch_call_no_redirect() const { + return impl().os_arm64x_dispatch_call_no_redirect(); + } + auto os_arm64x_dispatch_ret() const { + return impl().os_arm64x_dispatch_ret(); + } + auto os_arm64x_dispatch_call() const { + return impl().os_arm64x_dispatch_call(); + } + auto os_arm64x_dispatch_icall() const { + return impl().os_arm64x_dispatch_icall(); + } + auto os_arm64x_dispatch_icall_cfg() const { + return impl().os_arm64x_dispatch_icall_cfg(); + } + auto alternate_entry_point() const { + return impl().alternate_entry_point(); + } + auto auxiliary_iat() const { + return impl().auxiliary_iat(); + } + auto code_ranges_to_entry_points_count() const { + return impl().code_ranges_to_entry_points_count(); + } + auto redirection_metadata_count() const { + return impl().redirection_metadata_count(); + } + auto get_x64_information_function_pointer() const { + return impl().get_x64_information_function_pointer(); + } + auto set_x64_information_function_pointer() const { + return impl().set_x64_information_function_pointer(); + } + auto extra_rfe_table() const { + return impl().extra_rfe_table(); + } + auto extra_rfe_table_size() const { + return impl().extra_rfe_table_size(); + } + auto os_arm64x_dispatch_fptr() const { + return impl().os_arm64x_dispatch_fptr(); + } + auto auxiliary_iat_copy() const { + return impl().auxiliary_iat_copy(); + } + auto auxiliary_delay_import() const { + return impl().auxiliary_delay_import(); + } + auto auxiliary_delay_import_copy() const { + return impl().auxiliary_delay_import_copy(); + } + auto bitfield_info() const { + return impl().bitfield_info(); + } + + auto code_ranges() const { + return std::make_unique(impl()); + } + + auto redirections() const { + return std::make_unique(impl()); + } + + auto code_range_entry_point() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_CHPEMetadata& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_CHPEMetadataX86 : public PE_CHPEMetadata { + public: + using lief_t = LIEF::PE::CHPEMetadataX86; + + auto chpe_code_address_range_offset() const { + return impl().chpe_code_address_range_offset(); + } + + auto chpe_code_address_range_count() const { + return impl().chpe_code_address_range_count(); + } + + auto wowa64_exception_handler_function_pointer() const { + return impl().wowa64_exception_handler_function_pointer(); + } + + auto wowa64_dispatch_call_function_pointer() const { + return impl().wowa64_dispatch_call_function_pointer(); + } + + auto wowa64_dispatch_indirect_call_function_pointer() const { + return impl().wowa64_dispatch_indirect_call_function_pointer(); + } + + auto wowa64_dispatch_indirect_call_cfg_function_pointer() const { + return impl().wowa64_dispatch_indirect_call_cfg_function_pointer(); + } + + auto wowa64_dispatch_ret_function_pointer() const { + return impl().wowa64_dispatch_ret_function_pointer(); + } + + auto wowa64_dispatch_ret_leaf_function_pointer() const { + return impl().wowa64_dispatch_ret_leaf_function_pointer(); + } + + auto wowa64_dispatch_jump_function_pointer() const { + return impl().wowa64_dispatch_jump_function_pointer(); + } + + auto compiler_iat_pointer(uint32_t& is_set) const { + return details::make_optional(impl().compiler_iat_pointer(), is_set); + } + + auto wowa64_rdtsc_function_pointer(uint32_t& is_set) const { + return details::make_optional(impl().wowa64_rdtsc_function_pointer(), is_set); + } + + static auto classof(const PE_CHPEMetadata& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_CHPEMetadataARM64_it_const_range_entries = + PE_CHPEMetadataARM64::it_const_range_entries; +using PE_CHPEMetadataARM64_it_const_redirection_entries = + PE_CHPEMetadataARM64::it_const_redirection_entries; +using PE_CHPEMetadataARM64_it_const_code_range_entry_point = + PE_CHPEMetadataARM64::it_const_code_range_entry_point; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp new file mode 100644 index 0000000..02c7f54 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp @@ -0,0 +1,442 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixup.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupARM64Kernel.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupARM64X.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupControlTransfer.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupGeneric.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicFixupUnknown.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/FunctionOverride.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/FunctionOverrideInfo.hpp" + +#include "LIEF/rust/PE/Relocation.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_DynamicFixup : public Mirror { + public: + using lief_t = LIEF::PE::DynamicFixup; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_DynamicFixupARM64Kernel_entry + : private Mirror { + public: + using lief_t = LIEF::PE::DynamicFixupARM64Kernel::reloc_entry_t; + using Mirror::Mirror; + + auto rva() const { + return get().rva; + } + auto indirect_call() const { + return get().indirect_call; + } + auto register_index() const { + return get().register_index; + } + uint8_t import_type() const { + return to_int(get().import_type); + } + auto iat_index() const { + return get().iat_index; + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_DynamicFixupARM64Kernel : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::DynamicFixupARM64Kernel; + + class it_relocations + : public Iterator { + public: + it_relocations(const PE_DynamicFixupARM64Kernel::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto relocations() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_DynamicFixupARM64X_entry + : private Mirror { + public: + using lief_t = LIEF::PE::DynamicFixupARM64X::reloc_entry_t; + using Mirror::Mirror; + + auto rva() const { + return get().rva; + } + auto value() const { + return get().value; + } + uint32_t size() const { + return get().size; + } + auto get_type() const { + return as_u32(get().type); + } + auto get_bytes() const { + return make_span(get().bytes); + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_DynamicFixupARM64X : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::DynamicFixupARM64X; + + class it_relocations + : public Iterator { + public: + it_relocations(const PE_DynamicFixupARM64X::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto relocations() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + + +class PE_DynamicFixupControlTransfer_entry + : private Mirror { + public: + using lief_t = LIEF::PE::DynamicFixupControlTransfer::reloc_entry_t; + using Mirror::Mirror; + + auto rva() const { + return get().rva; + } + auto is_call() const { + return get().is_call; + } + auto iat_index() const { + return get().iat_index; + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_DynamicFixupControlTransfer : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::DynamicFixupControlTransfer; + + class it_relocations + : public Iterator< + PE_DynamicFixupControlTransfer_entry, + LIEF::PE::DynamicFixupControlTransfer::it_const_relocations + > { + public: + it_relocations(const PE_DynamicFixupControlTransfer::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto relocations() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_DynamicFixupGeneric : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::DynamicFixupGeneric; + + class it_relocations + : public Iterator { + public: + it_relocations(const PE_DynamicFixupGeneric::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto relocations() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_DynamicFixupUnknown : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::DynamicFixupUnknown; + + auto payload() const { + return make_span(impl().payload()); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_FunctionOverride_image_bdd_dynamic_relocation_t + : private Mirror { + public: + using lief_t = LIEF::PE::FunctionOverride::image_bdd_dynamic_relocation_t; + using Mirror::Mirror; + + auto left() const { + return get().left; + } + auto right() const { + return get().right; + } + auto value() const { + return get().value; + } +}; + +class PE_FunctionOverride_image_bdd_info_t + : private Mirror { + public: + using lief_t = LIEF::PE::FunctionOverride::image_bdd_info_t; + using Mirror::Mirror; + + class it_relocations + : public ContainerIterator< + PE_FunctionOverride_image_bdd_dynamic_relocation_t, + std::vector + > { + public: + using container_t = + std::vector; + it_relocations(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto version() const { + return get().version; + } + auto original_size() const { + return get().original_size; + } + auto original_offset() const { + return get().original_offset; + } + auto payload() const { + return make_span(get().payload); + } + + auto relocations() const { + return std::make_unique(get().relocations); + } +}; + +class PE_FunctionOverrideInfo : public Mirror { + public: + using lief_t = LIEF::PE::FunctionOverrideInfo; + using Mirror::Mirror; + + class it_relocations + : public Iterator { + public: + it_relocations(const PE_FunctionOverrideInfo::lief_t& src) : + Iterator(src.relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto original_rva() const { + return get().original_rva(); + } + auto bdd_offset() const { + return get().bdd_offset(); + } + auto rva_size() const { + return get().rva_size(); + } + auto base_reloc_size() const { + return get().base_reloc_size(); + } + auto functions_rva() const { + return make_unique_vector(get().functions_rva()); + } + + auto relocations() const { + return std::make_unique(get()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_FunctionOverride : public PE_DynamicFixup { + public: + using lief_t = LIEF::PE::FunctionOverride; + + class it_func_overriding_info + : public Iterator { + public: + it_func_overriding_info(const PE_FunctionOverride::lief_t& src) : + Iterator(src.func_overriding_info()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_bdd_info + : public Iterator { + public: + it_bdd_info(const PE_FunctionOverride::lief_t& src) : + Iterator(src.bdd_info()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto func_overriding_info() const { + return std::make_unique(impl()); + } + + auto bdd_info() const { + return std::make_unique(impl()); + } + + auto bdd_info_at(uint32_t offset) const { + return details::try_unique( + impl().find_bdd_info(offset) + ); + } + + auto bdd_info_for(const PE_FunctionOverrideInfo& info) const { + return details::try_unique( + impl().find_bdd_info(info.get()) + ); + } + + static auto classof(const PE_DynamicFixup& meta) { + return lief_t::classof(&meta.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_DynamicFixupARM64Kernel_it_relocations = + PE_DynamicFixupARM64Kernel::it_relocations; +using PE_DynamicFixupARM64X_it_relocations = PE_DynamicFixupARM64X::it_relocations; +using PE_DynamicFixupControlTransfer_it_relocations = + PE_DynamicFixupControlTransfer::it_relocations; +using PE_DynamicFixupGeneric_it_relocations = + PE_DynamicFixupGeneric::it_relocations; +using PE_FunctionOverrideInfo_it_relocations = + PE_FunctionOverrideInfo::it_relocations; +using PE_FunctionOverride_image_bdd_info_t_it_relocations = + PE_FunctionOverride_image_bdd_info_t::it_relocations; +using PE_FunctionOverride_it_bdd_info = PE_FunctionOverride::it_bdd_info; +using PE_FunctionOverride_it_func_overriding_info = + PE_FunctionOverride::it_func_overriding_info; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp new file mode 100644 index 0000000..525571d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp @@ -0,0 +1,72 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationBase.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationV1.hpp" +#include "LIEF/PE/LoadConfigurations/DynamicRelocation/DynamicRelocationV2.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicFixup.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_DynamicRelocation : public Mirror { + public: + using lief_t = LIEF::PE::DynamicRelocation; + using Mirror::Mirror; + + auto version() const { + return get().version(); + } + auto symbol() const { + return get().symbol(); + } + + auto fixups() const { + return details::try_unique(get().fixups()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_DynamicRelocationV1 : public PE_DynamicRelocation { + public: + using lief_t = LIEF::PE::DynamicRelocationV1; + + static auto classof(const PE_DynamicRelocation& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_DynamicRelocationV2 : public PE_DynamicRelocation { + public: + using lief_t = LIEF::PE::DynamicRelocationV2; + + static auto classof(const PE_DynamicRelocation& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp new file mode 100644 index 0000000..3de786e --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp @@ -0,0 +1,127 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/LoadConfigurations/EnclaveConfiguration.hpp" +#include "LIEF/PE/LoadConfigurations/EnclaveImport.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_EnclaveImport : public Mirror { + public: + using lief_t = LIEF::PE::EnclaveImport; + using Mirror::Mirror; + + auto get_type() const { + return as_u32(get().type()); + } + auto min_security_version() const { + return get().min_security_version(); + } + auto import_name_rva() const { + return get().import_name_rva(); + } + auto import_name() const { + return to_unique_string(get().import_name()); + } + auto reserved() const { + return get().reserved(); + } + auto id() const { + return make_span(get().id()); + } + auto family_id() const { + return make_span(get().family_id()); + } + auto image_id() const { + return make_span(get().image_id()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_EnclaveConfiguration : public Mirror { + public: + using lief_t = LIEF::PE::EnclaveConfiguration; + using Mirror::Mirror; + + class it_imports + : public Iterator { + public: + it_imports(const PE_EnclaveConfiguration::lief_t& src) : + Iterator(src.imports()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto size() const { + return get().size(); + } + auto min_required_config_size() const { + return get().min_required_config_size(); + } + auto policy_flags() const { + return get().policy_flags(); + } + auto is_debuggable() const { + return get().is_debuggable(); + } + auto import_list_rva() const { + return get().import_list_rva(); + } + auto import_entry_size() const { + return get().import_entry_size(); + } + uint32_t nb_imports() const { + return get().nb_imports(); + } + auto imports() const { + return std::make_unique(get()); + } + auto family_id() const { + return make_span(get().family_id()); + } + auto image_id() const { + return make_span(get().image_id()); + } + auto image_version() const { + return get().image_version(); + } + auto security_version() const { + return get().security_version(); + } + auto enclave_size() const { + return get().enclave_size(); + } + auto nb_threads() const { + return get().nb_threads(); + } + auto enclave_flags() const { + return get().enclave_flags(); + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +using PE_EnclaveConfiguration_it_imports = PE_EnclaveConfiguration::it_imports; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp new file mode 100644 index 0000000..7a05533 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/LoadConfiguration.hpp @@ -0,0 +1,570 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/LoadConfigurations/LoadConfiguration.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/CodeIntegrity.hpp" +#include "LIEF/rust/PE/LoadConfiguration/CHPEMetadata.hpp" +#include "LIEF/rust/PE/LoadConfiguration/DynamicRelocation/DynamicRelocation.hpp" +#include "LIEF/rust/PE/LoadConfiguration/EnclaveConfiguration.hpp" +#include "LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp" +#include "LIEF/rust/optional.hpp" + +class PE_LoadConfiguration_guard_function_t + : public Mirror { + public: + using lief_t = LIEF::PE::LoadConfiguration::guard_function_t; + using Mirror::Mirror; + + auto rva() const { + return get().rva; + } + auto extra() const { + return get().extra; + } +}; + +class PE_LoadConfiguration : public Mirror { + public: + using lief_t = LIEF::PE::LoadConfiguration; + using Mirror::Mirror; + + class it_guard_cf_functions + : public Iterator { + public: + it_guard_cf_functions(const PE_LoadConfiguration::lief_t& src) : + Iterator(src.guard_cf_functions()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_guard_address_taken_iat_entries + : public Iterator { + public: + it_guard_address_taken_iat_entries(const PE_LoadConfiguration::lief_t& src) : + Iterator(src.guard_address_taken_iat_entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_guard_long_jump_targets + : public Iterator { + public: + it_guard_long_jump_targets(const PE_LoadConfiguration::lief_t& src) : + Iterator(src.guard_long_jump_targets()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_guard_eh_continuation + : public Iterator { + public: + it_guard_eh_continuation(const PE_LoadConfiguration::lief_t& src) : + Iterator(src.guard_eh_continuation_functions()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_dynamic_relocations + : public Iterator { + public: + it_dynamic_relocations(const PE_LoadConfiguration::lief_t& src) : + Iterator(src.dynamic_relocations()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto characteristics() const { + return get().characteristics(); + } + auto size() const { + return get().size(); + } + auto timedatestamp() const { + return get().timedatestamp(); + } + auto major_version() const { + return get().major_version(); + } + auto minor_version() const { + return get().minor_version(); + } + auto global_flags_clear() const { + return get().global_flags_clear(); + } + auto global_flags_set() const { + return get().global_flags_set(); + } + auto critical_section_default_timeout() const { + return get().critical_section_default_timeout(); + } + auto decommit_free_block_threshold() const { + return get().decommit_free_block_threshold(); + } + auto decommit_total_free_threshold() const { + return get().decommit_total_free_threshold(); + } + auto lock_prefix_table() const { + return get().lock_prefix_table(); + } + auto maximum_allocation_size() const { + return get().maximum_allocation_size(); + } + auto virtual_memory_threshold() const { + return get().virtual_memory_threshold(); + } + auto process_affinity_mask() const { + return get().process_affinity_mask(); + } + auto process_heap_flags() const { + return get().process_heap_flags(); + } + auto csd_version() const { + return get().csd_version(); + } + auto reserved1() const { + return get().reserved1(); + } + auto dependent_load_flags() const { + return get().dependent_load_flags(); + } + auto editlist() const { + return get().editlist(); + } + auto security_cookie() const { + return get().security_cookie(); + } + + uint64_t se_handler_table(uint32_t& is_set) const { + return details::make_optional(get().se_handler_table(), is_set); + } + + uint64_t se_handler_count(uint32_t& is_set) const { + return details::make_optional(get().se_handler_count(), is_set); + } + + auto seh_functions() const { + return make_unique_vector(get().seh_functions()); + } + + uint64_t guard_cf_check_function_pointer(uint32_t& is_set) const { + return details::make_optional(get().guard_cf_check_function_pointer(), is_set); + } + + uint64_t guard_cf_dispatch_function_pointer(uint32_t& is_set) const { + return details::make_optional(get().guard_cf_dispatch_function_pointer(), + is_set); + } + + uint64_t guard_cf_function_table(uint32_t& is_set) const { + return details::make_optional(get().guard_cf_function_table(), is_set); + } + + uint64_t guard_cf_function_count(uint32_t& is_set) const { + return details::make_optional(get().guard_cf_function_count(), is_set); + } + + auto guard_cf_functions() const { + return std::make_unique(get()); + } + + auto guard_flags(uint32_t& is_set) const { + return details::make_optional(get().guard_flags(), is_set); + } + + auto code_integrity() const { + return details::try_unique(get().code_integrity()); + } + + uint64_t guard_address_taken_iat_entry_table(uint32_t& is_set) const { + return details::make_optional(get().guard_address_taken_iat_entry_table(), + is_set); + } + + uint64_t guard_address_taken_iat_entry_count(uint32_t& is_set) const { + return details::make_optional(get().guard_address_taken_iat_entry_count(), + is_set); + } + + auto guard_address_taken_iat_entries() const { + return std::make_unique(get()); + } + + uint64_t guard_long_jump_target_table(uint32_t& is_set) const { + return details::make_optional(get().guard_long_jump_target_table(), is_set); + } + + uint64_t guard_long_jump_target_count(uint32_t& is_set) const { + return details::make_optional(get().guard_long_jump_target_count(), is_set); + } + + auto guard_long_jump_targets() const { + return std::make_unique(get()); + } + + uint64_t dynamic_value_reloc_table(uint32_t& is_set) const { + return details::make_optional(get().dynamic_value_reloc_table(), is_set); + } + + uint64_t hybrid_metadata_pointer(uint32_t& is_set) const { + return details::make_optional(get().hybrid_metadata_pointer(), is_set); + } + + uint64_t chpe_metadata_pointer(uint32_t& is_set) const { + return details::make_optional(get().chpe_metadata_pointer(), is_set); + } + + auto chpe_metadata() const { + return details::try_unique(get().chpe_metadata()); + } + + uint64_t guard_rf_failure_routine(uint32_t& is_set) const { + return details::make_optional(get().guard_rf_failure_routine(), is_set); + } + + uint64_t guard_rf_failure_routine_function_pointer(uint32_t& is_set) const { + return details::make_optional( + get().guard_rf_failure_routine_function_pointer(), is_set + ); + } + + auto dynamic_value_reloctable_offset(uint32_t& is_set) const { + return details::make_optional(get().dynamic_value_reloctable_offset(), is_set); + } + + auto dynamic_value_reloctable_section(uint32_t& is_set) const { + return details::make_optional(get().dynamic_value_reloctable_section(), + is_set); + } + + auto dynamic_relocations() const { + return std::make_unique(get()); + } + + auto reserved2(uint32_t& is_set) const { + return details::make_optional(get().reserved2(), is_set); + } + + uint64_t guard_rf_verify_stackpointer_function_pointer(uint32_t& is_set) const { + return details::make_optional( + get().guard_rf_verify_stackpointer_function_pointer(), is_set + ); + } + + auto hotpatch_table_offset(uint32_t& is_set) const { + return details::make_optional(get().hotpatch_table_offset(), is_set); + } + + auto reserved3(uint32_t& is_set) const { + return details::make_optional(get().reserved3(), is_set); + } + + uint64_t enclave_configuration_ptr(uint32_t& is_set) const { + return details::make_optional(get().enclave_configuration_ptr(), is_set); + } + + auto enclave_config() const { + return details::try_unique(get().enclave_config()); + } + + uint64_t volatile_metadata_pointer(uint32_t& is_set) const { + return details::make_optional(get().volatile_metadata_pointer(), is_set); + } + + auto volatile_metadata() const { + return details::try_unique(get().volatile_metadata()); + } + + uint64_t guard_eh_continuation_table(uint32_t& is_set) const { + return details::make_optional(get().guard_eh_continuation_table(), is_set); + } + + uint64_t guard_eh_continuation_count(uint32_t& is_set) const { + return details::make_optional(get().guard_eh_continuation_count(), is_set); + } + + auto guard_eh_continuation_functions() const { + return std::make_unique(get()); + } + + uint64_t guard_xfg_check_function_pointer(uint32_t& is_set) const { + return details::make_optional(get().guard_xfg_check_function_pointer(), + is_set); + } + + uint64_t guard_xfg_dispatch_function_pointer(uint32_t& is_set) const { + return details::make_optional(get().guard_xfg_dispatch_function_pointer(), + is_set); + } + + uint64_t guard_xfg_table_dispatch_function_pointer(uint32_t& is_set) const { + return details::make_optional( + get().guard_xfg_table_dispatch_function_pointer(), is_set + ); + } + + uint64_t cast_guard_os_determined_failure_mode(uint32_t& is_set) const { + return details::make_optional(get().cast_guard_os_determined_failure_mode(), + is_set); + } + + uint64_t guard_memcpy_function_pointer(uint32_t& is_set) const { + return details::make_optional(get().guard_memcpy_function_pointer(), is_set); + } + + uint64_t uma_function_pointers(uint32_t& is_set) const { + return details::make_optional(get().uma_function_pointers(), is_set); + } + + auto set_characteristics(uint32_t characteristics) { + get().characteristics(characteristics); + } + + auto set_size(uint32_t value) { + get().size(value); + } + + auto set_timedatestamp(uint32_t timedatestamp) { + get().timedatestamp(timedatestamp); + } + + auto set_major_version(uint16_t major_version) { + get().major_version(major_version); + } + + auto set_minor_version(uint16_t minor_version) { + get().minor_version(minor_version); + } + + auto set_global_flags_clear(uint32_t global_flags_clear) { + get().global_flags_clear(global_flags_clear); + } + + auto set_global_flags_set(uint32_t global_flags_set) { + get().global_flags_set(global_flags_set); + } + + auto set_critical_section_default_timeout(uint32_t val) { + get().critical_section_default_timeout(val); + } + + auto set_decommit_free_block_threshold(uint64_t val) { + get().decommit_free_block_threshold(val); + } + + auto set_decommit_total_free_threshold(uint64_t val) { + get().decommit_total_free_threshold(val); + } + + auto set_lock_prefix_table(uint64_t val) { + get().lock_prefix_table(val); + } + + auto set_maximum_allocation_size(uint64_t val) { + get().maximum_allocation_size(val); + } + + auto set_virtual_memory_threshold(uint64_t val) { + get().virtual_memory_threshold(val); + } + + auto set_process_affinity_mask(uint64_t val) { + get().process_affinity_mask(val); + } + + auto set_process_heap_flags(uint32_t val) { + get().process_heap_flags(val); + } + + auto set_csd_version(uint16_t val) { + get().csd_version(val); + } + + auto set_reserved1(uint16_t val) { + get().reserved1(val); + } + + auto set_dependent_load_flags(uint16_t val) { + get().dependent_load_flags(val); + } + + auto set_editlist(uint32_t val) { + get().editlist(val); + } + + auto set_security_cookie(uint64_t val) { + get().security_cookie(val); + } + + auto set_se_handler_table(uint64_t val) { + get().se_handler_table(val); + } + + auto set_se_handler_count(uint64_t val) { + get().se_handler_count(val); + } + + auto set_guard_cf_check_function_pointer(uint64_t val) { + get().guard_cf_check_function_pointer(val); + } + + auto set_guard_cf_dispatch_function_pointer(uint64_t val) { + get().guard_cf_dispatch_function_pointer(val); + } + + auto set_guard_cf_function_table(uint64_t val) { + get().guard_cf_function_table(val); + } + + auto set_guard_cf_function_count(uint64_t val) { + get().guard_cf_function_count(val); + } + + auto set_guard_flags(uint32_t flags) { + get().guard_flags(flags); + } + + auto set_guard_address_taken_iat_entry_table(uint64_t value) { + get().guard_address_taken_iat_entry_table(value); + } + + auto set_guard_address_taken_iat_entry_count(uint64_t value) { + get().guard_address_taken_iat_entry_count(value); + } + + auto set_guard_long_jump_target_table(uint64_t value) { + get().guard_long_jump_target_table(value); + } + + auto set_guard_long_jump_target_count(uint64_t value) { + get().guard_long_jump_target_count(value); + } + + auto set_dynamic_value_reloc_table(uint64_t value) { + get().dynamic_value_reloc_table(value); + } + + auto set_hybrid_metadata_pointer(uint64_t value) { + get().hybrid_metadata_pointer(value); + } + + auto set_guard_rf_failure_routine(uint64_t value) { + get().guard_rf_failure_routine(value); + } + + auto set_guard_rf_failure_routine_function_pointer(uint64_t value) { + get().guard_rf_failure_routine_function_pointer(value); + } + + auto set_dynamic_value_reloctable_offset(uint32_t value) { + get().dynamic_value_reloctable_offset(value); + } + + auto set_dynamic_value_reloctable_section(uint16_t value) { + get().dynamic_value_reloctable_section(value); + } + + auto set_reserved2(uint16_t value) { + get().reserved2(value); + } + + auto set_guard_rf_verify_stackpointer_function_pointer(uint64_t value) { + get().guard_rf_verify_stackpointer_function_pointer(value); + } + + auto set_hotpatch_table_offset(uint32_t value) { + get().hotpatch_table_offset(value); + } + + auto set_reserved3(uint32_t value) { + get().reserved3(value); + } + + auto set_enclave_configuration_ptr(uint64_t value) { + get().enclave_configuration_ptr(value); + } + + auto set_volatile_metadata_pointer(uint64_t value) { + get().volatile_metadata_pointer(value); + } + + auto set_guard_eh_continuation_table(uint64_t value) { + get().guard_eh_continuation_table(value); + } + + auto set_guard_eh_continuation_count(uint64_t value) { + get().guard_eh_continuation_count(value); + } + + auto set_guard_xfg_check_function_pointer(uint64_t value) { + get().guard_xfg_check_function_pointer(value); + } + + auto set_guard_xfg_dispatch_function_pointer(uint64_t value) { + get().guard_xfg_dispatch_function_pointer(value); + } + + auto set_guard_xfg_table_dispatch_function_pointer(uint64_t value) { + get().guard_xfg_table_dispatch_function_pointer(value); + } + + auto set_cast_guard_os_determined_failure_mode(uint64_t value) { + get().cast_guard_os_determined_failure_mode(value); + } + + auto set_guard_memcpy_function_pointer(uint64_t value) { + get().guard_memcpy_function_pointer(value); + } + + auto set_uma_function_pointers(uint64_t value) { + get().uma_function_pointers(value); + } +}; + +using PE_LoadConfiguration_it_guard_cf_functions = + PE_LoadConfiguration::it_guard_cf_functions; +using PE_LoadConfiguration_it_guard_address_taken_iat_entries = + PE_LoadConfiguration::it_guard_address_taken_iat_entries; +using PE_LoadConfiguration_it_guard_long_jump_targets = + PE_LoadConfiguration::it_guard_long_jump_targets; +using PE_LoadConfiguration_it_guard_eh_continuation = + PE_LoadConfiguration::it_guard_eh_continuation; +using PE_LoadConfiguration_it_dynamic_relocations = + PE_LoadConfiguration::it_dynamic_relocations; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp new file mode 100644 index 0000000..fdb6bdb --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/LoadConfiguration/VolatileMetadata.hpp @@ -0,0 +1,93 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/LoadConfigurations/VolatileMetadata.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_VolatileMetadata_range_t + : public Mirror { + public: + using lief_t = LIEF::PE::VolatileMetadata::range_t; + using Mirror::Mirror; + + auto start() const { + return get().start; + } + auto size() const { + return get().size; + } + auto end() const { + return get().end(); + } +}; + +class PE_VolatileMetadata : public Mirror { + public: + using lief_t = LIEF::PE::VolatileMetadata; + using Mirror::Mirror; + + class it_ranges + : public Iterator { + public: + it_ranges(const PE_VolatileMetadata::lief_t& src) : + Iterator(src.info_ranges()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto size() const { + return get().size(); + } + auto min_version() const { + return get().min_version(); + } + auto max_version() const { + return get().max_version(); + } + auto access_table_rva() const { + return get().access_table_rva(); + } + auto access_table_size() const { + return get().access_table_size(); + } + auto info_range_rva() const { + return get().info_range_rva(); + } + auto info_ranges_size() const { + return get().info_ranges_size(); + } + + const auto& access_table() const { + return get().access_table(); + } + + auto info_ranges() const { + return std::make_unique(get()); + } + + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +using PE_VolatileMetadata_it_ranges = PE_VolatileMetadata::it_ranges; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/OptionalHeader.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/OptionalHeader.hpp new file mode 100644 index 0000000..4a172a2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/OptionalHeader.hpp @@ -0,0 +1,134 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/OptionalHeader.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_OptionalHeader : private Mirror { + public: + using lief_t = LIEF::PE::OptionalHeader; + using Mirror::Mirror; + + auto magic() const { + return to_int(get().magic()); + } + + auto major_linker_version() const { + return get().major_linker_version(); + } + auto minor_linker_version() const { + return get().minor_linker_version(); + } + auto sizeof_code() const { + return get().sizeof_code(); + } + auto sizeof_initialized_data() const { + return get().sizeof_initialized_data(); + } + auto sizeof_uninitialized_data() const { + return get().sizeof_uninitialized_data(); + } + auto addressof_entrypoint() const { + return get().addressof_entrypoint(); + } + auto baseof_code() const { + return get().baseof_code(); + } + auto baseof_data() const { + return get().baseof_data(); + } + auto imagebase() const { + return get().imagebase(); + } + auto section_alignment() const { + return get().section_alignment(); + } + auto file_alignment() const { + return get().file_alignment(); + } + auto major_operating_system_version() const { + return get().major_operating_system_version(); + } + auto minor_operating_system_version() const { + return get().minor_operating_system_version(); + } + auto major_image_version() const { + return get().major_image_version(); + } + auto minor_image_version() const { + return get().minor_image_version(); + } + auto major_subsystem_version() const { + return get().major_subsystem_version(); + } + auto minor_subsystem_version() const { + return get().minor_subsystem_version(); + } + auto win32_version_value() const { + return get().win32_version_value(); + } + auto sizeof_image() const { + return get().sizeof_image(); + } + auto sizeof_headers() const { + return get().sizeof_headers(); + } + auto checksum() const { + return get().checksum(); + } + auto subsystem() const { + return as_u64(get().subsystem()); + } + auto dll_characteristics() const { + return get().dll_characteristics(); + } + auto sizeof_stack_reserve() const { + return get().sizeof_stack_reserve(); + } + auto sizeof_stack_commit() const { + return get().sizeof_stack_commit(); + } + auto sizeof_heap_reserve() const { + return get().sizeof_heap_reserve(); + } + auto sizeof_heap_commit() const { + return get().sizeof_heap_commit(); + } + auto loader_flags() const { + return get().loader_flags(); + } + auto numberof_rva_and_size() const { + return get().numberof_rva_and_size(); + } + + auto set_addressof_entrypoint(uint32_t value) { + get().addressof_entrypoint(value); + } + + auto set_imagebase(uint64_t value) { + get().imagebase(value); + } + + auto add_dll_characteristic(uint32_t value) { + get().add(LIEF::PE::OptionalHeader::DLL_CHARACTERISTICS(value)); + } + + auto remove_dll_characteristic(uint32_t value) { + get().remove(LIEF::PE::OptionalHeader::DLL_CHARACTERISTICS(value)); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Relocation.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Relocation.hpp new file mode 100644 index 0000000..222d4d7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Relocation.hpp @@ -0,0 +1,52 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/Relocation.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/RelocationEntry.hpp" + +class PE_Relocation : Mirror { + public: + using lief_t = LIEF::PE::Relocation; + using Mirror::Mirror; + + class it_entries + : public Iterator { + public: + it_entries(const PE_Relocation::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t virtual_address() const { + return get().virtual_address(); + } + uint32_t block_size() const { + return get().block_size(); + } + + auto entries() const { + return std::make_unique(get()); + } +}; + +using PE_Relocation_it_entries = PE_Relocation::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/RelocationEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/RelocationEntry.hpp new file mode 100644 index 0000000..e342ebc --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/RelocationEntry.hpp @@ -0,0 +1,42 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/RelocationEntry.hpp" +#include "LIEF/rust/Abstract/Relocation.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_RelocationEntry : public AbstractRelocation { + public: + using lief_t = LIEF::PE::RelocationEntry; + PE_RelocationEntry(const lief_t& obj) : + AbstractRelocation(obj) {} + + uint64_t position() const { + return impl().position(); + } + uint32_t get_type() const { + return to_int(impl().type()); + } + uint16_t data() const { + return impl().data(); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceAccelerator.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceAccelerator.hpp new file mode 100644 index 0000000..24e0cb7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceAccelerator.hpp @@ -0,0 +1,43 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/resources/ResourceAccelerator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ResourceAccelerator : private Mirror { + public: + using lief_t = LIEF::PE::ResourceAccelerator; + using Mirror::Mirror; + + auto flags() const { + return get().flags(); + } + auto ansi() const { + return get().ansi(); + } + auto id() const { + return get().id(); + } + auto padding() const { + return get().padding(); + } + + auto ansi_str() const { + return to_unique_string(std::string(get().ansi_str())); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceData.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceData.hpp new file mode 100644 index 0000000..f30b457 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceData.hpp @@ -0,0 +1,78 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/ResourceData.hpp" +#include "LIEF/rust/PE/ResourceNode.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_ResourceData : public PE_ResourceNode { + public: + using lief_t = LIEF::PE::ResourceData; + PE_ResourceData(const lief_t& obj) : + PE_ResourceNode(obj) {} + PE_ResourceData(std::unique_ptr obj) : + PE_ResourceNode(std::move(obj)) {} + + static auto create_from_data(const uint8_t* buffer, size_t size) { + return std::make_unique( + std::make_unique(std::vector{buffer, buffer + size}) + ); + } + + static auto create() { + return std::make_unique(std::make_unique()); + } + + + auto code_page() const { + return impl().code_page(); + } + auto reserved() const { + return impl().reserved(); + } + auto offset() const { + return impl().offset(); + } + + auto content() const { + return make_span(impl().content()); + } + + auto set_code_page(uint32_t value) { + impl().code_page(value); + } + + auto set_reserved(uint32_t value) { + impl().reserved(value); + } + + auto set_content(const uint8_t* ptr, size_t size) { + impl().content(ptr, size); + } + + static auto classof(const PE_ResourceNode& node) { + return lief_t::classof(&node.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceDirectory.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceDirectory.hpp new file mode 100644 index 0000000..ad6e4b7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceDirectory.hpp @@ -0,0 +1,65 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/ResourceDirectory.hpp" +#include "LIEF/rust/PE/ResourceNode.hpp" + +class PE_ResourceDirectory : public PE_ResourceNode { + public: + using lief_t = LIEF::PE::ResourceDirectory; + PE_ResourceDirectory(const lief_t& obj) : + PE_ResourceNode(obj) {} + PE_ResourceDirectory(std::unique_ptr obj) : + PE_ResourceNode(std::move(obj)) {} + + static auto create_from_id(uint32_t id) { + return std::make_unique(std::make_unique(id)); + } + + static auto create() { + return std::make_unique(std::make_unique()); + } + + + uint32_t characteristics() const { + return impl().characteristics(); + } + uint32_t time_date_stamp() const { + return impl().time_date_stamp(); + } + uint32_t major_version() const { + return impl().major_version(); + } + uint32_t minor_version() const { + return impl().minor_version(); + } + uint32_t numberof_name_entries() const { + return impl().numberof_name_entries(); + } + uint32_t numberof_id_entries() const { + return impl().numberof_id_entries(); + } + + static auto classof(const PE_ResourceNode& node) { + return lief_t::classof(&node.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceIcon.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceIcon.hpp new file mode 100644 index 0000000..a3122d4 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceIcon.hpp @@ -0,0 +1,61 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/resources/ResourceIcon.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_ResourceIcon : private Mirror { + public: + using lief_t = LIEF::PE::ResourceIcon; + using Mirror::Mirror; + + auto id() const { + return get().id(); + } + auto lang() const { + return get().lang(); + } + auto sublang() const { + return get().sublang(); + } + auto width() const { + return get().width(); + } + auto height() const { + return get().height(); + } + auto color_count() const { + return get().color_count(); + } + auto reserved() const { + return get().reserved(); + } + auto planes() const { + return get().planes(); + } + auto bit_count() const { + return get().bit_count(); + } + auto size() const { + return get().size(); + } + + Span pixels() const { + return make_span(get().pixels()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceNode.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceNode.hpp new file mode 100644 index 0000000..b1ee3ed --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceNode.hpp @@ -0,0 +1,83 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/ResourceNode.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ResourceNode : public Mirror { + public: + using lief_t = LIEF::PE::ResourceNode; + using Mirror::Mirror; + + class it_childs + : public Iterator { + public: + it_childs(const PE_ResourceNode::lief_t& src) : + Iterator(src.childs()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + static auto from_slice(const uint8_t* buffer, size_t size, uint64_t rva) { + return details::try_unique( + LIEF::PE::ResourceNode::parse(buffer, size, rva) + ); + } + + auto has_name() const { + return get().has_name(); + } + auto name() const { + return to_unique_string(get().utf8_name()); + } + + auto id() const { + return get().id(); + } + auto depth() const { + return get().depth(); + } + auto is_directory() const { + return get().is_directory(); + } + auto is_data() const { + return get().is_data(); + } + auto childs() const { + return std::make_unique(get()); + } + + auto add_child(const PE_ResourceNode& node) { + return std::make_unique(get().add_child(node.get())); + } + + auto delete_child(uint32_t id) { + get().delete_child(id); + } + + auto print() const { + return to_unique_string(get().to_string()); + } +}; + +using PE_ResourceNode_it_childs = PE_ResourceNode::it_childs; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceVersion.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceVersion.hpp new file mode 100644 index 0000000..2c13bca --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourceVersion.hpp @@ -0,0 +1,215 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include + +#include "LIEF/PE/resources/ResourceStringFileInfo.hpp" +#include "LIEF/PE/resources/ResourceStringTable.hpp" +#include "LIEF/PE/resources/ResourceVar.hpp" +#include "LIEF/PE/resources/ResourceVarFileInfo.hpp" +#include "LIEF/PE/resources/ResourceVersion.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ResourceStringTable_entry_t + : private Mirror { + public: + using lief_t = LIEF::PE::ResourceStringTable::entry_t; + using Mirror::Mirror; + + auto key() const { + return to_unique_string(get().key_u8()); + } + auto value() const { + return to_unique_string(get().value_u8()); + } +}; + +class PE_ResourceStringTable : private Mirror { + public: + using lief_t = LIEF::PE::ResourceStringTable; + using Mirror::Mirror; + + class it_entries + : public Iterator { + public: + it_entries(const PE_ResourceStringTable::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto get_type() const { + return get().type(); + } + auto key() const { + return to_unique_string(get().key_u8()); + } + auto entries() const { + return std::make_unique(get()); + } +}; + +class PE_ResourceVar : private Mirror { + public: + using lief_t = LIEF::PE::ResourceVar; + using Mirror::Mirror; + + auto get_type() const { + return get().type(); + } + auto key() const { + return to_unique_string(get().key_u8()); + } + + auto values() const { + const auto& v = get().values(); + return make_unique_vector(v.begin(), v.end()); + } +}; + +class PE_ResourceStringFileInfo + : private Mirror { + public: + using lief_t = LIEF::PE::ResourceStringFileInfo; + using Mirror::Mirror; + + class it_children + : public Iterator { + public: + it_children(const PE_ResourceStringFileInfo::lief_t& src) : + Iterator(src.children()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto get_type() const { + return get().type(); + } + auto key() const { + return to_unique_string(get().key_u8()); + } + auto children() const { + return std::make_unique(get()); + } +}; + +class PE_ResourceVarFileInfo : private Mirror { + public: + using lief_t = LIEF::PE::ResourceVarFileInfo; + using Mirror::Mirror; + + class it_vars : public Iterator { + public: + it_vars(const PE_ResourceVarFileInfo::lief_t& src) : + Iterator(src.vars()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto get_type() const { + return get().type(); + } + auto key() const { + return to_unique_string(get().key_u8()); + } + auto vars() const { + return std::make_unique(get()); + } +}; + +class PE_ResourceVersion : private Mirror { + public: + using lief_t = LIEF::PE::ResourceVersion; + using Mirror::Mirror; + + auto get_type() const { + return get().type(); + } + auto key() const { + return to_unique_string(get().key_u8()); + } + + auto file_info_signature() const { + return get().file_info().signature; + } + auto file_info_struct_version() const { + return get().file_info().struct_version; + } + auto file_info_file_version_ms() const { + return get().file_info().file_version_ms; + } + auto file_info_file_version_ls() const { + return get().file_info().file_version_ls; + } + auto file_info_product_version_ms() const { + return get().file_info().product_version_ms; + } + auto file_info_product_version_ls() const { + return get().file_info().product_version_ls; + } + auto file_info_file_flags_mask() const { + return get().file_info().file_flags_mask; + } + auto file_info_file_flags() const { + return get().file_info().file_flags; + } + auto file_info_file_os() const { + return get().file_info().file_os; + } + auto file_info_file_type() const { + return get().file_info().file_type; + } + auto file_info_file_subtype() const { + return get().file_info().file_subtype; + } + auto file_info_file_date_ms() const { + return get().file_info().file_date_ms; + } + auto file_info_file_date_ls() const { + return get().file_info().file_date_ls; + } + + auto string_file_info() const { + return details::try_unique( + get().string_file_info() + ); + } + + auto var_file_info() const { + return details::try_unique(get().var_file_info()); + } +}; + +using PE_ResourceStringFileInfo_it_children = + PE_ResourceStringFileInfo::it_children; +using PE_ResourceStringTable_it_entries = PE_ResourceStringTable::it_entries; +using PE_ResourceVarFileInfo_it_vars = PE_ResourceVarFileInfo::it_vars; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/ResourcesManager.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourcesManager.hpp new file mode 100644 index 0000000..3112fb2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/ResourcesManager.hpp @@ -0,0 +1,156 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/ResourcesManager.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/ResourceAccelerator.hpp" +#include "LIEF/rust/PE/ResourceIcon.hpp" +#include "LIEF/rust/PE/ResourceNode.hpp" +#include "LIEF/rust/PE/ResourceVersion.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ResourcesManager_string_entry_t + : private Mirror { + public: + using lief_t = LIEF::PE::ResourcesManager::string_entry_t; + using Mirror::Mirror; + + auto string() const { + return to_unique_string(get().string_u8()); + } + auto id() const { + return get().id; + } +}; + +class PE_ResourcesManager : private Mirror { + public: + using lief_t = LIEF::PE::ResourcesManager; + using Mirror::Mirror; + + class it_icons : public Iterator { + public: + it_icons(const PE_ResourcesManager::lief_t& src) : + Iterator(src.icons()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_version + : public ContainerIterator> { + public: + it_version(const PE_ResourcesManager::lief_t& src) : + ContainerIterator(src.version()) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + class it_accelerator + : public Iterator { + public: + it_accelerator(const PE_ResourcesManager::lief_t& src) : + Iterator(src.accelerator()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_string_table_entry + : public ContainerIterator { + public: + using container_t = LIEF::PE::ResourcesManager::strings_table_t; + it_string_table_entry(const PE_ResourcesManager::lief_t& src) : + ContainerIterator(src.string_table()) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto find_node_type(uint32_t type) const { + return details::try_unique( + get().get_node_type(LIEF::PE::ResourcesManager::TYPE(type)) + ); + } + + auto get_types() const { + auto values = make_unique_vector(); + auto types = get().get_types(); + std::transform(types.begin(), types.end(), std::back_inserter(*values), + [](LIEF::PE::ResourcesManager::TYPE ty) { + return (uint32_t)ty; + }); + return values; + } + + auto has_type(uint32_t type) const { + return get().has_type(LIEF::PE::ResourcesManager::TYPE(type)); + } + + auto manifest() const { + return to_unique_string(get().manifest()); + } + auto set_manifest(const std::string& str) { + get().manifest(str); + } + auto print_tree() const { + return to_unique_string(get().print()); + } + + auto print_tree_with_depth(uint32_t depth) const { + return to_unique_string(get().print(depth)); + } + auto html() const { + return make_unique_vector(get().html()); + } + auto icons() const { + return std::make_unique(get()); + } + auto version() const { + return std::make_unique(get()); + } + auto accelerator() const { + return std::make_unique(get()); + } + auto string_table() const { + return std::make_unique(get()); + } +}; + +using PE_ResourcesManager_it_icons = PE_ResourcesManager::it_icons; +using PE_ResourcesManager_it_version = PE_ResourcesManager::it_version; +using PE_ResourcesManager_it_accelerator = PE_ResourcesManager::it_accelerator; +using PE_ResourcesManager_it_string_table_entry = + PE_ResourcesManager::it_string_table_entry; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/RichEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/RichEntry.hpp new file mode 100644 index 0000000..8785400 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/RichEntry.hpp @@ -0,0 +1,35 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/RichEntry.hpp" +#include "LIEF/rust/Mirror.hpp" + +class PE_RichEntry : private Mirror { + public: + using lief_t = LIEF::PE::RichEntry; + using Mirror::Mirror; + + uint16_t id() const { + return get().id(); + } + uint16_t build_id() const { + return get().build_id(); + } + uint32_t count() const { + return get().count(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/RichHeader.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/RichHeader.hpp new file mode 100644 index 0000000..d09cd1a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/RichHeader.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include + +#include "LIEF/PE/RichHeader.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/RichEntry.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_RichHeader : Mirror { + public: + using lief_t = LIEF::PE::RichHeader; + using Mirror::Mirror; + class it_entries + : public Iterator { + public: + it_entries(const PE_RichHeader::lief_t& src) : + Iterator(src.entries()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t key() const { + return get().key(); + } + auto set_key(uint32_t key) { + get().key(key); + } + + auto raw() const { + return make_unique_vector(get().raw()); + } + auto raw_with_key(uint32_t xor_key) const { + return make_unique_vector(get().raw(xor_key)); + } + + auto entries() const { + return std::make_unique(get()); + } +}; + +using PE_RichHeader_it_entries = PE_RichHeader::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionAArch64.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionAArch64.hpp new file mode 100644 index 0000000..b9d78bd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionAArch64.hpp @@ -0,0 +1,164 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/ExceptionInfo.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/PE/exceptions_info/AArch64/PackedFunction.hpp" +#include "LIEF/PE/exceptions_info/AArch64/UnpackedFunction.hpp" +#include "LIEF/PE/exceptions_info/RuntimeFunctionAArch64.hpp" + +class PE_RuntimeFunctionAArch64 : public PE_ExceptionInfo { + public: + using lief_t = LIEF::PE::RuntimeFunctionAArch64; + PE_RuntimeFunctionAArch64(const lief_t& obj) : + PE_ExceptionInfo(obj) {} + + auto length() const { + return impl().length(); + } + auto flag() const { + return as_u32(impl().flag()); + } + auto rva_end() const { + return impl().rva_end(); + } + + static auto classof(const PE_ExceptionInfo& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_aarch64_PackedFunction : public PE_RuntimeFunctionAArch64 { + public: + using lief_t = LIEF::PE::unwind_aarch64::PackedFunction; + + auto frame_size() const { + return impl().frame_size(); + } + auto reg_I() const { + return impl().reg_I(); + } + auto reg_F() const { + return impl().reg_F(); + } + auto H() const { + return impl().H(); + } + auto CR() const { + return impl().CR(); + } + + static auto classof(const PE_RuntimeFunctionAArch64& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + + +class PE_unwind_aarch64_UnpackedFunction_epilog_scope_t + : public Mirror { + public: + using lief_t = LIEF::PE::unwind_aarch64::UnpackedFunction::epilog_scope_t; + using Mirror::Mirror; + + auto start_offset() const { + return get().start_offset; + } + auto start_index() const { + return get().start_index; + } + auto reserved() const { + return get().reserved; + } +}; + +class PE_unwind_aarch64_UnpackedFunction : public PE_RuntimeFunctionAArch64 { + public: + using lief_t = LIEF::PE::unwind_aarch64::UnpackedFunction; + + class it_const_epilog_scopes + : public Iterator< + PE_unwind_aarch64_UnpackedFunction_epilog_scope_t, + LIEF::PE::unwind_aarch64::UnpackedFunction::it_const_epilog_scopes + > { + public: + it_const_epilog_scopes(const PE_unwind_aarch64_UnpackedFunction::lief_t& src) : + Iterator(std::move(src.epilog_scopes())) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + + auto xdata_rva() const { + return impl().xdata_rva(); + } + auto version() const { + return impl().version(); + } + auto X() const { + return impl().X(); + } + auto E() const { + return impl().E(); + } + auto epilog_count() const { + return impl().epilog_count(); + } + auto epilog_offset() const { + return impl().epilog_offset(); + } + auto code_words() const { + return impl().code_words(); + } + auto exception_handler() const { + return impl().exception_handler(); + } + auto unwind_code() const { + return make_span(impl().unwind_code()); + } + + auto epilog_scopes() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_RuntimeFunctionAArch64& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_unwind_aarch64_UnpackedFunction_it_const_epilog_scopes = + PE_unwind_aarch64_UnpackedFunction::it_const_epilog_scopes; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionX64.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionX64.hpp new file mode 100644 index 0000000..3e29251 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/RuntimeFunctionX64.hpp @@ -0,0 +1,129 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/exceptions_info/RuntimeFunctionX64.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/ExceptionInfo.hpp" +#include "LIEF/rust/PE/UnwindCodeX64.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" + +class PE_RuntimeFunctionX64_unwind_info_t; + +class PE_RuntimeFunctionX64 : public PE_ExceptionInfo { + public: + using lief_t = LIEF::PE::RuntimeFunctionX64; + PE_RuntimeFunctionX64(const lief_t& obj) : + PE_ExceptionInfo(obj) {} + + auto rva_end() const { + return impl().rva_end(); + } + + auto unwind_rva() const { + return impl().unwind_rva(); + } + + auto size() const { + return impl().size(); + } + + auto unwind_info() const { + return details::try_unique( + impl().unwind_info() + ); + } + + static auto classof(const PE_ExceptionInfo& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_RuntimeFunctionX64_unwind_info_t + : public Mirror { + public: + using lief_t = LIEF::PE::RuntimeFunctionX64::unwind_info_t; + using Mirror::Mirror; + + class it_opcodes : public ContainerIterator< + PE_unwind_x64_Code, + std::vector> + > { + public: + using container_t = std::vector>; + it_opcodes(container_t content) : + ContainerIterator(std::move(content)) {} + auto next() { + return ContainerIterator::next(); + } + auto size() const { + return ContainerIterator::size(); + } + }; + + auto version() const { + return get().version; + } + + auto flags() const { + return get().flags; + } + + auto sizeof_prologue() const { + return get().sizeof_prologue; + } + + auto count_opcodes() const { + return get().count_opcodes; + } + + auto frame_reg() const { + return get().frame_reg; + } + + auto frame_reg_offset() const { + return get().frame_reg_offset; + } + auto raw_opcodes() const { + return make_span(get().raw_opcodes); + } + + uint32_t handler(uint32_t& is_set) const { + return details::make_optional(get().handler, is_set); + } + + auto opcodes() const { + it_opcodes::container_t ops = get().opcodes(); + return std::make_unique(std::move(ops)); + } + + auto chained() const { + return details::try_unique(get().chained); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +using PE_RuntimeFunctionX64_unwind_info_t_it_opcodes = + PE_RuntimeFunctionX64_unwind_info_t::it_opcodes; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/Section.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/Section.hpp new file mode 100644 index 0000000..c1c4116 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/Section.hpp @@ -0,0 +1,98 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/Section.hpp" +#include "LIEF/rust/Abstract/Section.hpp" +#include "LIEF/rust/COFF/String.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_Binary; +class PE_Factory; + +class PE_Section : public AbstractSection { + public: + friend class PE_Binary; + friend class PE_Factory; + + using lief_t = LIEF::PE::Section; + PE_Section(const lief_t& sec) : + AbstractSection(sec) {} + PE_Section(std::unique_ptr impl) : + AbstractSection(std::move(impl)) {} + + static auto create() { + return std::make_unique(std::make_unique()); + } + + static auto create_with_name(const std::string& name) { + return std::make_unique(std::make_unique(name)); + } + + static auto create_with_content(const std::string& name, const uint8_t* buffer, + size_t size) { + return std::make_unique( + std::make_unique(name, std::vector{buffer, buffer + size}) + ); + } + + auto sizeof_raw_data() const { + return impl().sizeof_raw_data(); + } + auto virtual_size() const { + return impl().virtual_size(); + } + auto pointerto_raw_data() const { + return impl().pointerto_raw_data(); + } + auto pointerto_relocation() const { + return impl().pointerto_relocation(); + } + auto pointerto_line_numbers() const { + return impl().pointerto_line_numbers(); + } + auto numberof_relocations() const { + return impl().numberof_relocations(); + } + auto numberof_line_numbers() const { + return impl().numberof_line_numbers(); + } + auto characteristics() const { + return impl().characteristics(); + } + + auto is_discardable() const { + return impl().is_discardable(); + } + + Span padding() const { + return make_span(impl().padding()); + } + + auto coff_string() const { + return details::try_unique(impl().coff_string()); + } + + auto set_virtual_size(uint32_t virtual_size) { + impl().virtual_size(virtual_size); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/TLS.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/TLS.hpp new file mode 100644 index 0000000..d47327b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/TLS.hpp @@ -0,0 +1,97 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/TLS.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/DataDirectories.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_TLS : public Mirror { + public: + using lief_t = LIEF::PE::TLS; + using Mirror::Mirror; + + static auto create() { + return std::make_unique(std::make_unique()); + } + + auto callbacks() const { + return make_unique_vector(get().callbacks()); + } + + auto addressof_index() const { + return get().addressof_index(); + } + auto addressof_callbacks() const { + return get().addressof_callbacks(); + } + auto sizeof_zero_fill() const { + return get().sizeof_zero_fill(); + } + auto characteristics() const { + return get().characteristics(); + } + + auto data_template() const { + return make_span(get().data_template()); + } + auto addressof_raw_data() const { + return make_unique_vector( + details::make_vector(get().addressof_raw_data()) + ); + } + + auto section() const { + return details::try_unique( + get().section() + ); // NOLINT(lang-analyzer-cplusplus.NewDeleteLeaks) + } + auto data_directory() const { + return details::try_unique( + get().directory() + ); // NOLINT(lang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto add_callback(uint64_t addr) { + get().add_callback(addr); + } + + auto set_callbacks(const uint64_t* ptr, size_t size) { + get().callbacks({ptr, ptr + size}); + } + + auto set_addressof_index(uint64_t value) { + get().addressof_index(value); + } + + auto set_addressof_callback(uint64_t value) { + get().addressof_callbacks(value); + } + + auto set_sizeof_zero_fill(uint32_t value) { + get().sizeof_zero_fill(value); + } + + auto set_characteristics(uint32_t value) { + get().characteristics(value); + } + + auto set_data_template(const uint8_t* ptr, size_t size) { + get().data_template({ptr, ptr + size}); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/UnwindCodeX64.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/UnwindCodeX64.hpp new file mode 100644 index 0000000..eaae703 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/UnwindCodeX64.hpp @@ -0,0 +1,204 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/exceptions_info/UnwindCodeX64.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_unwind_x64_Code : public Mirror { + public: + using lief_t = LIEF::PE::ExceptionInfo; + using Mirror::Mirror; + + auto position() const { + return get().position(); + } + + uint32_t opcode() const { + return to_int(get().opcode()); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_unwind_x64_Alloc : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::Alloc; + PE_unwind_x64_Alloc(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto size() const { + return impl().size(); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_PushNonVol : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::PushNonVol; + PE_unwind_x64_PushNonVol(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto reg() const { + return to_int(impl().reg()); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_PushMachFrame : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::PushMachFrame; + PE_unwind_x64_PushMachFrame(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto value() const { + return impl().value(); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_SetFPReg : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::SetFPReg; + PE_unwind_x64_SetFPReg(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto reg() const { + return to_int(impl().reg()); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_SaveNonVolatile : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::SaveNonVolatile; + PE_unwind_x64_SaveNonVolatile(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto reg() const { + return to_int(impl().reg()); + } + auto offset() const { + return impl().offset(); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_SaveXMM128 : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::SaveXMM128; + PE_unwind_x64_SaveXMM128(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto num() const { + return impl().num(); + } + + auto offset() const { + return impl().offset(); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_Epilog : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::Epilog; + PE_unwind_x64_Epilog(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + auto flags() const { + return impl().flags(); + } + + auto size() const { + return impl().size(); + } + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +class PE_unwind_x64_Spare : public PE_unwind_x64_Code { + public: + using lief_t = LIEF::PE::unwind_x64::Spare; + PE_unwind_x64_Spare(const lief_t& obj) : + PE_unwind_x64_Code(obj) {} + + static auto classof(const PE_unwind_x64_Code& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeView.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeView.hpp new file mode 100644 index 0000000..d0a5553 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeView.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/debug/CodeView.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" + +class PE_CodeView : public PE_Debug { + public: + using lief_t = LIEF::PE::CodeView; + PE_CodeView(const lief_t& obj) : + PE_Debug(obj) {} + PE_CodeView(std::unique_ptr obj) : + PE_Debug(std::move(obj)) {} + + uint32_t signature() const { + return to_int(impl().signature()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeViewPDB.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeViewPDB.hpp new file mode 100644 index 0000000..9526862 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/CodeViewPDB.hpp @@ -0,0 +1,83 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/debug/CodeViewPDB.hpp" +#include "LIEF/rust/PE/debug/CodeView.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_CodeViewPDB : public PE_CodeView { + public: + using lief_t = LIEF::PE::CodeViewPDB; + PE_CodeViewPDB(const lief_t& obj) : + PE_CodeView(obj) {} + PE_CodeViewPDB(std::unique_ptr obj) : + PE_CodeView(std::move(obj)) {} + + static auto create() { + return std::make_unique( + std::make_unique() + ); + } + + static auto create_with_filename(const std::string& filename) { + return std::make_unique( + std::make_unique(filename) + ); + } + + auto age() const { + return impl().age(); + } + + auto guid() const { + return to_unique_string(impl().guid()); + } + + auto filename() const { + return to_unique_string(impl().filename()); + } + + auto signature() const { + return make_unique_vector(details::make_vector(impl().signature())); + } + + auto set_filename(const std::string& filename) { + impl().filename(filename); + } + + auto set_age(uint32_t age) { + impl().age(age); + } + + auto set_signature(const uint8_t* array, size_t size) { + assert(sizeof(LIEF::PE::CodeViewPDB::signature_t) == size); + LIEF::PE::CodeViewPDB::signature_t sig; + std::copy(array, array + size, sig.begin()); + impl().signature(sig); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } + lief_t& impl() { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Debug.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Debug.hpp new file mode 100644 index 0000000..e6a6f62 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Debug.hpp @@ -0,0 +1,74 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/debug/Debug.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/Section.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_Debug : public Mirror { + public: + using lief_t = LIEF::PE::Debug; + using Mirror::Mirror; + + auto characteristics() const { + return get().characteristics(); + } + auto timestamp() const { + return get().timestamp(); + } + auto major_version() const { + return get().major_version(); + } + auto minor_version() const { + return get().minor_version(); + } + uint32_t get_type() const { + return to_int(get().type()); + } + auto sizeof_data() const { + return get().sizeof_data(); + } + auto addressof_rawdata() const { + return get().addressof_rawdata(); + } + auto pointerto_rawdata() const { + return get().pointerto_rawdata(); + } + + auto section() const { + return details::try_unique(get().section()); + } + + Span payload() const { + return make_span(get().payload()); + } + + auto set_characteristics(uint32_t value) { + get().characteristics(value); + } + auto set_timestamp(uint32_t value) { + get().timestamp(value); + } + auto set_major_version(uint16_t value) { + get().major_version(value); + } + auto set_minor_version(uint16_t value) { + get().minor_version(value); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/ExDllCharacteristics.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/ExDllCharacteristics.hpp new file mode 100644 index 0000000..8741976 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/ExDllCharacteristics.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/debug/ExDllCharacteristics.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" + +class PE_ExDllCharacteristics : public PE_Debug { + public: + using lief_t = LIEF::PE::ExDllCharacteristics; + PE_ExDllCharacteristics(const lief_t& obj) : + PE_Debug(obj) {} + + uint32_t characteristics() const { + return to_int(impl().characteristics()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/FPO.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/FPO.hpp new file mode 100644 index 0000000..ae3525c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/FPO.hpp @@ -0,0 +1,96 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/debug/FPO.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/helpers.hpp" + + +class PE_FPO_entry_t : private Mirror { + public: + using lief_t = LIEF::PE::FPO::entry_t; + using Mirror::Mirror; + + auto rva() const { + return get().rva; + } + auto proc_size() const { + return get().proc_size; + } + auto nb_locals() const { + return get().nb_locals; + } + auto parameters_size() const { + return get().parameters_size; + } + auto prolog_size() const { + return get().prolog_size; + } + auto nb_saved_regs() const { + return get().nb_saved_regs; + } + auto use_seh() const { + return get().use_seh; + } + auto use_bp() const { + return get().use_bp; + } + auto reserved() const { + return get().reserved; + } + auto get_type() const { + return as_u32(get().type); + } + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class PE_FPO : public PE_Debug { + public: + using lief_t = LIEF::PE::FPO; + PE_FPO(const lief_t& obj) : + PE_Debug(obj) {} + + class it_entries + : public Iterator { + public: + it_entries(const PE_FPO::lief_t& src) : + Iterator(std::move(src.entries())) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto entries() const { + return std::make_unique(impl()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_FPO_it_entries = PE_FPO::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PDBChecksum.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PDBChecksum.hpp new file mode 100644 index 0000000..fc4b046 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PDBChecksum.hpp @@ -0,0 +1,44 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/debug/PDBChecksum.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_PDBChecksum : public PE_Debug { + public: + using lief_t = LIEF::PE::PDBChecksum; + PE_PDBChecksum(const lief_t& obj) : + PE_Debug(obj) {} + + auto hash() const { + return make_span(impl().hash()); + } + + auto algo() const { + return to_int(impl().algorithm()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Pogo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Pogo.hpp new file mode 100644 index 0000000..807e1a7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Pogo.hpp @@ -0,0 +1,59 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/PE/debug/PogoEntry.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/PE/debug/Pogo.hpp" + +class PE_Pogo : public PE_Debug { + public: + using lief_t = LIEF::PE::Pogo; + class it_entries + : public Iterator { + public: + it_entries(const PE_Pogo::lief_t& src) : + Iterator(std::move(src.entries())) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + auto entries() const { + return std::make_unique(impl()); + } + + uint32_t pogo_signature() const { + return as_u32(impl().signature()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_Pogo_it_entries = PE_Pogo::it_entries; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PogoEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PogoEntry.hpp new file mode 100644 index 0000000..bc8a487 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/PogoEntry.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/debug/PogoEntry.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_PogoEntry : private Mirror { + public: + using lief_t = LIEF::PE::PogoEntry; + using Mirror::Mirror; + + uint32_t start_rva() const { + return get().start_rva(); + } + uint32_t size() const { + return get().size(); + } + auto name() const { + return to_unique_string(get().name()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Repro.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Repro.hpp new file mode 100644 index 0000000..3130a5a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/Repro.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/debug/Repro.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" +#include "LIEF/rust/Span.hpp" + + +class PE_Repro : public PE_Debug { + public: + using lief_t = LIEF::PE::Repro; + PE_Repro(const lief_t& obj) : + PE_Debug(obj) {} + + auto hash() const { + return make_span(impl().hash()); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/debug/VCFeature.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/VCFeature.hpp new file mode 100644 index 0000000..0b9174c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/debug/VCFeature.hpp @@ -0,0 +1,49 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/debug/VCFeature.hpp" +#include "LIEF/rust/PE/debug/Debug.hpp" + +class PE_VCFeature : public PE_Debug { + public: + using lief_t = LIEF::PE::VCFeature; + PE_VCFeature(const lief_t& obj) : + PE_Debug(obj) {} + + auto pre_vcpp() const { + return impl().pre_vcpp(); + } + auto c_cpp() const { + return impl().c_cpp(); + } + auto gs() const { + return impl().gs(); + } + auto sdl() const { + return impl().sdl(); + } + auto guards() const { + return impl().guards(); + } + + static auto classof(const PE_Debug& entry) { + return lief_t::classof(&entry.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/ContentInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/ContentInfo.hpp new file mode 100644 index 0000000..eec07b9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/ContentInfo.hpp @@ -0,0 +1,51 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ContentInfo_Content : public Mirror { + public: + using lief_t = LIEF::PE::ContentInfo::Content; + using Mirror::Mirror; + + auto content_type() const { + return to_unique_string(get().content_type()); + } +}; + +class PE_ContentInfo : private Mirror { + public: + using lief_t = LIEF::PE::ContentInfo; + using Mirror::Mirror; + + auto content_type() const { + return to_unique_string(get().content_type()); + } + + auto value() const { + return std::make_unique(get().value()); + } + + auto digest_algorithm() const { + return as_u32(get().digest_algorithm()); + } + + auto digest() const { + return make_unique_vector(get().digest()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/GenericContent.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/GenericContent.hpp new file mode 100644 index 0000000..9ec711f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/GenericContent.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/GenericContent.hpp" +#include "LIEF/rust/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_GenericContent : public PE_ContentInfo_Content { + public: + using lief_t = LIEF::PE::GenericContent; + + auto raw() const { + return make_span(impl().raw()); + } + + auto oid() const { + return to_unique_string(impl().oid()); + } + + static auto classof(const PE_ContentInfo_Content& info) { + return lief_t::classof(&info.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/PKCS9TSTInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/PKCS9TSTInfo.hpp new file mode 100644 index 0000000..b30fcc1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/PKCS9TSTInfo.hpp @@ -0,0 +1,31 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/PKCS9TSTInfo.hpp" +#include "LIEF/rust/PE/signature/ContentInfo.hpp" + +class PE_PKCS9TSTInfo : public PE_ContentInfo_Content { + public: + using lief_t = LIEF::PE::PKCS9TSTInfo; + + static auto classof(const PE_ContentInfo_Content& info) { + return lief_t::classof(&info.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/RsaInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/RsaInfo.hpp new file mode 100644 index 0000000..e725963 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/RsaInfo.hpp @@ -0,0 +1,51 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/signature/RsaInfo.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_RsaInfo : private Mirror { + public: + using lief_t = LIEF::PE::RsaInfo; + using Mirror::Mirror; + + uint32_t key_size() const { + return get().key_size(); + } + auto has_public_key() const { + return get().has_public_key(); + } + auto has_private_key() const { + return get().has_private_key(); + } + auto N() const { + return make_unique_vector(get().N()); + } + auto E() const { + return make_unique_vector(get().E()); + } + auto D() const { + return make_unique_vector(get().D()); + } + auto P() const { + return make_unique_vector(get().P()); + } + auto Q() const { + return make_unique_vector(get().Q()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/Signature.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/Signature.hpp new file mode 100644 index 0000000..6867b91 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/Signature.hpp @@ -0,0 +1,135 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/BinaryStream/SpanStream.hpp" +#include "LIEF/PE/signature/Signature.hpp" +#include "LIEF/PE/signature/SignatureParser.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/PE/signature/SignerInfo.hpp" +#include "LIEF/rust/PE/signature/x509.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_Signature : private Mirror { + friend class PE_Binary; + + public: + using lief_t = LIEF::PE::Signature; + using Mirror::Mirror; + + class it_certificates + : public Iterator { + public: + it_certificates(const PE_Signature::lief_t& src) : + Iterator(src.certificates()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_signers + : public Iterator { + public: + it_signers(const PE_Signature::lief_t& src) : + Iterator(src.signers()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + static auto parse(const std::string& path) { + std::unique_ptr sig; + if (auto res = LIEF::PE::SignatureParser::parse(path)) { + sig = std::make_unique(std::move(*res)); + } + return details::try_unique(std::move(sig)); + } + + static auto from_raw(uint8_t* buffer, size_t size) { + LIEF::SpanStream stream(buffer, size); + auto res = LIEF::PE::SignatureParser::parse(stream); + std::unique_ptr sig; + if (res) { + sig = std::make_unique(std::move(*res)); + } + return sig ? std::make_unique(std::move(sig)) : nullptr; + } + + + auto version() const { + return get().version(); + } + auto digest_algorithm() const { + return as_u32(get().digest_algorithm()); + } + auto raw_der() const { + return make_span(get().raw_der()); + } + + auto content_info() const { + return std::make_unique(get().content_info()); + } + + auto certificates() const { + return std::make_unique(get()); + } + + auto signers() const { + return std::make_unique(get()); + } + + auto find_crt_by_serial(const uint8_t* serial, size_t size) const { + return details::try_unique( + get().find_crt(std::vector{serial, serial + size}) + ); + } + + auto find_crt_by_subject(const std::string& subject) const { + return details::try_unique(get().find_crt_subject(subject)); + } + + auto find_crt_by_subject_and_serial(const std::string& subject, + const uint8_t* serial, size_t size) const { + std::vector serial_vec{serial, serial + size}; + return details::try_unique(get().find_crt_subject(subject, + serial_vec)); + } + + auto find_crt_by_issuer(const std::string& issuer) const { + return details::try_unique(get().find_crt_issuer(issuer)); + } + + auto find_crt_by_issuer_and_serial(const std::string& issuer, + const uint8_t* serial, size_t size) const { + std::vector serial_vec{serial, serial + size}; + return details::try_unique(get().find_crt_issuer(issuer, serial_vec)); + } + + auto check(uint32_t flags) const { + return as_u32(get().check(LIEF::PE::Signature::VERIFICATION_CHECKS(flags))); + } +}; + +using PE_Signature_it_certificates = PE_Signature::it_certificates; +using PE_Signature_it_signers = PE_Signature::it_signers; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SignerInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SignerInfo.hpp new file mode 100644 index 0000000..8adfa41 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SignerInfo.hpp @@ -0,0 +1,115 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/signature/SignerInfo.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/PE/signature/x509.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_SignerInfo : private Mirror { + public: + using lief_t = LIEF::PE::SignerInfo; + using Mirror::Mirror; + + class it_authenticated_attributes + : public Iterator { + public: + it_authenticated_attributes(const PE_SignerInfo::lief_t& src) : + Iterator(src.authenticated_attributes()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_unauthenticated_attributes + : public Iterator { + public: + it_unauthenticated_attributes(const PE_SignerInfo::lief_t& src) : + Iterator(src.unauthenticated_attributes()) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + uint32_t version() const { + return get().version(); + } + auto issuer() const { + return to_unique_string(get().issuer()); + } + auto digest_algorithm() const { + return as_u32(get().digest_algorithm()); + } + auto encryption_algorithm() const { + return as_u32(get().encryption_algorithm()); + } + Span serial_number() const { + return make_span(get().serial_number()); + } + + auto encrypted_digest() const { + return make_unique_vector(get().encrypted_digest()); + } + + auto cert() const { + return details::try_unique(get().cert()); + } + + auto authenticated_attributes() const { + return std::make_unique(get()); + } + + auto unauthenticated_attributes() const { + return std::make_unique(get()); + } + + auto raw_auth_data() const { + return make_span(get().raw_auth_data()); + } + + auto get_attribute(uint32_t type) const { + return details::try_unique( + get().get_attribute(LIEF::PE::Attribute::TYPE(type)) + ); + } + + auto get_auth_attribute(uint32_t type) const { + return details::try_unique( + get().get_auth_attribute(LIEF::PE::Attribute::TYPE(type)) + ); + } + + auto get_unauth_attribute(uint32_t type) const { + return details::try_unique( + get().get_unauth_attribute(LIEF::PE::Attribute::TYPE(type)) + ); + } +}; + +using PE_SignerInfo_it_authenticated_attributes = + PE_SignerInfo::it_authenticated_attributes; +using PE_SignerInfo_it_unauthenticated_attributes = + PE_SignerInfo::it_unauthenticated_attributes; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SpcIndirectData.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SpcIndirectData.hpp new file mode 100644 index 0000000..b5f6563 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/SpcIndirectData.hpp @@ -0,0 +1,49 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/SpcIndirectData.hpp" +#include "LIEF/rust/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_SpcIndirectData : public PE_ContentInfo_Content { + public: + using lief_t = LIEF::PE::SpcIndirectData; + + auto digest_algorithm() const { + return as_u32(impl().digest_algorithm()); + } + + auto digest() const { + return make_span(impl().digest()); + } + + auto file() const { + return to_unique_string(impl().file()); + } + + auto url() const { + return to_unique_string(impl().url()); + } + + static auto classof(const PE_ContentInfo_Content& info) { + return lief_t::classof(&info.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/Attribute.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/Attribute.hpp new file mode 100644 index 0000000..cef591f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/Attribute.hpp @@ -0,0 +1,18 @@ +#pragma once +#include "LIEF/PE/signature/Attribute.hpp" +#include "LIEF/rust/Mirror.hpp" + +class PE_Attribute : public Mirror { + public: + friend class PE_ContentType; + friend class PE_GenericType; + friend class PE_MsSpcNestedSignature; + friend class PE_MsSpcStatementType; + friend class PE_PKCS9AtSequenceNumber; + friend class PE_PKCS9CounterSignature; + friend class PE_PKCS9MessageDigest; + friend class PE_PKCS9SigningTime; + friend class PE_SpcSpOpusInfo; + using lief_t = LIEF::PE::Attribute; + using Mirror::Mirror; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/ContentType.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/ContentType.hpp new file mode 100644 index 0000000..fc452a9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/ContentType.hpp @@ -0,0 +1,24 @@ +#pragma once +#include "LIEF/PE/signature/attributes/ContentType.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_ContentType : public PE_Attribute { + public: + using lief_t = LIEF::PE::ContentType; + PE_ContentType(const lief_t& base) : + PE_Attribute(base) {} + + auto oid() const { + return to_unique_string(impl().oid()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/GenericType.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/GenericType.hpp new file mode 100644 index 0000000..a1ca111 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/GenericType.hpp @@ -0,0 +1,28 @@ +#pragma once +#include "Attribute.hpp" +#include "LIEF/PE/signature/attributes/GenericType.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_GenericType : public PE_Attribute { + public: + using lief_t = LIEF::PE::GenericType; + PE_GenericType(const lief_t& base) : + PE_Attribute(base) {} + + auto oid() const { + return to_unique_string(impl().oid()); + } + auto raw_content() const { + return make_span(impl().raw_content()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsCounterSign.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsCounterSign.hpp new file mode 100644 index 0000000..bc9f834 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsCounterSign.hpp @@ -0,0 +1,84 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/attributes/MsCounterSign.hpp" +#include "LIEF/rust/PE/signature/ContentInfo.hpp" +#include "LIEF/rust/PE/signature/SignerInfo.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/PE/signature/x509.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_MsCounterSign : public PE_Attribute { + public: + using lief_t = LIEF::PE::MsCounterSign; + PE_MsCounterSign(const lief_t& base) : + PE_Attribute(base) {} + + class it_certificates : public Iterator { + public: + it_certificates(const PE_MsCounterSign::lief_t& src) : + Iterator(std::move(src.certificates())) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + class it_signers : public Iterator { + public: + it_signers(const PE_MsCounterSign::lief_t& src) : + Iterator(std::move(src.signers())) {} + auto next() { + return Iterator::next(); + } + auto size() const { + return Iterator::size(); + } + }; + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + auto version() const { + return impl().version(); + } + auto digest_algorithm() const { + return as_u32(impl().digest_algorithm()); + } + + auto content_info() const { + return std::make_unique(impl().content_info()); + } + + auto certificates() const { + return std::make_unique(impl()); + } + + auto signers() const { + return std::make_unique(impl()); + } + + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using PE_MsCounterSign_it_certificates = PE_MsCounterSign::it_certificates; +using PE_MsCounterSign_it_signers = PE_MsCounterSign::it_signers; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsManifestBinaryID.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsManifestBinaryID.hpp new file mode 100644 index 0000000..f517045 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsManifestBinaryID.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/attributes/MsManifestBinaryID.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_MsManifestBinaryID : public PE_Attribute { + public: + using lief_t = LIEF::PE::MsManifestBinaryID; + PE_MsManifestBinaryID(const lief_t& base) : + PE_Attribute(base) {} + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + auto manifest_id() const { + return to_unique_string(impl().manifest_id()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcNestedSignature.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcNestedSignature.hpp new file mode 100644 index 0000000..c1b8b65 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcNestedSignature.hpp @@ -0,0 +1,24 @@ +#pragma once +#include "LIEF/PE/signature/attributes/MsSpcNestedSignature.hpp" +#include "LIEF/rust/PE/signature/Signature.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" + +class PE_MsSpcNestedSignature : public PE_Attribute { + public: + using lief_t = LIEF::PE::MsSpcNestedSignature; + PE_MsSpcNestedSignature(const lief_t& base) : + PE_Attribute(base) {} + + auto sig() const { + return std::make_unique(impl().sig()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcStatementType.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcStatementType.hpp new file mode 100644 index 0000000..c7160dd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/MsSpcStatementType.hpp @@ -0,0 +1,25 @@ +#pragma once +#include "LIEF/PE/signature/attributes/MsSpcStatementType.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_MsSpcStatementType : public PE_Attribute { + using lief_t = LIEF::PE::MsSpcStatementType; + + public: + PE_MsSpcStatementType(const lief_t& base) : + PE_Attribute(base) {} + + auto oid() const { + return to_unique_string(impl().oid()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9AtSequenceNumber.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9AtSequenceNumber.hpp new file mode 100644 index 0000000..f8bd861 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9AtSequenceNumber.hpp @@ -0,0 +1,23 @@ +#pragma once +#include "LIEF/PE/signature/attributes/PKCS9AtSequenceNumber.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" + +class PE_PKCS9AtSequenceNumber : public PE_Attribute { + public: + using lief_t = LIEF::PE::PKCS9AtSequenceNumber; + PE_PKCS9AtSequenceNumber(const lief_t& base) : + PE_Attribute(base) {} + + uint32_t number() const { + return impl().number(); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9CounterSignature.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9CounterSignature.hpp new file mode 100644 index 0000000..6f03b73 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9CounterSignature.hpp @@ -0,0 +1,24 @@ +#pragma once +#include "LIEF/PE/signature/attributes/PKCS9CounterSignature.hpp" +#include "LIEF/rust/PE/signature/SignerInfo.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" + +class PE_PKCS9CounterSignature : public PE_Attribute { + public: + using lief_t = LIEF::PE::PKCS9CounterSignature; + PE_PKCS9CounterSignature(lief_t& base) : + PE_Attribute(base) {} + + auto signer() const { + return std::make_unique(impl().signer()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9MessageDigest.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9MessageDigest.hpp new file mode 100644 index 0000000..57d5faf --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9MessageDigest.hpp @@ -0,0 +1,25 @@ +#pragma once +#include "LIEF/PE/signature/attributes/PKCS9MessageDigest.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/Span.hpp" + +class PE_PKCS9MessageDigest : public PE_Attribute { + using lief_t = LIEF::PE::PKCS9MessageDigest; + + public: + PE_PKCS9MessageDigest(const lief_t& base) : + PE_Attribute(base) {} + + Span digest() const { + return make_span(impl().digest()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9SigningTime.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9SigningTime.hpp new file mode 100644 index 0000000..ef471fd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/PKCS9SigningTime.hpp @@ -0,0 +1,25 @@ +#pragma once +#include "LIEF/PE/signature/attributes/PKCS9SigningTime.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_PKCS9SigningTime : public PE_Attribute { + using lief_t = LIEF::PE::PKCS9SigningTime; + + public: + PE_PKCS9SigningTime(const lief_t& base) : + PE_Attribute(base) {} + + auto time() const { + return make_unique_vector(details::make_vector(impl().time())); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SigningCertificateV2.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SigningCertificateV2.hpp new file mode 100644 index 0000000..b06a5f2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SigningCertificateV2.hpp @@ -0,0 +1,33 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/attributes/SigningCertificateV2.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" + +class PE_SigningCertificateV2 : public PE_Attribute { + public: + using lief_t = LIEF::PE::SigningCertificateV2; + PE_SigningCertificateV2(const lief_t& base) : + PE_Attribute(base) {} + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp new file mode 100644 index 0000000..9029767 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/attributes/SpcRelaxedPeMarkerCheck.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" + +class PE_SpcRelaxedPeMarkerCheck : public PE_Attribute { + public: + using lief_t = LIEF::PE::SpcRelaxedPeMarkerCheck; + PE_SpcRelaxedPeMarkerCheck(const lief_t& base) : + PE_Attribute(base) {} + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + auto value() const { + return impl().value(); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcSpOpusInfo.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcSpOpusInfo.hpp new file mode 100644 index 0000000..a453bf6 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/attributes/SpcSpOpusInfo.hpp @@ -0,0 +1,27 @@ +#pragma once +#include "LIEF/PE/signature/attributes/SpcSpOpusInfo.hpp" +#include "LIEF/rust/PE/signature/attributes/Attribute.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_SpcSpOpusInfo : public PE_Attribute { + public: + using lief_t = LIEF::PE::SpcSpOpusInfo; + PE_SpcSpOpusInfo(const lief_t& base) : + PE_Attribute(base) {} + + auto program_name() const { + return to_unique_string(impl().program_name()); + } + auto more_info() const { + return to_unique_string(impl().more_info()); + } + + static auto classof(const PE_Attribute& attr) { + return lief_t::classof(&attr.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/signature/x509.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/x509.hpp new file mode 100644 index 0000000..b4368a9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/signature/x509.hpp @@ -0,0 +1,96 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/PE/signature/x509.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/PE/signature/RsaInfo.hpp" +#include "LIEF/rust/helpers.hpp" + +class PE_x509 : private Mirror { + public: + using lief_t = LIEF::PE::x509; + using Mirror::Mirror; + + uint32_t version() const { + return get().version(); + } + auto serial_number() const { + return make_unique_vector(get().serial_number()); + } + + auto signature_algorithm() const { + return to_unique_string(get().signature_algorithm()); + } + auto valid_from() const { + return make_unique_vector(details::make_vector(get().valid_from())); + } + + auto valid_to() const { + return make_unique_vector(details::make_vector(get().valid_to())); + } + + auto issuer() const { + return to_unique_string(get().issuer()); + } + auto subject() const { + return to_unique_string(get().subject()); + } + auto raw() const { + return make_unique_vector(get().raw()); + } + + auto key_type() const { + return as_u32(get().key_type()); + } + auto is_ca() const { + return get().is_ca(); + } + auto signature() const { + return make_unique_vector(get().signature()); + } + + auto rsa_info() const { + return std::make_unique(get().rsa_info()); + } + + auto check_signature(const uint8_t* hash, size_t hsize, const uint8_t* signature, + size_t sigsiz, uint32_t algo) const { + return as_u32(get().check_signature({hash, hash + hsize}, + {signature, signature + sigsiz}, + LIEF::PE::ALGORITHMS(algo))); + } + + auto verify(const PE_x509& ca) const { + return as_u32(get().verify(ca.get())); + } + + auto key_usage() const { + auto result = make_unique_vector(); + for (LIEF::PE::x509::KEY_USAGE ku : get().key_usage()) { + result->push_back(to_int(ku)); + } + return result; + } + auto ext_key_usage() const { + auto v = get().ext_key_usage(); + return make_unique_vector(v.begin(), v.end()); + } + auto certificate_policies() const { + auto v = get().certificate_policies(); + return make_unique_vector(v.begin(), v.end()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/PE/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/PE/utils.hpp new file mode 100644 index 0000000..6b2f74f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/PE/utils.hpp @@ -0,0 +1,62 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/PE/signature/OIDToString.hpp" +#include "LIEF/PE/utils.hpp" +#include "LIEF/rust/PE/Binary.hpp" +#include "LIEF/rust/PE/Import.hpp" +#include "LIEF/rust/helpers.hpp" +#include + +class PE_Utils { + public: + static auto is_pe(const std::string& file) { + return LIEF::PE::is_pe(file); + } + + static auto check_layout(const PE_Binary& bin, std::string* error) { + return LIEF::PE::check_layout(static_cast(bin.get()), + error); + } + + static uint32_t get_type(const std::string& file) { + if (auto res = LIEF::PE::get_type(file)) { + return static_cast(*res); + } + return 0; + } + + static auto get_imphash(const PE_Binary& bin, uint32_t mode) { + return to_unique_string( + LIEF::PE::get_imphash(static_cast(bin.get()), + LIEF::PE::IMPHASH_MODE(mode)) + ); + } + + static auto oid_to_string(const std::string& oid) { + const char* result = LIEF::PE::oid_to_string(oid); + return to_unique_string(result ? std::string(result) : std::string()); + } + + static std::unique_ptr resolve_ordinals(const PE_Import& imp, + bool strict, bool use_std) { + if (auto res = LIEF::PE::resolve_ordinals(imp.get(), strict, use_std)) { + return std::make_unique( + std::make_unique(std::move(*res)) + ); + } + return nullptr; + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/Span.hpp b/vendor/lief/api/rust/include/LIEF/rust/Span.hpp new file mode 100644 index 0000000..35d59ac --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Span.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/span.hpp" +#include + +class Span { + public: + uint8_t* ptr = nullptr; + uint64_t size = 0; +}; + +inline Span make_span(LIEF::span content) { + return Span{content.data(), content.size()}; +} + +inline Span make_span(LIEF::span content) { + return Span{const_cast(content.data()), content.size()}; +} + + +inline Span make_span(LIEF::span content) { + return Span{reinterpret_cast(content.data()), content.size()}; +} + +inline Span make_span(LIEF::span content) { + return Span{reinterpret_cast(const_cast(content.data())), + content.size()}; +} + +inline Span make_span(const std::vector& content) { + return Span{const_cast(content.data()), content.size()}; +} + +template +inline Span make_span(const std::array& array) { + return Span{const_cast(array.data()), N}; +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/Stream.hpp b/vendor/lief/api/rust/include/LIEF/rust/Stream.hpp new file mode 100644 index 0000000..b32dffc --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/Stream.hpp @@ -0,0 +1,92 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/BinaryStream/VectorStream.hpp" + +#include "LIEF/ELF/Parser.hpp" +#include "LIEF/ELF/utils.hpp" +#include "LIEF/rust/ELF/Binary.hpp" + +#include "LIEF/PE/Parser.hpp" +#include "LIEF/PE/utils.hpp" +#include "LIEF/rust/PE/Binary.hpp" + +#include "LIEF/MachO/Parser.hpp" +#include "LIEF/MachO/utils.hpp" +#include "LIEF/rust/MachO/FatBinary.hpp" + +#include "LIEF/COFF/Parser.hpp" +#include "LIEF/COFF/utils.hpp" +#include "LIEF/rust/COFF/Binary.hpp" + +#include "LIEF/visibility.h" + +struct IRustStream; + +class RustStream { + public: + RustStream() = delete; + RustStream(std::unique_ptr stream) : + stream_(std::move(stream)) {} + LIEF_API + static std::unique_ptr from_rust(uint8_t* buffer, size_t size); + + auto is_elf() const { + return LIEF::ELF::is_elf(*stream_); + } + + auto is_pe() const { + return LIEF::PE::is_pe(*stream_); + } + + auto is_macho() const { + return LIEF::MachO::is_macho(*stream_); + } + + auto is_coff() const { + return LIEF::COFF::is_coff(*stream_); + } + + auto as_elf() { + return details::try_unique( + LIEF::ELF::Parser::parse(std::move(stream_)) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto as_macho() { + return details::try_unique( + LIEF::MachO::Parser::parse(std::move(stream_)) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto as_pe() { + return details::try_unique( + LIEF::PE::Parser::parse(std::move(stream_)) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto as_coff() { + return details::try_unique( + LIEF::COFF::Parser::parse(std::move(stream_)) + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + ~RustStream() = default; + + private: + std::unique_ptr stream_; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/AssemblerConfig.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/AssemblerConfig.hpp new file mode 100644 index 0000000..8a94f5d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/AssemblerConfig.hpp @@ -0,0 +1,9 @@ +#pragma once +#include "LIEF/asm/AssemblerConfig.hpp" +#include "LIEF/visibility.h" +#include + +struct AssemblerConfig_r; + +LIEF_API std::unique_ptr + from_rust(const AssemblerConfig_r& config); diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/Engine.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/Engine.hpp new file mode 100644 index 0000000..12729cd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/Engine.hpp @@ -0,0 +1,25 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/Engine.hpp" + +#include "LIEF/rust/Mirror.hpp" + + +class asm_Engine : private Mirror { + public: + using lief_t = LIEF::assembly::Engine; + using Mirror::Mirror; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/Instruction.hpp new file mode 100644 index 0000000..4c2d136 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/Instruction.hpp @@ -0,0 +1,108 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/Instruction.hpp" +#include "LIEF/rust/Span.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/rust/Mirror.hpp" + +class asm_Instruction : public Mirror { + public: + using lief_t = LIEF::assembly::Instruction; + using Mirror::Mirror; + + auto address() const { + return get().address(); + } + + uint64_t size() const { + return get().size(); + } + + auto raw() const { + return make_span(get().raw()); + } + + auto mnemonic() const { + return to_unique_string(get().mnemonic()); + } + + auto to_string() const { + return to_unique_string(get().to_string(/*with_address=*/true)); + } + auto to_string_no_address() const { + return to_unique_string(get().to_string(/*with_address=*/false)); + } + + auto is_call() const { + return get().is_call(); + } + + auto is_terminator() const { + return get().is_terminator(); + } + + auto is_branch() const { + return get().is_branch(); + } + + auto is_syscall() const { + return get().is_syscall(); + } + auto is_memory_access() const { + return get().is_memory_access(); + } + auto is_move_reg() const { + return get().is_move_reg(); + } + auto is_add() const { + return get().is_add(); + } + auto is_trap() const { + return get().is_trap(); + } + auto is_barrier() const { + return get().is_barrier(); + } + auto is_return() const { + return get().is_return(); + } + auto is_indirect_branch() const { + return get().is_indirect_branch(); + } + auto is_conditional_branch() const { + return get().is_conditional_branch(); + } + auto is_unconditional_branch() const { + return get().is_unconditional_branch(); + } + auto is_compare() const { + return get().is_compare(); + } + auto is_move_immediate() const { + return get().is_move_immediate(); + } + auto is_bitcast() const { + return get().is_bitcast(); + } + uint64_t memory_access() const { + return to_int(get().memory_access()); + } + uint64_t branch_target(uint32_t& err) const { + return details::make_error(get().branch_target(), err); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Instruction.hpp new file mode 100644 index 0000000..d76e6b8 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Instruction.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/aarch64/Operand.hpp" + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_aarch64_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::aarch64::Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_aarch64_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + auto operands() const { + return std::make_unique(impl()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_aarch64_Instruction_it_operands = asm_aarch64_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Operand.hpp new file mode 100644 index 0000000..3e33be3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/aarch64/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_aarch64_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::aarch64::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands.hpp new file mode 100644 index 0000000..480c42b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands.hpp @@ -0,0 +1,6 @@ +#pragma once +#include "LIEF/rust/asm/aarch64/Operand.hpp" +#include "LIEF/rust/asm/aarch64/operands/Immediate.hpp" +#include "LIEF/rust/asm/aarch64/operands/Memory.hpp" +#include "LIEF/rust/asm/aarch64/operands/PCRelative.hpp" +#include "LIEF/rust/asm/aarch64/operands/Register.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Immediate.hpp new file mode 100644 index 0000000..1c4cc36 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Immediate.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/aarch64/Operand.hpp" + +class asm_aarch64_operands_Immediate : public asm_aarch64_Operand { + public: + using lief_t = LIEF::assembly::aarch64::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_aarch64_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Memory.hpp new file mode 100644 index 0000000..e50d1e3 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Memory.hpp @@ -0,0 +1,65 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/aarch64/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_aarch64_operands_Memory_offset_t { + public: + uint64_t value = 0; + uint32_t enum_type = 0; +}; + +class asm_aarch64_operands_Memory_shift_info_t { + public: + int32_t enum_type = 0; + int8_t value = 0; +}; + +class asm_aarch64_operands_Memory : public asm_aarch64_Operand { + public: + using lief_t = LIEF::assembly::aarch64::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + + asm_aarch64_operands_Memory_offset_t offset() const { + const lief_t::offset_t off = impl().offset(); + return { + /*.value = */ (uint64_t)off.reg, + /*.type = */ (uint32_t)to_int(off.type), + }; + } + + asm_aarch64_operands_Memory_shift_info_t shift() const { + const lief_t::shift_info_t info = impl().shift(); + return { + /*.type = */ (int32_t)info.type, + /*.value = */ info.value, + }; + } + + static auto classof(const asm_aarch64_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/PCRelative.hpp new file mode 100644 index 0000000..88fbb07 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/PCRelative.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/aarch64/Operand.hpp" + +class asm_aarch64_operands_PCRelative : public asm_aarch64_Operand { + public: + using lief_t = LIEF::assembly::aarch64::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_aarch64_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Register.hpp new file mode 100644 index 0000000..57ecce5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/aarch64/operands/Register.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/aarch64/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_aarch64_operands_Register_reg_t { + public: + uint64_t reg = 0; + uint32_t enum_type = 0; +}; + +class asm_aarch64_operands_Register : public asm_aarch64_Operand { + public: + using lief_t = LIEF::assembly::aarch64::operands::Register; + + asm_aarch64_operands_Register_reg_t value() const { + lief_t::reg_t info = impl().value(); + return { + /*.reg =*/(uint64_t)to_int(info.reg), + /*.enum_type =*/(uint32_t)to_int(info.type), + }; + } + + static auto classof(const asm_aarch64_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/arm/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/arm/Instruction.hpp new file mode 100644 index 0000000..f14c9d5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/arm/Instruction.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_arm_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::arm::Instruction; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Instruction.hpp new file mode 100644 index 0000000..796033f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Instruction.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/ebpf/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::ebpf::Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_ebpf_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + auto operands() const { + return std::make_unique(impl()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_ebpf_Instruction_it_operands = asm_ebpf_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Operand.hpp new file mode 100644 index 0000000..462e3d2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/ebpf/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::ebpf::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Immediate.hpp new file mode 100644 index 0000000..9e5ab34 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Immediate.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/ebpf/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_operands_Immediate : public asm_ebpf_Operand { + public: + using lief_t = LIEF::assembly::ebpf::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_ebpf_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Memory.hpp new file mode 100644 index 0000000..5b6e226 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Memory.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/ebpf/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_operands_Memory : public asm_ebpf_Operand { + public: + using lief_t = LIEF::assembly::ebpf::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + + auto displacement() const { + return impl().displacement(); + } + + static auto classof(const asm_ebpf_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/PCRelative.hpp new file mode 100644 index 0000000..d47af37 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/PCRelative.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/ebpf/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_operands_PCRelative : public asm_ebpf_Operand { + public: + using lief_t = LIEF::assembly::ebpf::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_ebpf_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Register.hpp new file mode 100644 index 0000000..f18ae3b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/ebpf/operands/Register.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/ebpf/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_ebpf_operands_Register : public asm_ebpf_Operand { + public: + using lief_t = LIEF::assembly::ebpf::operands::Register; + + uint64_t value() const { + return to_int(impl().value()); + } + + static auto classof(const asm_ebpf_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Instruction.hpp new file mode 100644 index 0000000..a15ba9f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Instruction.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/mips/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::mips::Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_mips_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + auto operands() const { + return std::make_unique(impl()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_mips_Instruction_it_operands = asm_mips_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Operand.hpp new file mode 100644 index 0000000..8a7db49 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/mips/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::mips::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Immediate.hpp new file mode 100644 index 0000000..5ec624a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Immediate.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/mips/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_operands_Immediate : public asm_mips_Operand { + public: + using lief_t = LIEF::assembly::mips::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_mips_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Memory.hpp new file mode 100644 index 0000000..bb40130 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Memory.hpp @@ -0,0 +1,54 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/mips/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_operands_Memory_offset_t { + public: + uint64_t value = 0; + uint32_t enum_type = 0; +}; + +class asm_mips_operands_Memory : public asm_mips_Operand { + public: + using lief_t = LIEF::assembly::mips::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + + asm_mips_operands_Memory_offset_t offset() const { + const lief_t::offset_t off = impl().offset(); + uint64_t value = off.type == lief_t::offset_t::TYPE::REG ? + (uint64_t)to_int(off.reg) : + (uint64_t)off.displacement; + return { + /*.value = */ value, + /*.enum_type = */ (uint32_t)to_int(off.type), + }; + } + + static auto classof(const asm_mips_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/PCRelative.hpp new file mode 100644 index 0000000..e9cada2 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/PCRelative.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/mips/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_operands_PCRelative : public asm_mips_Operand { + public: + using lief_t = LIEF::assembly::mips::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_mips_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Register.hpp new file mode 100644 index 0000000..13b8244 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/mips/operands/Register.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/mips/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_mips_operands_Register : public asm_mips_Operand { + public: + using lief_t = LIEF::assembly::mips::operands::Register; + + uint64_t value() const { + return to_int(impl().value()); + } + + static auto classof(const asm_mips_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Instruction.hpp new file mode 100644 index 0000000..96cc9c1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Instruction.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/powerpc/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::powerpc::Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_powerpc_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + auto operands() const { + return std::make_unique(impl()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_powerpc_Instruction_it_operands = asm_powerpc_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Operand.hpp new file mode 100644 index 0000000..a019d94 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/powerpc/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::powerpc::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Immediate.hpp new file mode 100644 index 0000000..4712f99 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Immediate.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/powerpc/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_operands_Immediate : public asm_powerpc_Operand { + public: + using lief_t = LIEF::assembly::powerpc::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_powerpc_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Memory.hpp new file mode 100644 index 0000000..aa3c8ae --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Memory.hpp @@ -0,0 +1,54 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/powerpc/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_operands_Memory_offset_t { + public: + uint64_t value = 0; + uint32_t enum_type = 0; +}; + +class asm_powerpc_operands_Memory : public asm_powerpc_Operand { + public: + using lief_t = LIEF::assembly::powerpc::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + + asm_powerpc_operands_Memory_offset_t offset() const { + const lief_t::offset_t off = impl().offset(); + uint64_t value = off.type == lief_t::offset_t::TYPE::REG ? + (uint64_t)to_int(off.reg) : + (uint64_t)off.displacement; + return { + /*.value = */ value, + /*.enum_type = */ (uint32_t)to_int(off.type), + }; + } + + static auto classof(const asm_powerpc_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/PCRelative.hpp new file mode 100644 index 0000000..163d001 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/PCRelative.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/powerpc/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_operands_PCRelative : public asm_powerpc_Operand { + public: + using lief_t = LIEF::assembly::powerpc::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_powerpc_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Register.hpp new file mode 100644 index 0000000..72084ef --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/powerpc/operands/Register.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/powerpc/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_powerpc_operands_Register : public asm_powerpc_Operand { + public: + using lief_t = LIEF::assembly::powerpc::operands::Register; + + uint64_t value() const { + return to_int(impl().value()); + } + + static auto classof(const asm_powerpc_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Instruction.hpp new file mode 100644 index 0000000..1227034 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Instruction.hpp @@ -0,0 +1,60 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/riscv/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::riscv::Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_riscv_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + auto operands() const { + return std::make_unique(impl()); + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_riscv_Instruction_it_operands = asm_riscv_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Operand.hpp new file mode 100644 index 0000000..17b004a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/riscv/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::riscv::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Immediate.hpp new file mode 100644 index 0000000..eb2b613 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Immediate.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/riscv/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_operands_Immediate : public asm_riscv_Operand { + public: + using lief_t = LIEF::assembly::riscv::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_riscv_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Memory.hpp new file mode 100644 index 0000000..0b40b30 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Memory.hpp @@ -0,0 +1,41 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/riscv/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_operands_Memory : public asm_riscv_Operand { + public: + using lief_t = LIEF::assembly::riscv::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + + auto displacement() const { + return impl().displacement(); + } + + static auto classof(const asm_riscv_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/PCRelative.hpp new file mode 100644 index 0000000..e4b05e4 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/PCRelative.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/riscv/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_operands_PCRelative : public asm_riscv_Operand { + public: + using lief_t = LIEF::assembly::riscv::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_riscv_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Register.hpp new file mode 100644 index 0000000..9741626 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/riscv/operands/Register.hpp @@ -0,0 +1,47 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/riscv/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_riscv_operands_Register_reg_t { + public: + uint64_t reg = 0; + uint32_t enum_type = 0; +}; + +class asm_riscv_operands_Register : public asm_riscv_Operand { + public: + using lief_t = LIEF::assembly::riscv::operands::Register; + + asm_riscv_operands_Register_reg_t value() const { + lief_t::reg_t info = impl().value(); + return { + /*.reg =*/(uint64_t)to_int(info.reg), + /*.enum_type =*/(uint32_t)to_int(info.type), + }; + } + + static auto classof(const asm_riscv_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Instruction.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Instruction.hpp new file mode 100644 index 0000000..d4bfaab --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Instruction.hpp @@ -0,0 +1,85 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" +#include "LIEF/rust/asm/x86/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_x86_Instruction : public asm_Instruction { + public: + using lief_t = LIEF::assembly::x86::Instruction; + using asm_Instruction::asm_Instruction; + + class it_operands + : public ForwardIterator { + public: + it_operands(const asm_x86_Instruction::lief_t& src) : + ForwardIterator(src.operands()) {} + + auto next() { + return ForwardIterator::next(); + } + auto size() const { + return ForwardIterator::size(); + } + }; + + uint64_t opcode() const { + return to_int(impl().opcode()); + } + + auto operands() const { + return std::make_unique(impl()); + } + + auto has_lock_prefix() const { + return impl().has_lock_prefix(); + } + + auto is_lockable() const { + return impl().is_lockable(); + } + + auto is_atomic() const { + return impl().is_atomic(); + } + + auto lock() const { + return details::try_unique( + impl().lock() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + auto unlock() const { + return details::try_unique( + impl().unlock() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks) + } + + static auto classof(const asm_Instruction& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +using asm_x86_Instruction_it_operands = asm_x86_Instruction::it_operands; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Operand.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Operand.hpp new file mode 100644 index 0000000..22608d0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/Operand.hpp @@ -0,0 +1,29 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/asm/x86/Operand.hpp" + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_x86_Operand : public Mirror { + public: + using lief_t = LIEF::assembly::x86::Operand; + using Mirror::Mirror; + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands.hpp new file mode 100644 index 0000000..f2b14c9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands.hpp @@ -0,0 +1,6 @@ +#pragma once +#include "LIEF/rust/asm/x86/Operand.hpp" +#include "LIEF/rust/asm/x86/operands/Immediate.hpp" +#include "LIEF/rust/asm/x86/operands/Memory.hpp" +#include "LIEF/rust/asm/x86/operands/PCRelative.hpp" +#include "LIEF/rust/asm/x86/operands/Register.hpp" diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Immediate.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Immediate.hpp new file mode 100644 index 0000000..8e050bc --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Immediate.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/x86/Operand.hpp" + +class asm_x86_operands_Immediate : public asm_x86_Operand { + public: + using lief_t = LIEF::assembly::x86::operands::Immediate; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_x86_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Memory.hpp new file mode 100644 index 0000000..dfaab42 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Memory.hpp @@ -0,0 +1,50 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/x86/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_x86_operands_Memory : public asm_x86_Operand { + public: + using lief_t = LIEF::assembly::x86::operands::Memory; + + uint64_t base() const { + return to_int(impl().base()); + } + uint64_t scaled_register() const { + return to_int(impl().scaled_register()); + } + uint64_t segment_register() const { + return to_int(impl().segment_register()); + } + + auto scale() const { + return impl().scale(); + } + auto displacement() const { + return impl().displacement(); + } + + static auto classof(const asm_x86_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/PCRelative.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/PCRelative.hpp new file mode 100644 index 0000000..77dee89 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/PCRelative.hpp @@ -0,0 +1,36 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/x86/Operand.hpp" + +class asm_x86_operands_PCRelative : public asm_x86_Operand { + public: + using lief_t = LIEF::assembly::x86::operands::PCRelative; + + auto value() const { + return impl().value(); + } + + static auto classof(const asm_x86_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Register.hpp b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Register.hpp new file mode 100644 index 0000000..61f767c --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/asm/x86/operands/Register.hpp @@ -0,0 +1,37 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include + +#include "LIEF/rust/asm/x86/Operand.hpp" +#include "LIEF/rust/helpers.hpp" + +class asm_x86_operands_Register : public asm_x86_Operand { + public: + using lief_t = LIEF::assembly::x86::operands::Register; + + uint64_t value() const { + return to_int(impl().value()); + } + + static auto classof(const asm_x86_Operand& inst) { + return lief_t::classof(&inst.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/debug_location.hpp b/vendor/lief/api/rust/include/LIEF/rust/debug_location.hpp new file mode 100644 index 0000000..f24dcdd --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/debug_location.hpp @@ -0,0 +1,41 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/debug_loc.hpp" +#include + +class DebugLocation { + public: + DebugLocation(std::string file, uint64_t line) : + line_(line), + file_(std::move(file)) {} + + auto file() const { + return std::make_unique(file_); + } + auto line() const { + return line_; + } + + private: + uint64_t line_ = 0; + std::string file_; +}; + +namespace details { +inline auto make_location(const LIEF::debug_location_t& loc) { + return std::make_unique(loc.file, loc.line); +} +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/error.hpp b/vendor/lief/api/rust/include/LIEF/rust/error.hpp new file mode 100644 index 0000000..4b70751 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/error.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/errors.hpp" +namespace details { + +template +inline auto make_error(LIEF::result result, uint32_t& err) { + if (result) { + err = 0; + return std::move(*result); + } + err = static_cast(LIEF::get_error(result)); + return T{}; +} + +inline bool make_ok_error(LIEF::ok_error_t ok_err, uint32_t& err) { + if (ok_err) { + err = 0; + return true; + } + err = static_cast(LIEF::get_error(ok_err)); + return false; +} + +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/helpers.hpp b/vendor/lief/api/rust/include/LIEF/rust/helpers.hpp new file mode 100644 index 0000000..220d9d5 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/helpers.hpp @@ -0,0 +1,97 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +#include +#include +#include +#include +#include +#include + +template +using unique_vector = std::unique_ptr>; + +template +inline auto to_int(T value) { + using underlying_t = typename std::underlying_type_t; + static_assert(std::is_enum_v, "Must be an enum"); + return static_cast(value); +} + +inline auto to_unique_string(std::string s) { + return std::make_unique(std::move(s)); +} + +inline auto to_unique_string(std::string_view s) { + return std::make_unique(s); +} + +template +inline auto as_u8(T value) { + return static_cast(value); +} + +template +inline auto as_u16(T value) { + return static_cast(value); +} + +template +inline auto as_u32(T value) { + return static_cast(value); +} + +template +inline auto as_u64(T value) { + return static_cast(value); +} + +template +inline auto as_i32(T value) { + return static_cast(value); +} + +template +inline auto as_i64(T value) { + return static_cast(value); +} + +template +unique_vector make_unique_vector(Args... args) { + return std::make_unique>(std::forward(args)...); +} + +template +inline unique_vector to_vector(const std::array& array) { + auto result = make_unique_vector(); + result->reserve(array.size()); + std::transform(array.begin(), array.end(), std::back_inserter(*result), + [](const T& value) { return (uint64_t)value; }); + return result; +} + +template +inline unique_vector to_vector(const std::vector& vec) { + if (vec.empty()) { + return {}; + } + auto result = make_unique_vector(); + result->reserve(vec.size()); + std::transform(vec.begin(), vec.end(), std::back_inserter(*result), + [](const T& value) { return (uint64_t)value; }); + return result; +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/logging.hpp b/vendor/lief/api/rust/include/LIEF/rust/logging.hpp new file mode 100644 index 0000000..6c40e60 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/logging.hpp @@ -0,0 +1,73 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/logging.hpp" +#include "LIEF/rust/helpers.hpp" +#include +#include + +class LIEF_Logging { + public: + static auto disable() { + LIEF::logging::disable(); + } + static auto reset() { + LIEF::logging::reset(); + } + static auto enable() { + LIEF::logging::enable(); + } + static auto set_level(uint32_t lvl) { + LIEF::logging::set_level(LIEF::logging::Level(lvl)); + } + static auto set_path(const std::string& path) { + LIEF::logging::set_path(path); + } + + static auto log(uint32_t lvl, const std::string& msg) { + LIEF::logging::log(LIEF::logging::Level(lvl), msg); + } + + static auto get_level() { + return as_u32(LIEF::logging::get_level()); + } +}; + +class LIEF_Logging_Scoped { + public: + LIEF_Logging_Scoped() = delete; + LIEF_Logging_Scoped(const LIEF_Logging_Scoped&) = delete; + LIEF_Logging_Scoped& operator=(const LIEF_Logging_Scoped&) = delete; + + static auto create(uint32_t lvl) { + return std::unique_ptr(new LIEF_Logging_Scoped(lvl)); + } + + auto set_level(uint32_t lvl) const { + scoped_.set_level(LIEF::logging::Level(lvl)); + } + + auto reset() { + scoped_.reset(); + } + + ~LIEF_Logging_Scoped() = default; + + private: + explicit LIEF_Logging_Scoped(uint32_t lvl) : + scoped_(LIEF::logging::Level(lvl)) {} + + LIEF::logging::Scoped scoped_{LIEF::logging::Level::Info}; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/optional.hpp b/vendor/lief/api/rust/include/LIEF/rust/optional.hpp new file mode 100644 index 0000000..c68db1b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/optional.hpp @@ -0,0 +1,38 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include +namespace details { +template +inline T make_optional(std::optional&& result, uint32_t& is_set) { + if (result) { + is_set = 1; + return *result; + } + is_set = 0; + return T{}; +} + +template +inline T make_optional(const std::optional& result, uint32_t& is_set) { + if (result) { + is_set = 1; + return *result; + } + is_set = 0; + return T{}; +} +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/range.hpp b/vendor/lief/api/rust/include/LIEF/rust/range.hpp new file mode 100644 index 0000000..750d07a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/range.hpp @@ -0,0 +1,39 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/range.hpp" + +#include +#include + +class Range { + public: + uint64_t low = 0; + uint64_t high = 0; +}; + +namespace details { +inline Range make_range(LIEF::range_t range) { + return Range{range.low, range.high}; +} + +inline std::vector make_range(const std::vector& ranges) { + std::vector results; + results.reserve(ranges.size()); + std::transform(ranges.begin(), ranges.end(), std::back_inserter(results), + [](const LIEF::range_t& R) { return make_range(R); }); + return results; +} +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime.hpp new file mode 100644 index 0000000..6825a8f --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime.hpp @@ -0,0 +1,48 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/rust/runtime/Assembler.hpp" +#include "LIEF/rust/runtime/Disassembler.hpp" +#include "LIEF/rust/runtime/Host.hpp" +#include "LIEF/rust/runtime/Memory.hpp" +#include "LIEF/rust/runtime/MemoryLayout.hpp" +#include "LIEF/rust/runtime/Module.hpp" +#include "LIEF/rust/runtime/Process.hpp" +#include "LIEF/rust/runtime/android/Host.hpp" +#include "LIEF/rust/runtime/android/Module.hpp" +#include "LIEF/rust/runtime/android/Process.hpp" +#include "LIEF/rust/runtime/android/Property.hpp" +#include "LIEF/rust/runtime/linux/Host.hpp" +#include "LIEF/rust/runtime/linux/Module.hpp" +#include "LIEF/rust/runtime/linux/Process.hpp" +#include "LIEF/rust/runtime/osx/Host.hpp" +#include "LIEF/rust/runtime/osx/Module.hpp" +#include "LIEF/rust/runtime/osx/Process.hpp" +#include "LIEF/rust/runtime/windows/Host.hpp" +#include "LIEF/rust/runtime/windows/Module.hpp" + +inline bool runtime_enabled() { + return LIEF::runtime::is_enabled(); +} + +inline auto runtime_platform() { + return to_int(LIEF::runtime::platform()); +} + +inline auto runtime_arch() { + return to_int(LIEF::runtime::arch()); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Assembler.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Assembler.hpp new file mode 100644 index 0000000..63fdece --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Assembler.hpp @@ -0,0 +1,36 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include +#include +#include + +#include "LIEF/runtime/assembler.hpp" +#include "LIEF/rust/asm/AssemblerConfig.hpp" +#include "LIEF/rust/helpers.hpp" + +inline auto runtime_assemble(uint64_t address, const std::string& Asm) { + return make_unique_vector(LIEF::runtime::assemble(address, Asm)); +} + +inline auto runtime_assemble_with_config(uint64_t address, const std::string& Asm, + const AssemblerConfig_r& ffi_config) { + std::unique_ptr config = from_rust(ffi_config); + assert(config != nullptr); + return make_unique_vector(LIEF::runtime::assemble(address, Asm, + *config)); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Disassembler.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Disassembler.hpp new file mode 100644 index 0000000..6754bed --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Disassembler.hpp @@ -0,0 +1,38 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include + +#include "LIEF/runtime/disassembler.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/asm/Instruction.hpp" + +class runtime_it_instructions + : public ForwardIterator { + public: + runtime_it_instructions(uint64_t addr) : + ForwardIterator(LIEF::runtime::disassemble(static_cast(addr))) {} + + auto next() { + return ForwardIterator::next(); + } +}; + +inline auto runtime_disassemble(uint64_t addr) { + return std::make_unique(addr); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Host.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Host.hpp new file mode 100644 index 0000000..5fe9e35 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Host.hpp @@ -0,0 +1,43 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/Host.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_Host { + public: + using lief_t = LIEF::runtime::Host; + + static auto name() { + return to_unique_string(lief_t::name()); + } + + static auto home_dir() { + return to_unique_string(lief_t::home_dir()); + } + + static auto tmp_dir() { + return to_unique_string(lief_t::tmp_dir()); + } + + static auto config_dir() { + return to_unique_string(lief_t::config_dir()); + } + + static auto cache_dir() { + return to_unique_string(lief_t::cache_dir()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Memory.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Memory.hpp new file mode 100644 index 0000000..90d59ee --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Memory.hpp @@ -0,0 +1,105 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/Memory.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_Memory_Chunk : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::runtime::Memory::Chunk; + + uint64_t addr() const { + return get().addr(); + } + uint64_t size() const { + return get().size(); + } + auto permissions() const { + return get().permissions(); + } + uint64_t page_start() const { + return get().page_start(); + } + uint64_t page_end() const { + return get().page_end(); + } + + void change_permissions(uint32_t p) { + get().change_permissions(p); + } + + void make_x() { + get().make_x(); + } + void make_rw() { + get().make_rw(); + } + void make_rx() { + get().make_rx(); + } + void make_rwx() { + get().make_rwx(); + } + void make_ro() { + get().make_ro(); + } + + void cache_flush() { + get().cache_flush(); + } + + auto is_valid() const { + return get().is_valid(); + } + + void deallocate(uint32_t& err) { + details::make_error(get().deallocate(), err); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class runtime_Memory : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::runtime::Memory; + + static auto mmap(uint64_t size, uint32_t flags, uint32_t permission) { + return details::try_unique(lief_t::mmap(size, flags, + permission)); + } + + static auto mmap_hint(uint64_t hint, uint64_t size, uint32_t flags, + uint32_t permission) { + return details::try_unique( + lief_t::mmap_hint(hint, size, flags, permission) + ); + } + + static void munmap(runtime_Memory_Chunk& chunk, uint32_t& err) { + details::make_error(lief_t::munmap(chunk.get()), err); + } + + static void mprotect(runtime_Memory_Chunk& chunk, uint32_t flags, + uint32_t& err) { + details::make_error(lief_t::mprotect(chunk.get(), flags), err); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/MemoryLayout.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/MemoryLayout.hpp new file mode 100644 index 0000000..0582163 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/MemoryLayout.hpp @@ -0,0 +1,67 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/MemoryLayout.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_MemoryLayout_Region + : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::runtime::MemoryLayout::Region; + + auto name() const { + return to_unique_string(get().name()); + } + + uint64_t addr() const { + return get().addr(); + } + + uint64_t size() const { + return get().size(); + } + + uint64_t end_addr() const { + return get().end_addr(); + } + + auto contains(uint64_t addr) const { + return get().contains(addr); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class runtime_it_memory_layout + : public ForwardIterator { + public: + runtime_it_memory_layout() : + ForwardIterator(LIEF::runtime::memory_layout()) {} + + auto next() { + return ForwardIterator::next(); + } +}; + +inline auto runtime_memory_layout() { + return std::make_unique(); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Module.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Module.hpp new file mode 100644 index 0000000..1957a96 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Module.hpp @@ -0,0 +1,81 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/Module.hpp" +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_Module : public Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::runtime::Module; + + auto name() const { + return to_unique_string(get().name()); + } + auto path() const { + return to_unique_string(get().path()); + } + auto imagebase() const { + return get().imagebase(); + } + + uint64_t size() const { + return get().size(); + } + auto end() const { + return get().end(); + } + + auto contains(uint64_t addr) const { + return get().contains(addr); + } +}; + + +class runtime_it_modules + : public ForwardIterator { + public: + runtime_it_modules() : + ForwardIterator(LIEF::runtime::modules()) {} + + auto next() { + return ForwardIterator::next(); + } +}; + +inline auto runtime_modules() { + return std::make_unique(); +} + +inline auto runtime_module_from_name(const std::string& name) { + return details::try_unique( + LIEF::runtime::module_from_name(name) + ); +} + +inline auto runtime_module_from_path(const std::string& path) { + return details::try_unique( + LIEF::runtime::module_from_path(path) + ); +} + +inline auto runtime_module_from_addr(uint64_t addr) { + return details::try_unique( + LIEF::runtime::module_from_addr(addr) + ); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/Process.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/Process.hpp new file mode 100644 index 0000000..0c8d1f1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/Process.hpp @@ -0,0 +1,45 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/Process.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_Process : private Mirror { + public: + using Mirror::Mirror; + using lief_t = LIEF::runtime::Process; + + static int32_t pid() { + return lief_t::pid(); + } + + static int32_t tid() { + return lief_t::tid(); + } + + static auto platform() { + return as_u32(lief_t::platform()); + } + + static auto arch() { + return as_u32(lief_t::arch()); + } + + static auto page_size() { + return lief_t::page_size(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Host.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Host.hpp new file mode 100644 index 0000000..f39921d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Host.hpp @@ -0,0 +1,30 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/android/Host.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_android_Host { + public: + using lief_t = LIEF::runtime::android::Host; + + static int64_t sdk_version() { + if (auto version = lief_t::sdk_version()) { + return (int64_t)(*version); + } + return -1; + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Module.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Module.hpp new file mode 100644 index 0000000..7585f6b --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Module.hpp @@ -0,0 +1,73 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/android/Module.hpp" +#include "LIEF/rust/ELF/Binary.hpp" +#include "LIEF/rust/runtime/Module.hpp" + +class runtime_android_Module : public runtime_Module { + public: + using lief_t = LIEF::runtime::android::Module; + runtime_android_Module(std::unique_ptr mod) : + runtime_Module(std::move(mod)) {} + + auto handle() const { + return reinterpret_cast(impl().handle()); + } + + auto dlsym(const std::string& name) const { + return reinterpret_cast(impl().dlsym(name)); + } + + auto parse_from_path() const { + return details::try_unique(impl().parse_from_path()); + } + + auto parse_from_path_with_config(const ELF_ParserConfig& config) const { + return details::try_unique(impl().parse_from_path(config.conf())); + } + + auto parse_from_memory() const { + return details::try_unique(impl().parse_from_memory()); + } + + auto parse_from_memory_with_config(const ELF_ParserConfig& config) const { + return details::try_unique( + impl().parse_from_memory(config.conf()) + ); + } + + static auto from_handle(uint64_t handle) { + return details::try_unique( + lief_t::from_handle(reinterpret_cast(handle)) + ); + } + + static bool classof(const runtime_Module& M) { + return lief_t::classof(&M.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +inline auto runtime_android_dlopen(const std::string& name) { + return details::try_unique( + LIEF::runtime::android::dlopen(name) + ); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Process.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Process.hpp new file mode 100644 index 0000000..1993aa7 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Process.hpp @@ -0,0 +1,39 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/android/Process.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/runtime/android/Property.hpp" + +class runtime_android_Process { + public: + using lief_t = LIEF::runtime::android::Process; + + static auto cmdline() { + return to_unique_string(lief_t::cmdline()); + } + + static auto get_system_property(const std::string& name) { + return details::try_unique( + lief_t::get_system_property(name) + ); + } + + static auto properties() { + return std::make_unique(lief_t::properties()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Property.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Property.hpp new file mode 100644 index 0000000..3b7b638 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/android/Property.hpp @@ -0,0 +1,60 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" + +#include "LIEF/runtime/android/Property.hpp" + +class runtime_android_Property : public Mirror { + public: + using lief_t = LIEF::runtime::android::Property; + using Mirror::Mirror; + + auto name() const { + return to_unique_string(get().name()); + } + + auto value() const { + return to_unique_string(get().value()); + } + + auto serial() const { + return get().serial(); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class runtime_android_it_properties + : public ContainerIterator> { + public: + runtime_android_it_properties( + std::vector properties + ) : + ContainerIterator(std::move(properties)) {} + + // NOLINTNEXTLINE + auto next() { + return ContainerIterator::next(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Host.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Host.hpp new file mode 100644 index 0000000..3cb25f0 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Host.hpp @@ -0,0 +1,39 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/linux/Host.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_linux_Host { + public: + using lief_t = LIEF::runtime::Linux::Host; + + static auto sys_name() { + return to_unique_string(lief_t::sys_name()); + } + + static auto sys_release() { + return to_unique_string(lief_t::sys_release()); + } + + static auto sys_version() { + return to_unique_string(lief_t::sys_version()); + } + + static auto hardware() { + return to_unique_string(lief_t::hardware()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Module.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Module.hpp new file mode 100644 index 0000000..a6b018a --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Module.hpp @@ -0,0 +1,73 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/linux/Module.hpp" +#include "LIEF/rust/ELF/Binary.hpp" +#include "LIEF/rust/runtime/Module.hpp" + +class runtime_linux_Module : public runtime_Module { + public: + using lief_t = LIEF::runtime::Linux::Module; + runtime_linux_Module(std::unique_ptr mod) : + runtime_Module(std::move(mod)) {} + + auto handle() const { + return (uint64_t)impl().handle(); + } + + auto dlsym(const std::string& name) const { + return reinterpret_cast(impl().dlsym(name)); + } + + auto parse_from_path() const { + return details::try_unique(impl().parse_from_path()); + } + + auto parse_from_path_with_config(const ELF_ParserConfig& config) const { + return details::try_unique(impl().parse_from_path(config.conf())); + } + + auto parse_from_memory() const { + return details::try_unique(impl().parse_from_memory()); + } + + auto parse_from_memory_with_config(const ELF_ParserConfig& config) const { + return details::try_unique( + impl().parse_from_memory(config.conf()) + ); + } + + static auto from_handle(uint64_t handle) { + return details::try_unique( + lief_t::from_handle(reinterpret_cast(handle)) + ); + } + + static bool classof(const runtime_Module& M) { + return lief_t::classof(&M.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +inline auto runtime_linux_dlopen(const std::string& name) { + return details::try_unique( + LIEF::runtime::Linux::dlopen(name) + ); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Process.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Process.hpp new file mode 100644 index 0000000..f1f6ed9 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/linux/Process.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/linux/Process.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_linux_Process { + public: + using lief_t = LIEF::runtime::Linux::Process; + + static auto cmdline() { + return to_unique_string(lief_t::cmdline()); + } + + static auto glibc_version() { + return to_unique_string(lief_t::glibc_version()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Host.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Host.hpp new file mode 100644 index 0000000..6f41414 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Host.hpp @@ -0,0 +1,89 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/osx/Host.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_osx_Host { + public: + using lief_t = LIEF::runtime::osx::Host; + + static auto os_version_name() { + return to_unique_string(lief_t::os_version_name()); + } + + static auto is_sip_enabled() { + return lief_t::is_sip_enabled(); + } +}; + +class runtime_osx_Host_version_t { + public: + using lief_t = LIEF::runtime::osx::Host::version_t; + + runtime_osx_Host_version_t() : + impl_(0, 0, 0) {} + + runtime_osx_Host_version_t(const lief_t& v) : + impl_(v) {} + + uint32_t get_major() const { + return impl_.major; + } + uint32_t get_minor() const { + return impl_.minor; + } + uint32_t get_patch() const { + return impl_.patch; + } + + auto to_string() const { + return to_unique_string(impl_.to_string()); + } + + static auto os_version() { + return std::make_unique( + LIEF::runtime::osx::Host::os_version() + ); + } + + static auto big_sur() { + return std::make_unique(lief_t::BigSur()); + } + + static auto monterey() { + return std::make_unique(lief_t::Monterey()); + } + + static auto ventura() { + return std::make_unique(lief_t::Ventura()); + } + + static auto sonoma() { + return std::make_unique(lief_t::Sonoma()); + } + + static auto sequoia() { + return std::make_unique(lief_t::Sequoia()); + } + + static auto tahoe() { + return std::make_unique(lief_t::Tahoe()); + } + + private: + lief_t impl_; +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Module.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Module.hpp new file mode 100644 index 0000000..9817e73 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Module.hpp @@ -0,0 +1,61 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/osx/Module.hpp" +#include "LIEF/rust/MachO/Binary.hpp" +#include "LIEF/rust/runtime/Module.hpp" + +class runtime_osx_Module : public runtime_Module { + public: + using lief_t = LIEF::runtime::osx::Module; + runtime_osx_Module(std::unique_ptr mod) : + runtime_Module(std::move(mod)) {} + + auto handle() const { + return reinterpret_cast(impl().handle()); + } + + auto dlsym(const std::string& name) const { + return reinterpret_cast(impl().dlsym(name)); + } + + auto parse_from_path() const { + return details::try_unique(impl().parse_from_path()); + } + + auto parse_from_memory() const { + return details::try_unique(impl().parse_from_memory()); + } + + static auto from_handle(uint64_t handle) { + return details::try_unique( + lief_t::from_handle(reinterpret_cast(handle)) + ); + } + + static bool classof(const runtime_Module& M) { + return lief_t::classof(&M.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +inline auto runtime_osx_dlopen(const std::string& name) { + return details::try_unique(LIEF::runtime::osx::dlopen(name)); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Process.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Process.hpp new file mode 100644 index 0000000..29be6bb --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/osx/Process.hpp @@ -0,0 +1,27 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/osx/Process.hpp" +#include "LIEF/rust/helpers.hpp" + +class runtime_osx_Process { + public: + using lief_t = LIEF::runtime::osx::Process; + + static auto dyld_version() { + return to_unique_string(lief_t::dyld_version()); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Host.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Host.hpp new file mode 100644 index 0000000..533f1f8 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Host.hpp @@ -0,0 +1,55 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/Mirror.hpp" + +#include "LIEF/runtime/windows/Host.hpp" + +#include + +class runtime_windows_Host_version_t + : public Mirror { + public: + using lief_t = LIEF::runtime::windows::Host::version_t; + using Mirror::Mirror; + + runtime_windows_Host_version_t() : + Mirror::Mirror(std::make_unique()) {} + + runtime_windows_Host_version_t(const lief_t& v) : + Mirror::Mirror(std::make_unique(v)) {} + + auto get_major() const { + return get().major; + } + auto get_minor() const { + return get().minor; + } + auto get_build_number() const { + return get().build_number; + } +}; + +class runtime_windows_Host { + public: + using lief_t = LIEF::runtime::windows::Host; + + static auto version() { + return std::make_unique( + LIEF::runtime::windows::Host::version() + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/LdrDataTableEntry.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/LdrDataTableEntry.hpp new file mode 100644 index 0000000..d02d8f1 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/LdrDataTableEntry.hpp @@ -0,0 +1,153 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/Iterator.hpp" +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/rust/optional.hpp" + +#include "LIEF/runtime/windows/LdrDataTableEntry.hpp" + +class runtime_windows_LdrDataTableEntry + : public Mirror { + public: + using lief_t = LIEF::runtime::windows::LdrDataTableEntry; + using Mirror::Mirror; + + auto dll_base() const { + return (uint64_t)get().dll_base(); + } + + auto entry_point() const { + return (uint64_t)get().entry_point(); + } + + auto size_of_image() const { + return get().size_of_image(); + } + + auto full_dll_name() const { + return to_unique_string(get().full_dll_name()); + } + + auto base_dll_name() const { + return to_unique_string(get().base_dll_name()); + } + + auto flags() const { + return get().flags(); + } + + auto obsolete_load_count() const { + return get().obsolete_load_count(); + } + + auto tls_index() const { + return get().tls_index(); + } + + auto time_date_stamp() const { + return get().time_date_stamp(); + } + + auto entry_point_activation_context() const { + return (uint64_t)get().entry_point_activation_context(); + } + + auto lock() const { + return (uint64_t)get().lock(); + } + + uint64_t ddag_node(uint32_t& is_set) const { + return details::make_optional(get().ddag_node(), is_set); + } + + uint64_t load_context(uint32_t& is_set) const { + return details::make_optional(get().load_context(), is_set); + } + + uint64_t parent_dll_base(uint32_t& is_set) const { + return details::make_optional(get().parent_dll_base(), is_set); + } + + uint64_t switch_back_context(uint32_t& is_set) const { + return details::make_optional(get().switch_back_context(), is_set); + } + + uint64_t original_base(uint32_t& is_set) const { + return details::make_optional(get().original_base(), is_set); + } + + int64_t load_time(uint32_t& is_set) const { + return details::make_optional(get().load_time(), is_set); + } + + uint32_t base_name_hash_value(uint32_t& is_set) const { + return details::make_optional(get().base_name_hash_value(), is_set); + } + + int32_t load_reason(uint32_t& is_set) const { + return details::make_optional(get().load_reason(), is_set); + } + + uint32_t implicit_path_options(uint32_t& is_set) const { + return details::make_optional(get().implicit_path_options(), is_set); + } + + uint32_t reference_count(uint32_t& is_set) const { + return details::make_optional(get().reference_count(), is_set); + } + + uint32_t dependent_load_flags(uint32_t& is_set) const { + return details::make_optional(get().dependent_load_flags(), is_set); + } + + uint8_t signing_level(uint32_t& is_set) const { + return details::make_optional(get().signing_level(), is_set); + } + + uint32_t check_sum(uint32_t& is_set) const { + return details::make_optional(get().check_sum(), is_set); + } + + uint64_t active_patch_image_base(uint32_t& is_set) const { + return details::make_optional(get().active_patch_image_base(), is_set); + } + + uint32_t hot_patch_state(uint32_t& is_set) const { + return details::make_optional(get().hot_patch_state(), is_set); + } + + auto to_string() const { + return to_unique_string(get().to_string()); + } +}; + +class runtime_windows_it_ldr_data_table_entry + : public ForwardIterator { + public: + runtime_windows_it_ldr_data_table_entry( + LIEF::iterator_range + range + ) : + ForwardIterator(std::move(range)) {} + + // NOLINTNEXTLINE + auto next() { + return ForwardIterator::next(); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Module.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Module.hpp new file mode 100644 index 0000000..490690d --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Module.hpp @@ -0,0 +1,71 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/runtime/windows/Module.hpp" +#include "LIEF/rust/PE/Binary.hpp" +#include "LIEF/rust/runtime/Module.hpp" + +class runtime_windows_Module : public runtime_Module { + public: + using lief_t = LIEF::runtime::windows::Module; + runtime_windows_Module(std::unique_ptr mod) : + runtime_Module(std::move(mod)) {} + + auto handle() const { + return (uint64_t)impl().handle(); + } + + auto dlsym(const std::string& name) const { + return reinterpret_cast(impl().dlsym(name)); + } + + auto parse_from_path() const { + return details::try_unique(impl().parse_from_path()); + } + + auto parse_from_path_with_config(const PE_ParserConfig& config) const { + return details::try_unique(impl().parse_from_path(config.conf())); + } + + auto parse_from_memory() const { + return details::try_unique(impl().parse_from_memory()); + } + + auto parse_from_memory_with_config(const PE_ParserConfig& config) const { + return details::try_unique(impl().parse_from_memory(config.conf())); + } + + static bool classof(const runtime_Module& M) { + return lief_t::classof(&M.get()); + } + + private: + const lief_t& impl() const { + return as(this); + } +}; + +inline auto runtime_windows_dlopen(const std::string& name) { + return details::try_unique( + LIEF::runtime::windows::dlopen(name) + ); +} + +inline auto runtime_windows_find_module(const std::string& name) { + return details::try_unique( + LIEF::runtime::windows::find_module(name) + ); +} diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/PEB.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/PEB.hpp new file mode 100644 index 0000000..abbf208 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/PEB.hpp @@ -0,0 +1,60 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/runtime/windows/LdrDataTableEntry.hpp" + +#include "LIEF/runtime/windows/PEB.hpp" + +class runtime_windows_PEB : public Mirror { + public: + using lief_t = LIEF::runtime::windows::PEB; + using Mirror::Mirror; + + auto being_debugged() const { + return get().being_debugged(); + } + + auto ldr() const { + return (uint64_t)get().ldr(); + } + + auto process_parameters() const { + return (uint64_t)get().process_parameters(); + } + + auto atl_thunk_slist_ptr() const { + return (uint64_t)get().atl_thunk_slist_ptr(); + } + + auto atl_thunk_slist_ptr32() const { + return get().atl_thunk_slist_ptr32(); + } + + auto post_process_init_routine() const { + return (uint64_t)get().post_process_init_routine(); + } + + auto session_id() const { + return get().session_id(); + } + + auto entries() const { + return std::make_unique( + get().entries() + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Process.hpp b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Process.hpp new file mode 100644 index 0000000..a1d2063 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/runtime/windows/Process.hpp @@ -0,0 +1,31 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include "LIEF/rust/Mirror.hpp" +#include "LIEF/rust/runtime/windows/PEB.hpp" + +#include "LIEF/runtime/windows/Process.hpp" + +class runtime_windows_Process { + public: + using lief_t = LIEF::runtime::windows::Process; + + static auto peb() { + return details::try_unique( + LIEF::runtime::windows::Process::peb() + ); + } +}; diff --git a/vendor/lief/api/rust/include/LIEF/rust/utils.hpp b/vendor/lief/api/rust/include/LIEF/rust/utils.hpp new file mode 100644 index 0000000..928b632 --- /dev/null +++ b/vendor/lief/api/rust/include/LIEF/rust/utils.hpp @@ -0,0 +1,57 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include "LIEF/rust/error.hpp" +#include "LIEF/rust/helpers.hpp" +#include "LIEF/utils.hpp" + +class LIEFVersion { + public: + uint64_t major = 0; + uint64_t minor = 0; + uint64_t patch = 0; + uint64_t id = 0; +}; + +inline bool is_extended() { + return LIEF::is_extended(); +} + +inline auto demangle(const std::string& mangled, uint32_t& err) { + return to_unique_string(details::make_error(LIEF::demangle(mangled), + err)); +} + +inline auto extended_version_info() { + return to_unique_string(LIEF::extended_version_info()); +} + +inline LIEFVersion extended_version() { + auto version = LIEF::extended_version(); + return {version.major, version.minor, version.patch, version.id}; +} + +inline LIEFVersion version() { + auto version = LIEF::version(); + return {version.major, version.minor, version.patch, version.id}; +} +inline auto dump(const uint8_t* buffer, size_t size) { + return to_unique_string(LIEF::dump(buffer, size)); +} + +inline auto dump_with_limit(const uint8_t* buffer, size_t size, uint64_t limit) { + return to_unique_string(LIEF::dump(buffer, size, /*title=*/"", /*prefix=*/"", + limit)); +} diff --git a/vendor/lief/api/rust/src/CMakeLists.txt b/vendor/lief/api/rust/src/CMakeLists.txt new file mode 100644 index 0000000..86e741c --- /dev/null +++ b/vendor/lief/api/rust/src/CMakeLists.txt @@ -0,0 +1,6 @@ +target_sources(LIB_LIEF PRIVATE + symbol.cpp + stream.cpp + dsc_SubCache.cpp + dwarf_editor.cpp +) diff --git a/vendor/lief/api/rust/src/dsc_SubCache.cpp b/vendor/lief/api/rust/src/dsc_SubCache.cpp new file mode 100644 index 0000000..67717ab --- /dev/null +++ b/vendor/lief/api/rust/src/dsc_SubCache.cpp @@ -0,0 +1,9 @@ +#include "LIEF/MachO/Binary.hpp" +#include "LIEF/rust/DyldSharedCache/DyldSharedCache.hpp" +#include "LIEF/rust/DyldSharedCache/SubCache.hpp" + +std::unique_ptr dsc_SubCache::cache() const { + return details::try_unique( + get().cache() + ); // NOLINT(clang-analyzer-cplusplus.NewDeleteLeaks +} diff --git a/vendor/lief/api/rust/src/dwarf_editor.cpp b/vendor/lief/api/rust/src/dwarf_editor.cpp new file mode 100644 index 0000000..2fc3be8 --- /dev/null +++ b/vendor/lief/api/rust/src/dwarf_editor.cpp @@ -0,0 +1,6 @@ +#include "LIEF/rust/DWARF/editor/PointerType.hpp" +#include "LIEF/rust/DWARF/editor/Type.hpp" + +std::unique_ptr DWARF_editor_Type::pointer_to() const { + return details::try_unique(get().pointer_to()); +} diff --git a/vendor/lief/api/rust/src/stream.cpp b/vendor/lief/api/rust/src/stream.cpp new file mode 100644 index 0000000..bb0dee6 --- /dev/null +++ b/vendor/lief/api/rust/src/stream.cpp @@ -0,0 +1,25 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "LIEF/rust/Stream.hpp" +#include "LIEF/BinaryStream/VectorStream.hpp" +#include +#include + +std::unique_ptr RustStream::from_rust(uint8_t* buffer, size_t size) { + std::vector vector{buffer, buffer + size}; + auto vstream = std::make_unique(std::move(vector)); + return std::make_unique(std::move(vstream)); +} diff --git a/vendor/lief/api/rust/src/symbol.cpp b/vendor/lief/api/rust/src/symbol.cpp new file mode 100644 index 0000000..af236c9 --- /dev/null +++ b/vendor/lief/api/rust/src/symbol.cpp @@ -0,0 +1,26 @@ +/* Copyright 2024 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "LIEF/rust/MachO/Symbol.hpp" +#include "LIEF/rust/MachO/BindingInfo.hpp" +#include "LIEF/rust/MachO/ExportInfo.hpp" + +std::unique_ptr MachO_Symbol::export_info() const { + return details::try_unique(impl().export_info()); +} + +std::unique_ptr MachO_Symbol::binding_info() const { + return details::try_unique(impl().binding_info()); +} diff --git a/vendor/lief/cmake/ChooseMSVCCRT.cmake b/vendor/lief/cmake/ChooseMSVCCRT.cmake deleted file mode 100644 index 95d6d21..0000000 --- a/vendor/lief/cmake/ChooseMSVCCRT.cmake +++ /dev/null @@ -1,111 +0,0 @@ -# Copied from LLVM's ChooseMVSCCRT -# (https://github.com/llvm-mirror/llvm/blob/master/cmake/modules/ChooseMSVCCRT.cmake) - -# The macro choose_msvc_crt() takes a list of possible -# C runtimes to choose from, in the form of compiler flags, -# to present to the user. (MTd for /MTd, etc) -# -# The macro is invoked at the end of the file. -# -# CMake already sets CRT flags in the CMAKE_CXX_FLAGS_* and -# CMAKE_C_FLAGS_* variables by default. To let the user -# override that for each build type: -# 1. Detect which CRT is already selected, and reflect this in -# LIEF_USE_CRT_* so the user can have a better idea of what -# changes they're making. -# 2. Replace the flags in both variables with the new flag via a regex. -# 3. set() the variables back into the cache so the changes -# are user-visible. - -### Helper macros: ### -macro(make_crt_regex regex crts) - set(${regex} "") - foreach(crt ${${crts}}) - # Trying to match the beginning or end of the string with stuff - # like [ ^]+ didn't work, so use a bunch of parentheses instead. - set(${regex} "${${regex}}|(^| +)/${crt}($| +)") - endforeach(crt) - string(REGEX REPLACE "^\\|" "" ${regex} "${${regex}}") -endmacro(make_crt_regex) - -macro(get_current_crt crt_current regex flagsvar) - # Find the selected-by-CMake CRT for each build type, if any. - # Strip off the leading slash and any whitespace. - string(REGEX MATCH "${${regex}}" ${crt_current} "${${flagsvar}}") - string(REPLACE "/" " " ${crt_current} "${${crt_current}}") - string(STRIP "${${crt_current}}" ${crt_current}) -endmacro(get_current_crt) - -# Replaces or adds a flag to a variable. -# Expects 'flag' to be padded with spaces. -macro(set_flag_in_var flagsvar regex flag) - string(REGEX MATCH "${${regex}}" current_flag "${${flagsvar}}") - if("${current_flag}" STREQUAL "") - set(${flagsvar} "${${flagsvar}}${${flag}}") - else() - string(REGEX REPLACE "${${regex}}" "${${flag}}" ${flagsvar} "${${flagsvar}}") - endif() - string(STRIP "${${flagsvar}}" ${flagsvar}) - # Make sure this change gets reflected in the cache/gui. - # CMake requires the docstring parameter whenever set() touches the cache, - # so get the existing docstring and re-use that. - get_property(flagsvar_docs CACHE ${flagsvar} PROPERTY HELPSTRING) - set(${flagsvar} "${${flagsvar}}" CACHE STRING "${flagsvar_docs}" FORCE) -endmacro(set_flag_in_var) - -set(LIEF_CRT "") -macro(choose_msvc_crt MSVC_CRT) - if(LIEF_USE_CRT) - message(FATAL_ERROR - "LIEF_USE_CRT is deprecated. Use the CMAKE_BUILD_TYPE-specific -variables (LIEF_USE_CRT_DEBUG, etc) instead.") - endif() - - make_crt_regex(MSVC_CRT_REGEX ${MSVC_CRT}) - - foreach(build_type ${CMAKE_CONFIGURATION_TYPES} ${CMAKE_BUILD_TYPE}) - string(TOUPPER "${build_type}" build) - if (NOT LIEF_USE_CRT_${build}) - get_current_crt(LIEF_USE_CRT_${build} - MSVC_CRT_REGEX - CMAKE_CXX_FLAGS_${build}) - set(LIEF_USE_CRT_${build} - "${LIEF_USE_CRT_${build}}" - CACHE STRING "Specify VC++ CRT to use for ${build_type} configurations." - FORCE) - set_property(CACHE LIEF_USE_CRT_${build} - PROPERTY STRINGS ;${${MSVC_CRT}}) - endif(NOT LIEF_USE_CRT_${build}) - endforeach(build_type) - - foreach(build_type ${CMAKE_CONFIGURATION_TYPES} ${CMAKE_BUILD_TYPE}) - string(TOUPPER "${build_type}" build) - if ("${LIEF_USE_CRT_${build}}" STREQUAL "") - set(flag_string " ") - else() - set(flag_string " /${LIEF_USE_CRT_${build}} ") - list(FIND ${MSVC_CRT} ${LIEF_USE_CRT_${build}} idx) - if (idx LESS 0) - message(FATAL_ERROR - "Invalid value for LIEF_USE_CRT_${build}: ${LIEF_USE_CRT_${build}}. Valid options are one of: ${${MSVC_CRT}}") - endif (idx LESS 0) - message(STATUS "Using ${build_type} VC++ CRT: ${LIEF_USE_CRT_${build}}") - endif() - foreach(lang C CXX) - set_flag_in_var(CMAKE_${lang}_FLAGS_${build} MSVC_CRT_REGEX flag_string) - endforeach(lang) - endforeach(build_type) -endmacro(choose_msvc_crt MSVC_CRT) - -string(TOUPPER "${CMAKE_BUILD_TYPE}" build) -set(LIEF_CRT "/${LIEF_USE_CRT_${build}}") -message(STATUS "LIEF_CRT: ${LIEF_CRT}") -# List of valid CRTs for MSVC -set(MSVC_CRT - MD - MDd - MT - MTd) - -choose_msvc_crt(MSVC_CRT) - diff --git a/vendor/lief/cmake/FindPythonLibsNew.cmake b/vendor/lief/cmake/FindPythonLibsNew.cmake deleted file mode 100644 index 6ad5fe1..0000000 --- a/vendor/lief/cmake/FindPythonLibsNew.cmake +++ /dev/null @@ -1,270 +0,0 @@ -# - Find python libraries -# This module finds the libraries corresponding to the Python interpreter -# FindPythonInterp provides. -# This code sets the following variables: -# -# PYTHONLIBS_FOUND - have the Python libs been found -# PYTHON_PREFIX - path to the Python installation -# PYTHON_LIBRARIES - path to the python library -# PYTHON_INCLUDE_DIRS - path to where Python.h is found -# PYTHON_MODULE_EXTENSION - lib extension, e.g. '.so' or '.pyd' -# PYTHON_MODULE_PREFIX - lib name prefix: usually an empty string -# PYTHON_SITE_PACKAGES - path to installation site-packages -# PYTHON_IS_DEBUG - whether the Python interpreter is a debug build -# -# Thanks to talljimbo for the patch adding the 'LDVERSION' config -# variable usage. - -#============================================================================= -# Copyright 2001-2009 Kitware, Inc. -# Copyright 2012 Continuum Analytics, Inc. -# -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# * Neither the names of Kitware, Inc., the Insight Software Consortium, -# nor the names of their contributors may be used to endorse or promote -# products derived from this software without specific prior written -# permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#============================================================================= - -# Checking for the extension makes sure that `LibsNew` was found and not just `Libs`. -if(PYTHONLIBS_FOUND AND PYTHON_MODULE_EXTENSION) - return() -endif() - -if(PythonLibsNew_FIND_QUIETLY) - set(_pythonlibs_quiet QUIET) -else() - set(_pythonlibs_quiet "") -endif() - -if(PythonLibsNew_FIND_REQUIRED) - set(_pythonlibs_required REQUIRED) -endif() - -# Check to see if the `python` command is present and from a virtual -# environment, conda, or GHA activation - if it is, try to use that. - -if(NOT DEFINED PYTHON_EXECUTABLE) - if(DEFINED ENV{VIRTUAL_ENV}) - find_program( - PYTHON_EXECUTABLE python - PATHS "$ENV{VIRTUAL_ENV}" "$ENV{VIRTUAL_ENV}/bin" - NO_DEFAULT_PATH) - elseif(DEFINED ENV{CONDA_PREFIX}) - find_program( - PYTHON_EXECUTABLE python - PATHS "$ENV{CONDA_PREFIX}" "$ENV{CONDA_PREFIX}/bin" - NO_DEFAULT_PATH) - elseif(DEFINED ENV{pythonLocation}) - find_program( - PYTHON_EXECUTABLE python - PATHS "$ENV{pythonLocation}" "$ENV{pythonLocation}/bin" - NO_DEFAULT_PATH) - endif() - if(NOT PYTHON_EXECUTABLE) - unset(PYTHON_EXECUTABLE) - endif() -endif() - -# Use the Python interpreter to find the libs. -if(NOT PythonLibsNew_FIND_VERSION) - set(PythonLibsNew_FIND_VERSION "3.6") -endif() - -find_package(PythonInterp ${PythonLibsNew_FIND_VERSION} ${_pythonlibs_required} - ${_pythonlibs_quiet}) - -if(NOT PYTHONINTERP_FOUND) - set(PYTHONLIBS_FOUND FALSE) - set(PythonLibsNew_FOUND FALSE) - return() -endif() - -# According to https://stackoverflow.com/questions/646518/python-how-to-detect-debug-interpreter -# testing whether sys has the gettotalrefcount function is a reliable, cross-platform -# way to detect a CPython debug interpreter. -# -# The library suffix is from the config var LDVERSION sometimes, otherwise -# VERSION. VERSION will typically be like "2.7" on unix, and "27" on windows. -execute_process( - COMMAND - "${PYTHON_EXECUTABLE}" "-c" " -import sys;import struct; -import sysconfig as s -USE_SYSCONFIG = sys.version_info >= (3, 10) -if not USE_SYSCONFIG: - from distutils import sysconfig as ds -print('.'.join(str(v) for v in sys.version_info)); -print(sys.prefix); -if USE_SYSCONFIG: - scheme = s.get_default_scheme() - if scheme == 'posix_local': - # Debian's default scheme installs to /usr/local/ but we want to find headers in /usr/ - scheme = 'posix_prefix' - print(s.get_path('platinclude', scheme)) - print(s.get_path('platlib')) -else: - print(ds.get_python_inc(plat_specific=True)); - print(ds.get_python_lib(plat_specific=True)); -print(s.get_config_var('EXT_SUFFIX') or s.get_config_var('SO')); -print(hasattr(sys, 'gettotalrefcount')+0); -print(struct.calcsize('@P')); -print(s.get_config_var('LDVERSION') or s.get_config_var('VERSION')); -print(s.get_config_var('LIBDIR') or ''); -print(s.get_config_var('MULTIARCH') or ''); -" - RESULT_VARIABLE _PYTHON_SUCCESS - OUTPUT_VARIABLE _PYTHON_VALUES - ERROR_VARIABLE _PYTHON_ERROR_VALUE) - -if(NOT _PYTHON_SUCCESS MATCHES 0) - if(PythonLibsNew_FIND_REQUIRED) - message(FATAL_ERROR "Python config failure:\n${_PYTHON_ERROR_VALUE}") - endif() - set(PYTHONLIBS_FOUND FALSE) - set(PythonLibsNew_FOUND FALSE) - return() -endif() - -# Convert the process output into a list -if(WIN32) - string(REGEX REPLACE "\\\\" "/" _PYTHON_VALUES ${_PYTHON_VALUES}) -endif() -string(REGEX REPLACE ";" "\\\\;" _PYTHON_VALUES ${_PYTHON_VALUES}) -string(REGEX REPLACE "\n" ";" _PYTHON_VALUES ${_PYTHON_VALUES}) -list(GET _PYTHON_VALUES 0 _PYTHON_VERSION_LIST) -list(GET _PYTHON_VALUES 1 PYTHON_PREFIX) -list(GET _PYTHON_VALUES 2 PYTHON_INCLUDE_DIR) -list(GET _PYTHON_VALUES 3 PYTHON_SITE_PACKAGES) -list(GET _PYTHON_VALUES 4 PYTHON_MODULE_EXTENSION) -list(GET _PYTHON_VALUES 5 PYTHON_IS_DEBUG) -list(GET _PYTHON_VALUES 6 PYTHON_SIZEOF_VOID_P) -list(GET _PYTHON_VALUES 7 PYTHON_LIBRARY_SUFFIX) -list(GET _PYTHON_VALUES 8 PYTHON_LIBDIR) -list(GET _PYTHON_VALUES 9 PYTHON_MULTIARCH) - -# Make sure the Python has the same pointer-size as the chosen compiler -# Skip if CMAKE_SIZEOF_VOID_P is not defined -if(CMAKE_SIZEOF_VOID_P AND (NOT "${PYTHON_SIZEOF_VOID_P}" STREQUAL "${CMAKE_SIZEOF_VOID_P}")) - if(PythonLibsNew_FIND_REQUIRED) - math(EXPR _PYTHON_BITS "${PYTHON_SIZEOF_VOID_P} * 8") - math(EXPR _CMAKE_BITS "${CMAKE_SIZEOF_VOID_P} * 8") - message(FATAL_ERROR "Python config failure: Python is ${_PYTHON_BITS}-bit, " - "chosen compiler is ${_CMAKE_BITS}-bit") - endif() - set(PYTHONLIBS_FOUND FALSE) - set(PythonLibsNew_FOUND FALSE) - return() -endif() - -# The built-in FindPython didn't always give the version numbers -string(REGEX REPLACE "\\." ";" _PYTHON_VERSION_LIST ${_PYTHON_VERSION_LIST}) -list(GET _PYTHON_VERSION_LIST 0 PYTHON_VERSION_MAJOR) -list(GET _PYTHON_VERSION_LIST 1 PYTHON_VERSION_MINOR) -list(GET _PYTHON_VERSION_LIST 2 PYTHON_VERSION_PATCH) -set(PYTHON_VERSION "${PYTHON_VERSION_MAJOR}.${PYTHON_VERSION_MINOR}.${PYTHON_VERSION_PATCH}") - -# Make sure all directory separators are '/' -string(REGEX REPLACE "\\\\" "/" PYTHON_PREFIX "${PYTHON_PREFIX}") -string(REGEX REPLACE "\\\\" "/" PYTHON_INCLUDE_DIR "${PYTHON_INCLUDE_DIR}") -string(REGEX REPLACE "\\\\" "/" PYTHON_SITE_PACKAGES "${PYTHON_SITE_PACKAGES}") - -if(CMAKE_HOST_WIN32) - set(PYTHON_LIBRARY "${PYTHON_PREFIX}/libs/python${PYTHON_LIBRARY_SUFFIX}.lib") - - # when run in a venv, PYTHON_PREFIX points to it. But the libraries remain in the - # original python installation. They may be found relative to PYTHON_INCLUDE_DIR. - if(NOT EXISTS "${PYTHON_LIBRARY}") - get_filename_component(_PYTHON_ROOT ${PYTHON_INCLUDE_DIR} DIRECTORY) - set(PYTHON_LIBRARY "${_PYTHON_ROOT}/libs/python${PYTHON_LIBRARY_SUFFIX}.lib") - endif() - - # if we are in MSYS & MINGW, and we didn't find windows python lib, look for system python lib - if(DEFINED ENV{MSYSTEM} - AND MINGW - AND NOT EXISTS "${PYTHON_LIBRARY}") - if(PYTHON_MULTIARCH) - set(_PYTHON_LIBS_SEARCH "${PYTHON_LIBDIR}/${PYTHON_MULTIARCH}" "${PYTHON_LIBDIR}") - else() - set(_PYTHON_LIBS_SEARCH "${PYTHON_LIBDIR}") - endif() - unset(PYTHON_LIBRARY) - find_library( - PYTHON_LIBRARY - NAMES "python${PYTHON_LIBRARY_SUFFIX}" - PATHS ${_PYTHON_LIBS_SEARCH} - NO_DEFAULT_PATH) - endif() - - # raise an error if the python libs are still not found. - if(NOT EXISTS "${PYTHON_LIBRARY}") - message(FATAL_ERROR "Python libraries not found") - endif() - -else() - if(PYTHON_MULTIARCH) - set(_PYTHON_LIBS_SEARCH "${PYTHON_LIBDIR}/${PYTHON_MULTIARCH}" "${PYTHON_LIBDIR}") - else() - set(_PYTHON_LIBS_SEARCH "${PYTHON_LIBDIR}") - endif() - #message(STATUS "Searching for Python libs in ${_PYTHON_LIBS_SEARCH}") - # Probably this needs to be more involved. It would be nice if the config - # information the python interpreter itself gave us were more complete. - find_library( - PYTHON_LIBRARY - NAMES "python${PYTHON_LIBRARY_SUFFIX}" - PATHS ${_PYTHON_LIBS_SEARCH} - NO_DEFAULT_PATH) - - # If all else fails, just set the name/version and let the linker figure out the path. - if(NOT PYTHON_LIBRARY) - set(PYTHON_LIBRARY python${PYTHON_LIBRARY_SUFFIX}) - endif() -endif() - -mark_as_advanced(PYTHON_LIBRARY PYTHON_INCLUDE_DIR) - -# We use PYTHON_INCLUDE_DIR, PYTHON_LIBRARY and PYTHON_DEBUG_LIBRARY for the -# cache entries because they are meant to specify the location of a single -# library. We now set the variables listed by the documentation for this -# module. -set(PYTHON_INCLUDE_DIRS "${PYTHON_INCLUDE_DIR}") -set(PYTHON_LIBRARIES "${PYTHON_LIBRARY}") -if(NOT PYTHON_DEBUG_LIBRARY) - set(PYTHON_DEBUG_LIBRARY "") -endif() -set(PYTHON_DEBUG_LIBRARIES "${PYTHON_DEBUG_LIBRARY}") - -find_package_message(PYTHON "Found PythonLibs: ${PYTHON_LIBRARY}" - "${PYTHON_EXECUTABLE}${PYTHON_VERSION_STRING}") - -set(PYTHONLIBS_FOUND TRUE) -set(PythonLibsNew_FOUND TRUE) - -if(NOT PYTHON_MODULE_PREFIX) - set(PYTHON_MODULE_PREFIX "") -endif() diff --git a/vendor/lief/cmake/FindSphinx.cmake b/vendor/lief/cmake/FindSphinx.cmake deleted file mode 100644 index 9d252e8..0000000 --- a/vendor/lief/cmake/FindSphinx.cmake +++ /dev/null @@ -1,27 +0,0 @@ -# CMake find_package() Module for Sphinx documentation generator -# http://sphinx-doc.org/ -# -# Example usage: -# -# find_package(Sphinx) -# -# If successful the following variables will be defined -# SPHINX_FOUND -# SPHINX_EXECUTABLE - -find_program(SPHINX_EXECUTABLE - NAMES sphinx-build sphinx-build2 - DOC "Path to sphinx-build executable") - -# Handle REQUIRED and QUIET arguments -# this will also set SPHINX_FOUND to true if SPHINX_EXECUTABLE exists -include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(Sphinx - "Failed to locate sphinx-build executable" - SPHINX_EXECUTABLE) - -# Provide options for controlling different types of output -option(SPHINX_OUTPUT_HTML "Output standalone HTML files" ON) -option(SPHINX_OUTPUT_MAN "Output man pages" ON) - -option(SPHINX_WARNINGS_AS_ERRORS "When building documentation treat warnings as errors" ON) diff --git a/vendor/lief/LIEF.pc.in b/vendor/lief/cmake/LIEF.pc.in similarity index 100% rename from vendor/lief/LIEF.pc.in rename to vendor/lief/cmake/LIEF.pc.in diff --git a/vendor/lief/cmake/LIEFApi.cmake b/vendor/lief/cmake/LIEFApi.cmake deleted file mode 100644 index 42e0b8d..0000000 --- a/vendor/lief/cmake/LIEFApi.cmake +++ /dev/null @@ -1,25 +0,0 @@ -if(__add_lief_api) - return() -endif() -set(__add_lief_api ON) - -# Python -# ------ -if (LIEF_PYTHON_API) - if(WIN32) - set(PYTHON_BUILD_LIEF_DIRECTORY "${CMAKE_BINARY_DIR}/api/python/Release") - else() - set(PYTHON_BUILD_LIEF_DIRECTORY "${CMAKE_BINARY_DIR}/api/python") - endif() - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/api/python") -endif() - -# C API -# ----- -if(LIEF_C_API) - target_include_directories(LIB_LIEF - PUBLIC "$") - - include("${CMAKE_CURRENT_SOURCE_DIR}/api/c/CMakeLists.txt") -endif() - diff --git a/vendor/lief/cmake/LIEFCompilerDetection.cmake b/vendor/lief/cmake/LIEFCompilerDetection.cmake index 14b808c..806f8f4 100644 --- a/vendor/lief/cmake/LIEFCompilerDetection.cmake +++ b/vendor/lief/cmake/LIEFCompilerDetection.cmake @@ -1,30 +1,26 @@ -if(__add_lief_compiler_detection) - return() -endif() -set(__add_lief_compiler_detection ON) +include_guard(GLOBAL) set(LIEF_SUPPORT_CXX11 0) set(LIEF_SUPPORT_CXX14 0) set(LIEF_SUPPORT_CXX17 0) -if (cxx_std_11 IN_LIST CMAKE_CXX_COMPILE_FEATURES) +if(cxx_std_11 IN_LIST CMAKE_CXX_COMPILE_FEATURES) set(LIEF_SUPPORT_CXX11 1) endif() -if (cxx_std_14 IN_LIST CMAKE_CXX_COMPILE_FEATURES) - if (${MSVC} AND ${MSVC_TOOLSET_VERSION} GREATER_EQUAL 141) - set(LIEF_SUPPORT_CXX14 1) - elseif((NOT DEFINED MSVC) OR (NOT ${MSVC})) - set(LIEF_SUPPORT_CXX14 1) - endif() +if(cxx_std_14 IN_LIST CMAKE_CXX_COMPILE_FEATURES) + set(LIEF_SUPPORT_CXX14 1) +endif() + +if(cxx_std_17 IN_LIST CMAKE_CXX_COMPILE_FEATURES) + set(LIEF_SUPPORT_CXX17 1) endif() -if (cxx_std_17 IN_LIST CMAKE_CXX_COMPILE_FEATURES) - if (${MSVC} AND ${MSVC_TOOLSET_VERSION} GREATER_EQUAL 142) - set(LIEF_SUPPORT_CXX17 1) - elseif((NOT DEFINED MSVC) OR (NOT ${MSVC})) - set(LIEF_SUPPORT_CXX17 1) - endif() +if(NOT LIEF_SUPPORT_CXX17) + message(FATAL_ERROR + "LIEF requires a compiler with C++17 support, but 'cxx_std_17' is not " + "advertised in CMAKE_CXX_COMPILE_FEATURES for " + "${CMAKE_CXX_COMPILER_ID} ${CMAKE_CXX_COMPILER_VERSION}.") endif() configure_file( @@ -32,4 +28,3 @@ configure_file( "${CMAKE_CURRENT_BINARY_DIR}/compiler_support.h" @ONLY ) - diff --git a/vendor/lief/cmake/LIEFCompilerFlags.cmake b/vendor/lief/cmake/LIEFCompilerFlags.cmake index 2812849..9a058f0 100644 --- a/vendor/lief/cmake/LIEFCompilerFlags.cmake +++ b/vendor/lief/cmake/LIEFCompilerFlags.cmake @@ -1,150 +1,102 @@ -include(CheckCCompilerFlag) -include(CheckCXXCompilerFlag) -if(__add_lief_compiler_flags) - return() -endif() -set(__add_lief_compiler_flags ON) - -function(append value) - foreach(variable ${ARGN}) - set(${variable} "${${variable}} ${value}" PARENT_SCOPE) - endforeach(variable) -endfunction() - -function(append_if condition value) - if (${condition}) - foreach(variable ${ARGN}) - set(${variable} "${${variable}} ${value}" PARENT_SCOPE) - endforeach(variable) - endif() -endfunction() - -macro(ADD_FLAG_IF_SUPPORTED flag name) - CHECK_C_COMPILER_FLAG("${flag}" "C_SUPPORTS_${name}") - CHECK_CXX_COMPILER_FLAG("${flag}" "CXX_SUPPORTS_${name}") - - if (C_SUPPORTS_${name}) - target_compile_options(LIB_LIEF PRIVATE ${flag}) +include_guard(GLOBAL) + +if((CMAKE_CXX_COMPILER_ID MATCHES "Clang" OR CMAKE_CXX_COMPILER_ID MATCHES "GNU") AND NOT MSVC) + target_compile_options(LIB_LIEF PRIVATE + -Wall + -Wextra + -Wpedantic + -Wno-expansion-to-defined + -Wno-unused-lambda-capture + # Promote this warning into an error as error management + # where the result is 'result' might miss the "return {}" + -Werror=return-type + -fdiagnostics-color=always + ) + if(CMAKE_CXX_COMPILER_ID MATCHES "Clang") + if(CMAKE_GENERATOR MATCHES "Ninja") + target_compile_options(LIB_LIEF PRIVATE + -fcolor-diagnostics + ) + endif() + else(CMAKE_CXX_COMPILER_ID MATCHES "GNU") + # GCC specific flags endif() - if (CXX_SUPPORTS_${name}) - target_compile_options(LIB_LIEF PRIVATE ${flag}) + if (LIEF_DISABLE_EXCEPTIONS) + target_compile_options(LIB_LIEF PRIVATE -fno-exceptions) endif() -endmacro() - - -if (MSVC) - add_definitions(-DNOMINMAX) endif() -if(CMAKE_COMPILER_IS_GNUCXX OR CMAKE_CXX_COMPILER_ID MATCHES "Clang") - if (UNIX) - if (LIEF_FORCE32) - target_compile_options(LIB_LIEF PRIVATE -m32) - - set_property(TARGET LIB_LIEF PROPERTY LINK_FLAGS -m32) - endif() +if(MSVC) + target_compile_definitions(LIB_LIEF PRIVATE NOMINMAX) + + target_compile_options(LIB_LIEF PRIVATE + /W4 + + # Disabled warnings. + /wd4141 # Suppress ''modifier' : used more than once' (because of __forceinline combined with inline) + /wd4146 # Suppress 'unary minus operator applied to unsigned type, result still unsigned' + /wd4244 # Suppress ''argument' : conversion from 'type1' to 'type2', possible loss of data' + /wd4267 # Suppress ''var' : conversion from 'size_t' to 'type', possible loss of data' + /wd4291 # Suppress ''declaration' : no matching operator delete found; memory will not be freed if initialization throws an exception' + /wd4351 # Suppress 'new behavior: elements of array 'array' will be default initialized' + /wd4456 # Suppress 'declaration of 'var' hides local variable' + /wd4457 # Suppress 'declaration of 'var' hides function parameter' + /wd4458 # Suppress 'declaration of 'var' hides class member' + /wd4459 # Suppress 'declaration of 'var' hides global declaration' + /wd4503 # Suppress ''identifier' : decorated name length exceeded, name was truncated' + /wd4624 # Suppress ''derived class' : destructor could not be generated because a base class destructor is inaccessible' + /wd4722 # Suppress 'function' : destructor never returns, potential memory leak + /wd4100 # Suppress 'unreferenced formal parameter' + /wd4127 # Suppress 'conditional expression is constant' + /wd4512 # Suppress 'assignment operator could not be generated' + /wd4505 # Suppress 'unreferenced local function has been removed' + /wd4610 # Suppress ' can never be instantiated' + /wd4510 # Suppress 'default constructor could not be generated' + /wd4702 # Suppress 'unreachable code' + /wd4245 # Suppress ''conversion' : conversion from 'type1' to 'type2', signed/unsigned mismatch' + /wd4706 # Suppress 'assignment within conditional expression' + /wd4310 # Suppress 'cast truncates constant value' + /wd4701 # Suppress 'potentially uninitialized local variable' + /wd4703 # Suppress 'potentially uninitialized local pointer variable' + /wd4389 # Suppress 'signed/unsigned mismatch' + /wd4611 # Suppress 'interaction between '_setjmp' and C++ object destruction is non-portable' + /wd4805 # Suppress 'unsafe mix of type and type in operation' + /wd4204 # Suppress 'nonstandard extension used : non-constant aggregate initializer' + /wd4577 # Suppress 'noexcept used with no exception handling mode specified; termination on exception is not guaranteed' + /wd4091 # Suppress 'typedef: ignored on left of '' when no variable is declared' + # C4592 is disabled because of false positives in Visual Studio 2015 + # Update 1. Re-evaluate the usefulness of this diagnostic with Update 2. + /wd4592 # Suppress ''var': symbol will be dynamically initialized (implementation limitation) + /wd4319 # Suppress ''operator' : zero extending 'type' to 'type' of greater size' + # C4709 is disabled because of a bug with Visual Studio 2017 as of + # v15.8.8. Re-evaluate the usefulness of this diagnostic when the bug is fixed. + /wd4709 # Suppress comma operator within array index expression + + # We'd like this warning to be enabled, but it triggers from code in + # WinBase.h that we don't have control over. + /wd5105 # Suppress macro expansion producing 'defined' has undefined behavior + + # Ideally, we'd like this warning to be enabled, but even MSVC 2019 doesn't + # support the 'aligned' attribute in the way that clang sources requires (for + # any code that uses the LLVM_ALIGNAS macro), so this is must be disabled to + # avoid unwanted alignment warnings. + /wd4324 # Suppress 'structure was padded due to __declspec(align())' + + # Promoted warnings. + /w14062 # Promote 'enumerator in switch of enum is not handled' to level 1 warning. + + # Promoted warnings to errors. + /we4238 # Promote 'nonstandard extension used : class rvalue used as lvalue' to error. + + /wd4530 # Supress C++ exception handler used, but unwind semantics are not enabled + /wd4251 # remove: needs to have dll-interface to be used by clients of class + ) + + if (LIEF_DISABLE_EXCEPTIONS) + target_compile_options(LIB_LIEF PRIVATE /EHsc-) endif() - -endif() - -if (NOT MSVC) - ADD_FLAG_IF_SUPPORTED("-Wall" WALL) - ADD_FLAG_IF_SUPPORTED("-Wextra" WEXTRA) - ADD_FLAG_IF_SUPPORTED("-Wpedantic" WPEDANTIC) - ADD_FLAG_IF_SUPPORTED("-fno-stack-protector" NO_STACK_PROTECTOR) - ADD_FLAG_IF_SUPPORTED("-fomit-frame-pointer" OMIT_FRAME_POINTER) - ADD_FLAG_IF_SUPPORTED("-fno-strict-aliasing" NO_STRICT_ALIASING) - ADD_FLAG_IF_SUPPORTED("-fexceptions" EXCEPTION) - ADD_FLAG_IF_SUPPORTED("-Wno-expansion-to-defined" NO_EXPANSION_TO_DEFINED) - - # Promote this warning into an error as Leaf error management - # where the result is 'result' might miss the "return {}" - ADD_FLAG_IF_SUPPORTED("-Werror=return-type" ERR_RET_TYPE) - - - ADD_FLAG_IF_SUPPORTED("-fdiagnostics-color=always" DIAGNOSTICS_COLOR) - ADD_FLAG_IF_SUPPORTED("-fcolor-diagnostics" COLOR_DIAGNOSTICS) -endif() - -#ADD_FLAG_IF_SUPPORTED("-Wduplicated-cond" HAS_DUPLICATED_COND) -#ADD_FLAG_IF_SUPPORTED("-Wduplicated-branches" HAS_DUPLICATED_BRANCHES) -#ADD_FLAG_IF_SUPPORTED("-Wlogical-op" HAS_LOGICAL_OP) -#ADD_FLAG_IF_SUPPORTED("-Wshadow" HAS_SHADOW) -# ========================================= -# MSVC FLAGS -# This part is inspired from LLVM: -# https://github.com/llvm-mirror/llvm/blob/a86576d8771c89502d239f0b85a1a6992020aa47/cmake/modules/HandleLLVMOptions.cmake -# ========================================= -set(msvc_warning_flags - # Disabled warnings. - -wd4141 # Suppress ''modifier' : used more than once' (because of __forceinline combined with inline) - -wd4146 # Suppress 'unary minus operator applied to unsigned type, result still unsigned' - -wd4180 # Suppress 'qualifier applied to function type has no meaning; ignored' - -wd4244 # Suppress ''argument' : conversion from 'type1' to 'type2', possible loss of data' - -wd4258 # Suppress ''var' : definition from the for loop is ignored; the definition from the enclosing scope is used' - -wd4267 # Suppress ''var' : conversion from 'size_t' to 'type', possible loss of data' - -wd4291 # Suppress ''declaration' : no matching operator delete found; memory will not be freed if initialization throws an exception' - -wd4345 # Suppress 'behavior change: an object of POD type constructed with an initializer of the form () will be default-initialized' - -wd4351 # Suppress 'new behavior: elements of array 'array' will be default initialized' - -wd4355 # Suppress ''this' : used in base member initializer list' - -wd4456 # Suppress 'declaration of 'var' hides local variable' - -wd4457 # Suppress 'declaration of 'var' hides function parameter' - -wd4458 # Suppress 'declaration of 'var' hides class member' - -wd4459 # Suppress 'declaration of 'var' hides global declaration' - -wd4503 # Suppress ''identifier' : decorated name length exceeded, name was truncated' - -wd4624 # Suppress ''derived class' : destructor could not be generated because a base class destructor is inaccessible' - -wd4722 # Suppress 'function' : destructor never returns, potential memory leak - -wd4800 # Suppress ''type' : forcing value to bool 'true' or 'false' (performance warning)' - -wd4100 # Suppress 'unreferenced formal parameter' - -wd4127 # Suppress 'conditional expression is constant' - -wd4512 # Suppress 'assignment operator could not be generated' - -wd4505 # Suppress 'unreferenced local function has been removed' - -wd4610 # Suppress ' can never be instantiated' - -wd4510 # Suppress 'default constructor could not be generated' - -wd4702 # Suppress 'unreachable code' - -wd4245 # Suppress 'signed/unsigned mismatch' - -wd4706 # Suppress 'assignment within conditional expression' - -wd4310 # Suppress 'cast truncates constant value' - -wd4701 # Suppress 'potentially uninitialized local variable' - -wd4703 # Suppress 'potentially uninitialized local pointer variable' - -wd4389 # Suppress 'signed/unsigned mismatch' - -wd4611 # Suppress 'interaction between '_setjmp' and C++ object destruction is non-portable' - -wd4805 # Suppress 'unsafe mix of type and type in operation' - -wd4204 # Suppress 'nonstandard extension used : non-constant aggregate initializer' - -wd4577 # Suppress 'noexcept used with no exception handling mode specified; termination on exception is not guaranteed' - -wd4091 # Suppress 'typedef: ignored on left of '' when no variable is declared' - # C4592 is disabled because of false positives in Visual Studio 2015 - # Update 1. Re-evaluate the usefulness of this diagnostic with Update 2. - -wd4592 # Suppress ''var': symbol will be dynamically initialized (implementation limitation) - -wd4319 # Suppress ''operator' : zero extending 'type' to 'type' of greater size' - -wd4710 # Suppress 'function not inlined' - -wd4820 # Suppress 'XXX bytes padding added after data member' - -wd4514 # Suppress 'unreferenced inline function has been removed' - - # Ideally, we'd like this warning to be enabled, but MSVC 2013 doesn't - # support the 'aligned' attribute in the way that clang sources requires (for - # any code that uses the LLVM_ALIGNAS macro), so this is must be disabled to - # avoid unwanted alignment warnings. - # When we switch to requiring a version of MSVC that supports the 'alignas' - # specifier (MSVC 2015?) this warning can be re-enabled. - -wd4324 # Suppress 'structure was padded due to __declspec(align())' - - # Promoted warnings. - -w14062 # Promote 'enumerator in switch of enum is not handled' to level 1 warning. - - # Promoted warnings to errors. - -we4238 # Promote 'nonstandard extension used : class rvalue used as lvalue' to error. -) - -if (MSVC) - set(msvc_warning_flags "/W4 ${msvc_warning_flags}") - string(REGEX REPLACE " /W[0-4]" "" CMAKE_C_FLAGS "${CMAKE_C_FLAGS}") - string(REGEX REPLACE " /W[0-4]" "" CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}") - #foreach(flag ${msvc_warning_flags}) - # target_compile_options(LIB_LIEF PRIVATE ${flag}) - #endforeach(flag) endif() # Speed up MSVC build @@ -154,13 +106,12 @@ if (MSVC_IDE) if (NOT LIEF_COMPILER_JOBS STREQUAL "1") if(LIEF_COMPILER_JOBS STREQUAL "0") message(STATUS "Number of parallel compiler jobs set to /MP") - add_definitions(/MP) + target_compile_options(LIB_LIEF PRIVATE /MP) else() message(STATUS "Number of parallel compiler jobs set to /MP${LIEF_COMPILER_JOBS}") - add_definitions(/MP${LIEF_COMPILER_JOBS}) + target_compile_options(LIB_LIEF PRIVATE /MP${LIEF_COMPILER_JOBS}) endif() else() message(STATUS "Parallel compilation disabled") endif() endif() - diff --git a/vendor/lief/cmake/LIEFConfig.cmake.in b/vendor/lief/cmake/LIEFConfig.cmake.in new file mode 100644 index 0000000..0af3ee1 --- /dev/null +++ b/vendor/lief/cmake/LIEFConfig.cmake.in @@ -0,0 +1,214 @@ +#.rst: +# LIEFConfig +# -------- +# +# Populate the native LIEF targets. +# +# IMPORTED Targets +# ^^^^^^^^^^^^^^^^ +# +# This module defines :prop_tgt:`IMPORTED` target ``LIEF::LIEF`` +# +# Hints +# ^^^^^ +# +# A user may set ``LIEF_DIR`` to the directory where ``LIEFConfig.cmake`` file +# resides to tell CMake where to find this file. +# +# To choose between STATIC and SHARED version of LIEF library, one can use +# ``COMPONENTS STATIC`` of ``COMPONENTS SHARED``. If no components are +# specified, then a user may set ``LIEF_SHARED_LIBS`` to a true value to +# request shared libraries. By default, if no variables or components are set, +# the static library is preferred if present, else shared library will be used. +# +# .. code-block:: cmake +# +# find_package(LIEF 0.11.0 REQUIRED COMPONENTS STATIC) + + +# CMake component support for static and shared libraries based on +# https://alexreinking.com/blog/building-a-dual-shared-and-static-library-with-cmake.html + +# Process known components +set(LIEF_known_comps STATIC SHARED) +set(LIEF_comp_STATIC NO) +set(LIEF_comp_SHARED NO) +foreach(_comp ${LIEF_FIND_COMPONENTS}) + if(";${LIEF_known_comps};" MATCHES ";${_comp};") + set(LIEF_comp_${_comp} YES) + else() + set(LIEF_NOT_FOUND_MESSAGE + "LIEF does not recognize component `${_comp}`.") + set(LIEF_FOUND FALSE) + return() + endif() +endforeach() + + +# Validate component selection makes sense +if(LIEF_comp_STATIC AND LIEF_comp_SHARED) + set(LIEF_NOT_FOUND_MESSAGE + "LIEF `STATIC` and `SHARED` components are mutually exclusive.") + set(LIEF_FOUND FALSE) + return() +endif() + + +# These files are generated by CMake and hold the LIEF library target(s). +set(LIEF_static_export "${CMAKE_CURRENT_LIST_DIR}/LIEFExport-static.cmake") +set(LIEF_shared_export "${CMAKE_CURRENT_LIST_DIR}/LIEFExport-shared.cmake") + +# Fix when cross-compiling for OSX with 'CMAKE_INSTALL_NAME_DIR' +if (APPLE AND (NOT CMAKE_OSX_DEPLOYMENT_TARGET OR + CMAKE_OSX_DEPLOYMENT_TARGET VERSION_GREATER 10.4)) + if(NOT CMAKE_SHARED_LIBRARY_RUNTIME_C_FLAG) + set(CMAKE_SHARED_LIBRARY_RUNTIME_C_FLAG "-Wl,-rpath,") + endif() +endif() + +# Helper macro to load the requested targets, where `lib_type` is `static` or +# `shared` +macro(LIEF_load_targets lib_type) + if(NOT EXISTS "${LIEF_${lib_type}_export}") + set(LIEF_NOT_FOUND_MESSAGE + "LIEF `${lib_type}` libraries were requested but not found.") + set(LIEF_FOUND FALSE) + return() + endif () + + if("${lib_type}" STREQUAL "static") + # Need to find all dependencies even if they're private when LIEF is + # compiled statically + include(CMakeFindDependencyMacro) + + if(@LIEF_EXTERNAL_MBEDTLS@) + find_dependency(MbedTLS 4.0.0 EXACT) + endif() + + if(@LIEF_EXTERNAL_UTF8CPP@) + find_dependency(utf8cpp) + endif() + + if(@LIEF_EXTERNAL_SPDLOG@) + find_dependency(spdlog) + endif() + + if(@LIEF_ENABLE_JSON@ AND @LIEF_NLOHMANN_JSON_EXTERNAL@) + find_dependency(nlohmann_json) + endif() + + if(NOT @LIEF_DISABLE_FROZEN@ AND @LIEF_OPT_FROZEN_EXTERNAL@) + find_dependency(frozen) + endif() + + if(@LIEF_OPT_EXTERNAL_EXPECTED@) + find_dependency(tl-expected) + endif() + + endif() + + # Include the respective targets file + include("${LIEF_${lib_type}_export}") +endmacro() + +# Run the logic to choose static or shared libraries +# 1. Check components +if(LIEF_comp_STATIC) + LIEF_load_targets("static") +elseif(LIEF_comp_SHARED) + LIEF_load_targets("shared") +# 2. Check LIEF-only library selection +elseif(DEFINED LIEF_SHARED_LIBS AND LIEF_SHARED_LIBS) + LIEF_load_targets("shared") +elseif(DEFINED LIEF_SHARED_LIBS AND NOT LIEF_SHARED_LIBS) + LIEF_load_targets("static") +# 3. Check CMake build type and choose what's available +elseif(BUILD_SHARED_LIBS) + if(EXISTS "${LIEF_shared_export}") + LIEF_load_targets("shared") + else() + LIEF_load_targets("static") + endif() +else() + if(EXISTS "${LIEF_static_export}") + LIEF_load_targets("static") + else() + LIEF_load_targets("shared") + endif() +endif() + + +# Attach location of public interface libraries that don't have +# their own CMake config that would otherwise be found using `find_dependency` +# Header-only library can be found relatively easily + +if(@LIEF_EXTERNAL_EXPECTED@) + find_path(TL_EXPECTED_INCLUDE_DIR tl/expected.hpp) + if(NOT TL_EXPECTED_INCLUDE_DIR) + set(LIEF_NOT_FOUND_MESSAGE "Could not find include directory with 'tl/expected.hpp'. Consider setting `TL_EXPECTED_INCLUDE_DIR` during CMake configuration") + set(LIEF_FOUND FALSE) + return() + endif() + set_property(TARGET LIEF::LIEF APPEND PROPERTY + INTERFACE_SYSTEM_INCLUDE_DIRECTORIES "${TL_EXPECTED_INCLUDE_DIR}" + ) +endif() + +if(@LIEF_EXTERNAL_SPAN@) + find_path(TCB_SPAN_INCLUDE_DIR tcb/span.hpp) + if(NOT TCB_SPAN_INCLUDE_DIR) + set(LIEF_NOT_FOUND_MESSAGE "Could not find include directory with 'tcb/span.hpp'. Consider setting `TCB_SPAN_INCLUDE_DIR` during CMake configuration") + set(LIEF_FOUND FALSE) + return() + endif() + set_property(TARGET LIEF::LIEF APPEND PROPERTY + INTERFACE_SYSTEM_INCLUDE_DIRECTORIES "${TCB_SPAN_INCLUDE_DIR}" + ) +endif() + +if(@LIEF_EXTENDED@) + set(LIEF_CORE_EXTENDED TRUE) +else() + set(LIEF_CORE_EXTENDED FALSE) +endif() + +if (@LIEF_RUNTIME@) + set(LIEF_RUNTIME 1) + set(LIEF_RUNTIME_PLATFORM "@LIEF_RUNTIME_PLATFORM@") + set(LIEF_RUNTIME_ARCH "@LIEF_RUNTIME_ARCH@") + set(LIEF_RUNTIME_PLATFORM_LINUX @LIEF_RUNTIME_PLATFORM_LINUX@) + set(LIEF_RUNTIME_PLATFORM_WINDOWS @LIEF_RUNTIME_PLATFORM_WINDOWS@) + set(LIEF_RUNTIME_PLATFORM_ANDROID @LIEF_RUNTIME_PLATFORM_ANDROID@) + set(LIEF_RUNTIME_PLATFORM_OSX @LIEF_RUNTIME_PLATFORM_OSX@) + set(LIEF_RUNTIME_PLATFORM_IOS @LIEF_RUNTIME_PLATFORM_IOS@) + + set(LIEF_RUNTIME_ARCH_ARM64 @LIEF_RUNTIME_ARCH_ARM64@) + set(LIEF_RUNTIME_ARCH_X86_64 @LIEF_RUNTIME_ARCH_X86_64@) + set(LIEF_RUNTIME_ARCH_RISCV64 @LIEF_RUNTIME_ARCH_RISCV64@) +else() + set(LIEF_RUNTIME 0) +endif() + +# Set this for backwards compatibility. This isn't quite the path to the +# actual library file, but using the target is strictly better because it +# includes all other information needed to correctly link and use LIEF +set(LIEF_LIBRARIES LIEF::LIEF) + +# Set this for backwards compatibility +get_target_property(LIEF_INCLUDE_DIRS LIEF::LIEF INTERFACE_INCLUDE_DIRECTORIES) + +# Set the following for backwards compatibility +if(DEFINED LIEF_INCLUDE_DIR) + if(EXISTS "${LIEF_INCLUDE_DIR}/LIEF/version.h") + file(STRINGS "${LIEF_INCLUDE_DIR}/LIEF/version.h" LIEF_H REGEX "^#define LIEF_VERSION \"[^\"]*\"$") + + string(REGEX REPLACE "^.*LIEF_VERSION \"([0-9]+).*$" "\\1" LIEF_VERSION_MAJOR "${LIEF_H}") + string(REGEX REPLACE "^.*LIEF_VERSION \"[0-9]+\\.([0-9]+).*$" "\\1" LIEF_VERSION_MINOR "${LIEF_H}") + string(REGEX REPLACE "^.*LIEF_VERSION \"[0-9]+\\.[0-9]+\\.([0-9]+).*$" "\\1" LIEF_VERSION_PATCH "${LIEF_H}") + set(LIEF_VERSION_STRING "${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}") + + set(LIEF_MAJOR_VERSION "${LIEF_VERSION_MAJOR}") + set(LIEF_MINOR_VERSION "${LIEF_VERSION_MINOR}") + set(LIEF_PATCH_VERSION "${LIEF_VERSION_PATCH}") + endif() +endif() diff --git a/vendor/lief/cmake/LIEFDependencies.cmake b/vendor/lief/cmake/LIEFDependencies.cmake index 27e3412..24a5f50 100644 --- a/vendor/lief/cmake/LIEFDependencies.cmake +++ b/vendor/lief/cmake/LIEFDependencies.cmake @@ -1,25 +1,21 @@ -if(__add_lief_dependencies) - return() -endif() -set(__add_lief_dependencies ON) +include_guard(GLOBAL) + +include(FetchContent) # Json # ---- if(LIEF_ENABLE_JSON) if(NOT LIEF_OPT_NLOHMANN_JSON_EXTERNAL) - set(LIBJSON_VERSION 3.9.1) - set(LIBJSON_SHA256 SHA256=5db3b7b3356a0742e06b27b6ee744f8ee487ed9c0f8cf3f9778a2076e7a933ba) + set(LIBJSON_VERSION 3.12.0) + set(LIBJSON_SHA256 SHA256=6a2249e5d61c2a8351abfac218e08e9a43426dddb493950d30f3b8acfbbc648d) set(LIBJSON_URL "${THIRD_PARTY_DIRECTORY}/json-${LIBJSON_VERSION}.zip" CACHE STRING "URL to the JSON lib repo") - ExternalProject_Add(lief_libjson - URL ${LIBJSON_URL} - URL_HASH ${LIBJSON_SHA256} - UPDATE_COMMAND "" - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_libjson SOURCE_DIR) - set(LIBJSON_SOURCE_DIR "${SOURCE_DIR}") + FetchContent_Declare(lief_libjson + URL ${LIBJSON_URL} + URL_HASH ${LIBJSON_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_libjson) + set(LIBJSON_SOURCE_DIR "${lief_libjson_SOURCE_DIR}") endif() message(STATUS "Enable JSON support") set(ENABLE_JSON_SUPPORT 1) @@ -32,153 +28,167 @@ endif() # mbed TLS # -------- if(NOT LIEF_OPT_MBEDTLS_EXTERNAL) - set(MBED_TLS_VERSION 3.1.0) - set(MBED_TLS_SHA256 SHA256=8ec791eaed8332c50cade2bcc17b75ae5931ac00824a761b5aa4e7586645b72b) - set(MBED_TLS_URL "${THIRD_PARTY_DIRECTORY}/mbedtls-${MBED_TLS_VERSION}.zip" CACHE STRING "URL to MbedTLS") - set(MBED_TLS_PREFIX "${CMAKE_CURRENT_BINARY_DIR}/mbed_tls") - - - ExternalProject_Add(lief_mbed_tls - PREFIX ${MBED_TLS_PREFIX} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - INSTALL_COMMAND "" - URL ${MBED_TLS_URL} - URL_HASH ${MBED_TLS_SHA256} - UPDATE_COMMAND "" # repetitive update are a pain - BUILD_BYPRODUCTS ${MBED_TLS_PREFIX}) - - ExternalProject_get_property(lief_mbed_tls SOURCE_DIR) - set(MBEDTLS_SOURCE_DIR "${SOURCE_DIR}") - set(MBEDTLS_INCLUDE_DIRS "${MBEDTLS_SOURCE_DIR}/include") - - set(mbedtls_src_crypto - "${MBEDTLS_SOURCE_DIR}/library/aes.c" - "${MBEDTLS_SOURCE_DIR}/library/aesni.c" - "${MBEDTLS_SOURCE_DIR}/library/aria.c" - "${MBEDTLS_SOURCE_DIR}/library/asn1parse.c" - "${MBEDTLS_SOURCE_DIR}/library/asn1write.c" - "${MBEDTLS_SOURCE_DIR}/library/base64.c" - "${MBEDTLS_SOURCE_DIR}/library/bignum.c" - "${MBEDTLS_SOURCE_DIR}/library/camellia.c" - "${MBEDTLS_SOURCE_DIR}/library/ccm.c" - "${MBEDTLS_SOURCE_DIR}/library/chacha20.c" - "${MBEDTLS_SOURCE_DIR}/library/chachapoly.c" - "${MBEDTLS_SOURCE_DIR}/library/cipher.c" - "${MBEDTLS_SOURCE_DIR}/library/cipher_wrap.c" - "${MBEDTLS_SOURCE_DIR}/library/constant_time.c" - "${MBEDTLS_SOURCE_DIR}/library/cmac.c" - "${MBEDTLS_SOURCE_DIR}/library/ctr_drbg.c" - "${MBEDTLS_SOURCE_DIR}/library/des.c" - "${MBEDTLS_SOURCE_DIR}/library/dhm.c" - "${MBEDTLS_SOURCE_DIR}/library/ecdh.c" - "${MBEDTLS_SOURCE_DIR}/library/ecdsa.c" - "${MBEDTLS_SOURCE_DIR}/library/ecjpake.c" - "${MBEDTLS_SOURCE_DIR}/library/ecp.c" - "${MBEDTLS_SOURCE_DIR}/library/ecp_curves.c" - "${MBEDTLS_SOURCE_DIR}/library/entropy.c" - "${MBEDTLS_SOURCE_DIR}/library/entropy_poll.c" - "${MBEDTLS_SOURCE_DIR}/library/error.c" - "${MBEDTLS_SOURCE_DIR}/library/gcm.c" - "${MBEDTLS_SOURCE_DIR}/library/hkdf.c" - "${MBEDTLS_SOURCE_DIR}/library/hmac_drbg.c" - "${MBEDTLS_SOURCE_DIR}/library/md.c" - "${MBEDTLS_SOURCE_DIR}/library/md5.c" - "${MBEDTLS_SOURCE_DIR}/library/memory_buffer_alloc.c" - "${MBEDTLS_SOURCE_DIR}/library/mps_reader.c" - "${MBEDTLS_SOURCE_DIR}/library/mps_trace.c" - "${MBEDTLS_SOURCE_DIR}/library/nist_kw.c" - "${MBEDTLS_SOURCE_DIR}/library/oid.c" - "${MBEDTLS_SOURCE_DIR}/library/padlock.c" - "${MBEDTLS_SOURCE_DIR}/library/pem.c" - "${MBEDTLS_SOURCE_DIR}/library/pk.c" - "${MBEDTLS_SOURCE_DIR}/library/pk_wrap.c" - "${MBEDTLS_SOURCE_DIR}/library/pkcs12.c" - "${MBEDTLS_SOURCE_DIR}/library/pkcs5.c" - "${MBEDTLS_SOURCE_DIR}/library/pkparse.c" - "${MBEDTLS_SOURCE_DIR}/library/pkwrite.c" - "${MBEDTLS_SOURCE_DIR}/library/platform.c" - "${MBEDTLS_SOURCE_DIR}/library/platform_util.c" - "${MBEDTLS_SOURCE_DIR}/library/poly1305.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_aead.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_cipher.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_client.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_driver_wrappers.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_ecp.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_hash.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_mac.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_rsa.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_se.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_slot_management.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_crypto_storage.c" - "${MBEDTLS_SOURCE_DIR}/library/psa_its_file.c" - "${MBEDTLS_SOURCE_DIR}/library/ripemd160.c" - "${MBEDTLS_SOURCE_DIR}/library/rsa.c" - "${MBEDTLS_SOURCE_DIR}/library/rsa_alt_helpers.c" - "${MBEDTLS_SOURCE_DIR}/library/sha1.c" - "${MBEDTLS_SOURCE_DIR}/library/sha256.c" - "${MBEDTLS_SOURCE_DIR}/library/sha512.c" - "${MBEDTLS_SOURCE_DIR}/library/ssl_debug_helpers_generated.c" - "${MBEDTLS_SOURCE_DIR}/library/threading.c" - "${MBEDTLS_SOURCE_DIR}/library/timing.c" - "${MBEDTLS_SOURCE_DIR}/library/version.c" - "${MBEDTLS_SOURCE_DIR}/library/version_features.c" + set(MBEDTLS_VERSION 4.0.0.r0.gec4044008d) + set(MBEDTLS_SHA256 SHA256=01aec4471547dec5308853ff0d797611a68a521a10496898b626035dfdc07183) + set(MBEDTLS_URL "${THIRD_PARTY_DIRECTORY}/mbedtls-${MBEDTLS_VERSION}.zip" CACHE STRING "URL to MbedTLS") + FetchContent_Declare(lief_mbedtls + URL ${MBEDTLS_URL} + URL_HASH ${MBEDTLS_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" ) + FetchContent_MakeAvailable(lief_mbedtls) + set(MBEDTLS_SOURCE_DIR "${lief_mbedtls_SOURCE_DIR}") + + set(MBEDTLS_INCLUDE_DIRS) - set(mbedtls_src_x509 - #"${MBEDTLS_SOURCE_DIR}/library/certs.c" - #"${MBEDTLS_SOURCE_DIR}/library/pkcs11.c" - "${MBEDTLS_SOURCE_DIR}/library/x509.c" - "${MBEDTLS_SOURCE_DIR}/library/x509_create.c" - "${MBEDTLS_SOURCE_DIR}/library/x509_crl.c" - "${MBEDTLS_SOURCE_DIR}/library/x509_crt.c" - "${MBEDTLS_SOURCE_DIR}/library/x509_csr.c" - "${MBEDTLS_SOURCE_DIR}/library/x509write_crt.c" - "${MBEDTLS_SOURCE_DIR}/library/x509write_csr.c" + list(APPEND MBEDTLS_INCLUDE_DIRS + "${MBEDTLS_SOURCE_DIR}/include" + "${MBEDTLS_SOURCE_DIR}/library" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/include" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/include" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/include/tf-psa-crypto/private/everest" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/include/tf-psa-crypto/private/everest/kremlib" ) - set(mbedtls_src_tls + set(mbedtls_src_files "${MBEDTLS_SOURCE_DIR}/library/debug.c" + #"${MBEDTLS_SOURCE_DIR}/library/mbedtls_config.c" + "${MBEDTLS_SOURCE_DIR}/library/mps_reader.c" + "${MBEDTLS_SOURCE_DIR}/library/mps_trace.c" "${MBEDTLS_SOURCE_DIR}/library/net_sockets.c" + "${MBEDTLS_SOURCE_DIR}/library/pkcs7.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_cache.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_ciphersuites.c" - "${MBEDTLS_SOURCE_DIR}/library/ssl_cli.c" + "${MBEDTLS_SOURCE_DIR}/library/ssl_client.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_cookie.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_msg.c" - "${MBEDTLS_SOURCE_DIR}/library/ssl_srv.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_ticket.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_tls.c" - "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_keys.c" - "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_server.c" + "${MBEDTLS_SOURCE_DIR}/library/ssl_tls12_client.c" + "${MBEDTLS_SOURCE_DIR}/library/ssl_tls12_server.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_client.c" "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_generic.c" + "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_keys.c" + "${MBEDTLS_SOURCE_DIR}/library/ssl_tls13_server.c" + "${MBEDTLS_SOURCE_DIR}/library/timing.c" + "${MBEDTLS_SOURCE_DIR}/library/version.c" + "${MBEDTLS_SOURCE_DIR}/library/error.c" + "${MBEDTLS_SOURCE_DIR}/library/x509.c" + "${MBEDTLS_SOURCE_DIR}/library/x509_create.c" + "${MBEDTLS_SOURCE_DIR}/library/x509_crl.c" + "${MBEDTLS_SOURCE_DIR}/library/x509_crt.c" + "${MBEDTLS_SOURCE_DIR}/library/x509_csr.c" + "${MBEDTLS_SOURCE_DIR}/library/x509_oid.c" + "${MBEDTLS_SOURCE_DIR}/library/x509write.c" + "${MBEDTLS_SOURCE_DIR}/library/x509write_crt.c" + "${MBEDTLS_SOURCE_DIR}/library/x509write_csr.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_crypto.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_crypto_client.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_crypto_slot_management.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_crypto_storage.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_its_file.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/tf_psa_crypto_config.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/tf_psa_crypto_version.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/core/psa_crypto_driver_wrappers_no_static.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/aes.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/aesce.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/aesni.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/aria.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/asn1parse.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/asn1write.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/base64.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/bignum.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/bignum_core.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/bignum_mod.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/bignum_mod_raw.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/block_cipher.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/camellia.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ccm.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/chacha20.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/chachapoly.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/cipher.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/cipher_wrap.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/cmac.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/constant_time.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ctr_drbg.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecdh.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecdsa.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecjpake.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecp.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecp_curves.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ecp_curves_new.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/entropy.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/entropy_poll.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/gcm.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/hmac_drbg.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/lmots.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/lms.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/md.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/md5.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/memory_buffer_alloc.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/nist_kw.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/oid.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pem.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pk.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pk_ecc.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pk_rsa.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pk_wrap.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pkcs5.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pkparse.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/pkwrite.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/platform.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/platform_util.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/poly1305.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_aead.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_cipher.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_ecp.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_ffdh.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_hash.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_mac.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_pake.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_crypto_rsa.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/psa_util.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/ripemd160.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/rsa.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/rsa_alt_helpers.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/sha1.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/sha256.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/sha3.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/sha512.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/builtin/src/threading.c" + + #"${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/library/Hacl_Curve25519.c" + #"${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/library/Hacl_Curve25519_joined.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/library/everest.c" + #"${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/library/legacy/Hacl_Curve25519.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/everest/library/x25519.c" + + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/p256-m/p256-m/p256-m.c" + "${MBEDTLS_SOURCE_DIR}/tf-psa-crypto/drivers/p256-m/p256-m_driver_entrypoints.c" ) endif() add_library(lief_spdlog INTERFACE) if(LIEF_EXTERNAL_SPDLOG) - find_package(spdlog REQUIRED) + find_package(spdlog 1.17.0 REQUIRED) list(APPEND CMAKE_MODULE_PATH "${SPDLOG_DIR}/cmake") target_link_libraries(lief_spdlog INTERFACE spdlog::spdlog) get_target_property(SPDLOG_INC_DIR spdlog::spdlog INTERFACE_INCLUDE_DIRECTORIES) target_include_directories(lief_spdlog SYSTEM INTERFACE ${SPDLOG_INC_DIR}) else() - set(SPDLOG_VERSION 1.10.0) - set(SPDLOG_SHA256 SHA256=7be28ff05d32a8a11cfba94381e820dd2842835f7f319f843993101bcab44b66) + set(SPDLOG_VERSION 1.17.0) + set(SPDLOG_SHA256 SHA256=b11912a82d149792fef33fabd0503b13d54aeac25c1464755461d4108ea71fc2) set(SPDLOG_URL "${THIRD_PARTY_DIRECTORY}/spdlog-${SPDLOG_VERSION}.zip" CACHE STRING "URL to the spdlog source") - ExternalProject_Add(lief_spdlog_project - URL ${SPDLOG_URL} - URL_HASH ${SPDLOG_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - UPDATE_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_spdlog_project SOURCE_DIR) - set(SPDLOG_SOURCE_DIR "${SOURCE_DIR}") - add_dependencies(lief_spdlog lief_spdlog_project) + FetchContent_Declare(lief_spdlog_project + URL ${SPDLOG_URL} + URL_HASH ${SPDLOG_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_spdlog_project) + set(SPDLOG_SOURCE_DIR "${lief_spdlog_project_SOURCE_DIR}") target_include_directories(lief_spdlog SYSTEM INTERFACE "$") endif() @@ -191,73 +201,62 @@ if (LIEF_SUPPORT_CXX14 AND NOT LIEF_DISABLE_FROZEN) set(LIEF_FROZEN_ENABLED 1) if (NOT LIEF_OPT_FROZEN_EXTERNAL) - set(FROZEN_VERSION e6ddc43) - set(FROZEN_SHA256 SHA256=7aa0ab44eb91fc2c2431bd2e78bd3545aae750793a880064f6df0ef84c819065) + set(FROZEN_VERSION 61dce5a) + set(FROZEN_SHA256 SHA256=c94ba33d5369749e8d8ba12fb87d60de02ddac981051383a8d321968abb6a314) set(FROZEN_URL "${THIRD_PARTY_DIRECTORY}/frozen-${FROZEN_VERSION}.zip" CACHE STRING "URL to Frozen") - ExternalProject_Add(lief_frozen - URL ${FROZEN_URL} - URL_HASH ${FROZEN_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - UPDATE_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_frozen SOURCE_DIR) - set(FROZEN_INCLUDE_DIR "${SOURCE_DIR}/include") + FetchContent_Declare(lief_frozen + URL ${FROZEN_URL} + URL_HASH ${FROZEN_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_frozen) + set(FROZEN_INCLUDE_DIR "${lief_frozen_SOURCE_DIR}/include") endif() endif() - -# Boost leaf +# expected # ---------- -if(NOT LIEF_EXTERNAL_LEAF) - set(LEAF_VERSION a781140) - set(LEAF_SHA256 SHA256=af980c4b5288dd78f4ac47b42899cfeb47b335cd3191f8b3cd95b67be419b941) - set(LEAF_URL "${THIRD_PARTY_DIRECTORY}/leaf-${LEAF_VERSION}.zip" CACHE STRING "URL to Leaf") - ExternalProject_Add(lief_leaf # :) - URL ${LEAF_URL} - URL_HASH ${LEAF_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - UPDATE_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_leaf SOURCE_DIR) - set(LEAF_SRC_DIR "${SOURCE_DIR}") +if(NOT LIEF_EXTERNAL_EXPECTED) + set(EXPECTED_VERSION 1.3.1) + set(EXPECTED_SHA256 SHA256=68bbfd81a6d312c4518b5a1831f465fa03811355af9aa9c7403348545d1d2a56) + set(EXPECTED_URL "${THIRD_PARTY_DIRECTORY}/expected-${EXPECTED_VERSION}.zip" CACHE STRING "URL to Expected") + set(EXPECTED_BUILD_TESTS OFF) + set(EXPECTED_BUILD_PACKAGE OFF) + FetchContent_Declare(lief_expected + URL ${EXPECTED_URL} + URL_HASH ${EXPECTED_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_expected) + set(EXPECTED_SRC_DIR "${lief_expected_SOURCE_DIR}") endif() # utfcpp # ------ if(NOT LIEF_OPT_UTFCPP_EXTERNAL) - set(UTFCPP_VERSION 3.1.2) # Custom fix to remove use of SUBLANG_DEFAULT in common.hpp and all.hpp - set(UTFCPP_SHA256 SHA256=b77bff122a6d4f2a7a1ab409086bbb59bf899a2fdde12e1a85a4305fa91764c4) + set(UTFCPP_VERSION 4.0.9) + set(UTFCPP_SHA256 SHA256=73802895d0cf7b000cdf8e6ee5d69b963a829d4ea419562afd8f190adef87d5f) set(UTFCPP_URL "${THIRD_PARTY_DIRECTORY}/utfcpp-${UTFCPP_VERSION}.zip" CACHE STRING "URL to UTFCPP") - ExternalProject_Add(lief_utfcpp - URL ${UTFCPP_URL} - URL_HASH ${UTFCPP_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - UPDATE_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_utfcpp SOURCE_DIR) - set(UTFCPP_INCLUDE_DIR "${SOURCE_DIR}/source") + FetchContent_Declare(lief_utfcpp + URL ${UTFCPP_URL} + URL_HASH ${UTFCPP_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_utfcpp) + set(UTFCPP_INCLUDE_DIR "${lief_utfcpp_SOURCE_DIR}/source") endif() # https://github.com/tcbrindle/span # --------------------------------- if(NOT LIEF_EXTERNAL_SPAN) - set(TCB_SPAN_VERSION 427f6bd) - set(TCB_SPAN_SHA256 SHA256=3fde1bb8be41da080d10ad18b3b7a6b1045349dc8ae64fc4380b977478ec68d3) + set(TCB_SPAN_VERSION b70b0ff) + set(TCB_SPAN_SHA256 SHA256=f3d47ed83507fce94245a9f3cf97bc433cd1116f94d11ac0dca1a6f53bbeb239) set(TCB_SPAN_URL "${THIRD_PARTY_DIRECTORY}/tcb-span-${TCB_SPAN_VERSION}.zip" CACHE STRING "URL to tcb/span") - ExternalProject_Add(lief_span - URL ${TCB_SPAN_URL} - URL_HASH ${TCB_SPAN_SHA256} - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - UPDATE_COMMAND "" - INSTALL_COMMAND "") - - ExternalProject_get_property(lief_span SOURCE_DIR) - set(TCB_SPAN_SRC_DIR "${SOURCE_DIR}") + FetchContent_Declare(lief_span + URL ${TCB_SPAN_URL} + URL_HASH ${TCB_SPAN_SHA256} + SOURCE_SUBDIR "__DO_NOT_BUILD__" + ) + FetchContent_MakeAvailable(lief_span) + set(TCB_SPAN_SRC_DIR "${lief_span_SOURCE_DIR}") endif() diff --git a/vendor/lief/cmake/LIEFGit.cmake b/vendor/lief/cmake/LIEFGit.cmake index 5462886..42ed8d8 100644 --- a/vendor/lief/cmake/LIEFGit.cmake +++ b/vendor/lief/cmake/LIEFGit.cmake @@ -1,7 +1,4 @@ -if(__add_lief_git) - return() -endif() -set(__add_lief_git ON) +include_guard(GLOBAL) execute_process( @@ -44,28 +41,38 @@ string(COMPARE NOTEQUAL "${LIEF_GIT_COMMIT_TAGGED}" "" LIEF_IS_TAGGED) string(REGEX MATCHALL "([0-9]+)" VERSION_STRING "${LIEF_GIT_TAG}") message(STATUS "Tagged: ${LIEF_IS_TAGGED}") -if (${LIEF_IS_TAGGED}) +if (LIEF_IS_TAGGED) message(STATUS "Tag: ${LIEF_GIT_TAG}") else() - if(LIEF_GIT_BRANCH MATCHES "^release-") + if(LIEF_GIT_BRANCH MATCHES "^release[-/]") string(REGEX MATCHALL "([0-9]+)" VERSION_STRING "${LIEF_GIT_BRANCH}") message(STATUS "${VERSION_STRING}") endif() endif() message(STATUS "Current branch: ${LIEF_GIT_BRANCH}") - if (VERSION_STRING) + list(LENGTH VERSION_STRING VERSION_STRING_LEN) list(GET VERSION_STRING 0 LIEF_VERSION_MAJOR) list(GET VERSION_STRING 1 LIEF_VERSION_MINOR) - list(GET VERSION_STRING 2 LIEF_VERSION_PATCH) + if (VERSION_STRING_LEN GREATER 2) + list(GET VERSION_STRING 2 LIEF_VERSION_PATCH) + else() + set(LIEF_VERSION_PATCH 0) + endif() - if (NOT ${LIEF_IS_TAGGED}) - if(LIEF_GIT_BRANCH MATCHES "^release-") + if (NOT LIEF_IS_TAGGED) + if(LIEF_GIT_BRANCH MATCHES "^release[-/]") message(STATUS "Release branch") else() - MATH(EXPR LIEF_VERSION_MINOR "${LIEF_VERSION_MINOR}+1") - set(LIEF_VERSION_PATCH 0) + if (LIEF_VERSION_MINOR EQUAL 17) + set(LIEF_VERSION_MAJOR 1) + set(LIEF_VERSION_MINOR 0) + set(LIEF_VERSION_PATCH 0) + else() + MATH(EXPR LIEF_VERSION_MINOR "${LIEF_VERSION_MAJOR}+1") + set(LIEF_VERSION_PATCH 0) + endif() endif() endif() else() @@ -73,4 +80,3 @@ else() set(LIEF_VERSION_MINOR 0) set(LIEF_VERSION_PATCH 0) endif() - diff --git a/vendor/lief/cmake/LIEFOptions.cmake b/vendor/lief/cmake/LIEFOptions.cmake index 5845edd..2fcb069 100644 --- a/vendor/lief/cmake/LIEFOptions.cmake +++ b/vendor/lief/cmake/LIEFOptions.cmake @@ -1,35 +1,72 @@ -if(__add_lief_options) - return() -endif() -set(__add_lief_options ON) +include_guard(GLOBAL) include(CMakeDependentOption) option(LIEF_TESTS "Enable tests" OFF) -option(LIEF_DOC "Enable documentation" OFF) option(LIEF_PYTHON_API "Enable Python Bindings" OFF) -option(LIEF_C_API "C API" ON) option(LIEF_EXAMPLES "Build LIEF C++ examples" ON) option(LIEF_FORCE32 "Force build LIEF 32 bits version" OFF) -option(LIEF_COVERAGE "Perform code coverage" OFF) option(LIEF_USE_CCACHE "Use ccache to speed up compilation" ON) option(LIEF_EXTRA_WARNINGS "Enable extra warning from the compiler" OFF) option(LIEF_LOGGING "Enable logging" ON) option(LIEF_LOGGING_DEBUG "Enable debug logging" ON) option(LIEF_ENABLE_JSON "Enable JSON-related APIs" ON) -option(LIEF_OPT_NLOHMANN_JSON_EXTERNAL "Use nlohmann/json externaly" OFF) +option(LIEF_OPT_NLOHMANN_JSON_EXTERNAL "Use nlohmann/json externally" OFF) option(LIEF_FORCE_API_EXPORTS "Force exports of API symbols" OFF) +option(LIEF_PY_LIEF_EXT "Use a pre-installed version of LIEF for the bindings" OFF) +option(LIEF_PRECOMPILED "Use a pre-compiled version of LIEF" OFF) +option(LIEF_RUST_API "Generate the C++ bridge for Rust's cxx" OFF) +option(LIEF_DISABLE_EXCEPTIONS "Disable C++ exceptions on the core library" ON) +option(LIEF_SO_VERSION "Embed versioning for LIEF shared library target" OFF) +option(LIEF_COMPILE_DOC_EXAMPLES "Compile C++ examples in doc/code/" OFF) option(LIEF_DISABLE_FROZEN "Disable Frozen even if it is supported" OFF) +option(LIEF_RUNTIME "Enable runtime features" OFF) option(LIEF_ELF "Build LIEF with ELF module" ON) -option(LIEF_PE "Build LIEF with PE module" ON) +option(LIEF_PE "Build LIEF with PE module" ON) +option(LIEF_COFF "Build LIEF with COFF module" ON) option(LIEF_MACHO "Build LIEF with MachO module" ON) option(LIEF_DEX "Build LIEF with DEX module" ON) option(LIEF_ART "Build LIEF with ART module" ON) +# Extended features +option(LIEF_DEBUG_INFO "Build LIEF with DWARF/PDB support" OFF) +option(LIEF_OBJC "Build LIEF with ObjC metadata support" OFF) +option(LIEF_DYLD_SHARED_CACHE "Build LIEF with Dyld shared cache support" OFF) +option(LIEF_ASM "Build LIEF with assembler/disassembler support" OFF) +option(LIEF_RUNTIME_EXTENDED "Build LIEF with assembler/disassembler support" OFF) + +if (LIEF_COFF AND NOT LIEF_PE) + message(FATAL_ERROR "COFF module requires LIEF_PE enabled") +endif() + +if (LIEF_PE AND NOT LIEF_COFF) + message(FATAL_ERROR "PE module requires LIEF_COFF enabled") +endif() + +if (LIEF_PY_LIEF_EXT) + set(LIEF_PRECOMPILED ON) +endif() + +cmake_dependent_option(LIEF_PYTHON_EDITABLE "Make an editable build " OFF + "LIEF_PYTHON_API" OFF) + +cmake_dependent_option(LIEF_PY_LIEF_EXT_SHARED + "Use a 'SHARED' version of LIEF instead of a static one" OFF + "LIEF_PY_LIEF_EXT" OFF) + +cmake_dependent_option(LIEF_PYTHON_STATIC "Internal usage" OFF + "LIEF_PYTHON_API" OFF) + +cmake_dependent_option(LIEF_PYTHON_STABLE_ABI "Compile LIEF Python bindings with the stable ABI" OFF + "LIEF_PYTHON_API" OFF) + +cmake_dependent_option(LIEF_PYTHON_FREE_THREADED "Compile LIEF Python bindings with free-threading enabled" OFF + "LIEF_PYTHON_API" OFF) + # OAT support relies on the ELF and DEX format. -# Therefore, these options must be enabled to support use this format +# Therefore, these options must be enabled to support this format cmake_dependent_option(LIEF_OAT "Build LIEF with OAT module" ON "LIEF_ELF;LIEF_DEX" OFF) @@ -49,6 +86,11 @@ option(LIEF_FUZZING "Fuzz LIEF" OFF) # Profiling option(LIEF_PROFILING "Enable performance profiling" OFF) +# QA / Linters +option(LIEF_CLANG_TIDY "Enable clang-tidy checks" OFF) +cmake_dependent_option(LIEF_CLANG_TIDY_WARN_ERR + "Enable WarningsAsErrors when running clang-tidy" OFF "LIEF_CLANG_TIDY" OFF) + # Install options cmake_dependent_option(LIEF_INSTALL_COMPILED_EXAMPLES "Install LIEF Compiled examples" OFF "LIEF_EXAMPLES" OFF) @@ -58,9 +100,8 @@ cmake_dependent_option(LIEF_INSTALL_COMPILED_EXAMPLES "Install LIEF Compiled exa option(LIEF_EXTERNAL_SPDLOG OFF) # This option enables to provide an external -# version of Boost Leaf (e.g. present on the system) -option(LIEF_OPT_EXTERNAL_LEAF OFF) -set(LIEF_EXTERNAL_LEAF_DIR ) +# version of TartanLlama/expected (e.g. present on the system) +option(LIEF_OPT_EXTERNAL_EXPECTED OFF) # This option enables to provide an external version of utf8cpp option(LIEF_OPT_UTFCPP_EXTERNAL OFF) @@ -68,8 +109,8 @@ option(LIEF_OPT_UTFCPP_EXTERNAL OFF) # This option enables to provide an external version of MbedTLS option(LIEF_OPT_MBEDTLS_EXTERNAL OFF) -# This option enables to provide an external version of pybind11 -option(LIEF_OPT_PYBIND11_EXTERNAL OFF) +# This option enables to provide an external version of nanobind +option(LIEF_OPT_NANOBIND_EXTERNAL OFF) # This option enables to provide an external # version of https://github.com/tcbrindle/span (e.g. present on the system) @@ -81,13 +122,21 @@ set(_LIEF_USE_FROZEN ON) if(LIEF_DISABLE_FROZEN) set(_LIEF_USE_FROZEN OFF) endif() + cmake_dependent_option(LIEF_OPT_FROZEN_EXTERNAL "Use an external provided version of Frozen" OFF "_LIEF_USE_FROZEN" OFF) +option(LIEF_USE_MELKOR "Build Melkor for testing" ON) + +# This option enables the install target in the cmake +option(LIEF_INSTALL "Generate the install target." ON) +set(LIEF_RUNTIME_SUPPORT 0) + set(LIEF_ELF_SUPPORT 0) set(LIEF_PE_SUPPORT 0) set(LIEF_MACHO_SUPPORT 0) +set(LIEF_COFF_SUPPORT 0) set(LIEF_OAT_SUPPORT 0) set(LIEF_DEX_SUPPORT 0) set(LIEF_VDEX_SUPPORT 0) @@ -100,11 +149,21 @@ set(LIEF_LOGGING_DEBUG_SUPPORT 0) set(LIEF_FROZEN_ENABLED 0) set(LIEF_EXTERNAL_FROZEN 0) -set(LIEF_EXTERNAL_LEAF 0) +set(LIEF_EXTERNAL_EXPECTED 0) set(LIEF_EXTERNAL_UTF8CPP 0) set(LIEF_EXTERNAL_MBEDTLS 0) set(LIEF_EXTERNAL_SPAN 0) +set(LIEF_DEBUG_INFO_SUPPORT 0) +set(LIEF_OBJC_SUPPORT 0) +set(LIEF_DYLD_SHARED_CACHE_SUPPORT 0) +set(LIEF_ASM_SUPPORT 0) +set(LIEF_EXTENDED 0) + +if(LIEF_RUNTIME) + set(LIEF_RUNTIME_SUPPORT 1) +endif() + if(LIEF_ELF) set(LIEF_ELF_SUPPORT 1) endif() @@ -117,6 +176,10 @@ if(LIEF_MACHO) set(LIEF_MACHO_SUPPORT 1) endif() +if(LIEF_COFF) + set(LIEF_COFF_SUPPORT 1) +endif() + if(LIEF_OAT) set(LIEF_OAT_SUPPORT 1) endif() @@ -156,8 +219,8 @@ if(NOT LIEF_DISABLE_FROZEN) endif() endif() -if(LIEF_OPT_EXTERNAL_LEAF) - set(LIEF_EXTERNAL_LEAF 1) +if(LIEF_OPT_EXTERNAL_EXPECTED) + set(LIEF_EXTERNAL_EXPECTED 1) endif() if(LIEF_OPT_UTFCPP_EXTERNAL) @@ -173,8 +236,42 @@ if(LIEF_OPT_EXTERNAL_SPAN) endif() if(LIEF_PYTHON_API) - if(LIEF_OPT_PYBIND11_EXTERNAL) - set(LIEF_EXTERNAL_PYBIND11 1) + if(LIEF_OPT_NANOBIND_EXTERNAL) + set(LIEF_EXTERNAL_NANOBIND 1) endif() endif() +# ------------------------------------------------------------------------------ +# Extended features +# ------------------------------------------------------------------------------ +if (LIEF_DEBUG_INFO) + set(LIEF_DEBUG_INFO_SUPPORT 1) +endif() + +if (LIEF_OBJC) + set(LIEF_OBJC_SUPPORT 1) +endif() + +if (LIEF_DYLD_SHARED_CACHE) + set(LIEF_DYLD_SHARED_CACHE_SUPPORT 1) +endif() + +if (LIEF_ASM) + set(LIEF_ASM_SUPPORT 1) +endif() + +if (LIEF_RUNTIME_EXTENDED) + set(LIEF_RUNTIME_EXTENDED_SUPPORT 1) +endif() + +if (LIEF_DEBUG_INFO OR + LIEF_OBJC OR + LIEF_DYLD_SHARED_CACHE OR + LIEF_ASM OR + LIEF_RUNTIME_EXTENDED) # or any other extended feature + set(LIEF_EXTENDED 1) +endif() + +if (LIEF_RUNTIME) + include(LIEFRuntime) +endif() diff --git a/vendor/lief/cmake/LIEFRuntime.cmake b/vendor/lief/cmake/LIEFRuntime.cmake new file mode 100644 index 0000000..de5e569 --- /dev/null +++ b/vendor/lief/cmake/LIEFRuntime.cmake @@ -0,0 +1,62 @@ +include_guard(GLOBAL) + +set(LIEF_RUNTIME_SUPPORTED_PLATFORMS "linux" "windows" "android" "ios" "osx") +set(LIEF_RUNTIME_SUPPORTED_ARCH "x86_64" "arm64" "riscv64") + +set(LIEF_RUNTIME_PLATFORM_LINUX 0) +set(LIEF_RUNTIME_PLATFORM_WINDOWS 0) +set(LIEF_RUNTIME_PLATFORM_ANDROID 0) +set(LIEF_RUNTIME_PLATFORM_OSX 0) +set(LIEF_RUNTIME_PLATFORM_IOS 0) + +set(LIEF_RUNTIME_ARCH_ARM64 0) +set(LIEF_RUNTIME_ARCH_X86_64 0) +set(LIEF_RUNTIME_ARCH_RISCV64 0) + +if(NOT DEFINED LIEF_RUNTIME_PLATFORM) + message(FATAL_ERROR + "'LIEF_RUNTIME_PLATFORM' is not set.\n Supported platforms: ${LIEF_RUNTIME_SUPPORTED_PLATFORMS}" + ) +endif() + +if (LIEF_RUNTIME_PLATFORM STREQUAL "linux") + set(LIEF_RUNTIME_PLATFORM_LINUX 1) +elseif (LIEF_RUNTIME_PLATFORM STREQUAL "windows") + set(LIEF_RUNTIME_PLATFORM_WINDOWS 1) +elseif (LIEF_RUNTIME_PLATFORM STREQUAL "osx") + set(LIEF_RUNTIME_PLATFORM_OSX 1) +elseif (LIEF_RUNTIME_PLATFORM STREQUAL "ios") + set(LIEF_RUNTIME_PLATFORM_IOS 1) +elseif (LIEF_RUNTIME_PLATFORM STREQUAL "android") + set(LIEF_RUNTIME_PLATFORM_ANDROID 1) +else() + message(FATAL_ERROR + "'${LIEF_RUNTIME_PLATFORM}' is not a valid platform.\n Supported platforms: ${LIEF_RUNTIME_SUPPORTED_PLATFORMS}" + ) +endif() + +if(NOT DEFINED LIEF_RUNTIME_ARCH) + message( + FATAL_ERROR + "'LIEF_RUNTIME_ARCH' is not set.\n Supported architectures: ${LIEF_RUNTIME_SUPPORTED_ARCH}" + ) +endif() + +if (LIEF_RUNTIME_ARCH STREQUAL "x86_64") + set(LIEF_RUNTIME_ARCH_X86_64 1) +elseif (LIEF_RUNTIME_ARCH MATCHES "(arm64|aarch64)") + set(LIEF_RUNTIME_ARCH_ARM64 1) +elseif (LIEF_RUNTIME_ARCH STREQUAL "riscv64") + set(LIEF_RUNTIME_ARCH_RISCV64 1) +else() + message(FATAL_ERROR + "'${LIEF_RUNTIME_ARCH}' is not a valid architecture.\n Supported platforms: ${LIEF_RUNTIME_SUPPORTED_ARCH}" + ) +endif() + +if (LIEF_RUNTIME_PLATFORM_OSX OR LIEF_RUNTIME_PLATFORM_IOS) + enable_language(OBJCXX) +endif() + +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/include/LIEF/runtime/config.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/include/LIEF/runtime/config.h" @ONLY) diff --git a/vendor/lief/cmake/ios.toolchain.cmake b/vendor/lief/cmake/ios.toolchain.cmake deleted file mode 100644 index de5aa44..0000000 --- a/vendor/lief/cmake/ios.toolchain.cmake +++ /dev/null @@ -1,740 +0,0 @@ -# This file is part of the ios-cmake project. It was retrieved from -# https://github.com/gerstrong/ios-cmake.git which is a fork of -# https://github.com/cristeab/ios-cmake.git, which again is a fork of -# https://code.google.com/p/ios-cmake/. Which in turn is based off of -# the Platform/Darwin.cmake and Platform/UnixPaths.cmake files which -# are included with CMake 2.8.4 -# -# The ios-cmake project is licensed under the new BSD license. -# -# Copyright (c) 2014, Bogdan Cristea and LTE Engineering Software, -# Kitware, Inc., Insight Software Consortium. All rights reserved. -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -# This file is based off of the Platform/Darwin.cmake and -# Platform/UnixPaths.cmake files which are included with CMake 2.8.4 -# It has been altered for iOS development. -# -# Updated by Alex Stewart (alexs.mac@gmail.com) -# -# ***************************************************************************** -# Now maintained by Alexander Widerberg (widerbergaren [at] gmail.com) -# under the BSD-3-Clause license -# https://github.com/leetal/ios-cmake -# ***************************************************************************** -# -# INFORMATION / HELP -# -# The following arguments control the behaviour of this toolchain: -# -# PLATFORM: (default "OS") -# OS = Build for iPhoneOS. -# OS64 = Build for arm64 iphoneOS. -# OS64COMBINED = Build for arm64 x86_64 iphoneOS. Combined into FAT STATIC lib (supported on 3.14+ of CMakewith "-G Xcode" argument ONLY) -# SIMULATOR = Build for x86 i386 iphoneOS Simulator. -# SIMULATOR64 = Build for x86_64 iphoneOS Simulator. -# TVOS = Build for arm64 tvOS. -# TVOSCOMBINED = Build for arm64 x86_64 tvOS. Combined into FAT STATIC lib (supported on 3.14+ of CMake with "-G Xcode" argument ONLY) -# SIMULATOR_TVOS = Build for x86_64 tvOS Simulator. -# WATCHOS = Build for armv7k arm64_32 for watchOS. -# WATCHOSCOMBINED = Build for armv7k arm64_32 x86_64 watchOS. Combined into FAT STATIC lib (supported on 3.14+ of CMake with "-G Xcode" argument ONLY) -# SIMULATOR_WATCHOS = Build for x86_64 for watchOS Simulator. -# -# CMAKE_OSX_SYSROOT: Path to the SDK to use. By default this is -# automatically determined from PLATFORM and xcodebuild, but -# can also be manually specified (although this should not be required). -# -# CMAKE_DEVELOPER_ROOT: Path to the Developer directory for the platform -# being compiled for. By default this is automatically determined from -# CMAKE_OSX_SYSROOT, but can also be manually specified (although this should -# not be required). -# -# DEPLOYMENT_TARGET: Minimum SDK version to target. Default 2.0 on watchOS and 9.0 on tvOS+iOS -# -# ENABLE_BITCODE: (1|0) Enables or disables bitcode support. Default 1 (true) -# -# ENABLE_ARC: (1|0) Enables or disables ARC support. Default 1 (true, ARC enabled by default) -# -# ENABLE_VISIBILITY: (1|0) Enables or disables symbol visibility support. Default 0 (false, visibility hidden by default) -# -# ENABLE_STRICT_TRY_COMPILE: (1|0) Enables or disables strict try_compile() on all Check* directives (will run linker -# to actually check if linking is possible). Default 0 (false, will set CMAKE_TRY_COMPILE_TARGET_TYPE to STATIC_LIBRARY) -# -# ARCHS: (armv7 armv7s armv7k arm64 arm64_32 i386 x86_64) If specified, will override the default architectures for the given PLATFORM -# OS = armv7 armv7s arm64 (if applicable) -# OS64 = arm64 (if applicable) -# SIMULATOR = i386 -# SIMULATOR64 = x86_64 -# TVOS = arm64 -# SIMULATOR_TVOS = x86_64 (i386 has since long been deprecated) -# WATCHOS = armv7k arm64_32 (if applicable) -# SIMULATOR_WATCHOS = x86_64 (i386 has since long been deprecated) -# -# This toolchain defines the following variables for use externally: -# -# XCODE_VERSION: Version number (not including Build version) of Xcode detected. -# SDK_VERSION: Version of SDK being used. -# CMAKE_OSX_ARCHITECTURES: Architectures being compiled for (generated from PLATFORM). -# APPLE_TARGET_TRIPLE: Used by autoconf build systems. NOTE: If "ARCHS" are overridden, this will *NOT* be set! -# -# This toolchain defines the following macros for use externally: -# -# set_xcode_property (TARGET XCODE_PROPERTY XCODE_VALUE XCODE_VARIANT) -# A convenience macro for setting xcode specific properties on targets. -# Available variants are: All, Release, RelWithDebInfo, Debug, MinSizeRel -# example: set_xcode_property (myioslib IPHONEOS_DEPLOYMENT_TARGET "3.1" "all"). -# -# find_host_package (PROGRAM ARGS) -# A macro used to find executable programs on the host system, not within the -# environment. Thanks to the android-cmake project for providing the -# command. -# -# ******************************** DEPRECATIONS ******************************* -# -# IOS_DEPLOYMENT_TARGET: (Deprecated) Alias to DEPLOYMENT_TARGET -# CMAKE_IOS_DEVELOPER_ROOT: (Deprecated) Alias to CMAKE_DEVELOPER_ROOT -# IOS_PLATFORM: (Deprecated) Alias to PLATFORM -# IOS_ARCH: (Deprecated) Alias to ARCHS -# -# ***************************************************************************** -# - -# Fix for PThread library not in path -set(CMAKE_THREAD_LIBS_INIT "-lpthread") -set(CMAKE_HAVE_THREADS_LIBRARY 1) -set(CMAKE_USE_WIN32_THREADS_INIT 0) -set(CMAKE_USE_PTHREADS_INIT 1) - -# Cache what generator is used -set(USED_CMAKE_GENERATOR "${CMAKE_GENERATOR}" CACHE STRING "Expose CMAKE_GENERATOR" FORCE) - -if(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14") - set(MODERN_CMAKE YES) -endif() - -# Get the Xcode version being used. -execute_process(COMMAND xcodebuild -version - OUTPUT_VARIABLE XCODE_VERSION - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) -string(REGEX MATCH "Xcode [0-9\\.]+" XCODE_VERSION "${XCODE_VERSION}") -string(REGEX REPLACE "Xcode ([0-9\\.]+)" "\\1" XCODE_VERSION "${XCODE_VERSION}") - -# Assuming that xcode 12.0 is installed you most probably have ios sdk 14.2 or later installed (tested on Big Sur) -# if you don't set a deployment target it will be set the way you only get 64-bit builds -if(NOT DEFINED DEPLOYMENT_TARGET AND XCODE_VERSION VERSION_GREATER 12.0) - option(DROP_32_BIT "Will make drop 32-bit support universally. On later sdks you won't be able to build 32-bit apps" yes) - # Temporarily fix the arm64 issues in CMake install-combined by excluding arm64 for simulator builds (needed for Apple Silicon...) - set(CMAKE_XCODE_ATTRIBUTE_EXCLUDED_ARCHS[sdk=iphonesimulator*] "arm64") -endif() - -######## ALIASES (DEPRECATION WARNINGS) - -if(DEFINED IOS_PLATFORM) - set(PLATFORM ${IOS_PLATFORM}) - message(DEPRECATION "IOS_PLATFORM argument is DEPRECATED. Consider using the new PLATFORM argument instead.") -endif() - -if(DEFINED IOS_DEPLOYMENT_TARGET) - set(DEPLOYMENT_TARGET ${IOS_DEPLOYMENT_TARGET}) - message(DEPRECATION "IOS_DEPLOYMENT_TARGET argument is DEPRECATED. Consider using the new DEPLOYMENT_TARGET argument instead.") -endif() - -if(DEFINED CMAKE_IOS_DEVELOPER_ROOT) - set(CMAKE_DEVELOPER_ROOT ${CMAKE_IOS_DEVELOPER_ROOT}) - message(DEPRECATION "CMAKE_IOS_DEVELOPER_ROOT argument is DEPRECATED. Consider using the new CMAKE_DEVELOPER_ROOT argument instead.") -endif() - -if(DEFINED IOS_ARCH) - set(ARCHS ${IOS_ARCH}) - message(DEPRECATION "IOS_ARCH argument is DEPRECATED. Consider using the new ARCHS argument instead.") -endif() - -######## END ALIASES - -# Unset the FORCE on cache variables if in try_compile() -set(FORCE_CACHE FORCE) -get_property(_CMAKE_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) -if(_CMAKE_IN_TRY_COMPILE) - unset(FORCE_CACHE) -endif() - -# Default to building for iPhoneOS if not specified otherwise, and we cannot -# determine the platform from the CMAKE_OSX_ARCHITECTURES variable. The use -# of CMAKE_OSX_ARCHITECTURES is such that try_compile() projects can correctly -# determine the value of PLATFORM from the root project, as -# CMAKE_OSX_ARCHITECTURES is propagated to them by CMake. -if(NOT DEFINED PLATFORM) - if (CMAKE_OSX_ARCHITECTURES) - if(CMAKE_OSX_ARCHITECTURES MATCHES "arm64" AND CMAKE_OSX_SYSROOT MATCHES ".*iphoneos.*") - set(PLATFORM "OS64") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES ".*arm.*" AND CMAKE_OSX_SYSROOT MATCHES ".*iphoneos.*") - set(PLATFORM "OS") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES "i386" AND CMAKE_OSX_SYSROOT MATCHES ".*iphonesimulator.*") - set(PLATFORM "SIMULATOR") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES "x86_64" AND CMAKE_OSX_SYSROOT MATCHES ".*iphonesimulator.*") - set(PLATFORM "SIMULATOR64") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES "arm64" AND CMAKE_OSX_SYSROOT MATCHES ".*appletvos.*") - set(PLATFORM "TVOS") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES "x86_64" AND CMAKE_OSX_SYSROOT MATCHES ".*appletvsimulator.*") - set(PLATFORM "SIMULATOR_TVOS") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES ".*armv7k.*" AND CMAKE_OSX_SYSROOT MATCHES ".*watchos.*") - set(PLATFORM "WATCHOS") - elseif(CMAKE_OSX_ARCHITECTURES MATCHES "i386" AND CMAKE_OSX_SYSROOT MATCHES ".*watchsimulator.*") - set(PLATFORM "SIMULATOR_WATCHOS") - endif() - endif() - if (NOT PLATFORM) - if(DROP_32_BIT) - set(PLATFORM "OS64") - else() - set(PLATFORM "OS") - endif() - endif() -endif() - -set(PLATFORM_INT "${PLATFORM}" CACHE STRING "Type of platform for which the build targets.") - -# Handle the case where we are targeting iOS and a version above 10.3.4 (32-bit support dropped officially) -if(PLATFORM_INT STREQUAL "OS" AND DEPLOYMENT_TARGET VERSION_GREATER_EQUAL 10.3.4) - set(PLATFORM_INT "OS64") - message(STATUS "Targeting minimum SDK version ${DEPLOYMENT_TARGET}. Dropping 32-bit support.") -elseif(PLATFORM_INT STREQUAL "SIMULATOR" AND DEPLOYMENT_TARGET VERSION_GREATER_EQUAL 10.3.4) - set(PLATFORM_INT "SIMULATOR64") - message(STATUS "Targeting minimum SDK version ${DEPLOYMENT_TARGET}. Dropping 32-bit support.") -endif() - -# Determine the platform name and architectures for use in xcodebuild commands -# from the specified PLATFORM name. -if(PLATFORM_INT STREQUAL "OS") - set(SDK_NAME iphoneos) - if(NOT ARCHS) - set(ARCHS armv7 armv7s arm64) - set(APPLE_TARGET_TRIPLE_INT arm-apple-ios) - endif() -elseif(PLATFORM_INT STREQUAL "OS64") - set(SDK_NAME iphoneos) - if(NOT ARCHS) - if (XCODE_VERSION VERSION_GREATER 10.0) - set(ARCHS arm64) # Add arm64e when Apple have fixed the integration issues with it, libarclite_iphoneos.a is currently missung bitcode markers for example - else() - set(ARCHS arm64) - endif() - set(APPLE_TARGET_TRIPLE_INT aarch64-apple-ios) - endif() -elseif(PLATFORM_INT STREQUAL "OS64COMBINED") - set(SDK_NAME iphoneos) - if(MODERN_CMAKE) - if(NOT ARCHS) - if (XCODE_VERSION VERSION_GREATER 10.0) - set(ARCHS arm64 x86_64) # Add arm64e when Apple have fixed the integration issues with it, libarclite_iphoneos.a is currently missung bitcode markers for example - else() - set(ARCHS arm64 x86_64) - endif() - set(APPLE_TARGET_TRIPLE_INT aarch64-x86_64-apple-ios) - endif() - else() - message(FATAL_ERROR "Please make sure that you are running CMake 3.14+ to make the OS64COMBINED setting work") - endif() -elseif(PLATFORM_INT STREQUAL "SIMULATOR") - set(SDK_NAME iphonesimulator) - if(NOT ARCHS) - set(ARCHS i386) - set(APPLE_TARGET_TRIPLE_INT i386-apple-ios) - endif() - message(DEPRECATION "SIMULATOR IS DEPRECATED. Consider using SIMULATOR64 instead.") -elseif(PLATFORM_INT STREQUAL "SIMULATOR64") - set(SDK_NAME iphonesimulator) - if(NOT ARCHS) - set(ARCHS x86_64) - set(APPLE_TARGET_TRIPLE_INT x86_64-apple-ios) - endif() -elseif(PLATFORM_INT STREQUAL "TVOS") - set(SDK_NAME appletvos) - if(NOT ARCHS) - set(ARCHS arm64) - set(APPLE_TARGET_TRIPLE_INT aarch64-apple-tvos) - endif() -elseif (PLATFORM_INT STREQUAL "TVOSCOMBINED") - set(SDK_NAME appletvos) - if(MODERN_CMAKE) - if(NOT ARCHS) - set(ARCHS arm64 x86_64) - set(APPLE_TARGET_TRIPLE_INT aarch64-x86_64-apple-tvos) - endif() - else() - message(FATAL_ERROR "Please make sure that you are running CMake 3.14+ to make the TVOSCOMBINED setting work") - endif() -elseif(PLATFORM_INT STREQUAL "SIMULATOR_TVOS") - set(SDK_NAME appletvsimulator) - if(NOT ARCHS) - set(ARCHS x86_64) - set(APPLE_TARGET_TRIPLE_INT x86_64-apple-tvos) - endif() -elseif(PLATFORM_INT STREQUAL "WATCHOS") - set(SDK_NAME watchos) - if(NOT ARCHS) - if (XCODE_VERSION VERSION_GREATER 10.0) - set(ARCHS armv7k arm64_32) - set(APPLE_TARGET_TRIPLE_INT aarch64_32-apple-watchos) - else() - set(ARCHS armv7k) - set(APPLE_TARGET_TRIPLE_INT arm-apple-watchos) - endif() - endif() -elseif(PLATFORM_INT STREQUAL "WATCHOSCOMBINED") - set(SDK_NAME watchos) - if(MODERN_CMAKE) - if(NOT ARCHS) - if (XCODE_VERSION VERSION_GREATER 10.0) - set(ARCHS armv7k arm64_32 i386) - set(APPLE_TARGET_TRIPLE_INT aarch64_32-i386-apple-watchos) - else() - set(ARCHS armv7k i386) - set(APPLE_TARGET_TRIPLE_INT arm-i386-apple-watchos) - endif() - endif() - else() - message(FATAL_ERROR "Please make sure that you are running CMake 3.14+ to make the WATCHOSCOMBINED setting work") - endif() -elseif(PLATFORM_INT STREQUAL "SIMULATOR_WATCHOS") - set(SDK_NAME watchsimulator) - if(NOT ARCHS) - set(ARCHS i386) - set(APPLE_TARGET_TRIPLE_INT i386-apple-watchos) - endif() -else() - message(FATAL_ERROR "Invalid PLATFORM: ${PLATFORM_INT}") -endif() - -if(MODERN_CMAKE AND PLATFORM_INT MATCHES ".*COMBINED" AND NOT USED_CMAKE_GENERATOR MATCHES "Xcode") - message(FATAL_ERROR "The COMBINED options only work with Xcode generator, -G Xcode") -endif() - -# If user did not specify the SDK root to use, then query xcodebuild for it. -execute_process(COMMAND xcodebuild -version -sdk ${SDK_NAME} Path - OUTPUT_VARIABLE CMAKE_OSX_SYSROOT_INT - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) -if (NOT DEFINED CMAKE_OSX_SYSROOT_INT AND NOT DEFINED CMAKE_OSX_SYSROOT) - message(SEND_ERROR "Please make sure that Xcode is installed and that the toolchain" - "is pointing to the correct path. Please run:" - "sudo xcode-select -s /Applications/Xcode.app/Contents/Developer" - "and see if that fixes the problem for you.") - message(FATAL_ERROR "Invalid CMAKE_OSX_SYSROOT: ${CMAKE_OSX_SYSROOT} " - "does not exist.") -elseif(DEFINED CMAKE_OSX_SYSROOT_INT) - set(CMAKE_OSX_SYSROOT "${CMAKE_OSX_SYSROOT_INT}" CACHE INTERNAL "") -endif() - -# Set Xcode property for SDKROOT as well if Xcode generator is used -if(USED_CMAKE_GENERATOR MATCHES "Xcode") - set(CMAKE_OSX_SYSROOT "${SDK_NAME}" CACHE INTERNAL "") - if(NOT DEFINED CMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM) - set(CMAKE_XCODE_ATTRIBUTE_DEVELOPMENT_TEAM "123456789A") - endif() -endif() - -# Specify minimum version of deployment target. -if(NOT DEFINED DEPLOYMENT_TARGET) - if (PLATFORM_INT STREQUAL "WATCHOS" OR PLATFORM_INT STREQUAL "SIMULATOR_WATCHOS") - # Unless specified, SDK version 2.0 is used by default as minimum target version (watchOS). - set(DEPLOYMENT_TARGET "2.0" - CACHE STRING "Minimum SDK version to build for." ) - else() - # Unless specified, SDK version 9.0 is used by default as minimum target version (iOS, tvOS). - set(DEPLOYMENT_TARGET "9.0" - CACHE STRING "Minimum SDK version to build for." ) - endif() - message(STATUS "Using the default min-version since DEPLOYMENT_TARGET not provided!") -endif() - -# Use bitcode or not -if(NOT DEFINED ENABLE_BITCODE AND NOT ARCHS MATCHES "((^|;|, )(i386|x86_64))+") - # Unless specified, enable bitcode support by default - message(STATUS "Enabling bitcode support by default. ENABLE_BITCODE not provided!") - set(ENABLE_BITCODE TRUE) -elseif(NOT DEFINED ENABLE_BITCODE) - message(STATUS "Disabling bitcode support by default on simulators. ENABLE_BITCODE not provided for override!") - set(ENABLE_BITCODE FALSE) -endif() -set(ENABLE_BITCODE_INT ${ENABLE_BITCODE} CACHE BOOL "Whether or not to enable bitcode" ${FORCE_CACHE}) -# Use ARC or not -if(NOT DEFINED ENABLE_ARC) - # Unless specified, enable ARC support by default - set(ENABLE_ARC TRUE) - message(STATUS "Enabling ARC support by default. ENABLE_ARC not provided!") -endif() -set(ENABLE_ARC_INT ${ENABLE_ARC} CACHE BOOL "Whether or not to enable ARC" ${FORCE_CACHE}) -# Use hidden visibility or not -if(NOT DEFINED ENABLE_VISIBILITY) - # Unless specified, disable symbols visibility by default - set(ENABLE_VISIBILITY FALSE) - message(STATUS "Hiding symbols visibility by default. ENABLE_VISIBILITY not provided!") -endif() -set(ENABLE_VISIBILITY_INT ${ENABLE_VISIBILITY} CACHE BOOL "Whether or not to hide symbols (-fvisibility=hidden)" ${FORCE_CACHE}) -# Set strict compiler checks or not -if(NOT DEFINED ENABLE_STRICT_TRY_COMPILE) - # Unless specified, disable strict try_compile() - set(ENABLE_STRICT_TRY_COMPILE FALSE) - message(STATUS "Using NON-strict compiler checks by default. ENABLE_STRICT_TRY_COMPILE not provided!") -endif() -set(ENABLE_STRICT_TRY_COMPILE_INT ${ENABLE_STRICT_TRY_COMPILE} CACHE BOOL "Whether or not to use strict compiler checks" ${FORCE_CACHE}) -# Get the SDK version information. -execute_process(COMMAND xcodebuild -sdk ${CMAKE_OSX_SYSROOT} -version SDKVersion - OUTPUT_VARIABLE SDK_VERSION - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) - -# Find the Developer root for the specific iOS platform being compiled for -# from CMAKE_OSX_SYSROOT. Should be ../../ from SDK specified in -# CMAKE_OSX_SYSROOT. There does not appear to be a direct way to obtain -# this information from xcrun or xcodebuild. -if (NOT DEFINED CMAKE_DEVELOPER_ROOT AND NOT USED_CMAKE_GENERATOR MATCHES "Xcode") - get_filename_component(PLATFORM_SDK_DIR ${CMAKE_OSX_SYSROOT} PATH) - get_filename_component(CMAKE_DEVELOPER_ROOT ${PLATFORM_SDK_DIR} PATH) - if (NOT DEFINED CMAKE_DEVELOPER_ROOT) - message(FATAL_ERROR "Invalid CMAKE_DEVELOPER_ROOT: " - "${CMAKE_DEVELOPER_ROOT} does not exist.") - endif() -endif() -# Find the C & C++ compilers for the specified SDK. -if(NOT CMAKE_C_COMPILER) - execute_process(COMMAND xcrun -sdk ${CMAKE_OSX_SYSROOT} -find clang - OUTPUT_VARIABLE CMAKE_C_COMPILER - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) - message(STATUS "Using C compiler: ${CMAKE_C_COMPILER}") -endif() -if(NOT CMAKE_CXX_COMPILER) - execute_process(COMMAND xcrun -sdk ${CMAKE_OSX_SYSROOT} -find clang++ - OUTPUT_VARIABLE CMAKE_CXX_COMPILER - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) - message(STATUS "Using CXX compiler: ${CMAKE_CXX_COMPILER}") -endif() -# Find (Apple's) libtool. -execute_process(COMMAND xcrun -sdk ${CMAKE_OSX_SYSROOT} -find libtool - OUTPUT_VARIABLE BUILD_LIBTOOL - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) -message(STATUS "Using libtool: ${BUILD_LIBTOOL}") -# Configure libtool to be used instead of ar + ranlib to build static libraries. -# This is required on Xcode 7+, but should also work on previous versions of -# Xcode. -set(CMAKE_C_CREATE_STATIC_LIBRARY - "${BUILD_LIBTOOL} -static -o ") -set(CMAKE_CXX_CREATE_STATIC_LIBRARY - "${BUILD_LIBTOOL} -static -o ") -# Find the toolchain's provided install_name_tool if none is found on the host -if(NOT CMAKE_INSTALL_NAME_TOOL) - execute_process(COMMAND xcrun -sdk ${CMAKE_OSX_SYSROOT} -find install_name_tool - OUTPUT_VARIABLE CMAKE_INSTALL_NAME_TOOL_INT - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) - set(CMAKE_INSTALL_NAME_TOOL ${CMAKE_INSTALL_NAME_TOOL_INT} CACHE STRING "" ${FORCE_CACHE}) -endif() -# Get the version of Darwin (OS X) of the host. -execute_process(COMMAND uname -r - OUTPUT_VARIABLE CMAKE_HOST_SYSTEM_VERSION - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) -if(SDK_NAME MATCHES "iphone") - set(CMAKE_SYSTEM_NAME iOS CACHE INTERNAL "" ${FORCE_CACHE}) -endif() -# CMake 3.14+ support building for iOS, watchOS and tvOS out of the box. -if(MODERN_CMAKE) - if(SDK_NAME MATCHES "appletv") - set(CMAKE_SYSTEM_NAME tvOS CACHE INTERNAL "" ${FORCE_CACHE}) - elseif(SDK_NAME MATCHES "watch") - set(CMAKE_SYSTEM_NAME watchOS CACHE INTERNAL "" ${FORCE_CACHE}) - endif() - # Provide flags for a combined FAT library build on newer CMake versions - if(PLATFORM_INT MATCHES ".*COMBINED") - set(CMAKE_XCODE_ATTRIBUTE_ONLY_ACTIVE_ARCH "NO") - set(CMAKE_IOS_INSTALL_COMBINED YES CACHE INTERNAL "" ${FORCE_CACHE}) - message(STATUS "Will combine built (static) artifacts into FAT lib...") - endif() -elseif(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.10") - # Legacy code path prior to CMake 3.14 or fallback if no SDK_NAME specified - set(CMAKE_SYSTEM_NAME iOS CACHE INTERNAL "" ${FORCE_CACHE}) -else() - # Legacy code path prior to CMake 3.14 or fallback if no SDK_NAME specified - set(CMAKE_SYSTEM_NAME Darwin CACHE INTERNAL "" ${FORCE_CACHE}) -endif() -# Standard settings. -set(CMAKE_SYSTEM_VERSION ${SDK_VERSION} CACHE INTERNAL "") -set(UNIX TRUE CACHE BOOL "") -set(APPLE TRUE CACHE BOOL "") -set(IOS TRUE CACHE BOOL "") -set(CMAKE_AR ar CACHE FILEPATH "" FORCE) -set(CMAKE_RANLIB ranlib CACHE FILEPATH "" FORCE) -set(CMAKE_STRIP strip CACHE FILEPATH "" FORCE) -# Set the architectures for which to build. -set(CMAKE_OSX_ARCHITECTURES ${ARCHS} CACHE STRING "Build architecture for iOS") -# Change the type of target generated for try_compile() so it'll work when cross-compiling, weak compiler checks -if(ENABLE_STRICT_TRY_COMPILE_INT) - message(STATUS "Using strict compiler checks (default in CMake).") -else() - set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) -endif() -# All iOS/Darwin specific settings - some may be redundant. -set(CMAKE_MACOSX_BUNDLE YES) -set(CMAKE_XCODE_ATTRIBUTE_CODE_SIGNING_REQUIRED "NO") -set(CMAKE_SHARED_LIBRARY_PREFIX "lib") -set(CMAKE_SHARED_LIBRARY_SUFFIX ".dylib") -set(CMAKE_SHARED_MODULE_PREFIX "lib") -set(CMAKE_SHARED_MODULE_SUFFIX ".so") -set(CMAKE_C_COMPILER_ABI ELF) -set(CMAKE_CXX_COMPILER_ABI ELF) -set(CMAKE_C_HAS_ISYSROOT 1) -set(CMAKE_CXX_HAS_ISYSROOT 1) -set(CMAKE_MODULE_EXISTS 1) -set(CMAKE_DL_LIBS "") -set(CMAKE_C_OSX_COMPATIBILITY_VERSION_FLAG "-compatibility_version ") -set(CMAKE_C_OSX_CURRENT_VERSION_FLAG "-current_version ") -set(CMAKE_CXX_OSX_COMPATIBILITY_VERSION_FLAG "${CMAKE_C_OSX_COMPATIBILITY_VERSION_FLAG}") -set(CMAKE_CXX_OSX_CURRENT_VERSION_FLAG "${CMAKE_C_OSX_CURRENT_VERSION_FLAG}") - -if(ARCHS MATCHES "((^|;|, )(arm64|arm64e|x86_64))+") - set(CMAKE_C_SIZEOF_DATA_PTR 8) - set(CMAKE_CXX_SIZEOF_DATA_PTR 8) - if(ARCHS MATCHES "((^|;|, )(arm64|arm64e))+") - set(CMAKE_SYSTEM_PROCESSOR "aarch64") - else() - set(CMAKE_SYSTEM_PROCESSOR "x86_64") - endif() -else() - set(CMAKE_C_SIZEOF_DATA_PTR 4) - set(CMAKE_CXX_SIZEOF_DATA_PTR 4) - set(CMAKE_SYSTEM_PROCESSOR "arm") -endif() - -# Note that only Xcode 7+ supports the newer more specific: -# -m${SDK_NAME}-version-min flags, older versions of Xcode use: -# -m(ios/ios-simulator)-version-min instead. -if(${CMAKE_VERSION} VERSION_LESS "3.11") - if(PLATFORM_INT STREQUAL "OS" OR PLATFORM_INT STREQUAL "OS64") - if(XCODE_VERSION VERSION_LESS 7.0) - set(SDK_NAME_VERSION_FLAGS - "-mios-version-min=${DEPLOYMENT_TARGET}") - else() - # Xcode 7.0+ uses flags we can build directly from SDK_NAME. - set(SDK_NAME_VERSION_FLAGS - "-m${SDK_NAME}-version-min=${DEPLOYMENT_TARGET}") - endif() - elseif(PLATFORM_INT STREQUAL "TVOS") - set(SDK_NAME_VERSION_FLAGS - "-mtvos-version-min=${DEPLOYMENT_TARGET}") - elseif(PLATFORM_INT STREQUAL "SIMULATOR_TVOS") - set(SDK_NAME_VERSION_FLAGS - "-mtvos-simulator-version-min=${DEPLOYMENT_TARGET}") - elseif(PLATFORM_INT STREQUAL "WATCHOS") - set(SDK_NAME_VERSION_FLAGS - "-mwatchos-version-min=${DEPLOYMENT_TARGET}") - elseif(PLATFORM_INT STREQUAL "SIMULATOR_WATCHOS") - set(SDK_NAME_VERSION_FLAGS - "-mwatchos-simulator-version-min=${DEPLOYMENT_TARGET}") - else() - # SIMULATOR or SIMULATOR64 both use -mios-simulator-version-min. - set(SDK_NAME_VERSION_FLAGS - "-mios-simulator-version-min=${DEPLOYMENT_TARGET}") - endif() -else() - # Newer versions of CMake sets the version min flags correctly - set(CMAKE_OSX_DEPLOYMENT_TARGET ${DEPLOYMENT_TARGET} CACHE STRING - "Set CMake deployment target" ${FORCE_CACHE}) -endif() - -if(DEFINED APPLE_TARGET_TRIPLE_INT) - set(APPLE_TARGET_TRIPLE ${APPLE_TARGET_TRIPLE_INT} CACHE STRING - "Autoconf target triple compatible variable" ${FORCE_CACHE}) -endif() - -if(ENABLE_BITCODE_INT) - set(BITCODE "-fembed-bitcode") - set(CMAKE_XCODE_ATTRIBUTE_BITCODE_GENERATION_MODE "bitcode") - set(CMAKE_XCODE_ATTRIBUTE_ENABLE_BITCODE "YES") -else() - set(BITCODE "") - set(CMAKE_XCODE_ATTRIBUTE_ENABLE_BITCODE "NO") -endif() - -if(ENABLE_ARC_INT) - set(FOBJC_ARC "-fobjc-arc") - set(CMAKE_XCODE_ATTRIBUTE_CLANG_ENABLE_OBJC_ARC "YES") -else() - set(FOBJC_ARC "-fno-objc-arc") - set(CMAKE_XCODE_ATTRIBUTE_CLANG_ENABLE_OBJC_ARC "NO") -endif() - -if(NOT ENABLE_VISIBILITY_INT) - set(VISIBILITY "-fvisibility=hidden") - set(CMAKE_XCODE_ATTRIBUTE_GCC_SYMBOLS_PRIVATE_EXTERN "YES") -else() - set(VISIBILITY "") - set(CMAKE_XCODE_ATTRIBUTE_GCC_SYMBOLS_PRIVATE_EXTERN "NO") -endif() - -if(NOT IOS_TOOLCHAIN_HAS_RUN) - #Check if Xcode generator is used, since that will handle these flags automagically - if(USED_CMAKE_GENERATOR MATCHES "Xcode") - message(STATUS "Not setting any manual command-line buildflags, since Xcode is selected as generator.") - else() - set(CMAKE_C_FLAGS - "${SDK_NAME_VERSION_FLAGS} ${BITCODE} -fobjc-abi-version=2 ${FOBJC_ARC} ${CMAKE_C_FLAGS}") - # Hidden visibilty is required for C++ on iOS. - set(CMAKE_CXX_FLAGS - "${SDK_NAME_VERSION_FLAGS} ${BITCODE} ${VISIBILITY} -fvisibility-inlines-hidden -fobjc-abi-version=2 ${FOBJC_ARC} ${CMAKE_CXX_FLAGS}") - set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS} -O0 -g ${CMAKE_CXX_FLAGS_DEBUG}") - set(CMAKE_CXX_FLAGS_MINSIZEREL "${CMAKE_CXX_FLAGS} -DNDEBUG -Os -ffast-math ${CMAKE_CXX_FLAGS_MINSIZEREL}") - set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS} -DNDEBUG -O2 -g -ffast-math ${CMAKE_CXX_FLAGS_RELWITHDEBINFO}") - set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS} -DNDEBUG -O3 -ffast-math ${CMAKE_CXX_FLAGS_RELEASE}") - set(CMAKE_C_LINK_FLAGS "${SDK_NAME_VERSION_FLAGS} -Wl,-search_paths_first ${CMAKE_C_LINK_FLAGS}") - set(CMAKE_CXX_LINK_FLAGS "${SDK_NAME_VERSION_FLAGS} -Wl,-search_paths_first ${CMAKE_CXX_LINK_FLAGS}") - set(CMAKE_ASM_FLAGS "${CFLAGS} -x assembler-with-cpp -arch ${CMAKE_OSX_ARCHITECTURES}") - - # In order to ensure that the updated compiler flags are used in try_compile() - # tests, we have to forcibly set them in the CMake cache, not merely set them - # in the local scope. - set(VARS_TO_FORCE_IN_CACHE - CMAKE_C_FLAGS - CMAKE_CXX_FLAGS - CMAKE_CXX_FLAGS_DEBUG - CMAKE_CXX_FLAGS_RELWITHDEBINFO - CMAKE_CXX_FLAGS_MINSIZEREL - CMAKE_CXX_FLAGS_RELEASE - CMAKE_C_LINK_FLAGS - CMAKE_CXX_LINK_FLAGS) - foreach(VAR_TO_FORCE ${VARS_TO_FORCE_IN_CACHE}) - set(${VAR_TO_FORCE} "${${VAR_TO_FORCE}}" CACHE STRING "" ${FORCE_CACHE}) - endforeach() - endif() - - ## Print status messages to inform of the current state - message(STATUS "Configuring ${SDK_NAME} build for platform: ${PLATFORM_INT}, architecture(s): ${ARCHS}") - message(STATUS "Using SDK: ${CMAKE_OSX_SYSROOT_INT}") - if(DEFINED APPLE_TARGET_TRIPLE) - message(STATUS "Autoconf target triple: ${APPLE_TARGET_TRIPLE}") - endif() - message(STATUS "Using minimum deployment version: ${DEPLOYMENT_TARGET}" - " (SDK version: ${SDK_VERSION})") - if(MODERN_CMAKE) - message(STATUS "Merging integrated CMake 3.14+ iOS,tvOS,watchOS,macOS toolchain(s) with this toolchain!") - endif() - if(USED_CMAKE_GENERATOR MATCHES "Xcode") - message(STATUS "Using Xcode version: ${XCODE_VERSION}") - endif() - if(DEFINED SDK_NAME_VERSION_FLAGS) - message(STATUS "Using version flags: ${SDK_NAME_VERSION_FLAGS}") - endif() - message(STATUS "Using a data_ptr size of: ${CMAKE_CXX_SIZEOF_DATA_PTR}") - message(STATUS "Using install_name_tool: ${CMAKE_INSTALL_NAME_TOOL}") - if(ENABLE_BITCODE_INT) - message(STATUS "Enabling bitcode support.") - else() - message(STATUS "Disabling bitcode support.") - endif() - - if(ENABLE_ARC_INT) - message(STATUS "Enabling ARC support.") - else() - message(STATUS "Disabling ARC support.") - endif() - - if(NOT ENABLE_VISIBILITY_INT) - message(STATUS "Hiding symbols (-fvisibility=hidden).") - endif() -endif() - -set(CMAKE_PLATFORM_HAS_INSTALLNAME 1) -set(CMAKE_SHARED_LINKER_FLAGS "-rpath @executable_path/Frameworks -rpath @loader_path/Frameworks") -set(CMAKE_SHARED_LIBRARY_CREATE_C_FLAGS "-dynamiclib -Wl,-headerpad_max_install_names") -set(CMAKE_SHARED_MODULE_CREATE_C_FLAGS "-bundle -Wl,-headerpad_max_install_names") -set(CMAKE_SHARED_MODULE_LOADER_C_FLAG "-Wl,-bundle_loader,") -set(CMAKE_SHARED_MODULE_LOADER_CXX_FLAG "-Wl,-bundle_loader,") -set(CMAKE_FIND_LIBRARY_SUFFIXES ".tbd" ".dylib" ".so" ".a") -set(CMAKE_SHARED_LIBRARY_SONAME_C_FLAG "-install_name") - -# Set the find root to the iOS developer roots and to user defined paths. -set(CMAKE_FIND_ROOT_PATH ${CMAKE_OSX_SYSROOT_INT} ${CMAKE_PREFIX_PATH} CACHE STRING "Root path that will be prepended - to all search paths") -# Default to searching for frameworks first. -set(CMAKE_FIND_FRAMEWORK FIRST) -# Set up the default search directories for frameworks. -set(CMAKE_FRAMEWORK_PATH - ${CMAKE_DEVELOPER_ROOT}/Library/PrivateFrameworks - ${CMAKE_OSX_SYSROOT_INT}/System/Library/Frameworks - ${CMAKE_FRAMEWORK_PATH} CACHE STRING "Frameworks search paths" ${FORCE_CACHE}) - -set(IOS_TOOLCHAIN_HAS_RUN TRUE CACHE BOOL "Has the CMake toolchain run already?" ${FORCE_CACHE}) - -# By default, search both the specified iOS SDK and the remainder of the host filesystem. -if(NOT CMAKE_FIND_ROOT_PATH_MODE_PROGRAM) - set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM BOTH CACHE STRING "" ${FORCE_CACHE}) -endif() -if(NOT CMAKE_FIND_ROOT_PATH_MODE_LIBRARY) - set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY BOTH CACHE STRING "" ${FORCE_CACHE}) -endif() -if(NOT CMAKE_FIND_ROOT_PATH_MODE_INCLUDE) - set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE BOTH CACHE STRING "" ${FORCE_CACHE}) -endif() -if(NOT CMAKE_FIND_ROOT_PATH_MODE_PACKAGE) - set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE BOTH CACHE STRING "" ${FORCE_CACHE}) -endif() - -# -# Some helper-macros below to simplify and beautify the CMakeFile -# - -# This little macro lets you set any Xcode specific property. -macro(set_xcode_property TARGET XCODE_PROPERTY XCODE_VALUE XCODE_RELVERSION) - set(XCODE_RELVERSION_I "${XCODE_RELVERSION}") - if(XCODE_RELVERSION_I STREQUAL "All") - set_property(TARGET ${TARGET} PROPERTY - XCODE_ATTRIBUTE_${XCODE_PROPERTY} "${XCODE_VALUE}") - else() - set_property(TARGET ${TARGET} PROPERTY - XCODE_ATTRIBUTE_${XCODE_PROPERTY}[variant=${XCODE_RELVERSION_I}] "${XCODE_VALUE}") - endif() -endmacro(set_xcode_property) - -# This macro lets you find executable programs on the host system. -macro(find_host_package) - set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) - set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER) - set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER) - set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE NEVER) - set(IOS FALSE) - find_package(${ARGN}) - set(IOS TRUE) - set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM BOTH) - set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY BOTH) - set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE BOTH) - set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE BOTH) -endmacro(find_host_package) diff --git a/vendor/lief/cmake/linux/s390x-toolchain.cmake b/vendor/lief/cmake/linux/s390x-toolchain.cmake new file mode 100644 index 0000000..0233fc9 --- /dev/null +++ b/vendor/lief/cmake/linux/s390x-toolchain.cmake @@ -0,0 +1,26 @@ +# CMake toolchain file for s390x cross-compilation +# This file configures CMake to cross-compile LIEF for s390x architecture from x86_64 host + +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_PROCESSOR s390x) + +# Specify the cross-compiler +set(CMAKE_C_COMPILER s390x-linux-gnu-gcc) +set(CMAKE_CXX_COMPILER s390x-linux-gnu-g++) +set(CMAKE_AR s390x-linux-gnu-ar) +set(CMAKE_RANLIB s390x-linux-gnu-ranlib) +set(CMAKE_STRIP s390x-linux-gnu-strip) + +# Where to look for the target environment +set(CMAKE_FIND_ROOT_PATH /usr/s390x-linux-gnu) + +# Search for programs in the build host directories +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + +# Search for libraries and headers in the target directories +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# Target IBM z13 or newer for optimal compatibility +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=z13" CACHE STRING "C flags for s390x") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=z13" CACHE STRING "CXX flags for s390x") diff --git a/vendor/lief/config/mbedtls/config.h b/vendor/lief/config/mbedtls/config.h new file mode 100644 index 0000000..fc29d0b --- /dev/null +++ b/vendor/lief/config/mbedtls/config.h @@ -0,0 +1,9 @@ +#include "mbedtls/mbedtls_config.h" + +#if defined(MBEDTLS_ARCH_IS_X86) + #undef MBEDTLS_AESNI_C +#endif + +#if defined(MBEDTLS_DEBUG_C) + #undef MBEDTLS_DEBUG_C +#endif diff --git a/vendor/lief/config/mbedtls/psa_config.h b/vendor/lief/config/mbedtls/psa_config.h new file mode 100644 index 0000000..836d9b1 --- /dev/null +++ b/vendor/lief/config/mbedtls/psa_config.h @@ -0,0 +1,14 @@ +// Disable MbedTLS options that are not thread-safe. See +// `tests/scripts/components-sanitizers.sh` in the MbedTLS tree: both options +// are unset there when building with MBEDTLS_THREADING_PTHREAD under TSan. +#if defined(MBEDTLS_THREADING_C) + // Self-tests do not currently use multiple threads. + #if defined(MBEDTLS_SELF_TEST) + #undef MBEDTLS_SELF_TEST + #endif + + // Interruptible ECC operations are not thread-safe. + #if defined(MBEDTLS_ECP_RESTARTABLE) + #undef MBEDTLS_ECP_RESTARTABLE + #endif +#endif diff --git a/vendor/lief/doc/CMakeLists.txt b/vendor/lief/doc/CMakeLists.txt deleted file mode 100644 index ba0f360..0000000 --- a/vendor/lief/doc/CMakeLists.txt +++ /dev/null @@ -1,60 +0,0 @@ -find_package(Doxygen) -find_package(Sphinx) - -if(NOT DOXYGEN_FOUND) - message(STATUS "Doc disabled: doxygen not found") -elseif(NOT SPHINX_FOUND) - message(FATAL "Doc disabled: sphinx-build not found") -elseif(${CMAKE_CURRENT_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_BINARY_DIR}) - message(STATUS "You have to build the doc in another directory !") -else() - message(STATUS "Sphinx: ${SPHINX_EXECUTABLE}") - add_custom_target(lief-doxygen - COMMAND - ${CMAKE_COMMAND} -E env - "LIEF_VERSION=${LIEF_VERSION_MAJOR}.${LIEF_VERSION_MINOR}.${LIEF_VERSION_PATCH}-${LIEF_COMMIT_HASH}" - "LIEF_INPUT=${CMAKE_SOURCE_DIR}/src ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include/LIEF ${CMAKE_SOURCE_DIR}/api/c/include ${CMAKE_SOURCE_DIR}/doc/doxygen/" - "LIEF_EXCLUDE=${CMAKE_BINARY_DIR}/include/LIEF/third-party" - "LIEF_INCLUDE_PATH=${CMAKE_BINARY_DIR}/include ${CMAKE_SOURCE_DIR}/include" - "LIEF_DOXYGEN_WARN_FILE=${CMAKE_BINARY_DIR}/doxygen-warn.log" - ${DOXYGEN_EXECUTABLE} ${CMAKE_SOURCE_DIR}/doc/doxygen/Doxyfile - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating Doxygen documentation" VERBATIM) - - add_custom_target(lief-sphinx - COMMAND ${CMAKE_COMMAND} -E env - "PYTHONPATH=${CMAKE_SOURCE_DIR}:${CMAKE_BINARY_DIR}/../:${CMAKE_BINARY_DIR}/api/python:$ENV{PYTHONPATH}" - "LIEF_DOXYGEN_XML=${CMAKE_CURRENT_BINARY_DIR}/doxygen/xml/" - ${SPHINX_EXECUTABLE} -a -E -j4 -w ${CMAKE_BINARY_DIR}/sphinx-warn.log ${CMAKE_SOURCE_DIR}/doc/sphinx sphinx-doc - DEPENDS pyLIEF lief-doxygen - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating Sphinx Documentation" VERBATIM) - - add_custom_target(lief-doc ALL - DEPENDS lief-sphinx lief-doxygen - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating documentation with Doxygen and Sphinx" VERBATIM) - - add_custom_target(lief-quick-sphinx - COMMAND ${CMAKE_COMMAND} -E env - "PYTHONPATH=${CMAKE_SOURCE_DIR}:${CMAKE_BINARY_DIR}/../:${CMAKE_BINARY_DIR}/api/python:$ENV{PYTHONPATH}" - "LIEF_DOXYGEN_XML=${CMAKE_CURRENT_BINARY_DIR}/doxygen/xml/" - "FORCE_RTD_THEME=0" - ${SPHINX_EXECUTABLE} -j4 -w ${CMAKE_BINARY_DIR}/sphinx-warn.log ${CMAKE_SOURCE_DIR}/doc/sphinx sphinx-doc - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating Sphinx documentation quickly" VERBATIM) - - install( - DIRECTORY - ${CMAKE_CURRENT_BINARY_DIR}/doxygen/html/ - DESTINATION - share/LIEF/doc/doxygen - COMPONENT doc) - - install( - DIRECTORY - ${CMAKE_CURRENT_BINARY_DIR}/sphinx-doc/ - DESTINATION - share/LIEF/doc/sphinx - COMPONENT doc) -endif() diff --git a/vendor/lief/doc/code/README.md b/vendor/lief/doc/code/README.md new file mode 100644 index 0000000..83d080e --- /dev/null +++ b/vendor/lief/doc/code/README.md @@ -0,0 +1,39 @@ +# Documentation code examples + +The files in this directory back the code snippets used in the +documentation. + +This guarantees that the snippets referenced in the documentation stay in sync with the +actual LIEF API: if an API changes, these files stop compiling/linting and the +error are caught instead of silently staying in the docs. + +## Marker convention + +Each snippet is wrapped between a pair of marker comments so that +`literalinclude` can extract exactly the region shown in the docs: + +``` +# lief-doc: -start + +# lief-doc: -end +``` + +C++ and Rust use `// lief-doc: -start` / `// lief-doc: -end`. + +On the documentation side: + +```rst +.. literalinclude:: /../code/python/elf.py + :language: python + :start-after: lief-doc: parse-start + :end-before: lief-doc: parse-end + :dedent: +``` + +The marker lines themselves are excluded from the generated doc +(`:start-after:` / `:end-before:`), and `:dedent:` strips the leading +indentation coming from the enclosing function. + +**Keep the marker around the code** and put every bit of scaffolding +(imports, includes, `None` narrowing, ...) *outside* the marked +region. diff --git a/vendor/lief/doc/code/cpp/CMakeLists.txt b/vendor/lief/doc/code/cpp/CMakeLists.txt new file mode 100644 index 0000000..29c06a1 --- /dev/null +++ b/vendor/lief/doc/code/cpp/CMakeLists.txt @@ -0,0 +1,18 @@ +cmake_minimum_required(VERSION 3.30) +project(lief-doc-code CXX) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +if (NOT TARGET LIB_LIEF) + find_package(LIEF REQUIRED) +endif() + +file(GLOB LIEF_DOC_CODE_SOURCES CONFIGURE_DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/*.cpp") + +add_library(lief-doc-code OBJECT ${LIEF_DOC_CODE_SOURCES}) +target_link_libraries(lief-doc-code PRIVATE LIEF::LIEF) +target_compile_options(lief-doc-code PRIVATE + -Wno-unused-variable + -Wno-unused-parameter +) diff --git a/vendor/lief/doc/code/cpp/abstract.cpp b/vendor/lief/doc/code/cpp/abstract.cpp new file mode 100644 index 0000000..9e01fdc --- /dev/null +++ b/vendor/lief/doc/code/cpp/abstract.cpp @@ -0,0 +1,26 @@ +#include + +#include +#include +#include + +void parse_forms() { + // lief-doc: parse-start + std::unique_ptr target = LIEF::Parser::parse("some.elf"); + + target = LIEF::Parser::parse("some.macho"); + + target = LIEF::Parser::parse("some.exe"); + // lief-doc: parse-end + (void)target; +} + +void downcast() { + // lief-doc: downcast-start + std::unique_ptr target = LIEF::Parser::parse("some.elf"); + + if (LIEF::ELF::Binary::classof(target.get())) { + auto& elf = static_cast(*target); + } + // lief-doc: downcast-end +} diff --git a/vendor/lief/doc/code/cpp/assembler.cpp b/vendor/lief/doc/code/cpp/assembler.cpp new file mode 100644 index 0000000..3b10dcf --- /dev/null +++ b/vendor/lief/doc/code/cpp/assembler.cpp @@ -0,0 +1,118 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +void disassemble_assemble() { + // lief-doc: disassemble-assemble-start + std::unique_ptr elf; + + std::vector syscall_addresses; + for (const auto& inst : elf->disassemble(0x400090)) { + if (inst.is_syscall()) { + syscall_addresses.push_back(inst.address()); + } + } + + for (uint64_t addr : syscall_addresses) { + elf->assemble(addr, R"asm( + mov x1, x0; + str x1, [x2, #8]; + )asm"); + } + // lief-doc: disassemble-assemble-end +} + +void context_error() { + // lief-doc: context-error-start + std::unique_ptr elf; + elf->assemble(elf->entrypoint(), R"asm( + mov rdi, rax; + call a_custom_function; + )asm"); + // lief-doc: context-error-end +} + +void config_resolver() { + // lief-doc: config-resolver-start + class MyConfig : public LIEF::assembly::AssemblerConfig { + public: + std::optional resolve_symbol(const std::string& name) override { + if (name == "a_custom_function") { + return 0x1000; + } + return std::nullopt; + } + }; + + MyConfig myconfig; + + std::unique_ptr elf; + + elf->assemble(elf->entrypoint(), R"asm( + mov rdi, rax; + call a_custom_function; + )asm", + myconfig); + // lief-doc: config-resolver-end +} + +void config_target() { + // lief-doc: config-target-start + class MyConfig : public LIEF::assembly::AssemblerConfig { + public: + MyConfig() = delete; + MyConfig(LIEF::Binary& target) : + LIEF::assembly::AssemblerConfig(), + target_(&target) {} + + std::optional resolve_symbol(const std::string& name) override { + if (auto addr = target_->get_function_address(name)) { + return *addr; + } + return std::nullopt; + } + + ~MyConfig() override = default; + + private: + LIEF::Binary* target_ = nullptr; + }; + + std::unique_ptr elf; + MyConfig myconfig(*elf); + + elf->assemble(elf->entrypoint(), R"asm( + mov rdi, rax; + call a_custom_function; + )asm", + myconfig); + // lief-doc: config-target-end +} + +void disable_instruction() { + // lief-doc: nop-out-start + std::unique_ptr elf; + + // Overwrite the first call in the region (e.g. a call to an anti-debugging + // routine) with nops + for (const auto& inst : elf->disassemble(0x401200)) { + if (inst.is_call()) { + std::string nops; + for (size_t i = 0; i < inst.size(); ++i) { + nops += "nop\n"; + } + elf->assemble(inst.address(), nops); + break; + } + } + + elf->write("patched.bin"); + // lief-doc: nop-out-end +} diff --git a/vendor/lief/doc/code/cpp/coff.cpp b/vendor/lief/doc/code/cpp/coff.cpp new file mode 100644 index 0000000..cb3db1e --- /dev/null +++ b/vendor/lief/doc/code/cpp/coff.cpp @@ -0,0 +1,37 @@ +#include +#include + +#include + +void sections() { + // lief-doc: sections-start + std::unique_ptr coff; + + for (const LIEF::COFF::Section& section : coff->sections()) { + std::cout << section.name() << '\n'; + } + // lief-doc: sections-end +} + +void disassemble() { + // lief-doc: disassemble-start + std::unique_ptr coff; + + for (const auto& inst : coff->disassemble("?foo@@YAHHH@Z")) { + std::cout << inst.to_string() << '\n'; + } + + // Using demangled representation + for (const auto& inst : coff->disassemble("int __cdecl bar(int, int)")) { + std::cout << inst.to_string() << '\n'; + } + // lief-doc: disassemble-end +} + +void parse_forms() { + // lief-doc: parse-start + + // Using a file path as a std::string + std::unique_ptr coff = LIEF::COFF::Parser::parse("test.obj"); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/cpp/disassembler.cpp b/vendor/lief/doc/code/cpp/disassembler.cpp new file mode 100644 index 0000000..3b91f65 --- /dev/null +++ b/vendor/lief/doc/code/cpp/disassembler.cpp @@ -0,0 +1,68 @@ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +void disassemble() { + // lief-doc: disassemble-start + std::unique_ptr pe; + + for (const auto& inst : pe->disassemble("_WinRT")) { + std::cout << inst.to_string() << '\n'; + } + // lief-doc: disassemble-end +} + +void check_opcode() { + // lief-doc: downcast-start + std::unique_ptr inst; + + if (const auto* riscv_inst = inst->as()) { + LIEF::assembly::riscv::OPCODE opcode = riscv_inst->opcode(); + } + // lief-doc: downcast-end +} + +void dsc_disassemble() { + // lief-doc: dsc-disassemble-start + std::unique_ptr dyld_cache; + + for (const auto& inst : dyld_cache->disassemble(0x1886f4a44)) { + std::cout << inst.to_string() << '\n'; + } + // lief-doc: dsc-disassemble-end +} + +void dwarf_function() { + // lief-doc: dwarf-func-start + auto elf = LIEF::ELF::Parser::parse("/bin/hello"); + + if (const auto* dwarf = elf->debug_info()->as()) { + std::unique_ptr _main = dwarf->find_function("main"); + for (const auto& inst : _main->instructions()) { + std::cout << inst.to_string() << '\n'; + } + } + // lief-doc: dwarf-func-end +} + +void x86_lock() { + // lief-doc: x86-lock-start + std::unique_ptr inst; + + if (inst->has_lock_prefix() || inst->is_atomic()) { + std::cout << inst->to_string() << " is atomic\n"; + } else if (inst->is_lockable()) { + if (auto locked = inst->lock()) { + std::cout << "atomic version: " << locked->to_string() << '\n'; + } + } + // lief-doc: x86-lock-end +} diff --git a/vendor/lief/doc/code/cpp/dsc.cpp b/vendor/lief/doc/code/cpp/dsc.cpp new file mode 100644 index 0000000..938bea3 --- /dev/null +++ b/vendor/lief/doc/code/cpp/dsc.cpp @@ -0,0 +1,69 @@ +#include +#include + +#include +#include + +using namespace LIEF::dsc; + +void iterate_libraries() { + // lief-doc: libraries-start + std::unique_ptr dyld_cache; + + for (const LIEF::dsc::Dylib& dylib : dyld_cache->libraries()) { + std::cout << dylib.address() << ' ' << dylib.path() << '\n'; + } + // lief-doc: libraries-end +} + +void extract() { + // lief-doc: extract-start + std::unique_ptr dyld_cache; + + std::unique_ptr liblockdown = + dyld_cache->find_lib_from_name("liblockdown.dylib"); + + std::unique_ptr macho = liblockdown->get(); + for (const LIEF::MachO::SegmentCommand& segment : macho->segments()) { + std::cout << segment.name() << '\n'; + } + // lief-doc: extract-end +} + +void write_back() { + // lief-doc: write-start + std::unique_ptr dyld_cache; + + std::unique_ptr liblockdown = + dyld_cache->find_lib_from_name("liblockdown.dylib"); + + std::unique_ptr macho = liblockdown->get(); + macho->write("on-disk-liblockdown.dylib"); + // lief-doc: write-end +} + +void random_access() { + // lief-doc: random-access-start + std::unique_ptr dyld_cache; + + // No cost + auto libraries = dyld_cache->libraries(); + + // O(1) cost: the iterator is random access, so an arbitrary library can be + // reached by index without materializing the ones before it. + std::cout << "First library: " << libraries[0]->path() << '\n'; + + // O(libraries.size()) cost + for (const Dylib& dylib : libraries) { + std::cout << dylib.path() << '\n'; + } + // lief-doc: random-access-end +} + +void load() { + // lief-doc: load-start + std::unique_ptr dyld_cache = + LIEF::dsc::load("macos-15.0.1/"); + // lief-doc: load-end + (void)dyld_cache; +} diff --git a/vendor/lief/doc/code/cpp/dwarf.cpp b/vendor/lief/doc/code/cpp/dwarf.cpp new file mode 100644 index 0000000..5216703 --- /dev/null +++ b/vendor/lief/doc/code/cpp/dwarf.cpp @@ -0,0 +1,138 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +using namespace LIEF::logging; + +void embedded() { + // lief-doc: embedded-start + auto elf = LIEF::ELF::Parser::parse("/bin/with_debug"); + if (const LIEF::DebugInfo* info = elf->debug_info()) { + assert(LIEF::dwarf::DebugInfo::classof(info) && "Wrong debug type"); + + const auto& dwarf_dbg = static_cast(*info); + } + // lief-doc: embedded-end +} + +void load() { + // lief-doc: load-start + auto dbg = LIEF::dwarf::load("/bin/with_debug"); + dbg = LIEF::dwarf::load("external_dwarf"); + dbg = LIEF::dwarf::load("debug.dwo"); + // lief-doc: load-end + (void)dbg; +} + +void iterate() { + // lief-doc: iterate-start + std::unique_ptr dbg; + + for (const LIEF::dwarf::CompilationUnit& CU : dbg->compilation_units()) { + log(Level::Info, "Producer: {}", CU.producer()); + for (const LIEF::dwarf::Function& func : CU.functions()) { + log(Level::Info, "name={}, linkage={}, address={}", func.name(), + func.linkage_name(), std::to_string(func.address().value_or(0))); + } + + for (const LIEF::dwarf::Variable& var : CU.variables()) { + log(Level::Info, "name={}, address={}", var.name(), + std::to_string(var.address().value_or(0))); + } + + for (const LIEF::dwarf::Type& ty : CU.types()) { + log(Level::Info, "name={}, size={}", ty.name().value_or(""), + std::to_string(ty.size().value_or(0))); + } + } + + dbg->find_function("_ZNSi4peekEv"); + dbg->find_function("std::basic_istream >::peek()"); + dbg->find_function(0x137a70); + + dbg->find_variable("_ZNSt12out_of_rangeC1EPKc"); + dbg->find_variable("std::out_of_range::out_of_range(char const*)"); + dbg->find_variable(0x2773a0); + // lief-doc: iterate-end +} + +void load_external() { + // lief-doc: load-external-start + std::unique_ptr binary; + + binary->load_debug_info("/home/romain/dev/LIEF/some.dwo"); + // lief-doc: load-external-end +} + +void disassemble_external() { + // lief-doc: disassemble-start + std::unique_ptr binary; + + binary->load_debug_info("/home/romain/dev/LIEF/some.dwo"); + + // The location (address/size) of `my_function` is defined in some.dwo + for (const LIEF::assembly::Instruction& inst : + binary->disassemble("my_function")) + { + std::cout << inst << '\n'; + } + // lief-doc: disassemble-end +} + +void to_decl() { + // lief-doc: to-decl-start + auto dbg = LIEF::dwarf::load("/bin/with_debug"); + + std::unique_ptr func = dbg->find_function("main"); + std::cout << func->to_decl() << '\n'; + + LIEF::DeclOpt opt; + opt.is_cpp(true).indentation(4); + + for (const LIEF::dwarf::CompilationUnit& CU : dbg->compilation_units()) { + std::cout << CU.to_decl(opt) << '\n'; + } + // lief-doc: to-decl-end +} + +void editor_from_binary() { + // lief-doc: editor-from-binary-start + std::unique_ptr pe = LIEF::PE::Parser::parse("demo.exe"); + + std::unique_ptr editor = + LIEF::dwarf::Editor::from_binary(*pe); + // lief-doc: editor-from-binary-end + (void)editor; +} + +void editor_create() { + // lief-doc: editor-create-start + std::unique_ptr editor; + + std::unique_ptr unit = + editor->create_compilation_unit(); + + unit->set_producer("LIEF"); + + std::unique_ptr func = + unit->create_function("hello"); + + func->set_address(0x123); + + func->set_return_type(*unit->create_structure("my_struct_t")->pointer_to()); + + std::unique_ptr var = + func->create_stack_variable("local_var"); + + var->set_stack_offset(8); + editor->write("/tmp/out.debug"); + // lief-doc: editor-create-end +} diff --git a/vendor/lief/doc/code/cpp/elf.cpp b/vendor/lief/doc/code/cpp/elf.cpp new file mode 100644 index 0000000..e04a313 --- /dev/null +++ b/vendor/lief/doc/code/cpp/elf.cpp @@ -0,0 +1,221 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +using namespace LIEF::ELF; + +void inspect() { + // lief-doc: inspect-start + std::unique_ptr elf; + + std::cout << elf->header().entrypoint(); + + for (const LIEF::ELF::Section& section : elf->sections()) { + std::cout << section.name() << section.content().size() << '\n'; + } + // lief-doc: inspect-end +} + +void modify_write() { + // lief-doc: write-start + std::unique_ptr elf; + + elf->add_library("libdemo.so"); + elf->write("new.elf"); + // lief-doc: write-end +} + +void write_bytes() { + // lief-doc: write-bytes-start + std::unique_ptr elf; + + std::ostringstream os; + elf->write(os); + std::string buffer = os.str(); + + const auto* start = reinterpret_cast(buffer.data()); + size_t size = buffer.size(); + // lief-doc: write-bytes-end + (void)start; + (void)size; +} + +void add_loaded_segment() { + // lief-doc: add-segment-start + std::unique_ptr elf; + + LIEF::ELF::Segment segment; + segment.type(LIEF::ELF::Segment::TYPE::LOAD); + segment.content({1, 2, 3}); + + LIEF::ELF::Segment* new_segment = elf->add(segment); + elf->write("new.elf"); + // lief-doc: add-segment-end + (void)new_segment; +} + +void add_loaded_section() { + // lief-doc: add-section-loaded-start + std::unique_ptr elf; + + LIEF::ELF::Section section(".lief_demo"); + section.content({1, 2, 3}); + + LIEF::ELF::Section* new_section = elf->add(section, /*loaded=*/true); + elf->write("new.elf"); + // lief-doc: add-section-loaded-end + (void)new_section; +} + +void add_unloaded_section() { + // lief-doc: add-section-unloaded-start + std::unique_ptr elf; + + LIEF::ELF::Section section(".metadata"); + section.content({1, 2, 3}); + + LIEF::ELF::Section* new_section = elf->add(section, /*loaded=*/false); + elf->write("new.elf"); + // lief-doc: add-section-unloaded-end + (void)new_section; +} + +void parse_from_dump() { + // lief-doc: dump-start + auto elf = LIEF::ELF::Parser::parse_from_dump("module.dump", 0x7f9b98e00000); + + for (const LIEF::ELF::Segment& segment : elf->segments()) { + std::cout << to_string(segment.type()) << '\n'; + } + // lief-doc: dump-end +} + +void module_dump() { + // lief-doc: dump-runtime-start + // Find the module to dump in the current process + auto mod = LIEF::runtime::module_from_name("libc.so.6"); + + // Dump the module's memory into a file (the raw bytes are also returned) + std::vector data = mod->dump("module.dump"); + + auto elf = LIEF::ELF::Parser::parse_from_dump("module.dump", mod->imagebase()); + // lief-doc: dump-runtime-end + (void)data; + (void)elf; +} + +void advanced_parse_write() { + // lief-doc: advanced-start + LIEF::ELF::ParserConfig parser_config; + parser_config.parse_overlay = false; + + auto elf = LIEF::ELF::Parser::parse("my.elf", parser_config); + + LIEF::ELF::Builder::config_t builder_config; + builder_config.gnu_hash = false; + + elf->write("new.elf", builder_config); + // lief-doc: advanced-end +} + +void rpath_add() { + // lief-doc: rpath-add-start + std::unique_ptr elf; + + LIEF::ELF::DynamicEntryRunPath runpath("$ORIGIN:/opt/lib64"); + + elf->add(runpath); + + LIEF::ELF::DynamicEntryRunPath other_runpath( + std::vector{"$ORIGIN", "/opt/lib64"} + ); + + elf->add(other_runpath); + + elf->write("updated.elf"); + // lief-doc: rpath-add-end +} + +void rpath_change() { + // lief-doc: rpath-change-start + std::unique_ptr elf; + + auto* runpath = elf->get(LIEF::ELF::DynamicEntry::TAG::RUNPATH) + ->cast(); + + assert(runpath != nullptr); + + runpath->runpath("$ORIGIN:/opt/lib64"); + runpath->append("lib-x86_64-gnu"); + + elf->write("updated.elf"); + // lief-doc: rpath-change-end +} + +void rpath_remove() { + // lief-doc: rpath-remove-start + std::unique_ptr elf; + + // Remove **all** DT_RUNPATH entries + elf->remove(LIEF::ELF::DynamicEntry::TAG::RUNPATH); + + // Remove all entries that contain '$ORIGIN' + std::vector to_remove; + for (DynamicEntry& entry : elf->dynamic_entries()) { + if (auto* dt_entry = entry.cast()) { + if (dt_entry->runpath().find("$ORIGIN") != std::string::npos) { + to_remove.push_back(dt_entry); + } + } + } + + for (LIEF::ELF::DynamicEntryRunPath* entry : to_remove) { + elf->remove(*entry); + } + + elf->write("updated.elf"); + // lief-doc: rpath-remove-end +} + +void symver_remove_symbol() { + // lief-doc: symver-symbol-start + std::unique_ptr elf; + + LIEF::ELF::Symbol* sym = elf->get_dynamic_symbol("printf"); + + assert(sym != nullptr); + + sym->symbol_version()->as_global(); + + elf->write("updated.elf"); + // lief-doc: symver-symbol-end +} + +void symver_remove_library() { + // lief-doc: symver-library-start + std::unique_ptr elf; + + elf->remove_version_requirement("libm.so.6"); + + elf->write("updated.elf"); + // lief-doc: symver-library-end +} + +void parse_forms() { + // lief-doc: parse-start + + // Using a file path as a std::string + std::unique_ptr elf = LIEF::ELF::Parser::parse("/bin/ls"); + + // Using a vector + std::vector my_raw_elf; + elf = LIEF::ELF::Parser::parse(my_raw_elf); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/cpp/error_handling.cpp b/vendor/lief/doc/code/cpp/error_handling.cpp new file mode 100644 index 0000000..b17a066 --- /dev/null +++ b/vendor/lief/doc/code/cpp/error_handling.cpp @@ -0,0 +1,16 @@ +#include +#include + +using namespace LIEF; +using namespace LIEF::PE; + +void error_handling() { + // lief-doc: result-handling-start + result pe_type = PE::get_type("/tmp/NotPE.elf"); + if (pe_type) { + PE_TYPE effective_type = pe_type.value(); + } else { + lief_errors err = as_lief_err(pe_type); + } + // lief-doc: result-handling-end +} diff --git a/vendor/lief/doc/code/cpp/intro.cpp b/vendor/lief/doc/code/cpp/intro.cpp new file mode 100644 index 0000000..96933ba --- /dev/null +++ b/vendor/lief/doc/code/cpp/intro.cpp @@ -0,0 +1,22 @@ +#include +#include + + +void intro() { + // lief-doc: intro-start + std::unique_ptr fat = + LIEF::MachO::Parser::parse("libobjc.dylib"); + + for (const LIEF::MachO::Binary& macho : *fat) { + for (const LIEF::MachO::BindingInfo& binding : macho.bindings()) { + std::cout << binding.address() << ' ' << binding.symbol()->name() << '\n'; + } + + if (macho.is_ios()) { + if (const LIEF::MachO::EncryptionInfo* info = macho.encryption_info()) { + std::cout << info->crypt_id() << '\n'; + } + } + } + // lief-doc: intro-end +} diff --git a/vendor/lief/doc/code/cpp/logging.cpp b/vendor/lief/doc/code/cpp/logging.cpp new file mode 100644 index 0000000..0ed958a --- /dev/null +++ b/vendor/lief/doc/code/cpp/logging.cpp @@ -0,0 +1,14 @@ +#include + +void example() { + // lief-doc: example-start + // Set global level to Err + LIEF::logging::set_level(LIEF::logging::Level::Err); + + { + // Temporarily set global level to Debug (RAII) + LIEF::logging::Scoped _(LIEF::logging::Level::Debug); + LIEF::logging::log(LIEF::logging::Level::Debug, "This is a debug message"); + } + // lief-doc: example-end +} diff --git a/vendor/lief/doc/code/cpp/macho.cpp b/vendor/lief/doc/code/cpp/macho.cpp new file mode 100644 index 0000000..4b8da37 --- /dev/null +++ b/vendor/lief/doc/code/cpp/macho.cpp @@ -0,0 +1,148 @@ +#include +#include +#include +#include +#include +#include + +#include +#include + +using namespace LIEF::MachO; + +void iterate() { + // lief-doc: iterate-start + std::unique_ptr fat; + + // Iterate + for (const LIEF::MachO::Binary& macho : *fat) { + std::cout << macho.entrypoint() << '\n'; + std::cout << macho.commands().size() << '\n'; + } + + // Pick one at the specified index (without taking ownership) + const LIEF::MachO::Binary* macho = fat->at(0); + + // Pick one at the specified index and taking ownership + std::unique_ptr owned = fat->take(0); + + // Pick one with the given arch and taking ownership + std::unique_ptr arm64 = + fat->take(LIEF::MachO::Header::CPU_TYPE::ARM64); + // lief-doc: iterate-end + (void)macho; + (void)owned; + (void)arm64; +} + +void write_bytes() { + // lief-doc: write-bytes-start + std::unique_ptr macho; + + std::ostringstream os; + macho->write(os); + std::string buffer = os.str(); + + const auto* start = reinterpret_cast(buffer.data()); + size_t size = buffer.size(); + // lief-doc: write-bytes-end + (void)start; + (void)size; +} + +void parse_from_dump() { + // lief-doc: dump-start + auto fat = LIEF::MachO::Parser::parse_from_dump("module.dump", 0x11e32c000); + const LIEF::MachO::Binary* macho = fat->at(0); + + for (const LIEF::MachO::SegmentCommand& segment : macho->segments()) { + std::cout << segment.name() << '\n'; + } + // lief-doc: dump-end +} + +void module_dump() { + // lief-doc: dump-runtime-start + // Find the module to dump in the current process + auto mod = LIEF::runtime::module_from_name("libsystem_c.dylib"); + + // Dump the module's memory into a file (the raw bytes are also returned) + std::vector data = mod->dump("module.dump"); + + auto fat = LIEF::MachO::Parser::parse_from_dump("module.dump", mod->imagebase()); + // lief-doc: dump-runtime-end + (void)data; + (void)fat; +} + +void rpath_change_lib() { + // lief-doc: rpath-change-lib-start + std::unique_ptr macho = + LIEF::MachO::Parser::parse("hello.bin")->take(0); + + LIEF::MachO::DylibCommand* lib = macho->find_library("libmylib.dylib"); + lib->name("/opt/homebrew/my_package/libmylib.dylib"); + + macho->write("hello_fixed.bin"); + // lief-doc: rpath-change-lib-end +} + +void rpath_add() { + // lief-doc: rpath-add-start + std::unique_ptr macho = + LIEF::MachO::Parser::parse("hello.bin")->take(0); + + auto rpath = LIEF::MachO::RPathCommand::create("/opt/homebrew/my_package"); + macho->add(*rpath); + // lief-doc: rpath-add-end +} + +void rpath_atrpath() { + // lief-doc: rpath-atrpath-start + std::unique_ptr macho; + + LIEF::MachO::DylibCommand* lib = macho->find_library("libmylib.dylib"); + lib->name("@rpath/libmylib.dylib"); + + macho->write("hello_fixed.bin"); + // lief-doc: rpath-atrpath-end +} + +void parse_forms() { + // lief-doc: parse-start + + // Using a file path as a std::string + std::unique_ptr macho = + LIEF::MachO::Parser::parse("/bin/ls"); + + // Using a vector + std::vector my_raw_macho; + macho = LIEF::MachO::Parser::parse(my_raw_macho); + // lief-doc: parse-end +} + +void write_fat() { + // lief-doc: write-fat-start + std::unique_ptr macho; + + macho->take(LIEF::MachO::Header::CPU_TYPE::ARM64)->write("fit.macho"); + macho->write("fat.macho"); + // lief-doc: write-fat-end +} + +void advanced_parse_write() { + // lief-doc: advanced-start + LIEF::MachO::ParserConfig parser_config; + parser_config.parse_dyld_bindings = false; + + std::unique_ptr fat = + LIEF::MachO::Parser::parse("my.macho", parser_config); + + LIEF::MachO::Binary* macho = fat->at(0); + + LIEF::MachO::Builder::config_t builder_config; + builder_config.linkedit = false; + + macho->write("new.macho", builder_config); + // lief-doc: advanced-end +} diff --git a/vendor/lief/doc/code/cpp/memory_layout.cpp b/vendor/lief/doc/code/cpp/memory_layout.cpp new file mode 100644 index 0000000..338fd28 --- /dev/null +++ b/vendor/lief/doc/code/cpp/memory_layout.cpp @@ -0,0 +1,69 @@ +#include +#include +#include +#include +#include + +#include + +void iterate() { + // lief-doc: iterate-start + for (const LIEF::runtime::MemoryLayout::Region& region : + LIEF::runtime::memory_layout()) + { + std::cout << region.addr() << '-' << region.end_addr() << ' ' << region.name() + << '\n'; + } + // lief-doc: iterate-end +} + +void inspect(uint64_t address) { + // lief-doc: inspect-start + size_t count = 0; + uint64_t mapped = 0; + std::unordered_map footprint; + LIEF::runtime::MemoryLayout::Region enclosing; + + for (const LIEF::runtime::MemoryLayout::Region& region : + LIEF::runtime::memory_layout()) + { + ++count; + mapped += region.size(); + + std::string name = + region.name().empty() ? "" : std::string(region.name()); + + footprint[name] += region.size(); + + if (region.contains(address)) { + enclosing = region; + } + } + + std::cout << count << " regions, " << (mapped / 1024) << " KB mapped\n"; + + for (const auto& [name, size] : footprint) { + std::cout << size << ' ' << name << '\n'; + } + + if (enclosing.size() > 0) { + std::cout << address << ": " << enclosing.name() << '+' + << (address - enclosing.addr()) << '\n'; + } + // lief-doc: inspect-end +} + +void stack_and_heap() { + // lief-doc: stack-heap-start + for (const LIEF::runtime::MemoryLayout::Region& region : + LIEF::runtime::memory_layout()) + { + // On Linux and Android, the kernel names the regions that back the stack + // and the heap of the process. + if (region.name() == "[stack]" || region.name() == "[heap]") { + std::cout << region.name() << ": " << region.addr() << '-' + << region.end_addr() << '\n'; + } + } + // lief-doc: stack-heap-end +} diff --git a/vendor/lief/doc/code/cpp/objc.cpp b/vendor/lief/doc/code/cpp/objc.cpp new file mode 100644 index 0000000..8fc0061 --- /dev/null +++ b/vendor/lief/doc/code/cpp/objc.cpp @@ -0,0 +1,34 @@ +#include +#include + +#include +#include + +void check() { + // lief-doc: check-start + std::unique_ptr macho; + + std::unique_ptr metadata = macho->objc_metadata(); + + if (metadata != nullptr) { + std::cout << "Objective metadata found\n"; + } + // lief-doc: check-end +} + +void inspect() { + // lief-doc: inspect-start + std::unique_ptr bin; + + std::unique_ptr metadata = bin->objc_metadata(); + + for (const LIEF::objc::Class& clazz : metadata->classes()) { + std::cout << "name=" << clazz.name() << '\n'; + for (const LIEF::objc::Method& meth : clazz.methods()) { + std::cout << " method.name=" << meth.name() << '\n'; + } + } + + std::cout << metadata->to_decl(); + // lief-doc: inspect-end +} diff --git a/vendor/lief/doc/code/cpp/pdb.cpp b/vendor/lief/doc/code/cpp/pdb.cpp new file mode 100644 index 0000000..a5f6fbd --- /dev/null +++ b/vendor/lief/doc/code/cpp/pdb.cpp @@ -0,0 +1,104 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +using namespace LIEF::logging; + +void load_pdb() { + // lief-doc: load-start + std::unique_ptr pe; + + if (const LIEF::DebugInfo* info = pe->debug_info()) { + assert(LIEF::pdb::DebugInfo::classof(info) && "Wrong DebugInfo type"); + const auto& pdb = static_cast(*info); + } + + // Or loading directly the pdb file + std::unique_ptr pdb = LIEF::pdb::load("some.pdb"); + // lief-doc: load-end + (void)pdb; +} + +void load_ext() { + // lief-doc: load-ext-start + std::unique_ptr binary; + + binary->load_debug_info(R"(C:\Users\romain\LIEF.pdb)"); + // lief-doc: load-ext-end +} + +void disassemble() { + // lief-doc: disassemble-start + std::unique_ptr binary; + + binary->load_debug_info(R"(C:\Users\romain\LIEF.pdb)"); + + // The location (address/size) of `my_function` is defined in LIEF.pdb + for (const LIEF::assembly::Instruction& inst : + binary->disassemble("my_function")) + { + std::cout << inst << '\n'; + } + // lief-doc: disassemble-end +} + +void to_decl() { + // lief-doc: to-decl-start + std::unique_ptr pdb; + + LIEF::DeclOpt opt; + opt.is_cpp(true); + + for (const LIEF::pdb::Type& ty : pdb->types()) { + std::cout << ty.to_decl(opt) << '\n'; + } + + for (const LIEF::pdb::CompilationUnit& CU : pdb->compilation_units()) { + std::cout << CU.to_decl(opt) << '\n'; + for (const LIEF::pdb::Function& func : CU.functions()) { + std::cout << func.to_decl(opt) << '\n'; + } + } + // lief-doc: to-decl-end +} + +void explore() { + // lief-doc: explore-start + std::unique_ptr pdb; + log(Level::Info, "age={}, guid={}", std::to_string(pdb->age()), pdb->guid()); + + for (const LIEF::pdb::PublicSymbol& symbol : pdb->public_symbols()) { + log(Level::Info, "name={}, section={}, RVA={}", symbol.name(), + symbol.section_name(), std::to_string(symbol.RVA())); + } + + for (const LIEF::pdb::Type& ty : pdb->types()) { + if (LIEF::pdb::types::Class::classof(&ty)) { + const auto* clazz = ty.as(); + log(Level::Info, "Class[name]={}", clazz->name().value_or("")); + } + } + + for (const LIEF::pdb::CompilationUnit& CU : pdb->compilation_units()) { + log(Level::Info, "module={}", CU.module_name()); + for (const std::string& src : CU.sources()) { + log(Level::Info, " - {}", src); + } + + for (const LIEF::pdb::Function& func : CU.functions()) { + log(Level::Info, "name={}, section={}, RVA={}, code size={}", func.name(), + func.section_name(), std::to_string(func.RVA()), + std::to_string(func.code_size())); + } + } + // lief-doc: explore-end +} diff --git a/vendor/lief/doc/code/cpp/pe.cpp b/vendor/lief/doc/code/cpp/pe.cpp new file mode 100644 index 0000000..dd6b652 --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe.cpp @@ -0,0 +1,118 @@ +#include +#include +#include +#include +#include +#include + +#include +#include + +using namespace LIEF::PE; + +void inspect() { + // lief-doc: inspect-start + std::unique_ptr pe; + + if (const LIEF::PE::RichHeader* rich = pe->rich_header()) { + std::cout << *rich << '\n'; + } + + for (const LIEF::PE::Section& section : pe->sections()) { + std::cout << section.name() << section.content().size() << '\n'; + } + // lief-doc: inspect-end +} + +void add_section() { + // lief-doc: add-section-start + std::unique_ptr pe; + + LIEF::PE::Section section(".hello"); + section.content(std::vector(0x100, 0xCC)); + pe->add_section(section); + + pe->write("new.exe"); + // lief-doc: add-section-end +} + +void parse_from_dump() { + // lief-doc: dump-start + auto pe = LIEF::PE::Parser::parse_from_dump("module.dump", 0x7ffd21b80000); + + for (const LIEF::PE::Import& imp : pe->imports()) { + std::cout << imp.name() << '\n'; + } + // lief-doc: dump-end +} + +void module_dump() { + // lief-doc: dump-runtime-start + // Find the module to dump in the current process + auto mod = LIEF::runtime::module_from_name("target.dll"); + + // Dump the module's memory into a file (the raw bytes are also returned) + std::vector data = mod->dump("module.dump"); + + auto pe = LIEF::PE::Parser::parse_from_dump("module.dump", mod->imagebase()); + // lief-doc: dump-runtime-end + (void)data; + (void)pe; +} + +void advanced_parse_write() { + // lief-doc: advanced-start + LIEF::PE::ParserConfig parser_config; + parser_config.parse_signature = false; + + auto pe = LIEF::PE::Parser::parse("some.exe", parser_config); + + LIEF::PE::Builder::config_t builder_config; + builder_config.imports = true; + + pe->write("new.exe", builder_config); + // lief-doc: advanced-end +} + +void write_bytes() { + // lief-doc: write-bytes-start + std::unique_ptr pe; + + std::ostringstream os; + pe->write(os); + std::string buffer = os.str(); + + const auto* start = reinterpret_cast(buffer.data()); + size_t size = buffer.size(); + // lief-doc: write-bytes-end + (void)start; + (void)size; +} + +void authenticode() { + // lief-doc: authenticode-start + auto pe = LIEF::PE::Parser::parse("signed.exe"); + + for (const LIEF::PE::Signature& sig : pe->signatures()) { + for (const LIEF::PE::x509& crt : sig.certificates()) { + std::cout << crt << '\n'; + } + } + + std::cout << (pe->verify_signature() == + LIEF::PE::Signature::VERIFICATION_FLAGS::OK) + << '\n'; + // lief-doc: authenticode-end +} + +void parse_forms() { + // lief-doc: parse-start + + // Using a file path as a std::string + std::unique_ptr pe = LIEF::PE::Parser::parse("some.exe"); + + // Using a vector + std::vector my_raw_pe; + pe = LIEF::PE::Parser::parse(my_raw_pe); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/cpp/pe_debug.cpp b/vendor/lief/doc/code/cpp/pe_debug.cpp new file mode 100644 index 0000000..299af47 --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe_debug.cpp @@ -0,0 +1,38 @@ +#include + +#include + +void change_name() { + // lief-doc: change-name-start + std::unique_ptr pe; + + pe->codeview_pdb()->filename(R"(C:\A\B\C\path.pdb)"); + + pe->write("out.dll"); + // lief-doc: change-name-end +} + +void remove() { + // lief-doc: remove-start + std::unique_ptr pe; + + // Remove a single CodeViewPDB entry + pe->remove_debug(*pe->codeview_pdb()); + + // Remove all entries + pe->clear_debug(); + + pe->write("out.dll"); + // lief-doc: remove-end +} + +void add() { + // lief-doc: add-start + std::unique_ptr pe; + + LIEF::PE::CodeViewPDB cv("MyCustom.pdb"); + pe->add_debug_info(cv); + + pe->write("out.dll"); + // lief-doc: add-end +} diff --git a/vendor/lief/doc/code/cpp/pe_exports.cpp b/vendor/lief/doc/code/cpp/pe_exports.cpp new file mode 100644 index 0000000..bc8c2de --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe_exports.cpp @@ -0,0 +1,51 @@ +#include + +#include + +void create_export_entries() { + // lief-doc: create-entries-start + std::unique_ptr pe; + + LIEF::PE::Export* exp = pe->get_export(); + + // Remove an entry + exp->remove_entry("my_exported_name"); + + // Add a new export + exp->add_entry("fuzz_me", 0x10010); + + LIEF::PE::Builder::config_t config; + config.exports = true; + config.export_section = ".myedata"; + + pe->write("out.dll", config); + // lief-doc: create-entries-end +} + +void convert_to_dll() { + // lief-doc: dll-header-start + std::unique_ptr pe; + + pe->header().add_characteristic(LIEF::PE::Header::CHARACTERISTICS::DLL); + pe->optional_header().addressof_entrypoint(0); + // lief-doc: dll-header-end +} + +void create_export_table() { + // lief-doc: create-table-start + std::unique_ptr pe; + + LIEF::PE::Export exp("lib_exe2dll.dll", + { + LIEF::PE::ExportEntry("cbk1", 0x0001000), + LIEF::PE::ExportEntry("cbk2", 0x0001010), + }); + + pe->set_export(exp); + + LIEF::PE::Builder::config_t config; + config.exports = true; + + pe->write("lib_exe2dll.dll", config); + // lief-doc: create-table-end +} diff --git a/vendor/lief/doc/code/cpp/pe_imports.cpp b/vendor/lief/doc/code/cpp/pe_imports.cpp new file mode 100644 index 0000000..0426523 --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe_imports.cpp @@ -0,0 +1,81 @@ +#include +#include +#include + +#include + +void remove_import() { + // lief-doc: remove-import-start + std::unique_ptr pe; + + pe->remove_import("kernel32.dll"); + + LIEF::PE::Builder::config_t config; + config.imports = true; + + pe->write("new.exe", config); + // lief-doc: remove-import-end +} + +void remove_import_entry() { + // lief-doc: remove-import-entry-start + std::unique_ptr pe; + + LIEF::PE::Import* kernel32 = pe->get_import("kernel32.dll"); + kernel32->remove_entry("IsDebuggerPresent"); + + LIEF::PE::Builder::config_t config; + config.imports = true; + + pe->write("new.exe", config); + // lief-doc: remove-import-entry-end +} + +void add_import() { + // lief-doc: add-import-start + std::unique_ptr pe; + + LIEF::PE::Import& stdio = pe->add_import("api-ms-win-crt-stdio-l1-1-0.dll"); + LIEF::PE::ImportEntry& _puts = stdio.add_entry("puts"); + + LIEF::PE::Builder::config_t config; + config.imports = true; + + pe->write("new.exe", config); + // lief-doc: add-import-end + (void)_puts; +} + +void add_import_cbk() { + // lief-doc: add-import-cbk-start + std::unique_ptr pe; + + LIEF::PE::Import& stdio = pe->add_import("api-ms-win-crt-stdio-l1-1-0.dll"); + LIEF::PE::ImportEntry& _puts = stdio.add_entry("puts"); + + LIEF::PE::Builder::config_t config; + config.imports = true; + config.resolved_iat_cbk = [](LIEF::PE::Binary* pe, const LIEF::PE::Import* imp, + const LIEF::PE::ImportEntry* entry, + uint32_t RVA) -> void { + // Process + return; + }; + + pe->write("new.exe", config); + // lief-doc: add-import-cbk-end + (void)_puts; +} + +void add_import_func() { + // lief-doc: add-import-func-start + std::unique_ptr pe; + LIEF::PE::Import& kernel32 = pe->add_import("kernel32.dll"); + LIEF::PE::ImportEntry& _GetStartupInfoW = kernel32.add_entry("GetStartupInfoW"); + + LIEF::PE::Builder::config_t config; + config.imports = true; + + pe->write("new.exe", config); + // lief-doc: add-import-func-end +} diff --git a/vendor/lief/doc/code/cpp/pe_resources.cpp b/vendor/lief/doc/code/cpp/pe_resources.cpp new file mode 100644 index 0000000..bcda0c3 --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe_resources.cpp @@ -0,0 +1,69 @@ +#include +#include +#include +#include + +#include +#include + +using namespace LIEF; +using namespace LIEF::PE; + +void access_root() { + // lief-doc: access-root-start + std::unique_ptr pe; + + LIEF::PE::ResourceNode* rsrc = pe->resources(); + + std::cout << *rsrc << '\n'; + // lief-doc: access-root-end +} + +void add_child() { + // lief-doc: add-child-start + std::unique_ptr pe; + + LIEF::PE::ResourceNode* root = pe->resources(); + + LIEF::PE::ResourceDirectory dir_node(/*id=*/100); + LIEF::PE::ResourceData data_node(std::vector{1, 2, 3}); + + (*root).add_child(dir_node).add_child(data_node); + + pe->write("new.exe"); + // lief-doc: add-child-end +} + +void set_manifest() { + // lief-doc: manifest-start + std::unique_ptr pe; + + result manager = pe->resources_manager(); + manager->manifest(R"manifest( + + + + + + + + + + + )manifest"); + + pe->write("new.exe"); + // lief-doc: manifest-end +} + +void transfer_resources() { + // lief-doc: transfer-start + std::unique_ptr from; + std::unique_ptr to; + + to->set_resources(*from->resources()); + + to->write("new.exe"); + // lief-doc: transfer-end +} diff --git a/vendor/lief/doc/code/cpp/pe_tls.cpp b/vendor/lief/doc/code/cpp/pe_tls.cpp new file mode 100644 index 0000000..e0bc449 --- /dev/null +++ b/vendor/lief/doc/code/cpp/pe_tls.cpp @@ -0,0 +1,49 @@ +#include +#include +#include +#include + +#include + +using namespace LIEF::PE; + +void modify_callbacks() { + // lief-doc: modify-callbacks-start + std::unique_ptr pe; + + TLS* tls = pe->tls(); + + std::vector callbacks = tls->callbacks(); + + // Remove the last entry + callbacks.pop_back(); + + // Add an address + callbacks.push_back(0x140001010); + + tls->callbacks(std::move(callbacks)); + + pe->write("tls_modified.exe"); + // lief-doc: modify-callbacks-end +} + +void create_tls() { + // lief-doc: create-tls-start + LIEF::PE::TLS tls; + + tls.callbacks(std::vector{ + 0x140001000, + 0x140001010, + }); + // lief-doc: create-tls-end + (void)tls; +} + +void add_tls(std::unique_ptr& pe) { + LIEF::PE::TLS tls; + // lief-doc: add-tls-start + pe->tls(tls); // `tls` defined previously + + pe->write("tls_demo.exe"); + // lief-doc: add-tls-end +} diff --git a/vendor/lief/doc/code/cpp/tuto_authenticode.cpp b/vendor/lief/doc/code/cpp/tuto_authenticode.cpp new file mode 100644 index 0000000..7394814 --- /dev/null +++ b/vendor/lief/doc/code/cpp/tuto_authenticode.cpp @@ -0,0 +1,16 @@ +#include +#include + +// lief-doc: ios-main-start +#include + +int main(int argc, char** argv) { + std::unique_ptr pe = LIEF::PE::Parser::parse(argv[1]); + if (pe->verify_signature() == LIEF::PE::Signature::VERIFICATION_FLAGS::OK) { + std::cout << "Signature ok!" << "\n"; + return 0; + } + std::cout << "Error!" << "\n"; + return 1; +} +// lief-doc: ios-main-end diff --git a/vendor/lief/doc/code/cpp/tuto_coredump.cpp b/vendor/lief/doc/code/cpp/tuto_coredump.cpp new file mode 100644 index 0000000..d4647a6 --- /dev/null +++ b/vendor/lief/doc/code/cpp/tuto_coredump.cpp @@ -0,0 +1,15 @@ +#include + +#include + +using namespace LIEF::ELF; + +void corefile_downcast(std::unique_ptr& binary) { + // lief-doc: corefile-downcast-start + for (const Note& note : binary->notes()) { + if (CoreFile::classof(¬e)) { + const auto& nt_core_file = static_cast(note); + } + } + // lief-doc: corefile-downcast-end +} diff --git a/vendor/lief/doc/code/python/abstract.py b/vendor/lief/doc/code/python/abstract.py new file mode 100644 index 0000000..e9fbef3 --- /dev/null +++ b/vendor/lief/doc/code/python/abstract.py @@ -0,0 +1,22 @@ +import lief + + +def parse_forms() -> None: + # lief-doc: parse-start + target = lief.parse("/tmp/some.elf") + + target = lief.parse("/Users/demo/some.macho") + + target = lief.parse(r"C:\some.pe.exe") + # lief-doc: parse-end + _ = target + + +def upcast() -> None: + # lief-doc: upcast-start + target = lief.parse("some.elf") + assert type(target) is lief.ELF.Binary + + abstract = target.abstract + assert type(abstract) is lief.Binary + # lief-doc: upcast-end diff --git a/vendor/lief/doc/code/python/assembler.py b/vendor/lief/doc/code/python/assembler.py new file mode 100644 index 0000000..fdccb40 --- /dev/null +++ b/vendor/lief/doc/code/python/assembler.py @@ -0,0 +1,105 @@ +from typing import override + +import lief + + +def disassemble_assemble(elf: lief.ELF.Binary) -> None: + # lief-doc: disassemble-assemble-start + elf: lief.ELF.Binary + + syscall_addresses = [ + inst.address for inst in elf.disassemble(0x400090) if inst.is_syscall + ] + + for syscall_addr in syscall_addresses: + elf.assemble( + syscall_addr, + """ + mov x1, x0; + str x1, [x2, #8]; + """, + ) + # lief-doc: disassemble-assemble-end + + +def context_error(elf: lief.ELF.Binary) -> None: + # lief-doc: context-error-start + elf: lief.ELF.Binary + + elf.assemble( + elf.entrypoint, + """ + mov rdi, rax; + call a_custom_function; + """, + ) + # lief-doc: context-error-end + + +def config_resolver(elf: lief.ELF.Binary) -> None: + # lief-doc: config-resolver-start + class MyConfig(lief.assembly.AssemblerConfig): + def __init__(self): + super().__init__() # Important! + + @override + def resolve_symbol(self, name: str) -> int | None: + if name == "a_custom_function": + return 0x1000 + return None + + elf: lief.ELF.Binary + + elf.assemble( + elf.entrypoint, + """ + mov rdi, rax; + call a_custom_function; + """, + MyConfig(), + ) + # lief-doc: config-resolver-end + + +def config_target(elf: lief.ELF.Binary) -> None: + # lief-doc: config-target-start + class MyConfig(lief.assembly.AssemblerConfig): + def __init__(self, target: lief.Binary): + super().__init__() # Important! + + self._target = target + + @override + def resolve_symbol(self, name: str) -> int | None: + addr = self._target.get_function_address(name) + if isinstance(addr, lief.lief_errors): + return None + return addr + + elf: lief.ELF.Binary + config = MyConfig(elf) + + elf.assemble( + elf.entrypoint, + """ + mov rdi, rax; + call a_custom_function; + """, + config, + ) + # lief-doc: config-target-end + + +def disable_instruction(elf: lief.ELF.Binary) -> None: + # lief-doc: nop-out-start + elf: lief.ELF.Binary + + # Overwrite the first call in the region (e.g. a call to an anti-debugging + # routine) with nops + for inst in elf.disassemble(0x401200): + if inst.is_call: + elf.assemble(inst.address, "nop\n" * inst.size) + break + + elf.write("patched.bin") + # lief-doc: nop-out-end diff --git a/vendor/lief/doc/code/python/coff.py b/vendor/lief/doc/code/python/coff.py new file mode 100644 index 0000000..00039a6 --- /dev/null +++ b/vendor/lief/doc/code/python/coff.py @@ -0,0 +1,43 @@ +import pathlib + +import lief + + +def sections(coff: lief.COFF.Binary) -> None: + # lief-doc: sections-start + coff: lief.COFF.Binary + + for section in coff.sections: + print(section.name) + # lief-doc: sections-end + + +def disassemble(coff: lief.COFF.Binary) -> None: + # lief-doc: disassemble-start + coff: lief.COFF.Binary + + for inst in coff.disassemble("?foo@@YAHHH@Z"): + print(inst) + + # Using demangled representation + for inst in coff.disassemble("int __cdecl bar(int, int)"): + print(inst) + # lief-doc: disassemble-end + + +def parse_forms() -> lief.COFF.Binary | None: + # lief-doc: parse-start + + # Using a filepath as a string + coff: lief.COFF.Binary | None = lief.COFF.parse("hello.obj") + + # Using a Path from pathlib + coff: lief.COFF.Binary | None = lief.COFF.parse( + pathlib.Path(r"C:\Users\romain\test.obj") + ) + + # Using an io object + with open("/tmp/test.ob", "rb") as f: + coff: lief.COFF.Binary | None = lief.COFF.parse(f) + # lief-doc: parse-end + return coff diff --git a/vendor/lief/doc/code/python/disassembler.py b/vendor/lief/doc/code/python/disassembler.py new file mode 100644 index 0000000..7280b3f --- /dev/null +++ b/vendor/lief/doc/code/python/disassembler.py @@ -0,0 +1,101 @@ +import lief + + +def disassemble(elf: lief.ELF.Binary) -> None: + # lief-doc: disassemble-start + elf: lief.ELF.Binary + + for inst in elf.disassemble(0x400120): + print(inst) + # lief-doc: disassemble-end + + +def check_opcode( + inst: lief.assembly.Instruction, +) -> "lief.assembly.riscv.OPCODE | None": + # lief-doc: downcast-start + inst: lief.assembly.Instruction + + match inst: + case lief.assembly.riscv.Instruction(): + opcode: lief.assembly.riscv.OPCODE = inst.opcode + # lief-doc: downcast-end + return opcode + return None + + +def dsc_disassemble(dyld_cache: lief.dsc.DyldSharedCache) -> None: + # lief-doc: dsc-disassemble-start + dyld_cache: lief.dsc.DyldSharedCache + + for inst in dyld_cache.disassemble(0x1886F4A44): + print(inst) + # lief-doc: dsc-disassemble-end + + +def operands_aarch64(macho: lief.MachO.Binary) -> None: + # lief-doc: operands-aarch64-start + macho: lief.MachO.Binary + + for inst in macho.disassemble(0x400120): + print(inst) + # Check inst properties + if inst.is_branch: + print(f"Resolved: {inst.branch_target}") + + for idx, operand in enumerate(inst.operands): + match operand: + case lief.assembly.aarch64.operands.Register(): + print(f"op[{idx}]: REG - {operand.value}") + case lief.assembly.aarch64.operands.Memory(): + print(f"op[{idx}]: MEM - {operand.base}") + case lief.assembly.aarch64.operands.PCRelative(): + print(f"op[{idx}]: PCR - {operand.value}") + case lief.assembly.aarch64.operands.Immediate(): + print(f"op[{idx}]: IMM - {operand.value}") + # lief-doc: operands-aarch64-end + + +def operands_x86(elf: lief.ELF.Binary) -> None: + # lief-doc: operands-x86-start + elf: lief.ELF.Binary + + for inst in elf.disassemble(0x1000200): + print(inst) + # Check inst properties + if inst.is_branch: + print(f"Resolved: {inst.branch_target}") + + for idx, operand in enumerate(inst.operands): + match operand: + case lief.assembly.x86.operands.Register(): + print(f"op[{idx}]: REG - {operand.value}") + case lief.assembly.x86.operands.Memory(): + print(f"op[{idx}]: MEM - {operand.base}") + case lief.assembly.x86.operands.PCRelative(): + print(f"op[{idx}]: PCR - {operand.value}") + case lief.assembly.x86.operands.Immediate(): + print(f"op[{idx}]: IMM - {operand.value}") + # lief-doc: operands-x86-end + + +def dwarf_function() -> None: + # lief-doc: dwarf-func-start + elf = lief.ELF.parse("/bin/hello") + + main = elf.debug_info.find_function("main") + + for inst in main.instructions: + print(inst) + # lief-doc: dwarf-func-end + + +def x86_lock(inst: lief.assembly.x86.Instruction) -> None: + # lief-doc: x86-lock-start + inst: lief.assembly.x86.Instruction + + if inst.has_lock_prefix or inst.is_atomic: + print(f"{inst} is atomic") + elif inst.is_lockable and (locked := inst.lock()) is not None: + print(f"atomic version of {inst}: {locked}") + # lief-doc: x86-lock-end diff --git a/vendor/lief/doc/code/python/dsc.py b/vendor/lief/doc/code/python/dsc.py new file mode 100644 index 0000000..c9c9e4c --- /dev/null +++ b/vendor/lief/doc/code/python/dsc.py @@ -0,0 +1,58 @@ +import lief + + +def load() -> lief.dsc.DyldSharedCache | None: + # lief-doc: load-start + dyld_cache: lief.dsc.DyldSharedCache | None = lief.dsc.load("macos-15.0.1/") + # lief-doc: load-end + return dyld_cache + + +def iterate_libraries(dyld_cache: lief.dsc.DyldSharedCache) -> None: + # lief-doc: libraries-start + dyld_cache: lief.dsc.DyldSharedCache + + for dylib in dyld_cache.libraries: + print(f"{dylib.address:#016x}: {dylib.path}") + # lief-doc: libraries-end + + +def extract(dyld_cache: lief.dsc.DyldSharedCache) -> None: + # lief-doc: extract-start + dyld_cache: lief.dsc.DyldSharedCache + + liblockdown = dyld_cache.find_lib_from_name("liblockdown.dylib") + + macho = liblockdown.get() + + for segment in macho.segments: + print(segment.name) + # lief-doc: extract-end + + +def write_back(dyld_cache: lief.dsc.DyldSharedCache) -> None: + # lief-doc: write-start + dyld_cache: lief.dsc.DyldSharedCache + + liblockdown = dyld_cache.find_lib_from_name("liblockdown.dylib") + + macho = liblockdown.get() + macho.write("on-disk-liblockdown.dylib") + # lief-doc: write-end + + +def random_access(dyld_cache: lief.dsc.DyldSharedCache) -> lief.dsc.Dylib | None: + # lief-doc: random-access-start + dyld_cache: lief.dsc.DyldSharedCache + + # No cost + libraries = dyld_cache.libraries + + # O(1) cost + first_lib = libraries[0] + + # O(len(libraries)) cost + for lib in libraries: + print(lib.path) + # lief-doc: random-access-end + return first_lib diff --git a/vendor/lief/doc/code/python/dwarf.py b/vendor/lief/doc/code/python/dwarf.py new file mode 100644 index 0000000..37f9c67 --- /dev/null +++ b/vendor/lief/doc/code/python/dwarf.py @@ -0,0 +1,118 @@ +import lief + + +def embedded() -> None: + # lief-doc: embedded-start + + elf = lief.ELF.parse("/bin/with_debug") + if debug_info := elf.debug_info: + assert isinstance(debug_info, lief.dwarf.DebugInfo) + print(f"DWARF Debug handler: {debug_info}") + # lief-doc: embedded-end + + +def load() -> lief.dwarf.DebugInfo | None: + # lief-doc: load-start + + dbg: lief.dwarf.DebugInfo | None = lief.dwarf.load("/bin/with_debug") + dbg: lief.dwarf.DebugInfo | None = lief.dwarf.load("external_dwarf") + dbg: lief.dwarf.DebugInfo | None = lief.dwarf.load("debug.dwo") + # lief-doc: load-end + return dbg + + +def iterate(dbg: lief.dwarf.DebugInfo) -> None: + # lief-doc: iterate-start + dbg: lief.dwarf.DebugInfo + + for compilation_unit in dbg.compilation_units: + print(compilation_unit.producer) + for func in compilation_unit.functions: + print(func.name, func.linkage_name, func.address) + + for var in compilation_unit.variables: + print(var.name, var.address) + + for ty in compilation_unit.types: + print(ty.name, ty.size) + + dbg.find_function("_ZNSi4peekEv") + dbg.find_function("std::basic_istream >::peek()") + dbg.find_function(0x137A70) + + dbg.find_variable("_ZNSt12out_of_rangeC1EPKc") + dbg.find_variable("std::out_of_range::out_of_range(char const*)") + dbg.find_variable(0x2773A0) + + dbg.find_type("my_type_t") + # lief-doc: iterate-end + + +def load_external(binary: lief.Binary) -> lief.DebugInfo | None: + # lief-doc: load-external-start + binary: lief.Binary + + dbg = binary.load_debug_info("/home/romain/dev/LIEF/some.dwo") + # lief-doc: load-external-end + return dbg + + +def disassemble_external(binary: lief.Binary) -> None: + # lief-doc: disassemble-start + binary: lief.Binary + + binary.load_debug_info("/home/romain/dev/LIEF/some.dwo") + + # The location (address/size) of `my_function` is defined in some.dwo + for inst in binary.disassemble("my_function"): + print(inst) + # lief-doc: disassemble-end + + +def to_decl() -> None: + # lief-doc: to-decl-start + dbg = lief.dwarf.load("/bin/with_debug") + + func = dbg.find_function("main") + print(func.to_decl()) + + opt = lief.DeclOpt() + opt.is_cpp = True + opt.indentation = 4 + + for cu in dbg.compilation_units: + # Emit the definition of the functions of the compilation unit + print(cu.to_decl(opt)) + # lief-doc: to-decl-end + + +def editor_from_binary() -> lief.dwarf.Editor | None: + # lief-doc: editor-from-binary-start + pe = lief.PE.parse("demo.exe") + assert isinstance(pe, lief.PE.Binary) + + editor = lief.dwarf.Editor.from_binary(pe) + # lief-doc: editor-from-binary-end + return editor + + +def editor_create(editor: lief.dwarf.Editor) -> None: + # lief-doc: editor-create-start + editor: lief.dwarf.Editor + + unit = editor.create_compilation_unit() + unit.set_producer("LIEF") + + func = unit.create_function("hello") + func.set_address(0x123) + + struct_ptr = unit.create_structure("my_struct_t").pointer_to() + assert isinstance(struct_ptr, lief.dwarf.editor.PointerType) + + func.set_return_type(struct_ptr) + + var = func.create_stack_variable("local_var") + var.set_stack_offset(8) + + editor.write("/tmp/out.debug") + # lief-doc: editor-create-end diff --git a/vendor/lief/doc/code/python/elf.py b/vendor/lief/doc/code/python/elf.py new file mode 100644 index 0000000..566e886 --- /dev/null +++ b/vendor/lief/doc/code/python/elf.py @@ -0,0 +1,210 @@ +import pathlib + +import lief + + +def inspect(elf: lief.ELF.Binary) -> None: + # lief-doc: inspect-start + elf: lief.ELF.Binary + + print(elf.header.entrypoint) + + for section in elf.sections: + print(section.name, len(section.content)) + # lief-doc: inspect-end + + +def modify_write(elf: lief.ELF.Binary) -> None: + # lief-doc: write-start + elf: lief.ELF.Binary + + elf.add_library("libdemo.so") + elf.write("new.elf") + # lief-doc: write-end + + +def write_bytes(elf: lief.ELF.Binary) -> bytes: + # lief-doc: write-bytes-start + elf: lief.ELF.Binary + + new_elf: bytes = elf.write_to_bytes() + # lief-doc: write-bytes-end + return new_elf + + +def add_loaded_segment(elf: lief.ELF.Binary) -> lief.ELF.Segment | None: + # lief-doc: add-segment-start + elf: lief.ELF.Binary + + segment = lief.ELF.Segment() + segment.type = lief.ELF.Segment.TYPES.LOAD + segment.content = list(b"Hello World") + + new_segment = elf.add(segment) + + elf.write("new.elf") + # lief-doc: add-segment-end + return new_segment + + +def add_loaded_section(elf: lief.ELF.Binary) -> lief.ELF.Section | None: + # lief-doc: add-section-loaded-start + elf: lief.ELF.Binary + + section = lief.ELF.Section(".lief_demo") + section.content = list(b"Hello World") + + new_section = elf.add(section, loaded=True) + + elf.write("new.elf") + # lief-doc: add-section-loaded-end + return new_section + + +def add_unloaded_section(elf: lief.ELF.Binary) -> lief.ELF.Section | None: + # lief-doc: add-section-unloaded-start + elf: lief.ELF.Binary + + section = lief.ELF.Section(".metadata") + section.content = list(b"version: 1.2.3") + + # /!\ Note that loaded is set to False here + # ------------------------------------------ + new_section = elf.add(section, loaded=False) + + elf.write("new.elf") + # lief-doc: add-section-unloaded-end + return new_section + + +def parse_from_dump() -> None: + # lief-doc: dump-start + # 0x7f9b98e00000 is the (absolute) address at which the dump was mapped + elf = lief.ELF.parse_from_dump("module.dump", 0x7F9B98E00000) + assert elf is not None + + for segment in elf.segments: + print(segment.type, hex(segment.virtual_address)) + # lief-doc: dump-end + + +def module_dump() -> None: + # lief-doc: dump-runtime-start + # Find the module to dump in the current process + mod = lief.runtime.module_from_name("libc.so.6") + assert mod is not None + + # Dump the module's memory into a file (the raw bytes are also returned) + data: bytes = mod.dump("module.dump") + + # and parse it back using the same imagebase: + elf = lief.ELF.parse_from_dump(data, mod.imagebase) + # lief-doc: dump-runtime-end + assert elf is not None + + +def advanced_parse_write() -> None: + # lief-doc: advanced-start + parser_config = lief.ELF.ParserConfig() + parser_config.parse_overlay = False + + elf = lief.ELF.parse("my.elf", parser_config) + assert isinstance(elf, lief.ELF.Binary) + + builder_config = lief.ELF.Builder.config_t() + builder_config.gnu_hash = False + + elf.write("new.elf", builder_config) + # lief-doc: advanced-end + + +def rpath_add(elf: lief.ELF.Binary) -> None: + # lief-doc: rpath-add-start + elf: lief.ELF.Binary + + runpath = lief.ELF.DynamicEntryRunPath("$ORIGIN:/opt/lib64") + + elf.add(runpath) + + other_runpath = lief.ELF.DynamicEntryRunPath(["$ORIGIN", "/opt/lib64"]) + + elf.add(other_runpath) + + elf.write("updated.elf") + # lief-doc: rpath-add-end + + +def rpath_change(elf: lief.ELF.Binary) -> None: + # lief-doc: rpath-change-start + elf: lief.ELF.Binary + + runpath = elf.get(lief.ELF.DynamicEntry.TAG.RUNPATH) + assert runpath is not None + + runpath.runpath = "$ORIGIN:/opt/lib64" + runpath.append("lib-x86_64-gnu") + + elf.write("updated.elf") + # lief-doc: rpath-change-end + + +def rpath_remove(elf: lief.ELF.Binary) -> None: + # lief-doc: rpath-remove-start + elf: lief.ELF.Binary + + # Remove **all** DT_RUNPATH entries + elf.remove(lief.ELF.DynamicEntry.TAG.RUNPATH) + + # Remove all entries that contain '$ORIGIN' + to_remove: list[lief.ELF.DynamicEntryRunPath] = [] + for dt_entry in elf.dynamic_entries: + if not isinstance(dt_entry, lief.ELF.DynamicEntryRunPath): + continue + + if "$ORIGIN" in dt_entry.runpath: + to_remove.append(dt_entry) + + for entry in to_remove: + elf.remove(entry) + + elf.write("updated.elf") + # lief-doc: rpath-remove-end + + +def symver_remove_symbol(elf: lief.ELF.Binary) -> None: + # lief-doc: symver-symbol-start + elf: lief.ELF.Binary + + sym = elf.get_dynamic_symbol("printf") + assert sym is not None and sym.symbol_version is not None + + sym.symbol_version.as_global() + + elf.write("updated.elf") + # lief-doc: symver-symbol-end + + +def symver_remove_library(elf: lief.ELF.Binary) -> None: + # lief-doc: symver-library-start + elf: lief.ELF.Binary + + elf.remove_version_requirement("libm.so.6") + + elf.write("updated.elf") + # lief-doc: symver-library-end + + +def parse_forms() -> lief.ELF.Binary | None: + # lief-doc: parse-start + + # Using filepath + elf: lief.ELF.Binary | None = lief.ELF.parse("/bin/ls") + + # Using a Path from pathlib + elf: lief.ELF.Binary | None = lief.ELF.parse(pathlib.Path(r"C:\Users\test.elf")) + + # Using an io object + with open("/bin/ssh", "rb") as f: + elf: lief.ELF.Binary | None = lief.ELF.parse(f) + # lief-doc: parse-end + return elf diff --git a/vendor/lief/doc/code/python/error_handling.py b/vendor/lief/doc/code/python/error_handling.py new file mode 100644 index 0000000..a3a6598 --- /dev/null +++ b/vendor/lief/doc/code/python/error_handling.py @@ -0,0 +1,27 @@ +# ruff: noqa: BLE001 +import lief + + +def get_type_exception() -> lief.PE.PE_TYPE | lief.lief_errors | None: + pe_type: lief.PE.PE_TYPE | lief.lief_errors | None = None + # lief-doc: get-type-exception-start + try: + pe_type = lief.PE.get_type("/tmp/NotPE.elf") + # If it does not fail, pe_type handles a lief.PE.PE_TYPE object + except Exception as e: + print(f"Error: {e}") + # lief-doc: get-type-exception-end + return pe_type + + +def get_type_error() -> None: + # lief-doc: get-type-error-start + pe_type = lief.PE.get_type("/tmp/NotPE.elf") + + if pe_type == lief.lief_errors.file_error: + print("File error") + elif isinstance(pe_type, lief.lief_errors): + print("Another kind of error") + else: + print(f"No error, type is: {pe_type}") + # lief-doc: get-type-error-end diff --git a/vendor/lief/doc/code/python/intro.py b/vendor/lief/doc/code/python/intro.py new file mode 100644 index 0000000..1147a53 --- /dev/null +++ b/vendor/lief/doc/code/python/intro.py @@ -0,0 +1,20 @@ +import lief + + +def intro() -> None: + # lief-doc: intro-start + + elf: lief.ELF.Binary | None = lief.ELF.parse("libc.so") + assert elf is not None + + for symbol in elf.symbols: + print(symbol.address, symbol.name) + + print(elf.header) + + for entry in elf.dynamic_entries: + if isinstance(entry, lief.ELF.DynamicEntryLibrary): + entry.name = "libhello.so" + + elf.write("modified.elf") + # lief-doc: intro-end diff --git a/vendor/lief/doc/code/python/logging.py b/vendor/lief/doc/code/python/logging.py new file mode 100644 index 0000000..bfad2e5 --- /dev/null +++ b/vendor/lief/doc/code/python/logging.py @@ -0,0 +1,12 @@ +import lief + + +def example() -> None: + # lief-doc: example-start + # Set global level to Err + lief.logging.set_level(lief.logging.Level.Err) + + # Temporarily set global level to Debug + with lief.logging.level_scope(lief.logging.Level.Debug): + lief.logging.log(lief.logging.Level.Debug, "This is a debug message") + # lief-doc: example-end diff --git a/vendor/lief/doc/code/python/macho.py b/vendor/lief/doc/code/python/macho.py new file mode 100644 index 0000000..c2fa358 --- /dev/null +++ b/vendor/lief/doc/code/python/macho.py @@ -0,0 +1,158 @@ +import pathlib + +import lief + + +def iterate(fat: lief.MachO.FatBinary) -> lief.MachO.Binary | None: + # lief-doc: iterate-start + fat: lief.MachO.FatBinary + + # Iterate + for macho in fat: + print(macho.entrypoint) + print(len(macho.commands)) + + # Pick one at the specified index + macho = fat.at(0) + + # Pick one based on the architecture + macho = fat.take(lief.MachO.Header.CPU_TYPE.ARM64) + # lief-doc: iterate-end + return macho + + +def write_bytes(macho: lief.MachO.Binary) -> bytes: + # lief-doc: write-bytes-start + macho: lief.MachO.Binary + + new_macho: bytes = macho.write_to_bytes() + # lief-doc: write-bytes-end + return new_macho + + +def parse_from_dump() -> None: + # lief-doc: dump-start + # 0x11e32c000 is the (absolute) address at which the dump was mapped + fat = lief.MachO.parse_from_dump("module.dump", 0x11E32C000) + assert isinstance(fat, lief.MachO.FatBinary) + + macho = fat.at(0) + assert isinstance(fat, lief.MachO.Binary) + + for segment in macho.segments: + print(segment.name, hex(segment.virtual_address)) + # lief-doc: dump-end + + +def module_dump() -> None: + # lief-doc: dump-runtime-start + # Find the module to dump in the current process + mod = lief.runtime.module_from_name("libsystem_c.dylib") + assert isinstance(mod, lief.runtime.osx.Module) + + # Dump the module's memory into a file (the raw bytes are also returned) ... + data: bytes = mod.dump("module.dump") + + # ... and parse it back using the same imagebase: + macho = lief.MachO.parse_from_dump(data, mod.imagebase) + # lief-doc: dump-runtime-end + assert isinstance(macho, lief.MachO.FatBinary) + + +def rpath_atrpath(macho: lief.MachO.Binary) -> None: + # lief-doc: rpath-atrpath-start + macho: lief.MachO.Binary + + lib = macho.find_library("libmylib.dylib") + assert isinstance(lib, lief.MachO.DylibCommand) + + lib.name = "@rpath/libmylib.dylib" + + macho.write("hello_fixed.bin") + # lief-doc: rpath-atrpath-end + + +def parse_forms() -> lief.MachO.FatBinary | None: + # lief-doc: parse-start + + # Using filepath + macho: lief.MachO.FatBinary | None = lief.MachO.parse("/bin/ls") + + # Using a Path from pathlib + macho: lief.MachO.FatBinary | None = lief.MachO.parse( + pathlib.Path(r"C:\Users\test.macho") + ) + + # Using an io object + with open("/bin/ssh", "rb") as f: + macho: lief.MachO.FatBinary | None = lief.MachO.parse(f) + # lief-doc: parse-end + return macho + + +def write_fat(macho: lief.MachO.FatBinary) -> None: + # lief-doc: write-fat-start + macho: lief.MachO.FatBinary + + macho.at(0).write("fit.macho") + macho.write("fat.macho") # write-back the whole FAT binary + # lief-doc: write-fat-end + + +def advanced_parse_write() -> None: + # lief-doc: advanced-start + parser_config = lief.MachO.ParserConfig() + parser_config.parse_dyld_bindings = False + + fat = lief.MachO.parse("my.macho", parser_config) + assert isinstance(fat, lief.MachO.FatBinary) + + macho = fat.at(0) + assert isinstance(fat, lief.MachO.Binary) + + builder_config = lief.MachO.Builder.config_t() + builder_config.linkedit = False + + macho.write("new.macho", builder_config) + # lief-doc: advanced-end + + +def rpath_change_lib() -> None: + # lief-doc: rpath-change-lib-start + fat = lief.MachO.parse("hello.bin") + assert isinstance(fat, lief.MachO.FatBinary) + + macho = fat.at(0) + assert isinstance(fat, lief.MachO.Binary) + + lib = macho.find_library("libmylib.dylib") + assert isinstance(lib, lief.MachO.DylibCommand) + + lib.name = "/opt/homebrew/my_package/libmylib.dylib" + + macho.write("hello_fixed.bin") + # lief-doc: rpath-change-lib-end + + +def rpath_add() -> None: + # lief-doc: rpath-add-start + fat = lief.MachO.parse("hello.bin") + assert isinstance(fat, lief.MachO.FatBinary) + + macho = fat.at(0) + assert isinstance(fat, lief.MachO.Binary) + + rpath = lief.MachO.RPathCommand.create("/opt/homebrew/my_package") + assert isinstance(rpath, lief.MachO.RPathCommand) + + macho.add(rpath) + # lief-doc: rpath-add-end + + +def parse_config() -> None: + # lief-doc: parse-config-start + fatbinary_1 = lief.MachO.parse("/usr/bin/ls", config=lief.MachO.ParserConfig.deep) + # or + fatbinary_2 = lief.MachO.parse("/usr/bin/ls", config=lief.MachO.ParserConfig.quick) + # lief-doc: parse-config-end + _ = (fatbinary_1, fatbinary_2) diff --git a/vendor/lief/doc/code/python/memory_layout.py b/vendor/lief/doc/code/python/memory_layout.py new file mode 100644 index 0000000..2d15228 --- /dev/null +++ b/vendor/lief/doc/code/python/memory_layout.py @@ -0,0 +1,49 @@ +from collections import defaultdict + +import lief + + +def iterate() -> None: + # lief-doc: iterate-start + for region in lief.runtime.memory_layout(): + print(f"{region.addr:#014x}-{region.end_addr:#014x} {region.name}") + # lief-doc: iterate-end + + +def inspect(address: int) -> None: + # lief-doc: inspect-start + address: int + + count = 0 + mapped = 0 + footprint: defaultdict[str, int] = defaultdict(int) + enclosing: lief.runtime.MemoryLayout.Region | None = None + + for region in lief.runtime.memory_layout(): + count += 1 + mapped += region.size + + name = region.name if region.name else "" + footprint[name] += region.size + + if region.contains(address): + enclosing = region + + print(f"{count} regions, {mapped // 1024} KB mapped") + + for name, size in footprint.items(): + print(f"{size:#010x} {name}") + + if enclosing is not None: + print(f"{address:#x}: {enclosing.name}+{address - enclosing.addr:#x}") + # lief-doc: inspect-end + + +def stack_and_heap() -> None: + # lief-doc: stack-heap-start + for region in lief.runtime.memory_layout(): + # On Linux and Android, the kernel names the regions that back the + # stack and the heap of the process. + if region.name in ("[stack]", "[heap]"): + print(f"{region.name}: {region.addr:#014x}-{region.end_addr:#014x}") + # lief-doc: stack-heap-end diff --git a/vendor/lief/doc/code/python/objc.py b/vendor/lief/doc/code/python/objc.py new file mode 100644 index 0000000..0171fde --- /dev/null +++ b/vendor/lief/doc/code/python/objc.py @@ -0,0 +1,39 @@ +import lief + + +def check(macho: lief.MachO.Binary) -> None: + # lief-doc: check-start + macho: lief.MachO.Binary + + metadata = macho.objc_metadata + if metadata is not None: + print("Objective-C metadata found") + # lief-doc: check-end + + +def inspect(macho: lief.MachO.Binary) -> None: + # lief-doc: inspect-start + macho: lief.MachO.Binary + + metadata = macho.objc_metadata + for clazz in metadata.classes: + print(f"name={clazz.name}") + for meth in clazz.methods: + print(f" method.name={meth.name}") + print(metadata.to_decl()) + # lief-doc: inspect-end + + +# lief-doc: no-address-start +def print_without_address(macho: lief.MachO.Binary): + + metadata = macho.objc_metadata + + config = lief.objc.DeclOpt() + config.show_annotations = False + + for cls in metadata.classes: + print(cls.to_decl(config)) + + +# lief-doc: no-address-end diff --git a/vendor/lief/doc/code/python/pdb.py b/vendor/lief/doc/code/python/pdb.py new file mode 100644 index 0000000..e99271a --- /dev/null +++ b/vendor/lief/doc/code/python/pdb.py @@ -0,0 +1,81 @@ +import lief + + +def load_pdb(pe: lief.PE.Binary) -> lief.pdb.DebugInfo | None: + # lief-doc: load-start + pe: lief.PE.Binary + + if (debug_info := pe.debug_info) is not None: + assert isinstance(debug_info, lief.pdb.DebugInfo) + print(f"PDB Debug handler: {debug_info}") + + # Or you can load the PDB directly: + pdb = lief.pdb.load("some.pdb") + # lief-doc: load-end + return pdb + + +def load_ext(binary: lief.Binary) -> lief.DebugInfo | None: + # lief-doc: load-ext-start + binary: lief.Binary + + dbg = binary.load_debug_info(r"C:\Users\romain\LIEF.pdb") + # lief-doc: load-ext-end + return dbg + + +def disassemble(binary: lief.Binary) -> lief.DebugInfo | None: + # lief-doc: disassemble-start + binary: lief.Binary + + dbg = binary.load_debug_info(r"C:\Users\romain\LIEF.pdb") + + # The location (address/size) of `my_function` is defined in LIEF.pdb + for inst in binary.disassemble("my_function"): + print(inst) + # lief-doc: disassemble-end + return dbg + + +def to_decl(pdb: lief.pdb.DebugInfo) -> None: + # lief-doc: to-decl-start + pdb: lief.pdb.DebugInfo + + opt = lief.DeclOpt() + opt.is_cpp = True + + for ty in pdb.types: + print(ty.to_decl(opt)) + + for cu in pdb.compilation_units: + # Emit the definition of the functions of the compilation unit + print(cu.to_decl(opt)) + + for func in cu.functions: + print(func.to_decl(opt)) + # lief-doc: to-decl-end + + +def explore(pdb: lief.pdb.DebugInfo) -> None: + # lief-doc: explore-start + pdb: lief.pdb.DebugInfo + + print(f"arg={pdb.age}, guid={pdb.guid}") + + for sym in pdb.public_symbols: + print(f"name={sym.name}, section={sym.section_name}, RVA={sym.RVA}") + + for ty in pdb.types: + if isinstance(ty, lief.pdb.types.Class): + print(f"Class[name]={ty.name}") + + for cu in pdb.compilation_units: + print(f"module={cu.module_name}") + for src in cu.sources: + print(f" - {src}") + + for func in cu.functions: + print( + f"name={func.name}, section={func.section_name}, RVA={func.RVA}, code_size={func.code_size}" + ) + # lief-doc: explore-end diff --git a/vendor/lief/doc/code/python/pe.py b/vendor/lief/doc/code/python/pe.py new file mode 100644 index 0000000..01f7f6d --- /dev/null +++ b/vendor/lief/doc/code/python/pe.py @@ -0,0 +1,106 @@ +import pathlib + +import lief + + +def inspect(pe: lief.PE.Binary) -> None: + # lief-doc: inspect-start + pe: lief.PE.Binary + + print(pe.rich_header) + print(pe.authentihash_md5.hex(":")) + + for section in pe.sections: + print(section.name, len(section.content)) + # lief-doc: inspect-end + + +def add_section(pe: lief.PE.Binary) -> None: + # lief-doc: add-section-start + pe: lief.PE.Binary + + section = lief.PE.Section(".hello") + section.content = [0xCC] * 0x100 + pe.add_section(section) + + pe.write("new.exe") + # lief-doc: add-section-end + + +def parse_from_dump() -> None: + # lief-doc: dump-start + # 0x7ffd21b80000 is the (absolute) address at which the dump was mapped + pe = lief.PE.parse_from_dump("module.dump", 0x7FFD21B80000) + assert isinstance(pe, lief.PE.Binary) + + for imp in pe.imports: + print(imp.name) + # lief-doc: dump-end + + +def module_dump() -> None: + # lief-doc: dump-runtime-start + # Find the module to dump in the current process + mod = lief.runtime.module_from_name("target.dll") + assert isinstance(mod, lief.runtime.windows.Module) + + # Dump the module's memory into a file (the raw bytes are also returned) ... + data: bytes = mod.dump("module.dump") + + # ... and parse it back using the same imagebase: + pe = lief.PE.parse_from_dump(data, mod.imagebase) + # lief-doc: dump-runtime-end + assert isinstance(pe, lief.PE.Binary) + + +def advanced_parse_write() -> None: + # lief-doc: advanced-start + parser_config = lief.PE.ParserConfig() + parser_config.parse_signature = False + + pe = lief.PE.parse("some.exe", parser_config) + assert isinstance(pe, lief.PE.Binary) + + builder_config = lief.PE.Builder.config_t() + builder_config.imports = True + + pe.write("new.exe", builder_config) + # lief-doc: advanced-end + + +def write_bytes(pe: lief.PE.Binary) -> bytes: + # lief-doc: write-bytes-start + pe: lief.PE.Binary + + new_pe: bytes = pe.write_to_bytes() + # lief-doc: write-bytes-end + return new_pe + + +def authenticode() -> None: + # lief-doc: authenticode-start + pe = lief.PE.parse("signed.exe") + assert isinstance(pe, lief.PE.Binary) + + for signature in pe.signatures: + for crt in signature.certificates: + print(crt) + + assert pe.verify_signature() == lief.PE.Signature.VERIFICATION_FLAGS.OK + # lief-doc: authenticode-end + + +def parse_forms() -> lief.PE.Binary | None: + # lief-doc: parse-start + + # Using filepath + pe: lief.PE.Binary | None = lief.PE.parse(r"C:\Users\test.exe") + + # Using a Path from pathlib + pe: lief.PE.Binary | None = lief.PE.parse(pathlib.Path(r"C:\Users\test.exe")) + + # Using an io object + with open(r"C:\Users\test.exe", "rb") as f: + pe: lief.PE.Binary | None = lief.PE.parse(f) + # lief-doc: parse-end + return pe diff --git a/vendor/lief/doc/code/python/pe_debug.py b/vendor/lief/doc/code/python/pe_debug.py new file mode 100644 index 0000000..9b6bb58 --- /dev/null +++ b/vendor/lief/doc/code/python/pe_debug.py @@ -0,0 +1,35 @@ +import lief + + +def change_name(pe: lief.PE.Binary) -> None: + # lief-doc: change-name-start + pe: lief.PE.Binary + + assert isinstance(pe.codeview_pdb, lief.PE.CodeViewPDB) + pe.codeview_pdb.filename = r"C:\A\B\C\path.pdb" + + pe.write("out.dll") + # lief-doc: change-name-end + + +def remove(pe: lief.PE.Binary) -> None: + # lief-doc: remove-start + # Remove a single CodeViewPDB entry + assert pe.codeview_pdb is not None + pe.remove_debug(pe.codeview_pdb) + + # Remove all entries + pe.clear_debug() + + pe.write("out.dll") + # lief-doc: remove-end + + +def add(pe: lief.PE.Binary) -> None: + # lief-doc: add-start + cv = lief.PE.CodeViewPDB("MyCustom.pdb") + + pe.add_debug_info(cv) + + pe.write("out.dll") + # lief-doc: add-end diff --git a/vendor/lief/doc/code/python/pe_exports.py b/vendor/lief/doc/code/python/pe_exports.py new file mode 100644 index 0000000..48584ca --- /dev/null +++ b/vendor/lief/doc/code/python/pe_exports.py @@ -0,0 +1,52 @@ +import lief + + +def create_export_entries(pe: lief.PE.Binary) -> None: + # lief-doc: create-entries-start + pe: lief.PE.Binary + + exp = pe.get_export() + assert isinstance(exp, lief.PE.Export) + + # Remove an entry + exp.remove_entry("my_exported_name") + + # Add a new export + exp.add_entry("fuzz_me", 0x10010) + + config = lief.PE.Builder.config_t() + config.exports = True + config.export_section = ".myedata" # optional + + pe.write("out.dll", config) + # lief-doc: create-entries-end + + +def convert_to_dll(pe: lief.PE.Binary) -> None: + # lief-doc: dll-header-start + pe: lief.PE.Binary + + pe.header.add_characteristic(lief.PE.Header.CHARACTERISTICS.DLL) + pe.optional_header.addressof_entrypoint = 0 + # lief-doc: dll-header-end + + +def create_export_table(pe: lief.PE.Binary) -> None: + # lief-doc: create-table-start + pe: lief.PE.Binary + + exp = lief.PE.Export( + "lib_exe2dll.dll", + [ + lief.PE.ExportEntry("cbk1", 0x0001000), + lief.PE.ExportEntry("cbk2", 0x0001010), + ], + ) + + pe.set_export(exp) + + config = lief.PE.Builder.config_t() + config.exports = True + + pe.write("lib_exe2dll.dll") + # lief-doc: create-table-end diff --git a/vendor/lief/doc/code/python/pe_imports.py b/vendor/lief/doc/code/python/pe_imports.py new file mode 100644 index 0000000..7c798a3 --- /dev/null +++ b/vendor/lief/doc/code/python/pe_imports.py @@ -0,0 +1,78 @@ +import lief + + +def remove_import(pe: lief.PE.Binary) -> None: + # lief-doc: remove-import-start + pe: lief.PE.Binary + + pe.remove_import("kernel32.dll") + + config = lief.PE.Builder.config_t() + config.imports = True + + pe.write("new.exe", config) + # lief-doc: remove-import-end + + +def remove_import_entry(pe: lief.PE.Binary) -> None: + # lief-doc: remove-import-entry-start + pe: lief.PE.Binary + + kernel32 = pe.get_import("kernel32.dll") + assert kernel32 is not None + kernel32.remove_entry("IsDebuggerPresent") + + config = lief.PE.Builder.config_t() + config.imports = True + + pe.write("new.exe", config) + # lief-doc: remove-import-entry-end + + +def add_import(pe: lief.PE.Binary) -> None: + # lief-doc: add-import-start + pe: lief.PE.Binary + + stdio = pe.add_import("api-ms-win-crt-stdio-l1-1-0.dll") + stdio.add_entry("puts") + + config = lief.PE.Builder.config_t() + config.imports = True + + pe.write("new.exe", config) + # lief-doc: add-import-end + + +def add_import_cbk(pe: lief.PE.Binary) -> None: + # lief-doc: add-import-cbk-start + pe: lief.PE.Binary + + def iat_resolution_cbk( + pe: lief.PE.Binary, imp: lief.PE.Import, entry: lief.PE.ImportEntry, rva: int + ): + # Process + return + + stdio = pe.add_import("api-ms-win-crt-stdio-l1-1-0.dll") + stdio.add_entry("puts") + + config = lief.PE.Builder.config_t() + config.imports = True + config.resolved_iat_cbk = iat_resolution_cbk + + pe.write("new.exe", config) + # lief-doc: add-import-cbk-end + + +def add_import_func(pe: lief.PE.Binary) -> None: + # lief-doc: add-import-func-start + pe: lief.PE.Binary + + kernel32 = pe.add_import("kernel32.dll") + kernel32.add_entry("GetStartupInfoW") + + config = lief.PE.Builder.config_t() + config.imports = True + + pe.write("new.exe", config) + # lief-doc: add-import-func-end diff --git a/vendor/lief/doc/code/python/pe_resources.py b/vendor/lief/doc/code/python/pe_resources.py new file mode 100644 index 0000000..9df8f6a --- /dev/null +++ b/vendor/lief/doc/code/python/pe_resources.py @@ -0,0 +1,71 @@ +import lief + + +def access_root(pe: lief.PE.Binary) -> None: + # lief-doc: access-root-start + pe: lief.PE.Binary + rsrc = pe.resources + + print(rsrc) + # lief-doc: access-root-end + + +def add_child(pe: lief.PE.Binary) -> None: + # lief-doc: add-child-start + pe: lief.PE.Binary + + rsrc = pe.resources + assert isinstance(rsrc, lief.PE.ResourceNode) + + dir_node = lief.PE.ResourceDirectory(100) + data_node = lief.PE.ResourceData([1, 2, 3]) + + rsrc.add_child(dir_node).add_child(data_node) + # lief-doc: add-child-end + + +def pretty_print(pe: lief.PE.Binary) -> None: + # lief-doc: pretty-print-start + pe: lief.PE.Binary + + tree = pe.resources + print(tree) + # lief-doc: pretty-print-end + + +def set_manifest(pe: lief.PE.Binary) -> None: + # lief-doc: manifest-start + pe: lief.PE.Binary + + manager = pe.resources_manager + assert isinstance(manager, lief.PE.ResourcesManager) + + manager.manifest = """ + + + + + + + + + + + """ + + pe.write("new.exe") + # lief-doc: manifest-end + + +def transfer_resources(from_pe: lief.PE.Binary, to_pe: lief.PE.Binary) -> None: + # lief-doc: transfer-start + from_pe: lief.PE.Binary + to_pe: lief.PE.Binary + + resources = from_pe.resources + assert isinstance(resources, lief.PE.ResourceNode) + + to_pe.set_resources(resources) + to_pe.write("new.exe") + # lief-doc: transfer-end diff --git a/vendor/lief/doc/code/python/pe_tls.py b/vendor/lief/doc/code/python/pe_tls.py new file mode 100644 index 0000000..26d7516 --- /dev/null +++ b/vendor/lief/doc/code/python/pe_tls.py @@ -0,0 +1,43 @@ +import lief + + +def modify_callbacks(pe: lief.PE.Binary) -> None: + # lief-doc: modify-callbacks-start + pe: lief.PE.Binary + + tls = pe.tls + assert isinstance(tls, lief.PE.TLS) + + callbacks: list[int] = tls.callbacks + + # Remove the last entry + callbacks.pop() + + # Add an address + callbacks.append(0x140001010) + + tls.callbacks = callbacks + + pe.write("tls_modified.exe") + # lief-doc: modify-callbacks-end + + +def create_tls() -> lief.PE.TLS: + # lief-doc: create-tls-start + tls = lief.PE.TLS() + + tls.callbacks = [ + 0x140001000, + 0x140001010, + ] + # lief-doc: create-tls-end + return tls + + +def add_tls(pe: lief.PE.Binary) -> None: + tls = create_tls() + # lief-doc: add-tls-start + pe.tls = tls # `tls` defined previously + + pe.write("tls_demo.exe") + # lief-doc: add-tls-end diff --git a/vendor/lief/doc/code/python/tuto_android.py b/vendor/lief/doc/code/python/tuto_android.py new file mode 100644 index 0000000..06dfeef --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_android.py @@ -0,0 +1,58 @@ +import lief + + +def oat_symbols() -> None: + # lief-doc: oat-symbols-start + oat = lief.OAT.parse("SomeOAT") + assert oat is not None + for s in oat.dynamic_symbols: + print(s) + # lief-doc: oat-symbols-end + + +def oat_extract_dex(oat: lief.OAT.Binary) -> None: + # lief-doc: oat-extract-dex-start + oat: lief.OAT.Binary + + dex = oat.dex_files[0] + dex.save("/tmp/classes.dex") + # lief-doc: oat-extract-dex-end + + +def dex_source_files(dex: lief.DEX.File) -> None: + # lief-doc: dex-source-files-start + dex: lief.DEX.File + + for cls in dex.classes: + if cls.source_filename: + print(cls) + # lief-doc: dex-source-files-end + + +def dex_strings(dex: lief.DEX.File) -> None: + # lief-doc: dex-strings-start + dex: lief.DEX.File + + for s in dex.strings: + if "http" in s: + print(s) + # lief-doc: dex-strings-end + + +def dex_deobfuscate(dex: lief.DEX.File) -> None: + # lief-doc: dex-deobfuscate-start + dex: lief.DEX.File + + for cls in dex.classes: + if cls.source_filename: + print(cls.pretty_name + ": ---> " + cls.source_filename) + # lief-doc: dex-deobfuscate-end + + +def art_header() -> None: + # lief-doc: art-header-start + art = lief.ART.parse("boot.art") + assert isinstance(art, lief.ART.File) + + print(art.header) + # lief-doc: art-header-end diff --git a/vendor/lief/doc/code/python/tuto_authenticode.py b/vendor/lief/doc/code/python/tuto_authenticode.py new file mode 100644 index 0000000..5289901 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_authenticode.py @@ -0,0 +1,116 @@ +import lief + + +def signatures(pe: lief.PE.Binary) -> lief.PE.Signature: + # lief-doc: signatures-start + pe: lief.PE.Binary + + print(len(pe.signatures)) + + signature = pe.signatures[0] + # lief-doc: signatures-end + return signature + + +def signature_info(signature: lief.PE.Signature) -> None: + # lief-doc: signature-info-start + signature: lief.PE.Signature + + # Print certificate information + for crt in signature.certificates: + print(crt) + + # Print the authentihash value embedded in the signature + print(signature.content_info.digest.hex()) + + # Print signer information + print(signature.signers[0]) + # lief-doc: signature-info-end + + +def compute_authentihash(pe: lief.PE.Binary) -> None: + # lief-doc: authentihash-start + pe: lief.PE.Binary + + print(pe.authentihash(lief.PE.ALGORITHMS.SHA_256).hex()) + # lief-doc: authentihash-end + + +def extract_raw_der(signature: lief.PE.Signature) -> None: + # lief-doc: raw-der-start + from pathlib import Path + + signature: lief.PE.Signature + + Path("/tmp/extracted.p7b").write_bytes(signature.raw_der) + # lief-doc: raw-der-end + + +def verify(pe: lief.PE.Binary) -> None: + # lief-doc: verify-start + pe: lief.PE.Binary + + print(pe.verify_signature()) # lief.PE.Signature.VERIFICATION_FLAGS.OK + # lief-doc: verify-end + + +def verify_detached(pe: lief.PE.Binary) -> None: + # lief-doc: verify-detached-start + pe: lief.PE.Binary + + detached_sig = lief.PE.Signature.parse("/tmp/detached.p7b") + assert isinstance(detached_sig, lief.PE.Signature) + + print(pe.verify_signature(detached_sig)) + # lief-doc: verify-detached-end + + +def verify_hash_only(pe: lief.PE.Binary) -> None: + # lief-doc: verify-hash-only-start + pe: lief.PE.Binary + + pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.HASH_ONLY) + # lief-doc: verify-hash-only-end + + +def verify_lifetime(pe: lief.PE.Binary, signature: lief.PE.Signature) -> None: + # lief-doc: verify-lifetime-start + pe: lief.PE.Binary + signature: lief.PE.Signature + + pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING) + signature.check(lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING) + # lief-doc: verify-lifetime-end + + +def verify_skip_cert_time(pe: lief.PE.Binary, signature: lief.PE.Signature) -> None: + # lief-doc: verify-skip-cert-time-start + pe: lief.PE.Binary + signature: lief.PE.Signature + + # Returns lief.PE.Signature.VERIFICATION_FLAGS.OK even if + # the certificates have expired + pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME) + signature.check(lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME) + # lief-doc: verify-skip-cert-time-end + + +def is_trusted_by_bundle(signature: lief.PE.Signature) -> None: + # lief-doc: is-trusted-bundle-start + signature: lief.PE.Signature + + CA_BUNDLE = lief.PE.x509.parse("ms_bundle.pem") + signer = signature.signers[0] + print(signer.cert.is_trusted_by(CA_BUNDLE)) + # lief-doc: is-trusted-bundle-end + + +def is_trusted_by_list(signer: lief.PE.SignerInfo) -> None: + # lief-doc: is-trusted-list-start + signer: lief.PE.SignerInfo + + cert1 = lief.PE.x509.parse("ca1.crt")[0] + cert2 = lief.PE.x509.parse("ca2.crt")[0] + + print(signer.cert.is_trusted_by([cert1, cert2])) + # lief-doc: is-trusted-list-end diff --git a/vendor/lief/doc/code/python/tuto_coredump.py b/vendor/lief/doc/code/python/tuto_coredump.py new file mode 100644 index 0000000..868f206 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_coredump.py @@ -0,0 +1,77 @@ +import lief + + +def list_segments(core: lief.ELF.Binary) -> None: + # lief-doc: segments-start + core: lief.ELF.Binary + + segments = core.segments + print(f"Number of segments {len(segments)}") + + for segment in segments: + print(hex(segment.virtual_address)) + # lief-doc: segments-end + + +def corefile_check(binary: lief.ELF.Binary) -> None: + # lief-doc: corefile-check-start + binary: lief.ELF.Binary + + for note in binary.notes: + if isinstance(note, lief.ELF.CoreFile): + print("This is a CoreFile note") + # lief-doc: corefile-check-end + + +def iter_files(nt_core_file: lief.ELF.CoreFile) -> None: + # lief-doc: iter-files-start + nt_core_file: lief.ELF.CoreFile + + for file_entry in nt_core_file: + print(file_entry) + # lief-doc: iter-files-end + + +def registers(core: lief.ELF.Binary) -> None: + # lief-doc: registers-start + core: lief.ELF.Binary + + for note in core.notes: + if not isinstance(note, lief.ELF.CorePrStatus): + continue + + # Both are equivalent + print(note.pc) + reg_values = note.register_values + print(reg_values[lief.ELF.CorePrStatus.Registers.AARCH64.PC.value]) + # lief-doc: registers-end + + +def set_register(core: lief.ELF.Binary) -> None: + # lief-doc: set-register-start + core: lief.ELF.Binary + + prstatus = core.get(lief.ELF.Note.TYPE.CORE_PRSTATUS) + assert isinstance(prstatus, lief.ELF.CorePrStatus) + + prstatus.set(lief.ELF.CorePrStatus.Registers.AARCH64.PC, 0xDEADC0DE) + + core.write("/tmp/new.core") + # lief-doc: set-register-end + + +def parse_coredump() -> None: + # lief-doc: parse-core-start + + core = lief.parse("ELF64_AArch64_core_hello.core") + # lief-doc: parse-core-end + _ = core + + +def get_corefile(core: lief.ELF.Binary) -> lief.ELF.Note | None: + # lief-doc: get-corefile-start + core: lief.ELF.Binary + + nt_core_file = core.get(lief.ELF.Note.TYPE.CORE_FILE) + # lief-doc: get-corefile-end + return nt_core_file diff --git a/vendor/lief/doc/code/python/tuto_elf_bin2lib.py b/vendor/lief/doc/code/python/tuto_elf_bin2lib.py new file mode 100644 index 0000000..8f18ff3 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_elf_bin2lib.py @@ -0,0 +1,24 @@ +import sys + +import lief + + +def export_function(crackme101: lief.ELF.Binary) -> None: + # lief-doc: export-start + crackme101: lief.ELF.Binary + + addr = crackme101.get_function_address("check_found") # 0x72A + assert isinstance(addr, int) + crackme101.add_exported_function(addr, "check_found") + crackme101.write("libcrackme101.so") + # lief-doc: export-end + + +def remove_pie() -> None: + # lief-doc: remove-pie-start + path = sys.argv[1] + bin_ = lief.parse(path) + assert isinstance(bin_, lief.ELF.Binary) + bin_[lief.ELF.DynamicEntry.TAG.FLAGS_1].remove(lief.ELF.DynamicEntryFlags.FLAG.PIE) + bin_.write(path + ".patched") + # lief-doc: remove-pie-end diff --git a/vendor/lief/doc/code/python/tuto_elf_hooking.py b/vendor/lief/doc/code/python/tuto_elf_hooking.py new file mode 100644 index 0000000..f4107ec --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_elf_hooking.py @@ -0,0 +1,31 @@ +import lief + + +def hooking(libm: lief.ELF.Binary, hook: lief.ELF.Binary) -> None: + # lief-doc: inject-start + libm: lief.ELF.Binary + hook: lief.ELF.Binary + + exp_symbol = libm.get_symbol("exp") + hook_symbol = hook.get_symbol("hook") + assert hook_symbol is not None + + code_segment = hook.segment_from_virtual_address(hook_symbol.value) + assert code_segment is not None + + segment_added = libm.add(code_segment) + # lief-doc: inject-end + assert exp_symbol is not None + assert segment_added is not None + + # lief-doc: update-start + new_address = ( + segment_added.virtual_address + hook_symbol.value - code_segment.virtual_address + ) + exp_symbol.value = new_address + exp_symbol.type = lief.ELF.Symbol.TYPE.FUNC # it might have been GNU_IFUNC + # lief-doc: update-end + + # lief-doc: write-start + libm.write("libm.so.6") + # lief-doc: write-end diff --git a/vendor/lief/doc/code/python/tuto_elf_plt_got.py b/vendor/lief/doc/code/python/tuto_elf_plt_got.py new file mode 100644 index 0000000..f32b9a0 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_elf_plt_got.py @@ -0,0 +1,40 @@ +import lief + + +def inject_hook() -> None: + # lief-doc: inject-start + + crackme = lief.parse("crackme.bin") + assert isinstance(crackme, lief.ELF.Binary) + + hook = lief.parse("hook") + assert isinstance(hook, lief.ELF.Binary) + + segment_added = crackme.add(hook.segments[0]) + # lief-doc: inject-end + _ = segment_added + + +def compute_hook_address(hook: lief.ELF.Binary, segment_added: lief.ELF.Segment) -> int: + # lief-doc: hook-address-start + hook: lief.ELF.Binary + segment_added: lief.ELF.Segment + + my_memcmp = hook.get_symbol("my_memcmp") + assert my_memcmp is not None + + my_memcmp_addr = segment_added.virtual_address + my_memcmp.value + # lief-doc: hook-address-end + return my_memcmp_addr + + +def patch_got(crackme: lief.ELF.Binary, my_memcmp_addr: int) -> None: + # lief-doc: patch-got-start + crackme.patch_pltgot("memcmp", my_memcmp_addr) + # lief-doc: patch-got-end + + +def rebuild(crackme: lief.ELF.Binary) -> None: + # lief-doc: rebuild-start + crackme.write("crackme.hooked") + # lief-doc: rebuild-end diff --git a/vendor/lief/doc/code/python/tuto_elf_symbols.py b/vendor/lief/doc/code/python/tuto_elf_symbols.py new file mode 100644 index 0000000..a1289d0 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_elf_symbols.py @@ -0,0 +1,59 @@ +import lief + + +def imported_exported(binary: lief.Binary, library: lief.Binary) -> None: + # lief-doc: imported-exported-start + binary: lief.Binary + library: lief.Binary + + print(binary.imported_functions) + print(library.exported_functions) + # lief-doc: imported-exported-end + + +def load_binaries() -> None: + # lief-doc: load-start + + hashme = lief.parse("hashme") + libm = lief.parse("/usr/lib/libm.so.6") + # Note: the path to libm.so.6 might be different on your system. + # lief-doc: load-end + _ = (hashme, libm) + + +def change_imported(hashme: lief.ELF.Binary) -> None: + # lief-doc: change-imported-start + hashme: lief.ELF.Binary + + hashme_pow_sym = next(i for i in hashme.imported_symbols if i.name == "pow") + hashme_log_sym = next(i for i in hashme.imported_symbols if i.name == "log") + + hashme_pow_sym.name = "cos" + hashme_log_sym.name = "sin" + # lief-doc: change-imported-end + + +def swap_all(hashme: lief.ELF.Binary, libm: lief.ELF.Binary) -> None: + # lief-doc: swap-all-start + def swap(obj, a, b): + symbol_a = next(i for i in obj.dynamic_symbols if i.name == a) + symbol_b = next(i for i in obj.dynamic_symbols if i.name == b) + b_name = symbol_b.name + symbol_b.name = symbol_a.name + symbol_a.name = b_name + + hashme: lief.ELF.Binary + libm: lief.ELF.Binary + + hashme_pow_sym = next(i for i in hashme.imported_symbols if i.name == "pow") + hashme_log_sym = next(i for i in hashme.imported_symbols if i.name == "log") + + hashme_pow_sym.name = "cos" + hashme_log_sym.name = "sin" + + swap(libm, "log", "sin") + swap(libm, "pow", "cos") + + hashme.write("hashme.obf") + libm.write("libm.so.6") + # lief-doc: swap-all-end diff --git a/vendor/lief/doc/code/python/tuto_frida.py b/vendor/lief/doc/code/python/tuto_frida.py new file mode 100644 index 0000000..7c07b26 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_frida.py @@ -0,0 +1,12 @@ +import lief + + +def inject_gadget() -> None: + # lief-doc: inject-start + + libnative = lief.parse("libnative.so") + assert isinstance(libnative, lief.ELF.Binary) + + libnative.add_library("libgadget.so") # Injection! + libnative.write("libnative.so") + # lief-doc: inject-end diff --git a/vendor/lief/doc/code/python/tuto_macho_mod.py b/vendor/lief/doc/code/python/tuto_macho_mod.py new file mode 100644 index 0000000..a092681 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_macho_mod.py @@ -0,0 +1,106 @@ +import lief + + +def show_relocations(app: lief.MachO.Binary) -> None: + # lief-doc: relocations-start + app: lief.MachO.Binary + + for relocation in app.relocations: + print(relocation) + # lief-doc: relocations-end + + +def show_export_info(app: lief.MachO.Binary) -> None: + # lief-doc: export-info-start + app: lief.MachO.Binary + + for s in app.symbols: + if s.has_export_info: + print(s.export_info) + # lief-doc: export-info-end + + +def remove_signature(ssh: lief.MachO.Binary) -> None: + # lief-doc: remove-signature-start + ssh: lief.MachO.Binary + + ssh.remove_signature() + + ssh.write("ssh.nosigned") + # lief-doc: remove-signature-end + + +def add_library(clang: lief.MachO.Binary) -> None: + # lief-doc: add-library-start + clang: lief.MachO.Binary + + clang.add_library("/Users/romain/libexample.dylib") + + clang.write("/tmp/clang.new") + # lief-doc: add-library-end + + +def add_section( + app: lief.MachO.Binary, raw_shell: list[int] +) -> lief.MachO.Section | None: + # lief-doc: add-section-start + app: lief.MachO.Binary + raw_shell: list[int] + + section = lief.MachO.Section.create("__shell", raw_shell) + assert isinstance(section, lief.MachO.Section) + + section.alignment = 2 + section += lief.MachO.Section.FLAGS.SOME_INSTRUCTIONS + section += lief.MachO.Section.FLAGS.PURE_INSTRUCTIONS + + section = app.add_section(section) + print(section) + # lief-doc: add-section-end + return section + + +def remove_signature_and_write(app: lief.MachO.Binary) -> None: + # lief-doc: remove-sig-write-start + app: lief.MachO.Binary + + app.remove_signature() + app.write("./id.modified") + # lief-doc: remove-sig-write-end + + +def show_rebase_opcodes() -> None: + # lief-doc: rebase-opcodes-start + app = lief.parse("MachO64_x86-64_binary_id.bin") + print(app.dyld_info.show_rebases_opcodes) + # lief-doc: rebase-opcodes-end + + +def show_bind_opcodes(app: lief.MachO.Binary) -> None: + # lief-doc: bind-opcodes-start + app: lief.MachO.Binary + + print(app.dyld_info.show_bind_opcodes) + # lief-doc: bind-opcodes-end + + +def show_export_trie() -> None: + # lief-doc: export-trie-start + app = lief.parse("FAT_MachO_x86_x86-64_library_libdyld.dylib") + print(app.dyld_info.show_export_trie) + # lief-doc: export-trie-end + + +def set_entrypoint(app: lief.MachO.Binary, section: lief.MachO.Section) -> None: + # lief-doc: set-entrypoint-start + app: lief.MachO.Binary + section: lief.MachO.Section + + __TEXT = app.get_segment("__TEXT") + assert __TEXT is not None + + main = app.main_command + assert main is not None + + main.entrypoint = section.virtual_address - __TEXT.virtual_address + # lief-doc: set-entrypoint-end diff --git a/vendor/lief/doc/code/python/tuto_pe_hooking.py b/vendor/lief/doc/code/python/tuto_pe_hooking.py new file mode 100644 index 0000000..fab0d79 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_pe_hooking.py @@ -0,0 +1,30 @@ +import lief + + +def disable_aslr(binary: lief.PE.Binary) -> None: + # lief-doc: disable-aslr-start + binary: lief.PE.Binary + + binary.optional_header.dll_characteristics &= ( + ~lief.PE.OptionalHeader.DLL_CHARACTERISTICS.DYNAMIC_BASE + ) + # lief-doc: disable-aslr-end + + +def disable_nx(binary: lief.PE.Binary) -> None: + # lief-doc: disable-nx-start + binary: lief.PE.Binary + + binary.optional_header.dll_characteristics &= ( + ~lief.PE.OptionalHeader.DLL_CHARACTERISTICS.NX_COMPAT + ) + # lief-doc: disable-nx-end + + +def add_exitprocess(binary: lief.PE.Binary) -> None: + # lief-doc: add-exitprocess-start + binary: lief.PE.Binary + + kernel32 = binary.get_import("KERNEL32.dll") + kernel32.add_entry("ExitProcess") + # lief-doc: add-exitprocess-end diff --git a/vendor/lief/doc/code/python/tuto_pe_resource.py b/vendor/lief/doc/code/python/tuto_pe_resource.py new file mode 100644 index 0000000..b94bfc1 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_pe_resource.py @@ -0,0 +1,101 @@ +import lief + + +def resource_section(binary: lief.PE.Binary) -> None: + # lief-doc: resource-section-start + binary: lief.PE.Binary + + if binary.has_resources: + rsrc_directory = binary.data_directory( + lief.PE.DataDirectory.TYPES.RESOURCE_TABLE + ) + assert rsrc_directory is not None + if rsrc_directory.has_section: + print(rsrc_directory.section) + # lief-doc: resource-section-end + + +def manifest_tree(filezilla: lief.PE.Binary) -> None: + # lief-doc: manifest-tree-start + filezilla: lief.PE.Binary + + root = filezilla.resources + assert root is not None + + # First level => Type (ResourceDirectory node) + manifest_node = next( + i for i in root.childs if i.id == lief.PE.ResourcesManager.TYPE.MANIFEST + ) + print(manifest_node) + + # Second level => ID (ResourceDirectory node) + id_node = manifest_node.childs[0] + print(id_node) + + # Third level => Lang (ResourceData node) + lang_node = id_node.childs[0] + print(lang_node) + + manifest = bytes(lang_node.content).decode("utf8") + + print(manifest) + # lief-doc: manifest-tree-end + + +def overview(filezilla: lief.PE.Binary) -> None: + # lief-doc: overview-start + filezilla: lief.PE.Binar + + resource_manager = filezilla.resources_manager + print(resource_manager) + # lief-doc: overview-end + + +def get_manifest(filezilla: lief.PE.Binary) -> None: + # lief-doc: get-manifest-start + resources_manager = filezilla.resources_manager + + manifest = resources_manager.manifest + print(manifest) + # lief-doc: get-manifest-end + + +def set_admin(filezilla: lief.PE.Binary) -> None: + # lief-doc: set-admin-start + filezilla: lief.PE.Binary + + resources_manager = filezilla.resources_manager + assert isinstance(resources_manager, lief.PE.ResourcesManager) + + manifest = resources_manager.manifest + assert isinstance(manifest, str) + + manifest = manifest.replace("asInvoker", "requireAdministrator") + resources_manager.manifest = manifest + # lief-doc: set-admin-end + + +def load_managers() -> None: + # lief-doc: load-managers-start + mfc = lief.parse("mfc.exe") + cmd = lief.parse("cmd.exe") + + mfc_rsrc_manager = mfc.resources_manager + cmd_rsrc_manager = cmd.resources_manager + # lief-doc: load-managers-end + _ = (mfc_rsrc_manager, cmd_rsrc_manager) + + +def change_icons( + mfc_rsrc_manager: lief.PE.ResourcesManager, + cmd_rsrc_manager: lief.PE.ResourcesManager, +) -> None: + # lief-doc: change-icons-start + mfc_rsrc_manager: lief.PE.ResourcesManager + cmd_rsrc_manager: lief.PE.ResourcesManager + + mfc_icons = mfc_rsrc_manager.icons + cmd_icons = cmd_rsrc_manager.icons + for i in range(min(len(mfc_icons), len(cmd_icons))): + mfc_rsrc_manager.change_icon(mfc_icons[i], cmd_icons[i]) + # lief-doc: change-icons-end diff --git a/vendor/lief/doc/code/python/tuto_play_formats.py b/vendor/lief/doc/code/python/tuto_play_formats.py new file mode 100644 index 0000000..de7c705 --- /dev/null +++ b/vendor/lief/doc/code/python/tuto_play_formats.py @@ -0,0 +1,99 @@ +import lief + + +def elf_parse() -> None: + # lief-doc: elf-parse-start + binary = lief.parse("/bin/ls") + # lief-doc: elf-parse-end + _ = binary + + +def elf_header(binary: lief.ELF.Binary) -> lief.ELF.Header: + # lief-doc: elf-header-start + binary: lief.ELF.Binary + + header = binary.header + # lief-doc: elf-header-end + return header + + +def elf_change_header(header: lief.ELF.Header) -> None: + # lief-doc: elf-change-header-start + header: lief.ELF.Header + + header.entrypoint = 0x123 + header.machine_type = lief.ELF.ARCH.AARCH64 + # lief-doc: elf-change-header-end + + +def elf_write(binary: lief.ELF.Binary) -> None: + # lief-doc: elf-write-start + binary: lief.ELF.Binary + + binary.write("ls.modified") + # lief-doc: elf-write-end + + +def elf_sections(binary: lief.ELF.Binary) -> None: + # lief-doc: elf-sections-start + binary: lief.ELF.Binary + + for section in binary.sections: + print(section.name) # section name + print(section.size) # section size + print(len(section.content)) # Should match the previous print + # lief-doc: elf-sections-end + + +def elf_text(binary: lief.ELF.Binary) -> None: + # lief-doc: elf-text-start + binary: lief.ELF.Binary + + text = binary.get_section(".text") + assert text is not None + text.content = bytes([0x33] * text.size) + # lief-doc: elf-text-end + + +def pe_parse() -> None: + # lief-doc: pe-parse-start + binary = lief.parse("C:\\Windows\\explorer.exe") + # lief-doc: pe-parse-end + _ = binary + + +def pe_headers(binary: lief.PE.Binary) -> None: + # lief-doc: pe-headers-start + binary: lief.PE.Binary + + print(binary.dos_header) + print(binary.header) + print(binary.optional_header) + # lief-doc: pe-headers-end + + +def pe_imports(binary: lief.PE.Binary) -> None: + # lief-doc: pe-imports-start + # Using the abstract layer + binary: lief.PE.Binary + + for func in binary.imported_functions: + print(func) + + # Using the PE definition + for func in binary.imports: + print(func) + # lief-doc: pe-imports-end + + +def pe_imports_detailed(binary: lief.PE.Binary) -> None: + # lief-doc: pe-imports-detailed-start + binary: lief.PE.Binary + + for imported_library in binary.imports: + print("Library name: " + imported_library.name) + for func in imported_library.entries: + if not func.is_ordinal: + print(func.name) + print(func.iat_address) + # lief-doc: pe-imports-detailed-end diff --git a/vendor/lief/doc/code/python/ty.toml b/vendor/lief/doc/code/python/ty.toml new file mode 100644 index 0000000..723d9ac --- /dev/null +++ b/vendor/lief/doc/code/python/ty.toml @@ -0,0 +1,5 @@ +[rules] +unused-type-ignore-comment = "ignore" +unused-ignore-comment = "ignore" +unresolved-attribute = "ignore" +unsupported-operator = "ignore" diff --git a/vendor/lief/doc/code/python/utilities.py b/vendor/lief/doc/code/python/utilities.py new file mode 100644 index 0000000..4108588 --- /dev/null +++ b/vendor/lief/doc/code/python/utilities.py @@ -0,0 +1,37 @@ +import lief + + +def demangle_msvc() -> None: + # lief-doc: demangle-msvc-start + lief.demangle("?h@@YAXH@Z") + # lief-doc: demangle-msvc-end + + +def demangle_rust() -> None: + # lief-doc: demangle-rust-start + lief.demangle("_RNvCskwGfYPst2Cb_3foo16example_function") + # lief-doc: demangle-rust-end + + +def demangle_itanium() -> None: + # lief-doc: demangle-itanium-start + lief.demangle("_ZTSN3lld13SpecificAllocINS_4coff9TpiSourceEEE") + # lief-doc: demangle-itanium-end + + +def demangle_swift() -> None: + # lief-doc: demangle-swift-start + lief.demangle("_$s10Foundation4DataV15_RepresentationON") + # lief-doc: demangle-swift-end + + +def dump_section() -> None: + # lief-doc: dump-start + pe = lief.PE.parse("some.exe") + assert isinstance(pe, lief.PE.Binary) + + text = pe.get_section(".text") + assert isinstance(pe, lief.PE.Section) + + print(lief.dump(text.content)) + # lief-doc: dump-end diff --git a/vendor/lief/doc/code/rust/Cargo.lock b/vendor/lief/doc/code/rust/Cargo.lock new file mode 100644 index 0000000..2ba68fb --- /dev/null +++ b/vendor/lief/doc/code/rust/Cargo.lock @@ -0,0 +1,2075 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "addr2line" +version = "0.25.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b5d307320b3181d6d7954e663bd7c774a838b8220fe0593c86d9fb09f498b4b" +dependencies = [ + "gimli", +] + +[[package]] +name = "adler2" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa" + +[[package]] +name = "anstyle" +version = "1.0.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" + +[[package]] +name = "atomic-waker" +version = "1.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1505bd5d3d116872e7271a6d4e16d81d0c8570876c8de68093a09ac269d8aac0" + +[[package]] +name = "autocfg" +version = "1.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53" + +[[package]] +name = "aws-lc-rs" +version = "1.18.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ce2b2dcc879c3bae0d371e77c99f2238400ef24ec001394befa67b6e543add9e" +dependencies = [ + "aws-lc-sys", + "zeroize", +] + +[[package]] +name = "aws-lc-sys" +version = "0.44.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f09fae7be8bb3174e05c6afdb34199e6dc0c7c04ba9fa237b1967adfbde27483" +dependencies = [ + "cc", + "cmake", + "dunce", + "fs_extra", + "pkg-config", +] + +[[package]] +name = "backtrace" +version = "0.3.76" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb531853791a215d7c62a30daf0dde835f381ab5de4589cfe7c649d2cbe92bd6" +dependencies = [ + "addr2line", + "cfg-if", + "libc", + "miniz_oxide", + "object", + "rustc-demangle", + "windows-link", +] + +[[package]] +name = "backtrace-ext" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "537beee3be4a18fb023b570f80e3ae28003db9167a751266b259926e25539d50" +dependencies = [ + "backtrace", +] + +[[package]] +name = "base64" +version = "0.22.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6" + +[[package]] +name = "bitflags" +version = "2.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b588b76d00fde79687d7646a9b5bdf3cc0f655e0bbd080335a95d7e96f3587da" + +[[package]] +name = "bumpalo" +version = "3.20.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72f5acc6cb2ba439de613abc23857ec3d78374d8ed5ac84e9d11336e87da8649" + +[[package]] +name = "bytes" +version = "1.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fc652a48c352aef3ea3aed32080501cf3ef6ed5da78602a020c991775b0aff04" + +[[package]] +name = "cc" +version = "1.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "509591b7bcd67f4ef775afad7662703b4935daaa6ec0e5605cfb1090b32a2b6d" +dependencies = [ + "find-msvc-tools", + "jobserver", + "libc", + "shlex", +] + +[[package]] +name = "cfg-if" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" + +[[package]] +name = "cfg_aliases" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f079e83a288787bcd14a6aea84cee5c87a67c5a3e660c30f557a3d24761b3527" + +[[package]] +name = "chacha20" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d524456ba66e72eb8b115ff89e01e497f8e6d11d78b70b1aa13c0fbd97540a81" +dependencies = [ + "cfg-if", + "cpufeatures", + "rand_core", +] + +[[package]] +name = "clap" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "473c7e07f409a8d772161724aa8db6a765a2532a70f9667eeb7b49d3d02fbdca" +dependencies = [ + "clap_builder", +] + +[[package]] +name = "clap_builder" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7b48fea5a88e9ae728a2dcbedbfc0e730f7d60da42e1cb049a83c9fb8b789889" +dependencies = [ + "anstyle", + "clap_lex", + "strsim", +] + +[[package]] +name = "clap_lex" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" + +[[package]] +name = "cmake" +version = "0.1.58" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c0f78a02292a74a88ac736019ab962ece0bc380e3f977bf72e376c5d78ff0678" +dependencies = [ + "cc", +] + +[[package]] +name = "codespan-reporting" +version = "0.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "af491d569909a7e4dee0ad7db7f5341fef5c614d5b8ec8cf765732aba3cff681" +dependencies = [ + "serde", + "termcolor", + "unicode-width 0.2.2", +] + +[[package]] +name = "combine" +version = "4.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ba5a308b75df32fe02788e748662718f03fde005016435c444eea572398219fd" +dependencies = [ + "bytes", + "memchr", +] + +[[package]] +name = "core-foundation" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2a6cd9ae233e7f62ba4e9353e81a88df7fc8a5987b8d445b4d90c879bd156f6" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "core-foundation-sys" +version = "0.8.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "773648b94d0e5d620f64f280777445740e61fe701025087ec8b57f45c791888b" + +[[package]] +name = "cpufeatures" +version = "0.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b2a41393f66f16b0823bb79094d54ac5fbd34ab292ddafb9a0456ac9f87d201" +dependencies = [ + "libc", +] + +[[package]] +name = "crc32fast" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511" +dependencies = [ + "cfg-if", +] + +[[package]] +name = "cxx" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6fe442a792c7c736eea18b32a7f8a3b63cf8aafabda6760042dc2fdeda456291" +dependencies = [ + "cc", + "cxx-build", + "cxxbridge-cmd", + "cxxbridge-flags", + "cxxbridge-macro", + "foldhash", + "link-cplusplus", +] + +[[package]] +name = "cxx-build" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3184a94384c663718698311a78a51ac00c484c10b4eeac06fb0a068c5f64fa2" +dependencies = [ + "cc", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "scratch", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-cmd" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0148d8fd1199329ddf1d157a5e134e51ceff37c6a7ddd38615c399d81cb05d8d" +dependencies = [ + "clap", + "codespan-reporting", + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "cxxbridge-flags" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "52850339faed2eaadd24e286dc1d8268cc6f8a7bd9524d713adc9099566b4c89" + +[[package]] +name = "cxxbridge-macro" +version = "1.0.198" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2c77c856545d886c9bd5215409ebb63b925e262135248b50c79e5a5f194ee47c" +dependencies = [ + "indexmap", + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "deranged" +version = "0.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7cd812cc2bc1d69d4764bd80df88b4317eaef9e773c75226407d9bc0876b211c" +dependencies = [ + "powerfmt", +] + +[[package]] +name = "displaydoc" +version = "0.2.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6232dd377dcc64799954cbd3a9bb882e9cdc1308ccd87b1c098f1fb2eaf82a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "dunce" +version = "1.0.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92773504d58c093f6de2459af4af33faa518c13451eb8f2b5698ed3d36e7c813" + +[[package]] +name = "equivalent" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" + +[[package]] +name = "errno" +version = "0.3.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "find-msvc-tools" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d45db016d36b838f563236e9193d0ee6ce38f3f68b6c94e914b4929c96bbb890" + +[[package]] +name = "flate2" +version = "1.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c" +dependencies = [ + "miniz_oxide", + "zlib-rs", +] + +[[package]] +name = "foldhash" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77ce24cb58228fbb8aa041425bb1050850ac19177686ea6e0f41a70416f56fdb" + +[[package]] +name = "form_urlencoded" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cb4cb245038516f5f85277875cdaa4f7d2c9a0fa0468de06ed190163b1581fcf" +dependencies = [ + "percent-encoding", +] + +[[package]] +name = "fs_extra" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "42703706b716c37f96a77aea830392ad231f44c9e9a67872fa5548707e11b11c" + +[[package]] +name = "futures-channel" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1f9e3d69d39e4862ffed03ed071a76f9a13ba1d9109d355b0f0aa6b15e393c4" +dependencies = [ + "futures-core", + "futures-sink", +] + +[[package]] +name = "futures-core" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92d699e522242e69e3003b94ecc1f960f3a5e015aa7c5d7486e65ad01dd94f5e" + +[[package]] +name = "futures-io" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53c0fa8157de1303bfffdaa1cc2a673bfffb60102f76b0ef4441659124373fed" + +[[package]] +name = "futures-sink" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1944426bf7d03f1d14f708785e4b33efd750b36d48a157b836b3efc15ede8e1d" + +[[package]] +name = "futures-task" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cd417de3d1d015fc3bfd2b1ea46dfc7bab72ef86f1cc7cc9c78e728b34a6d1fd" + +[[package]] +name = "futures-util" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0d50a92467f8ba5dd6e3ee5d4bd04d73ab2e4e1c44474a0674821dfce14b79bc" +dependencies = [ + "futures-core", + "futures-io", + "futures-sink", + "futures-task", + "memchr", + "pin-project-lite", + "slab", +] + +[[package]] +name = "getrandom" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "wasi", + "wasm-bindgen", +] + +[[package]] +name = "getrandom" +version = "0.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "300e883d756b2e4ec94e02791f39b04b522276138852cfc41d9fb7e904106099" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "r-efi", + "rand_core", + "wasm-bindgen", +] + +[[package]] +name = "gimli" +version = "0.32.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e629b9b98ef3dd8afe6ca2bd0f89306cec16d43d907889945bc5d6687f2f13c7" + +[[package]] +name = "git-version" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1ad568aa3db0fcbc81f2f116137f263d7304f512a1209b35b85150d3ef88ad19" +dependencies = [ + "git-version-macro", +] + +[[package]] +name = "git-version-macro" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53010ccb100b96a67bc32c0175f0ed1426b31b655d562898e57325f81c023ac0" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "hashbrown" +version = "0.17.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" + +[[package]] +name = "http" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "918d3568bebf352712bc2ef3d46a8bcf1a75b373be6539de198e9105cbbf9ce0" +dependencies = [ + "bytes", + "itoa", +] + +[[package]] +name = "http-body" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ca2a8f2913ee65f60facd6a5905613afaa448497a0230cc41ce022d93290bc2c" +dependencies = [ + "bytes", + "http", +] + +[[package]] +name = "http-body-util" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "23169fe34a5fbcdd3f3862e78fb9b6fccd5f02a6dc6f732547005d45631ce71c" +dependencies = [ + "bytes", + "futures-core", + "http", + "http-body", + "pin-project-lite", +] + +[[package]] +name = "httparse" +version = "1.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6dbf3de79e51f3d586ab4cb9d5c3e2c14aa28ed23d180cf89b4df0454a69cc87" + +[[package]] +name = "hyper" +version = "1.11.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d22053281f852e11534f5198498373cbb59295120a20771d90f7ed1897490a72" +dependencies = [ + "atomic-waker", + "bytes", + "futures-channel", + "futures-core", + "http", + "http-body", + "httparse", + "itoa", + "pin-project-lite", + "smallvec", + "tokio", + "want", +] + +[[package]] +name = "hyper-rustls" +version = "0.27.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "33ca68d021ef39cf6463ab54c1d0f5daf03377b70561305bb89a8f83aab66e0f" +dependencies = [ + "http", + "hyper", + "hyper-util", + "rustls", + "tokio", + "tokio-rustls", + "tower-service", +] + +[[package]] +name = "hyper-util" +version = "0.1.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "96547c2556ec9d12fb1578c4eaf448b04993e7fb79cbaad930a656880a6bdfa0" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-util", + "http", + "http-body", + "hyper", + "ipnet", + "libc", + "percent-encoding", + "pin-project-lite", + "socket2", + "tokio", + "tower-service", + "tracing", +] + +[[package]] +name = "icu_collections" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4c6b649701667bbe825c3b7e6388cb521c23d88644678e83c0c4d0a621a34b43" +dependencies = [ + "displaydoc", + "potential_utf", + "yoke", + "zerofrom", + "zerovec", +] + +[[package]] +name = "icu_locale_core" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "edba7861004dd3714265b4db54a3c390e880ab658fec5f7db895fae2046b5bb6" +dependencies = [ + "displaydoc", + "litemap", + "tinystr", + "writeable", + "zerovec", +] + +[[package]] +name = "icu_normalizer" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f6c8828b67bf8908d82127b2054ea1b4427ff0230ee9141c54251934ab1b599" +dependencies = [ + "icu_collections", + "icu_normalizer_data", + "icu_properties", + "icu_provider", + "smallvec", + "zerovec", +] + +[[package]] +name = "icu_normalizer_data" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7aedcccd01fc5fe81e6b489c15b247b8b0690feb23304303a9e560f37efc560a" + +[[package]] +name = "icu_properties" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "020bfc02fe870ec3a66d93e677ccca0562506e5872c650f893269e08615d74ec" +dependencies = [ + "icu_collections", + "icu_locale_core", + "icu_properties_data", + "icu_provider", + "zerotrie", + "zerovec", +] + +[[package]] +name = "icu_properties_data" +version = "2.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "616c294cf8d725c6afcd8f55abc17c56464ef6211f9ed59cccffe534129c77af" + +[[package]] +name = "icu_provider" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "85962cf0ce02e1e0a629cc34e7ca3e373ce20dda4c4d7294bbd0bf1fdb59e614" +dependencies = [ + "displaydoc", + "icu_locale_core", + "writeable", + "yoke", + "zerofrom", + "zerotrie", + "zerovec", +] + +[[package]] +name = "idna" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b0875f23caa03898994f6ddc501886a45c7d3d62d04d2d90788d47be1b1e4de" +dependencies = [ + "idna_adapter", + "smallvec", + "utf8_iter", +] + +[[package]] +name = "idna_adapter" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3acae9609540aa318d1bc588455225fb2085b9ed0c4f6bd0d9d5bcd86f1a0344" +dependencies = [ + "icu_normalizer", + "icu_properties", +] + +[[package]] +name = "indexmap" +version = "2.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" +dependencies = [ + "equivalent", + "hashbrown", +] + +[[package]] +name = "ipnet" +version = "2.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6a756c3fac73139e83f14c2d742155dd2b78d3ee56597b419a0579b7bdd6dd78" + +[[package]] +name = "is_ci" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7655c9839580ee829dfacba1d1278c2b7883e50a277ff7541299489d6bdfdc45" + +[[package]] +name = "itoa" +version = "1.0.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" + +[[package]] +name = "jni" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5efd9a482cf3a427f00d6b35f14332adc7902ce91efb778580e180ff90fa3498" +dependencies = [ + "cfg-if", + "combine", + "jni-macros", + "jni-sys", + "log", + "simd_cesu8", + "thiserror", + "walkdir", + "windows-link", +] + +[[package]] +name = "jni-macros" +version = "0.22.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a00109accc170f0bdb141fed3e393c565b6f5e072365c3bd58f5b062591560a3" +dependencies = [ + "proc-macro2", + "quote", + "rustc_version", + "simd_cesu8", + "syn 2.0.119", +] + +[[package]] +name = "jni-sys" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c6377a88cb3910bee9b0fa88d4f42e1d2da8e79915598f65fb0c7ee14c878af2" +dependencies = [ + "jni-sys-macros", +] + +[[package]] +name = "jni-sys-macros" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "38c0b942f458fe50cdac086d2f946512305e5631e720728f2a61aabcd47a6264" +dependencies = [ + "quote", + "syn 2.0.119", +] + +[[package]] +name = "jobserver" +version = "0.1.35" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1c00acbd29eabad4a2392fa0e921c874934dbbf4194312ad20f04a0ed67a3cb3" +dependencies = [ + "getrandom 0.4.3", + "libc", +] + +[[package]] +name = "js-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0e0c1080212aad755ea003d18543e8768dd432c48819efd73a7bf1e39b7a5a3a" +dependencies = [ + "cfg-if", + "futures-util", + "wasm-bindgen", +] + +[[package]] +name = "libc" +version = "0.2.189" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2" + +[[package]] +name = "lief" +version = "2.0.0" +dependencies = [ + "bitflags", + "cxx", + "lief-ffi", + "num-bigint", + "num-derive", + "num-traits", +] + +[[package]] +name = "lief-build" +version = "2.0.0" +dependencies = [ + "git-version", + "miette", + "reqwest", + "semver", + "zip", +] + +[[package]] +name = "lief-doc-code" +version = "0.0.0" +dependencies = [ + "lief", +] + +[[package]] +name = "lief-ffi" +version = "2.0.0" +dependencies = [ + "cxx", + "lief-build", + "miette", +] + +[[package]] +name = "link-cplusplus" +version = "1.0.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7f78c730aaa7d0b9336a299029ea49f9ee53b0ed06e9202e8cb7db9bae7b8c82" +dependencies = [ + "cc", +] + +[[package]] +name = "linux-raw-sys" +version = "0.12.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53" + +[[package]] +name = "litemap" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "47d9d19d1d6efa0109d2f65ff4c85cddd50bd572e5a00127ab10987290bcefae" + +[[package]] +name = "log" +version = "0.4.33" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ceec5bc11778974d1bcb055b18002eba7f4b3518b6a0081b3af5f21666da9ad" + +[[package]] +name = "lru-slab" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "112b39cec0b298b6c1999fee3e31427f74f676e4cb9879ed1a121b43661a4154" + +[[package]] +name = "memchr" +version = "2.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf8baf1c55e62ffcace7a9f06f4bd9cd3f0c4beb022d3b367256b91b87513d98" + +[[package]] +name = "miette" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f98efec8807c63c752b5bd61f862c165c115b0a35685bdcfd9238c7aeb592b7" +dependencies = [ + "backtrace", + "backtrace-ext", + "cfg-if", + "miette-derive", + "owo-colors", + "supports-color", + "supports-hyperlinks", + "supports-unicode", + "terminal_size", + "textwrap", + "unicode-width 0.1.14", +] + +[[package]] +name = "miette-derive" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db5b29714e950dbb20d5e6f74f9dcec4edbcc1067bb7f8ed198c097b8c1a818b" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "miniz_oxide" +version = "0.8.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316" +dependencies = [ + "adler2", + "simd-adler32", +] + +[[package]] +name = "mio" +version = "1.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "30d65c71f1ce40ab09135ce117d742b9f8a19ff91a41a8b57ed50bc2de59c427" +dependencies = [ + "libc", + "wasi", + "windows-sys 0.61.2", +] + +[[package]] +name = "num-bigint" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93e7820bc0a80a0238e650327316f929ba18d5be054b647490a3a6a339f3e7c0" +dependencies = [ + "num-integer", + "num-traits", +] + +[[package]] +name = "num-conv" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9" + +[[package]] +name = "num-derive" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e4e98dc3b890f6c23a0f9d3d491a2823d0dea0fa656302a13dd225fa924112a8" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "num-integer" +version = "0.1.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ce2d95d4b3734dc35aa2f45e1aa22cd416814592a4f9d9205e11affd5b8e10b" +dependencies = [ + "num-traits", +] + +[[package]] +name = "num-traits" +version = "0.2.19" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" +dependencies = [ + "autocfg", +] + +[[package]] +name = "object" +version = "0.37.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe" +dependencies = [ + "memchr", +] + +[[package]] +name = "once_cell" +version = "1.21.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" + +[[package]] +name = "openssl-probe" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7c87def4c32ab89d880effc9e097653c8da5d6ef28e6b539d313baaacfbafcbe" + +[[package]] +name = "owo-colors" +version = "4.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d211803b9b6b570f68772237e415a029d5a50c65d382910b879fb19d3271f94d" + +[[package]] +name = "percent-encoding" +version = "2.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220" + +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" + +[[package]] +name = "pkg-config" +version = "0.3.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f6b464fbc74e149a392436b17d523f769e057cb6877f6a5c4618bc6f11800548" + +[[package]] +name = "potential_utf" +version = "0.1.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d83eb9bc6d8e5cf568e7a1101d60ee05e81ed50ea106026f3d18deeb046d7661" +dependencies = [ + "zerovec", +] + +[[package]] +name = "powerfmt" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "439ee305def115ba05938db6eb1644ff94165c5ab5e9420d1c1bcedbba909391" + +[[package]] +name = "proc-macro2" +version = "1.0.107" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "985e7ec9bb745e6ce6535b544d84d6cd6f7ad8bd711c398938ae983b91a766d9" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "quinn" +version = "0.11.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c1a41e437b6bbd489372cd4971de128e85c855f56c57f283d20ff016cf7c0a8" +dependencies = [ + "bytes", + "cfg_aliases", + "pin-project-lite", + "quinn-proto", + "quinn-udp", + "rustc-hash", + "rustls", + "socket2", + "thiserror", + "tokio", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-proto" +version = "0.11.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "04759210543be93709136e28212294a659ef5001836ff4eab4d663e4529bba83" +dependencies = [ + "aws-lc-rs", + "bytes", + "getrandom 0.4.3", + "lru-slab", + "rand", + "rand_pcg", + "ring", + "rustc-hash", + "rustls", + "rustls-pki-types", + "slab", + "thiserror", + "tinyvec", + "tracing", + "web-time", +] + +[[package]] +name = "quinn-udp" +version = "0.5.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "35a133f956daabe89a61a685c2649f13d82d5aa4bd5d12d1277e1072a21c0694" +dependencies = [ + "cfg_aliases", + "libc", + "once_cell", + "socket2", + "tracing", + "windows-sys 0.61.2", +] + +[[package]] +name = "quote" +version = "1.0.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fbf4db142a473a8d80c26bbf18454ed458bf8d26c8219c331daecfdbd079001" +dependencies = [ + "proc-macro2", +] + +[[package]] +name = "r-efi" +version = "6.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf" + +[[package]] +name = "rand" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c7f5fa3a058cd35567ef9bfa5e75732bee0f9e4c55fa90477bef2dfcdbc4be80" +dependencies = [ + "chacha20", + "getrandom 0.4.3", + "rand_core", +] + +[[package]] +name = "rand_core" +version = "0.10.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63b8176103e19a2643978565ca18b50549f6101881c443590420e4dc998a3c69" + +[[package]] +name = "rand_pcg" +version = "0.10.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "caa0f4137e1c0a72f4c651489402276c8e8e1cf081f3b0ba156d2cbeef09e86a" +dependencies = [ + "rand_core", +] + +[[package]] +name = "reqwest" +version = "0.13.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "219c5811de6525e5416c7d5d53bb656d3afdbc6c5af816e0802bcfa42dbdc1c3" +dependencies = [ + "base64", + "bytes", + "futures-channel", + "futures-core", + "futures-util", + "http", + "http-body", + "http-body-util", + "hyper", + "hyper-rustls", + "hyper-util", + "js-sys", + "log", + "percent-encoding", + "pin-project-lite", + "quinn", + "rustls", + "rustls-pki-types", + "rustls-platform-verifier", + "sync_wrapper", + "tokio", + "tokio-rustls", + "tower", + "tower-http", + "tower-service", + "url", + "wasm-bindgen", + "wasm-bindgen-futures", + "web-sys", +] + +[[package]] +name = "ring" +version = "0.17.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7" +dependencies = [ + "cc", + "cfg-if", + "getrandom 0.2.17", + "libc", + "untrusted", + "windows-sys 0.52.0", +] + +[[package]] +name = "rustc-demangle" +version = "0.1.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b74b56ffa8bb2830709a538c2cbcae9aa062db0d2a42563bfb09bdaae44020eb" + +[[package]] +name = "rustc-hash" +version = "2.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b1e7f9a428571be2dc5bc0505c13fb6bf936822b894ec87abf8a08a4e51742d" + +[[package]] +name = "rustc_version" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cfcb3a22ef46e85b45de6ee7e79d063319ebb6594faafcf1c225ea92ab6e9b92" +dependencies = [ + "semver", +] + +[[package]] +name = "rustix" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190" +dependencies = [ + "bitflags", + "errno", + "libc", + "linux-raw-sys", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls" +version = "0.23.43" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0283386ce02abc0151e1761d08802dfe86c173b0b494af5cbc086574e453da06" +dependencies = [ + "aws-lc-rs", + "once_cell", + "rustls-pki-types", + "rustls-webpki", + "subtle", + "zeroize", +] + +[[package]] +name = "rustls-native-certs" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dab5152771c58876a2146916e53e35057e1a4dfa2b9df0f0305b07f611fdea4d" +dependencies = [ + "openssl-probe", + "rustls-pki-types", + "schannel", + "security-framework", +] + +[[package]] +name = "rustls-pki-types" +version = "1.15.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2f4925028c7eb5d1fcdaf196971378ed9d2c1c4efc7dc5d011256f76c99c0a96" +dependencies = [ + "web-time", + "zeroize", +] + +[[package]] +name = "rustls-platform-verifier" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "26d1e2536ce4f35f4846aa13bff16bd0ff40157cdb14cc056c7b14ba41233ba0" +dependencies = [ + "core-foundation", + "core-foundation-sys", + "jni", + "log", + "once_cell", + "rustls", + "rustls-native-certs", + "rustls-platform-verifier-android", + "rustls-webpki", + "security-framework", + "security-framework-sys", + "webpki-root-certs", + "windows-sys 0.61.2", +] + +[[package]] +name = "rustls-platform-verifier-android" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f87165f0995f63a9fbeea62b64d10b4d9d8e78ec6d7d51fb2125fda7bb36788f" + +[[package]] +name = "rustls-webpki" +version = "0.103.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0527518605e68109d875e248ea259b6758801cf165e4b2c2733ae3b51f12535a" +dependencies = [ + "aws-lc-rs", + "ring", + "rustls-pki-types", + "untrusted", +] + +[[package]] +name = "rustversion" +version = "1.0.23" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf54715a573b99ac80df0bc206da022bcd442c974952c7b9720069370852e21f" + +[[package]] +name = "same-file" +version = "1.0.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "schannel" +version = "0.1.29" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "91c1b7e4904c873ef0710c1f407dde2e6287de2bebc1bbbf7d430bb7cbffd939" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "scratch" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d68f2ec51b097e4c1a75b681a8bec621909b5e91f15bb7b840c4f2f7b01148b2" + +[[package]] +name = "security-framework" +version = "3.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7f4bc775c73d9a02cde8bf7b2ec4c9d12743edf609006c7facc23998404cd1d" +dependencies = [ + "bitflags", + "core-foundation", + "core-foundation-sys", + "libc", + "security-framework-sys", +] + +[[package]] +name = "security-framework-sys" +version = "2.17.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2691df843ecc5d231c0b14ece2acc3efb62c0a398c7e1d875f3983ce020e3" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "semver" +version = "1.0.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd" + +[[package]] +name = "serde" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4148590afebada386688f18773da617792bf2ef03ffc1e4cbd2b1d45b023e0ba" +dependencies = [ + "serde_core", + "serde_derive", +] + +[[package]] +name = "serde_core" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67dca2c9c51e58a4791a4b1ed58308b39c64224d349a935ab5039aa360942a48" +dependencies = [ + "serde_derive", +] + +[[package]] +name = "serde_derive" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e7a5d71263a5a7d47b41f6b3f06ba276f10cc18b0931f1799f710578e2309348" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "shlex" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8fadd59c855ef2080decdef8ff161eb6661b86933c9d82e5ba29dc602a55aba" + +[[package]] +name = "simd-adler32" +version = "0.3.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3a219298ac11a56ea9a6d2120044824d6f01aeb034955e7af7bc16858527deea" + +[[package]] +name = "simd_cesu8" +version = "1.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11031e251abf8611c80f460e19dbdeb54a66db918e49c65a7065b46ac7aec520" +dependencies = [ + "rustc_version", + "simdutf8", +] + +[[package]] +name = "simdutf8" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3a9fe34e3e7a50316060351f37187a3f546bce95496156754b601a5fa71b76e" + +[[package]] +name = "slab" +version = "0.4.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5" + +[[package]] +name = "smallvec" +version = "1.15.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ed6a63f02c8539c91a8685a86f4099661ba3da017932f6ebbea6de3f0fa7c90" + +[[package]] +name = "socket2" +version = "0.6.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c3d1e2c7f27f8d4cb10542a02c49005dbd6e93095799d6f3be745fae9f8fedd4" +dependencies = [ + "libc", + "windows-sys 0.61.2", +] + +[[package]] +name = "stable_deref_trait" +version = "1.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596" + +[[package]] +name = "strsim" +version = "0.11.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" + +[[package]] +name = "subtle" +version = "2.6.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292" + +[[package]] +name = "supports-color" +version = "3.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c64fc7232dd8d2e4ac5ce4ef302b1d81e0b80d055b9d77c7c4f51f6aa4c867d6" +dependencies = [ + "is_ci", +] + +[[package]] +name = "supports-hyperlinks" +version = "3.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e396b6523b11ccb83120b115a0b7366de372751aa6edf19844dfb13a6af97e91" + +[[package]] +name = "supports-unicode" +version = "3.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b7401a30af6cb5818bb64852270bb722533397edcfc7344954a38f420819ece2" + +[[package]] +name = "syn" +version = "2.0.119" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "872831b642d1a07999a962a351ed35b955ea2cfc8f3862091e2a240a84f17297" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "syn" +version = "3.0.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "53e9bae58849f64dfa4f5d5ae372c8341f7305f82a3868709269343628b659a3" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "sync_wrapper" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0bf256ce5efdfa370213c1dabab5935a12e49f2c58d15e9eac2870d3b4f27263" +dependencies = [ + "futures-core", +] + +[[package]] +name = "synstructure" +version = "0.13.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "728a70f3dbaf5bab7f0c4b1ac8d7ae5ea60a4b5549c8a5914361c99147a709d2" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] + +[[package]] +name = "termcolor" +version = "1.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "06794f8f6c5c898b3275aebefa6b8a1cb24cd2c6c79397ab15774837a0bc5755" +dependencies = [ + "winapi-util", +] + +[[package]] +name = "terminal_size" +version = "0.4.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "230a1b821ccbd75b185820a1f1ff7b14d21da1e442e22c0863ea5f08771a8874" +dependencies = [ + "rustix", + "windows-sys 0.61.2", +] + +[[package]] +name = "textwrap" +version = "0.16.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c13547615a44dc9c452a8a534638acdf07120d4b6847c8178705da06306a3057" +dependencies = [ + "unicode-linebreak", + "unicode-width 0.2.2", +] + +[[package]] +name = "thiserror" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ec86235f5fcc2a73650310756d2ac5b138a5780bbbdfae3eeccec992c435ba4f" +dependencies = [ + "thiserror-impl", +] + +[[package]] +name = "thiserror-impl" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bc04cd3e1236dd4a98afca4569f2deb3f120e5422a4023be2cb683f8486292af" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "time" +version = "0.3.45" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f9e442fc33d7fdb45aa9bfeb312c095964abdf596f7567261062b2a7107aaabd" +dependencies = [ + "deranged", + "js-sys", + "num-conv", + "powerfmt", + "serde_core", + "time-core", +] + +[[package]] +name = "time-core" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8b36ee98fd31ec7426d599183e8fe26932a8dc1fb76ddb6214d05493377d34ca" + +[[package]] +name = "tinystr" +version = "0.8.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1e27c91459209c2986af3dcf603a5a74a4368754ce37414f59acc971167f643" +dependencies = [ + "displaydoc", + "zerovec", +] + +[[package]] +name = "tinyvec" +version = "1.12.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb4ebadaa0af04fab11ae01eb5f9fdb5f9c5b875506e210e71c07873528baa7f" +dependencies = [ + "tinyvec_macros", +] + +[[package]] +name = "tinyvec_macros" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1f3ccbac311fea05f86f61904b462b55fb3df8837a366dfc601a0161d0532f20" + +[[package]] +name = "tokio" +version = "1.53.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "202caea871b69668250d242070849eb495be178ed697a3e98aebce5bc81a0bed" +dependencies = [ + "bytes", + "libc", + "mio", + "pin-project-lite", + "socket2", + "windows-sys 0.61.2", +] + +[[package]] +name = "tokio-rustls" +version = "0.26.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1729aa945f29d91ba541258c8df89027d5792d85a8841fb65e8bf0f4ede4ef61" +dependencies = [ + "rustls", + "tokio", +] + +[[package]] +name = "tower" +version = "0.5.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ebe5ef63511595f1344e2d5cfa636d973292adc0eec1f0ad45fae9f0851ab1d4" +dependencies = [ + "futures-core", + "futures-util", + "pin-project-lite", + "sync_wrapper", + "tokio", + "tower-layer", + "tower-service", +] + +[[package]] +name = "tower-http" +version = "0.6.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4cfcf7e2740e6fc6d4d688b4ef00650406bb94adf4731e43c096c3a19fe40840" +dependencies = [ + "bitflags", + "bytes", + "futures-util", + "http", + "http-body", + "pin-project-lite", + "tower", + "tower-layer", + "tower-service", + "url", +] + +[[package]] +name = "tower-layer" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "121c2a6cda46980bb0fcd1647ffaf6cd3fc79a013de288782836f6df9c48780e" + +[[package]] +name = "tower-service" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8df9b6e13f2d32c91b9bd719c00d1958837bc7dec474d94952798cc8e69eeec3" + +[[package]] +name = "tracing" +version = "0.1.44" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "63e71662fa4b2a2c3a26f570f037eb95bb1f85397f3cd8076caed2f026a6d100" +dependencies = [ + "pin-project-lite", + "tracing-core", +] + +[[package]] +name = "tracing-core" +version = "0.1.36" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db97caf9d906fbde555dd62fa95ddba9eecfd14cb388e4f491a66d74cd5fb79a" +dependencies = [ + "once_cell", +] + +[[package]] +name = "try-lock" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e421abadd41a4225275504ea4d6566923418b7f05506fbc9c0fe86ba7396114b" + +[[package]] +name = "typed-path" +version = "0.12.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e28f89b80c87b8fb0cf04ab448d5dd0dd0ade2f8891bae878de66a75a28600e" + +[[package]] +name = "unicode-ident" +version = "1.0.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" + +[[package]] +name = "unicode-linebreak" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3b09c83c3c29d37506a3e260c08c03743a6bb66a9cd432c6934ab501a190571f" + +[[package]] +name = "unicode-width" +version = "0.1.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af" + +[[package]] +name = "unicode-width" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b4ac048d71ede7ee76d585517add45da530660ef4390e49b098733c6e897f254" + +[[package]] +name = "untrusted" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1" + +[[package]] +name = "url" +version = "2.5.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ff67a8a4397373c3ef660812acab3268222035010ab8680ec4215f38ba3d0eed" +dependencies = [ + "form_urlencoded", + "idna", + "percent-encoding", + "serde", +] + +[[package]] +name = "utf8_iter" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be" + +[[package]] +name = "walkdir" +version = "2.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "29790946404f91d9c5d06f9874efddea1dc06c5efe94541a7d6863108e3a5e4b" +dependencies = [ + "same-file", + "winapi-util", +] + +[[package]] +name = "want" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bfa7760aed19e106de2c7c0b581b509f2f25d3dacaf737cb82ac61bc6d760b0e" +dependencies = [ + "try-lock", +] + +[[package]] +name = "wasi" +version = "0.11.1+wasi-snapshot-preview1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" + +[[package]] +name = "wasm-bindgen" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1b70935747edd64d89de3efa29d73789b806c15798f8e7dca4d8ac356b50ce70" +dependencies = [ + "cfg-if", + "once_cell", + "rustversion", + "wasm-bindgen-macro", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-futures" +version = "0.4.77" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b7777d5cc23d0e91404e53ce2d5e8ec7acae3026b16233dba62cd3246457950" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "wasm-bindgen-macro" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77775f8f3f7217702089053b94958f8f54061a3f663417df76e19cbdcca29bc1" +dependencies = [ + "quote", + "wasm-bindgen-macro-support", +] + +[[package]] +name = "wasm-bindgen-macro-support" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e11d33f857dc2fb11b8bc75aee111aa9cbeb12cd9f25efd3d4c2a3dd4e235284" +dependencies = [ + "bumpalo", + "proc-macro2", + "quote", + "syn 2.0.119", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-shared" +version = "0.2.127" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ef64dbcc55df09c7e5a46182d181c2cfa3e925f3da937ea764728b4bbb9dcbf" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "web-sys" +version = "0.3.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c435338968042f4f59a557f690a253676d47ce13ceb55d70100e7facf6620a30" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "web-time" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5a6580f308b1fad9207618087a65c04e7a10bc77e02c8e84e9b00dd4b12fa0bb" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "webpki-root-certs" +version = "1.0.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b96554aa2acc8ccdb7e1c9a58a7a68dd5d13bccc69cd124cb09406db612a1c9b" +dependencies = [ + "rustls-pki-types", +] + +[[package]] +name = "winapi-util" +version = "0.1.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22" +dependencies = [ + "windows-sys 0.61.2", +] + +[[package]] +name = "windows-link" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" + +[[package]] +name = "windows-sys" +version = "0.52.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" +dependencies = [ + "windows-targets", +] + +[[package]] +name = "windows-sys" +version = "0.61.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc" +dependencies = [ + "windows-link", +] + +[[package]] +name = "windows-targets" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" +dependencies = [ + "windows_aarch64_gnullvm", + "windows_aarch64_msvc", + "windows_i686_gnu", + "windows_i686_gnullvm", + "windows_i686_msvc", + "windows_x86_64_gnu", + "windows_x86_64_gnullvm", + "windows_x86_64_msvc", +] + +[[package]] +name = "windows_aarch64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" + +[[package]] +name = "windows_aarch64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" + +[[package]] +name = "windows_i686_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" + +[[package]] +name = "windows_i686_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" + +[[package]] +name = "windows_i686_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66" + +[[package]] +name = "windows_x86_64_gnu" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78" + +[[package]] +name = "windows_x86_64_gnullvm" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.52.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" + +[[package]] +name = "writeable" +version = "0.6.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ad82d2a33cdc9674dc7465672f271e096168fcdbe0f799d9e6db8c5892679dc" + +[[package]] +name = "yoke" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "709fe23a0424b6a435d82152b1bd3fdfb0833487d5fa90d05d42762a9891fef5" +dependencies = [ + "stable_deref_trait", + "yoke-derive", + "zerofrom", +] + +[[package]] +name = "yoke-derive" +version = "0.8.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "de844c262c8848816172cef550288e7dc6c7b7814b4ee56b3e1553f275f1858e" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zerofrom" +version = "0.1.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0ec05a11813ea801ff6d75110ad09cd0824ddba17dfe17128ea0d5f68e6c5272" +dependencies = [ + "zerofrom-derive", +] + +[[package]] +name = "zerofrom-derive" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11532158c46691caf0f2593ea8358fed6bbf68a0315e80aae9bd41fbade684a1" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", + "synstructure", +] + +[[package]] +name = "zeroize" +version = "1.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e13c156562582aa81c60cb29407084cdb54c4164760106ab78e6c5b0858cf64e" + +[[package]] +name = "zerotrie" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4ea269c3bd32f0a32c321907a2ae912ba6f4649bb0fc764a15627e99a7095a3f" +dependencies = [ + "displaydoc", + "yoke", + "zerofrom", +] + +[[package]] +name = "zerovec" +version = "0.11.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bb0464e17806c1d976d5cba29399c7f08e516e279e2ba493f63123b5fca67dd8" +dependencies = [ + "yoke", + "zerofrom", + "zerovec-derive", +] + +[[package]] +name = "zerovec-derive" +version = "0.11.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9f212a141d820099d57ffafb9569be9617a6f27d3dc881fbee8fb56642f917a9" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.3", +] + +[[package]] +name = "zip" +version = "7.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c42e33efc22a0650c311c2ef19115ce232583abbe80850bc8b66509ebef02de0" +dependencies = [ + "crc32fast", + "flate2", + "indexmap", + "memchr", + "time", + "typed-path", + "zopfli", +] + +[[package]] +name = "zlib-rs" +version = "0.6.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "34b31d188d9d685a4f9c7b46d6e36631b07058d2cfe190267adce54dc230bf12" + +[[package]] +name = "zopfli" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f05cd8797d63865425ff89b5c4a48804f35ba0ce8d125800027ad6017d2b5249" +dependencies = [ + "bumpalo", + "crc32fast", + "log", + "simd-adler32", +] diff --git a/vendor/lief/doc/code/rust/Cargo.toml b/vendor/lief/doc/code/rust/Cargo.toml new file mode 100644 index 0000000..112f041 --- /dev/null +++ b/vendor/lief/doc/code/rust/Cargo.toml @@ -0,0 +1,15 @@ +[package] +name = "lief-doc-code" +version = "0.0.0" +edition = "2024" +rust-version = "1.85.0" +publish = false + +[lib] +path = "src/lib.rs" + +[dependencies] +lief = { path = "../../../api/rust/crates/lief" } + +[lints.clippy] +field_reassign_with_default = "allow" diff --git a/vendor/lief/doc/code/rust/src/assembler.rs b/vendor/lief/doc/code/rust/src/assembler.rs new file mode 100644 index 0000000..659cddd --- /dev/null +++ b/vendor/lief/doc/code/rust/src/assembler.rs @@ -0,0 +1,112 @@ +use std::collections::HashMap; +use std::sync::Arc; + +use lief::assembly::Instruction; +use lief::generic::{Binary, Symbol}; + +pub fn disassemble_assemble(some_elf: &mut lief::elf::Binary) { + // lief-doc: disassemble-assemble-start + let elf: &mut lief::elf::Binary = some_elf; + + let syscall_addresses: Vec = elf + .disassemble_address(0x400090) + .filter(|inst| inst.is_syscall()) + .map(|inst| inst.address()) + .collect(); + + for addr in syscall_addresses { + elf.assemble( + addr, + r#" + mov x1, x0; + str x1, [x2, #8]; + "#, + ); + } + // lief-doc: disassemble-assemble-end +} + +pub fn context_error(some_elf: &mut lief::elf::Binary) { + // lief-doc: context-error-start + let elf: &mut lief::elf::Binary = some_elf; + + elf.assemble( + elf.entrypoint(), + r#" + mov rdi, rax; + call a_custom_function; + "#, + ); + // lief-doc: context-error-end +} + +pub fn config_resolver(some_elf: &mut lief::elf::Binary) { + // lief-doc: config-resolver-start + let elf: &mut lief::elf::Binary = some_elf; + + let mut config = lief::assembly::AssemblerConfig::default(); + + let resolver = Arc::new(|symbol: &str| { + if symbol == "a_custom_function" { + return Some(0x1000); + } + None + }); + + config.symbol_resolver = Some(resolver); + + elf.assemble_with_config( + elf.entrypoint(), + r#" + mov rdi, rax; + call a_custom_function; + "#, + &config, + ); + // lief-doc: config-resolver-end +} + +pub fn config_target(some_elf: &mut lief::elf::Binary) { + // lief-doc: config-target-start + let elf: &mut lief::elf::Binary = some_elf; + + let mut config = lief::assembly::AssemblerConfig::default(); + + let sym_map: HashMap = elf + .exported_symbols() + .map(|sym| (sym.name(), sym.value())) + .collect(); + + let resolver = Arc::new(move |symbol: &str| sym_map.get(symbol).copied()); + + config.symbol_resolver = Some(resolver); + + elf.assemble_with_config( + elf.entrypoint(), + r#" + mov rdi, rax; + call a_custom_function; + "#, + &config, + ); + // lief-doc: config-target-end +} + +pub fn disable_instruction(some_elf: &mut lief::elf::Binary) { + // lief-doc: nop-out-start + let elf: &mut lief::elf::Binary = some_elf; + + // Overwrite the first call in the region (e.g. a call to an anti-debugging + // routine) with nops + let target = elf + .disassemble_address(0x401200) + .find(|inst| inst.is_call()) + .map(|inst| (inst.address(), inst.size())); + + if let Some((address, size)) = target { + elf.assemble(address, &"nop\n".repeat(size as usize)); + } + + elf.write("patched.bin"); + // lief-doc: nop-out-end +} diff --git a/vendor/lief/doc/code/rust/src/coff.rs b/vendor/lief/doc/code/rust/src/coff.rs new file mode 100644 index 0000000..4bc9b81 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/coff.rs @@ -0,0 +1,30 @@ +pub fn sections(some_coff: &lief::coff::Binary) { + // lief-doc: sections-start + let coff: &lief::coff::Binary = some_coff; + + for section in coff.sections() { + println!("{section:?} {section}"); + } + // lief-doc: sections-end +} + +pub fn disassemble(some_coff: &lief::coff::Binary) { + // lief-doc: disassemble-start + let coff: &lief::coff::Binary = some_coff; + + for inst in coff.disassemble_function("?foo@@YAHHH@Z") { + println!("{}", inst); + } + + // Using demangled representation + for inst in coff.disassemble_function("int __cdecl bar(int, int)") { + println!("{}", inst); + } + // lief-doc: disassemble-end +} + +pub fn parse_forms() { + // lief-doc: parse-start + let coff: lief::coff::Binary = lief::coff::Binary::parse("test.obj").unwrap(); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/rust/src/disassembler.rs b/vendor/lief/doc/code/rust/src/disassembler.rs new file mode 100644 index 0000000..eac2e56 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/disassembler.rs @@ -0,0 +1,58 @@ +use lief::generic::Binary; + +pub fn disassemble(some_elf: &lief::elf::Binary) { + // lief-doc: disassemble-start + let elf: &lief::elf::Binary = some_elf; + + for inst in elf.disassemble_address(0x400) { + println!("{}", inst); + } + // lief-doc: disassemble-end +} + +// lief-doc: downcast-start +pub fn check_opcode(some_inst: &lief::assembly::Instructions) { + let inst: &lief::assembly::Instructions = some_inst; + + if let lief::assembly::Instructions::RiscV(riscv) = inst { + println!("{:?}", riscv.opcode()); + } +} +// lief-doc: downcast-end + +pub fn dsc_disassemble(some_dyld_cache: &lief::dsc::DyldSharedCache) { + // lief-doc: dsc-disassemble-start + let dyld_cache: &lief::dsc::DyldSharedCache = some_dyld_cache; + + for inst in dyld_cache.disassemble(0x1886f4a44) { + println!("{}", inst); + } + // lief-doc: dsc-disassemble-end +} + +pub fn dwarf_function() { + // lief-doc: dwarf-func-start + let elf = lief::elf::Binary::parse("/bin/ls").unwrap(); + if let Some(lief::DebugInfo::Dwarf(dwarf)) = elf.debug_info() + && let Some(func) = dwarf.function_by_name("main") + { + for inst in func.instructions() { + println!("{}", inst); + } + } + // lief-doc: dwarf-func-end +} + +pub fn x86_lock(some_inst: &lief::assembly::x86::Instruction) { + // lief-doc: x86-lock-start + let inst: &lief::assembly::x86::Instruction = some_inst; + + if inst.has_lock_prefix() || inst.is_atomic() { + println!("{} is atomic", inst); + } else if inst.is_lockable() + && let Some(locked) = inst.lock() + { + println!("atomic version: {}", locked); + } + // lief-doc: x86-lock-end +} diff --git a/vendor/lief/doc/code/rust/src/dsc.rs b/vendor/lief/doc/code/rust/src/dsc.rs new file mode 100644 index 0000000..5917677 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/dsc.rs @@ -0,0 +1,40 @@ +pub fn iterate_libraries(some_dyld_cache: &lief::dsc::DyldSharedCache) { + // lief-doc: libraries-start + let dyld_cache: &lief::dsc::DyldSharedCache = some_dyld_cache; + + for dylib in dyld_cache.libraries() { + println!("0x{:016x}: {}", dylib.address(), dylib.path()); + } + // lief-doc: libraries-end +} + +pub fn extract(some_dyld_cache: &lief::dsc::DyldSharedCache) { + // lief-doc: extract-start + let dyld_cache: &lief::dsc::DyldSharedCache = some_dyld_cache; + + let liblockdown = dyld_cache.find_lib_from_name("liblockdown.dylib").unwrap(); + + let macho = liblockdown.get().unwrap(); + + for segment in macho.segments() { + println!("{}", segment.name()); + } + // lief-doc: extract-end +} + +pub fn write_back(some_dyld_cache: &lief::dsc::DyldSharedCache) { + // lief-doc: write-start + let dyld_cache: &lief::dsc::DyldSharedCache = some_dyld_cache; + + let liblockdown = dyld_cache.find_lib_from_name("liblockdown.dylib").unwrap(); + let mut macho = liblockdown.get().unwrap(); + + macho.write("on-disk-liblockdown.dylib"); + // lief-doc: write-end +} + +pub fn load() { + // lief-doc: load-start + let dyld_cache = lief::dsc::load_from_path("macos-15.0.1/", ""); + // lief-doc: load-end +} diff --git a/vendor/lief/doc/code/rust/src/dwarf.rs b/vendor/lief/doc/code/rust/src/dwarf.rs new file mode 100644 index 0000000..234de5e --- /dev/null +++ b/vendor/lief/doc/code/rust/src/dwarf.rs @@ -0,0 +1,140 @@ +use std::path::{Path, PathBuf}; +use std::process; + +use lief::dwarf::editor::types::EditorType; +use lief::dwarf::types::DwarfType; +use lief::generic::Binary; + +pub fn embedded() { + // lief-doc: embedded-start + let elf = lief::elf::Binary::parse("/bin/ls").unwrap(); + if let Some(lief::DebugInfo::Dwarf(dwarf)) = elf.debug_info() { + // DWARF debug info + } + // lief-doc: embedded-end +} + +pub fn load() { + // lief-doc: load-start + let dbg = lief::dwarf::load("/bin/with_debug"); + let dbg = lief::dwarf::load("external_dwarf"); + let dbg = lief::dwarf::load("debug.dwo"); + // lief-doc: load-end +} + +pub fn iterate(some_path: &Path) { + // lief-doc: iterate-start + let path: &Path = some_path; + + let dbg = lief::dwarf::load(path).unwrap_or_else(|| { + process::exit(1); + }); + + for cu in dbg.compilation_units() { + println!("Producer: {}", cu.producer()); + for func in cu.functions() { + println!( + "name={}, linkage={}, address={}", + func.name(), + func.linkage_name(), + func.address().unwrap_or(0) + ); + } + + for var in cu.variables() { + println!( + "name={}, address={}", + var.name(), + var.address().unwrap_or(0) + ); + } + + for ty in cu.types() { + println!( + "name={}, size={}", + ty.name().unwrap_or("".to_string()), + ty.size().unwrap_or(0) + ); + } + } + + dbg.function_by_name("_ZNSi4peekEv"); + dbg.function_by_name("std::basic_istream >::peek()"); + dbg.function_by_addr(0x137a70); + + dbg.variable_by_name("_ZNSt12out_of_rangeC1EPKc"); + dbg.variable_by_name("std::out_of_range::out_of_range(char const*)"); + dbg.variable_by_addr(0x137a70); + // lief-doc: iterate-end +} + +pub fn load_external(some_bin: &mut dyn lief::generic::Binary) { + // lief-doc: load-external-start + let bin: &mut dyn lief::generic::Binary = some_bin; + + let path = PathBuf::from("/home/romain/dev/LIEF/some.dwo"); + + bin.load_debug_info(&path); + // lief-doc: load-external-end +} + +pub fn disassemble_external(some_bin: &mut dyn lief::generic::Binary) { + // lief-doc: disassemble-start + let bin: &mut dyn lief::generic::Binary = some_bin; + + let path = PathBuf::from("/home/romain/dev/LIEF/some.dwo"); + + bin.load_debug_info(&path); + + // The location (address/size) of `my_function` is defined in some.dwo + for inst in bin.disassemble_symbol("my_function") { + println!("{inst}"); + } + // lief-doc: disassemble-end +} + +pub fn to_decl() { + // lief-doc: to-decl-start + let dbg = lief::dwarf::load("/bin/with_debug").unwrap(); + + if let Some(func) = dbg.function_by_name("main") { + println!("{}", func.to_decl()); + } + + let opt = lief::DeclOpt { + is_cpp: true, + indentation: 4, + ..Default::default() + }; + for cu in dbg.compilation_units() { + println!("{}", cu.to_decl_with_opt(&opt)); + } + // lief-doc: to-decl-end +} + +pub fn editor_from_binary(some_path: &Path) { + // lief-doc: editor-from-binary-start + let path: &Path = some_path; + + let mut bin = lief::pe::Binary::parse(path).unwrap(); + let editor = lief::dwarf::Editor::from_binary(&mut bin); + // lief-doc: editor-from-binary-end +} + +pub fn editor_create(some_editor: &mut lief::dwarf::Editor) { + // lief-doc: editor-create-start + let editor: &mut lief::dwarf::Editor = some_editor; + + let mut unit = editor.create_compile_unit().unwrap(); + unit.set_producer("LIEF"); + + let mut func = unit.create_function("hello").unwrap(); + func.set_address(0x123); + func.set_return_type(&unit.create_structure("my_struct_t").pointer_to()); + + let mut var = func.create_stack_variable("local_var"); + var.set_stack_offset(8); + + editor.write("/tmp/out.debug"); + // lief-doc: editor-create-end +} diff --git a/vendor/lief/doc/code/rust/src/elf.rs b/vendor/lief/doc/code/rust/src/elf.rs new file mode 100644 index 0000000..10421d8 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/elf.rs @@ -0,0 +1,202 @@ +use std::path::PathBuf; + +use lief::elf::dynamic; +use lief::generic::Section; + +pub fn inspect(some_elf: &lief::elf::Binary) { + // lief-doc: inspect-start + let elf: &lief::elf::Binary = some_elf; + + println!("{}", elf.header().entrypoint()); + + for section in elf.sections() { + println!("{} {}", section.name(), section.content().len()); + } + // lief-doc: inspect-end +} + +pub fn modify_write(some_elf: &mut lief::elf::Binary) { + // lief-doc: write-start + let elf: &mut lief::elf::Binary = some_elf; + + elf.add_library("libdemo.so"); + elf.write("new.elf"); + // lief-doc: write-end +} + +pub fn write_bytes(some_elf: &mut lief::elf::Binary) { + // lief-doc: write-bytes-start + let elf: &mut lief::elf::Binary = some_elf; + + let bytes: Vec = elf.write_to_bytes(); + // lief-doc: write-bytes-end +} + +pub fn add_loaded_segment(some_elf: &mut lief::elf::Binary) { + // lief-doc: add-segment-start + let elf: &mut lief::elf::Binary = some_elf; + + let mut segment = lief::elf::Segment::new(); + segment.set_type(lief::elf::segment::Type::LOAD); + segment.set_content(&[1, 2, 3]); + + elf.add_segment(&segment); + elf.write("new.elf"); + // lief-doc: add-segment-end +} + +pub fn add_loaded_section(some_elf: &mut lief::elf::Binary) { + // lief-doc: add-section-loaded-start + let elf: &mut lief::elf::Binary = some_elf; + + let section = lief::elf::Section::new_with_content(".lief_demo", &[1, 2, 3]); + + elf.add_section( + §ion, + /* loaded= */ true, + lief::elf::binary::SecInsertPos::AUTO, + ); + elf.write("new.elf"); + // lief-doc: add-section-loaded-end +} + +pub fn add_unloaded_section(some_elf: &mut lief::elf::Binary) { + // lief-doc: add-section-unloaded-start + let elf: &mut lief::elf::Binary = some_elf; + + let section = lief::elf::Section::new_with_content(".metadata", b"version: 1.2.3"); + + // /!\ Note that loaded is set to false here + // ----------------------------------------- + elf.add_section( + §ion, + /* loaded= */ false, + lief::elf::binary::SecInsertPos::AUTO, + ); + elf.write("new.elf"); + // lief-doc: add-section-unloaded-end +} + +pub fn parse_from_dump() { + // lief-doc: dump-start + let elf = lief::elf::Binary::parse_from_dump("module.dump", 0x7f9b_98e0_0000).unwrap(); + + for segment in elf.segments() { + println!("{:?} {:#x}", segment.p_type(), segment.virtual_address()); + } + // lief-doc: dump-end +} + +pub fn module_dump() { + // lief-doc: dump-runtime-start + use lief::runtime::Module; + + let module = lief::runtime::module_from_name("libc.so.6").unwrap(); + + // Dump the module's memory into a file (the raw bytes are also returned) + let data = module.dump_to_file("module.dump"); + + let elf = lief::elf::Binary::parse_from_dump("module.dump", module.imagebase()).unwrap(); + // lief-doc: dump-runtime-end +} + +pub fn advanced_parse_write() { + // lief-doc: advanced-start + let mut parser_config = lief::elf::ParserConfig::default(); + parser_config.parse_overlay = false; + + let mut elf = lief::elf::parse_with_config("my.elf", &parser_config).unwrap(); + + let mut builder_config = lief::elf::builder::Config::default(); + builder_config.gnu_hash = false; + + elf.write_with_config("new.elf", builder_config); + // lief-doc: advanced-end +} + +pub fn rpath_add(some_elf: &mut lief::elf::Binary) { + // lief-doc: rpath-add-start + let elf: &mut lief::elf::Binary = some_elf; + + let runpath = lief::elf::dynamic::RunPath::new("$ORIGIN:/opt/lib64"); + + elf.add_dynamic_entry(&runpath); + + let other_runpath = lief::elf::dynamic::RunPath::with_paths(&["$ORIGIN", "/opt/lib64"]); + + elf.add_dynamic_entry(&other_runpath); + + let output = PathBuf::from("updated.elf"); + + elf.write(output.as_path()); + // lief-doc: rpath-add-end +} + +pub fn rpath_change(some_elf: &mut lief::elf::Binary) { + // lief-doc: rpath-change-start + let elf: &mut lief::elf::Binary = some_elf; + + if let Some(dynamic::Entries::RunPath(mut runpath)) = + elf.dynamic_entry_by_tag(dynamic::Tag::RUNPATH) + { + runpath.set_runpath("$ORIGIN:/opt/lib64"); + runpath.append("lib-x86_64-gnu"); + } + + let output = PathBuf::from("updated.elf"); + + elf.write(output.as_path()); + // lief-doc: rpath-change-end +} + +pub fn rpath_remove(some_elf: &mut lief::elf::Binary) { + // lief-doc: rpath-remove-start + let elf: &mut lief::elf::Binary = some_elf; + + // Remove **all** DT_RUNPATH entries + elf.remove_dynamic_entries_by_tag(dynamic::Tag::RUNPATH); + + // Remove all entries that contain '$ORIGIN' + elf.remove_dynamic_entry_if(|e| { + if let dynamic::Entries::RunPath(runpath) = e { + return runpath.runpath().contains("$ORIGIN"); + } + false + }); + + let output = PathBuf::from("updated.elf"); + elf.write(output.as_path()); + // lief-doc: rpath-remove-end +} + +pub fn symver_remove_symbol(some_elf: &mut lief::elf::Binary) { + // lief-doc: symver-symbol-start + let elf: &mut lief::elf::Binary = some_elf; + + if let Some(sym) = elf.dynamic_symbol_by_name("printf") + && let Some(mut symver) = sym.symbol_version() + { + symver.as_global(); + } + + let output = PathBuf::from("updated.elf"); + elf.write(output.as_path()); + // lief-doc: symver-symbol-end +} + +pub fn symver_remove_library(some_elf: &mut lief::elf::Binary) { + // lief-doc: symver-library-start + let elf: &mut lief::elf::Binary = some_elf; + + elf.remove_version_requirement("libm.so.6"); + + let output = PathBuf::from("updated.elf"); + elf.write(output.as_path()); + // lief-doc: symver-library-end +} + +pub fn parse_forms() { + // lief-doc: parse-start + let elf: lief::elf::Binary = lief::elf::Binary::parse("/bin/ls").unwrap(); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/rust/src/intro.rs b/vendor/lief/doc/code/rust/src/intro.rs new file mode 100644 index 0000000..ec2448b --- /dev/null +++ b/vendor/lief/doc/code/rust/src/intro.rs @@ -0,0 +1,32 @@ +use std::path::Path; +use std::process; + +pub fn intro(path: &Path) { + // lief-doc: intro-start + let mut file = std::fs::File::open(path).expect("Can't open the file"); + + if let Some(lief::Binary::PE(pe)) = lief::Binary::from(&mut file) { + let rich_header = pe.rich_header().unwrap_or_else(|| { + println!("Rich header not found!"); + process::exit(0); + }); + + println!("Rich header key: 0x{:x}", rich_header.key()); + for entry in rich_header.entries() { + println!( + "id: 0x{:04x} build_id: 0x{:04x} count: #{}", + entry.id(), + entry.build_id(), + entry.count() + ); + } + + let result = pe.verify_signature(lief::pe::signature::VerificationChecks::DEFAULT); + if result == lief::pe::signature::VerificationFlags::OK { + println!("Valid signature!"); + } else { + println!("Signature not valid: {:?}", result); + } + } + // lief-doc: intro-end +} diff --git a/vendor/lief/doc/code/rust/src/lib.rs b/vendor/lief/doc/code/rust/src/lib.rs new file mode 100644 index 0000000..2d720b0 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/lib.rs @@ -0,0 +1,20 @@ +#![allow(dead_code, unused_variables, unused_mut, unused_imports)] + +pub mod assembler; +pub mod coff; +pub mod disassembler; +pub mod dsc; +pub mod dwarf; +pub mod elf; +pub mod intro; +pub mod logging; +pub mod macho; +pub mod memory_layout; +pub mod objc; +pub mod pdb; +pub mod pe; +pub mod pe_debug; +pub mod pe_exports; +pub mod pe_imports; +pub mod pe_resources; +pub mod pe_tls; diff --git a/vendor/lief/doc/code/rust/src/logging.rs b/vendor/lief/doc/code/rust/src/logging.rs new file mode 100644 index 0000000..b647004 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/logging.rs @@ -0,0 +1,12 @@ +pub fn example() { + // lief-doc: example-start + // Set global level to Err + lief::logging::set_level(lief::logging::Level::Err); + + { + // Temporarily set global level to Debug (RAII) + let _scoped = lief::logging::Scoped::new(lief::logging::Level::Debug); + lief::logging::log(lief::logging::Level::Debug, "This is a debug message"); + } + // lief-doc: example-end +} diff --git a/vendor/lief/doc/code/rust/src/macho.rs b/vendor/lief/doc/code/rust/src/macho.rs new file mode 100644 index 0000000..c65a656 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/macho.rs @@ -0,0 +1,114 @@ +use lief::generic::Binary; +use lief::macho::commands::RPath; + +pub fn iterate(some_fat: &lief::macho::FatBinary) { + // lief-doc: iterate-start + let fat: &lief::macho::FatBinary = some_fat; + + // Iterate + for macho in fat.iter() { + println!("{}", macho.entrypoint()); + } + + // Pick one with the given arch + let arm64 = fat + .with_cpu(lief::macho::header::CpuType::ARM64) + .expect("Missing ARM64"); + // lief-doc: iterate-end +} + +pub fn write_bytes(some_macho: &mut lief::macho::Binary) { + // lief-doc: write-bytes-start + let macho: &mut lief::macho::Binary = some_macho; + + let bytes: Vec = macho.write_to_bytes(); + // lief-doc: write-bytes-end +} + +pub fn parse_from_dump() { + // lief-doc: dump-start + let fat = lief::macho::FatBinary::parse_from_dump("module.dump", 0x1_1e32_c000).unwrap(); + let macho = fat.iter().next().unwrap(); + + for segment in macho.segments() { + println!("{} {:#x}", segment.name(), segment.virtual_address()); + } + // lief-doc: dump-end +} + +pub fn module_dump() { + // lief-doc: dump-runtime-start + use lief::runtime::Module; + + let module = lief::runtime::module_from_name("libsystem_c.dylib").unwrap(); + + // Dump the module's memory into a file (the raw bytes are also returned) + let data = module.dump_to_file("module.dump"); + + let fat = lief::macho::FatBinary::parse_from_dump("module.dump", module.imagebase()).unwrap(); + // lief-doc: dump-runtime-end +} + +pub fn rpath_change_lib() { + // lief-doc: rpath-change-lib-start + let fat = lief::macho::FatBinary::parse("hello.bin").unwrap(); + let mut binary = fat.iter().next().unwrap(); + + let mut lib = binary.find_library("libmylib.dylib").unwrap(); + lib.set_name("/opt/homebrew/my_package/libmylib.dylib"); + + binary.write("hello_fixed.bin"); + // lief-doc: rpath-change-lib-end +} + +pub fn rpath_add() { + // lief-doc: rpath-add-start + let fat = lief::macho::FatBinary::parse("hello.bin").unwrap(); + let mut binary = fat.iter().next().unwrap(); + + let rpath = RPath::new("/opt/homebrew/my_package"); + binary.add_command(rpath); + // lief-doc: rpath-add-end +} + +pub fn rpath_atrpath(some_binary: &mut lief::macho::Binary) { + // lief-doc: rpath-atrpath-start + let binary: &mut lief::macho::Binary = some_binary; + + let mut lib = binary.find_library("libmylib.dylib").unwrap(); + lib.set_name("@rpath/libmylib.dylib"); + + binary.write("hello_fixed.bin"); + // lief-doc: rpath-atrpath-end +} + +pub fn parse_forms() { + // lief-doc: parse-start + let macho: lief::macho::FatBinary = lief::macho::FatBinary::parse("/bin/ls").unwrap(); + // lief-doc: parse-end +} + +pub fn write_fat(some_fat: &mut lief::macho::FatBinary) { + // lief-doc: write-fat-start + let fat: &mut lief::macho::FatBinary = some_fat; + fat.with_cpu(lief::macho::header::CpuType::ARM64) + .unwrap() + .write("fit.macho"); + // lief-doc: write-fat-end +} + +pub fn advanced_parse_write() { + // lief-doc: advanced-start + let mut parser_config = lief::macho::ParserConfig::default(); + parser_config.parse_dyld_bindings = false; + + let mut fat = lief::macho::parse_with_config("my.macho", &parser_config).unwrap(); + + let mut macho = fat.iter().next().unwrap(); + + let mut builder_config = lief::macho::builder::Config::default(); + builder_config.linkedit = false; + + macho.write_with_config("new.macho", builder_config); + // lief-doc: advanced-end +} diff --git a/vendor/lief/doc/code/rust/src/memory_layout.rs b/vendor/lief/doc/code/rust/src/memory_layout.rs new file mode 100644 index 0000000..dfc05b1 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/memory_layout.rs @@ -0,0 +1,70 @@ +use std::collections::BTreeMap; + +pub fn iterate() { + // lief-doc: iterate-start + for region in lief::runtime::memory_layout() { + println!( + "{:#014x}-{:#014x} {}", + region.addr(), + region.end_addr(), + region.name() + ); + } + // lief-doc: iterate-end +} + +pub fn inspect(address: u64) { + // lief-doc: inspect-start + let mut count = 0usize; + let mut mapped = 0u64; + let mut footprint: BTreeMap = BTreeMap::new(); + let mut enclosing: Option = None; + + for region in lief::runtime::memory_layout() { + count += 1; + mapped += region.size(); + + let mut name = region.name(); + if name.is_empty() { + name = String::from(""); + } + + *footprint.entry(name).or_insert(0) += region.size(); + + if region.contains(address) { + enclosing = Some(region); + } + } + + println!("{count} regions, {} KB mapped", mapped / 1024); + + for (name, size) in &footprint { + println!("{size:#010x} {name}"); + } + + if let Some(region) = enclosing { + println!( + "{address:#x}: {}+{:#x}", + region.name(), + address - region.addr() + ); + } + // lief-doc: inspect-end +} + +pub fn stack_and_heap() { + // lief-doc: stack-heap-start + for region in lief::runtime::memory_layout() { + // On Linux and Android, the kernel names the regions that back the + // stack and the heap of the process. + let name = region.name(); + if name == "[stack]" || name == "[heap]" { + println!( + "{name}: {:#014x}-{:#014x}", + region.addr(), + region.end_addr() + ); + } + } + // lief-doc: stack-heap-end +} diff --git a/vendor/lief/doc/code/rust/src/objc.rs b/vendor/lief/doc/code/rust/src/objc.rs new file mode 100644 index 0000000..d2f9929 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/objc.rs @@ -0,0 +1,38 @@ +use std::process; + +pub fn check(some_macho: &lief::macho::Binary) { + // lief-doc: check-start + let macho: &lief::macho::Binary = some_macho; + + if let Some(metadata) = macho.objc_metadata() { + println!("Objective-C metadata found"); + } + // lief-doc: check-end +} + +pub fn inspect(some_macho: &lief::macho::Binary) { + // lief-doc: inspect-start + let macho: &lief::macho::Binary = some_macho; + + let Some(metadata) = macho.objc_metadata() else { + process::exit(1); + }; + + for class in metadata.classes() { + println!("name={}", class.name()); + for method in class.methods() { + println!(" method.name={}", method.name()); + } + } + println!("{}", metadata.to_decl()); + // lief-doc: inspect-end +} + +// lief-doc: classdump-start +fn classdump(macho: &lief::macho::Binary) { + let metadata = macho.objc_metadata().expect("Missing Objective-C info"); + for class in metadata.classes() { + println!("{}", class.to_decl()); + } +} +// lief-doc: classdump-end diff --git a/vendor/lief/doc/code/rust/src/pdb.rs b/vendor/lief/doc/code/rust/src/pdb.rs new file mode 100644 index 0000000..79589b8 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pdb.rs @@ -0,0 +1,105 @@ +use std::path::{Path, PathBuf}; +use std::process; + +use lief::generic::Binary; +use lief::pdb::types::PdbType; + +pub fn load_pdb(some_pe: &lief::pe::Binary) { + // lief-doc: load-start + let pe: &lief::pe::Binary = some_pe; + if let Some(lief::DebugInfo::Pdb(pdb)) = pe.debug_info() { + // PDB debug info + } + + let pdb = lief::pdb::load("some.pdb"); + // lief-doc: load-end +} + +pub fn load_ext(some_bin: &mut dyn lief::generic::Binary) { + // lief-doc: load-ext-start + let bin: &mut dyn lief::generic::Binary = some_bin; + + let path = PathBuf::from("C:\\Users\\romain\\LIEF.pdb"); + + bin.load_debug_info(&path); + // lief-doc: load-ext-end +} + +pub fn disassemble(some_bin: &mut dyn lief::generic::Binary) { + // lief-doc: disassemble-start + let bin: &mut dyn lief::generic::Binary = some_bin; + + let path = PathBuf::from("C:\\Users\\romain\\LIEF.pdb"); + + bin.load_debug_info(&path); + + // The location (address/size) of `my_function` is defined in LIEF.pdb + for inst in bin.disassemble_symbol("my_function") { + println!("{inst}"); + } + // lief-doc: disassemble-end +} + +pub fn to_decl(some_pdb: &lief::pdb::DebugInfo) { + // lief-doc: to-decl-start + let pdb: &lief::pdb::DebugInfo = some_pdb; + + let opt = lief::DeclOpt { + is_cpp: true, + ..Default::default() + }; + + for ty in pdb.types() { + println!("{}", ty.to_decl_with_opt(&opt)); + } + + for cu in pdb.compilation_units() { + println!("{}", cu.to_decl_with_opt(&opt)); + for func in cu.functions() { + println!("{}", func.to_decl_with_opt(&opt)); + } + } + // lief-doc: to-decl-end +} + +pub fn explore(path: &Path) { + // lief-doc: explore-start + let pdb = lief::pdb::load(path).unwrap_or_else(|| { + process::exit(1); + }); + + println!("age={}, guid={}", pdb.age(), pdb.guid()); + + for symbol in pdb.public_symbols() { + println!( + "name={}, section={}, RVA={}", + symbol.name(), + symbol.section_name().unwrap_or("".to_string()), + symbol.rva() + ); + } + + for ty in pdb.types() { + if let lief::pdb::Type::Class(clazz) = ty { + println!("Class[name]={}", clazz.name().unwrap_or_default()); + } + } + + for cu in pdb.compilation_units() { + println!("module={}", cu.module_name()); + for src in cu.sources() { + println!(" - {}", src); + } + + for func in cu.functions() { + println!( + "name={}, section={}, RVA={}, code_size={}", + func.name(), + func.section_name(), + func.rva(), + func.code_size() + ); + } + } + // lief-doc: explore-end +} diff --git a/vendor/lief/doc/code/rust/src/pe.rs b/vendor/lief/doc/code/rust/src/pe.rs new file mode 100644 index 0000000..0bc12fc --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe.rs @@ -0,0 +1,93 @@ +use lief::generic::Section; + +pub fn inspect(some_pe: &lief::pe::Binary) { + // lief-doc: inspect-start + let pe: &lief::pe::Binary = some_pe; + + println!("{:?}", pe.rich_header().expect("Missing Rich header")); + + for section in pe.sections() { + println!("{} {}", section.name(), section.content().len()); + } + // lief-doc: inspect-end +} + +pub fn add_section() { + // lief-doc: add-section-start + let mut pe = lief::pe::Binary::parse("some.exe").unwrap(); + + let mut section = lief::pe::Section::new_with_name(".hello"); + section.set_content(&[0xCC; 0x100]); + pe.add_section(section); + + pe.write("new.exe"); + // lief-doc: add-section-end +} + +pub fn parse_from_dump() { + // lief-doc: dump-start + let pe = lief::pe::Binary::parse_from_dump("module.dump", 0x7ffd_21b8_0000).unwrap(); + + for imp in pe.imports() { + println!("{}", imp.name()); + } + // lief-doc: dump-end +} + +pub fn module_dump() { + // lief-doc: dump-runtime-start + use lief::runtime::Module; + + let module = lief::runtime::module_from_name("target.dll").unwrap(); + + // Dump the module's memory into a file (the raw bytes are also returned) + let data = module.dump_to_file("module.dump"); + + let pe = lief::pe::Binary::parse_from_dump("module.dump", module.imagebase()).unwrap(); + // lief-doc: dump-runtime-end +} + +pub fn advanced_parse_write() { + // lief-doc: advanced-start + let mut parser_config = lief::pe::parser_config::Config::default(); + parser_config.parse_signature = false; + + let mut pe = lief::pe::parse_with_config("some.exe", &parser_config).unwrap(); + + let mut config = lief::pe::builder::Config::default(); + config.imports = true; + + pe.write_with_config("new.exe", config); + // lief-doc: advanced-end +} + +pub fn write_bytes(some_pe: &mut lief::pe::Binary) { + // lief-doc: write-bytes-start + let pe: &mut lief::pe::Binary = some_pe; + + let bytes: Vec = pe.write_to_bytes(); + // lief-doc: write-bytes-end +} + +pub fn authenticode() { + // lief-doc: authenticode-start + if let Some(lief::Binary::PE(pe)) = lief::Binary::parse("signed.exe") { + for sig in pe.signatures() { + for crt in sig.certificates() { + println!("{:?}", crt); + } + } + + assert!( + pe.verify_signature(lief::pe::signature::VerificationChecks::DEFAULT) + == lief::pe::signature::VerificationFlags::OK + ); + } + // lief-doc: authenticode-end +} + +pub fn parse_forms() { + // lief-doc: parse-start + let pe: lief::pe::Binary = lief::pe::Binary::parse("/bin/ls").unwrap(); + // lief-doc: parse-end +} diff --git a/vendor/lief/doc/code/rust/src/pe_debug.rs b/vendor/lief/doc/code/rust/src/pe_debug.rs new file mode 100644 index 0000000..ba02d55 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe_debug.rs @@ -0,0 +1,40 @@ +pub fn change_name(some_pe: &mut lief::pe::Binary) { + // lief-doc: change-name-start + let pe: &mut lief::pe::Binary = some_pe; + + pe.codeview_pdb() + .unwrap() + .set_filename(r#"C:\A\B\C\path.pdb"#); + + pe.write("out.exe"); + // lief-doc: change-name-end +} + +pub fn add(some_pe: &mut lief::pe::Binary) { + // lief-doc: add-start + let pe: &mut lief::pe::Binary = some_pe; + + let cv = lief::pe::debug::CodeViewPDB::with_filename("MyCustom.pdb"); + + pe.add_debug_info(&cv); + + pe.write("out.exe"); + // lief-doc: add-end +} + +pub fn remove(some_pe: &mut lief::pe::Binary) { + // lief-doc: remove-start + let pe: &mut lief::pe::Binary = some_pe; + + // Remove a single CodeViewPDB entry + if let Some(cv_pdb) = pe.codeview_pdb() { + todo!("Not Implemented yet"); + //pe.remove_debug(cv_pdb); + } + + // Remove all entries + pe.clear_debug(); + + pe.write("out.exe"); + // lief-doc: remove-end +} diff --git a/vendor/lief/doc/code/rust/src/pe_exports.rs b/vendor/lief/doc/code/rust/src/pe_exports.rs new file mode 100644 index 0000000..2b76e87 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe_exports.rs @@ -0,0 +1,48 @@ +pub fn convert_to_dll(some_pe: &mut lief::pe::Binary) { + // lief-doc: dll-header-start + let pe: &mut lief::pe::Binary = some_pe; + + pe.header() + .add_characteristic(lief::pe::headers::Characteristics::DLL); + pe.optional_header().set_addressof_entrypoint(0); + // lief-doc: dll-header-end +} + +pub fn create_export_table(some_pe: &mut lief::pe::Binary) { + // lief-doc: create-table-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut exp = lief::pe::Export::new(); + + exp.set_name("lib_exe2dll.dll"); + exp.add_entry_by_name("cbk1", 0x0001000); + exp.add_entry_by_name("cbk2", 0x0001010); + + pe.set_export(&exp); + + let mut config = lief::pe::builder::Config::default(); + config.exports = true; + + pe.write_with_config("lib_exe2dll.dll", config); + // lief-doc: create-table-end +} + +pub fn create_export_entries(some_pe: &mut lief::pe::Binary) { + // lief-doc: create-entries-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut exp: lief::pe::Export = pe.export().unwrap(); + + // Remove an entry + exp.remove_entry_by_name("my_exported_name"); + + // Add a new export + exp.add_entry_by_name("fuzz_me", 0x10010); + + let mut config = lief::pe::builder::Config::default(); + config.exports = true; + config.export_section = ".myedata".to_string(); + + pe.write_with_config("out.dll", config); + // lief-doc: create-entries-end +} diff --git a/vendor/lief/doc/code/rust/src/pe_imports.rs b/vendor/lief/doc/code/rust/src/pe_imports.rs new file mode 100644 index 0000000..a60101e --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe_imports.rs @@ -0,0 +1,55 @@ +pub fn remove_import(some_pe: &mut lief::pe::Binary) { + // lief-doc: remove-import-start + let pe: &mut lief::pe::Binary = some_pe; + + pe.remove_import("kernel32.dll"); + + let mut config = lief::pe::builder::Config::default(); + config.imports = true; + + pe.write_with_config("new.exe", config); + // lief-doc: remove-import-end +} + +pub fn remove_import_entry(some_pe: &mut lief::pe::Binary) { + // lief-doc: remove-import-entry-start + let pe: &mut lief::pe::Binary = some_pe; + + if let Some(mut kernel32) = pe.import_by_name("kernel32.dll") { + kernel32.remove_entry_by_name("IsDebuggerPresent"); + } + + let mut config = lief::pe::builder::Config::default(); + config.imports = true; + + pe.write_with_config("new.exe", config); + // lief-doc: remove-import-entry-end +} + +pub fn add_import(some_pe: &mut lief::pe::Binary) { + // lief-doc: add-import-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut stdio = pe.add_import("api-ms-win-crt-stdio-l1-1-0.dll"); + let _puts = stdio.add_entry_by_name("puts"); + + let mut config = lief::pe::builder::Config::default(); + config.imports = true; + + pe.write_with_config("new.exe", config); + // lief-doc: add-import-end +} + +pub fn add_import_func(some_pe: &mut lief::pe::Binary) { + // lief-doc: add-import-func-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut kernel32 = pe.add_import("kernel32.dll"); + let _get_startup_info = kernel32.add_entry_by_name("GetStartupInfoW"); + + let mut config = lief::pe::builder::Config::default(); + config.imports = true; + + pe.write_with_config("new.exe", config); + // lief-doc: add-import-func-end +} diff --git a/vendor/lief/doc/code/rust/src/pe_resources.rs b/vendor/lief/doc/code/rust/src/pe_resources.rs new file mode 100644 index 0000000..3b8dd07 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe_resources.rs @@ -0,0 +1,59 @@ +use lief::pe::resources::{Node, NodeBase}; + +pub fn access_root(some_pe: &lief::pe::Binary) { + // lief-doc: access-root-start + let pe: &lief::pe::Binary = some_pe; + + let rsrc = pe.resources().unwrap(); + + println!("{}", &rsrc as &dyn NodeBase); + // lief-doc: access-root-end +} + +pub fn add_child(some_pe: &mut lief::pe::Binary) { + // lief-doc: add-child-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut root = pe.resources().unwrap(); + + let mut dir_node = lief::pe::resources::Directory::with_id(100); + let data_node = lief::pe::resources::Data::with_buffer(&[1, 2, 3]); + + dir_node.add_child(&Node::Data(data_node)); + root.add_child(&Node::Directory(dir_node)); + + pe.write("new.exe"); + // lief-doc: add-child-end +} + +pub fn set_manifest(some_pe: &mut lief::pe::Binary) { + // lief-doc: manifest-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut manager = pe.resources_manager().unwrap(); + + manager.set_manifest( + r#" + + + + + + + + + + + "#, + ); + + pe.write("new.exe"); + // lief-doc: manifest-end +} + +pub fn transfer_resources(from_pe: &lief::pe::Binary, to_pe: &mut lief::pe::Binary) { + // lief-doc: transfer-start + to_pe.set_resources(&from_pe.resources().unwrap()); + // lief-doc: transfer-end +} diff --git a/vendor/lief/doc/code/rust/src/pe_tls.rs b/vendor/lief/doc/code/rust/src/pe_tls.rs new file mode 100644 index 0000000..f998275 --- /dev/null +++ b/vendor/lief/doc/code/rust/src/pe_tls.rs @@ -0,0 +1,36 @@ +pub fn modify_callbacks(some_pe: &mut lief::pe::Binary) { + // lief-doc: modify-callbacks-start + let pe: &mut lief::pe::Binary = some_pe; + + let mut tls = pe.tls().unwrap(); + + let mut callbacks: Vec = tls.callbacks(); + + // Remove the last entry + callbacks.pop(); + + // Add an address + callbacks.push(0x140001010); + + tls.set_callbacks(&callbacks); + + pe.write("tls_modified.exe"); + // lief-doc: modify-callbacks-end +} + +pub fn create_tls() { + // lief-doc: create-tls-start + let mut tls = lief::pe::TLS::new(); + + tls.set_callbacks(&[0x140001000, 0x140001010]); + // lief-doc: create-tls-end +} + +pub fn add_tls(pe: &mut lief::pe::Binary) { + let tls = lief::pe::TLS::new(); + // lief-doc: add-tls-start + pe.set_tls(&tls); // `tls` defined previously + + pe.write("tls_demo.exe"); + // lief-doc: add-tls-end +} diff --git a/vendor/lief/doc/doxygen/Doxyfile b/vendor/lief/doc/doxygen/Doxyfile index 3edfc58..2092871 100644 --- a/vendor/lief/doc/doxygen/Doxyfile +++ b/vendor/lief/doc/doxygen/Doxyfile @@ -1,4 +1,4 @@ -# Doxyfile 1.8.20 +# Doxyfile 1.9.8 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project. @@ -12,6 +12,16 @@ # For lists, items can also be appended using: # TAG += value [value, ...] # Values that contain spaces should be placed between quotes (\" \"). +# +# Note: +# +# Use doxygen to compare the used configuration file with the template +# configuration file: +# doxygen -x [configFile] +# Use doxygen to compare the used configuration file with the template +# configuration file without replacing the environment variables or CMake type +# replacement variables: +# doxygen -x_noenv [configFile] #--------------------------------------------------------------------------- # Project related configuration options @@ -60,16 +70,28 @@ PROJECT_LOGO = $(LIEF_LOGO) OUTPUT_DIRECTORY = ./doxygen -# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- -# directories (in 2 levels) under the output directory of each output format and -# will distribute the generated files over these directories. Enabling this +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create up to 4096 +# sub-directories (in 2 levels) under the output directory of each output format +# and will distribute the generated files over these directories. Enabling this # option can be useful when feeding doxygen a huge amount of source files, where # putting all generated files in the same directory would otherwise causes -# performance problems for the file system. +# performance problems for the file system. Adapt CREATE_SUBDIRS_LEVEL to +# control the number of sub-directories. # The default value is: NO. CREATE_SUBDIRS = NO +# Controls the number of sub-directories that will be created when +# CREATE_SUBDIRS tag is set to YES. Level 0 represents 16 directories, and every +# level increment doubles the number of directories, resulting in 4096 +# directories at level 8 which is the default and also the maximum value. The +# sub-directories are organized in 2 levels, the first level always has a fixed +# number of 16 directories. +# Minimum value: 0, maximum value: 8, default value: 8. +# This tag requires that the tag CREATE_SUBDIRS is set to YES. + +CREATE_SUBDIRS_LEVEL = 8 + # If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII # characters to appear in the names of generated files. If set to NO, non-ASCII # characters will be escaped, for example _xE3_x81_x84 will be used for Unicode @@ -81,14 +103,14 @@ ALLOW_UNICODE_NAMES = NO # The OUTPUT_LANGUAGE tag is used to specify the language in which all # documentation generated by doxygen is written. Doxygen will use this # information to generate all constant output in the proper language. -# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, -# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), -# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, -# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), -# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, -# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, -# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, -# Ukrainian and Vietnamese. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Bulgarian, +# Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, English +# (United States), Esperanto, Farsi (Persian), Finnish, French, German, Greek, +# Hindi, Hungarian, Indonesian, Italian, Japanese, Japanese-en (Japanese with +# English messages), Korean, Korean-en (Korean with English messages), Latvian, +# Lithuanian, Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, +# Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, +# Swedish, Turkish, Ukrainian and Vietnamese. # The default value is: English. OUTPUT_LANGUAGE = English @@ -250,16 +272,16 @@ TAB_SIZE = 4 # the documentation. An alias has the form: # name=value # For example adding -# "sideeffect=@par Side Effects:\n" +# "sideeffect=@par Side Effects:^^" # will allow you to put the command \sideeffect (or @sideeffect) in the # documentation, which will result in a user-defined paragraph with heading -# "Side Effects:". You can put \n's in the value part of an alias to insert -# newlines (in the resulting output). You can put ^^ in the value part of an -# alias to insert a newline as if a physical newline was in the original file. -# When you need a literal { or } or , in the value part of an alias you have to -# escape them by means of a backslash (\), this can lead to conflicts with the -# commands \{ and \} for these it is advised to use the version @{ and @} or use -# a double escape (\\{ and \\}) +# "Side Effects:". Note that you cannot put \n's in the value part of an alias +# to insert newlines (in the resulting output). You can put ^^ in the value part +# of an alias to insert a newline as if a physical newline was in the original +# file. When you need a literal { or } or , in the value part of an alias you +# have to escape them by means of a backslash (\), this can lead to conflicts +# with the commands \{ and \} for these it is advised to use the version @{ and +# @} or use a double escape (\\{ and \\}) ALIASES = @@ -304,8 +326,8 @@ OPTIMIZE_OUTPUT_SLICE = NO # extension. Doxygen has a built-in mapping, but you can override or extend it # using this tag. The format is ext=language, where ext is a file extension, and # language is one of the parsers supported by doxygen: IDL, Java, JavaScript, -# Csharp (C#), C, C++, D, PHP, md (Markdown), Objective-C, Python, Slice, VHDL, -# Fortran (fixed format Fortran: FortranFixed, free formatted Fortran: +# Csharp (C#), C, C++, Lex, D, PHP, md (Markdown), Objective-C, Python, Slice, +# VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran: # FortranFree, unknown formatted Fortran: Fortran. In the later case the parser # tries to guess whether the code is fixed or free formatted code, this is the # default for Fortran type files). For instance to make doxygen treat .inc files @@ -315,7 +337,10 @@ OPTIMIZE_OUTPUT_SLICE = NO # Note: For files without extension you can use no_extension as a placeholder. # # Note that for custom extensions you also need to set FILE_PATTERNS otherwise -# the files are not read by doxygen. +# the files are not read by doxygen. When specifying no_extension you should add +# * to the FILE_PATTERNS. +# +# Note see also the list of default file extension mappings. EXTENSION_MAPPING = @@ -338,6 +363,17 @@ MARKDOWN_SUPPORT = YES TOC_INCLUDE_HEADINGS = 5 +# The MARKDOWN_ID_STYLE tag can be used to specify the algorithm used to +# generate identifiers for the Markdown headings. Note: Every identifier is +# unique. +# Possible values are: DOXYGEN use a fixed 'autotoc_md' string followed by a +# sequence number starting at 0 and GITHUB use the lower case version of title +# with any whitespace replaced by '-' and punctuation characters removed. +# The default value is: DOXYGEN. +# This tag requires that the tag MARKDOWN_SUPPORT is set to YES. + +MARKDOWN_ID_STYLE = DOXYGEN + # When enabled doxygen tries to link words that correspond to documented # classes, or namespaces to their corresponding documentation. Such a link can # be prevented in individual cases by putting a % sign in front of the word or @@ -449,19 +485,27 @@ TYPEDEF_HIDES_STRUCT = NO LOOKUP_CACHE_SIZE = 0 -# The NUM_PROC_THREADS specifies the number threads doxygen is allowed to use +# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use # during processing. When set to 0 doxygen will based this on the number of # cores available in the system. You can set it explicitly to a value larger # than 0 to get more control over the balance between CPU load and processing # speed. At this moment only the input processing can be done using multiple # threads. Since this is still an experimental feature the default is set to 1, -# which efficively disables parallel processing. Please report any issues you +# which effectively disables parallel processing. Please report any issues you # encounter. Generating dot graphs in parallel is controlled by the # DOT_NUM_THREADS setting. # Minimum value: 0, maximum value: 32, default value: 1. NUM_PROC_THREADS = 8 +# If the TIMESTAMP tag is set different from NO then each generated page will +# contain the date or date and time when the page was generated. Setting this to +# NO can help when comparing the output of multiple runs. +# Possible values are: YES, NO, DATETIME and DATE. +# The default value is: NO. + +TIMESTAMP = NO + #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- @@ -474,7 +518,7 @@ NUM_PROC_THREADS = 8 # normally produced when WARNINGS is set to YES. # The default value is: NO. -EXTRACT_ALL = NO +EXTRACT_ALL = YES # If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will # be included in the documentation. @@ -498,7 +542,7 @@ EXTRACT_PACKAGE = NO # included in the documentation. # The default value is: NO. -EXTRACT_STATIC = YES +EXTRACT_STATIC = NO # If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined # locally in source files will be included in the documentation. If set to NO, @@ -506,7 +550,7 @@ EXTRACT_STATIC = YES # for Java sources. # The default value is: YES. -EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_CLASSES = NO # This flag is only useful for Objective-C code. If set to YES, local methods, # which are defined in the implementation section but not in the interface are @@ -525,6 +569,13 @@ EXTRACT_LOCAL_METHODS = NO EXTRACT_ANON_NSPACES = NO +# If this flag is set to YES, the name of an unnamed parameter in a declaration +# will be determined by the corresponding definition. By default unnamed +# parameters remain unnamed in the output. +# The default value is: YES. + +RESOLVE_UNNAMED_PARAMS = YES + # If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all # undocumented members inside documented classes or files. If set to NO these # members will be included in the various overviews, but no documentation @@ -536,7 +587,8 @@ HIDE_UNDOC_MEMBERS = NO # If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. If set # to NO, these classes will be included in the various overviews. This option -# has no effect if EXTRACT_ALL is enabled. +# will also hide undocumented C++ concepts if enabled. This option has no effect +# if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_CLASSES = NO @@ -553,7 +605,7 @@ HIDE_FRIEND_COMPOUNDS = YES # blocks will be appended to the function's detailed documentation block. # The default value is: NO. -HIDE_IN_BODY_DOCS = NO +HIDE_IN_BODY_DOCS = YES # The INTERNAL_DOCS tag determines if documentation that is typed after a # \internal command is included. If the tag is set to NO then the documentation @@ -562,14 +614,22 @@ HIDE_IN_BODY_DOCS = NO INTERNAL_DOCS = NO -# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file -# names in lower-case letters. If set to YES, upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# (including Cygwin) and Mac users are advised to set this option to NO. -# The default value is: system dependent. - -CASE_SENSE_NAMES = YES +# With the correct setting of option CASE_SENSE_NAMES doxygen will better be +# able to match the capabilities of the underlying filesystem. In case the +# filesystem is case sensitive (i.e. it supports files in the same directory +# whose names only differ in casing), the option must be set to YES to properly +# deal with such files in case they appear in the input. For filesystems that +# are not case sensitive the option should be set to NO to properly deal with +# output files written for symbols that only differ in casing, such as for two +# classes, one named CLASS and the other named Class, and to also support +# references to files without having to specify the exact matching casing. On +# Windows (including Cygwin) and MacOS, users should typically set this option +# to NO, whereas on Linux or other Unix flavors it should typically be set to +# YES. +# Possible values are: SYSTEM, NO and YES. +# The default value is: SYSTEM. + +CASE_SENSE_NAMES = SYSTEM # If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with # their full class and namespace scopes in the documentation. If set to YES, the @@ -748,7 +808,8 @@ FILE_VERSION_FILTER = # output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. You can # optionally specify a file name after the option, if omitted DoxygenLayout.xml -# will be used as the name of the layout file. +# will be used as the name of the layout file. See also section "Changing the +# layout of pages" for information. # # Note that if you run doxygen from a directory containing a file called # DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE @@ -775,7 +836,7 @@ CITE_BIB_FILES = # messages are off. # The default value is: NO. -QUIET = NO +QUIET = YES # The WARNINGS tag can be used to turn on/off the warning messages that are # generated to standard error (stderr) by doxygen. If WARNINGS is set to YES @@ -794,24 +855,50 @@ WARNINGS = YES WARN_IF_UNDOCUMENTED = NO # If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some parameters -# in a documented function, or documenting parameters that don't exist or using -# markup commands wrongly. +# potential errors in the documentation, such as documenting some parameters in +# a documented function twice, or documenting parameters that don't exist or +# using markup commands wrongly. # The default value is: YES. WARN_IF_DOC_ERROR = YES +# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete +# function parameter documentation. If set to NO, doxygen will accept that some +# parameters have no documentation without warning. +# The default value is: YES. + +WARN_IF_INCOMPLETE_DOC = YES + # This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that # are documented, but have no documentation for their parameters or return -# value. If set to NO, doxygen will only warn about wrong or incomplete -# parameter documentation, but not about the absence of documentation. If -# EXTRACT_ALL is set to YES then this flag will automatically be disabled. +# value. If set to NO, doxygen will only warn about wrong parameter +# documentation, but not about the absence of documentation. If EXTRACT_ALL is +# set to YES then this flag will automatically be disabled. See also +# WARN_IF_INCOMPLETE_DOC # The default value is: NO. WARN_NO_PARAMDOC = NO +# If WARN_IF_UNDOC_ENUM_VAL option is set to YES, doxygen will warn about +# undocumented enumeration values. If set to NO, doxygen will accept +# undocumented enumeration values. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: NO. + +WARN_IF_UNDOC_ENUM_VAL = NO + # If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when -# a warning is encountered. +# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS +# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but +# at the end of the doxygen process doxygen will return with a non-zero status. +# If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS_PRINT then doxygen behaves +# like FAIL_ON_WARNINGS but in case no WARN_LOGFILE is defined doxygen will not +# write the warning messages in between other messages but write them at the end +# of a run, in case a WARN_LOGFILE is defined the warning messages will be +# besides being in the defined file also be shown at the end of a run, unless +# the WARN_LOGFILE is defined as - i.e. standard output (stdout) in that case +# the behavior will remain as with the setting FAIL_ON_WARNINGS. +# Possible values are: NO, YES, FAIL_ON_WARNINGS and FAIL_ON_WARNINGS_PRINT. # The default value is: NO. WARN_AS_ERROR = NO @@ -822,13 +909,27 @@ WARN_AS_ERROR = NO # and the warning text. Optionally the format may contain $version, which will # be replaced by the version of the file (if it could be obtained via # FILE_VERSION_FILTER) +# See also: WARN_LINE_FORMAT # The default value is: $file:$line: $text. WARN_FORMAT = "$file:$line: $text" +# In the $text part of the WARN_FORMAT command it is possible that a reference +# to a more specific place is given. To make it easier to jump to this place +# (outside of doxygen) the user can define a custom "cut" / "paste" string. +# Example: +# WARN_LINE_FORMAT = "'vi $file +$line'" +# See also: WARN_FORMAT +# The default value is: at line $line of file $file. + +WARN_LINE_FORMAT = "at line $line of file $file" + # The WARN_LOGFILE tag can be used to specify a file to which warning and error # messages should be written. If left blank the output is written to standard -# error (stderr). +# error (stderr). In case the file specified cannot be opened for writing the +# warning and error messages are written to standard error. When as file - is +# specified the warning and error messages are written to standard output +# (stdout). WARN_LOGFILE = $(LIEF_DOXYGEN_WARN_FILE) @@ -847,12 +948,23 @@ INPUT = $(LIEF_INPUT) # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses # libiconv (or the iconv built into libc) for the transcoding. See the libiconv -# documentation (see: https://www.gnu.org/software/libiconv/) for the list of -# possible encodings. +# documentation (see: +# https://www.gnu.org/software/libiconv/) for the list of possible encodings. +# See also: INPUT_FILE_ENCODING # The default value is: UTF-8. INPUT_ENCODING = UTF-8 +# This tag can be used to specify the character encoding of the source files +# that doxygen parses The INPUT_FILE_ENCODING tag can be used to specify +# character encoding on a per file pattern basis. Doxygen will compare the file +# name with each pattern and apply the encoding instead of the default +# INPUT_ENCODING) if there is a match. The character encodings are a list of the +# form: pattern=encoding (like *.php=ISO-8859-1). See cfg_input_encoding +# "INPUT_ENCODING" for further information on supported encodings. + +INPUT_FILE_ENCODING = + # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and # *.h) to filter out the source-files in the directories. @@ -861,19 +973,24 @@ INPUT_ENCODING = UTF-8 # need to set EXTENSION_MAPPING for the extension otherwise the files are not # read by doxygen. # -# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, -# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, -# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, -# *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C comment), -# *.doc (to be provided as doxygen C comment), *.txt (to be provided as doxygen -# C comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd, -# *.vhdl, *.ucf, *.qsf and *.ice. +# Note the list of default checked file patterns might differ from the list of +# default file extension mappings. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cxxm, +# *.cpp, *.cppm, *.c++, *.c++m, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, +# *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp, *.h++, *.ixx, *.l, *.cs, *.d, *.php, +# *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be +# provided as doxygen C comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, +# *.f18, *.f, *.for, *.vhd, *.vhdl, *.ucf, *.qsf and *.ice. FILE_PATTERNS = *.c \ *.cc \ *.cxx \ + *.cxxm \ *.cpp \ + *.cppm \ *.c++ \ + *.c++m \ *.java \ *.ii \ *.ixx \ @@ -889,6 +1006,8 @@ FILE_PATTERNS = *.c \ *.hxx \ *.hpp \ *.h++ \ + *.ixx \ + *.l \ *.cs \ *.d \ *.php \ @@ -901,16 +1020,16 @@ FILE_PATTERNS = *.c \ *.md \ *.mm \ *.dox \ - *.doc \ - *.txt \ *.py \ *.pyw \ - *.tcc \ *.f90 \ *.f95 \ *.f03 \ *.f08 \ *.f18 \ + *.tcc \ + *.doc \ + *.txt \ *.f \ *.for \ *.vhd \ @@ -954,10 +1073,7 @@ EXCLUDE_PATTERNS = # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test -# -# Note that the wildcards are matched against the file with absolute path, so to -# exclude all test directories use the pattern */test/* +# ANamespace::AClass, ANamespace::*Test EXCLUDE_SYMBOLS = @@ -1002,6 +1118,11 @@ IMAGE_PATH = # code is scanned, but not when the output code is generated. If lines are added # or removed, the anchors will not be placed correctly. # +# Note that doxygen will use the data processed and written to standard output +# for further processing, therefore nothing else, like debug statements or used +# commands (so in case of a Windows batch file always use @echo OFF), should be +# written to standard output. +# # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. @@ -1043,6 +1164,15 @@ FILTER_SOURCE_PATTERNS = USE_MDFILE_AS_MAINPAGE = doxygen_index.md +# The Fortran standard specifies that for fixed formatted Fortran code all +# characters from position 72 are to be considered as comment. A common +# extension is to allow longer lines before the automatic comment starts. The +# setting FORTRAN_COMMENT_AFTER will also make it possible that longer lines can +# be processed before the automatic comment starts. +# Minimum value: 7, maximum value: 10000, default value: 72. + +FORTRAN_COMMENT_AFTER = 72 + #--------------------------------------------------------------------------- # Configuration options related to source browsing #--------------------------------------------------------------------------- @@ -1073,13 +1203,13 @@ STRIP_CODE_COMMENTS = YES # entity all documented functions referencing it will be listed. # The default value is: NO. -REFERENCED_BY_RELATION = NO +REFERENCED_BY_RELATION = YES # If the REFERENCES_RELATION tag is set to YES then for each documented function # all documented entities called/used by that function will be listed. # The default value is: NO. -REFERENCES_RELATION = NO +REFERENCES_RELATION = YES # If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set # to YES then the hyperlinks from functions in REFERENCES_RELATION and @@ -1140,10 +1270,11 @@ VERBATIM_HEADERS = YES ALPHABETICAL_INDEX = YES -# In case all classes in a project start with a common prefix, all classes will -# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag -# can be used to specify a prefix (or a list of prefixes) that should be ignored -# while generating the index headers. +# The IGNORE_PREFIX tag can be used to specify a prefix (or a list of prefixes) +# that should be ignored while generating the index headers. The IGNORE_PREFIX +# tag works for classes, function and member names. The entity will be placed in +# the alphabetical list under the first letter of the entity name that remains +# after removing the prefix. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. IGNORE_PREFIX = @@ -1222,7 +1353,12 @@ HTML_STYLESHEET = # Doxygen will copy the style sheet files to the output directory. # Note: The order of the extra style sheet files is of importance (e.g. the last # style sheet in the list overrules the setting of the previous ones in the -# list). For an example see the documentation. +# list). +# Note: Since the styling of scrollbars can currently not be overruled in +# Webkit/Chromium, the styling will be left out of the default doxygen.css if +# one or more extra stylesheets have been specified. So if scrollbar +# customization is desired it has to be added explicitly. For an example see the +# documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_STYLESHEET = @@ -1237,9 +1373,22 @@ HTML_EXTRA_STYLESHEET = HTML_EXTRA_FILES = +# The HTML_COLORSTYLE tag can be used to specify if the generated HTML output +# should be rendered with a dark or light theme. +# Possible values are: LIGHT always generate light mode output, DARK always +# generate dark mode output, AUTO_LIGHT automatically set the mode according to +# the user preference, use light mode if no preference is set (the default), +# AUTO_DARK automatically set the mode according to the user preference, use +# dark mode if no preference is set and TOGGLE allow to user to switch between +# light and dark mode via a button. +# The default value is: AUTO_LIGHT. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE = AUTO_LIGHT + # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen # will adjust the colors in the style sheet and background images according to -# this color. Hue is specified as an angle on a colorwheel, see +# this color. Hue is specified as an angle on a color-wheel, see # https://en.wikipedia.org/wiki/Hue for more information. For instance the value # 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 # purple, and 360 is red again. @@ -1249,7 +1398,7 @@ HTML_EXTRA_FILES = HTML_COLORSTYLE_HUE = 220 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors -# in the HTML output. For a value of 0 the output will use grayscales only. A +# in the HTML output. For a value of 0 the output will use gray-scales only. A # value of 255 will produce the most vivid colors. # Minimum value: 0, maximum value: 255, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. @@ -1267,15 +1416,6 @@ HTML_COLORSTYLE_SAT = 100 HTML_COLORSTYLE_GAMMA = 80 -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting this -# to YES can help to show when doxygen was last run and thus if the -# documentation is up to date. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_TIMESTAMP = NO - # If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML # documentation will contain a main index with vertical navigation menus that # are dynamically created via JavaScript. If disabled, the navigation index will @@ -1295,6 +1435,13 @@ HTML_DYNAMIC_MENUS = YES HTML_DYNAMIC_SECTIONS = NO +# If the HTML_CODE_FOLDING tag is set to YES then classes and functions can be +# dynamically folded and expanded in the generated HTML source code. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_CODE_FOLDING = YES + # With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries # shown in the various tree structured indices initially; the user can expand # and collapse entries dynamically later on. Doxygen will expand the tree to @@ -1310,10 +1457,11 @@ HTML_INDEX_NUM_ENTRIES = 100 # If the GENERATE_DOCSET tag is set to YES, additional index files will be # generated that can be used as input for Apple's Xcode 3 integrated development -# environment (see: https://developer.apple.com/xcode/), introduced with OSX -# 10.5 (Leopard). To create a documentation set, doxygen will generate a -# Makefile in the HTML output directory. Running make will produce the docset in -# that directory and running make install will install the docset in +# environment (see: +# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To +# create a documentation set, doxygen will generate a Makefile in the HTML +# output directory. Running make will produce the docset in that directory and +# running make install will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at # startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy # genXcode/_index.html for more information. @@ -1330,6 +1478,13 @@ GENERATE_DOCSET = NO DOCSET_FEEDNAME = "Doxygen generated docs" +# This tag determines the URL of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDURL = + # This tag specifies a string that should uniquely identify the documentation # set bundle. This should be a reverse domain-name style string, e.g. # com.mycompany.MyDocSet. Doxygen will append .docset to the name. @@ -1355,8 +1510,12 @@ DOCSET_PUBLISHER_NAME = Publisher # If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three # additional HTML index files: index.hhp, index.hhc, and index.hhk. The # index.hhp is a project file that can be read by Microsoft's HTML Help Workshop -# (see: https://www.microsoft.com/en-us/download/details.aspx?id=21138) on -# Windows. +# on Windows. In the beginning of 2021 Microsoft took the original page, with +# a.o. the download links, offline the HTML help workshop was already many years +# in maintenance mode). You can download the HTML help workshop from the web +# archives at Installation executable (see: +# http://web.archive.org/web/20160201063255/http://download.microsoft.com/downlo +# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe). # # The HTML Help Workshop contains a compiler that can convert all HTML output # generated by doxygen into a single compiled HTML file (.chm). Compiled HTML @@ -1413,6 +1572,16 @@ BINARY_TOC = NO TOC_EXPAND = NO +# The SITEMAP_URL tag is used to specify the full URL of the place where the +# generated documentation will be placed on the server by the user during the +# deployment of the documentation. The generated sitemap is called sitemap.xml +# and placed on the directory specified by HTML_OUTPUT. In case no SITEMAP_URL +# is specified no sitemap is generated. For information about the sitemap +# protocol see https://www.sitemaps.org +# This tag requires that the tag GENERATE_HTML is set to YES. + +SITEMAP_URL = + # If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and # QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that # can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help @@ -1431,16 +1600,17 @@ QCH_FILE = lief.qch # The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help # Project output. For more information please see Qt Help Project / Namespace -# (see: https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace). +# (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace). # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_QHP is set to YES. -QHP_NAMESPACE = org.lief +QHP_NAMESPACE = re.lief # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt # Help Project output. For more information please see Qt Help Project / Virtual -# Folders (see: https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual- -# folders). +# Folders (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual-folders). # The default value is: doc. # This tag requires that the tag GENERATE_QHP is set to YES. @@ -1448,16 +1618,16 @@ QHP_VIRTUAL_FOLDER = liefdoc # If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom # filter to add. For more information please see Qt Help Project / Custom -# Filters (see: https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom- -# filters). +# Filters (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_NAME = # The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the # custom filter to add. For more information please see Qt Help Project / Custom -# Filters (see: https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom- -# filters). +# Filters (see: +# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_ATTRS = @@ -1469,9 +1639,9 @@ QHP_CUST_FILTER_ATTRS = QHP_SECT_FILTER_ATTRS = -# The QHG_LOCATION tag can be used to specify the location of Qt's -# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the -# generated .qhp file. +# The QHG_LOCATION tag can be used to specify the location (absolute path +# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to +# run qhelpgenerator on the generated .qhp file. # This tag requires that the tag GENERATE_QHP is set to YES. QHG_LOCATION = @@ -1514,16 +1684,28 @@ DISABLE_INDEX = NO # to work a browser that supports JavaScript, DHTML, CSS and frames is required # (i.e. any modern browser). Windows users are probably better off using the # HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can -# further fine-tune the look of the index. As an example, the default style -# sheet generated by doxygen has an example that shows how to put an image at -# the root of the tree instead of the PROJECT_NAME. Since the tree basically has -# the same information as the tab index, you could consider setting -# DISABLE_INDEX to YES when enabling this option. +# further fine tune the look of the index (see "Fine-tuning the output"). As an +# example, the default style sheet generated by doxygen has an example that +# shows how to put an image at the root of the tree instead of the PROJECT_NAME. +# Since the tree basically has the same information as the tab index, you could +# consider setting DISABLE_INDEX to YES when enabling this option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_TREEVIEW = NO +# When both GENERATE_TREEVIEW and DISABLE_INDEX are set to YES, then the +# FULL_SIDEBAR option determines if the side bar is limited to only the treeview +# area (value NO) or if it should extend to the full height of the window (value +# YES). Setting this to YES gives a layout similar to +# https://docs.readthedocs.io with more room for contents, but less room for the +# project logo, title, and description. If either GENERATE_TREEVIEW or +# DISABLE_INDEX is set to NO, this option has no effect. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FULL_SIDEBAR = NO + # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that # doxygen will group on one line in the generated HTML documentation. # @@ -1548,6 +1730,13 @@ TREEVIEW_WIDTH = 250 EXT_LINKS_IN_WINDOW = NO +# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email +# addresses. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +OBFUSCATE_EMAILS = YES + # If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg # tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see # https://inkscape.org) to generate formulas as SVG images instead of PNGs for @@ -1568,17 +1757,6 @@ HTML_FORMULA_FORMAT = png FORMULA_FONTSIZE = 10 -# Use the FORMULA_TRANSPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are not -# supported properly for IE 6.0, but are supported on all modern browsers. -# -# Note that when changing this option you need to delete any form_*.png files in -# the HTML output directory before the changes have effect. -# The default value is: YES. -# This tag requires that the tag GENERATE_HTML is set to YES. - -FORMULA_TRANSPARENT = YES - # The FORMULA_MACROFILE can contain LaTeX \newcommand and \renewcommand commands # to create new LaTeX commands to be used in formulas as building blocks. See # the section "Including formulas" for details. @@ -1596,11 +1774,29 @@ FORMULA_MACROFILE = USE_MATHJAX = NO +# With MATHJAX_VERSION it is possible to specify the MathJax version to be used. +# Note that the different versions of MathJax have different requirements with +# regards to the different settings, so it is possible that also other MathJax +# settings have to be changed when switching between the different MathJax +# versions. +# Possible values are: MathJax_2 and MathJax_3. +# The default value is: MathJax_2. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_VERSION = MathJax_2 + # When MathJax is enabled you can set the default output format to be used for -# the MathJax output. See the MathJax site (see: -# http://docs.mathjax.org/en/latest/output.html) for more details. +# the MathJax output. For more details about the output format see MathJax +# version 2 (see: +# http://docs.mathjax.org/en/v2.7-latest/output.html) and MathJax version 3 +# (see: +# http://docs.mathjax.org/en/latest/web/components/output.html). # Possible values are: HTML-CSS (which is slower, but has the best -# compatibility), NativeMML (i.e. MathML) and SVG. +# compatibility. This is the name for Mathjax version 2, for MathJax version 3 +# this will be translated into chtml), NativeMML (i.e. MathML. Only supported +# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This +# is the name for Mathjax version 3, for MathJax version 2 this will be +# translated into HTML-CSS) and SVG. # The default value is: HTML-CSS. # This tag requires that the tag USE_MATHJAX is set to YES. @@ -1613,22 +1809,29 @@ MATHJAX_FORMAT = HTML-CSS # MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax # Content Delivery Network so you can quickly see the result without installing # MathJax. However, it is strongly recommended to install a local copy of -# MathJax from https://www.mathjax.org before deployment. -# The default value is: https://cdn.jsdelivr.net/npm/mathjax@2. +# MathJax from https://www.mathjax.org before deployment. The default value is: +# - in case of MathJax version 2: https://cdn.jsdelivr.net/npm/mathjax@2 +# - in case of MathJax version 3: https://cdn.jsdelivr.net/npm/mathjax@3 # This tag requires that the tag USE_MATHJAX is set to YES. -MATHJAX_RELPATH = https://cdn.jsdelivr.net/npm/mathjax@2 +MATHJAX_RELPATH = # The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax # extension names that should be enabled during MathJax rendering. For example +# for MathJax version 2 (see +# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions): # MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# For example for MathJax version 3 (see +# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html): +# MATHJAX_EXTENSIONS = ams # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_EXTENSIONS = # The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces # of code that will be used on startup of the MathJax code. See the MathJax site -# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# (see: +# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an # example see the documentation. # This tag requires that the tag USE_MATHJAX is set to YES. @@ -1675,7 +1878,8 @@ SERVER_BASED_SEARCH = NO # # Doxygen ships with an example indexer (doxyindexer) and search engine # (doxysearch.cgi) which are based on the open source search engine library -# Xapian (see: https://xapian.org/). +# Xapian (see: +# https://xapian.org/). # # See the section "External Indexing and Searching" for details. # The default value is: NO. @@ -1688,8 +1892,9 @@ EXTERNAL_SEARCH = NO # # Doxygen ships with an example indexer (doxyindexer) and search engine # (doxysearch.cgi) which are based on the open source search engine library -# Xapian (see: https://xapian.org/). See the section "External Indexing and -# Searching" for details. +# Xapian (see: +# https://xapian.org/). See the section "External Indexing and Searching" for +# details. # This tag requires that the tag SEARCHENGINE is set to YES. SEARCHENGINE_URL = @@ -1798,29 +2003,31 @@ PAPER_TYPE = a4 EXTRA_PACKAGES = -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the -# generated LaTeX document. The header should contain everything until the first -# chapter. If it is left blank doxygen will generate a standard header. See -# section "Doxygen usage" for information on how to let doxygen write the -# default header to a separate file. +# The LATEX_HEADER tag can be used to specify a user-defined LaTeX header for +# the generated LaTeX document. The header should contain everything until the +# first chapter. If it is left blank doxygen will generate a standard header. It +# is highly recommended to start with a default header using +# doxygen -w latex new_header.tex new_footer.tex new_stylesheet.sty +# and then modify the file new_header.tex. See also section "Doxygen usage" for +# information on how to generate the default header that doxygen normally uses. # -# Note: Only use a user-defined header if you know what you are doing! The -# following commands have a special meaning inside the header: $title, -# $datetime, $date, $doxygenversion, $projectname, $projectnumber, -# $projectbrief, $projectlogo. Doxygen will replace $title with the empty -# string, for the replacement values of the other commands the user is referred -# to HTML_HEADER. +# Note: Only use a user-defined header if you know what you are doing! +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. The following +# commands have a special meaning inside the header (and footer): For a +# description of the possible markers and block names see the documentation. # This tag requires that the tag GENERATE_LATEX is set to YES. LATEX_HEADER = -# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the -# generated LaTeX document. The footer should contain everything after the last -# chapter. If it is left blank doxygen will generate a standard footer. See +# The LATEX_FOOTER tag can be used to specify a user-defined LaTeX footer for +# the generated LaTeX document. The footer should contain everything after the +# last chapter. If it is left blank doxygen will generate a standard footer. See # LATEX_HEADER for more information on how to generate a default footer and what -# special commands can be used inside the footer. -# -# Note: Only use a user-defined footer if you know what you are doing! +# special commands can be used inside the footer. See also section "Doxygen +# usage" for information on how to generate the default footer that doxygen +# normally uses. Note: Only use a user-defined footer if you know what you are +# doing! # This tag requires that the tag GENERATE_LATEX is set to YES. LATEX_FOOTER = @@ -1863,10 +2070,16 @@ PDF_HYPERLINKS = YES USE_PDFLATEX = YES -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode -# command to the generated LaTeX files. This will instruct LaTeX to keep running -# if errors occur, instead of asking the user for help. This option is also used -# when generating formulas in HTML. +# The LATEX_BATCHMODE tag signals the behavior of LaTeX in case of an error. +# Possible values are: NO same as ERROR_STOP, YES same as BATCH, BATCH In batch +# mode nothing is printed on the terminal, errors are scrolled as if is +# hit at every error; missing files that TeX tries to input or request from +# keyboard input (\read on a not open input stream) cause the job to abort, +# NON_STOP In nonstop mode the diagnostic message will appear on the terminal, +# but there is no possibility of user interaction just like in batch mode, +# SCROLL In scroll mode, TeX will stop only for missing files to input or if +# keyboard input is necessary and ERROR_STOP In errorstop mode, TeX will stop at +# each error, asking for user intervention. # The default value is: NO. # This tag requires that the tag GENERATE_LATEX is set to YES. @@ -1879,7 +2092,6 @@ LATEX_BATCHMODE = NO LATEX_HIDE_INDICES = NO - # The LATEX_BIB_STYLE tag can be used to specify the style to use for the # bibliography, e.g. plainnat, or ieeetr. See # https://en.wikipedia.org/wiki/BibTeX and \cite for more info. @@ -1888,14 +2100,6 @@ LATEX_HIDE_INDICES = NO LATEX_BIB_STYLE = plain -# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated -# page will contain the date and time when the page was generated. Setting this -# to NO can help when comparing the output of multiple runs. -# The default value is: NO. -# This tag requires that the tag GENERATE_LATEX is set to YES. - -LATEX_TIMESTAMP = NO - # The LATEX_EMOJI_DIRECTORY tag is used to specify the (relative or absolute) # path from which the emoji images will be read. If a relative path is entered, # it will be relative to the LATEX_OUTPUT directory. If left blank the @@ -2012,7 +2216,7 @@ MAN_LINKS = NO # captures the structure of the code including all documentation. # The default value is: NO. -GENERATE_XML = YES # Used by breathe +GENERATE_XML = YES # The XML_OUTPUT tag is used to specify where the XML pages will be put. If a # relative path is entered the value of OUTPUT_DIRECTORY will be put in front of @@ -2061,13 +2265,39 @@ DOCBOOK_OUTPUT = docbook #--------------------------------------------------------------------------- # If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an -# AutoGen Definitions (see http://autogen.sourceforge.net/) file that captures +# AutoGen Definitions (see https://autogen.sourceforge.net/) file that captures # the structure of the code including all documentation. Note that this feature # is still experimental and incomplete at the moment. # The default value is: NO. GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# Configuration options related to Sqlite3 output +#--------------------------------------------------------------------------- + +# If the GENERATE_SQLITE3 tag is set to YES doxygen will generate a Sqlite3 +# database with symbols found by doxygen stored in tables. +# The default value is: NO. + +GENERATE_SQLITE3 = NO + +# The SQLITE3_OUTPUT tag is used to specify where the Sqlite3 database will be +# put. If a relative path is entered the value of OUTPUT_DIRECTORY will be put +# in front of it. +# The default directory is: sqlite3. +# This tag requires that the tag GENERATE_SQLITE3 is set to YES. + +SQLITE3_OUTPUT = sqlite3 + +# The SQLITE3_OVERWRITE_DB tag is set to YES, the existing doxygen_sqlite3.db +# database file will be recreated with each doxygen run. If set to NO, doxygen +# will warn if an a database file is already found and not modify it. +# The default value is: YES. +# This tag requires that the tag GENERATE_SQLITE3 is set to YES. + +SQLITE3_RECREATE_DB = YES + #--------------------------------------------------------------------------- # Configuration options related to the Perl module output #--------------------------------------------------------------------------- @@ -2142,7 +2372,8 @@ SEARCH_INCLUDES = YES # The INCLUDE_PATH tag can be used to specify one or more directories that # contain include files that are not input files but should be processed by the -# preprocessor. +# preprocessor. Note that the INCLUDE_PATH is not recursive, so the setting of +# RECURSIVE has no effect here. # This tag requires that the tag SEARCH_INCLUDES is set to YES. INCLUDE_PATH = $(LIEF_INCLUDE_PATH) @@ -2187,6 +2418,7 @@ PREDEFINED = \ # definition found in the source code. # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. + EXPAND_AS_DEFINED = _LIEF_EI EXPAND_AS_DEFINED += _LIEF_EN EXPAND_AS_DEFINED += _LIEF_EN_2 @@ -2206,6 +2438,9 @@ EXPAND_AS_DEFINED += LIEF_VDEX_VISITABLE EXPAND_AS_DEFINED += LIEF_VDEX_FORWARD EXPAND_AS_DEFINED += LIEF_ART_VISITABLE EXPAND_AS_DEFINED += LIEF_ART_FORWARD +EXPAND_AS_DEFINED += ELF_RELOC +EXPAND_AS_DEFINED += FUNCTION_VARIANT_FLAG + # If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will # remove all references to function-like macros that are alone on a line, have @@ -2242,15 +2477,15 @@ TAGFILES = GENERATE_TAGFILE = -# If the ALLEXTERNALS tag is set to YES, all external class will be listed in -# the class index. If set to NO, only the inherited external classes will be -# listed. +# If the ALLEXTERNALS tag is set to YES, all external classes and namespaces +# will be listed in the class and namespace index. If set to NO, only the +# inherited external classes will be listed. # The default value is: NO. ALLEXTERNALS = NO # If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will be +# in the topic index. If set to NO, only the current project's groups will be # listed. # The default value is: YES. @@ -2264,16 +2499,9 @@ EXTERNAL_GROUPS = YES EXTERNAL_PAGES = YES #--------------------------------------------------------------------------- -# Configuration options related to the dot tool +# Configuration options related to diagram generator tools #--------------------------------------------------------------------------- -# You can include diagrams made with dia in doxygen documentation. Doxygen will -# then run dia to produce the diagram and insert it in the documentation. The -# DIA_PATH tag allows you to specify the directory where the dia binary resides. -# If left empty dia is assumed to be found in the default search path. - -DIA_PATH = - # If set to YES the inheritance and collaboration graphs will hide inheritance # and usage relations if the target is undocumented or is not a class. # The default value is: YES. @@ -2282,7 +2510,7 @@ HIDE_UNDOC_RELATIONS = YES # If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is # available from the path. This tool is part of Graphviz (see: -# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent +# https://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent # Bell Labs. The other options in this section have no effect if this option is # set to NO # The default value is: NO. @@ -2299,37 +2527,51 @@ HAVE_DOT = YES DOT_NUM_THREADS = 0 -# When you want a differently looking font in the dot files that doxygen -# generates you can specify the font name using DOT_FONTNAME. You need to make -# sure dot is able to find the font, which can be done by putting it in a -# standard location or by setting the DOTFONTPATH environment variable or by -# setting DOT_FONTPATH to the directory containing the font. -# The default value is: Helvetica. +# DOT_COMMON_ATTR is common attributes for nodes, edges and labels of +# subgraphs. When you want a differently looking font in the dot files that +# doxygen generates you can specify fontname, fontcolor and fontsize attributes. +# For details please see Node, +# Edge and Graph Attributes specification You need to make sure dot is able +# to find the font, which can be done by putting it in a standard location or by +# setting the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. Default graphviz fontsize is 14. +# The default value is: fontname=Helvetica,fontsize=10. # This tag requires that the tag HAVE_DOT is set to YES. -DOT_FONTNAME = Helvetica +DOT_COMMON_ATTR = "fontname=Helvetica,fontsize=10" -# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of -# dot graphs. -# Minimum value: 4, maximum value: 24, default value: 10. +# DOT_EDGE_ATTR is concatenated with DOT_COMMON_ATTR. For elegant style you can +# add 'arrowhead=open, arrowtail=open, arrowsize=0.5'. Complete documentation about +# arrows shapes. +# The default value is: labelfontname=Helvetica,labelfontsize=10. # This tag requires that the tag HAVE_DOT is set to YES. -DOT_FONTSIZE = 10 +DOT_EDGE_ATTR = "labelfontname=Helvetica,labelfontsize=10" -# By default doxygen will tell dot to use the default font as specified with -# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set -# the path where dot can find it using this tag. +# DOT_NODE_ATTR is concatenated with DOT_COMMON_ATTR. For view without boxes +# around nodes set 'shape=plain' or 'shape=plaintext' Shapes specification +# The default value is: shape=box,height=0.2,width=0.4. +# This tag requires that the tag HAVE_DOT is set to YES. + +DOT_NODE_ATTR = "shape=box,height=0.2,width=0.4" + +# You can set the path where dot can find font specified with fontname in +# DOT_COMMON_ATTR and others dot attributes. # This tag requires that the tag HAVE_DOT is set to YES. DOT_FONTPATH = -# If the CLASS_GRAPH tag is set to YES (or GRAPH) then doxygen will generate a -# graph for each documented class showing the direct and indirect inheritance -# relations. In case HAVE_DOT is set as well dot will be used to draw the graph, -# otherwise the built-in generator will be used. If the CLASS_GRAPH tag is set -# to TEXT the direct and indirect inheritance relations will be shown as texts / -# links. -# Possible values are: NO, YES, TEXT and GRAPH. +# If the CLASS_GRAPH tag is set to YES or GRAPH or BUILTIN then doxygen will +# generate a graph for each documented class showing the direct and indirect +# inheritance relations. In case the CLASS_GRAPH tag is set to YES or GRAPH and +# HAVE_DOT is enabled as well, then dot will be used to draw the graph. In case +# the CLASS_GRAPH tag is set to YES and HAVE_DOT is disabled or if the +# CLASS_GRAPH tag is set to BUILTIN, then the built-in generator will be used. +# If the CLASS_GRAPH tag is set to TEXT the direct and indirect inheritance +# relations will be shown as texts / links. +# Possible values are: NO, YES, TEXT, GRAPH and BUILTIN. # The default value is: YES. CLASS_GRAPH = GRAPH @@ -2337,14 +2579,21 @@ CLASS_GRAPH = GRAPH # If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a # graph for each documented class showing the direct and indirect implementation # dependencies (inheritance, containment, and class references variables) of the -# class with other documented classes. +# class with other documented classes. Explicit enabling a collaboration graph, +# when COLLABORATION_GRAPH is set to NO, can be accomplished by means of the +# command \collaborationgraph. Disabling a collaboration graph can be +# accomplished by means of the command \hidecollaborationgraph. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. COLLABORATION_GRAPH = YES # If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for -# groups, showing the direct groups dependencies. +# groups, showing the direct groups dependencies. Explicit enabling a group +# dependency graph, when GROUP_GRAPHS is set to NO, can be accomplished by means +# of the command \groupgraph. Disabling a directory graph can be accomplished by +# means of the command \hidegroupgraph. See also the chapter Grouping in the +# manual. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. @@ -2367,10 +2616,32 @@ UML_LOOK = NO # but if the number exceeds 15, the total amount of fields shown is limited to # 10. # Minimum value: 0, maximum value: 100, default value: 10. -# This tag requires that the tag HAVE_DOT is set to YES. +# This tag requires that the tag UML_LOOK is set to YES. UML_LIMIT_NUM_FIELDS = 10 +# If the DOT_UML_DETAILS tag is set to NO, doxygen will show attributes and +# methods without types and arguments in the UML graphs. If the DOT_UML_DETAILS +# tag is set to YES, doxygen will add type and arguments for attributes and +# methods in the UML graphs. If the DOT_UML_DETAILS tag is set to NONE, doxygen +# will not generate fields with class member information in the UML graphs. The +# class diagrams will look similar to the default class diagrams but using UML +# notation for the relationships. +# Possible values are: NO, YES and NONE. +# The default value is: NO. +# This tag requires that the tag UML_LOOK is set to YES. + +DOT_UML_DETAILS = NO + +# The DOT_WRAP_THRESHOLD tag can be used to set the maximum number of characters +# to display on a single line. If the actual line length exceeds this threshold +# significantly it will wrapped across multiple lines. Some heuristics are apply +# to avoid ugly line breaks. +# Minimum value: 0, maximum value: 1000, default value: 17. +# This tag requires that the tag HAVE_DOT is set to YES. + +DOT_WRAP_THRESHOLD = 17 + # If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and # collaboration graphs will show the relations between templates and their # instances. @@ -2382,7 +2653,9 @@ TEMPLATE_RELATIONS = NO # If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to # YES then doxygen will generate a graph for each documented file showing the # direct and indirect include dependencies of the file with other documented -# files. +# files. Explicit enabling an include graph, when INCLUDE_GRAPH is is set to NO, +# can be accomplished by means of the command \includegraph. Disabling an +# include graph can be accomplished by means of the command \hideincludegraph. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. @@ -2391,7 +2664,10 @@ INCLUDE_GRAPH = YES # If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are # set to YES then doxygen will generate a graph for each documented file showing # the direct and indirect include dependencies of the file with other documented -# files. +# files. Explicit enabling an included by graph, when INCLUDED_BY_GRAPH is set +# to NO, can be accomplished by means of the command \includedbygraph. Disabling +# an included by graph can be accomplished by means of the command +# \hideincludedbygraph. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. @@ -2431,16 +2707,26 @@ GRAPHICAL_HIERARCHY = YES # If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the # dependencies a directory has on other directories in a graphical way. The # dependency relations are determined by the #include relations between the -# files in the directories. +# files in the directories. Explicit enabling a directory graph, when +# DIRECTORY_GRAPH is set to NO, can be accomplished by means of the command +# \directorygraph. Disabling a directory graph can be accomplished by means of +# the command \hidedirectorygraph. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. DIRECTORY_GRAPH = YES +# The DIR_GRAPH_MAX_DEPTH tag can be used to limit the maximum number of levels +# of child directories generated in directory dependency graphs by dot. +# Minimum value: 1, maximum value: 25, default value: 1. +# This tag requires that the tag DIRECTORY_GRAPH is set to YES. + +DIR_GRAPH_MAX_DEPTH = 1 + # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images # generated by dot. For an explanation of the image formats see the section # output formats in the documentation of the dot tool (Graphviz (see: -# http://www.graphviz.org/)). +# https://www.graphviz.org/)). # Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order # to make the SVG files visible in IE 9+ (other browsers do not have this # requirement). @@ -2477,11 +2763,12 @@ DOT_PATH = DOTFILE_DIRS = -# The MSCFILE_DIRS tag can be used to specify one or more directories that -# contain msc files that are included in the documentation (see the \mscfile -# command). +# You can include diagrams made with dia in doxygen documentation. Doxygen will +# then run dia to produce the diagram and insert it in the documentation. The +# DIA_PATH tag allows you to specify the directory where the dia binary resides. +# If left empty dia is assumed to be found in the default search path. -MSCFILE_DIRS = +DIA_PATH = # The DIAFILE_DIRS tag can be used to specify one or more directories that # contain dia files that are included in the documentation (see the \diafile @@ -2490,10 +2777,10 @@ MSCFILE_DIRS = DIAFILE_DIRS = # When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the -# path where java can find the plantuml.jar file. If left blank, it is assumed -# PlantUML is not used or called during a preprocessing step. Doxygen will -# generate a warning when it encounters a \startuml command in this case and -# will not generate output for the diagram. +# path where java can find the plantuml.jar file or to the filename of jar file +# to be used. If left blank, it is assumed PlantUML is not used or called during +# a preprocessing step. Doxygen will generate a warning when it encounters a +# \startuml command in this case and will not generate output for the diagram. PLANTUML_JAR_PATH = @@ -2531,38 +2818,37 @@ DOT_GRAPH_MAX_NODES = 50 MAX_DOT_GRAPH_DEPTH = 0 -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not seem -# to support this out of the box. -# -# Warning: Depending on the platform used, enabling this option may lead to -# badly anti-aliased labels on the edges of a graph (i.e. they become hard to -# read). -# The default value is: NO. -# This tag requires that the tag HAVE_DOT is set to YES. - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) support -# this, this feature is disabled by default. -# The default value is: NO. -# This tag requires that the tag HAVE_DOT is set to YES. - -DOT_MULTI_TARGETS = NO - # If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page # explaining the meaning of the various boxes and arrows in the dot generated # graphs. +# Note: This tag requires that UML_LOOK isn't set, i.e. the doxygen internal +# graphical representation for inheritance and collaboration diagrams is used. # The default value is: YES. # This tag requires that the tag HAVE_DOT is set to YES. GENERATE_LEGEND = YES -# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot +# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate # files that are used to generate the various graphs. +# +# Note: This setting is not only used for dot files but also for msc temporary +# files. # The default value is: YES. -# This tag requires that the tag HAVE_DOT is set to YES. DOT_CLEANUP = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. If the MSCGEN_TOOL tag is left empty (the default), then doxygen will +# use a built-in version of mscgen tool to produce the charts. Alternatively, +# the MSCGEN_TOOL tag can also specify the name an external tool. For instance, +# specifying prog as the value, doxygen will call the tool as prog -T +# -o . The external tool should support +# output file formats "png", "eps", "svg", and "ismap". + +MSCGEN_TOOL = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the \mscfile +# command). + +MSCFILE_DIRS = diff --git a/vendor/lief/doc/doxygen/doxygen_index.md b/vendor/lief/doc/doxygen/doxygen_index.md index 668ae87..24c116a 100644 --- a/vendor/lief/doc/doxygen/doxygen_index.md +++ b/vendor/lief/doc/doxygen/doxygen_index.md @@ -1,6 +1,6 @@ Welcome to the LIEF's Doxygen Documentation -LIEF Architecture +LIEF Architecture To get started, you can look at the LIEF::ELF namespace or the LIEF::PE::Binary class. diff --git a/vendor/lief/doc/requirements.txt b/vendor/lief/doc/requirements.txt index 57a309d..8407825 100644 --- a/vendor/lief/doc/requirements.txt +++ b/vendor/lief/doc/requirements.txt @@ -1,4 +1,8 @@ -sphinx -alabaster -breathe -sphinx_rtd_theme +requests==2.34.2 +sphinx==9.1.99 +myst-parser==5.1.0 +Pygments==2.20.0 +breathe==4.36.0 +sphinx-tabs==3.5.0 +markdownify==1.2.3 +lxml==6.1.0 diff --git a/vendor/lief/doc/sphinx/_cross_api.md b/vendor/lief/doc/sphinx/_cross_api.md new file mode 100644 index 0000000..e4cface --- /dev/null +++ b/vendor/lief/doc/sphinx/_cross_api.md @@ -0,0 +1,1776 @@ +```{eval-rst} +.. |demangle| lief-api:: LIEF.demangle() + + :rust:func:`lief::demangle` + :py:func:`lief.demangle` + :cpp:func:`LIEF::demangle` + +.. |lief-dump| lief-api:: LIEF.dump() + + :rust:func:`lief::dump` + :rust:func:`lief::dump_with_limit` + :py:func:`lief.dump` + :cpp:func:`LIEF::dump` + +.. |get_int_from_virtual_address| lief-api:: LIEF.get_int_from_virtual_address() + + :rust:method:`lief::elf::Binary::get_int_from_virtual_address [struct]` + :py:meth:`lief.Binary.get_int_from_virtual_address` + :cpp:func:`LIEF::Binary::get_int_from_virtual_address` + +.. |lief-parse| lief-api:: lief.parse() + + :rust:method:`lief::Binary::parse [enum]` + :rust:method:`lief::Binary::from [enum]` + :py:func:`lief.parse` + +.. Logging ===================================================================== + +.. |lief-logging-level| lief-api:: lief.logging.Level + + :rust:enum:`lief::logging::Level` + :py:class:`lief.logging.Level` + :cpp:enum:`LIEF::logging::Level` + +.. ObjC ========================================================================== + +.. |lief-objc-metadata| lief-api:: lief.ObjC.Metadata + + :rust:struct:`lief::objc::Metadata` + :py:class:`lief.objc.Metadata` + :cpp:class:`LIEF::objc::Metadata` + +.. |lief-objc-metadata-to_decl| lief-api:: lief.ObjC.Metadata.to_decl() + + :rust:method:`lief::objc::Metadata::to_decl [struct]` + :py:meth:`lief.objc.Metadata.to_decl` + :cpp:func:`LIEF::objc::Metadata::to_decl` + +.. |lief-objc-metadata-categories| lief-api:: lief.ObjC.Metadata.categories + + :rust:method:`lief::objc::Metadata::categories [struct]` + :py:attr:`lief.objc.Metadata.categories` + :cpp:func:`LIEF::objc::Metadata::categories` + +.. |lief-objc-category| lief-api:: lief.ObjC.Category + + :rust:struct:`lief::objc::Category` + :py:class:`lief.objc.Category` + :cpp:class:`LIEF::objc::Category` + +.. |lief-objc-method-address| lief-api:: lief.ObjC.Method.address() + + :rust:method:`lief::objc::Method::address [struct]` + :py:attr:`lief.objc.Method.address` + :cpp:func:`LIEF::objc::Method::address` + +.. |lief-objc-metadata-to_decl_opt| lief-api:: lief.ObjC.Metadata.to_decl() + + :rust:method:`lief::objc::Metadata::to_decl_with_opt [struct]` + :py:meth:`lief.objc.Metadata.to_decl` + :cpp:func:`LIEF::objc::Metadata::to_decl` + +.. |lief-objc-class-to_decl_opt| lief-api:: lief.ObjC.Class.to_decl() + + :rust:method:`lief::objc::Class::to_decl_with_opt [struct]` + :py:meth:`lief.objc.Class.to_decl` + :cpp:func:`LIEF::objc::Class::to_decl` + +.. |lief-objc-proto-to_decl_opt| lief-api:: lief.ObjC.Protocol.to_decl() + + :rust:method:`lief::objc::Protocol::to_decl_with_opt [struct]` + :py:meth:`lief.objc.Protocol.to_decl` + :cpp:func:`LIEF::objc::Protocol::to_decl` + +.. |lief-objc-declopt| lief-api:: lief.ObjC.DeclOpt + + :rust:struct:`lief::objc::DeclOpt` + :py:class:`lief.objc.DeclOpt` + :cpp:struct:`LIEF::objc::DeclOpt` + +.. DebugInfo =================================================================== + +.. |lief-debug-info-find_function_address| lief-api:: lief.DebugInfo.find_function_address() + + :rust:method:`lief::generic::DebugInfo::find_function_address [trait]` + :py:meth:`lief.DebugInfo.find_function_address` + :cpp:func:`LIEF::DebugInfo::find_function_address` + +.. |lief-declopt| lief-api:: lief.DeclOpt + + :rust:struct:`lief::DeclOpt` + :py:class:`lief.DeclOpt` + :cpp:class:`LIEF::DeclOpt` + +.. DWARF ======================================================================= + +.. |lief-dwarf-binary-debug-info| lief-api:: lief.Binary.debug_info() + + :rust:method:`lief::elf::Binary::debug_info [struct]` + :py:attr:`lief.Binary.debug_info` + :cpp:func:`LIEF::Binary::debug_info` + +.. |lief-dwarf-function| lief-api:: lief.dwarf.Function + + :rust:struct:`lief::dwarf::Function` + :py:class:`lief.dwarf.Function` + :cpp:class:`LIEF::dwarf::Function` + + +.. |lief-dwarf-function-is-external| lief-api:: lief.dwarf.Function.is_external() + + :rust:method:`lief::dwarf::Function::is_external [struct]` + :py:attr:`lief.dwarf.Function.is_external` + :cpp:func:`LIEF::dwarf::Function::is_external` + +.. |lief-dwarf-CompilationUnit| lief-api:: lief.dwarf.CompilationUnit + + :rust:struct:`lief::dwarf::CompilationUnit` + :py:class:`lief.dwarf.CompilationUnit` + :cpp:class:`LIEF::dwarf::CompilationUnit` + +.. |lief-dwarf-cu-imported-functions| lief-api:: lief.dwarf.CompilationUnit.imported_functions() + + :rust:method:`lief::dwarf::CompilationUnit::imported_functions [struct]` + :py:attr:`lief.dwarf.CompilationUnit.imported_functions` + :cpp:func:`LIEF::dwarf::CompilationUnit::imported_functions` + +.. |lief-dwarf-debug-info| lief-api:: lief.dwarf.DebugInfo + + :rust:struct:`lief::dwarf::DebugInfo` + :py:class:`lief.dwarf.DebugInfo` + :cpp:class:`LIEF::dwarf::DebugInfo` + +.. |lief-dwarf-load| lief-api:: lief.dwarf.load() + + :rust:func:`lief::dwarf::load` + :py:func:`lief.dwarf.load` + :cpp:func:`LIEF::dwarf::load` + +.. |lief-dwarf-function-instructions| lief-api:: lief.dwarf.Function.instructions() + + :rust:method:`lief::dwarf::Function::instructions [struct]` + :cpp:func:`LIEF::dwarf::Function::instructions` + :py:attr:`lief.dwarf.Function.instructions` + +.. |lief-dwarf-editor| lief-api:: lief.dwarf.Editor + + :rust:struct:`lief::dwarf::Editor` + :py:class:`lief.dwarf.Editor` + :cpp:class:`LIEF::dwarf::Editor` + +.. |lief-dwarf-editor-from_binary| lief-api:: lief.dwarf.Editor.from_binary() + + :rust:method:`lief::dwarf::Editor::from_binary [struct]` + :cpp:func:`LIEF::dwarf::Editor::from_binary` + :py:func:`lief.dwarf.Editor.from_binary` + +.. |lief-dwarf-editor-CompilationUnit| lief-api:: lief.dwarf.editor.CompilationUnit + + :rust:struct:`lief::dwarf::editor::CompilationUnit` + :py:class:`lief.dwarf.editor.CompilationUnit` + :cpp:class:`LIEF::dwarf::editor::CompilationUnit` + +.. |lief-dwarf-editor-Function| lief-api:: lief.dwarf.editor.Function + + :rust:struct:`lief::dwarf::editor::Function` + :py:class:`lief.dwarf.editor.Function` + :cpp:class:`LIEF::dwarf::editor::Function` + +.. |lief-dwarf-editor-Variable| lief-api:: lief.dwarf.editor.Variable + + :rust:struct:`lief::dwarf::editor::Variable` + :py:class:`lief.dwarf.editor.Variable` + :cpp:class:`LIEF::dwarf::editor::Variable` + +.. |lief-dwarf-editor-Type| lief-api:: lief.dwarf.editor.Type + + :rust:enum:`lief::dwarf::editor::Type` + :py:class:`lief.dwarf.editor.Type` + :cpp:class:`LIEF::dwarf::editor::Type` + +.. |lief-dwarf-variable| lief-api:: lief.dwarf.Variable + + :rust:struct:`lief::dwarf::Variable` + :py:class:`lief.dwarf.Variable` + :cpp:class:`LIEF::dwarf::Variable` + + +.. |lief-dwarf-lexical-block| lief-api:: lief.dwarf.LexicalBlock + + :rust:struct:`lief::dwarf::LexicalBlock` + :py:class:`lief.dwarf.LexicalBlock` + :cpp:class:`LIEF::dwarf::LexicalBlock` + +.. |lief-dwarf-function-description| lief-api:: lief.dwarf.Function.description() + + :rust:method:`lief::dwarf::Function::description [struct]` + :cpp:func:`LIEF::dwarf::Function::description` + :py:attr:`lief.dwarf.Function.description` + +.. |lief-dwarf-variable-description| lief-api:: lief.dwarf.Variable.description() + + :rust:method:`lief::dwarf::Variable::description [struct]` + :cpp:func:`LIEF::dwarf::Variable::description` + :py:attr:`lief.dwarf.Variable.description` + +.. |lief-dwarf-lexical-block-description| lief-api:: lief.dwarf.LexicalBlock.description() + + :rust:method:`lief::dwarf::LexicalBlock::description [struct]` + :cpp:func:`LIEF::dwarf::LexicalBlock::description` + :py:attr:`lief.dwarf.LexicalBlock.description` + +.. |lief-dwarf-editor-Function-lexical-block| lief-api:: lief.dwarf.editor.Function.LexicalBlock + + :rust:struct:`lief::dwarf::editor::function::LexicalBlock` + :py:class:`lief.dwarf.editor.Function.LexicalBlock` + :cpp:class:`LIEF::dwarf::editor::Function::LexicalBlock` + +.. |lief-dwarf-types-Enum-entries| lief-api:: lief.dwarf.types.Enum.entries() + + :rust:method:`lief::dwarf::types::Enum::entries [struct]` + :cpp:func:`LIEF::dwarf::types::Enum::entries` + :py:attr:`lief.dwarf.types.Enum.entries` + +.. |lief-dwarf-function-to_decl| lief-api:: lief.dwarf.Function.to_decl() + + :rust:method:`lief::dwarf::Function::to_decl [struct]` + :rust:method:`lief::dwarf::Function::to_decl_with_opt [struct]` + :py:meth:`lief.dwarf.Function.to_decl` + :cpp:func:`LIEF::dwarf::Function::to_decl` + +.. |lief-dwarf-variable-to_decl| lief-api:: lief.dwarf.Variable.to_decl() + + :rust:method:`lief::dwarf::Variable::to_decl [struct]` + :rust:method:`lief::dwarf::Variable::to_decl_with_opt [struct]` + :py:meth:`lief.dwarf.Variable.to_decl` + :cpp:func:`LIEF::dwarf::Variable::to_decl` + +.. |lief-dwarf-type-to_decl| lief-api:: lief.dwarf.Type.to_decl() + + :rust:method:`lief::dwarf::Type::to_decl [enum]` + :rust:method:`lief::dwarf::Type::to_decl_with_opt [enum]` + :py:meth:`lief.dwarf.Type.to_decl` + :cpp:func:`LIEF::dwarf::Type::to_decl` + +.. |lief-dwarf-cu-to_decl| lief-api:: lief.dwarf.CompilationUnit.to_decl() + + :rust:method:`lief::dwarf::CompilationUnit::to_decl [struct]` + :rust:method:`lief::dwarf::CompilationUnit::to_decl_with_opt [struct]` + :py:meth:`lief.dwarf.CompilationUnit.to_decl` + :cpp:func:`LIEF::dwarf::CompilationUnit::to_decl` + +.. PDB ========================================================================= + +.. |lief-pdb-binary-debug-info| lief-api:: lief.Binary.debug_info() + + :rust:method:`lief::pe::Binary::debug_info [struct]` + :py:attr:`lief.Binary.debug_info` + :cpp:func:`LIEF::Binary::debug_info` + +.. |lief-pdb-debug-info| lief-api:: lief.pdb.DebugInfo + + :rust:struct:`lief::pdb::DebugInfo` + :py:class:`lief.pdb.DebugInfo` + :cpp:class:`LIEF::pdb::DebugInfo` + +.. |lief-pdb-load| lief-api:: lief.pdb.load() + + :rust:func:`lief::pdb::load` + :py:func:`lief.pdb.load` + :cpp:func:`LIEF::pdb::load` + +.. |lief-pdb-buildmetadata| lief-api:: lief.pdb.BuildMetadata + + :rust:struct:`lief::pdb::BuildMetadata` + :py:class:`lief.pdb.BuildMetadata` + :cpp:class:`LIEF::pdb::BuildMetadata` + +.. |lief-pdb-CompilationUnit| lief-api:: lief.pdb.CompilationUnit + + :rust:struct:`lief::pdb::CompilationUnit` + :py:class:`lief.pdb.CompilationUnit` + :cpp:class:`LIEF::pdb::CompilationUnit` + +.. |lief-pdb-compilationunit-buildmetadata| lief-api:: lief.pdb.CompilationUnit.build_metadata() + + :rust:method:`lief::pdb::CompilationUnit::build_metadata [struct]` + :py:attr:`lief.pdb.CompilationUnit.build_metadata` + :cpp:func:`LIEF::pdb::CompilationUnit::build_metadata` + +.. |lief-pdb-is_pdb| lief-api:: lief.pdb.is_pdb + + :rust:func:`lief::pdb::is_pdb` + :py:meth:`lief.is_pdb` + :cpp:func:`bool LIEF::pdb::is_pdb(const std::std::string &)` + +.. |lief-pdb-types-Enum| lief-api:: lief.pdb.types.Enum + + :rust:struct:`lief::pdb::types::Enum` + :py:class:`lief.pdb.types.Enum` + :cpp:class:`LIEF::pdb::types::Enum` + +.. |lief-pdb-types-Function| lief-api:: lief.pdb.types.Function + + :rust:struct:`lief::pdb::types::Function` + :py:class:`lief.pdb.types.Function` + :cpp:class:`LIEF::pdb::types::Function` + +.. |lief-pdb-types-Array| lief-api:: lief.pdb.types.Array + + :rust:struct:`lief::pdb::types::Array` + :py:class:`lief.pdb.types.Array` + :cpp:class:`LIEF::pdb::types::Array` + +.. |lief-pdb-types-Simple| lief-api:: lief.pdb.types.Simple + + :rust:struct:`lief::pdb::types::Simple` + :py:class:`lief.pdb.types.Simple` + :cpp:class:`LIEF::pdb::types::Simple` + +.. |lief-pdb-types-Method| lief-api:: lief.pdb.types.Method + + :rust:struct:`lief::pdb::types::Method` + :py:class:`lief.pdb.types.Method` + :cpp:class:`LIEF::pdb::types::Method` + +.. |lief-pdb-type-to_decl| lief-api:: lief.pdb.Type.to_decl() + + :rust:method:`lief::pdb::Type::to_decl [enum]` + :rust:method:`lief::pdb::Type::to_decl_with_opt [enum]` + :py:meth:`lief.pdb.Type.to_decl` + :cpp:func:`LIEF::pdb::Type::to_decl` + +.. |lief-pdb-Function| lief-api:: lief.pdb.Function + + :rust:struct:`lief::pdb::Function` + :py:class:`lief.pdb.Function` + :cpp:class:`LIEF::pdb::Function` + +.. |lief-pdb-function-to_decl| lief-api:: lief.pdb.Function.to_decl() + + :rust:method:`lief::pdb::Function::to_decl [struct]` + :rust:method:`lief::pdb::Function::to_decl_with_opt [struct]` + :py:meth:`lief.pdb.Function.to_decl` + :cpp:func:`LIEF::pdb::Function::to_decl` + +.. |lief-pdb-cu-to_decl| lief-api:: lief.pdb.CompilationUnit.to_decl() + + :rust:method:`lief::pdb::CompilationUnit::to_decl [struct]` + :rust:method:`lief::pdb::CompilationUnit::to_decl_with_opt [struct]` + :py:meth:`lief.pdb.CompilationUnit.to_decl` + :cpp:func:`LIEF::pdb::CompilationUnit::to_decl` + +.. PE ========================================================================== + +.. |lief-pe-parser-config| lief-api:: lief.PE.ParserConfig + + :rust:struct:`lief::pe::ParserConfig` + :py:class:`lief.PE.ParserConfig` + :cpp:class:`LIEF::PE::ParserConfig` + +.. |lief-pe-parser-config-parse_exceptions| lief-api:: lief.PE.ParserConfig.parse_exceptions + + :rust:member:`lief::pe::ParserConfig::parse_exceptions [struct]` + :py:attr:`lief.PE.ParserConfig.parse_exceptions` + :cpp:member:`LIEF::PE::ParserConfig::parse_exceptions` + +.. |lief-pe-parser-config-parse_arm64x_binary| lief-api:: lief.PE.ParserConfig.parse_arm64x_binary + + :rust:member:`lief::pe::ParserConfig::parse_arm64x_binary [struct]` + :py:attr:`lief.PE.ParserConfig.parse_arm64x_binary` + :cpp:member:`LIEF::PE::ParserConfig::parse_arm64x_binary` + +.. |lief-pe-builder| lief-api:: lief.PE.Builder + + :py:class:`lief.PE.Builder` + :cpp:class:`LIEF::PE::Builder` + +.. |lief-pe-parse| lief-api:: lief.PE.parse() + + :rust:method:`lief::pe::Binary::parse [struct]` + :py:func:`lief.PE.parse` + :cpp:func:`LIEF::PE::Parser::parse` + +.. |lief-pe-parse_from_dump| lief-api:: lief.PE.parse_from_dump() + + :rust:method:`lief::pe::Binary::parse_from_dump [struct]` + :py:func:`lief.PE.parse_from_dump` + :cpp:func:`LIEF::PE::Parser::parse_from_dump` + +.. |lief-pe-binary| lief-api:: lief.PE.Binary + + :rust:struct:`lief::pe::Binary` + :py:class:`lief.PE.Binary` + :cpp:class:`LIEF::PE::Binary` + +.. |lief-pe-binary-offset_to_rva| lief-api:: lief.PE.Binary.offset_to_rva() + + :rust:method:`lief::pe::Binary::offset_to_rva [struct]` + :py:meth:`lief.PE.Binary.offset_to_rva` + :cpp:func:`LIEF::PE::Binary::offset_to_rva` + +.. |lief-pe-binary-rva_to_offset| lief-api:: lief.PE.Binary.rva_to_offset() + + :rust:method:`lief::pe::Binary::rva_to_offset [struct]` + :py:meth:`lief.PE.Binary.rva_to_offset` + :cpp:func:`LIEF::PE::Binary::rva_to_offset` + +.. |lief-pe-binary-va_to_offset| lief-api:: lief.PE.Binary.va_to_offset() + + :rust:method:`lief::pe::Binary::va_to_offset [struct]` + :py:meth:`lief.PE.Binary.va_to_offset` + :cpp:func:`LIEF::PE::Binary::va_to_offset` + +.. |lief-pe-tls| lief-api:: lief.PE.TLS + + :rust:struct:`lief::pe::TLS` + :py:class:`lief.PE.TLS` + :cpp:class:`LIEF::PE::TLS` + +.. |lief-pe-binary-exceptions| lief-api:: lief.PE.Binary + + :rust:method:`lief::pe::Binary::exceptions [struct]` + :py:attr:`lief.PE.Binary.exceptions` + :cpp:func:`LIEF::PE::Binary::exceptions` + +.. |lief-pe-loadconfig| lief-api:: lief.PE.LoadConfiguration + + :rust:struct:`lief::pe::LoadConfiguration` + :py:class:`lief.PE.LoadConfiguration` + :cpp:class:`LIEF::PE::LoadConfiguration` + +.. |lief-pe-chpe_metadata| lief-api:: lief.PE.CHPEMetadata + + :rust:enum:`lief::pe::CHPEMetadata` + :py:class:`lief.PE.CHPEMetadata` + :cpp:class:`LIEF::PE::CHPEMetadata` + +.. |lief-pe-chpe_metadata-arm64| lief-api:: lief.PE.CHPEMetadataARM64 + + :rust:struct:`lief::pe::chpe_metadata_arm64::CHPEMetadata` + :py:class:`lief.PE.CHPEMetadataARM64` + :cpp:class:`LIEF::PE::CHPEMetadataARM64` + +.. |lief-pe-dynamic-relocation| lief-api:: lief.PE.DynamicRelocation + + :rust:enum:`lief::pe::DynamicRelocation` + :py:class:`lief.PE.DynamicRelocation` + :cpp:class:`LIEF::PE::DynamicRelocation` + +.. |lief-pe-enclave-configuration| lief-api:: lief.PE.EnclaveConfiguration + + :rust:struct:`lief::pe::EnclaveConfiguration` + :py:class:`lief.PE.EnclaveConfiguration` + :cpp:class:`LIEF::PE::EnclaveConfiguration` + +.. |lief-pe-volatile-metadata| lief-api:: lief.PE.VolatileMetadata + + :rust:struct:`lief::pe::VolatileMetadata` + :py:class:`lief.PE.VolatileMetadata` + :cpp:class:`LIEF::PE::VolatileMetadata` + + +.. |lief-pe-exceptioninfo| lief-api:: lief.PE.ExceptionInfo + + :rust:enum:`lief::pe::exception::RuntimeExceptionFunction` + :py:class:`lief.PE.ExceptionInfo` + :cpp:class:`LIEF::PE::ExceptionInfo` + +.. |lief-pe-section-coff_string| lief-api:: lief.PE.Section.coff_string + + :rust:method:`lief::pe::Section::coff_string [struct]` + :py:attr:`lief.PE.Section.coff_string` + :cpp:func:`LIEF::PE::Section::coff_string` + +.. |lief-pe-codeviewpdb-filename| lief-api:: lief.PE.CodeViewPDB.filename() + + :rust:method:`lief::pe::debug::CodeViewPDB::filename [struct]` + :py:attr:`lief.PE.CodeViewPDB.filename` + :cpp:func:`LIEF::PE::CodeViewPDB::filename` + +.. |lief-pe-delayimportentry-demangled_name| lief-api:: lief.PE.DelayImportEntry.demangled_name() + + :rust:method:`lief::pe::delay_import::DelayImportEntry::demangled_name [struct]` + :py:attr:`lief.PE.DelayImportEntry.demangled_name` + :cpp:func:`LIEF::PE::DelayImportEntry::demangled_name` + +.. |lief-pe-importentry-demangled_name| lief-api:: lief.PE.ImportEntry.demangled_name() + + :rust:method:`lief::pe::import::ImportEntry::demangled_name [struct]` + :py:attr:`lief.PE.ImportEntry.demangled_name` + :cpp:func:`LIEF::PE::ImportEntry::demangled_name` + +.. |lief-pe-exportentry-demangled_name| lief-api:: lief.PE.ExportEntry.demangled_name() + + :rust:method:`lief::pe::export::Entry::demangled_name [struct]` + :py:attr:`lief.PE.ExportEntry.demangled_name` + :cpp:func:`LIEF::PE::ExportEntry::demangled_name` + +.. |lief-pe-export-entry| lief-api:: lief.PE.ExportEntry + + :rust:struct:`lief::pe::export::Entry` + :py:class:`lief.PE.ExportEntry` + :cpp:class:`LIEF::PE::ExportEntry` + +.. |lief-pe-binary-write| lief-api:: lief.PE.Binary.write() + + :rust:method:`lief::pe::Binary::write [struct]` + :py:meth:`lief.PE.Binary.write` + :cpp:func:`LIEF::PE::Binary::write` + +.. |lief-macho-binary-virtual_address_to_offset| lief-api:: lief.MachO.Binary.virtual_address_to_offset() + + :rust:method:`lief::macho::Binary::virtual_address_to_offset [struct]` + :py:meth:`lief.MachO.Binary.virtual_address_to_offset` + :cpp:func:`LIEF::MachO::Binary::virtual_address_to_offset` + +.. |lief-pe-binary-write_to_bytes| lief-api:: lief.PE.Binary.write_to_bytes() + + :rust:method:`lief::pe::Binary::write_to_bytes [struct]` + :rust:method:`lief::pe::Binary::write_to_bytes_with_config [struct]` + :py:meth:`lief.PE.Binary.write_to_bytes` + :cpp:func:`std::unique_ptr LIEF::PE::Binary::write(std::ostream &)` + :cpp:func:`std::unique_ptr LIEF::PE::Binary::write(std::ostream &, const Builder::config_t &)` + +.. |lief-pe-binary-signatures| lief-api:: lief.PE.Binary.signatures() + + :rust:method:`lief::pe::Binary::signatures [struct]` + :py:attr:`lief.PE.Binary.signatures` + :cpp:func:`LIEF::PE::Binary::signatures` + +.. |lief-pe-binary-is_arm64ec| lief-api:: lief.PE.Binary.is_arm64ec() + + :rust:method:`lief::pe::Binary::is_arm64ec [struct]` + :py:attr:`lief.PE.Binary.is_arm64ec` + :cpp:func:`LIEF::PE::Binary::is_arm64ec` + +.. |lief-pe-binary-is_arm64x| lief-api:: lief.PE.Binary.is_arm64x() + + :rust:method:`lief::pe::Binary::is_arm64x [struct]` + :py:attr:`lief.PE.Binary.is_arm64x` + :cpp:func:`LIEF::PE::Binary::is_arm64x` + +.. |lief-pe-binary-nested_pe_binary| lief-api:: lief.PE.Binary.nested_pe_binary() + + :rust:method:`lief::pe::Binary::nested_pe_binary [struct]` + :py:attr:`lief.PE.Binary.nested_pe_binary` + :cpp:func:`LIEF::PE::Binary::nested_pe_binary` + +.. |lief-pe-signature| lief-api:: lief.PE.Signature + + :rust:struct:`lief::pe::Signature` + :py:class:`lief.PE.Signature` + :cpp:class:`LIEF::PE::Signature` + +.. |lief-pe-signature-check| lief-api:: lief.PE.Signature.check() + + :rust:method:`lief::pe::Signature::check [struct]` + :py:meth:`lief.PE.Signature.check` + :cpp:func:`LIEF::PE::Signature::check` + +.. |lief-pe-binary-verify_signature| lief-api:: lief.PE.Binary.verify_signature() + + :rust:method:`lief::pe::Binary::verify_signature [struct]` + :py:meth:`lief.PE.Binary.verify_signature` + :cpp:func:`LIEF::PE::Binary::verify_signature` + +.. |lief-pe-datadirectory| lief-api:: lief.PE.DataDirectory + + :rust:struct:`lief::pe::DataDirectory` + :py:class:`lief.PE.DataDirectory` + :cpp:class:`LIEF::PE::DataDirectory` + +.. |lief-pe-datadirectory-content| lief-api:: lief.PE.DataDirectory.content() + + :rust:method:`lief::pe::DataDirectory::content [struct]` + :py:attr:`lief.PE.DataDirectory.content` + :cpp:func:`LIEF::PE::DataDirectory::content` + +.. |lief-pe-resource-node-parse| lief-api:: lief.PE.ResourceNode.parse() + + :rust:method:`lief::pe::ResourceNode::from_slice [enum]` + :py:func:`lief.PE.ResourceNode.parse` + :cpp:func:`LIEF::PE::ResourceNode::parse` + +.. |lief-pe-binary-remove-import| lief-api:: lief.PE.Binary.remove_import() + + :rust:method:`lief::pe::Binary::remove_import [struct]` + :py:func:`lief.PE.Binary.remove_import` + :cpp:func:`LIEF::PE::Binary::remove_import` + +.. |lief-pe-binary-remove-all-import| lief-api:: lief.PE.Binary.remove_all_imports() + + :rust:method:`lief::pe::Binary::remove_all_imports [struct]` + :py:func:`lief.PE.Binary.remove_all_imports` + :cpp:func:`LIEF::PE::Binary::remove_all_imports` + +.. |lief-pe-binary-add-import| lief-api:: lief.PE.Binary.add_import() + + :rust:method:`lief::pe::Binary::add_import [struct]` + :rust:method:`lief::pe::Binary::add_import_at_pos [struct]` + :py:func:`lief.PE.Binary.add_import` + :cpp:func:`LIEF::PE::Binary::add_import` + +.. |lief-pe-import-add-entry| lief-api:: lief.PE.Import.add_entry() + + :rust:method:`lief::pe::import::Import::add_entry_by_name [struct]` + :py:func:`lief.PE.Import.add_entry` + :cpp:func:`LIEF::PE::Import::add_entry` + +.. |lief-pe-import| lief-api:: lief.PE.Import + + :rust:struct:`lief::pe::import::Import` + :py:class:`lief.PE.Import` + :cpp:class:`LIEF::PE::Import` + +.. |lief-pe-importentry| lief-api:: lief.PE.ImportEntry + + :rust:struct:`lief::pe::import::ImportEntry` + :py:class:`lief.PE.ImportEntry` + :cpp:class:`LIEF::PE::ImportEntry` + +.. |lief-pe-importentry-iat-value| lief-api:: lief.PE.ImportEntry.iat_value + + :rust:method:`lief::pe::import::ImportEntry::iat_value [struct]` + :py:attr:`lief.PE.ImportEntry.iat_value` + :cpp:func:`LIEF::PE::ImportEntry::iat_value` + +.. |lief-pe-importentry-ilt-value| lief-api:: lief.PE.ImportEntry.ilt_value + + :rust:method:`lief::pe::import::ImportEntry::ilt_value [struct]` + :py:attr:`lief.PE.ImportEntry.ilt_value` + :cpp:func:`LIEF::PE::ImportEntry::ilt_value` + +.. |lief-pe-importentry-iat-address| lief-api:: lief.PE.ImportEntry.iat_address() + + :rust:method:`lief::pe::import::ImportEntry::iat_address [struct]` + :py:attr:`lief.PE.ImportEntry.iat_address` + :cpp:func:`LIEF::PE::ImportEntry::iat_address` + +.. |lief-pe-builder-config-resolved_iat_cbk| lief-api:: lief.PE.Builder.config_t.resolved_iat_cbk + + :py:attr:`lief.PE.Builder.config_t.resolved_iat_cbk` + :cpp:member:`LIEF::PE::Builder::config_t::resolved_iat_cbk` + +.. |lief-pe-builder-config-imports| lief-api:: lief.PE.Builder.config_t.imports + + :rust:member:`lief::pe::builder::Config::imports [struct]` + :py:attr:`lief.PE.Builder.config_t.imports` + :cpp:member:`LIEF::PE::Builder::config_t::imports` + +.. |lief-pe-builder-config-exports| lief-api:: lief.PE.Builder.config_t.exports + + :rust:member:`lief::pe::builder::Config::exports [struct]` + :py:attr:`lief.PE.Builder.config_t.exports` + :cpp:member:`LIEF::PE::Builder::config_t::exports` + +.. |lief-pe-builder-config-export_section| lief-api:: lief.PE.Builder.config_t.export_section + + :rust:member:`lief::pe::builder::Config::export_section [struct]` + :py:attr:`lief.PE.Builder.config_t.export_section` + :cpp:member:`LIEF::PE::Builder::config_t::export_section` + +.. |lief-pe-builder-config| lief-api:: lief.PE.Builder.config_t + + :rust:struct:`lief::pe::::builder::Config` + :py:class:`lief.PE.Builder.config_t` + :cpp:class:`LIEF::PE::Builder::config_t` + +.. |lief-pe-import-remove-entry| lief-api:: lief.PE.Import.remove_entry + + :rust:method:`lief::pe::import::Import::remove_entry_by_name [struct]` + :rust:method:`lief::pe::import::Import::remove_entry_by_ordinal [struct]` + :py:func:`lief.PE.Import.remove_entry` + :cpp:func:`LIEF::PE::Import::remove_entry` + +.. |lief-pe-resource-manager| lief-api:: lief.PE.ResourcesManager + + :rust:struct:`lief::pe::resources::Manager` + :py:class:`lief.PE.ResourcesManager` + :cpp:class:`LIEF::PE::ResourcesManager` + +.. |lief-pe-resourcestringtable| lief-api:: lief.PE.ResourceStringTable + + :py:class:`lief.PE.ResourceStringTable` + :cpp:class:`LIEF::PE::ResourceStringTable` + + +.. |lief-pe-resource-node| lief-api:: lief.PE.ResourceNode + + :rust:enum:`lief::pe::resources::Node` + :py:class:`lief.PE.ResourceNode` + :cpp:class:`LIEF::PE::ResourceNode` + +.. |lief-pe-resource-node-add-child| lief-api:: lief.PE.ResourceNode.add_child() + + :rust:method:`lief::pe::resources::NodeBase::add_child [trait]` + :py:meth:`lief.PE.ResourceNode.add_child` + :cpp:func:`LIEF::PE::ResourceNode::add_child` + +.. |lief-pe-resource-node-remove-child| lief-api:: lief.PE.ResourceNode.delete_child() + + :rust:method:`lief::pe::resources::NodeBase::delete_child [trait]` + :py:meth:`lief.PE.ResourceNode.delete_child` + :cpp:func:`LIEF::PE::ResourceNode::delete_child` + +.. |lief-pe-binary-resources| lief-api:: lief.PE.Binary.resources() + + :rust:method:`lief::pe::Binary::resources [struct]` + :py:attr:`lief.PE.Binary.resources` + :cpp:func:`LIEF::PE::Binary::resources` + +.. |lief-pe-binary-set_resources| lief-api:: lief.PE.Binary.set_resources() + + :rust:method:`lief::pe::Binary::set_resources [struct]` + :py:func:`lief.PE.Binary.set_resources` + :cpp:func:`LIEF::PE::Binary::set_resources` + +.. |lief-pe-debug| lief-api:: lief.PE.Debug + + :rust:enum:`lief::pe::debug::Entries` + :py:class:`lief.PE.Debug` + :cpp:class:`LIEF::PE::Debug` + +.. |lief-pe-codeviewpdb| lief-api:: lief.PE.CodeViewPDB + + :rust:struct:`lief::pe::debug::CodeViewPDB` + :py:class:`lief.PE.CodeViewPDB` + :cpp:class:`LIEF::PE::CodeViewPDB` + +.. |lief-pe-binary-clear-debug| lief-api:: lief.PE.Binary.clear_debug + + :rust:method:`lief::pe::Binary::clear_debug [struct]` + :py:func:`lief.PE.Binary.clear_debug` + :cpp:func:`LIEF::PE::Binary::clear_debug` + +.. |lief-pe-binary-remove-debug| lief-api:: lief.PE.Binary.remove_debug + + :rust:method:`lief::pe::Binary::remove_debug [struct]` + :py:func:`lief.PE.Binary.remove_debug` + :cpp:func:`LIEF::PE::Binary::remove_debug` + + +.. |lief-pe-binary-add-debug-info| lief-api:: lief.PE.Binary.add_debug_info + + :rust:method:`lief::pe::Binary::add_debug_info [struct]` + :py:func:`lief.PE.Binary.add_debug_info` + :cpp:func:`LIEF::PE::Binary::add_debug_info` + +.. |lief-pe-vcfeature| lief-api:: lief.PE.VCFeature + + :rust:struct:`lief::pe::debug::VCFeature` + :py:class:`lief.PE.VCFeature` + :cpp:class:`LIEF::PE::VCFeature` + +.. |lief-pe-fpo| lief-api:: lief.PE.FPO + + :rust:struct:`lief::pe::debug::FPO` + :py:class:`lief.PE.FPO` + :cpp:class:`LIEF::PE::FPO` + +.. |lief-pe-exdllcharacteristics| lief-api:: lief.PE.ExDllCharacteristics + + :rust:struct:`lief::pe::debug::ExDllCharacteristics` + :py:class:`lief.PE.ExDllCharacteristics` + :cpp:class:`LIEF::PE::ExDllCharacteristics` + +.. |lief-pe-pdbchecksum| lief-api:: lief.PE.PDBChecksum + + :rust:struct:`lief::pe::debug::PDBChecksum` + :py:class:`lief.PE.PDBChecksum` + :cpp:class:`LIEF::PE::PDBChecksum` + +.. Abstract ==================================================================== + +.. |lief-abstract-binary| lief-api:: lief.abstract.Binary + + :rust:trait:`lief::generic::Binary` + :py:class:`lief.Binary` + :cpp:class:`LIEF::Binary` + +.. |lief-binary-offset_to_virtual_address| lief-api:: lief.Binary.offset_to_virtual_address() + + :rust:method:`lief::generic::Binary::offset_to_virtual_address [trait]` + :py:meth:`lief.Binary.offset_to_virtual_address` + :cpp:func:`LIEF::Binary::offset_to_virtual_address` + +.. |lief-abstract-parse| lief-api:: lief.abstract.parse + + :py:func:`lief.parse` + :cpp:func:`LIEF::Parser::parse` + +.. |lief-header-architectures| lief-api:: lief.Header.ARCHITECTURES + + :py:class:`lief.Header.ARCHITECTURES` + :cpp:enum:`LIEF::Header::ARCHITECTURES` + +.. |lief-header-modes| lief-api:: lief.Header.MODES + + :py:class:`lief.Header.MODES` + :cpp:enum:`LIEF::Header::MODES` + +.. |lief-header-object-types| lief-api:: lief.Header.OBJECT_TYPES + + :py:class:`lief.Header.OBJECT_TYPES` + :cpp:enum:`LIEF::Header::OBJECT_TYPES` + +.. |lief-header-endianness| lief-api:: lief.Header.ENDIANNESS + + :py:class:`lief.Header.ENDIANNESS` + :cpp:enum:`LIEF::Header::ENDIANNESS` + +.. |lief-abstract-binary-page_size| lief-api:: lief.abstract.Binary.page_size() + + :rust:method:`lief::generic::Binary::page_size [trait]` + :py:attr:`lief.Binary.page_size` + :cpp:func:`LIEF::Binary::page_size` + +.. |lief-abstract-binary-load_debug_info| lief-api:: lief.abstract.Binary.load_debug_info() + + :rust:method:`lief::generic::Binary::load_debug_info [trait]` + :py:meth:`lief.Binary.load_debug_info` + :cpp:func:`LIEF::Binary::load_debug_info` + +.. |lief-abstract-binary-patch_address| lief-api:: lief.abstract.Binary.patch_address() + + :rust:method:`lief::generic::Binary::patch_address [trait]` + :py:meth:`lief.Binary.patch_address` + :cpp:func:`LIEF::Binary::patch_address` + +.. |lief-abstract-binary-get_content_from_virtual_address| lief-api:: lief.abstract.Binary.get_content_from_virtual_address() + + :py:meth:`lief.Binary.get_content_from_virtual_address` + :cpp:func:`LIEF::Binary::get_content_from_virtual_address` + +.. |lief-abstract-section-search| lief-api:: lief.abstract.Section.search() + + :py:meth:`lief.Section.search` + :cpp:func:`LIEF::Section::search` + +.. ELF ========================================================================= + +.. |lief-elf-symbol-demangled_name| lief-api:: lief.ELF.Symbol.demangled_name() + + :rust:method:`lief::elf::Symbol::demangled_name [struct]` + :py:attr:`lief.ELF.Symbol.demangled_name` + :cpp:func:`LIEF::ELF::Symbol::demangled_name` + +.. |lief-elf-parse| lief-api:: lief.ELF.parse() + + :rust:method:`lief::elf::Binary::parse [struct]` + :py:func:`lief.ELF.parse` + :cpp:func:`LIEF::ELF::Parser::parse` + +.. |lief-elf-parse_from_dump| lief-api:: lief.ELF.parse_from_dump() + + :rust:method:`lief::elf::Binary::parse_from_dump [struct]` + :py:func:`lief.ELF.parse_from_dump` + :cpp:func:`LIEF::ELF::Parser::parse_from_dump` + +.. |lief-elf-parser-config| lief-api:: lief.ELF.ParserConfig + + :py:class:`lief.ELF.ParserConfig` + :cpp:class:`LIEF::ELF::ParserConfig` + +.. |lief-elf-builder-config| lief-api:: lief.ELF.Builder.config_t + + :py:class:`lief.ELF.Builder.config_t` + :cpp:struct:`LIEF::ELF::Builder::config_t` + +.. |lief-elf-binary| lief-api:: lief.ELF.Binary + + :rust:struct:`lief::elf::Binary` + :py:class:`lief.ELF.Binary` + :cpp:class:`LIEF::ELF::Binary` + +.. |lief-elf-binary-target-android| lief-api:: lief.ELF.Binary.is_targeting_android + + :rust:method:`lief::elf::Binary::is_targeting_android [struct]` + :py:attr:`lief.ELF.Binary.is_targeting_android` + :cpp:func:`LIEF::ELF::Binary::is_targeting_android` + +.. |lief-elf-binary-write| lief-api:: lief.ELF.Binary.write() + + :rust:method:`lief::elf::Binary::write [struct]` + :rust:method:`lief::elf::Binary::write_with_config [struct]` + :py:meth:`lief.ELF.Binary.write` + :cpp:func:`LIEF::ELF::Binary::write` + +.. |lief-elf-binary-write_to_bytes| lief-api:: lief.ELF.Binary.write_to_bytes() + + :rust:method:`lief::elf::Binary::write_to_bytes [struct]` + :rust:method:`lief::elf::Binary::write_to_bytes_with_config [struct]` + :py:meth:`lief.ELF.Binary.write_to_bytes` + :cpp:func:`std::unique_ptr LIEF::ELF::Binary::write(std::ostream &)` + :cpp:func:`std::unique_ptr LIEF::ELF::Binary::write(std::ostream &, const Builder::config_t &)` + +.. |lief-elf-binary-add| lief-api:: lief.ELF.Binary.add() + + :rust:method:`lief::elf::Binary::add_section [struct]` + :rust:method:`lief::elf::Binary::add_segment [struct]` + :py:func:`lief.ELF.Binary.add` + :cpp:func:`LIEF::ELF::Binary::add` + +.. |lief-elf-aarch64pauth| lief-api:: lief.ELF.AArch64PAuth + + :py:class:`lief.ELF.AArch64PAuth` + :cpp:class:`LIEF::ELF::AArch64PAuth` + +.. |lief-elf-relocation-resolve| lief-api:: lief.ELF.Relocation.resolve() + + :rust:method:`lief::elf::Relocation::resolve [struct]` + :rust:method:`lief::elf::Relocation::resolve_with_base_address [struct]` + :py:func:`lief.ELF.Relocation.resolve` + :cpp:func:`LIEF::ELF::Relocation::resolve` + +.. |lief-elf-relocation-r_info| lief-api:: lief.ELF.Relocation.r_info() + + :py:meth:`lief.ELF.Relocation.r_info` + :cpp:func:`LIEF::ELF::Relocation::r_info` + +.. |lief-elf-header-is_mips_n64| lief-api:: lief.ELF.Header.is_mips_n64 + + :rust:method:`lief::elf::Header::is_mips_n64 [struct]` + :py:attr:`lief.ELF.Header.is_mips_n64` + :cpp:func:`LIEF::ELF::Header::is_mips_n64` + +.. |lief-elf-segment| lief-api:: lief.ELF.Segment + + :rust:struct:`lief::elf::Segment` + :py:class:`lief.ELF.Segment` + :cpp:class:`LIEF::ELF::Segment` + +.. |lief-elf-section| lief-api:: lief.ELF.Section + + :rust:struct:`lief::elf::Section` + :py:class:`lief.ELF.Section` + :cpp:class:`LIEF::ELF::Section` + +.. |lief-elf-parser-config-page_size| lief-api:: lief.ELF.ParserConfig.page_size + + :rust:member:`lief::elf::ParserConfig::page_size [struct]` + :py:attr:`lief.ELF.ParserConfig.page_size` + :cpp:member:`LIEF::ELF::ParserConfig::page_size` + +.. |lief-elf-binary-remove-segment| lief-api:: lief.ELF.Binary.remove_segment() + + :rust:method:`lief::elf::Binary::remove_segment [struct]` + :rust:method:`lief::elf::Binary::remove_segments_by_type [struct]` + :py:meth:`lief.ELF.Binary.remove` + :cpp:func:`void LIEF::ELF::Binary::remove(const Segment &, bool)` + :cpp:func:`void LIEF::ELF::Binary::remove(Segment::TYPE, bool)` + +.. |lief-elf-DynamicEntryRpath| lief-api:: lief.ELF.DynamicEntryRpath + + :rust:struct:`lief::elf::dynamic::Rpath` + :py:class:`lief.ELF.DynamicEntryRpath` + :cpp:class:`LIEF::ELF::DynamicEntryRpath` + +.. |lief-elf-DynamicEntryRunPath| lief-api:: lief.ELF.DynamicEntryRunPath + + :rust:struct:`lief::elf::dynamic::RunPath` + :py:class:`lief.ELF.DynamicEntryRunPath` + :cpp:class:`LIEF::ELF::DynamicEntryRunPath` + +.. |lief-elf-DynamicEntryRunPath-insert| lief-api:: lief.ELF.DynamicEntryRunPath.insert() + + :rust:method:`lief::elf::dynamic::RunPath::insert [struct]` + :py:meth:`lief.ELF.DynamicEntryRunPath.insert` + :cpp:func:`LIEF::ELF::DynamicEntryRunPath::insert` + +.. Mach-O ====================================================================== + +.. |lief-macho-binary| lief-api:: lief.MachO.Binary + + :rust:struct:`lief::macho::Binary` + :py:class:`lief.MachO.Binary` + :cpp:class:`LIEF::MachO::Binary` + +.. |lief-macho-binary-objc-metadata| lief-api:: lief.MachO.Binary.objc_metadata + + :rust:method:`lief::macho::Binary::objc_metadata [struct]` + :py:attr:`lief.MachO.Binary.objc_metadata` + :cpp:func:`LIEF::MachO::Binary::objc_metadata` + +.. |lief-macho-binary-is-ios| lief-api:: lief.MachO.Binary.is_ios() + + :rust:method:`lief::macho::Binary::is_ios [struct]` + :py:attr:`lief.MachO.Binary.is_ios` + :cpp:func:`LIEF::MachO::Binary::is_ios` + +.. |lief-macho-binary-is-macos| lief-api:: lief.MachO.Binary.is_macos() + + :rust:method:`lief::macho::Binary::is_macos [struct]` + :py:attr:`lief.MachO.Binary.is_macos` + :cpp:func:`LIEF::MachO::Binary::is_macos` + +.. |lief-macho-binary-platform| lief-api:: lief.MachO.Binary.platform() + + :rust:method:`lief::macho::Binary::platform [struct]` + :py:attr:`lief.MachO.Binary.platform` + :cpp:func:`LIEF::MachO::Binary::platform` + +.. |lief-macho-binary-symbol_stubs| lief-api:: lief.MachO.Binary.symbol_stubs() + + :rust:method:`lief::macho::Binary::symbol_stubs [struct]` + :py:attr:`lief.MachO.Binary.symbol_stubs` + :cpp:func:`LIEF::MachO::Binary::symbol_stubs` + +.. |lief-macho-stub| lief-api:: lief.MachO.Stub + + :rust:struct:`lief::macho::Stub` + :py:class:`lief.MachO.Stub` + :cpp:class:`LIEF::MachO::Stub` + +.. |lief-macho-threadlocalvariables| lief-api:: lief.MachO.ThreadLocalVariables + + :rust:struct:`lief::macho::ThreadLocalVariables` + :py:class:`lief.MachO.ThreadLocalVariables` + :cpp:class:`LIEF::MachO::ThreadLocalVariables` + +.. |lief-macho-threadlocalvariables-thunk| lief-api:: lief.MachO.ThreadLocalVariables.Thunk + + :rust:struct:`lief::macho::thread_local_variables::Thunk` + :py:class:`lief.MachO.ThreadLocalVariables.Thunk` + :cpp:class:`LIEF::MachO::ThreadLocalVariables::Thunk` + +.. |lief-macho-subclient| lief-api:: lief.MachO.SubClient + + :rust:struct:`lief::macho::commands::SubClient` + :py:class:`lief.MachO.SubClient` + :cpp:class:`LIEF::MachO::SubClient` + +.. |lief-macho-routine| lief-api:: lief.MachO.Routine + + :rust:struct:`lief::macho::commands::Routine` + :py:class:`lief.MachO.Routine` + :cpp:class:`LIEF::MachO::Routine` + +.. |lief-macho-dyldinfo| lief-api:: lief.MachO.DyldInfo + + :rust:struct:`lief::macho::commands::DyldInfo` + :py:class:`lief.MachO.DyldInfo` + :cpp:class:`LIEF::MachO::DyldInfo` + +.. |lief-macho-chainedbindinginfo| lief-api:: lief.MachO.ChainedBindingInfo + + :rust:struct:`lief::macho::binding_info::Chained` + :py:class:`lief.MachO.ChainedBindingInfo` + :cpp:class:`LIEF::MachO::ChainedBindingInfo` + +.. |lief-macho-indirectbindinginfo| lief-api:: lief.MachO.IndirectBindingInfo + + :rust:struct:`lief::macho::binding_info::Indirect` + :py:class:`lief.MachO.IndirectBindingInfo` + :cpp:class:`LIEF::MachO::IndirectBindingInfo` + +.. |lief-macho-dynamicsymbolcommand| lief-api:: lief.MachO.DynamicSymbolCommand + + :rust:struct:`lief::macho::commands::DynamicSymbolCommand` + :py:class:`lief.MachO.DynamicSymbolCommand` + :cpp:class:`LIEF::MachO::DynamicSymbolCommand` + +.. |lief-macho-binary-bindings| lief-api:: lief.MachO.Binary.bindings() + + :rust:method:`lief::macho::Binary::bindings [struct]` + :py:attr:`lief.MachO.Binary.bindings` + :cpp:func:`LIEF::MachO::Binary::bindings` + +.. |lief-macho-symbol-demangled_name| lief-api:: lief.MachO.Symbol.demangled_name() + + :rust:method:`lief::macho::Symbol::demangled_name [struct]` + :py:attr:`lief.MachO.Symbol.demangled_name` + :cpp:func:`LIEF::MachO::Symbol::demangled_name` + +.. |lief-macho-parse| lief-api:: lief.MachO.parse() + + :rust:method:`lief::macho::FatBinary::parse [struct]` + :py:func:`lief.MachO.parse` + :cpp:func:`LIEF::MachO::Parser::parse` + +.. |lief-macho-parse_from_dump| lief-api:: lief.MachO.parse_from_dump() + + :rust:method:`lief::macho::FatBinary::parse_from_dump [struct]` + :py:func:`lief.MachO.parse_from_dump` + :cpp:func:`LIEF::MachO::Parser::parse_from_dump` + +.. |lief-macho-fatbinary| lief-api:: lief.MachO.FatBinary + + :rust:struct:`lief::macho::FatBinary` + :py:class:`lief.MachO.FatBinary` + :cpp:class:`LIEF::MachO::FatBinary` + +.. |lief-macho-binary-write| lief-api:: lief.MachO.Binary.write() + + :rust:method:`lief::macho::Binary::write [struct]` + :rust:method:`lief::macho::Binary::write_with_config [struct]` + :py:meth:`lief.MachO.Binary.write` + :cpp:func:`LIEF::MachO::Binary::write` + +.. |lief-macho-binary-write_to_bytes| lief-api:: lief.MachO.Binary.write_to_bytes() + + :rust:method:`lief::macho::Binary::write_to_bytes [struct]` + :rust:method:`lief::macho::Binary::write_to_bytes_with_config [struct]` + :py:meth:`lief.MachO.Binary.write_to_bytes` + :cpp:func:`std::unique_ptr LIEF::MachO::Binary::write(std::ostream &)` + :cpp:func:`std::unique_ptr LIEF::MachO::Binary::write(std::ostream &, const Builder::config_t &)` + + +.. |lief-macho-fatbinary-create| lief-api:: lief.MachO.FatBinary.create() + + :py:meth:`lief.MachO.FatBinary.create` + :cpp:func:`LIEF::MachO::FatBinary::create` + +.. |lief-macho-fatbinary-write| lief-api:: lief.MachO.FatBinary.write() + + :py:meth:`lief.FatBinary.Binary.write` + :cpp:func:`LIEF::FatBinary::Binary::write` + +.. |lief-macho-parser-config| lief-api:: lief.MachO.ParserConfig + + :py:class:`lief.MachO.ParserConfig` + :cpp:class:`LIEF::MachO::ParserConfig` + +.. |lief-macho-builder-config| lief-api:: lief.MachO.Builder.config_t + + :rust:struct:`lief::pe::builder::Config` + :py:class:`lief.MachO.Builder.config_t` + :cpp:class:`LIEF::MachO::Builder::config_t` + +.. |lief-macho-atom-info| lief-api:: lief.MachO.AtomInfo + + :rust:struct:`lief::macho::commands::AtomInfo` + :py:class:`lief.MachO.AtomInfo` + :cpp:class:`LIEF::MachO::AtomInfo` + +.. |lief-macho-encryptioninfo| lief-api:: lief.MachO.EncryptionInfo + + :rust:struct:`lief::macho::commands::EncryptionInfo` + :py:class:`lief.MachO.EncryptionInfo` + :cpp:class:`LIEF::MachO::EncryptionInfo` + +.. |lief-macho-binary-find_library| lief-api:: lief.MachO.Binary.find_library() + + :rust:method:`lief::macho::Binary::find_library [struct]` + :py:meth:`lief.MachO.Binary.find_library` + :cpp:func:`LIEF::MachO::Binary::find_library` + +.. |lief-macho-rpath| lief-api:: lief.MachO.RPathCommand + + :rust:struct:`lief::macho::commands::RPath` + :py:class:`lief.MachO.RPathCommand` + :cpp:class:`LIEF::MachO::RPathCommand` + +.. |lief-macho-note-command| lief-api:: lief.MachO.Note + + :rust:struct:`lief::macho::commands::Note` + :py:class:`lief.MachO.NoteCommand` + :cpp:class:`LIEF::MachO::NoteCommand` + +.. |lief-macho-function-variants-command| lief-api:: lief.MachO.FunctionVariants + + :rust:struct:`lief::macho::commands::FunctionVariants` + :py:class:`lief.MachO.FunctionVariants` + :cpp:class:`LIEF::MachO::FunctionVariants` + +.. |lief-macho-function-variant-fixups-command| lief-api:: lief.MachO.FunctionVariantFixups + + :rust:struct:`lief::macho::commands::FunctionVariantFixups` + :py:class:`lief.MachO.FunctionVariantFixups` + :cpp:class:`LIEF::MachO::FunctionVariantFixups` + +.. |lief-macho-lazy-load-dylib-info-command| lief-api:: lief.MachO.LazyLoadDylibInfo + + :rust:struct:`lief::macho::commands::LazyLoadDylibInfo` + :py:class:`lief.MachO.LazyLoadDylibInfo` + :cpp:class:`LIEF::MachO::LazyLoadDylibInfo` + +.. dyld shared cache =========================================================== + +.. |lief-dsc-load| lief-api:: lief.dsc.load() + + :rust:func:`lief::dsc::load_from_path` + :rust:func:`lief::dsc::load_from_files` + :py:func:`lief.dsc.load` + :cpp:func:`LIEF::dsc::load` + +.. |lief-dsc-dyldsharedcache| lief-api:: lief.dsc.DyldSharedCache + + :rust:struct:`lief::dsc::DyldSharedCache` + :py:class:`lief.dsc.DyldSharedCache` + :cpp:class:`LIEF::dsc::DyldSharedCache` + +.. |lief-dsc-dyldsharedcache-disassemble| lief-api:: lief.dsc.DyldSharedCache.disassemble() + + :rust:method:`lief::dsc::DyldSharedCache::disassemble [struct]` + :py:meth:`lief.dsc.DyldSharedCache.disassemble` + :cpp:func:`LIEF::dsc::DyldSharedCache::disassemble` + +.. |lief-dsc-dyldsharedcache-libraries| lief-api:: lief.dsc.DyldSharedCache.libraries() + + :rust:method:`lief::dsc::DyldSharedCache::libraries [struct]` + :py:attr:`lief.dsc.DyldSharedCache.libraries` + :cpp:func:`LIEF::dsc::DyldSharedCache::libraries` + +.. |lief-dsc-dylib| lief-api:: lief.dsc.Dylib + + :rust:struct:`lief::dsc::Dylib` + :py:class:`lief.dsc.Dylib` + :cpp:class:`LIEF::dsc::Dylib` + +.. |lief-dsc-dylib-eopt| lief-api:: lief.dsc.Dylib.extract_opt_t + + :rust:struct:`lief::dsc::dylib::ExtractOpt` + :py:class:`lief.dsc.Dylib.extract_opt_t` + :cpp:struct:`LIEF::dsc::Dylib::extract_opt_t` + +.. |lief-dsc-dylib-eopt-fix_branches| lief-api:: lief.dsc.Dylib.extract_opt_t.fix_branches + + :rust:member:`lief::dsc::dylib::ExtractOpt::fix_branches [struct]` + :py:attr:`lief.dsc.Dylib.extract_opt_t.fix_branches` + :cpp:member:`LIEF::dsc::Dylib::extract_opt_t::fix_branches` + +.. |lief-dsc-enable_cache| lief-api:: lief.dsc.enable_cache() + + :rust:func:`lief::dsc::enable_cache` + :py:func:`lief.dsc.enable_cache` + :cpp:func:`LIEF::dsc::enable_cache` + +.. |lief-dsc-dylib-get| lief-api:: lief.dsc.Dylib.get() + + :rust:method:`lief::dsc::Dylib::get [struct]` + :py:meth:`lief.dsc.Dylib.get` + :cpp:func:`LIEF::dsc::Dylib::get` + +.. |lief-dsc-dyldsharedcache-enable_caching| lief-api:: lief.dsc.DyldSharedCache.enable_caching + + :rust:method:`lief::dsc::DyldSharedCache::enable_caching [struct]` + :py:meth:`lief.dsc.DyldSharedCache.enable_caching` + :cpp:func:`LIEF::dsc::DyldSharedCache::enable_caching` + +.. extended utils ============================================================= + +.. |lief-is-extended| lief-api:: lief.__extended__ + + :rust:func:`lief::is_extended` + :py:data:`lief._lief.__extended__` + :cpp:func:`LIEF::is_extended` + +.. |lief-extended-version-info| lief-api:: lief.extended_version_info() + + :rust:func:`lief::extended_version_info` + :cpp:func:`LIEF::extended_version_info` + +.. assembly ==================================================================== + +.. |lief-disassemble| lief-api:: lief.Binary.disassemble() + + :rust:method:`lief::generic::Binary::disassemble [trait]` + :rust:method:`lief::generic::Binary::disassemble_symbol [trait]` + :rust:method:`lief::generic::Binary::disassemble_address [trait]` + :rust:method:`lief::generic::Binary::disassemble_slice [trait]` + :cpp:func:`LIEF::Binary::disassemble` + :py:meth:`lief.Binary.disassemble` + :py:meth:`lief.Binary.disassemble_from_bytes` + +.. |lief-assemble| lief-api:: lief.Binary.assemble() + + :rust:method:`lief::generic::Binary::assemble [trait]` + :cpp:func:`LIEF::Binary::assemble` + :py:meth:`lief.Binary.assemble` + +.. |lief-asm-instruction| lief-api:: lief.assembly.Instruction + + :rust:enum:`lief::assembly::Instructions` + :cpp:class:`LIEF::assembly::Instruction` + :py:class:`lief.assembly.Instruction` + +.. |lief-asm-instruction-as| lief-api:: LIEF::assembly::Instruction::as() + + :cpp:func:`LIEF::assembly::Instruction::as` + +.. |lief-asm-x86-instruction| lief-api:: lief.assembly.x86.Instruction + + :rust:struct:`lief::assembly::x86::Instruction` + :cpp:class:`LIEF::assembly::x86::Instruction` + :py:class:`lief.assembly.x86.Instruction` + +.. |lief-asm-arm-instruction| lief-api:: lief.assembly.arm.Instruction + + :rust:struct:`lief::assembly::arm::Instruction` + :cpp:class:`LIEF::assembly::arm::Instruction` + :py:class:`lief.assembly.arm.Instruction` + +.. |lief-asm-aarch64-instruction| lief-api:: lief.assembly.aarch64.Instruction + + :rust:struct:`lief::assembly::aarch64::Instruction` + :cpp:class:`LIEF::assembly::aarch64::Instruction` + :py:class:`lief.assembly.aarch64.Instruction` + +.. |lief-asm-powerpc-instruction| lief-api:: lief.assembly.powerpc.Instruction + + :rust:struct:`lief::assembly::powerpc::Instruction` + :cpp:class:`LIEF::assembly::powerpc::Instruction` + :py:class:`lief.assembly.powerpc.Instruction` + +.. |lief-asm-mips-instruction| lief-api:: lief.assembly.mips.Instruction + + :rust:struct:`lief::assembly::mips::Instruction` + :cpp:class:`LIEF::assembly::mips::Instruction` + :py:class:`lief.assembly.mips.Instruction` + +.. |lief-asm-riscv-instruction| lief-api:: lief.assembly.riscv.Instruction + + :rust:struct:`lief::assembly::riscv::Instruction` + :cpp:class:`LIEF::assembly::riscv::Instruction` + :py:class:`lief.assembly.riscv.Instruction` + +.. |lief-asm-ebpf-instruction| lief-api:: lief.assembly.ebpf.Instruction + + :rust:struct:`lief::assembly::ebpf::Instruction` + :cpp:class:`LIEF::assembly::ebpf::Instruction` + :py:class:`lief.assembly.ebpf.Instruction` + + +.. |lief-asm-AssemblerConfig| lief-api:: lief.assembly.AssemblerConfig + + :rust:struct:`lief::assembly::AssemblerConfig` + :cpp:class:`LIEF::assembly::AssemblerConfig` + :py:class:`lief.assembly.AssemblerConfig` + +.. COFF Format ================================================================ + +.. |lief-coff-parse| lief-api:: lief.COFF.parse() + + :rust:method:`lief::coff::Binary::parse [struct]` + :py:func:`lief.COFF.parse` + :cpp:func:`LIEF::COFF::Parser::parse` + +.. |lief-coff-section-coff_string| lief-api:: lief.COFF.Section.coff_string + + :rust:method:`lief::coff::Section::coff_string [struct]` + :py:attr:`lief.COFF.Section.coff_string` + :cpp:func:`LIEF::COFF::Section::coff_string` + +.. |lief-coff-Binary| lief-api:: lief.COFF.Binary + + :rust:struct:`lief::coff::Binary` + :py:class:`lief.COFF.Binary` + :cpp:class:`LIEF::COFF::Binary` + +.. |lief-coff-binary-disassemble| lief-api:: lief.COFF.Binary.disassemble() + + :rust:method:`lief::coff::Binary::disassemble_slice [struct]` + :rust:method:`lief::coff::Binary::disassemble_function [struct]` + :rust:method:`lief::coff::Binary::disassemble_symbol [struct]` + :py:meth:`lief.COFF.Binary.disassemble` + :py:meth:`lief.COFF.Binary.disassemble_from_bytes` + :cpp:func:`LIEF::COFF::Binary::disassemble` + +.. |lief-coff-binary-get_section| lief-api:: lief.COFF.Binary.get_section() + + :rust:method:`lief::coff::Binary::section_by_name [struct]` + :py:meth:`lief.COFF.Binary.get_section` + :cpp:func:`LIEF::COFF::Binary::get_section` + +.. |lief-elf-DynamicEntryAuxiliary| lief-api:: lief.ELF.DynamicEntryAuxiliary + + :py:class:`lief.ELF.DynamicEntryAuxiliary` + :cpp:class:`LIEF::ELF::DynamicEntryAuxiliary` + :rust:struct:`lief::elf::dynamic::Auxiliary` + +.. |lief-elf-DynamicEntryFilter| lief-api:: lief.ELF.DynamicEntryFilter + + :py:class:`lief.ELF.DynamicEntryFilter` + :cpp:class:`LIEF::ELF::DynamicEntryFilter` + :rust:struct:`lief::elf::dynamic::Filter` + +.. |lief-pe-check_layout| lief-api:: lief.PE.check_layout() + + :py:func:`lief.PE.check_layout` + :cpp:func:`LIEF::PE::check_layout` + :rust:func:`lief::pe::check_layout` + +.. |lief-macho-check_layout| lief-api:: lief.MachO.check_layout() + + :py:func:`lief.MachO.check_layout` + :cpp:func:`LIEF::MachO::check_layout` + :rust:func:`lief::macho::check_layout` + :rust:func:`lief::macho::check_fat_layout` + +.. |lief-elf-check_layout| lief-api:: lief.ELF.check_layout() + + :py:func:`lief.ELF.check_layout` + :cpp:func:`LIEF::ELF::check_layout` + :rust:func:`lief::elf::check_layout` + +.. |lief-assembly-mips-Instruction-operands| lief-api:: lief.assembly.mips.Instruction.operands() + + :rust:method:`lief::assembly::mips::Instruction::operands [struct]` + :py:attr:`lief.assembly.mips.Instruction.operands` + :cpp:func:`LIEF::assembly::mips::Instruction::operands` + +.. |lief-assembly-powerpc-Instruction-operands| lief-api:: lief.assembly.powerpc.Instruction.operands() + + :rust:method:`lief::assembly::powerpc::Instruction::operands [struct]` + :py:attr:`lief.assembly.powerpc.Instruction.operands` + :cpp:func:`LIEF::assembly::powerpc::Instruction::operands` + +.. |lief-assembly-ebpf-Instruction-operands| lief-api:: lief.assembly.ebpf.Instruction.operands() + + :rust:method:`lief::assembly::ebpf::Instruction::operands [struct]` + :py:attr:`lief.assembly.ebpf.Instruction.operands` + :cpp:func:`LIEF::assembly::ebpf::Instruction::operands` + +.. |lief-assembly-riscv-Instruction-operands| lief-api:: lief.assembly.riscv.Instruction.operands() + + :rust:method:`lief::assembly::riscv::Instruction::operands [struct]` + :py:attr:`lief.assembly.riscv.Instruction.operands` + :cpp:func:`LIEF::assembly::riscv::Instruction::operands` + +.. |lief-assembly-x86-Instruction-has_lock_prefix| lief-api:: lief.assembly.x86.Instruction.has_lock_prefix() + + :rust:method:`lief::assembly::x86::Instruction::has_lock_prefix [struct]` + :py:attr:`lief.assembly.x86.Instruction.has_lock_prefix` + :cpp:func:`LIEF::assembly::x86::Instruction::has_lock_prefix` + +.. |lief-assembly-x86-Instruction-is_lockable| lief-api:: lief.assembly.x86.Instruction.is_lockable() + + :rust:method:`lief::assembly::x86::Instruction::is_lockable [struct]` + :py:attr:`lief.assembly.x86.Instruction.is_lockable` + :cpp:func:`LIEF::assembly::x86::Instruction::is_lockable` + +.. |lief-assembly-x86-Instruction-is_atomic| lief-api:: lief.assembly.x86.Instruction.is_atomic() + + :rust:method:`lief::assembly::x86::Instruction::is_atomic [struct]` + :py:attr:`lief.assembly.x86.Instruction.is_atomic` + :cpp:func:`LIEF::assembly::x86::Instruction::is_atomic` + +.. |lief-assembly-x86-Instruction-lock| lief-api:: lief.assembly.x86.Instruction.lock() + + :rust:method:`lief::assembly::x86::Instruction::lock [struct]` + :py:meth:`lief.assembly.x86.Instruction.lock` + :cpp:func:`LIEF::assembly::x86::Instruction::lock` + +.. |lief-assembly-x86-Instruction-unlock| lief-api:: lief.assembly.x86.Instruction.unlock() + + :rust:method:`lief::assembly::x86::Instruction::unlock [struct]` + :py:meth:`lief.assembly.x86.Instruction.unlock` + :cpp:func:`LIEF::assembly::x86::Instruction::unlock` + +.. Runtime ==================================================================== + +.. |lief-runtime-enabled| lief-api:: lief.runtime.enabled + + :rust:func:`lief::runtime::enabled` + :py:attr:`lief.runtime.enabled` + :cpp:func:`LIEF::runtime::is_enabled` + +.. |lief-runtime-platform| lief-api:: lief.runtime.platform + + :rust:func:`lief::runtime::platform` + :py:attr:`lief.runtime.platform` + :cpp:func:`LIEF::runtime::platform` + +.. |lief-runtime-arch| lief-api:: lief.runtime.arch + + :rust:func:`lief::runtime::arch` + :py:attr:`lief.runtime.arch` + :cpp:func:`LIEF::runtime::arch` + +.. |lief-runtime-host| lief-api:: lief.runtime.Host + + :rust:struct:`lief::runtime::Host` + :py:class:`lief.runtime.Host` + :cpp:class:`LIEF::runtime::Host` + +.. |lief-runtime-assemble| lief-api:: lief.runtime.assemble() + + :rust:func:`lief::runtime::assemble` + :rust:func:`lief::runtime::assemble_with_config` + :py:func:`lief.runtime.assemble` + :cpp:func:`LIEF::runtime::assemble` + +.. |lief-runtime-disassemble| lief-api:: lief.runtime.disassemble() + + :rust:func:`lief::runtime::disassemble` + :py:func:`lief.runtime.disassemble` + :cpp:func:`LIEF::runtime::disassemble` + +.. |lief-runtime-process| lief-api:: lief.runtime.Process + + :rust:struct:`lief::runtime::Process` + :py:class:`lief.runtime.Process` + :cpp:class:`LIEF::runtime::Process` + +.. |lief-runtime-linux-host| lief-api:: lief.runtime.linux.Host + + :rust:struct:`lief::runtime::linux::Host` + :py:class:`lief.runtime.linux.Host` + :cpp:class:`LIEF::runtime::Linux::Host` + +.. |lief-runtime-linux-host-sys_name| lief-api:: lief.runtime.linux.Host.sys_name() + + :rust:method:`lief::runtime::linux::Host::sys_name [struct]` + :py:attr:`lief.runtime.linux.Host.sys_name` + :cpp:func:`LIEF::runtime::Linux::Host::sys_name` + +.. |lief-runtime-linux-host-sys_release| lief-api:: lief.runtime.linux.Host.sys_release() + + :rust:method:`lief::runtime::linux::Host::sys_release [struct]` + :py:attr:`lief.runtime.linux.Host.sys_release` + :cpp:func:`LIEF::runtime::Linux::Host::sys_release` + +.. |lief-runtime-linux-host-sys_version| lief-api:: lief.runtime.linux.Host.sys_version() + + :rust:method:`lief::runtime::linux::Host::sys_version [struct]` + :py:attr:`lief.runtime.linux.Host.sys_version` + :cpp:func:`LIEF::runtime::Linux::Host::sys_version` + +.. |lief-runtime-linux-host-hardware| lief-api:: lief.runtime.linux.Host.hardware() + + :rust:method:`lief::runtime::linux::Host::hardware [struct]` + :py:attr:`lief.runtime.linux.Host.hardware` + :cpp:func:`LIEF::runtime::Linux::Host::hardware` + +.. |lief-runtime-linux-process| lief-api:: lief.runtime.linux.Process + + :rust:struct:`lief::runtime::linux::Process` + :py:class:`lief.runtime.linux.Process` + :cpp:class:`LIEF::runtime::Linux::Process` + +.. |lief-runtime-linux-process-glibc_version| lief-api:: lief.runtime.linux.Process.glibc_version() + + :rust:method:`lief::runtime::linux::Process::glibc_version [struct]` + :py:attr:`lief.runtime.linux.Process.glibc_version` + :cpp:func:`LIEF::runtime::Linux::Process::glibc_version` + +.. |lief-runtime-memory| lief-api:: lief.runtime.Memory + + :rust:struct:`lief::runtime::Memory` + :py:class:`lief.runtime.Memory` + :cpp:class:`LIEF::runtime::Memory` + +.. |lief-runtime-memory-mmap_hint| lief-api:: lief.runtime.Memory.mmap_hint() + + :rust:method:`lief::runtime::Memory::mmap_hint [struct]` + :py:meth:`lief.runtime.Memory.mmap_hint` + :cpp:func:`LIEF::runtime::Memory::mmap_hint` + +.. |lief-runtime-memory-chunk| lief-api:: lief.runtime.Memory.Chunk + + :rust:struct:`lief::runtime::memory::Chunk` + :py:class:`lief.runtime.Memory.Chunk` + :cpp:class:`LIEF::runtime::Memory::Chunk` + +.. |lief-runtime-memory-chunk-deallocate| lief-api:: lief.runtime.Memory.Chunk.deallocate() + + :rust:method:`lief::runtime::memory::Chunk::deallocate [struct]` + :py:meth:`lief.runtime.Memory.Chunk.deallocate` + :cpp:func:`LIEF::runtime::Memory::Chunk::deallocate` + +.. |lief-runtime-memory-chunk-cache_flush| lief-api:: lief.runtime.Memory.Chunk.cache_flush() + + :rust:method:`lief::runtime::memory::Chunk::cache_flush [struct]` + :py:meth:`lief.runtime.Memory.Chunk.cache_flush` + :cpp:func:`LIEF::runtime::Memory::Chunk::cache_flush` + +.. |lief-runtime-memorylayout| lief-api:: lief.runtime.MemoryLayout + + :py:class:`lief.runtime.MemoryLayout` + :cpp:class:`LIEF::runtime::MemoryLayout` + +.. |lief-runtime-memorylayout-region| lief-api:: lief.runtime.MemoryLayout.Region + + :rust:struct:`lief::runtime::Region` + :py:class:`lief.runtime.MemoryLayout.Region` + :cpp:class:`LIEF::runtime::MemoryLayout::Region` + +.. |lief-runtime-memory_layout| lief-api:: lief.runtime.memory_layout() + + :rust:func:`lief::runtime::memory_layout` + :py:func:`lief.runtime.memory_layout` + :cpp:func:`LIEF::runtime::memory_layout` + +.. |lief-runtime-module| lief-api:: lief.runtime.Module + + :rust:trait:`lief::runtime::module::Module` + :py:class:`lief.runtime.Module` + :cpp:class:`LIEF::runtime::Module` + +.. |lief-runtime-module-dump| lief-api:: lief.runtime.Module.dump() + + :rust:method:`lief::runtime::module::Module::dump [trait]` + :py:meth:`lief.runtime.Module.dump` + :cpp:func:`LIEF::runtime::Module::dump` + +.. |lief-runtime-module_from_name| lief-api:: lief.runtime.module_from_name() + + :rust:func:`lief::runtime::module_from_name` + :py:func:`lief.runtime.module_from_name` + :cpp:func:`LIEF::runtime::module_from_name` + +.. |lief-runtime-module_from_path| lief-api:: lief.runtime.module_from_path() + + :rust:func:`lief::runtime::module_from_path` + :py:func:`lief.runtime.module_from_path` + :cpp:func:`LIEF::runtime::module_from_path` + +.. |lief-runtime-module_from_addr| lief-api:: lief.runtime.module_from_addr() + + :rust:func:`lief::runtime::module_from_addr` + :py:func:`lief.runtime.module_from_addr` + :cpp:func:`LIEF::runtime::module_from_addr` + +.. |lief-runtime-linux-module| lief-api:: lief.runtime.linux.Module + + :rust:struct:`lief::runtime::linux::Module` + :py:class:`lief.runtime.linux.Module` + :cpp:class:`LIEF::runtime::Linux::Module` + +.. |lief-runtime-linux-dlopen| lief-api:: lief.runtime.linux.dlopen() + + :rust:func:`lief::runtime::linux::dlopen` + :py:func:`lief.runtime.linux.dlopen` + :cpp:func:`LIEF::runtime::Linux::dlopen` + +.. |lief-runtime-linux-module-dlsym| lief-api:: lief.runtime.linux.Module.dlsym() + + :rust:method:`lief::runtime::linux::Module::dlsym [struct]` + :py:meth:`lief.runtime.linux.Module.dlsym` + :cpp:func:`LIEF::runtime::Linux::Module::dlsym` + +.. |lief-runtime-windows-module| lief-api:: lief.runtime.windows.Module + + :rust:struct:`lief::runtime::windows::Module` + :py:class:`lief.runtime.windows.Module` + :cpp:class:`LIEF::runtime::windows::Module` + +.. |lief-runtime-windows-process| lief-api:: lief.runtime.windows.Process + + :rust:struct:`lief::runtime::windows::Process` + :py:class:`lief.runtime.windows.Process` + :cpp:class:`LIEF::runtime::windows::Process` + +.. |lief-runtime-windows-peb| lief-api:: lief.runtime.windows.PEB + + :rust:struct:`lief::runtime::windows::PEB` + :py:class:`lief.runtime.windows.PEB` + :cpp:class:`LIEF::runtime::windows::PEB` + + +.. |lief-runtime-windows-peb-entries| lief-api:: lief.runtime.windows.PEB.entries + + :rust:method:`lief::runtime::windows::PEB::entries [struct]` + :py:attr:`lief.runtime.windows.PEB.entries` + :cpp:func:`LIEF::runtime::windows::PEB::entries` + +.. |lief-runtime-windows-ldr| lief-api:: lief.runtime.windows.LdrDataTableEntry + + :rust:struct:`lief::runtime::windows::LdrDataTableEntry` + :py:class:`lief.runtime.windows.LdrDataTableEntry` + :cpp:class:`LIEF::runtime::windows::LdrDataTableEntry` + +.. |lief-runtime-windows-host| lief-api:: lief.runtime.windows.Host + + :rust:struct:`lief::runtime::windows::Host` + :py:class:`lief.runtime.windows.Host` + :cpp:class:`LIEF::runtime::windows::Host` + +.. |lief-runtime-windows-host-version| lief-api:: lief.runtime.windows.Host.version() + + :rust:method:`lief::runtime::windows::Host::version [struct]` + :py:attr:`lief.runtime.windows.Host.version` + :cpp:func:`LIEF::runtime::windows::Host::version` + +.. |lief-runtime-osx-module| lief-api:: lief.runtime.osx.Module + + :rust:struct:`lief::runtime::osx::Module` + :py:class:`lief.runtime.osx.Module` + :cpp:class:`LIEF::runtime::osx::Module` + +.. |lief-runtime-osx-host| lief-api:: lief.runtime.osx.Host + + :rust:struct:`lief::runtime::osx::Host` + :py:class:`lief.runtime.osx.Host` + :cpp:class:`LIEF::runtime::osx::Host` + +.. |lief-runtime-osx-host-os_version_name| lief-api:: lief.runtime.osx.Host.os_version_name() + + :rust:method:`lief::runtime::osx::Host::os_version_name [struct]` + :py:attr:`lief.runtime.osx.Host.os_version_name` + :cpp:func:`LIEF::runtime::osx::Host::os_version_name` + +.. |lief-runtime-osx-host-is-sip-enabled| lief-api:: lief.runtime.osx.Host.is_sip_enabled + + :rust:method:`lief::runtime::osx::Host::is_sip_enabled [struct]` + :py:attr:`lief.runtime.osx.Host.is_sip_enabled` + :cpp:func:`LIEF::runtime::osx::Host::is_sip_enabled` + +.. |lief-runtime-osx-process| lief-api:: lief.runtime.osx.Process + + :rust:struct:`lief::runtime::osx::Process` + :py:class:`lief.runtime.osx.Process` + :cpp:class:`LIEF::runtime::osx::Process` + +.. |lief-runtime-osx-process-dyld_version| lief-api:: lief.runtime.osx.Process.dyld_version() + + :rust:method:`lief::runtime::osx::Process::dyld_version [struct]` + :py:attr:`lief.runtime.osx.Process.dyld_version` + :cpp:func:`LIEF::runtime::osx::Process::dyld_version` + +.. |lief-runtime-android-host| lief-api:: lief.runtime.android.Host + + :rust:struct:`lief::runtime::android::Host` + :py:class:`lief.runtime.android.Host` + :cpp:class:`LIEF::runtime::android::Host` + +.. |lief-runtime-android-host-sdk_version| lief-api:: lief.runtime.android.Host.sdk_version() + + :rust:method:`lief::runtime::android::Host::sdk_version [struct]` + :py:attr:`lief.runtime.android.Host.sdk_version` + :cpp:func:`LIEF::runtime::android::Host::sdk_version` + +.. |lief-runtime-android-process| lief-api:: lief.runtime.android.Process + + :rust:struct:`lief::runtime::android::Process` + :py:class:`lief.runtime.android.Process` + :cpp:class:`LIEF::runtime::android::Process` + +.. |lief-runtime-android-process-get_system_property| lief-api:: lief.runtime.android.Process.get_system_property() + + :rust:method:`lief::runtime::android::Process::get_system_property [struct]` + :py:meth:`lief.runtime.android.Process.get_system_property` + :cpp:func:`LIEF::runtime::android::Process::get_system_property` + +.. |lief-runtime-android-process-properties| lief-api:: lief.runtime.android.Process.properties() + + :rust:method:`lief::runtime::android::Process::properties [struct]` + :py:attr:`lief.runtime.android.Process.properties` + :cpp:func:`LIEF::runtime::android::Process::properties` + +.. |lief-runtime-android-property| lief-api:: lief.runtime.android.Property + + :rust:struct:`lief::runtime::android::Property` + :py:class:`lief.runtime.android.Property` + :cpp:class:`LIEF::runtime::android::Property` + +.. |lief-runtime-android-module| lief-api:: lief.runtime.android.Module + + :rust:struct:`lief::runtime::android::Module` + :py:class:`lief.runtime.android.Module` + :cpp:class:`LIEF::runtime::android::Module` + +.. |lief-runtime-android-dlopen| lief-api:: lief.runtime.android.dlopen() + + :rust:func:`lief::runtime::android::dlopen` + :py:func:`lief.runtime.android.dlopen` + :cpp:func:`LIEF::runtime::android::dlopen` + +.. |lief-runtime-android-module-dlsym| lief-api:: lief.runtime.android.Module.dlsym() + + :rust:method:`lief::runtime::android::Module::dlsym [struct]` + :py:meth:`lief.runtime.android.Module.dlsym` + :cpp:func:`LIEF::runtime::android::Module::dlsym` +``` diff --git a/vendor/lief/doc/sphinx/_static/binaryninja/trigger-dwarf-plugin.webp b/vendor/lief/doc/sphinx/_static/binaryninja/trigger-dwarf-plugin.webp new file mode 100644 index 0000000..2d952e4 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/binaryninja/trigger-dwarf-plugin.webp differ diff --git a/vendor/lief/doc/sphinx/_static/cant-find-lib.png b/vendor/lief/doc/sphinx/_static/cant-find-lib.png new file mode 100644 index 0000000..6c238eb Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/cant-find-lib.png differ diff --git a/vendor/lief/doc/sphinx/_static/css/custom.css b/vendor/lief/doc/sphinx/_static/css/custom.css index 30abea5..16abfdb 100644 --- a/vendor/lief/doc/sphinx/_static/css/custom.css +++ b/vendor/lief/doc/sphinx/_static/css/custom.css @@ -3,6 +3,37 @@ max-height: 500px; } +html[data-theme="dark"] .highlight .hll { + margin-inline-start: -0.55rem; + padding-inline-start: 0.55rem; +} + +html[data-theme="light"] .docs-content dt.sig .property { + color: #007681; +} + .center { text-align: center; } + +.fixed-paragraph { + margin-top: 0; + margin-bottom: 1rem; +} + +li .fixed-paragraph { + margin-top: 0; + margin-bottom: 0rem; +} + +.align-default { + text-align: inherit; +} + +a.btn:visited { + color: #fff; +} + +.img-comparison-slider-div { + overflow-y: auto; +} diff --git a/vendor/lief/doc/sphinx/_static/elements.webp b/vendor/lief/doc/sphinx/_static/elements.webp new file mode 100644 index 0000000..437312f Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/elements.webp differ diff --git a/vendor/lief/doc/sphinx/_static/example.cpp b/vendor/lief/doc/sphinx/_static/example.cpp index 4addad1..d309b73 100644 --- a/vendor/lief/doc/sphinx/_static/example.cpp +++ b/vendor/lief/doc/sphinx/_static/example.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,12 +18,16 @@ class MyClass { public: - MyClass(void) : message_{"hello"} {}; - MyClass(const std::string& message) : message_{message} {}; - void say_hello(void) { std::cout << this->message_<< std::endl; } + MyClass(void) : + message_{"hello"} {} + MyClass(const std::string& message) : + message_{message} {} + void say_hello(void) { + std::cout << this->message_ << '\n'; + } private: - std::string message_; + std::string message_; }; diff --git a/vendor/lief/doc/sphinx/_static/ghidra/codebrowser-export-dwarf.webp b/vendor/lief/doc/sphinx/_static/ghidra/codebrowser-export-dwarf.webp new file mode 100644 index 0000000..7b82e31 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/ghidra/codebrowser-export-dwarf.webp differ diff --git a/vendor/lief/doc/sphinx/_static/ghidra/ghidra-check.png b/vendor/lief/doc/sphinx/_static/ghidra/ghidra-check.png new file mode 100644 index 0000000..6f1081e Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/ghidra/ghidra-check.png differ diff --git a/vendor/lief/doc/sphinx/_static/ghidra/project-dwarf-export.webp b/vendor/lief/doc/sphinx/_static/ghidra/project-dwarf-export.webp new file mode 100644 index 0000000..89ca20d Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/ghidra/project-dwarf-export.webp differ diff --git a/vendor/lief/doc/sphinx/_static/lief-extended-history-link.webp b/vendor/lief/doc/sphinx/_static/lief-extended-history-link.webp new file mode 100644 index 0000000..cef642f Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/lief-extended-history-link.webp differ diff --git a/vendor/lief/doc/sphinx/_static/lief-social.webp b/vendor/lief/doc/sphinx/_static/lief-social.webp new file mode 100644 index 0000000..f6260e3 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/lief-social.webp differ diff --git a/vendor/lief/doc/sphinx/_static/lief_with_bn.webp b/vendor/lief/doc/sphinx/_static/lief_with_bn.webp new file mode 100644 index 0000000..cac855c Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/lief_with_bn.webp differ diff --git a/vendor/lief/doc/sphinx/_static/lief_with_ghidra.webp b/vendor/lief/doc/sphinx/_static/lief_with_ghidra.webp new file mode 100644 index 0000000..d82ee8a Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/lief_with_ghidra.webp differ diff --git a/vendor/lief/doc/sphinx/_static/login.webp b/vendor/lief/doc/sphinx/_static/login.webp new file mode 100644 index 0000000..9884e66 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/login.webp differ diff --git a/vendor/lief/doc/sphinx/_static/macos-dylib-issue.png b/vendor/lief/doc/sphinx/_static/macos-dylib-issue.png new file mode 100644 index 0000000..63541f8 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/macos-dylib-issue.png differ diff --git a/vendor/lief/doc/sphinx/_static/main.webp b/vendor/lief/doc/sphinx/_static/main.webp new file mode 100644 index 0000000..2657edb Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/main.webp differ diff --git a/vendor/lief/doc/sphinx/_static/objc-class-dump.webp b/vendor/lief/doc/sphinx/_static/objc-class-dump.webp new file mode 100644 index 0000000..1bb5f32 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/objc-class-dump.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_debug/overview.webp b/vendor/lief/doc/sphinx/_static/pe_debug/overview.webp new file mode 100644 index 0000000..0558ae9 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_debug/overview.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_exports/overview.webp b/vendor/lief/doc/sphinx/_static/pe_exports/overview.webp new file mode 100644 index 0000000..6577ae1 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_exports/overview.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_imports/lief-mod.webp b/vendor/lief/doc/sphinx/_static/pe_imports/lief-mod.webp new file mode 100644 index 0000000..52f5904 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_imports/lief-mod.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_imports/llvm-link-layout.webp b/vendor/lief/doc/sphinx/_static/pe_imports/llvm-link-layout.webp new file mode 100644 index 0000000..f7695c8 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_imports/llvm-link-layout.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_imports/msvc_layout.webp b/vendor/lief/doc/sphinx/_static/pe_imports/msvc_layout.webp new file mode 100644 index 0000000..dfee0cb Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_imports/msvc_layout.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_rsrc/overview.webp b/vendor/lief/doc/sphinx/_static/pe_rsrc/overview.webp new file mode 100644 index 0000000..b697a24 Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_rsrc/overview.webp differ diff --git a/vendor/lief/doc/sphinx/_static/pe_tls/tls.webp b/vendor/lief/doc/sphinx/_static/pe_tls/tls.webp new file mode 100644 index 0000000..489bbfd Binary files /dev/null and b/vendor/lief/doc/sphinx/_static/pe_tls/tls.webp differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot.png b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot.png index 8fde6b7..ebdc982 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot.png and b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot2.png b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot2.png index 54a41b9..cc5ec19 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot2.png and b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot2.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot3.png b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot3.png index 92e2b99..26e5b9c 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot3.png and b/vendor/lief/doc/sphinx/_static/tutorial/05/pltgot3.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/07/07_pe_resource_manager.png b/vendor/lief/doc/sphinx/_static/tutorial/07/07_pe_resource_manager.png index 1a5d251..9f781cb 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/07/07_pe_resource_manager.png and b/vendor/lief/doc/sphinx/_static/tutorial/07/07_pe_resource_manager.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/07/07_resource_tree.png b/vendor/lief/doc/sphinx/_static/tutorial/07/07_resource_tree.png index 13cd288..c4e93c5 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/07/07_resource_tree.png and b/vendor/lief/doc/sphinx/_static/tutorial/07/07_resource_tree.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.pdf b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.pdf deleted file mode 100644 index 6962f1b..0000000 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.pdf and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.png b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.png index 3d848c1..f8f2344 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.png and b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_a.png differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.pdf b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.pdf deleted file mode 100644 index f767818..0000000 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.pdf and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.png b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.png index 504b1ab..ccca712 100644 Binary files a/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.png and b/vendor/lief/doc/sphinx/_static/tutorial/08/bin2lib_b.png differ diff --git a/vendor/lief/doc/sphinx/_static/windows_sdk/s1.png b/vendor/lief/doc/sphinx/_static/windows_sdk/s1.png deleted file mode 100644 index bd24d72..0000000 Binary files a/vendor/lief/doc/sphinx/_static/windows_sdk/s1.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/windows_sdk/s2.png b/vendor/lief/doc/sphinx/_static/windows_sdk/s2.png deleted file mode 100644 index adf73c2..0000000 Binary files a/vendor/lief/doc/sphinx/_static/windows_sdk/s2.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/windows_sdk/s3.png b/vendor/lief/doc/sphinx/_static/windows_sdk/s3.png deleted file mode 100644 index a01cc3c..0000000 Binary files a/vendor/lief/doc/sphinx/_static/windows_sdk/s3.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/windows_sdk/s4.png b/vendor/lief/doc/sphinx/_static/windows_sdk/s4.png deleted file mode 100644 index fe6ad67..0000000 Binary files a/vendor/lief/doc/sphinx/_static/windows_sdk/s4.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/windows_sdk/s5.png b/vendor/lief/doc/sphinx/_static/windows_sdk/s5.png deleted file mode 100644 index 164542f..0000000 Binary files a/vendor/lief/doc/sphinx/_static/windows_sdk/s5.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/code.png b/vendor/lief/doc/sphinx/_static/xcode_integration/code.png deleted file mode 100644 index 93993fc..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/code.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/result.png b/vendor/lief/doc/sphinx/_static/xcode_integration/result.png deleted file mode 100644 index 5dc614e..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/result.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step1.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step1.png deleted file mode 100644 index e4ce225..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step1.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step2.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step2.png deleted file mode 100644 index 10a6590..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step2.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step3.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step3.png deleted file mode 100644 index 8cbb1f2..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step3.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step4.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step4.png deleted file mode 100644 index cf7a2c9..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step4.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step5.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step5.png deleted file mode 100644 index d88fbb2..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step5.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step6.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step6.png deleted file mode 100644 index 5b1824a..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step6.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_static/xcode_integration/step7.png b/vendor/lief/doc/sphinx/_static/xcode_integration/step7.png deleted file mode 100644 index 013bd76..0000000 Binary files a/vendor/lief/doc/sphinx/_static/xcode_integration/step7.png and /dev/null differ diff --git a/vendor/lief/doc/sphinx/_templates/layout.html b/vendor/lief/doc/sphinx/_templates/layout.html new file mode 100644 index 0000000..b3f7d00 --- /dev/null +++ b/vendor/lief/doc/sphinx/_templates/layout.html @@ -0,0 +1,37 @@ +{% extends "!layout.html" %} + +{% block htmltitle %} + {% if seo_title %} + {{ seo_title|e }} + {% else %} + {{ super() }} + {% endif %} +{% endblock %} + +{% block extrahead %} + {{ super() }} + {% if seo_noindex %} + + {% endif %} + {% if canonical_url and seo_title and seo_description %} + + + + + + + + + + + + + + + + + {% endif %} + {% if seo_breadcrumb_json %} + + {% endif %} +{% endblock %} diff --git a/vendor/lief/doc/sphinx/ai.md b/vendor/lief/doc/sphinx/ai.md new file mode 100644 index 0000000..95b57dc --- /dev/null +++ b/vendor/lief/doc/sphinx/ai.md @@ -0,0 +1,64 @@ +--- +description: Read LIEF documentation as resolved Markdown or retrieve guides and API symbols from versioned JSON indexes with canonical links and content hashes. +--- + +# {fa}`fa-solid fa-robot` Documentation for AI + +Every documentation page has a Markdown copy at the same path with `.html` +replaced by `.md`. For example, `runtime/intro.html` has a `runtime/intro.md` +copy. The HTML page advertises this copy with an alternate link in its head, +following the [llms.txt proposal](https://llmstxt.org/). + +The Markdown contains the rendered documentation: code included from example +files, every language tab, API signatures, tables, and notes. Links and image +URLs are absolute, so content remains usable when read outside this website. +Section and API headings link to their original HTML anchors for citation. + +## Choose a resource + +These files are generated alongside each version of the documentation: + +| Resource | Use it to | +| --- | --- | +| [`llms.txt`](llms.txt) | Find the relevant guide or API page, with a description of each page | +| [`index.json`](index.json) | Search document titles, descriptions, and full text, then fetch a Markdown page | +| [`index.chunks.json`](index.chunks.json) | Retrieve individual sections or API symbols with their heading context and citation URLs | +| [`llms-full.txt`](llms-full.txt) | Download all Markdown pages, including API references, for local indexing | +| [`objects.inv`](objects.inv) | Look up documented symbols by name | +| [`sitemap.xml`](sitemap.xml) | Enumerate canonical HTML pages | + +Start with `llms.txt` and fetch the pages relevant to the task. The full corpus +includes large API references; it may exceed an assistant's context window. +The exported corpus covers the Sphinx documentation. The API guides also link +to the separate Rust and Doxygen references. + +## Match the documentation to the installation + +Markdown metadata and JSON records carry `documentationVersion`, +`documentationChannel`, `canonical`, and `markdownURL`. The `latest` channel +tracks development; `stable` tracks the latest release. Match API usage to the +installed LIEF version, platform, architecture, and enabled features. + +Use the {doc}`installation` guide to choose a build. Read {doc}`extended/intro` +for Extended features and {doc}`runtime/intro` for runtime availability. Basic +runtime support is an independent build option. Memory-layout enumeration, +assembly, and disassembly require Extended. + +## Retrieve and update chunks + +Both JSON indexes declare a `schemaVersion`. Each chunk contains Markdown and +plain text, its document title and description, a `headingPath`, and a `url` +pointing to the canonical HTML section or API symbol. Chunk sizes follow the +documentation structure; code blocks stay intact. + +`documentID` identifies a canonical page, including its version channel. +`chunkID` identifies a section within that page. These IDs remain stable across +builds when the page URL and section anchor stay the same. `position`, +`documentChunkCount`, `previousChunkID`, and `nextChunkID` allow retrieval of +surrounding context. Positions start at zero; neighbors are empty strings at +document boundaries. + +Compare the index's `corpusHash` to detect changes to content or metadata, then +compare individual `contentHash` values to find changed Markdown bodies. Both +use SHA-256. The chunk index describes the hash inputs and ordering. Build +timestamps are excluded so unchanged content produces the same indexes. diff --git a/vendor/lief/doc/sphinx/api/binary_abstraction/cpp.md b/vendor/lief/doc/sphinx/api/binary_abstraction/cpp.md new file mode 100644 index 0000000..44b7868 --- /dev/null +++ b/vendor/lief/doc/sphinx/api/binary_abstraction/cpp.md @@ -0,0 +1,55 @@ +# {fa}`regular fa-file-code` C++ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::Parser +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::Header +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::Binary +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. doxygenclass:: LIEF::Section +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. doxygenclass:: LIEF::Symbol +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. doxygenclass:: LIEF::Relocation +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. doxygenclass:: LIEF::Function +``` diff --git a/vendor/lief/doc/sphinx/api/binary_abstraction/index.md b/vendor/lief/doc/sphinx/api/binary_abstraction/index.md new file mode 100644 index 0000000..064601b --- /dev/null +++ b/vendor/lief/doc/sphinx/api/binary_abstraction/index.md @@ -0,0 +1,61 @@ +(binary-abstraction)= + +# {fa}`brands fa-uncharted` Binary Abstraction + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +{ref}`ELF `, {ref}`PE `, {ref}`Mach-O ` +binaries share similar characteristics, such as an entry point, imported/exported +functions, etc. + +These shared characteristics are represented in an *abstract* layer, which is +defined by an inheritance relationship in C++/Python and by a trait in Rust. + +Specifically, {sub-ref}`lief-elf-binary`, {sub-ref}`lief-pe-binary`, and {sub-ref}`lief-macho-binary` +either inherit or implement the trait: {sub-ref}`lief-abstract-binary`. + +In Python/C++, one can access an *abstract* binary object by using the generic +{sub-ref}`lief-abstract-parse` function: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/abstract.py", "parse") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/abstract.cpp", "parse") }} +::: +:::: + +Due to Python's dynamic polymorphism, the return value of +{py:func}`lief.parse` is automatically cast into either: +{class}`lief.ELF.Binary`, {class}`lief.PE.Binary`, or {class}`lief.MachO.Binary`. +To **upcast** this object into a {class}`lief.Binary` object, one can use the +{attr}`lief.Binary.abstract` attribute, which returns a {class}`lief.Binary` +instance: + +{{ literalinclude("../../../code/python/abstract.py", "upcast") }} + +In C++, a {cpp:class}`LIEF::Binary` instance can be **downcast** to its underlying +type using the `classof` idiom: + +{{ literalinclude("../../../code/cpp/abstract.cpp", "downcast") }} + +```{eval-rst} +.. seealso:: + + - :cpp:func:`LIEF::ELF::Binary::classof` + - :cpp:func:`LIEF::PE::Binary::classof` + - :cpp:func:`LIEF::MachO::Binary::classof` +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/api/binary_abstraction/python.md b/vendor/lief/doc/sphinx/api/binary_abstraction/python.md new file mode 100644 index 0000000..9168be1 --- /dev/null +++ b/vendor/lief/doc/sphinx/api/binary_abstraction/python.md @@ -0,0 +1,81 @@ +# {fa}`brands fa-python` Python + +## Parser + +```{eval-rst} +.. autofunction:: lief.parse +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. lief-inheritance:: lief._lief.Binary + :top-classes: lief._lief.Binary + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.Header +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. lief-inheritance:: lief._lief.Section + :top-classes: lief._lief.Section + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.Section +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. lief-inheritance:: lief._lief.Symbol + :top-classes: lief._lief.Symbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.Symbol + +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. lief-inheritance:: lief._lief.Relocation + :top-classes: lief._lief.Relocation + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.Relocation + +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. autoclass:: lief.Function +``` diff --git a/vendor/lief/doc/sphinx/api/binary_abstraction/rust.md b/vendor/lief/doc/sphinx/api/binary_abstraction/rust.md new file mode 100644 index 0000000..fb9da12 --- /dev/null +++ b/vendor/lief/doc/sphinx/api/binary_abstraction/rust.md @@ -0,0 +1,6 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check the module {rust:module}`lief::generic` which contains all the +abstracted traits +::: diff --git a/vendor/lief/doc/sphinx/api/c/elf.rst b/vendor/lief/doc/sphinx/api/c/elf.rst deleted file mode 100644 index 526484d..0000000 --- a/vendor/lief/doc/sphinx/api/c/elf.rst +++ /dev/null @@ -1,110 +0,0 @@ -ELF ---- - -.. doxygenfunction:: elf_parse - :project: lief - - -.. doxygenfunction:: elf_binary_destroy - :project: lief - - -.. doxygenfunction:: elf_binary_save_header - :project: lief - -Elf_Binary_t -************ - -.. doxygenstruct:: Elf_Binary_t - :project: lief - - ----------- - -Elf_Header_t -************ - -.. doxygenstruct:: Elf_Header_t - :project: lief - ----------- - -Elf_Section_t -************* - -.. doxygenstruct:: Elf_Section_t - :project: lief - ----------- - -Elf_Segment_t -************* - -.. doxygenstruct:: Elf_Segment_t - :project: lief - ----------- - -Dynamic Entries -*************** - -Elf_DynamicEntry_t -~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_t - :project: lief - ----------- - -Elf_DynamicEntry_Library_t -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_Library_t - :project: lief - ----------- - -Elf_DynamicEntry_SharedObject_t -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_SharedObject_t - :project: lief - ----------- - -Elf_DynamicEntry_Array_t -~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_Array_t - :project: lief - ----------- - -Elf_DynamicEntry_Rpath_t -~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_Rpath_t - :project: lief - ----------- - -Elf_DynamicEntry_RunPath_t -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_RunPath_t - :project: lief - ----------- - -Elf_DynamicEntry_Flags_t -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenstruct:: Elf_DynamicEntry_Flags_t - :project: lief - - -Utilities -********* - -.. doxygengroup:: elf_utils_c_api - :project: lief diff --git a/vendor/lief/doc/sphinx/api/c/index.rst b/vendor/lief/doc/sphinx/api/c/index.rst deleted file mode 100644 index 0757310..0000000 --- a/vendor/lief/doc/sphinx/api/c/index.rst +++ /dev/null @@ -1,18 +0,0 @@ - -.. _c-api-ref: - -C -== - -.. warning:: - - The LIEF C API is **very** limited compared to the Python API. - -.. toctree:: - :maxdepth: 2 - - elf.rst - pe.rst - macho.rst - logging.rst - diff --git a/vendor/lief/doc/sphinx/api/c/logging.rst b/vendor/lief/doc/sphinx/api/c/logging.rst deleted file mode 100644 index bd66966..0000000 --- a/vendor/lief/doc/sphinx/api/c/logging.rst +++ /dev/null @@ -1,12 +0,0 @@ -Logging -======= - -.. doxygenfunction:: lief_logging_disable - :project: lief - -.. doxygenfunction:: lief_logging_enable - :project: lief - -.. doxygenfunction:: lief_logging_set_level - :project: lief - diff --git a/vendor/lief/doc/sphinx/api/c/macho.rst b/vendor/lief/doc/sphinx/api/c/macho.rst deleted file mode 100644 index 80bb219..0000000 --- a/vendor/lief/doc/sphinx/api/c/macho.rst +++ /dev/null @@ -1,60 +0,0 @@ -MachO ------ - -.. doxygenfunction:: macho_parse - :project: lief - - -.. doxygenfunction:: macho_binaries_destroy - :project: lief - - -Macho_Binary_t -************** - -.. doxygenstruct:: Macho_Binary_t - :project: lief - - ----------- - -Macho_Header_t -************** - -.. doxygenstruct:: Macho_Header_t - :project: lief - ----------- - -Macho_Section_t -*************** - -.. doxygenstruct:: Macho_Section_t - :project: lief - ----------- - -Macho_Segment_t -*************** - -.. doxygenstruct:: Macho_Segment_t - :project: lief - - ----------- - -Macho_Command_t -*************** - -.. doxygenstruct:: Macho_Command_t - :project: lief - - ----------- - -Macho_Symbol_t -************** - -.. doxygenstruct:: Macho_Symbol_t - :project: lief - diff --git a/vendor/lief/doc/sphinx/api/c/pe.rst b/vendor/lief/doc/sphinx/api/c/pe.rst deleted file mode 100644 index f290141..0000000 --- a/vendor/lief/doc/sphinx/api/c/pe.rst +++ /dev/null @@ -1,78 +0,0 @@ -PE --- - - -.. doxygenfunction:: pe_parse - :project: lief - - -.. doxygenfunction:: pe_binary_destroy - :project: lief - -Pe_Binary_t -************ - -.. doxygenstruct:: Pe_Binary_t - :project: lief - - ----------- - -Pe_DosHeader_t -************** - -.. doxygenstruct:: Pe_DosHeader_t - :project: lief - ----------- - -Pe_Header_t -*********** - -.. doxygenstruct:: Pe_Header_t - :project: lief - ----------- - -Pe_OptionalHeader_t -******************* - -.. doxygenstruct:: Pe_OptionalHeader_t - :project: lief - - ----------- - -Pe_Section_t -************ - -.. doxygenstruct:: Pe_Section_t - :project: lief - - ----------- - -Pe_DataDirectory_t -****************** - -.. doxygenstruct:: Pe_DataDirectory_t - :project: lief - - ----------- - -Pe_Import_t -*********** - -.. doxygenstruct:: Pe_Import_t - :project: lief - - ----------- - -Pe_ImportEntry_t -**************** - -.. doxygenstruct:: Pe_ImportEntry_t - :project: lief - diff --git a/vendor/lief/doc/sphinx/api/cpp/abstract.rst b/vendor/lief/doc/sphinx/api/cpp/abstract.rst deleted file mode 100644 index 79ad003..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/abstract.rst +++ /dev/null @@ -1,80 +0,0 @@ -Abstract --------- - -Parser -******* - -.. doxygenclass:: LIEF::Parser - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::Header - :project: lief - ----------- - - -Binary -****** - -.. doxygenclass:: LIEF::Binary - :project: lief - ----------- - -Section -******* - -.. doxygenclass:: LIEF::Section - :project: lief - ----------- - -Symbol -****** - -.. doxygenclass:: LIEF::Symbol - :project: lief - - ----------- - -Relocation -********** - -.. doxygenclass:: LIEF::Relocation - :project: lief - ----------- - -Function -******** - -.. doxygenclass:: LIEF::Function - :project: lief - - -Enums -***** - -.. doxygenenum:: LIEF::EXE_FORMATS - :project: lief - -.. doxygenenum:: LIEF::OBJECT_TYPES - :project: lief - -.. doxygenenum:: LIEF::ARCHITECTURES - :project: lief - -.. doxygenenum:: LIEF::MODES - :project: lief - -.. doxygenenum:: LIEF::ENDIANNESS - :project: lief - - - diff --git a/vendor/lief/doc/sphinx/api/cpp/art.rst b/vendor/lief/doc/sphinx/api/cpp/art.rst deleted file mode 100644 index 1a22bb1..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/art.rst +++ /dev/null @@ -1,47 +0,0 @@ -ART ---- - -Utilities -********* - -.. doxygenfunction:: LIEF::ART::is_art(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::ART::is_art(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::ART::version(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::ART::version(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::ART::android_version - :project: lief - ----------- - -Parser -******* - -.. doxygenclass:: LIEF::ART::Parser - :project: lief - ----------- - - -File -**** - -.. doxygenclass:: LIEF::ART::File - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::ART::Header - :project: lief - - diff --git a/vendor/lief/doc/sphinx/api/cpp/dex.rst b/vendor/lief/doc/sphinx/api/cpp/dex.rst deleted file mode 100644 index ed0b711..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/dex.rst +++ /dev/null @@ -1,116 +0,0 @@ -DEX ---- - -Utilities -********* - -.. doxygenfunction:: LIEF::DEX::is_dex(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::DEX::is_dex(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::DEX::version(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::DEX::version(const std::vector&) - :project: lief - - ----------- - -Parser -******* - -.. doxygenclass:: LIEF::DEX::Parser - :project: lief - ----------- - - -File -**** - -.. doxygenclass:: LIEF::DEX::File - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::DEX::Header - :project: lief - ----------- - -Method -****** - -.. doxygenclass:: LIEF::DEX::Method - :project: lief - ----------- - -Class -***** - -.. doxygenclass:: LIEF::DEX::Class - :project: lief - ----------- - -Field -***** - -.. doxygenclass:: LIEF::DEX::Field - :project: lief - ----------- - -Code Info -********* - -.. doxygenclass:: LIEF::DEX::CodeInfo - :project: lief - ----------- - -Prototype -********* - -.. doxygenclass:: LIEF::DEX::Prototype - :project: lief - ----------- - -Type -**** - -.. doxygenclass:: LIEF::DEX::Type - :project: lief - ----------- - -MapList -******* - -.. doxygenclass:: LIEF::DEX::MapList - :project: lief - - ----------- - -MapItem -******* - -.. doxygenclass:: LIEF::DEX::MapItem - :project: lief - - - - - - - - diff --git a/vendor/lief/doc/sphinx/api/cpp/elf.rst b/vendor/lief/doc/sphinx/api/cpp/elf.rst deleted file mode 100644 index daaa976..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/elf.rst +++ /dev/null @@ -1,521 +0,0 @@ -ELF ---- - -Parser -******* - -.. doxygenclass:: LIEF::ELF::Parser - :project: lief - - - ----------- - - -Binary -****** - -.. doxygenclass:: LIEF::ELF::Binary - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::ELF::Header - :project: lief - ----------- - -Section -******* - -.. doxygenclass:: LIEF::ELF::Section - :project: lief - ----------- - -Segment -******* - -.. doxygenclass:: LIEF::ELF::Segment - :project: lief - ----------- - -Dynamic Entry -************* - -.. doxygenclass:: LIEF::ELF::DynamicEntry - :project: lief - ----------- - -Dynamic Entry Library -********************* - -.. doxygenclass:: LIEF::ELF::DynamicEntryLibrary - :project: lief - ----------- - -Dynamic Shared Object -********************* - -.. doxygenclass:: LIEF::ELF::DynamicSharedObject - :project: lief - ----------- - -Dynamic Entry Run Path -********************** - -.. doxygenclass:: LIEF::ELF::DynamicEntryRunPath - :project: lief - ----------- - -Dynamic Entry RPath -******************* - -.. doxygenclass:: LIEF::ELF::DynamicEntryRpath - :project: lief - ----------- - -Dynamic Entry Array -******************* - -.. doxygenclass:: LIEF::ELF::DynamicEntryArray - :project: lief - ----------- - -Dynamic Entry Flags -******************* - -.. doxygenclass:: LIEF::ELF::DynamicEntryFlags - :project: lief - ----------- - -Relocations -*********** - -.. doxygenclass:: LIEF::ELF::Relocation - :project: lief - ----------- - -Symbol -****** - -.. doxygenclass:: LIEF::ELF::Symbol - :project: lief - ----------- - -Symbol Version -************** - -.. doxygenclass:: LIEF::ELF::SymbolVersion - :project: lief - ----------- - -Symbol Version Auxiliary -************************ - -.. doxygenclass:: LIEF::ELF::SymbolVersionAux - :project: lief - ----------- - -Symbol Version Definition -************************* - -.. doxygenclass:: LIEF::ELF::SymbolVersionDefinition - :project: lief - ----------- - -Symbol Version Requirement -************************** - -.. doxygenclass:: LIEF::ELF::SymbolVersionRequirement - :project: lief - ----------- - -Symbol Version Auxiliary Requirement -************************************ - -.. doxygenclass:: LIEF::ELF::SymbolVersionAuxRequirement - :project: lief - ----------- - -GNU Hash table -************** - -.. doxygenclass:: LIEF::ELF::GnuHash - :project: lief - ----------- - -SYSV Hash table -*************** - -.. doxygenclass:: LIEF::ELF::SysvHash - :project: lief - ----------- - -Note -**** - -.. doxygenclass:: LIEF::ELF::Note - :project: lief - ----------- - - -Note Details -************ - -.. doxygenclass:: LIEF::ELF::NoteDetails - :project: lief - ----------- - -Core PrPsInfo -************* - -.. doxygenclass:: LIEF::ELF::CorePrPsInfo - :project: lief - ----------- - - -Core File -********* - -.. doxygenclass:: LIEF::ELF::CoreFile - :project: lief - ----------- - - -Core File Entry -*************** - -.. doxygenstruct:: LIEF::ELF::CoreFileEntry - :project: lief - ----------- - -Core PrStatus -************* - -.. doxygenclass:: LIEF::ELF::CorePrStatus - :project: lief - ----------- - - -Core Siginfo -************* - -.. doxygenclass:: LIEF::ELF::CoreSigInfo - :project: lief - ----------- - -Core Auxiliary Vector -********************* - -.. doxygenclass:: LIEF::ELF::CoreAuxv - :project: lief - ----------- - -Android Note -************ - -.. doxygenclass:: LIEF::ELF::AndroidNote - :project: lief - ----------- - -Note ABI -******** - -.. doxygenclass:: LIEF::ELF::NoteAbi - :project: lief - ----------- - -Builder -******* - -.. doxygenclass:: LIEF::ELF::Builder - :project: lief - ----------- - - -Utilities -********* - -.. doxygenfunction:: LIEF::ELF::is_elf(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::ELF::is_elf(const std::vector&) - :project: lief - ----------- - - - -Enums -***** - -Architectures -~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ARCH - :project: lief - ----------- - -Identity -~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::IDENTITY - :project: lief - ----------- - -Binary types -~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::E_TYPE - :project: lief - ----------- - -Version -~~~~~~~ - -.. doxygenenum:: LIEF::ELF::VERSION - :project: lief - ----------- - -ELF Class -~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_CLASS - :project: lief - ----------- - -ELF Data -~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_DATA - :project: lief - ----------- - -ELF OS/ABI -~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::OS_ABI - :project: lief - ----------- - -Symbol section index -~~~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::SYMBOL_SECTION_INDEX - :project: lief - ----------- - -Section types -~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_SECTION_TYPES - :project: lief - ----------- - -Section flags -~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_SECTION_FLAGS - :project: lief - ----------- - -Symbol bindings -~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::SYMBOL_BINDINGS - :project: lief - ----------- - -Symbol visibility -~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_SYMBOL_VISIBILITY - :project: lief - ----------- - -Symbol types -~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_SYMBOL_TYPES - :project: lief - ----------- - - -Segment types -~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::SEGMENT_TYPES - :project: lief - ----------- - -Segment flags -~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::ELF_SEGMENT_FLAGS - :project: lief - ----------- - -Dynamic tags -~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::DYNAMIC_TAGS - :project: lief - ----------- - -Dynamic flags -~~~~~~~~~~~~~ -.. doxygenenum:: LIEF::ELF::DYNAMIC_FLAGS - :project: lief - ----------- - -Dynamic flags 1 -~~~~~~~~~~~~~~~ -.. doxygenenum:: LIEF::ELF::DYNAMIC_FLAGS_1 - :project: lief - ----------- - -Dynamic symbols counting -~~~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::DYNSYM_COUNT_METHODS - :project: lief - ----------- - - -Note types -~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::NOTE_TYPES - :project: lief - ----------- - -Note Core types -~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::NOTE_TYPES_CORE - :project: lief - ----------- - - -Note ABIs -~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::NOTE_ABIS - :project: lief - - ----------- - - -Relocation purpose -~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOCATION_PURPOSES - :project: lief - ----------- - -Relocations x86-64 -~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_x86_64 - :project: lief - ----------- - - -Relocations x86 (i386) -~~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_i386 - :project: lief - ----------- - -Relocations ARM -~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_ARM - :project: lief - ----------- - -Relocations AARCH64 -~~~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_AARCH64 - :project: lief - - -Relocations MIPS -~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_MIPS - :project: lief - - -Relocations PPC -~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_POWERPC32 - :project: lief - - -Relocations PPC64 -~~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::ELF::RELOC_POWERPC64 - :project: lief diff --git a/vendor/lief/doc/sphinx/api/cpp/index.md b/vendor/lief/doc/sphinx/api/cpp/index.md new file mode 100644 index 0000000..4bfd04c --- /dev/null +++ b/vendor/lief/doc/sphinx/api/cpp/index.md @@ -0,0 +1,52 @@ +(cpp-api-ref)= + +# {fa}`regular fa-file-code` C++ + +:::{note} +You can also find the Doxygen documentation [here](../../doxygen/) +::: + +## Iterators + +```{eval-rst} +.. doxygenclass:: LIEF::ref_iterator +``` + +```{eval-rst} +.. doxygentypedef:: LIEF::const_ref_iterator +``` + +```{eval-rst} +.. doxygenclass:: LIEF::filter_iterator +``` + +```{eval-rst} +.. doxygentypedef:: LIEF::const_filter_iterator +``` + +```{eval-rst} +.. doxygenclass:: LIEF::iterator_range + +``` + +## BinaryStream + +```{eval-rst} +.. doxygenclass:: LIEF::BinaryStream +``` + +```{eval-rst} +.. doxygenclass:: LIEF::FileStream +``` + +```{eval-rst} +.. doxygenclass:: LIEF::SpanStream +``` + +```{eval-rst} +.. doxygenclass:: LIEF::VectorStream +``` + +```{eval-rst} +.. doxygenclass:: LIEF::MemoryStream +``` diff --git a/vendor/lief/doc/sphinx/api/cpp/index.rst b/vendor/lief/doc/sphinx/api/cpp/index.rst deleted file mode 100644 index b2c01f2..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _cpp-api-ref: - -C++ -=== - -The original Doxygen documentation is also available `here <../../doxygen/>`_ - -.. toctree:: - :maxdepth: 2 - - abstract.rst - elf.rst - pe.rst - macho.rst - oat.rst - dex.rst - vdex.rst - art.rst - - -.. toctree:: - :caption: Platforms - :maxdepth: 2 - - platforms/android.rst - -.. _cpp-api-error-handling: - -Error Handling --------------- - -.. doxygentypedef:: LIEF::result - :project: lief - -.. doxygenfunction:: LIEF::as_lief_err - :project: lief - -.. doxygenenum:: lief_errors - :project: lief - -.. doxygentypedef:: LIEF::ok_error_t - :project: lief - -.. doxygenfunction:: LIEF::ok - :project: lief - -.. doxygenstruct:: LIEF::ok_t - :project: lief - -See also the section :ref:`err_handling` - -Exceptions ----------- - -.. warning:: - - Exceptions will be progressively removed as explained in :ref:`err_handling` - -.. doxygenclass:: LIEF::exception - :project: lief - -.. doxygenclass:: LIEF::bad_file - :project: lief - -.. doxygenclass:: LIEF::bad_format - :project: lief - -.. doxygenclass:: LIEF::not_implemented - :project: lief - -.. doxygenclass:: LIEF::not_supported - :project: lief - -.. doxygenclass:: LIEF::integrity_error - :project: lief - -.. doxygenclass:: LIEF::read_out_of_bound - :project: lief - -.. doxygenclass:: LIEF::not_found - :project: lief - -.. doxygenclass:: LIEF::corrupted - :project: lief - -.. doxygenclass:: LIEF::conversion_error - :project: lief - -.. doxygenclass:: LIEF::type_error - :project: lief - -.. doxygenclass:: LIEF::builder_error - :project: lief - -.. doxygenclass:: LIEF::parser_error - :project: lief - -.. doxygenclass:: LIEF::pe_error - :project: lief - -.. doxygenclass:: LIEF::pe_bad_section_name - :project: lief - - -Iterators ---------- - -.. doxygenclass:: LIEF::ref_iterator - :project: lief - -.. doxygentypedef:: LIEF::const_ref_iterator - :project: lief - -.. doxygenclass:: LIEF::filter_iterator - :project: lief - -.. doxygentypedef:: LIEF::const_filter_iterator - :project: lief - -Logging -------- - -.. doxygenfunction:: LIEF::logging::disable - :project: lief - -.. doxygenfunction:: LIEF::logging::enable - :project: lief - -.. doxygenfunction:: LIEF::logging::set_level - :project: lief - -Logging levels -~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::logging::LOGGING_LEVEL - :project: lief - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/api/cpp/macho.rst b/vendor/lief/doc/sphinx/api/cpp/macho.rst deleted file mode 100644 index 825e16e..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/macho.rst +++ /dev/null @@ -1,495 +0,0 @@ -MachO ------ - -Parsers -******* - -.. doxygenclass:: LIEF::MachO::Parser - :project: lief - - -.. doxygenclass:: LIEF::MachO::BinaryParser - :project: lief - - -.. doxygenstruct:: LIEF::MachO::ParserConfig - :project: lief - ----------- - -FatBinary -********* - -.. doxygenclass:: LIEF::MachO::FatBinary - :project: lief - ----------- - -Binary -****** - -.. doxygenclass:: LIEF::MachO::Binary - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::MachO::Header - :project: lief - - ----------- - -Builder -******* - -.. doxygenclass:: LIEF::MachO::Builder - :project: lief - ----------- - -DylibCommand -************ - -.. doxygenclass:: LIEF::MachO::DylibCommand - :project: lief - - ----------- - -DylinkerCommand -**************** - -.. doxygenclass:: LIEF::MachO::DylinkerCommand - :project: lief - - ----------- - - -DynamicSymbolCommand -******************** - -.. doxygenclass:: LIEF::MachO::DynamicSymbolCommand - :project: lief - - ----------- - -LoadCommand -*********** - -.. doxygenclass:: LIEF::MachO::LoadCommand - :project: lief - - ----------- - -MainCommand -*********** - -.. doxygenclass:: LIEF::MachO::MainCommand - :project: lief - - ----------- - -Section -******* - -.. doxygenclass:: LIEF::MachO::Section - :project: lief - - ----------- - - -SegmentCommand -************** - -.. doxygenclass:: LIEF::MachO::SegmentCommand - :project: lief - - ----------- - -Symbol -****** - -.. doxygenclass:: LIEF::MachO::Symbol - :project: lief - - ----------- - -SymbolCommand -************* - -.. doxygenclass:: LIEF::MachO::SymbolCommand - :project: lief - - ----------- - -UUIDCommand -*********** - -.. doxygenclass:: LIEF::MachO::UUIDCommand - :project: lief - ----------- - -Dyld Info -********* - -.. doxygenclass:: LIEF::MachO::DyldInfo - :project: lief - - -Function starts -*************** - -.. doxygenclass:: LIEF::MachO::FunctionStarts - :project: lief - - ----------- - -Source Version -************** - -.. doxygenclass:: LIEF::MachO::SourceVersion - :project: lief - ----------- - - -Version Min -*********** - -.. doxygenclass:: LIEF::MachO::VersionMin - :project: lief - ----------- - -Relocation -********** - -.. doxygenclass:: LIEF::MachO::Relocation - :project: lief - ----------- - - -Relocation Object -***************** - -.. doxygenclass:: LIEF::MachO::RelocationObject - :project: lief - ----------- - - -Relocation Dyld -*************** - -.. doxygenclass:: LIEF::MachO::RelocationDyld - :project: lief - ----------- - -Relocation Dyld -*************** - -.. doxygenclass:: LIEF::MachO::RelocationDyld - :project: lief - ----------- - - -Relocation Fixup -**************** - -.. doxygenclass:: LIEF::MachO::RelocationFixup - :project: lief - ----------- - -Dyld Binding Info -***************** - -.. doxygenclass:: LIEF::MachO::DyldBindingInfo - :project: lief - ----------- - -Chained Binding Info -******************** - -.. doxygenclass:: LIEF::MachO::ChainedBindingInfo - :project: lief - ----------- - -Export Info -*********** - -.. doxygenclass:: LIEF::MachO::ExportInfo - :project: lief - ----------- - - -Thread Command -************** - -.. doxygenclass:: LIEF::MachO::ThreadCommand - :project: lief - ----------- - -RPath Command -************* - -.. doxygenclass:: LIEF::MachO::RPathCommand - :project: lief - ----------- - - -Code Signature -************** - -.. doxygenclass:: LIEF::MachO::CodeSignature - :project: lief - ----------- - -Data In Code -************ - -.. doxygenclass:: LIEF::MachO::DataInCode - :project: lief - ----------- - -Data Code Entry -**************** - -.. doxygenclass:: LIEF::MachO::DataCodeEntry - :project: lief - ----------- - -Segment Split Info -****************** - -.. doxygenclass:: LIEF::MachO::SegmentSplitInfo - :project: lief - ----------- - -Sub-Framework -************* - -.. doxygenclass:: LIEF::MachO::SubFramework - :project: lief - ----------- - -Dyld Environment -**************** - -.. doxygenclass:: LIEF::MachO::DyldEnvironment - :project: lief - ----------- - -Encryption Info -*************** - -.. doxygenclass:: LIEF::MachO::EncryptionInfo - :project: lief - ----------- - - -Build Version -************* - -.. doxygenclass:: LIEF::MachO::BuildVersion - :project: lief - ----------- - - -Build Tool Version -****************** - -.. doxygenclass:: LIEF::MachO::BuildToolVersion - :project: lief - ----------- - -Fileset Command -*************** - -.. doxygenclass:: LIEF::MachO::FilesetCommand - :project: lief - ----------- - -DyldChainedFixups Command -************************* - -.. doxygenclass:: LIEF::MachO::DyldChainedFixups - :project: lief - ----------- - -DyldExportsTrie Command -************************ - -.. doxygenclass:: LIEF::MachO::DyldExportsTrie - :project: lief - ----------- - -Code Signature Dir Command -************************** - -.. doxygenclass:: LIEF::MachO::CodeSignatureDir - :project: lief - ----------- - - -Linker Optimization Hint Command -******************************** - -.. doxygenclass:: LIEF::MachO::LinkerOptHint - :project: lief - ----------- - - -Two Level Hints Command -*********************** - -.. doxygenclass:: LIEF::MachO::TwoLevelHints - :project: lief - ----------- - - -Utilities -********* - -.. doxygenfunction:: LIEF::MachO::is_macho(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::MachO::is_macho(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::MachO::is_fat(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::MachO::is_64(const std::string&) - :project: lief - - ----------- - - -Enums -***** - -.. doxygenenum:: LIEF::MachO::MACHO_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::FILE_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::HEADER_FLAGS - :project: lief - -.. doxygenenum:: LIEF::MachO::LOAD_COMMAND_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::MACHO_SEGMENTS_FLAGS - :project: lief - -.. doxygenenum:: LIEF::MachO::MACHO_SECTION_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::MACHO_SECTION_FLAGS - :project: lief - -.. doxygenenum:: LIEF::MachO::MACHO_SYMBOL_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::SYMBOL_DESCRIPTIONS - :project: lief - -.. doxygenenum:: LIEF::MachO::X86_RELOCATION - :project: lief - -.. doxygenenum:: LIEF::MachO::X86_64_RELOCATION - :project: lief - -.. doxygenenum:: LIEF::MachO::PPC_RELOCATION - :project: lief - -.. doxygenenum:: LIEF::MachO::ARM_RELOCATION - :project: lief - -.. doxygenenum:: LIEF::MachO::ARM64_RELOCATION - :project: lief - -.. doxygenenum:: LIEF::MachO::CPU_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::CPU_SUBTYPES_X86 - :project: lief - -.. doxygenenum:: LIEF::MachO::RELOCATION_ORIGINS - :project: lief - -.. doxygenenum:: LIEF::MachO::REBASE_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::BINDING_CLASS - :project: lief - -.. doxygenenum:: LIEF::MachO::REBASE_OPCODES - :project: lief - -.. doxygenenum:: LIEF::MachO::BIND_TYPES - :project: lief - -.. doxygenenum:: LIEF::MachO::BIND_SPECIAL_DYLIB - :project: lief - -.. doxygenenum:: LIEF::MachO::BIND_OPCODES - :project: lief - -.. doxygenenum:: LIEF::MachO::EXPORT_SYMBOL_KINDS - :project: lief - -.. doxygenenum:: LIEF::MachO::EXPORT_SYMBOL_FLAGS - :project: lief - -.. doxygenenum:: LIEF::MachO::VM_PROTECTIONS - :project: lief - -.. doxygenenum:: LIEF::MachO::SYMBOL_ORIGINS - :project: lief - -.. doxygenenum:: LIEF::MachO::DYLD_CHAINED_FORMAT - :project: lief - -.. doxygenenum:: LIEF::MachO::DYLD_CHAINED_PTR_FORMAT - :project: lief - diff --git a/vendor/lief/doc/sphinx/api/cpp/oat.rst b/vendor/lief/doc/sphinx/api/cpp/oat.rst deleted file mode 100644 index b1b9277..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/oat.rst +++ /dev/null @@ -1,120 +0,0 @@ -OAT ---- - -Utilities -********* - -.. doxygenfunction:: LIEF::OAT::is_oat(const LIEF::ELF::Binary &elf_binary) - :project: lief - -.. doxygenfunction:: LIEF::OAT::is_oat(const std::string &file) - :project: lief - -.. doxygenfunction:: LIEF::OAT::is_oat(const std::vector &raw)) - :project: lief - -.. doxygenfunction:: LIEF::OAT::version(const LIEF::ELF::Binary &elf_binary) - :project: lief - -.. doxygenfunction:: LIEF::OAT::version(const std::string &file) - :project: lief - -.. doxygenfunction:: LIEF::OAT::version(const std::vector &raw) - :project: lief - -.. doxygenfunction:: LIEF::OAT::android_version - :project: lief - ----------- - -Parser -******* - -.. doxygenclass:: LIEF::OAT::Parser - :project: lief - ----------- - - -Binary -****** - -.. doxygenclass:: LIEF::OAT::Binary - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::OAT::Header - :project: lief - - ----------- - -DexFile -******* - -.. doxygenclass:: LIEF::OAT::DexFile - :project: lief - - ----------- - -Class -***** - -.. doxygenclass:: LIEF::OAT::Class - :project: lief - - ----------- - -Method -****** - -.. doxygenclass:: LIEF::OAT::Method - :project: lief - - ----------- - -Enums -***** - - -OAT Class types -~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::OAT::OAT_CLASS_TYPES - :project: lief - ----------- - - -OAT Class Status -~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::OAT::OAT_CLASS_STATUS - :project: lief - ----------- - - -Header Keys -~~~~~~~~~~~ - -.. doxygenenum:: LIEF::OAT::HEADER_KEYS - :project: lief - ----------- - - -Instruction sets -~~~~~~~~~~~~~~~~ - -.. doxygenenum:: LIEF::OAT::INSTRUCTION_SETS - :project: lief - - diff --git a/vendor/lief/doc/sphinx/api/cpp/pe.rst b/vendor/lief/doc/sphinx/api/cpp/pe.rst deleted file mode 100644 index 32c97a4..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/pe.rst +++ /dev/null @@ -1,651 +0,0 @@ -PE --- - -Binary -****** - -.. doxygenclass:: LIEF::PE::Binary - :project: lief - ----------- - -Dos Header -********** - -.. doxygenclass:: LIEF::PE::DosHeader - :project: lief - ----------- - -Header -******* - -.. doxygenclass:: LIEF::PE::Header - :project: lief - ----------- - -Optional Header -*************** - -.. doxygenclass:: LIEF::PE::OptionalHeader - :project: lief - ----------- - -Data Directory -************** - -.. doxygenclass:: LIEF::PE::DataDirectory - :project: lief - ----------- - -Section -******* - -.. doxygenclass:: LIEF::PE::Section - :project: lief - ----------- - - -Import -******* - -.. doxygenclass:: LIEF::PE::Import - :project: lief - ----------- - - -Import Entry -************ - -.. doxygenclass:: LIEF::PE::ImportEntry - :project: lief - ----------- - -Delay Import -************ - -.. doxygenclass:: LIEF::PE::DelayImport - :project: lief - ----------- - -Delay Import Entry -****************** - -.. doxygenclass:: LIEF::PE::DelayImportEntry - :project: lief - ----------- - -TLS -*** - -.. doxygenclass:: LIEF::PE::TLS - :project: lief - ----------- - -Debug -***** - -.. doxygenclass:: LIEF::PE::Debug - :project: lief - ----------- - -Code View -********* - -.. doxygenclass:: LIEF::PE::CodeView - :project: lief - ----------- - -Code View PDB -************* - -.. doxygenclass:: LIEF::PE::CodeViewPDB - :project: lief - ----------- - - -Symbol -******* - -.. doxygenclass:: LIEF::PE::Symbol - :project: lief - ----------- - -Relocation -********** - -.. doxygenclass:: LIEF::PE::Relocation - :project: lief - - ----------- - -Relocation Entry -**************** - -.. doxygenclass:: LIEF::PE::RelocationEntry - :project: lief - - ----------- - -Export -****** - -.. doxygenclass:: LIEF::PE::Export - :project: lief - - ----------- - -Export Entry -************ - -.. doxygenclass:: LIEF::PE::ExportEntry - :project: lief - - ----------- - -Signature -********* - -.. doxygenclass:: LIEF::PE::Signature - :project: lief - - ----------- - -Signature Attribute -******************* - -.. doxygenclass:: LIEF::PE::Attribute - :project: lief - - ----------- - -Signature ContentType -********************* - -.. doxygenclass:: LIEF::PE::ContentType - :project: lief - - ----------- - -Signature GenericType -********************* - -.. doxygenclass:: LIEF::PE::GenericType - :project: lief - - ----------- - -Signature MsSpcNestedSignature -******************************* - -.. doxygenclass:: LIEF::PE::MsSpcNestedSignature - :project: lief - - ----------- - - -Signature MsSpcStatementType -**************************** - -.. doxygenclass:: LIEF::PE::MsSpcStatementType - :project: lief - - ----------- - - -Signature PKCS9AtSequenceNumber -******************************* - -.. doxygenclass:: LIEF::PE::PKCS9AtSequenceNumber - :project: lief - - ----------- - - -Signature PKCS9CounterSignature -******************************* - -.. doxygenclass:: LIEF::PE::PKCS9CounterSignature - :project: lief - - ----------- - - -Signature PKCS9MessageDigest -**************************** - -.. doxygenclass:: LIEF::PE::PKCS9MessageDigest - :project: lief - - ----------- - - -Signature PKCS9SigningTime -************************** - -.. doxygenclass:: LIEF::PE::PKCS9SigningTime - :project: lief - - ----------- - - -Signature SpcSpOpusInfo -*********************** - -.. doxygenclass:: LIEF::PE::SpcSpOpusInfo - :project: lief - - ----------- - - -RsaInfo -******* - -.. doxygenclass:: LIEF::PE::RsaInfo - :project: lief - - ----------- - - -x509 -**** - -.. doxygenclass:: LIEF::PE::x509 - :project: lief - - ----------- - - -ContentInfo -*********** - -.. doxygenclass:: LIEF::PE::ContentInfo - :project: lief - - ----------- - - -SignerInfo -********** - -.. doxygenclass:: LIEF::PE::SignerInfo - :project: lief - - ----------- - - -Builder -******* - -.. doxygenclass:: LIEF::PE::Builder - :project: lief - - ----------- - - -Resources Manager -***************** - -.. doxygenclass:: LIEF::PE::ResourcesManager - :project: lief - - ----------- - - -Resource Node -************* - -.. doxygenclass:: LIEF::PE::ResourceNode - :project: lief - - ----------- - - -Resource Directory -****************** - -.. doxygenclass:: LIEF::PE::ResourceDirectory - :project: lief - - ----------- - - -Resource Data -************* - -.. doxygenclass:: LIEF::PE::ResourceData - :project: lief - - ----------- - - -Resource Icon -************* - -.. doxygenclass:: LIEF::PE::ResourceIcon - :project: lief - ----------- - -Resource Dialog -*************** - -.. doxygenclass:: LIEF::PE::ResourceDialog - :project: lief - ----------- - - -Resource Dialog Item -******************** - -.. doxygenclass:: LIEF::PE::ResourceDialogItem - :project: lief - ----------- - - -Resource Version -**************** - -.. doxygenclass:: LIEF::PE::ResourceVersion - :project: lief - ----------- - - -Resource Fixed File Info -************************ - -.. doxygenclass:: LIEF::PE::ResourceFixedFileInfo - :project: lief - ----------- - - -Resource Var File Info -********************** - -.. doxygenclass:: LIEF::PE::ResourceVarFileInfo - :project: lief - - ----------- - - -Resource String File Info -************************* - -.. doxygenclass:: LIEF::PE::ResourceStringFileInfo - :project: lief - - ----------- - -Lang code item -************** - -.. doxygenclass:: LIEF::PE::LangCodeItem - :project: lief - - ----------- - -Resource String Table -********************* - -.. doxygenclass:: LIEF::PE::ResourceStringTable - :project: lief - - ----------- - -Rich Header -*********** - -.. doxygenclass:: LIEF::PE::RichHeader - :project: lief - ----------- - -Rich Entry -********** - -.. doxygenclass:: LIEF::PE::RichEntry - :project: lief - ----------- - -Code Integrity -************** - -.. doxygenclass:: LIEF::PE::CodeIntegrity - :project: lief - ----------- - -Pogo -**** - -.. doxygenclass:: LIEF::PE::Pogo - :project: lief - ----------- - -Pogo Entry -************** - -.. doxygenclass:: LIEF::PE::PogoEntry - :project: lief - ----------- - -Load Configuration -****************** - -.. doxygenclass:: LIEF::PE::LoadConfiguration - :project: lief - - -Load Configuration V0 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV0 - :project: lief - -Load Configuration V1 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV1 - :project: lief - -Load Configuration V2 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV2 - :project: lief - -Load Configuration V3 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV3 - :project: lief - -Load Configuration V4 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV4 - :project: lief - -Load Configuration V5 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV5 - :project: lief - -Load Configuration V6 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV6 - :project: lief - -Load Configuration V7 -~~~~~~~~~~~~~~~~~~~~~ - -.. doxygenclass:: LIEF::PE::LoadConfigurationV7 - :project: lief - -------------------- - -Utilities -********* - -.. doxygenfunction:: LIEF::PE::get_type(const std::string &) - :project: lief - -.. doxygenfunction:: LIEF::PE::get_type(const std::vector< uint8_t > &) - :project: lief - -.. doxygenfunction:: LIEF::PE::is_pe(const std::string &) - :project: lief - -.. doxygenfunction:: LIEF::PE::is_pe(const std::vector< uint8_t > &) - :project: lief - -.. doxygenfunction:: LIEF::PE::get_imphash - :project: lief - -.. doxygenenum:: LIEF::PE::IMPHASH_MODE - :project: lief - -.. doxygenfunction:: LIEF::PE::resolve_ordinals - :project: lief - -.. doxygenfunction:: LIEF::PE::oid_to_string - :project: lief - ----------- - -Enums -***** - -.. doxygenenum:: LIEF::PE::MACHINE_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::HEADER_CHARACTERISTICS - :project: lief - -.. doxygenenum:: LIEF::PE::SYMBOL_STORAGE_CLASS - :project: lief - -.. doxygenenum:: LIEF::PE::SYMBOL_BASE_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::SYMBOL_COMPLEX_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::RELOCATIONS_BASE_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::RELOCATIONS_I386 - :project: lief - -.. doxygenenum:: LIEF::PE::RELOCATIONS_AMD64 - :project: lief - -.. doxygenenum:: LIEF::PE::RELOCATIONS_ARM - :project: lief - -.. doxygenenum:: LIEF::PE::DATA_DIRECTORY - :project: lief - -.. doxygenenum:: LIEF::PE::SUBSYSTEM - :project: lief - -.. doxygenenum:: LIEF::PE::DLL_CHARACTERISTICS - :project: lief - -.. doxygenenum:: LIEF::PE::DEBUG_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::RESOURCE_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::RESOURCE_LANGS - :project: lief - -.. doxygenenum:: LIEF::PE::RESOURCE_SUBLANGS - :project: lief - -.. doxygenenum:: LIEF::PE::CODE_PAGES - :project: lief - -.. doxygenenum:: LIEF::PE::WINDOW_STYLES - :project: lief - -.. doxygenenum:: LIEF::PE::EXTENDED_WINDOW_STYLES - :project: lief - -.. doxygenenum:: LIEF::PE::DIALOG_BOX_STYLES - :project: lief - -.. doxygenenum:: LIEF::PE::FIXED_VERSION_OS - :project: lief - -.. doxygenenum:: LIEF::PE::FIXED_VERSION_FILE_FLAGS - :project: lief - -.. doxygenenum:: LIEF::PE::FIXED_VERSION_FILE_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::FIXED_VERSION_FILE_SUB_TYPES - :project: lief - -.. doxygenenum:: LIEF::PE::WIN_VERSION - :project: lief - -.. doxygenenum:: LIEF::PE::GUARD_CF_FLAGS - :project: lief - -.. doxygenenum:: LIEF::PE::ALGORITHMS - :project: lief - -.. doxygenenum:: LIEF::PE::SIG_ATTRIBUTE_TYPES - :project: lief diff --git a/vendor/lief/doc/sphinx/api/cpp/platforms/android.rst b/vendor/lief/doc/sphinx/api/cpp/platforms/android.rst deleted file mode 100644 index a875f62..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/platforms/android.rst +++ /dev/null @@ -1,20 +0,0 @@ -Android -======= - - -Utilities -********* - -.. doxygenfunction:: LIEF::Android::code_name - :project: lief - -.. doxygenfunction:: LIEF::Android::version_string - :project: lief - ------------ - -Android Versions -***************** - -.. doxygenenum:: LIEF::Android::ANDROID_VERSIONS - :project: lief diff --git a/vendor/lief/doc/sphinx/api/cpp/vdex.rst b/vendor/lief/doc/sphinx/api/cpp/vdex.rst deleted file mode 100644 index 37f2245..0000000 --- a/vendor/lief/doc/sphinx/api/cpp/vdex.rst +++ /dev/null @@ -1,47 +0,0 @@ -VDEX ----- - -Utilities -********* - -.. doxygenfunction:: LIEF::VDEX::is_vdex(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::VDEX::is_vdex(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::VDEX::version(const std::string&) - :project: lief - -.. doxygenfunction:: LIEF::VDEX::version(const std::vector&) - :project: lief - -.. doxygenfunction:: LIEF::VDEX::android_version - :project: lief - ----------- - -Parser -******* - -.. doxygenclass:: LIEF::VDEX::Parser - :project: lief - ----------- - - -File -**** - -.. doxygenclass:: LIEF::VDEX::File - :project: lief - ----------- - -Header -****** - -.. doxygenclass:: LIEF::VDEX::Header - :project: lief - - diff --git a/vendor/lief/doc/sphinx/api/error_handling/index.md b/vendor/lief/doc/sphinx/api/error_handling/index.md new file mode 100644 index 0000000..cbc221f --- /dev/null +++ b/vendor/lief/doc/sphinx/api/error_handling/index.md @@ -0,0 +1,86 @@ +(err_handling)= + +# {fa}`solid fa-triangle-exclamation` Error Handling + +## Introduction + +LIEF manages errors using: + +1. Exceptions (deprecated and removed since LIEF 0.13.0) +2. [std::expected (tl::expected)](https://github.com/TartanLlama/expected) + +It turns out that using C++ exceptions (and RTTI) was not the best design choice, +as LIEF, as a library, can be used in a `-fno-exceptions` context. +Consequently, we moved to a mechanism based on the `ResultOrError` +idiom. This idiom is similar to those found in LLVM with +[llvm::ErrorOr](https://llvm.org/doxygen/classllvm_1_1ErrorOr.html) and in Rust +with [std::result](https://doc.rust-lang.org/std/result/). +LIEF uses a {title-reference}`std::expected`-like interface to handle errors. Since this +interface is only available in C++23, we rely on +[TartanLlama/expected](https://github.com/TartanLlama/expected), which +provides this interface for C++11/C++17. + +Functions using this idiom return a {cpp:type}`LIEF::result`, which wraps either +the successful result or an error. + +The user can process this result as follows: + +{{ literalinclude("../../../code/cpp/error_handling.cpp", "result-handling") }} + +In the case of Python, we leverage the *dynamic* features of the language to +return either the expected value or an error if the function fails. +For instance, in previous versions of {func}`lief.PE.get_type`, the +implementation raised an exception to inform the user: + +{{ literalinclude("../../../code/python/error_handling.py", "get-type-exception") }} + +With the new implementation that relies on the `ResultOrError` idiom, the +function returns the {class}`lief.PE.PE_TYPE` value if everything is correct, +and returns a {class}`lief.lief_errors` in case of a processing error. + +The user can handle this new interface by using the `isinstance()` function or by comparing the value with +a {class}`lief.lief_errors` attribute: + +{{ literalinclude("../../../code/python/error_handling.py", "get-type-error") }} + +## {fa}`solid fa-code` API + +### C++ + +```{eval-rst} +.. doxygenclass:: LIEF::result +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::as_lief_err +``` + +```{eval-rst} +.. doxygenenum:: lief_errors +``` + +```{eval-rst} +.. doxygenclass:: LIEF::ok_error_t +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ok +``` + +```{eval-rst} +.. doxygenstruct:: LIEF::ok_t +``` + +### Python + +```{eval-rst} +.. autoclass:: lief.lief_errors +``` + +```{eval-rst} +.. autoclass:: lief.ok_t +``` + +```{eval-rst} +.. autoclass:: lief.ok_error_t +``` diff --git a/vendor/lief/doc/sphinx/api/index.rst b/vendor/lief/doc/sphinx/api/index.rst deleted file mode 100644 index 5591500..0000000 --- a/vendor/lief/doc/sphinx/api/index.rst +++ /dev/null @@ -1,12 +0,0 @@ -API -=== - -.. toctree:: - :maxdepth: 2 - - python/index.rst - cpp/index.rst - c/index.rst - - - diff --git a/vendor/lief/doc/sphinx/api/logging/index.md b/vendor/lief/doc/sphinx/api/logging/index.md new file mode 100644 index 0000000..393afdf --- /dev/null +++ b/vendor/lief/doc/sphinx/api/logging/index.md @@ -0,0 +1,108 @@ +# {fa}`regular fa-rectangle-list` Logging + +This section details the API for interacting with LIEF's logging engine. + +LIEF uses [spdlog](https://github.com/gabime/spdlog) for its logging +mechanism, and this API provides an abstraction over that implementation. + +## {fa}`solid fa-code` API + +### C++ + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::disable +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::enable +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::set_level +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::set_path +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::log(Level level, const std::string &fmt, const Args&... args) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::log(Level level, const std::string &fmt, const std::vector &args) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::log(Level level, const std::string &msg) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::logging::reset +``` + +```{eval-rst} +.. doxygenenum:: LIEF::logging::Level +``` + +```{eval-rst} +.. doxygenclass:: LIEF::logging::Scoped +``` + +## Example + +{{ literalinclude("../../../code/cpp/logging.cpp", "example") }} + +### Python + +```{eval-rst} +.. autofunction:: lief.logging.set_level +``` + +```{eval-rst} +.. autofunction:: lief.logging.enable +``` + +```{eval-rst} +.. autofunction:: lief.logging.disable +``` + +```{eval-rst} +.. autofunction:: lief.logging.set_path +``` + +```{eval-rst} +.. autofunction:: lief.logging.log +``` + +```{eval-rst} +.. autofunction:: lief.logging.level_scope +``` + +```{eval-rst} +.. autoclass:: lief.logging.Scoped + :members: +``` + +```{eval-rst} +.. autoclass:: lief.logging.Level +``` + +## Example + +{{ literalinclude("../../../code/python/logging.py", "example") }} + +### Rust + +- {rust:func}`lief::logging::disable` +- {rust:func}`lief::logging::enable` +- {rust:func}`lief::logging::set_level` +- {rust:func}`lief::logging::set_path` +- {rust:func}`lief::logging::log` +- {rust:func}`lief::logging::reset` +- {rust:enum}`lief::logging::Level` +- {rust:struct}`lief::logging::Scoped` + +## Example + +{{ literalinclude("../../../code/rust/src/logging.rs", "example") }} diff --git a/vendor/lief/doc/sphinx/api/python/abstract.rst b/vendor/lief/doc/sphinx/api/python/abstract.rst deleted file mode 100644 index 5f4a3ab..0000000 --- a/vendor/lief/doc/sphinx/api/python/abstract.rst +++ /dev/null @@ -1,131 +0,0 @@ -Abstract --------- - - -Parser -******* - -.. autofunction:: lief.parse - ----------- - -Binary -****** - -.. autoclass:: lief.Binary - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.Header - :members: - :inherited-members: - :undoc-members: - ----------- - - -Section -******* - -.. autoclass:: lief.Section - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol -****** - -.. autoclass:: lief.Symbol - :members: - :inherited-members: - :undoc-members: - - ----------- - -Relocation -********** - -.. autoclass:: lief.Relocation - :members: - :inherited-members: - :undoc-members: - - ----------- - -Function -******** - -.. autoclass:: lief.Function - :members: - :inherited-members: - :undoc-members: - - - -Enums -***** - - -Executable formats -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.EXE_FORMATS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Object types -~~~~~~~~~~~~ - -.. autoclass:: lief.OBJECT_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -Architectures -~~~~~~~~~~~~~ - -.. autoclass:: lief.ARCHITECTURES - :members: - :inherited-members: - :undoc-members: - ----------- - -Modes -~~~~~ - -.. autoclass:: lief.MODES - :members: - :inherited-members: - :undoc-members: - ----------- - -Endianness -~~~~~~~~~~ - -.. autoclass:: lief.ENDIANNESS - :members: - :inherited-members: - :undoc-members: - - - - diff --git a/vendor/lief/doc/sphinx/api/python/art.rst b/vendor/lief/doc/sphinx/api/python/art.rst deleted file mode 100644 index e6c0128..0000000 --- a/vendor/lief/doc/sphinx/api/python/art.rst +++ /dev/null @@ -1,43 +0,0 @@ -ART ---- - -Utilities -********* - -.. autofunction:: lief.ART.is_art - -.. autofunction:: lief.ART.version - -.. autofunction:: lief.ART.android_version - ----------- - - -Parser -****** - -.. autofunction:: lief.ART.parse - ----------- - - -File -**** - -.. autoclass:: lief.ART.File - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.ART.Header - :members: - :inherited-members: - :undoc-members: - - - diff --git a/vendor/lief/doc/sphinx/api/python/dex.rst b/vendor/lief/doc/sphinx/api/python/dex.rst deleted file mode 100644 index cec8850..0000000 --- a/vendor/lief/doc/sphinx/api/python/dex.rst +++ /dev/null @@ -1,149 +0,0 @@ -DEX ---- - -Utilities -********* - -.. autofunction:: lief.DEX.is_dex - -.. autofunction:: lief.DEX.version - - ----------- - -Parser -******* - -.. autofunction:: lief.DEX.parse - ----------- - - -File -**** - -.. autoclass:: lief.DEX.File - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.DEX.Header - :members: - :inherited-members: - :undoc-members: - - ----------- - -Method -****** - -.. autoclass:: lief.DEX.Method - :members: - :inherited-members: - :undoc-members: - - ----------- - -Field -***** - -.. autoclass:: lief.DEX.Field - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Class -****** - -.. autoclass:: lief.DEX.Class - :members: - :inherited-members: - :undoc-members: - ----------- - -Code Info -********* - -.. autoclass:: lief.DEX.CodeInfo - :members: - :inherited-members: - :undoc-members: - - ----------- - -Prototype -********* - -.. autoclass:: lief.DEX.Prototype - :members: - :inherited-members: - :undoc-members: - - ----------- - -Type -**** - -.. autoclass:: lief.DEX.Type - :members: - :inherited-members: - :undoc-members: - ----------- - -MapList -******* - -.. autoclass:: lief.DEX.MapList - :members: - :inherited-members: - :undoc-members: - ----------- - -MapItem -******* - -.. autoclass:: lief.DEX.MapItem - :members: - :inherited-members: - :undoc-members: - - ----------- - -Enums -***** - - -Access Flags -~~~~~~~~~~~~ - -.. autoclass:: lief.DEX.ACCESS_FLAGS - :members: - :inherited-members: - :undoc-members: - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/api/python/elf.rst b/vendor/lief/doc/sphinx/api/python/elf.rst deleted file mode 100644 index 56f978c..0000000 --- a/vendor/lief/doc/sphinx/api/python/elf.rst +++ /dev/null @@ -1,684 +0,0 @@ -ELF ---- - -Parser -******* - -.. autofunction:: lief.ELF.parse - ----------- - -Binary -****** - -.. autoclass:: lief.ELF.Binary - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.ELF.Header - :members: - :inherited-members: - :undoc-members: - ----------- - -Section -******* - -.. autoclass:: lief.ELF.Section - :members: - :inherited-members: - :undoc-members: - ----------- - -Segment -******* - -.. autoclass:: lief.ELF.Segment - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry -************* - -.. autoclass:: lief.ELF.DynamicEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry Library -********************* - -.. autoclass:: lief.ELF.DynamicEntryLibrary - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Shared Object -********************* - -.. autoclass:: lief.ELF.DynamicSharedObject - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry Run Path -********************** - -.. autoclass:: lief.ELF.DynamicEntryRunPath - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry RPath -******************* - -.. autoclass:: lief.ELF.DynamicEntryRpath - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry Array -******************* - -.. autoclass:: lief.ELF.DynamicEntryArray - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Entry Flags -******************* - -.. autoclass:: lief.ELF.DynamicEntryFlags - :members: - :inherited-members: - :undoc-members: - - ----------- - -Relocations -*********** - -.. autoclass:: lief.ELF.Relocation - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol -****** - -.. autoclass:: lief.ELF.Symbol - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol Version -************** - -.. autoclass:: lief.ELF.SymbolVersion - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol Version Auxiliary -************************ - -.. autoclass:: lief.ELF.SymbolVersionAux - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol Version Definition -************************* - -.. autoclass:: lief.ELF.SymbolVersionDefinition - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol Version Requirement -************************** - -.. autoclass:: lief.ELF.SymbolVersionRequirement - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol Version Auxiliary Requirement -************************************ - -.. autoclass:: lief.ELF.SymbolVersionAuxRequirement - :members: - :inherited-members: - :undoc-members: - ----------- - - -GNU Hash table -************** - -.. autoclass:: lief.ELF.GnuHash - :members: - :inherited-members: - :undoc-members: - ----------- - - -SYSV Hash table -*************** - -.. autoclass:: lief.ELF.SysvHash - :members: - :inherited-members: - :undoc-members: - ----------- - - -Note -**** - -.. autoclass:: lief.ELF.Note - :members: - :inherited-members: - :undoc-members: - ----------- - -Note Details -************ - -.. autoclass:: lief.ELF.NoteDetails - :members: - :inherited-members: - :undoc-members: - ----------- - -Core PrPsInfo -************* - -.. autoclass:: lief.ELF.CorePrPsInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Core PrStatus -************* - -.. autoclass:: lief.ELF.CorePrStatus - :members: - :inherited-members: - :undoc-members: - ----------- - -Core File -********* - -.. autoclass:: lief.ELF.CoreFile - :members: - :inherited-members: - :undoc-members: - ----------- - - -Core File Entry -*************** - -.. autoclass:: lief.ELF.CoreFileEntry - :members: - :inherited-members: - :undoc-members: - ----------- - - -Core Siginfo -************ - -.. autoclass:: lief.ELF.CoreSigInfo - :members: - :inherited-members: - :undoc-members: - ----------- - - -Core Auxiliary Vector -********************* - -.. autoclass:: lief.ELF.CoreAuxv - :members: - :inherited-members: - :undoc-members: - ----------- - -Android Note -************* - -.. autoclass:: lief.ELF.AndroidNote - :members: - :inherited-members: - :undoc-members: - ----------- - -Note ABI -******** - -.. autoclass:: lief.ELF.NoteAbi - :members: - :inherited-members: - :undoc-members: - ----------- - - -Builder -******* - -.. autoclass:: lief.ELF.Builder - :members: - :inherited-members: - :undoc-members: - - -Enums -***** - -Identity -~~~~~~~~ - -.. autoclass:: lief.ELF.IDENTITY - :members: - :inherited-members: - :undoc-members: - ----------- - - -ELF Class -~~~~~~~~~ - -.. autoclass:: lief.ELF.ELF_CLASS - :members: - :inherited-members: - :undoc-members: - ----------- - -ELF Data -~~~~~~~~ - -.. autoclass:: lief.ELF.ELF_DATA - :members: - :inherited-members: - :undoc-members: - ----------- - -ELF OS/ABI -~~~~~~~~~~ - -.. autoclass:: lief.ELF.OS_ABI - :members: - :inherited-members: - :undoc-members: - ----------- - - -Symbol section index -~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SYMBOL_SECTION_INDEX - :members: - :inherited-members: - :undoc-members: - ----------- - - -Binary types -~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.E_TYPE - :members: - :inherited-members: - :undoc-members: - ----------- - -Section types -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SECTION_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -Section flags -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SECTION_FLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Segment types -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SEGMENT_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -Segment flags -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SEGMENT_FLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Architectures -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.ARCH - :members: - :inherited-members: - :undoc-members: - ----------- - -Version -~~~~~~~ - -.. autoclass:: lief.ELF.VERSION - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic tags -~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.DYNAMIC_TAGS - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic flags -~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.DYNAMIC_FLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Dynamic flags 1 -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.DYNAMIC_FLAGS_1 - :members: - :inherited-members: - :undoc-members: - ----------- - - -Symbol types -~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SYMBOL_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol bindings -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SYMBOL_BINDINGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Symbol Visibility -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.SYMBOL_VISIBILITY - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocations x86-64 -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_X86_64 - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocations x86 (i386) -~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_i386 - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocations ARM -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_ARM - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocations AARCH64 -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_AARCH64 - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocations MIPS -~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_MIPS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocations PPC -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_PPC - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocations PPC64 -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_PPC64 - :members: - :inherited-members: - :undoc-members: - ----------- - - -Dynamic symbols counting -~~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.DYNSYM_COUNT_METHODS - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocation purpose -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.RELOCATION_PURPOSES - :members: - :inherited-members: - :undoc-members: - ----------- - - -Note types -~~~~~~~~~~ - -.. autoclass:: lief.ELF.NOTE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -Note ABIs -~~~~~~~~~ - -.. autoclass:: lief.ELF.NOTE_ABIS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Note Core types -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.NOTE_TYPES_CORE - :members: - :inherited-members: - :undoc-members: - ----------- - -ARM Processor flags -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.ARM_EFLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - -MIPS Processor flags -~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.MIPS_EFLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - -PPC64 Processor flags -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.PPC64_EFLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -Hexagon Processor flags -~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.ELF.HEXAGON_EFLAGS - :members: - :inherited-members: - :undoc-members: diff --git a/vendor/lief/doc/sphinx/api/python/index.rst b/vendor/lief/doc/sphinx/api/python/index.rst deleted file mode 100644 index 2d5f770..0000000 --- a/vendor/lief/doc/sphinx/api/python/index.rst +++ /dev/null @@ -1,75 +0,0 @@ -.. _python-api-ref: - -Python -====== - -.. toctree:: - :caption: Common - :maxdepth: 1 - - utilities.rst - abstract.rst - -.. toctree:: - :caption: Formats specific - :maxdepth: 2 - - elf.rst - pe.rst - macho.rst - oat.rst - dex.rst - vdex.rst - art.rst - -.. toctree:: - :caption: Platforms - :maxdepth: 2 - - platforms/android.rst - - -Logging -------- - -.. autofunction:: lief.logging.set_level - -.. autofunction:: lief.logging.enable - -.. autofunction:: lief.logging.disable - - -Logging levels -~~~~~~~~~~~~~~ - -.. autoclass:: lief.logging.LOGGING_LEVEL - :members: - :inherited-members: - :undoc-members: - -.. _python-api-error-handling: - -Error Handling --------------- - -.. autoclass:: lief.lief_errors - :members: - :inherited-members: - :undoc-members: - -.. autoclass:: lief.ok_t - :members: - :inherited-members: - :undoc-members: - -See also the section :ref:`err_handling` - -Exceptions ----------- - -In the future versions of LIEF, the exceptions will be removed to be replaced with the ``ResultOrError`` -idiom. - -See: - * https://llvm.org/docs/ProgrammersManual.html#error-handling - * https://doc.rust-lang.org/book/ch09-02-recoverable-errors-with-result.html#recoverable-errors-with-result diff --git a/vendor/lief/doc/sphinx/api/python/macho.rst b/vendor/lief/doc/sphinx/api/python/macho.rst deleted file mode 100644 index 86a96a5..0000000 --- a/vendor/lief/doc/sphinx/api/python/macho.rst +++ /dev/null @@ -1,744 +0,0 @@ -MachO ------ - - -Parser -******* - -.. autofunction:: lief.MachO.parse - -.. autoclass:: lief.MachO.ParserConfig - :members: - :inherited-members: - :undoc-members: - -.. code-block:: python - - fatbinary_1 = lief.MachO.parse("/usr/bin/ls", config=lief.MachO.ParserConfig.deep) - # or - fatbinary_2 = lief.MachO.parse("/usr/bin/ls", config=lief.MachO.ParserConfig.quick) - - ----------- - - -FatBinary -********* - -.. autoclass:: lief.MachO.FatBinary - :members: - :inherited-members: - :undoc-members: - ----------- - - -.. _python-macho-binary-api-ref: - -Binary -****** - -.. autoclass:: lief.MachO.Binary - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.MachO.Header - :members: - :inherited-members: - :undoc-members: - ----------- - - -Section -******* - -.. autoclass:: lief.MachO.Section - :members: - :inherited-members: - :undoc-members: - ----------- - - -SegmentCommand -************** - -.. autoclass:: lief.MachO.SegmentCommand - :members: - :inherited-members: - :undoc-members: - ----------- - - -LoadCommand -*********** - -.. autoclass:: lief.MachO.LoadCommand - :members: - :inherited-members: - :undoc-members: - ----------- - - -DylibCommand -************ - -.. autoclass:: lief.MachO.DylibCommand - :members: - :inherited-members: - :undoc-members: - - ----------- - -DylinkerCommand -*************** - -.. autoclass:: lief.MachO.DylinkerCommand - :members: - :inherited-members: - :undoc-members: - - ----------- - -UUIDCommand -*********** - -.. autoclass:: lief.MachO.UUIDCommand - :members: - :inherited-members: - :undoc-members: - - ----------- - - -MainCommand -*********** - -.. autoclass:: lief.MachO.MainCommand - :members: - :inherited-members: - :undoc-members: - ----------- - - -Symbol -****** - -.. autoclass:: lief.MachO.Symbol - :members: - :inherited-members: - :undoc-members: - ----------- - - -Symbol Command -************** - -.. autoclass:: lief.MachO.SymbolCommand - :members: - :inherited-members: - :undoc-members: - ----------- - -Dynamic Symbol Command -********************** - -.. autoclass:: lief.MachO.DynamicSymbolCommand - :members: - :inherited-members: - :undoc-members: - ----------- - -Dyld Info -********* - -.. autoclass:: lief.MachO.DyldInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Function starts -*************** - -.. autoclass:: lief.MachO.FunctionStarts - :members: - :inherited-members: - :undoc-members: - ----------- - -Source Version -************** - -.. autoclass:: lief.MachO.SourceVersion - :members: - :inherited-members: - :undoc-members: - ----------- - - -Version Min -*********** - -.. autoclass:: lief.MachO.VersionMin - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocation -********** - -.. autoclass:: lief.MachO.Relocation - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocation Object -***************** - -.. autoclass:: lief.MachO.RelocationObject - :members: - :inherited-members: - :undoc-members: - ----------- - - -Relocation Dyld -*************** - -.. autoclass:: lief.MachO.RelocationDyld - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocation Fixup -**************** - -.. autoclass:: lief.MachO.RelocationFixup - :members: - :inherited-members: - :undoc-members: - ----------- - - -Binding Info -************ - -.. autoclass:: lief.MachO.BindingInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Dyld Binding Info -***************** - -.. autoclass:: lief.MachO.DyldBindingInfo - :members: - :inherited-members: - :undoc-members: - ----------- - - -Chained Binding Info -******************** - -.. autoclass:: lief.MachO.ChainedBindingInfo - :members: - :inherited-members: - :undoc-members: - ----------- - - -Export Info -*********** - -.. autoclass:: lief.MachO.ExportInfo - :members: - :inherited-members: - :undoc-members: - ----------- - - -Thread Command -************** - -.. autoclass:: lief.MachO.ThreadCommand - :members: - :inherited-members: - :undoc-members: - ----------- - -RPath Command -************* - -.. autoclass:: lief.MachO.RPathCommand - :members: - :inherited-members: - :undoc-members: - ----------- - - -Code Signature -************** - -.. autoclass:: lief.MachO.CodeSignature - :members: - :inherited-members: - :undoc-members: - ----------- - -Data In Code -************ - -.. autoclass:: lief.MachO.DataInCode - :members: - :inherited-members: - :undoc-members: - ----------- - -Data Code Entry -*************** - -.. autoclass:: lief.MachO.DataCodeEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -Segment Split Info -****************** - -.. autoclass:: lief.MachO.SegmentSplitInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Sub Framework -************* - -.. autoclass:: lief.MachO.SubFramework - :members: - :inherited-members: - :undoc-members: - ----------- - -Dyld Environment -**************** - -.. autoclass:: lief.MachO.DyldEnvironment - :members: - :inherited-members: - :undoc-members: - ----------- - -Encryption Info -*************** - -.. autoclass:: lief.MachO.EncryptionInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Build Version -************* - -.. autoclass:: lief.MachO.BuildVersion - :members: - :inherited-members: - :undoc-members: - ----------- - -Build Tool Version -****************** - -.. autoclass:: lief.MachO.BuildToolVersion - :members: - :inherited-members: - :undoc-members: - ----------- - -Fileset Command -*************** - -.. autoclass:: lief.MachO.FilesetCommand - :members: - :inherited-members: - :undoc-members: - ----------- - -DyldChainedFixups Command -************************* - -.. autoclass:: lief.MachO.DyldChainedFixups - :members: - :inherited-members: - :undoc-members: - ----------- - -DyldExportsTrie Command -*********************** - -.. autoclass:: lief.MachO.DyldExportsTrie - :members: - :inherited-members: - :undoc-members: - ----------- - -Code Signature Dir Command -************************** - -.. autoclass:: lief.MachO.CodeSignatureDir - :members: - :inherited-members: - :undoc-members: - ----------- - -Two Level Hints -*************** - -.. autoclass:: lief.MachO.TwoLevelHints - :members: - :inherited-members: - :undoc-members: - ----------- - -Linker Optimization Hint -************************ - -.. autoclass:: lief.MachO.LinkerOptHint - :members: - :inherited-members: - :undoc-members: - ----------- - -Builder -******* - -.. autoclass:: lief.MachO.Builder - :members: - :inherited-members: - :undoc-members: - ----------- - -Enums -***** - - -CPU_TYPES -~~~~~~~~~ - -.. autoclass:: lief.MachO.CPU_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -FILE_TYPES -~~~~~~~~~~ - -.. autoclass:: lief.MachO.FILE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -HEADER_FLAGS -~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.HEADER_FLAGS - :members: - :inherited-members: - :undoc-members: - ----------- - - -LOAD_COMMAND_TYPES -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.LOAD_COMMAND_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -SECTION_TYPES -~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.SECTION_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -MACHO_TYPES -~~~~~~~~~~~ - -.. autoclass:: lief.MachO.MACHO_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - - -X86_RELOCATION -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.X86_RELOCATION - :members: - :inherited-members: - :undoc-members: - ----------- - - -X86_64_RELOCATION -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.X86_64_RELOCATION - :members: - :inherited-members: - :undoc-members: - ----------- - - -PPC_RELOCATION -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.PPC_RELOCATION - :members: - :inherited-members: - :undoc-members: - ----------- - - -ARM_RELOCATION -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.ARM_RELOCATION - :members: - :inherited-members: - :undoc-members: - ----------- - -ARM64_RELOCATION -~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.ARM64_RELOCATION - :members: - :inherited-members: - :undoc-members: - - ----------- - -RELOCATION_ORIGINS -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.RELOCATION_ORIGINS - :members: - :inherited-members: - :undoc-members: - - ----------- - -REBASE_TYPES -~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.REBASE_TYPES - :members: - :inherited-members: - :undoc-members: - - - ----------- - -BINDING_CLASS -~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.BINDING_CLASS - :members: - :inherited-members: - :undoc-members: - - ----------- - -REBASE_OPCODES -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.REBASE_OPCODES - :members: - :inherited-members: - :undoc-members: - - ----------- - -BIND_TYPES -~~~~~~~~~~ - -.. autoclass:: lief.MachO.BIND_TYPES - :members: - :inherited-members: - :undoc-members: - - ----------- - -BIND_SPECIAL_DYLIB -~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.BIND_SPECIAL_DYLIB - :members: - :inherited-members: - :undoc-members: - - ----------- - -BIND_OPCODES -~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.BIND_OPCODES - :members: - :inherited-members: - :undoc-members: - - ----------- - -EXPORT_SYMBOL_KINDS -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.EXPORT_SYMBOL_KINDS - :members: - :inherited-members: - :undoc-members: - - ----------- - -EXPORT_SYMBOL_FLAGS -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.EXPORT_SYMBOL_FLAGS - :members: - :inherited-members: - :undoc-members: - - ----------- - -VM_PROTECTIONS -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.VM_PROTECTIONS - :members: - :inherited-members: - :undoc-members: - - ----------- - -SYMBOL_ORIGINS -~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.SYMBOL_ORIGINS - :members: - :inherited-members: - :undoc-members: - ----------- - -SECTION_FLAGS -~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.SECTION_FLAGS - :members: - :inherited-members: - :undoc-members: - -DYLD_CHAINED_FORMAT -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.DYLD_CHAINED_FORMAT - :members: - :inherited-members: - :undoc-members: - -DYLD_CHAINED_PTR_FORMAT -~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.MachO.DYLD_CHAINED_PTR_FORMAT - :members: - :inherited-members: - :undoc-members: diff --git a/vendor/lief/doc/sphinx/api/python/oat.rst b/vendor/lief/doc/sphinx/api/python/oat.rst deleted file mode 100644 index ec7ae3f..0000000 --- a/vendor/lief/doc/sphinx/api/python/oat.rst +++ /dev/null @@ -1,120 +0,0 @@ -OAT ---- - -Utilities -********* - -.. autofunction:: lief.OAT.is_oat - -.. autofunction:: lief.OAT.version - -.. autofunction:: lief.OAT.android_version - ----------- - -Parser -******* - -.. autofunction:: lief.OAT.parse - ----------- - - -Binary -****** - -.. autoclass:: lief.OAT.Binary - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.OAT.Header - :members: - :inherited-members: - :undoc-members: - - ----------- - -DexFile -******* - -.. autoclass:: lief.OAT.DexFile - :members: - :inherited-members: - :undoc-members: - - ----------- - -Class -***** - -.. autoclass:: lief.OAT.Class - :members: - :inherited-members: - :undoc-members: - - ----------- - -Method -****** - -.. autoclass:: lief.OAT.Method - :members: - :inherited-members: - :undoc-members: - ----------- - -Enums -***** - -OAT Class types -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.OAT.OAT_CLASS_TYPES - :members: - :inherited-members: - :undoc-members: - - ----------- - - -OAT Class Status -~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.OAT.OAT_CLASS_STATUS - :members: - :inherited-members: - :undoc-members: - - ----------- - -Header Keys -~~~~~~~~~~~ - -.. autoclass:: lief.OAT.HEADER_KEYS - :members: - :inherited-members: - :undoc-members: - - ----------- - -Instruction sets -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.OAT.INSTRUCTION_SETS - :members: - :inherited-members: - :undoc-members: - diff --git a/vendor/lief/doc/sphinx/api/python/pe.rst b/vendor/lief/doc/sphinx/api/python/pe.rst deleted file mode 100644 index 5af1f7e..0000000 --- a/vendor/lief/doc/sphinx/api/python/pe.rst +++ /dev/null @@ -1,979 +0,0 @@ -PE --- - -Parser -******* - -.. autofunction:: lief.PE.parse - - -Binary -****** - -.. autoclass:: lief.PE.Binary - :members: - :inherited-members: - :undoc-members: - ----------- - -Dos Header -********** - -.. autoclass:: lief.PE.DosHeader - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -******* - -.. autoclass:: lief.PE.Header - :members: - :inherited-members: - :undoc-members: - ----------- - -Optional Header -*************** - -.. autoclass:: lief.PE.OptionalHeader - :members: - :inherited-members: - :undoc-members: - ----------- - -Data Directory -************** - -.. autoclass:: lief.PE.DataDirectory - :members: - :inherited-members: - :undoc-members: - ----------- - -Section -******* - -.. autoclass:: lief.PE.Section - :members: - :inherited-members: - :undoc-members: - ----------- - - -Import -******* - -.. autoclass:: lief.PE.Import - :members: - :inherited-members: - :undoc-members: - ----------- - - -Import Entry -************ - -.. autoclass:: lief.PE.ImportEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -Delay Import -************ - -.. autoclass:: lief.PE.DelayImport - :members: - :inherited-members: - :undoc-members: - ----------- - - -Delay Import Entry -****************** - -.. autoclass:: lief.PE.DelayImportEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -TLS -*** - -.. autoclass:: lief.PE.TLS - :members: - :inherited-members: - :undoc-members: - ----------- - -Symbol -******* - -.. autoclass:: lief.PE.Symbol - :members: - :inherited-members: - :undoc-members: - ----------- - -Relocation -********** - -.. autoclass:: lief.PE.Relocation - :members: - :inherited-members: - :undoc-members: - - ----------- - -Relocation Entry -**************** - -.. autoclass:: lief.PE.RelocationEntry - :members: - :inherited-members: - :undoc-members: - - ----------- - -Export -****** - -.. autoclass:: lief.PE.Export - :members: - :inherited-members: - :undoc-members: - - ----------- - -Export Entry -************ - -.. autoclass:: lief.PE.ExportEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature -********* - -.. autoclass:: lief.PE.Signature - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature Attribute -******************* - -.. autoclass:: lief.PE.Attribute - :members: - :inherited-members: - :undoc-members: - ----------- - - -Signature ContentType -********************* - -.. autoclass:: lief.PE.ContentType - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature GenericType -********************* - -.. autoclass:: lief.PE.GenericType - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature MsSpcNestedSignature -****************************** - -.. autoclass:: lief.PE.MsSpcNestedSignature - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature MsSpcStatementType -**************************** - -.. autoclass:: lief.PE.MsSpcStatementType - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature PKCS9AtSequenceNumber -******************************* - -.. autoclass:: lief.PE.PKCS9AtSequenceNumber - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature PKCS9CounterSignature -******************************* - -.. autoclass:: lief.PE.PKCS9CounterSignature - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature PKCS9MessageDigest -**************************** - -.. autoclass:: lief.PE.PKCS9MessageDigest - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature PKCS9SigningTime -************************** - -.. autoclass:: lief.PE.PKCS9SigningTime - :members: - :inherited-members: - :undoc-members: - ----------- - -Signature SpcSpOpusInfo -*********************** - -.. autoclass:: lief.PE.SpcSpOpusInfo - :members: - :inherited-members: - :undoc-members: - ----------- - - -RsaInfo -******* - -.. autoclass:: lief.PE.RsaInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -x509 -**** - -.. autoclass:: lief.PE.x509 - :members: - :inherited-members: - :undoc-members: - ----------- - -ContentInfo -*********** - -.. autoclass:: lief.PE.ContentInfo - :members: - :inherited-members: - :undoc-members: - - ----------- - - -SignerInfo -********** - -.. autoclass:: lief.PE.SignerInfo - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Builder -******* - -.. autoclass:: lief.PE.Builder - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Resource Node -************* - -.. autoclass:: lief.PE.ResourceNode - :members: - :inherited-members: - :undoc-members: - - ----------- - - - -Resource Directory -****************** - -.. autoclass:: lief.PE.ResourceDirectory - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Resource Data -************* - -.. autoclass:: lief.PE.ResourceData - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Resources Manager -***************** - -.. autoclass:: lief.PE.ResourcesManager - :members: - :inherited-members: - :undoc-members: - - ----------- - -Resource Icon -************* - -.. autoclass:: lief.PE.ResourceIcon - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Resource Dialog -*************** - -.. autoclass:: lief.PE.ResourceDialog - :members: - :inherited-members: - :undoc-members: - - ----------- - -Resource Dialog Item -********************* - -.. autoclass:: lief.PE.ResourceDialogItem - :members: - :inherited-members: - :undoc-members: - - ----------- - - -Resource Version -**************** - -.. autoclass:: lief.PE.ResourceVersion - :members: - :inherited-members: - :undoc-members: - ----------- - -Resource Fixed File Info -************************ - -.. autoclass:: lief.PE.ResourceFixedFileInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Resource Var File Info -********************** - -.. autoclass:: lief.PE.ResourceVarFileInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Resource String File Info -************************* - -.. autoclass:: lief.PE.ResourceStringFileInfo - :members: - :inherited-members: - :undoc-members: - ----------- - -Lang code item -************** - -.. autoclass:: lief.PE.LangCodeItem - :members: - :inherited-members: - :undoc-members: - ----------- - -Resource String Table -********************* - -.. autoclass:: lief.PE.ResourceStringTable - :members: - :inherited-members: - :undoc-members: - ----------- - -Rich Header -*********** - -.. autoclass:: lief.PE.RichHeader - :members: - :inherited-members: - :undoc-members: - ----------- - -Rich Entry -********** - -.. autoclass:: lief.PE.RichEntry - :members: - :inherited-members: - :undoc-members: - ----------- - -Debug -***** - -.. autoclass:: lief.PE.Debug - :members: - :inherited-members: - :undoc-members: - ----------- - - -Code View -********* - -.. autoclass:: lief.PE.CodeView - :members: - :inherited-members: - :undoc-members: - ----------- - - -Code View PDB -************** - -.. autoclass:: lief.PE.CodeViewPDB - :members: - :inherited-members: - :undoc-members: - ----------- - -Code Integrity -************** - -.. autoclass:: lief.PE.CodeIntegrity - :members: - :inherited-members: - :undoc-members: - ----------- - - -Pogo -**** - -.. autoclass:: lief.PE.Pogo - :members: - :inherited-members: - :undoc-members: - ----------- - - -Pogo Entry -********** - -.. autoclass:: lief.PE.PogoEntry - :members: - :inherited-members: - :undoc-members: - ----------- - - -Load Configuration -****************** - -.. autoclass:: lief.PE.LoadConfiguration - :members: - :inherited-members: - :undoc-members: - - -Load Configuration V0 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV0 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V1 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV1 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V2 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV2 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V3 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV3 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V4 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV4 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V5 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV5 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V6 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV6 - :members: - :show-inheritance: - :undoc-members: - -Load Configuration V7 -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.LoadConfigurationV7 - :members: - :show-inheritance: - :undoc-members: - - -Utilities -********* - - -.. autofunction:: lief.PE.is_pe - -.. autofunction:: lief.PE.get_type - -.. autofunction:: lief.PE.get_imphash - -.. autoclass:: lief.PE.IMPHASH_MODE - :members: - :inherited-members: - :undoc-members: - -.. autofunction:: lief.PE.resolve_ordinals - ------------ - -Enums -***** - -PE_TYPE -~~~~~~~ - -.. autoclass:: lief.PE.PE_TYPE - :members: - :inherited-members: - :undoc-members: - ----------- - -MACHINE_TYPES -~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.MACHINE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -HEADER_CHARACTERISTICS -~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.HEADER_CHARACTERISTICS - :members: - :inherited-members: - :undoc-members: - ----------- - -SUBSYSTEM -~~~~~~~~~ - -.. autoclass:: lief.PE.SUBSYSTEM - :members: - :inherited-members: - :undoc-members: - ----------- - -DATA_DIRECTORY -~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.DATA_DIRECTORY - :members: - :inherited-members: - :undoc-members: - ----------- - -DLL_CHARACTERISTICS -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.DLL_CHARACTERISTICS - :members: - :inherited-members: - :undoc-members: - ----------- - -SECTION_CHARACTERISTICS -~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SECTION_CHARACTERISTICS - :members: - :inherited-members: - :undoc-members: - ----------- - -SECTION_TYPES -~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SECTION_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -SYMBOL_BASE_TYPES -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SYMBOL_BASE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -SYMBOL_COMPLEX_TYPES -~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SYMBOL_COMPLEX_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -SYMBOL_SECTION_NUMBER -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SYMBOL_SECTION_NUMBER - :members: - :inherited-members: - :undoc-members: - ----------- - -SYMBOL_STORAGE_CLASS -~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SYMBOL_STORAGE_CLASS - :members: - :inherited-members: - :undoc-members: - ----------- - -RELOCATIONS_BASE_TYPES -~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.RELOCATIONS_BASE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -DEBUG_TYPES -~~~~~~~~~~~ - -.. autoclass:: lief.PE.DEBUG_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -RESOURCE_TYPES -~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.RESOURCE_TYPES - :members: - :inherited-members: - :undoc-members: - ----------- - -RESOURCE_LANGS -~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.RESOURCE_LANGS - :members: - :inherited-members: - :undoc-members: - ----------- - -RESOURCE_SUBLANGS -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.RESOURCE_SUBLANGS - :members: - :inherited-members: - :undoc-members: - ----------- - -FIXED_VERSION_FILE_SUB_TYPES -~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.CODE_PAGES - :members: - :inherited-members: - :undoc-members: - ----------- - -WINDOW_STYLES -~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.WINDOW_STYLES - :members: - :inherited-members: - :undoc-members: - - ----------- - -EXTENDED_WINDOW_STYLES -~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.EXTENDED_WINDOW_STYLES - :members: - :inherited-members: - :undoc-members: - - ----------- - -DIALOG_BOX_STYLES -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.DIALOG_BOX_STYLES - :members: - :inherited-members: - :undoc-members: - - ----------- - -FIXED_VERSION_OS -~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.FIXED_VERSION_OS - :members: - :inherited-members: - :undoc-members: - - ----------- - -FIXED_VERSION_FILE_FLAGS -~~~~~~~~~~~~~~~~~~~~~~~~ -.. autoclass:: lief.PE.FIXED_VERSION_FILE_FLAGS - :members: - :inherited-members: - :undoc-members: - - ----------- - -FIXED_VERSION_FILE_TYPES -~~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.FIXED_VERSION_FILE_TYPES - :members: - :inherited-members: - :undoc-members: - - ----------- - -FIXED_VERSION_FILE_SUB_TYPES -~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.FIXED_VERSION_FILE_SUB_TYPES - :members: - :inherited-members: - :undoc-members: - - ----------- - -WIN_VERSION -~~~~~~~~~~~ - -.. autoclass:: lief.PE.WIN_VERSION - :members: - :inherited-members: - :undoc-members: - - ----------- - -GUARD_CF_FLAGS -~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.GUARD_CF_FLAGS - :members: - :inherited-members: - :undoc-members: - - ----------- - -CODE_VIEW_SIGNATURES -~~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.CODE_VIEW_SIGNATURES - :members: - :inherited-members: - :undoc-members: - - -POGO_SIGNATURES -~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.POGO_SIGNATURES - :members: - :inherited-members: - :undoc-members: - - -ALGORITHMS -~~~~~~~~~~ - -.. autoclass:: lief.PE.ALGORITHMS - :members: - :inherited-members: - :undoc-members: - - -SIG_ATTRIBUTE_TYPES -~~~~~~~~~~~~~~~~~~~ - -.. autoclass:: lief.PE.SIG_ATTRIBUTE_TYPES - :members: - :inherited-members: - :undoc-members: diff --git a/vendor/lief/doc/sphinx/api/python/platforms/android.rst b/vendor/lief/doc/sphinx/api/python/platforms/android.rst deleted file mode 100644 index 2572c02..0000000 --- a/vendor/lief/doc/sphinx/api/python/platforms/android.rst +++ /dev/null @@ -1,21 +0,0 @@ -Android -======= - - -Utilities -********* - -.. autofunction:: lief.Android.code_name - -.. autofunction:: lief.Android.version_string - ------------ - - -Android Versions -***************** - -.. autoclass:: lief.Android.ANDROID_VERSIONS - :members: - :inherited-members: - :undoc-members: diff --git a/vendor/lief/doc/sphinx/api/python/utilities.rst b/vendor/lief/doc/sphinx/api/python/utilities.rst deleted file mode 100644 index 6722a5f..0000000 --- a/vendor/lief/doc/sphinx/api/python/utilities.rst +++ /dev/null @@ -1,30 +0,0 @@ -Utilities ---------- - -.. autofunction:: lief.is_pe - -.. autofunction:: lief.is_elf - -.. autofunction:: lief.is_macho - -.. autofunction:: lief.is_oat - -.. autofunction:: lief.oat_version - -.. autofunction:: lief.is_dex - -.. autofunction:: lief.dex_version - -.. autofunction:: lief.is_vdex - -.. autofunction:: lief.vdex_version - -.. autofunction:: lief.is_art - -.. autofunction:: lief.art_version - -.. autofunction:: lief.shell - -.. autofunction:: lief.breakp - -.. autofunction:: lief.demangle diff --git a/vendor/lief/doc/sphinx/api/python/vdex.rst b/vendor/lief/doc/sphinx/api/python/vdex.rst deleted file mode 100644 index d45438b..0000000 --- a/vendor/lief/doc/sphinx/api/python/vdex.rst +++ /dev/null @@ -1,42 +0,0 @@ -VDEX ----- - -Utilities -********* - -.. autofunction:: lief.VDEX.is_vdex - -.. autofunction:: lief.VDEX.version - -.. autofunction:: lief.VDEX.android_version - ----------- - -Parser -****** - -.. autofunction:: lief.VDEX.parse - ----------- - - -File -**** - -.. autoclass:: lief.VDEX.File - :members: - :inherited-members: - :undoc-members: - ----------- - -Header -****** - -.. autoclass:: lief.VDEX.Header - :members: - :inherited-members: - :undoc-members: - - - diff --git a/vendor/lief/doc/sphinx/api/rust/index.md b/vendor/lief/doc/sphinx/api/rust/index.md new file mode 100644 index 0000000..57bb565 --- /dev/null +++ b/vendor/lief/doc/sphinx/api/rust/index.md @@ -0,0 +1,120 @@ +(lief_rust_bindings)= + +# {fa}`brands fa-rust` Rust + +:::{note} +The API is documented here {sub-ref}`lief-rust-doc` and the nightly doc is +here: {sub-ref}`lief-rust-doc-nightly`. +::: + +```toml +[package] +name = "my-awesome-project" +version = "0.0.1" +edition = "2024" + +[dependencies] +lief = { git = "https://github.com/lief-project/LIEF", branch = "main" } +``` + +:::{warning} +LIEF rust bindings are not on `docs.rs` because of network restrictions: + +::: + +## Precompiled FFI Bindings + +LIEF's Rust bindings are split into two parts: + +1. `lief`: the high-level, idiomatic Rust API. +2. `lief-ffi`: the low-level FFI API based on [cxx](https://cxx.rs/). + +Two additional crates support the build process: + +- `lief-build`: build-script helper used by `lief-ffi` to fetch the + pre-compiled artifacts and emit the `cargo` link directives. +- `lief-ffigen`: standalone CLI that generates the C++ side of the + `cxx` bridge from the `#[cxx::bridge]` modules declared in + `lief-ffi`. + +Building `lief-ffi` requires generating the C++ bridge files with +`lief-ffigen` and then compiling them alongside `libLIEF`. Both steps +can take several minutes. + +To save time, LIEF provides pre-compiled versions of these artifacts, which +are downloaded from GitHub (for releases) or an S3 bucket (for nightly +builds). + +(lief-rust-precompiled)= + +### `LIEF_RUST_PRECOMPILED` + +If you need to avoid downloading these pre-compiled files, set +`LIEF_RUST_PRECOMPILED` to point to the directory that contains these files: + +```text +/home/romain/out +└── lib +    ├── libLIEF.a +    └── liblief-sys.a + +1 directory, 2 files + +LIEF_RUST_PRECOMPILED=/home/romain/out cargo build [...] +``` + +This variable can also be used when building in **offline** mode +(e.g., `cargo --offline`). + +As of now, the following targets are supported with pre-compilation: + +| Target | Description | +| ----------------------------- | ----------------------------------------------------- | +| `x86_64-unknown-linux-gnu` | Regular Linux x86-64 (Ubuntu 21.10+, Debian 12+, ...) | +| `i686-unknown-linux-gnu` | Regular Linux i686 (Ubuntu 19.10, Debian 10, ...) | +| `x86_64-unknown-linux-musl` | Musl target that allows full static build | +| `i686-unknown-linux-musl` | Linux i686 with Musl | +| `aarch64-unknown-linux-gnu` | Linux aarch64 (Debian 12+) | +| `aarch64-unknown-linux-musl` | Linux aarch64 with Musl | +| `aarch64-linux-android` | Android aarch64 (API 30+) | +| `x86_64-linux-android` | Android x86_64 (API 30+) | +| `x86_64-apple-darwin` | macOS 11+ x86-64 | +| `aarch64-apple-darwin` | macOS 11+ arm64 (Apple Silicon) | +| `aarch64-apple-ios` | iOS 12+ | +| `x86_64-pc-windows-msvc[MT]` | Regular Windows x86-64 (static UCRT runtime) | +| `x86_64-pc-windows-msvc[MD]` | Regular Windows x86-64 (dynamic UCRT runtime `.dll`) | +| `aarch64-pc-windows-msvc[MT]` | Regular Windows arm64 (static UCRT runtime) | +| `aarch64-pc-windows-msvc[MD]` | Regular Windows arm64 (dynamic UCRT runtime `.dll`) | + +### Precompilation + +The assets of the pre-compiled output are: + +1. LIEF static library: `LIEF.{a,lib}` +2. `liefsys.{a,lib}`: bridge between C++ and Rust + +The LIEF static library must be compiled as described in the +{ref}`compilation_ref` section using the CMake option: `-DLIEF_RUST_API=ON`. + +`liefsys.{a,lib}` is built in two steps. First, generate the C++ bridge +files with `lief-ffigen`: + +```console +$ cargo build [--profile release] -p lief-ffigen +$ target/{release,debug}/lief-ffigen \ + --output-dir cxx-bridge/ \ + --source-dir lief-ffi/ +``` + +Then compile them as a regular CMake-based library: + +```console +$ cmake -GNinja \ + -S api/rust/cmake-ffi/ \ + -B cxx-bridge-build/ \ + -DLIEF_DIR=$INSTALL_DIR/lib/cmake/LIEF \ + -DLIEF_RUST_FFI_SRC=cxx-bridge/ \ + -DCMAKE_INSTALL_PREFIX=cxx-bridge-out/ + +$ ninja -C cxx-bridge-build/ +``` diff --git a/vendor/lief/doc/sphinx/api/utilities/index.md b/vendor/lief/doc/sphinx/api/utilities/index.md new file mode 100644 index 0000000..bb3ede4 --- /dev/null +++ b/vendor/lief/doc/sphinx/api/utilities/index.md @@ -0,0 +1,159 @@ +# {fa}`solid fa-hand-holding-hand` Utilities + +## Demangling + +LIEF exposes a demangling API for the following formats: + +::::{tabs} +:::{tab} {fa}`brands fa-windows` MSVC +**Input** + +{{ literalinclude("../../../code/python/utilities.py", "demangle-msvc") }} + +**Result** + +```{code-block} text +void __cdecl h(int) +``` +::: +:::{tab} {fa}`brands fa-rust` Rust +**Input** + +{{ literalinclude("../../../code/python/utilities.py", "demangle-rust") }} + +**Result** + +```{code-block} text +foo::example_function +``` +::: +:::{tab} {fa}`regular fa-file-code` Itanium C++ +**Input** + +{{ literalinclude("../../../code/python/utilities.py", "demangle-itanium") }} + +**Result** + +```{code-block} text +typeinfo name for lld::SpecificAlloc +``` +::: +:::{tab} {fa}`brands fa-swift` Swift/Obj-C +**Input** + +{{ literalinclude("../../../code/python/utilities.py", "demangle-swift") }} + +**Result** + +```{code-block} text +type metadata for Foundation.Data._Representation +``` +::: +:::: + +```{eval-rst} +.. doxygenfunction:: LIEF::demangle +``` + +```{eval-rst} +.. autofunction:: lief.demangle +``` + +{fa}`brands fa-rust` {rust:func}`lief::demangle` + +## Extended Version + +To check if the current build is an {ref}`extended ` version, +you can use: + +```{eval-rst} +.. doxygenfunction:: LIEF::is_extended +``` + +```{eval-rst} +.. autodata:: lief._lief.__extended__ +``` + +{rust:func}`lief::is_extended` + +In C++, you can also check if `LIEF_EXTENDED` is defined: + +```cpp +#include + +#if defined(LIEF_EXTENDED) +// Extended version +#else +// Regular version +#endif +``` + +To get details about the version of the current extended build: + +```{eval-rst} +.. doxygenfunction:: LIEF::extended_version_info +``` + +## Android Platform + +```{eval-rst} +.. autofunction:: lief.Android.code_name +``` + +```{eval-rst} +.. autofunction:: lief.Android.version_string +``` + +```{eval-rst} +.. autoclass:: lief.Android.ANDROID_VERSIONS + :members: + :inherited-members: + :undoc-members: +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::Android::code_name +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::Android::version_string +``` + +```{eval-rst} +.. doxygenenum:: LIEF::Android::ANDROID_VERSIONS +``` + +## Python Leaks + +```{eval-rst} +.. autofunction:: lief.disable_leak_warning +``` + +## Helpers + +The `lief.dump()` utility can be used to pretty-print a buffer. + +For example: + +{{ literalinclude("../../../code/python/utilities.py", "dump") }} + +```{eval-rst} +.. autofunction:: lief.dump +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dump(const std::vector &data, const std::string &title = "", const std::string &prefix = "", size_t limit = 0) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dump(const uint8_t *buffer, size_t size, const std::string &title = "", const std::string &prefix = "", size_t limit = 0) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dump(span data, const std::string &title = "", const std::string &prefix = "", size_t limit = 0) +``` + +- {fa}`brands fa-rust` {rust:func}`lief::dump` +- {fa}`brands fa-rust` {rust:func}`lief::dump_with_limit` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/changelog.md b/vendor/lief/doc/sphinx/changelog.md new file mode 100644 index 0000000..a6c9a43 --- /dev/null +++ b/vendor/lief/doc/sphinx/changelog.md @@ -0,0 +1,2591 @@ +(changelog-ref)= + +# {fa}`solid fa-code-compare` Changelog + +## 2.0.0 - Not Released Yet + +:::{admonition} Breaking Changes +:class: warning + +- **C++17 Migration**: LIEF public headers, public API, and STL have been bumped from C++11 to **C++17**. +- **C API Removal**: The legacy C API has been completely removed. +- **Logging Level Renaming**: {sub-ref}`lief-logging-level` and its enumerators are now + written in `CamelCase` +::: + +```{eval-rst} + +:Assembly: + + * Add API to inspect and rewrite the ``LOCK`` prefix of x86 instructions: + + - |lief-assembly-x86-Instruction-has_lock_prefix| + - |lief-assembly-x86-Instruction-is_lockable| + - |lief-assembly-x86-Instruction-is_atomic| + - |lief-assembly-x86-Instruction-lock| + - |lief-assembly-x86-Instruction-unlock| + +:ELF: + + * Fix the layout of the segments added by LIEF for the architectures that + can use pages larger than 4K (:issue:`1366`) + * Fix the modification of binaries that have already been modified by LIEF. + The segment table was relocated a second time which, for the non-PIE + binaries, shifted the sections without shifting the segments nor the + dynamic entries. It resulted in a ``DT_STRTAB`` that was no longer pointing + to ``.dynstr`` (i.e. garbage ``DT_NEEDED``/``DT_RUNPATH`` names) and in a + ``PT_PHDR`` that was not wrapped by a ``PT_LOAD`` segment (:issue:`1366`). + * |lief-elf-check_layout| now reports the ``PT_LOAD`` segments that can't be + mapped independently because they share the same page. It also report + mismatch between ``.dynstr`` virtual address and ``DT_STRTAB``. + * Add support for the MIPS n64 relocation encoding + (:pr:`1367` by :github_user:`plusls`). + * Add |lief-elf-header-is_mips_n64| to check whether a binary uses this + encoding. + * |lief-elf-relocation-resolve| now supports ``R_MIPS_REL32``. + +:COFF: + + * Add |lief-coff-binary-get_section| to look up a section by its name. Names + that are stored in the COFF string table (i.e. longer than 8 bytes) can be + resolved either from their regular value or from their ``/`` + placeholder: + + .. code-block:: python + + import lief + + coff = lief.COFF.parse("dwarf.obj") + + section = coff.get_section(".debug_rnglists") + section.name # '/18' + section.coff_string.string # '.debug_rnglists' + +:Runtime: + + * Add |lief-runtime-memory-mmap_hint| to allocate memory close to a given + address. + * Add |lief-runtime-memorylayout| to inspect the memory layout of the current + process. |lief-runtime-memory_layout| iterates over the mapped + |lief-runtime-memorylayout-region| (:ref:`documentation `): + + .. code-block:: python + + import lief + + for region in lief.runtime.memory_layout(): + print(f"{region.addr:#014x}-{region.end_addr:#014x} {region.name}") + +:C++: + + * The parsers now take the file path as a ``std::string_view`` and they also + accept a ``std::filesystem::path``: + + .. code-block:: cpp + + #include + #include + + std::filesystem::path path = "/bin/ls"; + std::unique_ptr elf = LIEF::ELF::Parser::parse(path); + +:Dependencies: + + * Update nanobind to version ``3.0.1`` + +:Python: + + * Python 3.9 is no longer supported. nanobind 3 requires Python 3.10 or newer. +``` + +## 1.0.0 - July 12th, 2026 + +:::{admonition} Runtime +:class: tip + +LIEF now provides runtime features as described here: {ref}`Runtime ` +::: + +```{eval-rst} + +:BinaryNinja: + + * Add :ref:`Android JNI Analyzer ` + * The DWARF import plugin now supports comments + +:Ghidra: + + * Add support for generating DWARF from firmware or binaries without + a precise format or architecture (:issue:`1249`) + +:DWARF: + + * Add support for accessing the bit size of bit-field declarations (:issue:`1265`) + * Add support for accessing Enum entries: |lief-dwarf-types-Enum-entries| + * Add support for reading from or assigning a register to a function parameter + * Add support for reading from or assigning a description (``DW_AT_description``) + to a |lief-dwarf-function|, |lief-dwarf-variable|, or |lief-dwarf-lexical-block|: + + - |lief-dwarf-function-description| + - |lief-dwarf-variable-description| + - |lief-dwarf-lexical-block-description| + + * Enable the creation of nested |lief-dwarf-editor-Function-lexical-block| + * Add support for generating a C/C++ definition for a whole + |lief-dwarf-CompilationUnit| (|lief-dwarf-cu-to_decl|). The output of the + following ``to_decl()`` functions can now be configured through the new + |lief-declopt| structure: + + - |lief-dwarf-function-to_decl| + - |lief-dwarf-variable-to_decl| + - |lief-dwarf-type-to_decl| + - |lief-dwarf-cu-to_decl| + + .. code-block:: python + + import lief + + dbg = lief.dwarf.load("/bin/with_debug") + + opt = lief.DeclOpt() + opt.is_cpp = True + opt.indentation = 4 + + for cu in dbg.compilation_units: + print(cu.to_decl(opt)) + +:PDB: + + * Improve support and the API for ``LF_ENUM``: |lief-pdb-types-Enum| + * Improve support and the API for ``LF_PROCEDURE``: |lief-pdb-types-Function| + * Improve support and the API for ``LF_ARRAY``: |lief-pdb-types-Array| + * Improve support and the API for *simple* types: |lief-pdb-types-Simple| + * Improve support and the API for ``LF_ONEMETHOD``: |lief-pdb-types-Method| + * Add support for generating a C/C++ definition for a |lief-pdb-Function| + (|lief-pdb-function-to_decl|) and a |lief-pdb-CompilationUnit| + (|lief-pdb-cu-to_decl|), configurable with the new |lief-declopt| structure. + +:ELF: + + * Add support for ``DT_AUXILIARY`` tag: |lief-elf-DynamicEntryAuxiliary| + (:issue:`1159`). + * Add support for ``DT_FILTER`` tag: |lief-elf-DynamicEntryFilter| + * Add |lief-elf-parse_from_dump| to parse an ELF binary from a memory dump + +:COFF: + + * Add |lief-coff-section-coff_string| for accessing the full section name when + this name does not fit in 8 bytes. + +:Mach-O: + + * Add support for writing big-endian Mach-O binaries (:issue:`1236`) + * Introduce an API for selecting a specific Mach-O binary by architecture + from a FAT binary (:pr:`1283`) + * Add |lief-macho-fatbinary-create| to create a FAT binary from + a list of |lief-macho-binary| objects targeting different architectures + * Add support for |lief-macho-threadlocalvariables| + * Fix an extra byte being written after the thread state of an + ``LC_UNIXTHREAD``/``LC_THREAD`` command, which shifted the following + load commands by one byte (:issue:`1344`) + * Add support for editing the runtime tables of the ``LC_FUNCTION_VARIANTS`` + command and committing the changes on write: + |lief-macho-function-variants-command| + * Add a structured parser, editing API and writer for the + ``LC_FUNCTION_VARIANT_FIXUPS`` command: + |lief-macho-function-variant-fixups-command| + * Add support for the ``LC_LAZY_LOAD_DYLIB_INFO`` command: + |lief-macho-lazy-load-dylib-info-command| + * Add |lief-macho-parse_from_dump| to parse a Mach-O binary from a memory dump + +:PE: + + * Add setters for |lief-pe-importentry-iat-value| and |lief-pe-importentry-ilt-value| + * Add |lief-pe-binary-offset_to_rva| to convert a raw offset into a RVA + * Add |lief-pe-parse_from_dump| to parse a PE binary from a memory dump + * Update |lief-binary-offset_to_virtual_address| for PE binaries to + return an **absolute** virtual address instead of a RVA (:issue:`1318`) + * Add support for adding an |lief-pe-import| at a specific position: + |lief-pe-binary-add-import| (:pr:`1298`) + * Improve support for EFI binaries, such as ``bzImage`` (:pr:`1293`) + +:ObjC: + + * Add support for Objective-C categories (:issue:`1353`): |lief-objc-category|, + accessible through |lief-objc-metadata-categories| + +:Assembly: + + * Add support for iterating over the operands of MIPS, PowerPC, eBPF and + RISC-V instructions (``Register``, ``Immediate``, ``Memory`` and + ``PCRelative``): + + - |lief-assembly-mips-Instruction-operands| + - |lief-assembly-powerpc-Instruction-operands| + - |lief-assembly-ebpf-Instruction-operands| + - |lief-assembly-riscv-Instruction-operands| + +:Rust: + + .. warning:: + + The Minimum Supported Rust Version (MSRV) is now ``1.85.0`` (previously + ``1.74.0``). + + * The Rust FFI no longer relies on ``autocxx`` and ``bindgen``. It is now + built on top of plain ``cxx``, which simplifies the bindings and reduces + the iteration time + * The Rust bindings directory has been renamed from ``api/rust/cargo/`` to + ``api/rust/crates/`` + * Add support for the ``aarch64-linux-android`` and ``x86_64-linux-android`` + targets + +:C++: + + * Add ``LIEF_LIFETIMEBOUND`` annotations wrapping ``[[clang::lifetimebound]]`` + to leverage Clang's `lifetime analysis `_. + This helps detect dangling references at compile time for methods that return + references or iterators tied to an object's lifetime: + + .. code-block:: cpp + + // Clang can now warn about this dangling reference: + auto& hdr = LIEF::ELF::Parser::parse("a.out")->header(); + LIEF_INFO("{}", hdr.header_size()); + // /src/src/ELF/Binary.cpp:63:15: error: object whose reference is captured + // does not live long enough [-Werror,-Wlifetime-safety-use-after-scope] + // 63 | auto& hdr = LIEF::ELF::Parser::parse("a.out")->header(); + // | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // /src/src/ELF/Binary.cpp:63:47: note: destroyed here + // 63 | auto& hdr = LIEF::ELF::Parser::parse("a.out")->header(); + // | ^ + // /src/src/ELF/Binary.cpp:64:19: note: later used here + // 64 | LIEF_INFO("{}", hdr.header_size()); + +:Dependencies: + + * Update nanobind to version ``v2.13.x`` + * Update tl-expected to version ``1.3.1`` + * Update utfcpp to version ``4.0.9`` + * Update frozen to commit ``61dce5a`` + * Update spdlog to version ``1.17.0`` + * Update mbedtls to version ``4.0.0`` + +:Extended: + + * Use LLVM ``22.x`` + * Add support to directly download a package from the **History**: + + .. image:: ./_static/lief-extended-history-link.webp + :scale: 50 % + +:Python: + + * Python 3.8 is no longer supported + * Add support for the free-threaded Python builds. + The C++ core is now thread-safe with respect to its few static variables, + and can be used when the GIL is disabled (:issue:`1255`): + + .. code-block:: python + + from concurrent.futures import ThreadPoolExecutor + import lief + + def strip(path: str) -> None: + binary = lief.ELF.parse(path) + binary.strip() + binary.write(f"{path}.stripped") + + with ThreadPoolExecutor() as pool: + pool.map(strip, ["/bin/ls", "/bin/cat", "/bin/echo"]) +``` + +## 0.17.6 - March 18th, 2026 + +```{eval-rst} + +:ELF: + + * Fix alignment for ``PHDR/SHDR`` and improve ``TLS/RELR`` handling (:issue:`1315`) + * Skip ``NOBITS`` sections in layout calculations and improve index retrieval + (related to :issue:`1315`) + +:PE: + + * Fix IAT parsing issue by :github_user:`itamarga` in PR :pr:`1314`) +``` + +## 0.17.5 - March 8th, 2026 + +```{eval-rst} + +:ELF: + + * Add missing segments in X86_64 coredump parser (:issue:`1278`) + * Add TLSDESC_PLT and TLSDESC_GOT to ELF dynamic tags (:issue:`1311`) + * Fix dynamic entry shifting for Android relocations (:issue:`1309`) + +:MachO: + + * Fix ``DyldInfo::show_bindings`` integer overflow (:issue:`1313`) +``` + +## 0.17.4 - February 21st, 2026 + +```{eval-rst} + +:PE: + + * Fixed the address type in the TLS builder (by :github_user:`Immortalety` + in PR :pr:`1296`) + +:MachO: + + * Fixed |lief-macho-binary-virtual_address_to_offset| to properly handle + non-file-backed segments, such as ``__DATA`` segments containing only + ``ZEROFILL`` sections like ``__bss`` (by :github_user:`jalopezg-git` + in PR :pr:`1301`, fixing :issue:`1299`). + + * Fixed ``patch_relocation()`` to correctly process tagged pointers + (by :github_user:`jalopezg-git` in PR :pr:`1302`, fixing :issue:`1300`). + +:COFF: + + * Resolved a compilation conflict with the Windows ``minwindef.h`` macro + ``#define max``. + +:CMake: + + * Fixed compiler flag issues on Windows when compiling with ``clang-cl`` + (by :github_user:`sigewinnefish` in PR :pr:`1306`). + +:Python: + + * Bumped various Python backend build dependencies in + ``api/python/build-requirements.txt`` to support Python ``3.14`` when + compiling from sources (:issue:`1304`). +``` + +## 0.17.3 - January 24th, 2026 + +```{eval-rst} + +:PE: + + * Fixed bug with resources (:issue:`1281`). + * Fixed VA/RVA confusion in the PE builder (:issue:`1284`). +``` + +## 0.17.2 - January 3rd, 2026 + +```{eval-rst} + +:Mach-O: + + * Differentiate Mach-O FAT magic bytes and Java classes + (by :github_user:`wangmot`, :issue:`1215`). + +:Compilation: + + * Fixed MinGW compilation for some configurations + (by :github_user:`TheBrokenRail`, :commit:`dabbb72`). + +:PE: + + * Fixed alignment issue when rebuilding PE relocations (:issue:`1261`). + * Fixed infinite loop when processing v2 dynamic relocations + (by :github_user:`chengyongru`, fixing :issue:`1273`). + +:ELF: + + * Ensure that added DYN ELF sections are properly aligned + (by :github_user:`schmchrt`, fixing :issue:`1261`). + * Fixed GnuHash null dereference (:issue:`1277`). + +:Mach-O: + + * Fixed major performance issue when parsing certain Mach-O files + (by :github_user:`trevor-e`, fixing :issue:`1262`). +``` + +## 0.17.1 - October 25th, 2025 + +```{eval-rst} + +:ELF: + + * Fixed :issue:`1251`. + +:Compilation: + + * Fixed missing visibility (:pr:`1254`). + * Fixed incorrect paging computations that occurred when only a subset + of formats was enabled. + * Fixed include issue with the COFF format. +``` + +## 0.17.0 - September 14th, 2025 + +:::{admonition} BinaryNinja & Ghidra Plugins +:class: tip + +LIEF-based plugins for Binary Ninja and Ghidra have been bootstrapped here: + +- {ref}`Ghidra plugin ` +- {ref}`BinaryNinja plugin ` +::: + +:::{admonition} LIEF Tools +:class: tip + +I initiated a `Tools` section which aims at providing utilities based on LIEF (mostly +CLI): + +- {ref}`lief-patchelf ` +::: + +```{eval-rst} + +:Assembler: + + * Add support for :ref:`Contextual Assembly Patching ` + +:DSC: + + * Add enum for the latest dyld shared cache version introducing + changes in the header layout (``dyld-1284.13 - 2025-04-25``) + + .. code-block:: diff + + uint64_t dynamicDataOffset; + uint64_t dynamicDataMaxSize; + uint32_t tproMappingsOffset; + uint32_t tproMappingsCount; + + uint64_t functionVariantInfoAddr; + + uint64_t functionVariantInfoSize; + + uint64_t prewarmingDataOffset; + + uint64_t prewarmingDataSize; + }; + + * Add enum for the latest dyld shared cache version introducing + changes in the header layout (``dyld-1231.3 - 2024-09-24``) + + .. code-block:: diff + + uint64_t dynamicDataOffset; + uint64_t dynamicDataMaxSize; + + uint32_t tproMappingsOffset; + + uint32_t tproMappingsCount; + }; + + * Fix symbol resolution issue: :issue:`1127` + +:PE: + + * Please check :ref:`LIEF 0.17.0 - PE changelog ` + * :github_user:`luadebug` added support for pretty printing OID value and + non-roman characters in X509 certificates (see: :pr:`1226`, :issue:`1219`) + +:COFF: + + * Initial support for the COFF format: see the :ref:`COFF section ` + +:Mach-O: + + * Initial support for |lief-macho-function-variants-command| and + |lief-macho-function-variant-fixups-command| commands (``LC_FUNCTION_VARIANTS, LC_FUNCTION_VARIANT_FIXUPS``) + * Add support for |lief-macho-note-command| command (``LC_NOTE``) + * Add support for |lief-macho-atom-info| command (``LC_ATOM_INFO``) + * Add support for modifying Mach-O commands that embed variable-length data + (:issue:`1204`, :issue:`1125`). See: :ref:`RPath and Library Path Modification `. + + .. code-block:: python + + # Change library name + for lib in macho.libraries: + lib.name += "/some/path/lib.dylib" + + # Change rpath + for rpath in macho.rpaths: + rpath.path += '/a/very/long/path/that/needs/expansion' + + * Add |lief-macho-binary-find_library| + * To void ``#define`` conflicts with Apple SDK, the following enums have been renamed: + + .. tabs:: + + .. tab:: :fa:`brands fa-python` Python + + .. code-block:: diff + + - lief.MachO.FAT_MAGIC + + lief.MachO.MAGIC_FAT + + - lief.MachO.FAT_CIGAM + + lief.MachO.CIGAM_FAT + + - lief.MachO.Symbol.ORIGIN.LC_SYMTAB + + lief.MachO.Symbol.ORIGIN.SYMTAB + + - lief.MachO.Section.TYPE.S_4BYTE_LITERALS + + lief.MachO.Section.TYPE.IS_4BYTE_LITERALS + + - lief.MachO.Section.TYPE.S_8BYTE_LITERALS + + lief.MachO.Section.TYPE.IS_8BYTE_LITERALS + + - lief.MachO.Section.TYPE.S_16BYTE_LITERALS + + lief.MachO.Section.TYPE.IS_16BYTE_LITERALS + + + .. tab:: :fa:`regular fa-file-code` C++ + + .. code-block:: diff + + - MACHO_TYPES::MH_MAGIC + - MACHO_TYPES::MH_CIGAM + - MACHO_TYPES::MH_MAGIC_64 + - MACHO_TYPES::MH_CIGAM_64 + - MACHO_TYPES::FAT_MAGIC + - MACHO_TYPES::FAT_CIGAM + + + MACHO_TYPES::MAGIC + + MACHO_TYPES::CIGAM + + MACHO_TYPES::MAGIC_64 + + MACHO_TYPES::CIGAM_64 + + MACHO_TYPES::MAGIC_FAT + + MACHO_TYPES::CIGAM_FAT + + - Section::TYPE::S_16BYTE_LITERALS + + Section::TYPE::IS_16BYTE_LITERALS + + - Section::TYPE::S_4BYTE_LITERALS + + Section::TYPE::IS_4BYTE_LITERALS + + - Section::TYPE::S_8BYTE_LITERALS + + Section::TYPE::IS_8BYTE_LITERALS + + - Symbol::ORIGIN::LC_SYMTAB + + Symbol::ORIGIN::SYMTAB + +:ELF: + + * LIEF newly-inserted sections are now compatible with a ``strip`` after the + modification of the binary (see: :ref:`Adding a section/segment `) + * Enhance support for IA64 architecture. + * Introduce :attr:`lief.ELF.Segment.raw_flags` to access the raw (integer) + value of the flag + * If an ELF binary uses a custom page size, its value can be defined in the + parser configuration: |lief-elf-parser-config-page_size|. + * Add support for SH4 + * Add suport for x32/ILP32 ELF binaries (:issue:`1225`) + * Add support for S390x + * Better endianess support when writing back a binary. + * Enhance support for removing segments (:issue:`1233`): |lief-elf-binary-remove-segment| + * Enhance support for removing or modifying symbol versions (related to the + :ref:`lief-patchelf ` initiative) + * New doc section: :ref:`Symbol Versions ` + * New doc section: :ref:`R[UN]PATH Modification ` + +:DWARF: + + * LIEF extended can now process DWARF debug info in PE binaries + * Add support for creating DWARF: :ref:`DWARF Editor ` + (require extended version ``>= 0.17.0.2623``) + +:PDB: + + * Add |lief-pdb-is_pdb| + * Add support for CodeView symbols: ``S_COMPILE3, S_COMPILE2, S_BUILDINFO, S_ENVBLOCK``. + These symbols are exposed through the interface |lief-pdb-buildmetadata|, + which can be accessed using |lief-pdb-compilationunit-buildmetadata|. + This metadata provides build time information such as: + + .. code-block:: text + + Module Name : * Linker * + Build Metadata: + Frontend Version: 0.0.0.0 + Backend Version : 14.37.32825.0 + Tool Version : Microsoft (R) LINK + Language : LINK + Target : X64 + Environment: + cwd: C:\Users\romai\dev\rust\ast-grep + exe: C:\Program Files\Microsoft Visual Studio\2022\Community\[...] + pdb: C:\Users\romai\dev\rust\ast-grep\target\debug\deps\ast_grep.pdb + cmd: /NOLOGO /LIBPATH:C:\Users\romai\dev\rust\ast-grep\target\[...] + + + Module Name : std-4ee9ee8805e6ac55.std.ddad90bab7781587-cgu.0.rcgu.o + Object : C:\Users\romai\scoop\persist\rustup\.rustup\toolchains\[...] + Build Metadata: + Frontend Version: 1.74.0.0 + Backend Version : 17004.0.0.0 + Tool Version : clang LLVM (rustc version 1.74.0 (79e9716c9 2023-11-13)) + Language : RUST + Target : X64 + Build Info: + Current directory: /rustc/79e9716c980570bfd1f666e3b16ac583f0168962 + Build tool : C:\a\rust\rust\build\x86_64-pc-windows-msvc\stage1\bin\rustc.exe + Source file : library\std\src\lib.rs\@\std.ddad90bab7781587-cgu.0 + Command line : "-cc1" "--crate-name" "std" "--edition=2021" [...] + +:OAT: + + * Parsing Android OAT files requires to **explicitly** use :func:`lief.OAT.parse` + + .. code-block:: python + + import lief + + # Before LIEF 0.17.0 this function returned a lief.OAT.Binary object + lief.parse("CallDeviceId.oat") + + # Since LIEF 0.17.0 this function returns a lief.ELF.Binary object + lief.parse("CallDeviceId.oat") + + # Return a lief.OAT.Binary object + lief.OAT.parse("CallDeviceId.oat") + +:Abstraction: + + * Expose |lief-abstract-binary-page_size| + * Add |lief-abstract-binary-load_debug_info| to attach an external debug file + to a |lief-abstract-binary|. See these sections for more details: + :ref:`DWARF: Loading an external debug file ` + :ref:`PDB: Loading an external debug file ` + * Add |lief-debug-info-find_function_address| + +:Extended: + + * Fix issue in the Python bindings while trying to access ``lief.__LIEF_MAIN_COMMIT__`` + * Fix CMake issue with ``find_package(lief-extended)`` + * Use LLVM ``21.1.x`` + +:Build System: + + * LIEF is now available in `vcpkg `_. + Many thanks to :github_user:`luadebug` for this support. + +:Dependencies: + + * Move to tl-expected ``1.2.0`` + * Move to utfcpp ``4.0.6`` + * Move to mbedtls ``3.6.4`` + * Move to spdlog ``1.15.3`` + * Move to ``nlohmann/json`` ``3.12.0`` + * Upgrade nanobind to version ``v2.8.x`` + +:Utilities: + + * Add |lief-dump| +``` + +## 0.16.7 - October 5th, 2025 + +```{eval-rst} + +:Python: + + * Add wheels for Python 3.14 + +:Mach-O: + + * Fix ``has_nx`` (:pr:`1218`) + * Fix :issue:`1228` + +:ELF: + + * Fix :issue:`1241` + +:Other: + + * :pr:`1220` +``` + +## 0.16.6 - May 29th, 2025 + +```{eval-rst} + +:Compilation: + + * Fix missing header (:issue:`1192`) + * Fix GCC 15 issue (:issue:`1203`) + * Fix :issue:`1210` + +:Mach-O: + + * Fix use-after-move (:issue:`1212`) + * Fix :issue:`1206` + +:Python: + + * Fix Python logger warning + +:Other: + + * :issue:`1217` + * :pr:`1216` +``` + +## 0.16.5 - April 19th, 2025 + +```{eval-rst} + +:ELF: + + * Relax the condition over the ``DT_SYMENT`` entry (:issue:`1177`) + +:Mach-O: + + * Modifications on |lief-macho-encryptioninfo| are now committed when doing a + ``write()``. See: :issue:`1173` + +:Compilation: + + * Fix compilation issue when targeting Linux i386/i686 (:issue:`1189`) + * Better support for external ``fmt`` library + * Fix ``fmt`` unicode issue + * Fix missing ``cstdio`` (:issue:`1184`) + +:Packages: + + * Add Python, Rust, SDK packages for Windows ARM64 (``aarch64-pc-windows-msvc``) + * Add Python, Rust, SDK packages for Linux Musl ARM64 (``aarch64-unknown-linux-musl``) + * Add Python, Rust, SDK packages for Linux Musl i686 (``i686-unknown-linux-musl``) +``` + +## 0.16.4 - February 23rd, 2025 + +```{eval-rst} + +:Python: + + * Relax checks on the enum verification. As described in :issue:`1170` and + :issue:`1172`, an invalid enum led to an unrecoverable error. The new + behavior now returns the raw ``int`` value if it can't be converted into the + given enum. + + * Upgrade nanobind to version ``v2.5.0`` + +:PE: + + * Fix export forwarding issue (:issue:`1168`) + +:MachO: + + * Fix truncated ``nlist_t.n_type`` when rewriting a Mach-O binary +``` + +## 0.16.3 - February 1st, 2025 + +```{eval-rst} + +:ELF: + + * Fix issue when parsing the dynamic table with an invalid offset (bug found + by :github_user:`lebr0nli`) + * Fix endianness issue with ``IA64`` binaries (:issue:`1164`) + +:PE: + + * Fix missing original forwarded function name (:issue:`1166`) + +:Misc: + + * Add support for spdlog compiled with ``SPDLOG_WCHAR_FILENAMES`` (:issue:`1147`) +``` + +## 0.16.2 - January 1st, 2025 + +```{eval-rst} + +:Compilation: + + * Fix broken ``aarch64`` Python wheel which is related to a toolchain issue + (:issue:`1146`) +``` + +## 0.16.1 - December 26th, 2024 + +```{eval-rst} + +:MachO: + + * Various fixes from :github_user:`DzenIsRich` & :github_user:`peledins-zimperium` + Thanks to them, Mach-O modification is more reliable. + + * Fix issue when building with ``-DLIEF_MACHO=ON`` (see: :issue:`1138`) + +:Rust: + + * Fix min-rustc version issue (see: :commit:`75a27f0e`) + +:Compilation: + + * Fix missing ``LIEF_API`` visibility (:commit:`e01f92a0`, :pr:`1140`) +``` + +## 0.16.0 - December 10th, 2024 + +```{eval-rst} + +:Abstraction: + + * Add |get_int_from_virtual_address| to read an **integer** value + at a specific virtual address + + **C++** + + .. code-block:: cpp + + LIEF::Binary& bin; + + uint16_t short_value = bin.get_int_from_virtual_address(0x140002CC8); + + **Python** + + .. code-block:: python + + some_bin: lief.Binary = ... + long_value = some_bin.get_int_from_virtual_address(0x140002CC8, 4) + # or + long_value = some_bin.get_int_from_virtual_address(0x140002CC8, ctypes.sizeof(ctypes.c_uint32)) + + **Rust** + + .. code-block:: rust + + elf: &lief::elf::Binary + let value: i16 = elf.get_int_from_virtual_address::(0x401126).unwrap(); + + * Global code cleaning (especially, |lief-header-architectures| and + |lief-header-modes| is now more meaningful) + * Re-scope ``lief.ARCHITECTURES`` into |lief-header-architectures| + * Re-scope ``lief.MODES`` into |lief-header-modes| + * Re-scope ``lief.OBJECT_TYPES`` into |lief-header-object-types| + * Re-scope ``lief.ENDIANNESS`` into |lief-header-endianness| + + +:MachO: + + * Fix endianness support (:issue:`1110`) + * Add helpers to determine the platform targeted by a Mach-O binary: + + - |lief-macho-binary-is-ios| + - |lief-macho-binary-is-macos| + - |lief-macho-binary-platform| + + * Expose an iterator over the stub entries located in ``__stubs,__auth_stubs,__symbol_stub,__picsymbolstub4``: + + |lief-macho-binary-symbol_stubs| - |lief-macho-stub| + + * Add support for the ``LC_SUBCLIENT`` command: |lief-macho-subclient| + * Add support for the ``LC_ROUTINE/LC_ROUTINE64`` command: |lief-macho-routine| + * Expose an iterator for the indirect symbols in |lief-macho-dynamicsymbolcommand| + * Add |lief-macho-binary-bindings| + to iterate over the bindings info located in |lief-macho-dyldinfo| or + |lief-macho-chainedbindinginfo| + * Add |lief-macho-indirectbindinginfo| to represent a binding operation + inferred from the indirect symbol table. + + This can be handy if a Mach-O does not have the commands |lief-macho-dyldinfo| + or |lief-macho-chainedbindinginfo| (e.g. extracted shared cache library) + +:PE: + + * Fix authenticode error while reading RSA PKCS#1 1.5 padding + +:ELF: + + * Fix issue when multiple empty strings are present in the ``.symtab`` section + (:pr:`1124`) + * Add |lief-elf-relocation-resolve| to resolve the value of relocations + * Add support for eBPF relocations. + * Add support for ``GNU_PROPERTY_AARCH64_FEATURE_PAUTH`` GNU property note: + |lief-elf-aarch64pauth|. + * Add |lief-elf-binary-target-android| to check if an ELF targets Android + * Fix a critical error when rewriting ELF file with ``DT_RELR`` relocations. + This error leads to a crash of the modified binary. + * Fix error while (re)generating ELF's RELR relocations (:issue:`1097`) + * Add support for RISC-V architecture + * Fix bug when trying to remove a dynamic symbol that is associated with + multiple relocations (:issue:`1089`) + +:Rust: + + * Mutable API are progressively introduced: + + - ELF: + + - :rust:method:`lief::elf::Binary::write [struct]` + - :rust:method:`lief::elf::Binary::write_with_config [struct]` + - :rust:method:`lief::elf::Binary::add_library [struct]` + + - PE: + + - :rust:method:`lief::pe::Binary::write [struct]` + + - MachO: + + - :rust:method:`lief::macho::Binary::write [struct]` + - :rust:method:`lief::macho::Binary::write_with_config [struct]` + - :rust:method:`lief::macho::Binary::add_library [struct]` + + * Thanks to :github_user:`Huntragon` Rust bindings can be used without openssl (see: :pr:`1105`) + * Rust precompiled Linux packages are now supported for Debian 10 & Ubuntu 19.10. + Before, they require at least Debian 11 & Ubuntu 20.04 + * Add support for the ``x86_64-unknown-linux-musl`` target which allows to + generate full static executable. + * Add :rust:enum:`lief::elf::header::Arch` + * Add :rust:struct:`lief::elf::dynamic::Flags` + +:ObjC: + + + * The header-like generation (|lief-objc-metadata-to_decl|) is now including + method's address as a comment: + + **Before** + + .. code-block:: objc + + @interface GCKUIImageHints { + long long _imageType; + NSObject * _customData; + struct CGSize _imageSize; + } + + (bool)supportsSecureCoding:(GCKUIImageHints *)self :(SEL)id; + - (bool)isEqual:(GCKUIImageHints *)self :(SEL)id :(NSObject *)arg2; + + **After** + + .. code-block:: objc + + @interface GCKUIImageHints { + long long _imageType; + NSObject * _customData; + struct CGSize _imageSize; + } + // Address: 0x00001aa448 + + (bool)supportsSecureCoding:(GCKUIImageHints *)self :(SEL)id; + // Address: 0x00001aa5ec + - (bool)isEqual:(GCKUIImageHints *)self :(SEL)id :(NSObject *)arg2; + + * Fix |lief-objc-method-address| for *small* methods. + * The output of |lief-objc-metadata-to_decl_opt| can now be configured with + |lief-objc-declopt|. + +:DWARF: + + * Add |lief-dwarf-function-is-external| + * Add |lief-dwarf-cu-imported-functions| + * Add ``DW_TAG_typedef`` support + +:Extended: + + .. note:: + + * `LIEF extended `_ is now open to everyone + * C++ SDK is now available + * Rust package is now available + + * Initial assembler support: :ref:`Assembler ` + * Initial disassembler support: :ref:`Disassembler ` + * Linux Python wheels are now ``manylinux_2_27`` compliants. In other words, + they are working with a glibc from at least 2018. + * Support for :ref:`Dyld shared cache ` + * |lief-elf-symbol-demangled_name| is working on **all** platforms + (not only unix-based builds) + * |lief-macho-symbol-demangled_name| is working on **all** platforms + (not only unix-based builds) + * |lief-pe-delayimportentry-demangled_name| + * |lief-pe-importentry-demangled_name| + * |lief-pe-exportentry-demangled_name| + + .. code-block:: python + + pe = lief.PE.parse("some.exe") + + if exp := pe.get_export(): + for entry in exp.entries: + # e.g.void __cdecl Platform::Details::EventSourceUninitialize(void **) + print(entry.demangled_name) + + for imp in pe.imports: + for entry in imp.entries: + # e.g. void __cdecl std::_Xlength_error(char const *) + print(entry.demangled_name) + + * Add |demangle| to demangle symbols (c.f. :issue:`1054`) + * The extended version is now using a versioning matching LIEF regular version + +:Python Bindings: + + * Upgrade nanobind from ``1.8.0`` to ``2.4.0`` + * ``*.pyi`` stubs are now generated by nanobind (replacing mypy's stugen) + +:Dependencies: + + * Upgrade MbedTLS from ``3.2.1`` to ``3.6.1`` + +:doc: + + * Global restructuring of the documentation + + * Add Sphinx cross-reference support for Rust. For instance, this link: + :rust:method:`lief::elf::Binary::debug_info [struct]` references the + documentation of ``debug_info`` in the Rust documentation page. + + * Add cross-api menu directive. For instance, this *link*: |lief-dwarf-debug-info| + toggles a menu to access the documentation of DWARF's debug info for Rust, + Python & C++. +``` + +## 0.15.1 - July 23th, 2024 + +```{eval-rst} + +:MachO: + + * Fix missing commit for ``.hwx`` support +``` + +## 0.15.0 - July 21th, 2024 + +```{eval-rst} + +:Extended: + + .. note:: + + See: https://extended.lief.re and :ref:`extended-intro` + + * Add support for DWARF: :ref:`extended-dwarf` + * Add support for PDB: :ref:`extended-pdb` + * Add support for Objective-C: :ref:`extended-objc` + + +:Repo: + * ``master`` branch has been renamed ``main`` + +:Rust: + * First (beta) release of the bindings (c.f. :ref:`lief_rust_bindings`) + +:ELF: + * Add support to create custom notes (:issue:`1026`): + + .. code-block:: python + + elf: lief.ELF.Binary = ... + + elf += lief.ELF.Note.create( + name="my-custom-note", + original_type=lief.ELF.Note.TYPE.UNKNOWN, + description=list(b"Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed"), + section_name=".lief.note.custom" + ) + + config = lief.ELF.Builder.config_t() + config.notes = True + elf.write("/tmp/new-binary.elf", config) + + * Add :meth:`lief.ELF.Binary.get_relocated_dynamic_array` which allows + to get a **relocated** view of the of init/fini entries. This function can + handy ELF init array/fini array functions are defined through relocations. + See: :issue:`1058`, :issue:`626` + * Add support for QNX Stack note (:issue:`1065`) + * The ``static_symbols`` API functions has been renamed in ``symtab_symbols``. + + LIEF was naming symbols located in the ``.symtab`` sections as **static + symbols** in opposition to the ``.dynsym`` symbols. This naming can be + confusing since the concept of **static symbol** in a program is well + defined (i.e. ``static bool my_var``) and not applicable in this case. + + **Therefore, the ``xxx_static_symbols`` API is has been renamed + ``xxx_symtab_symbol``.** + + * Re-scope ``DYNAMIC_TAGS`` into :class:`lief.ELF.DynamicEntry.TAG` + * Re-scope ``E_TYPE`` into :class:`lief.ELF.Header.FILE_TYPE` + * Re-scope ``VERSION`` into :class:`lief.ELF.Header.VERSION` + * Re-scope ``ELF_CLASS`` into :class:`lief.ELF.Header.CLASS` + * Re-scope ``ELF_DATA`` into :class:`lief.ELF.Header.ELF_DATA` + * Re-scope ``OS_ABI`` into :class:`lief.ELF.Header.OS_ABI` + * Re-scope ``ELF_SECTION_TYPES`` into :class:`lief.ELF.Section.TYPE` + * Re-scope ``ELF_SECTION_FLAGS`` into :class:`lief.ELF.Section.FLAGS` + * Re-scope ``SYMBOL_BINDINGS`` into :class:`lief.ELF.Symbol.BINDING` + * Re-scope ``ELF_SYMBOL_TYPES`` into :class:`lief.ELF.Symbol.TYPE` + * Re-scope ``ELF_SYMBOL_VISIBILITY`` into :class:`lief.ELF.Symbol.VISIBILITY` + * Re-scope ``SEGMENT_TYPES`` into :class:`lief.ELF.Segment.TYPE` + * Re-scope ``ELF_SEGMENT_FLAGS`` into :class:`lief.ELF.Segment.FLAG` + * Re-scope ``DYNAMIC_FLAGS_1`` into :class:`lief.ELF.DynamicEntryFlags.FLAG` + * Re-scope ``DYNAMIC_FLAGS`` into :class:`lief.ELF.DynamicEntryFlags.FLAG` + * Re-scope ``DYNSYM_COUNT_METHODS`` into :class:`lief.ELF.ParserConfig.DYNSYM_COUNT` + * Re-scope ``RELOCATION_PURPOSES`` into :class:`lief.ELF.Relocation.PURPOSE` + * ``RELOC_x86_64``, ``RELOC_i386``, ... have been re-scoped **and merged** + into :class:`lief.ELF.Relocation.TYPE` + + * Add support for Android packed relocation format (``DT_ANDROID_REL{A}``) + * Add support for relative relocation format (``DT_RELR``) + +:PE: + * Authenticode: + Add partial support for the following PKCS #7 attributes: + + - ``1.3.6.1.4.1.311.3.3.1 - Ms-CounterSign`` (:class:`lief.PE.MsCounterSign`) + - ``1.3.6.1.4.1.311.10.3.28 - Ms-ManifestBinaryID`` (:class:`lief.PE.MsManifestBinaryID`) + - ``1.3.6.1.4.1.311.2.6.1 - SPC_RELAXED_PE_MARKER_CHECK_OBJID`` (:class:`lief.PE.SpcRelaxedPeMarkerCheck`) + - ``1.2.840.113549.1.9.16.2.47 - SIGNING_CERTIFICATE_V2`` (:class:`lief.PE.SigningCertificateV2`) + + - ``1.2.840.113549.1.9.16.1.4 - PKCS#9 TSTInfo`` (:class:`lief.PE.PKCS9TSTInfo`) + + * Add :attr:`lief.PE.CodeViewPDB.guid` attribute (:issue:`480`) + * Move ``lief.PE.OptionalHeader.computed_checksum`` to :meth:`lief.PE.Binary.compute_checksum` + + In previous versions of LIEF, :attr:`lief.PE.OptionalHeader.checksum` was + re-computed (on purpose) in the parsing phase. On large + binaries, this re-computation can have a **strong impact** on the performances. + Thus, this computation has been deferred to a dedicated method :meth:`lief.PE.Binary.compute_checksum` + + .. code-block:: python + + pe = lief.PE.parse("...") + # Before: + computed = pe.optional_header.computed_checksum + # Now: + computed = pe.compute_checksum() + +:MachO: + + * Add support to modify Mach-O rpath (see: :issue:`1074`) + * Add helper :attr:`lief.MachO.Binary.support_arm64_ptr_auth` to check if a + Mach-O binary is supporting ARM64 pointer authentication (arm64e) + * Fix **major performance issue when processing Mach-O binaries on Windows & macOS** + * Add generic :class:`lief.MachO.UnknownCommand` to support Apple private Load + commands not officially supported by LIEF. + * Re-scope ``LOAD_COMMAND_TYPES`` into :class:`lief.MachO.LoadCommand.TYPE` + * Re-scope ``FILE_TYPES`` into :class:`lief.MachO.Header.FILE_TYPE` + * Re-scope ``HEADER_FLAGS`` into :class:`lief.MachO.Header.FLAGS` + * Re-scope ``MACHO_SEGMENTS_FLAGS`` into :class:`lief.MachO.SegmentCommand.FLAGS` + * Re-scope ``MACHO_SECTION_TYPES`` into :class:`lief.MachO.Section.TYPE` + * Re-scope ``MACHO_SECTION_FLAGS`` into :class:`lief.MachO.Section.FLAGS` + * Re-scope ``REBASE_TYPES`` into :class:`lief.MachO.DyldInfo.REBASE_TYPE` + * Re-scope ``REBASE_OPCODES`` into :class:`lief.MachO.DyldInfo.REBASE_OPCODES` + * Re-scope ``BIND_OPCODES`` into :class:`lief.MachO.DyldInfo.BIND_OPCODES` + * Re-scope ``BINDING_CLASS`` into :class:`lief.MachO.DyldBindingInfo.CLASS` + * Re-scope ``BIND_TYPES`` into :class:`lief.MachO.DyldBindingInfo.TYPE` + * Re-scope ``EXPORT_SYMBOL_FLAGS`` into :class:`lief.MachO.ExportInfo.FLAGS` + * Re-scope ``EXPORT_SYMBOL_KINDS`` into :class:`lief.MachO.ExportInfo.KIND` + * Re-scope ``RELOCATION_ORIGINS`` into :class:`lief.MachO.Relocation.ORIGIN` + * Re-scope ``SYMBOL_ORIGINS`` into :class:`lief.MachO.Symbol.ORIGIN` + * Re-scope ``VM_PROTECTIONS`` into :class:`lief.MachO.SegmentCommand.VM_PROTECTIONS` + * Re-scope ``CPU_TYPES`` into :class:`lief.MachO.Header.CPU_TYPE` + +:CMake: + + * ``LIEFConfig.cmake`` is now installed in ``/lib/cmake/LIEF/`` + instead of ``/share/LIEF/cmake/`` + + +:Python Bindings: + + * Add :func:`lief.disable_leak_warning` to disable Nanobind warning about "leaks". + + .. warning:: + + These warnings does not necessarily mean that LIEF leak objects. These + warnings might happen in `Cyclic garbage collection `_. + +:Documentation: + + * Add icons + * Include inheritance diagram for Python API (e.g. :class:`lief.ELF.Note`) +``` + +## 0.14.1 - February 11th, 2024 + +```{eval-rst} + +:ELF: + * Fix regression in Symbol Version Definition processing (:issue:`1014`) + +:PE: + * Address :issue:`1016` by creating aliases: + + - :attr:`lief.PE.ContentInfo.digest` to :attr:`lief.PE.SpcIndirectData.digest` + - :attr:`lief.PE.ContentInfo.digest_algorithm` to :attr:`lief.PE.SpcIndirectData.digest_algorithm` + +:Python: + + * Fix regression in iterator's performances +``` + +## 0.14.0 - January 20, 2024 + +```{eval-rst} + +:ELF: + * Add support for the GNU note properies (:issue:`975`). + + :Example: + + .. code-block:: python + + elf = lief.ELF.parse("...") + note = elf.get(lief.ELF.Note.TYPE.GNU_PROPERTY_TYPE_0) + aarch64_feat: lief.ELF.AArch64Feature = note.find(lief.ELF.NoteGnuProperty.Property.TYPE.AARCH64_FEATURES) + if lief.ELF.AArch64Feature.FEATURE.BTI in aarch64_feat.features: + print("BTI supported") + + See: + + - :class:`lief.ELF.NoteGnuProperty` + - :class:`lief.ELF.AArch64Feature` + - :class:`lief.ELF.NoteNoCopyOnProtected` + - :class:`lief.ELF.StackSize` + - :class:`lief.ELF.X86Features` + - :class:`lief.ELF.X86ISA` + + + * Refactoring of the ELF note processing + * Fix relocation issue when using ``-Wl,--emit-relocs`` (c.f. :issue:`897` / :pr:`898` by :github_user:`adamjseitz`) + * Improve the computation of the dynamic symbols thanks to :github_user:`adamjseitz` (c.f. :issue:`922`) + * Add support for the LoongArch architecture thanks to :github_user:`loongson-zn` (c.f. :pr:`921`) + + * Add a :class:`lief.ELF.ParserConfig` interface that can be used to tweak + which parts of the ELF format should be parsed. + + :Example: + + .. code-block:: python + + config = lief.ELF.ParserConfig() + + # Skip parsing static and dynamic symbols + config.parse_static_symbols = False + config.parse_dyn_symbols = False + + elf = lief.ELF.parse("target.elf", config) + +:MachO: + + * The *fileset name* is now stored in :attr:`lief.MachO.Binary.fileset_name` + (instead of `lief.MachO.Binary.name`) + +:PE: + * ``RESOURCE_SUBLANGS`` has been removed + * ``RESOURCE_LANGS`` is now defined in a dedicated header: ``LIEF/PE/resources/langs.hpp`` + * ``RESOURCE_TYPES`` is now scoped in ``ResourcesManager::TYPE`` + * ``GUARD_CF_FLAGS`` is now scoped as :class:`~lief.PE.LoadConfigurationV1.IMAGE_GUARD` in + :class:`lief.PE.LoadConfigurationV1` + * ``SECTION_CHARACTERISTICS`` is now scoped within the + :class:`~lief.PE.Section` class instead of being globally defined: + + .. code-block:: python + + # Before + lief.PE.SECTION_CHARACTERISTICS.CNT_CODE + # Now: + lief.PE.Section.CHARACTERISTICS.CNT_CODE + * ``DATA_DIRECTORY`` is now scoped within the + :class:`~lief.PE.DataDirectory` class instead of being globally defined: + + .. code-block:: python + + # Before + lief.PE.DATA_DIRECTORY.IAT + # Now: + lief.PE.DataDirectory.TYPES.IAT + + * ``MACHINE_TYPES`` and ``HEADER_CHARACTERISTICS`` are now scoped within the + :class:`~lief.PE.Header` class instead of being globally defined: + + .. code-block:: python + + # Before + lief.PE.MACHINE_TYPES.AMD64 + # Now: + lief.PE.Header.MACHINE_TYPES.AMD64 + + * :attr:`lief.PE.Header.characteristics` now returns a + `list`/`std::vector` instead of a ``set``. + * :attr:`lief.PE.OptionalHeader.dll_characteristics_lists` now returns a + ``list``/``std::vector`` instead of a ``set``. + * ``SUBSYSTEM`` and ``DLL_CHARACTERISTICS`` are now scoped within the + :class:`~lief.PE.OptionalHeader` class instead of being globally defined: + + .. code-block:: python + + # Before + lief.PE.SUBSYSTEM.NATIVE + # Now: + lief.PE.OptionalHeader.SUBSYSTEM.NATIVE + * :attr:`lief.PE.DosHeader.used_bytes_in_the_last_page` has been renamed in + :attr:`lief.PE.DosHeader.used_bytes_in_last_page` + * Refactoring of the Debug directory processing: + :class:`lief.PE.Debug` is now the root class of: + :class:`lief.PE.CodeView` / :class:`lief.PE.CodeView`, :class:`lief.PE.Pogo`, + :class:`lief.PE.Repro`. + + The parsing logic has been cleaned and the tests updated. + * Add a :class:`lief.PE.ParserConfig` interface that can be used to tweak + which parts of the PE format should be parsed (:issue:`839`). + + :Example: + + .. code-block:: python + + config = lief.PE.ParserConfig() + + # Skip parsing PE authenticode + config.parse_signature = False + + pe = lief.PE.parse("pe.exe", config) + +:Abstraction: + + * ``LIEF::EXE_FORMATS`` is now scoped in ``LIEF::Binary::FORMATS`` + * All the `Binary` classes now implement `classof`: + + .. code-block:: cpp + + std::unique_ptr bin = LIEF::Parser::parse("..."); + if (LIEF::PE::Binary::classof(bin.get())) { + auto& pe_file = static_cast(*bin); + } + +:General Design: + + * Python parser functions (like: :func:`lief.PE.parse`) now accept `os.PathLike` + arguments like `pathlib.Path` (:issue:`974`). + * Remove the `lief.Binary.name` attribute + * LIEF is now compiled with C++17 (the API remains C++11 compliant) + * Switch to `nanobind `_ for the + Python bindings. + * CI are now more efficient. + * The Python documentation for properties now contains the type of the + property. +``` + +## 0.13.2 - June 17, 2023 + +```{eval-rst} + +:PE: + + Fix authenticode inconsitency (:issue:`932`) + +:ELF: + + Fix missing undef (:issue:`929`) +``` + +## 0.13.1 - May 28, 2023 + +```{eval-rst} + +:PE: + + * Fix PE authenticode verification issue in the case of special characters (:issue:`912`) + +:Misc: + + * Fix mypy stubs (:issue:`909`) + * Fix missing include (:issue:`918`) + * Fix C99 comments (:issue:`916`) + * Fix AArch64 docker image (:issue:`904`) +``` + +## 0.13.0 - April 9, 2023 + +```{eval-rst} + +:ELF: + + * Fix overflow issue in segments (c.f. :issue:`845` found by :github_user:`liyansong2018`) + * Fix missing relationship between symbols and sections (c.f. :issue:`841`) + * Fix coredump parsing issue (c.f. :issue:`830` found by :github_user:`Lan1keA`) + * Fix and (re)enable removing dynamic symbols (c.f. :issue:`828`) + * Add support for `NT_GNU_BUILD_ATTRIBUTE_OPEN` and `NT_GNU_BUILD_ATTRIBUTE_FUNC` (c.f. :issue:`816`) + * [CVE-2022-38497] Fix ELF core parsing issue (:issue:`766` found by :github_user:`CCWANG19`) + * [CVE-2022-38306] Fix a heap overflow found by :github_user:`CCWANG19` (:issue:`763`) + * :github_user:`aeflores` fixed an issue when there are multiple versions associated with a symbol + (see: :issue:`749` for the details). + * Handle binaries compiled with the `-static-pie` flag correctly (see: :issue:`747`) + * Add support for modifying section-less binaries. The ELF :class:`~lief.ELF.Section` objects gain + the :meth:`lief.ELF.Section.as_frame` method which defines the section as a *framed* section. + + A framed section is a section that concretely does not wraps data and can be corrupted. + + :Example: + + .. code-block:: python + + elf = lief.parse("/bin/ssh") + text = elf.get_section(".text").as_frame() + + # We can now corrupt all the fields of the section + text.offset = 0xdeadc0de + text.size = 0xffffff + text.address = 0x123 + + elf.write("/tmp/out") + + * Add API to precisely define how the segments table should be relocated. + One might want to enforce a certain ELF layout while adding sections/ segments. + It is now possible to call the method: :meth:`~lief.ELF.Binary.relocate_phdr_table` + to define how the segments table should be relocated for welcoming the + new sections/segments: + + .. code-block:: python + + elf = lief.parse("...") + # Enforce a specific relocation type: + # The new segments table will be shift at the end + # of the file + elf.relocate_phdr_table(Binary.PHDR_RELOC.FILE_END) + + # Add sections/segments + # [...] + elf.write("out.elf") + + See: + + - :meth:`lief.ELF.Binary.relocate_phdr_table` + - :class:`lief.ELF.Binary.PHDR_RELOC` + +:MachO: + + * Add :attr:`~lief.MachO.Binary.rpaths` iterator (:issue:`291`) + * Add support for parsing Mach-O in memory + * Fix a memory issue (found by :github_user:`bladchan` via :issue:`806`) + * [CVE-2022-40923] Fix parsing issue (:issue:`784` found by :github_user:`bladchan`) + * [CVE-2022-40922] Fix parsing issue (:issue:`781` found by :github_user:`bladchan`) + * [CVE-2022-38307] Fix a segfault when the Mach-O binary does not have segments (found by :github_user:`CCWANG19` via :issue:`764`) + * Enable to create exports + * Fix the layout of the binaries modified by LIEF such as they can be (re)signed. + * Add support for `LC_DYLD_CHAINED_FIXUPS` and `LC_DYLD_EXPORTS_TRIE` + * Global enhancement when modifying the `__LINKEDIT` content + * Add API to get a :class:`~lief.MachO.Section` from a specified segment's name and section's name. + + :Example: + + .. code-block:: python + + sec = bin.get_section("__DATA", "__objc_metadata") + + * Add API to remove a :class:`~lief.MachO.Section` from a specified segment's name and section's name. + + :Example: + + .. code-block:: python + + sec = bin.remove_section("__DATA", "__objc_metadata") + + * Add :attr:`lief.MachO.Binary.page_size` + +:PE: + + * The Python API now returns `bytes` objects instead of `List[int]` + * Remove :meth:`lief.PE.ResourceNode.sort_by_id` + * Fix the ordering of children of :class:`~lief.PE.ResourceNode` + * Remove deprecated functions related to PE hooking. + * Add support for new PE LoadConfiguration structures. + +:DEX: + + * Fix multiple parsing issues raised by :github_user:`bladchan` + +:Other: + + * [CVE-2022-38497]: :issue:`765` found by :github_user:`CCWANG19` + * [CVE-2022-38495]: :issue:`767` found by :github_user:`CCWANG19` + +:General Design: + + * :github_user:`ZehMatt` added the support to write LIEF binaries object through a `std::ostream` interface + (:commit:`9d55f538602989c69454639565910884c5c5ac7c`) + * Remove the exceptions + * The library contains less static initializers which should improve the loading time. + +:Python Bindings: + + * Move to a build system compliant with ``pyproject.toml`` + * Provide typing stubs: :issue:`650` + * PyPI releases no longer provide source distribution (`sdist`) + +:Dependencies: + + * Move to spdlog 1.11.0 + * Move to `Pybind11 - 2.10.1 `_ + * Move to nlohmann/json 3.11.2 + * Move to MbedTLS 3.2.1 + * Move to utfcpp 3.2.1 +``` + +## 0.12.3 - November 1, 2022 + +This release contains several security fixes: + +> - [CVE-2022-38497] Fix ELF core parsing issue ({issue}`766` found by {github_user}`CCWANG19`) +> - [CVE-2022-38306] Fix a heap overflow found by {github_user}`CCWANG19` ({issue}`763`) +> - Fix a memory issue (found by {github_user}`bladchan` via {issue}`806`) +> - [CVE-2022-40923] Fix parsing issue ({issue}`784` found by {github_user}`bladchan`) +> - [CVE-2022-40922] Fix parsing issue ({issue}`781` found by {github_user}`bladchan`) +> - [CVE-2022-38307] Fix a segfault when the Mach-O binary does not have segments (found by {github_user}`CCWANG19` via {issue}`764`) + +## 0.12.1 - April 08, 2022 + +```{eval-rst} + +:ELF: + * Fix section inclusion calculations (:pr:`692`) + +:PE: + * Fix parsing regressions (:issue:`689`, :issue:`687`, :issue:`686`, :issue:`685`, :issue:`691`, :issue:`693`) + +:Compilation: + * Nightly builds are now upload to Saleway's S3 server: + + - https://lief.s3-website.fr-par.scw.cloud/latest/lief + - https://lief.s3-website.fr-par.scw.cloud/latest/sdk + + * Fix `GLIBCXX_USE_CXX11_ABI=1` ABI issue (see: :issue:`683`) +``` + +## 0.12.0 - March 25, 2022 + +```{eval-rst} + +:ELF: + * :github_user:`ahaensler` added the support to insert and assign a :class:`lief.ELF.SymbolVersionAuxRequirement` (see: :pr:`670`) + * Enhance the ELF parser to support corner cases described by `netspooky `_ in : + + - https://tmpout.sh/2/14.html (*84 byte aarch64 ELF*) + - https://tmpout.sh/2/3.html (*Some ELF Parser Bugs*) + + * New ELF Builder which is more efficient in terms of speed and + in terms of number of segments added when modifying binaries (see: https://lief-project.github.io/blog/2022-01-23-new-elf-builder/) + + * :github_user:`Clcanny` improved (see :pr:`507` and :pr:`509`) the reconstruction of the dynamic symbol table + by sorting local symbols and non-exported symbols. It fixes the following warning when parsing + a modified binary with ``readelf`` + + .. code-block:: text + + Warning: local symbol 29 found at index >= .dynsym's sh_info value of 1 + +:MachO: + * Change the layout of the binaries generated by LIEF such as they are compliant with ``codesign`` checks + * The API to configure the MachO parser has been redesigned to provide a better granularity + + .. code-block:: python + + config = lief.MachO.ParserConfig() + config.parse_dyld_bindings = False + config.parse_dyld_exports = True + config.parse_dyld_rebases = False + + lief.MachO.parse("/tmp/big.macho", config) + + * :github_user:`LucaMoroSyn` added the support for the ``LC_FILESET_ENTRY``. This command is usually + found in kernel cache files + * ``LIEF::MachO::Binary::get_symbol`` now returns a pointer (instead of a reference). If the symbol + can't be found, it returns a nullptr. + * Add API to select a :class:`~lief.MachO.Binary` from a :class:`~lief.MachO.FatBinary` by its architecture. See: + :meth:`lief.MachO.FatBinary.take`. + + .. code-block:: python + + fat = lief.MachO.parse("/bin/ls") + fit = fat.take(lief.MachO.CPU_TYPES.x86_64) + + * Handle the `0x0D` binding opcode (see: :issue:`524`) + * :github_user:`xhochy` fixed performances issues in the Mach-O parser (see :pr:`579`) + +:PE: + * Adding :attr:`lief.PE.OptionalHeader.computed_checksum` that re-computes the :attr:`lief.PE.OptionalHeader.checksum` + (c.f. issue :issue:`660`) + * Enable to recompute the :class:`~lief.PE.RichHeader` (issue: :issue:`587`) + + - :meth:`~lief.PE.RichHeader.raw` + - :meth:`~lief.PE.RichHeader.hash` + + * Add support for PE's delayed imports. see: + + - :class:`~lief.PE.DelayImport` / :class:`~lief.PE.DelayImportEntry` + - :attr:`~lief.PE.Binary.delay_imports` + + * :attr:`lief.PE.LoadConfiguration.reserved1` has been aliased to :attr:`lief.PE.LoadConfiguration.dependent_load_flags` + * :attr:`lief.PE.LoadConfiguration.characteristics` has been aliased to :attr:`lief.PE.LoadConfiguration.size` + * Thanks to :github_user:`gdesmar`, we updated the PE checks to support PE files that have a corrupted + :attr:`lief.PE.OptionalHeader.magic` (cf. :issue:`644`) + +:DEX: + * :github_user:`DanielFi` added support for DEX's fields (see: :pr:`547`) + +:Abstraction: + * Abstract binary imagebase for PE, ELF and Mach-O (:attr:`lief.Binary.imagebase`) + * Add :meth:`lief.Binary.offset_to_virtual_address` + * Add PE imports/exports as *abstracted* symbols + +:Compilation & Integration: + * :github_user:`ekilmer` updated and modernized the CMake integration files through the PR: :pr:`674` + * Enable to use a pre-compiled version of spdlog. This feature aims + at improving compilation time when developing on LIEF. + + One can provide path to spdlog install through: + + .. code-block:: console + + $ python ./setup.py --spdlog-dir=path/to/lib/cmake/spdlog [...] + # or + $ cmake -DLIEF_EXTERNAL_SPDLOG=ON -Dspdlog_DIR=path/to/lib/cmake/spdlog ... + + * Enable to feed LIEF's dependencies externally (c.f. :ref:`lief_third_party`) + * Replace the keywords ``and``, ``or``, ``not`` with ``&&``, ``||`` and ``!``. + +:Dependencies: + * Upgrade to MbedTLS 3.1.0 + * Upgrade Catch2 to 2.13.8 + * The different dependencies can be *linked* externally (cf. above and :ref:`lief_third_party`) + +:Documentation: + * New section about the errors handling (:ref:`err_handling`) and the upcoming + deprecation of the exceptions. + * New section about how to compile LIEF for debugging/developing. See: :ref:`lief_debug` + +:General Design: + + :span: + + LIEF now exposes Section/Segment's data through a `span` interface. + As `std::span` is available in the STL from C++20 and the LIEF public API aims at being + C++11 compliant, we expose this `span` thanks to `tcbrindle/span `_. + This new interface enables to avoid copies of ``std::vector`` which can be costly. + With this new interface, the original ``std::vector`` can be retrieved as follows: + + .. code-block:: cpp + + auto bin = LIEF::ELF::Parser::parse("/bin/ls"); + + if (const auto* section = bin->get_section(".text")) { + LIEF::span text_ref = section->content(); + std::vector copy = {std::begin(text_ref), std::end(text_ref)}; + } + + In Python, span are wrapped by a **read-only** `memory view `_. + The original *list of bytes* can be retrieved as follows: + + .. code-block:: python + + bin = lief.parse("/bin/ls") + section = bin.get_section(".text") + + if section is not None: + memory_view = section.content + list_of_bytes = list(memory_view) + + :Exceptions: + + .. warning:: + + We started to refactor the API and the internal design to remove C++ exceptions. + These changes are described a the dedicated blog (`LIEF RTTI & Exceptions `_) + + To highlighting the content of the blog for the end users, + functions that returned a **reference and which threw an exception** in the case + of a failure are now returning a **pointer that is set to nullptr** in the case of a failure. + + If we consider this original code: + + .. code-block:: cpp + + LIEF::MachO::Binary& bin = ...; + + try { + LIEF::MachO::UUIDCommand& cmd = bin.uuid(); + std::cout << cmd << "\n"; + } catch (const LIEF::not_found&) { + // ... dedicated processing + } + + // Other option with has_uuid() + if (bin.has_uuid()) { + LIEF::MachO::UUIDCommand& cmd = bin.uuid(); + std::cout << cmd << "\n"; + } + + It can now be written as: + + .. code-block:: cpp + + LIEF::MachO::Binary& bin = ...; + + if (LIEF::MachO::UUIDCommand* cmd = bin.uuid();) { + std::cout << *cmd << "\n"; + } else { + // ... dedicated processing as it is a nullptr + } + + // Other option with has_uuid() + if (bin.has_uuid()) { // It ensures that it is not a nullptr + LIEF::MachO::UUIDCommand& cmd = *bin.uuid(); + std::cout << cmd << "\n"; + } + + .. seealso:: + + - :ref:`Error Handling section` + - `List of the functions that changed `_ +``` + +## 0.11.X - Patch Releases + +(release-0115)= + +### 0.11.5 - May 22, 2021 + +- Remove usage of `not` in public headers ({commit}`b8e825b464418de385146bb3f89ef6126f4de5d4`) + +```{eval-rst} + +:ELF: + * :github_user:`pdreiter` fixed the issue :issue:`418` + +:PE: + * Fix issue when computing :attr:`lief.PE.Binary.sizeof_headers` (:commit:`ab3f073ac0c60d8453070f83dd4dc04fe60aa0a5`) + +:MachO: + * Fix error on property :attr:`lief.MachO.BuildVersion.sdk` (see :issue:`533`) +``` + +(release-0114)= + +### 0.11.4 - March 09, 2021 + +```{eval-rst} + +:PE: + * Fix missing bound check when computing the authentihash +``` + +(release-0113)= + +### 0.11.3 - March 03, 2021 + +```{eval-rst} + +:PE: + * Add sanity check on the signature's length that could lead to a ``std::bad_alloc`` exception +``` + +(release-0112)= + +### 0.11.2 - February 24, 2021 + +```{eval-rst} + +:PE: + * Fix regression in the behavior of the PE section's name. One can now access the full + section's name (with trailing bytes) through :attr:`lief.PE.Section.fullname` (see: :issue:`551`) +``` + +(release-0111)= + +### 0.11.1 - February 22, 2021 + +```{eval-rst} + +:PE: + * :meth:`lief.PE.x509.is_trusted_by` and :meth:`lief.PE.x509.verify` now return + a better :attr:`lief.PE.x509.VERIFICATION_FLAGS` instead of just :attr:`lief.PE.x509.VERIFICATION_FLAGS.BADCERT_NOT_TRUSTED` + (see: :issue:`532`) + * Fix errors in the computation of the Authentihash +``` + +(release-0110)= + +## 0.11.0 - January 19, 2021 + +```{eval-rst} + +:ELF: + * :github_user:`mkomet` updated enums related to Android (see: :commit:`9dd641d380a5defd0a71a9f42dde2fe9c9cb1dbd`) + * :github_user:`aeflores` added MIPS relocations support in the ELF parser + * Fix :meth:`~lief.ELF.Binary.extend` on a ELF section (cf. issue :issue:`477`) + * Fix issue when exporting symbols on empty-gnu-hash ELF binary (:commit:`1381f9a115e6e312ac0ab3deb46a78e481b81796`) + * Fix reconstruction issue when the binary is prelinked (cf. issue :issue:`466`) + * Add ``DF_1_PIE`` flag + * Fix parsing issue of the ``.eh_frame`` section when the base address is not 0. + * :github_user:`JanuszL` enhanced the algorithm that computes the string table. + It moves from a ``N^2`` algorithm to a ``Nlog(N)`` (:commit:`1e0c4e81d4a3fd7282713f111193e42f198f8967`). + * Fix ``.eh_frame`` parsing issue (:commit:`b57f32333a85d0f172206bc5d20aabe2d7942738`) + * :github_user:`aeflores` fixed parsing issue in ELF relocations (:commit:`6c53646bb790acf28f2999527eafad30db7d6b69`) + * Add ``PT_GNU_PROPERTY`` enum + * Bug fix in the symbols table reconstruction (ELF) + +:PE: + * Enhance PE Authenticode. See `PE Authenticode `_ + * :func:`~lief.PE.get_imphash` can now generate the same value as pefile and Virus Total (:issue:`299`) + + .. code-block:: python + + pe = lief.parse("example.exe") + vt_imphash = lief.PE.get_imphash(pe, lief.PE.IMPHASH_MODE.PEFILE) + lief_imphash = lief.PE.get_imphash(pe, lief.PE.IMPHASH_MODE.DEFAULT) + + .. seealso:: + + :class:`lief.PE.IMPHASH_MODE` and :func:`lief.PE.get_imphash` + * Remove the padding entry (0) from the rich header + * ``lief.PE.LangCodeItem.items`` now returns a dictionary for which the values are **bytes** (instead of + ``str`` object). This change is related to ``utf-16`` support. + * :github_user:`kohnakagawa` fixed wrong enums values: :commit:`c03125045e32a9cd65c613585eb4d0385350c6d2`, :commit:`6ee808a1e4611d09c6cf0aea82a612be69584db9`, :commit:`cd05f34bae681fc8af4b5e7cc28eaef816802b6f` + * :github_user:`kohnakagawa` fixed a bug in the PE resources parser (:commit:`a7254d1ba935783f16effbc7faddf993c57e82f7`) + * Handle PE forwarded exports (issue :issue:`307`) + +:Mach-O: + * Add API to access either ``LC_CODE_SIGNATURE`` or ``DYLIB_CODE_SIGN_DRS`` (issue :issue:`476`) + * Fix issue when parsing twice a Mach-O file (issue :issue:`479`) + +:Dependencies: + * Replace ``easyloggingpp`` with `spdlog 1.8.1 `_ + * Upgrade ``frozen`` to 1.0.0 + * Upgrade ``json`` to 3.7.3 + * Upgrade ``pybind11`` to 2.6.0 + * Upgrade ``mbedtls`` to 2.16.6 + +:Documentation: + * :github_user:`aguinet` updated the `bin2lib tutorial `_ with the support + of the new glibc versions (:commit:`7884e57aa1d103f3bd37682e47f412bfe7a3aa34`) + * Global update and enable to build the documentation out-of-tree + * Changing the theme + +:Misc: + * Add Python 3.9 support + * ``FindLIEF.cmake`` deprecates ``LIEF_ROOT``. You should use ``LIEF_DIR`` instead. + + +:Logging: + + We changed the logging interface. The following log levels have been removed: + + - LOG_GLOBAL + - LOG_FATAL + - LOG_VERBOSE + - LOG_UNKNOWN + + We also moved from an class-interface based to functions. + + Example: + + .. code-block:: python + + lief.logging.disable() + lief.logging.enable() + lief.logging.set_level(lief.logging.LEVEL.INFO) + + See: :func:`lief.logging.set_level` + + .. note:: + + The log functions now output on ``stderr`` instead of ``stdout`` +``` + +## 0.10.1 - November 29, 2019 + +- Fix regression in parsing Python `bytes` +- Add Python API to demangle strings: `lief.demangle` + +## 0.10.0 - November 24, 2019 + +```{eval-rst} + +:ELF: + + * Add build support for ELF notes + * Add coredump support (:commit:`9fc3a8a43358f608cf18ddbe341e1d94b13cb9e0`) + * Enable to bind a relocation with a symbol (:commit:`a9f3cb8f9b4a1f2cdaa95eee4568ff0b162f77cd`) + + :Example: + + .. code-block:: python + + relocation = "..." + + symbol = lief.ELF.Symbol() + symbol.name = "printf123" + relocation.symbol = symbol + + * Add constructors (:commit:`67d924a2206c36cb9979d8b1b194b03b2d592e71`) + * Expose ELF destructors (:commit:`957384cd361c4a485470f877658af2bf052dbe0a`) + * Add ``remove_static_symbol`` (:commit:`c6779702b1fec3c67b0c19a36576830fe18bd9d9`) + * Add support for static relocation writing (:commit:`d1b98d69ade662e2471ce2905bf3fb247dfc3143`) + * Expose function to get strings located in the ``.rodata`` section (:commit:`02f4851c9f0c2bfa6fb4f51dab393a1db83b4851`) + * Export ELF ABI version (:commit:`8d7ec26a93800b0729c2c05be8c55c8318ba3b20`) + +:PE: + + * Improve PE Authenticode parsing (:commit:`535623de3aa4f8ddc34536331b802e2cbdc44faf`) + * Fix alignment issue when removing a PE section (:commit:`04dddd371080d731fab965b127cb15a91c57d53c`) + * Parse PE debug data directory as a list of debug entries (by :github_user:`1orenz0` - :commit:`fcc75dd87982e52d77a1c7ee7e674741a199e41b`) + * Add support to parse POGO debug entries (by :github_user:`1orenz0` - :commit:`3537440b8d0da6c9c3d00c25f7da8a04f29154d2`) + +:Mach-O: + + * Enhance Mach-O modifications by exposing an API to: + + - Add load commands + - Add sections + - Add segments + + See: :commit:`406115c8d097da0b61f00b2bb7b2442322ffc5d1` + + * Enable ``write()`` on FAT Mach-O (:commit:`16595316fd588619ea39b942817d6527e0601fbd`) + * Introduce Mach-O Build Version command (:commit:`6f967238fcd369210839605ab08c30d647a09a65`) + * Enable to remove Mach-O symbols (:commit:`616d739da513092e9ab7446654414b0929d5d5cf`) + * Add support for adding ``LC_UNIXTHREAD`` commands in a MachO (by :github_user:`nezetic` - :commit:`64d2597284149441fc734b251648ca917cd816e3`) + + +:Abstract Layer: + + * Expose ``remove_section()`` in the abstract layer (:commit:`918438c6bee52c8421d809bc3b42974165e5fa0b`) + * Expose ``write()`` in the abstract layer (:commit:`af4d48ed2e1f1b96687644f2fc4661fcbdb979a6`) + * Expose API to list functions found in a binary (:commit:`b5a08463ad63811e9e9432812406aadd74ab8c09`) + +:Android: + + * Add partial support for Android 9 (:commit:`bce9ebe17064b1ca16b00dc14eebb5d5dd440184`) + + +:Misc: + + * :github_user:`lkollar` added support for Python 3.8 in CI (Linux & OSX only) + * Update Pybind11 dependency to ``v2.4.3`` + * Enhance Python install + * Thanks to :github_user:`lkollar`, Linux CI now produces **manylinux1-compliant wheels** +``` + +Many thanks to the contributors: {github_user}`recvfrom`, {github_user}`pbrunet`, +{github_user}`mackncheesiest`, {github_user}`wisk`, {github_user}`nezetic`, +{github_user}`lkollar`, {github_user}`jbremer`, {github_user}`DaLynX`, {github_user}`1orenz0`, +{github_user}`breadchris`, {github_user}`0xbf00`, {github_user}`unratito`, {github_user}`strazzere`, +{github_user}`aguinetqb`, {github_user}`mingwandroid`, {github_user}`serge-sans-paille-qb`, {github_user}`yrp604`, +{github_user}`majin42`, {github_user}`KOLANICH` + +## 0.9.0 - June 11, 2018 + +LIEF 0.9 comes with new formats related to Android: OAT, DEX, VDEX and ART. It also fixes bugs and thanks to +{github_user}`yd0b0N`, ELF parser now supports big and little endian binaries. We also completed the JSON serialization of LIEF objects. + +### Features + +```{eval-rst} + +:MachO: + + * Enable to configure the Mach-O parser for quick parsing: :commit:`880b99aeef825786dd65aed286d7c4d23b62f564` + * Add :class:`lief.MachO.EncryptionInfo` command: :commit:`f4e2d81bfe84238d463bdb65297c296635e783b1` + * Add :class:`lief.MachO.RPathCommand` command: :commit:`196994dc089885ff2f1268e51f5514f7fcbc5cff` + * Add :class:`lief.MachO.DataInCode` command: :commit:`a16e1c4d13c7071fabe6a5a46b6d6c0fd9565b72` + * Add :class:`lief.MachO.SubFramework` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` + * Add :class:`lief.MachO.SegmentSplitInfo` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` + * Add :class:`lief.MachO.DyldEnvironment` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` + * API to show export-trie, rebase and binding opcodes: :commit:`5d56141061bfc27e3c971e9e474dc86fdaf0c6a9` + + +:PE: + + * Add PE Code View: :commit:`eab4a7614fdf6e9a180b1c638903310da0b83118` + + +:ELF: + + * Add support for ``.note.android.ident`` section: :commit:`d13db18214006ce654b723a882f70c3d7eabd20d` + * Enable to add unlimited number of dynamic entries: :commit:`a40da3e3b4b985b18a6e6026d594f524b7bae963` + * Add support for PPC relocations: :commit:`08b514191f661eeabbdf8ecacd1d7dd35a67ca54` + * Endianness support: :commit:`e794ac1502ee7636755bd441923368f88525a7d0` +``` + +### API + +> - {func}`lief.breakp` and {func}`lief.shell` +> - {func}`lief.parse` now support `io` streams as input +> - Parser now returns a `std::unique_ptr` instead of a raw pointer: {commit}`cd1cc457cf3d63cfc5faa945657887200cedb8b3` + +### Misc + +- Use [frozen](https://github.com/serge-sans-paille/frozen) for some internal `std::map` (If C++14 is supported by the compiler) + +### Acknowledgments + +- {github_user}`yd0b0N` for {pr}`162` and {pr}`166` (Endianness support and PPC relocations) +- {github_user}`0xbf00` for {pr}`128` (`LC_RPATH` command) +- {github_user}`illera88` for {pr}`118` + +## 0.8.3 + +- [Mach-O] Fix typo on comparison operator - {commit}`abbc264833894973f601f700b3abcc109904f722` + +## 0.8.2 + +- [ELF] Increase the upper limit of relocation number - {commit}`077bc329bdcc249cb8ed0b8bcb9630e1c9eede94` + +## 0.8.1 - October 18, 2017 + +- Fix an alignment issue in the ELF builder. See {commit}`8db199c04e9e6bcdbda165ab5c42d88218a0beb6` +- Add assertion on the setuptools version: {commit}`62e5825e27bb637c2f42f4d05690a100213beb03` + +## 0.8.0 - October 16, 2017 + +LIEF 0.8.0 mainly improves the MachO parser and the ELF builder. It comes with [Dockerfiles](https://github.com/lief-project/Dockerlief) for [CentOS](https://github.com/lief-project/Dockerlief/blob/v0.1.0/dockerlief/dockerfiles/centos.docker) and [Android](https://github.com/lief-project/Dockerlief/blob/v0.1.0/dockerlief/dockerfiles/android.docker). + +[LibFuzzer](https://llvm.org/docs/LibFuzzer.html) has also been integrated in the project to enhance the parsers + +### Features + +```{eval-rst} + +:Abstract Layer: + + * :class:`~lief.Relocation` are now abstracted from the 3 formats - :commit:`9503f2fc7b6c14bebd4c220bda4a243d87f14bd1` + * ``PIE`` and ``NX`` are abstracted through the :attr:`~lief.Binary.is_pie` and :attr:`~lief.Binary.has_nx` properties + * Add the :meth:`lief.Section.search` and :meth:`lief.Section.search_all` methods to look for patterns in the section's content. + +:ELF: + + * ``DT_FLAGS`` and ``DT_FLAGS_1`` are now parsed into :class:`~lief.ELF.DynamicEntryFlags` - :commit:`754b8afa2b41993e6c37d2d9003cebdccc641d23` + * Handle relocations of object files (``.o``) - :commit:`483b8dc2eabee3da29ce5e5ff2e25c2a3c9ca297` + + * Global enhancement of the ELF builder: + + One can now add **multiple** :class:`~lief.ELF.Section` or :class:`~lief.ELF.Segment` into an ELF: + + .. code-block:: python + + elf = lief.parse("/bin/cat") + + for i in range(3): + segment = Segment() + segment.type = SEGMENT_TYPES.LOAD + segment.content = [i & 0xFF] * 0x1000 + elf += segment + + + for i in range(3): + section = Section("lief_{:02d}".format(i)) + section.content = [i & 0xFF] * 0x1000 + elf += section + + elf.write("foo") + + .. code-block:: console + + $ readelf -l ./foo + PHDR 0x0000000000000040 0x0000000000000040 0x0000000000000040 + 0x00000000000061f8 0x00000000000061f8 R E 0x8 + INTERP 0x0000000000006238 0x0000000000006238 0x0000000000006238 + 0x000000000000001c 0x000000000000001c R 0x1 + [Requesting program interpreter: /lib64/ld-linux-x86-64.so.2] + LOAD 0x0000000000000000 0x0000000000000000 0x0000000000000000 + 0x000000000000d6d4 0x000000000000d6d4 R E 0x200000 + LOAD 0x000000000000da90 0x000000000020da90 0x000000000020da90 + 0x0000000000000630 0x00000000000007d0 RW 0x200000 + LOAD 0x000000000000f000 0x000000000040f000 0x000000000040f000 + 0x0000000000001000 0x0000000000001000 0x1000 + LOAD 0x0000000000010000 0x0000000000810000 0x0000000000810000 + 0x0000000000001000 0x0000000000001000 0x1000 + LOAD 0x0000000000011000 0x0000000001011000 0x0000000001011000 + 0x0000000000001000 0x0000000000001000 0x1000 + .... + + $ readelf -S ./foo + ... + [27] lief_00 PROGBITS 0000000002012000 00012000 + 0000000000001000 0000000000000000 0 0 4096 + [28] lief_01 PROGBITS 0000000004013000 00013000 + 0000000000001000 0000000000000000 0 0 4096 + [29] lief_02 PROGBITS 0000000008014000 00014000 + 0000000000001000 0000000000000000 0 0 4096 + + .. warning:: + + There are issues with executables statically linked with libraries that use ``TLS`` + + See: :issue:`98` + + + + + One can now add **multiple** entries in the dynamic table: + + .. code-block:: python + + elf = lief.parse("/bin/cat") + + elf.add_library("libfoo.so") + elf.add(DynamicEntryRunPath("$ORIGIN")) + elf.add(DynamicEntry(DYNAMIC_TAGS.INIT, 123)) + elf.add(DynamicSharedObject("libbar.so")) + + elf.write("foo") + + .. code-block:: console + + $ readelf -d foo + 0x0000000000000001 (NEEDED) Shared library: [libfoo.so] + 0x0000000000000001 (NEEDED) Shared library: [libc.so.6] + 0x000000000000000c (INIT) 0x7b + 0x000000000000000c (INIT) 0x3600 + ... + 0x000000000000001d (RUNPATH) Bibliothèque runpath:[$ORIGIN] + 0x000000000000000e (SONAME) Bibliothèque soname: [libbar.so] + + See :commit:`b94900ca7f500912bfe249cd534055942e28e34b`, :commit:`1e410e6c950c391f0d1a3f12cb6f8e4c9fb16539` for details. + + * :commit:`b2d36940f60eacfa602c115cb542e11c70b6841c` enables modification of the ELF interpreter without **length restriction** + + .. code-block:: python + + elf = lief.parse("/bin/cat") + elf.interpreter = "/a/very/long/path/to/another/interpreter" + elf.write("foo") + + .. code-block:: console + + $ readelf -l foo + Program Headers: + Type Offset VirtAddr PhysAddr + FileSiz MemSiz Flags Align + PHDR 0x0000000000000040 0x0000000000000040 0x0000000000000040 + 0x00000000000011f8 0x00000000000011f8 R E 0x8 + INTERP 0x000000000000a000 0x000000000040a000 0x000000000040a000 + 0x0000000000001000 0x0000000000001000 R 0x1 + [Requesting program interpreter: /a/very/long/path/to/another/interpreter] + .... + + * Enhancement of the dynamic symbols counting - :commit:`985d1249b72494a0e62f34042b3c9cbfa0706e90` + * Enable editing ELF's notes: + + .. code-block:: python + + elf = lief.parse("/bin/ls") + build_id = elf[NOTE_TYPES.BUILD_ID] + build_id.description = [0xFF] * 20 + elf.write("foo") + + .. code-block:: console + + $ readelf -n foo + Displaying notes found in: .note.gnu.build-id + Owner Data size Description + GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) + Build ID: ffffffffffffffffffffffffffffffffffffffff + + See commit :commit:`3be9dd0ff58ec68cb8813e01d6798c16b42dac22` for more details + +:PE: + + * Add :func:`~lief.PE.get_imphash` and :func:`~lief.PE.resolve_ordinals` functions - :commit:`a89bc6df4f242d7641292acdb184927449d14fff`, :commit:`dfa8e985c0561427a20088750693a004de587b1c` + * Parse the *Load Config Table* into :class:`~lief.PE.LoadConfiguration` (up to Windows 10 SDK 15002 with *hotpatch_table_offset*) + + .. code-block:: python + + from lief import to_json + import json + pe = lief.parse("some.exe") + loadconfig = to_json(pe.load_configuration)) # Using the lief.to_json function + pprint(json.loads(to_json(loadconfig))) + + .. code-block:: javascript + + {'characteristics': 248, + 'code_integrity': {'catalog': 0, + 'catalog_offset': 0, + 'flags': 0, + 'reserved': 0}, + 'critical_section_default_timeout': 0, + 'csd_version': 0, + 'editlist': 0, + ... + 'guard_cf_check_function_pointer': 5368782848, + 'guard_cf_dispatch_function_pointer': 5368782864, + 'guard_cf_function_count': 15, + 'guard_cf_function_table': 5368778752, + 'guard_flags': 66816, + 'guard_long_jump_target_count': 0, + 'guard_long_jump_target_table': 0, + 'guard_rf_failure_routine': 5368713280, + 'guard_rf_failure_routine_function_pointer': 5368782880, + ... + + For details, see commit: :commit:`0234e3b8bbb6f6f3490392f8c295fde284a99334` + + + + +:MachO: + + * The ``dyld`` structure is parsed (deeply) into :class:`~lief.MachO.DyldInfo`. It includes: + + * Binding opcodes + * Rebases opcodes + * Export trie + + See: :commit:`e2b81e0a8e187cae5f0f115241243a84ee7696b6`, :commit:`0e972d69ce35731867d82c047eef7eb9ea58e3ec`, :commit:`f7cc518dcfbb0557fd8d396144bf99a222d96705`, :commit:`782295bfb86d2a12584c5b16a37a26d56d1ee235`, :issue:`67` + + * Section relocations are now parsed into :attr:`lief.MachO.Section.relocations` - :commit:`29c8157ecc3b308bd521cb1daee3c2e3a2cffb28` + * ``LC_FUNCTION_STARTS`` is parsed into :class:`~lief.MachO.FunctionStarts` (:commit:`18d89198a0cc63ff291ae9110f465354c3b8f1e6`) + * ``LC_SOURCE_VERSION``, ``LC_VERSION_MIN_MACOSX`` and ``LC_VERSION_MIN_IPHONEOS`` are + parsed into :class:`~lief.MachO.SourceVersion` and :class:`~lief.MachO.VersionMin` (:commit:`c359778194db874669884aaccb52a4b05546bc07`, :commit:`0b4bb7d56520cd0ea08bbcb9530e5e0c96ac14ae`, :commit:`5b993117ed391db18ba775cabefa5f3981b2f1cc`, :issue:`45`) + * ``LC_THREAD`` and ``LC_UNIXTHREAD`` are now parsed into :class:`~lief.MachO.ThreadCommand` - :commit:`23257830b291c40a3aed92360040f2b0b11ffa72` +``` + +### Fixes + +Fix enums conflicts({issue}`32`) - {commit}`66b4cd4550ecf6cf3adb4900e6ad7ac33f1f7f32` + +Fix most of the memory leaks: {commit}`88dafa8db6e752393f69d73f68d295e91963b8da`, {commit}`d9b1436730b5d33a753e7dfa4301697a0c676066`, {commit}`554fa153af943b97a16fc4a52ab8459a3d0a9bc7`, {commit}`3602643f5d02a1c78c4de609cc47f193f3a8840f` + +```{eval-rst} + +:ELF: + + * Bug Fix when counting dynamic symbols from the GnuHash Table - :commit:`9036a2405dc44726f40cb77cab1bcbf371ab7a70` + +:PE: + + * Fix nullptr dereference in resources - :commit:`e90fe1b6c6f6a605390bcd1026435ce7503e7e6a` + * Handle encoding issues in the Python API - `8c7ceaf `_ + * Sanitize DLL names + +:MachO: + + * Fix :issue:`87`, :issue:`92` + * Fix memory leaks and *some* performance issues: :issue:`94` +``` + +### API + +In the C++ API `get_XXX()` getters have been renamed into `XXX()` (e.g. `get_header()` becomes `header()`) - {commit}`a4c69f7868da1de5d09aa26e977dedb720e36cbd`, {commit}`e805669865b130057413f456958a471d8f0ac0b1` + +```{eval-rst} + +:Abstract: + + * :class:`lief.Binary` gains the :attr:`~lief.Binary.format` property - :commit:`9391238f114fe963890777c2d8b90f2caaa5510c` + * :func:`lief.parse` can now takes a list of integers - :commit:`f330fa887d14d47f0683144430ac9695d3136561` + * Add :meth:`~lief.Binary.has_symbol` and :meth:`~lief.Binary.get_symbol` to :class:`lief.Binary` - :commit:`f121af5ca61a22fd83acc5c7094b50ed1cda8226` + * [Python API] Enhance the access to the abstract layer through the :attr:`~lief.Binary.abstract` attribute - :commit:`07138549a46db87c7b924fd072356030b1d5c6bc` + + One can now do: + + .. code-block:: python + + elf = lief.ELF.parse("/bin/ls") # Could be lief.MachO / lief.PE + abstract = elf.abstract # Return the lief.Binary object + + +:ELF: + + * Relocation gains the :attr:`~lief.ELF.Relocation.purpose` property - :commit:`b7b0bde4d51c54d8d226e5320b1b0d2cc48137c4` + * Add :attr:`lief.ELF.Binary.symbols` which return an iterator over **all** symbols (static and dynamic) - :commit:`af6ab65dc91169627f4fbb87cda92093eb699a1e` + * ``Header.sizeof_section_header`` has been renamed into :attr:`~lief.ELF.Header.section_header_size` - :commit:`d96971b0c3f8ff50add349957f571b8daa00708a` + * ``Segment.flag`` has been renamed into :attr:`~lief.ELF.Segment.flags` - :commit:`20a5f666deb89b06b79a1c4418ac938497fb658c` + * Add: + + * :attr:`~lief.ELF.Header.arm_flags_list`, + * :attr:`~lief.ELF.Header.mips_flags_list` + * :attr:`~lief.ELF.Header.ppc64_flags_list` + * :attr:`~lief.ELF.Header.hexagon_flags_list` + + to :class:`~lief.ELF.Header` - :commit:`730d045e05dca7ef3cd6a51d1175f280be356c70` + + To check if a given flag is set, one can do: + + .. code-block:: python + + >>> if lief.ELF.ARM_EFLAGS.EABI_VER5 in lief.ELF.Header "yes" else "no" + * [Python] Segment flags: ``PF_X``, ``PF_W``, ``PF_X`` has been renamed into :attr:`~lief.ELF.SEGMENT_FLAGS.X`, :attr:`~lief.ELF.SEGMENT_FLAGS.W`, :attr:`~lief.ELF.SEGMENT_FLAGS.X` - :commit:`d70ef9ec2c42619434352dbd7b74a835ebad7569` + * Add :attr:`lief.ELF.Section.flags_list` - :commit:`4937b7193a5760df85d0ac1567afc011a22cdb98` + * Enhancement for :attr:`~lief.ELF.DynamicEntryRpath` and :attr:`~lief.ELF.DynamicEntryRunPath`: :commit:`c375a47da7c4c524e886f9238f8dd51a44501087` + * Enhancement for :attr:`~lief.ELF.DynamicEntryArray`: :commit:`81440ce00cdfc793161a0dc394ada345307dc24b` + * Add some *operators* :commit:`3b200b30503847be4779447c76f5207d18daf77f`, :commit:`43bd06f8f32196454ee2305201f4e27b3a3c8a1e` + + + +:PE: + * Add some *operators* :commit:`5666351e07b7bf4a9624033f670d02b8806d2663` + +:MachO: + + * :func:`lief.MachO.parse` can now takes a list of integers - :commit:`f330fa887d14d47f0683144430ac9695d3136561` + * :func:`lief.MachO.parse` now returns a :class:`~lief.MachO.FatBinary` instead of a ``list`` of :class:`~lief.MachO.Binary`. :class:`~lief.MachO.FatBinary` has a similar API as a list - :commit:`3602643f5d02a1c78c4de609cc47f193f3a8840f` + * Add some *operators*: :commit:`cbe835484751396daffe7f8d238cbb85d66470ab` + +:Logging: + + Add an API to configure the logger - :commit:`4600c2ba8d7d17b5965c2b74faeb7e4d2128de17` + + Example: + + .. code-block:: python + + from lief import Logger + Logger.disable() + Logger.enable() + Logger.set_level(lief.LEVEL.INFO) + + See: :class:`lief.Logger` +``` + +### Build system + +- Add [`FindLIEF.cmake`](https://github.com/lief-project/LIEF/blob/e8ac976c994f6612e8dcca994032403c2d6f580f/scripts/FindLIEF.cmake) - {commit}`6dd8b10325e832a7520bf5ae3a588b9e022d0345` +- Add ASAN, TSAN, USAN, LSAN - {commit}`7f6aeb0d0d74eae886f4b312e12e8f71e1d5da6a` +- Add LibFuzzer - {commit}`7a0dc28ea29a30209e944ebcde27f7c0ab234651` + +### Documentation + +```{eval-rst} + +:References: + + * recomposer, bearparser, IAT_patcher, PEframe, Manalyze, MachOView, elf-dissector +``` + +### Acknowledgments + +- {github_user}`alvarofe` for {pr}`47` +- {github_user}`aguinet` for {pr}`55`, {pr}`61`, {pr}`65`, {pr}`77` +- {github_user}`jevinskie` for {pr}`75` +- {github_user}`liumuqing` for {pr}`80` +- {github_user}`Manouchehri` for {pr}`106` + +## 0.7.0 - July 3, 2017 + +### Features + +```{eval-rst} + +:Abstract Layer: + + * Add bitness (32bits / 64bits) - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` + * Add object type (Library, executable etc) - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` + * Add *mode* Thumbs, 16bits etc - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` + * Add endianness - :commit:`7ea08f72c43212f2e3f401b5c2c2614bc9aab8de`, :issue:`29` + +:ELF: + + * Enable dynamic symbols permutation - :commit:`2dea7cb6d631b69995567e056a97e526f588b8ff` + * Fully handle section-less binaries - :commit:`de40c068316b3334e4c8d81ecb3efc177ab24c3b` + * Parse ELF notes - :commit:`241aac7bedaf18ab5e3f0c9775a8a51cb0b40a3e` + * Parse SYSV hash table - :commit:`afa74cee88f730acef84fe6d9c984455a28463e7`, :issue:`36` + * Add relocation size - :commit:`f1766f2c297caed636c7f32730cd10b62bfcc757` + +:PE: + + * Parse PE Overlay - :commit:`e0634c1cf6d12fbdc5bcc1745059005e46e5d805` + * Enable PE Hooking - :commit:`24f6b7213647469e269ead9441d78204162d08ec` + * Parse and rebuilt dos stub - :commit:`3f0639712617007e2e0431cb5eeb9be204c5d74b` + * Add a *resources manager* to provide an enhanced API over the resources - :commit:`8473c8e126f2a8f14728ad3f8ebb59c45ac55d2d` + * Serialize PE objects into JSON - :commit:`673f5a36f0d339ad9390427292fa6e725b8fd907`, :issue:`18` + * Parse Rich Header - :commit:`0893bd9b08f2248ae8f656ccd81b1be12e8ae57e`, :issue:`15` +``` + +### Bug Fixes + +```{eval-rst} + +:ELF: + + * Bug fix when a GNU hash has empty buckets - `21a6c30 `_ + +:PE: + + * Bug fix in the signature parser: :issue:`30`, :commit:`4af0256ce7c5577e0b1010c6f9b566634f0a3993` + * Bug fix in the resources parser: Infinite loop - :commit:`a569cc13d99354ff96932460f5b1fd859378f252` + * Add more *out-of-bounds* checks on relocations and exports - :commit:`9364f644e937a6a5d69c64c2ef4eaa1fbdd2cfad` + * Use ``min(SizeOfRawData, VirtualSize)`` for the section's size and truncate the size to the file size - :commit:`61bf14ba1182fe458453599ff014de5d71d25680` + + +:MachO: + + * Bug fix when a binary hasn't a ``LC_MAIN`` command - :commit:`957501fe76596e0396c66d08540884876cea049c` +``` + +### API + +```{eval-rst} + +:Abstract Layer: + + * :attr:`lief.Header.is_32` and :attr:`lief.Header.is_64` + * :attr:`lief.Header.object_type` + * :attr:`lief.Header.modes` + * :attr:`lief.Header.endianness` + + +:ELF: + + * :meth:`lief.ELF.Binary.permute_dynamic_symbols` + * ``lief.ELF.Segment.data`` has been renamed to :attr:`lief.ELF.Segment.content` + * :func:`lief.ELF.parse` takes an optional parameters: symbol counting - :class:`lief.ELF.DYNSYM_COUNT_METHODS` + * :attr:`lief.ELF.Relocation.size` + + :Notes: + + * :class:`lief.ELF.Note` + * :attr:`lief.ELF.Binary.has_notes` + * :attr:`lief.ELF.Binary.notes` + + :Hash Tables: + + * :class:`lief.ELF.SysvHash` + * :attr:`lief.ELF.Binary.use_gnu_hash` + * :attr:`lief.ELF.Binary.use_sysv_hash` + * :attr:`lief.ELF.Binary.sysv_hash` + +:PE: + + * :attr:`lief.PE.Symbol.has_section` + * :meth:`lief.PE.Binary.hook_function` + * :meth:`lief.PE.Binary.get_content_from_virtual_address` takes either an **Absolute** virtual address or a **Relative** virtual address + * ``lief.PE.Binary.section_from_virtual_address`` has been renamed to :meth:`lief.PE.Binary.section_from_rva`. + * ``lief.PE.parse_from_raw`` has been removed. One can use :func:`lief.PE.parse`. + * ``lief.PE.Section.data`` has been **removed**. Please use :attr:`lief.PE.Section.content` + + + :Dos Stub: + + * :attr:`lief.PE.Binary.dos_stub` + * :attr:`lief.PE.Builder.build_dos_stub` + + :Rich Header: + + * :attr:`lief.PE.Binary.rich_header` + * :attr:`lief.PE.Binary.has_rich_header` + * :class:`lief.PE.RichHeader` + * :class:`lief.PE.RichEntry` + + :Overlay: + + * :attr:`lief.PE.Binary.overlay` + * :attr:`lief.PE.Builder.build_overlay` + + :Imports: + + * :attr:`lief.PE.Binary.has_import` + * :meth:`lief.PE.Binary.get_import` + + :Resources: + + * :attr:`lief.PE.Binary.resources` + * :class:`lief.PE.ResourceData` + * :class:`lief.PE.ResourceDirectory` + * :class:`lief.PE.ResourceNode` + * ``lief.PE.LangCodeItem`` + * :class:`lief.PE.ResourceDialog` + * :class:`lief.PE.ResourceDialogItem` + * :class:`lief.PE.ResourceFixedFileInfo` + * :class:`lief.PE.ResourceIcon` + * :class:`lief.PE.ResourceStringFileInfo` + * :class:`lief.PE.ResourceVarFileInfo` + * :class:`lief.PE.ResourceVersion` + +:MachO: + + * :attr:`lief.MachO.Binary.has_entrypoint` + * :attr:`lief.MachO.Symbol.demangled_name` + + :UUID: + + * :attr:`lief.MachO.Binary.has_uuid` + * :attr:`lief.MachO.Binary.uuid` + * :class:`lief.MachO.UUIDCommand` + + :Main Command: + + * :attr:`lief.MachO.Binary.has_main_command` + * :attr:`lief.MachO.Binary.main_command` + * :class:`lief.MachO.MainCommand` + + + :Dylinker: + + * :attr:`lief.MachO.Binary.has_dylinker` + * :attr:`lief.MachO.Binary.dylinker` + * :class:`lief.MachO.DylinkerCommand` +``` + +### Documentation + +```{eval-rst} + +:References: + + * elfsteem, pelook, PortEx, elfsharp, metasm, amoco, Goblin + +:Tutorials: + + * `PE Hooking `_, `Resources Manipulation `_ + +:Integration: + + * `XCode `_, `CMake `_ +``` + +### Acknowledgments + +- [ek0](https://github.com/ek0): {pr}`24` +- [ACSC-CyberLab](https://github.com/ACSC-CyberLab): {pr}`33`, {pr}`34`, {pr}`37`, {pr}`39` +- Hyrum Anderson who pointed bugs in the PE parser +- My colleagues for the feedback and suggestions (Adrien, SebK, Pierrick) + +## 0.6.1 - April 6, 2017 + +### Bug Fixes + +```{eval-rst} + +:ELF: + + * Don't rely on :attr:`lief.ELF.Section.entry_size` to count symbols - :commit:`004c6769bec37e303bbe7aaceb49f4b05c8eec84` +``` + +### API + +```{eval-rst} + +:PE: + + * :attr:`lief.PE.TLS.has_section` + * :attr:`lief.PE.TLS.has_data_directory` +``` + +### Documentation + +```{eval-rst} + +:Integration: + + * `Visual Studio `_ +``` + +### Acknowledgments + +- [Philippe](https://github.com/doegox) for the proofreading. + +## 0.6.0 - March 30, 2017 + +First public release + +```{eval-rst} +.. toctree:: + :hidden: + + changelog/pe-0-17-0 +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/changelog.rst b/vendor/lief/doc/sphinx/changelog.rst deleted file mode 100644 index e044752..0000000 --- a/vendor/lief/doc/sphinx/changelog.rst +++ /dev/null @@ -1,1111 +0,0 @@ -Changelog -========= - -0.13.0 - Not Released Yet -------------------------- - -:ELF: - - * Fix a heap overflow found by :github_user:`CCWANG19` (:issue:`763`) - * :github_user:`aeflores` fixed an issue when there are multiple versions associated with a symbol - (see: :issue:`749` for the details). - * Handle binaries compiled with the `-static-pie` flag correctly (see: :issue:`747`) - * Add support for modifying section-less binaries. The ELF :class:`~lief.ELF.Section` objects gain - the :meth:`lief.ELF.Section.as_frame` method which defines the section as a *framed* section. - - A framed section is a section that concretely does not wraps data and can be corrupted. - - :Example: - - .. code-block:: python - - elf = lief.parse("/bin/ssh") - text = elf.get_section(".text").as_frame() - - # We can now corrupt all the fields of the section - text.offset = 0xdeadc0de - text.size = 0xffffff - text.address = 0x123 - - elf.write("/tmp/out") - -:MachO: - - * Fix a segfault when the Mach-O binary does not have segments (found by :github_user:`CCWANG19` via :issue:`764`) - * Enable to create exports - * Fix the layout of the binaries modified by LIEF such as they can be (re)signed. - * Add support for `LC_DYLD_CHAINED_FIXUPS` and `LC_DYLD_EXPORTS_TRIE` - * Global enhancement when modifying the `__LINKEDIT` content - * Add API to get a :class:`~lief.MachO.Section` from a specified segment's name and section's name. - - :Example: - - .. code-block:: python - - sec = bin.get_section("__DATA", "__objc_metadata") - - * Add API to remove a :class:`~lief.MachO.Section` from a specified segment's name and section's name. - - :Example: - - .. code-block:: python - - sec = bin.remove_section("__DATA", "__objc_metadata") - - * Add :attr:`lief.MachO.Binary.page_size` - -:PE: - - * Remove :meth:`lief.PE.ResourceNode.sort_by_id` - * Fix the ordering of childs of :class:`~lief.PE.ResourceNode` - -:General Design: - - * :github_user:`ZehMatt` added the support to write LIEF binaries object through a `std::ostream` interface - (:commit:`9d55f538602989c69454639565910884c5c5ac7c`) - * Remove the exceptions - - -0.12.1 - April 08, 2022 ------------------------- - -:ELF: - * Fix section inclusion calculations (:pr:`692`) - -:PE: - * Fix parsing regressions (:issue:`689`, :issue:`687`, :issue:`686`, :issue:`685`, :issue:`691`, :issue:`693`) - -:Compilation: - * Nightly builds are now upload to Saleway's S3 server: - - - https://lief.s3-website.fr-par.scw.cloud/latest/lief - - https://lief.s3-website.fr-par.scw.cloud/latest/sdk - - * Fix `GLIBCXX_USE_CXX11_ABI=1` ABI issue (see: :issue:`683`) - -0.12.0 - March 25, 2022 ------------------------ - -:ELF: - * :github_user:`ahaensler` added the support to insert and assign a :class:`lief.ELF.SymbolVersionAuxRequirement` (see: :pr:`670`) - * Enhance the ELF parser to support corner cases described by `netspooky `_ in : - - - https://tmpout.sh/2/14.html (*84 byte aarch64 ELF*) - - https://tmpout.sh/2/3.html (*Some ELF Parser Bugs*) - - * New ELF Builder which is more efficient in terms of speed and - in terms of number of segments added when modifying binaries (see: https://lief-project.github.io/blog/2022-01-23-new-elf-builder/) - - * :github_user:`Clcanny` improved (see :pr:`507` and :pr:`509`) the reconstruction of the dynamic symbol table - by sorting local symbols and non-exported symbols. It fixes the following warning when parsing - a modified binary with ``readelf`` - - .. code-block:: text - - Warning: local symbol 29 found at index >= .dynsym's sh_info value of 1 - -:MachO: - * Change the layout of the binaries generated by LIEF such as they are compliant with ``codesign`` checks - * The API to configure the MachO parser has been redesigned to provide a better granularity - - .. code-block:: python - - config = lief.MachO.ParserConfig() - config.parse_dyld_bindings = False - config.parse_dyld_exports = True - config.parse_dyld_rebases = False - - lief.MachO.parse("/tmp/big.macho", config) - - * :github_user:`LucaMoroSyn` added the support for the ``LC_FILESET_ENTRY``. This command is usually - found in kernel cache files - * ``LIEF::MachO::Binary::get_symbol`` now returns a pointer (instead of a reference). If the symbol - can't be found, it returns a nullptr. - * Add API to select a :class:`~lief.MachO.Binary` from a :class:`~lief.MachO.FatBinary` by its architecture. See: - :meth:`lief.MachO.FatBinary.take`. - - .. code-block:: python - - fat = lief.MachO.parse("/bin/ls") - fit = fat.take(lief.MachO.CPU_TYPES.x86_64) - - * Handle the `0x0D` binding opcode (see: :issue:`524`) - * :github_user:`xhochy` fixed performances issues in the Mach-O parser (see :pr:`579`) - -:PE: - * Adding :attr:`lief.PE.OptionalHeader.computed_checksum` that re-computes the :attr:`lief.PE.OptionalHeader.checksum` - (c.f. issue :issue:`660`) - * Enable to recompute the :class:`~lief.PE.RichHeader` (issue: :issue:`587`) - - - :meth:`~lief.PE.RichHeader.raw` - - :meth:`~lief.PE.RichHeader.hash` - - * Add support for PE's delayed imports. see: - - - :class:`~lief.PE.DelayImport` / :class:`~lief.PE.DelayImportEntry` - - :attr:`~lief.PE.Binary.delay_imports` - - * :attr:`lief.PE.LoadConfiguration.reserved1` has been aliased to :attr:`lief.PE.LoadConfiguration.dependent_load_flags` - * :attr:`lief.PE.LoadConfiguration.characteristics` has been aliased to :attr:`lief.PE.LoadConfiguration.size` - * Thanks to :github_user:`gdesmar`, we updated the PE checks to support PE files that have a corrupted - :attr:`lief.PE.OptionalHeader.magic` (cf. :issue:`644`) - -:DEX: - * :github_user:`DanielFi` added support for DEX's fields (see: :pr:`547`) - -:Abstraction: - * Abstract binary imagebase for PE, ELF and Mach-O (:attr:`lief.Binary.imagebase`) - * Add :meth:`lief.Binary.offset_to_virtual_address` - * Add PE imports/exports as *abstracted* symbols - -:Compilation & Integration: - * :github_user:`ekilmer` updated and modernized the CMake integration files through the PR: :pr:`674` - * Enable to use a pre-compiled version of spdlog. This feature aims - at improving compilation time when developing on LIEF. - - One can provide path to spdlog install through: - - .. code-block:: console - - $ python ./setup.py --spdlog-dir=path/to/lib/cmake/spdlog [...] - # or - $ cmake -DLIEF_EXTERNAL_SPDLOG=ON -Dspdlog_DIR=path/to/lib/cmake/spdlog ... - - * Enable to feed LIEF's dependencies externally (c.f. :ref:`lief_third_party`) - * Replace the keywords ``and``, ``or``, ``not`` with ``&&``, ``||`` and ``!``. - -:Dependencies: - * Upgrade to MbedTLS 3.1.0 - * Upgrade Catch2 to 2.13.8 - * The different dependencies can be *linked* externally (cf. above and :ref:`lief_third_party`) - -:Documentation: - * New section about the errors handling (:ref:`err_handling`) and the upcoming - deprecation of the exceptions. - * New section about how to compile LIEF for debugging/developing. See: :ref:`lief_debug` - -:General Design: - - :span: - - LIEF now exposes Section/Segment's data through a `span` interface. - As `std::span` is available in the STL from C++20 and the LIEF public API aims at being - C++11 compliant, we expose this `span` thanks to `tcbrindle/span `_. - This new interface enables to avoid copies of ``std::vector`` which can be costly. - With this new interface, the original ``std::vector`` can be retrieved as follows: - - .. code-block:: cpp - - auto bin = LIEF::ELF::Parser::parse("/bin/ls"); - - if (const auto* section = bin->get_section(".text")) { - LIEF::span text_ref = section->content(); - std::vector copy = {std::begin(text_ref), std::end(text_ref)}; - } - - In Python, span are wrapped by a **read-only** `memory view `_. - The original *list of bytes* can be retrieved as follows: - - .. code-block:: python - - bin = lief.parse("/bin/ls") - section = bin.get_section(".text") - - if section is not None: - memory_view = section.content - list_of_bytes = list(memory_view) - - :Exceptions: - - .. warning:: - - We started to refactor the API and the internal design to remove C++ exceptions. - These changes are described a the dedicated blog (`LIEF RTTI & Exceptions `_) - - To highlighting the content of the blog for the end users, - functions that returned a **reference and which threw an exception** in the case - of a failure are now returning a **pointer that is set to nullptr** in the case of a failure. - - If we consider this original code: - - .. code-block:: cpp - - LIEF::MachO::Binary& bin = ...; - - try { - LIEF::MachO::UUIDCommand& cmd = bin.uuid(); - std::cout << cmd << "\n"; - } catch (const LIEF::not_found&) { - // ... dedicated processing - } - - // Other option with has_uuid() - if (bin.has_uuid()) { - LIEF::MachO::UUIDCommand& cmd = bin.uuid(); - std::cout << cmd << "\n"; - } - - It can now be written as: - - .. code-block:: cpp - - LIEF::MachO::Binary& bin = ...; - - if (LIEF::MachO::UUIDCommand* cmd = bin.uuid();) { - std::cout << *cmd << "\n"; - } else { - // ... dedicated processing as it is a nullptr - } - - // Other option with has_uuid() - if (bin.has_uuid()) { // It ensures that it is not a nullptr - LIEF::MachO::UUIDCommand& cmd = *bin.uuid(); - std::cout << cmd << "\n"; - } - - .. seealso:: - - - :ref:`C++ API for errors handling ` - - :ref:`Python API for errors handling ` - - `List of the functions that changed `_ - - -0.11.X - Patch Releases ------------------------ - -.. _release-0115: - -0.11.5 - May 22, 2021 -********************* - -* Remove usage of ``not`` in public headers (:commit:`b8e825b464418de385146bb3f89ef6126f4de5d4`) - -:ELF: - * :github_user:`pdreiter` fixed the issue :issue:`418` - -:PE: - * Fix issue when computing :attr:`lief.PE.Binary.sizeof_headers` (:commit:`ab3f073ac0c60d8453070f83dd4dc04fe60aa0a5`) - -:MachO: - * Fix error on property :attr:`lief.MachO.BuildVersion.sdk` (see :issue:`533`) - -.. _release-0114: - -0.11.4 - March 09, 2021 -*********************** - -:PE: - * Fix missing bound check when computing the authentihash - -.. _release-0113: - -0.11.3 - March 03, 2021 -*********************** - -:PE: - * Add sanity check on the signature's length that could lead to a ``std::bad_alloc`` exception - -.. _release-0112: - - -0.11.2 - February 24, 2021 -************************** - -:PE: - * Fix regression in the behavior of the PE section's name. One can now access the full - section's name (with trailing bytes) through :attr:`lief.PE.Section.fullname` (see: :issue:`551`) - -.. _release-0111: - -0.11.1 - February 22, 2021 -************************** - -:PE: - * :meth:`lief.PE.x509.is_trusted_by` and :meth:`lief.PE.x509.verify` now return - a better :attr:`lief.PE.x509.VERIFICATION_FLAGS` instead of just :attr:`lief.PE.x509.VERIFICATION_FLAGS.BADCERT_NOT_TRUSTED` - (see: :issue:`532`) - * Fix errors in the computation of the Authentihash - -.. _release-0110: - -0.11.0 - January 19, 2021 -------------------------- - -:ELF: - * :github_user:`mkomet` updated enums related to Android (see: :commit:`9dd641d380a5defd0a71a9f42dde2fe9c9cb1dbd`) - * :github_user:`aeflores` added MIPS relocations support in the ELF parser - * Fix :meth:`~lief.ELF.Binary.extend` on a ELF section (cf. issue :issue:`477`) - * Fix issue when exporting symbols on empty-gnu-hash ELF binary (:commit:`1381f9a115e6e312ac0ab3deb46a78e481b81796`) - * Fix reconstruction issue when the binary is prelinked (cf. issue :issue:`466`) - * Add ``DF_1_PIE`` flag - * Fix parsing issue of the ``.eh_frame`` section when the base address is not 0. - * :github_user:`JanuszL` enhanced the algorithm that computes the string table. - It moves from a ``N^2`` algorithm to a ``Nlog(N)`` (:commit:`1e0c4e81d4a3fd7282713f111193e42f198f8967`). - * Fix ``.eh_frame`` parsing issue (:commit:`b57f32333a85d0f172206bc5d20aabe2d7942738`) - * :github_user:`aeflores` fixed parsing issue in ELF relocations (:commit:`6c53646bb790acf28f2999527eafad30db7d6b69`) - * Add ``PT_GNU_PROPERTY`` enum - * Bug fix in the symbols table reconstruction (ELF) - -:PE: - * Enhance PE Authenticode. See `PE Authenticode `_ - * :func:`~lief.PE.get_imphash` can now generate the same value as pefile and Virus Total (:issue:`299`) - - .. code-block:: python - - pe = lief.parse("example.exe") - vt_imphash = lief.PE.get_imphash(pe, lief.PE.IMPHASH_MODE.PEFILE) - lief_imphash = lief.PE.get_imphash(pe, lief.PE.IMPHASH_MODE.DEFAULT) - - .. seealso:: - - :class:`lief.PE.IMPHASH_MODE` and :func:`lief.PE.get_imphash` - * Remove the padding entry (0) from the rich header - * :attr:`~lief.PE.LangCodeItem.items` now returns a dictionary for which the values are **bytes** (instead of - ``str`` object). This change is related to ``utf-16`` support. - * :github_user:`kohnakagawa` fixed wrong enums values: :commit:`c03125045e32a9cd65c613585eb4d0385350c6d2`, :commit:`6ee808a1e4611d09c6cf0aea82a612be69584db9`, :commit:`cd05f34bae681fc8af4b5e7cc28eaef816802b6f` - * :github_user:`kohnakagawa` fixed a bug in the PE resources parser (:commit:`a7254d1ba935783f16effbc7faddf993c57e82f7`) - * Handle PE forwarded exports (issue :issue:`307`) - -:Mach-O: - * Add API to access either ``LC_CODE_SIGNATURE`` or ``DYLIB_CODE_SIGN_DRS`` (issue :issue:`476`) - * Fix issue when parsing twice a Mach-O file (issue :issue:`479`) - -:Dependencies: - * Replace ``easyloggingpp`` with `spdlog 1.8.1 `_ - * Upgrade ``frozen`` to 1.0.0 - * Upgrade ``json`` to 3.7.3 - * Upgrade ``pybind11`` to 2.6.0 - * Upgrade ``mbedtls`` to 2.16.6 - -:Documentation: - * :github_user:`aguinet` updated the `bin2lib tutorial `_ with the support - of the new glibc versions (:commit:`7884e57aa1d103f3bd37682e47f412bfe7a3aa34`) - * Global update and enable to build the documentation out-of-tree - * Changing the theme - -:Misc: - * Add Python 3.9 support - * ``FindLIEF.cmake`` deprecates ``LIEF_ROOT``. You should use ``LIEF_DIR`` instead. - - -:Logging: - - We changed the logging interface. The following log levels have been removed: - - - LOG_GLOBAL - - LOG_FATAL - - LOG_VERBOSE - - LOG_UNKNOWN - - We also moved from an class-interface based to functions. - - Example: - - .. code-block:: python - - lief.logging.disable() - lief.logging.enable() - lief.logging.set_level(lief.logging.LOGGING_LEVEL.INFO) - - See: :func:`lief.logging.set_level` - - .. note:: - - The log functions now output on ``stderr`` instead of ``stdout`` - - - -0.10.1 - November 29, 2019 --------------------------- - -- Fix regression in parsing Python ``bytes`` -- Add Python API to demangle strings: ``lief.demangle`` - - -0.10.0 - November 24, 2019 --------------------------- - -:ELF: - - * Add build support for ELF notes - * Add coredump support (:commit:`9fc3a8a43358f608cf18ddbe341e1d94b13cb9e0`) - * Enable to bind a relocation with a symbol (:commit:`a9f3cb8f9b4a1f2cdaa95eee4568ff0b162f77cd`) - - :Example: - - .. code-block:: python - - relocation = "..." - - symbol = lief.ELF.Symbol() - symbol.name = "printf123" - relocation.symbol = symbol - - * Add constructors (:commit:`67d924a2206c36cb9979d8b1b194b03b2d592e71`) - * Expose ELF destructors (:commit:`957384cd361c4a485470f877658af2bf052dbe0a`) - * Add ``remove_static_symbol`` (:commit:`c6779702b1fec3c67b0c19a36576830fe18bd9d9`) - * Add support for static relocation writing (:commit:`d1b98d69ade662e2471ce2905bf3fb247dfc3143`) - * Expose function to get strings located in the ``.rodata`` section (:commit:`02f4851c9f0c2bfa6fb4f51dab393a1db83b4851`) - * Export ELF ABI version (:commit:`8d7ec26a93800b0729c2c05be8c55c8318ba3b20`) - -:PE: - - * Improve PE Authenticode parsing (:commit:`535623de3aa4f8ddc34536331b802e2cbdc44faf`) - * Fix alignment issue when removing a PE section (:commit:`04dddd371080d731fab965b127cb15a91c57d53c`) - * Parse PE debug data directory as a list of debug entries (by :github_user:`1orenz0` - :commit:`fcc75dd87982e52d77a1c7ee7e674741a199e41b`) - * Add support to parse POGO debug entries (by :github_user:`1orenz0` - :commit:`3537440b8d0da6c9c3d00c25f7da8a04f29154d2`) - -:Mach-O: - - * Enhance Mach-O modifications by exposing an API to: - - - Add load commands - - Add sections - - Add segments - - See: :commit:`406115c8d097da0b61f00b2bb7b2442322ffc5d1` - - * Enable ``write()`` on FAT Mach-O (:commit:`16595316fd588619ea39b942817d6527e0601fbd`) - * Introduce Mach-O Build Version command (:commit:`6f967238fcd369210839605ab08c30d647a09a65`) - * Enable to remove Mach-O symbols (:commit:`616d739da513092e9ab7446654414b0929d5d5cf`) - * Add support for adding ``LC_UNIXTHREAD`` commands in a MachO (by :github_user:`nezetic` - :commit:`64d2597284149441fc734b251648ca917cd816e3`) - - -:Abstract Layer: - - * Expose ``remove_section()`` in the abstract layer (:commit:`918438c6bee52c8421d809bc3b42974165e5fa0b`) - * Expose ``write()`` in the abstract layer (:commit:`af4d48ed2e1f1b96687644f2fc4661fcbdb979a6`) - * Expose API to list functions found in a binary (:commit:`b5a08463ad63811e9e9432812406aadd74ab8c09`) - -:Android: - - * Add partial support for Android 9 (:commit:`bce9ebe17064b1ca16b00dc14eebb5d5dd440184`) - - -:Misc: - - * :github_user:`lkollar` added support for Python 3.8 in CI (Linux & OSX only) - * Update Pybind11 dependency to ``v2.4.3`` - * Enhance Python install (see: :ref:`v10-label`) - * Thanks to :github_user:`lkollar`, Linux CI now produces **manylinux1-compliant wheels** - -Many thanks to the contributors: :github_user:`recvfrom`, :github_user:`pbrunet`, -:github_user:`mackncheesiest`, :github_user:`wisk`, :github_user:`nezetic`, -:github_user:`lkollar`, :github_user:`jbremer`, :github_user:`DaLynX`, :github_user:`1orenz0`, -:github_user:`breadchris`, :github_user:`0xbf00`, :github_user:`unratito`, :github_user:`strazzere`, -:github_user:`aguinetqb`, :github_user:`mingwandroid`, :github_user:`serge-sans-paille-qb`, :github_user:`yrp604`, -:github_user:`majin42`, :github_user:`KOLANICH` - -0.9.0 - June 11, 2018 ---------------------- - -LIEF 0.9 comes with new formats related to Android: OAT, DEX, VDEX and ART. It also fixes bugs and thanks to -:github_user:`yd0b0N`, ELF parser now supports big and little endian binaries. We also completed the JSON serialization of LIEF objects. - - -Features -******** - -:MachO: - - * Enable to configure the Mach-O parser for quick parsing: :commit:`880b99aeef825786dd65aed286d7c4d23b62f564` - * Add :class:`lief.MachO.EncryptionInfo` command: :commit:`f4e2d81bfe84238d463bdb65297c296635e783b1` - * Add :class:`lief.MachO.RPathCommand` command: :commit:`196994dc089885ff2f1268e51f5514f7fcbc5cff` - * Add :class:`lief.MachO.DataInCode` command: :commit:`a16e1c4d13c7071fabe6a5a46b6d6c0fd9565b72` - * Add :class:`lief.MachO.SubFramework` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` - * Add :class:`lief.MachO.SegmentSplitInfo` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` - * Add :class:`lief.MachO.DyldEnvironment` command: :commit:`9e3b5b45f78cc075f2192c245247af00b88b5e3c` - * API to show export-trie, rebase and binding opcodes: :commit:`5d56141061bfc27e3c971e9e474dc86fdaf0c6a9` - - -:PE: - - * Add PE Code View: :commit:`eab4a7614fdf6e9a180b1c638903310da0b83118` - - -:ELF: - - * Add support for ``.note.android.ident`` section: :commit:`d13db18214006ce654b723a882f70c3d7eabd20d` - * Enable to add unlimited number of dynamic entries: :commit:`a40da3e3b4b985b18a6e6026d594f524b7bae963` - * Add support for PPC relocations: :commit:`08b514191f661eeabbdf8ecacd1d7dd35a67ca54` - * Endianness support: :commit:`e794ac1502ee7636755bd441923368f88525a7d0` - -API -*** - - * :func:`lief.breakp` and :func:`lief.shell` - * :func:`lief.parse` now support ``io`` streams as input - * Parser now returns a ``std::unique_ptr`` instead of a raw pointer: :commit:`cd1cc457cf3d63cfc5faa945657887200cedb8b3` - -Misc -**** - -* Use `frozen `_ for some internal ``std::map`` (If C++14 is supported by the compiler) - -Acknowledgements -**************** - -* :github_user:`yd0b0N` for :pr:`162` and :pr:`166` (Endianness support and PPC relocations) -* :github_user:`0xbf00` for :pr:`128` (``LC_RPATH`` command) -* :github_user:`illera88` for :pr:`118` - - -0.8.3 ------ - -* [Mach-O] Fix typo on comparison operator - :commit:`abbc264833894973f601f700b3abcc109904f722` - -0.8.2 ------ - -* [ELF] Increase the upper limit of relocation number - :commit:`077bc329bdcc249cb8ed0b8bcb9630e1c9eede94` - -0.8.1 - October 18, 2017 ------------------------- - -* Fix an alignment issue in the ELF builder. See :commit:`8db199c04e9e6bcdbda165ab5c42d88218a0beb6` -* Add assertion on the setuptools version: :commit:`62e5825e27bb637c2f42f4d05690a100213beb03` - - -0.8.0 - October 16, 2017 ------------------------- - -LIEF 0.8.0 mainly improves the MachO parser and the ELF builder. It comes with `Dockerfiles `_ for `CentOS `_ and `Android `_. - -`LibFuzzer `_ has also been integrated in the project to enhance the parsers - - -Features -******** - - -:Abstract Layer: - - * :class:`~lief.Relocation` are now abstracted from the 3 formats - :commit:`9503f2fc7b6c14bebd4c220bda4a243d87f14bd1` - * ``PIE`` and ``NX`` are abstracted through the :attr:`~lief.Binary.is_pie` and :attr:`~lief.Binary.has_nx` properties - * Add the :meth:`lief.Section.search` and :meth:`lief.Section.search_all` methods to look for patterns in the section's content. - -:ELF: - - * ``DT_FLAGS`` and ``DT_FLAGS_1`` are now parsed into :class:`~lief.ELF.DynamicEntryFlags` - :commit:`754b8afa2b41993e6c37d2d9003cebdccc641d23` - * Handle relocations of object files (``.o``) - :commit:`483b8dc2eabee3da29ce5e5ff2e25c2a3c9ca297` - - * Global enhancement of the ELF builder: - - One can now add **multiple** :class:`~lief.ELF.Section` or :class:`~lief.ELF.Segment` into an ELF: - - .. code-block:: python - - elf = lief.parse("/bin/cat") - - for i in range(3): - segment = Segment() - segment.type = SEGMENT_TYPES.LOAD - segment.content = [i & 0xFF] * 0x1000 - elf += segment - - - for i in range(3): - section = Section("lief_{:02d}".format(i)) - section.content = [i & 0xFF] * 0x1000 - elf += section - - elf.write("foo") - - .. code-block:: console - - $ readelf -l ./foo - PHDR 0x0000000000000040 0x0000000000000040 0x0000000000000040 - 0x00000000000061f8 0x00000000000061f8 R E 0x8 - INTERP 0x0000000000006238 0x0000000000006238 0x0000000000006238 - 0x000000000000001c 0x000000000000001c R 0x1 - [Requesting program interpreter: /lib64/ld-linux-x86-64.so.2] - LOAD 0x0000000000000000 0x0000000000000000 0x0000000000000000 - 0x000000000000d6d4 0x000000000000d6d4 R E 0x200000 - LOAD 0x000000000000da90 0x000000000020da90 0x000000000020da90 - 0x0000000000000630 0x00000000000007d0 RW 0x200000 - LOAD 0x000000000000f000 0x000000000040f000 0x000000000040f000 - 0x0000000000001000 0x0000000000001000 0x1000 - LOAD 0x0000000000010000 0x0000000000810000 0x0000000000810000 - 0x0000000000001000 0x0000000000001000 0x1000 - LOAD 0x0000000000011000 0x0000000001011000 0x0000000001011000 - 0x0000000000001000 0x0000000000001000 0x1000 - .... - - $ readelf -S ./foo - ... - [27] lief_00 PROGBITS 0000000002012000 00012000 - 0000000000001000 0000000000000000 0 0 4096 - [28] lief_01 PROGBITS 0000000004013000 00013000 - 0000000000001000 0000000000000000 0 0 4096 - [29] lief_02 PROGBITS 0000000008014000 00014000 - 0000000000001000 0000000000000000 0 0 4096 - - .. warning:: - - There are issues with executables statically linked with libraries that use ``TLS`` - - See: :issue:`98` - - - - - One can now add **multiple** entries in the dynamic table: - - .. code-block:: python - - elf = lief.parse("/bin/cat") - - elf.add_library("libfoo.so") - elf.add(DynamicEntryRunPath("$ORIGIN")) - elf.add(DynamicEntry(DYNAMIC_TAGS.INIT, 123)) - elf.add(DynamicSharedObject("libbar.so")) - - elf.write("foo") - - .. code-block:: console - - $ readelf -d foo - 0x0000000000000001 (NEEDED) Shared library: [libfoo.so] - 0x0000000000000001 (NEEDED) Shared library: [libc.so.6] - 0x000000000000000c (INIT) 0x7b - 0x000000000000000c (INIT) 0x3600 - ... - 0x000000000000001d (RUNPATH) Bibliothèque runpath:[$ORIGIN] - 0x000000000000000e (SONAME) Bibliothèque soname: [libbar.so] - - See :commit:`b94900ca7f500912bfe249cd534055942e28e34b`, :commit:`1e410e6c950c391f0d1a3f12cb6f8e4c9fb16539` for details. - - * :commit:`b2d36940f60eacfa602c115cb542e11c70b6841c` enables modification of the ELF interpreter without **length restriction** - - .. code-block:: python - - elf = lief.parse("/bin/cat") - elf.interpreter = "/a/very/long/path/to/another/interpreter" - elf.write("foo") - - .. code-block:: console - - $ readelf -l foo - Program Headers: - Type Offset VirtAddr PhysAddr - FileSiz MemSiz Flags Align - PHDR 0x0000000000000040 0x0000000000000040 0x0000000000000040 - 0x00000000000011f8 0x00000000000011f8 R E 0x8 - INTERP 0x000000000000a000 0x000000000040a000 0x000000000040a000 - 0x0000000000001000 0x0000000000001000 R 0x1 - [Requesting program interpreter: /a/very/long/path/to/another/interpreter] - .... - - * Enhancement of the dynamic symbols counting - :commit:`985d1249b72494a0e62f34042b3c9cbfa0706e90` - * Enable editing ELF's notes: - - .. code-block:: python - - elf = lief.parse("/bin/ls") - build_id = elf[NOTE_TYPES.BUILD_ID] - build_id.description = [0xFF] * 20 - elf.write("foo") - - .. code-block:: console - - $ readelf -n foo - Displaying notes found in: .note.gnu.build-id - Owner Data size Description - GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) - Build ID: ffffffffffffffffffffffffffffffffffffffff - - See commit :commit:`3be9dd0ff58ec68cb8813e01d6798c16b42dac22` for more details - -:PE: - - * Add :func:`~lief.PE.get_imphash` and :func:`~lief.PE.resolve_ordinals` functions - :commit:`a89bc6df4f242d7641292acdb184927449d14fff`, :commit:`dfa8e985c0561427a20088750693a004de587b1c` - * Parse the *Load Config Table* into :class:`~lief.PE.LoadConfiguration` (up to Windows 10 SDK 15002 with *hotpatch_table_offset*) - - .. code-block:: python - - from lief import to_json - import json - pe = lief.parse("some.exe") - loadconfig = to_json(pe.load_configuration)) # Using the lief.to_json function - pprint(json.loads(to_json(loadconfig))) - - .. code-block:: javascript - - {'characteristics': 248, - 'code_integrity': {'catalog': 0, - 'catalog_offset': 0, - 'flags': 0, - 'reserved': 0}, - 'critical_section_default_timeout': 0, - 'csd_version': 0, - 'editlist': 0, - ... - 'guard_cf_check_function_pointer': 5368782848, - 'guard_cf_dispatch_function_pointer': 5368782864, - 'guard_cf_function_count': 15, - 'guard_cf_function_table': 5368778752, - 'guard_flags': 66816, - 'guard_long_jump_target_count': 0, - 'guard_long_jump_target_table': 0, - 'guard_rf_failure_routine': 5368713280, - 'guard_rf_failure_routine_function_pointer': 5368782880, - ... - - For details, see commit: :commit:`0234e3b8bbb6f6f3490392f8c295fde284a99334` - - - - -:MachO: - - * The ``dyld`` structure is parsed (deeply) into :class:`~lief.MachO.DyldInfo`. It includes: - - * Binding opcodes - * Rebases opcodes - * Export trie - - See: :commit:`e2b81e0a8e187cae5f0f115241243a84ee7696b6`, :commit:`0e972d69ce35731867d82c047eef7eb9ea58e3ec`, :commit:`f7cc518dcfbb0557fd8d396144bf99a222d96705`, :commit:`782295bfb86d2a12584c5b16a37a26d56d1ee235`, :issue:`67` - - * Section relocations are now parsed into :attr:`lief.MachO.Section.relocations` - :commit:`29c8157ecc3b308bd521cb1daee3c2e3a2cffb28` - * ``LC_FUNCTION_STARTS`` is parsed into :class:`~lief.MachO.FunctionStarts` (:commit:`18d89198a0cc63ff291ae9110f465354c3b8f1e6`) - * ``LC_SOURCE_VERSION``, ``LC_VERSION_MIN_MACOSX`` and ``LC_VERSION_MIN_IPHONEOS`` are - parsed into :class:`~lief.MachO.SourceVersion` and :class:`~lief.MachO.VersionMin` (:commit:`c359778194db874669884aaccb52a4b05546bc07`, :commit:`0b4bb7d56520cd0ea08bbcb9530e5e0c96ac14ae`, :commit:`5b993117ed391db18ba775cabefa5f3981b2f1cc`, :issue:`45`) - * ``LC_THREAD`` and ``LC_UNIXTHREAD`` are now parsed into :class:`~lief.MachO.ThreadCommand` - :commit:`23257830b291c40a3aed92360040f2b0b11ffa72` - - -Fixes -***** - -Fix enums conflicts(:issue:`32`) - :commit:`66b4cd4550ecf6cf3adb4900e6ad7ac33f1f7f32` - -Fix most of the memory leaks: :commit:`88dafa8db6e752393f69d73f68d295e91963b8da`, :commit:`d9b1436730b5d33a753e7dfa4301697a0c676066`, :commit:`554fa153af943b97a16fc4a52ab8459a3d0a9bc7`, :commit:`3602643f5d02a1c78c4de609cc47f193f3a8840f` - -:ELF: - - * Bug Fix when counting dynamic symbols from the GnuHash Table - :commit:`9036a2405dc44726f40cb77cab1bcbf371ab7a70` - -:PE: - - * Fix nullptr dereference in resources - :commit:`e90fe1b6c6f6a605390bcd1026435ce7503e7e6a` - * Handle encoding issues in the Python API - `8c7ceaf `_ - * Sanitize DLL names - -:MachO: - - * Fix :issue:`87`, :issue:`92` - * Fix memory leaks and *some* performance issues: :issue:`94` - - - - -API -*** - -In the C++ API ``get_XXX()`` getters have been renamed into ``XXX()`` (e.g. ``get_header()`` becomes ``header()``) - :commit:`a4c69f7868da1de5d09aa26e977dedb720e36cbd`, :commit:`e805669865b130057413f456958a471d8f0ac0b1` - -:Abstract: - - * :class:`lief.Binary` gains the :attr:`~lief.Binary.format` property - :commit:`9391238f114fe963890777c2d8b90f2caaa5510c` - * :func:`lief.parse` can now takes a list of integers - :commit:`f330fa887d14d47f0683144430ac9695d3136561` - * Add :meth:`~lief.Binary.has_symbol` and :meth:`~lief.Binary.get_symbol` to :class:`lief.Binary` - :commit:`f121af5ca61a22fd83acc5c7094b50ed1cda8226` - * [Python API] Enhance the access to the abstract layer through the :attr:`~lief.Binary.abstract` attribute - :commit:`07138549a46db87c7b924fd072356030b1d5c6bc` - - One can now do: - - .. code-block:: python - - elf = lief.ELF.parse("/bin/ls") # Could be lief.MachO / lief.PE - abstract = elf.abstract # Return the lief.Binary object - - -:ELF: - - * Relocation gains the :attr:`~lief.ELF.Relocation.purpose` property - :commit:`b7b0bde4d51c54d8d226e5320b1b0d2cc48137c4` - * Add :attr:`lief.ELF.Binary.symbols` which return an iterator over **all** symbols (static and dynamic) - :commit:`af6ab65dc91169627f4fbb87cda92093eb699a1e` - * ``Header.sizeof_section_header`` has been renamed into :attr:`~lief.ELF.Header.section_header_size` - :commit:`d96971b0c3f8ff50add349957f571b8daa00708a` - * ``Segment.flag`` has been renamed into :attr:`~lief.ELF.Segment.flags` - :commit:`20a5f666deb89b06b79a1c4418ac938497fb658c` - * Add: - - * :attr:`~lief.ELF.Header.arm_flags_list`, - * :attr:`~lief.ELF.Header.mips_flags_list` - * :attr:`~lief.ELF.Header.ppc64_flags_list` - * :attr:`~lief.ELF.Header.hexagon_flags_list` - - to :class:`~lief.ELF.Header` - :commit:`730d045e05dca7ef3cd6a51d1175f280be356c70` - - To check if a given flag is set, one can do: - - .. code-block:: python - - >>> if lief.ELF.ARM_EFLAGS.EABI_VER5 in lief.ELF.Header "yes" else "no" - * [Python] Segment flags: ``PF_X``, ``PF_W``, ``PF_X`` has been renamed into :attr:`~lief.ELF.SEGMENT_FLAGS.X`, :attr:`~lief.ELF.SEGMENT_FLAGS.W`, :attr:`~lief.ELF.SEGMENT_FLAGS.X` - :commit:`d70ef9ec2c42619434352dbd7b74a835ebad7569` - * Add :attr:`lief.ELF.Section.flags_list` - :commit:`4937b7193a5760df85d0ac1567afc011a22cdb98` - * Enhancement for :attr:`~lief.ELF.DynamicEntryRpath` and :attr:`~lief.ELF.DynamicEntryRunPath`: :commit:`c375a47da7c4c524e886f9238f8dd51a44501087` - * Enhancement for :attr:`~lief.ELF.DynamicEntryArray`: :commit:`81440ce00cdfc793161a0dc394ada345307dc24b` - * Add some *operators* :commit:`3b200b30503847be4779447c76f5207d18daf77f`, :commit:`43bd06f8f32196454ee2305201f4e27b3a3c8a1e` - - - -:PE: - * Add some *operators* :commit:`5666351e07b7bf4a9624033f670d02b8806d2663` - -:MachO: - - * :func:`lief.MachO.parse` can now takes a list of integers - :commit:`f330fa887d14d47f0683144430ac9695d3136561` - * :func:`lief.MachO.parse` now returns a :class:`~lief.MachO.FatBinary` instead of a ``list`` of :class:`~lief.MachO.Binary`. :class:`~lief.MachO.FatBinary` has a similar API as a list - :commit:`3602643f5d02a1c78c4de609cc47f193f3a8840f` - * Add some *operators*: :commit:`cbe835484751396daffe7f8d238cbb85d66470ab` - -:Logging: - - Add an API to configure the logger - :commit:`4600c2ba8d7d17b5965c2b74faeb7e4d2128de17` - - Example: - - .. code-block:: python - - from lief import Logger - Logger.disable() - Logger.enable() - Logger.set_level(lief.LOGGING_LEVEL.INFO) - - See: :class:`lief.Logger` - -Build system -************ - -* Add `FindLIEF.cmake `_ - :commit:`6dd8b10325e832a7520bf5ae3a588b9e022d0345` -* Add ASAN, TSAN, USAN, LSAN - :commit:`7f6aeb0d0d74eae886f4b312e12e8f71e1d5da6a` -* Add LibFuzzer - :commit:`7a0dc28ea29a30209e944ebcde27f7c0ab234651` - - -Documentation -************* - -:References: - - * recomposer, bearparser, IAT_patcher, PEframe, Manalyze, MachOView, elf-dissector - - -Acknowledgements -**************** - -* :github_user:`alvarofe` for :pr:`47` -* :github_user:`aguinet` for :pr:`55`, :pr:`61`, :pr:`65`, :pr:`77` -* :github_user:`jevinskie` for :pr:`75` -* :github_user:`liumuqing` for :pr:`80` -* :github_user:`Manouchehri` for :pr:`106` - - -0.7.0 - July 3, 2017 ---------------------- - -Features -******** - -:Abstract Layer: - - * Add bitness (32bits / 64bits) - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` - * Add object type (Library, executable etc) - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` - * Add *mode* Thumbs, 16bits etc - :commit:`78d1adb41e8b0d21a6f6fe94014753ce68e0ffa1` - * Add endianness - :commit:`7ea08f72c43212f2e3f401b5c2c2614bc9aab8de`, :issue:`29` - -:ELF: - - * Enable dynamic symbols permutation - :commit:`2dea7cb6d631b69995567e056a97e526f588b8ff` - * Fully handle section-less binaries - :commit:`de40c068316b3334e4c8d81ecb3efc177ab24c3b` - * Parse ELF notes - :commit:`241aac7bedaf18ab5e3f0c9775a8a51cb0b40a3e` - * Parse SYSV hash table - :commit:`afa74cee88f730acef84fe6d9c984455a28463e7`, :issue:`36` - * Add relocation size - :commit:`f1766f2c297caed636c7f32730cd10b62bfcc757` - -:PE: - - * Parse PE Overlay - :commit:`e0634c1cf6d12fbdc5bcc1745059005e46e5d805` - * Enable PE Hooking - :commit:`24f6b7213647469e269ead9441d78204162d08ec` - * Parse and rebuilt dos stub - :commit:`3f0639712617007e2e0431cb5eeb9be204c5d74b` - * Add a *resources manager* to provide an enhanced API over the resources - :commit:`8473c8e126f2a8f14728ad3f8ebb59c45ac55d2d` - * Serialize PE objects into JSON - :commit:`673f5a36f0d339ad9390427292fa6e725b8fd907`, :issue:`18` - * Parse Rich Header - :commit:`0893bd9b08f2248ae8f656ccd81b1be12e8ae57e`, :issue:`15` - -Bug Fixes -********* - -:ELF: - - * Bug fix when a GNU hash has empty buckets - `21a6c30 `_ - -:PE: - - * Bug fix in the signature parser: :issue:`30`, :commit:`4af0256ce7c5577e0b1010c6f9b566634f0a3993` - * Bug fix in the resources parser: Infinite loop - :commit:`a569cc13d99354ff96932460f5b1fd859378f252` - * Add more *out-of-bounds* checks on relocations and exports - :commit:`9364f644e937a6a5d69c64c2ef4eaa1fbdd2cfad` - * Use ``min(SizeOfRawData, VirtualSize)`` for the section's size and truncate the size to the file size - :commit:`61bf14ba1182fe458453599ff014de5d71d25680` - - -:MachO: - - * Bug fix when a binary hasn't a ``LC_MAIN`` command - :commit:`957501fe76596e0396c66d08540884876cea049c` - -API -*** - -:Abstract Layer: - - * :attr:`lief.Header.is_32` and :attr:`lief.Header.is_64` - * :attr:`lief.Header.object_type` - * :attr:`lief.Header.modes` - * :attr:`lief.Header.endianness` - - -:ELF: - - * :meth:`lief.ELF.Binary.permute_dynamic_symbols` - * ``lief.ELF.Segment.data`` has been renamed to :attr:`lief.ELF.Segment.content` - * :func:`lief.ELF.parse` takes an optional parameters: symbol counting - :class:`lief.ELF.DYNSYM_COUNT_METHODS` - * :attr:`lief.ELF.Relocation.size` - - :Notes: - - * :class:`lief.ELF.Note` - * :attr:`lief.ELF.Binary.has_notes` - * :attr:`lief.ELF.Binary.notes` - - :Hash Tables: - - * :class:`lief.ELF.SysvHash` - * :attr:`lief.ELF.Binary.use_gnu_hash` - * :attr:`lief.ELF.Binary.use_sysv_hash` - * :attr:`lief.ELF.Binary.sysv_hash` - -:PE: - - * :attr:`lief.PE.Symbol.has_section` - * :meth:`lief.PE.Binary.hook_function` - * :meth:`lief.PE.Binary.get_content_from_virtual_address` takes either an **Absolute** virtual address or a **Relative** virtual address - * ``lief.PE.Binary.section_from_virtual_address`` has been renamed to :meth:`lief.PE.Binary.section_from_rva`. - * ``lief.PE.parse_from_raw`` has been removed. One can use :func:`lief.PE.parse`. - * ``lief.PE.Section.data`` has been **removed**. Please use :attr:`lief.PE.Section.content` - - - :Dos Stub: - - * :attr:`lief.PE.Binary.dos_stub` - * :attr:`lief.PE.Builder.build_dos_stub` - - :Rich Header: - - * :attr:`lief.PE.Binary.rich_header` - * :attr:`lief.PE.Binary.has_rich_header` - * :class:`lief.PE.RichHeader` - * :class:`lief.PE.RichEntry` - - :Overlay: - - * :attr:`lief.PE.Binary.overlay` - * :attr:`lief.PE.Builder.build_overlay` - - :Imports: - - * :attr:`lief.PE.Binary.has_import` - * :meth:`lief.PE.Binary.get_import` - - :Resources: - - * :attr:`lief.PE.Binary.resources` - * :class:`lief.PE.ResourceData` - * :class:`lief.PE.ResourceDirectory` - * :class:`lief.PE.ResourceNode` - * :class:`lief.PE.LangCodeItem` - * :class:`lief.PE.ResourceDialog` - * :class:`lief.PE.ResourceDialogItem` - * :class:`lief.PE.ResourceFixedFileInfo` - * :class:`lief.PE.ResourceIcon` - * :class:`lief.PE.ResourceStringFileInfo` - * :class:`lief.PE.ResourceVarFileInfo` - * :class:`lief.PE.ResourceVersion` - -:MachO: - - * :attr:`lief.MachO.Binary.has_entrypoint` - * :attr:`lief.MachO.Symbol.demangled_name` - - :UUID: - - * :attr:`lief.MachO.Binary.has_uuid` - * :attr:`lief.MachO.Binary.uuid` - * :class:`lief.MachO.UUIDCommand` - - :Main Command: - - * :attr:`lief.MachO.Binary.has_main_command` - * :attr:`lief.MachO.Binary.main_command` - * :class:`lief.MachO.MainCommand` - - - :Dylinker: - - * :attr:`lief.MachO.Binary.has_dylinker` - * :attr:`lief.MachO.Binary.dylinker` - * :class:`lief.MachO.DylinkerCommand` - - -Documentation -************* - -:References: - - * elfsteem, pelook, PortEx, elfsharp, metasm, amoco, Goblin - -:Tutorials: - - * `PE Hooking `_, `Resources Manipulation `_ - -:Integration: - - * `XCode `_, `CMake `_ - -Acknowledgements -**************** - -* `ek0 `_: :pr:`24` -* `ACSC-CyberLab `_: :pr:`33`, :pr:`34`, :pr:`37`, :pr:`39` -* Hyrum Anderson who pointed bugs in the PE parser -* My collegues for the feedbacks and suggestions (Adrien, SebK, Pierrick) - -0.6.1 - April 6, 2017 ----------------------- - -Bug Fixes -********* - -:ELF: - - * Don't rely on :attr:`lief.ELF.Section.entry_size` to count symbols - :commit:`004c6769bec37e303bbe7aaceb49f4b05c8eec84` - -API -*** - -:PE: - - * :attr:`lief.PE.TLS.has_section` - * :attr:`lief.PE.TLS.has_data_directory` - - - -Documentation -************* - -:Integration: - - * `Visual Studio `_ - -Acknowledgements -**************** - -* `Philippe `_ for the proofreading. - - -0.6.0 - March 30, 2017 ----------------------- - -First public release diff --git a/vendor/lief/doc/sphinx/changelog/pe-0-17-0.md b/vendor/lief/doc/sphinx/changelog/pe-0-17-0.md new file mode 100644 index 0000000..a2cea42 --- /dev/null +++ b/vendor/lief/doc/sphinx/changelog/pe-0-17-0.md @@ -0,0 +1,315 @@ +(pe_0170_changelog)= + +# PE Changelog for LIEF 0.17.0 + +Compared to LIEF v0.16.x, version 0.17.0 includes a significant refactoring +of the PE parser and builder. These changes were necessary to align +LIEF's PE functionality with its ELF and Mach-O counterparts. +If your codebase uses LIEF to process PE binaries, you may encounter issues when +upgrading to LIEF 0.17.0. This page provides a comprehensive overview of the +various changes, but it cannot cover every detail. If you encounter an API issue +that is not described here, you can: + +1. Join our Discord server and ask your questions: {sub-ref}`lief-discord` +2. Review the git diff of the tests. Most of these changes are covered by tests, + so you should be able to find a relevant example. +3. Email me at: `me[at]romainthomas.fr` + +## PE Modifications + +To explore the new modification features, you can check the following pages: + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + ../formats/pe/modifications/imports + ../formats/pe/modifications/resources + ../formats/pe/modifications/tls + ../formats/pe/modifications/debug + ../formats/pe/modifications/exports +``` + +## COFF String & COFF Symbol + +As described in issue {issue}`1043`, if a section name exceeds +8 bytes, the linker may allocate a longer name in the +COFF string pool while setting the section's name with the offset in the COFF +string pool. + +You can access this COFF string using {sub-ref}`lief-pe-section-coff_string`, while +the string representing the offset (e.g., `/230`) remains in the +section's name. + +Additionally, optional COFF symbols, along with any auxiliary symbols, are now +processed correctly by LIEF: + +```python +import lief + +pe = lief.PE.parse("libLIEF.dll") +section = pe.sections[10] +print(section.name) # --> '/19' +print(section.coff_string) # --> '.debug_info' + +for symbol in pe.symbols: + print(symbol.name) + for aux in symbol.auxiliary_symbols: + print(aux) +``` + +Although this example is written in Python, the API is also available in C++ +and Rust. + +## Load Configuration + +The `IMAGE_LOAD_CONFIG_DIRECTORY` structures, represented in LIEF by +{sub-ref}`lief-pe-loadconfig`, regularly evolve with new Windows releases. +New Windows versions may introduce attributes for additional +functionality, such as Control Flow Guard. To manage these changes, +{sub-ref}`lief-pe-loadconfig` previously used a form of inheritance. For each new +attribute, a new class, such as `LoadConfigurationV12`, would inherit from +`LoadConfigurationV11`. This approach, though systematic, resulted in numerous +modifications -- especially in Rust -- raising questions about the decision to use +inheritance. + +Starting with LIEF v0.17.0, {sub-ref}`lief-pe-loadconfig` has adopted a **flat** +representation. In this new model, version-dependent attributes are represented +with an `option<>`-like container. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +```{code-block} python +import lief + +pe = lief.PE.parse("demo.exe") +offset: Optional[int] = pe.load_configuration.hotpatch_table_offset +``` +::: +:::{tab} {fa}`regular fa-file-code` C++ +```{code-block} cpp +auto pe = LIEF::PE::Parser::parse("demo.exe"); + +if (const LoadConfiguration* lconf = pe->load_configuration()) { + LIEF::optional offset = lconf->hotpatch_table_offset(); +} +``` +::: +:::{tab} {fa}`brands fa-rust` Rust +```{code-block} rust +if let Some(lief::Binary::PE(pe)) = lief::Binary::parse("demo.exe") { + if let Some(lconf) = pe.load_configuration() { + let offset: Option = lconf.hotpatch_table_offset(); + } +} +``` +::: +:::: + +Additionally, {sub-ref}`lief-pe-loadconfig` now provides an API that allows access to +the internal data associated with this structure: + +- {sub-ref}`lief-pe-chpe_metadata` +- {sub-ref}`lief-pe-dynamic-relocation` +- {sub-ref}`lief-pe-enclave-configuration` +- {sub-ref}`lief-pe-volatile-metadata` + +Some of these structures are important to correctly support ARM64EC/ARM64X +PE binaries (#teasing). + +## Debug Information + +LIEF version 0.17.0 supports more types of debug entries and provides a +user-friendly API: + +- {sub-ref}`lief-pe-vcfeature` +- {sub-ref}`lief-pe-fpo` +- {sub-ref}`lief-pe-exdllcharacteristics` +- {sub-ref}`lief-pe-pdbchecksum` + +As described in the {ref}`Debug Modification ` +section, you can modify debug entries to perform various actions: + +```python +pe = lief.PE.parse("some.dll") +# Changing the PDB file path to a URL +pe.codeview_pdb.filename = "https://lief.re/" +pe.write("out.dll") +``` + +## Resources + +Some interfaces exposed by the {sub-ref}`lief-pe-resource-manager` have been redesigned +to make them more consistent with their underlying representation in the PE +format. + +For example, `lief.PE.LangCodeItem` has been renamed and refactored into +{sub-ref}`lief-pe-resourcestringtable`. + +Resource-related enums have been re-scoped to avoid definition conflicts +between Windows headers and LIEF: + +| `lief.PE.EXTENDED_WINDOW_STYLES` | {class}`lief.PE.ResourceDialog.WINDOW_EXTENDED_STYLES` | +| -------------------------------------- | -------------------------------------------------------------------- | +| `lief.PE.WINDOW_STYLES` | {class}`lief.PE.ResourceDialog.WINDOW_STYLES` | +| `lief.PE.DIALOG_BOX_STYLES` | {class}`lief.PE.ResourceDialog.DIALOG_STYLES` | +| `lief.PE.FIXED_VERSION_OS` | {class}`lief.PE.ResourceVersion.fixed_file_info_t.VERSION_OS` | +| `lief.PE.FIXED_VERSION_FILE_FLAGS` | {class}`lief.PE.ResourceVersion.fixed_file_info_t.FILE_FLAGS` | +| `lief.PE.FIXED_VERSION_FILE_SUB_TYPES` | {class}`lief.PE.ResourceVersion.fixed_file_info_t.FILE_TYPE_DETAILS` | +| `lief.PE.ACCELERATOR_FLAGS` | {class}`lief.PE.ResourceAccelerator.FLAGS` | +| `lief.PE.ACCELERATOR_VK_CODES` | {class}`lief.PE.ACCELERATOR_CODES` | + +## Exception Info + +For x86-64 and ARM64 PE binaries, stack unwinding information is referenced by +the data directory: `IMAGE_DIRECTORY_ENTRY_EXCEPTION`. Even if your code is +compiled without exception support, this information may still be generated by the linker. + +The entries of this data directory are represented by the +{sub-ref}`lief-pe-exceptioninfo` structure, which is specialized for x64 and +ARM64 functions. Regardless of the underlying architecture, each entry in this +table exposes a function RVA. +From a reverse engineering perspective, these RVAs offer a valuable set of +function start addresses that can be used to begin disassembling the binary. + +Given a {sub-ref}`lief-pe-binary` instance, one can iterate over these +{sub-ref}`lief-pe-exceptioninfo` entries using {sub-ref}`lief-pe-binary-exceptions`: + +```python +pe = lief.PE.parse("Windows.Media.Protection.PlayReady.dll", lief.PE.ParserConfgi.all) +print(pe.exceptions[10]) +``` + +```text +RuntimeFunctionX64 { + RVA: [0x0c9350, 0x0c9382] (50 bytes) + Unwind info RVA: 0x68eb5c + unwind_info_t { + Version: 1 + Flags: 0 + Size of prologue: 20 + Nb opcodes: 8 (6) + Opcodes: [ + 0x14 SAVE_NONVOL reg=RDI, offset=0x000078 + 0x14 SAVE_NONVOL reg=RBX, offset=0x000070 + 0x14 ALLOC_SMALL size=64 + 0x10 PUSH_NONVOL reg=R15 + 0x0e PUSH_NONVOL reg=R14 + 0x0c PUSH_NONVOL reg=R12 + ]; + } +} +``` + +```python +pe = lief.PE.parse("win11_arm64x_Windows.Media.Protection.PlayReady.dll", lief.PE.ParserConfgi.all) +print(pe.exceptions[10]) +``` + +```text +Runtime Unpacked AArch64 Function { + Range(RVA): 0x00822bb8 - 0x00822c08 + Unwind location (RVA): 0x00d63838 + Length=80 Vers=0 X=0 E=0, CodeWords=8 + Epilogs=1 + Prolog unwind: + 0x0000 e1...... mov fp, sp + 0x0001 81...... stp x29, x30, [sp, #-16]! + 0x0002 e6...... save next + 0x0003 e6...... save next + 0x0004 e6...... save next + 0x0005 e6...... save next + 0x0006 e76689.. stp q6, q7, [sp, #-160]! + 0x0009 fc...... pacibsp + 0x000a e4...... end + Epilog #1 unwind: (Offset=10, Index=11, Reserved=0) + 0x0000 81...... ldp x29, x30, [sp], #16 + 0x0001 e74e88.. ldp q14, q15, [sp, #128] + 0x0004 e74c86.. ldp q12, q13, [sp, #96] + 0x0007 e74a84.. ldp q10, q11, [sp, #64] + 0x000a e74882.. ldp q8, q9, [sp, #32] + 0x000d e76689.. ldp q6, q7, [sp], #160 + 0x0010 fc...... autibsp + 0x0011 e3...... nop + 0x0012 e3...... nop + 0x0013 e4...... end +} +``` + +:::{admonition} ARM64 - `SAVE_ANY_REG` +:class: tip + +Thank you to [Eli Friedman](https://github.com/efriedma-quic) and [Martin Storsjö](https://github.com/mstorsjo) +for their work on reverse engineering this undocumented unwind opcode. +::: + +LIEF provides a detailed API for the structures involved in PE +exceptions and stack unwinding. + +:::{admonition} Performance Considerations +:class: warning + +In-depth analysis of exception metadata can introduce significant overhead. +Therefore, {sub-ref}`lief-pe-parser-config-parse_exceptions` must be +**explicitly** enabled. +::: + +## ARM64EC / ARM64X + +With the recent release of Snapdragon X, ARM64-based Windows computers are +becoming increasingly popular. This shift introduces some changes to +the PE format. One notable change is the introduction of ARM64X binaries, which +can be compared to the Mach-O FAT concept, where a single binary contains multiple +architectures. + +In the case of ARM64X, a single PE file encapsulates ARM64 and ARM64EC architectures. +LIEF v0.17.0 exposes the following helpers to determine whether the binary is +ARM64X or ARM64EC: {sub-ref}`lief-pe-binary-is_arm64ec`, {sub-ref}`lief-pe-binary-is_arm64x`. + +For an ARM64X binary, you can use {sub-ref}`lief-pe-binary-nested_pe_binary` to access the +embedded ARM64EC **representation** of the binary. + +:::{admonition} Performance Considerations +:class: warning + +Parsing a nested ARM64EC binary can introduce additional overhead compared to +the 0.16.x version. +Therefore, {sub-ref}`lief-pe-parser-config-parse_arm64x_binary` must be +**explicitly** enabled. +::: + +## Other Changes + +The workaround involving `undef.h` has been removed. This file was used to +`#undef` certain Windows defines that conflicted with LIEF enum definitions. +You can now safely include Windows headers alongside LIEF headers. If you +encounter any conflicts, please report the issue. + +The *builder* engine has been refactored to resolve numerous errors and bugs +associated with PE modifications. It now uses a more conservative approach. +For more details, please refer to the {ref}`PE ` page. + +The *"PE from Scratch"* feature has been removed, as it had significant bugs +that often resulted in corrupted binaries. This feature will be reintroduced in +a future release. If you rely on this feature, please reach out. + +```{eval-rst} + +:List of changes: + + * Fixed missing original forwarded function name (:issue:`1166`) + + * |lief-pe-datadirectory| now exposes |lief-pe-datadirectory-content| to + access the raw bytes wrapped by the data directory + + * PE's resource tree can now be parsed in a standalone way using + |lief-pe-resource-node-parse|. + + .. code-block:: python + + resource_tree = bytes("....") + original_rva = 0x20000 + tree: lief.PE.ResourceNode = lief.PE.ResourceNode.parse(resource_tree, original_rva) +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/compilation.md b/vendor/lief/doc/sphinx/compilation.md new file mode 100644 index 0000000..f2e5e86 --- /dev/null +++ b/vendor/lief/doc/sphinx/compilation.md @@ -0,0 +1,242 @@ +```{eval-rst} +.. role:: strike + :class: strike +``` + +(compilation_ref)= + +# {fa}`solid fa-laptop-code` Compilation + +To compile **LIEF**, you need at least the following: + +- C++17 compiler (GCC, Clang, MSVC, etc.) +- CMake +- Python >= 3.10 (for the bindings) + +:::{note} +Compiling from scratch with all options enabled can take approximately +20 minutes on a standard laptop. +::: + +## Libraries only (SDK) + +```console +$ git clone https://github.com/lief-project/LIEF.git +$ cd LIEF +$ mkdir build +$ cd build +$ cmake -DCMAKE_BUILD_TYPE=Release .. +$ cmake --build . --target LIB_LIEF --config Release +``` + +:::{warning} +On Windows, you can choose which CRT to use by setting the +`CMAKE_MSVC_RUNTIME_LIBRARY` variable: + +```console +$ cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_MSVC_RUNTIME_LIBRARY=MultiThreaded .. +``` + +For Debug, you should set the CRT to **MTd**: + +```console +$ cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_MSVC_RUNTIME_LIBRARY=MultiThreadedDebug .. +$ cmake --build . --target LIB_LIEF --config Debug +``` +::: + +## Python bindings + +The Python bindings are built from the `api/python` directory, which uses a +[PEP 517](https://peps.python.org/pep-0517/) build backend based on +[scikit-build-core](https://scikit-build-core.readthedocs.io/): + +```console +$ git clone https://github.com/lief-project/LIEF.git +$ cd LIEF/api/python +$ pip install [-e] [--user] . +# Or +$ pip install [-e] api/python +``` + +:::{note} +You can speed up the compilation by installing [ccache](https://ccache.dev/) +or [sccache](https://github.com/mozilla/sccache). +::: + +You can customize the compilation by setting the `PYLIEF_CONF` environment +variable to the path of a TOML configuration file. By default, the Python +bindings use `config-default.toml` in the Python binding directory: + +```toml +[lief.build] +type = "Release" +cache = true +ninja = true +parallel-jobs = 0 + +[lief.formats] +elf = true +pe = false +macho = true +... +``` + +```console +$ PYLIEF_CONF=/tmp/my-custom.toml pip install . +``` + +(lief_free_threaded)= + +### Free-threaded Python + +Since LIEF 1.0.0, the Python bindings can be compiled against the free-threaded +Python builds. This is controlled through the +`free-threaded` flag of the `[lief.build]` section of the configuration: + +```toml +[lief.build] +type = "Release" +free-threaded = true +``` + +:::{warning} +When MbedTLS is resolved externally (`LIEF_OPT_MBEDTLS_EXTERNAL=ON`), you +must make sure that the provided build enables threading support. LIEF +cannot tweak the threading configuration in that case. +::: + +At runtime, you can check whether the currently loaded extension was compiled +with free-threading support through {attr}`lief.__free_threaded__`. + +## Runtime features + +The {ref}`runtime features ` are **not** enabled by default and +must be explicitly turned on. See {ref}`runtime-intro` for the CMake options +and TOML configuration used to enable the runtime module. + +(lief_debug)= + +## Debugging + +By default, LIEF is compiled with `CMAKE_BUILD_TYPE` set to `Release`. +You can change this behavior by setting it to either `RelWithDebInfo` or +`Debug` during CMake's configuration step: + +```console +$ cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo [...] .. +``` + +Alternatively, the Python bindings can also be compiled with debug information +by changing the `type` in the `[lief.build]` section of `config-default.toml`: + +```toml +[lief.build] +type = "RelWithDebInfo" +``` + +:::{note} +When developing LIEF, you can use: + +```console +$ PYLIEF_CONF=~/lief-debug.toml pip install [-e] api/python +``` + +With `lief-debug.toml` set to: + +```toml +[lief.build] +type = "RelWithDebInfo" +... + +[lief.logging] +enabled = true +debug = true +``` +::: + +(lief_third_party)= + +## Third Party + +LIEF relies on several external projects, and we aim to limit dependencies in +the public headers as much as possible. The following table summarizes these +dependencies and their scopes. `internal` means that it is required to +compile LIEF but not to use it. `external` means that it is required for both. + +| Dependency | Scope | Purpose | +| ---------------------------------------- | ---------- | ------------------------------------------ | +| {github-ref}`tcbrindle/span` | `external` | C++11 span interface | +| {github-ref}`TartanLlama/expected` | `external` | Error handling (see: {ref}`err_handling` ) | +| {github-ref}`gabime/spdlog` | `internal` | Logging | +| {github-ref}`Mbed-TLS/mbedtls` | `internal` | ASN.1 parser / Hash functions | +| {github-ref}`nemtrif/utfcpp` | `internal` | Unicode support (for PE and DEX files) | +| {github-ref}`nlohmann/json` | `internal` | Serialize LIEF objects into JSON | +| {github-ref}`wjakob/nanobind` | `internal` | Python bindings | +| {github-ref}`serge-sans-paille/frozen` | `internal` | `constexpr` containers | +| {github-ref}`IOActive/Melkor_ELF_Fuzzer` | `internal` | ELF Fuzzing | +| {github-ref}`catchorg/Catch2` | `internal` | Unit Testing | + +With the exception of MbedTLS, all of these dependencies are header-only. +By default, they are embedded and managed by LIEF to simplify compilation and +integration. + +Nevertheless, package managers often require linking against system libraries +rather than using vendored dependencies [^ref-issue] [^ref-vcpk]. + +To address this requirement, you can control the integration of LIEF's +dependencies using the following CMake options: + +> - `LIEF_OPT_NLOHMANN_JSON_EXTERNAL` +> - `LIEF_OPT_UTFCPP_EXTERNAL` +> - `LIEF_OPT_MBEDTLS_EXTERNAL` +> - `LIEF_EXTERNAL_SPDLOG` +> - `LIEF_OPT_FROZEN_EXTERNAL` +> - `LIEF_OPT_EXTERNAL_SPAN/LIEF_EXTERNAL_SPAN_DIR` +> - `LIEF_OPT_EXTERNAL_EXPECTED` +> - `LIEF_OPT_NANOBIND_EXTERNAL` + +By setting these flags, LIEF will resolve dependencies using CMake's +`find_package(...)`, which relies on `_DIR` to locate the package. + +For example, LIEF can be compiled using the following configuration: + +```console +$ cmake .. -GNinja \ + -DLIEF_OPT_NLOHMANN_JSON_EXTERNAL=ON \ + -Dnlohmann_json_DIR=/lief-third-party/json/install/lib/cmake/nlohmann_json \ + -DLIEF_OPT_MBEDTLS_EXTERNAL=on \ + -DMbedTLS_DIR=/lief-third-party/mbedtls/install/cmake +``` + +:::{warning} +As mentioned previously, MbedTLS is not header-only. This means that if it is *externalized*, the static +version of LIEF will not include the MbedTLS object files, and the end user will have to manually link +`LIEF.a` with a provided version of MbedTLS. +::: + +[^ref-issue]: + +[^ref-vcpk]: + +## Continuous Integration + +LIEF uses GitHub Actions to test and release nightly builds. The configuration +of this CI can also be a good source of information for the compilation process. +In particular, [scripts/docker/linux-sdk-x64](https://github.com/lief-project/LIEF/blob/main/scripts/docker/linux-sdk-x64) +contains the build process to generate the **Linux x86-64 SDK**. + +On Windows, the SDK is built with the following Python script: +[scripts/windows/package_sdk.py](https://github.com/lief-project/LIEF/blob/main/scripts/windows/package_sdk.py) + +For **OSX**, refer to the CI config [.github/workflows/osx.yml](https://github.com/lief-project/LIEF/blob/main/.github/workflows/osx.yml), +and for **iOS**, see the [scripts/osx/package_ios.sh](https://github.com/lief-project/LIEF/blob/main/scripts/osx/package_ios.sh) +script, to see how LIEF is compiled (and cross-compiled) for these platforms. + +## CMake Options + +{{ literalinclude("../../cmake/LIEFOptions.cmake") }} + +## Docker + +See [liefproject](https://hub.docker.com/u/liefproject) on Docker Hub diff --git a/vendor/lief/doc/sphinx/compilation.rst b/vendor/lief/doc/sphinx/compilation.rst deleted file mode 100644 index ad3c11c..0000000 --- a/vendor/lief/doc/sphinx/compilation.rst +++ /dev/null @@ -1,221 +0,0 @@ -.. role:: strike - :class: strike - -Compilation -=========== - -To compile **LIEF**, you need at least the following requirements: - -- C++14 compiler (GCC, Clang, MSVC..) -- CMake -- Python >= 3.6 (for the bindings) - -To build the documentation: - -- Doxygen (= ``1.8.10``, the CI uses ``1.8.20``) -- Sphinx (with ``sphinx_rtd_theme`` module) -- breathe (>= ``4.25.1``) - -.. note:: - - A compilation from scratch with all the options enabled can take ~30 minutes on a regular laptop. - -Libraries only (SDK) --------------------- - -.. code-block:: console - - $ git clone https://github.com/lief-project/LIEF.git - $ cd LIEF - $ mkdir build - $ cd build - $ cmake -DLIEF_PYTHON_API=off -DCMAKE_BUILD_TYPE=Release .. - $ cmake --build . --target LIB_LIEF --config Release - -.. warning:: - - On Windows one can choose the CRT to use by setting the ``LIEF_USE_CRT_`` variable: - - .. code-block:: console - - $ cmake -DCMAKE_BUILD_TYPE=Release -DLIEF_USE_CRT_RELEASE=MT .. - - For Debug, you should set the CRT to **MTd**: - - .. code-block:: - - $ cmake -DCMAKE_BUILD_TYPE=Debug -DLIEF_USE_CRT_DEBUG=MTd .. - $ cmake --build . --target LIB_LIEF --config Debug - - - -Library and Python bindings ---------------------------- - -.. code-block:: console - - $ git clone https://github.com/lief-project/LIEF.git - $ cd LIEF - $ python ./setup.py [--ninja] build install [--user] - -.. note:: - - You can speed-up the compilation by installing `ccache `_ or `sccache `_ - -If you want to enable tests, you can add ``--lief-test`` after ``setup.py``. - -.. _lief_debug: - -Debugging ---------- - -By default, LIEF is compiled with ``CMAKE_BUILD_TYPE`` set to ``Release``. One can change this behavior -by setting either ``RelWithDebInfo`` or ``Debug`` during the cmake's configuration step: - -.. code-block:: console - - $ cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo [...] .. - -On the other hand, Python bindings can also be compiled with debug information by using -the ``--debug`` flag: - -.. code-block:: console - - $ python ./setup.py build --debug - - -.. note:: - - When developing on LIEF, you can use: - - .. code-block:: console - - $ python ./setup [--ninja] build --debug develop --user - - Compared to the ``install`` command, ``develop`` creates a ``.egg-link`` - that links to the native LIEF library currently presents in you build directory. - - The ``--user`` flag is used to avoid creating the ``.egg-link`` system-wide (i.e. ``/usr/lib/python3.9/site-packages``). - Instead, it links the ``.egg-link`` in the user's local dir (e.g. ``~/.local/lib/python3.9/site-packages``) - - -.. _lief_third_party: - -Third Party ------------ - -LIEF relies on few external projects and we try to limit as much as possible -the dependencies in the public headers. This table summarizes these -dependencies and their scope. ``internal`` means that it is required to compile -LIEF but it is not required to use LIEF. ``external`` means that it is required for both. - -+-----------------------------------+--------------+--------------------------------------------+ -| Dependency | Scope | Purpose | -+-----------------------------------+--------------+--------------------------------------------+ -| `tcb/span `_ | ``external`` | C++11 span interface | -+-----------------------------------+--------------+--------------------------------------------+ -| `Boost Leaf `_ | ``external`` | Error handling (see: :ref:`err_handling` ) | -+-----------------------------------+--------------+--------------------------------------------+ -| `spdlog `_ | ``internal`` | Logging | -+-----------------------------------+--------------+--------------------------------------------+ -| `MbedTLS `_ | ``internal`` | ASN.1 parser / Hash functions | -+-----------------------------------+--------------+--------------------------------------------+ -| `utfcpp `_ | ``internal`` | Unicode support (for PE and DEX files) | -+-----------------------------------+--------------+--------------------------------------------+ -| `json `_ | ``internal`` | Serialize LIEF's object into JSON | -+-----------------------------------+--------------+--------------------------------------------+ -| `pybind11 `_ | ``internal`` | Python bindings | -+-----------------------------------+--------------+--------------------------------------------+ -| `Frozen `_ | ``internal`` | ``constexpr`` containers | -+-----------------------------------+--------------+--------------------------------------------+ -| `Catch2 `_ | ``internal`` | Testing | -+-----------------------------------+--------------+--------------------------------------------+ -| `Melkor ELF Fuzzer `_ | ``internal`` | ELF Fuzzing | -+-----------------------------------+--------------+--------------------------------------------+ - -.. _span_ref: https://github.com/tcbrindle/span -.. _spdlog_ref: https://github.com/gabime/spdlog -.. _mbedtls_ref: https://github.com/ARMmbed/mbedtls -.. _leaf_ref: https://github.com/boostorg/leaf -.. _utfcpp_ref: https://github.com/nemtrif/utfcpp -.. _json_ref: https://github.com/nlohmann/json -.. _pybind11_ref: https://github.com/pybind/pybind11 -.. _frozen_ref: https://github.com/serge-sans-paille/frozen -.. _melkor_ref: https://github.com/IOActive/Melkor_ELF_Fuzzer - -Except MbedTLS, all these dependencies are header-only and they are by default embedded/managed by LIEF such as it -eases the compilation and the integration. - -Nevertheless, packages manager might require to not self-use/embed external dependencies [#ref_issue]_ [#ref_vcpk]_. - -To address this requirement, the user can control the integration of LIEF's dependencies using the following -cmake's options: - - * ``LIEF_OPT_NLOHMANN_JSON_EXTERNAL`` - * ``LIEF_OPT_EXTERNAL_LEAF`` / ``LIEF_EXTERNAL_LEAF_DIR`` - * ``LIEF_OPT_UTFCPP_EXTERNAL`` - * ``LIEF_OPT_MBEDTLS_EXTERNAL`` - * ``LIEF_EXTERNAL_SPDLOG`` - * ``LIEF_OPT_FROZEN_EXTERNAL`` - * ``LIEF_OPT_EXTERNAL_SPAN/LIEF_EXTERNAL_SPAN_DIR`` - * ``LIEF_OPT_PYBIND11_EXTERNAL`` - -By setting these flags, LIEF resolves the dependencies with CMake ``find_package(...)`` which -is aware of ``_DIR`` to find the package. Boost's Leaf does not provide -CMake files that can be resolved with ``find_package`` so the user can provide ``LIEF_EXTERNAL_LEAF_DIR`` instead, -which must point to the directory that contains ``boost/leaf``. - -As a result, LIEF can be, for instance, compiled with the following configuration: - -.. code-block:: console - - $ cmake .. -GNinja \ - -DLIEF_OPT_NLOHMANN_JSON_EXTERNAL=ON \ - -Dnlohmann_json_DIR=/lief-third-party/json/install/lib/cmake/nlohmann_json \ - -DLIEF_OPT_MBEDTLS_EXTERNAL=on \ - -DMbedTLS_DIR=/lief-third-party/mbedtls/install/cmake \ - -DLIEF_OPT_EXTERNAL_LEAF=on \ - -DLIEF_EXTERNAL_LEAF_DIR=/lief-third-party/leaf/include/cmake - -.. warning:: - - As mentioned previously, MbedTLS is not header-only which means that if it is *externalized* the static - version of LIEF won't include the MbedTLS object files and the end user will have to link again ``LIEF.a`` - with a provided version of MbedTLS. - -.. [#ref_issue] https://github.com/lief-project/LIEF/issues/605 -.. [#ref_vcpk] https://github.com/microsoft/vcpkg/blob/master/docs/maintainers/maintainer-guide.md#do-not-use-vendored-dependencies - -Continuous Integration ----------------------- - -LIEF uses different CI (Github Action, AppVeyor, ...) to test and release nightly builds. The configuration -of these CI can also be a good source of information for the compilation process. -In particular, `scripts/docker/travis-linux-sdk.sh `_ -contains the build process to generate the **Linux x86-64 SDK**. - -The ``build_script`` section of `.appveyor.yml `_ -contains the logic for generating **Windows Python wheels and the SDK**. - -For **OSX & iOS**, the CI configs `.github/workflows/ios.yml `_ -and `.github/workflows/osx.yml `_ -to compile (and cross-compile) LIEF for these platforms. - -CMake Options -------------- - -.. literalinclude:: ../../cmake/LIEFOptions.cmake - -Docker ------- - - -See `liefproject `_ on Dockerhub - -.. container:: strike - - See the `Dockerlief `_ repo. - - - - diff --git a/vendor/lief/doc/sphinx/conf.py b/vendor/lief/doc/sphinx/conf.py index 61979ec..8d2ee1d 100644 --- a/vendor/lief/doc/sphinx/conf.py +++ b/vendor/lief/doc/sphinx/conf.py @@ -1,191 +1,107 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- -# -# LIEF documentation build configuration file - -import lief -import os -import pathlib -from docutils import nodes - -GENERATE_DOXYGEN = False -DOXYGEN_XML_PATH = None -USE_RTD_THEME = False - -try: - import sphinx_lief -except Exception: - import sphinx_rtd_theme - USE_RTD_THEME = True - - -try: - import breathe - DOXYGEN_XML_PATH = os.getenv("LIEF_DOXYGEN_XML", None) - if DOXYGEN_XML_PATH is not None and pathlib.Path(DOXYGEN_XML_PATH).exists(): - DOXYGEN_XML_PATH = pathlib.Path(DOXYGEN_XML_PATH).resolve().absolute() - GENERATE_DOXYGEN = True -except Exception: - GENERATE_DOXYGEN = False - - -FORCE_RTD_THEME = os.environ.get("FORCE_RTD_THEME", False) -FORCE_RTD_THEME = FORCE_RTD_THEME in ("1", "true", "yes") - -if FORCE_RTD_THEME: - import sphinx_rtd_theme - -USE_RTD_THEME = USE_RTD_THEME or FORCE_RTD_THEME +import sys +from pathlib import Path + +sys.path.insert(0, Path(__file__).parent.as_posix()) + +from sphinx.application import Sphinx +from sphinx_lief_doc.ai import setup as setup_ai +from sphinx_lief_doc.config import init_config as lief_init_config +from sphinx_lief_doc.img_comparison import setup as setup_img_comparison +from sphinx_lief_doc.inheritance_diagram import LIEFInheritanceDiagram +from sphinx_lief_doc.lief_api import setup as setup_lief_api +from sphinx_lief_doc.literalinclude import LiteralInclude +from sphinx_lief_doc.plugin_package import setup as setup_plugin_packages +from sphinx_lief_doc.python_typing import setup as setup_python_typing +from sphinx_lief_doc.roles import setup as setup_roles +from sphinx_lief_doc.rust_domain import RustDomain +from sphinx_lief_doc.sdk_package import setup as setup_sdk_packages +from sphinx_lief_doc.seo import setup as setup_seo +from sphinx_lief_doc.writers.html5 import HTML5Translator extensions = [ - 'sphinx.ext.mathjax', - 'sphinx.ext.autodoc', + "myst_parser", + "sphinx.ext.mathjax", + "sphinx.ext.autodoc", + "sphinx.ext.extlinks", + "sphinx_tabs.tabs", + "sphinx.ext.inheritance_diagram", + "breathe", + "sphinx_lief", ] -if GENERATE_DOXYGEN: - extensions += ["breathe"] - breathe_projects = { - "lief": DOXYGEN_XML_PATH, - } - # Add any paths that contain templates here, relative to this directory. -templates_path = ['_templates'] - -source_suffix = '.rst' - -master_doc = 'index' - -project = 'LIEF' -html_title = "LIEF Documentation" -copyright = '2020, Quarkslab' -author = 'Romain Thomas' - -version = lief.__tag__ if lief.__is_tagged__ else lief.__version__ -release = lief.__version__ -commit = lief.__commit__ - -language = "en" -autoclass_content = 'both' +templates_path = ["_templates"] +source_suffix = {".md": "markdown"} +exclude_patterns = ["_cross_api.md"] -if GENERATE_DOXYGEN: - breathe_default_members = ('members', 'protected-members', 'undoc-members') - breathe_show_enumvalue_initializer = True - -exclude_patterns = [] - -# -- Options for HTML output ---------------------------------------------- -def commit_role(name, rawtext, text, lineno, inliner, options={}, content=[]): - commit_link = nodes.reference( - "", text[:7], refuri="https://github.com/lief-project/LIEF/commit/{}".format(text), **options) - - return [commit_link], [] - - -def pr_role(name, rawtext, text, lineno, inliner, options={}, content=[]): - pr_link = nodes.reference( - "", '#' + text, refuri="https://github.com/lief-project/LIEF/pull/{}".format(text), **options) - - return [pr_link], [] - - -def issue_role(name, rawtext, text, lineno, inliner, options={}, content=[]): - issue_link = nodes.reference( - "", '#' + text, refuri="https://github.com/lief-project/LIEF/issues/{}".format(text), **options) +myst_enable_extensions = [ + "colon_fence", + "substitution", +] +myst_all_links_external = True +myst_footnote_sort = False +myst_substitutions = { + "cross_api": "```{include} /_cross_api.md\n```", + "literalinclude": LiteralInclude(), +} - return [issue_link], [] +extlinks = { + "github-ref": ("https://github.com/%s", "%s"), + "llvm-pr": ("https://github.com/llvm/llvm-project/pull/%s", "llvm/llvm-project#%s"), +} -def github_user(name, rawtext, text, lineno, inliner, options={}, content=[]): - issue_link = nodes.reference( - "", text, refuri="https://github.com/{}".format(text), **options) +# Can be used for debugging breathe +# breathe_debug_trace_directives = True +# breathe_debug_trace_doxygen_ids = True +# breathe_debug_trace_qualification = True - return [issue_link], [] +master_doc = "index" -def setup(app): - app.add_css_file('css/custom.css') # may also be an URL +suppress_warnings = ["config.cache"] - app.add_role('commit', commit_role) - app.add_role('pr', pr_role) - app.add_role('issue', issue_role) - app.add_role('github_user', github_user) +project = "LIEF" +html_title = "LIEF Documentation" +copyright = "2020, Quarkslab" +author = "Romain Thomas" -linkcheck_request_headers = { - "*": { - "Accept": "text/html,application/atom+xml", - "User-Agent": "Mozilla/5.0 (X11; Linux x86_64; rv:83.0) Gecko/20100101 Firefox/83.0", - } +language = "en" +autoclass_content = "both" +autodoc_default_options = { + "exclude-members": "@entries", + "undoc-members": True, + "inherited-members": False, + "show-inheritance": False, + "members": True, } -linkcheck_workers = 1 -linkcheck_ignore = [ - 'https://github.com', - 'http://github.com', -] - - -if not USE_RTD_THEME: - pygments_style = "xcode" - endpoint = "stable" if lief.__is_tagged__ else "latest" - extensions.append("sphinx_lief") - html_theme_path = sphinx_lief.html_theme_path() - html_context = sphinx_lief.get_html_context() - html_theme = "sphinx_lief" - html_base_url = "https://lief-project.github.io/" - base_url = "{}/doc/{}".format(html_base_url, endpoint) - html_theme_options = { - "commit": commit, - "base_url": "{}/".format(base_url), - "repo_url": "https://github.com/lief-project/LIEF/", - "repo_name": "LIEF", - "html_minify": True, - "html_prettify": False, - "css_minify": True, - "logo_icon": "logo_blue.png", - "globaltoc_depth": 2, - "color_primary": "blue", - "color_accent": "cyan", - "touch_icon": "favicon.ico", - "nav_links": [ - { - "href": html_base_url, - "internal": False, - "title": "Home" - }, - { - "href": "{}/blog".format(html_base_url), - "internal": False, - "title": "Blog" - }, - { - "href": "{}/download".format(html_base_url), - "internal": False, - "title": "Download" - }, - { - "href": "index", - "internal": True, - "title": "Documentation", - "subnav": [ - { - "title": "Doxygen", - "href": "{}/doxygen".format(base_url), - }, - ] - }, - { - "href": "{}/about".format(html_base_url), - "internal": False, - "title": "About", - }, - ], - "table_classes": ["plain"], - } -else: - html_theme = "sphinx_rtd_theme" - html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] - -html_last_updated_fmt = '%d/%m/%Y, %H:%M:%S' -html_logo = '_static/logo_blue.png' -html_favicon = '_static/favicon.ico' -html_static_path = ['_static'] - -htmlhelp_basename = 'LIEFdoc' +# exclude_patterns = [ +# "api", +# "tutorials/*.md", +# "changelog/*.md", +# "extended", +# "formats", +# "changelog.md", +# "references.md", +# "intro.md", +# "installation.md", +# "compilation.md", +# ] + + +def setup(app: Sphinx): + lief_init_config(app) + + app.add_css_file("css/custom.css") # may also be an URL + app.add_domain(RustDomain) + + setup_python_typing(app) + setup_roles(app) + setup_lief_api(app) + setup_img_comparison(app) + setup_plugin_packages(app) + setup_sdk_packages(app) + setup_seo(app) + setup_ai(app) + + app.add_directive("lief-inheritance", LIEFInheritanceDiagram) + app.set_translator("html", HTML5Translator) diff --git a/vendor/lief/doc/sphinx/error_handling.rst b/vendor/lief/doc/sphinx/error_handling.rst deleted file mode 100644 index d25afcf..0000000 --- a/vendor/lief/doc/sphinx/error_handling.rst +++ /dev/null @@ -1,60 +0,0 @@ -.. _err_handling: - -Error Handling -============== - -Currently, LIEF manages the errors using two mechanisms: - -1. The exceptions (widely used) -2. `Boost's LEAF `_ - -It turns out that using the C++ exceptions (and the RTTI) were not the better design choice as LIEF (as a -library) can be used in ``-fno-exceptions`` context. This is why we are slowly moving to the second mechanism -which is based on the ``ResultOrError`` idiom. We can find this kind idiom in LLVM with `llvm::ErrorOr `_, -in Rust with `std::result `_ and in `Boost LEAF `_. -We based our implementation from Boost LEAF as can be integrated smoothly in LIEF. - -Basically, the LIEF functions that use this idiom return a :cpp:type:`LIEF::result` which wraps the effective -result or an error. - -The user can process this result as follows: - -.. code-block:: cpp - - result pe_type = PE::get_type("/tmp/NotPE.elf") - if (pe_type) { - PE_TYPE effective_type = pe_type.value(); - } else { - lief_errors err = as_lief_err(pe_type); - } - -In the case of Python, we leverage the *dynamic* features of the language to return either: the expected value -or an error if the function failed. For instance, if we take the :func:`lief.PE.get_type` function, -the former implementation of this function raised an exception to inform the user: - -.. code-block:: python - - try: - pe_type = lief.PE.get_type("/tmp/NotPE.elf") - # If it does not fail, pe_type handles a lief.PE.PE_TYPE object - except Exception as e: - print(f"Error: {e}") - -With the new implementation that relies on the ``ResultOrError`` idiom, the function returns the -:class:`lief.PE.PE_TYPE` value is everything is ok and in the case of a processing error, it returns a -:class:`lief.lief_errors`. - -The user can handle this new interface by using the ``isinstance()`` function or by comparing the value with -a :class:`lief.lief_errors` attribute: - -.. code-block:: python - - pe_type = lief.PE.get_type("/tmp/NotPE.elf") - - if pe_type == lief.lief_errors.file_error: - print("File error") - elif isinstance(pe_type, lief.lief_errors): - print("Another kind of error") - else: - print("No error, type is: {}".format(pe_type)) - diff --git a/vendor/lief/doc/sphinx/extended/assembler/cpp.md b/vendor/lief/doc/sphinx/extended/assembler/cpp.md new file mode 100644 index 0000000..75f7cbd --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/assembler/cpp.md @@ -0,0 +1,10 @@ +# {fa}`regular fa-file-code` C++ + +- {cpp:func}`LIEF::Binary::assemble` +- {cpp:class}`LIEF::assembly::Engine` + +## AssemblerConfig + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::AssemblerConfig +``` diff --git a/vendor/lief/doc/sphinx/extended/assembler/index.md b/vendor/lief/doc/sphinx/extended/assembler/index.md new file mode 100644 index 0000000..de95fe4 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/assembler/index.md @@ -0,0 +1,181 @@ +--- +description: Patch executable code with LIEF Extended, choose virtual addresses and patch sizes, and resolve symbols through an assembler configuration. +--- + +(extended-assembler)= + +# {fa}`solid fa-user-secret` Assembler + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +LIEF Extended can assemble instructions and patch them into a parsed binary with +{sub-ref}`lief-assemble`. + +## Patch a binary + +Pass a virtual address in the binary and assembly text for its architecture. +The following example assumes an AArch64 ELF binary: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/assembler.py", "disassemble-assemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/assembler.cpp", "disassemble-assemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/assembler.rs", "disassemble-assemble") }} +::: +:::: + +The call returns the generated bytes and patches the binary object. Save the +result with the format's write API, such as {sub-ref}`lief-elf-binary-write`, +{sub-ref}`lief-pe-binary-write`, or {sub-ref}`lief-macho-binary-write`. + +:::{warning} +The assembler works well for `AArch64/ARM64E`, `x86/x86-64`, and `RISC-V` +but support for other architectures is currently limited. +::: + +## Technical Details + +Similar to the {ref}`disassembler `, this assembler is +based on the LLVM MC layer. + +The assembly text is consumed by the `llvm::MCAsmParser` object, and we +*intercept* the raw generated assembly bytes from the `llvm::MCObjectWriter`. + +We also resolve `llvm::MCFixup` for a vast majority of the generated fixups. +An important feature introduced in LIEF 0.17.0 is support for resolving symbols +or labels **on the fly**. + +(extended-assembler-contextual-patching)= + +## Contextual Assembly Patching + +Given assembly code and a target address, we might want to use a **context** +to resolve symbols referenced in the assembly listing. + +For example, consider the following x86-64 patch: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/assembler.py", "context-error") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/assembler.cpp", "context-error") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/assembler.rs", "context-error") }} +::: +:::: + +In this example, `a_custom_function` is undefined, so the assembler engine +cannot resolve it and reports an unresolved fixup: + +```text +warning: Fixup not resolved: + call a_custom_function +``` + +LIEF exposes a {sub-ref}`lief-asm-AssemblerConfig` interface that can be used to +configure the engine and to **dynamically** resolve symbols used in the assembly +listing: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/assembler.py", "config-resolver", emphasize_lines="1-9,19") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/assembler.cpp", "config-resolver", emphasize_lines="1-9,11,19") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/assembler.rs", "config-resolver", emphasize_lines="3-12,20") }} +::: +:::: + +Return the symbol's address in the same address space as the patch, or no value +when it cannot be resolved. An unresolved symbol diagnostic needs to be handled +before using the resulting patch. + +This interface can be used to wrap a context, such as a generic +{sub-ref}`lief-abstract-binary`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/assembler.py", "config-target", prepend="import lief", emphasize_lines="6,10-13,16") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/assembler.cpp", "config-target", emphasize_lines="4-6,9-12,22") }} +::: +:::: + +The Rust bindings do not offer the same flexibility to capture the +{sub-ref}`lief-abstract-binary`. Nevertheless, the closure associated with the +{rust:member}`lief::assembly::AssemblerConfig::symbol_resolver [struct]` +can capture most of its context: + +::::{tabs} +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/assembler.rs", "config-target", emphasize_lines="5-12") }} +::: +:::: + +## Use Cases + +Patching code with the assembler is a fast alternative to editing raw bytes by +hand: it is useful for bypassing a check while reverse engineering, +hot-patching a bug in a shipped executable, or inserting instrumentation. + +### Disabling an Instruction + +To strip a single instruction like a call to a telemetry or anti-debugging +routine *without* shifting the rest of the +function we can overwrite it with as many `nop` bytes as it occupied. Pairing the +{ref}`disassembler ` with {sub-ref}`lief-assemble` lets you +do this: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/assembler.py", "nop-out") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/assembler.cpp", "nop-out") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/assembler.rs", "nop-out") }} +::: +:::: + +:::{note} +The snippets above assume `x86/x86-64`, where a `nop` is a single byte, +so `inst.size` of them fill the slot exactly. On a fixed-width instruction set such as +`AArch64` every instruction is 4 bytes, so we would emit `inst.size / 4` instead. +::: + +## In-Memory Assembler + +In addition to patching binaries on disk or within standard file formats, the +assembly engine is also available for JIT compilation and in-memory operations. +This is exposed through the runtime API {sub-ref}`lief-runtime-assemble`, as detailed in the +{ref}`Runtime Memory ` documentation. + +## API + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` {doc}`Rust API ` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/assembler/python.md b/vendor/lief/doc/sphinx/extended/assembler/python.md new file mode 100644 index 0000000..ae3e31d --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/assembler/python.md @@ -0,0 +1,10 @@ +# {fa}`brands fa-python` Python + +- {meth}`lief.Binary.assemble` +- {class}`lief.assembly.Engine` + +## AssemblerConfig + +```{eval-rst} +.. autoclass:: lief.assembly.AssemblerConfig +``` diff --git a/vendor/lief/doc/sphinx/extended/assembler/rust.md b/vendor/lief/doc/sphinx/extended/assembler/rust.md new file mode 100644 index 0000000..d31d950 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/assembler/rust.md @@ -0,0 +1,3 @@ +# {fa}`brands fa-rust` Rust + +- {rust:method}`lief::generic::Binary::assemble [trait]` diff --git a/vendor/lief/doc/sphinx/extended/debug_info/index.md b/vendor/lief/doc/sphinx/extended/debug_info/index.md new file mode 100644 index 0000000..35380c1 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/debug_info/index.md @@ -0,0 +1,87 @@ +--- +description: Load DWARF and PDB debug information, attach matching debug files to binaries, and navigate the shared Python, C++, and Rust APIs. +--- + +(debug-info)= + +# {fa}`solid fa-magnifying-glass` Debug Information + +Debug information connects machine code with source-level names, types, +functions, variables, and locations. {ref}`LIEF Extended ` reads +{ref}`DWARF ` and {ref}`PDB ` through format-specific +APIs and the common interfaces documented below. + +## Choose how to load debug information + +| Input | Starting point | +| --- | --- | +| A binary containing DWARF sections | Parse the binary and access {sub-ref}`lief-dwarf-binary-debug-info` | +| A separate DWARF file or a Mach-O debug companion | Load it with {sub-ref}`lief-dwarf-load` | +| A PDB file | Load it with {sub-ref}`lief-pdb-load` | +| A parsed binary and its matching external debug file | Attach the file with {sub-ref}`lief-abstract-binary-load_debug_info` | + + +Attaching an external file makes its information available to the parsed binary. +The {sub-ref}`lief-disassemble` API can then disassemble functions by name. Attaching the +file does not embed it into the executable. Use the debug file from the same +build: {sub-ref}`lief-abstract-binary-load_debug_info` does not verify build IDs or +PDB identifiers for you. + +The {ref}`DWARF ` and {ref}`PDB ` guides show how to +iterate over compilation units, find functions and types, and generate C/C++ +declarations. + +## Shared API reference + +### {fa}`regular fa-file-code` C++ + +#### DebugInfo + +```{eval-rst} +.. doxygenclass:: LIEF::DebugInfo +``` + +#### debug_location_t + +```{eval-rst} +.. doxygenstruct:: LIEF::debug_location_t +``` + +#### DeclOpt + +```{eval-rst} +.. doxygenclass:: LIEF::DeclOpt +``` + +______________________________________________________________________ + +### {fa}`brands fa-python` Python + +#### DebugInfo + +```{eval-rst} +.. autoclass:: lief.DebugInfo + +``` + +#### debug_location_t + +```{eval-rst} +.. autoclass:: lief.debug_location_t +``` + +#### DeclOpt + +```{eval-rst} +.. autoclass:: lief.DeclOpt +``` + +______________________________________________________________________ + +### {fa}`brands fa-rust` Rust + +- {rust:trait}`lief::generic::DebugInfo` +- {rust:struct}`lief::DebugLocation` +- {rust:struct}`lief::DeclOpt` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/aarch64.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/aarch64.md new file mode 100644 index 0000000..772582b --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/aarch64.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` AArch64 + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::Instruction +``` + +## Opcodes + +See `LIEF::assembly::aarch64::OPCODE` in `include/asm/aarch64/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::aarch64::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/arm.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/arm.md new file mode 100644 index 0000000..6996d44 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/arm.md @@ -0,0 +1,12 @@ +# {fa}`solid fa-microchip` ARM + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::arm::Instruction + +``` + +## Opcodes + +See `LIEF::assembly::arm::OPCODE` in `include/asm/arm/opcodes.hpp` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/ebpf.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/ebpf.md new file mode 100644 index 0000000..c8dff18 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/ebpf.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` eBPF + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::Instruction +``` + +## Opcodes + +See `LIEF::assembly::ebpf::OPCODE` in `include/asm/ebpf/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::ebpf::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/mips.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/mips.md new file mode 100644 index 0000000..ba36b21 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/mips.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` Mips + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::Instruction +``` + +## Opcodes + +See `LIEF::assembly::mips::OPCODE` in `include/asm/mips/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::mips::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/powerpc.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/powerpc.md new file mode 100644 index 0000000..2f20a32 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/powerpc.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` PowerPC + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::Instruction +``` + +## Opcodes + +See `LIEF::assembly::powerpc::OPCODE` in `include/asm/powerpc/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::powerpc::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/riscv.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/riscv.md new file mode 100644 index 0000000..a1afabd --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/riscv.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` RISC-V + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::Instruction +``` + +## Opcodes + +See `LIEF::assembly::riscv::OPCODE` in `include/asm/riscv/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::riscv::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/x86.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/x86.md new file mode 100644 index 0000000..46736d1 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/arch/x86.md @@ -0,0 +1,41 @@ +# {fa}`solid fa-microchip` X86/x86-64 + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::Instruction +``` + +## Opcodes + +See `LIEF::assembly::x86::OPCODE` in `include/asm/x86/opcodes.hpp` + +## Operands + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::Operand +``` + +### Immediate + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::operands::Immediate +``` + +### Register + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::operands::Register +``` + +### Memory + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::operands::Memory +``` + +### PCRelative + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::x86::operands::PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/cpp/index.md b/vendor/lief/doc/sphinx/extended/disassembler/cpp/index.md new file mode 100644 index 0000000..1c9ecde --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/cpp/index.md @@ -0,0 +1,29 @@ +# {fa}`regular fa-file-code` C++ + +## Architectures + +```{eval-rst} +.. toctree:: + :caption:  Architectures + :maxdepth: 1 + + arch/x86 + arch/aarch64 + arch/riscv + arch/arm + arch/ebpf + arch/mips + arch/powerpc +``` + +## Engine + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::Engine +``` + +## Instruction + +```{eval-rst} +.. doxygenclass:: LIEF::assembly::Instruction +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/index.md b/vendor/lief/doc/sphinx/extended/disassembler/index.md new file mode 100644 index 0000000..bdc87b0 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/index.md @@ -0,0 +1,211 @@ +--- +description: Disassemble executable code with LIEF Extended, inspect architecture-specific instructions and operands, and use debug information or live memory. +--- + +(extended-disassembler)= + +# {fa}`solid fa-dna` Disassembler + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp/index + python/index + rust +``` + +## Introduction + +LIEF Extended provides a user-friendly API for disassembling code within various +parts of executable formats for the following architectures: +x86/x86-64, ARM, AArch64, RISC-V, MIPS, PowerPC, and eBPF. + +## Disassemble a binary + +You can begin disassembling code within a binary using the {sub-ref}`lief-disassemble` +function, which is exposed in the abstraction layer: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/disassembler.py", "disassemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/disassembler.cpp", "disassemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/disassembler.rs", "disassemble") }} +::: +:::: + +From a design perspective, the disassembler returns a *lazy* iterator, +yielding a {sub-ref}`lief-asm-instruction` instance as it evaluates the +instruction at each address. + +Consequently, when calling `elf.disassemble_address(0x400)`, no disassembly +occurs until the iterator is advanced. + +## Inspect instructions and operands + +Instructions are represented by the {sub-ref}`lief-asm-instruction` object, +which is extended by architecture-specific objects: + +- {sub-ref}`lief-asm-x86-instruction` +- {sub-ref}`lief-asm-arm-instruction` +- {sub-ref}`lief-asm-aarch64-instruction` +- {sub-ref}`lief-asm-powerpc-instruction` +- {sub-ref}`lief-asm-mips-instruction` +- {sub-ref}`lief-asm-riscv-instruction` +- {sub-ref}`lief-asm-ebpf-instruction` + +In Python, use pattern matching or `isinstance(...)` to select an +architecture-specific {sub-ref}`lief-asm-instruction`: + +{{ literalinclude("../../../code/python/disassembler.py", "downcast") }} + +In C++, use {sub-ref}`lief-asm-instruction-as` to access the architecture-specific +instruction: + +{{ literalinclude("../../../code/cpp/disassembler.cpp", "downcast") }} + +In Rust, match the architecture variant of {sub-ref}`lief-asm-instruction`: + +{{ literalinclude("../../../code/rust/src/disassembler.rs", "downcast") }} + +:::{note} +You can also check the assembler documentation here: {ref}`Assembler ` +::: + +For the `x86/x86-64` and `AArch64` architectures, you can also iterate +over an instruction's operands: + +::::{tabs} +:::{tab} {fa}`solid fa-microchip` AArch64 +{{ literalinclude("../../../code/python/disassembler.py", "operands-aarch64", prepend="import lief") }} +::: +:::{tab} {fa}`solid fa-microchip` x86/x86-64 +{{ literalinclude("../../../code/python/disassembler.py", "operands-x86", prepend="import lief") }} +::: +:::: + +See the architecture-specific {doc}`Python ` and +{doc}`C++ ` references for operand types and instruction properties. +To write a patch using assembly text, continue with the +{ref}`assembler guide `. + +## x86/x86-64 + +On x86/x86-64, {sub-ref}`lief-asm-x86-instruction` also exposes an API to inspect and +rewrite the `LOCK` prefix of an instruction: + +- {sub-ref}`lief-assembly-x86-Instruction-has_lock_prefix` +- {sub-ref}`lief-assembly-x86-Instruction-is_lockable` +- {sub-ref}`lief-assembly-x86-Instruction-is_atomic` +- {sub-ref}`lief-assembly-x86-Instruction-lock` +- {sub-ref}`lief-assembly-x86-Instruction-unlock` + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/disassembler.py", "x86-lock", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/disassembler.cpp", "x86-lock") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/disassembler.rs", "x86-lock") }} +::: +:::: + +## Use Cases + +### DWARF Function + +In addition to the regular {sub-ref}`lief-disassemble` API, you can use +{sub-ref}`lief-dwarf-function-instructions` to disassemble a {ref}`DWARF ` +function. + +:::{warning} +{sub-ref}`lief-dwarf-function-instructions` only works if the DWARF debug info +is **embedded** in the binary. This is the default behavior for +{ref}`ELF ` binaries, but this is not the case for Mach-O +`.dSYM` files. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/disassembler.py", "dwarf-func", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/disassembler.cpp", "dwarf-func") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/disassembler.rs", "dwarf-func") }} +::: +:::: + +### Dyld Shared Cache + +A disassembly API is also provided for the {sub-ref}`lief-dsc-dyldsharedcache` object +via {sub-ref}`lief-dsc-dyldsharedcache-disassemble`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/disassembler.py", "dsc-disassemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/disassembler.cpp", "dsc-disassemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/disassembler.rs", "dsc-disassemble") }} +::: +:::: + +### COFF Support + +The {sub-ref}`lief-coff-Binary` interface does not inherit from the generic {sub-ref}`lief-abstract-binary`, +but it also exposes an API to disassemble code in COFF object files: {sub-ref}`lief-coff-binary-disassemble`. + +For more details, please check the {ref}`COFF Disassembler ` section + +### In-Memory Disassembler + +The disassembler is also available for analyzing code directly in the memory of +the running process. This functionality is exposed through the runtime API +{sub-ref}`lief-runtime-disassemble`, as detailed in the {ref}`Runtime Memory ` +documentation. + +## Technical Details + +The disassembler is based on LLVM's MC layer, which is known to be efficient and +accurate for disassembling code. This LLVM MC layer is already used by +other projects like [capstone](https://www.capstone-engine.org/) or, more +recently, [Nyxstone](https://github.com/emproof-com/nyxstone). + +Compared to Capstone, LIEF uses a mainstream LLVM version with limited +modifications to the MC layer. On the other hand, it does not expose a C API, +supports fewer architectures than Capstone, and does not expose a standalone API. + +:::{note} +The current LLVM version is {sub-ref}`lief-llvm-version`. +::: + +Unlike Nyxstone's disassembler, LIEF hides LLVM from the public API, +meaning that LLVM does not need to be installed on the system. +On the other hand, it does not expose a standalone API. + +The major difference between LIEF's disassembler and other projects is that +it **does not expose a standalone API** for disassembling arbitrary code. +The disassembler is bound to the object from which the API is +exposed ({sub-ref}`lief-abstract-binary`, {sub-ref}`lief-dwarf-function`, +{sub-ref}`lief-dsc-dyldsharedcache-disassemble`, etc.). + +## API + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` Rust API: {rust:module}`lief::assembly` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/aarch64.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/aarch64.md new file mode 100644 index 0000000..b4c8b52 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/aarch64.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` AArch64 + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.Instruction +``` + +## Opcodes + +See: `lief.assembly.aarch64.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.Operand + :top-classes: lief._lief.assembly.aarch64.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.operands.Immediate + :top-classes: lief._lief.assembly.aarch64.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.operands.Register + :top-classes: lief._lief.assembly.aarch64.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.operands.Memory + :top-classes: lief._lief.assembly.aarch64.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.aarch64.operands.PCRelative + :top-classes: lief._lief.assembly.aarch64.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.aarch64.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/arm.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/arm.md new file mode 100644 index 0000000..5f2e1c3 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/arm.md @@ -0,0 +1,17 @@ +# {fa}`solid fa-microchip` ARM + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.arm.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.arm.Instruction +``` + +## Opcodes + +See: `lief.assembly.arm.OPCODE` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/ebpf.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/ebpf.md new file mode 100644 index 0000000..fa57795 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/ebpf.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` eBPF + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.Instruction +``` + +## Opcodes + +See: `lief.assembly.ebpf.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.Operand + :top-classes: lief._lief.assembly.ebpf.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.operands.Immediate + :top-classes: lief._lief.assembly.ebpf.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.operands.Register + :top-classes: lief._lief.assembly.ebpf.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.operands.Memory + :top-classes: lief._lief.assembly.ebpf.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.ebpf.operands.PCRelative + :top-classes: lief._lief.assembly.ebpf.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.ebpf.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/mips.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/mips.md new file mode 100644 index 0000000..160c3b0 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/mips.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` Mips + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.Instruction +``` + +## Opcodes + +See: `lief.assembly.mips.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.Operand + :top-classes: lief._lief.assembly.mips.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.operands.Immediate + :top-classes: lief._lief.assembly.mips.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.operands.Register + :top-classes: lief._lief.assembly.mips.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.operands.Memory + :top-classes: lief._lief.assembly.mips.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.mips.operands.PCRelative + :top-classes: lief._lief.assembly.mips.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.mips.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/powerpc.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/powerpc.md new file mode 100644 index 0000000..d446cef --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/powerpc.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` PowerPC + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.Instruction +``` + +## Opcodes + +See: `lief.assembly.powerpc.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.Operand + :top-classes: lief._lief.assembly.powerpc.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.operands.Immediate + :top-classes: lief._lief.assembly.powerpc.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.operands.Register + :top-classes: lief._lief.assembly.powerpc.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.operands.Memory + :top-classes: lief._lief.assembly.powerpc.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.powerpc.operands.PCRelative + :top-classes: lief._lief.assembly.powerpc.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.powerpc.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/riscv.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/riscv.md new file mode 100644 index 0000000..720b1a1 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/riscv.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` RISC-V + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.Instruction +``` + +## Opcodes + +See: `lief.assembly.riscv.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.Operand + :top-classes: lief._lief.assembly.riscv.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.operands.Immediate + :top-classes: lief._lief.assembly.riscv.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.operands.Register + :top-classes: lief._lief.assembly.riscv.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.operands.Memory + :top-classes: lief._lief.assembly.riscv.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.riscv.operands.PCRelative + :top-classes: lief._lief.assembly.riscv.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.riscv.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/arch/x86.md b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/x86.md new file mode 100644 index 0000000..3115e74 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/arch/x86.md @@ -0,0 +1,77 @@ +# {fa}`solid fa-microchip` x86/x86-64 + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.Instruction +``` + +## Opcodes + +See: `lief.assembly.x86.OPCODE` + +## Operands + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.Operand + :top-classes: lief._lief.assembly.x86.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.Operand +``` + +### Immediate + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.operands.Immediate + :top-classes: lief._lief.assembly.x86.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.operands.Immediate +``` + +### Register + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.operands.Register + :top-classes: lief._lief.assembly.x86.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.operands.Register +``` + +### Memory + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.operands.Memory + :top-classes: lief._lief.assembly.x86.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.operands.Memory +``` + +### PCRelative + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.x86.operands.PCRelative + :top-classes: lief._lief.assembly.x86.Operand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.x86.operands.PCRelative +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/python/index.md b/vendor/lief/doc/sphinx/extended/disassembler/python/index.md new file mode 100644 index 0000000..fa695d8 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/python/index.md @@ -0,0 +1,35 @@ +# {fa}`brands fa-python` Python + +## Architectures + +```{eval-rst} +.. toctree:: + :caption:  Architectures + :maxdepth: 1 + + arch/x86 + arch/aarch64 + arch/arm + arch/ebpf + arch/riscv + arch/mips + arch/powerpc +``` + +## Engine + +```{eval-rst} +.. autoclass:: lief.assembly.Engine +``` + +## Instruction + +```{eval-rst} +.. lief-inheritance:: lief._lief.assembly.Instruction + :top-classes: lief._lief.assembly.Instruction + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.assembly.Instruction +``` diff --git a/vendor/lief/doc/sphinx/extended/disassembler/rust.md b/vendor/lief/doc/sphinx/extended/disassembler/rust.md new file mode 100644 index 0000000..cbe7181 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/disassembler/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::assembly` +::: diff --git a/vendor/lief/doc/sphinx/extended/dsc/cpp.md b/vendor/lief/doc/sphinx/extended/dsc/cpp.md new file mode 100644 index 0000000..86dcb33 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dsc/cpp.md @@ -0,0 +1,72 @@ +# {fa}`regular fa-file-code` C++ + +:::{note} +You can also find the Doxygen documentation here: [here](../../doxygen/) +::: + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::load(const std::string &path, const std::string &arch = "") +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::load(const std::vector &files) +``` + +## Cache Processing + +:::{warning} +If you aim at extracting several libraries from a dyld shared cache, it is +**highly** recommended to enable caching. Otherwise, performances can be +impacted. +::: + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::enable_cache() +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::enable_cache(const std::string &dir) + +``` + +## DyldSharedCache + +```{eval-rst} +.. doxygenclass:: LIEF::dsc::DyldSharedCache + +``` + +## Dylib + +```{eval-rst} +.. doxygenclass:: LIEF::dsc::Dylib + +``` + +## MappingInfo + +```{eval-rst} +.. doxygenclass:: LIEF::dsc::MappingInfo + +``` + +## SubCache + +```{eval-rst} +.. doxygenclass:: LIEF::dsc::SubCache + +``` + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::is_shared_cache(BinaryStream&) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::is_shared_cache(const std::vector< uint8_t > &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::dsc::is_shared_cache(const uint8_t *, size_t) +``` diff --git a/vendor/lief/doc/sphinx/extended/dsc/index.md b/vendor/lief/doc/sphinx/extended/dsc/index.md new file mode 100644 index 0000000..fac430e --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dsc/index.md @@ -0,0 +1,182 @@ +--- +description: Load Apple Dyld shared caches, inspect and extract libraries as Mach-O files, and configure extraction and caching with LIEF Extended. +--- + +(extended-dsc)= + +# {fa}`solid fa-diagram-predecessor` Dyld Shared Cache + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +LIEF Extended can inspect Apple's Dyld shared cache, enumerate its libraries, +and extract them as Mach-O binaries. + +## Load a cache and list its libraries + +One can load a shared cache using the {sub-ref}`lief-dsc-load` function: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dsc.py", "load", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dsc.cpp", "load", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dsc.rs", "load") }} +::: +:::: + +:::{note} +Pass a directory to {sub-ref}`lief-dsc-load` to load the whole cache, or an explicit +set of files to load a subset. Keep the main cache and its matching subcache files +together: an extraction may need data from more than one file. +::: + +From this {sub-ref}`lief-dsc-dyldsharedcache` object, we can inspect the embedded +{sub-ref}`lief-dsc-dylib` as follows: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dsc.py", "libraries") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dsc.cpp", "libraries") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dsc.rs", "libraries") }} +::: +:::: + +## Extract a library + +Find a {sub-ref}`lief-dsc-dylib`, then use {sub-ref}`lief-dsc-dylib-get` to extract a +{sub-ref}`lief-macho-binary` for analysis. Check both the library lookup and the +extraction result before using the Mach-O object: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dsc.py", "extract") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dsc.cpp", "extract") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dsc.rs", "extract") }} +::: +:::: + +Use {sub-ref}`lief-macho-binary-write` to save the extracted object to a file: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dsc.py", "write") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dsc.cpp", "write") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dsc.rs", "write") }} +::: +:::: + +:::{warning} +By default, LIEF retains Dyld shared cache optimizations. Review +{sub-ref}`lief-dsc-dylib-eopt` when the extracted library needs references and +other cache-specific structures recovered. Writing a Mach-O file alone does not +guarantee it can be loaded independently of the cache. +::: + +## {fa}`solid fa-stopwatch` Performance Considerations + +Dyld shared cache files are quite large, meaning they cannot be processed in +the same way as standard {sub-ref}`lief-macho-binary` or {sub-ref}`lief-elf-binary` binaries. + +The Dyld shared cache support in LIEF follows the principle: +*don't pay overhead for what you don't access*. This is the opposite of the +implementation of {sub-ref}`lief-pe-parse`, {sub-ref}`lief-macho-parse`, and {sub-ref}`lief-elf-parse`. + +:::{note} +These functions parse all format structures (with decent performance) +because: + +1. Most binary sizes are less than one gigabyte. +2. A complete representation is required for modifying binaries. +::: + +From a technical perspective, LIEF uses a {cpp:class}`LIEF::FileStream` to +access Dyld shared cache structures on demand. Thus, in-memory consumption +is limited to the size of the structures being accessed. The drawback of +using {cpp:class}`~LIEF::FileStream` is that because it uses file-based access, +it takes more time compared to a {cpp:class}`LIEF::VectorStream`. + +Additionally, LIEF's Dyld shared cache implementation **heavily** relies on +the iterator pattern to follow the principle: *don't pay overhead for what you don't access*. + +For instance, {sub-ref}`lief-dsc-dyldsharedcache-libraries` returns an **iterator** +over the {sub-ref}`lief-dsc-dylib`. Therefore, if you don't iterate, you don't pay for the +access and parsing of the {sub-ref}`lief-dsc-dylib` objects. + +Where possible, LIEF implements the random access iterator trait [^footnote-1] +so that we can programmatically do: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dsc.py", "random-access") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dsc.cpp", "random-access") }} +::: +:::: + +When extracting a {sub-ref}`lief-macho-binary` from a {sub-ref}`lief-dsc-dylib` object using +{sub-ref}`lief-dsc-dylib-get`, **the extraction can take a substantial amount of time**, +especially if certain deoptimizations are enabled (c.f. {sub-ref}`lief-dsc-dylib-eopt`). + +For instance, {sub-ref}`lief-dsc-dylib-eopt-fix_branches` may require iterating over the +Dyld shared cache's stub islands several times. To improve overall performance, +LIEF provides a cache-based optimization that can be enabled and configured with: + +- {sub-ref}`lief-dsc-enable_cache` +- {sub-ref}`lief-dsc-dyldsharedcache-enable_caching` + +:::{admonition} When should you turn caching on? +:class: warning + +You can **skip** LIEF's caching if: + +- You don't plan to extract libraries from the shared cache. +- You plan to extract only one library from the shared cache and **only once** +- You don't want to have LIEF cache artifacts on your system. + +For all other situations, you should turn on {sub-ref}`lief-dsc-enable_cache`. + +**By default, the cache mechanism is not enabled.** +::: + +[^footnote-1]: + +## {fa}`solid fa-book-open-reader` References + +- {github-ref}`arandomdev/DyldExtractor` +- {github-ref}`blacktop/ipsw` +- {github-ref}`apple-oss-distributions/dyld` +- + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` Rust API: {rust:module}`lief::dsc` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/dsc/python.md b/vendor/lief/doc/sphinx/extended/dsc/python.md new file mode 100644 index 0000000..c22ddef --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dsc/python.md @@ -0,0 +1,48 @@ +# {fa}`brands fa-python` Python + +```{eval-rst} +.. autofunction:: lief.dsc.load +``` + +## Cache Processing + +:::{warning} +If you aim at extracting several libraries from a dyld shared cache, it is +**highly** recommended to enable caching. Otherwise, performances can be +impacted. +::: + +```{eval-rst} +.. autofunction:: lief.dsc.enable_cache +``` + +## DyldSharedCache + +```{eval-rst} +.. autoclass:: lief.dsc.DyldSharedCache + +``` + +## Dylib + +```{eval-rst} +.. autoclass:: lief.dsc.Dylib +``` + +## MappingInfo + +```{eval-rst} +.. autoclass:: lief.dsc.MappingInfo +``` + +## SubCache + +```{eval-rst} +.. autoclass:: lief.dsc.SubCache +``` + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_shared_cache +``` diff --git a/vendor/lief/doc/sphinx/extended/dsc/rust.md b/vendor/lief/doc/sphinx/extended/dsc/rust.md new file mode 100644 index 0000000..398e9cc --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dsc/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::dsc` +::: diff --git a/vendor/lief/doc/sphinx/extended/dwarf/cpp.md b/vendor/lief/doc/sphinx/extended/dwarf/cpp.md new file mode 100644 index 0000000..8db9e58 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dwarf/cpp.md @@ -0,0 +1,420 @@ +# {fa}`regular fa-file-code` C++ + +:::{note} +You can also find the Doxygen documentation here: [here](../../doxygen/) +::: + +```{eval-rst} +.. doxygenfunction:: LIEF::dwarf::load + +``` + +## DebugInfo + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::DebugInfo +``` + +______________________________________________________________________ + +## CompilationUnit + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::CompilationUnit +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Function +``` + +______________________________________________________________________ + +## Parameter + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Parameter +``` + +______________________________________________________________________ + +## Formal Parameter + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::parameters::Formal +``` + +______________________________________________________________________ + +## Template Value Parameter + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::parameters::TemplateValue +``` + +______________________________________________________________________ + +## Template Type Parameter + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::parameters::TemplateType +``` + +______________________________________________________________________ + +## Scope + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Scope +``` + +______________________________________________________________________ + +## Variable + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Variable +``` + +______________________________________________________________________ + +## LexicalBlock + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::LexicalBlock +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Type +``` + +______________________________________________________________________ + +## Array + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Array +``` + +______________________________________________________________________ + +## Base + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Base +``` + +______________________________________________________________________ + +## ClassLike + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::ClassLike +``` + +______________________________________________________________________ + +## Structure + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Structure +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Class +``` + +______________________________________________________________________ + +## Union + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Union +``` + +______________________________________________________________________ + +## Packed + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Packed +``` + +______________________________________________________________________ + +## Const + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Const +``` + +______________________________________________________________________ + +## Pointer + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Pointer +``` + +______________________________________________________________________ + +## Typedef + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Typedef +``` + +______________________________________________________________________ + +## Atomic + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Atomic +``` + +______________________________________________________________________ + +## Coarray + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Coarray +``` + +______________________________________________________________________ + +## Dynamic + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Dynamic +``` + +______________________________________________________________________ + +## Enum + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Enum +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::File +``` + +______________________________________________________________________ + +## Immutable + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Immutable +``` + +______________________________________________________________________ + +## Interface + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Interface +``` + +______________________________________________________________________ + +## PointerToMember + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::PointerToMember +``` + +______________________________________________________________________ + +## RValueReference + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::RValueReference +``` + +______________________________________________________________________ + +## Reference + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Reference +``` + +______________________________________________________________________ + +## Restrict + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Restrict +``` + +______________________________________________________________________ + +## SetTy + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::SetTy +``` + +______________________________________________________________________ + +## Shared + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Shared +``` + +______________________________________________________________________ + +## StringTy + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::StringTy +``` + +______________________________________________________________________ + +## Subroutine + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Subroutine +``` + +______________________________________________________________________ + +## TemplateAlias + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::TemplateAlias +``` + +______________________________________________________________________ + +## Thrown + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Thrown +``` + +______________________________________________________________________ + +## Volatile + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::types::Volatile + +``` + +______________________________________________________________________ + +## Editor + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::Editor +``` + +______________________________________________________________________ + +## Editor - CompilationUnit + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::CompilationUnit +``` + +______________________________________________________________________ + +## Editor - Function + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::Function +``` + +______________________________________________________________________ + +## Editor - Variable + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::Variable + +``` + +______________________________________________________________________ + +## Editor - Type + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::Type +``` + +______________________________________________________________________ + +## Editor - PointerType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::PointerType +``` + +______________________________________________________________________ + +## Editor - EnumType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::EnumType +``` + +______________________________________________________________________ + +## Editor - BaseType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::BaseType +``` + +______________________________________________________________________ + +## Editor - ArrayType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::ArrayType +``` + +______________________________________________________________________ + +## Editor - FunctionType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::FunctionType + +``` + +______________________________________________________________________ + +## Editor - `TypeDef` + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::TypeDef + +``` + +______________________________________________________________________ + +## Editor - StructType + +```{eval-rst} +.. doxygenclass:: LIEF::dwarf::editor::StructType +``` diff --git a/vendor/lief/doc/sphinx/extended/dwarf/index.md b/vendor/lief/doc/sphinx/extended/dwarf/index.md new file mode 100644 index 0000000..6441d96 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dwarf/index.md @@ -0,0 +1,215 @@ +--- +description: Read DWARF functions, types, and variables, attach external debug files, generate declarations, and create new DWARF files with LIEF Extended. +--- + +(extended-dwarf)= + +# {fa}`solid fa-bars-staggered` DWARF + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +LIEF Extended can read DWARF functions, variables, types, and source locations, +generate C/C++ declarations, and create new debug files. + +DWARF debug information can be embedded in a binary or stored in a separate file. +To inspect compiler-generated DWARF, build with debug information and preserve +it when stripping the binary. Debug files can also be generated from analysis +results with the {ref}`DWARF editor `. For an overview of +loading and associating debug files, see {ref}`debug-info`. + +## Load and inspect DWARF + +When DWARF debug information is embedded within the binary, +you can access it using the {sub-ref}`lief-dwarf-binary-debug-info` attribute. +This attribute returns a {sub-ref}`lief-dwarf-debug-info` object: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "embedded", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "embedded") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "embedded") }} +::: +:::: + +Additionally, the {sub-ref}`lief-dwarf-load` function can be used to load a +DWARF file, whether it is embedded or standalone: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "load", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "load") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "load") }} +::: +:::: + +For a macOS `.dSYM` bundle, pass the path to the DWARF object inside +`Contents/Resources/DWARF/`. Check the loader's return value before accessing +compilation units or searching for a function or type. + +Once loaded, you can use the {sub-ref}`lief-dwarf-debug-info` API to interact with the +debug information: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "iterate") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "iterate") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "iterate") }} +::: +:::: + +(extended-dwarf-load-ext)= + +## Attach an external debug file + +In the case of an external DWARF file, you can bind this debug file to +a {sub-ref}`lief-abstract-binary` using the {sub-ref}`lief-abstract-binary-load_debug_info` +function. + +Here's an example: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "load-external") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "load-external") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "load-external") }} +::: +:::: + +Use a debug file produced by the same build as the binary. Attaching it updates +LIEF's analysis object. It does not insert DWARF sections into the executable. +The {sub-ref}`lief-disassemble` function can then resolve functions defined by +that debug file while reading their machine code from the binary: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "disassemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "disassemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "disassemble") }} +::: +:::: + +Additionally, you may also want to explore the +{ref}`BinaryNinja ` and +{ref}`Ghidra ` DWARF export plugins, which generate +debug information based on the analysis performed by these frameworks. + +(extended-dwarf-to-decl)= + +## Generating C/C++ Definitions + +DWARF functions, variables, types, and compilation units can be rendered as +C/C++ declarations using: + +- {sub-ref}`lief-dwarf-function-to_decl` +- {sub-ref}`lief-dwarf-variable-to_decl` +- {sub-ref}`lief-dwarf-type-to_decl` +- {sub-ref}`lief-dwarf-cu-to_decl` + +The generated output can be configured with a {sub-ref}`lief-declopt` structure (e.g. to +prefer C++ syntax or change the indentation): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "to-decl") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "to-decl") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "to-decl") }} +::: +:::: + +(extended-dwarf-editor)= + +## DWARF Editor + +:::{admonition} Editing Existing DWARF +:class: warning + +LIEF does not currently support modifying an **existing** DWARF file. +::: + +LIEF provides a comprehensive high-level API for programmatically creating +DWARF files. This works by using the {sub-ref}`lief-dwarf-editor` interface, which can be +instantiated using {sub-ref}`lief-dwarf-editor-from_binary`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "editor-from-binary") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "editor-from-binary") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "editor-from-binary") }} +::: +:::: + +Given this {sub-ref}`lief-dwarf-editor`, you can create one or more +{sub-ref}`lief-dwarf-editor-CompilationUnit` entries, which own various +{sub-ref}`lief-dwarf-editor-Function`, {sub-ref}`lief-dwarf-editor-Variable`, and +{sub-ref}`lief-dwarf-editor-Type` objects. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/dwarf.py", "editor-create") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/dwarf.cpp", "editor-create") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/dwarf.rs", "editor-create") }} +::: +:::: + +:::{admonition} BinaryNinja & Ghidra +:class: note + +This feature is provided as a plugin for {ref}`BinaryNinja ` +and {ref}`Ghidra `. +::: + +______________________________________________________________________ + +## API + +You can find the documentation of the API for the different languages here: + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` Rust API: {rust:module}`lief::dwarf` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/dwarf/python.md b/vendor/lief/doc/sphinx/extended/dwarf/python.md new file mode 100644 index 0000000..d312394 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dwarf/python.md @@ -0,0 +1,653 @@ +# {fa}`brands fa-python` Python + +```{eval-rst} +.. autofunction:: lief.dwarf.load +``` + +## DebugInfo + +```{eval-rst} +.. autoclass:: lief.dwarf.DebugInfo +``` + +______________________________________________________________________ + +## CompilationUnit + +```{eval-rst} +.. autoclass:: lief.dwarf.CompilationUnit +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. autoclass:: lief.dwarf.Function +``` + +______________________________________________________________________ + +## Parameter + +```{eval-rst} +.. autoclass:: lief.dwarf.Parameter +``` + +______________________________________________________________________ + +## Formal Parameter + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.parameters.Formal + :top-classes: lief._lief.dwarf.Parameter + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.parameters.Formal +``` + +______________________________________________________________________ + +## Template Value Parameter + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.parameters.TemplateValue + :top-classes: lief._lief.dwarf.Parameter + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.parameters.TemplateValue +``` + +______________________________________________________________________ + +## Template Type Parameter + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.parameters.TemplateType + :top-classes: lief._lief.dwarf.Parameter + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.parameters.TemplateType +``` + +______________________________________________________________________ + +## Scope + +```{eval-rst} +.. autoclass:: lief.dwarf.Scope +``` + +______________________________________________________________________ + +## Variable + +```{eval-rst} +.. autoclass:: lief.dwarf.Variable +``` + +______________________________________________________________________ + +## LexicalBlock + +```{eval-rst} +.. autoclass:: lief.dwarf.LexicalBlock +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.Type + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.Type +``` + +______________________________________________________________________ + +## Array + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Array + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Array +``` + +______________________________________________________________________ + +## Base + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Base + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Base +``` + +______________________________________________________________________ + +## ClassLike + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.ClassLike + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.ClassLike +``` + +______________________________________________________________________ + +## Structure + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Structure + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Structure +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Class + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Class +``` + +______________________________________________________________________ + +## Union + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Union + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Union +``` + +______________________________________________________________________ + +## Packed + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Packed + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Packed +``` + +______________________________________________________________________ + +## Const + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Const + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Const +``` + +______________________________________________________________________ + +## Pointer + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Pointer + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Pointer + +``` + +______________________________________________________________________ + +## Typedef + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Typedef + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Typedef +``` + +______________________________________________________________________ + +## Atomic + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Atomic + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Atomic +``` + +______________________________________________________________________ + +## Coarray + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Coarray + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Coarray +``` + +______________________________________________________________________ + +## Dynamic + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Dynamic + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Dynamic +``` + +______________________________________________________________________ + +## Enum + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Enum + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Enum +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.File + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.File +``` + +______________________________________________________________________ + +## Immutable + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Immutable + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Immutable +``` + +______________________________________________________________________ + +## Interface + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Interface + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Interface +``` + +______________________________________________________________________ + +## PointerToMember + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.PointerToMember + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.PointerToMember +``` + +______________________________________________________________________ + +## RValueReference + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.RValueReference + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.RValueReference +``` + +______________________________________________________________________ + +## Reference + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Reference + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Reference +``` + +______________________________________________________________________ + +## Restrict + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Restrict + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Restrict +``` + +______________________________________________________________________ + +## SetTy + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.SetTy + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.SetTy +``` + +______________________________________________________________________ + +## Shared + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Shared + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Shared +``` + +______________________________________________________________________ + +## StringTy + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.StringTy + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.StringTy +``` + +______________________________________________________________________ + +## Subroutine + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Subroutine + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Subroutine +``` + +______________________________________________________________________ + +## TemplateAlias + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.TemplateAlias + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.TemplateAlias + +``` + +______________________________________________________________________ + +## Thrown + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Thrown + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Thrown +``` + +______________________________________________________________________ + +## Volatile + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.types.Volatile + :top-classes: lief._lief.dwarf.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.types.Volatile +``` + +______________________________________________________________________ + +## Editor + +```{eval-rst} +.. autoclass:: lief.dwarf.Editor +``` + +______________________________________________________________________ + +## Editor - CompilationUnit + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.CompilationUnit +``` + +______________________________________________________________________ + +## Editor - Function + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.Function +``` + +______________________________________________________________________ + +## Editor - Variable + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.Variable +``` + +______________________________________________________________________ + +## Editor - Type + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.Type + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.Type +``` + +______________________________________________________________________ + +## Editor - PointerType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.PointerType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.PointerType +``` + +______________________________________________________________________ + +## Editor - EnumType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.EnumType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.EnumType +``` + +______________________________________________________________________ + +## Editor - BaseType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.BaseType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.BaseType +``` + +______________________________________________________________________ + +## Editor - ArrayType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.ArrayType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.ArrayType +``` + +______________________________________________________________________ + +## Editor - FunctionType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.FunctionType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.FunctionType +``` + +______________________________________________________________________ + +## Editor - `TypeDef` + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.TypeDef + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.TypeDef +``` + +______________________________________________________________________ + +## Editor - StructType + +```{eval-rst} +.. lief-inheritance:: lief._lief.dwarf.editor.StructType + :top-classes: lief._lief.dwarf.editor.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.dwarf.editor.StructType +``` diff --git a/vendor/lief/doc/sphinx/extended/dwarf/rust.md b/vendor/lief/doc/sphinx/extended/dwarf/rust.md new file mode 100644 index 0000000..ff93e36 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/dwarf/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::dwarf` +::: diff --git a/vendor/lief/doc/sphinx/extended/intro.md b/vendor/lief/doc/sphinx/extended/intro.md new file mode 100644 index 0000000..1ecdaed --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/intro.md @@ -0,0 +1,201 @@ +--- +description: LIEF Extended features, install Python wheels or C++ and Rust SDKs, verify your build, and find guides for debug information, assembly, Apple metadata, and other extended features. +--- + +(extended-intro)= + +# {fa}`cubes` What is LIEF Extended? + +## Introduction + +*LIEF Extended* is an enhanced version of LIEF, providing additional features +such as support for the Dyld shared cache, Objective-C metadata, PDB, and DWARF. + +While the main version of LIEF focuses on providing support for +ELF, PE, and Mach-O, LIEF Extended aims to provide functionality that +was not originally intended for integration into the core LIEF project. + +You can find the differences between the two versions in this table: + +```{eval-rst} ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| Module | Regular Version | Extended Version | Note | ++=============================================+===================+===================+====================================================+ +| :ref:`ELF ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`PE ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`Mach-O ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`COFF ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`DEX ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`OAT ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`VDEX ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`ART ` | :fa-check:`check` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`Runtime ` | :fa-check:`check` | :fa-check:`check` | Only enabled in LIEF extended wheels | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`PDB ` | :xmark:`mark` | :fa-check:`check` | Support based on LLVM :ref:`[1] ` | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`DWARF ` | :xmark:`mark` | :fa-check:`check` | Support based on LLVM :ref:`[1] ` | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`ObjC ` | :xmark:`mark` | :fa-check:`check` | Support based on :github-ref:`romainthomas/iCDump` | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`Dyld Shared Cache ` | :xmark:`mark` | :fa-check:`check` | | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`Disassembler ` | :xmark:`mark` | :fa-check:`check` | Support based on LLVM :ref:`[1] ` | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +| :ref:`Assembler ` | :xmark:`mark` | :fa-check:`check` | Support based on LLVM :ref:`[1] ` | ++---------------------------------------------+-------------------+-------------------+----------------------------------------------------+ +``` + +```{raw} html +
+
+

Get Access

+

To access the extended version, you must oauth-login with GitHub here:

+ LIEF Extended +
+
+
+``` + +To access the extended version, you must **oauth-login** with **GitHub** here: {sub-ref}`lief-extended-url`. + +Once logged in, you can download the package of your choice +(e.g., LIEF Extended - Python 3.10 for macOS arm64). + +:::{admonition} Email +:class: warning + +If you don't receive the download email, you can download the package directly +from your **History** section. +::: + +## Versioning + +LIEF Extended uses a slightly different versioning scheme than regular LIEF packages. + +First, **every extended package** is based on the current `main` branch +of LIEF. If you need an (extended) build for a specific commit or tag, +please contact {sub-ref}`lief-extended-email`. + +In Python, you can check the commit of LIEF being used in the extended version +with: + +```bash +# Make sure it's the extended version +$ python -c "import lief;print(lief.__extended__)" + +# Print LIEF's main commit +$ python -c "import lief;print(lief.__LIEF_MAIN_COMMIT__)" +``` + +With the C++/Rust SDK, you can call {sub-ref}`lief-extended-version-info` to +get details about the current version. + +Additional features exposed by LIEF Extended are not always represented in +a public commit while still being git-versioned. An incremental build number is +used to represent internal changes not associated with a public commit. + +For example, version `0.16.0.2380` includes 10 more commits than +version `0.16.0.2370`. + +## Python Wheels + +Python packages are delivered as a wheel for the required platform/version +(e.g., `lief_extended-0.16.0.post2370-cp312-cp312-win_amd64.whl`). + +You can install this wheel using pip in one of the following ways: + +```console +$ venv\Scripts\python.exe -m pip install C:\Users\tmp\lief_extended-0.16.0.post2370-cp312-cp312-win_amd64.whl +``` + +Or + +```console +$ venv\Scripts\python.exe -m pip install --find-links C:\Users\tmp\ lief_extended +``` + +You can verify that LIEF Extended is correctly installed with: + +```console +$ python -c "import lief;print(lief.__extended__)" +True +``` + +## C++ SDK + +The C++ SDK is delivered as a `.zip/.tar.gz` archive containing: + +- A compiled shared library (`libLIEF.so`, `LIEF.dll`, `libLIEF.dylib`) +- Header files +- CMake helper files + +Compared to the regular version, this SDK **does not** ship a static version of +LIEF, and the shared library is compiled with all extended features. + +Here is the layout for the macOS arm64 SDK, for example: + +```text +LIEF-extended-sdk-0.16.0.2378-Darwin-arm64/ + lib/libLIEF.dylib + lib/cmake/LIEF/lief-extended-config-version.cmake + include/[...] +``` + +## Rust SDK + +The Rust SDK is also delivered as a `.zip/.tar.gz` archive containing all the +files needed for use with the `LIEF_RUST_PRECOMPILED` environment variable, +as described in the {ref}`Rust ` section. + +Once the archive is extracted, you just have to set the `LIEF_RUST_PRECOMPILED` +environment variable to the extracted path: + +```console +$ tar xzvf LIEF-extended-rust-0.16.0.2378-Linux-x86_64.tar.gz + LIEF-extended-rust-0.16.0.2378-Linux-x86_64/lib/ + LIEF-extended-rust-0.16.0.2378-Linux-x86_64/lib/libLIEF.so + LIEF-extended-rust-0.16.0.2378-Linux-x86_64/lib/liblief-sys.a + +$ export LIEF_RUST_PRECOMPILED=$(pwd)/LIEF-extended-rust-0.16.0.2378-Linux-x86_64 +``` + +You can then use all the extended features in Rust: + +```console +$ cargo build my-lief-extended-project +``` + +(extended-llvm)= + +## LIEF Extended & LLVM + +LIEF Extended relies on LLVM for certain features, such as the +{ref}`disassembler ` and +{ref}`DWARF `/{ref}`PDB ` support. + +The LLVM version used by LIEF is based on the upstream version and integrated +into LIEF Extended so that users do not have to handle LLVM compilation or +integration. + +:::{note} +LIEF is currently using LLVM {sub-ref}`lief-llvm-version`. +::: + +Whenever possible and appropriate, bug fixes and enhancements have been +submitted as PRs to the LLVM project: + +- {llvm-pr}`119057` +- {llvm-pr}`119056` +- {llvm-pr}`116480` +- {llvm-pr}`116479` +- {llvm-pr}`97954` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/objc/cpp.md b/vendor/lief/doc/sphinx/extended/objc/cpp.md new file mode 100644 index 0000000..16db037 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/objc/cpp.md @@ -0,0 +1,67 @@ +# C++ + +:::{note} +You can also find the Doxygen documentation here: [here](../../doxygen/) +::: + +## Metadata + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Metadata +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Class +``` + +______________________________________________________________________ + +## Category + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Category +``` + +______________________________________________________________________ + +## Protocol + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Protocol +``` + +______________________________________________________________________ + +## Instance Variable (IVar) + +```{eval-rst} +.. doxygenclass:: LIEF::objc::IVar +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Method +``` + +______________________________________________________________________ + +## Property + +```{eval-rst} +.. doxygenclass:: LIEF::objc::Property +``` + +______________________________________________________________________ + +## DeclOpt + +```{eval-rst} +.. doxygenstruct:: LIEF::objc::DeclOpt +``` diff --git a/vendor/lief/doc/sphinx/extended/objc/index.md b/vendor/lief/doc/sphinx/extended/objc/index.md new file mode 100644 index 0000000..dcbac67 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/objc/index.md @@ -0,0 +1,150 @@ +--- +description: Inspect Objective-C classes, methods, properties, and protocols in Mach-O files and generate header-like declarations with LIEF Extended. +--- + +(extended-objc)= + +# {fa}`brands fa-apple` Objective-C + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 2 + + cpp + python + rust +``` + +## Introduction + +LIEF Extended reads Objective-C classes, methods, properties, and protocols from +Mach-O metadata. It can also generate header-like declarations. + +This information comes from Objective-C runtime metadata in the file, so it can +be present even when source-level debug information is unavailable. + +## Inspect metadata + +If a Mach-O binary embeds Objective-C metadata, it can be accessed through +{sub-ref}`lief-macho-binary-objc-metadata`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/objc.py", "check") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/objc.cpp", "check") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/objc.rs", "check") }} +::: +:::: + +When metadata is present, use {sub-ref}`lief-objc-metadata` to inspect it. +In particular, the {sub-ref}`lief-objc-metadata-to_decl` function can be used to generate +a header-like output of all the Objective-C metadata found in the binary. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/objc.py", "inspect") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/objc.cpp", "inspect") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/objc.rs", "inspect") }} +::: +:::: + +## Class Dump + +Generate header-like declarations to review the classes and protocols found in +the binary. The output describes the recorded metadata, including method +signatures. It does not recover method implementations or the original headers. + +```{image} ../../_static/objc-class-dump.webp +:alt: Objective-C class dump based on LIEF & LLVM +``` + +LIEF provides a way to generate this header-like information at various levels: + +- {sub-ref}`lief-objc-metadata-to_decl_opt` +- {sub-ref}`lief-objc-class-to_decl_opt` +- {sub-ref}`lief-objc-proto-to_decl_opt` + +Technically, this output is created by generating a Clang AST and applying +the LLVM printer visitor to it. + +::::{tabs} +:::{tab} {fa}`brands fa-rust` Code +{{ literalinclude("../../../code/rust/src/objc.rs", "classdump") }} +::: +:::{tab} {fa}`solid fa-terminal` Result +```{code-block} objc +@interface APMEventFilter { + bool _sessionScoped; + bool _dynamic; + bool _sequence; + int _audienceID; + int _filterID; + NSString * _eventName; + NSData * _data; +} +// Address: 0x0101859ee0 +- (NSObject *)initWithAudienceID:(APMEventFilter *)self filterID:(SEL)id eventName:(int)arg2 data:(int)arg3 sessionScoped:(NSObject *)arg4 dynamic:(NSObject *)arg5 sequence:(bool)arg6 :(bool)arg7 :(bool)arg8; +// Address: 0x0101682590 +- (int)audienceID:(APMEventFilter *)self :(SEL)id; +// Address: 0x01017b6d98 +- (int)filterID:(APMEventFilter *)self :(SEL)id; +// Address: 0x01018a4a6c +- (bool)isSessionScoped:(APMEventFilter *)self :(SEL)id; +// Address: 0x01017630d4 +- (bool)isDynamic:(APMEventFilter *)self :(SEL)id; +// Address: 0x01016adbb4 +- (bool)isSequence:(APMEventFilter *)self :(SEL)id; +// Address: 0x010187a5f8 +- (NSObject *)eventName:(APMEventFilter *)self :(SEL)id; +// Address: 0x0101581bfc +- (NSObject *)data:(APMEventFilter *)self :(SEL)id; +// Address: 0x01018e1f3c +- (void).cxx_destruct:(APMEventFilter *)self :(SEL)id; +@property void eventName; +@property void data; +@property void audienceID; +@property void filterID; +@property void sessionScoped; +@property void dynamic; +@property void sequence; +@property void hash; +@property void superclass; +@property void description; +@property void debugDescription; +@end +``` +::: +:::: + +The {sub-ref}`lief-objc-declopt` can be used to customize the generated output. For +example, we can remove the commented addresses associated with Objective-C +methods using this option: + +{{ literalinclude("../../../code/python/objc.py", "no-address") }} + +## {fa}`solid fa-book-open-reader` References + +- {github-ref}`romainthomas/iCDump` +- {github-ref}`nygard/class-dump` +- + +## API + +You can find the documentation of the API for the different languages here: + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` Rust API: {rust:module}`lief::objc` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/objc/python.md b/vendor/lief/doc/sphinx/extended/objc/python.md new file mode 100644 index 0000000..cc7a56d --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/objc/python.md @@ -0,0 +1,63 @@ +# Python + +## Metadata + +```{eval-rst} +.. autoclass:: lief.objc.Metadata +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. autoclass:: lief.objc.Class +``` + +______________________________________________________________________ + +## Category + +```{eval-rst} +.. autoclass:: lief.objc.Category +``` + +______________________________________________________________________ + +## Protocol + +```{eval-rst} +.. autoclass:: lief.objc.Protocol +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. autoclass:: lief.objc.Method +``` + +______________________________________________________________________ + +## IVar + +```{eval-rst} +.. autoclass:: lief.objc.IVar +``` + +______________________________________________________________________ + +## Property + +```{eval-rst} +.. autoclass:: lief.objc.Property +``` + +______________________________________________________________________ + +## DeclOpt + +```{eval-rst} +.. autoclass:: lief.objc.DeclOpt +``` diff --git a/vendor/lief/doc/sphinx/extended/objc/rust.md b/vendor/lief/doc/sphinx/extended/objc/rust.md new file mode 100644 index 0000000..a75799e --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/objc/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::objc` +::: diff --git a/vendor/lief/doc/sphinx/extended/pdb/cpp.md b/vendor/lief/doc/sphinx/extended/pdb/cpp.md new file mode 100644 index 0000000..2b8da19 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/pdb/cpp.md @@ -0,0 +1,175 @@ +# C++ + +:::{note} +You can also find the Doxygen documentation here: [here](../../doxygen/) +::: + +```{eval-rst} +.. doxygenfunction:: LIEF::pdb::load + +``` + +## DebugInfo + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::DebugInfo +``` + +______________________________________________________________________ + +## PublicSymbol + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::PublicSymbol +``` + +______________________________________________________________________ + +## CompilationUnit + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::CompilationUnit +``` + +______________________________________________________________________ + +## BuildMetadata + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::BuildMetadata +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::Function +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::Type +``` + +______________________________________________________________________ + +## Array + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Array +``` + +______________________________________________________________________ + +## Attribute (type) + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Attribute +``` + +______________________________________________________________________ + +## BitField + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::BitField +``` + +______________________________________________________________________ + +## ClassLike + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::ClassLike +``` + +______________________________________________________________________ + +## Structure + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Structure +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Class +``` + +______________________________________________________________________ + +## Interface + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Interface +``` + +______________________________________________________________________ + +## Enum + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Enum +``` + +______________________________________________________________________ + +## Function (type) + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Function +``` + +______________________________________________________________________ + +## Method (type) + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Method +``` + +______________________________________________________________________ + +## Modifier + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Modifier +``` + +______________________________________________________________________ + +## Pointer + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Pointer +``` + +______________________________________________________________________ + +## Simple + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Simple +``` + +______________________________________________________________________ + +## Union + +```{eval-rst} +.. doxygenclass:: LIEF::pdb::types::Union + +``` + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::pdb::is_pdb(const std::string&) +``` diff --git a/vendor/lief/doc/sphinx/extended/pdb/index.md b/vendor/lief/doc/sphinx/extended/pdb/index.md new file mode 100644 index 0000000..0faec86 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/pdb/index.md @@ -0,0 +1,137 @@ +--- +description: Locate and load PDB debug information, associate it with a PE binary, inspect symbols and types, and generate C++ declarations with LIEF Extended. +--- + +(extended-pdb)= + +# {fa}`brands fa-windows` PDB + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +Unlike DWARF debug information, PDB debug information is always stored +externally from the original binary. Nevertheless, the original binary keeps +the path of the PDB file in the {sub-ref}`lief-pe-codeviewpdb-filename` attribute. + +Based on this fact, {sub-ref}`lief-pdb-binary-debug-info` tries to instantiate a +{sub-ref}`lief-pdb-debug-info` object using this file path. If it fails, it returns +`nullptr` or `None`. + +You can also instantiate a {sub-ref}`lief-pdb-debug-info` object using {sub-ref}`lief-pdb-load`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pdb.py", "load") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pdb.cpp", "load") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pdb.rs", "load") }} +::: +:::: + +At this point, the PDB instance ({sub-ref}`lief-pdb-debug-info`) can be used to explore +the PDB debug information: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pdb.py", "explore") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pdb.cpp", "explore") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pdb.rs", "explore") }} +::: +:::: + +(extended-pdb-load-ext)= + +## Attach a PDB to a binary + +You can also use the {sub-ref}`lief-abstract-binary-load_debug_info` function to bind +a PDB file to an existing {sub-ref}`lief-abstract-binary`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pdb.py", "load-ext") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pdb.cpp", "load-ext") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pdb.rs", "load-ext") }} +::: +:::: + +Note that {sub-ref}`lief-abstract-binary-load_debug_info` can also attach an external +DWARF file to a PE binary, even though this is not a typical use case. +For instance, the {ref}`BinaryNinja ` and +{ref}`Ghidra ` DWARF export plugins can generate +a DWARF file for a PE binary based on analysis performed by these frameworks. + +This external loading API is useful for adding debug information that might not +already be present in the binary. For instance, the {sub-ref}`lief-disassemble` function +can leverage this additional debug information to disassemble functions +defined in the debug file previously loaded: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pdb.py", "disassemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pdb.cpp", "disassemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pdb.rs", "disassemble") }} +::: +:::: + +(extended-pdb-to-decl)= + +## Generating C/C++ Definitions + +PDB types, functions and compilation units can be turned into C/C++ definitions +using the `to_decl()` function: + +- {sub-ref}`lief-pdb-type-to_decl` +- {sub-ref}`lief-pdb-function-to_decl` +- {sub-ref}`lief-pdb-cu-to_decl` + +The generated output can be configured with a {sub-ref}`lief-declopt` structure: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pdb.py", "to-decl") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pdb.cpp", "to-decl") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pdb.rs", "to-decl") }} +::: +:::: + +______________________________________________________________________ + +## API + +You can find the documentation of the API for the different languages here: + +{fa}`brands fa-python` {doc}`Python API ` + +{fa}`regular fa-file-code` {doc}`C++ API ` + +{fa}`brands fa-rust` Rust API: {rust:module}`lief::pdb` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/extended/pdb/python.md b/vendor/lief/doc/sphinx/extended/pdb/python.md new file mode 100644 index 0000000..609fd32 --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/pdb/python.md @@ -0,0 +1,261 @@ +# Python + +```{eval-rst} +.. autofunction:: lief.pdb.load +``` + +## DebugInfo + +```{eval-rst} +.. autoclass:: lief.pdb.DebugInfo +``` + +______________________________________________________________________ + +## CompilationUnit + +```{eval-rst} +.. autoclass:: lief.pdb.CompilationUnit +``` + +______________________________________________________________________ + +## BuildMetadata + +```{eval-rst} +.. autoclass:: lief.pdb.BuildMetadata +``` + +______________________________________________________________________ + +## PublicSymbol + +```{eval-rst} +.. autoclass:: lief.pdb.PublicSymbol +``` + +______________________________________________________________________ + +## Function + +```{eval-rst} +.. autoclass:: lief.pdb.Function +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.Type + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.Type +``` + +______________________________________________________________________ + +## Array + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Array + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Array +``` + +______________________________________________________________________ + +## Attribute (type) + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Attribute + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Attribute +``` + +______________________________________________________________________ + +## BitField + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.BitField + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.BitField +``` + +______________________________________________________________________ + +## ClassLike + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.ClassLike + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.ClassLike +``` + +______________________________________________________________________ + +## Structure + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Structure + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Structure +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Class + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Class +``` + +______________________________________________________________________ + +## Interface + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Interface + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Interface +``` + +______________________________________________________________________ + +## Enum + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Enum + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Enum +``` + +______________________________________________________________________ + +## Function (type) + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Function + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Function +``` + +______________________________________________________________________ + +## Method (type) + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Method + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Method +``` + +______________________________________________________________________ + +## Modifier + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Modifier + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Modifier +``` + +______________________________________________________________________ + +## Pointer + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Pointer + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Pointer +``` + +______________________________________________________________________ + +## Simple + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Simple + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Simple +``` + +______________________________________________________________________ + +## Union + +```{eval-rst} +.. lief-inheritance:: lief._lief.pdb.types.Union + :top-classes: lief._lief.pdb.Type + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.pdb.types.Union +``` + +______________________________________________________________________ + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_pdb +``` diff --git a/vendor/lief/doc/sphinx/extended/pdb/rust.md b/vendor/lief/doc/sphinx/extended/pdb/rust.md new file mode 100644 index 0000000..b47a24a --- /dev/null +++ b/vendor/lief/doc/sphinx/extended/pdb/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::pdb` +::: diff --git a/vendor/lief/doc/sphinx/formats/android/art/cpp.md b/vendor/lief/doc/sphinx/formats/android/art/cpp.md new file mode 100644 index 0000000..7a122f0 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/art/cpp.md @@ -0,0 +1,56 @@ +# {fa}`regular fa-file-code` C++ + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::ART::is_art(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ART::is_art(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ART::version(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ART::version(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ART::android_version + :project: lief +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::ART::Parser + :project: lief +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. doxygenclass:: LIEF::ART::File + :project: lief +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::ART::Header + :project: lief + +``` diff --git a/vendor/lief/doc/sphinx/formats/android/art/index.md b/vendor/lief/doc/sphinx/formats/android/art/index.md new file mode 100644 index 0000000..f333653 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/art/index.md @@ -0,0 +1,16 @@ +(format-art)= + +# {fa}`brands fa-android` ART + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python +``` + +LIEF provides **basic** support for Android's ART files. For details about +this format, please refer to the {ref}`Android Formats ` +tutorial. diff --git a/vendor/lief/doc/sphinx/formats/android/art/python.md b/vendor/lief/doc/sphinx/formats/android/art/python.md new file mode 100644 index 0000000..72f0559 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/art/python.md @@ -0,0 +1,41 @@ +# {fa}`brands fa-python` Python + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_art +``` + +```{eval-rst} +.. autofunction:: lief.ART.version +``` + +```{eval-rst} +.. autofunction:: lief.ART.android_version +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. autofunction:: lief.ART.parse +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. autoclass:: lief.ART.File +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.ART.Header + + +``` diff --git a/vendor/lief/doc/sphinx/formats/android/dex/cpp.md b/vendor/lief/doc/sphinx/formats/android/dex/cpp.md new file mode 100644 index 0000000..2670e3a --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/dex/cpp.md @@ -0,0 +1,131 @@ +# {fa}`regular fa-file-code` C++ + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::DEX::is_dex(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::DEX::is_dex(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::DEX::version(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::DEX::version(const std::vector&) + :project: lief + +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Parser + :project: lief +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::File + :project: lief +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Header + :project: lief +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Method + :project: lief +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Class + :project: lief +``` + +______________________________________________________________________ + +## Field + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Field + :project: lief +``` + +______________________________________________________________________ + +## Code Info + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::CodeInfo + :project: lief +``` + +______________________________________________________________________ + +## Prototype + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Prototype + :project: lief +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::Type + :project: lief +``` + +______________________________________________________________________ + +## MapList + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::MapList + :project: lief + +``` + +______________________________________________________________________ + +## MapItem + +```{eval-rst} +.. doxygenclass:: LIEF::DEX::MapItem + :project: lief + + + + + + + +``` diff --git a/vendor/lief/doc/sphinx/formats/android/dex/index.md b/vendor/lief/doc/sphinx/formats/android/dex/index.md new file mode 100644 index 0000000..263d221 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/dex/index.md @@ -0,0 +1,15 @@ +(format-dex)= + +# {fa}`brands fa-android` DEX + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python +``` + +LIEF enables parsing Android DEX files as detailed in the tutorial: +{ref}`Android Formats `. diff --git a/vendor/lief/doc/sphinx/formats/android/dex/python.md b/vendor/lief/doc/sphinx/formats/android/dex/python.md new file mode 100644 index 0000000..2b97ae3 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/dex/python.md @@ -0,0 +1,116 @@ +# {fa}`brands fa-python` Python + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_dex +``` + +```{eval-rst} +.. autofunction:: lief.DEX.version + +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. autofunction:: lief.DEX.parse +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. autoclass:: lief.DEX.File +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.DEX.Header + +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. autoclass:: lief.DEX.Method + +``` + +______________________________________________________________________ + +## Field + +```{eval-rst} +.. autoclass:: lief.DEX.Field + +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. autoclass:: lief.DEX.Class +``` + +______________________________________________________________________ + +## Code Info + +```{eval-rst} +.. autoclass:: lief.DEX.CodeInfo + +``` + +______________________________________________________________________ + +## Prototype + +```{eval-rst} +.. autoclass:: lief.DEX.Prototype + +``` + +______________________________________________________________________ + +## Type + +```{eval-rst} +.. autoclass:: lief.DEX.Type +``` + +______________________________________________________________________ + +## MapList + +```{eval-rst} +.. autoclass:: lief.DEX.MapList +``` + +______________________________________________________________________ + +## MapItem + +```{eval-rst} +.. autoclass:: lief.DEX.MapItem + +``` + +______________________________________________________________________ + +## Enums + +### Access Flags + +```{eval-rst} +.. autoclass:: lief.DEX.ACCESS_FLAGS +``` diff --git a/vendor/lief/doc/sphinx/formats/android/index.md b/vendor/lief/doc/sphinx/formats/android/index.md new file mode 100644 index 0000000..39344ae --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/index.md @@ -0,0 +1,13 @@ +(format-android)= + +# {fa}`brands fa-android` Android + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + oat/index + dex/index + vdex/index + art/index +``` diff --git a/vendor/lief/doc/sphinx/formats/android/oat/cpp.md b/vendor/lief/doc/sphinx/formats/android/oat/cpp.md new file mode 100644 index 0000000..76f29ce --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/oat/cpp.md @@ -0,0 +1,135 @@ +# {fa}`regular fa-file-code` C++ + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::is_oat(const LIEF::ELF::Binary &elf_binary) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::is_oat(std::string_view file) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::is_oat(const std::vector &raw)) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::version(const LIEF::ELF::Binary &elf_binary) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::version(std::string_view file) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::version(const std::vector &raw) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::OAT::android_version + :project: lief +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::Parser + :project: lief +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::Binary + :project: lief +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::Header + :project: lief + +``` + +______________________________________________________________________ + +## DexFile + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::DexFile + :project: lief + +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::Class + :project: lief + +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. doxygenclass:: LIEF::OAT::Method + :project: lief + +``` + +______________________________________________________________________ + +## Enums + +### OAT Class types + +```{eval-rst} +.. doxygenenum:: LIEF::OAT::OAT_CLASS_TYPES + :project: lief +``` + +______________________________________________________________________ + +### OAT Class Status + +```{eval-rst} +.. doxygenenum:: LIEF::OAT::OAT_CLASS_STATUS + :project: lief +``` + +______________________________________________________________________ + +### Header Keys + +```{eval-rst} +.. doxygenenum:: LIEF::OAT::HEADER_KEYS + :project: lief +``` + +______________________________________________________________________ + +### Instruction sets + +```{eval-rst} +.. doxygenenum:: LIEF::OAT::INSTRUCTION_SETS + :project: lief + +``` diff --git a/vendor/lief/doc/sphinx/formats/android/oat/index.md b/vendor/lief/doc/sphinx/formats/android/oat/index.md new file mode 100644 index 0000000..472dcce --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/oat/index.md @@ -0,0 +1,16 @@ +(format-oat)= + +# {fa}`brands fa-android` OAT + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python +``` + +Android OAT files are essentially ELF files, and LIEF exposes a specific API for +them. You can check out the {ref}`Android Formats ` +tutorial for more details. diff --git a/vendor/lief/doc/sphinx/formats/android/oat/python.md b/vendor/lief/doc/sphinx/formats/android/oat/python.md new file mode 100644 index 0000000..d4e6b72 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/oat/python.md @@ -0,0 +1,103 @@ +# {fa}`brands fa-python` Python + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_oat +``` + +```{eval-rst} +.. autofunction:: lief.OAT.version +``` + +```{eval-rst} +.. autofunction:: lief.OAT.android_version +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. autofunction:: lief.OAT.parse +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. autoclass:: lief.OAT.Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.OAT.Header + +``` + +______________________________________________________________________ + +## DexFile + +```{eval-rst} +.. autoclass:: lief.OAT.DexFile + +``` + +______________________________________________________________________ + +## Class + +```{eval-rst} +.. autoclass:: lief.OAT.Class + +``` + +______________________________________________________________________ + +## Method + +```{eval-rst} +.. autoclass:: lief.OAT.Method +``` + +______________________________________________________________________ + +## Enums + +### OAT Class types + +```{eval-rst} +.. autoclass:: lief.OAT.OAT_CLASS_TYPES + +``` + +______________________________________________________________________ + +### OAT Class Status + +```{eval-rst} +.. autoclass:: lief.OAT.OAT_CLASS_STATUS + +``` + +______________________________________________________________________ + +### Header Keys + +```{eval-rst} +.. autoclass:: lief.OAT.HEADER_KEYS + +``` + +______________________________________________________________________ + +### Instruction sets + +```{eval-rst} +.. autoclass:: lief.OAT.INSTRUCTION_SETS +``` diff --git a/vendor/lief/doc/sphinx/formats/android/vdex/cpp.md b/vendor/lief/doc/sphinx/formats/android/vdex/cpp.md new file mode 100644 index 0000000..eb87003 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/vdex/cpp.md @@ -0,0 +1,56 @@ +# {fa}`regular fa-file-code` C++ + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::VDEX::is_vdex(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::VDEX::is_vdex(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::VDEX::version(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::VDEX::version(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::VDEX::android_version + :project: lief +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::VDEX::Parser + :project: lief +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. doxygenclass:: LIEF::VDEX::File + :project: lief +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::VDEX::Header + :project: lief + +``` diff --git a/vendor/lief/doc/sphinx/formats/android/vdex/index.md b/vendor/lief/doc/sphinx/formats/android/vdex/index.md new file mode 100644 index 0000000..1f40cfa --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/vdex/index.md @@ -0,0 +1,15 @@ +(format-vdex)= + +# {fa}`brands fa-android` VDEX + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python +``` + +Android VDEX files are *partially* supported by LIEF, and you can refer to the +{ref}`Android Formats ` tutorial for details. diff --git a/vendor/lief/doc/sphinx/formats/android/vdex/python.md b/vendor/lief/doc/sphinx/formats/android/vdex/python.md new file mode 100644 index 0000000..1849574 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/android/vdex/python.md @@ -0,0 +1,41 @@ +# {fa}`brands fa-python` Python + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_vdex +``` + +```{eval-rst} +.. autofunction:: lief.VDEX.version +``` + +```{eval-rst} +.. autofunction:: lief.VDEX.android_version +``` + +______________________________________________________________________ + +## Parser + +```{eval-rst} +.. autofunction:: lief.VDEX.parse +``` + +______________________________________________________________________ + +## File + +```{eval-rst} +.. autoclass:: lief.VDEX.File +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.VDEX.Header + + +``` diff --git a/vendor/lief/doc/sphinx/formats/coff/cpp.md b/vendor/lief/doc/sphinx/formats/coff/cpp.md new file mode 100644 index 0000000..2c6c5cd --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/coff/cpp.md @@ -0,0 +1,163 @@ +# {fa}`regular fa-file-code` C++ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Parser +``` + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::ParserConfig +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Header +``` + +______________________________________________________________________ + +## Regular Header + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::RegularHeader +``` + +______________________________________________________________________ + +## BigObj Header + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::BigObjHeader +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Section +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Relocation +``` + +______________________________________________________________________ + +## String + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::String +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::Symbol +``` + +______________________________________________________________________ + +## AuxiliarySymbol + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliarySymbol +``` + +______________________________________________________________________ + +## AuxiliaryCLRToken + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliaryCLRToken +``` + +______________________________________________________________________ + +## AuxiliaryFunctionDefinition + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliaryFunctionDefinition +``` + +______________________________________________________________________ + +## AuxiliaryWeakExternal + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliaryWeakExternal +``` + +______________________________________________________________________ + +## AuxiliarybfAndefSymbol + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliarybfAndefSymbol +``` + +______________________________________________________________________ + +## AuxiliarySectionDefinition + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliarySectionDefinition +``` + +______________________________________________________________________ + +## AuxiliaryFile + +```{eval-rst} +.. doxygenclass:: LIEF::COFF::AuxiliaryFile +``` + +______________________________________________________________________ + +## Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::get_kind(BinaryStream &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_coff(BinaryStream &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_coff(std::string_view) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_coff(const std::vector< uint8_t > &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_coff(const uint8_t *, size_t) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_bigobj(BinaryStream &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::COFF::is_regular(BinaryStream &) +``` diff --git a/vendor/lief/doc/sphinx/formats/coff/index.md b/vendor/lief/doc/sphinx/formats/coff/index.md new file mode 100644 index 0000000..4c0d6e2 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/coff/index.md @@ -0,0 +1,70 @@ +(format-coff)= + +# {fa}`brands fa-windows` COFF + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +COFF object files can be parsed using {sub-ref}`lief-coff-parse` or the generic +{sub-ref}`lief-parse` function: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/coff.py", "parse", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/coff.cpp", "parse", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/coff.rs", "parse") }} +::: +:::: + +These functions return a {sub-ref}`lief-coff-Binary` instance that exposes the main API +for processing and accessing COFF information: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/coff.py", "sections") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/coff.cpp", "sections") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/coff.rs", "sections") }} +::: +:::: + +(format-coff-disassembler)= + +## Disassembler + +The {sub-ref}`lief-coff-Binary` object exposes a disassembler API for iterating over +the instructions of a COFF binary. One can disassemble a function using +{sub-ref}`lief-coff-binary-disassemble`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/coff.py", "disassemble") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/coff.cpp", "disassemble") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/coff.rs", "disassemble") }} +::: +:::: + +For more details about the disassembler and the {sub-ref}`lief-asm-instruction` API, +please refer to the {ref}`Disassembler section `. + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/coff/python.md b/vendor/lief/doc/sphinx/formats/coff/python.md new file mode 100644 index 0000000..6c0dd6d --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/coff/python.md @@ -0,0 +1,201 @@ +# {fa}`brands fa-python` Python + +## Parser + +```{eval-rst} +.. autofunction:: lief.COFF.parse +``` + +```{eval-rst} +.. autoclass:: lief.COFF.ParserConfig +``` + +## Binary + +```{eval-rst} +.. autoclass:: lief.COFF.Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.Header + :top-classes: lief._lief.COFF.Header + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.Header +``` + +______________________________________________________________________ + +## RegularHeader + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.RegularHeader + :top-classes: lief._lief.COFF.Header + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.RegularHeader +``` + +______________________________________________________________________ + +## BigObjHeader + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.BigObjHeader + :top-classes: lief._lief.COFF.Header + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.BigObjHeader +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. autoclass:: lief.COFF.Section +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. autoclass:: lief.COFF.Relocation +``` + +______________________________________________________________________ + +## String + +```{eval-rst} +.. autoclass:: lief.COFF.String +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.Symbol + :top-classes: lief._lief.Symbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.Symbol +``` + +______________________________________________________________________ + +## AuxiliarySymbol + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliarySymbol + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliarySymbol +``` + +______________________________________________________________________ + +## AuxiliaryCLRToken + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliaryCLRToken + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliaryCLRToken +``` + +______________________________________________________________________ + +## AuxiliaryFunctionDefinition + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliaryFunctionDefinition + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliaryFunctionDefinition +``` + +______________________________________________________________________ + +## AuxiliaryWeakExternal + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliaryWeakExternal + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliaryWeakExternal +``` + +______________________________________________________________________ + +## AuxiliarybfAndefSymbol + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliarybfAndefSymbol + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliarybfAndefSymbol +``` + +______________________________________________________________________ + +## AuxiliarySectionDefinition + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliarySectionDefinition + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliarySectionDefinition +``` + +______________________________________________________________________ + +## AuxiliaryFile + +```{eval-rst} +.. lief-inheritance:: lief._lief.COFF.AuxiliaryFile + :top-classes: lief._lief.COFF.AuxiliarySymbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.COFF.AuxiliaryFile +``` + +## Utilities + +```{eval-rst} +.. autofunction:: lief.is_coff +``` diff --git a/vendor/lief/doc/sphinx/formats/coff/rust.md b/vendor/lief/doc/sphinx/formats/coff/rust.md new file mode 100644 index 0000000..68a5ca3 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/coff/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::coff` +::: diff --git a/vendor/lief/doc/sphinx/formats/elf.rst b/vendor/lief/doc/sphinx/formats/elf.rst deleted file mode 100644 index 6255c6d..0000000 --- a/vendor/lief/doc/sphinx/formats/elf.rst +++ /dev/null @@ -1,131 +0,0 @@ -ELF Format -========== - -Duality sections/segments --------------------------- - -In the ``ELF`` format there are two kinds of containers for handling data: - - * Sections - * Segments - -A first sight it's a bit disturbing because it's two representations of the same data. In fact these two representations are used differently. - -**Sections** are usually used at **link** time by the linker (e.g. ``/bin/ld``) whereas **segments** are usually used at **load** time by kernel and loader (e.g. ``/lib/ld-linux.so``). - -Sections header table is not mandatory so you can execute an ELF binary without sections header table. Let's take an example: - -.. code-block:: console - - $ readelf -Sh /bin/ls - ELF Header: - Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 - Class: ELF64 - Data: 2's complement, little endian - Version: 1 (current) - OS/ABI: UNIX - System V - ABI Version: 0 - Type: EXEC (Executable file) - Machine: Advanced Micro Devices X86-64 - Version: 0x1 - Entry point address: 0x4022f0 - Start of program headers: 64 (bytes into file) - Start of section headers: 37840 (bytes into file) - Flags: 0x0 - Size of this header: 64 (bytes) - Size of program headers: 56 (bytes) - Number of program headers: 9 - Size of section headers: 64 (bytes) - Number of section headers: 28 - Section header string table index: 27 - - Section Headers: - [Nr] Name Type Address Offset - Size EntSize Flags Link Info Align - [ 0] NULL 0000000000000000 00000000 - 0000000000000000 0000000000000000 0 0 0 - [ 1] .interp PROGBITS 0000000000400238 00000238 - 000000000000001c 0000000000000000 A 0 0 1 - [ 2] .note.ABI-tag NOTE 0000000000400254 00000254 - 0000000000000020 0000000000000000 A 0 0 4 - [ 3] .note.gnu.build-i NOTE 0000000000400274 00000274 - 0000000000000024 0000000000000000 A 0 0 4 - [ 4] .gnu.hash GNU_HASH 0000000000400298 00000298 - 0000000000000060 0000000000000000 A 5 0 8 - [ 5] .dynsym DYNSYM 00000000004002f8 000002f8 - 00000000000006d8 0000000000000018 A 6 1 8 - [ 6] .dynstr STRTAB 00000000004009d0 000009d0 - 00000000000002f1 0000000000000000 A 0 0 1 - [ 7] .gnu.version VERSYM 0000000000400cc2 00000cc2 - 0000000000000092 0000000000000002 A 5 0 2 - ... - - [27] .shstrtab STRTAB 0000000000000000 000092d6 - 00000000000000f8 0000000000000000 0 0 1 - Key to Flags: - W (write), A (alloc), X (execute), M (merge), S (strings), l (large) - I (info), L (link order), G (group), T (TLS), E (exclude), x (unknown) - O (extra OS processing required) o (OS specific), p (processor specific) - -Now we remove sections header with **LIEF**: - -.. code-block:: python - - from lief import ELF - binary = ELF.Parse("/bin/ls") # Build an ELF binary - header = binary.header - header.section_header_offset = 0; - header numberof_section_headers = 0; - binary.write("out.bin"); - -Now if we run ``out.bin``: - -.. code-block:: console - - $ ./out.bin - elf_reader.py elf_remove_section_table.py library_symbols_obfuscation out.bin - elf_rebuilder.py elf_symbol_obfuscation.py nm.py pe_reader.py - -We can check that sections header table has been removed: - -.. code-block:: console - - $ readelf -Sh ./out.bin - ELF Header: - Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 - Class: ELF64 - Data: 2's complement, little endian - Version: 1 (current) - OS/ABI: UNIX - System V - ABI Version: 0 - Type: EXEC (Executable file) - Machine: Advanced Micro Devices X86-64 - Version: 0x1 - Entry point address: 0x4022f0 - Start of program headers: 64 (bytes into file) - Start of section headers: 0 (bytes into file) - Flags: 0x0 - Size of this header: 64 (bytes) - Size of program headers: 56 (bytes) - Number of program headers: 9 - Size of section headers: 64 (bytes) - Number of section headers: 0 - Section header string table index: 27 - - There are no sections in this file. - -As content can be used and updated by both sections and segments we can't store it in sections/segments. Instead we use an interface to manage content. The manager interface looks like this: - -| - -.. image:: ../_static/data_handler.png - :height: 539 px - :width: 1080 px - :scale: 40 % - :alt: alternate text - :align: center - -| - -The manager is implemented in the ``ELF::DataHandler::Handler`` class. - diff --git a/vendor/lief/doc/sphinx/formats/elf/cpp.md b/vendor/lief/doc/sphinx/formats/elf/cpp.md new file mode 100644 index 0000000..481abc4 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/elf/cpp.md @@ -0,0 +1,371 @@ +# {fa}`regular fa-file-code` C++ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Parser +``` + +```{eval-rst} +.. doxygenstruct:: LIEF::ELF::ParserConfig +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Header +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Section +``` + +______________________________________________________________________ + +## Segment + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Segment +``` + +______________________________________________________________________ + +## Dynamic Entry + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntry +``` + +______________________________________________________________________ + +## Dynamic Entry Library + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryLibrary +``` + +______________________________________________________________________ + +## Dynamic Shared Object + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicSharedObject +``` + +______________________________________________________________________ + +## Dynamic Entry Run Path + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryRunPath +``` + +______________________________________________________________________ + +## Dynamic Entry RPath + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryRpath +``` + +______________________________________________________________________ + +## Dynamic Entry Array + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryArray +``` + +______________________________________________________________________ + +## Dynamic Entry Flags + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryFlags +``` + +______________________________________________________________________ + +## Dynamic Entry Auxiliary + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryAuxiliary +``` + +______________________________________________________________________ + +## Dynamic Entry Filter + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::DynamicEntryFilter +``` + +______________________________________________________________________ + +## Relocations + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Relocation +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Symbol +``` + +______________________________________________________________________ + +## Symbol Version + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SymbolVersion +``` + +______________________________________________________________________ + +## Symbol Version Auxiliary + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SymbolVersionAux +``` + +______________________________________________________________________ + +## Symbol Version Definition + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SymbolVersionDefinition +``` + +______________________________________________________________________ + +## Symbol Version Requirement + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SymbolVersionRequirement +``` + +______________________________________________________________________ + +## Symbol Version Auxiliary Requirement + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SymbolVersionAuxRequirement +``` + +______________________________________________________________________ + +## GNU Hash table + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::GnuHash +``` + +______________________________________________________________________ + +## SYSV Hash table + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::SysvHash +``` + +______________________________________________________________________ + +## Note + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Note +``` + +______________________________________________________________________ + +## Core PrPsInfo + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::CorePrPsInfo +``` + +______________________________________________________________________ + +## Core File + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::CoreFile +``` + +______________________________________________________________________ + +## Core PrStatus + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::CorePrStatus +``` + +______________________________________________________________________ + +## Core Siginfo + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::CoreSigInfo +``` + +______________________________________________________________________ + +## Core Auxiliary Vector + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::CoreAuxv +``` + +______________________________________________________________________ + +## Android Identity + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::AndroidIdent +``` + +______________________________________________________________________ + +## QNX Stack + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::QNXStack +``` + +______________________________________________________________________ + +## Note ABI + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::NoteAbi +``` + +______________________________________________________________________ + +## Note Gnu Property + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::NoteGnuProperty +``` + +______________________________________________________________________ + +## Generic + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Generic +``` + +______________________________________________________________________ + +## AArch64 Feature + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::AArch64Feature +``` + +______________________________________________________________________ + +## AArch64 PAuth + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::AArch64PAuth + +``` + +______________________________________________________________________ + +## Needed + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Needed +``` + +______________________________________________________________________ + +## No Copy on Protected + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::NoteNoCopyOnProtected +``` + +______________________________________________________________________ + +## Stack Size + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::StackSize +``` + +______________________________________________________________________ + +## X86 Feature + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::X86Features +``` + +______________________________________________________________________ + +## X86 ISA + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::X86ISA +``` + +______________________________________________________________________ + +## Builder + +```{eval-rst} +.. doxygenclass:: LIEF::ELF::Builder +``` + +______________________________________________________________________ + +## Utilities + +```{doxygenfunction} LIEF::ELF::check_layout +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ELF::is_elf(std::string_view) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::ELF::is_elf(const std::vector&) +``` + +______________________________________________________________________ + +## Enums + +### Architectures + +```{eval-rst} +.. doxygenenum:: LIEF::ELF::ARCH +``` + +### Processor Flags + +```{eval-rst} +.. doxygenenum:: LIEF::ELF::PROCESSOR_FLAGS +``` diff --git a/vendor/lief/doc/sphinx/formats/elf/index.md b/vendor/lief/doc/sphinx/formats/elf/index.md new file mode 100644 index 0000000..beaca1c --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/elf/index.md @@ -0,0 +1,443 @@ +(format-elf)= + +# {fa}`brands fa-linux` ELF + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +ELF binaries can be parsed with LIEF using the {sub-ref}`lief-elf-parse` function: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "parse", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "parse", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "parse") }} +::: +:::: + +:::{note} +In Python, you can also use {py:func}`lief.parse`, which returns a +{class}`lief.ELF.Binary` object. +::: + +With the parsed ELF binary, you can use the {sub-ref}`lief-elf-binary` API to +inspect or modify the binary itself. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "inspect") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "inspect") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "inspect") }} +::: +:::: + +After modifying a {sub-ref}`lief-elf-binary` object, you can use the +{sub-ref}`lief-elf-binary-write` method to write it back to a raw ELF file. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "write") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "write") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "write") }} +::: +:::: + +```{eval-rst} +.. seealso:: + + :ref:`binary-abstraction` +``` + +You can also use {sub-ref}`lief-elf-binary-write_to_bytes` to get the new ELF binary +as a buffer of bytes: + +:::{note} +This API can also take an extra {sub-ref}`lief-elf-builder-config` parameter. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "write-bytes") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "write-bytes") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "write-bytes") }} +::: +:::: + +(format-elf-section-segment)= + +## Adding a Section/Segment + +The ELF format uses two tables to represent different slices of the binary: + +1. The sections table +2. The segments table + +While the sections table offers a detailed view of the binary, it is primarily +used by the **compiler** and the **linker**. In particular, this table is not required +for **loading** and **executing** an ELF file. While the Android loader +enforces the presence of a sections table and requires specific sections, +this table is not used during the actual loading process. + +To modify an ELF file to load additional content into memory (e.g., code or data), +adding a {sub-ref}`lief-elf-segment` is recommended over adding a section: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "add-segment") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "add-segment") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "add-segment") }} +::: +:::: + +Alternatively, you can create a {sub-ref}`lief-elf-section`, which will **implicitly** +create an associated `PT_LOAD` segment: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "add-section-loaded") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "add-section-loaded") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "add-section-loaded") }} +::: +:::: + +As mentioned above, the segments table is more critical than the sections table +from a loading perspective. Therefore, it is more appropriate to explicitly add +a new segment rather than adding a section that implicitly adds a segment. + +On the other hand, for debugging purposes or specialized tools, you might want +to add a **non-loaded** section. In this case, the section data is inserted at +the end of the binary, immediately after the data wrapped by the segments: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "add-section-unloaded") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "add-section-unloaded") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "add-section-unloaded") }} +::: +:::: + +See: {sub-ref}`lief-elf-binary-add` for detailed API information. + +(format-elf-dump)= + +## Dump Analysis + +LIEF has the support to process ELF memory dump with {sub-ref}`lief-elf-parse_from_dump`. This function +translates the file offsets referenced by the ELF structures into their location inside +the dump, using the base address passed as the second parameter: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "dump") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "dump") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "dump") }} +::: +:::: + +:::{note} +The second parameter **must** be the (absolute) virtual address at which the +dump was mapped. It is used to convert the virtual addresses found in the ELF +structures back into an offset within the dump. +::: + +:::{warning} +Parsing an ELF from a dump is subject to the same limitations as +parsing it from memory: the segments (`PT_LOAD`) and the program headers are +reliable, but the **section header table is generally not mapped** and the +content of the dynamic table (dynamic entries, dynamic symbols and +relocations) reflects its *runtime* state and may not be recoverable. Prefer +working with the segments when analyzing a dump. +::: + +### Producing a dump with the runtime API + +Such a dump can be produced from a live process thanks to the LIEF +{ref}`runtime ` and, more precisely, the +{ref}`Module API `. {sub-ref}`lief-runtime-module-dump` captures the +memory of a loaded module (from its imagebase over its virtual size): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "dump-runtime") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "dump-runtime") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "dump-runtime") }} +::: +:::: + +## Advanced Parsing/Writing + +{sub-ref}`lief-elf-parse` can take an extra {sub-ref}`lief-elf-parser-config` parameter to specify +parts of the ELF format to skip during parsing. + +:::{warning} +Generally, {sub-ref}`lief-elf-binary-write` requires a **complete** initial +parsing of the ELF file. +::: + +Similarly, {sub-ref}`lief-elf-binary-write` can also take an extra {sub-ref}`lief-elf-builder-config` +to specify which parts of the ELF should be rebuilt. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "advanced") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "advanced") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "advanced") }} +::: +:::: + +## DWARF Support + +If the binary embeds DWARF debug information, you can use +{sub-ref}`lief-dwarf-binary-debug-info` to access the underlying {sub-ref}`lief-dwarf-debug-info` +object. + +Note that this support is only available in the {ref}`Extended ` +version of LIEF. + +(format-elf-rpath-modification)= + +## R[UN]PATH Modification + +LIEF provides comprehensive facilities for manipulating a binary's RPATH/RUNPATH. + +:::{admonition} DT_RPATH vs DT_RUNPATH +:class: tip + +`DT_RPATH` and `DT_RUNPATH` are both dynamic tags used to +specify runtime library search paths. + +`DT_RPATH` is now considered legacy because it does not respect the +precedence of the `LD_LIBRARY_PATH` environment variable. This means that +if `LD_LIBRARY_PATH` is set to a valid directory where the library can +be found, it will be ignored in favor of the `DT_RPATH` value. +Therefore, the `DT_RUNPATH` tag should be preferred over `DT_RPATH`. + +Note that if both tags are present, the loader will use the `DT_RUNPATH` +entry over the legacy `DT_RPATH`. +::: + +The `DT_RPATH` tag is represented by the {sub-ref}`lief-elf-DynamicEntryRpath` +interface, and the `DT_RUNPATH` tag by {sub-ref}`lief-elf-DynamicEntryRunPath`. + +The RPATH/RUNPATH modifications supported by LIEF include: + +**Adding a new entry** + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "rpath-add") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "rpath-add") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "rpath-add") }} +::: +:::: + +**Changing an entry** + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "rpath-change") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "rpath-change") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "rpath-change") }} +::: +:::: + +**Removing entries** + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "rpath-remove") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "rpath-remove") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "rpath-remove") }} +::: +:::: + +You can also check the {ref}`lief-patchelf ` section for a +command-line interface. + +(format-elf-symbols-version)= + +## Symbol Versions + +The ELF format supports symbol versioning, allowing multiple versions of +the same function or variable to coexist within a single shared object. + +During compilation, the linker selects the appropriate symbols and versions +based on the libraries provided as input. For example, if a program uses the +`printf` function and is linked with a version of `libc.so` that exposes +`printf@@GLIBC_2.40`, the compiled executable will require at least that +version of the `libc` to run. + +These versioning requirements can be problematic when creating executables or +libraries intended for a wide range of Linux distributions. + +The **best way** to ensure maximum compatibility is to target the minimum +supported version of glibc. For instance, if you aim to support Linux +distributions with at least glibc version `2.28` (released in 2018), you +should specifically provide that version of `libc.so` during linking: + +```console +$ ld --sysroot=/sysroot/glibc-2.28/ my_program.o -o my_program.elf +$ ld -L /sysroot/glibc-2.28/lib64/ my_program.o -o my_program.elf -lc +``` + +In situations where you lack control over the link step, you may want to change +the versioning **post-compilation**. LIEF can be used in these situations to +perform the following modifications on symbol versions. + +**Remove the version for a specific symbol** + +In this example, we remove the version attached to the `printf` symbol +by setting the versioning as global (the default setting for imported functions). + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "symver-symbol") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "symver-symbol") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "symver-symbol") }} +::: +:::: + +**Remove all the versions for a specific library** + +In this example, we remove all the symbol versions associated with an imported +library (`libm.so.6`): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/elf.py", "symver-library") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/elf.cpp", "symver-library") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/elf.rs", "symver-library") }} +::: +:::: + +::::{tabs} +:::{tab} {fa}`solid fa-terminal` Before +```{code-block} console +$ readelf -V input.elf + +Version symbols section '.gnu.version' contains 48 entries: + Addr: 00000000000009bc Offset: 0x0009bc Link: 6 (.dynsym) + 000: 0 (*local*) 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) + 004: 2 (GLIBC_2.2.5) 0 (*local*) 4 (GLIBC_2.17) 3 (GLIBC_2.2.5) + 008: 2 (GLIBC_2.2.5) 5 (GLIBC_2.27) 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) + 00c: 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 6 (GLIBC_2.4) 2 (GLIBC_2.2.5) + 010: 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) + 014: 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 0 (*local*) + 018: 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) + 01c: 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) + 020: 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) + 024: 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) + 028: 3 (GLIBC_2.2.5) 0 (*local*) 3 (GLIBC_2.2.5) 3 (GLIBC_2.2.5) + 02c: 3 (GLIBC_2.2.5) 7 (GLIBC_2.29) 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) + +Version needs section '.gnu.version_r' contains 2 entries: + Addr: 0000000000000a20 Offset: 0x000a20 Link: 7 (.dynstr) + 0x0000: Version: 1 File: libm.so.6 Cnt: 3 + 0x0010: Name: GLIBC_2.29 Flags: none Version: 7 + 0x0020: Name: GLIBC_2.27 Flags: none Version: 5 + 0x0030: Name: GLIBC_2.2.5 Flags: none Version: 3 + 0x0040: Version: 1 File: libc.so.6 Cnt: 3 + 0x0050: Name: GLIBC_2.4 Flags: none Version: 6 + 0x0060: Name: GLIBC_2.17 Flags: none Version: 4 + 0x0070: Name: GLIBC_2.2.5 Flags: none Version: 2 +``` +::: +:::{tab} {fa}`solid fa-terminal` After +```{code-block} console +$ readelf -V updated.elf + +Version symbols section '.gnu.version' contains 48 entries: + Addr: 00000000000009bc Offset: 0x0009bc Link: 6 (.dynsym) + 000: 0 (*local*) 1 (*global*) 1 (*global*) 1 (*global*) + 004: 1 (*global*) 0 (*local*) 4 (GLIBC_2.17) 1 (*global*) + 008: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 00c: 1 (*global*) 1 (*global*) 6 (GLIBC_2.4) 1 (*global*) + 010: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 014: 1 (*global*) 1 (*global*) 1 (*global*) 0 (*local*) + 018: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 01c: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 020: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 024: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + 028: 1 (*global*) 0 (*local*) 1 (*global*) 1 (*global*) + 02c: 1 (*global*) 1 (*global*) 1 (*global*) 1 (*global*) + +Version needs section '.gnu.version_r' contains 1 entries: + Addr: 0000000000000a20 Offset: 0x000a20 Link: 7 (.dynstr) + 0x0000: Version: 1 File: libc.so.6 Cnt: 3 + 0x0010: Name: GLIBC_2.4 Flags: none Version: 6 + 0x0020: Name: GLIBC_2.17 Flags: none Version: 4 + 0x0030: Name: GLIBC_2.2.5 Flags: none Version: 2 +``` +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/elf/python.md b/vendor/lief/doc/sphinx/formats/elf/python.md new file mode 100644 index 0000000..5befc7a --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/elf/python.md @@ -0,0 +1,546 @@ +# {fa}`brands fa-python` Python + +## Parser + +```{eval-rst} +.. autofunction:: lief.ELF.parse +``` + +```{eval-rst} +.. autoclass:: lief.ELF.ParserConfig +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. autoclass:: lief.ELF.Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.ELF.Header +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.Section + :top-classes: lief._lief.Section + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.Section +``` + +______________________________________________________________________ + +## Segment + +```{eval-rst} +.. autoclass:: lief.ELF.Segment +``` + +______________________________________________________________________ + +## Dynamic Entry + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntry + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntry +``` + +______________________________________________________________________ + +## Dynamic Entry Library + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryLibrary + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryLibrary +``` + +______________________________________________________________________ + +## Dynamic Shared Object + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicSharedObject + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicSharedObject +``` + +______________________________________________________________________ + +## Dynamic Entry Run Path + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryRunPath + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryRunPath +``` + +______________________________________________________________________ + +## Dynamic Entry RPath + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryRpath + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryRpath +``` + +______________________________________________________________________ + +## Dynamic Entry Array + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryArray + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryArray +``` + +______________________________________________________________________ + +## Dynamic Entry Flags + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryFlags + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryFlags + +``` + +______________________________________________________________________ + +## Dynamic Entry Auxiliary + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryAuxiliary + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryAuxiliary +``` + +______________________________________________________________________ + +## Dynamic Entry Filter + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.DynamicEntryFilter + :top-classes: lief._lief.ELF.DynamicEntry + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.DynamicEntryFilter +``` + +______________________________________________________________________ + +## Relocations + +```{eval-rst} +.. autoclass:: lief.ELF.Relocation +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. autoclass:: lief.ELF.Symbol +``` + +______________________________________________________________________ + +## Symbol Version + +```{eval-rst} +.. autoclass:: lief.ELF.SymbolVersion +``` + +______________________________________________________________________ + +## Symbol Version Auxiliary + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.SymbolVersionAux + :top-classes: lief._lief.SymbolVersionAux + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.SymbolVersionAux +``` + +______________________________________________________________________ + +## Symbol Version Definition + +```{eval-rst} +.. autoclass:: lief.ELF.SymbolVersionDefinition +``` + +______________________________________________________________________ + +## Symbol Version Requirement + +```{eval-rst} +.. autoclass:: lief.ELF.SymbolVersionRequirement +``` + +______________________________________________________________________ + +## Symbol Version Auxiliary Requirement + +```{eval-rst} +.. autoclass:: lief.ELF.SymbolVersionAuxRequirement +``` + +______________________________________________________________________ + +## GNU Hash table + +```{eval-rst} +.. autoclass:: lief.ELF.GnuHash +``` + +______________________________________________________________________ + +## SYSV Hash table + +```{eval-rst} +.. autoclass:: lief.ELF.SysvHash +``` + +______________________________________________________________________ + +## Note + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.Note + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.Note +``` + +______________________________________________________________________ + +## Core PrPsInfo + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.CorePrPsInfo + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.CorePrPsInfo +``` + +______________________________________________________________________ + +## Core PrStatus + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.CorePrStatus + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.CorePrStatus +``` + +______________________________________________________________________ + +## Core File + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.CoreFile + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.CoreFile +``` + +______________________________________________________________________ + +## Core Siginfo + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.CoreSigInfo + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.CoreSigInfo +``` + +______________________________________________________________________ + +## Core Auxiliary Vector + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.CoreAuxv + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.CoreAuxv +``` + +______________________________________________________________________ + +## Android Ident + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.AndroidIdent + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.AndroidIdent +``` + +______________________________________________________________________ + +## QNX Stack + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.QNXStack + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.QNXStack +``` + +______________________________________________________________________ + +## Note ABI + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.NoteAbi + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.NoteAbi +``` + +______________________________________________________________________ + +## Note Gnu Property + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.NoteGnuProperty + :top-classes: lief._lief.ELF.Note + :parts: 2 +``` + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.NoteGnuProperty.Property + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 3 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.NoteGnuProperty +``` + +______________________________________________________________________ + +## Generic + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.Generic + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.Generic +``` + +______________________________________________________________________ + +## AArch64 Feature + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.AArch64Feature + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.AArch64Feature +``` + +______________________________________________________________________ + +## AArch64 PAuth + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.AArch64PAuth + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.AArch64PAuth +``` + +______________________________________________________________________ + +## Needed + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.Needed + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.Needed +``` + +______________________________________________________________________ + +## No Copy on Protected + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.NoteNoCopyOnProtected + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.NoteNoCopyOnProtected +``` + +______________________________________________________________________ + +## Stack Size + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.StackSize + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.StackSize +``` + +______________________________________________________________________ + +## X86 Feature + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.X86Features + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.X86Features +``` + +______________________________________________________________________ + +## X86 ISA + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.X86ISA + :top-classes: lief._lief.ELF.NoteGnuProperty.Property + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.ELF.X86ISA +``` + +______________________________________________________________________ + +## Builder + +```{eval-rst} +.. autoclass:: lief.ELF.Builder +``` + +## Enums + +### Architectures + +```{eval-rst} +.. autoclass:: lief.ELF.ARCH + +``` + +### Processor Flags + +```{eval-rst} +.. autoclass:: lief.ELF.PROCESSOR_FLAGS + +``` + +## Utilities + +```{eval-rst} +.. autofunction:: lief.ELF.check_layout +``` + +```{eval-rst} +.. autofunction:: lief.is_elf +``` diff --git a/vendor/lief/doc/sphinx/formats/elf/rust.md b/vendor/lief/doc/sphinx/formats/elf/rust.md new file mode 100644 index 0000000..2f74da5 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/elf/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::elf` +::: diff --git a/vendor/lief/doc/sphinx/formats/index.rst b/vendor/lief/doc/sphinx/formats/index.rst deleted file mode 100644 index f8de55d..0000000 --- a/vendor/lief/doc/sphinx/formats/index.rst +++ /dev/null @@ -1,9 +0,0 @@ -Formats -======= - -.. toctree:: - :maxdepth: 2 - - elf.rst - pe.rst - diff --git a/vendor/lief/doc/sphinx/formats/macho/cpp.md b/vendor/lief/doc/sphinx/formats/macho/cpp.md new file mode 100644 index 0000000..22f5cfe --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/macho/cpp.md @@ -0,0 +1,565 @@ +# {fa}`regular fa-file-code` C++ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Parser + :project: lief + +``` + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::BinaryParser + :project: lief + +``` + +```{eval-rst} +.. doxygenstruct:: LIEF::MachO::ParserConfig + :project: lief +``` + +______________________________________________________________________ + +## FatBinary + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::FatBinary + :project: lief +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Binary + :project: lief +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Header + :project: lief + +``` + +______________________________________________________________________ + +## Builder + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Builder + :project: lief +``` + +______________________________________________________________________ + +## DylibCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DylibCommand + :project: lief + +``` + +______________________________________________________________________ + +## DylinkerCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DylinkerCommand + :project: lief + +``` + +______________________________________________________________________ + +## DynamicSymbolCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DynamicSymbolCommand + :project: lief + +``` + +______________________________________________________________________ + +## LoadCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::LoadCommand + :project: lief + +``` + +______________________________________________________________________ + +## MainCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::MainCommand + :project: lief + +``` + +______________________________________________________________________ + +## NoteCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::NoteCommand + :project: lief +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Section + :project: lief + +``` + +______________________________________________________________________ + +## ThreadLocalVariables + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::ThreadLocalVariables + :project: lief + +``` + +______________________________________________________________________ + +## SegmentCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SegmentCommand + :project: lief + +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Symbol + :project: lief + +``` + +______________________________________________________________________ + +## SymbolCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SymbolCommand + :project: lief + +``` + +______________________________________________________________________ + +## UUIDCommand + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::UUIDCommand + :project: lief +``` + +______________________________________________________________________ + +## Dyld Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DyldInfo + :project: lief +``` + +______________________________________________________________________ + +## Function starts + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::FunctionStarts + :project: lief +``` + +______________________________________________________________________ + +## Function Variants + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::FunctionVariants + :project: lief +``` + +______________________________________________________________________ + +## Function Variant Fixups + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::FunctionVariantFixups + :project: lief +``` + +______________________________________________________________________ + +## Lazy Load Dylib Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::LazyLoadDylibInfo + :project: lief +``` + +______________________________________________________________________ + +## Source Version + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SourceVersion + :project: lief +``` + +______________________________________________________________________ + +## Version Min + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::VersionMin + :project: lief +``` + +______________________________________________________________________ + +## Routine + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Routine + :project: lief +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Relocation + :project: lief +``` + +______________________________________________________________________ + +## Relocation Object + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::RelocationObject + :project: lief +``` + +______________________________________________________________________ + +## Relocation Dyld + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::RelocationDyld + :project: lief +``` + +______________________________________________________________________ + +## Relocation Fixup + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::RelocationFixup + :project: lief +``` + +______________________________________________________________________ + +## Dyld Binding Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DyldBindingInfo + :project: lief +``` + +______________________________________________________________________ + +## Chained Binding Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::ChainedBindingInfo + :project: lief +``` + +______________________________________________________________________ + +## Export Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::ExportInfo + :project: lief +``` + +______________________________________________________________________ + +## Thread Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::ThreadCommand + :project: lief +``` + +______________________________________________________________________ + +## RPath Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::RPathCommand + :project: lief +``` + +______________________________________________________________________ + +## Code Signature + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::CodeSignature + :project: lief +``` + +______________________________________________________________________ + +## Data In Code + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DataInCode + :project: lief +``` + +______________________________________________________________________ + +## Data Code Entry + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DataCodeEntry + :project: lief +``` + +______________________________________________________________________ + +## Segment Split Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SegmentSplitInfo + :project: lief +``` + +______________________________________________________________________ + +## Sub-Framework + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SubFramework + :project: lief +``` + +______________________________________________________________________ + +## Sub-Client + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::SubClient + :project: lief +``` + +______________________________________________________________________ + +## Dyld Environment + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DyldEnvironment + :project: lief +``` + +______________________________________________________________________ + +## Encryption Info + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::EncryptionInfo + :project: lief +``` + +______________________________________________________________________ + +## Build Version + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::BuildVersion + :project: lief +``` + +______________________________________________________________________ + +## Build Tool Version + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::BuildToolVersion + :project: lief +``` + +______________________________________________________________________ + +## Fileset Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::FilesetCommand + :project: lief +``` + +______________________________________________________________________ + +## DyldChainedFixups Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DyldChainedFixups + :project: lief +``` + +______________________________________________________________________ + +## DyldExportsTrie Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::DyldExportsTrie + :project: lief +``` + +______________________________________________________________________ + +## Code Signature Dir Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::CodeSignatureDir + :project: lief +``` + +______________________________________________________________________ + +## Linker Optimization Hint Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::LinkerOptHint + :project: lief +``` + +______________________________________________________________________ + +## Two Level Hints Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::TwoLevelHints + :project: lief +``` + +______________________________________________________________________ + +## Unknown Command + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::UnknownCommand + :project: lief +``` + +______________________________________________________________________ + +## Stub + +```{eval-rst} +.. doxygenclass:: LIEF::MachO::Stub + :project: lief +``` + +______________________________________________________________________ + +## Utilities + +```{doxygenfunction} LIEF::MachO::check_layout(const Binary&, std::string*) +``` + +```{doxygenfunction} LIEF::MachO::check_layout(const FatBinary&, std::string*) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::MachO::is_macho(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::MachO::is_macho(const std::vector&) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::MachO::is_fat(std::string_view) + :project: lief +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::MachO::is_64(std::string_view) + :project: lief + +``` + +______________________________________________________________________ + +## Enums + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::MACHO_TYPES + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::X86_RELOCATION + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::X86_64_RELOCATION + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::PPC_RELOCATION + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::ARM_RELOCATION + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::ARM64_RELOCATION + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::DYLD_CHAINED_FORMAT + :project: lief +``` + +```{eval-rst} +.. doxygenenum:: LIEF::MachO::DYLD_CHAINED_PTR_FORMAT + :project: lief +``` diff --git a/vendor/lief/doc/sphinx/formats/macho/index.md b/vendor/lief/doc/sphinx/formats/macho/index.md new file mode 100644 index 0000000..21b41e3 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/macho/index.md @@ -0,0 +1,246 @@ +(format-macho)= + +# {fa}`brands fa-apple` Mach-O + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +Mach-O binaries can be parsed using the {sub-ref}`lief-macho-parse` function. + +:::{note} +The Mach-O format defines FAT binaries, which can embed different +architectures into a single file. {sub-ref}`lief-macho-parse` always returns a +{sub-ref}`lief-macho-fatbinary`, assuming that a non-FAT Mach-O can be represented as +a {sub-ref}`lief-macho-fatbinary` containing a single architecture. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "parse", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "parse", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "parse") }} +::: +:::: + +This {sub-ref}`lief-macho-fatbinary` object exposes facilities to either iterate over the +different {sub-ref}`lief-macho-binary` or pick/take a specific one: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "iterate") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "iterate") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "iterate") }} +::: +:::: + +After modifying a {sub-ref}`lief-macho-binary` or {sub-ref}`lief-macho-fatbinary` object, you can +use either {sub-ref}`lief-macho-binary-write` or {sub-ref}`lief-macho-fatbinary-write` to write +it back to a raw Mach-O file. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "write-fat") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "write-fat") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "write-fat") }} +::: +:::: + +You can also use {sub-ref}`lief-macho-binary-write_to_bytes` to get the new Mach-O binary +as a buffer of bytes: + +:::{note} +This API can also take an extra {sub-ref}`lief-macho-builder-config` parameter. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "write-bytes") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "write-bytes") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "write-bytes") }} +::: +:::: + +## Advanced Parsing/Writing + +{sub-ref}`lief-macho-parse` can take an extra {sub-ref}`lief-macho-parser-config` parameter to specify +parts of the Mach-O format to skip during parsing. + +:::{warning} +Generally, {sub-ref}`lief-macho-binary-write` and {sub-ref}`lief-macho-fatbinary-write` +require a **complete** initial parsing of the Mach-O file. +::: + +Similarly, {sub-ref}`lief-macho-binary-write` can also take an extra {sub-ref}`lief-macho-builder-config` +to specify which parts of the Mach-O should be rebuilt. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "advanced") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "advanced") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "advanced") }} +::: +:::: + +```{eval-rst} +.. seealso:: + + :ref:`binary-abstraction` + +``` + +(format-macho-dump)= + +## Dump Analysis + +LIEF has the support to process Mach-O memory dump with {sub-ref}`lief-macho-parse_from_dump`. This function +translates the file offsets referenced by the Mach-O structures into their location inside +the dump, using the base address passed as the second parameter. As for the regular parser, +it returns a {sub-ref}`lief-macho-fatbinary`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "dump") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "dump") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "dump") }} +::: +:::: + +:::{note} +The second parameter **must** be the (absolute) virtual address at which the +dump was mapped. It is used to convert the virtual addresses found in the +Mach-O structures back into an offset within the dump. +::: + +### Producing a dump with the runtime API + +Such a dump can be produced from a live process thanks to the LIEF +{ref}`runtime ` and, more precisely, the +{ref}`Module API `. {sub-ref}`lief-runtime-module-dump` captures the +memory of a loaded module (from its imagebase over its virtual size): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "dump-runtime") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "dump-runtime") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "dump-runtime") }} +::: +:::: + +(format-macho-rpath)= + +## RPath and Library Path Modification + +Sometimes, we need to modify the Mach-O RPath commands or the (absolute) path of +a linked library in an executable. When recompiling or linking the executable +is not possible, LIEF can be used for these modifications. + +For example, let's consider a binary with the following dependencies: + +```bash +$ otool -L hello.bin +hello: + /Users/romain/dev/libmylib.dylib (compatibility version 0.0.0, current version 0.0.0) + /usr/lib/libc++.1.dylib (compatibility version 1.0.0, current version 1700.255.0) + /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1345.100.2) +``` + +One can change the directory of `libmylib.dylib` with the following code: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "rpath-change-lib") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "rpath-change-lib") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "rpath-change-lib") }} +::: +:::: + +:::{note} +It is worth mentioning that LIEF doesn't impose restrictions on the length of modified library +paths. LIEF manages all internal modifications to support both longer and +shorter library paths. +::: + +This type of modification can be used in conjunction with the `@rpath` +feature of Mach-O binaries: + +1. We can add an extra `LC_RPATH` ({sub-ref}`lief-macho-rpath`) command to `hello.bin`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "rpath-add") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "rpath-add") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "rpath-add") }} +::: +:::: + +2. Then, we can change the library path of `libmylib.dylib` to include the RPath prefix: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/macho.py", "rpath-atrpath") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/macho.cpp", "rpath-atrpath") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/macho.rs", "rpath-atrpath") }} +::: +:::: + +## Objective-C Support + +If a Mach-O binary is compiled from Objective-C sources, it may contain +metadata represented by the {sub-ref}`lief-objc-metadata` object. + +This metadata can help understand the underlying structures of the binary, and +{ref}`LIEF Extended ` provides support for accessing this +information through {sub-ref}`lief-macho-binary-objc-metadata`. + +For more details, you can check the {ref}`Obj-C section `. + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/macho/python.md b/vendor/lief/doc/sphinx/formats/macho/python.md new file mode 100644 index 0000000..8a2f136 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/macho/python.md @@ -0,0 +1,782 @@ +# {fa}`brands fa-python` Python + +## Parser + +```{eval-rst} +.. autofunction:: lief.MachO.parse +``` + +```{eval-rst} +.. autoclass:: lief.MachO.ParserConfig +``` + +{{ literalinclude("../../../code/python/macho.py", "parse-config") }} + +______________________________________________________________________ + +## FatBinary + +```{eval-rst} +.. autoclass:: lief.MachO.FatBinary +``` + +______________________________________________________________________ + +(python-macho-binary-api-ref)= + +## Binary + +```{eval-rst} +.. autoclass:: lief.MachO.Binary +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. autoclass:: lief.MachO.Header +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.Section + :top-classes: lief._lief.Section + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.Section +``` + +______________________________________________________________________ + +## ThreadLocalVariables + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.ThreadLocalVariables + :top-classes: lief._lief.MachO.Section + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.ThreadLocalVariables +``` + +______________________________________________________________________ + +## SegmentCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.SegmentCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SegmentCommand +``` + +______________________________________________________________________ + +## LoadCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.LoadCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.LoadCommand +``` + +______________________________________________________________________ + +## DylibCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DylibCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DylibCommand + +``` + +______________________________________________________________________ + +## DylinkerCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DylinkerCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DylinkerCommand + +``` + +______________________________________________________________________ + +## UUIDCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.UUIDCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.UUIDCommand + +``` + +______________________________________________________________________ + +## MainCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.MainCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.MainCommand +``` + +______________________________________________________________________ + +## NoteCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.NoteCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.NoteCommand +``` + +______________________________________________________________________ + +## Symbol + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.Symbol + :top-classes: lief._lief.Symbol + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.Symbol +``` + +______________________________________________________________________ + +## Symbol Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DylinkerCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SymbolCommand +``` + +______________________________________________________________________ + +## Dynamic Symbol Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DynamicSymbolCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DynamicSymbolCommand +``` + +______________________________________________________________________ + +## Dyld Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DyldInfo + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DyldInfo +``` + +______________________________________________________________________ + +## Function starts + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.FunctionStarts + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.FunctionStarts +``` + +______________________________________________________________________ + +## Function Variants + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.FunctionVariants + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.FunctionVariants +``` + +______________________________________________________________________ + +## Function Variant Fixups + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.FunctionVariantFixups + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.FunctionVariantFixups +``` + +______________________________________________________________________ + +## Lazy Load Dylib Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.LazyLoadDylibInfo + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.LazyLoadDylibInfo +``` + +______________________________________________________________________ + +## Source Version + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.SourceVersion + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 + +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SourceVersion +``` + +______________________________________________________________________ + +## Version Min + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.VersionMin + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.VersionMin +``` + +______________________________________________________________________ + +## Routine + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.Routine + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.Routine +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.Relocation + :top-classes: lief._lief.Relocation + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.Relocation +``` + +______________________________________________________________________ + +## Relocation Object + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.RelocationObject + :top-classes: lief._lief.Relocation + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.RelocationObject +``` + +______________________________________________________________________ + +## Relocation Dyld + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.RelocationDyld + :top-classes: lief._lief.Relocation + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.RelocationDyld +``` + +______________________________________________________________________ + +## Relocation Fixup + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.RelocationFixup + :top-classes: lief._lief.Relocation + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.RelocationFixup +``` + +______________________________________________________________________ + +## Binding Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.BindingInfo + :top-classes: lief._lief.MachO.BindingInfo + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.BindingInfo +``` + +______________________________________________________________________ + +## Dyld Binding Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DyldBindingInfo + :top-classes: lief._lief.MachO.BindingInfo + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DyldBindingInfo +``` + +______________________________________________________________________ + +## Chained Binding Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.ChainedBindingInfo + :top-classes: lief._lief.MachO.BindingInfo + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.ChainedBindingInfo +``` + +______________________________________________________________________ + +## Export Info + +```{eval-rst} +.. autoclass:: lief.MachO.ExportInfo +``` + +______________________________________________________________________ + +## Thread Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.ThreadCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.ThreadCommand +``` + +______________________________________________________________________ + +## RPath Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.RPathCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.RPathCommand +``` + +______________________________________________________________________ + +## Code Signature + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.CodeSignature + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.CodeSignature +``` + +______________________________________________________________________ + +## Data In Code + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DataInCode + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DataInCode +``` + +______________________________________________________________________ + +## Data Code Entry + +```{eval-rst} +.. autoclass:: lief.MachO.DataCodeEntry +``` + +______________________________________________________________________ + +## Segment Split Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.SegmentSplitInfo + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SegmentSplitInfo +``` + +______________________________________________________________________ + +## Sub Framework + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.SubFramework + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SubFramework +``` + +______________________________________________________________________ + +## Sub Client + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.SubClient + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.SubClient +``` + +______________________________________________________________________ + +## Dyld Environment + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DyldEnvironment + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DyldEnvironment +``` + +______________________________________________________________________ + +## Encryption Info + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.EncryptionInfo + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.EncryptionInfo +``` + +______________________________________________________________________ + +## Build Version + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.BuildVersion + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.BuildVersion +``` + +______________________________________________________________________ + +## Build Tool Version + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.BuildToolVersion + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.BuildToolVersion +``` + +______________________________________________________________________ + +## Fileset Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.FilesetCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.FilesetCommand +``` + +______________________________________________________________________ + +## DyldChainedFixups Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DyldChainedFixups + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DyldChainedFixups +``` + +______________________________________________________________________ + +## DyldExportsTrie Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.DyldExportsTrie + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.DyldExportsTrie +``` + +______________________________________________________________________ + +## Code Signature Dir Command + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.CodeSignatureDir + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.CodeSignatureDir +``` + +______________________________________________________________________ + +## Two Level Hints + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.TwoLevelHints + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.TwoLevelHints +``` + +______________________________________________________________________ + +## Linker Optimization Hint + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.LinkerOptHint + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.LinkerOptHint +``` + +______________________________________________________________________ + +## UnknownCommand + +```{eval-rst} +.. lief-inheritance:: lief._lief.MachO.UnknownCommand + :top-classes: lief._lief.MachO.LoadCommand + :parts: 2 +``` + +```{eval-rst} +.. autoclass:: lief.MachO.UnknownCommand +``` + +______________________________________________________________________ + +## Stub + +```{eval-rst} +.. autoclass:: lief.MachO.Stub +``` + +______________________________________________________________________ + +## Builder + +```{eval-rst} +.. autoclass:: lief.MachO.Builder +``` + +______________________________________________________________________ + +## Utilities + +```{eval-rst} +.. autofunction:: lief.MachO.check_layout +``` + +______________________________________________________________________ + +## Enums + +### MACHO_TYPES + +```{eval-rst} +.. autoclass:: lief.MachO.MACHO_TYPES +``` + +______________________________________________________________________ + +### X86_RELOCATION + +```{eval-rst} +.. autoclass:: lief.MachO.X86_RELOCATION +``` + +______________________________________________________________________ + +### X86_64_RELOCATION + +```{eval-rst} +.. autoclass:: lief.MachO.X86_64_RELOCATION +``` + +______________________________________________________________________ + +### PPC_RELOCATION + +```{eval-rst} +.. autoclass:: lief.MachO.PPC_RELOCATION +``` + +______________________________________________________________________ + +### ARM_RELOCATION + +```{eval-rst} +.. autoclass:: lief.MachO.ARM_RELOCATION +``` + +______________________________________________________________________ + +### ARM64_RELOCATION + +```{eval-rst} +.. autoclass:: lief.MachO.ARM64_RELOCATION + +``` + +### DYLD_CHAINED_FORMAT + +```{eval-rst} +.. autoclass:: lief.MachO.DYLD_CHAINED_FORMAT +``` + +### DYLD_CHAINED_PTR_FORMAT + +```{eval-rst} +.. autoclass:: lief.MachO.DYLD_CHAINED_PTR_FORMAT +``` diff --git a/vendor/lief/doc/sphinx/formats/macho/rust.md b/vendor/lief/doc/sphinx/formats/macho/rust.md new file mode 100644 index 0000000..c3d9872 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/macho/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::macho` +::: diff --git a/vendor/lief/doc/sphinx/formats/pe.rst b/vendor/lief/doc/sphinx/formats/pe.rst deleted file mode 100644 index f06bf85..0000000 --- a/vendor/lief/doc/sphinx/formats/pe.rst +++ /dev/null @@ -1,55 +0,0 @@ -PE Format -========= - -In this part we won't describe PE format totally but some parts that are tricky. - - -Rebuilding Import Table ------------------------ - -When a PE binary uses external library, it usually has an import table stored in the .idata section. This table has the following structure: - -| - -.. image:: ../_static/iat4.png - :width: 465px - :height: 800px - :scale: 70% - :alt: alternate text - :align: center - -| - -The lookup table holds offset to imported function's name. In the example, we import functions `Sleep` and `GetTickCount` from the `kernel32.dll`. - -The address table is identical (in most cases) to the lookup table but at runtime it will hold the imported function's address. The first entry will hold the address of `Sleep` and the second one the address of `GetTickCount`. - -If the program need to call `Sleep` function the assembly code should look like this: - -.. code-block:: nasm - - call address_table[entry1] ; call to sleep - -When rebuilding binary in ``LIEF`` we don't patch at any moment the assembly code which is a strong constraint for rebuilding import table. As we don't know exact structure of import table in the original binary (address table could be before lookup table...). -` -The reconstructed import table is built in another section named ``.idata``. To keep a consistent binary we patch the original binary in the following way: - -Each entry in the address table is replaced with the address of the entry in the trampoline section. (see figure 2) - -| - -.. image:: ../_static/iat3.png - :width: 928px - :height: 1835px - :scale: 40% - :alt: alternate text - :align: center - -| - -So if we have a call to an imported function we will have the following sequence of instructions: - -.. code-block:: nasm - - call address_table_original[entry1] ; call to trampoline[0] - jmp *address_table[entry1] ; jump to Sleep address diff --git a/vendor/lief/doc/sphinx/formats/pe/cpp.md b/vendor/lief/doc/sphinx/formats/pe/cpp.md new file mode 100644 index 0000000..4a3a866 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/cpp.md @@ -0,0 +1,852 @@ +# {fa}`regular fa-file-code` C++ + +## Parser + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Parser +``` + +```{eval-rst} +.. doxygenstruct:: LIEF::PE::ParserConfig +``` + +______________________________________________________________________ + +## Binary + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Binary +``` + +______________________________________________________________________ + +## Dos Header + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DosHeader +``` + +______________________________________________________________________ + +## Header + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Header +``` + +______________________________________________________________________ + +## Optional Header + +```{eval-rst} +.. doxygenclass:: LIEF::PE::OptionalHeader +``` + +______________________________________________________________________ + +## Data Directory + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DataDirectory +``` + +______________________________________________________________________ + +## Section + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Section +``` + +______________________________________________________________________ + +## Import + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Import +``` + +______________________________________________________________________ + +## Import Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ImportEntry +``` + +______________________________________________________________________ + +## Delay Import + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DelayImport +``` + +______________________________________________________________________ + +## Delay Import Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DelayImportEntry +``` + +______________________________________________________________________ + +## TLS + +```{eval-rst} +.. doxygenclass:: LIEF::PE::TLS +``` + +______________________________________________________________________ + +## Debug + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Debug +``` + +______________________________________________________________________ + +## Code View + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CodeView +``` + +______________________________________________________________________ + +## Code View PDB + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CodeViewPDB +``` + +______________________________________________________________________ + +## Relocation + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Relocation + +``` + +______________________________________________________________________ + +## Relocation Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RelocationEntry + +``` + +______________________________________________________________________ + +## Export + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Export + +``` + +______________________________________________________________________ + +## Export Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ExportEntry + +``` + +______________________________________________________________________ + +## Signature + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Signature + +``` + +______________________________________________________________________ + +## Signature Attribute + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Attribute + +``` + +______________________________________________________________________ + +## Signature ContentType + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ContentType + +``` + +______________________________________________________________________ + +## Signature GenericType + +```{eval-rst} +.. doxygenclass:: LIEF::PE::GenericType + +``` + +______________________________________________________________________ + +## Signature MsSpcNestedSignature + +```{eval-rst} +.. doxygenclass:: LIEF::PE::MsSpcNestedSignature + +``` + +______________________________________________________________________ + +## Signature MsSpcStatementType + +```{eval-rst} +.. doxygenclass:: LIEF::PE::MsSpcStatementType + +``` + +______________________________________________________________________ + +## Signature PKCS9AtSequenceNumber + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PKCS9AtSequenceNumber + +``` + +______________________________________________________________________ + +## Signature PKCS9CounterSignature + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PKCS9CounterSignature + +``` + +______________________________________________________________________ + +## Signature PKCS9MessageDigest + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PKCS9MessageDigest + +``` + +______________________________________________________________________ + +## Signature PKCS9SigningTime + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PKCS9SigningTime + +``` + +______________________________________________________________________ + +## Signature SpcSpOpusInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::SpcSpOpusInfo + +``` + +______________________________________________________________________ + +## Signature SpcIndirectData + +```{eval-rst} +.. doxygenclass:: LIEF::PE::SpcIndirectData + +``` + +______________________________________________________________________ + +## Signature GenericContent + +```{eval-rst} +.. doxygenclass:: LIEF::PE::GenericContent + +``` + +______________________________________________________________________ + +## RsaInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RsaInfo + +``` + +______________________________________________________________________ + +## x509 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::x509 + +``` + +______________________________________________________________________ + +## ContentInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ContentInfo + +``` + +______________________________________________________________________ + +## SignerInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::SignerInfo + +``` + +______________________________________________________________________ + +## MsCounterSign + +```{eval-rst} +.. doxygenclass:: LIEF::PE::MsCounterSign +``` + +______________________________________________________________________ + +## PKCS9TSTInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PKCS9TSTInfo +``` + +______________________________________________________________________ + +## MsManifestBinaryID + +```{eval-rst} +.. doxygenclass:: LIEF::PE::MsManifestBinaryID +``` + +______________________________________________________________________ + +## SpcRelaxedPeMarkerCheck + +```{eval-rst} +.. doxygenclass:: LIEF::PE::SpcRelaxedPeMarkerCheck +``` + +______________________________________________________________________ + +## SigningCertificateV2 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::SigningCertificateV2 +``` + +______________________________________________________________________ + +## Builder + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Builder + +``` + +______________________________________________________________________ + +## Resources Manager + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourcesManager + +``` + +______________________________________________________________________ + +## Resource Node + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceNode + +``` + +______________________________________________________________________ + +## Resource Directory + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceDirectory + +``` + +______________________________________________________________________ + +## Resource Data + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceData +``` + +______________________________________________________________________ + +## Resource Icon + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceIcon +``` + +______________________________________________________________________ + +## Resource Dialog + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceDialog +``` + +______________________________________________________________________ + +## Resource Dialog -- Regular + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceDialogRegular +``` + +______________________________________________________________________ + +## Resource Dialog -- Extended + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceDialogExtended +``` + +______________________________________________________________________ + +## Resource Version + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceVersion +``` + +______________________________________________________________________ + +## Resource Var File Info + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceVarFileInfo +``` + +______________________________________________________________________ + +## Resource Var + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceVar +``` + +______________________________________________________________________ + +## Resource String File Info + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceStringFileInfo + +``` + +______________________________________________________________________ + +## Resource String Table + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceStringTable + +``` + +______________________________________________________________________ + +## Resource Accelerator + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ResourceAccelerator +``` + +______________________________________________________________________ + +## Rich Header + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RichHeader +``` + +______________________________________________________________________ + +## Rich Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RichEntry +``` + +______________________________________________________________________ + +## Code Integrity + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CodeIntegrity +``` + +______________________________________________________________________ + +## Pogo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Pogo +``` + +______________________________________________________________________ + +## Pogo Entry + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PogoEntry +``` + +______________________________________________________________________ + +## Repro + +```{eval-rst} +.. doxygenclass:: LIEF::PE::Repro +``` + +______________________________________________________________________ + +## PDBChecksum + +```{eval-rst} +.. doxygenclass:: LIEF::PE::PDBChecksum +``` + +______________________________________________________________________ + +## VCFeature + +```{eval-rst} +.. doxygenclass:: LIEF::PE::VCFeature +``` + +______________________________________________________________________ + +## ExDllCharacteristics + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ExDllCharacteristics +``` + +______________________________________________________________________ + +## Frame Pointer Omission (FPO) + +```{eval-rst} +.. doxygenclass:: LIEF::PE::FPO +``` + +______________________________________________________________________ + +## Exception Info + +```{eval-rst} +.. doxygenclass:: LIEF::PE::ExceptionInfo +``` + +______________________________________________________________________ + +## RuntimeFunctionX64 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RuntimeFunctionX64 +``` + +______________________________________________________________________ + +## unwind_x64 - Code + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::Code +``` + +______________________________________________________________________ + +## unwind_x64 - Alloc + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::Alloc +``` + +______________________________________________________________________ + +## unwind_x64 - PushNonVol + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::PushNonVol +``` + +______________________________________________________________________ + +## unwind_x64 - PushMachFrame + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::PushMachFrame +``` + +______________________________________________________________________ + +## unwind_x64 - SetFPReg + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::SetFPReg +``` + +______________________________________________________________________ + +## unwind_x64 - SaveNonVolatile + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::SaveNonVolatile +``` + +______________________________________________________________________ + +## unwind_x64 - SaveXMM128 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::SaveXMM128 +``` + +______________________________________________________________________ + +## unwind_x64 - Epilog + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::Epilog +``` + +______________________________________________________________________ + +## unwind_x64 - Spare + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_x64::Spare +``` + +______________________________________________________________________ + +## RuntimeFunctionAArch64 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::RuntimeFunctionAArch64 +``` + +## Runtime AArch64 (Packed) Function + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_aarch64::PackedFunction + +``` + +## Runtime AArch64 (UnpackedFunction) Function + +```{eval-rst} +.. doxygenclass:: LIEF::PE::unwind_aarch64::UnpackedFunction +``` + +______________________________________________________________________ + +## Load Configuration + +```{eval-rst} +.. doxygenclass:: LIEF::PE::LoadConfiguration +``` + +______________________________________________________________________ + +## CHPEMetadata + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CHPEMetadata +``` + +## CHPEMetadata (ARM64) + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CHPEMetadataARM64 +``` + +## CHPEMetadata (X86) + +```{eval-rst} +.. doxygenclass:: LIEF::PE::CHPEMetadataX86 +``` + +______________________________________________________________________ + +## DynamicRelocation + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicRelocation + +``` + +## DynamicRelocationV1 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicRelocationV1 +``` + +## DynamicRelocationV2 + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicRelocationV2 +``` + +______________________________________________________________________ + +## DynamicFixup + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixup + +``` + +## DynamicFixupControlTransfer + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixupControlTransfer +``` + +## DynamicFixupARM64Kernel + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixupARM64Kernel +``` + +## DynamicFixupARM64X + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixupARM64X +``` + +## DynamicFixupGeneric + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixupGeneric + +``` + +## DynamicFixupUnknown + +```{eval-rst} +.. doxygenclass:: LIEF::PE::DynamicFixupUnknown + +``` + +## FunctionOverride + +```{eval-rst} +.. doxygenclass:: LIEF::PE::FunctionOverride +``` + +## FunctionOverrideInfo + +```{eval-rst} +.. doxygenclass:: LIEF::PE::FunctionOverrideInfo +``` + +______________________________________________________________________ + +## EnclaveConfiguration + +```{eval-rst} +.. doxygenclass:: LIEF::PE::EnclaveConfiguration +``` + +______________________________________________________________________ + +## EnclaveImport + +```{eval-rst} +.. doxygenclass:: LIEF::PE::EnclaveImport +``` + +______________________________________________________________________ + +## Volatile Metadata + +```{eval-rst} +.. doxygenclass:: LIEF::PE::VolatileMetadata +``` + +______________________________________________________________________ + +## Utilities + +```{doxygenfunction} LIEF::PE::check_layout +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::get_type(std::string_view) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::get_type(const std::vector< uint8_t > &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::is_pe(std::string_view) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::is_pe(const std::vector< uint8_t > &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::get_imphash +``` + +```{eval-rst} +.. doxygenenum:: LIEF::PE::IMPHASH_MODE +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::resolve_ordinals +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::PE::oid_to_string +``` + +______________________________________________________________________ + +## Enums + +```{eval-rst} +.. doxygenenum:: LIEF::PE::PE_TYPE +``` + +```{eval-rst} +.. doxygenenum:: LIEF::PE::CODE_PAGES +``` + +```{eval-rst} +.. doxygenenum:: LIEF::PE::ALGORITHMS +``` + +```{eval-rst} +.. doxygenenum:: LIEF::PE::ACCELERATOR_CODES +``` diff --git a/vendor/lief/doc/sphinx/formats/pe/index.md b/vendor/lief/doc/sphinx/formats/pe/index.md new file mode 100644 index 0000000..382164d --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/index.md @@ -0,0 +1,224 @@ +(format-pe)= + +# {fa}`brands fa-windows` PE + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +```{eval-rst} +.. toctree:: + :caption:  Modifications + :maxdepth: 1 + + modifications/imports + modifications/resources + modifications/tls + modifications/debug + modifications/exports +``` + +## Introduction + +PE binaries can be parsed using the {sub-ref}`lief-pe-parse` function. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "parse", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "parse", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "parse") }} +::: +:::: + +:::{note} +In Python, you can also use the generic {py:func}`lief.parse`, which returns a +{class}`lief.PE.Binary` object. +::: + +With the parsed PE binary, you can use the {sub-ref}`lief-pe-binary` API to +inspect or modify the binary itself. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "inspect") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "inspect") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "inspect") }} +::: +:::: + +After modifying a {sub-ref}`lief-pe-binary` object, you can use {sub-ref}`lief-pe-binary-write` to +write the changes back to a raw PE file. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "add-section") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "add-section") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "add-section") }} +::: +:::: + +```{eval-rst} +.. seealso:: + + :ref:`binary-abstraction` + +``` + +(format-pe-dump)= + +## Dump Analysis + +LIEF has the support to process PE memory dump with {sub-ref}`lief-pe-parse_from_dump`. This function +translates the file offsets referenced by the PE structures into their location inside +the dump, using the base address passed as the second parameter: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "dump") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "dump") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "dump") }} +::: +:::: + +:::{note} +The second parameter **must** be the (absolute) virtual address at which the +dump was mapped. It is used to convert the RVAs found in the PE structures +back into an offset within the dump. +::: + +### Producing a dump with the runtime API + +Such a dump can be produced from a live process thanks to the LIEF +{ref}`runtime ` and, more precisely, the +{ref}`Module API `. {sub-ref}`lief-runtime-module-dump` captures the +memory of a loaded module (from its imagebase over its virtual size): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "dump-runtime") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "dump-runtime") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "dump-runtime") }} +::: +:::: + +## Advanced Parsing/Writing + +```{eval-rst} +.. toctree:: + :caption:  Modifications + :maxdepth: 1 + + modifications/imports + modifications/resources + modifications/tls +``` + +{sub-ref}`lief-pe-parse` can take an extra {sub-ref}`lief-pe-parser-config` parameter to specify +parts of the PE format to ignore during parsing. + +:::{warning} +Generally, {sub-ref}`lief-pe-binary-write` requires a **complete** initial +parsing of the PE file. +::: + +Similarly, {sub-ref}`lief-pe-binary-write` can take an extra {sub-ref}`lief-pe-builder-config` +parameter to include or ignore parts of the PE binary during the build +process. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "advanced") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "advanced") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "advanced") }} +::: +:::: + +You can also use {sub-ref}`lief-pe-binary-write_to_bytes` to get the new PE binary +as a buffer of bytes: + +:::{note} +This API can also take an extra {sub-ref}`lief-pe-builder-config` parameter. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "write-bytes") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "write-bytes") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "write-bytes") }} +::: +:::: + +## PDB Support + +Using {ref}`LIEF Extended `, you can access PDB debug information +({sub-ref}`lief-pdb-debug-info`) using the {sub-ref}`lief-pdb-binary-debug-info` function. + +For more details regarding PDB support, please refer to the +{ref}`PDB section `. + +## Authenticode + +LIEF supports PE Authenticode by providing an API for inspecting and +**verifying** PE executable signatures. + +PE Authenticode signatures can be accessed by iterating over +{sub-ref}`lief-pe-binary-signatures`. The {sub-ref}`lief-pe-binary-verify_signature` function can +be used to verify that a PE binary is correctly signed. + +:::{note} +Typically, a signed PE executable contains a single signature, but the +format allows for multiple signatures. Consequently, +{sub-ref}`lief-pe-binary-signatures` returns an iterator rather than a single +signature object. +::: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/pe.py", "authenticode") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/pe.cpp", "authenticode") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/pe.rs", "authenticode") }} +::: +:::: + +You can find additional details about Authenticode support in this tutorial: +{ref}`PE Authenticode ` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/pe/modifications/debug.md b/vendor/lief/doc/sphinx/formats/pe/modifications/debug.md new file mode 100644 index 0000000..d1913aa --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/modifications/debug.md @@ -0,0 +1,64 @@ +(pe_debug_modification)= + +# {fa}`solid fa-gears` Debug Modification + +LIEF can create, modify, or delete PE debug information entries. + +:::{figure} ../../../_static/pe_debug/overview.webp +:alt: PE Debug Overview +:scale: 50% +::: + +This debug information is located in the `IMAGE_DIRECTORY_ENTRY_DEBUG` and is +represented in LIEF through the {sub-ref}`lief-pe-debug` class. + +These entries can be modified using the API exposed by these structures. +For example, the PDB path referenced in a {sub-ref}`lief-pe-codeviewpdb` entry can be +changed as follows: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_debug.py", "change-name") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_debug.cpp", "change-name") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_debug.rs", "change-name") }} +::: +:::: + +The {sub-ref}`lief-pe-binary-remove-debug` function can be used to remove a specific +entry, whereas the {sub-ref}`lief-pe-binary-clear-debug` function removes **all** +debug entries: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_debug.py", "remove") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_debug.cpp", "remove") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_debug.rs", "remove") }} +::: +:::: + +Finally, {sub-ref}`lief-pe-binary-add-debug-info` can be used to add a crafted debug +entry to an existing PE. + +For example, a custom {sub-ref}`lief-pe-codeviewpdb` can be created as follows: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_debug.py", "add") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_debug.cpp", "add") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_debug.rs", "add") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/pe/modifications/exports.md b/vendor/lief/doc/sphinx/formats/pe/modifications/exports.md new file mode 100644 index 0000000..1b1acf8 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/modifications/exports.md @@ -0,0 +1,93 @@ +# {fa}`solid fa-gears` Exports Modification + +:::{figure} ../../../_static/pe_exports/overview.webp +:alt: PE Resources Overview +:scale: 50% +::: + +LIEF provides extensive support for modifying the PE export table, enabling you +to add, remove, or modify export entries, or create an entire export table for +a PE binary. + +This functionality requires enabling {sub-ref}`lief-pe-builder-config-exports`, as the +modified export table is **relocated** to a **new** section. The section name +can be controlled with {sub-ref}`lief-pe-builder-config-export_section`. + +## Creating Export Entries + +Creating a {sub-ref}`lief-pe-export-entry` is useful for exposing a "hidden" function by +its address, allowing it to be used like a standard linker-generated export. + +This could be used for code lifting or fuzzing. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_exports.py", "create-entries") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_exports.cpp", "create-entries") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_exports.rs", "create-entries") }} +::: +:::: + +## Creating an Export Table + +This section introduces the API for creating an export table. We'll explore a +scenario where we want to convert a PE executable into a DLL. + +:::{note} +The process of converting an executable to a library is also detailed for ELF +binaries in the tutorial: {ref}`tuto_elf_bin2lib`. +::: + +First, we must update the PE headers to ensure they are compliant with the DLL +format: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_exports.py", "dll-header") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_exports.cpp", "dll-header") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_exports.rs", "dll-header") }} +::: +:::: + +Then, we can start creating and populating a new export table: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_exports.py", "create-table") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_exports.cpp", "create-table") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_exports.rs", "create-table") }} +::: +:::: + +:::{admonition} Limitations +:class: tip + +This binary-to-library example assumes that the original executable was +compiled to be position-independent, meaning it contains relocations. +::: + +Within a Python environment, we can verify that `lib_exe2dll.dll` can be +loaded as a DLL and that we can call `cbk1` and `cbk2`: + +```python +import ctypes + +lib = ctypes.windll.LoadLibrary("lib_exe2dll.dll") + +assert lib.cbk1() >= 0 +assert lib.cbk2() >= 0 +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/pe/modifications/imports.md b/vendor/lief/doc/sphinx/formats/pe/modifications/imports.md new file mode 100644 index 0000000..c2682aa --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/modifications/imports.md @@ -0,0 +1,400 @@ +# {fa}`solid fa-gears` Imports Modification + +This section describes the different operations supported by LIEF to modify the +PE import table. Please note that any operation not mentioned on this page +should be considered unsupported or might lead to a corrupted binary. + +| Operation | Supported | +| ------------------------------------------------------------ | ----------------- | +| {ref}`Add new import ` | {fa-check}`check` | +| {ref}`Add an imported function ` | {fa-check}`check` | +| {ref}`Remove an import ` | {fa-check}`check` | +| {ref}`Remove an imported function ` | {fa-check}`check` | +| Extend original IAT | {xmark}`mark` | +| Extend original ILT | {fa-check}`check` | + +:::{admonition} Implementation Update +:class: note + +Compared to previous versions of LIEF, import table modification has been +completely redesigned to be more reliable when modifying or rebuilding +a PE binary. +::: + +(ref-imp-mod-intro)= + +## Introduction + +Modifying the PE import table generically and reliably can be challenging +due to its flexible layout and strong dependency on the assembly code. +To better understand these challenges and how LIEF addresses them, let's +start with the layout of the import table generated by the MSVC linker +(`link.exe`): + +(fig-msvc-layout)= + +:::{figure} ../../../_static/pe_imports/msvc_layout.webp +:alt: Import Table (MSVC Layout) +:scale: 50% + +Import Table Layout (`MSVC/link.exe`) +::: + +First, the import table is referenced by the {sub-ref}`lief-pe-datadirectory` +indexed by the `IMPORT_TABLE` value. +The RVA of this data directory points to the beginning of the raw structure +describing the import table, while the size of the data directory provides the +length of this table. +For each imported library (e.g., `kernel32.dll`), the import header references +three locations: + +1. Address (RVA) of the import **lookup** table (**ILT**) +2. RVA of the imported library name (e.g., RVA of the string `kernel32.dll`) +3. Address (RVA) of the import **address** table (**IAT**) + +The IAT and the ILT point to an array of integers (pointer width) ending with a +zero. In the on-disk PE binary, both tables are filled with an RVA referencing +the imported function name (or an ordinal value). + +For example, if the binary imports `kernel32.dll!GetCurrentProcess` and +`kernel32.dll!TerminateProcess`, we would have the following ILT/IAT: + +```cpp +uintptr_t IAT[3] = { + RVA("GetCurrentProcess"), + RVA("TerminateProcess"), + 0 +}; + +uintptr_t ILT[3] = { + RVA("GetCurrentProcess"), + RVA("TerminateProcess"), + 0 +}; +``` + +When Windows loads the binary and resolves its imports, it fills the **IAT** +with the **resolved addresses** of the imported functions: + +```diff + uintptr_t IAT[3] = { +- RVA("GetCurrentProcess"), +- RVA("TerminateProcess"), ++ 0x7ff7bfdb3f00, // GetCurrentProcess resolved address ++ 0x7ff7ceab4f00, // TerminateProcess resolved address + 0 + }; +``` + +On the other hand, the ILT is left unchanged when the binary is loaded +(according to Microsoft documentation). +While the import header references three RVAs, the PE format (and the Windows +loader) does not enforce any specific ordering between them. This means the +ILT can appear before the IAT or vice versa. + +Figure {ref}`fig-msvc-layout` shows the layout when linking a PE binary with +MSVC `link.exe`. As shown in this figure, the IATs come first, followed by the +import headers, then the ILT, and finally the strings (DLL names and imported +function names). + +This layout can vary depending on the linker used to generate the final PE file. +In Figure {ref}`fig-llvm-layout`, we can see that the IAT follows the ILT, +which is the default order for PE binaries generated by LLVM `ld-link.exe`. + +(fig-llvm-layout)= + +:::{figure} ../../../_static/pe_imports/llvm-link-layout.webp +:alt: Import Table (LLVM Layout) +:scale: 50% + +Import Table Layout (`LLVM/ld-link.exe`) +::: + +Since we cannot assume any predefined layout or ordering of import table +elements, we cannot safely recreate a new table at the same locations as the +original without risking overwriting important data. +Additionally, if we add new imports or imported functions, the modified import +table would no longer fit in the original location. + +To address these constraints, a generic solution involves relocating the import +table elsewhere within the binary. + +:::{admonition} Builder Config +:class: warning + +As this modification is not conservative (i.e., it impacts the layout of the +binary even if the import table remains unchanged), it must be explicitly +enabled using the builder's config attribute: {sub-ref}`lief-pe-builder-config-imports` +::: + +We can relocate the import headers, the ILTs, and the strings (DLL names and +import names), but we **cannot** relocate the IAT arbitrarily within the binary. +The import table informs the Windows loader about the functions required by the +program. When the loader resolves an imported function, its address is written +to the IAT, and the assembly code accesses this IAT using stubbing +instructions like these: + +```nasm +jmp [rip + #IAT_FIXUP]; // e.g. jmp *IAT[3]; +``` + +or + +```nasm +mov rax, [rip + #IAT_FIXUP]; +call rax; +``` + +If we relocate the IAT elsewhere in the binary without taking other factors into +account, the instructions referencing the IAT become invalid. + +Several solutions exist for this problem, one of which involves creating +trampolines between the original IAT and the new IAT location. This approach +was used in **former versions** of LIEF; you can read the blog post +[Washi's Injecting Code using Imported Functions into Native PE Files](https://blog.washi.dev/posts/import-patching/) +for more details. + +The new approach used by LIEF relocates most elements of the import table +(headers, ILTs, and strings) but keeps the original IATs **in their original +locations**. + +(fig-lief-import-table-relocation)= + +:::{figure} ../../../_static/pe_imports/lief-mod.webp +:alt: LIEF Import Table Relocation +:scale: 50% + +LIEF import table relocation +::: + +By keeping the original IATs in place, we avoid creating trampolines that +require generating assembly. However, this approach introduces constraints +on how imports can be modified. Specifically, we must ensure that the +untouched IAT remains consistent with the assembly code that uses it. + +(ref-remove-import)= + +## Removing Import + +You can remove an imported library using the {sub-ref}`lief-pe-binary-remove-import` +function, or remove all libraries with {sub-ref}`lief-pe-binary-remove-all-import`: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_imports.py", "remove-import") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_imports.cpp", "remove-import") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_imports.rs", "remove-import") }} +::: +:::: + +(ref-remove-import-entry)= + +## Removing an imported function + +To remove an imported function, use {sub-ref}`lief-pe-import-remove-entry` on an +{sub-ref}`lief-pe-import` instance. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_imports.py", "remove-import-entry") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_imports.cpp", "remove-import-entry") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_imports.rs", "remove-import-entry") }} +::: +:::: + +Since this operation removes an entry from the IAT, and we cannot shrink the +table without patching the assembly (or using trampolines), the workaround +involves replacing the removed entry with another existing entry. +For example, if we remove `IsDebuggerPresent` from `Kernel32.dll`, the IAT +changes as follows: + +```{eval-rst} + +:Before: + + .. code-block:: cpp + + // Import Address Table of Kernel32.dll + uintptr_t IAT[] = { + RVA("GetCurrentProcess"), + RVA("IsDebuggerPresent"), + RVA("TerminateProcess"), + 0 + }; + + +:After: + + .. code-block:: cpp + + // Import Address Table of Kernel32.dll + uintptr_t IAT[] = { + RVA("GetCurrentProcess"), + RVA("GetCurrentProcess"), + RVA("TerminateProcess"), + 0 + }; +``` + +:::{admonition} Implicit Operation +:class: tip + +LIEF **implicitly** performs this padding during the build process. +::: + +This works because we can reuse the IAT entry associated with the deleted +function as a placeholder for any other imported function. Windows allows +duplicate symbols for a given import, so duplicating an import is perfectly +valid and maintains the IAT's original length. + +(ref-add-imp)= + +## Creating a new import + +LIEF allows you to create and add new imports using the +{sub-ref}`lief-pe-binary-add-import` and {sub-ref}`lief-pe-import-add-entry` functions: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_imports.py", "add-import") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_imports.cpp", "add-import") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_imports.rs", "add-import") }} +::: +:::: + +As shown in Figure {ref}`fig-lief-import-table-relocation`, this modification +introduces a new IAT located near the relocated import table. This new IAT +contains values for the newly imported functions (`puts` in this example). +Consequently, the Windows loader will resolve the imported functions in this +table. + +When crafting new imports and adding functions, you may need to determine the +IAT address ({sub-ref}`lief-pe-importentry-iat-address`) associated with these new +functions. + +The new IAT containing user-created imports is generated during the LIEF write +operation. Notably, **there is no reliable way to determine the address of the +new IAT before the write operation**. + +To address this limitation and allow for modifications after the new IAT is +created, {sub-ref}`lief-pe-builder-config` accepts a callback via its +{sub-ref}`lief-pe-builder-config-resolved_iat_cbk` attribute: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_imports.py", "add-import-cbk", emphasize_lines="1-4,11") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_imports.cpp", "add-import-cbk", emphasize_lines="6-12") }} +::: +:::: + +:::{admonition} Rust Bindings +:class: warning + +This callback is not yet available in Rust. +::: + +:::{admonition} Nanobind Leaks +:class: warning + +Due to Python's reference counting, you might encounter Nanobind warnings +about leaked objects. You can disable these warnings using +{py:func}`lief.disable_leak_warning`. +::: + +The fourth parameter of this callback, `uint32_t RVA`, is the address in the +IAT where the address of the resolved function ({sub-ref}`lief-pe-importentry`) will be +stored by the loader. + +For example, these addresses can be traced as follows: + +```python +def iat_resolution_cbk(pe: lief.PE.Binary, imp: lief.PE.Import, + entry: lief.PE.ImportEntry, rva: int): + print(f"{imp.name}!{entry.name}: 0x{rva:010x}") + +# [...] +stdio = dll.add_import("api-ms-win-crt-stdio-l1-1-0.dll") + +stdio.add_entry("puts") +stdio.add_entry("__p__commode") +stdio.add_entry("_set_fmode") + +# [...] +``` + +Which can result in the following output: + +```text +api-ms-win-crt-stdio-l1-1-0.dll!puts: 0x000046c9e2 +api-ms-win-crt-stdio-l1-1-0.dll!__p__commode: 0x000046c9ea +api-ms-win-crt-stdio-l1-1-0.dll!_set_fmode: 0x000046c9f2 +``` + +Given this output, the IAT address of `puts` is at RVA `0x000046c9e2`. +This information can be used to patch sections that need this address: + +```python +def iat_resolution_cbk(pe: lief.PE.Binary, imp: lief.PE.Import, + entry: lief.PE.ImportEntry, rva: int): + code = pe.get_section(".injected") + patch(code, rva) +``` + +(ref-add-imp-func)= + +## Adding a new imported function + +LIEF can also be used to add a function to an **existing** import, but this +must be done carefully to avoid corrupting the binary. + +Since we cannot extend the original IAT of the import where we want to add +the new function, the workaround involves adding a new import with the **same +name** as the existing one and adding the function to this duplicate import. + +```text +// Original Import +* kernel32.dll + │ + ├── GetCurrentProcessId IAT[0] + │ + ├── GetCurrentThreadId IAT[1] + │ + └── GetModuleHandleW IAT[2] + +// Duplicated import +* kernel32.dll + │ + └── GetStartupInfoW NEW IAT[0] + │ + └────────-> New Import +``` + +The code is very similar to that in {ref}`ref-add-imp`. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_imports.py", "add-import-func") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_imports.cpp", "add-import-func") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_imports.rs", "add-import-func") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/formats/pe/modifications/resources.md b/vendor/lief/doc/sphinx/formats/pe/modifications/resources.md new file mode 100644 index 0000000..48aa8f0 --- /dev/null +++ b/vendor/lief/doc/sphinx/formats/pe/modifications/resources.md @@ -0,0 +1,108 @@ +# {fa}`solid fa-gears` Resources Modification + +:::{figure} ../../../_static/pe_rsrc/overview.webp +:alt: PE Resources Overview +:scale: 50% +::: + +LIEF allows you to modify (or create) PE resources at different levels: + +- Directly on the binary tree ({sub-ref}`lief-pe-resource-node`) +- Using the {sub-ref}`lief-pe-resource-manager`. + +## Binary Tree Modifications + +The resource root node can be accessed using the {sub-ref}`lief-pe-binary-resources` +function: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_resources.py", "access-root") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_resources.cpp", "access-root") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_resources.rs", "access-root") }} +::: +:::: + +From this {sub-ref}`lief-pe-resource-node` instance, you can use the +{sub-ref}`lief-pe-resource-node-add-child` or {sub-ref}`lief-pe-resource-node-remove-child` +functions to add or delete nodes: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../code/python/pe_resources.py", "add-child") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../code/cpp/pe_resources.cpp", "add-child") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../code/rust/src/pe_resources.rs", "add-child") }} +::: +:::: + +This low-level API can be used to modify the tree or change the data of a +specific node. + +:::{admonition} Pretty Printing +:class: tip + +You can also *print* a node to get a formatted representation of the +resource tree: + +{{ literalinclude("../../../../code/python/pe_resources.py", "pretty-print") }} + +```text +├── Directory ID: 0000 (0x0000) +│ ├── Directory ID: 0016 (0x0010) type: VERSION +│ │ └── Directory ID: 0001 (0x0001) +│ │ └── Data ID: 0000 (0x0000) Lang: 0x00 / Sublang: 0x00 length=772 (0x000304), offset: 0x1ca0 +│ │ ├── Hex: 04:03:34:00:00:00:56:00:53:00:5f:00:56:00:45:00:52:00:53:00 +│ │ └── Str: ..4...V.S._.V.E.R.S. +│ └── Directory ID: 0024 (0x0018) type: MANIFEST +│ └── Directory ID: 0001 (0x0001) +│ └── Data ID: 1033 (0x0409) Lang: 0x09 / Sublang: 0x01 length=1900 (0x00076c), offset: 0x1fa4 +│ ├── Hex: 3c:61:73:73:65:6d:62:6c:79:20:78:6d:6c:6e:73:3d:22:75:72:6e +│ └── Str: - int main(int argc, const char** argv) { - std::unique_ptr elf = LIEF::ELF::Parser::parse("/usr/bin/ls"); - std::unique_ptr pe = LIEF::PE::Parser::parse("C:\\Windows\\explorer.exe"); - std::unique_ptr macho = LIEF::MachO::Parser::parse("/usr/bin/ls"); - - std::unique_ptr oat = LIEF::OAT::Parser::parse("android.odex"); - std::unique_ptr dex = LIEF::DEX::Parser::parse("classes.dex"); - std::unique_ptr vdex = LIEF::VDEX::Parser::parse("classes.vdex"); - std::unique_ptr art = LIEF::ART::Parser::parse("boot.art"); - - std::cout << *elf << std::endl; - std::cout << *pe << std::endl; - std::cout << *macho << std::endl; - - std::cout << *oat << std::endl; - std::cout << *dex << std::endl; - std::cout << *vdex << std::endl; - std::cout << *art << std::endl; - } - - -C++ API documentation is available here: :ref:`cpp-api-ref` - -C --- - -.. code-block:: c - - #include - int main(int argc, const char** argv) { - - Elf_Binary_t* elf_binary = elf_parse("/usr/bin/ls"); - Pe_Binary_t* pe_binary = pe_parse("C:\\Windows\\explorer.exe"); - Macho_Binary_t** macho_binaries = macho_parse("/usr/bin/ls"); - - Pe_Section_t** pe_sections = pe_binary->sections; - Elf_Section_t** elf_sections = elf_binary->sections; - Macho_Section_t** macho_sections = macho_binaries[0]->sections; - - for (size_t i = 0; pe_sections[i] != NULL; ++i) { - printf("%s\n", pe_sections[i]->name) - } - - for (size_t i = 0; elf_sections[i] != NULL; ++i) { - printf("%s\n", elf_sections[i]->name) - } - - for (size_t i = 0; macho_sections[i] != NULL; ++i) { - printf("%s\n", macho_sections[i]->name) - } - - elf_binary_destroy(elf_binary); - pe_binary_destroy(pe_binary); - macho_binaries_destroy(macho_binaries); - } - - -C API documentation is available here: :ref:`c-api-ref` - - - - - - - - - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/index.md b/vendor/lief/doc/sphinx/index.md new file mode 100644 index 0000000..eef62aa --- /dev/null +++ b/vendor/lief/doc/sphinx/index.md @@ -0,0 +1,113 @@ +--- +description: LIEF documentation for parsing, inspecting, modifying, and writing ELF, PE, Mach-O, COFF, Android, and other executable formats in C++, Python, and Rust. +--- + +# LIEF Documentation + +LIEF is a cross-platform library for parsing, inspecting, modifying, and +writing executable formats. Explore guides, tutorials, and API references for +ELF, PE, Mach-O, COFF, Android formats, and more in C++, Python, and Rust. + +```{eval-rst} +.. toctree:: + :maxdepth: 2 + + intro + installation + compilation +``` + +```{eval-rst} +.. toctree:: + :caption:  Formats + :maxdepth: 2 + + formats/elf/index + formats/macho/index + formats/pe/index + formats/coff/index + formats/android/index +``` + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + api/binary_abstraction/index + api/utilities/index + api/error_handling/index + api/logging/index + api/cpp/index + api/rust/index + runtime/intro +``` + +```{eval-rst} +.. toctree:: + :caption:  LIEF Extended + :maxdepth: 1 + + extended/intro + extended/debug_info/index + extended/dwarf/index + extended/pdb/index + extended/objc/index + extended/dsc/index + extended/disassembler/index + extended/assembler/index +``` + +```{eval-rst} +.. toctree:: + :caption:  Plugins + :maxdepth: 1 + + plugins/ghidra/index + plugins/binaryninja/index +``` + +```{eval-rst} +.. toctree:: + :caption:  Tools + :maxdepth: 1 + + tools/lief-patchelf/index +``` + +```{eval-rst} +.. toctree:: + :caption:  Tutorials + :maxdepth: 1 + + tutorials/01_play_with_formats + tutorials/02_pe_from_scratch + tutorials/03_elf_change_symbols + tutorials/04_elf_hooking + tutorials/05_elf_infect_plt_got + tutorials/06_pe_hooking + tutorials/07_pe_resource + tutorials/08_elf_bin2lib + tutorials/09_frida_lief + tutorials/10_android_formats + tutorials/11_macho_modification + tutorials/12_elf_coredump + tutorials/13_pe_authenticode +``` + +```{eval-rst} +.. toctree:: + :caption:  Extra Information + :maxdepth: 1 + + references + changelog + +``` + +```{eval-rst} +.. toctree:: + :hidden: + + ai +``` diff --git a/vendor/lief/doc/sphinx/index.rst b/vendor/lief/doc/sphinx/index.rst deleted file mode 100644 index 8ab6ba8..0000000 --- a/vendor/lief/doc/sphinx/index.rst +++ /dev/null @@ -1,47 +0,0 @@ -Welcome to LIEF's documentation! -================================ - -.. toctree:: - :maxdepth: 2 - - intro - installation - getting_started - compilation - error_handling - -.. toctree:: - :caption: Tutorials - :maxdepth: 1 - - tutorials/01_play_with_formats - tutorials/02_pe_from_scratch - tutorials/03_elf_change_symbols - tutorials/04_elf_hooking - tutorials/05_elf_infect_plt_got - tutorials/06_pe_hooking - tutorials/07_pe_resource - tutorials/08_elf_bin2lib - tutorials/09_frida_lief - tutorials/10_android_formats - tutorials/11_macho_modification - tutorials/12_elf_coredump - tutorials/13_pe_authenticode - -.. toctree:: - :caption: API - :maxdepth: 1 - - api/python/index - api/cpp/index - api/c/index - -.. toctree:: - :caption: Extra Information - :maxdepth: 1 - - formats/index - references - changelog - - diff --git a/vendor/lief/doc/sphinx/installation.md b/vendor/lief/doc/sphinx/installation.md new file mode 100644 index 0000000..4dc6f35 --- /dev/null +++ b/vendor/lief/doc/sphinx/installation.md @@ -0,0 +1,175 @@ +# {fa}`solid fa-gears` Installation and Integration + +## {fa}`regular fa-file-code` SDK + +For each platform supported by LIEF, the SDK packages contain: + +- static and shared libraries +- headers +- compiled examples + +Nightly builds can be downloaded at: , +while official releases are available on the GitHub releases page: +. + +## {fa}`brands fa-python` Python + +Nightly Python wheels are uploaded to an S3 bucket for **each commit** on the +main branch. They can be installed using: + +```console +$ pip install [--user] --index-url https://lief.s3-website.fr-par.scw.cloud/latest lief +``` + +For tagged releases, the wheels are uploaded to PyPI and can be installed using: + +```console +$ pip install lief +``` + +You can also compile and install from source as follows: + +```console +$ git clone https://github.com/lief-project/LIEF +$ pip install LIEF/api/python +# Or pip+git: +$ pip install git+https://github.com/lief-project/LIEF.git#subdirectory=api/python +``` + +For more details about the compilation options, see the {ref}`compilation_ref` section. + +## {fa}`brands fa-rust` Rust + +You can add LIEF as a dependency in a Rust project as follows: + +```toml +# For nightly build +[dependencies] +lief = { git = "https://github.com/lief-project/LIEF", branch = "main" } + +# For a tagged release +[dependencies] +lief = "1.0.0" +``` + +You can find more details in the {ref}`Rust API section `. + +## CMake Integration + +There are several ways to integrate LIEF as a dependency into another project. +The following methods are listed in order of preference according to CMake best practices. +These snippets show basic examples; please refer to the official CMake documentation +for questions related to more complex project setups. + +### find_package() + +Using [CMake find_package()](https://cmake.org/cmake/help/latest/command/find_package.html): + +{{ literalinclude("../../examples/cmake/find_package/CMakeLists.txt", language="cmake", lines="5-12") }} + +To integrate this within a project: + +{{ literalinclude("../../examples/cmake/find_package/CMakeLists.txt", language="cmake", lines="13-") }} + +For the compilation: + +```{include} ../../examples/cmake/find_package/README.md +:start-line: 2 +``` + +A *full* example is available in the `examples/cmake/find_package` directory. + +### add_subdirectory() or FetchContent + +First, configure the options you want to use as defaults for the LIEF project: + +{{ literalinclude("../../examples/cmake/add_subdirectory/CMakeLists.txt", language="cmake", lines="7-19") }} + +Using [CMake add_subdirectory()](https://cmake.org/cmake/help/latest/command/add_subdirectory.html) +to add LIEF as a submodule from a source directory: + +{{ literalinclude("../../examples/cmake/add_subdirectory/CMakeLists.txt", language="cmake", lines="21-28") }} + +You can also use the +[CMake FetchContent module](https://cmake.org/cmake/help/latest/module/FetchContent.html) +to download or specify a LIEF source directory outside the current directory: + +{{ literalinclude("../../examples/cmake/add_subdirectory/CMakeLists.txt", language="cmake", lines="33-61") }} + +To integrate this within a project: + +{{ literalinclude("../../examples/cmake/add_subdirectory/CMakeLists.txt", language="cmake", lines="65-") }} + +For the compilation: + +```{include} ../../examples/cmake/add_subdirectory/README.md +:start-line: 2 +``` + +A *full* example is available in the `examples/cmake/add_subdirectory` directory. + +### External Project + +If you don't want to use LIEF as a submodule, +you can use [CMake External Project](https://cmake.org/cmake/help/latest/module/ExternalProject.html) +to set up your project as a [\*superbuild\*](https://www.kitware.com/cmake-superbuilds-git-submodules): + +{{ literalinclude("../../examples/cmake/external_project/CMakeLists.txt", language="cmake", lines="1-41") }} + +To integrate this with a main `HelloLIEF` project located in a subdirectory +(which looks exactly like the `find_package()` example shown earlier): + +{{ literalinclude("../../examples/cmake/external_project/CMakeLists.txt", language="cmake", lines="44-") }} + +For the compilation: + +```{include} ../../examples/cmake/external_project/README.md +:start-line: 2 +``` + +A *full* example is available in the `examples/cmake/external_project` directory. + +## Visual Studio Integration + +Given a pre-compiled version of the LIEF SDK (e.g., `LIEF-1.0.0-win64.zip`): + +```text +. +├── bin +│   ├── pe_reader.exe +│   └── vdex_reader.exe +├── include +│   └── LIEF +├── lib +│   ├── LIEF.dll +│   ├── LIEF.lib +│   └── pkgconfig +└── share + └── LIEF +``` + +Add the `include/` directory to the compiler search path: +`Configuration Properties > C/C++ > General > Additional Include Directories` +and include either `LIEF.lib` or `LIEF.dll` during the linking step: + +`Configuration Properties > Linker > Input > Additional Dependencies` + +:::{warning} +`LIEF.dll` is compiled with the `/MD` flag (`MultiThreadedDLL`), while +`LIEF.lib` is compiled with the `/MT` flag (`MultiThreaded`). + +If this configuration is not suitable for your project, you can compile LIEF +with your required runtime. +::: + +## Xcode Integration + +Similar to Visual Studio, you should configure the Xcode project to include +LIEF's `include/` and `lib/` directories: + +- `include/`: `Build Settings > Search Paths > Header Search Paths` +- `lib/`: `Build Settings > Search Paths > Library Search Paths` + +Then, you can add `libLIEF.a` or `libLIEF.dylib` to the list of libraries to link against: + +`Build Phases > Link Binary With Libraries` diff --git a/vendor/lief/doc/sphinx/installation.rst b/vendor/lief/doc/sphinx/installation.rst deleted file mode 100644 index 374e986..0000000 --- a/vendor/lief/doc/sphinx/installation.rst +++ /dev/null @@ -1,302 +0,0 @@ -Installation and Integration -============================ - -SDK ---- - -For each platform supported by LIEF there is an SDK that contains: - -* Static library -* Headers -* Examples - -Nightly build can be downloaded on: https://lief-project.github.io/packages/sdk while releases are available -on Github release page: https://github.com/lief-project/LIEF/releases. - -Python ------- - -.. _v10-label: - -Since 0.10.0 -************ - -To install nightly build (master): - -.. code-block:: console - - $ pip install [--user] --index-url https://lief-project.github.io/packages lief - -You can also directly download the Python wheel package on: https://lief-project.github.io/packages/lief - -.. note:: - - If you already installed a nightly version of LIEF you may need the flag: ``--no-cache-dir`` - - -To install **release** package - -.. code-block:: console - - $ pip install lief - -Release packages can be found on `PyPI `_ and the Github release page: https://github.com/lief-project/LIEF/releases - -Using ``setup.py``, one can build and install lief as follows: - -.. code-block:: console - - $ python ./setup.py [--user] install - -LIEF modules can also be parameterized using the following options: - -.. code-block:: console - - $ python ./setup.py --help - ... - - --lief-test Build and make tests - --ninja Use Ninja as build system - --sdk Build SDK package - --lief-no-json Disable JSON module - --lief-no-logging Disable logging module - --lief-no-elf Disable ELF module - --lief-no-pe Disable PE module - --lief-no-macho Disable Mach-O module - --lief-no-android Disable Android formats - --lief-no-art Disable ART module - --lief-no-vdex Disable VDEX module - --lief-no-oat Disable OAT module - --lief-no-dex Disable DEX module - -From 0.8.0 to 0.9.0 -******************* - -To install **release** package - - -.. code-block:: console - - $ pip install pylief-VERSION.zip - -Release packages can be found here: `Releases `_ - -Before 0.8.0 -************ - -To install the Python API (example with ``Python 3.5``): - -.. code-block:: console - - $ pip install lief-XX.YY.ZZ_py35.tar.gz - - -Visual Studio Integration -------------------------- - -The pre-built SDK is compiled in release configuration with the *Multi-threaded* runtime library. - -As example we compile the following snippet with Visual Studio 2015 - -.. code-block:: cpp - - #include "stdafx.h" - - #include - - int main() - { - std::unique_ptr pe_binary = LIEF::PE::Parser::parse("C:\\Windows\\explorer.exe"); - std::cout << *pe_binary << std::endl; - return 0; - } - -First the build type must be set to ``Release``: - -.. figure:: _static/windows_sdk/s1.png - :align: center - - Build type set to ``Release`` - - -Then we need to specify the location of the LIEF include directory: - -.. figure:: _static/windows_sdk/s2.png - :align: center - - LIEF include directory - -and the location of the ``LIEF.lib`` library: - - -.. figure:: _static/windows_sdk/s5.png - :align: center - - LIEF library - -As ``LIEF.lib`` was compiled with the ``\MT`` flag we have to set it: - -.. figure:: _static/windows_sdk/s3.png - :align: center - - *Multi-threaded* as runtime library - -LIEF makes use of ``and, or, not`` C++ keywords. As **MSVC** doesn't support these keywords by default, we need to add the special file ``iso646.h``: - -.. figure:: _static/windows_sdk/s4.png - :align: center - - Add ``iso646.h`` file - -XCode Integration ------------------ - -To integrate LIEF within a XCode project, one needs to follow these steps: - -First we create a new project: - -.. figure:: _static/xcode_integration/step1.png - :align: center - - New Project - -For this example we select a *Command Line Tool*: - -.. figure:: _static/xcode_integration/step2.png - :align: center - - Command Line Tool - - -.. figure:: _static/xcode_integration/step3.png - :align: center - - Project options - -Then we need to add the static library ``libLIEF.a`` or the shared one (``libLIEF.dylib``) - -.. figure:: _static/xcode_integration/step4.png - :align: center - - Project configuration - Build Phases - - -.. figure:: _static/xcode_integration/step5.png - :align: center - - Project configuration - Build Phases - - -.. figure:: _static/xcode_integration/step6.png - :align: center - - Project configuration - Build Phases - -In the `Build Settings - Search Paths` one needs to specify the paths to the **include directory** and to location of the LIEF libraries (``libLIEF.a`` and/or ``libLIEF.dylib``) - -.. figure:: _static/xcode_integration/step7.png - :align: center - - Libraries and Include search paths - -Once the new project configured we can use LIEF: - - -.. figure:: _static/xcode_integration/code.png - :align: center - - Source code - -and run it: - -.. figure:: _static/xcode_integration/result.png - :align: center - - Output - - -CMake Integration ------------------ - -There are a few ways to integrate LIEF as a dependency in another project. The different methods are listed in order of preference and CMake best practice. These listings are only to show basic examples. Please refer to the CMake documentation for questions related to more complex project setup. - - -find_package() -************** - -Using `CMake find_package() `_: - -.. literalinclude:: ../../examples/cmake/find_package/CMakeLists.txt - :language: cmake - :lines: 5-12 - -And now, to be integrated within a project: - -.. literalinclude:: ../../examples/cmake/find_package/CMakeLists.txt - :language: cmake - :lines: 13- - -For the compilation: - -.. include:: ../../examples/cmake/find_package/README.rst - :start-line: 3 - -A *full* example is available in the ``examples/cmake/find_package`` directory. - - -add_subdirectory() or FetchContent -********************************** - -First, set up the options you want to set as default for the LIEF project: - -.. literalinclude:: ../../examples/cmake/add_subdirectory/CMakeLists.txt - :language: cmake - :lines: 7-19 - -Using `CMake add_subdirectory() `_ to add a submodule LIEF source directory: - -.. literalinclude:: ../../examples/cmake/add_subdirectory/CMakeLists.txt - :language: cmake - :lines: 21-28 - -If we are using a CMake version greater than or equal to 3.11, we can use `CMake FetchContent module `_ to download or specify a LIEF source directory outside of the current directory: - -.. literalinclude:: ../../examples/cmake/add_subdirectory/CMakeLists.txt - :language: cmake - :lines: 33-61 - -And now, to be integrated within a project: - -.. literalinclude:: ../../examples/cmake/add_subdirectory/CMakeLists.txt - :language: cmake - :lines: 65- - -For the compilation: - -.. include:: ../../examples/cmake/add_subdirectory/README.rst - :start-line: 3 - -A *full* example is available in the ``examples/cmake/add_subdirectory`` directory. - - -External Project -**************** - -If you don't want to use LIEF as a submodule or upgrade to CMake 3.11, we can use `CMake External Project `_ to set up a project as a `*superbuild* `_: - -.. literalinclude:: ../../examples/cmake/external_project/CMakeLists.txt - :language: cmake - :lines: 1-41 - -And now, to be integrated with our main ``HelloLIEF`` project that is located in a subdirectory and looks exactly like the ``find_package()`` example shown earlier: - -.. literalinclude:: ../../examples/cmake/external_project/CMakeLists.txt - :language: cmake - :lines: 44- - -For the compilation: - -.. include:: ../../examples/cmake/external_project/README.rst - :start-line: 3 - -A *full* example is available in the ``examples/cmake/external_project`` directory. diff --git a/vendor/lief/doc/sphinx/intro.md b/vendor/lief/doc/sphinx/intro.md new file mode 100644 index 0000000..813c603 --- /dev/null +++ b/vendor/lief/doc/sphinx/intro.md @@ -0,0 +1,129 @@ +# {fa}`solid fa-door-open` Introduction + +The purpose of this project is to provide a cross-platform library to parse, +modify, and abstract the {ref}`ELF `, {ref}`PE `, and +{ref}`Mach-O ` formats. + +From a technical standpoint, the library is written in C++ with a C++17 public +interface and exposes bindings for Python and Rust. + +As a result, you can use LIEF through an idiomatic API in these languages: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../code/python/intro.py", "intro", prepend="import lief") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../code/cpp/intro.cpp", "intro", prepend="#include ") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../code/rust/src/intro.rs", "intro") }} +::: +:::: + +The project is also dedicated to providing comprehensive documentation and +maintaining strong development standards, including: + +- A test suite with code coverage and non-regression testing +- Address Sanitizer checks ([ASAN](https://clang.llvm.org/docs/AddressSanitizer.html)) +- Continuous Integration for testing and releasing packages +- Dockerization of various CI steps +- A comprehensive {ref}`changelog ` +- Nightly builds + +```{image} _static/elements.webp +:alt: LIEF Architecture +``` + +```{eval-rst} +| +``` + +To get started with LIEF's features, you can check the documentation for specific +formats: {ref}`ELF `, {ref}`PE `, or {ref}`Mach-O `. +Integrating LIEF into your project is also straightforward: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +**With pip** + +```{code-block} console +$ pip install lief +``` + +**Using a requirements.txt file** + +```{code-block} text +lief==1.0.0 +``` +::: +:::{tab} {fa}`regular fa-file-code` C++ +**Compiler command line** + +```{code-block} console +$ clang++ -lLIEF -I/include/ ... +``` + +**CMake** + +```{code-block} cmake +find_package(LIEF) + +target_link_libraries(my-project LIEF::LIEF) +``` +::: +:::{tab} {fa}`brands fa-rust` Rust +**Nightly version** + +```{code-block} toml +# For nightly build +[dependencies] +lief = { git = "https://github.com/lief-project/LIEF", branch = "main" } +``` + +**Released version** + +```{code-block} toml +# For a tagged release +[dependencies] +lief = "1.0.0" +``` +::: +:::: + +You can find additional content, including release notes, on the [LIEF blog](/blog/): + +- [LIEF 1.0.0 release info](/blog/2026-07-13-lief-1-0-0/) +- [LIEF 0.17.0 release info](/blog/2025-09-14-lief-0-17-0/) +- [LIEF 0.16.0 release info](/blog/2024-12-10-lief-0-16-0/) +- [LIEF 0.15.0 release info](/blog/2024-07-21-lief-0.15-0/) +- [LIEF 0.14.0 release info](/blog/2024-01-20-lief-0-14-0/) +- [LIEF 0.13.0 release info](/blog/2023-04-09-lief-0-13-0/) +- [LIEF 0.12.0 release info](/blog/2022-03-27-lief-v0-12-0/) +- [LIEF 0.11.1 release info](/blog/2021-02-22-lief-0-11-1/) +- [LIEF 0.11.0 release info](/blog/2021-01-19-lief-0-11-0/) +- [LIEF 0.9.0 release info](/blog/2018-06-11-lief-0-9-0/) + +Additional practical examples are available in the +[examples/](https://github.com/lief-project/LIEF/tree/main/examples) directory. + +## {fa}`cubes` Extended Version + +{ref}`LIEF Extended ` adds {ref}`PDB ` and +{ref}`DWARF ` analysis, {ref}`Objective-C metadata `, +{ref}`Dyld shared caches `, and +{ref}`assembly `/{ref}`disassembly `. + +## {fa}`solid fa-wand-magic-sparkles` Runtime + +The optional {ref}`runtime API ` inspects the process running LIEF: +its host, loaded modules, and memory. Start with the + +## {fa}`solid fa-book` Additional Documentation + +- {fa}`solid fa-book` [Doxygen](doxygen/) + +- {fa}`brands fa-rust` Rust documentation: + + - Stable: {sub-ref}`lief-rust-doc` + - Nightly: {sub-ref}`lief-rust-doc-nightly` diff --git a/vendor/lief/doc/sphinx/intro.rst b/vendor/lief/doc/sphinx/intro.rst deleted file mode 100644 index 3cc3513..0000000 --- a/vendor/lief/doc/sphinx/intro.rst +++ /dev/null @@ -1,30 +0,0 @@ - -Introduction -============ - -The purpose of this project is to provide a cross platform library which can parse, modify and abstract -``ELF``, ``PE``, ``MachO`` and Android formats. - -Main features: - -* Parser: LIEF can parse ``ELF``, ``PE``, ``MachO``, ``DEX``, ``OAT``, ``ART`` and ``VDEX``. - Moreover it provides an user-friendly API to access format internals. -* Modify: LIEF enables to modify **some** parts of these formats. -* Abstract: Usually formats have common features like sections, symbols, entry point... - LIEF tries to provide an abstraction over these characteristics. -* API: LIEF can be used in C++, Python and, to a lesser extent, in C - -The global architecture looks like this: - -.. image:: _static/architecture.png - :alt: LIEF Architecture - :align: center - -| - - -In the architecture, each format has its own *namespace*, parser and builder. -The parser takes a binary, library... as input and decomposes in LIEF object. -For instance, the ``ELF`` format has segments, so ``ELF::Parser`` will parse segments to create ``ELF::Segment``. -In the ``ELF::Binary`` class we will have a list of ``ELF::Segment`` which can be modified (change type, size, content...). -Then the ``ELF::Builder`` will transform ``ELF::Binary`` into a valid executable. diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after.svg new file mode 100644 index 0000000..1d129f1 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after.svg @@ -0,0 +1 @@ +   jint JNI_OnLoad(JavaVM* vm, void* reserved) 00401270  uint64_t x21 = _ReadMSR(tpidr_el0) 00401284  int64_t var_48 = *(x21 + 0x28) 0040129c  JNIEnv* env 0040129c  int32_t result 0040129c  bool cond:1 0040129c   0040129c  if ((*vm)->GetEnv(vm, &env, 0x10004) == 0) 004012a8      JNIEnv* env_1 = env 004012c0      void var_e0 004012c0      sub_401138(&data_400b5c, &var_e0, 0x41) 004012d4      JNINativeMethod var_90 0040129c  else 004012a0      result = -0x1f40 004012a0   diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after_java.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after_java.svg new file mode 100644 index 0000000..1cd6634 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/after_java.svg @@ -0,0 +1 @@ +   jbyteArray Java_com_bytedance_sdk_component_embedapplog_PangleEncryptUtils_ttEncrypt(JNIEnv* env,      jobject thiz, jbyteArray arg3, jsize arg4) 0000108c  uint64_t x26 = _ReadMSR(tpidr_el0) 00001090  int64_t x8 = *(x26 + 0x28) 00001094  jbyteArray result = nullptr 00001094   000010a8  if (arg3 != 0 && arg4 s>= 1) 000010b0      int128_t v0 = *"UK*@3oKpFlVVnads" 000010d4      __builtin_strncpy(&data_9830, "UK*@3oKpFlVVnadsTfdA", 0x14) 000010d8      jsize x0_1 = ss_encrypted_size(zx.q(arg4), v0) 000010e4      jbyte* x0_3 = malloc(zx.q(arg4)) 000010f0      jbyte* x0_5 = malloc(sx.q(x0_1)) 00001114      (*env)->GetByteArrayRegion(env, arg3, 0, arg4, x0_3) 00001114       00001138      if ((ss_encrypt(x0_3, zx.q(arg4), &data_9830, strlen(&data_9830), x0_5) & 0x80000000) 00001138              != 0) 00001190          result = nullptr 00001138      else 00001154          result = (*env)->NewByteArray(env, x0_1) 00001170          (*env)->SetByteArrayRegion(env, result, 0, x0_1, x0_5) 00001170           00001174          if (x0_3 != 0) 0000117c              free(x0_3) 0000117c           00001180          if (x0_5 != 0) 00001188              free(x0_5) 00001188   000011a0  if (*(x26 + 0x28) == x8) 000011c0      return result 000011c0   000011c4  __stack_chk_fail() 000011c4  noreturn \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before.svg new file mode 100644 index 0000000..d341847 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before.svg @@ -0,0 +1 @@ +   uint64_t JNI_OnLoad(int64_t* arg1) 00401270  uint64_t x21 = _ReadMSR(tpidr_el0) 00401284  int64_t var_48 = *(x21 + 0x28) 0040129c  int64_t* var_2d8 0040129c  uint64_t result 0040129c  bool cond:1 0040129c   0040129c  if ((*(*arg1 + 0x30))(arg1, &var_2d8, 0x10004) == 0) 004012a8      int64_t* x19_1 = var_2d8 004012c0      void var_e0 004012c0      sub_401138(&data_400b5c, &var_e0, 0x41) 004012d4      void* var_90 = &var_e0 0040129c  else 004012a0      result = 0xffffe0c0 004012a0   diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before_java.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before_java.svg new file mode 100644 index 0000000..828522d --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/img/before_java.svg @@ -0,0 +1 @@ +   int64_t Java_com_bytedance_sdk_component_embedapplog_PangleEncryptUtils_ttEncrypt(int64_t* arg1,      int64_t arg2, int64_t arg3, int32_t arg4) 0000108c  uint64_t x26 = _ReadMSR(tpidr_el0) 00001090  int64_t x8 = *(x26 + 0x28) 00001094  int64_t result = 0 00001094   000010a8  if (arg3 != 0 && arg4 s>= 1) 000010b0      int128_t v0 = *"UK*@3oKpFlVVnads" 000010d4      __builtin_strncpy(&data_9830, "UK*@3oKpFlVVnadsTfdA", 0x14) 000010d8      int32_t x0_1 = ss_encrypted_size(zx.q(arg4), v0) 000010e4      int64_t x0_3 = malloc(zx.q(arg4)) 000010f0      int64_t x0_5 = malloc(sx.q(x0_1)) 00001114      (*(*arg1 + 0x640))(arg1, arg3, 0, zx.q(arg4), x0_3)  {"ed_size"} 00001114       00001138      if ((ss_encrypt(x0_3, zx.q(arg4), &data_9830, strlen(&data_9830), x0_5) & 0x80000000) 00001138              != 0) 00001190          result = 0 00001138      else 00001154          result = (*(*arg1 + 0x580))(arg1, zx.q(x0_1)) 00001170          (*(*arg1 + 0x680))(arg1, result, 0, zx.q(x0_1), x0_5)  {"ptUtils_ttDecrypt"} 00001170           00001174          if (x0_3 != 0) 0000117c              free(x0_3) 0000117c           00001180          if (x0_5 != 0) 00001188              free(x0_5) 00001188   000011a0  if (*(x26 + 0x28) == x8) 000011c0      return result 000011c0   000011c4  __stack_chk_fail() 000011c4  noreturn \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/index.md new file mode 100644 index 0000000..299f378 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-jni/index.md @@ -0,0 +1,47 @@ +(plugins-binaryninja-analyzers-android-jni)= + +# {fa}`solid fa-object-ungroup` Android JNI + +This analyzer improves support for JNI functions in Android native +libraries. It works by providing a BinaryNinja type library `android-jni.bntl`, +which is placed next to the plugin's shared library: + +```text +. +├── lief-analysis-plugin-linux-x86_64.so +├── lief-dwarf-plugin-linux-x86_64.so +└── typelib + └── aarch64 + └── android-jni.bntl +``` + +This type library should be installed in one of the following locations: + +- **Linux:** `~/.binaryninja/typelib/aarch64/android-jni.bntl` +- **Windows:** `C:\Users\romain\AppData\Roaming\Binary Ninja\typelib\aarch64\android-jni.bntl` +- **macOS:** `~/Library/Application Support/Binary Ninja/typelib/aarch64/android-jni.bntl` + +After installation, select `Plugins > LIEF > Enhance Analysis`. The +plugin will then import all types related to Android JNI. + +In addition, it will automatically define the type for the `JNI_OnLoad` +function: + +```{eval-rst} +.. img-comparison:: + :left: img/before.svg + :right: img/after.svg +``` + +Functions tagged [^f1] with `"LIEF - Android JNI Function"` are also +updated to expose the correct type in the first two arguments: + +```{eval-rst} +.. img-comparison:: + :left: img/before_java.svg + :right: img/after_java.svg +``` + +{{ cross_api }} + +[^f1]: On a given function, right-click: `Tags and Bookmarks > Add Tag ... > LIEF - Android JNI Function` diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_after.svg new file mode 100644 index 0000000..1f6968b --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_after.svg @@ -0,0 +1,21 @@ + + + + + + + .rela.dyn section started  {0x40a950-0x40a9b6} +0040a950  char format[0x4] = "APS2" +0040a954  sleb128 nb_relocs = 0xb +0040a955  sleb128 reloc_offset = 0x0 +0040a956  sleb128 group_size = 0xb +0040a957  sleb128 group_flags = 0x8 +0040a958  sleb128 reloc_offset_0 = ... +0040a95b  ... +.rela.dyn section ended  {0x40a950-0x40a9b6} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_before.svg new file mode 100644 index 0000000..df7e07a --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/img/packed_before.svg @@ -0,0 +1,21 @@ + + + + + + + .rela.dyn section started  {0x40a950-0x40a9b6} +0040a950  41 50 53 32 0b 00 0b 08 88 b5 10 81 82 80 80 e0  APS2............ +0040a960  2f 00 e0 0c 81 88 80 80 a0 02 00 08 81 88 80 80  /............... +0040a970  c0 03 00 08 81 88 80 80 e0 3b 00 08 81 88 80 80  .........;...... +0040a980  80 3b 00 08 81 88 80 80 b0 31 00 08 81 88 80 80  .;.......1...... +0040a990  e0 2f 00 08 81 88 80 80 b0 15 00 08 81 88 80 80  ./.............. +0040a9a0  c0 08 00 80 c4 00 81 82 80 80 80 3b 00 88 13 81  ...........;.... +0040a9b0  82 80 80 b0 15 00                                ...... +.rela.dyn section ended  {0x40a950-0x40a9b6} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/index.md new file mode 100644 index 0000000..5c1dd57 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/android-packed-relocations/index.md @@ -0,0 +1,21 @@ +(plugins-binaryninja-analyzers-android-packed-relocations)= + +# {fa}`solid fa-object-ungroup` Android Packed Relocations + +This analyzer enhances the type definition of Android-specific relocation data +(`DT_ANDROID_RELA`) + +```{eval-rst} +.. img-comparison:: + :left: img/packed_before.svg + :right: img/packed_after.svg +``` + +:::{admonition} Relocation +:class: note + +Please note that the **processing** of these relocations is part of the +{ref}`Relocations ` analyzer. +::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/index.md new file mode 100644 index 0000000..f6e935c --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/index.md @@ -0,0 +1,14 @@ +(plugins-binaryninja-analyzer-elf)= + +# {fa}`brands fa-linux` ELF Analyzers + +```{eval-rst} +.. toctree:: + :caption:  ELF + :maxdepth: 1 + + android-packed-relocations/index + relative-relocations/index + relocations/index + android-jni/index +``` diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_after.svg new file mode 100644 index 0000000..6dc0688 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_after.svg @@ -0,0 +1,28 @@ + + + + + + + .relr.dyn section started  {0x40a9b8-0x40aa88} +0040a9b8  uintptr_t r_relr[0x1a] = +0040a9b8  { +0040a9b8      [0x00] =  0x0000000000040000 +0040a9c0      [0x01] =  0x5555555555555555 +0040a9c8      [0x02] =  0xc8dffffffffeaaab +0040a9d0      [0x03] =  0xaaaaaa9800191111 +0040a9d8      [0x04] =  0x5555555555555555 +0040a9e0      [0x05] =  0xaaaaaaaaaaaaaaab +0040a9e8      [0x06] =  0x5555555555555555 +0040a9f0      [0x07] =  0xaaaaaaaaaaaaaaab +0040a9f8      [0x08] =  0x5555555555555555 +0040aa00      [0x09] =  0xaaaaaaaaaaaaaaab +0040aa08      [0x0a] =  0x5555555555555555 +0040aa10      .... +.relr.dyn section ended  {0x40a9b8-0x40aa88} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_before.svg new file mode 100644 index 0000000..0835fbb --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/img/rel_before.svg @@ -0,0 +1,28 @@ + + + + + + + .relr.dyn section started  {0x40a9b8-0x40aa88} +0040a9b8                          00 00 04 00 00 00 00 00          ........ +0040a9c0  55 55 55 55 55 55 55 55 ab aa fe ff ff ff df c8  UUUUUUUU........ +0040a9d0  11 11 19 00 98 aa aa aa 55 55 55 55 55 55 55 55  ........UUUUUUUU +0040a9e0  ab aa aa aa aa aa aa aa 55 55 55 55 55 55 55 55  ........UUUUUUUU +0040a9f0  ab aa aa aa aa aa aa aa 55 55 55 55 55 55 55 55  ........UUUUUUUU +0040aa00  ab aa aa aa aa aa aa aa 55 55 55 55 55 55 55 55  ........UUUUUUUU +0040aa10  ab aa aa aa aa aa aa aa 55 55 55 55 55 55 55 55  ........UUUUUUUU +0040aa20  ab aa aa aa aa aa aa ea 55 55 55 ad 8a 00 54 55  ........UUU...TU +0040aa30  ab aa aa aa aa aa aa aa 55 55 d5 ff ff ff 00 00  ........UU...... +0040aa40  60 40 04 00 00 00 00 00 f1 42 10 80 90 18 01 00  `@.......B...... +0040aa50  11 21 00 50 b4 10 42 20 ff 70 fe 8c 38 00 a1 02  .!.P..B .p..8... +0040aa60  01 00 00 00 00 00 00 f1 37 00 71 00 42 95 7b 0f  ........7.q.B.{. +0040aa70  01 00 00 a0 77 00 1f 20 1d 00 50 c9 ff 01 00 00  ....w.. ..P..... +0040aa80  3d 00 00 00 00 00 00 00                          =....... +.relr.dyn section ended  {0x40a9b8-0x40aa88} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/index.md new file mode 100644 index 0000000..b6627ba --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relative-relocations/index.md @@ -0,0 +1,21 @@ +(plugins-binaryninja-analyzers-relative-relocations)= + +# {fa}`solid fa-object-ungroup` Relative Relocations + +This analyzer enhances the type definition of relative relocation data +(`DT_RELR`) + +```{eval-rst} +.. img-comparison:: + :left: img/rel_before.svg + :right: img/rel_after.svg +``` + +:::{admonition} Relocation +:class: note + +Please note that the **processing** of these relocations is part of the +{ref}`Relocations ` analyzer. +::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_after.svg new file mode 100644 index 0000000..c4b485e --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_after.svg @@ -0,0 +1,48 @@ + + + + + + + .fini_array section started  {0x441e40-0x441e98} +00441e40  void (* fini_array[0xb])() = +00441e40  { +00441e40      void (* fini_array)() = __on_dlclose_late +00441e48      void (* data_441e48)() = __on_dlclose +00441e50      void (* data_441e50)() = fib_lookup_exit +00441e58      void (* data_441e58)() = ctrl_exit +00441e60      void (* data_441e60)() = addr_exit +00441e68      void (* data_441e68)() = link_exit +00441e70      void (* data_441e70)() = macsec_exit +00441e78      void (* data_441e78)() = vlan_exit +00441e80      void (* data_441e80)() = route_exit +00441e88      void (* data_441e88)() = release_routing_table_names +00441e90      void (* data_441e90)() = release_proto_names +00441e98  } +.fini_array section ended  {0x441e40-0x441e98} + +.init_array section started  {0x441e98-0x441f08} +00441e98  void (* init_array[0xe])() = +00441e98  { +00441e98      void (* init_array)() = init_have_lse_atomics +00441ea0      void (* data_441ea0)() = __init_cpu_features +00441ea8      void (* data_441ea8)() = init_msg_size +00441eb0      void (* data_441eb0)() = init_default_cb +00441eb8      void (* data_441eb8)() = nl_debug_init +00441ec0      void (* data_441ec0)() = fib_lookup_init +00441ec8      void (* data_441ec8)() = ctrl_init +00441ed0      void (* data_441ed0)() = addr_init +00441ed8      void (* data_441ed8)() = link_init +00441ee0      void (* data_441ee0)() = macsec_init +00441ee8      void (* data_441ee8)() = vlan_init +00441ef0      void (* data_441ef0)() = route_init +00441ef8      void (* data_441ef8)() = init_routing_table_names +00441f00      void (* data_441f00)() = init_proto_names +00441f08  } +.init_array section ended  {0x441e98-0x441f08} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_before.svg new file mode 100644 index 0000000..392fe38 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/array_before.svg @@ -0,0 +1,48 @@ + + + + + + + .fini_array section started  {0x441e40-0x441e98} +00441e40  void (* fini_array[0xb])() = +00441e40  { +00441e40      [0x0] = 0x1c020 +00441e48      [0x1] = 0x1c000 +00441e50      [0x2] = 0x2bd80 +00441e58      [0x3] = 0x2c780 +00441e60      [0x4] = 0x2ef50 +00441e68      [0x5] = 0x32690 +00441e70      [0x6] = 0x34410 +00441e78      [0x7] = 0x38620 +00441e80      [0x8] = 0x3a600 +00441e88      [0x9] = 0x3d430 +00441e90      [0xa] = 0x3d530 +00441e98  } +.fini_array section ended  {0x441e40-0x441e98} + +.init_array section started  {0x441e98-0x441f08} +00441e98  void (* init_array[0xe])() = +00441e98  { +00441e98      [0x0] = 0x1c30c +00441ea0      [0x1] = 0x1c650 +00441ea8      [0x2] = 0x246f0 +00441eb0      [0x3] = 0x284c0 +00441eb8      [0x4] = 0x29810 +00441ec0      [0x5] = 0x2bd70 +00441ec8      [0x6] = 0x2c770 +00441ed0      [0x7] = 0x2ef40 +00441ed8      [0x8] = 0x32680 +00441ee0      [0x9] = 0x34400 +00441ee8      [0xa] = 0x38610 +00441ef0      [0xb] = 0x3a5f0 +00441ef8      [0xc] = 0x3d3a0 +00441f00      [0xd] = 0x3d4a0 +00441f08  } +.init_array section ended  {0x441e98-0x441f08} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_after.svg new file mode 100644 index 0000000..71826f2 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_after.svg @@ -0,0 +1,22 @@ + + + + + + + .data.rel.ro (PROGBITS) section started  {0x421010-0x422310} +00421020  void* data_421038 = 0x0 +00421028  void* data_421028 = android::Choreographer::~Choreographer() +00421030  void* data_421030 = android::Choreographer::~Choreographer() +00421038  void* data_421038 = 0x0 +00421040  void* data_421040 = android::Choreographer::dispatchVsync(int64_t, uint64_t, uint32_t) +00421048  void* data_421048 = android::Choreographer::dispatchHotplug(int64_t, uint64_t, bool) +00421050  void* data_421050 = android::Choreographer::dispatchHotplug(int64_t, uint64_t, bool) +00421058  void* data_421058 = android::Choreographer::handleMessage(android::Message const&) +.data.rel.ro (PROGBITS) section ended  {0x421010-0x422310} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_before.svg new file mode 100644 index 0000000..df21d79 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/img/data_relro_before.svg @@ -0,0 +1,22 @@ + + + + + + + .data.rel.ro (PROGBITS) section started  {0x421010-0x422310} +00421020  00 00 00 00 00 00 00 00 6c 2c 01 00 00 00 00 00  ........l,...... +00421030  98 2c 01 00 00 00 00 00 00 00 00 00 00 00 00 00  .,.............. +00421040  d4 28 01 00 00 00 00 00 fc 2a 01 00 00 00 00 00  .(.......*...... +00421050  fc 2a 01 00 00 00 00 00 00 2b 01 00 00 00 00 00  .*.......+...... +00421060  60 00 00 00 00 00 00 00 d8 ff ff ff ff ff ff ff  `............... +00421070  00 00 00 00 00 00 00 00 cc 2c 01 00 00 00 00 00  .........,...... +00421080  fc 2c 01 00 00 00 00 00 78 2b 01 00 00 00 00 00  .,......x+...... +00421090  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................ +.data.rel.ro (PROGBITS) section ended  {0x421010-0x422310} + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/index.md new file mode 100644 index 0000000..f44644c --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/elf/relocations/index.md @@ -0,0 +1,35 @@ +(plugins-binaryninja-analyzers-relocations)= + +# {fa}`solid fa-object-ungroup` Relocations + +This analyzer enhances support for binaries that use recent relocation formats +not recognized by BinaryNinja (e.g., `DT_ANDROID_RELA`, `DT_RELR`). + +For instance, here is LIEF-based processing of `DT_ANDROID_RELA` +relocations: + +```{eval-rst} +.. img-comparison:: + :left: img/array_before.svg + :right: img/array_after.svg + +``` + +Here is one for `DT_RELR` relocations: + +```{eval-rst} +.. img-comparison:: + :left: img/data_relro_before.svg + :right: img/data_relro_after.svg +``` + +```{eval-rst} +.. toctree:: + :caption:  See also + :maxdepth: 1 + + ../android-packed-relocations/index + ../relative-relocations/index +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_after.svg new file mode 100644 index 0000000..1023f6c --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_after.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_before.svg new file mode 100644 index 0000000..803ad9c --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/featmap_before.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_after.svg new file mode 100644 index 0000000..fc9973d --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_after.svg @@ -0,0 +1,34 @@ + + + + + + + .pdata section started  {0x140017000-0x140017d50} +140017000  struct _LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY __arm64_runtime_function_entry = +140017000  { +140017000      uint32_t BeginAddress = 0x1000 +140017004      uint32_t UnwindData = 0x12740 +140017008  } +140017008  struct _LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY __arm64_runtime_function_entry = +140017008  { +140017008      uint32_t BeginAddress = 0x1020 +14001700c      uint32_t UnwindData = 0x1274c +140017010  } +140017010  struct _LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY __arm64_runtime_function_entry = +140017010  { +140017010      uint32_t BeginAddress = 0x1060 +140017014      uint32_t UnwindData = 0x1275c +140017018  } +140017018  struct _LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY __arm64_runtime_function_entry = +140017018  { +140017018      uint32_t BeginAddress = 0x1080 +14001701c      uint32_t UnwindData = 0x1276c +140017020  } +140017020  struct _LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY __arm64_runtime_function_entry = + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_before.svg new file mode 100644 index 0000000..7f26d94 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/pdata_before.svg @@ -0,0 +1,33 @@ + + + + + + + .pdata section started  {0x140017000-0x140017d50} +140017000  00 10 00 00 40 27 01 00 20 10 00 00 4c 27 01 00  ....@'.. ...L'.. +140017010  60 10 00 00 5c 27 01 00 80 10 00 00 6c 27 01 00  `...\'......l'.. +140017020  e0 10 00 00 18 29 01 00 00 11 00 00 c0 2a 01 00  .....).......*.. +140017030  18 11 00 00 cc 2a 01 00 50 11 00 00 e4 2c 01 00  .....*..P....,.. +140017040  80 11 00 00 ec 2c 01 00 00 12 00 00 f4 2c 01 00  .....,.......,.. +140017050  80 12 00 00 fc 2c 01 00 00 13 00 00 04 2d 01 00  .....,.......-.. +140017060  80 13 00 00 0c 2d 01 00 f0 13 00 00 14 2d 01 00  .....-.......-.. +140017070  60 14 00 00 1c 2d 01 00 d0 14 00 00 24 2d 01 00  `....-......$-.. +140017080  40 15 00 00 2c 2d 01 00 b0 15 00 00 34 2d 01 00  @...,-......4-.. +140017090  20 16 00 00 3c 2d 01 00 90 16 00 00 44 2d 01 00   ...<-......D-.. +1400170a0  00 17 00 00 4c 2d 01 00 50 17 00 00 54 2d 01 00  ....L-..P...T-.. +1400170b0  a0 17 00 00 5c 2d 01 00 f0 17 00 00 64 2d 01 00  ....\-......d-.. +1400170c0  40 18 00 00 6c 2d 01 00 b0 18 00 00 74 2d 01 00  @...l-......t-.. +1400170d0  20 19 00 00 7c 2d 01 00 90 19 00 00 84 2d 01 00   ...|-.......-.. +1400170e0  00 1a 00 00 8c 2d 01 00 70 1a 00 00 94 2d 01 00  .....-..p....-.. +1400170f0  e0 1a 00 00 9c 2d 01 00 50 1b 00 00 a4 2d 01 00  .....-..P....-.. +140017100  c0 1b 00 00 ac 2d 01 00 30 1c 00 00 b4 2d 01 00  .....-..0....-.. +140017110  a0 1c 00 00 bc 2d 01 00 10 1d 00 00 c4 2d 01 00  .....-.......-.. +140017120  80 1d 00 00 cc 2d 01 00 d0 1d 00 00 d4 2d 01 00  .....-.......-.. +140017130  20 1e 00 00 dc 2d 01 00 70 1e 00 00 e4 2d 01 00   ....-..p....-.. + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_after.svg new file mode 100644 index 0000000..77f03d2 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_after.svg @@ -0,0 +1,42 @@ + + + + + + + .rdata section started  {0x140010000-0x1400152d8} +140012710  struct LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA __arm64_runtime_function_entry_xdata = +140012710  { +140012710      uint32_t HeaderData = 0x820000b +140012714  } +140012714  uint8_t __arm64_unwind_code[0x4] = +140012714  { +140012714      [0x0] =  0x81 +140012715      [0x1] =  0xe4 +140012716      [0x2] =  0xe3 +140012717      [0x3] =  0xe3 +140012718  } +140012718  struct LIEF_IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA __arm64_runtime_function_entry_xdata = +140012718  { +140012718      uint32_t HeaderData = 0x40400014 +14001271c  } +14001271c  uint32_t __arm64_epilog_scopes[0x1] = +14001271c  { +14001271c      [0x0] =  0x02c0000a +140012720  } +140012720  uint8_t __arm64_unwind_code[0x20] = +140012720  { +140012720      [0x00] =  0xe1 +140012721      [0x01] =  0x81 +140012722      [0x02] =  0xe6 +140012723      [0x03] =  0xe6 +140012724      [0x04] =  0xe6 +140012725      [0x05] =  0xe6 +               [....] +140012740  } + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_before.svg new file mode 100644 index 0000000..812de38 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/img/rdata_before.svg @@ -0,0 +1,17 @@ + + + + + + + .rdata section started  {0x140010000-0x1400152d8} +140012710  0b 00 20 08 81 e4 e3 e3 14 00 40 40 0a 00 c0 02  .. .......@@.... +140012720  e1 81 e6 e6 e6 e6 e7 66 89 fc e4 81 e7 4e 88 e7  .......f.....N.. +140012730  4c 86 e7 4a 84 e7 48 82 e7 66 89 fc e3 e3 e4 e3  L..J..H..f...... +140012740  06 00 40 08 05 00 80 00 01 e4 e4 00 0b 00 40 10  ..@...........@. + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/index.md new file mode 100644 index 0000000..5307646 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/exceptions-analyzer/index.md @@ -0,0 +1,40 @@ +(plugins-binaryninja-analyzers-exceptions)= + +# {fa}`solid fa-object-ungroup` Exceptions + +This analyzer improves the representation and underlying data of PE exceptions +metadata, primarily for ARM64 and ARM64EC binaries. + +```{eval-rst} +.. img-comparison:: + :left: img/pdata_before.svg + :right: img/pdata_after.svg +``` + +```{raw} html +
+``` + +```{eval-rst} +.. img-comparison:: + :left: img/rdata_before.svg + :right: img/rdata_after.svg +``` + +Additionally, it defines functions automatically based on the metadata of exceptions. +This results in a more accurate representation of the binary, as illustrated in this feature map: + +```{eval-rst} +.. img-comparison:: + :left: img/featmap_before.svg + :right: img/featmap_after.svg +``` + +```{eval-rst} +.. seealso:: + + See also this blog post: https://lief.re/blog/2025-02-16-arm64ec-pe-support/#binaryninja-arm64ec-support + +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/index.md new file mode 100644 index 0000000..3828d54 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/index.md @@ -0,0 +1,12 @@ +(plugins-binaryninja-analyzer-pe)= + +# {fa}`brands fa-windows` PE Analyzers + +```{eval-rst} +.. toctree:: + :caption:  PE + :maxdepth: 1 + + loadconfig-analyzer/index + exceptions-analyzer/index +``` diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_after.svg new file mode 100644 index 0000000..d0a3f13 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_after.svg @@ -0,0 +1,40 @@ + + + + + + + 1400111e8  char const data_1400111e8[0xe] = "Hello World!\n", 0 +1400111f6                                                                    00 00                                                .. +1400111f8  struct _LIEF_IMAGE_ARM64EC_METADATA_V2 __image_arm64ec_metadata = +1400111f8  { +1400111f8      uint32_t Version = 0x2 +1400111fc      uint32_t CodeMap = 0x11e00 +140011200      uint32_t CodeMapCount = 0x2 +140011204      uint32_t CodeRangesToEntryPoints = 0x11cb4 +140011208      uint32_t RedirectionMetadata = 0x19000 +14001120c      uint32_t __os_arm64x_dispatch_call_no_redirect = 0x11000 +140011210      uint32_t __os_arm64x_dispatch_ret = 0x11008 +140011214      uint32_t __os_arm64x_dispatch_call = 0x11018 +140011218      uint32_t __os_arm64x_dispatch_icall = 0x11010 +14001121c      uint32_t __os_arm64x_dispatch_icall_cfg = 0x11020 +140011220      uint32_t AlternateEntryPoint = 0x0 +140011224      uint32_t AuxiliaryIAT = 0x15000 +140011228      uint32_t CodeRangesToEntryPointsCount = 0x1 +14001122c      uint32_t RedirectionMetadataCount = 0x1 +140011230      uint32_t GetX64InformationFunctionPointer = 0x11028 +140011234      uint32_t SetX64InformationFunctionPointer = 0x11030 +140011238      uint32_t ExtraRFETable = 0x17000 +14001123c      uint32_t ExtraRFETableSize = 0xd38 +140011240      uint32_t __os_arm64x_dispatch_fptr = 0x11038 +140011244      uint32_t AuxiliaryIATCopy = 0x13e48 +140011248      uint32_t AuxDelayloadIAT = 0x0 +14001124c      uint32_t AuxDelayloadIATCopy = 0x0 +140011250      uint32_t ReservedBitField = 0x0 +140011254  } + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_before.svg new file mode 100644 index 0000000..613b5e5 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/chpe_metadata_before.svg @@ -0,0 +1,17 @@ + + + + + + + 1400111e0  00 00 00 00 01 00 00 00 48 65 6c 6c 6f 20 57 6f 72 6c 64 21 0a 00 00 00 02 00 00 00 00 1e 01 00  ........Hello World!............ +140011200  02 00 00 00 b4 1c 01 00 00 90 01 00 00 10 01 00 08 10 01 00 18 10 01 00 10 10 01 00 20 10 01 00  ............................ ... +140011220  00 00 00 00 00 50 01 00 01 00 00 00 01 00 00 00 28 10 01 00 30 10 01 00 00 70 01 00 38 0d 00 00  .....P..........(...0....p..8... +140011240  38 10 01 00 48 3e 01 00 00 00 00 00 00 00 00 00 00 00 00 00 40 10 01 00 48 10 01 00 50 10 01 00  8...H>..............@...H...P... +140011260  58 10 01 00 60 10 01 00 68 10 01 00 00 00 00 00                                                  X...`...h....... + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_after.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_after.svg new file mode 100644 index 0000000..4fcf5de --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_after.svg @@ -0,0 +1,70 @@ + + + + + + + 140011b20  struct _LIEF_IMAGE_LOAD_CONFIG_DIRECTORY64 __load_configuration_directory_table = +140011b20  { +140011b20      uint32_t Size = 0x140 +140011b24      uint32_t TimeDateStamp = 0x0 +140011b28      uint16_t MajorVersion = 0x0 +140011b2a      uint16_t MinorVersion = 0x0 +140011b2c      uint32_t GlobalFlagsClear = 0x0 +140011b30      uint32_t GlobalFlagsSet = 0x0 +140011b34      uint32_t CriticalSectionDefaultTimeout = 0x0 +140011b38      uintptr_t DeCommitFreeBlockThreshold = 0x0 +140011b40      uintptr_t DeCommitTotalFreeThreshold = 0x0 +140011b48      void* LockPrefixTable = 0x0 +140011b50      uintptr_t MaximumAllocationSize = 0x0 +140011b58      uintptr_t VirtualMemoryThreshold = 0x0 +140011b60      uintptr_t ProcessHeapFlags = 0x0 +140011b68      uint32_t ProcessAffinityMask = 0x0 +140011b6c      uint16_t CSDVersion = 0x0 +140011b6e      uint16_t DependentLoadFlags = 0x0 +140011b70      void* EditList = 0x0 +140011b78      void* SecurityCookie = __security_cookie +140011b80      uintptr_t* SEHandlerTable = 0x0 +140011b88      uintptr_t SEHandlerCount = 0x0 +140011b90      void (** GuardCFCheckFunctionPointer)() = __guard_check_icall_fptr +140011b98      void (** GuardCFDispatchFunctionPointer)() = __guard_dispatch_icall_fptr +140011ba0      uint32_t* SEHandlerTable = 0x0 +140011ba8      uintptr_t GuardCFFunctionCount = 0x0 +140011bb0      enum GuardFlags = IMAGE_GUARD_CF_INSTRUMENTED +140011bb4      struct CodeIntegrity = +140011bb4      { +140011bb4          uint16_t Flags = 0x0 +140011bb6          uint16_t Catalog = 0x0 +140011bb8          uint32_t CatalogOffset = 0x0 +140011bbc          uint32_t Reserved = 0x0 +140011bc0      } +140011bc0      void* GuardAddressTakenIatEntryTable = 0x0 +140011bc8      uintptr_t GuardAddressTakenIatEntryCount = 0x0 +140011bd0      void* GuardLongJumpTargetTable = 0x0 +140011bd8      uintptr_t GuardLongJumpTargetCount = 0x0 +140011be0      void* DynamicValueRelocTable = 0x0 +140011be8      struct _LIEF_IMAGE_ARM64EC_METADATA_V2* const CHPEMetadataPointer = __image_arm64ec_metadata +140011bf0      void (** GuardRFFailureRoutine)() = 0x0 +140011bf8      void (** GuardRFFailureRoutineFunctionPointer)() = 0x0 +140011c00      uint32_t DynamicValueRelocTableOffset = 0x0 +140011c04      uint16_t DynamicValueRelocTableSection = 0x0 +140011c06      uint16_t Reserved2 = 0x0 +140011c08      void (** GuardRFVerifyStackPointerFunctionPointer)() = 0x0 +140011c10      uint32_t HotPatchTableOffset = 0x0 +140011c14      uint32_t Reserved3 = 0x0 +140011c18      void* EnclaveConfigurationPointer = 0x0 +140011c20      void* VolatileMetadataPointer = 0x0 +140011c28      void* GuardEHContinuationTable = 0x0 +140011c30      void* GuardEHContinuationCount = 0x0 +140011c38      void (** GuardXFGCheckFunctionPointer)() = data_140011078 +140011c40      void (** GuardXFGDispatchFunctionPointer)() = data_140011088 +140011c48      void (** GuardXFGTableDispatchFunctionPointer)() = data_140011090 +140011c50      void (** CastGuardOsDeterminedFailureMode)() = 0x140011098 +140011c58      void (** GuardMemcpyFunctionPointer)() = data_1400110a0 +140011c60  } + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_before.svg b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_before.svg new file mode 100644 index 0000000..5543785 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/img/loadconfig_before.svg @@ -0,0 +1,65 @@ + + + + + + + 140011b20  struct Load_Configuration_Directory_Table __load_configuration_directory_table = +140011b20  { +140011b20      uint32_t characteristics = 0x140 +140011b24      uint32_t timeDateStamp = 0x0 +140011b28      uint16_t majorVersion = 0x0 +140011b2a      uint16_t minorVersion = 0x0 +140011b2c      uint32_t globalFlagsClear = 0x0 +140011b30      uint32_t globalFlagsSet = 0x0 +140011b34      uint32_t criticalSectionDefaultTimeout = 0x0 +140011b38      uint64_t deCommitFreeBlockThreshold = 0x0 +140011b40      uint64_t deCommitTotalFreeThreshold = 0x0 +140011b48      uint64_t lockPrefixTable = 0x0 +140011b50      uint64_t maximumAllocationSize = 0x0 +140011b58      uint64_t virtualMemoryThreshold = 0x0 +140011b60      uint64_t processAffinityMask = 0x0 +140011b68      uint32_t processHeapFlags = 0x0 +140011b6c      uint16_t csdVersion = 0x0 +140011b6e      uint16_t reserved = 0x0 +140011b70      uint64_t editList = 0x0 +140011b78      uint64_t securityCookie = 0x140016040 +140011b80      uint64_t seHandlerTable = 0x0 +140011b88      uint64_t seHandlerCount = 0x0 +140011b90      uint64_t guardCFCheckFunctionPointer = 0x140011070 +140011b98      uint64_t guardCFDispatchFunctionPointer = 0x140011080 +140011ba0      uint64_t guardCFFunctionTable = 0x0 +140011ba8      uint64_t guardCFFunctionCount = 0x0 +140011bb0      uint32_t guardFlags = 0x100 +140011bb4      uint16_t Flags = 0x0 +140011bb6      uint16_t Catalog = 0x0 +140011bb8      uint32_t CatalogOffset = 0x0 +140011bbc      uint32_t Reserved = 0x0 +140011bc0      uint64_t guardAddressTakenIatEntryTable = 0x0 +140011bc8      uint64_t guardAddressTakenIatEntryCount = 0x0 +140011bd0      uint64_t guardLongJumpTargetTable = 0x0 +140011bd8      uint64_t guardLongJumpTargetCount = 0x0 +140011be0      uint64_t dynamicValueRelocTable = 0x0 +140011be8      uint64_t CHPEMetadataPointer = 0x1400111f8 +140011bf0      uint64_t guardRFFailureRoutine = 0x0 +140011bf8      uint64_t guardRFFailureRoutineFunctionPointer = 0x0 +140011c00      uint32_t dynamicValueRelocTableOffset = 0x0 +140011c04      uint16_t dynamicValueRelocTableSection = 0x0 +140011c06      uint16_t reserved2 = 0x0 +140011c08      uint64_t guardRFVerifyStackPointerFunctionPointer = 0x0 +140011c10      uint32_t hotPatchTableOffset = 0x0 +140011c14      uint32_t reserved3 = 0x0 +140011c18      uint64_t enclaveConfigurationPointer = 0x0 +140011c20      uint64_t volatileMetadataPointer = 0x0 +140011c28      uint64_t guardEHContinuationTable = 0x0 +140011c30      uint64_t guardEHContinuationCount = 0x0 +140011c38      uint64_t guardXFGCheckFunctionPointer = 0x140011078 +140011c40      uint64_t guardXFGDispatchFunctionPointer = 0x140011088 +140011c48      uint64_t guardXFGTableDispatchFunctionPointer = 0x140011090 +140011c50  } + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/index.md new file mode 100644 index 0000000..0f1f8a9 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/analyzers/pe/loadconfig-analyzer/index.md @@ -0,0 +1,30 @@ +(plugins-binaryninja-analyzers-loadconfig)= + +# {fa}`solid fa-object-ungroup` LoadConfiguration + +This analyzer enhances the representation and underlying data of the PE +LoadConfiguration structure within BinaryNinja. + +```{eval-rst} +.. img-comparison:: + :left: img/loadconfig_before.svg + :right: img/loadconfig_after.svg +``` + +The layout of this structure -- exposed in LIEF through the +{sub-ref}`lief-pe-loadconfig` interface -- evolves frequently across new Windows releases. +By running this analyzer, you obtain a more complete and accurate representation +of these attributes along with their correct data types. + +Beyond the Load Configuration, the analyzer also defines additional structures, such as +{sub-ref}`lief-pe-chpe_metadata-arm64`, which provide valuable context for analyzing ARM64EC binaries. +These definitions make it easier to interpret the purpose of certain +functions and pointers, leading to deeper insights during reverse engineering. + +```{eval-rst} +.. img-comparison:: + :left: img/chpe_metadata_before.svg + :right: img/chpe_metadata_after.svg +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/dwarf/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/dwarf/index.md new file mode 100644 index 0000000..9603a37 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/dwarf/index.md @@ -0,0 +1,90 @@ +(plugins-binaryninja-dwarf)= + +# {fa}`solid fa-user-ninja` BinaryNinja - DWARF Plugin + +## Export as DWARF + +:::{admonition} BinaryNinja builtin plugin +:class: tip + +Binary Ninja already embeds a DWARF export plugin that exposes +most of the functionality provided by this plugin. However, this plugin +exports additional information, such as stack variables and basic blocks. +::: + +To export DWARF information from a BinaryNinja `BinaryView` representation, +use the menu: `Plugins > LIEF > Export as DWARF` + +```{raw} html +BinaryNinja DWARF exporter +
+
+``` + +### Support & Limitations + +This extension tries to convert most of the information registered in a +BinaryView into DWARF structures, but this support is not exhaustive; here is an +overview of what is and is not exported. + +**BinaryNinja::BinaryView** + +- {fa-check}`check` Function +- {fa-check}`check` Data Variables +- {fa-check}`check` Types +- {fa-check}`check` Comments + +**BinaryNinja::Function** + +- {fa-check}`check` Name +- {fa-check}`check` Address range +- {fa-check}`check` Parameters +- {fa-check}`check` Type of parameters +- {fa-check}`check` Return type +- {fa-check}`check` Stack variables +- {fa-check}`check` Types of stack variables +- {fa-check}`check` Basic Blocks +- {fa-check}`check` Comments + +**BinaryNinja::DataVariable** + +- {fa-check}`check` Name +- {fa-check}`check` Type +- {fa-check}`check` Address +- {fa-check}`check` Comments + +**BinaryNinja::Type** + +- {fa-check}`check` `BNTypeClass::VoidTypeClass` + +- {fa-check}`check` `BNTypeClass::BoolTypeClass` + +- {fa-check}`check` `BNTypeClass::IntegerTypeClass` + +- {fa-check}`check` `BNTypeClass::FloatTypeClass` + +- {fa-check}`check` `BNTypeClass::PointerTypeClass` + +- {fa-check}`check` `BNTypeClass::PointerTypeClass` + +- {fa-check}`check` `BNTypeClass::StructureTypeClass` + + - {fa-check}`check` `BNTypeClass::ClassStructureType` + - {fa-check}`check` `BNTypeClass::UnionStructureType` + - {fa-check}`check` `BNTypeClass::StructStructureType` + +- {fa-check}`check` `BNTypeClass::EnumerationTypeClass` + +- {fa-check}`check` `BNTypeClass::NamedTypeReferenceClass` + +- {fa-check}`check` `BNTypeClass::ArrayTypeClass` + +- {fa-check}`check` `BNTypeClass::WideCharTypeClass` + +- {fa-check}`check` `BNTypeClass::FunctionTypeClass` + +- {xmark}`mark` `BNTypeClass::VarArgsTypeClass` + +- {xmark}`mark` `BNTypeClass::ValueTypeClass` + +Any types not mentioned here are not supported. diff --git a/vendor/lief/doc/sphinx/plugins/binaryninja/index.md b/vendor/lief/doc/sphinx/plugins/binaryninja/index.md new file mode 100644 index 0000000..7ea9d37 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/binaryninja/index.md @@ -0,0 +1,109 @@ +(plugins-binaryninja)= + +# {fa}`solid fa-user-ninja` BinaryNinja + +```{raw} html +
+LIEF integrated with Binary Ninja +``` + +Similar to the {ref}`Ghidra plugin `, LIEF can be used +as a BinaryNinja plugin. + +```{eval-rst} +.. toctree:: + :caption:  Features + :maxdepth: 2 + + dwarf/index + analyzers/elf/index + analyzers/pe/index +``` + +```{eval-rst} +.. plugin-package:: binaryninja + :file: latest/plugins/index.json +``` + +First, download the LIEF plugin package from {sub-ref}`lief-plugin-url` or +from the packages listed above. Then, follow the official procedure to install +plugins: + +For instance, if you install the {ref}`DWARF Plugin `, +you should have this file installed: + +- **Linux:** `~/.binaryninja/plugins/lief-dwarf-plugin-linux-x86_64.so` +- **Windows:** `C:\Users\romain\AppData\Roaming\Binary Ninja\plugins\lief-dwarf-plugin-windows-x86_64.dll` +- **macOS:** `~/Library/Application Support/Binary Ninja/plugins/lief-dwarf-plugin-darwin-arm64.dylib` + +:::{admonition} Shared Library +:class: warning + +In addition to the previously installed library, the plugins require the +installation of `LIEF.dll`, `libLIEF.dylib`, or `libLIEF.so` next to the +plugin directory. You can download this library from the following list: + +```{eval-rst} +.. sdk-package:: SDK + :file: latest/sdk/index.json + :filter: win64, linux-x86_64, darwin +``` + +or from here: {sub-ref}`lief-sdk-url`. Some plugins (like the {ref}`DWARF Plugin `) +require the extended version, which can be downloaded from {sub-ref}`lief-extended-url`. + +Given this shared library, you must copy it into the plugin directory (or its +parent for Linux and macOS). + +- **macOS**: + + - `~/Library/Application Support/Binary Ninja/plugins/libLIEF.dylib` + - `~/Library/Application Support/Binary Ninja/libLIEF.dylib` + +- **Linux**: + + - `~/.binaryninja/plugins/libLIEF.so` + - `~/.binaryninja/libLIEF.so` + +- **Windows**: + + - `C:\Users\romain\AppData\Roaming\Binary Ninja\plugins\LIEF.dll` + - `%APPDATA%\Binary Ninja\plugins\LIEF.dll` +::: + +## {fa}`solid fa-bug` Troubleshooting + +**Plugin module failed to load** + +```text +[:0 Default] Plugin module '~/.binaryninja/plugins/lief-dwarf-plugin-linux-x86_64.so' failed to load +[:0 Default] dlerror() reports: libLIEF.so: cannot open shared object file: No such file or directory +``` + +This means that `libLIEF.so`, `libLIEF.dylib`, or `LIEF.dll` is not correctly +installed in the `plugins/` directory. Make sure that the LIEF shared library is +next to the plugin that failed to load. + +**This feature requires LIEF extended** + +This error means that you need to install the extended version of the shared +library. See the {ref}`extended section ` for more information. + +**libLIEF.dylib can't be opened because Apple cannot check it for malicious software** + +`libLIEF.dylib` is self-signed and does not use an Apple certificate; +therefore, it is considered as coming from an *unknown developer*. + +You can address this issue in different ways: + +1. You can compile `libLIEF.dylib` yourself and sign the compiled library + with your certificate. +2. You can add a security exception as described here: + +```{raw} html +macOS library loading issue +
+
+``` diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_after.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_after.svg new file mode 100644 index 0000000..65a7c4c --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_after.svg @@ -0,0 +1,45 @@ + + + + + + + 140017000 00 10 00 00 40 27 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017000 00 10 00 00           ibo32  __aarch64_function@140001000                           BeginAddress     XREF[2]:   14000029c(*), 140011238(*) +      140017004 40 27 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012740     ExceptionInfoRVA +140017008 20 10 00 00 4c 27 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017008 20 10 00 00           ibo32  __aarch64_function@140001020                           BeginAddress +      14001700c 4c 27 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_14001274c     ExceptionInfoRVA +140017010 60 10 00 00 5c 27 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017010 60 10 00 00           ibo32  __aarch64_function@140001060                           BeginAddress +      140017014 5c 27 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_14001275c     ExceptionInfoRVA +140017018 80 10 00 00 6c 27 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017018 80 10 00 00           ibo32  __aarch64_function@140001080                           BeginAddress +      14001701c 6c 27 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_14001276c     ExceptionInfoRVA +140017020 e0 10 00 00 18 29 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017020 e0 10 00 00           ibo32  __aarch64_function@1400010e0                           BeginAddress +      140017024 18 29 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012918     ExceptionInfoRVA +140017028 00 11 00 00 c0 2a 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017028 00 11 00 00           ibo32  __aarch64_function@140001100                           BeginAddress +      14001702c c0 2a 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012ac0     ExceptionInfoRVA +140017030 18 11 00 00 cc 2a 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017030 18 11 00 00           ibo32  __aarch64_function@140001118                           BeginAddress +      140017034 cc 2a 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012acc     ExceptionInfoRVA +140017038 50 11 00 00 e4 2c 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017038 50 11 00 00           ibo32  __aarch64_function@140001150                           BeginAddress +      14001703c e4 2c 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012ce4     ExceptionInfoRVA +140017040 80 11 00 00 ec 2c 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017040 80 11 00 00           ibo32  __aarch64_function@140001180                           BeginAddress +      140017044 ec 2c 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012cec     ExceptionInfoRVA +140017048 00 12 00 00 f4 2c 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017048 00 12 00 00           ibo32  __aarch64_function@140001200                           BeginAddress +      14001704c f4 2c 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012cf4     ExceptionInfoRVA +140017050 80 12 00 00 fc 2c 01 00    IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY +      140017050 80 12 00 00           ibo32  __aarch64_function@140001280                           BeginAddress +      140017054 fc 2c 01 00           ibo32  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA_140012cfc     ExceptionInfoRVA + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_before.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_before.svg new file mode 100644 index 0000000..763f56d --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/pdata_before.svg @@ -0,0 +1,45 @@ + + + + + + + 140017000 00            ??                         00h +140017001 10            ??                         10h +140017002 00            ??                         00h +140017003 00            ??                         00h +140017004 40            ??                         40h    @ +140017005 27            ??                         27h    ' +140017006 01            ??                         01h +140017007 00            ??                         00h +140017008 20            ??                         20h +140017009 10            ??                         10h +14001700a 00            ??                         00h +14001700b 00            ??                         00h +14001700c 4c            ??                         4Ch    L +14001700d 27            ??                         27h    ' +14001700e 01            ??                         01h +14001700f 00            ??                         00h +140017010 60            ??                         60h    ` +140017011 10            ??                         10h +140017012 00            ??                         00h +140017013 00            ??                         00h +140017014 5c            ??                         5Ch    \ +140017015 27            ??                         27h    ' +140017016 01            ??                         01h +140017017 00            ??                         00h +140017018 80            ??                         80h +140017019 10            ??                         10h +14001701a 00            ??                         00h +14001701b 00            ??                         00h +14001701c 6c            ??                         6Ch    l +14001701d 27            ??                         27h    ' +14001701e 01            ??                         01h +14001701f 00            ??                         00h +140017020 e0            ??                         E0h + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_after.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_after.svg new file mode 100644 index 0000000..5f4cac0 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_after.svg @@ -0,0 +1,49 @@ + + + + + + + 140012710 0b 00 20 08                                  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA +      140012710 0b 00 20                                dword:18                  Bh                FunctionLength             XREF[1]:   140017a14(*) +      140012712 20                                      dword:2                   0h                Version +      140012712 20                                      dword:1                   0h                ExceptionDataPresent +      140012712 20                                      dword:1                   1h                EpilogInHeader +      140012712 20 08                                   dword:5                   0h                EpilogCount +      140012713 08                                      dword:5                   1h                CodeWords +                    __arm64_unwind_code@140012714 +140012714 81 e4 e3 e3                                  db[4] +   140012714 [0]           81h, E4h, E3h, E3h +                    IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA  XREF[1]:   140017a1c(*) +140012718 14 00 40 40                                  IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA +      140012718 14 00 40                                dword:18                  14h               FunctionLength             XREF[1]:   140017a1c(*) +      14001271a 40                                      dword:2                   0h                Version +      14001271a 40                                      dword:1                   0h                ExceptionDataPresent +      14001271a 40                                      dword:1                   0h                EpilogInHeader +      14001271a 40 40                                   dword:5                   1h                EpilogCount +      14001271b 40                                      dword:5                   8h                CodeWords +                    __arm64_epilog_scopes@14001271c +14001271c 0a 00 c0 02                                  EpilogScope[1] +      14001271c 0a 00 c0 02                             EpilogScope                                 [0] +         14001271c 0a 00 c0                                dword:18                  Ah                StartOffset +         14001271e c0                                      dword:4                   0h                Res +         14001271e c0 02                                   dword:10                  Bh                ExceptionDataPresent +                    __arm64_unwind_code@140012720 +140012720 e1 81 e6 e6 e6 e6 e7 66 89 fc e4 81 e7       db[32] +          4e 88 e7 4c 86 e7 4a 84 e7 48 82 e7 66 +          89 fc e3 e3 e4 e3 +   140012720 [0]           E1h, 81h, E6h, E6h, +   140012724 [4]           E6h, E6h, E7h, 66h, +   140012728 [8]           89h, FCh, E4h, 81h, +   14001272c [12]          E7h, 4Eh, 88h, E7h, +   140012730 [16]          4Ch, 86h, E7h, 4Ah, +   140012734 [20]          84h, E7h, 48h, 82h, +   140012738 [24]          E7h, 66h, 89h, FCh, +   14001273c [28]          E3h, E3h, E4h, E3h +                    IMAGE_ARM64_RUNTIME_FUNCTION_ENTRY_XDATA  XREF[1]:   140017004(*) + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_before.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_before.svg new file mode 100644 index 0000000..e4c999b --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/img/rdata_before.svg @@ -0,0 +1,49 @@ + + + + + + + 140012710 0b                ??        0Bh +140012711 00                ??        00h +140012712 20                ??        20h +140012713 08                ??        08h +140012714 81                ??        81h +140012715 e4                ??        E4h +140012716 e3                ??        E3h +140012717 e3                ??        E3h +140012718 14                ??        14h +140012719 00                ??        00h +14001271a 40                ??        40h    @ +14001271b 40                ??        40h    @ +14001271c 0a                ??        0Ah +14001271d 00                ??        00h +14001271e c0                ??        C0h +14001271f 02                ??        02h +140012720 e1                ??        E1h +140012721 81                ??        81h +140012722 e6                ??        E6h +140012723 e6                ??        E6h +140012724 e6                ??        E6h +140012725 e6                ??        E6h +140012726 e7                ??        E7h +140012727 66                ??        66h    f +140012728 89                ??        89h +140012729 fc                ??        FCh +14001272a e4                ??        E4h +14001272b 81                ??        81h +14001272c e7                ??        E7h +14001272d 4e                ??        4Eh    N +14001272e 88                ??        88h +14001272f e7                ??        E7h +140012730 4c                ??        4Ch    L +140012731 86                ??        86h +140012732 e7                ??        E7h +140012733 4a                ??        4Ah    J +140012734 84                ??        84h + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/index.md b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/index.md new file mode 100644 index 0000000..d4a7f84 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/exceptions-analyzer/index.md @@ -0,0 +1,18 @@ +(plugins-ghidra-analyzers-exceptions)= + +# {fa}`solid fa-object-ungroup` Ghidra - Analyzers - Exceptions + +This analyzer improves the representation and underlying data of PE exceptions +metadata, primarily for ARM64 and ARM64EC binaries. + +```{eval-rst} +.. img-comparison:: + :left: img/pdata_before.svg + :right: img/pdata_after.svg +``` + +```{eval-rst} +.. img-comparison:: + :left: img/rdata_before.svg + :right: img/rdata_after.svg +``` diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_after.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_after.svg new file mode 100644 index 0000000..cbe6d87 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_after.svg @@ -0,0 +1,42 @@ + + + + + + +                     IMAGE_ARM64EC_METADATA_V2_1400111f8       XREF[1]:   140011be8(*) +1400111f8 02 00 00 00 00 1e 01 00 02 00 00 00 b4       IMAGE_ARM64EC_METADATA_V2 +          1c 01 00 00 90 01 00 00 10 01 00 08 10 +          01 00 18 10 01 00 10 10 01 00 20 10 01 +      1400111f8 02 00 00 00 00 1e 01 00 02 00 00 00 b4  IMAGE_ARM64EC_METADATA                                                                              V1 +                1c 01 00 00 90 01 00 00 10 01 00 08 10 +                01 00 18 10 01 00 10 10 01 00 20 10 01 +         1400111f8 02 00 00 00                             ddw                2h                                                             Version +         1400111fc 00 1e 01 00                             ibo32              IMAGE_ARM64EC_METADATA_CODE_RANGE_ARRAY_140011e00              CodeMap +         140011200 02 00 00 00                             ddw                2h                                                             CodeMapCount +         140011204 b4 1c 01 00                             ibo32              IMAGE_ARM64EC_CODE_RANGE_ENTRY_POINT_ARRAY_140011cb4           CodeRangesToEntryPoints +         140011208 00 90 01 00                             ibo32              IMAGE_ARM64EC_METADATA_REDIRECTION_ARRAY_140019000             RedirectionMetadata +         14001120c 00 10 01 00                             ibo32              DAT_140011000                                                  __os_arm64x_dispatch_call_no_redirect +         140011210 08 10 01 00                             ibo32              DAT_140011008                                                  __os_arm64x_dispatch_ret +         140011214 18 10 01 00                             ibo32              DAT_140011018                                                  __os_arm64x_dispatch_call +         140011218 10 10 01 00                             ibo32              PTR_DAT_140011010                                              __os_arm64x_dispatch_icall +         14001121c 20 10 01 00                             ibo32              PTR_DAT_140011020                                              __os_arm64x_dispatch_icall_cfg +         140011220 00 00 00 00                             ibo32              NaP                                                            AlternateEntryPoint +         140011224 00 50 01 00                             ibo32              PTR_DAT_140015000                                              AuxiliaryIAT +         140011228 01 00 00 00                             ddw                1h                                                             CodeRangesToEntryPointsCount +         14001122c 01 00 00 00                             ddw                1h                                                             RedirectionMetadataCount +         140011230 28 10 01 00                             ibo32              DAT_140011028                                                  GetX64InformationFunctionPointer +         140011234 30 10 01 00                             ibo32              DAT_140011030                                                  SetX64InformationFunctionPointer +         140011238 00 70 01 00                             ibo32              IMAGE_ARM64_RUNTIME_FUNCTION_UNPACKED_ENTRY_140017000          ExtraRFETable +         14001123c 38 0d 00 00                             ddw                D38h                                                           ExtraRFETableSize +         140011240 38 10 01 00                             ibo32              DAT_140011038                                                  __os_arm64x_dispatch_fptr +         140011244 48 3e 01 00                             ibo32              PTR_DAT_140013e48                                              AuxiliaryIATCopy +      140011248 00 00 00 00                             ibo32              NaP                                                            AuxDelayloadIAT +      14001124c 00 00 00 00                             ibo32              NaP                                                            AuxDelayloadIATCopy +      140011250 00 00 00 00                             ddw                0h                                                             ReservedBitField + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_before.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_before.svg new file mode 100644 index 0000000..cda55ef --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/chpe_metadata_before.svg @@ -0,0 +1,42 @@ + + + + + + +                     DAT_1400111f8                             XREF[1]:   140011be8(*) +1400111f8 02                                           ??                                                   02h +1400111f9 00                                           ??                                                   00h +1400111fa 00                                           ??                                                   00h +1400111fb 00                                           ??                                                   00h +1400111fc 00                                           ??                                                   00h +1400111fd 1e                                           ??                                                   1Eh +1400111fe 01                                           ??                                                   01h +1400111ff 00                                           ??                                                   00h +140011200 02                                           ??                                                   02h +140011201 00                                           ??                                                   00h +140011202 00                                           ??                                                   00h +140011203 00                                           ??                                                   00h +140011204 b4                                           ??                                                   B4h +140011205 1c                                           ??                                                   1Ch +140011206 01                                           ??                                                   01h +140011207 00                                           ??                                                   00h +140011208 00                                           ??                                                   00h +140011209 90                                           ??                                                   90h +14001120a 01                                           ??                                                   01h +14001120b 00                                           ??                                                   00h +14001120c 00                                           ??                                                   00h +14001120d 10                                           ??                                                   10h +14001120e 01                                           ??                                                   01h +14001120f 00                                           ??                                                   00h +140011210 08                                           ??                                                   08h +140011211 10                                           ??                                                   10h +140011212 01                                           ??                                                   01h +140011213 00                                           ??                                                   00h +140011214 18                                           ??                                                   18h + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_after.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_after.svg new file mode 100644 index 0000000..9dedb86 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_after.svg @@ -0,0 +1,65 @@ + + + + + + +                     IMAGE_LOAD_CONFIG_DIRECTORY64_140011b20   XREF[1]:   1400001c0(*) +140011b20 40 01 00 00 00 00 00 00 00 00 00 00 00       IMAGE_LOAD_CONFIG_DIRECTORY64 +          00 00 00 00 00 00 00 00 00 00 00 00 00 +          00 00 00 00 00 00 00 00 00 00 00 00 00 +      140011b20 40 01 00 00                             ddw                       140h                                  Size                            XREF[1]:   1400001c0(*) +      140011b24 00 00 00 00                             ddw                       0h                                    TimeDateStamp +      140011b28 00 00                                   dw                        0h                                    MajorVersion +      140011b2a 00 00                                   dw                        0h                                    MinorVersion +      140011b2c 00 00 00 00                             ddw                       0h                                    GlobalFlagsClear +      140011b30 00 00 00 00                             ddw                       0h                                    GlobalFlagsSet +      140011b34 00 00 00 00                             ddw                       0h                                    CriticalSectionDefaultTimeout +      140011b38 00 00 00 00 00 00 00 00                 dq                        0h                                    DeCommitFreeBlockThreshold +      140011b40 00 00 00 00 00 00 00 00                 dq                        0h                                    DeCommitTotalFreeThreshold +      140011b48 00 00 00 00 00 00 00 00                 addr                      00000000                              LockPrefixTable +      140011b50 00 00 00 00 00 00 00 00                 dq                        0h                                    MaximumAllocationSize +      140011b58 00 00 00 00 00 00 00 00                 dq                        0h                                    VirtualMemoryThreshold +      140011b60 00 00 00 00 00 00 00 00                 dq                        0h                                    ProcessAffinityMask +      140011b68 00 00 00 00                             ddw                       0h                                    ProcessHeapFlags +      140011b6c 00 00                                   dw                        0h                                    CSDVersion +      140011b6e 00 00                                   dw                        0h                                    DependentLoadFlags +      140011b70 00 00 00 00 00 00 00 00                 addr                      00000000                              EditList +      140011b78 40 60 01 40 01 00 00 00                 addr                      DAT_140016040                         SecurityCookie                         = 32h    2 +      140011b80 00 00 00 00 00 00 00 00                 dq *                      00000000                              SEHandlerTable +      140011b88 00 00 00 00 00 00 00 00                 dq                        0h                                    SEHandlerCount +      140011b90 70 10 01 40 01 00 00 00                 addr                      PTR__guard_check_icall_140011070      GuardCFCheckFunctionPointer            = 14000b8d8 +      140011b98 80 10 01 40 01 00 00 00                 addr                      PTR__guard_dispatch_icall_140011080   GuardCFDispatchFunctionPointer         = 14000e2c0 +      140011ba0 00 00 00 00 00 00 00 00                 ddw *                     00000000                              GuardCFFunctionTable +      140011ba8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardCFFunctionCount +      140011bb0 00 01 00 00                             IMAGE_GUARD_FLAGS         IMAGE_GUARD_CF_INSTRUMENTED           GuardFlags +      140011bb4 00 00 00 00 00 00 00 00 00 00 00 00     IMAGE_LOAD_CONFIG_CODE_I                                        CodeIntegrity +      140011bc0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardAddressTakenIatEntryTable +      140011bc8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardAddressTakenIatEntryCount +      140011bd0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardLongJumpTargetTable +      140011bd8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardLongJumpTargetCount +      140011be0 00 00 00 00 00 00 00 00                 addr                      00000000                              DynamicValueRelocTable +      140011be8 f8 11 01 40 01 00 00 00                 IMAGE_ARM64EC_METADATA_V  IMAGE_ARM64EC_METADATA_V2_1400111f8   CHPEMetadataPointer +      140011bf0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFFailureRoutine +      140011bf8 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFFailureRoutineFunctionPointer +      140011c00 00 00 00 00                             ibo32                     NaP                                   DynamicValueRelocTableOffset +      140011c04 00 00                                   dw                        0h                                    DynamicValueRelocTableSection +      140011c06 00 00                                   dw                        0h                                    Reserved2 +      140011c08 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFVerifyStackPointerFunctionPoin +      140011c10 00 00 00 00                             ibo32                     NaP                                   HotPatchTableOffset +      140011c14 00 00 00 00                             ddw                       0h                                    Reserved3 +      140011c18 00 00 00 00 00 00 00 00                 addr                      00000000                              EnclaveConfigurationPointer +      140011c20 00 00 00 00 00 00 00 00                 addr                      00000000                              VolatileMetadataPointer +      140011c28 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardEHContinuationTable +      140011c30 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardEHContinuationCount +      140011c38 78 10 01 40 01 00 00 00                 addr                      PTR__guard_check_icall_140011078      GuardXFGCheckFunctionPointer           = 14000b8d8 +      140011c40 88 10 01 40 01 00 00 00                 addr                      PTR_LAB_140011088                     GuardXFGDispatchFunctionPointer        = 14000e2e0 +      140011c48 90 10 01 40 01 00 00 00                 addr                      PTR_LAB_140011090                     GuardXFGTableDispatchFunctionPointer   = 14000e2e0 +      140011c50 98 10 01 40 01 00 00 00                 addr                      DAT_140011098                         CastGuardOsDeterminedFailureMode +      140011c58 a0 10 01 40 01 00 00 00                 addr                      PTR_LAB_1400110a0                     GuardMemcpyFunctionPointer             = 14000e080 + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_before.svg b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_before.svg new file mode 100644 index 0000000..023ff03 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/img/loadconfig_before.svg @@ -0,0 +1,57 @@ + + + + + + +                     IMAGE_LOAD_CONFIG_DIRECTORY64_140011b20   XREF[1]:   1400001c0(*) +140011b20 40 01 00 00 00 00 00 00 00 00 00 00 00       IMAGE_LOAD_CONFIG_DIRECTORY64 +          00 00 00 00 00 00 00 00 00 00 00 00 00 +          00 00 00 00 00 00 00 00 00 00 00 00 00 +      140011b20 40 01 00 00                             ddw                       140h                                  Size                            XREF[1]:   1400001c0(*) +      140011b24 00 00 00 00                             ddw                       0h                                    TimeDateStamp +      140011b28 00 00                                   dw                        0h                                    MajorVersion +      140011b2a 00 00                                   dw                        0h                                    MinorVersion +      140011b2c 00 00 00 00                             ddw                       0h                                    GlobalFlagsClear +      140011b30 00 00 00 00                             ddw                       0h                                    GlobalFlagsSet +      140011b34 00 00 00 00                             ddw                       0h                                    CriticalSectionDefaultTimeout +      140011b38 00 00 00 00 00 00 00 00                 dq                        0h                                    DeCommitFreeBlockThreshold +      140011b40 00 00 00 00 00 00 00 00                 dq                        0h                                    DeCommitTotalFreeThreshold +      140011b48 00 00 00 00 00 00 00 00                 addr                      00000000                              LockPrefixTable +      140011b50 00 00 00 00 00 00 00 00                 dq                        0h                                    MaximumAllocationSize +      140011b58 00 00 00 00 00 00 00 00                 dq                        0h                                    VirtualMemoryThreshold +      140011b60 00 00 00 00 00 00 00 00                 dq                        0h                                    ProcessAffinityMask +      140011b68 00 00 00 00                             ddw                       0h                                    ProcessHeapFlags +      140011b6c 00 00                                   dw                        0h                                    CsdVersion +      140011b6e 00 00                                   dw                        0h                                    DependentLoadFlags +      140011b70 00 00 00 00 00 00 00 00                 addr                      00000000                              EditList +      140011b78 40 60 01 40 01 00 00 00                 addr                      DAT_140016040                         SecurityCookie                         = 32h    2 +      140011b80 00 00 00 00 00 00 00 00                 addr                      00000000                              SEHandlerTable +      140011b88 00 00 00 00 00 00 00 00                 dq                        0h                                    SEHandlerCount +      140011b90 70 10 01 40 01 00 00 00                 addr                      PTR__guard_check_icall_140011070      GuardCFCCheckFunctionPointer           = 14000b8d8 +      140011b98 80 10 01 40 01 00 00 00                 addr                      PTR__guard_dispatch_icall_140011080   GuardCFDispatchFunctionPointer         = 14000e2c0 +      140011ba0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardCFFunctionTable +      140011ba8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardCFFunctionCount +      140011bb0 00 01 00 00                             IMAGE_GUARD_FLAGS         IMAGE_GUARD_CF_INSTRUMENTED           GuardFlags +      140011bb4 00 00 00 00 00 00 00 00 00 00 00 00     IMAGE_LOAD_CONFIG_CODE_I                                        CodeIntegrity +      140011bc0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardAddressTakenIatEntryTable +      140011bc8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardAddressTakenIatEntryCount +      140011bd0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardLongJumpTargetTable +      140011bd8 00 00 00 00 00 00 00 00                 dq                        0h                                    GuardLongJumpTargetCount +      140011be0 00 00 00 00 00 00 00 00                 addr                      00000000                              DynamicValueRelocTable +      140011be8 f8 11 01 40 01 00 00 00                 addr                      DAT_1400111f8                         CHPEMetadataPointer                    = 02h +      140011bf0 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFFailureRoutine +      140011bf8 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFFailureRoutineFunctionPointer +      140011c00 00 00 00 00                             ddw                       0h                                    DynamicValueRelocTableOffset +      140011c04 00 00                                   dw                        0h                                    DynamicValueRelocTableSection +      140011c06 00 00                                   dw                        0h                                    Reserved1 +      140011c08 00 00 00 00 00 00 00 00                 addr                      00000000                              GuardRFVerifyStackPointerFunctionPoin +      140011c10 00 00 00 00                             ddw                       0h                                    HotPatchTableOffset +      140011c14 00 00 00 00                             ddw                       0h                                    Reserved2 +      140011c18 00 00 00 00 00 00 00 00                 dq                        0h                                    Reserved3 + + + + + \ No newline at end of file diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/index.md b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/index.md new file mode 100644 index 0000000..0227772 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/analyzers/loadconfig-analyzer/index.md @@ -0,0 +1,40 @@ +(plugins-ghidra-analyzers-loadconfig)= + +# {fa}`solid fa-object-ungroup` Ghidra - Analyzers - `IMAGE_LOAD_CONFIG_DIRECTORY` + +This analyzer enhances the representation and underlying data of the PE +LoadConfiguration structure within Ghidra. + +```{eval-rst} +.. img-comparison:: + :left: img/loadconfig_before.svg + :right: img/loadconfig_after.svg + :width: 100% +``` + +The layout of this structure -- exposed in LIEF through the +{sub-ref}`lief-pe-loadconfig` interface -- evolves frequently across new Windows releases. +As of today, Ghidra does not natively recognize many of the newer attributes +introduced in recent versions. By running this analyzer, you obtain a more +complete and accurate representation of these attributes along with their correct data types. + +Beyond the Load Configuration, the analyzer also defines additional structures, such as +{sub-ref}`lief-pe-chpe_metadata-arm64`, which provide valuable context for analyzing ARM64EC binaries. +These definitions make it easier to interpret the purpose of certain +functions and pointers, leading to deeper insights during reverse engineering. + +```{eval-rst} +.. img-comparison:: + :left: img/chpe_metadata_before.svg + :right: img/chpe_metadata_after.svg + :width: 100% + +``` + +:::{admonition} BinaryNinja +:class: tip + +BinaryNinja's LIEF plugin also provides this support: {ref}`plugins-binaryninja-analyzers-loadconfig` +::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/dwarf/index.md b/vendor/lief/doc/sphinx/plugins/ghidra/dwarf/index.md new file mode 100644 index 0000000..6f88662 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/dwarf/index.md @@ -0,0 +1,101 @@ +(plugins-ghidra-dwarf)= + +# {fa}`solid fa-dragon` Ghidra - DWARF Plugin + +## Export as DWARF + +This functionality exports Ghidra's program information into a DWARF file. +This exported information includes function names, types, stack variables, etc. + +You can use this extension in different ways as documented below: + +### Project Manager + +This extension provides a DWARF exporter that can be used by right-clicking +on the binary to export, then: `Export > Format > DWARF`: + +```{raw} html +Ghidra DWARF exporter +
+
+``` + +### CodeBrowser + +From the `CodeBrowser` tool, you can left-click on the LIEF menu and select +`Export as DWARF`: + +```{raw} html +Ghidra DWARF exporter +
+
+``` + +### Scripts + +You can also use the Java API from a (headless) script to export a given +Ghidra program: + +```java +import lief.ghidra.core.dwarf.export.Manager; +import lief.ghidra.core.NativeBridge; + +public class LiefDwarfExportScript extends GhidraScript { + @Override + protected void run() throws Exception { + NativeBridge.init(); + Manager manager = new Manager(currentProgram); + File output = new File("/home/romain/output.dwarf"); + manager.export(output); + } +} +``` + +### Support & Limitations + +This extension tries to convert as much as possible of Ghidra's internal binary +representation into DWARF structures, but this support is not exhaustive; here is +an overview of what is and is not exported. + +**ghidra.program.model.listing.Program** + +- {fa-check}`check` Function +- {fa-check}`check` Data Variables +- {fa-check}`check` Types +- {xmark}`mark` Comments + +**ghidra.program.model.listing.Function** + +- {fa-check}`check` Name +- {fa-check}`check` Address range +- {fa-check}`check` Parameters +- {fa-check}`check` Type of parameters +- {fa-check}`check` Return type +- {fa-check}`check` Stack variables +- {fa-check}`check` Types of stack variables +- {xmark}`mark` Comments +- {xmark}`mark` CodeUnits + +**ghidra.program.model.listing.Data** + +- {fa-check}`check` Name +- {fa-check}`check` Type +- {fa-check}`check` Address +- {xmark}`mark` Comments + +**ghidra.program.model.data.DataType** + +- {fa-check}`check` `ghidra.program.model.data.VoidDataType` +- {fa-check}`check` `ghidra.program.model.data.AbstractIntegerDataType` +- {fa-check}`check` `ghidra.program.model.data.Array` +- {fa-check}`check` `ghidra.program.model.data.TypeDef` +- {fa-check}`check` `ghidra.program.model.data.Composite` +- {fa-check}`check` `ghidra.program.model.data.Enum` +- {fa-check}`check` `ghidra.program.model.data.FunctionDefinition` +- {fa-check}`check` `ghidra.program.model.data.Pointer` + +Any types not mentioned here are not supported. + +### References + + diff --git a/vendor/lief/doc/sphinx/plugins/ghidra/index.md b/vendor/lief/doc/sphinx/plugins/ghidra/index.md new file mode 100644 index 0000000..043fa18 --- /dev/null +++ b/vendor/lief/doc/sphinx/plugins/ghidra/index.md @@ -0,0 +1,100 @@ +(plugins-ghidra)= + +# {fa}`solid fa-dragon` Ghidra + +```{raw} html +
+Ghidra with LIEF +``` + +Similar to the {ref}`BinaryNinja plugin `, LIEF can be used +as a Ghidra plugin. + +```{eval-rst} +.. toctree:: + :caption:  Features + :maxdepth: 1 + + dwarf/index + analyzers/loadconfig-analyzer/index + analyzers/exceptions-analyzer/index +``` + +```{eval-rst} +.. plugin-package:: ghidra + :file: latest/plugins/index.json +``` + +## {fa}`solid fa-gear` Installation + +First, download the LIEF plugin package from {sub-ref}`lief-plugin-url` or +from the packages listed above. Then, follow the official procedure to install +extensions: [GhidraDocs/GettingStarted.md](https://github.com/NationalSecurityAgency/ghidra/blob/175cf9488722df3f8a718236c9e2c0ebfcd8cdb7/GhidraDocs/GettingStarted.md#extensions) + +:::{admonition} Shared Library +:class: warning + +In addition to the previously installed package, the plugins require the +installation of `LIEF.dll`, `libLIEF.dylib`, or `libLIEF.so` next to the +extension directory. You can download this library from the following list: + +```{eval-rst} +.. sdk-package:: SDK + :file: latest/sdk/index.json + :filter: win64, linux-x86_64, darwin +``` + +or from here: {sub-ref}`lief-sdk-url`. Some plugins (like the {ref}`DWARF Plugin `) +require the extended version, which can be downloaded from {sub-ref}`lief-extended-url`. + +Given this shared library, you must copy it into the Ghidra settings +directory. For instance: + +- macOS: `~/Library/ghidra/ghidra_11.3.2_PUBLIC/Extensions/libLIEF.dylib` +- Linux: `~/.config/ghidra/ghidra_11.3.2_PUBLIC/Extensions/libLIEF.so` +- Windows: `C:\Users\romain\AppData\Roaming\ghidra\ghidra_11.3.2_PUBLIC\Extensions\LIEF.dll` +- Windows: `%APPDATA%\ghidra\ghidra_11.3.2_PUBLIC\Extensions\LIEF.dll` +::: + +You can verify that the plugin is correctly installed by opening the +`CodeBrowser` tool on a binary and ensuring that you can see the LIEF +configuration in `File > Configure` (**from the CodeBrowser, not the projects window**). + +Alternatively, you can try running the headless script: `LiefVersionInfoScript.java`, +which should output information about the installed version. + +## {fa}`solid fa-bug` Troubleshooting + +**Couldn't find the native library** + +This means that `libLIEF.so`, `libLIEF.dylib`, or `LIEF.dll` is not +correctly installed in the `Extensions/` directory. The details of the error +provide the expected path(s). + +```{raw} html +Ghidra native library issue +
+
+``` + +**This feature requires LIEF extended** + +This error means that you need to install the extended version of the shared +library. See the {ref}`extended section ` for more information. + +**libLIEF.dylib can't be opened because Apple cannot check it for malicious software** + +`libLIEF.dylib` is self-signed and does not use an Apple certificate. +Therefore, it is considered as coming from an *unknown developer*. + +You can address this issue in different ways: + +1. You can compile `libLIEF.dylib` yourself and sign the compiled library + with your certificate. +2. You can add a security exception as described here: + +```{raw} html +macOS library loading issue +
+
+``` diff --git a/vendor/lief/doc/sphinx/references.md b/vendor/lief/doc/sphinx/references.md new file mode 100644 index 0000000..3b891a8 --- /dev/null +++ b/vendor/lief/doc/sphinx/references.md @@ -0,0 +1,158 @@ +# {fa}`fa-solid fa-book-bookmark` References + +## Blog Posts & White Papers + +```{eval-rst} +.. role:: strike + :class: strike +``` + +- 2021-06-03: [QBDL: Quarkslab Dynamic Loader](https://www.sstic.org/2021/presentation/qbdl_quarkslab_dynamic_loader/) +- 2021-04-27: [An Empirical Evaluation of Automated Machine Learning Techniques for Malware Detection - IWSPA 21](https://dl.acm.org/doi/pdf/10.1145/3445970.3451155) +- 2021-01-25: [Static PE antimalware evasion - Francisco Javier Gomez Galvez](http://openaccess.uoc.edu/webapps/o2/bitstream/10609/127010/7/fgomezgalvezTFM0121memoria.pdf) +- 2020-10-23: [[Write-up] Using a PIE binary as a Shared Library: HCSC-2020 CTF Writeup](https://medium.com/bugbountywriteup/using-a-pie-binary-as-a-shared-library-hcsc-2020-ctf-writeup-390a8a437f31) by [István Tóth](https://twitter.com/an0n_r0) +- 2020-02-04: [x0rro: A PE/ELF/MachO Crypter for x86 and x86_64 Based on Radare2 by phra](https://iwantmore.pizza/posts/x0rro.html) +- 2019-11-01: [Isolating the logic of an encrypted protocol with LIEF and kaitai](https://x-c3ll.github.io/posts/blackbox-lief-kaitai/) by [@TheXC3LL](https://twitter.com/THEXC3LL) +- 2018-10-26: [[Write-up] HITCON 2018 - Unexecutable](https://github.com/pwning/public-writeup/tree/21b31d1aa916f07a16423a1c2944c498a29271fb/hitcon2018/unexecutable/) by [Andrew Wesie](https://github.com/awesie) +- 2018-10-06: [[Write-up] Flare-on Challenge (Level 3)](https://bruce30262.github.io/flare-on-challenge-2018-write-up/) +- 2018-09-30: [Write-up] DragonCTF-Teaser-Brutal Oldskull by z3r0s +- 2018-09-07: [Using a non-system glibc](https://www.ayrx.me/using-a-non-system-libc) by [Ayrx](https://www.ayrx.me/) +- 2018-07-02: [PWN problem patch method commonly used in competition](http://p4nda.top/2018/07/02/patch-in-pwn/) +- 2018-05-03: [When SideChannelMarvels meet LIEF](https://blog.quarkslab.com/when-sidechannelmarvels-meet-lief.html) +- 2018-03-11: [Fuzzing Arbitrary Functions in ELF Binaries](https://blahcat.github.io/posts/2018/03/11/fuzzing-arbitrary-functions-in-elf-binaries.html/) +- 2018-02-01: [Dissecting Mobile Native Code Packers Case Study](https://blog.zimperium.com/dissecting-mobile-native-code-packers-case-study/) +- 2017-11-02: [Have Fun With LIEF and Executable Formats](https://blog.quarkslab.com/have-fun-with-lief-and-executable-formats.html) +- 2017-04-04: [LIEF Library to Instrument Executable Formats](https://blog.quarkslab.com/lief-library-to-instrument-executable-formats.html) + +## Projects using LIEF + +| Name | Language | Link | Topic | Summary | +| ------------------------------- | ---------- | -------------------------------------------------------------------------------------------------------------------------- | -------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | +| shrinkwrap | Python | | ELF | A tool that embeds required dependencies into top-level executables | +| sqlelf | Python | | ELF Analysis | Explore ELF objects through the power of SQL | +| Maat | Python/C++ | | Symbolic Execution | Symbolic Execution Framework based on Ghidra's sleigh | +| QBDL | Python/C++ | | Binary Loader | QBDI aims to provide a modular and portable way to dynamically load and link binaries. | +| BLint | Python | | Static Analysis | A binary linter for checking security properties and capabilities in executables | +| Datalog Disassembly | C++ | | Binary Analysis | DDisasm is a fast disassembler which is accurate enough for the resulting assembly code to be reassembled. DDisasm is implemented using the datalog (souffle) declarative logic programming language to compile disassembly rules and heuristics | +| Mobile-Security-Framework-MobSF | Python | | Mobile Analysis | Mobile Security Framework (MobSF) is an automated, all-in-one mobile application (Android/iOS/Windows) pen-testing, malware analysis and security assessment framework capable of performing static and dynamic analysis. | +| checksec.py | Python | | Static Analysis | A simple tool to verify the security properties of your binaries. These properties can be enabled by your compiler to enforce the security of your executables, and mitigate exploitation | +| youarespecial | Python | | Machine Learning | Machine learning models on malware | +| gym-malware | Python | | Machine Learning | Learn how to bypass AV through machine learning. | +| MISP | Python | | Malware | Malware Information Sharing Platform and Threat Sharing | +| Virus Disinfector KIT | Python | | Malware | A tool for disinfecting PE files | +| lief-sys | Rust | | Binding | Rust binding for LIEF | +| Ledger-Donjon/rainbow | Python | | Dynamic Analysis | Trace generator based on Unicorn and LIEF as loader. | +| smda | Python | | Static Analysis | Recursive disassembler using LIEF as ELF and PE loader | +| conan-io/hooks | Python | [binary-linter.py](https://github.com/conan-io/hooks/blob/7f2882299cbdb545c397a0f37dc9394a7bbc0902/hooks/binary-linter.py) | Static Analysis | Binary linter | +| Wiggle | Python | | Binary search engine | An executable binary metadata search engine. | +| ANBU | C++ | | Unpacking | Automatic New Binary Unpacker with PIN DBI Framework | + +## Similar Projects + +| Name | Language | Link | +| --------- | -------- | ------------------------------------------- | +| filebytes | Python | | +| angr/cle | Python | | +| pypeelf | Python | | +| object | Rust | | +| Goblin | Rust | | + +## Parsers/Modifiers + +### ELF + +| Name | Language | Link | +| ------------ | -------- | ----------------------------------------------------------------------- | +| pyelftools | Python | | +| pylibelf | Python | | +| pydevtools | Python | | +| elfparser | C++ ? | | +| libelf | C | {strike}`hxxp://www.mr511.de/software/` | +| elfio | C++ | | +| radare2 | C/Python | | +| node-elf | node.js | | +| readelf | C | | +| elfesteem | Python | | +| elfsharp | C# | {strike}`hxxp://elfsharp.hellsgate.pl/index.shtml` | +| metasm | Ruby | | +| amoco | Python | | +| Goblin | Rust | | +| Mithril | Ruby | | +| ELFkickers | C | | +| libelfmaster | C | | +| libelf.js | JS | | +| elfy.io | JS ? | | +| elfhash | C | | + +### PE + +| Name | Language | Link | +| ------------- | ---------- | ------------------------------------------------------------------------------ | +| pefiles | Python | | +| radare2 | C | | +| PE.Explorer | C++/C# ? | | +| CFF Explorer | C++/C# ? | | +| PE Browser 64 | C++/C# ? | {strike}`http://www.smidgeonsoft.prohosting.com/pebrowse-pro-file-viewer.html` | +| PE View | C++/C# ? | | +| FileAlyzer | C++/C# ? | | +| PE Studio | C++/C# ? | | +| PEDumper | C | | +| PE Parse | C++/Python | | +| PEParse | C# | | +| PE Bliss | C++ | | +| PE Net | .NET | | +| libpe | C++ | | +| elfesteem | Python | | +| pelook | C ? | | +| PortEx | Java | | +| metasm | Ruby | | +| amoco | Python | | +| Goblin | Rust | | + +### Mach-O + +| Name | Language | Link | +| ------------ | -------- | --------------------------------------------------------------------- | +| radare2 | C | | +| MachO-Kit | C/ObjC | | +| optool | ObjC | | +| macho_edit | C++ | | +| macholib | Python | | +| elfsharp | C# | {strike}`http://elfsharp.hellsgate.pl/index.shtml` | +| elfesteem | Python | | +| metasm | Ruby | | +| Goblin | Rust | | +| MachOView | ObjC | | +| XMachOViewer | C++ | | + +## Tools + +| Name | Language | Link | Format | Summary | +| ------------------------ | -------- | -------------------------------------------------------- | ------------ | -------------------------------------------------------- | +| Dress | Python | | ELF | Adds static symbols | +| objconv | C++ | | ELF/PE/MachO | Format converter | +| PEDetour | C++ | | PE | Hook exported functions | +| python-elf | Python | | ELF | ELF binary format manipulation tool | +| PEDetour | C++ | | PE | Hook exported functions | +| libmaelf | C | | ELF | A library for dissecting and infecting ELF binaries. | +| peinjector | C | | PE | MITM PE file infector | +| backdoor factory | C++ | | ELF/PE/MachO | Patch PE, ELF, Mach-O binaries with shellcode | +| RePEconstruct | C | | PE | PE Unpacker | +| patchkit | Python | | ELF | Patch binary | +| unstrip | Python | | ELF | Unstrip static binary | +| sym2elf | Python | | ELF | Exports IDA symbols to the original binary | +| elfhash | C | | ELF | Manipulate ELF's hash | +| recomposer | Python | | PE | Modifies parts of a PE file to bypass antivirus software | +| bearparser | C++ | | PE | Portable Executable parsing library with a GUI | +| IAT patcher | C++ | | PE | IAT hooking application | +| PEframe | Python | | PE | PE Static analyzer | +| Manalyze | C++ | | PE | PE Static analyzer | +| elf-dissector | C++ | | ELF | Tool to inspect ELF files | +| InfectPE | C++ | | PE | Inject code into PE file | +| termux-elf-cleaner | C++ | | ELF | Utility to remove unused ELF sections causing warnings. | +| vdexExtractor | C | | VDEX | Extract DEX from VDEX | +| insert_dylib | C | | Mach-O | Insert a dylib load command | +| optool | Obj-C | | Mach-O | Modify Mach-O commands: Resign, insert commands, ... | +| reflective- polymorphism | C | | PE | Transform PE files between EXE and DLL | +| XELFViewer | C++/Qt | | ELF | ELF file viewer/editor for Windows, Linux and macOS. | +| strongarm | Python | | Mach-O | Cross-platform ARM64 Mach-O analysis library | diff --git a/vendor/lief/doc/sphinx/references.rst b/vendor/lief/doc/sphinx/references.rst deleted file mode 100644 index 5193dec..0000000 --- a/vendor/lief/doc/sphinx/references.rst +++ /dev/null @@ -1,292 +0,0 @@ - -References -========== - -Blog Posts & White Papers --------------------------- - -.. role:: strike - :class: strike - -* 2021-06-03: `QBDL: QuarkslaB Dynamic Loader `_ -* 2021-04-27: `An Empirical Evaluation of Automated Machine LearningTechniques for Malware Detection - IWSPA 21 `_ -* 2021-01-25: `Static PE antimalware evasion - Francisco Javier Gomez Galvez `_ -* 2020-10-23: `[Write-up] Using a PIE binary as a Shared Library — HCSC-2020 CTF Writeup `_ by `István Tóth `_ -* 2020-02-04: `x0rro — A PE/ELF/MachO Crypter for x86 and x86_64 Based on Radare2 by phra `_ -* 2019-11-01: `Isolating the logic of an encrypted protocol with LIEF and kaitai `_ by `@TheXC3LL `_ -* 2018-10-26: `[Write-up] HITCON 2018 - Unexecutable `_ by `Andrew Wesie `_ -* 2018-10-06: `[Write-up] Flare-on Challenge (Level 3) `_ -* 2018-09-30: [Write-up] DragonCTF-Teaser-Brutal Oldskull by z3r0s -* 2018-09-07: `Using a non-system glibc `_ by `Ayrx `_ -* 2018-07-02: `PWN problem patch method commonly used in competition `_ -* 2018-05-03: `When SideChannelMarvels meet LIEF `_ -* 2018-03-11: `Fuzzing Arbitrary Functions in ELF Binaries `_ -* 2018-02-01: `Dissecting Mobile Native Code Packers Case Study `_ -* 2017-11-02: `Have Fun With LIEF and Executable Formats `_ -* 2017-04-04: `LIEF Library to Instrument Executable Formats `_ - -Projects using LIEF -------------------- - -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Name | Language | Link | Topic | Summarize | -+=================================+============+==============================================================================================================================+======================+==============================================================================================+ -| Maat | Python/C++ | https://maat.re/ | Symbol Execution | Symbolic Execution Framework based on Ghidra's sleigh | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| QBDL | Python/C++ | https://github.com/quarkslab/QBDL | Binary Loader | QBDI aims at providing a modular and portable way to dynamically load and link binaries. | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| BLint | Python | https://git.sr.ht/~prabhu/blint | Static Analysis | Binary Linter to check the security properties, and capabilities in your executables | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Datalog Disassembly | C++ | https://github.com/GrammaTech/ddisasm | Binary Analysis | DDisasm is a fast disassembler which is accurate enough for the resulting | -| | | | | assembly code to be reassembled. DDisasm is implemented using the datalog | -| | | | | (souffle) declarative logic programming language to compile disassembly rules and heuristics | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Mobile-Security-Framework-MobSF | Python | https://github.com/MobSF/Mobile-Security-Framework-MobSF | Mobile Analysis | Mobile Security Framework (MobSF) is an automated, all-in-one mobile application | -| | | | | (Android/iOS/Windows) pen-testing, malware analysis and security assessment | -| | | | | framework capable of performing static and dynamic analysis. | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| checksec.py | Python | https://github.com/Wenzel/checksec.py | Static Analysis | A simple tool to verify the security properties of your binaries. | -| | | | | These properties can be enabled by your compiler | -| | | | | to enforce the security of your executables, and mitigate exploits | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| youarespecial | Python | https://github.com/endgameinc/youarespecial | Machine Learning | Machine learning models on | -| | | | | Malwares | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| gym-malware | Python | https://github.com/endgameinc/gym-malware | Machine Learning | Learn how to bypass AV through | -| | | | | machine learning. | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| MISP | Python | https://github.com/MISP/MISP | Malware | Malware Information Sharing | -| | | | | Platform and Threat Sharing | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Virus Disinfector KIT | Python | https://github.com/Fare9/Virus_Disinfector_KIT | Malware | Tool to disinfect PE files | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| lief-sys | Rust | https://github.com/tathanhdinh/lief-sys | Binding | Rust binding for LIEF | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Ledger-Donjon/rainbow | Python | https://github.com/Ledger-Donjon/rainbow | Dynamic Analysis | Trace generator based on Unicorn | -| | | | | and LIEF as loader. | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| smda | Python | https://github.com/danielplohmann/smda | Static Analysis | Recursive disassembler using LIEF as | -| | | | | ELF and PE loader | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| conan-io/hooks | Python | `binary-linter.py `_ | Static Analysis | Binary linter | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Wiggle | Python | https://github.com/ChiChou/wiggle | Binary search engine | An executable binary metadata search engine. | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| ANBU | C++ | https://github.com/Fare9/ANBU | Unpacking | Automatic New Binary Unpacker with PIN DBI Framework | -+---------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ - -Similar Projects ----------------- - -+-----------+----------+-------------------------------------------+ -| Name | Language | Link | -+===========+==========+===========================================+ -| filebytes | Python | https://github.com/sashs/filebytes | -+-----------+----------+-------------------------------------------+ -| angr/cle | Python | https://github.com/angr/cle | -+-----------+----------+-------------------------------------------+ -| pypeelf | Python | https://github.com/crackinglandia/pypeelf | -+-----------+----------+-------------------------------------------+ -| object | Rust | https://github.com/gimli-rs/object | -+-----------+----------+-------------------------------------------+ -| Goblin | Rust | https://github.com/m4b/goblin | -+-----------+----------+-------------------------------------------+ - -Parsers/Modifiers ------------------ - -ELF -~~~ - -+--------------+----------+-----------------------------------------------------------------------+ -| Name | Language | Link | -+==============+==========+=======================================================================+ -| pyelftools | Python | https://github.com/eliben/pyelftools | -+--------------+----------+-----------------------------------------------------------------------+ -| pylibelf | Python | https://github.com/crackinglandia/pylibelf | -+--------------+----------+-----------------------------------------------------------------------+ -| pydevtools | Python | https://github.com/arowser/pydevtools | -+--------------+----------+-----------------------------------------------------------------------+ -| elfparser | C++ ? | http://elfparser.com/index.html | -+--------------+----------+-----------------------------------------------------------------------+ -| libelf | C | :strike:`hxxp://www.mr511.de/software/` | -+--------------+----------+-----------------------------------------------------------------------+ -| elfio | C++ | http://elfio.sourceforge.net/ | -+--------------+----------+-----------------------------------------------------------------------+ -| radare2 | C/Python | https://github.com/radare/radare2/tree/master/libr/bin/format/elf | -+--------------+----------+-----------------------------------------------------------------------+ -| node-elf | node.js | https://github.com/sifteo/node-elf | -+--------------+----------+-----------------------------------------------------------------------+ -| readelf | C | https://github.com/bminor/binutils-gdb/blob/master/binutils/readelf.c | -+--------------+----------+-----------------------------------------------------------------------+ -| elfesteem | Python | https://github.com/LRGH/elfesteem | -+--------------+----------+-----------------------------------------------------------------------+ -| elfsharp | C# | :strike:`hxxp://elfsharp.hellsgate.pl/index.shtml` | -+--------------+----------+-----------------------------------------------------------------------+ -| metasm | Ruby | https://github.com/jjyg/metasm | -+--------------+----------+-----------------------------------------------------------------------+ -| amoco | Python | https://github.com/bdcht/amoco | -+--------------+----------+-----------------------------------------------------------------------+ -| Goblin | Rust | https://github.com/m4b/goblin | -+--------------+----------+-----------------------------------------------------------------------+ -| Mithril | Ruby | https://github.com/jbangert/mithril | -+--------------+----------+-----------------------------------------------------------------------+ -| ELFkickers | C | http://www.muppetlabs.com/~breadbox/software/elfkickers.html | -+--------------+----------+-----------------------------------------------------------------------+ -| libelfmaster | C | https://github.com/elfmaster/libelfmaster | -+--------------+----------+-----------------------------------------------------------------------+ -| libelf.js | JS | https://github.com/AlexAltea/libelf.js | -+--------------+----------+-----------------------------------------------------------------------+ -| elfy.io | JS ? | https://elfy.io/ | -+--------------+----------+-----------------------------------------------------------------------+ -| elfhash | C | https://github.com/cjacker/elfhash | -+--------------+----------+-----------------------------------------------------------------------+ - - -PE -~~ - -+---------------+------------+--------------------------------------------------------------------------------+ -| Name | Language | Link | -+===============+============+================================================================================+ -| pefiles | Python | https://github.com/erocarrera/pefile | -+---------------+------------+--------------------------------------------------------------------------------+ -| radare2 | C | https://github.com/radare/radare2/tree/master/libr/bin/format/pe | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE.Explorer | C++/C# ? | http://www.pe-explorer.com/ | -+---------------+------------+--------------------------------------------------------------------------------+ -| CFF Explorer | C++/C# ? | http://www.ntcore.com/exsuite.php | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE Browser 64 | C++/C# ? | :strike:`http://www.smidgeonsoft.prohosting.com/pebrowse-pro-file-viewer.html` | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE View | C++/C# ? | http://wjradburn.com/software/ | -+---------------+------------+--------------------------------------------------------------------------------+ -| FileAlyzer | C++/C# ? | https://www.safer-networking.org/products/filealyzer/ | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE Studio | C++/C# ? | https://www.winitor.com/ | -+---------------+------------+--------------------------------------------------------------------------------+ -| PEDumper | C | https://github.com/maldevel/PEdumper | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE Parse | C++/Python | https://github.com/trailofbits/pe-parse | -+---------------+------------+--------------------------------------------------------------------------------+ -| PEParse | C# | https://github.com/DKorablin/PEReader | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE Bliss | C++ | https://github.com/BackupGGCode/portable-executable-library | -+---------------+------------+--------------------------------------------------------------------------------+ -| PE Net | .NET | https://github.com/secana/PeNet | -+---------------+------------+--------------------------------------------------------------------------------+ -| libpe | C++ | https://github.com/evilsocket/libpe/tree/master/libpe | -+---------------+------------+--------------------------------------------------------------------------------+ -| elfesteem | Python | https://github.com/LRGH/elfesteem | -+---------------+------------+--------------------------------------------------------------------------------+ -| pelook | C ? | http://bytepointer.com/tools/index.htm#pelook | -+---------------+------------+--------------------------------------------------------------------------------+ -| PortEx | Java | https://github.com/struppigel/PortEx | -+---------------+------------+--------------------------------------------------------------------------------+ -| metasm | Ruby | https://github.com/jjyg/metasm | -+---------------+------------+--------------------------------------------------------------------------------+ -| amoco | Python | https://github.com/bdcht/amoco | -+---------------+------------+--------------------------------------------------------------------------------+ -| Goblin | Rust | https://github.com/m4b/goblin | -+---------------+------------+--------------------------------------------------------------------------------+ - -Mach-O -~~~~~~ - -+--------------+----------+---------------------------------------------------------------------+ -| Name | Language | Link | -+==============+==========+=====================================================================+ -| radare2 | C | https://github.com/radare/radare2/tree/master/libr/bin/format/mach0 | -+--------------+----------+---------------------------------------------------------------------+ -| MachO-Kit | C/ObjC | https://github.com/DeVaukz/MachO-Kit | -+--------------+----------+---------------------------------------------------------------------+ -| optool | ObjC | https://github.com/alexzielenski/optool | -+--------------+----------+---------------------------------------------------------------------+ -| macho_edit | C++ | https://github.com/Tyilo/macho_edit | -+--------------+----------+---------------------------------------------------------------------+ -| macholib | Python | https://pypi.org/project/macholib/ | -+--------------+----------+---------------------------------------------------------------------+ -| elfsharp | C# | :strike:`http://elfsharp.hellsgate.pl/index.shtml` | -+--------------+----------+---------------------------------------------------------------------+ -| elfesteem | Python | https://github.com/LRGH/elfesteem | -+--------------+----------+---------------------------------------------------------------------+ -| metasm | Ruby | https://github.com/jjyg/metasm | -+--------------+----------+---------------------------------------------------------------------+ -| Goblin | Rust | https://github.com/m4b/goblin | -+--------------+----------+---------------------------------------------------------------------+ -| MachOView | ObjC | https://github.com/gdbinit/MachOView | -+--------------+----------+---------------------------------------------------------------------+ -| XMachOViewer | C++ | https://github.com/horsicq/XMachOViewer | -+--------------+----------+---------------------------------------------------------------------+ - - -Tools ------ - -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| Name | Language | Link | Format | Summarize | -+====================+==========+========================================================+==============+======================================================+ -| Dress | Python | https://github.com/docileninja/dress | ELF | Add static symbols | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| objconv | C++ | https://www.agner.org/optimize/#objconv | ELF/PE/MachO | Format converter | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| PEDetour | C++ | https://github.com/chen-charles/PEDetour | PE | Hook exported functions | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| python-elf | Python | https://github.com/tbursztyka/python-elf | ELF | ELF binary format | -| | | | | manipulation | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| PEDetour | C++ | https://github.com/chen-charles/PEDetour | PE | Hook exported functions | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| libmaelf | C | https://github.com/tiago4orion/libmalelf | ELF | Library for Dissect and | -| | | | | Infect ELF Binaries. | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| peinjector | C | https://github.com/JonDoNym/peinjector | PE | MITM PE file infector | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| backdoor | C++ | https://github.com/secretsquirrel/the-backdoor-factory | ELF/PE/MachO | Patch PE, ELF, Mach-O | -| factory | | | | binaries with shellcode | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| RePEconstruct | C | https://github.com/DavidKorczynski/RePEconstruct | PE | PE Unpacker | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| patchkit | Python | https://github.com/lunixbochs/patchkit | ELF | Patch binary | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| unstrip | Python | https://github.com/pzread/unstrip | ELF | Unstrip static binary | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| sym2elf | Python | https://github.com/danigargu/syms2elf | ELF | Export IDA's symbols to | -| | | | | the original binary | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| elfhash | C | https://github.com/cjacker/elfhash | ELF | Manipulate ELF's hash | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| recomposer | Python | https://github.com/secretsquirrel/recomposer | PE | Change some parts of a | -| | | | | PE ile in order to bypass | -| | | | | Antivirus | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| bearparser | C++ | https://github.com/hasherezade/bearparser | PE | Portable Executable parsing | -| | | | | library with a GUI | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| IAT patcher | C++ | http://hasherezade.github.io/IAT_patcher | PE | IAT hooking application | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| PEframe | Python | https://github.com/guelfoweb/peframe | PE | PE Static analyzer | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| Manalyze | C++ | https://github.com/JusticeRage/Manalyze | PE | PE Static analyzer | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| elf-dissector | C++ | https://github.com/KDE/elf-dissector | ELF | Tool to inspect ELF files | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| InfectPE | C++ | https://github.com/secrary/InfectPE | PE | Inject code into PE file | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| termux-elf-cleaner | C++ | https://github.com/termux/termux-elf-cleaner | ELF | Utility to remove unused ELF | -| | | | | sections causing warnings. | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| vdexExtractor | C | https://github.com/anestisb/vdexExtractor | VDEX | Extract DEX from VDEX | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| insert_dylib | C | https://github.com/Tyilo/insert_dylib | Mach-O | Insert a dylib load command | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| optool | Obj-C | https://github.com/alexzielenski/optool | Mach-O | Modify Mach-O commands: | -| | | | | Resign, insert commands, ... | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| reflective- | C | https://github.com/zeroSteiner/reflective-polymorphism | PE | Transform PE files between | -| polymorphism | | | | EXE and DLL | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| XELFViewer | C++/Qt | https://github.com/horsicq/XELFViewer | ELF | ELF file viewer/editor for Windows, Linux and MacOS. | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ -| strongarm | Python | https://github.com/datatheorem/strongarm | Mach-O | Cross-platform ARM64 Mach-O analysis library | -+--------------------+----------+--------------------------------------------------------+--------------+------------------------------------------------------+ diff --git a/vendor/lief/doc/sphinx/runtime/components/host.md b/vendor/lief/doc/sphinx/runtime/components/host.md new file mode 100644 index 0000000..59df9ed --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/components/host.md @@ -0,0 +1,103 @@ +--- +description: Query the hostname, user directories, and platform-specific host information with the LIEF runtime API. +--- + +(runtime_host)= + +# {fa}`solid fa-server` Host + +The {sub-ref}`lief-runtime-host` interface exposes an API to query information about +the host on which LIEF is running. It provides a cross-platform API for +common values like the hostname and user directories for configuration, cache, +and temporary files. +Use {ref}`Process ` for process-specific information such as +the PID and page size. + +## {fa}`solid fa-globe` Cross-platform + +The following snippet illustrates how to retrieve the generic host +information that is available on every supported platform: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "host") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "host") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "host") }} +::: +:::: + +## {fa}`brands fa-linux` Linux + +The {sub-ref}`lief-runtime-linux-host` interface exposes Linux-specific host information: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "host-linux") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "host-linux") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "host-linux") }} +::: +:::: + +## {fa}`brands fa-windows` Windows + +The {sub-ref}`lief-runtime-windows-host` interface exposes Windows-specific host +information such as the operating system version +({sub-ref}`lief-runtime-windows-host-version`): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_windows.py", "host-windows") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_windows.cpp", "host-windows") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_windows.rs", "host-windows") }} +::: +:::: + +## {fa}`brands fa-apple` macOS + +The {sub-ref}`lief-runtime-osx-host` interface exposes macOS-specific host +information such as whether System Integrity +Protection is enabled ({sub-ref}`lief-runtime-osx-host-is-sip-enabled`): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_osx.py", "host-osx") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_osx.cpp", "host-osx") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_osx.rs", "host-osx") }} +::: +:::: + +## {fa}`brands fa-android` Android + +The {sub-ref}`lief-runtime-android-host` interface exposes Android-specific host +information such as the device's SDK/API level +({sub-ref}`lief-runtime-android-host-sdk_version`): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_android.py", "host-android") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_android.cpp", "host-android") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_android.rs", "host-android") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/components/memory.md b/vendor/lief/doc/sphinx/runtime/components/memory.md new file mode 100644 index 0000000..0f8a04f --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/components/memory.md @@ -0,0 +1,146 @@ +--- +description: Allocate, read, write, and release process memory with LIEF, then explore platform-specific assembly and disassembly examples. +--- + +(runtime_memory)= + +# {fa}`solid fa-memory` Memory + +The {sub-ref}`lief-runtime-memory` interface exposes an API to allocate, inspect and +manipulate memory in the current process. It can be used to map anonymous +pages, change their protection, and read or write bytes at valid mapped addresses. + +## Allocate, write, and read memory + +Start with a writable allocation and release it when finished. This Python +example uses the process's page size and checks whether allocation succeeded: + +```python +import lief +from lief.runtime import Memory, Process + +if not lief.runtime.enabled: + raise RuntimeError("Install or build LIEF with runtime support") + +chunk = Memory.mmap( + Process.page_size, + Memory.ANONYMOUS | Memory.PRIVATE, + Memory.READ | Memory.WRITE, +) +if chunk is None: + raise RuntimeError("Memory allocation failed") + +try: + message = b"LIEF runtime" + Memory.write(message, chunk.addr) + print(Memory.read(chunk.addr, len(message))) +finally: + chunk.deallocate() +``` + +The allocation is represented by a {sub-ref}`lief-runtime-memory-chunk`. + +If placement matters, {sub-ref}`lief-runtime-memory-mmap_hint` accepts a preferred +address. Always use the address in the returned chunk: a hint does not guarantee +the requested location. + +## Generate and inspect code + +Combined with {sub-ref}`lief-runtime-assemble`, it enables lightweight JIT +code generation directly from LIEF, while {sub-ref}`lief-runtime-disassemble` can be +used to disassemble code directly from memory. + +### {fa}`brands fa-linux` Linux x86-64 + +The following snippet allocates a writable and executable page, assembles a +small x86-64 stub inside it that prints `LIEF Runtime Extended Demo`, calls +the resulting function, and rewrites part of the buffer before invoking it +again: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "memory") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "memory") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "memory") }} +::: +:::: + +### {fa}`brands fa-windows` Windows ARM64 + +:::{admonition} x86-64 +:class: tip + +This part focuses on the ARM64 architecture but it works in the exact same way +for Windows x86-64. +::: + +Similarly, we can JIT a `Hello World` shellcode on Windows ARM64 with the +following snippet: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_windows.py", "memory") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_windows.cpp", "memory") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_windows.rs", "memory") }} +::: +:::: + +Note that this shellcode uses the external functions `GetStdHandle` and +`WriteFile` that are **dynamically** resolved and injected into the shellcode +**at runtime**. The shellcode is thus generated with dynamic information that +would otherwise have been tedious to resolve at the assembly level. + +### {fa}`brands fa-apple` macOS ARM64 + +:::{admonition} SIP +:class: warning + +Allocating and executing JIT memory on macOS requires System Integrity +Protection (SIP) to be disabled. The snippet below therefore only runs the +JIT part when {sub-ref}`lief-runtime-osx-host-is-sip-enabled` reports that SIP is +disabled. +::: + +Similarly, we can JIT a `Hello World` shellcode on macOS ARM64. The shellcode +calls `write`, which is **dynamically** resolved from `libSystem` at +runtime: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_osx.py", "memory") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_osx.cpp", "memory") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_osx.rs", "memory") }} +::: +:::: + +### {fa}`brands fa-android` Android ARM64 + +Similarly, we can JIT a small AArch64 stub on Android to print +`LIEF Runtime Extended Demo`. The Python tab calls `write`, +which is **dynamically** resolved from Bionic `libc` at runtime: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_android.py", "memory") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_android.cpp", "memory") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_android.rs", "memory") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/components/memory_layout.md b/vendor/lief/doc/sphinx/runtime/components/memory_layout.md new file mode 100644 index 0000000..d85b39d --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/components/memory_layout.md @@ -0,0 +1,111 @@ +--- +description: Inspect mapped memory regions with LIEF Extended, calculate virtual address-space usage, and locate mappings by address or name. +--- + +(runtime_memory_layout)= + +# {fa}`solid fa-map` Memory Layout + +The {sub-ref}`lief-runtime-memorylayout` interface exposes the memory layout of +the **current** process: the regions that are mapped in its address space. + +## Enumerate mapped regions + +{sub-ref}`lief-runtime-memory_layout` returns an iterator over these +regions, ordered by address: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/memory_layout.py", "iterate") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/memory_layout.cpp", "iterate") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/memory_layout.rs", "iterate") }} +::: +:::: + +For illustration, a Linux process running `/usr/bin/cat` could have this layout: + +```{code-block} text +0x563668f9d000-0x563668f9f000 /usr/bin/cat +0x563668f9f000-0x563668fa6000 /usr/bin/cat +0x563668fa6000-0x563668fa9000 /usr/bin/cat +0x563668fa9000-0x563668faa000 /usr/bin/cat +0x563668faa000-0x563668fab000 /usr/bin/cat +0x56367cb52000-0x56367cb73000 [heap] +0x7f2d28e00000-0x7f2d29196000 /usr/lib/locale/locale-archive +0x7f2d291be000-0x7f2d29200000 +0x7f2d29200000-0x7f2d29224000 /usr/lib/libc.so.6 +[...] +0x7f2d29478000-0x7f2d2947a000 [vdso] +0x7f2d2947a000-0x7f2d2947b000 /lib64/ld-linux-x86-64.so.2 +[...] +0x7ffd162f1000-0x7ffd16312000 [stack] +0xffffffffff600000-0xffffffffff601000 [vsyscall] +``` + +A {sub-ref}`lief-runtime-memorylayout-region` describes a half-open address range: +the start address is included, and the end address is excluded. Its name can be: + +- the name or the path of the module mapped at this address + (e.g. `/usr/lib/libc.so.6`); +- the identifier of a region that is not backed by a file + (e.g. `[stack]`, `[heap]`, `[vdso]`); +- **empty**, for anonymous regions. + +As shown in the output above, a module is not mapped as a single region: it +usually gets one region per set of permissions. + +Names and mappings depend on the operating system and can change as the process +allocates memory or loads libraries. A region describes a mapping: it does not +own the mapped memory. + +## {fa}`solid fa-magnifying-glass` Inspecting the layout + +The following snippet iterates over the memory layout to: + +- Compute the total mapped size +- Group that size by region name +- Locate the region containing a given address + +These totals measure virtual address space. They are not resident-memory (RSS) +measurements, and grouping anonymous regions combines unrelated allocations. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/memory_layout.py", "inspect") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/memory_layout.cpp", "inspect") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/memory_layout.rs", "inspect") }} +::: +:::: + +## {fa}`brands fa-linux` Linux / {fa}`brands fa-android` Android + +On Linux and Android, named mappings such as `[stack]` and `[heap]` can be located +when present. They do not account for every thread stack or allocator-managed +allocation: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../code/python/memory_layout.py", "stack-heap") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../code/cpp/memory_layout.cpp", "stack-heap") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../code/rust/src/memory_layout.rs", "stack-heap") }} +::: +:::: + +```text +[heap]: 0x56367cb52000-0x56367cb73000 +[stack]: 0x7ffd162f1000-0x7ffd16312000 +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/components/modules.md b/vendor/lief/doc/sphinx/runtime/components/modules.md new file mode 100644 index 0000000..6ea299a --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/components/modules.md @@ -0,0 +1,132 @@ +--- +description: Enumerate loaded modules, resolve symbols, parse files and in-memory images, and interpret live addresses with the LIEF runtime API. +--- + +(runtime_modules)= + +# {fa}`solid fa-cubes` Modules + +The {sub-ref}`lief-runtime-module` interface exposes the different modules +(executables and shared libraries) that are loaded in the current process. +It is a cross-platform API and is extended on each supported platform with +OS-specific helpers (e.g. {sub-ref}`lief-runtime-linux-module`, +{sub-ref}`lief-runtime-windows-module`, {sub-ref}`lief-runtime-osx-module`). + +## Enumerate and locate modules + +The following Linux example enumerates the loaded modules, prints their +attributes, and selects `libc` for later inspection. The enumeration API is shared +by all supported platforms: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "modules") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "modules") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "modules") }} +::: +:::: + +For a direct lookup, use {sub-ref}`lief-runtime-module_from_name`, +{sub-ref}`lief-runtime-module_from_path`, or {sub-ref}`lief-runtime-module_from_addr`. +Name and path lookups use exact matches. Address lookup expects an absolute +address in the current process. + +The platform-specific module interfaces let you parse an image from its path on +disk or from its current mapping: + +| Operation | Result | +| --- | --- | +| Parse from the module's path | The executable file as stored on disk, using its file layout | +| Parse from memory | The loaded image, which may contain relocations and runtime changes | +| {sub-ref}`lief-runtime-module-dump` | Raw bytes from the module's mapped address range | + +Parsing produces a LIEF binary object for analysis. Modifying that object does +not automatically patch the running module. You should use the {ref}`memory API ` +when you intend to write to the process's memory. + +A raw memory dump is not necessarily a valid on-disk executable. For offline +analysis, use the dump-parsing APIs documented for {ref}`ELF `, +{ref}`PE `, and {ref}`Mach-O `. + +## {fa}`brands fa-linux` Linux + +On Linux, {sub-ref}`lief-runtime-linux-module` extends the generic interface with +platform-specific helpers. In particular, it exposes the {sub-ref}`lief-runtime-linux-dlopen` +& {sub-ref}`lief-runtime-linux-module-dlsym` and can parse the +module directly from its path on disk or from its in-memory representation. +The following snippet demonstrates these operations on the `libc` module: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "modules-linux") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "modules-linux") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "modules-linux") }} +::: +:::: + +## {fa}`brands fa-windows` Windows + +On Windows, you can perform similar operations such as in-memory parsing, accessing +the `HMODULE` handle, and resolving functions through a dlsym-like helper: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_windows.py", "modules-windows") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_windows.cpp", "modules-windows") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_windows.rs", "modules-windows") }} +::: +:::: + +## {fa}`brands fa-apple` macOS + +System libraries can be located in the {ref}`Dyld shared cache ` even +when their module paths look like ordinary files. In that case, parsing from the +path can fail. The example below parses the mapped library from memory and lists +its exported symbols: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_osx.py", "modules-osx") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_osx.cpp", "modules-osx") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_osx.rs", "modules-osx") }} +::: +:::: + +## {fa}`brands fa-android` Android + +On Android, {sub-ref}`lief-runtime-android-module` extends the generic interface with +the same helpers as on Linux: loading a library with +{sub-ref}`lief-runtime-android-dlopen`, resolving symbols with +{sub-ref}`lief-runtime-android-module-dlsym` and parsing modules from their path on +disk. The following snippet +demonstrates these operations on the Bionic `libc` and `liblog` modules: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_android.py", "modules-android") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_android.cpp", "modules-android") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_android.rs", "modules-android") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/components/process.md b/vendor/lief/doc/sphinx/runtime/components/process.md new file mode 100644 index 0000000..85601a5 --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/components/process.md @@ -0,0 +1,118 @@ +--- +description: Inspect the current process and thread IDs, page size, environment variables, and platform-specific loader information with LIEF. +--- + +(runtime_process)= + +# {fa}`solid fa-gears` Process + +The {sub-ref}`lief-runtime-process` interface exposes an API to query information +about the current process. It provides cross-platform API and is extended +on each platform with additional OS-specific helpers. + +## Query the current process + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "process") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "process") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "process") }} +::: +:::: + +## {fa}`brands fa-linux` Linux + +On Linux, {sub-ref}`lief-runtime-linux-process` extends the generic interface with +platform-specific helpers. For instance, +{sub-ref}`lief-runtime-linux-process-glibc_version` returns the version of the GNU +C Library loaded in the current process: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_linux.py", "process-linux") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_linux.cpp", "process-linux") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_linux.rs", "process-linux") }} +::: +:::: + +## {fa}`brands fa-windows` Windows + +On Windows, the process interface is extended with +{sub-ref}`lief-runtime-windows-process` which exposes the Process Environment +Block (PEB) of the current process. The returned {sub-ref}`lief-runtime-windows-peb` +object provides access to some fields of the structure (whether the +process is being debugged, the loader data, the process parameters, ...): + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_windows.py", "process-windows") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_windows.cpp", "process-windows") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_windows.rs", "process-windows") }} +::: +:::: + +The loader's module list is exposed through {sub-ref}`lief-runtime-windows-peb-entries`, +which yields {sub-ref}`lief-runtime-windows-ldr` objects. In addition to +the base name and image base, each entry exposes the extended +`LDR_DATA_TABLE_ENTRY` fields. + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_windows.py", "peb-module-details") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_windows.cpp", "peb-module-details") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_windows.rs", "peb-module-details") }} +::: +:::: + +## {fa}`brands fa-apple` macOS + +On macOS, {sub-ref}`lief-runtime-osx-process` extends the generic interface with +platform-specific helpers. For instance, {sub-ref}`lief-runtime-osx-process-dyld_version` +returns the version of `dyld` (the dynamic loader) in the current process: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_osx.py", "process-osx") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_osx.cpp", "process-osx") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_osx.rs", "process-osx") }} +::: +:::: + +## {fa}`brands fa-android` Android + +On Android, {sub-ref}`lief-runtime-android-process` extends the generic interface. Here are +some examples of the API: + +::::{tabs} +:::{tab} {fa}`brands fa-python` Python +{{ literalinclude("../../../../api/python/examples/runtime_android.py", "process-android") }} +::: +:::{tab} {fa}`regular fa-file-code` C++ +{{ literalinclude("../../../../examples/cpp/runtime_android.cpp", "process-android") }} +::: +:::{tab} {fa}`brands fa-rust` Rust +{{ literalinclude("../../../../api/rust/examples/src/bin/runtime_android.rs", "process-android") }} +::: +:::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/cpp.md b/vendor/lief/doc/sphinx/runtime/cpp.md new file mode 100644 index 0000000..1fafa30 --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/cpp.md @@ -0,0 +1,249 @@ +# {fa}`regular fa-file-code` C++ + +## {fa}`solid fa-screwdriver-wrench` Utilities + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::is_enabled() +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::platform() +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::arch() +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::modules() +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::assemble(uint64_t, const std::string&, assembly::AssemblerConfig&) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::disassemble(uintptr_t) +``` + +______________________________________________________________________ + +## {fa}`solid fa-gears` Process + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Process +``` + +______________________________________________________________________ + +## {fa}`solid fa-server` Host + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Host +``` + +______________________________________________________________________ + +## {fa}`solid fa-cubes` Module + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Module +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::module_from_name(const std::string &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::module_from_path(const std::string &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::module_from_addr(uintptr_t) +``` + +______________________________________________________________________ + +## {fa}`solid fa-memory` Memory + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Memory +``` + +______________________________________________________________________ + +## {fa}`solid fa-map` MemoryLayout + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::MemoryLayout +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::memory_layout() +``` + +______________________________________________________________________ + +## {fa}`brands fa-linux` Linux + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Linux::Module +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::Linux::dlopen(const std::string &) + +``` + +______________________________________________________________________ + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Linux::Host + +``` + +______________________________________________________________________ + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::Linux::Process + +``` + +______________________________________________________________________ + +## {fa}`brands fa-android` Android + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::android::Module +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::android::dlopen(const std::string &) + +``` + +______________________________________________________________________ + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::android::Host + +``` + +______________________________________________________________________ + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::android::Process + +``` + +### {fa}`solid fa-tag` Property + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::android::Property + +``` + +______________________________________________________________________ + +## {fa}`brands fa-apple` macOS + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::osx::Module +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::osx::dlopen(const std::string &) +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::osx::Host +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::osx::Process + +``` + +______________________________________________________________________ + +## {fa}`brands fa-windows` Windows + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::windows::Module +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::windows::dlopen(const std::string &) +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::windows::find_module(const std::string &) +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::windows::Host +``` + +### {fa}`solid fa-syringe` Injector + +```{eval-rst} +.. doxygenstruct:: LIEF::runtime::windows::injection_context_t +``` + +```{eval-rst} +.. doxygenfunction:: LIEF::runtime::windows::inject_spawn(const injection_context_t &) +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::windows::Process +``` + +### {fa}`solid fa-box` PEB + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::windows::PEB +``` + +### {fa}`solid fa-table-list` LdrDataTableEntry + +```{eval-rst} +.. doxygenclass:: LIEF::runtime::windows::LdrDataTableEntry +``` + +______________________________________________________________________ + +## {fa}`solid fa-microchip` ARCH + +```{eval-rst} +.. doxygenenum:: LIEF::runtime::ARCH +``` + +## {fa}`solid fa-desktop` PLATFORMS + +```{eval-rst} +.. doxygenenum:: LIEF::runtime::PLATFORMS +``` diff --git a/vendor/lief/doc/sphinx/runtime/intro.md b/vendor/lief/doc/sphinx/runtime/intro.md new file mode 100644 index 0000000..29dae69 --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/intro.md @@ -0,0 +1,115 @@ +--- +description: Enable LIEF's runtime API and inspect the current process, loaded modules, host information, and memory in Python, C++, and Rust. +--- + +(runtime-intro)= + +# {fa}`solid fa-wand-magic-sparkles` Runtime + +```{eval-rst} +.. toctree:: + :caption:  Components + :maxdepth: 1 + + components/host + components/process + components/memory + components/memory_layout + components/modules +``` + +```{eval-rst} +.. toctree:: + :caption:  API + :maxdepth: 1 + + cpp + python + rust +``` + +## Introduction + +LIEF's runtime module provides facilities to inspect and interact with the +current process in which the API is used. You can, for instance, list +modules loaded in memory or read the content at a specific memory address. + +These runtime features are **not** enabled by default and must be explicitly +turned on when compiling LIEF. + +When using CMake, you must enable the `LIEF_RUNTIME` option (`-DLIEF_RUNTIME=ON`) +followed by the target platform and the architecture for which you want to use +the runtime API: + +```console +$ cmake [...] \ + -DLIEF_RUNTIME=ON \ + -DLIEF_RUNTIME_PLATFORM=windows \ + -DLIEF_RUNTIME_ARCH=arm64 +``` + +:::{note} +Only `arm64`, `x86_64` and `riscv64` are currently supported for +`LIEF_RUNTIME_ARCH`. The supported values for `LIEF_RUNTIME_PLATFORM` +are `linux`, `windows`, `android` and `osx`. +::: + +To compile the Python bindings with the runtime features, +you must enable the `lief.features.runtime` option and specify the +target platform and architecture within the `[lief.runtime]` block: + +```{code-block} toml +:emphasize-lines: 20,22-24 + +[lief.build] +type = "Release" +cache = true +ninja = true +parallel-jobs = 0 + +[lief.formats] +elf = true +pe = true +macho = true +android = true +art = true +vdex = true +oat = true +dex = true + +[lief.features] +json = true +frozen = true +runtime = true + +[lief.runtime] +platform = 'linux' +architecture = 'x86_64' +``` + +The runtime features are split in the following components: + +```{eval-rst} +.. toctree:: + :caption:  Components + :maxdepth: 1 + + components/host + components/process + components/memory + components/memory_layout + components/modules +``` + +## API reference + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + cpp + python + rust +``` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/runtime/python.md b/vendor/lief/doc/sphinx/runtime/python.md new file mode 100644 index 0000000..fbd6841 --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/python.md @@ -0,0 +1,249 @@ +# {fa}`brands fa-python` Python + +:::{admonition} Python `void*` +:class: warning + +The Python bindings manage opaque `void*` pointers as +[Capsules](https://docs.python.org/3/c-api/capsule.html#capsules). +Given a Capsule, there is no easy way to convert it into a raw address and vice +versa. +To address this limitation, LIEF exposes {py:func}`lief.to_int` and {py:func}`lief.to_ptr` +to convert back and forth between raw addresses and pointers. +::: + +## {fa}`solid fa-screwdriver-wrench` Utilities + +```{eval-rst} +.. autofunction:: lief.to_int +``` + +```{eval-rst} +.. autofunction:: lief.to_ptr +``` + +```{eval-rst} +.. autoattribute:: lief.runtime.enabled +``` + +```{eval-rst} +.. autoattribute:: lief.runtime.platform +``` + +```{eval-rst} +.. autoattribute:: lief.runtime.arch +``` + +```{eval-rst} +.. autofunction:: lief.runtime.modules +``` + +```{eval-rst} +.. autofunction:: lief.runtime.assemble +``` + +```{eval-rst} +.. autofunction:: lief.runtime.disassemble +``` + +______________________________________________________________________ + +## {fa}`solid fa-server` Host + +```{eval-rst} +.. autoclass:: lief.runtime.Host +``` + +______________________________________________________________________ + +## {fa}`solid fa-gears` Process + +```{eval-rst} +.. autoclass:: lief.runtime.Process +``` + +______________________________________________________________________ + +## {fa}`solid fa-cubes` Module + +```{eval-rst} +.. autoclass:: lief.runtime.Module +``` + +```{eval-rst} +.. autofunction:: lief.runtime.module_from_name +``` + +```{eval-rst} +.. autofunction:: lief.runtime.module_from_path +``` + +```{eval-rst} +.. autofunction:: lief.runtime.module_from_addr +``` + +______________________________________________________________________ + +## {fa}`solid fa-memory` Memory + +```{eval-rst} +.. autoclass:: lief.runtime.Memory +``` + +______________________________________________________________________ + +## {fa}`solid fa-map` MemoryLayout + +```{eval-rst} +.. autoclass:: lief.runtime.MemoryLayout +``` + +```{eval-rst} +.. autofunction:: lief.runtime.memory_layout +``` + +______________________________________________________________________ + +## {fa}`brands fa-linux` Linux + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. autoclass:: lief.runtime.linux.Module +``` + +```{eval-rst} +.. autofunction:: lief.runtime.linux.dlopen +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. autoclass:: lief.runtime.linux.Host +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. autoclass:: lief.runtime.linux.Process + +``` + +______________________________________________________________________ + +## {fa}`brands fa-android` Android + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. autoclass:: lief.runtime.android.Module +``` + +```{eval-rst} +.. autofunction:: lief.runtime.android.dlopen +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. autoclass:: lief.runtime.android.Host +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. autoclass:: lief.runtime.android.Process +``` + +### {fa}`solid fa-tag` Property + +```{eval-rst} +.. autoclass:: lief.runtime.android.Property +``` + +______________________________________________________________________ + +## {fa}`brands fa-apple` macOS + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. autoclass:: lief.runtime.osx.Module +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. autoclass:: lief.runtime.osx.Host +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. autoclass:: lief.runtime.osx.Process +``` + +______________________________________________________________________ + +## {fa}`brands fa-windows` Windows + +### {fa}`solid fa-cubes` Module + +```{eval-rst} +.. autoclass:: lief.runtime.windows.Module +``` + +```{eval-rst} +.. autofunction:: lief.runtime.windows.dlopen +``` + +```{eval-rst} +.. autofunction:: lief.runtime.windows.find_module +``` + +### {fa}`solid fa-server` Host + +```{eval-rst} +.. autoclass:: lief.runtime.windows.Host +``` + +### {fa}`solid fa-syringe` Injector + +```{eval-rst} +.. autoclass:: lief.runtime.windows.injection_context_t +``` + +```{eval-rst} +.. autofunction:: lief.runtime.windows.inject_spawn +``` + +### {fa}`solid fa-gears` Process + +```{eval-rst} +.. autoclass:: lief.runtime.windows.Process +``` + +### {fa}`solid fa-box` PEB + +```{eval-rst} +.. autoclass:: lief.runtime.windows.PEB +``` + +### {fa}`solid fa-table-list` LdrDataTableEntry + +```{eval-rst} +.. autoclass:: lief.runtime.windows.LdrDataTableEntry +``` + +______________________________________________________________________ + +## {fa}`solid fa-microchip` ARCH + +```{eval-rst} +.. autoclass:: lief.runtime.ARCH +``` + +## {fa}`solid fa-desktop` PLATFORMS + +```{eval-rst} +.. autoclass:: lief.runtime.PLATFORMS +``` diff --git a/vendor/lief/doc/sphinx/runtime/rust.md b/vendor/lief/doc/sphinx/runtime/rust.md new file mode 100644 index 0000000..e5d8bd6 --- /dev/null +++ b/vendor/lief/doc/sphinx/runtime/rust.md @@ -0,0 +1,5 @@ +# {fa}`brands fa-rust` Rust + +:::{note} +Please check: {rust:module}`lief::runtime` +::: diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/__init__.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/ai.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/ai.py new file mode 100644 index 0000000..bd806bb --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/ai.py @@ -0,0 +1,495 @@ +import hashlib +import json +import re +from collections import Counter +from html import escape +from pathlib import Path +from urllib.parse import quote, urldefrag, urljoin + +from bs4 import BeautifulSoup, Tag +from markdown_it import MarkdownIt +from markdownify import MarkdownConverter +from sphinx.application import Sphinx +from sphinx.errors import ExtensionError +from sphinx.util import logging + +logger = logging.getLogger(__name__) +PLAIN_PARSER = MarkdownIt("commonmark").enable("table") + + +def digest(text: str) -> str: + return hashlib.sha256(text.encode("utf-8")).hexdigest() + + +def serialize(value) -> str: + return json.dumps(value, ensure_ascii=False, sort_keys=True) + + +def plain_text(markdown: str) -> str: + soup = BeautifulSoup(PLAIN_PARSER.render(markdown), "lxml") + return " ".join(soup.get_text(" ", strip=True).split()) + + +def inline_code(text: str) -> str: + fence = "`" * (1 + max((len(x) for x in re.findall(r"`+", text)), default=0)) + return f"{fence} {text} {fence}" + + +class DocumentationMarkdown(MarkdownConverter): + """Keep Sphinx signatures, code, tabs, and citation targets readable.""" + + def __init__(self, canonical: str): + super().__init__(heading_style="ATX", bullets="-", autolinks=False) + self.canonical = canonical + self.headings: dict[str, dict] = {} + + def escape(self, text, parent_tags): + # Template arguments and comparison operators are text, not HTML tags. + return super().escape(escape(text, quote=False), parent_tags) + + def heading(self, level: int, title: str, fragment: str, *, code=False) -> str: + title = " ".join(title.split()) + url = self.canonical + (f"#{fragment}" if fragment else "") + label = ( + inline_code(title) + if code + else self.escape(title, set()).replace("[", r"\[").replace("]", r"\]") + ) + line = f"{'#' * level} [{label}](<{url}>)" + self.headings[line] = { + "heading": title, + "headingLevel": level, + "url": url, + } + return f"\n\n{line}\n\n" + + def convert_hN(self, n, el, text, parent_tags): + fragment = el.get("id", "") + if not fragment and el.parent.name == "section": + fragment = el.parent.get("id", "") + return self.heading(n, el.get_text(), fragment) + + def convert_dt(self, el, text, parent_tags): + if "sig-object" not in el.get("class", ()) or not el.get("id"): + return f"\n\n**{text.strip()}**\n\n" + section = el.find_parent("section") + title = ( + section.find(re.compile(r"^h[1-6]$"), recursive=False) if section else None + ) + depth = int(title.name[1]) if title else 1 + depth = min(6, depth + len(el.find_parents("dl"))) + names = el.select(".sig-prename, .sig-name") + name = "".join(node.get_text() for node in names) or el.get_text() + return self.heading(depth, name, el["id"], code=True) + text.strip() + "\n\n" + + def convert_dd(self, el, text, parent_tags): + # Definition-list indentation would turn nested API entries into code. + return f"\n\n{text.strip()}\n\n" + + def convert_pre(self, el, text, parent_tags): + code = el.get_text().rstrip("\n") + language = "" + for ancestor in [el, *el.parents]: + for cls in ancestor.get("class", ()): + if cls.startswith(("highlight-", "language-")): + language = cls.split("-", 1)[1] + break + if language: + break + fence = "`" * max( + 3, 1 + max((len(x) for x in re.findall(r"`+", code)), default=0) + ) + return f"\n\n{fence}{language}\n{code}\n{fence}\n\n" + + def convert_div(self, el, text, parent_tags): + if "admonition" in el.get("class", ()): + return ( + "\n\n" + + "\n".join("> " + line for line in text.strip().splitlines()) + + "\n\n" + ) + return super().convert_div(el, text, parent_tags) + + def convert_p(self, el, text, parent_tags): + if "admonition-title" in el.get("class", ()): + text = f"**{text.strip()}**" + return super().convert_p(el, text, parent_tags) + + def convert_a(self, el, text, parent_tags): + # Angle brackets preserve URLs containing parentheses in API anchors. + href = el.get("href") + if href: + el["href"] = "<" + quote(href, safe="/:#?&=@+!$'()*;,%-._~") + ">" + result = super().convert_a(el, text, parent_tags) + if href: + el["href"] = href + return result + + def convert_td(self, el, text, parent_tags): + return super().convert_td(el, text.replace("|", r"\|"), parent_tags) + + convert_th = convert_td + + def convert_table(self, el, text, parent_tags): + # Markdown tables cannot represent row spans or nested tables. + if el.select_one("[rowspan], table"): + return f"\n\n{el}\n\n" + return super().convert_table(el, text, parent_tags) + + +def prepare_article(soup: BeautifulSoup, canonical: str) -> Tag: + article = soup.select_one("article.docs-content") + if article is None: + raise ExtensionError(f"AI export: missing documentation article in {canonical}") + + for panel in article.select('[role="tabpanel"]'): + tab = article.find(id=panel.get("aria-labelledby", "")) + if tab: + label = soup.new_tag("p") + label.append(soup.new_tag("strong")) + label.strong.string = tab.get_text(" ", strip=True) + panel.insert(0, label) + + for node in article.select( + "script, style, .headerlink, .viewcode-link, .linenos, .lineno, " + '.copybtn, [role="tablist"]' + ): + node.decompose() + for table in article.select("table.highlighttable"): + code = table.select_one(".highlight") + if code: + table.replace_with(code.extract()) + + # Language menus contain real API links but their trigger is only a button. + for menu in article.select(".dropdown-menu"): + menu.name = "span" + menu.insert(0, " (") + for link in menu.select("a")[:-1]: + link.insert_after("; ") + menu.append(")") + for trigger in article.select('a[data-toggle="dropdown"]'): + trigger.unwrap() + for dropdown in article.select(".dropdown"): + dropdown.name = "span" + + for node in article.select("[href], [src]"): + for attr in ("href", "src"): + if node.get(attr): + node[attr] = urljoin(canonical, node[attr]) + return article + + +def split_chunks( + markdown: str, headings: dict[str, dict], document: dict +) -> list[dict]: + chunks = [] + current = { + "heading": document["title"], + "headingLevel": 0, + "url": document["canonical"], + } + path: list[tuple[int, str]] = [] + lines: list[str] = [] + fence = "" + + def flush(): + body = "\n".join(lines).strip() + if not body: + return + fragment = urldefrag(current["url"])[1] + key = f"fragment:{fragment}" if fragment else "document-root" + chunks.append( + { + **document, + **current, + "chunkID": digest(f"{document['documentID']}:{key}"), + "headingPath": [title for _, title in path], + "markdown": body, + "content": plain_text(body), + "contentHash": digest(body), + } + ) + + for line in markdown.splitlines(): + marker = re.match(r"^(`{3,}|~{3,})", line) + if marker: + run = marker[1] + if not fence: + fence = run + elif ( + run[0] == fence[0] + and len(run) >= len(fence) + and not line[len(run) :].strip() + ): + fence = "" + if not fence and line in headings: + flush() + lines = [] + current = headings[line] + while path and path[-1][0] >= current["headingLevel"]: + path.pop() + path.append((current["headingLevel"], current["heading"])) + lines.append(line) + flush() + for position, chunk in enumerate(chunks): + chunk.update( + position=position, + documentChunkCount=len(chunks), + previousChunkID=chunks[position - 1]["chunkID"] if position else "", + nextChunkID=chunks[position + 1]["chunkID"] + if position + 1 < len(chunks) + else "", + ) + return chunks + + +def markdown_document(document: dict, body: str) -> str: + metadata = "\n".join( + f"{key}: {serialize(value)}" for key, value in document.items() + ) + return f"---\n{metadata}\n---\n\n{body}\n" + + +def validate_code_blocks(article: Tag, markdown: str, docname: str): + expected = Counter(pre.get_text().rstrip("\n") for pre in article.select("pre")) + actual = Counter() + for token in PLAIN_PARSER.parse(markdown): + if token.type in {"fence", "code_block"}: + actual[token.content.rstrip("\n")] += 1 + elif token.type == "html_block": + table = BeautifulSoup(token.content, "lxml") + actual.update(pre.get_text().rstrip("\n") for pre in table.select("pre")) + if expected - actual: + raise ExtensionError(f"AI export: code blocks lost or changed in {docname}") + + +def llms_index(documents: list[dict], base_url: str, version: str, channel: str) -> str: + lines = [ + "# LIEF documentation", + "", + "> LIEF parses, inspects, modifies, and writes executable formats in C++, Python, and Rust.", + "", + f"Documentation version: {version}. Channel: {channel}. Canonical documentation: {base_url}", + "", + ( + "Match these references to the installed LIEF version. The latest channel follows development; " + "the stable channel documents the latest release. Check the installation and feature guides " + "for platform, architecture, and build requirements." + ), + "", + ( + "LIEF Extended adds debug information, Objective-C metadata, dyld shared cache, assembly, " + "and disassembly features. Basic runtime support is an independent build option; runtime " + "memory-layout enumeration, assembly, and disassembly require Extended." + ), + "", + ( + "Each page has a resolved Markdown copy with absolute citation links, expanded code includes, " + "all language tabs, and API signatures. The indexes cover this Sphinx documentation; separate " + "Rustdoc and Doxygen sites are linked from the API guides. Use individual pages or chunks " + "for targeted retrieval; llms-full.txt bundles every page and can be large." + ), + "", + "## Machine-readable resources", + "", + ] + for path, title, description in ( + ( + "index.json", + "Document index", + "Titles, descriptions, versions, Markdown URLs, and full text.", + ), + ( + "index.chunks.json", + "Retrieval chunks", + "Heading and API symbol chunks with citation URLs, stable IDs, hashes, and neighbours.", + ), + ( + "llms-full.txt", + "Complete Markdown corpus", + "Every exported document, including API references.", + ), + ("sitemap.xml", "Sitemap", "Canonical HTML pages in this documentation build."), + ( + "objects.inv", + "Sphinx symbol inventory", + "Resolved cross-reference targets for documented APIs.", + ), + ): + lines.append(f"- [{title}]({urljoin(base_url, path)}): {description}") + + groups: dict[str, list[dict]] = { + name: [] + for name in ( + "Start here", + "LIEF Extended", + "Runtime", + "Formats and API references", + "Tutorials", + "Plugins and tools", + "Optional", + ) + } + for document in documents: + name = document["docname"] + if name in {"index", "intro", "installation", "compilation", "ai"}: + group = "Start here" + elif name.startswith("extended/"): + group = "LIEF Extended" + elif name.startswith("runtime/"): + group = "Runtime" + elif name.startswith(("formats/", "api/")): + group = "Formats and API references" + elif name.startswith("tutorials/"): + group = "Tutorials" + elif name.startswith(("plugins/", "tools/")): + group = "Plugins and tools" + else: + group = "Optional" + groups[group].append(document) + for name, pages in groups.items(): + if pages: + lines.extend(["", f"## {name}", ""]) + if name == "Start here": + order = ["index", "intro", "installation", "compilation", "ai"] + pages.sort(key=lambda page: order.index(page["docname"])) + else: + pages.sort( + key=lambda page: ( + 0 if page["docname"].endswith("/intro") else 1, + str(Path(page["docname"]).parent), + 0 if page["docname"].endswith("/index") else 1, + page["docname"], + ) + ) + for page in pages: + title = page["title"].replace("[", r"\[").replace("]", r"\]") + lines.append( + f"- [{title}]({page['markdownURL']}): {page['description']}" + ) + return "\n".join(lines) + "\n" + + +def add_discovery_links(app: Sphinx, pagename, templatename, context, doctree): + if app.builder.name != "html" or pagename not in app.env.found_docs: + return + metadata = BeautifulSoup(context["metatags"], "lxml") + if "noindex" in app.env.metadata.get(pagename, {}) or any( + "noindex" in tag.get("content", "").lower() + for tag in metadata.select('meta[name="robots"]') + ): + return + canonical = context.get("canonical_url") + if not canonical: + raise ExtensionError(f"AI export: missing canonical URL for {pagename}") + markdown_url = canonical.removesuffix(".html") + ".md" + base_url = app.config.html_theme_options["base_url"] + context["metatags"] += ( + f'\n' + f'\n' + ) + + +def remove_purged_markdown(app: Sphinx, env, docname: str): + if app.builder.name == "html": + Path(app.builder.get_outfilename(docname)).with_suffix(".md").unlink( + missing_ok=True + ) + + +def export_documentation(app: Sphinx, exception: Exception | None): + if exception is not None or app.builder.name != "html": + return + output = Path(app.outdir) + base_url = app.config.html_theme_options["base_url"] + version = app.config.release + channel = app.config.lief_doc_endpoint + documents, chunks, full = [], [], [] + for docname in sorted(app.env.found_docs): + html_path = Path(app.builder.get_outfilename(docname)) + soup = BeautifulSoup(html_path.read_text(encoding="utf-8"), "lxml") + if any( + "noindex" in tag.get("content", "").lower() + for tag in soup.select('meta[name="robots"]') + ): + html_path.with_suffix(".md").unlink(missing_ok=True) + continue + canonical = soup.select_one('link[rel="canonical"]')["href"] + markdown_url = canonical.removesuffix(".html") + ".md" + for relation, media_type, url in ( + ("alternate", "text/markdown", markdown_url), + ("describedby", "text/plain", urljoin(base_url, "llms.txt")), + ): + links = soup.find_all("link", rel=relation, type=media_type) + if len(links) != 1 or links[0].get("href") != url: + raise ExtensionError(f"AI export: invalid {relation} link in {docname}") + document = { + "documentID": digest(canonical), + "docname": docname, + "title": soup.title.get_text(), + "description": soup.select_one('meta[name="description"]')["content"], + "canonical": canonical, + "markdownURL": markdown_url, + "documentationVersion": version, + "documentationChannel": channel, + "language": app.config.language or "en", + } + converter = DocumentationMarkdown(canonical) + article = prepare_article(soup, canonical) + body = converter.convert_soup(article).strip() + if not body: + raise ExtensionError(f"AI export: empty Markdown for {docname}") + validate_code_blocks(article, body, docname) + document["contentHash"] = digest(body) + markdown = markdown_document(document, body) + html_path.with_suffix(".md").write_text(markdown, encoding="utf-8") + page_chunks = split_chunks(body, converter.headings, document) + chunks.extend(page_chunks) + documents.append( + {**document, "content": " ".join(chunk["content"] for chunk in page_chunks)} + ) + full.append(markdown) + + for filename, records, key in ( + ("index.json", documents, "documents"), + ("index.chunks.json", chunks, "chunks"), + ): + payload = { + "schemaVersion": "1.0", + "canonicalSite": base_url, + "documentationVersion": version, + "documentationChannel": channel, + "documentCount": len(documents), + "corpusHash": digest(serialize(records)), + key: records, + } + if key == "chunks": + payload.update( + chunkCount=len(chunks), + chunking={ + "strategy": "html-heading-and-api-symbol", + "ordering": "docname ascending, then source order", + "identity": "documentID = SHA-256(canonical); chunkID = SHA-256(documentID + ':fragment:' + anchor), or ':document-root' without an anchor", + "contentHash": "SHA-256 of the UTF-8 Markdown body", + "corpusHash": "SHA-256 of the JSON records, including metadata, using Python json.dumps with ensure_ascii=False and sort_keys=True", + "navigation": "position is zero-based within a document; neighbour IDs are empty at document boundaries", + }, + ) + (output / filename).write_text(serialize(payload) + "\n", encoding="utf-8") + (output / "llms-full.txt").write_text("\n\n".join(full), encoding="utf-8") + (output / "llms.txt").write_text( + llms_index(documents, base_url, version, channel), encoding="utf-8" + ) + if len({chunk["chunkID"] for chunk in chunks}) != len(chunks): + raise ExtensionError("AI export: duplicate chunk IDs") + logger.info( + "Exported %d Markdown documents and %d retrieval chunks", + len(documents), + len(chunks), + ) + + +def setup(app: Sphinx): + app.connect("html-page-context", add_discovery_links, priority=650) + app.connect("env-purge-doc", remove_purged_markdown) + app.connect("build-finished", export_documentation, priority=950) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/config/__init__.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/__init__.py new file mode 100644 index 0000000..1acd247 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/__init__.py @@ -0,0 +1,16 @@ +import lief +import sphinx_lief + +from sphinx.application import Sphinx +from sphinx_lief_doc.config.breathe_config import setup as setup_breathe +from sphinx_lief_doc.config.lief_config import setup as setup_lief +from sphinx_lief_doc.config.html_config import setup as setup_html +from sphinx_lief_doc.config.link_check import setup as setup_link_check + +def init_config(app: Sphinx): + app.config.pygments_style = "xcode" + + setup_lief(app) + setup_html(app) + setup_breathe(app) + setup_link_check(app) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/config/breathe_config.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/breathe_config.py new file mode 100644 index 0000000..a04b333 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/breathe_config.py @@ -0,0 +1,46 @@ +import lief +import os +import sphinx_lief + +from pathlib import Path +from sphinx.application import Sphinx + +CURRENT_DIR = Path(__file__).parent +LIEF_ROOT_DIR = (CURRENT_DIR / "../../../..").resolve().absolute() + +DOXYGEN_XML_PATH = Path(os.environ['LIEF_DOXYGEN_XML']).resolve().absolute() + +assert DOXYGEN_XML_PATH.exists() + +def setup(app: Sphinx): + app.config.breathe_default_members = ('members', 'protected-members', 'undoc-members') + app.config.breathe_show_enumvalue_initializer = True + + PREDEFINED = ( + "LIEF_API=", + "LIEF_LOCAL=", + "__cplusplus", + ) + + EXPAND_AS_DEFINED = ( + "_LIEF_EI", + "_LIEF_EN", + "_LIEF_EN_2", + ) + app.config.breathe_projects = { + "lief": DOXYGEN_XML_PATH, + } + + app.config.breathe_domain_by_extension = { + "h" : "c", + "hpp" : "cpp", + } + + app.config.breathe_doxygen_config_options = { + "WARN_IF_UNDOCUMENTED": "NO", + "MACRO_EXPANSION": "YES", + 'PREDEFINED': " ".join(PREDEFINED), + 'EXPAND_AS_DEFINED': " ".join(EXPAND_AS_DEFINED) + } + + app.config.breathe_default_project = "lief" diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/config/html_config.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/html_config.py new file mode 100644 index 0000000..72e2e9e --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/html_config.py @@ -0,0 +1,90 @@ +import os + +import lief +import sphinx_lief +from sphinx.application import Sphinx + + +def minify_option() -> dict[str, bool]: + if os.getenv("LIEF_DOC_MINIFY") is not None: + return { + "html_minify": True, + "css_minify": True, + "html_prettify": False, + } + + return { + "html_minify": False, + "css_minify": False, + "html_prettify": False, + } + + +def setup(app: Sphinx): + app.config.html_theme_path = sphinx_lief.html_theme_path() + app.config.html_context = sphinx_lief.get_html_context() + app.config.html_theme = app.config.lief_html_theme + app.config.html_base_url = app.config.lief_public_website + app.config.base_url = ( + f"{app.config.html_base_url}/doc/{app.config.lief_doc_endpoint}" + ) + app.config.html_last_updated_fmt = "%d/%m/%Y, %H:%M:%S" + app.config.html_logo = "_static/logo_blue.png" + app.config.html_favicon = "_static/favicon.ico" + app.config.html_static_path = ["_static"] + app.config.htmlhelp_basename = "LIEFdoc" + app.config.html_theme_options = { + "commit": app.config.lief_commit, + "base_url": f"{app.config.base_url}/", + "sponsor_link": app.config.lief_gh_sponsor_url, + "extended_link": app.config.lief_extended_url, + "discord_invite": app.config.lief_discord, + "repo_url": app.config.lief_gh_repo_url, + "repo_name": app.config.lief_gh_repo, + "logo_icon": "logo_blue.png", + "globaltoc_depth": 2, + "color_primary": "blue", + "color_accent": "cyan", + "touch_icon": "favicon.ico", + "nav_links": [ + { + "href": app.config.html_base_url, + "internal": False, + "title": "Home", + "icon": "fa-solid fa-house", + }, + { + "href": f"{app.config.html_base_url}/blog", + "internal": False, + "title": "Blog", + "icon": "fa-solid fa-rss", + }, + { + "href": f"{app.config.html_base_url}/download", + "internal": False, + "title": "Download", + "icon": "fa-solid fa-download", + }, + { + "href": "index", + "internal": True, + "title": "Documentation", + "icon": "fa-solid fa-book", + "subnav": [ + { + "title": "Doxygen", + "href": f"{app.config.base_url}/doxygen", + }, + ], + }, + { + "href": f"{app.config.html_base_url}/about", + "internal": False, + "title": "About", + "icon": "fa-solid fa-bars-staggered", + }, + ], + "table_classes": ["plain"], + } + + app.config.html_theme_options.update(minify_option()) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/config/lief_config.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/lief_config.py new file mode 100644 index 0000000..5ff3738 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/lief_config.py @@ -0,0 +1,145 @@ +import os +from pathlib import Path +from typing import Any + +import lief +from docutils import nodes +from sphinx.application import Sphinx +from sphinx.transforms import SphinxTransform +from sphinx.util import logging + +logger = logging.getLogger(__name__) + +_LIEF_VERSION_ENV_KEY = "LIEF_VERSION" +_LIEF_RUST_DOC_ENV_KEY = "LIEF_RUST_DOC_CHECK_PATH" +_LIEF_RELEASE_ENV_KEY = "LIEF_DOC_IS_RELEASE" + + +class RegisterNestedTargets(SphinxTransform): + """Register targets parsed inside MyST ``eval-rst`` blocks.""" + + default_priority = 190 + + def apply(self, **_kwargs: Any) -> None: + for element in self.document.findall(nodes.Element): + if isinstance(element, nodes.substitution_definition): + continue + + ids = element.get("ids", ()) + names = element.get("names", ()) + if not ids and not names: + continue + + if names and not any(name in self.document.nameids for name in names): + self.document.note_explicit_target(element) + elif ids and not all(id_ in self.document.ids for id_ in ids): + self.document.set_id(element) + + +class RegisterSubstitutions(SphinxTransform): + """Register substitution definitions parsed inside MyST ``eval-rst`` blocks.""" + + default_priority = 200 + + def apply(self, **_kwargs: Any) -> None: + for definition in self.document.findall(nodes.substitution_definition): + for name in definition["names"]: + if self.document.nameids.get(name) in definition["ids"]: + self.document.nameids.pop(name) + self.document.nametypes.pop(name) + if name not in self.document.substitution_defs: + self.document.note_substitution_def(definition, name) + + +class Substitutions(SphinxTransform): + default_priority = 210 + + def apply(self, **_kwargs: Any) -> None: + for ref in self.document.findall(nodes.substitution_reference): + refname = ref["refname"] + text = None + if refname == "lief-extended-url": + text = self.config.lief_extended_url + elif refname == "lief-rust-doc-nightly": + text = self.config.lief_rust_doc_nightly + elif refname == "lief-rust-doc": + text = self.config.lief_rust_doc + elif refname == "lief-extended-email": + text = self.config.lief_extended_email + elif refname == "lief-llvm-version": + text = self.config.lief_llvm_version + elif refname == "lief-discord": + text = self.config.lief_discord + elif refname == "lief-plugin-url": + text = f"{self.config.lief_plugin_url}/index.html" + elif refname == "lief-sdk-url": + text = f"{self.config.lief_sdk_url}/index.html" + + if text is None: + continue + + if text.startswith(("http://", "https://")): + ref.replace_self(nodes.reference(text, text, refuri=text)) + else: + ref.replace_self(nodes.Text(text)) + + +def get_version() -> str: + return os.getenv(_LIEF_VERSION_ENV_KEY) or ( + lief.__tag__ if lief.__is_tagged__ else lief.__version__ + ) + + +def get_release() -> str: + return os.getenv(_LIEF_VERSION_ENV_KEY) or lief.__version__ + + +def get_rust_doc_check() -> Path | None: + value = os.getenv(_LIEF_RUST_DOC_ENV_KEY) + if value is not None: + return Path(value).resolve().absolute() + return None + + +def setup(app: Sphinx): + app.config.version = get_version() + app.config.release = get_release() + + app.config.lief_is_release = ( + os.getenv(_LIEF_RELEASE_ENV_KEY) is not None or lief.__is_tagged__ + ) + + app.config.lief_commit = os.getenv("LIEF_COMMIT") or lief.__commit__ + app.config.lief_public_website = "https://lief.re" + app.config.lief_html_theme = "sphinx_lief" + app.config.lief_doc_endpoint = "stable" if app.config.lief_is_release else "latest" + app.config.lief_gh_repo = "LIEF" + app.config.lief_gh_org = "lief-project" + app.config.lief_discord = "https://discord.gg/jGQtyAYChJ" + app.config.lief_gh_repo_url = "https://github.com/lief-project/LIEF" + app.config.lief_gh_sponsor_url = "https://github.com/sponsors/lief-project" + app.config.lief_extended_url = "https://extended.lief.re/" + app.config.lief_extended_email = "extended@lief.re" + app.config.lief_llvm_version = "22.x" + + app.config.lief_rust_doc_base_url = "https://lief.re/doc/stable/rust" + app.config.lief_rust_doc = f"{app.config.lief_rust_doc_base_url}/lief" + + app.config.lief_rust_s3_url_prefix = "https://lief-rs.s3.fr-par.scw.cloud" + app.config.lief_s3_url_prefix = "https://lief.s3.fr-par.scw.cloud" + + app.config.lief_rust_doc_nightly_base_url = ( + f"{app.config.lief_rust_s3_url_prefix}/doc/latest" + ) + app.config.lief_rust_doc_nightly = ( + f"{app.config.lief_rust_doc_nightly_base_url}/lief/index.html" + ) + + app.config.lief_rust_doc_check = get_rust_doc_check() + + app.config.lief_plugin_url = f"{app.config.lief_s3_url_prefix}/latest/plugins" + app.config.lief_sdk_url = f"{app.config.lief_s3_url_prefix}/latest/sdk" + + app.add_transform(RegisterNestedTargets) + app.add_transform(RegisterSubstitutions) + app.add_transform(Substitutions) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/config/link_check.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/link_check.py new file mode 100644 index 0000000..a306bbc --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/config/link_check.py @@ -0,0 +1,14 @@ +from sphinx.application import Sphinx + +def setup(app: Sphinx): + app.config.linkcheck_workers = 1 + app.config.linkcheck_ignore = [ + 'https://github.com', + 'http://github.com', + ] + app.config.linkcheck_request_headers = { + "*": { + "Accept": "text/html,application/atom+xml", + "User-Agent": "Mozilla/5.0 (X11; Linux x86_64; rv:83.0) Gecko/20100101 Firefox/83.0", + } + } diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/img_comparison.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/img_comparison.py new file mode 100644 index 0000000..0b0082a --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/img_comparison.py @@ -0,0 +1,108 @@ +from __future__ import annotations + + +from typing import TYPE_CHECKING +import shutil + +from hashlib import md5 + +from pathlib import Path +from sphinx.directives import SphinxDirective +from sphinx.util import logging +from sphinx.application import Sphinx + +from sphinx.writers.html import HTML5Translator + +from docutils import nodes +from docutils.nodes import Element, Node + +if TYPE_CHECKING: + from typing import ClassVar + + from sphinx.application import Sphinx + from sphinx.util.typing import OptionSpec + +logger = logging.getLogger(__name__) + +def get_name(file: Path) -> str: + return md5(bytes(file.absolute())).hexdigest() + file.name + +class image_comparison(nodes.General, nodes.Element): + def __init__(self, left: Path, right: Path, width: str | None): + super().__init__() + self.left = left + self.right = right + self.width = width + +def visit_svg_files(self: HTML5Translator, node: Element): + left = node.left.read_text() + right = node.right.read_text() + self.body.append(f""" + +
{left}
+
{right}
+
+ """) + + raise nodes.SkipNode + +def visit_image_comparison(self: HTML5Translator, node: Element): + if node.left.name.endswith(".svg"): + assert node.right.name.endswith(".svg") + return visit_svg_files(self, node) + images_dir = Path(self.builder.outdir / '_images') + images_dir.mkdir(exist_ok=True) + + shutil.copy2(node.left, images_dir / get_name(node.left)) + shutil.copy2(node.right, images_dir / get_name(node.right)) + + inline_style = "" + if node.width is not None: + inline_style = f'style="max-width:{node.width};"' + + self.body.append(f""" + + + + + """) + + raise nodes.SkipNode + +def depart_image_comparison(_: HTML5Translator, __: Element): + pass + +class ImageComparison(SphinxDirective): + has_content = True + required_arguments = 0 + optional_arguments = 2 + final_argument_whitespace = False + + option_spec: ClassVar[OptionSpec] = { + 'left': str, + 'right': str, + 'width': str, + } + + def run(self) -> list[Node]: + left_img = Path(self.options['left']) + right_img = Path(self.options['right']) + + + current_file, _ = self.get_source_info() + current_file_dir = Path(current_file).parent + + assert (current_file_dir / left_img).is_file() + assert (current_file_dir / right_img).is_file() + + node = image_comparison( + current_file_dir / left_img, + current_file_dir / right_img, + self.options.get('width', None) + ) + node.document = self.state.document + return [node] + +def setup(app: Sphinx): + app.add_directive("img-comparison", ImageComparison) + app.add_node(image_comparison, html=(visit_image_comparison, depart_image_comparison)) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/inheritance_diagram.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/inheritance_diagram.py new file mode 100644 index 0000000..931c623 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/inheritance_diagram.py @@ -0,0 +1,35 @@ +import inspect +import lief +from sphinx.ext.inheritance_diagram import InheritanceDiagram +from sphinx.util.typing import OptionSpec +from docutils.nodes import Node + +class LIEFInheritanceDiagram(InheritanceDiagram): + option_spec: OptionSpec = { + **InheritanceDiagram.option_spec, + 'depth': int + } + def _check_module(self, module, obj, depth: int): + if not module.__name__.startswith("lief"): + return [] + + classes = [] + for name, member in inspect.getmembers(module): + if inspect.isclass(member) and issubclass(member, obj): + mro = inspect.getmro(member) + if (0 < depth and mro.index(obj) <= depth) or depth == 0: + classes.append(f"{module.__name__}.{name}") + if inspect.ismodule(member) and member != module: + classes.extend(self._check_module(member, obj, depth)) + return list(set(classes)) + + def run(self) -> list[Node]: + cls = None + depth = self.options.get('depth', 0) + if self.arguments[0].startswith("lief._lief"): + elements = self.arguments[0].split(".")[2:] + cls = lief._lief + for element in elements: + cls = getattr(cls, element) + self.arguments[0] = " ".join(self._check_module(lief, cls, depth)) + return super().run() diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/lief_api.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/lief_api.py new file mode 100644 index 0000000..b969817 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/lief_api.py @@ -0,0 +1,167 @@ +import re + +from docutils import nodes +from docutils.nodes import Element, Node +from sphinx.application import Sphinx +from sphinx.directives import SphinxDirective +from sphinx.util import logging +from sphinx.writers.html import HTML5Translator + +logger = logging.getLogger(__name__) + + +def _slugify(name: str) -> str: + return re.sub(r"[^a-z0-9_-]+", "-", name.casefold()).strip("-") + + +class liefapi_name(nodes.TextElement, nodes.Inline): + pass + + +def visit_liefapi_name_node(self: HTML5Translator, node: Element): + base_id = node["lief-api-id"] + counts = getattr(self, "_lief_api_id_counts", {}) + count = counts.get(base_id, 0) + 1 + counts[base_id] = count + self._lief_api_id_counts = counts + + string_id = base_id if count == 1 else f"{base_id}-{count}" + for sibling in node.parent.children: + sibling["lief-api-rendered-id"] = string_id + + self.body.append( + f""" + ") + + +def depart_liefapi_name_node(self, node: Element): + pass + + +class liefapi_elements(nodes.General, nodes.Element, nodes.Inline): + pass + + +def visit_custom_literal(self: HTML5Translator, node: nodes.literal): + text = self.encode(node.children[0].astext()) + icon = "" + if "rust" in node["classes"]: + icon = ' ' + elif "py" in node["classes"]: + icon = ' ' + elif "cpp" in node["classes"]: + icon = ' ' + + self.body.append( + """ + {icon}{text} + """.format(classes=" ".join(node["classes"]), text=text, icon=icon) + ) + + +def visit_liefapi_elements_node(self: HTML5Translator, node: Element): + self.body.append( + '") + + +def depart_liefapi_elements_node(self, node: Element): + pass + + +class liefapi(nodes.General, nodes.Element, nodes.Inline): + pass + + +def visit_liefapi_node(self: HTML5Translator, node: Element): + self.body.append( + self.starttag(node, "div", classes=["dropdown"], style="display:inline;") + ) + for element in node.children: + if isinstance(element, liefapi_name): + visit_liefapi_name_node(self, element) + + if isinstance(element, liefapi_elements): + visit_liefapi_elements_node(self, element) + + self.body.append("") + raise nodes.SkipNode + + +def depart_liefapi_node(self: HTML5Translator, node: Element): + pass + + +class LIEFApi(SphinxDirective): + has_content = True + required_arguments = 1 + optional_arguments = 0 + final_argument_whitespace = False + + def run(self) -> list[Node]: + if len(self.arguments) != 1: + raise RuntimeError("Missing argument for lief-api") + + node = liefapi() + node.document = self.state.document + + name = self.arguments[0] + identifier = f"lief-api-{_slugify(name)}-{self.env.new_serialno('lief-api')}" + name_node = liefapi_name(text=name) + name_node["lief-api-id"] = identifier + node += name_node + + elements = liefapi_elements() + elements.document = self.state.document + elements["lief-api-id"] = identifier + self.state.nested_parse(self.content, self.content_offset, elements) + + node += elements + return [node] + + +def setup(app: Sphinx): + app.add_directive("lief-api", LIEFApi) + app.add_node(liefapi, html=(visit_liefapi_node, depart_liefapi_node)) + + app.add_node(liefapi_name, html=(visit_liefapi_name_node, depart_liefapi_name_node)) + + app.add_node( + liefapi_elements, + html=(visit_liefapi_elements_node, depart_liefapi_elements_node), + ) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/literalinclude.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/literalinclude.py new file mode 100644 index 0000000..6d8fcc6 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/literalinclude.py @@ -0,0 +1,114 @@ +from __future__ import annotations + +import json +from pathlib import PurePosixPath +from typing import Any + +from sphinx.directives.code import LiteralInclude as SphinxLiteralInclude + +_LANGUAGES = { + ".c": "c", + ".cc": "cpp", + ".cpp": "cpp", + ".cxx": "cpp", + ".h": "cpp", + ".hh": "cpp", + ".hpp": "cpp", + ".hxx": "cpp", + ".py": "python", + ".pyi": "python", + ".rs": "rust", +} + + +class LiteralInclude: + """Build a Sphinx ``literalinclude`` directive from a MyST substitution. + + The optional ``marker`` argument follows the convention used by LIEF's + examples: ``lief-doc: -start`` and ``lief-doc: -end``. + It also enables automatic dedenting and infers the lexer from the source + file's extension. + """ + + def __repr__(self) -> str: + return "LiteralInclude()" + + def __eq__(self, other: object) -> bool: + return type(self) is type(other) + + def __call__( + self, + filename: str, + marker: str | None = None, + /, + **options: Any, + ) -> str: + filename = _single_line("filename", filename) + normalized = {name.replace("_", "-"): value for name, value in options.items()} + + unknown = normalized.keys() - SphinxLiteralInclude.option_spec.keys() + if unknown: + names = ", ".join(sorted(unknown)) + raise ValueError(f"unsupported literalinclude option(s): {names}") + + if marker is not None: + marker = _single_line("marker", marker) + conflicts = normalized.keys() & { + "start-after", + "start-at", + "end-before", + "end-at", + } + if conflicts: + names = ", ".join(sorted(conflicts)) + raise ValueError( + f"marker cannot be combined with literalinclude option(s): {names}" + ) + + language = _infer_language(filename) + if language is None and "language" not in normalized: + raise ValueError( + f"cannot infer the language for {filename!r}; pass language=..." + ) + + defaults: dict[str, Any] = {} + if language is not None: + defaults["language"] = language + defaults.update( + { + "start-after": f"lief-doc: {marker}-start", + "end-before": f"lief-doc: {marker}-end", + "dedent": True, + } + ) + defaults.update(normalized) + normalized = defaults + + lines = [f"```{{literalinclude}} {filename}"] + for name, value in normalized.items(): + if value is False: + continue + if value is True or value is None: + lines.append(f":{name}:") + continue + + value = _single_line(name, str(value)) + lines.append(f":{name}: {json.dumps(value)}") + lines.append("```") + return "\n".join(lines) + + +def _single_line(name: str, value: str) -> str: + value = value.strip() + if not value: + raise ValueError(f"{name} cannot be empty") + if "\n" in value or "\r" in value: + raise ValueError(f"{name} must fit on one line") + return value + + +def _infer_language(filename: str) -> str | None: + path = PurePosixPath(filename) + if path.name == "CMakeLists.txt": + return "cmake" + return _LANGUAGES.get(path.suffix.lower()) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/plugin_package.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/plugin_package.py new file mode 100644 index 0000000..99a3ba2 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/plugin_package.py @@ -0,0 +1,84 @@ +from __future__ import annotations + +import requests + +from typing import TYPE_CHECKING + +from sphinx.directives import SphinxDirective +from sphinx.util import logging +from sphinx.application import Sphinx + +from sphinx.writers.html import HTML5Translator + +from docutils import nodes +from docutils.nodes import Element, Node + +if TYPE_CHECKING: + from typing import ClassVar + + from sphinx.application import Sphinx + from sphinx.util.typing import OptionSpec + +logger = logging.getLogger(__name__) + +class lief_package(nodes.General, nodes.Element): + def __init__(self, s3_prefix: str, kind: str, files: list[dict]): + super().__init__() + self.s3_prefix = s3_prefix + self.kind = kind + self.files = files + +def visit_lief_package(self: HTML5Translator, node: Element): + html_files = "" + for file in node.files: + html_files += f""" +
  • + +  {file['name']} +
  • + """ + + self.body.append(f""" +
    +

    + +  Downloads + +

    +
      + {html_files} +
    +
    + """) + + raise nodes.SkipNode + +def depart_lief_package(_: HTML5Translator, __: Element): + pass + +class PluginPackage(SphinxDirective): + has_content = True + required_arguments = 1 + optional_arguments = 0 + final_argument_whitespace = False + + option_spec: ClassVar[OptionSpec] = { + 'file': str, + } + + def run(self) -> list[Node]: + config = self.env.config + + name = self.arguments[0] + + index_file = f"{config.lief_s3_url_prefix}/{self.options['file']}" + logger.info("Indexing %s based on %s", name, index_file) + content = requests.get(index_file, timeout=5).json() + + node = lief_package(config.lief_s3_url_prefix, name, content[name]) + node.document = self.state.document + return [node] + +def setup(app: Sphinx): + app.add_directive("plugin-package", PluginPackage) + app.add_node(lief_package, html=(visit_lief_package, depart_lief_package)) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/python_typing.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/python_typing.py new file mode 100644 index 0000000..965a8e3 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/python_typing.py @@ -0,0 +1,168 @@ +import inspect +import re +from typing import Any + +from sphinx.application import Sphinx +from sphinx.util import logging +from sphinx.util.inspect import getdoc, signature_from_str + +RE_INST = re.compile(r"\s=\s<.*\sobject\sat[^>]*>") + +logger = logging.getLogger("lief-python-typing") + + +def clean_nanobind_typehint(typehint: str) -> str: + typehint = RE_INST.sub("", typehint) + typehint = typehint.replace("_lief.", "") + return typehint + + +def process_function_signature(signature: inspect.Signature, has_overload: bool): + args = "(*args)" + if not has_overload: + args_str = [] + for name, hint in signature.parameters.items(): + if hint.annotation == inspect.Parameter.empty: + args_str.append(name) + else: + args_str.append(f"{name}: {hint.annotation}") + + args = "(" + ",".join(args_str) + ")" + + if signature.return_annotation == inspect.Parameter.empty: + return args, None + + return args, signature.return_annotation + + +def process_property( + name: str, obj: Any, _options: Any, signature: str, return_annotation: str +) -> tuple[str | None, str | None] | None: + """ + Get the nanobind typehint for a property + """ + if not hasattr(obj, "fget"): + return signature, return_annotation + + fget = getattr(obj, "fget") + typestr = getdoc(fget) + if typestr is None: + return signature, return_annotation + + lines = typestr.splitlines() + + if len(lines) == 0: + return signature, return_annotation + try: + hint = clean_nanobind_typehint(lines[0]) + sig = signature_from_str(hint) + + return_annotation = sig.return_annotation + if return_annotation == inspect.Parameter.empty: + logger.warning("Can't generate annotation for '%s'", name) + return_annotation = "" + + return "()", return_annotation + except Exception as e: + logger.warning("Error: %s", name) + + return "()", return_annotation + + +def process_function(name: str, obj, options, signature: str, return_annotation: str): + """ + Get the nanobind typehint for a function + """ + typestr = getdoc(obj) + if typestr is None: + return signature, return_annotation + + lines = typestr.splitlines() + + if len(lines) == 0: + return signature, return_annotation + + empty_idx = 0 + try: + empty_idx = lines.index("") + except ValueError: + pass + + is_overloaded = empty_idx > 1 + + rettypes = set() + arg = None + for idx, line in enumerate(lines): + if len(line) == 0: + break + try: + hint = clean_nanobind_typehint(line) + signature = signature_from_str(hint) + arg, ret = process_function_signature(signature, is_overloaded) + rettypes.add(str(ret)) + except Exception as e: + logger.warning(f"Error with {name}: {line} ({e})") + + if len(rettypes) == 0 or arg is None: + return signature, return_annotation + + if len(rettypes) == 1: + return arg, rettypes.pop() + + return arg, " | ".join(rettypes) + + +def on_process_signature( + app: Sphinx, + what: str, + name: str, + obj: Any, + options: Any, + args: str, + retann: str, +) -> tuple[str | None, str | None] | None: + + # autodoc is great for auto generating documentation of regular packages + # but it has some limitation (like the properties) for native Python + # bindings. + # + # This event listener generate the type hint for our nanobind-based bindings + match what: + case "property": + return process_property(name, obj, options, args, retann) + + case "function": + return process_function(name, obj, options, args, retann) + + case "attribute": + if hasattr(obj, "__call__"): + return process_function(name, obj, options, args, retann) + + return args, retann + + +def autodoc_process_docstring(app, what, name, obj, options, lines: list[str]): + if len(lines) > 2 or len(lines) == 0: + return + line = lines[0] + + if line.startswith("(self)"): + lines[:] = [] + return + + +def autodoc_skip_member(app, what, name: str, obj: Any, skip: bool, options): + if ( + not skip + and isinstance(obj, type) + and name.startswith("it_") + and hasattr(obj, "__next__") + ): + return True + return None + + +def setup(app: Sphinx): + app.connect("autodoc-process-signature", on_process_signature) + app.connect("autodoc-process-docstring", autodoc_process_docstring) + app.connect("autodoc-skip-member", autodoc_skip_member) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/roles.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/roles.py new file mode 100644 index 0000000..3fcacf9 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/roles.py @@ -0,0 +1,73 @@ +from docutils import nodes +from docutils.nodes import raw + +from collections.abc import Sequence # NoQA: TCH003 + +from docutils.parsers.rst.states import Inliner # NoQA: TCH002 + +from sphinx.environment import BuildEnvironment +from sphinx.config import Config +from sphinx.application import Sphinx + +def _get_env(inliner: Inliner) -> BuildEnvironment: + return inliner.document.settings.env + +def _get_config(inliner) -> Config: + return _get_env(inliner).config + +def _github_prefix(config: Config): + return f"https://github.com/{config.lief_gh_org}/{config.lief_gh_repo}" + +def issue_role(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = None, content: Sequence[str] = ()): + + config = _get_config(inliner) + return [ + nodes.reference("", '#' + text, + refuri=f"{_github_prefix(config)}/issues/{text}", + **options or {}) + ], [] + +def commit_role(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = None, content: Sequence[str] = ()): + config = _get_config(inliner) + return [ + nodes.reference("", text[:7], + refuri=f"{_github_prefix(config)}/commit/{text}", + **options or {}) + ], [] + +def pr_role(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = None, content: Sequence[str] = ()): + config = _get_config(inliner) + return [ + nodes.reference("", '#' + text, + refuri=f"{_github_prefix(config)}/pull/{text}") + ], [] + +def github_user(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = None, content: Sequence[str] = ()): + return [ + nodes.reference("", text, refuri=f"https://github.com/{text}", + **options or {}) + ], [] + +def xmark(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = {}, content: Sequence[str] = ()): + options["format"] = "html" + node = raw(text='', **options) + return [node], [] + +def fa_check(name: str, rawtext: str, text: str, lineno: int, + inliner: Inliner, options: dict | None = {}, content: Sequence[str] = ()): + options["format"] = "html" + node = raw(text='', **options) + return [node], [] + +def setup(app: Sphinx): + app.add_role('commit', commit_role) + app.add_role('pr', pr_role) + app.add_role('issue', issue_role) + app.add_role('github_user', github_user) + app.add_role('xmark', xmark) + app.add_role('fa-check', fa_check) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/__init__.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/__init__.py new file mode 100644 index 0000000..cb43ed3 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/__init__.py @@ -0,0 +1 @@ +from .rustdomain import RustDomain diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/rustdomain.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/rustdomain.py new file mode 100644 index 0000000..64beb62 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/rust_domain/rustdomain.py @@ -0,0 +1,235 @@ +from __future__ import annotations + +from bs4 import BeautifulSoup +import re +from pathlib import Path +from copy import copy +from typing import TYPE_CHECKING, Any, Callable, Final, cast + +from docutils import nodes +from docutils.nodes import Element, Node, system_message, reference +from docutils.parsers.rst import Directive +from docutils.statemachine import StringList + +from sphinx import addnodes +from sphinx.addnodes import desc_signature, pending_xref +from sphinx.directives import ObjectDescription +from sphinx.domains import Domain, ObjType +from sphinx.locale import _, __ +from sphinx.roles import EmphasizedLiteral, XRefRole +from sphinx.util import docname_join, logging, ws_re +from sphinx.util.docutils import SphinxDirective +from sphinx.util.nodes import clean_astext, make_id, make_refnode + +if TYPE_CHECKING: + from collections.abc import Iterable, Iterator + + from sphinx.application import Sphinx + from sphinx.builders import Builder + from sphinx.environment import BuildEnvironment + from sphinx.util.typing import OptionSpec, RoleFunction + +logger = logging.getLogger(__name__) + +class RustXRef(XRefRole): + def process_link(self, env, refnode, has_explicit_title, title, target): + return title, target + +class RustDomain(Domain): + name = 'rust' + label = "Rust" + + object_types: dict[str, ObjType] = { + # ObjType( + # lname: localized name of the type + # roles: all the roles that can refer to an object of this type + # attrs: object attributes + 'struct': ObjType(_('struct'), 'struct'), + 'trait': ObjType(_('trait'), 'trait'), + 'method': ObjType(_('method'), 'method'), + 'module': ObjType(_('module'), 'module'), + 'member': ObjType(_('member'), 'member'), + 'enum': ObjType(_('enum'), 'enum'), + 'function': ObjType(_('function'), 'func'), + } + + directives: dict[str, Any] = { + } + + roles = { + 'struct': RustXRef(), + 'trait': RustXRef(), + 'method': RustXRef(), + 'module': RustXRef(), + 'member': RustXRef(), + 'enum': RustXRef(), + 'func': RustXRef(), + } + + initial_data: dict[str, dict[str, tuple[Any]]] = { + 'objects': {}, # fullname -> docname, objtype + } + + def clear_doc(self, docname: str) -> None: + return + + def process_doc(self, env: BuildEnvironment, docname: str, + document: nodes.document) -> None: + return + + def process_field_xref(self, pnode: pending_xref) -> None: + return + + def merge_domaindata(self, docnames: list[str], otherdata: dict[str, Any]) -> None: + return + + def gen_url(self, env: BuildEnvironment, target: str, url: str) -> str | None: + config = env.config + if config.lief_rust_doc_check is not None: + path: Path = config.lief_rust_doc_check / url + target_name = path.name + + if '#' in target_name: + filename, anchor = target_name.split('#') + normalized = path.parent / filename + if not normalized.exists(): + logger.warning("Path %s for %s does not exist", url, target) + return None + html = normalized.read_text() + soup = BeautifulSoup(html, 'html.parser') + if soup.find(id=anchor) is None: + logger.warning("Missing reference: %s in %s for %s", anchor, normalized, target) + return None + + elif not path.exists(): + logger.warning("Path %s for %s does not exist", url, target) + return None + + url_domain = config.lief_rust_doc_base_url if config.lief_is_release else \ + config.lief_rust_doc_nightly_base_url + + return f"{url_domain}/{url}" + + def _find_struct(self, env: BuildEnvironment, target: str) -> str | None: + parts = target.split('::') + prefix = "/".join(parts[:-1]) + suffix = f"struct.{parts[-1]}.html" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_module(self, env: BuildEnvironment, target: str) -> str | None: + parts = target.split('::') + prefix = "/".join(parts) + suffix = "index.html" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_trait(self, env: BuildEnvironment, target: str) -> str | None: + """ + e.g. :rust:trait:`lief::generic::Symbol` + """ + parts = target.split('::') + prefix = "/".join(parts[:-1]) + suffix = f"trait.{parts[-1]}.html" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_method(self, env: BuildEnvironment, target: str) -> str | None: + """ + e.g. :rust:method:`lief::Relocation::address [trait]` + """ + ref, spec = target.split(' ') + spec = spec.replace("[", "").replace("]", "") + + parts = ref.split('::') + prefix = "/".join(parts[:-2]) + suffix = f"{spec}.{parts[-2]}.html#method.{parts[-1]}" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_member(self, env: BuildEnvironment, target: str) -> str | None: + """ + e.g. :rust:member:`lief::Range::low [struct]` + """ + ref, spec = target.split(' ') + spec = spec.replace("[", "").replace("]", "") + + parts = ref.split('::') + prefix = "/".join(parts[:-2]) + suffix = f"{spec}.{parts[-2]}.html#structfield.{parts[-1]}" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_enum(self, env: BuildEnvironment, target: str) -> str | None: + """ + e.g. :rust:enum:`lief::elf::header::Class` + """ + parts = target.split('::') + prefix = "/".join(parts[:-1]) + suffix = f"enum.{parts[-1]}.html" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _find_func(self, env: BuildEnvironment, target: str) -> str | None: + """ + e.g. :rust:func:`lief::is_extended` + """ + parts = target.split('::') + prefix = "/".join(parts[:-1]) + suffix = f"fn.{parts[-1]}.html" + + return self.gen_url(env, target, f"{prefix}/{suffix}") + + def _resolve_xref_impl(self, env: BuildEnvironment, + typ: str, target: str) -> str | None: + if typ == "struct": + return self._find_struct(env, target) + + if typ == "module": + return self._find_module(env, target) + + if typ == "trait": + return self._find_trait(env, target) + + if typ == "method": + return self._find_method(env, target) + + if typ == "member": + return self._find_member(env, target) + + if typ == "enum": + return self._find_enum(env, target) + + if typ == "func": + return self._find_func(env, target) + + logger.warning("Can't compute xref for: %s (%s)", target, typ) + return None + + def resolve_xref(self, env: BuildEnvironment, fromdocname: str, builder: Builder, + typ: str, target: str, node: pending_xref, + contnode: Element) -> Element | None: + refuri = self._resolve_xref_impl(env, typ, target) + # strip the [] from the text + text_node: nodes.Text = contnode.children[0] + contnode.children = [ + nodes.Text(text_node.split(' ')[0]) + ] + + if refuri is None: + node = reference("", "", refuri="#") + node += contnode + return node + + node = reference("", "", refuri=refuri) + node += contnode + return node + + def resolve_any_xref(self, env: BuildEnvironment, fromdocname: str, builder: Builder, + target: str, node: pending_xref, contnode: Element, + ) -> list[tuple[str, Element]]: + return [] + + def get_objects(self) -> Iterator[tuple[str, str, str, str, str, int]]: + return + yield diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/sdk_package.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/sdk_package.py new file mode 100644 index 0000000..2c30a70 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/sdk_package.py @@ -0,0 +1,107 @@ +from __future__ import annotations + +import requests + +from typing import TYPE_CHECKING + +from sphinx.directives import SphinxDirective +from sphinx.util import logging +from sphinx.application import Sphinx + +from sphinx.writers.html import HTML5Translator + +from docutils import nodes +from docutils.nodes import Element, Node + +if TYPE_CHECKING: + from typing import ClassVar + + from sphinx.application import Sphinx + from sphinx.util.typing import OptionSpec + +logger = logging.getLogger(__name__) + +class lief_sdk_package(nodes.General, nodes.Element): + def __init__(self, title: str, s3_prefix: str, files: list[dict]): + super().__init__() + self.s3_prefix = s3_prefix + self.files = files + self.title = title + +def visit_lief_sdk_package(self: HTML5Translator, node: Element): + html_files = "" + for file in node.files: + html_files += f""" +
  • + +  {file['name']} +
  • + """ + + self.body.append(f""" +
    +

    + +  {node.title} + +

    +
      + {html_files} +
    +
    + """) + + raise nodes.SkipNode + +def depart_lief_sdk_package(_: HTML5Translator, __: Element): + pass + +def _normalize(string: str) -> str: + string = string.lower() + string = string.strip() + return string + +def list_str(argument: str) -> list[str] | None: + if argument is None: + return None + + values = argument.split(',') + return [_normalize(s) for s in values] + +class SdkPackage(SphinxDirective): + has_content = True + required_arguments = 1 + optional_arguments = 2 + final_argument_whitespace = False + + option_spec: ClassVar[OptionSpec] = { + 'file': str, + 'filter': list_str, + } + + def run(self) -> list[Node]: + config = self.env.config + + sdk_filter = self.options['filter'] + title = self.arguments[0] + + index_file = f"{config.lief_s3_url_prefix}/{self.options['file']}" + logger.info("Indexing sdk based on %s (filter: %s)", index_file, sdk_filter) + + content = requests.get(index_file, timeout=5).json() + logger.info("Filters: %s", sdk_filter) + if sdk_filter is None or len(sdk_filter) == 0: + node = lief_sdk_package(title, config.lief_s3_url_prefix, content) + else: + filtered_files = [] + for file in content: + if any(s in file['name'].lower() for s in sdk_filter): + filtered_files.append(file) + node = lief_sdk_package(title, config.lief_s3_url_prefix, filtered_files) + + node.document = self.state.document + return [node] + +def setup(app: Sphinx): + app.add_directive("sdk-package", SdkPackage) + app.add_node(lief_sdk_package, html=(visit_lief_sdk_package, depart_lief_sdk_package)) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/seo.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/seo.py new file mode 100644 index 0000000..afcbea1 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/seo.py @@ -0,0 +1,482 @@ +from __future__ import annotations + +import json +import re +from html import unescape +from pathlib import Path +from typing import Any +from urllib.parse import urljoin +from xml.etree import ElementTree + +from docutils import nodes +from sphinx.application import Sphinx +from sphinx.environment import BuildEnvironment +from sphinx.errors import ExtensionError +from sphinx_lief_doc.lief_api import liefapi_elements + +MAX_DESCRIPTION_LENGTH = 160 +MIN_DESCRIPTION_LENGTH = 50 +ROOT_DESCRIPTION = ( + "LIEF documentation for parsing, inspecting, modifying, and writing ELF, " + "PE, Mach-O, COFF, Android, and other executable formats in C++, Python, " + "and Rust." +) +ROOT_TITLE = "LIEF Documentation - ELF, PE, Mach-O and Binary Analysis" +SOCIAL_IMAGE = "_static/lief-social.webp" + +_HTML_TAG = re.compile(r"<[^>]+>") +_LANGUAGE_TITLES = {"C++", "Python", "Rust"} +_UNHELPFUL_LEADS = ( + "please check:", + "you can also find the doxygen documentation", +) + + +def _plain_text(value: object) -> str: + text = unescape(_HTML_TAG.sub(" ", str(value or ""))) + return " ".join(text.replace("¶", " ").split()) + + +def _truncate(value: str, limit: int = MAX_DESCRIPTION_LENGTH) -> str: + text = _plain_text(value) + if len(text) <= limit: + return text + shortened = text[: limit - 1].rsplit(" ", 1)[0].rstrip(" ,;:-") + return f"{shortened}…" + + +def _parent_titles(context: dict[str, Any]) -> list[str]: + titles = [] + for parent in context.get("parents", ()): + title = _plain_text(parent.get("title", "")) + if title: + titles.append(title) + return titles + + +def _paragraph_text(paragraph: nodes.paragraph) -> str: + parts = [] + + def collect(node: nodes.Node) -> None: + if isinstance(node, liefapi_elements): + return + if isinstance(node, nodes.Text): + parts.append(str(node)) + return + for child in node.children: + collect(child) + + collect(paragraph) + return _plain_text("".join(parts)) + + +def _page_subject(context: dict[str, Any]) -> str: + title = _plain_text(context.get("title", "")) + parents = _parent_titles(context) + parent = parents[-1] if parents else "" + + if title in _LANGUAGE_TITLES and parent: + return f"{parent} {title} API" + if parent in _LANGUAGE_TITLES and len(parents) > 1: + return f"{title} {parent} {parents[-2]}" + if parent and parent.casefold() not in title.casefold(): + return f"{title} in {parent}" + return title + + +def _page_title(app: Sphinx, pagename: str, context: dict[str, Any]) -> str: + if pagename == app.config.root_doc: + return ROOT_TITLE + if pagename == "genindex": + return "LIEF API Index - LIEF Documentation" + + title = _plain_text(context.get("title", pagename)) + parents = _parent_titles(context) + parent = parents[-1] if parents else "" + + if title in _LANGUAGE_TITLES and parent: + subject = f"{parent} {title} API" + elif parent in _LANGUAGE_TITLES and len(parents) > 1: + subject = f"{title} - {parent} {parents[-2]}" + elif parent and parent.casefold() not in title.casefold(): + subject = f"{title} - {parent}" + else: + subject = title + + return f"{subject} - LIEF Documentation" + + +def _lead_paragraph(app: Sphinx, pagename: str) -> str: + if pagename not in app.env.found_docs: + return "" + + doctree = app.env.get_doctree(pagename) + for paragraph in doctree.findall(nodes.paragraph): + ancestor = paragraph.parent + while ancestor is not None and isinstance( + ancestor, (nodes.document, nodes.section) + ): + ancestor = ancestor.parent + if ancestor is not None: + continue + + candidate = _paragraph_text(paragraph) + if len(candidate) < 24: + continue + if candidate.casefold().startswith(_UNHELPFUL_LEADS): + continue + return candidate + return "" + + +def _page_description(app: Sphinx, pagename: str, context: dict[str, Any]) -> str: + if context.get("seo_description_in_metatags"): + return _truncate(context.get("seo_description", "")) + authored_description = app.env.metadata.get(pagename, {}).get("description", "") + if authored_description: + return _truncate(authored_description) + if pagename == app.config.root_doc: + return ROOT_DESCRIPTION + if pagename == "genindex": + return ( + "Alphabetical index of LIEF C++, Python, and Rust APIs for parsing, " + "inspecting, modifying, and writing executable formats." + ) + + subject = _page_subject(context) + paragraph = _lead_paragraph(app, pagename) + if paragraph: + description = paragraph + if subject and subject.casefold() not in paragraph.casefold(): + description = f"{subject}. {paragraph}" + description = _truncate(description) + if len(description) >= MIN_DESCRIPTION_LENGTH: + return description + + return _truncate( + f"{subject} reference documentation for LIEF, including APIs and " + "examples for parsing, inspecting, modifying, and writing executable " + "formats." + ) + + +def _page_url(app: Sphinx, pagename: str) -> str: + base_url = app.config.html_theme_options.get("base_url", "") + if not base_url: + return "" + target = app.builder.get_target_uri(pagename).lstrip("/") + return f"{base_url.rstrip('/')}/{target}" + + +def _breadcrumb_json( + app: Sphinx, + pagename: str, + context: dict[str, Any], + canonical_url: str, +) -> str: + if pagename == app.config.root_doc or not canonical_url: + return "" + + root_url = _page_url(app, app.config.root_doc) + items = [("Docs", root_url)] + for parent in context.get("parents", ()): + name = _plain_text(parent.get("title", "")) + link = parent.get("link", "") + if name and link: + items.append((name, urljoin(canonical_url, link))) + items.append((_plain_text(context.get("title", "")), canonical_url)) + + unique_items = [] + seen_urls = set() + for name, url in items: + if not name or not url or url in seen_urls: + continue + seen_urls.add(url) + unique_items.append((name, url)) + + if len(unique_items) < 2: + return "" + + payload = { + "@context": "https://schema.org", + "@type": "BreadcrumbList", + "itemListElement": [ + { + "@type": "ListItem", + "position": position, + "name": name, + "item": url, + } + for position, (name, url) in enumerate(unique_items, start=1) + ], + } + return json.dumps(payload, ensure_ascii=False, separators=(",", ":")).replace( + "<", "\\u003c" + ) + + +def add_seo_context( + app: Sphinx, + pagename: str, + templatename: str, + context: dict[str, Any], + doctree: nodes.document | None, +) -> None: + del templatename, doctree + + context["seo_title"] = _page_title(app, pagename, context) + context["seo_description"] = _page_description(app, pagename, context) + + if pagename == "genindex": + context["seo_noindex"] = True + + if pagename in {"genindex", "search"}: + return + + canonical_url = context.get("canonical_url") or context.get("pageurl") + if not canonical_url: + canonical_url = _page_url(app, pagename) + context["canonical_url"] = canonical_url + + base_url = app.config.html_theme_options.get("base_url", "") + context["seo_image_url"] = f"{base_url.rstrip('/')}/{SOCIAL_IMAGE}" + context["seo_breadcrumb_json"] = _breadcrumb_json( + app, pagename, context, canonical_url + ) + + +def remove_stale_helpers(app: Sphinx) -> None: + if app.builder.name == "html": + (Path(app.outdir) / "_cross_api.html").unlink(missing_ok=True) + + +def remove_purged_page(app: Sphinx, env: BuildEnvironment, docname: str) -> None: + """Keep incremental output free of HTML for removed or renamed sources.""" + del env + if app.builder.name != "html": + return + + output = Path(app.outdir).resolve() + page = Path(app.builder.get_outfilename(docname)).resolve() + if page.suffix == ".html" and page.is_relative_to(output): + page.unlink(missing_ok=True) + + +class _MetadataParser: + def __init__(self, path: Path) -> None: + from bs4 import BeautifulSoup + + self.soup = BeautifulSoup(path.read_text(encoding="utf-8"), "html.parser") + + def title(self) -> str: + return _plain_text(self.soup.title.string if self.soup.title else "") + + def meta(self, *, name: str = "", prop: str = "") -> list[str]: + attrs = {"name": name} if name else {"property": prop} + return [ + tag.get("content", "").strip() for tag in self.soup.find_all("meta", attrs) + ] + + def links(self, relation: str) -> list[str]: + return [ + tag.get("href", "").strip() + for tag in self.soup.find_all("link", rel=relation) + ] + + def json_ld(self) -> list[dict[str, Any]]: + payloads = [] + for script in self.soup.find_all("script", type="application/ld+json"): + payloads.append(json.loads(script.string or "{}")) + return payloads + + +def validate_seo(app: Sphinx, exception: Exception | None) -> None: + if exception is not None or app.builder.name != "html": + return + + output = Path(app.outdir) + errors = [] + seen_titles: dict[str, str] = {} + seen_descriptions: dict[str, str] = {} + seen_canonicals: dict[str, str] = {} + + if (output / "_cross_api.html").exists(): + errors.append("internal helper _cross_api.html must not be generated") + + for path in sorted(output.rglob("*.html")): + if ".doctrees" in path.parts: + continue + relative = path.relative_to(output).as_posix() + metadata = _MetadataParser(path) + title = metadata.title() + descriptions = metadata.meta(name="description") + robots = ",".join(metadata.meta(name="robots")).casefold() + noindex = "noindex" in robots + + title_key = title.casefold() + if not title: + errors.append(f"{relative}: missing title") + elif not noindex: + if title_key in seen_titles: + errors.append( + f"{relative}: duplicate title also used by {seen_titles[title_key]}" + ) + else: + seen_titles[title_key] = relative + + if len(descriptions) != 1: + errors.append( + f"{relative}: expected one meta description, found {len(descriptions)}" + ) + elif not noindex and not ( + MIN_DESCRIPTION_LENGTH <= len(descriptions[0]) <= MAX_DESCRIPTION_LENGTH + ): + errors.append( + f"{relative}: meta description length is {len(descriptions[0])}" + ) + elif not noindex: + description_key = descriptions[0].casefold() + if description_key in seen_descriptions: + errors.append( + f"{relative}: duplicate description also used by " + f"{seen_descriptions[description_key]}" + ) + else: + seen_descriptions[description_key] = relative + + missing_alt = [ + img for img in metadata.soup.find_all("img") if not img.has_attr("alt") + ] + if missing_alt: + errors.append(f"{relative}: {len(missing_alt)} image(s) missing alt") + + if noindex: + continue + + if metadata.soup.find("h1") is None: + errors.append(f"{relative}: missing a level-one heading") + + canonicals = metadata.links("canonical") + if len(canonicals) != 1 or not canonicals[0].startswith("https://"): + errors.append(f"{relative}: expected one absolute HTTPS canonical URL") + elif canonicals[0] in seen_canonicals: + errors.append( + f"{relative}: duplicate canonical also used by " + f"{seen_canonicals[canonicals[0]]}" + ) + else: + seen_canonicals[canonicals[0]] = relative + + social_properties = {} + for prop in ("og:title", "og:description", "og:type", "og:url", "og:image"): + social_properties[prop] = metadata.meta(prop=prop) + if len(metadata.meta(prop=prop)) != 1: + errors.append(f"{relative}: expected one {prop} property") + twitter_properties = {} + for name in ( + "twitter:card", + "twitter:title", + "twitter:description", + "twitter:image", + ): + twitter_properties[name] = metadata.meta(name=name) + if len(twitter_properties[name]) != 1: + errors.append(f"{relative}: expected one {name} property") + + if social_properties["og:title"] != [title]: + errors.append(f"{relative}: og:title does not match the page title") + if descriptions and social_properties["og:description"] != descriptions: + errors.append( + f"{relative}: og:description does not match the meta description" + ) + if canonicals and social_properties["og:url"] != canonicals: + errors.append(f"{relative}: og:url does not match the canonical URL") + if social_properties["og:image"] and not social_properties["og:image"][ + 0 + ].startswith("https://"): + errors.append(f"{relative}: og:image must use an absolute HTTPS URL") + if twitter_properties["twitter:card"] != ["summary"]: + errors.append(f"{relative}: twitter:card must be summary") + if twitter_properties["twitter:title"] != [title]: + errors.append(f"{relative}: twitter:title does not match the page title") + if descriptions and twitter_properties["twitter:description"] != descriptions: + errors.append( + f"{relative}: twitter:description does not match the meta description" + ) + if ( + social_properties["og:image"] + and twitter_properties["twitter:image"] != social_properties["og:image"] + ): + errors.append(f"{relative}: twitter:image does not match og:image") + + if relative != "index.html": + try: + breadcrumbs = [ + item + for item in metadata.json_ld() + if item.get("@type") == "BreadcrumbList" + ] + except (json.JSONDecodeError, AttributeError) as error: + errors.append(f"{relative}: invalid JSON-LD: {error}") + else: + if len(breadcrumbs) != 1: + errors.append( + f"{relative}: expected one BreadcrumbList JSON-LD object" + ) + else: + breadcrumb_items = breadcrumbs[0].get("itemListElement", ()) + if len(breadcrumb_items) < 2: + errors.append( + f"{relative}: breadcrumb JSON-LD needs at least two items" + ) + elif [item.get("position") for item in breadcrumb_items] != list( + range(1, len(breadcrumb_items) + 1) + ): + errors.append( + f"{relative}: breadcrumb positions must be consecutive" + ) + elif not all( + item.get("name") + and str(item.get("item", "")).startswith("https://") + for item in breadcrumb_items + ): + errors.append( + f"{relative}: breadcrumb names and HTTPS URLs are required" + ) + elif ( + canonicals and breadcrumb_items[-1].get("item") != canonicals[0] + ): + errors.append( + f"{relative}: final breadcrumb must match the canonical URL" + ) + + sitemap = output / "sitemap.xml" + if not sitemap.exists(): + errors.append("sitemap.xml was not generated") + else: + root = ElementTree.parse(sitemap).getroot() + namespace = {"s": "http://www.sitemaps.org/schemas/sitemap/0.9"} + locations = [node.text or "" for node in root.findall("s:url/s:loc", namespace)] + if len(locations) != len(set(locations)): + errors.append("sitemap.xml contains duplicate URLs") + if any(url.endswith("/_cross_api.html") for url in locations): + errors.append("sitemap.xml contains the internal cross API helper") + expected_locations = set(seen_canonicals) + if set(locations) != expected_locations: + missing = expected_locations - set(locations) + unexpected = set(locations) - expected_locations + errors.append( + "sitemap.xml does not match the indexable HTML pages; " + f"missing={sorted(missing)}, unexpected={sorted(unexpected)}" + ) + + if errors: + details = "\n".join(f"- {error}" for error in errors) + raise ExtensionError(f"SEO validation failed:\n{details}") + + +def setup(app: Sphinx) -> None: + app.connect("builder-inited", remove_stale_helpers) + app.connect("env-purge-doc", remove_purged_page) + app.connect("html-page-context", add_seo_context, priority=600) + app.connect("build-finished", validate_seo, priority=900) diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/writers/__init__.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/writers/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/vendor/lief/doc/sphinx/sphinx_lief_doc/writers/html5.py b/vendor/lief/doc/sphinx/sphinx_lief_doc/writers/html5.py new file mode 100644 index 0000000..06adf64 --- /dev/null +++ b/vendor/lief/doc/sphinx/sphinx_lief_doc/writers/html5.py @@ -0,0 +1,42 @@ +from docutils import nodes +from docutils.nodes import title +from sphinx.builders import Builder +from sphinx.util import logging +from sphinx.writers.html5 import HTML5Translator as BaseHTML5Translator +from sphinx_lief_doc.lief_api import liefapi + +logger = logging.getLogger(__name__) + + +class HTML5Translator(BaseHTML5Translator): + def __init__(self, document: nodes.document, builder: Builder) -> None: + super().__init__(document, builder) + self.meta = [tag for tag in self.meta if 'name="viewport"' not in tag] + + def visit_paragraph(self, node: nodes.paragraph): + # We can't have
    element in a

    scope + # NOT ALLOWED: + #

    + #

    hello
    + #

    + # Hence, if a liefapi node is within our children, + # we need to replace with a
    tag. The style of this
    is + # defined by the class fixed-paragraph located in custom.css + if any(isinstance(e, liefapi) for e in node.children): + node.get("classes", []).append("fixed-paragraph") + self.body.append(self.starttag(node, "div")) + else: + super().visit_paragraph(node) + + def depart_paragraph(self, node: nodes.paragraph): + if "fixed-paragraph" in node.get("classes", []): + self.body.append("
    ") + else: + super().depart_paragraph(node) + + def visit_Text(self, node): + if isinstance(node.parent, title): + # Skip encoding + self.body.append(node.astext()) + return + super().visit_Text(node) diff --git a/vendor/lief/doc/sphinx/tools/lief-patchelf/index.md b/vendor/lief/doc/sphinx/tools/lief-patchelf/index.md new file mode 100644 index 0000000..6e6f2fc --- /dev/null +++ b/vendor/lief/doc/sphinx/tools/lief-patchelf/index.md @@ -0,0 +1,63 @@ +(tools-lief-patchelf)= + +# {fa}`solid fa-screwdriver-wrench` lief-patchelf + +`lief-patchelf` is an implementation of the original patchelf created by NixOS +([NixOS/patchelf](https://github.com/NixOS/patchelf)), based on LIEF. + +This LIEF-based version is written in Rust, offering a more robust, modern, and +maintainable implementation compared to the original project. + +:::{admonition} CLI +:class: tip + +It is worth mentioning that `lief-patchelf` maintains the same command-line interface as the +original NixOS implementation, allowing for a seamless transition between +the two versions. +::: + +## Compilation + +You can build `lief-patchelf` using `cargo` from the +`src/tools/lief-patchelf` directory with the following commands: + +```bash +$ cargo build [--release] +$ ./target/{release,debug}/lief-patchelf --version +``` + +Since LIEF is a cross-platform library that supports various platforms and +architectures, you can compile (or cross-compile) this tool for other platforms. +For example, you can generate a Windows ARM64 executable as follows: + +```powershell +rustup.exe target add $RUST_TARGET (optional) +$env:RUSTFLAGS="-Ctarget-feature=+crt-static" +cargo build --target=aarch64-pc-windows-msvc +./target/{release,debug}/lief-patchelf.exe --version +``` + +For more information about the supported platforms, please refer to the +{ref}`Rust Bindings ` section. + +## Man Page + +Given the `lief-patchelf` binary, you can generate a man page using the +following command: + +```bash +$ lief-patchelf --generate-manpage ./lief-patchelf.1 +``` + +This functionality is provided by the [clap_mangen](https://crates.io/crates/clap_mangen) +crate. + +## Shell Completion + +Thanks to [clap](https://github.com/clap-rs/clap) and its `clap_complete` +extension, which generates auto-completion for various shells, you can generate +completion stubs for `lief-patchelf` with: + +```bash +$ ./lief-patchelf --generate {bash, elvish, fish, powershell, zsh} +``` diff --git a/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.md b/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.md new file mode 100644 index 0000000..e65aef8 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.md @@ -0,0 +1,68 @@ +# 01 - Parse and manipulate formats + +The objective of this tutorial is to provide an overview of LIEF's API for +parsing and manipulating formats. + +______________________________________________________________________ + +## ELF + +We'll start with the `ELF` format. To create an {class}`.ELF.Binary` from a +file, simply pass its path to the {sub-ref}`lief-abstract-parse` or {sub-ref}`lief-elf-parse` +functions. + +:::{note} +With the Python API, these functions exhibit the same behavior, but in C++, +{sub-ref}`lief-abstract-parse` will return a pointer to a +{sub-ref}`lief-abstract-binary` object, whereas {sub-ref}`lief-elf-parse` +will return a {sub-ref}`lief-elf-binary` object. +::: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-parse", prepend="import lief") }} + +Once the ELF file has been parsed, we can access its {class}`~lief.ELF.Header`: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-header") }} + +To change the entry point and the target architecture ({class}`~lief.ELF.ARCH`): + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-change-header") }} + +Then, write these changes to a new ELF binary: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-write") }} + +We can also iterate over the {class}`~lief.ELF.Section` entries as follows: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-sections") }} + +To modify the content of the `.text` section: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "elf-text") }} + +## PE + +As with the `ELF` section, you can use the {sub-ref}`lief-abstract-parse` or +{sub-ref}`lief-pe-parse` functions to create a {class}`.PE.Binary` + +{{ literalinclude("../../code/python/tuto_play_formats.py", "pe-parse", prepend="import lief") }} + +To access the various PE headers ({class}`~lief.PE.DosHeader`, +{class}`~lief.PE.Header`, and {class}`~lief.PE.OptionalHeader`): + +{{ literalinclude("../../code/python/tuto_play_formats.py", "pe-headers") }} + +You can also access imported functions in two ways: + +1. Using the *abstract* layer +2. Using the PE definition + +{{ literalinclude("../../code/python/tuto_play_formats.py", "pe-imports") }} + +For finer granularity regarding the location of imported functions in libraries, +or to access other fields of the PE imports, we can process the imports as +follows: + +{{ literalinclude("../../code/python/tuto_play_formats.py", "pe-imports-detailed") }} + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.rst b/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.rst deleted file mode 100644 index 22111b1..0000000 --- a/vendor/lief/doc/sphinx/tutorials/01_play_with_formats.rst +++ /dev/null @@ -1,124 +0,0 @@ -01 - Parse and manipulate formats ---------------------------------- - -The objective of this tutorial is to give an overview of the LIEF's API to parse and manipulate formats - -By Romain Thomas - `@rh0main `_ - ------ - -ELF -~~~ - -We start by the ``ELF`` format. To create an :class:`.ELF.Binary` from a file we just have to give its path to the :func:`lief.parse` or :func:`lief.ELF.parse` functions - -.. note:: - - With the Python API, these functions have the same behaviour but in C++, :cpp:func:`LIEF::Parser::parse` will - return a pointer to a :cpp:class:`LIEF::Binary` object whereas :cpp:func:`LIEF::ELF::Parser::parse` will return - a :cpp:class:`LIEF::ELF::Binary` object - -.. code-block:: python - - import lief - binary = lief.parse("/bin/ls") - -Once the ELF file has been parsed, we can access to its :class:`~lief.ELF.Header`: - -.. code-block:: python - - header = binary.header - -Change the entry point and the target architecture (:class:`~lief.ELF.ARCH`) - -.. code-block:: python - - header.entrypoint = 0x123 - header.machine_type = lief.ELF.ARCH.AARCH64 - -and then rebuild it: - -.. code-block:: python - - binary.write("ls.modified") - -We can also iterate over binary :class:`~lief.ELF.Section`\s as follows: - -.. code-block:: python - - for section in binary.sections: - print(section.name) # section's name - print(section.size) # section's size - print(len(section.content)) # Should match the previous print - - -To modify the content of the ``.text`` section: - -.. code-block:: python - - text = binary.get_section(".text") - text.content = bytes([0x33] * text.size) - - -PE -~~~ - -As for the ``ELF`` part, we can use the :func:`lief.parse` or :func:`lief.PE.parse` functions to create a :class:`.PE.Binary` - - -.. code-block:: python - - import lief - binary = lief.parse("C:\\Windows\\explorer.exe") - - -To access to the different PE headers (:class:`~lief.PE.DosHeader`, :class:`~lief.PE.Header` and :class:`~lief.PE.OptionalHeader`): - -.. code-block:: python - - print(binary.dos_header) - print(binary.header) - print(binary.optional_header) - -One can also access to the imported functions using two methods. The abstract one which will the use the LIEF abstract layer: - -.. code-block:: python - - for func in binary.imported_functions: - print(func) - -To have a better granularity on the location of the imported function in libraries or to access to other fields of the PE imports: - -.. code-block:: python - - for imported_library in binary.imports: - print("Library name: " + imported_library.name) - for func in imported_library.entries: - if not func.is_ordinal: - print(func.name) - print(func.iat_address) - -LIEF enables to modify all the properties of the :class:`~lief.PE.Import` and :class:`~lief.PE.ImportEntry` but to take account of the modification, the :class:`~lief.PE.Builder` must be -configured as follow: - -.. code-block:: python - - builder = lief.PE.Builder(binary) - builder.build_imports(True) - builder.patch_imports(True) - - builder.build() - builder.write("result.exe") - - - - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.md b/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.md new file mode 100644 index 0000000..48d7379 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.md @@ -0,0 +1,158 @@ +(02-pe-from-scratch)= + +# 02 - Create a PE from scratch (Deprecated) + +:::{warning} +This tutorial is no longer functional or accurate for LIEF version >= `0.17.0`. +::: + +In this tutorial, we introduce the LIEF API for creating a simple PE executable +from scratch. + +______________________________________________________________________ + +LIEF enables the creation of a simple PE from scratch. +The aim of this tutorial is to create an executable that shows a +"Hello World" `MessageBoxA`. + +First, we must create a {class}`~lief.PE.Binary`: + +```python +from lief import PE + +binary32 = PE.Binary("pe_from_scratch", PE.PE_TYPE.PE32) +``` + +The first parameter is the binary name, and the second is the binary type: +`PE32` or `PE32_PLUS` (see {class}`~lief.PE.PE_TYPE`). +The {class}`~lief.PE.Binary` constructor automatically creates +{class}`~lief.PE.DosHeader`, {class}`~lief.PE.Header`, +{class}`~lief.PE.OptionalHeader`, and an empty {class}`~lief.PE.DataDirectory`. + +Now that we have a minimal binary, we must add sections. We will have a first +section holding assembly code (`.text`) and a second one containing strings +(`.data`): + +```python +section_text = PE.Section(".text") +section_text.content = code +section_text.virtual_address = 0x1000 + +section_data = PE.Section(".data") +section_data.content = data +section_data.virtual_address = 0x2000 +``` + +A `MessageBoxA` is composed of a title and a message. These two strings can +be stored in the `.data` section as follows: + +```python +title = "LIEF is awesome\0" +message = "Hello World\0" + +data = list(map(ord, title)) +data += list(map(ord, message)) +``` + +The **pseudo** assembly code of the `.text` section is provided in the +following listing: + +```nasm +push 0x00 ; uType +push "LIEF is awesome" ; Title +push "Hello World" ; Message +push 0 ; hWnd +call MessageBoxA ; +push 0 ; uExitCode +call ExitProcess ; +``` + +Instead of pushing strings, we must push the **virtual addresses** of these +strings. In the PE format, a section's virtual address is actually a +**relative** virtual address (relative to {attr}`.OptionalHeader.imagebase` when +ASLR is not enabled). By default, the {class}`~lief.PE.Binary` constructor sets +the {attr}`~lief.PE.OptionalHeader.imagebase` to `0x400000`. + +As a result, the virtual addresses of the strings are: + +> - **title**: {attr}`~lief.PE.OptionalHeader.imagebase` + {attr}`~lief.PE.Section.virtual_address` + 0 = `0x402000` +> - **message**: {attr}`~lief.PE.OptionalHeader.imagebase` + {attr}`~lief.PE.Section.virtual_address` + `len(title)` = `0x402010` + +```nasm +push 0x00 ; uType +push 0x402000 ; Title +push 0x402010 ; Message +push 0 ; hWnd +call MessageBoxA ; +push 0 ; uExitCode +call ExitProcess ; +``` + +As the code uses `MessageBoxA`, we need to import `user32.dll` into the +binary's {class}`~lief.PE.Import` entries and add the `MessageBoxA` +{class}`~lief.PE.ImportEntry`. +To do so, we can use the {meth}`~lief.PE.Binary.add_library` method combined +with {meth}`~lief.PE.Import.add_entry`: + +```python +user32 = binary32.add_library("user32.dll") +user32.add_entry("MessageBoxA") +``` + +The same applies to `ExitProcess` (`kernel32.dll`): + +```python +kernel32 = binary32.add_library("kernel32.dll") +kernel32.add_entry("ExitProcess") +``` + +Once the necessary libraries and functions have been added to the binary, +we must determine their addresses (**I**mport **A**ddress **T**able). + +To do so, we can use the `lief.PE.Binary.predict_function_rva` method, which +returns the `IAT` address set by the {class}`~lief.PE.Builder`: + +```python +ExitProcess_addr = binary32.predict_function_rva("kernel32.dll", "ExitProcess") +MessageBoxA_addr = binary32.predict_function_rva("user32.dll", "MessageBoxA") +print("Address of 'ExitProcess': 0x{:06x} ".format(ExitProcess_addr)) +print("Address of 'MessageBoxA': 0x{:06x} ".format(MessageBoxA_addr)) +``` + +```console +Address of 'ExitProcess': 0x00306a +Address of 'MessageBoxA': 0x00305c +``` + +Thus, the **absolute** virtual addresses of `MessageBoxA` and +`ExitProcess` are: + +> - `MessageBoxA`: {attr}`~lief.PE.OptionalHeader.imagebase` + `0x306a` = `0x40306a` +> - `ExitProcess`: {attr}`~lief.PE.OptionalHeader.imagebase` + `0x305c` = `0x40305c` + +And the associated assembly code: + +```nasm +push 0x00 ; uType +push 0x402000 ; Title +push 0x402010 ; Message +push 0 ; hWnd +call 0x40306a ; +push 0 ; uExitCode +call 0x40305c ; +``` + +The transformation of the {class}`~lief.PE.Binary` into an executable is +performed by the {class}`~lief.PE.Builder` class. + +By default, the import table is not rebuilt, so we must configure the builder +to rebuild it: + +```python +builder = lief.PE.Builder(binary32) +builder.build_imports(True) +builder.build() +builder.write("pe_from_scratch.exe") +``` + +You can now use the newly created binary. diff --git a/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.rst b/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.rst deleted file mode 100644 index 6c3a89c..0000000 --- a/vendor/lief/doc/sphinx/tutorials/02_pe_from_scratch.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. _02-pe-from-scratch: - -02 - Create a PE from scratch ------------------------------ - -In this tutorial we introduce LIEF API to create a simple PE executable from scratch - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ----------- - -LIEF enables to create simple PE from scratch. The aim of this tutorial is to create an executable which pop a ``MessageBoxA`` with "Hello Word" - -First, we have to create a :class:`~lief.PE.Binary` : - - -.. code-block:: python - - from lief import PE - - binary32 = PE.Binary("pe_from_scratch", PE.PE_TYPE.PE32) - -The first parameter is the binary's name and the second, the binary's type: ``PE32`` or ``PE32_PLUS`` (see :class:`~lief.PE.PE_TYPE`). -The :class:`~lief.PE.Binary`'s constructor creates automatically :class:`~lief.PE.DosHeader`, :class:`~lief.PE.Header`, :class:`~lief.PE.OptionalHeader` an empty :class:`~lief.PE.DataDirectory`. - -Now that we have a minimal binary, we have to add sections. We will have a first section holding assembly code (``.text``) and a second one containing strings (``.data``): - -.. code-block:: python - - section_text = PE.Section(".text") - section_text.content = code - section_text.virtual_address = 0x1000 - - section_data = PE.Section(".data") - section_data.content = data - section_data.virtual_address = 0x2000 - -A ``MessageBoxA`` is composed of a title and a message. These two strings can be stored in the ``.data`` as follows: - -.. code-block:: python - - title = "LIEF is awesome\0" - message = "Hello World\0" - - data = list(map(ord, title)) - data += list(map(ord, message)) - -The **pseudo** assembly code of the ``.text`` section is given in next listing: - -.. code-block:: nasm - - push 0x00 ; uType - push "LIEF is awesome" ; Title - push "Hello World" ; Message - push 0 ; hWnd - call MessageBoxA ; - push 0 ; uExitCode - call ExitProcess ; - - -Instead of pushing strings we have to push the **virtual address** of these strings. In the PE format a section's virtual address is in fact a **relative** virtual address (relative to :attr:`.OptionalHeader.imagebase` when the ASLR is not enabled). By default the :class:`~lief.PE.Binary`'s constructor sets the :attr:`~lief.PE.OptionalHeader.imagebase` to ``0x400000``. - -As a result, the virtual addresses of the strings are: - - * **title**: :attr:`~lief.PE.OptionalHeader.imagebase` + :attr:`~lief.PE.Section.virtual_address` + 0 = ``0x402000`` - * **message**: :attr:`~lief.PE.OptionalHeader.imagebase` + :attr:`~lief.PE.Section.virtual_address` + ``len(title)`` = ``0x402010`` - -.. code-block:: nasm - - push 0x00 ; uType - push 0x402000 ; Title - push 0x402010 ; Message - push 0 ; hWnd - call MessageBoxA ; - push 0 ; uExitCode - call ExitProcess ; - -As the code uses ``MessageBoxA``, we need to import ``user32.dll`` into the binary's :class:`~lief.PE.Import`\s and the ``MessageBoxA`` :class:`~lief.PE.ImportEntry`. -To do so, we can use the :meth:`~lief.PE.Binary.add_library` method combined with :meth:`~lief.PE.Import.add_entry`: - -.. code-block:: python - - user32 = binary32.add_library("user32.dll") - user32.add_entry("MessageBoxA") - -Same for ``ExitProcess`` (``kernel32.dll``): - -.. code-block:: python - - kernel32 = binary32.add_library("kernel32.dll") - kernel32.add_entry("ExitProcess") - -Once needed libraries and functions are added to the binary, we have to determine their addresses (**I**\mport **A**\ddress **T**\able). - -For that, we can use the :meth:`~lief.PE.Binary.predict_function_rva` method which will return the ``IAT`` address set by the :class:`~lief.PE.Builder`: - - -.. automethod:: lief.PE.Binary.predict_function_rva - :noindex: - - -.. code-block:: python - - ExitProcess_addr = binary32.predict_function_rva("kernel32.dll", "ExitProcess") - MessageBoxA_addr = binary32.predict_function_rva("user32.dll", "MessageBoxA") - print("Address of 'ExitProcess': 0x{:06x} ".format(ExitProcess_addr)) - print("Address of 'MessageBoxA': 0x{:06x} ".format(MessageBoxA_addr)) - - -.. code-block:: console - - Address of 'ExitProcess': 0x00306a - Address of 'MessageBoxA': 0x00305c - -Thus, the **absolute** virtual addresses of ``MessageBoxA`` and ``ExitProcess`` are: - - * ``MessageBoxA``: :attr:`~lief.PE.OptionalHeader.imagebase` + ``0x306a`` = ``0x40306a`` - * ``ExitProcess``: :attr:`~lief.PE.OptionalHeader.imagebase` + ``0x305c`` = ``0x40305c`` - -And the associated assembly code: - -.. code-block:: nasm - - push 0x00 ; uType - push 0x402000 ; Title - push 0x402010 ; Message - push 0 ; hWnd - call 0x40306a ; - push 0 ; uExitCode - call 0x40305c ; - - -The transformation of the :class:`~lief.PE.Binary` into an executable is performed by the :class:`~lief.PE.Builder` class. - -By default the import table is not rebuilt so we have to configure the builder to rebuild it: - -.. code-block:: python - - builder = lief.PE.Builder(binary32) - builder.build_imports(True) - builder.build() - builder.write("pe_from_scratch.exe") - - -You can now enjoy the newly created binary. - - - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.md b/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.md new file mode 100644 index 0000000..b960359 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.md @@ -0,0 +1,117 @@ +# 03 - Play with ELF symbols + +In this tutorial, we will see how to modify dynamic symbols in both an +executable and a library. + +______________________________________________________________________ + +When a library is dynamically linked to an executable, the required libraries +are referenced in the `DT_NEEDED` entries within the dynamic table +(`PT_DYNAMIC`). + +Additionally, functions imported from this library are referenced in the +dynamic symbols table with the following attributes: + +- {attr}`~lief.ELF.Symbol.value` set to `0` +- {attr}`~lief.ELF.Symbol.type` set to {attr}`~lief.ELF.Symbol.TYPE.FUNC` + +Similarly, when a library exports functions, they are registered in the +dynamic symbols table with the following attributes: + +- {attr}`~lief.ELF.Symbol.value` set to the address of the function in the library +- {attr}`~lief.ELF.Symbol.type` set to {attr}`~lief.ELF.Symbol.TYPE.FUNC` + +Imported and exported functions are abstracted in LIEF, and you can iterate +over these elements using the following properties: +{attr}`~lief.Binary.exported_functions` and {attr}`~lief.Binary.imported_functions` + +{{ literalinclude("../../code/python/tuto_elf_symbols.py", "imported-exported") }} + +When analyzing a binary, imported functions can reveal information about its +underlying functionality. To avoid revealing these symbols, one solution could +be to statically link the library with the executable. Another solution is to +confuse the reverse engineer by swapping these symbols, which is the purpose +of this tutorial. + +Consider the following code: + +```C +#include +#include +#include + +double hashme(double input) { + return pow(input, 4) + log(input + 3); +} + +int main(int argc, char** argv) { + if (argc != 2) { + printf("Usage: %s N\n", argv[0]); + return EXIT_FAILURE; + } + + double N = (double)atoi(argv[1]); + double hash = hashme(N); + printf("%f\n", hash); + + return EXIT_SUCCESS; +} +``` + +Basically, this program takes an integer as a parameter and performs a +computation on this value. + +```console +$ hashme 123 +228886645.836282 +``` + +```{image} ../_static/tutorial/03/hashme.png +:align: center +:scale: 60 % +``` + +The `pow` and `log` functions are located in the `libm.so.6` library. +Using LIEF, we can swap these function **names** with other function **names**. +For example, let's swap `pow` and `log` with `cos` and `sin`: + +First, we must load both the library and the executable: + +{{ literalinclude("../../code/python/tuto_elf_symbols.py", "load", prepend="import lief") }} + +Then, we can change the names of the two imported functions in the +**executable**: + +{{ literalinclude("../../code/python/tuto_elf_symbols.py", "change-imported") }} + +And we must do the same in the library: the `log` symbol name is swapped +with `sin`, and `pow` with `cos`: + +{{ literalinclude("../../code/python/tuto_elf_symbols.py", "swap-all") }} + +```{image} ../_static/tutorial/03/hashme_obf.png +:align: center +:scale: 60 % +``` + +At this point, we have a modified version of `libm.so` in the same directory +as `hashme.obf`. To force the loading of this modified version of +`libm.so`, we can set the `LD_LIBRARY_PATH` environment variable: + +```console +$ LD_LIBRARY_PATH=. hashme.obf 123 +228886645.836282 +``` + +Without this environment variable, the Linux loader would resolve `libm.so` +using the original path, and the computation would be performed using `sin` +and `cos`: + +```console +$ hashme.obf 123 +-0.557978 +``` + +Another more realistic use case could involve swapping symbols in +cryptographic libraries like OpenSSL. For example, `EVP_DecryptInit` and +`EVP_EncryptInit` have the same prototype and could be swapped. diff --git a/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.rst b/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.rst deleted file mode 100644 index 96a45dd..0000000 --- a/vendor/lief/doc/sphinx/tutorials/03_elf_change_symbols.rst +++ /dev/null @@ -1,175 +0,0 @@ -03 - Play with ELF symbols --------------------------- - -In this tutorial we will see how to modify dynamic symbols in both a binary and a library. - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ------ - -When a binary is linked against a library, the library needed is stored in a ``DT_NEEDED`` entry from the -dynamic table and the needed functions needed are registered in the dynamic symbols table with the following attributes: - -* :attr:`~lief.ELF.Symbol.value` set to ``0`` -* :attr:`~lief.ELF.Symbol.type` set to :attr:`~lief.ELF.SYMBOL_TYPES.FUNC` - -Similarly, when a library exports functions it has a ``DT_SONAME`` entry in the dynamic table and the functions -exported are registered in the dynamic symbols table with the following attributes: - -* :attr:`~lief.ELF.Symbol.value` set to address of the function in the library -* :attr:`~lief.ELF.Symbol.type` set to :attr:`~lief.ELF.SYMBOL_TYPES.FUNC` - -Imported and exported functions are abstracted by LIEF thus you can iterate over these elements with :attr:`~lief.Binary.exported_functions` and :attr:`~lief.Binary.imported_functions` - -.. code-block:: python - - import lief - binary = lief.parse("/usr/bin/ls") - library = lief.parse("/usr/lib/libc.so.6") - - print(binary.imported_functions) - print(library.exported_functions) - - -When analyzing a binary, imported function names are very helpful for the reverse engineering. One solution is to link statically the binary and the library. -Another solution is to blow mind the reverser's mind by swapping these symbols. - -Take a look at the following code: - -.. code-block:: C - - #include - #include - #include - - double hashme(double input) { - return pow(input, 4) + log(input + 3); - } - - int main(int argc, char** argv) { - if (argc != 2) { - printf("Usage: %s N\n", argv[0]); - return EXIT_FAILURE; - } - - double N = (double)atoi(argv[1]); - double hash = hashme(N); - printf("%f\n", hash); - - return EXIT_SUCCESS; - } - -Basically, this program takes an integer as argument and performs some computation on this value. - -.. code-block:: console - - $ hashme 123 - 228886645.836282 - -.. image:: ../_static/tutorial/03/hashme.png - :scale: 60 % - :align: center - - - -The ``pow`` and ``log`` functions are located in the ``libm.so.6`` library. One interesting trick to do with LIEF is -to swap this function **name** with other functions **name**. In this tutorial we will swap them with ``cos`` and ``sin`` functions. - -First we have to load both the library and the binary: - -.. code-block:: python - - #!/usr/bin/env python3 - import lief - - - hashme = lief.parse("hashme") - libm = lief.parse("/usr/lib/libm.so.6") - -Then when change the name of the two imported functions in the **binary**: - - -.. code-block:: python - - hashme_pow_sym = next(filter(lambda e : e.name == "pow", my_binary.imported_symbols)) - hashme_log_sym = next(filter(lambda e : e.name == "log", my_binary.imported_symbols)) - - hashme_pow_sym.name = "cos" - hashme_log_sym.name = "sin" - - -finally we swap ``log`` with ``sin`` and ``pow`` with ``cos`` in the **library** and we rebuild the two objects: - -.. code-block:: python - - #!/usr/bin/env python3 - import lief - - - hashme = lief.parse("hashme") - libm = lief.parse("/usr/lib/libm.so.6") - - - def swap(obj, a, b): - symbol_a = next(filter(lambda e : e.name == a, obj.dynamic_symbols)) - symbol_b = next(filter(lambda e : e.name == b, obj.dynamic_symbols)) - b_name = symbol_b.name - symbol_b.name = symbol_a.name - symbol_a.name = b_name - - hashme_pow_sym = next(filter(lambda e : e.name == "pow", my_binary.imported_symbols)) - hashme_log_sym = next(filter(lambda e : e.name == "log", my_binary.imported_symbols)) - - hashme_pow_sym.name = "cos" - hashme_log_sym.name = "sin" - - - swap(libm, "log", "sin") - swap(libm, "pow", "cos") - - hashme.write("hashme.obf") - libm.write("libm.so.6") - -.. image:: ../_static/tutorial/03/hashme_obf.png - :scale: 60 % - :align: center - - -With this script, we built a modified ``libm`` in our current directory and we have to force the Linux loader to use this one when executing ``binary.obf``. -To do so we export ``LD_LIBRARY_PATH`` to the current directory: - -.. code-block:: console - - $ LD_LIBRARY_PATH=. hashme.obf 123 - 228886645.836282 - -If we omit it, it will use the default ``libm`` and hash computation will be done with ``sin`` and ``cos``: - - -.. code-block:: console - - $ hashme.obf 123 - -0.557978 - - -One real use case could be to swap symbols in cryptographic libraries like OpenSSL. For example ``EVP_DecryptInit`` and ``EVP_EncryptInit`` have the same prototype so we could swap them. - - - - - - - - - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.md b/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.md new file mode 100644 index 0000000..69a798e --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.md @@ -0,0 +1,74 @@ +# 04 - ELF Hooking + +The objective of this tutorial is to hook a library function. + +______________________________________________________________________ + +In the previous tutorial, we saw how to swap symbol names in a shared library. +We will now see the mechanism for hooking a function in a shared library. + +The targeted library is the standard math library (`libm.so`), and we will +insert a hook on the `exp` function so that {math}`\exp(x) = x + 1`. +The source code of the sample that uses this function is provided in the +following listing: + +```cpp +#include +#include +#include + +int main(int argc, char **argv) { + if (argc != 2) { + printf("Usage: %s \n", argv[0]); + exit(-1); + } + + int a = atoi(argv[1]); + printf("exp(%d) = %f\n", a, exp(a)); + return 0; +} +``` + +The hook function is as follows: + +```cpp +double hook(double x) { + return x + 1; +} +``` + +Compiled with {code}`gcc -Os -nostdlib -nodefaultlibs -fPIC -Wl,-shared hook.c -o hook`. + +To inject this hook into the library, we use the {meth}`~lief.ELF.Binary.add` (segment) method: + +```{eval-rst} +.. automethod:: lief.ELF.Binary.add + :noindex: +``` + +First, we find the code for our hook function and add it to the library: + +{{ literalinclude("../../code/python/tuto_elf_hooking.py", "inject") }} + +Once the stub is injected, we must calculate the new address for the `exp` +symbol and update it: + +{{ literalinclude("../../code/python/tuto_elf_hooking.py", "update") }} + +Note that we must update the symbol type to a regular {title-reference}`FUNC` because, on many +distributions, {title-reference}`libm.so` is built with automatic hardware detection and exposes +symbols as [GNU_IFUNC](https://sourceware.org/glibc/wiki/GNU_IFUNC), which uses a different dynamic binding protocol +compared to regular functions. + +Finally, we write the patched library to a file in the current directory: + +{{ literalinclude("../../code/python/tuto_elf_hooking.py", "write") }} + +To test the patched library: + +```console +$ ./do_math.bin 1 +exp(1) = 2.718282 +$ LD_LIBRARY_PATH=. ./do_math.bin 1 +exp(1) = 2.000000 +``` diff --git a/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.rst b/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.rst deleted file mode 100644 index 97f67b5..0000000 --- a/vendor/lief/doc/sphinx/tutorials/04_elf_hooking.rst +++ /dev/null @@ -1,70 +0,0 @@ -04 - ELF Hooking ----------------- - -The objective of this tutorial is to hook a library function - -Scripts and materials are available here: `materials `_ - -By Romain Thomas - `@rh0main `_ - ------- - -In the previous tutorial we saw how to swap symbols names from a shared library, we will now see the mechanism to hook a function in a shared library. - -The targeted library is the standard math library (``libm.so``) and we will insert a hook on the ``exp`` function so that :math:`exp(x) = x + 1`. The source code of the sample that uses this function is given in the following listing: - -.. code-block:: cpp - - #include - #include - #include - - int main(int argc, char **argv) { - if (argc != 2) { - printf("Usage: %s \n", argv[0]); - exit(-1); - } - - int a = atoi(argv[1]); - printf("exp(%d) = %f\n", a, exp(a)); - return 0; - } - - -The hooking function is as simple as: - -.. code-block:: cpp - - double hook(double x) { - return x + 1; - } - -Compiled with :code:`gcc -Os -nostdlib -nodefaultlibs -fPIC -Wl,-shared hook.c -o hook`. - -To inject this hook into the library, we use the :meth:`~lief.ELF.Binary.add` (segment) method - -.. automethod:: lief.ELF.Binary.add - :noindex: - -Once the stub is injected we just have to change the address of the ``exp`` symbol: - -.. code-block:: python - - exp_symbol = libm.get_symbol("exp") - hook_symbol = hook.get_symbol("hook") - - exp_symbol.value = segment_added.virtual_address + hook_symbol.value - - -To test the patched library: - -.. code-block:: console - - $ ./do_math.bin 1 - exp(1) = 2.718282 - LD_LIBRARY_PATH=. ./do_math.bin 1 - exp(1) = 2.000000 - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.md b/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.md new file mode 100644 index 0000000..432e3ab --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.md @@ -0,0 +1,174 @@ +# 05 - Infecting the PLT/GOT + +The objective of this tutorial is to hook an imported function in an ELF binary. + +______________________________________________________________________ + +Hooking imported functions by infecting the `.got` section is a well-known +technique [^f1] [^f2], and this tutorial focuses on its implementation using +LIEF. + +These figures illustrate the PLT/GOT mechanism: + +:::{figure} ../_static/tutorial/05/pltgot.png +:align: center + +With lazy binding, the first time the function is called, the `got` entry +redirects to the PLT instruction. +::: + +:::{figure} ../_static/tutorial/05/pltgot3.png +:align: center + +The second time, the `got` entry holds the address in the shared library. +::: + +Basically, the infection is done in two steps: + +> - First, we inject our hook. +> - Second, we redirect the targeted function to our hook by patching the `got`. + +This can be summarized by the following figure: + +:::{figure} ../_static/tutorial/05/pltgot2.png +:align: center +::: + +As an example, we will use a basic *crackme* that performs a +{manpage}`memcmp(3)` on the flag and user input. + +```cpp +#include +#include +#include + +// Damn_YoU_Got_The_Flag +char password[] = "\x18\x3d\x31\x32\x03\x05\x33\x09\x03\x1b\x33\x28\x03\x08\x34\x39\x03\x1a\x30\x3d\x3b"; + +inline int check(char* input); + +int check(char* input) { + for (int i = 0; i < sizeof(password) - 1; ++i) { + password[i] ^= 0x5c; + } + return memcmp(password, input, sizeof(password) - 1); +} + +int main(int argc, char **argv) { + if (argc != 2) { + printf("Usage: %s \n", argv[0]); + return EXIT_FAILURE; + } + + if (strlen(argv[1]) == (sizeof(password) - 1) && check(argv[1]) == 0) { + puts("You got it !!"); + return EXIT_SUCCESS; + } + + puts("Wrong"); + return EXIT_FAILURE; + +} +``` + +The flag is XORed with `0x5C`. To validate the *crackme*, the user must +enter `Damn_YoU_Got_The_Flag`: + +```console +$ crackme.bin foo +Wrong +$ crackme.bin Damn_YoU_Got_The_Flag +You got it !! +``` + +The hook will consist of printing the arguments of `memcmp` and returning +`0`: + +```cpp +#include "arch/x86_64/syscall.c" +#define stdout 1 + +int my_memcmp(const void* lhs, const void* rhs, int n) { + const char msg[] = "Hook memcmp\n"; + _write(stdout, msg, sizeof(msg)); + _write(stdout, (const char*)lhs, n); + _write(stdout, "\n", 2); + _write(stdout, (const char*)rhs, n); + _write(stdout, "\n", 2); + return 0; +} +``` + +Since the hook will be injected into the crackme, it must meet the following +requirements: + +- Assembly code must be *position-independent* (compiled with `-fPIC` or `-pie/-fPIE` flags). +- It must not use external libraries such as `libc.so` (`-nostdlib -nodefaultlibs` flags). + +Due to these requirements, the hook is compiled with: +{code}`gcc -nostdlib -nodefaultlibs -fPIC -Wl,-shared hook.c -o hook`. + +## Injecting the hook + +The first step is to inject the hook into the binary. To do so, we will add a +{class}`~lief.ELF.Segment`: + +{{ literalinclude("../../code/python/tuto_elf_plt_got.py", "inject", prepend="import lief") }} + +All assembly code for the hook is contained in the first +{attr}`~lief.ELF.Segment.TYPE.LOAD` segment of `hook`. + +Once the hook is added, its virtual address will be the +{attr}`~lief.ELF.Segment.virtual_address` of `segment_added`, and we can +proceed with the `got` patching. + +## Patching the `got` + +LIEF provides a function to easily patch the `got` entry associated with a +{class}`~lief.ELF.Symbol`: + +```{eval-rst} +.. automethod:: lief.ELF.Binary.patch_pltgot + :noindex: +``` + +The offset of the `memcmp` function is stored in the +{attr}`~lief.ELF.Symbol.value` attribute of the associated dynamic symbol. +Thus, its virtual address will be: + +- `my_memcmp`: {attr}`~lief.ELF.Symbol.value` + `segment_added.virtual_address` + +{{ literalinclude("../../code/python/tuto_elf_plt_got.py", "hook-address") }} + +Finally, we can patch `memcmp` from the crackme with this value: + +{{ literalinclude("../../code/python/tuto_elf_plt_got.py", "patch-got") }} + +And rebuild it: + +{{ literalinclude("../../code/python/tuto_elf_plt_got.py", "rebuild") }} + +## Run + +Since a check on the input size is performed before checking the flag value, we +must provide an input with the correct length (regardless of its content): + +```console +$ crackme.hooked XXXXXXXXXXXXXXXXXXXXX +Hook memcmp +Damn_YoU_Got_The_Flag +XXXXXXXXXXXXXXXXXXXXX +You got it !! +``` + +```{rubric} References +``` + +```{eval-rst} +.. role:: strike + :class: strike +``` + +[^f1]: {strike}`hxxp://vxheaven.org/lib/vrn00.html` + +[^f2]: diff --git a/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.rst b/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.rst deleted file mode 100644 index 6adffe3..0000000 --- a/vendor/lief/doc/sphinx/tutorials/05_elf_infect_plt_got.rst +++ /dev/null @@ -1,186 +0,0 @@ -05 - Infecting the plt/got --------------------------- - -The objective of this tutorial is to hook an imported function in an ELF binary. - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ------ - -Hooking imported functions by infecting the ``.got`` section is a well-known technique [#f1]_ [#f2]_ and this tutorial will be focused -on its implementation using LIEF. - -These figures illustrate the ``plt/got`` mechanism: - -.. figure:: ../_static/tutorial/05/pltgot.png - :scale: 40 % - :align: center - - With lazy binding, the first time that the function is called the ``got`` entry redirects to the plt instruction. - - -.. figure:: ../_static/tutorial/05/pltgot3.png - :scale: 40 % - :align: center - - The Second time, ``got`` entry holds the address in the shared library. - - - -Basically the infection is done in two steps: - - * Firstly, we inject our hook - * Secondly, we redirect the targeted function to our hook by patching the ``got`` - -It can be summed up by the following figure: - -.. figure:: ../_static/tutorial/05/pltgot2.png - :scale: 50 % - :align: center - - -As example, we will use a basic *crackme* which performs a :manpage:`memcmp(3)` on the flag and user's input. - -.. code-block:: cpp - - #include - #include - #include - - // Damn_YoU_Got_The_Flag - char password[] = "\x18\x3d\x31\x32\x03\x05\x33\x09\x03\x1b\x33\x28\x03\x08\x34\x39\x03\x1a\x30\x3d\x3b"; - - inline int check(char* input); - - int check(char* input) { - for (int i = 0; i < sizeof(password) - 1; ++i) { - password[i] ^= 0x5c; - } - return memcmp(password, input, sizeof(password) - 1); - } - - int main(int argc, char **argv) { - if (argc != 2) { - printf("Usage: %s \n", argv[0]); - return EXIT_FAILURE; - } - - if (strlen(argv[1]) == (sizeof(password) - 1) && check(argv[1]) == 0) { - puts("You got it !!"); - return EXIT_SUCCESS; - } - - puts("Wrong"); - return EXIT_FAILURE; - - } - -The flag is *xored* with ``0x5C``. To validate the *crackme*, the user has to enter ``Damn_YoU_Got_The_Flag``: - -.. code-block:: console - - $ crackme.bin foo - Wrong - $ crackme.bin Damn_YoU_Got_The_Flag - You got it !! - -The hook will consist in printing arguments of ``memcmp`` and returning ``0``: - -.. code-block:: cpp - - #include "arch/x86_64/syscall.c" - #define stdout 1 - - int my_memcmp(const void* lhs, const void* rhs, int n) { - const char msg[] = "Hook memcmp\n"; - _write(stdout, msg, sizeof(msg)); - _write(stdout, (const char*)lhs, n); - _write(stdout, "\n", 2); - _write(stdout, (const char*)rhs, n); - _write(stdout, "\n", 2); - return 0; - } - -As the hook is going to be injected into the crackme, it must have the following requirements: - -* Assembly code must be *position independant* (compiled with ``-fPIC`` or ``-pie/-fPIE`` flags) -* Don't use external libraries such as ``libc.so`` (``-nostdlib -nodefaultlibs`` flags) - - -Due to the requirements, the hook is compiled with: :code:`gcc -nostdlib -nodefaultlibs -fPIC -Wl,-shared hook.c -o hook`. - -Injecting the hook -~~~~~~~~~~~~~~~~~~ - -The first step is to inject the hook into the binary. To do so we will add a :class:`~lief.ELF.Segment`: - -.. code-block:: python - - import lief - - crackme = lief.parse("crackme.bin") - hook = lief.parse("hook") - - segment_added = crackme.add(hook.segments[0]) - -All assembly code of the hook stands in the first :attr:`~lief.ELF.SEGMENT_TYPES.LOAD` segment of ``hook``. - -Once the hook added, its virtual address is :attr:`~lief.ELF.Segment.virtual_address` of ``segment_added`` and we can processed to the ``got`` patching. - -Patching the ``got`` -~~~~~~~~~~~~~~~~~~~~ - -LIEF provides a function to easily patch the ``got`` entry associated with a :class:`~lief.ELF.Symbol`: - - -.. automethod:: lief.ELF.Binary.patch_pltgot - :noindex: - -The offset of the ``memcmp`` function is stored in the :attr:`~lief.ELF.Symbol.value` attribute of the associated dynamic symbol. Thus its virtual address will be: - -* ``my_memcpy``: :attr:`~lief.ELF.Symbol.value` + ``segment_added.virtual_address`` - -.. code-block:: python - - my_memcmp = hook.get_symbol("my_memcmp") - my_memcmp_addr = segment_added.virtual_address + my_memcmp.value - -Finally we can patch the ``memcmp`` from the crakme with this value: - -.. code-block:: python - - crackme.patch_pltgot('memcmp', my_memcmp_addr) - -And rebuild it: - -.. code-block:: python - - crackme.write("crackme.hooked") - - -Run -~~~ - -As a check on the input size is performed before checking the flag value, we have to provide an input with the correct length (no matter its content): - -.. code-block:: console - - $ crackme.hooked XXXXXXXXXXXXXXXXXXXXX - Hook add - Damn_YoU_Got_The_Flag - XXXXXXXXXXXXXXXXXXXXX - You got it !! - - -.. rubric:: References - -.. role:: strike - :class: strike - -.. [#f1] :strike:`hxxp://vxheaven.org/lib/vrn00.html` -.. [#f2] http://phrack.org/issues/56/7.html - - diff --git a/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.md b/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.md new file mode 100644 index 0000000..525f625 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.md @@ -0,0 +1,151 @@ +(06-pe-hooking)= + +# 06 - PE Hooking (Deprecated) + +:::{warning} +This tutorial is no longer functional as the PE hooking functions have been +removed from LIEF. +::: + +The objective of this tutorial is to show how to hook imported functions. + +______________________________________________________________________ + +The targeted binary is a simple `PE64` *HelloWorld* that prints the first +argument to the console: + +```cpp +#include "stdafx.h" +#include + +int main(int argc, char** argv) { + printf("Hello: %s\n", argv[1]); + return 0; +} +``` + +```console +$ PE64_x86-64_binary_HelloWorld.exe World +$ Hello: World +``` + +Using LIEF, we will replace the function that prints the message to the console +with a `MessageBox`. + +By disassembling the binary, we can see that the *print* occurs in the function +`sub_140001030`, which uses two external functions: `__acrt_iob_func` and +`__stdio_common_vfprintf`. + +:::{figure} ../_static/tutorial/06/06_hooking_1.png +:align: center +:scale: 80 % +::: + +:::{figure} ../_static/tutorial/06/06_hooking_2.png +:align: center +:scale: 80 % +::: + +According to the Microsoft x64 calling convention, the format string is located +in the `rcx` register, and the input message is in the `rdx` register. + +Basically, the {ref}`hooking-code` replaces the `__acrt_iob_func` function and +displays a `MessageBox` with the `rdx` message. + +```{code-block} nasm +:caption: hooking code +:name: hooking-code + +add rsp, 0x48 ; Stack unwind +xor rcx, rcx ; hWnd +mov rdx, rdx ; Message +mov r8, 0x0140009000 ; Title +xor r9, r9 ; MB_OK +mov rax, 0x014000A3E4 ; MessageBoxA address +call [rax] ; MessageBoxA(hWnd, Message, Title, MB_OK) +xor rcx, rcx ; exit value +mov rax, 0x014000A3d4 ; ExitProcess address +call [rax] ; ExitProcess(0) +ret ; Never reached +``` + +:::{note} +As in tutorial {ref}`02-pe-from-scratch`, the addresses of `MessageBoxA` +and `ExitProcess` can be found using the function: +::: + +First, we create the `.htext` section, which will hold the hooking code: + +```python +section_text = lief.PE.Section(".htext") +section_text.content = code +section_text.virtual_address = 0x7000 +section_text.characteristics = lief.PE.Section.CHARACTERISTICS.CNT_CODE | lief.PE.Section.CHARACTERISTICS.MEM_READ | lief.PE.Section.CHARACTERISTICS.MEM_EXECUTE + +section_text = pe.add_section(section_text) +``` + +Next, we create the `.hdata` section for the `MessageBox` title: + +```python +title = "LIEF is awesome\0" +data = list(map(ord, title)) + +section_data = lief.PE.Section(".hdata") +section_data.content = data +section_data.virtual_address = 0x8000 +section_data.characteristics = lief.PE.Section.CHARACTERISTICS.CNT_INITIALIZED_DATA | lief.PE.Section.CHARACTERISTICS.MEM_READ + +section_data = pe.add_section(section_data) +``` + +Since ASLR is enabled, we will disable it to avoid dealing with relocations: + +{{ literalinclude("../../code/python/tuto_pe_hooking.py", "disable-aslr") }} + +We will also disable `NX` protection: + +{{ literalinclude("../../code/python/tuto_pe_hooking.py", "disable-nx") }} + +As `ExitProcess` is not imported in `KERNEL32.dll`, we need to add it: + +{{ literalinclude("../../code/python/tuto_pe_hooking.py", "add-exitprocess") }} + +The `MessageBoxA` function is located in `user32.dll`, so we must add it: + +```python +user32 = binary.add_library("user32.dll") +user32.add_entry("MessageBoxA") +``` + +Then, we proceed to hook the `__acrt_iob_func` function: + +```python +pe.hook_function("__acrt_iob_func", binary.optional_header.imagebase + section_text.virtual_address) +``` + +Finally, we configure the {class}`~lief.PE.Builder` to create a new import +table and patch the original one with trampolines. + +```python +builder = lief.PE.Builder(binary) + +builder.build_imports(True).patch_imports(True) + +builder.build() + +builder.write("lief_pe_hooking.exe") +``` + +Now we can run the final executable: + +```console +$ lief_pe_hooking.exe "Hooking World" +``` + +:::{figure} ../_static/tutorial/06/06_hooking_3.png +:align: center +:scale: 80 % +::: + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.rst b/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.rst deleted file mode 100644 index d94d34b..0000000 --- a/vendor/lief/doc/sphinx/tutorials/06_pe_hooking.rst +++ /dev/null @@ -1,157 +0,0 @@ -06 - PE Hooking ---------------- - -The objective of this tutorial is show how we can hook imported functions - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ------- - -The targeted binary is a simple ``PE64`` *HelloWorld* which prints the first argument on in the console: - -.. code-block:: cpp - - #include "stdafx.h" - #include - - int main(int argc, char** argv) { - printf("Hello: %s\n", argv[1]); - return 0; - } - -.. code-block:: console - - $ PE64_x86-64_binary_HelloWorld.exe World - $ Hello: World - -Using LIEF, we will replace the function that prints the message in the console with a ``MessageBox`` - -By disassembling the binary we can see that the *print* occurs in the function ``sub_140001030`` and it uses two -external functions: ``__acrt_iob_func`` and ``__stdio_common_vfprintf``. - - -.. figure:: ../_static/tutorial/06/06_hooking_1.png - :scale: 80 % - :align: center - - -.. figure:: ../_static/tutorial/06/06_hooking_2.png - :scale: 80 % - :align: center - -Due to the Microsoft x64 calling convention, the format is located in the ``rcx`` and the input message in the ``rdx`` register. - -Basically the :ref:`hooking-code` replaces the ``__acrt_iob_func`` function and shows a ``MessageBox`` with the ``rdx`` message. - -.. code-block:: nasm - :caption: hooking code - :name: hooking-code - - add rsp, 0x48 ; Stack unwind - xor rcx, rcx ; hWnd - mov rdx, rdx ; Message - mov r8, 0x0140009000 ; Title - xor r9, r9 ; MB_OK - mov rax, 0x014000A3E4 ; MessageBoxA address - call [rax] ; MessageBoxA(hWnd, Message, Title, MB_OK) - xor rcx, rcx ; exit value - mov rax, 0x014000A3d4 ; ExitProcess address - call [rax] ; ExitProcess(0) - ret ; Never reached - -.. note:: - - As for tutorial :ref:`02-pe-from-scratch`, the address of ``MessageBoxA`` and ``ExitProcess`` can be found - with the function: - - .. automethod:: lief.PE.Binary.predict_function_rva - :noindex: - - -First we create the ``.htext`` section which will hold the hooking code: - -.. code-block:: python - - section_text = lief.PE.Section(".htext") - section_text.content = code - section_text.virtual_address = 0x7000 - section_text.characteristics = lief.PE.SECTION_CHARACTERISTICS.CNT_CODE | lief.PE.SECTION_CHARACTERISTICS.MEM_READ | lief.PE.SECTION_CHARACTERISTICS.MEM_EXECUTE - - section_text = pe.add_section(section_text) - -Then the ``.hdata`` section for the ``MessageBox`` title: - -.. code-block:: python - - title = "LIEF is awesome\0" - data = list(map(ord, title)) - - section_data = lief.PE.Section(".hdata") - section_data.content = data - section_data.virtual_address = 0x8000 - section_data.characteristics = lief.PE.SECTION_CHARACTERISTICS.CNT_INITIALIZED_DATA | lief.PE.SECTION_CHARACTERISTICS.MEM_READ - - section_data = pe.add_section(section_data) - -As the ASLR is enabled we will disable it to avoid to deal with relocations: - -.. code-block:: python - - binary.optional_header.dll_characteristics &= ~lief.PE.DLL_CHARACTERISTICS.DYNAMIC_BASE - -We will also disable the ``NX`` protection: - - -.. code-block:: python - - binary.optional_header.dll_characteristics &= ~lief.PE.DLL_CHARACTERISTICS.NX_COMPAT - -As ``ExitProcess`` is not imported in ``KERNEL32.dll`` we need to add it: - -.. code-block:: python - - kernel32 = binary.get_import("KERNEL32.dll") - kernel32.add_entry("ExitProcess") - -The ``MessageBoxA`` function is located in the ``user32.dll`` thus we have to add it: - - -.. code-block:: python - - user32 = binary.add_library("user32.dll") - user32.add_entry("MessageBoxA") - -Then we proceed to the hook of the ``__acrt_iob_func`` function: - -.. code-block:: python - - pe.hook_function("__acrt_iob_func", binary.optional_header.imagebase + section_text.virtual_address) - -And finally we configure the :class:`~lief.PE.Builder` to create a new import table and to patch the original one with trampolines. - -.. code-block:: python - - - builder = lief.PE.Builder(binary) - - builder.build_imports(True).patch_imports(True) - - builder.build() - - builder.write("lief_pe_hooking.exe") - -Now we can run the final executable: - -.. code-block:: console - - $ lief_pe_hooking.exe "Hooking World" - - -.. figure:: ../_static/tutorial/06/06_hooking_3.png - :scale: 80 % - :align: center - - diff --git a/vendor/lief/doc/sphinx/tutorials/07_pe_resource.md b/vendor/lief/doc/sphinx/tutorials/07_pe_resource.md new file mode 100644 index 0000000..54281d0 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/07_pe_resource.md @@ -0,0 +1,207 @@ +# 07 - PE Resources + +This tutorial provides an overview of the resource structure in a PE file and +explains how to manipulate it using LIEF. + +______________________________________________________________________ + +Unlike the **ELF** and **Mach-O** formats, **PE** enables embedding *resources* +(icons, images, dialogs, etc.) within an executable or a DLL. + +These resources are usually located in the `.rsrc` section, but this is not +an absolute rule. + +To retrieve the section where resources are located, you can use the +{attr}`~lief.PE.DataDirectory.section` attribute of the associated +{class}`~lief.PE.DataDirectory`: + +{{ literalinclude("../../code/python/tuto_pe_resource.py", "resource-section") }} + +```console +.rsrc 22e0d8 23f000 22e200 236c00 0 4.3596 CNT_INITIALIZED_DATA - MEM_READ +``` + +## Resource Structure + +The underlying structure used to represent resources is a tree: + +:::{figure} ../_static/tutorial/07/07_resource_tree.png +:align: center +::: + +In the resource tree, there are basically two kinds of nodes: + +1. {class}`~lief.PE.ResourceDirectory`: Contains information about the subtree. +2. {class}`~lief.PE.ResourceData`: Used to store raw data. These nodes are the **leaves** of the tree. + +The first three levels of the tree have a special meaning: + +- Level 1: The {attr}`~lief.PE.ResourceDirectory.id` represents the {class}`~lief.PE.ResourcesManager.TYPE`. +- Level 2: The {attr}`~lief.PE.ResourceDirectory.id` represents an ID for accessing the resource. +- Level 3: The {attr}`~lief.PE.ResourceDirectory.id` represents the {class}`~lief.PE.RESOURCE_LANGS` / SUBLANG of the resource. + +You can check if a given binary embeds resources using the +{attr}`~lief.PE.Binary.has_resources` property. You can then access this +structure through the {attr}`~lief.PE.Binary.resources` property, which returns +a {class}`~lief.PE.ResourceDirectory` representing the **root** of the tree. + +Given a {class}`~lief.PE.ResourceDirectory`, the +{attr}`~lief.PE.ResourceDirectory.childs` property returns an **iterator** +(similar to a `list`) over the subtree associated with the node. + +The following snippet retrieves the {attr}`~lief.PE.ResourcesManager.TYPE.MANIFEST` +element and prints it: + +{{ literalinclude("../../code/python/tuto_pe_resource.py", "manifest-tree") }} + +```console +[DIRECTORY] - ID: 0x18 - Depth: 1 - Childs : 1 + Characteristics : 0 + Time/Date stamp : 0 + Major version : 0 + Minor version : 0 + Number of name entries : 0 + Number of id entries : 1 + +[DIRECTORY] - ID: 0x01 - Depth: 2 - Childs : 1 + Characteristics : 0 + Time/Date stamp : 0 + Major version : 0 + Minor version : 0 + Number of name entries : 0 + Number of id entries : 1 + +[DATA] - ID: 0x409 - Depth: 3 - Childs : 0 + Code page : 0 + Reserved : 0 + Size : 1666 + Hash : ffffffffb00b5419 + + + + + + +``` + +This tag has the following options: + +- **Level**: Indicates the security level the application is requesting. + + - `asInvoker`: Same permissions as the process that started it. + - `highestAvailable`: The application will run with the highest permission level possible. + - `requireAdministrator`: The application will run with administrator permissions. + +- **uiAccess** (Optional): Indicates whether the application requires access to protected user interface elements. + + - `true` + - `false` + +Using {class}`~lief.PE.ResourcesManager`, replacing the `asInvoker` value +with `requireAdministrator` is straightforward: + +{{ literalinclude("../../code/python/tuto_pe_resource.py", "set-admin") }} + +The PE {class}`~lief.PE.Builder` can be configured to rebuild the resource tree. +To apply the modifications, we must rebuild it: + +:::{warning} +By default, the {class}`~lief.PE.Builder` does not rebuild the resource tree. +::: + +```python +builder = lief.PE.Builder(filezilla) +builder.build_resources(True) +builder.build() +builder.write("filezilla_rsrc.exe") +``` + +:::{figure} ../_static/tutorial/07/filezilla.png +:align: center +:scale: 90 % +::: + +## Playing with Icons + +The {meth}`~lief.PE.ResourcesManager.change_icon` method switches icons between +two applications. + +As in the previous section, obtain the {class}`~lief.PE.ResourcesManager` as +follows: + +{{ literalinclude("../../code/python/tuto_pe_resource.py", "load-managers") }} + +Then, switch the first icons of the applications: + +{{ literalinclude("../../code/python/tuto_pe_resource.py", "change-icons") }} + +The MFC icons before switching: + +:::{figure} ../_static/tutorial/07/mfc.png +:align: center +:scale: 90 % +::: + +After the switch: + +:::{figure} ../_static/tutorial/07/mfc_modified.png +:align: center +:scale: 90 % +::: + +```{rubric} References +``` + +[^f1]: diff --git a/vendor/lief/doc/sphinx/tutorials/07_pe_resource.rst b/vendor/lief/doc/sphinx/tutorials/07_pe_resource.rst deleted file mode 100644 index a327c13..0000000 --- a/vendor/lief/doc/sphinx/tutorials/07_pe_resource.rst +++ /dev/null @@ -1,272 +0,0 @@ -07 - PE Resources ------------------ - -This tutorial gives an overview of the resource structure in a PE file and how they can be manipulated using LIEF - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ------- - -Unlike **ELF** and **Mach-O** formats, **PE** enables to embed *resources* (icons, images, raw, dialog ...) within an -executable or a DLL. - -These resources are usually located in the ``.rsrc`` section but this is not an absolute rule. - -To retrieve the section in which resources are located, one can use the :attr:`~lief.PE.DataDirectory.section` attribute of the associated :class:`~lief.PE.DataDirectory` - -.. code-block:: python - - binary = lief.parse("C:\\Windows\\explorer.exe") - if binary.has_resources: - rsrc_directory = binary.data_directory(lief.PE.DATA_DIRECTORY.RESOURCE_TABLE) - if rsrc_directory.has_section: - print(rsrc_directory.section) - -.. code-block:: console - - .rsrc 22e0d8 23f000 22e200 236c00 0 4.3596 CNT_INITIALIZED_DATA - MEM_READ - -Resource structure -****************** - -The underlying structure used to represent resources is a tree: - -.. figure:: ../_static/tutorial/07/07_resource_tree.png - :scale: 90 % - :align: center - -In the resource tree we basically have two kinds of node: - -#. :class:`~lief.PE.ResourceDirectory`: Contains some information about the subtree. -#. :class:`~lief.PE.ResourceData`: Used to store raw data. These nodes are the **leaf** of the tree - -The first 3 levels of the tree have a special meaning: - -* Level 1: The :attr:`~lief.PE.ResourceDirectory.id` represents the :class:`~lief.PE.RESOURCE_TYPES` -* Level 2: The :attr:`~lief.PE.ResourceDirectory.id` represents an ID to access to the resource -* Level 3: The :attr:`~lief.PE.ResourceDirectory.id` represents the :class:`~lief.PE.RESOURCE_LANGS` / :class:`~lief.PE.RESOURCE_SUBLANGS` of the resource. - - -We can check that a given binary embed resources with the :attr:`~lief.PE.Binary.has_resources` property, then we can access to this structure -through the :attr:`~lief.PE.Binary.resources` property which returns a :class:`~lief.PE.ResourceDirectory` representing the **root** of the tree. - -Given a :class:`~lief.PE.ResourceDirectory`, the :attr:`~lief.PE.ResourceDirectory.childs` property returns an **iterator** (quiet similar to a ``list``) over the sub tree associated with the node. - -The following snippet retrieves the :attr:`~lief.PE.RESOURCE_TYPES.MANIFEST` element and print it. - -.. code-block:: python - - filezilla = lief.parse("filezilla.exe") - - if not filezilla.has_resources: - print("'{}' has no resources. Abort!".format(filezilla.name), file=sys.stderr) - sys.exit(1) - - root = filezilla.resources - - # First level => Type ((ResourceDirectory node) - manifest_node = next(iter(filter(lambda e : e.id == lief.PE.RESOURCE_TYPES.MANIFEST, root.childs))) - print(manifest_node) - - # Second level => ID (ResourceDirectory node) - id_node = manifest_node.childs[0] - print(id_node) - - # Third level => Lang (ResourceData node) - lang_node = id_node.childs[0] - print(lang_node) - - manifest = bytes(lang_node.content).decode("utf8") - - print(manifest) - -.. code-block:: console - - [DIRECTORY] - ID: 0x18 - Depth: 1 - Childs : 1 - Characteristics : 0 - Time/Date stamp : 0 - Major version : 0 - Minor version : 0 - Number of name entries : 0 - Number of id entries : 1 - - [DIRECTORY] - ID: 0x01 - Depth: 2 - Childs : 1 - Characteristics : 0 - Time/Date stamp : 0 - Major version : 0 - Minor version : 0 - Number of name entries : 0 - Number of id entries : 1 - - [DATA] - ID: 0x409 - Depth: 3 - Childs : 0 - Code page : 0 - Reserved : 0 - Size : 1666 - Hash : ffffffffb00b5419 - - - - `_ - -Among these tags, the ``requestedExecutionLevel`` tag *"describes the minimum security permissions required for the application to run on the client computer."* [#f1]_ - -.. code-block:: xml - - - - - -This tag has the following options: - -* **Level**: Indicates the security level the application is requesting - - * ``asInvoker``: Same permission as the process that started it - * ``highestAvailable``: The application will run with the highest permission level that it can - * ``requireAdministrator``: The application will run with administrator permissions - -* **uiAccess** (Optional): Indicates whether the application requires access to protected user interface elements - - * ``true`` - * ``false`` - -Thanks to the :class:`~lief.PE.ResourcesManager` replacing the ``asInvoker`` value to ``requireAdministrator`` is as simple as: - -.. code-block:: python - - filezilla = lief.parse("filezilla.exe") - - resources_manager = filezilla.resources_manager - - if not resources_manager.has_manifest: - print("'{}' has no manifest. Abort!".format(filezilla.name), file=sys.stderr) - sys.exit(1) - - manifest = resources_manager.manifest - manifest = manifest.replace("asInvoker", "requireAdministrator") - resources_manager.manifest = manifest - -The PE :class:`~lief.PE.Builder` can be configured to rebuild or not the resource tree. To take account of modifications we need to rebuild it: - -.. warning:: - - By default the :class:`~lief.PE.Builder` doesn't rebuild the resource tree. - -.. code-block:: python - - builder = lief.PE.Builder(filezilla) - builder.build_resources(True) - builder.build() - builder.write("filezilla_rsrc.exe") - - -.. figure:: ../_static/tutorial/07/filezilla.png - :scale: 90 % - :align: center - - - -Play with Icons -*************** - -The :meth:`~lief.PE.ResourcesManager.change_icon` method switch icons from two applications. - -In the same way as the previous part, we get the :class:`~lief.PE.ResourcesManager` as follow: - -.. code-block:: python - - mfc = lief.parse("mfc.exe") - cmd = lief.parse("cmd.exe") - - mfc_rsrc_manager = mfc.resources_manager - cmd_rsrc_manager = cmd.resources_manager - -Then we can switch the first icons of the applications: - -.. code-block:: python - - mfc_icons = mfc_rsrc_manager.icons - cmd_icons = cmd_rsrc_manager.icons - for i in range(min(len(mfc_icons), len(cmd_icons))): - mfc_rsrc_manager.change_icon(mfc_icons[i], cmd_icons[i]) - - -The MFC icons before switching: - -.. figure:: ../_static/tutorial/07/mfc.png - :scale: 90 % - :align: center - - -After the switch: - -.. figure:: ../_static/tutorial/07/mfc_modified.png - :scale: 90 % - :align: center - - - -.. rubric:: References - -.. [#f1] https://docs.microsoft.com/en-us/previous-versions/visualstudio/visual-studio-2015/deployment/trustinfo-element-clickonce-application - diff --git a/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.md b/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.md new file mode 100644 index 0000000..c7ede2d --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.md @@ -0,0 +1,271 @@ +(tuto_elf_bin2lib)= + +# 08 - Transforming an ELF executable into a library + +In this tutorial, we will see how to convert a **PIE** executable into a library. + +______________________________________________________________________ + +## Introduction + +Examining the header of an ELF PIE executable reveals that it has the same type +as a shared object (i.e., a library): + +```console +$ readelf -h /usr/bin/ssh|grep Type +Type: DYN (Shared object file) + +$ readelf -h /usr/lib/libm.so|grep Type +Type: DYN (Shared object file) +``` + +Using LIEF, we can access this information through the +{attr}`~lief.ELF.Header.file_type` attribute: + +```python +>>> libm = lief.parse("/usr/lib/libm.so.6") +>>> print(libm.header.file_type) +FILE_TYPE.DYN + +>>> ssh = lief.parse("/usr/bin/ssh") +>>> print(ssh.header.file_type) +FILE_TYPE.DYN +``` + +The main difference between PIE binaries and shared libraries is how symbols +are exported. + +A shared library is designed to expose functions so that executables can bind +to it, whereas executables should not expose functions [^footnote-1]. + +This is confirmed by the number of exported functions in the two different +objects: + +```python +>>> print(len(libm.exported_functions)) +572 +>>> print(len(ssh.exported_functions)) +10 +``` + +In this tutorial, we will see how to transform raw function addresses into +exported functions associated with a symbol, thus exposing internal functions +of the executable. + +## Exporting functions + +Such a transformation can be useful if we find a function at a given address +and want to instrument it (using `dlopen`/`dlsym`, for example). Once the +target function is exported, we can link it as we would for a *normal* library. + +For example, in a fuzzing scenario, if one identifies a parser function, we can +export it and then feed its inputs using AFL. This allows us to bypass the +normal entry point to reach the function directly. + +Let's see how it works on a basic *crackme*: + +```cpp +#include +#include +#include + +#define NOINLINE __attribute__ ((noinline)) + +NOINLINE int check_found(char* input) { + if (strcmp(input, "easy") == 0) { + return 1; + } + return 0; +} + +int main(int argc, char** argv) { + + if (argc != 2) { + printf("Usage: %s flag\n", argv[0]); + return -1; + } + + if (check_found(argv[1])) { + printf("Well done!\n"); + } else { + printf("Wrong!\n"); + } + return 0; +} +``` + +This code takes a string as input and calls the `check_found` function on this +string. It returns `1` if the input is `easy`, and `0` otherwise. + +The `__attribute__ ((noinline))` is used to ensure the `check_found` +function is not inlined by the compiler. If the function is inlined, there +will be no address associated with it. + +The following figure summarizes the execution flow: + +:::{figure} ../_static/tutorial/08/bin2lib_a.png +:align: center +::: + +The *crackme* can be compiled with: + +```console +$ gcc crackme101.c -O0 -fPIE -pie -Wl,-strip-all,--hash-style=sysv -o crackme101.bin -fvisibility=hidden +$ ./crackme101.bin foo +Wrong! +$ ./crackme101.bin easy +Well done! +``` + +Note the use of the `-fvisibility=hidden` flag. It prevents the compiler from +automatically exporting functions, such as `check_found`. Opening +`crackme101.bin` with LIEF confirms that no functions are exported: + +```python +>>> import lief +>>> crackme101 = lief.parse("./crackme101.bin") +>>> print(len(crackme101.exported_functions)) +0 +``` + +Using a disassembler, we can quickly identify the address of the check function: + +:::{figure} ../_static/tutorial/08/crackme101_ida.png +:align: center +::: + +In this case, the **check** function is located at address: `0x72A` [^footnote-2]. + +Now that we have identified the address, we can export it as a named function: +`check_found`. + +{{ literalinclude("../../code/python/tuto_elf_bin2lib.py", "export") }} + +And that's all! + +`libcrackme101.so` is now a **library** that exports one function: +`check_found`. + +```python +>>> import lief +>>> libcrackme101 = lief.parse("./libcrackme101.so") +>>> print(len(libcrackme101.exported_functions)) +1 +>>> print(libcrackme101.exported_functions[0]) +check_found +``` + +Notably, `libcrackme101.so` remains an executable: + +```console +$ ./libcrackme101.so foo +Wrong! +$ ./libcrackme101.so easy +Well done! +``` + +Since we have exported a function, we can now use `dlopen` on +`libcrackme101.so` and `dlsym` on `check_found`: + +```{code-block} cpp +:emphasize-lines: 9,14 + +#include +#include +#include + +typedef int(*check_t)(char*); + +int main (int argc, char** argv) { + + void* handler = dlopen("./libcrackme101.so", RTLD_LAZY); + if (!handler) { + fprintf(stderr, "dlopen error: %s\n", dlerror()); + return 1; + } + check_t check_found = (check_t)dlsym(handler, "check_found"); + + int output = check_found(argv[1]); + + printf("Output of check_found('%s'): %d\n", argv[1], output); + + return 0; +} +``` + +Running the code above should yield a similar output: + +```console +$ gcc instrument.c -O0 -fPIE -pie -o instrument.bin -ldl +$ ./instrument.bin test +Output of check_found('test'): 0 +$ ./instrument.bin easy +Output of check_found('easy'): 1 +``` + +If `dlopen` returns an error, please read [the following section about glibc >= 2.29](#glibc229). + +The transformation of the execution flow can be represented as follows: + +:::{figure} ../_static/tutorial/08/bin2lib_b.png +:align: center +::: + +(glibc229)= + +## Warning for glibc >= 2.29 users + +If you are using `glibc >= 2.29` (or a similar version depending on your +Linux distribution), you might have encountered this error while using the +{title-reference}`dlopen` function: + +```{code} +dlopen error: cannot dynamically load position-independent executable +``` + +Loading PIE binaries as shared libraries was not really an intended use case +for `dlopen`, and it used to work without being properly supported. One +reason is that it [does not seem trivial to support](https://sourceware.org/bugzilla/show_bug.cgi?id=11754) all possible use +cases (issues with certain relocations and ELF constructors). + +These glibc versions now [implement a check](https://patchwork.ozlabs.org/project/glibc/patch/20190312130235.8E82C89CE49C@oldenburg2.str.redhat.com/) +to deny `dlopen` calls with PIE binaries. This is done by verifying that the +`DF_1_PIE` flag is not present in the dynamic information flags. + +To circumvent this check, LIEF can be used to remove the `DF_1_PIE` flag: + +{{ literalinclude("../../code/python/tuto_elf_bin2lib.py", "remove-pie", prepend="import lief", emphasize_lines="5") }} + +## Conclusion + +Because PIE executables are designed to be mapped at a random base address, +they generally behave like a library. We only need to export the relevant +functions. + +For non-PIE executables, such a transformation would be very difficult because +it requires first transforming the executable into a *relocatable* executable. +This involves creating relocations, patching absolute jumps, etc. + +LIEF currently only supports this transformation for ELF, and we need to +investigate the PE and Mach-O cases [^footnote-3]. + +```{rubric} Notes +``` + +[^footnote-1]: Some functions can be exported by the linker, such as `_init`. + +[^footnote-2]: The mapped virtual address will be `BASE + 0x72A`, where `BASE` is randomly chosen by ASLR. + +[^footnote-3]: In macOS, all executables are compiled with the PIE flag. + +```{eval-rst} + +:API: + + * :meth:`lief.ELF.Binary.add_exported_function` + * :meth:`lief.ELF.Binary.export_symbol` + + * :attr:`lief.ELF.Symbol.visibility` + * :attr:`lief.ELF.Symbol.name` + * :attr:`lief.ELF.Symbol.value` +``` diff --git a/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.rst b/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.rst deleted file mode 100644 index ee0f639..0000000 --- a/vendor/lief/doc/sphinx/tutorials/08_elf_bin2lib.rst +++ /dev/null @@ -1,278 +0,0 @@ -08 - Transforming an ELF executable into a library --------------------------------------------------- - -In this tutorial, we will see how to convert a **PIE** executable into a library - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ , updated by Adrien Guinet - `@adriengnt `_ - ------- - -Introduction -~~~~~~~~~~~~ - -Actually, if we look at the header of a ELF PIE executable one can notice that it has the same type as a shared object (i.e. library) - -.. code-block:: console - - $ readelf -h /usr/bin/ssh|grep Type - Type: DYN (Shared object file) - - $ readelf -h /usr/lib/libm.so|grep Type - Type: DYN (Shared object file) - -Using LIEF we can access this information through the :attr:`~lief.ELF.Header.file_type` attribute - -.. code-block:: python - - >>> libm = lief.parse("/usr/lib/libm.so.6") - >>> print(libm.header.file_type) - E_TYPE.DYNAMIC - - >>> ssh = lief.parse("/usr/bin/ssh") - >>> print(ss.header.file_type) - E_TYPE.DYNAMIC - -The main difference between a PIE binaries and a shared libraries is how symbols are exported. - -A shared library aims to expose functions so that executable can bind to it whereas executables shouldn't not expose functions [1]_ - -It's confirmed with the number of exported functions in the two different objects: - -.. code-block:: python - - >>> print(len(libm.exported_functions)) - 572 - >>> print(len(ssh.exported_functions)) - 10 - -In this tutorial we will see how we can transform raw function addresses into exported functions associated with a symbol, -thus thus exposing internal functions of the executable. - -Exporting functions -~~~~~~~~~~~~~~~~~~~ - -Such transformation can be useful if we found a function at a given address and want to instrument it (using ``dlopen``/``dlsym`` for example). -Once the target function is exported we can link it as we would do for a *normal* library. - -For example in a fuzzing scenario if one identifies a function that is a parser, we can export it and then we can feed its inputs with AFL. Thus we cut the path from the normal entrypoint to reach the function. - -Let's see how it works on a basic *crackme*: - -.. code-block:: cpp - - #include - #include - #include - - #define NOINLINE __attribute__ ((noinline)) - - NOINLINE int check_found(char* input) { - if (strcmp(input, "easy") == 0) { - return 1; - } - return 0; - } - - int main(int argc, char** argv) { - - if (argc != 2) { - printf("Usage: %s flag\n", argv[0]); - exit(-1); - } - - if (check_found(argv[1])) { - printf("Well done!\n"); - } else { - printf("Wrong!\n"); - } - return 0; - } - - -This code takes a string as input and call the ``check_found`` function on this -string, then it returns ``1`` if the input is ``easy``. ``0`` otherwise. - -The ``__attribute__ ((noinline))`` is used to make sure the ``check_found`` -function won't be inlined by the compiler. Indeed, if the function check is -inlined, there won't be an address associated to this function. - -This figure sump-up the execution flow: - -.. figure:: ../_static/tutorial/08/bin2lib_a.png - :scale: 25% - :align: center - -The *crackme* can be compiled with: - -.. code-block:: console - - $ gcc crackme101.c -O0 -fPIE -pie -Wl,-strip-all,--hash-style=sysv -o crackme101.bin -fvisibility=hidden - $ ./crackme101.bin foo - Wrong! - $ ./crackme101.bin easy - Well done! - -Note the usage of the ``-fvisibility=hidden`` flag. It makes the compiler not -automatically export functions, like the ``check_found`` one. By opening -``crackme101.bin`` with LIEF, we can check that no functions are exported: - -.. code-block:: python - - >>> import lief - >>> crackme101 = lief.parse("./crackme101.bin") - >>> print(len(crackme101.exported_functions)) - 0 - -Using a disassembler we can quickly identify the check function address: - -.. figure:: ../_static/tutorial/08/crackme101_ida.png - :scale: 100% - :align: center - -In this case, the **check** function is located at the address: ``0x72A`` [2]_ - -Now that we identified the address we can export it as a named function: ``check_found`` - -.. code-block:: python - - >>> crackme101.add_exported_function(0x72A, "check_found") - >>> crackme101.write("libcrackme101.so") - -And that all! - -``libcrackme101.so`` is now a **library** that export one function: ``check_found``. - -.. code-block:: python - - >>> import lief - >>> libcrackme101 = lief.parse("./libcrackme101.so") - >>> print(len(crackme101.exported_functions)) - 1 - >>> print(crackme101.exported_functions[0]) - check_found - -It turns out that ``libcrackme101.so`` is still an executable: - -.. code-block:: console - - $ ./libcrackme101.so foo - Wrong! - $ ./libcrackme101.so easy - Well done! - -Since we have exported a function we can now use ``dlopen`` on ``libcrackme101.so`` and -``dlsym`` on ``check_found`` - -.. code-block:: cpp - :emphasize-lines: 9,14 - - #include - #include - #include - - typedef int(*check_t)(char*); - - int main (int argc, char** argv) { - - void* handler = dlopen("./libcrackme101.so", RTLD_LAZY); - if (!handler) { - fprintf(stderr, "dlopen error: %s\n", dlerror()); - return 1; - } - check_t check_found = (check_t)dlsym(handler, "check_found"); - - int output = check_found(argv[1]); - - printf("Output of check_found('%s'): %d\n", argv[1], output); - - return 0; - } - -Running the code above should give a similar output: - -.. code-block:: console - - $ gcc instrument.c -O0 -fPIE -pie -o instrument.bin -ldl - $ ./instrument.bin test - Output of check('test'): 0 - $ ./instrument.bin easy - Output of check('easy'): 1 - -If ``dlopen`` returns an error, please read `the following section about glibc >= 2.29 <#glibc229>`_. - -The transformation of the execution flow can be represented as follow: - -.. figure:: ../_static/tutorial/08/bin2lib_b.png - :scale: 25% - :align: center - -.. _glic229: - -Warning for glibc >= 2.29 users -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -If you are using ``glibc >= 2.29`` (or a close version depending on your Linux -distribution), you might have encountered this error while using the `dlopen` -function: - -.. code:: - - dlopen error: cannot dynamically load position-independent executable - -Loading PIE binaries as shared libraries wasn't indeed really an intended use -case for ``dlopen``, and it used to work without really being properly -supported. One of the reasons is that it `does not seem that trivial to -support `_ all the -possible use cases (issues with some relocations and ELF constructors). - -These glibc versions now `implements a check -`_ -to deny calls to ``dlopen`` with PIE binaries. This is done by verifying the -``DF_1_PIE`` flag isn't present in the list of dynamic information flags. - - -In order to circumvent this test, LIEF can be used to remove this ``DF_1_PIE`` flag: - -.. code-block:: python - :emphasize-lines: 5 - - import lief - import sys - path = sys.argv[1] - bin_ = lief.parse(path) - bin_[lief.ELF.DYNAMIC_TAGS.FLAGS_1].remove(lief.ELF.DYNAMIC_FLAGS_1.PIE) - bin_.write(path + ".patched") - - -Conclusion -~~~~~~~~~~ - -Because PIE executables aim to be mapped at a random base address, they globally behave as a library. We only need to export the *interesting* functions. - -For non-PIE executables such transformation would be very difficult because it requires to transform first -the executable into a *relocatable* executable. It means creating relocations, patching absolute *jump*, ... - -LIEF only support this transformation for ELF and we need to investigate the PE and Mach-O cases [3]_. - - -.. rubric:: Notes - -.. [1] Some functions can be exported by the linker such as ``_init`` -.. [2] The mapped virtual address will be ``BASE + 0x72A`` where ``BASE`` is randomly choosed by the ASLR -.. [3] In OSX all executables are compiled with the PIE flag. - - -:API: - - * :meth:`lief.ELF.Binary.add_exported_function` - * :meth:`lief.ELF.Binary.export_symbol` - - * :attr:`lief.ELF.Symbol.visibility` - * :attr:`lief.ELF.Symbol.name` - * :attr:`lief.ELF.Symbol.value` - - - diff --git a/vendor/lief/doc/sphinx/tutorials/09_frida_lief.md b/vendor/lief/doc/sphinx/tutorials/09_frida_lief.md new file mode 100644 index 0000000..ea49380 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/09_frida_lief.md @@ -0,0 +1,302 @@ +# 09 - How to use Frida on a non-rooted device + +In this tutorial, we will see how to use the Frida gadget on a non-rooted device. + +______________________________________________________________________ + +In recent years, Frida has become the standard tool for performing hooking. It +supports various platforms and enables writing hooks quickly and dynamically. + +Most of the time, there are no constraints on using Frida on a rooted device, +but in some scenarios, the application being analyzed might check its +environment. + +A technique based on modifying the Dalvik bytecode has been well-described by +[@ikoz](https://twitter.com/ikoz) in the post "[Using Frida on Android without root](https://koz.io/using-frida-on-android-without-root/)". In this tutorial, +we propose a new technique that does not require modifying the Dalvik +bytecode (i.e., `classes.dex`). + +## Frida Gadget + +In its default mode, Frida first needs to inject an *agent* into the targeted +application so that it resides in the process's memory space. + +On Android and Linux, this injection is typically performed with `ptrace` by +attaching to or spawning a process and then injecting the agent. Once the agent +is injected, it communicates with its server through a pipe. + +Some types of injection require privileges. For example, a *normal* user +cannot use `ptrace`. To address this constraint, Frida provides another mode +of operation called "embedded". In this mode, the user is responsible for +injecting the *frida-gadget* library. + +Such injection can be performed using: + +- Environment variables: `LD_PRELOAD`, `DYLD_INSERT_LIBRARIES`, etc. + +- Using `dlopen`. + +- In an open-source target, using the linker to link with the Frida gadget. + +- ... + +For more information about the Frida gadget, refer to the documentation: +[frida-gadget](https://frida.re/docs/gadget/) + +## Frida & LIEF + +One less-known but established injection technique is based on modifying the +ELF format. This was well-explained by Mayhem in +[Phrack](http://phrack.org/issues/61/8.html) [^footnote-1], and LIEF provides a +user-friendly API [^footnote-2] to perform it. + +To summarize, executable formats include libraries that are linked with the +executable. We can obtain a list of linked libraries using `ldd` or +`readelf` (Unix) or with [elf_reader.py](https://github.com/lief-project/LIEF/blob/main/api/python/examples/elf_reader.py) (Linux, Windows, OSX): + +```console +$ python ./elf_reader.py -d /bin/ls + +== Dynamic entries == + +|Tag | Value | Info | +|NEEDED | 0x1 | libcap.so.2 | +|NEEDED | 0x80 | libc.so.6 | +``` + +Here, `/bin/ls` has two dependencies: + +- `libcap.so.2` +- `libc.so.6` + +During the loading phase of the executable, the loader iterates over these +libraries and maps them into the process's memory space. Once mapped, it calls +their constructors [^footnote-3]. + +The idea is to add `frida-agent.so` as a dependency of native libraries +embedded in the APK. + +Adding such a dependency is as simple as: + +{{ literalinclude("../../code/python/tuto_frida.py", "inject", prepend="import lief") }} + +## Telegram + +To illustrate the process, we will inject the Frida gadget into the Telegram +application. It is an interesting target because: + +- It contains only one native library, so the library will be loaded early. +- It demonstrates LIEF's reliability in modifying ELF files. +- It is a real-world application. + +Regarding the environment, we will use Telegram version `4.8.4-12207` +(February 18, 2018) on an Android 6.0.1 device with an AArch64 architecture +(Samsung Galaxy S6). + +### Injection with LIEF + +As explained above, the injection is simply a call to +{meth}`lief.ELF.Binary.add_library` on the `libtmessages.28.so` library. + +Prior to injection, `libtmessages.28.so` is linked against the following +libraries: + +```bash +$ readelf -d ./libtmessages.28.so|grep NEEDED + 0x0000000000000001 (NEEDED) Shared library: [libjnigraphics.so] + 0x0000000000000001 (NEEDED) Shared library: [liblog.so] + 0x0000000000000001 (NEEDED) Shared library: [libz.so] + 0x0000000000000001 (NEEDED) Shared library: [libOpenSLES.so] + 0x0000000000000001 (NEEDED) Shared library: [libEGL.so] + 0x0000000000000001 (NEEDED) Shared library: [libGLESv2.so] + 0x0000000000000001 (NEEDED) Shared library: [libdl.so] + 0x0000000000000001 (NEEDED) Shared library: [libstdc++.so] + 0x0000000000000001 (NEEDED) Shared library: [libm.so] + 0x0000000000000001 (NEEDED) Shared library: [libc.so] +``` + +After `telegram.add_library("libgadget.so")`, the new dependency is at the +first position: + +```bash +$ readelf -d ./libtmessages.28.so|grep NEEDED + 0x0000000000000001 (NEEDED) Shared library: [libgadget.so] + 0x0000000000000001 (NEEDED) Shared library: [libjnigraphics.so] + 0x0000000000000001 (NEEDED) Shared library: [liblog.so] + 0x0000000000000001 (NEEDED) Shared library: [libz.so] + 0x0000000000000001 (NEEDED) Shared library: [libOpenSLES.so] + 0x0000000000000001 (NEEDED) Shared library: [libEGL.so] + 0x0000000000000001 (NEEDED) Shared library: [libGLESv2.so] + 0x0000000000000001 (NEEDED) Shared library: [libdl.so] + 0x0000000000000001 (NEEDED) Shared library: [libstdc++.so] + 0x0000000000000001 (NEEDED) Shared library: [libm.so] + 0x0000000000000001 (NEEDED) Shared library: [libc.so] +``` + +### Configuring the Frida Gadget + +According to the documentation, the Frida gadget allows the use of a +configuration file to parameterize interaction: + +- **Listing**: Interaction is the same as frida-server. +- **Script**: Direct interaction with a JS script at a specified path. +- **ScriptDirectory**: Same as *Script*, but for multiple applications and scripts. + +The *Listing* interaction would require the `android.permission.INTERNET` +permission. While we could add this permission by modifying the manifest, +we will use the *Script* interaction instead, as it does not require additional +permissions. + +The Frida payload will be located in the `/data/local/tmp/myscript.js` file. +The gadget configuration for this context is provided below: + +```json +{ + "interaction": { + "type": "script", + "path": "/data/local/tmp/myscript.js", + "on_change": "reload" + } +} +``` + +Using a configuration file must follow two requirements: + +1. The file must have the same name as the gadget library (e.g., `libgadget.so` and `libgadget.conf`). +2. The configuration file must be located in the **same** directory as the gadget library. + +The second requirement means that after installation on the device, the gadget +library will look for the configuration file in the +`/data/app/org.telegram.messenger-1/lib` directory. + +When installing an application, the Android package manager copies files from +the `lib/` directory of the APK only if [^footnote-4]: + +- They start with the prefix `lib`. +- They end with the suffix `.so`. +- It is `gdbserver`. + +Frida is aware of these requirements, as illustrated in the listing below. +Hence, we can simply add the `.so` suffix to `libgadget.conf`: + +```cpp +#if ANDROID + if (!FileUtils.test (config_path, FileTest.EXISTS)) { + var ext_index = config_path.last_index_of_char ('.'); + if (ext_index != -1) { + config_path = config_path[0:ext_index] + ".config.so"; + } else { + config_path = config_path + ".config.so"; + } + } +#endif +``` + +

    lib/gadget/gadget.vala

    + +Finally, the `lib` directory of the new Telegram `.apk` has the following +structure: + +```bash +$ tree lib +. +└── arm64-v8a + ├── libgadget.config.so + ├── libgadget.so + └── libtmessages.28.so +``` + +With `libtmessages.28.so` linked against `libgadget.so`: + +```bash +$ readelf -d ./arm64-v8a/libtmessages.28.so + 0x0000000000000001 (NEEDED) Shared library: [libgadget.so] + ... +``` + +### Run + +Once: + +1. The injection is performed in `libtmessages.28.so`. +2. The gadget library and its configuration are placed in the `/lib/ABI` directory. +3. The application is resigned. + +We can install the repackaged APK (`new.apk`) and push `myscript.js` to +`/data/local/tmp`: + +```console +$ adb shell install new.apk +$ adb push myscript.js /data/local/tmp +$ adb shell chmod 777 /data/local/tmp/myscript.js +``` + +The Frida script `myscript.js` used in this tutorial simply calls the Android +log function: + +```javascript +'use strict'; + +console.log("Waiting for Java.."); + +Java.perform(function () { + var Log = Java.use("android.util.Log"); + Log.v("frida-lief", "Have fun!"); +}); +``` + +

    myscript.js

    + +Lastly, we can run the Telegram application and observe the Android logs: + +:::{figure} ../_static/tutorial/09/telegram.png +:align: center +:scale: 25% +::: + +```console +$ adb logcat -s "frida-lief:V" +--------- beginning of system +--------- beginning of main +03-24 17:23:51.908 10243 10243 V frida-lief: Have fun! +``` + +## Conclusion + +This tutorial demonstrated how static format instrumentation and dynamic +instrumentation can be combined. + +Here is a quick summary of the advantages and disadvantages of this technique: + +```{eval-rst} + +:Advantages: + + * Does not require a rooted device. + * Does not depend on frida-server. + * Can be used to bypass some anti-Frida protections. + * Does not modify ``AndroidManifest.xml`` or DEX files. + +:Disadvantages: + + * Requires adding files to the APK. + * Requires the application to have at least one native library. + * Relies on the library being loaded early in the application execution. +``` + +```{rubric} Notes +``` + +[^footnote-1]: Note that LIEF **does not** modify the {attr}`~lief.ELF.DynamicEntry.TAG.DEBUG` entry ... + +[^footnote-2]: Modifying the ELF Dynamic section is not as simple as the API might suggest. + +[^footnote-3]: In the ELF format, these are located in the {attr}`~lief.ELF.DynamicEntry.TAG.INIT_ARRAY` or {attr}`~lief.ELF.DynamicEntry.TAG.INIT` entries. + +[^footnote-4]: For those interested, checks are performed in the `framework_base/core/jni/com_android_internal_content_NativeLibraryHelper.cpp` file. + Notably, these checks on the prefix and suffix are only performed if the application is not *debuggable*. + +```{rubric} API +``` + +- {meth}`lief.ELF.Binary.add_library` diff --git a/vendor/lief/doc/sphinx/tutorials/09_frida_lief.rst b/vendor/lief/doc/sphinx/tutorials/09_frida_lief.rst deleted file mode 100644 index b0f0b71..0000000 --- a/vendor/lief/doc/sphinx/tutorials/09_frida_lief.rst +++ /dev/null @@ -1,302 +0,0 @@ -09 - How to use frida on a non-rooted device --------------------------------------------- - -In this tutorial we will see how to use Frida gadget on a non-rooted device. - -Scripts and materials are available here: `materials `_ - - -By Romain Thomas - `@rh0main `_ - ------- - -From the last few years, Frida became the tool of the trade to perform hooking. It supports various platforms and -enables to write hooks quickly and dynamically. - -Most of the time there are no constraints to use Frida on a rooted device but in some scenario the application to analyze could -check its environment. - -A technique based on modifying the Dalvik bytecode has been well described by `@ikoz `_ in the post "`Using Frida on Android without root `_". In this tutorial we propose a new technique without modifying the Dalvik Bytecode (i.e. ``classes.dex``). - -Frida Gadget -~~~~~~~~~~~~ - -In the default mode, Frida needs in a first step to inject an *agent* in the targeted application so that it is in the memory space of the process. - -On Android and Linux such injection is done with ``ptrace`` by attaching or spawning a process and then injecting the agent. -Once the agent is injected, it communicates with its server through a pipe. - -Some kind of injection require privileges. For example, we can't use ``ptrace`` as a *normal* user. To address this constraint, Frida provides another -mode of operation called "embedded". In this mode the user is responsible to inject the *frida-gadget* library. - -Such injection could be done with: - -* Environment variables: ``LD_PRELOAD``, ``DYLD_INSERT_LIBRARIES`` ... -* Using ``dlopen`` -* In an open-source target, use the linker to link with frida-gadget. -* ... - -For more information about Frida gadget, here is the documentation: `frida-gadget `_ - -Frida & LIEF -~~~~~~~~~~~~ - -One less known injection technique but quite old is based on modifying the ELF format. It has been well explained by Mayhem in `Phrack `_ [1]_ and LIEF provides a user-friendly API [2]_ to do it. - -To summarize, executable formats include libraries that are linked with executable. We can have list of linked libraries with -``ldd`` or ``readelf`` (Unix) or with `elf_reader.py `_ (Linux, Windows, OSX): - -.. code-block:: console - - $ python ./elf_reader.py -d /bin/ls - - == Dynamic entries == - - |Tag | Value | Info | - |NEEDED | 0x1 | libcap.so.2 | - |NEEDED | 0x80 | libc.so.6 | - -Here ``/bin/ls`` has two dependencies: - -* ``libcap.so.2`` -* ``libc.so.6`` - -In the loading phase of the executable, the loader iterates over these libraries and map them in the memory space of the process. Once mapped it calls its constructor [3]_. - -The idea is to add ``frida-agent.so`` as a dependency of native libraries embedded in the APK. - -Adding such dependencies is as simple as: - -.. code-block:: python - - import lief - - libnative = lief.parse("libnative.so") - libnative.add_library("libgadget.so") # Injection! - libnative.write("libnative.so") - -Telegram -~~~~~~~~ - -To explain the process, we will inject frida gadget in the Telegram application. It's an interesting target because: - -* It contains only one native library so the library should be loaded early. -* It shows the reliability of LIEF to modify ELF files -* It's a real app - - -Regarding the environment, we will use the version ``4.8.4-12207`` of Telegram (February 18, 2018) on an Android 6.0.1 device with an AArch64 architecture (Samsung Galaxy S6) - -Injection with LIEF -################### - -As explained above, the injection is just a call to the :meth:`lief.ELF.Binary.add_library` on the ``libtmessages.28.so`` library. - -Prior to the injection ``libtmessages.28.so`` is linked against the following libraries - -.. code-block:: bash - - $ readelf -d ./libtmessages.28.so|grep NEEDED - 0x0000000000000001 (NEEDED) Shared library: [libjnigraphics.so] - 0x0000000000000001 (NEEDED) Shared library: [liblog.so] - 0x0000000000000001 (NEEDED) Shared library: [libz.so] - 0x0000000000000001 (NEEDED) Shared library: [libOpenSLES.so] - 0x0000000000000001 (NEEDED) Shared library: [libEGL.so] - 0x0000000000000001 (NEEDED) Shared library: [libGLESv2.so] - 0x0000000000000001 (NEEDED) Shared library: [libdl.so] - 0x0000000000000001 (NEEDED) Shared library: [libstdc++.so] - 0x0000000000000001 (NEEDED) Shared library: [libm.so] - 0x0000000000000001 (NEEDED) Shared library: [libc.so] - -After ``telegram.add_library("libgadget.so")`` we have the new dependency at the first position: - -.. code-block:: bash - - $ readelf -d ./libtmessages.28.so|grep NEEDED - 0x0000000000000001 (NEEDED) Shared library: [libgadget.so] - 0x0000000000000001 (NEEDED) Shared library: [libjnigraphics.so] - 0x0000000000000001 (NEEDED) Shared library: [liblog.so] - 0x0000000000000001 (NEEDED) Shared library: [libz.so] - 0x0000000000000001 (NEEDED) Shared library: [libOpenSLES.so] - 0x0000000000000001 (NEEDED) Shared library: [libEGL.so] - 0x0000000000000001 (NEEDED) Shared library: [libGLESv2.so] - 0x0000000000000001 (NEEDED) Shared library: [libdl.so] - 0x0000000000000001 (NEEDED) Shared library: [libstdc++.so] - 0x0000000000000001 (NEEDED) Shared library: [libm.so] - 0x0000000000000001 (NEEDED) Shared library: [libc.so] - - - -Configuration of Frida Gadget -############################# - -From the documentation, Frida gadget enables to use a configuration file to parametrize the interaction: - -* **Listing**: Interaction is the same as frida-server -* **Script**: Direct interaction with a JS script for which the path is specified in the configuration -* **ScriptDirectory**: Same as *Script* but for multiple applications and multiple scripts - -*Listing* interaction would require ``android.permission.INTERNET`` permission. We can add such permission by modifying the manifest. Instead, we will use the *Script* interaction which does not require permission. - -The Frida payload will be located in ``/data/local/tmp/myscript.js`` file. The gadget configuration associated with context is given below - -.. code-block:: json - - { - "interaction": { - "type": "script", - "path": "/data/local/tmp/myscript.js", - "on_change": "reload" - } - } - -Use of configuration file must follow two requirements: - -1. File must have the same name as the gadget library name (e.g. ``libgadget.so`` and ``libgadget.conf``) -2. The configuration file must be located in the **same** directory as the gadget library - -The second requirement means that after the installation on the device, the gadget library will look for the config file in the ``/data/app/org.telegram.messenger-1/lib`` directory. - -When installing an application, the Android package manager will copy files from the ``lib/`` directory of the APK only if [4]_: - -* It starts with the prefix ``lib`` -* It ends with the suffix ``.so`` -* It's ``gdbserver`` - -Frida is aware of these requirements as illustrated in listing below. Hence we can simply add the suffix ``.so`` to ``libgadget.conf`` - -.. code-block:: cpp - - #if ANDROID - if (!FileUtils.test (config_path, FileTest.EXISTS)) { - var ext_index = config_path.last_index_of_char ('.'); - if (ext_index != -1) { - config_path = config_path[0:ext_index] + ".config.so"; - } else { - config_path = config_path + ".config.so"; - } - } - #endif - -.. rst-class:: center - -`lib/gadget/gadget.vala `_ - -Finally, the ``lib`` directory of the new Telegram ``.apk`` has the following structure: - -.. code-block:: bash - - $ tree lib - . - └── arm64-v8a - ├── libgadget.config.so - ├── libgadget.so - └── libtmessages.28.so - -With ``libtmessages.28.so`` linked with ``libgadget.so`` - -.. code-block:: bash - - $ readelf -d ./arm64-v8a/libtmessages.28.so - 0x0000000000000001 (NEEDED) Shared library: [libgadget.so] - ... - - - -Run -#### - -Once: - -1. The injection done in ``libtmessages.28.so`` -2. The gadget library and its configuration placed in the ``/lib/ABI`` directory -3. The application resigned - -We can install the repackaged APK ``new.apk`` and push ``myscript.js`` in ``/data/local/tmp``: - -.. code-block:: console - - $ adb shell install new.apk - $ adb push myscript.js /data/local/tmp - $ adb shell chmod 777 /data/local/tmp/myscript.js - -The Frida script ``myscript.js`` used in this tutorial is just a call to the Android log function: - -.. code-block:: javascript - - 'use strict'; - - console.log("Waiting for Java.."); - - Java.perform(function () { - var Log = Java.use("android.util.Log"); - Log.v("frida-lief", "Have fun!"); - }); - -.. rst-class:: center - -myscript.js - - -Lastly, we can run the telegram application and observe the Android logs: - -.. figure:: ../_static/tutorial/09/telegram.png - :scale: 25% - :align: center - -.. code-block:: console - - $ adb logcat -s "frida-lief:V" - --------- beginning of system - --------- beginning of main - 03-24 17:23:51.908 10243 10243 V frida-lief: Have Fun! - - -Conclusion -~~~~~~~~~~ - -With this tutorial we demonstrated how format instrumentation and dynamic instrumentation can be combined. - -Here is a quick summary of advantages/disadvantages of this technique - -:Advantages: - - * Doesn't require rooted device - * Doesn't depend of frida-server - * Can be used to bypass some anti-frida - * Doesn't modify ``AndroidManifest.xml`` and DEX file(s) - -:Disadvantages: - - * Require to add files in the APK - * Require that the application have at least one native library - * Hope that the library is loaded early in the application - - - -.. rubric:: Notes - -.. [1] Note that LIEF **does not** modify the :attr:`~lief.ELF.DYNAMIC_TAGS.DEBUG` entry ... - -.. [2] Modification of the ELF Dynamic section is not as easy as the API looks like. - -.. [3] In the ELF format they are located in the :attr:`~lief.ELF.DYNAMIC_TAGS.INIT_ARRAY` or :attr:`~lief.ELF.DYNAMIC_TAGS.INIT` entries - -.. [4] For those who are interested, checks are done in the ``framework_base/core/jni/com_android_internal_content_NativeLibraryHelper.cpp`` file. - Actually these checks on the prefix and suffix are only done if the application is not *debuggable*. - - - - -.. rubric:: API - -* :meth:`lief.ELF.Binary.add_library` - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/10_android_formats.md b/vendor/lief/doc/sphinx/tutorials/10_android_formats.md new file mode 100644 index 0000000..5871e2f --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/10_android_formats.md @@ -0,0 +1,485 @@ +(tuto-android-formats)= + +# 10 - Android formats + +This tutorial introduces Android formats and the API for using them. This +includes DEX, OAT, VDEX, and ART. + +______________________________________________________________________ + +## Introduction + +Let's start with a quick overview of the compilation, installation, and +execution of Android applications. + +When developing applications, the main part of the code is usually written in +Java. Developers can also write native code (`C/C++`) through the Java Native +Interface (JNI). + +In the APK building process, Java code is eventually transformed into Dalvik +bytecode, which is interpreted by the Android Java virtual machine. The Android +JVM differs from Oracle's implementation; among other differences, it is +register-based, whereas Oracle's implementation is stack-based. + +To produce Dalvik bytecode, Java sources are first compiled with `javac` into +Java bytecode, which Android then transforms into Dalvik bytecode using the +`dx` compiler (or the newer `D8`). This bytecode is finally wrapped in DEX +files, such as `classes.dex`. The DEX format is specific to Android, and its +documentation is available [here](https://source.android.com/devices/tech/dalvik/dex-format). + +During APK installation, the system applies optimizations to the DEX file to +speed up execution. Interpreting bytecode is not as efficient as executing +native code, and the Dalvik virtual machine is based on 32-bit registers, +whereas most recent CPUs are 64-bit. + +To address this issue, and prior to Android 4.4 (KitKat), the runtime used JIT +compilation to transform Dalvik bytecode into assembly. JIT occurred **during +execution** each time the application was run. Since Android 4.4, Android has +used a new runtime that performs optimizations **during installation**. +Consequently, installation takes more time, but the transformation to native +code is performed only once. + +To optimize Dalvik bytecode, the original DEX file (e.g., `classes.dex`) is +transformed into another file containing the native code. This new file +typically has the `.odex` or `.oat` extension and is wrapped in the ELF +format. Using the ELF format makes sense for two main reasons: + +- It is the default format used by Linux and Android to package assembly code. +- It enables the use of the same loader: `/system/bin/linker{64}`. + +OAT files are actually ELF files, which is why we chose to add support for this +format in LIEF. The ELF format acts as a wrapper around the Android-specific +OAT format. + +Basically, the associated ELF exports a few symbols: + +{{ literalinclude("../../code/python/tuto_android.py", "oat-symbols") }} + +```text +oatdata OBJECT GLOBAL 1000 1262000 +oatexec OBJECT GLOBAL 1263000 10d4060 +oatlastword OBJECT GLOBAL 233705c 4 +oatbss OBJECT GLOBAL 2338000 f5050 +oatbsslastword OBJECT GLOBAL 242d04c 4 +``` + +These symbols serve as pointers to specific parts of the OAT format. For +example, `oatdata` points to the beginning of the underlying OAT format, +while `oatexec` points to the native code. For a deeper understanding of OAT +internal structures, see: + +- [Hiding Behind ART - Black Hat 2015](https://www.blackhat.com/docs/asia-15/materials/asia-15-Sabanal-Hiding-Behind-ART-wp.pdf) +- [Dalvik and ART](http://newandroidbook.com/files/ArtOfDalvik.pdf) +- [OAT internal structures](http://romainthomas.fr/oat/) + +These different formats can be a bit confusing. To summarize: + +```{eval-rst} +.. centered:: DEX files are transformed into ``.odex`` files, which are primarily ELF files wrapping a custom OAT format. +``` + +:::{figure} ../_static/tutorial/10/elf_oat.png +:align: center +:scale: 50% +::: + +OAT structure is poorly documented, and its internal structures change with +**each version** of Android without backward compatibility. This means OAT +files produced on Android 6.0.1 can only be used on that version. + +______________________________________________________________________ + +In the Android framework, the `dex2oat` executable is responsible for +converting and optimizing APK DEX files into OATs. This executable is located +in the `/system/bin/` directory, and its output can be viewed via logcat: + +```console +$ adb logcat -s "dex2oat:I" +... +05-04 10:16:37.218 1987 1987 I dex2oat : /system/bin/dex2oat --compiler-filter=speed --dex-file=/data/user/0/com.google.android.gms/snet/installed/snet.jar --oat-file=/data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex +05-04 10:16:37.688 1987 1998 W dex2oat : Compilation of void com.google.android.snet.Snet.enterSnetIdle(android.content.Context, android.os.Bundle) took 116.995ms +05-04 10:16:37.768 1987 1987 I dex2oat : ---------------------------------------------------- +05-04 10:16:37.768 1987 1987 I dex2oat : : S T A R T I N G . . . +05-04 10:16:37.768 1987 1987 E dex2oat : : oat location is not valid /data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex +05-04 10:16:37.768 1987 1987 I dex2oat : dex2oat took 552.045ms (threads: 8) arena alloc=3MB java alloc=1150KB native alloc=8MB free=3MB +05-04 12:25:50.878 10460 10460 I dex2oat : /system/bin/dex2oat --compiler-filter=speed +... +``` + +The output above shows the transformation of SafetyNet DEX files, located in +`/data/user/0/com.google.android.gms/snet/installed/snet.jar`, into an **OAT** +saved in `/data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex`. + +One can see that the extension is `.dex`, which suggests a DEX file rather +than an OAT. However, checking the file type reveals: + +```console +$ file snet.dex +snet.dex: ELF 64-bit LSB shared object, ARM aarch64, version 1 (GNU/Linux), dynamically linked, stripped +``` + +It is an ELF file. + +:::{warning} +Do not trust extensions: +**.dex** can be **DEX** or **OAT**, **.odex** files are **OAT**, **.oat** files are **OAT**, etc. +::: + +The process of converting Java sources into OAT can be simplified with the +following diagram: + +:::{figure} ../_static/tutorial/10/java2oat.png +:align: center +::: + +## The Missing DEX + +When analyzing applications from the Google Play Store, the APK usually +contains `classes.dex` files. Since these files contain the Dalvik bytecode, +most tools rely on them for analysis (decompilation, static analysis, etc.). + +However, when analyzing manufacturer firmware (or ROMs), these DEX files might +be missing. For example, the Samsung `com.android.settings` application is +associated with the `/system/priv-app/SecSettings2` directory, which has the +following structure: + +```console +$ tree system/priv-app/SecSettings2 + +├── oat +│ └── arm64 +│ └── SecSettings2.odex +└── SecSettings2.apk + +2 directories, 2 files +``` + +The `SecSettings2.apk` file does not contain any `.dex` files: + +```console +$ unzip -l ./SecSettings2.apk|grep -c "classes.dex" +0 +``` + +Next to `SecSettings2.apk` is `SecSettings2.odex`, which is the OAT file +resulting from the optimization of the missing DEX file. Since ROM developers +control the Android version and target architecture, they only need to provide +the OAT file. + +This "feature" can also be used to hinder analysis and reverse engineering. +Since the Dalvik bytecode resides in the DEX file, analysis is quite limited +without it. + +Fortunately, a copy of the original DEX is included within the OAT! While it is +not an exact copy (as `dex2oat` replaces some Dalvik instructions, such as +`invoke-virtual`, with optimized ones [^footnote-1]), starting with **Android N**, +the original instructions can also be recovered. + +Prior to Android Oreo (8.0.0), DEX files were embedded in the OAT itself. +After Oreo, the transformation performed by `dex2oat` generates two files: + +- **classes.odex**: OAT containing native code +- **classes.vdex**: VDEX file containing a copy of the original DEX files + +The DEX files originally located in the OAT have been exported to a **new +file** with a **new format**: VDEX. This format is completely different from +OAT; specifically, it is not an ELF file. + +Similar to the OAT format, VDEX internal structures change with each version of +Android without backward compatibility. + +There also exist tools [^footnote-4] [^footnote-5] [^footnote-6] to extract DEX files from OAT/VDEX files, +but extraction [^footnote-3] is either limited to OAT [^footnote-4] or VDEX [^footnote-5]. LIEF aims to +provide a single framework for dealing with these formats. + +## OAT and VDEX + +As explained previously, the internal structures of these formats change with +each version of Android. LIEF provides an abstraction of these modifications, +allowing users to work with OAT or VDEX without worrying about the underlying +version. + +LIEF currently supports OAT files from Android 6.0 Marshmallow (OAT v64) to +Android 8.0.1 Oreo (OAT v131). + +The OAT version can be obtained using the {func}`lief.OAT.version` function: + +```python +>>> import lief +>>> lief.OAT.version("classes.odex") # From Android 6 +64 +>>> lief.OAT.version("classes.odex") # From Android 7 +88 +``` + +The associated Android version can be accessed using +{func}`lief.OAT.android_version`: + +```python +>>> lief.OAT.android_version(64) +ANDROID_VERSIONS.VERSION_601 +>>> lief.OAT.android_version(124) +ANDROID_VERSIONS.VERSION_800 +>>> lief.Android.code_name(lief.Android.ANDROID_VERSIONS.VERSION_800) +'Oreo' +>>> lief.Android.version_string(lief.Android.ANDROID_VERSIONS.VERSION_800) +"8.0.0" +``` + +To reflect the fact that OAT files are first and foremost ELF files, the +{class}`lief.OAT.Binary` class extends {sub-ref}`lief-elf-binary`: + +```python +>>> import lief +>>> oat = lief.OAT.parse("classes.odex") +>>> type(oat) +_pylief.OAT.Binary +>>> isinstance(oat, lief.ELF.Binary) +True +``` + +Thus, the same ELF API is available (adding sections, modifying dynamic +entries, etc.), and the {class}`lief.OAT.Binary` object adds the following +methods: + +```{eval-rst} +.. autoclass:: lief.OAT.Binary + :noindex: + :members: + :undoc-members: +``` + +If the OAT targets Android Marshmallow or Nougat (6 or 7), DEX files can be +retrieved via the {attr}`lief.OAT.Binary.dex_files` attribute: + +{{ literalinclude("../../code/python/tuto_android.py", "oat-extract-dex") }} + +In the code above, the {class}`lief.DEX.File` has been extracted to +`/tmp/classes.dex` (with de-optimization). + +If the OAT targets Android Oreo or above, extraction uses the VDEX file. The +{func}`lief.OAT.parse` function accepts an OAT file, or both an OAT **and** a +VDEX file. Providing the VDEX file allows the {class}`lief.OAT.Binary` object +to offer the same functionality as it does for pre-Oreo OAT files. + +If the VDEX file is not provided, the {class}`lief.OAT.Binary` will have +limited information: + +```python +# Without VDEX file +>>> oat_oreo = lief.OAT.parse("KeyChain.odex") +>>> len(oat_oreo.dex_files) +0 +>>> len(oat_oreo.classes) +0 +>>> len(oat_oreo.oat_dex_files) +1 +>>> oat_dex_file = oat_oreo.oat_dex_files[0] +>>> print(oat_dex_file) +/system/app/KeyChain/KeyChain.apk - (Checksum: 0x206c8ab1) +``` + +```python +# With VDEX file +>>> oat_oreo = lief.OAT.parse("KeyChain.odex", "KeyChain.vdex") +>>> len(oat_oreo.dex_files) +1 +>>> len(oat_oreo.classes) +17 +>>> oat_oreo.dex_files[0].save("/tmp/classes.dex") +``` + +The LIEF VDEX module can also be used directly: + +```python +>>> vdex = lief.VDEX.parse("KeyChain.vdex") +``` + +Because the VDEX format is completely different from OAT, ELF, PE, and Mach-O, +the VDEX parser creates a {class}`lief.VDEX.File` object rather than a +{class}`~lief.Binary`. DEX files can be extracted using the +{attr}`lief.VDEX.File.dex_files` attribute: + +```python +>>> len(vdex.dex_files) +1 +>>> vdex.dex_files[0].save("/tmp/KeyChain.dex") # With de-optimization +``` + +## DEX + +The previous section covered the OAT and VDEX formats and how to access the +underlying DEX. This section introduces the primary API for the +{class}`lief.DEX.File` object. + +The LIEF DEX module allows you to obtain information about Java code, such as +strings, class names, Dalvik bytecode, etc. + +:::{note} +Since the LIEF project focuses solely on formats, the DEX module does not +include a Dalvik disassembler. +::: + +The primary API for a DEX file is in the {class}`lief.DEX.File` object. This +object can be generated using: + +> - {attr}`lief.OAT.Binary.dex_files` +> - {attr}`lief.VDEX.File.dex_files` +> - {func}`lief.DEX.parse` + +```python +>>> oat = lief.OAT.parse("SecSettings2.odex") +>>> type(oat.dex_files[0]) +_pylief.DEX.File + +>>> vdex = lief.VDEX.parse("SecSettings2.odex") +>>> type(vdex.dex_files[0]) +_pylief.DEX.File + +>>> dex = lief.DEX.parse("classes.dex") +>>> type(dex) +_pylief.DEX.File +``` + +Once created, strings can be accessed via the {attr}`lief.DEX.File.strings` +attribute: + +{{ literalinclude("../../code/python/tuto_android.py", "dex-strings") }} + +```text +https://analytics.mopub.com/i/jot/exchange_client_event +https://app-measurement.com/a +https://mobilecrashreporting.googleapis.com/v1/crashes:batchCreate?key= +https://pagead2.googlesyndication.com/pagead/gen_204?id=gmob-apps +https://plus.google.com/ +https://ssl.google-analytics.com +https://support.google.com/dfp_premium/answer/7160685#push +https://www.google.com +... +``` + +Similarly, methods and classes are available via the +{attr}`lief.DEX.File.classes` and {attr}`lief.DEX.File.methods` attributes: + +{{ literalinclude("../../code/python/tuto_android.py", "dex-source-files") }} + +```text +com.avast.android.sdk.antitheft.internal.protection.wipe.a - CalendarWiper.java - 3 Methods +com.avast.android.account.internal.identity.a - AvastIdentityProvider.java - 17 Methods +com.avast.android.account.internal.identity.d - FacebookIdentityProvider.java - 19 Methods +com.avast.android.lib.wifiscanner.internal.b$a - WifiScannerComponentFactory.java - 1 Methods +``` + +In the DEX file format, a special attribute for classes records the original +source filename: [source_file_idx](https://source.android.com/devices/tech/dalvik/dex-format#class-def-item). +Some obfuscators mangle class names but preserve this attribute! Since Java +source filenames are associated with class names, the deobfuscated name can +often be recovered using: + +> - {attr}`lief.DEX.Class.source_filename` +> - {attr}`lief.DEX.Class.pretty_name` + +{{ literalinclude("../../code/python/tuto_android.py", "dex-deobfuscate") }} + +```text +com.avast.android.sdk.antitheft.internal.protection.wipe.a: ---> CalendarWiper.java +com.avast.android.account.internal.identity.a ---> AvastIdentityProvider.java +com.avast.android.account.internal.identity.d ---> FacebookIdentityProvider.java +com.avast.android.lib.wifiscanner.internal.b$a ---> WifiScannerComponentFactory.java + + +DEX methods are represented by the :class:`~lief.DEX.Method` object, and raw +Dalvik bytecode can be accessed via :attr:`lief.DEX.Method.bytecode`. +``` + +## ART + +**ART** is the name of the **Android Runtime**, but it is also a **format**! +This format is used for optimization by the Android **framework**. + +As discussed previously, Android has its own implementation of the Java +virtual machine based on Dalvik bytecode. This JVM is implemented in C++, and +Java primitives (`java.lang.String`, `java.lang.Object`, etc.) are mirrored +with C++ objects: + +- `java.lang.Class`: `art::mirror::Class` + +- `java.lang.String`: `art::mirror::String` + +- `java.lang.reflect.Method`: `art::mirror::Method` + +- ... + +When a **new** Java class is instantiated, a mirrored C++ object is created +(memory allocation, constructor calls, etc.), and the JVM maintains a +reference to this C++ object. To speed up the boot process and avoid +re-instantiating well-known classes [^footnote-2] at each boot, Android uses the ART +format to store instances of C++ objects. It can be thought of as a heap dump +of C++ objects. + +As with OAT and VDEX, the internal structures of this format change with each +version of Android. + +LIEF 0.9 provides basic support for this format and exposes the ART +{class}`lief.ART.Header`. The primary API is available in the +{class}`lief.ART.File` object. + +{{ literalinclude("../../code/python/tuto_android.py", "art-header") }} + +```text +Version: 46 +Image Begin: 0x70000000 +Image Size: 0x238ac8 +Checksum: 0x997c0fb0 +OAT File Begin: 0x70a5b000 +OAT File End: 0x71272000 +OAT Data Begin: 0x70a5c000 +OAT Data End: 0x7126df70 +Patch Delta: 0 +Pointer Size: 8 +Compile pic: true +Number of sections: 10 +Number of methods: 7 +Boot Image Begin: 0 +Boot Image Size: 0 +Boot OAT Begin: 0 +Boot OAT Size: 0 +Storage Mode: UNCOMPRESSED +Data Size: 0x2389f0 +``` + +## Conclusion + +LIEF 0.9 provides *read-only* access to these formats, but future versions +should allow for modification (adding methods, changing names, patching +checksums, etc.). + +Enjoy! + +```{rubric} Notes +``` + +[^footnote-1]: + - + - + +[^footnote-2]: Usually those from the Android Framework. + +[^footnote-3]: Other tools may have additional features like a disassembler or + pseudo-code generation that are not covered in LIEF. + +[^footnote-4]: Dextra by Jonathan Levin: + +[^footnote-5]: vdexExtractor by Anestis Bechtsoudis: + +[^footnote-6]: smali by JesusFreke: + +```{rubric} API +``` + +- {class}`lief.OAT.Binary` +- {class}`lief.VDEX.File` +- {class}`lief.DEX.File` +- {class}`lief.ART.File` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/tutorials/10_android_formats.rst b/vendor/lief/doc/sphinx/tutorials/10_android_formats.rst deleted file mode 100644 index 1960e37..0000000 --- a/vendor/lief/doc/sphinx/tutorials/10_android_formats.rst +++ /dev/null @@ -1,450 +0,0 @@ -10 - Android formats --------------------- - -This tutorial introduces Android formats as well as the API to use them. We are talking about DEX, OAT, VDEX and ART. - -Files used in this tutorial are available on the `tutorials repository `_ - -By Romain Thomas - `@rh0main `_ - ------- - -Introduction -~~~~~~~~~~~~ - -Let's start with a quick reminder about *compilation*, installation and the execution of Android applications. - -When dealing with application development, the main part of the code is usually written in Java. Developers can also write native code (``C/C++``) through -the Java Native Interface (JNI) interface. - -In the APK building process, the Java code is eventually transformed in the Dalvik bytecode which is interpreted by the Android Java virtual machine. The Android JVM is different from -the implementation by Oracle and, among the differences, it is based on registers whereas the one from Oracle is based on a stack. - -To produce the Dalvik bytecode, Java sources are first compiled with ``javac`` into the Java bytecode and then Android transforms this -bytecode into the Dalvik one by using the ``dx`` compiler (or the new one: ``D8``). This bytecode is finally wrapped in a DEX file(s) such as ``classes.dex``. The DEX format is specific -to Android and the documentation is available `here `_. - -During the installation of the APK, the system applies optimizations on this DEX file in order to speed-up the execution. Indeed interpreting bytecode is not as -efficient as executing native code and the Dalvik virtual machine is based on registers that are 32-bits width size whereas most of the recent CPU are 64-bits width. - -To address this issue and prior to Android 4.4 (KitKat), the runtime used JIT compilation to transform Dalvik bytecode into assembly. The JIT ocurred **during the execution** and it was done -each time the application was executed. Since Android 4.4 they moved to a new runtime which, among other features, performs the optimizations **during the installation**. -Consequently the installation takes more time but transformations to native code are done once. - -To optimize the Dalvik bytecode, the original DEX file (e.g. ``classes.dex``) is transformed into another file that will contain the native code. This new file usually has -the ``.odex``, ``.oat`` extension and is wrapped by the ELF format. Using ELF format makes sense for mainly two reasons: - -- It's the default format used by Linux and Android to *package* assembly code. -- It enables to use the same loader: ``/system/bin/linker{64}`` - -OAT files are in fact ELF and this is why, we choose to add this new format in LIEF. -This ELF format is actually used as a wrapper over another format which is specific to Android: the OAT format. - -Basically the ELF associated exports few symbols: - -.. code-block:: python - - import lief - - oat = lief.parse("SomeOAT") - for s in oat.dynamic_symbols: - print(s) - - -.. code-block:: text - - oatdata OBJECT GLOBAL 1000 1262000 - oatexec OBJECT GLOBAL 1263000 10d4060 - oatlastword OBJECT GLOBAL 233705c 4 - oatbss OBJECT GLOBAL 2338000 f5050 - oatbsslastword OBJECT GLOBAL 242d04c 4 - -These symbols are a kind of pointers to specific part of the OAT format. For example, ``oatdata`` will point to the begining of the underlying OAT format whereas ``oatexec`` points -to the native code. For those who are interested in a deeper understand of OAT internal structures, See: - -* `Hiding Behind ART - Black Hat 2015 `_ -* `Dalvik and ART `_ -* `OAT internal structures `_ - - -These different formats can be a bit confusing and to summarize: - -.. centered:: DEX are transformed into ``.odex`` files that are primarily ELF files wrapping a custom OAT format. - -.. figure:: ../_static/tutorial/10/elf_oat.png - :scale: 50% - :align: center - -The structure of the OAT is poorly documented and its internal structures change for **each version** of Android without backward compatibility. -It means that OAT files produced on Android 6.0.1 can only be used on this version. - -------- - -In the Android framework the ``dex2oat`` executable is responsible to convert and optimize the APK DEX files into OATs. This executable is located in the -``/system/bin/`` directory and we can have its output through logcat: - -.. code-block:: console - - $ adb logcat -s "dex2oat:I" - ... - 05-04 10:16:37.218 1987 1987 I dex2oat : /system/bin/dex2oat --compiler-filter=speed --dex-file=/data/user/0/com.google.android.gms/snet/installed/snet.jar --oat-file=/data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex - 05-04 10:16:37.688 1987 1998 W dex2oat : Compilation of void com.google.android.snet.Snet.enterSnetIdle(android.content.Context, android.os.Bundle) took 116.995ms - 05-04 10:16:37.768 1987 1987 I dex2oat : ---------------------------------------------------- - 05-04 10:16:37.768 1987 1987 I dex2oat : : S T A R T I N G . . . - 05-04 10:16:37.768 1987 1987 E dex2oat : : oat location is not valid /data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex - 05-04 10:16:37.768 1987 1987 I dex2oat : dex2oat took 552.045ms (threads: 8) arena alloc=3MB java alloc=1150KB native alloc=8MB free=3MB - 05-04 12:25:50.878 10460 10460 I dex2oat : /system/bin/dex2oat --compiler-filter=speed - ... - -The output above is the transformation of SaftyNet DEX files, located in ``/data/user/0/com.google.android.gms/snet/installed/snet.jar``, into an **OAT** saved in ``/data/user/0/com.google.android.gms/snet/dalvik-cache/snet.dex``. - -One can notice that the extension is ``.dex`` so it should be a DEX file and not an OAT. Actually if we check the type: - -.. code-block:: console - - $ file snet.dex - snet.dex: ELF 64-bit LSB shared object, ARM aarch64, version 1 (GNU/Linux), dynamically linked, stripped - -We can see an ELF. - -.. warning:: - - Do not trust extensions: - **.dex** can be **DEX** or **OAT**, **.odex** are **OAT**, **.oat** are **OAT**, ... - - -The process of converting Java sources into the OAT can be simplified with the following diagram: - - -.. figure:: ../_static/tutorial/10/java2oat.png - :align: center - - -The Missing DEX -~~~~~~~~~~~~~~~ - -If we analyze applications from the Google PlayStore, we usually have the ``classes.dex`` file(s) in APK. As this file contains the Dalvik bytecode, most of the tools rely -on this file to perform the analysis (decompilation, static analysis, ...) - -However when analyzing constructor firmwares (or ROM) these DEX files could miss. For example, if we are interested in ``com.android.settings`` from Samsung, -the application is associated with the ``/system/priv-app/SecSettings2`` directory which has the following structure: - -.. code-block:: console - - $ tree system/priv-app/SecSettings2 - - ├── oat - │ └── arm64 - │ └── SecSettings2.odex - └── SecSettings2.apk - - 2 directories, 2 files - -By looking at the files in ``SecSettings2.apk``, we can't find ``.dex`` files: - -.. code-block:: console - - $ unzip -l ./SecSettings2.apk|grep -c "classes.dex" - 0 - -Next to the ``SecSettings2.apk``, we find ``SecSettings2.odex`` which is the OAT file resulting of the optimization of the missing DEX file. -As ROM developers control the Android **version** and the target architecture, they just have to provide the OAT file. - -They can also use this *"feature"* to avoid analysis and reverse engineering of the application. As the Dalvik bytecode is located in the DEX file, without this file the analysis -is quite limited. - -Thankfully there is a copy of the original DEX within the OAT! Actually it's not an exact copy as ``dex2oat`` replaces some Dalvik instructions (like ``invoke-virtual``) with optimized ones [1]_ but starting from **Android N**, we can also recover the original instructions. - -Prior Android Oreo (8.0.0) DEX files were embedded in the OAT itself and after Oreo, the transformation performed by ``dex2oat`` generates two files: - -- **classes.odex**: OAT containing native code -- **classes.vdex**: VDEX file containing copy of original DEX files - -The DEX files originally located in the OAT has been exported **in a new file** with **a new format**: the VDEX format. This new format is completely -different from OAT, especially it's not an ELF. - -In the same way as OAT format, VDEX internal structures change for each version of Android without backward compatibility. - -It also exists tools [4]_ [5]_ [6]_ to extract DEX from OAT/VDEX files but the **extraction** [3]_ is either limited to OAT [4]_ or to VDEX [5]_. With LIEF we aim to provide a single framework to deal with these formats. - -OAT and VDEX -~~~~~~~~~~~~ - -As explained in the previous part, internal structures of the formats change for each version of Android. LIEF provides an abstraction -of these modifications and the user can deal with OAT or VDEX without carrying of the underlying version of the OAT. - -It currently supports OAT files from Android 6.0 Marshmallow (OAT v64) to Android 8.0.1 Oreo (OAT v131). - -The OAT version is available with the :func:`lief.OAT.version` function: - -.. code-block:: python - - >>> import lief - >>> lief.OAT.version("classes.odex") # From Android 6 - 64 - >>> lief.OAT.version("classes.odex") # From Android 7 - 88 - -One can also access to the associated Android version by using :func:`lief.OAT.android_version`: - -.. code-block:: python - - >>> lief.OAT.android_version(64) - ANDROID_VERSIONS.VERSION_601 - >>> lief.OAT.android_version(124) - ANDROID_VERSIONS.VERSION_800 - >>> lief.Android.code_name(lief.Android.ANDROID_VERSIONS.VERSION_800) - 'Oreo' - >>> lief.Android.version_string(lief.Android.ANDROID_VERSIONS.VERSION_800) - "8.0.0" - -To express the fact that OAT files are first ELF, the :class:`lief.OAT.Binary` class extends the :class:`lief.ELF.Binary` - -.. code-block:: python - - >>> import lief - >>> oat = lief.parse("classes.odex") - >>> type(oat) - _pylief.OAT.Binary - >>> isinstance(oat, lief.ELF.Binary) - True - -Thus the same ELF API is available: adding sections, modifying dynamic entries, etc and the :class:`lief.OAT.Binary` object adds the following methods: - -.. autoclass:: lief.OAT.Binary - :noindex: - :members: - :undoc-members: - -If the given OAT targets Android Marshmallow or Nougat (6 or 7) then DEX files can be retrieved with the :attr:`lief.OAT.Binary.dex_files` attribute: - -.. code-block:: python - - >>> len(oat.dex_files) # > 1 if multi-dex - 1 - >>> dex = oat.dex_files[0] - >>> dex.save("/tmp/classes.dex") - -From the code above, the :class:`lief.DEX.File` has been extracted to ``/tmp/classes.dex`` (with de-optimization). - -If the given OAT targets Android Oreo or above, then extraction is done by using the VDEX file. The :func:`lief.OAT.parse` function accepts an OAT file or -an OAT **and** a VDEX file. By providing the VDEX file in the second parameter, the :class:`lief.OAT.Binary` object will have the same functionalities as the one for OAT pre-Oreo. - -If the VDEX file is not provided then :class:`lief.OAT.Binary` will have limited information: - -.. code-block:: python - - # Without VDEX file - >>> oat_oreo = lief.parse("KeyChain.odex") - >>> len(oat_oreo.dex_files) - 0 - >>> len(oat_oreo.classes) - 0 - >>> len(oat_oreo.oat_dex_files) - 1 - >>> oat_dex_file = oat_oreo.oat_dex_files[0] - >>> print(oat_dex_file) - /system/app/KeyChain/KeyChain.apk - (Checksum: 0x206c8ab1) - - -.. code-block:: python - - # With VDEX file - >>> oat_oreo = lief.OAT.parse("KeyChain.odex", "KeyChain.vdex") - >>> len(oat_oreo.dex_files) - 1 - >>> len(oat_oreo.classes) - 17 - >>> oat_oreo.dex_files[0].save("/tmp/classes.dex") - -We can also use the LIEF's VDEX module directly: - -.. code-block:: python - - >>> vdex = lief.VDEX.parse("KeyChain.vdex") - -As the VDEX format is completely different from OAT, ELF, PE and Mach-O the VDEX parser creates a :class:`lief.VDEX.File` object and not a :class:`~lief.Binary`. -We can also extract DEX files with the :attr:`lief.VDEX.File.dex_files` attribute: - -.. code-block:: python - - >>> len(vdex.dex_files) - 1 - >>> vdex.dex_files[0].save("/tmp/KeyChain.dex") # With de-optimization - - -DEX -~~~ - -The previous part was about the OAT/VDEX formats and how to access to the underlying DEX. This part introduces the main API for the :class:`lief.DEX.File` object. - -The LIEF DEX module enables to get information about Java code such as String, classes name, dalvik bytecodes, ... - -.. note:: - - As LIEF project is only focused on formats, there won't be Dalvik disassembler in the DEX module. - -The main API for a DEX file is in the :class:`lief.DEX.File` object. This object can be generated using: - - * :attr:`lief.OAT.Binary.dex_files` - * :attr:`lief.VDEX.File.dex_files` - * :func:`lief.DEX.parse` - -.. code-block:: python - - >>> oat = lief.parse("SecSettings2.odex") - >>> type(oat.dex_files[0]) - _pylief.DEX.File - - >>> vdex = lief.VDEX.parse("SecSettings2.odex") - >>> type(vdex.dex_files[0]) - _pylief.DEX.File - - >>> dex = lief.DEX.parse("classes.dex") - >>> type(dex) - _pylief.DEX.File - - -Once created, we can access to the strings with the :attr:`lief.DEX.File.strings` attribute: - -.. code-block:: python - - >>> len(dex.strings) - 23529 - >>> for s in dex.strings: - ... if http in s: - ... print(s) - - https://analytics.mopub.com/i/jot/exchange_client_event - https://app-measurement.com/a - https://mobilecrashreporting.googleapis.com/v1/crashes:batchCreate?key= - https://pagead2.googlesyndication.com/pagead/gen_204?id=gmob-apps - https://plus.google.com/ - https://ssl.google-analytics.com - https://support.google.com/dfp_premium/answer/7160685#push - https://www.google.com - ... - -Similarly, methods and classes are available with the :attr:`lief.DEX.File.classes` / :attr:`lief.DEX.File.methods` attributes: - -.. code-block:: python - - for cls in dex.classes: - if cls.source_filename: - print(cls) - -.. code-block:: text - - com.avast.android.sdk.antitheft.internal.protection.wipe.a - CalendarWiper.java - 3 Methods - com.avast.android.account.internal.identity.a - AvastIdentityProvider.java - 17 Methods - com.avast.android.account.internal.identity.d - FacebookIdentityProvider.java - 19 Methods - com.avast.android.lib.wifiscanner.internal.b$a - WifiScannerComponentFactory.java - 1 Methods - -In the DEX file format, there is a special attribute for classes that register the original source filename: `source_file_idx `_. -Some *obfuscators* mangle classes but keep this attribute! Since Java source filenames are associated with class names, we can easily recover the deobfuscated name using: - - * :attr:`lief.DEX.Class.source_filename` - * :attr:`lief.DEX.Class.pretty_name` - -.. code-block:: python - - for cls in dex.classes: - if cls.source_filename: - print(cls.pretty_name + ": ---> " + cls.source_filename) - -.. code-block:: text - - com.avast.android.sdk.antitheft.internal.protection.wipe.a: ---> CalendarWiper.java - com.avast.android.account.internal.identity.a ---> AvastIdentityProvider.java - com.avast.android.account.internal.identity.d ---> FacebookIdentityProvider.java - com.avast.android.lib.wifiscanner.internal.b$a ---> WifiScannerComponentFactory.java - - - If we are interested with DEX methods, they are represented with the :class:`~lief.DEX.Method` object and we can access to the **raw** Dalvik bytecode through :attr:`lief.DEX.Method.bytecode` - -ART -~~~ - -**ART** is the name of the **Android Runtime** but it's also a **format**! This format is used for optimization purpose by the Android's **framework**. - -As discussed previously, Android has its own implementation of the Java virtual based on the Dalvik bytecode. -This JVM is implemented in C++ and Java primitives (``java.lang.String``, ``java.lang.Object``, etc) are mirrored with C++ objects: - -* ``java.lang.Class``: ``art::mirror::Class`` -* ``java.lang.String``: ``art::mirror::String`` -* ``java.lang.reflect.Method``: ``art::mirror::Method`` -* ... - -When instantiating a **new** Java class, it creates a mirrored C++ object (Memory allocation, calling constructors, ...) and the JVM handles a reference on this C++ object. To speed up the boot process and to avoid instantiation of well-known classes [2]_ at each boot, Android uses the ART format to store instances of C++ objects. To simplify, it can be seen as a heap dump of C++ objects. - -In the same way as OAT and VDEX, the internal structures of this format change for each version of Android. - -LIEF 0.9 has a very basic support for this format and only exposes the ART :class:`lief.ART.Header`. The main API is available in the :class:`lief.ART.File` object. - -.. code-block:: python - - art = lief.ART.parse("boot.art") - print(art.header) - -.. code-block:: text - - Version: 46 - Image Begin: 0x70000000 - Image Size: 0x238ac8 - Checksum: 0x997c0fb0 - OAT File Begin: 0x70a5b000 - OAT File End: 0x71272000 - OAT Data Begin: 0x70a5c000 - OAT Data End: 0x7126df70 - Patch Delta: 0 - Pointer Size: 8 - Compile pic: true - Number of sections: 10 - Number of methods: 7 - Boot Image Begin: 0 - Boot Image Size: 0 - Boot OAT Begin: 0 - Boot OAT Size: 0 - Storage Mode: UNCOMPRESSED - Data Size: 0x2389f0 - - -oatlastword -~~~~~~~~~~~ - -LIEF 0.9 is *read-only* on these formats but further versions should enable to modify them (Add methods, change names, patch checksum, ...) - -Enjoy! - - -.. rubric:: Notes - -.. [1] * http://mylifewithandroid.blogspot.com/2009/05/about-quick-method-invocation.html - * https://github.com/JesusFreke/smali/wiki/UnresolvableOdexInstruction - -.. [2] Usually the ones from the Android Framework - -.. [3] They have other nices features like a disassembler, pseudo-code, ... that are not cover in LIEF - -.. [4] Dextra by Jonathan Levin: http://newandroidbook.com/tools/dextra.html - -.. [5] vdexExtractor by Anestis Bechtsoudis: https://github.com/anestisb/vdexExtractor - -.. [6] smali by JesusFreke: https://github.com/JesusFreke/smali/wiki/DeodexInstructions - - -.. rubric:: API - -* :class:`lief.OAT.Binary` -* :class:`lief.VDEX.File` -* :class:`lief.DEX.File` -* :class:`lief.ART.File` - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/11_macho_modification.md b/vendor/lief/doc/sphinx/tutorials/11_macho_modification.md new file mode 100644 index 0000000..dd34825 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/11_macho_modification.md @@ -0,0 +1,424 @@ +# 11 - Mach-O Modification + +This tutorial covers Mach-O format modification and introduces some internal +aspects of the format. + +Files and scripts used in this tutorial are available in the +[tutorials repository](https://github.com/lief-project/tutorials/tree/master/11_macho_modification). + +______________________________________________________________________ + +## Introduction + +A basic Mach-O binary (i.e., not FAT) can be represented in four parts, as +described in this diagram: + +:::{figure} ../_static/tutorial/11/image1.png +:align: center +::: + +The first part begins with a header that can be accessed through the +{attr}`lief.MachO.Binary.header` attribute. The second part contains the load +commands table, which can be iterated over using +{attr}`lief.MachO.Binary.load_commands`. This is optionally followed by padding +or free space. Finally, the fourth part contains the raw data (assembly code, +rebase bytecode, signatures, etc.). + +Load commands such as {class}`~lief.MachO.SegmentCommand` or +{class}`~lief.MachO.DyldInfo` can be associated with *raw data* located after +the load command table and the padding section. The padding section is used by +macOS to sign the binary after compilation by adding a custom command. The +`codesign` utility extends the *raw data* area with the signature and adds an +`LC_CODE_SIGNATURE` or `LC_DYLIB_CODE_SIGN_DRS` command in the padding +area. + +Since load commands are the base unit of the Mach-O format (segments, shared +libraries, entry points, etc., are all *commands*), the ability to add arbitrary +commands to a binary enables interesting possibilities such as code injection, +anti-analysis, etc. + +Different techniques exist for adding new commands to a Mach-O binary: + +- Replacing an existing load command that is not mandatory for execution, such + as {class}`~lief.MachO.UUIDCommand` or {class}`~lief.MachO.CodeSignature`. +- Using the padding area to expand the command header. + +The main limitation of these techniques is that the size and number of commands +that can be added are tied to the padding section size or the size of the +command replaced. + +If the padding size is small, we cannot add a `LOAD_DYLIB` command with a +very long library path. Moreover, `codesign` may complain if there is +insufficient space to add the `LC_CODE_SIGNATURE` because we are using space +that was reserved for it. + +The following sections discuss format modifications and how LIEF addresses +these limitations. + +## When PIE Makes Things Easier + +macOS and iOS executables are typically compiled with flags that make them +position-independent. Instructions generated by the compiler use relative +addressing associated with *rebase* information. + +To simplify, PIE binaries allow the *raw data* section to be mapped at a random +base address. LIEF leverages this by shifting the raw data section within the +format. + +:::{figure} ../_static/tutorial/11/image2.png +:align: center +::: + +Such a transformation also requires maintaining consistent format metadata. +Specifically, when we shift the raw data, we must update relocations, segment +offsets, virtual addresses, etc. Once the raw data is shifted and the metadata +updated, we have arbitrary space between the load command table and the raw +data section. Thus, we can extend the load command table as shown in the +figure below: + +:::{figure} ../_static/tutorial/11/image3.png +:align: center +::: + +:::{warning} +The size of the shift must be aligned with the page size to avoid issues with +section and segment alignment. +::: + +Maintaining format consistency after a shift transformation is complex. The +next section presents parts of the Mach-O format that must be updated to +maintain consistency. + +## When Mach-O Makes Things Harder + +After the shift operation, we must update several load commands: + +- {attr}`lief.MachO.SymbolCommand.symbol_offset` / {attr}`lief.MachO.SymbolCommand.strings_offset` + +- {attr}`lief.MachO.DataInCode.data_offset`, {attr}`lief.MachO.CodeSignature.data_offset`, {attr}`lief.MachO.SegmentSplitInfo.data_offset` + +- {attr}`lief.MachO.MainCommand.entrypoint` + +- {attr}`lief.MachO.FunctionStarts.data_offset` / {attr}`lief.MachO.FunctionStarts.functions` + +- {class}`~lief.MachO.DynamicSymbolCommand` + +- {attr}`lief.MachO.Section.offset` / {attr}`lief.MachO.Section.virtual_address` + +- {attr}`lief.MachO.SegmentCommand.offset` / {attr}`lief.MachO.SegmentCommand.virtual_address` + +- ... + +We also need to update: + +- Relocations +- Binding information +- Export information + +While the ELF and PE formats use structures for internal storage of +relocations and exports, the Mach-O format uses bytecode to *rebase* the +binary. Export information is stored in a [trie](https://en.wikipedia.org/wiki/Trie) +data structure. The use of tries and bytecode reduces binary size but makes +updates more difficult, as we must interpret and regenerate the bytecode. + +### Rebase Bytecode + +As mentioned previously, recent Mach-O loaders use bytecode to relocate (or +rebase) the binary. The offset and size of the bytecode are specified in the +{attr}`lief.MachO.DyldInfo.rebase` attribute. Basically, the bytecode is +composed of {class}`~lief.MachO.DyldInfo.REBASE_OPCODES` that define addresses to +relocate. + +:::{warning} +Note that the {class}`~lief.MachO.Section` object has a +{attr}`~lief.MachO.Section.relocation_offset` attribute. This appears to be +used only for Mach-O object files ({attr}`lief.MachO.Header.FILE_TYPE.OBJECT`) or +executables using an old version of the Mach-O loader. + +This offset points to a list of relocation structures (not bytecode), the +number of which is defined by {attr}`~lief.MachO.Section.numberof_relocations`. +::: + +To determine which addresses must be relocated, we must interpret the bytecode. + +The {attr}`lief.MachO.DyldInfo.show_rebases_opcodes` attribute returns the +bytecode as *pseudo-code*: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "rebase-opcodes", prepend="import lief") }} + +```text +[SET_TYPE_IMM] Type: POINTER +[SET_SEGMENT_AND_OFFSET_ULEB] Segment Index := 2 (__DATA) Segment Offset := 0x20 +[DO_REBASE_ULEB_TIMES] + for i in range(26): + rebase(POINTER, __DATA, 0x20) + Segment Offset += 0x8 (0x28) + + rebase(POINTER, __DATA, 0x28) + Segment Offset += 0x8 (0x30) + + rebase(POINTER, __DATA, 0x30) + Segment Offset += 0x8 (0x38) + + rebase(POINTER, __DATA, 0x38) + Segment Offset += 0x8 (0x40) + + rebase(POINTER, __DATA, 0x40) + Segment Offset += 0x8 (0x48) + ... +[DONE] +``` + +From the output above, we can see that the loader will rebase **pointers** in +the `__DATA` segment at offsets `0x20, 0x28, 0x38, ...`. + +For those who only care about the exact addresses being relocated, this output +is not very user-friendly. LIEF also provides a **representation** of this +bytecode by creating {class}`lief.MachO.Relocation` objects, which are the +result of interpreting the bytecode. + +The {attr}`lief.MachO.Binary.relocations` attribute returns an iterator over +{class}`lief.MachO.Relocation` objects that **model** a relocation, similar to +{class}`lief.ELF.Relocation` and {class}`lief.PE.Relocation`. + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "relocations") }} + +```text +100002020 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _err +100002028 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _errx +100002030 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _exit +100002038 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _fprintf +100002040 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _free +100002048 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _fwrite +... +``` + +Using this representation, we can update relocations by adding the shift size +to the {attr}`lief.MachO.Relocation.address` attribute. + +When the Mach-O builder reconstructs the final binary, it **regenerates** and +optimizes the rebase bytecode according to the current state of the +relocations. The process can be summarized by the following diagram: + +:::{figure} ../_static/tutorial/11/lief_bytecode.png +:align: center +::: + +### Binding Bytecode + +The Mach-O loader also uses bytecode to bind imported functions or symbols. +This bytecode is used in three different binding methods: + +- Normal binding +- Weak binding (used when the same symbol is defined multiple times) +- Lazy binding (bound only when the symbol is accessed) + +The bytecode can be pretty-printed with {attr}`~lief.MachO.DyldInfo.show_bind_opcodes`, +{attr}`~lief.MachO.DyldInfo.show_weak_bind_opcodes`, and +{attr}`~lief.MachO.DyldInfo.show_lazy_bind_opcodes`: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "bind-opcodes") }} + +```text +[SET_DYLIB_ORDINAL_IMM] + Library Ordinal := 1 +[SET_SYMBOL_TRAILING_FLAGS_IMM] + Symbol name := ___stderrp + Is Weak ? false +[SET_TYPE_IMM] + Type := POINTER +[SET_SEGMENT_AND_OFFSET_ULEB] + Segment := __DATA + Segment Offset := 0x10 +[DO_BIND] + bind(POINTER, __DATA, 0x10, ___stderrp, library_ordinal=/usr/lib/libSystem.B.dylib, addend=0, is_weak_import=false) + Segment Offset += 0x8 (0x18) +``` + +The representation and update process are identical to those described in the +*Rebase Bytecode* section. + +### Export Trie + +For exported functions and symbols, the Mach-O format uses a *trie* structure +to store export information. The trie offset and size are specified in the +{attr}`~lief.MachO.DyldInfo.export_trie` attribute. + +Once parsed, trie entries are represented via the {class}`~lief.MachO.ExportInfo` +object and can be retrieved using the {attr}`~lief.MachO.Symbol.export_info` +attribute. + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "export-trie") }} + +```text +... +_@off.0x17 + _N@off.0x21 + _NS@off.0x50 + _NSI@off.0x5d + _NSInstallLinkEditErrorHandlers@off.0x11d + _NSInstallLinkEditErrorHandlers{addr: 0x126b, flags: 0} +... +``` + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "export-info") }} + +```text +Node Offset: 128 +Flags: 0 +Address: 126b +Symbol: _NSInstallLinkEditErrorHandlers + +Node Offset: 5f6 +Flags: 0 +Address: 2168 +Symbol: _NSIsSymbolDefinedInObjectFileImage + +Node Offset: 1a0 +Flags: 0 +Address: 1391 +Symbol: _NSIsSymbolNameDefined +... +``` + +After the shift operation, export information is patched by updating the +{attr}`~lief.MachO.ExportInfo.address` attribute, and a new export trie is +generated from the updated data. + +## Removing the Signature + +Removing the `LC_CODE_SIGNATURE` command is a basic modification that is +very useful when modifying Mach-O files. Since the signature verifies the +integrity of the binary, this command typically needs to be removed after +modifying the file. The binary can be re-signed once all modifications are +finished. + +LIEF provides the {meth}`lief.MachO.Binary.remove_signature` function to +remove this command: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "remove-signature") }} + +## Code Injection with Shared Libraries + +As explained in the talk on format modification [^footnote-1], one way to inject code +into a program's memory space is to force the loader to load a library +(previously unlinked) that contains a constructor function. + +For a Mach-O binary, this can be achieved by adding one of these load commands: + +- {attr}`~lief.MachO.LoadCommand.TYPE.ID_DYLIB` + +- {attr}`~lief.MachO.LoadCommand.TYPE.LOAD_DYLIB` + +- ... + +Consider an example using `clang`. First, we create a small library that +defines a constructor: + +```cpp +#include +#include + +__attribute__((constructor)) +void my_constructor(void) { + printf("Hello World\n"); +} +``` + +This is compiled with: + +```console +$ clang -fPIC -shared libexample.c -o libexample.dylib +``` + +Then, we add a new {attr}`~lief.MachO.LoadCommand.TYPE.LOAD_DYLIB` using the +{meth}`lief.MachO.Binary.add_library` function: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "add-library") }} + +Finally, we run `clang.new` and observe that `Hello World` is printed +before the main execution of `clang`: + +```console +$ chmod u+x /tmp/clang.new + +$ /tmp/clang.new +Hello World +clang: error: no input files +``` + +We can also see the new {attr}`~lief.MachO.LoadCommand.TYPE.LOAD_DYLIB` command +using `otool`: + +```console +$ otool -l /tmp/clang.new|grep -C4 LOAD_DYLIB + +... +cmdsize 16 +dataoff 73864 +datasize 0 +Load command 16 + cmd LC_LOAD_DYLIB + cmdsize 56 + name /Users/romain/libexample.dylib (offset 24) + time stamp 2 Thu Jan 1 01:00:02 1970 + current version 0.0.0 +``` + +## Adding a Section/Segment + +Since we can allocate arbitrary space between the load command table and the +raw data, we can also extend an existing {class}`~lief.MachO.LoadCommand`. In +particular, Mach-O segments are commands associated with the LIEF object +{class}`lief.MachO.SegmentCommand`. + +To add a new section to the `__TEXT` segment, we must extend the load command +associated with that segment to accommodate a new section structure. We must +also reserve space for the section's content. Since the content of the +`__TEXT` segment begins at offset 0 and ends somewhere in the raw data, the +appropriate place to insert the new content is between the end of the load +command table and the beginning of the raw data: + +:::{figure} ../_static/tutorial/11/extendtxt.png +:align: center +::: + +The process described above is implemented via the +{meth}`lief.MachO.Binary.add_section` method. + +In this example, we will inject assembly code that executes `/bin/sh`: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "add-section") }} + +We can then change the entry point by setting the +{attr}`lief.MachO.MainCommand.entrypoint` attribute: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "set-entrypoint") }} + +Finally, we remove the signature and reconstruct the binary: + +{{ literalinclude("../../code/python/tuto_macho_mod.py", "remove-sig-write") }} + +The execution of `id.modified` should yield a similar output: + +```console +Mac-mini:tmp romain$ ./id.modified +tmp @ [romain] $ +``` + +You can also check other tools such as optool [^footnote-2] or insert_dylib [^footnote-3]. + +```{rubric} References +``` + +[^footnote-1]: + +[^footnote-2]: + +[^footnote-3]: + +```{rubric} API +``` + +- {meth}`lief.MachO.Binary.add_section` +- {meth}`lief.MachO.Binary.add_library` diff --git a/vendor/lief/doc/sphinx/tutorials/11_macho_modification.rst b/vendor/lief/doc/sphinx/tutorials/11_macho_modification.rst deleted file mode 100644 index e9b53ac..0000000 --- a/vendor/lief/doc/sphinx/tutorials/11_macho_modification.rst +++ /dev/null @@ -1,414 +0,0 @@ -11 - Mach-O Modification -------------------------- - -This tutorial deals with Mach-O format modification and introduces some internal aspects of the format. - -Files and scripts used in this tutorial are available on the `tutorials repository `_ - -By Romain Thomas - `@rh0main `_ - ------- - -Introduction -~~~~~~~~~~~~ - -A basic Mach-O binary (i.e. not FAT) can be represented in fours parts that are described in this diagram: - - -.. figure:: ../_static/tutorial/11/image1.png - :align: center - - -The first part begins with a header that can be accessed through the :attr:`lief.MachO.Binary.header` attribute. In the second part, we have the load commands table which can be iterated using :attr:`lief.MachO.Binary.load_commands` -then, we can optionally have padding or free space. Finally, we have the raw data (assembly code, rebase bytecode, signature, ...) - -Load commands like :class:`~lief.MachO.SegmentCommand` or :class:`~lief.MachO.DyldInfo` can be associated with *raw data* that are located after the load command table and the padding section. -The padding section is used by OSX to sign the binary after the compilation by adding a custom command. The ``codesign`` utility extends the *raw data* area with the signature and adds a ``LC_CODE_SIGNATURE`` or a ``LC_DYLIB_CODE_SIGN_DRS`` command in the padding area. - -Since load commands are the base unit of the Mach-O format -- segments, shared libraries, entry point, etc are somehow *commands* -- being able to add arbitrary commands in a binary -enables interesting like code injection, anti-analysis, ... - -Different techniques exist to add new command in a Mach-O binary: - -* One can replace an existing load command that is not mandatory for the execution like :class:`~lief.MachO.UUIDCommand` or :class:`~lief.MachO.CodeSignature`. -* One can use the padding area add to the command header. - -The main limitation of these techniques is that the size and the number of commands that can be added are tied to the padding section size or to the size of the command replaced. - -If the padding size is tiny, we can't add a ``LOAD_DYLIB`` command with a *very long* library path. Moreover ``codesign`` may complain that there are not enough spaces to add the ``LC_CODE_SIGNATURE`` since we are using the space that was reserved for it. - - -Next parts are about format modifications and how we managed to address this limitation. - -When PIE makes thing easier -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -OSX and iOS executables are by default compiled with flags that make them position independent. Instructions generated by the compiler will use -relative addressing associated with *rebase* information. - -To simplify (not accurate), PIE binaries enable to *map* the raw data section at a random base address. -The idea that is implemented in LIEF is that raw data section can be mapped at a random base address so it can also be shifted within the format. - - -.. figure:: ../_static/tutorial/11/image2.png - :align: center - - -Such transformation also requires to keep a consistent state of the format metadata. Especially, when we shift the raw data we need to update relocations, segment offsets, virtual address, etc. Once the raw data shifted and -the metadata updated, we have an arbitrary space between the load command table and the raw data section. Thus we can extend the load command table as shown in figure below: - - -.. figure:: ../_static/tutorial/11/image3.png - :align: center - - -.. warning:: - - The size of the shift must be aligned on a page size to avoid issues with section and segment alignments. - - -Keeping the format consistency after the shift transformation is not easy. The next part presents some parts of the Mach-O format that need to be updated in order to keep the consistency. - -When Mach-O makes thing harder -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -After the shift operation, we need to update several load commands of the Mach-O format: - -* :attr:`lief.MachO.SymbolCommand.symbol_offset` / :attr:`lief.MachO.SymbolCommand.strings_offset` -* :attr:`lief.MachO.DataInCode.data_offset`, :attr:`lief.MachO.CodeSignature.data_offset`, :attr:`lief.MachO.SegmentSplitInfo.data_offset` -* :attr:`lief.MachO.MainCommand.entrypoint` -* :attr:`lief.MachO.FunctionStarts.data_offset` / :attr:`lief.MachO.FunctionStarts.functions` -* :class:`~lief.MachO.DynamicSymbolCommand` -* :attr:`lief.MachO.Section.offset` / :attr:`lief.MachO.Section.virtual_address` -* :attr:`lief.MachO.SegmentCommand.offset` / :attr:`lief.MachO.SegmentCommand.virtual_address` -* ... - -We also need to update: - -* Relocations -* Binding information -* Export information - -Whereas ELF and PE formats use some kinds of ``struct`` for internal storage of relocations and exports, Mach-O format uses a bytecode to *rebase* the binary. Export information are stored in a `trie `_ data structure. The use of trie and bytecode reduces the binary size but it makes the update more difficult as we need to interpret and regenerate the bytecode. - -Rebase bytecode -*************** - -As mentioned in the previous part, recent Mach-O loader uses a bytecode to relocate (or rebase) the binary. -Offset and size of the bytecode are given in :attr:`lief.MachO.DyldInfo.rebase` attribute. Basically, bytecode is compound of :class:`~lief.MachO.REBASE_OPCODES` that define addresses to relocate. - -.. warning:: - - One can notice that :class:`~lief.MachO.Section` object has a :attr:`~lief.MachO.Section.relocation_offset` attribute. Actually, it seems to be only - used for Mach-O object files (:attr:`lief.MachO.FILE_TYPES.OBJECT`) or with an executable that uses an old version of the Mach-O loader. - - This offset points to a list of relocation structures (not bytecode) for which the number is defined by :attr:`~lief.MachO.Section.numberof_relocations`. - - -To know which addresses need to be relocated, we have to interpret the bytecode. - -The :attr:`lief.MachO.DyldInfo.show_rebases_opcodes` attribute returns the bytecode as *pseudo code*: - -.. code-block:: python - - import lief - app = lief.parse("MachO64_x86-64_binary_id.bin") - print(app.dyld_info.show_rebases_opcodes) - -.. code-block:: text - - [SET_TYPE_IMM] Type: POINTER - [SET_SEGMENT_AND_OFFSET_ULEB] Segment Index := 2 (__DATA) Segment Offset := 0x20 - [DO_REBASE_ULEB_TIMES] - for i in range(26): - rebase(POINTER, __DATA, 0x20) - Segment Offset += 0x8 (0x28) - - rebase(POINTER, __DATA, 0x28) - Segment Offset += 0x8 (0x30) - - rebase(POINTER, __DATA, 0x30) - Segment Offset += 0x8 (0x38) - - rebase(POINTER, __DATA, 0x38) - Segment Offset += 0x8 (0x40) - - rebase(POINTER, __DATA, 0x40) - Segment Offset += 0x8 (0x48) - ... - [DONE] - -From the above output, we can see that the loader will rebase **pointer** in the ``__DATA`` segment at offset ``0x20, 0x28, 0x38, ...``. - -For those who only care about which exact addresses are relocated, this output is not very user-friendly. LIEF also provides a **representation** of this bytecode by creating :class:`lief.MachO.Relocation` object. -They are the result of the **interpretation** of the bytecode. - -The :attr:`lief.MachO.Binary.relocations` attribute returns an iterator over :class:`lief.MachO.Relocation` objects that **model** a relocation in a similar object as :class:`lief.ELF.Relocation` and :class:`lief.PE.Relocation`. - -.. code-block:: python - - for relocation in app.relocations: - print(relocation) - -.. code-block:: text - - 100002020 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _err - 100002028 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _errx - 100002030 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _exit - 100002038 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _fprintf - 100002040 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _free - 100002048 POINTER 64 DYLDINFO __DATA.__la_symbol_ptr _fwrite - ... - -Using this representation, we can update relocations by adding the shift size to the :attr:`lief.MachO.Relocation.address` attribute. - -When the Mach-O builder reconstructs the final binary, it **regenerates** and optimize the rebase bytecode -according to the current state of the relocations. The process can be summed up with the following diagram: - -.. figure:: ../_static/tutorial/11/lief_bytecode.png - :align: center - -Binding bytecode -**************** - -The Mach-O loader also uses a bytecode to bind imported functions or imported symbols. Actually, this bytecode is used in three different binding methods: - -* Normal binding -* Weak binding -- Used when the same symbol is defined multiple times -* Lazy binding -- Bound only when there is an access to the symbol - -The bytecode can be pretty printed with the :attr:`~lief.MachO.DyldInfo.show_bind_opcodes`, :attr:`~lief.MachO.DyldInfo.show_weak_bind_opcodes` and :attr:`~lief.MachO.DyldInfo.show_lazy_bind_opcodes`: - -.. code-block:: python - - print(app.dyld_info.show_bind_opcodes) - -.. code-block:: text - - [SET_DYLIB_ORDINAL_IMM] - Library Ordinal := 1 - [SET_SYMBOL_TRAILING_FLAGS_IMM] - Symbol name := ___stderrp - Is Weak ? false - [SET_TYPE_IMM] - Type := POINTER - [SET_SEGMENT_AND_OFFSET_ULEB] - Segment := __DATA - Segment Offset := 0x10 - [DO_BIND] - bind(POINTER, __DATA, 0x10, ___stderrp, library_ordinal=/usr/lib/libSystem.B.dylib, addend=0, is_weak_import=false) - Segment Offset += 0x8 (0x18) - -The representation and the update process is the same as the one described in the section about *Rebase bytecode* - -Export Trie -*********** - -Regarding exported functions and exported symbols, Mach-O format uses a *trie* structure to store export information. Trie offset and size are given in the :attr:`~lief.MachO.DyldInfo.export_trie` attribute. - -Once parsed, trie entries are represented through the :class:`~lief.MachO.ExportInfo` object and can be retrieved with the :attr:`~lief.MachO.Symbol.export_info` attribute. - -.. code-block:: python - - app = lief.parse("FAT_MachO_x86_x86-64_library_libdyld.dylib") - print(app.dyld_info.show_export_trie) - -.. code-block:: text - - ... - _@off.0x17 - _N@off.0x21 - _NS@off.0x50 - _NSI@off.0x5d - _NSInstallLinkEditErrorHandlers@off.0x11d - _NSInstallLinkEditErrorHandlers{addr: 0x126b, flags: 0} - ... - -.. code-block:: python - - for s in app.symbols: - if s.has_export_info: - print(s.export_info) - -.. code-block:: text - - Node Offset: 128 - Flags: 0 - Address: 126b - Symbol: _NSInstallLinkEditErrorHandlers - - Node Offset: 5f6 - Flags: 0 - Address: 2168 - Symbol: _NSIsSymbolDefinedInObjectFileImage - - Node Offset: 1a0 - Flags: 0 - Address: 1391 - Symbol: _NSIsSymbolNameDefined - ... - -After the shift operation, export information are patched by updating the :attr:`~lief.MachO.ExportInfo.address` attribute, then a new export trie is generated from the previous updates. - - -Removing signature -~~~~~~~~~~~~~~~~~~ - -Removing the ``LC_CODE_SIGNATURE`` command is a basic modification that is pretty useful when modifying Mach-O file. Since the signature -checks the integrity of the binary, we usually need to remove this command after modification on the file. We can still re-sign the binary once all modifications finished. - -LIEF provides the :meth:`lief.MachO.Binary.remove_signature` function to remove this command: - -.. code-block:: python - - ssh = lief.parse("/usr/bin/ssh") - - ssh.remove_signature() - - ssh.write("ssh.nosigned") - -Code Injection with shared libraries -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -As explained in the talk about format modification [1]_, one way to inject code within the memory space of a program is to force the loader to load a library (that was not previously linked) that contains a constructor function. - -For a Mach-O binary, it can be achieved by adding one of these load commands: - -* :attr:`~lief.MachO.LOAD_COMMAND_TYPES.ID_DYLIB` -* :attr:`~lief.MachO.LOAD_COMMAND_TYPES.LOAD_DYLIB` -* ... - -Let's take an example with ``clang``. First, we need to create a tiny library which defines a constructor: - -.. code-block:: cpp - - #include - #include - - __attribute__((constructor)) - void my_constructor(void) { - printf("Hello World\n"); - } - -Which is complied with - -.. code-block:: console - - $ clang -fPIC -shared libexample.c -o libexample.dylib - -Then we add a new :attr:`~lief.MachO.LOAD_COMMAND_TYPES.LOAD_DYLIB` using the :meth:`lief.MachO.Binary.add_library` function: - -.. code-block:: python - - import lief - clang = lief.parse("/usr/bin/clang") - - clang.add_library("/Users/romain/libexample.dylib") - - clang.write("/tmp/clang.new") - -Finally, we run ``clang.new`` and see that ``Hello World`` is printed before the main execution of clang: - -.. code-block:: console - - $ chmod u+x /tmp/clang.new - - $ /tmp/clang.new - Hello World - clang: error: no input files - -We can also observe the new :attr:`~lief.MachO.LOAD_COMMAND_TYPES.LOAD_DYLIB` command with otool: - -.. code-block:: console - - $ otool -l /tmp/clang.new|grep -C4 LOAD_DYLIB - - ... - cmdsize 16 - dataoff 73864 - datasize 0 - Load command 16 - cmd LC_LOAD_DYLIB - cmdsize 56 - name /Users/romain/libexample.dylib (offset 24) - time stamp 2 Thu Jan 1 01:00:02 1970 - current version 0.0.0 - - - -Adding Section/Segment -~~~~~~~~~~~~~~~~~~~~~~ - -As we can allocate arbitrary space between the load command table and the raw data, we can also extend an existing :class:`~lief.MachO.LoadCommand`. -Especially, Mach-O segments are commands that are associated with the LIEF object :class:`lief.MachO.SegmentCommand`. - -To add a new section in the ``__TEXT`` segment, we must extend the load command associated with this segment so that we can add a new section structure. We must also reserve space for the content of the section. -As the content of the ``__TEXT`` segment begin at offset 0 and finish somewhere in the raw data, the right place to insert the new content is between the end of the load command table and the beginning of the raw data: - -.. figure:: ../_static/tutorial/11/extendtxt.png - :align: center - - -The process described above is implemented through the :meth:`lief.MachO.Binary.add_section` method. - -Here is an example in which we will inject assembly code that executes ``/bin/sh``: - -.. code-block:: python - - - app = lief.parse("MachO64_x86-64_binary_id.bin") - - raw_shell = [...] # Assembly code - section = lief.MachO.Section("__shell", raw_shell) - - section.alignment = 2 - section += lief.MachO.SECTION_FLAGS.SOME_INSTRUCTIONS - section += lief.MachO.SECTION_FLAGS.PURE_INSTRUCTIONS - - section = app.add_section(section) - print(section) - -Then we can change the entry point by setting the :attr:`lief.MachO.MainCommand.entrypoint` attribute: - -.. code-block:: python - - __TEXT = app.get_segment("__TEXT") - app.main_command.entrypoint = section.virtual_address - __TEXT.virtual_address - -Finally, we remove the signature and reconstruct the binary: - -.. code-block:: python - - app.remove_signature() - app.write("./id.modified") - -The execution of ``id.modified`` should give a similar output: - -.. code-block:: console - - Mac-mini:tmp romain$ ./id.modified - tmp @ [romain] $ - -You can also check other tools such as optool [2]_ or insert_dylib [3]_ - -.. rubric:: References - -.. [1] http://romainthomas.fr/slides/18-06-Recon18-Formats-Instrumentation.pdf - -.. [2] https://github.com/alexzielenski/optool - -.. [3] https://github.com/Tyilo/insert_dylib - -.. rubric:: API - -* :meth:`lief.MachO.Binary.add_section` -* :meth:`lief.MachO.Binary.add_library` - - - - - - - - - diff --git a/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.md b/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.md new file mode 100644 index 0000000..51a0aa4 --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.md @@ -0,0 +1,158 @@ +# 12 - ELF Coredump + +This tutorial introduces the API for analyzing and manipulating ELF coredumps. + +______________________________________________________________________ + +## Introduction + +ELF core [^footnote-1] files provide information about the CPU state and memory state of +a program at the time the coredump was generated. The memory state includes a +*snapshot* of all segments mapped into the process's memory space. The CPU +state contains register values from when the core dump was generated. + +Coredump files use a subset of ELF structures to store this information. +**Segments** are used for the memory state of the process, while ELF notes +({class}`lief.ELF.Note`) are used for process metadata (PID, signal, etc.). +Notably, the CPU state is stored in a note with a specific type. + +Here is an overview of the coredump layout: + +:::{figure} ../_static/tutorial/12/elf_notes.png +:align: center +::: + +For more details about coredump internal structures, refer to the following +blog post: [Anatomy of an ELF core file](https://www.gabriel.urdhr.fr/2015/05/29/core-file/). + +## Coredump Analysis + +Since core files are effectively ELF files, they can be opened using the +{sub-ref}`lief-abstract-parse` function: + +{{ literalinclude("../../code/python/tuto_coredump.py", "parse-core", prepend="import lief") }} + +We can iterate over the {class}`~lief.ELF.Segment` objects to inspect the +memory state of the program: + +{{ literalinclude("../../code/python/tuto_coredump.py", "segments") }} + +To resolve the relationship between libraries and segments, we can examine the +special note {class}`lief.ELF.CoreFile`: + +{{ literalinclude("../../code/python/tuto_coredump.py", "get-corefile") }} + +ELF notes are represented via the main {class}`lief.ELF.Note` interface. Some +notes, such as {class}`lief.ELF.CoreFile`, expose additional APIs by extending +the original {class}`lief.ELF.Note`. + +```{eval-rst} +.. lief-inheritance:: lief._lief.ELF.Note + :top-classes: lief._lief.ELF.Note + :depth: 1 + :parts: 1 +``` + +:::{note} +All note details inherit from the base class {class}`lief.ELF.Note` +(or {cpp:class}`LIEF::ELF::Note`). + +Specifically, in C++, we must downcast using the {title-reference}`classof` function: + +{{ literalinclude("../../code/cpp/tuto_coredump.cpp", "corefile-downcast") }} + +This is roughly equivalent in Python to: + +{{ literalinclude("../../code/python/tuto_coredump.py", "corefile-check") }} +::: + +We can use the {attr}`lief.ELF.CoreFile.files` attribute or iterate directly +over the {class}`lief.ELF.CoreFile` object. Both provide access to +{class}`lief.ELF.CoreFileEntry` objects: + +{{ literalinclude("../../code/python/tuto_coredump.py", "iter-files") }} + +```text +/data/local/tmp/hello-exe: [0x5580b86000, 0x5580b88000]@0 +/data/local/tmp/hello-exe: [0x5580b97000, 0x5580b98000]@0x1000 +/data/local/tmp/hello-exe: [0x5580b98000, 0x5580b99000]@0x2000 +/system/lib64/libcutils.so: [0x7fb7593000, 0x7fb7595000]@0xf000 +/system/lib64/libcutils.so: [0x7fb7595000, 0x7fb7596000]@0x11000 +/system/lib64/libnetd_client.so: [0x7fb75fb000, 0x7fb75fc000]@0x2000 +/system/lib64/libnetd_client.so: [0x7fb75fc000, 0x7fb75fd000]@0x3000 +/system/lib64/libdl.so: [0x7fb7a2e000, 0x7fb7a2f000]@0x1000 +/system/lib64/libdl.so: [0x7fb7a2f000, 0x7fb7a30000]@0x2000 +/data/local/tmp/liblibhello.so: [0x7fb7b22000, 0x7fb7b2a000]@0xcb000 +/data/local/tmp/liblibhello.so: [0x7fb7b2a000, 0x7fb7b2b000]@0xd3000 +/system/lib64/libc.so: [0x7fb7c0e000, 0x7fb7c14000]@0xc5000 +/system/lib64/libc.so: [0x7fb7c14000, 0x7fb7c16000]@0xcb000 +/system/lib64/liblog.so: [0x7fb7c6c000, 0x7fb7c6d000]@0x16000 +/system/lib64/liblog.so: [0x7fb7c6d000, 0x7fb7c6e000]@0x17000 +/system/lib64/libc++.so: [0x7fb7d6f000, 0x7fb7d77000]@0xe2000 +/system/lib64/libc++.so: [0x7fb7d77000, 0x7fb7d78000]@0xea000 +/system/lib64/libm.so: [0x7fb7db8000, 0x7fb7db9000]@0x36000 +/system/lib64/libm.so: [0x7fb7db9000, 0x7fb7dba000]@0x37000 +/system/bin/linker64: [0x7fb7e93000, 0x7fb7f87000]@0 +/system/bin/linker64: [0x7fb7f88000, 0x7fb7f8c000]@0xf4000 +/system/bin/linker64: [0x7fb7f8c000, 0x7fb7f8d000]@0xf8000 +``` + +From this output, we can see that the {class}`~lief.ELF.Segment` entries of the +main executable (`/data/local/tmp/hello-exe`) are mapped from address +`0x5580b86000` to `0x5580b99000`. + +The register state can also be accessed by looking for the +{class}`lief.ELF.CorePrStatus` note: + +{{ literalinclude("../../code/python/tuto_coredump.py", "registers") }} + +```text +0x5580b86f50 +0x5580b86f50 +``` + +## Coredump Manipulation + +To a certain extent, LIEF enables the modification of coredumps. For instance, +we can update register values as follows: + +{{ literalinclude("../../code/python/tuto_coredump.py", "set-register") }} + +When opening `/tmp/new.core` in GDB, we can observe the modification: + +:::{figure} ../_static/tutorial/12/gdb.png +:align: center +::: + +## Final word + +One advantage of a coredump over a raw binary is that **relocations** and +**dependencies** are already resolved within the coredump. + +This API can be used in conjunction with other tools. For example, we could use +the [Triton](https://triton.quarkslab.com/) API: + +- [AArch64Cpu::setConcreteRegisterValue()](https://github.com/JonathanSalwan/Triton/blob/a61651ce331ac53ec09e1d8fef5eab744e98c9de/src/libtriton/arch/architecture.cpp#L343) +- [AArch64Cpu::setConcreteMemoryAreaValue()](https://github.com/JonathanSalwan/Triton/blob/a61651ce331ac53ec09e1d8fef5eab744e98c9de/src/libtriton/arch/architecture.cpp#L329-L340) + +to map the coredump into Triton and then use its engines for taint +analysis and symbolic execution. + +```{rubric} References +``` + +[^footnote-1]: + +```{rubric} API +``` + +- {func}`lief.parse` +- {class}`lief.ELF.Note` +- {class}`lief.ELF.CorePrPsInfo` +- {class}`lief.ELF.CorePrStatus` +- {class}`lief.ELF.CoreFile` +- {class}`lief.ELF.CoreFileEntry` +- {class}`lief.ELF.CoreSigInfo` +- {class}`lief.ELF.CoreAuxv` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.rst b/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.rst deleted file mode 100644 index 4c10212..0000000 --- a/vendor/lief/doc/sphinx/tutorials/12_elf_coredump.rst +++ /dev/null @@ -1,192 +0,0 @@ -12 - ELF Coredump ------------------ - -This tutorial introduces the API to analyze and manipulate ELF coredump - -Files and scripts used in this tutorial are available on the `tutorials repository `_ - ------- - -Introduction -~~~~~~~~~~~~ - -ELF core [1]_ files provide information about the CPU state and the memory state of a program when the coredump -has been generated. The memory state embeds -a *snapshot* of all segments mapped in the memory space of the program. The CPU state contains register values -when the core dump has been generated. - -Coredump files use a subset of the ELF structures to register these information. **Segments** are used for -the memory state of the process while ELF notes (:class:`lief.ELF.Note`) are used for process metadata (pid, signal, ...) -Especially, the CPU state is stored in a note with a special type. - - -Here is an overview of coredump layout : - -.. figure:: ../_static/tutorial/12/elf_notes.png - :align: center - - -For more details about coredump internal structure, one can look at the following blog post: `Anatomy of an ELF core file `_ - -Coredump Analysis -~~~~~~~~~~~~~~~~~ - -As corefiles are effectively ELF, we can open these files using the :func:`lief.parse` function: - -.. code-block:: python - - import lief - - core = lief.parse("ELF64_AArch64_core_hello.core") - -We can iterate over the :class:`~lief.ELF.Segment` objects to inspect the memory state of the program: - -.. code-block:: python - - segments = core.segments - print("Number of segments {}".format(len(segments))) - - for segment in segments: - print(hex(segment.virtual_address)) - -To resolve the relationship between libraries and segments, we can look at the special note :class:`lief.ELF.CoreFile`: - -.. code-block:: python - - note_file = [n for n in core.notes if n.type_core == lief.ELF.NOTE_TYPES_CORE.FILE] - assert len(note_file) == 1 - - note_file = note_file.pop() - -.. warning:: - - Due to enum conflict between :class:`lief.ELF.NOTE_TYPES` and :class:`lief.ELF.NOTE_TYPES_CORE`, - scripts must use :attr:`lief.ELF.Note.type_core` on ELF corefile instead of :attr:`lief.ELF.Note.type` - -The ``note_file`` variable is basically an object :class:`lief.ELF.Note` on which the attribute -:attr:`lief.ELF.Note.details` can be access to have the underlying specialization of the note. -In the case of a note type :attr:`lief.ELF.NOTE_TYPES_CORE.FILE`, the attribute :attr:`~lief.ELF.Note.details` returns an -instance of :class:`lief.ELF.CoreFile`. - -.. note:: - - All note details inherit from the base class :class:`lief.ELF.NoteDetails` (or :cpp:class:`LIEF::ELF::NoteDetails`) - - Especially, in C++ we must downcast the reference returned by :cpp:func:`LIEF::ELF::Note::details`: - - .. code-block:: cpp - - note = ... - // Check Type - // ... - const auto& note_file = reinterpret_cast(note.details()); - - - -We can eventually use the attribute :attr:`lief.ELF.CoreFile.files` or directly iterate on -the :class:`lief.ELF.CoreFile` object. Both give access to the :class:`lief.ELF.CoreFileEntry`: objects - -.. code-block:: python - - for file_entry in note_file: - print(file_entry) - -.. code-block:: text - - /data/local/tmp/hello-exe: [0x5580b86000, 0x5580b88000]@0 - /data/local/tmp/hello-exe: [0x5580b97000, 0x5580b98000]@0x1000 - /data/local/tmp/hello-exe: [0x5580b98000, 0x5580b99000]@0x2000 - /system/lib64/libcutils.so: [0x7fb7593000, 0x7fb7595000]@0xf000 - /system/lib64/libcutils.so: [0x7fb7595000, 0x7fb7596000]@0x11000 - /system/lib64/libnetd_client.so: [0x7fb75fb000, 0x7fb75fc000]@0x2000 - /system/lib64/libnetd_client.so: [0x7fb75fc000, 0x7fb75fd000]@0x3000 - /system/lib64/libdl.so: [0x7fb7a2e000, 0x7fb7a2f000]@0x1000 - /system/lib64/libdl.so: [0x7fb7a2f000, 0x7fb7a30000]@0x2000 - /data/local/tmp/liblibhello.so: [0x7fb7b22000, 0x7fb7b2a000]@0xcb000 - /data/local/tmp/liblibhello.so: [0x7fb7b2a000, 0x7fb7b2b000]@0xd3000 - /system/lib64/libc.so: [0x7fb7c0e000, 0x7fb7c14000]@0xc5000 - /system/lib64/libc.so: [0x7fb7c14000, 0x7fb7c16000]@0xcb000 - /system/lib64/liblog.so: [0x7fb7c6c000, 0x7fb7c6d000]@0x16000 - /system/lib64/liblog.so: [0x7fb7c6d000, 0x7fb7c6e000]@0x17000 - /system/lib64/libc++.so: [0x7fb7d6f000, 0x7fb7d77000]@0xe2000 - /system/lib64/libc++.so: [0x7fb7d77000, 0x7fb7d78000]@0xea000 - /system/lib64/libm.so: [0x7fb7db8000, 0x7fb7db9000]@0x36000 - /system/lib64/libm.so: [0x7fb7db9000, 0x7fb7dba000]@0x37000 - /system/bin/linker64: [0x7fb7e93000, 0x7fb7f87000]@0 - /system/bin/linker64: [0x7fb7f88000, 0x7fb7f8c000]@0xf4000 - /system/bin/linker64: [0x7fb7f8c000, 0x7fb7f8d000]@0xf8000 - -From this output, we can see that the :class:`~lief.ELF.Segment` of the main executable -(``/data/local/tmp/hello-exe``), are mapped from address ``0x5580b86000`` to address ``0x5580b99000``. - -One can also access to the registers state by using the note for which the :attr:`~lief.ELF.Note.type_core` -is :class:`lief.ELF.CorePrStatus`. - -.. code-block:: python - - for note in core.notes: - if note.type_core == lief.ELF.NOTE_TYPES_CORE.PRSTATUS: - details = note.details - print(details) - - # Print instruction pointer - print(hex(details[lief.ELF.CorePrStatus.REGISTERS.AARCH64_PC])) - # or - print(hex(details.get(lief.ELF.CorePrStatus.REGISTERS.AARCH64_PC))) - -.. code-block:: text - - 0x5580b86f50 - 0x5580b86f50 - - -Coredump manipulation -~~~~~~~~~~~~~~~~~~~~~ - -LIEF enables, to a certain extent, to modify coredump. For instance, -we can update the register values as follows: - -.. code-block:: python - - note_prstatus = [n for n in core.notes if n.type_core == lief.ELF.NOTE_TYPES_CORE.PRSTATUS][0] - note_prstatus.details[lief.ELF.CorePrStatus.REGISTERS.AARCH64_PC] = 0xDEADC0DE - - core.write("/tmp/new.core") - -When opening ``/tmp/new.core`` in GDB, we can observe the modification: - -.. figure:: ../_static/tutorial/12/gdb.png - :align: center - -Final word -~~~~~~~~~~ - -One advantage of the coredump over the raw binary -is that **relocations** and **dependencies** are resolved inside the coredump. - -This API could be used in association with other tools. For instance, we could use `Triton `_ API: - -- `AArch64Cpu::setConcreteRegisterValue() `_ -- `AArch64Cpu::setConcreteMemoryAreaValue() `_ - -to map the coredump in Triton and then use its engines: Taint analysis, symbolic execution. - - -.. rubric:: References - -.. [1] https://www.gabriel.urdhr.fr/2015/05/29/core-file/ - - - -.. rubric:: API - -* :func:`lief.parse` -* :attr:`lief.ELF.Note.details` - -* :class:`lief.ELF.CorePrPsInfo` -* :class:`lief.ELF.CorePrStatus` -* :class:`lief.ELF.CoreFile` -* :class:`lief.ELF.CoreFileEntry` -* :class:`lief.ELF.CoreSigInfo` -* :class:`lief.ELF.CoreAuxv` - diff --git a/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.md b/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.md new file mode 100644 index 0000000..8d2bb3e --- /dev/null +++ b/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.md @@ -0,0 +1,458 @@ +(pe-authenticode)= + +# 13 - PE Authenticode + +This tutorial explains how to process and verify PE Authenticode with LIEF. + +______________________________________________________________________ + +## Introduction + +PE Authenticode is the signature scheme used by Windows to sign and verify the +integrity of PE executables. The signature is associated with the +{attr}`~lief.PE.DataDirectory.TYPES.CERTIFICATE_TABLE` data directory, which is +not always tied to a section (implying that the signature is not necessarily +mapped into memory). In fact, the data directory entry points to a file offset, +not an RVA. This signature is wrapped in a PKCS #7 container with custom object +types, as defined in the official documentation [^footnote-1]. + +Parsing these signatures has been a goal since LIEF's inception. Before +version {ref}`v0.11.0 `, the implementation was incomplete and +sometimes inaccurate. Since version {ref}`v0.11.0 `, and thanks +to sponsorship from the [CERT Gouvernemental of Luxembourg](https://www.govcert.lu/en/), +we have refactored the Authenticode parser [^footnote-2] and implemented signature +verification functions. + +## Exploring the PKCS #7 Signature + +The LIEF API exposes most internal components of the PKCS #7 container +associated with Authenticode. First, we can access the PE signatures through +the {sub-ref}`lief-pe-binary-signatures` attribute [^footnote-3]: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "signatures") }} + +Although we usually find only **one** signature, PE executables can embed +multiple signatures using the `/as` command of `signtool.exe`. This is why +the {attr}`~lief.PE.Binary.signatures` attribute returns an **iterator** over +the signatures parsed by LIEF. + +The {class}`signature ` variable is a +{sub-ref}`lief-pe-signature` object, which mirrors the PKCS #7 container and +includes methods for verifying its integrity. + +Within this object, we can access the following attributes: + +- {class}`~lief.PE.x509` certificates used to sign the executable: {attr}`lief.PE.Signature.certificates` + +- The {class}`~lief.PE.ContentInfo` object containing the authentihash: {attr}`lief.PE.ContentInfo.digest` + +- The {class}`~lief.PE.SignerInfo` structures: {attr}`lief.PE.Signature.signers` + + :::{note} + While the PKCS #7 standard supports multiple signers, Microsoft + specifications require **exactly one** signer. + ::: + +The `__str__()` methods of these objects are overloaded to facilitate +pretty-printing their content: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "signature-info") }} + +```text +cert. version : 3 +serial number : 04:09:18:1B:5F:D5:BB:66:75:53:43:B5:6F:95:50:08 +issuer name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA +subject name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA +issued on : 2013-10-22 12:00:00 +expires on : 2028-10-22 12:00:00 +signed using : RSA with SHA-256 +RSA key size : 2048 bits +basic constraints : CA=true, max_pathlen=0 +key usage : Digital Signature, Key Cert Sign, CRL Sign +ext key usage : Code Signing + +cert. version : 3 +serial number : 09:70:EF:4B:AD:5C:C4:4A:1C:2B:C3:D9:64:01:67:4C +issuer name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA +subject name : C=CZ, L=Praha, O=Avast Software s.r.o., OU=RE stapler cistodc, CN=Avast Software s.r.o. +issued on : 2020-04-02 00:00:00 +expires on : 2023-03-09 12:00:00 +signed using : RSA with SHA-256 +RSA key size : 2048 bits +basic constraints : CA=false +key usage : Digital Signature +ext key usage : Code Signing + +a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 +SHA_256/RSA - C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - 4 auth attr - 1 unauth attr +``` + +For PE files, the authentihash is computed using the +{meth}`lief.PE.Binary.authentihash` function, which takes a +{class}`lief.PE.ALGORITHMS` enum as a parameter to define the hash algorithm. + +For instance, to compute the SHA-256 authentihash, pass +{attr}`lief.PE.ALGORITHMS.SHA_256`: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "authentihash") }} + +```text +a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 +``` + +:::{note} +To compare the {meth}`lief.PE.Binary.authentihash` value with the signed one +(i.e., {attr}`lief.PE.ContentInfo.digest`), you must use the same hash +algorithm as defined by {attr}`lief.PE.Signature.digest_algorithm`. +::: + +We also provide shortcut attributes in the Python API to compute authentihash +values: + +| Hash Algorithm | Binary Attribute | +| -------------- | ------------------------------------------- | +| MD5 | {attr}`~lief.PE.Binary.authentihash_md5` | +| SHA1 | {attr}`~lief.PE.Binary.authentihash_sha1` | +| SHA-256 | {attr}`~lief.PE.Binary.authentihash_sha256` | +| SHA-512 | {attr}`~lief.PE.Binary.authentihash_sha512` | + +LIEF also exposes the original raw signature blob via the +{attr}`lief.PE.Signature.raw_der` property, which allows for exporting the +signature: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "raw-der") }} + +Then, you can use `openssl` to process its content: + +```text +$ openssl pkcs7 -inform der -print -in /tmp/extracted.p7b -noout -text +... + sig_alg: + algorithm: sha256WithRSAEncryption (1.2.840.113549.1.1.11) + parameter: NULL + signature: (0 unused bits) + 0000 - 31 c3 a7 f3 70 e3 2c 49-15 bd f4 09 6c 27 4e 1...p.,I....l'N + 000f - 00 a9 23 df cb ea 7f 99-55 cb 24 88 75 e8 c4 ..#.....U.$.u.. + 001e - de 48 4f 70 dd 2a 27 5c-df be 36 f6 84 0d ad .HOp.*'\..6.... + 002d - 35 5e 65 f7 af 55 01 7a-2d 01 18 a0 d6 98 a4 5^e..U.z-...... + 003c - d1 bd 19 e9 a4 03 f4 a3-4d 12 6e 72 5f 6b 3a ........M.nr_k: + 004b - b8 de 45 f1 63 80 b0 47-42 f6 38 b8 e7 5b dd ..E.c..GB.8..[. + 005a - cf f2 f8 c2 61 4b 2c 19-b7 7d 78 8f 2e 0c b0 ....aK,..}x.... + 0069 - 7c f2 d9 8e 9f 65 4e 21-63 19 6a 5b 0c 91 12 |....eN!c.j[... + 0078 - 44 29 fe 91 d5 6f 5d 9c-4d 7b a1 74 c6 69 d9 D)...o].M{.t.i. + 0087 - e7 23 26 54 35 5c 38 33-c5 a7 92 0d 70 a5 2a .#&T5\83....p.* + 0096 - 33 77 4a fc 86 b0 fa 59-2f 24 f6 a1 45 b2 09 3wJ....Y/$..E.. + 00a5 - 75 2d a1 81 68 e4 67 11-46 e3 fb bf 0c c5 d5 u-..h.g.F...... + 00b4 - d7 7b 7b 35 fb d6 e8 4a-c9 13 82 82 a7 0c 3e .{{5...J......> + 00c3 - 6f 61 e0 37 15 e0 37 5d-b8 22 14 ad 54 58 0e oa.7..7]."..TX. + 00d2 - 95 6c 2b b1 d2 c7 6c 86-a1 9f fa d8 37 ca f7 .l+...l.....7.. + 00e1 - 56 75 b0 9d df 7c 46 43-20 87 8a a3 81 47 82 Vu...|FC ....G. + 00f0 - 99 57 87 12 46 96 02 7c-a7 77 b9 42 4d c8 05 .W..F..|.w.BM.. + 00ff - 0a . + crl: + + signer_info: + version: 1 + issuer_and_serial: + issuer: C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA + serial: 12549442701880659695003200114191853388 + digest_alg: + algorithm: sha256 (2.16.840.1.101.3.4.2.1) + parameter: NULL + auth_attr: + object: contentType (1.2.840.113549.1.9.3) + set: + OBJECT:undefined (1.3.6.1.4.1.311.2.1.4) + + object: undefined (1.3.6.1.4.1.311.2.1.11) +``` + +The [pe_authenticode_reader.py](https://github.com/lief-project/LIEF/blob/main/api/python/examples/pe_authenticode_reader.py) +script in the [examples/](https://github.com/lief-project/LIEF/tree/main/api/python/examples) directory +can also be used to inspect the signature: + +```console +$ python pe_authenticode_reader.py --all avast_free_antivirus_setup_online.exe +``` + +```text +Signature version : 1 +Digest Algorithm : ALGORITHMS.SHA_256 +Content Info: + Content Type : 1.3.6.1.4.1.311.2.1.4 (SPC_INDIRECT_DATA_CONTENT) + Digest Algorithm: ALGORITHMS.SHA_256 + Digest : a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 +Certificates + Version : 3 + Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA + Subject : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA + Serial Number : 0409181b5fd5bb66755343b56f955008 + Signature Algorithm: SHA256_WITH_RSA_ENCRYPTION + Valid from : 2013/10/22 - 12:00:00 + Valid to : 2028/10/22 - 12:00:00 + Key usage : CRL_SIGN - KEY_CERT_SIGN - DIGITAL_SIGNATURE + Ext key usage : CODE_SIGNING + RSA key size : 2048 + =========================================== + Version : 3 + Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA + Subject : C=CZ, L=Praha, O=Avast Software s.r.o., OU=RE stapler cistodc, CN=Avast Software s.r.o. + Serial Number : 0970ef4bad5cc44a1c2bc3d96401674c + Signature Algorithm: SHA256_WITH_RSA_ENCRYPTION + Valid from : 2020/04/02 - 00:00:00 + Valid to : 2023/03/09 - 12:00:00 + Key usage : DIGITAL_SIGNATURE + Ext key usage : CODE_SIGNING + RSA key size : 2048 + =========================================== +Signer(s) + Version : 1 + Serial Number : 0970ef4bad5cc44a1c2bc3d96401674c + Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA + Digest Algorithm : ALGORITHMS.SHA_256 + Encryption Algorithm: ALGORITHMS.RSA + Encrypted Digest : 758db1f480eb25bada6c ... + Authenticated attributes: + Content Type OID: 1.3.6.1.4.1.311.2.1.4 (SPC_INDIRECT_DATA_CONTENT) + MS Statement type OID: 1.3.6.1.4.1.311.2.1.21 (INDIVIDUAL_CODE_SIGNING) + Info: http://www.avast.com + PKCS9 Message Digest: 3983816a7d1c62962540ec66fa8790fa45d1063cb23e933677de459f0b73c577 + Un-authenticated attributes: + Generic Type 1.3.6.1.4.1.311.3.3.1 (MS_COUNTER_SIGN) +``` + +## Verifying the Signature + +In addition to parsing Authenticode signatures, LIEF can also verify the +integrity of the authentihash using the +{sub-ref}`lief-pe-binary-verify_signature` method. This method returns +{attr}`lief.PE.Signature.VERIFICATION_FLAGS.OK` if the signature is valid, or +another enum value if it is invalid (see: +{attr}`lief.PE.Signature.VERIFICATION_FLAGS`): + +{{ literalinclude("../../code/python/tuto_authenticode.py", "verify") }} + +You can also verify a PE binary with a **detached signature** by providing a +{class}`signature ` object to +{meth}`~lief.PE.Binary.verify_signature`: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "verify-detached", emphasize_lines="1,4") }} + +The verification process does not rely on external components (i.e., neither +OpenSSL nor the WinTrust API). Instead, we attempt to reproduce the same checks +described in the RFCs and official Authenticode documentation [^footnote-4]. + +These checks include: + +```{eval-rst} +A. Verifying the integrity of the signature (:meth:`lief.PE.Signature.check()`): + + 1. Ensuring there is exactly one :class:`~lief.PE.SignerInfo` structure. + 2. Confirming that digest algorithms are consistent + (:attr:`Signature.digest_algorithm ` ``==`` :attr:`ContentInfo.digest_algorithm ` ``==`` :attr:`SignerInfo.digest_algorithm `). + 3. If :class:`~lief.PE.SignerInfo` has authenticated attributes, verifying + their integrity. Otherwise, verifying the integrity of the + :class:`~lief.PE.ContentInfo` against the signer's certificate. + 4. If authenticated attributes exist, confirming the presence of a + :class:`lief.PE.PKCS9MessageDigest` attribute whose + :attr:`~lief.PE.PKCS9MessageDigest.digest` matches the hash of the + :class:`~lief.PE.ContentInfo`. + 5. If a countersignature exists in the **unauthenticated attributes**, + verifying its integrity and ensuring it includes a valid *timestamp*. + 6. Checking certificate expiration relative to any *timestamp*. + +B. If the signature is valid, confirming that :attr:`lief.PE.ContentInfo.digest` + matches the computed :meth:`~lief.PE.Binary.authentihash`. +``` + +These checks represent the default behavior of +{meth}`~lief.PE.Binary.verify_signature`. You can, however, pass +{class}`lief.PE.Signature.VERIFICATION_CHECKS` flags to customize this +behavior: + +```{eval-rst} + +:Hash Only: + + Using :attr:`VERIFICATION_CHECKS.HASH_ONLY ` + only performs step ``B)`` (i.e., checks the authentihash values regardless + of signature integrity). + + .. literalinclude:: ../../code/python/tuto_authenticode.py + :language: python + :start-after: lief-doc: verify-hash-only-start + :end-before: lief-doc: verify-hash-only-end + :dedent: + + +:Lifetime Signing: + + Using :attr:`VERIFICATION_CHECKS.LIFETIME_SIGNING ` + allows timestamped signatures to expire if their certificate has expired. + This corresponds to `WTD_LIFETIME_SIGNING_FLAG `_. + + .. literalinclude:: ../../code/python/tuto_authenticode.py + :language: python + :start-after: lief-doc: verify-lifetime-start + :end-before: lief-doc: verify-lifetime-end + :dedent: + + +:Skip Certificate Time Check: + + Using :attr:`VERIFICATION_CHECKS.SKIP_CERT_TIME ` + prevents LIEF from raising an error if certificates have expired. + + .. literalinclude:: ../../code/python/tuto_authenticode.py + :language: python + :start-after: lief-doc: verify-skip-cert-time-start + :end-before: lief-doc: verify-skip-cert-time-end + :dedent: +``` + +:::{note} +To verify the integrity of a {class}`~lief.PE.Signature` object, you can use +{sub-ref}`lief-pe-signature-check`. +::: + +## Certificate Chain of Trust + +Finally, the certificate chain can be verified using: + +1. {meth}`lief.PE.x509.verify` +2. {meth}`lief.PE.x509.is_trusted_by` + +{meth}`~lief.PE.x509.verify` is used to verify a signed certificate against its +CA. Given a CA {class}`~lief.PE.x509` certificate, `CA.verify(signed)` +confirms that the `signed` parameter was indeed signed by `CA`. + +Alternatively, {meth}`~lief.PE.x509.is_trusted_by` checks whether a given +{class}`~lief.PE.x509` certificate can be verified against a **list of +certificates**: + +{{ literalinclude("../../code/python/tuto_authenticode.py", "is-trusted-bundle") }} + +{{ literalinclude("../../code/python/tuto_authenticode.py", "is-trusted-list") }} + +## Limitations + +Regarding the PKCS #7 structure, LIEF can parse and process most of its +elements. However, the {class}`lief.PE.SignerInfo` structure can embed +attributes (authenticated or otherwise) whose ASN.1 structure may or may not +be public. As of LIEF v0.11.0, the following OIDs are not yet supported: + +| OID | Description | +| -------------------------- | ------------------------------------------------------------ | +| 1.3.6.1.4.1.311.3.3.1 | Ms-CounterSign (undocumented, supported in LIEF 0.15.0) | +| 1.2.840.113549.1.9.16.2.12 | S/MIME Signing certificate (id-aa-signingCertificate) | +| 1.3.6.1.4.1.311.2.6.1 | SPC_COMMERCIAL_SP_KEY_PURPOSE_OBJID | +| 1.3.6.1.4.1.311.10.3.28 | szOID_PLATFORM_MANIFEST_BINARY_ID (supported in LIEF 0.15.0) | + +These unsupported attributes are wrapped in the {class}`lief.PE.GenericType`, +which exposes the raw ASN.1 blob via the {attr}`~lief.PE.GenericType.raw_content` +property. + +## Conclusion + +Under the hood, most of the work is performed by +[mbedtls](https://github.com/Mbed-TLS/mbedtls), which provides the following +primitives used by LIEF: + +- ASN.1 decoder +- x509 certificate processing (parsing AND verification) +- Hash algorithms +- Public key algorithms + +A small C++ snippet can also be cross-compiled for iOS: + +{{ literalinclude("../../code/cpp/tuto_authenticode.cpp", "ios-main") }} + +This allows for verifying the integrity of a PE executable on an iPhone: + +```console +iPhone:~ root# file PE32_x86-64_binary_avast-free-antivirus-setup-online.exe +PE32_x86-64_binary_avast-free-antivirus-setup-online.exe: PE32 executable (GUI) Intel 80386, for MS Windows +iPhone:~ root# file ./pe_authenticode_check +./pe_authenticode_check: Mach-O 64-bit arm64 executable, flags: +iPhone:~ root# ./pe_authenticode_check PE32_x86-64_binary_avast-free-antivirus-setup-online.exe +Signature ok! +iPhone:~ root# +``` + +While this example may seem niche, it highlights the project's purpose: + +- Providing a cross-platform and cross-format library. +- Exposing both a high-level API (Python) and a low-level API (C++). +- Minimizing dependencies so that the static version of LIEF does not require external libraries [^footnote-5]. + +```console +$ otool -L pe_authenticode_check + +/System/Library/Frameworks/Foundation.framework/Foundation (compatibility version 300.0.0, current version 1770.255.0) +/usr/lib/libobjc.A.dylib (compatibility version 1.0.0, current version 228.0.0) +/usr/lib/libc++.1.dylib (compatibility version 1.0.0, current version 904.4.0) +/usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1292.60.1) +``` + +In addition to LIEF, you may be interested in other projects that handle +Authenticode: + +| Project | URL | +| ---------------- | ------------------------------------------------------------------------------ | +| signify | | +| winsign | | +| uthenticode | | +| AuthenticodeLint | | +| osslsigncode | | +| yara-x | (which has support for PE Authenticode) | + +Finally, additional information about Authenticode can be found in the Trail of +Bits blog post [^footnote-6]. For Authenticode techniques used by Dropbox, refer to the +Microsoft website [^footnote-7]. If you are interested in how PKCS #7 integrity works, +refer to *Manually verify PKCS#7 signed data with OpenSSL* [^footnote-8]. + +```{rubric} References +``` + +[^footnote-1]: + +[^footnote-2]: Which is now exception-free. + +[^footnote-3]: This tutorial uses the Python API, but the C++ API is very similar. + +[^footnote-4]: See [src/PE/signature/Signature.cpp - check()](https://github.com/lief-project/LIEF/tree/master/src/PE/signature/Signature.cpp) for the implementation. + +[^footnote-5]: Except for the C/C++ STL. + +[^footnote-6]: + +[^footnote-7]: + +[^footnote-8]: + +```{rubric} API +``` + +- {sub-ref}`lief-pe-binary-verify_signature` +- {meth}`lief.PE.Binary.authentihash` +- {attr}`lief.PE.Binary.authentihash_md5` +- {attr}`lief.PE.Binary.authentihash_sha1` +- {attr}`lief.PE.Binary.authentihash_sha256` +- {attr}`lief.PE.Binary.authentihash_sha512` +- {sub-ref}`lief-pe-binary-signatures` +- {sub-ref}`lief-pe-signature` +- {class}`lief.PE.x509` +- {class}`lief.PE.ContentInfo` +- {class}`lief.PE.SignerInfo` +- {class}`lief.PE.Attribute` +- {class}`lief.PE.ContentType` +- {class}`lief.PE.GenericType` +- {class}`lief.PE.MsSpcNestedSignature` +- {class}`lief.PE.MsSpcStatementType` +- {class}`lief.PE.PKCS9AtSequenceNumber` +- {class}`lief.PE.PKCS9CounterSignature` +- {class}`lief.PE.PKCS9MessageDigest` +- {class}`lief.PE.PKCS9SigningTime` +- {class}`lief.PE.SpcSpOpusInfo` + +{{ cross_api }} diff --git a/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.rst b/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.rst deleted file mode 100644 index de28cd2..0000000 --- a/vendor/lief/doc/sphinx/tutorials/13_pe_authenticode.rst +++ /dev/null @@ -1,502 +0,0 @@ -13 - PE Authenticode --------------------- - -This tutorial explains how to process and verify PE authenticode with LIEF - -By Romain Thomas - `@rh0main `_ - ------- - -Introduction -~~~~~~~~~~~~ - -PE authenticode is the signature scheme used by Windows to sign and verify the integrity of PE executables. -The signature is associated with the data directory :attr:`~lief.PE.DATA_DIRECTORY.CERTIFICATE_TABLE` -that is not always tied to a section (it implies that the signature is not necessarily mapped in memory). -This signature is wrapped in a PKCS #7 container with custom object types as defined -in the official documentation [#]_. - -This signature is not new in PE files and since the beginning of LIEF, we aimed to parse it. -Before the version :ref:`v0.11.0 `, the implementation was somehow incomplete and inaccurate but -since the version :ref:`v0.11.0 ` and thanks to the sponsoring of the `CERT Gouvernemental of Luxembourg `_, -we refactored the design of the authenticode parser [#]_ and we implemented functions to verify the signature. - - -Exploring PKCS #7 Signature -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -LIEF API tries to expose most of the internal components of the PKCS #7 container associated with the -Aunthenticode. -First, we can access the PE's signature through the :attr:`lief.PE.Binary.signatures` attribute -[#]_: - -.. code-block:: python - - import lief - pe = lief.parse("avast_free_antivirus_setup_online.exe") - print(len(pe.signatures)) - - signature = pe.signatures[0] - -Although we usually find only **one** signature, PE executables can embed multiple signatures thanks to -the ``/as`` command of ``signtool.exe``. This is why the :attr:`~lief.PE.Binary.signatures` attribute returns an -**iterator** over the signatures parsed by LIEF. - -The :class:`signature ` variable is actually a :class:`lief.PE.Signature` object which basically -mirrors the PKCS #7 container plus some method to verify its integrity. - -Within this object, we can access the following attributes: - -* :class:`~lief.PE.x509` certificates used to sign the executable: :attr:`lief.PE.Signature.certificates` -* The :class:`~lief.PE.ContentInfo` object that contains the authentihash value: :attr:`lief.PE.ContentInfo.digest` -* The :class:`~lief.PE.SignerInfo` structure: :attr:`lief.PE.Signature.signers` - - .. note:: - - While the PKCS #7 standard enables multiple signers, Microsoft specifications require **one** and **only one** - signer. - -The ``__str__()`` functions of these objects are overloaded so that we can pretty-print the content of these objects easily: - -.. code-block:: python - - # Print certificates information - for crt in signature.certificates: - print(crt) - - # Print the authentihash value embedded in the signature - print(signature.content_info.digest.hex()) - - # Print signer information - print(signature.signers[0]) - -.. code-block:: text - - cert. version : 3 - serial number : 04:09:18:1B:5F:D5:BB:66:75:53:43:B5:6F:95:50:08 - issuer name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA - subject name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - issued on : 2013-10-22 12:00:00 - expires on : 2028-10-22 12:00:00 - signed using : RSA with SHA-256 - RSA key size : 2048 bits - basic constraints : CA=true, max_pathlen=0 - key usage : Digital Signature, Key Cert Sign, CRL Sign - ext key usage : Code Signing - - cert. version : 3 - serial number : 09:70:EF:4B:AD:5C:C4:4A:1C:2B:C3:D9:64:01:67:4C - issuer name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - subject name : C=CZ, L=Praha, O=Avast Software s.r.o., OU=RE stapler cistodc, CN=Avast Software s.r.o. - issued on : 2020-04-02 00:00:00 - expires on : 2023-03-09 12:00:00 - signed using : RSA with SHA-256 - RSA key size : 2048 bits - basic constraints : CA=false - key usage : Digital Signature - ext key usage : Code Signing - - a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 - SHA_256/RSA - C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - 4 auth attr - 1 unauth attr - -Regarding the PE files, the authentihash is computed through the function :meth:`lief.PE.Binary.authentihash` -which takes a :class:`lief.PE.ALGORITHMS` enum as parameter to define which hash algorithm must be -used to compute the digest. - -For instance, to compute the SHA-256 value of the authenticode, we just have to pass :attr:`lief.PE.ALGORITHMS.SHA_256`: - -.. code-block:: python - - print(pe.authentihash(lief.PE.ALGORITHMS.SHA_256).hex()) - -.. code-block:: text - - a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 - -.. note:: - - To compare the :meth:`lief.PE.Binary.authentihash` value with the signed one (i.e. :attr:`lief.PE.ContentInfo.digest`) - we must use the same hash algorithm as defined by :attr:`lief.PE.Signature.digest_algorithm` - -We also expose in the Python API, shortcut attributes to compute the authentihash values for: - -+----------------+---------------------------------------------+ -| Hash Algorithm | Binary's Attribute | -+================+=============================================+ -| MD5 | :attr:`~lief.PE.Binary.authentihash_md5` | -+----------------+---------------------------------------------+ -| SHA1 | :attr:`~lief.PE.Binary.authentihash_sha1` | -+----------------+---------------------------------------------+ -| SHA-256 | :attr:`~lief.PE.Binary.authentihash_sha256` | -+----------------+---------------------------------------------+ -| SHA-512 | :attr:`~lief.PE.Binary.authentihash_sha512` | -+----------------+---------------------------------------------+ - -LIEF also exposes the original raw signature blob through the property :attr:`lief.PE.Signature.raw_der` which -enables to export the signature: - -.. code-block:: python - - from pathlib import Path - - Path("/tmp/extracted.p7b").write_bytes(signature.raw_der) - -Then, we can use ``openssl`` to process its content: - -.. code-block:: text - - $ openssl pkcs7 -inform der -print -in /tmp/extracted.p7b -noout -text - ... - sig_alg: - algorithm: sha256WithRSAEncryption (1.2.840.113549.1.1.11) - parameter: NULL - signature: (0 unused bits) - 0000 - 31 c3 a7 f3 70 e3 2c 49-15 bd f4 09 6c 27 4e 1...p.,I....l'N - 000f - 00 a9 23 df cb ea 7f 99-55 cb 24 88 75 e8 c4 ..#.....U.$.u.. - 001e - de 48 4f 70 dd 2a 27 5c-df be 36 f6 84 0d ad .HOp.*'\..6.... - 002d - 35 5e 65 f7 af 55 01 7a-2d 01 18 a0 d6 98 a4 5^e..U.z-...... - 003c - d1 bd 19 e9 a4 03 f4 a3-4d 12 6e 72 5f 6b 3a ........M.nr_k: - 004b - b8 de 45 f1 63 80 b0 47-42 f6 38 b8 e7 5b dd ..E.c..GB.8..[. - 005a - cf f2 f8 c2 61 4b 2c 19-b7 7d 78 8f 2e 0c b0 ....aK,..}x.... - 0069 - 7c f2 d9 8e 9f 65 4e 21-63 19 6a 5b 0c 91 12 |....eN!c.j[... - 0078 - 44 29 fe 91 d5 6f 5d 9c-4d 7b a1 74 c6 69 d9 D)...o].M{.t.i. - 0087 - e7 23 26 54 35 5c 38 33-c5 a7 92 0d 70 a5 2a .#&T5\83....p.* - 0096 - 33 77 4a fc 86 b0 fa 59-2f 24 f6 a1 45 b2 09 3wJ....Y/$..E.. - 00a5 - 75 2d a1 81 68 e4 67 11-46 e3 fb bf 0c c5 d5 u-..h.g.F...... - 00b4 - d7 7b 7b 35 fb d6 e8 4a-c9 13 82 82 a7 0c 3e .{{5...J......> - 00c3 - 6f 61 e0 37 15 e0 37 5d-b8 22 14 ad 54 58 0e oa.7..7]."..TX. - 00d2 - 95 6c 2b b1 d2 c7 6c 86-a1 9f fa d8 37 ca f7 .l+...l.....7.. - 00e1 - 56 75 b0 9d df 7c 46 43-20 87 8a a3 81 47 82 Vu...|FC ....G. - 00f0 - 99 57 87 12 46 96 02 7c-a7 77 b9 42 4d c8 05 .W..F..|.w.BM.. - 00ff - 0a . - crl: - - signer_info: - version: 1 - issuer_and_serial: - issuer: C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - serial: 12549442701880659695003200114191853388 - digest_alg: - algorithm: sha256 (2.16.840.1.101.3.4.2.1) - parameter: NULL - auth_attr: - object: contentType (1.2.840.113549.1.9.3) - set: - OBJECT:undefined (1.3.6.1.4.1.311.2.1.4) - - object: undefined (1.3.6.1.4.1.311.2.1.11) - -The `authenticode_reader.py `_ -script located in the `examples/ `_ directory -can also be used to inspect the signature: - -.. code-block:: console - - $ python authenticode_reader.py --all avast_free_antivirus_setup_online.exe - -.. code-block:: text - - Signature version : 1 - Digest Algorithm : ALGORITHMS.SHA_256 - Content Info: - Content Type : 1.3.6.1.4.1.311.2.1.4 (SPC_INDIRECT_DATA_CONTENT) - Digest Algorithm: ALGORITHMS.SHA_256 - Digest : a738da4446a4e78ab647db7e53427eb07961c994317f4c59d7edbea5cc786d80 - Certificates - Version : 3 - Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA - Subject : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - Serial Number : 0409181b5fd5bb66755343b56f955008 - Signature Algorithm: SHA256_WITH_RSA_ENCRYPTION - Valid from : 2013/10/22 - 12:00:00 - Valid to : 2028/10/22 - 12:00:00 - Key usage : CRL_SIGN - KEY_CERT_SIGN - DIGITAL_SIGNATURE - Ext key usage : CODE_SIGNING - RSA key size : 2048 - =========================================== - Version : 3 - Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - Subject : C=CZ, L=Praha, O=Avast Software s.r.o., OU=RE stapler cistodc, CN=Avast Software s.r.o. - Serial Number : 0970ef4bad5cc44a1c2bc3d96401674c - Signature Algorithm: SHA256_WITH_RSA_ENCRYPTION - Valid from : 2020/04/02 - 00:00:00 - Valid to : 2023/03/09 - 12:00:00 - Key usage : DIGITAL_SIGNATURE - Ext key usage : CODE_SIGNING - RSA key size : 2048 - =========================================== - Signer(s) - Version : 1 - Serial Number : 0970ef4bad5cc44a1c2bc3d96401674c - Issuer : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA - Digest Algorithm : ALGORITHMS.SHA_256 - Encryption Algorithm: ALGORITHMS.RSA - Encrypted Digest : 758db1f480eb25bada6c ... - Authenticated attributes: - Content Type OID: 1.3.6.1.4.1.311.2.1.4 (SPC_INDIRECT_DATA_CONTENT) - MS Statement type OID: 1.3.6.1.4.1.311.2.1.21 (INDIVIDUAL_CODE_SIGNING) - Info: http://www.avast.com - PKCS9 Message Digest: 3983816a7d1c62962540ec66fa8790fa45d1063cb23e933677de459f0b73c577 - Un-authenticated attributes: - Generic Type 1.3.6.1.4.1.311.3.3.1 (MS_COUNTER_SIGN) - -Verifying the Signature -~~~~~~~~~~~~~~~~~~~~~~~ - -Besides the fact that LIEF can parse PE's authenticode signature, LIEF can also verify the integrity of the authentihash -thanks to the method: :meth:`lief.PE.Binary.verify_signature` which outputs :attr:`lief.PE.Signature.VERIFICATION_FLAGS.OK` -if the signature is valid or another enum (see: :attr:`lief.PE.Signature.VERIFICATION_FLAGS`) when it is invalid: - -.. code-block:: python - - pe = lief.parse("avast_free_antivirus_setup_online.exe") - print(pe.verify_signature()) # lief.PE.Signature.VERIFICATION_FLAGS.OK - -We can also verify a PE binary with a **detached signature** by providing a :class:`signature ` -object to :meth:`~lief.PE.Binary.verify_signature`: - -.. code-block:: python - :emphasize-lines: 3,4 - - pe = lief.parse("avast_free_antivirus_setup_online.exe") - - detached_sig = lief.PE.Signature.parse("/tmp/detached.p7b") - print(pe.verify_signature(detached_sig)) - -The verification process does not rely on an external component (i.e. neither openssl or WinTrust API) but we try -to reproduce the same checks as described in the RFC(s) and the official documentation of the Authenticode -[#]_. - -These checks include: - -A. Check the integrity of the signature (:meth:`lief.PE.Signature.check()`): - - 1. There is ONE and only ONE :class:`~lief.PE.SignerInfo` - 2. Digest algorithms are consistent - (:attr:`Signature.digest_algorithm ` ``==`` :attr:`ContentInfo.digest_algorithm ` ``==`` :attr:`SignerInfo.digest_algorithm `) - 3. If the :class:`~lief.PE.SignerInfo` has authenticated attributes, check their integrity. Otherwise, check - the integrity of the :class:`~lief.PE.ContentInfo` against the Signer's certificate. - 4. If they are authenticated attributes, check that there is a - :class:`lief.PE.PKCS9MessageDigest` attribute for which the :attr:`~lief.PE.PKCS9MessageDigest.digest` - matches the hash of the :class:`~lief.PE.ContentInfo` - 5. If there is a counter signature in the **un-authenticated attributes**, verify its integrity and check - that it wraps a valid *timestamping*. - 6. Check the expiration of the certificates according to the potential *timestamping* - -B. If the signature is valid, check that :attr:`lief.PE.ContentInfo.digest` matches the computed - :meth:`~lief.PE.Binary.authentihash` - -These checks are the default behavior of the :meth:`~lief.PE.Binary.verify_signature`. Nevertheless, you could -pass :class:`lief.PE.Signature.VERIFICATION_CHECKS` flags to customize its behavior: - -:Hash Only: - - By using :attr:`VERIFICATION_CHECKS.HASH_ONLY `, it only performs - step ``B)`` (i.e. check the authentihash values regardless of the signature integrity) - - .. code-block:: python - - pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.HASH_ONLY) - - -:Lifetime Signing: - - By using :attr:`VERIFICATION_CHECKS.LIFETIME_SIGNING `, timestamped - signatures can expire if their certificate expired. It has the same meaning as `WTD_LIFETIME_SIGNING_FLAG `_ - - .. code-block:: python - - pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING) - signature.check(lief.PE.Signature.VERIFICATION_CHECKS.LIFETIME_SIGNING) - - -:Skip Cerificate Check Time: - - By using :attr:`VERIFICATION_CHECKS.SKIP_CERT_TIME `, - LIEF doesn't raise an error if the certificate(s) expired. - - .. code-block:: python - - # Returns lief.PE.Signature.VERIFICATION_FLAGS.OK even though - # the certificates expired - pe.verify_signature(lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME) - signature.check(lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME) - -.. note:: - - To verify the integrity of a :class:`~lief.PE.Signature` object, you can use - :meth:`lief.PE.Signature.check` - - -Certificate Chain of Trust -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Last but not least, we can also verify the certificates chain thanks to: - -1. :meth:`lief.PE.x509.verify` -2. :meth:`lief.PE.x509.is_trusted_by` - -:meth:`~lief.PE.x509.verify` aims to verify a signed certificate from its CA. Given a CA :class:`~lief.PE.x509` -certificate, ``CA.verify(signed)`` verifies that the ``signed`` parameter has been signed by ``CA``. - -On the other hand, :meth:`~lief.PE.x509.is_trusted_by` can be used to check that a given :class:`~lief.PE.x509` -certificate is verified against a **list of certificates**: - -.. code-block:: python - - CA_BUNDLE = lief.PE.x509.parse("ms_bundle.pem") - signer = signature.signers[0] - print(signer.cert.is_trusted_by(CA_BUNDLE)) - -.. code-block:: python - - cert1 = lief.PE.x509.parse("ca1.crt") - cert2 = lief.PE.x509.parse("ca2.crt") - - print(signer.cert.is_trusted_by([cert1, cert2])) - - -Limitations -~~~~~~~~~~~ - -Regarding the PKCS #7 structure itself, LIEF is able to parse and process most of its elements. Nevertheless, -the :class:`lief.PE.SignerInfo` structure can embed attributes (authenticated or not) for which the ASN.1 structure -can be public or not. As of LIEF v0.11.0 we do not support yet the following OIDs: - -+----------------------------+-------------------------------------------------------+ -| OID | Description | -+============================+=======================================================+ -| 1.3.6.1.4.1.311.3.3.1 | Ms-CounterSign (undocumented) | -+----------------------------+-------------------------------------------------------+ -| 1.2.840.113549.1.9.16.2.12 | S/MIME Signing certificate (id-aa-signingCertificate) | -+----------------------------+-------------------------------------------------------+ -| 1.3.6.1.4.1.311.2.6.1 | SPC_COMMERCIAL_SP_KEY_PURPOSE_OBJID | -+----------------------------+-------------------------------------------------------+ -| 1.3.6.1.4.1.311.10.3.28 | szOID_PLATFORM_MANIFEST_BINARY_ID | -+----------------------------+-------------------------------------------------------+ - -These not-supported attributes are wrapped within the :class:`lief.PE.GenericType` that exposes the raw -ASN.1 blob with the property :attr:`~lief.PE.GenericType.raw_content`. - -Conclusion -~~~~~~~~~~ - -Under the hood, most of the work is done by `mbedtls `_ which provides the following primitive used -by LIEF: - -- ASN.1 decoder -- x509 certificate processing (parsing AND verification) -- Hash algorithms -- Public key algorithms - -For the *fun*, we can also cross-compile a small C++ snippet for iOS: - -.. code-block:: cpp - - #include - - int main(int argc, char** argv) { - std::unique_ptr pe = LIEF::PE::Parser::parse(argv[1]) - if (pe->verify_signature() == LIEF::PE::Signature::VERIFICATION_FLAGS.OK) { - std::cout << "Signature ok!" << "\n"; - return 0; - } - std::cout << "Error!" << "\n"; - return 1; - } - -So that we can verify the integrity of a PE executable on an iPhone: - -.. code-block:: console - - iPhone:~ root# file PE32_x86-64_binary_avast-free-antivirus-setup-online.exe - PE32_x86-64_binary_avast-free-antivirus-setup-online.exe: PE32 executable (GUI) Intel 80386, for MS Windows - iPhone:~ root# file ./pe_authenticode_check - ./pe_authenticode_check: Mach-O 64-bit arm64 executable, flags: - iPhone:~ root# ./pe_authenticode_check PE32_x86-64_binary_avast-free-antivirus-setup-online.exe - Signature ok! - iPhone:~ root# - -Whilst this example is quite useless, it emphasizes the purpose of this project: - -- Provide a cross-platform and cross-format library -- Expose a high-level API (Python) as well as a (more or less) low-level API (C++) -- Few dependencies so that the static version of LIEF does not need external libraries [#]_. - -.. code-block:: console - - $ otool -L pe_authenticode_check - - /System/Library/Frameworks/Foundation.framework/Foundation (compatibility version 300.0.0, current version 1770.255.0) - /usr/lib/libobjc.A.dylib (compatibility version 1.0.0, current version 228.0.0) - /usr/lib/libc++.1.dylib (compatibility version 1.0.0, current version 904.4.0) - /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1292.60.1) - - -To complete these functionalities of LIEF, you might also be interested in the following projects -that deal with Authenticode: - -+------------------+----------------------------------------------+ -| Project | URL | -+==================+==============================================+ -| signify | https://github.com/ralphje/signify | -+------------------+----------------------------------------------+ -| winsign | https://github.com/mozilla-releng/winsign | -+------------------+----------------------------------------------+ -| uthenticode | https://github.com/trailofbits/uthenticode | -+------------------+----------------------------------------------+ -| AuthenticodeLint | https://github.com/vcsjones/AuthenticodeLint | -+------------------+----------------------------------------------+ -| osslsigncode | https://github.com/mtrojnar/osslsigncode | -+------------------+----------------------------------------------+ - -Finally, you can find additional information about the Authenticode in Trail of Bits blog post [#]_. -If you are interested in Authenticode tricks used by Dropbox, you can take a look at Microsoft website [#]_ and -if you are interested in understanding how the integrity of the PKCS #7 works, you can look at *Manual verify PKCS#7 signed data with OpenSSL* [#]_ - - -.. rubric:: References - -.. [#] http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/Authenticode_PE.docx - -.. [#] Which now exceptions-free - -.. [#] This tutorial uses the Python API but the C++ API is very similar - -.. [#] See: `src/PE/signature/Signature.cpp - check() `_ for the implementation - -.. [#] Except the C/C++ STL - -.. [#] https://blog.trailofbits.com/2020/05/27/verifying-windows-binaries-without-windows/ - -.. [#] https://docs.microsoft.com/en-us/archive/blogs/ieinternals/caveats-for-authenticode-code-signing - -.. [#] http://qistoph.blogspot.com/2012/01/manual-verify-pkcs7-signed-data-with.html - - - -.. rubric:: API - -* :meth:`lief.PE.Binary.verify_signature` -* :meth:`lief.PE.Binary.authentihash` -* :attr:`lief.PE.Binary.authentihash_md5` -* :attr:`lief.PE.Binary.authentihash_sha1` -* :attr:`lief.PE.Binary.authentihash_sha256` -* :attr:`lief.PE.Binary.authentihash_sha512` -* :attr:`lief.PE.Binary.signatures` - -* :class:`lief.PE.Signature` -* :class:`lief.PE.x509` -* :class:`lief.PE.ContentInfo` -* :class:`lief.PE.SignerInfo` -* :class:`lief.PE.Attribute` -* :class:`lief.PE.ContentType` -* :class:`lief.PE.GenericType` -* :class:`lief.PE.MsSpcNestedSignature` -* :class:`lief.PE.MsSpcStatementType` -* :class:`lief.PE.PKCS9AtSequenceNumber` -* :class:`lief.PE.PKCS9CounterSignature` -* :class:`lief.PE.PKCS9MessageDigest` -* :class:`lief.PE.PKCS9SigningTime` -* :class:`lief.PE.SpcSpOpusInfo` - diff --git a/vendor/lief/doc/sphinx/tutorials/index.rst b/vendor/lief/doc/sphinx/tutorials/index.rst deleted file mode 100644 index a222b8d..0000000 --- a/vendor/lief/doc/sphinx/tutorials/index.rst +++ /dev/null @@ -1,16 +0,0 @@ -Tutorials -========= - -.. toctree:: - :maxdepth: 2 - - 01_play_with_formats.rst - 02_pe_from_scratch.rst - 03_elf_change_symbols.rst - 04_elf_hooking.rst - 05_elf_infect_plt_got.rst - 06_pe_hooking.rst - 07_pe_resource.rst - - - diff --git a/vendor/lief/examples/CMakeLists.txt b/vendor/lief/examples/CMakeLists.txt index 3b84d61..9a8d63f 100644 --- a/vendor/lief/examples/CMakeLists.txt +++ b/vendor/lief/examples/CMakeLists.txt @@ -1,22 +1,9 @@ - -add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/cpp") - -if (LIEF_C_API) - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/c") +add_subdirectory(cpp) + +if (LIEF_INSTALL) + install( + DIRECTORY cmake + DESTINATION ${CMAKE_INSTALL_DATADIR}/LIEF/examples + COMPONENT examples + ) endif() - - -install( - DIRECTORY python - DESTINATION share/LIEF/examples - COMPONENT examples -) - -install( - DIRECTORY cmake - DESTINATION share/LIEF/examples - COMPONENT examples -) - - - diff --git a/vendor/lief/examples/c/CMakeLists.txt b/vendor/lief/examples/c/CMakeLists.txt deleted file mode 100644 index e438810..0000000 --- a/vendor/lief/examples/c/CMakeLists.txt +++ /dev/null @@ -1,75 +0,0 @@ -include(CheckCCompilerFlag) - -set(LIEF_ELF_C_EXAMPLES - elf_reader.c) - -set(LIEF_PE_C_EXAMPLES - pe_reader.c) - -set(LIEF_MACHO_C_EXAMPLES - macho_reader.c) - -set(LIEF_C_EXAMPLES) - -if (LIEF_ELF) - set(LIEF_C_EXAMPLES "${LIEF_C_EXAMPLES}" "${LIEF_ELF_C_EXAMPLES}") -endif() - -if (LIEF_PE) - set(LIEF_C_EXAMPLES "${LIEF_C_EXAMPLES}" "${LIEF_PE_C_EXAMPLES}") -endif() - -if (LIEF_MACHO) - set(LIEF_C_EXAMPLES "${LIEF_C_EXAMPLES}" "${LIEF_MACHO_C_EXAMPLES}") -endif() - -if (LIEF_C_API) -foreach(example ${LIEF_C_EXAMPLES}) - string(REGEX REPLACE ".c\$" "" output_target "c_${example}") - string(REGEX REPLACE ".c\$" "" output_name "${example}") - - add_executable("${output_target}" "${example}") - - target_include_directories(${output_target} PUBLIC - $) - - if (MSVC) - set_property(TARGET "${output_target}" PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) - target_compile_options("${output_target}" PUBLIC ${LIEF_CRT}) - endif() - - set(LIEF_EXAMPLES_C_FLAGS) - CHECK_C_COMPILER_FLAG("-ansi" HAS_ANSI) - if (HAS_ANSI) - set(LIEF_EXAMPLES_C_FLAGS ${LIEF_EXAMPLES_C_FLAGS} -ansi) - endif() - - set_property(TARGET "${output_target}" PROPERTY C_STANDARD 99) - set_property(TARGET "${output_target}" PROPERTY C_STANDARD_REQUIRED ON) - - target_compile_options("${output_target}" PRIVATE ${LIEF_EXAMPLES_C_FLAGS}) - - if(CMAKE_COMPILER_IS_GNUCXX OR CMAKE_CXX_COMPILER_ID MATCHES "Clang") - if (UNIX) - if (LIEF_FORCE32) - target_compile_options("${output_target}" PRIVATE -m32) - set_property(TARGET "${output_target}" PROPERTY LINK_FLAGS -m32) - endif() - endif() - endif() - - - - set_target_properties("${output_target}" PROPERTIES OUTPUT_NAME "${output_name}") - target_link_libraries ("${output_target}" LIB_LIEF) -endforeach() -endif() - - -install( - DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/ - DESTINATION share/LIEF/examples/c - COMPONENT examples - FILES_MATCHING REGEX "(.*).(hpp|h|c)$" -) - diff --git a/vendor/lief/examples/c/elf_reader.c b/vendor/lief/examples/c/elf_reader.c deleted file mode 100644 index 23c8bd0..0000000 --- a/vendor/lief/examples/c/elf_reader.c +++ /dev/null @@ -1,313 +0,0 @@ -#include -#include -#include - -#include - - -int main(int argc, char **argv) { - size_t i, j; - - if (argc != 2) { - fprintf(stderr, "Usage: %s \n", argv[0]); - return EXIT_FAILURE ; - } - - Elf_Binary_t *elf_binary = elf_parse(argv[1]); - fprintf(stdout, "Binary Name: %s\n", elf_binary->name); - fprintf(stdout, "Interpreter: %s\n", elf_binary->interpreter); - - Elf_Header_t header = elf_binary->header; - uint8_t *identity = header.identity; - fprintf(stdout, "Header\n"); - fprintf(stdout, "======\n"); - fprintf(stdout, "Magic: %x %x %x %x\n", identity[0], identity[1], identity[2], identity[3]); - fprintf(stdout, "Class: %s\n", ELF_CLASS_to_string(identity[LIEF_ELF_EI_CLASS])); - fprintf(stdout, "Endianness: %s\n", ELF_DATA_to_string(identity[LIEF_ELF_EI_DATA])); - fprintf(stdout, "Version: %s\n", VERSION_to_string(identity[LIEF_ELF_EI_VERSION])); - fprintf(stdout, "OS/ABI: %s\n", OS_ABI_to_string(identity[LIEF_ELF_EI_OSABI])); - fprintf(stdout, "File type: %s\n", E_TYPE_to_string(header.file_type)); - fprintf(stdout, "Architecture: %s\n", ARCH_to_string(header.machine_type)); - fprintf(stdout, "Version: %s\n", VERSION_to_string(header.object_file_version)); - fprintf(stdout, "Segments offset: 0x%" PRIx64 "\n", header.program_headers_offset); - fprintf(stdout, "Sections offset: 0x%" PRIx64 "\n", header.section_headers_offset); - fprintf(stdout, "Processor flags: %x\n", header.processor_flags); - fprintf(stdout, "Header Size: %x\n", header.header_size); - fprintf(stdout, "Program header size: %x\n", header.program_header_size); - fprintf(stdout, "Nb segments: %d\n", header.numberof_segments); - fprintf(stdout, "Section header size: %x\n", header.section_header_size); - fprintf(stdout, "Nb sections: %d\n", header.numberof_sections); - fprintf(stdout, "Name string table idx: %d\n", header.name_string_table_idx); - - Elf_Section_t** sections = elf_binary->sections; - /*for (size_t i = 0; sections[i] != NULL; ++i) {*/ - for (i = 0; i < header.numberof_sections; ++i) { - Elf_Section_t* section = sections[i]; - fprintf(stdout, "" - "%-20s " - "%-10s " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "%d " - "0x%06" PRIx64 " " - "0x%06" PRIx64 " " - "%.6f " - "\n", - section->name, - ELF_SECTION_TYPES_to_string(section->type), - section->virtual_address, - section->size, - section->offset, - section->link, - section->alignment, - section->entry_size, - section->entropy - ); - if (section->size > 3) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - section->content[0], section->content[1], section->content[2]); - } - } - - /* Dynamic symbols */ - fprintf(stdout, "Dynamic symbols:\n"); - Elf_Symbol_t** dynamic_symbols = elf_binary->dynamic_symbols; - for (i = 0; dynamic_symbols[i] != NULL; ++i) { - Elf_Symbol_t* symbol = dynamic_symbols[i]; - const char* import_export = ""; - - if (symbol->is_imported) { - import_export = "I"; - } - - if (symbol->is_imported) { - import_export = "E"; - } - - fprintf(stdout, "" - "%-20s " - "%-10s " - "%-10s " - "0x%02x " - "0x%02x" - "0x%010" PRIx64 " " - "0x%06" PRIx64 " " - "%-3s " - "\n", - symbol->name, - ELF_SYMBOL_TYPES_to_string(symbol->type), - SYMBOL_BINDINGS_to_string(symbol->binding), - symbol->other, - symbol->shndx, - symbol->value, - symbol->size, - import_export - ); - } - - /* Static symbols */ - fprintf(stdout, "Static symbols:\n"); - Elf_Symbol_t** static_symbols = elf_binary->static_symbols; - for (i = 0; static_symbols[i] != NULL; ++i) { - Elf_Symbol_t* symbol = static_symbols[i]; - - const char* import_export = ""; - - if (symbol->is_imported) { - import_export = "I"; - } - - if (symbol->is_imported) { - import_export = "E"; - } - - fprintf(stdout, "" - "%-20s " - "%-10s " - "%-10s " - "0x%02x " - "0x%02x" - "0x%010" PRIx64 " " - "0x%06" PRIx64 " " - "%-3s " - "\n", - symbol->name, - ELF_SYMBOL_TYPES_to_string(symbol->type), - SYMBOL_BINDINGS_to_string(symbol->binding), - symbol->other, - symbol->shndx, - symbol->value, - symbol->size, - import_export - ); - } - - - fprintf(stdout, "Segments:\n"); - Elf_Segment_t** segments = elf_binary->segments; - for (i = 0; segments[i] != NULL; ++i) { - Elf_Segment_t* segment = segments[i]; - fprintf(stdout, "" - "%-20s " - "0x%06" PRIx32 " " - "0x%010" PRIx64 " " - "0x%06" PRIx64 " " - "0x%010" PRIx64 " " - "0x%06" PRIx64 " " - "0x%06" PRIx64 " " - "\n", - SEGMENT_TYPES_to_string(segment->type), - segment->flags, - segment->virtual_address, - segment->virtual_size, - segment->offset, - segment->size, - segment->alignment - ); - if (segment->size > 3) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - segment->content[0], segment->content[1], segment->content[2]); - } - } - - Elf_DynamicEntry_t **dynamic_entries = elf_binary->dynamic_entries; - for (i = 0; dynamic_entries[i] != NULL; ++i) { - Elf_DynamicEntry_t* entry = dynamic_entries[i]; - switch(entry->tag) { - case LIEF_ELF_DT_NEEDED: - { - Elf_DynamicEntry_Library_t* e = (Elf_DynamicEntry_Library_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "%-20s " - "\n", - DYNAMIC_TAGS_to_string(e->tag), - e->value, - e->name - ); - break; - } - case LIEF_ELF_DT_SONAME: - { - Elf_DynamicEntry_SharedObject_t* e = (Elf_DynamicEntry_SharedObject_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "%-20s " - "\n", - DYNAMIC_TAGS_to_string(e->tag), - e->value, - e->name - ); - break; - } - - case LIEF_ELF_DT_RPATH: - { - Elf_DynamicEntry_Rpath_t* e = (Elf_DynamicEntry_Rpath_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "%-20s " - "\n", - DYNAMIC_TAGS_to_string(e->tag), - e->value, - e->rpath - ); - break; - } - - case LIEF_ELF_DT_RUNPATH: - { - Elf_DynamicEntry_RunPath_t* e = (Elf_DynamicEntry_RunPath_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "%-20s " - "\n", - DYNAMIC_TAGS_to_string(e->tag), - e->value, - e->runpath - ); - break; - } - - case LIEF_ELF_DT_FLAGS: - { - Elf_DynamicEntry_Flags_t* e = (Elf_DynamicEntry_Flags_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " ", - DYNAMIC_TAGS_to_string(e->tag), - e->value); - - enum LIEF_ELF_DYNAMIC_FLAGS* flags = e->flags; - for (j = 0; flags[j] != 0; ++j) { - fprintf(stdout, "%s ", DYNAMIC_FLAGS_to_string(flags[j])); - } - - fprintf(stdout, "\n"); - break; - } - - case LIEF_ELF_DT_FLAGS_1: - { - Elf_DynamicEntry_Flags_t* e = (Elf_DynamicEntry_Flags_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " ", - DYNAMIC_TAGS_to_string(e->tag), - e->value); - - enum LIEF_ELF_DYNAMIC_FLAGS_1* flags = e->flags_1; - for (j = 0; flags[j] != 0; ++j) { - fprintf(stdout, "%s ", DYNAMIC_FLAGS_1_to_string(flags[j])); - } - - fprintf(stdout, "\n"); - break; - } - - - case LIEF_ELF_DT_INIT_ARRAY: - case LIEF_ELF_DT_FINI_ARRAY: - case LIEF_ELF_DT_PREINIT_ARRAY: - { - Elf_DynamicEntry_Array_t* e = (Elf_DynamicEntry_Array_t*)entry; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " ", - DYNAMIC_TAGS_to_string(e->tag), - e->value - ); - uint64_t* array = e->array; - for (j = 0; array[j] != 0; ++j) { - fprintf(stdout, "" "0x%06" PRIx64 " ", array[j]); - } - - fprintf(stdout, "\n"); - break; - } - - default: - { - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "\n", - DYNAMIC_TAGS_to_string(entry->tag), - entry->value - ); - break; - } - } - } - - - - elf_binary_destroy(elf_binary); - - return EXIT_SUCCESS; -} diff --git a/vendor/lief/examples/c/macho_reader.c b/vendor/lief/examples/c/macho_reader.c deleted file mode 100644 index f39284c..0000000 --- a/vendor/lief/examples/c/macho_reader.c +++ /dev/null @@ -1,158 +0,0 @@ -#include -#include -#include - -#include - - -void print_binary(Macho_Binary_t* binary) { - fprintf(stdout, "Binary Name: %s\n", binary->name); - - Macho_Header_t header = binary->header; - fprintf(stdout, "Header\n"); - fprintf(stdout, "========\n"); - fprintf(stdout, "Magic: 0x%" PRIx32 "\n", header.magic); - fprintf(stdout, "CPU Type: %s\n", CPU_TYPES_to_string(header.cpu_type)); - fprintf(stdout, "CPU SubType: 0x%" PRIx32 "\n", header.cpu_subtype); - fprintf(stdout, "File type: %s\n", FILE_TYPES_to_string(header.file_type)); - fprintf(stdout, "Number of commands: 0x%" PRIx32 "\n", header.nb_cmds); - fprintf(stdout, "Commands size: 0x%" PRIx32 "\n", header.sizeof_cmds); - fprintf(stdout, "flags: 0x%" PRIx32 "\n", header.flags); - fprintf(stdout, "reserved: 0x%" PRIx32 "\n", header.reserved); - - fprintf(stdout, "Commands\n"); - fprintf(stdout, "========\n"); - Macho_Command_t** commands = binary->commands; - for (size_t i = 0; commands[i] != NULL; ++i) { - Macho_Command_t* command = commands[i]; - fprintf(stdout, "" - "%-20s " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "\n", - LOAD_COMMAND_TYPES_to_string(command->command), - command->size, - command->offset - ); - if (command->size > 3) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - command->data[0], command->data[1], command->data[2]); - } - } - - fprintf(stdout, "Segments\n"); - fprintf(stdout, "========\n"); - Macho_Segment_t** segments = binary->segments; - for (size_t i = 0; segments[i] != NULL; ++i) { - Macho_Segment_t* segment = segments[i]; - fprintf(stdout, "" - "%-20s " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "\n", - segment->name, - segment->virtual_address, - segment->virtual_size, - segment->file_size, - segment->file_offset, - segment->max_protection, - segment->init_protection, - segment->numberof_sections, - segment->flags - ); - - if (segment->file_size > 3) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - segment->content[0], segment->content[1], segment->content[2]); - } - } - - - fprintf(stdout, "Sections\n"); - fprintf(stdout, "========\n"); - Macho_Section_t** sections = binary->sections; - for (size_t i = 0; sections[i] != NULL; ++i) { - Macho_Section_t* section = sections[i]; - fprintf(stdout, "" - "%-20s " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "%-30s " - "0x%02" PRIx32 " " - "0x%02" PRIx32 " " - "0x%02" PRIx32 " " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "0x%010" PRIx64 " " - "%.6f " - "\n", - section->name, - section->alignment, - section->relocation_offset, - section->numberof_relocations, - section->flags, - MACHO_SECTION_TYPES_to_string(section->type), - section->reserved1, - section->reserved2, - section->reserved3, - section->virtual_address, - section->offset, - section->size, - section->entropy - ); - if (section->size > 3) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - section->content[0], section->content[1], section->content[2]); - } - } - - fprintf(stdout, "Symbols\n"); - fprintf(stdout, "=======\n"); - Macho_Symbol_t** symbols = binary->symbols; - for (size_t i = 0; symbols[i] != NULL; ++i) { - Macho_Symbol_t* symbol = symbols[i]; - fprintf(stdout, "" - "%-30s " - "0x%02" PRIx32 " " - "0x%02" PRIx32 " " - "0x%04" PRIx16 " " - "0x%010" PRIx64 " " - "\n", - symbol->name, - (uint32_t)symbol->type, - (uint32_t)symbol->numberof_sections, - symbol->description, - symbol->value - ); - } - - -} - -int main(int argc, char **argv) { - size_t idx; - - if (argc != 2) { - fprintf(stderr, "Usage: %s \n", argv[0]); - return EXIT_FAILURE ; - } - - Macho_Binary_t** macho_binaries = macho_parse(argv[1]); - for (idx = 0; macho_binaries[idx] != NULL; ++idx) { - print_binary(macho_binaries[idx]); - } - - - macho_binaries_destroy(macho_binaries); - - return EXIT_SUCCESS; - -} diff --git a/vendor/lief/examples/c/pe_reader.c b/vendor/lief/examples/c/pe_reader.c deleted file mode 100644 index 5d37ece..0000000 --- a/vendor/lief/examples/c/pe_reader.c +++ /dev/null @@ -1,160 +0,0 @@ -#include -#include -#include - -#include - - -int main(int argc, char **argv) { - - if (argc != 2) { - fprintf(stderr, "Usage: %s \n", argv[0]); - return EXIT_FAILURE ; - } - - Pe_Binary_t *pe_binary = pe_parse(argv[1]); - - fprintf(stdout, "Binary Name: %s\n", pe_binary->name); - - Pe_DosHeader_t dos_header = pe_binary->dos_header; - - uint16_t *reserved = dos_header.reserved; - uint16_t *reserved2 = dos_header.reserved2; - - fprintf(stdout, "DosHeader\n"); - fprintf(stdout, "=========\n"); - fprintf(stdout, "Used bytes in the last page: 0x%x\n", dos_header.used_bytes_in_the_last_page); - fprintf(stdout, "File size in pages: 0x%x\n", dos_header.file_size_in_pages); - fprintf(stdout, "Number of relocations: 0x%x\n", dos_header.numberof_relocation); - fprintf(stdout, "Header size in paragraphs: 0x%x\n", dos_header.header_size_in_paragraphs); - fprintf(stdout, "Minimum extra paragraphs: 0x%x\n", dos_header.minimum_extra_paragraphs); - fprintf(stdout, "Maximum extra paragraphs: 0x%x\n", dos_header.maximum_extra_paragraphs); - fprintf(stdout, "Initial relative ss: 0x%x\n", dos_header.initial_relative_ss); - fprintf(stdout, "Initial sp: 0x%x\n", dos_header.initial_sp); - fprintf(stdout, "Checksum: 0x%x\n", dos_header.checksum); - fprintf(stdout, "Initial ip: 0x%x\n", dos_header.initial_ip); - fprintf(stdout, "Initial relative cs: 0x%x\n", dos_header.initial_relative_cs); - fprintf(stdout, "Address of relocation table: 0x%x\n", dos_header.addressof_relocation_table); - fprintf(stdout, "Overlay number: 0x%x\n", dos_header.overlay_number); - fprintf(stdout, "Reserved: %x %x %x %x\n", reserved[0], reserved[1], reserved[2], reserved[3]); - fprintf(stdout, "OEM id: 0x%x\n", dos_header.oem_id); - fprintf(stdout, "OEM info: 0x%x\n", dos_header.oem_info); - fprintf(stdout, "Reserved2: %x %x %x %x %x %x %x %x %x %x\n", - reserved2[0], reserved2[1], reserved2[2], reserved2[3], reserved2[4], - reserved2[5], reserved2[6], reserved2[7], reserved2[8], reserved2[9]); - fprintf(stdout, "Address of new exeheader: 0x%x\n", dos_header.addressof_new_exeheader); - - - Pe_Header_t header = pe_binary->header; - fprintf(stdout, "Header\n"); - fprintf(stdout, "======\n"); - fprintf(stdout, "Machine: %s\n", MACHINE_TYPES_to_string(header.machine)); - fprintf(stdout, "Number of sections: %d\n", header.numberof_sections); - fprintf(stdout, "Timestamp: 0x%x\n", header.time_date_stamp); - fprintf(stdout, "Pointer to symbol table: 0x%x\n", header.pointerto_symbol_table); - fprintf(stdout, "Number of symbols: %d\n", header.numberof_symbols); - fprintf(stdout, "Sizeof optional header: 0x%x\n", header.sizeof_optional_header); - fprintf(stdout, "Characteristics: 0x%x\n", header.characteristics); - - - Pe_OptionalHeader_t optional_header = pe_binary->optional_header; - fprintf(stdout, "Optional Header\n"); - fprintf(stdout, "===============\n"); - fprintf(stdout, "Magic: %s\n", PE_TYPES_to_string(optional_header.magic)); - fprintf(stdout, "Major linker version: 0x%x\n", optional_header.major_linker_version); - fprintf(stdout, "Minor linker version: 0x%x\n", optional_header.minor_linker_version); - fprintf(stdout, "Size ofcode: 0x%x\n", optional_header.sizeof_code); - fprintf(stdout, "Size of initialized data: 0x%x\n", optional_header.sizeof_initialized_data); - fprintf(stdout, "Size of uninitialized data: 0x%x\n", optional_header.sizeof_uninitialized_data); - fprintf(stdout, "Address of entrypoint: 0x%x\n", optional_header.addressof_entrypoint); - fprintf(stdout, "Base of code: 0x%x\n", optional_header.baseof_code); - fprintf(stdout, "Base of data: 0x%x\n", optional_header.baseof_data); - fprintf(stdout, "Imagebase: 0x%" PRIx64 "\n", optional_header.imagebase); - fprintf(stdout, "Section alignment: 0x%x\n", optional_header.section_alignment); - fprintf(stdout, "File alignment: 0x%x\n", optional_header.file_alignment); - fprintf(stdout, "Major operating system version: 0x%x\n", optional_header.major_operating_system_version); - fprintf(stdout, "Minor operating system version: 0x%x\n", optional_header.minor_operating_system_version); - fprintf(stdout, "Major image version: 0x%x\n", optional_header.major_image_version); - fprintf(stdout, "Minor image version: 0x%x\n", optional_header.minor_image_version); - fprintf(stdout, "Major subsystem version: 0x%x\n", optional_header.major_subsystem_version); - fprintf(stdout, "Minor subsystem version: 0x%x\n", optional_header.minor_subsystem_version); - fprintf(stdout, "Win32 version value: 0x%x\n", optional_header.win32_version_value); - fprintf(stdout, "Size of image: 0x%x\n", optional_header.sizeof_image); - fprintf(stdout, "Size of headers: 0x%x\n", optional_header.sizeof_headers); - fprintf(stdout, "Checksum: 0x%x\n", optional_header.checksum); - fprintf(stdout, "subsystem: %s\n", SUBSYSTEM_to_string(optional_header.subsystem)); - fprintf(stdout, "DLL characteristics: 0x%x\n", optional_header.dll_characteristics); - fprintf(stdout, "Size of stack reserve: 0x%" PRIx64 "\n", optional_header.sizeof_stack_reserve); - fprintf(stdout, "Size of stack commit: 0x%" PRIx64 "\n", optional_header.sizeof_stack_commit); - fprintf(stdout, "Size of heap reserve: 0x%" PRIx64 "\n", optional_header.sizeof_heap_reserve); - fprintf(stdout, "Size of heap commit: 0x%" PRIx64 "\n", optional_header.sizeof_heap_commit); - fprintf(stdout, "Loader flags: 0x%x\n", optional_header.loader_flags); - fprintf(stdout, "Number of rva and size: 0x%x\n", optional_header.numberof_rva_and_size); - - - fprintf(stdout, "\nDataDirectories\n"); - fprintf(stdout, "===============\n"); - Pe_DataDirectory_t** data_directories = pe_binary->data_directories; - for (size_t i = 0; data_directories[i] != NULL; ++i) { - fprintf(stdout, "RVA 0x%" PRIx32 "\n", data_directories[i]->rva); - fprintf(stdout, "Size 0x%" PRIx32 "\n", data_directories[i]->size); - } - - fprintf(stdout, "\nSections\n"); - fprintf(stdout, "========\n"); - - Pe_Section_t** sections = pe_binary->sections; - for (size_t i = 0; sections[i] != NULL; ++i) { - Pe_Section_t* section = sections[i]; - fprintf(stdout, "" - "%-20s " - "0x%06" PRIx64 " " - "0x%06" PRIx64 " " - "0x%06" PRIx64 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "0x%06" PRIx32 " " - "%.6f " - "\n", - section->name, - section->virtual_address, - section->size, - section->offset, - section->virtual_size, - section->pointerto_relocation, - section->pointerto_line_numbers, - section->characteristics, - section->entropy - ); - - if (section->size > 3 && section->content != NULL) { - fprintf(stdout, "content[0..3]: %02x %02x %02x\n", - section->content[0], section->content[1], section->content[2]); - } - } - - - fprintf(stdout, "\nImports\n"); - fprintf(stdout, "========\n"); - Pe_Import_t** imports = pe_binary->imports; - if (imports != NULL) { - for (size_t i = 0; imports[i] != NULL; ++i) { - fprintf(stdout, "Name: %s\n", imports[i]->name); - Pe_ImportEntry_t** entries = imports[i]->entries; - for (size_t i = 0; entries[i] != NULL; ++i) { - if (entries[i]->name != NULL) { - fprintf(stdout, " %s\n", entries[i]->name); - } - } - - } - } - - - - pe_binary_destroy(pe_binary); - - return EXIT_SUCCESS; - -} diff --git a/vendor/lief/examples/cmake/add_subdirectory/CMakeLists.txt b/vendor/lief/examples/cmake/add_subdirectory/CMakeLists.txt index c4e02b8..a620df5 100644 --- a/vendor/lief/examples/cmake/add_subdirectory/CMakeLists.txt +++ b/vendor/lief/examples/cmake/add_subdirectory/CMakeLists.txt @@ -1,6 +1,4 @@ -# Minimum of 3.5 for adding submodule of LIEF because LIEF min is 3.5, -# otherwise 3.11+ for FetchContent command -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.21) project(SubdirLIEF LANGUAGES CXX) @@ -14,7 +12,7 @@ option(LIEF_EXAMPLES "Build LIEF examples" OFF) option(LIEF_TESTS "Build LIEF tests" OFF) if(MSVC) - set(LIEF_USE_CRT_RELEASE "MT" CACHE STRING "LIEF CRT option") + set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded" CACHE STRING "CRT option") endif() @@ -35,8 +33,8 @@ else() # URL of the LIEF repo (Can be your fork) set(LIEF_GIT_URL "https://github.com/lief-project/LIEF.git") - # LIEF's version to be used (can be 'master') - set(LIEF_VERSION 0.12.0) + # LIEF's version to be used (can be 'main') + set(LIEF_VERSION 1.0.0) include(FetchContent) FetchContent_Declare(LIEF @@ -66,13 +64,9 @@ endif() # ================== add_executable(HelloLIEF main.cpp) -if(MSVC) - set_property(TARGET HelloLIEF PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) -endif() - # Enable C++11 set_property(TARGET HelloLIEF - PROPERTY CXX_STANDARD 11 + PROPERTY CXX_STANDARD 17 PROPERTY CXX_STANDARD_REQUIRED ON) # Link the executable with LIEF diff --git a/vendor/lief/examples/cmake/add_subdirectory/README.md b/vendor/lief/examples/cmake/add_subdirectory/README.md new file mode 100644 index 0000000..c6c4f28 --- /dev/null +++ b/vendor/lief/examples/cmake/add_subdirectory/README.md @@ -0,0 +1,9 @@ +# LIEF CMake Integration Example - add_subdirectory + +```console +$ mkdir build +$ cd build +$ cmake .. +$ make +$ HelloLIEF /bin/ls # or explorer.exe or whatever +``` diff --git a/vendor/lief/examples/cmake/add_subdirectory/README.rst b/vendor/lief/examples/cmake/add_subdirectory/README.rst deleted file mode 100644 index 442f34a..0000000 --- a/vendor/lief/examples/cmake/add_subdirectory/README.rst +++ /dev/null @@ -1,12 +0,0 @@ -LIEF CMake Integration Example - add_subdirectory -================================================= - - -.. code-block:: console - - $ mkdir build - $ cd build - $ cmake .. - $ make - $ HelloLIEF /bin/ls # or explorer.exe or whatever - diff --git a/vendor/lief/examples/cmake/add_subdirectory/main.cpp b/vendor/lief/examples/cmake/add_subdirectory/main.cpp index c81de6d..fba9b06 100644 --- a/vendor/lief/examples/cmake/add_subdirectory/main.cpp +++ b/vendor/lief/examples/cmake/add_subdirectory/main.cpp @@ -1,13 +1,15 @@ -#include #include +#include int main(int argc, char** argv) { if (argc != 2) { - std::cerr << "Usage: " << argv[0] << " " << std::endl; + std::cerr << "Usage: " << argv[0] << " " << '\n'; return 1; } - auto binary = LIEF::Parser::parse(argv[1]); - std::cout << *binary << std::endl; + if (auto binary = LIEF::Parser::parse(argv[1])) { + std::cout << *binary << '\n'; + } + return 0; } diff --git a/vendor/lief/examples/cmake/external_project/CMakeLists.txt b/vendor/lief/examples/cmake/external_project/CMakeLists.txt index d9384e1..3dca054 100644 --- a/vendor/lief/examples/cmake/external_project/CMakeLists.txt +++ b/vendor/lief/examples/cmake/external_project/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.0) +cmake_minimum_required(VERSION 3.21) project(CMakeLIEF LANGUAGES NONE) @@ -12,8 +12,8 @@ set(LIEF_INSTALL_DIR "${LIEF_PREFIX}/install") # URL of the LIEF repo (Can be your fork) set(LIEF_GIT_URL "https://github.com/lief-project/LIEF.git") -# LIEF's version to be used (can be 'master') -set(LIEF_VERSION 0.12.0) +# LIEF's version to be used (can be 'main') +set(LIEF_VERSION 0.13.0) # LIEF compilation config set(LIEF_CMAKE_ARGS @@ -26,7 +26,7 @@ set(LIEF_CMAKE_ARGS ) if(MSVC) - list(APPEND ${LIEF_CMAKE_ARGS} -DLIEF_USE_CRT_RELEASE=MT) + list(APPEND ${LIEF_CMAKE_ARGS} -DCMAKE_MSVC_RUNTIME_LIBRARY=MultiThreaded) endif() ExternalProject_Add(LIEF @@ -49,6 +49,6 @@ ExternalProject_Add(HelloLIEF BINARY_DIR "${CMAKE_CURRENT_BUILD_DIR}" INSTALL_COMMAND "" CMAKE_ARGS - "-DLIEF_DIR=${LIEF_INSTALL_DIR}/share/LIEF/cmake" + "-DLIEF_DIR=${LIEF_INSTALL_DIR}/lib/cmake/LIEF" -DCMAKE_BUILD_TYPE=RelWithDebInfo ) diff --git a/vendor/lief/examples/cmake/external_project/HelloLIEF/CMakeLists.txt b/vendor/lief/examples/cmake/external_project/HelloLIEF/CMakeLists.txt index d0e3dd6..52337b3 100644 --- a/vendor/lief/examples/cmake/external_project/HelloLIEF/CMakeLists.txt +++ b/vendor/lief/examples/cmake/external_project/HelloLIEF/CMakeLists.txt @@ -14,14 +14,9 @@ find_package(LIEF REQUIRED COMPONENTS STATIC) # COMPONENTS: - # ================== add_executable(HelloLIEF main.cpp) -if(MSVC) - set_property(TARGET HelloLIEF PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) -endif() - - # Enable C++11 set_property(TARGET HelloLIEF - PROPERTY CXX_STANDARD 11 + PROPERTY CXX_STANDARD 17 PROPERTY CXX_STANDARD_REQUIRED ON) # Link the executable with LIEF diff --git a/vendor/lief/examples/cmake/external_project/HelloLIEF/main.cpp b/vendor/lief/examples/cmake/external_project/HelloLIEF/main.cpp index c81de6d..4f6d485 100644 --- a/vendor/lief/examples/cmake/external_project/HelloLIEF/main.cpp +++ b/vendor/lief/examples/cmake/external_project/HelloLIEF/main.cpp @@ -1,13 +1,14 @@ -#include #include +#include int main(int argc, char** argv) { if (argc != 2) { - std::cerr << "Usage: " << argv[0] << " " << std::endl; + std::cerr << "Usage: " << argv[0] << " " << '\n'; return 1; } - auto binary = LIEF::Parser::parse(argv[1]); - std::cout << *binary << std::endl; + if (auto binary = LIEF::Parser::parse(argv[1])) { + std::cout << *binary << '\n'; + } return 0; } diff --git a/vendor/lief/examples/cmake/external_project/README.md b/vendor/lief/examples/cmake/external_project/README.md new file mode 100644 index 0000000..4ccfa74 --- /dev/null +++ b/vendor/lief/examples/cmake/external_project/README.md @@ -0,0 +1,9 @@ +# LIEF CMake Integration Example - ExternalProject + +```console +$ mkdir build +$ cd build +$ cmake .. +$ make +$ HelloLIEF /bin/ls # or explorer.exe or what ever +``` diff --git a/vendor/lief/examples/cmake/external_project/README.rst b/vendor/lief/examples/cmake/external_project/README.rst deleted file mode 100644 index 09eb42b..0000000 --- a/vendor/lief/examples/cmake/external_project/README.rst +++ /dev/null @@ -1,12 +0,0 @@ -LIEF CMake Integration Example - ExternalProject -================================================ - - -.. code-block:: console - - $ mkdir build - $ cd build - $ cmake .. - $ make - $ HelloLIEF /bin/ls # or explorer.exe or what ever - diff --git a/vendor/lief/examples/cmake/find_package/CMakeLists.txt b/vendor/lief/examples/cmake/find_package/CMakeLists.txt index d0e3dd6..52337b3 100644 --- a/vendor/lief/examples/cmake/find_package/CMakeLists.txt +++ b/vendor/lief/examples/cmake/find_package/CMakeLists.txt @@ -14,14 +14,9 @@ find_package(LIEF REQUIRED COMPONENTS STATIC) # COMPONENTS: - # ================== add_executable(HelloLIEF main.cpp) -if(MSVC) - set_property(TARGET HelloLIEF PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) -endif() - - # Enable C++11 set_property(TARGET HelloLIEF - PROPERTY CXX_STANDARD 11 + PROPERTY CXX_STANDARD 17 PROPERTY CXX_STANDARD_REQUIRED ON) # Link the executable with LIEF diff --git a/vendor/lief/examples/cmake/find_package/README.md b/vendor/lief/examples/cmake/find_package/README.md new file mode 100644 index 0000000..1cc40cf --- /dev/null +++ b/vendor/lief/examples/cmake/find_package/README.md @@ -0,0 +1,9 @@ +# LIEF CMake Integration Example - find_package() + +```console +$ mkdir build +$ cd build +$ cmake -DLIEF_DIR=/lib/cmake/LIEF/ .. +$ make +$ HelloLIEF /bin/ls # or explorer.exe or whatever +``` diff --git a/vendor/lief/examples/cmake/find_package/README.rst b/vendor/lief/examples/cmake/find_package/README.rst deleted file mode 100644 index 18331b7..0000000 --- a/vendor/lief/examples/cmake/find_package/README.rst +++ /dev/null @@ -1,12 +0,0 @@ -LIEF CMake Integration Example - find_package() -=============================================== - - -.. code-block:: console - - $ mkdir build - $ cd build - $ cmake -DLIEF_DIR=/share/LIEF/cmake .. - $ make - $ HelloLIEF /bin/ls # or explorer.exe or whatever - diff --git a/vendor/lief/examples/cmake/find_package/main.cpp b/vendor/lief/examples/cmake/find_package/main.cpp index c81de6d..fba9b06 100644 --- a/vendor/lief/examples/cmake/find_package/main.cpp +++ b/vendor/lief/examples/cmake/find_package/main.cpp @@ -1,13 +1,15 @@ -#include #include +#include int main(int argc, char** argv) { if (argc != 2) { - std::cerr << "Usage: " << argv[0] << " " << std::endl; + std::cerr << "Usage: " << argv[0] << " " << '\n'; return 1; } - auto binary = LIEF::Parser::parse(argv[1]); - std::cout << *binary << std::endl; + if (auto binary = LIEF::Parser::parse(argv[1])) { + std::cout << *binary << '\n'; + } + return 0; } diff --git a/vendor/lief/examples/cpp/CMakeLists.txt b/vendor/lief/examples/cpp/CMakeLists.txt index 3cc0a83..8c26e25 100644 --- a/vendor/lief/examples/cpp/CMakeLists.txt +++ b/vendor/lief/examples/cpp/CMakeLists.txt @@ -1,102 +1,132 @@ -set(LIEF_ELF_CPP_EXAMPLES - elf_reader.cpp - elf_add_section.cpp - elf_builder.cpp - elf_section_rename.cpp - elf_strip.cpp - elf_symbols.cpp -) - -set(LIEF_PE_CPP_EXAMPLES - pe_builder.cpp - pe_reader.cpp - pe_authenticode_check.cpp -) - -set(LIEF_MACHO_CPP_EXAMPLES - macho_reader.cpp - macho_builder.cpp -) - -set(LIEF_OAT_CPP_EXAMPLES - oat_reader.cpp -) - -set(LIEF_VDEX_CPP_EXAMPLES - vdex_reader.cpp -) - -set(LIEF_ART_CPP_EXAMPLES - art_reader.cpp -) - -set(LIEF_DEX_CPP_EXAMPLES - dex_reader.cpp -) - set(LIEF_CPP_EXAMPLES - abstract_reader.cpp logging.cpp + disassembler.cpp + abstract_reader.cpp benchmark.cpp ) +if (LIEF_ELF AND LIEF_PE AND LIEF_MACHO) + list(APPEND LIEF_CPP_EXAMPLES + dwarf_inspect.cpp + pdb_inspect.cpp + objc_inspect.cpp + dyld_shared_cache_reader.cpp + dwarf_editor.cpp + ) +endif() + if (LIEF_ELF) - set(LIEF_CPP_EXAMPLES "${LIEF_CPP_EXAMPLES}" "${LIEF_ELF_CPP_EXAMPLES}") + list(APPEND LIEF_CPP_EXAMPLES + elf_reader.cpp + elf_add_section.cpp + elf_builder.cpp + elf_section_rename.cpp + elf_strip.cpp + elf_symbols.cpp + ) endif() if (LIEF_PE) - set(LIEF_CPP_EXAMPLES "${LIEF_CPP_EXAMPLES}" "${LIEF_PE_CPP_EXAMPLES}") + list(APPEND LIEF_CPP_EXAMPLES + pe_builder.cpp + pe_reader.cpp + pe_authenticode_check.cpp + ) endif() if (LIEF_MACHO) - set(LIEF_CPP_EXAMPLES "${LIEF_CPP_EXAMPLES}" "${LIEF_MACHO_CPP_EXAMPLES}") + list(APPEND LIEF_CPP_EXAMPLES + macho_reader.cpp + macho_builder.cpp + ) endif() if (LIEF_OAT) - set(LIEF_CPP_EXAMPLES ${LIEF_CPP_EXAMPLES} ${LIEF_OAT_CPP_EXAMPLES}) + list(APPEND LIEF_CPP_EXAMPLES + oat_reader.cpp + ) endif() if (LIEF_VDEX) - set(LIEF_CPP_EXAMPLES ${LIEF_CPP_EXAMPLES} ${LIEF_VDEX_CPP_EXAMPLES}) + list(APPEND LIEF_CPP_EXAMPLES + vdex_reader.cpp + ) endif() if (LIEF_ART) - set(LIEF_CPP_EXAMPLES ${LIEF_CPP_EXAMPLES} ${LIEF_ART_CPP_EXAMPLES}) + list(APPEND LIEF_CPP_EXAMPLES + art_reader.cpp + ) endif() if (LIEF_DEX) - set(LIEF_CPP_EXAMPLES ${LIEF_CPP_EXAMPLES} ${LIEF_DEX_CPP_EXAMPLES}) + list(APPEND LIEF_CPP_EXAMPLES + dex_reader.cpp + ) +endif() + +if (LIEF_RUNTIME) + if (LIEF_RUNTIME_PLATFORM_LINUX) + list(APPEND LIEF_CPP_EXAMPLES + runtime_linux.cpp + ) + endif() + + if (LIEF_RUNTIME_PLATFORM_WINDOWS) + list(APPEND LIEF_CPP_EXAMPLES + runtime_windows.cpp + ) + endif() + + if (LIEF_RUNTIME_PLATFORM_OSX) + list(APPEND LIEF_CPP_EXAMPLES + runtime_osx.cpp + ) + endif() + + if (LIEF_RUNTIME_PLATFORM_ANDROID) + list(APPEND LIEF_CPP_EXAMPLES + runtime_android.cpp + ) + endif() +endif() + +if(APPLE) + list(APPEND LIEF_CPP_EXAMPLES + macho_from_memory.cpp + ) endif() foreach(example ${LIEF_CPP_EXAMPLES}) string(REGEX REPLACE ".cpp\$" "" output_name "${example}") - add_executable("${output_name}" "${example}") + add_executable(${output_name} ${example}) # Don't use default include dir - set_property(TARGET "${output_name}" PROPERTY INCLUDE_DIRECTORIES "") - - if (MSVC) - set_property(TARGET "${output_name}" PROPERTY LINK_FLAGS /NODEFAULTLIB:MSVCRT) - target_compile_options("${output_name}" PUBLIC ${LIEF_CRT}) - endif() + set_property(TARGET "${output_name}" + PROPERTY INCLUDE_DIRECTORIES "" + ) set_target_properties( ${output_name} PROPERTIES POSITION_INDEPENDENT_CODE ON - CXX_STANDARD 11 - CXX_STANDARD_REQUIRED ON) + CXX_STANDARD_REQUIRED ON + INCLUDE_DIRECTORIES "") - if(CMAKE_COMPILER_IS_GNUCXX OR CMAKE_CXX_COMPILER_ID MATCHES "Clang") - if (UNIX) - if (LIEF_FORCE32) - target_compile_options("${output_name}" PRIVATE -m32) + if (${output_name} MATCHES "^runtime_") + set_target_properties(${output_name} PROPERTIES CXX_STANDARD 23) + else() + set_target_properties(${output_name} PROPERTIES CXX_STANDARD 17) + endif() - set_property(TARGET "${output_name}" PROPERTY LINK_FLAGS -m32) - endif() - endif() + target_link_libraries(${output_name} PUBLIC LIB_LIEF) + + if (LIEF_ASAN) + target_link_libraries(${output_name} INTERFACE libclang_rt.asan.a) endif() - target_link_libraries("${output_name}" PUBLIC LIB_LIEF) + if (LIEF_TSAN) + target_link_libraries(${output_name} INTERFACE libclang_rt.tsan.a) + endif() if (CMAKE_BUILD_TYPE MATCHES "Release") if (UNIX AND NOT APPLE) @@ -117,6 +147,7 @@ foreach(example ${LIEF_CPP_EXAMPLES}) ) endif() endif() + if(LIEF_INSTALL_COMPILED_EXAMPLES) install( TARGETS ${output_name} @@ -126,12 +157,11 @@ foreach(example ${LIEF_CPP_EXAMPLES}) endif() endforeach() - -install( - DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/ - DESTINATION share/LIEF/examples/cpp - COMPONENT examples - FILES_MATCHING REGEX "(.*).(hpp|h|cpp)$" -) - - +if (LIEF_INSTALL) + install( + DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/ + DESTINATION ${CMAKE_INSTALL_DATADIR}/LIEF/examples/cpp + COMPONENT examples + FILES_MATCHING REGEX "(.*).(hpp|h|cpp)$" + ) +endif() diff --git a/vendor/lief/examples/cpp/abstract_reader.cpp b/vendor/lief/examples/cpp/abstract_reader.cpp index 1628d77..d3aa169 100644 --- a/vendor/lief/examples/cpp/abstract_reader.cpp +++ b/vendor/lief/examples/cpp/abstract_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +18,7 @@ #include -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "Abstract Reader" << '\n'; if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; @@ -41,26 +41,24 @@ int main(int argc, char **argv) { } std::cout << "== Exported functions ==" << '\n'; - for(const LIEF::Function& func : binary->exported_functions()) { + for (const LIEF::Function& func : binary->exported_functions()) { std::cout << func << '\n'; } std::cout << "== Imported functions ==" << '\n'; - for(const LIEF::Function& func : binary->imported_functions()) { + for (const LIEF::Function& func : binary->imported_functions()) { std::cout << func << '\n'; } std::cout << "== Imported Libraries ==" << '\n'; - for(const std::string& name : binary->imported_libraries()) { + for (const std::string& name : binary->imported_libraries()) { std::cout << name << '\n'; } std::cout << "== Relocation ==" << '\n'; - for(const LIEF::Relocation& relocation : binary->relocations()) { + for (const LIEF::Relocation& relocation : binary->relocations()) { std::cout << relocation << '\n'; } return 0; - - } diff --git a/vendor/lief/examples/cpp/art_reader.cpp b/vendor/lief/examples/cpp/art_reader.cpp index f982b1e..650d6e4 100644 --- a/vendor/lief/examples/cpp/art_reader.cpp +++ b/vendor/lief/examples/cpp/art_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,8 +22,8 @@ using namespace LIEF::ART; -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -35,4 +35,3 @@ int main(int argc, char **argv) { return EXIT_FAILURE; } - diff --git a/vendor/lief/examples/cpp/benchmark.cpp b/vendor/lief/examples/cpp/benchmark.cpp index 4f8a61b..fa9cb16 100644 --- a/vendor/lief/examples/cpp/benchmark.cpp +++ b/vendor/lief/examples/cpp/benchmark.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,14 +13,14 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include #include +#include #include -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -33,8 +33,7 @@ int main(int argc, char **argv) { end = std::chrono::system_clock::now(); - size_t elapsed_seconds = std::chrono::duration_cast(end - start).count(); + size_t elapsed_seconds = + std::chrono::duration_cast(end - start).count(); std::cout << "[Parser] Time: " << std::dec << elapsed_seconds << "s" << '\n'; - } - diff --git a/vendor/lief/examples/cpp/dex_reader.cpp b/vendor/lief/examples/cpp/dex_reader.cpp index 636fd77..67fe91c 100644 --- a/vendor/lief/examples/cpp/dex_reader.cpp +++ b/vendor/lief/examples/cpp/dex_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,8 +22,8 @@ using namespace LIEF::DEX; -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -36,4 +36,3 @@ int main(int argc, char **argv) { return EXIT_FAILURE; } - diff --git a/vendor/lief/examples/cpp/disassembler.cpp b/vendor/lief/examples/cpp/disassembler.cpp new file mode 100644 index 0000000..a522ace --- /dev/null +++ b/vendor/lief/examples/cpp/disassembler.cpp @@ -0,0 +1,37 @@ +#include + +using namespace LIEF::logging; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + err("This example requires the extended version of LIEF"); + return EXIT_FAILURE; + } + + if (argc != 3) { + err("Usage: {}
    ", argv[0]); + return EXIT_FAILURE; + } + + std::unique_ptr target = LIEF::Parser::parse(argv[1]); + + if (target == nullptr) { + err("Can't parse: {}", argv[1]); + return EXIT_FAILURE; + } + + std::string add_str = argv[2]; + uint64_t addr = 0; + + if (add_str.size() > 2 && add_str[0] == '0' && add_str[1] == 'x') { + addr = std::strtoull(add_str.c_str() + 2, /*__endptr=*/nullptr, 16); + } else { + addr = std::strtoull(add_str.c_str(), /*__endptr=*/nullptr, 10); + } + + for (const LIEF::assembly::Instruction& inst : target->disassemble(addr)) { + info("{}", inst.to_string()); + } + + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/dwarf_editor.cpp b/vendor/lief/examples/cpp/dwarf_editor.cpp new file mode 100644 index 0000000..22ab2d6 --- /dev/null +++ b/vendor/lief/examples/cpp/dwarf_editor.cpp @@ -0,0 +1,42 @@ +#include +#include +#include +#include + +#include +#include + +using namespace LIEF::logging; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + std::cerr << "This example requires the extended version of LIEF\n"; + return EXIT_FAILURE; + } + + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return EXIT_FAILURE; + } + + std::unique_ptr pe = LIEF::PE::Parser::parse(argv[1]); + std::unique_ptr editor = + LIEF::dwarf::Editor::from_binary(*pe); + + std::unique_ptr unit = + editor->create_compilation_unit(); + unit->set_producer("LIEF"); + + std::unique_ptr func = + unit->create_function("hello"); + func->set_address(0x123); + + func->set_return_type(*unit->create_structure("my_struct_t")->pointer_to()); + + std::unique_ptr var = + func->create_stack_variable("local_var"); + + var->set_stack_offset(8); + editor->write("/tmp/out.debug"); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/dwarf_inspect.cpp b/vendor/lief/examples/cpp/dwarf_inspect.cpp new file mode 100644 index 0000000..3498783 --- /dev/null +++ b/vendor/lief/examples/cpp/dwarf_inspect.cpp @@ -0,0 +1,52 @@ +#include +#include +#include + +#include +#include + +using namespace LIEF::logging; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + std::cerr << "This example requires the extended version of LIEF\n"; + return EXIT_FAILURE; + } + + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return EXIT_FAILURE; + } + + set_level(Level::Info); + std::unique_ptr dbg = LIEF::dwarf::load(argv[1]); + if (!dbg) { + return EXIT_FAILURE; + } + for (const LIEF::dwarf::CompilationUnit& CU : dbg->compilation_units()) { + log(Level::Info, "Producer: {}", CU.producer()); + for (const LIEF::dwarf::Function& func : CU.functions()) { + log(Level::Info, "name={}, linkage={}, address={}", func.name(), + func.linkage_name(), std::to_string(func.address().value_or(0))); + } + + for (const LIEF::dwarf::Variable& var : CU.variables()) { + log(Level::Info, "name={}, address={}", var.name(), + std::to_string(var.address().value_or(0))); + } + + for (const LIEF::dwarf::Type& ty : CU.types()) { + log(Level::Info, "name={}, size={}", ty.name().value_or(""), + std::to_string(ty.size().value_or(0))); + } + } + + dbg->find_function("_ZNSi4peekEv"); + dbg->find_function("std::basic_istream >::peek()"); + dbg->find_function(0x137a70); + + dbg->find_variable("_ZNSt12out_of_rangeC1EPKc"); + dbg->find_function("std::out_of_range::out_of_range(char const*)"); + dbg->find_function(0x2773a0); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/dyld_shared_cache_reader.cpp b/vendor/lief/examples/cpp/dyld_shared_cache_reader.cpp new file mode 100644 index 0000000..71520d5 --- /dev/null +++ b/vendor/lief/examples/cpp/dyld_shared_cache_reader.cpp @@ -0,0 +1,35 @@ +#include +#include +#include + +#include + +using namespace LIEF::logging; + +static constexpr auto LOG_LVL = Level::Info; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + log(Level::Err, "This example requires the extended version of LIEF"); + return EXIT_FAILURE; + } + + if (argc != 2) { + log(Level::Err, "Usage: {} ", argv[0]); + return EXIT_FAILURE; + } + + set_level(Level::Info); + std::unique_ptr dyld_cache = + LIEF::dsc::load(argv[1]); + if (dyld_cache == nullptr) { + log(Level::Err, "Can't read {} as a shared cache file", argv[0]); + return EXIT_FAILURE; + } + + for (const LIEF::dsc::Dylib& lib : dyld_cache->libraries()) { + log(LOG_LVL, "{}: {}", std::to_string(lib.address()), lib.path()); + } + + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/elf_add_section.cpp b/vendor/lief/examples/cpp/elf_add_section.cpp index 26a3f25..adb9ecc 100644 --- a/vendor/lief/examples/cpp/elf_add_section.cpp +++ b/vendor/lief/examples/cpp/elf_add_section.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,18 +15,12 @@ */ #include #include -#include -#include -#include -#include - -#include #include using namespace LIEF::ELF; -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "ELF Section rename" << '\n'; if (argc != 3) { std::cerr << "Usage: " << argv[0] << " " << '\n'; diff --git a/vendor/lief/examples/cpp/elf_builder.cpp b/vendor/lief/examples/cpp/elf_builder.cpp index b39aa19..f6b206c 100644 --- a/vendor/lief/examples/cpp/elf_builder.cpp +++ b/vendor/lief/examples/cpp/elf_builder.cpp @@ -1,51 +1,57 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* ELF binary modification and rebuild. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Demonstrates how to parse an ELF binary, make modifications (add a section, + * add an exported symbol, change library search paths), and write the result. * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * Usage: ./elf_builder */ + #include #include -#include -#include -#include +#include -#include #include -int main(int argc, char **argv) { - std::cout << "ELF builder" << '\n'; +using namespace LIEF::ELF; + +int main(int argc, char** argv) { if (argc != 3) { - std::cerr << "Usage: " << argv[0] << " " << '\n'; - return -1; + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; } - std::unique_ptr binary = LIEF::ELF::Parser::parse(argv[1]); - LIEF::ELF::Segment seg; - seg.type(LIEF::ELF::SEGMENT_TYPES::PT_LOAD); - //seg.content(std::vector(0x100)); - //binary->add(seg); - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); - //LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_WARN); - //binary->get(LIEF::ELF::SEGMENT_TYPES::PT_GNU_RELRO).type(LIEF::ELF::SEGMENT_TYPES::PT_NULL); - LIEF::ELF::Builder builder{*binary}; - LIEF::ELF::Builder::config_t config; - config.force_relocate = true; + auto binary = Parser::parse(argv[1]); + if (binary == nullptr) { + std::cerr << "Failed to parse: " << argv[1] << "\n"; + return 1; + } + + // Add a new data section with custom content + Section new_section(".lief"); + new_section.type(Section::TYPE::PROGBITS); + new_section.add(Section::FLAGS::ALLOC); + std::vector content = {'L', 'I', 'E', 'F'}; + new_section.content(content); + binary->add(new_section); - builder.set_config(config); - builder.build(); - builder.write(argv[2]); + // Modify RUNPATH to add a custom library search directory + for (DynamicEntry& entry : binary->dynamic_entries()) { + if (auto* runpath = entry.cast()) { + std::string current{runpath->runpath()}; + if (!current.empty()) { + current += ':'; + } + runpath->runpath(current + "/opt/custom/lib"); + std::cout << "Updated RUNPATH: " << runpath->runpath() << "\n"; + break; + } + } - //binary->write(argv[2]); + // Write the modified binary with relocation support + Builder::config_t config; + config.force_relocate = true; + binary->write(argv[2], config); + std::cout << "Modified binary written to: " << argv[2] << "\n"; return 0; } diff --git a/vendor/lief/examples/cpp/elf_reader.cpp b/vendor/lief/examples/cpp/elf_reader.cpp index 2421b46..e8a9517 100644 --- a/vendor/lief/examples/cpp/elf_reader.cpp +++ b/vendor/lief/examples/cpp/elf_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,23 +22,24 @@ using namespace LIEF::ELF; -int main(int argc, char **argv) { +int main(int argc, char** argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; } - std::unique_ptr binary = std::unique_ptr{Parser::parse(argv[1])}; + std::unique_ptr binary = + std::unique_ptr{Parser::parse(argv[1])}; if (binary == nullptr) { return EXIT_FAILURE; } binary->functions(); - std::cout << "Binary: " << binary->name() << '\n'; + std::cout << "Binary: " << argv[1] << '\n'; std::cout << "Interpreter: " << binary->interpreter() << '\n'; std::cout << "== Header ==" << '\n'; std::cout << binary->header() << '\n'; @@ -60,10 +61,10 @@ int main(int argc, char **argv) { std::cout << entry << '\n'; } - auto static_symbols = binary->static_symbols(); - if (static_symbols.size() > 0) { - std::cout << "== Static symbols ==" << '\n'; - for (const Symbol& symbol : static_symbols) { + auto symtab_symbols = binary->symtab_symbols(); + if (symtab_symbols.size() > 0) { + std::cout << "== .symtab (debug) symbols ==" << '\n'; + for (const Symbol& symbol : symtab_symbols) { std::cout << symbol << '\n'; } } @@ -115,26 +116,5 @@ int main(int argc, char **argv) { } } - - - //std::cout << "== Symbol Version ==" << '\n'; - //std::vector* symbolsVersion = binary->get_symbol_version(); - //for (const auto &symVersion : *symbolsVersion) { - // std::cout << symVersion << '\n'; - //} - - - //std::cout << "== Symbols Version Requirement ==" << '\n'; - //std::vector *symR = binary->get_symbol_version_requirement(); - //for (SymbolVersionRequirement &symbolR : *symR) { - // std::cout << symbolR << '\n' << std::endl; - // auto symAux = symbolR.get_auxiliary_symbols(); - // for (auto &symbolAux : symAux) { - // std::cout << *symbolAux << '\n'; - // } - // std::cout << '\n'; - //} - return 0; - } diff --git a/vendor/lief/examples/cpp/elf_section_rename.cpp b/vendor/lief/examples/cpp/elf_section_rename.cpp index 4b792b8..91264b9 100644 --- a/vendor/lief/examples/cpp/elf_section_rename.cpp +++ b/vendor/lief/examples/cpp/elf_section_rename.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,19 +13,15 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +#include #include #include -#include -#include -#include -#include - -#include // // Rename the first section name. // Ex: ./tools/ELFSectionRename /bin/ls ./lsRename // +// ``` // $ readelf -S /bin/ls // // [Nr] Nom Type Adresse Décalage @@ -49,13 +45,13 @@ // [ 2] .note.ABI-tag NOTE 0000000000400254 00000254 // 0000000000000020 0000000000000000 A 0 0 4 // .... +// ``` // -// -// -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "ELF Section rename" << '\n'; if (argc != 3) { - std::cerr << "Usage: " << argv[0] << " " << '\n'; + std::cerr << "Usage: " << argv[0] << " " + << '\n'; return -1; } @@ -66,6 +62,4 @@ int main(int argc, char **argv) { binary->write(argv[2]); return 0; - - } diff --git a/vendor/lief/examples/cpp/elf_strip.cpp b/vendor/lief/examples/cpp/elf_strip.cpp index 5253ea9..197e022 100644 --- a/vendor/lief/examples/cpp/elf_strip.cpp +++ b/vendor/lief/examples/cpp/elf_strip.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,15 +13,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +#include #include #include -#include -#include -#include - -#include -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "ELF Strip" << '\n'; if (argc != 3) { std::cerr << "Usage: " << argv[0] << " " << '\n'; diff --git a/vendor/lief/examples/cpp/elf_symbols.cpp b/vendor/lief/examples/cpp/elf_symbols.cpp index ecf75ee..543fa6f 100644 --- a/vendor/lief/examples/cpp/elf_symbols.cpp +++ b/vendor/lief/examples/cpp/elf_symbols.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,7 +20,7 @@ using namespace LIEF::ELF; -int main(int argc, char **argv) { +int main(int argc, char** argv) { if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -44,5 +44,4 @@ int main(int argc, char **argv) { return 0; - } diff --git a/vendor/lief/examples/cpp/logging.cpp b/vendor/lief/examples/cpp/logging.cpp index c5091da..f7b30fa 100644 --- a/vendor/lief/examples/cpp/logging.cpp +++ b/vendor/lief/examples/cpp/logging.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +18,7 @@ #include -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "Abstract Reader" << '\n'; if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; @@ -28,9 +28,16 @@ int main(int argc, char **argv) { std::cout << "Parsing with DEBUG level" << '\n'; std::cout << "========================" << '\n'; - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); + LIEF::logging::set_level(LIEF::logging::Level::Debug); std::unique_ptr binary_global = LIEF::Parser::parse(argv[1]); + // Log a message with LIEF's logger + LIEF::logging::log(LIEF::logging::Level::Debug, "Hi!"); + + // Log a formatted message with LIEF's logger + LIEF::logging::log(LIEF::logging::Level::Debug, "Hi: {} here is your number: {}", + argv[0], std::to_string(argc)); + // Disable logger LIEF::logging::disable(); std::unique_ptr binary_debug = LIEF::Parser::parse(argv[1]); diff --git a/vendor/lief/examples/cpp/macho_builder.cpp b/vendor/lief/examples/cpp/macho_builder.cpp index f8d2b84..a84deba 100644 --- a/vendor/lief/examples/cpp/macho_builder.cpp +++ b/vendor/lief/examples/cpp/macho_builder.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,25 +13,14 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -// -// Description -// =========== -// The tool is used to test the rebuilding of a binary. -// It take a binary as first argument, decompose it, rebuild the binary and then -// save it (second argument) -// - #include #include -#include -#include -#include #include using namespace LIEF; -int main(int argc, char **argv) { +int main(int argc, char** argv) { std::cout << "MachO Rebuilder" << '\n'; if (argc != 3) { std::cerr << "Usage: " << argv[0] << " " << "\n"; diff --git a/vendor/lief/examples/cpp/macho_from_memory.cpp b/vendor/lief/examples/cpp/macho_from_memory.cpp new file mode 100644 index 0000000..43acf7d --- /dev/null +++ b/vendor/lief/examples/cpp/macho_from_memory.cpp @@ -0,0 +1,68 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include +#include + +using namespace LIEF::MachO; + +// Create a "fake" bss section +uint8_t data[0x4001]; +static struct foo { + uint64_t x[0x20]; +} bar; + +uintptr_t get_module_base_address(const std::string& name) { + const size_t nb_images = _dyld_image_count(); + for (size_t i = 0; i < nb_images; ++i) { + std::string image_name = _dyld_get_image_name(i); + std::cout << "Image at index #" << i << " :" << image_name << "\n"; + if (image_name.find(name) != std::string::npos) { + return reinterpret_cast(_dyld_get_image_header(i)); + } + } + + return 0; +} + +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); + + // const uintptr_t base = get_module_base_address("macho_from_memory"); + const uintptr_t base = get_module_base_address("in_mem.test"); + if (base == 0) { + return EXIT_FAILURE; + } + for (size_t i = 0; i < 234; ++i) { + data[i] = base & 0xFF; + } + bar.x[0] = 1; + memset(data, 0x4001, 1); + + std::cout << "Base address: 0x" << std::hex << base << "\n"; + std::unique_ptr binaries = Parser::parse_from_memory(base); + if (binaries == nullptr || binaries->empty()) { + std::cerr << "Parsing failed" << '\n'; + } + std::cout << "Parsing Done!" << "\n"; + for (Binary& bin : *binaries) { + bin.write("/tmp/mem_rewrite.bin"); + } + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/macho_reader.cpp b/vendor/lief/examples/cpp/macho_reader.cpp index 03b0973..6db002f 100644 --- a/vendor/lief/examples/cpp/macho_reader.cpp +++ b/vendor/lief/examples/cpp/macho_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,7 +17,6 @@ #include #include -#include using namespace LIEF::MachO; @@ -61,11 +60,10 @@ void print_binary(const Binary& binary) { for (const Relocation& relocation : binary.relocations()) { std::cout << relocation << '\n'; } - } -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); std::cout << "MachO Reader" << '\n'; if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; @@ -80,4 +78,3 @@ int main(int argc, char **argv) { return 0; } - diff --git a/vendor/lief/examples/cpp/oat_reader.cpp b/vendor/lief/examples/cpp/oat_reader.cpp index 846a178..fc40324 100644 --- a/vendor/lief/examples/cpp/oat_reader.cpp +++ b/vendor/lief/examples/cpp/oat_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,8 +22,8 @@ using namespace LIEF::OAT; -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -36,4 +36,3 @@ int main(int argc, char **argv) { return EXIT_FAILURE; } - diff --git a/vendor/lief/examples/cpp/objc_inspect.cpp b/vendor/lief/examples/cpp/objc_inspect.cpp new file mode 100644 index 0000000..91fea4d --- /dev/null +++ b/vendor/lief/examples/cpp/objc_inspect.cpp @@ -0,0 +1,50 @@ +#include +#include +#include +#include + +#include + +using namespace LIEF::logging; + +static constexpr auto LOG_LVL = Level::Info; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + log(Level::Err, "This example requires the extended version of LIEF"); + return EXIT_FAILURE; + } + + if (argc != 2) { + log(Level::Err, "Usage: {} ", argv[0]); + return EXIT_FAILURE; + } + + set_level(Level::Info); + std::unique_ptr fat = + LIEF::MachO::Parser::parse(argv[1]); + if (!fat) { + return EXIT_FAILURE; + } + LIEF::MachO::Binary* bin = fat->at(0); + if (!bin) { + return EXIT_FAILURE; + } + + std::unique_ptr metadata = bin->objc_metadata(); + if (!metadata) { + return EXIT_FAILURE; + } + + for (const LIEF::objc::Class& clazz : metadata->classes()) { + log(LOG_LVL, "name={}", clazz.name()); + for (const LIEF::objc::Method& meth : clazz.methods()) { + log(LOG_LVL, " method.name={}", meth.name()); + } + } + + log(LOG_LVL, metadata->to_decl()); + + + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/pdb_inspect.cpp b/vendor/lief/examples/cpp/pdb_inspect.cpp new file mode 100644 index 0000000..79f0c14 --- /dev/null +++ b/vendor/lief/examples/cpp/pdb_inspect.cpp @@ -0,0 +1,56 @@ +#include +#include +#include +#include +#include +#include + +using namespace LIEF::logging; + +int main(int argc, const char** argv) { + if (!LIEF::is_extended()) { + std::cerr << "This example requires the extended version of LIEF\n"; + return EXIT_FAILURE; + } + + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return EXIT_FAILURE; + } + + std::unique_ptr pdb = LIEF::pdb::load(argv[1]); + if (!pdb) { + return EXIT_FAILURE; + } + set_level(Level::Info); + + log(Level::Info, "age={}, guid={}", std::to_string(pdb->age()), pdb->guid()); + + for (const LIEF::pdb::PublicSymbol& symbol : pdb->public_symbols()) { + log(Level::Info, "name={}, section={}, RVA={}", symbol.name(), + symbol.section_name(), std::to_string(symbol.RVA())); + } + + for (const LIEF::pdb::Type& ty : pdb->types()) { + if (LIEF::pdb::types::Class::classof(&ty)) { + const auto* clazz = ty.as(); + log(Level::Info, "Class[name]={}", *clazz->name()); + } + } + + for (const LIEF::pdb::CompilationUnit& CU : pdb->compilation_units()) { + log(Level::Info, "module={}", CU.module_name()); + for (const std::string& src : CU.sources()) { + log(Level::Info, " - {}", src); + } + + for (const LIEF::pdb::Function& func : CU.functions()) { + log(Level::Info, "name={}, section={}, RVA={}, code size={}", func.name(), + func.section_name(), std::to_string(func.RVA()), + std::to_string(func.code_size())); + } + } + + + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/pe_authenticode_check.cpp b/vendor/lief/examples/cpp/pe_authenticode_check.cpp index bf5dd81..bb603a3 100644 --- a/vendor/lief/examples/cpp/pe_authenticode_check.cpp +++ b/vendor/lief/examples/cpp/pe_authenticode_check.cpp @@ -7,7 +7,7 @@ using namespace LIEF::PE; -int main(int argc, char **argv) { +int main(int argc, char** argv) { if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << "\n"; return 1; diff --git a/vendor/lief/examples/cpp/pe_builder.cpp b/vendor/lief/examples/cpp/pe_builder.cpp index 42e3864..5cb944f 100644 --- a/vendor/lief/examples/cpp/pe_builder.cpp +++ b/vendor/lief/examples/cpp/pe_builder.cpp @@ -1,53 +1,56 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* PE binary modification and rebuild. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Demonstrates how to parse a PE binary, make modifications (add a section, + * modify DLL characteristics, add an import), and write the result. * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * Usage: ./pe_builder */ -// -// Description -// =========== -// This program shows how to use the LIEF's PE Builder API. -// It takes a PE binary as input and write the reconstructed binary in the file -// given in the second argument. #include #include -#include -#include -#include +#include #include using namespace LIEF::PE; -int main(int argc, char **argv) { - std::cout << "PE Rebuilder" << '\n'; + +int main(int argc, char** argv) { if (argc != 3) { - std::cerr << "Usage: " << argv[0] << " " << '\n'; - return -1; + std::cerr << "Usage: " << argv[0] << " \n"; + return EXIT_FAILURE; + } + + auto binary = Parser::parse(argv[1]); + if (binary == nullptr) { + std::cerr << "Failed to parse: " << argv[1] << "\n"; + return EXIT_FAILURE; } - std::unique_ptr binary{Parser::parse(argv[1])}; - Builder builder{*binary}; + // Add a new section with custom data + Section new_section(".lief"); + new_section.add_characteristic(Section::CHARACTERISTICS::MEM_READ); + new_section.add_characteristic(Section::CHARACTERISTICS::CNT_INITIALIZED_DATA); + std::vector content = {'L', 'I', 'E', 'F'}; + new_section.content(content); + binary->add_section(new_section); - builder - .build_imports(false) - .patch_imports(false) - .build_tls(false) - .build_resources(false); + // Enable ASLR if not already enabled + auto& opt = binary->optional_header(); + if (!opt.has(OptionalHeader::DLL_CHARACTERISTICS::DYNAMIC_BASE)) { + opt.add(OptionalHeader::DLL_CHARACTERISTICS::DYNAMIC_BASE); + std::cout << "Enabled ASLR (DYNAMIC_BASE)\n"; + } + + // Enable NX/DEP if not already enabled + if (!opt.has(OptionalHeader::DLL_CHARACTERISTICS::NX_COMPAT)) { + opt.add(OptionalHeader::DLL_CHARACTERISTICS::NX_COMPAT); + std::cout << "Enabled DEP (NX_COMPAT)\n"; + } - builder.build(); - builder.write(argv[2]); - std::cout << binary->name() << '\n'; + // Write the modified binary + Builder::config_t config; + binary->write(argv[2], config); - return 0; + std::cout << "Modified binary written to: " << argv[2] << "\n"; + return EXIT_SUCCESS; } diff --git a/vendor/lief/examples/cpp/pe_reader.cpp b/vendor/lief/examples/cpp/pe_reader.cpp index e4b543f..e162385 100644 --- a/vendor/lief/examples/cpp/pe_reader.cpp +++ b/vendor/lief/examples/cpp/pe_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,15 +21,15 @@ using namespace LIEF::PE; -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); std::cout << "PE Reader" << '\n'; if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; - return -1; + return EXIT_FAILURE; } - std::unique_ptr binary{Parser::parse(argv[1])}; + std::unique_ptr binary = Parser::parse(argv[1]); std::cout << "== Dos Header ==" << '\n'; std::cout << binary->dos_header() << '\n'; @@ -40,9 +40,9 @@ int main(int argc, char **argv) { std::cout << "== Optional Header ==" << '\n'; std::cout << binary->optional_header() << '\n'; - if (binary->has_rich_header()) { + if (const LIEF::PE::RichHeader* rich_header = binary->rich_header()) { std::cout << "== Rich Header ==" << '\n'; - std::cout << binary->rich_header() << '\n'; + std::cout << *rich_header << '\n'; } std::cout << "== Data Directories ==" << '\n'; @@ -69,24 +69,23 @@ int main(int argc, char **argv) { } } - if (binary->has_tls()) { + if (const LIEF::PE::TLS* tls = binary->tls()) { std::cout << "== TLS ==" << '\n'; - std::cout << binary->tls() << '\n'; + std::cout << *tls << '\n'; } - if (binary->has_exports()) { + if (const LIEF::PE::Export* exp = binary->get_export()) { std::cout << "== Exports ==" << '\n'; - std::cout << binary->get_export() << '\n'; + std::cout << *exp << '\n'; } if (!binary->symbols().empty()) { std::cout << "== Symbols ==" << '\n'; - for (const Symbol& symbol : binary->symbols()) { + for (const LIEF::COFF::Symbol& symbol : binary->symbols()) { std::cout << symbol << '\n'; } } - if (binary->has_debug()) { std::cout << "== Debug ==" << '\n'; for (const Debug& debug : binary->debug()) { @@ -94,7 +93,6 @@ int main(int argc, char **argv) { } } - if (auto manager = binary->resources_manager()) { std::cout << "== Resources ==" << '\n'; std::cout << *manager << '\n'; diff --git a/vendor/lief/examples/cpp/runtime_android.cpp b/vendor/lief/examples/cpp/runtime_android.cpp new file mode 100644 index 0000000..18df7a5 --- /dev/null +++ b/vendor/lief/examples/cpp/runtime_android.cpp @@ -0,0 +1,265 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#if defined(LIEF_RUNTIME_PLATFORM_ANDROID) + #include +#endif + +using namespace LIEF::logging; + +inline std::string hex(uint64_t value) { + return std::format("{:#06x}", value); +} + +void host_info() { + info("Host"); + // lief-doc: host-start + info(" Hostname: {}", LIEF::runtime::Host::name()); + info(" Home: {}", LIEF::runtime::Host::home_dir()); + info(" Cache: {}", LIEF::runtime::Host::cache_dir()); + info(" Temp: {}", LIEF::runtime::Host::tmp_dir()); + info(" Config: {}", LIEF::runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-android-start + if (auto sdk = LIEF::runtime::android::Host::sdk_version()) { + info(" SDK: {}", std::to_string(*sdk)); + } + // lief-doc: host-android-end +} + +void process_info() { + info("Process"); + // lief-doc: process-start + info(" PID: {}", std::to_string(LIEF::runtime::Process::pid())); + info(" TID: {}", std::to_string(LIEF::runtime::Process::tid())); + info(" Page size: {}", hex(LIEF::runtime::Process::page_size())); + info(" Arch: {}", + std::to_string((uint32_t)LIEF::runtime::Process::arch())); + info(" Platform: {}", + std::to_string((uint32_t)LIEF::runtime::Process::platform())); + // lief-doc: process-end + + // lief-doc: process-android-start + if (auto prop = LIEF::runtime::android::Process::get_system_property( + "ro.build.version.sdk" + )) + { + info(" {}: {} (serial: {})", prop->name(), prop->value(), + std::to_string(prop->serial())); + } + + for (const auto& prop : LIEF::runtime::android::Process::properties()) { + info(" {}: {} (serial: {})", prop.name(), prop.value(), + std::to_string(prop.serial())); + } + // lief-doc: process-android-end +} + +void modules_info() { + info("Module API"); + std::unique_ptr libc; + // lief-doc: modules-start + for (const LIEF::runtime::Module& mod : LIEF::runtime::modules()) { + info("{}", mod.to_string()); + // Look for the Bionic C library + if (mod.name().ends_with("libc.so")) { + info("libc.so found: {} ([{}, {}])", mod.path(), hex(mod.imagebase()), + hex(mod.end())); + libc.reset(mod.clone().release()->as()); + } + } + // lief-doc: modules-end + + if (libc == nullptr) { + return; + } + + // lief-doc: modules-android-start + info("libc path: {}", libc->path()); + if (void* cxa_finalize = libc->dlsym("__cxa_finalize")) { + info("{}!__cxa_finalize: {}", libc->name(), + hex(reinterpret_cast(cxa_finalize))); + } + + if (void* malloc_fn = libc->dlsym("malloc")) { + auto malloc_ptr = reinterpret_cast(malloc_fn); + info("{}!malloc: {}", libc->name(), hex(malloc_ptr)); + + auto malloc_instructions = LIEF::runtime::disassemble(malloc_ptr); + + // Dump the first instructions of malloc + for (const LIEF::assembly::Instruction& inst : + malloc_instructions | std::views::take(4)) + { + info(" {}", inst.to_string()); + } + } + + if (std::unique_ptr elf_on_disk = libc->parse_from_path()) { + if (const LIEF::Symbol* sym = elf_on_disk->get_symbol("__cxa_finalize")) { + info("__cxa_finalize: {}", hex(sym->value())); + } + } + + if (std::unique_ptr liblog = + LIEF::runtime::android::dlopen("liblog.so")) + { + info("liblog loaded: {} (dlopen handle={})", liblog->path(), + hex(reinterpret_cast(liblog->handle()))); + + if (void* log_print = liblog->dlsym("__android_log_print")) { + info("{}!__android_log_print: {}", liblog->name(), + hex(reinterpret_cast(log_print))); + } + } + // lief-doc: modules-android-end +} + +void memory_example() { + info("Memory"); + // lief-doc: memory-start + using Mem = LIEF::runtime::Memory; + auto chunk = Mem::mmap(LIEF::runtime::Process::page_size(), + Mem::MP_ANONYMOUS | Mem::MP_PRIVATE, + Mem::P_READ | Mem::P_WRITE | Mem::P_EXEC); + + if (!chunk) { + return; + } + + struct Config : LIEF::assembly::AssemblerConfig { + std::optional resolve_symbol(const std::string& name) override { + std::unique_ptr libc = + LIEF::runtime::android::dlopen("libc.so"); + if (libc == nullptr) { + err("Failed to dlopen libc.so"); + return std::nullopt; + } + + if (name == "write") { + return reinterpret_cast(libc->dlsym("write")); + } + return std::nullopt; + } + } config; + + std::vector raw_inst = LIEF::runtime::assemble(chunk->addr(), R"asm( + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + ldr x8, =write + + mov x0, 1 // STDOUT_FILENO + adr x1, msg // buf = &msg + mov x2, 27 // len("LIEF Runtime Extended Demo\n") + blr x8 // write(STDOUT_FILENO, msg, 27) + + ldp x29, x30, [sp], 16 + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + )asm", + config); + + // Disassemble the JITed stub from memory + auto instructions = LIEF::runtime::disassemble(chunk->addr()); + for (const LIEF::assembly::Instruction& inst : + instructions | std::views::take(9)) + { + info("{}", inst.to_string()); + } + + // Dump as raw bytes + std::vector raw_bytes; + Mem::read(chunk->addr(), raw_bytes, raw_inst.size()); + std::string hex_bytes; + for (uint8_t byte : raw_bytes) { + if (!hex_bytes.empty()) { + hex_bytes += ':'; + } + hex_bytes += std::format("{:02x}", static_cast(byte)); + } + info("{}", hex_bytes); + + // Flush the instruction cache before executing the freshly written code. + // This is required on AArch64. + chunk->cache_flush(); + + // Change the permission to R-X and invoke the JITed function + chunk->make_rx(); + + using shellcode_t = void (*)(); + auto hello_jit = reinterpret_cast(chunk->addr()); + hello_jit(); + + // Change the message + const char new_msg[] = "Hello C++ runtime World!\n"; + std::string_view view_inst(reinterpret_cast(raw_inst.data()), + raw_inst.size()); + size_t pos = view_inst.find("LIEF Runtime"); + assert(pos != std::string_view::npos); + chunk->make_rw(); + Mem::write(reinterpret_cast(new_msg), sizeof(new_msg) - 1, + chunk->addr() + pos); + chunk->make_rx(); + chunk->cache_flush(); + + hello_jit(); + + // Don't miss good practices! + (void)chunk->deallocate(); + // lief-doc: memory-end +} + +int main(int /*argc*/, char** /*argv*/) { +#if defined(LIEF_RUNTIME_PLATFORM_ANDROID) + __android_log_set_logger(__android_log_stderr_logger); +#endif + LIEF::logging::Scoped scope(Level::Info); + if (!LIEF::runtime::is_enabled()) { + err("LIEF's runtime is not enabled"); + return EXIT_SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/runtime_linux.cpp b/vendor/lief/examples/cpp/runtime_linux.cpp new file mode 100644 index 0000000..5e3ea58 --- /dev/null +++ b/vendor/lief/examples/cpp/runtime_linux.cpp @@ -0,0 +1,220 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +using namespace LIEF::logging; + +inline std::string hex(uint64_t value) { + return std::format("{:#06x}", value); +} + +void host_info() { + info("Host"); + // lief-doc: host-start + info(" Hostname: {}", LIEF::runtime::Host::name()); + info(" Home: {}", LIEF::runtime::Host::home_dir()); + info(" Cache: {}", LIEF::runtime::Host::cache_dir()); + info(" Temp: {}", LIEF::runtime::Host::tmp_dir()); + info(" Config: {}", LIEF::runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-linux-start + info(" sys_name: {}", LIEF::runtime::Linux::Host::sys_name()); + info(" sys_release: {}", LIEF::runtime::Linux::Host::sys_release()); + info(" sys_version: {}", LIEF::runtime::Linux::Host::sys_version()); + info(" hardware: {}", LIEF::runtime::Linux::Host::hardware()); + // lief-doc: host-linux-end +} + +void process_info() { + info("Process"); + // lief-doc: process-start + info(" PID: {}", std::to_string(LIEF::runtime::Process::pid())); + info(" TID: {}", std::to_string(LIEF::runtime::Process::tid())); + info(" Page size: {}", hex(LIEF::runtime::Process::page_size())); + info(" Arch: {}", + std::to_string((uint32_t)LIEF::runtime::Process::arch())); + info(" Platform: {}", + std::to_string((uint32_t)LIEF::runtime::Process::platform())); + if (auto term = LIEF::runtime::Process::get_env("TERM")) { + info(" TERM: {}", *term); + } + // lief-doc: process-end + + // lief-doc: process-linux-start + info(" glibc: {}", LIEF::runtime::Linux::Process::glibc_version()); + // lief-doc: process-linux-end +} + +void modules_info() { + info("Module API"); + std::unique_ptr libc; + // lief-doc: modules-start + for (const LIEF::runtime::Module& mod : LIEF::runtime::modules()) { + info("{}", mod.to_string()); + // Look for the libc + if (mod.name().ends_with("libc.so")) { + info("libc.so found: {} ([{}, {}])", mod.path(), hex(mod.imagebase()), + hex(mod.end())); + libc.reset(mod.clone().release()->as()); + } + } + // lief-doc: modules-end + + if (libc == nullptr) { + return; + } + + // lief-doc: modules-linux-start + info("libc path: {}", libc->path()); + if (void* cxa_finalize = libc->dlsym("__cxa_finalize")) { + info("{}!__cxa_finalize: {}", libc->name(), + hex(reinterpret_cast(cxa_finalize))); + } + + if (void* malloc_fn = libc->dlsym("malloc")) { + auto malloc_ptr = reinterpret_cast(malloc_fn); + info("{}!malloc: {}", libc->name(), + hex(reinterpret_cast(malloc_fn))); + auto malloc_instructions = LIEF::runtime::disassemble(malloc_ptr); + + // Dump the first instructions of malloc + for (const LIEF::assembly::Instruction& inst : + malloc_instructions | std::views::take(4)) + { + info(" {}", inst.to_string()); + } + } + + // This parses the ELF from its path on the disk + if (std::unique_ptr elf_on_disk = libc->parse_from_path()) { + if (const LIEF::Symbol* sym = elf_on_disk->get_symbol("__cxa_finalize")) { + info("__cxa_finalize: {}", hex(sym->value())); + } + } + + // This code loads 'librt.so' and wraps the dlopen handle in a Module. + if (std::unique_ptr librt = + LIEF::runtime::Linux::dlopen("librt.so.1")) + { + info("librt loaded: {} (dlopen handle={})", librt->path(), + hex(reinterpret_cast(librt->handle()))); + + // Alternately you could do this: + { + void* handle = dlopen("librt.so.1", RTLD_NOW); + auto librt_alt = LIEF::runtime::Linux::Module::from_handle(handle); + } + + // Parse the ELF directly from memory. + if (std::unique_ptr librt_mem = librt->parse_from_memory()) + { + // Look for the relocation associated with the **imported** symbol + // `__cxa_finalize` that is defined in the libc. The relocation holds + // the address where the function is resolved. Reading this address + // gives back the same value previously returned by dlsym. + for (const auto& reloc : librt_mem->relocations()) { + const auto* sym = reloc.symbol(); + if (sym == nullptr || sym->name() != "__cxa_finalize") { + continue; + } + uintptr_t abs_reloc_addr = librt->imagebase() + reloc.address(); + auto resolved = LIEF::runtime::Memory::read(abs_reloc_addr); + info("{} -> {} -> {}", librt->name(), hex(abs_reloc_addr), hex(resolved)); + break; + } + } + } + // lief-doc: modules-linux-end +} + +void memory_example() { + info("Memory"); + // lief-doc: memory-start + using Mem = LIEF::runtime::Memory; + auto chunk = Mem::mmap(LIEF::runtime::Process::page_size(), + Mem::MP_ANONYMOUS | Mem::MP_PRIVATE, + Mem::P_READ | Mem::P_WRITE | Mem::P_EXEC); + + if (!chunk) { + return; + } + + std::vector raw_inst = LIEF::runtime::assemble(chunk->addr(), R"asm( + .global _start + + .text + _start: + push 1 + pop rax + mov edi, eax + lea rsi, [rip + msg] + mov rdx, 28 + syscall + ret + + msg: + .ascii "LIEF Runtime Extended Demo\n" + )asm"); + + // Change the permission to R-X and invoke the JITed function + chunk->make_rx(); + + using shellcode_t = void (*)(); + auto hello_jit = reinterpret_cast(chunk->addr()); + hello_jit(); + + const char new_msg[] = "Hello C++ runtime World!\n\0"; + std::string_view view_inst(reinterpret_cast(raw_inst.data()), + raw_inst.size()); + size_t pos = view_inst.find("LIEF Runtime Extended"); + assert(pos != std::string_view::npos); + chunk->make_rw(); + Mem::write(reinterpret_cast(new_msg), sizeof(new_msg) - 1, + chunk->addr() + pos); + chunk->make_rx(); + + hello_jit(); + + // Don't miss good practices! + (void)chunk->deallocate(); + // lief-doc: memory-end +} + +int main(int /*argc*/, char** /*argv*/) { + LIEF::logging::Scoped scope(Level::Info); + if (!LIEF::runtime::is_enabled()) { + err("LIEF's runtime is not enabled"); + return EXIT_SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/runtime_osx.cpp b/vendor/lief/examples/cpp/runtime_osx.cpp new file mode 100644 index 0000000..33ee8df --- /dev/null +++ b/vendor/lief/examples/cpp/runtime_osx.cpp @@ -0,0 +1,247 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +using namespace LIEF::logging; + +inline std::string hex(uint64_t value) { + return std::format("{:#06x}", value); +} + +void host_info() { + info("Host"); + // lief-doc: host-start + info(" Hostname: {}", LIEF::runtime::Host::name()); + info(" Home: {}", LIEF::runtime::Host::home_dir()); + info(" Cache: {}", LIEF::runtime::Host::cache_dir()); + info(" Temp: {}", LIEF::runtime::Host::tmp_dir()); + info(" Config: {}", LIEF::runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-osx-start + info(" Version: {}", LIEF::runtime::osx::Host::os_version_name()); + info(" SIP: {}", + LIEF::runtime::osx::Host::is_sip_enabled() ? "enabled" : "disabled"); + // lief-doc: host-osx-end +} + +void process_info() { + info("Process"); + // lief-doc: process-start + info(" PID: {}", std::to_string(LIEF::runtime::Process::pid())); + info(" TID: {}", std::to_string(LIEF::runtime::Process::tid())); + info(" Page size: {}", hex(LIEF::runtime::Process::page_size())); + info(" Arch: {}", + std::to_string((uint32_t)LIEF::runtime::Process::arch())); + info(" Platform: {}", + std::to_string((uint32_t)LIEF::runtime::Process::platform())); + // lief-doc: process-end + + // lief-doc: process-osx-start + info(" dyld: {}", LIEF::runtime::osx::Process::dyld_version()); + // lief-doc: process-osx-end +} + +void modules_info() { + info("Module API"); + + // Module referencing libsystem_c.dylib in memory + std::unique_ptr libsystem; + + // lief-doc: modules-start + auto mods = LIEF::runtime::modules(); + for (auto it = mods.begin(); it != mods.end(); ++it) { + info("{}", it->to_string()); + // Look for the C library + if (it->name().ends_with("libsystem_c.dylib")) { + info("libsystem_c.dylib found: {} ([{}, {}])", it->path(), + hex(it->imagebase()), hex(it->end())); + // Transfer ownership so 'libsystem' outlives this loop + std::unique_ptr mod = it.yield(); + libsystem.reset(mod.release()->as()); + } + } + // lief-doc: modules-end + + if (libsystem == nullptr) { + return; + } + + // lief-doc: modules-osx-start + info("libsystem_c path: {}", libsystem->path()); + if (void* p_arc4_init = libsystem->dlsym("arc4_init")) { + info("{}!arc4_init: {}", libsystem->name(), + hex(reinterpret_cast(p_arc4_init))); + + // Disassemble malloc directly from its resolved memory address + auto instructions = + LIEF::runtime::disassemble(reinterpret_cast(p_arc4_init)); + for (const LIEF::assembly::Instruction& inst : + instructions | std::views::take(4)) + { + info(" {}", inst.to_string()); + } + } + + // libsystem->path() looks like a valid path but libsystem_c.dylib lives + // in the dyld-shared-cache. Therefore, it's pointless to try to parse the + // library from its filepath as the library does not exist on the disk + std::unique_ptr macho_on_disk; + { + LIEF::logging::Scoped disable_logger(LIEF::logging::Level::Off); + macho_on_disk = libsystem->parse_from_path(); + } + if (macho_on_disk == nullptr) { + info("As expected, {} is not present in the filesystem", libsystem->path()); + } + + // But we can parse it from memory: + if (std::unique_ptr macho_memory = + libsystem->parse_from_memory()) + { + info("in-memory imagebase: {}", hex(macho_memory->imagebase())); + for (const LIEF::MachO::Symbol& S : macho_memory->exported_symbols()) { + info(std::format("{:10}: {:#010x}", S.name(), S.value())); + } + } + // lief-doc: modules-osx-end +} + +void memory_example() { + info("Memory"); + // lief-doc: memory-start + // The JIT below allocates and executes RWX memory. On macOS this is only + // permitted when SIP is disabled. + if (LIEF::runtime::osx::Host::is_sip_enabled()) { + warn("SIP is enabled: skipping the JIT memory example"); + return; + } + + using Mem = LIEF::runtime::Memory; + // Note the `MP_JIT` here that is used to switch the allocated chunk into R-X + // once the shellcode is committed. + auto chunk = Mem::mmap(LIEF::runtime::Process::page_size(), + Mem::MP_ANONYMOUS | Mem::MP_PRIVATE | Mem::MP_JIT, + Mem::P_READ | Mem::P_WRITE); + + if (!chunk) { + return; + } + + class Config : public LIEF::assembly::AssemblerConfig { + public: + std::optional resolve_symbol(const std::string& name) override { + // The message to print + static constexpr char HELLO[] = "Hello World\n"; + static constexpr uint32_t HELLO_LEN = sizeof(HELLO) - 1; + + // libSystem re-exports the libc symbols (write, ...) + static auto libsystem = LIEF::runtime::osx::dlopen("libSystem.B.dylib"); + + if (libsystem == nullptr) { + err("Failed to dlopen libSystem.B.dylib"); + return std::nullopt; + } + + // Resolve the symbols that are used by the shellcode + if (name == "write") { + return reinterpret_cast(libsystem->dlsym("write")); + } + + if (name == "var_msg") { + return reinterpret_cast(HELLO); + } + + if (name == "var_msg_len") { + return HELLO_LEN; + } + + return std::nullopt; + } + }; + + Config config; + + // clang-format off + + // Shellcode dynamically compiled and whose referenced symbols are resolved + // at runtime by the provided Config + std::vector raw_inst = LIEF::runtime::assemble(chunk->addr(), R"asm( + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -16]! + mov x29, sp + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x8, =write // write(2) libc wrapper + ldr x1, =var_msg // buffer + ldr w2, =var_msg_len // length + + // write(STDOUT_FILENO, msg, len) + mov x0, 1 + blr x8 + + mov x0, xzr + ldp x29, x30, [sp], 16 + ret + )asm", config); + // clang-format on + + // Flush the instruction cache + chunk->cache_flush(); + + // Change the permission to R-X and invoke the JITed function. + chunk->make_rx(); + + using shellcode_t = void (*)(); + auto hello_jit = reinterpret_cast(chunk->addr()); + + // This call prints the message "Hello World" on the console + hello_jit(); + + // Don't miss good practices! + (void)chunk->deallocate(); + // lief-doc: memory-end +} + +int main(int /*argc*/, char** /*argv*/) { + LIEF::logging::Scoped scope(Level::Info); + if (!LIEF::runtime::is_enabled()) { + err("LIEF's runtime is not enabled"); + return EXIT_SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/runtime_windows.cpp b/vendor/lief/examples/cpp/runtime_windows.cpp new file mode 100644 index 0000000..136a398 --- /dev/null +++ b/vendor/lief/examples/cpp/runtime_windows.cpp @@ -0,0 +1,326 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +using namespace LIEF::logging; + +inline std::string hex(uint64_t value) { + return std::format("{:#06x}", value); +} + +void host_info() { + info("Host"); + // lief-doc: host-start + info(" Hostname: {}", LIEF::runtime::Host::name()); + info(" Home: {}", LIEF::runtime::Host::home_dir()); + info(" Cache: {}", LIEF::runtime::Host::cache_dir()); + info(" Temp: {}", LIEF::runtime::Host::tmp_dir()); + info(" Config: {}", LIEF::runtime::Host::config_dir()); + // lief-doc: host-end + + // lief-doc: host-windows-start + info(" Version: {}", LIEF::runtime::windows::Host::version().to_string()); + // lief-doc: host-windows-end +} + +void process_info() { + info("Process"); + // lief-doc: process-start + info(" PID: {}", std::to_string(LIEF::runtime::Process::pid())); + info(" TID: {}", std::to_string(LIEF::runtime::Process::tid())); + info(" Page size: {}", hex(LIEF::runtime::Process::page_size())); + info(" Arch: {}", + std::to_string((uint32_t)LIEF::runtime::Process::arch())); + info(" Platform: {}", + std::to_string((uint32_t)LIEF::runtime::Process::platform())); + if (auto userdomain = LIEF::runtime::Process::get_env("USERDOMAIN")) { + info(" USERDOMAIN:{}", *userdomain); + } + // lief-doc: process-end + + // lief-doc: process-windows-start + if (auto peb = LIEF::runtime::windows::Process::peb()) { + info(" PEB.BeingDebugged: {}", + peb->being_debugged() ? "true" : "false"); + info(" PEB.Ldr: {}", hex(peb->ldr())); + info(" PEB.ProcessParameters: {}", hex(peb->process_parameters())); + info(" PEB.AtlThunkSListPtr: {}", hex(peb->atl_thunk_slist_ptr())); + info(" PEB.AtlThunkSListPtr32: {}", hex(peb->atl_thunk_slist_ptr32())); + info(" PEB.PostProcessInitRoutine: {}", + hex(peb->post_process_init_routine())); + info(" PEB.SessionId: {}", hex(peb->session_id())); + } + // lief-doc: process-windows-end + + // lief-doc: peb-modules-start + if (auto peb = LIEF::runtime::windows::Process::peb()) { + auto entries = peb->entries(); + + size_t count = 0; + for (const auto& entry : entries) { + if (count < 3) { + info(" module[{}]: {} (base={}, size={})", std::to_string(count), + entry.base_dll_name(), hex(entry.dll_base()), + hex(entry.size_of_image())); + } + ++count; + } + info(" -> {} modules in the load order list", std::to_string(count)); + + // LdrDataTableEntry::Iterator is bidirectional: step back from the + // past-the-end position to reach the last loaded module. + if (count > 0) { + auto it = entries.end(); + --it; + info(" last module (walking backwards): {}", it->base_dll_name()); + } + } + // lief-doc: peb-modules-end + + // lief-doc: peb-module-details-start + if (auto peb = LIEF::runtime::windows::Process::peb()) { + auto entries = peb->entries(); + auto it = entries.begin(); + if (it != entries.end()) { + info(" {} extended LDR_DATA_TABLE_ENTRY fields:", it->base_dll_name()); + + // Always available across the supported Windows versions: + info(" Flags: {}", hex(it->flags())); + info(" ObsoleteLoadCount: {}", + std::to_string(it->obsolete_load_count())); + info(" TlsIndex: {}", hex(it->tls_index())); + info(" TimeDateStamp: {}", hex(it->time_date_stamp())); + + // Version-gated fields: each optional is empty when the host kernel + // predates the field, so the OS version drives what gets printed. + if (auto v = it->ddag_node()) { // Windows 8+ + info(" DdagNode: {}", hex(*v)); + } + if (auto v = it->original_base()) { // Windows 8+ + info(" OriginalBase: {}", hex(*v)); + } + if (auto v = it->load_reason()) { // Windows 8+ + info(" LoadReason: {}", std::to_string(*v)); + } + if (auto v = it->signing_level()) { // Windows 10+ + info(" SigningLevel: {}", std::to_string((uint32_t)*v)); + } + if (auto v = it->check_sum()) { // Windows 10+ + info(" CheckSum: {}", hex(*v)); + } + if (auto v = it->hot_patch_state()) { // Windows 11+ + info(" HotPatchState: {}", std::to_string(*v)); + } + } + } + // lief-doc: peb-module-details-end +} + +void modules_info() { + info("Module API"); + std::unique_ptr ntdll; + // lief-doc: modules-start + auto mods = LIEF::runtime::modules(); + for (auto it = mods.begin(); it != mods.end(); ++it) { + info("{}", it->to_string()); + // Look for the libc + if (it->name().ends_with("ntdll.dll")) { + info("ntdll.dll found: {} ([{}, {}])", it->path(), hex(it->imagebase()), + hex(it->end())); + // Transfer ownership so 'ntdll' outlives this loop + std::unique_ptr mod = it.yield(); + ntdll.reset(mod.release()->as()); + } + } + // lief-doc: modules-end + + if (ntdll == nullptr) { + return; + } + + // lief-doc: modules-windows-start + info("ntdll path: {}", ntdll->path()); + if (void* _NtQueryInformationProcess = ntdll->dlsym("NtQueryInformationProcess")) + { + info("{}!NtQueryInformationProcess: {}", ntdll->name(), + hex(reinterpret_cast(_NtQueryInformationProcess))); + } + + if (std::unique_ptr pe_on_disk = ntdll->parse_from_path()) { + info("on-disk imagebase: {}", hex(pe_on_disk->optional_header().imagebase())); + if (const LIEF::Symbol* sym = + pe_on_disk->get_symbol("NtQueryInformationProcess")) + { + info("NtQueryInformationProcess: {}", hex(sym->value())); + } + } + + if (std::unique_ptr pe_memory = ntdll->parse_from_memory()) { + const uintptr_t imagebase = pe_memory->optional_header().imagebase(); + info("in-memory imagebase: {}", hex(imagebase)); + if (const LIEF::Symbol* sym = pe_memory->get_symbol("RtlFreeHeap")) { + info("RtlFreeHeap: {}", hex(sym->value())); + + // Disassemble RtlFreeHeap from memory + auto instructions = LIEF::runtime::disassemble(imagebase + sym->value()); + auto first_instructions = instructions | std::views::take(4); + + for (const LIEF::assembly::Instruction& inst : first_instructions) { + info(" {}", inst.to_string()); + } + } + } + // lief-doc: modules-windows-end +} + +void memory_example() { + info("Memory"); + // lief-doc: memory-start + using Mem = LIEF::runtime::Memory; + auto chunk = Mem::mmap(LIEF::runtime::Process::page_size(), + Mem::MP_ANONYMOUS | Mem::MP_PRIVATE, + Mem::P_READ | Mem::P_WRITE | Mem::P_EXEC); + + if (!chunk) { + return; + } + + class Config : public LIEF::assembly::AssemblerConfig { + public: + std::optional resolve_symbol(const std::string& name) override { + // The message to print + static constexpr char HELLO[] = "Hello World\n"; + static constexpr uint32_t HELLO_LEN = sizeof(HELLO) - 1; + + static auto kernel32 = LIEF::runtime::windows::dlopen("kernel32.dll"); + + if (kernel32 == nullptr) { + err("Failed to dlopen kernel32.dll"); + return std::nullopt; + } + + // Resolve the symbols that are used by the shellcode + if (name == "GetStdHandle") { + return reinterpret_cast(kernel32->dlsym("GetStdHandle")); + } + + if (name == "WriteFile") { + return reinterpret_cast(kernel32->dlsym("WriteFile")); + } + + if (name == "var_msg") { + return reinterpret_cast(HELLO); + } + + if (name == "var_msg_len") { + return HELLO_LEN; + } + + return std::nullopt; + } + }; + + Config config; + + // clang-format off + + // Shellcode dynamically compiled and whose referenced symbols are resolved + // at runtime by the provided Config + std::vector raw_inst = LIEF::runtime::assemble(chunk->addr(), R"asm( + .text + .global main + .align 2 + + main: + stp x29, x30, [sp, -64]! + mov x29, sp + stp x19, x20, [sp, 16] + stp x21, x22, [sp, 32] + + // Here we use symbols that are **dynamically** resolved by the + // AssemblerConfig + ldr x19, =GetStdHandle + ldr x20, =WriteFile + ldr x21, =var_msg + ldr w22, =var_msg_len + + // Call GetStdHandle(STD_OUTPUT_HANDLE) + // STD_OUTPUT_HANDLE = -11 + // GetStdHandle is stored in x19 + mov w0, -11 + blr x19 + + // Call ---> bool WriteFile( + // HANDLE hConsoleOutput, // x0: from GetStdHandle (already set) + // const VOID *lpBuffer, // x1: pointer to string + // DWORD nNumberOfCharsToWrite, // w2: length of string + // LPDWORD lpNumberOfCharsWritten,// x3: pointer to written count + // LPVOID lpReserved // x4: NULL + // ); + mov x1, x21 + mov w2, w22 + add x3, sp, 48 + mov x4, xzr + blr x20 + + mov x0, xzr + ldp x21, x22, [sp, 32] + ldp x19, x20, [sp, 16] + ldp x29, x30, [sp], 64 + ret + )asm", config); + // clang-format on + + // Flush the instruction cache + chunk->cache_flush(); + + // Change the permission to R-X and invoke the JITed function. + chunk->make_rx(); + + using shellcode_t = void (*)(); + auto hello_jit = reinterpret_cast(chunk->addr()); + + // This call prints the message "Hello World" on the console + hello_jit(); + + // Don't miss good practices! + (void)chunk->deallocate(); + // lief-doc: memory-end +} + +int main(int /*argc*/, char** /*argv*/) { + LIEF::logging::Scoped scope(Level::Info); + if (!LIEF::runtime::is_enabled()) { + err("LIEF's runtime is not enabled"); + return EXIT_SUCCESS; + } + + host_info(); + process_info(); + modules_info(); + memory_example(); + return EXIT_SUCCESS; +} diff --git a/vendor/lief/examples/cpp/vdex_reader.cpp b/vendor/lief/examples/cpp/vdex_reader.cpp index 77a6c5d..9583a88 100644 --- a/vendor/lief/examples/cpp/vdex_reader.cpp +++ b/vendor/lief/examples/cpp/vdex_reader.cpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,8 +22,8 @@ using namespace LIEF::VDEX; -int main(int argc, char **argv) { - LIEF::logging::set_level(LIEF::logging::LOGGING_LEVEL::LOG_DEBUG); +int main(int argc, char** argv) { + LIEF::logging::set_level(LIEF::logging::Level::Debug); if (argc != 2) { std::cerr << "Usage: " << argv[0] << " " << '\n'; return EXIT_FAILURE; @@ -38,4 +38,3 @@ int main(int argc, char **argv) { } return EXIT_FAILURE; } - diff --git a/vendor/lief/examples/python b/vendor/lief/examples/python new file mode 120000 index 0000000..a7a2e33 --- /dev/null +++ b/vendor/lief/examples/python @@ -0,0 +1 @@ +../api/python/examples \ No newline at end of file diff --git a/vendor/lief/examples/python/abstract_json.py b/vendor/lief/examples/python/abstract_json.py deleted file mode 100644 index 8a64632..0000000 --- a/vendor/lief/examples/python/abstract_json.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Dump abstract informations in a JSON format -# see: abstract_reader.py - -import argparse -import sys -import lief -import json - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('binary', help = 'A binary') - args = parser.parse_args() - - binary = lief.parse(args.binary) - json_data = json.loads(lief.to_json_from_abstract(binary)) - print(json.dumps(json_data, sort_keys = True, indent = 4)) - -if __name__ == "__main__": - sys.exit(main()) - diff --git a/vendor/lief/examples/python/abstract_reader.py b/vendor/lief/examples/python/abstract_reader.py deleted file mode 100644 index 908555f..0000000 --- a/vendor/lief/examples/python/abstract_reader.py +++ /dev/null @@ -1,213 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Universal format reader. -# Input can be PE, ELF or Mach-O - -import lief -import sys -import argparse -import traceback - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - - - -@exceptions_handler(Exception) -def print_header(binary): - header = binary.header - - print("== Header ==\n") - format_str = "{:<15} {:<30}" - format_hex = "{:<15} 0x{:<13x}" - format_dec = "{:<15} {:<30d}" - - - modes_str = " - ".join([str(m).split(".")[-1] for m in header.modes]) - bitness = "" - if header.is_32: - bitness = "32-bits" - - if header.is_64: - bitness = "64-bits" - - - print(format_str.format("Architecture:", str(header.architecture).split(".")[-1])) - print(format_str.format("Modes:", modes_str)) - print(format_hex.format("Entrypoint:", header.entrypoint)) - print(format_str.format("Object type:", str(header.object_type).split(".")[-1])) - print(format_str.format("Endianness:", str(header.endianness).split(".")[-1])) - print(format_str.format("Bitness:", bitness)) - print("") - - -@exceptions_handler(Exception) -def print_sections(binary): - print("== Sections ==") - f_title = "|{:<30} | {:<18}| {:<18}| {:<18}| {:<9}|" - f_value = "|{:<30} | 0x{:<16x}| 0x{:<16x}| 0x{:<16x}| {:<9.2f}|" - print(f_title.format("Name", "File offset", "Size", "Virtual Address", "Entropy")) - for section in binary.sections: - print(f_value.format(\ - section.name,\ - section.offset,\ - section.size,\ - section.virtual_address,\ - section.entropy)) - print("") - - -@exceptions_handler(Exception) -def print_relocations(binary): - print("== Relocations ==") - f_title = "|{:<18} | {:<6}|" - f_value = "|0x{:<16x} | {:<6d}|" - print(f_title.format("Address", "Size")) - for relocation in binary.relocations: - print(f_value.format(\ - relocation.address,\ - relocation.size)) - print("") - -@exceptions_handler(Exception) -def print_symbols(binary): - - print("== Symbols ==") - - f = "|{:<30} |" - - print(f.format("Name")) - - for symbol in binary.symbols: - print(f.format(symbol.name)) - print("") - - -@exceptions_handler(Exception) -def print_exported_functions(binary): - - print("== Exported functions ==") - f = "|{:<30} |" - print(f.format("Name")) - for func in binary.exported_functions: - print(f.format(func)) - print("") - -@exceptions_handler(Exception) -def print_imported_functions(binary): - - print("== Imported functions ==") - f = "|{:<30} |" - print(f.format("Name")) - for func in binary.imported_functions: - print(f.format(func)) - print("") - - -@exceptions_handler(Exception) -def print_imported_libraries(binary): - - print("== Imported Libraries ==") - f = "|{:<30} |" - print(f.format("Name")) - for library in binary.libraries: - print(f.format(library)) - print("") - -def main(): - parser = argparse.ArgumentParser(usage='%(prog)s [options] ') - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-H', '--header', - action='store_true', dest='show_header', - help='Display header') - - parser.add_argument('-i', '--imported', - action='store_true', dest='show_imported_functions', - help='Display imported functions') - - parser.add_argument('-L', '--libraries', - action='store_true', dest='show_libraries', - help='Display Imported Libraries') - - parser.add_argument('-r', '--relocations', - action='store_true', dest='show_relocs', - help='Display the relocations (if present)') - - parser.add_argument('-s', '--symbols', - action='store_true', dest='show_symbols', - help='Display Symbols') - - parser.add_argument('-S', '--sections', - action='store_true', dest='show_sections', - help='Display Sections') - - parser.add_argument('-x', '--exported', - action='store_true', dest='show_exported_functions', - help='Display exported functions') - - parser.add_argument("binary", - metavar="", - help='Target File') - - args = parser.parse_args() - - binary = None - try: - binary = lief.parse(args.binary) - except lief.exception as e: - print(e) - sys.exit(1) - - binary = binary.abstract - if args.show_header or args.show_all: - print_header(binary) - - if (args.show_imported_functions or args.show_all) and len(binary.imported_functions) > 0: - print_imported_functions(binary) - - if (args.show_exported_functions or args.show_all) and len(binary.exported_functions) > 0: - print_exported_functions(binary) - - if (args.show_libraries or args.show_all) and len(binary.libraries) > 0: - print_imported_libraries(binary) - - if (args.show_sections or args.show_all) and len(binary.sections) > 0: - print_sections(binary) - - if (args.show_symbols or args.show_all) and len(binary.symbols) > 0: - print_symbols(binary) - - if (args.show_relocs or args.show_all) and len(binary.relocations) > 0: - print_relocations(binary) - -if __name__ == "__main__": - main() - - - diff --git a/vendor/lief/examples/python/authenticode/api_example.py b/vendor/lief/examples/python/authenticode/api_example.py deleted file mode 100644 index 2c1c0f9..0000000 --- a/vendor/lief/examples/python/authenticode/api_example.py +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env python -import lief -import sys -import os - -# Parse PE file -pe = lief.parse(sys.argv[1]) - -sep = (":") if sys.version_info.minor > 7 else () - -# Get authenticode -print(pe.authentihash_md5.hex(*sep)) # 1c:a0:91:53:dc:9a:3a:5f:34:1d:7f:9b:b9:56:69:4d -print(pe.authentihash(lief.PE.ALGORITHMS.SHA_1).hex(*sep)) # 1e:ad:dc:29:1e:db:41:a2:69:c2:ba:ae:4b:fb:9d:31:e7:bb:ab:59 - -# Check signature according to PKCS #7 and Microsoft documentation -print(pe.verify_signature()) # Return VERIFICATION_FLAGS.OK - -bin_ca = None -# Look for the root CA in the PE file -for crt in pe.signatures[0].certificates: - if crt.issuer == "C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA": - bin_ca = crt - -# Verify CA chain -bundle_path = os.getenv("LIEF_CA_BUNDLE", None) # Path to CA bundle (one can use those from signify: - # signify/certs/authenticode-bundle.pem) -if bundle_path is not None: - # Parse cert bundle and return a list of lief.PE.x509 objects - bundle = lief.PE.x509.parse(bundle_path) - print(bin_ca.is_trusted_by(bundle)) # VERIFICATION_FLAGS.OK - - -# Get the certificate used by the signer -cert_signer = pe.signatures[0].signers[0].cert -print(cert_signer) -bin_ca.verify(cert_signer) # Verify that cert_signer is signed the the CA - -# running with: -# LIEF_CA_BUNDLE=signify/signify/certs/authenticode-bundle.pem python ./authenticode.py avast_free_antivirus_setup_online.exe -# -# 1c:a0:91:53:dc:9a:3a:5f:34:1d:7f:9b:b9:56:69:4d -# 1e:ad:dc:29:1e:db:41:a2:69:c2:ba:ae:4b:fb:9d:31:e7:bb:ab:59 -# VERIFICATION_FLAGS.OK -# cert. version : 3 -# serial number : 04:09:18:1B:5F:D5:BB:66:75:53:43:B5:6F:95:50:08 -# issuer name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert Assured ID Root CA -# subject name : C=US, O=DigiCert Inc, OU=www.digicert.com, CN=DigiCert SHA2 Assured ID Code Signing CA -# issued on : 2013-10-22 12:00:00 -# expires on : 2028-10-22 12:00:00 -# signed using : RSA with SHA-256 -# RSA key size : 2048 bits -# basic constraints : CA=true, max_pathlen=0 -# key usage : Digital Signature, Key Cert Sign, CRL Sign -# ext key usage : Code Signing -# -# VERIFICATION_FLAGS.OK diff --git a/vendor/lief/examples/python/authenticode/authenticode_reader.py b/vendor/lief/examples/python/authenticode/authenticode_reader.py deleted file mode 100644 index 4920376..0000000 --- a/vendor/lief/examples/python/authenticode/authenticode_reader.py +++ /dev/null @@ -1,306 +0,0 @@ -#!/usr/bin/env python -import lief -from lief.PE import oid_to_string -import argparse -import json -import sys -import string -import argparse -import traceback -import pathlib - -try: - from prettyprinter import pprint -except ImportError: - from pprint import pprint - -HAS_EXCEPTION = False -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - HAS_EXCEPTION = True - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60, file=sys.stderr) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60, file=sys.stderr) - -@exceptions_handler(Exception) -def print_attr(indent: int, auth: lief.PE.Attribute): - if auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.CONTENT_TYPE: - print_content_type(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.PKCS9_SIGNING_TIME: - print_signing_time(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.MS_SPC_STATEMENT_TYPE: - print_ms_statement_type(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.PKCS9_MESSAGE_DIGEST: - print_pkcs_msg_dg(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.PKCS9_COUNTER_SIGNATURE: - print_pkcs_counter_sig(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.GENERIC_TYPE: - print_generic_type(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.SPC_SP_OPUS_INFO: - print_spc_sp_opus_info(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.MS_SPC_NESTED_SIGN: - print_ms_nested_sig(indent, auth) - elif auth.type == lief.PE.SIG_ATTRIBUTE_TYPES.PKCS9_AT_SEQUENCE_NUMBER: - print_pkcs9_at_seq_number(indent, auth) - else: - print(" " * indent, type(auth), auth) - - -@exceptions_handler(Exception) -def print_pkcs9_at_seq_number(indent: int, auth: lief.PE.PKCS9AtSequenceNumber): - print("{} PKCS #9 sequence number: {}".format(" " * indent, auth.number)) - -@exceptions_handler(Exception) -def print_ms_nested_sig(indent: int, auth: lief.PE.MsSpcNestedSignature): - print("{} MS Nested Signature:".format(" " * indent)) - print_all(auth.signature, indent + 2) - -@exceptions_handler(Exception) -def print_spc_sp_opus_info(indent: int, auth: lief.PE.SpcSpOpusInfo): - if len(auth.program_name) > 0 and len(auth.more_info) > 0: - print("{} Info: {} {}".format(" " * indent, auth.program_name, auth.more_info)) - elif len(auth.program_name) > 0 and len(auth.more_info) == 0: - print("{} Info: {}".format(" " * indent, auth.program_name)) - elif len(auth.program_name) == 0 and len(auth.more_info) > 0: - print("{} Info: {}".format(" " * indent, auth.more_info)) - else: - print("{} Info: ".format(" " * indent)) - -@exceptions_handler(Exception) -def print_generic_type(indent: int, auth: lief.PE.GenericType): - print("{} Generic Type {} ({})".format(" " * indent, auth.oid, lief.PE.oid_to_string(auth.oid))) - -@exceptions_handler(Exception) -def print_content_type(indent: int, auth: lief.PE.ContentType): - print("{} Content Type OID: {} ({})".format(" " * indent, auth.oid, lief.PE.oid_to_string(auth.oid))) - -@exceptions_handler(Exception) -def print_signing_time(indent: int, auth: lief.PE.PKCS9SigningTime): - print("{} Signing Time: {}/{:02}/{:02} - {:02}:{:02}:{:02}".format(" " * indent, *auth.time)) - -@exceptions_handler(Exception) -def print_ms_statement_type(indent: int, auth: lief.PE.MsSpcStatementType): - print("{} MS Statement type OID: {} ({})".format(" " * indent, auth.oid, lief.PE.oid_to_string(auth.oid))) - -@exceptions_handler(Exception) -def print_pkcs_msg_dg(indent: int, auth: lief.PE.PKCS9MessageDigest): - print("{} PKCS9 Message Digest: {}".format(" " * indent, auth.digest.hex())) - -@exceptions_handler(Exception) -def print_crt(indent: int, crt: lief.PE.x509): - print("{} Version : {:d}".format(" " * indent, crt.version)) - print("{} Issuer : {}".format(" " * indent, crt.issuer)) - print("{} Subject : {}".format(" " * indent, crt.subject)) - print("{} Serial Number : {}".format(" " * indent, crt.serial_number.hex())) - print("{} Signature Algorithm: {}".format(" " * indent, lief.PE.oid_to_string(crt.signature_algorithm))) - print("{} Valid from : {}/{:02d}/{:02d} - {:02d}:{:02d}:{:02d}".format(" " * indent, *crt.valid_from)) - print("{} Valid to : {}/{:02d}/{:02d} - {:02d}:{:02d}:{:02d}".format(" " * indent, *crt.valid_to)) - if len(crt.key_usage) > 0: - print("{} Key usage : {}".format(" " * indent, " - ".join(str(e).split(".")[-1] for e in crt.key_usage))) - if len(crt.ext_key_usage) > 0: - print("{} Ext key usage : {}".format(" " * indent, " - ".join(lief.PE.oid_to_string(e) for e in crt.ext_key_usage))) - if crt.rsa_info is not None: - rsa_info = crt.rsa_info - print("{} RSA key size : {}".format(" " * indent, rsa_info.key_size)) - print("{} ===========================================".format(" " * indent)) - -@exceptions_handler(Exception) -def print_pkcs_counter_sig(indent: int, auth: lief.PE.PKCS9CounterSignature): - print("{} PKCS9 counter signature".format(" " * indent)) - signer = auth.signer - print("{} Version : {:d}".format(" " * indent, signer.version)) - print("{} Serial Number : {}".format(" " * indent, signer.serial_number.hex())) - print("{} Issuer : {}".format(" " * indent, signer.issuer)) - print("{} Digest Algorithm : {}".format(" " * indent, signer.digest_algorithm)) - print("{} Encryption Algorithm: {}".format(" " * indent, signer.encryption_algorithm)) - print("{} Encrypted Digest : {} ...".format(" " * indent, signer.encrypted_digest.hex()[:20])) - - if len(signer.authenticated_attributes) > 0: - print("{} Authenticated attributes:".format(" " * indent)) - for auth in signer.authenticated_attributes: - print_attr(indent + 4, auth) - - if len(signer.unauthenticated_attributes) > 0: - print("{} Un-Authenticated attributes:".format(" " * indent)) - for auth in signer.unauthenticated_attributes: - print_attr(indent + 4, auth) -@exceptions_handler(Exception) -def print_all(sig: lief.PE.Signature, indent: int = 2): - ci: lief.PE.ContentInfo = sig.content_info - print("{}Signature version : {}".format(" " * indent, sig.version)) - print("{}Digest Algorithm : {!s}".format(" " * indent, sig.digest_algorithm)) - print("{}Content Info:".format(" " * indent)) - print("{} Content Type : {!s} ({})".format(" " * indent, ci.content_type, lief.PE.oid_to_string(ci.content_type))) - print("{} Digest Algorithm: {!s}".format(" " * indent, ci.digest_algorithm)) - print("{} Digest : {!s}".format(" " * indent, ci.digest.hex())) - print("{}Certificates".format(" " * indent)) - for crt in sig.certificates: - print_crt(indent, crt) - print("{}Signer(s)".format(" " * indent)) - for signer in sig.signers: - print("{} Version : {:d}".format(" " * indent, signer.version)) - print("{} Serial Number : {}".format(" " * indent, signer.serial_number.hex())) - print("{} Issuer : {}".format(" " * indent, signer.issuer)) - print("{} Digest Algorithm : {}".format(" " * indent, signer.digest_algorithm)) - print("{} Encryption Algorithm: {}".format(" " * indent, signer.encryption_algorithm)) - print("{} Encrypted Digest : {} ...".format(" " * indent, signer.encrypted_digest.hex()[:20])) - if len(signer.authenticated_attributes) > 0: - print("{} Authenticated attributes:".format(" " * indent)) - for auth in signer.authenticated_attributes: - print_attr(indent + 4, auth) - - if len(signer.unauthenticated_attributes) > 0: - print("{} Un-authenticated attributes:".format(" " * indent)) - for auth in signer.unauthenticated_attributes: - print_attr(indent + 4, auth) - - -@exceptions_handler(Exception) -def show_crts(sig: lief.PE.Signature, args): - for crt in sig.certificates: - print_crt(0, crt) - -@exceptions_handler(Exception) -def process_signature(sig: lief.PE.Signature, args): - if args.show_all: - print_all(sig) - - if args.show_crt: - show_crts(sig, args) - - if args.show_hash: - print("Authentihash: {}".format(sig.content_info.digest.hex())) - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument("file") - - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-c', '--crt', - action='store_true', dest='show_crt', - help='Show embedded x509 certificates') - - parser.add_argument('-H', '--hash', - action='store_true', dest='show_hash', - help='Show the autentihash value') - - parser.add_argument('-C', '--check', - action='store_true', dest='check_sig', - help='Check the signature') - - parser.add_argument('-D', '--allow-expired', - action='store_true', dest='allow_expired', - help='Allow expired certificates') - - parser.add_argument('-s', '--save', - dest='ext_file_path', - help='Extract and save the PKCS #7') - - - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - lief.logging.set_level(args.main_verbosity) - - if lief.PE.is_pe(args.file): - binary = None - try: - binary: lief.PE.Binary = lief.PE.parse(args.file) - if binary is None: - print("Error while parsing {}".format(args.file)) - sys.exit(1) - except lief.exception as e: - print(e) - sys.exit(1) - - if args.check_sig: - flags = lief.PE.Signature.VERIFICATION_CHECKS.DEFAULT - if args.allow_expired: - flags = lief.PE.Signature.VERIFICATION_CHECKS.SKIP_CERT_TIME - res = binary.verify_signature(flags) - print(res) - - if args.show_hash: - print("Binary MD5 authentihash: {}".format(binary.authentihash_md5.hex())) - print("Binary SHA-1 authentihash: {}".format(binary.authentihash_sha1.hex())) - print("Binary SHA-256 authentihash: {}".format(binary.authentihash_sha256.hex())) - - for idx, sig in enumerate(binary.signatures): - process_signature(sig, args) - if args.ext_file_path: - path = args.ext_file_path - if idx > 0: - path += str(idx) - if not path.endswith(".p7b"): - path += ".p7b" - outpath = pathlib.Path(path) - outpath.write_bytes(sig.raw_der) - print("Signature saved to {}".format(outpath)) - else: - # Try as a regular p7b signature - sig = lief.PE.Signature.parse(args.file) - if sig is None: - print("Fail to parse the signature") - sys.exit(1) - process_signature(sig, args) - - -if __name__ == "__main__": - main() - if HAS_EXCEPTION: - sys.exit(1) diff --git a/vendor/lief/examples/python/change_elf_interpreter.py b/vendor/lief/examples/python/change_elf_interpreter.py deleted file mode 100644 index 9db0348..0000000 --- a/vendor/lief/examples/python/change_elf_interpreter.py +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env python -import lief -import argparse -import os -import stat -import sys - -def change_interpreter(target, interpreter, output=None): - if not os.path.isfile(target) or not lief.is_elf(target): - print("Wrong target! ({})".format(target)) - return 1 - - - if not os.path.isfile(interpreter) or not lief.is_elf(interpreter): - print("Wrong interpreter! ({})".format(interpreter)) - return 1 - - binary = lief.parse(target) - if not binary.has_interpreter: - print("The given target doesn't have interpreter!") - return 1 - - binary.interpreter = interpreter - - output_path = output - if output_path is None: - output_path = os.path.basename(target) - output_path += "_updated" - - if os.path.isfile(output_path): - os.remove(output_path) - - binary.write(output_path) - - # Set as executable - st = os.stat(output_path) - os.chmod(output_path, st.st_mode | stat.S_IEXEC) - return 0 - - -def main(): - parser = argparse.ArgumentParser(description='Change the ELF interpreter of the given binary') - - - parser.add_argument("-o", "--output", - help = 'Path to the binary rewritten', - action = 'store', - default = None) - - parser.add_argument("target", - metavar="", - help='Target ELF file') - - parser.add_argument("interpreter", - metavar="", - help='Path to the new interpreter') - - - args = parser.parse_args() - - status = change_interpreter(args.target, args.interpreter, args.output) - sys.exit(status) - - -if __name__ == "__main__": - main() - - diff --git a/vendor/lief/examples/python/dex_json.py b/vendor/lief/examples/python/dex_json.py deleted file mode 100644 index 0bfb66b..0000000 --- a/vendor/lief/examples/python/dex_json.py +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a DEX file in the JSON format - -import argparse -import sys -import lief -import json - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('file', help='DEX binary') - args = parser.parse_args() - - if not lief.DEX.is_dex(args.file): - print("{} is not a DEX file".format(args.file)) - return 1 - dexfile = lief.DEX.parse(args.file) - json_data = json.loads(lief.to_json(dexfile)) - print(json.dumps(json_data, sort_keys = True, indent = 4)) - -if __name__ == "__main__": - sys.exit(main()) - diff --git a/vendor/lief/examples/python/dex_reader.py b/vendor/lief/examples/python/dex_reader.py deleted file mode 100644 index ec7c258..0000000 --- a/vendor/lief/examples/python/dex_reader.py +++ /dev/null @@ -1,248 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about Android DEX files -import sys -import os -import argparse -import traceback -import lief -from lief import DEX - -EXIT_STATUS = 0 -terminal_rows, terminal_columns = 100, 100 -try: - terminal_rows, terminal_columns = os.popen('stty size', 'r').read().split() -except ValueError: - pass - - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - global EXIT_STATUS - print("{} raised: {}".format(self.func.__name__, e)) - EXIT_STATUS = 1 - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - -@exceptions_handler(Exception) -def print_information(dexfile): - print("== Information ==") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - version = dexfile.version - - print("DEX File version: {}".format(version)) - print("") - - -@exceptions_handler(Exception) -def print_header(dexfile): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - print("== Header ==") - header = dexfile.header - print(header) - -@exceptions_handler(Exception) -def print_classes(dexfile): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - classes = dexfile.classes - - print("== Classes ==") - for cls in classes: - print(cls) - -@exceptions_handler(Exception) -def print_fields(dexfile): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - fields = dexfile.fields - - print("== Fields ==") - for f in fields: - print(f) - -@exceptions_handler(Exception) -def print_methods(dexfile): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - methods = dexfile.methods - - print("== Methods ==") - for m in methods: - print(m) - -@exceptions_handler(Exception) -def print_strings(dexfile): - print("== Strings ==") - for s in dexfile.strings: - print(s) - -@exceptions_handler(Exception) -def print_types(dexfile): - print("== Types ==") - for t in dexfile.types: - print(t) - -@exceptions_handler(Exception) -def print_prototypes(dexfile): - print("== Prototypes ==") - for t in dexfile.prototypes: - print(t) - -@exceptions_handler(Exception) -def print_map(dexfile): - print("== Map ==") - print(dexfile.map) - - -def main(): - parser = argparse.ArgumentParser(usage='%(prog)s [options] DEX files') - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-H', '--header', - action='store_true', dest='show_header', - help='Display header') - - parser.add_argument('-c', '--classes', - action='store_true', dest='show_classes', - help='Display classes') - - parser.add_argument('-f', '--fields', - action='store_true', dest='show_fields', - help='Display Fields') - - parser.add_argument('-m', '--methods', - action='store_true', dest='show_methods', - help='Display Methods') - - parser.add_argument('-s', '--strings', - action='store_true', dest='show_strings', - help='Display Strings') - - parser.add_argument('-t', '--types', - action='store_true', dest='show_types', - help='Display Types') - - parser.add_argument('-p', '--prototypes', - action='store_true', dest='show_prototypes', - help='Display Prototypes') - - parser.add_argument('-M', '--map', - action='store_true', dest='show_map', - help='Display Map') - - parser.add_argument("file", - metavar="", - help='Target DEX File') - - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - - lief.logging.set_level(args.main_verbosity) - - binary = None - try: - dexfile = DEX.parse(args.file) - except lief.exception as e: - print(e) - sys.exit(1) - - print_information(dexfile) - - if args.show_header or args.show_all: - print_header(dexfile) - - if (args.show_classes or args.show_all) and len(dexfile.classes) > 0: - print_classes(dexfile) - - if (args.show_fields or args.show_all) and len(dexfile.fields) > 0: - print_fields(dexfile) - - if (args.show_methods or args.show_all) and len(dexfile.methods) > 0: - print_methods(dexfile) - - if (args.show_strings or args.show_all) and len(dexfile.strings) > 0: - print_strings(dexfile) - - if (args.show_types or args.show_all) and len(dexfile.types) > 0: - print_types(dexfile) - - if (args.show_prototypes or args.show_all) and len(dexfile.prototypes) > 0: - print_prototypes(dexfile) - - if args.show_map or args.show_all: - print_map(dexfile) - - sys.exit(EXIT_STATUS) - - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/python/elf_bin2lib.py b/vendor/lief/examples/python/elf_bin2lib.py deleted file mode 100644 index 3564445..0000000 --- a/vendor/lief/examples/python/elf_bin2lib.py +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python -import argparse -import lief -import sys - -def bin2lib(binary, address, output, name=""): - if not binary.is_pie: - print("It only works with PIE binaries") - sys.exit(1) - - function = binary.add_exported_function(address, name) - print("Function created:") - print(function) - binary.write(output) - - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="") - - parser.add_argument("--name", "-n", default="", help="Name of the function to create") - parser.add_argument("--output", "-o", default="libfoo.so", help="Output name. (Default: %(default)") - - parser.add_argument("binary", help="The target binary") - parser.add_argument("address", type=lambda e: int(e, 0), help="Address of the function to export") - - - args = parser.parse_args() - binary = lief.parse(args.binary) - bin2lib(binary, args.address, args.output, name=args.name) diff --git a/vendor/lief/examples/python/elf_json.py b/vendor/lief/examples/python/elf_json.py deleted file mode 100644 index e5df13b..0000000 --- a/vendor/lief/examples/python/elf_json.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a ELF binary in the JSON format -# -# python elf_json.py /bin/ls -#   -# { -# "dynamic_entries": [ -# { -# "library": "libcap.so.2", -# "tag": "NEEDED", -# "value": 1 -# }, -# { -# "library": "libc.so.6", -# "tag": "NEEDED", -# "value": 74 -# }, -# ... - - -import argparse -import sys -import lief -import json - - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('binary', help='ELF binary') - args = parser.parse_args() - - binary = lief.parse(args.binary) - json_data = json.loads(lief.to_json(binary)) - print(json.dumps(json_data, sort_keys = True, indent = 4)) - -if __name__ == "__main__": - sys.exit(main()) - diff --git a/vendor/lief/examples/python/elf_reader.py b/vendor/lief/examples/python/elf_reader.py deleted file mode 100644 index f31a4e5..0000000 --- a/vendor/lief/examples/python/elf_reader.py +++ /dev/null @@ -1,643 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about an ELF binary - -import os -import sys -import textwrap -import traceback - -import lief -from lief import ELF -import argparse - -terminal_rows, terminal_columns = 100, 110 -try: - terminal_rows, terminal_columns = os.popen('stty size', 'r').read().split() -except ValueError: - pass - -terminal_columns = int(terminal_columns) - 10 -terminal_rows = int(terminal_rows) - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - - -@exceptions_handler(Exception) -def print_header(binary): - header = binary.header - identity = header.identity - - - print("== Header ==\n") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<13x}" - format_dec = "{:<30} {:<30d}" - format_ide = "{:<30} {:<02x} {:<02x} {:<02x} {:<02x}" - - eflags_str = "" - if header.machine_type == lief.ELF.ARCH.ARM: - eflags_str = " - ".join([str(s).split(".")[-1] for s in header.arm_flags_list]) - - if header.machine_type in [lief.ELF.ARCH.MIPS, lief.ELF.ARCH.MIPS_RS3_LE, lief.ELF.ARCH.MIPS_X]: - eflags_str = " - ".join([str(s).split(".")[-1] for s in header.mips_flags_list]) - - if header.machine_type == lief.ELF.ARCH.PPC64: - eflags_str = " - ".join([str(s).split(".")[-1] for s in header.ppc64_flags_list]) - - if header.machine_type == lief.ELF.ARCH.HEXAGON: - eflags_str = " - ".join([str(s).split(".")[-1] for s in header.hexagon_flags_list]) - print(identity) - print(format_ide.format("Magic:", identity[0], identity[1], identity[2], identity[3])) - print(format_str.format("Class:", str(header.identity_class).split(".")[-1])) - print(format_str.format("Endianness:", str(header.identity_data).split(".")[-1])) - print(format_str.format("Version:", str(header.identity_version).split(".")[-1])) - print(format_str.format("OS/ABI:", str(header.identity_os_abi).split(".")[-1])) - print(format_dec.format("ABI Version:", header.identity_abi_version)) - print(format_str.format("File Type:", str(header.file_type).split(".")[-1])) - print(format_str.format("Machine Type:", str(header.machine_type).split(".")[-1])) - print(format_str.format("Object File Version:", str(header.object_file_version).split(".")[-1])) - print(format_hex.format("Entry Point:", header.entrypoint)) - print(format_hex.format("Program Header Offset:", header.program_header_offset)) - print(format_hex.format("Section Header Offset:", header.section_header_offset)) - print(format_hex.format("Processor flags:", header.processor_flag) + eflags_str) - print(format_dec.format("Header Size:", header.header_size)) - print(format_dec.format("Program Header Size:", header.program_header_size)) - print(format_dec.format("Section Header Size:", header.section_header_size)) - print(format_dec.format("Number of segments:", header.numberof_segments)) - print(format_dec.format("Number of sections:", header.numberof_sections)) - print("") - - -@exceptions_handler(Exception) -def print_sections(binary): - sections = binary.sections - if len(sections) > 0: - print("== Sections ==\n") - f_title = "|{:<30} | {:<12}| {:<17}| {:<12}| {:<10}| {:<8}| {:<8}|" - f_value = "|{:<30} | {:<12}| 0x{:<14x} | 0x{:<10x}| 0x{:<8x}| {:<8.2f}| {:<10}" - print(f_title.format("Name", "Type", "Virtual address", "File offset", "Size", "Entropy", "Segment(s)")) - - for section in sections: - segments_str = " - ".join([str(s.type).split(".")[-1] for s in section.segments]) - print(f_value.format( - section.name, - str(section.type).split(".")[-1], - section.virtual_address, - section.file_offset, - section.size, - abs(section.entropy), - segments_str)) - print("") - else: - print("No sections") - -@exceptions_handler(Exception) -def print_segments(binary): - segments = binary.segments - # Segments - if len(segments) > 0: - print("== Segments ==\n") - f_title = "|{:<30} | {:<10}| {:<18}| {:<17}| {:<17}| {:<17}| {:<19}|" - f_value = "|{:<30} | {:<10}| 0x{:<16x}| 0x{:<15x}| 0x{:<15x}| 0x{:<15x}| {}" - print(f_title.format("Type", - "Flags", "File offset", "Virtual Address", "Virtual Size", "Size", "Sections")) - - for segment in segments: - sections = segment.sections - s = ", ".join([section.name for section in sections]) - flags_str = ["-"] * 3 - if ELF.SEGMENT_FLAGS.R in segment: - flags_str[0] = "r" - - if ELF.SEGMENT_FLAGS.W in segment: - flags_str[1] = "w" - - if ELF.SEGMENT_FLAGS.X in segment: - flags_str[2] = "x" - flags_str = "".join(flags_str) - - print(f_value.format( - str(segment.type).split(".")[-1], - flags_str, - segment.file_offset, - segment.virtual_address, - segment.virtual_size, - segment.physical_size, s)) - print("") - else: - print("No segments") - -@exceptions_handler(Exception) -def print_dynamic_entries(binary): - dynamic_entries = binary.dynamic_entries - # Dynamic entries - if len(dynamic_entries) == 0: - return - - print("== Dynamic entries ==\n") - f_title = "|{:<16} | {:<10}| {:<20}|" - f_value = "|{:<16} | 0x{:<8x}| {:<20}|" - print(f_title.format("Tag", "Value", "Info")) - for entry in dynamic_entries: - if entry.tag == ELF.DYNAMIC_TAGS.NULL: - continue - - if entry.tag in [ELF.DYNAMIC_TAGS.SONAME, ELF.DYNAMIC_TAGS.NEEDED, ELF.DYNAMIC_TAGS.RUNPATH, ELF.DYNAMIC_TAGS.RPATH]: - print(f_value.format(str(entry.tag).split(".")[-1], entry.value, entry.name)) - elif type(entry) is ELF.DynamicEntryArray: # [ELF.DYNAMIC_TAGS.INIT_ARRAY,ELF.DYNAMIC_TAGS.FINI_ARRAY]: - print(f_value.format(str(entry.tag).split(".")[-1], entry.value, ", ".join(map(hex, entry.array)))) - elif entry.tag == ELF.DYNAMIC_TAGS.FLAGS: - flags_str = " - ".join([str(ELF.DYNAMIC_FLAGS(s)).split(".")[-1] for s in entry.flags]) - print(f_value.format(str(entry.tag).split(".")[-1], entry.value, flags_str)) - elif entry.tag == ELF.DYNAMIC_TAGS.FLAGS_1: - flags_str = " - ".join([str(ELF.DYNAMIC_FLAGS_1(s)).split(".")[-1] for s in entry.flags]) - print(f_value.format(str(entry.tag).split(".")[-1], entry.value, flags_str)) - else: - print(f_value.format(str(entry.tag).split(".")[-1], entry.value, "")) - - print("") - - -@exceptions_handler(Exception) -def print_symbols(symbols, no_trunc): - can_demangle = len(symbols) > 0 and len(symbols[0].demangled_name) > 0 - if can_demangle: - maxsize = max([len(symbol.demangled_name) for symbol in symbols]) - else: - maxsize = max([len(symbol.name) for symbol in symbols]) - - SIZE = 70 - maxsize = min(maxsize, terminal_columns - SIZE) if terminal_columns > SIZE else terminal_columns - - f_title = "|{:<" + str(maxsize) + "} | {:<7}| {:<8}| {:<10}| {:<8}| {:<4}| {:<14}|" - f_value = "|{:<" + str(maxsize) + "} | {:<7}| {:<8x}| {:<10}| {:<8}| {:<4}| {:<14}|" - - print(f_title.format("Name", "Type", "Value", "Visibility", "Binding", "I/E", "Version")) - - for symbol in symbols: - symbol_version = symbol.symbol_version if symbol.has_version else "" - - import_export = "" - if symbol.imported: - import_export = "I" - - if symbol.exported: - import_export = "E" - - symbol_name = symbol.demangled_name - if len(symbol_name) == 0: - symbol_name = symbol.name - - wrapped = textwrap.wrap(symbol_name, maxsize) - - if len(wrapped) <= 1 or no_trunc: - symbol_name = symbol_name - else: - symbol_name = wrapped[0][:-3] + "..." - - print(f_value.format( - symbol_name, - str(symbol.type).split(".")[-1], - symbol.value, - str(symbol.visibility).split(".")[-1], - str(symbol.binding).split(".")[-1], - import_export, - str(symbol_version) - )) - -@exceptions_handler(Exception) -def print_dynamic_symbols(binary, args): - print("== Dynamic symbols ==\n") - print_symbols(binary.dynamic_symbols, args.no_trunc) - - -@exceptions_handler(Exception) -def print_static_symbols(binary, args): - print("== Static symbols ==\n") - print_symbols(binary.static_symbols, args.no_trunc) - -@exceptions_handler(Exception) -def print_relocations(binary, relocations): - f_title = "|{:<10} | {:<10}| {:<8}| {:<8}| {:<8}| {:<15}| {:<30} |" - f_value = "|0x{:<8x} | {:<10}| {:<8d}| {:<8d}| {:<8x}| {:<15}| {:<30} |" - - print(f_title.format("Address", "Type", "Info", "Size", "Addend", "Purpose", "Symbol")) - - for relocation in relocations: - type = str(relocation.type) - if binary.header.machine_type == ELF.ARCH.x86_64: - type = str(ELF.RELOCATION_X86_64(relocation.type)) - elif binary.header.machine_type == ELF.ARCH.i386: - type = str(ELF.RELOCATION_i386(relocation.type)) - elif binary.header.machine_type == ELF.ARCH.ARM: - type = str(ELF.RELOCATION_ARM(relocation.type)) - elif binary.header.machine_type == ELF.ARCH.AARCH64: - type = str(ELF.RELOCATION_AARCH64(relocation.type)) - - symbol_name = "" - if relocation.has_symbol: - symbol: lief.ELF.Symbol = relocation.symbol - if len(symbol.name) > 0: - symbol_name = symbol.name - elif symbol.type == lief.ELF.SYMBOL_TYPES.SECTION: - shndx = symbol.shndx - sections = binary.sections - if 0 < shndx and shndx < len(sections): - symbol_name = sections[shndx].name + " + " + hex(relocation.addend) - else: - symbol_name = "
    ".format(shndx) - - - print(f_value.format( - relocation.address, - type.split(".")[-1], - relocation.info, - relocation.size, - relocation.addend, - str(relocation.purpose).split(".")[-1], - symbol_name)) - - -@exceptions_handler(Exception) -def print_all_relocations(binary): - dynamicrelocations = binary.dynamic_relocations - pltgot_relocations = binary.pltgot_relocations - object_relocations = binary.object_relocations - - if len(dynamicrelocations) > 0: - print("== Dynamic Relocations ==\n") - print_relocations(binary, dynamicrelocations) - - - if len(pltgot_relocations) > 0: - print("== PLT/GOT Relocations ==\n") - print_relocations(binary, pltgot_relocations) - - if len(object_relocations) > 0: - print("== Object Relocations ==\n") - print_relocations(binary, object_relocations) - -@exceptions_handler(Exception) -def print_exported_symbols(binary, args): - symbols = binary.exported_symbols - - print("== Exported symbols ==\n") - if len(symbols) == 0: - print("No exports!") - return - print_symbols(symbols, args.no_trunc) - -@exceptions_handler(Exception) -def print_imported_symbols(binary, args): - symbols = binary.imported_symbols - print("== Imported symbols ==\n") - - if len(symbols) == 0: - print("No imports!") - return - print_symbols(symbols, args.no_trunc) - -@exceptions_handler(Exception) -def print_information(binary): - print("== Information ==\n") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - print(format_str.format("Name:", binary.name)) - print(format_hex.format("Address base:", binary.imagebase)) - print(format_hex.format("Virtual size:", binary.virtual_size)) - print(format_str.format("PIE:", str(binary.is_pie))) - print(format_str.format("NX:", str(binary.has_nx))) - -@exceptions_handler(Exception) -def print_gnu_hash(binary): - print("== GNU Hash ==\n") - - if not binary.use_gnu_hash: - return - - gnu_hash = binary.gnu_hash - - format_str = "{:<30} {}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - - print(format_dec.format("Number of buckets:", gnu_hash.nb_buckets)) - print(format_dec.format("First symbol index:", gnu_hash.symbol_index)) - print(format_hex.format("Shift Count:", gnu_hash.shift2)) - print(format_str.format("Bloom filters:", gnu_hash.bloom_filters)) - print(format_str.format("Buckets:", gnu_hash.buckets)) - print(format_str.format("Hash values:", gnu_hash.hash_values)) - - -@exceptions_handler(Exception) -def print_sysv_hash(binary): - print("== SYSV Hash ==\n") - - if not binary.use_sysv_hash: - return - - sysv_hash = binary.sysv_hash - - format_str = "{:<30} {}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - - print(format_dec.format("Number of buckets:", sysv_hash.nbucket)) - print(format_dec.format("Number of chains:", sysv_hash.nchain)) - print(format_str.format("Buckets:", sysv_hash.buckets)) - print(format_str.format("Chains:", sysv_hash.chains)) - - -@exceptions_handler(Exception) -def print_notes(binary): - print("== Notes ==\n") - - format_str = "{:<19} {}" - format_hex = "{:<19} 0x{:<28x}" - format_dec = "{:<19} {:<30d}" - - notes = binary.notes - for idx, note in enumerate(notes): - description = note.description - description_str = " ".join(map(lambda e : "{:02x}".format(e), description[:16])) - if len(description) > 16: - description_str += " ..." - - print("Note #{:d}".format(idx)) - - type_str = note.type_core if note.is_core else note.type - type_str = str(type_str).split(".")[-1] - - print(format_str.format("Name:", note.name)) - print(format_str.format("Type:", type_str)) - print(format_str.format("Description:", description_str)) - - note_details = note.details - - if type(note_details) == lief.ELF.AndroidNote: - print(format_dec.format("SDK Version:", note_details.sdk_version)) - print(format_str.format("NDK Version:", note_details.ndk_version)) - print(format_str.format("NDK build number:", note_details.ndk_build_number)) - - if type(note_details) == lief.ELF.NoteAbi: - version = note_details.version - version_str = "{:d}.{:d}.{:d}".format(version[0], version[1], version[2]) - - print(format_str.format("ABI:", note_details.abi)) - print(format_str.format("Version:", version_str)) - - if ELF.NOTE_TYPES(note.type) == ELF.NOTE_TYPES.GOLD_VERSION: - print(format_str.format("Version:", "".join(map(chr, note.description)))) - - if note.is_core: - print(note_details) - - - print("\n") - - -@exceptions_handler(Exception) -def print_ctor(binary): - print("== Constructors ==\n") - - print("Functions: ({:d})".format(len(binary.ctor_functions))) - for idx, f in enumerate(binary.ctor_functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - -@exceptions_handler(Exception) -def print_strings(binary): - print("== Strings ==\n") - - - strings = binary.strings - print("Strings: ({:d})".format(len(binary.strings))) - for s in strings: - print(" {}".format(s)) - - -@exceptions_handler(Exception) -def print_functions(binary): - print("== Functions ==\n") - - functions = binary.functions - print("Functions: ({:d})".format(len(functions))) - for idx, f in enumerate(functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - - -def main(): - parser = argparse.ArgumentParser(add_help=False, prog=sys.argv[0]) - parser.add_argument("elf_file") - - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Equivalent to: -h -l -S -s -r -d -V') - - parser.add_argument('-d', '--dynamic', - action='store_true', dest='show_dynamic_tags', - help='Display the dynamic section') - - parser.add_argument('-H', '--help', - action='help', dest='help', - help='Display this information') - - parser.add_argument('-h', '--file-header', - action='store_true', dest='show_file_header', - help='Display the ELF file header') - - parser.add_argument('-i', '--imported', - action='store_true', dest='show_imported_symbols', - help='Display imported symbols') - - parser.add_argument('-l', '--program-headers', '--segments', - action='store_true', dest='show_program_header', - help='Display the program headers') - - parser.add_argument('-S', '--section-headers', '--sections', - action='store_true', dest='show_section_header', - help="Display the sections' headers") - - parser.add_argument('-e', '--headers', - action='store_true', dest='show_all_headers', - help='Equivalent to: -h -l -S') - - parser.add_argument('-s', '--symbols', '--syms', - action='store_true', dest='show_symbols', - help='Display the symbol table') - - parser.add_argument('--dynamic-symbols', '--dsyms', - action='store_true', dest='show_dynamic_symbols', - help='Display the dynamic symbols') - - parser.add_argument('--static-symbols', '--ssyms', - action='store_true', dest='show_static_symbols', - help='Display the static symbols') - - parser.add_argument('-r', '--relocs', - action='store_true', dest='show_relocs', - help='Display the relocations (if present)') - - parser.add_argument('-V', '--version-info', - action='store_true', dest='show_version_info', - help='Display the version sections (if present)') - - parser.add_argument('-x', '--exported', - action='store_true', dest='show_exported_symbols', - help='Display exported symbols') - - parser.add_argument('--gnu-hash', - action='store_true', dest='show_gnu_hash', - help='Display GNU Hash') - - parser.add_argument('--sysv-hash', - action='store_true', dest='show_sysv_hash', - help='Display SYSV Hash') - - parser.add_argument('-n', '--notes', - action='store_true', dest='show_notes', - help='Display Notes') - - parser.add_argument('--no-trunc', - action='store_true', dest='no_trunc', - default=False, - help='Do not trunc symbol names ...') - - parser.add_argument('--ctor', - action='store_true', dest='show_ctor', - help='Constructor functions') - - parser.add_argument('--strings', - action='store_true', dest='show_strings', - help='Strings present in the current ELF') - - parser.add_argument('--functions', - action='store_true', dest='show_functions', - help='List all function addresses found') - - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - - lief.logging.set_level(args.main_verbosity) - binary = ELF.parse(args.elf_file) - print_information(binary) - if args.show_all: - do_file_header = do_section_header = do_program_header = True - - if args.show_all_headers: - do_file_header = do_section_header = do_program_header = True - else: - do_file_header = args.show_file_header - do_section_header = args.show_section_header - do_program_header = args.show_program_header - - if do_file_header or args.show_all: - print_header(binary) - - if do_section_header or args.show_all: - print_sections(binary) - - if do_program_header or args.show_all: - print_segments(binary) - - if args.show_dynamic_tags or args.show_all: - print_dynamic_entries(binary) - - if (args.show_symbols or args.show_all or args.show_dynamic_symbols) and len(binary.dynamic_symbols) > 0: - print_dynamic_symbols(binary, args) - - if (args.show_symbols or args.show_all or args.show_static_symbols) and len(binary.static_symbols) > 0: - print_static_symbols(binary, args) - - if args.show_relocs or args.show_all: - print_all_relocations(binary) - - if args.show_imported_symbols or args.show_all: - print_imported_symbols(binary, args) - - if args.show_exported_symbols or args.show_all: - print_exported_symbols(binary, args) - - if (args.show_gnu_hash or args.show_all) and binary.use_gnu_hash: - print_gnu_hash(binary) - - if (args.show_sysv_hash or args.show_all) and binary.use_sysv_hash: - print_sysv_hash(binary) - - if args.show_notes or args.show_all: - print_notes(binary) - - if args.show_ctor or args.show_all: - print_ctor(binary) - - if args.show_strings or args.show_all: - print_strings(binary) - - if args.show_functions: - print_functions(binary) - - - - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/python/elf_remove_section_table.py b/vendor/lief/examples/python/elf_remove_section_table.py deleted file mode 100644 index 439a56c..0000000 --- a/vendor/lief/examples/python/elf_remove_section_table.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Remove the section table from an ELF binary -# so that some tools are blow minded (e.g. gdb) -# -# Example: -# $ python elf_remove_section_table.py /bin/ls ls_without_sections -# $ ls -# elf_remove_section_table.py ls_without_sections -# $ ls_without_sections -# $ elf_remove_section_table.py ls_without_sections -# $ readelf -S ls_without_sections -# -# Il n'y a pas de section dans ce fichier. -# $ gdb ls_without_sections -# "ls_without_sections": not in executable format: File format not recognized - -import sys -import lief -from lief import ELF - -def remove_section_table(filename, output): - binary = lief.parse(filename) # Build an ELF binary - - header = binary.header - header.section_header_offset = 0; - header.numberof_sections = 0; - - binary.write(output); - - -if __name__ == "__main__": - - if len(sys.argv) != 3: - print("Usage: {} ".format(sys.argv[0])) - sys.exit(1) - - remove_section_table(sys.argv[1], sys.argv[2]) diff --git a/vendor/lief/examples/python/elf_symbol_obfuscation.py b/vendor/lief/examples/python/elf_symbol_obfuscation.py deleted file mode 100644 index 8938b53..0000000 --- a/vendor/lief/examples/python/elf_symbol_obfuscation.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - - -# In this example, we replace all statics symbols in the .symtab -# with a random name. -# -# Example: -# -# >>> readelf -s ./hello_c -# -# 28: 0600700 0 OBJECT LOCAL DEFAULT 19 __JCR_LIST__ -# 29: 0400420 0 FUNC LOCAL DEFAULT 12 deregister_tm_clones -# 30: 0400460 0 FUNC LOCAL DEFAULT 12 register_tm_clones -# 31: 04004a0 0 FUNC LOCAL DEFAULT 12 __do_global_dtors_aux -# 32: 0600920 1 OBJECT LOCAL DEFAULT 24 completed.6940 -# 33: 06006f8 0 OBJECT LOCAL DEFAULT 18 __do_global_dtors_aux_fin -# ... -# -# >>> python elf_symbol_obfuscation ./hello_c ./hello_c.obf -# -# >>> readelf -s ./hello_c.obf -# -# 28: 0600700 0 OBJECT LOCAL DEFAULT 19 xnsffdfsryna -# 29: 0400420 0 FUNC LOCAL DEFAULT 12 wsadqwrubbmdugrxzwiv -# 30: 0400460 0 FUNC LOCAL DEFAULT 12 wrgeecrckeskyishte -# 31: 04004a0 0 FUNC LOCAL DEFAULT 12 pqhfpptwtqzuiefrwnwdk -# 32: 0600920 1 OBJECT LOCAL DEFAULT 24 vwevxfvdmcrjdv -# 33: 06006f8 0 OBJECT LOCAL DEFAULT 18 rksefyibghsyhbbnfikknpvzc - - - -import lief -import sys -import random, string - -def randomword(length): - return ''.join(random.choice(string.ascii_lowercase) for i in range(length)) - -def randomize(binary, output): - - symbols = binary.static_symbols - if len(symbols) == 0: - print("No symbols") - return - for symbol in symbols: - symbol.name = randomword(len(symbol.name)) - - binary.write(output) - -if __name__ == '__main__': - if len(sys.argv) != 3: - print("Usage:", sys.argv[0], " ") - sys.exit(-1) - - binary = lief.parse(sys.argv[1]) - randomize(binary, sys.argv[2]) - - diff --git a/vendor/lief/examples/python/elf_unstrip.py b/vendor/lief/examples/python/elf_unstrip.py deleted file mode 100644 index 6a9e30e..0000000 --- a/vendor/lief/examples/python/elf_unstrip.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# In this example, we assume that we found -# the ``main`` function at address 0x402A00 -# and we add a static symbol to the binary -# so that we can do: -# -# (gdb) break main -# Breakpoint 1 at 0x402a00 - -from lief import ELF -import sys - -binary = ELF.parse(sys.argv[1]) - -symtab_section = ELF.Section() -symtab_section.name = "" -symtab_section.type = ELF.SECTION_TYPES.SYMTAB -symtab_section.entry_size = 0x18 -symtab_section.alignment = 8 -symtab_section.link = len(binary.sections) + 1 -symtab_section.content = [0] * 100 - -symstr_section = ELF.Section() -symstr_section.name = "" -symstr_section.type = ELF.SECTION_TYPES.STRTAB -symstr_section.entry_size = 1 -symstr_section.alignment = 1 -symstr_section.content = [0] * 100 - -symtab_section = binary.add(symtab_section, loaded=False) -symstr_section = binary.add(symstr_section, loaded=False) - -symbol = ELF.Symbol() -symbol.name = "" -symbol.type = ELF.SYMBOL_TYPES.NOTYPE -symbol.value = 0 -symbol.binding = ELF.SYMBOL_BINDINGS.LOCAL -symbol.size = 0 -symbol.shndx = 0 -symbol = binary.add_static_symbol(symbol) - -symbol = ELF.Symbol() -symbol.name = "main" -symbol.type = ELF.SYMBOL_TYPES.FUNC -symbol.value = 0x402A00 -symbol.binding = ELF.SYMBOL_BINDINGS.LOCAL -symbol.shndx = 14 -symbol = binary.add_static_symbol(symbol) - -print(symbol) - -binary.write(sys.argv[2]) - diff --git a/vendor/lief/examples/python/entropy.py b/vendor/lief/examples/python/entropy.py deleted file mode 100644 index 3ded310..0000000 --- a/vendor/lief/examples/python/entropy.py +++ /dev/null @@ -1,103 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Inspired from binwalk: https://github.com/devttys0/binwalk/ -# -# Description: -# Show show entropy of the differents binary's section -# -# Requirement: pyqtgraph - - -import pyqtgraph as pg -import sys -import math -from lief import parse, ELF, PE -from pyqtgraph.Qt import QtCore, QtGui - - -class Entropy(object): - - DEFAULT_BLOCK_SIZE = 512 - DEFAULT_DATA_POINTS = 2048 - DEFAULT_THRESHOLD = 9 - - def __init__(self, path): - self.binary = parse(path) - self.block_size = None - self.result = dict((section, []) for section in self.binary.sections) - - - def entropy(self, data): - entropy = 0 - - if data: - length = len(data) - - seen = dict(((x, 0) for x in range(0, 256))) - for byte in data: - seen[byte] += 1 - - for x in range(0, 256): - p_x = float(seen[x]) / length - if p_x > 0: - entropy -= p_x * math.log(p_x, 2) - - return (entropy) - - def compute_entropy_section(self, section): - content = section.content - size = len(content) - - if self.block_size is None: - block_size = size / self.DEFAULT_DATA_POINTS - # Round up to the nearest DEFAULT_BLOCK_SIZE - block_size = int(block_size + ((self.DEFAULT_BLOCK_SIZE - block_size) % self.DEFAULT_BLOCK_SIZE)) - else: - block_size = self.block_size - - if block_size <= 0: - block_size = self.DEFAULT_BLOCK_SIZE - - i = 0 - while (i + block_size) < size: - entropy = self.entropy(content[i:i + block_size]) - self.result[section].append((section.offset + i , entropy)) - i += block_size - - - def plot(self): - plt = pg.plot(title = "Entropy") - plt.addLegend() - - for idx, (section, result) in enumerate(self.result.items()): - x = [] - y = [] - for offset, entropy in result: - x.append(offset) - y.append(entropy) - if len(result) > self.DEFAULT_THRESHOLD: - c1 = plt.plot(x, y,\ - pen=pg.intColor(idx * 10, 100),\ - name=section.name,\ - antialias = True,\ - fillLevel=0,\ - fillBrush=pg.intColor(idx * 10, 100, alpha = 40)) - - def run(self): - - for section in self.binary.sections: - self.compute_entropy_section(section) - self.plot() - - if (sys.flags.interactive != 1) or not hasattr(QtCore, 'PYQT_VERSION'): - QtGui.QApplication.instance().exec_() - - -if __name__ == '__main__': - if len(sys.argv) != 2: - print("Usage: {} ".format(sys.argv[0])) - sys.exit(0); - - Entropy(sys.argv[1]).run() - diff --git a/vendor/lief/examples/python/json_dump.py b/vendor/lief/examples/python/json_dump.py deleted file mode 100644 index 4176452..0000000 --- a/vendor/lief/examples/python/json_dump.py +++ /dev/null @@ -1,14 +0,0 @@ -import lief -import json -import sys - -if len(sys.argv) != 2: - print("Usage: {} ".format(sys.argv[0])) - sys.exit(1) - - -obj = lief.parse(sys.argv[1]) - -json_data = json.loads(lief.to_json(obj)) - -print(json.dumps(json_data, sort_keys = True, indent = 4)) diff --git a/vendor/lief/examples/python/keygen/KeygenMe b/vendor/lief/examples/python/keygen/KeygenMe deleted file mode 100644 index 9c642d0..0000000 Binary files a/vendor/lief/examples/python/keygen/KeygenMe and /dev/null differ diff --git a/vendor/lief/examples/python/keygen/lief_patch.py b/vendor/lief/examples/python/keygen/lief_patch.py deleted file mode 100644 index c5d0e2d..0000000 --- a/vendor/lief/examples/python/keygen/lief_patch.py +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env python2 - -# Description -# ----------- -# Patch binary to remove anti-debug - -import sys -from lief import ELF -import distorm3 - - -def remove_anti_debug(binary): - patch = [0x83, 0xf8, 0xff, 0x90, 0x90] # cmp eax, 0xFFFFFFFF - ep = binary.header.entrypoint - text_section = binary.section_from_virtual_address(ep) - code = "".join(map(chr, text_section.content)) - iterable = distorm3.DecodeGenerator(text_section.virtual_address, code, distorm3.Decode32Bits) - for (offset, size, instruction, hexdump) in iterable: - if "CMP EAX, 0x3000" in instruction: - # Patch 3d 00 30 00 00 - binary.patch_address(offset, patch) - print("[PATCH] %.8x: %-32s %s" % (offset, hexdump, instruction)) - - # Distorm didn't get this one - binary.patch_address(0x804936B, patch) - -def crack_it(binary): - # user: what you wants - # serial: any NUMBER - - patch1 = [0x31, 0xD2] # xor edx, edx - patch2 = [0x31, 0xC0] # xor eax, eax - - binary.patch_address(0x8049486, patch1) # xor edx, edi --> xor edx, edx - binary.patch_address(0x8049488, patch2) # xor eax, ecx --> xor eax, eax - -def main(argv): - binary = ELF.parse("./KeygenMe") - remove_anti_debug(binary) - crack_it(binary) - binary.write("./KeygenMe.crack") - return 0 - - -if __name__ == "__main__": - sys.exit(main(sys.argv)) - - - - diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/Makefile b/vendor/lief/examples/python/library_symbols_obfuscation/Makefile deleted file mode 100644 index d8f333f..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -CC=gcc -CXX=g++ - -all: binadd.bin obfu - -libadd.so: libadd.c - $(CC) -Wl,--hash-style=gnu -fPIC -shared -o $@ $^ - -binadd.bin: binadd.c libadd.so - $(CC) $^ -Wl,--hash-style=gnu -L. -ladd -o $@ - chmod a+rx $@ - -run: libadd.so binadd.bin obfu - LD_LIBRARY_PATH=. ./binadd.bin 1 2 - LD_LIBRARY_PATH=. ./binadd_obf.bin 1 2 - - -obfu: binadd.bin libadd.so - python ./obfu.py - chmod a+x *.bin - chmod a+x *.so - -.PHONY: clean - -clean: - rm -rf *.o *~ *.so *.bin diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/README.md b/vendor/lief/examples/python/library_symbols_obfuscation/README.md deleted file mode 100644 index 7491e39..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/README.md +++ /dev/null @@ -1,8 +0,0 @@ -Presentation -============ - -The aim of this example is to show how we can change dynamic symbols in both -library and binary. - -In the example we will change the symbol `add` to `abc` and the library name -`libadd.so` to `libabc.so` diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/binadd.c b/vendor/lief/examples/python/library_symbols_obfuscation/binadd.c deleted file mode 100644 index d1a0cbb..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/binadd.c +++ /dev/null @@ -1,16 +0,0 @@ -#include -#include - -#include "libadd.h" - -int main(int argc, char **argv) { - if (argc != 3) { - printf("Usage: %s \n", argv[0]); - exit(-1); - } - - int res = add(atoi(argv[1]), atoi(argv[2])); - printf("From myLIb, a + b = %d\n", res); - return 0; -} - diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/libadd.c b/vendor/lief/examples/python/library_symbols_obfuscation/libadd.c deleted file mode 100644 index 6611953..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/libadd.c +++ /dev/null @@ -1,9 +0,0 @@ -#include -#include -#include "libadd.h" - -int add(int a, int b) { - printf("%d + %d = %d\n", a, b, a+b); - return a + b; -} - diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/libadd.h b/vendor/lief/examples/python/library_symbols_obfuscation/libadd.h deleted file mode 100644 index 1c2e626..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/libadd.h +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -int add(int a, int b); diff --git a/vendor/lief/examples/python/library_symbols_obfuscation/obfu.py b/vendor/lief/examples/python/library_symbols_obfuscation/obfu.py deleted file mode 100644 index 9cacecd..0000000 --- a/vendor/lief/examples/python/library_symbols_obfuscation/obfu.py +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env python -import lief - -libadd = lief.ELF.parse("./libadd.so") -binadd = lief.ELF.parse("./binadd.bin") - -libadd_dynsym = libadd.dynamic_symbols -binadd_dynsym = binadd.dynamic_symbols - -# Change add in the libary -for sym in libadd_dynsym: - if sym.name == "add": - sym.name = "abc" - -# Change "add" in the binary -for sym in binadd_dynsym: - if sym.name == "add": - sym.name = "abc" - - -# change library name in the binary -for entry in binadd.dynamic_entries: - if entry.tag == lief.ELF.NEEDED and entry.name == "libadd.so": - entry.name = "libabc.so" - - -libadd.write("libabc.so"); -binadd.write("binadd_obf.bin") - - diff --git a/vendor/lief/examples/python/macho_parser_tweak.py b/vendor/lief/examples/python/macho_parser_tweak.py deleted file mode 100644 index 7d6f483..0000000 --- a/vendor/lief/examples/python/macho_parser_tweak.py +++ /dev/null @@ -1,23 +0,0 @@ -import lief -import sys -import time - -# Do not parse dyld info -config = lief.MachO.ParserConfig() -config.parse_dyld_bindings = False -config.parse_dyld_exports = False -config.parse_dyld_rebases = False - -t1 = time.time() -lief.MachO.parse(sys.argv[1], config) -t2 = time.time() -print(f"Done in {t2 - t1}s") - - -# Parse the dyld information -config.full_dyldinfo(True) - -t1 = time.time() -lief.MachO.parse(sys.argv[1], config) -t2 = time.time() -print(f"Done in {t2 - t1}s") diff --git a/vendor/lief/examples/python/macho_reader.py b/vendor/lief/examples/python/macho_reader.py deleted file mode 100644 index c50345c..0000000 --- a/vendor/lief/examples/python/macho_reader.py +++ /dev/null @@ -1,1028 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a Mach-O binary - -import sys -import os -import argparse -import traceback -import lief -from lief import MachO - -terminal_rows, terminal_columns = 100, 100 -try: - terminal_rows, terminal_columns = os.popen('stty size', 'r').read().split() -except ValueError: - pass - -terminal_columns = int(terminal_columns) -terminal_rows = int(terminal_rows) -EXIT_STATUS = 0 - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - global EXIT_STATUS - print("{} raised: {}".format(self.func.__name__, e)) - EXIT_STATUS = 1 - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - - - -@exceptions_handler(Exception) -def print_information(binary): - print("== Information ==") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - header: lief.MachO.Header = binary.header - cpu = str(header.cpu_type).split('.')[-1] - - - print(format_str.format("Name:", binary.name)) - print(format_hex.format("Address base:", binary.imagebase)) - print(format_str.format("PIE:", str(binary.is_pie))) - print(format_str.format("NX:", str(binary.has_nx))) - print(format_str.format("Arch:", cpu)) - print("") - -@exceptions_handler(Exception) -def print_header(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - print("== Header ==") - header = binary.header - flags_str = " - ".join([str(s).split(".")[-1] for s in header.flags_list]) - - print(format_str.format("Magic:", str(header.magic).split(".")[-1])) - print(format_str.format("CPU Type:", str(header.cpu_type).split(".")[-1])) - print(format_hex.format("CPU sub-type:", header.cpu_subtype)) - print(format_str.format("File Type:", str(header.file_type).split(".")[-1])) - print(format_str.format("Flags:", flags_str)) - print(format_dec.format("Number of commands:", header.nb_cmds)) - print(format_hex.format("Size of commands:", header.sizeof_cmds)) - print(format_hex.format("Reserved:", header.reserved)) - -@exceptions_handler(Exception) -def print_commands(binary): - - f_title = "|{:<20}|{:<11}|{:<11}|" - f_value = "|{:<20}|0x{:08x} |0x{:08x} |" - print("== Commands ==") - print(f_title.format("Command", "Offset", "Size")) - for command in binary.commands: - print(f_value.format( - str(command.command).split(".")[-1], - command.command_offset, - command.size)) - print("") - -@exceptions_handler(Exception) -def print_libraries(binary): - - f_title = "|{:<30}|{:<10}|{:<16}|{:<22}|" - f_value = "|{:<30}|{:<10d}|{:<16}|{:<22}|" - print("== Libraries ==") - print(f_title.format("Name", "Timestamp", "Current Version", "Compatibility Version")) - for library in binary.libraries: - current_version_str = "{:d}.{:d}.{:d}".format(*library.current_version) - compatibility_version_str = "{:d}.{:d}.{:d}".format(*library.compatibility_version) - print(f_value.format( - library.name, - library.timestamp, - current_version_str, - compatibility_version_str)) - print("") - -@exceptions_handler(Exception) -def print_segments(binary): - - f_title = "|{:<20}|{:<16}|{:<16}|{:<16}|{:16}|{:16}|{:16}|{}" - f_value = "|{:<20}|0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |{}" - print("== Segments ==") - print(f_title.format( - "Name", "Virtual Address", "Virtual Size", - "Offset", "Size", "Max Protection", - "Init Protection", "Sections")) - for segment in binary.segments: - sections = ", ".join(map(lambda s : s.name, segment.sections)) - print(f_value.format( - segment.name, - segment.virtual_address, - segment.virtual_size, - segment.file_offset, - segment.file_size, - segment.max_protection, - segment.init_protection, - sections)) - - print("") - -@exceptions_handler(Exception) -def print_sections(binary): - - f_title = "|{:<20}|{:<16}|{:<16}|{:<16}|{:16}|{:22}|{:19}|{:25}|{:25}|" - f_value = "|{:<20}|0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<13x} |0x{:<19x} |0x{:<16x} |{:<25}|{:<25}" - - print("== Sections ==") - - print(f_title.format( - "Name", "Virtual Address", "Offset", "Size", - "Alignement", "Number of Relocations", "Relocation offset", - "Type", "Flags")) - - - - - for section in binary.sections: - flags_str = " - ".join([str(s).split(".")[-1] for s in section.flags_list]) - print(f_value.format( - section.name, - section.virtual_address, - section.offset, - section.size, - section.alignment, - section.numberof_relocations, - section.relocation_offset, - str(section.type).split(".")[-1], - flags_str)) - if len(section.relocations) > 0: - for idx, reloc in enumerate(section.relocations): - name = reloc.symbol.name if reloc.has_symbol else "" - secname = " - " + reloc.section.name if reloc.has_section else "" - type = str(reloc.type) - if reloc.architecture == MachO.CPU_TYPES.x86: - type = str(MachO.X86_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.x86_64: - type = str(MachO.X86_64_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.ARM: - type = str(MachO.ARM_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.ARM64: - type = str(MachO.ARM64_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.POWERPC: - type = str(MachO.PPC_RELOCATION(reloc.type)) - - - print(" [Reloc #{:d} {section}] {name:<10} 0x{address:<6x} {type:<20} {size:d} {pcrel} {scat}".format( - idx, - section=secname, - name=name, - address=reloc.address, - type=type.split(".")[-1], - size=reloc.size, - pcrel=str(reloc.pc_relative), - scat=str(reloc.is_scattered))) - print("") - - - print("") - -@exceptions_handler(Exception) -def print_symbols(binary): - symbols = binary.symbols - if len(symbols) == 0: - return - try: - maxsize = max([len(symbol.demangled_name) for symbol in symbols]) - except: - maxsize = max([len(symbol.name) for symbol in symbols]) - maxsize = min(maxsize, terminal_columns - 90) if terminal_columns > 90 else terminal_columns - - f_title = "|{:<" + str(maxsize) + "} |{:<6}|{:<19}|{:<16}|{:16}| {:s}" - f_value = "|{:<" + str(maxsize) + "} |0x{:<3x} |0x{:<16x} |0x{:<13x} |0x{:<13x} | {:s}" - print("== Symbols ==") - print(f_title.format( - "Name", "Type", "Number of Sections", "Description", "Value", "Library")) - for symbol in binary.symbols: - libname = "" - if symbol.has_binding_info and symbol.binding_info.has_library: - libname = symbol.binding_info.library.name - - - symbol_value = 0 - if symbol.has_export_info: - symbol_value = symbol.export_info.address - elif symbol.has_binding_info: - symbol_value = symbol.binding_info.address - else: - symbol_value = symbol.value - - try: - symbol_name = symbol.demangled_name - except: - symbol_name = symbol.name - print(f_value.format( - symbol_name, - symbol.type, - symbol.numberof_sections, - symbol.description, - symbol_value, - libname)) - print("") - -@exceptions_handler(Exception) -def print_symbol_command(binary): - print("== Symbol Command ==") - - scmd = binary.symbol_command - - format_str = "{:<17} {:<30}" - format_hex = "{:<17} 0x{:<28x}" - format_dec = "{:<17} {:<30d}" - - print(format_hex.format("Symbol offset", scmd.symbol_offset)) - print(format_dec.format("Number of symbols", scmd.numberof_symbols)) - - print(format_hex.format("String offset", scmd.strings_offset)) - print(format_hex.format("String size", scmd.strings_size)) - - print("") - -@exceptions_handler(Exception) -def print_dynamic_symbol_command(binary): - print("== Dynamic Symbol Command ==") - - dyscmd = binary.dynamic_symbol_command - - format_str = "{:<36} {:<30}" - format_hex = "{:<36} 0x{:<28x}" - format_dec = "{:<36} {:<30d}" - - print(format_dec.format("First local symbol index", dyscmd.idx_local_symbol)) - print(format_dec.format("Number of local symbols", dyscmd.nb_local_symbols)) - - print(format_dec.format("External symbol index", dyscmd.idx_external_define_symbol)) - print(format_dec.format("Number of external symbols", dyscmd.nb_external_define_symbols)) - - print(format_dec.format("Undefined symbol index", dyscmd.idx_undefined_symbol)) - print(format_dec.format("Number of undefined symbols", dyscmd.nb_undefined_symbols)) - - print(format_dec.format("Table of content offset", dyscmd.toc_offset)) - print(format_dec.format("Number of entries in TOC", dyscmd.nb_toc)) - - print(format_hex.format("Module table offset", dyscmd.module_table_offset)) - print(format_dec.format("Number of entries in module table", dyscmd.nb_module_table)) - - print(format_hex.format("External reference table offset", dyscmd.external_reference_symbol_offset)) - print(format_dec.format("Number of external reference", dyscmd.nb_external_reference_symbols)) - - print(format_hex.format("Indirect symbols offset", dyscmd.indirect_symbol_offset)) - print(format_dec.format("Number of indirect symbols", dyscmd.nb_indirect_symbols)) - - print(format_hex.format("External relocation offset", dyscmd.external_relocation_offset)) - print(format_dec.format("Number of external relocations", dyscmd.nb_external_relocations)) - - print(format_hex.format("Local relocation offset", dyscmd.local_relocation_offset)) - print(format_dec.format("Number of local relocations", dyscmd.nb_local_relocations)) - - print("") - - -@exceptions_handler(Exception) -def print_uuid(binary): - print("== UUID ==") - cmd = binary.uuid - uuid_str = " ".join(map(lambda e : "{:02x}".format(e), cmd.uuid)) - print("UUID: {}".format(uuid_str)) - - print("") - - -@exceptions_handler(Exception) -def print_main_command(binary): - - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Main Command ==") - cmd = binary.main_command - - print(format_hex.format("Entry point:", cmd.entrypoint)) - print(format_hex.format("Stack size:", cmd.stack_size)) - - print("") - - -@exceptions_handler(Exception) -def print_thread_command(binary): - - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Thread Command ==") - cmd = binary.thread_command - - print(format_hex.format("Flavor:", cmd.flavor)) - print(format_hex.format("Count:", cmd.count)) - print(format_hex.format("PC:", cmd.pc)) - - print("") - -@exceptions_handler(Exception) -def print_rpath_command(binary): - - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Rpath Command ==") - cmd = binary.rpath - print("Path: {}".format(cmd.path)) - - - print("") - - - -@exceptions_handler(Exception) -def print_dylinker(binary): - print("== Dylinker ==") - print("Path: {}".format(binary.dylinker.name)) - - print("") - -@exceptions_handler(Exception) -def print_function_starts(binary): - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Function Starts ==") - - fstarts = binary.function_starts - - print(format_hex.format("Offset:", fstarts.data_offset)) - print(format_hex.format("Size:", fstarts.data_size)) - print("Functions: ({:d})".format(len(fstarts.functions))) - for idx, address in enumerate(fstarts.functions): - print(" [{:d}] __TEXT + 0x{:x}".format(idx, address)) - - print("") - -@exceptions_handler(Exception) -def print_data_in_code(binary): - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Data In Code ==") - - datacode = binary.data_in_code - - print(format_hex.format("Offset:", datacode.data_offset)) - print(format_hex.format("Size:", datacode.data_size)) - print("") - for entry in datacode.entries: - type_str = str(entry.type).split(".")[-1] - print("- {:<14}: 0x{:x} ({:d} bytes)".format(type_str, entry.offset, entry.length)) - print("") - - -@exceptions_handler(Exception) -def print_segment_split_info(binary): - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Segment Split Info ==") - - sinfo = binary.segment_split_info - - print(format_hex.format("Offset:", sinfo.data_offset)) - print(format_hex.format("Size:", sinfo.data_size)) - - print("") - - -@exceptions_handler(Exception) -def print_sub_framework(binary): - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Sub Framework ==") - - sinfo = binary.sub_framework - print(format_str.format("Umbrella:", sinfo.umbrella)) - - print("") - -@exceptions_handler(Exception) -def print_dyld_environment(binary): - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Dyld Environment ==") - - env = binary.dyld_environment - print(format_str.format("Value:", env.value)) - - print("") - - -@exceptions_handler(Exception) -def print_dyld_info(binary): - print("== Dyld Info ==") - f_title = "|{:<12}|{:<11}|{:<11}|" - f_value = "|{:<12}|0x{:<8x} |0x{:<8x} |" - - dyld_info = binary.dyld_info - - print(f_title.format("Type", "Offset", "Size")) - print(f_value.format("Rebase", dyld_info.rebase[0], dyld_info.rebase[1])) - print(f_value.format("Bind", dyld_info.bind[0], dyld_info.bind[1])) - print(f_value.format("Weak Bind", dyld_info.weak_bind[0], dyld_info.weak_bind[1])) - print(f_value.format("Lazy Bind", dyld_info.lazy_bind[0], dyld_info.lazy_bind[1])) - print(f_value.format("Export", dyld_info.export_info[0], dyld_info.export_info[1])) - - print("") - - print("Bindings") - print("--------") - for idx, binfo in enumerate(dyld_info.bindings): - print("{:10}: {}".format("Class", str(binfo.binding_class).split(".")[-1])) - print("{:10}: {}".format("Type", str(binfo.binding_type).split(".")[-1])) - print("{:10}: {:x}".format("Address", binfo.address)) - - if binfo.has_symbol: - print("{:10}: {}".format("Symbol", binfo.symbol.name)) - - if binfo.has_segment: - print("{:10}: {}".format("Segment", binfo.segment.name)) - - if binfo.has_library: - print("{:10}: {}".format("Library", binfo.library.name)) - - if binfo.binding_class == lief.MachO.BINDING_CLASS.LAZY: - print("{:10}: {}".format("Offset", binfo.original_offset)) - - print("") - - print("") - - print("Exports") - print("-------") - for idx, einfo in enumerate(dyld_info.exports): - output = "0x{:08x} - {}".format(einfo.address, einfo.symbol.name) - if einfo.alias: - output += " - {}".format(einfo.alias.name) - if einfo.alias_library: - output += " from {}".format(einfo.alias_library.name) - print(output) - - #print("{:10}: {:<10x}".format("Address", einfo.address)) - #print("{:10}: {:<10x}".format("Flags", einfo.flags)) - - #if binfo.has_symbol: - # print("{:10}: {}".format("Symbol", einfo.symbol.name)) - - print("") - - - - print("") - - -@exceptions_handler(Exception) -def print_rebase_opcodes(binary): - print("== Rebase opcodes ==") - - print(binary.dyld_info.show_rebases_opcodes) - - print("") - -@exceptions_handler(Exception) -def print_bind_opcodes(binary): - print("== Bind opcodes ==") - - print(binary.dyld_info.show_bind_opcodes) - - print("") - -@exceptions_handler(Exception) -def print_weak_bind_opcodes(binary): - print("== Weak bind opcodes ==") - - print(binary.dyld_info.show_weak_bind_opcodes) - - print("") - -@exceptions_handler(Exception) -def print_lazy_bind_opcodes(binary): - print("== Lazy bind opcodes ==") - - print(binary.dyld_info.show_lazy_bind_opcodes) - - print("") - -@exceptions_handler(Exception) -def print_export_trie(binary): - print("== Export trie ==") - if binary.has_dyld_info: - print(binary.dyld_info.show_export_trie) - if binary.has_dyld_exports_trie: - trie: lief.MachO.DyldExportsTrie = binary.dyld_exports_trie - print("Linkedit position: 0x{} (0x{:x} bytes)".format(trie.data_offset, trie.data_size)) - print(trie.show_export_trie()) - - print("") - -@exceptions_handler(Exception) -def print_source_version(binary): - print("== Source Version ==") - - version = binary.source_version.version - - print("Version: {:d}.{:d}.{:d}.{:d}.{:d}".format(*version)) - - print("") - - -@exceptions_handler(Exception) -def print_version_min(binary): - print("== Version Min ==") - - version = binary.version_min.version - sdk = binary.version_min.sdk - - print("Version: {:d}.{:d}.{:d}".format(*version)) - print("SDK: {:d}.{:d}.{:d}".format(*sdk)) - - print("") - - -@exceptions_handler(Exception) -def print_relocations(binary): - print("== Relocations ==") - - f_value = "|0x{address:<10x} | {size:<4d} | {type:<15} | {pcrel:<11} | {secseg:<23} | {symbol}" - f_title = "|{address:<12} | {size:<4} | {type:<15} | {pcrel:<11} | {secseg:<23} | {symbol}" - - print(f_title.format( - address="Address", - size="Size", - type="Type", - pcrel="PC Relative", - secseg="Section/Section", - symbol="Symbol")) - - - for reloc in binary.relocations: - type_str = "" - if reloc.origin == lief.MachO.RELOCATION_ORIGINS.DYLDINFO: - type_str = str(lief.MachO.REBASE_TYPES(reloc.type)).split(".")[-1] - - if reloc.origin == lief.MachO.RELOCATION_ORIGINS.RELOC_TABLE: - if reloc.architecture == MachO.CPU_TYPES.x86: - type_str = str(MachO.X86_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.x86_64: - type_str = str(MachO.X86_64_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.ARM: - type_str = str(MachO.ARM_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.ARM64: - type_str = str(MachO.ARM64_RELOCATION(reloc.type)) - - if reloc.architecture == MachO.CPU_TYPES.POWERPC: - type_str = str(MachO.PPC_RELOCATION(reloc.type)) - - type_str = type_str.split(".")[-1] - - symbol_name = "" - if reloc.has_symbol: - symbol_name = reloc.symbol.name - - secseg_name = "" - if reloc.has_segment and reloc.has_section: - secseg_name = "{}.{}".format(reloc.segment.name, reloc.section.name) - else: - if reloc.has_segment: - secseg_name = reloc.segment.name - - if reloc.has_section: - secseg_name = reloc.section.name - - print(f_value.format( - address=reloc.address, - size=reloc.size, - type=type_str, - pcrel=str(reloc.pc_relative), - secseg=secseg_name, - symbol=symbol_name)) - - - print("") - -@exceptions_handler(Exception) -def print_encryption_info(binary): - - format_str = "{:<13} {:<30}" - format_hex = "{:<13} 0x{:<28x}" - format_dec = "{:<13} {:<30d}" - - print("== Encryption Info ==") - cmd = binary.encryption_info - - print(format_hex.format("Offset:", cmd.crypt_offset)) - print(format_hex.format("Size:", cmd.crypt_size)) - print(format_dec.format("ID:", cmd.crypt_id)) - - print("") - - -@exceptions_handler(Exception) -def print_ctor(binary): - print("== Constructors ==\n") - - print("Functions: ({:d})".format(len(binary.ctor_functions))) - for idx, f in enumerate(binary.ctor_functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - - -@exceptions_handler(Exception) -def print_unwind_functions(binary): - print("== Unwind functions ==\n") - - print("Functions: ({:d})".format(len(binary.unwind_functions))) - for idx, f in enumerate(binary.unwind_functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - -@exceptions_handler(Exception) -def print_functions(binary): - print("== Functions ==\n") - - print("Functions: ({:d})".format(len(binary.functions))) - for idx, f in enumerate(binary.functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - -@exceptions_handler(Exception) -def print_build_version(binary): - print("== Build Version ==\n") - - build_version = binary.build_version - - print("Platform: {}".format(str(build_version.platform).split(".")[-1])) - print("Min OS: {:d}.{:d}.{:d}".format(*build_version.minos)) - print("SDK: {:d}.{:d}.{:d}".format(*build_version.sdk)) - - tools = build_version.tools - if len(tools) > 0: - print("~~ Tools ({}) ~~".format(len(tools))) - for tool in tools: - tool_str = str(tool.tool).split(".")[-1] - print(" {} - {}.{}.{}".format(tool_str, *tool.version)) - -def print_chained_fixups(binary: lief.MachO.Binary): - if not binary.has_dyld_chained_fixups: - return - print("== Dyld Chained Fixups ==") - fixups: lief.MachO.DyldChainedFixups = binary.dyld_chained_fixups - print(fixups) - - -def main(): - parser = argparse.ArgumentParser(usage='%(prog)s [options] ') - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-c', '--commands', - action='store_true', dest='show_commands', - help='Display Commands') - - parser.add_argument('-H', '--header', - action='store_true', dest='show_header', - help='Display header') - - parser.add_argument('-L', '--libraries', - action='store_true', dest='show_libraries', - help='Display Imported Libraries') - - parser.add_argument('-l', '--segments', - action='store_true', dest='show_segments', - help='Display Segments') - - parser.add_argument('-r', '--relocations', - action='store_true', dest='show_relocs', - help='Display the relocations (if present)') - - parser.add_argument('-s', '--symbols', - action='store_true', dest='show_symbols', - help='Display Symbols') - - parser.add_argument('-S', '--sections', - action='store_true', dest='show_sections', - help='Display Sections') - - parser.add_argument('--uuid', - action='store_true', dest='show_uuid', - help='Display the UUID command') - - parser.add_argument('--main', - action='store_true', dest='show_main', - help='Display the Main command') - - parser.add_argument('--dylinker', - action='store_true', dest='show_dylinker', - help='Display the Dylinker command') - - parser.add_argument('--dyldinfo', - action='store_true', dest='show_dyldinfo', - help='Display the DyldInfo command') - - parser.add_argument('--function-starts', - action='store_true', dest='show_function_starts', - help='Display the FunctionStarts command') - - parser.add_argument('--rebase-opcodes', - action='store_true', dest='show_rebase_opcodes', - help='Display the "Rebase" opcodes') - - parser.add_argument('--source-version', - action='store_true', dest='show_source_version', - help="Display the 'Source Version' command") - - parser.add_argument('--version-min', - action='store_true', dest='show_version_min', - help="Display the 'Version Min' command") - - parser.add_argument('--thread-command', - action='store_true', dest='show_thread_command', - help="Display the 'Thread Command' command") - - parser.add_argument('--rpath-command', - action='store_true', dest='show_rpath_command', - help="Display the 'Rpath Command' command") - - parser.add_argument('--symbol-command', - action='store_true', dest='show_symbol_command', - help="Display the 'Symbol Command' command") - - parser.add_argument('--dynamic-symbol-command', - action='store_true', dest='show_dynamic_symbol_command', - help="Display the 'Symbol Command' command") - - parser.add_argument('--data-in-code', - action='store_true', dest='show_data_in_code', - help="Display the 'Data In Code' command") - - parser.add_argument('--segment-split-info', - action='store_true', dest='show_segment_split_info', - help="Display the 'Segment Split Info' command") - - parser.add_argument('--sub-framework', - action='store_true', dest='show_sub_framework', - help="Display the 'Sub Framework' command") - - parser.add_argument('--dyld-environment', - action='store_true', dest='show_dyld_env', - help="Display the 'Dyld Environment' command") - - parser.add_argument('--encryption-info', - action='store_true', dest='show_encrypt_info', - help="Display the 'Encryption Info' command") - - parser.add_argument('--bind-opcodes', - action='store_true', dest='show_bind_opcodes', - help='Display the "Bind" opcodes') - - parser.add_argument('--weak-bind-opcodes', - action='store_true', dest='show_weak_bind_opcodes', - help='Display the "Weak Bind" opcodes') - - parser.add_argument('--lazy-bind-opcodes', - action='store_true', dest='show_lazy_bind_opcodes', - help='Display the "Lazy Bind" opcodes') - - parser.add_argument('--export-trie', - action='store_true', dest='show_export_trie', - help='Display the export trie') - - parser.add_argument('--opcodes', - action='store_true', dest='show_opcodes', - help='Display the bind and rebase opcodes') - - parser.add_argument('--ctor', - action='store_true', dest='show_ctor', - help='Constructor functions') - - parser.add_argument('--unwind-functions', - action='store_true', dest='show_ufunctions', - help='Functions from unwind info') - - parser.add_argument('--functions', - action='store_true', dest='show_functions', - help='All functions found in the binary') - - parser.add_argument('--build-version', - action='store_true', dest='show_build_version', - help='Show build version') - - parser.add_argument('--chained-fixups', - action='store_true', dest='show_chained_fixups', - help='Show Dyld Chained Fixups') - - parser.add_argument('--check-layout', - action='store_true', dest='check_layout', - help='Check the layout of the binary') - - parser.add_argument("binary", - metavar="", - help='Target Mach-O File') - - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - - lief.logging.set_level(args.main_verbosity) - - binaries = MachO.parse(args.binary) - if binaries is None: - print("Can't parse {}".format(args.binary)) - sys.exit(1) - - if len(binaries) > 1: - print("Fat Mach-O: {:d} binaries".format(len(binaries))) - - if args.check_layout: - isok, err = MachO.check_layout(binaries) - if not isok: - print(err) - - for binary in binaries: - print_information(binary) - - if args.show_header or args.show_all: - print_header(binary) - - if args.show_commands or args.show_all: - print_commands(binary) - - if args.show_libraries or args.show_all: - print_libraries(binary) - - if args.show_segments or args.show_all: - print_segments(binary) - - if args.show_sections or args.show_all: - print_sections(binary) - - if args.show_symbols or args.show_all: - print_symbols(binary) - - if (args.show_uuid or args.show_all) and binary.has_uuid: - print_uuid(binary) - - if (args.show_main or args.show_all) and binary.has_main_command: - print_main_command(binary) - - if (args.show_dylinker or args.show_all) and binary.has_dylinker: - print_dylinker(binary) - - if (args.show_dyldinfo or args.show_all) and binary.has_dyld_info: - print_dyld_info(binary) - - if (args.show_function_starts or args.show_all) and binary.has_function_starts: - print_function_starts(binary) - - if (args.show_source_version or args.show_all) and binary.has_source_version: - print_source_version(binary) - - if (args.show_version_min or args.show_all) and binary.has_version_min: - print_version_min(binary) - - if (args.show_relocs or args.show_all) and len(binary.relocations) > 0: - print_relocations(binary) - - if (args.show_thread_command or args.show_all) and binary.has_thread_command: - print_thread_command(binary) - - if (args.show_rpath_command or args.show_all) and binary.has_rpath: - print_rpath_command(binary) - - if (args.show_symbol_command or args.show_all) and binary.has_symbol_command: - print_symbol_command(binary) - - if (args.show_dynamic_symbol_command or args.show_all) and binary.has_dynamic_symbol_command: - print_dynamic_symbol_command(binary) - - if (args.show_data_in_code or args.show_all) and binary.has_data_in_code: - print_data_in_code(binary) - - if (args.show_segment_split_info or args.show_all) and binary.has_segment_split_info: - print_segment_split_info(binary) - - if (args.show_sub_framework or args.show_all) and binary.has_sub_framework: - print_sub_framework(binary) - - if (args.show_dyld_env or args.show_all) and binary.has_dyld_environment: - print_dyld_environment(binary) - - if (args.show_encrypt_info or args.show_all) and binary.has_encryption_info: - print_encryption_info(binary) - - if (args.show_rpath_command or args.show_all) and binary.has_rpath: - print_rpath_command(binary) - - if (args.show_rebase_opcodes or args.show_opcodes) and binary.has_dyld_info: - print_rebase_opcodes(binary) - - if (args.show_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: - print_bind_opcodes(binary) - - if (args.show_weak_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: - print_weak_bind_opcodes(binary) - - if (args.show_lazy_bind_opcodes or args.show_opcodes) and binary.has_dyld_info: - print_lazy_bind_opcodes(binary) - - if (args.show_export_trie or args.show_opcodes): - print_export_trie(binary) - - if args.show_ctor or args.show_all: - print_ctor(binary) - - if args.show_ufunctions or args.show_all: - print_unwind_functions(binary) - - if args.show_functions or args.show_all: - print_functions(binary) - - if (args.show_build_version or args.show_all) and binary.has_build_version: - print_build_version(binary) - - if args.show_chained_fixups or args.show_all: - print_chained_fixups(binary) - - - sys.exit(EXIT_STATUS) - - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/python/nm.py b/vendor/lief/examples/python/nm.py deleted file mode 100644 index ed6260c..0000000 --- a/vendor/lief/examples/python/nm.py +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# -# This tool is a cross format Linux nm like. It prints all symbols -# present in the binary. For `PE` it will print symbols in the *symbol section* -# and for `ELF` it will print *static* symbols **AND** *dynamic* symbols. -# -# Example: -# -# >>> nm("/usr/bin/ls") -# >>> nm("C:\\Windows\\explorer.exe") - -import sys -from lief import parse - -def nm(filename): - """ Return symbols from *filename* binary """ - binary = parse(filename) # Build an abstract binary - symbols = binary.symbols - - if len(symbols) > 0: - for symbol in symbols: - print(symbol) - else: - print("No symbols found") - - -if __name__ == "__main__": - - if len(sys.argv) != 2: - print("Usage: " + sys.argv[0] + " ") - sys.exit(-1) - - nm(sys.argv[1]) - - diff --git a/vendor/lief/examples/python/oat_reader.py b/vendor/lief/examples/python/oat_reader.py deleted file mode 100644 index ac7d2ba..0000000 --- a/vendor/lief/examples/python/oat_reader.py +++ /dev/null @@ -1,211 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a Android OAT files - -import argparse -import os -import sys -import traceback - -import lief -from lief import OAT - -EXIT_STATUS = 0 -terminal_rows, terminal_columns = 100, 100 -try: - terminal_rows, terminal_columns = os.popen('stty size', 'r').read().split() -except ValueError: - pass - - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - global EXIT_STATUS - print("{} raised: {}".format(self.func.__name__, e)) - EXIT_STATUS = 1 - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - -@exceptions_handler(Exception) -def print_information(binary): - print("== Information ==") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - - android_version = lief.OAT.android_version(binary.header.version) - code_name = lief.Android.code_name(android_version) - version = lief.Android.version_string(android_version) - - print("Version: {} - Android {} {}".format(binary.header.version, version, code_name)) - print("Number of dex files: {}".format(len(binary.oat_dex_files))) - print("Number of classes: {}".format(len(binary.classes))) - print("Number of methods: {}".format(len(binary.methods))) - print("") - - -@exceptions_handler(Exception) -def print_header(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - print("== Header ==") - header = binary.header - print(header) - -@exceptions_handler(Exception) -def print_dex_files(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - oat_dex_files = binary.oat_dex_files - - print("== Dex files ==") - for oat_dex in oat_dex_files: - print(oat_dex) - -@exceptions_handler(Exception) -def print_classes(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - classes = binary.classes - - print("== Classes ==") - for cls in classes: - print(cls) - -@exceptions_handler(Exception) -def print_methods(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - methods = binary.methods - - print("== Methods ==") - for m in methods: - print(m) - - -def main(): - parser = argparse.ArgumentParser(usage='%(prog)s [options] oat files') - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-H', '--header', - action='store_true', dest='show_header', - help='Display header') - - parser.add_argument('-c', '--classes', - action='store_true', dest='show_classes', - help='Display classes') - - parser.add_argument('-d', '--dex', - action='store_true', dest='show_dex', - help='Display Dex files') - - parser.add_argument('-m', '--methods', - action='store_true', dest='show_methods', - help='Display Methods') - - parser.add_argument('-x', '--extract', - action='store_true', dest='extract_dex', - help='Extract DEX files') - - parser.add_argument("binary", - metavar="", - help='Target OAT File') - - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - - lief.logging.set_level(args.main_verbosity) - - - binary = None - try: - binary = OAT.parse(args.binary) - except lief.exception as e: - print(e) - sys.exit(1) - - print_information(binary) - - if args.show_header or args.show_all: - print_header(binary) - - if (args.show_dex or args.show_all) and len(binary.oat_dex_files) > 0: - print_dex_files(binary) - - if args.show_classes and len(binary.classes) > 0: - print_classes(binary) - - if args.show_methods and len(binary.methods) > 0: - print_methods(binary) - - sys.exit(EXIT_STATUS) - - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/python/pe_authenticode.py b/vendor/lief/examples/python/pe_authenticode.py deleted file mode 100644 index 1e58cb5..0000000 --- a/vendor/lief/examples/python/pe_authenticode.py +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -import sys -import lief - -# Description: -# ----------- -# Print certificates included in a signed PE -# -# Example: -# python pe_authenticode.py driver.sys -# -# Version: 3 -# Serial Number: 61:04:ca:69:00:00:00:00:00:08 -# Signature Algorithm: SHA1_WITH_RSA_ENCRYPTION -# Valid from: 2007-6-5 22:3:21 -# Valid to: 2012-6-5 22:13:21 -# Issuer: C=US, ST=Washington, L=Redmond, O=Microsoft Corporation, CN=Microsoft Time-Stamp PCA -# Subject: C=US, ST=Washington, L=Redmond, O=Microsoft Corporation, OU=nCipher DSE ESN:A5B0-CDE0-DC94, CN=Microsoft Time-Stamp Service -# -# Version: 3 -# Serial Number: 61:01:c6:c1:00:00:00:00:00:07 -# Signature Algorithm: SHA1_WITH_RSA_ENCRYPTION -# Valid from: 2008-10-22 20:39:22 -# Valid to: 2010-1-22 20:49:22 -# Issuer: C=US, ST=Washington, L=Redmond, O=Microsoft Corporation, CN=Microsoft Windows Verification PCA -# Subject: C=US, ST=Washington, L=Redmond, O=Microsoft Corporation, OU=MOPR, CN=Microsoft Windows -# .... - -def print_crt(binary): - for crt in binary.signatures[0].certificates: - print(crt) - -if __name__ == '__main__': - if len(sys.argv) != 2: - print("Usage: {} ".format(sys.argv[0])) - sys.exit(1) - - binary = lief.parse(sys.argv[1]) - print_crt(binary) - - - diff --git a/vendor/lief/examples/python/pe_forwardinfo.py b/vendor/lief/examples/python/pe_forwardinfo.py deleted file mode 100644 index 8a85fd7..0000000 --- a/vendor/lief/examples/python/pe_forwardinfo.py +++ /dev/null @@ -1,9 +0,0 @@ -import lief -import sys - -pe = lief.parse(sys.argv[1]) -exports = pe.get_export() - -for e in filter(lambda e: e.is_forwarded, exports.entries): - fwd = e.forward_information - print(f"{e.name:<35} -> {fwd.library}.{fwd.function}") diff --git a/vendor/lief/examples/python/pe_from_scratch.py b/vendor/lief/examples/python/pe_from_scratch.py deleted file mode 100644 index 03fbdad..0000000 --- a/vendor/lief/examples/python/pe_from_scratch.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description: -# Create a PE which pop a MessageBox -# with the message "Hello World" - -from lief import PE - -title = "LIEF is awesome\0" -message = "Hello World\0" - -data = list(map(ord, title)) -data += list(map(ord, message)) -code = [ - 0x6a, 0x00, # push 0x00 uType - 0x68, 0x00, 0x20, 0x40, 0x00, # push VA(title) - 0x68, 0x10, 0x20, 0x40, 0x00, # push VA(message) - 0x6a, 0x00, # push 0 hWnd - 0xFF, 0x15, 0x54, 0x30, 0x40, 0x00, # call MessageBoxA - 0x6A, 0x00, # push 0 uExitCode - 0xFF, 0x15, 0x4C, 0x30, 0x40, 0x00 # call ExitProcess - ] - -binary32 = PE.Binary("pe_from_scratch", PE.PE_TYPE.PE32) - -section_text = PE.Section(".text") -section_text.content = code -section_text.virtual_address = 0x1000 - -section_data = PE.Section(".data") -section_data.content = data -section_data.virtual_address = 0x2000 - -section_text = binary32.add_section(section_text, PE.SECTION_TYPES.TEXT) -section_data = binary32.add_section(section_data, PE.SECTION_TYPES.DATA) - -print(section_text) -print(section_data) - -binary32.optional_header.addressof_entrypoint = section_text.virtual_address - -kernel32 = binary32.add_library("kernel32.dll") -kernel32.add_entry("ExitProcess") - -user32 = binary32.add_library("user32.dll") -user32.add_entry("MessageBoxA") - - -ExitProcess_addr = binary32.predict_function_rva("kernel32.dll", "ExitProcess") -MessageBoxA_addr = binary32.predict_function_rva("user32.dll", "MessageBoxA") -print("Address of 'ExitProcess': 0x{:06x} ".format(ExitProcess_addr)) -print("Address of 'MessageBoxA': 0x{:06x} ".format(MessageBoxA_addr)) - -builder = PE.Builder(binary32) -builder.build_imports(True) -builder.build() -builder.write("pe_from_scratch.exe") - diff --git a/vendor/lief/examples/python/pe_json.py b/vendor/lief/examples/python/pe_json.py deleted file mode 100644 index 2256137..0000000 --- a/vendor/lief/examples/python/pe_json.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a PE binary in the JSON format -# -# python pe_json.py C:\\windows\\explorer.exe -#   -# { -# "dynamic_entries": [ -# { -# "library": "libcap.so.2", -# "tag": "NEEDED", -# "value": 1 -# }, -# { -# "library": "libc.so.6", -# "tag": "NEEDED", -# "value": 74 -# }, -# ... - - -import argparse -import sys -import lief -import json - - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('binary', help='PE binary') - args = parser.parse_args() - - binary = lief.parse(args.binary) - json_data = json.loads(lief.to_json(binary)) - print(json.dumps(json_data, sort_keys=True, indent=4)) - -if __name__ == "__main__": - sys.exit(main()) - diff --git a/vendor/lief/examples/python/pe_reader.py b/vendor/lief/examples/python/pe_reader.py deleted file mode 100644 index 7be3e7c..0000000 --- a/vendor/lief/examples/python/pe_reader.py +++ /dev/null @@ -1,633 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- -# -# Description -# ----------- -# Print information about a PE file - -import lief -from lief import PE -from lief.PE import oid_to_string - -import argparse -import sys -import traceback - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - -@exceptions_handler(Exception) -def print_information(binary): - print("== Information ==\n") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - print(format_str.format("Name:", binary.name)) - print(format_hex.format("Virtual size:", binary.virtual_size)) - print(format_str.format("Imphash:", PE.get_imphash(binary))) - print(format_str.format("PIE:", str(binary.is_pie))) - print(format_str.format("NX:", str(binary.has_nx))) - -@exceptions_handler(Exception) -def print_header(binary): - dos_header = binary.dos_header - header = binary.header - optional_header = binary.optional_header - - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - print("== Dos Header ==") - print(format_str.format("Magic:", str((dos_header.magic)))) - print(format_dec.format("Used bytes in the last page:", dos_header.used_bytes_in_the_last_page)) - print(format_dec.format("File size in pages:", dos_header.file_size_in_pages)) - print(format_dec.format("Number of relocations:", dos_header.numberof_relocation)) - print(format_dec.format("Header size in paragraphs:", dos_header.header_size_in_paragraphs)) - print(format_dec.format("Minimum extra paragraphs:", dos_header.minimum_extra_paragraphs)) - print(format_dec.format("Maximum extra paragraphs", dos_header.maximum_extra_paragraphs)) - print(format_dec.format("Initial relative SS", dos_header.initial_relative_ss)) - print(format_hex.format("Initial SP:", dos_header.initial_sp)) - print(format_hex.format("Checksum:", dos_header.checksum)) - print(format_dec.format("Initial IP:", dos_header.initial_ip)) - print(format_dec.format("Initial CS:", dos_header.initial_relative_cs)) - print(format_hex.format("Address of relocation table:", dos_header.addressof_relocation_table)) - print(format_dec.format("Overlay number:", dos_header.overlay_number)) - print(format_dec.format("OEM ID:", dos_header.oem_id)) - print(format_dec.format("OEM information", dos_header.oem_info)) - print(format_hex.format("Address of optional header:", dos_header.addressof_new_exeheader)) - print("") - - print("== Header ==") - - char_str = " - ".join([str(chara).split(".")[-1] for chara in header.characteristics_list]) - - print(format_str.format("Signature:", "".join(map(chr, header.signature)))) - print(format_str.format("Machine:", str(header.machine))) - print(format_dec.format("Number of sections:", header.numberof_sections)) - print(format_dec.format("Time Date stamp:", header.time_date_stamps)) - print(format_dec.format("Pointer to symbols:", header.pointerto_symbol_table)) - print(format_dec.format("Number of symbols:", header.numberof_symbols)) - print(format_dec.format("Size of optional header:", header.sizeof_optional_header)) - print(format_str.format("Characteristics:", char_str)) - print("") - - - dll_char_str = " - ".join([str(chara).split(".")[-1] for chara in optional_header.dll_characteristics_lists]) - subsystem_str = str(optional_header.subsystem).split(".")[-1] - print("== Optional Header ==") - magic = "PE32" if optional_header.magic == PE.PE_TYPE.PE32 else "PE64" - print(format_str.format("Magic:", magic)) - print(format_dec.format("Major linker version:", optional_header.major_linker_version)) - print(format_dec.format("Minor linker version:", optional_header.minor_linker_version)) - print(format_dec.format("Size of code:", optional_header.sizeof_code)) - print(format_dec.format("Size of initialized data:", optional_header.sizeof_initialized_data)) - print(format_dec.format("Size of uninitialized data:", optional_header.sizeof_uninitialized_data)) - print(format_hex.format("Entry point:", optional_header.addressof_entrypoint)) - print(format_hex.format("Base of code:", optional_header.baseof_code)) - if magic == "PE32": - print(format_hex.format("Base of data", optional_header.baseof_data)) - print(format_hex.format("Image base:", optional_header.imagebase)) - print(format_hex.format("Section alignment:", optional_header.section_alignment)) - print(format_hex.format("File alignment:", optional_header.file_alignment)) - print(format_dec.format("Major operating system version:", optional_header.major_operating_system_version)) - print(format_dec.format("Minor operating system version:", optional_header.minor_operating_system_version)) - print(format_dec.format("Major image version:", optional_header.major_image_version)) - print(format_dec.format("Minor image version:", optional_header.minor_image_version)) - print(format_dec.format("Major subsystem version:", optional_header.major_subsystem_version)) - print(format_dec.format("Minor subsystem version:", optional_header.minor_subsystem_version)) - print(format_dec.format("WIN32 version value:", optional_header.win32_version_value)) - print(format_hex.format("Size of image:", optional_header.sizeof_image)) - print(format_hex.format("Size of headers:", optional_header.sizeof_headers)) - print(format_hex.format("Checksum:", optional_header.checksum)) - print(format_str.format("Subsystem:", subsystem_str)) - print(format_str.format("DLL Characteristics:", dll_char_str)) - print(format_hex.format("Size of stack reserve:", optional_header.sizeof_stack_reserve)) - print(format_hex.format("Size of stack commit:", optional_header.sizeof_stack_commit)) - print(format_hex.format("Size of heap reserve:", optional_header.sizeof_heap_reserve)) - print(format_hex.format("Size of heap commit:", optional_header.sizeof_heap_commit)) - print(format_dec.format("Loader flags:", optional_header.loader_flags)) - print(format_dec.format("Number of RVA and size:", optional_header.numberof_rva_and_size)) - print("") - -@exceptions_handler(Exception) -def print_data_directories(binary): - data_directories = binary.data_directories - - print("== Data Directories ==") - f_title = "|{:<24} | {:<10} | {:<10} | {:<8} |" - f_value = "|{:<24} | 0x{:<8x} | 0x{:<8x} | {:<8} |" - print(f_title.format("Type", "RVA", "Size", "Section")) - - for directory in data_directories: - section_name = directory.section.name if directory.has_section else "" - print(f_value.format(str(directory.type).split('.')[-1], directory.rva, directory.size, section_name)) - print("") - - -@exceptions_handler(Exception) -def print_sections(binary): - sections = binary.sections - - print("== Sections ==") - f_title = "|{:<10} | {:<16} | {:<16} | {:<18} | {:<16} | {:<9} | {:<9}" - f_value = "|{:<10} | 0x{:<14x} | 0x{:<14x} | 0x{:<16x} | 0x{:<14x} | {:<9.2f} | {:<9}" - print(f_title.format("Name", "Offset", "Size", "Virtual Address", "Virtual size", "Entropy", "Flags")) - - for section in sections: - flags = "" - for flag in section.characteristics_lists: - flags += str(flag).split(".")[-1] + " " - print(f_value.format(section.name, section.offset, section.size, section.virtual_address, section.virtual_size, section.entropy, flags)) - print("") - - -@exceptions_handler(Exception) -def print_symbols(binary): - symbols = binary.symbols - if len(symbols) > 0: - print("== Symbols ==") - f_title = "|{:<20} | {:<10} | {:<8} | {:<8} | {:<8} | {:<13} |" - f_value = u"|{:<20} | 0x{:<8x} | {:<14} | {:<10} | {:<12} | {:<13} |" - - print(f_title.format("Name", "Value", "Section number", "Basic type", "Complex type", "Storage class")) - for symbol in symbols: - section_nb_str = "" - if symbol.section_number <= 0: - section_nb_str = str(PE.SYMBOL_SECTION_NUMBER(symbol.section_number)).split(".")[-1] - else: - try: - section_nb_str = symbol.section.name - except Exception: - section_nb_str = "section<{:d}>".format(symbol.section_number) - - - print(f_value.format( - symbol.name[:20], - symbol.value, - section_nb_str, - str(symbol.base_type).split(".")[-1], - str(symbol.complex_type).split(".")[-1], - str(symbol.storage_class).split(".")[-1])) - -@exceptions_handler(Exception) -def print_imports(binary, resolve=False): - print("== Imports ==") - imports = binary.imports - - for import_ in imports: - if resolve: - import_ = lief.PE.resolve_ordinals(import_) - - print(import_.name) - entries = import_.entries - f_value = " {:<33} 0x{:<14x} 0x{:<14x} 0x{:<16x}" - for entry in entries: - print(f_value.format(entry.name, entry.data, entry.iat_value, entry.hint)) - print("") - -@exceptions_handler(Exception) -def print_tls(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - - print("== TLS ==") - tls = binary.tls - callbacks = tls.callbacks - print(format_hex.format("Address of callbacks:", tls.addressof_callbacks)) - if len(callbacks) > 0: - print("Callbacks:") - for callback in callbacks: - print(" " + hex(callback)) - - print(format_hex.format("Address of index:", tls.addressof_index)) - print(format_hex.format("Size of zero fill:", tls.sizeof_zero_fill)) - print("{:<33} 0x{:<10x} 0x{:<10x}".format("Address of raw data:", - tls.addressof_raw_data[0], tls.addressof_raw_data[1])) - print(format_hex.format("Size of raw data:", len(tls.data_template))) - print(format_hex.format("Characteristics:", tls.characteristics)) - print(format_str.format("Section:", tls.section.name)) - print(format_str.format("Data directory:", str(tls.directory.type))) - print("") - -@exceptions_handler(Exception) -def print_relocations(binary): - relocations = binary.relocations - print("== Relocations ==") - for relocation in relocations: - entries = relocation.entries - print(hex(relocation.virtual_address)) - for entry in entries: - print(" 0x{:<8x} {:<8}".format(entry.position, str(entry.type).split(".")[-1])) - print("") - -@exceptions_handler(Exception) -def print_export(binary): - print("== Exports ==") - exports = binary.get_export() - entries = exports.entries - f_value = "{:<20} 0x{:<10x} 0x{:<10x} 0x{:<6x} 0x{:<6x} 0x{:<10x}" - print(f_value.format(exports.name, exports.export_flags, exports.timestamp, exports.major_version, exports.minor_version, exports.ordinal_base)) - entries = sorted(entries, key=lambda e : e.ordinal) - for entry in entries: - extern = "[EXTERN]" if entry.is_extern else "" - print(" {:<20} {:d} 0x{:<10x} {:<13}".format(entry.name[:20], entry.ordinal, entry.address, extern)) - print("") - - -@exceptions_handler(Exception) -def print_debug(binary): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - debugs = binary.debug - print("== Debug ({}) ==".format(len(debugs))) - for debug in debugs: - print(format_hex.format("Characteristics:", debug.characteristics)) - print(format_hex.format("Timestamp:", debug.timestamp)) - print(format_dec.format("Major version:", debug.major_version)) - print(format_dec.format("Minor version:", debug.minor_version)) - print(format_str.format("type:", str(debug.type).split(".")[-1])) - print(format_hex.format("Size of data:", debug.sizeof_data)) - print(format_hex.format("Address of raw data:", debug.addressof_rawdata)) - print(format_hex.format("Pointer to raw data:", debug.pointerto_rawdata)) - - if debug.has_code_view: - code_view = debug.code_view - cv_signature = code_view.cv_signature - - if cv_signature in (lief.PE.CODE_VIEW_SIGNATURES.PDB_70, lief.PE.CODE_VIEW_SIGNATURES.PDB_70): - sig_str = " ".join(map(lambda e : "{:02x}".format(e), code_view.signature)) - print(format_str.format("Code View Signature:", str(cv_signature).split(".")[-1])) - print(format_str.format("Signature:", sig_str)) - print(format_dec.format("Age:", code_view.age)) - print(format_str.format("Filename:", code_view.filename)) - - if debug.has_pogo: - pogo = debug.pogo - sig_str = str(pogo.signature).split(".")[-1] - print(format_str.format("Signature:", sig_str)) - print("Entries:") - for entry in pogo.entries: - print(" {:<20} 0x{:x} ({:d})".format(entry.name, entry.start_rva, entry.size)) - - print("\n") - - -@exceptions_handler(Exception) -def print_signature(binary): - format_str = "{:<33} {:<30}" - format_dec = "{:<33} {:<30d}" - for signature in binary.signatures: - print(signature) - -@exceptions_handler(Exception) -def print_rich_header(binary): - print("== Rich Header ==") - header = binary.rich_header - print("Key: 0x{:08x}".format(header.key)) - - for entry in header.entries: - print(" - ID: {:04x} Build ID: {:04x} Count: {:d}".format(entry.id, entry.build_id, entry.count)) - print("") - - -@exceptions_handler(Exception) -def print_resources(binary): - print("== Resources ==") - manager = binary.resources_manager - - print(manager) - - print("") - -@exceptions_handler(Exception) -def print_load_configuration(binary): - format_str = "{:<45} {:<30}" - format_hex = "{:<45} 0x{:<28x}" - format_dec = "{:<45} {:<30d}" - - print("== Load Configuration ==") - config = binary.load_configuration - - - print(format_str.format("Version:", str(config.version).split(".")[-1])) - print(format_dec.format("Characteristics:", config.characteristics)) - print(format_dec.format("Timedatestamp:", config.timedatestamp)) - print(format_dec.format("Major version:", config.major_version)) - print(format_dec.format("Minor version:", config.minor_version)) - print(format_hex.format("Global flags clear:", config.global_flags_clear)) - print(format_hex.format("Global flags set:", config.global_flags_set)) - print(format_dec.format("Critical section default timeout:", config.critical_section_default_timeout)) - print(format_hex.format("Decommit free block threshold:", config.decommit_free_block_threshold)) - print(format_hex.format("Decommit total free threshold:", config.decommit_total_free_threshold)) - print(format_hex.format("Lock prefix table:", config.lock_prefix_table)) - print(format_hex.format("Maximum allocation size:", config.maximum_allocation_size)) - print(format_hex.format("Virtual memory threshold:", config.virtual_memory_threshold)) - print(format_hex.format("Process affinity mask:", config.process_affinity_mask)) - print(format_hex.format("Process heap flags:", config.process_heap_flags)) - print(format_hex.format("CSD Version:", config.csd_version)) - print(format_hex.format("Reserved 1:", config.reserved1)) - print(format_hex.format("Edit list:", config.editlist)) - print(format_hex.format("Security cookie:", config.security_cookie)) - - if isinstance(config, lief.PE.LoadConfigurationV0): - print(format_hex.format("SE handler table:", config.se_handler_table)) - print(format_dec.format("SE handler count:", config.se_handler_count)) - - if isinstance(config, lief.PE.LoadConfigurationV1): - flags_str = " - ".join(map(lambda e : str(e).split(".")[-1], config.guard_cf_flags_list)) - print(format_hex.format("GCF check function pointer:", config.guard_cf_check_function_pointer)) - print(format_hex.format("GCF dispatch function pointer:", config.guard_cf_dispatch_function_pointer)) - print(format_hex.format("GCF function table :", config.guard_cf_function_table)) - print(format_dec.format("GCF Function count :", config.guard_cf_function_count)) - print("{:<45} {} (0x{:x})".format("Guard flags:", flags_str, int(config.guard_flags))) - - if isinstance(config, lief.PE.LoadConfigurationV2): - code_integrity = config.code_integrity - print("Code Integrity:") - print(format_dec.format(" " * 3 + "Flags:", code_integrity.flags)) - print(format_dec.format(" " * 3 + "Catalog:", code_integrity.catalog)) - print(format_hex.format(" " * 3 + "Catalog offset:", code_integrity.catalog_offset)) - print(format_dec.format(" " * 3 + "Reserved:", code_integrity.reserved)) - - if isinstance(config, lief.PE.LoadConfigurationV3): - print(format_hex.format("Guard address taken iat entry table:", config.guard_address_taken_iat_entry_table)) - print(format_hex.format("Guard address taken iat entry count:", config.guard_address_taken_iat_entry_count)) - print(format_hex.format("Guard long jump target table:", config.guard_long_jump_target_table)) - print(format_hex.format("Guard long jump target count:", config.guard_long_jump_target_count)) - - - if isinstance(config, lief.PE.LoadConfigurationV4): - print(format_hex.format("Dynamic value relocation table:", config.dynamic_value_reloc_table)) - print(format_hex.format("Hybrid metadata pointer:", config.hybrid_metadata_pointer)) - - - if isinstance(config, lief.PE.LoadConfigurationV5): - print(format_hex.format("GRF failure routine:", config.guard_rf_failure_routine)) - print(format_hex.format("GRF failure routine function pointer:", config.guard_rf_failure_routine_function_pointer)) - print(format_hex.format("Dynamic value reloctable offset:", config.dynamic_value_reloctable_offset)) - print(format_hex.format("Dynamic value reloctable section:", config.dynamic_value_reloctable_section)) - - - if isinstance(config, lief.PE.LoadConfigurationV6): - print(format_hex.format("GRF verify stackpointer function pointer:", config.guard_rf_verify_stackpointer_function_pointer)) - print(format_hex.format("Hotpatch table offset:", config.hotpatch_table_offset)) - - - if isinstance(config, lief.PE.LoadConfigurationV7): - print(format_hex.format("Reserved 3:", config.reserved3)) - - print("") - - -@exceptions_handler(Exception) -def print_ctor(binary): - print("== Constructors ==\n") - - print("Functions: ({:d})".format(len(binary.ctor_functions))) - for idx, f in enumerate(binary.ctor_functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - - -@exceptions_handler(Exception) -def print_exception_functions(binary): - print("== Exception functions ==\n") - - print("Functions: ({:d})".format(len(binary.exception_functions))) - for idx, f in enumerate(binary.exception_functions): - print(" [{:d}] {}: 0x{:x}".format(idx, f.name, f.address)) - - -@exceptions_handler(Exception) -def print_functions(binary): - print("== Functions ==\n") - - print("Functions: ({:d})".format(len(binary.functions))) - for idx, f in enumerate(binary.functions): - print(" [{:d}] {}: 0x{:x} ({:d} bytes)".format(idx, f.name, f.address, f.size)) - - -@exceptions_handler(Exception) -def print_delay_imports(binary): - delay_imports = binary.delay_imports - if len(delay_imports) == 0: - return - print("== Delay Imports ==\n") - for imp in delay_imports: - print(imp.name) - print(" Attribute: {}".format(imp.attribute)) - print(" Handle: 0x{:x}".format(imp.handle)) - print(" IAT: 0x{:x}".format(imp.iat)) - print(" Names Table: 0x{:x}".format(imp.names_table)) - print(" Bound IAT: 0x{:x}".format(imp.biat)) - print(" Unload IAT: 0x{:x}".format(imp.uiat)) - print(" Timestamp: 0x{:x}".format(imp.timestamp)) - for entry in imp.entries: - print(" {:<25} 0x{:08x}: 0x{:010x} - 0x{:x}".format(entry.name, entry.value, entry.iat_value, entry.hint)) - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument("pe_file") - - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all informations') - - parser.add_argument('-d', '--data-directories', - action='store_true', dest='show_data_directories', - help='Display data directories') - - parser.add_argument('--dbg', - action='store_true', dest='show_debug', - help='Display debug directory') - - parser.add_argument('-g', '--signature', - action='store_true', dest='show_signature', - help="Display the binary's signature if any") - - parser.add_argument('-H', '--header', - action='store_true', dest='show_headers', - help='Display headers') - - parser.add_argument('-i', '--import', - action='store_true', dest='show_imports', - help='Display imported functions and libraries') - - parser.add_argument('--resolve-ordinals', - action='store_true', dest='resolve_ordinals', - help="When used with --import, it attempts to resolve names of ordinal imports") - - parser.add_argument('-r', '--relocs', - action='store_true', dest='show_relocs', - help='Display the relocations (if present)') - - parser.add_argument('-R', '--rich-header', - action='store_true', dest='show_richheader', - help='Display the Rich Header') - - parser.add_argument('--resources', '--rsrc', - action='store_true', dest='show_resources', - help='Display the resources (if present)') - - parser.add_argument('-S', '--section-headers', '--sections', - action='store_true', dest='show_section_header', - help="Display the sections' headers") - - parser.add_argument('-s', '--symbols', '--syms', - action='store_true', dest='show_symbols', - help='Display symbols') - - parser.add_argument('-t', '--tls', - action='store_true', dest='show_tls', - help='Display TLS informations') - - parser.add_argument('-x', '--export', - action='store_true', dest='show_export', - help='Display exported functions/libraries') - - parser.add_argument('--load-config', - action='store_true', dest='show_loadconfig', - help='Display load configuration') - - parser.add_argument('--ctor', - action='store_true', dest='show_ctor', - help='Constructor functions') - - parser.add_argument('-f', '--functions', - action='store_true', dest='show_functions', - help='Display all functions found in the binary') - - parser.add_argument('--exception-functions', - action='store_true', dest='show_pfunctions', - help='Display functions found in the exception directory') - - parser.add_argument('--delay-imports', - action='store_true', dest='show_delay_imports', - help='Display delay imports') - - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - lief.logging.set_level(args.main_verbosity) - - binary = None - try: - binary = PE.parse(args.pe_file) - except lief.exception as e: - print(e) - sys.exit(1) - - if binary is None: - sys.exit(1) - - print_information(binary) - - if args.show_data_directories or args.show_all: - print_data_directories(binary) - - if args.show_headers or args.show_all: - print_header(binary) - - if (args.show_imports or args.show_all) and binary.has_imports: - print_imports(binary, resolve=args.resolve_ordinals) - - if (args.show_relocs or args.show_all) and binary.has_relocations: - print_relocations(binary) - - if args.show_section_header or args.show_all: - print_sections(binary) - - if args.show_symbols or args.show_all: - print_symbols(binary) - - if (args.show_tls or args.show_all) and binary.has_tls: - print_tls(binary) - - if (args.show_export or args.show_all) and binary.has_exports: - print_export(binary) - - if (args.show_debug or args.show_all) and binary.has_debug: - print_debug(binary) - - if (args.show_signature or args.show_all) and binary.has_signatures: - print_signature(binary) - - if (args.show_richheader or args.show_all) and binary.has_rich_header: - print_rich_header(binary) - - if (args.show_resources or args.show_all) and binary.has_resources: - print_resources(binary) - - if (args.show_loadconfig or args.show_all) and binary.has_configuration: - print_load_configuration(binary) - - if args.show_ctor or args.show_all: - print_ctor(binary) - - if args.show_functions or args.show_all: - print_functions(binary) - - if args.show_pfunctions or args.show_all: - print_exception_functions(binary) - - if args.show_delay_imports or args.show_all: - print_delay_imports(binary) - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/python/pe_resources_manager.py b/vendor/lief/examples/python/pe_resources_manager.py deleted file mode 100644 index d127717..0000000 --- a/vendor/lief/examples/python/pe_resources_manager.py +++ /dev/null @@ -1,8 +0,0 @@ -#!/usr/bin/env python -import sys -import lief - -b = lief.parse(sys.argv[1]) -manager = b.resources_manager -print(manager) -print(manager.manifest) diff --git a/vendor/lief/examples/python/vdex_json.py b/vendor/lief/examples/python/vdex_json.py deleted file mode 100644 index 844cfb3..0000000 --- a/vendor/lief/examples/python/vdex_json.py +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about a DEX file in the JSON format - -import argparse -import sys -import lief -import json - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument('file', help='VDEX file') - args = parser.parse_args() - - if not lief.VDEX.is_vdex(args.file): - print("{} is not a VDEX file".format(args.file)) - return 1 - dexfile = lief.VDEX.parse(args.file) - json_data = json.loads(lief.to_json(dexfile)) - print(json.dumps(json_data, sort_keys = True, indent = 4)) - -if __name__ == "__main__": - sys.exit(main()) - diff --git a/vendor/lief/examples/python/vdex_reader.py b/vendor/lief/examples/python/vdex_reader.py deleted file mode 100644 index 83a7c6a..0000000 --- a/vendor/lief/examples/python/vdex_reader.py +++ /dev/null @@ -1,139 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- - -# Description -# ----------- -# Print information about Android VDEX files -import sys -import os -import argparse -import traceback -import lief -from lief import VDEX, DEX - -EXIT_STATUS = 0 -terminal_rows, terminal_columns = 100, 100 -try: - terminal_rows, terminal_columns = os.popen('stty size', 'r').read().split() -except ValueError: - pass - - -class exceptions_handler(object): - func = None - - def __init__(self, exceptions, on_except_callback=None): - self.exceptions = exceptions - self.on_except_callback = on_except_callback - - def __call__(self, *args, **kwargs): - if self.func is None: - self.func = args[0] - return self - try: - return self.func(*args, **kwargs) - except self.exceptions as e: - global EXIT_STATUS - print("{} raised: {}".format(self.func.__name__, e)) - EXIT_STATUS = 1 - if self.on_except_callback is not None: - self.on_except_callback(e) - else: - print("-" * 60) - print("Exception in {}: {}".format(self.func.__name__, e)) - exc_type, exc_value, exc_traceback = sys.exc_info() - traceback.print_tb(exc_traceback) - print("-" * 60) - -@exceptions_handler(Exception) -def print_information(vdexfile): - print("== Information ==") - format_str = "{:<30} {:<30}" - format_hex = "{:<30} 0x{:<28x}" - format_dec = "{:<30} {:<30d}" - version = vdexfile.header.version - - print("VDEX File version: {}".format(version)) - print("") - - -@exceptions_handler(Exception) -def print_header(vdexfile): - format_str = "{:<33} {:<30}" - format_hex = "{:<33} 0x{:<28x}" - format_dec = "{:<33} {:<30d}" - - print("== Header ==") - header = vdexfile.header - print(header) - -def main(): - parser = argparse.ArgumentParser(usage='%(prog)s [options] VDEX files') - parser.add_argument('-a', '--all', - action='store_true', dest='show_all', - help='Show all information') - - parser.add_argument('-H', '--header', - action='store_true', dest='show_header', - help='Display header') - - parser.add_argument("file", - metavar="", - help='Target DEX File') - # Logging setup - logger_group = parser.add_argument_group('Logger') - verbosity = logger_group.add_mutually_exclusive_group() - - verbosity.add_argument('--debug', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.DEBUG) - - verbosity.add_argument('--trace', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.TRACE) - - verbosity.add_argument('--info', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.INFO) - - verbosity.add_argument('--warn', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.WARNING) - - verbosity.add_argument('--err', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.ERROR) - - verbosity.add_argument('--critical', - dest='main_verbosity', - action='store_const', - const=lief.logging.LOGGING_LEVEL.CRITICAL) - - parser.set_defaults(main_verbosity=lief.logging.LOGGING_LEVEL.WARNING) - - args = parser.parse_args() - - lief.logging.set_level(args.main_verbosity) - - vdexfile = None - try: - vdexfile = DEX.parse(args.file) - except lief.exception as e: - print(e) - sys.exit(1) - - print_information(vdexfile) - - if args.show_header or args.show_all: - print_header(vdexfile) - - sys.exit(EXIT_STATUS) - - -if __name__ == "__main__": - main() diff --git a/vendor/lief/examples/rust b/vendor/lief/examples/rust new file mode 120000 index 0000000..7c914ba --- /dev/null +++ b/vendor/lief/examples/rust @@ -0,0 +1 @@ +../api/rust/examples/src/bin \ No newline at end of file diff --git a/vendor/lief/fuzzing/CMakeLists.txt b/vendor/lief/fuzzing/CMakeLists.txt index d034391..3552eef 100644 --- a/vendor/lief/fuzzing/CMakeLists.txt +++ b/vendor/lief/fuzzing/CMakeLists.txt @@ -8,12 +8,12 @@ set(LIEF_FUZZER_SRC foreach(fuzzer ${LIEF_FUZZER_SRC}) string(REGEX REPLACE ".cpp\$" "" output "${fuzzer}") - add_executable("${output}" "${fuzzer}") + add_executable("${output}" "${fuzzer}") set_target_properties( "${output}" PROPERTIES POSITION_INDEPENDENT_CODE ON - CXX_STANDARD 11 + CXX_STANDARD 17 CXX_STANDARD_REQUIRED ON) set_property(TARGET "${output}" @@ -22,7 +22,7 @@ foreach(fuzzer ${LIEF_FUZZER_SRC}) # Don't use default include dir #set_property(TARGET "${output}" "${output}_shared" PROPERTY INCLUDE_DIRECTORIES "") - target_link_libraries("${output}" PUBLIC LIB_LIEF asan) + target_link_libraries("${output}" PUBLIC LIB_LIEF) endforeach() diff --git a/vendor/lief/fuzzing/elf_fuzzer.cpp b/vendor/lief/fuzzing/elf_fuzzer.cpp index c6e9d67..5d8a6e5 100644 --- a/vendor/lief/fuzzing/elf_fuzzer.cpp +++ b/vendor/lief/fuzzing/elf_fuzzer.cpp @@ -1,11 +1,11 @@ +#include #include -#include #include #include -extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { - std::vector raw = {data, data + size}; - if (auto b = LIEF::ELF::Parser::parse(raw)) { +extern "C" int LLVMFuzzerTestOneInput(const uint8_t* data, size_t size) { + auto stream = std::make_unique(data, size); + if (auto b = LIEF::ELF::Parser::parse(std::move(stream))) { std::stringstream oss; oss << *b; } diff --git a/vendor/lief/fuzzing/macho_fuzzer.cpp b/vendor/lief/fuzzing/macho_fuzzer.cpp index 515088e..46f5960 100644 --- a/vendor/lief/fuzzing/macho_fuzzer.cpp +++ b/vendor/lief/fuzzing/macho_fuzzer.cpp @@ -1,9 +1,9 @@ #include -#include #include #include +#include -extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { +extern "C" int LLVMFuzzerTestOneInput(const uint8_t* data, size_t size) { std::vector raw = {data, data + size}; if (auto b = LIEF::MachO::Parser::parse(raw)) { diff --git a/vendor/lief/fuzzing/pe_fuzzer.cpp b/vendor/lief/fuzzing/pe_fuzzer.cpp index e5e15c9..4a2a943 100644 --- a/vendor/lief/fuzzing/pe_fuzzer.cpp +++ b/vendor/lief/fuzzing/pe_fuzzer.cpp @@ -1,12 +1,14 @@ +#include #include -#include #include #include -extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { - std::vector raw = {data, data + size}; +extern "C" int LLVMFuzzerTestOneInput(const uint8_t* data, size_t size) { + auto stream = std::make_unique(data, size); - if (auto b = LIEF::PE::Parser::parse(raw)) { + if (auto b = LIEF::PE::Parser::parse(std::move(stream), + LIEF::PE::ParserConfig::all())) + { std::stringstream oss; oss << *b; } diff --git a/vendor/lief/fuzzing/pkcs7_signature.cpp b/vendor/lief/fuzzing/pkcs7_signature.cpp index 6fefcb5..954cc03 100644 --- a/vendor/lief/fuzzing/pkcs7_signature.cpp +++ b/vendor/lief/fuzzing/pkcs7_signature.cpp @@ -1,12 +1,11 @@ #include "LIEF/PE/signature/SignatureParser.hpp" #include "LIEF/logging.hpp" -__attribute__((constructor)) void foo(){ +__attribute__((constructor)) void foo() { LIEF::logging::disable(); } -LIEF_API extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { +LIEF_API extern "C" int LLVMFuzzerTestOneInput(const uint8_t* data, size_t size) { LIEF::PE::SignatureParser::parse(std::vector{data, data + size}); - return 0; // Non-zero return values are reserved for future use. + return 0; // Non-zero return values are reserved for future use. } - diff --git a/vendor/lief/fuzzing/pme_fuzzer.cpp b/vendor/lief/fuzzing/pme_fuzzer.cpp index c08c79a..7005367 100644 --- a/vendor/lief/fuzzing/pme_fuzzer.cpp +++ b/vendor/lief/fuzzing/pme_fuzzer.cpp @@ -1,9 +1,9 @@ #include -#include #include #include +#include -extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { +extern "C" int LLVMFuzzerTestOneInput(const uint8_t* data, size_t size) { std::vector raw = {data, data + size}; if (auto b = LIEF::Parser::parse(raw)) { std::stringstream oss; diff --git a/vendor/lief/include/LIEF/ART.hpp b/vendor/lief/include/LIEF/ART.hpp index 797f880..e53bc75 100644 --- a/vendor/lief/include/LIEF/ART.hpp +++ b/vendor/lief/include/LIEF/ART.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,16 +13,18 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_H_ -#define LIEF_ART_H_ +#ifndef LIEF_ART_H +#define LIEF_ART_H +// IWYU pragma: begin_exports #include "LIEF/config.h" #if defined(LIEF_ART_SUPPORT) -#include "LIEF/ART/Parser.hpp" -#include "LIEF/ART/utils.hpp" -#include "LIEF/ART/File.hpp" -#include "LIEF/ART/EnumToString.hpp" + #include "LIEF/ART/EnumToString.hpp" + #include "LIEF/ART/File.hpp" + #include "LIEF/ART/Parser.hpp" + #include "LIEF/ART/utils.hpp" #endif +// IWYU pragma: end_exports #endif diff --git a/vendor/lief/include/LIEF/ART/EnumToString.hpp b/vendor/lief/include/LIEF/ART/EnumToString.hpp index 016ad86..1bd7888 100644 --- a/vendor/lief/include/LIEF/ART/EnumToString.hpp +++ b/vendor/lief/include/LIEF/ART/EnumToString.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,13 +13,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_ENUM_TO_STRING_H_ -#define LIEF_ART_ENUM_TO_STRING_H_ -#include "LIEF/visibility.h" +#ifndef LIEF_ART_ENUM_TO_STRING_H +#define LIEF_ART_ENUM_TO_STRING_H #include "LIEF/ART/enums.hpp" +#include "LIEF/visibility.h" + -namespace LIEF { -namespace ART { +namespace LIEF::ART { LIEF_API const char* to_string(STORAGE_MODES e); @@ -33,8 +33,7 @@ LIEF_API const char* to_string(ART_44::IMAGE_METHODS e); LIEF_API const char* to_string(ART_17::IMAGE_ROOTS e); LIEF_API const char* to_string(ART_44::IMAGE_ROOTS e); -} // namespace ART -} // namespace LIEF +} -#endif +#endif diff --git a/vendor/lief/include/LIEF/ART/File.hpp b/vendor/lief/include/LIEF/ART/File.hpp index bd21e79..48367ee 100644 --- a/vendor/lief/include/LIEF/ART/File.hpp +++ b/vendor/lief/include/LIEF/ART/File.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,17 +13,17 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_FILE_H_ -#define LIEF_ART_FILE_H_ -#include +#ifndef LIEF_ART_FILE_H +#define LIEF_ART_FILE_H +#include #include "LIEF/ART/Header.hpp" -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" + -namespace LIEF { -namespace ART { +namespace LIEF::ART { class Parser; class LIEF_API File : public Object { @@ -31,15 +31,13 @@ class LIEF_API File : public Object { public: File& operator=(const File& copy) = delete; - File(const File& copy) = delete; + File(const File& copy) = delete; - const Header& header() const; - Header& header(); + const Header& header() const LIEF_LIFETIMEBOUND; + Header& header() LIEF_LIFETIMEBOUND; void accept(Visitor& visitor) const override; - bool operator==(const File& rhs) const; - bool operator!=(const File& rhs) const; ~File() override; @@ -52,6 +50,6 @@ class LIEF_API File : public Object { }; } -} + #endif diff --git a/vendor/lief/include/LIEF/ART/Header.hpp b/vendor/lief/include/LIEF/ART/Header.hpp index f434ed2..078d237 100644 --- a/vendor/lief/include/LIEF/ART/Header.hpp +++ b/vendor/lief/include/LIEF/ART/Header.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,17 +13,21 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_HEADER_H_ -#define LIEF_ART_HEADER_H_ +#ifndef LIEF_ART_HEADER_H +#define LIEF_ART_HEADER_H + +#include +#include +#include -#include "LIEF/ART/types.hpp" #include "LIEF/ART/enums.hpp" +#include "LIEF/ART/types.hpp" -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" + -namespace LIEF { -namespace ART { +namespace LIEF::ART { class Parser; class LIEF_API Header : public Object { @@ -76,54 +80,52 @@ class LIEF_API Header : public Object { void accept(Visitor& visitor) const override; - bool operator==(const Header& rhs) const; - bool operator!=(const Header& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Header& hdr); - virtual ~Header(); + ~Header() override; private: - magic_t magic_; - art_version_t version_; + magic_t magic_{}; + art_version_t version_ = 0; - uint32_t image_begin_; - uint32_t image_size_; + uint32_t image_begin_ = 0; + uint32_t image_size_ = 0; - uint32_t oat_checksum_; + uint32_t oat_checksum_ = 0; - uint32_t oat_file_begin_; - uint32_t oat_file_end_; + uint32_t oat_file_begin_ = 0; + uint32_t oat_file_end_ = 0; - uint32_t oat_data_begin_; - uint32_t oat_data_end_; + uint32_t oat_data_begin_ = 0; + uint32_t oat_data_end_ = 0; - int32_t patch_delta_; - uint32_t image_roots_; + int32_t patch_delta_ = 0; + uint32_t image_roots_ = 0; - uint32_t pointer_size_; + uint32_t pointer_size_ = 0; - bool compile_pic_; + bool compile_pic_ = false; - uint32_t nb_sections_; - uint32_t nb_methods_; + uint32_t nb_sections_ = 0; + uint32_t nb_methods_ = 0; - bool is_pic_; + bool is_pic_ = false; // From ART 29 // =========== - uint32_t boot_image_begin_; - uint32_t boot_image_size_; + uint32_t boot_image_begin_ = 0; + uint32_t boot_image_size_ = 0; - uint32_t boot_oat_begin_; - uint32_t boot_oat_size_; + uint32_t boot_oat_begin_ = 0; + uint32_t boot_oat_size_ = 0; - STORAGE_MODES storage_mode_; + STORAGE_MODES storage_mode_ = STORAGE_MODES::STORAGE_UNCOMPRESSED; - uint32_t data_size_; + uint32_t data_size_ = 0; }; } // Namespace ART -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/ART/Parser.hpp b/vendor/lief/include/LIEF/ART/Parser.hpp index cf6ba4b..a09dc07 100644 --- a/vendor/lief/include/LIEF/ART/Parser.hpp +++ b/vendor/lief/include/LIEF/ART/Parser.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,39 +13,47 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_PARSER_H_ -#define LIEF_ART_PARSER_H_ +#ifndef LIEF_ART_PARSER_H +#define LIEF_ART_PARSER_H +#include #include #include #include "LIEF/ART/types.hpp" +#include "LIEF/path.hpp" #include "LIEF/visibility.h" -struct Profiler; - namespace LIEF { class BinaryStream; namespace ART { class File; -//! @brief Class which parses an ART file and transform into a ART::File object +/// Class which parses an ART file and transforms it into an ART::File object class LIEF_API Parser { public: - friend struct ::Profiler; - static std::unique_ptr parse(const std::string& file); - static std::unique_ptr parse(std::vector data, const std::string& name = ""); + static std::unique_ptr parse(std::string_view file); + + /// Same as parse(std::string_view) but the file is given as a + /// `std::filesystem::path` + template = 0> + static std::unique_ptr parse(const PathT& file) { + return parse(file.string()); + } + + static std::unique_ptr parse(std::vector data, + std::string_view name = ""); Parser& operator=(const Parser& copy) = delete; - Parser(const Parser& copy) = delete; + Parser(const Parser& copy) = delete; private: Parser(); - Parser(const std::string& file); + Parser(std::string_view file); Parser(std::vector data); - virtual ~Parser(); + ~Parser(); - void init(const std::string& name, art_version_t version); + void init(std::string_view name, art_version_t version); template void parse_file(); @@ -97,13 +105,13 @@ class LIEF_API Parser { //// Parse a **Single** java.lang.DexCache object - //template - //void parse_class_roots(size_t object_offset); + // template + // void parse_class_roots(size_t object_offset); std::unique_ptr file_; std::unique_ptr stream_; uint32_t imagebase_ = 0; }; -} // namespace ART -} // namespace LIEF +} +} #endif diff --git a/vendor/lief/include/LIEF/ART/enums.hpp b/vendor/lief/include/LIEF/ART/enums.hpp index 2b8045f..08365d2 100644 --- a/vendor/lief/include/LIEF/ART/enums.hpp +++ b/vendor/lief/include/LIEF/ART/enums.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,40 +13,41 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_ENUMS_H_ -#define LIEF_ART_ENUMS_H_ +#ifndef LIEF_ART_ENUMS_H +#define LIEF_ART_ENUMS_H +#include -namespace LIEF { -namespace ART { -enum STORAGE_MODES { +namespace LIEF::ART { + +enum STORAGE_MODES : uint32_t { STORAGE_UNCOMPRESSED = 0, - STORAGE_LZ4 = 1, - STORAGE_LZ4HC = 2, + STORAGE_LZ4 = 1, + STORAGE_LZ4HC = 2, }; namespace ART_17 { enum IMAGE_METHODS { - RESOLUTION_METHOD = 0, - IMT_CONFLICT_METHOD = 1, - IMT_UNIMPLEMENTED_METHOD = 2, - CALLEE_SAVE_METHOD = 3, - REFS_ONLY_SAVE_METHOD = 4, + RESOLUTION_METHOD = 0, + IMT_CONFLICT_METHOD = 1, + IMT_UNIMPLEMENTED_METHOD = 2, + CALLEE_SAVE_METHOD = 3, + REFS_ONLY_SAVE_METHOD = 4, REFS_AND_ARGS_SAVE_METHOD = 5, }; enum IMAGE_SECTIONS { - SECTION_OBJECTS = 0, - SECTION_ART_FIELDS = 1, - SECTION_ART_METHODS = 2, - SECTION_INTERNED_STRINGS = 3, - SECTION_IMAGE_BITMAP = 4, + SECTION_OBJECTS = 0, + SECTION_ART_FIELDS = 1, + SECTION_ART_METHODS = 2, + SECTION_INTERNED_STRINGS = 3, + SECTION_IMAGE_BITMAP = 4, }; enum IMAGE_ROOTS { - DEX_CACHES = 0, - CLASS_ROOTS = 1, + DEX_CACHES = 0, + CLASS_ROOTS = 1, }; @@ -59,19 +60,18 @@ using ART_17::IMAGE_METHODS; using ART_17::IMAGE_ROOTS; enum IMAGE_SECTIONS { - SECTION_OBJECTS = 0, - SECTION_ART_FIELDS = 1, - SECTION_ART_METHODS = 2, - SECTION_RUNTIME_METHODS = 3, // New in ART 29 - SECTION_IMT_CONFLICT_TABLES = 4, // New in ART 29 - SECTION_DEX_CACHE_ARRAYS = 5, // New in ART 29 - SECTION_INTERNED_STRINGS = 6, - SECTION_CLASS_TABLE = 7, // New in ART 29 - SECTION_IMAGE_BITMAP = 8, + SECTION_OBJECTS = 0, + SECTION_ART_FIELDS = 1, + SECTION_ART_METHODS = 2, + SECTION_RUNTIME_METHODS = 3, // New in ART 29 + SECTION_IMT_CONFLICT_TABLES = 4, // New in ART 29 + SECTION_DEX_CACHE_ARRAYS = 5, // New in ART 29 + SECTION_INTERNED_STRINGS = 6, + SECTION_CLASS_TABLE = 7, // New in ART 29 + SECTION_IMAGE_BITMAP = 8, }; - } // Namespace ART_29 @@ -81,16 +81,16 @@ using ART_29::IMAGE_METHODS; using ART_29::IMAGE_ROOTS; enum IMAGE_SECTIONS { - SECTION_OBJECTS = 0, - SECTION_ART_FIELDS = 1, - SECTION_ART_METHODS = 2, - SECTION_RUNTIME_METHODS = 3, - SECTION_IM_TABLES = 4, // New in ART 30 - SECTION_IMT_CONFLICT_TABLES = 5, - SECTION_DEX_CACHE_ARRAYS = 6, - SECTION_INTERNED_STRINGS = 7, - SECTION_CLASS_TABLE = 8, - SECTION_IMAGE_BITMAP = 9, + SECTION_OBJECTS = 0, + SECTION_ART_FIELDS = 1, + SECTION_ART_METHODS = 2, + SECTION_RUNTIME_METHODS = 3, + SECTION_IM_TABLES = 4, // New in ART 30 + SECTION_IMT_CONFLICT_TABLES = 5, + SECTION_DEX_CACHE_ARRAYS = 6, + SECTION_INTERNED_STRINGS = 7, + SECTION_CLASS_TABLE = 8, + SECTION_IMAGE_BITMAP = 9, }; } // Namespace ART_30 @@ -100,19 +100,19 @@ namespace ART_44 { using ART_30::IMAGE_SECTIONS; enum IMAGE_METHODS { - RESOLUTION_METHOD = 0, - IMT_CONFLICT_METHOD = 1, - IMT_UNIMPLEMENTED_METHOD = 2, + RESOLUTION_METHOD = 0, + IMT_CONFLICT_METHOD = 1, + IMT_UNIMPLEMENTED_METHOD = 2, SAVE_ALL_CALLEE_SAVES_METHOD = 3, // New in ART 44 - SAVE_REFS_ONLY_METHOD = 4, // New in ART 44 - SAVE_REFS_AND_ARGS_METHOD = 5, // New in ART 44 - SAVE_EVERYTHING_METHOD = 6, // New in ART 44 + SAVE_REFS_ONLY_METHOD = 4, // New in ART 44 + SAVE_REFS_AND_ARGS_METHOD = 5, // New in ART 44 + SAVE_EVERYTHING_METHOD = 6, // New in ART 44 }; enum IMAGE_ROOTS { - DEX_CACHES = 0, - CLASS_ROOTS = 1, + DEX_CACHES = 0, + CLASS_ROOTS = 1, CLASS_LOADER = 2, // New in ART 44 }; @@ -121,13 +121,13 @@ enum IMAGE_ROOTS { namespace ART_46 { -using ART_30::IMAGE_SECTIONS; using ART_30::IMAGE_METHODS; using ART_30::IMAGE_ROOTS; +using ART_30::IMAGE_SECTIONS; } // Namespace ART_46 } -} + #endif diff --git a/vendor/lief/include/LIEF/ART/hash.hpp b/vendor/lief/include/LIEF/ART/hash.hpp index 32e8910..f09921b 100644 --- a/vendor/lief/include/LIEF/ART/hash.hpp +++ b/vendor/lief/include/LIEF/ART/hash.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,27 +13,30 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_HASH_H_ -#define LIEF_ART_HASH_H_ +#ifndef LIEF_ART_HASH_H +#define LIEF_ART_HASH_H -#include "LIEF/visibility.h" #include "LIEF/hash.hpp" -#include "LIEF/ART.hpp" +#include "LIEF/visibility.h" namespace LIEF { +class Object; + namespace ART { +class File; +class Header; class LIEF_API Hash : public LIEF::Hash { public: - static size_t hash(const Object& obj); + static LIEF::Hash::value_type hash(const Object& obj); public: using LIEF::Hash::Hash; using LIEF::Hash::visit; public: - void visit(const File& file) override; - void visit(const Header& header) override; + void visit(const File& file) override; + void visit(const Header& header) override; ~Hash() override; }; diff --git a/vendor/lief/include/LIEF/ART/java_structures.hpp b/vendor/lief/include/LIEF/ART/java_structures.hpp index e94a482..d26bff4 100644 --- a/vendor/lief/include/LIEF/ART/java_structures.hpp +++ b/vendor/lief/include/LIEF/ART/java_structures.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,31 +13,28 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_JAVA_STRUCTURES_H_ -#define LIEF_ART_JAVA_STRUCTURES_H_ +#ifndef LIEF_ART_JAVA_STRUCTURES_H +#define LIEF_ART_JAVA_STRUCTURES_H -#include -#include #include "LIEF/types.hpp" -#include "LIEF/ART/enums.hpp" -#include "LIEF/ART/types.hpp" +#include -namespace LIEF { -//! @brief Namespace related to the LIEF's ART module -namespace ART { -namespace details { +/// Namespace related to the LIEF's ART module + + +namespace LIEF::ART::details { struct no_brooks_read_barrier_t {}; // ====================== // Android 6.0.1 - ART 17 // ====================== -namespace ART_17 { -//! @brief Namespace related to the Java part of ART 17 -namespace Java { + +/// Namespace related to the Java part of ART 17 +namespace ART_17::Java { using heap_reference_t = uint32_t; @@ -49,25 +46,25 @@ struct brooks_read_barrier_t { template struct jobject_t { heap_reference_t klass; - uint32_t monitor; - T brooks_read_barrier; + uint32_t monitor; + T brooks_read_barrier; }; template<> struct jobject_t { heap_reference_t klass; - uint32_t monitor; + uint32_t monitor; }; template struct ALIGNED_(4) jarray_t { jobject_t object; - int32_t length; + int32_t length; uint32_t* elements; }; template struct ALIGNED_(4) jclass_t { - jobject_t object; + jobject_t object; heap_reference_t class_loader; heap_reference_t component_type; @@ -86,8 +83,8 @@ struct ALIGNED_(4) jclass_t { uint64_t virtual_methods; uint32_t class_size; uint32_t clinit_thread_id; - int32_t dex_class_def_idx; - int32_t dex_type_idx; + int32_t dex_class_def_idx; + int32_t dex_type_idx; uint32_t num_direct_methods; uint32_t num_instance_fields; uint32_t num_reference_instance_fields; @@ -97,15 +94,15 @@ struct ALIGNED_(4) jclass_t { uint32_t object_size; uint32_t primitive_type; uint32_t reference_instance_offsets; - int32_t status; + int32_t status; }; template struct ALIGNED_(4) jstring_t { jobject_t object; - int32_t count; - uint32_t hash_code; - uint16_t* value; + int32_t count; + uint32_t hash_code; + uint16_t* value; }; template @@ -118,21 +115,21 @@ struct ALIGNED_(4) jdex_cache_t { heap_reference_t resolved_methods; heap_reference_t resolved_types; heap_reference_t strings; - uint64_t dex_file; + uint64_t dex_file; }; } // Namespace Java -} // Namespace ART_17 +// Namespace ART_17 // ====================== // Android 7.0.0 - ART 29 // ====================== -namespace ART_29 { -//! @brief Namespace related to the Java part of ART 29 -namespace Java { -using heap_reference_t = ART_17::Java::heap_reference_t; + +/// Namespace related to the Java part of ART 29 +namespace ART_29::Java { +using heap_reference_t = ART_17::Java::heap_reference_t; using brooks_read_barrier_t = ART_17::Java::brooks_read_barrier_t; template @@ -143,9 +140,9 @@ using jarray_t = ART_17::Java::jarray_t; template struct ALIGNED_(4) jclass_t { - jobject_t object; + jobject_t object; - heap_reference_t annotation_type; // ADDED in ART 29 + heap_reference_t annotation_type; // ADDED in ART 29 heap_reference_t class_loader; heap_reference_t component_type; heap_reference_t dex_cache; @@ -153,19 +150,19 @@ struct ALIGNED_(4) jclass_t { heap_reference_t iftable; heap_reference_t name; heap_reference_t super_class; - heap_reference_t verify_error; // Type CHANGED from Class to Object + heap_reference_t verify_error; // Type CHANGED from Class to Object heap_reference_t vtable; uint32_t access_flags; - uint64_t dex_cache_strings; // direct_methods REPLACED with dex_cache_string + uint64_t dex_cache_strings; // direct_methods REPLACED with dex_cache_string uint64_t ifields; - uint64_t methods; // ADDED in ART 29 + uint64_t methods; // ADDED in ART 29 uint64_t sfields; - uint32_t class_flags; // virtual_methods REPLACED with class_flags + uint32_t class_flags; // virtual_methods REPLACED with class_flags uint32_t class_size; uint32_t clinit_thread_id; - int32_t dex_class_def_idx; - int32_t dex_type_idx; + int32_t dex_class_def_idx; + int32_t dex_type_idx; // uint32_t num_direct_methods; // REMOVED in ART 29 // uint32_t num_instance_fields; // REMOVED in ART 29 uint32_t num_reference_instance_fields; @@ -175,10 +172,10 @@ struct ALIGNED_(4) jclass_t { uint32_t object_size; uint32_t primitive_type; uint32_t reference_instance_offsets; - int32_t status; + int32_t status; - uint16_t copied_methods_offset; // ADDED in ART 29 - uint16_t virtual_methods_offset; // ADDED in ART 29 + uint16_t copied_methods_offset; // ADDED in ART 29 + uint16_t virtual_methods_offset; // ADDED in ART 29 }; @@ -192,33 +189,31 @@ struct ALIGNED_(4) jdex_cache_t { heap_reference_t dex; heap_reference_t location; - uint64_t dex_file; // LOCATION CHANGED - uint64_t resolved_fields; // TYPE CHANGED from heap_reference_t to uint64_t - uint64_t resolved_methods; // TYPE CHANGED from heap_reference_t to uint64_t - uint64_t resolved_types; // TYPE CHANGED from heap_reference_t to uint64_t - uint64_t strings; // TYPE CHANGED from heap_reference_t to uint64_t - uint32_t num_resolved_fields; // ADDED in ART 29 - uint32_t num_resolved_methods; // ADDED in ART 29 - uint32_t num_resolved_types; // ADDED in ART 29 - uint32_t num_strings; // ADDED in ART 29 + uint64_t dex_file; // LOCATION CHANGED + uint64_t resolved_fields; // TYPE CHANGED from heap_reference_t to uint64_t + uint64_t resolved_methods; // TYPE CHANGED from heap_reference_t to uint64_t + uint64_t resolved_types; // TYPE CHANGED from heap_reference_t to uint64_t + uint64_t strings; // TYPE CHANGED from heap_reference_t to uint64_t + uint32_t num_resolved_fields; // ADDED in ART 29 + uint32_t num_resolved_methods; // ADDED in ART 29 + uint32_t num_resolved_types; // ADDED in ART 29 + uint32_t num_strings; // ADDED in ART 29 }; - - } // Namespace Java -} // Namespace ART_29 +// Namespace ART_29 // ====================== // Android 7.1.X - ART 30 // ====================== -namespace ART_30 { -//! @brief Namespace related to the Java part of ART 30 -namespace Java { -using heap_reference_t = ART_29::Java::heap_reference_t; +/// Namespace related to the Java part of ART 30 +namespace ART_30::Java { + +using heap_reference_t = ART_29::Java::heap_reference_t; using brooks_read_barrier_t = ART_29::Java::brooks_read_barrier_t; template @@ -239,18 +234,18 @@ template using jdex_cache_t = ART_29::Java::jdex_cache_t; } // Namespace Java -} // Namespace ART_30 +// Namespace ART_30 // ====================== // Android 8.0.0 - ART 44 // ====================== -namespace ART_44 { -//! @brief Namespace related to the Java part of ART 44 -namespace Java { +/// Namespace related to the Java part of ART 44 +namespace ART_44::Java { -using heap_reference_t = ART_30::Java::heap_reference_t; + +using heap_reference_t = ART_30::Java::heap_reference_t; using brooks_read_barrier_t = ART_30::Java::brooks_read_barrier_t; template @@ -261,13 +256,13 @@ using jarray_t = ART_30::Java::jarray_t; template struct ALIGNED_(4) jclass_t { - jobject_t object; + jobject_t object; // heap_reference_t annotation_type; // REMOVED in ART 44 heap_reference_t class_loader; heap_reference_t component_type; heap_reference_t dex_cache; - heap_reference_t ext_data; // ADDED in ART 44 + heap_reference_t ext_data; // ADDED in ART 44 heap_reference_t iftable; heap_reference_t name; heap_reference_t super_class; @@ -279,26 +274,26 @@ struct ALIGNED_(4) jclass_t { uint64_t ifields; uint64_t methods; uint64_t sfields; - uint32_t access_flags; // ADDED in ART 44 + uint32_t access_flags; // ADDED in ART 44 uint32_t class_flags; uint32_t class_size; uint32_t clinit_thread_id; - int32_t dex_class_def_idx; - int32_t dex_type_idx; + int32_t dex_class_def_idx; + int32_t dex_type_idx; uint32_t num_reference_instance_fields; uint32_t num_reference_static_fields; uint32_t object_size; - uint32_t object_size_alloc_fast_path; // ADDED in ART 44 + uint32_t object_size_alloc_fast_path; // ADDED in ART 44 uint32_t primitive_type; uint32_t reference_instance_offsets; - int32_t status; + int32_t status; uint16_t copied_methods_offset; uint16_t virtual_methods_offset; }; // No changes in jstring structure but string can be -// encoded as as char16_t or char (compressed) +// encoded as char16_t or char (compressed) // count[0] (LSB) == 1 ----> compressed // count[0] (LSB) == 0 ----> chat16_t template @@ -310,35 +305,35 @@ struct ALIGNED_(4) jdex_cache_t { // heap_reference_t dex; // REMOVED in ART 44 heap_reference_t location; - uint32_t num_resolved_call_sites; // ADDED in ART 44 (related to DEX38 format) - uint64_t dex_file; - uint64_t resolved_call_sites; // ADDED in ART 44 (related to DEX38 format) - uint64_t resolved_fields; - uint64_t resolved_method_types; // ADDED in ART 44 - uint64_t resolved_methods; - uint64_t resolved_types; - uint64_t strings; - uint32_t num_resolved_fields; - uint32_t num_resolved_methods_types; // ADDED in ART 44 - uint32_t num_resolved_methods; - uint32_t num_resolved_types; - uint32_t num_strings; + uint32_t num_resolved_call_sites; // ADDED in ART 44 (related to DEX38 format) + uint64_t dex_file; + uint64_t resolved_call_sites; // ADDED in ART 44 (related to DEX38 format) + uint64_t resolved_fields; + uint64_t resolved_method_types; // ADDED in ART 44 + uint64_t resolved_methods; + uint64_t resolved_types; + uint64_t strings; + uint32_t num_resolved_fields; + uint32_t num_resolved_methods_types; // ADDED in ART 44 + uint32_t num_resolved_methods; + uint32_t num_resolved_types; + uint32_t num_strings; }; } // Namespace Java -} // Namespace ART_44 +// Namespace ART_44 // ====================== // Android 8.1.X - ART 46 // ====================== -namespace ART_46 { -//! @brief Namespace related to the Java part of ART 46 -namespace Java { -using heap_reference_t = ART_44::Java::heap_reference_t; +/// Namespace related to the Java part of ART 46 +namespace ART_46::Java { + +using heap_reference_t = ART_44::Java::heap_reference_t; using brooks_read_barrier_t = ART_44::Java::brooks_read_barrier_t; template @@ -357,17 +352,17 @@ template using jdex_cache_t = ART_44::Java::jdex_cache_t; } // Namespace Java -} // Namespace ART_46 +// Namespace ART_46 // ====================== // Android 9.0.0 - ART 66 // ====================== -namespace ART_56 { -//! @brief Namespace related to the Java part of ART 46 -namespace Java { -using heap_reference_t = ART_46::Java::heap_reference_t; +/// Namespace related to the Java part of ART 46 +namespace ART_56::Java { + +using heap_reference_t = ART_46::Java::heap_reference_t; using brooks_read_barrier_t = ART_46::Java::brooks_read_barrier_t; template @@ -386,12 +381,11 @@ template using jdex_cache_t = ART_46::Java::jdex_cache_t; } // Namespace Java -} // Namespace ART_56 - -} // namespace details -} // Namespace ART -} // Namespace LIEF +// Namespace ART_56 +} +// Namespace ART +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/ART/json.hpp b/vendor/lief/include/LIEF/ART/json.hpp index d3c4e85..502f5d6 100644 --- a/vendor/lief/include/LIEF/ART/json.hpp +++ b/vendor/lief/include/LIEF/ART/json.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,8 +13,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_PUBLIC_JSON_H_ -#define LIEF_ART_PUBLIC_JSON_H_ +#ifndef LIEF_ART_PUBLIC_JSON_H +#define LIEF_ART_PUBLIC_JSON_H #include "LIEF/visibility.h" #include diff --git a/vendor/lief/include/LIEF/ART/types.hpp b/vendor/lief/include/LIEF/ART/types.hpp index 0d77ab3..dc38ed0 100644 --- a/vendor/lief/include/LIEF/ART/types.hpp +++ b/vendor/lief/include/LIEF/ART/types.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,18 +13,17 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_TYPE_TRAITS_H_ -#define LIEF_ART_TYPE_TRAITS_H_ +#ifndef LIEF_ART_TYPE_TRAITS_H +#define LIEF_ART_TYPE_TRAITS_H -#include -#include "LIEF/iterators.hpp" +#include -namespace LIEF { -namespace ART { - using art_version_t = uint32_t; +namespace LIEF::ART { -} // Namesapce ART -} // Namespace LIEF +using art_version_t = uint32_t; + +} // Namespace ART +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/ART/utils.hpp b/vendor/lief/include/LIEF/ART/utils.hpp index bc28352..8e687d0 100644 --- a/vendor/lief/include/LIEF/ART/utils.hpp +++ b/vendor/lief/include/LIEF/ART/utils.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,39 +13,37 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ART_UTILS_H_ -#define LIEF_ART_UTILS_H_ +#ifndef LIEF_ART_UTILS_H +#define LIEF_ART_UTILS_H -#include +#include #include #include "LIEF/ART/types.hpp" #include "LIEF/platforms/android.hpp" -#include "LIEF/types.hpp" #include "LIEF/visibility.h" -namespace LIEF { -namespace ART { -//! @brief Check if the given file is an ART one. -LIEF_API bool is_art(const std::string& file); +namespace LIEF::ART { -//! @brief Check if the given raw data is an ART one. +/// Check if the given file is an ART one. +LIEF_API bool is_art(std::string_view file); + +/// Check if the given raw data is an ART one. LIEF_API bool is_art(const std::vector& raw); -//! @brief Return the ART version of the given file -LIEF_API art_version_t version(const std::string& file); +/// Return the ART version of the given file +LIEF_API art_version_t version(std::string_view file); -//! @brief Return the ART version of the raw data +/// Return the ART version of the raw data LIEF_API art_version_t version(const std::vector& raw); -//! @brief Return the ANDROID_VERSIONS associated with the given ART version +/// Return the ANDROID_VERSIONS associated with the given ART version LIEF_API LIEF::Android::ANDROID_VERSIONS android_version(art_version_t version); } -} #endif diff --git a/vendor/lief/include/LIEF/ASM.hpp b/vendor/lief/include/LIEF/ASM.hpp new file mode 100644 index 0000000..73e1d6b --- /dev/null +++ b/vendor/lief/include/LIEF/ASM.hpp @@ -0,0 +1,30 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_ASM_H +#define LIEF_ASM_H +// IWYU pragma: begin_exports +#include "LIEF/asm/Engine.hpp" +#include "LIEF/asm/Instruction.hpp" + +#include "LIEF/asm/aarch64.hpp" +#include "LIEF/asm/arm.hpp" +#include "LIEF/asm/ebpf.hpp" +#include "LIEF/asm/mips.hpp" +#include "LIEF/asm/powerpc.hpp" +#include "LIEF/asm/riscv.hpp" +#include "LIEF/asm/x86.hpp" +// IWYU pragma: end_exports +#endif diff --git a/vendor/lief/include/LIEF/Abstract.hpp b/vendor/lief/include/LIEF/Abstract.hpp index 2e2d740..e3f6d91 100644 --- a/vendor/lief/include/LIEF/Abstract.hpp +++ b/vendor/lief/include/LIEF/Abstract.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,16 +13,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_H_ -#define LIEF_ABSTRACT_H_ +#ifndef LIEF_ABSTRACT_H +#define LIEF_ABSTRACT_H -#include -#include -#include -#include -#include -#include -#include -#include +// IWYU pragma: begin_exports +#include "LIEF/Abstract/Binary.hpp" +#include "LIEF/Abstract/Function.hpp" +#include "LIEF/Abstract/Parser.hpp" +#include "LIEF/Abstract/Relocation.hpp" +#include "LIEF/Abstract/Section.hpp" +#include "LIEF/Abstract/Symbol.hpp" +// IWYU pragma: end_exports #endif diff --git a/vendor/lief/include/LIEF/Abstract/Binary.hpp b/vendor/lief/include/LIEF/Abstract/Binary.hpp index 59ade34..c58cad4 100644 --- a/vendor/lief/include/LIEF/Abstract/Binary.hpp +++ b/vendor/lief/include/LIEF/Abstract/Binary.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,208 +13,449 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_BINARY_H_ -#define LIEF_ABSTRACT_BINARY_H_ +#ifndef LIEF_ABSTRACT_BINARY_H +#define LIEF_ABSTRACT_BINARY_H -#include +#include #include +#include -#include "LIEF/types.hpp" -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" -#include "LIEF/iterators.hpp" +#include "LIEF/compiler_attributes.hpp" #include "LIEF/errors.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/span.hpp" +#include "LIEF/visibility.h" -#include "LIEF/Abstract/Header.hpp" #include "LIEF/Abstract/Function.hpp" +#include "LIEF/Abstract/Header.hpp" + +#include "LIEF/asm/AssemblerConfig.hpp" +#include "LIEF/asm/Instruction.hpp" -//! LIEF namespace +namespace llvm { +class MCInst; +} + +/// LIEF namespace namespace LIEF { class Section; class Relocation; class Symbol; -//! Abstract binary that exposes an uniform API for the -//! different executable file formats -class LIEF_API Binary : public Object { +class DebugInfo; - public: +namespace assembly { +class Engine; +} - //! Type of a virtual address +/// Generic interface representing a binary executable. +/// +/// This class provides a unified interface across multiple binary formats +/// such as ELF, PE, Mach-O, and others. It enables users to access binary +/// components like headers, sections, symbols, relocations, +/// and functions in a format-agnostic way. +/// +/// Subclasses like LIEF::PE::Binary implement format-specific API +class LIEF_API Binary : public Object { + public: + /// Enumeration of virtual address types used for patching and memory access. enum class VA_TYPES { - AUTO = 0, ///< Try to guess if it's relative or not - RVA = 1, ///< Relative - VA = 2, ///< Absolute + /// Automatically determine if the address is absolute or relative + /// (default behavior). + AUTO = 0, + + /// Relative Virtual Address (RVA), offset from image base. + RVA = 1, + + /// Absolute Virtual Address. + VA = 2, + }; + + enum FORMATS { + UNKNOWN = 0, + ELF, + PE, + MACHO, + OAT, }; using functions_t = std::vector; - //! Internal container + /// Internal container using sections_t = std::vector; - //! Iterator that outputs LIEF::Section& + /// Iterator that outputs LIEF::Section& using it_sections = ref_iterator; - //! Iterator that outputs const LIEF::Section& + /// Iterator that outputs const LIEF::Section& using it_const_sections = const_ref_iterator; - //! Internal container + /// Internal container using symbols_t = std::vector; - //! Iterator that outputs LIEF::Symbol& + /// Iterator that outputs LIEF::Symbol& using it_symbols = ref_iterator; - //! Iterator that outputs const LIEF::Symbol& + /// Iterator that outputs const LIEF::Symbol& using it_const_symbols = const_ref_iterator; - //! Internal container + /// Internal container using relocations_t = std::vector; - //! Iterator that outputs LIEF::Relocation& + /// Iterator that outputs LIEF::Relocation& using it_relocations = ref_iterator; - //! Iterator that outputs const LIEF::Relocation& + /// Iterator that outputs const LIEF::Relocation& using it_const_relocations = const_ref_iterator; + /// Instruction iterator + using instructions_it = iterator_range; + public: Binary(); - virtual ~Binary(); - - Binary& operator=(const Binary&); - Binary(const Binary&); - - //! Executable format (ELF, PE, Mach-O) of the underlying binary - EXE_FORMATS format() const; - - //! Return the abstract header of the binary - Header header() const; - - //! Return an iterator over the abstracted symbols in which the elements **can** be modified - it_symbols symbols(); - - //! Return an iterator over the abstracted symbols in which the elements **can't** be modified - it_const_symbols symbols() const; - - //! Check if a Symbol with the given name exists - bool has_symbol(const std::string& name) const; - - //! Return the Symbol with the given name - //! If the symbol does not exist, return a nullptr - const Symbol* get_symbol(const std::string& name) const; - - Symbol* get_symbol(const std::string& name); - - //! Return an iterator over the binary's sections (LIEF::Section) - it_sections sections(); - it_const_sections sections() const; - - //! Remove **all** the sections in the underlying binary + Binary(FORMATS fmt); + + ~Binary() override; + + Binary& operator=(const Binary&) = delete; + Binary(const Binary&) = delete; + + /// Executable format (ELF, PE, Mach-O) of the underlying binary + FORMATS format() const { + return format_; + } + + /// Return the abstract header of the binary + Header header() const { + return get_abstract_header(); + } + + /// Return an iterator over the abstracted symbols in which the elements **can** + /// be modified + it_symbols symbols() LIEF_LIFETIMEBOUND { + return get_abstract_symbols(); + } + + /// Return an iterator over the abstracted symbols in which the elements + /// **can't** be modified + it_const_symbols symbols() const LIEF_LIFETIMEBOUND { + return const_cast(this)->get_abstract_symbols(); + } + + /// Check if a Symbol with the given name exists + bool has_symbol(const std::string& name) const { + return get_symbol(name) != nullptr; + } + + /// Return the Symbol with the given name + /// If the symbol does not exist, return a nullptr + const Symbol* get_symbol(const std::string& name) const LIEF_LIFETIMEBOUND; + + Symbol* get_symbol(const std::string& name) LIEF_LIFETIMEBOUND { + return const_cast(static_cast(this)->get_symbol(name)); + } + + /// Return an iterator over the binary's sections (LIEF::Section) + it_sections sections() LIEF_LIFETIMEBOUND { + return get_abstract_sections(); + } + + it_const_sections sections() const LIEF_LIFETIMEBOUND { + return const_cast(this)->get_abstract_sections(); + } + + /// Remove **all** the sections in the underlying binary virtual void remove_section(const std::string& name, bool clear = false) = 0; - //! Return an iterator over the binary relocation (LIEF::Relocation) - it_relocations relocations(); - it_const_relocations relocations() const; + /// Return an iterator over the binary relocations (LIEF::Relocation) + it_relocations relocations() LIEF_LIFETIMEBOUND { + return get_abstract_relocations(); + } - //! Binary's entrypoint (if any) - virtual uint64_t entrypoint() const = 0; + it_const_relocations relocations() const LIEF_LIFETIMEBOUND { + return const_cast(this)->get_abstract_relocations(); + } - //! Binary's name - const std::string& name() const; + /// Binary's entrypoint (if any) + virtual uint64_t entrypoint() const = 0; - //! Binary's original size - uint64_t original_size() const; + /// Binary's original size + uint64_t original_size() const { + return original_size_; + } - //! Return the functions exported by the binary - functions_t exported_functions() const; + /// Return the functions exported by the binary + functions_t exported_functions() const { + return get_abstract_exported_functions(); + } - //! Return libraries which are imported by the binary - std::vector imported_libraries() const; + /// Return libraries which are imported by the binary + std::vector imported_libraries() const { + return get_abstract_imported_libraries(); + } - //! Return functions imported by the binary - functions_t imported_functions() const; + /// Return functions imported by the binary + functions_t imported_functions() const { + return get_abstract_imported_functions(); + } - //! Return the address of the given function name - virtual result get_function_address(const std::string& func_name) const; + /// Return the address of the given function name + virtual result + get_function_address(const std::string& func_name) const; - //! Method so that a ``visitor`` can visit us + /// Method so that a ``visitor`` can visit us void accept(Visitor& visitor) const override; std::vector xref(uint64_t address) const; - //! Patch the content at virtual address @p address with @p patch_value - //! - //! @param[in] address Address to patch - //! @param[in] patch_value Patch to apply - //! @param[in] addr_type Specify if the address should be used as an - //! absolute virtual address or a RVA - virtual void patch_address(uint64_t address, const std::vector& patch_value, + /// Patch the content at virtual address @p address with @p patch_value + /// + /// @param[in] address Address to patch + /// @param[in] patch_value Patch to apply + /// @param[in] addr_type Specify if the address should be used as an + /// absolute virtual address or a RVA + virtual void patch_address(uint64_t address, + const std::vector& patch_value, VA_TYPES addr_type = VA_TYPES::AUTO) = 0; - //! Patch the address with the given value - //! - //! @param[in] address Address to patch - //! @param[in] patch_value Patch to apply - //! @param[in] size Size of the value in **bytes** (1, 2, ... 8) - //! @param[in] addr_type Specify if the address should be used as an absolute virtual address or an RVA - virtual void patch_address(uint64_t address, uint64_t patch_value, size_t size = sizeof(uint64_t), + /// Patch the address with the given value + /// + /// @param[in] address Address to patch + /// @param[in] patch_value Patch to apply + /// @param[in] size Size of the value in **bytes** (1, 2, ... 8) + /// @param[in] addr_type Specify if the address should be used as an absolute + /// virtual address or an RVA + virtual void patch_address(uint64_t address, uint64_t patch_value, + size_t size = sizeof(uint64_t), VA_TYPES addr_type = VA_TYPES::AUTO) = 0; - //! Return the content located at the given virtual address - virtual std::vector get_content_from_virtual_address(uint64_t virtual_address, - uint64_t size, VA_TYPES addr_type = VA_TYPES::AUTO) const = 0; - - //! Change the binary's name - void name(const std::string& name); - - //! @brief Change binary's original size. - //! - //! @warning - //! This function should be used carefully as some optimizations - //! can be performed with this value - void original_size(uint64_t size); - - //! Check if the binary is position independent + /// Return the content located at the given virtual address + virtual span get_content_from_virtual_address( + uint64_t virtual_address, uint64_t size, VA_TYPES addr_type = VA_TYPES::AUTO + ) const LIEF_LIFETIMEBOUND = 0; + + /// Get the integer value at the given virtual address + template + LIEF::result + get_int_from_virtual_address(uint64_t va, + VA_TYPES addr_type = VA_TYPES::AUTO) const { + T value; + static_assert(std::is_integral_v, "Require an integral type"); + span raw = + get_content_from_virtual_address(va, sizeof(T), addr_type); + if (raw.empty() || raw.size() < sizeof(T)) { + return make_error_code(lief_errors::read_error); + } + + std::copy(raw.data(), raw.data() + sizeof(T), + reinterpret_cast(&value)); + return value; + } + + /// Change binary's original size. + /// + /// @warning + /// This function should be used carefully as some optimizations + /// can be performed with this value + void original_size(uint64_t size) { + original_size_ = size; + } + + /// Check if the binary is position independent virtual bool is_pie() const = 0; - //! Check if the binary uses ``NX`` protection + /// Check if the binary uses ``NX`` protection virtual bool has_nx() const = 0; - //! Default image base address if the ASLR is not enabled. + /// Default image base address if the ASLR is not enabled. virtual uint64_t imagebase() const = 0; - //! Constructor functions that are called prior any other functions + /// Constructor functions that are called prior any other functions virtual functions_t ctor_functions() const = 0; - //! Convert the given offset into a virtual address. - //! - //! @param[in] offset The offset to convert. - //! @param[in] slide If not 0, it will replace the default base address (if any) - virtual result offset_to_virtual_address(uint64_t offset, uint64_t slide = 0) const = 0; - - virtual std::ostream& print(std::ostream& os) const; - - //! Build & transform the Binary object representation into a *real* executable - virtual void write(const std::string& name) = 0; - virtual void write(std::ostream& os) = 0; - - LIEF_API friend std::ostream& operator<<(std::ostream& os, const Binary& binary); + /// Convert the given offset into a virtual address. + /// + /// @param[in] offset The offset to convert. + /// @param[in] slide If not 0, it will replace the default base address (if + /// any) + virtual result offset_to_virtual_address(uint64_t offset, + uint64_t slide = 0) const = 0; + + virtual std::ostream& print(std::ostream& os) const { + return os; + } + + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const Binary& binary) { + binary.print(os); + return os; + } + + /// Return the debug info if present. It can be either a + /// LIEF::dwarf::DebugInfo or a LIEF::pdb::DebugInfo + /// + /// For ELF and Mach-O binaries, it returns the given DebugInfo object **only** + /// if the binary embeds the DWARF debug info in the binary itself. + /// + /// For PE file, this function tries to find the **external** PDB using + /// the LIEF::PE::CodeViewPDB::filename() output (if present). One can also + /// use LIEF::pdb::load() or LIEF::pdb::DebugInfo::from_file() to get PDB debug + /// info. + /// + /// @warning This function requires LIEF's extended version otherwise it + /// **always** returns a nullptr + DebugInfo* debug_info() const LIEF_LIFETIMEBOUND; + + /// Disassemble code starting at the given virtual address and with the given + /// size. + /// + /// ```cpp + /// auto insts = binary->disassemble(0xacde, 100); + /// for (std::unique_ptr inst : insts) { + /// std::cout << inst->to_string() << '\n'; + /// } + /// ``` + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(uint64_t address, size_t size) const; + + /// Disassemble code starting at the given virtual address + /// + /// ```cpp + /// auto insts = binary->disassemble(0xacde); + /// for (std::unique_ptr inst : insts) { + /// std::cout << inst->to_string() << '\n'; + /// } + /// ``` + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(uint64_t address) const; + + /// Disassemble code for the given symbol name + /// + /// ```cpp + /// auto insts = binary->disassemble("__libc_start_main"); + /// for (std::unique_ptr inst : insts) { + /// std::cout << inst->to_string() << '\n'; + /// } + /// ``` + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const std::string& function) const; + + /// Disassemble code provided by the given buffer at the specified + /// `address` parameter. + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const uint8_t* buffer, size_t size, + uint64_t address = 0) const; + + + /// Disassemble code provided by the given vector of bytes at the specified + /// `address` parameter. + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const std::vector& buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + instructions_it disassemble(LIEF::span buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + instructions_it disassemble(LIEF::span buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + /// Assemble **and patch** the provided assembly code at the specified address. + /// + /// The function returns the generated assembly bytes + /// + /// ```cpp + /// bin->assemble(0x12000440, R"asm( + /// xor rax, rbx; + /// mov rcx, rax; + /// )asm"); + /// ``` + /// + /// If you need to configure the assembly engine or to define addresses for + /// symbols, you can provide your own assembly::AssemblerConfig. + std::vector assemble(uint64_t address, const std::string& Asm, + assembly::AssemblerConfig& config = + assembly::AssemblerConfig::default_config()); + + /// Assemble **and patch** the address with the given LLVM MCInst. + /// + /// @warning Because of ABI compatibility, this MCInst can **only be used** + /// with the **same** version of LLVM used by LIEF (see documentation) + std::vector assemble(uint64_t address, const llvm::MCInst& inst); + + /// Assemble **and patch** the address with the given LLVM MCInst. + /// + /// @warning Because of ABI compatibility, this MCInst can **only be used** + /// with the **same** version of LLVM used by LIEF (see documentation) + std::vector assemble(uint64_t address, + const std::vector& insts); + + /// Get the default memory page size according to the architecture and + /// the format of the current binary + virtual uint64_t page_size() const; + + /// Load and associate an external debug file (e.g., DWARF or PDB) with this + /// binary. + /// + /// This method attempts to load the debug information from the file located at + /// the given path, and binds it to the current binary instance. If successful, + /// it returns a pointer to the loaded DebugInfo object. + /// + /// @param path Path to the external debug file (e.g., `.dwarf`, `.pdb`) + /// @return Pointer to the loaded DebugInfo object on success, or `nullptr` on + /// failure. + /// + /// @warning It is the caller's responsibility to ensure that the debug file is + /// compatible with the binary. Incorrect associations may lead to + /// inconsistent or invalid results. + /// + /// @note This function does not verify that the debug file matches the binary's + /// unique identifier (e.g., build ID, GUID). + DebugInfo* load_debug_info(const std::string& path); + + /// Size of the binary when mapped in memory + virtual uint64_t virtual_size() const { + return 0; + } protected: - EXE_FORMATS format_ = EXE_FORMATS::FORMAT_UNKNOWN; - std::string name_; - + FORMATS format_ = FORMATS::UNKNOWN; + mutable std::unique_ptr debug_info_; + mutable std::unordered_map> engines_; uint64_t original_size_ = 0; - // These functions need to be overloaded by the object that claims to extend this Abstract Binary + assembly::Engine* get_engine(uint64_t address) const; + + template + LIEF_LOCAL assembly::Engine* get_cache_engine(uint64_t address, F&& f) const; + + // These functions need to be overloaded by the object that claims to extend this + // Abstract Binary virtual Header get_abstract_header() const = 0; virtual symbols_t get_abstract_symbols() = 0; virtual sections_t get_abstract_sections() = 0; virtual relocations_t get_abstract_relocations() = 0; - virtual functions_t get_abstract_exported_functions() const = 0; - virtual functions_t get_abstract_imported_functions() const = 0; - virtual std::vector get_abstract_imported_libraries() const = 0; + virtual functions_t get_abstract_exported_functions() const = 0; + virtual functions_t get_abstract_imported_functions() const = 0; + virtual std::vector get_abstract_imported_libraries() const = 0; }; + +LIEF_API const char* to_string(Binary::VA_TYPES e); +LIEF_API const char* to_string(Binary::FORMATS e); + } + #endif diff --git a/vendor/lief/include/LIEF/Abstract/DebugInfo.hpp b/vendor/lief/include/LIEF/Abstract/DebugInfo.hpp new file mode 100644 index 0000000..2cbc415 --- /dev/null +++ b/vendor/lief/include/LIEF/Abstract/DebugInfo.hpp @@ -0,0 +1,81 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DEBUGINFO_H +#define LIEF_DEBUGINFO_H +#include +#include +#include + +#include "LIEF/visibility.h" +#include +namespace LIEF { + +class Binary; + +namespace details { +class DebugInfo; +} + +/// This class provides a generic interface for accessing debug information +/// from different formats such as DWARF and PDB. +/// +/// Users can use this interface to access high-level debug features like +/// resolving function addresses. +/// +/// @see LIEF::pdb::DebugInfo, LIEF::dwarf::DebugInfo +class LIEF_API DebugInfo { + public: + friend class Binary; + enum class FORMAT { + UNKNOWN = 0, + DWARF, + PDB, + }; + DebugInfo(std::unique_ptr impl); + + virtual ~DebugInfo(); + + virtual FORMAT format() const { + return FORMAT::UNKNOWN; + } + + /// This function can be used to **down cast** a DebugInfo instance: + /// + /// ```cpp + /// std::unique_ptr dbg = bin->debug_info(); + /// if (const auto* dwarf = inst->as()) { + /// dwarf->find_function("main"); + /// } + /// ``` + template + const T* as() const { + static_assert(std::is_base_of_v, + "Requires DebugInfo inheritance"); + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + /// Attempt to resolve the address of the function specified by `name`. + virtual std::optional + find_function_address(const std::string& name) const = 0; + + protected: + std::unique_ptr impl_; +}; + +} +#endif diff --git a/vendor/lief/include/LIEF/Abstract/EnumToString.hpp b/vendor/lief/include/LIEF/Abstract/EnumToString.hpp deleted file mode 100644 index 70478f2..0000000 --- a/vendor/lief/include/LIEF/Abstract/EnumToString.hpp +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ENUM_TO_STRING_H -#define LIEF_ENUM_TO_STRING_H -#include "LIEF/visibility.h" - -#include "LIEF/Abstract/enums.hpp" -#include "LIEF/Abstract/Binary.hpp" - -namespace LIEF { -LIEF_API const char* to_string(EXE_FORMATS e); -LIEF_API const char* to_string(ARCHITECTURES e); -LIEF_API const char* to_string(OBJECT_TYPES e); -LIEF_API const char* to_string(MODES e); -LIEF_API const char* to_string(ENDIANNESS e); -LIEF_API const char* to_string(Binary::VA_TYPES e); -LIEF_API const char* to_string(Function::FLAGS e); -} // namespace LIEF - -#endif - diff --git a/vendor/lief/include/LIEF/Abstract/Function.hpp b/vendor/lief/include/LIEF/Abstract/Function.hpp index 7b7d5ff..b96bb48 100644 --- a/vendor/lief/include/LIEF/Abstract/Function.hpp +++ b/vendor/lief/include/LIEF/Abstract/Function.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,80 +13,106 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_FUNCTION_H_ -#define LIEF_ABSTRACT_FUNCTION_H_ +#ifndef LIEF_ABSTRACT_FUNCTION_H +#define LIEF_ABSTRACT_FUNCTION_H #include -#include +#include #include "LIEF/Abstract/Symbol.hpp" +#include "LIEF/enums.hpp" #include "LIEF/visibility.h" namespace LIEF { -//! Class that represents a function in the binary +/// Class that represents a function in the binary class LIEF_API Function : public Symbol { public: - //! Flags used to characterize the semantic - //! of the function - enum class FLAGS { + /// Flags used to characterize the semantics of the function + enum class FLAGS : uint32_t { NONE = 0, - //! The function acts as constructor. - //! - //! Usually this flag is associated with functions - //! that are located in the ``.init_array``, ``__mod_init_func`` or ``.tls`` sections - CONSTRUCTOR, - - //! The function acts a destructor. - //! - //! Usually this flag is associated with functions - //! that are located in the ``.fini_array`` or ``__mod_term_func`` sections - DESTRUCTOR, - - //! The function is associated with Debug information - DEBUG, - - //! The function is exported by the binary and the address() method - //! returns its virtual address in the binary - EXPORTED, - - //! The function is **imported** by the binary and the address() should return 0 - IMPORTED, + /// The function acts as a constructor. + /// + /// Usually this flag is associated with functions + /// that are located in the `.init_array`, `__mod_init_func` or `.tls` sections + CONSTRUCTOR = 1 << 0, + + /// The function acts as a destructor. + /// + /// Usually this flag is associated with functions + /// that are located in the `.fini_array` or `__mod_term_func` sections + DESTRUCTOR = 1 << 1, + + /// The function is associated with Debug information + DEBUG_INFO = 1 << 2, + + /// The function is exported by the binary and the address() method + /// returns its virtual address in the binary + EXPORTED = 1 << 3, + + /// The function is **imported** by the binary and the address() should return + /// 0 + IMPORTED = 1 << 4, }; - using flags_list_t = std::vector; - using flags_t = std::set; - public: - Function(); - Function(const std::string& name); - Function(uint64_t address); - Function(const std::string& name, uint64_t address); - Function(const std::string& name, uint64_t address, const flags_list_t& flags); - Function(const Function&); - Function& operator=(const Function&); - virtual ~Function(); - - //! List of FLAGS - flags_list_t flags() const; - - //! Add a flag to the current function - Function& add(FLAGS f); - - //! Address of the current function. For functions that are set with the FLAGS::IMPORTED flag, - //! this value is likely 0. - uint64_t address() const; - void address(uint64_t address); - - //! Method so that the ``visitor`` can visit us + Function() = default; + Function(const std::string& name) : + Symbol(name) {} + Function(uint64_t address) : + Function("", address) {} + Function(const std::string& name, uint64_t address) : + Symbol(name, address) {} + Function(const std::string& name, uint64_t address, FLAGS flags) : + Function(name, address) { + flags_ = flags; + } + + Function(const Function&) = default; + Function& operator=(const Function&) = default; + + ~Function() override = default; + + /// List of FLAGS + std::vector flags_list() const; + + FLAGS flags() const { + return flags_; + } + + /// Add a flag to the current function + Function& add(FLAGS f) { + flags_ = (FLAGS)((uint32_t)flags_ | (uint32_t)f); + return *this; + } + + /// Check if the function has the given flag + bool has(FLAGS f) const { + return ((uint32_t)flags_ & (uint32_t)f) != 0; + } + + /// Address of the current function. For functions that are set with the + /// FLAGS::IMPORTED flag, this value is likely 0. + uint64_t address() const { + return value_; + } + + void address(uint64_t address) { + value_ = address; + } + void accept(Visitor& visitor) const override; - LIEF_API friend std::ostream& operator<<(std::ostream& os, const Function& entry); + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const Function& entry); protected: - flags_t flags_; + FLAGS flags_ = FLAGS::NONE; }; + +LIEF_API const char* to_string(Function::FLAGS e); } -#endif +ENABLE_BITMASK_OPERATORS(LIEF::Function::FLAGS); +#endif diff --git a/vendor/lief/include/LIEF/Abstract/Header.hpp b/vendor/lief/include/LIEF/Abstract/Header.hpp index e2fb370..60dfb24 100644 --- a/vendor/lief/include/LIEF/Abstract/Header.hpp +++ b/vendor/lief/include/LIEF/Abstract/Header.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,60 +13,135 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_HEADER_H_ -#define LIEF_ABSTRACT_HEADER_H_ +#ifndef LIEF_ABSTRACT_HEADER_H +#define LIEF_ABSTRACT_HEADER_H -#include -#include +#include +#include +#include #include "LIEF/Object.hpp" +#include "LIEF/enums.hpp" #include "LIEF/visibility.h" -#include "LIEF/types.hpp" - -#include "LIEF/Abstract/enums.hpp" namespace LIEF { -class LIEF_API Header : public Object { - public: - Header(); - Header(const Header&); - Header& operator=(const Header&); - virtual ~Header(); - - - ARCHITECTURES architecture() const; - const std::set& modes() const; - OBJECT_TYPES object_type() const; - uint64_t entrypoint() const; - ENDIANNESS endianness() const; - - - //! @brief ``true`` if the binary target a ``32-bits`` architecture - bool is_32() const; +namespace ELF { +class Binary; +} - //! @brief ``true`` if the binary target a ``64-bits`` architecture - bool is_64() const; +namespace PE { +class Binary; +} - //! @brief Method so that the ``visitor`` can visit us - void accept(Visitor& visitor) const override; +namespace MachO { +class Binary; +} - void architecture(ARCHITECTURES arch); - void modes(const std::set& m); - void object_type(OBJECT_TYPES type); - void entrypoint(uint64_t entrypoint); - void endianness(ENDIANNESS endianness); +class LIEF_API Header : public Object { + public: + enum class ARCHITECTURES { + UNKNOWN = 0, + ARM, + ARM64, + MIPS, + X86, + X86_64, + PPC, + SPARC, + SYSZ, + XCORE, + RISCV, + LOONGARCH, + PPC64, + }; + + enum class ENDIANNESS { + UNKNOWN = 0, + BIG, + LITTLE, + }; + + enum MODES : uint64_t { + NONE = 0, + + BITS_16 = 1LLU << 0, /// 16-bits architecture + BITS_32 = 1LLU << 1, /// 32-bits architecture + BITS_64 = 1LLU << 2, /// 64-bits architecture + THUMB = 1LLU << 3, /// Support ARM Thumb mode + + ARM64E = 1LLU << 4, /// ARM64 with extended (security) features + }; + + enum class OBJECT_TYPES { + UNKNOWN = 0, + EXECUTABLE, + LIBRARY, + OBJECT, + }; + + static Header from(const LIEF::ELF::Binary& elf); + static Header from(const LIEF::PE::Binary& pe); + static Header from(const LIEF::MachO::Binary& macho); + + Header() = default; + Header(const Header&) = default; + Header& operator=(const Header&) = default; + ~Header() override = default; + + /// Target architecture + ARCHITECTURES architecture() const { + return architecture_; + } + + /// Optional features for the given architecture + MODES modes() const { + return modes_; + } + + /// MODES as a vector + std::vector modes_list() const; + + bool is(MODES m) const { + return ((uint64_t)m & (uint64_t)modes_) != 0; + } + + OBJECT_TYPES object_type() const { + return object_type_; + } + uint64_t entrypoint() const { + return entrypoint_; + } + + ENDIANNESS endianness() const { + return endianness_; + } + + bool is_32() const { + return ((uint64_t)modes_ & (uint64_t)MODES::BITS_32) != 0; + } + + bool is_64() const { + return ((uint64_t)modes_ & (uint64_t)MODES::BITS_64) != 0; + } + + void accept(Visitor& visitor) const override; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Header& hdr); protected: - ARCHITECTURES architecture_ = ARCHITECTURES::ARCH_NONE; - std::set modes_; - OBJECT_TYPES object_type_ = OBJECT_TYPES::TYPE_NONE; - uint64_t entrypoint_ = 0; - ENDIANNESS endianness_ = ENDIANNESS::ENDIAN_NONE; - - + ARCHITECTURES architecture_ = ARCHITECTURES::UNKNOWN; + OBJECT_TYPES object_type_ = OBJECT_TYPES::UNKNOWN; + uint64_t entrypoint_ = 0; + ENDIANNESS endianness_ = ENDIANNESS::UNKNOWN; + MODES modes_ = MODES::NONE; }; + +LIEF_API const char* to_string(Header::ARCHITECTURES e); +LIEF_API const char* to_string(Header::OBJECT_TYPES e); +LIEF_API const char* to_string(Header::MODES e); +LIEF_API const char* to_string(Header::ENDIANNESS e); } +ENABLE_BITMASK_OPERATORS(LIEF::Header::MODES); + #endif diff --git a/vendor/lief/include/LIEF/Abstract/Parser.hpp b/vendor/lief/include/LIEF/Abstract/Parser.hpp index df280c0..2de820f 100644 --- a/vendor/lief/include/LIEF/Abstract/Parser.hpp +++ b/vendor/lief/include/LIEF/Abstract/Parser.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,44 +13,55 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_BUILDER_H_ -#define LIEF_ABSTRACT_BUILDER_H_ +#ifndef LIEF_ABSTRACT_PARSER_H +#define LIEF_ABSTRACT_PARSER_H -#include +#include +#include #include #include +#include "LIEF/path.hpp" #include "LIEF/visibility.h" -struct Profiler; - namespace LIEF { +class BinaryStream; class Binary; -//! Main interface to parse an executable regardless of its format +/// Main interface to parse an executable regardless of its format class LIEF_API Parser { public: - friend struct ::Profiler; + /// Construct an LIEF::Binary from the given filename + /// + /// @warning If the target file is a FAT Mach-O, it will return the **last** one + /// @see LIEF::MachO::Parser::parse + static std::unique_ptr parse(std::string_view filename); + + /// Same as parse(std::string_view) but the file is given as a + /// `std::filesystem::path` + template = 0> + static std::unique_ptr parse(const PathT& filename) { + return parse(filename.string()); + } - //! Construct an LIEF::Binary from the given filename - //! - //! @warning If the target file is a FAT Mach-O, it will return the **last** one - //! @see LIEF::MachO::Parser::parse - static std::unique_ptr parse(const std::string& filename); + /// Construct an LIEF::Binary from the given raw data + /// + /// @warning If the target file is a FAT Mach-O, it will return the **last** one + /// @see LIEF::MachO::Parser::parse + static std::unique_ptr parse(const std::vector& raw); - //! @brief Construct an LIEF::Binary from the given raw data - //! - //! @warning If the target file is a FAT Mach-O, it will return the **last** one - //! @see LIEF::MachO::Parser::parse - static std::unique_ptr parse(const std::vector& raw, const std::string& name = ""); + /// Construct an LIEF::Binary from the given stream + /// + /// @warning If the target file is a FAT Mach-O, it will return the **last** one + /// @see LIEF::MachO::Parser::parse + static std::unique_ptr parse(std::unique_ptr stream); protected: - Parser(const std::string& file); - uint64_t binary_size_ = 0; - std::string binary_name_; + Parser(std::string_view file); + uint64_t binary_size_ = 0; - ~Parser(); + ~Parser() = default; Parser(); }; } diff --git a/vendor/lief/include/LIEF/Abstract/Relocation.hpp b/vendor/lief/include/LIEF/Abstract/Relocation.hpp index 67b7290..1773a9c 100644 --- a/vendor/lief/include/LIEF/Abstract/Relocation.hpp +++ b/vendor/lief/include/LIEF/Abstract/Relocation.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,61 +13,84 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_RELOCATION_H_ -#define LIEF_ABSTRACT_RELOCATION_H_ +#ifndef LIEF_ABSTRACT_RELOCATION_H +#define LIEF_ABSTRACT_RELOCATION_H + +#include +#include -#include "LIEF/types.hpp" #include "LIEF/Object.hpp" #include "LIEF/visibility.h" namespace LIEF { -//! Class which represents an abstracted Relocation +/// Class which represents an abstracted Relocation class LIEF_API Relocation : public Object { public: - Relocation(); + Relocation() = default; + + /// Constructor from a relocation's address and size + Relocation(uint64_t address, uint8_t size) : + address_(address), + size_(size) {} - //! Constructor from a relocation's address and size - Relocation(uint64_t address, uint8_t size); + ~Relocation() override = default; - virtual ~Relocation(); + Relocation& operator=(const Relocation&) = default; + Relocation(const Relocation&) = default; + void swap(Relocation& other) { + std::swap(address_, other.address_); + std::swap(size_, other.size_); + } - Relocation& operator=(const Relocation&); - Relocation(const Relocation&); - void swap(Relocation& other); + /// Relocation's address + virtual uint64_t address() const { + return address_; + } - //! Relocation's address - virtual uint64_t address() const; + /// Relocation size in **bits** + virtual size_t size() const { + return size_; + } - //! Relocation size in **bits** - virtual size_t size() const; + virtual void address(uint64_t address) { + address_ = address; + } - virtual void address(uint64_t address); - virtual void size(size_t size); + virtual void size(size_t size) { + size_ = (uint8_t)size; + } - //! Method so that the ``visitor`` can visit us + /// Method so that the ``visitor`` can visit us void accept(Visitor& visitor) const override; - bool operator==(const Relocation& rhs) const; - bool operator!=(const Relocation& rhs) const; - //! Comparaison based on the Relocation's **address** - virtual bool operator<(const Relocation& rhs) const; + /// Comparison based on the Relocation's **address** + virtual bool operator<(const Relocation& rhs) const { + return address() < rhs.address(); + } - //! Comparaison based on the Relocation's **address** - virtual bool operator<=(const Relocation& rhs) const; + /// Comparison based on the Relocation's **address** + virtual bool operator<=(const Relocation& rhs) const { + return !(address() > rhs.address()); + } - //! Comparaison based on the Relocation's **address** - virtual bool operator>(const Relocation& rhs) const; + /// Comparison based on the Relocation's **address** + virtual bool operator>(const Relocation& rhs) const { + return address() > rhs.address(); + } - //! Comparaison based on the Relocation's **address** - virtual bool operator>=(const Relocation& rhs) const; + /// Comparison based on the Relocation's **address** + virtual bool operator>=(const Relocation& rhs) const { + return !(address() < rhs.address()); + } - LIEF_API friend std::ostream& operator<<(std::ostream& os, const Relocation& entry); + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const Relocation& entry); protected: uint64_t address_ = 0; - uint8_t size_ = 0; + uint8_t size_ = 0; }; diff --git a/vendor/lief/include/LIEF/Abstract/Section.hpp b/vendor/lief/include/LIEF/Abstract/Section.hpp index 4f43a56..ff2c217 100644 --- a/vendor/lief/include/LIEF/Abstract/Section.hpp +++ b/vendor/lief/include/LIEF/Abstract/Section.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,65 +13,87 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_SECTION_H_ -#define LIEF_ABSTRACT_SECTION_H_ +#ifndef LIEF_ABSTRACT_SECTION_H +#define LIEF_ABSTRACT_SECTION_H +#include +#include #include #include -#include -#include "LIEF/types.hpp" -#include "LIEF/span.hpp" #include "LIEF/Object.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/span.hpp" #include "LIEF/visibility.h" namespace LIEF { -//! Class which represents an abstracted section +/// Class which represents an abstracted section class LIEF_API Section : public Object { public: static constexpr size_t npos = -1; - Section(); - Section(std::string name); + Section() = default; + Section(std::string name) : + name_(std::move(name)) {} - virtual ~Section(); + ~Section() override = default; - Section& operator=(const Section&); - Section(const Section&); + Section& operator=(const Section&) = default; + Section(const Section&) = default; - //! section's name - virtual std::string name() const; + /// Section's name + virtual std::string_view name() const LIEF_LIFETIMEBOUND { + return fullname().substr(0, fullname().find_first_of('\0')); + } - //! Return the **complete** section's name which might - //! trailing (``0``) bytes - virtual const std::string& fullname() const; + /// Return the **complete** section's name which might include + /// trailing (``0``) bytes + virtual std::string_view fullname() const LIEF_LIFETIMEBOUND { + return name_; + } - //! section's content - virtual span content() const; + /// Section's content + virtual span content() const LIEF_LIFETIMEBOUND { + return {}; + } - //! Change the section size - virtual void size(uint64_t size); + /// Change the section size + virtual void size(uint64_t size) { + size_ = size; + } - //! section's size (size in the binary, not the virtual size) - virtual uint64_t size() const; + /// Section's size (size in the binary, not the virtual size) + virtual uint64_t size() const { + return size_; + } - //! Offset in the binary - virtual uint64_t offset() const; + /// Offset in the binary + virtual uint64_t offset() const { + return offset_; + } - //! Address where the section should be mapped - virtual uint64_t virtual_address() const; + /// Address where the section should be mapped + virtual uint64_t virtual_address() const { + return virtual_address_; + } - virtual void virtual_address(uint64_t virtual_address); + virtual void virtual_address(uint64_t virtual_address) { + virtual_address_ = virtual_address; + } - //! Change the section's name - virtual void name(const std::string& name); + /// Change the section's name + virtual void name(std::string name) { + name_ = std::move(name); + } - //! Change section content - virtual void content(const std::vector& data); + /// Change section content + virtual void content(const std::vector&) {} - virtual void offset(uint64_t offset); + virtual void offset(uint64_t offset) { + offset_ = offset; + } - //! Section's entropy + /// Section's entropy double entropy() const; // Search functions @@ -89,25 +111,21 @@ class LIEF_API Section : public Object { std::vector search_all(const std::string& v) const; - //! @brief Method so that the ``visitor`` can visit us + /// Method so that the ``visitor`` can visit us void accept(Visitor& visitor) const override; - bool operator==(const Section& rhs) const; - bool operator!=(const Section& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Section& entry); protected: std::string name_; - uint64_t virtual_address_ = 0; - uint64_t size_ = 0; - uint64_t offset_ = 0; + uint64_t virtual_address_ = 0; + uint64_t size_ = 0; + uint64_t offset_ = 0; private: template std::vector search_all_(const T& v) const; - - }; } diff --git a/vendor/lief/include/LIEF/Abstract/Symbol.hpp b/vendor/lief/include/LIEF/Abstract/Symbol.hpp index c2b2bd1..ff82dc3 100644 --- a/vendor/lief/include/LIEF/Abstract/Symbol.hpp +++ b/vendor/lief/include/LIEF/Abstract/Symbol.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,45 +13,77 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_SYMBOLS_H_ -#define LIEF_ABSTRACT_SYMBOLS_H_ +#ifndef LIEF_ABSTRACT_SYMBOLS_H +#define LIEF_ABSTRACT_SYMBOLS_H +#include +#include #include #include "LIEF/Object.hpp" +#include "LIEF/compiler_attributes.hpp" #include "LIEF/visibility.h" namespace LIEF { -//! This class represents a symbol in an executable format. +/// This class represents a symbol in an executable format. class LIEF_API Symbol : public Object { public: - Symbol(); - Symbol(std::string name); - Symbol(std::string name, uint64_t value); - Symbol(std::string name, uint64_t value, uint64_t size); - Symbol(const Symbol&); - Symbol& operator=(const Symbol&); - virtual ~Symbol(); + Symbol() = default; + Symbol(std::string name) : + name_(std::move(name)) {} - void swap(Symbol& other); + Symbol(std::string name, uint64_t value) : + name_(std::move(name)), + value_(value) {} - //! Return the symbol's name - virtual const std::string& name() const; - virtual std::string& name(); + Symbol(std::string name, uint64_t value, uint64_t size) : + name_(std::move(name)), + value_(value), + size_(size) {} - //! Set symbol name - virtual void name(const std::string& name); + Symbol(const Symbol&) = default; + Symbol& operator=(const Symbol&) = default; - // Symbol's value which is usually the **address** of the symbol - virtual uint64_t value() const; - virtual void value(uint64_t value); + Symbol(Symbol&&) = default; + Symbol& operator=(Symbol&&) = default; - //! This size of the symbol (when applicable) - virtual uint64_t size() const; - virtual void size(uint64_t value); + ~Symbol() override = default; - //! Method so that the ``visitor`` can visit us + void swap(Symbol& other) noexcept; + + /// Return the symbol's name + virtual std::string_view name() const LIEF_LIFETIMEBOUND { + return name_; + } + + virtual std::string& name() { + return name_; + } + + /// Set symbol name + virtual void name(std::string name) { + name_ = std::move(name); + } + + /// Symbol's value which is usually the **address** of the symbol + virtual uint64_t value() const { + return value_; + } + virtual void value(uint64_t value) { + value_ = value; + } + + /// The size of the symbol (when applicable) + virtual uint64_t size() const { + return size_; + } + + virtual void size(uint64_t value) { + size_ = value; + } + + /// Method so that the ``visitor`` can visit us void accept(Visitor& visitor) const override; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Symbol& entry); @@ -64,4 +96,3 @@ class LIEF_API Symbol : public Object { } #endif - diff --git a/vendor/lief/include/LIEF/Abstract/enums.hpp b/vendor/lief/include/LIEF/Abstract/enums.hpp deleted file mode 100644 index 4b357aa..0000000 --- a/vendor/lief/include/LIEF/Abstract/enums.hpp +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_ABSTRACT_ENUMS_H_ -#define LIEF_ABSTRACT_ENUMS_H_ - -#include "LIEF/types.hpp" - -namespace LIEF { - -//! LIEF executable format -enum EXE_FORMATS { - FORMAT_UNKNOWN = 0, - FORMAT_ELF = 1, /// ELF. See: LIEF::ELF - FORMAT_PE = 2, /// PE. See: LIEF::PE - FORMAT_MACHO = 3, /// Mach-O. See: LIEF::MachO -}; - -enum OBJECT_TYPES { - TYPE_NONE = 0, - TYPE_EXECUTABLE = 1, - TYPE_LIBRARY = 2, - TYPE_OBJECT = 3, -}; - -// Inspired from capstone -enum ARCHITECTURES { - ARCH_NONE = 0, - ARCH_ARM = 1, - ARCH_ARM64 = 2, - ARCH_MIPS = 3, - ARCH_X86 = 4, - ARCH_PPC = 5, - ARCH_SPARC = 6, - ARCH_SYSZ = 7, - ARCH_XCORE = 8, - ARCH_INTEL = 9, - ARCH_RISCV = 10, -}; - -enum MODES { - MODE_NONE = 0, - MODE_16 = 1, - MODE_32 = 2, - MODE_64 = 3, - MODE_ARM = 4, - MODE_THUMB = 5, - MODE_MCLASS = 6, - MODE_MICRO = 7, - MODE_MIPS3 = 8, - MODE_MIPS32R6 = 9, - MODE_MIPSGP64 = 10, - MODE_V7 = 11, - MODE_V8 = 12, - MODE_V9 = 13, - MODE_MIPS32 = 14, - MODE_MIPS64 = 15, -}; - -enum ENDIANNESS { - ENDIAN_NONE = 0, - ENDIAN_BIG = 1, - ENDIAN_LITTLE = 2, -}; - - - - - -} // namespace LIEF -#endif diff --git a/vendor/lief/include/LIEF/Abstract/hash.hpp b/vendor/lief/include/LIEF/Abstract/hash.hpp index 8078996..8868272 100644 --- a/vendor/lief/include/LIEF/Abstract/hash.hpp +++ b/vendor/lief/include/LIEF/Abstract/hash.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,32 +13,35 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_HASH_H_ -#define LIEF_ABSTRACT_HASH_H_ +#ifndef LIEF_ABSTRACT_HASH_H +#define LIEF_ABSTRACT_HASH_H -#include "LIEF/visibility.h" #include "LIEF/hash.hpp" -#include "LIEF/Abstract.hpp" +#include "LIEF/visibility.h" namespace LIEF { +class Binary; +class Header; +class Relocation; +class Object; class LIEF_API AbstractHash : public LIEF::Hash { public: - static size_t hash(const Object& obj); + static LIEF::Hash::value_type hash(const Object& obj); public: using LIEF::Hash::Hash; using LIEF::Hash::visit; public: - void visit(const Binary& binary) override; - void visit(const Header& header) override; - void visit(const Section& section) override; - void visit(const Symbol& symbol) override; + void visit(const Binary& binary) override; + void visit(const Header& header) override; + void visit(const Section& section) override; + void visit(const Symbol& symbol) override; void visit(const Relocation& relocation) override; - void visit(const Function& function) override; + void visit(const Function& function) override; - virtual ~AbstractHash(); + ~AbstractHash() override; }; } diff --git a/vendor/lief/include/LIEF/Abstract/json.hpp b/vendor/lief/include/LIEF/Abstract/json.hpp index db0de88..c133c1b 100644 --- a/vendor/lief/include/LIEF/Abstract/json.hpp +++ b/vendor/lief/include/LIEF/Abstract/json.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,8 +13,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_ABSTRACT_JSON_H_ -#define LIEF_ABSTRACT_JSON_H_ +#ifndef LIEF_ABSTRACT_JSON_H +#define LIEF_ABSTRACT_JSON_H #include "LIEF/visibility.h" #include @@ -26,5 +26,4 @@ LIEF_API std::string to_json_from_abstract(const Object& v); } -#endif // LIEF_JSON_SUPPORT - +#endif diff --git a/vendor/lief/include/LIEF/BinaryStream/ASN1Reader.hpp b/vendor/lief/include/LIEF/BinaryStream/ASN1Reader.hpp new file mode 100644 index 0000000..d5c2b7d --- /dev/null +++ b/vendor/lief/include/LIEF/BinaryStream/ASN1Reader.hpp @@ -0,0 +1,71 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_ASN1_READER_H +#define LIEF_ASN1_READER_H + +#include +#include +#include +#include + +#include "LIEF/errors.hpp" + +struct mbedtls_x509_crt; +struct mbedtls_x509_time; + +namespace LIEF { +class BinaryStream; + +class ASN1Reader { + public: + ASN1Reader() = delete; + + ASN1Reader(BinaryStream& stream) : + stream_(stream) {} + + ASN1Reader(const ASN1Reader&) = delete; + ASN1Reader& operator=(const ASN1Reader&) = delete; + + + result is_tag(int tag); + + result read_tag(int tag); + result read_len(); + result read_alg(); + result read_oid(); + result read_bool(); + result read_int(); + result read_int64(); + result> read_large_int(); + + result> read_bitstring(); + result> read_octet_string(); + result read_utf8_string(); + result> read_cert(); + result x509_read_names(); + result> x509_read_serial(); + result> x509_read_time(); + + std::string get_str_tag(); + + static std::string tag2str(int tag); + + private: + BinaryStream& stream_; +}; + +} +#endif diff --git a/vendor/lief/include/LIEF/BinaryStream/BinaryStream.hpp b/vendor/lief/include/LIEF/BinaryStream/BinaryStream.hpp index acfcf98..3f9c237 100644 --- a/vendor/lief/include/LIEF/BinaryStream/BinaryStream.hpp +++ b/vendor/lief/include/LIEF/BinaryStream/BinaryStream.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,90 +13,118 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_BINARY_STREAM_H_ -#define LIEF_BINARY_STREAM_H_ +#ifndef LIEF_BINARY_STREAM_H +#define LIEF_BINARY_STREAM_H +#include #include -#include -#include -#include +#include +#include #include -#include -#include +#include -#include "LIEF/BinaryStream/Convert.hpp" +#include "LIEF/endianness_support.hpp" #include "LIEF/errors.hpp" - -struct mbedtls_x509_crt; -struct mbedtls_x509_time; +#include "LIEF/visibility.h" namespace LIEF { +class ASN1Reader; +class Binary; - -//! Class that is used to a read stream of data from different sources -class BinaryStream { +/// Class that is used to a read stream of data from different sources +class LIEF_API BinaryStream { public: + friend class ASN1Reader; + enum class STREAM_TYPE { UNKNOWN = 0, VECTOR, MEMORY, SPAN, FILE, + DUMP, ELF_DATA_HANDLER, }; - BinaryStream(); - virtual ~BinaryStream(); + BinaryStream(STREAM_TYPE type) : + stype_(type) {} + virtual ~BinaryStream() = default; virtual uint64_t size() const = 0; - inline STREAM_TYPE type() const { + STREAM_TYPE type() const { return stype_; } - result read_uleb128() const; - result read_sleb128() const; + bool is_memory_stream() const { + return type() == STREAM_TYPE::MEMORY; + } + + bool is_dump_stream() const { + return type() == STREAM_TYPE::DUMP; + } + + bool is_memory_view() const { + return is_memory_stream() || is_dump_stream(); + } + + const BinaryStream& skip_uleb128() const LIEF_LIFETIMEBOUND { + static_cast(read_uleb128()); + return *this; + } + + const BinaryStream& skip_sleb128() const LIEF_LIFETIMEBOUND { + static_cast(read_sleb128()); + return *this; + } + + result read_uleb128(size_t* size = nullptr) const; + result read_sleb128(size_t* size = nullptr) const; result read_dwarf_encoded(uint8_t encoding) const; - result read_string(size_t maxsize = ~static_cast(0)) const; - result peek_string(size_t maxsize = ~static_cast(0)) const; - result peek_string_at(size_t offset, size_t maxsize = ~static_cast(0)) const; + result read_string(size_t maxsize = ~size_t{0}) const; + result peek_string(size_t maxsize = ~size_t{0}) const; + result peek_string_at(size_t offset, + size_t maxsize = ~size_t{0}) const; result read_u16string() const; result peek_u16string() const; - result read_mutf8(size_t maxsize = ~static_cast(0)) const; + result read_mutf8(size_t maxsize = ~size_t{0}) const; result read_u16string(size_t length) const; result peek_u16string(size_t length) const; result peek_u16string_at(size_t offset, size_t length) const; - virtual inline ok_error_t peek_data(std::vector& container, - uint64_t offset, uint64_t size) - { - + virtual ok_error_t peek_data(std::vector& container, uint64_t offset, + uint64_t size, uint64_t virtual_address = 0) { if (size == 0) { return ok(); } // Even though offset + size < ... => offset < ... // the addition could overflow so it's worth checking both - const bool read_ok = offset <= this->size() && (offset + size) <= this->size() - /* Check for an overflow */ - && (static_cast(offset) >= 0 && static_cast(size) >= 0) - && (static_cast(offset + size) >= 0); + const bool read_ok = offset <= this->size() && + (offset + size) <= this->size() + /* Check for an overflow */ + && (int64_t(offset) >= 0 && int64_t(size) >= 0) && + (int64_t(offset + size) >= 0); if (!read_ok) { return make_error_code(lief_errors::read_error); } - container.resize(size); - if (peek_in(container.data(), offset, size)) { - return ok(); + + if (container.size() < size) { + std::vector buffer(size); + const ok_error_t res = peek_in(buffer.data(), offset, size, virtual_address); + container = std::move(buffer); + return res; } - return make_error_code(lief_errors::read_error); + + return peek_in(container.data(), offset, size, virtual_address); } - virtual inline ok_error_t read_data(std::vector& container, uint64_t size) { + virtual ok_error_t read_data(std::vector& container, uint64_t size) { if (!peek_data(container, pos(), size)) { return make_error_code(lief_errors::read_error); } @@ -105,16 +133,124 @@ class BinaryStream { return ok(); } - void setpos(size_t pos) const; - void increment_pos(size_t value) const; - void decrement_pos(size_t value) const; - size_t pos() const; + ok_error_t read_data(std::vector& container) { + const size_t size = this->size() - this->pos(); + return read_data(container, size); + } + + template + ok_error_t read_objects(std::vector& container, uint64_t count) { + if (count == 0) { + return ok(); + } + const size_t size = count * sizeof(T); + auto ret = peek_objects(container, count); + if (!ret) { + return make_error_code(lief_errors::read_error); + } + increment_pos(size); + return ok(); + } + + template + ok_error_t peek_objects(std::vector& container, uint64_t count) { + return peek_objects_at(pos(), container, count); + } + + template + ok_error_t peek_objects_at(uint64_t offset, std::vector& container, + uint64_t count) { + if (count == 0) { + return ok(); + } + const auto current_p = pos(); + setpos(offset); + + const size_t size = count * sizeof(T); + + if (!can_read(offset, size)) { + setpos(current_p); + return make_error_code(lief_errors::read_error); + } + + ok_error_t res = make_error_code(lief_errors::inconsistent); + + if (container.size() < count) { + std::vector buffer(count); + res = peek_in(buffer.data(), pos(), size); + container = std::move(buffer); + } else { + res = peek_in(container.data(), pos(), size); + } + + setpos(current_p); + return res; + } + + void setpos(size_t pos) const { + pos_ = pos; + } + + const BinaryStream& increment_pos(size_t value) const LIEF_LIFETIMEBOUND { + pos_ += value; + return *this; + } + + void decrement_pos(size_t value) const { + if (pos_ > value) { + pos_ -= value; + } else { + pos_ = 0; + } + } - operator bool() const; + size_t pos() const { + return pos_; + } + + bool is_valid() const { + return pos_ < size(); + } + + operator bool() const { + return is_valid(); + } template const T* read_array(size_t size) const; + template + ok_error_t peek_array(std::array& dst) const { + if /*constexpr*/ (N == 0) { + return ok(); + } + // Even though offset + size < ... => offset < ... + // the addition could overflow so it's worth checking both + const bool read_ok = pos_ <= size() && + (pos_ + N) <= size() + /* Check for an overflow */ + && (int64_t(pos_) >= 0 && int64_t(N) >= 0) && + (int64_t(pos_ + N) >= 0); + + if (!read_ok) { + return make_error_code(lief_errors::read_error); + } + if (peek_in(dst.data(), pos_, N)) { + return ok(); + } + return make_error_code(lief_errors::read_error); + } + + template + ok_error_t read_array(std::array& dst) const { + if (!peek_array(dst)) { + return make_error_code(lief_errors::read_error); + } + + increment_pos(N); + return ok(); + } + template result peek() const; @@ -130,72 +266,71 @@ class BinaryStream { template result read() const; + template + const BinaryStream& skip() const LIEF_LIFETIMEBOUND { + static_cast(read()); + return *this; + } + template bool can_read() const; template bool can_read(size_t offset) const; - size_t align(size_t align_on) const; - - /* Functions that are endianness aware */ - template - typename std::enable_if::value, result>::type peek_conv() const; + bool can_read(int64_t offset, int64_t size) const { + return offset < (int64_t)this->size() && + size < ((int64_t)this->size() - offset); + } - template - typename std::enable_if::value, result>::type peek_conv() const; + size_t align(size_t align_on) const; - template - result peek_conv(size_t offset) const; + void set_endian_swap(bool swap) { + endian_swap_ = swap; + } template - result read_conv() const; - - /* Read an array of values and adjust endianness as needed */ - template - std::unique_ptr read_conv_array(size_t size) const; - - template - std::unique_ptr peek_conv_array(size_t offset, size_t size) const; + static bool is_all_zero(const T& buffer) { + const auto* ptr = reinterpret_cast(&buffer); + return std::all_of(ptr, ptr + sizeof(T), [](uint8_t x) { return x == 0; }); + } - template - static T swap_endian(T u); + bool should_swap() const { + return endian_swap_; + } - void set_endian_swap(bool swap); + virtual const uint8_t* p() const { + return nullptr; + } - /* ASN.1 & X509 parsing functions */ - virtual result asn1_read_tag(int tag); - virtual result asn1_read_len(); - virtual result asn1_read_alg(); - virtual result asn1_read_oid(); - virtual result asn1_read_int(); - virtual result> asn1_read_bitstring(); - virtual result> asn1_read_octet_string(); - virtual result> asn1_read_cert(); - virtual result x509_read_names(); - virtual result> x509_read_serial(); - virtual result> x509_read_time(); + virtual uint8_t* start() { + return const_cast(static_cast(this)->start()); + } + virtual uint8_t* p() { + return const_cast(static_cast(this)->p()); + } - template - static bool is_all_zero(const T& buffer) { - const auto* ptr = reinterpret_cast(&buffer); - return std::all_of(ptr, ptr + sizeof(T), - [] (uint8_t x) { return x == 0; }); + virtual uint8_t* end() { + return const_cast(static_cast(this)->end()); } - inline bool should_swap() const { - return endian_swap_; + virtual const uint8_t* start() const { + return nullptr; } - protected: - virtual result read_at(uint64_t offset, uint64_t size) const = 0; - inline virtual ok_error_t peek_in(void* dst, uint64_t offset, uint64_t size) const { - if (auto raw = read_at(offset, size)) { - if (dst == nullptr) { - return make_error_code(lief_errors::read_error); - } + virtual const uint8_t* end() const { + return nullptr; + } + virtual result read_at(uint64_t offset, uint64_t size, + uint64_t virtual_address = 0) const = 0; + virtual ok_error_t peek_in(void* dst, uint64_t offset, uint64_t size, + uint64_t virtual_address = 0) const { + if (dst == nullptr) { + return make_error_code(lief_errors::read_error); + } + if (auto raw = read_at(offset, size, virtual_address)) { const void* ptr = *raw; if (ptr == nullptr) { @@ -207,6 +342,29 @@ class BinaryStream { } return make_error_code(lief_errors::read_error); } + + template + const T* cast() const { + static_assert(std::is_base_of_v, + "Require BinaryStream inheritance"); + if (T::classof(*this)) { + return static_cast(this); + } + return nullptr; + } + + template + T* cast() { + return const_cast(static_cast(this)->cast()); + } + + virtual bool bind_binary(Binary& /*bin*/) { + return false; + } + + protected: + BinaryStream() = default; + mutable size_t pos_ = 0; bool endian_swap_ = false; STREAM_TYPE stype_ = STREAM_TYPE::UNKNOWN; @@ -222,31 +380,82 @@ class ScopedStream { explicit ScopedStream(BinaryStream& stream, uint64_t pos) : pos_{stream.pos()}, - stream_{stream} - { + stream_{stream} { stream_.setpos(pos); } explicit ScopedStream(BinaryStream& stream) : pos_{stream.pos()}, - stream_{stream} - {} + stream_{stream} {} - inline ~ScopedStream() { + ~ScopedStream() { stream_.setpos(pos_); } + BinaryStream* operator->() { + return &stream_; + } + + BinaryStream& operator*() { + return stream_; + } + + const BinaryStream& operator*() const { + return stream_; + } + private: uint64_t pos_ = 0; BinaryStream& stream_; }; +class ToggleEndianness { + public: + ToggleEndianness(const ToggleEndianness&) = delete; + ToggleEndianness& operator=(const ToggleEndianness&) = delete; + + ToggleEndianness(ToggleEndianness&&) = delete; + ToggleEndianness& operator=(ToggleEndianness&&) = delete; + + explicit ToggleEndianness(BinaryStream& stream, bool value) : + endian_swap_(stream.should_swap()), + stream_{stream} { + stream.set_endian_swap(value); + } + + explicit ToggleEndianness(BinaryStream& stream) : + endian_swap_(stream.should_swap()), + stream_{stream} { + stream.set_endian_swap(!stream_.should_swap()); + } + + ~ToggleEndianness() { + stream_.set_endian_swap(endian_swap_); + } + + BinaryStream* operator->() { + return &stream_; + } + + BinaryStream& operator*() { + return stream_; + } + + const BinaryStream& operator*() const { + return stream_; + } + + private: + bool endian_swap_ = false; + BinaryStream& stream_; +}; + template result BinaryStream::read() const { result tmp = this->peek(); if (!tmp) { - return tmp.error(); + return tmp; } this->increment_pos(sizeof(T)); return tmp; @@ -258,6 +467,9 @@ result BinaryStream::peek() const { T ret{}; if (auto res = peek_in(&ret, pos(), sizeof(T))) { setpos(current_p); + if (endian_swap_) { + swap_endian(&ret); + } return ret; } @@ -267,7 +479,7 @@ result BinaryStream::peek() const { template result BinaryStream::peek(size_t offset) const { - size_t saved_offset = this->pos(); + const size_t saved_offset = this->pos(); this->setpos(offset); result r = this->peek(); this->setpos(saved_offset); @@ -286,7 +498,7 @@ const T* BinaryStream::peek_array(size_t size) const { template const T* BinaryStream::peek_array(size_t offset, size_t size) const { - size_t saved_offset = this->pos(); + const size_t saved_offset = this->pos(); this->setpos(offset); const T* r = this->peek_array(size); this->setpos(saved_offset); @@ -317,89 +529,5 @@ const T* BinaryStream::read_array(size_t size) const { return tmp; } - -template -result BinaryStream::read_conv() const { - result tmp = this->peek_conv(); - if (!tmp) { - return tmp.error(); - } - this->increment_pos(sizeof(T)); - return tmp; -} - -template -typename std::enable_if::value, result>::type BinaryStream::peek_conv() const { - T ret; - if (auto res = peek_in(&ret, pos(), sizeof(T))) { - if (endian_swap_) { - return swap_endian(ret); - } - return ret; - } - return make_error_code(lief_errors::read_error); -} - -template -typename std::enable_if::value, result>::type BinaryStream::peek_conv() const { - T ret; - if (auto res = peek_in(&ret, pos(), sizeof(T))) { - if (endian_swap_) { - LIEF::Convert::swap_endian(&ret); - } - return ret; - } - return make_error_code(lief_errors::read_error); -} - - -template -result BinaryStream::peek_conv(size_t offset) const { - size_t saved_offset = this->pos(); - this->setpos(offset); - result r = this->peek_conv(); - this->setpos(saved_offset); - return r; -} - - -template -std::unique_ptr BinaryStream::read_conv_array(size_t size) const { - const T *t = this->read_array(size); - - if (t == nullptr) { - return nullptr; - } - - std::unique_ptr uptr(new T[size]); - - for (size_t i = 0; i < size; i++) { - uptr[i] = t[i]; - if (this->endian_swap_) { - LIEF::Convert::swap_endian(& uptr[i]); - } /* else no conversion, just provide the copied data */ - } - return uptr; -} - - -template -std::unique_ptr BinaryStream::peek_conv_array(size_t offset, size_t size) const { - const T *t = this->peek_array(offset, size); - - if (t == nullptr) { - return nullptr; - } - - std::unique_ptr uptr(new T[size]); - - for (size_t i = 0; i < size; i++) { - uptr[i] = t[i]; - if (this->endian_swap_) { - LIEF::Convert::swap_endian(& uptr[i]); - } /* else no conversion, just provide the copied data */ - } - return uptr; -} } #endif diff --git a/vendor/lief/include/LIEF/BinaryStream/Convert.hpp b/vendor/lief/include/LIEF/BinaryStream/Convert.hpp deleted file mode 100644 index a428d7e..0000000 --- a/vendor/lief/include/LIEF/BinaryStream/Convert.hpp +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2021 - 2022 R. Thomas - * Copyright 2021 - 2022 Quarkslab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef LIEF_CONVERT_H_ -#define LIEF_CONVERT_H_ -namespace LIEF { -namespace Convert { - -template -void swap_endian(T*); - -} -} - -#endif // LIEF_CONVERT_H_ diff --git a/vendor/lief/include/LIEF/BinaryStream/DumpStream.hpp b/vendor/lief/include/LIEF/BinaryStream/DumpStream.hpp new file mode 100644 index 0000000..dd56d09 --- /dev/null +++ b/vendor/lief/include/LIEF/BinaryStream/DumpStream.hpp @@ -0,0 +1,97 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DUMP_STREAM_H +#define LIEF_DUMP_STREAM_H + +#include +#include + +#include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/visibility.h" + +namespace LIEF { +class Binary; + +/// This stream interface provides facilities to parse a dumped binary. +/// +/// A dump is a contiguous capture of a process memory that starts at a given +/// base address. This stream owns (or weakly references) +/// another BinaryStream that holds the raw dump and translates file offsets +/// into dump offsets according to this base address and the binary layout. +class LIEF_API DumpStream : public BinaryStream { + public: + DumpStream() = delete; + DumpStream(uintptr_t base_address, BinaryStream& ref) : + BinaryStream(BinaryStream::STREAM_TYPE::DUMP), + baseaddr_(base_address), + ref_(&ref) {} + + DumpStream(uintptr_t base_address, std::unique_ptr owned) : + BinaryStream(BinaryStream::STREAM_TYPE::DUMP), + baseaddr_(base_address), + owned_(std::move(owned)), + ref_(owned_.get()) {} + + DumpStream(const DumpStream&) = delete; + DumpStream& operator=(const DumpStream&) = delete; + + DumpStream(DumpStream&&) noexcept = default; + DumpStream& operator=(DumpStream&&) noexcept = default; + + uintptr_t base_address() const { + return baseaddr_; + } + + Binary* binary() LIEF_LIFETIMEBOUND { + return binary_; + } + + uint64_t size() const override { + return ref_->size(); + } + + bool bind_binary(Binary& bin) override { + binary_ = &bin; + return true; + } + + std::vector content() const; + + result read_at(uint64_t /*offset*/, uint64_t /*size*/, + uint64_t /*virtual_address*/ = 0) const override { + return make_error_code(lief_errors::not_supported); + } + + ok_error_t peek_in(void* dst, uint64_t offset, uint64_t size, + uint64_t virtual_address = 0) const override; + + ~DumpStream() override = default; + + static bool classof(const BinaryStream& stream) { + return stream.type() == BinaryStream::STREAM_TYPE::DUMP; + } + + protected: + uintptr_t baseaddr_ = 0; + Binary* binary_ = nullptr; + std::unique_ptr owned_; + BinaryStream* ref_ = nullptr; +}; +} + +#endif diff --git a/vendor/lief/include/LIEF/BinaryStream/FileStream.hpp b/vendor/lief/include/LIEF/BinaryStream/FileStream.hpp index fb3da0f..b3e62b6 100644 --- a/vendor/lief/include/LIEF/BinaryStream/FileStream.hpp +++ b/vendor/lief/include/LIEF/BinaryStream/FileStream.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -16,41 +16,47 @@ #ifndef LIEF_FILE_STREAM_H #define LIEF_FILE_STREAM_H -#include -#include +#include #include +#include -#include "LIEF/errors.hpp" #include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/visibility.h" + namespace LIEF { -//! Stream interface over a std::ifstream -class FileStream : public BinaryStream { +/// Stream interface over a `std::ifstream` +class LIEF_API FileStream : public BinaryStream { public: - static result from_file(const std::string& file); - FileStream(std::ifstream fs, uint64_t size); + static result from_file(std::string_view file); + FileStream(std::ifstream fs, uint64_t size) : + BinaryStream(STREAM_TYPE::FILE), + ifs_(std::move(fs)), + size_(size) {} FileStream() = delete; - // VectorStream should not be copyable for performances reasons FileStream(const FileStream&) = delete; FileStream& operator=(const FileStream&) = delete; - FileStream(FileStream&& other); - FileStream& operator=(FileStream&& other); + FileStream(FileStream&& other) noexcept = default; + FileStream& operator=(FileStream&& other) noexcept = default; - inline uint64_t size() const override { + uint64_t size() const override { return size_; } std::vector content() const; - ~FileStream() override; + ~FileStream() override = default; - static bool classof(const BinaryStream& stream); + static bool classof(const BinaryStream& stream) { + return stream.type() == STREAM_TYPE::FILE; + } - protected: - inline ok_error_t peek_in(void* dst, uint64_t offset, uint64_t size) const override { - if (offset > size_ || offset + size > size_) { + ok_error_t peek_in(void* dst, uint64_t offset, uint64_t size, + uint64_t /* virtual_address */ = 0) const override { + if (offset > size_ || size > size_ - offset) { return make_error_code(lief_errors::read_error); } const auto pos = ifs_.tellg(); @@ -59,9 +65,12 @@ class FileStream : public BinaryStream { ifs_.seekg(pos); return ok(); } - inline result read_at(uint64_t, uint64_t) const override { + + result read_at(uint64_t, uint64_t, uint64_t) const override { return make_error_code(lief_errors::not_supported); } + + protected: mutable std::ifstream ifs_; uint64_t size_ = 0; }; diff --git a/vendor/lief/include/LIEF/BinaryStream/MemoryStream.hpp b/vendor/lief/include/LIEF/BinaryStream/MemoryStream.hpp index 443782e..7bff73a 100644 --- a/vendor/lief/include/LIEF/BinaryStream/MemoryStream.hpp +++ b/vendor/lief/include/LIEF/BinaryStream/MemoryStream.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -16,48 +16,71 @@ #ifndef LIEF_MEMORY_STREAM_H #define LIEF_MEMORY_STREAM_H -#include -#include +#include #include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/visibility.h" namespace LIEF { class Binary; -class MemoryStream : public BinaryStream { +class LIEF_API MemoryStream : public BinaryStream { public: + using BinaryStream::end; + using BinaryStream::p; + using BinaryStream::start; + MemoryStream() = delete; MemoryStream(uintptr_t base_address); - MemoryStream(uintptr_t base_address, uint64_t size); + MemoryStream(uintptr_t base_address, uint64_t size) : + BinaryStream(BinaryStream::STREAM_TYPE::MEMORY), + baseaddr_(base_address), + size_(size) {} MemoryStream(const MemoryStream&) = delete; MemoryStream& operator=(const MemoryStream&) = delete; - MemoryStream(MemoryStream&&); - MemoryStream& operator=(MemoryStream&&); + MemoryStream(MemoryStream&&) noexcept = default; + MemoryStream& operator=(MemoryStream&&) noexcept = default; + + uintptr_t base_address() const { + return baseaddr_; + } + + const uint8_t* p() const override { + return start() + pos(); + } + + const uint8_t* start() const override { + return reinterpret_cast(baseaddr_); + } - inline uintptr_t base_address() const { - return this->baseaddr_; + const uint8_t* end() const override { + return start() + size_; } - inline uint64_t end() const { - return this->baseaddr_ + this->size_; + Binary* binary() { + return binary_; } - inline void binary(Binary& bin) { - this->binary_ = &bin; + uint64_t size() const override { + return size_; } - inline Binary* binary() { - return this->binary_; + bool bind_binary(Binary& bin) override { + binary_ = &bin; + return true; } - uint64_t size() const override; - ~MemoryStream() override; + ~MemoryStream() override = default; - static bool classof(const BinaryStream& stream); + static bool classof(const BinaryStream& stream) { + return stream.type() == BinaryStream::STREAM_TYPE::MEMORY; + } protected: - result read_at(uint64_t offset, uint64_t size) const override; + result read_at(uint64_t offset, uint64_t size, + uint64_t va) const override; uintptr_t baseaddr_ = 0; uint64_t size_ = 0; Binary* binary_ = nullptr; diff --git a/vendor/lief/include/LIEF/BinaryStream/SpanStream.hpp b/vendor/lief/include/LIEF/BinaryStream/SpanStream.hpp index 318b438..ed26a89 100644 --- a/vendor/lief/include/LIEF/BinaryStream/SpanStream.hpp +++ b/vendor/lief/include/LIEF/BinaryStream/SpanStream.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -16,41 +16,109 @@ #ifndef LIEF_SPAN_STREAM_H #define LIEF_SPAN_STREAM_H -#include +#include +#include +#include +#include +#include +#include "LIEF/BinaryStream/BinaryStream.hpp" #include "LIEF/errors.hpp" #include "LIEF/span.hpp" -#include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/visibility.h" namespace LIEF { -class SpanStream : public BinaryStream { +class VectorStream; +class LIEF_API SpanStream : public BinaryStream { public: - static result from_vector(const std::vector& data); - SpanStream(span data); - SpanStream(span data); - SpanStream(const std::vector& data); + using BinaryStream::end; + using BinaryStream::p; + using BinaryStream::start; + + static result from_vector(const std::vector& data) { + return SpanStream(data); + } + + template + static result from_array(const std::array& data) { + return SpanStream(data.data(), N); + } + + SpanStream(span data) : + SpanStream(data.data(), data.size()) {} + + SpanStream(span data) : + SpanStream(data.data(), data.size()) {} + + SpanStream(const uint8_t* p, size_t size) : + BinaryStream(BinaryStream::STREAM_TYPE::SPAN), + data_{p, p + size} {} + + SpanStream(const std::vector& data) : + SpanStream(data.data(), data.size()) {} + + std::unique_ptr clone() const { + return std::make_unique(*this); + } + SpanStream() = delete; - SpanStream(const SpanStream&) = delete; - SpanStream& operator=(const SpanStream&) = delete; + SpanStream(const SpanStream& other) = default; + SpanStream& operator=(const SpanStream& other) = default; - SpanStream(SpanStream&& other); - SpanStream& operator=(SpanStream&& other); + SpanStream(SpanStream&& other) noexcept = default; + SpanStream& operator=(SpanStream&& other) noexcept = default; - inline uint64_t size() const override { + uint64_t size() const override { return data_.size(); } - std::vector content() const; + const uint8_t* p() const override { + return data_.data() + this->pos(); + } - result slice(size_t offset, size_t size) const; - result slice(size_t offset) const; + const uint8_t* start() const override { + return data_.data(); + } - static bool classof(const BinaryStream& stream); - ~SpanStream() override; + const uint8_t* end() const override { + return data_.data() + size(); + } + + std::vector content() const { + return {data_.begin(), data_.end()}; + } + + result slice(size_t offset, size_t size) const { + if (offset > data_.size() || size > data_.size() - offset) { + return make_error_code(lief_errors::read_out_of_bound); + } + return data_.subspan(offset, size); + } + result slice(size_t offset) const { + if (offset > data_.size()) { + return make_error_code(lief_errors::read_out_of_bound); + } + return data_.subspan(offset, data_.size() - offset); + } + + std::unique_ptr to_vector() const; + + static bool classof(const BinaryStream& stream) { + return stream.type() == BinaryStream::STREAM_TYPE::SPAN; + } + + ~SpanStream() override = default; protected: - result read_at(uint64_t offset, uint64_t size) const override; + result read_at(uint64_t offset, uint64_t size, + uint64_t /*va*/) const override { + const uint64_t stream_size = this->size(); + if (offset > stream_size || size > stream_size - offset) { + return make_error_code(lief_errors::read_error); + } + return data_.data() + offset; + } span data_; }; } diff --git a/vendor/lief/include/LIEF/BinaryStream/VectorStream.hpp b/vendor/lief/include/LIEF/BinaryStream/VectorStream.hpp index 49c69ac..f7e06ef 100644 --- a/vendor/lief/include/LIEF/BinaryStream/VectorStream.hpp +++ b/vendor/lief/include/LIEF/BinaryStream/VectorStream.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,19 +13,30 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef VECTOR_BINARY_STREAM_H -#define VECTOR_BINARY_STREAM_H +#ifndef LIEF_VECTOR_STREAM_H +#define LIEF_VECTOR_STREAM_H +#include +#include #include -#include -#include "LIEF/errors.hpp" #include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/visibility.h" + namespace LIEF { -class VectorStream : public BinaryStream { +class SpanStream; +class LIEF_API VectorStream : public BinaryStream { public: - static result from_file(const std::string& file); - VectorStream(std::vector data); + using BinaryStream::end; + using BinaryStream::p; + using BinaryStream::start; + + static result from_file(std::string_view file); + VectorStream(std::vector data) : + BinaryStream(BinaryStream::STREAM_TYPE::VECTOR), + binary_(std::move(data)), + size_(binary_.size()) {} VectorStream() = delete; @@ -33,60 +44,51 @@ class VectorStream : public BinaryStream { VectorStream(const VectorStream&) = delete; VectorStream& operator=(const VectorStream&) = delete; - VectorStream(VectorStream&& other); - VectorStream& operator=(VectorStream&& other); + VectorStream(VectorStream&& other) noexcept = default; + VectorStream& operator=(VectorStream&& other) noexcept = default; - inline uint64_t size() const override { + uint64_t size() const override { return size_; } - const std::vector& content() const; + const std::vector& content() const { + return binary_; + } - inline std::vector&& move_content() { + std::vector&& move_content() { size_ = 0; return std::move(binary_); } - inline uint8_t* p() { - return this->binary_.data() + this->pos(); - } - - inline const uint8_t* p() const { + const uint8_t* p() const override { return this->binary_.data() + this->pos(); } - inline uint8_t* start() { + const uint8_t* start() const override { return this->binary_.data(); } - inline const uint8_t* start() const { - return this->binary_.data(); - } - - inline uint8_t* end() { + const uint8_t* end() const override { return this->binary_.data() + this->binary_.size(); } - inline const uint8_t* end() const { - return this->binary_.data() + this->binary_.size(); - } - result asn1_read_tag(int tag) override; - result asn1_read_len() override; - result asn1_read_alg() override; - result asn1_read_oid() override; - result asn1_read_int() override; - result> asn1_read_bitstring() override; - result> asn1_read_octet_string() override; - result> asn1_read_cert() override; - result x509_read_names() override; - result> x509_read_serial() override; - result> x509_read_time() override; + std::unique_ptr slice(uint32_t offset, size_t size) const; + std::unique_ptr slice(uint32_t offset) const; - static bool classof(const BinaryStream& stream); + static bool classof(const BinaryStream& stream) { + return stream.type() == STREAM_TYPE::VECTOR; + } protected: - result read_at(uint64_t offset, uint64_t size) const override; + result read_at(uint64_t offset, uint64_t size, + uint64_t /*va*/) const override { + const uint64_t stream_size = this->size(); + if (offset > stream_size || size > stream_size - offset) { + return make_error_code(lief_errors::read_error); + } + return binary_.data() + offset; + } std::vector binary_; uint64_t size_ = 0; // Original size without alignment }; diff --git a/vendor/lief/include/LIEF/COFF.hpp b/vendor/lief/include/LIEF/COFF.hpp new file mode 100644 index 0000000..d458c69 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF.hpp @@ -0,0 +1,44 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_H +#define LIEF_COFF_H +// IWYU pragma: begin_exports +#include "LIEF/config.h" + +#if defined(LIEF_COFF_SUPPORT) + #include "LIEF/COFF/BigObjHeader.hpp" + #include "LIEF/COFF/Binary.hpp" + #include "LIEF/COFF/Header.hpp" + #include "LIEF/COFF/Parser.hpp" + #include "LIEF/COFF/ParserConfig.hpp" + #include "LIEF/COFF/RegularHeader.hpp" + #include "LIEF/COFF/Relocation.hpp" + #include "LIEF/COFF/Section.hpp" + #include "LIEF/COFF/String.hpp" + #include "LIEF/COFF/Symbol.hpp" + #include "LIEF/COFF/utils.hpp" + + #include "LIEF/COFF/AuxiliarySymbol.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp" + #include "LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp" +// IWYU pragma: end_exports +#endif + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbol.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbol.hpp new file mode 100644 index 0000000..ca58338 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbol.hpp @@ -0,0 +1,126 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_SYMBOL_H +#define LIEF_COFF_AUXILIARY_SYMBOL_H + +#include +#include +#include + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/span.hpp" +#include "LIEF/visibility.h" + +namespace LIEF { +class BinaryStream; + +namespace COFF { +class Symbol; + +/// Class that represents an auxiliary symbol. +/// +/// An auxiliary symbol has the same size as a regular LIEF::PE::Symbol (18 +/// bytes) but its content depends on the parent symbol. +class LIEF_API AuxiliarySymbol { + public: + AuxiliarySymbol() = default; + AuxiliarySymbol(std::vector payload) : + payload_(std::move(payload)) {} + AuxiliarySymbol(const AuxiliarySymbol&) = default; + AuxiliarySymbol& operator=(const AuxiliarySymbol&) = default; + + AuxiliarySymbol(AuxiliarySymbol&&) = default; + AuxiliarySymbol& operator=(AuxiliarySymbol&&) = default; + + LIEF_LOCAL static std::unique_ptr + parse(Symbol& sym, std::vector payload); + + virtual std::unique_ptr clone() const { + return std::make_unique(*this); + } + + /// Type discriminator for the subclasses + enum class TYPE { + UNKNOWN = 0, + CLR_TOKEN, + /// Auxiliary Format 1 from the PE-COFF documentation + FUNC_DEF, + + /// Auxiliary Format 2: .bf and .ef Symbols from the PE-COFF documentation + BF_AND_EF, + + /// Auxiliary Format 3: Weak Externals from the PE-COFF documentation + WEAK_EXTERNAL, + + /// Auxiliary Format 4: Files from the PE-COFF documentation + FILE, + + /// Auxiliary Format 5: Section Definitions from the PE-COFF documentation + SEC_DEF, + }; + + AuxiliarySymbol(TYPE ty) : + type_(ty) {} + + static TYPE get_aux_type(const Symbol& sym); + + TYPE type() const { + return type_; + } + + /// For unknown type **only**, return the raw representation of this symbol + span payload() const LIEF_LIFETIMEBOUND { + return payload_; + } + + span payload() LIEF_LIFETIMEBOUND { + return payload_; + } + + virtual std::string to_string() const; + + virtual ~AuxiliarySymbol() = default; + + /// Helper to **downcast** an AuxiliarySymbol into a concrete implementation + template + const T* as() const { + static_assert(std::is_base_of_v, + "Require AuxiliarySymbol inheritance"); + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + template + T* as() { + return const_cast(static_cast(this)->as()); + } + + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const AuxiliarySymbol& aux) { + os << aux.to_string(); + return os; + } + + protected: + TYPE type_ = TYPE::UNKNOWN; + std::vector payload_; +}; + +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp new file mode 100644 index 0000000..dc0b90d --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryCLRToken.hpp @@ -0,0 +1,106 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_CLR_TOKEN_H +#define LIEF_COFF_AUXILIARY_CLR_TOKEN_H + +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { +class Symbol; +class Parser; + +/// Auxiliary symbol associated with the `CLR_TOKEN` storage class +class LIEF_API AuxiliaryCLRToken : public AuxiliarySymbol { + public: + friend class Parser; + + LIEF_LOCAL static std::unique_ptr + parse(const std::vector& payload); + + AuxiliaryCLRToken() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::CLR_TOKEN) {} + + AuxiliaryCLRToken(uint8_t aux_type, uint8_t reserved, uint32_t symbol_idx, + std::vector rgb_reserved) : + AuxiliarySymbol(AuxiliarySymbol::TYPE::CLR_TOKEN), + aux_type_(aux_type), + reserved_(reserved), + symbol_idx_(symbol_idx), + rgb_reserved_(std::move(rgb_reserved)) {} + + AuxiliaryCLRToken(const AuxiliaryCLRToken&) = default; + AuxiliaryCLRToken& operator=(const AuxiliaryCLRToken&) = default; + + AuxiliaryCLRToken(AuxiliaryCLRToken&&) = default; + AuxiliaryCLRToken& operator=(AuxiliaryCLRToken&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + /// `IMAGE_AUX_SYMBOL_TYPE` which should be `IMAGE_AUX_SYMBOL_TYPE_TOKEN_DEF` (1) + uint8_t aux_type() const { + return aux_type_; + } + + /// Reserved value (should be 0) + uint8_t reserved() const { + return aux_type_; + } + + /// Index in the symbol table + uint32_t symbol_idx() const { + return symbol_idx_; + } + + /// Symbol referenced by symbol_idx() (if resolved) + const Symbol* symbol() const { + return sym_; + } + + Symbol* symbol() { + return sym_; + } + + /// Reserved (padding) values. Should be 0 + span rgb_reserved() const LIEF_LIFETIMEBOUND { + return rgb_reserved_; + } + + std::string to_string() const override; + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::CLR_TOKEN; + } + + ~AuxiliaryCLRToken() override = default; + + private: + uint8_t aux_type_ = 0; + uint8_t reserved_ = 0; + uint32_t symbol_idx_ = 0; + std::vector rgb_reserved_; + Symbol* sym_ = nullptr; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp new file mode 100644 index 0000000..db7b69b --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFile.hpp @@ -0,0 +1,86 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_PE_AUXILIARY_FILE_H +#define LIEF_PE_AUXILIARY_FILE_H + +#include +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// This auxiliary symbol represents a filename (auxiliary format 4) +/// +/// The Symbol::name itself should start with `.file`, and this auxiliary record +/// gives the name of a source-code file. +/// +/// Reference: +/// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-4-files +class LIEF_API AuxiliaryFile : public AuxiliarySymbol { + public: + LIEF_LOCAL static std::unique_ptr + parse(const std::vector& payload); + + AuxiliaryFile() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::FILE) {} + + AuxiliaryFile(std::string file) : + AuxiliarySymbol(AuxiliarySymbol::TYPE::FILE), + filename_(std::move(file)) {} + + AuxiliaryFile(const AuxiliaryFile&) = default; + AuxiliaryFile& operator=(const AuxiliaryFile&) = default; + + AuxiliaryFile(AuxiliaryFile&&) = default; + AuxiliaryFile& operator=(AuxiliaryFile&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + /// The associated filename + std::string_view filename() const LIEF_LIFETIMEBOUND { + return filename_; + } + + AuxiliaryFile& filename(std::string file) { + filename_ = std::move(file); + return *this; + } + + std::string to_string() const override { + std::string out = "AuxiliaryFile {\n"; + out += " " + filename_ + "\n}"; + return out; + } + + ~AuxiliaryFile() override = default; + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::FILE; + } + + protected: + std::string filename_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp new file mode 100644 index 0000000..179272b --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryFunctionDefinition.hpp @@ -0,0 +1,109 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_FUNCTION_DEF_H +#define LIEF_COFF_AUXILIARY_FUNCTION_DEF_H + +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// This auxiliary symbols marks the beginning of a function definition. +/// +/// Reference: +/// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-1-function-definitions +class LIEF_API AuxiliaryFunctionDefinition : public AuxiliarySymbol { + public: + LIEF_LOCAL static std::unique_ptr + parse(const std::vector& payload); + + AuxiliaryFunctionDefinition() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::FUNC_DEF) {} + + AuxiliaryFunctionDefinition(uint32_t tagidx, uint32_t totalsz, uint32_t ptr_line, + uint32_t ptr_next_func, uint16_t padding) : + AuxiliarySymbol(AuxiliarySymbol::TYPE::FUNC_DEF), + tag_index_(tagidx), + total_size_(totalsz), + ptr_to_linenb_(ptr_line), + ptr_to_next_func_(ptr_next_func), + padding_(padding) {} + + AuxiliaryFunctionDefinition(const AuxiliaryFunctionDefinition&) = default; + AuxiliaryFunctionDefinition& + operator=(const AuxiliaryFunctionDefinition&) = default; + + AuxiliaryFunctionDefinition(AuxiliaryFunctionDefinition&&) = default; + AuxiliaryFunctionDefinition& operator=(AuxiliaryFunctionDefinition&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + /// The symbol-table index of the corresponding `.bf` (begin function) + /// symbol record. + uint32_t tag_index() const { + return tag_index_; + } + + /// The size of the executable code for the function itself. + /// + /// If the function is in its own section, the `SizeOfRawData` in the section + /// header is greater or equal to this field, depending on alignment + /// considerations. + uint32_t total_size() const { + return total_size_; + } + + /// The file offset of the first COFF line-number entry for the function, + /// or zero if none exists (deprecated) + uint32_t ptr_to_line_number() const { + return ptr_to_linenb_; + } + + /// The symbol-table index of the record for the next function. If the function + /// is the last in the symbol table, this field is set to zero. + uint32_t ptr_to_next_func() const { + return ptr_to_next_func_; + } + + /// Padding value (should be 0) + uint16_t padding() const { + return padding_; + } + + std::string to_string() const override; + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::FUNC_DEF; + } + + ~AuxiliaryFunctionDefinition() override = default; + + private: + uint32_t tag_index_ = 0; + uint32_t total_size_ = 0; + uint32_t ptr_to_linenb_ = 0; + uint32_t ptr_to_next_func_ = 0; + uint16_t padding_ = 0; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp new file mode 100644 index 0000000..8689f60 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp @@ -0,0 +1,166 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_SEC_DEF_H +#define LIEF_COFF_AUXILIARY_SEC_DEF_H + +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// This auxiliary symbol exposes information about the associated section. +/// +/// It **duplicates** some information that are provided in the section header +class LIEF_API AuxiliarySectionDefinition : public AuxiliarySymbol { + public: + LIEF_LOCAL static std::unique_ptr + parse(const std::vector& payload); + + AuxiliarySectionDefinition() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::SEC_DEF) {} + + AuxiliarySectionDefinition(uint32_t length, uint16_t nb_relocs, + uint16_t nb_lines, uint32_t checksum, + uint32_t sec_idx, uint8_t selection, + uint8_t reserved) : + AuxiliarySymbol(AuxiliarySymbol::TYPE::SEC_DEF), + length_(length), + nb_relocs_(nb_relocs), + nb_lines_(nb_lines), + checksum_(checksum), + sec_idx_(sec_idx), + selection_((COMDAT_SELECTION)selection), + reserved_(reserved) {} + + AuxiliarySectionDefinition(const AuxiliarySectionDefinition&) = default; + AuxiliarySectionDefinition& + operator=(const AuxiliarySectionDefinition&) = default; + + AuxiliarySectionDefinition(AuxiliarySectionDefinition&&) = default; + AuxiliarySectionDefinition& operator=(AuxiliarySectionDefinition&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + /// Values for the AuxiliarySectionDefinition::selection attribute + /// + /// See: + /// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#comdat-sections-object-only + enum class COMDAT_SELECTION : uint8_t { + NONE = 0, + + /// If this symbol is already defined, the linker issues a `multiply defined + /// symbol` error. + NODUPLICATES = 1, + + /// Any section that defines the same COMDAT symbol can be linked; the rest + /// are removed. + ANY, + + /// The linker chooses an arbitrary section among the definitions for this + /// symbol. If all definitions are not the same size, a `multiply defined + /// symbol` error is issued. + SAME_SIZE, + + /// The linker chooses an arbitrary section among the definitions for this + /// symbol. If all definitions do not match exactly, a + /// `multiply defined symbol` error is issued. + EXACT_MATCH, + + /// The section is linked if a certain other COMDAT section is linked. + /// This other section is indicated by the Number field of the auxiliary + /// symbol record for the section definition. This setting is useful for + /// definitions that have components in multiple sections + /// (for example, code in one and data in another), but where all must be + /// linked or discarded as a set. The other section this section is + /// associated with must be a COMDAT section, which can be another + /// associative COMDAT section. An associative COMDAT section's section + /// association chain can't form a loop. The section association chain must + /// eventually come to a COMDAT section that doesn't have + /// COMDAT_SELECTION::ASSOCIATIVE set. + ASSOCIATIVE, + + /// The linker chooses the largest definition from among all the definitions + /// for this symbol. If multiple definitions have this size, the choice + /// between them is arbitrary. + LARGEST, + }; + + /// The size of section data. The same as `SizeOfRawData` in the section header. + uint32_t length() const { + return length_; + } + + /// The number of relocation entries for the section. + uint16_t nb_relocs() const { + return nb_relocs_; + } + + /// The number of line-number entries for the section. + uint16_t nb_line_numbers() const { + return nb_lines_; + } + + /// The checksum for communal data. It is applicable if the + /// `IMAGE_SCN_LNK_COMDAT` flag is set in the section header. + uint32_t checksum() const { + return checksum_; + } + + /// One-based index into the section table for the associated section. + /// This is used when the COMDAT selection setting is 5. + uint32_t section_idx() const { + return sec_idx_; + } + + /// The COMDAT selection number. This is applicable if the section is a + /// COMDAT section. + COMDAT_SELECTION selection() const { + return selection_; + } + + /// Reserved value (should be 0) + uint8_t reserved() const { + return reserved_; + } + + std::string to_string() const override; + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::SEC_DEF; + } + + ~AuxiliarySectionDefinition() override = default; + + private: + uint32_t length_ = 0; + uint16_t nb_relocs_ = 0; + uint16_t nb_lines_ = 0; + uint32_t checksum_ = 0; + uint32_t sec_idx_ = 0; + COMDAT_SELECTION selection_ = COMDAT_SELECTION::NONE; + uint8_t reserved_ = 0; +}; + +LIEF_API const char* to_string(AuxiliarySectionDefinition::COMDAT_SELECTION e); + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp new file mode 100644 index 0000000..d38957e --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliaryWeakExternal.hpp @@ -0,0 +1,115 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_WEAK_EXTERNAL_H +#define LIEF_COFF_AUXILIARY_WEAK_EXTERNAL_H + +#include +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// "Weak externals" are a mechanism for object files that allows flexibility at +/// link time. A module can contain an unresolved external symbol (`sym1`), but +/// it can also include an auxiliary record that indicates that if `sym1` is not +/// present at link time, another external symbol (`sym2`) is used to resolve +/// references instead. +/// +/// If a definition of `sym1` is linked, then an external reference to the +/// symbol is resolved normally. If a definition of `sym1` is not linked, then all +/// references to the weak external for `sym1` refer to `sym2` instead. The +/// external symbol, `sym2`, must always be linked; typically, it is defined in the +/// module that contains the weak reference to `sym1`. +/// +/// Reference: +/// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#auxiliary-format-3-weak-externals +class LIEF_API AuxiliaryWeakExternal : public AuxiliarySymbol { + public: + enum class CHARACTERISTICS : uint32_t { + /// No library search for `sym1` should be performed. + SEARCH_NOLIBRARY = 1, + + /// A library search for `sym1` should be performed. + SEARCH_LIBRARY = 2, + + /// `sym1` is an alias for sym2 + SEARCH_ALIAS = 3, + + ANTI_DEPENDENCY = 4, + }; + + LIEF_LOCAL static std::unique_ptr + parse(const std::vector& payload); + + AuxiliaryWeakExternal() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::WEAK_EXTERNAL) {} + + AuxiliaryWeakExternal(uint32_t sym_idx, uint32_t characteristics, + std::vector padding) : + AuxiliarySymbol(AuxiliarySymbol::TYPE::WEAK_EXTERNAL), + sym_idx_(sym_idx), + characteristics_(characteristics), + padding_(std::move(padding)) { + assert(padding_.size() == 10); + } + + AuxiliaryWeakExternal(const AuxiliaryWeakExternal&) = default; + AuxiliaryWeakExternal& operator=(const AuxiliaryWeakExternal&) = default; + + AuxiliaryWeakExternal(AuxiliaryWeakExternal&&) = default; + AuxiliaryWeakExternal& operator=(AuxiliaryWeakExternal&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + /// The symbol-table index of `sym2`, the symbol to be linked if `sym1` is not + /// found. + uint32_t sym_idx() const { + return sym_idx_; + } + + CHARACTERISTICS characteristics() const { + return (CHARACTERISTICS)characteristics_; + } + + span padding() const LIEF_LIFETIMEBOUND { + return padding_; + } + + std::string to_string() const override; + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::WEAK_EXTERNAL; + } + + ~AuxiliaryWeakExternal() override = default; + + private: + uint32_t sym_idx_ = 0; + uint32_t characteristics_ = 0; + std::vector padding_; +}; + +LIEF_API const char* to_string(AuxiliaryWeakExternal::CHARACTERISTICS e); + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp new file mode 100644 index 0000000..a8bfa13 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/AuxiliarySymbols/AuxiliarybfAndefSymbol.hpp @@ -0,0 +1,58 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_AUXILIARY_BF_AND_EF_H +#define LIEF_COFF_AUXILIARY_BF_AND_EF_H + +#include + +#include "LIEF/COFF/AuxiliarySymbol.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +class LIEF_API AuxiliarybfAndefSymbol : public AuxiliarySymbol { + public: + LIEF_LOCAL static std::unique_ptr + parse(Symbol& sym, const std::vector& payload); + + AuxiliarybfAndefSymbol() : + AuxiliarySymbol(AuxiliarySymbol::TYPE::BF_AND_EF) {} + + AuxiliarybfAndefSymbol(const AuxiliarybfAndefSymbol&) = default; + AuxiliarybfAndefSymbol& operator=(const AuxiliarybfAndefSymbol&) = default; + + AuxiliarybfAndefSymbol(AuxiliarybfAndefSymbol&&) = default; + AuxiliarybfAndefSymbol& operator=(AuxiliarybfAndefSymbol&&) = default; + + std::unique_ptr clone() const override { + return std::make_unique(*this); + } + + std::string to_string() const override { + return "AuxiliarybfAndefSymbol"; + } + + static bool classof(const AuxiliarySymbol* sym) { + return sym->type() == AuxiliarySymbol::TYPE::BF_AND_EF; + } + + ~AuxiliarybfAndefSymbol() override = default; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/BigObjHeader.hpp b/vendor/lief/include/LIEF/COFF/BigObjHeader.hpp new file mode 100644 index 0000000..09f8d91 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/BigObjHeader.hpp @@ -0,0 +1,124 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_BIGOBJ_HEADER_H +#define LIEF_COFF_BIGOBJ_HEADER_H +#include +#include + +#include "LIEF/COFF/Header.hpp" + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/span.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// This class represents the header for a COFF object compiled +/// with `/bigobj` support (i.e. the number of sections can exceed 65536). +/// +/// The raw definition of the bigobj header is located in `winnt.h` and named +/// `ANON_OBJECT_HEADER_BIGOBJ` +class LIEF_API BigObjHeader : public Header { + public: + static constexpr auto UUID_SZ = 16; + BigObjHeader() : + Header(KIND::BIGOBJ) {} + + static std::unique_ptr create(BinaryStream& stream); + + BigObjHeader& operator=(const BigObjHeader&) = default; + BigObjHeader(const BigObjHeader&) = default; + + BigObjHeader& operator=(BigObjHeader&&) = default; + BigObjHeader(BigObjHeader&&) = default; + + std::unique_ptr
    clone() const override { + return std::unique_ptr
    (new BigObjHeader(*this)); + } + + /// The version of this header which must be >= 2 + uint16_t version() const { + return version_; + } + + /// Originally named `ClassID`, this uuid should match: + /// `{D1BAA1C7-BAEE-4ba9-AF20-FAF66AA4DCB8}` + span uuid() const LIEF_LIFETIMEBOUND { + return uuid_; + } + + /// Size of data that follows the header + uint32_t sizeof_data() const { + return sizeof_data_; + } + + /// 1 means that it contains metadata + uint32_t flags() const { + return flags_; + } + + /// Size of CLR metadata + uint32_t metadata_size() const { + return metadata_size_; + } + + /// Offset of CLR metadata + uint32_t metadata_offset() const { + return metadata_offset_; + } + + void version(uint16_t value) { + version_ = value; + } + + void sizeof_data(uint32_t value) { + sizeof_data_ = value; + } + + void flags(uint32_t value) { + flags_ = value; + } + + void metadata_size(uint32_t value) { + metadata_size_ = value; + } + + void metadata_offset(uint32_t value) { + metadata_offset_ = value; + } + + static bool classof(const Header* header) { + return header->kind() == Header::KIND::BIGOBJ; + } + + ~BigObjHeader() override = default; + + std::string to_string() const override; + + protected: + uint16_t version_ = 0; + std::array uuid_ = {}; + + uint32_t sizeof_data_ = 0; + uint32_t flags_ = 0; + uint32_t metadata_size_ = 0; + uint32_t metadata_offset_ = 0; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/Binary.hpp b/vendor/lief/include/LIEF/COFF/Binary.hpp new file mode 100644 index 0000000..e8214cc --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Binary.hpp @@ -0,0 +1,283 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_BINARY_H +#define LIEF_COFF_BINARY_H +#include "LIEF/iterators.hpp" +#include "LIEF/span.hpp" +#include "LIEF/visibility.h" + +#include "LIEF/COFF/String.hpp" + +#include "LIEF/asm/Instruction.hpp" + +#include +#include +#include +#include +#include + +namespace LIEF { + +namespace assembly { +class Engine; +} + +namespace COFF { +class Header; +class Parser; +class Section; +class Relocation; +class Symbol; + +/// Class that represents a COFF Binary +class LIEF_API Binary { + public: + friend class Parser; + + /// Internal container used to store COFF's section + using sections_t = std::vector>; + + /// Iterator that outputs Section& object + using it_sections = ref_iterator; + + /// Iterator that outputs const Section& object + using it_const_sections = const_ref_iterator; + + /// Internal container used to store COFF's relocations + using relocations_t = std::vector>; + + /// Iterator that outputs Relocation& object + using it_relocations = ref_iterator; + + /// Iterator that outputs const Relocation& object + using it_const_relocations = + const_ref_iterator; + + /// Internal container used to store COFF's strings + using strings_table_t = std::vector; + + /// Iterator that outputs String& object + using it_strings_table = ref_iterator; + + /// Iterator that outputs const String& object + using it_const_strings_table = const_ref_iterator; + + /// Internal container used to store COFF's symbols + using symbols_t = std::vector>; + + /// Iterator that outputs Symbol& object + using it_symbols = ref_iterator; + + /// Iterator that outputs Symbol& object + using it_const_symbols = const_ref_iterator; + + /// Instruction iterator + using instructions_it = iterator_range; + + /// Iterator which outputs COFF symbols representing functions + using it_functions = filter_iterator; + + /// Iterator which outputs COFF symbols representing functions + using it_const_function = const_filter_iterator; + + /// The COFF header + const Header& header() const { + return *header_; + } + + Header& header() { + return *header_; + } + + /// Iterator over the different sections located in this COFF binary + it_sections sections() LIEF_LIFETIMEBOUND { + return sections_; + } + + it_const_sections sections() const LIEF_LIFETIMEBOUND { + return sections_; + } + + /// Iterator over **all** the relocations used by this COFF binary + it_relocations relocations() LIEF_LIFETIMEBOUND { + return relocations_; + } + + it_const_relocations relocations() const LIEF_LIFETIMEBOUND { + return relocations_; + } + + /// Iterator over the COFF's symbols + it_symbols symbols() LIEF_LIFETIMEBOUND { + return symbols_; + } + + it_const_symbols symbols() const LIEF_LIFETIMEBOUND { + return symbols_; + } + + /// Iterator over the COFF's strings + it_const_strings_table string_table() const LIEF_LIFETIMEBOUND { + return strings_table_; + } + + it_strings_table string_table() LIEF_LIFETIMEBOUND { + return strings_table_; + } + + /// Try to find the COFF string at the given offset in the COFF string table. + /// + /// @warning This offset must include the first 4 bytes holding the size of + /// the table. Hence, the first string starts a the offset 4. + String* find_string(uint32_t offset) LIEF_LIFETIMEBOUND { + auto it = std::find_if(strings_table_.begin(), strings_table_.end(), + [offset](const String& item) { + return offset == item.offset(); + }); + return it == strings_table_.end() ? nullptr : &*it; + } + + const String* find_string(uint32_t offset) const LIEF_LIFETIMEBOUND { + return const_cast(this)->find_string(offset); + } + + /// Iterator over the functions implemented in this COFF + it_const_function functions() const LIEF_LIFETIMEBOUND; + + it_functions functions() LIEF_LIFETIMEBOUND; + + /// Try to find the function (symbol) with the given name + const Symbol* find_function(const std::string& name) const LIEF_LIFETIMEBOUND; + + Symbol* find_function(const std::string& name) LIEF_LIFETIMEBOUND { + return const_cast( + static_cast(this)->find_function(name) + ); + } + + /// Try to find the function (symbol) with the given **demangled** name + const Symbol* + find_demangled_function(const std::string& name) const LIEF_LIFETIMEBOUND; + + Symbol* find_demangled_function(const std::string& name) LIEF_LIFETIMEBOUND { + return const_cast( + static_cast(this)->find_demangled_function(name) + ); + } + + /// Disassemble code for the given symbol + /// + /// ```cpp + /// const Symbol* func = binary->find_demangled_function("int __cdecl + /// my_function(int, int)"); auto insts = binary->disassemble(*func); for + /// (std::unique_ptr inst : insts) { + /// std::cout << inst->to_string() << '\n'; + /// } + /// ``` + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const Symbol& symbol) const; + + /// Disassemble code for the given symbol name + /// + /// ```cpp + /// auto insts = binary->disassemble("main"); + /// for (std::unique_ptr inst : insts) { + /// std::cout << inst->to_string() << '\n'; + /// } + /// ``` + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const std::string& symbol) const; + + /// Disassemble code provided by the given buffer at the specified + /// `address` parameter. + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const uint8_t* buffer, size_t size, + uint64_t address = 0) const; + + + /// Disassemble code provided by the given vector of bytes at the specified + /// `address` parameter. + /// + /// @see LIEF::assembly::Instruction + instructions_it disassemble(const std::vector& buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + instructions_it disassemble(LIEF::span buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + instructions_it disassemble(LIEF::span buffer, + uint64_t address = 0) const { + return disassemble(buffer.data(), buffer.size(), address); + } + + /// Return the section matching the given name or a nullptr if it can't be + /// found. + /// + /// Section names that do not fit in the 8 bytes allocated by the COFF format + /// are stored in the COFF string table while the section itself only holds a + /// `/` placeholder. This function transparently resolves both forms, + /// so a long name can be looked up with its **regular** value: + /// + /// ```cpp + /// const Section* sec = binary->get_section(".debug_rnglists"); + /// sec->name(); // "/18" + /// sec->coff_string()->str(); // ".debug_rnglists" + /// ``` + /// + /// @param[in] name Name of the section + Section* get_section(std::string_view name) LIEF_LIFETIMEBOUND { + return const_cast( + static_cast(this)->get_section(name) + ); + } + + const Section* get_section(std::string_view name) const LIEF_LIFETIMEBOUND; + + std::string to_string() const; + + LIEF_API friend std::ostream& operator<<(std::ostream& os, const Binary& bin) { + os << bin.to_string(); + return os; + } + + ~Binary(); + + private: + Binary(); + std::unique_ptr
    header_; + sections_t sections_; + relocations_t relocations_; + strings_table_t strings_table_; + symbols_t symbols_; + + mutable std::unordered_map> engines_; + + assembly::Engine* get_engine(uint64_t address) const; + + template + LIEF_LOCAL assembly::Engine* get_cache_engine(uint64_t address, F&& f) const; +}; + +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/Header.hpp b/vendor/lief/include/LIEF/COFF/Header.hpp new file mode 100644 index 0000000..d7e33ae --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Header.hpp @@ -0,0 +1,152 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_HEADER_H +#define LIEF_COFF_HEADER_H +#include +#include +#include + +#include "LIEF/PE/Header.hpp" +#include "LIEF/visibility.h" + +namespace LIEF { +class BinaryStream; + +namespace COFF { + +/// Class that represents the COFF header. It is subclassed by +/// LIEF::COFF::RegularHeader and LIEF::COFF::BigObjHeader for normal vs +/// `/bigobj` files +class LIEF_API Header { + public: + enum class KIND { + UNKNOWN = 0, + REGULAR, + BIGOBJ, + }; + + /// The different architectures (mirrored from PE) + using MACHINE_TYPES = LIEF::PE::Header::MACHINE_TYPES; + + /// Create a header from the given stream + static std::unique_ptr
    create(BinaryStream& stream); + static std::unique_ptr
    create(BinaryStream& stream, KIND kind); + + Header() = default; + Header(KIND kind) : + kind_(kind) {} + + Header& operator=(const Header&) = default; + Header(const Header&) = default; + + Header& operator=(Header&&) = default; + Header(Header&&) = default; + + virtual std::unique_ptr
    clone() const = 0; + + /// The type of this header: whether it is regular or using the `/bigobj` + /// format + KIND kind() const { + return kind_; + } + + /// The machine type targeted by this COFF + MACHINE_TYPES machine() const { + return machine_; + } + + /// The number of sections + uint32_t nb_sections() const { + return nb_sections_; + } + + /// Offset of the symbols table + uint32_t pointerto_symbol_table() const { + return pointerto_symbol_table_; + } + + /// Number of symbols (including auxiliary symbols) + uint32_t nb_symbols() const { + return nb_symbols_; + } + + /// Timestamp when the COFF has been generated + uint32_t timedatestamp() const { + return timedatestamp_; + } + + void machine(MACHINE_TYPES machine) { + machine_ = machine; + } + + void nb_sections(uint32_t value) { + nb_sections_ = value; + } + + void pointerto_symbol_table(uint32_t value) { + pointerto_symbol_table_ = value; + } + + void nb_symbols(uint32_t value) { + nb_symbols_ = value; + } + + void timedatestamp(uint32_t value) { + timedatestamp_ = value; + } + + virtual std::string to_string() const; + + LIEF_API friend std::ostream& operator<<(std::ostream& os, const Header& hdr) { + os << hdr.to_string(); + return os; + } + + template + const T* as() const { + static_assert(std::is_base_of_v, "Require Header inheritance"); + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + virtual ~Header() = default; + + protected: + KIND kind_ = KIND::UNKNOWN; + MACHINE_TYPES machine_ = MACHINE_TYPES::UNKNOWN; + uint32_t nb_sections_ = 0; + uint32_t pointerto_symbol_table_ = 0; + uint32_t nb_symbols_ = 0; + uint32_t timedatestamp_ = 0; +}; + +LIEF_API inline const char* to_string(Header::KIND kind) { + switch (kind) { + case Header::KIND::UNKNOWN: return "UNKNOWN"; + case Header::KIND::REGULAR: return "REGULAR"; + case Header::KIND::BIGOBJ: return "BIGOBJ"; + } + return "UNKNOWN"; +} + +LIEF_API inline const char* to_string(Header::MACHINE_TYPES machine) { + return LIEF::PE::to_string(machine); +} +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/Parser.hpp b/vendor/lief/include/LIEF/COFF/Parser.hpp new file mode 100644 index 0000000..cdca726 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Parser.hpp @@ -0,0 +1,114 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_PARSER_H +#define LIEF_COFF_PARSER_H +#include "LIEF/BinaryStream/BinaryStream.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/path.hpp" +#include "LIEF/visibility.h" + +#include +#include + +#include "LIEF/COFF/Header.hpp" +#include "LIEF/COFF/ParserConfig.hpp" + + +namespace LIEF::COFF { +class Binary; +class Section; +class String; +class Symbol; + +class Parser { + public: + static constexpr size_t MAX_NB_SECTIONS = 1 << 20; + + /// Parse the COFF binary referenced by the `stream` argument with the + /// given config + static LIEF_API std::unique_ptr + parse(std::unique_ptr stream, + const ParserConfig& config = ParserConfig::default_conf()); + + /// Parse the COFF binary pointed by the `file` argument with the given config + static LIEF_API std::unique_ptr + parse(std::string_view file, + const ParserConfig& config = ParserConfig::default_conf()); + + /// Same as parse(std::string_view, const ParserConfig&) but the file is + /// given as a `std::filesystem::path` + template = 0> + static std::unique_ptr + parse(const PathT& file, + const ParserConfig& config = ParserConfig::default_conf()) { + return parse(file.string(), config); + } + + /// @private + struct SymSec { + size_t sec_idx = 0; + Symbol* symbol = nullptr; + + friend bool operator<(SymSec lhs, SymSec rhs) { + return lhs.sec_idx < rhs.sec_idx; + } + + friend bool operator==(SymSec lhs, SymSec rhs) { + return lhs.sec_idx == rhs.sec_idx && lhs.symbol == rhs.symbol; + } + + friend bool operator!=(SymSec lhs, SymSec rhs) { + return !(lhs == rhs); + } + }; + + /// <=> std::unordered_multimap
    + using SymSecMap = std::vector; + + /// @private + LIEF_LOCAL void memoize(String str); + + /// @private + LIEF_LOCAL String* find_coff_string(uint32_t offset) const; + + ~Parser(); + + private: + Parser(std::unique_ptr stream, const ParserConfig& config, + Header::KIND kind); + + ok_error_t process(); + ok_error_t parse_header(); + ok_error_t parse_optional_header(); + ok_error_t parse_sections(); + ok_error_t parse_relocations(Section& section); + ok_error_t parse_symbols(); + ok_error_t parse_string_table(); + + std::unique_ptr stream_; + std::unique_ptr bin_; + Header::KIND kind_ = Header::KIND::UNKNOWN; + + std::map memoize_coff_str_; + std::map symbol_idx_; + SymSecMap symsec_; + + LIEF_MAYBE_UNUSED ParserConfig config_; +}; +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/ParserConfig.hpp b/vendor/lief/include/LIEF/COFF/ParserConfig.hpp new file mode 100644 index 0000000..9d6abfd --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/ParserConfig.hpp @@ -0,0 +1,38 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_PARSER_CONFIG_H +#define LIEF_COFF_PARSER_CONFIG_H + +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { +/// Class used to configure the COFF parser +class LIEF_API ParserConfig { + public: + static const ParserConfig& default_conf() { + static const ParserConfig DEFAULT; + return DEFAULT; + } + + static const ParserConfig& all() { + // To be updated when there are options that are off by default + return default_conf(); + } +}; +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/RegularHeader.hpp b/vendor/lief/include/LIEF/COFF/RegularHeader.hpp new file mode 100644 index 0000000..cd0dfe6 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/RegularHeader.hpp @@ -0,0 +1,77 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_REGULAR_HEADER_H +#define LIEF_COFF_REGULAR_HEADER_H +#include "LIEF/COFF/Header.hpp" +#include "LIEF/visibility.h" +#include + + +namespace LIEF::COFF { + +/// This class represents the COFF header for non-bigobj +class LIEF_API RegularHeader : public Header { + public: + RegularHeader() : + Header(KIND::REGULAR) {} + + /// Create a RegularHeader from the given stream + static std::unique_ptr create(BinaryStream& stream); + + RegularHeader& operator=(const RegularHeader&) = default; + RegularHeader(const RegularHeader&) = default; + + RegularHeader& operator=(RegularHeader&&) = default; + RegularHeader(RegularHeader&&) = default; + + std::unique_ptr
    clone() const override { + return std::unique_ptr
    (new RegularHeader(*this)); + } + + /// The size of the optional header which follows this header (should be 0) + uint16_t sizeof_optionalheader() const { + return sizeof_optionalheader_; + } + + /// Characteristics + uint16_t characteristics() const { + return characteristics_; + } + + void sizeof_optionalheader(uint16_t value) { + sizeof_optionalheader_ = value; + } + + void characteristics(uint16_t value) { + characteristics_ = value; + } + + static bool classof(const Header* header) { + return header->kind() == Header::KIND::REGULAR; + } + + ~RegularHeader() override = default; + + std::string to_string() const override; + + protected: + uint16_t sizeof_optionalheader_ = 0; + uint16_t characteristics_ = 0; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/Relocation.hpp b/vendor/lief/include/LIEF/COFF/Relocation.hpp new file mode 100644 index 0000000..331b422 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Relocation.hpp @@ -0,0 +1,212 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_RELOCATION_H +#define LIEF_COFF_RELOCATION_H +#include +#include +#include + +#include "LIEF/Abstract/Relocation.hpp" +#include "LIEF/COFF/Header.hpp" +#include "LIEF/visibility.h" + +namespace LIEF { +class BinaryStream; +namespace COFF { +class Section; +class Parser; +class Symbol; + +/// This class represents a COFF relocation +class LIEF_API Relocation : public LIEF::Relocation { + public: + friend class Parser; + + static constexpr uint32_t I386 = 1 << 17; + static constexpr uint32_t X64 = 1 << 18; + static constexpr uint32_t ARM = 1 << 19; + static constexpr uint32_t ARM64 = 1 << 20; + static constexpr uint32_t MIPS = 1 << 21; + + /// The different relocation types. + /// + /// Please note that the original type is encoded on 16 bits but we encode + /// the type on 32-bits by adding a discriminator from the 17th bit + enum class TYPE : uint32_t { + UNKNOWN = uint32_t(-1), + I386_ABSOLUTE = I386 + 0x0000, + I386_DIR16 = I386 + 0x0001, + I386_REL16 = I386 + 0x0002, + I386_DIR32 = I386 + 0x0006, + I386_DIR32NB = I386 + 0x0007, + I386_SEG12 = I386 + 0x0009, + I386_SECTION = I386 + 0x000A, + I386_SECREL = I386 + 0x000B, + I386_TOKEN = I386 + 0x000C, + I386_SECREL7 = I386 + 0x000D, + I386_REL32 = I386 + 0x0014, + + AMD64_ABSOLUTE = X64 + 0x0000, + AMD64_ADDR64 = X64 + 0x0001, + AMD64_ADDR32 = X64 + 0x0002, + AMD64_ADDR32NB = X64 + 0x0003, + AMD64_REL32 = X64 + 0x0004, + AMD64_REL32_1 = X64 + 0x0005, + AMD64_REL32_2 = X64 + 0x0006, + AMD64_REL32_3 = X64 + 0x0007, + AMD64_REL32_4 = X64 + 0x0008, + AMD64_REL32_5 = X64 + 0x0009, + AMD64_SECTION = X64 + 0x000A, + AMD64_SECREL = X64 + 0x000B, + AMD64_SECREL7 = X64 + 0x000C, + AMD64_TOKEN = X64 + 0x000D, + AMD64_SREL32 = X64 + 0x000E, + AMD64_PAIR = X64 + 0x000F, + AMD64_SSPAN32 = X64 + 0x0010, + + ARM_ABSOLUTE = ARM + 0x0000, + ARM_ADDR32 = ARM + 0x0001, + ARM_ADDR32NB = ARM + 0x0002, + ARM_BRANCH24 = ARM + 0x0003, + ARM_BRANCH11 = ARM + 0x0004, + ARM_TOKEN = ARM + 0x0005, + ARM_BLX24 = ARM + 0x0008, + ARM_BLX11 = ARM + 0x0009, + ARM_REL32 = ARM + 0x000A, + ARM_SECTION = ARM + 0x000E, + ARM_SECREL = ARM + 0x000F, + ARM_MOV32A = ARM + 0x0010, + ARM_MOV32T = ARM + 0x0011, + ARM_BRANCH20T = ARM + 0x0012, + ARM_BRANCH24T = ARM + 0x0014, + ARM_BLX23T = ARM + 0x0015, + ARM_PAIR = ARM + 0x0016, + + ARM64_ABSOLUTE = ARM64 + 0x0000, + ARM64_ADDR32 = ARM64 + 0x0001, + ARM64_ADDR32NB = ARM64 + 0x0002, + ARM64_BRANCH26 = ARM64 + 0x0003, + ARM64_PAGEBASE_REL21 = ARM64 + 0x0004, + ARM64_REL21 = ARM64 + 0x0005, + ARM64_PAGEOFFSET_12A = ARM64 + 0x0006, + ARM64_PAGEOFFSET_12L = ARM64 + 0x0007, + ARM64_SECREL = ARM64 + 0x0008, + ARM64_SECREL_LOW12A = ARM64 + 0x0009, + ARM64_SECREL_HIGH12A = ARM64 + 0x000A, + ARM64_SECREL_LOW12L = ARM64 + 0x000B, + ARM64_TOKEN = ARM64 + 0x000C, + ARM64_SECTION = ARM64 + 0x000D, + ARM64_ADDR64 = ARM64 + 0x000E, + ARM64_BRANCH19 = ARM64 + 0x000F, + ARM64_BRANCH14 = ARM64 + 0x0010, + ARM64_REL32 = ARM64 + 0x0011, + + MIPS_ABSOLUTE = MIPS + 0x0000, + MIPS_REFHALF = MIPS + 0x0001, + MIPS_REFWORD = MIPS + 0x0002, + MIPS_JMPADDR = MIPS + 0x0003, + MIPS_REFHI = MIPS + 0x0004, + MIPS_REFLO = MIPS + 0x0005, + MIPS_GPREL = MIPS + 0x0006, + MIPS_LITERAL = MIPS + 0x0007, + MIPS_SECTION = MIPS + 0x000A, + MIPS_SECREL = MIPS + 0x000B, + MIPS_SECRELLO = MIPS + 0x000C, + MIPS_SECRELHI = MIPS + 0x000D, + MIPS_JMPADDR16 = MIPS + 0x0010, + MIPS_REFWORDNB = MIPS + 0x0022, + MIPS_PAIR = MIPS + 0x0025, + }; + + /// Convert a relocation enum type into a 16-bits value. + static uint16_t to_value(TYPE rtype) { + return (uint16_t)rtype; + } + + /// Create a relocation type from its raw value and the architecture + static TYPE from_value(uint16_t value, Header::MACHINE_TYPES arch) { + switch (arch) { + case Header::MACHINE_TYPES::ARM64: return TYPE(value + ARM64); + + case Header::MACHINE_TYPES::AMD64: return TYPE(value + X64); + + case Header::MACHINE_TYPES::I386: return TYPE(value + I386); + + case Header::MACHINE_TYPES::ARM: + case Header::MACHINE_TYPES::ARMNT: + case Header::MACHINE_TYPES::THUMB: return TYPE(value + ARM); + + case Header::MACHINE_TYPES::R4000: return TYPE(value + MIPS); + + default: return TYPE::UNKNOWN; + } + return TYPE::UNKNOWN; + } + + /// Create a relocation from the given stream + static std::unique_ptr parse(BinaryStream& stream, + Header::MACHINE_TYPES arch); + + /// Symbol index associated with this relocation + uint32_t symbol_idx() const { + return symbol_idx_; + } + + /// Symbol associated with the relocation (if any) + Symbol* symbol() { + return symbol_; + } + + const Symbol* symbol() const { + return symbol_; + } + + /// Type of the relocation + TYPE type() const { + return type_; + } + + /// Section in which the relocation takes place + Section* section() { + return section_; + } + + const Section* section() const { + return section_; + } + + std::string to_string() const; + + LIEF_API friend std::ostream& operator<<(std::ostream& os, const Relocation& R) { + os << R.to_string(); + return os; + } + + ~Relocation() override = default; + + private: + Relocation() = default; + uint32_t symbol_idx_ = 0; + TYPE type_ = TYPE::UNKNOWN; + Section* section_ = nullptr; + Symbol* symbol_ = nullptr; +}; + +LIEF_API const char* to_string(Relocation::TYPE e); + +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/Section.hpp b/vendor/lief/include/LIEF/COFF/Section.hpp new file mode 100644 index 0000000..7e7fc57 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Section.hpp @@ -0,0 +1,269 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_SECTION_H +#define LIEF_COFF_SECTION_H +#include +#include +#include +#include + +#include "LIEF/Abstract/Section.hpp" +#include "LIEF/COFF/AuxiliarySymbols/AuxiliarySectionDefinition.hpp" +#include "LIEF/PE/Section.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" +#include + +namespace LIEF { +class BinaryStream; + +namespace COFF { +class Relocation; +class Parser; +class Symbol; + + +/// This class represents a COFF section +class LIEF_API Section : public LIEF::Section { + public: + friend class Parser; + using LIEF::Section::name; + + using COMDAT_SELECTION = AuxiliarySectionDefinition::COMDAT_SELECTION; + + /// This structure wraps comdat information which is composed of the symbol + /// associated with the comdat section and its selection flag + struct LIEF_API ComdatInfo { + Symbol* symbol = nullptr; + COMDAT_SELECTION kind = COMDAT_SELECTION::NONE; + }; + + /// Mirror Characteristics from PE + using CHARACTERISTICS = LIEF::PE::Section::CHARACTERISTICS; + + /// Container for the relocations in this section (owned by the Binary object) + using relocations_t = std::vector; + + /// Iterator that outputs Relocation& + using it_relocations = ref_iterator; + + /// Iterator that outputs const Relocation& + using it_const_relocations = + const_ref_iterator; + + /// Container for the symbols associated with this section (owned by the Binary + /// object) + using symbols_t = std::vector; + + /// Iterator that outputs Symbol& + using it_symbols = ref_iterator; + + /// Iterator that outputs const Symbol& + using it_const_symbols = const_ref_iterator; + + /// Parse a section from the given stream + static std::unique_ptr
    parse(BinaryStream& stream); + + /// Return the size of the data in the section. + uint32_t sizeof_raw_data() const { + return size_; + } + + /// Virtual size of the section (should be 0) + uint32_t virtual_size() const { + return virtual_size_; + } + + /// Content wrapped by this section + span content() const LIEF_LIFETIMEBOUND override { + return content_; + } + + /// Offset to the section's content + uint32_t pointerto_raw_data() const { + return offset_; + } + + /// Offset to the relocation table + uint32_t pointerto_relocation() const { + return pointer_to_relocations_; + } + + /// The file pointer to the beginning of line-number entries for the section. + /// + /// This is set to zero if there are no COFF line numbers. + /// This value should be zero for an image because COFF debugging information + /// is deprecated and modern debug information relies on the PDB files. + uint32_t pointerto_line_numbers() const { + return pointer_to_linenumbers_; + } + + /// Number of relocations. + /// + /// @warning If the number of relocations is greater than 0xFFFF (maximum + /// value for 16-bits integer), then the number of relocations is + /// stored in the virtual address of the **first** relocation. + uint16_t numberof_relocations() const { + return number_of_relocations_; + } + + /// Number of line number entries (if any). + uint16_t numberof_line_numbers() const { + return number_of_linenumbers_; + } + + /// Characteristics of the section: it provides information about + /// the permissions of the section when mapped. It can also provide + /// information about the *purpose* of the section (contain code, BSS-like, ...) + uint32_t characteristics() const { + return characteristics_; + } + + /// Check if the section has the given CHARACTERISTICS + bool has_characteristic(CHARACTERISTICS c) const { + return (characteristics() & (uint32_t)c) > 0; + } + + /// List of the section characteristics + std::vector characteristics_list() const { + return LIEF::PE::Section::characteristics_to_list(characteristics_); + } + + /// True if the section can be discarded as needed. + /// + /// This is typically the case for debug-related sections + bool is_discardable() const { + return has_characteristic(CHARACTERISTICS::MEM_DISCARDABLE); + } + + void clear(uint8_t c) { + std::fill(content_.begin(), content_.end(), c); + } + + /// Iterator over the relocations associated with this section + it_relocations relocations() LIEF_LIFETIMEBOUND { + return relocations_; + } + + it_const_relocations relocations() const LIEF_LIFETIMEBOUND { + return relocations_; + } + + /// Iterator over the symbols associated with this section + it_symbols symbols() LIEF_LIFETIMEBOUND { + return symbols_; + } + + it_const_symbols symbols() const LIEF_LIFETIMEBOUND { + return symbols_; + } + + /// Return comdat information (only if the section has the + /// CHARACTERISTICS::LNK_COMDAT characteristic) + std::optional comdat_info() const; + + /// Whether there is a large number of relocations whose number need + /// to be stored in the virtual address attribute + bool has_extended_relocations() const { + static constexpr auto MAX_RELOC = /*uint16_t::max*/ 65535; + return has_characteristic(CHARACTERISTICS::LNK_NRELOC_OVFL) && + numberof_relocations() == MAX_RELOC; + } + + void content(const std::vector& data) override { + content_ = data; + } + + void name(std::string name) override; + + void virtual_size(uint32_t virtual_sz) { + virtual_size_ = virtual_sz; + } + + void pointerto_raw_data(uint32_t ptr) { + offset(ptr); + } + + void pointerto_relocation(uint32_t ptr) { + pointer_to_relocations_ = ptr; + } + + void pointerto_line_numbers(uint32_t ptr) { + pointer_to_linenumbers_ = ptr; + } + + void numberof_relocations(uint16_t nb) { + number_of_relocations_ = nb; + } + + void numberof_line_numbers(uint16_t nb) { + number_of_linenumbers_ = nb; + } + + void sizeof_raw_data(uint32_t size) { + this->size(size); + } + + void characteristics(uint32_t characteristics) { + characteristics_ = characteristics; + } + + /// Return the COFF string associated with the section's name (or a nullptr) + /// + /// This coff string is usually present for long section names whose length + /// does not fit in the 8 bytes allocated by the COFF format. + String* coff_string() { + return coff_string_; + } + + const String* coff_string() const { + return coff_string_; + } + + std::string to_string() const; + + LIEF_API friend std::ostream& operator<<(std::ostream& os, const Section& sec) { + os << sec.to_string(); + return os; + } + + ~Section() override = default; + + private: + Section() = default; + + std::vector content_; + uint32_t virtual_size_ = 0; + uint32_t pointer_to_relocations_ = 0; + uint32_t pointer_to_linenumbers_ = 0; + uint16_t number_of_relocations_ = 0; + uint16_t number_of_linenumbers_ = 0; + uint32_t characteristics_ = 0; + + relocations_t relocations_; + symbols_t symbols_; + + String* coff_string_ = nullptr; +}; + +inline const char* to_string(Section::CHARACTERISTICS e) { + return LIEF::PE::to_string(e); +} + +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/String.hpp b/vendor/lief/include/LIEF/COFF/String.hpp new file mode 100644 index 0000000..a4dd9ae --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/String.hpp @@ -0,0 +1,87 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_STRING_H +#define LIEF_COFF_STRING_H +#include +#include +#include +#include + +#include "LIEF/visibility.h" + + +namespace LIEF::COFF { + +/// This class represents a string located in the COFF string table. +/// +/// Some of these strings can be used for section names that are greater than 8 +/// bytes. See: LIEF::PE::Section::coff_string() +/// +/// Reference: +/// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-string-table +class LIEF_API String { + public: + String() = default; + String(uint32_t offset, std::string str) : + str_(std::move(str)), + offset_(offset) {} + + String(const String&) = default; + String& operator=(const String&) = default; + + String(String&&) = default; + String& operator=(String&&) = default; + + ~String() = default; + + /// The actual string + std::string_view str() const LIEF_LIFETIMEBOUND { + return str_; + } + + /// Mutable access to the underlying string storage. + std::string& str() LIEF_LIFETIMEBOUND { + return str_; + } + + /// The offset of this string the in the COFF string table. + /// This offset includes the first 4-bytes that holds the table size + uint32_t offset() const { + return offset_; + } + + String& str(std::string str) LIEF_LIFETIMEBOUND { + str_ = std::move(str); + return *this; + } + + String& offset(uint32_t value) LIEF_LIFETIMEBOUND { + offset_ = value; + return *this; + } + + friend LIEF_API std::ostream& operator<<(std::ostream& os, const String& str) { + os << str.str(); + return os; + } + + private: + std::string str_; + uint32_t offset_ = 0; +}; +} + +#endif diff --git a/vendor/lief/include/LIEF/COFF/Symbol.hpp b/vendor/lief/include/LIEF/COFF/Symbol.hpp new file mode 100644 index 0000000..0871e58 --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/Symbol.hpp @@ -0,0 +1,293 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_SYMBOL_H +#define LIEF_COFF_SYMBOL_H + +#include "LIEF/Abstract/Symbol.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" +#include + +#include +#include + +namespace LIEF { +class BinaryStream; +namespace COFF { +class Parser; +class AuxiliarySymbol; +class String; +class Section; + +/// This class represents a COFF symbol +class LIEF_API Symbol : public LIEF::Symbol { + public: + friend class Parser; + + using auxiliary_symbols_t = std::vector>; + + using it_auxiliary_symbols_t = + ref_iterator; + + using it_const_auxiliary_symbols_t = + const_ref_iterator; + + struct parsing_context_t { + std::function find_string; + bool is_bigobj; + }; + static std::unique_ptr parse(parsing_context_t& ctx, + BinaryStream& stream, size_t* idx); + + Symbol(); + Symbol(const Symbol&); + Symbol& operator=(const Symbol&); + + Symbol(Symbol&&) noexcept; + Symbol& operator=(Symbol&&) noexcept; + + /// The symbol provides general type or debugging information but does not + /// correspond to a section. Microsoft tools use this setting along with + /// `.file` records. + static constexpr auto SYM_SEC_IDX_DEBUG = -2; + + /// The symbol has an absolute (non-relocatable) value and is not an address. + static constexpr auto SYM_SEC_IDX_ABS = -1; + + /// The symbol record is not yet assigned a section. A value of zero indicates + /// that a reference to an external symbol is defined elsewhere. A value of + /// non-zero is a common symbol with a size that is specified by the value. + static constexpr auto SYM_SEC_IDX_UNDEF = 0; + + static constexpr auto SYM_COMPLEX_TYPE_SHIFT = 4; + + /// Reference: + /// https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#storage-class + enum class STORAGE_CLASS : int32_t { + INVALID = 0xFF, + + END_OF_FUNCTION = -1, ///< Physical end of function + NONE = 0, ///< No symbol + AUTOMATIC = 1, ///< Stack variable + EXTERNAL = 2, ///< External symbol + STATIC = 3, ///< Static + REGISTER = 4, ///< Register variable + EXTERNAL_DEF = 5, ///< External definition + LABEL = 6, ///< Label + UNDEFINED_LABEL = 7, ///< Undefined label + MEMBER_OF_STRUCT = 8, ///< Member of structure + ARGUMENT = 9, ///< Function argument + STRUCT_TAG = 10, ///< Structure tag + MEMBER_OF_UNION = 11, ///< Member of union + UNION_TAG = 12, ///< Union tag + TYPE_DEFINITION = 13, ///< Type definition + UNDEFINED_STATIC = 14, ///< Undefined static + ENUM_TAG = 15, ///< Enumeration tag + MEMBER_OF_ENUM = 16, ///< Member of enumeration + REGISTER_PARAM = 17, ///< Register parameter + BIT_FIELD = 18, ///< Bit field + BLOCK = 100, + FUNCTION = 101, + END_OF_STRUCT = 102, ///< End of structure + FILE = 103, ///< File name + SECTION = 104, + WEAK_EXTERNAL = 105, ///< Duplicate tag + CLR_TOKEN = 107, + }; + + enum class BASE_TYPE : uint32_t { + TY_NULL = 0, ///< No type information or unknown base type. + TY_VOID = 1, ///< Used with void pointers and functions. + TY_CHAR = 2, ///< A character (signed byte). + TY_SHORT = 3, ///< A 2-byte signed integer. + TY_INT = 4, ///< A natural integer type on the target. + TY_LONG = 5, ///< A 4-byte signed integer. + TY_FLOAT = 6, ///< A 4-byte floating-point number. + TY_DOUBLE = 7, ///< An 8-byte floating-point number. + TY_STRUCT = 8, ///< A structure. + TY_UNION = 9, ///< A union. + TY_ENUM = 10, ///< An enumerated type. + TY_MOE = 11, ///< A member of enumeration (a specific value). + TY_BYTE = 12, ///< A byte; unsigned 1-byte integer. + TY_WORD = 13, ///< A word; unsigned 2-byte integer. + TY_UINT = 14, ///< An unsigned integer of natural size. + TY_DWORD = 15, ///< An unsigned 4-byte integer. + }; + + enum class COMPLEX_TYPE : uint32_t { + TY_NULL = 0, ///< No complex type; simple scalar variable. + TY_POINTER = 1, ///< A pointer to base type. + TY_FUNCTION = 2, ///< A function that returns a base type. + TY_ARRAY = 3, ///< An array of base type. + }; + + /// Check if the given section index is a reserved value + static constexpr bool is_reversed_sec_idx(int16_t idx) { + return idx <= 0; + } + + /// The symbol type. The first byte represents the base type (see: base_type()) + /// while the upper byte represents the complex type, if any (see: + /// complex_type()). + uint16_t type() const { + return type_; + } + + /// Storage class of the symbol which indicates what kind of definition a + /// symbol represents. + STORAGE_CLASS storage_class() const { + return (STORAGE_CLASS)storage_class_; + } + + /// The simple (base) data type + BASE_TYPE base_type() const { + return (BASE_TYPE)(type_ & 0x0F); + } + + /// The complex type (if any) + COMPLEX_TYPE complex_type() const { + return (COMPLEX_TYPE)((type_ & 0xF0) >> SYM_COMPLEX_TYPE_SHIFT); + } + + /// The signed integer that identifies the section, using a one-based index + /// into the section table. Some values have special meaning: + /// + /// * 0: The symbol record is not yet assigned a section. A value of zero + /// indicates that a reference to an external symbol is defined elsewhere. + /// A value of non-zero is a common symbol with a size that is specified + /// by the value. + /// * -1: The symbol has an absolute (non-relocatable) value and is not an + /// address. + /// * -2: The symbol provides general type or debugging information but does + /// not correspond to a section. Microsoft tools use this setting along + /// with `.file` records + int16_t section_idx() const { + return section_idx_; + } + + /// Section associated with this symbol (if any) + Section* section() LIEF_LIFETIMEBOUND { + return section_; + } + + const Section* section() const LIEF_LIFETIMEBOUND { + return section_; + } + + bool is_external() const { + return storage_class() == STORAGE_CLASS::EXTERNAL; + } + + bool is_weak_external() const { + return storage_class() == STORAGE_CLASS::WEAK_EXTERNAL; + } + + bool is_absolute() const { + return section_idx() == SYM_SEC_IDX_ABS; + } + + bool is_undefined() const { + return is_external() && section_idx() == SYM_SEC_IDX_UNDEF && value() == 0; + } + + bool is_function_line_info() const { + return storage_class() == STORAGE_CLASS::FUNCTION; + } + + bool is_function() const { + return complex_type() == COMPLEX_TYPE::TY_FUNCTION; + } + + bool is_file_record() const { + return storage_class() == STORAGE_CLASS::FILE; + } + + /// Auxiliary symbols associated with this symbol. + it_auxiliary_symbols_t auxiliary_symbols() LIEF_LIFETIMEBOUND { + return auxiliary_symbols_; + } + + it_const_auxiliary_symbols_t auxiliary_symbols() const LIEF_LIFETIMEBOUND { + return auxiliary_symbols_; + } + + /// Name of the symbol. If the symbol does not use a short name, it returns + /// the string pointed by the COFF string offset + std::string_view name() const LIEF_LIFETIMEBOUND override; + + std::string& name() override; + + /// COFF string used to represent the (long) symbol name + const String* coff_name() const LIEF_LIFETIMEBOUND { + return coff_name_; + } + + String* coff_name() LIEF_LIFETIMEBOUND { + return coff_name_; + } + + /// Demangled representation of the symbol or an empty string if it can't + /// be demangled + std::string demangled_name() const; + + Symbol& type(uint16_t ty) LIEF_LIFETIMEBOUND { + type_ = ty; + return *this; + } + + Symbol& storage_class(uint8_t value) LIEF_LIFETIMEBOUND { + storage_class_ = value; + return *this; + } + + Symbol& section_idx(int16_t idx) LIEF_LIFETIMEBOUND { + section_idx_ = idx; + return *this; + } + + /// Add a new auxiliary record + AuxiliarySymbol& + add_aux(std::unique_ptr sym) LIEF_LIFETIMEBOUND; + + std::string to_string() const; + + LIEF_API friend std::ostream& operator<<(std::ostream& os, const Symbol& entry) { + os << entry.to_string(); + return os; + } + + ~Symbol() override; + + private: + template + static std::unique_ptr parse_impl(parsing_context_t& ctx, + BinaryStream& stream, size_t* idx); + String* coff_name_ = nullptr; + uint16_t type_ = 0; + uint8_t storage_class_ = 0; + int16_t section_idx_ = 0; + auxiliary_symbols_t auxiliary_symbols_; + Section* section_ = nullptr; +}; + +LIEF_API const char* to_string(Symbol::STORAGE_CLASS e); +LIEF_API const char* to_string(Symbol::BASE_TYPE e); +LIEF_API const char* to_string(Symbol::COMPLEX_TYPE e); + +} +} +#endif diff --git a/vendor/lief/include/LIEF/COFF/utils.hpp b/vendor/lief/include/LIEF/COFF/utils.hpp new file mode 100644 index 0000000..b9cdbad --- /dev/null +++ b/vendor/lief/include/LIEF/COFF/utils.hpp @@ -0,0 +1,63 @@ +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_COFF_UTILS_H +#define LIEF_COFF_UTILS_H +#include "LIEF/BinaryStream/SpanStream.hpp" +#include "LIEF/COFF/Header.hpp" +#include "LIEF/visibility.h" + +#include + + +namespace LIEF::COFF { + +/// This function determines if the given stream wraps a COFF binary and if so, +/// whether it's a regular or bigobj COFF. +LIEF_API Header::KIND get_kind(BinaryStream& stream); + +/// Check if the given stream wraps a COFF file +LIEF_API inline bool is_coff(BinaryStream& stream) { + return get_kind(stream) != Header::KIND::UNKNOWN; +} + +/// Check if the `file` is a COFF +LIEF_API bool is_coff(std::string_view file); + +/// Check if the given buffer points to a COFF file +LIEF_API inline bool is_coff(const uint8_t* buffer, size_t size) { + LIEF::SpanStream strm(buffer, size); + return is_coff(strm); +} + +/// Check if the given buffer points to a COFF file +LIEF_API inline bool is_coff(const std::vector& buffer) { + return is_coff(buffer.data(), buffer.size()); +} + +/// Check if the COFF file wrapped by the given stream is a `bigobj` +LIEF_API inline bool is_bigobj(BinaryStream& stream) { + return get_kind(stream) == Header::KIND::BIGOBJ; +} + +/// Check if the COFF file wrapped by the given stream is regular +/// (i.e. not a bigobj) +LIEF_API inline bool is_regular(BinaryStream& stream) { + return get_kind(stream) == Header::KIND::REGULAR; +} + +} + +#endif diff --git a/vendor/lief/include/LIEF/DEX.hpp b/vendor/lief/include/LIEF/DEX.hpp index 281109b..fff0c9e 100644 --- a/vendor/lief/include/LIEF/DEX.hpp +++ b/vendor/lief/include/LIEF/DEX.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,20 +13,22 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_H_ -#define LIEF_DEX_H_ +#ifndef LIEF_DEX_H +#define LIEF_DEX_H +// IWYU pragma: begin_exports #include "LIEF/config.h" #if defined(LIEF_DEX_SUPPORT) -#include "LIEF/DEX/Parser.hpp" -#include "LIEF/DEX/utils.hpp" -#include "LIEF/DEX/File.hpp" -#include "LIEF/DEX/Class.hpp" -#include "LIEF/DEX/Prototype.hpp" -#include "LIEF/DEX/Header.hpp" -#include "LIEF/DEX/Method.hpp" -#include "LIEF/DEX/Field.hpp" -#include "LIEF/DEX/EnumToString.hpp" + #include "LIEF/DEX/Class.hpp" + #include "LIEF/DEX/EnumToString.hpp" + #include "LIEF/DEX/Field.hpp" + #include "LIEF/DEX/File.hpp" + #include "LIEF/DEX/Header.hpp" + #include "LIEF/DEX/Method.hpp" + #include "LIEF/DEX/Parser.hpp" + #include "LIEF/DEX/Prototype.hpp" + #include "LIEF/DEX/utils.hpp" +// IWYU pragma: end_exports #endif #endif diff --git a/vendor/lief/include/LIEF/DEX/Class.hpp b/vendor/lief/include/LIEF/DEX/Class.hpp index 36c7342..601b573 100644 --- a/vendor/lief/include/LIEF/DEX/Class.hpp +++ b/vendor/lief/include/LIEF/DEX/Class.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,25 +13,27 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_CLASS_H_ -#define LIEF_DEX_CLASS_H_ +#ifndef LIEF_DEX_CLASS_H +#define LIEF_DEX_CLASS_H +#include #include +#include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" #include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" -#include "LIEF/DEX/enums.hpp" #include "LIEF/DEX/deopt.hpp" +#include "LIEF/DEX/enums.hpp" + -namespace LIEF { -namespace DEX { +namespace LIEF::DEX { class Parser; class Field; class Method; -//! Class which represents a DEX Class (i.e. a Java/Kotlin class) +/// Class which represents a DEX Class (i.e. a Java/Kotlin class) class LIEF_API Class : public Object { friend class Parser; @@ -55,7 +57,8 @@ class LIEF_API Class : public Object { public: static std::string package_normalized(const std::string& pkg_name); static std::string fullname_normalized(const std::string& pkg_cls); - static std::string fullname_normalized(const std::string& pkg, const std::string& cls_name); + static std::string fullname_normalized(const std::string& pkg, + const std::string& cls_name); Class(); Class(const Class&) = delete; @@ -64,60 +67,58 @@ class LIEF_API Class : public Object { Class(std::string fullname, uint32_t access_flags = ACCESS_FLAGS::ACC_UNKNOWN, Class* parent = nullptr, std::string source_filename = ""); - //! Mangled class name (e.g. ``Lcom/example/android/MyActivity;``) - const std::string& fullname() const; + /// Mangled class name (e.g. ``Lcom/example/android/MyActivity;``) + std::string_view fullname() const; - //! Package Name + /// Package Name std::string package_name() const; - //! Class name + /// Class name std::string name() const; - //! Demangled class name + /// Demangled class name std::string pretty_name() const; - //! Check if the class has the given access flag + /// Check if the class has the given access flag bool has(ACCESS_FLAGS f) const; - //! Access flags used by this class + /// Access flags used by this class access_flags_list_t access_flags() const; - //! Filename associated with this class (if any) - const std::string& source_filename() const; + /// Filename associated with this class (if any) + std::string_view source_filename() const; - //! True if the current class extends another one + /// True if the current class extends another one bool has_parent() const; - //! Parent class + /// Parent class const Class* parent() const; Class* parent(); - //! Methods implemented in this class + /// Methods implemented in this class it_const_methods methods() const; it_methods methods(); - //! Return Methods having the given name + /// Return Methods having the given name it_named_methods methods(const std::string& name); it_const_named_methods methods(const std::string& name) const; - //! Fields implemented in this class + /// Fields implemented in this class it_const_fields fields() const; it_fields fields(); - //! Return Fields having the given name + /// Return Fields having the given name it_named_fields fields(const std::string& name); it_const_named_fields fields(const std::string& name) const; - //! De-optimize information + /// De-optimize information dex2dex_class_info_t dex2dex_info() const; - //! Original index in the DEX class pool + /// Original index in the DEX class pool size_t index() const; void accept(Visitor& visitor) const override; - bool operator==(const Class& rhs) const; - bool operator!=(const Class& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Class& cls); @@ -125,15 +126,15 @@ class LIEF_API Class : public Object { private: std::string fullname_; - uint32_t access_flags_ = ACCESS_FLAGS::ACC_UNKNOWN; - Class* parent_ = nullptr; - methods_t methods_; - fields_t fields_; + uint32_t access_flags_ = ACCESS_FLAGS::ACC_UNKNOWN; + Class* parent_ = nullptr; + methods_t methods_; + fields_t fields_; std::string source_filename_; uint32_t original_index_ = UINT_MAX; }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/CodeInfo.hpp b/vendor/lief/include/LIEF/DEX/CodeInfo.hpp index 17e6749..ffb4c66 100644 --- a/vendor/lief/include/LIEF/DEX/CodeInfo.hpp +++ b/vendor/lief/include/LIEF/DEX/CodeInfo.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,19 +13,22 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_CODE_INFO_H_ -#define LIEF_DEX_CODE_INFO_H_ -#include "LIEF/visibility.h" +#ifndef LIEF_DEX_CODE_INFO_H +#define LIEF_DEX_CODE_INFO_H + +#include +#include + #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" -namespace LIEF { -namespace DEX { +namespace LIEF::DEX { namespace details { struct code_item; } + class Parser; -class Method; class LIEF_API CodeInfo : public Object { friend class Parser; @@ -39,20 +42,19 @@ class LIEF_API CodeInfo : public Object { void accept(Visitor& visitor) const override; - bool operator==(const CodeInfo& rhs) const; - bool operator!=(const CodeInfo& rhs) const; + uint16_t nb_registers() const; - virtual ~CodeInfo(); + ~CodeInfo() override; - LIEF_API friend std::ostream& operator<<(std::ostream& os, const CodeInfo& cinfo); + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const CodeInfo& cinfo); private: uint16_t nb_registers_ = 0; uint16_t args_input_sizes_ = 0; uint16_t output_sizes_ = 0; - }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/EnumToString.hpp b/vendor/lief/include/LIEF/DEX/EnumToString.hpp index 146bcf6..a464013 100644 --- a/vendor/lief/include/LIEF/DEX/EnumToString.hpp +++ b/vendor/lief/include/LIEF/DEX/EnumToString.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,23 +13,22 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_ENUM_TO_STRING_H_ -#define LIEF_DEX_ENUM_TO_STRING_H_ -#include "LIEF/visibility.h" -#include "LIEF/DEX/enums.hpp" +#ifndef LIEF_DEX_ENUM_TO_STRING_H +#define LIEF_DEX_ENUM_TO_STRING_H #include "LIEF/DEX/MapItem.hpp" #include "LIEF/DEX/Type.hpp" +#include "LIEF/DEX/enums.hpp" +#include "LIEF/visibility.h" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { LIEF_API const char* to_string(MapItem::TYPES e); LIEF_API const char* to_string(ACCESS_FLAGS e); LIEF_API const char* to_string(Type::TYPES e); LIEF_API const char* to_string(Type::PRIMITIVES e); -} // namespace DEX -} // namespace LIEF +} -#endif +#endif diff --git a/vendor/lief/include/LIEF/DEX/Field.hpp b/vendor/lief/include/LIEF/DEX/Field.hpp index 21aaf6c..0d84b90 100644 --- a/vendor/lief/include/LIEF/DEX/Field.hpp +++ b/vendor/lief/include/LIEF/DEX/Field.hpp @@ -1,4 +1,4 @@ -/* Copyright 2021 - 2022 R. Thomas +/* Copyright 2021 - 2026 R. Thomas * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -12,26 +12,29 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_FIELD_H_ -#define LIEF_DEX_FIELD_H_ +#ifndef LIEF_DEX_FIELD_H +#define LIEF_DEX_FIELD_H +#include #include +#include #include "LIEF/DEX/enums.hpp" -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" #include "LIEF/DEX/Type.hpp" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Class; -//! Class which represent a DEX Field +/// Class which represents a DEX Field class LIEF_API Field : public Object { friend class Parser; + public: using access_flags_list_t = std::vector; @@ -42,41 +45,39 @@ class LIEF_API Field : public Object { Field(const Field&); Field& operator=(const Field&); - //! Name of the Field - const std::string& name() const; + /// Name of the Field + std::string_view name() const; - //! True if a class is associated with this field - //! (which should be the case) + /// True if a class is associated with this field + /// (which should be the case) bool has_class() const; - //! Class associated with this Field - const Class* cls() const; - Class* cls(); + /// Class associated with this Field + const Class* cls() const LIEF_LIFETIMEBOUND; + Class* cls() LIEF_LIFETIMEBOUND; - //! Index in the DEX Fields pool + /// Index in the DEX Fields pool size_t index() const; - //! True if this field is a static one. + /// True if this field is a static one. bool is_static() const; - //! Field's prototype - const Type* type() const; - Type* type(); + /// Field's prototype + const Type* type() const LIEF_LIFETIMEBOUND; + Type* type() LIEF_LIFETIMEBOUND; void accept(Visitor& visitor) const override; - //! Check if the field has the given ACCESS_FLAGS + /// Check if the field has the given ACCESS_FLAGS bool has(ACCESS_FLAGS f) const; - //! ACCESS_FLAGS as a list + /// ACCESS_FLAGS as a list access_flags_list_t access_flags() const; - bool operator==(const Field& rhs) const; - bool operator!=(const Field& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Field& mtd); - virtual ~Field(); + ~Field() override; private: void set_static(bool v); @@ -91,5 +92,5 @@ class LIEF_API Field : public Object { }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/File.hpp b/vendor/lief/include/LIEF/DEX/File.hpp index fd0b75b..ffc3d7d 100644 --- a/vendor/lief/include/LIEF/DEX/File.hpp +++ b/vendor/lief/include/LIEF/DEX/File.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,27 +13,30 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_FILE_H_ -#define LIEF_DEX_FILE_H_ +#ifndef LIEF_DEX_FILE_H +#define LIEF_DEX_FILE_H +#include #include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" #include "LIEF/DEX/Header.hpp" #include "LIEF/DEX/MapList.hpp" -#include "LIEF/DEX/instructions.hpp" #include "LIEF/DEX/deopt.hpp" +#include "LIEF/DEX/instructions.hpp" +#include "LIEF/DEX/types.hpp" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Class; class Method; class Type; class Prototype; +class Field; -//! Class that represents a DEX file +/// Class that represents a DEX file class LIEF_API File : public Object { friend class Parser; @@ -47,98 +50,98 @@ class LIEF_API File : public Object { using it_methods = ref_iterator; using it_const_methods = const_ref_iterator; - using strings_t = std::vector>; - using it_strings = ref_iterator; - using it_const_strings = const_ref_iterator; + using strings_t = std::vector>; + using it_strings = ref_iterator; + using it_const_strings = + const_ref_iterator; - using types_t = std::vector>; - using it_types = ref_iterator; - using it_const_types = const_ref_iterator; + using types_t = std::vector>; + using it_types = ref_iterator; + using it_const_types = const_ref_iterator; - using prototypes_t = std::vector>; - using it_prototypes = ref_iterator; - using it_const_prototypes = const_ref_iterator; + using prototypes_t = std::vector>; + using it_prototypes = ref_iterator; + using it_const_prototypes = + const_ref_iterator; - using fields_t = std::vector>; - using it_fields = ref_iterator; - using it_const_fields = const_ref_iterator; + using fields_t = std::vector>; + using it_fields = ref_iterator; + using it_const_fields = const_ref_iterator; public: File& operator=(const File& copy) = delete; - File(const File& copy) = delete; + File(const File& copy) = delete; - //! Version of the current DEX file + /// Version of the current DEX file dex_version_t version() const; - //! Name of this file - const std::string& name() const; + /// Name of this file + std::string_view name() const; void name(const std::string& name); - //! Location of this file - const std::string& location() const; + /// Location of this file + std::string_view location() const; void location(const std::string& location); - //! DEX header - const Header& header() const; - Header& header(); + /// DEX header + const Header& header() const LIEF_LIFETIMEBOUND; + Header& header() LIEF_LIFETIMEBOUND; - //! **All** classes used in the DEX file - it_const_classes classes() const; - it_classes classes(); + /// **All** classes used in the DEX file + it_const_classes classes() const LIEF_LIFETIMEBOUND; + it_classes classes() LIEF_LIFETIMEBOUND; - //! Check if the given class name exists + /// Check if the given class name exists bool has_class(const std::string& class_name) const; - //! Return the DEX::Class object associated with the given name - const Class* get_class(const std::string& class_name) const; + /// Return the DEX::Class object associated with the given name + const Class* get_class(const std::string& class_name) const LIEF_LIFETIMEBOUND; - Class* get_class(const std::string& class_name); + Class* get_class(const std::string& class_name) LIEF_LIFETIMEBOUND; - //! Return the DEX::Class object associated with the given index - const Class* get_class(size_t index) const; + /// Return the DEX::Class object associated with the given index + const Class* get_class(size_t index) const LIEF_LIFETIMEBOUND; - Class* get_class(size_t index); + Class* get_class(size_t index) LIEF_LIFETIMEBOUND; - //! De-optimize information + /// De-optimize information dex2dex_info_t dex2dex_info() const; - //! De-optimize information as JSON + /// De-optimize information as JSON std::string dex2dex_json_info() const; - //! Return an iterator over **all** the DEX::Method used in this DEX file - it_const_methods methods() const; - it_methods methods(); + /// Return an iterator over **all** the DEX::Method used in this DEX file + it_const_methods methods() const LIEF_LIFETIMEBOUND; + it_methods methods() LIEF_LIFETIMEBOUND; - //! Return an iterator over **all** the DEX::Field used in this DEX file - it_const_fields fields() const; - it_fields fields(); + /// Return an iterator over **all** the DEX::Field used in this DEX file + it_const_fields fields() const LIEF_LIFETIMEBOUND; + it_fields fields() LIEF_LIFETIMEBOUND; - //! String pool - it_const_strings strings() const; - it_strings strings(); + /// String pool + it_const_strings strings() const LIEF_LIFETIMEBOUND; + it_strings strings() LIEF_LIFETIMEBOUND; - //! Type pool - it_const_types types() const; - it_types types(); + /// Type pool + it_const_types types() const LIEF_LIFETIMEBOUND; + it_types types() LIEF_LIFETIMEBOUND; - //! Prototype pool - it_prototypes prototypes(); - it_const_prototypes prototypes() const; + /// Prototype pool + it_prototypes prototypes() LIEF_LIFETIMEBOUND; + it_const_prototypes prototypes() const LIEF_LIFETIMEBOUND; - //! DEX Map + /// DEX Map const MapList& map() const; MapList& map(); - //! Extract the current dex file and deoptimize it + /// Extract the current dex file and deoptimize it std::string save(const std::string& path = "", bool deoptimize = true) const; std::vector raw(bool deoptimize = true) const; void accept(Visitor& visitor) const override; - bool operator==(const File& rhs) const; - bool operator!=(const File& rhs) const; ~File() override; @@ -151,26 +154,28 @@ class LIEF_API File : public Object { static void deoptimize_nop(uint8_t* inst_ptr, uint32_t value); static void deoptimize_return(uint8_t* inst_ptr, uint32_t value); - static void deoptimize_invoke_virtual(uint8_t* inst_ptr, uint32_t value, OPCODES new_inst); - static void deoptimize_instance_field_access(uint8_t* inst_ptr, uint32_t value, OPCODES new_inst); + static void deoptimize_invoke_virtual(uint8_t* inst_ptr, uint32_t value, + OPCODES new_inst); + static void deoptimize_instance_field_access(uint8_t* inst_ptr, uint32_t value, + OPCODES new_inst); std::string name_; std::string location_; - Header header_; - classes_t classes_; - methods_t methods_; - fields_t fields_; - strings_t strings_; - types_t types_; + Header header_; + classes_t classes_; + methods_t methods_; + fields_t fields_; + strings_t strings_; + types_t types_; prototypes_t prototypes_; - MapList map_; + MapList map_; classes_list_t class_list_; std::vector original_data_; }; } -} + #endif diff --git a/vendor/lief/include/LIEF/DEX/Header.hpp b/vendor/lief/include/LIEF/DEX/Header.hpp index e70de83..c22c4b2 100644 --- a/vendor/lief/include/LIEF/DEX/Header.hpp +++ b/vendor/lief/include/LIEF/DEX/Header.hpp @@ -1,6 +1,6 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,30 +14,35 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_HEADER_H_ -#define LIEF_DEX_HEADER_H_ +#ifndef LIEF_DEX_HEADER_H +#define LIEF_DEX_HEADER_H -#include "LIEF/DEX/types.hpp" +#include +#include +#include +#include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" namespace LIEF { +class Visitor; + namespace DEX { class Parser; -//! Class which represents the DEX header. -//! This is the first structure that begins the DEX format. -//! -//! The official documentation is provided here: -//! https://source.android.com/devices/tech/dalvik/dex-format#header-item +/// Class which represents the DEX header. +/// This is the first structure that begins the DEX format. +/// +/// The official documentation is provided here: +/// https://source.android.com/devices/tech/dalvik/dex-format#header-item class LIEF_API Header : public Object { friend class Parser; public: using location_t = std::pair; - using magic_t = std::array; + using magic_t = std::array; using signature_t = std::array; Header(); @@ -47,28 +52,28 @@ class LIEF_API Header : public Object { template LIEF_LOCAL Header(const T& header); - //! The DEX magic bytes (``DEX\n`` followed by the DEX version) + /// The DEX magic bytes (``DEX\n`` followed by the DEX version) magic_t magic() const; - //! The file checksum + /// The file checksum uint32_t checksum() const; - //! SHA-1 DEX signature (which is not really used as a signature) + /// SHA-1 DEX signature (which is not really used as a signature) signature_t signature() const; - //! Size of the entire file (including the current the header) + /// Size of the entire file (including the current the header) uint32_t file_size() const; - //! Size of this header. It should be 0x70 + /// Size of this header. It should be 0x70 uint32_t header_size() const; - //! File endianess of the file + /// File endianness of the file uint32_t endian_tag() const; - //! Offset from the start of the file to the map list (see: DEX::MapList) + /// Offset from the start of the file to the map list (see: DEX::MapList) uint32_t map() const; - //! Offset and size of the string pool + /// Offset and size of the string pool location_t strings() const; location_t link() const; location_t types() const; @@ -84,47 +89,45 @@ class LIEF_API Header : public Object { void accept(Visitor& visitor) const override; - bool operator==(const Header& rhs) const; - bool operator!=(const Header& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Header& hdr); - virtual ~Header(); + ~Header() override; private: - magic_t magic_; - uint32_t checksum_; - signature_t signature_; - uint32_t file_size_; + magic_t magic_{}; + uint32_t checksum_ = 0; + signature_t signature_{}; + uint32_t file_size_ = 0; - uint32_t header_size_; - uint32_t endian_tag_; + uint32_t header_size_ = 0; + uint32_t endian_tag_ = 0; - uint32_t link_size_; - uint32_t link_off_; + uint32_t link_size_ = 0; + uint32_t link_off_ = 0; - uint32_t map_off_; + uint32_t map_off_ = 0; - uint32_t string_ids_size_; - uint32_t string_ids_off_; + uint32_t string_ids_size_ = 0; + uint32_t string_ids_off_ = 0; - uint32_t type_ids_size_; - uint32_t type_ids_off_; + uint32_t type_ids_size_ = 0; + uint32_t type_ids_off_ = 0; - uint32_t proto_ids_size_; - uint32_t proto_ids_off_; + uint32_t proto_ids_size_ = 0; + uint32_t proto_ids_off_ = 0; - uint32_t field_ids_size_; - uint32_t field_ids_off_; + uint32_t field_ids_size_ = 0; + uint32_t field_ids_off_ = 0; - uint32_t method_ids_size_; - uint32_t method_ids_off_; + uint32_t method_ids_size_ = 0; + uint32_t method_ids_off_ = 0; - uint32_t class_defs_size_; - uint32_t class_defs_off_; + uint32_t class_defs_size_ = 0; + uint32_t class_defs_off_ = 0; - uint32_t data_size_; - uint32_t data_off_; + uint32_t data_size_ = 0; + uint32_t data_off_ = 0; }; } // Namespace DEX diff --git a/vendor/lief/include/LIEF/DEX/MapItem.hpp b/vendor/lief/include/LIEF/DEX/MapItem.hpp index 1b6a6ab..15f5f56 100644 --- a/vendor/lief/include/LIEF/DEX/MapItem.hpp +++ b/vendor/lief/include/LIEF/DEX/MapItem.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,43 +13,46 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_MAP_ITEM_H_ -#define LIEF_MAP_ITEM_H_ +#ifndef LIEF_MAP_ITEM_H +#define LIEF_MAP_ITEM_H + +#include +#include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Class; -//! Class which represents an element of the MapList object +/// Class which represents an element of the MapList object class LIEF_API MapItem : public Object { friend class Parser; public: enum class TYPES : uint16_t { - HEADER = 0x0000, - STRING_ID = 0x0001, - TYPE_ID = 0x0002, - PROTO_ID = 0x0003, - FIELD_ID = 0x0004, - METHOD_ID = 0x0005, - CLASS_DEF = 0x0006, - CALL_SITE_ID = 0x0007, - METHOD_HANDLE = 0x0008, - MAP_LIST = 0x1000, - TYPE_LIST = 0x1001, + HEADER = 0x0000, + STRING_ID = 0x0001, + TYPE_ID = 0x0002, + PROTO_ID = 0x0003, + FIELD_ID = 0x0004, + METHOD_ID = 0x0005, + CLASS_DEF = 0x0006, + CALL_SITE_ID = 0x0007, + METHOD_HANDLE = 0x0008, + MAP_LIST = 0x1000, + TYPE_LIST = 0x1001, ANNOTATION_SET_REF_LIST = 0x1002, - ANNOTATION_SET = 0x1003, - CLASS_DATA = 0x2000, - CODE = 0x2001, - STRING_DATA = 0x2002, - DEBUG_INFO = 0x2003, - ANNOTATION = 0x2004, - ENCODED_ARRAY = 0x2005, - ANNOTATIONS_DIRECTORY = 0x2006, + ANNOTATION_SET = 0x1003, + CLASS_DATA = 0x2000, + CODE = 0x2001, + STRING_DATA = 0x2002, + DEBUG_INFO = 0x2003, + ANNOTATION = 0x2004, + ENCODED_ARRAY = 0x2005, + ANNOTATIONS_DIRECTORY = 0x2006, }; @@ -60,36 +63,33 @@ class LIEF_API MapItem : public Object { MapItem(const MapItem&); MapItem& operator=(const MapItem&); - //! The type of the item + /// The type of the item TYPES type() const; - //! Reserved value (likely for alignment prupose) + /// Reserved value (likely for alignment purpose) uint16_t reserved() const; - //! The number of elements (the real meaning depends on the type) + /// The number of elements (the real meaning depends on the type) uint32_t size() const; - //! Offset from the start of the DEX file to the items associated with - //! the underlying TYPES + /// Offset from the start of the DEX file to the items associated with + /// the underlying TYPES uint32_t offset() const; void accept(Visitor& visitor) const override; - bool operator==(const MapItem& rhs) const; - bool operator!=(const MapItem& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const MapItem& item); - virtual ~MapItem(); + ~MapItem() override; private: - TYPES type_; - uint16_t reserved_; - uint32_t size_; - uint32_t offset_; - + TYPES type_ = TYPES::HEADER; + uint16_t reserved_ = 0; + uint32_t size_ = 0; + uint32_t offset_ = 0; }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/MapList.hpp b/vendor/lief/include/LIEF/DEX/MapList.hpp index 7679dc4..587a8bd 100644 --- a/vendor/lief/include/LIEF/DEX/MapList.hpp +++ b/vendor/lief/include/LIEF/DEX/MapList.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,34 +13,34 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_MAP_LIST_H_ -#define LIEF_MAP_LIST_H_ +#ifndef LIEF_MAP_LIST_H +#define LIEF_MAP_LIST_H #include #include -#include "LIEF/visibility.h" -#include "LIEF/iterators.hpp" #include "LIEF/Object.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" #include "LIEF/DEX/MapItem.hpp" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Class; -//! Class which represents the ``map_list`` structure that -//! follows the main DEX header. -//! -//! This MapList aims at referencing the location of other DEX structures as -//! described in https://source.android.com/devices/tech/dalvik/dex-format#map-item +/// Class which represents the ``map_list`` structure that +/// follows the main DEX header. +/// +/// This MapList aims at referencing the location of other DEX structures as +/// described in https://source.android.com/devices/tech/dalvik/dex-format#map-item class LIEF_API MapList : public Object { friend class Parser; public: - using items_t = std::map; - using it_items_t = ref_iterator>; - using it_const_items_t = const_ref_iterator>; + using items_t = std::map; + using it_items_t = ref_iterator>; + using it_const_items_t = const_ref_iterator>; public: MapList(); @@ -48,29 +48,27 @@ class LIEF_API MapList : public Object { MapList(const MapList&); MapList& operator=(const MapList&); - //! Iterator over LIEF::DEX::MapItem + /// Iterator over LIEF::DEX::MapItem it_items_t items(); it_const_items_t items() const; - //! Check if the given type exists + /// Check if the given type exists bool has(MapItem::TYPES type) const; - //! Return the LIEF::DEX::MapItem associated with the given type - const MapItem& get(MapItem::TYPES type) const; + /// Return the LIEF::DEX::MapItem associated with the given type + const MapItem& get(MapItem::TYPES type) const LIEF_LIFETIMEBOUND; - //! Return the LIEF::DEX::MapItem associated with the given type - MapItem& get(MapItem::TYPES type); + /// Return the LIEF::DEX::MapItem associated with the given type + MapItem& get(MapItem::TYPES type) LIEF_LIFETIMEBOUND; - //! Return the LIEF::DEX::MapItem associated with the given type + /// Return the LIEF::DEX::MapItem associated with the given type const MapItem& operator[](MapItem::TYPES type) const; - //! Return the LIEF::DEX::MapItem associated with the given type + /// Return the LIEF::DEX::MapItem associated with the given type MapItem& operator[](MapItem::TYPES type); void accept(Visitor& visitor) const override; - bool operator==(const MapList& rhs) const; - bool operator!=(const MapList& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const MapList& mtd); @@ -78,9 +76,8 @@ class LIEF_API MapList : public Object { private: items_t items_; - }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/Method.hpp b/vendor/lief/include/LIEF/DEX/Method.hpp index 060db30..2ae3e2e 100644 --- a/vendor/lief/include/LIEF/DEX/Method.hpp +++ b/vendor/lief/include/LIEF/DEX/Method.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,27 +13,30 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_METHOD_H_ -#define LIEF_DEX_METHOD_H_ +#ifndef LIEF_DEX_METHOD_H +#define LIEF_DEX_METHOD_H +#include #include +#include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" -#include "LIEF/DEX/enums.hpp" #include "LIEF/DEX/CodeInfo.hpp" #include "LIEF/DEX/deopt.hpp" +#include "LIEF/DEX/enums.hpp" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Class; class Prototype; -//! Class which represents a DEX::Method +/// Class which represents a DEX::Method class LIEF_API Method : public Object { friend class Parser; + public: using access_flags_list_t = std::vector; @@ -45,31 +48,31 @@ class LIEF_API Method : public Object { Method(const Method&); Method& operator=(const Method&); - //! Name of the Method - const std::string& name() const; + /// Name of the Method + std::string_view name() const; - //! True if a class is associated with this method + /// True if a class is associated with this method bool has_class() const; - //! DEX::Class associated with this Method or a nullptr - //! if not resolved + /// DEX::Class associated with this Method or a nullptr + /// if not resolved const Class* cls() const; Class* cls(); - //! Offset to the Dalvik Bytecode + /// Offset to the Dalvik Bytecode uint64_t code_offset() const; - //! Dalvik Bytecode as bytes + /// Dalvik Bytecode as bytes const bytecode_t& bytecode() const; - //! Index in the DEX Methods pool + /// Index in the DEX Methods pool size_t index() const; - //! True if this method is a virtual one. - //! i.e. not **static**, **private**, **finale** or constructor + /// True if this method is a virtual one. + /// i.e. not **static**, **private**, **final** or constructor bool is_virtual() const; - //! Method's prototype or a nullptr if it is not resolved + /// Method's prototype or a nullptr if it is not resolved const Prototype* prototype() const; Prototype* prototype(); @@ -79,18 +82,18 @@ class LIEF_API Method : public Object { const dex2dex_method_info_t& dex2dex_info() const; - //! Check if the current method has the given ACCESS_FLAGS + /// Check if the current method has the given ACCESS_FLAGS bool has(ACCESS_FLAGS f) const; - //! ACCESS_FLAGS as an std::set + /// ACCESS_FLAGS as an std::set access_flags_list_t access_flags() const; - bool operator==(const Method& rhs) const; - bool operator!=(const Method& rhs) const; + // CodeInfo to get additional data about a method i.e. argument count + const CodeInfo& code_info() const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Method& mtd); - virtual ~Method(); + ~Method() override; private: void set_virtual(bool v); @@ -109,9 +112,8 @@ class LIEF_API Method : public Object { CodeInfo code_info_; dex2dex_method_info_t dex2dex_info_; - }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/Parser.hpp b/vendor/lief/include/LIEF/DEX/Parser.hpp index 9139019..c619116 100644 --- a/vendor/lief/include/LIEF/DEX/Parser.hpp +++ b/vendor/lief/include/LIEF/DEX/Parser.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,43 +13,55 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_PARSER_H_ -#define LIEF_DEX_PARSER_H_ +#ifndef LIEF_DEX_PARSER_H +#define LIEF_DEX_PARSER_H +#include +#include #include +#include +#include +#include "LIEF/DEX/types.hpp" +#include "LIEF/path.hpp" #include "LIEF/visibility.h" -#include "LIEF/BinaryStream/VectorStream.hpp" - -#include "LIEF/DEX/File.hpp" - -struct Profiler; - namespace LIEF { +class VectorStream; + namespace DEX { class Class; class Method; class Field; +class File; +class Type; -//! Class which parses a DEX file to produce a DEX::File object +/// Class which parses a DEX file to produce a DEX::File object class LIEF_API Parser { public: - friend struct ::Profiler; - //! Parse the DEX file from the file path given in parameter - static std::unique_ptr parse(const std::string& file); - static std::unique_ptr parse(std::vector data, const std::string& name = ""); + /// Parse the DEX file from the file path given in parameter + static std::unique_ptr parse(std::string_view file); + + /// Same as parse(std::string_view) but the file is given as a + /// `std::filesystem::path` + template = 0> + static std::unique_ptr parse(const PathT& file) { + return parse(file.string()); + } + + static std::unique_ptr parse(std::vector data, + std::string_view name = ""); Parser& operator=(const Parser& copy) = delete; - Parser(const Parser& copy) = delete; + Parser(const Parser& copy) = delete; private: Parser(); - Parser(const std::string& file); + Parser(std::string_view file); Parser(std::vector data); ~Parser(); - void init(const std::string& name, dex_version_t version); + void init(std::string_view name, dex_version_t version); template void parse_file(); @@ -117,9 +129,6 @@ class LIEF_API Parser { std::unique_ptr stream_; }; - - - -} // namespace DEX -} // namespace LIEF +} +} #endif diff --git a/vendor/lief/include/LIEF/DEX/Prototype.hpp b/vendor/lief/include/LIEF/DEX/Prototype.hpp index ea9bbfc..bd3c66b 100644 --- a/vendor/lief/include/LIEF/DEX/Prototype.hpp +++ b/vendor/lief/include/LIEF/DEX/Prototype.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,54 +13,52 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_PROTOTYPE_H_ -#define LIEF_DEX_PROTOTYPE_H_ +#ifndef LIEF_DEX_PROTOTYPE_H +#define LIEF_DEX_PROTOTYPE_H -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" #include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { class Parser; class Type; -//! Class which represents a DEX method prototype +/// Class which represents a DEX method prototype class LIEF_API Prototype : public Object { friend class Parser; public: using parameters_type_t = std::vector; - using it_params = ref_iterator; - using it_const_params = const_ref_iterator; + using it_params = ref_iterator; + using it_const_params = const_ref_iterator; public: Prototype(); Prototype(const Prototype& other); - //! Type returned or a nullptr if not resolved - const Type* return_type() const; - Type* return_type(); + /// Type returned or a nullptr if not resolved + const Type* return_type() const LIEF_LIFETIMEBOUND; + Type* return_type() LIEF_LIFETIMEBOUND; - //! Types of the parameters + /// Types of the parameters it_const_params parameters_type() const; it_params parameters_type(); void accept(Visitor& visitor) const override; - bool operator==(const Prototype& rhs) const; - bool operator!=(const Prototype& rhs) const; - LIEF_API friend std::ostream& operator<<(std::ostream& os, const Prototype& type); + LIEF_API friend std::ostream& operator<<(std::ostream& os, + const Prototype& type); - virtual ~Prototype(); + ~Prototype() override; private: Type* return_type_ = nullptr; parameters_type_t params_; - }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/Type.hpp b/vendor/lief/include/LIEF/DEX/Type.hpp index 6667bef..95b273b 100644 --- a/vendor/lief/include/LIEF/DEX/Type.hpp +++ b/vendor/lief/include/LIEF/DEX/Type.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,39 +13,45 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_TYPE_H_ -#define LIEF_DEX_TYPE_H_ +#ifndef LIEF_DEX_TYPE_H +#define LIEF_DEX_TYPE_H + +#include +#include +#include -#include "LIEF/visibility.h" #include "LIEF/Object.hpp" +#include "LIEF/visibility.h" + -namespace LIEF { -namespace DEX { +namespace LIEF::DEX { class Parser; +class Class; -//! Class which represents a DEX type as described in the -//! format specifications: https://source.android.com/devices/tech/dalvik/dex-format#typedescriptor +/// Class which represents a DEX type as described in the +/// format specifications: +/// https://source.android.com/devices/tech/dalvik/dex-format#typedescriptor class LIEF_API Type : public Object { friend class Parser; public: enum class TYPES { - UNKNOWN = 0, + UNKNOWN = 0, PRIMITIVE = 1, - CLASS = 2, - ARRAY = 3, + CLASS = 2, + ARRAY = 3, }; enum class PRIMITIVES { - VOID_T = 0x01, + VOID_T = 0x01, BOOLEAN = 0x02, - BYTE = 0x03, - SHORT = 0x04, - CHAR = 0x05, - INT = 0x06, - LONG = 0x07, - FLOAT = 0x08, - DOUBLE = 0x09, + BYTE = 0x03, + SHORT = 0x04, + CHAR = 0x05, + INT = 0x06, + LONG = 0x07, + FLOAT = 0x08, + DOUBLE = 0x09, }; using array_t = std::vector; @@ -58,41 +64,39 @@ class LIEF_API Type : public Object { Type(const std::string& mangled); Type(const Type& other); - //! Whether it is a primitive type, a class, ... + /// Whether it is a primitive type, a class, ... TYPES type() const; const Class& cls() const; const array_t& array() const; const PRIMITIVES& primitive() const; - //! **IF** the current type is a TYPES::CLASS, return the - //! associated DEX::CLASS. Otherwise the returned value is **undefined**. + /// **IF** the current type is a TYPES::CLASS, return the + /// associated DEX::CLASS. Otherwise, the returned value is **undefined**. Class& cls(); - //! **IF** the current type is a TYPES::ARRAY, return the - //! associated array. Otherwise the returned value is **undefined**. + /// **IF** the current type is a TYPES::ARRAY, return the + /// associated array. Otherwise, the returned value is **undefined**. array_t& array(); - //! **IF** the current type is a TYPES::PRIMITIVE, return the - //! associated PRIMITIVES. Otherwise the returned value is **undefined**. + /// **IF** the current type is a TYPES::PRIMITIVE, return the + /// associated PRIMITIVES. Otherwise, the returned value is **undefined**. PRIMITIVES& primitive(); - //! Return the array dimension if the current type is - //! an array. Otherwise it returns 0 + /// Return the array dimension if the current type is + /// an array. Otherwise, it returns 0 size_t dim() const; - //! In the case of a TYPES::ARRAY, return the array's type - const Type& underlying_array_type() const; - Type& underlying_array_type(); + /// In the case of a TYPES::ARRAY, return the array's type + const Type& underlying_array_type() const LIEF_LIFETIMEBOUND; + Type& underlying_array_type() LIEF_LIFETIMEBOUND; void accept(Visitor& visitor) const override; - bool operator==(const Type& rhs) const; - bool operator!=(const Type& rhs) const; LIEF_API friend std::ostream& operator<<(std::ostream& os, const Type& type); - virtual ~Type(); + ~Type() override; private: void parse(const std::string& type); @@ -106,5 +110,5 @@ class LIEF_API Type : public Object { }; } // Namespace DEX -} // Namespace LIEF +// Namespace LIEF #endif diff --git a/vendor/lief/include/LIEF/DEX/deopt.hpp b/vendor/lief/include/LIEF/DEX/deopt.hpp index 442ddec..be3c33d 100644 --- a/vendor/lief/include/LIEF/DEX/deopt.hpp +++ b/vendor/lief/include/LIEF/DEX/deopt.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,22 +13,22 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_DEOPT_TYPES_H_ -#define LIEF_DEX_DEOPT_TYPES_H_ -#include +#ifndef LIEF_DEX_DEOPT_TYPES_H +#define LIEF_DEX_DEOPT_TYPES_H #include +#include + -namespace LIEF { -namespace DEX { +namespace LIEF::DEX { class Class; class Method; // Method Index: {dex_pc: index, ...} using dex2dex_method_info_t = std::unordered_map; -using dex2dex_class_info_t = std::unordered_map; -using dex2dex_info_t = std::unordered_map; +using dex2dex_class_info_t = std::unordered_map; +using dex2dex_info_t = std::unordered_map; } -} + #endif diff --git a/vendor/lief/include/LIEF/DEX/enums.hpp b/vendor/lief/include/LIEF/DEX/enums.hpp index 23fb69f..0be9e25 100644 --- a/vendor/lief/include/LIEF/DEX/enums.hpp +++ b/vendor/lief/include/LIEF/DEX/enums.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,70 +13,60 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_ENUMS_H_ -#define LIEF_DEX_ENUMS_H_ +#ifndef LIEF_DEX_ENUMS_H +#define LIEF_DEX_ENUMS_H -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { enum ACCESS_FLAGS { - ACC_UNKNOWN = 0x0, - ACC_PUBLIC = 0x1, - ACC_PRIVATE = 0x2, - ACC_PROTECTED = 0x4, - ACC_STATIC = 0x8, - ACC_FINAL = 0x10, - ACC_SYNCHRONIZED = 0x20, - ACC_VOLATILE = 0x40, - ACC_BRIDGE = 0x40, - ACC_TRANSIENT = 0x80, - ACC_VARARGS = 0x80, - ACC_NATIVE = 0x100, - ACC_INTERFACE = 0x200, - ACC_ABSTRACT = 0x400, - ACC_STRICT = 0x800, - ACC_SYNTHETIC = 0x1000, - ACC_ANNOTATION = 0x2000, - ACC_ENUM = 0x4000, - ACC_CONSTRUCTOR = 0x10000, - ACC_DECLARED_SYNCHRONIZED = 0x20000 + ACC_UNKNOWN = 0x0, + ACC_PUBLIC = 0x1, + ACC_PRIVATE = 0x2, + ACC_PROTECTED = 0x4, + ACC_STATIC = 0x8, + ACC_FINAL = 0x10, + ACC_SYNCHRONIZED = 0x20, + ACC_VOLATILE = 0x40, + ACC_BRIDGE = 0x40, + ACC_TRANSIENT = 0x80, + ACC_VARARGS = 0x80, + ACC_NATIVE = 0x100, + ACC_INTERFACE = 0x200, + ACC_ABSTRACT = 0x400, + ACC_STRICT = 0x800, + ACC_SYNTHETIC = 0x1000, + ACC_ANNOTATION = 0x2000, + ACC_ENUM = 0x4000, + ACC_CONSTRUCTOR = 0x10000, + ACC_DECLARED_SYNCHRONIZED = 0x20000, }; enum METHOD_TYPES { - METHOD_UNKNOWN = 0x00, - METHOD_VIRTUAL = 0x01, - METHOD_DIRECT = 0x02, // Deprecated + METHOD_UNKNOWN = 0x00, + METHOD_VIRTUAL = 0x01, + METHOD_DIRECT = 0x02, // Deprecated - METHOD_EXTERN = 0x03, - METHOD_CTOR = 0x04, - METHOD_STATIC = 0x05, - METHOD_STATIC_CTOR = 0x06, + METHOD_EXTERN = 0x03, + METHOD_CTOR = 0x04, + METHOD_STATIC = 0x05, + METHOD_STATIC_CTOR = 0x06, }; static const ACCESS_FLAGS access_flags_list[] = { - ACCESS_FLAGS::ACC_UNKNOWN, - ACCESS_FLAGS::ACC_PUBLIC, - ACCESS_FLAGS::ACC_PRIVATE, - ACCESS_FLAGS::ACC_PROTECTED, - ACCESS_FLAGS::ACC_STATIC, - ACCESS_FLAGS::ACC_FINAL, - ACCESS_FLAGS::ACC_SYNCHRONIZED, - ACCESS_FLAGS::ACC_VOLATILE, - ACCESS_FLAGS::ACC_BRIDGE, - ACCESS_FLAGS::ACC_TRANSIENT, - ACCESS_FLAGS::ACC_VARARGS, - ACCESS_FLAGS::ACC_NATIVE, - ACCESS_FLAGS::ACC_INTERFACE, - ACCESS_FLAGS::ACC_ABSTRACT, - ACCESS_FLAGS::ACC_STRICT, - ACCESS_FLAGS::ACC_SYNTHETIC, - ACCESS_FLAGS::ACC_ANNOTATION, - ACCESS_FLAGS::ACC_ENUM, - ACCESS_FLAGS::ACC_CONSTRUCTOR, - ACCESS_FLAGS::ACC_DECLARED_SYNCHRONIZED, + ACCESS_FLAGS::ACC_UNKNOWN, ACCESS_FLAGS::ACC_PUBLIC, + ACCESS_FLAGS::ACC_PRIVATE, ACCESS_FLAGS::ACC_PROTECTED, + ACCESS_FLAGS::ACC_STATIC, ACCESS_FLAGS::ACC_FINAL, + ACCESS_FLAGS::ACC_SYNCHRONIZED, ACCESS_FLAGS::ACC_VOLATILE, + ACCESS_FLAGS::ACC_BRIDGE, ACCESS_FLAGS::ACC_TRANSIENT, + ACCESS_FLAGS::ACC_VARARGS, ACCESS_FLAGS::ACC_NATIVE, + ACCESS_FLAGS::ACC_INTERFACE, ACCESS_FLAGS::ACC_ABSTRACT, + ACCESS_FLAGS::ACC_STRICT, ACCESS_FLAGS::ACC_SYNTHETIC, + ACCESS_FLAGS::ACC_ANNOTATION, ACCESS_FLAGS::ACC_ENUM, + ACCESS_FLAGS::ACC_CONSTRUCTOR, ACCESS_FLAGS::ACC_DECLARED_SYNCHRONIZED, }; } -} + #endif diff --git a/vendor/lief/include/LIEF/DEX/hash.hpp b/vendor/lief/include/LIEF/DEX/hash.hpp index 5dd8b8a..31aad5b 100644 --- a/vendor/lief/include/LIEF/DEX/hash.hpp +++ b/vendor/lief/include/LIEF/DEX/hash.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,37 +13,49 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_HASH_H_ -#define LIEF_DEX_HASH_H_ +#ifndef LIEF_DEX_HASH_H +#define LIEF_DEX_HASH_H -#include "LIEF/visibility.h" #include "LIEF/hash.hpp" -#include "LIEF/DEX.hpp" +#include "LIEF/visibility.h" namespace LIEF { +class Object; + namespace DEX { -//! Class which implements a visitor to compute -//! a **deterministic** hash for LIEF DEX objects +class Class; +class Field; +class File; +class Header; +class MapItem; +class MapList; +class Method; +class Prototype; +class CodeInfo; +class Type; + +/// Class which implements a visitor to compute +/// a **deterministic** hash for LIEF DEX objects class LIEF_API Hash : public LIEF::Hash { public: - static size_t hash(const Object& obj); + static LIEF::Hash::value_type hash(const Object& obj); public: using LIEF::Hash::Hash; using LIEF::Hash::visit; public: - void visit(const File& file) override; - void visit(const Header& header) override; - void visit(const Class& cls) override; - void visit(const Field& field) override; - void visit(const Method& method) override; + void visit(const File& file) override; + void visit(const Header& header) override; + void visit(const Class& cls) override; + void visit(const Field& field) override; + void visit(const Method& method) override; void visit(const CodeInfo& code_info) override; - void visit(const Type& type) override; - void visit(const Prototype& type) override; - void visit(const MapItem& item) override; - void visit(const MapList& list) override; + void visit(const Type& type) override; + void visit(const Prototype& type) override; + void visit(const MapItem& item) override; + void visit(const MapList& list) override; ~Hash() override; }; diff --git a/vendor/lief/include/LIEF/DEX/instructions.hpp b/vendor/lief/include/LIEF/DEX/instructions.hpp index 37423e5..ee36b2f 100644 --- a/vendor/lief/include/LIEF/DEX/instructions.hpp +++ b/vendor/lief/include/LIEF/DEX/instructions.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,270 +13,270 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_INSTRUCTIONS_H_ -#define LIEF_DEX_INSTRUCTIONS_H_ +#ifndef LIEF_DEX_INSTRUCTIONS_H +#define LIEF_DEX_INSTRUCTIONS_H #include "LIEF/visibility.h" -#include "LIEF/types.hpp" #include +#include -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { enum SWITCH_ARRAY_IDENT : uint16_t { IDENT_PACKED_SWITCH = 0x0100, IDENT_SPARSE_SWITCH = 0x0200, - IDENT_FILL_ARRAY = 0x0300, + IDENT_FILL_ARRAY = 0x0300, }; -//! The Dalvik Opcodes +/// The Dalvik Opcodes enum OPCODES : uint8_t { - OP_NOP = 0x00, - OP_MOVE = 0x01, - OP_MOVE_FROM_16 = 0x02, - OP_MOVE_16 = 0x03, - OP_MOVE_WIDE = 0x04, - OP_MOVE_WIDE_FROM_16 = 0x05, - OP_MOVE_WIDE_16 = 0x06, - OP_MOVE_OBJECT = 0x07, - OP_MOVE_OBJECT_FROM_16 = 0x08, - OP_MOVE_OBJECT_16 = 0x09, - OP_MOVE_RESULT = 0x0a, - OP_MOVE_RESULT_WIDE = 0x0b, - OP_MOVE_RESULT_OBJECT = 0x0c, - OP_MOVE_EXCEPTION = 0x0d, - OP_RETURN_VOID = 0x0e, - OP_RETURN = 0x0f, - OP_RETURN_WIDE = 0x10, - OP_RETURN_OBJECT = 0x11, - OP_CONST_4 = 0x12, - OP_CONST_16 = 0x13, - OP_CONST = 0x14, - OP_CONST_HIGH_16 = 0x15, - OP_CONST_WIDE_16 = 0x16, - OP_CONST_WIDE_32 = 0x17, - OP_CONST_WIDE = 0x18, - OP_CONST_WIDE_HIGH_16 = 0x19, - OP_CONST_STRING = 0x1a, - OP_CONST_STRING_JUMBO = 0x1b, - OP_CONST_CLASS = 0x1c, - OP_MONITOR_ENTER = 0x1d, - OP_MONITOR_EXIT = 0x1e, - OP_CHECK_CAST = 0x1f, - OP_INSTANCE_OF = 0x20, - OP_ARRAY_LENGTH = 0x21, - OP_NEW_INSTANCE = 0x22, - OP_NEW_ARRAY = 0x23, - OP_FILLED_NEW_ARRAY = 0x24, + OP_NOP = 0x00, + OP_MOVE = 0x01, + OP_MOVE_FROM_16 = 0x02, + OP_MOVE_16 = 0x03, + OP_MOVE_WIDE = 0x04, + OP_MOVE_WIDE_FROM_16 = 0x05, + OP_MOVE_WIDE_16 = 0x06, + OP_MOVE_OBJECT = 0x07, + OP_MOVE_OBJECT_FROM_16 = 0x08, + OP_MOVE_OBJECT_16 = 0x09, + OP_MOVE_RESULT = 0x0a, + OP_MOVE_RESULT_WIDE = 0x0b, + OP_MOVE_RESULT_OBJECT = 0x0c, + OP_MOVE_EXCEPTION = 0x0d, + OP_RETURN_VOID = 0x0e, + OP_RETURN = 0x0f, + OP_RETURN_WIDE = 0x10, + OP_RETURN_OBJECT = 0x11, + OP_CONST_4 = 0x12, + OP_CONST_16 = 0x13, + OP_CONST = 0x14, + OP_CONST_HIGH_16 = 0x15, + OP_CONST_WIDE_16 = 0x16, + OP_CONST_WIDE_32 = 0x17, + OP_CONST_WIDE = 0x18, + OP_CONST_WIDE_HIGH_16 = 0x19, + OP_CONST_STRING = 0x1a, + OP_CONST_STRING_JUMBO = 0x1b, + OP_CONST_CLASS = 0x1c, + OP_MONITOR_ENTER = 0x1d, + OP_MONITOR_EXIT = 0x1e, + OP_CHECK_CAST = 0x1f, + OP_INSTANCE_OF = 0x20, + OP_ARRAY_LENGTH = 0x21, + OP_NEW_INSTANCE = 0x22, + OP_NEW_ARRAY = 0x23, + OP_FILLED_NEW_ARRAY = 0x24, OP_FILLED_NEW_ARRAY_RANGE = 0x25, - OP_FILL_ARRAY_DATA = 0x26, - OP_THROW = 0x27, - OP_GOTO = 0x28, - OP_GOTO_16 = 0x29, - OP_GOTO_32 = 0x2a, - OP_PACKED_SWITCH = 0x2b, - OP_SPARSE_SWITCH = 0x2c, - OP_CMPL_FLOAT = 0x2d, - OP_CMPG_FLOAT = 0x2e, - OP_CMPL_DOUBLE = 0x2f, - OP_CMPG_DOUBLE = 0x30, - OP_CMP_LONG = 0x31, - OP_IF_EQ = 0x32, - OP_IF_NE = 0x33, - OP_IF_LT = 0x34, - OP_IF_GE = 0x35, - OP_IF_GT = 0x36, - OP_IF_LE = 0x37, - OP_IF_EQZ = 0x38, - OP_IF_NEZ = 0x39, - OP_IF_LTZ = 0x3a, - OP_IF_GEZ = 0x3b, - OP_IF_GTZ = 0x3c, - OP_IF_LEZ = 0x3d, - OP_AGET = 0x44, - OP_AGET_WIDE = 0x45, - OP_AGET_OBJECT = 0x46, - OP_AGET_BOOLEAN = 0x47, - OP_AGET_BYTE = 0x48, - OP_AGET_CHAR = 0x49, - OP_AGET_SHORT = 0x4a, - OP_APUT = 0x4b, - OP_APUT_WIDE = 0x4c, - OP_APUT_OBJECT = 0x4d, - OP_APUT_BOOLEAN = 0x4e, - OP_APUT_BYTE = 0x4f, - OP_APUT_CHAR = 0x50, - OP_APUT_SHORT = 0x51, - OP_IGET = 0x52, - OP_IGET_WIDE = 0x53, - OP_IGET_OBJECT = 0x54, - OP_IGET_BOOLEAN = 0x55, - OP_IGET_BYTE = 0x56, - OP_IGET_CHAR = 0x57, - OP_IGET_SHORT = 0x58, - OP_IPUT = 0x59, - OP_IPUT_WIDE = 0x5a, - OP_IPUT_OBJECT = 0x5b, - OP_IPUT_BOOLEAN = 0x5c, - OP_IPUT_BYTE = 0x5d, - OP_IPUT_CHAR = 0x5e, - OP_IPUT_SHORT = 0x5f, - OP_SGET = 0x60, - OP_SGET_WIDE = 0x61, - OP_SGET_OBJECT = 0x62, - OP_SGET_BOOLEAN = 0x63, - OP_SGET_BYTE = 0x64, - OP_SGET_CHAR = 0x65, - OP_SGET_SHORT = 0x66, - OP_SPUT = 0x67, - OP_SPUT_WIDE = 0x68, - OP_SPUT_OBJECT = 0x69, - OP_SPUT_BOOLEAN = 0x6a, - OP_SPUT_BYTE = 0x6b, - OP_SPUT_CHAR = 0x6c, - OP_SPUT_SHORT = 0x6d, - OP_INVOKE_VIRTUAL = 0x6e, - OP_INVOKE_SUPER = 0x6f, - OP_INVOKE_DIRECT = 0x70, - OP_INVOKE_STATIC = 0x71, - OP_INVOKE_INTERFACE = 0x72, + OP_FILL_ARRAY_DATA = 0x26, + OP_THROW = 0x27, + OP_GOTO = 0x28, + OP_GOTO_16 = 0x29, + OP_GOTO_32 = 0x2a, + OP_PACKED_SWITCH = 0x2b, + OP_SPARSE_SWITCH = 0x2c, + OP_CMPL_FLOAT = 0x2d, + OP_CMPG_FLOAT = 0x2e, + OP_CMPL_DOUBLE = 0x2f, + OP_CMPG_DOUBLE = 0x30, + OP_CMP_LONG = 0x31, + OP_IF_EQ = 0x32, + OP_IF_NE = 0x33, + OP_IF_LT = 0x34, + OP_IF_GE = 0x35, + OP_IF_GT = 0x36, + OP_IF_LE = 0x37, + OP_IF_EQZ = 0x38, + OP_IF_NEZ = 0x39, + OP_IF_LTZ = 0x3a, + OP_IF_GEZ = 0x3b, + OP_IF_GTZ = 0x3c, + OP_IF_LEZ = 0x3d, + OP_AGET = 0x44, + OP_AGET_WIDE = 0x45, + OP_AGET_OBJECT = 0x46, + OP_AGET_BOOLEAN = 0x47, + OP_AGET_BYTE = 0x48, + OP_AGET_CHAR = 0x49, + OP_AGET_SHORT = 0x4a, + OP_APUT = 0x4b, + OP_APUT_WIDE = 0x4c, + OP_APUT_OBJECT = 0x4d, + OP_APUT_BOOLEAN = 0x4e, + OP_APUT_BYTE = 0x4f, + OP_APUT_CHAR = 0x50, + OP_APUT_SHORT = 0x51, + OP_IGET = 0x52, + OP_IGET_WIDE = 0x53, + OP_IGET_OBJECT = 0x54, + OP_IGET_BOOLEAN = 0x55, + OP_IGET_BYTE = 0x56, + OP_IGET_CHAR = 0x57, + OP_IGET_SHORT = 0x58, + OP_IPUT = 0x59, + OP_IPUT_WIDE = 0x5a, + OP_IPUT_OBJECT = 0x5b, + OP_IPUT_BOOLEAN = 0x5c, + OP_IPUT_BYTE = 0x5d, + OP_IPUT_CHAR = 0x5e, + OP_IPUT_SHORT = 0x5f, + OP_SGET = 0x60, + OP_SGET_WIDE = 0x61, + OP_SGET_OBJECT = 0x62, + OP_SGET_BOOLEAN = 0x63, + OP_SGET_BYTE = 0x64, + OP_SGET_CHAR = 0x65, + OP_SGET_SHORT = 0x66, + OP_SPUT = 0x67, + OP_SPUT_WIDE = 0x68, + OP_SPUT_OBJECT = 0x69, + OP_SPUT_BOOLEAN = 0x6a, + OP_SPUT_BYTE = 0x6b, + OP_SPUT_CHAR = 0x6c, + OP_SPUT_SHORT = 0x6d, + OP_INVOKE_VIRTUAL = 0x6e, + OP_INVOKE_SUPER = 0x6f, + OP_INVOKE_DIRECT = 0x70, + OP_INVOKE_STATIC = 0x71, + OP_INVOKE_INTERFACE = 0x72, OP_RETURN_VOID_NO_BARRIER = 0x73, - OP_INVOKE_VIRTUAL_RANGE = 0x74, - OP_INVOKE_SUPER_RANGE = 0x75, - OP_INVOKE_DIRECT_RANGE = 0x76, - OP_INVOKE_STATIC_RANGE = 0x77, + OP_INVOKE_VIRTUAL_RANGE = 0x74, + OP_INVOKE_SUPER_RANGE = 0x75, + OP_INVOKE_DIRECT_RANGE = 0x76, + OP_INVOKE_STATIC_RANGE = 0x77, OP_INVOKE_INTERFACE_RANGE = 0x78, - OP_NEG_INT = 0x7b, - OP_NOT_INT = 0x7c, - OP_NEG_LONG = 0x7d, - OP_NOT_LONG = 0x7e, - OP_NEG_FLOAT = 0x7f, - OP_NEG_DOUBLE = 0x80, - OP_INT_TO_LONG = 0x81, - OP_INT_TO_FLOAT = 0x82, - OP_INT_TO_DOUBLE = 0x83, - OP_LONG_TO_INT = 0x84, - OP_LONG_TO_FLOAT = 0x85, - OP_LONG_TO_DOUBLE = 0x86, - OP_FLOAT_TO_INT = 0x87, - OP_FLOAT_TO_LONG = 0x88, - OP_FLOAT_TO_DOUBLE = 0x89, - OP_DOUBLE_TO_INT = 0x8a, - OP_DOUBLE_TO_LONG = 0x8b, - OP_DOUBLE_TO_FLOAT = 0x8c, - OP_INT_TO_BYTE = 0x8d, - OP_INT_TO_CHAR = 0x8e, - OP_INT_TO_SHORT = 0x8f, - OP_ADD_INT = 0x90, - OP_SUB_INT = 0x91, - OP_MUL_INT = 0x92, - OP_DIV_INT = 0x93, - OP_REM_INT = 0x94, - OP_AND_INT = 0x95, - OP_OR_INT = 0x96, - OP_XOR_INT = 0x97, - OP_SHL_INT = 0x98, - OP_SHR_INT = 0x99, - OP_USHR_INT = 0x9a, - OP_ADD_LONG = 0x9b, - OP_SUB_LONG = 0x9c, - OP_MUL_LONG = 0x9d, - OP_DIV_LONG = 0x9e, - OP_REM_LONG = 0x9f, - OP_AND_LONG = 0xa0, - OP_OR_LONG = 0xa1, - OP_XOR_LONG = 0xa2, - OP_SHL_LONG = 0xa3, - OP_SHR_LONG = 0xa4, - OP_USHR_LONG = 0xa5, - OP_ADD_FLOAT = 0xa6, - OP_SUB_FLOAT = 0xa7, - OP_MUL_FLOAT = 0xa8, - OP_DIV_FLOAT = 0xa9, - OP_REM_FLOAT = 0xaa, - OP_ADD_DOUBLE = 0xab, - OP_SUB_DOUBLE = 0xac, - OP_MUL_DOUBLE = 0xad, - OP_DIV_DOUBLE = 0xae, - OP_REM_DOUBLE = 0xaf, - OP_ADD_INT_2_ADDR = 0xb0, - OP_SUB_INT_2_ADDR = 0xb1, - OP_MUL_INT_2_ADDR = 0xb2, - OP_DIV_INT_2_ADDR = 0xb3, - OP_REM_INT_2_ADDR = 0xb4, - OP_AND_INT_2_ADDR = 0xb5, - OP_OR_INT_2_ADDR = 0xb6, - OP_XOR_INT_2_ADDR = 0xb7, - OP_SHL_INT_2_ADDR = 0xb8, - OP_SHR_INT_2_ADDR = 0xb9, - OP_USHR_INT_2_ADDR = 0xba, - OP_ADD_LONG_2_ADDR = 0xbb, - OP_SUB_LONG_2_ADDR = 0xbc, - OP_MUL_LONG_2_ADDR = 0xbd, - OP_DIV_LONG_2_ADDR = 0xbe, - OP_REM_LONG_2_ADDR = 0xbf, - OP_AND_LONG_2_ADDR = 0xc0, - OP_OR_LONG_2_ADDR = 0xc1, - OP_XOR_LONG_2_ADDR = 0xc2, - OP_SHL_LONG_2_ADDR = 0xc3, - OP_SHR_LONG_2_ADDR = 0xc4, - OP_USHR_LONG_2_ADDR = 0xc5, - OP_ADD_FLOAT_2_ADDR = 0xc6, - OP_SUB_FLOAT_2_ADDR = 0xc7, - OP_MUL_FLOAT_2_ADDR = 0xc8, - OP_DIV_FLOAT_2_ADDR = 0xc9, - OP_REM_FLOAT_2_ADDR = 0xca, - OP_ADD_DOUBLE_2_ADDR = 0xcb, - OP_SUB_DOUBLE_2_ADDR = 0xcc, - OP_MUL_DOUBLE_2_ADDR = 0xcd, - OP_DIV_DOUBLE_2_ADDR = 0xce, - OP_REM_DOUBLE_2_ADDR = 0xcf, - OP_ADD_INT_LIT_16 = 0xd0, - OP_RSUB_INT = 0xd1, - OP_MUL_INT_LIT_16 = 0xd2, - OP_DIV_INT_LIT_16 = 0xd3, - OP_REM_INT_LIT_16 = 0xd4, - OP_AND_INT_LIT_16 = 0xd5, - OP_OR_INT_LIT_16 = 0xd6, - OP_XOR_INT_LIT_16 = 0xd7, - OP_ADD_INT_LIT_8 = 0xd8, - OP_RSUB_INT_LIT_8 = 0xd9, - OP_MUL_INT_LIT_8 = 0xda, - OP_DIV_INT_LIT_8 = 0xdb, - OP_REM_INT_LIT_8 = 0xdc, - OP_AND_INT_LIT_8 = 0xdd, - OP_OR_INT_LIT_8 = 0xde, - OP_XOR_INT_LIT_8 = 0xdf, - OP_SHL_INT_LIT_8 = 0xe0, - OP_SHR_INT_LIT_8 = 0xe1, - OP_USHR_INT_LIT_8 = 0xe2, + OP_NEG_INT = 0x7b, + OP_NOT_INT = 0x7c, + OP_NEG_LONG = 0x7d, + OP_NOT_LONG = 0x7e, + OP_NEG_FLOAT = 0x7f, + OP_NEG_DOUBLE = 0x80, + OP_INT_TO_LONG = 0x81, + OP_INT_TO_FLOAT = 0x82, + OP_INT_TO_DOUBLE = 0x83, + OP_LONG_TO_INT = 0x84, + OP_LONG_TO_FLOAT = 0x85, + OP_LONG_TO_DOUBLE = 0x86, + OP_FLOAT_TO_INT = 0x87, + OP_FLOAT_TO_LONG = 0x88, + OP_FLOAT_TO_DOUBLE = 0x89, + OP_DOUBLE_TO_INT = 0x8a, + OP_DOUBLE_TO_LONG = 0x8b, + OP_DOUBLE_TO_FLOAT = 0x8c, + OP_INT_TO_BYTE = 0x8d, + OP_INT_TO_CHAR = 0x8e, + OP_INT_TO_SHORT = 0x8f, + OP_ADD_INT = 0x90, + OP_SUB_INT = 0x91, + OP_MUL_INT = 0x92, + OP_DIV_INT = 0x93, + OP_REM_INT = 0x94, + OP_AND_INT = 0x95, + OP_OR_INT = 0x96, + OP_XOR_INT = 0x97, + OP_SHL_INT = 0x98, + OP_SHR_INT = 0x99, + OP_USHR_INT = 0x9a, + OP_ADD_LONG = 0x9b, + OP_SUB_LONG = 0x9c, + OP_MUL_LONG = 0x9d, + OP_DIV_LONG = 0x9e, + OP_REM_LONG = 0x9f, + OP_AND_LONG = 0xa0, + OP_OR_LONG = 0xa1, + OP_XOR_LONG = 0xa2, + OP_SHL_LONG = 0xa3, + OP_SHR_LONG = 0xa4, + OP_USHR_LONG = 0xa5, + OP_ADD_FLOAT = 0xa6, + OP_SUB_FLOAT = 0xa7, + OP_MUL_FLOAT = 0xa8, + OP_DIV_FLOAT = 0xa9, + OP_REM_FLOAT = 0xaa, + OP_ADD_DOUBLE = 0xab, + OP_SUB_DOUBLE = 0xac, + OP_MUL_DOUBLE = 0xad, + OP_DIV_DOUBLE = 0xae, + OP_REM_DOUBLE = 0xaf, + OP_ADD_INT_2_ADDR = 0xb0, + OP_SUB_INT_2_ADDR = 0xb1, + OP_MUL_INT_2_ADDR = 0xb2, + OP_DIV_INT_2_ADDR = 0xb3, + OP_REM_INT_2_ADDR = 0xb4, + OP_AND_INT_2_ADDR = 0xb5, + OP_OR_INT_2_ADDR = 0xb6, + OP_XOR_INT_2_ADDR = 0xb7, + OP_SHL_INT_2_ADDR = 0xb8, + OP_SHR_INT_2_ADDR = 0xb9, + OP_USHR_INT_2_ADDR = 0xba, + OP_ADD_LONG_2_ADDR = 0xbb, + OP_SUB_LONG_2_ADDR = 0xbc, + OP_MUL_LONG_2_ADDR = 0xbd, + OP_DIV_LONG_2_ADDR = 0xbe, + OP_REM_LONG_2_ADDR = 0xbf, + OP_AND_LONG_2_ADDR = 0xc0, + OP_OR_LONG_2_ADDR = 0xc1, + OP_XOR_LONG_2_ADDR = 0xc2, + OP_SHL_LONG_2_ADDR = 0xc3, + OP_SHR_LONG_2_ADDR = 0xc4, + OP_USHR_LONG_2_ADDR = 0xc5, + OP_ADD_FLOAT_2_ADDR = 0xc6, + OP_SUB_FLOAT_2_ADDR = 0xc7, + OP_MUL_FLOAT_2_ADDR = 0xc8, + OP_DIV_FLOAT_2_ADDR = 0xc9, + OP_REM_FLOAT_2_ADDR = 0xca, + OP_ADD_DOUBLE_2_ADDR = 0xcb, + OP_SUB_DOUBLE_2_ADDR = 0xcc, + OP_MUL_DOUBLE_2_ADDR = 0xcd, + OP_DIV_DOUBLE_2_ADDR = 0xce, + OP_REM_DOUBLE_2_ADDR = 0xcf, + OP_ADD_INT_LIT_16 = 0xd0, + OP_RSUB_INT = 0xd1, + OP_MUL_INT_LIT_16 = 0xd2, + OP_DIV_INT_LIT_16 = 0xd3, + OP_REM_INT_LIT_16 = 0xd4, + OP_AND_INT_LIT_16 = 0xd5, + OP_OR_INT_LIT_16 = 0xd6, + OP_XOR_INT_LIT_16 = 0xd7, + OP_ADD_INT_LIT_8 = 0xd8, + OP_RSUB_INT_LIT_8 = 0xd9, + OP_MUL_INT_LIT_8 = 0xda, + OP_DIV_INT_LIT_8 = 0xdb, + OP_REM_INT_LIT_8 = 0xdc, + OP_AND_INT_LIT_8 = 0xdd, + OP_OR_INT_LIT_8 = 0xde, + OP_XOR_INT_LIT_8 = 0xdf, + OP_SHL_INT_LIT_8 = 0xe0, + OP_SHR_INT_LIT_8 = 0xe1, + OP_USHR_INT_LIT_8 = 0xe2, // ODEX - OP_IGET_QUICK = 0xe3, - OP_IGET_WIDE_QUICK = 0xe4, - OP_IGET_OBJECT_QUICK = 0xe5, - OP_IPUT_QUICK = 0xe6, - OP_IPUT_WIDE_QUICK = 0xe7, - OP_IPUT_OBJECT_QUICK = 0xe8, - OP_INVOKE_VIRTUAL_QUICK = 0xe9, - OP_INVOKE_VIRTUAL_RANGE_QUICK = 0xea, - OP_IPUT_BOOLEAN_QUICK = 0xeb, - OP_IPUT_BYTE_QUICK = 0xec, - OP_IPUT_CHAR_QUICK = 0xed, - OP_IPUT_SHORT_QUICK = 0xee, - OP_IGET_BOOLEAN_QUICK = 0xef, - OP_IGET_BYTE_QUICK = 0xf0, - OP_IGET_CHAR_QUICK = 0xf1, - OP_IGET_SHORT_QUICK = 0xf2, + OP_IGET_QUICK = 0xe3, + OP_IGET_WIDE_QUICK = 0xe4, + OP_IGET_OBJECT_QUICK = 0xe5, + OP_IPUT_QUICK = 0xe6, + OP_IPUT_WIDE_QUICK = 0xe7, + OP_IPUT_OBJECT_QUICK = 0xe8, + OP_INVOKE_VIRTUAL_QUICK = 0xe9, + OP_INVOKE_VIRTUAL_RANGE_QUICK = 0xea, + OP_IPUT_BOOLEAN_QUICK = 0xeb, + OP_IPUT_BYTE_QUICK = 0xec, + OP_IPUT_CHAR_QUICK = 0xed, + OP_IPUT_SHORT_QUICK = 0xee, + OP_IGET_BOOLEAN_QUICK = 0xef, + OP_IGET_BYTE_QUICK = 0xf0, + OP_IGET_CHAR_QUICK = 0xf1, + OP_IGET_SHORT_QUICK = 0xf2, // From DEX 38 - OP_INVOKE_POLYMORPHIC = 0xfa, + OP_INVOKE_POLYMORPHIC = 0xfa, OP_INVOKE_POLYMORPHIC_RANGE = 0xfb, - OP_INVOKE_CUSTOM = 0xfc, - OP_INVOKE_CUSTOM_RANGE = 0xfd, + OP_INVOKE_CUSTOM = 0xfc, + OP_INVOKE_CUSTOM_RANGE = 0xfd, // From DEX 39 - OP_CONST_METHOD_HANDLE = 0xfe, - OP_CONST_METHOD_TYPE = 0xff, + OP_CONST_METHOD_HANDLE = 0xfe, + OP_CONST_METHOD_TYPE = 0xff, }; enum INST_FORMATS : uint8_t { @@ -335,11 +335,11 @@ struct fill_array_data { uint16_t ident; uint16_t element_width; uint32_t size; - //uint8_t data[size]; + // uint8_t data[size]; }; -//! Return the INST_FORMATS format associated with the given opcode +/// Return the INST_FORMATS format associated with the given opcode LIEF_API INST_FORMATS inst_format_from_opcode(OPCODES op); LIEF_API size_t inst_size_from_format(INST_FORMATS fmt); @@ -349,8 +349,11 @@ LIEF_API bool is_switch_array(const uint8_t* ptr, const uint8_t* end); LIEF_API size_t switch_array_size(const uint8_t* ptr, const uint8_t* end); +inline bool valid_inst_size(const uint8_t* ptr, const uint8_t* end, size_t size) { + return size != 0 && size != SIZE_MAX && (size_t)(end - ptr) >= size; +} + } // Namespace LIEF -} // Namespace DEX +// Namespace DEX #endif - diff --git a/vendor/lief/include/LIEF/DEX/json.hpp b/vendor/lief/include/LIEF/DEX/json.hpp index 1b60df0..30ebec0 100644 --- a/vendor/lief/include/LIEF/DEX/json.hpp +++ b/vendor/lief/include/LIEF/DEX/json.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,8 +13,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_PUBLIC_JSON_H_ -#define LIEF_DEX_PUBLIC_JSON_H_ +#ifndef LIEF_DEX_PUBLIC_JSON_H +#define LIEF_DEX_PUBLIC_JSON_H #include "LIEF/visibility.h" #include diff --git a/vendor/lief/include/LIEF/DEX/types.hpp b/vendor/lief/include/LIEF/DEX/types.hpp index 9c50062..c4f35c5 100644 --- a/vendor/lief/include/LIEF/DEX/types.hpp +++ b/vendor/lief/include/LIEF/DEX/types.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,16 +13,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_TYPEDEF_H_ -#define LIEF_DEX_TYPEDEF_H_ +#ifndef LIEF_DEX_TYPEDEF_H +#define LIEF_DEX_TYPEDEF_H #include -namespace LIEF { -namespace DEX { + +namespace LIEF::DEX { using dex_version_t = uint32_t; } -} + #endif diff --git a/vendor/lief/include/LIEF/DEX/utils.hpp b/vendor/lief/include/LIEF/DEX/utils.hpp index 11135b3..ef5df81 100644 --- a/vendor/lief/include/LIEF/DEX/utils.hpp +++ b/vendor/lief/include/LIEF/DEX/utils.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,32 +13,34 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DEX_UTILS_H_ -#define LIEF_DEX_UTILS_H_ +#ifndef LIEF_DEX_UTILS_H +#define LIEF_DEX_UTILS_H -#include +#include #include #include "LIEF/DEX/types.hpp" -#include "LIEF/types.hpp" #include "LIEF/visibility.h" namespace LIEF { +class BinaryStream; namespace DEX { -//! Check if the given file is a DEX. -LIEF_API bool is_dex(const std::string& file); +/// Check if the given file is a DEX. +LIEF_API bool is_dex(std::string_view file); -//! Check if the given raw data is a DEX. +/// Check if the given raw data is a DEX. LIEF_API bool is_dex(const std::vector& raw); -//! Return the DEX version of the given file -LIEF_API dex_version_t version(const std::string& file); +/// Return the DEX version of the given file +LIEF_API dex_version_t version(std::string_view file); -//! Return the DEX version of the raw data +/// Return the DEX version of the raw data LIEF_API dex_version_t version(const std::vector& raw); +dex_version_t version(BinaryStream& stream); + } } diff --git a/vendor/lief/include/LIEF/DWARF.hpp b/vendor/lief/include/LIEF/DWARF.hpp index d4d69b5..250a3ab 100644 --- a/vendor/lief/include/LIEF/DWARF.hpp +++ b/vendor/lief/include/LIEF/DWARF.hpp @@ -1,5 +1,5 @@ -/* Copyright 2017 - 2022 R. Thomas - * Copyright 2017 - 2022 Quarkslab +/* Copyright 2017 - 2026 R. Thomas + * Copyright 2017 - 2026 Quarkslab * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,9 +13,33 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef LIEF_DWARF_H_ -#define LIEF_DWARF_H_ +#ifndef LIEF_DWARF_H +#define LIEF_DWARF_H +// IWYU pragma: begin_exports +#include "LIEF/DWARF/CompilationUnit.hpp" +#include "LIEF/DWARF/DebugInfo.hpp" +#include "LIEF/DWARF/Editor.hpp" +#include "LIEF/DWARF/Function.hpp" +#include "LIEF/DWARF/LexicalBlock.hpp" +#include "LIEF/DWARF/Parameter.hpp" +#include "LIEF/DWARF/Scope.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/Variable.hpp" #include "LIEF/DWARF/enums.hpp" +#include "LIEF/DWARF/types.hpp" + +#include "LIEF/DWARF/editor/ArrayType.hpp" +#include "LIEF/DWARF/editor/BaseType.hpp" +#include "LIEF/DWARF/editor/CompilationUnit.hpp" +#include "LIEF/DWARF/editor/EnumType.hpp" +#include "LIEF/DWARF/editor/Function.hpp" +#include "LIEF/DWARF/editor/FunctionType.hpp" +#include "LIEF/DWARF/editor/PointerType.hpp" +#include "LIEF/DWARF/editor/StructType.hpp" +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/DWARF/editor/TypeDef.hpp" +#include "LIEF/DWARF/editor/Variable.hpp" +// IWYU pragma: end_exports #endif diff --git a/vendor/lief/include/LIEF/DWARF/CompilationUnit.hpp b/vendor/lief/include/LIEF/DWARF/CompilationUnit.hpp new file mode 100644 index 0000000..e5e8e42 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/CompilationUnit.hpp @@ -0,0 +1,278 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_COMPILATION_UNIT_H +#define LIEF_DWARF_COMPILATION_UNIT_H +#include +#include +#include + +#include "LIEF/DWARF/Function.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DebugDeclOpt.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/range.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf { + +namespace details { +class CompilationUnit; +class CompilationUnitIt; +} + +/// This class represents a DWARF compilation unit +class LIEF_API CompilationUnit { + public: + class Iterator final + : public iterator_facade_base { + public: + using implementation = details::CompilationUnitIt; + using iterator_facade_base::operator++; + using iterator_facade_base::operator--; + + LIEF_API Iterator(); + + LIEF_API Iterator(std::unique_ptr impl); + + LIEF_API Iterator(const Iterator&); + LIEF_API Iterator& operator=(const Iterator&); + + LIEF_API Iterator(Iterator&&) noexcept; + LIEF_API Iterator& operator=(Iterator&&) noexcept; + + LIEF_API ~Iterator(); + + friend LIEF_API bool operator==(const Iterator& LHS, const Iterator& RHS); + friend bool operator!=(const Iterator& LHS, const Iterator& RHS) { + return !(LHS == RHS); + } + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator++(); + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator--(); + + LIEF_API const CompilationUnit& operator*() const LIEF_LIFETIMEBOUND; + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API const CompilationUnit* operator->() const LIEF_LIFETIMEBOUND; + + /// Transfer ownership of the compilation unit at the current position + /// to the caller. Returns `nullptr` if the iterator is past-the-end. + LIEF_API std::unique_ptr yield(); + + private: + void load() const; + + std::unique_ptr impl_; + mutable std::unique_ptr cached_; + }; + + /// Iterator over the dwarf::Function + using functions_it = iterator_range; + + /// Iterator over the dwarf::Type + using types_it = iterator_range; + + /// Iterator over the CompilationUnit's variables + using vars_it = iterator_range; + + /// Languages supported by the DWARF (v5) format. + /// See: https://dwarfstd.org/languages.html + /// + /// Some languages (like C++11, C++17, ..) have a version (11, 17, ...) which + /// is stored in a dedicated attribute: #version + class Language { + public: + enum LANG : uint32_t { + UNKNOWN = 0, + C, + CPP, + RUST, + DART, + MODULA, + FORTRAN, + SWIFT, + D, + JAVA, + COBOL, + }; + + /// The language itself + LANG lang = UNKNOWN; + + /// Version of the language (e.g. 17 for C++17) + uint32_t version = 0; + + Language() = default; + Language(LANG lang, uint32_t version) : + lang(lang), + version(version) {} + Language(LANG lang) : + Language(lang, 0) {} + + Language(const Language&) = default; + Language& operator=(const Language&) = default; + Language(Language&&) = default; + Language& operator=(Language&&) = default; + ~Language() = default; + }; + CompilationUnit(std::unique_ptr impl); + ~CompilationUnit(); + + /// Name of the file associated with this compilation unit (e.g. `test.cpp`) + /// Return an **empty** string if the name is not found or can't be resolved + /// + /// This value matches the `DW_AT_name` attribute + std::string name() const; + + /// Information about the program (or library) that generated this compilation + /// unit. For instance, it can output: `Debian clang version 17.0.6`. + /// + /// It returns an **empty** string if the producer is not present or can't be + /// resolved + /// + /// This value matches the `DW_AT_producer` attribute + std::string producer() const; + + /// Return the path to the directory in which the compilation took place for + /// compiling this compilation unit (e.g. `/workdir/build`) + /// + /// It returns an **empty** string if the entry is not present or can't be + /// resolved + /// + /// This value matches the `DW_AT_comp_dir` attribute + std::string compilation_dir() const; + + /// Original language of this compilation unit. + /// + /// This value matches the `DW_AT_language` attribute. + Language language() const; + + /// Return the lowest virtual address owned by this compilation unit. + uint64_t low_address() const; + + /// Return the highest virtual address owned by this compilation unit. + uint64_t high_address() const; + + /// Return the size of the compilation unit according to its range of address. + /// + /// If the compilation is fragmented (i.e. there are some address ranges + /// between the lowest address and the highest that are not owned by the CU), + /// then it returns the sum of **all** the address ranges owned by this CU. + /// + /// If the compilation unit is **not** fragmented, then it basically returns + /// `high_address - low_address`. + uint64_t size() const; + + /// Return a list of address ranges owned by this compilation unit. + /// + /// If the compilation unit owns a contiguous range, it should return + /// **a single** range. + std::vector ranges() const; + + /// Try to find the function whose name is given in parameter. + /// + /// The provided name can be demangled + std::unique_ptr + find_function(const std::string& name) const LIEF_LIFETIMEBOUND; + + /// Try to find the function at the given address + std::unique_ptr find_function(uint64_t addr) const LIEF_LIFETIMEBOUND; + + /// Try to find the Variable at the given address + std::unique_ptr find_variable(uint64_t addr) const LIEF_LIFETIMEBOUND; + + /// Try to find the Variable with the given name + std::unique_ptr + find_variable(const std::string& name) const LIEF_LIFETIMEBOUND; + + /// Return an iterator over the functions implemented in this compilation + /// unit. + /// + /// Note that this iterator only iterates over the functions that have a + /// **concrete** implementation in the compilation unit. + /// + /// For instance with this code: + /// + /// ```cpp + /// inline const char* get_secret_env() { + /// return getenv("MY_SECRET_ENV"); + /// } + /// + /// int main() { + /// printf("%s", get_secret_env()); + /// return 0; + /// } + /// ``` + /// + /// The iterator will only return **one function** for `main` since + /// `get_secret_env` is inlined and thus, its implementation is located in + /// `main`. + functions_it functions() const LIEF_LIFETIMEBOUND; + + /// Return an iterator over the functions **imported** in this compilation + /// unit **but not** implemented. + /// + /// For instance with this code: + /// + /// ```cpp + /// #include + /// int main() { + /// printf("Hello\n"); + /// return 0; + /// } + /// ``` + /// + /// `printf` is imported from the standard libc so the function is returned by + /// the iterator. On the other hand, `main()` is implemented in this + /// compilation unit so it is not returned by imported_function() but + /// functions(). + functions_it imported_functions() const LIEF_LIFETIMEBOUND; + + /// Return an iterator over the different types defined in this + /// compilation unit. + types_it types() const LIEF_LIFETIMEBOUND; + + /// Return an iterator over all the variables defined in this compilation + /// unit: + /// + /// ```cpp + /// static int A = 1; // Returned by the iterator + /// static const char* B = "Hello"; // Returned by the iterator + /// + /// int get() { + /// static int C = 2; // Returned by the iterator + /// return C; + /// } + /// ``` + vars_it variables() const LIEF_LIFETIMEBOUND; + + /// Generate a C/C++ definition for the functions defined in this + /// compilation unit. + std::string to_decl(const DeclOpt& opt = DeclOpt()) const; + + private: + std::unique_ptr impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/DebugInfo.hpp b/vendor/lief/include/LIEF/DWARF/DebugInfo.hpp new file mode 100644 index 0000000..92f5fd0 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/DebugInfo.hpp @@ -0,0 +1,101 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_INFO_H +#define LIEF_DWARF_INFO_H +#include +#include + +#include "LIEF/Abstract/DebugInfo.hpp" +#include "LIEF/DWARF/CompilationUnit.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/iterators.hpp" + +#include "LIEF/visibility.h" + + +/// Namespace for the DWARF debug format +namespace LIEF::dwarf { +class Function; +class Variable; + +/// This class represents a DWARF debug information. It can embed different +/// compilation units which can be accessed through compilation_units() . +/// +/// This class can be instantiated from LIEF::Binary::debug_info() or load() +class LIEF_API DebugInfo : public LIEF::DebugInfo { + public: + using LIEF::DebugInfo::DebugInfo; + + static std::unique_ptr from_file(const std::string& path); + + /// Iterator over the CompilationUnit + using compilation_units_it = iterator_range; + + /// Try to find the function with the given name (mangled or not) + /// + /// ```cpp + /// const DebugInfo& info = ...; + /// if (auto func = info.find_function("_ZNSt6localeD1Ev")) { + /// // Found + /// } + /// if (auto func = info.find_function("std::locale::~locale()")) { + /// // Found + /// } + /// ``` + std::unique_ptr + find_function(const std::string& name) const LIEF_LIFETIMEBOUND; + + /// Try to find the function at the given **virtual** address + std::unique_ptr find_function(uint64_t addr) const LIEF_LIFETIMEBOUND; + + /// Try to find the variable with the given name. This name can be mangled or + /// not. + std::unique_ptr + find_variable(const std::string& name) const LIEF_LIFETIMEBOUND; + + /// Try to find the variable at the given **virtual** address + std::unique_ptr find_variable(uint64_t addr) const LIEF_LIFETIMEBOUND; + + /// Try to find the type with the given name + std::unique_ptr + find_type(const std::string& name) const LIEF_LIFETIMEBOUND; + + /// Iterator on the CompilationUnit embedded in this dwarf + compilation_units_it compilation_units() const LIEF_LIFETIMEBOUND; + + /// Attempt to resolve the address of the function specified by `name`. + std::optional + find_function_address(const std::string& name) const override; + + FORMAT format() const override { + return LIEF::DebugInfo::FORMAT::DWARF; + } + + static bool classof(const LIEF::DebugInfo* info) { + return info->format() == LIEF::DebugInfo::FORMAT::DWARF; + } + + ~DebugInfo() override = default; +}; + + +/// Load DWARF file from the given path +inline std::unique_ptr load(const std::string& dwarf_path) { + return DebugInfo::from_file(dwarf_path); +} + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Editor.hpp b/vendor/lief/include/LIEF/DWARF/Editor.hpp new file mode 100644 index 0000000..850dbcf --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Editor.hpp @@ -0,0 +1,77 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_H +#define LIEF_DWARF_EDITOR_H +#include +#include +#include + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + +namespace LIEF { +class Binary; +namespace dwarf { + +namespace details { +class Editor; +} + +namespace editor { +class CompilationUnit; +} + +/// This class exposes the main API to create DWARF information +class LIEF_API Editor { + public: + Editor() = delete; + Editor(std::unique_ptr impl); + + enum class FORMAT : uint32_t { + ELF, + MACHO, + PE, + }; + + enum class ARCH : uint32_t { + UNKNOWN, + X64, + X86, + AARCH64, + ARM, + }; + + /// Instantiate an editor for the given binary object + static std::unique_ptr from_binary(LIEF::Binary& bin); + + /// Instantiate an editor for the given format and arch + static std::unique_ptr create(FORMAT fmt, ARCH arch); + + /// Create a new compilation unit + std::unique_ptr + create_compilation_unit() LIEF_LIFETIMEBOUND; + + /// Write the DWARF file to the specified output + void write(const std::string& output); + + ~Editor(); + + private: + std::unique_ptr impl_; +}; + +} +} +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Function.hpp b/vendor/lief/include/LIEF/DWARF/Function.hpp new file mode 100644 index 0000000..adb1039 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Function.hpp @@ -0,0 +1,186 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_FUNCTION_H +#define LIEF_DWARF_FUNCTION_H + +#include +#include + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" + +#include "LIEF/DWARF/LexicalBlock.hpp" +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/DWARF/Variable.hpp" +#include "LIEF/asm/Instruction.hpp" +#include "LIEF/range.hpp" + + +namespace LIEF::dwarf { + +class Scope; +class Parameter; + +namespace details { +class Function; +class FunctionIt; +} + +/// This class represents a DWARF function which can be associated with either: +/// `DW_TAG_subprogram` or `DW_TAG_inlined_subroutine`. +class LIEF_API Function { + public: + class Iterator final + : public iterator_facade_base { + public: + using implementation = details::FunctionIt; + using iterator_facade_base::operator++; + using iterator_facade_base::operator--; + + LIEF_API Iterator(); + + LIEF_API Iterator(std::unique_ptr impl); + + LIEF_API Iterator(const Iterator&); + LIEF_API Iterator& operator=(const Iterator&); + + LIEF_API Iterator(Iterator&&) noexcept; + LIEF_API Iterator& operator=(Iterator&&) noexcept; + + LIEF_API ~Iterator(); + + friend LIEF_API bool operator==(const Iterator& LHS, const Iterator& RHS); + + friend bool operator!=(const Iterator& LHS, const Iterator& RHS) { + return !(LHS == RHS); + } + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator++(); + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator--(); + + LIEF_API const Function& operator*() const LIEF_LIFETIMEBOUND; + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API const Function* operator->() const LIEF_LIFETIMEBOUND; + + /// Transfer ownership of the function at the current position to the + /// caller. Returns `nullptr` if the iterator is past-the-end. + LIEF_API std::unique_ptr yield(); + + private: + void load() const; + + std::unique_ptr impl_; + mutable std::unique_ptr cached_; + }; + + /// Iterator over the variables defined in the scope of this function + using vars_it = iterator_range; + using parameters_t = std::vector>; + using thrown_types_t = std::vector>; + + using lexical_blocks_it = iterator_range; + + using instructions_it = iterator_range; + + Function(std::unique_ptr impl); + + /// The name of the function (`DW_AT_name`) + std::string name() const; + + /// The name of the function which is used for linking (`DW_AT_linkage_name`). + /// + /// This name differs from name() as it is usually mangled. The function + /// returns an empty string if the linkage name is not available. + std::string linkage_name() const; + + /// Return the address of the function (`DW_AT_entry_pc` or `DW_AT_low_pc`). + result address() const; + + /// Return an iterator of variables (`DW_TAG_variable`) defined within the + /// scope of this function. This includes regular stack-based variables as + /// well as static ones. + vars_it variables() const LIEF_LIFETIMEBOUND; + + /// Whether this function is created by the compiler and not + /// present in the original source code + bool is_artificial() const; + + /// Whether the function is defined **outside** the current compilation unit + /// (`DW_AT_external`). + bool is_external() const; + + /// Return the size taken by this function in the binary + uint64_t size() const; + + /// Ranges of virtual addresses owned by this function + std::vector ranges() const; + + /// Original source code location + debug_location_t debug_location() const; + + /// Return the dwarf::Type associated with the **return type** of this + /// function + std::unique_ptr type() const LIEF_LIFETIMEBOUND; + + /// Return the function's parameters (including any template parameter) + parameters_t parameters() const LIEF_LIFETIMEBOUND; + + /// List of exceptions (types) that can be thrown by the function. + /// + /// For instance, given this Swift code: + /// + /// ```swift + /// func summarize(_ ratings: [Int]) throws(StatisticsError) { + /// // ... + /// } + /// ``` + /// + /// thrown_types() returns one element associated with the Type: + /// `StatisticsError`. + thrown_types_t thrown_types() const LIEF_LIFETIMEBOUND; + + /// Return the scope in which this function is defined + std::unique_ptr scope() const LIEF_LIFETIMEBOUND; + + /// Disassemble the current function by returning an iterator over + /// the assembly::Instruction + instructions_it instructions() const LIEF_LIFETIMEBOUND; + + /// Iterator over the LexicalBlock owned by this function + lexical_blocks_it lexical_blocks() const LIEF_LIFETIMEBOUND; + + /// Description (`DW_AT_description`) of this function or an empty string + std::string description() const; + + /// Generates a C/C++ definition for this function + std::string to_decl(const DeclOpt& opt = DeclOpt()) const; + + ~Function(); + + private: + std::unique_ptr impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/LexicalBlock.hpp b/vendor/lief/include/LIEF/DWARF/LexicalBlock.hpp new file mode 100644 index 0000000..38c3e6a --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/LexicalBlock.hpp @@ -0,0 +1,135 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_LEXICAL_BLOCK_H +#define LIEF_DWARF_LEXICAL_BLOCK_H + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/range.hpp" +#include "LIEF/visibility.h" +#include + +#include +#include +#include + + +namespace LIEF::dwarf { + +namespace details { +class LexicalBlock; +class LexicalBlockIt; +} + +/// This class represents a DWARF lexical block (`DW_TAG_lexical_block`) +class LIEF_API LexicalBlock { + public: + class Iterator final + : public iterator_facade_base { + public: + using implementation = details::LexicalBlockIt; + using iterator_facade_base::operator++; + using iterator_facade_base::operator--; + + LIEF_API Iterator(); + + LIEF_API Iterator(std::unique_ptr impl); + + LIEF_API Iterator(const Iterator&); + LIEF_API Iterator& operator=(const Iterator&); + + LIEF_API Iterator(Iterator&&) noexcept; + LIEF_API Iterator& operator=(Iterator&&) noexcept; + + LIEF_API ~Iterator(); + + friend LIEF_API bool operator==(const Iterator& LHS, const Iterator& RHS); + friend bool operator!=(const Iterator& LHS, const Iterator& RHS) { + return !(LHS == RHS); + } + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator++(); + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator--(); + + LIEF_API const LexicalBlock& operator*() const LIEF_LIFETIMEBOUND; + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API const LexicalBlock* operator->() const LIEF_LIFETIMEBOUND; + + /// Transfer ownership of the lexical block at the current position + /// to the caller. Returns `nullptr` if the iterator is past-the-end. + LIEF_API std::unique_ptr yield(); + + private: + void load() const; + + std::unique_ptr impl_; + mutable std::unique_ptr cached_; + }; + + using sub_blocks_it = iterator_range; + + LexicalBlock(std::unique_ptr impl); + LexicalBlock() = delete; + LexicalBlock& operator=(const LexicalBlock&) = delete; + LexicalBlock(const LexicalBlock&) = delete; + + /// Return the *name* associated with this lexical block or an + /// empty string + std::string name() const; + + /// Return the description associated with this lexical block or an + /// empty string + std::string description() const; + + /// Return an iterator over the sub-LexicalBlock owned by this block. + sub_blocks_it sub_blocks() const LIEF_LIFETIMEBOUND; + + /// Return the start address of this block + std::optional addr() const; + + /// Return the size of this block as the difference of the highest address and + /// the lowest address. + uint64_t size() const; + + /// Return the lowest virtual address owned by this block. + std::optional low_pc() const; + + /// Return the highest virtual address owned by this block. + std::optional high_pc() const; + + /// Return a list of address ranges owned by this block. + /// + /// If the lexical block owns a contiguous range, it should return + /// **a single** range. + std::vector ranges() const; + + ~LexicalBlock(); + + LIEF_LOCAL static std::unique_ptr + create(std::unique_ptr impl); + + protected: + std::unique_ptr impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Parameter.hpp b/vendor/lief/include/LIEF/DWARF/Parameter.hpp new file mode 100644 index 0000000..de39c1c --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Parameter.hpp @@ -0,0 +1,190 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_PARAMETER_H +#define LIEF_DWARF_PARAMETER_H + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + +#include +#include +#include + + +namespace LIEF::dwarf { + +class Type; + +namespace details { +class Parameter; +} + +/// This class represents a DWARF parameter which can be either: +/// - A regular function parameter (see: parameters::Formal) +/// - A template type parameter (see: parameters::TemplateType) +/// - A template value parameter (see: parameters::TemplateValue) +class LIEF_API Parameter { + public: + enum class KIND { + UNKNOWN = 0, + TEMPLATE_TYPE, ///< DW_TAG_template_type_parameter + TEMPLATE_VALUE, ///< DW_TAG_template_value_parameter + FORMAL, ///< DW_TAG_formal_parameter + }; + + /// This class exposes information about the location of a parameter + class LIEF_API Location { + public: + enum class Type : uint8_t { + UNKNOWN = 0, + REG, + }; + Location(Type ty) : + type(ty) {} + + template + const T* as() const { + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + Type type = Type::UNKNOWN; + }; + + /// This class represents a register location + class LIEF_API RegisterLoc : public Location { + public: + RegisterLoc(uint64_t reg_id) : + Location(Type::REG), + id(reg_id) {} + + static bool classof(const Location* loc) { + return loc->type == Type::REG; + } + + /// DWARF id of the register + uint64_t id = 0; + }; + + Parameter() = delete; + Parameter(Parameter&& other) noexcept; + Parameter& operator=(Parameter&& other) noexcept; + Parameter& operator=(const Parameter&) = delete; + Parameter(const Parameter&) = delete; + + + KIND kind() const; + + /// Name of the parameter + std::string name() const; + + /// Type of this parameter + std::unique_ptr type() const LIEF_LIFETIMEBOUND; + + /// Location of this parameter. For instance it can be a specific register + /// that is not following the calling convention. + std::unique_ptr location() const LIEF_LIFETIMEBOUND; + + template + const T* as() const { + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + virtual ~Parameter(); + + LIEF_LOCAL static std::unique_ptr + create(std::unique_ptr impl); + + protected: + Parameter(std::unique_ptr impl); + std::unique_ptr impl_; +}; + +namespace parameters { + +/// This class represents a regular function parameter. +/// +/// For instance, given this prototype: +/// +/// ```cpp +/// int main(int argc, const char** argv); +/// ``` +/// +/// The function `main` has two parameters::Formal parameters: +/// +/// 1. `argc` (Parameter::name) typed as `int` (types::Base from Parameter::type) +/// 2. `argv` (Parameter::name) typed as `const char**` +/// (types::Const from Parameter::type) +class LIEF_API Formal : public Parameter { + public: + using Parameter::Parameter; + static bool classof(const Parameter* P) { + return P->kind() == Parameter::KIND::FORMAL; + } + + ~Formal() override = default; +}; + + +/// This class represents a template **value** parameter. +/// +/// For instance, given this prototype: +/// +/// ```cpp +/// template +/// void generic(); +/// ``` +/// +/// The function `generic` has one parameters::TemplateValue parameter: `X`. +class LIEF_API TemplateValue : public Parameter { + public: + using Parameter::Parameter; + static bool classof(const Parameter* P) { + return P->kind() == Parameter::KIND::TEMPLATE_VALUE; + } + + ~TemplateValue() override = default; +}; + +/// This class represents a template **type** parameter. +/// +/// For instance, given this prototype: +/// +/// ```cpp +/// template +/// void generic(); +/// ``` +/// +/// The function `generic` has one parameters::TemplateType parameter: `Y`. +class LIEF_API TemplateType : public Parameter { + public: + using Parameter::Parameter; + static bool classof(const Parameter* P) { + return P->kind() == Parameter::KIND::TEMPLATE_TYPE; + } + + ~TemplateType() override = default; +}; + +} + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Scope.hpp b/vendor/lief/include/LIEF/DWARF/Scope.hpp new file mode 100644 index 0000000..2e1f95f --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Scope.hpp @@ -0,0 +1,67 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_SCOPE_H +#define LIEF_DWARF_SCOPE_H + +#include +#include +#include + +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf { + +namespace details { +class Scope; +} + +/// This class materializes a scope in which Function, Variable, Type, ... +/// can be defined. +class LIEF_API Scope { + public: + enum class TYPE : uint32_t { + UNKNOWN = 0, + UNION, + CLASS, + STRUCT, + NAMESPACE, + FUNCTION, + COMPILATION_UNIT, + }; + Scope(std::unique_ptr impl); + + /// Name of the scope. For instance namespace's name or function's name. + std::string name() const; + + /// Parent scope (if any) + std::unique_ptr parent() const; + + /// The current scope type + TYPE type() const; + + /// Represent the whole chain of all (parent) scopes using the provided + /// separator. E.g. `ns1::ns2::Class1::Struct2::Type` + std::string chained(const std::string& sep = "::") const; + + ~Scope(); + + private: + std::unique_ptr impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Type.hpp b/vendor/lief/include/LIEF/DWARF/Type.hpp new file mode 100644 index 0000000..2578256 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Type.hpp @@ -0,0 +1,201 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_TYPE_H +#define LIEF_DWARF_TYPE_H + +#include + +#include "LIEF/DebugDeclOpt.hpp" +#include "LIEF/canbe_unique.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/debug_loc.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf { +class Scope; + +namespace details { +class Type; +class TypeIt; +} + +/// This class represents a DWARF Type which includes: +/// +/// - `DW_TAG_array_type` +/// - `DW_TAG_atomic_type` +/// - `DW_TAG_base_type` +/// - `DW_TAG_class_type` +/// - `DW_TAG_coarray_type` +/// - `DW_TAG_const_type` +/// - `DW_TAG_dynamic_type` +/// - `DW_TAG_enumeration_type` +/// - `DW_TAG_file_type` +/// - `DW_TAG_immutable_type` +/// - `DW_TAG_interface_type` +/// - `DW_TAG_packed_type` +/// - `DW_TAG_pointer_type` +/// - `DW_TAG_ptr_to_member_type` +/// - `DW_TAG_reference_type` +/// - `DW_TAG_restrict_type` +/// - `DW_TAG_rvalue_reference_type` +/// - `DW_TAG_set_type` +/// - `DW_TAG_shared_type` +/// - `DW_TAG_string_type` +/// - `DW_TAG_structure_type` +/// - `DW_TAG_subroutine_type` +/// - `DW_TAG_template_alias` +/// - `DW_TAG_thrown_type` +/// - `DW_TAG_typedef` +/// - `DW_TAG_union_type` +/// - `DW_TAG_unspecified_type` +/// - `DW_TAG_volatile_type` +class LIEF_API Type { + public: + class Iterator final + : public iterator_facade_base { + public: + using implementation = details::TypeIt; + using iterator_facade_base::operator++; + using iterator_facade_base::operator--; + + LIEF_API Iterator(); + + LIEF_API Iterator(std::unique_ptr impl); + + LIEF_API Iterator(const Iterator&); + LIEF_API Iterator& operator=(const Iterator&); + + LIEF_API Iterator(Iterator&&) noexcept; + LIEF_API Iterator& operator=(Iterator&&) noexcept; + + LIEF_API ~Iterator(); + + friend LIEF_API bool operator==(const Iterator& LHS, const Iterator& RHS); + friend bool operator!=(const Iterator& LHS, const Iterator& RHS) { + return !(LHS == RHS); + } + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator++(); + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator--(); + + LIEF_API const Type& operator*() const LIEF_LIFETIMEBOUND; + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API const Type* operator->() const LIEF_LIFETIMEBOUND; + + /// Transfer ownership of the type at the current position to the + /// caller. Returns `nullptr` if the iterator is past-the-end. + LIEF_API std::unique_ptr yield(); + + private: + void load() const; + + std::unique_ptr impl_; + mutable std::unique_ptr cached_; + }; + + LIEF_LOCAL Type(std::unique_ptr impl); + LIEF_LOCAL Type(details::Type& impl); + + Type(const Type&) = delete; + Type& operator=(const Type&) = delete; + + Type(Type&&) noexcept; + Type& operator=(Type&&) noexcept; + + virtual ~Type(); + + enum class KIND { + UNKNOWN = 0, + UNSPECIFIED, + BASE, + CONST_KIND, + CLASS, + ARRAY, + POINTER, + STRUCT, + UNION, + TYPEDEF, + REF, + SET_TYPE, + STRING, + SUBROUTINE, + POINTER_MEMBER, + PACKED, + FILE, + THROWN, + VOLATILE, + RESTRICT, + INTERFACE, + SHARED, + RVALREF, + TEMPLATE_ALIAS, + COARRAY, + DYNAMIC, + ATOMIC, + IMMUTABLE, + ENUM, + }; + + KIND kind() const; + + /// Whether this type is a `DW_TAG_unspecified_type` + bool is_unspecified() const { + return kind() == KIND::UNSPECIFIED; + } + + /// Return the type's name using either `DW_AT_name` or `DW_AT_picture_string` + /// (if any). + result name() const; + + /// Return the size of the type or an error if it can't be computed. + /// + /// This size should match the equivalent of `sizeof(Type)`. + result size() const; + + /// Return the debug location where this type is defined. + debug_location_t location() const; + + /// Return the scope in which this type is defined + std::unique_ptr scope() const; + + /// Generates a C/C++ definition for this type + std::string to_decl(const DeclOpt& opt = DeclOpt()) const; + + template + const T* as() const { + if (T::classof(this)) { + return static_cast(this); + } + return nullptr; + } + + static std::unique_ptr + create(std::unique_ptr impl LIEF_LIFETIMEBOUND); + + protected: + LIEF::details::canbe_unique impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/Variable.hpp b/vendor/lief/include/LIEF/DWARF/Variable.hpp new file mode 100644 index 0000000..5f682c6 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/Variable.hpp @@ -0,0 +1,144 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_VARIABLE_H +#define LIEF_DWARF_VARIABLE_H + +#include + +#include "LIEF/DWARF/Type.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/debug_loc.hpp" +#include "LIEF/errors.hpp" +#include "LIEF/iterators.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf { +class Scope; + +namespace details { +class Variable; +class VariableIt; +} + +/// This class represents a DWARF variable which can be owned by a +/// dwarf::Function or a dwarf::CompilationUnit +class LIEF_API Variable { + public: + class Iterator final + : public iterator_facade_base { + public: + using implementation = details::VariableIt; + using iterator_facade_base::operator++; + using iterator_facade_base::operator--; + + LIEF_API Iterator(); + + LIEF_API Iterator(std::unique_ptr impl); + + LIEF_API Iterator(const Iterator&); + LIEF_API Iterator& operator=(const Iterator&); + + LIEF_API Iterator(Iterator&&) noexcept; + LIEF_API Iterator& operator=(Iterator&&) noexcept; + + LIEF_API ~Iterator(); + + friend LIEF_API bool operator==(const Iterator& LHS, const Iterator& RHS); + friend bool operator!=(const Iterator& LHS, const Iterator& RHS) { + return !(LHS == RHS); + } + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator++(); + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API Iterator& operator--(); + + LIEF_API const Variable& operator*() const LIEF_LIFETIMEBOUND; + + // NOLINTNEXTLINE(bugprone-derived-method-shadowing-base-method) + LIEF_API const Variable* operator->() const LIEF_LIFETIMEBOUND; + + /// Transfer ownership of the variable at the current position to the + /// caller. Returns `nullptr` if the iterator is past-the-end. + LIEF_API std::unique_ptr yield(); + + private: + void load() const; + + std::unique_ptr impl_; + mutable std::unique_ptr cached_; + }; + + Variable(std::unique_ptr impl); + + /// Name of the variable (usually demangled) + std::string name() const; + + /// The name of the variable which is used for linking (`DW_AT_linkage_name`). + /// + /// This name differs from name() as it is usually mangled. The function + /// returns an empty string if the linkage name is not available. + std::string linkage_name() const; + + /// Address of the variable. + /// + /// If the variable is **static**, it returns the **virtual address** + /// where it is defined. + /// If the variable is stack-based, it returns the **relative offset** from + /// the frame based register. + /// + /// If the address can't be resolved, it returns a lief_errors. + result address() const; + + /// Return the size of the variable (or a lief_errors if it can't be + /// resolved). + /// + /// This size is defined by its type. + result size() const; + + /// Whether it's a `constexpr` variable + bool is_constexpr() const; + + /// Whether this variable is allocated on the stack + bool is_stack_based() const; + + /// The original source location where the variable is defined. + debug_location_t debug_location() const; + + /// Return the type of this variable + std::unique_ptr type() const LIEF_LIFETIMEBOUND; + + /// Return the scope in which this variable is defined + std::unique_ptr scope() const LIEF_LIFETIMEBOUND; + + /// Description (`DW_AT_description`) of the variable or an empty string + std::string description() const; + + /// Generates a C/C++ definition for this variable + std::string to_decl(const DeclOpt& opt = DeclOpt()) const; + + ~Variable(); + + private: + std::unique_ptr impl_; +}; + +} + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/editor/ArrayType.hpp b/vendor/lief/include/LIEF/DWARF/editor/ArrayType.hpp new file mode 100644 index 0000000..752c4da --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/editor/ArrayType.hpp @@ -0,0 +1,40 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_ARRAY_TYPE_H +#define LIEF_DWARF_EDITOR_ARRAY_TYPE_H + +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf::editor { + +/// This class represents an array type (`DW_TAG_array_type`). +class LIEF_API ArrayType : public Type { + public: + template>> + ArrayType(Args&&... args) : + Type(std::forward(args)...) {} + + static bool classof(const Type* type); + + ~ArrayType() override = default; +}; + +} + + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/editor/BaseType.hpp b/vendor/lief/include/LIEF/DWARF/editor/BaseType.hpp new file mode 100644 index 0000000..a2cbe6c --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/editor/BaseType.hpp @@ -0,0 +1,52 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_BASE_TYPE_H +#define LIEF_DWARF_EDITOR_BASE_TYPE_H + +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/visibility.h" +#include + + +namespace LIEF::dwarf::editor { + +/// This class represents a primitive type like `int, char`. +class LIEF_API BaseType : public Type { + public: + template>> + BaseType(Args&&... args) : + Type(std::forward(args)...) {} + + enum class ENCODING : uint32_t { + NONE = 0, + ADDRESS, + SIGNED, + SIGNED_CHAR, + UNSIGNED, + UNSIGNED_CHAR, + BOOLEAN, + FLOAT, + }; + + static bool classof(const Type* type); + + ~BaseType() override = default; +}; + +} + + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/editor/CompilationUnit.hpp b/vendor/lief/include/LIEF/DWARF/editor/CompilationUnit.hpp new file mode 100644 index 0000000..de0860c --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/editor/CompilationUnit.hpp @@ -0,0 +1,112 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_COMPILATION_UNIT_H +#define LIEF_DWARF_EDITOR_COMPILATION_UNIT_H +#include +#include + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + +#include "LIEF/DWARF/editor/BaseType.hpp" +#include "LIEF/DWARF/editor/FunctionType.hpp" +#include "LIEF/DWARF/editor/PointerType.hpp" +#include "LIEF/DWARF/editor/StructType.hpp" + + +namespace LIEF::dwarf::editor { +class Function; +class Variable; +class Type; +class EnumType; +class TypeDef; +class ArrayType; + +namespace details { +class CompilationUnit; +} + +/// This class represents an **editable** DWARF compilation unit +class LIEF_API CompilationUnit { + public: + CompilationUnit() = delete; + CompilationUnit(std::unique_ptr impl); + + /// Set the `DW_AT_producer` producer attribute. + /// + /// This attribute aims to inform about the program that generated this + /// compilation unit (e.g. `LIEF Extended`) + CompilationUnit& set_producer(const std::string& producer) LIEF_LIFETIMEBOUND; + + /// Create a new function owned by this compilation unit + std::unique_ptr + create_function(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Create a new **global** variable owned by this compilation unit + std::unique_ptr + create_variable(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Create a `DW_TAG_unspecified_type` type with the given name + std::unique_ptr + create_generic_type(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Create an enum type (`DW_TAG_enumeration_type`) + std::unique_ptr + create_enum(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Create a typedef with the name provided in the first parameter which aliases + /// the type provided in the second parameter + std::unique_ptr create_typedef(const std::string& name, + const Type& type) LIEF_LIFETIMEBOUND; + + /// Create a struct-like type (struct, class, union) with the given name. + std::unique_ptr create_structure( + const std::string& name, StructType::TYPE kind = StructType::TYPE::STRUCT + ) LIEF_LIFETIMEBOUND; + + /// Create a primitive type with the given name and size. + std::unique_ptr create_base_type( + const std::string& name, size_t size, + BaseType::ENCODING encoding = BaseType::ENCODING::NONE + ) LIEF_LIFETIMEBOUND; + + /// Create a function type with the given name. + std::unique_ptr + create_function_type(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Create a pointer on the provided type + std::unique_ptr + create_pointer_type(const Type& ty) LIEF_LIFETIMEBOUND { + return ty.pointer_to(); + } + + /// Create a `void` type + std::unique_ptr create_void_type() LIEF_LIFETIMEBOUND; + + /// Create an array type with the given name, type and size. + std::unique_ptr create_array(const std::string& name, + const Type& type, + size_t count) LIEF_LIFETIMEBOUND; + + ~CompilationUnit(); + + private: + std::unique_ptr impl_; +}; + +} + + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/editor/EnumType.hpp b/vendor/lief/include/LIEF/DWARF/editor/EnumType.hpp new file mode 100644 index 0000000..36b1e11 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/editor/EnumType.hpp @@ -0,0 +1,70 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_ENUM_TYPE_H +#define LIEF_DWARF_EDITOR_ENUM_TYPE_H +#include +#include + +#include "LIEF/DWARF/editor/Type.hpp" +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf::editor { + +namespace details { +class EnumValue; +} + +/// This class represents an editable enum type (`DW_TAG_enumeration_type`) +class LIEF_API EnumType : public Type { + public: + template>> + EnumType(Args&&... args) : + Type(std::forward(args)...) {} + + /// This class represents an enum value + class LIEF_API Value { + public: + Value() = delete; + Value(std::unique_ptr impl); + + ~Value(); + + private: + std::unique_ptr impl_; + }; + + /// Define the number of bytes required to hold an instance of the + /// enumeration (`DW_AT_byte_size`). + EnumType& set_size(uint64_t size) LIEF_LIFETIMEBOUND; + + /// Set the underlying type that is used to encode this enum + EnumType& set_underlying_type(const Type& type) LIEF_LIFETIMEBOUND; + + /// Add an enum value by specifying its name and its integer value + std::unique_ptr add_value(const std::string& name, + int64_t value) LIEF_LIFETIMEBOUND; + + static bool classof(const Type* type); + + ~EnumType() override = default; +}; + +} + + +#endif diff --git a/vendor/lief/include/LIEF/DWARF/editor/Function.hpp b/vendor/lief/include/LIEF/DWARF/editor/Function.hpp new file mode 100644 index 0000000..14c2ef4 --- /dev/null +++ b/vendor/lief/include/LIEF/DWARF/editor/Function.hpp @@ -0,0 +1,163 @@ +/* Copyright 2022 - 2026 R. Thomas + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef LIEF_DWARF_EDITOR_FUNCTION_H +#define LIEF_DWARF_EDITOR_FUNCTION_H +#include +#include +#include +#include + +#include "LIEF/compiler_attributes.hpp" +#include "LIEF/visibility.h" + + +namespace LIEF::dwarf::editor { +class Type; +class Variable; + +namespace details { +class Function; +class FunctionParameter; +class FunctionLexicalBlock; +class FunctionLabel; +} + +/// This class represents an **editable** DWARF function (`DW_TAG_subprogram`) +class LIEF_API Function { + public: + struct LIEF_API range_t { + range_t() = default; + range_t(uint64_t start, uint64_t end) : + start(start), + end(end) {} + uint64_t start = 0; + uint64_t end = 0; + }; + + /// This class represents a parameter of the current function + /// (`DW_TAG_formal_parameter`) + class LIEF_API Parameter { + public: + Parameter() = delete; + Parameter(std::unique_ptr impl); + + ~Parameter(); + + /// Assign this parameter to a specific named register. + Parameter& assign_register(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Assign this parameter to the given DWARF register id (e.g. `DW_OP_reg0`). + Parameter& assign_register(uint64_t reg) LIEF_LIFETIMEBOUND; + + private: + std::unique_ptr impl_; + }; + + /// This class mirrors the `DW_TAG_lexical_block` DWARF tag + class LIEF_API LexicalBlock { + public: + LexicalBlock() = delete; + LexicalBlock(std::unique_ptr impl); + + /// Create a sub-block with the given low/high addresses. + std::unique_ptr add_block(uint64_t start, + uint64_t end) LIEF_LIFETIMEBOUND; + + /// Create a sub-block with the given range of addresses. + std::unique_ptr + add_block(const std::vector& range) LIEF_LIFETIMEBOUND; + + /// Create a `DW_AT_description` entry with the description + /// provided in parameter. + LexicalBlock& + add_description(const std::string& description) LIEF_LIFETIMEBOUND; + + /// Create a `DW_AT_name` entry to associate a name to this entry + LexicalBlock& add_name(const std::string& name) LIEF_LIFETIMEBOUND; + + ~LexicalBlock(); + + private: + std::unique_ptr impl_; + }; + + /// This class mirrors the `DW_TAG_label` DWARF tag + class LIEF_API Label { + public: + Label() = delete; + Label(std::unique_ptr impl); + + ~Label(); + + private: + std::unique_ptr impl_; + }; + + Function() = delete; + Function(std::unique_ptr impl); + + /// Set the address of this function by defining `DW_AT_entry_pc` + Function& set_address(uint64_t addr) LIEF_LIFETIMEBOUND; + + /// Set the upper and lower bound addresses for this function. This assumes + /// that the function is contiguous between `low` and `high`. + /// + /// Underneath, the function defines `DW_AT_low_pc` and `DW_AT_high_pc` + Function& set_low_high(uint64_t low, uint64_t high) LIEF_LIFETIMEBOUND; + + /// Set the ranges of addresses owned by the implementation of this function + /// by setting the `DW_AT_ranges` attribute. + /// + /// This setter should be used for non-contiguous functions. + Function& set_ranges(const std::vector& ranges) LIEF_LIFETIMEBOUND; + + /// Set the function as external by defining `DW_AT_external` to true. + /// This means that the function is **imported** by the current compilation + /// unit. + Function& set_external() LIEF_LIFETIMEBOUND; + + /// Set the return type of this function + Function& set_return_type(const Type& type) LIEF_LIFETIMEBOUND; + + /// Add a parameter to the current function + std::unique_ptr add_parameter(const std::string& name, + const Type& type) LIEF_LIFETIMEBOUND; + + /// Create a stack-based variable owned by the current function + std::unique_ptr + create_stack_variable(const std::string& name) LIEF_LIFETIMEBOUND; + + /// Add a lexical block with the given range + std::unique_ptr add_lexical_block(uint64_t start, + uint64_t end) LIEF_LIFETIMEBOUND; + + /// Add a label at the given address + std::unique_ptr